ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

4649 files changed, 4 insertions, 818750 deletions

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
deleted file mode 100644
index 1072725501..0000000000
--- a/.gitlab-ci.yml
+++ /dev/null
@@ -1,154 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-image: jbettis/bionic-20200807-20sep21
-
-# You can update that image using this repo:
-#   https://gitlab.com/zephyr-ec/gitlab-ci-runner/-/tree/main
-
-# Change pip's cache directory to be inside the project directory since we can
-# only cache local items.
-variables:
-  PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"
-
-# Pip's cache doesn't store the python packages
-# https://pip.pypa.io/en/stable/reference/pip_install/#caching
-#
-# If you want to also cache the installed packages, you have to install
-# them in a virtualenv and cache it as well.
-cache:
-  paths:
-    - .cache/pip
-    - venv/
-
-
-# The directory structure is:
-#
-# /zephyr
-# /builds/zephyr-ec/ec       EC_DIR
-before_script:
-  - export MODULES_DIR="$HOME/modules"
-  - mkdir -p "${MODULES_DIR}"
-  - export ZEPHYR_BASE="$HOME/zephyr"
-  - git clone -b chromeos-v2.6 https://chromium.googlesource.com/chromiumos/third_party/zephyr "${ZEPHYR_BASE}26"
-  - git clone -b chromeos-main https://chromium.googlesource.com/chromiumos/third_party/zephyr/cmsis "${MODULES_DIR}/cmsis"
-  - git clone -b chromeos-main https://chromium.googlesource.com/chromiumos/third_party/zephyr/hal_stm32 "${MODULES_DIR}/hal_stm32"
-  - git clone -b main https://chromium.googlesource.com/chromiumos/third_party/zephyr/nanopb "${MODULES_DIR}/nanopb"
-  - git clone -b main https://chromium.googlesource.com/chromiumos/third_party/cryptoc "${MODULES_DIR}/cryptoc"
-  - ln -s "$(pwd)" "${MODULES_DIR}/ec"
-  - python3 -V  # Print out python version for debugging
-  - python3 -m pip install zephyr/zmake --user
-  - export BUILD_DIR=build
-  - export ZEPHYR_DIR=/zephyr
-  - export PATH="$PATH:$HOME/.local/bin"
-  - python3 -m pip install anytree --user
-  - python3 -m pip install pyelftools --user
-  - export PYTHONIOENCODING=utf-8
-
-# Users of this template must set:
-# $PROJECT to the project to build in zephyr/projects. E.g. "lazor")
-# $VERSION to the Zephyr version to use (e.g. 25 for 2.5, 26 for 2.6)
-# $PROJECT_SUBDIR if it is in a subdirectory. E.g. "trogdor/"
-.build_template: &build_template
-  stage: build
-  script:
-    - zmake --zephyr-base "${ZEPHYR_BASE}${VERSION}"
-      --modules-dir "${MODULES_DIR}" -l DEBUG configure -b
-      -B "${BUILD_DIR}/${PROJECT}" -t ${TOOLCHAIN:-zephyr}
-      zephyr/projects/${PROJECT_SUBDIR}${PROJECT}
-    - for b in "${BUILD_DIR}/${PROJECT}"/build-* ; do
-      bdir=$(basename ${b}) ;
-      ninja -C ${b} ram_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_ram_report.txt" ;
-      cp ${b}/ram.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_ram.json" ;
-      ninja -C ${b} rom_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_rom_report.txt" ;
-      cp ${b}/rom.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_rom.json" ;
-      done
-    - ls "${BUILD_DIR}/${PROJECT}" "${BUILD_DIR}/${PROJECT}/output"
-  artifacts:
-    paths:
-      - build/${PROJECT}/output/*
-    expire_in: 1 week
-
-delbin:
-  variables:
-    PROJECT: "delbin"
-    PROJECT_SUBDIR: "volteer/"
-    VERSION: 26
-  <<: *build_template
-
-hayato:
-  variables:
-    PROJECT: "hayato"
-    PROJECT_SUBDIR: "asurada/"
-    VERSION: 26
-  <<: *build_template
-
-herobrine_npcx9:
-  variables:
-    PROJECT: "herobrine_npcx9"
-    PROJECT_SUBDIR: "herobrine/"
-    VERSION: 26
-  <<: *build_template
-
-it8xxx2_evb:
-  variables:
-    PROJECT: "it8xxx2_evb"
-    VERSION: 26
-  <<: *build_template
-
-kohaku:
-  variables:
-    PROJECT: "kohaku"
-    VERSION: 26
-  <<: *build_template
-
-lazor:
-  variables:
-    PROJECT: "lazor"
-    PROJECT_SUBDIR: "trogdor/"
-    VERSION: 26
-  <<: *build_template
-
-native_posix:
-  variables:
-    PROJECT: "posix-ec"
-    TOOLCHAIN: "host"
-    VERSION: 26
-  <<: *build_template
-
-volteer:
-  variables:
-    PROJECT: "volteer"
-    PROJECT_SUBDIR: "volteer/"
-    VERSION: 26
-  <<: *build_template
-
-coverage:
-  stage: test
-  script:
-    - zmake --zephyr-base "${ZEPHYR_BASE}26"
-      --modules-dir "${MODULES_DIR}" -l DEBUG coverage
-      "${BUILD_DIR}/zcoverage"
-    - make -j CRYPTOC_DIR="${MODULES_DIR}/cryptoc"
-      FTDIVERSION=1 HOSTGCOV='gcov'
-      CROSS_COMPILE_arm=/opt/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-
-      coverage
-    - lcov -o build/merged.info -a build/coverage/lcov.info -a build/zcoverage/lcov.info
-    - lcov -o build/merged_no_zephyr.info -r build/merged.info '/home/uboot/zephyr26/*' '/home/uboot/modules/*' '/usr/include/x86_64-linux-gnu/*'
-    - grep "SF:" build/zcoverage/projects_herobrine_herobrine_npcx9.info | sort -u | sed -e 's|^SF:||' | xargs lcov -o build/merged_no_zephyr_herobrine_npcx9.info -e build/merged_no_zephyr.info
-    - /usr/bin/genhtml -q -o build/merged_no_zephyr_herobrine_npcx9_rpt -t "Herobrine npcx9 coverage w/o zephyr" -p /builds/zephyr-ec/ec -s build/merged_no_zephyr_herobrine_npcx9.info
-  artifacts:
-    paths:
-      - build/zcoverage/coverage_rpt/*
-      - build/coverage/coverage_rpt/*
-      - build/*.info
-      - build/*_rpt
-    expire_in: 1 week
-
-testall:
-  stage: test
-  script:
-    - zmake --zephyr-base "${ZEPHYR_BASE}26"
-      --modules-dir "${MODULES_DIR}" -l DEBUG testall
-
diff --git a/Makefile b/Makefile
index fbc59c42df..a47b64aae9 100644
--- a/Makefile
+++ b/Makefile
@@ -93,14 +93,6 @@ not_cfg = $(subst ro rw,y,$(filter-out $(1:y=ro rw),ro rw))
 # Include those now, since they must be defined for _flag_cfg below.
 include $(BDIR)/build.mk
 
-ifneq ($(ENV_VARS),)
-# Let's make sure $(out)/env_config.h changes if value any of the above
-# variables has changed since the prvious make invocation. This in turn will
-# make sure that relevant object files are re-built.
-current_set = $(foreach env_flag, $(ENV_VARS), $(env_flag)=$($(env_flag)))
-$(shell util/env_changed.sh "$(out)/env_config.h" "$(current_set)")
-endif
-
 # Baseboard directory
 ifneq (,$(BASEBOARD))
 BASEDIR:=baseboard/$(BASEBOARD)
@@ -130,7 +122,7 @@ UC_PROJECT:=$(call uppercase,$(PROJECT))
 # Transform the configuration into make variables.  This must be done after
 # the board/baseboard/project/chip/core variables are defined, since some of
 # the configs are dependent on particular configurations.
-includes=include core/$(CORE)/include include/driver $(dirs) $(out) fuzz test third_party
+includes=include core/$(CORE)/include include/driver $(dirs) $(out) third_party
 ifdef CTS_MODULE
 includes+=cts/$(CTS_MODULE) cts
 endif
@@ -261,8 +253,6 @@ include chip/$(CHIP)/build.mk
 include core/$(CORE)/build.mk
 include common/build.mk
 include driver/build.mk
-include fuzz/build.mk
-include power/build.mk
 -include private/build.mk
 -include private-kandou/build.mk
 ifneq ($(PDIR),)
@@ -271,9 +261,6 @@ endif
 ifneq ($(PBDIR),)
 include $(PBDIR)/build.mk
 endif
-include test/build.mk
-include util/build.mk
-include util/lock/build.mk
 
 includes+=$(includes-y)
 
@@ -312,37 +299,11 @@ endef
 $(eval $(call get_sources,y))
 $(eval $(call get_sources,ro))
 
-# The following variables are meant to be initialized in the baseboard or
-# board's build.mk. They will later be appended to in util/build.mk with
-# utils that should be generated for all boards.
-#
-# build-util-bin-y - Utils for the system doing the "build".
-#                    For example, the 64-bit x86 GNU/Linux running make.
-#                    These are often program that are needed by the build
-#                    system to generate code for use in firmware.
-# host-util-bin-y  - Utils for the target platform on top of the EC.
-#                    For example, the 32-bit x86 Chromebook.
-# build-util-art-y - Build ?artifacts? for the system doing the "build"
-#
-# The util targets added to these variable will pickup extra build objects
-# from their optional <util_name>-objs make variable.
-#
-# See commit bc4c1b4 for more context.
-build-utils := $(call objs_from_dir,$(out)/util,build-util-bin)
-host-utils := $(call objs_from_dir,$(out)/util,host-util-bin)
-build-art := $(call objs_from_dir,$(out),build-util-art)
-# Use the util_name with an added .c AND the special <util_name>-objs variable.
-build-srcs := $(foreach u,$(build-util-bin-y),$(sort $($(u)-objs:%.o=util/%.c) \
-                $(wildcard util/$(u).c)))
-host-srcs := $(foreach u,$(host-util-bin-y),$(sort $($(u)-objs:%.o=util/%.c) \
-               $(wildcard util/$(u).c)))
-
-dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common fuzz power test \
+dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common \
 	cts/common cts/$(CTS_MODULE) $(out)/gen
 dirs+= private private-kandou $(PDIR) $(PBDIR)
 dirs+=$(shell find common -type d)
 dirs+=$(shell find driver -type d)
-common_dirs=util
 
 ifeq ($(custom-ro_objs-y),)
 ro-common-objs := $(sort $(foreach obj, $(all-obj-y), $(out)/RO/$(obj)))
@@ -373,7 +334,7 @@ deps := $(ro-deps) $(rw-deps) $(deps-y)
 $(config): $(out)/$(PROJECT).bin
 	@printf '%s=y\n' $(_tsk_cfg) $(_flag_cfg) > $@
 
-def_all_deps:=$(config) $(PROJECT_EXTRA) notice rw size utils
+def_all_deps:=$(config) $(PROJECT_EXTRA) notice rw size
 ifeq ($(CONFIG_FW_INCLUDE_RO),y)
 def_all_deps+=ro
 endif
diff --git a/Makefile.rules b/Makefile.rules
index be7885a198..da4ecf378f 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -195,14 +195,10 @@ build_boards: | $(FAILED_BOARDS_DIR)
 	$(MAKE) try_build_boards
 
 .PHONY: buildall_only
-buildall_only: build_boards build_cros_ec_commands
-	$(MAKE) build_cts
-	$(MAKE) buildfuzztests
+buildall_only: build_boards
 
 .PHONY: buildall
 buildall: buildall_only
-	$(MAKE) runtests
-	@touch .tests-passed
 	@echo "$@ completed successfully!"
 	$(call cmd_stats,RO)
 	$(call cmd_stats,RW)
@@ -213,26 +209,11 @@ buildall: buildall_only
 		printf "%-10s: %6d\n" $$board $$size; \
 	 done
 
-.PHONY: try_build_tests
-try_build_tests: $(foreach b, $(BOARDS), tests-$(b))
-
-.PHONY: buildalltests
-buildalltests: | $(FAILED_BOARDS_DIR)
-	$(MAKE) try_build_tests
-	@echo "$@ completed successfully!"
-
 .PHONY: print-boards
 print-boards:
 	$(call cmd_pretty_print_list,\
 		$(sort $(boards)))
 
-ifeq ($(ALLOW_CONFIG),)
-cmd_check_allowed = ./util/check_allowed.sh ${config} util/config_allowed.txt .
-else
-cmd_check_allowed = true
-endif
-quiet_cmd_check_allowed = CHECK_ALLOWED ${config}
-
 # Print any important notices at the end of the build.
 .PHONY: notice
 notice: $(config)
@@ -269,157 +250,6 @@ hex-$(CONFIG_RW_B) += $(out)/RW/$(PROJECT).RW_B.hex
 hex: $(hex-y)
 .PHONY: hex
 
-.PHONY: utils-art
-utils-art: $(build-art)
-
-.PHONY: utils-host
-utils-host: $(host-utils)
-
-.PHONY: utils-build
-utils-build: $(build-utils)
-
-.PHONY: utils
-utils: utils-host utils-build utils-art
-
-# On board test binaries
-test-targets=$(foreach t,$(test-list-y),test-$(t))
-.PHONY: $(test-targets)
-
-ifeq "$(CONFIG_COMMON_RUNTIME)" "y"
-$(test-targets): test-%:
-	@set -e ; \
-	$(call echo,"  BUILD   $(out)/$*") \
-	$(MAKE) BOARD=$(BOARD) PROJECT=$* \
-	        V=$(V) out=$(out)/$* TEST_BUILD=y; \
-	cp $(out)/$*/$*.bin $(out)/test-$*.bin
-endif
-
-.PHONY: tests
-tests: $(test-targets)
-
-.PHONY: print-tests
-print-tests:
-	$(call cmd_pretty_print_list, \
-		$(sort $(test-targets)))
-
-# Emulator test executables
-host-test-targets=$(foreach t,$(test-list-host),host-$(t))
-run-test-targets=$(foreach t,$(test-list-host),run-$(t))
-.PHONY: $(host-test-targets) $(run-test-targets)
-
-$(host-test-targets): host-%: | $(FAILED_BOARDS_DIR)
-	@touch $(FAILED_BOARDS_DIR)/test-$*
-	+$(call quiet,host_test,BUILD  )
-
-$(run-test-targets): run-%: host-%
-	$(call quiet,run_host_test,TEST   )
-	@rm -f $(FAILED_BOARDS_DIR)/test-$*
-
-host-coverage-targets=$(foreach t,$(test-list-host),host-coverage-$(t))
-run-coverage-targets=$(foreach t,$(test-list-host),run-coverage-$(t))
-.PHONY: $(host-coverage-targets) $(run-coverage-targets)
-
-$(host-coverage-targets): host-coverage-%: | $(FAILED_BOARDS_DIR)
-	@touch $(FAILED_BOARDS_DIR)/test-$*
-	+$(call quiet,coverage_test,BUILD  )
-
-$(run-coverage-targets): run-coverage-%: host-coverage-%
-	$(call quiet,run_coverage_test,TEST   )
-	@rm -f $(FAILED_BOARDS_DIR)/test-$*
-
-.PHONY: print-host-tests
-print-host-tests:
-	$(call cmd_pretty_print_list, \
-		$(sort $(host-test-targets) $(run-test-targets)))
-
-# Fuzzing tests
-
-fuzz-test-targets=$(foreach t,$(fuzz-test-list-host),host-$(t))
-run-fuzz-test-targets=$(foreach t,$(fuzz-test-list-host),run-$(t))
-
-.PHONY: $(fuzz-test-targets) $(run-fuzz-test-targets)
-
-$(fuzz-test-targets): TEST_FLAG=TEST_FUZZ=y TEST_ASAN=$(TEST_ASAN) \
-	TEST_MSAN=$(TEST_MSAN) TEST_UBSAN=$(TEST_UBSAN) \
-	CROSS_COMPILE=$(shell echo $(HOSTCC) | grep -v ccache | \
-		sed -e 's/[^-]*$$//')
-$(fuzz-test-targets): host-%: | $(FAILED_BOARDS_DIR)
-	@touch $(FAILED_BOARDS_DIR)/test-$*
-	+$(call quiet,host_test,BUILD  )
-$(run-fuzz-test-targets): run-%: host-%
-	$(call quiet,run_fuzz,TEST   )
-	@rm -f $(FAILED_BOARDS_DIR)/test-$*
-
-$(FAILED_BOARDS_DIR):
-	@mkdir $(FAILED_BOARDS_DIR)
-
-.PHONY: print-host-fuzzers
-print-host-fuzzers:
-	$(call cmd_pretty_print_list, \
-		$(sort $(fuzz-test-targets) $(run-fuzz-test-targets)))
-
-.PHONY: buildfuzztests
-buildfuzztests: $(fuzz-test-targets)
-
-.PHONY: hosttests runhosttests runfuzztests runtests
-hosttests: $(host-test-targets)
-runhosttests: TEST_FLAG=TEST_HOSTTEST=y
-runhosttests: $(run-test-targets)
-runfuzztests: $(run-fuzz-test-targets)
-runtests: runhosttests runfuzztests run-genvif_test
-
-# Automatically enumerate all suites.
-cts_excludes := common
-cts_suites := $(filter-out $(cts_excludes), \
-	$(shell find cts -maxdepth 1 -mindepth 1 -type d -printf "%f "))
-
-# Add boards below as CTS is expanded.
-cts_boards := stm32l476g-eval nucleo-f072rb
-
-.PHONY: build_cts
-
-# Create CTS rule automatically for given suite and board
-# $1: suite name
-# $2: board name
-define make-cts =
-build_cts: cts-$(1)-$(2)
-cts-$(1)-$(2): | $(FAILED_BOARDS_DIR)
-	@touch $(FAILED_BOARDS_DIR)/cts-$(2)-$(1)
-	$$(MAKE) CTS_MODULE=$(1) BOARD=$(2)
-	@rm -f $(FAILED_BOARDS_DIR)/cts-$(2)-$(1)
-# Do not remove this blank line
-
-endef
-
-# Create rules for all cts-suite-board combinations. Additionally, we serialize
-# targets per board: cts-x-board -> cts-y-board -> ...
-# If we don't serialize targets, parallel make fails because all suites
-# try to produce ec.bin in the same directory (e.g. build/stm32l476g-eval).
-$(foreach b, $(cts_boards), \
-	$(foreach s, $(cts_suites), \
-		$(eval $(call make-cts,$(s),$(b))) \
-	) \
-)
-
-cov-boards=lazor volteer
-cov-test-targets=$(foreach t,$(cov-test-list-host),build/coverage/$(t).info)
-cov-test-targets+=$(foreach t,$(cov-boards),build/coverage/initial-$(t).info)
-bldversion=$(shell (./util/getversion.sh ; echo VERSION) | $(CPP) -P -)
-
-# lcov fails when multiple instances run at the same time.
-# We need to run them sequentially by using flock
-cmd_lcov=flock /tmp/ec-lcov-lock -c "lcov --gcov-tool \
-	$(HOSTGCOV) -q -o $@ -c -d build/coverage/$* -t $* \
-	--exclude '*/ec/test/*' --exclude '*/ec/include/tests/*'"
-cmd_lcov-initial=flock /tmp/ec-lcov-lock -c "lcov --gcov-tool \
-	$(GCOV) -q -o $@ -c -d build/coverage/initial-$* \
-	-i -t $* --exclude '*/ec/test/*' --exclude '*/ec/include/tests/*'"
-cmd_merge_cov=lcov -o build/coverage/lcov.info $(foreach info,$^,-a ${info})
-cmd_report_cov=genhtml -q -o build/coverage/coverage_rpt -t \
-	       "EC Unittest "$(bldversion) -s $^
-cmd_strip_lcov=sed -i build/coverage/lcov.info \
-	-e 's/\/mnt\/host\/source\/src\/platform\/ec\///'
-
 # Unless V is set to 0 we always want the 'size:' target to report its output,
 # there is no point in generating a short form command trace when calculating
 # size.
@@ -454,20 +284,6 @@ cmd_stats= \
 	printf "%-10s: %6d\n" $$board $$size; \
   done
 
-.DELETE_ON_ERROR: build/coverage/initial-%.info build/coverage/%.info
-build/coverage/initial-%.info:
-	$(MAKE) TEST_COVERAGE=y BOARD=$* compile-only
-	$(call quiet,lcov-initial,COV    )
-build/coverage/%.info: run-coverage-%
-	$(call quiet,lcov,COV    )
-
-.PHONY: coverage
-coverage: TEST_FLAG=TEST_COVERAGE=y
-coverage: $(cov-test-targets)
-	$(call quiet,merge_cov,MERGE  )
-	$(call quiet,report_cov,REPORT )
-	$(call quiet,strip_lcov,STRIP  )
-
 $(out)/libec.a: $(ro-objs)
 	$(call quiet,libec,BUILD )
 
@@ -633,12 +449,6 @@ $(sharedlib-objs): | $(out)/ec_version.h
 $(out)/ec_version.h:
 	$(call quiet,version,VERSION)
 
-$(build-utils): $(out)/%:$(build-srcs)
-	$(call quiet,c_to_build,BUILDCC)
-
-$(host-utils): $(out)/%:$(host-srcs)
-	$(call quiet,c_to_host,HOSTCC )
-
 $(out)/cscope.files: $(out)/$(PROJECT).bin
 	$(call quiet,deps_to_list,SH     )
 
@@ -648,62 +458,10 @@ $(out)/TAGS: $(out)/cscope.files
 $(out)/tags: $(out)/cscope.files
 	$(call quiet,ctags,CTAGS  )
 
-.PHONY: npx-monitor-dir
-npx-monitor-dir:
-	$(Q)mkdir -p ${out}/chip/npcx/spiflashfw
-
-# See "Commonly used compiler options" for more documentation
-
-# TODO: optional make rules for PROJECT_EXTRA
-$(npcx-monitor-fw-bin):$(npcx-monitor-fw).c npx-monitor-dir
-	$(if $(V),,@echo '  EXTBIN ' $(subst $(out)/,,$@) ; )
-	$(Q)$(CC) $(CFLAGS) -MMD -MF $(out)/$(npcx-lfw).d -c $< \
-		-MT $(out)/$(npcx-monitor-fw).o -o $(out)/$(npcx-monitor-fw).o
-	$(Q)$(CC) $(out)/$(npcx-monitor-fw).o $(LDFLAGS) \
-		-o $(out)/$(npcx-monitor-fw).elf -Wl,-T,$(npcx-monitor-fw).ld \
-		-Wl,-Map,$(out)/$(npcx-monitor-fw).map
-	$(Q)$(OBJCOPY) -O binary $(out)/$(npcx-monitor-fw).elf $@
-
-$(out)/$(npcx-monitor-hdr)_ro.o:$(npcx-monitor-hdr).c npx-monitor-dir
-	$(Q)$(CC) $(CFLAGS) -DSECTION_IS_RO=$(EMPTY) -MMD -c $< -MT $@ -o $@
-
-$(npcx-monitor-hdr-ro-bin):$(out)/$(npcx-monitor-hdr)_ro.o
-	$(if $(V),,@echo '  EXTBIN ' $(subst $(out)/,,$@) ; )
-	$(Q)$(OBJCOPY) -O binary $< $@
-
-$(out)/$(npcx-monitor-hdr)_rw.o:$(npcx-monitor-hdr).c npx-monitor-dir
-	$(Q)$(CC) $(CFLAGS) -MMD -c $< -MT $@ -o $@
-
-$(npcx-monitor-hdr-rw-bin):$(out)/$(npcx-monitor-hdr)_rw.o
-	$(if $(V),,@echo '  EXTBIN ' $(subst $(out)/,,$@) ; )
-	$(Q)$(OBJCOPY) -O binary $< $@
-
 .PHONY: xrefs
 xrefs: $(call targ_if_prog,etags,$(out)/TAGS) \
 	$(call targ_if_prog,ctags,$(out)/tags)
 
-openocd-cfg-flash = $(or $(wildcard $(BDIR)/openocd-flash.cfg),\
-	$(error Board $(BOARD) doesn't support OpenOCD flashing))
-
-.PHONY: flash
-flash: $(out)/ec.bin
-	openocd -c "set BOARD $(BOARD)"\
-		-c "set BUILD_DIR $(out)"\
-		-f $(openocd-cfg-flash)
-
-.PHONY: flash_ec
-flash_ec: $(out)/ec.bin
-	./util/flash_ec --board $(BOARD) --image $(out)/ec.bin --port $(PORT)
-
-.PHONY: flash_dfu
-flash_dfu: $(out)/ec.bin
-	sudo ./$(BDIR)/dfu $(out)/ec.bin
-
-# Deprecated, use print-make-vars instead
-.PHONY: print-baseboard
-print-baseboard:
-	@echo "${BASEBOARD}"
-
 # Print variables identifying and providing Makefile-specific
 # configuration for each board. The format is one variable per line,
 # in the format KEY=VALUE.
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
index 0cfaa932a9..59ed811b4c 100644
--- a/PRESUBMIT.cfg
+++ b/PRESUBMIT.cfg
@@ -20,9 +20,3 @@ cros_license_check :
   --exclude_regex=^third_party/linux/
   --exclude_regex=^third_party/sha2/
   --exclude_regex=^third_party/unacl-curve25519/
-
-[Hook Scripts]
-presubmit_check = util/presubmit_check.sh
-config_option_check = util/config_option_check.py
-host_command_check = util/host_command_check.sh
-ec_commands_h = util/linux_ec_commands_h_check.sh
diff --git a/README.fmap b/README.fmap
deleted file mode 100644
index 416d27fe50..0000000000
--- a/README.fmap
+++ /dev/null
@@ -1,40 +0,0 @@
-In the most general case, the flash layout looks something like this:
-
-  +---------------------+
-  | Reserved for EC use |
-  +---------------------+
-
-  +---------------------+
-  |     Vblock B        |
-  +---------------------+
-  |  RW firmware B      |
-  +---------------------+
-
-  +---------------------+
-  |     Vblock A        |
-  +---------------------+
-  |  RW firmware A      |
-  +---------------------+
-
-  +---------------------+
-  |       FMAP          |
-  +---------------------+
-  |   Public root key   |
-  +---------------------+
-  |  Read-only firmware |
-  +---------------------+
-
-
-BIOS firmware (and kernel) put the vblock info at the start of each image
-where it's easy to find. The Blizzard EC expects the firmware vector table
-to come first, so we have to put the vblock at the end. This means we have
-to know where to look for it, but that's built into the FMAP and the RO
-firmware anyway, so that's not an issue.
-
-The RO firmware doesn't need a vblock of course, but it does need some
-reserved space for vboot-related things.
-
-Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public
-root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If
-we reserve 4K at the top of each FW image, that should give us plenty of
-room for vboot-related stuff.
diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c
deleted file mode 100644
index c89348a562..0000000000
--- a/baseboard/asurada/baseboard.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada baseboard-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "it5205_sbu.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power_button.h"
-#include "power.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-
-#include "gpio_list.h"
-
-/* Wake-up pins for hibernate */
-enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/*
- * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
- * at default.
- * In order to set frequency independently for each channels,
- * We use timing registers 09h~0Bh, and the supported frequency will be:
- * 50KHz, 100KHz, 400KHz, or 1MHz.
- * I2C channels (D, E and F) can be set different frequency on different ports.
- * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
- * the individual prescale register.
- * The frequency of SMBus module is 24MHz on default.
- * The allowed range of I2C(D/E/F) frequency is as following setting.
- * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
- * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
- * Channel D has multi-function and can be used as UART interface.
- * Channel F is reserved for EC debug.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"bat_chg",  IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-	{"sensor",   IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"usb0",     IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"usb1",     IT83XX_I2C_CH_E, 400, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
-{
-	const static struct cc_para_t
-		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-	};
-
-	return &cc_parameter[port];
-}
diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h
deleted file mode 100644
index f3c0808660..0000000000
--- a/baseboard/asurada/baseboard.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* IT81202-bx config */
-/*
- * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
- * connect to 1.8v on other versions.
- */
-#define CONFIG_IT83XX_VCC_1P8V
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_CHIPSET_MT8192
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Chipset */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_COMMON
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* BC12 */
-#define CONFIG_BC12_DETECT_MT6360
-#define CONFIG_BC12_DETECT_PI3USB9201
-#undef CONFIG_BC12_SINGLE_DRIVER
-#define CONFIG_USB_CHARGER
-
-/* Charger */
-#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
-#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238C
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-
-/* Keyboard */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* I2C */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
-#define I2C_PORT_POWER   IT83XX_I2C_CH_A
-#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0  IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1  IT83XX_I2C_CH_E
-#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define CONFIG_SMBUS_PEC
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* PD / USB-C / PPC */
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_IT83XX_TUNE_CC_PHY
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_SYV682C
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_MUX_IT5205 /* C0 */
-#define CONFIG_USB_MUX_PS8743 /* C1 */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FRS_PPC
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#define CONFIG_USB_PID 0x5053
-#define CONFIG_USB_POWER_DELIVERY
-
-/* USB-A */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-#define USB_PORT_COUNT USBA_PORT_COUNT
-
-/* UART */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Sensor */
-#ifdef HAS_TASK_MOTIONSENSE
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_ACCELS
-
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
-#endif
-
-/* SPI / Host Command */
-#define CONFIG_SPI
-
-/* MKBP */
-#define CONFIG_MKBP_EVENT
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* Voltage regulator control */
-#define CONFIG_HOSTCMD_REGULATOR
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* And the MKBP events */
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT))
-
-#include "baseboard_common.h"
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-#include "power/mt8192.h"
-
-void board_reset_pd_mcu(void);
-enum board_sub_board board_get_sub_board(void);
-void usb_a0_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h
deleted file mode 100644
index 0245ae42bf..0000000000
--- a/baseboard/asurada/baseboard_common.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada baseboard-specific onfiguration common to ECOS and Zephyr */
-
-#ifndef __CROS_EC_BASEBOARD_COMMON_H
-#define __CROS_EC_BASEBOARD_COMMON_H
-
-/* GPIO name remapping */
-#define GPIO_EN_HDMI_PWR        GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_FRS_EN      GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2
-#define GPIO_PS185_EC_DP_HPD    GPIO_X_EC_GPIO2
-#define GPIO_USB_C1_DP_IN_HPD   GPIO_EC_X_GPIO3
-#define GPIO_PS185_PWRDN_ODL    GPIO_EC_X_GPIO3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-
-enum board_sub_board {
-	SUB_BOARD_NONE = -1,
-	SUB_BOARD_TYPEC,
-	SUB_BOARD_HDMI,
-	SUB_BOARD_COUNT,
-};
-
-/**
- * board_get_version() - Get the board version
- *
- * Read the ADC to obtain the board version
- *
- * @return board version in the range 0 to 14 inclusive
- */
-int board_get_version(void);
-
-void ppc_interrupt(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void x_ec_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BASEBOARD_COMMON_H */
diff --git a/baseboard/asurada/board_chipset.c b/baseboard/asurada/board_chipset.c
deleted file mode 100644
index 4d12fb0334..0000000000
--- a/baseboard/asurada/board_chipset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada baseboard-chipset specific configuration */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c
deleted file mode 100644
index a4590f3199..0000000000
--- a/baseboard/asurada/board_id.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "util.h"
-
-/**
- * Conversion based on following table:
- *
- * ID | Rp   | Rd   | Voltage
- *    | kOhm | kOhm | mV
- * ---+------+------+--------
- *  0 | 51.1 |  2.2 | 136.2
- *  1 | 51.1 | 6.81 | 388.1
- *  2 | 51.1 |   11 | 584.5
- *  3 | 57.6 |   18 | 785.7
- *  4 | 51.1 |   22 | 993.2
- *  5 | 51.1 |   30 | 1220.7
- *  6 | 51.1 | 39.2 | 1432.6
- *  7 |   56 |   56 | 1650.0
- *  8 |   47 | 61.9 | 1875.8
- *  9 |   47 | 80.6 | 2084.5
- * 10 |   56 |  124 | 2273.3
- * 11 | 51.1 |  150 | 2461.5
- * 12 |   47 |  200 | 2672.1
- * 13 |   47 |  330 | 2888.6
- * 14 |   47 |  680 | 3086.7
- */
-const static int voltage_map[] = {
-	136,
-	388,
-	584,
-	785,
-	993,
-	1220,
-	1432,
-	1650,
-	1875,
-	2084,
-	2273,
-	2461,
-	2672,
-	2888,
-	3086,
-};
-
-const int threshold_mv = 100;
-
-/**
- * Convert ADC value to board id using the voltage table above.
- *
- * @param ch	ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1.
- *
- * @return	a non-negative board id, or negative value if error.
- */
-static int adc_value_to_numeric_id(enum adc_channel ch)
-{
-	int mv;
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
-	/* Wait to allow cap charge */
-	msleep(10);
-
-	mv = adc_read_channel(ch);
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ch);
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 1);
-
-	if (mv == ADC_READ_ERROR)
-		return -EC_ERROR_UNKNOWN;
-
-	for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) {
-		if (IN_RANGE(mv, voltage_map[i] - threshold_mv,
-			     voltage_map[i] + threshold_mv))
-			return i;
-	}
-
-	return -EC_ERROR_UNKNOWN;
-}
-
-static int version = -1;
-
-/* b/163963220: Cache ADC value before board_hibernate_late() reads it */
-static void board_version_init(void)
-{
-	version = adc_value_to_numeric_id(ADC_BOARD_ID_0);
-	if (version < 0) {
-		ccprints("WARN:BOARD_ID_0");
-		ccprints("Assuming board id = 0");
-
-		version = 0;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1);
-
-__override int board_get_version(void)
-{
-	return version;
-}
diff --git a/baseboard/asurada/build.mk b/baseboard/asurada/build.mk
deleted file mode 100644
index ce7b7272bd..0000000000
--- a/baseboard/asurada/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-y+=board_chipset.o
-baseboard-y+=board_id.o
-baseboard-y+=hibernate.o
-baseboard-y+=regulator.o
-baseboard-y+=usbc_config.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c
deleted file mode 100644
index b26bd44adc..0000000000
--- a/baseboard/asurada/hibernate.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charger.h"
-#include "driver/charger/isl923x_public.h"
-#include "gpio.h"
-#include "system.h"
-
-/* Hayato board specific hibernate implementation */
-__override void board_hibernate_late(void)
-{
-	/*
-	 * Turn off PP5000_A. Required for devices without Z-state.
-	 * Don't care for devices with Z-state.
-	 */
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-
-	/*
-	 * GPIO_EN_SLP_Z not implemented in rev0/1,
-	 * fallback to usual hibernate process.
-	 */
-	if (board_get_version() <= 1) {
-		if (IS_ENABLED(BOARD_ASURADA) ||
-			(IS_ENABLED(CONFIG_ZEPHYR) &&
-			IS_ENABLED(CONFIG_BOARD_ASURADA)))
-			return;
-	}
-
-	isl9238c_hibernate(CHARGER_SOLO);
-
-	gpio_set_level(GPIO_EN_SLP_Z, 1);
-
-	/* should not reach here */
-	__builtin_unreachable();
-}
diff --git a/baseboard/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c
deleted file mode 100644
index 9ee59a5cc3..0000000000
--- a/baseboard/asurada/it5205_sbu.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IT5205 Type-C SBU OVP handler
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "it5205.h"
-#include "stdbool.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#define OVP_RETRY_DELAY_US_MIN (100 * MSEC)
-
-static unsigned int ovp_retry_delay_us = OVP_RETRY_DELAY_US_MIN;
-
-static void reset_retry_delay(void)
-{
-	CPRINTS("IT5205 SBU OVP cleared");
-	ovp_retry_delay_us = OVP_RETRY_DELAY_US_MIN;
-}
-DECLARE_DEFERRED(reset_retry_delay);
-
-static void reset_csbu(void)
-{
-	/* double the retry time up to 1 minute */
-	ovp_retry_delay_us = MIN(ovp_retry_delay_us * 2, MINUTE);
-	/* and reset it if interrupt not triggered in a short period */
-	hook_call_deferred(&reset_retry_delay_data, 500 * MSEC);
-
-	/* re-enable sbu interrupt */
-	it5205h_enable_csbu_switch(&usb_muxes[0], false);
-	it5205h_enable_csbu_switch(&usb_muxes[0], true);
-}
-DECLARE_DEFERRED(reset_csbu);
-
-static void it5205h_hook_ac_change(void)
-{
-	int reg;
-
-	/* Check if the board has IT5205H, and read its ovp status */
-	if (i2c_read8(I2C_PORT_USB_MUX0, IT5205H_SBU_I2C_ADDR_FLAGS,
-		      IT5205H_REG_ISR, &reg))
-		return;
-
-	/*
-	 * Re-poll ovp status immediately if AC detached, because ovp will
-	 * likely be recovered.
-	 *
-	 * Always perform the re-poll even when this hook is triggered by
-	 * unrelated events.
-	 */
-	if (reg & IT5205H_ISR_CSBU_OVP)
-		hook_call_deferred(&reset_csbu_data, 0);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, it5205h_hook_ac_change, HOOK_PRIO_DEFAULT);
-
-void it5205h_sbu_interrupt(enum gpio_signal signal)
-{
-	CPRINTS("IT5205 SBU OVP triggered");
-	hook_call_deferred(&reset_csbu_data, ovp_retry_delay_us);
-	hook_call_deferred(&reset_retry_delay_data, -1);
-}
diff --git a/baseboard/asurada/it5205_sbu.h b/baseboard/asurada/it5205_sbu.h
deleted file mode 100644
index 8dc59520dd..0000000000
--- a/baseboard/asurada/it5205_sbu.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IT5205 Type-C SBU OVP handler
- */
-
-#ifndef __CROS_EC_ASURADA_IT5205_SBU_H
-#define __CROS_EC_ASURADA_IT5205_SBU_H
-
-void it5205h_sbu_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ASURADA_IT5205_SBU_H */
diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c
deleted file mode 100644
index 35670bda82..0000000000
--- a/baseboard/asurada/regulator.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "bc12/mt6360_public.h"
-
-/* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
-}
-
-int board_regulator_enable(uint32_t index, uint8_t enable)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_enable(id, enable);
-}
-
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_is_enabled(id, enabled);
-}
-
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
-}
-
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_voltage(id, voltage_mv);
-}
diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c
deleted file mode 100644
index f9ba7e5a4d..0000000000
--- a/baseboard/asurada/usb_pd_policy.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "adc.h"
-#include "atomic.h"
-#include "baseboard_common.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "timer.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#if CONFIG_USB_PD_3A_PORTS != 1
-#error Asurada reference must have at least one 3.0 A port
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-int svdm_get_hpd_gpio(int port)
-{
-	/* HPD is low active, inverse the result */
-	return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL);
-}
-
-void svdm_set_hpd_gpio(int port, int en)
-{
-	/*
-	 * HPD is low active, inverse the en
-	 * TODO: C0&C1 shares the same HPD, implement FCFS policy.
-	 */
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en);
-}
-
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-	}
-
-	return 1;
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (!is_dp_muxable(port)) {
-		/* TODO(waihong): Info user? */
-		CPRINTS("p%d: The other port is already muxed.", port);
-		return 0; /* nak */
-	}
-
-	if (lvl)
-		gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port);
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry(port);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq && !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq && cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		/*
-		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
-		 * very short (500us), we can use udelay instead of usleep for
-		 * more stable pulse period.
-		 */
-		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	static int vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
-	int vbus;
-
-	if ((IS_ENABLED(BOARD_HAYATO) && board_get_version() < 4) ||
-	    (IS_ENABLED(BOARD_SPHERION) && board_get_version() < 1))
-		return ppc_is_vbus_present(port);
-
-	/*
-	 * (b:181203590#comment20) TODO(yllin): use
-	 *  PD_VSINK_DISCONNECT_PD for non-5V case.
-	 */
-	vbus = adc_read_channel(board_get_vbus_adc(port)) >=
-	       PD_V_SINK_DISCONNECT_MAX;
-
-#ifdef CONFIG_USB_CHARGER
-	/*
-	 * There's no PPC to inform VBUS change for usb_charger, so inform
-	 * the usb_charger now.
-	 */
-	if (!!(vbus_prev[port] != vbus))
-		usb_charger_vbus_change(port, vbus);
-
-	if (vbus)
-		atomic_or(&vbus_prev[port], 1);
-	else
-		atomic_clear(&vbus_prev[port]);
-#endif
-	return vbus;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow Vconn swap if AP is on. */
-	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c
deleted file mode 100644
index e552c97771..0000000000
--- a/baseboard/asurada/usbc_config.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada baseboard-specific USB-C configuration */
-
-#include "adc.h"
-#include "baseboard_common.h"
-#include "bc12/pi3usb9201_public.h"
-#include "bc12/mt6360_public.h"
-#include "button.h"
-#include "charger.h"
-#include "charge_state_v2.h"
-#include "charger/isl923x_public.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "task.h"
-#include "ppc/syv682x_public.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "tcpm/it8xxx2_pd_public.h"
-#include "uart.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_mux/ps8743_public.h"
-#include "usb_mux/it5205_public.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Baseboard */
-
-static void baseboard_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1);
-
-/* Sub-board */
-
-enum board_sub_board board_get_sub_board(void)
-{
-	static enum board_sub_board sub = SUB_BOARD_NONE;
-
-	if (sub != SUB_BOARD_NONE)
-		return sub;
-
-	/* HDMI board has external pull high. */
-	if (gpio_get_level(GPIO_EC_X_GPIO3)) {
-		sub = SUB_BOARD_HDMI;
-		/* Only has 1 PPC with HDMI subboard */
-		ppc_cnt = 1;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH);
-	} else {
-		sub = SUB_BOARD_TYPEC;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL,
-			       GPIO_INT_BOTH | GPIO_PULL_UP);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW);
-	}
-
-	CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC");
-	return sub;
-}
-
-static void sub_board_init(void)
-{
-	board_get_sub_board();
-}
-DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1);
-
-/* Detect subboard */
-static void board_tcpc_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	/* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */
-	gpio_enable_interrupt(GPIO_X_EC_GPIO2);
-
-	/* If this is not a Type-C subboard, disable the task. */
-	if (board_get_sub_board() != SUB_BOARD_TYPEC)
-		task_disable_task(TASK_ID_PD_C1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* PPC */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	{
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* BC12 */
-const struct mt6360_config_t mt6360_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS,
-};
-
-const struct pi3usb9201_config_t
-		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	/* [0]: unused */
-	[1] = {
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	}
-};
-
-struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{ .drv = &mt6360_drv },
-	{ .drv = &pi3usb9201_drv },
-};
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_BC12_INT_ODL)
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	else
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void board_sub_bc12_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	else
-		/* If this is not a Type-C subboard, disable the task. */
-		task_disable_task(TASK_ID_USB_CHG_P1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_PPC_INT_ODL)
-		/* C0: PPC interrupt */
-		syv682x_interrupt(0);
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-/* USB-A */
-const int usb_port_enable[] = {
-	GPIO_EN_PP5000_USB_A0_VBUS,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-void usb_a0_interrupt(enum gpio_signal signal)
-{
-	enum usb_charge_mode mode = gpio_get_level(signal) ?
-		USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED;
-
-	for (int i = 0; i < USB_PORT_COUNT; i++)
-		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
-}
-
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-	int reg = 0;
-
-	rv = ps8743_read(me, PS8743_REG_MODE, &reg);
-	if (rv)
-		return rv;
-
-	/* Disable FLIP pin, enable I2C control. */
-	reg |= PS8743_MODE_FLIP_REG_CONTROL;
-	/* Disable CE_USB pin, enable I2C control. */
-	reg |= PS8743_MODE_USB_REG_CONTROL;
-	/* Disable CE_DP pin, enable I2C control. */
-	reg |= PS8743_MODE_DP_REG_CONTROL;
-
-	/*
-	 * DP specific config
-	 *
-	 * Enable/Disable IN_HPD on the DB.
-	 */
-	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
-		       mux_state & USB_PD_MUX_DP_ENABLED);
-
-	return ps8743_write(me, PS8743_REG_MODE, reg);
-}
-
-const struct usb_mux usbc0_virtual_mux = {
-	.usb_port = 0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usbc1_virtual_mux = {
-	.usb_port = 1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc0_virtual_mux,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_virtual_mux,
-		.board_set = &board_ps8743_mux_set,
-	},
-};
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO: check correct operation for Asurada */
-}
-
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-	return 0;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
-	 * should already be set correctly in the PPC driver via the pd
-	 * state machine.
-	 */
-}
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-	int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() ==
-							       SUB_BOARD_TYPEC);
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Handle PS185 HPD changing state.
- */
-int debounced_hpd;
-
-static void ps185_hdmi_hpd_deferred(void)
-{
-	const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD);
-
-	/* HPD status not changed, probably a glitch, just return. */
-	if (debounced_hpd == new_hpd)
-		return;
-
-	debounced_hpd = new_hpd;
-
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd);
-	CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug");
-}
-DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
-
-#define PS185_HPD_DEBOUCE 250
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE);
-}
-
-/* HDMI/TYPE-C function shared subboard interrupt */
-void x_ec_interrupt(enum gpio_signal signal)
-{
-	int sub = board_get_sub_board();
-
-	if (sub == SUB_BOARD_TYPEC)
-		/* C1: PPC interrupt */
-		syv682x_interrupt(1);
-	else if (sub == SUB_BOARD_HDMI)
-		hdmi_hpd_interrupt(signal);
-	else
-		CPRINTS("Undetected subboard interrupt.");
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-enum adc_channel board_get_vbus_adc(int port)
-{
-	if (port == 0)
-		return  ADC_VBUS_C0;
-	if (port == 1)
-		return  ADC_VBUS_C1;
-	CPRINTSUSB("Unknown vbus adc port id: %d", port);
-	return ADC_VBUS_C0;
-}
-#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c
deleted file mode 100644
index 2e60b565f8..0000000000
--- a/baseboard/brask/baseboard.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "gpio_signal.h"
-
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h
deleted file mode 100644
index 4b9d8f386a..0000000000
--- a/baseboard/brask/baseboard.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brask baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted HC
- */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
-
-/* NPCX9 config */
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-/*
- * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
- * the "UART1" (NPCX_UART_PORT0) controller when used for
- * CONSOLE_UART.
- */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 for UART1 */
-
-/* CrOS Board Info */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-
-/* EC Defines */
-#define CONFIG_LTO
-#define CONFIG_FPU
-
-/* Verified boot configs */
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Work around double CR50 reset by waiting in initial power on. */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Host communication */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-
-/* USBC BC1.2 */
-#define CONFIG_USB_CHARGER
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Support Barrel Jack */
-#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-/*
- * TODO(b/197475210): Don't allow the system to boot to S0 when
- * the power is lower than CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
- * since there is no battery.
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		30000
-
-/* Chipset config */
-#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/*
- * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM
- * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers
- * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent
- * EC from system shutdown.
- */
-/* #define CONFIG_BOARD_HAS_RTC_RESET */
-
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Buttons */
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_BUTTON_X86
-
-/* Matrix Keyboard Protocol */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-
-/* Thermal features */
-#define CONFIG_DPTF
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_PWM
-
-/* Enable I2C Support */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* UART COMMAND */
-#define CONFIG_CMD_CHARGEN
-
-/* USB Type C and USB PD defines */
-/* Enable the new USB-C PD stack */
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-
-#define CONFIG_CMD_HCDEBUG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_ALT_MODE_UFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_NCT38XX
-
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
-#define CONFIG_CMD_USB_PD_PE
-
-/*
- * The PS8815 TCPC was found to require a 50ms delay to consistently work
- * with non-PD chargers.  Override the default low-power mode exit delay.
- */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
-
-/* Enable USB3.2 DRD */
-#define CONFIG_USB_PD_USB32_DRD
-
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-
-#define CONFIG_USBC_PPC
-/* Note - SN5S330 support automatically adds
- * CONFIG_USBC_PPC_POLARITY
- * CONFIG_USBC_PPC_SBU
- * CONFIG_USBC_PPC_VCONN
- */
-#define CONFIG_USBC_PPC_DEDICATED_INT
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling SOP* communication */
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_USB_PD_DECODE_SOP
-
-/*
- * USB ID
- * This is allocated specifically for Brask
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x5058
-/* Device version of product. */
-#define CONFIG_USB_BCD_DEV 0x0000
-
-/* Remove predefined features */
-#undef CONFIG_HIBERNATE
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_KEYBOARD_VIVALDI
-
-#ifndef __ASSEMBLER__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "common.h"
-#include "baseboard_usbc_config.h"
-#include "extpower.h"
-
-/*
- * Configure run-time data structures and operation based on CBI data. This
- * typically includes customization for changes in the BOARD_VERSION and
- * FW_CONFIG fields in CBI. This routine is called from the baseboard after
- * the CBI data has been initialized.
- */
-__override_proto void board_cbi_init(void);
-
-/*
- * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
- * FW_CONFIG to the board specific defaults.
- */
-__override_proto void board_init_fw_config(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h
deleted file mode 100644
index 1b3d9e5d3f..0000000000
--- a/baseboard/brask/baseboard_usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* brask family-specific USB-C configuration */
-
-#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
-#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
-
-#include "gpio_signal.h"
-
-/* Common definition for the USB PD interrupt handlers. */
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void retimer_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk
deleted file mode 100644
index 5ba6b135f9..0000000000
--- a/baseboard/brask/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brask baseboard specific files build
-#
-
-baseboard-y=
-baseboard-y+=baseboard.o
-baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c
deleted file mode 100644
index 33de5ca5eb..0000000000
--- a/baseboard/brask/usb_pd_policy.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Brask boards */
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_vdo.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap after the PP5000_Z1 rail is enabled */
-	return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/* Responses specifically for the enablement of TBT mode in the role of UFP */
-
-#define OPOS_TBT 1
-
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID,
-						CONFIG_USB_BCD_DEV);
-
-/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
-
-static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
-{
-	/* TODO(b/154962766): Get an XID */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_I(IDH)] = vdo_idh_rev30;
-		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
-		/* TODO(b/181620145): Customize for brya */
-		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
-		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
-		return VDO_I(PTYPE_DFP_VDO) + 1;
-	}
-
-	/* PD Revision 2.0 */
-	payload[VDO_I(IDH)] = vdo_idh;
-	return VDO_I(PRODUCT) + 1;
-}
-
-static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
-	return 2;
-}
-
-static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
-		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
-		return ARRAY_SIZE(vdo_tbt_modes) + 1;
-	} else {
-		return 0; /* NAK */
-	}
-}
-
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
-{
-	mux_state_t mux_state = 0;
-
-	/* Do not enter mode while CPU is off. */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return 0; /* NAK */
-
-	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
-		return 0; /* NAK */
-
-	mux_state = usb_mux_get(port);
-	/*
-	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
-	 * UFP (responder) should be in USB mode or safe mode before sending
-	 * Enter Mode Command response.
-	 */
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
-		pd_ufp_set_enter_mode(port, payload);
-		set_tbt_compat_mode_ready(port);
-		CPRINTS("UFP Enter TBT mode");
-		return 1; /* ACK */
-	}
-
-	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
-	return 0;
-}
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_tbt_compat_response_identity,
-	.svids = &svdm_tbt_compat_response_svids,
-	.modes = &svdm_tbt_compat_response_modes,
-	.enter_mode = &svdm_tbt_compat_response_enter_mode,
-	.amode = NULL,
-	.exit_mode = NULL,
-};
diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c
deleted file mode 100644
index 976831812f..0000000000
--- a/baseboard/brya/baseboard.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "gpio_signal.h"
-
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_ACOK_OD,
-	GPIO_GSC_EC_PWR_BTN_ODL,
-	GPIO_LID_OPEN,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h
deleted file mode 100644
index 757b504d16..0000000000
--- a/baseboard/brya/baseboard.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* NPCX9 config */
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-/*
- * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
- * the "UART1" (NPCX_UART_PORT0) controller when used for
- * CONSOLE_UART.
- */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 for UART1 */
-
-/* EC Defines */
-#define CONFIG_LTO
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-#define CONFIG_DPTF
-#define CONFIG_FPU
-
-/* Verified boot configs */
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#define CONFIG_HIBERNATE_PSL
-
-/* Work around double CR50 reset by waiting in initial power on. */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Host communication */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/*
- * TODO(b/179648721): implement sensors
- */
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_MKBP_INPUT_DEVICES
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT		512
-
-#define CONFIG_CMD_CHARGER_DUMP
-
-#define CONFIG_USB_CHARGER
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated)
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
-
-/* Common battery defines */
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_CMD_BATT_MFG_ACCESS
-/*
- * Enable support for battery hostcmd, supporting longer strings.
- * support for EC_CMD_BATTERY_GET_STATIC version 1.
- */
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Chipset config */
-#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
-
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-
-/*
- * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM
- * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers
- * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent
- * EC from system shutdown.
- */
-/* #define CONFIG_BOARD_HAS_RTC_RESET */
-
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Buttons / Switches */
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_SWITCH
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#ifdef CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#else
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
-#endif
-
-/* Thermal features */
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-
-#define CONFIG_PWM
-
-/* Enable I2C Support */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* EDP back-light control defines */
-#define CONFIG_BACKLIGHT_LID
-
-/* UART COMMAND */
-#define CONFIG_CMD_CHARGEN
-
-/* USB Type C and USB PD defines */
-/* Enable the new USB-C PD stack */
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-
-#define CONFIG_CMD_HCDEBUG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_ALT_MODE_UFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_NCT38XX
-
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
-#define CONFIG_CMD_USB_PD_PE
-
-/*
- * The PS8815 TCPC was found to require a 50ms delay to consistently work
- * with non-PD chargers.  Override the default low-power mode exit delay.
- */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
-
-/* Enable USB3.2 DRD */
-#define CONFIG_USB_PD_USB32_DRD
-
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-
-#define CONFIG_USBC_PPC
-/* Note - SN5S330 support automatically adds
- * CONFIG_USBC_PPC_POLARITY
- * CONFIG_USBC_PPC_SBU
- * CONFIG_USBC_PPC_VCONN
- */
-#define CONFIG_USBC_PPC_DEDICATED_INT
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling SOP* communication */
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_USB_PD_DECODE_SOP
-
-/*
- * USB ID
- * This is allocated specifically for Brya
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x504F
-/* Device version of product. */
-#define CONFIG_USB_BCD_DEV 0x0000
-
-#ifndef __ASSEMBLER__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "common.h"
-#include "baseboard_usbc_config.h"
-#include "extpower.h"
-
-/**
- * Configure run-time data structures and operation based on CBI data. This
- * typically includes customization for changes in the BOARD_VERSION and
- * FW_CONFIG fields in CBI. This routine is called from the baseboard after
- * the CBI data has been initialized.
- */
-__override_proto void board_cbi_init(void);
-
-/**
- * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
- * FW_CONFIG to the board specific defaults.
- */
-__override_proto void board_init_fw_config(void);
-
-/*
- * Check battery disconnect state.
- * This function will return if battery is initialized or not.
- * @return true - initialized. false - not.
- */
-__override_proto bool board_battery_is_initialized(void);
-
-/*
- * Return the board revision number.
- */
-uint8_t get_board_id(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/brya/baseboard_usbc_config.h b/baseboard/brya/baseboard_usbc_config.h
deleted file mode 100644
index f8b9fab35c..0000000000
--- a/baseboard/brya/baseboard_usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* brya family-specific USB-C configuration */
-
-#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
-#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
-
-#include "gpio_signal.h"
-
-/* Common definition for the USB PD interrupt handlers. */
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void retimer_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c
deleted file mode 100644
index 94c9926820..0000000000
--- a/baseboard/brya/battery_presence.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common battery presence checking for Brya family.
- * Each board should implement board_battery_info[] to define the specific
- * battery packs supported.
- */
-#include <stdbool.h>
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "common.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-__overridable bool board_battery_is_initialized(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) != EC_SUCCESS ? false :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-
-	if (battery_is_cut_off())
-		return BP_NO;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres == BP_NO)
-		return BP_NO;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if ((batt_pres == BP_YES) && (batt_pres == batt_pres_prev))
-		return BP_YES;
-
-	/*
-	 * Check battery initialization. If the battery is not initialized,
-	 * then return BP_NOT_SURE. Battery could be in ship
-	 * mode and might require pre-charge current to wake it up. BP_NO is not
-	 * returned here because charger state machine will not provide
-	 * pre-charge current assuming that battery is not present.
-	 */
-	if (!board_battery_is_initialized())
-		return BP_NOT_SURE;
-
-	return BP_YES;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/baseboard/brya/build.mk b/baseboard/brya/build.mk
deleted file mode 100644
index ca983f26ac..0000000000
--- a/baseboard/brya/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brya baseboard specific files build
-#
-
-baseboard-y=
-baseboard-y+=baseboard.o
-baseboard-y+=battery_presence.o
-baseboard-y+=cbi.o
-baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c
deleted file mode 100644
index 6d9e2b93fa..0000000000
--- a/baseboard/brya/cbi.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-
-#include "console.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-static uint8_t board_id;
-
-uint8_t get_board_id(void)
-{
-	return board_id;
-}
-
-__overridable void board_cbi_init(void)
-{
-}
-
-__overridable void board_init_fw_config(void)
-{
-}
-
-/*
- * Read CBI from I2C EEPROM and initialize variables for board variants.
- */
-static void cbi_init(void)
-{
-	uint32_t cbi_val;
-
-	/* Board ID */
-	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
-	    cbi_val > UINT8_MAX)
-		CPRINTS("CBI: Read Board ID failed");
-	else
-		board_id = cbi_val;
-
-	CPRINTS("Board ID: %d", board_id);
-
-	board_init_fw_config();
-
-	/* Allow the board project to make runtime changes based on CBI data */
-	board_cbi_init();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c
deleted file mode 100644
index 04be67147d..0000000000
--- a/baseboard/brya/charger_bq25720.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/charger/bq25710.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "util.h"
-
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
-		.drv = &bq25710_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = board_is_usb_pd_port_present(port);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-					  int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c
deleted file mode 100644
index df291bd9c9..0000000000
--- a/baseboard/brya/usb_pd_policy.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Brya boards */
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_vdo.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap after the PP5000_Z1 rail is enabled */
-	return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/* Responses specifically for the enablement of TBT mode in the role of UFP */
-
-#define OPOS_TBT 1
-
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID,
-						CONFIG_USB_BCD_DEV);
-
-/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
-
-static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
-{
-	/* TODO(b/154962766): Get an XID */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_I(IDH)] = vdo_idh_rev30;
-		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
-		/* TODO(b/181620145): Customize for brya */
-		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
-		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
-		return VDO_I(PTYPE_DFP_VDO) + 1;
-	}
-
-	/* PD Revision 2.0 */
-	payload[VDO_I(IDH)] = vdo_idh;
-	return VDO_I(PRODUCT) + 1;
-}
-
-static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
-	return 2;
-}
-
-static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
-		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
-		return ARRAY_SIZE(vdo_tbt_modes) + 1;
-	} else {
-		return 0; /* NAK */
-	}
-}
-
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
-{
-	mux_state_t mux_state = 0;
-
-	/* Do not enter mode while CPU is off. */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return 0; /* NAK */
-
-	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
-		return 0; /* NAK */
-
-	mux_state = usb_mux_get(port);
-	/*
-	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
-	 * UFP (responder) should be in USB mode or safe mode before sending
-	 * Enter Mode Command response.
-	 */
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
-		pd_ufp_set_enter_mode(port, payload);
-		set_tbt_compat_mode_ready(port);
-		CPRINTS("UFP Enter TBT mode");
-		return 1; /* ACK */
-	}
-
-	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
-	return 0;
-}
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_tbt_compat_response_identity,
-	.svids = &svdm_tbt_compat_response_svids,
-	.modes = &svdm_tbt_compat_response_modes,
-	.enter_mode = &svdm_tbt_compat_response_enter_mode,
-	.amode = NULL,
-	.exit_mode = NULL,
-};
diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c
deleted file mode 100644
index daf5e218d2..0000000000
--- a/baseboard/cherry/baseboard.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cherry baseboard-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/rt1718s.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/ps8802.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/rt1718s.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/anx3443.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "pwm_chip.h"
-#include "pwm.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-static void bc12_interrupt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void usb_a0_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Wake-up pins for hibernate */
-enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Override default setting, called after charger_chips_init */
-static void baseboard_charger_init(void)
-{
-	/* b/198707662#comment9 */
-	int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP)
-			<< ISL9238_INPUT_VOLTAGE_REF_SHIFT;
-
-	i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_INPUT_VOLTAGE, reg);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2);
-
-__override void board_hibernate_late(void)
-{
-	/*
-	 * Turn off PP5000_A. Required for devices without Z-state.
-	 * Don't care for devices with Z-state.
-	 */
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-	isl9238c_hibernate(CHARGER_SOLO);
-	gpio_set_level(GPIO_EN_SLP_Z, 1);
-
-	/* should not reach here */
-	__builtin_unreachable();
-}
-
-static void board_tcpc_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-}
-/* Must be done after I2C */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void rt1718s_tcpc_interrupt(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(1);
-}
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
-	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-	{"TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_CHARGER,
-	},
-};
-
-/* PPC */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	{
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = RT1718S_I2C_ADDR_FLAGS,
-		.drv = &rt1718s_ppc_drv,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* BC12 */
-const struct mt6360_config_t mt6360_config = {
-	.i2c_port = 0,
-	.i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS,
-};
-
-__maybe_unused const struct pi3usb9201_config_t
-		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0] = {
-		.i2c_port = I2C_PORT_USB0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	}
-	/* [1]: unused */
-};
-
-struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-#ifdef CONFIG_BC12_DETECT_PI3USB9201
-	{ .drv = &pi3usb9201_drv },
-#elif defined(CONFIG_BC12_DETECT_MT6360)
-	{ .drv = &mt6360_drv },
-#else
-#error must pick one of PI3USB9201 or MT6360 for port 0
-#endif
-	{ .drv = &rt1718s_bc12_drv },
-};
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	syv682x_interrupt(0);
-}
-
-/* PWM */
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4,
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4,
-	},
-	[PWM_CH_LED3] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		.freq_hz = 10000, /* SYV226 supports 10~100kHz */
-		.pcfsr_sel = PWM_PRESCALER_C6,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* USB-A */
-const int usb_port_enable[] = {
-	GPIO_EN_PP5000_USB_A0_VBUS_X,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-__maybe_unused void usb_a0_interrupt(enum gpio_signal signal)
-{
-	enum usb_charge_mode mode = gpio_get_level(signal) ?
-		USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED;
-
-	for (int i = 0; i < USB_PORT_COUNT; i++)
-		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
-}
-
-/* USB Mux */
-
-const struct usb_mux usbc0_virtual_mux = {
-	.usb_port = 0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usbc1_virtual_mux = {
-	.usb_port = 1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-static int board_ps8802_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	/* Make sure the PS8802 is awake */
-	RETURN_ERROR(ps8802_i2c_wake(me));
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		RETURN_ERROR(ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB));
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		RETURN_ERROR(ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int board_anx3443_mux_set(const struct usb_mux *me,
-				 mux_state_t mux_state)
-{
-	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
-		       mux_state & USB_PD_MUX_DP_ENABLED);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
-		.driver = &ps8802_usb_mux_driver,
-		.next_mux = &usbc0_virtual_mux,
-		.board_set = &board_ps8802_mux_set,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
-		.driver = &anx3443_usb_mux_driver,
-		.next_mux = &usbc1_virtual_mux,
-		.board_set = &board_anx3443_mux_set,
-	},
-};
-
-/*
- * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
- * at default.
- * In order to set frequency independently for each channels,
- * We use timing registers 09h~0Bh, and the supported frequency will be:
- * 50KHz, 100KHz, 400KHz, or 1MHz.
- * I2C channels (D, E and F) can be set different frequency on different ports.
- * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
- * the individual prescale register.
- * The frequency of SMBus module is 24MHz on default.
- * The allowed range of I2C(D/E/F) frequency is as following setting.
- * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
- * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
- * Channel D has multi-function and can be used as UART interface.
- * Channel F is reserved for EC debug.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"bat_chg",  IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-	{"sensor",   IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"usb0",     IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"usb1",     IT83XX_I2C_CH_E, 1000, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB1,
-			.addr_flags = RT1718S_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1718s_tcpm_drv,
-	},
-};
-
-__override int board_rt1718s_init(int port)
-{
-	/* set GPIO 1~3 as push pull, as output, output low. */
-	rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW);
-	rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW);
-	rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW);
-
-	/* gpio 1/2 output high when receiving frx signal */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
-			RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0xFF));
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL,
-			RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF));
-
-	/* Turn on SBU switch */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01,
-				RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
-				RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN |
-				RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN,
-				0xFF));
-	/* Trigger GPIO 1/2 change when FRS signal received */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2));
-	/* Set FRS signal detect time to 46.875us */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
-			RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
-			0xFF));
-
-	return EC_SUCCESS;
-}
-
-const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
-{
-	const static struct cc_para_t cc_parameter = {
-		.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-		.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-	};
-
-	if (port == USBPD_PORT_A)
-		return &cc_parameter;
-	return NULL;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * C0 TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return PD_STATUS_TCPC_ALERT_1;
-	return 0;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0: The internal TCPC on ITE EC does not have a reset signal,
-	 * but it will get reset when the EC gets reset.
-	 */
-	/* C1: Add code if TCPC chips need a reset */
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
-	 * should already be set correctly in the PPC driver via the pd
-	 * state machine.
-	 */
-}
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-	bool is_valid_port = (port == 0 || port == 1);
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling C%d as sink failed.", i);
-		}
-		rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, 1);
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, !(port == 1));
-
-	return EC_SUCCESS;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-
-	/* TODO: add rt1718s */
-	return 0;
-}
-/* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
-}
-
-int board_regulator_enable(uint32_t index, uint8_t enable)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_enable(id, enable);
-}
-
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_is_enabled(id, enabled);
-}
-
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
-}
-
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_voltage(id, voltage_mv);
-}
-
-static void baseboard_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-#ifndef BOARD_CHERRY
-	gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1);
-
-__override int board_pd_set_frs_enable(int port, int enable)
-{
-	if (port == 1)
-		/*
-		 * Use set_flags (implemented by a single i2c write) instead
-		 * of set_level (= i2c_update) to save one read operation in
-		 * FRS path.
-		 */
-		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
-				enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
-	return EC_SUCCESS;
-}
-
-__override int board_get_vbus_voltage(int port)
-{
-	int voltage = 0;
-
-	switch (port) {
-	case 0:
-		voltage = adc_read_channel(ADC_VBUS);
-		break;
-	case 1:
-		rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage);
-		break;
-	default:
-		return 0;
-	}
-
-	return voltage;
-}
diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h
deleted file mode 100644
index 8dc1dbfb91..0000000000
--- a/baseboard/cherry/baseboard.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cherry board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* IT81202-bx config */
-/*
- * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
- * connect to 1.8v on other versions.
- */
-#define CONFIG_IT83XX_VCC_1P8V
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_CHIPSET_MT8192
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Chipset */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_COMMON
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* BC12 */
-#ifdef BOARD_CHERRY
-#define CONFIG_BC12_DETECT_PI3USB9201
-#endif
-#define CONFIG_BC12_DETECT_MT6360
-#undef CONFIG_BC12_SINGLE_DRIVER
-#define CONFIG_USB_CHARGER
-
-/* CBI */
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CBI_EEPROM
-#define CONFIG_CMD_CBI
-#define I2C_PORT_EEPROM IT83XX_I2C_CH_A
-#define I2C_ADDR_EEPROM_FLAGS 0x50
-
-/* Charger */
-#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
-#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238C
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-/* Not used in boot flow, set to 0 to suppress system_can_boot_ap warning */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 0
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-
-/* Keyboard */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* I2C */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_CHARGER  IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY  IT83XX_I2C_CH_A
-#define I2C_PORT_ACCEL    IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0     IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1     IT83XX_I2C_CH_E
-#define I2C_PORT_USB0     IT83XX_I2C_CH_C
-#define I2C_PORT_USB1     IT83XX_I2C_CH_E
-#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define CONFIG_SMBUS_PEC
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* PD / USB-C / PPC */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_IT83XX_TUNE_CC_PHY
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_RT1718S
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USBC_RETIMER_PS8802 /* C0 */
-#define CONFIG_USB_MUX_ANX3443 /* C1 */
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DPS
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_FRS_PPC
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_PPC
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_RT1718S
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
-#define CONFIG_USB_PID 0x5054
-#define CONFIG_USB_POWER_DELIVERY
-
-#define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_VOLTAGE_MV 20000
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW 60000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* USB-A */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-#define USB_PORT_COUNT USBA_PORT_COUNT
-
-/* UART */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Sensor */
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_ACCELS
-
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* SPI / Host Command */
-#define CONFIG_SPI
-
-/* MKBP */
-#define CONFIG_MKBP_EVENT
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* Voltage regulator control */
-#define CONFIG_HOSTCMD_REGULATOR
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-#include "power/mt8192.h"
-
-enum adc_channel {
-	ADC_VBUS,                /* ADC 0 */
-	ADC_BOARD_ID,            /* ADC 1 */
-	ADC_SKU_ID,              /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
-	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
-
-	/* Number of ADC channels */
-	ADC_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1,
-	PWM_CH_LED2,
-	PWM_CH_LED3,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-void board_reset_pd_mcu(void);
-void rt1718s_tcpc_interrupt(enum gpio_signal signal);
-
-/* RT1718S gpio to pin name mapping */
-#define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1
-#define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2
-#define GPIO_EN_USB_C1_FRS    RT1718S_GPIO3
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/cherry/build.mk b/baseboard/cherry/build.mk
deleted file mode 100644
index ae82c1ca68..0000000000
--- a/baseboard/cherry/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c
deleted file mode 100644
index 0c7f4dcee5..0000000000
--- a/baseboard/cherry/usb_pd_policy.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "adc.h"
-#include "atomic.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "driver/tcpm/rt1718s.h"
-#include "driver/tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#if CONFIG_USB_PD_3A_PORTS != 1
-#error Cherry reference must have at least one 3.0 A port
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-/* The port that the aux channel is on. */
-static enum {
-	AUX_PORT_NONE = -1,
-	AUX_PORT_C0 = 0,
-	AUX_PORT_C1HDMI = 1,
-} aux_port = AUX_PORT_NONE;
-
-int svdm_get_hpd_gpio(int port)
-{
-	/* HPD is low active, inverse the result */
-	return !gpio_get_level(GPIO_EC_AP_DP_HPD_ODL);
-}
-
-void svdm_set_hpd_gpio(int port, int en)
-{
-	/*
-	 * HPD is low active, inverse the en
-	 * TODO: C0&C1 shares the same HPD, implement FCFS policy.
-	 */
-	gpio_set_level(GPIO_EC_AP_DP_HPD_ODL, !en);
-}
-
-static void aux_switch_port(int port)
-{
-	if (port != AUX_PORT_NONE)
-		gpio_set_level_verbose(CC_USBPD, GPIO_DP_PATH_SEL, !port);
-	aux_port = port;
-}
-
-static void aux_display_disconnected(int port)
-{
-	/* Gets the other port. C0 -> C1, C1 -> C0. */
-	int other_port = !port;
-
-	/* If the current port is not the aux port, nothing needs to be done. */
-	if (aux_port != port)
-		return;
-
-	/* If the other port is connected to a external display, switch aux. */
-	if (dp_status[other_port] & DP_FLAGS_DP_ON)
-		aux_switch_port(other_port);
-	else
-		aux_switch_port(AUX_PORT_NONE);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry(port);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq && !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq && cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		/*
-		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
-		 * very short (500us), we can use udelay instead of usleep for
-		 * more stable pulse period.
-		 */
-		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/*
-	 * Cherry can only output to 1 display port at a time.
-	 * This implements FCFS policy by changing the aux channel. If a
-	 * display is connected to the either port (says A), and the port A
-	 * will be served until the display is disconnected from port A.
-	 * It won't output to the other display which connects to port B.
-	 */
-	if (lvl && aux_port == AUX_PORT_NONE)
-		/*
-		 * A display is connected, and no display was plugged on either
-		 * port.
-		 */
-		aux_switch_port(port);
-	else if (!lvl)
-		aux_display_disconnected(port);
-
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-
-	aux_display_disconnected(port);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
-	int vbus;
-
-	/*
-	 * Use ppc_is_vbus_present for all ports on Cherry, and
-	 * port 1 on other devices.
-	 */
-	if (IS_ENABLED(BOARD_CHERRY) || port == 1)
-		return ppc_is_vbus_present(port);
-
-	/* b/181203590: use ADC for port 0 (syv682x) */
-	vbus = (adc_read_channel(ADC_VBUS) >= PD_V_SINK_DISCONNECT_MAX);
-
-#ifdef CONFIG_USB_CHARGER
-	/*
-	 * There's no PPC to inform VBUS change for usb_charger, so inform
-	 * the usb_charger now.
-	 */
-	if (!!(vbus_prev[port] != vbus))
-		usb_charger_vbus_change(port, vbus);
-
-	if (vbus)
-		atomic_or(&vbus_prev[port], 1);
-	else
-		atomic_clear(&vbus_prev[port]);
-#endif
-	return vbus;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	if (port == 1)
-		rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow Vconn swap if AP is on. */
-	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	if (port == 1)
-		rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
deleted file mode 100644
index 2f71f03068..0000000000
--- a/baseboard/dedede/baseboard.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dedede family-specific configuration */
-
-#include "adc.h"
-#include "board_config.h"
-#include "cbi_fw_config.h"
-#include "charger/isl923x_public.h"
-#include "charger/sm5803.h"
-#include "chipset.h"
-#include "common.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "power/icelake.h"
-#include "power/intel_x86.h"
-#include "system.h"
-#include "usb_pd.h"
-
-/******************************************************************************/
-/*
- * PWROK signal configuration, see the PWROK Generation Flow Diagram in the
- * Jasper Lake Platform Design Guide for the list of potential signals.
- *
- * Dedede boards use this PWROK sequence:
- *	GPIO_ALL_SYS_PWRGD - turns on VCCIN rail
- *	GPIO_EC_AP_VCCST_PWRGD_OD - asserts VCCST_PWRGD to AP, requires 2ms
- *		delay from VCCST stable to meet the tCPU00 platform sequencing
- *		timing
- *	GPIO_EC_AP_PCH_PWROK_OD - asserts PMC_PCH_PWROK to the AP. Note that
- *		PMC_PCH_PWROK is also gated by the IMVP9_VRRDY_OD output from
- *		the VCCIN voltage rail controller.
- *	GPIO_EC_AP_SYS_PWROK - asserts PMC_SYS_PWROK to the AP
- *
- * Both PMC_PCH_PWROK and PMC_SYS_PWROK signals must both be asserted before
- * the Jasper Lake SoC deasserts PMC_RLTRST_N. The platform may deassert
- * PMC_PCH_PWROK and PMC_SYS_PWROK in any order to optimize overall boot
- * latency.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
-	{
-		.gpio = GPIO_ALL_SYS_PWRGD,
-	},
-	{
-		.gpio = GPIO_EC_AP_VCCST_PWRGD_OD,
-		.delay_ms = 2,
-	},
-	{
-		.gpio = GPIO_EC_AP_PCH_PWROK_OD,
-	},
-	{
-		.gpio = GPIO_EC_AP_SYS_PWROK,
-	},
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
-	/* No delays needed during S0 exit */
-	{
-		.gpio = GPIO_EC_AP_VCCST_PWRGD_OD,
-	},
-	{
-		.gpio = GPIO_EC_AP_PCH_PWROK_OD,
-	},
-	{
-		.gpio = GPIO_EC_AP_SYS_PWROK,
-	},
-	/* Turn off the VCCIN rail last */
-	{
-		.gpio = GPIO_ALL_SYS_PWRGD,
-	},
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
-
-
-/*
- * Dedede does not use hibernate wake pins, but the super low power "Z-state"
- * instead in which the EC is powered off entirely.  Power will be restored to
- * the EC once one of the wake up events occurs.  These events are ACOK, lid
- * open, and a power button press.
- */
-const enum gpio_signal hibernate_wake_pins[] = {};
-const int hibernate_wake_pins_used;
-
-__override void board_after_rsmrst(int rsmrst)
-{
-	/*
-	 * b:148688874: If RSMRST# is de-asserted, enable the pull-up on
-	 * PG_PP1050_ST_OD.  It won't be enabled prior to this signal going high
-	 * because the load switch for PP1050_ST cannot pull the PG low.  Once
-	 * it's asserted, disable the pull up so we don't inidicate that the
-	 * power is good before the rail is actually ready.
-	 */
-	int flags = rsmrst ? GPIO_PULL_UP : 0;
-
-	flags |= GPIO_INT_BOTH;
-
-	gpio_set_flags(GPIO_PG_PP1050_ST_OD, flags);
-}
-
-/*
- * Dedede does not have a GPIO indicating ACOK, therefore the charger or TCPC
- * can call this function once it detects a VBUS presence change with which we
- * can trigger the HOOK_AC_CHANGE hook.
- */
-__override void board_check_extpower(void)
-{
-	static int last_extpower_present;
-	int extpower_present = extpower_is_present();
-
-	if (last_extpower_present ^ extpower_present)
-		extpower_handle_update(extpower_present);
-
-	last_extpower_present = extpower_present;
-}
-
-uint32_t pp3300_a_pgood;
-__override int intel_x86_get_pg_ec_dsw_pwrok(void)
-{
-	/*
-	 * The PP3300_A rail is an input to generate DPWROK.  Assuming that
-	 * power is good if voltage is at least 80% of nominal level.  We cannot
-	 * read the ADC values during an interrupt, therefore, this power good
-	 * value is updated via ADC threshold interrupts.
-	 */
-	return pp3300_a_pgood;
-}
-
-/* Store away PP300_A good status before sysjumps */
-#define BASEBOARD_SYSJUMP_TAG	0x4242 /* BB */
-#define BASEBOARD_HOOK_VERSION	1
-
-static void pp3300_a_pgood_preserve(void)
-{
-	system_add_jump_tag(BASEBOARD_SYSJUMP_TAG, BASEBOARD_HOOK_VERSION,
-			    sizeof(pp3300_a_pgood), &pp3300_a_pgood);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, pp3300_a_pgood_preserve, HOOK_PRIO_DEFAULT);
-
-static void baseboard_prepare_power_signals(void)
-{
-	const int *stored;
-	int version, size;
-
-	stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG,
-						  &version, &size);
-	if (stored && (version == BASEBOARD_HOOK_VERSION) &&
-					(size == sizeof(pp3300_a_pgood)))
-		/* Valid PP3300 status found, restore before CHIPSET init */
-		pp3300_a_pgood = *stored;
-
-	/* Restore pull-up on PG_PP1050_ST_OD */
-	if (system_jumped_to_this_image() &&
-					gpio_get_level(GPIO_RSMRST_L_PGOOD))
-		board_after_rsmrst(1);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST);
-
-__override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
-{
-	/*
-	 * SLP_S3_L is a qualifying input signal to ALL_SYS_PWRGD logic.
-	 * So ensure ALL_SYS_PWRGD remains LOW during SLP_S3_L assertion.
-	 */
-	if (!gpio_get_level(GPIO_SLP_S3_L))
-		return 0;
-	/*
-	 * ALL_SYS_PWRGD is an AND of DRAM PGOOD, VCCST PGOOD, and VCCIO_EXT
-	 * PGOOD.
-	 */
-	return gpio_get_level(GPIO_PG_PP1050_ST_OD) &&
-		gpio_get_level(GPIO_PG_DRAM_OD) &&
-		gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
-}
-
-__override int power_signal_get_level(enum gpio_signal signal)
-{
-	if (signal == GPIO_PG_EC_DSW_PWROK)
-		return intel_x86_get_pg_ec_dsw_pwrok();
-
-	if (signal == GPIO_PG_EC_ALL_SYS_PWRGD)
-		return intel_x86_get_pg_ec_all_sys_pwrgd();
-
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-		/* Check signal is from GPIOs or VWs */
-		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire(signal);
-	}
-	return gpio_get_level(signal);
-
-}
-
-void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * We need to deassert ALL_SYS_PGOOD within 200us of SLP_S3_L asserting.
-	 * that is why we do this here instead of waiting for the chipset
-	 * driver to.
-	 * Early protos do not pull VCCST_PWRGD below Vil in hardware logic,
-	 * so we need to do the same for this signal.
-	 * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during
-	 * SLP_S3_L assertion.
-	 */
-	if (!gpio_get_level(GPIO_SLP_S3_L)) {
-		gpio_set_level(GPIO_ALL_SYS_PWRGD, 0);
-		gpio_set_level(GPIO_EN_VCCIO_EXT, 0);
-		gpio_set_level(GPIO_EC_AP_VCCST_PWRGD_OD, 0);
-		gpio_set_level(GPIO_EC_AP_PCH_PWROK_OD, 0);
-	}
-	/* Now chain off to the normal power signal interrupt handler. */
-	power_signal_interrupt(signal);
-}
-
-void baseboard_chipset_startup(void)
-{
-#ifdef CONFIG_PWM_KBLIGHT
-	/* Allow keyboard backlight to be enabled */
-	gpio_set_level(GPIO_EN_KB_BL, 1);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-void baseboard_chipset_shutdown(void)
-{
-#ifdef CONFIG_PWM_KBLIGHT
-	/* Turn off the keyboard backlight if it's on. */
-	gpio_set_level(GPIO_EN_KB_BL, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
-void board_hibernate_late(void)
-{
-	volatile uint32_t busy = 0;
-
-	/* Disable any pull-ups on C0 and C1 interrupt lines */
-	gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT);
-	#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT);
-	#endif
-	/*
-	 * Turn on the Z state.  This will not return as it will cut power to
-	 * the EC.
-	 */
-	gpio_set_level(GPIO_EN_SLP_Z, 1);
-
-	/*
-	 * Interrupts are disabled at this point, so busy-loop to consume some
-	 * time (something on the order of at least 1 second, depending on EC
-	 * chip being used)
-	 */
-	while (busy < 100000)
-		busy++;
-
-	/*
-	 * Still awake despite turning on zombie state?  Reset with AP off is
-	 * the best we can do in this situation.
-	 */
-	system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
-
-	/* Await our reset */
-	while (1)
-		;
-}
-
-int board_is_i2c_port_powered(int port)
-{
-	if (port != I2C_PORT_SENSOR)
-		return 1;
-
-	/* Sensor rails are off in S5/G3 */
-	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
-}
-
-int extpower_is_present(void)
-{
-	int port;
-	int rv;
-	bool acok;
-	enum ec_error_list (*check_acok)(int port, bool *acok);
-
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
-		check_acok = raa489000_is_acok;
-	else if (IS_ENABLED(CONFIG_CHARGER_SM5803))
-		check_acok = sm5803_is_acok;
-
-	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		rv = check_acok(port, &acok);
-		if ((rv == EC_SUCCESS) && acok)
-			return 1;
-	}
-
-	return 0;
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (get_cbi_fw_config_kblight() == KB_BL_ABSENT)
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
deleted file mode 100644
index a8a0ed3ff2..0000000000
--- a/baseboard/dedede/baseboard.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dedede board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-
-/*
- * Variant EC defines. Pick one:
- * VARIANT_DEDEDE_EC_NPCX796FC
- */
-#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \
-	defined(VARIANT_KEEBY_EC_NPCX797FC)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* No tach. */
-
-	/* Internal SPI flash on NPCX7 */
-	#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#elif defined(VARIANT_DEDEDE_EC_IT8320) || \
-	defined(VARIANT_KEEBY_EC_IT8320)
-	/* IT83XX config */
-	#define CONFIG_IT83XX_VCC_1P8V
-	/* I2C Bus Configuration */
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_C
-	#define I2C_PORT_SUB_USB_C1	IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_C0		IT83XX_I2C_CH_F
-
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	#define CONFIG_ADC_VOLTAGE_COMPARATOR	/* ITE ADC thresholds */
-
-	#undef CONFIG_UART_TX_BUF_SIZE		/* UART */
-	#define CONFIG_UART_TX_BUF_SIZE 4096
-#else
-#error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!"
-#endif
-
-/*
- * The key difference between Keeby and Dedede is that Keeby variants don't have
- * a connection to H1 and therefore do not use EFS2.
- */
-#if defined(VARIANT_KEEBY_EC_NPCX797FC) || defined(VARIANT_KEEBY_EC_IT8320)
-#define KEEBY_VARIANT 1
-#else
-#define KEEBY_VARIANT 0
-#endif
-
-/*
- * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
- * in the EC code base.
- */
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L		GPIO_EC_AP_MKBP_INT_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_U
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-#if !KEEBY_VARIANT
-#define GPIO_PACKET_MODE_EN	GPIO_ECH1_PACKET_MODE
-#endif
-#define GPIO_PCH_DSW_PWROK	GPIO_EC_AP_DPWROK
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_AP_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_AP_RSMRST_L
-#define GPIO_PCH_RTCRST		GPIO_EC_AP_RTCRST
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_PCH_WAKE_L		GPIO_EC_AP_WAKE_ODL
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_RSMRST_PWRGD_L
-#if KEEBY_VARIANT
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#else
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#endif
-#define GPIO_RSMRST_L_PGOOD	GPIO_RSMRST_PWRGD_L
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_USB_C0_DP_HPD	GPIO_EC_AP_USB_C0_HPD
-#define GPIO_USB_C1_DP_HPD	GPIO_EC_AP_USB_C1_HDMI_HPD
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN_ODL
-#define GPIO_WP			GPIO_EC_WP_OD
-#define GMR_TABLET_MODE_GPIO_L	GPIO_LID_360_L
-
-/* Common EC defines */
-
-/* Work around double CR50 reset by waiting in initial power on. */
-#if !KEEBY_VARIANT
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#endif
-
-/* Optional console commands */
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Enable i2ctrace command */
-#define CONFIG_I2C_DEBUG
-
-/* Assert CCD when a debug device is connected */
-#if !KEEBY_VARIANT
-#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#endif
-
-/* EC Modules */
-#define CONFIG_ADC
-#define CONFIG_CRC8
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_EVENTS
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#if !KEEBY_VARIANT
-#define CONFIG_VBOOT_EFS2
-#endif
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATTERY_PRES_ODL
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/* Buttons / Switches */
-#define CONFIG_SWITCH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* CBI */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#if KEEBY_VARIANT
-#define CONFIG_EEPROM_CBI_WP
-#endif
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 256
-#define CONFIG_USB_CHARGER
-#define CONFIG_TRICKLE_CHARGING
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_MKBP_INPUT_DEVICES
-
-/* Backlight */
-#define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EN_BL_OD
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-
-/* SoC */
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_CHIPSET_JASPERLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-/* USB Type-C */
-#define CONFIG_USB_MUX_PI3USB31532
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Temp Sensor */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO  GPIO_EN_PP3300_A
-#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
-
-/* USB PD */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-/* #define CONFIG_USB_PD_VBUS_DETECT_CHARGER */
-#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
-#define CONFIG_USB_PD_DECODE_SOP
-#if KEEBY_VARIANT
-#define CONFIG_USB_PID 0x5059
-#else
-#define CONFIG_USB_PID 0x5042
-#endif
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-#if !KEEBY_VARIANT
-/* UART COMMAND */
-#define CONFIG_CMD_CHARGEN
-#endif
-
-/* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
-#define PD_OPERATING_POWER_MW 15000
-
-/* TODO(b:147314141): Verify these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-
-#ifndef __ASSEMBLER__
-
-#include "common.h"
-#include "gpio_signal.h"
-
-/* Common enums */
-#if defined(VARIANT_DEDEDE_EC_NPCX796FC)
-#elif defined(VARIANT_DEDEDE_EC_IT8320) || \
-	defined(VARIANT_KEEBY_EC_IT8320)
-	enum board_vcmp {
-		VCMP_SNS_PP3300_LOW,
-		VCMP_SNS_PP3300_HIGH,
-		VCMP_COUNT
-	};
-#endif
-
-/* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */
-void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal);
-
-/* Reset all TCPCs */
-void board_reset_pd_mcu(void);
-
-/*
- * Bit to indicate if the PP3000_A rail's power is good. Will be updated by ADC
- * interrupt.
- */
-extern uint32_t pp3300_a_pgood;
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk
deleted file mode 100644
index 6d7452081e..0000000000
--- a/baseboard/dedede/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o cbi_fw_config.o
-baseboard-$(VARIANT_DEDEDE_EC_NPCX796FC)+=variant_ec_npcx796fc.o
-baseboard-$(VARIANT_KEEBY_EC_NPCX797FC)+=variant_ec_npcx796fc.o
-baseboard-$(VARIANT_DEDEDE_EC_IT8320)+=variant_ec_it8320.o
-baseboard-$(VARIANT_KEEBY_EC_IT8320)+=variant_ec_it8320.o
diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c
deleted file mode 100644
index 27d23733de..0000000000
--- a/baseboard/dedede/cbi_fw_config.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_fw_config.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-/****************************************************************************
- * Dedede CBI FW Configuration
- */
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache FW_CONFIG on init since we don't expect it to change in runtime */
-static uint32_t cached_fw_config;
-
-static void cbi_fw_config_init(void)
-{
-	if (cbi_get_fw_config(&cached_fw_config) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_fw_config = 0;
-
-	CPRINTS("FW_CONFIG: 0x%04X", cached_fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST);
-
-enum fw_config_db get_cbi_fw_config_db(void)
-{
-	return ((cached_fw_config & FW_CONFIG_DB_MASK) >> FW_CONFIG_DB_OFFSET);
-}
-
-enum fw_config_kblight_type get_cbi_fw_config_kblight(void)
-{
-	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK)
-			>> FW_CONFIG_KB_BL_OFFSET);
-}
-
-enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void)
-{
-	return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK)
-			>> FW_CONFIG_TABLET_MODE_OFFSET);
-}
-
-int get_cbi_fw_config_keyboard(void)
-{
-	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK)
-			>> FW_CONFIG_KB_LAYOUT_OFFSET);
-}
-
-enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void)
-{
-	return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK)
-		>> FW_CONFIG_KB_NUMPAD_OFFSET);
-}
-
-enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void)
-{
-	return ((cached_fw_config & FW_CONFIG_HDMI_MASK)
-		>> FW_CONFIG_HDMI_OFFSET);
-}
diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h
deleted file mode 100644
index c9782522fa..0000000000
--- a/baseboard/dedede/cbi_fw_config.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_FW_CONFIG__H_
-#define _DEDEDE_CBI_FW_CONFIG__H_
-
-/****************************************************************************
- * Dedede CBI FW Configuration
- */
-
-/*
- * Daughter Board (Bits 0-3)
- */
-enum fw_config_db {
-	DB_NONE,
-	DB_2C,
-	DB_1C_LTE,
-	DB_1A_HDMI,
-	DB_1C_1A,
-	DB_LTE_HDMI,
-	DB_1C_1A_LTE,
-	DB_1C,
-	DB_1A_HDMI_LTE,
-};
-#define FW_CONFIG_DB_OFFSET			0
-#define FW_CONFIG_DB_MASK			GENMASK(3, 0)
-
-/*
- * Keyboard backlight (1 bit)
- */
-enum fw_config_kblight_type {
-	KB_BL_ABSENT = 0,
-	KB_BL_PRESENT = 1,
-};
-#define FW_CONFIG_KB_BL_OFFSET			8
-#define FW_CONFIG_KB_BL_MASK			GENMASK(8, 8)
-
-/*
- * Keyboard numeric pad (1 bit)
- */
-enum fw_config_numeric_pad_type {
-	NUMERIC_PAD_ABSENT = 0,
-	NUMERIC_PAD_PRESENT = 1,
-};
-#define FW_CONFIG_KB_NUMPAD_OFFSET		9
-#define FW_CONFIG_KB_NUMPAD_MASK		GENMASK(9, 9)
-
-/*
- * Tablet Mode (1 bit)
- */
-enum fw_config_tablet_mode_type {
-	TABLET_MODE_ABSENT = 0,
-	TABLET_MODE_PRESENT = 1,
-};
-#define FW_CONFIG_TABLET_MODE_OFFSET		10
-#define FW_CONFIG_TABLET_MODE_MASK		GENMASK(10, 10)
-
-#define FW_CONFIG_KB_LAYOUT_OFFSET		12
-#define FW_CONFIG_KB_LAYOUT_MASK		GENMASK(13, 12)
-
-/*
- * Hdmi (1 bit)
- */
-enum fw_config_hdmi_type {
-	HDMI_ABSENT = 0,
-	HDMI_PRESENT = 1,
-};
-#define FW_CONFIG_HDMI_OFFSET			17
-#define FW_CONFIG_HDMI_MASK			GENMASK(17, 17)
-
-enum fw_config_db get_cbi_fw_config_db(void);
-enum fw_config_kblight_type get_cbi_fw_config_kblight(void);
-enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void);
-enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void);
-enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void);
-
-int get_cbi_fw_config_keyboard(void);
-
-#endif /* _DEDEDE_CBI_FW_CONFIG__H_ */
diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c
deleted file mode 100644
index 59f07da086..0000000000
--- a/baseboard/dedede/variant_ec_it8320.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_[DEDEDE|KEEBY]_IT8320 configuration */
-
-#include "adc_chip.h"
-#include "atomic.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "power.h"
-#include "registers.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-static void pp3300_a_pgood_low(void)
-{
-	atomic_clear_bits(&pp3300_a_pgood, 1);
-
-	/* Disable low interrupt while asserted */
-	vcmp_enable(VCMP_SNS_PP3300_LOW, 0);
-
-	/* Enable high interrupt */
-	vcmp_enable(VCMP_SNS_PP3300_HIGH, 1);
-
-	/*
-	 * Call power_signal_interrupt() with a fake GPIO in order for the
-	 * chipset task to pick up the change in power sequencing signals.
-	 */
-	power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
-}
-
-static void pp3300_a_pgood_high(void)
-{
-	atomic_or(&pp3300_a_pgood, 1);
-
-	/* Disable high interrupt while asserted */
-	vcmp_enable(VCMP_SNS_PP3300_HIGH, 0);
-
-	/* Enable low interrupt */
-	vcmp_enable(VCMP_SNS_PP3300_LOW, 1);
-
-	/*
-	 * Call power_signal_interrupt() with a fake GPIO in order for the
-	 * chipset task to pick up the change in power sequencing signals.
-	 */
-	power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
-}
-
-const struct vcmp_t vcmp_list[] = {
-	[VCMP_SNS_PP3300_LOW] = {
-		.name = "VCMP_SNS_PP3300_LOW",
-		.threshold = 600, /* mV */
-		.flag = LESS_EQUAL_THRESHOLD,
-		.vcmp_thresh_cb = &pp3300_a_pgood_low,
-		.scan_period = VCMP_SCAN_PERIOD_600US,
-		.adc_ch = CHIP_ADC_CH0,
-	},
-	[VCMP_SNS_PP3300_HIGH] = {
-		.name = "VCMP_SNS_PP3300_HIGH",
-		.threshold = 2700, /* mV */
-		.flag = GREATER_THRESHOLD,
-		.vcmp_thresh_cb = &pp3300_a_pgood_high,
-		.scan_period = VCMP_SCAN_PERIOD_600US,
-		.adc_ch = CHIP_ADC_CH0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(vcmp_list) <= CHIP_VCMP_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT);
-
-/* I2C Ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-#ifdef HAS_TASK_MOTIONSENSE
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
-#endif
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
-#endif
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c
deleted file mode 100644
index 6d9dfb368a..0000000000
--- a/baseboard/dedede/variant_ec_npcx796fc.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_[DEDEDE|KEEBY]_NPCX79[6/7]FC configuration */
-
-#include "adc.h"
-#include "atomic.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-void pp3300_a_pgood_high(void)
-{
-	atomic_or(&pp3300_a_pgood, 1);
-
-	/* Disable this interrupt while it's asserted. */
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0);
-	/* Enable the voltage low interrupt. */
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
-
-	/*
-	 * Call power_signal_interrupt() with a fake GPIO in order for the
-	 * chipset task to pick up the change in power sequencing signals.
-	 */
-	power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
-}
-
-void pp3300_a_pgood_low(void)
-{
-	atomic_clear_bits(&pp3300_a_pgood, 1);
-
-	/* Disable this interrupt while it's asserted. */
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0);
-	/* Enable the voltage high interrupt. */
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
-
-	/*
-	 * Call power_signal_interrupt() with a fake GPIO in order for the
-	 * chipset task to pick up the change in power sequencing signals.
-	 */
-	power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
-}
-
-const struct npcx_adc_thresh_t adc_pp3300_a_pgood_high = {
-	.adc_ch = ADC_VSNS_PP3300_A,
-	.adc_thresh_cb = pp3300_a_pgood_high,
-	.thresh_assert = 2700,
-};
-
-const struct npcx_adc_thresh_t adc_pp3300_a_pgood_low = {
-	.adc_ch = ADC_VSNS_PP3300_A,
-	.adc_thresh_cb = pp3300_a_pgood_low,
-	.lower_or_higher = 1,
-	.thresh_assert = 600,
-};
-
-static void set_up_adc_irqs(void)
-{
-	/* Set interrupt thresholds for the ADC. */
-	npcx_adc_register_thresh_irq(NPCX_ADC_THRESH1,
-				     &adc_pp3300_a_pgood_high);
-	npcx_adc_register_thresh_irq(NPCX_ADC_THRESH2, &adc_pp3300_a_pgood_low);
-	npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 1);
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
-}
-DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1);
-
-static void disable_adc_irqs_deferred(void)
-{
-	CPRINTS("%s", __func__);
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0);
-	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0);
-	npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 0);
-
-	/*
-	 * If we're already in G3, PP3300_A is already off.  Since the ADC
-	 * interrupts were already disabled, this data is stale.  Therefore,
-	 * force the PGOOD value to 0 and have the chipset task re-evaluate.
-	 * This should help prevent leakage.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		pp3300_a_pgood = 0;
-	power_signal_interrupt(GPIO_PG_EC_DSW_PWROK);
-}
-DECLARE_DEFERRED(disable_adc_irqs_deferred);
-
-/*
- * The ADC interrupts are only needed for booting up.  The assumption is that
- * the PP3300_A rail will not go down during runtime.  Therefore, we'll disable
- * the ADC interrupts shortly after booting up and also after shutting down.
- */
-static void disable_adc_irqs(void)
-{
-	int delay = 200 * MSEC;
-
-	/*
-	 * The EC stays in S5 for about 10s after shutting before heading down
-	 * to G3.  Therefore, we'll postpone disabling the ADC IRQs until after
-	 * this occurs.
-	 */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		delay = 15 * SECOND;
-	hook_call_deferred(&disable_adc_irqs_deferred_data, delay);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_adc_irqs, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, disable_adc_irqs, HOOK_PRIO_DEFAULT);
-
-/*
- * We only need the ADC interrupts functional when powering up.  Therefore, only
- * enable them from our wake sources.  These will be the power button, or lid
- * open.  Below is a summary of the ADC interrupt action per power state and
- * wake source.
- *
- * Powering up to S0: ADC interrupts will be disabled after ~200ms.
- * S0ix/S3: No action as ADC interrupts are already disabled if suspending.
- * Powering down to S5/G3: ADC interrupts will be disabled after ~15s.
- * Powering up from S5/G3: ADC interrupts will be enabled.  They will be
- *                         disabled ~200ms after passing thru S3.
- * Power button press: If the system is in S5/G3, ADC interrupts will be
- *                     enabled.
- * Lid open: ADC interrupts will be enabled.
- */
-static void enable_adc_irqs(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		CPRINTS("%s", __func__);
-		hook_call_deferred(&disable_adc_irqs_deferred_data, -1);
-		npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch,
-					1);
-		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
-		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enable_adc_irqs, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, enable_adc_irqs, HOOK_PRIO_DEFAULT);
-
-static void enable_adc_irqs_via_lid(void)
-{
-	if (lid_is_open())
-		enable_adc_irqs();
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT);
-
-/* I2C Ports */
-__attribute__((weak)) const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 1000, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-
-#ifdef HAS_TASK_MOTIONSENSE
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
-#endif
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
-#endif
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c
deleted file mode 100644
index 933fdc0eff..0000000000
--- a/baseboard/goroh/baseboard.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Goroh baseboard-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/it5205.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power_button.h"
-#include "power.h"
-#include "power.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-static void bc12_interrupt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void x_ec_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-static enum board_sub_board board_get_sub_board(void);
-
-/* Wake-up pins for hibernate */
-enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-__override void board_hibernate_late(void)
-{
-	/*
-	 * Turn off PP5000_A. Required for devices without Z-state.
-	 * Don't care for devices with Z-state.
-	 */
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-
-	/*
-	 * GPIO_EN_SLP_Z not implemented in rev0/1,
-	 * fallback to usual hibernate process.
-	 */
-	if (IS_ENABLED(BOARD_GOROH) && board_get_version() <= 1)
-		return;
-
-	isl9238c_hibernate(CHARGER_SOLO);
-
-	gpio_set_level(GPIO_EN_SLP_Z, 1);
-
-	/* should not reach here */
-	__builtin_unreachable();
-}
-
-/* Detect subboard */
-static void board_tcpc_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	/* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */
-	gpio_enable_interrupt(GPIO_X_EC_GPIO2);
-
-	/* If this is not a Type-C subboard, disable the task. */
-	if (board_get_sub_board() != SUB_BOARD_TYPEC)
-		task_disable_task(TASK_ID_PD_C1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* PPC */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	{
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* BC12 */
-const struct mt6360_config_t mt6360_config = {
-	.i2c_port = 0,
-	.i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS,
-};
-
-const struct pi3usb9201_config_t
-		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	/* [0]: unused */
-	[1] = {
-		.i2c_port = 4,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	}
-};
-
-struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{ .drv = &mt6360_drv },
-	{ .drv = &pi3usb9201_drv },
-};
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_BC12_INT_ODL)
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	else
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void board_sub_bc12_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	else
-		/* If this is not a Type-C subboard, disable the task. */
-		task_disable_task(TASK_ID_USB_CHG_P1);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_PPC_INT_ODL)
-		/* C0: PPC interrupt */
-		syv682x_interrupt(0);
-}
-
-/* Sub-board */
-
-static enum board_sub_board board_get_sub_board(void)
-{
-	static enum board_sub_board sub = SUB_BOARD_NONE;
-
-	if (sub != SUB_BOARD_NONE)
-		return sub;
-
-	/* HDMI board has external pull high. */
-	if (gpio_get_level(GPIO_EC_X_GPIO3)) {
-		sub = SUB_BOARD_HDMI;
-		/* Only has 1 PPC with HDMI subboard */
-		ppc_cnt = 1;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH);
-	} else {
-		sub = SUB_BOARD_TYPEC;
-		/* EC_X_GPIO1 */
-		gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW);
-		/* X_EC_GPIO2 */
-		gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL,
-			       GPIO_INT_BOTH | GPIO_PULL_UP);
-		/* EC_X_GPIO3 */
-		gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW);
-	}
-
-	CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC");
-	return sub;
-}
-
-static void sub_board_init(void)
-{
-	board_get_sub_board();
-}
-DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1);
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_BL_EN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* USB-A */
-const int usb_port_enable[] = {
-	GPIO_EN_PP5000_USB_A0_VBUS,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/* USB Mux */
-
-void board_usb_mux_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		ps8743_tune_usb_eq(&usb_muxes[1],
-				   PS8743_USB_EQ_TX_12_8_DB,
-				   PS8743_USB_EQ_RX_12_8_DB);
-}
-DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
-
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-	int reg = 0;
-
-	rv = ps8743_read(me, PS8743_REG_MODE, &reg);
-	if (rv)
-		return rv;
-
-	/* Disable FLIP pin, enable I2C control. */
-	reg |= PS8743_MODE_FLIP_REG_CONTROL;
-	/* Disable CE_USB pin, enable I2C control. */
-	reg |= PS8743_MODE_USB_REG_CONTROL;
-	/* Disable CE_DP pin, enable I2C control. */
-	reg |= PS8743_MODE_DP_REG_CONTROL;
-
-	/*
-	 * DP specific config
-	 *
-	 * Enable/Disable IN_HPD on the DB.
-	 */
-	gpio_set_level(GPIO_USB_C1_DP_IN_HPD,
-		       mux_state & USB_PD_MUX_DP_ENABLED);
-
-	return ps8743_write(me, PS8743_REG_MODE, reg);
-}
-
-const struct usb_mux usbc0_virtual_mux = {
-	.usb_port = 0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usbc1_virtual_mux = {
-	.usb_port = 1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc0_virtual_mux,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_virtual_mux,
-		.board_set = &board_ps8743_mux_set,
-	},
-};
-
-/*
- * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
- * at default.
- * In order to set frequency independently for each channels,
- * We use timing registers 09h~0Bh, and the supported frequency will be:
- * 50KHz, 100KHz, 400KHz, or 1MHz.
- * I2C channels (D, E and F) can be set different frequency on different ports.
- * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
- * the individual prescale register.
- * The frequency of SMBus module is 24MHz on default.
- * The allowed range of I2C(D/E/F) frequency is as following setting.
- * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
- * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
- * Channel D has multi-function and can be used as UART interface.
- * Channel F is reserved for EC debug.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"bat_chg",  IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-	{"sensor",   IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"usb0",     IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"usb1",     IT83XX_I2C_CH_E, 400, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO: check correct operation for GOROH */
-}
-
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
-{
-	const static struct cc_para_t
-		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-	};
-
-	return &cc_parameter[port];
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-	return 0;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
-	 * chip code (it83xx/intc.c)
-	 */
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin and PPC vconn because polarity and PPC vconn
-	 * should already be set correctly in the PPC driver via the pd
-	 * state machine.
-	 */
-}
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-	int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() ==
-							       SUB_BOARD_TYPEC);
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Handle PS185 HPD changing state.
- */
-int debounced_hpd;
-
-static void ps185_hdmi_hpd_deferred(void)
-{
-	const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD);
-
-	/* HPD status not changed, probably a glitch, just return. */
-	if (debounced_hpd == new_hpd)
-		return;
-
-	debounced_hpd = new_hpd;
-
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd);
-	CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug");
-}
-DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
-
-#define PS185_HPD_DEBOUCE 250
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE);
-}
-
-/* HDMI/TYPE-C function shared subboard interrupt */
-static void x_ec_interrupt(enum gpio_signal signal)
-{
-	int sub = board_get_sub_board();
-
-	if (sub == SUB_BOARD_TYPEC)
-		/* C1: PPC interrupt */
-		syv682x_interrupt(1);
-	else if (sub == SUB_BOARD_HDMI)
-		hdmi_hpd_interrupt(signal);
-	else
-		CPRINTS("Undetected subboard interrupt.");
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-/* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
-}
-
-int board_regulator_enable(uint32_t index, uint8_t enable)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_enable(id, enable);
-}
-
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_is_enabled(id, enabled);
-}
-
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
-}
-
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_voltage(id, voltage_mv);
-}
-
-static void baseboard_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1);
diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h
deleted file mode 100644
index 55fa0ffab7..0000000000
--- a/baseboard/goroh/baseboard.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Goroh board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* IT81202-bx config */
-/*
- * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't
- * connect to 1.8v on other versions.
- */
-#define CONFIG_IT83XX_VCC_1P8V
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_CHIPSET_MT8192
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-
-/* Chipset */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_COMMON
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* BC12 */
-#define CONFIG_BC12_DETECT_MT6360
-#define CONFIG_BC12_DETECT_PI3USB9201
-#undef CONFIG_BC12_SINGLE_DRIVER
-#define CONFIG_USB_CHARGER
-
-/* Charger */
-#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */
-#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */
-#define ADC_VBUS ADC_VBUS_C0 /* ADC name remap */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238C
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-
-/* Keyboard */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* I2C */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
-#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0  IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1  IT83XX_I2C_CH_E
-#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define CONFIG_SMBUS_PEC
-
-/* LED */
-#define CONFIG_LED_COMMON
-
-/* PD / USB-C / PPC */
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_IT83XX_TUNE_CC_PHY
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_SYV682C
-#define CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_MUX_IT5205 /* C0 */
-#define CONFIG_USB_MUX_PS8743 /* C1 */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FRS_PPC
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#define CONFIG_USB_PID 0x5566  /* TODO: update PID */
-#define CONFIG_USB_POWER_DELIVERY
-
-#define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_VOLTAGE_MV 20000
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW 60000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* USB-A */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT USBA_PORT_COUNT
-
-/* UART */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Sensor */
-#ifdef HAS_TASK_MOTIONSENSE
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_ACCELS
-
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
-#endif
-
-/* SPI / Host Command */
-#define CONFIG_SPI
-
-/* MKBP */
-#define CONFIG_MKBP_EVENT
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_USE_GPIO
-
-/* Voltage regulator control */
-#define CONFIG_HOSTCMD_REGULATOR
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* GPIO name remapping */
-#define GPIO_EN_HDMI_PWR        GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_FRS_EN      GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2
-#define GPIO_PS185_EC_DP_HPD    GPIO_X_EC_GPIO2
-#define GPIO_USB_C1_DP_IN_HPD   GPIO_EC_X_GPIO3
-#define GPIO_PS185_PWRDN_ODL    GPIO_EC_X_GPIO3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-#include "power/mt8192.h"
-
-enum board_sub_board {
-	SUB_BOARD_NONE = -1,
-	SUB_BOARD_TYPEC,
-	SUB_BOARD_HDMI,
-	SUB_BOARD_COUNT,
-};
-
-int board_get_version(void);
-void board_reset_pd_mcu(void);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c
deleted file mode 100644
index a8bee6d412..0000000000
--- a/baseboard/goroh/board_id.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "util.h"
-
-/**
- * Conversion based on following table:
- *
- * ID | Rp   | Rd   | Voltage
- *    | kOhm | kOhm | mV
- * ---+------+------+--------
- *  0 | 51.1 |  2.2 | 136.2
- *  1 | 51.1 | 6.81 | 388.1
- *  2 | 51.1 |   11 | 584.5
- *  3 | 57.6 |   18 | 785.7
- *  4 | 51.1 |   22 | 993.2
- *  5 | 51.1 |   30 | 1220.7
- *  6 | 51.1 | 39.2 | 1432.6
- *  7 |   56 |   56 | 1650.0
- *  8 |   47 | 61.9 | 1875.8
- *  9 |   47 | 80.6 | 2084.5
- * 10 |   56 |  124 | 2273.3
- * 11 | 51.1 |  150 | 2461.5
- * 12 |   47 |  200 | 2672.1
- * 13 |   47 |  330 | 2888.6
- * 14 |   47 |  680 | 3086.7
- */
-const static int voltage_map[] = {
-	136,
-	388,
-	584,
-	785,
-	993,
-	1220,
-	1432,
-	1650,
-	1875,
-	2084,
-	2273,
-	2461,
-	2672,
-	2888,
-	3086,
-};
-
-const int threshold_mv = 100;
-
-/**
- * Convert ADC value to board id using the voltage table above.
- *
- * @param ch	ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1.
- *
- * @return	a non-negative board id, or negative value if error.
- */
-static int adc_value_to_numeric_id(enum adc_channel ch)
-{
-	int mv;
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
-	/* Wait to allow cap charge */
-	msleep(10);
-
-	mv = adc_read_channel(ch);
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ch);
-
-	gpio_set_level(GPIO_EN_EC_ID_ODL, 1);
-
-	if (mv == ADC_READ_ERROR)
-		return -EC_ERROR_UNKNOWN;
-
-	for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) {
-		if (IN_RANGE(mv, voltage_map[i] - threshold_mv,
-			     voltage_map[i] + threshold_mv))
-			return i;
-	}
-
-	return -EC_ERROR_UNKNOWN;
-}
-
-static int version = -1;
-
-/* b/163963220: Cache ADC value before board_hibernate_late() reads it */
-static void board_version_init(void)
-{
-	version = adc_value_to_numeric_id(ADC_BOARD_ID_0);
-	if (version < 0) {
-		ccprints("WARN:BOARD_ID_0");
-		ccprints("Assuming board id = 0");
-
-		version = 0;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1);
-
-int board_get_version(void)
-{
-	return version;
-}
diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk
deleted file mode 100644
index 58e9934bc0..0000000000
--- a/baseboard/goroh/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o board_id.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c
deleted file mode 100644
index 72213d311c..0000000000
--- a/baseboard/goroh/usb_pd_policy.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "charge_manager.h"
-#include "chipset.h"
-#include "timer.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#if CONFIG_USB_PD_3A_PORTS != 1
-#error Goroh reference must have at least one 3.0 A port
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-int svdm_get_hpd_gpio(int port)
-{
-	/* HPD is low active, inverse the result */
-	return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL);
-}
-
-void svdm_set_hpd_gpio(int port, int en)
-{
-	/*
-	 * HPD is low active, inverse the en
-	 * TODO: C0&C1 shares the same HPD, implement FCFS policy.
-	 */
-	gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en);
-}
-
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-	}
-
-	return 1;
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (!is_dp_muxable(port)) {
-		/* TODO(waihong): Info user? */
-		CPRINTS("p%d: The other port is already muxed.", port);
-		return 0; /* nak */
-	}
-
-	if (lvl)
-		gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port);
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry(port);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq && !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq && cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		/*
-		 * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is
-		 * very short (500us), we can use udelay instead of usleep for
-		 * more stable pulse period.
-		 */
-		udelay(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(yllin): check SNK VBUS detection */
-	return ppc_is_vbus_present(port);
-
-	/*
-	 * (b:181203590#comment20) TODO(yllin): use
-	 *  PD_VSINK_DISCONNECT_PD for non-5V case.
-	 */
-	return charge_manager_get_vbus_voltage(port) >=
-	       PD_V_SINK_DISCONNECT_MAX;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow Vconn swap if AP is on. */
-	return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/grunt/analyzestack.yaml b/baseboard/grunt/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/baseboard/grunt/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c
deleted file mode 100644
index cf49fc0566..0000000000
--- a/baseboard/grunt/baseboard.c
+++ /dev/null
@@ -1,815 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Grunt family-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/bc12/max14637.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		"SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_VBUS] = {
-		"VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID1] = {
-		"SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID2] = {
-		"SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PCH_SLP_S3_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"},
-	{GPIO_PCH_SLP_S5_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"},
-	{GPIO_S0_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"},
-	{GPIO_S5_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-	[USB_PD_PORT_ANX74XX] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-		/* Alert is active-low, open-drain */
-		.flags = TCPC_FLAGS_ALERT_OD,
-	},
-#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
-	[USB_PD_PORT_ANX74XX] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-#endif
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-#endif
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
-		if (!gpio_get_level(GPIO_USB_C0_PD_RST))
-#endif
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX74XX)
-		return;
-
-	switch (mode) {
-	case ANX74XX_NORMAL_MODE:
-		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-		break;
-	case ANX74XX_STANDBY_MODE:
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		break;
-	default:
-		break;
-	}
-}
-#endif /* VARIANT_GRUNT_TCPC_0_ANX3429 */
-
-void board_reset_pd_mcu(void)
-{
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-	/* Assert reset to TCPC1 (ps8751) */
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-
-	/* Assert reset to TCPC0 (anx3429) */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-
-	/* TCPC1 (ps8751) requires 1ms reset down assertion */
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-
-	/* Deassert reset to TCPC1 */
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	/* Disable TCPC0 power */
-	gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
-
-	/*
-	 * anx3429 requires 10ms reset/power down assertion
-	 */
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
-#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
-	/* Assert reset to TCPC0 (anx3447) */
-	gpio_set_level(GPIO_USB_C0_PD_RST, 1);
-	msleep(ANX74XX_RESET_HOLD_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST, 0);
-	msleep(ANX74XX_RESET_FINISH_MS);
-
-	/* Assert reset to TCPC1 (ps8751) */
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-#endif
-}
-
-static uint32_t sku_id;
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* Tune USB mux registers for treeya's port 1 Rx measurement */
-	if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) ||
-	   sku_id == 0xbe || sku_id == 0xbf)
-		mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40);
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
-	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-#endif
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
-
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	int port = (signal == GPIO_USB_C0_SWCTL_INT_ODL) ? 0 : 1;
-
-	sn5s330_interrupt(port);
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_SWCTL_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_SWCTL_INT_ODL) == 0;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L
-					      : GPIO_USB_C1_OC_L;
-	/* Note that the levels are inverted because the pin is active low. */
-	int lvl = is_overcurrented ? 0 : 1;
-
-	gpio_set_level(signal, lvl);
-
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-/* BC 1.2 chip Configuration */
-const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_L,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_L,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-};
-
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_5V,
-	GPIO_EN_USB_A1_5V,
-};
-
-static void baseboard_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight. This ensures that the backlight stays off
-	 * in S3, no matter what the AP has it set to. The AP also controls it.
-	 * This is here more for legacy reasons.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_resume(void)
-{
-	/* Allow display backlight to turn on. See above backlight comment */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0);
-
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_startup(void)
-{
-	/*
-	 * Enable sensor power (lid accel, gyro) in S3 for calculating the lid
-	 * angle (needed on convertibles to disable resume from keyboard in
-	 * tablet mode).
-	 */
-	gpio_set_level(GPIO_EN_PP1800_SENSOR, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_shutdown(void)
-{
-	/* Disable sensor power (lid accel, gyro) in S5. */
-	gpio_set_level(GPIO_EN_PP1800_SENSOR, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
-int board_is_i2c_port_powered(int port)
-{
-	if (port != I2C_PORT_SENSOR)
-		return 1;
-
-	/* Sensor power (lid accel, gyro) is off in S5 (and G3). */
-	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
-}
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-
-	CPRINTS("New chg p%d", port);
-
-	if (port == CHARGE_PORT_NONE) {
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTS("p%d: sink disable failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTF("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 95% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/*
- * We use 11 as the scaling factor so that the maximum mV value below (2761)
- * can be compressed to fit in a uint8_t.
- */
-#define THERMISTOR_SCALING_FACTOR 11
-
-/*
- * Values are calculated from the "Resistance VS. Temperature" table on the
- * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
- */
-static const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
-};
-
-static const struct thermistor_info thermistor_info = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR,
-	.num_pairs = ARRAY_SIZE(thermistor_data),
-	.data = thermistor_data,
-};
-
-static int board_get_temp(int idx, int *temp_k)
-{
-	/* idx is the sensor index set below in temp_sensors[] */
-	int mv = adc_read_channel(
-		idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER);
-	int temp_c;
-
-	if (mv < 0)
-		return -1;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return 0;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0},
-	{"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1},
-	{"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-#ifdef HAS_TASK_MOTIONSENSE
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = NULL,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* HAS_TASK_MOTIONSENSE */
-
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-static const int sku_thresh_mv[] = {
-	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
-	/* R1 = 51.1 kOhm */
-	200,  /* 124 mV, 2.0 Kohm */
-	366,  /* 278 mV, 4.7 Kohm */
-	550,  /* 456 mV, 8.2  Kohm */
-	752,  /* 644 mV, 12.4 Kohm */
-	927,  /* 860 mV, 18.0 Kohm */
-	1073, /* 993 mV, 22.0 Kohm */
-	1235, /* 1152 mV, 27.4 Kohm */
-	1386, /* 1318 mV, 34.0 Kohm */
-	1552, /* 1453 mV, 40.2 Kohm */
-	/* R1 = 10.0 kOhm */
-	1739, /* 1650 mV, 10.0 Kohm */
-	1976, /* 1827 mV, 12.4 Kohm */
-	2197, /* 2121 mV, 18.0 Kohm */
-	2344, /* 2269 mV, 22.0 Kohm */
-	2484, /* 2418 mV, 27.4 Kohm */
-	2636, /* 2550 mV, 34.0 Kohm */
-	2823, /* 2721 mV, 47.0 Kohm */
-};
-
-static int board_read_sku_adc(enum adc_channel chan)
-{
-	int mv;
-	int i;
-
-	mv = adc_read_channel(chan);
-
-	if (mv == ADC_READ_ERROR)
-		return -1;
-
-	for (i = 0; i < ARRAY_SIZE(sku_thresh_mv); i++)
-		if (mv < sku_thresh_mv[i])
-			return i;
-
-	return -1;
-}
-
-static uint32_t board_get_adc_sku_id(void)
-{
-	int sku_id1, sku_id2;
-
-	sku_id1 = board_read_sku_adc(ADC_SKU_ID1);
-	sku_id2 = board_read_sku_adc(ADC_SKU_ID2);
-
-	if (sku_id1 < 0 || sku_id2 < 0)
-		return 0;
-
-	return (sku_id2 << 4) | sku_id1;
-}
-
-static int board_get_gpio_board_version(void)
-{
-	return
-		(!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
-}
-
-static int board_version;
-
-static void cbi_init(void)
-{
-	board_version = board_get_gpio_board_version();
-	sku_id = board_get_adc_sku_id();
-
-	/*
-	 * Use board version and SKU ID from CBI EEPROM if the board supports
-	 * it and the SKU ID set via resistors + ADC is not valid.
-	 */
-#ifdef CONFIG_CBI_EEPROM
-	if (sku_id == 0 || sku_id == 0xff) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) == EC_SUCCESS)
-			board_version = val;
-		if (cbi_get_sku_id(&val) == EC_SUCCESS)
-			sku_id = val;
-	}
-#endif
-
-#ifdef HAS_TASK_MOTIONSENSE
-	board_update_sensor_config_from_sku();
-#endif
-
-	ccprints("Board Version: %d (0x%x)", board_version, board_version);
-	ccprints("SKU: %d (0x%x)", sku_id, sku_id);
-}
-/*
- * Reading the SKU resistors requires the ADC module. If we are using EEPROM
- * then we also need the I2C module, but that is available before ADC.
- */
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_ADC + 1);
-
-__override uint32_t board_get_sku_id(void)
-{
-	return sku_id;
-}
-
-int board_get_version(void)
-{
-	return board_version;
-}
-
-/*
- * Returns 1 for boards that are convertible into tablet mode, and zero for
- * clamshells.
- */
-int board_is_convertible(void)
-{
-	/* Grunt: 6 */
-	/* Kasumi360: 82 */
-	/* Treeya360: a8-af, be, bf*/
-	return (sku_id == 6 || sku_id == 82 ||
-		((sku_id >= 0xa8) && (sku_id <= 0xaf)) ||
-		sku_id == 0xbe || sku_id == 0xbf);
-}
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return board_is_convertible();
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 * All Treeya and Treeya360 models do not support keyboard backlight.
-	 */
-	if (sku_id == 16 || sku_id == 17 ||
-	    sku_id == 20 || sku_id == 21 ||
-	    sku_id == 32 || sku_id == 33 ||
-	    sku_id == 40 || sku_id == 41 ||
-	    sku_id == 44 || sku_id == 45 ||
-	    ((sku_id >= 0xa0) && (sku_id <= 0xaf)) ||
-		sku_id == 0xbe || sku_id == 0xbf)
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Some versions of some boards keep the port 0 PPC powered on while
-	 * the EC hibernates (so Closed Case Debugging keeps working).
-	 * Make sure the source FET is off and turn on the sink FET, so that
-	 * plugging in AC will wake the EC. This matches the dead-battery
-	 * behavior of the powered off PPC.
-	 */
-	ppc_vbus_source_enable(0, 0);
-	ppc_vbus_sink_enable(0, 1);
-
-	/*
-	 * If CCD not active, set port 0 SBU_EN=0 to avoid power leakage during
-	 * hibernation (b/175674973).
-	 */
-	if (gpio_get_level(GPIO_CCD_MODE_ODL))
-		ppc_set_sbu(0, 0);
-}
diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h
deleted file mode 100644
index c97ece285f..0000000000
--- a/baseboard/grunt/baseboard.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Grunt family-specific configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \
-	+ defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1
-#error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447
-#endif
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Internal SPI flash on NPCX7 */
-/* Flash is 1MB but reserve half for future use. */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_HOSTCMD_SKUID
-#define CONFIG_I2C
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-#define CONFIG_BC12_DETECT_MAX14637
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-
-/*
- * This limit impairs compatibility with BC1.2 chargers that are not actually
- * capable of supplying 500 mA of current.  When the charger is paralleled with
- * the battery, raising this limit allows the power system to draw more current
- * from the charger during startup.  This improves compatibility with system
- * batteries that may become excessively imbalanced after extended periods of
- * rest.
- *
- * See also b/111214767
- */
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_USB_CHARGER
-
-#define CONFIG_CHIPSET_STONEY
-#define CONFIG_CHIPSET_RESET_HOOK
-/*
- * ACOK from ISL9238 sometimes has a negative pulse after connecting
- * USB-C power. We want to ignore it. b/77455171
- */
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#ifdef VARIANT_GRUNT_TCPC_0_ANX3429
-#define CONFIG_USB_PD_TCPM_ANX3429
-#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
-#define CONFIG_USB_PD_TCPM_ANX7447
-#endif
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT 2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Require PD negotiation to be complete when we are in a low-battery condition
- * prior to releasing depthcharge to the kernel.
- */
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15001
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3
-
-/* Increase length of history buffer for port80 messages. */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT3_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
-/* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* Thermal */
-#define CONFIG_TEMP_SENSOR_SB_TSI
-
-#ifndef VARIANT_GRUNT_NO_SENSORS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#endif /* VARIANT_GRUNT_NO_SENSORS */
-
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "math_util.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_VBUS,
-	ADC_SKU_ID1,
-	ADC_SKU_ID2,
-	ADC_CH_COUNT
-};
-
-enum power_signal {
-	X86_SLP_S3_N,
-	X86_SLP_S5_N,
-	X86_S0_PGOOD,
-	X86_S5_PGOOD,
-	POWER_SIGNAL_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-/*
- * Matrix to rotate accelerators into the standard reference frame.  The default
- * is the identity which is correct for the reference design.  Variations of
- * Grunt may need to change it for manufacturability.
- * For the lid:
- *  +x to the right
- *  +y up
- *  +z out of the page
- *
- * The principle axes of the body are aligned with the lid when the lid is in
- * the 180 degree position (open, flat).
- *
- * Boards within the Grunt family may need to modify this definition at
- * board_init() time.
- */
-extern mat33_fp_t grunt_base_standard_ref;
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void anx74xx_cable_det_interrupt(enum gpio_signal signal);
-
-int board_get_version(void);
-int board_is_convertible(void);
-void board_update_sensor_config_from_sku(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/grunt/build.mk b/baseboard/grunt/build.mk
deleted file mode 100644
index cb9d607c36..0000000000
--- a/baseboard/grunt/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c
deleted file mode 100644
index 7c4fff953c..0000000000
--- a/baseboard/grunt/usb_pd_policy.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Grunt boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since 5V rail is off */
-	return gpio_get_level(GPIO_S5_PGOOD);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-mux_state_t svdm_dp_mux_mode(int port)
-{
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	/*
-	 * Multi-function operation is only allowed if that pin config is
-	 * supported.
-	 */
-	if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref)
-		return USB_PD_MUX_DOCK;
-	else
-		return USB_PD_MUX_DP_ENABLED;
-}
-
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	mux_state_t mux_mode = svdm_dp_mux_mode(port);
-
-	if (!pin_mode)
-		return 0;
-
-	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
-
-	/*
-	 * Place the USB Type-C pins that are to be re-configured to DisplayPort
-	 * Configuration into the Safe state. For USB_PD_MUX_DOCK, the
-	 * superspeed signals can remain connected. For USB_PD_MUX_DP_ENABLED,
-	 * disconnect the superspeed signals here, before the pins are
-	 * re-configured to DisplayPort (in svdm_dp_post_config, when we receive
-	 * the config ack).
-	 */
-	if (mux_mode == USB_PD_MUX_DP_ENABLED)
-		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
-__override void svdm_dp_post_config(int port)
-{
-	/* Connect the SBU and USB lines to the connector. */
-	ppc_set_sbu(port, 1);
-	usb_mux_set(port, svdm_dp_mux_mode(port), USB_SWITCH_CONNECT,
-		    polarity_rm_dts(pd_get_polarity(port)));
-
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	gpio_set_level(PORT_TO_HPD(port), 1);
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h
deleted file mode 100644
index 2eea7a158f..0000000000
--- a/baseboard/guybrush/base_fw_config.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _GUYBRUSH_BASE_FW_CONFIG__H_
-#define _GUYBRUSH_BASE_FW_CONFIG__H_
-
-#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/*
- * Takes a bit offset and bit width and returns the fw_config field at that
- * offset and width. Returns -1 if an error occurs.
- */
-int get_fw_config_field(uint8_t offset, uint8_t width);
-
-/*
- * Each Guybrush board variant will define a board specific fw_config schema.
- * Below is the schema agnostic interface for fw_config fields.
- * Fields that are not applicable outside a specific Guybrush variant do not
- * need to be included here.
- */
-
-enum board_usb_a1_retimer {
-	USB_A1_RETIMER_UNKNOWN,
-	USB_A1_RETIMER_PS8811,
-	USB_A1_RETIMER_ANX7491
-};
-
-enum board_usb_c1_mux {
-	USB_C1_MUX_UNKNOWN,
-	USB_C1_MUX_PS8818,
-	USB_C1_MUX_ANX7451
-};
-
-enum board_form_factor {
-	FORM_FACTOR_UNKNOWN,
-	FORM_FACTOR_CLAMSHELL,
-	FORM_FACTOR_CONVERTIBLE
-};
-
-bool board_has_kblight(void);
-enum board_usb_a1_retimer board_get_usb_a1_retimer(void);
-enum board_usb_c1_mux board_get_usb_c1_mux(void);
-enum board_form_factor board_get_form_factor(void);
-bool board_is_convertible(void);
-
-#endif /* _GUYBRUSH_BASE_FW_CONFIG__H_ */
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc
deleted file mode 100644
index 259ccd9286..0000000000
--- a/baseboard/guybrush/base_gpio.inc
+++ /dev/null
@@ -1,150 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GSC Signals */
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)	/* Write Protect Enabled */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_ODR_HIGH)						/* Case Closed Debug Mode */
-GPIO(EC_GSC_PACKET_MODE,	PIN(B, 1), GPIO_OUT_LOW)						/* GSC Packet Mode */
-ALTERNATE(			PIN_MASK(6, BIT(4) | BIT(5)), 0,		MODULE_UART, 0) 	/* UART_EC_TX_GSC_DBG_RX_R, UART_GSC_DBG_TX_EC_RX_R */
-
-/* Power Signals */
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, 	power_button_interrupt)	/* Mechanical Power Button */
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH, 			power_button_interrupt) /* Power Button */
-GPIO_INT(SLP_S3_L,		PIN(6, 1), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* Sleep S3 */
-GPIO_INT(SLP_S5_L,		PIN(7, 2), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S5 */
-GPIO_INT(SLP_S3_S0I3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S0ix */
-GPIO_INT(PG_PWR_S5,		PIN(C, 0), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* S5 Power OK */
-GPIO_INT(PG_PCORE_S0_R_OD,	PIN(B, 6), GPIO_INT_BOTH, 			power_signal_interrupt) /* S0 Power OK */
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)	/* AC Power Present */
-GPIO_INT(EC_PCORE_INT_ODL,	PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)	/* Power Core Interrupt */
-GPIO_INT(PG_GROUPC_S0_OD,	PIN(A, 3), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group C S0 */
-GPIO_INT(PG_LPDDR4X_S3_OD,	PIN(9, 5), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group LPDDR4 S3 */
-GPIO(EN_PWR_S5,			PIN(B, 7), GPIO_OUT_LOW)						/* Enable S5 Power */
-GPIO(EN_PWR_S0_R,		PIN(F, 1), GPIO_OUT_LOW)
-GPIO(EN_PWR_PCORE_S0_R,		PIN(E, 1), GPIO_OUT_LOW)
-ALTERNATE(/*MECH_PWR_BTN_ODL*/	PIN_MASK(D, BIT(2)), 0,				MODULE_PMU, 0)		/* PSL - Mechanical Power Button */
-ALTERNATE(/*LID_OPEN*/		PIN_MASK(0, BIT(2)), 0, 			MODULE_PMU, 0)		/* PSL - Lid Open */
-ALTERNATE(/*ACOK_OD*/		PIN_MASK(0, BIT(0)), 0,				MODULE_PMU, 0)		/* PSL - AC Power Present */
-
-/* SOC Signals */
-GPIO(EC_ENTERING_RW,		PIN(6, 6), GPIO_OUT_LOW) 						/* Tell SOC we entered RW */
-GPIO(EC_SYS_RST_L,		PIN(7, 6), GPIO_ODR_HIGH)						/* Cold Reset SOC */
-GPIO(EC_SOC_RSMRST_L,		PIN(C, 5), GPIO_OUT_LOW)						/* Resume Reset SOC */
-GPIO(EC_CLR_CMOS,		PIN(A, 1), GPIO_OUT_LOW)						/* Clear SOC CMOS */
-GPIO(EC_MEM_EVENT,		PIN(A, 5), GPIO_OUT_LOW)						/* Memory Thermal Event to SOC*/
-GPIO(EC_SOC_PWR_BTN_L,		PIN(6, 3), GPIO_OUT_HIGH)						/* Power Button to SOC */
-GPIO(EC_SOC_PWR_GOOD,		PIN(D, 3), GPIO_OUT_LOW)						/* Power Good to SOC */
-GPIO(EC_SOC_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)						/* Wake SOC */
-GPIO(EC_SOC_INT_L,		PIN(8, 3), GPIO_OUT_HIGH)						/* Matrix Keyboard Protocol Event to SOC */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)						/* Force SOC into HTC-active state */
-GPIO(SOC_ALERT_EC_L,		PIN(E, 2), GPIO_INPUT)							/* Sideband-Temperature Iterrupt */
-GPIO(SOC_THERMTRIP_ODL, 	PIN(E, 5), GPIO_INPUT)							/* Temperature Trip Sensor */
-
-/* USB Signals */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(C, 7), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(7, 5), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(9, 6), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO(USB_C0_C1_FAULT_ODL,	PIN(7, 3), GPIO_ODR_HIGH)						/* C0/C1 Fault to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(3, 4), GPIO_OUT_HIGH)						/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(3, 7), GPIO_OUT_HIGH)						/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)						/* C0 DP Hotplug Detect */
-GPIO(USB_C1_HPD,		PIN(F, 4), GPIO_OUT_LOW)						/* C1 DP Hotplug Detect */
-
-/* Sensor Signals */
-GPIO(3AXIS_INT_L,		PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)					/* 3 Axis Accel */
-GPIO_INT(LID_OPEN,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)		/* Lid Open */
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)	/* Volume Down */
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, 	button_interrupt)	/* Volume Up */
-GPIO(EC_BATT_PRES_ODL,		PIN(9, 4), GPIO_INPUT)							/* Battery Present */
-ALTERNATE(/*TEMP_SOC|CHRG|MEM*/	PIN_MASK(4, BIT(3) | BIT(4) | BIT(5)), 0, 	MODULE_ADC, 0)		/* SOC, Charger and Memory Temperature */
-ALTERNATE(			PIN_MASK(4, BIT(1) | BIT(2)), 0,		MODULE_ADC, 0)		/* EC_ADC_CORE_IMON1, EC_ADC_SOC_IMON2 */
-
-/* LED Signals */
-GPIO(EC_DISABLE_DISP_BL,	PIN(A, 6), GPIO_OUT_HIGH)						/* Disable Display Backlight */
-
-/* Fan Signals */
-ALTERNATE(			PIN_MASK(C, BIT(3)), 0, 			MODULE_PWM, 0)		/* EC_FAN_PWM - Fan PWM */
-ALTERNATE(			PIN_MASK(4, BIT(0)), 0, 			MODULE_PWM, 0)		/* EC_FAN_SPEED - Fan Speed */
-
-/* I2C Signals -- i2c pins need to be exposed as GPIO for bit banging, even though set to alternate mode below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_CBI_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_CBI_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SOC_SIC,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_SOC_SID,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(			PIN_MASK(B, BIT(4) | BIT(5)), 0, 		MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(			PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, 	MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(			PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(			PIN_MASK(D, BIT(0) | BIT(1)), 0, 		MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(			PIN_MASK(F, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(			PIN_MASK(3, BIT(3) | BIT(6)), 0, 		MODULE_I2C, 0)		/* I2C5 */
-ALTERNATE(			PIN_MASK(E, BIT(3) | BIT(4)), 0, 		MODULE_I2C, 0)		/* I2C6 */
-ALTERNATE(			PIN_MASK(B, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C7 */
-
-/* Keyboard Signals */
-GPIO(EN_KB_BL, 			PIN(9, 7), GPIO_OUT_HIGH)						/* Enable Keyboard Backlight */
-ALTERNATE(/*PWM_KB_BL*/ 	PIN_MASK(C, BIT(2)), 0, 			MODULE_PWM, 0)		/* Keyboard Backlight Level */
-ALTERNATE(/*KSI_00-01*/		PIN_MASK(3, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_INPUT)
-ALTERNATE(/*KSI_02-07*/		PIN_MASK(2, GENMASK(7, 2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_INPUT)
-ALTERNATE(/*KSO_00-01*/		PIN_MASK(2, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-GPIO(EC_KSO_02_INV, 		PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(/*KSO_03-09*/		PIN_MASK(1, GENMASK(6, 0)), 0,			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-ALTERNATE(/*KSO_10-13*/		PIN_MASK(0, GENMASK(7, 4)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-ALTERNATE(/*KSO_14*/		PIN_MASK(8, BIT(2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-
-/* b/186135022: Pull eSPI RST# high to disable */
-GPIO(EC_ESPI_RST_L,		PIN(5, 4), GPIO_PULL_UP)
-
-#if 0
-/*
- * SOC eSPI Bus
- * These signals do not need to be explicitly configured.
- * Leaving here so all signals are documented.
- */
-GPIO(ESPI_SOC_CLK,		PIN(5, 5), GPIO_DEFAULT)
-GPIO(ESPI_SOC_CS_EC_L,		PIN(5, 3), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D0_EC,		PIN(4, 6), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D1_EC,		PIN(4, 7), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D2_EC,		PIN(5, 1), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D3_EC,		PIN(5, 2), GPIO_DEFAULT)
-GPIO(ESPI_EC_ALERT_SOC_L,	PIN(5, 7), GPIO_DEFAULT)
-#endif
-
-/* TCPC C0 */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)
-IOEX(USB_C0_PPC_EN_L,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_LOW)
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-IOEX(EN_PP5000_USB_A0_VBUS,	EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)
-IOEX(USB_A0_LIMIT_SDP,		EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_LOW)
-IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)
-
-/* TCPC C1 */
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)
-IOEX(USB_A1_RETIMER_RST,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)
-IOEX(USB_C1_IN_HPD,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_LOW)
-IOEX(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)
-IOEX_INT(USB_C1_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-IOEX(EN_PP5000_USB_A1_VBUS_DB,	EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_LOW)
-IOEX(USB_A1_LIMIT_SDP_DB,	EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c
deleted file mode 100644
index 344ea459de..0000000000
--- a/baseboard/guybrush/baseboard.c
+++ /dev/null
@@ -1,894 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush family-specific configuration */
-
-#include "cros_board_info.h"
-#include "base_fw_config.h"
-#include "battery_fuel_gauge.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chip/npcx/ps2_chip.h"
-#include "chip/npcx/pwm_chip.h"
-#include "chipset.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/anx7491.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/anx7451.h"
-#include "driver/usb_mux/amd_fp6.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "isl9241.h"
-#include "keyboard_scan.h"
-#include "nct38xx.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "pwm.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void reset_nct38xx_port(int port);
-
-/* Wake Sources */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* Power Signal Input List */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_N] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
-		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
-		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
-	},
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BATT_SCL,
-		.sda = GPIO_EC_I2C_BATT_SDA,
-	},
-	{
-		.name = "usb_mux",
-		.port = I2C_PORT_USB_MUX,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USBC_MUX_SCL,
-		.sda = GPIO_EC_I2C_USBC_MUX_SDA,
-	},
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_POWER_SCL,
-		.sda = GPIO_EC_I2C_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_CBI_SCL,
-		.sda = GPIO_EC_I2C_CBI_SDA,
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		.name = "soc_thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SOC_SIC,
-		.sda = GPIO_EC_I2C_SOC_SID,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_PP5000_USB_A0_VBUS,
-	IOEX_EN_PP5000_USB_A1_VBUS_DB,
-};
-
-static void baseboard_interrupt_init(void)
-{
-	/* Enable Power Group interrupts. */
-	gpio_enable_interrupt(GPIO_PG_GROUPC_S0_OD);
-	gpio_enable_interrupt(GPIO_PG_LPDDR4X_S3_OD);
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *);
-struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
-					  mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: PS8818 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_c1_ps8818_mux_set,
-};
-
-__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me,
-					   mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: ANX7451 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_anx7451 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS,
-	.driver = &anx7451_usb_mux_driver,
-	.board_set = &board_c1_anx7451_mux_set,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		/* .next_mux = filled in by setup_mux based on fw_config */
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[USBC_PORT_C0] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED_CHRG] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED_FULL] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_S0_PGOOD,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 6500,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it needs a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-static void setup_mux(void)
-{
-	switch (board_get_usb_c1_mux()) {
-	case USB_C1_MUX_PS8818:
-		CPRINTSUSB("C1: Setting PS8818 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-		break;
-	case USB_C1_MUX_ANX7451:
-		CPRINTSUSB("C1: Setting ANX7451 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451;
-		break;
-	default:
-		CPRINTSUSB("C1: Mux is unknown");
-	}
-}
-DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int cur_port = charge_manager_get_active_charge_port();
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * If this port had booted in dead battery mode, go
-			 * ahead and reset it so EN_SNK responds properly.
-			 */
-			if (nct38xx_get_boot_type(i) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-				reset_nct38xx_port(cur_port);
-				pd_set_error_recovery(i);
-			}
-
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (tcpm_get_src_ctrl(port)) {
-		CPRINTSUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Disallow changing ports if we booted in dead battery mode and don't
-	 * have sufficient power to withstand Vbus loss.  The NCT3807 may
-	 * continue to keep EN_SNK low on the original port and allow a
-	 * dangerous level of voltage to pass through to the initial charge
-	 * port (see b/183660105)
-	 *
-	 * If we do have sufficient power, then reset the dead battery port and
-	 * set up Type-C error recovery on its connection.
-	 */
-	if (cur_port != CHARGE_PORT_NONE &&
-			port != cur_port &&
-			nct38xx_get_boot_type(cur_port) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-		if (pd_is_battery_capable()) {
-			reset_nct38xx_port(cur_port);
-			pd_set_error_recovery(cur_port);
-		} else {
-			CPRINTSUSB("Battery too low for charge port change");
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_is_i2c_port_powered(int port)
-{
-	switch (port) {
-	case I2C_PORT_USB_MUX:
-	case I2C_PORT_SENSOR:
-		/* USB mux and sensor i2c bus is unpowered in Z1 */
-		return chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 0 : 1;
-	case I2C_PORT_THERMAL_AP:
-		/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
-		return chipset_in_state(CHIPSET_STATE_ANY_OFF |
-					CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1;
-	default:
-		return 1;
-	}
-}
-
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv;
-
-	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-
-	return rv;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-void sbu_fault_interrupt(enum ioex_signal signal)
-{
-	int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1;
-
-	pd_handle_overcurrent(port);
-}
-
-static void set_ac_prochot(void)
-{
-	isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA);
-}
-DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage = 0;
-	int rv;
-
-	rv = charger_get_vbus_voltage(port, &voltage);
-
-	if (rv) {
-		CPRINTSUSB("%s rv=%d", __func__, rv);
-		return 0;
-	}
-
-	/*
-	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
-	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
-	 * This partly defeats the point of ramping, but will still catch
-	 * VBUS below 4.5V and above 0V.
-	 */
-	if (voltage == 0) {
-		CPRINTSUSB("%s vbus=0", __func__);
-		return 0;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE)
-		CPRINTSUSB("%s vbus=%d", __func__, voltage);
-
-	return voltage < BC12_MIN_VOLTAGE;
-}
-
-/**
- * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
- * PCH_PWRBTN_L.
- */
-void board_pwrbtn_to_pch(int level)
-{
-	timestamp_t start;
-	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
-
-	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
-	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
-		start = get_time();
-		do {
-			usleep(200);
-			if (gpio_get_level(GPIO_PCH_RSMRST_L))
-				break;
-		} while (time_since32(start) < timeout_rsmrst_rise_us);
-
-		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
-			ccprints("Error pwrbtn: RSMRST_L still low");
-
-		msleep(G3_TO_PWRBTN_DELAY_MS);
-	}
-	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
-}
-
-void board_hibernate(void)
-{
-	int port;
-
-	/*
-	 * If we are charging, then drop the Vbus level down to 5V to ensure
-	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
-	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
-	 * (b/79218851, b/143778351, b/147007265)
-	 */
-	port = charge_manager_get_active_charge_port();
-	if (port != CHARGE_PORT_NONE) {
-		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
-
-		/* Give PD task and PPC chip time to get to 5V */
-		msleep(SAFE_RESET_VBUS_DELAY_MS);
-	}
-
-	/* Try to put our battery fuel gauge into sleep mode */
-	if (battery_sleep_fuel_gauge() != EC_SUCCESS)
-		cprints(CC_SYSTEM, "Failed to send battery sleep command");
-}
-
-__overridable enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = ps8811_i2c_read(me, PS8811_REG_PAGE1,
-				     PS8811_REG1_USB_BEQ_LEVEL, &val);
-	} while (rv && --tries);
-
-	if (rv) {
-		CPRINTSUSB("A1: PS8811 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: PS8811 retimer detected");
-	rv = board_a1_ps8811_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv);
-	return rv;
-}
-
-/* PS8811 is just a type-A USB retimer, reusing mux structure for convience. */
-const struct usb_mux usba1_ps8811 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
-	.board_init = &baseboard_a1_ps8811_retimer_init,
-};
-
-__overridable enum ec_error_list
-board_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val);
-	} while (rv && --tries);
-	if (rv) {
-		CPRINTSUSB("A1: ANX7491 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: ANX7491 retimer detected");
-	rv = board_a1_anx7491_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv);
-	return rv;
-}
-
-/* ANX7491 is just a type-A USB retimer, reusing mux structure for convience. */
-const struct usb_mux usba1_anx7491 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS,
-	.board_init = &baseboard_a1_anx7491_retimer_init,
-};
-
-void baseboard_a1_retimer_setup(void)
-{
-	struct usb_mux a1_retimer;
-	switch (board_get_usb_a1_retimer()) {
-	case USB_A1_RETIMER_ANX7491:
-		a1_retimer = usba1_anx7491;
-		break;
-	case USB_A1_RETIMER_PS8811:
-		a1_retimer = usba1_ps8811;
-		break;
-	default:
-		CPRINTSUSB("A1: Unknown retimer!");
-		return;
-	}
-	a1_retimer.board_init(&a1_retimer);
-}
-DECLARE_DEFERRED(baseboard_a1_retimer_setup);
-
-static void baseboard_chipset_suspend(void)
-{
-	/* Disable display and keyboard backlights. */
-	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 1);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_resume(void)
-{
-	/* Enable display and keyboard backlights. */
-	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 0);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-	/* Some retimers take several ms to be ready, so defer setup call */
-	hook_call_deferred(&baseboard_a1_retimer_setup_data, 20 * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-	case USBC_PORT_C1:
-		gpio_set_level(GPIO_USB_C0_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
-	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
-					gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
-					gpio_get_level(GPIO_PG_GROUPC_S0_OD));
-}
-
-void baseboard_en_pwr_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
-	gpio_set_level(GPIO_EN_PWR_S0_R,
-					gpio_get_level(GPIO_SLP_S3_L) &&
-					gpio_get_level(GPIO_PG_PWR_S5));
-
-	/* Now chain off to the normal power signal interrupt handler. */
-	power_signal_interrupt(signal);
-}
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
deleted file mode 100644
index ef1338c5d5..0000000000
--- a/baseboard/guybrush/baseboard.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* NPCX9 config */
-#define CONFIG_PORT80_4_BYTE
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Optional features */
-#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */
-#define CONFIG_I2C_DEBUG /* Print i2c traces */
-#define CONFIG_CMD_S5_TIMEOUT /* Allow a user-specified timeout to exit S5 */
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Vboot Config */
-#define CONFIG_CRC8
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN	GPIO_EC_GSC_PACKET_MODE
-
-/* CBI Config */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-
-/* Power Config */
-#define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define G3_TO_PWRBTN_DELAY_MS 16
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_EN_PWR_A		GPIO_EN_PWR_S5
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_SOC_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_EC_SOC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S3_S0I3_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L	GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_SOC_PWR_GOOD
-#define GPIO_PCH_WAKE_L		GPIO_EC_SOC_WAKE_L
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_S0_PGOOD		GPIO_PG_PCORE_S0_R_OD
-#define GPIO_S5_PGOOD		GPIO_PG_PWR_S5
-#define GPIO_SYS_RESET_L	GPIO_EC_SYS_RST_L
-#define SAFE_RESET_VBUS_DELAY_MS 900
-#define SAFE_RESET_VBUS_MV 5000
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Thermal Config */
-#define CONFIG_ADC
-#define CONFIG_AMD_SB_RMI
-#define CONFIG_AMD_STT
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-#define CONFIG_TEMP_SENSOR_SB_TSI
-#define CONFIG_TEMP_SENSOR_TMP112
-#define CONFIG_THERMISTOR
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define GPIO_CPU_PROCHOT	GPIO_PROCHOT_ODL
-
-/* Flash Config */
-/* See config_chip-npcx9.h for SPI flash configuration */
-#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
-#define GPIO_WP_L			GPIO_EC_WP_L
-
-/* Host communication */
-#define CONFIG_CMD_CHARGEN
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
-
-/* Chipset config */
-#define CONFIG_CHIPSET_CEZANNE
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-
-/* Keyboard Config */
-#define CONFIG_KEYBOARD_BACKLIGHT
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_VIVALDI
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_KB_BL
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-
-/* Sensors */
-#ifdef HAS_TASK_MOTIONSENSE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-#endif  /* HAS_TASK_MOTIONSENSE */
-
-/* Backlight config */
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL
-
-/* Battery Config */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger Config */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-
-/*
- * EC will boot AP to depthcharge if: (BAT >= 2%) || (AC >= 50W)
- * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
- * Depthcharge to boot OS.
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
-
-/*
- * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
- * but that feature of ISL9241 is broken (b/160287056) so we have to use
- * CONFIG_CHARGE_RAMP_SW instead.
- */
-#define CONFIG_CHARGE_RAMP_SW
-
-/* USB Type C and USB PD config */
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-/* TODO: Enable TCPMv2 Fast Role Swap (FRS) */
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_NCT38XX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_SBU
-#define CONFIG_USBC_PPC_AOZ1380
-#define CONFIG_USBC_RETIMER_PI3HDX1204
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USBC_RETIMER_PS8811
-#define CONFIG_USBC_RETIMER_PS8818
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_AMD_FP6
-
-#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD
-#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
-
-/* TODO(b/176988382): Tune values for guybrush */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Max Power = 100 W */
-#define PD_MAX_POWER_MW		((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-
-/* USB-A config */
-#define USB_PORT_COUNT USBA_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB
-
-/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
-#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328
-
-/*
- * USB ID - This is allocated specifically for Guybrush
- */
-#define CONFIG_USB_PID 0x504D
-
-/* BC 1.2 */
-/*
- * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
- * until voltage drops to 4.5V. Don't go lower than this to be kind to the
- * charger (see b/67964166).
- */
-#define BC12_MIN_VOLTAGE 4500
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_UPDATE_IF_CHANGED
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT4_1
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT6_1
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/* Volume Button Config */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-
-/* Fan Config */
-#define CONFIG_FANS FAN_CH_COUNT
-/* TODO: Set CONFIG_FAN_INIT_SPEED, defaults to 100 */
-
-/* LED Config */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Power input signals */
-enum power_signal {
-	X86_SLP_S0_N,		/* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N,		/* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N,		/* SOC  -> SLP_S5_L */
-
-	X86_S0_PGOOD,		/* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD,		/* PMIC -> S5_PWROK */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/* TMP112 sensors */
-enum tmp112_sensor {
-	TMP112_SOC,
-	TMP112_AMB,
-	TMP112_COUNT,
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* PWM Channels */
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_CHRG,
-	PWM_CH_LED_FULL,
-	PWM_CH_COUNT
-};
-
-/* Fan Channels */
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void sbu_fault_interrupt(enum ioex_signal signal);
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal);
-void baseboard_en_pwr_s0(enum gpio_signal signal);
-
-int board_get_soc_temp_k(int idx, int *temp_k);
-
-/* CBI utility functions */
-uint32_t get_sku_id(void);
-uint32_t get_board_version(void);
-uint32_t get_fw_config(void);
-/* Board callback after CBI has been initialized */
-__overridable void board_cbi_init(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk
deleted file mode 100644
index 976ff2c931..0000000000
--- a/baseboard/guybrush/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Guybrush baseboard specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o
\ No newline at end of file
diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c
deleted file mode 100644
index 6d66b826dc..0000000000
--- a/baseboard/guybrush/cbi.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush CrOS Board Info(CBI) utilities */
-
-#include "base_fw_config.h"
-#include "console.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-uint32_t get_sku_id(void)
-{
-	static uint32_t sku_id;
-
-	if (sku_id == 0) {
-		uint32_t val;
-
-		if (cbi_get_sku_id(&val) != EC_SUCCESS)
-			return 0;
-		sku_id = val;
-	}
-	return sku_id;
-}
-
-uint32_t get_board_version(void)
-{
-	static uint32_t board_version;
-
-	if (board_version == 0) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) != EC_SUCCESS)
-			return -1;
-		board_version = val;
-	}
-	return board_version;
-}
-
-uint32_t get_fw_config(void)
-{
-	static uint32_t fw_config = UNINITIALIZED_FW_CONFIG;
-
-	if (fw_config == UNINITIALIZED_FW_CONFIG) {
-		uint32_t val;
-
-		if (cbi_get_fw_config(&val) != EC_SUCCESS)
-			return UNINITIALIZED_FW_CONFIG;
-		fw_config = val;
-	}
-	return  fw_config;
-}
-
-
-int get_fw_config_field(uint8_t offset, uint8_t width)
-{
-	uint32_t fw_config = get_fw_config();
-
-	if (fw_config == UNINITIALIZED_FW_CONFIG)
-		return -1;
-
-	return (fw_config >> offset) & ((1 << width) - 1);
-}
-
-
-__overridable void board_cbi_init(void)
-{
-}
-
-static void cbi_init(void)
-{
-	uint32_t board_ver = get_board_version();
-	uint32_t sku_id = get_sku_id();
-	uint32_t fw_config = get_fw_config();
-
-	if (board_ver != 0)
-		ccprints("Board Version: %d (0x%x)", board_ver, board_ver);
-	else
-		ccprints("Board Version: not set in cbi");
-
-	if (sku_id != 0)
-		ccprints("SKU ID: %d (0x%x)", sku_id, sku_id);
-	else
-		ccprints("SKU ID: not set in cbi");
-
-	if (fw_config != UNINITIALIZED_FW_CONFIG)
-		ccprints("FW Config: %d (0x%x)", fw_config, fw_config);
-	else
-		ccprints("FW Config: not set in cbi");
-
-	/* Allow the board project to make runtime changes based on CBI data */
-	board_cbi_init();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c
deleted file mode 100644
index 79725e827a..0000000000
--- a/baseboard/guybrush/usb_pd_policy.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Zork boards */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * Do not allow vconn swap 5V rail is off
-	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
-	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
-	 */
-	return gpio_get_level(GPIO_S5_PGOOD);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-		pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override int board_pd_set_frs_enable(int port, int enable)
-{
-	/*
-	 * Both PPCs require the FRS GPIO to be set as soon as FRS capability
-	 * is established.
-	 */
-	if (port == 0)
-		ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable);
-	else if (port == 1)
-		ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable);
-
-	return EC_SUCCESS;
-}
-
-/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
-int board_vbus_source_enabled(int port)
-{
-	return tcpm_get_src_ctrl(port);
-}
-
-/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
-int board_is_sourcing_vbus(int port)
-{
-	return board_vbus_source_enabled(port);
-}
diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c
deleted file mode 100644
index dd93e581cf..0000000000
--- a/baseboard/hatch/baseboard.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch family-specific configuration */
-#include "atomic.h"
-#include "battery_fuel_gauge.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/charger/bq25710.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "ec_commands.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "power.h"
-#include "stdbool.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_ACOK_OD,
-	GPIO_POWER_BUTTON_L,
-	/* EC_RST_ODL needs to wake device while in PSL hibernate. */
-	GPIO_SYS_RESET_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-#ifdef CONFIG_ACCEL_FIFO
-	{"sensor",  I2C_PORT_SENSOR,  100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-#endif
-	{"ppc0",    I2C_PORT_PPC0,    100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-#endif
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-#ifdef BOARD_AKEMI
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-#endif
-#ifdef BOARD_JINLON
-	{"thermal", I2C_PORT_THERMAL, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-#endif
-#ifdef BOARD_MUSHU
-	{"f75303_temp", I2C_PORT_THERMAL, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"gpu_temp", I2C_PORT_GPU, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-#endif
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  100, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
-		.drv = &bq25710_drv,
-	},
-};
-
-/******************************************************************************/
-/* Chipset callbacks/hooks */
-
-__attribute__((weak)) bool board_has_kb_backlight(void)
-{
-	/* Default enable keyboard backlight */
-	return true;
-}
-
-/* Called on AP S0iX -> S0 transition */
-static void baseboard_chipset_resume(void)
-{
-	if (board_has_kb_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void baseboard_chipset_suspend(void)
-{
-	if (board_has_kb_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int port;
-
-	/*
-	 * To support hibernate from ectool, keyboard, and console,
-	 * ensure that the AP is fully shutdown before hibernating.
-	 */
-#ifdef HAS_TASK_CHIPSET
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
-#endif
-
-	/*
-	 * If VBUS is not being provided by any of the PD ports,
-	 * then enable the SNK FET to allow AC to pass through
-	 * if it is later connected to ensure that AC_PRESENT
-	 * will wake up the EC from this state
-	 */
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		ppc_vbus_sink_enable(port, 1);
-
-	/*
-	 * This seems like a hack, but the AP chipset state machine
-	 * needs time to work through the transitions.  Also, it
-	 * works.
-	 */
-	msleep(300);
-}
-
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-#endif
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* Power Delivery and charging functions */
-void baseboard_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int level;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_1].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-#endif
-
-	return status;
-}
-
-static void reset_pd_port(int port, enum gpio_signal reset_gpio,
-			  int hold_delay, int finish_delay)
-{
-	int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH);
-
-	gpio_set_level(reset_gpio, level);
-	msleep(hold_delay);
-	gpio_set_level(reset_gpio, !level);
-	if (finish_delay)
-		msleep(finish_delay);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b/130194590): This should be replaced with a common function
-	 * once the gpio signal and delays are added to tcpc_config struct.
-	 */
-
-	/* Assert reset to TCPC for required delay only if we have a battery. */
-	if (battery_is_present() != BP_YES)
-		return;
-
-	/* Reset TCPC0 */
-	reset_pd_port(USB_PD_PORT_TCPC_0, GPIO_USB_C0_TCPC_RST,
-		      BOARD_TCPC_C0_RESET_HOLD_DELAY,
-		      BOARD_TCPC_C0_RESET_POST_DELAY);
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	/* Reset TCPC1 */
-	reset_pd_port(USB_PD_PORT_TCPC_1, GPIO_USB_C1_TCPC_RST,
-		      BOARD_TCPC_C1_RESET_HOLD_DELAY,
-		      BOARD_TCPC_C1_RESET_POST_DELAY);
-#endif
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USB_PD_PORT_TCPC_0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	return port == USB_PD_PORT_TCPC_0 ?
-		gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 :
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-#else
-		EC_SUCCESS;
-#endif
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-#ifdef USB_PD_PORT_TCPC_MST
-void baseboard_mst_enable_control(enum mst_source src, int level)
-{
-	static uint32_t mst_input_levels;
-
-	if (level)
-		atomic_or(&mst_input_levels, 1 << src);
-	else
-		atomic_clear_bits(&mst_input_levels, 1 << src);
-
-	gpio_set_level(GPIO_EN_MST, mst_input_levels ? 1 : 0);
-}
-#endif
-
-/* Enable or disable input devices, based on chipset state */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (board_is_convertible()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-static uint8_t sku_id;
-static uint8_t board_id;
-
-uint8_t get_board_sku(void)
-{
-	return sku_id;
-}
-
-uint8_t get_board_id(void)
-{
-	return board_id;
-}
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	/* SKU ID */
-	if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX) {
-		CPRINTS("Read SKU Error value :%d", val);
-		return;
-	}
-
-	sku_id = val;
-
-	CPRINTS("SKU: %d", sku_id);
-
-	/* Board ID */
-	if (cbi_get_board_version(&val) != EC_SUCCESS || val > UINT8_MAX) {
-		CPRINTS("Read Board ID Error (%d)", val);
-	}
-
-	board_id = val;
-
-	CPRINTS("Board ID: %d", board_id);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-__override enum ec_pd_port_location board_get_pd_port_location(int port)
-{
-	switch (port) {
-	case 0:
-		return EC_PD_PORT_LOCATION_LEFT_BACK;
-	case 1:
-		return EC_PD_PORT_LOCATION_RIGHT_BACK;
-	default:
-		return EC_PD_PORT_LOCATION_UNKNOWN;
-	}
-}
diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h
deleted file mode 100644
index bf9140b33f..0000000000
--- a/baseboard/hatch/baseboard.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#include "compiler.h"
-#include "stdbool.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#define CONFIG_I2C
-
-/* Optional console commands */
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DPTF
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* Don't wake up from suspend on any MKBP event */
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK 0
-
-/* I2C_PORT_ACCEL needs to be defined for i2c transactions */
-#define I2C_PORT_ACCEL I2C_PORT_SENSOR
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#if !defined(BOARD_PALKIA)
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#endif /* !BOARD_PALKIA */
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BQ25710
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated)
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
-
-/* Common battery defines */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#if defined(BOARD_PALKIA)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#else
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#endif
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USBC_PPC_DEDICATED_INT
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_PPC_DUMP
-
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-
-#define USB_PD_PORT_TCPC_0	0
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-#define USB_PD_PORT_TCPC_1	1
-#endif
-
-/* BC 1.2 */
-#define CONFIG_USB_CHARGER
-
-#if !defined(BOARD_PALKIA)
-/* Common Sensor Defines */
-#define CONFIG_TABLET_MODE
-#endif
-
-/* TODO(b/122273953): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-
-/* TODO(b/122273953): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-
-/* Other common defines */
-#define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EDP_BKLTEN_OD
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)
-
-#ifndef __ASSEMBLER__
-
-enum mst_source {
-	MST_TYPE_C0,
-	MST_TYPE_C1,
-	MST_HDMI,
-};
-
-/* Forward declare common (within Hatch) board-specific functions */
-bool board_has_kb_backlight(void);
-unsigned char get_board_sku(void);
-unsigned char get_board_id(void);
-void board_reset_pd_mcu(void);
-void baseboard_mst_enable_control(enum mst_source, int level);
-bool board_is_convertible(void);
-
-FORWARD_DECLARE_ENUM(battery_present);
-
-/* Check with variant about battery presence. */
-enum battery_present variant_battery_present(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c
deleted file mode 100644
index 063aa3721d..0000000000
--- a/baseboard/hatch/battery.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "gpio.h"
-#include "system.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-enum battery_present __attribute__((weak)) variant_battery_present(void)
-{
-	return BP_NOT_SURE;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	enum battery_present bp = variant_battery_present();
-
-	if (bp != BP_NOT_SURE)
-		return bp;
-
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Initialized
-	 */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	    battery_init() == 0) {
-		batt_pres = BP_NO;
-	}
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/baseboard/hatch/build.mk b/baseboard/hatch/build.mk
deleted file mode 100644
index 864225f605..0000000000
--- a/baseboard/hatch/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Hatch baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_BATTERY_SMART)+=battery.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c
deleted file mode 100644
index a66bfefe87..0000000000
--- a/baseboard/hatch/usb_pd_policy.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Hatch boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000_A);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c
deleted file mode 100644
index 3103aaf4c5..0000000000
--- a/baseboard/herobrine/baseboard.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine baseboard-specific configuration */
-
-#include "i2c.h"
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h
deleted file mode 100644
index 108f7f8cf5..0000000000
--- a/baseboard/herobrine/baseboard.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted event and HC:
- * The sensor stack is generating a lot of activity.
- * They can be enabled through the console command 'chan'.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Modules */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_FPU
-#define CONFIG_PWM
-#define CONFIG_PWM_DISPLIGHT
-#define CONFIG_HIBERNATE_PSL
-
-#define CONFIG_VBOOT_HASH
-
-#undef CONFIG_PECI
-
-#define CONFIG_HOSTCMD_SHI
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_HOSTCMD_SECTION_SORTED
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_CBI_GPIO
-#define CONFIG_CRC8
-#define CONFIG_POWER_BUTTON
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_CMD_BUTTON
-#define CONFIG_SWITCH
-#define CONFIG_LID_SWITCH
-#define CONFIG_EXTPOWER_GPIO
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Increase console output buffer since we have the RAM available. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_USB_CHARGER
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-
-/*
- * USB ID
- *
- * This is allocated specifically for Herobrine
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x5055
-
-/* USB */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* RTC */
-#define CONFIG_CMD_RTC
-#define CONFIG_HOSTCMD_RTC
-
-/* Sensors */
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
-
-#define PD_OPERATING_POWER_MW   10000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
-
-/* Chipset */
-#define CONFIG_CHIPSET_SC7280
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CHIPSET_RESUME_INIT_HOOK
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_CMD_AP_RESET_LOG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_LID_OPEN		GPIO_LID_OPEN_EC
-#define GPIO_SHI_CS_L		GPIO_AP_EC_SPI_CS_L
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_BATT_PRES_ODL	GPIO_EC_BATT_PRES_ODL
-#define GPIO_ENABLE_BACKLIGHT	GPIO_EC_BL_DISABLE_L
-#define GPIO_BOARD_VERSION1	GPIO_BRD_ID0
-#define GPIO_BOARD_VERSION2	GPIO_BRD_ID1
-#define GPIO_BOARD_VERSION3	GPIO_BRD_ID2
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-
-/* I2C Ports */
-#define I2C_PORT_BATTERY I2C_PORT_POWER
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_WLC     NPCX_I2C_PORT3_0
-#define I2C_PORT_RTC     NPCX_I2C_PORT4_1
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
-
-/* UART */
-#define CONFIG_CMD_CHARGEN
-
-/* Define the host events which are allowed to wake AP up from S3 */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
-
-/* And the MKBP events */
-#ifdef HAS_TASK_KEYSCAN
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
-#else
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
-#endif
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk
deleted file mode 100644
index f007fd7118..0000000000
--- a/baseboard/herobrine/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y+=baseboard.o
-baseboard-y+=usbc_config.o
-baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c
deleted file mode 100644
index 7ca2688aef..0000000000
--- a/baseboard/herobrine/usb_pd_policy.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* In G3, do not allow vconn swap since PP5000 rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-#if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
-#else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-#endif
-
-static void board_vbus_update_source_current(int port)
-{
-	/* Both port are controlled by PPC SN5S330. */
-	ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
-	ppc_vbus_source_enable(port, vbus_en[port]);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_vbus_sink_enable(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-	board_vbus_update_source_current(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return tcpm_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	uint8_t pin_mode = get_dp_pin_mode(port);
-
-	if (!pin_mode)
-		return 0;
-
-	/*
-	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
-	 * The AP only supports one DP phy. An external DP mux switches between
-	 * the two ports. Should switch those muxes when it is really used,
-	 * i.e. HPD high; otherwise, the real use case is preempted, like:
-	 *  (1) plug a dongle without monitor connected to port-0,
-	 *  (2) plug a dongle without monitor connected to port-1,
-	 *  (3) plug a monitor to the port-1 dongle.
-	 */
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-}
-
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-
-	return 1;
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	int cur_lvl = gpio_get_level(hpd);
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (!is_dp_muxable(port)) {
-		/* TODO(waihong): Info user? */
-		CPRINTS("p%d: The other port is already muxed.", port);
-		return 0;
-	}
-
-	/*
-	 * Initial implementation to handle HPD. Only the first-plugged port
-	 * works, i.e. sending HPD signal to AP. The second-plugged port
-	 * will be ignored.
-	 *
-	 * TODO(waihong): Continue the above case, if the first-plugged port
-	 * is then unplugged, switch to the second-plugged port and signal AP?
-	 */
-	if (lvl) {
-		/*
-		 * Enable and switch the DP port selection mux to the
-		 * correct port.
-		 *
-		 * TODO(waihong): Better to move switching DP mux to
-		 * the usb_mux abstraction.
-		 */
-		gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
-		gpio_set_level(GPIO_DP_MUX_OE_L, 0);
-
-		/* Connect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		/*
-		 * Connect the USB SS/DP lines in TCPC chip.
-		 *
-		 * When mf_pref not true, still use the dock muxing
-		 * because of the board USB-C topology (limited to 2
-		 * lanes DP).
-		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	} else {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Disconnect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 0);
-
-		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	}
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		pd_notify_dp_alt_mode_entry(port);
-
-	/* Configure TCPC for the HPD event, for proper muxing */
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-	/* Signal AP for the HPD event, through GPIO to AP */
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* Wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* Generate IRQ_HPD pulse */
-		gpio_set_level(hpd, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		gpio_set_level(hpd, 1);
-
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	} else if (irq & !lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0;
-	} else {
-		gpio_set_level(hpd, lvl);
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	}
-
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	if (is_dp_muxable(port)) {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Signal AP for the HPD low event */
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
-	}
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c
deleted file mode 100644
index 5e613c40a5..0000000000
--- a/baseboard/herobrine/usbc_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine family-specific USB-C configuration */
-
-#include "charger.h"
-#include "charger/isl923x_public.h"
-#include "charge_state.h"
-#include "usb_pd.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int usb_mv;
-	int port;
-
-	if (curr->state != ST_CHARGE)
-		return 0;
-
-	/* Lower the max requested voltage to 5V when battery is full. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    (curr->batt.status & STATUS_FULLY_CHARGED))
-		usb_mv = 5000;
-	else
-		usb_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != usb_mv) {
-		CPRINTS("VBUS limited to %dmV", usb_mv);
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, usb_mv);
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c
deleted file mode 100644
index df56697fbf..0000000000
--- a/baseboard/honeybuns/baseboard.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Honeybuns family-specific configuration */
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/mp4245.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "usb_pd.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usbc_ppc.h"
-#include "driver/tcpm/tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define POWER_BUTTON_SHORT_USEC (300 * MSEC)
-#define POWER_BUTTON_LONG_USEC (5000 * MSEC)
-#define POWER_BUTTON_DEBOUNCE_USEC (30)
-
-#define BUTTON_EVT_CHANGE   BIT(0)
-#define BUTTON_EVT_INFO     BIT(1)
-
-enum power {
-	POWER_OFF,
-	POWER_ON
-};
-
-enum button {
-	BUTTON_RELEASE,
-	BUTTON_PRESS,
-	BUTTON_PRESS_POWER_ON,
-	BUTTON_PRESS_SHORT,
-	BUTTON_PRESS_LONG,
-};
-
-#define LED_ON_OFF_BIT BIT(0)
-#define LED_COLOR_BIT BIT(2)
-#define LED_FLASH_SEQ_LENGTH 8
-
-enum led_color {
-	GREEN,
-	YELLOW,
-	OFF,
-};
-
-static enum power dock_state;
-#ifdef SECTION_IS_RW
-static int button_level;
-static int button_level_pending;
-static int dock_mf;
-static int led_count;
-#endif
-
-/******************************************************************************/
-
-__maybe_unused static void board_power_sequence(int enable)
-{
-	int i;
-
-	if (enable) {
-		for(i = 0; i < board_power_seq_count; i++) {
-			gpio_set_level(board_power_seq[i].signal,
-				       board_power_seq[i].level);
-			CPRINTS("power seq: rail = %d", i);
-			if (board_power_seq[i].delay_ms)
-				msleep(board_power_seq[i].delay_ms);
-		}
-	} else {
-		for(i = board_power_seq_count - 1; i >= 0; i--) {
-			gpio_set_level(board_power_seq[i].signal,
-				       !board_power_seq[i].level);
-			CPRINTS("sequence[%d]: level = %d", i,
-				!board_power_seq[i].level);
-		}
-	}
-
-	dock_state = enable;
-	CPRINTS("board: Power rails %s", dock_state ? "on" : "off");
-}
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"i2c1",  I2C_PORT_I2C1,  400, GPIO_EC_I2C1_SCL, GPIO_EC_I2C1_SDA},
-	{"i2c3",  I2C_PORT_I2C3,  400, GPIO_EC_I2C3_SCL, GPIO_EC_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#ifdef SECTION_IS_RW
-static void baseboard_set_led(enum led_color color)
-{
-	/*
-	 * TODO(b/164157329): The power button feature should be connected to a
-	 * 2 color LED which is part of the button. Currently, the power button
-	 * LED is a single color LED which is controlled by on the of the power
-	 * rails. Using the status LED now to demonstrate the LED behavior
-	 * associated with a power button press.
-	 */
-	CPRINTS("led: color = %d", color);
-
-	/* Not all boards may have LEDs under EC control */
-#if defined(GPIO_PWR_BUTTON_RED) && defined(GPIO_PWR_BUTTON_GREEN)
-	if (color == OFF) {
-		gpio_set_level(GPIO_PWR_BUTTON_RED, 1);
-		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 1);
-	} else if (color == GREEN) {
-		gpio_set_level(GPIO_PWR_BUTTON_RED, 1);
-		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0);
-	} else if (color == YELLOW) {
-		gpio_set_level(GPIO_PWR_BUTTON_RED, 0);
-		gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0);
-	}
-#endif
-}
-
-static void baseboard_led_callback(void);
-DECLARE_DEFERRED(baseboard_led_callback);
-
-static void baseboard_led_callback(void)
-{
-	/*
-	 * Flash LED on transition using a simple 3 bit counter. Bit 0 controls
-	 * LED on/off and bit 2 controls which color to set during the on phase.
-	 */
-	int color = led_count & LED_COLOR_BIT ? dock_mf : dock_mf ^ 1;
-
-	/*
-	 * TODO(b/164157329): This function implements a simple flashing
-	 * transition when the MF preference bit is changed via a long power
-	 * button press sequence. This might need to move to the board function
-	 * if not required/desired on all variants.
-	 */
-
-	if (led_count & LED_ON_OFF_BIT)
-		baseboard_set_led(color);
-	else
-		baseboard_set_led(OFF);
-
-	/* Flash sequence is 8 steps */
-	if (++led_count < LED_FLASH_SEQ_LENGTH)
-		hook_call_deferred(&baseboard_led_callback_data, 150 * MSEC);
-}
-
-static void baseboard_change_mf_led(void)
-{
-	led_count = 0;
-	baseboard_led_callback();
-}
-
-void baseboard_set_mst_lane_control(int mf)
-{
-	/*
-	 * The parameter mf reflects the desired lane control value. If the
-	 * current value does not match the desired, then the MST hub must first
-	 * be put into reset, so the MST hub will latch in the correct value
-	 * when it's taken out of reset.
-	 */
-	if (mf != gpio_get_level(GPIO_MST_HUB_LANE_SWITCH)) {
-		/* put MST into reset */
-		gpio_set_level(GPIO_MST_RST_L, 0);
-		msleep(1);
-		gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, mf);
-		CPRINTS("MST: lane control = %s", mf ? "high" : "low");
-		msleep(1);
-		/* lane control is set, take MST out of reset */
-		gpio_set_level(GPIO_MST_RST_L, 1);
-	}
-}
-
-static void baseboard_enable_mp4245(void)
-{
-	int mv;
-	int ma;
-
-	mp4245_set_voltage_out(5000);
-	mp4245_votlage_out_enable(1);
-	msleep(MP4245_VOUT_5V_DELAY_MS);
-	mp3245_get_vbus(&mv, &ma);
-	CPRINTS("mp4245: vout @ %d mV enabled", mv);
-}
-
-#endif /* SECTION_IS_RW */
-
-static void baseboard_init(void)
-{
-#ifdef SECTION_IS_RW
-	uint32_t fw_config;
-#endif
-
-	/* Turn on power rails */
-	board_power_sequence(1);
-	CPRINTS("board: Power rails enabled");
-
-#ifdef SECTION_IS_RW
-	/* Force TC state machine to start in TC_ERROR_RECOVERY */
-	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
-	/* Make certain SN5S330 PPC does full initialization */
-	system_set_reset_flags(EC_RESET_FLAG_EFS);
-
-	/*
-	 * Dock multi function (mf) preference is stored in bit 0 of fw_config
-	 * field of the CBI. If this value is programmed, then make sure the
-	 * MST_LANE_CONTROL gpio matches the mf bit.
-	 */
-	if (!cbi_get_fw_config(&fw_config)) {
-		dock_mf = CBI_FW_MF_PREFERENCE(fw_config);
-		baseboard_set_mst_lane_control(dock_mf);
-	} else {
-		dock_mf = dock_get_mf_preference();
-		cbi_set_fw_config(dock_mf);
-		CPRINTS("cbi: setting default result = %s",
-			cbi_get_fw_config(&fw_config) ? "pass" : "fail");
-	}
-
-#ifdef GPIO_USBC_UF_ATTACHED_SRC
-	/* Configure UF usbc ppc and check usbc state */
-	baseboard_config_usbc_usb3_ppc();
-#endif /* GPIO_USBC_UF_ATTACHED_SRC */
-
-	/* Enable power button interrupt */
-	gpio_enable_interrupt(GPIO_PWR_BTN);
-	/* Set dock mf preference LED */
-	baseboard_set_led(dock_mf);
-	/* Setup VBUS to default value */
-	baseboard_enable_mp4245();
-
-#else
-	/* Set up host port usbc to present Rd on CC lines */
-	if(baseboard_usbc_init(USB_PD_PORT_HOST))
-		CPRINTS("usbc: Failed to set up sink path");
-	else
-		CPRINTS("usbc: sink path configure success!");
-#endif /* SECTION_IS_RW */
-}
-/*
- * Power sequencing must run before any other chip init is attempted, so run
- * power sequencing as soon as I2C bus is initialized.
- */
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_INIT_I2C + 1);
-
-#ifdef SECTION_IS_RW
-static void baseboard_power_on(void)
-{
-	int port_max = board_get_usb_pd_port_count();
-	int port;
-
-	CPRINTS("pwrbtn: power on: mf = %d", dock_mf);
-	/* Adjust system flags to full PPC init occurs */
-	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
-	system_set_reset_flags(EC_RESET_FLAG_EFS);
-	/* Enable power rails and release reset signals */
-	board_power_sequence(1);
-	/* Set VBUS to 5V and enable output from mp4245 */
-	baseboard_enable_mp4245();
-	/* Set dock mf preference LED */
-	baseboard_set_led(dock_mf);
-	/*
-	 * Lane control (realtek MST) must be set prior to releasing MST
-	 * reset.
-	 */
-	baseboard_set_mst_lane_control(dock_mf);
-	/*
-	 * When the power to the PPC is turned off, then back on, the PPC will
-	 * default into dead battery mode. Dead battery resistors are disabled
-	 * as part of the full PPC intializaiton sequence. This is required to
-	 * force a detach event with port parter which can be attached as usbc
-	 * source when honeybuns power rails are off.
-	 */
-	for (port = 0; port < port_max; port++) {
-		ppc_init(port);
-		msleep(1000);
-		/* Inform TC state machine that it can resume */
-		pd_set_suspend(port, 0);
-	}
-	/* Enable usbc interrupts */
-	board_enable_usbc_interrupts();
-
-#ifdef GPIO_USBC_UF_ATTACHED_SRC
-	baseboard_config_usbc_usb3_ppc();
-#endif
-}
-
-static void baseboard_power_off(void)
-{
-	int port_max = board_get_usb_pd_port_count();
-	int port;
-
-	CPRINTS("pwrbtn: power off");
-	/* Put ports in TC suspend state */
-	for (port = 0; port < port_max; port++)
-		pd_set_suspend(port, 1);
-
-	/* Disable ucpd peripheral (prevents interrupts) */
-	tcpm_release(USB_PD_PORT_HOST);
-	/* Disable PPC/TCPC interrupts */
-	board_disable_usbc_interrupts();
-
-#ifdef GPIO_USBC_UF_ATTACHED_SRC
-	/* Disable PPC interrupts for PS8803 managed port */
-	baseboard_usbc_usb3_enable_interrupts(0);
-#endif
-	/* Set dock power button/MF preference LED */
-	baseboard_set_led(OFF);
-	/* Go into power off state */
-	board_power_sequence(0);
-}
-
-static void baseboard_toggle_mf(void)
-{
-	uint32_t fw_config;
-
-	if (!cbi_get_fw_config(&fw_config)) {
-		/* Update the user MF preference stored in CBI */
-		fw_config ^= CBI_FW_MF_MASK;
-		cbi_set_fw_config(fw_config);
-		/* Update variable used to track user MF preference */
-		dock_mf = CBI_FW_MF_PREFERENCE(fw_config);
-		/* Flash led for visual indication of user MF change */
-		baseboard_change_mf_led();
-
-		/*
-		 * Suspend, then release host port to force new MF setting to
-		 * take effect.
-		 */
-		pd_set_suspend(USB_PD_PORT_HOST, 1);
-		msleep(250);
-		pd_set_suspend(USB_PD_PORT_HOST, 0);
-	}
-}
-
-/*
- * Main task entry point for UCPD task
- */
-void power_button_task(void *u)
-{
-	int timer_us = POWER_BUTTON_DEBOUNCE_USEC * 4;
-	enum button state = BUTTON_RELEASE;
-	uint32_t evt;
-
-	/*
-	 * Capture current button level in case it's being pressed when the dock
-	 * is powered on. Note timer_us is initialized for debounce time to
-	 * double check.
-	 */
-	button_level = gpio_get_level(GPIO_PWR_BTN);
-
-	while (1) {
-		evt = task_wait_event(timer_us);
-		timer_us = -1;
-
-		if (evt == BUTTON_EVT_INFO) {
-			/* Only used for console command for debug */
-			CPRINTS("pwrbtn: pwr = %d, state = %d, level = %d",
-				dock_state, state, button_level);
-			continue;
-		}
-
-		switch (state) {
-		case BUTTON_RELEASE:
-			/*
-			 * Default wait state: Only need to check if the button
-			 * is pressed and start the short press timer.
-			 */
-			if (evt & BUTTON_EVT_CHANGE && button_level ==
-			    BUTTON_PRESSED_LEVEL) {
-				state = BUTTON_PRESS;
-				timer_us = (POWER_BUTTON_SHORT_USEC -
-						 POWER_BUTTON_DEBOUNCE_USEC);
-			}
-			break;
-		case BUTTON_PRESS:
-			/*
-			 * Validate short press by ensuring that button is still
-			 * pressed after short press timer expires.
-			 */
-			if (evt & BUTTON_EVT_CHANGE &&
-			    button_level == BUTTON_RELEASED_LEVEL) {
-				state = BUTTON_RELEASE;
-			} else {
-				/* Start long press timer */
-				timer_us = POWER_BUTTON_LONG_USEC -
-					POWER_BUTTON_SHORT_USEC;
-				/*
-				 * If dock is currently off, then change to the
-				 * power on state. If dock is already on, then
-				 * advance to short press state.
-				 */
-				if (dock_state == POWER_OFF) {
-					baseboard_power_on();
-				        state = BUTTON_PRESS_POWER_ON;
-				} else {
-					state = BUTTON_PRESS_SHORT;
-				}
-			}
-			break;
-		case BUTTON_PRESS_POWER_ON:
-			/*
-			 * Short press recognized and dock was just powered
-			 * on. If button is no longer pressed, then just return
-			 * to the default state. Else, button is still pressed
-			 * after long press timer has expired.
-			 */
-			if (evt & BUTTON_EVT_CHANGE &&
-			    button_level == BUTTON_RELEASED_LEVEL) {
-				state = BUTTON_RELEASE;
-			} else {
-				state = BUTTON_PRESS_LONG;
-				baseboard_toggle_mf();
-			}
-			break;
-		case BUTTON_PRESS_SHORT:
-			/*
-			 * Short press was recognized and dock power state was
-			 * already on. If button is now released, then turn dock
-			 * off.
-			 */
-			if (evt & BUTTON_EVT_CHANGE &&
-			    button_level == BUTTON_RELEASED_LEVEL) {
-				state = BUTTON_RELEASE;
-				baseboard_power_off();
-			} else {
-				state = BUTTON_PRESS_LONG;
-				baseboard_toggle_mf();
-			}
-			break;
-		case BUTTON_PRESS_LONG:
-			if (evt & BUTTON_EVT_CHANGE &&
-			    button_level == BUTTON_RELEASED_LEVEL) {
-				state = BUTTON_RELEASE;
-			}
-			break;
-		}
-	}
-}
-
-static void baseboard_power_button_debounce(void)
-{
-	int level = gpio_get_level(GPIO_PWR_BTN);
-
-	/* Sanity check, level should be same after debounce interval */
-	if (level != button_level_pending)
-		return;
-
-	button_level = level;
-	task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_CHANGE);
-}
-DECLARE_DEFERRED(baseboard_power_button_debounce);
-
-void baseboard_power_button_evt(int level)
-{
-	button_level_pending = level;
-
-	hook_call_deferred(&baseboard_power_button_debounce_data,
-			   POWER_BUTTON_DEBOUNCE_USEC);
-}
-
-static int command_pwr_btn(int argc, char **argv)
-{
-
-	if (argc == 1) {
-		task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "on")) {
-		baseboard_power_on();
-	} else if (!strcasecmp(argv[1], "off")) {
-		baseboard_power_off();
-	} else if (!strcasecmp(argv[1], "mf")) {
-		baseboard_toggle_mf();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn,
-			"<on|off|mf>",
-			"Simulate Power Button Press");
-
-#endif
diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h
deleted file mode 100644
index 1b56b07f8c..0000000000
--- a/baseboard/honeybuns/baseboard.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Honeybuns baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* EC Defines */
-#define CONFIG_CRC8
-
-/* Flash Lyaout */
-/*
- * Flash layout: we redefine the sections offsets and sizes as we will use
- * RO/RW regions of different sizes.
- */
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_FLASH_PSTATE
-/* Do not use a dedicated PSTATE bank */
-#undef CONFIG_FLASH_PSTATE_BANK
-
-#define CONFIG_SHAREDLIB_SIZE	0
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(64*1024)
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-#define CONFIG_STM_HWTIMER32
-#define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
-#define TIM_CLOCK_LSB 15
-#define TIM_WATCHDOG 7
-
-/* Honeybuns platform does not have a lid switch */
-#undef CONFIG_LID_SWITCH
-
-/* USART and EC console configs */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 3
-#define CONFIG_UART_TX_DMA
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART3_TX
-#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
-
-/* CBI Configs */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CMD_CBI
-#define CONFIG_EEPROM_CBI_WP
-#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
-#define GPIO_EC_CBI_WP GPIO_EC_FLASH_WP_ODL
-#define CBI_FW_MF_MASK BIT(0)
-#define CBI_FW_MF_PREFERENCE(val) (val & (CBI_FW_MF_MASK))
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_STREAM_USB
-#define CONFIG_USB_UPDATE
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-#define CONFIG_MAC_ADDR
-#define DEFAULT_MAC_ADDR "Uninitialized"
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
-#define USB_EP_COUNT		2
-
-#define USB_IFACE_UPDATE	0
-#define USB_IFACE_COUNT		1
-
-#ifndef __ASSEMBLER__
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_UPDATE_NAME,
-	USB_STR_COUNT
-};
-#endif
-
-/* RW Specific Config Options */
-#ifdef SECTION_IS_RW
-/* No AP on any honeybuns variants */
-#undef CONFIG_USB_PD_HOST_CMD
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_ALT_MODE_UFP_DP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_REV30
-/*
- * Source current limit pull options. Honeybuns always wants TYPEC_RP_3A0
- * current limits for the usbc host port (C0). For port C1, some variants are
- * designed with a 1.5A current limit. This variation is handled via
- * BOARD_C1_1A5_LIMIT which would be set in a variant's board.h file.
- *
- * CONFIG_USB_PD_3A_PORTS should be left at 0 as this will disable DPM from
- * doing any dynamic current limit management.
- */
-#undef CONFIG_USB_PD_PULLUP
-#define CONFIG_USB_PD_PULLUP TYPEC_RP_3A0
-#define CONFIG_USB_PD_3A_PORTS 0
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USB_PD_TCPM_STM32GX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USBC_SS_MUX
-
-#define CONFIG_HAS_TASK_PD_INT
-#define CONFIG_STM32G4_UCPD_DEBUG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-
-#define CONFIG_MP4245
-#define USB_HUB_OCP_RESET_MSEC (10 * MSEC)
-
-#else /* RO Specific Config Options */
-
-/* RWSIG Config Options */
-/* Sign and switch to RW partition on boot. */
-#define CONFIG_RWSIG
-#define CONFIG_RSA
-#define CONFIG_SHA256_UNROLLED
-#undef CONFIG_RWSIG_JUMP_TIMEOUT
-#define CONFIG_RWSIG_JUMP_TIMEOUT (7000 * MSEC)
-
-/* Don't build PD console command for RO */
-#undef CONFIG_CMD_PD
-#undef CONFIG_USB_PD_CONSOLE_CMD
-#undef CONFIG_USB_PD_HOST_CMD
-/* Make sure these files aren't built in RO */
-#undef CONFIG_USB_PRL_SM
-#undef CONFIG_USB_TYPEC_SM
-#undef CONFIG_USB_PE_SM
-
-#endif /* SECTION_IS_RW */
-
-#define CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_SHA256
-
-/* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     5000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       15000
-#define PD_OPERATING_POWER_MW 15000
-
-/* TODO(b:147314141): Verify these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "stddef.h"
-
-struct power_seq {
-	enum gpio_signal signal; /* power/reset gpio_signal to control */
-	int level;               /* level to set in power sequence */
-	unsigned int delay_ms;   /* delay (in msec) after setting gpio_signal */
-};
-
-enum mf_preference {
-	MF_OFF = 0,
-	MF_ON,
-};
-
-/*
- * This is required as adc_channel is included in adc.h which ends up being
- * included when TCPMv2 functions are included
- */
-enum adc_channel {
-	ADC_CH_COUNT
-};
-
-extern const struct power_seq board_power_seq[];
-extern const size_t board_power_seq_count;
-
-void baseboard_power_button_evt(int level);
-
-/*
- * Configure the host port to present Rd on both CC lines. This function is
- * called in RO which does not otherwise have usbc/usb-pd support.
- *
- * @return true - initialized. false - not.
- */
-int baseboard_usbc_init(int port);
-
-/*
- * Get a board's desired multi-function (MF) prefernce. This allows for board
- * specific policy.
- *
- * @return 1 if multi function (DP + USB3) is preferred, 0 otherwise
- */
-int dock_get_mf_preference(void);
-
-/*
- * Initialize and configure PPC used for USB3 only port
- *
- * @return EC success if PPC initialization is successful
- */
-int baseboard_config_usbc_usb3_ppc(void);
-
-/*
- * Called from interrupt handler for PS8803 attached.src gpio. This gpio signal
- * will be set high by the PS8803 when it's in the attached.src state and low
- * otherwise. For boards wich have a PPC on this port, this signal is used to
- * enable/disable VBUS in the PPC.
- */
-void baseboard_usb3_check_state(void);
-
-
-/*
- * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected
- * by the host in the DP Configure SVDM message.
- *
- * @param dock_mf 1 -> 2 lanes DP, 0 -> 4 lanes DP
- */
-void baseboard_set_mst_lane_control(int dock_mf);
-
-/*
- * Control enable/disable for interrupts used for usb3 only usbc port.
- *
- * @param enable -> 1 for enable, 0 for disable
- */
-void baseboard_usbc_usb3_enable_interrupts(int enable);
-
-/*
- * Called from interrupt handler for PPC used on usb3 only port.
- *
- */
-void baseboard_usbc_usb3_irq(void);
-
-/**
- * Determine if VBUS is present or not.
- *
- * @param port: The Type-C port number.
- * @return 1 if VBUS is present, 0 if not.
- */
-int c1_ps8805_is_vbus_present(int port);
-
-/**
- * Is the port sourcing Vbus?
- *
- * @param port: The Type-C port number.
- * @return 1 if sourcing Vbus, 0 if not.
- */
-int c1_ps8805_is_sourcing_vbus(int port);
-
-/**
- * Turn on/off VBUS for port C1
- *
- * @param port: The Type-C port number.
- * @param enable: 1: Turn on VBUS, 0: turn off VBUS.
- * @return EC_SUCCESS on success, error otherwise.
-	 */
-int c1_ps8805_vbus_source_enable(int port, int enable);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk
deleted file mode 100644
index 2868911925..0000000000
--- a/baseboard/honeybuns/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Honeybuns baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-y+=usbc_support.o
diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c
deleted file mode 100644
index ef2350a03d..0000000000
--- a/baseboard/honeybuns/usb_pd_policy.c
+++ /dev/null
@@ -1,638 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "chip/stm32/ucpd-stm32gx.h"
-#include "cros_board_info.h"
-#include "driver/mp4245.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/mp4245.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_dp_ufp.h"
-#include "usb_tc_sm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define MP4245_VOLTAGE_WINDOW BIT(2)
-#define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED)
-
-/* Voltage indexes for the PDOs */
-enum volt_idx {
-	PDO_IDX_5V   = 0,
-	PDO_IDX_9V   = 1,
-	PDO_IDX_15V  = 2,
-	PDO_IDX_20V  = 3,
-	PDO_IDX_COUNT
-};
-
-/* PDOs */
-const uint32_t pd_src_host_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   3000, PDO_FIXED_FLAGS),
-	[PDO_IDX_9V]  = PDO_FIXED(9000,   3000, 0),
-	[PDO_IDX_15V]  = PDO_FIXED(15000, 3000, 0),
-	[PDO_IDX_20V]  = PDO_FIXED(20000, 3000, 0),
-};
-BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT);
-
-#ifdef BOARD_C1_1A5_LIMIT
-const uint32_t pd_src_display_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   1500, PDO_FIXED_FLAGS),
-};
-#else
-const uint32_t pd_src_display_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   3000, PDO_FIXED_FLAGS),
-};
-#endif
-
-const uint32_t pd_snk_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   0, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-static int src_host_pdo_cnt_override;
-
-#define PD_DR_SWAP_ATTEMPT_MAX 3
-static int pd_dr_swap_attempt_count[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int command_hostpdo(int argc, char **argv)
-{
-	char *e;
-	int limit;
-
-	if (argc >= 2) {
-
-		limit = strtoi(argv[1], &e, 10);
-		if ((limit < 0) || (limit > PDO_IDX_COUNT))
-			return EC_ERROR_PARAM1;
-
-		src_host_pdo_cnt_override = limit;
-	}
-	ccprintf("src host pdo override = %d\n", src_host_pdo_cnt_override);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo,
-			"<0|1|2|3|4>",
-			"Limit number of PDOs for C0");
-
-int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	int pdo_cnt = 0;
-
-	if (port == USB_PD_PORT_HOST) {
-		*src_pdo =  pd_src_host_pdo;
-		pdo_cnt = ARRAY_SIZE(pd_src_host_pdo);
-		/*
-		 * This override is only active via a console command. Only used
-		 * for debug to limit the level of VBUS offered to port partner
-		 * if desired. The console command only allows 0 ->
-		 * PDO_IDX_COUNT for this value.
-		 */
-		if (src_host_pdo_cnt_override)
-			pdo_cnt = src_host_pdo_cnt_override;
-	} else {
-		*src_pdo =  pd_src_display_pdo;
-		pdo_cnt = ARRAY_SIZE(pd_src_display_pdo);
-	}
-
-	return pdo_cnt;
-}
-
-/*
- * Default Port Discovery DR Swap Policy.
- *
- * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap
- * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap
- */
-__override bool port_discovery_dr_swap_policy(int port,
-			enum pd_data_role dr, bool dr_swap_flag)
-{
-	/*
-	 * Port0: test if role is DFP
-	 * Port1: test if role is UFP
-	 */
-	enum pd_data_role role_test =
-		(port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : PD_ROLE_UFP;
-
-	/*
-	 * Request data role swap if not in the port's desired data role and if
-	 * the attempt count is less than the max allowed. This function is
-	 * called for each PE run once in a PD contract. If the port partner
-	 * rejects data role swap requests (eg compliance tester), want to limit
-	 * how many DR swap requests are attempted.
-	 */
-	if (dr == role_test && (pd_dr_swap_attempt_count[port]++ <
-				PD_DR_SWAP_ATTEMPT_MAX))
-		return true;
-
-	/* Do not perform a DR swap */
-	return false;
-}
-
-/*
- * Default Port Discovery VCONN Swap Policy.
- *
- * 1) No need to Vconn swap.  This board does not require any cable information.
- */
-__override bool port_discovery_vconn_swap_policy(int port,
-			bool vconn_swap_flag)
-{
-	return false;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*TODO: Dock is the Vconn source */
-	return 1;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return;
-
-	if (IS_ENABLED(BOARD_C1_NO_PPC) && port) {
-		prev_en = c1_ps8805_is_sourcing_vbus(port);
-		/* Disable VBUS via PPC. */
-		c1_ps8805_vbus_source_enable(port, 0);
-	} else {
-		prev_en = ppc_is_sourcing_vbus(port);
-		/* Disable VBUS via PPC. */
-		ppc_vbus_source_enable(port, 0);
-	}
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	if (port == USB_PD_PORT_HOST) {
-		int mv;
-		int ma;
-		int unused_mv;
-
-		/*
-		 * Because VBUS on C0 is turned on/off via the PPC, the
-		 * voltage from the mp4245 does not need to be turned off, or
-		 * set to 0V. Instead, reset VBUS voltage to default value
-		 * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next
-		 * attached.src condition.
-		 */
-		pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv,
-				     &unused_mv);
-		mp4245_set_voltage_out(mv);
-		/* Ensure voltage is back to 5V */
-		pd_transition_voltage(1);
-	}
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/*
-	 * Note: For host port, the mp4245 output voltage is set for 5V by
-	 * default and each time VBUS is turned off. VOUT from the mp4245 is
-	 * left enabled as there is a switch (either PPC or discrete) to turn
-	 * VBUS on/off on the wire.
-	 */
-	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
-		rv = c1_ps8805_vbus_source_enable(port, 1);
-	else
-		rv = ppc_vbus_source_enable(port, 1);
-
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-void pd_transition_voltage(int idx)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-	int mv;
-	int target_mv;
-	int mv_average = 0;
-	int ma;
-	int vbus_hi;
-	int vbus_lo;
-	int i;
-	int mv_buffer[MP4245_VOLTAGE_WINDOW];
-
-	/* Only C0 can provide more than 5V */
-	if (port != USB_PD_PORT_HOST)
-		return;
-
-	/*
-	 * Set the VBUS output voltage and current limit to the values specified
-	 * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st
-	 * PDO of SRC_CAP which must always be 5V fixed supply.
-	 */
-	pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv,
-			     &mv);
-
-	/* Initialize sample delay buffer */
-	for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++)
-		mv_buffer[i] = 0;
-
-	/* Set VBUS level to value specified in the requested PDO */
-	mp4245_set_voltage_out(target_mv);
-	/* Wait for vbus to be within ~5% of its target value */
-	vbus_hi = target_mv + (target_mv >> 4);
-	vbus_lo = target_mv - (target_mv >> 4);
-
-	for (i = 0; i < 20; i++) {
-		/* Read current sample */
-		mv = 0;
-		mp3245_get_vbus(&mv, &ma);
-		/* Add new sample to cicrcular delay buffer */
-		mv_buffer[i & MP4245_VOLTAGE_WINDOW_MASK] = mv;
-		/*
-		 * Don't compute average until sample delay buffer is
-		 * full.
-		 */
-		if (i >= (MP4245_VOLTAGE_WINDOW_MASK)) {
-			int sum = 0;
-			int j;
-
-			/* Sum the voltage samples */
-			for (j = 0; j < MP4245_VOLTAGE_WINDOW; j++)
-				sum += mv_buffer[j];
-			/* Add rounding */
-			sum += MP4245_VOLTAGE_WINDOW / 2;
-			mv_average = sum / MP4245_VOLTAGE_WINDOW;
-			/*
-			 * Check if average is within the target
-			 * voltage range.
-			 */
-			if ((mv_average >= vbus_lo) &&
-			    (mv_average <= vbus_hi)) {
-				CPRINTS("usbc[%d]: VBUS to %d mV in %d steps",
-					port, target_mv, i);
-				return;
-			}
-		}
-
-		/*
-		 * The voltage ramp from 5V to 20V requires ~30
-		 * msec. The max loop count and this sleep time gives plenty
-		 * of time for this change.
-		 */
-		msleep(2);
-	}
-
-	CPRINTS("usbc[%d]: Vbus transition timeout: target = %d, measure = %d",
-		port, target_mv, mv_average);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
-		return c1_ps8805_is_vbus_present(port);
-	else
-		return ppc_is_vbus_present(port);
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	if (level == VBUS_PRESENT)
-		return pd_snk_is_vbus_provided(port);
-	else
-		return !pd_snk_is_vbus_provided(port);
-}
-
-int board_vbus_source_enabled(int port)
-{
-	if (IS_ENABLED(BOARD_C1_NO_PPC) && port)
-		return c1_ps8805_is_sourcing_vbus(port);
-	else
-		return ppc_is_sourcing_vbus(port);
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-
-}
-
-int pd_check_data_swap(int port,
-	enum pd_data_role data_role)
-{
-	int swap = 0;
-
-	if (port == 0)
-		swap = (data_role == PD_ROLE_DFP);
-	else if (port == 1)
-		swap = (data_role == PD_ROLE_UFP);
-
-	return swap;
-}
-
-int pd_check_power_swap(int port)
-{
-
-	if (pd_get_power_role(port) == PD_ROLE_SINK)
-		return 1;
-
-	return 0;
-}
-
-#ifdef BOARD_C1_1A5_LIMIT
-__override int typec_get_default_current_limit_rp(int port)
-{
-	int rp = TYPEC_RP_USB;
-
-	if (port == USB_PD_PORT_HOST)
-		rp = TYPEC_RP_3A0;
-	else if (port == USB_PD_PORT_DP)
-		rp = TYPEC_RP_1A5;
-
-	return rp;
-}
-#endif
-
-static void usb_tc_connect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	/*
-	 * The EC needs to indicate to the USB hub when the host port is
-	 * attached so that the USB-EP can be properly enumerated. GPIO_BPWR_DET
-	 * is used for this purpose.
-	 */
-	if (port == USB_PD_PORT_HOST) {
-		gpio_set_level(GPIO_BPWR_DET, 1);
-#ifdef GPIO_UFP_PLUG_DET
-		gpio_set_level(GPIO_UFP_PLUG_DET, 0);
-#endif
-	}
-
-	/* Clear data role swap attempt counter at each usbc attach */
-	pd_dr_swap_attempt_count[port] = 0;
-}
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, usb_tc_connect, HOOK_PRIO_DEFAULT);
-
-static void usb_tc_disconnect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	/* Only the host port disconnect is relevant */
-	if (port == USB_PD_PORT_HOST) {
-		gpio_set_level(GPIO_BPWR_DET, 0);
-#ifdef GPIO_UFP_PLUG_DET
-		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
-#endif
-	}
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT);
-
-__override bool pd_can_charge_from_device(int port, const int pdo_cnt,
-				      const uint32_t *pdos)
-{
-	/*
-	 * This function is called to determine if this port can be charged by
-	 * the port partner. We always want to be a power role source, so always
-	 * return false.
-	 */
-
-	return false;
-}
-
-static int vdm_is_dp_enabled(int port)
-{
-	mux_state_t mux_state = usb_mux_get(port);
-
-	return !!(mux_state & USB_PD_MUX_DP_ENABLED);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_HUB, /* UFP product type usbpd hub */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 0, /* Data caps as USB host     */
-				 1, /* Data caps as USB device   */
-				 IDH_PTYPE_HUB,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_UNDEFINED,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_RECONFIGURE,
-				   USB_R30_SS_U32_U40_GEN2);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	int vdo_count;
-
-	/* Verify that SVID is PD SID */
-	if (PD_VDO_VID(payload[0]) != USB_SID_PD) {
-		return 0;
-	}
-
-	/* Cstat and Product VDOs don't depend on spec revision */
-	payload[VDO_INDEX_CSTAT] = VDO_CSTAT(0);
-	payload[VDO_INDEX_PRODUCT] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_INDEX_IDH] = vdo_idh_rev30;
-		payload[VDO_INDEX_PTYPE_UFP1_VDO] = vdo_ufp1;
-		vdo_count = VDO_INDEX_PTYPE_UFP1_VDO;
-	} else {
-		payload[VDO_INDEX_IDH] = vdo_idh;
-		vdo_count = VDO_INDEX_PRODUCT;
-	}
-
-	/* Adjust VDO count for VDM header */
-	return vdo_count + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	/* Verify that SVID is PD SID */
-	if (PD_VDO_VID(payload[0]) != USB_SID_PD) {
-		return 0;
-	}
-
-	payload[1] = USB_SID_DISPLAYPORT << 16;
-	/* number of data objects VDO header + 1 SVID for DP */
-	return 2;
-}
-
-#define OPOS_DP 1
-
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */
-		    MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E,
-		    0, /* DFP pin cfg supported */
-		    0,		   /* usb2.0 signalling in AMode may be req */
-		    CABLE_RECEPTACLE,	   /* its a receptacle */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes));
-		return ARRAY_SIZE(vdo_dp_modes) + 1;
-	} else {
-		return 0; /* nak */
-	}
-}
-
-static int amode_dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = gpio_get_level(GPIO_DP_HPD);
-	int mf = dock_get_mf_preference();
-
-	if (opos != OPOS_DP)
-		return 0; /* nak */
-
-	payload[1] = VDO_DP_STATUS(0,		/* IRQ_HPD */
-				   (hpd == 1),	/* HPD_HI|LOW */
-				   0,		/* request exit DP */
-				   0,		/* request exit USB */
-				   mf,		/* MF pref */
-				   vdm_is_dp_enabled(port),
-				   0,		/* power low */
-				   0x2);
-	return 2;
-}
-
-static void svdm_configure_demux(int port, int enable, int mf)
-{
-	mux_state_t demux = usb_mux_get(port);
-
-	if (enable) {
-		demux |= USB_PD_MUX_DP_ENABLED;
-		/* 4 lane mode if MF is not preferred */
-		if (!mf)
-			demux &= ~USB_PD_MUX_USB_ENABLED;
-		/*
-		 * Make sure the MST_LANE_CONTROL gpio is set to match the DP
-		 * pin configuration selected by the host. Note that the mf
-		 * passed into this function reflects the pin configuration
-		 * selected by the host and not the user mf preference which is
-		 * stored in bit 0 of CBI fw_config.
-		 */
-		baseboard_set_mst_lane_control(mf);
-		CPRINTS("DP[%d]: DFP-D selected pin config %s",
-			port, mf ? "D" : "C");
-	} else {
-		demux &= ~USB_PD_MUX_DP_ENABLED;
-		demux |= USB_PD_MUX_USB_ENABLED;
-	}
-
-	/* Configure demux for 2/4 lane DP and USB3 configuration */
-	usb_mux_set(port, demux, USB_SWITCH_CONNECT, pd_get_polarity(port));
-}
-
-static int amode_dp_config(int port, uint32_t *payload)
-{
-	uint32_t dp_config = payload[1];
-	int mf;
-
-	/*
-	 * Check pin assignment selected by DFP_D to determine if 2 lane or 4
-	 * lane DP ALT-MODe is required. (note PIN_C is for 4 lane and PIN_D is
-	 * for 2 lane mode).
-	 */
-	mf = ((dp_config >> 8) & 0xff) == MODE_DP_PIN_D ? 1 : 0;
-	/* Configure demux for DP mode */
-	svdm_configure_demux(port, 1, mf);
-	/* Notify hpd->pd conv that a DP_CONFIG message has been received */
-	pd_ufp_enable_hpd_send(port);
-
-	return 1;
-}
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	int rv = 0; /* will generate a NAK */
-
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
-	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
-
-		/* Store valid object position to indicate mode is active */
-		pd_ufp_set_dp_opos(port, OPOS_DP);
-
-		/* Entering ALT-DP mode, enable DP connection in demux */
-		usb_pd_hpd_converter_enable(1);
-
-		/* ACK response has 1 VDO */
-		rv = 1;
-	}
-
-	CPRINTS("svdm_enter[%d]: svid = %x, ret = %d", port,
-		PD_VDO_VID(payload[0]), rv);
-
-	return rv;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	int opos = pd_ufp_get_dp_opos(port);
-
-	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
-	    (opos == OPOS_DP)) {
-		/* Clear mode active object position */
-		pd_ufp_set_dp_opos(port, 0);
-		/* Configure demux to disable DP mode */
-		svdm_configure_demux(port, 0, 0);
-		usb_pd_hpd_converter_enable(0);
-
-		return 1;
-	} else {
-		CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]);
-		return 0;
-	}
-}
-
-static struct amode_fx dp_fx = {
-	.status = &amode_dp_status,
-	.config = &amode_dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	/* We don't support, so ignore this message */
-	return 0;
-}
diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c
deleted file mode 100644
index 4d7049ad37..0000000000
--- a/baseboard/honeybuns/usbc_support.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USBC functions for RO */
-
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "sn5s330.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-#include "registers.h"
-#include "ucpd-stm32gx.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-enum usbc_states {
-	UNATTACHED_SNK,
-	ATTACH_WAIT_SNK,
-	ATTACHED_SNK,
-};
-
-/* Variables used to manage the simple usbc state machine */
-static int usbc_port;
-static int usbc_state;
-static int usbc_vbus;
-static enum tcpc_cc_voltage_status cc1_v;
-static enum tcpc_cc_voltage_status cc2_v;
-
-__maybe_unused static __const_data const char * const usbc_state_names[] = {
-	[UNATTACHED_SNK] = "Unattached.SNK",
-	[ATTACH_WAIT_SNK] = "AttachWait.SNK",
-	[ATTACHED_SNK] = "Attached.SNK",
-};
-
-static int read_reg(uint8_t port, int reg, int *regval)
-{
-	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
-}
-
-static int write_reg(uint8_t port, int reg, int regval)
-{
-	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
-}
-
-static int baseboard_ppc_enable_sink_path(int port)
-{
-	int regval;
-	int status;
-	int retries;
-
-	/*
-	 * It seems that sometimes setting the FUNC_SET1 register fails
-	 * initially.  Therefore, we'll retry a couple of times.
-	 */
-	retries = 0;
-	do {
-		status = write_reg(port, SN5S330_FUNC_SET1, SN5S330_ILIM_3_06);
-		if (status) {
-			retries++;
-			msleep(1);
-		} else {
-			break;
-		}
-	} while (retries < 10);
-
-	/* Turn off dead battery resistors, turn on CC FETs */
-	status = read_reg(port, SN5S330_FUNC_SET4, &regval);
-	if (!status) {
-		regval |= SN5S330_CC_EN;
-		status = write_reg(port, SN5S330_FUNC_SET4, regval);
-	}
-	if (status) {
-		return status;
-	}
-
-	/* Enable sink path via PP2 */
-	status = read_reg(port, SN5S330_FUNC_SET3, &regval);
-	if (!status) {
-		regval &= ~SN5S330_PP1_EN;
-		regval |= SN5S330_PP2_EN;
-		status = write_reg(port, SN5S330_FUNC_SET3, regval);
-	}
-	if (status) {
-		return status;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void baseboard_ucpd_apply_rd(int port)
-{
-	uint32_t cfgr1_reg;
-	uint32_t moder_reg;
-	uint32_t cr;
-
-	/* Ensure that clock to UCPD is enabled */
-	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
-
-	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
-	moder_reg = STM32_GPIO_MODER(GPIO_B);
-	moder_reg |= 0x3300;
-	STM32_GPIO_MODER(GPIO_B) = moder_reg;
-	/*
-	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
-	 * disabling ucpd causes the peripheral to quit any ongoing activity and
-	 * sets all ucpd registers back their default values.
-	 */
-
-	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
-	STM32_UCPD_CFGR1(port) = cfgr1_reg;
-
-	/* Enable ucpd  */
-	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN;
-
-	/* Apply Rd to both CC lines */
-	cr = STM32_UCPD_CR(port);
-	cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
-	STM32_UCPD_CR(port) = cr;
-
-	/*
-	 * After exiting reset, stm32gx will have dead battery mode enabled by
-	 * default which connects Rd to CC1/CC2. This should be disabled when EC
-	 * is powered up.
-	 */
-	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
-}
-
-
-static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int vstate_cc1;
-	int vstate_cc2;
-	int anamode;
-	uint32_t sr;
-
-	/*
-	 * cc_voltage_status is determined from vstate_cc bit field in the
-	 * status register. The meaning of the value vstate_cc depends on
-	 * current value of ANAMODE (src/snk).
-	 *
-	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
-	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
-	 * If presenting Rp (source), then need to to a circular shift of
-	 * vstate_ccx value:
-	 *     vstate_cc | cc_state
-	 *     ------------------
-	 *        0     ->    1
-	 *        1     ->    2
-	 *        2     ->    0
-	 */
-
-	/* Get vstate_ccx values and power role */
-	sr = STM32_UCPD_SR(port);
-	/* Get Rp or Rd active */
-	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
-	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
-
-	/* Do circular shift if port == source */
-	if (anamode) {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc1 += 4;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc2 += 4;
-	} else {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc1 = (vstate_cc1 + 1) % 3;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc2 = (vstate_cc2 + 1) % 3;
-	}
-
-	*cc1 = vstate_cc1;
-	*cc2 = vstate_cc2;
-}
-
-static int baseboard_rp_is_present(enum tcpc_cc_voltage_status cc1,
-				   enum tcpc_cc_voltage_status cc2)
-{
-	return (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF);
-}
-
-static void baseboard_usbc_check_connect(void);
-DECLARE_DEFERRED(baseboard_usbc_check_connect);
-
-static void baseboard_usbc_check_connect(void)
-{
-	enum tcpc_cc_voltage_status cc1;
-	enum tcpc_cc_voltage_status cc2;
-	int ppc_reg;
-	enum usbc_states enter_state = usbc_state;
-
-	/*
-	 * In RO, the only usbc related requirement is to enable the stm32g4
-	 * USB-EP to be enumerated by the host attached to C0. To prevent D+
-	 * being pulled high prior to VBUS presence, the EC uses GPIO_BPWR_DET
-	 * to signal the USB hub that VBUS is present. Therefore, we need a
-	 * simple usbc state machine to detect an attach (Rp and VBUS) event so
-	 * this GPIO signal is properly controlled in RO.
-	 *
-	 * Note that RO only runs until the RWSIG timer expires and jumps to RW,
-	 * and in RW, the full usb-pd stack is initialized and run.
-	 */
-
-	/* Get current CC voltage levels */
-	baseboard_ucpd_get_cc(usbc_port, &cc1, &cc2);
-	/* Update VBUS state */
-	if (!read_reg(usbc_port, SN5S330_INT_STATUS_REG3, &ppc_reg))
-		usbc_vbus = ppc_reg & SN5S330_VBUS_GOOD;
-
-	switch (usbc_state) {
-	case UNATTACHED_SNK:
-		/*
-		 * Require either CC1 or CC2 to have a valid Rp CC voltage level
-		 * to advance to ATTACH_WAIT_SNK.
-		 */
-		if (baseboard_rp_is_present(cc1, cc2))
-			usbc_state = ATTACH_WAIT_SNK;
-		break;
-	case ATTACH_WAIT_SNK:
-		/*
-		 * This state handles debounce by ensuring the CC voltages are
-		 * the same between two state machine iterations. If this
-		 * condition is met, and VBUS is present, then advance to
-		 * ATTACHED_SNK and set GPIO_BPWR_DET.
-		 *
-		 * If Rp voltage is no longer detected, then return to
-		 * UNATTACHED_SNK.
-		 */
-		if (usbc_vbus && cc1 == cc1_v && cc2 == cc2_v) {
-			usbc_state = ATTACHED_SNK;
-			gpio_set_level(GPIO_BPWR_DET, 1);
-		} else if (!baseboard_rp_is_present(cc1, cc2)) {
-			usbc_state = UNATTACHED_SNK;
-		}
-		break;
-	case ATTACHED_SNK:
-		/*
-		 * In this state, only checking for VBUS going away to indicate
-		 * a detach event and inform the USB hub via GPIO_BPWR_DET.
-		 */
-		if (!usbc_vbus) {
-			usbc_state = UNATTACHED_SNK;
-			gpio_set_level(GPIO_BPWR_DET, 0);
-		}
-		break;
-	}
-
-	/* Save CC voltage for debounce check */
-	cc1_v = cc1;
-	cc2_v = cc2;
-
-	if (enter_state != usbc_state)
-		CPRINTS("%s: cc1 = %d, cc2 = %d vbus = %d",
-			usbc_state_names[usbc_state], cc1, cc2, usbc_vbus);
-
-	hook_call_deferred(&baseboard_usbc_check_connect_data,
-			   PD_T_TRY_CC_DEBOUNCE);
-}
-
-int baseboard_usbc_init(int port)
-{
-	int rv;
-
-	/* Initialize ucpd and apply Rd to CC lines */
-	baseboard_ucpd_apply_rd(port);
-	/* Initialize ppc to enable sink path */
-	rv = baseboard_ppc_enable_sink_path(port);
-	if (rv)
-		CPRINTS("ppc init failed!");
-	/* Save host port value */
-	usbc_port = port;
-	/* Start RO usbc attach state machine */
-	gpio_set_level(GPIO_BPWR_DET, 0);
-	/* Start simple usbc state machine */
-	baseboard_usbc_check_connect();
-
-	return rv;
-}
-
-#ifdef SECTION_IS_RW
-int c1_ps8805_is_vbus_present(int port)
-{
-	int vbus;
-
-	vbus = tcpm_check_vbus_level(port, VBUS_PRESENT);
-
-	return vbus;
-}
-
-int c1_ps8805_is_sourcing_vbus(int port)
-{
-	int rv;
-	int level;
-
-	rv = ps8805_gpio_get_level(port, PS8805_GPIO_1, &level);
-	if (rv)
-		return 0;
-
-	return level;
-}
-
-
-int c1_ps8805_vbus_source_enable(int port, int enable)
-{
-
-	return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable);
-}
-
-__override bool usb_ufp_check_usb3_enable(int port)
-{
-	/* USB3.1 mux should be enabled based on UFP data role */
-	return port == USB_PD_PORT_HOST;
-}
-
-#ifdef GPIO_USBC_UF_ATTACHED_SRC
-static int ppc_ocp_count;
-
-static void baseboard_usb3_manage_vbus(void)
-{
-	int level = gpio_get_level(GPIO_USBC_UF_ATTACHED_SRC);
-
-	/*
-	 * GPIO_USBC_UF_MUX_VBUS_EN is an output from the PS8803 which tracks if
-	 * C2 is attached. When it's attached, this signal will be high. Use
-	 * this level to control PPC VBUS on/off.
-	 */
-	ppc_vbus_source_enable(USB_PD_PORT_USB3, level);
-	CPRINTS("C2: State = %s", level ? "Attached.SRC " : "Unattached.SRC");
-
-	/* Reset OCP event counter for detach */
-	if (!level) {
-		ppc_ocp_count = 0;
-
-#ifdef GPIO_USB_HUB_OCP_NOTIFY
-	/*
-	 * In the case of an OCP event on this port, the usb hub should be
-	 * notified via a GPIO signal. Following, an OCP, the attached.src state
-	 * for the usb3 only port is checked again. If it's attached, then make
-	 * sure the OCP notify signal is reset.
-	 */
-		gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1);
-#endif
-	}
-}
-DECLARE_DEFERRED(baseboard_usb3_manage_vbus);
-
-void baseboard_usb3_check_state(void)
-{
-	hook_call_deferred(&baseboard_usb3_manage_vbus_data, 0);
-}
-
-void baseboard_usbc_usb3_enable_interrupts(int enable)
-{
-	if (enable) {
-		/* Enable VBUS control interrupt for C2 */
-		gpio_enable_interrupt(GPIO_USBC_UF_ATTACHED_SRC);
-		/* Enable PPC interrupt */
-		gpio_enable_interrupt(GPIO_USBC_UF_PPC_INT_ODL);
-	} else {
-		/* Disable VBUS control interrupt for C2 */
-		gpio_disable_interrupt(GPIO_USBC_UF_ATTACHED_SRC);
-		/* Disable PPC interrupt */
-		gpio_disable_interrupt(GPIO_USBC_UF_PPC_INT_ODL);
-	}
-}
-
-int baseboard_config_usbc_usb3_ppc(void)
-{
-	int rv;
-
-	/*
-	 * This port is not usb-pd capable, but there is a ppc which must be
-	 * initialized, and keep the VBUS switch enabled.
-	 */
-	rv = ppc_init(USB_PD_PORT_USB3);
-	if (rv)
-		return rv;
-
-	/* Need to set current limit to 3A to match advertised value */
-	ppc_set_vbus_source_current_limit(USB_PD_PORT_USB3, TYPEC_RP_3A0);
-	/* Reset OCP event counter */
-	ppc_ocp_count = 0;
-
-	/* Check state at init time */
-	baseboard_usb3_manage_vbus();
-
-	/* Enable attached.src and PPC interrupts */
-	baseboard_usbc_usb3_enable_interrupts(1);
-
-	return EC_SUCCESS;
-}
-
-static void baseboard_usbc_usb3_handle_interrupt(void)
-{
-	int port = USB_PD_PORT_USB3;
-
-	/*
-	 * SN5S330's /INT pin is level, so process interrupts until it
-	 * deasserts if the chip has a dedicated interrupt pin.
-	 */
-	while (gpio_get_level(GPIO_USBC_UF_PPC_INT_ODL) == 0) {
-		int rise = 0;
-		int fall = 0;
-
-		read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise);
-		read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall);
-
-		/* Notify the system about the overcurrent event. */
-		if (rise & SN5S330_ILIM_PP1_MASK) {
-			CPRINTS("usb3_ppc: VBUS OC!");
-			gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0);
-			if (++ppc_ocp_count < 5)
-				hook_call_deferred(&baseboard_usb3_manage_vbus_data,
-						   USB_HUB_OCP_RESET_MSEC);
-			else
-				CPRINTS("usb3_ppc: VBUS OC limit reached!");
-		}
-
-		/* Clear the interrupt sources. */
-		write_reg(port, SN5S330_INT_TRIP_RISE_REG1, rise);
-		write_reg(port, SN5S330_INT_TRIP_FALL_REG1, fall);
-
-		read_reg(port, SN5S330_INT_TRIP_RISE_REG2, &rise);
-		read_reg(port, SN5S330_INT_TRIP_FALL_REG2, &fall);
-
-		/*
-		 * VCONN may be latched off due to an overcurrent.  Indicate
-		 * when the VCONN overcurrent happens.
-		 */
-		if (rise & SN5S330_VCONN_ILIM)
-			CPRINTS("usb3_ppc: VCONN OC!");
-
-		/*
-		 * CC overvoltage event. There is not action to take here, but
-		 * log the event.
-		 */
-		if (rise & SN5S330_CC1_CON || rise & SN5S330_CC2_CON)
-			CPRINTS("usb3_ppc: CC OV!");
-
-		/* Clear the interrupt sources. */
-		write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise);
-		write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall);
-
-	}
-}
-DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt);
-
-void baseboard_usbc_usb3_irq(void)
-{
-	hook_call_deferred(&baseboard_usbc_usb3_handle_interrupt_data, 0);
-}
-
-#endif /* defined(GPIO_USBC_UF_ATTACHED_SRC) */
-#endif /* defined(SECTION_IS_RW) */
-
diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md
deleted file mode 100644
index 39286e130d..0000000000
--- a/baseboard/intelrvp/README.md
+++ /dev/null
@@ -1,53 +0,0 @@
-This folder is for the baseboard for the board specific files which use Intel
-Reference Validation Platform (RVP) for developing the EC and other peripherals
-which can be hooked on EC or RVP.
-
-This baseboard follows the Intel Modular Embedded Controller Card (MECC)
-specification for pinout and these pin definitions remain same on all the RVPs.
-Chrome MECC spec is standardized for Icelake and successor RVPs hence this
-baseboard code is applicable to Icelake and its successors only.
-
-Following hardware features are supported on MECC header by RVP and can be
-validated by software by MECC.
-
-## MECC version 0.9 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header need to be added by MECC
-4.  Google H1 chip need to be added by MECC (optional for EC vendors)
-5.  2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer)
-6.  6 Temperature sensors
-7.  4 ADC
-8.  4 I2C Channels
-9.  1 Fan control
-
-## MECC version 1.0 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header need to be added by MECC
-4.  Google H1 chip need to be added by MECC (optional for EC vendors)
-5.  4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on
-    RVP
-6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
-7.  6 I2C Channels
-8.  2 SMLINK Channels
-9.  2 I3C channels
-
-## MECC version 1.1 features
-
-1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
-2.  Power control pins for Intel SOC are added
-3.  Servo V2 header is added on RVP as an AIC
-4.  Google H1 chip is added on RVP as an AIC
-5.  4 Type-C port support (SRC/SNK/MUX/Rerimer) as an (AIC)
-6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
-7.  6 I2C Channels
-8.  2 SMLINK Channels
-9.  2 I3C channels
-10. 1 Fan control
-11. 4 ADC based temperature sensors
-12. PECI control
-13. I2C based Keyboard is added on RVP as an AIC
-14. Both Google & Intel CCD support is added on RVP on Type-C port 0
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c
deleted file mode 100644
index 78f4b3613a..0000000000
--- a/baseboard/intelrvp/adlrvp.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP board-specific common configuration */
-
-#include "charger.h"
-#include "common.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "isl9241.h"
-#include "pca9675.h"
-#include "power/icelake.h"
-#include "sn5s330.h"
-#include "system.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* TCPC AIC GPIO Configuration */
-const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P0,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P1,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P3,
-		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
-		.ppc_intr_handler = sn5s330_interrupt,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB-C PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[TYPE_C_PORT_0] = {
-		.i2c_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.i2c_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.i2c_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.i2c_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
-		.drv = &sn5s330_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USB-C retimer Configuration */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#if defined(HAS_TASK_PD_C1)
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-#if defined(HAS_TASK_PD_C2)
-struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-#if defined(HAS_TASK_PD_C3)
-struct usb_mux usbc3_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_3,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-#endif
-
-/* USB muxes Configuration */
-struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.usb_port = TYPE_C_PORT_2,
-		.next_mux = &usbc2_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.usb_port = TYPE_C_PORT_3,
-		.next_mux = &usbc3_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */
-struct usb_mux soc_side_bb_retimer0_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.next_mux = &usbc0_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_0,
-	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
-};
-
-#if defined(HAS_TASK_PD_C1)
-struct usb_mux soc_side_bb_retimer1_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.next_mux = &usbc1_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_1,
-	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
-};
-#endif
-
-const struct bb_usb_control bb_controls[] = {
-	[TYPE_C_PORT_0] = {
-		.retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.retimer_rst_gpio = IOEX_USB_C1_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C1_BB_RETIMER_LS_EN,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.retimer_rst_gpio = IOEX_USB_C2_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C2_BB_RETIMER_LS_EN,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.retimer_rst_gpio = IOEX_USB_C3_BB_RETIMER_RST,
-		.usb_ls_en_gpio = IOEX_USB_C3_BB_RETIMER_LS_EN,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* Cache BB retimer power state */
-static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Each TCPC have corresponding IO expander and are available in pair */
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-	[IOEX_C1_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[IOEX_C2_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-	[IOEX_C3_PCA9675] = {
-		.i2c_host_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
-		.drv = &pca9675_ioexpander_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
-#if defined(HAS_TASK_PD_C2)
-	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ?
-				IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC;
-#else
-	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
-#endif
-
-	/* Overcurrent indication is active low signal */
-	ioex_set_level(oc_signal, is_overcurrented ? 0 : 1);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	/*
-	 * ADL-P-DDR5 RVP SKU has cascaded retimer topology.
-	 * Ports with cascaded retimers share common load switch and reset pin
-	 * hence no need to set the power state again if the 1st retimer's power
-	 * status has already changed.
-	 */
-	if (cache_bb_enable[me->usb_port] == enable)
-		return EC_SUCCESS;
-
-	cache_bb_enable[me->usb_port] = enable;
-
-	/* Handle retimer's power domain.*/
-	if (enable) {
-		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 1);
-
-		/*
-		 * minimum time from VCC to RESET_N de-assertion is 100us
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		msleep(1);
-		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 1);
-
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-
-	} else {
-		ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 0);
-		msleep(1);
-		ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 0);
-	}
-	return EC_SUCCESS;
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
-
-	if (ccd_intr_level) {
-		/* Default set the SBU lines to AUX mode on TCPC-AIC */
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0);
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
-	} else {
-		/* Set the SBU lines to CCD mode on TCPC-AIC */
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1);
-		ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0);
-	}
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
-DECLARE_HOOK(HOOK_INIT, board_connect_c0_sbu_deferred, HOOK_PRIO_INIT_I2C + 2);
-
-void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void enable_h1_irq(void)
-{
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
-
-static void configure_retimer_usbmux(void)
-{
-	switch (ADL_RVP_BOARD_ID(board_get_version())) {
-	case ADLN_LP5_ERB_SKU_BOARD_ID:
-	case ADLN_LP5_RVP_SKU_BOARD_ID:
-		/* No retimer on Port0 & Port1 */
-		usb_muxes[TYPE_C_PORT_0].driver = NULL;
-#if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].driver = NULL;
-#endif
-		break;
-
-	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
-		/* No retimer on Port-2 */
-#if defined(HAS_TASK_PD_C2)
-		usb_muxes[TYPE_C_PORT_2].driver = NULL;
-#endif
-		break;
-
-	case ADLP_DDR5_RVP_SKU_BOARD_ID:
-		/*
-		 * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1.
-		 * Change the default usb mux config on runtime to support
-		 * dual retimer topology.
-		 */
-		usb_muxes[TYPE_C_PORT_0].next_mux
-			= &soc_side_bb_retimer0_usb_mux;
-#if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].next_mux
-			= &soc_side_bb_retimer1_usb_mux;
-#endif
-		break;
-
-	/* Add additional board SKUs */
-
-	default:
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, configure_retimer_usbmux, HOOK_PRIO_INIT_I2C + 1);
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
- * as input.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
-	{
-		.gpio = GPIO_SYS_PWROK_EC,
-		.delay_ms = 3,
-	},
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
-	{
-		.gpio = GPIO_SYS_PWROK_EC,
-	},
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-__override int board_get_version(void)
-{
-	/* Cache the ADLRVP board ID */
-	static int adlrvp_board_id;
-
-	int port0, port1;
-	int fab_id, board_id, bom_id;
-
-	/* Board ID is already read */
-	if (adlrvp_board_id)
-		return adlrvp_board_id;
-
-	if (ioexpander_read_intelrvp_version(&port0, &port1))
-		return -1;
-	/*
-	 * Port0: bit 0   - BOM ID(2)
-	 *        bit 2:1 - FAB ID(1:0) + 1
-	 * Port1: bit 7:6 - BOM ID(1:0)
-	 *        bit 5:0 - BOARD ID(5:0)
-	 */
-	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
-	fab_id = ((port0 & 0x06) >> 1) + 1;
-	board_id = port1 & 0x3F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	adlrvp_board_id = board_id | (fab_id << 8);
-	return adlrvp_board_id;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	bool tbt_usb4 = true;
-
-	switch (ADL_RVP_BOARD_ID(board_get_version())) {
-	case ADLN_LP5_ERB_SKU_BOARD_ID:
-	case ADLN_LP5_RVP_SKU_BOARD_ID:
-		/* No retimer on both ports */
-		tbt_usb4 = false;
-		break;
-
-	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
-		/* No retimer on Port-2 hence no platform level AUX & LSx mux */
-#if defined(HAS_TASK_PD_C2)
-		if (port == TYPE_C_PORT_2)
-			tbt_usb4 = false;
-#endif
-		break;
-
-	/* Add additional board SKUs */
-	default:
-		break;
-	}
-
-	return tbt_usb4;
-}
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h
deleted file mode 100644
index 31bfc5aded..0000000000
--- a/baseboard/intelrvp/adlrvp.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-RVP specific configuration */
-
-#ifndef __ADLRVP_BOARD_H
-#define __ADLRVP_BOARD_H
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-#include "baseboard.h"
-
-/* RVP Board ids */
-#define CONFIG_BOARD_VERSION_GPIO
-#define ADLN_LP5_ERB_SKU_BOARD_ID	0x06
-#define ADLN_LP5_RVP_SKU_BOARD_ID	0x07
-#define ADLP_DDR5_RVP_SKU_BOARD_ID	0x12
-#define ADLP_LP5_T4_RVP_SKU_BOARD_ID	0x13
-#define ADL_RVP_BOARD_ID(id)		((id) & 0x3F)
-
-/* MECC config */
-#define CONFIG_INTEL_RVP_MECC_VERSION_1_0
-
-/* Support early firmware selection */
-#define CONFIG_VBOOT_EFS2
-
-/* Chipset */
-#define CONFIG_CHIPSET_ALDERLAKE
-
-/* USB PD config */
-#if defined(HAS_TASK_PD_C3)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 4
-#elif defined(HAS_TASK_PD_C2)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#elif defined(HAS_TASK_PD_C1)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#else
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#endif
-#define CONFIG_USB_MUX_VIRTUAL
-#define PD_MAX_POWER_MW              100000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-/* TCPC AIC config */
-/* Support NXP PCA9675 I/O expander. */
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_PCA9675
-#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX	0x21
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
-
-/* PPC */
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define I2C_ADDR_SN5S330_TCPC_AIC_PPC	0x40
-
-/* TCPC */
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define I2C_ADDR_FUSB302_TCPC_AIC	0x22
-
-/* Config BB retimer */
-#define CONFIG_USBC_RETIMER_INTEL_BB
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Connector side BB retimers */
-#define I2C_PORT0_BB_RETIMER_ADDR	0x56
-#if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_ADDR	0x57
-#endif
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT2_BB_RETIMER_ADDR	0x58
-#endif
-#if defined(HAS_TASK_PD_C3)
-#define I2C_PORT3_BB_RETIMER_ADDR	0x59
-#endif
-
-/* SOC side BB retimers (dual retimer config) */
-#define I2C_PORT0_BB_RETIMER_SOC_ADDR	0x54
-#if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_SOC_ADDR	0x55
-#endif
-
-/* I2C EEPROM */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
-#define I2C_PORT_EEPROM         I2C_PORT_PCA9555_BOARD_ID_GPIO
-
-/* Enable CBI */
-#define CONFIG_CBI_EEPROM
-
-/* Configure mux at runtime */
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Enable VCONN */
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Enable low power mode */
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Config Fan */
-#define CONFIG_FANS		1
-#define BOARD_FAN_MIN_RPM	3000
-#define BOARD_FAN_MAX_RPM	10000
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9241
-
-/* Port 80 */
-#define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
-
-/* Board Id */
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-
-/*
- * Frequent watchdog timer resets are seen, with the
- * increase in number of type-c ports. So increase
- * the timer value to support more type-c ports.
- */
-#ifdef VARIANT_INTELRVP_EC_IT8320
-#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3)
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 4000
-#endif
-#endif
-
-/*
- * Enable support for battery hostcmd, supporting longer strings.
- * Support for EC_CMD_BATTERY_GET_STATIC version 1.
- */
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT	1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_charge_ports {
-	TYPE_C_PORT_0,
-#if defined(HAS_TASK_PD_C1)
-	TYPE_C_PORT_1,
-#endif
-#if defined(HAS_TASK_PD_C2)
-	TYPE_C_PORT_2,
-#endif
-#if defined(HAS_TASK_PD_C3)
-	TYPE_C_PORT_3,
-#endif
-};
-
-/*
- * Each Type-C add in card has two I/O expanders hence even if one Type-C port
- * is enabled other I/O expander is available for usage.
- */
-enum ioex_port {
-	IOEX_C0_PCA9675,
-	IOEX_C1_PCA9675,
-#if defined(HAS_TASK_PD_C2)
-	IOEX_C2_PCA9675,
-	IOEX_C3_PCA9675,
-#endif
-	IOEX_PORT_COUNT
-};
-#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
-
-enum battery_type {
-	BATTERY_GETAC_SMP_HHP_408,
-	BATTERY_TYPE_COUNT,
-};
-
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
-void extpower_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-void board_connect_c0_sbu(enum gpio_signal s);
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __ADLRVP_BOARD_H */
diff --git a/baseboard/intelrvp/adlrvp_battery2s.c b/baseboard/intelrvp/adlrvp_battery2s.c
deleted file mode 100644
index bc61b407a0..0000000000
--- a/baseboard/intelrvp/adlrvp_battery2s.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Getac Battery (Getac SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50-R3
-	 */
-	[BATTERY_GETAC_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "Getac",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8800,        /* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408;
-
diff --git a/baseboard/intelrvp/adlrvp_battery3s.c b/baseboard/intelrvp/adlrvp_battery3s.c
deleted file mode 100644
index 315d5c247e..0000000000
--- a/baseboard/intelrvp/adlrvp_battery3s.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Getac Battery (Getac SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50-R3
-	 */
-	[BATTERY_GETAC_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "Getac",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 13050,        /* mV */
-			.voltage_normal = 11400,
-			.voltage_min = 9000,
-			.precharge_current = 256,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408;
-
diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
deleted file mode 100644
index e5522b02b3..0000000000
--- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc
+++ /dev/null
@@ -1,31 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-IOEX(USB_C0_BB_RETIMER_RST,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C0_BB_RETIMER_LS_EN,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C0_USB_MUX_CNTRL_1,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
-IOEX(USB_C0_USB_MUX_CNTRL_0,	EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
-
-IOEX(USB_C1_BB_RETIMER_RST,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C1_BB_RETIMER_LS_EN,	EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C0_C1_OC,		EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
-
-#if defined(HAS_TASK_PD_C2)
-IOEX(USB_C2_BB_RETIMER_RST,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C2_BB_RETIMER_LS_EN,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C2_USB_MUX_CNTRL_1,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW)
-IOEX(USB_C2_USB_MUX_CNTRL_0,	EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW)
-
-IOEX(USB_C3_BB_RETIMER_RST,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW)
-IOEX(USB_C3_BB_RETIMER_LS_EN,	EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW)
-IOEX(USB_C2_C3_OC,		EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH)
-#endif
-
-/* ADL-RVP has custom GPIO implementation for reading board ID */
-UNIMPLEMENTED(BOARD_VERSION1)
-UNIMPLEMENTED(BOARD_VERSION2)
-UNIMPLEMENTED(BOARD_VERSION3)
diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c
deleted file mode 100644
index 1e7b778c12..0000000000
--- a/baseboard/intelrvp/baseboard.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "adc_chip.h"
-#include "charge_state.h"
-#include "espi.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pca9555.h"
-#include "peci.h"
-#include "power.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-#ifdef CONFIG_TEMP_SENSOR
-/* Temperature sensors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SNS_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_AMBIENT,
-	},
-	[TEMP_SNS_BATTERY] = {
-		.name = "Battery",
-		.type = TEMP_SENSOR_TYPE_BATTERY,
-		.read = charge_get_battery_temp,
-		.idx = 0,
-	},
-	[TEMP_SNS_DDR] = {
-		.name = "DDR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_DDR,
-	},
-#ifdef CONFIG_PECI
-	[TEMP_SNS_PECI] = {
-		.name = "PECI",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = peci_temp_sensor_get_val,
-		.idx = 0,
-	},
-#endif /* CONFIG_PECI */
-	[TEMP_SNS_SKIN] = {
-		.name = "Skin",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_SKIN,
-	},
-	[TEMP_SNS_VR] = {
-		.name = "VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v0_22k6_47k_4050b,
-		.idx = ADC_TEMP_SNS_VR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(15),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SNS_AMBIENT] = thermal_a,
-	[TEMP_SNS_BATTERY] = thermal_a,
-	[TEMP_SNS_DDR] = thermal_a,
-#ifdef CONFIG_PECI
-	[TEMP_SNS_PECI] = thermal_a,
-#endif
-	[TEMP_SNS_SKIN] = thermal_a,
-	[TEMP_SNS_VR] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-#endif /* CONFIG_TEMP_SENSOR */
-
-#ifdef CONFIG_FANS
-/* Physical fan config */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,
-	.pgood_gpio = GPIO_ALL_SYS_PWRGD,
-	.enable_gpio = GPIO_FAN_POWER_EN,
-};
-
-/* Physical fan rpm config */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = BOARD_FAN_MIN_RPM,
-	.rpm_start = BOARD_FAN_MIN_RPM,
-	.rpm_max = BOARD_FAN_MAX_RPM,
-};
-
-/* FAN channels */
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-#endif /* CONFIG_FANS */
-
-static void board_init(void)
-{
-	/* Enable SOC SPI */
-	gpio_set_level(GPIO_EC_SPI_OE_N, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST);
-
-static void board_interrupts_init(void)
-{
-	/* DC Jack interrupt */
-	gpio_enable_interrupt(GPIO_DC_JACK_PRESENT);
-}
-DECLARE_HOOK(HOOK_INIT, board_interrupts_init, HOOK_PRIO_FIRST);
-
-int ioexpander_read_intelrvp_version(int *port0, int *port1)
-{
-	if (pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_0, port0))
-		return -1;
-
-	return pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-		I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-		PCA9555_CMD_INPUT_PORT_1, port1);
-}
-
-__override void intel_x86_sys_reset_delay(void)
-{
-	/*
-	 * From MAX6818 Data sheet, Range of 'Debounce Duaration' is
-	 * Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms.
-	 */
-	udelay(60 * MSEC);
-}
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
deleted file mode 100644
index de4cb671ac..0000000000
--- a/baseboard/intelrvp/baseboard.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP board-specific configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#include "compiler.h"
-#include "stdbool.h"
-
-#ifdef VARIANT_INTELRVP_EC_IT8320
-	#include "ite_ec.h"
-#elif defined(VARIANT_INTELRVP_EC_MCHP)
-	#include "mchp_ec.h"
-#elif defined(VARIANT_INTELRVP_EC_NPCX)
-	#include "npcx_ec.h"
-#else
-	#error "Define EC chip variant"
-#endif
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console commands  */
-#define CONFIG_CMD_CHARGER_DUMP
-#define CONFIG_CMD_KEYBOARD
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_CMD_USB_PD_PE
-
-/* Host commands  */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-/* Port80 display */
-#define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_SENSE_RESISTOR 5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_TRICKLE_CHARGING
-
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated)
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
-
-/* Keyboard */
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-
-/* UART */
-#define CONFIG_LOW_POWER_IDLE
-
-/* USB-A config */
-
-/* BC1.2 config */
-#ifdef HAS_TASK_USB_CHG_P0
-	#define CONFIG_CHARGE_RAMP_HW
-#endif
-
-/* Enable USB-PD REV 3.0 */
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x8086
-
-/* USB PD config */
-#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1)
-	#define CONFIG_USB_PD_TCPMV1
-	#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#else
-	#define CONFIG_USB_DRP_ACC_TRYSRC
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPM_MUX
-#endif
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-
-/* USB MUX */
-#ifdef CONFIG_USB_MUX_VIRTUAL
-	#define CONFIG_HOSTCMD_LOCATE_CHIP
-#endif
-#define CONFIG_USBC_SS_MUX
-
-/* SoC / PCH */
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_WP_ALWAYS
-
-/* Tablet mode */
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-
-/* Verified boot */
-#define CONFIG_CRC8
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VBOOT_HASH
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Temperature sensor */
-#ifdef CONFIG_TEMP_SENSOR
-	#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-	#define CONFIG_TEMP_SENSOR_POWER_GPIO   GPIO_EN_PP3300_A
-	#define CONFIG_THERMISTOR
-	#define CONFIG_THROTTLE_AP
-#ifdef CONFIG_PECI
-	#define CONFIG_PECI_COMMON
-#endif /* CONFIG_PECI */
-#endif /* CONFIG_TEMP_SENSOR */
-
-/* I2C ports */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* EC exclude modules */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "module_id.h"
-#include "registers.h"
-
-FORWARD_DECLARE_ENUM(tcpc_rp_value);
-
-/* PWM channels */
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-/* FAN channels */
-enum fan_channel {
-	FAN_CH_0,
-	FAN_CH_COUNT,
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_TEMP_SNS_AMBIENT,
-	ADC_TEMP_SNS_DDR,
-	ADC_TEMP_SNS_SKIN,
-	ADC_TEMP_SNS_VR,
-	ADC_CH_COUNT,
-};
-
-/* Temperature sensors */
-enum temp_sensor_id {
-	TEMP_SNS_AMBIENT,
-	TEMP_SNS_BATTERY,
-	TEMP_SNS_DDR,
-#ifdef CONFIG_PECI
-	TEMP_SNS_PECI,
-#endif
-	TEMP_SNS_SKIN,
-	TEMP_SNS_VR,
-	TEMP_SENSOR_COUNT,
-};
-
-/* TODO(b:132652892): Verify the below numbers. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* Define typical operating power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_VOLTAGE_MV      20000
-#define PD_MAX_CURRENT_MA      ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000)
-#define DC_JACK_MAX_VOLTAGE_MV 19000
-
-/* TCPC gpios */
-struct tcpc_gpio_t {
-	enum gpio_signal pin;
-	uint8_t pin_pol;
-};
-
-/* VCONN gpios */
-struct vconn_gpio_t {
-	enum gpio_signal cc1_pin;
-	enum gpio_signal cc2_pin;
-	uint8_t pin_pol;
-};
-
-struct tcpc_gpio_config_t {
-	/* VBUS interrput */
-	struct tcpc_gpio_t vbus;
-	/* Source enable */
-	struct tcpc_gpio_t src;
-	/* Sink enable */
-	struct tcpc_gpio_t snk;
-#if defined(CONFIG_USBC_VCONN) && defined(CHIP_FAMILY_IT83XX)
-	/* Enable VCONN */
-	struct vconn_gpio_t vconn;
-#endif
-	/* Enable source ILIM */
-	struct tcpc_gpio_t src_ilim;
-};
-extern const struct tcpc_gpio_config_t tcpc_gpios[];
-
-struct tcpc_aic_gpio_config_t {
-	/* TCPC interrupt */
-	enum gpio_signal tcpc_alert;
-	/* PPC interrupt */
-	enum gpio_signal ppc_alert;
-	/* PPC interrupt handler */
-	void (*ppc_intr_handler)(int port);
-};
-extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[];
-
-void board_charging_enable(int port, int enable);
-void board_vbus_enable(int port, int enable);
-void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp);
-int ioexpander_read_intelrvp_version(int *port0, int *port1);
-void board_dc_jack_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-bool is_typec_port(int port);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c
deleted file mode 100644
index 9f212fba4e..0000000000
--- a/baseboard/intelrvp/bc12.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP BC1.2 specific configuration */
-
-#include "common.h"
-#include "max14637.h"
-
-/* BC1.2 chip Configuration */
-#ifdef CONFIG_BC12_DETECT_MAX14637
-const struct max14637_config_t max14637_config[] = {
-	[TYPE_C_PORT_0] = {
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#ifdef HAS_TASK_PD_C1
-	[TYPE_C_PORT_1] = {
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-#endif /* HAS_TASK_PD_C1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-#endif /* CONFIG_BC12_DETECT_MAX14637 */
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
deleted file mode 100644
index 6abf8bbe0c..0000000000
--- a/baseboard/intelrvp/build.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-#Intel RVP common files
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o
-
-ifneq ($(CONFIG_USB_POWER_DELIVERY),)
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o
-baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o
-endif
-
-#EC specific files
-baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o
-baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
-baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o
-
-#BC1.2 specific files
-baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
-
-#Common board specific files
-ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \
-		$(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \
-		$(BOARD_ADLRVPP_MCHP1727)),)
-baseboard-y+=adlrvp.o
-ifneq ($(BOARD_ADLRVPM_ITE),)
-baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery2s.o
-else
-baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery3s.o
-endif
-endif
diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c
deleted file mode 100644
index 9f64cdd4e7..0000000000
--- a/baseboard/intelrvp/chg_usb_pd.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common USB PD charge configuration */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-bool is_typec_port(int port)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
-#else
-	return !(port == CHARGE_PORT_NONE);
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
-}
-
-static inline int board_dc_jack_present(void)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	return gpio_get_level(GPIO_DC_JACK_PRESENT);
-#else
-	return 0;
-#endif
-}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-static void board_dc_jack_handle(void)
-{
-	struct charge_port_info charge_dc_jack;
-
-	/* System is booted from DC Jack */
-	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
-		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
-	} else {
-		charge_dc_jack.current = 0;
-		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DEDICATED_CHARGE_PORT, &charge_dc_jack);
-}
-#endif
-
-void board_dc_jack_interrupt(enum gpio_signal signal)
-{
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	board_dc_jack_handle();
-#endif
-}
-
-static void board_charge_init(void)
-{
-	int port, supplier;
-	struct charge_port_info charge_init = {
-		.current = 0,
-		.voltage = USB_CHARGER_VOLTAGE_MV,
-	};
-
-	/* Initialize all charge suppliers to seed the charge manager */
-	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
-		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
-			charge_manager_update_charge(supplier, port,
-				&charge_init);
-	}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	board_dc_jack_handle();
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
-}
-DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
-
-int board_set_active_charge_port(int port)
-{
-	int i;
-	/* charge port is a realy physical port */
-	int is_real_port = (port >= 0 &&
-			port < CHARGE_PORT_COUNT);
-	/* check if we are source vbus on that port */
-	int source = board_vbus_source_enabled(port);
-
-	if (is_real_port && source) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	/*
-	 * Do not enable Type-C port if the DC Jack is present.
-	 * When the Type-C is active port, hardware circuit will
-	 * block DC jack from enabling +VADP_OUT.
-	 */
-	if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) {
-		CPRINTS("DC Jack present, Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
-
-	/* Make sure non-charging ports are disabled */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		board_charging_enable(i, 0);
-	}
-
-	/* Enable charging port */
-	if (is_typec_port(port))
-		board_charging_enable(port, 1);
-
-	CPRINTS("New chg p%d", port);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
deleted file mode 100644
index fa9f1e147f..0000000000
--- a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "console.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "system.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* Add code if TCPC chips need a reset */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	int src_en = 0;
-
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		src_en = gpio_get_level(tcpc_gpios[port].src.pin);
-
-		src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en;
-	}
-
-	return src_en;
-}
-
-void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int ilim_en;
-
-	/* Only Type-C ports can source VBUS */
-	if (is_typec_port(port)) {
-		/* Enable SRC ILIM if rp is MAX single source current */
-		ilim_en = (rp ==  TYPEC_RP_3A0 &&
-			board_vbus_source_enabled(port));
-
-		gpio_set_level(tcpc_gpios[port].src_ilim.pin,
-				tcpc_gpios[port].src_ilim.pin_pol ?
-				ilim_en : !ilim_en);
-	}
-}
-
-void board_charging_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].snk.pin,
-		tcpc_gpios[port].snk.pin_pol ? enable : !enable);
-
-}
-
-void board_vbus_enable(int port, int enable)
-{
-	gpio_set_level(tcpc_gpios[port].src.pin,
-		tcpc_gpios[port].src.pin_pol ? enable : !enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	int vbus_intr;
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	if (port == DEDICATED_CHARGE_PORT)
-		return 1;
-#endif
-
-	vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin);
-
-	return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (tcpc_gpios[i].vbus.pin == signal) {
-			schedule_deferred_pd_interrupt(i);
-			break;
-		}
-	}
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int i;
-
-	/* Check which port has the ALERT line set */
-	for (i = 0; i < CHARGE_PORT_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		/* Add TCPC alerts if present */
-	}
-
-	return status;
-}
-
-void board_tcpc_init(void)
-{
-	int i;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPCx interrupt */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		gpio_enable_interrupt(tcpc_gpios[i].vbus.pin);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
deleted file mode 100644
index 0c091efead..0000000000
--- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel-RVP family-specific configuration */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "driver/ppc/sn5s330.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "system.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void)
-{
-	/* Add code if TCPC chips need a reset */
-}
-
-static void baseboard_tcpc_init(void)
-{
-	int i;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* Enable PPC interrupts. */
-		if (tcpc_aic_gpios[i].ppc_intr_handler)
-			gpio_enable_interrupt(tcpc_aic_gpios[i].ppc_alert);
-
-		/* Enable TCPC interrupts. */
-		if (tcpc_config[i].bus_type != EC_BUS_TYPE_EMBEDDED)
-			gpio_enable_interrupt(tcpc_aic_gpios[i].tcpc_alert);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		if (signal == tcpc_aic_gpios[i].tcpc_alert) {
-			schedule_deferred_pd_interrupt(i);
-			break;
-		}
-	}
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int i;
-
-	/* Check which port has the ALERT line set */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		/* No alerts for embdeded TCPC */
-		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
-			continue;
-
-		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert))
-			status |= PD_STATUS_TCPC_ALERT_0 << i;
-	}
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (!tcpc_aic_gpios[port].ppc_intr_handler)
-		return 0;
-
-	return !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
-}
-
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (tcpc_aic_gpios[i].ppc_intr_handler &&
-			signal == tcpc_aic_gpios[i].ppc_alert) {
-			tcpc_aic_gpios[i].ppc_intr_handler(i);
-			break;
-		}
-	}
-}
-
-void board_charging_enable(int port, int enable)
-{
-	if (ppc_vbus_sink_enable(port, enable))
-		CPRINTS("C%d: sink path %s failed",
-				port, enable ? "en" : "dis");
-}
diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c
deleted file mode 100644
index bafddc5f9e..0000000000
--- a/baseboard/intelrvp/ite_ec.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP ITE EC specific configuration */
-
-#include "adc_chip.h"
-#include "common.h"
-#include "it83xx_pd.h"
-#include "keyboard_scan.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/*
- * PWM HW channelx binding tachometer channelx for fan control.
- * Four tachometer input pins but two tachometer modules only,
- * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or
- * [TACH_CH_TACH1A | TACH_CH_TACH1B]
- */
-const struct fan_tach_t fan_tach[] = {
-	[PWM_HW_CH_DCR0] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR1] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR2] = {
-		.ch_tach = TACH_CH_TACH1A,
-		.fan_p = 2,
-		.rpm_re = 1,
-		.s_duty = 1,
-	},
-	[PWM_HW_CH_DCR3] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR4] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR5] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR6] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR7] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL);
-
-/* PWM channels */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWM_HW_CH_DCR2,
-		.flags = PWM_CONFIG_HAS_RPM_MODE,
-		.freq_hz = 30000,
-		.pcfsr_sel = PWM_PRESCALER_C7,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-#if defined(CONFIG_USBC_VCONN) && defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-#ifndef CONFIG_USBC_PPC_VCONN
-	/*
-	 * Setting VCONN low by disabling the power switch before
-	 * enabling the VCONN on respective CC line
-	 */
-	gpio_set_level(tcpc_gpios[port].vconn.cc1_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
-	gpio_set_level(tcpc_gpios[port].vconn.cc2_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
-
-	if (enabled)
-		gpio_set_level((cc_pin != USBPD_CC_PIN_1) ?
-				tcpc_gpios[port].vconn.cc2_pin :
-				tcpc_gpios[port].vconn.cc1_pin,
-				tcpc_gpios[port].vconn.pin_pol);
-#endif
-}
-#endif
diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h
deleted file mode 100644
index c773a48b21..0000000000
--- a/baseboard/intelrvp/ite_ec.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP ITE EC specific configuration */
-
-#ifndef __CROS_EC_ITE_EC_H
-#define __CROS_EC_ITE_EC_H
-
-/* Optional feature - used by ITE */
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-#define CONFIG_IT83XX_VCC_1P8V
-
-/* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH13
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH15
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
-
-#ifdef CONFIG_USBC_VCONN
-	#define CONFIG_USBC_VCONN_SWAP
-	/* delay to turn on/off vconn */
-#endif
-#endif /* __CROS_EC_ITE_EC_H */
diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c
deleted file mode 100644
index 47dad8994f..0000000000
--- a/baseboard/intelrvp/led.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Phaser
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-const int led_charge_lvl_1 = 5;
-
-const int led_charge_lvl_2 = 97;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c
deleted file mode 100644
index 5f8768bdd9..0000000000
--- a/baseboard/intelrvp/led_states.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED state control for octopus boards
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_states.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-static enum led_states led_get_state(void)
-{
-	int  charge_lvl;
-	enum led_states new_state = LED_NUM_STATES;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Get percent charge */
-		charge_lvl = charge_get_percent();
-		/* Determine which charge state to use */
-		if (charge_lvl < led_charge_lvl_1)
-			new_state = STATE_CHARGING_LVL_1;
-		else if (charge_lvl < led_charge_lvl_2)
-			new_state = STATE_CHARGING_LVL_2;
-		else
-			new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			new_state = STATE_CHARGING_FULL_CHARGE;
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			new_state = STATE_DISCHARGE_S0;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_DISCHARGE_S3;
-		else
-			new_state = STATE_DISCHARGE_S5;
-		break;
-	case PWR_STATE_ERROR:
-		new_state = STATE_BATTERY_ERROR;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	return new_state;
-}
-
-static void led_update_battery(void)
-{
-	static uint8_t ticks, period;
-	static int led_state = LED_NUM_STATES;
-	int phase;
-	enum led_states desired_state = led_get_state();
-
-	/*
-	 * We always need to check the current state since the value could
-	 * have been manually overwritten. If we're in a new valid state,
-	 * update our ticks and period info. If our new state isn't defined,
-	 * continue using the previous one.
-	 */
-	if (desired_state != led_state && desired_state < LED_NUM_STATES) {
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
-		led_set_color_battery(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_battery(led_bat_state_table[led_state][phase].color);
-}
-
-static enum pwr_led_states pwr_led_get_state(void)
-{
-	if (extpower_is_present()) {
-		if (charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL)
-			return PWR_LED_STATE_OFF;
-		else
-			return PWR_LED_STATE_ON;
-	} else
-		return PWR_LED_STATE_SUSPEND_AC;
-}
-
-static void led_update_power(void)
-{
-	static uint8_t ticks, period;
-	static enum pwr_led_states led_state = PWR_LED_NUM_STATES;
-	int phase;
-	enum pwr_led_states desired_state = pwr_led_get_state();
-
-	/*
-	 * If we're in a new valid state, update our ticks and period info.
-	 * Otherwise, continue to use old state
-	 */
-	if (desired_state != led_state && desired_state < PWR_LED_NUM_STATES) {
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
-		led_set_color_power(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_power(led_pwr_state_table[led_state][phase].color);
-}
-
-static void led_init(void)
-{
-	/* If battery LED is enabled, set it to "off" to start with */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_color_battery(LED_OFF);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every hook tick (200 msec) */
-static void led_update(void)
-{
-	/*
-	 * If battery LED is enabled, set its state based on our power and
-	 * charge
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_update_battery();
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_update_power();
-}
-DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h
deleted file mode 100644
index 907ff5c8b8..0000000000
--- a/baseboard/intelrvp/led_states.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for stateful LEDs (charger and power)
- */
-
-#ifndef __CROS_EC_BASEBOARD_LED_H
-#define __CROS_EC_BASEBOARD_LED_H
-
-#include "ec_commands.h"
-
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
-
-/*
- * All LED states should have one phase defined,
- * and an additional phase can be defined for blinking
- */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
-
-/*
- * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
- *
- * STATE_CHARGING_LVL_2 is when led_charge_level_1 <=
- * charge_percentage < led_charge_level_2
- *
- * STATE_CHARGING_FULL_CHARGE is when led_charge_level_2 <=
- * charge_percentage < 100
- */
-enum led_states {
-	STATE_CHARGING_LVL_1,
-	STATE_CHARGING_LVL_2,
-	STATE_CHARGING_FULL_CHARGE,
-	STATE_DISCHARGE_S0,
-	STATE_DISCHARGE_S0_BAT_LOW,
-	STATE_DISCHARGE_S3,
-	STATE_DISCHARGE_S5,
-	STATE_BATTERY_ERROR,
-	STATE_FACTORY_TEST,
-	LED_NUM_STATES
-};
-
-struct led_descriptor {
-	enum ec_led_colors color;
-	uint8_t time;
-};
-
-
-/* Charging LED state table - defined in board's led.c */
-extern struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
-
-/* Charging LED state level 1 - defined in board's led.c */
-extern const int led_charge_lvl_1;
-
-/* Charging LED state level 2 - defined in board's led.c */
-extern const int led_charge_lvl_2;
-
-enum pwr_led_states {
-	PWR_LED_STATE_ON,
-	PWR_LED_STATE_SUSPEND_AC,
-	PWR_LED_STATE_SUSPEND_NO_AC,
-	PWR_LED_STATE_OFF,
-	PWR_LED_NUM_STATES
-};
-
-/* Power LED state table - defined in board's led.c */
-extern const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
-
-/**
- * Set battery LED color - defined in board's led.c
- *
- * @param color		Color to set on battery LED
- *
- */
-void led_set_color_battery(enum ec_led_colors color);
-
-/**
- * Set power LED color - defined in board's led.c
- */
-void led_set_color_power(enum ec_led_colors color);
-
-#endif /* __CROS_EC_BASEBOARD_LED_H */
diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c
deleted file mode 100644
index f1eb4678c1..0000000000
--- a/baseboard/intelrvp/mchp_ec.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP MCHP EC specific configuration */
-
-#include "adc_chip.h"
-#include "common.h"
-#include "keyboard_scan.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80 us from 50 us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/*
- * TODO - Fan and tach table.
- * MCHP MEC1322 and MEC170x have fan speed controller(s)
- * whereas MEC152x only has multiple TACH and PWM modules.
- * MEC152x fan control will require a firmware layer that uses
- * specified TACH and PWM modules.
- */
-
-/* PWM channels */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-#ifdef CHIP_FAMILY_MEC172X
-		.channel = PWM_HW_CH_0,
-#else
-		.channel = PWM_HW_CH_4,
-#endif
-		.flags = PWM_CONFIG_HAS_RPM_MODE,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h
deleted file mode 100644
index 227ccaef6d..0000000000
--- a/baseboard/intelrvp/mchp_ec.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP MCHP EC specific configuration */
-
-#ifndef __CROS_EC_MCHP_EC_H
-#define __CROS_EC_MCHP_EC_H
-
-/* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH7
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
-
-/*
- * ADC maximum voltage is a board level configuration.
- * MEC152x ADC can use an external 3.0 or 3.3V reference with
- * maximum values up to the reference voltage.
- * The ADC maximum voltage depends upon the external reference
- * voltage connected to MEC152x.
- */
-#define ADC_MAX_MVOLT 3000
-
-#endif /* __CROS_EC_MCHP_EC_H */
diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c
deleted file mode 100644
index d6eca2e55b..0000000000
--- a/baseboard/intelrvp/npcx_ec.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP NPCX EC specific configuration */
-
-#include "adc_chip.h"
-#include "fan_chip.h"
-#include "keyboard_scan.h"
-#include "pwm_chip.h"
-#include "time.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SNS_AMBIENT] = {
-		.name = "ADC_TEMP_SNS_AMBIENT",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_AMBIENT_CHANNEL,
-	},
-	[ADC_TEMP_SNS_DDR] = {
-		.name = "ADC_TEMP_SNS_DDR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_DDR_CHANNEL,
-	},
-	[ADC_TEMP_SNS_SKIN] = {
-		.name = "ADC_TEMP_SNS_SKIN",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_SKIN_CHANNEL,
-	},
-	[ADC_TEMP_SNS_VR] = {
-		.name = "ADC_TEMP_SNS_VR",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.input_ch = ADC_TEMP_SNS_VR_CHANNEL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWN_FAN_CHANNEL,
-		.flags = 0,
-		.freq = 30000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_2,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h
deleted file mode 100644
index 52bcb2dae6..0000000000
--- a/baseboard/intelrvp/npcx_ec.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel BASEBOARD-RVP NPCX EC specific configuration */
-
-#ifndef __CROS_EC_NPCX_EC_H
-#define __CROS_EC_NPCX_EC_H
-
-#if !defined(__ASSEMBLER__)
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-#endif /* __ASSEMBLER__ */
-
-/* ADC channels */
-#define ADC_MAX_MVOLT			ADC_MAX_VOLT
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	NPCX_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	NPCX_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	NPCX_ADC_CH2
-#define ADC_TEMP_SNS_VR_CHANNEL		NPCX_ADC_CH1
-
-/* KSO2 is inverted */
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-
-/* Fan */
-#define CONFIG_PWM
-#define PWN_FAN_CHANNEL		3
-
-/* GPIO64/65 are used as UART pins. */
-#define NPCX_UART_MODULE2	1
-
-#endif /* __CROS_EC_NPCX_EC_H */
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
deleted file mode 100644
index 6d173fd032..0000000000
--- a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	board_vbus_enable(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	board_vbus_enable(port, 0);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if PP5000 rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	board_set_vbus_source_current_limit(port, rp);
-}
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
deleted file mode 100644
index 29a538231f..0000000000
--- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = board_vbus_source_enabled(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if PP3300 rail is enabled */
-	return gpio_get_level(GPIO_EN_PP3300_A);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-
-int board_vbus_source_enabled(int port)
-{
-	if (is_typec_port(port))
-		return ppc_is_sourcing_vbus(port);
-	return 0;
-}
diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c
deleted file mode 100644
index 00459b12bc..0000000000
--- a/baseboard/ite_evb/baseboard.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ite_evb baseboard configuration */
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power_button.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "gpio_list.h"
-
-#if defined(CONFIG_FANS) || defined(CONFIG_PWM)
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0, /* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1500,
-	.rpm_start = 1500,
-	.rpm_max = 6500,
-};
-
-const struct fan_t fans[] = {
-	{ .conf = &fan_conf_0,
-	  .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
-
-/*
- * PWM HW channelx binding tachometer channelx for fan control.
- * Four tachometer input pins but two tachometer modules only,
- * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or
- * [TACH_CH_TACH1A | TACH_CH_TACH1B]
- */
-const struct fan_tach_t fan_tach[] = {
-	[PWM_HW_CH_DCR0] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR1] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR2] = {
-		.ch_tach = TACH_CH_TACH1A,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR3] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR4] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR5] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR6] = {
-		.ch_tach = TACH_CH_NULL,
-		.fan_p = -1,
-		.rpm_re = -1,
-		.s_duty = -1,
-	},
-	[PWM_HW_CH_DCR7] = {
-		.ch_tach = TACH_CH_TACH0A,
-		.fan_p = 2,
-		.rpm_re = 50,
-		.s_duty = 30,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL);
-#endif /* defined(CONFIG_FANS) || defined(CONFIG_PWM) */
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-#if defined(CONFIG_SPI_FLASH_PORT)
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	[CONFIG_SPI_FLASH_PORT] = {
-		.port = CONFIG_SPI_FLASH_PORT,
-		.div = 0,
-		.gpio_cs = -1
-	},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-#endif
-
-/* Initialize board. */
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_LID_OPEN
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/*
- * I2C channels (A, B, and C) are using the same timing registers (00h~07h)
- * at default.
- * In order to set frequency independently for each channels,
- * We use timing registers 09h~0Bh, and the supported frequency will be:
- * 50KHz, 100KHz, 400KHz, or 1MHz.
- * I2C channels (D, E and F) can be set different frequency on different ports.
- * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and
- * the individual prescale register.
- * The frequency of SMBus module is 24MHz on default.
- * The allowed range of I2C(D/E/F) frequency is as following setting.
- * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1)
- * (SMBus Module Freq / 510) <=  I2C Freq <= (SMBus Module Freq / 8)
- * Channel D has multi-function and can be used as UART interface.
- * Channel F is reserved for EC debug.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_I2C_C_SCL,
-		.sda = GPIO_I2C_C_SDA,
-	},
-	{
-		.name = "evb-1",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_I2C_A_SCL,
-		.sda = GPIO_I2C_A_SDA,
-	},
-	{
-		.name = "evb-2",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA,
-	},
-	{
-		.name = "opt-4",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/ite_evb/baseboard.h b/baseboard/ite_evb/baseboard.h
deleted file mode 100644
index 7fe309491c..0000000000
--- a/baseboard/ite_evb/baseboard.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ite_evb baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* Optional features */
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_FANS 1
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-#define CONFIG_IT83XX_VCC_3P3V
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_S0
-#define CONFIG_PECI
-#define CONFIG_PECI_COMMON
-#define CONFIG_PECI_TJMAX 100
-#define CONFIG_POWER_BUTTON
-#define CONFIG_PWM
-/* Use CS0 of SSPI */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_UART_HOST
-#define CONFIG_HOSTCMD_LPC
-
-/* Optional console commands */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
-
-/* Debug */
-#undef CONFIG_CMD_FORCETIME
-#undef CONFIG_HOOK_DEBUG
-#undef CONFIG_KEYBOARD_DEBUG
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* I2C Bus Configuration */
-#define I2C_PORT_CHARGER IT83XX_I2C_CH_C
-#define I2C_PORT_BATTERY IT83XX_I2C_CH_C
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/ite_evb/build.mk b/baseboard/ite_evb/build.mk
deleted file mode 100644
index 77352145ee..0000000000
--- a/baseboard/ite_evb/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c
deleted file mode 100644
index 59f3da13f5..0000000000
--- a/baseboard/ite_evb/usb_pd_policy.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for ite_evb baseboard */
-
-#include "adc.h"
-#include "config.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "it83xx_pd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* ---------------- Power Data Objects (PDOs) ----------------- */
-#ifdef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_UNCONSTRAINED  | PDO_FIXED_COMM_CAP)
-
-/* Threshold voltage of VBUS provided (mV) */
-#define PD_VBUS_PROVIDED_THRESHOLD 3900
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4500, 14000, 10000),
-	PDO_VAR(4500, 14000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-#endif
-
-int pd_is_max_request_allowed(void)
-{
-	/* Max voltage request allowed */
-	return 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	int mv = ADC_READ_ERROR;
-
-	switch (port) {
-	case USBPD_PORT_A:
-		mv = adc_read_channel(ADC_VBUSSA);
-		break;
-	case USBPD_PORT_B:
-		mv = adc_read_channel(ADC_VBUSSB);
-		break;
-	case USBPD_PORT_C:
-		mv = adc_read_channel(ADC_VBUSSC);
-		break;
-	}
-
-	return mv > PD_VBUS_PROVIDED_THRESHOLD;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Provide VBUS */
-	board_pd_vbus_ctrl(port, 1);
-	/* Vbus provided or not */
-	return !pd_snk_is_vbus_provided(port);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Kill VBUS */
-	board_pd_vbus_ctrl(port, 0);
-}
-
-
-__override int pd_check_data_swap(int port, enum pd_data_role data_role)
-{
-	/* Always allow data swap: we can be DFP or UFP for USB */
-	return 1;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * VCONN is provided directly by the battery(PPVAR_SYS)
-	 * but use the same rules as power swap
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/*
- * We don't have mux on pd evb and not define CONFIG_USBC_SS_MUX,
- * so mux related functions do nothing then return.
- */
-__override int svdm_enter_dp_mode(int port, uint32_t mode_caps)
-{
-	/*
-	 * Do not enter dp mode, we let VDM enumeration stop after discover
-	 * modes have done.
-	 */
-	return -1;
-}
-
-__override void svdm_dp_post_config(int port)
-{
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	/* Ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-}
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-				uint32_t **rpayload)
-{
-	/* Return length 0, means nothing needn't tx */
-	return 0;
-}
-
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	/* Return length 0, means nothing needn't tx */
-	return 0;
-};
diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c
deleted file mode 100644
index f6a6b23110..0000000000
--- a/baseboard/kalista/baseboard.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kalista baseboard configuration */
-
-#include "adc.h"
-#include "baseboard.h"
-#include "battery.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/pmic_tps650x30.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "espi.h"
-#include "extpower.h"
-#include "espi.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "oz554.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static uint8_t board_version;
-static uint32_t oem;
-static uint32_t sku;
-
-enum bj_adapter {
-	BJ_90W_19V,
-	BJ_135W_19V,
-};
-
-/*
- * Bit masks to map SKU ID to BJ adapter wattage. 1:135W 0:90W
- * KBL-R i7 8550U	4	135
- * KBL-R i5 8250U	5	135
- * KBL-R i3 8130U	6	135
- * KBL-U i7 7600	3	135
- * KBL-U i5 7500	2	135
- * KBL-U i3 7100	1	90
- * KBL-U Celeron 3965	7	90
- * KBL-U Celeron 3865	0	90
- */
-#define BJ_ADAPTER_135W_MASK (1 << 4 | 1 << 5 | 1 << 6 | 1 << 3 | 1 << 2)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	if (!gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
-		return;
-#ifdef HAS_TASK_PDCMD
-	/* Exchange status with TCPCs */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-#endif
-}
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C0);
-}
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* TODO: Verify fan control and mft */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_FAN_PWR_EN,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2180,
-	.rpm_start = 2180,
-	.rpm_max = 4900,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc", I2C_PORT_TCPC0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"backlight", I2C_PORT_BACKLIGHT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	/* Alert is active-low, push-pull */
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = I2C_ADDR_TCPC0_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* 0x98 sets lower EQ of DP port (4.5db) */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	},
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-	GPIO_USB2_ENABLE,
-	GPIO_USB3_ENABLE,
-	GPIO_USB4_ENABLE,
-};
-
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
-	msleep(1);
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int reg;
-
-	/* This needs to be executed only once per boot. It could be run by RO
-	 * if we boot in recovery mode. It could be run by RW if we boot in
-	 * normal or dev mode. Note EFS makes RO jump to RW before HOOK_INIT. */
-	board_reset_pd_mcu();
-
-	/*
-	 * Wake up PS8751. If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 * Note PS8751 A3 will wake on any I2C access.
-	 */
-	i2c_read8(I2C_PORT_TCPC0, I2C_ADDR_TCPC0_FLAGS, 0xA0, &reg);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) &&
-			gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
-		return PD_STATUS_TCPC_ALERT_0;
-	return 0;
-}
-
-/*
- * TMP431 has one local and one remote sensor.
- *
- * Temperature sensors data; must be in same order as enum temp_sensor_id.
- * Sensor index and name must match those present in coreboot:
- *     src/mainboard/google/${board}/acpi/dptf.asl
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
- * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	/* {Twarn, Thigh, Thalt}, <on>
-	 * {Twarn, Thigh, X    }, <off>
-	 * fan_off, fan_max
-	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Initialize PMIC */
-#define I2C_PMIC_READ(reg, data) \
-	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-#define I2C_PMIC_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-static void board_pmic_init(void)
-{
-	int err;
-	int error_count = 0;
-	static uint8_t pmic_initialized = 0;
-
-	if (pmic_initialized)
-		return;
-
-	/* Read vendor ID */
-	while (1) {
-		int data;
-		err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data);
-		if (!err && data == TPS650X30_VENDOR_ID)
-			break;
-		else if (error_count > 5)
-			goto pmic_error;
-		error_count++;
-	}
-
-	/*
-	 * VCCIOCNT register setting
-	 * [6] : CSDECAYEN
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * VRMODECTRL:
-	 * [4] : VCCIOLPM clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PGMASK1 : Exclude VCCIO from Power Good Tree
-	 * [7] : MVCCIOPG clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PWFAULT_MASK1 Register settings
-	 * [7] : 1b V4 Power Fault Masked
-	 * [4] : 1b V7 Power Fault Masked
-	 * [2] : 1b V9 Power Fault Masked
-	 * [0] : 1b V13 Power Fault Masked
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 4 register configuration
-	 * [7:6] : 00b Reserved
-	 * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
-	 * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
-	 * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 3 register configuration
-	 * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
-	 * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
-	 * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
-	 * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 2 register configuration
-	 * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
-	 * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
-	 * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
-	 * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 1 register configuration
-	 * [7:2] : 00b Reserved
-	 * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Increase Voltage
-	 *  [7:0] : 0x2a default
-	 *  [5:4] : 10b default
-	 *  [5:4] : 01b 5.1V (0x1a)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PBCONFIG Register configuration
-	 *   [7] :      1b Power button debounce, 0ms (no debounce)
-	 *   [6] :      0b Power button reset timer logic, no action (default)
-	 * [5:0] : 011111b Force an Emergency reset time, 31s (default)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * V3.3A_DSW (VR3) control. Default: 0x2A.
-	 * [7:6] : 00b Disabled
-	 * [5:4] : 00b Vnom + 3%. (default: 10b 0%)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V33ADSWCNT, 0x0A);
-	if (err)
-		goto pmic_error;
-
-	CPRINTS("PMIC init done");
-	pmic_initialized = 1;
-	return;
-
-pmic_error:
-	CPRINTS("PMIC init failed");
-}
-
-void chipset_pre_init_callback(void)
-{
-	board_pmic_init();
-}
-
-/**
- * Notify PCH of the AC presence.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 30, .off =  5, .rpm = 2180},
-	{.on = 49, .off = 46, .rpm = 2680},
-	{.on = 53, .off = 50, .rpm = 3300},
-	{.on = 58, .off = 54, .rpm = 3760},
-	{.on = 63, .off = 59, .rpm = 4220},
-	{.on = 68, .off = 64, .rpm = 4660},
-	{.on = 75, .off = 70, .rpm = 4900},
-};
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-
-static const struct fan_step *fan_table = fan_table0;
-
-
-static void cbi_init(void)
-{
-	uint32_t val;
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT8_MAX)
-		board_version = val;
-	CPRINTS("Board Version: 0x%02x", board_version);
-
-	if (cbi_get_oem_id(&val) == EC_SUCCESS && val < OEM_COUNT)
-		oem = val;
-	CPRINTS("OEM: %d", oem);
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku = val;
-	CPRINTS("SKU: 0x%08x", sku);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void setup_bj(void)
-{
-	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ?
-			BJ_135W_19V : BJ_90W_19V;
-	gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V);
-}
-
-static void board_init(void)
-{
-	setup_bj();
-
-	board_extpower();
-
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
-}
diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h
deleted file mode 100644
index 230b815a48..0000000000
--- a/baseboard/kalista/baseboard.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kalista baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#undef  CONFIG_SYSTEM_UNLOCKED
-#define CONFIG_USB_PD_COMM_LOCKED
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_CRC8
-#define CONFIG_CEC
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_LED_COMMON
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_PWM
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
-#define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
-#define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
-#define CONFIG_FANS 1
-#define CONFIG_FAN_RPM_CUSTOM
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_PWM
-
-/* EC console commands */
-#define CONFIG_CMD_BUTTON
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP432
-
-/* USB */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT 4
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-
-/* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS	0x0b
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/* Verify and jump to RW image on boot */
-#define CONFIG_VBOOT_EFS
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/*
- * LED backlight controller
- */
-#define CONFIG_LED_DRIVER_OZ554
-
-/*
- * Flash layout. Since config_flash_layout.h is included before board.h,
- * we can only overwrite (=undef/define) these parameters here.
- *
- * Flash stores 3 images: RO, RW_A, RW_B. We divide the flash by 4.
- * A public key is stored at the end of RO. Signatures are stored at the
- * end of RW_A and RW_B, respectively.
- */
-#define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
-
-#define CONFIG_RWSIG
-#define CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RSA
-#ifdef SECTION_IS_RO
-#define CONFIG_RSA_OPTIMIZED
-#endif
-#define CONFIG_SHA256
-#ifdef SECTION_IS_RO
-#define CONFIG_SHA256_UNROLLED
-#endif
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_RED,
-	PWM_CH_LED_BLUE,
-	PWM_CH_FAN,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-enum OEM_ID {
-	OEM_KARMA = 7,
-	/* Number of OEM IDs */
-	OEM_COUNT
-};
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void led_critical(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk
deleted file mode 100644
index e64b6a2d71..0000000000
--- a/baseboard/kalista/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-y+=led.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
\ No newline at end of file
diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c
deleted file mode 100644
index e04eecf5e3..0000000000
--- a/baseboard/kalista/led.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Kalista
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_BLUE,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int blue = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_BLUE:
-		blue = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		blue = 1;
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (blue)
-		pwm_set_duty(PWM_CH_LED_BLUE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_BLUE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec. */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define LED_PULSE_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-	static uint8_t pwm_enabled = 0;
-
-	if (!pwm_enabled) {
-		pwm_enable(PWM_CH_LED_RED, 1);
-		pwm_enable(PWM_CH_LED_BLUE, 1);
-		pwm_enabled = 1;
-	}
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	LED_PULSE_TICK(LED_PULSE_TICK_US, LED_BLUE);
-	led_tick();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend, HOOK_PRIO_DEFAULT);
-
-static void led_shutdown(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task. */
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown();
-	}
-}
-
-void led_critical(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "blue")) {
-		set_color(id, LED_BLUE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		led_critical();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|blue|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		return set_color(id, LED_BLUE, brightness[EC_LED_COLOR_BLUE]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c
deleted file mode 100644
index 89af4b50fb..0000000000
--- a/baseboard/kalista/usb_pd_policy.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \
-			 PDO_FIXED_DATA_SWAP | \
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-int board_vbus_source_enabled(int port)
-{
-	if (port != 0)
-		return 0;
-	return gpio_get_level(GPIO_USB_C0_5V_EN);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Enable VBUS source */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS source */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
diff --git a/baseboard/keeby b/baseboard/keeby
deleted file mode 120000
index 14558486f6..0000000000
--- a/baseboard/keeby
+++ /dev/null
@@ -1 +0,0 @@
-dedede
\ No newline at end of file
diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c
deleted file mode 100644
index 68542b4fb6..0000000000
--- a/baseboard/kukui/base_detect_kukui.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "base_state.h"
-#include "board.h"
-#include "charge_manager.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/* Krane base detection code */
-
-/* Base detection and debouncing */
-#define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-enum kukui_pogo_device_type {
-	DEVICE_TYPE_ERROR = -2,
-	DEVICE_TYPE_UNKNOWN = -1,
-	DEVICE_TYPE_DETACHED = 0,
-#ifdef VARIANT_KUKUI_POGO_DOCK
-	DEVICE_TYPE_DOCK,
-#endif
-	DEVICE_TYPE_KEYBOARD,
-	DEVICE_TYPE_COUNT,
-};
-
-struct {
-	int mv_low, mv_high;
-} static const pogo_detect_table[] = {
-	[DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */
-#ifdef VARIANT_KUKUI_POGO_DOCK
-	[DEVICE_TYPE_DOCK] = {141, 173},       /* 10K, 0.5K ohm */
-#endif
-	[DEVICE_TYPE_KEYBOARD] = {270, 400},   /* 10K, 1K ohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT);
-
-static uint64_t base_detect_debounce_time;
-static enum kukui_pogo_device_type pogo_type;
-
-int kukui_pogo_extpower_present(void)
-{
-#ifdef VARIANT_KUKUI_POGO_DOCK
-	return pogo_type == DEVICE_TYPE_DOCK &&
-	       gpio_get_level(GPIO_POGO_VBUS_PRESENT);
-#else
-	return 0;
-#endif
-}
-
-static enum kukui_pogo_device_type get_device_type(int mv)
-{
-	int i;
-
-	if (mv == ADC_READ_ERROR)
-		return DEVICE_TYPE_ERROR;
-
-	for (i = 0; i < DEVICE_TYPE_COUNT; i++) {
-		if (pogo_detect_table[i].mv_low <= mv &&
-				mv <= pogo_detect_table[i].mv_high)
-			return i;
-	}
-
-	return DEVICE_TYPE_UNKNOWN;
-}
-
-static void enable_charge(int enable)
-{
-#ifdef VARIANT_KUKUI_POGO_DOCK
-	if (enable) {
-		struct charge_port_info info = {
-			.voltage = 5000, .current = 1500};
-		/*
-		 * Set supplier type to PD to have same priority as type c
-		 * port.
-		 */
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info);
-	} else {
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL);
-	}
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-#endif
-}
-
-static void enable_power_supply(int enable)
-{
-	gpio_set_level(GPIO_EN_PP3300_POGO, enable);
-}
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-static void base_set_device_type(enum kukui_pogo_device_type device_type)
-{
-	switch (device_type) {
-	case DEVICE_TYPE_ERROR:
-	case DEVICE_TYPE_UNKNOWN:
-		hook_call_deferred(&base_detect_deferred_data,
-				BASE_DETECT_RETRY_US);
-		break;
-
-	case DEVICE_TYPE_DETACHED:
-		enable_power_supply(0);
-		enable_charge(0);
-		base_set_state(0);
-		break;
-
-#ifdef VARIANT_KUKUI_POGO_DOCK
-	case DEVICE_TYPE_DOCK:
-		enable_power_supply(0);
-		enable_charge(1);
-		base_set_state(1);
-		break;
-#endif
-
-	case DEVICE_TYPE_KEYBOARD:
-		enable_charge(0);
-		enable_power_supply(1);
-		base_set_state(1);
-		break;
-
-	case DEVICE_TYPE_COUNT:
-		/* should not happen */
-		break;
-	}
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int mv;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	/*
-	 * Disable interrupt first to prevent it triggered by value
-	 * changed from 1 to disabled state(=0).
-	 */
-	gpio_disable_interrupt(GPIO_POGO_ADC_INT_L);
-	gpio_set_flags(GPIO_POGO_ADC_INT_L, GPIO_ANALOG);
-	mv = adc_read_channel(ADC_POGO_ADC_INT_L);
-	/* restore the pin function */
-	gpio_set_flags(GPIO_POGO_ADC_INT_L, GPIO_INT_BOTH);
-	gpio_enable_interrupt(GPIO_POGO_ADC_INT_L);
-
-	pogo_type = get_device_type(mv);
-	CPRINTS("POGO: adc=%d, type=%d", mv, pogo_type);
-
-	base_set_device_type(pogo_type);
-}
-
-void pogo_adc_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-
-	if (base_detect_debounce_time <= time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
-	}
-
-	base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US;
-}
-
-static void pogo_chipset_init(void)
-{
-	/* Enable pogo interrupt */
-	gpio_enable_interrupt(GPIO_POGO_ADC_INT_L);
-
-	hook_call_deferred(&base_detect_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, pogo_chipset_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void pogo_chipset_shutdown(void)
-{
-	/* Disable pogo interrupt */
-	gpio_disable_interrupt(GPIO_POGO_ADC_INT_L);
-
-	enable_power_supply(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pogo_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state >= EC_SET_BASE_STATE_RESET) {
-		CPRINTS("BD forced reset");
-		pogo_chipset_init();
-		return;
-	}
-
-	gpio_disable_interrupt(GPIO_POGO_ADC_INT_L);
-	pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED);
-	base_set_device_type(state == EC_SET_BASE_STATE_ATTACH
-					? DEVICE_TYPE_KEYBOARD
-					: DEVICE_TYPE_DETACHED);
-	CPRINTS("BD forced %sconnected", state == EC_SET_BASE_STATE_ATTACH ?
-						  "" : "dis");
-}
-
-#ifdef VARIANT_KUKUI_POGO_DOCK
-static void board_pogo_charge_init(void)
-{
-	int i;
-
-	/* Initialize all charge suppliers to 0 */
-	for (i = 0; i < CHARGE_SUPPLIER_COUNT; i++)
-		charge_manager_update_charge(i, CHARGE_PORT_POGO, NULL);
-}
-DECLARE_HOOK(HOOK_INIT, board_pogo_charge_init,
-	     HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-#endif
diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c
deleted file mode 100644
index 3f9a1c36c6..0000000000
--- a/baseboard/kukui/baseboard.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "charger.h"
-#include "chipset.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#ifndef CONFIG_CHARGER_RUNTIME_CONFIG
-#if defined(VARIANT_KUKUI_CHARGER_MT6370)
-#include "driver/charger/rt946x.h"
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = RT946X_ADDR_FLAGS,
-		.drv = &rt946x_drv,
-	},
-};
-#elif defined(VARIANT_KUKUI_CHARGER_ISL9238)
-#include "driver/charger/isl923x.h"
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-#endif /* VARIANT_KUKUI_CHARGER_* */
-
-#endif /* CONFIG_CHARGER_RUNTIME_CONFIG */
-
-void board_reset_pd_mcu(void)
-{
-}
-
-void board_config_pre_init(void)
-{
-#ifdef VARIANT_KUKUI_EC_STM32F098
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-	/*
-	 * Remap USART1 and SPI2 DMA:
-	 *
-	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
-	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
-	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
-
-#elif defined(VARIANT_KUKUI_EC_STM32L431)
-#ifdef	CONFIG_DMA
-	dma_init();
-#endif
-	/*
-	 * Remap USART1 and SPI2 DMA:
-	 *
-	 * DMA2_CH=DMA1_CH+8
-	 *
-	 * Ch6 (DMA2): USART1_TX / Ch7: USART1_RX (0010)
-	 * Ch4 (DMA1): SPI2_RX   / Ch5: SPI2_TX (0010)
-	 *
-	 *    (*((volatile unsigned long *)(0x400200A8UL))) = 0x00011000;
-	 *    (*((volatile unsigned long *)(0x400204A8UL))) = 0x00200000;
-	 */
-
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (1 << 12) | (1 << 16);
-	STM32_DMA_CSELR(STM32_DMAC_CH14) = (2 << 20) | (2 << 24);
-#endif
-}
-
-enum kukui_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_REV0 = 0,
-	BOARD_VERSION_REV1 = 1,
-	BOARD_VERSION_REV2 = 2,
-	BOARD_VERSION_REV3 = 3,
-	BOARD_VERSION_REV4 = 4,
-	BOARD_VERSION_REV5 = 5,
-	BOARD_VERSION_REV6 = 6,
-	BOARD_VERSION_REV7 = 7,
-	BOARD_VERSION_REV8 = 8,
-	BOARD_VERSION_REV9 = 9,
-	BOARD_VERSION_REV10 = 10,
-	BOARD_VERSION_REV11 = 11,
-	BOARD_VERSION_REV12 = 12,
-	BOARD_VERSION_REV13 = 13,
-	BOARD_VERSION_REV14 = 14,
-	BOARD_VERSION_REV15 = 15,
-	BOARD_VERSION_COUNT,
-};
-
-/* map from kukui_board_version to board id voltage in mv */
-#ifdef VARIANT_KUKUI_EC_IT81202
-const int16_t kukui_board_id_map[] = {
-	136,   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	388,   /* 51.1k , 6.8K ohm */
-	584,   /* 51.1K , 11K ohm */
-	785,   /* 56K   , 17.4K ohm */
-	993,   /* 51.1K , 22K ohm */
-	1221,  /* 51.1K , 30K ohm */
-	1433,  /* 51.1K , 39.2K ohm */
-	1650,  /* 56K   , 56K ohm */
-	1876,  /* 47K   , 61.9K ohm */
-	2084,  /* 47K   , 80.6K ohm */
-	2273,  /* 56K   , 124K ohm */
-	2461,  /* 51.1K , 150K ohm */
-	2672,  /* 47K   , 200K ohm */
-	2889,  /* 47K   , 330K ohm */
-	3086,  /* 47K   , 680K ohm */
-	3300,  /* 56K   , NC */
-};
-
-#define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */
-#else
-const int16_t kukui_board_id_map[] = {
-	109,   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	211,   /* 51.1k , 6.8K ohm */
-	319,   /* 51.1K , 11K ohm */
-	427,   /* 56K   , 17.4K ohm */
-	542,   /* 51.1K , 22K ohm */
-	666,   /* 51.1K , 30K ohm */
-	781,   /* 51.1K , 39.2K ohm */
-	900,   /* 56K   , 56K ohm */
-	1023,  /* 47K   , 61.9K ohm */
-	1137,  /* 47K   , 80.6K ohm */
-	1240,  /* 56K   , 124K ohm */
-	1343,  /* 51.1K , 150K ohm */
-	1457,  /* 47K   , 200K ohm */
-	1576,  /* 47K   , 330K ohm */
-	1684,  /* 47K   , 680K ohm */
-	1800,  /* 56K   , NC */
-};
-
-#define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
-#endif /* VARIANT_KUKUI_EC_IT81202 */
-BUILD_ASSERT(ARRAY_SIZE(kukui_board_id_map) == BOARD_VERSION_COUNT);
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv;
-	int i;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
-	/* Wait to allow cap charge */
-	msleep(20);
-	mv = adc_read_channel(ADC_BOARD_ID);
-
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ADC_BOARD_ID);
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 1);
-
-	for (i = 0; i < BOARD_VERSION_COUNT; ++i) {
-		if (mv < kukui_board_id_map[i] + THRESHOLD_MV) {
-			version = i;
-			break;
-		}
-	}
-
-#ifdef VARIANT_KUKUI_EC_STM32F098
-	/*
-	 * For devices without pogo, Disable ADC module after we detect the
-	 * board version, since this is the only thing ADC module needs to do
-	 * for this board.
-	 */
-	if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 &&
-			version != BOARD_VERSION_UNKNOWN)
-		adc_disable();
-#endif
-
-	return version;
-}
-
-static void baseboard_spi_init(void)
-{
-#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
-	/* Set SPI PA15,PB3/4/5/13/14/15 pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xc0000000;
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xfc000fc0;
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_spi_init, HOOK_PRIO_INIT_SPI + 1);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-#ifdef VARIANT_KUKUI_JACUZZI
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the
-		 * keyboard. When the chipset is on, the EC keeps the
-		 * keyboard enabled and the AP decides whether to
-		 * ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0,
-					     KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h
deleted file mode 100644
index 87ebeb40e1..0000000000
--- a/baseboard/kukui/baseboard.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kukui board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * Variant battery defines, pick one:
- * VARIANT_KUKUI_BATTERY_MAX17055
- * VARIANT_KUKUI_BATTERY_MM8013
- * VARIANT_KUKUI_BATTERY_BQ27541
- * VARIANT_KUKUI_BATTERY_SMART
- */
-#if defined(VARIANT_KUKUI_BATTERY_MAX17055)
-#define CONFIG_BATTERY_MAX17055
-#define CONFIG_BATTERY_MAX17055_ALERT
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
-#elif defined(VARIANT_KUKUI_BATTERY_MM8013)
-#define CONFIG_BATTERY_MM8013
-#elif defined(VARIANT_KUKUI_BATTERY_BQ27541)
-#define CONFIG_BATTERY_BQ27541
-#elif defined(VARIANT_KUKUI_BATTERY_SMART)
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_FUEL_GAUGE
-#else
-#error Must define a VARIANT_KUKUI_BATTERY
-#endif /* VARIANT_KUKUI_BATTERY */
-
-/*
- * Variant charger defines, pick one:
- * VARIANT_KUKUI_CHARGER_MT6370
- * VARIANT_KUKUI_CHARGER_ISL9238
- */
-#if defined(VARIANT_KUKUI_CHARGER_MT6370)
-#define CONFIG_CHARGER_MT6370
-#define CONFIG_CHARGER_MT6370_BC12_GPIO
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_USB_PD_TCPM_MT6370
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-
-/* TCPC MT6370 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/*
- * The Maximum input voltage is 13.5V, need another 5% tolerance.
- * 12.85V * 1.05 = 13.5V
- */
-#define PD_MAX_VOLTAGE_MV 12850
-#define CONFIG_USB_PD_PREFER_MV
-#elif defined(VARIANT_KUKUI_CHARGER_ISL9238)
-#define CONFIG_CHARGER_ISL9238C
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */
-#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGE_RAMP_HW
-
-/* TCPC FUSB302 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  160000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* b/2230219: 15V has better charging performance than 20V */
-#define PD_MAX_VOLTAGE_MV 15000
-#else
-#error Must define a VARIANT_KUKUI_CHARGER
-#endif /* VARIANT_KUKUI_CHARGER */
-
-/*
- * Variant pogo defines, if pick, VARIANT_KUKUI_POGO_KEYBOARD is mandatory
- * VARIANT_KUKUI_POGO_KEYBOARD
- * VARIANT_KUKUI_POGO_DOCK
- */
-#ifdef VARIANT_KUKUI_POGO_DOCK
-#ifndef VARIANT_KUKUI_POGO_KEYBOARD
-#error VARIANT_KUKUI_POGO_KEYBOARD is mandatory if use dock
-#endif /* !VARIANT_KUKUI_POGO_KEYBOARD */
-#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 1
-#endif /* VARIANT_KUKUI_POGO_DOCK */
-
-#ifdef VARIANT_KUKUI_POGO_KEYBOARD
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_BASE_ATTACHED_SWITCH
-#endif
-
-/* define this if the board is jacuzzi family */
-#ifdef VARIANT_KUKUI_JACUZZI
-#define CONFIG_HOSTCMD_AP_SET_SKUID
-/*
- * IT81202 based boards are variant of jacuzzi and I/O expander isn't required
- * on them.
- */
-#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_IT8801
-#define CONFIG_IO_EXPANDER_PORT_COUNT 1
-#define CONFIG_KEYBOARD_NOT_RAW
-
-#endif
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-#define PD_OPERATING_POWER_MW 30000
-
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-#else /* !VARIANT_KUKUI_JACUZZI */
-
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
-#endif /* VARIANT_KUKUI_JACUZZI */
-
-#if defined(SECTION_IS_RW) || defined(VARIANT_KUKUI_EC_IT81202)
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#endif
-
-/*
- * Define this flag if board controls dp mux via gpio pins USB_C0_DP_OE_L and
- * USB_C0_DP_POLARITY.
- *
- * board must provide function board_set_dp_mux_control(output_enable, polarity)
- *
- * #define VARIANT_KUKUI_DP_MUX_GPIO
- */
-
-/* Optional modules */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_CHIPSET_MT8183
-#define CONFIG_CMD_ACCELS
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-#ifdef SECTION_IS_RO
-#undef CONFIG_SYSTEM_UNLOCKED /* Disabled in RO to save space */
-#else
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-#endif
-
-/* Bootblock */
-#ifdef SECTION_IS_RO
-#define CONFIG_BOOTBLOCK
-
-#define EMMC_SPI_PORT 2
-#endif
-
-/* Optional features */
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_PRESERVE_LOGS
-
-/* Required for FAFT */
-#define CONFIG_CMD_BUTTON
-#define CONFIG_CMD_CHARGEN
-
-/* By default, set hcdebug to off */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-#define CONFIG_LTO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_VBOOT_HASH
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#define CONFIG_USB_CHARGER
-
-/* Increase tx buffer size, as we'd like to stream EC log to AP. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-#define GPIO_LID_OPEN GPIO_HALL_INT_L
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-#ifndef VARIANT_KUKUI_TABLET_PWRBTN
-#define POWERBTN_BOOT_DELAY 0
-#endif
-
-/* USB PD config */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#ifdef BOARD_KODAMA
-#define PD_MAX_CURRENT_MA     2000
-#else
-#define PD_MAX_CURRENT_MA     3000
-#endif
-
-/* Optional for testing */
-#undef CONFIG_PECI
-#undef CONFIG_PSTORE
-
-#define CONFIG_TASK_PROFILING
-#define CONFIG_MKBP_USE_GPIO
-
-/*
- * Variant EC defines. Pick one:
- * VARIANT_KUKUI_EC_STM32F098
- * VARIANT_KUKUI_EC_IT81202
- * VARIANT_KUKUI_EC_STM32L431
- */
-#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
-/* Timer selection */
-#define TIM_CLOCK32  2
-#define TIM_WATCHDOG 7
-
-/* 48 MHz SYSCLK clock frequency */
-#ifdef VARIANT_KUKUI_EC_STM32L431
-#define CPU_CLOCK 80000000
-#else
-#define CPU_CLOCK 48000000
-#endif
-
-#undef  CONFIG_HIBERNATE
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_WATCHDOG_HELP
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_RX_DMA
-
-/* This option is limited to TCPMv1 */
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-/* STM32F098 based boards use TCPMv1 */
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_BATTFAKE
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_MD
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_TIMERINFO
-
-/* save space at RO image */
-#ifdef SECTION_IS_RO
-#undef CONFIG_CMD_ADC
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CRASH
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_IDLE_STATS
-#undef CONFIG_CMD_MFALLOW
-#undef CONFIG_CMD_MMAPINFO
-#undef CONFIG_CMD_PWR_AVG
-#undef CONFIG_CMD_REGULATOR
-#undef CONFIG_CMD_RW
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_CMD_SLEEPMASK
-#undef CONFIG_CMD_SLEEPMASK_SET
-#undef CONFIG_CMD_SYSLOCK
-#undef CONFIG_CMD_TYPEC
-#undef CONFIG_HOSTCMD_FLASHPD
-#undef CONFIG_HOSTCMD_RWHASHPD
-#undef CONFIG_CONSOLE_CMDHELP
-
-#undef CONFIG_HOSTCMD_GET_UPTIME_INFO
-#undef CONFIG_CMD_AP_RESET_LOG
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_I2C_XFER
-
-/* free flash space */
-#undef CONFIG_USB_PD_DEBUG_LEVEL
-#define CONFIG_USB_PD_DEBUG_LEVEL 0
-#undef CONFIG_USB_PD_LOGGING
-#define CONFIG_COMMON_GPIO_SHORTNAMES
-#define CONFIG_DEBUG_ASSERT_BRIEF
-/* Exclude PD state names from RO image to save space */
-#undef CONFIG_USB_PD_TCPMV1_DEBUG
-#endif
-#elif defined(VARIANT_KUKUI_EC_IT81202)
-#define CONFIG_IT83XX_HARD_RESET_BY_GPG1
-#define CONFIG_IT83XX_VCC_1P8V
-
-/* IT81202 based boards use TCPMv2 */
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_TCPMV2
-#else
-#error "Must define a VARIANT_KUKUI_EC_XXX!"
-#endif
-
-#ifndef __ASSEMBLER__
-#ifdef VARIANT_KUKUI_DP_MUX_GPIO
-void board_set_dp_mux_control(int output_enable, int polarity);
-#endif /* VARIANT_KUKUI_DP_MUX_GPIO */
-
-/* If POGO pin is providing power. */
-int kukui_pogo_extpower_present(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c
deleted file mode 100644
index 94f46b3326..0000000000
--- a/baseboard/kukui/battery_bq27541.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "charger_mt6370.h"
-#include "console.h"
-#include "driver/tcpm/mt6370.h"
-#include "ec_commands.h"
-#include "util.h"
-
-#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
-
-#define BATT_ID 0
-
-#define BATTERY_CPT_CHARGE_MIN_TEMP 0
-#define BATTERY_CPT_CHARGE_MAX_TEMP 50
-
-#define CHARGER_LIMIT_TIMEOUT_HOURS 48
-#define CHARGER_LIMIT_TIMEOUT_HOURS_TEMP 2
-
-#define BAT_LEVEL_PD_LIMIT 85
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_CPT = 0,
-	BATTERY_COUNT
-};
-
-static const struct battery_info info[] = {
-	[BATTERY_CPT] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_voltage	= 3400,
-		.precharge_current	= 256,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 50,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info[BATT_ID];
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	static timestamp_t deadline_48;
-	static timestamp_t deadline_2;
-	int cycle_count = 0, rv, val;
-	unsigned char rcv = 0, rcv_cycle = 0, rcv_soh = 0;
-	/* (FullCharge Capacity / Design Capacity) * 100 = SOH */
-	int full_cap = 0, design_cap = 0, soh = 0;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *        ZONE_0   ZONE_1     ZONE_2
-	 * -----+--------+--------+------------+----- Temperature (C)
-	 *      t0       t1       t2           t3
-	 */
-	enum {
-		TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */
-		TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */
-		TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */
-		TEMP_ZONE_3, /* t3 < bat_temp_c <= t4 */
-		TEMP_ZONE_COUNT
-	} temp_zone;
-
-	static struct {
-		int temp_min; /* 0.1 deg C */
-		int temp_max; /* 0.1 deg C */
-		int desired_current; /* mA */
-		int desired_voltage; /* mV */
-	} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
-		[BATTERY_CPT] = {
-			/* TEMP_ZONE_0 */
-			{BATTERY_CPT_CHARGE_MIN_TEMP * 10, 150, 1408, 4370},
-			/* TEMP_ZONE_1 */
-			{150, 430, 3520, 4370},
-			/* TEMP_ZONE_2 */
-			{430, 450, 2112, 4320},
-			/* TEMP_ZONE_3 */
-			{450, BATTERY_CPT_CHARGE_MAX_TEMP * 10, 1760, 4170},
-		},
-	};
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < temp_zones[BATT_ID][0].temp_min) ||
-	    (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else {
-		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
-			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
-				break;
-		}
-	}
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-	case TEMP_ZONE_1:
-	case TEMP_ZONE_2:
-	case TEMP_ZONE_3:
-		curr->requested_current =
-			temp_zones[BATT_ID][temp_zone].desired_current;
-		curr->requested_voltage =
-			temp_zones[BATT_ID][temp_zone].desired_voltage;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		curr->requested_current = curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-		break;
-	}
-
-	/* Check cycle count to decrease charging voltage. */
-	rv = battery_cycle_count(&val);
-	if (!rv)
-		cycle_count = val;
-	if (cycle_count > 20 && cycle_count <= 50)
-		rcv_cycle = 50;
-	else if (cycle_count > 50 && cycle_count <= 300)
-		rcv_cycle = 65;
-	else if (cycle_count > 300 && cycle_count <= 600)
-		rcv_cycle = 80;
-	else if (cycle_count > 600 && cycle_count <= 1000)
-		rcv_cycle = 100;
-	else if (cycle_count > 1000)
-		rcv_cycle = 150;
-	/* Check SOH to decrease charging voltage. */
-	if (!battery_full_charge_capacity(&full_cap) &&
-		!battery_design_capacity(&design_cap))
-		soh = ((full_cap * 100) / design_cap);
-	if (soh > 70 && soh <= 75)
-		rcv_soh = 50;
-	else if (soh > 60 && soh <= 70)
-		rcv_soh = 65;
-	else if (soh > 55 && soh <= 60)
-		rcv_soh = 80;
-	else if (soh > 50 && soh <= 55)
-		rcv_soh = 100;
-	else if (soh <= 50)
-		rcv_soh = 150;
-	rcv = MAX(rcv_cycle, rcv_soh);
-	curr->requested_voltage -= rcv;
-
-	/* Should not keep charging voltage > 4250mV for 48hrs. */
-	if ((curr->state == ST_DISCHARGE) ||
-		curr->chg.voltage < 4250) {
-		deadline_48.val = 0;
-	/* Starting count 48hours */
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
-		if (deadline_48.val == 0)
-			deadline_48.val = get_time().val +
-				CHARGER_LIMIT_TIMEOUT_HOURS * HOUR;
-		/* If charging voltage keep > 4250 for 48hrs,
-		 * set charging voltage = 4250
-		 */
-		else if (timestamp_expired(deadline_48, NULL))
-			curr->requested_voltage = 4250;
-	}
-	/* Should not keeep battery voltage > 4100mV and
-	 * battery temperature > 45C for two hour
-	 */
-	if (curr->state == ST_DISCHARGE ||
-		curr->batt.voltage < 4100 ||
-		bat_temp_c < 450) {
-		deadline_2.val = 0;
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
-		if (deadline_2.val == 0)
-			deadline_2.val = get_time().val +
-				CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR;
-		else if (timestamp_expired(deadline_2, NULL)) {
-			/* Set discharge and charging voltage = 4100mV */
-			if (curr->batt.voltage >= 4100) {
-				curr->requested_current = 0;
-				curr->requested_voltage = 4100;
-			}
-		}
-	}
-
-#ifdef VARIANT_KUKUI_CHARGER_MT6370
-	mt6370_charger_profile_override(curr);
-#endif /* CONFIG_CHARGER_MT6370 */
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-int get_battery_manufacturer_name(char *dest, int size)
-{
-	static const char * const name[] = {
-		[BATTERY_CPT] = "AS1XXXD3Ka",
-	};
-	ASSERT(dest);
-	strzcpy(dest, name[BATT_ID], size);
-	return EC_SUCCESS;
-}
diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c
deleted file mode 100644
index 6247f665aa..0000000000
--- a/baseboard/kukui/battery_max17055.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "charger_mt6370.h"
-#include "console.h"
-#include "driver/battery/max17055.h"
-#include "ec_commands.h"
-#include "util.h"
-
-#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
-
-#define BATT_ID 0
-
-#define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0
-#define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_COUNT
-};
-
-static const struct battery_info info[] = {
-	[BATTERY_SIMPLO] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3860,
-		.voltage_min		= 3000,
-		.precharge_current	= 256,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-};
-
-static const struct max17055_batt_profile batt_profile[] = {
-	[BATTERY_SIMPLO] = {
-		.is_ez_config		= 1,
-		.design_cap		= MAX17055_DESIGNCAP_REG(6910),
-		.ichg_term		= MAX17055_ICHGTERM_REG(235),
-		.v_empty_detect		= MAX17055_VEMPTY_REG(3000, 3600),
-	},
-};
-
-static const struct max17055_alert_profile alert_profile[] = {
-	[BATTERY_SIMPLO] = {
-		.v_alert_mxmn = VALRT_DISABLE,
-		.t_alert_mxmn = MAX17055_TALRTTH_REG(
-			BATTERY_SIMPLO_CHARGE_MAX_TEMP,
-			BATTERY_SIMPLO_CHARGE_MIN_TEMP),
-		.s_alert_mxmn = SALRT_DISABLE,
-		.i_alert_mxmn = IALRT_DISABLE,
-	},
-};
-
-const struct max17055_batt_profile *max17055_get_batt_profile(void)
-{
-	return &batt_profile[BATT_ID];
-}
-
-const struct max17055_alert_profile *max17055_get_alert_profile(void)
-{
-	return &alert_profile[BATT_ID];
-}
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info[BATT_ID];
-}
-
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	if (battery_is_present() == BP_YES)
-		return BATTERY_NOT_DISCONNECTED;
-	return BATTERY_DISCONNECTED;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *        ZONE_0   ZONE_1     ZONE_2
-	 * -----+--------+--------+------------+----- Temperature (C)
-	 *      t0       t1       t2           t3
-	 */
-	enum {
-		TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */
-		TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */
-		TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */
-		TEMP_ZONE_3, /* t3 < bat_temp_c <= t4 */
-		TEMP_ZONE_COUNT
-	} temp_zone;
-	static struct {
-		int temp_min; /* 0.1 deg C */
-		int temp_max; /* 0.1 deg C */
-		int desired_current; /* mA */
-		int desired_voltage; /* mV */
-	} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
-		[BATTERY_SIMPLO] = {
-			/* Add a empty range here to avoid TEMP_ZONE_COUNT mismatch. */
-			/* TEMP_ZONE_0 */
-			{BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10,
-				BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10, 1772, 4376},
-			/* TEMP_ZONE_1 */
-			{BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10, 150, 1772, 4376},
-			/* TEMP_ZONE_2 */
-			{150, 450, 4020, 4376},
-			/* TEMP_ZONE_3 */
-			{450, BATTERY_SIMPLO_CHARGE_MAX_TEMP * 10, 3350, 4300},
-		},
-	};
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones[BATT_ID]) == TEMP_ZONE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < temp_zones[BATT_ID][0].temp_min) ||
-	    (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else {
-		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
-			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
-				break;
-		}
-	}
-
-	if (curr->state != ST_CHARGE)
-		return 0;
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-	case TEMP_ZONE_1:
-	case TEMP_ZONE_2:
-	case TEMP_ZONE_3:
-		curr->requested_current =
-			temp_zones[BATT_ID][temp_zone].desired_current;
-		curr->requested_voltage =
-			temp_zones[BATT_ID][temp_zone].desired_voltage;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		curr->requested_current = curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-		break;
-	}
-
-#ifdef VARIANT_KUKUI_CHARGER_MT6370
-	mt6370_charger_profile_override(curr);
-#endif /* CONFIG_CHARGER_MT6370 */
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-int get_battery_manufacturer_name(char *dest, int size)
-{
-	static const char * const name[] = {
-		[BATTERY_SIMPLO] = "SIMPLO",
-	};
-	ASSERT(dest);
-	strzcpy(dest, name[BATT_ID], size);
-	return EC_SUCCESS;
-}
-
diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c
deleted file mode 100644
index e7f422e561..0000000000
--- a/baseboard/kukui/battery_mm8013.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "charger_mt6370.h"
-#include "console.h"
-#include "driver/tcpm/mt6370.h"
-#include "ec_commands.h"
-#include "util.h"
-
-#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
-
-#define BATT_ID 0
-
-#define BATTERY_SCUD_CHARGE_MIN_TEMP 0
-#define BATTERY_SCUD_CHARGE_MAX_TEMP 50
-
-#define BAT_LEVEL_PD_LIMIT 85
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SCUD = 0,
-	BATTERY_COUNT
-};
-
-static const struct battery_info info[] = {
-	[BATTERY_SCUD] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3850,
-		.voltage_min		= 3000,
-		.precharge_voltage	= 3400,
-		.precharge_current	= 256,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 50,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 59,
-	},
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info[BATT_ID];
-}
-
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	if (battery_is_present() == BP_YES)
-		return BATTERY_NOT_DISCONNECTED;
-	return BATTERY_DISCONNECTED;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *        ZONE_0   ZONE_1     ZONE_2
-	 * -----+--------+--------+------------+----- Temperature (C)
-	 *      t0       t1       t2           t3
-	 */
-	enum {
-		TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */
-		TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */
-		TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */
-		TEMP_ZONE_COUNT
-	} temp_zone;
-
-	static struct {
-		int temp_min; /* 0.1 deg C */
-		int temp_max; /* 0.1 deg C */
-		int desired_current; /* mA */
-		int desired_voltage; /* mV */
-	} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
-		[BATTERY_SCUD] = {
-		/* TEMP_ZONE_0 */
-		{BATTERY_SCUD_CHARGE_MIN_TEMP * 10, 150, 1400, 4400},
-		/* TEMP_ZONE_1 */
-		{150, 450, 3500, 4400},
-		/* TEMP_ZONE_2 */
-		{450, BATTERY_SCUD_CHARGE_MAX_TEMP * 10, 3500, 4200},
-		},
-	};
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < temp_zones[BATT_ID][0].temp_min) ||
-	    (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else {
-		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
-			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
-				break;
-		}
-	}
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-	case TEMP_ZONE_1:
-	case TEMP_ZONE_2:
-		curr->requested_current =
-			temp_zones[BATT_ID][temp_zone].desired_current;
-		curr->requested_voltage =
-			temp_zones[BATT_ID][temp_zone].desired_voltage;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		curr->requested_current = curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-		break;
-	}
-
-#ifdef VARIANT_KUKUI_CHARGER_MT6370
-	mt6370_charger_profile_override(curr);
-#endif /* CONFIG_CHARGER_MT6370 */
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c
deleted file mode 100644
index ba2af17443..0000000000
--- a/baseboard/kukui/battery_smart.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "timer.h"
-#include "util.h"
-
-enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres = BP_NOT_SURE;
-
-#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-#endif
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres == BP_NO)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Check battery disconnect status. If we are unable to read battery
-	 * disconnect status, then return BP_NOT_SURE. Battery could be in ship
-	 * mode and might require pre-charge current to wake it up. BP_NO is not
-	 * returned here because charger state machine will not provide
-	 * pre-charge current assuming that battery is not present.
-	 */
-	if (battery_get_disconnect_state() == BATTERY_DISCONNECT_ERROR)
-		return BP_NOT_SURE;
-
-	/* Ensure the battery is not in cutoff state */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL)
-		return BP_NO;
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
-
-#ifdef CONFIG_I2C_BITBANG
-static void fix_single_param(int flag, int *cached, int *curr)
-{
-	if (flag)
-		*curr = *cached;
-	else
-		*cached = *curr;
-}
-
-#define CACHE_INVALIDATION_TIME_US (5 * SECOND)
-
-/*
- * b:144195782: bitbang fails randomly, and there's no way to
- * notify kernel side that bitbang read failed.
- * Thus, if any value in batt_params is bad, replace it with a cached
- * good value, to make sure we never send random numbers to kernel
- * side.
- */
-__override void board_battery_compensate_params(struct batt_params *batt)
-{
-	static struct batt_params batt_cache = { 0 };
-	static timestamp_t deadline;
-
-	/*
-	 * If battery keeps failing for 5 seconds, stop hiding the error and
-	 * report back to host.
-	 */
-	if (batt->flags & BATT_FLAG_BAD_ANY) {
-		if (timestamp_expired(deadline, NULL))
-			return;
-	} else {
-		deadline.val = get_time().val + CACHE_INVALIDATION_TIME_US;
-	}
-
-	/* return cached values for at most CACHE_INVALIDATION_TIME_US */
-	fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE,
-			&batt_cache.state_of_charge,
-			&batt->state_of_charge);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE,
-			&batt_cache.voltage,
-			&batt->voltage);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT,
-			&batt_cache.current,
-			&batt->current);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE,
-			&batt_cache.desired_voltage,
-			&batt->desired_voltage);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT,
-			&batt_cache.desired_current,
-			&batt->desired_current);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY,
-			&batt_cache.remaining_capacity,
-			&batt->remaining_capacity);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY,
-			&batt_cache.full_capacity,
-			&batt->full_capacity);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS,
-			&batt_cache.status,
-			&batt->status);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE,
-			&batt_cache.temperature,
-			&batt->temperature);
-	/*
-	 * If battery_compensate_params() didn't calculate display_charge
-	 * for us, also update it with last good value.
-	 */
-	fix_single_param(batt->display_charge == 0,
-			&batt_cache.display_charge,
-			&batt->display_charge);
-
-	/* remove bad flags after applying cached values */
-	batt->flags &= ~BATT_FLAG_BAD_ANY;
-}
-#endif /* CONFIG_I2C_BITBANG */
diff --git a/baseboard/kukui/build.mk b/baseboard/kukui/build.mk
deleted file mode 100644
index c64f6978c8..0000000000
--- a/baseboard/kukui/build.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-# Select eMMC CMD0 driver.
-EMMC_CMD0_DRIVER=$(if $(CHIP_IT83XX),emmc_ite.o,emmc.o)
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(CONFIG_BOOTBLOCK)+=$(EMMC_CMD0_DRIVER)
-
-baseboard-$(VARIANT_KUKUI_BATTERY_MAX17055)+=battery_max17055.o
-baseboard-$(VARIANT_KUKUI_BATTERY_MM8013)+=battery_mm8013.o
-baseboard-$(VARIANT_KUKUI_BATTERY_BQ27541)+=battery_bq27541.o
-baseboard-$(VARIANT_KUKUI_BATTERY_SMART)+=battery_smart.o
-
-baseboard-$(VARIANT_KUKUI_CHARGER_MT6370)+=charger_mt6370.o
-
-baseboard-$(VARIANT_KUKUI_POGO_KEYBOARD)+=base_detect_kukui.o
-
-$(out)/RO/baseboard/$(BASEBOARD)/$(EMMC_CMD0_DRIVER): $(out)/bootblock_data.h
-
-# bootblock size from 12769.0
-DEFAULT_BOOTBLOCK_SIZE:=21504
diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c
deleted file mode 100644
index 327b567db6..0000000000
--- a/baseboard/kukui/charger_mt6370.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger_mt6370.h"
-#include "console.h"
-#include "driver/charger/rt946x.h"
-#include "driver/tcpm/mt6370.h"
-#include "hooks.h"
-#include "power.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define BAT_LEVEL_PD_LIMIT 85
-#define SYSTEM_PLT_MW 3500
-/*
- * b/143318064: Prefer a voltage above 5V to force it picks a voltage
- * above 5V at first. If PREFER_MV is 5V, when desired power is around
- * 15W ~ 11W, it would pick 5V/3A initially, and mt6370 can only sink
- * around 10W, and cause a low charging efficiency.
- */
-#define PREVENT_CURRENT_DROP_MV 6000
-#define DEFAULT_PREFER_MV 5000
-/*
- * We empirically chose 300mA as the limit for when buck inefficiency is
- * noticeable.
- */
-#define STABLE_CURRENT_DELTA 300
-
-struct pd_pref_config_t pd_pref_config = {
-	.mv = PREVENT_CURRENT_DROP_MV,
-	.cv = 70,
-	.plt_mw = SYSTEM_PLT_MW,
-	.type = PD_PREFER_BUCK,
-};
-
-static void update_plt_suspend(void)
-{
-	pd_pref_config.plt_mw = 0;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, update_plt_suspend, HOOK_PRIO_DEFAULT);
-
-static void update_plt_resume(void)
-{
-	pd_pref_config.plt_mw = SYSTEM_PLT_MW;
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT);
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* wait time to evaluate charger thermal status */
-static timestamp_t thermal_wait_until;
-/* input current bound when charger throttled */
-static int throttled_ma = PD_MAX_CURRENT_MA;
-/* charge_ma in last board_set_charge_limit call */
-static int prev_charge_limit;
-/* charge_mv in last board_set_charge_limit call */
-static int prev_charge_mv;
-
-#ifndef CONFIG_BATTERY_SMART
-int board_cut_off_battery(void)
-{
-	/* The cut-off procedure is recommended by Richtek. b/116682788 */
-	rt946x_por_reset();
-	mt6370_vconn_discharge(0);
-	rt946x_cutoff_battery();
-
-	return EC_SUCCESS;
-}
-#endif
-
-static void board_set_charge_limit_throttle(int charge_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MIN(throttled_ma, MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT)),
-		charge_mv);
-}
-
-static void battery_thermal_control(struct charge_state_data *curr)
-{
-	int input_current, jc_temp;
-	static int skip_reset;
-	/*
-	 * mt6370's input current setting is 50mA step, use 50 as well for
-	 * easy value mapping.
-	 */
-	const int k_p = 50;
-
-	if (charge_manager_get_charger_voltage() == 5000 ||
-	    curr->state != ST_CHARGE) {
-		/* We already set the charge limit, do not reset it again. */
-		if (skip_reset)
-			return;
-		skip_reset = 1;
-		thermal_wait_until.val = 0;
-		throttled_ma = PD_MAX_CURRENT_MA;
-		board_set_charge_limit_throttle(prev_charge_limit,
-						prev_charge_mv);
-		return;
-	}
-
-	skip_reset = 0;
-
-	if (thermal_wait_until.val == 0)
-		goto thermal_exit;
-
-	if (get_time().val < thermal_wait_until.val)
-		return;
-
-	/* If we fail to read adc, skip for this cycle. */
-	if (rt946x_get_adc(MT6370_ADC_TEMP_JC, &jc_temp))
-		return;
-
-	/* If we fail to read input curr limit, skip for this cycle. */
-	if (charger_get_input_current_limit(CHARGER_SOLO, &input_current))
-		return;
-
-	/*
-	 * If input current limit is maximum, and we are under thermal budget,
-	 * just skip.
-	 */
-	if (input_current == PD_MAX_CURRENT_MA &&
-	    jc_temp < thermal_bound.target + thermal_bound.err)
-		return;
-
-	/* If the temp is within +- err, thermal is under control */
-	if (jc_temp < thermal_bound.target + thermal_bound.err &&
-	    jc_temp > thermal_bound.target - thermal_bound.err)
-		return;
-
-	/*
-	 * PID algorithm (https://en.wikipedia.org/wiki/PID_controller),
-	 * and operates on only P value.
-	 */
-	throttled_ma = MIN(
-		PD_MAX_CURRENT_MA,
-		/*
-		 * Should not pass the previously set input current by
-		 * charger manager.  This value might be related the charger's
-		 * capability.
-		 */
-		MIN(prev_charge_limit,
-		    input_current + k_p * (thermal_bound.target - jc_temp)));
-
-	/* If the input current doesn't change, just skip. */
-	if (throttled_ma != input_current)
-		board_set_charge_limit_throttle(throttled_ma, prev_charge_mv);
-
-thermal_exit:
-	thermal_wait_until.val = get_time().val + (3 * SECOND);
-}
-
-int command_jc(int argc, char **argv)
-{
-	static int prev_jc_temp;
-	int jc_temp;
-
-	if (rt946x_get_adc(MT6370_ADC_TEMP_JC, &jc_temp))
-		jc_temp = prev_jc_temp;
-
-	ccprintf("JC Temp: %d\n", jc_temp);
-	prev_jc_temp = jc_temp;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(jc, command_jc, "", "mt6370 junction temp");
-
-/*
- * b/143318064: A workwround for mt6370 bad buck efficiency.
- * If the delta of VBUS and VBAT(on krane, desired voltage 4.4V) is too small
- * (i.e. < 500mV), the buck throughput will be bounded, and causing that we
- * can't drain 5V/3A when battery SoC above around 40%.
- * This function watches battery current. If we see battery current drops after
- * switching from high voltage to 5V (This will happen if we enable
- * CONFIG_USB_PD_PREFER_MV and set prefer votage to 5V), the charger will lost
- * power due to the inefficiency (e.g. switch from 9V/1.67A = 15W to 5V/3A,
- * but mt6370 would only sink less than 5V/2.4A = 12W), and we will request a
- * higher voltage PDO to prevent a slow charging time.
- */
-static void battery_desired_curr_dynamic(struct charge_state_data *curr)
-{
-	static int prev_stable_current = CHARGE_CURRENT_UNINITIALIZED;
-	static int prev_supply_voltage;
-	int supply_voltage;
-	int stable_current;
-	int delta_current;
-
-	if (curr->state != ST_CHARGE) {
-		prev_supply_voltage = 0;
-		prev_stable_current = CHARGE_CURRENT_UNINITIALIZED;
-		/*
-		 * Always force higher voltage on first PD negotiation.
-		 * When desired power is around 15W ~ 11W, PD would pick
-		 * 5V/3A initially, but mt6370 can't drain that much, and
-		 * causes a low charging efficiency.
-		 */
-		pd_pref_config.mv = PREVENT_CURRENT_DROP_MV;
-		return;
-	}
-
-	supply_voltage = charge_manager_get_charger_voltage();
-	stable_current = charge_get_stable_current();
-
-	if (!charge_is_current_stable())
-		return;
-
-	if (!prev_supply_voltage)
-		goto update_charge;
-
-	delta_current = prev_stable_current - stable_current;
-	if (curr->batt.state_of_charge >= pd_pref_config.cv &&
-	    supply_voltage == DEFAULT_PREFER_MV &&
-	    prev_supply_voltage > supply_voltage &&
-	    delta_current > STABLE_CURRENT_DELTA) {
-		/* Raise perfer voltage above 5000mV */
-		pd_pref_config.mv = PREVENT_CURRENT_DROP_MV;
-		/*
-		 * Delay stable current evaluation for 5 mins if we see a
-		 * current drop.  It's a reasonable waiting time since that
-		 * the battery desired current can't catch the gap that fast
-		 * in the period.
-		 */
-		charge_reset_stable_current_us(5 * MINUTE);
-		/* Rewrite the stable current to re-evalute desired watt */
-		charge_set_stable_current(prev_stable_current);
-
-		/*
-		 * do not alter current by thermal if we just raising PD
-		 * voltage
-		 */
-		thermal_wait_until.val = get_time().val + (10 * SECOND);
-	} else {
-		pd_pref_config.mv = DEFAULT_PREFER_MV;
-		/*
-		 * If the power supply is plugged while battery full,
-		 * the stable_current will always be 0 such that we are unable
-		 * to switch to 5V. We force evaluating PDO to switch to 5V.
-		 */
-		if (prev_supply_voltage == supply_voltage && !stable_current &&
-		    !prev_stable_current &&
-		    supply_voltage != DEFAULT_PREFER_MV &&
-		    charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
-			pd_set_new_power_request(
-				charge_manager_get_active_charge_port());
-	}
-
-update_charge:
-	prev_supply_voltage = supply_voltage;
-	prev_stable_current = stable_current;
-}
-
-#ifdef CONFIG_BATTERY_SMART
-static void charge_enable_eoc_and_te(void)
-{
-	rt946x_enable_charge_eoc(1);
-	rt946x_enable_charge_termination(1);
-}
-DECLARE_DEFERRED(charge_enable_eoc_and_te);
-#endif
-
-void mt6370_charger_profile_override(struct charge_state_data *curr)
-{
-	static int previous_chg_limit_mv;
-	int chg_limit_mv = pd_get_max_voltage();
-
-	battery_desired_curr_dynamic(curr);
-
-	battery_thermal_control(curr);
-
-#ifdef CONFIG_BATTERY_SMART
-	/*
-	 * SMP battery uses HW pre-charge circuit and pre-charge current is
-	 * limited to ~50mA. Once the charge current is lower than IEOC level
-	 * within CHG_TEDG_EOC, and TE is enabled, the charging power path will
-	 * be turned off. Disable EOC and TE when battery stays over discharge
-	 * state, otherwise enable EOC and TE.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) {
-		const struct battery_info *batt_info = battery_get_info();
-		static int normal_charge_lock, over_discharge_lock;
-
-		if (curr->batt.voltage < batt_info->voltage_min) {
-			normal_charge_lock = 0;
-
-			if (!over_discharge_lock && curr->state == ST_CHARGE) {
-				over_discharge_lock = 1;
-				rt946x_enable_charge_eoc(0);
-				rt946x_enable_charge_termination(0);
-			}
-		} else {
-			over_discharge_lock = 0;
-
-			if (!normal_charge_lock) {
-				normal_charge_lock = 1;
-				/*
-				 * b/148045048: When the battery is activated
-				 * in shutdown mode, the adapter cannot boot
-				 * DUT automatically. It's a workaround to
-				 * delay 4.5 second to enable charger EOC
-				 * and TE function.
-				 */
-				hook_call_deferred(
-						&charge_enable_eoc_and_te_data,
-						(4.5 * SECOND));
-			}
-		}
-	}
-#endif
-
-	/* Limit input (=VBUS) to 5V when soc > 85% and charge current < 1A. */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT) &&
-	    charge_get_percent() > BAT_LEVEL_PD_LIMIT &&
-	    curr->batt.current < 1000 && power_get_state() != POWER_S0)
-		chg_limit_mv = 5500;
-	else
-		chg_limit_mv = PD_MAX_VOLTAGE_MV;
-
-	if (chg_limit_mv != previous_chg_limit_mv)
-		CPRINTS("VBUS limited to %dmV", chg_limit_mv);
-	previous_chg_limit_mv = chg_limit_mv;
-
-	/* Pull down VBUS */
-	if (pd_get_max_voltage() != chg_limit_mv)
-		pd_set_external_voltage_limit(0, chg_limit_mv);
-
-	/*
-	 * When the charger says it's done charging, even if fuel gauge says
-	 * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with
-	 * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI
-	 * and battery LED indicate full charge.
-	 *
-	 * Enable this hack on on-board gauge only (b/142097561)
-	 */
-	if (IS_ENABLED(CONFIG_BATTERY_MAX17055) && rt946x_is_charge_done()) {
-		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
-						 curr->batt.state_of_charge);
-	}
-
-}
-
-#ifndef CONFIG_BATTERY_SMART
-static void board_charge_termination(void)
-{
-	static uint8_t te;
-	/* Enable charge termination when we are sure battery is present. */
-	if (!te && battery_is_present() == BP_YES) {
-		if (!rt946x_enable_charge_termination(1))
-			te = 1;
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
-	     HOOK_PRIO_DEFAULT);
-#endif
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	prev_charge_limit = charge_ma;
-	prev_charge_mv = charge_mv;
-	board_set_charge_limit_throttle(charge_ma, charge_mv);
-}
diff --git a/baseboard/kukui/charger_mt6370.h b/baseboard/kukui/charger_mt6370.h
deleted file mode 100644
index 880b00a1a8..0000000000
--- a/baseboard/kukui/charger_mt6370.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BASEBOARD_CHARGER_MT6370_H
-#define __CROS_EC_BASEBOARD_CHARGER_MT6370_H
-
-#include "charge_state.h"
-
-void mt6370_charger_profile_override(struct charge_state_data *curr);
-
-struct mt6370_thermal_bound {
-	/* mt6370 junction's thermal target in Celsius degree */
-	int target;
-	/* mt6370 junction's thermal evaluation error in Celsius degree */
-	int err;
-};
-
-extern struct mt6370_thermal_bound thermal_bound;
-#endif
diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c
deleted file mode 100644
index 68953d8923..0000000000
--- a/baseboard/kukui/emmc.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Transfer bootblock over SPI by emulating eMMC "Alternative Boot operation"
- * (section 6.3.4 of eMMC 5.0 specification, JESD84-B50).
- *
- * eMMC boot operation looks a lot like SPI: CMD is unidirectional MOSI, DAT is
- * unidirectional MISO. CLK is driven by the master. However, there is no
- * chip-select, and the clock is active for a long time before any command is
- * sent on the CMD line. From SPI perspective, this looks like a lot of '1'
- * are being sent from the master.
- *
- * To catch the commands, we setup DMA to write the data into a circular buffer
- * (in_msg), and monitor for a falling edge on CMD (emmc_cmd_interrupt). Once
- * an interrupt is received, we scan the circular buffer, in reverse, to
- * be as fast as possible and minimize chances of missing the command.
- *
- * We then figure out the bit-wise command alignment, decode it, and, upon
- * receiving BOOT_INITIATION command, setup DMA to respond with the data on the
- * DAT line. The data in bootblock_data.h is preprocessed to include necessary
- * eMMC headers: acknowledge boot mode, start of block, CRC, end of block, etc.
- * The host can only slow down transfer by stopping the clock, which is
- * compatible with SPI.
- *
- * In some cases (e.g. if the BootROM expects data over 8 lanes instead of 1),
- * the BootROM will quickly interrupt the transfer with an IDLE command. In this
- * case we interrupt the transfer, and the BootROM will try again.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "dma.h"
-#include "endian.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#include "bootblock_data.h"
-
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-#if EMMC_SPI_PORT == 1
-#define STM32_SPI_EMMC_REGS STM32_SPI1_REGS
-#define STM32_DMAC_SPI_EMMC_TX STM32_DMAC_SPI1_TX
-#define STM32_DMAC_SPI_EMMC_RX STM32_DMAC_SPI1_RX
-#elif EMMC_SPI_PORT == 2
-#define STM32_SPI_EMMC_REGS STM32_SPI2_REGS
-#define STM32_DMAC_SPI_EMMC_TX STM32_DMAC_SPI2_TX
-#define STM32_DMAC_SPI_EMMC_RX STM32_DMAC_SPI2_RX
-#else
-#error "Please define EMMC_SPI_PORT in board.h."
-#endif
-
-/* Is eMMC emulation enabled? */
-static int emmc_enabled;
-
-/* Maximum amount of time to wait for AP to boot. */
-static timestamp_t boot_deadline;
-#define BOOT_TIMEOUT (5 * SECOND)
-#define EMMC_STATUS_CHECK_PERIOD (10 * MSEC)
-
-/* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */
-#define SPI_RX_BUF_BYTES 1024
-#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4)
-static uint32_t in_msg[SPI_RX_BUF_WORDS];
-
-/* Macros to advance in the circular buffer. */
-#define RX_BUF_NEXT_32(i) (((i) + 1) & (SPI_RX_BUF_WORDS - 1))
-#define RX_BUF_DEC_32(i, j) (((i) - (j)) & (SPI_RX_BUF_WORDS - 1))
-#define RX_BUF_PREV_32(i) RX_BUF_DEC_32((i), 1)
-
-enum emmc_cmd {
-	EMMC_ERROR = -1,
-	EMMC_IDLE = 0,
-	EMMC_PRE_IDLE,
-	EMMC_BOOT,
-};
-
-static const struct dma_option dma_tx_option = {
-	STM32_DMAC_SPI_EMMC_TX, (void *)&STM32_SPI_EMMC_REGS->dr,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-};
-
-/* Circular RX buffer */
-static const struct dma_option dma_rx_option = {
-	STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC
-};
-
-/* Setup DMA to transfer bootblock. */
-static void bootblock_transfer(void)
-{
-	static int transfer_try;
-
-	dma_chan_t *txdma = dma_get_channel(STM32_DMAC_SPI_EMMC_TX);
-
-	dma_prepare_tx(&dma_tx_option, sizeof(bootblock_raw_data),
-		       bootblock_raw_data);
-	dma_go(txdma);
-
-	CPRINTS("transfer %d", ++transfer_try);
-}
-
-/* Abort an ongoing transfer. */
-static void bootblock_stop(void)
-{
-	const uint32_t timeout = 1 * MSEC;
-	uint32_t start;
-
-	dma_disable(STM32_DMAC_SPI_EMMC_TX);
-
-	/*
-	 * Wait for SPI FIFO to become empty.
-	 * We timeout after 1 ms in case the bus is not clocked anymore.
-	 */
-	start = __hw_clock_source_read();
-	while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL &&
-			__hw_clock_source_read() - start < timeout)
-		;
-
-	/* Then flush SPI FIFO, and make sure DAT line stays idle (high). */
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-}
-
-static enum emmc_cmd emmc_parse_command(int index)
-{
-	int32_t shift0;
-	uint32_t data[3];
-
-	if (in_msg[index] == 0xffffffff)
-		return EMMC_ERROR;
-
-	data[0] = htobe32(in_msg[index]);
-	index = RX_BUF_NEXT_32(index);
-	data[1] = htobe32(in_msg[index]);
-	index = RX_BUF_NEXT_32(index);
-	data[2] = htobe32(in_msg[index]);
-
-	/* Figure out alignment (cmd starts with 01) */
-
-	/* Number of leading ones. */
-	shift0 = __builtin_clz(~data[0]);
-
-	data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-	data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
-
-	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
-		/* 400000000095 GO_IDLE_STATE */
-		CPRINTS("goIdle");
-		return EMMC_IDLE;
-	}
-
-	if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) {
-		/* 40f0f0f0f0fd GO_PRE_IDLE_STATE */
-		CPRINTS("goPreIdle");
-		return EMMC_PRE_IDLE;
-	}
-
-	if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) {
-		/* 40fffffffae5 BOOT_INITIATION */
-		CPRINTS("bootInit");
-		return EMMC_BOOT;
-	}
-
-	CPRINTS("eMMC error");
-	return EMMC_ERROR;
-}
-
-
-/*
- * Wake the EMMC task when there is a falling edge on the CMD line, so that we
- * can capture the command.
- */
-void emmc_cmd_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_EMMC);
-	CPRINTF("i");
-}
-
-static void emmc_init_spi(void)
-{
-#if EMMC_SPI_PORT == 1
-	/* Reset SPI */
-	STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1;
-	STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1;
-
-	/* Enable clocks to SPI module */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-#elif EMMC_SPI_PORT == 2
-#ifdef CHIP_FAMILY_STM32L4
-	/* Reset SPI */
-	STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2;
-
-	/* Enable clocks to SPI module */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
-#else
-	/* Reset SPI */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Enable clocks to SPI module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-#endif
-#else
-#error "Please define EMMC_SPI_PORT in board.h."
-#endif
-	clock_wait_bus_cycles(BUS_APB, 1);
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-
-	STM32_SPI_EMMC_REGS->cr2 =
-		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8) |
-		STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN;
-
-	/* Manual CS, disable. */
-	STM32_SPI_EMMC_REGS->cr1 = STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI;
-
-	/* Flush SPI TX FIFO, and make sure DAT line stays idle (high). */
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-	STM32_SPI_EMMC_REGS->dr = 0xff;
-
-	/* Enable the SPI peripheral */
-	STM32_SPI_EMMC_REGS->cr1 |= STM32_SPI_CR1_SPE;
-}
-DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI);
-
-static void emmc_check_status(void);
-DECLARE_DEFERRED(emmc_check_status);
-
-static void emmc_enable_spi(void)
-{
-	if (emmc_enabled)
-		return;
-
-	disable_sleep(SLEEP_MASK_EMMC);
-
-	/* Start receiving in circular buffer in_msg. */
-	dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);
-	/* Enable internal chip select. */
-	STM32_SPI_EMMC_REGS->cr1 &= ~STM32_SPI_CR1_SSI;
-	/*
-	 * EMMC_CMD and SPI1_NSS share EXTI15, make sure GPIO_EMMC_CMD is
-	 * selected.
-	 */
-	gpio_disable_interrupt(GPIO_SPI1_NSS);
-	gpio_enable_interrupt(GPIO_EMMC_CMD);
-
-	emmc_enabled = 1;
-	CPRINTS("emmc enabled");
-
-	boot_deadline.val = get_time().val + BOOT_TIMEOUT;
-
-	/* Check if AP has booted periodically. */
-	hook_call_deferred(&emmc_check_status_data, EMMC_STATUS_CHECK_PERIOD);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST);
-
-static void emmc_disable_spi(void)
-{
-	if (!emmc_enabled)
-		return;
-
-	/* Cancel check hook. */
-	hook_call_deferred(&emmc_check_status_data, -1);
-
-	gpio_disable_interrupt(GPIO_EMMC_CMD);
-	/*
-	 * EMMC_CMD and SPI1_NSS share EXTI15, so re-enable interrupt on
-	 * SPI1_NSS to reconfigure the interrupt selection.
-	 */
-	gpio_enable_interrupt(GPIO_SPI1_NSS);
-	/* Disable TX DMA. */
-	dma_disable(STM32_DMAC_SPI_EMMC_TX);
-	/* Disable internal chip select. */
-	STM32_SPI_EMMC_REGS->cr1 |= STM32_SPI_CR1_SSI;
-	/* Disable RX DMA. */
-	dma_disable(STM32_DMAC_SPI_EMMC_RX);
-
-	/* Blank out buffer to make sure we do not look at old data. */
-	memset(in_msg, 0xff, sizeof(in_msg));
-
-	enable_sleep(SLEEP_MASK_EMMC);
-
-	emmc_enabled = 0;
-	CPRINTS("emmc disabled");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, emmc_disable_spi, HOOK_PRIO_FIRST);
-
-static void emmc_check_status(void)
-{
-	/* Bootblock switch disabled, switch off emulation */
-	if (gpio_get_level(GPIO_BOOTBLOCK_EN_L) == 1) {
-		emmc_disable_spi();
-		return;
-	}
-
-	if (timestamp_expired(boot_deadline, NULL)) {
-		CPRINTS("emmc: AP failed to boot.");
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
-		return;
-	}
-
-	/* Check if AP has booted again, next time. */
-	hook_call_deferred(&emmc_check_status_data, EMMC_STATUS_CHECK_PERIOD);
-}
-
-void emmc_task(void *u)
-{
-	int dma_pos, i;
-	dma_chan_t *rxdma;
-	enum emmc_cmd cmd;
-	/* Are we currently transmitting data? */
-	int tx = 0;
-
-	rxdma = dma_get_channel(STM32_DMAC_SPI_EMMC_RX);
-
-	while (1) {
-		/* Wait for a command */
-		task_wait_event(-1);
-
-		dma_pos = dma_bytes_done(rxdma, sizeof(in_msg)) / 4;
-		i = RX_BUF_PREV_32(dma_pos);
-
-		/*
-		 * By now, bus should be idle again (it takes <10us to transmit
-		 * a command, less than is needed to process interrupt and wake
-		 * this task).
-		 */
-		if (in_msg[i] != 0xffffffff) {
-			CPRINTF("?");
-			/* TODO(b:110907438): We should probably just retry. */
-			continue;
-		}
-
-		/*
-		 * Find a command, looking from the end of the buffer to make
-		 * it faster.
-		 */
-		while (i != dma_pos && in_msg[i] == 0xffffffff)
-			i = RX_BUF_PREV_32(i);
-
-		/*
-		 * We missed the command? That should not happen if we process
-		 * the buffer quickly enough (and the interrupt was real).
-		 */
-		if (i == dma_pos) {
-			CPRINTF("!");
-			continue;
-		}
-
-		/*
-		 * We found the end of the command, now find the beginning
-		 * (commands are 6-byte long so the starting point is either 2
-		 * or 1 word before the end of the command).
-		 */
-		i = RX_BUF_DEC_32(i, 2);
-		if (in_msg[i] == 0xffffffff)
-			i = RX_BUF_NEXT_32(i);
-
-		cmd = emmc_parse_command(i);
-
-		if (!tx) {
-			/*
-			 * When not transferring, host will send GO_IDLE_STATE,
-			 * GO_PRE_IDLE_STATE, then BOOT_INITIATION commands. But
-			 * all we really care about is the BOOT_INITIATION
-			 * command: start the transfer.
-			 */
-			if (cmd == EMMC_BOOT) {
-				tx = 1;
-				bootblock_transfer();
-			}
-		} else {
-			/*
-			 * Host sends GO_IDLE_STATE to abort the transfer (e.g.
-			 * when an incorrect number of lanes is used) and when
-			 * the transfer is complete.
-			 * Also react to GO_PRE_IDLE_STATE in case we missed
-			 * GO_IDLE_STATE command.
-			 */
-			if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) {
-				bootblock_stop();
-				tx = 0;
-			}
-		}
-	}
-}
diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c
deleted file mode 100644
index 8c3e63064c..0000000000
--- a/baseboard/kukui/emmc_ite.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "endian.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "intc.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#include "bootblock_data.h"
-
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-enum emmc_cmd {
-	EMMC_ERROR = -1,
-	EMMC_IDLE = 0,
-	EMMC_PRE_IDLE,
-	EMMC_BOOT,
-};
-
-static void emmc_reset_spi_tx(void)
-{
-	/* Reset TX FIFO and count monitor */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* Send idle state (high/0xff) if master clocks in data. */
-	IT83XX_SPI_FCR = 0;
-}
-
-static void emmc_reset_spi_rx(void)
-{
-	/* End Rx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* Reset RX FIFO and count monitor */
-	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
-}
-
-/*
- * Set SPI module work as eMMC Alternative Boot Mode.
- * (CS# pin isn't required, and dropping data until CMD goes low)
- */
-static void emmc_enable_spi(void)
-{
-	/* Set SPI pin mux to eMMC (GPM2:CLK, GPM3:CMD, GPM6:DATA0) */
-	IT83XX_GCTRL_PIN_MUX0 |= BIT(7);
-	/* Enable eMMC Alternative Boot Mode */
-	IT83XX_SPI_EMMCBMR |= IT83XX_SPI_EMMCABM;
-	/* Reset TX and RX FIFO */
-	emmc_reset_spi_tx();
-	emmc_reset_spi_rx();
-	/* Response idle state (high) */
-	IT83XX_SPI_SPISRDR = 0xff;
-	/* FIFO will be overwritten once it's full */
-	IT83XX_SPI_GCR2 = 0;
-	/* Write to clear pending interrupt bits */
-	IT83XX_SPI_ISR = 0xff;
-	IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-	/* Enable RX fifo full interrupt */
-	IT83XX_SPI_IMR = 0xff;
-	IT83XX_SPI_RX_VLISMR |= IT83XX_SPI_RVLIM;
-	IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_FIFO_FULL;
-	/*
-	 * Enable interrupt to detect AP's BOOTBLOCK_EN_L. So EC is able to
-	 * switch SPI module back to communication mode once BOOTBLOCK_EN_L
-	 * goes high (AP Jumped to bootloader).
-	 */
-	gpio_clear_pending_interrupt(GPIO_BOOTBLOCK_EN_L);
-	gpio_enable_interrupt(GPIO_BOOTBLOCK_EN_L);
-
-	disable_sleep(SLEEP_MASK_EMMC);
-	CPRINTS("eMMC emulation enabled");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST);
-
-static void emmc_init_spi(void)
-{
-	/* Enable alternate function */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-}
-DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI + 1);
-
-static void emmc_send_data_over_spi(uint8_t *tx, int tx_size, int rst_tx)
-{
-	int i;
-
-	/* Reset TX FIFO and count monitor */
-	if (rst_tx)
-		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* CPU access TX FIFO1 and FIFO2 */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
-
-	/* Write response data to TX FIFO */
-	for (i = 0; i < tx_size; i += 4)
-		IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(tx + i);
-	/*
-	 * After writing data to TX FIFO is finished, this bit will
-	 * be to indicate the SPI slave controller.
-	 */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
-	/* End CPU access TX FIFO */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* SPI module access TX FIFO */
-	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
-}
-
-static void emmc_bootblock_transfer(void)
-{
-	int tx_size, sent = 0, remaining = sizeof(bootblock_raw_data);
-	uint8_t *raw = (uint8_t *)bootblock_raw_data;
-	const uint32_t timeout_us = 200;
-	uint32_t start;
-
-	/*
-	 * HW will transmit the data of FIFO1 or FIFO2 in turn.
-	 * So when a FIFO is empty, we need to fill the FIFO out
-	 * immediately.
-	 */
-	emmc_send_data_over_spi(&raw[sent], 256, 1);
-	sent += 256;
-
-	while (sent < remaining) {
-		/* Wait for FIFO1 or FIFO2 have been transmitted */
-		start = __hw_clock_source_read();
-		while (!(IT83XX_SPI_TXFSR & BIT(0)) &&
-			(__hw_clock_source_read() - start < timeout_us))
-			;
-		/* Abort an ongoing transfer due to a command is received. */
-		if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL)
-			break;
-		/* fill out next 128 bytes to FIFO1 or FIFO2 */
-		tx_size = (remaining - sent) < 128 ? (remaining - sent) : 128;
-		emmc_send_data_over_spi(&raw[sent], tx_size, 0);
-		sent += tx_size;
-	}
-}
-
-static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0)
-{
-	int32_t shift0;
-	uint32_t data[3];
-
-	data[0] = htobe32(cmd0[index]);
-	data[1] = htobe32(cmd0[index+1]);
-	data[2] = htobe32(cmd0[index+2]);
-
-	if ((data[0] & 0xff000000) != 0x40000000) {
-		/* Figure out alignment (cmd starts with 01) */
-		/* Number of leading ones. */
-		shift0 = __builtin_clz(~data[0]);
-
-		data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-		data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
-	}
-
-	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
-		/* 400000000095 GO_IDLE_STATE */
-		CPRINTS("goIdle");
-		return EMMC_IDLE;
-	}
-
-	if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) {
-		/* 40f0f0f0f0fd GO_PRE_IDLE_STATE */
-		CPRINTS("goPreIdle");
-		return EMMC_PRE_IDLE;
-	}
-
-	if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) {
-		/* 40fffffffae5 BOOT_INITIATION */
-		CPRINTS("bootInit");
-		return EMMC_BOOT;
-	}
-
-	CPRINTS("eMMC error");
-	return EMMC_ERROR;
-}
-
-void spi_emmc_cmd0_isr(uint32_t *cmd0_payload)
-{
-	enum emmc_cmd cmd;
-
-	for (int i = 0; i < 8; i++) {
-		if (cmd0_payload[i] == 0xffffffff)
-			continue;
-
-		cmd = emmc_parse_command(i, &cmd0_payload[i]);
-
-		if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) {
-			/* Abort an ongoing transfer. */
-			emmc_reset_spi_tx();
-			break;
-		}
-
-		if (cmd == EMMC_BOOT) {
-			emmc_bootblock_transfer();
-			break;
-		}
-	}
-}
diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c
deleted file mode 100644
index 28ef005ee8..0000000000
--- a/baseboard/kukui/usb_pd_policy.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_policy.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static int board_get_polarity(int port)
-{
-	/* Krane's aux mux polarity is reversed. Workaround to flip it back. */
-	if (IS_ENABLED(BOARD_KRANE) && board_get_version() == 3)
-		return !polarity_rm_dts(pd_get_polarity(port));
-
-	return polarity_rm_dts(pd_get_polarity(port));
-}
-
-static uint8_t vbus_en;
-
-#define VBUS_EN_SYSJUMP_TAG		0x5645 /* VE */
-#define VBUS_EN_HOOK_VERSION	1
-
-static void vbus_en_preserve_state(void)
-{
-	system_add_jump_tag(VBUS_EN_SYSJUMP_TAG, VBUS_EN_HOOK_VERSION,
-			    sizeof(vbus_en), &vbus_en);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, vbus_en_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void vbus_en_restore_state(void)
-{
-	const uint8_t *prev_vbus_en;
-	int size, version;
-
-	prev_vbus_en = (const uint8_t *)system_get_jump_tag(
-		VBUS_EN_SYSJUMP_TAG, &version, &size);
-
-	if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION &&
-		size == sizeof(*prev_vbus_en)) {
-		memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en));
-	}
-}
-DECLARE_HOOK(HOOK_INIT, vbus_en_restore_state, HOOK_PRIO_DEFAULT);
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	if (IS_ENABLED(BOARD_KUKUI) && board_get_version() <= 1)
-		return charger_is_sourcing_otg_power(port);
-	else
-		return board_vbus_source_enabled(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	if (port != CHARGE_PORT_USB_C)
-		return EC_ERROR_INVAL;
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en = 1;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	if (IS_ENABLED(VARIANT_KUKUI_CHARGER_ISL9238))
-		charge_set_output_current_limit(CHARGER_SOLO, 3300, 5000);
-	else
-		charger_enable_otg_power(CHARGER_SOLO, 1);
-
-	gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-	gpio_set_level(GPIO_EN_PP5000_USBC, 1);
-	if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C))
-		charger_set_current(CHARGER_SOLO, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port != CHARGE_PORT_USB_C)
-		return;
-
-	prev_en = vbus_en;
-	/* Disable VBUS */
-	vbus_en = 0;
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	if (IS_ENABLED(VARIANT_KUKUI_CHARGER_ISL9238))
-		charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
-	else
-		charger_enable_otg_power(CHARGER_SOLO, 0);
-
-	gpio_set_level(GPIO_EN_PP5000_USBC, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* always allow vconn swap, since PSYS sources VCONN */
-	return 1;
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__overridable int board_has_virtual_mux(void)
-{
-	return IS_ENABLED(CONFIG_USB_MUX_VIRTUAL);
-}
-
-static void board_usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
-{
-	usb_mux_set(port, mux_mode, usb_mode, polarity);
-
-	if (!board_has_virtual_mux())
-		/* b:149181702: Inform AP of DP status */
-		host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-__override void svdm_safe_dp_mode(int port)
-{
-	/* make DP interface safe until configure */
-	dp_flags[port] = 0;
-	dp_status[port] = 0;
-	board_usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-			  board_get_polarity(port));
-}
-
-__override int svdm_enter_dp_mode(int port, uint32_t mode_caps)
-{
-	/* Kukui/Krane doesn't support superspeed lanes. */
-	const uint32_t support_pin_mode = board_has_virtual_mux() ?
-		(MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL;
-
-	/**
-	 * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane)
-	 * capable
-	 */
-	if ((mode_caps & MODE_DP_SNK) &&
-	    (mode_caps & ((support_pin_mode << MODE_DP_DFP_PIN_SHIFT) |
-			  (support_pin_mode << MODE_DP_UFP_PIN_SHIFT)))) {
-		svdm_safe_dp_mode(port);
-		return 0;
-	}
-
-	CPRINTS("ERR:DP mode SNK or C&E missing! 0x%x", mode_caps);
-	return -1;
-}
-
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	int status = dp_status[port];
-	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-	int pin_mode;
-
-	/* Kukui doesn't support multi-function mode, mask it out. */
-	if (board_has_virtual_mux())
-		status &= ~PD_VDO_DPSTS_MF_MASK;
-
-	pin_mode = pd_dfp_dp_get_pin_mode(port, status);
-
-	if (!pin_mode)
-		return 0;
-
-	if (board_has_virtual_mux())
-		board_usb_mux_set(port, USB_PD_MUX_DP_ENABLED,
-				  USB_SWITCH_CONNECT, board_get_polarity(port));
-	else
-		board_usb_mux_set(
-			port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED,
-			USB_SWITCH_CONNECT, board_get_polarity(port));
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	gpio_set_level(GPIO_USB_C0_HPD_OD, 1);
-#ifdef VARIANT_KUKUI_DP_MUX_GPIO
-	board_set_dp_mux_control(1, board_get_polarity(port));
-#endif
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int cur_lvl = gpio_get_level(GPIO_USB_C0_HPD_OD);
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		gpio_set_level(GPIO_USB_C0_HPD_OD, 1);
-
-#ifdef VARIANT_KUKUI_DP_MUX_GPIO
-		board_set_dp_mux_control(1, board_get_polarity(port));
-#endif
-
-		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	} else if (irq & !lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	} else {
-		gpio_set_level(GPIO_USB_C0_HPD_OD, lvl);
-#ifdef VARIANT_KUKUI_DP_MUX_GPIO
-		board_set_dp_mux_control(lvl, board_get_polarity(port));
-#endif
-		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	}
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
-#ifdef VARIANT_KUKUI_DP_MUX_GPIO
-	board_set_dp_mux_control(0, 0);
-#endif
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/kukui/usb_pd_policy.h b/baseboard/kukui/usb_pd_policy.h
deleted file mode 100644
index 78e0213f53..0000000000
--- a/baseboard/kukui/usb_pd_policy.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BASEBOARD_USB_PD_POLICY_H
-#define __CROS_EC_BASEBOARD_USB_PD_POLICY_H
-
-#include "common.h"
-
-__override_proto int board_has_virtual_mux(void);
-
-#endif /* __CROS_EC_BASEBOARD_USB_PD_POLICY_H */
diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c
deleted file mode 100644
index a34a08f1fe..0000000000
--- a/baseboard/mtscp-rv32i/baseboard.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* MT SCP RV32i configuration */
-
-#include "cache.h"
-#include "csr.h"
-#include "registers.h"
-
-#define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1)))
-
-struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = {
-	/* SRAM (for most code, data) */
-	{0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R},
-	/* SRAM (for IPI shared buffer) */
-	{SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R},
-	/* For AP domain */
-#ifdef CHIP_VARIANT_MT8195
-	{0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P},
-#else
-	{0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R},
-#endif
-	/* For SCP sys */
-	{0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R},
-#ifdef CHIP_VARIANT_MT8195
-	{0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R},
-#else
-	{0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R},
-#endif
-};
-
-#include "gpio_list.h"
diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h
deleted file mode 100644
index a8f3b522a0..0000000000
--- a/baseboard/mtscp-rv32i/baseboard.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MT SCP RV32i board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI)))
-
-#define CONFIG_FLASH_SIZE_BYTES CONFIG_RAM_BASE
-#define CONFIG_LTO
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_UART_CONSOLE 0
-
-/* IPI configs */
-#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(SCP_FW_END -                                                         \
-	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
-#define CONFIG_IPI
-#define CONFIG_RPMSG_NAME_SERVICE
-
-#define SCP_IPI_INIT 0
-#define SCP_IPI_VDEC_H264 1
-#define SCP_IPI_VDEC_VP8 2
-#define SCP_IPI_VDEC_VP9 3
-#define SCP_IPI_VENC_H264 4
-#define SCP_IPI_VENC_VP8 5
-#define SCP_IPI_MDP_INIT 6
-#define SCP_IPI_MDP_DEINIT 7
-#define SCP_IPI_MDP_FRAME 8
-#define SCP_IPI_DIP 9
-#define SCP_IPI_ISP_CMD 10
-#define SCP_IPI_ISP_FRAME 11
-#define SCP_IPI_FD_CMD 12
-#define SCP_IPI_HOST_COMMAND 13
-#define SCP_IPI_VDEC_LAT 14
-#define SCP_IPI_VDEC_CORE 15
-#define SCP_IPI_COUNT 16
-
-#define IPI_COUNT SCP_IPI_COUNT
-
-#define SCP_IPI_NS_SERVICE 0xFF
-
-/* Access DRAM through cached access */
-#define CONFIG_DRAM_BASE 0x10000000
-/* Shared memory address in AP physical address space. */
-#define CONFIG_DRAM_BASE_LOAD 0x50000000
-#define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
-
-/* MPU settings */
-#define NR_MPU_ENTRIES 16
-
-#ifndef __ASSEMBLER__
-#include "gpio_signal.h"
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/mtscp-rv32i/build.mk b/baseboard/mtscp-rv32i/build.mk
deleted file mode 100644
index 420a3a4e08..0000000000
--- a/baseboard/mtscp-rv32i/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-baseboard-y+=baseboard.o
-
-baseboard-$(HAS_TASK_VDEC_SERVICE)+=vdec.o
-baseboard-$(HAS_TASK_VENC_SERVICE)+=venc.o
-baseboard-$(HAS_TASK_MDP_SERVICE)+=mdp.o
diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c
deleted file mode 100644
index b0756a797a..0000000000
--- a/baseboard/mtscp-rv32i/mdp.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "ipi_chip.h"
-#include "mdp.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static void event_mdp_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_MDP_SERVICE);
-}
-static struct consumer const event_mdp_consumer;
-static struct queue const event_mdp_queue = QUEUE_DIRECT(4,
-	struct mdp_msg_service, null_producer, event_mdp_consumer);
-static struct consumer const event_mdp_consumer = {
-	.queue = &event_mdp_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_mdp_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT_SCP
-void mdp_common_init(void) {}
-void mdp_ipi_task_handler(void *pvParameters) {}
-#endif
-
-static void mdp_ipi_handler(int id, void *data, unsigned int len)
-{
-	struct mdp_msg_service rsv_msg;
-
-	if (!len) {
-		CPRINTS("len is zero.");
-		return;
-	}
-
-	rsv_msg.id = id;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_mdp_queue, &rsv_msg))
-		CPRINTS("Could not send mdp id: %d to the queue.", id);
-}
-DECLARE_IPI(SCP_IPI_MDP_INIT, mdp_ipi_handler, 0);
-DECLARE_IPI(SCP_IPI_MDP_FRAME, mdp_ipi_handler, 0);
-DECLARE_IPI(SCP_IPI_MDP_DEINIT, mdp_ipi_handler, 0);
-
-void mdp_service_task(void *u)
-{
-	struct mdp_msg_service rsv_msg;
-	size_t size;
-
-	mdp_common_init();
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq();
-		size = queue_remove_unit(&event_mdp_queue, &rsv_msg);
-		ipi_enable_irq();
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			mdp_ipi_task_handler(&rsv_msg);
-	}
-}
diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h
deleted file mode 100644
index eea3ffb289..0000000000
--- a/baseboard/mtscp-rv32i/mdp.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_MDP_H
-#define __CROS_EC_SCP_MDP_H
-
-struct mdp_msg_service {
-	int id;
-	unsigned char msg[20];
-};
-BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void mdp_common_init(void);
-void mdp_ipi_task_handler(void *pvParameters);
-
-#endif  /* __CROS_EC_SCP_MDP_H */
diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c
deleted file mode 100644
index c3f5f5a9cf..0000000000
--- a/baseboard/mtscp-rv32i/vdec.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "vdec.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static void event_vdec_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_VDEC_SERVICE);
-}
-static struct consumer const event_vdec_consumer;
-static struct queue const event_vdec_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_consumer);
-static struct consumer const event_vdec_consumer = {
-	.queue = &event_vdec_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_vdec_written,
-	}),
-};
-
-static void event_vdec_core_written(struct consumer const *consumer,
-				    size_t count)
-{
-	task_wake(TASK_ID_VDEC_CORE_SERVICE);
-}
-static struct consumer const event_vdec_core_consumer;
-static struct queue const event_vdec_core_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_core_consumer);
-static struct consumer const event_vdec_core_consumer = {
-	.queue = &event_vdec_core_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_vdec_core_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT_SCP
-void vdec_msg_handler(void *data) {}
-void vdec_core_msg_handler(void *data) {}
-#endif
-
-static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct vdec_msg rsv_msg;
-
-	if (!len) {
-		CPRINTS("len is zero.");
-		return;
-	}
-
-	rsv_msg.type = VDEC_LAT;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_vdec_queue, &rsv_msg))
-		CPRINTS("Could not send vdec %d to the queue.", rsv_msg.type);
-}
-DECLARE_IPI(SCP_IPI_VDEC_LAT, vdec_h264_ipi_handler, 0);
-
-static void vdec_h264_ipi_core_handler(int id, void *data, uint32_t len)
-{
-	struct vdec_msg rsv_msg;
-
-	if (!len) {
-		CPRINTS("len is zero.");
-		return;
-	}
-
-	rsv_msg.type = VDEC_CORE;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_vdec_core_queue, &rsv_msg))
-		CPRINTS("Could not send vdec %d to core queue.", rsv_msg.type);
-}
-DECLARE_IPI(SCP_IPI_VDEC_CORE, vdec_h264_ipi_core_handler, 0);
-
-void vdec_service_task(void *u)
-{
-	struct vdec_msg rsv_msg;
-	size_t size;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq();
-		size = queue_remove_unit(&event_vdec_queue, &rsv_msg);
-		ipi_enable_irq();
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			vdec_msg_handler(rsv_msg.msg);
-	}
-}
-
-void vdec_core_service_task(void *u)
-{
-	struct vdec_msg rsv_msg;
-	size_t size;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq();
-		size = queue_remove_unit(&event_vdec_core_queue, &rsv_msg);
-		ipi_enable_irq();
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			vdec_core_msg_handler(rsv_msg.msg);
-	}
-}
diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h
deleted file mode 100644
index cdc16ba9e0..0000000000
--- a/baseboard/mtscp-rv32i/vdec.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_VDEC_H
-#define __CROS_EC_SCP_VDEC_H
-
-#include "compile_time_macros.h"
-
-enum vdec_type {
-	VDEC_LAT,
-	VDEC_CORE,
-	VDEC_MAX,
-};
-
-struct vdec_msg {
-	enum vdec_type type;
-	unsigned char msg[48];
-};
-BUILD_ASSERT(member_size(struct vdec_msg, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void vdec_core_msg_handler(void *msg);
-void vdec_msg_handler(void *msg);
-
-#endif /* __CROS_EC_SCP_VDEC_H */
diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c
deleted file mode 100644
index 09bb0cbd39..0000000000
--- a/baseboard/mtscp-rv32i/venc.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "venc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static void event_venc_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_VENC_SERVICE);
-}
-static struct consumer const event_venc_consumer;
-static struct queue const event_venc_queue = QUEUE_DIRECT(8,
-	struct venc_msg, null_producer, event_venc_consumer);
-static struct consumer const event_venc_consumer = {
-	.queue = &event_venc_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_venc_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT_SCP
-void venc_h264_msg_handler(void *data) {}
-#endif
-
-static void venc_h264_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct venc_msg rsv_msg;
-
-	if (!len) {
-		CPRINTS("len is zero.");
-		return;
-	}
-
-	rsv_msg.type = VENC_H264;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_venc_queue, &rsv_msg))
-		CPRINTS("Could not send venc %d to the queue.", rsv_msg.type);
-}
-DECLARE_IPI(SCP_IPI_VENC_H264, venc_h264_ipi_handler, 0);
-
-void venc_service_task(void *u)
-{
-	struct venc_msg rsv_msg;
-	size_t size;
-
-	typedef void (*venc_msg_handler)(void *msg);
-	static venc_msg_handler mtk_venc_msg_handle[VENC_MAX] = {
-		[VENC_H264] = venc_h264_msg_handler,
-	};
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq();
-		size = queue_remove_unit(&event_venc_queue, &rsv_msg);
-		ipi_enable_irq();
-
-		if (!size)
-			task_wait_event(-1);
-		else if (mtk_venc_msg_handle[rsv_msg.type])
-			mtk_venc_msg_handle[rsv_msg.type](rsv_msg.msg);
-		else
-			CPRINTS("venc handler %d not exists.", rsv_msg.type);
-	}
-}
diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h
deleted file mode 100644
index 47454c4507..0000000000
--- a/baseboard/mtscp-rv32i/venc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_VENC_H
-#define __CROS_EC_SCP_VENC_H
-
-#include "compile_time_macros.h"
-
-enum venc_type {
-	VENC_H264,
-	VENC_MAX,
-};
-
-struct venc_msg {
-	enum venc_type type;
-	unsigned char msg[288];
-};
-BUILD_ASSERT(member_size(struct venc_msg, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void venc_h264_msg_handler(void *data);
-
-#endif /* __CROS_EC_SCP_VENC_H */
diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c
deleted file mode 100644
index 15e46f006e..0000000000
--- a/baseboard/nucleo-f412zg/base-board.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-
-__overridable void button_event(enum gpio_signal signal)
-{
-}
diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h
deleted file mode 100644
index d41cdfd207..0000000000
--- a/baseboard/nucleo-f412zg/base-board.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nucleo-F412ZG baseboard configuration */
-
-#ifndef __CROS_EC_BASE_BOARD_H
-#define __CROS_EC_BASE_BOARD_H
-
-/*-------------------------------------------------------------------------*
- * Flash layout:
- *
- * +++++++++++++
- * |    RO     |
- * | ......... |
- * |  Rollback | (two sectors)
- * +-----------+
- * |    RW     |
- * |           |
- * |           |
- * |           |
- * |           |
- * +++++++++++++
- *
- * We adjust the following macros to accommodate a for a rollback, RO,
- * and RW region of different sizes.
- *
- *-------------------------------------------------------------------------*/
-
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-#define CONFIG_SHAREDLIB_SIZE   0
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
-
-/* EC rollback protection block */
-#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * We want to prevent flash readout, and use it as indicator of protection
- * status.
- */
-#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-
-/*-------------------------------------------------------------------------*
- * UART Console Setup
- *-------------------------------------------------------------------------*/
-
-/* The UART console is on USART3 */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 3
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-#define CONFIG_UART_TX_REQ_CH 4
-#define CONFIG_UART_RX_REQ_CH 4
-/* We don't currently use DMA. */
-#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/*-------------------------------------------------------------------------*
- * Console Commands
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IDLE_STATS
-
-/*-------------------------------------------------------------------------*
- * Rollback Block
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_ROLLBACK
-#define CONFIG_MPU
-#define CONFIG_ROLLBACK_MPU_PROTECT
-
-/*
- * We do not use any "locally" generated entropy: this is normally used
- * to add local entropy when the main source of entropy is remote.
- */
-#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-#ifdef SECTION_IS_RW
-	#undef CONFIG_ROLLBACK_UPDATE
-#endif
-
-/*-------------------------------------------------------------------------*
- * RW Signature Verification
- *-------------------------------------------------------------------------*/
-
-#ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-	#define CONFIG_RSA
-	#define CONFIG_RWSIG
-#endif /* SECTION_IS_RO */
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_RWSIG_TYPE_RWSIG
-
-/*-------------------------------------------------------------------------*
- * Watchdog
- *-------------------------------------------------------------------------*/
-
-/*
- * RW does slow compute, RO does slow flash erase.
- */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 10000
-#define CONFIG_WATCHDOG_HELP
-
-/*-------------------------------------------------------------------------*
- * Disable Features
- *-------------------------------------------------------------------------*/
-
-#undef CONFIG_ADC
-#undef CONFIG_HIBERNATE
-#undef CONFIG_I2C
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/*-------------------------------------------------------------------------*
- * Other
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
-#define CONFIG_FPU
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
-#define CONFIG_RNG
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-	#define CONFIG_SPI
-#endif
-
-#ifndef __ASSEMBLER__
-	/* Timer selection */
-	#define TIM_CLOCK32 2
-	#define TIM_WATCHDOG 16
-	#include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc
deleted file mode 100644
index 4ebd99f91f..0000000000
--- a/baseboard/nucleo-f412zg/base-gpio.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Note that these pins map to the Nucleo-F412ZG.
- */
-
-/* Inputs and Interrupts */
-GPIO_INT(SPI1_NSS,        PIN(A, 4),  GPIO_INPUT, spi_event)
-GPIO_INT(BTN1,            PIN(C, 13), GPIO_INT_BOTH, button_event)
-GPIO(WP,                  PIN(B, 8),  GPIO_INPUT) /* Not same as bloonchipper */
-
-/* Outputs */
-GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(LED1,                PIN(B, 0),  GPIO_OUT_LOW) /* Green */
-GPIO(LED2,                PIN(B, 7),  GPIO_OUT_LOW) /* Blue */
-GPIO(LED3,                PIN(B, 14), GPIO_OUT_LOW) /* Red */
-
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART3: PD8/PD9 (TX/RX) */
-ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk
deleted file mode 100644
index 1456331fec..0000000000
--- a/baseboard/nucleo-f412zg/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Nucleo-F412ZG baseboard specific files build
-#
-
-# the IC is STmicro STM32F412
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f412
-
-baseboard-y=base-board.o
diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg
deleted file mode 100644
index 3333d1163a..0000000000
--- a/baseboard/nucleo-f412zg/openocd-flash.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_f4.cfg]
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset halt
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset
-shutdown
diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg
deleted file mode 100644
index 589d4400f4..0000000000
--- a/baseboard/nucleo-f412zg/openocd.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_f4.cfg]
-
-# Enabled EC task context support
-# This is supported by the upstream OpenOCD
-$_TARGETNAME configure -rtos Chromium-EC
diff --git a/baseboard/nucleo-h743zi/base-board.c b/baseboard/nucleo-h743zi/base-board.c
deleted file mode 100644
index 15e46f006e..0000000000
--- a/baseboard/nucleo-h743zi/base-board.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-
-__overridable void button_event(enum gpio_signal signal)
-{
-}
diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h
deleted file mode 100644
index df5e4bfa8c..0000000000
--- a/baseboard/nucleo-h743zi/base-board.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nucleo-H743ZI baseboard configuration */
-
-#ifndef __CROS_EC_BASE_BOARD_H
-#define __CROS_EC_BASE_BOARD_H
-
-/*
- * Flash layout:
- *
- * +++++++++++++
- * |    RO     | Bank 1
- * |           |
- * |           |
- * | ......... |
- * |  Rollback | (last two sectors)
- * +-----------+
- * |    RW     | Bank 2
- * |           |
- * |           |
- * |           |
- * |           |
- * +++++++++++++
- *
- * We adjust the following macros to accommodate a rollback region
- * and RO/RW regions of different sizes.
- */
-
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-/*
- * EC rollback protection block
- *
- * We need 2 independently erasable blocks, at a minimum.
- */
-#define CONFIG_ROLLBACK_SIZE   (2 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_ROLLBACK_OFF    ((CONFIG_FLASH_SIZE_BYTES / 2) - \
-				CONFIG_ROLLBACK_SIZE)
-
-#define CONFIG_RO_MEM_OFF      0
-#define CONFIG_RO_SIZE         CONFIG_ROLLBACK_OFF
-#define CONFIG_RW_MEM_OFF      (CONFIG_FLASH_SIZE_BYTES / 2)
-#define CONFIG_RW_SIZE         (CONFIG_FLASH_SIZE_BYTES / 2)
-
-#define CONFIG_RO_STORAGE_OFF  0
-#define CONFIG_RW_STORAGE_OFF  0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF   CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE  CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF    CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE   CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF             CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE            CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* Disabled features */
-
-#undef CONFIG_ADC
-#undef CONFIG_HIBERNATE
-#undef CONFIG_I2C
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* Enabled features */
-
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_FPU
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
-#define CONFIG_RNG
-#define CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#undef CONFIG_SHAREDLIB_SIZE
-#define CONFIG_SHAREDLIB_SIZE   0
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-#	define CONFIG_SPI
-#endif
-
-/*
- * We want to prevent flash readout, and use it as indicator of protection
- * status.
- */
-#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-
-/*
- * RW does slow compute, RO does slow flash erase.
- */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 10000
-
-/* Setup UART console */
-
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 3 /* The UART console is on USART3 */
-#define CONFIG_UART_TX_DMA
-#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Console commands */
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IDLE_STATS
-
-#ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-#	define CONFIG_RSA
-#	define CONFIG_RWSIG
-#endif  /* SECTION_IS_RO */
-
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-
-/*
- * We do not use any "locally" generated entropy: this is normally used
- * to add local entropy when the main source of entropy is remote.
- */
-#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-#ifdef SECTION_IS_RW
-#	undef CONFIG_ROLLBACK_UPDATE
-#endif
-/*
- * Add rollback protection
- */
-#define CONFIG_ROLLBACK
-#define CONFIG_ROLLBACK_MPU_PROTECT
-
-#ifndef __ASSEMBLER__
-	/* Timer selection */
-#	define TIM_CLOCK32 2
-#	define TIM_WATCHDOG 16
-#	include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-h743zi/base-ec.tasklist b/baseboard/nucleo-h743zi/base-ec.tasklist
deleted file mode 100644
index fae8952113..0000000000
--- a/baseboard/nucleo-h743zi/base-ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define BASEBOARD_CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/baseboard/nucleo-h743zi/base-gpio.inc b/baseboard/nucleo-h743zi/base-gpio.inc
deleted file mode 100644
index ef224cbaf1..0000000000
--- a/baseboard/nucleo-h743zi/base-gpio.inc
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Note that these pins map to the Nucleo-H743ZI V2 and are only slightly
- * compatible with the original version.
- *
- * The V2 is denoted by "Nucleo-H743ZI2" vs. "Nucleo-H743ZI".
- */
-
-/* Inputs ands Interrupts */
-GPIO_INT(SPI1_NSS,        PIN(A, 4),  GPIO_INPUT, spi_event)
-GPIO_INT(BTN1,            PIN(C, 13), GPIO_INT_BOTH, button_event)
-GPIO(WP,                  PIN(B, 7),  GPIO_INPUT)
-
-/* Outputs */
-GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(LED1,                PIN(B, 0),  GPIO_OUT_LOW) /* Green */
-GPIO(LED2,                PIN(E, 1),  GPIO_OUT_LOW) /* Yellow */
-GPIO(LED3,                PIN(B, 14), GPIO_OUT_LOW) /* Red */
-
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART3: PD8/PD9 */
-ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* SPI1 slave from the AP: PA4/5/6/7 */
-ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk
deleted file mode 100644
index e9f9ae3faa..0000000000
--- a/baseboard/nucleo-h743zi/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Nucleo-H743ZI baseboard specific files build
-#
-
-# the IC is STmicro STM32H743
-CHIP:=stm32
-CHIP_FAMILY:=stm32h7
-CHIP_VARIANT:=stm32h7x3
-
-baseboard-y=base-board.o
\ No newline at end of file
diff --git a/baseboard/nucleo-h743zi/openocd-flash.cfg b/baseboard/nucleo-h743zi/openocd-flash.cfg
deleted file mode 100644
index 4517266d7b..0000000000
--- a/baseboard/nucleo-h743zi/openocd-flash.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_h743zi.cfg]
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset halt
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset
-shutdown
diff --git a/baseboard/nucleo-h743zi/openocd.cfg b/baseboard/nucleo-h743zi/openocd.cfg
deleted file mode 100644
index 528e8d6cab..0000000000
--- a/baseboard/nucleo-h743zi/openocd.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_h743zi.cfg]
-
-# Enabled EC task context support
-# This is supported by the upstream OpenOCD
-$_TARGETNAME configure -rtos Chromium-EC
diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c
deleted file mode 100644
index 4f338ab131..0000000000
--- a/baseboard/octopus/baseboard.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Octopus family-specific configuration */
-
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/bc12/max14637.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "gpio.h"
-#include "hooks.h"
-#ifdef VARIANT_OCTOPUS_EC_ITE8320
-#include "intc.h"
-#endif
-#include "keyboard_scan.h"
-#include "power.h"
-#include "system.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-#ifndef CONFIG_KEYBOARD_KEYPAD
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-#else
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */
-#endif
-	},
-};
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_5V,
-	GPIO_EN_USB_A1_5V,
-};
-
-/******************************************************************************/
-/* BC 1.2 chip Configuration */
-const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-};
-
-/******************************************************************************/
-/* Charger Chip Configuration */
-#ifdef VARIANT_OCTOPUS_CHARGER_ISL9238
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-#endif
-
-/******************************************************************************/
-/* Chipset callbacks/hooks */
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-	/*
-	 * Since we disable eSPI module for IT8320 part when system goes into G3
-	 * state, so we need to enable it at system startup.
-	 */
-	espi_enable_pad(1);
-#endif
-
-	/* Enable 5.0V and 3.3V rails, and wait for Power Good */
-	power_5v_enable(task_get_current(), 1);
-
-	gpio_set_level(GPIO_EN_PP3300, 1);
-	while (!gpio_get_level(GPIO_PP5000_PG) ||
-	       !gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/* Enable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 1);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void baseboard_chipset_startup(void)
-{
-	/* Enable Trackpad in S3+, so it can be an AP wake source. */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void baseboard_chipset_resume(void)
-{
-	/*
-	 * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and
-	 * LID_OPEN connection in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	/* Enable the keyboard backlight */
-	gpio_set_level(GPIO_KB_BL_PWR_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void baseboard_chipset_suspend(void)
-{
-	/*
-	 * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and
-	 * LID_OPEN connection in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	/* Disable the keyboard backlight */
-	gpio_set_level(GPIO_KB_BL_PWR_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void baseboard_chipset_shutdown(void)
-{
-	/* Disable Trackpad in S5- to save power; not a low power wake source */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called by APL power state machine when transitioning to G3. */
-void chipset_do_shutdown(void)
-{
-#ifdef VARIANT_OCTOPUS_EC_ITE8320
-	/*
-	 * We want the processor to be reset before dropping the PP3300_A rail
-	 * below, otherwise the PP3300_LDO and PP3300_EC rails can be overloaded
-	 */
-	if (gpio_get_level(GPIO_PCH_SLP_S4_L)) {
-		/* assert RSMRST to PCH */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-		/* Wait SLP_S4 goes low; would rather watchdog than continue */
-		while (gpio_get_level(GPIO_PCH_SLP_S4_L))
-			;
-	}
-#endif
-
-	/* Disable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 0);
-
-	/* Disable 5.0V and 3.3V rails, and wait until they power down. */
-	power_5v_enable(task_get_current(), 0);
-
-	/*
-	 * Shutdown the 3.3V rail and wait for it to go down. We cannot wait
-	 * for the 5V rail since other tasks may be using it.
-	 */
-	gpio_set_level(GPIO_EN_PP3300, 0);
-	while (gpio_get_level(GPIO_PP3300_PG))
-		;
-
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-	/*
-	 * The IT8320 part doesn't go into its lowest power state in idle task
-	 * when the eSPI module is on and CS# is asserted, so we need to
-	 * manually disable it.
-	 */
-	espi_enable_pad(0);
-#endif
-}
-
-int board_is_i2c_port_powered(int port)
-{
-	if (port != I2C_PORT_SENSOR)
-		return 1;
-
-	/* Sensor rails are off in S5/G3 */
-	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
-}
-
-/******************************************************************************/
-/* Power Delivery and charing functions */
-
-#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-enum adc_channel board_get_vbus_adc(int port)
-{
-	if (port == 0)
-		return  ADC_VBUS_C0;
-	if (port == 1)
-		return  ADC_VBUS_C1;
-	CPRINTSUSB("Unknown vbus adc port id: %d", port);
-	return ADC_VBUS_C0;
-}
-#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
-
-void baseboard_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < board_get_usb_pd_port_count(); ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-/* Called after the cbi_init (via +2) */
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; (i < ppc_cnt) &&
-		    (i < board_get_usb_pd_port_count()); i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; (i < ppc_cnt) &&
-	    (i < board_get_usb_pd_port_count()); i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Empirically, the charger seems to draw a little more current that
-	 * it is set to, so we reduce our limit by 5%.
-	 */
-#if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238)
-	charge_ma = (charge_ma * 95) / 100;
-#endif
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-void board_hibernate(void)
-{
-	int port;
-
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 *
-	 * If board_hibernate() is called from within chipset task, then
-	 * chipset_do_shutdown needs to be called directly since
-	 * chipset_force_shutdown basically just sets wake event for chipset
-	 * task. But that will not help since chipset task is in board_hibernate
-	 * and never returns back to the power state machine to take down power
-	 * rails.
-	 */
-#ifdef HAS_TASK_CHIPSET
-	if (task_get_current() == TASK_ID_CHIPSET)
-		chipset_do_shutdown();
-	else
-#endif
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM);
-
-#ifdef CONFIG_USBC_PPC_NX20P3483
-	/*
-	 * If we are charging, then drop the Vbus level down to 5V to ensure
-	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
-	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
-	 * (b/79218851)
-	 */
-	port = charge_manager_get_active_charge_port();
-	if (port != CHARGE_PORT_NONE)
-		pd_request_source_voltage(port, NX20P348X_SAFE_RESET_VBUS_MV);
-#endif
-
-	/*
-	 * If Vbus isn't already on this port, then we need to put the PPC into
-	 * low power mode or open the SNK FET based on which signals wake up
-	 * the EC from hibernate.
-	 */
-	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		if (!pd_is_vbus_present(port)) {
-#ifdef VARIANT_OCTOPUS_EC_ITE8320
-			/*
-			 * ITE variant uses the PPC interrupts instead of
-			 * AC_PRESENT to wake up, so we do not need to enable
-			 * the SNK FETS.
-			 */
-			ppc_enter_low_power_mode(port);
-#else
-			/*
-			 * Open the SNK path to allow AC to pass through to the
-			 * charger when connected. This is need if the TCPC/PPC
-			 * rails do not go away and AC_PRESENT wakes up the EC
-			 * (b/79173959).
-			 */
-			ppc_vbus_sink_enable(port, 1);
-#endif
-		}
-	}
-
-	/*
-	 * Delay allows AP power state machine to settle down along
-	 * with any PD contract renegotiation, and tcpm to put TCPC into low
-	 * power mode if required.
-	 */
-	msleep(1500);
-}
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h
deleted file mode 100644
index 8b05c30f4c..0000000000
--- a/baseboard/octopus/baseboard.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Octopus board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*******************************************************************************
- * EC Config
- */
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-
-/*
- * Variant EC defines. Pick one:
- * VARIANT_OCTOPUS_EC_NPCX796FB
- * VARIANT_OCTOPUS_EC_ITE8320
- */
-#if defined(VARIANT_OCTOPUS_EC_NPCX796FB)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
-	#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-	/* Internal SPI flash on NPCX7 */
-	/* Flash is 1MB but reserve half for future use. */
-	#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT0_0
-	#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-	#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-	#define I2C_PORT_EEPROM		NPCX_I2C_PORT3_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT4_1
-	#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	/* Enable PSL hibernate mode. */
-	#define CONFIG_HIBERNATE_PSL
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-
-	/* Allow the EC to enter deep sleep in S0 */
-	#define CONFIG_LOW_POWER_S0
-#elif defined(VARIANT_OCTOPUS_EC_ITE8320)
-	/* IT83XX config */
-	#define CONFIG_IT83XX_VCC_1P8V
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_CHARGER	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_B
-	#define I2C_PORT_USBC0		IT83XX_I2C_CH_C
-	#define I2C_PORT_USBC1		IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_MUX	I2C_PORT_USBC0	/* For MUX driver */
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_F
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-	#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS
-#else
-	#error Must define a VARIANT_OCTOPUS_EC
-#endif /* VARIANT_OCTOPUS_EC */
-
-/* Common EC defines */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_DPTF
-#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_CMD_CHARGEN
-
-/* Port80 -- allow larger buffer for port80 messages */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/*
- * We don't need CONFIG_BACKLIGHT_LID since hardware AND's LID_OPEN and AP
- * signals with EC backlight enable signal.
- */
-
-/*******************************************************************************
- * Battery/Charger/Power Config
- */
-
-/*
- * Variant charger defines. Pick one:
- * VARIANT_OCTOPUS_CHARGER_ISL9238
- * VARIANT_OCTOPUS_CHARGER_BQ25703
- */
-#if defined(VARIANT_OCTOPUS_CHARGER_ISL9238)
-	#define CONFIG_CHARGER_ISL9238
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-	/*
-	 * ISL923x driver sets "Adapter insertion to Switching Debounce"
-	 * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703)
-	#define CONFIG_CHARGER_BQ25703
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-	/*
-	 * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time.
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 50
-#elif defined(CONFIG_CHARGER_RUNTIME_CONFIG)
-	#define CONFIG_CHARGER_ISL9238
-	#define CONFIG_CHARGER_BQ25710
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710 10
-
-	#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#else
-	#error Must define a VARIANT_OCTOPUS_CHARGER
-#endif /* VARIANT_OCTOPUS_CHARGER */
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_USB_CHARGER
-
-/* Common battery defines */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/*******************************************************************************
- * USB-C Configs
- * Automatically defined by VARIANT_OCTOPUS_EC_ variant.
- */
-
- /*
-  * Variant USBC defines. Pick one:
-  * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-  * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires)
-  */
-#if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)
-	#define CONFIG_USB_PD_TCPC_LOW_POWER
-	#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-	#define CONFIG_USB_PD_TCPM_ANX7447	/* C0 TCPC: ANX7447QN */
-#endif
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 TCPC: PS8751 */
-	#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-	#define CONFIG_USBC_PPC_NX20P3483
-#elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)
-	#undef CONFIG_USB_PD_TCPC_LOW_POWER
-	#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	#define CONFIG_USB_PD_VBUS_DETECT_PPC
-	#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0 & C1 TCPC: ITE EC */
-	#define CONFIG_USB_MUX_IT5205		/* C0 MUX: IT5205 */
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 Mux: PS8751 */
-	#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
-	#define CONFIG_USBC_PPC_SN5S330		/* C0 & C1 PPC: each SN5S330 */
-	#define CONFIG_USBC_PPC_VCONN
-	#define CONFIG_USBC_PPC_DEDICATED_INT
-#else
-	#error Must define a VARIANT_OCTOPUS_USBC
-#endif /* VARIANT_OCTOPUS_USBC */
-
-/* Common USB-C defines */
-#define USB_PD_PORT_TCPC_0	0
-#define USB_PD_PORT_TCPC_1	1
-#define CONFIG_USB_PID 0x5046
-
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_3A_PORTS 0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_BC12_DETECT_MAX14637
-#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
-#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_PPC_DUMP
-
-/* TODO(b/76218141): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-
-/* TODO(b/76218141): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*******************************************************************************
- * USB-A Configs
- */
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
-
-/*******************************************************************************
- * SoC / PCH Config
- */
-
- /* Common SoC / PCH defines */
-#define CONFIG_CHIPSET_GEMINILAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-/* TODO(b/74123961): Enable Virtual Wires after bringup */
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-
-/*******************************************************************************
- * Keyboard Config
- */
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#undef  CONFIG_KEYBOARD_VIVALDI
-
-/*******************************************************************************
- * Sensor Config
- */
-
-/* Common Sensor Defines */
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-/*
- * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
- */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
-#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
-
-#ifndef VARIANT_OCTOPUS_NO_SENSORS
-/*
- * Interrupt and fifo are only used for base accelerometer
- * and the lid sensor is polled real-time (in forced mode).
- */
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#endif /* VARIANT_OCTOPUS_NO_SENSORS */
-
-/*
- * Sensor stack in EC/Kernel depends on a hardware interrupt pin from EC->AP, so
- * do not define CONFIG_MKBP_USE_HOST_EVENT since all octopus boards use
- * hardware pin to send interrupt from EC -> AP (except casta).
- */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-
-/* Forward declare common (within octopus) board-specific functions */
-void board_reset_pd_mcu(void);
-
-#ifdef VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-void tcpc_alert_event(enum gpio_signal signal);
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk
deleted file mode 100644
index bb8a6f8267..0000000000
--- a/baseboard/octopus/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o cbi_ssfc.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(VARIANT_OCTOPUS_EC_NPCX796FB)+=variant_ec_npcx796fb.o
-baseboard-$(VARIANT_OCTOPUS_EC_ITE8320)+=variant_ec_ite8320.o
-baseboard-$(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)+= \
-	variant_usbc_standalone_tcpcs.o
-baseboard-$(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)+=variant_usbc_ec_tcpcs.o
diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c
deleted file mode 100644
index 80d8614eb5..0000000000
--- a/baseboard/octopus/cbi_ssfc.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-/****************************************************************************
- * Octopus CBI Second Source Factory Cache
- */
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static uint32_t cached_ssfc;
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc = 0;
-
-	CPRINTS("CBI SSFC: 0x%04X", cached_ssfc);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void)
-{
-	return ((cached_ssfc & SSFC_TCPC_P1_MASK) >> SSFC_TCPC_P1_OFFSET);
-}
-
-enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void)
-{
-	return ((cached_ssfc & SSFC_PPC_P1_MASK) >> SSFC_PPC_P1_OFFSET);
-}
-
-enum ssfc_charger get_cbi_ssfc_charger(void)
-{
-	return ((cached_ssfc & SSFC_CHARGER_MASK) >> SSFC_CHARGER_OFFSET);
-}
-
-enum ssfc_sensor get_cbi_ssfc_sensor(void)
-{
-	return ((cached_ssfc & SSFC_SENSOR_MASK) >> SSFC_SENSOR_OFFSET);
-}
diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h
deleted file mode 100644
index b762336e59..0000000000
--- a/baseboard/octopus/cbi_ssfc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _OCTOPUS_CBI_SSFC__H_
-#define _OCTOPUS_CBI_SSFC__H_
-
-/****************************************************************************
- * Octopus CBI Second Source Factory Cache
- */
-
-/*
- * TCPC Port 1 (Bits 0-2)
- */
-enum ssfc_tcpc_p1 {
-	SSFC_TCPC_P1_DEFAULT,
-	SSFC_TCPC_P1_PS8751,
-	SSFC_TCPC_P1_PS8755,
-};
-#define SSFC_TCPC_P1_OFFSET		0
-#define SSFC_TCPC_P1_MASK		GENMASK(2, 0)
-
-/*
- * PPC Port 1 (Bits 3-5)
- */
-enum ssfc_ppc_p1 {
-	SSFC_PPC_P1_DEFAULT,
-	SSFC_PPC_P1_NX20P348X,
-	SSFC_PPC_P1_SYV682X,
-};
-#define SSFC_PPC_P1_OFFSET		3
-#define SSFC_PPC_P1_MASK		GENMASK(5, 3)
-
-/*
- * Charger (Bits 8-6)
- */
-enum ssfc_charger {
-	SSFC_CHARGER_DEFAULT,
-	SSFC_CHARGER_ISL9238,
-	SSFC_CHARGER_BQ25710,
-};
-#define SSFC_CHARGER_OFFSET		6
-#define SSFC_CHARGER_MASK		GENMASK(8, 6)
-
-/*
- * Audio (Bits 11-9)
- */
-
-/*
- * Sensor (Bits 14-12)
- */
-enum ssfc_sensor {
-	SSFC_SENSOR_DEFAULT,
-	SSFC_SENSOR_BMI160,
-	SSFC_SENSOR_ICM426XX,
-};
-#define SSFC_SENSOR_OFFSET		12
-#define SSFC_SENSOR_MASK		GENMASK(14, 12)
-
-enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
-enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void);
-enum ssfc_charger get_cbi_ssfc_charger(void);
-enum ssfc_sensor get_cbi_ssfc_sensor(void);
-
-#endif /* _OCTOPUS_CBI_SSFC__H_ */
diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c
deleted file mode 100644
index 3dd6ad29f5..0000000000
--- a/baseboard/octopus/usb_pd_policy.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for octopus boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c
deleted file mode 100644
index 459ea113b3..0000000000
--- a/baseboard/octopus/variant_ec_ite8320.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_OCTOPUS_EC_ITE8320 configuration */
-
-#include "gpio.h"
-#include "i2c.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-	/*
-	 * The PPC interrupts (which fire when Vbus changes) is a proxy for
-	 * AC_PRESENT. This allows us to turn off the PPC SNK FETS during
-	 * hibernation which saves power. Once the EC wakes up, it will enable
-	 * the SNK FETs and power will make it to the rest of the system.
-	 */
-	GPIO_USB_C0_PD_INT_ODL,
-	GPIO_USB_C1_PD_INT_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",  IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"usbc0",  IT83XX_I2C_CH_C, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"usbc1",  IT83XX_I2C_CH_E, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"eeprom", IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c
deleted file mode 100644
index bccb360563..0000000000
--- a/baseboard/octopus/variant_ec_npcx796fb.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_OCTOPUS_EC_NPCX796FB configuration */
-
-#include "charge_manager.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "power.h"
-#ifdef CONFIG_PWM
-#include "pwm.h"
-#include "pwm_chip.h"
-#endif
-#include "timer.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	/* EC_RST_ODL needs to wake device while in PSL hibernate. */
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"charger", I2C_PORT_CHARGER, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-#ifndef VARIANT_OCTOPUS_NO_SENSORS
-	{"sensor",  I2C_PORT_SENSOR,  100, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-#endif
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#ifdef CONFIG_PWM
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP,
-								.freq = 100 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-#endif
diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c
deleted file mode 100644
index 2e3248410f..0000000000
--- a/baseboard/octopus/variant_usbc_ec_tcpcs.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_OCTOPUS_USBC_EC_TCPCS configuration */
-
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define USB_PD_PORT_ITE_0	0
-#define USB_PD_PORT_ITE_1	1
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-/******************************************************************************/
-/* USB-C MUX Configuration */
-
-/* TODO(crbug.com/826441): Consolidate this logic with other impls */
-static void board_it83xx_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
-	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-	enum gpio_signal gpio = me->usb_port ?
-		GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL;
-
-	/* Invert HPD level since GPIOs are active low. */
-	hpd_lvl = !hpd_lvl;
-
-	gpio_set_level(gpio, hpd_lvl);
-	if (hpd_irq) {
-		gpio_set_level(gpio, 1);
-		msleep(1);
-		gpio_set_level(gpio, hpd_lvl);
-	}
-}
-
-/* This configuration might be override by each boards */
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.usb_port = USB_PD_PORT_ITE_0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_it83xx_hpd_status,
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.usb_port = USB_PD_PORT_ITE_1,
-		/* Use PS8751 as mux only */
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &ps8xxx_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* Power Delivery and charing functions */
-
-void variant_tcpc_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-}
-/* Called after the baseboard_tcpc_init (via +3) */
-DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD
-	 * tasks.The (embedded) TCPC status since chip driver code will
-	 * handles its own interrupts and forward the correct events to
-	 * the PD_C0 task. See it83xx/intc.c
-	 */
-	return 0;
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently called from both
- * handle_pending_reboot() in common/system.c and baseboard_tcpc_init() in the
- * octopus/baseboard.c
- */
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: The internal TCPC on ITE EC does not have a reset signal,
-	 * but it will get reset when the EC gets reset.  We will, however,
-	 * reset the USB muxes here.
-	 */
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-
-	msleep(PS8XXX_RESET_DELAY_MS);
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-}
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin because the polarity should already be set
-	 * correctly in the PPC driver via the pd state machine.
-	 */
-	if (ppc_set_vconn(port, enabled) != EC_SUCCESS)
-		cprints(CC_USBPD, "C%d: Failed %sabling vconn",
-			port, enabled ? "en" : "dis");
-}
diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c
deleted file mode 100644
index fb5d466e65..0000000000
--- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common code for VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS configuration */
-
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-#else
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-#endif
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/******************************************************************************/
-/* USB-C MUX Configuration */
-
-#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* Tune USB mux registers for casta's port 0 Rx measurement */
-	mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40);
-	return EC_SUCCESS;
-}
-#endif
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-#else
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-#endif
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* Power Delivery and charing functions */
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_MUX_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_MUX_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void variant_tcpc_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_PD_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_PD_C1_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_MUX_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_MUX_INT_ODL);
-}
-/* Called after the baseboard_tcpc_init (via +3) */
-DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_MUX_INT_ODL)) {
-#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
-#else
-		if (!gpio_is_implemented(GPIO_USB_C0_PD_RST) ||
-		    !gpio_get_level(GPIO_USB_C0_PD_RST))
-#endif
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_MUX_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-	/*
-	 * C0: Assert reset to TCPC0 (PS8751) for required delay if we have a
-	 * battery
-	 */
-	if (battery_is_present() == BP_YES) {
-		/*
-		 * TODO(crbug:846412): After refactor, ensure that battery has
-		 * enough charge to last the reboot as well
-		 */
-		gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
-		msleep(PS8XXX_RESET_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
-	}
-#else
-	/*
-	 * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if
-	 * we have a battery
-	 *
-	 * Note: The TEST_R pin is not hooked up to a GPIO on all boards, so
-	 * verify the name exists before setting it.  After the name is
-	 * introduced for later board firmware, this pin will still be wired
-	 * to USB2_OTG_ID on the proto boards, which should be set to open
-	 * drain so it can't be driven high.
-	 */
-	if (gpio_is_implemented(GPIO_USB_C0_PD_RST) &&
-	    battery_is_present() == BP_YES) {
-		gpio_set_level(GPIO_USB_C0_PD_RST, 1);
-		msleep(ANX74XX_RESET_HOLD_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST, 0);
-		msleep(ANX74XX_RESET_FINISH_MS);
-	}
-#endif
-	/*
-	 * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if
-	 * we have a battery, otherwise we may brown out the system.
-	 */
-	if (battery_is_present() == BP_YES) {
-		/*
-		 * TODO(crbug:846412): After refactor, ensure that battery has
-		 * enough charge to last the reboot as well
-		 */
-		gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-		msleep(PS8XXX_RESET_DELAY_MS);
-		gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	} else {
-		CPRINTS("Skipping C1 TCPC reset because no battery");
-	}
-}
diff --git a/baseboard/trogdor/baseboard.c b/baseboard/trogdor/baseboard.c
deleted file mode 100644
index de01d58211..0000000000
--- a/baseboard/trogdor/baseboard.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor baseboard-specific configuration */
-
-#include "i2c.h"
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY ||
-		port == I2C_PORT_TCPC0 ||
-		port == I2C_PORT_TCPC1);
-}
diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h
deleted file mode 100644
index 4eabeb0ca3..0000000000
--- a/baseboard/trogdor/baseboard.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/*
- * By default, enable all console messages excepted event and HC:
- * The sensor stack is generating a lot of activity.
- * They can be enabled through the console command 'chan'.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Modules */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_FPU
-#define CONFIG_PWM
-#define CONFIG_PWM_DISPLIGHT
-
-#define CONFIG_VBOOT_HASH
-
-#undef CONFIG_PECI
-
-#define CONFIG_HOSTCMD_SHI
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_HOSTCMD_SECTION_SORTED
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_CMD_BUTTON
-#define CONFIG_SWITCH
-#define CONFIG_LID_SWITCH
-#define CONFIG_EXTPOWER_GPIO
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Increase console output buffer since we have the RAM available. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_USB_CHARGER
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-
-/*
- * USB ID
- *
- * This is allocated specifically for Trogdor
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x5043
-
-/* USB */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* RTC */
-#define CONFIG_CMD_RTC
-#define CONFIG_HOSTCMD_RTC
-
-/* Sensors */
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
-
-#define PD_OPERATING_POWER_MW   10000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
-
-/* Chipset */
-#define CONFIG_CHIPSET_SC7180
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CHIPSET_RESUME_INIT_HOOK
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_CMD_AP_RESET_LOG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_LID_OPEN		GPIO_LID_OPEN_EC
-#define GPIO_SHI_CS_L		GPIO_AP_EC_SPI_CS_L
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_BATT_PRES_ODL	GPIO_EC_BATT_PRES_ODL
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_ENABLE_BACKLIGHT	GPIO_EC_BL_DISABLE_L
-#define GPIO_BOARD_VERSION1	GPIO_BRD_ID0
-#define GPIO_BOARD_VERSION2	GPIO_BRD_ID1
-#define GPIO_BOARD_VERSION3	GPIO_BRD_ID2
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-
-/* I2C Ports */
-#define I2C_PORT_BATTERY I2C_PORT_POWER
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_WLC     NPCX_I2C_PORT3_0
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
-
-/* UART */
-#define CONFIG_CMD_CHARGEN
-
-/* Define the host events which are allowed to wake AP up from S3 */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
-
-/* And the MKBP events */
-#ifdef HAS_TASK_KEYSCAN
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
-#else
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
-#endif
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/trogdor/build.mk b/baseboard/trogdor/build.mk
deleted file mode 100644
index 0f36051eee..0000000000
--- a/baseboard/trogdor/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y+=baseboard.o
-baseboard-y+=hibernate.o
-baseboard-y+=power.o
-baseboard-y+=usbc_config.o
-baseboard-y+=usb_pd_policy.o
diff --git a/baseboard/trogdor/hibernate.c b/baseboard/trogdor/hibernate.c
deleted file mode 100644
index c28082e75d..0000000000
--- a/baseboard/trogdor/hibernate.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "system.h"
-
-void board_hibernate_late(void)
-{
-	/* Set the hibernate GPIO to turn off the rails */
-	gpio_set_level(GPIO_HIBERNATE_L, 0);
-}
diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c
deleted file mode 100644
index b539539c98..0000000000
--- a/baseboard/trogdor/power.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "task.h"
-
-void board_chipset_pre_init(void)
-{
-	/* Turn on the 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300_A, 1);
-
-	/* Turn on the 5V rail. */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 1);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-}
-DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
-
-void board_chipset_shutdown_complete(void)
-{
-	/* Turn off the 5V rail. */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 0);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-
-	/* Turn off the 3.3V and 5V rails. */
-	gpio_set_level(GPIO_EN_PP3300_A, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete,
-		HOOK_PRIO_DEFAULT);
diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c
deleted file mode 100644
index d7ed03e941..0000000000
--- a/baseboard/trogdor/usb_pd_policy.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* In G3, do not allow vconn swap since PP5000 rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-#if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
-#else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-#endif
-
-static void board_vbus_update_source_current(int port)
-{
-	/* Both port are controlled by PPC SN5S330. */
-	ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
-	ppc_vbus_source_enable(port, vbus_en[port]);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_vbus_sink_enable(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-	board_vbus_update_source_current(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return tcpm_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	uint8_t pin_mode = get_dp_pin_mode(port);
-
-	if (!pin_mode)
-		return 0;
-
-	/*
-	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
-	 * The AP only supports one DP phy. An external DP mux switches between
-	 * the two ports. Should switch those muxes when it is really used,
-	 * i.e. HPD high; otherwise, the real use case is preempted, like:
-	 *  (1) plug a dongle without monitor connected to port-0,
-	 *  (2) plug a dongle without monitor connected to port-1,
-	 *  (3) plug a monitor to the port-1 dongle.
-	 */
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-}
-
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-
-	return 1;
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	int cur_lvl = gpio_get_level(hpd);
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (!is_dp_muxable(port)) {
-		/* TODO(waihong): Info user? */
-		CPRINTS("p%d: The other port is already muxed.", port);
-		return 0;
-	}
-
-	/*
-	 * Initial implementation to handle HPD. Only the first-plugged port
-	 * works, i.e. sending HPD signal to AP. The second-plugged port
-	 * will be ignored.
-	 *
-	 * TODO(waihong): Continue the above case, if the first-plugged port
-	 * is then unplugged, switch to the second-plugged port and signal AP?
-	 */
-	if (lvl) {
-		/*
-		 * Enable and switch the DP port selection mux to the
-		 * correct port.
-		 *
-		 * TODO(waihong): Better to move switching DP mux to
-		 * the usb_mux abstraction.
-		 */
-		gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
-		gpio_set_level(GPIO_DP_MUX_OE_L, 0);
-
-		/* Connect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		/*
-		 * Connect the USB SS/DP lines in TCPC chip.
-		 *
-		 * When mf_pref not true, still use the dock muxing
-		 * because of the board USB-C topology (limited to 2
-		 * lanes DP).
-		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	} else {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Disconnect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 0);
-
-		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	}
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		pd_notify_dp_alt_mode_entry(port);
-
-	/* Configure TCPC for the HPD event, for proper muxing */
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-	/* Signal AP for the HPD event, through GPIO to AP */
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* Wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* Generate IRQ_HPD pulse */
-		gpio_set_level(hpd, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		gpio_set_level(hpd, 1);
-
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	} else if (irq & !lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0;
-	} else {
-		gpio_set_level(hpd, lvl);
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	}
-
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	if (is_dp_muxable(port)) {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Signal AP for the HPD low event */
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
-	}
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/trogdor/usbc_config.c b/baseboard/trogdor/usbc_config.c
deleted file mode 100644
index 8f3fb02c30..0000000000
--- a/baseboard/trogdor/usbc_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor family-specific USB-C configuration */
-
-#include "charger.h"
-#include "charger/isl923x_public.h"
-#include "charge_state.h"
-#include "usb_pd.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int usb_mv;
-	int port;
-
-	if (curr->state != ST_CHARGE)
-		return 0;
-
-	/* Lower the max requested voltage to 5V when battery is full. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    (curr->batt.status & STATUS_FULLY_CHARGED))
-		usb_mv = 5000;
-	else
-		usb_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != usb_mv) {
-		CPRINTS("VBUS limited to %dmV", usb_mv);
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, usb_mv);
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c
deleted file mode 100644
index 6b3ad33a35..0000000000
--- a/baseboard/volteer/baseboard.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific configuration */
-#include "adc.h"
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "charger.h"
-#include "charge_ramp.h"
-#include "cros_board_info.h"
-#include "driver/charger/isl9241.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#ifdef CONFIG_ZEPHYR
-#include "usbc_config.h"
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/******************************************************************************/
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_PP3300_REGULATOR] = {
-		.name = "TEMP_PP3300_REGULATOR",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH8,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_FAN] = {
-		.name = "TEMP_FAN",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_ACOK_OD,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1_CHARGER},
-	[TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR},
-	[TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3_DDR_SOC},
-	[TEMP_SENSOR_4_FAN] = {.name = "Fan",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h
deleted file mode 100644
index 38a464813a..0000000000
--- a/baseboard/volteer/baseboard.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#include <stdbool.h>
-
-/*
- * By default, enable all console messages excepted HC
- */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* Allow objects to be linked into a flash resident section */
-#define CONFIG_CHIP_INIT_ROM_REGION
-
-/* EC Defines */
-#define CONFIG_LTO
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DPTF
-#define CONFIG_FPU
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Host communication */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Chipset config */
-#define CONFIG_CHIPSET_TIGERLAKE
-#define CONFIG_CHIPSET_PP3300_RAIL_FIRST
-#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
-#define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_BOARD_HAS_RTC_RESET
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Thermal features */
-#define CONFIG_FANS			FAN_CH_COUNT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_PG_EC_DSW_PWROK
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT		512
-
-/*
- * Hardware based charge ramp is broken in the ISL9241 (b/169350714).
- */
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_ISL9241
-/* Setting ISL9241 Register Control1 switching frequency to 724kHz. */
-#define CONFIG_ISL9241_SWITCHING_FREQ	ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ
-
-#define CONFIG_USB_CHARGER
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated)
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
-
-/* Common battery defines */
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-
-/* Common LED defines */
-#define CONFIG_LED_COMMON
-
-/* EDP back-light control defines */
-#define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EC_EDP_BL_EN
-
-/* USB Type C and USB PD defines */
-/* Enable the new USB-C PD stack */
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-
-/*
- * TODO(b/158572770): TCPMv2: Conserve flash space
- * Add these console commands as flash space permits.
- */
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_ACCELS
-#undef CONFIG_CMD_ACCEL_INFO
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_PPC_DUMP
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_ALT_MODE_UFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_RT1715
-#define CONFIG_USB_PD_TCPM_TUSB422	/* USBC port C0 */
-#define CONFIG_USB_PD_TCPM_PS8815	/* USBC port USB3 DB */
-#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
-#define CONFIG_CMD_USB_PD_PE
-
-/*
- * Because of the CSE Lite, an extra cold AP reset is needed, and older cr50
- * firmware will not be able to detect it because of updated cr50 pin straps.
- * Therefore, the AP will require the EC to reset it so that the proper reset
- * signal will be read and verstage can execute again.
- */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/*
- * The PS8815 TCPC was found to require a 50ms delay to consistently work
- * with non-PD chargers.  Override the default low-power mode exit delay.
- */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
-
-/* Enable USB3.2 DRD */
-#define CONFIG_USB_PD_USB32_DRD
-
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#define CONFIG_USBC_PPC
-/* Note - SN5S330 support automatically adds
- * CONFIG_USBC_PPC_POLARITY
- * CONFIG_USBC_PPC_SBU
- * CONFIG_USBC_PPC_VCONN
- */
-#define CONFIG_USBC_PPC_DEDICATED_INT
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Enabling SOP* communication */
-#define CONFIG_CMD_USB_PD_CABLE
-#define CONFIG_USB_PD_DECODE_SOP
-
-/* UART COMMAND */
-#define CONFIG_CMD_CHARGEN
-
-/*
- * USB ID
- * This is allocated specifically for Volteer
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x503E
-/* Device version of product. */
-#define CONFIG_USB_BCD_DEV 0x0000
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_INTEL_BB
-#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Enable volume button command in EC console */
-#define CONFIG_CMD_BUTTON
-
-/* Enable volume button in ectool */
-#define CONFIG_HOSTCMD_BUTTON
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "common.h"
-#include "baseboard_usbc_config.h"
-#include "cbi.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_CHARGER,
-	ADC_TEMP_SENSOR_2_PP3300_REGULATOR,
-	ADC_TEMP_SENSOR_3_DDR_SOC,
-	ADC_TEMP_SENSOR_4_FAN,
-	ADC_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_CHARGER,
-	TEMP_SENSOR_2_PP3300_REGULATOR,
-	TEMP_SENSOR_3_DDR_SOC,
-	TEMP_SENSOR_4_FAN,
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * Check battery disconnect state.
- * This function will return if battery is initialized or not.
- * @return true - initialized. false - not.
- */
-__override_proto bool board_battery_is_initialized(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/volteer/baseboard_usbc_config.h b/baseboard/volteer/baseboard_usbc_config.h
deleted file mode 100644
index bf02b1cb34..0000000000
--- a/baseboard/volteer/baseboard_usbc_config.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* volteer family-specific USB-C configuration */
-
-#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
-#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
-
-#include "gpio_signal.h"
-
-/* Common definition for the USB PD interrupt handlers. */
-void ppc_interrupt(enum gpio_signal signal);
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c
deleted file mode 100644
index 4953d7a49e..0000000000
--- a/baseboard/volteer/battery_presence.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common battery presence checking for Volteer family.
- * Each board should implement board_battery_info[] to define the specific
- * battery packs supported.
- */
-#include <stdbool.h>
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "gpio.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
-
-static bool battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-__overridable bool board_battery_is_initialized(void)
-{
-	/*
-	 * Set default to return true
-	 */
-	return true;
-}
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-	bool batt_initialization_state;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Check battery initialization. If the battery is not initialized,
-	 * then return BP_NOT_SURE. Battery could be in ship
-	 * mode and might require pre-charge current to wake it up. BP_NO is not
-	 * returned here because charger state machine will not provide
-	 * pre-charge current assuming that battery is not present.
-	 */
-	batt_initialization_state = board_battery_is_initialized();
-	if (!batt_initialization_state)
-		return BP_NOT_SURE;
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Initialized
-	 */
-	if (battery_is_cut_off() || !battery_init())
-		batt_pres = BP_NO;
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/baseboard/volteer/build.mk b/baseboard/volteer/build.mk
deleted file mode 100644
index 08b68c5816..0000000000
--- a/baseboard/volteer/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Volteer baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-y+=battery_presence.o
-baseboard-y+=charger.o
-baseboard-y+=usb_pd_policy.o
-baseboard-y+=cbi.o
-baseboard-y+=cbi_ec_fw_config.o
-baseboard-y+=cbi_ssfc.o
-baseboard-y+=power.o
-baseboard-y+=usbc_config.o
diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c
deleted file mode 100644
index ea446acc4e..0000000000
--- a/baseboard/volteer/cbi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific functions, shared with Zephyr */
-
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-#include "system.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-static uint8_t board_id;
-
-uint8_t get_board_id(void)
-{
-	return board_id;
-}
-
-__overridable void board_cbi_init(void)
-{
-}
-
-/*
- * Read CBI from i2c eeprom and initialize variables for board variants
- *
- * Example for configuring for a USB3 DB:
- *   ectool cbi set 6 2 4 10
- */
-static void cbi_init(void)
-{
-	uint32_t cbi_val;
-
-	/* Board ID */
-	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
-	    cbi_val > UINT8_MAX)
-		CPRINTS("CBI: Read Board ID failed");
-	else
-		board_id = cbi_val;
-
-	CPRINTS("Board ID: %d", board_id);
-
-	/* FW config */
-	init_fw_config();
-
-	/* Allow the board project to make runtime changes based on CBI data */
-	board_cbi_init();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST);
diff --git a/baseboard/volteer/cbi.h b/baseboard/volteer/cbi.h
deleted file mode 100644
index 049c0f65e2..0000000000
--- a/baseboard/volteer/cbi.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific CBI functions, shared with Zephyr */
-
-#ifndef __CROS_EC_BASEBOARD_CBI_H
-#define __CROS_EC_BASEBOARD_CBI_H
-
-unsigned char get_board_id(void);
-
-/**
- * Configure run-time data structures and operation based on CBI data. This
- * typically includes customization for changes in the BOARD_VERSION and
- * FW_CONFIG fields in CBI. This routine is called from the baseboard after
- * the CBI data has been initialized.
- */
-__override_proto void board_cbi_init(void);
-
-#endif /* __CROS_EC_BASEBOARD_CBI_H */
diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c
deleted file mode 100644
index e602691aeb..0000000000
--- a/baseboard/volteer/cbi_ec_fw_config.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "cbi_ec_fw_config.h"
-#include "cros_board_info.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union volteer_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/****************************************************************************
- * Volteer FW_CONFIG access
- */
-void init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-}
-
-union volteer_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
-
-bool ec_cfg_has_tabletmode(void)
-{
-	return (fw_config.tabletmode == TABLETMODE_ENABLED);
-}
-
-bool ec_cfg_has_keyboard_backlight(void)
-{
-	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
-}
-
-bool ec_cfg_has_numeric_pad(void)
-{
-	return (fw_config.num_pad == NUMERIC_PAD_ENABLED);
-}
-
-enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void)
-{
-	return fw_config.kb_layout;
-}
diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h
deleted file mode 100644
index 0a44e1f9e4..0000000000
--- a/baseboard/volteer/cbi_ec_fw_config.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __VOLTEER_CBI_EC_FW_CONFIG_H_
-#define __VOLTEER_CBI_EC_FW_CONFIG_H_
-
-#include "stdbool.h"
-#include "stdint.h"
-
-/****************************************************************************
- * CBI FW_CONFIG layout shared by all Volteer boards
- *
- * Source of truth is the program/volteer/program.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB4_GEN2 = 1,
-	DB_USB3_ACTIVE = 2,
-	DB_USB4_GEN3 = 3,
-	DB_USB3_PASSIVE = 4,
-	DB_USB3_NO_A = 5,
-	DB_USB_COUNT
-};
-
-/*
- * Tablet Mode (1 bit), shared by all Volteer boards
- */
-enum ec_cfg_tabletmode_type {
-	TABLETMODE_DISABLED = 0,
-	TABLETMODE_ENABLED = 1,
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-enum ec_cfg_numeric_pad_type {
-	NUMERIC_PAD_DISABLED = 0,
-	NUMERIC_PAD_ENABLED = 1
-};
-
-enum ec_cfg_keyboard_layout {
-	KB_LAYOUT_DEFAULT = 0,
-	KB_LAYOUT_1 = 1
-};
-
-union volteer_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				thermal : 4;
-		uint32_t				audio : 3;
-		enum ec_cfg_tabletmode_type		tabletmode : 1;
-		uint32_t				lte_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		enum ec_cfg_numeric_pad_type		num_pad : 1;
-		uint32_t				sd_db : 4;
-		enum ec_cfg_keyboard_layout		kb_layout : 2;
-		uint32_t				reserved_2 : 10;
-	};
-	uint32_t raw_value;
-};
-
-/*
- * Each Volteer board must define the default FW_CONFIG options to use
- * if the CBI data has not been initialized.
- */
-extern union volteer_cbi_fw_config fw_config_defaults;
-
-/**
- * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the
- * FW_CONFIG to the board specific defaults.
- */
-void init_fw_config(void);
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union volteer_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-/**
- * Check if the FW_CONFIG has enabled tablet mode operation.
- *
- * @return true if board supports tablet mode, false if the board supports
- * clamshell operation only.
- */
-bool ec_cfg_has_tabletmode(void);
-
-/**
- * Check if the FW_CONFIG has enabled keyboard backlight.
- *
- * @return true if board supports keyboard backlight, false if the board
- * doesn't support it.
- */
-bool ec_cfg_has_keyboard_backlight(void);
-
-/**
- * Check if the FW_CONFIG has enabled numeric pad.
- *
- * @return true if board supports numeric pad, false if the board
- * doesn't support it.
- */
-bool ec_cfg_has_numeric_pad(void);
-
-/**
- * Get keyboard type from FW_CONFIG.
- *
- * @return the keyboard type.
- */
-enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void);
-
-#endif /* __VOLTEER_CBI_EC_FW_CONFIG_H_ */
diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c
deleted file mode 100644
index 42b11c4a1c..0000000000
--- a/baseboard/volteer/cbi_ssfc.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union volteer_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return cached_ssfc.lid_sensor;
-}
-
-enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void)
-{
-	return cached_ssfc.lightbar;
-}
diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h
deleted file mode 100644
index 27db1d3809..0000000000
--- a/baseboard/volteer/cbi_ssfc.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _VOLTEER_CBI_SSFC__H_
-#define _VOLTEER_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Volteer CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BASE_BMI160 = 1,
-	SSFC_SENSOR_BASE_ICM426XX = 2
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_LID_BMA255 = 1,
-	SSFC_SENSOR_LID_KX022 = 2
-};
-
-/*
- * Lightbar (Bits 6-7)
- */
-enum ec_ssfc_lightbar {
-	SSFC_LIGHTBAR_NONE = 0,
-	SSFC_LIGHTBAR_10_LED = 1,
-	SSFC_LIGHTBAR_12_LED = 2
-};
-
-union volteer_cbi_ssfc {
-	struct {
-		enum ec_ssfc_base_sensor base_sensor : 3;
-		enum ec_ssfc_lid_sensor lid_sensor : 3;
-		enum ec_ssfc_lightbar lightbar : 2;
-		uint32_t reserved_2 : 24;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-/**
- * Get lightbar type from SSFC_CONFIG.
- *
- * @return the lightbar type.
- */
-enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void);
-
-#endif /* _Volteer_CBI_SSFC__H_ */
diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c
deleted file mode 100644
index a674b98f41..0000000000
--- a/baseboard/volteer/charger.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific configuration */
-#include "common.h"
-#include "charger.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "driver/charger/isl9241_public.h"
-#include "gpio.h"
-#ifdef CONFIG_ZEPHYR
-#include "usbc_config.h"
-#endif
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Note that the level is inverted because the pin is active low. */
-	switch (port) {
-	case USBC_PORT_C0:
-		gpio_set_level(GPIO_USB_C0_OC_ODL, !is_overcurrented);
-		break;
-	case USBC_PORT_C1:
-		gpio_set_level(GPIO_USB_C1_OC_ODL, !is_overcurrented);
-		break;
-	}
-}
diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c
deleted file mode 100644
index fa20cfa93f..0000000000
--- a/baseboard/volteer/power.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "power/icelake.h"
-
-/*
- * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
- * 235) in the Tiger Lake Platform Design Guide for the list of potential
- * signals.
- *
- * Volteer uses this power sequence:
- *	GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
- *		the VCCST_PWRGD input to the AP so this signal must be delayed
- *		5 ms to meet the tCPU00 timing requirement.
- *	GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
- *		a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
- *		b/144478941 for full discussion.
- *
- * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
- * signals. If your board adds these signals to the EC, copy this array
- * to your board.c file and modify as needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
-	{
-		.gpio = GPIO_EN_PPVAR_VCCIN,
-		.delay_ms = 5,
-	},
-	{
-		.gpio = GPIO_EC_PCH_SYS_PWROK,
-		.delay_ms = 50 - 5,
-	},
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
-	/* No delays needed during S0 exit */
-	{
-		.gpio = GPIO_EC_PCH_SYS_PWROK,
-	},
-	/* Turn off VCCIN last */
-	{
-		.gpio = GPIO_EN_PPVAR_VCCIN,
-	},
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
-
-static void baseboard_init(void)
-{
-	/* Enable monitoring of the PROCHOT input to the EC */
-	gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c
deleted file mode 100644
index f939998b3d..0000000000
--- a/baseboard/volteer/usb_pd_policy.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Shared USB-C policy for Volteer boards */
-#include "charge_manager.h"
-#include "chipset.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "system.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000_A);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/* Responses specifically for the enablement of TBT mode in the role of UFP */
-
-#define OPOS_TBT 1
-
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(
-				CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
-
-static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
-{
-	/* TODO(b/154962766): Get an XID */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_I(IDH)] = vdo_idh_rev30;
-		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
-		/* TODO(b/156749387): Find power number for USB3/4 */
-		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
-		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
-		return VDO_I(PTYPE_DFP_VDO) + 1;
-	}
-
-	/* PD Revision 2.0 */
-	payload[VDO_I(IDH)] = vdo_idh;
-	return VDO_I(PRODUCT) + 1;
-}
-
-static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
-	return 2;
-}
-
-static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) {
-		memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes));
-		return ARRAY_SIZE(vdo_tbt_modes) + 1;
-	} else {
-		return 0; /* NAK */
-	}
-}
-
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
-{
-	mux_state_t mux_state = 0;
-
-	/* Do not enter mode while CPU is off. */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return 0; /* NAK */
-
-	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
-		return 0; /* NAK */
-
-	mux_state = usb_mux_get(port);
-	/*
-	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
-	 * UFP (responder) should be in USB mode or safe mode before sending
-	 * Enter Mode Command response.
-	 */
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
-		pd_ufp_set_enter_mode(port, payload);
-		set_tbt_compat_mode_ready(port);
-		CPRINTS("UFP Enter TBT mode");
-		return 1; /* ACK */
-	}
-
-	CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state);
-	return 0;
-}
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_tbt_compat_response_identity,
-	.svids = &svdm_tbt_compat_response_svids,
-	.modes = &svdm_tbt_compat_response_modes,
-	.enter_mode = &svdm_tbt_compat_response_enter_mode,
-	.amode = NULL,
-	.exit_mode = NULL,
-};
diff --git a/baseboard/volteer/usbc_config.c b/baseboard/volteer/usbc_config.c
deleted file mode 100644
index 1e483eae34..0000000000
--- a/baseboard/volteer/usbc_config.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific USB-C configuration */
-
-#include "common.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "gpio.h"
-#include "task.h"
-#ifdef CONFIG_ZEPHYR
-#include "usbc_config.h"
-#include "baseboard_usbc_config.h"
-#endif
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "driver/charger/isl9241_public.h"
-
-/******************************************************************************/
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	/* TODO: b/140572591 - check correct operation for Volteer */
-
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = USBC_PORT_C0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = USBC_PORT_C1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/**
- * Return if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	/*
-	 * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input
-	 * current until voltage drops to the minimum input voltage of the
-	 * charger, 4.096V.
-	 */
-	return voltage < ISL9241_BC12_MIN_VOLTAGE;
-}
diff --git a/baseboard/zork/analyzestack.yaml b/baseboard/zork/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/baseboard/zork/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c
deleted file mode 100644
index 0b48d1075b..0000000000
--- a/baseboard/zork/baseboard.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Zork family-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/charger/isl9241.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define SAFE_RESET_VBUS_MV 5000
-
-/*
- * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
- * until voltage drops to 4.5V. Don't go lower than this to be kind to the
- * charger (see b/67964166).
- */
-#define BC12_MIN_VOLTAGE 4500
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-__overridable int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv;
-
-	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-
-	return rv;
-}
-
-static void baseboard_chipset_suspend(void)
-{
-	/* Disable display and keyboard backlights. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1);
-	ioex_set_level(IOEX_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_resume(void)
-{
-	/* Enable display and keyboard backlights. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0);
-	ioex_set_level(IOEX_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/*
- * We use 11 as the scaling factor so that the maximum mV value below (2761)
- * can be compressed to fit in a uint8_t.
- */
-#define THERMISTOR_SCALING_FACTOR 11
-
-/*
- * Values are calculated from the "Resistance VS. Temperature" table on the
- * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
- */
-const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
-};
-
-const struct thermistor_info thermistor_info = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR,
-	.num_pairs = ARRAY_SIZE(thermistor_data),
-	.data = thermistor_data,
-};
-
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-		if (enable) {
-			keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-		} else {
-			/*
-			 * Ensure that the chipset is off before disabling the
-			 * keyboard. When the chipset is on, the EC keeps the
-			 * keyboard enabled and the AP decides whether to
-			 * ignore input devices or not.
-			 */
-			if (!chipset_in_s0)
-				keyboard_scan_enable(0,
-						     KB_SCAN_DISABLE_LID_ANGLE);
-		}
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS)
-		ccprints("Board Version: %d (0x%x)", val, val);
-	else
-		ccprints("Board Version: not set in cbi");
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		ccprints("SKU ID: %d (0x%x)", val, val);
-	else
-		ccprints("SKU ID: not set in cbi");
-
-	val = get_cbi_fw_config();
-	if (val != UNINITIALIZED_FW_CONFIG)
-		ccprints("FW Config: %d (0x%x)", val, val);
-	else
-		ccprints("FW Config: not set in cbi");
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/*
- * Returns 1 for boards that are convertible into tablet mode, and zero for
- * clamshells.
- */
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_config_has_lid_angle_tablet_mode();
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (ec_config_has_pwm_keyboard_backlight() == PWM_KEYBOARD_BACKLIGHT_NO)
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
-
-void board_hibernate(void)
-{
-	int port;
-
-	/*
-	 * If we are charging, then drop the Vbus level down to 5V to ensure
-	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
-	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
-	 * (b/79218851, b/143778351, b/147007265)
-	 */
-	port = charge_manager_get_active_charge_port();
-	if (port != CHARGE_PORT_NONE) {
-		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
-
-		/* Give PD task and PPC chip time to get to 5V */
-		msleep(900);
-	}
-}
-
-__overridable int check_hdmi_hpd_status(void)
-{
-	/* Default hdmi insert. */
-	return 1;
-}
-
-void sbu_fault_interrupt(enum ioex_signal signal)
-{
-	int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1;
-
-	pd_handle_overcurrent(port);
-}
-
-static void set_ac_prochot(void)
-{
-	isl9241_set_ac_prochot(CHARGER_SOLO, ZORK_AC_PROCHOT_CURRENT_MA);
-}
-DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
-
-DECLARE_DEFERRED(board_print_temps);
-int temps_interval;
-
-void board_print_temps(void)
-{
-	int t, i;
-	int rv;
-
-	cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW);
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		rv = temp_sensor_read(i, &t);
-		if (rv == EC_SUCCESS)
-			cprintf(CC_THERMAL, "%s=%dK (%dC) ",
-				temp_sensors[i].name, t, K_TO_C(t));
-	}
-	cprintf(CC_THERMAL, "]\n");
-
-	if (temps_interval > 0)
-		hook_call_deferred(&board_print_temps_data,
-				   temps_interval * SECOND);
-}
-
-static int command_temps_log(int argc, char **argv)
-{
-	char *e = NULL;
-
-	if (argc != 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	temps_interval = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	board_print_temps();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log,
-			"seconds",
-			"Print temp sensors periodically");
-
-/*
- * b/164921478: On G3->S5, wait for RSMRST_L to be deasserted before asserting
- * PWRBTN_L.
- */
-void board_pwrbtn_to_pch(int level)
-{
-	/* Add delay for G3 exit if asserting PWRBTN_L and S5_PGOOD is low. */
-	if (!level && !gpio_get_level(GPIO_S5_PGOOD)) {
-		/*
-		 * From measurement, wait 80 ms for RSMRST_L to rise after
-		 * S5_PGOOD.
-		 */
-		msleep(80);
-
-		if (!gpio_get_level(GPIO_S5_PGOOD))
-			ccprints("Error: pwrbtn S5_PGOOD low");
-	}
-	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage = 0;
-	int rv;
-
-	rv = charger_get_vbus_voltage(port, &voltage);
-
-	if (rv) {
-		ccprints("%s rv=%d", __func__, rv);
-		return 0;
-	}
-
-	/*
-	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
-	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
-	 * This partly defeats the point of ramping, but will still catch
-	 * VBUS below 4.5V and above 0V.
-	 */
-	if (voltage == 0) {
-		ccprints("%s vbus=0", __func__);
-		return 0;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE)
-		ccprints("%s vbus=%d", __func__, voltage);
-
-	return voltage < BC12_MIN_VOLTAGE;
-}
-
-/**
- * Always ramp up input current since AP needs higher power, even if battery is
- * very low or full. We can always re-ramp if input current increases beyond
- * what supplier can provide.
- */
-__override int charge_is_consuming_full_input_current(void)
-{
-	return 1;
-}
diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h
deleted file mode 100644
index d84ebbcef8..0000000000
--- a/baseboard/zork/baseboard.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Zork baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-#if (defined(VARIANT_ZORK_TREMBYLE) \
-	+ defined(VARIANT_ZORK_DALBOZ)) != 1
-#error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ
-#endif
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */
-
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC)))
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_UPDATE_IF_CHANGED
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-
-/* CBI EEPROM for board version and SKU ID */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_CRC8
-
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-/*
- * Enable support for battery hostcmd, supporting longer strings.
- *
- * Vilboz battery options' model names vary in the 8th character, which is
- * truncated in the memory mapped battery info; differentiating them requires
- * support for EC_CMD_BATTERY_GET_STATIC version 1.
- */
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-/*
- * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
- * but that feature of ISL9241 is broken (b/160287056) so we have to use
- * CONFIG_CHARGE_RAMP_SW instead.
- */
-#define CONFIG_CHARGE_RAMP_SW
-
-#define CONFIG_CHIPSET_STONEY
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
-#define CONFIG_THROTTLE_AP
-
-#ifdef VARIANT_ZORK_TREMBYLE
-	#define CONFIG_FANS FAN_CH_COUNT
-	#undef CONFIG_FAN_INIT_SPEED
-	#define CONFIG_FAN_INIT_SPEED 50
-#endif
-
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-#define CONFIG_LED_ONOFF_STATES
-
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_KEYBOARD_VIVALDI
-
-/*
- * USB ID
- *
- * This is allocated specifically for Zork
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x5040
-
-#define CONFIG_USB_PD_REV30
-
-/* Enable the TCPMv2 PD stack */
-#define CONFIG_USB_PD_TCPMV2
-
-#ifndef CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPMV1
-#else
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_DRP_ACC_TRYSRC
-
-	 /* Enable TCPMv2 Fast Role Swap */
-	 /* Turn off until FRSwap is working */
-	#undef CONFIG_USB_PD_FRS_TCPC
-#endif
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#ifdef VARIANT_ZORK_TREMBYLE
-/*
- * Use a custom HPD function that supports HPD on IO expander.
- * TODO(b/165622386) remove this when HPD is on EC GPIO.
- */
-#	define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#endif
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_NCT38XX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_SBU
-#define CONFIG_USBC_PPC_AOZ1380
-#define CONFIG_USBC_RETIMER_PI3HDX1204
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_MUX_AMD_FP5
-
-#if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-	#define CONFIG_USBC_PPC_NX20P3483
-	#define CONFIG_USBC_RETIMER_PS8802
-	#define CONFIG_USBC_RETIMER_PS8818
-	#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
-	#define CONFIG_USB_MUX_RUNTIME_CONFIG
-	/* USB-A config */
-	#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-	#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-	/* PS8818 RX Input Termination - default value */
-	#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM
-#elif defined(VARIANT_ZORK_DALBOZ)
-	#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
-#endif
-
-/* USB-A config */
-#define USB_PORT_COUNT USBA_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
-#define ZORK_AC_PROCHOT_CURRENT_MA 3328
-
-/*
- * EC will boot AP to depthcharge if: (BAT >= 4%) || (AC >= 50W)
- * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
- * Depthcharge to boot OS.
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
-
-/* Increase length of history buffer for port80 messages. */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* Increase console output buffer since we have the RAM available. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_USBA0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USBA1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_AP_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT4_1
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_EEPROM		I2C_PORT_SENSOR
-#define I2C_PORT_AP_AUDIO	NPCX_I2C_PORT6_1
-
-#if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_CHARGER_RUNTIME_CONFIG
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V1	NPCX_I2C_PORT4_1
-	#define I2C_PORT_AP_HDMI	NPCX_I2C_PORT7_0
-#elif defined(VARIANT_ZORK_DALBOZ)
-	#define I2C_PORT_BATTERY_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_BATTERY_V1	NPCX_I2C_PORT7_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT2_0
-#endif
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define CONFIG_MKBP_EVENT
-/* Host event is required to wake from sleep */
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-/* Required to enable runtime configuration */
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK (BIT(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED))
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* Thermal */
-#define CONFIG_TEMP_SENSOR_SB_TSI
-
-#ifdef HAS_TASK_MOTIONSENSE
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#endif
-
-/* Audio */
-#define CONFIG_AUDIO_CODEC
-#define CONFIG_AUDIO_CODEC_DMIC
-#define CONFIG_AUDIO_CODEC_I2S_RX
-
-/* CLI COMMAND */
-#define CONFIG_CMD_CHARGEN
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "math_util.h"
-#include "registers.h"
-
-enum power_signal {
-	X86_SLP_S3_N,
-	X86_SLP_S5_N,
-	X86_S0_PGOOD,
-	X86_S5_PGOOD,
-	POWER_SIGNAL_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-#ifdef VARIANT_ZORK_TREMBYLE
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-#endif
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-/*
- * Matrix to rotate accelerators into the standard reference frame.  The default
- * is the identity which is correct for the reference design.  Variations of
- * Zork may need to change it for manufacturability.
- * For the lid:
- *  +x to the right
- *  +y up
- *  +z out of the page
- *
- * The principle axes of the body are aligned with the lid when the lid is in
- * the 180 degree position (open, flat).
- *
- * Boards within the Zork family may need to modify this definition at
- * board_init() time.
- */
-extern mat33_fp_t zork_base_standard_ref;
-
-extern const struct thermistor_info thermistor_info;
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-
-void mst_hpd_interrupt(enum ioex_signal signal);
-void sbu_fault_interrupt(enum ioex_signal signal);
-
-#ifdef VARIANT_ZORK_TREMBYLE
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-__override_proto void ppc_interrupt(enum gpio_signal signal);
-#endif
-
-void board_print_temps(void);
-
-/* GPIO or IOEX signal used to set IN_HPD on DB retimer. */
-extern int board_usbc1_retimer_inhpd;
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk
deleted file mode 100644
index e79d60cc91..0000000000
--- a/baseboard/zork/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-y+=cbi_ec_fw_config.o
-baseboard-y+=cbi_ssfc.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(VARIANT_ZORK_TREMBYLE)+=variant_trembyle.o
-baseboard-$(VARIANT_ZORK_DALBOZ)+=variant_dalboz.o
diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c
deleted file mode 100644
index cbb0821c42..0000000000
--- a/baseboard/zork/cbi_ec_fw_config.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cbi_ec_fw_config.h"
-#include "cros_board_info.h"
-
-/****************************************************************************
- * CBI Zork EC FW Configuration
- */
-uint32_t get_cbi_fw_config(void)
-{
-	static uint32_t cached_fw_config = UNINITIALIZED_FW_CONFIG;
-
-	if (cached_fw_config == UNINITIALIZED_FW_CONFIG) {
-		uint32_t val;
-
-		if (cbi_get_fw_config(&val) == EC_SUCCESS)
-			cached_fw_config = val;
-	}
-	return cached_fw_config;
-}
-
-/*
- * get_cbi_ec_cfg_usb_db() will return the DB option number.
- */
-enum ec_cfg_usb_db_type ec_config_get_usb_db(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK)
-			>> EC_CFG_USB_DB_L);
-}
-
-/*
- * get_cbi_ec_cfg_usb_mb() will return the MB option number.
- */
-enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK)
-			>> EC_CFG_USB_MB_L);
-}
-
-/*
- * ec_config_has_lid_accel_sensor() will return ec_cfg_lid_accel_sensor_type
- */
-enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK)
-			>> EC_CFG_LID_ACCEL_SENSOR_L);
-}
-
-/*
- * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type
- */
-enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK)
-			>> EC_CFG_BASE_GYRO_SENSOR_L);
-}
-
-/*
- * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0
- */
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK)
-			>> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L);
-}
-
-/*
- * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0
- */
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK)
-			>> EC_CFG_LID_ANGLE_TABLET_MODE_L);
-}
-
-/*
- * ec_config_lte_present() will return 1 if present else 0.
- */
-enum ec_cfg_lte_present_type ec_config_lte_present(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK)
-			>> EC_CFG_LTE_PRESENT_L);
-}
-
-/*
- * ec_config_keyboard_layout() will return keyboard layout type.
- */
-enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void)
-{
-	return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK)
-			>> EC_CFG_KEYBOARD_LAYOUT_L);
-}
diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h
deleted file mode 100644
index 4888298e3a..0000000000
--- a/baseboard/zork/cbi_ec_fw_config.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _ZORK_CBI_EC_FW_CONFIG__H_
-#define _ZORK_CBI_EC_FW_CONFIG__H_
-
-/****************************************************************************
- * CBI Zork EC FW Configuration
- */
-#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF
-
-/*
- * USB Daughter Board (4 bits)
- *
- * get_cbi_ec_cfg_usb_db() will return the DB option number.
- * The option number will be defined in a variant or board level enumeration
- */
-#define EC_CFG_USB_DB_L				0
-#define EC_CFG_USB_DB_H				3
-#define EC_CFG_USB_DB_MASK \
-				GENMASK(EC_CFG_USB_DB_H,\
-					EC_CFG_USB_DB_L)
-
-/*
- * USB Main Board (4 bits)
- *
- * get_cbi_ec_cfg_usb_mb() will return the MB option number.
- * The option number will be defined in a variant or board level enumeration
- */
-#define EC_CFG_USB_MB_L				4
-#define EC_CFG_USB_MB_H				7
-#define EC_CFG_USB_MB_MASK \
-				GENMASK(EC_CFG_USB_MB_H,\
-					EC_CFG_USB_MB_L)
-
-/*
- * Lid Accelerometer Sensor (3 bits)
- *
- * ec_config_has_lid_accel_sensor() will return ec_cfg_lid_accel_sensor_type
- */
-enum ec_cfg_lid_accel_sensor_type {
-	LID_ACCEL_NONE = 0,
-	LID_ACCEL_KX022 = 1,
-	LID_ACCEL_LIS2DWL = 2,
-};
-#define EC_CFG_LID_ACCEL_SENSOR_L		8
-#define EC_CFG_LID_ACCEL_SENSOR_H		10
-#define EC_CFG_LID_ACCEL_SENSOR_MASK	\
-				GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\
-					EC_CFG_LID_ACCEL_SENSOR_L)
-
-/*
- * Base Gyro Sensor (3 bits)
- *
- * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type
- */
-enum ec_cfg_base_gyro_sensor_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_LSM6DSM = 2,
-	BASE_GYRO_ICM426XX = 3,
-};
-#define EC_CFG_BASE_GYRO_SENSOR_L		11
-#define EC_CFG_BASE_GYRO_SENSOR_H		13
-#define EC_CFG_BASE_GYRO_SENSOR_MASK	\
-				GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\
-					EC_CFG_BASE_GYRO_SENSOR_L)
-
-/*
- * PWM Keyboard Backlight (1 bit)
- *
- * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0
- */
-enum ec_cfg_pwm_keyboard_backlight_type {
-	PWM_KEYBOARD_BACKLIGHT_NO = 0,
-	PWM_KEYBOARD_BACKLIGHT_YES = 1,
-};
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \
-				GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\
-					EC_CFG_PWM_KEYBOARD_BACKLIGHT_L)
-
-/*
- * Lid Angle Tablet Mode (1 bit)
- *
- * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0
- */
-enum ec_cfg_lid_angle_tablet_mode_type {
-	LID_ANGLE_TABLET_MODE_NO = 0,
-	LID_ANGLE_TABLET_MODE_YES = 1,
-};
-#define EC_CFG_LID_ANGLE_TABLET_MODE_L		15
-#define EC_CFG_LID_ANGLE_TABLET_MODE_H		15
-#define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \
-				GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\
-					EC_CFG_LID_ANGLE_TABLET_MODE_L)
-
-/*
- * LTE Modem Present (1 bit)
- *
- * ec_config_lte_present() will return 1 if present else 0.
- */
-enum ec_cfg_lte_present_type {
-	LTE_NONE = 0,
-	LTE_PRESENT = 1,
-};
-#define EC_CFG_LTE_PRESENT_L		29
-#define EC_CFG_LTE_PRESENT_H		29
-#define EC_CFG_LTE_PRESENT_MASK \
-				GENMASK(EC_CFG_LTE_PRESENT_H,\
-					EC_CFG_LTE_PRESENT_L)
-
-/*
- * Keyboard Layout (2 bit)
- *
- * ec_config_keyboard_layout() will return keyboard layout type.
- */
-enum ec_cfg_keyboard_layout_type {
-	KB_LAYOUT_DEFAULT = 0,
-	KB_LAYOUT_1 = 1,
-};
-#define EC_CFG_KEYBOARD_LAYOUT_L		30
-#define EC_CFG_KEYBOARD_LAYOUT_H		31
-#define EC_CFG_KEYBOARD_LAYOUT_MASK \
-				GENMASK(EC_CFG_KEYBOARD_LAYOUT_H,\
-					EC_CFG_KEYBOARD_LAYOUT_L)
-
-
-uint32_t get_cbi_fw_config(void);
-enum ec_cfg_usb_db_type ec_config_get_usb_db(void);
-enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void);
-enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void);
-enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void);
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void);
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void);
-enum ec_cfg_lte_present_type ec_config_lte_present(void);
-enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void);
-
-#endif /* _ZORK_CBI_EC_FW_CONFIG__H_ */
diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c
deleted file mode 100644
index 1078ec6486..0000000000
--- a/baseboard/zork/cbi_ssfc.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static uint32_t cached_ssfc;
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (cached_ssfc & SSFC_BASE_GYRO_MASK) >> SSFC_BASE_GYRO_OFFSET;
-}
-
-enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void)
-{
-	return (cached_ssfc & SSFC_SPKR_AUTO_MODE_MASK) >>
-	       SSFC_SPKR_AUTO_MODE_OFFSET;
-}
-
-enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void)
-{
-	return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >>
-		SSFC_EDP_PHY_ALT_TUNING_OFFSET;
-}
-
-enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void)
-{
-	return (cached_ssfc & SSFC_C1_MUX_MASK) >>
-		SSFC_C1_MUX_OFFSET;
-}
diff --git a/baseboard/zork/cbi_ssfc.h b/baseboard/zork/cbi_ssfc.h
deleted file mode 100644
index c51d612a06..0000000000
--- a/baseboard/zork/cbi_ssfc.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _ZORK_CBI_SSFC__H_
-#define _ZORK_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Zork CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_gyro_sensor {
-	SSFC_BASE_GYRO_NONE = 0,
-	SSFC_BASE_GYRO_BMI160 = 1,
-	SSFC_BASE_GYRO_LSM6DSM = 2,
-	SSFC_BASE_GYRO_ICM426XX = 3,
-};
-#define SSFC_BASE_GYRO_OFFSET 0
-#define SSFC_BASE_GYRO_MASK GENMASK(2, 0)
-
-enum ec_ssfc_spkr_auto_mode {
-	SSFC_SPKR_AUTO_MODE_OFF = 0,
-	SSFC_SPKR_AUTO_MODE_ON = 1,
-};
-#define SSFC_SPKR_AUTO_MODE_OFFSET 3
-#define SSFC_SPKR_AUTO_MODE_MASK GENMASK(3, 3)
-
-/*
- * eDP PHY Alternate Tuning (Bits 4-5)
- */
-enum ec_ssfc_edp_phy_alt_tuning {
-	SSFC_EDP_PHY_ALT_TUNING_0 = 0,
-	SSFC_EDP_PHY_ALT_TUNING_1 = 1,
-	SSFC_EDP_PHY_ALT_TUNING_2 = 2,
-	SSFC_EDP_PHY_ALT_TUNING_3 = 3,
-};
-#define SSFC_EDP_PHY_ALT_TUNING_OFFSET 4
-#define SSFC_EDP_PHY_ALT_TUNING_MASK GENMASK(5, 4)
-
-/*
- * TypeC port 1 secondary MUX (Bits 6-7)
- */
-enum ec_ssfc_c1_mux {
-	SSFC_C1_MUX_NONE = 0,
-	SSFC_C1_MUX_TUSB544 = 1,
-	SSFC_C1_MUX_PS8818 = 2,
-};
-#define SSFC_C1_MUX_OFFSET 6
-#define SSFC_C1_MUX_MASK GENMASK(7, 6)
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get whether speaker amp auto mode is enabled from SSFC.
- */
-enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void);
-
-/**
- * Get the eDP PHY alternate tuning from SSFC.
- */
-enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void);
-
-/**
- * Get the C1 usb mux from SSFC.
- */
-enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void);
-
-#endif /* _ZORK_CBI_SSFC__H_ */
diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c
deleted file mode 100644
index 8dcdfa7635..0000000000
--- a/baseboard/zork/usb_pd_policy.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Zork boards */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since 5V rail is off */
-	return gpio_get_level(GPIO_S5_PGOOD);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Don't need to shutoff VBus if we are not sourcing it */
-	if (ppc_is_sourcing_vbus(port)) {
-		/* Disable VBUS. */
-		ppc_vbus_source_enable(port, 0);
-
-		/* Enable discharge if we were previously sourcing 5V */
-		if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-			pd_set_vbus_discharge(port, 1);
-	}
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-		pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c
deleted file mode 100644
index 10058bb8bc..0000000000
--- a/baseboard/zork/variant_dalboz.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/charger/isl9241.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "power.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-	case TEMP_SENSOR_SOC:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		/* adc power not ready when transition to S5 */
-		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_SOC;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_SOC,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-__overridable struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		}
-	},
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		}
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		}
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
-		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
-		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
-	},
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_POWER_SCL,
-		.sda = GPIO_EC_I2C_POWER_SDA,
-	},
-	{
-		.name = "ap_mux",
-		.port = I2C_PORT_USB_AP_MUX,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USBC_AP_MUX_SCL,
-		.sda = GPIO_EC_I2C_USBC_AP_MUX_SDA,
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl = GPIO_FCH_SIC,
-		.sda = GPIO_FCH_SID,
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_CBI_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_CBI_SDA,
-	},
-	{
-		.name = "ap_audio",
-		.port = I2C_PORT_AP_AUDIO,
-		.kbps = 400,
-		.scl = GPIO_I2C_AUDIO_USB_HUB_SCL,
-		.sda = GPIO_I2C_AUDIO_USB_HUB_SDA,
-	},
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY_V1,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BATT_SCL,
-		.sda = GPIO_EC_I2C_BATT_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*****************************************************************************
- * Charger
- */
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c
deleted file mode 100644
index b39380db59..0000000000
--- a/baseboard/zork/variant_trembyle.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl9241.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/ps8802.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
-		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
-		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
-	},
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BATT_SCL,
-		.sda = GPIO_EC_I2C_BATT_SDA,
-	},
-	{
-		.name = "ap_mux",
-		.port = I2C_PORT_USB_AP_MUX,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USBC_AP_MUX_SCL,
-		.sda = GPIO_EC_I2C_USBC_AP_MUX_SDA,
-	},
-	{
-		.name = "therm_chg",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl = GPIO_FCH_SIC_POWER_SCL,
-		.sda = GPIO_FCH_SID_POWER_SDA,
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_CBI_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_CBI_SDA,
-	},
-	{
-		.name = "ap_audio",
-		.port = I2C_PORT_AP_AUDIO,
-		.kbps = 400,
-		.scl = GPIO_FCH_I2C_AUDIO_SCL,
-		.sda = GPIO_FCH_I2C_AUDIO_SDA,
-	},
-	{
-		.name = "ap_hdmi",
-		.port = I2C_PORT_AP_HDMI,
-		.kbps = 400,
-		.scl = GPIO_FCH_I2C_HDMI_HUB_3V3_SCL,
-		.sda = GPIO_FCH_I2C_HDMI_HUB_3V3_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*****************************************************************************
- * Charger
- */
-
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER_V1,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-/*****************************************************************************
- * TCPC
- */
-
-void baseboard_tcpc_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-__overridable void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	case USBC_PORT_C1:
-		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/*****************************************************************************
- * IO expander
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[USBC_PORT_C0] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
-
-/*****************************************************************************
- * Custom Zork USB-C1 Retimer/MUX driver
- */
-
-/*
- * PS8802 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- */
-static int board_ps8802_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* Make sure the PS8802 is awake */
-	rv = ps8802_i2c_wake(me);
-	if (rv)
-		return rv;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-	}
-
-	return rv;
-}
-
-/*
- * PS8818 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- */
-static int board_ps8818_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					ZORK_PS8818_RX_INPUT_TERM);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	} else {
-		/* Disable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
-	}
-
-	return rv;
-}
-
-const struct usb_mux usbc1_ps8802 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
-	.driver = &ps8802_usb_mux_driver,
-	.board_set = &board_ps8802_mux_set,
-};
-const struct usb_mux usbc1_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_ps8818_mux_set,
-};
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-};
-
-/*
- * USB-C1 HPD may go through an IO expander, so we must use a custom HPD GPIO
- * control function with CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM.
- *
- * TODO(b/165622386) revert to non-custom GPIO control when HPD is no longer on
- * the IO expander in any variants.
- */
-void svdm_set_hpd_gpio(int port, int en)
-{
-	gpio_or_ioex_set_level(PORT_TO_HPD(port), en);
-}
-
-int svdm_get_hpd_gpio(int port)
-{
-	int out;
-
-	if (gpio_or_ioex_get_level(PORT_TO_HPD(port), &out) != EC_SUCCESS) {
-		ccprints("Failed to read current HPD for port C%d", port);
-		return 0;
-	}
-	return out;
-}
diff --git a/board/adlrvpm_ite/board.c b/board/adlrvpm_ite/board.c
deleted file mode 120000
index ea1b98c873..0000000000
--- a/board/adlrvpm_ite/board.c
+++ /dev/null
@@ -1 +0,0 @@
-../adlrvpp_ite/board.c
\ No newline at end of file
diff --git a/board/adlrvpm_ite/board.h b/board/adlrvpm_ite/board.h
deleted file mode 120000
index 2c75a3883c..0000000000
--- a/board/adlrvpm_ite/board.h
+++ /dev/null
@@ -1 +0,0 @@
-../adlrvpp_ite/board.h
\ No newline at end of file
diff --git a/board/adlrvpm_ite/build.mk b/board/adlrvpm_ite/build.mk
deleted file mode 120000
index ceffb75d7e..0000000000
--- a/board/adlrvpm_ite/build.mk
+++ /dev/null
@@ -1 +0,0 @@
-../adlrvpp_ite/build.mk
\ No newline at end of file
diff --git a/board/adlrvpm_ite/ec.tasklist b/board/adlrvpm_ite/ec.tasklist
deleted file mode 100644
index d593fbbf5f..0000000000
--- a/board/adlrvpm_ite/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-M-RVP-ITE board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpm_ite/gpio.inc b/board/adlrvpm_ite/gpio.inc
deleted file mode 120000
index 23611687c6..0000000000
--- a/board/adlrvpm_ite/gpio.inc
+++ /dev/null
@@ -1 +0,0 @@
-../adlrvpp_ite/gpio.inc
\ No newline at end of file
diff --git a/board/adlrvpm_ite/vif_override.xml b/board/adlrvpm_ite/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpm_ite/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
deleted file mode 100644
index 835cdcb986..0000000000
--- a/board/adlrvpp_ite/board.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-ITE board-specific configuration */
-#include "button.h"
-#include "fan.h"
-#include "fusb302.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "it83xx_pd.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	[I2C_CHAN_FLASH] = {
-		.name = "ec_flash",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_PROG_SCL,
-		.sda = GPIO_EC_I2C_PROG_SDA,
-	},
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_SMB_BS_CLK,
-		.sda = GPIO_SMB_BS_DATA,
-	},
-	[I2C_CHAN_TYPEC_0] = {
-		.name = "typec_0",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
-	},
-	[I2C_CHAN_TYPEC_1] = {
-		.name = "typec_1",
-		.port = IT83XX_I2C_CH_F,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[I2C_CHAN_TYPEC_2] = {
-		.name = "typec_2",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
-	},
-	[I2C_CHAN_TYPEC_3] = {
-		.name = "typec_3",
-		.port = IT83XX_I2C_CH_D,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_1,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_2,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_3,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
deleted file mode 100644
index a5f5c445ad..0000000000
--- a/board/adlrvpp_ite/board.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-ITE board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_IT8320
-
-#include "adlrvp.h"
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL_EC
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW_EC
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE_EC
-#define GPIO_PCH_WAKE_L			GPIO_PCH_WAKE_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_EC
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_EC
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_R_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD_EC
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL_EC
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC_R
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_R
-#define GPIO_UART1_RX			GPIO_UART_SERVO_TX_EC_RX
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET_EC
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L_EC
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L_EC
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD_EC
-#define GPIO_PCH_DSW_PWROK		GPIO_DSW_PWROK_EC
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GMR_TABLET_MODE_GPIO_L		GPIO_SLATE_MODE_INDICATION
-
-/* I2C ports & Configs */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
-
-/* Battery */
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
-
-/* Port 80 */
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0		IT83XX_I2C_CH_C
-#define I2C_PORT_TYPEC_1		IT83XX_I2C_CH_F
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2		IT83XX_I2C_CH_E
-#define I2C_PORT_TYPEC_3		IT83XX_I2C_CH_D
-#endif
-
-/* TCPC */
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-
-/* Config Fan */
-#define GPIO_FAN_POWER_EN	GPIO_EC_THRM_SEN_PWRGATE_N
-#define GPIO_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD_EC
-
-/* Increase EC speed */
-#undef PLL_CLOCK
-#define PLL_CLOCK	96000000
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
-	I2C_CHAN_FLASH,
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_TYPEC_0,
-	I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
-	I2C_CHAN_TYPEC_2,
-	I2C_CHAN_TYPEC_3,
-#endif
-	I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk
deleted file mode 100644
index fe5f548324..0000000000
--- a/board/adlrvpp_ite/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-ITE board-specific configuration
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist
deleted file mode 100644
index 5cb10b2907..0000000000
--- a/board/adlrvpp_ite/ec.tasklist
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-ITE board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
deleted file mode 100644
index f4db15c4d5..0000000000
--- a/board/adlrvpp_ite/gpio.inc
+++ /dev/null
@@ -1,202 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-ITE board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD_EC,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_EC,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N,		PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3_EC,	PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCST_PWRGD,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PM_SLP_SUS_EC, 	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_R_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_R_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP,		PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC_R,		PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID,		PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(EC_WP_ODL,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, 	PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-
-GPIO_INT(BC_ACOK_EC,		PIN(K, 3), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-GPIO_INT(UART_SERVO_TX_EC_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)
-
-/* USB-C interrupts */
-/* Using embedded TCPC for Port-0 */
-UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
-GPIO(NC_USBC_TCPC_ALRT_P0,	PIN(I, 7), GPIO_INPUT)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_FALLING, ppc_interrupt)
-
-#if defined(HAS_TASK_PD_C1)
-GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(G, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P1,		PIN(G, 0), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P1,	PIN(C, 4), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(J, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P2,		PIN(J, 1), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(E, 5), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C3)
-GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(J, 3), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INT_FALLING, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P3,		PIN(J, 3), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(E, 6), GPIO_INPUT)
-#endif
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INPUT)
-#endif
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-/* Sensor Interrupts */
-GPIO_INT(SLATE_MODE_INDICATION,	PIN(K, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL_EC,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PROCHOT_EC,		PIN(C, 0), GPIO_INPUT)
-GPIO(PM_RSMRST_EC,		PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N_EC,		PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N,		PIN(I, 2), GPIO_OUT_LOW)
-
-GPIO(EC_PCH_MKBP_INT_ODL_EC,	PIN(B, 7), GPIO_ODR_HIGH)
-GPIO(EDP_BKLT_EN,		PIN(J, 6), GPIO_OUT_HIGH)
-GPIO(EC_DS3,			PIN(L, 4), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(PCH_PWROK_EC_R,	PIN(K, 4), GPIO_INPUT)
-GPIO(SYS_PWROK_EC,	PIN(D, 1), GPIO_OUT_LOW)
-GPIO(DSW_PWROK_EC,	PIN(L, 6), GPIO_OUT_LOW)
-
-/* Host communication GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PLT_RST_L, 	PIN(H, 6), GPIO_INPUT | GPIO_PULL_UP) /* PCH_PLTRST_L */
-#endif
-GPIO(PCH_WAKE_N,	PIN(J, 0), GPIO_ODR_HIGH)
-
-/* Battery present */
-GPIO(BAT_DET_EC,	PIN(K, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L_EC,	PIN(A, 6), GPIO_OUT_HIGH)	/* BAT_LED_GREEN_L LED_2_L */
-GPIO(LED_2_L_EC,	PIN(A, 7), GPIO_OUT_HIGH)	/* AC_LED_GREEN_L LED_1_L */
-
-/* H1 pins */
-GPIO(EC_H1_PACKET_MODE_EC,	PIN(J, 4), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW_EC,		PIN(K, 7), GPIO_OUT_LOW)
-
-/* Case Closed Debug Mode */
-GPIO_INT(CCD_MODE_ODL,	PIN(B, 5), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* FAN control pins */
-GPIO(EC_THRM_SEN_PWRGATE_N,	PIN(K, 6), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(EC_I2C_PROG_SCL,		PIN(B, 3), GPIO_INPUT)	/* I2C_A_SCL */
-GPIO(EC_I2C_PROG_SDA,		PIN(B, 4), GPIO_INPUT)	/* I2C_A_SDA */
-GPIO(SMB_BS_CLK,		PIN(C, 1), GPIO_INPUT)	/* I2C_B_SCL */
-GPIO(SMB_BS_DATA,		PIN(C, 2), GPIO_INPUT)	/* I2C_B_SDA */
-
-/* P0 IT83XX_I2C_CH_C */
-GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(C, 7), GPIO_INPUT)	/* I2C_C_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(F, 7), GPIO_INPUT)	/* I2C_C_SDA */
-
-/* P1 IT83XX_I2C_CH_F */
-GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(A, 4), GPIO_INPUT)	/* I2C_F_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(A, 5), GPIO_INPUT)	/* I2C_F_SDA */
-
-/* P2 IT83XX_I2C_CH_E */
-GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(E, 0), GPIO_INPUT)	/* I2C_E_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(E, 7), GPIO_INPUT)	/* I2C_E_SDA */
-
-/* P3 IT83XX_I2C_CH_D */
-GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(H, 1), GPIO_INPUT)	/* I2C_D_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(H, 2), GPIO_INPUT)	/* I2C_D_SDA */
-
-/* Unused 1.8V or 3.3V compatiable pins */
-GPIO(TP_DEVELOPER_MODE_EC,	PIN(B, 2), GPIO_INPUT)
-GPIO(ESPI_CS1_N_R,		PIN(D, 3), GPIO_INPUT)
-GPIO(SUSWARN,			PIN(E, 1), GPIO_INPUT)
-GPIO(CPU_C10_GATE,		PIN(G, 1), GPIO_INPUT)
-GPIO(TP_GPIO_G2,		PIN(G, 2), GPIO_INPUT)
-GPIO(TP_GPIO_G6,		PIN(G, 6), GPIO_INPUT)
-GPIO(BATT_DISABLE_EC,		PIN(H, 0), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC,		PIN(H, 5), GPIO_INPUT)
-GPIO(SLP_S0_CS_EC,		PIN(I, 0), GPIO_INPUT)
-GPIO(SMC_SHUTDOWN,		PIN(K, 5), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC,		PIN(L, 1), GPIO_INPUT)
-GPIO(SMC_ONOFF_N,		PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(STD_ADPT_CNTRL_EC,		PIN(L, 5), GPIO_INPUT)
-GPIO(SMB_PCH_ALRT,		PIN(L, 7), GPIO_INPUT)
-GPIO(ESPI_ALERT0_R,		PIN(M, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Unused 3.3V compatiable pins */
-GPIO(TP_GPIO_A0,		PIN(A, 0), GPIO_INPUT)
-GPIO(TP_GPIO_A1,		PIN(A, 1), GPIO_INPUT)
-GPIO(TP_GPIO_A3,		PIN(A, 3), GPIO_INPUT)
-GPIO(TP_GPC3,			PIN(C, 3), GPIO_INPUT)
-GPIO(TP_GPC5,			PIN(C, 5), GPIO_INPUT)
-GPIO(TP_GPIO_E3,		PIN(E, 3), GPIO_INPUT)
-GPIO(TP_GPIO_H3,		PIN(H, 3), GPIO_INPUT)
-GPIO(TP_GPIO_H4,		PIN(H, 4), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)		/* I2C C SDA F7 */
-ALTERNATE(PIN_MASK(H, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C D SCL/SDA H1/H2 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) 	/* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)		/* TACH1A D7 */
diff --git a/board/adlrvpp_ite/vif_override.xml b/board/adlrvpp_ite/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_ite/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/adlrvpp_mchp1521/board.c b/board/adlrvpp_mchp1521/board.c
deleted file mode 100644
index 3e676a1c6c..0000000000
--- a/board/adlrvpp_mchp1521/board.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
-
-#include "button.h"
-#include "fan.h"
-#include "fusb302.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	/*
-	 * Port-80 Display, Charger, Battery, IO-expander, EEPROM,
-	 * ISH sensor, AUX-rail, power-monitor.
-	 */
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl = GPIO_SMB_BS_CLK,
-		.sda = GPIO_SMB_BS_DATA,
-	},
-	[I2C_CHAN_TCPC_0] = {
-		.name = "typec_0",
-		.port = I2C_PORT_TYPEC_0,
-		.kbps = 400,
-		.scl = GPIO_TYPEC_EC_SMBUS1_CLK_EC,
-		.sda = GPIO_TYPEC_EC_SMBUS1_DATA_EC,
-	},
-	[I2C_CHAN_TCPC_1] = {
-		.name = "typec_1",
-		.port = I2C_PORT_TYPEC_1,
-		.kbps = 400,
-		.scl = GPIO_TYPEC_EC_SMBUS3_CLK,
-		.sda = GPIO_TYPEC_EC_SMBUS3_DATA,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_0,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_1,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h
deleted file mode 100644
index 1d3cb4828f..0000000000
--- a/board/adlrvpp_mchp1521/board.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Microchip EC variant */
-#define VARIANT_INTELRVP_EC_MCHP
-
-/* UART for EC console */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-#include "adlrvp.h"
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-/* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_PCH_SPI_OE_N
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD_EC_N
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC_N
-#define GPIO_PCH_SLP_S0_L		GPIO_PM_SLP_S0_R_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_EC_TRACE_DATA_2
-#define GPIO_VCCST_PWRGD		GPIO_EC_TRACE_DATA_3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_N
-#define GPIO_SYS_RESET_L		GPIO_DG2_PRESENT
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_R
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_R
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3_R
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK_EC_R
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_TRACE_DATA_1
-
-/* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOL_UP_EC
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DOWN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_PWRBTN_EC_IN_N
-
-/* Sensors */
-#define GMR_TABLET_MODE_GPIO_L		GPIO_EC_SLATEMODE_HALLOUT_SNSR_R
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_R
-
-/* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT_EC
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC_IN
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BATT_ID_R
-
-/* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_EC_R_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N
-#define GPIO_EC_INT_L			GPIO_EC_TRACE_DATA_0
-
-/* H1 */
-#define GPIO_WP_L			GPIO_EC_WAKE_CLK_R
-#define GPIO_PACKET_MODE_EN		GPIO_EC_TRACE_CLK
-#define GPIO_ENTERING_RW		GPIO_DNX_FORCE_RELOAD_EC_R
-
-/* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_FAN_PWR_DISABLE
-
-/* LEDs */
-#define GPIO_BAT_LED_RED_L		GPIO_PM_BAT_STATUS_LED2
-#define GPIO_PWR_LED_WHITE_L		GPIO_PM_PWRBTN_LED
-
-/* Uart */
-#define GPIO_UART2_RX			GPIO_EC_UART_RX
-
-/* Case Closed Debug Mode interrupt */
-#define GPIO_CCD_MODE_ODL		GPIO_KBC_NUMLOCK
-
-/* USB-C interrupts */
-#define GPIO_USBC_TCPC_ALRT_P0		GPIO_TYPEC_EC_SMBUS_ALERT_0_R
-#define GPIO_USBC_TCPC_ALRT_P1		GPIO_TYPEC_EC_SMBUS_ALERT_1_R
-#define GPIO_USBC_TCPC_PPC_ALRT_P0	GPIO_KBC_SCANOUT_15
-#define GPIO_USBC_TCPC_PPC_ALRT_P1	GPIO_KBC_CAPSLOCK
-
-
-/* I2C ports & Configs */
-/* Charger */
-#define I2C_PORT_CHARGER		MCHP_I2C_PORT0
-/* Port 80 */
-#define I2C_PORT_PORT80			MCHP_I2C_PORT0
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
-/* Battery */
-#define I2C_PORT_BATTERY		MCHP_I2C_PORT0
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0		MCHP_I2C_PORT1
-#define I2C_PORT_TYPEC_1		MCHP_I2C_PORT5
-
-/*
- * MEC1521H loads firmware using QMSPI controller
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-
-/*
- * ADLRVP uses 32MB SPI flash- W25R256JVEIQ.But, EC binary to be generated
- * is of size 512KB. This bin is then later appended with 0xFF to become 32MB
- * binary for flashing purpose.
- */
-#define CONFIG_FLASH_SIZE_BYTES	(512 * 1024)
-#define CONFIG_SPI_FLASH_W25X40	/* TODO: change to W25R256 */
-
-/* ADC channels */
-/*
- * Undefining below and redefining based on ADL RVP schematics,
- * as they are already defined with different channels in mchp_ec.h.
- */
-#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
-#undef ADC_TEMP_SNS_VR_CHANNEL
-#undef ADC_TEMP_SNS_DDR_CHANNEL
-#undef ADC_TEMP_SNS_SKIN_CHANNEL
-
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH5
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH7
-
-/* To do: Remove once fan register details are added in mchp/fan.c */
-#undef CONFIG_FANS
-
-/* Use internal silicon 32KHz oscillator */
-#undef CONFIG_CLOCK_SRC_EXTERNAL
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_TCPC_0,
-	I2C_CHAN_TCPC_1,
-	I2C_CHAN_COUNT,
-};
-
-/* Map I2C port to controller */
-int board_i2c_p2c(int port);
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1521/build.mk b/board/adlrvpp_mchp1521/build.mk
deleted file mode 100644
index b53a3bb479..0000000000
--- a/board/adlrvpp_mchp1521/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration
-#
-
-# the IC is Microchip MEC1521 with SRAM of 256KB
-# external SPI is 32MB
-# external clock is crystal
-CHIP:=mchp
-CHIP_FAMILY:=mec152x
-CHIP_VARIANT:=mec1521
-CHIP_SPI_SIZE_KB:=512
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_mchp1521/ec.tasklist b/board/adlrvpp_mchp1521/ec.tasklist
deleted file mode 100644
index bf4660ce03..0000000000
--- a/board/adlrvpp_mchp1521/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1521/gpio.inc b/board/adlrvpp_mchp1521/gpio.inc
deleted file mode 100644
index fd20e16568..0000000000
--- a/board/adlrvpp_mchp1521/gpio.inc
+++ /dev/null
@@ -1,314 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration. */
-
-/*
- * MEC152X data sheets GPIO numbers are OCTAL.
- */
-
-/*
- * MEC1521H-SZ MECC board SPI flash is connected to MEC1521H-SZ shared SPI port.
- * GPIO055/SHD_CS0# pin is used to determine the boot source (eSPI Flash channel
- * or shared SPI). On RVP, SHD_CS0_N is connected to Flash0 and SHD_CS1_N is
- * connected to Flash1. Based on RVP design, Flash1 is meant for EC & Flash0
- * for Coreboot.But, for MEC, it is mandatory to route CS0 to external Flash
- * for EC to boot load the image. Hence, necessary rework must be taken care to
- * route CS0 to external Flash1.
- */
-/* Include common gpios needed for LFW loader and main process FW */
-#include "chip/mchp/lfw/gpio.inc"
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-
-/* As all signal names used here are supposed to match the schematic,
- * few pin names may not indicate the real purpose.Refer comments to clarify the pin usage.
- * Such pins are further renamed in board.h.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD,		PIN(057),	GPIO_INT_BOTH,	power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_EC_N,	PIN(012),	GPIO_INT_BOTH,	power_signal_interrupt)
-GPIO_INT(PM_SLP_S0_R_N,		PIN(0243),	GPIO_INT_BOTH,	power_signal_interrupt)
-/* Below meaningless pin names are to match the schematic.*/
-/* PG_EC_DSW_PWROK signal */
-GPIO_INT(EC_TRACE_DATA_2,	PIN(0202),	GPIO_INT_BOTH,	power_signal_interrupt)
-/* VCCST_PWRGD signal */
-GPIO_INT(EC_TRACE_DATA_3,	PIN(0203),	GPIO_INT_BOTH,	power_signal_interrupt)
-GPIO_INT(PM_SLP_SUS_N,		PIN(000),	GPIO_INT_BOTH,	power_signal_interrupt)
-
-/* Button interrupts */
-GPIO_INT(VOL_UP_EC,		PIN(0242),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOL_DOWN_EC,		PIN(0246),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(SMC_LID,		PIN(033),	GPIO_INT_BOTH | GPIO_PULL_UP,	lid_interrupt)
-/* Buffered power button input from
- * PMIC-SLG7NT4192VTR / PWRBTN_EC_SILEGO_OUTPUT */
-GPIO_INT(PWRBTN_EC_IN_N,	PIN(0163),	GPIO_INT_BOTH,	power_button_interrupt)
-
-/* DC Jack presence coming from +VADP_OUT */
-/* DC_JACK_PRESENT */
-GPIO_INT(STD_ADP_PRSNT_EC,	PIN(052),	GPIO_INT_BOTH,	board_dc_jack_interrupt)
-/* AC Present */
-GPIO_INT(BC_ACOK_EC_IN,		PIN(0172),	GPIO_INT_BOTH,	extpower_interrupt)
-
-/* H1 */
-/* WP_L interrupt pin */
-GPIO_INT(EC_WAKE_CLK_R,		PIN(0241),	GPIO_INT_BOTH,	switch_interrupt)
-
-/* Case Closed Debug Mode */
-/* CCD_MODE_ODL pin */
-GPIO_INT(KBC_NUMLOCK,		PIN(0255),	GPIO_INT_BOTH,	board_connect_c0_sbu)
-
-/* USB-C interrupts */
-/* Below meaningless pin names are to match the schematic */
-/* TCPC & PPC Alerts */
-/* USBC_TCPC_ALRT_P0 */
-GPIO_INT(TYPEC_EC_SMBUS_ALERT_0_R,	PIN(0132),	GPIO_INT_BOTH,	tcpc_alert_event)
-/* USBC_TCPC_ALRT_P1 */
-GPIO_INT(TYPEC_EC_SMBUS_ALERT_1_R,	PIN(0245),	GPIO_INT_BOTH,	tcpc_alert_event)
-/* USBC_TCPC_PPC_ALRT_P0 */
-GPIO_INT(KBC_SCANOUT_15,	PIN(0151),	GPIO_INT_BOTH,	ppc_interrupt)
-/* USBC_TCPC_PPC_ALRT_P1 */
-GPIO_INT(KBC_CAPSLOCK,		PIN(0127),	GPIO_INT_BOTH,	ppc_interrupt)
-
-/* Sensor Interrupts */
-/* GMR_TABLET_MODE_GPIO_L */
-GPIO_INT(EC_SLATEMODE_HALLOUT_SNSR_R,	PIN(064),	GPIO_INT_BOTH |
-					GPIO_SEL_1P8V,	gmr_tablet_switch_isr)
-
-/* UART Interrupt */
-GPIO_INT(EC_UART_RX,	PIN(0145),	GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP,
-						uart_deepsleep_interrupt)
-
-/* Power sequencing GPIOs */
-GPIO(PM_RSMRST_R,	PIN(054),	GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N_R,	PIN(0101),	GPIO_ODR_HIGH)
-GPIO(EC_PCH_SPI_OE_N,	PIN(024),	GPIO_OUT_LOW)
-GPIO(SYS_PWROK_EC_R,	PIN(043),	GPIO_OUT_LOW)
-/* Below names are meaningless to match schematic */
-/* PCH_DSW_PWROK */
-GPIO(EC_TRACE_DATA_1,	PIN(0201),	GPIO_OUT_LOW)
-/* SYS_RESET_L */
-GPIO(DG2_PRESENT,	PIN(0165),	GPIO_ODR_HIGH)
-/* EN_PP3300_A */
-GPIO(EC_DS3_R,		PIN(0226),	GPIO_OUT_LOW)
-/* PCH_PWROK_EC is an input, as it is driven by the Silego chip on RVP */
-GPIO(EC_PM_PCH_PWROK,	PIN(0106),	GPIO_INPUT)
-UNIMPLEMENTED(EN_PP5000)
-
-/* Host communication GPIOs */
-/* PCH_WAKE_L pin*/
-GPIO(SMC_WAKE_SCI_N,	PIN(0114),	GPIO_ODR_HIGH)
-/* EC_INT_L pin */
-GPIO(EC_TRACE_DATA_0,	PIN(0200),	GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(ESPI_RST_EC_R_N,	PIN(061),	GPIO_INPUT)
-#endif
-
-/* H1 Pins */
-/* PACKET_MODE_EN */
-GPIO(EC_TRACE_CLK,	PIN(0105),	GPIO_OUT_LOW)
-/* ENTERING_RW */
-GPIO(DNX_FORCE_RELOAD_EC_R,	PIN(0115),	GPIO_OUT_LOW)
-
-/* FAN control pins */
-GPIO(FAN_PWR_DISABLE,	PIN(060),	GPIO_OUT_LOW)
-
-/* EDP */
-GPIO(EC_EDP1_BKLT_EN,	PIN(0157),	GPIO_OUT_HIGH)
-
-/* LEDs */
-GPIO(PM_BAT_STATUS_LED2,	PIN(035),	GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_LED,		PIN(0254),	GPIO_OUT_LOW)
-
-/* Battery present */
-GPIO(BATT_ID_R,		PIN(0162),	GPIO_INPUT)
-
-/* VTR2 STRAP PIN - GPIO0104_UART0_TX
- * Voltage level strap used to determine,
- * if shared flash interface must be configured
- * for 3.3V or 1.8V.
- * 1 = 3.3V operation
- * 0 = 1.8V operation
- */
-GPIO(EC_VTR2_STRAP,	PIN(0104),	GPIO_INPUT)
-
-/* Tap Controller select strap - GPIO0170_UART1_TX
- * If any of the JTAG TAP controllers are used, GPIO170 must only
- * be configured as an output to a VTRx powered external function.
- * GPIO170 may only be configured as an input when
- * the JTAG TAP controllers are not needed or when an external driver
- * does not violate the Slave Select Timing.
- */
-GPIO(EC_JTAG_STRAP,	PIN(0170),	GPIO_ODR_HIGH)
-
-/* I2C pins */
-/* I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SMB_BS_CLK,		PIN(004),	GPIO_INPUT)
-GPIO(SMB_BS_DATA,		PIN(003),	GPIO_INPUT)
-GPIO(TYPEC_EC_SMBUS1_CLK_EC,	PIN(0131),	GPIO_INPUT)
-GPIO(TYPEC_EC_SMBUS1_DATA_EC,	PIN(0130),	GPIO_INPUT)
-GPIO(TYPEC_EC_SMBUS3_DATA,	PIN(0142),	GPIO_INPUT)
-GPIO(TYPEC_EC_SMBUS3_CLK,	PIN(0141),	GPIO_INPUT)
-
-/* Unused Pins */
-/* These have different meaning on RVP for alternate OS
- * support.Hence, keep them as input.
- */
-GPIO(PROCHOT_EC_R,		PIN(0253),	GPIO_INPUT)
-GPIO(BC_PROCHOT_EC_N,		PIN(034),	GPIO_INPUT)
-GPIO(EC_PEG_PLI_N_DG2,		PIN(036),	GPIO_INPUT)
-GPIO(PEG_PIM_DG2,		PIN(0240),	GPIO_INPUT)
-GPIO(KBD_BKLT_CTRL,		PIN(014),	GPIO_INPUT)
-GPIO(STD_ADPT_CNTRL_GPIO_R,	PIN(0171),	GPIO_INPUT)
-GPIO(SAF_G3_DETECT,		PIN(013),	GPIO_INPUT)
-GPIO(EC_GPIO015_PWM7,		PIN(015),	GPIO_INPUT)
-GPIO(EC_GPPC_B14,		PIN(0244),	GPIO_INPUT)
-GPIO(SX_EXIT_HOLDOFF_N,		PIN(0175),	GPIO_INPUT)
-GPIO(MIC_PRIVACY_EC,		PIN(0100),	GPIO_INPUT)
-GPIO(MIC_PRIVACY_SWITCH,	PIN(011),	GPIO_INPUT)
-GPIO(PECI_MUX_CTRL_ER_INT,	PIN(025),	GPIO_INPUT)
-GPIO(PEG_RTD3_COLD_MOD_SW_R,	PIN(0156),	GPIO_INPUT)
-GPIO(H_CATERR_EC_N,		PIN(0153),	GPIO_INPUT)
-GPIO(PM_BATLOW_N,		PIN(0140),	GPIO_INPUT)
-GPIO(HOME_BTN_EC_RVP_AEP_ID,	PIN(023),	GPIO_INPUT)
-GPIO(CPU_C10_GATE_N_R,		PIN(022),	GPIO_INPUT)
-GPIO(VREF_VTT,			PIN(044),	GPIO_INPUT)
-GPIO(HB_NVDC_SEL,		PIN(0161), 	GPIO_INPUT)
-GPIO(EC_VCI_OUT_WAKE_R,		PIN(0250),	GPIO_INPUT)
-GPIO(PM_SLP_S0_CS_N,		PIN(0221),	GPIO_INPUT)
-GPIO(GPPC_E7_EC_SMI_N_R,	PIN(0102),	GPIO_INPUT)
-GPIO(TC_RETIMER_FORCE_PWR_BTP_EC_R,	PIN(0222),	GPIO_INPUT)
-
-/* Alternate functions */
-
-/* Alternate functions GPIO definitions */
-
-/*
- * MCHP has 6 banks/ports each containing 32 GPIO's.
- * Each bank/port is connected to a GIRQ.
- * Port numbering Example:
- * GPIO_015 = 13 decimal. Port/bank = 13/32 = 0, bit = 13 % 32 = 13
- * GPIO_0123 = 83 decimal. Port/bank = 83/32 = 2, bit = 83 % 32 = 19
- * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
- */
-
-/*
- * Configure I2C as alternate function
- * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
- * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
- * I2C01_SDA = GPIO_0130(Bank=2, bit=24) Func1
- * I2C01_SCL = GPIO_0131(Bank=2, bit=25) Func1
- * I2C04_SDA = GPIO_0143(Bank=3, bit=3) Func1
- * I2C04_SCL = GPIO_0144(Bank=3, bit=4) Func1
- * I2C05_SDA = GPIO_0141(Bank=3, bit=1) Func1
- * I2C05_SDL = GPIO_0142(Bank=3, bit=2) Func1
- */
-ALTERNATE(PIN_MASK(0, 0x00000018),	GPIO_ALT_FUNC_1,	MODULE_I2C,
-								GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(2, 0x03000000),	GPIO_ALT_FUNC_1,	MODULE_I2C,
-								GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(3, 0x0000001E),	GPIO_ALT_FUNC_1,	MODULE_I2C,
-								GPIO_ODR_HIGH)
-
-/* Alternate pins for ADC */
-/*
- * ADC04 - ADC07
- * GPIO_0204 Func 1 = ADC04 - AMBIET_THERM_IN0
- * GPIO_0205 Func 1 = ADC05 - VR_THERM_IN
- * GPIO_0206 Func 1 = ADC06 - DDR_THERM_IN
- * GPIO_0207 Func 1 = ADC07 - SKIN_THERM_IN1
- * Bank 4 bits[4:5:6:7]
- */
-ALTERNATE(PIN_MASK(4, 0x00000F0),	GPIO_ALT_FUNC_1,	MODULE_ADC,
-								GPIO_ANALOG)
-/*
- * VREF2_ADC_R
- * GPIO_067 Func 1 = VREF2_ADC
- * Bank 1 bit [23]
- */
-ALTERNATE(PIN_MASK(1, 0x0800000),	GPIO_ALT_FUNC_1,	MODULE_ADC,
-								GPIO_ANALOG)
-
-/* Alternate pins for FAN */
-/*
- * GPIO_050 Func 1 = TACH0 - CPU_TACHO_FAN
- * GPIO_053 Func 1 = PWM0 - CPU_PWM_FAN
- * Bank 1 bits[8:11]
- */
-ALTERNATE(PIN_MASK(1, 0x0000900),	GPIO_ALT_FUNC_1,	MODULE_PWM,
-								GPIO_FLAG_NONE)
-
-/* KB pins */
-/*
- * MEC1521H-SZ (144 pin package)
- * KSO00 = GPIO_0040 Func2 bank 1 bit 0
- * KSO01 = GPIO_0045 Func1 bank 1 bit 5
- * KSO02 = GPIO_0046 Func1 bank 1 bit 6
- * KSO03 = GPIO_0047 Func1 bank 1 bit 7
- * KSO04 = GPIO_0107 Func2 bank 2 bit 7
- * KSO05 = GPIO_0112 Func1 bank 2 bit 10
- * KSO06 = GPIO_0113 Func1 bank 2 bit 11
- * KSO07 = GPIO_0120 Func1 bank 2 bit 16
- * KSO08 = GPIO_0121 Func2 bank 2 bit 17
- * KSO09 = GPIO_0122 Func2 bank 2 bit 18
- * KSO10 = GPIO_0123 Func2 bank 2 bit 19
- * KSO11 = GPIO_0124 Func2 bank 2 bit 20
- * KSO12 = GPIO_0125 Func2 bank 2 bit 21
- * For 8x16 test keyboard add KSO13 - KSO15
- * KSO13 = GPIO_0126 Func2 bank 2 bit 22
- * KSO14 = GPIO_0152 Func1 bank 3 bit 10
- * KSO15 = GPIO_0151 Func2 bank 3 bit 9
- *
- * KSI0 = GPIO_0017 Func1 bank 0 bit 15
- * KSI1 = GPIO_0020 Func1 bank 0 bit 16
- * KSI2 = GPIO_0021 Func1 bank 0 bit 17
- * KSI3 = GPIO_0026 Func1 bank 0 bit 22
- * KSI4 = GPIO_0027 Func1 bank 0 bit 23
- * KSI5 = GPIO_0030 Func1 bank 0 bit 24
- * KSI6 = GPIO_0031 Func1 bank 0 bit 25
- * KSI7 = GPIO_0032 Func1 bank 0 bit 26
- */
-/* KSO 0 Bank 1, Func2, bit 0 */
-ALTERNATE(PIN_MASK(1, 0x01),		2,	MODULE_KEYBOARD_SCAN,
-							GPIO_ODR_HIGH)
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xA0),		1,	MODULE_KEYBOARD_SCAN,
-							GPIO_ODR_HIGH)
-GPIO(KBD_KSO2,		PIN(046),	GPIO_OUT_LOW)
-#else
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xE0),		1,	MODULE_KEYBOARD_SCAN,
-							GPIO_ODR_HIGH)
-#endif
-
-/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
-ALTERNATE(PIN_MASK(2, 0x003E0080),	2,	MODULE_KEYBOARD_SCAN,
-							GPIO_ODR_HIGH)
-/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
-ALTERNATE(PIN_MASK(2, 0x00010C00),	1,	MODULE_KEYBOARD_SCAN,
-							GPIO_ODR_HIGH)
-
-/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
-ALTERNATE(PIN_MASK(0, 0x07C38000),	1,	MODULE_KEYBOARD_SCAN,
-						(GPIO_INPUT | GPIO_PULL_UP))
-
-/*
- * ESPI_RST_EC_R_N# - GPIO_0061 Func 1, Bank 1 bit[17]
- * ESPI_ALERT0_EC_R_N# - GPIO_0063 Func 1, Bank 1 bit[19]
- * ESPI_CLK_EC_R    - GPIO_0065 Func 1, Bank 1 bit[21]
- * ESPI_CS0_EC_R_N# - GPIO_0066 Func 1, Bank 1 bit[22]
- * ESPI_IO0_EC_R    - GPIO_0070 Func 1, Bank 1 bit[24]
- * ESPI_IO1_EC_R    - GPIO_0071 Func 1, Bank 1 bit[25]
- * ESPI_IO2_EC_R    - GPIO_0072 Func 1, Bank 1 bit[26]
- * ESPI_IO3_EC_R    - GPIO_0073 Func 1, Bank 1 bit[27]
- */
-ALTERNATE(PIN_MASK(1, 0x0F6A0000),	1,	MODULE_LPC,	GPIO_FLAG_NONE)
diff --git a/board/adlrvpp_mchp1521/vif_override.xml b/board/adlrvpp_mchp1521/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_mchp1521/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/adlrvpp_mchp1727/board.c b/board/adlrvpp_mchp1727/board.c
deleted file mode 100644
index 7e2b777e70..0000000000
--- a/board/adlrvpp_mchp1727/board.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-#include "button.h"
-#include "fusb302.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tcpm.h"
-#include "spi.h"
-#include "spi_chip.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl = GPIO_SMB_BS_CLK,
-		.sda = GPIO_SMB_BS_DATA,
-	},
-	[I2C_CHAN_TYPEC_0] = {
-		.name = "typec_0",
-		.port = I2C_PORT_TYPEC_0,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
-	},
-	[I2C_CHAN_TYPEC_1] = {
-		.name = "typec_1",
-		.port = I2C_PORT_TYPEC_1,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[I2C_CHAN_TYPEC_2] = {
-		.name = "typec_2",
-		.port = I2C_PORT_TYPEC_2,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
-	},
-	[I2C_CHAN_TYPEC_3] = {
-		.name = "typec_3",
-		.port = I2C_PORT_TYPEC_3,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_0,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#if defined(HAS_TASK_PD_C1)
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_1,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_2,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_3,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1727/board.h b/board/adlrvpp_mchp1727/board.h
deleted file mode 100644
index 50c666ece2..0000000000
--- a/board/adlrvpp_mchp1727/board.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* MCHP EC variant */
-#define VARIANT_INTELRVP_EC_MCHP
-
-/* UART for EC console */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 0
-
-#include "adlrvp.h"
-
-/*
- * External parallel crystal between XTAL1 and XTAL2 pins.
- *   #define CONFIG_CLOCK_SRC_EXTERNAL
- *   #define CONFIG_CLOCK_CRYSTAL
- * External single ended 32KHz 50% duty cycle input clock.
- *   #define CONFIG_CLOCK_SRC_EXTERNAL
- *   #undef CONFIG_CLOCK_CRYSTAL
- * Use internal silicon 32KHz oscillator
- *   #undef CONFIG_CLOCK_SRC_EXTERNAL
- *   CONFIG_CLOCK_CRYSTAL is a don't care
- */
-#undef	CONFIG_CLOCK_SRC_EXTERNAL
-
-/* MEC1727 integrated SPI chip 512KB SST25PF040C */
-#define CONFIG_SPI_FLASH_W25X40
-
-/*
- * Enable extra SPI flash and generic SPI
- * commands via EC UART
- */
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SPI_XFER
-
-/* MEC172x does not apply GP-SPI controllers */
-#undef CONFIG_MCHP_GPSPI
-
-/* ADC channels */
-#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
-#undef ADC_TEMP_SNS_DDR_CHANNEL
-#undef ADC_TEMP_SNS_SKIN_CHANNEL
-#undef ADC_TEMP_SNS_VR_CHANNEL
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH5
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH0
-
-/*
- * ADC maximum voltage is a board level configuration.
- * MEC172x ADC can use an external 3.0 or 3.3V reference with
- * maximum values up to the reference voltage.
- * The ADC maximum voltage depends upon the external reference
- * voltage connected to MEC172x.
- */
-#undef ADC_MAX_MVOLT
-#define ADC_MAX_MVOLT 3300
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-/* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_DSW_PWROK
-
-/* Sensors */
-#define GMR_TABLET_MODE_GPIO_L		GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_N
-
-/* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
-
-/* H1 */
-#define GPIO_WP_L			GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-
-/* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET
-
-/* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL
-
-/* LED */
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L
-
-/* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_THERM_SEN_MECC
-
-/* Charger */
-#define I2C_PORT_CHARGER	MCHP_I2C_PORT0
-
-/* Battery */
-#define I2C_PORT_BATTERY	MCHP_I2C_PORT0
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
-
-/* Port 80 */
-#define I2C_PORT_PORT80		MCHP_I2C_PORT0
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0	MCHP_I2C_PORT6
-/*
- * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
- *       on the RVP to reduce BOM stuffing options.
- */
-#define I2C_PORT_TYPEC_1	MCHP_I2C_PORT3
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2	MCHP_I2C_PORT7
-#define I2C_PORT_TYPEC_3	MCHP_I2C_PORT2
-#endif
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_TYPEC_0,
-	I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
-	I2C_CHAN_TYPEC_2,
-	I2C_CHAN_TYPEC_3,
-#endif
-	I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1727/build.mk b/board/adlrvpp_mchp1727/build.mk
deleted file mode 100644
index 2a056943d4..0000000000
--- a/board/adlrvpp_mchp1727/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-MCHP1727 board-specific configuration
-#
-
-# the IC is Microchip MEC172x 416 KB total SRAM
-# MEC1723SZ variant is 144 pin, loads from external SPI flash
-# MEC1727SZ variant is 144 pin, loads from 512KB internal SPI flash
-# external SPI is 512KB
-# clock is Internal ROSC
-CHIP:=mchp
-CHIP_FAMILY:=mec172x
-CHIP_VARIANT:=mec1727sz
-CHIP_SPI_SIZE_KB:=512
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_mchp1727/ec.tasklist b/board/adlrvpp_mchp1727/ec.tasklist
deleted file mode 100644
index d640149caa..0000000000
--- a/board/adlrvpp_mchp1727/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-MCHP1727 board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1727/gpio.inc b/board/adlrvpp_mchp1727/gpio.inc
deleted file mode 100644
index 1eea86462c..0000000000
--- a/board/adlrvpp_mchp1727/gpio.inc
+++ /dev/null
@@ -1,262 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-MCHP1727 board-specific configuration */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-/* include common gpio.inc under chip/mchp/lfw/... */
-#include "chip/mchp/lfw/gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD,		PIN(057), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD,		PIN(0221), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N,		PIN(0243), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3,		PIN(0201), GPIO_INT_BOTH, power_signal_interrupt)
-/* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(0207), GPIO_INT_BOTH, power_signal_interrupt) */
-GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(0227), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PM_SLP_S3_N,		PIN(0161), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S3_N,		PIN(0161), GPIO_INPUT)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PM_SLP_S4_N,		PIN(0162), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S4_N,		PIN(0162), GPIO_INPUT)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP,		PIN(036), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC,		PIN(0254), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID,		PIN(0226), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0115), GPIO_INT_BOTH, power_button_interrupt)
-
-/* DC / AC interrupts, DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, 	PIN(043), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-GPIO_INT(BC_ACOK,		PIN(0156), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-/* Sensor interrupt */
-GPIO_INT(SLATE_MODE_INDICATION,	PIN(0222), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* Flash WP interrupt */
-GPIO_INT(EC_FLASH_WP_ODL,	PIN(014), GPIO_INT_BOTH, switch_interrupt)
-
-/* Case Closed Debug Mode interrupt */
-GPIO_INT(CCD_MODE_ODL,		PIN(0175), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* UART0 RX interrupt, RX input wake event */
-GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USBC_TCPC_ALRT_P0,	PIN(0143), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(0240), GPIO_INT_BOTH, ppc_interrupt)
-
-#if defined(HAS_TASK_PD_C1)
-GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(0101), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P1,	PIN(0241), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P1,	PIN(0101), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C2)
-/* w/o rework: USBC_TCPC_ALRT_P2 -> VCI_OVRD_IN */
-GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(0144), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P2,	PIN(0130), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(0144), GPIO_INPUT)
-#endif
-
-#if defined(HAS_TASK_PD_C3)
-GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(0142), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_ALRT_P3,	PIN(0242), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(0142), GPIO_INPUT)
-#endif
-
-/* Host communication GPIOs */
-GPIO(SMC_WAKE_SCI_N_MECC,	PIN(051), GPIO_ODR_HIGH)
-GPIO(EC_PCH_MKBP_INT_ODL,	PIN(0127), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(LPC_ESPI_RST_N,		PIN(061), GPIO_INPUT)
-GPIO(PLT_RST_L, 		PIN(052), GPIO_INPUT) /* PCH_PLTRST_L */
-#endif
-
-/* Prochot GPIO */
-GPIO(PROCHOT_EC_N,		PIN(002), GPIO_INPUT)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL,		PIN(060), GPIO_ODR_HIGH)
-GPIO(PM_RSMRST_N,		PIN(054), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N,		PIN(016), GPIO_ODR_HIGH)
-/* w/o rework: EC_SPI_OE_MECC -> BGPO0 */
-GPIO(EC_SPI_OE_MECC,		PIN(042), GPIO_OUT_LOW)
-/* w/o rework: EC_DS3 -> VCI_OUT2 */
-GPIO(EC_DS3,			PIN(025), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
-GPIO(PCH_PWROK_EC,	PIN(0106), GPIO_INPUT)
-GPIO(SYS_PWROK,		PIN(0202), GPIO_OUT_LOW)
-GPIO(EC_DSW_PWROK,	PIN(034), GPIO_OUT_LOW)
-
-/* H1 GPIOs */
-GPIO(EC_H1_PACKET_MODE,		PIN(035), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW,		PIN(0102), GPIO_OUT_LOW)
-
-/* Battery present */
-GPIO(BAT_DET,		PIN(0206), GPIO_INPUT)
-
-/* EDP */
-GPIO(EDP_BKLT_EN_MECC,	PIN(022), GPIO_OUT_HIGH)
-
-/* LED */
-GPIO(LED_1_L,		PIN(0157), GPIO_OUT_HIGH)
-GPIO(LED_2_L,		PIN(0153), GPIO_OUT_HIGH)
-
-/* FAN control pins */
-GPIO(THERM_SEN_MECC,	PIN(0141), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SMB_BS_CLK,		PIN(004), GPIO_INPUT)	/* I2C00_SCL */
-GPIO(SMB_BS_DATA,		PIN(003), GPIO_INPUT)	/* I2C00_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(0140), GPIO_INPUT)	/* I2C06_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(0132), GPIO_INPUT)	/* I2C06_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(013), GPIO_INPUT)	/* I2C07_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(012), GPIO_INPUT)	/* I2C07_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(010), GPIO_INPUT)	/* I2C03_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(007), GPIO_INPUT)	/* I2C03_SDA */
-GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(0155), GPIO_INPUT)	/* I2C02_SCL */
-GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(0154), GPIO_INPUT)	/* I2C02_SDA */
-
-/* Unused pins */
-GPIO(SML1_CLK_MECC,		PIN(0131), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC,		PIN(000), GPIO_INPUT)
-GPIO(ESPI_ALERT0_N,		PIN(063), GPIO_INPUT)
-GPIO(BATT_DISABLE_EC,		PIN(067), GPIO_INPUT)
-/* Unused: GPIO(SLP_S0_CS_N,		PIN(nVCI_IN0), GPIO_INPUT) */
-GPIO(CPU_C10_GATE_MECC,		PIN(023), GPIO_INPUT)
-GPIO(SMC_SDOWN_MECC,		PIN(0255), GPIO_INPUT)
-GPIO(STD_ADPT_CNTRL_GPIO,	PIN(0244), GPIO_INPUT)
-GPIO(SMC_ONOFF_N,		PIN(0114), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(SUSWARN,			PIN(024), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC,		PIN(033), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-/* I2C pins alternate functions for ports 0, 2-3, 6-7
- * Configure I2C ports as I2C alternate function.
- * If board does not use external pull-ups then change GPIO flags
- * to enable internal pull-ups.
- * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
- * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
- * I2C02_SDA = GPIO_0154(Bank=3, bit=12) Func1
- * I2C02_SCL = GPIO_0155(Bank=3, bit=13) Func1
- * I2C03_SDA = GPIO_0007(Bank=0, bit=7) Func1
- * I2C03_SDL = GPIO_0010(Bank=0, bit=8) Func1
- * I2C06_SDA = GPIO_0132(Bank=2, bit=26) Func1
- * I2C06_SCL = GPIO_0140(Bank=3, bit=0) Func1
- * I2C07_SDA = GPIO_0012(Bank=0, bit=10) Func1
- * I2C07_SDL = GPIO_0013(Bank=0, bit=11) Func1
- */
-ALTERNATE(PIN_MASK(0,  0x00000D98), 1, MODULE_I2C, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(2,  0x04000000), 1, MODULE_I2C, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(3,  0x00003001), 1, MODULE_I2C, GPIO_ODR_HIGH)
-
-/* Alternate pins for ADC */
-/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
-/* ADC pins
- * GPIO200/ADC00 = VR_TMP/V_1P05
- * GPIO203/ADC03 = AMBIENT_TEMP
- * GPIO204/ADC04 = SKIN_THERM_IN_EC
- * GPIO205/ADC05 = DDR_TEMP/EC_5V
- * ADC00 = GPIO_0200(Bank=4, bit=0) Func1
- * ADC03 = GPIO_0203(Bank=4, bit=3) Func1
- * ADC04 = GPIO_0204(Bank=4, bit=4) Func1
- * ADC05 = GPIO_0205(Bank=4, bit=5) Func1
- */
-ALTERNATE(PIN_MASK(4,  0x0039), 1, MODULE_ADC, GPIO_ANALOG)
-
-/*
- * Alternate pins for RPM-FAN control
- *
- * GPIO050/GTACH0 = CPU_TACHO_FAN
- * GPIO053/GPWM0 = CPU_PWM_FAN
- * GTACH0 = GPIO_050(Bank=1, bit=8) Func2
- * GPWM0 = GPIO_053(Bank=1, bit=11) Func3
- */
-ALTERNATE(PIN_MASK(1, 0x0100), 2, MODULE_PWM, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(1, 0x0800), 3, MODULE_PWM, GPIO_FLAG_NONE)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
-/*
- * MEC172xH-SZ (144 pin package)
- * KSO00 = GPIO_0040 Func2 bank 1 bit 0
- * KSO01 = GPIO_0045 Func1 bank 1 bit 5
- * KSO02 = GPIO_0046 Func1 bank 1 bit 6
- * KSO03 = GPIO_0047 Func1 bank 1 bit 7
- * KSO04 = GPIO_0107 Func2 bank 2 bit 7
- * KSO05 = GPIO_0112 Func1 bank 2 bit 10
- * KSO06 = GPIO_0113 Func1 bank 2 bit 11
- * KSO07 = GPIO_0120 Func1 bank 2 bit 16
- * KSO08 = GPIO_0121 Func2 bank 2 bit 17
- * KSO09 = GPIO_0122 Func2 bank 2 bit 18
- * KSO10 = GPIO_0123 Func2 bank 2 bit 19
- * KSO11 = GPIO_0124 Func2 bank 2 bit 20
- * KSO12 = GPIO_0125 Func2 bank 2 bit 21
- * For 8x16 keyboard add KSO13 - KSO15
- * KSO13 = GPIO_0126 Func2 bank 2 bit 22
- * KSO14 = GPIO_0152 Func1 bank 3 bit 10
- * KSO15 = GPIO_0151 Func2 bank 3 bit 9
- *
- * KSI0 = GPIO_0017 Func1 bank 0 bit 15
- * KSI1 = GPIO_0020 Func1 bank 0 bit 16
- * KSI2 = GPIO_0021 Func1 bank 0 bit 17
- * KSI3 = GPIO_0026 Func1 bank 0 bit 22
- * KSI4 = GPIO_0027 Func1 bank 0 bit 23
- * KSI5 = GPIO_0030 Func1 bank 0 bit 24
- * KSI6 = GPIO_0031 Func1 bank 0 bit 25
- * KSI7 = GPIO_0032 Func1 bank 0 bit 26
- */
-/* KSO 0 Bank 1, Func2, bit 0 */
-ALTERNATE(PIN_MASK(1, 0x01), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xA0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2, PIN(046), GPIO_KB_OUTPUT_COL2)
-#else
-/* KSO 1-3 Bank 1, Func1, bits 5-7 */
-ALTERNATE(PIN_MASK(1, 0xE0), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-#endif
-
-/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
-ALTERNATE(PIN_MASK(2, 0x003E0080), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
-ALTERNATE(PIN_MASK(2, 0x00010C00), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
-ALTERNATE(PIN_MASK(0, 0x07C38000), 1, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-
-/*
- * ESPI_RESET# - GPIO_0061 Func 1, Bank 1 bit[17]
- * ESPI_ALERT# - GPIO_0063 Func 1, Bank 1 bit[19]
- * ESPI_CLK    - GPIO_0065 Func 1, Bank 1 bit[21]
- * ESPI_CS#    - GPIO_0066 Func 1, Bank 1 bit[22]
- * ESPI_IO0    - GPIO_0070 Func 1, Bank 1 bit[24]
- * ESPI_IO1    - GPIO_0071 Func 1, Bank 1 bit[25]
- * ESPI_IO2    - GPIO_0072 Func 1, Bank 1 bit[26]
- * ESPI_IO3    - GPIO_0073 Func 1, Bank 1 bit[27]
- */
-ALTERNATE(PIN_MASK(1, 0x0F6A0000), 1, MODULE_LPC, 0)
diff --git a/board/adlrvpp_mchp1727/vif_override.xml b/board/adlrvpp_mchp1727/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_mchp1727/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/adlrvpp_npcx/board.c b/board/adlrvpp_npcx/board.c
deleted file mode 100644
index d4221696f1..0000000000
--- a/board/adlrvpp_npcx/board.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADLRVP-NPCX board-specific configuration */
-#include "button.h"
-#include "fusb302.h"
-#include "lid_switch.h"
-#include "pca9675.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tcpm.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl = GPIO_SMB_BS_CLK,
-		.sda = GPIO_SMB_BS_DATA,
-	},
-	[I2C_CHAN_TYPEC_0] = {
-		.name = "typec_0",
-		.port = I2C_PORT_TYPEC_0,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P0,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P0,
-	},
-	[I2C_CHAN_TYPEC_1] = {
-		.name = "typec_1",
-		.port = I2C_PORT_TYPEC_1,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[I2C_CHAN_TYPEC_2] = {
-		.name = "typec_2",
-		.port = I2C_PORT_TYPEC_2,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P1,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P1,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[I2C_CHAN_TYPEC_3] = {
-		.name = "typec_3",
-		.port = I2C_PORT_TYPEC_3,
-		.kbps = 400,
-		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
-		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_0,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_1,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#if defined(HAS_TASK_PD_C2)
-	[TYPE_C_PORT_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_2,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-#if defined(HAS_TASK_PD_C3)
-	[TYPE_C_PORT_3] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TYPEC_3,
-			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
diff --git a/board/adlrvpp_npcx/board.h b/board/adlrvpp_npcx/board.h
deleted file mode 100644
index 8cf70b81a8..0000000000
--- a/board/adlrvpp_npcx/board.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-NPCX board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_NPCX
-
-#include "adlrvp.h"
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-/* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_DSW_PWROK
-
-/* Sensors */
-#define GMR_TABLET_MODE_GPIO_L		GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_N
-
-/* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
-
-/* H1 */
-#define GPIO_WP_L			GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-
-/* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET
-
-/* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL
-
-/* LED */
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L
-
-/* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_THERM_SEN_MECC
-
-/* I2C ports & Configs */
-/* Charger */
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-
-/* Battery */
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT7_0
-
-/* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	NPCX_I2C_PORT7_0
-
-/* Port 80 */
-#define I2C_PORT_PORT80		NPCX_I2C_PORT7_0
-
-/* USB-C I2C */
-#define I2C_PORT_TYPEC_0	NPCX_I2C_PORT0_0
-/*
- * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
- *       on the RVP to reduce BOM stuffing options.
- */
-#define I2C_PORT_TYPEC_1	NPCX_I2C_PORT2_0
-#if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2	NPCX_I2C_PORT1_0
-#endif
-#if defined(HAS_TASK_PD_C3)
-#define I2C_PORT_TYPEC_3	NPCX_I2C_PORT3_0
-#endif
-
-#ifndef __ASSEMBLER__
-
-enum adlrvp_i2c_channel {
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_TYPEC_0,
-	I2C_CHAN_TYPEC_1,
-#if defined(HAS_TASK_PD_C2)
-	I2C_CHAN_TYPEC_2,
-#endif
-#if defined(HAS_TASK_PD_C3)
-	I2C_CHAN_TYPEC_3,
-#endif
-	I2C_CHAN_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_npcx/build.mk b/board/adlrvpp_npcx/build.mk
deleted file mode 100644
index ec3450ee7e..0000000000
--- a/board/adlrvpp_npcx/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel ADL-P-RVP-NPCX board-specific configuration
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=intelrvp
-
-board-y=board.o
diff --git a/board/adlrvpp_npcx/ec.tasklist b/board/adlrvpp_npcx/ec.tasklist
deleted file mode 100644
index 6dddaa994c..0000000000
--- a/board/adlrvpp_npcx/ec.tasklist
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel ADL-P-RVP-NPCX board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C3, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C3, pd_interrupt_handler_task, 3, ULTRA_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_npcx/gpio.inc b/board/adlrvpp_npcx/gpio.inc
deleted file mode 100644
index a059b1c6b6..0000000000
--- a/board/adlrvpp_npcx/gpio.inc
+++ /dev/null
@@ -1,176 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel ADL-P-RVP-NPCX board-specific configuration */
-
-#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
-
-/* Power sequencing interrupts */
-GPIO_INT(ALL_SYS_PWRGD,		PIN(7, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD,		PIN(3, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_N,		PIN(A, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCPDSW_3P3,		PIN(4, 5), GPIO_INT_BOTH, power_signal_interrupt)
-/* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(7, 1), GPIO_INT_BOTH, power_signal_interrupt) */
-GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PM_SLP_S3_N,		PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S3_N,		PIN(B, 0), GPIO_INPUT)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PM_SLP_S4_N,		PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#else
-GPIO(PM_SLP_S4_N,		PIN(A, 5), GPIO_INPUT)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP,		PIN(6, 1), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOL_DN_EC,		PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(SMC_LID,		PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(STD_ADP_PRSNT, 	PIN(0, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) /* DC_JACK_PRESENT */
-
-GPIO_INT(BC_ACOK,		PIN(C, 6), GPIO_INT_BOTH, extpower_interrupt) /* AC Present */
-
-/* USB-C interrupts */
-GPIO_INT(USBC_TCPC_ALRT_P0,	PIN(4, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(6, 2), GPIO_INT_BOTH, tcpc_alert_event)
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(6, 3), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(6, 7), GPIO_INT_BOTH, tcpc_alert_event)
-#else
-GPIO(USBC_TCPC_ALRT_P2,		PIN(6, 3), GPIO_INPUT)
-GPIO(USBC_TCPC_ALRT_P3,		PIN(6, 7), GPIO_INPUT)
-#endif
-
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(F, 0), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(F, 1), GPIO_INT_BOTH, ppc_interrupt)
-#if defined(HAS_TASK_PD_C2)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(F, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(F, 3), GPIO_INT_BOTH, ppc_interrupt)
-#else
-GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(F, 2), GPIO_INPUT)
-GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(F, 3), GPIO_INPUT)
-#endif
-
-/* Host communication GPIOs */
-GPIO(SMC_WAKE_SCI_N_MECC,	PIN(A, 4), GPIO_ODR_HIGH)
-GPIO(EC_PCH_MKBP_INT_ODL,	PIN(F, 5), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(LPC_ESPI_RST_N,		PIN(5, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(PLT_RST_L, 		PIN(A, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PLTRST_L */
-#endif
-
-/* Sensor Interrupts */
-GPIO_INT(SLATE_MODE_INDICATION,	PIN(E, 5), GPIO_INT_BOTH | GPIO_SEL_1P8V, gmr_tablet_switch_isr)
-GPIO(PROCHOT_EC_N,		PIN(A, 7), GPIO_INPUT)
-
-/* Power sequencing GPIOs */
-GPIO(SYS_RST_ODL,		PIN(C, 5), GPIO_ODR_HIGH)
-/* GPIOD3 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
-GPIO(PM_RSMRST_N,		PIN(D, 3), GPIO_OUT_LOW)
-GPIO(PM_PWRBTN_N,		PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_MECC,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_DS3,			PIN(C, 4), GPIO_OUT_LOW)
-UNIMPLEMENTED(EN_PP5000)
-
-/* PCH_PWROK_EC is an input, as it's driven by the Silego chip on RVP */
-GPIO(PCH_PWROK_EC,	PIN(A, 0), GPIO_INPUT)
-GPIO(SYS_PWROK,		PIN(9, 3), GPIO_OUT_LOW)
-GPIO(EC_DSW_PWROK,	PIN(9, 5), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO_INT(EC_FLASH_WP_ODL,	PIN(9, 4), GPIO_INT_BOTH, switch_interrupt)
-GPIO(EC_H1_PACKET_MODE,		PIN(E, 2), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW,		PIN(D, 4), GPIO_OUT_LOW)
-
-/* Case Closed Debug Mode */
-GPIO_INT(CCD_MODE_ODL,		PIN(F, 4), GPIO_INT_BOTH, board_connect_c0_sbu)
-
-/* Battery present */
-GPIO(BAT_DET,		PIN(7, 6), GPIO_INPUT)
-
-/* EDP */
-GPIO(EDP_BKLT_EN_MECC,	PIN(E, 1), GPIO_OUT_HIGH)
-
-/* LED */
-GPIO(LED_1_L,		PIN(B, 6), GPIO_OUT_HIGH)
-GPIO(LED_2_L,		PIN(B, 7), GPIO_OUT_HIGH)
-
-/* FAN control pins */
-GPIO(THERM_SEN_MECC,	PIN(C, 0), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(SMB_BS_CLK,		PIN(B, 3), GPIO_INPUT)	/* I2C7_SCL0 */
-GPIO(SMB_BS_DATA,		PIN(B, 2), GPIO_INPUT)	/* I2C7_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P0,	PIN(B, 5), GPIO_INPUT)	/* I2C0_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P0,	PIN(B, 4), GPIO_INPUT)	/* I2C0_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P2,	PIN(9, 2), GPIO_INPUT)	/* I2C2_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P2,	PIN(9, 1), GPIO_INPUT)	/* I2C2_SDA0 */
-GPIO(USBC_TCPC_I2C_CLK_P1,	PIN(9, 0), GPIO_INPUT)	/* I2C1_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P1,	PIN(8, 7), GPIO_INPUT)	/* I2C1_SCL0 */
-GPIO(USBC_TCPC_I2C_CLK_P3,	PIN(D, 1), GPIO_INPUT)	/* I2C3_SCL0 */
-GPIO(USBC_TCPC_I2C_DATA_P3,	PIN(D, 0), GPIO_INPUT)	/* I2C3_SCL0 */
-
-/* Unused pins */
-GPIO(SML1_CLK_MECC,		PIN(3, 3), GPIO_INPUT)
-GPIO(SML1_DATA_MECC,		PIN(3, 6), GPIO_INPUT)
-GPIO(SMB_PCH_CLK,		PIN(C, 2), GPIO_INPUT)
-GPIO(SMB_PCH_DATA,		PIN(C, 1), GPIO_INPUT)
-GPIO(I3C_0_SCL,			PIN(E, 4), GPIO_INPUT)
-GPIO(I3C_0_SDA,			PIN(E, 3), GPIO_INPUT)
-GPIO(CPU_CAT_ERR_MECC,		PIN(3, 4), GPIO_INPUT)
-GPIO(TP29,			PIN(5, 0), GPIO_INPUT)
-GPIO(TP28,			PIN(5, 6), GPIO_INPUT)
-GPIO(ESPI_ALERT0_N,		PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(BATT_DISABLE_EC,		PIN(6, 6), GPIO_INPUT)
-GPIO(TP33,			PIN(7, 2), GPIO_INPUT)
-GPIO(TP26,			PIN(7, 3), GPIO_INPUT)
-GPIO(SLP_S0_CS_N,		PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PECI,			PIN(8, 1), GPIO_INPUT)
-GPIO(CPU_C10_GATE_MECC,		PIN(9, 6), GPIO_INPUT)
-GPIO(SMB_PCH_ALRT,		PIN(A, 3), GPIO_INPUT)
-GPIO(SMC_SDOWN_MECC,		PIN(B, 1), GPIO_INPUT)
-GPIO(STD_ADPT_CNTRL_GPIO,	PIN(C, 3), GPIO_INPUT)
-GPIO(SML1_ALERT,		PIN(C, 7), GPIO_INPUT)
-GPIO(SMC_ONOFF_N,		PIN(D, 2), GPIO_INPUT) /* Power button interrupt without H1 */
-GPIO(SUSWARN,			PIN(D, 5), GPIO_INPUT)
-GPIO(TP_GPIOD6_EC,		PIN(D, 6), GPIO_INPUT)
-GPIO(TP_GPIOD7_EC,		PIN(D, 7), GPIO_INPUT)
-GPIO(ME_G3_TO_M3_EC,		PIN(E, 0), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(8, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3) | BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP)
-
-/* Alternate pins for ADC */
-/* VR_TMP/V_1P05 - GPIO44, SKIN_THERM_IN_EC - GPIO43, AMBIENT_TEMP - GPIO42, DDR_TEMP/EC_5V - GPIO41 */
-ALTERNATE(PIN_MASK(4, BIT(1) | BIT(2) | BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(8, BIT(0)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* CPU_FAN_MECC GPIO80/PWM3_LED3 */
-/* GPIOA6 (Rework: CPU_TACHO_FAN is swapped with PM_RSMRST_N) */
-ALTERNATE(PIN_MASK(A, BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_02-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_14-15 */
diff --git a/board/adlrvpp_npcx/vif_override.xml b/board/adlrvpp_npcx/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/adlrvpp_npcx/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/akemi/battery.c b/board/akemi/battery.c
deleted file mode 100644
index 238716b116..0000000000
--- a/board/akemi/battery.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Hatch battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000,  /* mV */
-			.precharge_current	= 333,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
diff --git a/board/akemi/board.c b/board/akemi/board.c
deleted file mode 100644
index 5b88f82fb5..0000000000
--- a/board/akemi/board.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/g753.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-#include "battery_smart.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_CPU,
-				 .read = g753_get_val,
-				 .idx = 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Hatch Temperature sensors */
-/*
- * TODO(b/124316213): These setting need to be reviewed and set appropriately
- * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	uint8_t sku = get_board_sku();
-	/*
-	 * Check if the current sku id does not support keyboard backlight
-	 * and return the feature flag without EC_FEATURE_PWM_KEYB
-	 * sku_id = 1/2 - without keyboard backlight
-	 * sku_id = 3/4 - with keyboard backlight
-	 */
-	if (sku == 1 || sku == 2)
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
-
-/* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define QUICK_CHARGE_SUPPORT            0x01
-#define QUICK_CHARGE_ENABLE             0x02
-
-#define SB_QUICK_CHARGE_ENABLE          1
-#define SB_QUICK_CHARGE_DISABLE         0
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_OPTIONALMFG_FUNCTION2, &val);
-	if (rv)
-		return;
-
-	if (val & QUICK_CHARGE_SUPPORT) {
-		if (enable)
-			val |= QUICK_CHARGE_ENABLE;
-		else
-			val &= ~QUICK_CHARGE_ENABLE;
-
-		sb_write(SB_OPTIONALMFG_FUNCTION2, val);
-	}
-}
-
-/* Called on AP S5 -> S0 transition */
-static void board_chipset_startup(void)
-{
-	/* Normal charge current */
-	sb_quick_charge_mode(SB_QUICK_CHARGE_DISABLE);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_INIT_I2C+1);
-
-/* Called on AP S0 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Quick charge current */
-	sb_quick_charge_mode(SB_QUICK_CHARGE_ENABLE);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 3) ||
-		(sku == 4);
-}
diff --git a/board/akemi/board.h b/board/akemi/board.h
deleted file mode 100644
index de542a5f0e..0000000000
--- a/board/akemi/board.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* LSM6DS3TR-C Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-/* LIS2DWL Lid accel */
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* TI gauge IC 500ms WDT timeout setting under battery sleep mode
- * induced battery cut-off, under the following conditions:
- * 1. SMBus communication on FC is once per minute which allows
- * battery entering sleep mode;
- * 2. System load < 10mA and accumulate 5 hours will trigger battery
- * simulation and result in a 500ms WDT timeout. So change charge
- * max sleep time from once/minute to once/10 seconds to prevent
- * battery entering sleep mode. See b/133375756 and b/148822924.
- */
-#define CHARGE_MAX_SLEEP_USEC (10 * SECOND)
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_G753
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/akemi/build.mk b/board/akemi/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/akemi/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/akemi/ec.tasklist b/board/akemi/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/akemi/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/akemi/gpio.inc b/board/akemi/gpio.inc
deleted file mode 100644
index 1ea8cca58a..0000000000
--- a/board/akemi/gpio.inc
+++ /dev/null
@@ -1,140 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, lsm6dsm_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_USB_C3_PD_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_USB_C3_PD_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                             /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)                             /* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/akemi/led.c b/board/akemi/led.c
deleted file mode 100644
index ef31d2dead..0000000000
--- a/board/akemi/led.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Akemi
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/akemi/vif_override.xml b/board/akemi/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/akemi/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/aleena/analyzestack.yaml b/board/aleena/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/aleena/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/aleena/battery.c b/board/aleena/battery.c
deleted file mode 100644
index b3abae7f73..0000000000
--- a/board/aleena/battery.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Aleena battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP15O5L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_4012] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* Murata AP18K4K Battery Information */
-	[BATTERY_MURATA_4013] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304013",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/aleena/board.c b/board/aleena/board.c
deleted file mode 100644
index 0343a399c5..0000000000
--- a/board/aleena/board.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Aleena board-specific configuration */
-
-#include "button.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "console.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/led/lm3630a.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Motion sensors */
-static struct mutex icm426xx_mutex;
-
-static struct icm_drv_data_t g_icm426xx_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &icm426xx_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref_icm426xx,
-	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &icm426xx_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref_icm426xx,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static enum base_accelgyro_type base_accelgyro_config;
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_accelgyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (base_accelgyro_config != BASE_GYRO_NONE)
-		return;
-
-	if (board_is_convertible()) {
-		/* Check base accelgyro chip */
-		ret = icm_read8(&icm426xx_base_accel,
-				 ICM426XX_REG_WHO_AM_I, &val);
-		if (ret)
-			ccprints("Get ICM fail.");
-		if (val == ICM426XX_CHIP_ICM40608) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		}
-		base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-			 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-		ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-			 ? "ICM40608" : "BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_INIT_ADC + 2);
-
-void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void board_kblight_init(void)
-{
-	/*
-	 * Enable keyboard backlight. This needs to be done here because
-	 * the chip doesn't have power until PP3300_S0 comes up.
-	 */
-	gpio_set_level(GPIO_KB_BL_EN, 1);
-	lm3630a_poweron();
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 30 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/aleena/board.h b/board/aleena/board.h
deleted file mode 100644
index 9ad2a8b94b..0000000000
--- a/board/aleena/board.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Aleena board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3429
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Power and battery LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-
-#define CONFIG_LED_ONOFF_STATES
-
-#define I2C_PORT_KBLIGHT NPCX_I2C_PORT5_0
-
-/* KB backlight driver */
-#define CONFIG_LED_DRIVER_LM3630A
-
-#define CONFIG_MKBP_USE_GPIO
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-/*
- * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
- */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
-#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#ifndef __ASSEMBLER__
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_PANASONIC,
-	BATTERY_MURATA_4012,
-	BATTERY_MURATA_4013,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/aleena/build.mk b/board/aleena/build.mk
deleted file mode 100644
index c808e65aed..0000000000
--- a/board/aleena/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/aleena/ec.tasklist b/board/aleena/ec.tasklist
deleted file mode 100644
index dc898c4502..0000000000
--- a/board/aleena/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/aleena/gpio.inc b/board/aleena/gpio.inc
deleted file mode 100644
index 6fefcf88f1..0000000000
--- a/board/aleena/gpio.inc
+++ /dev/null
@@ -1,122 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	motion_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(E, 4), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(KB_BL_EN,			PIN(F, 2), GPIO_OUT_LOW)			/* Enable KB Backlight */
-GPIO(EC_INT_L,			PIN(A, 4), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
-										   EC_I2C_KB_BL_SCL */
-GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
-										   EC_I2C_KB_BL_SDA */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(EN_USB_C0_TCPC_PWR,	PIN(6, 0), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST_L,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP)	/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_1_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(BAT_LED_2_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)					/* KB Backlight */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)					/* GPIO00 = AC_PRESENT,
-										   GPIO01 = POWER_BUTTON_L,
-										   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 = LID_OPEN */
diff --git a/board/aleena/led.c b/board/aleena/led.c
deleted file mode 100644
index 4774a39045..0000000000
--- a/board/aleena/led.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "console.h"
-
-#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args)
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/*
- *	board_id	others	5, 6
- *	led1		Amber	Blue
- *	led2		Blue	Amber
- */
-static enum gpio_signal led_amber = GPIO_BAT_LED_1_L;
-static enum gpio_signal led_blue = GPIO_BAT_LED_2_L;
-
-/* Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static void board_led_init(void)
-{
-	int board_id =
-		(gpio_get_level(GPIO_BOARD_VERSION3) << 2) |
-		(gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(gpio_get_level(GPIO_BOARD_VERSION1) << 0);
-
-	CPRINTS("board_id=%d", board_id);
-
-	if ((board_id == 5) || (board_id == 6)) {
-		led_amber = GPIO_BAT_LED_2_L;
-		led_blue = GPIO_BAT_LED_1_L;
-		CPRINTS("LED: switch LED");
-	}
-
-}
-DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(led_blue, LED_ON_LVL);
-		gpio_set_level(led_amber, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(led_blue, LED_OFF_LVL);
-		gpio_set_level(led_amber, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(led_blue, LED_OFF_LVL);
-		gpio_set_level(led_amber, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/aleena/vif_override.xml b/board/aleena/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/aleena/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/ambassador/board.c b/board/ambassador/board.c
deleted file mode 100644
index f8dc910070..0000000000
--- a/board/ambassador/board.c
+++ /dev/null
@@ -1,935 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/ina3221.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_TCPPC_INT_ODL)
-		sn5s330_interrupt(0);
-}
-
-int ppc_get_alert_status(int port)
-{
-	return gpio_get_level(GPIO_USB_C0_TCPPC_INT_ODL) == 0;
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_TCPC_INT_ODL)
-		schedule_deferred_pd_interrupt(0);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int level;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	return status;
-}
-
-/* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Blink alert if insufficient power per system_can_boot_ap(). */
-	int insufficient_power =
-		(charge_ma * charge_mv) <
-		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
-	led_alert(insufficient_power);
-}
-
-static uint8_t usbc_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (!gpio_get_level(GPIO_USB_A2_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_USB_A3_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (ec_config_get_usb4_present() && !gpio_get_level(GPIO_USB_A4_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (usbc_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-/*
- * Barrel jack power supply handling
- *
- * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
- * barrel jack is connected, and the USB-C port can bring the EC up fine in
- * dead-battery mode. Both the USB-C and barrel jack switches do reverse
- * protection, so we're safe to turn one on then the other off- but we should
- * only do that if the system is off since it might still brown out.
- */
-
-/*
- * Barrel-jack power adapter ratings.
- */
-static const struct {
-	int voltage;
-	int current;
-} bj_power[] = {
-	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
-	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
-};
-
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
-/* Debounced connection state of the barrel jack */
-static int8_t adp_connected = -1;
-static void adp_connect_deferred(void)
-{
-	struct charge_port_info pi = { 0 };
-	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Debounce */
-	if (connected == adp_connected)
-		return;
-	if (connected) {
-		unsigned int bj = ec_config_get_bj_power();
-
-		pi.voltage = bj_power[bj].voltage;
-		pi.current = bj_power[bj].current;
-	}
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &pi);
-	adp_connected = connected;
-}
-DECLARE_DEFERRED(adp_connect_deferred);
-
-/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
-void adp_connect_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
-}
-
-static void adp_state_init(void)
-{
-	/*
-	 * Initialize all charge suppliers to 0. The charge manager waits until
-	 * all ports have reported in before doing anything.
-	 */
-	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
-		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
-			charge_manager_update_charge(j, i, NULL);
-	}
-
-	/* Report charge state from the barrel jack. */
-	adp_connect_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-};
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CORE] = {
-		.name = "Core",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(84),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	/*
-	 * For board version < 2, the directly connected recovery
-	 * button is not available.
-	 */
-	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	/*
-	 * Workaround to restore VBUS on PPC.
-	 * PP1 is sourced from PP5000_A, and when the CPU shuts down and
-	 * this rail drops, the PPC will internally turn off PP1_EN.
-	 * When the CPU starts again, and the rail is restored, the PPC
-	 * does not turn PP1_EN on again, causing VBUS to stay turned off.
-	 * The workaround is to check whether the PPC is sourcing VBUS, and
-	 * if so, make sure it is enabled.
-	 */
-	if (ppc_is_sourcing_vbus(0))
-		ppc_vbus_source_enable(0, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-/* Power Delivery and charging functions */
-static void board_tcpc_init(void)
-{
-	/*
-	 * Reset TCPC if we have had a system reset.
-	 * With EFSv2, it is possible to be in RW without
-	 * having reset the TCPC.
-	 */
-	if (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON)
-		board_reset_pd_mcu();
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	/* Enable other overcurrent interrupts */
-	gpio_enable_interrupt(GPIO_HDMI_CONN0_OC_ODL);
-	gpio_enable_interrupt(GPIO_HDMI_CONN1_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
-	if (ec_config_get_usb4_present()) {
-		/*
-		 * By default configured as output low.
-		 */
-		gpio_set_flags(GPIO_USB_A4_OC_ODL,
-			       GPIO_INPUT | GPIO_INT_BOTH);
-		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
-	} else {
-		/* Ensure no interrupts from pin */
-		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
-	}
-
-}
-/* Make sure this is called after fw_config is initialised */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-void board_reset_pd_mcu(void)
-{
-	int level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-		       TCPC_FLAGS_RESET_ACTIVE_HIGH);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, level);
-	msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, !level);
-	if (BOARD_TCPC_C0_RESET_POST_DELAY)
-		msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
-}
-
-int board_set_active_charge_port(int port)
-{
-	CPRINTS("Requested charge port change to %d", port);
-
-	/*
-	 * The charge manager may ask us to switch to no charger if we're
-	 * running off USB-C only but upstream doesn't support PD. It requires
-	 * that we accept this switch otherwise it triggers an assert and EC
-	 * reset; it's not possible to boot the AP anyway, but we want to avoid
-	 * resetting the EC so we can continue to do the "low power" LED blink.
-	 */
-	if (port == CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	if (port < 0 || CHARGE_PORT_COUNT <= port)
-		return EC_ERROR_INVAL;
-
-	if (port == charge_manager_get_active_charge_port())
-		return EC_SUCCESS;
-
-	/* Don't charge from a source port */
-	if (board_vbus_source_enabled(port))
-		return EC_ERROR_INVAL;
-
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		int bj_active, bj_requested;
-
-		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
-			/* Change is only permitted while the system is off */
-			return EC_ERROR_INVAL;
-
-		/*
-		 * Current setting is no charge port but the AP is on, so the
-		 * charge manager is out of sync (probably because we're
-		 * reinitializing after sysjump). Reject requests that aren't
-		 * in sync with our outputs.
-		 */
-		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
-		bj_requested = port == CHARGE_PORT_BARRELJACK;
-		if (bj_active != bj_requested)
-			return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charger p%d", port);
-
-	switch (port) {
-	case CHARGE_PORT_TYPEC0:
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
-		break;
-	case CHARGE_PORT_BARRELJACK:
-		/* Make sure BJ adapter is sourcing power */
-		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_L))
-			return EC_ERROR_INVAL;
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-	usbc_overcurrent = is_overcurrented;
-	update_5v_usage();
-}
-
-int extpower_is_present(void)
-{
-	return adp_connected;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	/*
-	 * Puff proto drives EN_PP5000_HDMI from EN_S0_RAILS so we cannot gate
-	 * core rails while in S0 because HDMI should remain powered.
-	 * EN_PP5000_HDMI is a separate EC output on all other boards.
-	 */
-	return board_version != 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-	/* This output isn't connected on protos; safe to set anyway. */
-	gpio_set_level(GPIO_EN_PP5000_HDMI, enable);
-}
-
-unsigned int ec_config_get_bj_power(void)
-{
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
-	/* Out of range value defaults to 0 */
-	if (bj >= ARRAY_SIZE(bj_power))
-		bj = 0;
-	return bj;
-}
-
-int ec_config_get_usb4_present(void)
-{
-	return !(fw_config & EC_CFG_NO_USB4_MASK);
-}
-
-unsigned int ec_config_get_thermal_solution(void)
-{
-	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
-}
-
-static void setup_thermal(void)
-{
-	unsigned int table = ec_config_get_thermal_solution();
-	/* Configure Fan */
-	switch (table) {
-	/* Default and table0 use single fan */
-	case 0:
-	default:
-		thermal_params[TEMP_SENSOR_CORE] = thermal_a;
-		break;
-	/* Table1 is fanless */
-	case 1:
-		fan_set_count(0);
-		thermal_params[TEMP_SENSOR_CORE] = thermal_b;
-		break;
-	}
-}
-/* fan_set_count should be called before  HOOK_INIT/HOOK_PRIO_DEFAULT */
-DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	static uint32_t history[POWER_READINGS];
-	static uint8_t index;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-		/*
-		 * Clear the first entry of the power table so that
-		 * it is re-initilalised when the CPU starts.
-		 */
-		history[0] = 0;
-	} else {
-		int32_t charger_mw;
-
-		delay = POWER_DELAY_MS * MSEC;
-		/*
-		 * Get current charger limit (in mw).
-		 * If not configured yet, skip.
-		 */
-		charger_mw = charge_manager_get_power_limit_uw() / 1000;
-		if (charger_mw != 0) {
-			int32_t gap, total, max, power;
-			int i;
-
-			/*
-			 * Read power usage.
-			 */
-			power = (adc_read_channel(ADC_VBUS) *
-				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
-			/* Init power table */
-			if (history[0] == 0) {
-				for (i = 0; i < POWER_READINGS; i++)
-					history[i] = power;
-			}
-			/*
-			 * Update the power readings and
-			 * calculate the average and max.
-			 */
-			history[index] = power;
-			index = (index + 1) % POWER_READINGS;
-			total = 0;
-			max = history[0];
-			for (i = 0; i < POWER_READINGS; i++) {
-				total += history[i];
-				if (history[i] > max)
-					max = history[i];
-			}
-			/*
-			 * For Type-C power supplies, there is
-			 * less tolerance for exceeding the rating,
-			 * so use the max power that has been measured
-			 * over the measuring period.
-			 * For barrel-jack supplies, the rating can be
-			 * exceeded briefly, so use the average.
-			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
-				power = max;
-			else
-				power = total / POWER_READINGS;
-			/*
-			 * Calculate gap, and if negative, power
-			 * demand is exceeding configured power budget, so
-			 * throttling is required to reduce the demand.
-			 */
-			gap = charger_mw - power;
-			/*
-			 * Limiting type-A power.
-			 */
-			if (gap <= 0) {
-				new_state |= THROT_TYPE_A;
-				headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-				if (!(current_state & THROT_TYPE_A))
-					gap += POWER_GAIN_TYPE_A;
-			}
-			/*
-			 * If the type-C port is sourcing power,
-			 * check whether it should be throttled.
-			 */
-			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
-				new_state |= THROT_TYPE_C;
-				headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-				if (!(current_state & THROT_TYPE_C))
-					gap += POWER_GAIN_TYPE_C;
-			}
-			/*
-			 * As a last resort, turn on PROCHOT to
-			 * throttle the CPU.
-			 */
-			if (gap <= 0)
-				new_state |= THROT_PROCHOT;
-		}
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
-
-		ppc_set_vbus_source_current_limit(0, rp);
-		tcpm_select_rp_value(0, rp);
-		pd_update_contract(0);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
diff --git a/board/ambassador/board.h b/board/ambassador/board.h
deleted file mode 100644
index de918b35ac..0000000000
--- a/board/ambassador/board.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-/* TODO: (b/143496253) re-enable CEC */
-/* #define CONFIG_CEC */
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-/* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 1
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
-
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-/* Less than this much blocks AP power-on. */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 30000
-#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
-
-/* USB type C */
-#define CONFIG_USB_PD_TCPMV2 /* Use TCPMv2 */
-#define CONFIG_USB_PD_REV30 /* Enable PD 3.0 functionality */
-#define CONFIG_USB_PD_DECODE_SOP
-#undef CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-#define USB_PD_PORT_TCPC_0	0
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are five ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-unsigned int ec_config_get_bj_power(void);
-int ec_config_get_usb4_present(void);
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ambassador/build.mk b/board/ambassador/build.mk
deleted file mode 100644
index 0f55c45f77..0000000000
--- a/board/ambassador/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-board-y+=led.o
diff --git a/board/ambassador/ec.tasklist b/board/ambassador/ec.tasklist
deleted file mode 100644
index f820cf903c..0000000000
--- a/board/ambassador/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
diff --git a/board/ambassador/gpio.inc b/board/ambassador/gpio.inc
deleted file mode 100644
index 9d718bb110..0000000000
--- a/board/ambassador/gpio.inc
+++ /dev/null
@@ -1,169 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Other interrupts */
-GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-/*
- * Directly connected recovery button (not available on some boards).
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
-
-/* Port power control interrupts */
-GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A0_OC_ODL,        PIN(E, 4), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-/* May be reconfigured as input */
-GPIO_INT(USB_A4_OC_ODL,        PIN(B, 0), GPIO_OUT_LOW | GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A2_STATUS_L,          PIN(6, 1), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,          PIN(C, 7), GPIO_INPUT)
-
-/* USB type C */
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(EN_PP_MST_OD,             PIN(9, 6), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-
-/* HDMI/CEC */
-GPIO(EN_PP5000_HDMI,           PIN(5, 0), GPIO_OUT_LOW)
-GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
-GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* Unused pins */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(F, 2))						/* EC_I2C_RFU_SDA */
-UNUSED(PIN(F, 3))						/* EC_I2C_RFU_SCL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(8, 0))						/* LED_BLUE_L */
-UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(9, 2))						/* K8  NC */
-UNUSED(PIN(9, 1))						/* L8  NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(C, 6))						/* B11 NC */
-UNUSED(PIN(E, 2))						/* B8  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(0, 0))						/* D11 NC */
-UNUSED(PIN(3, 2))						/* E5  NC */
-UNUSED(PIN(D, 6))						/* F6  NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(D, 2))						/* C11 NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(9, 3))						/* M11 NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/ambassador/led.c b/board/ambassador/led.c
deleted file mode 100644
index 659a63a483..0000000000
--- a/board/ambassador/led.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		red = 1;
-		white = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec.
- */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task.
-	 */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/ambassador/usb_pd_policy.c b/board/ambassador/usb_pd_policy.c
deleted file mode 100644
index 5bc754453a..0000000000
--- a/board/ambassador/usb_pd_policy.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Puff boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000_A);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	/* Ignore non-PD ports (the barrel jack). */
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return 0;
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/board/ambassador/vif_override.xml b/board/ambassador/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/ambassador/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/ampton/battery.c b/board/ampton/battery.c
deleted file mode 100644
index ee9b9b96e9..0000000000
--- a/board/ampton/battery.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-
-/*
- * Battery info for all ampton/apel battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C214] = {
-		.fuel_gauge = {
-			.manuf_name = "AS1GUXd3KB",
-			.device_name = "C214-43",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,
-			.voltage_normal = 11550,
-			.voltage_min = 9000,
-			.precharge_current = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_C204EE] = {
-		.fuel_gauge = {
-			.manuf_name = "AS1GVCD3KB",
-			.device_name = "C204-35",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,
-			.voltage_normal = 11550,
-			.voltage_min = 9000,
-			.precharge_current = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_C424] = {
-		.fuel_gauge = {
-			.manuf_name = "AS2GVID3jB",
-			.device_name = "C424-35",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,
-			.voltage_normal = 11550,
-			.voltage_min = 9000,
-			.precharge_current = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C214;
diff --git a/board/ampton/board.c b/board/ampton/board.c
deleted file mode 100644
index 1634f02991..0000000000
--- a/board/ampton/board.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Ampton/Apel board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/sync.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/usb_mux/it5205.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-static uint8_t sku_id;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_PD_INT_ODL)
-		sn5s330_interrupt(0);
-	else if (signal == GPIO_USB_C1_PD_INT_ODL)
-		sn5s330_interrupt(1);
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_C0_PD_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PD_INT_ODL) == 0;
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* USB-C MUX Configuration */
-
-#define USB_PD_PORT_ITE_0      0
-#define USB_PD_PORT_ITE_1      1
-
-static int tune_mux(const struct usb_mux *me);
-
-const struct usb_mux ampton_usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		/* Use PS8751 as mux only */
-		.usb_port = USB_PD_PORT_ITE_0,
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &ps8xxx_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &tune_mux,
-	},
-	[USB_PD_PORT_ITE_1] = {
-		/* Use PS8751 as mux only */
-		.usb_port = USB_PD_PORT_ITE_1,
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &ps8xxx_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &tune_mux,
-	}
-};
-
-/* Some external monitors can't display content normally (eg. ViewSonic VX2880).
- * We need to turn the mux for monitors to function normally.
- */
-static int tune_mux(const struct usb_mux *me)
-{
-	/* Auto EQ disabled, compensate for channel lost up to 3.6dB */
-	RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98));
-	/* DP output swing adjustment +15% */
-	RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION,
-			       0xc0));
-
-	return EC_SUCCESS;
-}
-/******************************************************************************/
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {.name = "VBUS_C0",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH13},
-	/* Vbus C1 sensing (10x voltage divider). SUB_EC_ADC */
-	[ADC_VBUS_C1] = {.name = "VBUS_C1",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH14},
-	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_AMB] = {.name = "TEMP_AMB",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH3},
-	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_CHARGER] = {.name = "TEMP_CHARGER",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH5},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t gyro_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-static const struct motion_sensor_t motion_sensor_bma253 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA255,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma2x2_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_bma253_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = BMA255_ACCEL_MIN_FREQ,
-	.max_frequency = BMA255_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &gyro_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[VSYNC] = {
-	 .name = "Camera VSYNC",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	/* SKU IDs of Ampton & unprovisioned: 1, 2, 3, 4, 255 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4
-		|| sku_id == 255;
-	}
-
-static int board_with_sensor_bma253(void)
-{
-	/* SKU ID 3 and 4 of Ampton with BMA253 */
-	return sku_id == 3 || sku_id == 4;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-		if (board_with_sensor_bma253())
-			motion_sensors[LID_ACCEL] = motion_sensor_bma253;
-
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void board_customize_usbc_mux(uint32_t board_version)
-{
-	if (board_version > 0) {
-		/* not proto, override the mux setting */
-		memcpy(usb_muxes, ampton_usb_muxes, sizeof(ampton_usb_muxes));
-	}
-}
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) != EC_SUCCESS)
-		return;
-	sku_id = val;
-	ccprints("SKU: %d", sku_id);
-
-	board_update_sensor_config_from_sku();
-
-	if (cbi_get_board_version(&val) != EC_SUCCESS)
-		return;
-	ccprints("Board version: %d", val);
-	board_customize_usbc_mux(val);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate_late(void)
-{
-	/*
-	 * Set KSO/KSI pins to GPIO input function to disable keyboard scan
-	 * while hibernating. This also prevent leakage current caused
-	 * by internal pullup of keyboard scan module.
-	 */
-	gpio_set_flags_by_mask(GPIO_KSO_H, 0xff, GPIO_INPUT);
-	gpio_set_flags_by_mask(GPIO_KSO_L, 0xff, GPIO_INPUT);
-	gpio_set_flags_by_mask(GPIO_KSI, 0xff, GPIO_INPUT);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/78344554): pass this signal upstream once hardware reworked */
-	cprints(CC_USBPD, "p%d: overcurrent!", port);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
diff --git a/board/ampton/board.h b/board/ampton/board.h
deleted file mode 100644
index c72378d625..0000000000
--- a/board/ampton/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Ampton/Apel board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_ITE8320
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_LED_COMMON
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
-
-/* Sensors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300
-
-#define CONFIG_ACCEL_BMA255	/* Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-/* Keyboard backlight is unimplemented in hardware */
-#undef CONFIG_PWM
-#undef CONFIG_PWM_KBLIGHT
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS_C0,
-	ADC_VBUS_C1,
-	ADC_TEMP_SENSOR_AMB,
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_C214,
-	BATTERY_C204EE,
-	BATTERY_C424,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ampton/build.mk b/board/ampton/build.mk
deleted file mode 100644
index cc6b73093e..0000000000
--- a/board/ampton/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/ampton/ec.tasklist b/board/ampton/ec.tasklist
deleted file mode 100644
index 2703dd0b5c..0000000000
--- a/board/ampton/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE)
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc
deleted file mode 100644
index 724d9a98d9..0000000000
--- a/board/ampton/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(E, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(WP_L,		 PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_SERVO_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(H, 6), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(H, 5), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-GPIO_INT(AC_PRESENT, 	 PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)		/* ACOK_OD */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-/* Other interrupts */
-GPIO_INT(TABLET_MODE_L,		PIN(H, 4), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(D, 6), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(D, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-GPIO(PCH_PLTRST_L,	 PIN(E, 3), GPIO_INPUT)		/* PLT_RST_L: Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(B, 6), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(K, 7), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(C, 5), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(D, 1), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L, 	 PIN(D, 0), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(K, 2), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(K, 3), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(K, 5), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(K, 1), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(D, 7), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 6), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(K, 4), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(B, 5), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(A, 2), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L, 	 PIN(C, 0), GPIO_INPUT)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(C, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 3), GPIO_INPUT)		/* EC_I2C_POWER_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_POWER_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(C, 1), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C1_SDA,		 PIN(C, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-GPIO(I2C2_SCL,		 PIN(F, 6), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(F, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C4_SCL,		 PIN(E, 0), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C4_SDA,		 PIN(E, 7), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C5_SCL,		 PIN(A, 4), GPIO_INPUT)		/* EC_I2C_PROG_SCL */
-GPIO(I2C5_SDA,		 PIN(A, 5), GPIO_INPUT)		/* EC_I2C_PROG_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(B, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(H, 3), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(K, 0), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(K, 6), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(J, 0), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* C0 DP Hotplug Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(J, 1), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* C1 DP Hotplug Detect */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(A, 0), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(I, 0), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(J, 4), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(J, 5), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C0_PD_RST_ODL,     PIN(L, 6), GPIO_ODR_HIGH)	/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_ODL,     PIN(L, 7), GPIO_ODR_HIGH)	/* C1 PD Reset */
-
-GPIO(CCD_MODE_ODL,	    PIN(C, 4), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_AMBER,  PIN(A, 6), GPIO_OUT_LOW)		/* LED_1_EC */
-GPIO(BAT_LED_WHITE,  PIN(A, 3), GPIO_OUT_LOW)		/* LED_2_EC */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L, PIN(E, 6), GPIO_ODR_HIGH)
-
-GPIO(WFCAM_VSYNC,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOB2_NC,	     PIN(B, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG0_NC,	     PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG1_NC,	     PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH0_NC,	     PIN(H, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL2_NC,	     PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC,	     PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC,	     PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD3_NC,      PIN(D, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOI1_NC,      PIN(I, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO12_NC,      PIN(I, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(B, 0x03), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x18), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, 0x06), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C1 - 1.8V */
-ALTERNATE(PIN_MASK(F, 0xC0), 0, MODULE_I2C, 0)		/* I2C2 */
-ALTERNATE(PIN_MASK(E, 0x81), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, 0x30), 0, MODULE_I2C, 0)		/* I2C5 */
-ALTERNATE(PIN_MASK(L, 0x03), 0, MODULE_ADC, 0)		/* ADC13 & ADC14: ADC_USB_C0_VBUS & ADC_USB_C1_VBUS */
-ALTERNATE(PIN_MASK(I, 0x28), 0, MODULE_ADC, 0)		/* ADC3 & ADC5: TEMP_SENSOR_AMB & TEMP_SENSOR_CHARGER */
diff --git a/board/ampton/led.c b/board/ampton/led.c
deleted file mode 100644
index e8c2c35d11..0000000000
--- a/board/ampton/led.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Ampton
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 94;
-
-/* Ampton: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_WHITE, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/ampton/vif_override.xml b/board/ampton/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/ampton/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/anahera/battery.c b/board/anahera/battery.c
deleted file mode 100644
index 95ca9be206..0000000000
--- a/board/anahera/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Anahera battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* 996QA193H Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-	/* B00C407792D0001 CosMX Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/anahera/board.c b/board/anahera/board.c
deleted file mode 100644
index c1de2df6ac..0000000000
--- a/board/anahera/board.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "peripheral_charger.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/anahera/board.h b/board/anahera/board.h
deleted file mode 100644
index c2a2c09796..0000000000
--- a/board/anahera/board.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Anahera board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-/* Sensors */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-#undef CONFIG_GMR_TABLET_MODE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* TODO: b/193452481 - measure and check these values on redrix */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/*
- * see b/174768555#comment22
- */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x58
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* Fan features */
-#define CONFIG_FANS		FAN_CH_COUNT
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR,
-	ADC_TEMP_SENSOR_2_SOC,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_REGULATOR,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR,
-	TEMP_SENSOR_2_SOC,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_REGULATOR,
-	TEMP_SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/anahera/build.mk b/board/anahera/build.mk
deleted file mode 100644
index ebfbe57fdc..0000000000
--- a/board/anahera/build.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Anahera board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/anahera/charger.c b/board/anahera/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/anahera/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/anahera/ec.tasklist b/board/anahera/ec.tasklist
deleted file mode 100644
index 5cf454d4c2..0000000000
--- a/board/anahera/ec.tasklist
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/anahera/fans.c b/board/anahera/fans.c
deleted file mode 100644
index c177df5578..0000000000
--- a/board/anahera/fans.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* TOOD(b/193487913): need to update for real fan */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
diff --git a/board/anahera/fw_config.c b/board/anahera/fw_config.c
deleted file mode 100644
index e59688b17d..0000000000
--- a/board/anahera/fw_config.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union redrix_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for redrix if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union redrix_cbi_fw_config fw_config_defaults = {
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Redrix FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		}
-	}
-}
-
-union redrix_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-bool ec_cfg_has_eps(void)
-{
-	return (fw_config.eps == EPS_ENABLED);
-}
diff --git a/board/anahera/fw_config.h b/board/anahera/fw_config.h
deleted file mode 100644
index 6480f07b35..0000000000
--- a/board/anahera/fw_config.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Redrix board.
- *
- * Source of truth is the project/brya/redrix/config.star configuration file.
- */
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-enum ec_cfg_eps_type {
-	EPS_DISABLED = 0,
-	EPS_ENABLED = 1
-};
-
-union redrix_cbi_fw_config {
-	struct {
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				lte_db : 2;
-		uint32_t				ufc : 2;
-		enum ec_cfg_eps_type			eps : 1;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union redrix_cbi_fw_config get_fw_config(void);
-
-/**
- * Check if the FW_CONFIG has enabled privacy screen.
- *
- * @return true if board supports privacy screen, false if the board
- * doesn't support it.
- */
-bool ec_cfg_has_eps(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/anahera/gpio.inc b/board/anahera/gpio.inc
deleted file mode 100644
index ceb5087bd4..0000000000
--- a/board/anahera/gpio.inc
+++ /dev/null
@@ -1,149 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(9, 6), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN,                    PIN(8, 6), GPIO_OUT_LOW)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,            PIN(A, 0), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* LED */
-GPIO(C0_CHARGE_LED_AMBER_L,          PIN(C, 4), GPIO_OUT_HIGH)	/* Amber C0 port */
-GPIO(C0_CHARGE_LED_WHITE_L,          PIN(C, 3), GPIO_OUT_HIGH)	/* White C0 port */
-GPIO(C1_CHARGE_LED_AMBER_L,          PIN(5, 7), GPIO_OUT_HIGH)	/* Amber C1 port */
-GPIO(C1_CHARGE_LED_WHITE_L,          PIN(9, 4), GPIO_OUT_HIGH)	/* White C1 port */
-GPIO(PWR_LED_WHITE_L,                PIN(C, 2), GPIO_OUT_HIGH)	/* Power LED */
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
-UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4 */
-UNUSED(PIN(5, 0))       /* GPIO50 */
-UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN_L */
-UNUSED(PIN(6, 0))       /* GPIO60/PWM7 */
-UNUSED(PIN(7, 3))       /* GPIO73/TA2 */
-UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
-UNUSED(PIN(9, 5))       /* GPIO95/SPIP_MISO */
-UNUSED(PIN(B, 4))       /* GPIOB4/I2C0_SDA0 */
-UNUSED(PIN(B, 5))       /* GPIOB5/I2C0_SCL0 */
-UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
-UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
-
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW)
diff --git a/board/anahera/i2c.c b/board/anahera/i2c.c
deleted file mode 100644
index 74208f4575..0000000000
--- a/board/anahera/i2c.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C1 */
-		.name = "tcpc0",
-		.port = I2C_PORT_USB_C0_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0",
-		.port = I2C_PORT_USB_C0_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0",
-		.port = I2C_PORT_USB_C0_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1,retimer1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/anahera/keyboard.c b/board/anahera/keyboard.c
deleted file mode 100644
index 90506163d9..0000000000
--- a/board/anahera/keyboard.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
-		TK_PLAY_PAUSE,		/* T9 */
-		TK_MICMUTE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config keybd2 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_PRIVACY_SCRN_TOGGLE,	/* T8 */
-		TK_KBD_BKLIGHT_TOGGLE,	/* T9 */
-		TK_MICMUTE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config *
-board_vivaldi_keybd_config(void)
-{
-	if (ec_cfg_has_eps() == 0)
-		return &keybd1;
-	else
-		return &keybd2;
-}
diff --git a/board/anahera/led.c b/board/anahera/led.c
deleted file mode 100644
index bd088bfe97..0000000000
--- a/board/anahera/led.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Redrix
- */
-
-#include <stdint.h>
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "task.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICK_INTERVAL_MS (500 * MSEC)
-#define LED_CYCLE_TIME_MS    (2000 * MSEC)
-#define LED_TICKS_PER_CYCLE  (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS       (1000 * MSEC)
-#define LED_ON_TICKS         (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
-				 GPIO_C0_CHARGE_LED_AMBER_L);
-	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
-				 GPIO_C0_CHARGE_LED_WHITE_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static unsigned int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x1) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static unsigned int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-void led_task(void *u)
-{
-	uint32_t start_time;
-	uint32_t task_duration;
-
-	while (1) {
-		start_time = get_time().le.lo;
-
-		if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-			led_set_power();
-
-		led_set_battery();
-
-		/* Compute time for this iteration */
-		task_duration = get_time().le.lo - start_time;
-		/*
-		 * Compute wait time required to for next desired LED tick. If
-		 * the duration exceeds the tick time, then don't sleep.
-		 */
-		if (task_duration < LED_TICK_INTERVAL_MS)
-			usleep(LED_TICK_INTERVAL_MS - task_duration);
-	}
-}
diff --git a/board/anahera/pwm.c b/board/anahera/pwm.c
deleted file mode 100644
index 54d0d05afb..0000000000
--- a/board/anahera/pwm.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/anahera/sensors.c b/board/anahera/sensors.c
deleted file mode 100644
index 43fc7ef045..0000000000
--- a/board/anahera/sensors.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "adc_chip.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR] = {
-		.name = "TEMP_DDR",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_SOC] = {
-		.name = "TEMP_SOC",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_REGULATOR] = {
-		.name = "TEMP_REGULATOR",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR] = {
-		.name = "DDR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR
-	},
-	[TEMP_SENSOR_2_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SOC
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_REGULATOR] = {
-		.name = "Regulator",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_REGULATOR
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_ddr = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to SOC, so we need to use the lower
- * SOC temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_regulator = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR] = thermal_ddr,
-	[TEMP_SENSOR_2_SOC] = thermal_cpu,
-	[TEMP_SENSOR_3_CHARGER] = thermal_charger,
-	[TEMP_SENSOR_4_REGULATOR] = thermal_regulator,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/anahera/usbc_config.c b/board/anahera/usbc_config.c
deleted file mode 100644
index 73a7b402cc..0000000000
--- a/board/anahera/usbc_config.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C1 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_C1_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C1) {
-		rst_signal = IOEX_USB_C1_RT_RST_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 1);
-
-	nct38xx_reset_notify(USBC_PORT_C0);
-	nct38xx_reset_notify(USBC_PORT_C1);
-
-	/* wait for chips to come up */
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-static void board_tcpc_init(void)
-{
-	int i;
-
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i) {
-			ioex_config[i].flags &= ~IOEX_FLAGS_DISABLED;
-			ioex_init(i);
-		}
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/anahera/usbc_config.h b/board/anahera/usbc_config.h
deleted file mode 100644
index c314466f77..0000000000
--- a/board/anahera/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Anahera board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/anahera/vif_override.xml b/board/anahera/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/anahera/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/asurada/battery.c b/board/asurada/battery.c
deleted file mode 100644
index 6237a5058c..0000000000
--- a/board/asurada/battery.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "usb_pd.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
diff --git a/board/asurada/board.c b/board/asurada/board.c
deleted file mode 100644
index b57d327015..0000000000
--- a/board/asurada/board.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Asurada board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/als_tcs3400.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable motion sensor interrupt */
-	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
-	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Sensor */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct stprivate_data g_lis2dwl_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-static enum base_accelgyro_type base_accelgyro_config;
-
-#ifdef BOARD_ASURADA_REV0
-/* Matrix to rotate accelerometer into standard reference frame */
-/* for rev 0 */
-static const mat33_fp_t base_standard_ref_rev0 = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)},
-};
-
-static void update_rotation_matrix(void)
-{
-	motion_sensors[BASE_ACCEL].rot_standard_ref =
-		&base_standard_ref_rev0;
-	motion_sensors[BASE_GYRO].rot_standard_ref =
-		&base_standard_ref_rev0;
-}
-DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	/*
-	 * TODO: calculate the actual coefficients and scaling factors
-	 */
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.1),
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-#endif /* BOARD_ASURADA_REV0 */
-
-#ifdef BOARD_HAYATO
-/* Matrix to rotate accelerometer into standard reference frame */
-/* for Hayato */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0 , 0},
-	{0, 0, FLOAT_TO_FP(1)},
-};
-
-static void update_rotation_matrix(void)
-{
-	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
-		return;
-
-	if (board_get_version() >= 2) {
-		motion_sensors[BASE_ACCEL].rot_standard_ref =
-			&base_standard_ref;
-		motion_sensors[BASE_GYRO].rot_standard_ref =
-			&base_standard_ref;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
-
-#endif
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
-	.rot_standard_ref = NULL,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = NULL,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = NULL, /* identity matrix */
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = NULL, /* identity matrix */
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.int_signal = GPIO_LID_ACCEL_INT_L,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = NULL, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-#ifdef BOARD_ASURADA_REV0
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-	[RGB_ALS] = {
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		/* freq = 0 indicates we should not use sensor directly */
-		.min_frequency = 0,
-		.max_frequency = 0,
-	},
-#endif /* BOARD_ASURADA_REV0 */
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void board_detect_motionsense(void)
-{
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (base_accelgyro_config != BASE_GYRO_NONE)
-		return;
-
-	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
-	if (val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		base_accelgyro_config =  BASE_GYRO_ICM426XX;
-		ccprints("Base Accelgyro: ICM426XX");
-	} else {
-		base_accelgyro_config = BASE_GYRO_BMI160;
-		ccprints("Base Accelgyro: BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
-	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM */
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED3] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-int board_accel_force_mode_mask(void)
-{
-	int version = board_get_version();
-
-	if (version == -1 || version >= 2)
-		return 0;
-	return BIT(LID_ACCEL);
-}
-
-static void board_suspend(void)
-{
-	if (board_get_version() >= 3)
-		gpio_set_level(GPIO_EN_5V_USM, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	if (board_get_version() >= 3)
-		gpio_set_level(GPIO_EN_5V_USM, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/asurada/board.h b/board/asurada/board.h
deleted file mode 100644
index d8ee03c9f4..0000000000
--- a/board/asurada/board.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Asurada board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Chipset config */
-
-/* Optional features */
-#define CONFIG_LTO
-
-/*
- * TODO: Remove this option once the VBAT no longer keeps high when
- * system's power isn't presented.
- */
-#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-
-/* BC12 */
-/* TODO(b/159583342): remove after rev0 deprecated */
-#define CONFIG_MT6360_BC12_GPIO
-
-/* LED */
-#ifdef BOARD_HAYATO
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#endif
-
-/* PD / USB-C / PPC */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define PD_MAX_CURRENT_MA 3000
-#define PD_OPERATING_POWER_MW 15000
-#ifdef BOARD_HAYATO
-#define PD_MAX_VOLTAGE_MV 15000
-#define PD_MAX_POWER_MW 45000
-#else
-#define PD_MAX_VOLTAGE_MV 20000
-#define PD_MAX_POWER_MW 60000
-#endif
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* Optional console commands */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
-
-/* Sensor */
-#define CONFIG_GMR_TABLET_MODE
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#ifdef BOARD_ASURADA_REV0
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-#else
-/* TODO(b/171931139): remove this after rev1 board deprecated */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (board_accel_force_mode_mask())
-#endif
-
-/* SPI / Host Command */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* USB-A */
-#define USBA_PORT_COUNT 1
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_TYPE_COUNT,
-};
-
-enum sensor_id {
-	BASE_ACCEL = 0,
-	BASE_GYRO,
-	LID_ACCEL,
-#ifdef BOARD_ASURADA_REV0
-	CLEAR_ALS,
-	RGB_ALS,
-#endif
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_VBUS_C0,             /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_VBUS_C1,             /* ADC 5 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
-
-	/* Number of ADC channels */
-	ADC_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1,
-	PWM_CH_LED2,
-	PWM_CH_LED3,
-	PWM_CH_COUNT,
-};
-
-int board_accel_force_mode_mask(void);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/asurada/build.mk b/board/asurada/build.mk
deleted file mode 100644
index d6866f8568..0000000000
--- a/board/asurada/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=asurada
-
-board-$(BOARD_HAYATO)=led_hayato.o
-board-$(BOARD_ASURADA)=led.o
-board-y+=battery.o board.o
-board-y+=usbc_config.o
diff --git a/board/asurada/ec.tasklist b/board/asurada/ec.tasklist
deleted file mode 100644
index ff47718bae..0000000000
--- a/board/asurada/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, 1024) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
-
diff --git a/board/asurada/gpio.inc b/board/asurada/gpio.inc
deleted file mode 100644
index 75d1fbafa5..0000000000
--- a/board/asurada/gpio.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
-	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* H1_EC_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         lid_interrupt)
-GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Chipset interrupts */
-GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_IMU_INT_L,     PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         motion_interrupt)
-GPIO_INT(LID_ACCEL_INT_L,    PIN(J, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         lis2dw12_interrupt)
-#ifdef BOARD_ASURADA_REV0
-GPIO_INT(ALS_RGB_INT_ODL,    PIN(F, 0), GPIO_INT_FALLING,
-         tcs3400_interrupt)
-#else
-GPIO(ALS_RGB_INT_ODL,        PIN(F, 0), GPIO_INPUT)
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_L,  PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-/* Note that netnames are reversed in asurada rev 0/1 */
-GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-
-/* Other interrupts */
-GPIO_INT(AP_XHCI_INIT_DONE,  PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         usb_a0_interrupt)
-#ifdef BOARD_ASURADA_REV0
-GPIO_INT(AC_PRESENT,         PIN(M, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         extpower_interrupt) /* AC_OK / AC_PRESENT in rev0 */
-#else /* HAYATO */
-GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
-#endif
-GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         switch_interrupt) /* EC_FLASH_WP_OD */
-GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-GPIO_INT(X_EC_GPIO2,         PIN(B, 2), GPIO_ODR_HIGH, x_ec_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
-GPIO(PG_MT6315_PROC_ODL,     PIN(E, 1), GPIO_INPUT)
-GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
-GPIO(PG_PP5000_A_ODL,        PIN(A, 6), GPIO_INPUT)
-GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
-GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
-
-/* USB and USBC Signals */
-GPIO(DP_AUX_PATH_SEL,        PIN(G, 0), GPIO_OUT_HIGH)
-GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_USB_A0_VBUS,  PIN(B, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,          PIN(H, 3), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
-GPIO(BC12_DET_EN,            PIN(J, 5), GPIO_OUT_LOW) /* EN_USB_C0_BC12_DET */
-GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
-GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
-GPIO(EN_5V_USM,              PIN(D, 7), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
-GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
-
-/* SPI pins - Alternate function below configures SPI module on these pins */
-
-/* NC / TP */
-
-/* Keyboard pins */
-
-/* Subboards HDMI/TYPEC */
-GPIO(EC_X_GPIO1,             PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EC_X_GPIO3,             PIN(J, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, 0x07), 1, MODULE_PWM, 0) /* PWM 0~2 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0x6F), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,5,6 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
-
-/* Unimplemented Pins  */
-GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-GPIO(PACKET_MODE_EN,         PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-/* b/160218054: behavior not defined */
-/* *_ODL pin has external pullup so don't pull it down. */
-GPIO(USB_A0_FAULT_ODL,       PIN(A, 7), GPIO_INPUT)
-GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3), GPIO_INPUT)
-GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
-GPIO(EN_PP3000_SD_U,         PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-/* reserved for future use */
-GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
-/*
- * ADC pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPI7,                PIN(I, 7), GPIO_OUT_LOW)
-/* NC pins, enable internal pull-up/down to avoid floating state. */
-#ifdef BOARD_ASURADA_REV0
-GPIO(NC_GPE5,                PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)
-#else /* HAYATO */
-GPIO(NC_GPM2,                PIN(M, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-#endif
-GPIO(NC_GPM3,                PIN(M, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-/*
- * These 4 pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPG3,                PIN(G, 3), GPIO_OUT_LOW)
-GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
-GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
-GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/asurada/led.c b/board/asurada/led.c
deleted file mode 100644
index 166ece92e9..0000000000
--- a/board/asurada/led.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Asurada
- */
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "driver/bc12/mt6360.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "stdbool.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-#define LED_OFF EC_LED_COLOR_COUNT
-
-const enum ec_led_id supported_led_ids[] = {
-	/* Main LED */
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-
-	/* Not used, give them some random name for testing */
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static void led_set_color_left(enum ec_led_colors color, int duty)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB2, duty);
-	mt6360_led_set_brightness(MT6360_LED_RGB3, duty);
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 1);
-		break;
-	case EC_LED_COLOR_WHITE:
-		mt6360_led_enable(MT6360_LED_RGB2, 1);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	}
-}
-
-static void led_set_color_right(enum ec_led_colors color, int duty)
-{
-	pwm_set_duty(PWM_CH_LED2, duty);
-	pwm_set_duty(PWM_CH_LED3, duty);
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED2, 0);
-		pwm_enable(PWM_CH_LED3, 1);
-		break;
-	case EC_LED_COLOR_WHITE:
-		pwm_enable(PWM_CH_LED2, 1);
-		pwm_enable(PWM_CH_LED3, 0);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED2, 0);
-		pwm_enable(PWM_CH_LED3, 0);
-		break;
-	}
-}
-
-static void led_set_color_power(enum ec_led_colors color, int duty)
-{
-	pwm_set_duty(PWM_CH_LED1, duty);
-	pwm_enable(PWM_CH_LED1, color == EC_LED_COLOR_WHITE);
-}
-
-static void led_set_color_battery(enum ec_led_colors color, int duty)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB1, duty);
-	mt6360_led_enable(MT6360_LED_RGB1, color == EC_LED_COLOR_WHITE);
-}
-
-static enum ec_error_list set_color(enum ec_led_id led_id,
-				    enum ec_led_colors color,
-				    int duty)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		led_set_color_left(color, duty);
-		return EC_SUCCESS;
-	case EC_LED_ID_RIGHT_LED:
-		led_set_color_right(color, duty);
-		return EC_SUCCESS;
-	case EC_LED_ID_POWER_LED:
-		led_set_color_power(color, duty);
-		return EC_SUCCESS;
-	case EC_LED_ID_BATTERY_LED:
-		led_set_color_battery(color, duty);
-		return EC_SUCCESS;
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_AMBER] =
-			MT6360_LED_BRIGHTNESS_MAX;
-		brightness_range[EC_LED_COLOR_WHITE] =
-			MT6360_LED_BRIGHTNESS_MAX;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_AMBER] = 100;
-		brightness_range[EC_LED_COLOR_WHITE] = 100;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 100;
-		break;
-	case EC_LED_ID_BATTERY_LED:
-		brightness_range[EC_LED_COLOR_WHITE] =
-			MT6360_LED_BRIGHTNESS_MAX;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(led_id, EC_LED_COLOR_AMBER,
-				 brightness[EC_LED_COLOR_AMBER]);
-	if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(led_id, EC_LED_COLOR_WHITE,
-				 brightness[EC_LED_COLOR_WHITE]);
-
-	return set_color(led_id, LED_OFF, 0);
-}
-
-static void update_led(enum ec_led_id led_id, bool is_active_charge_port,
-		       int duty, int tick)
-{
-	enum charge_state power_state = charge_get_state();
-
-	if (power_state == PWR_STATE_IDLE) {
-		/* Factory mode: blinking white (2sec on + 2sec off) */
-		set_color(led_id, (tick % 8 < 4) ? EC_LED_COLOR_WHITE : LED_OFF,
-			  duty);
-	} else if (power_state == PWR_STATE_ERROR) {
-		/* Battery error: blinking amber (1sec on + 1sec off) */
-		set_color(led_id, (tick % 4 < 2) ? EC_LED_COLOR_AMBER : LED_OFF,
-			  duty);
-	} else if (is_active_charge_port) {
-		/*
-		 * Active charge port: amber when charging, white if fully
-		 * charged.
-		 */
-		if (power_state == PWR_STATE_CHARGE)
-			set_color(led_id, EC_LED_COLOR_AMBER, duty);
-		else
-			set_color(led_id, EC_LED_COLOR_WHITE, duty);
-	} else {
-		/*
-		 * Non-active port:
-		 * Solid white in S0, blinking amber (3sec on + 1sec off) in S3,
-		 * and LED off in S5
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			set_color(led_id, EC_LED_COLOR_WHITE, duty);
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			set_color(
-				led_id,
-				(tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF,
-				duty);
-		else
-			set_color(led_id, LED_OFF, 0);
-
-	}
-}
-
-static void led_tick(void)
-{
-	static int tick;
-	int port = charge_manager_get_active_charge_port();
-
-	++tick;
-	/* Pick duty 1 and 50 respectively to have same brightness */
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		update_led(EC_LED_ID_LEFT_LED, port == 0, 1, tick);
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		update_led(EC_LED_ID_RIGHT_LED, port == 1, 50, tick);
-	/* Turn off unused LEDs */
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		set_color(EC_LED_ID_BATTERY_LED, LED_OFF, 0);
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/asurada/led_hayato.c b/board/asurada/led_hayato.c
deleted file mode 100644
index 1d3108c47b..0000000000
--- a/board/asurada/led_hayato.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-#include "driver/bc12/mt6360.h"
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB2, 50);
-	mt6360_led_set_brightness(MT6360_LED_RGB3, 50);
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 1);
-		break;
-	case EC_LED_COLOR_WHITE:
-		mt6360_led_enable(MT6360_LED_RGB2, 1);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB1, 1);
-	mt6360_led_enable(MT6360_LED_RGB1, color == EC_LED_COLOR_WHITE);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] =
-				MT6360_LED_BRIGHTNESS_MAX;
-		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/asurada/usbc_config.c b/board/asurada/usbc_config.c
deleted file mode 100644
index 2f35816abb..0000000000
--- a/board/asurada/usbc_config.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada board-specific USB-C configuration */
-
-#include "driver/ppc/syv682x.h"
-#include "driver/usb_mux/ps8743.h"
-#include "hooks.h"
-
-__override int syv682x_board_is_syv682c(int port)
-{
-	return board_get_version() > 2;
-}
-
-void board_usb_mux_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC) {
-		ps8743_tune_usb_eq(&usb_muxes[1],
-				   PS8743_USB_EQ_TX_12_8_DB,
-				   PS8743_USB_EQ_RX_12_8_DB);
-		ps8743_write(&usb_muxes[1],
-				   PS8743_REG_HS_DET_THRESHOLD,
-				   PS8743_USB_HS_THRESH_NEG_10);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/asurada/vif_override.xml b/board/asurada/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/asurada/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h
deleted file mode 100644
index e25a26dec0..0000000000
--- a/board/asurada_scp/board.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Asurada SCP configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/*
- * RW only, no flash
- * +-------------------- 0x0
- * | ROM vectortable, .text, .rodata, .data LMA
- * +-------------------- 0x58000
- * | RAM .bss, .data
- * +-------------------- 0x0ffc00
- * | Reserved (padding for 1k-alignment)
- * +-------------------- 0x0ffdb0
- * | IPI shared buffer with AP (288 + 8) * 2
- * +-------------------- 0x100000
- */
-#define CONFIG_ROM_BASE 0x0
-#define CONFIG_RAM_BASE 0x58000
-#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \
-			 CONFIG_RAM_BASE)
-
-#define SCP_FW_END 0x100000
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/asurada_scp/build.mk b/board/asurada_scp/build.mk
deleted file mode 100644
index f3c4a82a10..0000000000
--- a/board/asurada_scp/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=mt_scp
-CHIP_VARIANT:=mt8192
-BASEBOARD:=mtscp-rv32i
diff --git a/board/asurada_scp/ec.tasklist b/board/asurada_scp/ec.tasklist
deleted file mode 100644
index 6e2f613c6d..0000000000
--- a/board/asurada_scp/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, TRENTA_TASK_STACK_SIZE)
diff --git a/board/asurada_scp/gpio.inc b/board/asurada_scp/gpio.inc
deleted file mode 100644
index 3222a34e08..0000000000
--- a/board/asurada_scp/gpio.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
diff --git a/board/atlas/battery.c b/board/atlas/battery.c
deleted file mode 100644
index fb2fba18be..0000000000
--- a/board/atlas/battery.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
-
-enum battery_type {
-	BATTERY_LG,
-	BATTERY_LISHEN,
-	BATTERY_SIMPLO,
-	BATTERY_TYPE_COUNT,
-};
-
-struct board_batt_params {
-	const char *manuf_name;
-	const struct battery_info *batt_info;
-};
-
-/*
- * Set LISHEN as default since the LG precharge current level could cause the
- * LISHEN battery to not accept charge when it's recovering from a fully
- * discharged state.
- */
-#define DEFAULT_BATTERY_TYPE BATTERY_LISHEN
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-/* Battery may delay reporting battery present */
-static int battery_report_present = 1;
-
-/*
- * Battery info for LG A50. Note that the fields start_charging_min/max and
- * charging_min/max are not used for the Eve charger. The effective temperature
- * limits are given by discharging_min/max_c.
- */
-static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
-};
-
-/*
- * Battery info for LISHEN. Note that the fields start_charging_min/max and
- * charging_min/max are not used for the Eve charger. The effective temperature
- * limits are given by discharging_min/max_c.
- */
-static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
-};
-
-static const struct board_batt_params info[] = {
-	[BATTERY_LG] = {
-		.manuf_name = "LG A50",
-		.batt_info = &batt_info_lg,
-	},
-
-	[BATTERY_LISHEN] = {
-		.manuf_name = "Lishen A50",
-		.batt_info = &batt_info_lishen,
-	},
-
-	[BATTERY_SIMPLO] = {
-		.manuf_name = "Simplo A50",
-		.batt_info = &batt_info_lishen,
-	},
-
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	char name[3];
-	int i;
-
-	if (!battery_manufacturer_name(name, sizeof(name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
-				board_battery_type = i;
-				break;
-			}
-		}
-	}
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt: %s", info[board_battery_type].manuf_name);
-	else
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* Can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-	if (curr->batt.flags & BATT_FLAG_BAD_STATUS)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    !(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	return 0;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	const struct battery_info *batt_info;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c;
-	int disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	if (curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)
-		return 0;
-
-	bat_temp_c = curr->batt.temperature - 2731;
-	batt_info = battery_get_info();
-	/* Don't charge if outside of allowable temperature range */
-	if (bat_temp_c >= batt_info->charging_max_c * 10 ||
-	    bat_temp_c < batt_info->charging_min_c * 10) {
-		curr->requested_current = 0;
-		curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-	}
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATTERY_PRESENT_L) ? BP_NO : BP_YES;
-}
-
-/* Allow booting now that the battery has woke up */
-static void battery_now_present(void)
-{
-	CPRINTS("battery will now report present");
-	battery_report_present = 1;
-}
-DECLARE_DEFERRED(battery_now_present);
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	if (battery_hw_present() == BP_NO || battery_is_cut_off())
-		return BP_NO;
-
-	return BP_YES;
-}
diff --git a/board/atlas/board.c b/board/atlas/board.c
deleted file mode 100644
index 4881ed6898..0000000000
--- a/board/atlas/board.c
+++ /dev/null
@@ -1,629 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atlas board-specific configuration */
-
-#include "adc_chip.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/als_opt3001.h"
-#include "driver/pmic_bd99992gw.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "espi.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power_button.h"
-#include "power.h"
-#include "pwm_chip.h"
-#include "pwm.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-#include "gpio_list.h"
-
-/* Keyboard scan. Increase output_settle_us to 80us from default 50us. */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]       = { 3, 0, 10000 },
-	[PWM_CH_DB0_LED_BLUE]  = {
-		0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_RED]   = {
-		2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_GREEN] = {
-		6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_BLUE]  = {
-		1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_RED]   = {
-		7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_GREEN] = {
-		5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_ROP_EC_ACOK,
-	GPIO_LID_OPEN,
-	GPIO_MECH_PWR_BTN_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-const struct adc_t adc_channels[] = {
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT*1000/18,
-		ADC_READ_MAX+1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
-	 * 0.8V @ 45 W, i.e. 56250 uW/mV. Using ADC_MAX_VOLT*56250 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"power",   I2C_PORT_POWER,   100,
-	 GPIO_EC_I2C0_POWER_SCL,      GPIO_EC_I2C0_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   1000,
-	 GPIO_EC_I2C1_USB_C0_SCL,     GPIO_EC_I2C1_USB_C0_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   1000,
-	 GPIO_EC_I2C2_USB_C1_SCL,     GPIO_EC_I2C2_USB_C1_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  100,
-	 GPIO_EC_I2C3_SENSOR_3V3_SCL, GPIO_EC_I2C3_SENSOR_3V3_SDA},
-	{"battery", I2C_PORT_BATTERY, 100,
-	 GPIO_EC_I2C4_BATTERY_SCL,    GPIO_EC_I2C4_BATTERY_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		/* left port */
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = I2C_ADDR_TCPC_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	{
-		/* right port */
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = I2C_ADDR_TCPC_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_PD_RST_L, 0);
-	msleep(PS8XXX_RST_L_RST_H_DELAY_MS);
-	gpio_set_level(GPIO_USB_PD_RST_L, 1);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-	/* BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		      BD99992GW_REG_RESETIRQ1, &vrfault) != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT1, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT2, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_RESETIRQ1, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_PWRSTAT1, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_PWRSTAT2, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-static void board_pmic_disable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (0)   - Disable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_VCCIOCNT, 0x3a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x2a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage 0.85V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V085ACNT, 0x2a);
-}
-
-static void board_pmic_enable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (1)   - Enable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_VCCIOCNT, 0x7a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x6a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage 0.85V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V085ACNT, 0x6a);
-}
-
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
-		board_pmic_enable_slp_s0_vr_decay();
-	else if (state == HOST_SLEEP_EVENT_S0IX_RESUME)
-		board_pmic_disable_slp_s0_vr_decay();
-}
-
-static void board_pmic_init(void)
-{
-	board_report_pmic_fault("SYSJUMP");
-
-	/* Clear power source events */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_PWRSRCINT, 0xff);
-
-	/* Disable power button shutdown timer */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_PBCONFIG, 0x00);
-
-	if (system_jumped_late())
-		return;
-
-	/* DISCHGCNT1 - enable 100 ohm discharge on VCCIO */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_DISCHGCNT1, 0x01);
-
-	/*
-	 * DISCHGCNT2 - enable 100 ohm discharge on
-	 * V5.0A, V3.3DSW, V3.3A and V1.8A
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_DISCHGCNT2, 0x55);
-
-	/*
-	 * DISCHGCNT3 - enable 500 ohm discharge on
-	 * V1.8U_2.5U
-	 * DISCHGCNT3 - enable 100 ohm discharge on
-	 * V12U, V1.00A, V0.85A
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_DISCHGCNT3, 0xd5);
-
-	/* DISCHGCNT4 - enable 100 ohm discharge on V33S, V18S, V100S */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_DISCHGCNT4, 0x15);
-
-	/* VRMODECTRL - disable low-power mode for all rails */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_VRMODECTRL, 0x1f);
-
-	/* V5ADS3CNT - boost V5A_DS3 by 2% */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V5ADS3CNT, 0x1a);
-
-	board_pmic_disable_slp_s0_vr_decay();
-}
-DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int p;
-
-	/* Configure PSL pins */
-	for (p = 0; p < hibernate_wake_pins_used; p++)
-		system_config_psl_mode(hibernate_wake_pins[p]);
-
-	/*
-	 * Enter PSL mode.  Note that on Atlas, simply enabling PSL mode does
-	 * not cut the EC's power.  Therefore, we'll need to cut off power via
-	 * the ROP PMIC afterwards.
-	 */
-	system_enter_psl_mode();
-
-	/* Cut off DSW power via the ROP PMIC. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_SDWNCTRL, BD99992GW_SDWNCTRL_SWDN);
-
-	/* Wait for power to be cut. */
-	while (1)
-		;
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	if (system_get_board_version() < ATLAS_REV_FIXED_EC_WP) {
-		int dflags;
-
-		CPRINTS("Applying EC_WP_L workaround");
-		dflags = gpio_get_default_flags(GPIO_EC_WP_L);
-		gpio_set_flags(GPIO_EC_WP_L, dflags | GPIO_PULL_UP);
-	}
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are sourcing VBUS on the port */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && is_source) {
-		CPRINTS("No charging from p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_EN_USB_C0_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USB_C1_CHARGE_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_L :
-					     GPIO_EN_USB_C1_CHARGE_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_L :
-					     GPIO_EN_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Limit the input current to 95% negotiated limit,
- * to account for the charger chip margin.
- */
-
-static int charger_derate(int current)
-{
-	return current * 95 / 100;
-}
-
-static void board_charger_init(void)
-{
-	charger_set_input_current_limit(CHARGER_SOLO,
-					charger_derate(PD_MAX_CURRENT_MA));
-}
-DECLARE_HOOK(HOOK_INIT, board_charger_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = charger_derate(charge_ma);
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_KBD_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_KBD_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-int board_get_version(void)
-{
-	static int ver;
-
-	if (!ver) {
-		/*
-		 * Read the board EC ID on the tristate strappings
-		 * using ternary encoding: 0 = 0, 1 = 1, Hi-Z = 2
-		 */
-		uint8_t id0, id1, id2;
-
-		id0 = gpio_get_ternary(GPIO_BOARD_VERSION1);
-		id1 = gpio_get_ternary(GPIO_BOARD_VERSION2);
-		id2 = gpio_get_ternary(GPIO_BOARD_VERSION3);
-
-		ver = (id2 * 9) + (id1 * 3) + id0;
-		CPRINTS("Board ID = %d", ver);
-	}
-
-	return ver;
-}
-
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ALS] = {
-		.name = "Light",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_OPT3001,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &opt3001_drv,
-		.drv_data = &g_opt3001_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = OPT3001_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x2b11a1, /* from nocturne */
-		.min_frequency = OPT3001_LIGHT_MIN_FREQ,
-		.max_frequency = OPT3001_LIGHT_MAX_FREQ,
-		.config = {
-			/* Sensor on in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
diff --git a/board/atlas/board.h b/board/atlas/board.h
deleted file mode 100644
index 56685f1856..0000000000
--- a/board/atlas/board.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atlas board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_DPTF
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_SHA256_UNROLLED
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 95
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-/* battery briefly requests V=0, A=0 when woken up */
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-
-/* LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
-#define CONFIG_LED_PWM_COUNT 2
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-
-/* Temperature Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-
-/* Sensor */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ALS
-#define CONFIG_ALS_OPT3001
-#define ALS_COUNT 1
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 1024
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* USB */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#undef CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
-#define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 2
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY /* FIXME: b/77151299 */
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL		1 /* GPIO C2 is used as PWM1. */
-#define CONFIG_HIBERNATE_PSL	/* Enable PSL pins for wakeup */
-
-/* I2C ports */
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0	/* pmic/charger */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT3_0	/* als */
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT4_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT5_0	/* accel/gyro */
-
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_PMIC		I2C_PORT_POWER
-#define I2C_PORT_THERMAL	I2C_PORT_POWER
-
-/* I2C addresses */
-#define I2C_ADDR_TCPC_FLAGS	0x0B
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_BD99992_FLAGS	0x30
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_SYSTHERM0,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_SYSTHERM1,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_SYSTHERM2,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_SYSTHERM3,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_DB0_LED_BLUE,
-	PWM_CH_DB0_LED_RED,
-	PWM_CH_DB0_LED_GREEN,
-	PWM_CH_DB1_LED_BLUE,
-	PWM_CH_DB1_LED_RED,
-	PWM_CH_DB1_LED_GREEN,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-/* LID_ALS needs to be polled */
-#define CONFIG_ACCEL_FORCE_MODE_MASK	BIT(LID_ALS)
-
-enum adc_channel {
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			60000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-int board_get_version(void);
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/*
- * these are mappings from signal names used in the atlas schematics
- * vs. names hard-coded in various parts of the EC codebase.
- */
-
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_BATTERY_PRESENT_L	GPIO_EC_BATT_PRES_L
-#define GPIO_BOARD_VERSION1	GPIO_EC_BRD_ID1
-#define GPIO_BOARD_VERSION2	GPIO_EC_BRD_ID2
-#define GPIO_BOARD_VERSION3	GPIO_EC_BRD_ID3
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KB_ROW02_INV
-#define GPIO_PCH_ACOK		GPIO_EC_PCH_ACPRESENT
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_RSMRST_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C0_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
-#define GPIO_USB_C1_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_WP_L		GPIO_EC_WP_L
-
-/* ps8751 requires 1ms reset down assertion */
-#define PS8XXX_RST_L_RST_H_DELAY_MS	1
-
-#define ATLAS_REV_FIXED_EC_WP	4
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/atlas/build.mk b/board/atlas/build.mk
deleted file mode 100644
index f1619f73cd..0000000000
--- a/board/atlas/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/atlas/ec.tasklist b/board/atlas/ec.tasklist
deleted file mode 100644
index 33e3cccb16..0000000000
--- a/board/atlas/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc
deleted file mode 100644
index 4ce44cc130..0000000000
--- a/board/atlas/gpio.inc
+++ /dev/null
@@ -1,157 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB PD interrupt handler section */
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
-
-/* power seq interrupt handler section */
-GPIO_INT(ROP_DSW_PWROK_EC,	PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(ROP_EC_RSMRST_L,	PIN(E, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(A, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_SUS_L_PCH,		PIN(D, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(ROP_EC_ACOK,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-
-/* misc interrupt handler section */
-GPIO_INT(EC_WP_L,		PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-
-/* SoC section */
-GPIO(RSMRST_L,			PIN(3, 7), GPIO_OUT_LOW)			/* SOC Resume Reset */
-GPIO(EC_PCH_PWR_BTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power button to SOC */
-GPIO(EC_PCH_RTCRST,		PIN(7, 6), GPIO_OUT_LOW)			/* RTC Reset (broken) */
-GPIO(EC_PCH_WAKE_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* PCH wake */
-GPIO(EC_PROCHOT_ODL,		PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* SOC PROCHOT# */
-GPIO(SYS_RESET_L,		PIN(0, 2), GPIO_ODR_HIGH)			/* SOC reset */
-GPIO(USB_C0_DP_HPD,		PIN(C, 5), GPIO_INPUT)				/* C0 Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(C, 6), GPIO_INPUT)				/* C1 Hotplug Detect */
-
-/* power seq section */
-GPIO(EC_PCH_ACPRESENT,		PIN(7, 3), GPIO_ODR_LOW)			/* ACOK to SOC */
-/* note: SLP_SUS_L_PMIC is an input in the schematics */
-GPIO(SLP_SUS_L_PMIC,		PIN(E, 4), GPIO_OUT_LOW)			/* SOC SLP_SUS# */
-GPIO(SLP_S4_L,	    		PIN(A, 3), GPIO_INPUT)				/* SOC SLP_S4# */
-GPIO(SLP_S3_L,			PIN(A, 6), GPIO_INPUT)				/* SOC SLP_S3# */
-GPIO(ROP_INT_L,			PIN(D, 5), GPIO_INPUT | GPIO_PULL_UP)		/* PMIC IRQ (Unused) */
-
-/* USB PD section */
-GPIO(EN_USB_C0_5V_OUT,		PIN(6, 7), GPIO_OUT_LOW)			/* C0 5V Enable */
-GPIO(EN_USB_C0_CHARGE_L,	PIN(0, 3), GPIO_OUT_LOW)			/* alt fn */
-GPIO(EN_USB_C0_3A,		PIN(6, 2), GPIO_OUT_LOW)			/* 1.5/3.0 C0 current limit selection */
-GPIO(EN_USB_C1_5V_OUT,		PIN(7, 0), GPIO_OUT_LOW)			/* C1 5V Enable */
-GPIO(EN_USB_C1_CHARGE_L,	PIN(0, 4), GPIO_OUT_LOW)			/* alt fn */
-GPIO(EN_USB_C1_3A,		PIN(8, 3), GPIO_OUT_LOW)			/* alt fn 1.5/3.0 C1 current limit selection */
-
-GPIO(USB2_VBUSSENSE,		PIN(A, 2), GPIO_OUT_LOW)			/* USB OTG ID */
-GPIO(USB2_ID,			PIN(A, 0), GPIO_OUT_LOW)			/* USB OTG VBUS Sense */
-
-GPIO(USB_PD_RST_L,		PIN(F, 1), GPIO_OUT_LOW)			/* C0,C1 PD Reset */
-
-/* misc section */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_ENTERING_RW,		PIN(E, 1), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(EC_BL_DISABLE_L,		PIN(D, 3), GPIO_INPUT)				/* Enable Backlight */
-GPIO(EC_BRD_ID1,		PIN(9, 6), GPIO_INPUT)				/* Board ID bit0 */
-GPIO(EC_BRD_ID2,		PIN(9, 3), GPIO_INPUT)				/* Board ID bit1 */
-GPIO(EC_BRD_ID3,		PIN(F, 0), GPIO_INPUT)				/* Board ID bit2 */
-GPIO(KBD_BL_EN,			PIN(7, 5), GPIO_OUT_LOW)			/* KB backlight enable */
-GPIO(EC_PLATFORM_RST,		PIN(8, 6), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-
-GPIO(EC_I2C1_USB_C0_SCL,	PIN(9, 0), GPIO_INPUT)				/* alt fn I2C1_SCL */
-GPIO(EC_I2C1_USB_C0_SDA,	PIN(8, 7), GPIO_INPUT)				/* alt fn I2C1_SDA */
-GPIO(EC_I2C2_USB_C1_SCL,	PIN(9, 2), GPIO_INPUT)				/* alt fn I2C2_SCL */
-GPIO(EC_I2C2_USB_C1_SDA,	PIN(9, 1), GPIO_INPUT)				/* alt fn I2C2_SDA */
-GPIO(EC_I2C5_GYRO_SCL,		PIN(3, 3), GPIO_INPUT)				/* alt fn I2C5_SCL */
-GPIO(EC_I2C5_GYRO_SDA,		PIN(3, 6), GPIO_INPUT)				/* alt fn I2C5_SDA */
-GPIO(EC_I2C3_SENSOR_3V3_SCL,	PIN(D, 1), GPIO_INPUT)				/* alt fn I2C3_SCL */
-GPIO(EC_I2C3_SENSOR_3V3_SDA,	PIN(D, 0), GPIO_INPUT)				/* alt fn I2C3_SDA */
-GPIO(EC_I2C0_POWER_SCL,		PIN(B, 5), GPIO_INPUT)				/* alt fn I2C0_SCL */
-GPIO(EC_I2C0_POWER_SDA,		PIN(B, 4), GPIO_INPUT)				/* alt fn I2C0_SDA */
-GPIO(EC_I2C4_BATTERY_SCL,	PIN(F, 3), GPIO_INPUT)				/* alt fn I2C4_SCL */
-GPIO(EC_I2C4_BATTERY_SDA,	PIN(F, 2), GPIO_INPUT)				/* alt fn I2C4_SDA */
-
-/* Not connected */
-GPIO(NC_GPIO32,			PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO35,			PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO40,			PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO44,			PIN(4, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO45,			PIN(4, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO50,			PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO57,			PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO63,			PIN(6, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO66,			PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO82,			PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO95,			PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOB1,			PIN(B, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOB2,			PIN(B, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOB3,			PIN(B, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOB6,			PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOC7,			PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOD6,			PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOD7,			PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOE0,			PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(ACCELGYRO3_INT_L,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* WoV is unused */
-GPIO(NC_GPIO94,			PIN(9, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIO97,			PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOA5,			PIN(A, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOA7,			PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0)		/* PSL3&GPI01, PSL2&GPI00 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 */
-
-/* gpio alternate functions */
-ALTERNATE(PIN_MASK(0, 0x18), 0, MODULE_GPIO, 0)		/* GPIO03,4 */
-
-ALTERNATE(PIN_MASK(8, 0x08), 0, MODULE_GPIO, 0)		/* GPIO83 */
-
-/* GPIOA3,1 are enabled by default even though they are ALT functions */
-
-/* PWM channels */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)		/* GPIO60 PWM7 CHARGE_LED5 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* GPIO80 PWM3 KBD_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)		/* GPIOB7 PWM5 CHARGE_LED6 */
-ALTERNATE(PIN_MASK(C, 0x1d), 0, MODULE_PWM, 0)		/* GPIOC4,3,2,0 PWM2,0,1,6 CHARGE_LED2,1,4,3 */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0_SCL0|I2C0_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)		/* I2C1_SCL0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x06), 0, MODULE_I2C, 0)		/* I2C2_SCL0|I2C2_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3_SCL0|I2C3_SDA0 */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)		/* I2C4_SCL1|I2C4_SDA1 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)		/* I2C5_SDA0|I2C5_SCL0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(4, 0x0c), 0, MODULE_ADC, 0)		/* ADC2-3 */
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-
-/* keyboard */
-#define GPIO_KB_INPUT		(GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT		(GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2	(GPIO_OUT_LOW)
-
-/* keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-GPIO(EC_KB_ROW02_INV, PIN(1, 7), GPIO_KB_OUTPUT_COL2)
diff --git a/board/atlas/led.c b/board/atlas/led.c
deleted file mode 100644
index 9cb4dabfd3..0000000000
--- a/board/atlas/led.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atlas specific PWM LED settings. */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  70,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  35,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  55,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  62, 100,  31 },
-	[EC_LED_COLOR_AMBER]  = { 100,  31,   0 },
-};
-
-/*
- * Two tri-color LEDs with red, green, and blue channels.
- *
- * Note: This order must match tcpc_config[]
- */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	[PWM_LED0] = {
-		/* left port LEDs */
-		.ch0 = PWM_CH_DB1_LED_RED,
-		.ch1 = PWM_CH_DB1_LED_GREEN,
-		.ch2 = PWM_CH_DB1_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-	[PWM_LED1] = {
-		/* right port LEDs */
-		.ch0 = PWM_CH_DB0_LED_RED,
-		.ch1 = PWM_CH_DB0_LED_GREEN,
-		.ch2 = PWM_CH_DB0_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_YELLOW] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_LEFT_LED)
-		pwm_id = PWM_LED0;
-	else if (led_id == EC_LED_ID_RIGHT_LED)
-		pwm_id = PWM_LED1;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/atlas/usb_pd_policy.c b/board/atlas/usb_pd_policy.c
deleted file mode 100644
index 77a4941a9a..0000000000
--- a/board/atlas/usb_pd_policy.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
-	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
-
-	/*
-	 * 1.5 vs 3.0 A limit is controlled by a dedicated gpio where
-	 * high = 3.0A and low = 1.5A. VBUS on/off is controlled by
-	 * GPIO_USB_C0/1_5V_EN.
-	 */
-	gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
-	gpio_set_level(gpio_5v_en, vbus_en[port]);
-}
-
-void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return tcpci_tcpm_check_vbus_level(port, VBUS_PRESENT);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L :
-			      GPIO_EN_USB_C0_CHARGE_L, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-}
diff --git a/board/atlas/vif_override.xml b/board/atlas/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/atlas/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/baklava/board.c b/board/baklava/board.c
deleted file mode 100644
index 35a27d0c21..0000000000
--- a/board/baklava/board.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Baklava board-specific configuration */
-
-#include "common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/stm32gx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/ps8822.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "usb_descriptor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "usb_pd_dp_ufp.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define QUICHE_PD_DEBUG_LVL 1
-
-#ifdef SECTION_IS_RW
-#define CROS_EC_SECTION "RW"
-#else
-#define CROS_EC_SECTION "RO"
-#endif
-
-#ifdef SECTION_IS_RW
-static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	PD_DRP_TOGGLE_ON,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_HOST_USBC_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_HOST);
-		break;
-	default:
-		break;
-	}
-}
-
-void hpd_interrupt(enum gpio_signal signal)
-{
-	usb_pd_hpd_edge_event(signal);
-}
-
-static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
-{
-	baseboard_usb3_check_state();
-}
-
-static void board_pwr_btn_interrupt(enum gpio_signal signal)
-{
-	baseboard_power_button_evt(gpio_get_level(signal));
-}
-
-static void board_usbc_usb3_interrupt(enum gpio_signal signal)
-{
-	baseboard_usbc_usb3_irq();
-}
-#endif /* SECTION_IS_RW */
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/*
- * Table GPIO signals control both power rails and reset lines to various chips
- * on the board. The order the signals are changed and the delay between GPIO
- * signals is driven by USB/MST hub power sequencing requirements.
- */
-const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
-};
-const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
-
-/*
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Acer"),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("D501"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-#ifndef SECTION_IS_RW
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-	},
-};
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * PS8802 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
-
-	return rv;
-}
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &stm32gx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
-	},
-};
-
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct hpd_to_pd_config_t hpd_config = {
-	.port = USB_PD_PORT_HOST,
-	.signal = GPIO_DDI_MST_IN_HPD,
-};
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_SYSTEM, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_enable_usbc_interrupts(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Enable HPD interrupt */
-	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Enable VBUS control interrupt for C1 */
-	gpio_enable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
-}
-
-void board_disable_usbc_interrupts(void)
-{
-	/* Disable PPC interrupts. */
-	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Disable HPD interrupt */
-	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Disable VBUS control interrupt for C1 */
-	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
-}
-
-void board_tcpc_init(void)
-{
-	board_reset_pd_mcu();
-
-	/* Enable board usbc interrupts */
-	board_enable_usbc_interrupts();
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
-{
-	return pd_dual_role_init[port];
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	/*
-	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0
-	 * and C1, but TCPMv2 only knows about C0, as C1 is a type-c only
-	 * port that is managed directly by the PS8803 TCPC.
-	 */
-	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USB_PD_PORT_HOST)
-		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	return 0;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/174825406): check correct operation for honeybuns */
-}
-
-int dock_get_mf_preference(void)
-{
-	return MF_ON;
-}
-#endif /* SECTION_IS_RW */
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_debug_gpio_1_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_1, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_1_pulse);
-
-static void board_debug_gpio_2_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_2, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_2_pulse);
-
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
-{
-	switch (trigger) {
-	case TRIGGER_1:
-		gpio_set_level(GPIO_TRIGGER_1, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_1_pulse_data,
-					   pulse_usec);
-		break;
-	case TRIGGER_2:
-		gpio_set_level(GPIO_TRIGGER_2, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_2_pulse_data,
-					   pulse_usec);
-		break;
-	default:
-		CPRINTS("bad debug gpio selection");
-		break;
-	}
-}
-
-static int command_dplane(int argc, char **argv)
-{
-	char *e;
-	int lane;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	lane = strtoi(argv[1], &e, 10);
-
-	if ((lane != 2) && (lane != 4))
-		return EC_ERROR_PARAM1;
-
-	/* put MST into reset */
-	gpio_set_level(GPIO_MST_RST_L, 0);
-	msleep(1);
-	/* Set lane control to requested level */
-	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
-	msleep(1);
-	/* Take MST out of reset */
-	gpio_set_level(GPIO_MST_RST_L, 1);
-
-	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
-		 lane == 2 ? "2 lane" : "4 lane",
-		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
diff --git a/board/baklava/board.h b/board/baklava/board.h
deleted file mode 100644
index e061d2342d..0000000000
--- a/board/baklava/board.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Baklava board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-/*
- * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
- * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
- * using option bytes WRP registers.
- */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
-
-/* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_USB3   1
-
-/*
- * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc
- * port, but this is type-c capable only. Only the PPC for this port needs to be
- * controlled by FW.
- */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_MUX_PS8822
-
-#undef CONFIG_USB_VID
-#define CONFIG_USB_VID 0x502
-#define CONFIG_USB_PID 0x1195
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-
-/* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
-
-/* Required symbolic I2C port names */
-#define I2C_PORT_MP4245 I2C_PORT_I2C3
-#define I2C_PORT_EEPROM I2C_PORT_I2C3
-#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "registers.h"
-
-#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
-#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
-#define GPIO_BPWR_DET GPIO_HUB_BPWRDET
-#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
-#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
-
-#define BUTTON_PRESSED_LEVEL 1
-#define BUTTON_RELEASED_LEVEL 0
-
-#define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN
-#define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN
-
-enum  debug_gpio {
-	TRIGGER_1 = 0,
-	TRIGGER_2,
-};
-
-/*
- * Function used to control GPIO signals as a timing marker. This is intended to
- * be used for development/debugging purposes.
- *
- * @param trigger GPIO debug signal selection
- * @param level desired level of the debug gpio signal
- * @param pulse_usec pulse width if non-zero
- */
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
-
-/*
- * Function called in power on case to enable usbc related interrupts
- */
-void board_enable_usbc_interrupts(void);
-
-/*
- * Function called in power off case to disable usbc related interrupts
- */
-void board_disable_usbc_interrupts(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/baklava/build.mk b/board/baklava/build.mk
deleted file mode 100644
index 7e3e1240fd..0000000000
--- a/board/baklava/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g473xc
-BASEBOARD:=honeybuns
-
-board-y=board.o
diff --git a/board/baklava/dev_key.pem b/board/baklava/dev_key.pem
deleted file mode 100644
index 4897ceb44e..0000000000
--- a/board/baklava/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
-2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
-bRZ8puvzu+XNqsSS/tvsdYbNE5WC5sXtt7Wkm3mKn7PAti7oQrKbW1beFD0FgdAq
-JoweIdpkuOwDYtFBcF92LWWGziDcEXlc2v5Xj3qvixMLnhy+Ny1Byr2ApVaYZ56H
-JfjHKxbirNj4IrgmhdzfBIKxDf4mGibG0K1aC1io+SixtRV1cS6JRB0D+GS4QIcq
-y9bCMkBeVQLHhSo1UYZqbB7Qef0blQ2sxsXklo8Q5EIQOd6yiXiTelApOWDn3zTi
-uTkUo+99SPDLw/S3sR3uESxt+OYO2Yt6BWe2JSYBhHWB0Xc0PGItq7DUpm2cEWke
-vS91I/lBfqhOxQOvnEx5NM97/RBQMa3jJ5Jv/72X5oU6OcGmaliBJy3Tv0CSiI06
-qgRgWxMym/XA0ui/AgEDAoIBgQCGw1N/K08rnpmup8t3OxZoddwH7TtO6cKm1CNC
-9Dmk9YEjIe6R63AwKhK4r++OJQNqfWsA5VQwgAqTs7w0ToWpOI/ok3MKr5yphAjh
-jVVyMvLyTvzzZFMZ8qJ9Q95x2GH/PUhOWd4NDldEg/PPzm28+7G/zSskH0WBzGeS
-Oeli01kBNXFvCBQWkZh7SAJB4NZK6k7I7lnewJK2UOiR/uUKUcpct10UEyl6Hivc
-flXDjxBFFFoZUITHZJcd5frB0Bh+EiqJ3CnkSIjD4sTnZs/TP8CKhmYriabfBHdH
-j6ffcr5y8VhqDJK/ISSmWQO1c/rSziJLhx/ZrWvWp1FAbRg+kdh+RmV8hYIdEOq8
-PYOiERihd+eHVhtzsc74+cRGxPbaFJ2rpuJt+xk1Zp7IfGyyPWDmvXFKZgX+vo2s
-vJL6q9pPR57uUHL0xsxDrMH3HFxkl1ta5PsiBGXs+zG0EUzNKGtoRTCi176xUWyo
-NG+eWiL9ddeZVBzWeKfJGfwQ53sCgcEA+JE2E5kjvVCasSqERfDfIkSeOKoqWdZ2
-sAvTHibq6+vMBkRubNA0glHcUrMEBblDg3ds2z1A9YvwjwEUq9UFpVH3qfX9vaTX
-lLYFRZjcA3PkCJvFAt5eIlVXp+vgaEo6OcodLjDiqkYKzbMC13k5uM1wsEEwo2vI
-38vhHQlH1PHVTd8pt2Y7mOpDgxOOJLrvwuew7Lj9QSBRZ0EJxqv+1QA4EQ1cPr1H
-hGqggtL0ChLRV7KBHiLz9ggS5vHTEkFNAoHBANAwaSIfTnpAvkMoGy+iQyw0afC0
-7hnwhHKcAzqenT1Mzo3Yt7/zsZE8ywjKPe9C+ZHZyh+W373tCUQRnjpNOpNiVHzi
-ekFxl8kpLhpbB8LTXuRlQmtZjVQPbyuORPGDCzA05GGBN6mnXju+iQEz2WD8f3oY
-Jz5yYl54eAuMsFl5/0yehqBQjRvky5YRna2eNUKBvz+/BgjpZeb0DtLMffcAvrkQ
-FQbAwNvzvagMOEemjLSp9iXjQSNWJAdc86dMOwKBwQCltiQNEMJ+Nbx2HFguoJTB
-gxQlxsbmjvnKsoy+xJydR91ZgvRIis2sNpLhzK1ZJi0CT53nfitOXUsKALhyjgPD
-i/pxTqkpGI+4eVjZEJKs9+1bEoNXPulsOOUanUBFhtF73BN0IJccLrHed1c6UNEl
-3ksgK3XCR9s/3UC+Bi/jS+OJP3Ek7tJl8YJXYl7DJ0qB78tIe1OAwDZE1gaEcqnj
-VXq2COgp04UC8cBXN01cDIuPzFYUF01OsAyZ9oy21jMCgcEAisrwwWo0UYB+13AS
-H8GCHXhGoHieu/Wtob1XfGm+KN3fCTslKqJ2YNMyBdwpSiymYTvcFQ8/0/NbgrZp
-fDN8YkGNqJb8K6EP23DJZudageI/Qu4sR5EI4rT0x7Qt9ldcys3tllYlG8TpfSmw
-q3fmQKhU/BAaKaGW6aWlXQh1kPv/iGmvFYsIvUMyZAu+c77OLFZ/f9SusJuZRKK0
-jIhT+gB/Jgq4rysrPU0pGrLQL8RdzcakGUIrbOQYBOiib4gnAoHAVrvbmZGxyeeA
-oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
-FVCUiFxhOz05hpnB1ts70tuIWUJbWttMnhZPTpKa1dzZFB6qrlk2o/ONaSfNzpOZ
-FgKxBURFVzNMTlIh7QOZGoOeRg5BkFG5z21g8egYQ/1cY61BhaxJTz93HGKb0jYn
-QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
------END RSA PRIVATE KEY-----
diff --git a/board/baklava/ec.tasklist b/board/baklava/ec.tasklist
deleted file mode 100644
index 14c2c31393..0000000000
--- a/board/baklava/ec.tasklist
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/baklava/gpio.inc b/board/baklava/gpio.inc
deleted file mode 100644
index 144a5e3f8c..0000000000
--- a/board/baklava/gpio.inc
+++ /dev/null
@@ -1,93 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#ifdef SECTION_IS_RW
-GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
-GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
-GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
-GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
-GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
-#endif
-
-/* Power sequencing signals */
-GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
-GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
-GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
-GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
-GPIO(EN_PP1100_A,                   PIN(C,  7), GPIO_OUT_LOW)
-GPIO(EN_PP1050_A,                   PIN(A,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_C,                   PIN(D,  1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
-
-/* MST Hub signals */
-GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
-GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
-GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
-GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
-
-/* Display Demux signals */
-GPIO(DEMUX_DP_HDMI_MODE,            PIN(E, 15), GPIO_OUT_LOW)
-GPIO(DEMUX_DP_HDMI_PD_N,            PIN(B, 13), GPIO_ODR_LOW)
-
-/* USBC Mux and Demux Signals */
-GPIO(EN_DP_SINK,                    PIN(B, 14), GPIO_OUT_LOW)
-GPIO(DP_SINK_RESET,                 PIN(B, 15), GPIO_OUT_LOW)
-GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
-
-/* USB Hubs signals */
-GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
-GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
-GPIO(USBC_DATA_OCP_NOTIFY,          PIN(C,  2), GPIO_OUT_HIGH)
-GPIO(HUB_BPWRDET,                   PIN(C,  1), GPIO_OUT_LOW)
-
-/* USB-A Current limit switches, set default to 1.5A */
-GPIO(GBE_RESET_EC,                  PIN(C,  0), GPIO_OUT_LOW)
-GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
-GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
-GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
-
-
-/* Write protect */
-GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
-GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
-
-/* UART Bus */
-GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
-GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
-
-/*
- * I2C SCL/SDA pins. These will normally be under control of the peripheral from
- * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
- * these signals as regular GPIOs.
- */
-GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
-GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
-
-/* misc signals */
-GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART3_TX/RX GPIOC 10-11*/
-ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
-/* I2C Ports
- *   I2C1: SDA/SCL -> PB7/PA15
- *   I2C2: SDA/SCL -> PA8/PA9
- *   I2C3: SDA/SCL -> PC8/PC9
- */
-ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
-/* GPIOA4-7: SPI Signals */
-ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)
diff --git a/board/bds/board.c b/board/bds/board.c
deleted file mode 100644
index 91da893a52..0000000000
--- a/board/bds/board.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Stellaris EKB-LM4F-EAC board-specific configuration */
-
-#include "adc.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "registers.h"
-#include "util.h"
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* EC internal temperature is calculated by
-	 * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
-	 * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
-	 */
-	{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
-	 LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
-
-	/* Charger current is mapped from 0~4000mA to 0~1.6V.
-	 * And ADC maps 0~3.3V to ADC_READ_MAX.
-	 *
-	 * Note that on BDS, this is really just the turn pot on the Badger
-	 * board, but that's good enough for debugging the ADC.
-	 */
-	{"BDSPot", LM4_ADC_SEQ1, 33 * 4000, ADC_READ_MAX * 16, 0,
-	 LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"lightbar", 5, 400},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#include "gpio_list.h"
diff --git a/board/bds/board.h b/board/bds/board.h
deleted file mode 100644
index c859089f04..0000000000
--- a/board/bds/board.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Stellaris EKB-LM4F-EAC board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED  /* Allow dangerous commands */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* LM4 modules we don't use on link but still want to keep compiling */
-#define CONFIG_EEPROM
-#define CONFIG_PSTORE
-
-/* Modules we want to exclude */
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_HOSTCMD_LPC
-#undef CONFIG_PECI
-#undef CONFIG_SWITCH
-
-/* Write protect is active high */
-#define CONFIG_WP_ACTIVE_HIGH
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_EC_TEMP = 0,  /* EC internal die temperature in degrees K. */
-	ADC_CH_BDS_POT,      /* BDS pot input. */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_COUNT
-};
-
-/* I2C ports */
-#define I2C_PORT_LIGHTBAR 5  /* Port 5 / PA6:7 on link, but PG6:7 on badger */
-
-/* Second UART port */
-#define CONFIG_UART_HOST 1
-
-#include "gpio_signal.h"
-
-/* EEPROM blocks */
-#define EEPROM_BLOCK_START_PSTORE 16  /* Host persistent storage */
-#define EEPROM_BLOCK_COUNT_PSTORE 16
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bds/build.mk b/board/bds/build.mk
deleted file mode 100644
index e3e91f0bb2..0000000000
--- a/board/bds/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is TI Stellaris LM4
-CHIP:=lm4
-
-board-y=board.o
diff --git a/board/bds/ec.tasklist b/board/bds/ec.tasklist
deleted file mode 100644
index 7329da7d2d..0000000000
--- a/board/bds/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/bds/gpio.inc b/board/bds/gpio.inc
deleted file mode 100644
index 374894f932..0000000000
--- a/board/bds/gpio.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Recovery signal from DOWN button */
-GPIO(RECOVERY_L, PIN(D, 1), GPIO_PULL_UP)
-GPIO(DEBUG_LED,  PIN(A, 7), GPIO_OUT_LOW)
-
-/*
- * Signals which aren't implemented on BDS but we'll emulate anyway, to
- * make it more convenient to debug other code.
- */
-UNIMPLEMENTED(WP)          /* Write protect input */
-UNIMPLEMENTED(ENTERING_RW) /* EC entering RW code */
-
-ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART,     0) /* UART0 */
-ALTERNATE(PIN_MASK(G, 0x40), 3, MODULE_I2C,      0) /* I2C5 SCL */
-ALTERNATE(PIN_MASK(G, 0x80), 3, GPIO_OPEN_DRAIN, 0) /* I2C5 SDA */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART,     0) /* UART1 */
diff --git a/board/beetley/battery.c b/board/beetley/battery.c
deleted file mode 100644
index 94f5dbb630..0000000000
--- a/board/beetley/battery.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all beetley battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L20M3PG0 Battery Information */
-	[BATTERY_SMP1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP L20M3PG3 Battery Information */
-	[BATTERY_SMP2] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG3",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC L20L3PG0 Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Sunwoda L20D3PG0 Battery Information */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 205,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Celxert L20C3PG0 Battery Information */
-	[BATTERY_CELXPERT] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L20C3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP1;
diff --git a/board/beetley/board.c b/board/beetley/board.c
deleted file mode 100644
index 08c9ba5066..0000000000
--- a/board/beetley/board.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Beetley board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cros_board_info.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define INT_RECHECK_US 5000
-
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 80,
-	.debounce_down_us = 30 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
-}
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-};
-
-static const struct ec_response_keybd_config beetley_keybd = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &beetley_keybd;
-}
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS
-};
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t base_lsm6dsm_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,		/* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DS3,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_lsm6dsm_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DS3,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_lsm6dsm_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-
-	/* Set LEDs luminance */
-	pwm_set_duty(PWM_CH_LED_RED, 70);
-	pwm_set_duty(PWM_CH_LED_GREEN, 70);
-	pwm_set_duty(PWM_CH_LED_WHITE, 70);
-
-	/*Enable Base Accel interrupt*/
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-
-	/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
-	keyscan_config.actual_key_mask[11] = 0xfe;
-	keyscan_config.actual_key_mask[12] = 0xff;
-	keyscan_config.actual_key_mask[13] = 0xff;
-	keyscan_config.actual_key_mask[14] = 0xff;
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Charger IC need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 *
-	 * b:186717219: In order to solve the power consumption problem of
-	 * hibernate，HW solution is adopted after board id 3 to solve the
-	 * problem that AC cannot wake up hibernate mode.
-	 */
-	raa489000_hibernate(0, true);
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	if (port != 0 && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	CPRINTUSB("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
-		raa489000_enable_asgate(0, false);
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTUSB("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTUSB("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_WHITE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charge",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "5V_Inductor",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/beetley/board.h b/board/beetley/board.h
deleted file mode 100644
index bac25d4d67..0000000000
--- a/board/beetley/board.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Beetley board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSYCMD_BATTERY_V2
-
-/* Sysetem unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* DAC for PSYS */
-#define CONFIG_DAC
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/*SENSOR*/
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* PWM */
-#define CONFIG_PWM
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux */
-#define CONFIG_USB_MUX_IT5205
-
-/* KeyBoard */
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_WHITE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A, /* ADC0 */
-	ADC_TEMP_SENSOR_1, /* ADC2 */
-	ADC_TEMP_SENSOR_2, /* ADC3 */
-	ADC_TEMP_SENSOR_3, /* ADC15 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP1,
-	BATTERY_SMP2,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_CELXPERT,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/beetley/build.mk b/board/beetley/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/beetley/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/beetley/cbi_ssfc.c b/board/beetley/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/beetley/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/beetley/cbi_ssfc.h b/board/beetley/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/beetley/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/beetley/ec.tasklist b/board/beetley/ec.tasklist
deleted file mode 100644
index bdcbcdf074..0000000000
--- a/board/beetley/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/beetley/gpio.inc b/board/beetley/gpio.inc
deleted file mode 100644
index bbb793ee44..0000000000
--- a/board/beetley/gpio.inc
+++ /dev/null
@@ -1,152 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Used by baseboard z-state enable, but not present on beetley */
-UNIMPLEMENTED(USB_C1_INT_ODL)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/*TP*/
-GPIO(TP, PIN(C, 3), GPIO_INPUT | GPIO_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		    	/* ADC15: TEMP_SENSOR_3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* DAC */
-ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* RED led, GREEN led, WHITE led */
diff --git a/board/beetley/led.c b/board/beetley/led.c
deleted file mode 100644
index bf64b33dcf..0000000000
--- a/board/beetley/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Beetley specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
-	else
-		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/beetley/usb_pd_policy.c b/board/beetley/usb_pd_policy.c
deleted file mode 100644
index b7c0ca21df..0000000000
--- a/board/beetley/usb_pd_policy.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	if (port != 0)
-		return;
-
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port != 0)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
diff --git a/board/beetley/vif_override.xml b/board/beetley/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/beetley/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/berknip/analyzestack.yaml b/board/berknip/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/berknip/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/berknip/battery.c b/board/berknip/battery.c
deleted file mode 100644
index 526375c0db..0000000000
--- a/board/berknip/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Berknip battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 996QA193H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-/* Cosmx CA407792G Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/berknip/board.c b/board/berknip/board.c
deleted file mode 100644
index a119007de6..0000000000
--- a/board/berknip/board.c
+++ /dev/null
@@ -1,671 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Berknip board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charger.h"
-#include "cbi_ec_fw_config.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_115_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS5,
-};
-
-static int check_hdmi_hpd_status(void)
-{
-	return gpio_get_level(GPIO_DP1_HPD_EC_IN);
-}
-
-/*****************************************************************************
- * Board suspend / resume
- */
-
-static void board_chipset_resume(void)
-{
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 1);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
-		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  check_hdmi_hpd_status());
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
-	}
-
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * USB C0 port SBU mux use standalone PI3USB221
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			     bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	return EC_SUCCESS;
-}
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = pi3usb221_set_mux,
-};
-/*
- * Since PI3USB221 is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration
- */
-static void setup_mux(void)
-{
-	if (ec_config_has_usbc1_retimer_tusb544()) {
-		ccprints("C1 TUSB544 detected");
-		/*
-		 * Main MUX is FP5, secondary MUX is TUSB544
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
-	} else if (ec_config_has_usbc1_retimer_ps8743()) {
-		ccprints("C1 PS8743 detected");
-		/*
-		 * Main MUX is PS8743, secondary MUX is modified FP5
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
-		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-		/* Don't have the AMD FP5 flip */
-		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
-	}
-}
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		/* Filled in dynamically at startup */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_1,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_1,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_2,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_2,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
-		if (rv)
-			return rv;
-	}
-
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_1,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_61_UFP_43);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_1,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_61_UFP_43);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_2,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_61_UFP_43);
-		if (rv)
-			return rv;
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_2,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_61_UFP_43);
-		if (rv)
-			return rv;
-
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	} else {
-		/* Disable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
-	}
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usbc1_tusb544 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS1,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_mux_set,
-};
-const struct usb_mux usbc1_ps8743 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-	.driver = &ps8743_usb_mux_driver,
-};
-
-/*****************************************************************************
- * Use FW_CONFIG to set correct configuration.
- */
-enum gpio_signal GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V0;
-static uint32_t board_ver;
-int board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB_V1;
-
-static void board_version_check(void)
-{
-	cbi_get_board_version(&board_ver);
-
-	if (board_ver <= 2)
-		chg_chips[0].i2c_port = I2C_PORT_CHARGER_V0;
-
-	if (board_ver == 2) {
-		power_signal_list[X86_S0_PGOOD].gpio = GPIO_S0_PWROK_OD_V1;
-		GPIO_S0_PGOOD = GPIO_S0_PWROK_OD_V1;
-	}
-}
-/*
- * Use HOOK_PRIO_INIT_I2C so we re-map before charger_chips_init()
- * talks to the charger.
- */
-DECLARE_HOOK(HOOK_INIT, board_version_check, HOOK_PRIO_INIT_I2C);
-
-static void board_remap_gpio(void)
-{
-	if (board_ver >= 3) {
-		/*
-		 * TODO: remove code when older version_2
-		 * hardware is retired and no longer needed
-		 */
-		gpio_set_flags(GPIO_USB_C1_HPD_IN_DB_V1, GPIO_OUT_LOW);
-		board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB_V1;
-
-		if (ec_config_has_hdmi_retimer_pi3hdx1204())
-			gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
-
-	} else
-		board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-}
-
-static void setup_fw_config(void)
-{
-	setup_mux();
-
-	board_remap_gpio();
-}
-/* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-static void hdmi_hpd_handler(void)
-{
-	/* Pass HPD through DB OPT1 HDMI connector to AP's DP1 */
-	int hpd = check_hdmi_hpd_status();
-
-	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
-	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	/* Debounce for 2 msec */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-/*****************************************************************************
- * Fan
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3000,
-	.rpm_start = 3500,
-	.rpm_max = 6200,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-	case TEMP_SENSOR_SOC:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		/* adc power not ready when transition to S5 */
-		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_SOC;
-		break;
-	case TEMP_SENSOR_5V_REGULATOR:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		/* adc power not ready when transition to S5 */
-		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_5V_REGULATOR;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_SOC,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-	[TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_5V_REGULATOR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_thermistor_soc = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(62),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(66),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(57),
-	},
-	.temp_fan_off = C_TO_K(39),
-	.temp_fan_max = C_TO_K(60),
-};
-
-const static struct ec_thermal_config thermal_thermistor_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(99),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(99),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(98),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
-
-const static struct ec_thermal_config thermal_thermistor_5v = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(99),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(99),
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 29, .off =  5, .rpm = 3700},
-	{.on = 38, .off = 19, .rpm = 4000},
-	{.on = 48, .off = 33, .rpm = 4500},
-	{.on = 62, .off = 43, .rpm = 4800},
-	{.on = 76, .off = 52, .rpm = 5200},
-	{.on = 100, .off = 67, .rpm = 6200},
-};
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-
-static const struct fan_step *fan_table = fan_table0;
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
-}
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_CHARGER] = thermal_thermistor_charger;
-	thermal_params[TEMP_SENSOR_SOC] = thermal_thermistor_soc;
-	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
-	thermal_params[TEMP_SENSOR_5V_REGULATOR] = thermal_thermistor_5v;
-}
-DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-/*****************************************************************************
- * Power signals
- */
-
-struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PWROK_OD_V0,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
-{
-	/* USB-C0 always uses USB_C0_HPD (= DP3_HPD). */
-	if (port == 0)
-		return GPIO_USB_C0_HPD;
-
-	/*
-	 * USB-C1 OPT3 DB
-	 *    version_2 uses GPIO_NO_HPD
-	 *    version_3 uses USB_C1_HPD_IN_DB_V1 via RTD2141B MST hub
-	 *    to drive AP HPD, EC drives MST hub HPD input
-	 *    from USB-PD messages..
-	 */
-	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 3)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: GPIO_NO_HPD;
-
-	/* USB-C1 OPT1 DB uses DP2_HPD. */
-	return GPIO_DP2_HPD;
-}
diff --git a/board/berknip/board.h b/board/berknip/board.h
deleted file mode 100644
index 5ef9e33f0c..0000000000
--- a/board/berknip/board.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Berknip board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_TREMBYLE
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define RPM_DEVIATION 1
-#define CONFIG_FAN_RPM_CUSTOM
-
-#undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Type C mux/retimer */
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USBC_RETIMER_TUSB544
-#define TUSB544_I2C_ADDR_FLAGS1 0x0F
-#define CONFIG_TUSB544_EQ_BY_REGISTER
-
-#define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This GPIOs moved. Temporarily detect and support the V0 HW. */
-extern enum gpio_signal GPIO_S0_PGOOD;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_5V_REGULATOR,
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_5V_REGULATOR,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * BERKNIP_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	BERKNIP_MB_USBAC = 0,
-};
-
-/**
- * BERKNIP_DB_T_OPT1_USBAC_HMDI
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: PS8719
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: TUSB544
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- *
- *
- * BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: PS8719
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8743
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: none
- *		MST Hub: RTD2141B
- */
-enum ec_cfg_usb_db_type {
-	BERKNIP_DB_T_OPT1_USBAC_HMDI = 0,
-	BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB = 1,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_usbc1_retimer_ps8743(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
-}
-
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_usbc1_retimer_tusb544(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_mst_hub_rtd2141b(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
-}
-
-#define HAS_HDMI_CONN_HPD \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_hdmi_conn_hpd(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
-}
-
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
-#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio(port)
-
-extern const struct usb_mux usbc1_tusb544;
-extern const struct usb_mux usbc1_ps8743;
-extern struct usb_mux usbc1_amd_fp5_usb_mux;
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/berknip/build.mk b/board/berknip/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/berknip/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/berknip/ec.tasklist b/board/berknip/ec.tasklist
deleted file mode 100644
index 3a08ebc972..0000000000
--- a/board/berknip/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/berknip/gpio.inc b/board/berknip/gpio.inc
deleted file mode 100644
index 860cbba284..0000000000
--- a/board/berknip/gpio.inc
+++ /dev/null
@@ -1,156 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD_V0,	PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-
-/*
- * TODO(dbrockus@): remove code when older version_2 of hardware is
- * retired and no longer needed
- */
-#if 0
-GPIO(USB_C1_HPD_IN_DB_V1,	PIN(B, 1), GPIO_OUT_LOW)			/* C1 HPD V1 */
-#else
-#define GPIO_USB_C1_HPD_IN_DB_V1	GPIO_S0_PWROK_OD_V1
-GPIO_INT(S0_PWROK_OD_V1,	PIN(B, 1), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
-GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(NO_HPD)
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-GPIO(C1_CHARGE_LED_WHITE_DB_L,	PIN(7, 0), GPIO_OUT_HIGH)
-GPIO(C1_CHARGE_LED_AMBER_DB_L,	PIN(6, 7), GPIO_OUT_HIGH)
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, 	sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-
-IOEX(USB_A0_RETIMER_EN,		EXPIN(USBC_PORT_C0, 0, 0), GPIO_OUT_LOW)	/* A0 Retimer Enable */
-IOEX(USB_A0_RETIMER_RST,	EXPIN(USBC_PORT_C0, 0, 1), GPIO_OUT_LOW)	/* A0 Retimer Reset */
-IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_A1_RETIMER_RST_DB,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)	/* A1 Retimer Reset */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(HDMI_POWER_EN_DB,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)	/* HDMI retimer power enable */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_LOW)	/* HDMI Retimer Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,		EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)		/* ADC0, ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(C, BIT(3)), 0, MODULE_PWM, 0)				/* PWM0 LED */
-ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/berknip/led.c b/board/berknip/led.c
deleted file mode 100644
index 79d691ffac..0000000000
--- a/board/berknip/led.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_TICKS_PER_CYCLE_S3 35
-#define LED_ON_TICKS 5
-#define POWER_LED_ON_S3_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_LED_CHRG_L :
-				 GPIO_C1_CHARGE_LED_AMBER_DB_L);
-	white_led = (port == RIGHT_PORT ? GPIO_LED_FULL_L :
-				 GPIO_C1_CHARGE_LED_WHITE_DB_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Berknip, Berknip is non-power LED
-	 * design, blinking both two side battery white LEDs to indicate
-	 * system suspend with non-charging state.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
-		power_ticks++;
-
-		led_set_color_battery(RIGHT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		return;
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/berknip/vif_override.xml b/board/berknip/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/berknip/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/bland b/board/bland
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/bland
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/blipper/battery.c b/board/blipper/battery.c
deleted file mode 100644
index 114cfbc313..0000000000
--- a/board/blipper/battery.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all blipper battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L20M3PG0 Battery Information */
-	[BATTERY_SMP1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP L20M3PG3 Battery Information */
-	[BATTERY_SMP2] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG3",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC L20L3PG0 Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Sunwoda L20D3PG0 Battery Information */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 205,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Celxert L20C3PG0 Battery Information */
-	[BATTERY_CELXPERT] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L20C3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0008,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP1;
diff --git a/board/blipper/board.c b/board/blipper/board.c
deleted file mode 100644
index 2ca56a1b51..0000000000
--- a/board/blipper/board.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Blipper board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cros_board_info.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define INT_RECHECK_US 5000
-
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 80,
-	.debounce_down_us = 30 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
-}
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-};
-
-static const struct ec_response_keybd_config blipper_keybd = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-		return &blipper_keybd;
-}
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS
-};
-
-static uint32_t board_id;
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_lis2dwl_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_lis2dwl_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DS3,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = NULL,		/* identity matrix */
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DS3,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,               /* identity matrix */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-
-	/* Set LEDs luminance */
-	pwm_set_duty(PWM_CH_LED_RED, 70);
-	pwm_set_duty(PWM_CH_LED_GREEN, 70);
-	pwm_set_duty(PWM_CH_LED_WHITE, 70);
-
-	/* Enable Base Accel interrupt for Beetley */
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT)
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-
-	/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
-	keyscan_config.actual_key_mask[11] = 0xfe;
-	keyscan_config.actual_key_mask[12] = 0xff;
-	keyscan_config.actual_key_mask[13] = 0xff;
-	keyscan_config.actual_key_mask[14] = 0xff;
-
-	cbi_get_board_version(&board_id);
-
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/*
-		 * Base accel is not stuffed, don't allow
-		 * line to float.
-		 */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-				GPIO_INPUT | GPIO_PULL_DOWN);
-
-		gpio_set_flags(GPIO_VOLDN_BTN_ODL,
-				GPIO_INPUT | GPIO_PULL_DOWN);
-
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL,
-				GPIO_INPUT | GPIO_PULL_DOWN);
-
-	}
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Charger IC need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 *
-	 * b:186717219: In order to solve the power consumption problem of
-	 * hibernate，HW solution is adopted after board id 3 to solve the
-	 * problem that AC cannot wake up hibernate mode.
-	 */
-	if (board_id > 2)
-		raa489000_hibernate(0, true);
-	else
-		raa489000_hibernate(0, false);
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	if (port != 0 && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	CPRINTUSB("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
-		raa489000_enable_asgate(0, false);
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTUSB("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTUSB("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_WHITE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charge",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "5V_Inductor",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/blipper/board.h b/board/blipper/board.h
deleted file mode 100644
index fdee05e800..0000000000
--- a/board/blipper/board.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Blipper board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* DAC for PSYS */
-#define CONFIG_DAC
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/*SENSOR*/
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* PWM */
-#define CONFIG_PWM
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux */
-#define CONFIG_USB_MUX_IT5205
-
-/* KeyBoard */
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_WHITE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP1,
-	BATTERY_SMP2,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_CELXPERT,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/blipper/build.mk b/board/blipper/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/blipper/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/blipper/cbi_ssfc.c b/board/blipper/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/blipper/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/blipper/cbi_ssfc.h b/board/blipper/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/blipper/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/blipper/ec.tasklist b/board/blipper/ec.tasklist
deleted file mode 100644
index bdcbcdf074..0000000000
--- a/board/blipper/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/blipper/gpio.inc b/board/blipper/gpio.inc
deleted file mode 100644
index f072f1c832..0000000000
--- a/board/blipper/gpio.inc
+++ /dev/null
@@ -1,151 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Used by baseboard z-state enable, but not present on blipper */
-UNIMPLEMENTED(USB_C1_INT_ODL)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/*TP*/
-GPIO(TP, PIN(C, 3), GPIO_INPUT | GPIO_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		    	/* ADC15: TEMP_SENSOR_3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* DAC */
-ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* RED led, GREEN led, WHITE led */
diff --git a/board/blipper/led.c b/board/blipper/led.c
deleted file mode 100644
index 7ba065fa5e..0000000000
--- a/board/blipper/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Blipper specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
-	else
-		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/blipper/usb_pd_policy.c b/board/blipper/usb_pd_policy.c
deleted file mode 100644
index b7c0ca21df..0000000000
--- a/board/blipper/usb_pd_policy.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	if (port != 0)
-		return;
-
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port != 0)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
diff --git a/board/blipper/vif_override.xml b/board/blipper/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/blipper/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/bloog/battery.c b/board/bloog/battery.c
deleted file mode 100644
index f67b21d3b5..0000000000
--- a/board/bloog/battery.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all bloog battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack Coslight BDAK126150-W0P0703HT attery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL DynaPack DAK126150-W0G0703HT Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack SDI DAK126150-W020703HT Battery Information */
-	[BATTERY_DYNAPACK_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-24-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI P21GGH-03-N02 Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo Coslight 996QA149H Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo ATL 996QA150H Battery Information */
-	[BATTERY_SIMPLO_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-17-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER 996QA168H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* LGC MPPHPPMD021C Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "333-42-33-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Coslight B00C368598D0001 Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-33-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS_2] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/bloog/board.c b/board/bloog/board.c
deleted file mode 100644
index dfad4ab281..0000000000
--- a/board/bloog/board.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Bloog/Blooguard board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_a_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_b_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_a_cover_ref,
-		.default_range = 2, /* g */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*
- * Returns 1 for boards that are convertible into tablet mode, and zero for
- * clamshells.
- */
-int board_is_convertible(void)
-{
-	/*
-	 * Bloog: 33, 34, 35, 36
-	 * Blooguard: 49, 50, 51, 52
-	 * Bipship: 53, 54, 55, 56
-	 * Unprovisioned: 255
-	 */
-	return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36
-		|| sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52
-		|| sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56
-		|| sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-		/* Override sensor marix for Bipship. */
-		if (sku_id == 53 || sku_id == 54 || sku_id == 55
-			|| sku_id == 56)
-			motion_sensors[LID_ACCEL].rot_standard_ref =
-				&lid_b_cover_ref;
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate_late(void)
-{
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (sku_id == 33 || sku_id == 36 || sku_id == 51 ||
-		sku_id == 52 || sku_id == 53 || sku_id == 55 ||
-		sku_id == 66 || sku_id == 68)
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
diff --git a/board/bloog/board.h b/board/bloog/board.h
deleted file mode 100644
index 466c38aede..0000000000
--- a/board/bloog/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Bloog/Blooguard board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_SDI,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_ATL,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_LGC,
-	BATTERY_COS,
-	BATTERY_COS_2,
-	BATTERY_TYPE_COUNT,
-};
-
-int board_is_convertible(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bloog/build.mk b/board/bloog/build.mk
deleted file mode 100644
index 137e208b53..0000000000
--- a/board/bloog/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/bloog/ec.tasklist b/board/bloog/ec.tasklist
deleted file mode 100644
index 6eac78a042..0000000000
--- a/board/bloog/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/bloog/gpio.inc b/board/bloog/gpio.inc
deleted file mode 100644
index 3ee2f88eb1..0000000000
--- a/board/bloog/gpio.inc
+++ /dev/null
@@ -1,197 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,  PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)	/* EN_PP3300_TRACKPAD_ODL */
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(LED_AMBER_C0_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(LED_WHITE_C0_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(LED_AMBER_C1_L,	 PIN(0, 3), GPIO_OUT_HIGH)	/* LED_4_L */
-GPIO(LED_WHITE_C1_L,	 PIN(9, 7), GPIO_OUT_HIGH)	/* LED_5_L */
-GPIO(PWR_LED_WHITE_L,	 PIN(D, 7), GPIO_OUT_HIGH)	/* LED_3_L */
-
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	 PIN(6, 2), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,       PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP) /* GPO66_ARM_L_X86 */
-GPIO(GPOB6_NC,       PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP) /* EC_GP_SEL_ODL */
-
-/* Misc */
-GPIO(CCD_MODE_EC_L,   	   PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT)
-
-/* Unused pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)					/* EC_KSO_02_INV */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/bloog/led.c b/board/bloog/led.c
deleted file mode 100644
index ba1a865890..0000000000
--- a/board/bloog/led.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Bloog/Blooguard
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_ON_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_LED_AMBER_C1_L : GPIO_LED_AMBER_C0_L,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_LED_WHITE_C1_L : GPIO_LED_WHITE_C0_L,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(0, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(0, LED_AMBER);
-		else
-			led_set_color_battery(0, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(1, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(1, LED_AMBER);
-		else
-			led_set_color_battery(1, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(1, (port == 1) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Blooglet, Blooglet is non-power LED
-	 * design, blinking both two side battery white LEDs to indicate
-	 * system suspend with non-charging state.
-	 */
-	if (!board_is_convertible()) {
-		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
-			power_ticks++;
-
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(1, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(1, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(0, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/bloog/vif_override.xml b/board/bloog/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/bloog/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/bloonchipper b/board/bloonchipper
deleted file mode 120000
index cf1a7f228d..0000000000
--- a/board/bloonchipper
+++ /dev/null
@@ -1 +0,0 @@
-./hatch_fp
\ No newline at end of file
diff --git a/board/bobba/battery.c b/board/bobba/battery.c
deleted file mode 100644
index e53e839a68..0000000000
--- a/board/bobba/battery.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all bobba battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo AP13J7K Battery Information */
-	[BATTERY_SMP_AP13J7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "AP13J7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AC15A3J Battery Information */
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP19A8K Battery Information */
-	[BATTERY_LGC_AP19A8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KTxxxxGxxx",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC KT0030G023 Battery Information */
-	[BATTERY_LGC_G023] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G023",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-
-	/* Panasonic AP19A5K Battery Information */
-	[BATTERY_PANASONIC_AP19A5K] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305012",
-			.device_name = "AP19A5K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC15A3J;
diff --git a/board/bobba/board.c b/board/bobba/board.c
deleted file mode 100644
index 1ab1dad660..0000000000
--- a/board/bobba/board.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Bobba board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* Check PPC ID Pin and Board ver to decide which one ppc is used. */
-static bool support_syv_ppc(void)
-{
-	uint32_t board_version = 0;
-
-	if (cbi_get_board_version(&board_version) != EC_SUCCESS)
-		CPRINTSUSB("Get board version failed.");
-
-	if ((board_version == 5) && (gpio_get_level(GPIO_PPC_ID)))
-		return true;
-
-	return false;
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		if (support_syv_ppc())
-			syv682x_interrupt(0);
-		else
-			nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		if (support_syv_ppc())
-			syv682x_interrupt(1);
-		else
-			nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/*
- * Sparky360 SKU ID 26 has AR Cam, and move base accel/gryo to AR Cam board.
- * AR Cam board has about 16° bias with motherboard through Y axis.
- * Rotation matrix with 16° through Y axis:
- *     | cos(16°)      0       sin(16°)|   | 0.96126   0   0.27564|
- * R = |    0          1          0    | = |     0     1      0   |
- *     |-sin(16°)      0       cos(16°)|   |-0.27564   0   0.96126|
- *
- *                                           |0  -0.96126   0.27564|
- * base_ar_cam_ref = R * base_standard_ref = |1       0        0   |
- *                                           |0   0.27564   0.96126|
- */
-const mat33_fp_t base_ar_cam_ref = {
-	{ 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564)},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[VSYNC] = {
-	.name = "Camera VSYNC",
-	.active_mask = SENSOR_ACTIVE_S0,
-	.chip = MOTIONSENSE_CHIP_GPIO,
-	.type = MOTIONSENSE_TYPE_SYNC,
-	.location = MOTIONSENSE_LOC_CAMERA,
-	.drv = &sync_drv,
-	.default_range = 0,
-	.min_frequency = 0,
-	.max_frequency = 1,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm426xx_base_accel = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_icm_ref,
-	 .default_range = 4,  /* g */
-	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_icm_ref,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int board_is_convertible(void)
-{
-	/*
-	 * SKU ID of Bobba360, Sparky360, & unprovisioned: 9, 10, 11, 12,
-	 * 25, 26, 27, 255
-	 */
-	return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12
-		|| sku_id == 25 || sku_id == 26 || sku_id == 27
-		|| sku_id == 255;
-}
-
-static int board_with_ar_cam(void)
-{
-	/* SKU ID of Sparky360 with AR Cam: 26 */
-	return sku_id == 26;
-}
-static int base_gyro_config;
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		base_gyro_config = get_cbi_ssfc_sensor();
-		if (base_gyro_config == SSFC_SENSOR_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE GYRO is ICM426XX");
-		} else
-			ccprints("BASE GYRO is BMI160");
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/* Sparky360 with AR Cam: base accel/gyro sensor is on AR Cam board. */
-	if (board_with_ar_cam()) {
-		/* Enable interrupt from camera */
-		gpio_enable_interrupt(GPIO_WFCAM_VSYNC);
-
-		motion_sensors[BASE_ACCEL].rot_standard_ref = &base_ar_cam_ref;
-		motion_sensors[BASE_GYRO].rot_standard_ref = &base_ar_cam_ref;
-	} else {
-		/* Camera isn't stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_WFCAM_VSYNC, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case SSFC_SENSOR_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case SSFC_SENSOR_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static int board_has_keypad(void)
-{
-	return sku_id == 41 || sku_id == 42 || sku_id == 43 || sku_id == 44;
-}
-
-static void board_update_no_keypad_config_from_sku(void)
-{
-	if (!board_has_keypad()) {
-#ifndef TEST_BUILD
-		/* Disable scanning KSO13 & 14 if keypad isn't present. */
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-		keyscan_config.actual_key_mask[11] = 0xfa;
-		keyscan_config.actual_key_mask[12] = 0xca;
-
-		/* Search key is moved back to col=1,row=0 */
-		keyscan_config.actual_key_mask[0] = 0x14;
-		keyscan_config.actual_key_mask[1] = 0xff;
-#endif
-	}
-}
-
-static void board_usb_charge_mode_init(void)
-{
-	int i;
-
-	/*
-	 * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough because
-	 * USB_SYSJUMP_TAG preserves the settings to RW. And we should honor to it.
-	 */
-	if (system_jumped_late())
-		return;
-
-	/* Currently only blorb and droid support this feature. */
-	if ((sku_id < 32 || sku_id > 39) && (sku_id < 40 || sku_id > 47))
-		return;
-
-	/*
-	 * By default, turn the charging off when system suspends.
-	 * If system power on with connecting a USB device,
-	 * the OS must send an event to EC to clear the
-	 * inhibit_charging_in_suspend.
-	 */
-	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-				USB_DISALLOW_SUSPEND_CHARGE);
-}
-/*
- * usb_charge_init() is hooked in HOOK_PRIO_DEFAULT and set inhibit_charge to
- * USB_ALLOW_SUSPEND_CHARGE. As a result, in order to override this default
- * setting to USB_DISALLOW_SUSPEND_CHARGE this function should be hooked after
- * calling usb_charge_init().
- */
-DECLARE_HOOK(HOOK_INIT, board_usb_charge_mode_init, HOOK_PRIO_DEFAULT + 1);
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX)
-		return;
-	sku_id = val;
-	CPRINTSUSB("SKU: %d", sku_id);
-
-	board_update_sensor_config_from_sku();
-	board_update_no_keypad_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (sku_id == 33 || sku_id == 34 || sku_id == 41 || sku_id == 42)
-		return flags0;
-	else
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-}
-
-static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static void board_setup_ppc(void)
-{
-	if (!support_syv_ppc())
-		return;
-
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-	       &ppc_syv682x_port0,
-	       sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-	       &ppc_syv682x_port1,
-	       sizeof(struct ppc_config_t));
-
-	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
-	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
-}
-DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
-
-void board_hibernate_late(void) {
-
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
-
-	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
-}
diff --git a/board/bobba/board.h b/board/bobba/board.h
deleted file mode 100644
index 129f84b1a8..0000000000
--- a/board/bobba/board.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Bobba board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCEL_INFO
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_MFALLOW
-
-/* Reduce flash space usage */
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-#define CONFIG_LED_COMMON
-
-/*
- * Some bad battery which can report battery level correctly
- * but D-FET is disabled and can't be revived, so define reset
- * level to eable CL:1980406 function.
- */
-#define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel main source*/
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_SYNC		/* Camera VSYNC */
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* Motion Sense Task Events */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* Keyboard backliht */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-
-/* keypad */
-#define CONFIG_KEYBOARD_KEYPAD
-
-/* Additional PPC second source */
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#undef CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-
-#ifndef __ASSEMBLER__
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_SMP_AP13J7K,
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_LGC_AP19A8K,
-	BATTERY_LGC_G023,
-	BATTERY_PANASONIC_AP19A5K,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bobba/build.mk b/board/bobba/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/bobba/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/bobba/ec.tasklist b/board/bobba/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/bobba/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc
deleted file mode 100644
index edb76d05f6..0000000000
--- a/board/bobba/gpio.inc
+++ /dev/null
@@ -1,190 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT, 	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)            /* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,         PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(WFCAM_VSYNC,		PIN(0, 3), GPIO_INT_RISING , sync_interrupt)
-
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L, 	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_ORANGE_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_BLUE_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(LED_3_L,		 PIN(D, 7), GPIO_OUT_HIGH)
-
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	PIN(6, 2), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		PIN(9, 4), GPIO_ODR_HIGH)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(PPC_ID,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_DOWN)	/* PPC ID pin */
-
-/* Unused Pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/bobba/led.c b/board/bobba/led.c
deleted file mode 100644
index d833554ab4..0000000000
--- a/board/bobba/led.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Bobba
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Bobba: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/bobba/vif_override.xml b/board/bobba/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/bobba/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/boldar/battery.c b/board/boldar/battery.c
deleted file mode 100644
index 48f7fcda84..0000000000
--- a/board/boldar/battery.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/boldar/board.c b/board/boldar/board.c
deleted file mode 100644
index 49a3a79831..0000000000
--- a/board/boldar/board.c
+++ /dev/null
@@ -1,588 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN2,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3000,
-	.rpm_start = 3000,
-	.rpm_max = 10000,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(15),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(15),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/*
-		 * If using the side select to run both LEDs at the same time,
-		 * the frequency should be 1/2 of the color channel PWM
-		 * frequency to drive each LED equally.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Volteer specific USB daughter-board configuration */
-
-/* USBC TCPC configuration for USB3 daughter board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	if (usb_db == DB_USB3_ACTIVE) {
-		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	}
-}
-
-/*
- * Set up support for the USB3 daughterboard:
- *   Parade PS8815 TCPC (integrated retimer)
- *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
- *   Silergy SYV682A PPC (same as USB4 board)
- *   Virtual mux with stacked retimer
- */
-static void config_db_usb3_active(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
-}
-
-/*
- * Set up support for the passive USB3 daughterboard:
- *   TUSB422 TCPC (already the default)
- *   PI3USB9201 BC 1.2 chip (already the default)
- *   Silergy SYV682A PPC (already the default)
- *   Virtual mux without stacked retimer
- */
-
-static void config_db_usb3_passive(void)
-{
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
-}
-
-static void config_port_discrete_tcpc(int port)
-{
-	/*
-	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
-	 * simplicity allow either and decide at runtime which we are using.
-	 * Default to TUSB422, and switch to RT1715 if it is on the I2C bus and
-	 * the VID matches.
-	 */
-
-	int regval;
-
-	if (i2c_read16(port ? I2C_PORT_USB_C1 : I2C_PORT_USB_C0,
-		       RT1715_I2C_ADDR_FLAGS, TCPC_REG_VENDOR_ID,
-		       &regval) == EC_SUCCESS) {
-		if (regval == RT1715_VENDOR_ID) {
-			CPRINTS("C%d: RT1715 detected", port);
-			tcpc_config[port].i2c_info.addr_flags =
-				RT1715_I2C_ADDR_FLAGS;
-			tcpc_config[port].drv = &rt1715_tcpm_drv;
-			return;
-		}
-	}
-	CPRINTS("C%d: Default to TUSB422", port);
-}
-
-static const char *db_type_prefix = "USB DB type: ";
-__override void board_cbi_init(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	config_port_discrete_tcpc(0);
-	switch (usb_db) {
-	case DB_USB_ABSENT:
-		CPRINTS("%sNone", db_type_prefix);
-		break;
-	case DB_USB4_GEN2:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen1/2", db_type_prefix);
-		break;
-	case DB_USB4_GEN3:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen3", db_type_prefix);
-		break;
-	case DB_USB3_ACTIVE:
-		config_db_usb3_active();
-		CPRINTS("%sUSB3 Active", db_type_prefix);
-		break;
-	case DB_USB3_PASSIVE:
-		config_db_usb3_passive();
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB3 Passive", db_type_prefix);
-		break;
-	default:
-		CPRINTS("%sID %d not supported", db_type_prefix, usb_db);
-	}
-
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/boldar/board.h b/board/boldar/board.h
deleted file mode 100644
index 96289e71b7..0000000000
--- a/board/boldar/board.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* LIS2DH12 Lid accel */
-#define CONFIG_ACCEL_LIS2DH
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS/RGB */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-/*
- * USB ID
- * This is allocated specifically for Volteer
- * http://google3/hardware/standards/usb/
- */
-#define CONFIG_USB_PID 0x503E
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x37
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/boldar/build.mk b/board/boldar/build.mk
deleted file mode 100644
index 838d6a16ce..0000000000
--- a/board/boldar/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/boldar/ec.tasklist b/board/boldar/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/boldar/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/boldar/gpio.inc b/board/boldar/gpio.inc
deleted file mode 100644
index f41d198df5..0000000000
--- a/board/boldar/gpio.inc
+++ /dev/null
@@ -1,182 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Volteer, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C0_RT_RST_ODL,		PIN(4, 1), GPIO_ODR_LOW)	/* RST to Burnside bridge */
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C0_RT_INT_ODL,		PIN(F, 2), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(CATERR_L,			PIN(3, 4), GPIO_INPUT)		/* Catastrophic error */
-GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO96,             PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/boldar/led.c b/board/boldar/led.c
deleted file mode 100644
index 6ee71bbe19..0000000000
--- a/board/boldar/led.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
-
-/* Illuminates the LED on the side of the active charging port. If not charging,
- * illuminates both LEDs.
- */
-static void led_set_charge_port_tick(void)
-{
-	int port;
-	int side_select_duty;
-
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case 0:
-		side_select_duty = 100;
-		break;
-	case 1:
-		side_select_duty = 0;
-		break;
-	default:
-		side_select_duty = 50;
-	}
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
-}
-DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/boldar/sensors.c b/board/boldar/sensors.c
deleted file mode 100644
index 25fab11549..0000000000
--- a/board/boldar/sensors.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dh_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DH,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR0_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/boldar/vif_override.xml b/board/boldar/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/boldar/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/boten/battery.c b/board/boten/battery.c
deleted file mode 100644
index 0f4c8ffeb9..0000000000
--- a/board/boten/battery.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all boten battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L18D3PG1 Battery Information */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC L17L3PB0 Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Sunwoda L17M3PB0 Battery Information */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/boten/board.c b/board/boten/board.c
deleted file mode 100644
index b6301834bf..0000000000
--- a/board/boten/board.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Boten board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
-}
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/**
- * Deferred function to handle pen detect change
- */
-static void pendetect_deferred(void)
-{
-	static int debounced_pen_detect;
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	if (pen_detect == debounced_pen_detect)
-		return;
-
-	debounced_pen_detect = pen_detect;
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
-	gpio_set_level(GPIO_PEN_DET_PCH, !debounced_pen_detect);
-}
-DECLARE_DEFERRED(pendetect_deferred);
-
-void pen_detect_interrupt(enum gpio_signal s)
-{
-	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Charger IC need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(0, false);
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-};
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
-
-void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-	/* Enable gpio interrupt for pen detect */
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-
-	if (gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_PEN_DET_PCH, 1);
-
-	/* Set LEDs luminance */
-	pwm_set_duty(PWM_CH_LED_RED, 70);
-	pwm_set_duty(PWM_CH_LED_GREEN, 70);
-	pwm_set_duty(PWM_CH_LED_WHITE, 70);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	if (port != 0 && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	CPRINTUSB("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
-		raa489000_enable_asgate(0, false);
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTUSB("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTUSB("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_WHITE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	}
-
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* Sensor Data */
-static struct stprivate_data g_lis2dwl_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/boten/board.h b/board/boten/board.h
deleted file mode 100644
index 0e2a72015c..0000000000
--- a/board/boten/board.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Boten board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* DAC for PSYS */
-#define CONFIG_DAC
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux */
-#define CONFIG_USB_MUX_IT5205
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_WHITE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-void pen_detect_interrupt(enum gpio_signal s);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/boten/build.mk b/board/boten/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/boten/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/boten/cbi_ssfc.c b/board/boten/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/boten/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/boten/cbi_ssfc.h b/board/boten/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/boten/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/boten/ec.tasklist b/board/boten/ec.tasklist
deleted file mode 100644
index be1f92aff2..0000000000
--- a/board/boten/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/boten/gpio.inc b/board/boten/gpio.inc
deleted file mode 100644
index 4e8290c277..0000000000
--- a/board/boten/gpio.inc
+++ /dev/null
@@ -1,146 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Used by baseboard z-state enable, but not present on boten */
-UNIMPLEMENTED(USB_C1_INT_ODL)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-GPIO(EN_PP5000_PEN,	    	PIN(B, 5), GPIO_OUT_LOW)
-GPIO(PEN_DET_PCH,	    	PIN(F, 1), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL2_NC, PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* DAC */
-ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0) | BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* KB_BL_PWM, LED_[R,G,B]_ODL */
diff --git a/board/boten/led.c b/board/boten/led.c
deleted file mode 100644
index 93675966b3..0000000000
--- a/board/boten/led.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Boten specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
-	else
-		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/boten/usb_pd_policy.c b/board/boten/usb_pd_policy.c
deleted file mode 100644
index 65ee678263..0000000000
--- a/board/boten/usb_pd_policy.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	if (port != 0)
-		return;
-
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port != 0)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
diff --git a/board/boten/vif_override.xml b/board/boten/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/boten/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/brask/board.c b/board/brask/board.c
deleted file mode 100644
index a9c6b57ec5..0000000000
--- a/board/brask/board.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "power_button.h"
-#include "power.h"
-#include "switch.h"
-#include "throttle_ap.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-int board_set_active_charge_port(int port)
-{
-	/* TODO(b/197514362): set either barreljack or typec port */
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
-{
-}
diff --git a/board/brask/board.h b/board/brask/board.h
deleted file mode 100644
index 0d92b2c07f..0000000000
--- a/board/brask/board.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brask board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_MP2964
-
-/* Barrel Jack */
-#define DEDICATED_CHARGE_PORT 3
-
-/* HDMI CEC */
-#define CONFIG_CEC
-#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
-#define CEC_GPIO_IN  GPIO_HDMI_CEC_IN
-#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			4
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
-#define CONFIG_USB_PD_PPC
-#define CONFIG_USB_PD_TCPM_RT1715
-#define CONFIG_USBC_RETIMER_INTEL_BB
-/* TODO(b/197505149): need to fix the build error and clarify
- * how to set the usb_ls_en_gpio and retimer_rst_gpio
- * in the same array.
- */
-/* #define CONFIG_USBC_RETIMER_KB800X */
-#define CONFIG_USBC_PPC_SYV682X
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/* The design should support up to 100W. */
-/* TODO(b/197702356): Set the max PD to 60W now and change it
- * to 100W after we verify it.
- */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RECOVERY_L			GPIO_EC_RECOVERY_BTN_OD
-#define GPIO_RECOVERY_L_2		GPIO_GSC_EC_RECOVERY_BTN_OD
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_DP_REDRIVER		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_C2_TCPC		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC		NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_C2_PPC		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC		NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_BC12		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12		NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_MUX		NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX		NPCX_I2C_PORT6_1
-
-#define I2C_PORT_QI			NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/*
- * see b/174768555#comment22
- */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x57
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* ADC */
-#define CONFIG_ADC
-
-/*
- * TODO(b/197478860): Enable the fan control. We need
- * to check the sensor value and adjust the fan speed.
- */
-/* #define CONFIG_FANS			FAN_CH_COUNT */
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_CPU,
-	ADC_TEMP_SENSOR_2_CPU_VR,
-	ADC_TEMP_SENSOR_3_WIFI,
-	ADC_TEMP_SENSOR_4_DIMM,
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_CPU,
-	TEMP_SENSOR_2_CPU_VR,
-	TEMP_SENSOR_3_WIFI,
-	TEMP_SENSOR_4_DIMM,
-	TEMP_SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_GREEN,		/* PWM0 */
-	PWM_CH_FAN,                     /* PWM5 */
-	PWM_CH_LED_RED,                 /* PWM2 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/brask/build.mk b/board/brask/build.mk
deleted file mode 100644
index 442a708d78..0000000000
--- a/board/brask/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brask board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brask
-
-board-y=
-board-y+=board.o
-board-y+=i2c.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/brask/ec.tasklist b/board/brask/ec.tasklist
deleted file mode 100644
index 46863551f9..0000000000
--- a/board/brask/ec.tasklist
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CEC, cec_task, NULL, TASK_STACK_SIZE)
diff --git a/board/brask/gpio.inc b/board/brask/gpio.inc
deleted file mode 100644
index 01b82a2b74..0000000000
--- a/board/brask/gpio.inc
+++ /dev/null
@@ -1,182 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C2_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* CCD */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-
-/* Security */
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-
-/* Fan */
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-
-/* ADC, need to check the usage */
-GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
-
-/* Display */
-GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
-GPIO(HDMI_CONN_OC_ODL,               PIN(2, 4), GPIO_INPUT)
-
-/* BarrelJack */
-GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_INPUT)
-GPIO(BJ_ADP_PRESENT_ODL,             PIN(8, 2), GPIO_INPUT)
-
-/* Chipset PCH */
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-
-/* Button */
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_RECOVERY_BTN_OD,             PIN(2, 3), GPIO_INPUT)
-GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
-
-/* NFC */
-/* TODO(b/194068530): Enable NFC */
-GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
-GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
-GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
-
-/* Wireless Charger */
-/* TODO(b/191418683): Implement Qi Driver */
-GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_HIGH)
-GPIO(EC_I2C_QI_RESET_L,              PIN(9, 3), GPIO_OUT_HIGH)
-GPIO(EC_I2C_QI_INT_ODL,              PIN(9, 6), GPIO_INPUT)
-
-/* HDMI CEC */
-/* TODO(b/197474873): Enable HDMI CEC */
-GPIO(HDMI_CEC_IN,                    PIN(7, 3), GPIO_INPUT)
-GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
-GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
-
-/* I2C SCL/SDA */
-GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_DP_SCL,                  PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_DP_SDA,                  PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-
-/* USBA */
-GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
-GPIO(USB_A0_OC_ODL,                  PIN(3, 1), GPIO_INPUT)
-GPIO(USB_A1_OC_ODL,                  PIN(3, 0), GPIO_INPUT)
-GPIO(USB_A2_OC_ODL,                  PIN(2, 7), GPIO_INPUT)
-GPIO(USB_A3_OC_ODL,                  PIN(2, 6), GPIO_INPUT)
-GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
-GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
-GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,                PIN(1, 6), GPIO_INPUT)
-GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT)
-GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT)
-GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT)
-GPIO(USB_A_LOW_PWR3_OD,              PIN(1, 0), GPIO_INPUT)
-
-/* LED */
-/* TODO(b/197471359): LED implementation */
-GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
-GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
-
-/* USBC */
-GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-
-/* GPIO02_P2 to PU */
-/* GPIO03_P2 to PU */
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
-
-IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
-IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
-/* GPIO07_P2 to PU */
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
-UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
-UNUSED(PIN(9, 7))       /* GPIO97 */
-UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
-UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
-UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
-UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
-UNUSED(PIN(0, 5))       /* KSO12/GPIO05 */
-UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
-UNUSED(PIN(8, 0))       /* GPIO80/PWM3 */
diff --git a/board/brask/i2c.c b/board/brask/i2c.c
deleted file mode 100644
index 190f4f019e..0000000000
--- a/board/brask/i2c.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "dp_redriver",
-		.port = I2C_PORT_DP_REDRIVER,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_DP_SCL,
-		.sda = GPIO_EC_I2C_DP_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0,2",
-		.port = I2C_PORT_USB_C0_C2_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0,2",
-		.port = I2C_PORT_USB_C0_C2_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0,2",
-		.port = I2C_PORT_USB_C0_C2_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "wireless_charger",
-		.port = I2C_PORT_QI,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_QI_SCL,
-		.sda = GPIO_EC_I2C_QI_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/brask/led.c b/board/brask/led.c
deleted file mode 100644
index 6aaa890ec8..0000000000
--- a/board/brask/led.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Brask.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int green = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_GREEN:
-		green = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (green)
-		pwm_set_duty(PWM_CH_LED_GREEN, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_GREEN, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/*
- * When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec.
- */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/*
-	 * Assume there is no race condition with led_tick, which also
-	 * runs in hook_task.
-	 */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "green")) {
-		set_color(id, LED_GREEN, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/brask/pwm.c b/board/brask/pwm.c
deleted file mode 100644
index 5ad905f861..0000000000
--- a/board/brask/pwm.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000
-	},
-	[PWM_CH_LED_RED] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * TODO(b/197478860): Turn on the fan at 100% by default
-	 * We need to find tune the fan speed according to the
-	 * thermal sensor value.
-	 */
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, 100);
-
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_GREEN, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/brask/sensors.c b/board/brask/sensors.c
deleted file mode 100644
index 72b8297aa1..0000000000
--- a/board/brask/sensors.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "adc_chip.h"
-#include "hooks.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_CPU] = {
-		.name = "TEMP_CPU",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_CPU_VR] = {
-		.name = "TEMP_CPU_VR",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_WIFI] = {
-		.name = "TEMP_WIFI",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_DIMM] = {
-		.name = "TEMP_DIMM",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_CPU
-	},
-	[TEMP_SENSOR_2_CPU_VR] = {
-		.name = "CPU VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_CPU_VR
-	},
-	[TEMP_SENSOR_3_WIFI] = {
-		.name = "WIFI",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_WIFI
-	},
-	[TEMP_SENSOR_4_DIMM] = {
-		.name = "DIMM",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_DIMM
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/197478860): add the thermal sensor setting
- */
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CPU] = thermal_cpu,
-	[TEMP_SENSOR_2_CPU_VR] = thermal_cpu,
-	[TEMP_SENSOR_3_WIFI] = thermal_cpu,
-	[TEMP_SENSOR_4_DIMM] = thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/brask/usbc_config.c b/board/brask/usbc_config.c
deleted file mode 100644
index bd61f7ec1c..0000000000
--- a/board/brask/usbc_config.c
+++ /dev/null
@@ -1,389 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/retimer/kb800x.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		/* TODO(b/197505149): need to fix the build error and
-		 * clarify how to set the usb_ls_en_gpio and
-		 * retimer_rst_gpio in the same array.
-		 */
-		/*.driver = &kb800x_usb_mux_driver, */
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C2 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C2) {
-		rst_signal = IOEX_USB_C2_RT_RST_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-__override int bb_retimer_reset(const struct usb_mux *me)
-{
-	/*
-	 * TODO(b/193402306, b/195375738): Remove this once transition to
-	 * QS Silicon is complete
-	 */
-	bb_retimer_power_enable(me, false);
-	msleep(5);
-	bb_retimer_power_enable(me, true);
-	msleep(25);
-
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum gpio_signal tcpc_rst;
-
-	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
-
-	/*
-	 * TODO(b/179648104): figure out correct timing
-	 */
-
-	gpio_set_level(tcpc_rst, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(tcpc_rst, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-static void enable_ioex(int ioex)
-{
-	ioex_config[ioex].flags &= ~IOEX_FLAGS_DISABLED;
-	ioex_init(ioex);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		/*
-		 * These IO expander pins are implemented using the
-		 * C0/C2 TCPC, so they must be set up after the TCPC has
-		 * been taken out of reset.
-		 */
-		enable_ioex(IOEX_C0_NCT38XX);
-		enable_ioex(IOEX_C2_NCT38XX);
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
-
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C2)
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_C2_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	return true;
-}
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	if (!board_is_tbt_usb4_port(port))
-		return TBT_SS_RES_0;
-
-	return TBT_SS_TBT_GEN3;
-}
diff --git a/board/brask/usbc_config.h b/board/brask/usbc_config.h
deleted file mode 100644
index 7319bcb5e2..0000000000
--- a/board/brask/usbc_config.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	3
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/brask/vif_override.xml b/board/brask/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/brask/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/brya/battery.c b/board/brya/battery.c
deleted file mode 100644
index a18ab029b6..0000000000
--- a/board/brya/battery.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Brya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* POW-TECH GQA05 Battery Information */
-	[BATTERY_POWER_TECH] = {
-		/* BQ40Z50 Fuel Gauge */
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.device_name = "BATGQA05L22",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,		/* XDSG */
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 280,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -10,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
diff --git a/board/brya/board.c b/board/brya/board.c
deleted file mode 100644
index 1935988607..0000000000
--- a/board/brya/board.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "driver/als_tcs3400.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-__override void board_cbi_init(void)
-{
-	config_usb_db_type();
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-
-	if (get_board_id() == 1)
-		gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 1);
-	else
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-
-	if (get_board_id() == 1)
-		gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 0);
-	else
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO(b/181508008): tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-
-	if (get_board_id() == 1)
-		batt_pres = GPIO_ID_1_EC_BATT_PRES_ODL;
-	else
-		batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
-
-/*
- * Explicitly apply the board ID 1 *gpio.inc settings to pins that
- * were reassigned on current boards.
- */
-
-static void set_board_id_1_gpios(void)
-{
-	if (get_board_id() != 1)
-		return;
-
-	gpio_set_flags(GPIO_ID_1_EC_KB_BL_EN, GPIO_OUT_LOW);
-}
-DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST);
-
-/*
- * Reclaim GPIO pins on board ID 1 that are used as ADC inputs on
- * current boards. ALT function group MODULE_ADC pins are set in
- * HOOK_PRIO_INIT_ADC and can be reclaimed right after the hook runs.
- */
-
-static void board_id_1_reclaim_adc(void)
-{
-	if (get_board_id() != 1)
-		return;
-
-	/*
-	 * GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL is on GPIO34
-	 *
-	 * The TCPC has already been reset by board_tcpc_init() executed
-	 * from HOOK_PRIO_INIT_CHIPSET. Later, the pin gets set to ADC6
-	 * in HOOK_PRIO_INIT_ADC, so we simply need to set the pin back
-	 * to GPIO34.
-	 */
-	gpio_set_flags(GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL, GPIO_ODR_HIGH);
-	gpio_set_alternate_function(GPIO_PORT_3, BIT(4), GPIO_ALT_FUNC_NONE);
-
-	/*
-	 * The pin gets set to ADC7 in HOOK_PRIO_INIT_ADC, so we simply
-	 * need to set it back to GPIOE1.
-	 */
-	gpio_set_flags(GPIO_ID_1_EC_BATT_PRES_ODL, GPIO_INPUT);
-	gpio_set_alternate_function(GPIO_PORT_E, BIT(1), GPIO_ALT_FUNC_NONE);
-}
-DECLARE_HOOK(HOOK_INIT, board_id_1_reclaim_adc, HOOK_PRIO_INIT_ADC + 1);
diff --git a/board/brya/board.h b/board/brya/board.h
deleted file mode 100644
index a7e91a0507..0000000000
--- a/board/brya/board.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/*
- * Early brya boards are not set up for vivaldi
- */
-#undef CONFIG_KEYBOARD_VIVALDI
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 2
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-#undef CONFIG_LED_PWM_LOW_BATT_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-/* Lid accel */
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		4
-
-#define CONFIG_USB_PD_TCPM_PS8815
-#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/*
- * see b/174768555#comment22
- */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x57
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-#define CONFIG_FANS			FAN_CH_COUNT
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Older boards have a different ADC assignment.
- */
-
-#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_AMBIENT,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_WWAN,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_AMBIENT,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_WWAN,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_ID_1_C0_NCT38XX,
-	IOEX_ID_1_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED3,			/* PWM1 (orange on DB) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (white on DB) */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/brya/build.mk b/board/brya/build.mk
deleted file mode 100644
index 674c17c1df..0000000000
--- a/board/brya/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brya board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=tune_mp2964.o
-board-y+=usbc_config.o
diff --git a/board/brya/charger.c b/board/brya/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/brya/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/brya/ec.tasklist b/board/brya/ec.tasklist
deleted file mode 100644
index 470a1fcdde..0000000000
--- a/board/brya/ec.tasklist
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/brya/fans.c b/board/brya/fans.c
deleted file mode 100644
index 021f0de8e2..0000000000
--- a/board/brya/fans.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/181271666): thermistor placement and calibration
- *
- * Prototype fan spins at about 4200 RPM at 100% PWM, this
- * is specific to board ID 2 and might also apears in later
- * boards as well.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 4200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/brya/fw_config.c b/board/brya/fw_config.c
deleted file mode 100644
index fb8acb635d..0000000000
--- a/board/brya/fw_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union brya_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union brya_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Brya FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
-}
-
-union brya_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
diff --git a/board/brya/fw_config.h b/board/brya/fw_config.h
deleted file mode 100644
index 6e4eb3ef58..0000000000
--- a/board/brya/fw_config.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Brya board.
- *
- * Source of truth is the project/brya/brya/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1,
-	DB_USB_ABSENT2 = 15
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union brya_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union brya_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/brya/generated-gpio.inc b/board/brya/generated-gpio.inc
deleted file mode 100644
index 4daa60c5c9..0000000000
--- a/board/brya/generated-gpio.inc
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file was auto-generated.
- */
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-
-/* Pre-configured PSL balls:  J8  K6 */
diff --git a/board/brya/gpio.inc b/board/brya/gpio.inc
deleted file mode 100644
index 79a97b0475..0000000000
--- a/board/brya/gpio.inc
+++ /dev/null
@@ -1,74 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/*
- * Generated-gpio.inc is produced using a Brya specific tool that
- * parses the GPIO definitions derived from the board schematics and
- * EC pinout descriptions derived form the chip datasheets to generate
- * the Chrome EC GPIO pinout definitions. Due to the confidential
- * nature of schematics and datasheets, they are not provided here.
- *
- * Variants that do not auto-generate their GPIO definitions should
- * combine the Brya gpio.inc and generated-gpio.inc into their
- * gpio.inc and customize as appropriate.
- */
-
-#include "generated-gpio.inc"
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-/*
- * GPIOE1 is an ALT function ADC INPUT on board ID 2 and a GPIO INPUT on
- * board ID 1. This declaration gives us a signal name to use on board
- * ID 1.
- */
-GPIO(ID_1_EC_BATT_PRES_ODL,       PIN(E, 1), GPIO_INPUT)
-
-/*
- * GPIO34 is an INPUT on board ID 2 and ODR_LOW on board ID 1.
- *
- * Since this pin is pulled up to 3.3V through a 30.9K ohm resistor on
- * board ID 2, we will leak about 0.3mW until the pin is put in ALT mode
- * when MODULE_ADC configuration runs. Initializing the pin to ODR_LOW
- * gives us full control on both boards.
- */
-GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW)
-
-/* Board ID 1 IO expander configuration */
-
-IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
-/* GPIO03_P1 to PU */
-IOEX(ID_1_USB_C0_FRS_EN,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(ID_1_USB_C0_OC_ODL,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-/* GPIO07_P1 to PU */
-
-IOEX(ID_1_USB_C2_RT_RST_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-/* GPIO03_P2 to PU */
-IOEX(ID_1_USB_C2_FRS_EN,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(ID_1_USB_C1_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-IOEX(ID_1_USB_C2_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH)
-
-/* Board ID 2 IO expander configuration */
-
-/* GPIO02_P2 to PU */
-/* GPIO03_P2 to PU */
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
-
-IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
-IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
-/* GPIO07_P2 to PU */
diff --git a/board/brya/i2c.c b/board/brya/i2c.c
deleted file mode 100644
index bb55b13d0c..0000000000
--- a/board/brya/i2c.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0,2",
-		.port = I2C_PORT_USB_C0_C2_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0,2",
-		.port = I2C_PORT_USB_C0_C2_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0,2",
-		.port = I2C_PORT_USB_C0_C2_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/brya/keyboard.c b/board/brya/keyboard.c
deleted file mode 100644
index a9f033130d..0000000000
--- a/board/brya/keyboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/brya/led.c b/board/brya/led.c
deleted file mode 100644
index 68945ec79e..0000000000
--- a/board/brya/led.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya specific PWM LED settings: there are 2 LEDs on each side of the board,
- * each one can be controlled separately. The LED colors are white or amber,
- * and the default behavior is tied to the charging process: both sides are
- * amber while charging the battery and white when the battery is charged.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * We only have a white and an amber LED, so setting any other color results in
- * both LEDs being off.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
-};
-
-/* Two logical LEDs with amber and white channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1,
-		.ch1 = PWM_CH_LED2,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-	{
-		.ch0 = PWM_CH_LED3,
-		.ch1 = PWM_CH_LED4,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		pwm_id = PWM_LED0;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		pwm_id = PWM_LED1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/brya/pwm.c b/board/brya/pwm.c
deleted file mode 100644
index 6e662f8e7d..0000000000
--- a/board/brya/pwm.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED2] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED3] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED1] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000
-	},
-	[PWM_CH_LED4] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn on all the LED at 50%.
-	 * Turn on the fan at 100%.
-	 */
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_set_duty(PWM_CH_LED1, 50);
-	pwm_enable(PWM_CH_LED2, 1);
-	pwm_set_duty(PWM_CH_LED2, 50);
-	pwm_enable(PWM_CH_LED3, 1);
-	pwm_set_duty(PWM_CH_LED3, 50);
-	pwm_enable(PWM_CH_LED4, 1);
-	pwm_set_duty(PWM_CH_LED4, 50);
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/brya/sensors.c b/board/brya/sensors.c
deleted file mode 100644
index d4fd905884..0000000000
--- a/board/brya/sensors.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "driver/als_tcs3400_public.h"
-#include "hooks.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_AMBIENT] = {
-		.name = "TEMP_AMBIENT",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_WWAN] = {
-		.name = "TEMP_WWAN",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-static struct stprivate_data g_lis2dw12_data;
-static struct lsm6dso_data lsm6dso_data;
-
-/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DW12,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dw12_data,
-		.int_signal = GPIO_EC_ACCEL_INT_R_L,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Enable gpio interrupt for lid accel sensor */
-	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
-	},
-	[TEMP_SENSOR_2_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER,
-	},
-	[TEMP_SENSOR_4_WWAN] = {
-		.name = "WWAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_WWAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(60),
-};
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_ambient = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(60),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 125C, max absolute temperature 150C
- * PP3300 regulator: operating range -40 C to 125 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(105),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(120),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(65),
-};
-
-/*
- * TODO(b/180681346): update for brya WWAN module
- */
-static const struct ec_thermal_config thermal_wwan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(130),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(130),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(60),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_AMBIENT]	= thermal_ambient,
-	[TEMP_SENSOR_3_CHARGER] = thermal_charger,
-	[TEMP_SENSOR_4_WWAN] = thermal_wwan,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static void board_thermals_init(void)
-{
-	if (get_board_id() == 1) {
-		/*
-		 * Board ID 1 only has 3 sensors and the AMBIENT sensor
-		 * ADC pins have been reassigned, so we're down to 2
-		 * sensors that can easily be configured. So, alias the
-		 * AMBIENT sensor ADC channel to the unimplemented ADC
-		 * slots.
-		 */
-		adc_channels[ADC_TEMP_SENSOR_3_CHARGER].input_ch = NPCX_ADC_CH1;
-		adc_channels[ADC_TEMP_SENSOR_4_WWAN].input_ch = NPCX_ADC_CH1;
-	}
-}
-
-DECLARE_HOOK(HOOK_INIT, board_thermals_init, HOOK_PRIO_INIT_CHIPSET);
diff --git a/board/brya/tune_mp2964.c b/board/brya/tune_mp2964.c
deleted file mode 100644
index 198f06d8eb..0000000000
--- a/board/brya/tune_mp2964.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tune the MP2964 IMVP9.1 parameters for brya */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "mp2964.h"
-
-const static struct mp2964_reg_val rail_a[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-const static struct mp2964_reg_val rail_b[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-
-static void mp2964_on_startup(void)
-{
-	static int chip_updated;
-	int status;
-
-	if (get_board_id() != 1)
-		return;
-
-	if (chip_updated)
-		return;
-
-	chip_updated = 1;
-
-	ccprintf("%s: attempting to tune PMIC\n", __func__);
-
-	status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a),
-			     rail_b, ARRAY_SIZE(rail_b));
-	if (status != EC_SUCCESS)
-		ccprintf("%s: could not update all settings\n", __func__);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup,
-	     HOOK_PRIO_FIRST);
diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c
deleted file mode 100644
index 1780e1e16d..0000000000
--- a/board/brya/usbc_config.c
+++ /dev/null
@@ -1,465 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		/* Compatible with Silicon Mitus SM536A0 */
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		/*
-		 * b/179987870
-		 * schematics I2C map says ADDR3
-		 */
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set
- * to the virtual_usb_mux_driver so the AP gets notified of mux changes
- * and updates the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C2 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_ID_1_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_ID_1_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-void config_usb_db_type(void)
-{
-	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
-
-	/*
-	 * TODO(b/180434685): implement multiple DB types
-	 */
-
-	CPRINTS("Configured USB DB type number is %d", db_type);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		if (get_board_id() == 1)
-			rst_signal = IOEX_ID_1_USB_C0_RT_RST_ODL;
-		else
-			rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C2) {
-		if (get_board_id() == 1)
-			rst_signal = IOEX_ID_1_USB_C2_RT_RST_ODL;
-		else
-			rst_signal = IOEX_USB_C2_RT_RST_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-		if (get_board_id() == 1) {
-			int val;
-
-			/*
-			 * Check if we were able to deassert
-			 * reset. Board ID 1 uses a GPIO that is
-			 * uncontrollable when a debug accessory is
-			 * connected.
-			 */
-			if (ioex_get_level(rst_signal, &val) != EC_SUCCESS)
-				return EC_ERROR_UNKNOWN;
-			if (val != 1)
-				return EC_ERROR_NOT_POWERED;
-		}
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum gpio_signal tcpc_rst;
-
-	if (get_board_id() == 1)
-		tcpc_rst = GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL;
-	else
-		tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
-
-	/*
-	 * TODO(b/179648104): figure out correct timing
-	 */
-
-	gpio_set_level(tcpc_rst, 0);
-	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
-		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-	}
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(tcpc_rst, 1);
-	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
-		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-	}
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-static void enable_ioex(int ioex)
-{
-	ioex_config[ioex].flags &= ~IOEX_FLAGS_DISABLED;
-	ioex_init(ioex);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		/*
-		 * These IO expander pins are implemented using the
-		 * C0/C2 TCPC, so they must be set up after the TCPC has
-		 * been taken out of reset.
-		 */
-		if (get_board_id() == 1) {
-			enable_ioex(IOEX_ID_1_C0_NCT38XX);
-			enable_ioex(IOEX_ID_1_C2_NCT38XX);
-		} else {
-			enable_ioex(IOEX_C0_NCT38XX);
-			enable_ioex(IOEX_C2_NCT38XX);
-		}
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
-
-	if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
-		gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-		gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-		gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
-
-	if ((ec_cfg_usb_db_type() != DB_USB_ABSENT) &&
-	    gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if ((port == USBC_PORT_C1) &&
-		 (ec_cfg_usb_db_type() != DB_USB_ABSENT))
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C2)
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_C2_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
-			break;
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		if (ec_cfg_usb_db_type() == DB_USB_ABSENT)
-			break;
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		switch (ec_cfg_usb_db_type()) {
-		case DB_USB_ABSENT:
-		case DB_USB_ABSENT2:
-			break;
-		case DB_USB3_PS8815:
-			nx20p348x_interrupt(USBC_PORT_C1);
-			break;
-		}
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	if (port == USBC_PORT_C0 || port == USBC_PORT_C2)
-		return true;
-
-	return false;
-}
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	if (!board_is_tbt_usb4_port(port))
-		return TBT_SS_RES_0;
-
-	return TBT_SS_TBT_GEN3;
-}
diff --git a/board/brya/usbc_config.h b/board/brya/usbc_config.h
deleted file mode 100644
index 5d08a446fb..0000000000
--- a/board/brya/usbc_config.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	3
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/brya/vif_override.xml b/board/brya/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/brya/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/bugzzy/battery.c b/board/bugzzy/battery.c
deleted file mode 100644
index 55932feccf..0000000000
--- a/board/bugzzy/battery.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/*
- * Battery info for all bugzzy battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- *
- * Battery FET Status in Manufacture Access : bit15 & bit14
- *  b'00 - dfet : on / cfet : on
- *  b'01 - dfet : on / cfet : off
- *  b'10 - dfet : off / cfet : off
- *  b'11 - dfet : off / cfet : on
- *  The value b'10 is disconnect_val, so we can use b'01 for cfet_off_val
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* SDI Battery Information */
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4404D57",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0xc000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8700,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 55,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-/* Lower our input voltage to 5V in S0iX when battery is full. */
-#define PD_VOLTAGE_WHEN_FULL 5000
-static void reduce_input_voltage_when_full(void)
-{
-	static int saved_input_voltage = -1;
-	int max_pd_voltage_mv = pd_get_max_voltage();
-	int port;
-
-	if (charge_get_percent() == 100 &&
-			chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
-			saved_input_voltage = max_pd_voltage_mv;
-			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
-		}
-	} else if (saved_input_voltage != -1) {
-		if (max_pd_voltage_mv == PD_VOLTAGE_WHEN_FULL)
-			max_pd_voltage_mv = saved_input_voltage;
-		saved_input_voltage = -1;
-	}
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full,
-		HOOK_PRIO_DEFAULT);
diff --git a/board/bugzzy/board.c b/board/bugzzy/board.c
deleted file mode 100644
index 2d24c9553a..0000000000
--- a/board/bugzzy/board.c
+++ /dev/null
@@ -1,759 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2ds.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_8042.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.input_ch = NPCX_ADC_CH5,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Skin1",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Skin2",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-void board_init(void)
-{
-	int on;
-
-	/* Enable C0 interrupt and check if it needs processing */
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-
-		/* Set HDMI and sub-rail enables to output */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
-			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
-
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-
-		/* Enable interrupt for passing through HPD */
-		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-	} else {
-		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
-
-		/* Enable C1 interrupt and check if it needs processing */
-		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
-		check_c1_line();
-	}
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, false);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC, or send enable signal to HDMI
-	 * DB.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
-	} else {
-		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
-	}
-
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CHARGER_NUM - 1;
-	else
-		return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static struct stprivate_data g_lis2ds_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DS,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2ds_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2ds_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DS_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DS_ODR_MIN_VAL,
-		.max_frequency = LIS2DS_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-static int ps8743_tune_mux_c0(const struct usb_mux *me);
-static int ps8743_tune_mux_c1(const struct usb_mux *me);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_init = &ps8743_tune_mux_c0,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_init = &ps8743_tune_mux_c1,
-	}
-};
-/* USB Mux C0 : board_init of PS8743 */
-static int ps8743_tune_mux_c0(const struct usb_mux *me)
-{
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
-
-	return EC_SUCCESS;
-}
-/* USB Mux C1 : board_init of PS8743 */
-static int ps8743_tune_mux_c1(const struct usb_mux *me)
-{
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
-
-	ps8743_write(me,
-			PS8743_REG_USB_SWING,
-			PS8743_LFPS_SWG_TD);
-	ps8743_write(me,
-			PS8743_REG_DP_SETTING,
-			PS8743_DP_SWG_ADJ_P15P);
-
-	return EC_SUCCESS;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	/*
-	 * Future boards should use fw_config if needed.
-	 */
-
-	return &keybd1;
-}
-
-#ifndef TEST_BUILD
-/* This callback disables keyboard when convertibles are fully open */
-void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif
-/**
- * Enable panel power detection
- */
-static void panel_power_detect_init(void)
-{
-	gpio_enable_interrupt(GPIO_EN_PP1800_PANEL_S0);
-}
-DECLARE_HOOK(HOOK_INIT, panel_power_detect_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Handle VPN / VSN for mipi display.
- */
-static void panel_power_change_deferred(void)
-{
-	int signal = gpio_get_level(GPIO_EN_PP1800_PANEL_S0);
-
-	gpio_set_level(GPIO_EN_LCD_ENP, signal);
-	msleep(1);
-	gpio_set_level(GPIO_EN_LCD_ENN, signal);
-
-	gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present());
-}
-DECLARE_DEFERRED(panel_power_change_deferred);
-
-void panel_power_change_interrupt(enum gpio_signal signal)
-{
-	/* Reset lid debounce time */
-	hook_call_deferred(&panel_power_change_deferred_data, 1 * MSEC);
-}
-
-/**
- * Handle TSP_TA according to AC status
- */
-static void handle_tsp_ta(void)
-{
-	int signal = gpio_get_level(GPIO_EN_PP1800_PANEL_S0);
-
-	gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, handle_tsp_ta, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
diff --git a/board/bugzzy/board.h b/board/bugzzy/board.h
deleted file mode 100644
index 2697e17d8c..0000000000
--- a/board/bugzzy/board.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-/*
- * Keep the system unlocked in early development.
- * TODO(b/151264302): Make sure to remove this before production!
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Save some flash space */
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_BATTFAKE
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#define CONFIG_CHARGE_RAMP_HW
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
-
-/* Keyboard */
-
-/* LED */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
-
-
-/* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USB_MUX_PS8743
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-#define CONFIG_USB_PD_COMM_LOCKED
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-#undef PD_POWER_SUPPLY_TURN_ON_DELAY
-#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-/* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/*
- * I2C pin names for baseboard
- *
- * Note: these lines will be set as i2c on start-up, but this should be
- * okay since they're ODL.
- */
-#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
-#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/* LIS2DS Lid accel */
-#define CONFIG_ACCEL_LIS2DS
-#define CONFIG_ACCEL_LIS2DS_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_TEMP_SENSOR_3,     /* ADC5 */
-	ADC_TEMP_SENSOR_4,     /* ADC6 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-void panel_power_change_interrupt(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/bugzzy/build.mk b/board/bugzzy/build.mk
deleted file mode 100644
index 815a285d83..0000000000
--- a/board/bugzzy/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/bugzzy/cbi_ssfc.c b/board/bugzzy/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/bugzzy/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/bugzzy/cbi_ssfc.h b/board/bugzzy/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/bugzzy/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/bugzzy/ec.tasklist b/board/bugzzy/ec.tasklist
deleted file mode 100644
index d4fb416bce..0000000000
--- a/board/bugzzy/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/bugzzy/gpio.inc b/board/bugzzy/gpio.inc
deleted file mode 100644
index 979b2867c0..0000000000
--- a/board/bugzzy/gpio.inc
+++ /dev/null
@@ -1,139 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,          PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,          PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_FALLING | GPIO_SEL_1P8V, lis2ds_interrupt)
-GPIO_INT(EN_PP1800_PANEL_S0,     PIN(4, 1), GPIO_INT_BOTH, panel_power_change_interrupt)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-GPIO(LED_R_ODL,		PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(LED_G_ODL,		PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_B_ODL,		PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EN_LCD_ENN,	PIN(9, 7), GPIO_OUT_LOW)
-GPIO(EN_LCD_ENP,	PIN(8, 6), GPIO_OUT_LOW)
-GPIO(TSP_TA,		PIN(A, 2), GPIO_OUT_LOW)
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(EN_USB_A0_VBUS,	     PIN(6, 3), GPIO_OUT_LOW)
-
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-ALTERNATE(PIN_MASK(3, 0x90), 0, MODULE_ADC, 0)	/* ADC5-6 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_DOWN)
diff --git a/board/bugzzy/led.c b/board/bugzzy/led.c
deleted file mode 100644
index d04026e0f0..0000000000
--- a/board/bugzzy/led.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for bugzzy
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* bugzzy : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	if (color == EC_LED_COLOR_BLUE)
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	/*
-	 * Battery leds must be turn off when blue led is on
-	 * because bugzzy has 3-in-1 led.
-	 */
-	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-				!brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L,
-				!brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-				!brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/bugzzy/usb_pd_policy.c b/board/bugzzy/usb_pd_policy.c
deleted file mode 100644
index 15faf41ffc..0000000000
--- a/board/bugzzy/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/bugzzy/vif_override.xml b/board/bugzzy/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/bugzzy/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/burnet/battery.c b/board/burnet/battery.c
deleted file mode 100644
index 35a2ebc7df..0000000000
--- a/board/burnet/battery.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* Dynapack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Dynapack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Simplo CosMX Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_ATL;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/burnet/board.c b/board/burnet/board.c
deleted file mode 100644
index d932624b0a..0000000000
--- a/board/burnet/board.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-	force_discharge = enable;
-
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-/*
- * Returns 1 for boards that are convertible into tablet mode, and
- * zero for clamshells.
- */
-int board_is_convertible(void)
-{
-	/*
-	 * Burnet: 17
-	 * Esche: 16
-	 */
-	return system_get_sku_id() == 17;
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_bmi160_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_icm426xx_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-struct motion_sensor_t lid_accel_kx022 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_SENSORS,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.default_range = 2,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t base_accel_icm426xx = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = CONFIG_SPI_ACCEL_PORT,
-	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	.default_range = 4,
-	.rot_standard_ref = &base_icm426xx_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t base_gyro_icm426xx = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = CONFIG_SPI_ACCEL_PORT,
-	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm426xx_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = &base_bmi160_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_bmi160_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void sensor_interrupt(enum gpio_signal signal)
-{
-	switch (motion_sensors[BASE_ACCEL].chip) {
-	case MOTIONSENSE_CHIP_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case MOTIONSENSE_CHIP_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static void board_update_config(void)
-{
-	int val;
-	enum ec_error_list rv;
-
-	/* Ping for ack */
-	rv = i2c_read8(I2C_PORT_SENSORS,
-		       KX022_ADDR1_FLAGS, KX022_WHOAMI, &val);
-
-	if (rv == EC_SUCCESS)
-		motion_sensors[LID_ACCEL] = lid_accel_kx022;
-
-	/* Read icm-40608 chip content */
-	rv = icm_read8(&base_accel_icm426xx, ICM426XX_REG_WHO_AM_I, &val);
-
-	if (rv == EC_SUCCESS && val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = base_accel_icm426xx;
-		motion_sensors[BASE_GYRO] = base_gyro_icm426xx;
-	}
-
-	CPRINTS("Lid Accel Chip: %d", motion_sensors[LID_ACCEL].chip);
-	CPRINTS("Base Accel Chip: %d", motion_sensors[BASE_ACCEL].chip);
-}
-
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable interrupts from BMI160 sensor. */
-		gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-		/* For some reason we have to do this again in case of sysjump */
-		board_spi_enable();
-		board_update_config();
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Turn off GMR interrupt */
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_ACCEL_INT_ODL,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-		board_spi_disable();
-	}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/burnet/board.h b/board/burnet/board.h
deleted file mode 100644
index 009da83ac5..0000000000
--- a/board/burnet/board.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Burnet */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_VENDOR_PARAM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-/* ICM426XX Base accel/gyro */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_COS,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger */
-int board_get_charger_i2c(void);
-
-int board_is_convertible(void);
-
-/* Motion sensor interrupt */
-void sensor_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/burnet/build.mk b/board/burnet/build.mk
deleted file mode 100644
index a6e1c010d7..0000000000
--- a/board/burnet/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/burnet/ec.tasklist b/board/burnet/ec.tasklist
deleted file mode 100644
index c1330b86f8..0000000000
--- a/board/burnet/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/burnet/gpio.inc b/board/burnet/gpio.inc
deleted file mode 100644
index c43a232870..0000000000
--- a/board/burnet/gpio.inc
+++ /dev/null
@@ -1,120 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         sensor_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/burnet/led.c b/board/burnet/led.c
deleted file mode 100644
index 1f2b75325c..0000000000
--- a/board/burnet/led.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Kappa
- */
-
-#include "charge_state.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "led_common.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_OFF);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_ON);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_OFF);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	case EC_LED_ID_POWER_LED:
-		rv = led_set_color_power(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LED for Esche, Esche don't have power LED,
-	 * blinking battery white LED to indicate system suspend without
-	 * charging.
-	 */
-	if (!board_is_convertible()) {
-		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/burnet/vif_override.xml b/board/burnet/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/burnet/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/c2d2/board.c b/board/c2d2/board.c
deleted file mode 100644
index 3327ea43b6..0000000000
--- a/board/c2d2/board.c
+++ /dev/null
@@ -1,1095 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* C2D2 debug device board configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_ite_flash_support.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "update_fw.h"
-#include "usart_rx_dma.h"
-#include "usart_tx_dma.h"
-#include "usart-stm32f0.h"
-#include "usb_hw.h"
-#include "usb_i2c.h"
-#include "usb_spi.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Forward declarations */
-static void update_vrefs_and_shifters(void);
-DECLARE_DEFERRED(update_vrefs_and_shifters);
-static bool is_ec_i2c_enabled(void);
-
-/* Global state tracking current pin configuration and operations */
-static struct mutex vref_bus_state_mutex;
-static int vref_monitor_disable;
-#define VREF_MON_DIS_H1_RST_HELD	BIT(0)
-#define VREF_MON_DIS_EC_PWR_HELD	BIT(1)
-#define VREF_MON_DIS_SPI_MODE		BIT(2)
-
-/*
- * Tracks if bus pins are locked by a function like UART holding, I2C,
- * or SPI.
- */
-enum bus_lock {
-	BUS_UNLOCKED,	/* Normal UART; pins available for other functions */
-	BUS_UART_HELD,	/* UART locked to pins while holding RX low */
-	BUS_SPI,	/* SPI locked to pins */
-	BUS_I2C,	/* I2C bus locked to pins */
-};
-/* A0/A1 (H1 UART or SPI) */
-enum bus_lock h1_pins;
-/* B6/B7 (EC UART, EC I2C, or SPI) */
-enum bus_lock ec_pins;
-/* B10/B11 (AP UART, AUX I2C) */
-enum bus_lock ap_pins;
-
-static const char *lock_to_string(const enum bus_lock val)
-{
-	static const char *const names[] = {
-		[BUS_UNLOCKED] = "UART",
-		[BUS_UART_HELD] = "UART HELD",
-		[BUS_SPI] = "SPI",
-		[BUS_I2C] = "I2C",
-	};
-
-	if (val < 0 || val >= ARRAY_SIZE(names))
-		return "UNKNOWN";
-
-	return names[val];
-}
-
-static int command_bus_status(int argc, char **argv)
-{
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	ccprintf("H1 pins: %s\n", lock_to_string(h1_pins));
-	ccprintf("EC pins: %s\n", lock_to_string(ec_pins));
-	ccprintf("AP pins: %s\n", lock_to_string(ap_pins));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status,
-			"",
-			"Gets the bus state for swappable pins");
-
-
-/******************************************************************************
- ** Chip-specific board configuration
- */
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG & COMP clock */
-	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
-
-	/* enable DAC for comparator input */
-	STM32_RCC_APB1ENR |= STM32_RCC_DACEN;
-
-	/*
-	 * the DMA mapping is :
-	 *  Chan 3 : USART3_RX
-	 *  Chan 5 : USART1_RX
-	 *  Chan 6 : SPI2_RX
-	 *  Chan 7 : SPI2_TX
-	 *
-	 *  i2c : no dma
-	 *  tim16/17: no dma
-	 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);	/* Remap SPI2_RX to channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
-	STM32_SYSCFG_CFGR1 |= BIT(10);  /* Remap USART1 RX/TX DMA */
-}
-
-
-/******************************************************************************
- ** ADC channels
- */
-const struct adc_t adc_channels[] = {
-	/* Sensing the H1's voltage at the DUT side.  Converted to mV. */
-	[ADC_H1_SPI_VREF] = {
-		.name = "H1_VREF",
-		.factor_mul = 3300,
-		.factor_div = 4096,
-		.shift = 0,
-		.channel = STM32_AIN(3),
-	},
-	/* Sensing the EC's voltage at the DUT side.  Converted to mV. */
-	[ADC_EC_SPI_VREF] = {
-		.name = "EC_VREF",
-		.factor_mul = 3300,
-		.factor_div = 4096,
-		.shift = 0,
-		.channel = STM32_AIN(4),
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]			= usb_string_desc,
-	[USB_STR_VENDOR]		= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]		= USB_STRING_DESC("C2D2"),
-	[USB_STR_SERIALNO]		= 0,
-	[USB_STR_VERSION]		= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_USART4_STREAM_NAME]	= USB_STRING_DESC("CR50"),
-	[USB_STR_UPDATE_NAME]		= USB_STRING_DESC("Firmware update"),
-	[USB_STR_CONSOLE_NAME]		= USB_STRING_DESC("C2D2 Shell"),
-	[USB_STR_I2C_NAME]		= USB_STRING_DESC("I2C"),
-	[USB_STR_USART3_STREAM_NAME]	= USB_STRING_DESC("CPU"),
-	[USB_STR_USART1_STREAM_NAME]	= USB_STRING_DESC("EC"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ec",
-		.port = I2C_PORT_EC,
-		.kbps = 100,
-		.scl = GPIO_UART_DBG_TX_EC_RX_SCL,
-		.sda =  GPIO_UART_EC_TX_DBG_RX_SDA,
-		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
-	},
-	{
-		.name = "aux",
-		.port = I2C_PORT_AUX,
-		.kbps = 100,
-		.scl = GPIO_UART_DBG_TX_AP_RX_INA_SCL,
-		.sda =  GPIO_UART_AP_TX_DBG_RX_INA_SDA,
-		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Configure ITE flash support module */
-const struct ite_dfu_config_t ite_dfu_config = {
-	.i2c_port = I2C_PORT_EC,
-	/* PB6/7 are connected to complement outputs of TIM16/17 */
-	.use_complement_timer_channel = true,
-	.access_allow = &is_ec_i2c_enabled,
-	.scl = GPIO_UART_DBG_TX_EC_RX_SCL,
-	.sda = GPIO_UART_EC_TX_DBG_RX_SDA,
-};
-
-/*
- * I2C is always enabled, but the i2c pins may not be muxed to DUT. We will
- * let the i2c transactions fail instead of using the USB endpoint disable
- * status.
- */
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-/******************************************************************************
- * Forward UARTs as a USB serial interface.
- */
-
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
-
-/******************************************************************************
- * Forward USART1 (EC) as a simple USB serial interface.
- */
-
-static struct usart_config const usart1;
-struct usb_stream_config const usart1_usb;
-
-static struct queue const usart1_to_usb = QUEUE_DIRECT(128, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
-
-static struct usart_rx_dma const usart1_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH5, 32);
-
-static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart1_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG_USART_IFACE(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb,
-	usart1)
-
-
-/******************************************************************************
- * Forward USART3 (CPU) as a simple USB serial interface.
- */
-
-static struct usart_config const usart3;
-struct usb_stream_config const usart3_usb;
-
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
-
-static struct usart_rx_dma const usart3_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH3, 32);
-
-static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
-
-
-/******************************************************************************
- * Forward USART4 (cr50) as a simple USB serial interface.
- *
- * We do not try to share DMA channel 6 with SPI2, so just use interrupts
- */
-
-static struct usart_config const usart4;
-struct usb_stream_config const usart4_usb;
-
-static struct queue const usart4_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
-
-static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
-
-/******************************************************************************
- * Set up SPI over USB
- * Notes DMA Channel 6 is shared and mutually exclusive with USART4 RX
- */
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-void usb_spi_board_enable(struct usb_spi_config const *config)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-
-	/* Set all four SPI pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-void usb_spi_board_disable(struct usb_spi_config const *config)
-{
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Reset all four SPI pins to low speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) &= ~0xff000000;
-}
-
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI,
-	       USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE);
-
-/******************************************************************************
- * Check parity setting on usarts.
- */
-static int command_uart_parity(int argc, char **argv)
-{
-	int parity = 0, newparity;
-	struct usart_config const *usart;
-	char *e;
-
-	if ((argc < 2) || (argc > 3))
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart1"))
-		usart = &usart1;
-	else if (!strcasecmp(argv[1], "usart3"))
-		usart = &usart3;
-	else if (!strcasecmp(argv[1], "usart4"))
-		usart = &usart4;
-	else
-		return EC_ERROR_PARAM1;
-
-	if (argc == 3) {
-		parity = strtoi(argv[2], &e, 0);
-		if (*e || (parity < 0) || (parity > 2))
-			return EC_ERROR_PARAM2;
-
-		usart_set_parity(usart, parity);
-	}
-
-	newparity = usart_get_parity(usart);
-	ccprintf("Parity on %s is %d.\n", argv[1], newparity);
-
-	if ((argc == 3) && (newparity != parity))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
-			"Set parity on uart");
-
-/******************************************************************************
- * Set baud rate setting on usarts.
- */
-static int command_uart_baud(int argc, char **argv)
-{
-	int baud = 0;
-	struct usart_config const *usart;
-	char *e;
-
-	if ((argc < 2) || (argc > 3))
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart1"))
-		usart = &usart1;
-	else if (!strcasecmp(argv[1], "usart3"))
-		usart = &usart3;
-	else if (!strcasecmp(argv[1], "usart4"))
-		usart = &usart4;
-	else
-		return EC_ERROR_PARAM1;
-
-	baud = strtoi(argv[2], &e, 0);
-	if (*e || baud < 0)
-		return EC_ERROR_PARAM2;
-
-	usart_set_baud(usart, baud);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
-			"Set baud rate on uart");
-
-/******************************************************************************
- * Hold the usart pins low while disabling it, or return it to normal.
- */
-static int command_hold_usart_low(int argc, char **argv)
-{
-	enum bus_lock *bus;
-	enum gpio_signal rx;
-
-	if (argc > 3 || argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart1")) {
-		bus = &ec_pins;
-		rx = GPIO_UART_EC_TX_DBG_RX_SDA;
-	} else if (!strcasecmp(argv[1], "usart3")) {
-		bus = &ap_pins;
-		rx = GPIO_UART_AP_TX_DBG_RX_INA_SDA;
-	} else if (!strcasecmp(argv[1], "usart4")) {
-		bus = &h1_pins;
-		rx = GPIO_UART_H1_TX_DBG_RX;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	/* Updating the status of this port */
-	if (argc == 3) {
-		char *e;
-		const int hold_low = strtoi(argv[2], &e, 0);
-
-		if (*e || (hold_low < 0) || (hold_low > 1))
-			return EC_ERROR_PARAM2;
-
-		mutex_lock(&vref_bus_state_mutex);
-
-		if (hold_low && *bus != BUS_UART_HELD) {
-			/* Ensure no other use of these pins */
-			if (*bus != BUS_UNLOCKED) {
-				ccprintf("Cannot hold low! Pins busy: %s.\n",
-					 lock_to_string(*bus));
-				goto busy_error_unlock;
-			}
-
-			/*
-			 * No need to shutdown UART, just de-mux the RX pin from
-			 * UART and change it to a GPIO temporarily
-			 */
-			gpio_config_pin(MODULE_USART, rx, 0);
-			gpio_set_flags(rx, GPIO_OUT_LOW);
-
-			/* Update global uart state */
-			*bus = BUS_UART_HELD;
-		} else if (!hold_low && *bus == BUS_UART_HELD) {
-			/*
-			 * Mux the RX pin back to GPIO mode
-			 */
-			gpio_config_pin(MODULE_USART, rx, 1);
-
-			/* Update global uart state */
-			*bus = BUS_UNLOCKED;
-		}
-
-		mutex_unlock(&vref_bus_state_mutex);
-	}
-
-	/* Print status for get and set case. */
-	ccprintf("USART status: %s\n",
-			*bus == BUS_UART_HELD ? "held low" : "normal");
-
-	return EC_SUCCESS;
-
-busy_error_unlock:
-	mutex_unlock(&vref_bus_state_mutex);
-	return EC_ERROR_BUSY;
-}
-DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
-			"usart[1|3|4] [0|1]?",
-			"Get/set the hold-low state for usart port");
-
-
-/******************************************************************************
- * Console commands SPI programming
- */
-enum vref {
-	OFF = 0,
-	PP1800 = 1800,
-	PP3300 = 3300,
-};
-
-static int command_enable_spi(int argc, char **argv)
-{
-	static enum vref current_spi_vref_state;
-
-	if (argc > 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Updating the state */
-	if (argc == 2) {
-		int i;
-		char *e;
-		const enum vref spi_vref = strtoi(argv[1], &e, 0);
-		const enum gpio_signal uart_pins[] = {
-			GPIO_UART_DBG_TX_H1_RX,
-			GPIO_UART_H1_TX_DBG_RX,
-			GPIO_UART_DBG_TX_EC_RX_SCL,
-			GPIO_UART_EC_TX_DBG_RX_SDA,
-		};
-
-		if (*e)
-			return EC_ERROR_PARAM1;
-		if (spi_vref != OFF && spi_vref != PP1800 && spi_vref != PP3300)
-			return EC_ERROR_PARAM1;
-
-		mutex_lock(&vref_bus_state_mutex);
-
-		if (vref_monitor_disable & ~VREF_MON_DIS_SPI_MODE) {
-			ccprintf("Cannot update SPI with reset held.\n");
-			goto busy_error_unlock;
-		}
-
-		if (current_spi_vref_state == spi_vref) {
-			/* No change, do nothing */
-		} else if (spi_vref == OFF) {
-			/* We are transitioning from SPI to UART mode: */
-			/* Disable level shifter pass through */
-			gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, 0);
-			gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 0);
-
-			/* Disable SPI. Sets SPI pins to inputs. */
-			usb_spi_enable(&usb_spi, 0);
-
-			/* Set default state for chip select */
-			gpio_set_flags(GPIO_SPI_CSN, GPIO_INPUT);
-
-			/* Re-enable all UARTs pins we used. */
-			for (i = 0; i < ARRAY_SIZE(uart_pins); ++i)
-				gpio_config_pin(MODULE_USART, uart_pins[i], 1);
-
-			/* Ensure DUT's muxes are switched to UART mode */
-			gpio_set_level(GPIO_C2D2_MUX_UART_ODL, 0);
-
-			/* Update state and defer Vrefs update  */
-			h1_pins = BUS_UNLOCKED;
-			ec_pins = BUS_UNLOCKED;
-			vref_monitor_disable &= ~VREF_MON_DIS_SPI_MODE;
-			hook_call_deferred(&update_vrefs_and_shifters_data, 0);
-		} else if (vref_monitor_disable & VREF_MON_DIS_SPI_MODE) {
-			/* We are just changing voltages */
-			gpio_set_level(GPIO_SEL_SPIVREF_H1VREF_3V3,
-				       spi_vref == PP3300);
-			gpio_set_level(GPIO_SEL_SPIVREF_ECVREF_3V3,
-				       spi_vref == PP3300);
-		} else {
-			/* Ensure no other use of these pins */
-			if (h1_pins != BUS_UNLOCKED ||
-			    ec_pins != BUS_UNLOCKED) {
-				ccprintf(
-					"Cannot enter SPI! H1 pins: %s; EC pins: %s.\n",
-					lock_to_string(h1_pins),
-					lock_to_string(ec_pins));
-				goto busy_error_unlock;
-			}
-
-			/* We are transitioning from UART to SPI mode: */
-			/* Turn off comparator interrupt for Vref detection */
-			STM32_EXTI_IMR &= ~EXTI_COMP2_EVENT;
-
-			/* Disable level shifters to avoid glitching output */
-			gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, 0);
-			gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 0);
-
-			/*
-			 * De-select UART on all UARTs pins we are using to
-			 * avoid drive fights with SPI pins.
-			 */
-			for (i = 0; i < ARRAY_SIZE(uart_pins); ++i)
-				gpio_config_pin(MODULE_USART, uart_pins[i], 0);
-
-			/* Set default state for chip select */
-			gpio_set_flags(GPIO_SPI_CSN, GPIO_OUT_HIGH);
-
-			/* Enable SPI. Sets SPI pins to SPI alternate mode. */
-			usb_spi_enable(&usb_spi, 1);
-
-			/* Set requested Vref voltage */
-			gpio_set_level(GPIO_SEL_SPIVREF_H1VREF_3V3,
-				       spi_vref == PP3300);
-			gpio_set_level(GPIO_SEL_SPIVREF_ECVREF_3V3,
-				       spi_vref == PP3300);
-
-			/* Ensure DUT's muxes are switched to SPI mode */
-			gpio_set_level(GPIO_C2D2_MUX_UART_ODL, 1);
-
-			/* Enable level shifters passthrough */
-			gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, 1);
-			gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 1);
-
-			h1_pins = BUS_SPI;
-			ec_pins = BUS_SPI;
-			vref_monitor_disable |= VREF_MON_DIS_SPI_MODE;
-		}
-
-		current_spi_vref_state = spi_vref;
-
-		mutex_unlock(&vref_bus_state_mutex);
-	}
-
-	/* Print status for get and set case. */
-	ccprintf("SPI Vref: %d\n", current_spi_vref_state);
-
-	return EC_SUCCESS;
-
-busy_error_unlock:
-	mutex_unlock(&vref_bus_state_mutex);
-	return EC_ERROR_BUSY;
-}
-DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi,
-			"[0|1800|3300]?",
-			"Get/set the SPI Vref");
-
-/******************************************************************************
- * Console commands I2c programming mode
- */
-static bool is_ec_i2c_enabled(void)
-{
-	return ec_pins == BUS_I2C;
-}
-
-static inline enum i2c_freq to_i2c_freq(int kbps)
-{
-	switch (kbps) {
-	case 400:
-		return I2C_FREQ_400KHZ;
-	case 1000:
-		return I2C_FREQ_1000KHZ;
-	default:
-		return I2C_FREQ_100KHZ;
-	}
-}
-
-static inline int to_kbps(enum i2c_freq freq)
-{
-	switch (freq) {
-	case I2C_FREQ_400KHZ:
-		return 400;
-	case I2C_FREQ_1000KHZ:
-		return 1000;
-	default:
-		return 100;
-	}
-}
-
-static int command_enable_i2c(int argc, char **argv)
-{
-	int i2c_index;
-	enum bus_lock *bus;
-	enum gpio_signal sda, scl;
-
-	if (argc > 3 || argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "ec")) {
-		bus = &ec_pins;
-		i2c_index = I2C_PORT_EC;
-		sda = GPIO_UART_EC_TX_DBG_RX_SDA;
-		scl = GPIO_UART_DBG_TX_EC_RX_SCL;
-
-	} else if (!strcasecmp(argv[1], "ap")) {
-		bus = &ap_pins;
-		i2c_index = I2C_PORT_AUX;
-		sda = GPIO_UART_AP_TX_DBG_RX_INA_SDA;
-		scl = GPIO_UART_DBG_TX_AP_RX_INA_SCL;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	/* Updating the state */
-	if (argc == 3) {
-		char *e;
-		const int speed = strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (speed != 0 && speed != 100 && speed != 400 && speed != 1000)
-			return EC_ERROR_PARAM2;
-
-		mutex_lock(&vref_bus_state_mutex);
-
-		if (speed != 0 && *bus != BUS_I2C) {
-			/* Ensure no other use of these pins */
-			if (*bus != BUS_UNLOCKED) {
-				ccprintf("Cannot enable i2c! Pin busy: %s.\n",
-					 lock_to_string(*bus));
-				goto busy_error_unlock;
-			}
-
-			/* Change alternate mode to I2C */
-			gpio_config_pin(MODULE_I2C, sda, 1);
-			gpio_config_pin(MODULE_I2C, scl, 1);
-
-			/* Update state */
-			*bus = BUS_I2C;
-		} else if (speed == 0 && *bus == BUS_I2C) {
-			/* Update back to default UART mode */
-			gpio_config_pin(MODULE_USART, sda, 1);
-			gpio_config_pin(MODULE_USART, scl, 1);
-
-			/* Update state */
-			*bus = BUS_UNLOCKED;
-		}
-
-		mutex_unlock(&vref_bus_state_mutex);
-
-		/* If we have a non-zero speed, then set frequency */
-		if (speed)
-			i2c_set_freq(i2c_index, to_i2c_freq(speed));
-	}
-
-	/* Print status for get and set case. */
-	ccprintf("I2C speed kbps: %d\n",
-		 *bus == BUS_I2C ? to_kbps(i2c_get_freq(i2c_index)) : 0);
-
-	return EC_SUCCESS;
-
-busy_error_unlock:
-	mutex_unlock(&vref_bus_state_mutex);
-	return EC_ERROR_BUSY;
-}
-DECLARE_CONSOLE_COMMAND(enable_i2c, command_enable_i2c,
-			"[ec|ap] [0|100|400|1000]?",
-			"Get/set the I2C speed in kbps for EC and AP pins");
-
-/******************************************************************************
- * Console commands for asserting H1 reset and EC Power button
- */
-
-static int command_vref_alternate(int argc, char **argv,
-				  const enum gpio_signal vref_signal,
-				  const enum gpio_signal en_signal,
-				  const int state_flag,
-				  const char *const print_name)
-{
-	if (argc > 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Updating the state */
-	if (argc == 2) {
-		char *e;
-		const int hold_low = strtoi(argv[1], &e, 0);
-
-		if (*e || (hold_low < 0) || (hold_low > 1))
-			return EC_ERROR_PARAM1;
-
-		mutex_lock(&vref_bus_state_mutex);
-
-		if (vref_monitor_disable & VREF_MON_DIS_SPI_MODE) {
-			ccprintf("Cannot hold pin while in SPI mode.\n");
-			goto busy_error_unlock;
-		}
-
-		if (!!(vref_monitor_disable & state_flag) == hold_low) {
-			/* No change, do nothing */
-		} else if (hold_low) {
-			/* Turn off comparator interrupt for vref detection */
-			STM32_EXTI_IMR &= ~EXTI_COMP2_EVENT;
-			/* Start holding the ODL signal line low */
-			gpio_set_flags(vref_signal, GPIO_OUT_LOW);
-			/* Ensure the switch is connecting STM to DUT */
-			gpio_set_level(en_signal, 1);
-			vref_monitor_disable |= state_flag;
-		} else {
-			/* Return GPIO back to input for vref detection */
-			gpio_set_flags(vref_signal, GPIO_INPUT);
-			/* Transitioning out of hold, correct vrefs */
-			hook_call_deferred(&update_vrefs_and_shifters_data, 0);
-			vref_monitor_disable &= ~state_flag;
-		}
-
-		mutex_unlock(&vref_bus_state_mutex);
-	}
-
-	/* Print status for both get and set case */
-	ccprintf("%s held: %s\n", print_name,
-		 vref_monitor_disable & state_flag ? "yes" : "no");
-
-
-	return EC_SUCCESS;
-
-busy_error_unlock:
-	mutex_unlock(&vref_bus_state_mutex);
-	return EC_ERROR_BUSY;
-}
-
-static int command_pwr_button(int argc, char **argv)
-{
-	return command_vref_alternate(argc, argv,
-				      GPIO_SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL,
-				      GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN,
-				      VREF_MON_DIS_EC_PWR_HELD, "Power button");
-}
-DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button,
-			"[0|1]?",
-			"Get/set the power button state");
-
-static int command_h1_reset(int argc, char **argv)
-{
-	return command_vref_alternate(argc, argv,
-				      GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
-				      GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
-				      VREF_MON_DIS_H1_RST_HELD, "H1 reset");
-}
-DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset,
-			"[0|1]?",
-			"Get/set the h1 reset state");
-
-
-/******************************************************************************
- * Vref detection logic
- */
-
-/* Set by update and read by console command that polls for Vref presence */
-static enum vref h1_vref;
-static enum vref ec_vref;
-
-static int command_h1_vref_present(int argc, char **argv)
-{
-	ccprintf("H1 Vref: %s\n", h1_vref ? "on" : "off");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present,
-			"",
-			"Get if the h1 vref is present");
-
-/* Voltage thresholds for rail detection */
-#define VREF_3300_MIN_MV 2300
-#define VREF_1800_MIN_MV 1500
-
-static enum vref get_vref(enum adc_channel chan)
-{
-	const int adc = adc_read_channel(chan);
-
-	if (adc == ADC_READ_ERROR)
-		return OFF;
-	else if (adc > VREF_3300_MIN_MV)
-		return PP3300;
-	else if (adc > VREF_1800_MIN_MV)
-		return PP1800;
-	else
-		return OFF;
-}
-
-static inline void drain_vref_lines(void)
-{
-	mutex_lock(&vref_bus_state_mutex);
-	if (vref_monitor_disable) {
-		mutex_unlock(&vref_bus_state_mutex);
-		return;
-	}
-
-	/*
-	 * Disconnect level shifters to prevent any leakage on DUT side while we
-	 * are draining Vref lines for a proper read.
-	 */
-	gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, 0);
-	gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 0);
-
-	/* Disconnect Vref switches */
-	gpio_set_level(GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, 0);
-	gpio_set_level(GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN, 0);
-
-	/* Actively pull down floating voltage */
-	gpio_set_flags(GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL, GPIO_OUT_LOW);
-	gpio_set_flags(GPIO_SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL, GPIO_OUT_LOW);
-
-	/* Ensure we have enough time to drain line. Not in mutex */
-	mutex_unlock(&vref_bus_state_mutex);
-	msleep(5);
-	mutex_lock(&vref_bus_state_mutex);
-	if (vref_monitor_disable) {
-		mutex_unlock(&vref_bus_state_mutex);
-		/*
-		 * One or both of the Vref signals will still be low. This is
-		 * okay since anyone that just took over these signal will
-		 * also take over the enabled switch signals appropriately.
-		 *
-		 * If no one takes over the Vref signal, then the switch will
-		 * remain off and we won't pull down the DUT side.
-		 */
-		return;
-	}
-
-	/* Reset Vref GPIOs back to input for Vref detection */
-	gpio_set_flags(GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL, GPIO_INPUT);
-	gpio_set_flags(GPIO_SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL, GPIO_INPUT);
-
-	/* Reconnect Vref switches */
-	gpio_set_level(GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, 1);
-	gpio_set_level(GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN, 1);
-
-	mutex_unlock(&vref_bus_state_mutex);
-	/* Ensure we have enough time to charge line up to real voltage */
-	msleep(10);
-}
-
-/* This if forward declared as a deferred function above */
-static void update_vrefs_and_shifters(void)
-{
-	static enum vref prev_h1_vref, prev_ec_vref;
-
-	int adc_mv;
-
-	/* Disable Vref comparator interrupt before draining and measuring */
-	STM32_EXTI_IMR &= ~EXTI_COMP2_EVENT;
-
-	drain_vref_lines();
-
-	/* Ensure we aren't actively using Vref lines for other purposes */
-	mutex_lock(&vref_bus_state_mutex);
-	if (vref_monitor_disable) {
-		mutex_unlock(&vref_bus_state_mutex);
-		return;
-	}
-
-	/* Only get the EC Vref if H1 Vref is on */
-	h1_vref = get_vref(ADC_H1_SPI_VREF);
-	ec_vref = (h1_vref == OFF) ? OFF : get_vref(ADC_EC_SPI_VREF);
-
-	/*
-	 * It is possible that the user is physically holding the power button
-	 * while inserting the c2d2 connector on the DUT. In that case the
-	 * EC Vref (shared with power button ODL) will be OFF while H1 Vref is
-	 * on. We won't get a valid read on the EC Vref, so we just keep trying
-	 * to read in the background until we get out of that state.
-	 */
-	if (h1_vref != OFF && ec_vref == OFF) {
-		CPRINTS("Looks like DUT power button is held. Will try again.");
-		hook_call_deferred(&update_vrefs_and_shifters_data, 100 * MSEC);
-	}
-
-	/* Update C2D2 Vref and level shifters based on ADC Vref values */
-	gpio_set_level(GPIO_SEL_SPIVREF_H1VREF_3V3, h1_vref == PP3300);
-	gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, h1_vref != OFF);
-	gpio_set_level(GPIO_SEL_SPIVREF_ECVREF_3V3, ec_vref == PP3300);
-	gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, ec_vref != OFF);
-
-	/* Set up DAC2 for comparison on H1 Vref */
-	adc_mv = (h1_vref == PP3300) ? VREF_3300_MIN_MV : VREF_1800_MIN_MV;
-	/* 8-bit DAC based off of 3.3V rail */
-	STM32_DAC_DHR8R2 = 256 * adc_mv / 3300;
-
-	/* Clear any pending interrupts and enabled H1 Vref comparator */
-	STM32_EXTI_PR = EXTI_COMP2_EVENT;
-	STM32_EXTI_IMR |= EXTI_COMP2_EVENT;
-
-	mutex_unlock(&vref_bus_state_mutex);
-
-	if (prev_h1_vref != h1_vref || prev_ec_vref != ec_vref)
-		CPRINTS("Vref updated. H1: %d -> %d; EC: %d -> %d",
-			prev_h1_vref, h1_vref, prev_ec_vref, ec_vref);
-
-	/*
-	 * Transitioning from 3.3V to 1.8V should not happen and most likely
-	 * indicates a leakage path on the DUT being backpowered from C2D2 or
-	 * something else.
-	 */
-	if (prev_h1_vref == PP3300 && h1_vref == PP1800)
-		CPRINTS("Check for H1 Leakage!!!");
-	if (prev_ec_vref == PP3300 && ec_vref == PP1800)
-		CPRINTS("Check for EC Leakage!!!");
-	prev_h1_vref = h1_vref;
-	prev_ec_vref = ec_vref;
-}
-
-void set_up_comparator(void)
-{
-	/* Overwrite any previous values. This is the only comparator usage */
-	STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI |
-			 STM32_COMP_CMP2OUTSEL_NONE |
-			 STM32_COMP_CMP2INSEL_INM5 | /* Watch DAC_OUT2 (PA5) */
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2EN;
-
-	/* Set Falling and Rising interrupts for COMP2 */
-	STM32_EXTI_FTSR |= EXTI_COMP2_EVENT;
-	STM32_EXTI_RTSR |= EXTI_COMP2_EVENT;
-
-	/* Interrupt for COMP2 enabled when setting Vrefs */
-
-	/* Ensure IRQ will get called when comp module enables interrupt */
-	task_enable_irq(STM32_IRQ_COMP);
-}
-
-static void h1_vref_change(void)
-{
-	/* Ack the interrupt */
-	STM32_EXTI_PR = EXTI_COMP2_EVENT;
-
-	/* Disable interrupt, setting Vref will enable again */
-	STM32_EXTI_IMR &= ~EXTI_COMP2_EVENT;
-
-	hook_call_deferred(&update_vrefs_and_shifters_data, 0);
-}
-DECLARE_IRQ(STM32_IRQ_COMP, h1_vref_change, 1);
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	/* USB to serial queues */
-	queue_init(&usart1_to_usb);
-	queue_init(&usb_to_usart1);
-	queue_init(&usart3_to_usb);
-	queue_init(&usb_to_usart3);
-	queue_init(&usart4_to_usb);
-	queue_init(&usb_to_usart4);
-
-	/* UART init */
-	usart_init(&usart1);
-	usart_init(&usart3);
-	usart_init(&usart4);
-
-	/* Enabled DAC, when setting Vref, this voltage is adjusted */
-	STM32_DAC_CR = STM32_DAC_CR_EN2;
-
-	/* Set Vrefs and enabled level shifters */
-	set_up_comparator();
-
-	/*
-	 * Ensure we set up vrefs at least once. Don't call here because
-	 * there are delays in the reads
-	 */
-	hook_call_deferred(&update_vrefs_and_shifters_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************
- * Turn down USART before jumping to RW.
- */
-static void board_jump(void)
-{
-	/* Put the board into safer state while jumping */
-	gpio_set_level(GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, 0);
-	gpio_set_level(GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN, 0);
-	gpio_set_level(GPIO_EN_CLK_CSN_EC_UART, 0);
-	gpio_set_level(GPIO_EN_MISO_MOSI_H1_UART, 0);
-
-	/*
-	 * Shutdown all UARTS before jumping to RW. They will be reinitialized
-	 * after the jump is successful.
-	 */
-	usart_shutdown(&usart1);
-	usart_shutdown(&usart3);
-	usart_shutdown(&usart4);
-
-	/* Ensure SPI2 is disabled as well */
-	usb_spi_enable(&usb_spi, 0);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, board_jump, HOOK_PRIO_DEFAULT);
diff --git a/board/c2d2/board.h b/board/c2d2/board.h
deleted file mode 100644
index a8095ece4d..0000000000
--- a/board/c2d2/board.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* C2D2 configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-#define CONFIG_BOARD_PRE_INIT
-
-/* Enable USART */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1	/* EC USART */
-#define CONFIG_STREAM_USART3	/* AP USART - not connected by default */
-#define CONFIG_STREAM_USART4	/* H1 USART */
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* The UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_PID 0x5041
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-#define CONFIG_USB_UPDATE
-
-
-/* USB interface indexes (use define rather than enum to expand them)
- *
- * Note these values are used in servo_interface.py for the 'interface' value
- */
-#define USB_IFACE_USART4_STREAM	0	/* H1 */
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5	/* AP (not connected by default) */
-#define USB_IFACE_USART1_STREAM	6	/* EC */
-#define USB_IFACE_COUNT		7
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART1_STREAM	7
-#define USB_EP_COUNT		8
-
-/* Enable control of SPI over USB */
-#define CONFIG_USB_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT 0  /* SPI2 is 0th in stm's SPI_REGS var */
-
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_EC 0
-#define I2C_PORT_AUX 1
-
-/* See i2c_ite_flash_support.c for more information about these values */
-#define CONFIG_ITE_FLASH_SUPPORT
-#define CONFIG_I2C_XFER_LARGE_TRANSFER
-#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
-#undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
-
-/*
- * Set all ADC samples to take 239.5 clock cycles. This allows us to measure
- * weakly driven signals like the H1 Vref.
- */
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_239_5_CY
-
-/* Options features */
-#define CONFIG_ADC
-/*
- * See 'Programmable voltage detector characteristics' in the STM32F072x8
- * Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of
- * min:2.09V, max:2.27V.
- */
-#define CONFIG_PVD
-#define PVD_THRESHOLD 1
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_USART4_STREAM_NAME,
-	USB_STR_UPDATE_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_I2C_NAME,
-	USB_STR_USART3_STREAM_NAME,
-	USB_STR_USART1_STREAM_NAME,
-	USB_STR_COUNT
-};
-
-enum adc_channel {
-	ADC_H1_SPI_VREF, /* Either H1 Vref or SPI Vref depending on mode */
-	ADC_EC_SPI_VREF, /* Either EC Vref or SPI Vref depending on mode */
-	ADC_CH_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/c2d2/build.mk b/board/c2d2/build.mk
deleted file mode 100644
index 559b6b8e95..0000000000
--- a/board/c2d2/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072CBU6TR
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/c2d2/ec.tasklist b/board/c2d2/ec.tasklist
deleted file mode 100644
index c1fb169118..0000000000
--- a/board/c2d2/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/c2d2/gpio.inc b/board/c2d2/gpio.inc
deleted file mode 100644
index 485a603453..0000000000
--- a/board/c2d2/gpio.inc
+++ /dev/null
@@ -1,56 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-GPIO(UART_DBG_TX_H1_RX,		                PIN(A, 0), GPIO_INPUT)
-GPIO(UART_H1_TX_DBG_RX,		                PIN(A, 1), GPIO_INPUT)
-GPIO(EN_MISO_MOSI_H1_UART,		        PIN(A, 2), GPIO_OUT_LOW)
-GPIO(SPIVREF_RSVD_H1VREF_H1_RST_ODL,		PIN(A, 3), GPIO_INPUT)
-GPIO(SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL,	PIN(A, 4), GPIO_INPUT)
-GPIO(EN_CLK_CSN_EC_UART,	                PIN(A, 7), GPIO_OUT_LOW)
-
-GPIO(EN_SPIVREF_RSVD_H1VREF_H1_RST,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN,		PIN(B, 3), GPIO_OUT_LOW)
-GPIO(SEL_SPIVREF_H1VREF_3V3,		        PIN(B, 4), GPIO_OUT_LOW)
-GPIO(SEL_SPIVREF_ECVREF_3V3,		        PIN(B, 5), GPIO_OUT_LOW)
-GPIO(UART_DBG_TX_EC_RX_SCL,	                PIN(B, 6), GPIO_INPUT)
-GPIO(UART_EC_TX_DBG_RX_SDA,	                PIN(B, 7), GPIO_INPUT)
-/* Start C2D2 in UART mode */
-GPIO(C2D2_MUX_UART_ODL,	                        PIN(B, 8), GPIO_ODR_LOW)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(UART_DBG_TX_AP_RX_INA_SCL,	                PIN(B, 10), GPIO_INPUT)
-GPIO(UART_AP_TX_DBG_RX_INA_SDA,	                PIN(B, 11), GPIO_INPUT)
-
-/* Flash SPI interface */
-GPIO(SPI_CSN,			                PIN(B, 12), GPIO_INPUT)
-GPIO(SPI_CLK,			                PIN(B, 13), GPIO_INPUT)
-GPIO(SPI_MISO,			                PIN(B, 14), GPIO_INPUT)
-GPIO(SPI_MOSI,			                PIN(B, 15), GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-/* Default alternate mode pins */
-ALTERNATE(PIN_MASK(A, GENMASK(15, 14)), 1, MODULE_UART, 0)  /* USART2: PA14/PA15 - Servo stm32 console UART*/
-
-/* TIM16_OCN/TIM17_OCN: PB6/PB7 - Timer bit-banging for EC I2C lines */
-ALTERNATE(PIN_MASK(B, GENMASK( 7,  6)), 2, MODULE_I2C_TIMERS, 0)
-
-ALTERNATE(PIN_MASK(B, GENMASK( 7,  6)), 1, MODULE_I2C, 0)   /* I2C1: PB6/PB7 - I2C1: SCL/SDA (EC) */
-ALTERNATE(PIN_MASK(B, GENMASK(11, 10)), 1, MODULE_I2C, 0)   /* I2C2: PB10/PB11 - I2C2: SCL/SDA (AP) */
-
-ALTERNATE(PIN_MASK(B, GENMASK( 7,  6)), 0, MODULE_USART, 0) /* USART1: PB6/PB7 - Servo UART1 (EC) */
-ALTERNATE(PIN_MASK(B, GENMASK(11, 10)), 4, MODULE_USART, 0) /* USART3: PB10/PB11 - Servo UART2 (AP) */
-ALTERNATE(PIN_MASK(A, GENMASK( 1,  0)), 4, MODULE_USART, 0) /* USART4: PA0/PA1 - Servo UART3 (H1) */
-
-/*
- * Note BIT(12) is intentionally not marked for alternate mode since it is
- * directly controlled with gpio_set_level and configured in the spi driver.
- */
-ALTERNATE(PIN_MASK(B, GENMASK(15, 13)), 0, MODULE_SPI_FLASH, 0) /* SPI: PB15 - PB12 MOSI, MISO, CLK, CS */
diff --git a/board/cappy2/battery.c b/board/cappy2/battery.c
deleted file mode 100644
index aa81d0b353..0000000000
--- a/board/cappy2/battery.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "common.h"
-#include "util.h"
-
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
-
-/*
- * Battery info for lalala battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SDI Battery Information */
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4402D51",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0xc000,
-				.cfet_off_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 200,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	}
-};
-
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int current;
-	int voltage;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c;
-	const struct battery_info *batt_info;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
-	 * ---+------+--------+--------+------+--- Temperature (C)
-	 *    0      5        12       45     50
-	 */
-	enum {
-		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
-		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
-		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
-		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
-		TEMP_ZONE_COUNT,
-		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
-	} temp_zone;
-
-	/*
-	 * Precharge must be executed when communication is failed on
-	 * dead battery.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-		return 0;
-
-	current = curr->requested_current;
-	voltage = curr->requested_voltage;
-	bat_temp_c = curr->batt.temperature - 2731;
-	batt_info = battery_get_info();
-
-	/*
-	 * If the temperature reading is bad, assume the temperature
-	 * is out of allowable range.
-	 */
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < 0) || (bat_temp_c > 500))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else if (bat_temp_c <= 50)
-		temp_zone = TEMP_ZONE_0;
-	else if (bat_temp_c <= 120)
-		temp_zone = TEMP_ZONE_1;
-	else if (bat_temp_c <= 450)
-		temp_zone = TEMP_ZONE_2;
-	else
-		temp_zone = TEMP_ZONE_3;
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-
-	case TEMP_ZONE_1:
-		voltage += 100;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-
-	case TEMP_ZONE_2:
-		voltage += 100;
-		break;
-
-	case TEMP_ZONE_3:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		break;
-
-	case TEMP_OUT_OF_RANGE:
-		/* Don't charge if outside of allowable temperature range */
-		current = 0;
-		voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		if (curr->state != ST_DISCHARGE)
-			curr->state = ST_IDLE;
-		break;
-	}
-
-	if (voltage > batt_info->voltage_max)
-		voltage = batt_info->voltage_max;
-
-	curr->requested_voltage = voltage;
-	curr->requested_current = MIN(curr->requested_current, current);
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-				uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-				uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
diff --git a/board/cappy2/board.c b/board/cappy2/board.c
deleted file mode 100644
index ba0c4f04e9..0000000000
--- a/board/cappy2/board.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* cappy2 board-specific configuration */
-
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_mux/ps8743_public.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Keyboard scan setting */
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* BC 1.2 chip*/
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* modify AC DC prochot value */
-	isl923x_set_ac_prochot(CHARGER_SOLO, 4096);
-	isl923x_set_dc_prochot(CHARGER_SOLO, 6000);
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/cappy2/board.h b/board/cappy2/board.h
deleted file mode 100644
index be34d2b906..0000000000
--- a/board/cappy2/board.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* cappy2 board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KEEBY_EC_NPCX797FC
-#include "baseboard.h"
-
-#undef	GPIO_VOLUME_UP_L
-#undef	GPIO_VOLUME_DOWN_L
-#undef	CONFIG_VOLUME_BUTTONS
-
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#undef	CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* Keyboard */
-#undef	CONFIG_PWM_KBLIGHT
-
-/* LED defines */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
-
-/* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is used as PWM1. */
-
-/******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* BC1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* MUX */
-#define CONFIG_USB_MUX_PS8743
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_TEMP_SENSOR_3,     /* ADC6 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cappy2/build.mk b/board/cappy2/build.mk
deleted file mode 100644
index b012d8d502..0000000000
--- a/board/cappy2/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=keeby
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/cappy2/cbi_ssfc.c b/board/cappy2/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/cappy2/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/cappy2/cbi_ssfc.h b/board/cappy2/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/cappy2/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cappy2/ec.tasklist b/board/cappy2/ec.tasklist
deleted file mode 100644
index 0025c2985b..0000000000
--- a/board/cappy2/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/cappy2/gpio.inc b/board/cappy2/gpio.inc
deleted file mode 100644
index 00799bfdd8..0000000000
--- a/board/cappy2/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt)
-
-/* Button interrupts */
-GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      	PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      	PIN(8, 7), GPIO_INPUT)
-
-/* Extra Sub-board I/O pins */
-GPIO(LTE_EN, 			PIN(6, 0), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   		PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,		PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,			PIN(D, 3), GPIO_ODR_LOW)
-GPIO(EC_CBI_WP,			PIN(E, 5), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
-GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
-GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     	PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         	PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      	PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           	PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         	PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     	PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     	PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   	PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     	PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     	PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     	PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     	PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     	PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     	PIN(C, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  	PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     	PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     	PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    	PIN(E, 1), GPIO_INPUT)
-GPIO(EN_USB_A0_VBUS,	 	PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-/*
- * cappy2 doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(3, BIT(4)), 0, MODULE_ADC, 0)		/* ADC6 */
-ALTERNATE(PIN_MASK(4, BIT(3)|BIT(4)|BIT(5)), 0, MODULE_ADC, 0)	/* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(4)|BIT(5)), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(2)|BIT(3)), 0, MODULE_I2C, 0)	/* I2C7 */
-ALTERNATE(PIN_MASK(3, BIT(3)|BIT(6)), 0, MODULE_I2C, 0)	/* I2C5 */
-ALTERNATE(PIN_MASK(9, BIT(0)), 0, MODULE_I2C, 0)	/* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)	/* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO50_NC,	PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO56_NC,	PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO63_NC,	PIN(6, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO91_NC,	PIN(9, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO92_NC,	PIN(9, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO95_NC,	PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO97_NC,	PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOB4_NC,	PIN(B, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOB5_NC,	PIN(B, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF2_NC,	PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF3_NC,	PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF5_NC,	PIN(F, 5), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/cappy2/led.c b/board/cappy2/led.c
deleted file mode 100644
index fb6faae482..0000000000
--- a/board/cappy2/led.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for lalala
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* cappy2 : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-			{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	if (color == EC_LED_COLOR_BLUE) {
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	/* Battery leds must be turn off when blue led is on
-	 * because the led is 3-in-1 led.
-	 */
-	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-			!brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L,
-			!brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-			!brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/cappy2/usb_pd_policy.c b/board/cappy2/usb_pd_policy.c
deleted file mode 100644
index fd9018a3f0..0000000000
--- a/board/cappy2/usb_pd_policy.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/cappy2/vif_override.xml b/board/cappy2/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/cappy2/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/careena/analyzestack.yaml b/board/careena/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/careena/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/careena/battery.c b/board/careena/battery.c
deleted file mode 100644
index 7180109168..0000000000
--- a/board/careena/battery.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Careena battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack Coslight Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_bq4050_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_bq4050_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack SDI Battery Information */
-	[BATTERY_DYNAPACK_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-24-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_bq4050_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo Coslight Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo ATL Battery Information */
-	[BATTERY_SIMPLO_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-17-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = &battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-			.imbalance_mv = &battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/careena/board.c b/board/careena/board.c
deleted file mode 100644
index ea2a886c03..0000000000
--- a/board/careena/board.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Careena board-specific configuration */
-
-#include "button.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "thermal.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_WARN] = 0,
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(79),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_WARN] = 0,
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(71),
-			[EC_TEMP_THRESH_HALT] = 0,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static void board_init(void)
-{
-	/*
-	 * Ensure PROCHOT is deasserted after sysjump.
-	 * The GPIO was an input in old RO images. On sysjump to new RW, the
-	 * direction is changed to output but the level is not set, which
-	 * results in the output driving low, which asserts PROCHOT incorrectly.
-	 * (crbug.com/1226694)
-	 */
-	gpio_set_level(GPIO_CPU_PROCHOT, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * We have total 24 pins for keyboard connecter, {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {-1, -1},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {-1, -1},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-
-static int board_is_support_ps8755_tcpc(void)
-{
-	/*
-	 * 0: PS8751
-	 * 1: PS8755
-	 */
-	return gpio_get_level(GPIO_TCPC_ID);
-}
-
-__override uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Careena variant doesn't have ps8xxx product in the port 0 */
-	if (port == 0)
-		return 0;
-
-	if (board_is_support_ps8755_tcpc())
-		return PS8755_PRODUCT_ID;
-
-	return PS8751_PRODUCT_ID;
-}
-#endif
diff --git a/board/careena/board.h b/board/careena/board.h
deleted file mode 100644
index 75545cfcaa..0000000000
--- a/board/careena/board.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Careena board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3429
-#define VARIANT_GRUNT_NO_SENSORS
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-#define CONFIG_MKBP_USE_HOST_EVENT
-
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Thermal */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_BATTERY_MEASURE_IMBALANCE
-#define CONFIG_BATTERY_BQ4050
-
-/* Additional TCPC second source in Port 1 */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-
-#ifndef __ASSEMBLER__
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_SDI,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_ATL,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/careena/build.mk b/board/careena/build.mk
deleted file mode 100644
index c808e65aed..0000000000
--- a/board/careena/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/careena/ec.tasklist b/board/careena/ec.tasklist
deleted file mode 100644
index b562761311..0000000000
--- a/board/careena/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc
deleted file mode 100644
index c84c81a68e..0000000000
--- a/board/careena/gpio.inc
+++ /dev/null
@@ -1,116 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(E, 4), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(TCPC_ID,			PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)		/* TCPC ID pin */
-
-GPIO(BAT_LED_AMBER_L,		PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_L,		PIN(C, 4), GPIO_OUT_HIGH)
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-GPIO(PCH_SLP_S0_L,		PIN(A, 4), GPIO_INPUT)
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(EN_USB_C0_TCPC_PWR,	PIN(6, 0), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST_L,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP)	/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)					/* KB Backlight */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)					/* GPIO00 = AC_PRESENT,
-										   GPIO01 = POWER_BUTTON_L,
-										   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 = LID_OPEN */
diff --git a/board/careena/led.c b/board/careena/led.c
deleted file mode 100644
index 4188290b4f..0000000000
--- a/board/careena/led.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LED control for Careena
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-#include "system.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
-	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x4 ?
-				      LED_WHITE : LED_OFF);
-		return;
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/careena/vif_override.xml b/board/careena/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/careena/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/casta/battery.c b/board/casta/battery.c
deleted file mode 100644
index 0ced18e734..0000000000
--- a/board/casta/battery.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "common.h"
-#include "util.h"
-
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
-
-/*
- * Battery info for all casta battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4402D51",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8650,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 50,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int current;
-	int voltage;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c;
-	const struct battery_info *batt_info;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
-	 * ---+------+--------+--------+------+--- Temperature (C)
-	 *    0      5        12       45     50
-	 */
-	enum {
-		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
-		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
-		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
-		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
-		TEMP_ZONE_COUNT,
-		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
-	} temp_zone;
-
-        /*
-         * Precharge must be executed when communication is failed on
-	 * dead battery.
-         */
-        if(!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-                return 0;
-
-	current = curr->requested_current;
-	voltage = curr->requested_voltage;
-	bat_temp_c = curr->batt.temperature - 2731;
-	batt_info = battery_get_info();
-
-	/*
-	 * If the temperature reading is bad, assume the temperature
-	 * is out of allowable range.
-	 */
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < 0) || (bat_temp_c > 500))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else if (bat_temp_c <= 50)
-		temp_zone = TEMP_ZONE_0;
-	else if (bat_temp_c <= 120)
-		temp_zone = TEMP_ZONE_1;
-	else if (bat_temp_c <= 450)
-		temp_zone = TEMP_ZONE_2;
-	else
-		temp_zone = TEMP_ZONE_3;
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-	case TEMP_ZONE_1:
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-	case TEMP_ZONE_2:
-		break;
-	case TEMP_ZONE_3:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		/* Don't charge if outside of allowable temperature range */
-		current = 0;
-		voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		if (curr->state != ST_DISCHARGE)
-			curr->state = ST_IDLE;
-		break;
-	}
-
-	if(voltage > batt_info->voltage_max)
-		voltage = batt_info->voltage_max;
-
-	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
-	curr->requested_current = MIN(curr->requested_current, current);
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/casta/board.c b/board/casta/board.c
deleted file mode 100644
index 8b36ed0a69..0000000000
--- a/board/casta/board.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Casta board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/charger/bq25710.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static uint8_t sku_id;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* TODO(b/119872005): Casta: confirm thermistor parts */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Charger config.  Start i2c address at isl9238, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-/*
- * I2C callbacks to ensure bus free time for battery I2C transactions is at
- * least 5ms.
- */
-#define BATTERY_FREE_MIN_DELTA_US               (5 * MSEC)
-static timestamp_t battery_last_i2c_time;
-
-static int is_battery_i2c(const int port, const uint16_t slave_addr_flags)
-{
-	return (port == I2C_PORT_BATTERY)
-		&& (slave_addr_flags == BATTERY_ADDR_FLAGS);
-}
-
-static int is_battery_port(int port)
-{
-	return (port == I2C_PORT_BATTERY);
-}
-
-void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
-{
-	unsigned int time_delta_us;
-
-	if (!is_battery_i2c(port, slave_addr_flags))
-		return;
-
-	time_delta_us = time_since32(battery_last_i2c_time);
-	if (time_delta_us >= BATTERY_FREE_MIN_DELTA_US)
-		return;
-
-	usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
-}
-
-void i2c_end_xfer_notify(const int port, const uint16_t slave_addr_flags)
-{
-	/*
-	 * The bus free time needs to be maintained from last transaction
-	 * on I2C bus to any device on it to the next transaction to battery.
-	 */
-	if (!is_battery_port(port))
-		return;
-
-	battery_last_i2c_time = get_time();
-}
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX)
-		return;
-	sku_id = val;
-	CPRINTS("SKU: %d", sku_id);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C);
-
-static void board_init(void)
-{
-	if(get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
-		return;
-
-	chg_chips[0].drv = &bq25710_drv;
-	chg_chips[0].i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS;
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C);
-
-static void set_input_limit_on_ac_removal(void)
-{
-	if (extpower_is_present())
-		return;
-
-	if (get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
-		return;
-
-	charger_set_input_current_limit(0, CONFIG_CHARGER_INPUT_CURRENT);
-
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, set_input_limit_on_ac_removal, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (sku_id == 2)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
diff --git a/board/casta/board.h b/board/casta/board.h
deleted file mode 100644
index 934063c548..0000000000
--- a/board/casta/board.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Casta board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_TCPC_0_PS8751
-#define VARIANT_OCTOPUS_NO_SENSORS
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-#include "baseboard.h"
-
-#define CONFIG_LED_COMMON
-
-/* USB PD */
-#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-/*
- * This board configures two chargers, one of which can measure VBUS and one of
- * which cannot. Leave the default config, which defines
- * CONFIG_USB_PD_VBUS_MEASURE_CHARGER.
- */
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-
-/*
- * Don't allow the system to boot to S0 when the battery is low and unable to
- * communicate on locked systems (which haven't PD negotiated).
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
-
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
-
-/*
- * Allow an additional second during power button init to let PD negotiation
- * complete when we have no battery and need to meet
- * CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON.  SKUs which do not have a TCPC on
- * port 1 will take slightly longer to complete negotiation while the PD1 task
- * attempts to communicate with its TCPC before suspending.
- */
-#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
-
-/* Keyboard Backlight is unconnected in casta proto */
-#undef CONFIG_PWM
-#undef CONFIG_PWM_KBLIGHT
-
-/* All casta systems are clamshells */
-#undef CONFIG_TABLET_MODE
-
-/* TODO(b/119872005): Casta: confirm thermistor parts */
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* Battery W/A */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_I2C_XFER_BOARD_CALLBACK
-
-/* The board needs 100ms for VBUS_C[0|1]_BC12 to drop to lower VvbusUVLO */
-#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
-#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/casta/build.mk b/board/casta/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/casta/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/casta/ec.tasklist b/board/casta/ec.tasklist
deleted file mode 100644
index ac41d643dc..0000000000
--- a/board/casta/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/casta/gpio.inc b/board/casta/gpio.inc
deleted file mode 100644
index e37926b72e..0000000000
--- a/board/casta/gpio.inc
+++ /dev/null
@@ -1,173 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)	/* NC */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)			/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)	/* NC */
-
-GPIO(USB_C0_PD_RST_ODL,	    PIN(8, 3), GPIO_ODR_HIGH)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL,    PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				       GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,     PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL,    PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				       GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_RED_L,		PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(BAT_LED_GREEN_L,		PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(PWR_LED_BLUE_L,		PIN(D, 7), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,			PIN(9, 4), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,       PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,       PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Misc. */
-GPIO(CCD_MODE_ODL,   PIN(E, 3), GPIO_INPUT)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/casta/led.c b/board/casta/led.c
deleted file mode 100644
index 514ec096a5..0000000000
--- a/board/casta/led.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Casta 
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Casta : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-       					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-        }
-
-	if (color == EC_LED_COLOR_BLUE)
-	{
-                gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-        }
-
-	/* Battery leds must be turn off when blue led is on
-	 * because casta has 3-in-1 led.
-	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/casta/vif_override.xml b/board/casta/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/casta/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/cerise/battery.c b/board/cerise/battery.c
deleted file mode 100644
index 50d2bf397c..0000000000
--- a/board/cerise/battery.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/cerise/board.c b/board/cerise/board.c
deleted file mode 100644
index 78ab8f6de8..0000000000
--- a/board/cerise/board.c
+++ /dev/null
@@ -1,474 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = board_set_active_charge_port(port);
-	if (ret)
-		return ret;
-	force_discharge = enable;
-
-	return charger_discharge_on_ac(enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-
-	/* Enable USM mode */
-	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition, 5V DC-DC ctrl  */
-static void board_chipset_resume(void)
-{
-	/* Enable USM mode */
-	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Enable Normal mode */
-	ioex_set_level(IOEX_5V_DC_DC_MODE_CTRL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
diff --git a/board/cerise/board.h b/board/cerise/board.h
deleted file mode 100644
index 5cf8c06f01..0000000000
--- a/board/cerise/board.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-/* TODO(b:135086465) led implementation */
-#undef CONFIG_LED_COMMON
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#define CONFIG_LED_COMMON
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_TYPE_COUNT,
-};
-
-enum BOARD_SKU_ID {
-	BOARD_SKU_ID_UNKNOWN = -1,
-	BOARD_SKU_ID_REV0 = 0,
-	BOARD_SKU_ID_REV1 = 1,
-	BOARD_SKU_ID_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger */
-int board_get_charger_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cerise/build.mk b/board/cerise/build.mk
deleted file mode 100644
index a6e1c010d7..0000000000
--- a/board/cerise/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/cerise/ec.tasklist b/board/cerise/ec.tasklist
deleted file mode 100644
index 36be2e96a4..0000000000
--- a/board/cerise/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, 1024) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/cerise/gpio.inc b/board/cerise/gpio.inc
deleted file mode 100644
index d7d5b9837d..0000000000
--- a/board/cerise/gpio.inc
+++ /dev/null
@@ -1,117 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(5V_DC_DC_MODE_CTRL,   EXPIN(0, 0, 7), GPIO_OUT_LOW)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/cerise/led.c b/board/cerise/led.c
deleted file mode 100644
index 53bec5bf05..0000000000
--- a/board/cerise/led.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Damu
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "hooks.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]         = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]         = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/cerise/vif_override.xml b/board/cerise/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/cerise/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/cherry/battery.c b/board/cherry/battery.c
deleted file mode 100644
index 72daf4966d..0000000000
--- a/board/cherry/battery.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP16L5J Battery Information */
-	[BATTERY_PANASONIC_AC16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	[BATTERY_PANASONIC_AC16L5J_KT00205009] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00205009",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* AP16L8J */
-	[BATTERY_AP16L8J] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0020G010",
-			.device_name = "AP16L8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8700,
-			.voltage_normal         = 7500, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J;
diff --git a/board/cherry/board.c b/board/cherry/board.c
deleted file mode 100644
index 8e456e2c80..0000000000
--- a/board/cherry/board.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Cherry board configuration */
-
-#include "common.h"
-#include "console.h"
-#include "driver/accel_bma422.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/accelgyro_icm_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "motion_sense.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Sensor */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct icm_drv_data_t g_icm42607_data;
-static struct kionix_accel_data g_kx022_data;
-static struct accelgyro_saved_data_t g_bma422_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM42607,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm42607_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_icm42607_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-		.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = ICM42607_ACCEL_MIN_FREQ,
-		.max_frequency = ICM42607_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM42607,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm42607_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_icm42607_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = ICM42607_GYRO_MIN_FREQ,
-		.max_frequency = ICM42607_GYRO_MAX_FREQ,
-	},
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g, enough for laptop. */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			 /* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100,
-			},
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t bma422_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA422,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma4_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_bma422_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = BMA4_ACCEL_MIN_FREQ,
-	.max_frequency = BMA4_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, enough for laptop. */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-static void board_update_motion_sensor_config(void)
-{
-	if (system_get_board_version() >= 2) {
-		motion_sensors[LID_ACCEL] = bma422_lid_accel;
-		ccprints("LID ACCEL is BMA422");
-	} else {
-		ccprints("LID ACCEL is KX022");
-	}
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable motion sensor interrupt */
-	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
-	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
-
-	/* Disable PWM_CH_LED2(Green) for unuse */
-	pwm_enable(PWM_CH_LED2, 0);
-
-	board_update_motion_sensor_config();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/cherry/board.h b/board/cherry/board.h
deleted file mode 100644
index 9db5042085..0000000000
--- a/board/cherry/board.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Cherry board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Chipset config */
-#define CONFIG_BRINGUP
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED
-#define CONFIG_LTO
-
-/*
- * TODO: Remove this option once the VBAT no longer keeps high when
- * system's power isn't presented.
- */
-#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-
-/* BC12 */
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* PD / USB-C / PPC */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-
-/* Optional console commands */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
-
-/* Keyboard */
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_KB_BL
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensor */
-#define CONFIG_GMR_TABLET_MODE
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* ICM426XX Base accel/gyro */
-#define CONFIG_ACCELGYRO_ICM42607
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* KX022 Lid accel */
-#define CONFIG_ACCEL_KX022
-
-/* BMA422 Lid accel */
-#define CONFIG_ACCEL_BMA4XX
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-/* SPI / Host Command */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* USB-A */
-#define USBA_PORT_COUNT 1
-
-/* Temperature */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_PANASONIC_AC16L5J,
-	BATTERY_PANASONIC_AC16L5J_KT00205009,
-	BATTERY_AP16L8J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_TYPE_COUNT,
-};
-
-enum sensor_id {
-	BASE_ACCEL = 0,
-	BASE_GYRO,
-	LID_ACCEL,
-	SENSOR_COUNT,
-};
-
-int board_accel_force_mode_mask(void);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cherry/build.mk b/board/cherry/build.mk
deleted file mode 100644
index 0b0569c6d8..0000000000
--- a/board/cherry/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=cherry
-
-board-y+=led.o battery.o board.o
diff --git a/board/cherry/ec.tasklist b/board/cherry/ec.tasklist
deleted file mode 100644
index f9050fef87..0000000000
--- a/board/cherry/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(DPS, dps_task, NULL, 1280) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, 1024) \
-
diff --git a/board/cherry/gpio.inc b/board/cherry/gpio.inc
deleted file mode 100644
index bf3a3a3210..0000000000
--- a/board/cherry/gpio.inc
+++ /dev/null
@@ -1,160 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
-	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* GSC_EC_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         lid_interrupt)
-GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Chipset interrupts */
-GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_IMU_INT_L,     PIN(M, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         icm42607_interrupt)
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
-#ifdef BOARD_CHERRY
-GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
-#else /* TOMATO */
-GPIO_INT(USB_C0_BC12_INT_ODL,PIN(I, 5), GPIO_INT_FALLING, bc12_interrupt)
-#endif
-GPIO_INT(USB_C1_INT_ODL,     PIN(B, 2), GPIO_INT_FALLING, rt1718s_tcpc_interrupt)
-/* TODO: not used in other devices? */
-GPIO(LID_ACCEL_INT_L,        PIN(M, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V)
-
-/* Volume button interrupts */
-GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-
-/* Other interrupts */
-GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
-GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         switch_interrupt) /* EC_FLASH_WP_OD */
-GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-#ifndef BOARD_CHERRY
-GPIO_INT(AP_XHCI_INIT_DONE,  PIN(J, 5), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         usb_a0_interrupt)
-#endif
-
-/* Power Sequencing Signals */
-GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
-GPIO(PG_MT6315_PROC_B_ODL,   PIN(E, 1), GPIO_INPUT)
-GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
-GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
-GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
-
-/* USB and USBC Signals */
-GPIO(DP_PATH_SEL,            PIN(G, 0), GPIO_OUT_HIGH)
-/* TODO: Turn off in S3 */
-GPIO(DP_DEMUX_EN,            PIN(G, 1), GPIO_OUT_HIGH)
-GPIO(EC_AP_DP_HPD_ODL,       PIN(J, 0), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_USB_A0_VBUS_X,PIN(B, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_DP_IN_HPD,       PIN(H, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_DP_IN_HPD,       PIN(J, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,          PIN(F, 0), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EN_KB_BL,               PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
-GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
-GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
-GPIO(EN_5V_USM,              PIN(G, 3), GPIO_OUT_LOW)
-GPIO(USB_A0_FAULT_ODL,       PIN(J, 6), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SDA */
-GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
-GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
-GPIO(I2C_F_SCL,              PIN(A, 4), GPIO_INPUT) /* Rev 2+ I2C_PROG_SCL */
-GPIO(I2C_F_SDA,              PIN(A, 5), GPIO_INPUT) /* Rev 2+ I2C_PROG_SDA */
-GPIO(I2C_H_SCL,              PIN(H, 1), GPIO_INPUT) /* Rev 0,1 I2C_PROG_SCL */
-GPIO(I2C_H_SDA,              PIN(H, 2), GPIO_INPUT) /* Rev 0,1 I2C_PROG_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, 0b1111), 1, MODULE_PWM, 0) /* PWM 0,1,2,3 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0xCF), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,6,7 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
-
-/* Unimplemented Pins  */
-GPIO(PG_PP5000_S5_OD,        PIN(D, 2), GPIO_INPUT)
-GPIO(EC_GSC_PACKET_MODE,     PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-/* *_ODL pin has external pullup so don't pull it down. */
-GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
-/* reserved for future use */
-GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
-/*
- * ADC pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-#ifdef BOARD_CHERRY
-GPIO(NC_GPI5,                PIN(I, 5), GPIO_OUT_LOW)
-#endif
-/* NC pins, enable internal pull-up/down to avoid floating state. */
-GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-/*
- * These 4 pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
-GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
-GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
-
-/* Other unused pins */
-GPIO(PWM7,                   PIN(A, 7), GPIO_INPUT)
-GPIO(EC_NVME_PLN_ODL,        PIN(D, 7), GPIO_INPUT)
-GPIO(NVME_EC_PLA_S3_ODL,     PIN(I, 7), GPIO_INPUT)
-GPIO(EN_PP2500_NVME_X,       PIN(J, 2), GPIO_INPUT)
-GPIO(EN_PP1200_NVME_X,       PIN(J, 3), GPIO_INPUT)
-GPIO(PG_NVME_OD,             PIN(H, 3), GPIO_INPUT)
-
diff --git a/board/cherry/led.c b/board/cherry/led.c
deleted file mode 100644
index 43c4e45b86..0000000000
--- a/board/cherry/led.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "pwm.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,           3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED1, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED3, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		pwm_enable(PWM_CH_LED1, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED3, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED1, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED3, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else
-		led_set_color_battery(LED_OFF);
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/cherry/vif_override.xml b/board/cherry/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/cherry/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/cherry_scp/board.h b/board/cherry_scp/board.h
deleted file mode 100644
index a698ff2bb3..0000000000
--- a/board/cherry_scp/board.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cherry SCP configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/*
- * RW only, no flash
- * +-------------------- 0x0
- * | ROM vectortable, .text, .rodata, .data LMA
- * +-------------------- 0x58000
- * | RAM .bss, .data
- * +-------------------- 0xbfc00
- * | Reserved (padding for 1k-alignment)
- * +-------------------- 0xbfdb0
- * | IPI shared buffer with AP (288 + 8) * 2
- * +-------------------- 0xc0000
- */
-#define CONFIG_ROM_BASE 0x0
-#define CONFIG_RAM_BASE 0x68000
-#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \
-			 CONFIG_RAM_BASE)
-
-#define SCP_FW_END 0xc0000
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cherry_scp/build.mk b/board/cherry_scp/build.mk
deleted file mode 100644
index 0d6c33755f..0000000000
--- a/board/cherry_scp/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=mt_scp
-CHIP_VARIANT:=mt8195
-BASEBOARD:=mtscp-rv32i
diff --git a/board/cherry_scp/ec.tasklist b/board/cherry_scp/ec.tasklist
deleted file mode 100644
index f0e97e0ffe..0000000000
--- a/board/cherry_scp/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, TRENTA_TASK_STACK_SIZE)
diff --git a/board/cherry_scp/gpio.inc b/board/cherry_scp/gpio.inc
deleted file mode 100644
index 48b397b9a9..0000000000
--- a/board/cherry_scp/gpio.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
diff --git a/board/chocodile_vpdmcu/board.c b/board/chocodile_vpdmcu/board.c
deleted file mode 100644
index b3e49fc547..0000000000
--- a/board/chocodile_vpdmcu/board.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* chocodile board configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpc.h"
-#include "util.h"
-#include "vpd_api.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= 1 << 0;
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Do nothing */
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_VCONN_VSENSE] =  {
-	"VCONN_VSENSE",  3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)},
-	[ADC_CC_VPDMCU] =     {
-	"CC_VPDMCU",     3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)},
-	[ADC_CC_RP3A0_RD_L] = {
-	"CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)},
-	[ADC_RDCONNECT_REF] = {
-	"RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)},
-	[ADC_CC1_RP3A0_RD_L] = {
-	"CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)},
-	[ADC_CC2_RP3A0_RD_L] = {
-	"CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)},
-	[ADC_HOST_VBUS_VSENSE] = {
-	"HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)},
-	[ADC_CHARGE_VBUS_VSENSE] = {
-	"CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)},
-	[ADC_CC1_RPUSB_ODH] = {
-	"CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)},
-	[ADC_CC2_RPUSB_ODH] = {
-	"CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-void tcpc_alert_clear(int port)
-{
-	/* Do nothing */
-}
diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h
deleted file mode 100644
index 552f00aa09..0000000000
--- a/board/chocodile_vpdmcu/board.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* chocodile_mcu board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * The console task is too big to include in both RO and RW images. Therefore,
- * if the console task is defined, then only build an RW image. This can be
- * useful for debugging to have a full console. Otherwise, without this task,
- * a full RO and RW is built with a limited one-way output console.
- */
-#ifdef HAS_TASK_CONSOLE
-/*
- * The flash size is only 32kB.
- * No space for 2 partitions,
- * put only RW at the beginning of the flash
- */
-#undef CONFIG_FW_INCLUDE_RO
-#undef CONFIG_RW_MEM_OFF
-#define CONFIG_RW_MEM_OFF 0
-#undef CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE 0
-/* Fake full size if we had a RO partition */
-#undef CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE_BYTES
-#endif /* HAS_TASK_CONSOLE */
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#undef CONFIG_USB_PD_CONSOLE_CMD
-#undef CONFIG_USB_PD_HOST_CMD
-#undef CONFIG_CMD_PD
-#undef CONFIG_USBC_VCONN
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_COMMON_GPIO_SHORTNAMES
-#undef  CONFIG_DEBUG_ASSERT
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HIBERNATE
-#undef  CONFIG_HOSTCMD_EVENTS
-#define CONFIG_HW_CRC
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_STM_HWTIMER32
-#undef  CONFIG_TASK_PROFILING
-#undef  CONFIG_UART_TX_BUF_SIZE
-#undef  CONFIG_UART_TX_DMA
-#undef  CONFIG_UART_RX_DMA
-#define CONFIG_UART_TX_BUF_SIZE 128
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_VBUS_DETECT_NONE
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_CTVPD
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_VBOOT_HASH
-#define CONFIG_WATCHDOG
-#undef  CONFIG_WATCHDOG_HELP
-
-#define CONFIG_USB_PID 0x5036
-#define VPD_HW_VERSION 0x0001
-#define VPD_FW_VERSION 0x0001
-
-/* USB bcdDevice */
-#define USB_BCD_DEVICE 0
-
-/* Charge Through Current */
-#define VPD_CT_CURRENT VPD_CT_CURRENT_3A
-
-/* Vbus impedance in milliohms */
-#define VPD_VBUS_IMPEDANCE 65
-
-/* GND impedance in milliohms */
-#define VPD_GND_IMPEDANCE 33
-
-#define PD_OPERATING_POWER_MW           15000
-#define PD_MAX_POWER_MW                 45000
-#define PD_MAX_CURRENT_MA               3000
-#define PD_MAX_VOLTAGE_MV               20000
-/*
- * TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
- * MP FW.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifdef HAS_TASK_CONSOLE
-#undef  CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 2
-
-#else
-#undef  CONFIG_CONSOLE_CMDHELP
-#define CONFIG_DEBUG_PRINTF
-#define UARTN CONFIG_UART_CONSOLE
-#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
-#endif /* HAS_TASK_CONSOLE */
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#undef  CONFIG_FLASH_PSTATE_BANK
-#undef  CONFIG_FW_PSTATE_SIZE
-#define CONFIG_FW_PSTATE_SIZE 0
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_VCONN_VSENSE = 0,
-	ADC_CC_VPDMCU,
-	ADC_CC_RP3A0_RD_L,
-	ADC_RDCONNECT_REF,
-	ADC_CC1_RP3A0_RD_L,
-	ADC_CC2_RP3A0_RD_L,
-	ADC_HOST_VBUS_VSENSE,
-	ADC_CHARGE_VBUS_VSENSE,
-	ADC_CC1_RPUSB_ODH,
-	ADC_CC2_RPUSB_ODH,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* 1.5A Rp */
-#define PD_SRC_VNC            PD_SRC_1_5_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_1_5_RD_THRESH_MV
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/chocodile_vpdmcu/build.mk b/board/chocodile_vpdmcu/build.mk
deleted file mode 100644
index d4e5f58962..0000000000
--- a/board/chocodile_vpdmcu/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F051K8U6TR
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f05x
-
-board-y=board.o vpd_api.o
-#
-# This target builds RW only.  Therefore, remove RO from dependencies.
-all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/chocodile_vpdmcu/chocodile.html b/board/chocodile_vpdmcu/chocodile.html
deleted file mode 100644
index b38edf94ec..0000000000
--- a/board/chocodile_vpdmcu/chocodile.html
+++ /dev/null
@@ -1,9491 +0,0 @@
-<!DOCTYPE html>
-<html lang="en"><head>
-<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
-<link rel="icon" href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAEgAAABIAQMAAABvIyEEAAAABlBMVEUAAAAAAAClZ7nPAAAAAXRSTlMAQObYZgAAAFdJREFUKM9jYGBg+A+EEEANFvN/EDgAZMmDWT+ALHsw6w+QVQ9m/UNh/YcAXCyo6VRiAc38D8ZUYoH9/R9qBxVYNHAfVcOPQGxhi19E7CNSBCKVUDf9AQBM1TcCCjMB0AAAAABJRU5ErkJggg=="/>
-<title>chocodile/chocodile.cpm - 71311de5a6455abe5b4ca313ec5effaddaf8dff7</title>
-<body>
-<script>/* Javascript code for DiffUI. Directly embedded. */
-
-var zoom = 1;
-var dark = null;
-
-/** Activates or deactivates animations referenced by diff id.
- * classname -- used to select which animations to trigger
- * state -- whether to animate (or reset)
- * conflictswith -- classname this diff conflicts with.
- *                  Conflicting animations will not be started.
- */
-var setAnimation = function(classname, state, conflictswith='') {
-  var anims = document.getElementsByClassName(classname);
-  for (var i = 0; i < anims.length; i++) {
-    anims[i].setAttribute('fill', 'freeze');
-    anims[i].setAttribute('dur', state ? '1s': 'indefinite');
-    if (conflictswith) {
-      var attr = anims[i].getAttribute('attr');
-      var siblings = anims[i].parentElement.children;
-      for (var j = 0; j < siblings.length; j++) {
-        if (siblings[j].classList.contains(conflictswith)
-            && attr === siblings[j].getAttribute('attr'))
-          break;
-      }
-      if (j !== siblings.length)
-        continue;
-    }
-    anims[i].beginElement();
-  }
-};
-
-/** Callback for when a diff checkbox is clicked.
- * Animates the diff and, if checked, unsets any conflicting diffs.
- */
-var onDiffClick = function(target) {
-  setAnimation(target.name, target.checked);
-  if (!target.checked)
-    return;
-  var row = target;
-  var td = undefined;
-  while (row.tagName !== 'TR') {
-    td = row;
-    row = row.parentElement;
-  }
-  for (var i = 0; i < row.children.length; i++) {
-    if (row.children[i] === td)
-      continue;
-    var checkboxes = row.children[i].getElementsByTagName('input');
-    for (var j = 0; j < checkboxes.length; j++) {
-      if (checkboxes[j].checked) {
-        checkboxes[j].checked = false;
-        setAnimation(checkboxes[j].name, false, target.name);
-      }
-    }
-  }
-};
-
-/** Handles restarting animations when a page header is held down.
- * Also updates the history to include the page number.
- */
-var onHeaderMouse = function(evt, down) {
-  pushHash(evt.target.parentElement.id);
-  for (var tag in {animate:0, animateTransform:0}) {
-    var anims = evt.target.parentElement.getElementsByTagName(tag);
-    for (var i = 0; i < anims.length; i++) {
-      var hasattr = anims[i].hasAttribute('oldDur');
-      if (down && !hasattr) {
-        var olddur = anims[i].getAttribute('dur');
-        if (olddur === null || olddur === 'indefinite')
-          continue;
-        anims[i].setAttribute('oldDur', olddur);
-        anims[i].setAttribute('dur', 'indefinite');
-      } else if (!down && hasattr) {
-        anims[i].setAttribute('dur', anims[i].getAttribute('oldDur'));
-        anims[i].removeAttribute('oldDur');
-      } else {
-        continue;
-      }
-      anims[i].beginElement();
-    }
-  }
-};
-
-/** Callback on clicking the expand button for lists of diffs.
- */
-var onExpandClick = function(target) {
-  var show = target.value === '+';
-  var row = target;
-  var func = (function(e){
-    if (show) {
-      e.removeAttribute('hidden');
-    } else {
-      e.setAttribute('hidden', null);
-    }
-  });
-  while (row.tagName !== 'TR')
-    row = row.parentElement;
-  for (var i = 1; i < row.children.length; i++)
-    func(row.children[i]);
-  while (row = row.nextElementSibling) {
-    if (row.getElementsByTagName('th').length)
-      break;
-    func(row);
-  }
-  target.value = (show ? '-' : '+');
-};
-
-/** Validation function to ensure conflicts have been resolved.
- */
-var onSubmit = function() {
-  var rows = document.getElementsByClassName('conflict');
-  for (var i = 0; i < rows.length; i++) {
-    var checks = rows[i].getElementsByTagName('input');
-    for (var j = 0; j < checks.length; j++) {
-      if (checks[j].checked)
-        break;
-    }
-    if (j === checks.length) {
-      return confirm(
-          'Some conflicts do not have any changes selected.\n'
-        + 'Unselected changes will be abandoned entirely.\n'
-        + '\n'
-        + 'Accept anyway?'
-      );
-    }
-  }
-  return true;
-};
-
-/** Callback function when clicking on an instance.
- * Updates the location with the instance's path.
- */
-var onInstanceClick = function(target) {
-  while (target && !target.id)
-    target = target.parentElement;
-  if (target) {
-    // If this is the only instance of this refdes, strip the symbol suffix
-    var refdes = target.id.split('.')[0];
-    if (document.querySelectorAll("[id^='" + refdes + ".']").length > 1) {
-      pushHash(target.id);
-    } else {
-      pushHash(refdes);
-    }
-    if (target.classList.contains('highlight')) {
-      highlight();
-    } else {
-      highlight(target);
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-
-/** Updates the back/forward history with a new target (if not redundant).
- */
-var pushHash = function(target) {
-  window.history.replaceState(null, '', '#' + target);
-};
-
-/** Highlights an element and removes other highlights.
- */
-var highlight = function(elem, scroll) {
-  // Remove old highlights
-  var highlighted = document.getElementsByClassName('highlight');
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j0IA1dgxbuQDqQQdzITE6XI5c/mBsb36YAvod22Z/cS925npEapHJJBbUFx11e783tuNqoirXWf+H8j8zio4hoW8j/5ot9iLfiUfS3v+EcDE61UTXwprbSv0p4WxQnqPJn73OnkfnFfYXdlKG/N/pvIxQXEgVv8AnflWgueQPzscEWu7fRAYA9XvtoHkEoJ2CdL66e87aBn1e8RXInrzrWvzHdqK70Sm29gcGJbb3n9A22rjXcGQIBNg5O5DcmPMjbTziC68KE10NdtfSxsa0vfWl8NGbo5Pyck9hcOddYmSjm7jQWcDS7OBrdyTYWdhFvdfrau+unyOu4qqgGwSCRhe+vXmO1rc7EvZ3sRkhOxGmgHc3L6HS5u+ju4tzjteg/x056a3oOZwbn3u2z3LFm7b31vGQiW91WcbWsdhyY77++LW8/civOvTmOnVXkL6NbnTXv1PIch5mMtCGA5gWbYWLA8mDEnXoItrjmwNSee/KprVI5epucV1udNnbWzH4gCx+EZEtBVtb3Wa3+Eb8z5AfQ5K4l594W5hhs18OM5ZlyRmSCUksTrK06j5LHlCHEuGHefgXmVRME4UAREDEh6DimiWYlh1pS2lZlFiFbhs9NTh9XU0VSj8s6mmrkrAseElChxJV+8hQUhQspJBEfLzFlTLecMMm4JmnAcJzDhU8K9rQ4xQ01fTlZSpPtUIqZcwSZ8sEmVUSjLnyVtMlTUTEhUZxOy77cfMsmdg8r9q7K4zXLVqhYdnihkKXQUszFCXDT8TmbJzSoSRzltZWIl2LywrL78G0w40xl6bvRLfuO6Mt+MdTKKabM1N95l/hAxKilolz0X4VKqKQFEmaCSCVU/sCgJIEmaVDh89PF/+j1wmvRUYx4M4wcGqkibNXlDMlVPq8Ln24kSsJx1Yn4hQKTwmWiRi4xKXPXMQuZidEiUv2mwxwo4x8LuOeUYTPfCPPOX8+5Vi1BoTSQxgeVBxZYZiVS2by95LMzkU3Zh4iHeiJPOoKAmkM2+yqIhGg4jvd64biuHYxSprMLrJFbTKLe0kr4ihbBRlzUFpkmaApJVKnIRNSCOJAcR5jZzyLm/w8xudl3O2XsSy5jEgFZpMRkcAnyeNcoVVDUyzMpMRolzJcxEquoJ9TRzVS1iVPWUKbsvH0I4nDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEW+bTeVSCVzCdz2Zy+TSWUQUTMZrN5rGQ8vlksl8G0t+LjphHxbjMLBwcKwhb0RExDrbLLSFOOLShJIjmzZUiXMnTpiJUmUhUybNmLSiXLloBUta1qIShCUglSlEAAEktGTRUVZiVZS4fh1JU19fWz5VLR0VHIm1VXV1U9aZUimpqaQhc6fPnTFJlypMpC5kxakpQkqIEa9nbW9tPCSt6bcN+yB9mmUcy5FS6a8bJzL24mVMOoSplZ4dyGPbUzNnGniS1mbMUKuUOFhZl0inEDFQk4T0Zm/wAXEyzNw/KvDMmJKpc3F5qAqWk3STQSFhprK0qZ6TJPCfZyZyVImj028AvsET6yXRZr8bva0tNMTJqqPIFBUqlVk1BImJGaMSplpXRImIACsKwucK1ImJ+9YjQz5U6iOvFmXOuac95gmebM7ZjnebczzqI+0zef5jmkbOZzMogIS2lyMmMwefinlNtNoaZ77pS0y22y0ENNoQnoWqq6qtnzKqsnzquonK45s+omrmzlq0da5hUtQAAAST+EABLAcMen2D4Dg2XMMpMFwDCsPwXB6GX7GjwzC6ORQ0NLLKisok0tMiXJlFS1KmLKUAzFqVMWVLUVRBbd3Brz1rW1lDwA0tXWmoxzcC7H909N2GhB+TxlzJb3sW+gCzNc6i+8T2n6UANvUgAV8+hHxU0BrXFH1e3I7HX07EveMZSHNwR77fDz6X0aLg3EV3vpXenKpFDXrfypUeos+vw7G+vTqIgVLcP0t7yWuxG4Fix7tPQ9epNhvvfQ01A9RS17VEPfrq4BvyI52A0Lb3jHVJbTTz6bO40a14ltxJ1rX0tShJ0PPVQB3NxamjA37uDfkp2fo4tu0QlDOW89jzfQsOxb3xJTFCl/6EaUJAOnhf5CpJ69mf4c+bkdoiMoEX89i77h2PbhIHrFYRKdK0Bvag8LUBr+umDvb8J53+THf0+Nhk9CknRiCe4uAH0ZnjmIogUqelzb5fWuKW5I9f8A0w9kf7yh0OvkygB5vH4YkDc1J3+tx60GK6ahIfkf4D+EPYF78XTi0fyMUjFDb5AgHxHdFxzGv0OSW7aDnu5JDe/0i8SgNgCGdyfh+FzvoTEZUUb6aa69TtTyJIGB1253ueQIF2G7+rXi8S3Fn7aeRuHs17u+sQ1v13qfKl6UpanQgA8hzBvdzJ+AOltz3GrzJlH1Hx3fe2rDoRq8Nx8CtTW1tdq02BO2pHhagPrqTd/K3QB+m/YmMhEoDYHk/L383vzG5D292I7wrXUa+VqUAqBsAQka1w3vci7Db5eZbpGQlDdXt7/W/IW2L2e3rdrXoRU+VgbW8BTcUBoTVuZfcC1uWwJ3+g8ZCJZOum4/W/mw6RbnnwK/FsamtzrqeQ0GpN9CMV199+WnrrsDpGSlLWDM1ybdPIDlfX1tTzwuSdLgaA0JvWlh09epn6DfuXfbzDX9L5KEaM+tz2fUPpfT1e4i3Ou/vKPgnSvIkaV5eHPSptYfm+HO/LmT+XvGQlOw03P1qdgLnSOz+C/aE4v9nTOcNnzg7nmdZLn7K2PtiYCIK5RPoSHWpxMrzLI4gOynMErJccJgZrCRLTK1/aIYMRSG32/q4RjWKYDVJrMKrJtJOSU+0KC8qelJJ9nPkl5c+WXICJqVN+ZJSr8Q4dnzwzyR4o4FOy9nrL1Dj2GLTM+7mpl8Ndh86akJNXhOISuCswyrHCl6iinSVzAn2U0zJBUhW032GPbA8Ku0a9J+GvGtuU8H+M8X3IOAiXYwscOM9xpLaGmZBNZjELfy7PYxxakM5ZnkTENRTqWmZPP5rHRaZZD7H5P8TsOx0yqDFhKwvFSyEqKuGgrF2AEiZMUTInKNhTzlEKLCVOmLUJY8fftD/Ygzj4Wors15BVW54yHJ4p9TKTI9pmnLtOONS14lR0spMvFMOkJSFLxbD5MtclBXMrsOpKeQqrm5l8dpxolDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR03x34+8KuzZw6m/FDi9mmEyzliVJ90wlX+sTefTV1KjBSDLUpbUIqczuPUhQh4OGT3GWUPx8wfgpXBxsdDfLxjGsOwGhm4jidQmnp5dh+9NnTCDwSKeUPxTZyyPwoToAVrKJaVrTzrw68Ns4+K2aKHKGSMHnYti9YeOYR/ZUOG0aCBPxLFa1Q9jQYfTAgzJ808UyYqXTU0uorJ9PTzdO/tze0t4udsmcRmW4NyN4dcC4KLBkvDWXR6vez9MJFCIgp5xCjoYtpzBNy61DRcNKAVZckDsPDCWQ0VM2ImfTLVrOWfcTzVNVTpK6HBkq/ssPlrvP4VcSJtctJHt5hZKhK/zEghJlBSwZ033I+zz9lDJfgXQyMVnIkZn8RJ8kivzVVU6eHDTOk+yqMPyxTzgo4ZRhC50mdWFsUxKXNm/e5smlmSsNpcdjbwNKkA0pWtajW4G/I89KmuOA3HbXiYeY7dN7ux12hKeVxyvppvr1G3aLg09cA69b8/MjXqAb3IwIGx9N9nYvfnbXRwLQKQDcNo2nbv1d7c9zFxaiCKGvhU263NK6mx02odLXdhcdGt1/mCzt0EYypbbB2FnsdmflewOruHie2+DS9KC9BUelPhtrSosLVqQJuxHO2r9iLG3meQa8KpbliAPL3tt5ExObf59L+OuoA8a60p3RW1GbQtfTV/W+2x0jHVKIv57nV9x73sGd9CZaIkgWOl6UH4ingbDU0OHMkEdRfr+puPe0QmW2o+Y+LbDQjTlEoRXPQWrUHahJIFwKUp3vMXwBc6g67s3kNR37veLDLB66/p79y46CJCYoGgrem4qBtyVc05+W4XOzE6nXTmxB+P6RqkhtH00e/lcevxiqIpJ/etzH+O53pvc1rioNnuG5vt3ufreIzJS7Eatbf1c66/zjl9qT/Fbyr9PxxbxD+8fT/0xd7D/ABNy4v4/KOKopINQq2p/wr+FPLFwIZxcDkL+n16Rb7BIIDeRu/m7RTVFC97EWIFBvb7oF60qT5nTFOdne4f+JLeQH6SCSOTX0vbtoD6/xjqixcjn5a3Gh0prUDY2xU6XYON767cree8XiW3IXPy9x5OGiMuJJ33ItQnfSgNeYvzA3GKO+jq06Bxv6jr5AxIEasH1976377h+8RFv6XrS177C42150NQOZw7lg2g28xf0A0bm8yZRPIX2vz3Fr3ve452MJyIFNb35gX60qdxal9b1IrYWD9h/HnzOu0TJlAbcu+2/e1rcrxAdia2FKCvLTwvSgprf0FHfcaM/y09G31EZCUGw9B0HnbkN32i2uP8AUlWo0sbm1b60+I78jQmoD6lunnz+LPvZQ0yEyxvttyNrvv0OzDqIgOvU1uaig5G/qrwA1BoK3qHOhsDrsL+TsRvfrYNOlPTqBz/QbP6RbnXtSTUn1FPW3hcU7wtfADYeZt2fQFrOdBoOpnRLe5Ftg+xOpfQdSXIJ0sItjz9KitTy5aXJGxrTQi1jW+Lm6MO5JJLOAzO/Nj0LM2WmXuQwA+hr0sN99CBbXHKVNak/oW0rTQCwHTW4czZOybXe/n0HP35aUaOGa4HwNjryH72pswGdP2eXtk828F35Jwf7Uk0nGfOEQU1LpDxFfEROM9cNYYpbZhoaaLQHphnTJ0ItJqw99qzTI4R1aJVEzeWwMsy2x3DknxPqsLMrDMwzJlXhjiXIrVAzKyhTZKEzCHXVUqSNDxVEpJPslTJaJcgedv2nPsL4LnxGIZ38IKOiy5nYhdViOVpZlUWXc0zXWubNpASmmwHHqgEfjlmTg9fNQlVZKoaqoq8VmbZWWM0Zbzrl6T5tyfPpPmjK+YIBiaSLMMgmMJNpNN5dFIC4eOl0ygXX4SMhnkmqHmHVoNCK1BA2MkVEiqkyqimnSqinnIEyVOkrTMlTEKulaFoJSpJ2IJEeMeLYRiuA4nXYNjeHVuEYvhlTMo8RwzEqWdRV1FVSVcM2nqqWoRLnSJqDZSJiEqFizEGL7iaPnQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEeZ+1b2r+E/Y+4VzHifxTmhSkl2AynlOAcZVmXPOYvcl2HkUghHVpClU7r0zmT/dl8mge/GRzqR7lp/wCDmLMWHZZw+ZiGITLXRT0yCDPq54S4kyUnXnMmH8EpDqWRYHtjwb8Gs5eN+cKXKOT6QEsipxrGqlMwYTl7C/aBE3EcSnoBYOSikpJb1NdUcMinQTxrl6Qna17Y3FztlcS4nP3EyZmHlkEuKhckZClsTEnKuQ5K+tomBk0K6sh+YxqYeFdn2YX2xMJ5GMMqe+zy+Elstl+pmZszYnmmvVW16+FCCpNJRIUv7tSSSQ6JSTZS1sj285X4pykgnhQiWhH6BPBbwMyT4F5TlZaylSe0rJ6ZM7MGY6uVK/rjMdfKStqivmy0/wBnS05mzpeG4dKUaXD5MxYl+1qZ1XV1XmRp8ineJpXWugtrffwoTelaU42bjqbkEb206sebkM4eO21oJsBe22vXQk20I25OXuLb+lTpoR4358x56d4iuLWZ/eNbuw2Fxz063aMaZLBdxcjVnO4uBr0I72ie2/sTVNvCwJNL2/AjUACre1jyPI9+h3f0JIx1oI1BP+tc8m2ueelv7zRObfI0VXoTc33FQDe9qbdKUsQAf487Eb+rEODrEJTzD9W091ux8xExESLCpr/Ca87GlajTY8t6UMRobPd+m73csW3LbjUwqlPYM2rFtQ3yDbBnB5xObiiki+m42v41pQUAI/PFuj7Nz0HZ9tLAjQWERGWRe41sz8+j+XxtEtEWDavmDQ6a2JHjYDkNsVv27HrpcaN1fvERlf6vS1yQzcrAkkgeZGsSUxQ2URcChItToFUAtpT8Kj1AO9wwA8wz+lvWIlSknu99vgzn6N7xVETWg7w61NSegCiKDl41vinCLMS3QlvrtFnsfif5flfYtr+tUxJtcX/m/JR+dMPM+QB+CYtMkjR/R/0j9+19b+Ip6Vwe373fhL/BvdFPZHr/ALp/WPz7Sb3FP7V/TvfQnDzPmAPiIqJJOpPmG/WKZiQL98a6A0VvUnu18z41G+Dbkn1Ye5ou9h138vh1vo3naiqKA1UbEaGh8RVWh8Dv5Aw0A8ruPi58+8XiSnpcht/i/u98R1RdKivKwIIpXqRbla2lBatbuddd25+evUv21iVMo8r9WsPQHvaIbkWTvTauldKam3gBbStDhq372thps47Wu5v12kEo8tG2a2w0cNfbTRrtDcitfiJPIE/SpVrrX64qxO7Cwsz3fUm3OxvpdtJ0y25AcvPn/E9ohORBpc0HKoqNdtE+JNbeJFQwsL7Wvc6ue/q+pcPKlADMG6nduXPsPSILkRYgHfXcn1uelun8ogfvf7o5B7G3qx3dyNZUIJYi1tSzXbTyO79ogOP2N9qE2BN7bACmnTkK0wPL0A6gdzy/hGQiUzNcnV9HDEkancXN9QNmtzr9ahJN979NL3I1vpzsMXAMLhydADc9xytt5xlJltzJ9dXL30Gl7WFrOIgOPU36nQ16/W50Fr2pUjdTPsAOetr7u2z94yUoGp+L2u7OB5ksAX2i2uv1qEkcqg2A3obV6k610oKYuAIDm+4HXncga792JiZKe7bM5Jt+7bf++zagbPbXXtQDrUk67XoQfnvat7YrqfhyG258tXAta5OShAdy3YPz7EsS7q8hzjKB7OX2n2f+xRmmEydmlc1zz2c59MkqzNkkRAiJlkx6MiAqNzdw7+1vNsQsyQVuRc0y4t+Fk+aauIecls2ch53C9hZIz1WZWnppqgzKvBJ0z+3pX4plOpShxVNEFKZCw/FMkcSZU+4JRNInDUX7Uf2SctePeETsdwdNFl7xQw6lIwrH/Z+ypMdRTy+GRgmZvYoVMnUiglMmkxYInV2EHgVLRV0aZmHzt2jhtxJyLxgyLlniXw0zPK845GzhK2Jvl7MMnf8AfwcbCPd5K23EqCIiCmEFEIegJrKo5mGmcnmcNFyuaQkJMISJhmtpaGupMSpJFdQz5dTS1MtM2TOll0qSrYiykLSXRMlrCZktaVS5iUrSpI8Cs1ZVzDkjMOLZUzXhNZgeYMDq5lFieGV0v2c+nnIYpUkgqlz6aolKl1FHWU65tJXUk2RV0k6dTT5U1f3GMqOPwwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR0D2mu0lwy7KHB/M3GXirNfsMhkTX2aVyuGKVzrN2Zopl9Ulyll2FUR9qnM5eYWhsrKIOXQbUZOJrEQUol0fGw/x8dxuhy9hs/E8QmcMmSGly03m1M9QJlU8lP702aQWdkoSFTZikykLWnsjwn8K82eMmd8JyLk6j+8YjiK/a1dXNdNBguEyVyxX41ic4f5mhoZcxKlBPFPqZ65FFRyp9bVU0ibofdrfte8Ue2RxcmvFPiTHFiECoiX5JyXBRLr0gyDlb7Qp2EkMoSpLSYiIKe4/O5y7DtRk9mXvIx9thhMJBQeo2Zcx4hmfEpmIVy2S6kUlMgkyaOn4iUyZYIDki82aUhU2Y61cI4EI/RV4K+CWUPAzJNFlDKsgTJxEuqx/Hp8lCMSzHjHsgifiNYQVmXKB45dBh6Zq5OH0vDIlqmTFTp8/zU0/TRVR0uR89fGxrc0GOPkP0Ojj0v31bnpHaykN08mDHUC1jrYgC2jl4uDT+l97bU3FRXcHqNyBQYt/xbaEWt31BOhdhyL6wlAILgfBux2JY80nyETm3qfdPltS9ed9qjatb4oX0Nw5Lj8wvt56t1iFUvZn6al/gQ4LNd9jE1uJA1NKW2pvSm1DtyA0xaQ9wXfbfzH6d4gVL152J/5dX3tuxc67xObiRqTre1NjXStNa1rptbFL6N5HXTby+XSMdUndiDa6R05M/YAlrA7iJjcTWlSFaa3p1uQfOu/UAGF2JBOr3A+f0LamIVSjsHblYvyIZh5gbXiSiIA/eINKUrUDmLkK8b1A3GFxdgW1Zja50u3kGB56xEUajTooN79PeLxJREkalJ5XoedQDTbS/mdcUZNthvqm/v8AePIRYZb7eYD9eo131ismKvevzpodaEjwofywZtyX5tb0+Y7RaZY7bsQ7RWEWB+/6kA/8wP8Aj6OEsCwPViG82Pu/nZ7Ht0+gB9e7mIux+Ktbgk976rA+WDbkC/Ignz3inse3qf0h9q/nT6YRb7E9fUQMXQfepzNe74aLp8geuKEbgDzLHysTF3se3qf0jgYuv71TrY1r0NCTTT8N8VYs9g7bG/mwGmnK+sV9kOmt9/K4Px9IoqijyPjp6VKRTwv47G6kX6fME+5vhF6ZYGxJPIfFr+/pFFUSdikdK6enjuQCd8Pw9SBp+8/V9fcW3FouEsD91u9hztoPSIy4kH94k6G9K6V0NbbiopvbS697Ad226aaF9ObXiQI0ABPIJHfcsB7/AIRFXE63AF6gGh13oeQ5nWtCLClupO2w9NddreRiRMpXID3qPqO2ib2iG5E9dOZpcVItW1qCtTpfTFb6Dlone7F28zyv1MTpk6G50ub2cC3TdierNpCciamxrqQa2pXx6UoK72NsG5nowufTb5d4yEyujltGc3Ggb4htr3LwXH/4j0pWg0pz2uNTbbF1+wDf49LdrdmD7ROmXpy3FidTvcB2e7nV7awnYim9AAbDXXlXrva+nOoBtw8hci7HZ929G7XmShm66276vuNXOp0dr25187qoPG5/PTpbrbFzMLa8z9CwezG0TJlk7A+Thg/+8Q5/1Q1g0W91+xJPdT6E/P6cvLAB/Q337gAENbpfZnjJTLbvsdd2Y89LAWtfrbXX6ggEhNNtTr1ubbGgvfbF2nUvp1drjnYW7XtGQlF3ZzybqGBt2HCPNtYtzr1rWGutyL0vurWh0Gmwxcx/xE2G4A30sGcdA9umQiW1zcsWcWHlt29GvGUn2YntLs0diHiI3lbOEVMswdm7PM2Y/wAussJXERj2TZlEe5hDxFydBhSgibwjDTCMxyqFbCM1SWFbhnEKm0tkUVB9g5FzpUZWrPu9Utc7BquYDV04dRplqZP32mTtMCQPbISP8plpCWMyXLWjUL7Wv2U8I8f8sqxfA5NLhvipl+jmfs7ixTLky8cpZftJ37L45OYcVFPmKmKwqsmqKsHrpy5qVCiqcRkz957KWbMt57yvl7OuTZ3L8yZTzZJpbmHLc/lMQiKlk5kk3hGo6WzKBiEfC7DRcI+080qx7qwFJSoFI2mp6iTVSJNTTTUTqeolonSZ0shSJkqYkLQtChqlSSCD1j89uM4NiuXcXxPAccoKnCsZwauqsMxTDa2UqTV0NfRTl09VS1EpV0TZE6WuWsXDpcEggn6HE0fMhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPm85Zwyxw+ynmXPWdZ1BZcyjk+RzPMmZp9MnFNwMokcmg3o+ZTCKUhK3C1CwjDrpQ02484Uhtlpx1aEKhqaiRR086qqZqZNPTylzp81ZZEuVLSVrWpnLJSCWAJOgBJAj6uB4Ji2ZcZwrL2A0FRimNY3iFJhWFYdSpCqitxCunopqSmlBRSkLnTpiEBS1IlocqmLQgKUNCX2jHb3zX25uNcTmBpcwkvBzJT0wk3CHJEWoNuQMndebTF5qn8K08/Cqzdmsw0NFzUsuPIlUEzLcvw0TFtSpcxj9Sc65sqM1Yoqc65OG0pXLwymVbhlEjiqJwSpSfvNRwpVMZ/ZpEuSlSgjjX+jX7L32ccG+z5kKVhi001dnrHkU1dnbH5IKkT66WhRk4Ph05cuXOGCYMJs6TRcaUKrKiZV4nNlyV1iaWm8AtPmxSfEHfQ2ob2pWtz1rTHDS99rs/kWdmc3Lkh+mx2SWgj8wbrz0IJ73Lgk66tFwaiATYlJ0psTa3npTX6YtKWfkb2AY7aWZ20tpoLxCpHY2azX1a+4tobsDfV5zcRzNDzGn18DyItca05vvrdxaxvt1DB/K2OqW7tf1s3kCN+mo7Tm4jrUcxep8zTzNPle0pGosfduOXw6FogVLN+Q0dgdNtAeX7pZrOLTURANP3q+up2JrfbXyIpihDM4Nt9/W2lvzDnuLxqQNhfS9jqNCwLaHcM/nKQ/yVytt08vECu+BvuCG/e18jb42di0RKl6NZnNx15gM4dtLEsWiUiJNb3puDS/M3pXpXU7YtIDaEdWcdL6t6+cRKla27FnvewIB7fuuAwsIkoi/5iP7XOo12ANL0rp4YMdmc3cH5M7jW3pERlO9nZ7FiG32dx3ZmiQmKFhUXroaevxU7vQctNiuHJfXRQf4hn9OkRGQNWHMkO/lY3625iK6YobE+RvptcW8zXyxTlZOnb1uL/reIzJ6q0u7KFy7X0Onu86iYutu95X73zWflXywYDUK9fkRaLfYm9rD+8hh/4R8Y5/aa7p/vC/4n1xUEDVS+zhvKwinsTf8AJ5cXnZwB84faerf6/u4q45r9RD2J/wBX/m/WBiqDUD+yNNd7aC9xQYtLFmKzfQkegsTf6eAkl/3OliTfubeUUzF7d+3ME19e/T+u2K8P+qfM2b0A84u9iXYv5It70/MxTMUDbvHxJoDfoTflf02o9tE69yPV+bP6xcJHPj10sB/ugac+ZHrQVF0uSOdzU7XNTfpQfWuK3szl3FgQOwt0csIvEgBrJ3D6vqG0Atvaw2JiMuLuaEnw8OqqbUNPIYMGF0jnd/cAfc8TCVsxBFyNANuQ73dtS4ERlxKq6gV5kk/M9aHWuKtbQ9XZI8+e27nnEqZVzbhboA55mwN7HQ6O1oirfF6qJNDre2umwGtaDxvXFe5A6Is5Gz8+nbmHlEseYvbp1Zz6J20MRHIrr0oLmw6HlzNNCRioBZgANn0P689eHbQOIkSgH1u2j2uTsdTcg2dtohORBvVQSBWlSQT0F9/Ac6jarC5Nz1DAHsWfu/K8TBB5dmZrvdyLtb8ovzNohLf1pbeqvL8OeK3t8dBaxtvt6guYmTK5gDoBb06PcqN3cagRAdidaVUbipNhWo56VFDtS3TFWY3ccyfl5Nbz3jITL3Nn6G45aOpujBuhvAcfuaqqemnK+tRa4237wvi/UE6AbnVruNhd9Bbn1nRLJIYMOZcFuQIFhzAuw8otzz+p73gNuVDU62+7S+ADizgalRtbcW1G/KMhCOQHU2BHpoNTYvraLe8+b1J3oPWm4AH8uvnbF4AH5fXfy09dLaF3jJRL/ugPqTy2tbfn6g7W9x4nW2thpf0t0xcNuXf+frGQEgaX5q0FtQLO9/i5a8Z/vYqe0te4C50lnZV41z/ucEuIU6LPD3MU1fQmE4V5+nMSVJg4mMeWn7DkbOse6GI/3hXBZfzREQs9UICXTXNUyT214aZ0OFVKMBxKb/7sq5rUk6YocNDVzDZJUWKaapWWXqmVPUmaQhEyomR5tfb0+yojxGwKr8YMhYaVZ/yzQBeZcMo5ZM/OOXKGUyp8qRLSfvGYcBp0cdKEAVGJYTLm4ak1NVR4NSHcxxsdHhbDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEai3t7+3/Mc0ZqhexrwtmgGQ8rRjE240TqXxDhZzZniWRKXoDh8HmSGHpTkR4Qs1n7ClRSX84vS6GeagovKCjF6/wDipmpVVO/ZuhmPS06gvEpiFEioqkKdNI4/CZdKoJXNBKuKpKEEJVTni9WP6MDJPh7mCpz/AOJ6cWoMczxknGkZLl4KkJXNyfJxPC5dbNxmaJiSr71mCSqvwegrJASink4TmGhE2dNnVsmj1wYaLS6AtKqcxXQ2sRenjoa1NjfpbZtRsDr6m++9x6AeywCVo4geJJt/rJIsQbuD63u5DRc239AbG1xr1rT71ieSq3OLWO1xuk9NAH72e2hiJUvkxHLtpbnfZ3G0TkP1ArcaVGt9PDlQ2rzoa2M+ljcN9fMWIckWiBUofu668O36HZ7A6dHnNRBtcKHXyG532Oup7tzWhGxt+unpz1vdtGgXLvcMxfdvdcc9xtyMTG4kHQ92lqbddh86HQ60xRrWsG2v/EEndw+1neFUu2ludr+YsexY9dzMREfxAa6imxPIGnlrvhd+eum/kb78tRY7RCqVt7j5PYkp5lwQ1nu0S0RPJQP9oXHrQ1rfXagoMUYEu3LQsdrFvLW/SIjLIsNfo7l2D2ZRbV9olIiik3qOWh33JHjoaaXtTFAkjQ9gRyHPTU8iSzRGUNpsNrH38OnqfjXTFUpcHx+ZFQK9L05Ypw7FI2DgttcnQn05xGqWHDtsC9m83B20F+Z3NcRA1FLjYDTyT+tcU0s5SDzct6gN5E94tMp7t1d9ttSfifS5qCI0+MgfXyNaacqdNcUtq6S/NPvtf1iwy7a6mzjb/e+UVBEqFfj+X5U/HyxUgbpHrwjyBb3WiipWmnmNNLaa8/KP37Ss/v8A1H1wb/U/5ot9l0T6fwjl9pVsoA86p+dACfXDhP8AdJ6FQ+TQ9l27Ekj0NhHH7Uv+P5HAgDVA/wB6HsuifT+EcTEGpJXbnQDXyP6NjhoHZIHV1e8P9d4v9na3nZwPcG159xpFMxFtSdaHUEb7H9a9DgaKHkken84r7K46i3l1KlbdYpqiQKmwrWlh+Vb3HP6lrzVY9A+3T0J7ReJYGoax/e1Iu9iPmxuzRHMWBeo8hWo6Gg0Ntz5UrUAuGAS3Nn63u/S45ReEMxHO4ACQH1DkgX2ILcn2jqiiRWlK0uaDoa0AFN960pSutWfUk9gQC4+nYs+0Xpl9O+7jfca7gkjQsYiLih/FU8gN6HagA06keGKhrs3xPmWtrub83IiRMpx33Oh3fZLtve3URFXEHmEjrr0008rbHBuu/c99hzt6sLRMmULFr8/n7tQDq7m8Q1xA2+Lck+PM0PhUipvsQbmA6ak6G+psGZzsWA90TiX3HxNr2AKn0OwuO8QXIiv3lVpU0BNtbbeYF6Cx5VDtYeZv0YBn32BvqREyJZuwFtCQlvIaaWu5O+rGE5EGpv3dSANd61tbxN9BYgkVAfS5e5Onf4jd2cGJkyu6j1e3635sLk7xBciDse6KG5qa602BJryoBehG1wSHc/iPJ7DTV323ubuxjITL04mJFgAAW6PfezDUb84Dj+tDpqT59La6A1rypTF2vXk2nxLs2pto14nEsMH20SOnx5+93iGtwqNvX6/4m9LYrErNbQA6b7G5bTmHd72uDSwh7oYQjdg9iV7Qd7tLcKXuzzxUnRi+N3BWRQf7GmkcqsbxD4VwqoeVS2bvxBdWuNzJk2IcgpBmV95th+YQEZlqcrdmkzjMwxUNst4Z5uONUBwivm8WJ4ZKT7OYr81ZQJaWiYS54p1MSmVOJYrQqTMJWtU5Q8FPt8/Zql+FWcUeJuT6AScg59xCf9/pKcf2GWc4ThNrKqilyglIp8LxyWioxLCpaFTJdNUyMVoUoo6SThkmbnYx2lHnlDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR4I9oz2uobshdnaeZolMQj/OhnYxOS+FUJ3YZ5UPmONg3Fxea4mGiUuodl2TZeXJutDkJFw0ZN/wBhyaMabh5suJZ4nnLMIy9g82fLI+/VRNLQJ/CSJy0ninkKcFFMh5hdKkqmeylqAExxwPxEzanKOXp9TJUP60riqiwpDJJTUrQSuqUlQUDLo5TzmKFoXO9hJWAmcVDRTz3LIvPEDNXpjFxUyn0VFRE4Eyj4hyMjY6cRDjsRFREdGRTi34l+ZvOvfa4l91Trjz5inVrcSe9q3VcU8KUtRXMWpUwrWorUpaiXKlqJUVLLlSieIkufxOY+f9hH7UVX9l/7QOCZxxSrnKyFm5UvKfihIXNqDxZcxKrQtGY2R7UzsRypiRlY7K45M6bV0cvFsKlLp1Ysupl+UWnHoR1QKVoUhRQ6y4lSFpUhRStC0qopC0KBBCgFJUCDS4x8g2JB2t6fXyj9lNDW09RIpq+gqKeso62nk1dLV0k6XU0dbSVUpM+mqqafJUuTPp6iTMROkVElSpc2UtMyWVIW6voGItLiQpCqg2IOoIoCk7VHQ1NiDocUb3db/rtfXrrH1xwTQFJs731bdiHtyPufVVwbiL6kU0HSx8fWoxQh9Q7eR+WtrWEWLlm5I4g2o131v03t1vE1ERShNb7g9AK7jzsd9NbCk3ANm/KfkSe+2u7h4gVLOgYi7A7e8aC1iNdNIloiK0FQflTexPqTWpppcYoQAzuk+ZGmo823tERlB3/KexL6eZ3/AL3SJSIihFFFJva522FjprU79MUY3txc2fs40c21YjnERlHVgW04SAbau3/l9SHiUiJJ1orS4NPqAa9KfXFGdwe1x7jv7jEJlgPqNQxGg8nHuG8SERQ5qSba3+RFaDwvinDq3xc+QN28ojMvo/bV9WsSP+XSJCYqp+8lVib21526+OKM3S/JvXr6RGZQfRux79U38vOKwiP5TpqFVJ15jrXXrrfC9tfJrdXIB+tOdipQ6HysPNhflc77mKgiqAXUOmv5fj44HdwCOxJ7/LQ84tEp9DfV+I99OJvdptFT7WLVXWlqd38e6fw6YoyW095T32vbtAylbA+/z/d9PoRzEWP4kjxA/wDcJxayb2T/ALx/T4PFplKGpV6J+bfW0fpix/Gg00sPl8GDJ5J/3z+kU9mf7yvRH6xwMWP4gPADrrRNPx64AA6AeSi/I7Rd7JXU9w3wB+to4mL0HfJF/wB2lP1/iMXAJ04fVJ+LfOK+yJ1cdywbv+FttDFNUTXdR86fh+fO2K3br0b5vAyg/Pp+a/rbyAikqJpsBY6q8b0pS16W8N6g/lzOvmAPhEnsgzufhs1/yW6Hv1igqK/n9B+NPxxViSW6ch6k+7SL0yunTzOx8/8AW5RHVEi9ATyJNB5bX6G2DDdreenLb4d4kTLY7PyAfof7xHqAbRGXFE1+IDoAdL2JtSniedMXAE6Am57efI6b9IkTKvoTrd2353N9WcX6mIi4i1bnqTrTpYEepHOmDWuW6emvTcajVr6zJl9QNdBfzOr6NfsBEVyJ5knagsPWmg2sAD0OKhJsWYC7m/u6XawfvEiZQayQANzy33AcdH0eIa4nUV7o1uTf8SKC1afndwvr+I+jC/16bXicS3L/AJjYcm215X6ekQlxHI+Zp4eA8q7Hli5voW+uu3SJghhcsP7o13735687XiIt4qJ1NdeVbeZ+XTFeXbTl8vj31iUBnAHDbuTr6dHOh0O9IknXCGjtZ9buT58ugYdI/MIQwhDCEdy9nzjnnns18ZeH/G7hzHLgs1ZAn8LOIZn3zzMJOZf8UNO8tzX3CkOOybMsnfjpHN2QauQEe+Ed10IWn6WEYpVYLiNJidGvgn0k1MwByEzUXE2RMa5lT5ZVKmDdKjoQCODeJfh9l/xUyNmTIOaKdM/B8yYbNoZq/Zy5k6hqbTaDFaP2gUlFfhVdLp8QophDIqaeWVOjiB/o5dn/AI3ZL7SHBjh1xw4exKojKfEbLkLPYBp1xhyLlcX7x2BnWX5kqGW6wmcZansHMsvzhplxxtmaS2LaQtSUBR3FwnE6bGcNo8UpCTT1klM1AJBUhTlMyUvhJHtJM1K5MwAkCYhQe0fl38ScgY94W57zP4f5llCXjOV8Um4dUrQmYiTVyeFFRQYlSialMw0WK4dPpMToVrSlS6OrkLUlJUQO4cfRjhEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpEe067Vjnam7TmZIySTB6J4YcMVxfD3huwiJLsvjIWWRixmLN8O226uFU5m+dsuxkPGtttxMRluDyzCRlXJclKNY8848cdxucqUsqoaHjpKMO6FoQr+1qAASl6mcCpKwyjJTICroAGlHibmo5nzJUzJEwqwzDOPD8NSFPLWiWtqirSASgmrngrSsAKVTIpkLvLjHs1YA+J8SbAeeOGHU/Ttv56x1voO513tt7wfq3QHFTLBl0xRPoRoiBmi+7FhNO4xMgkkqpQFKY5tKnxXvf6w3ElSk+8bRj509P4uIBn/MP9b5AtuTfYOY/Tx/RFfaqHij4VVHgFm/E5UzPfg/QSVZVVULKKzH/C+ZPFNQJSFKUipqMj1s6Rl+eqUmnEvAazKyDJnz5VfWTOq2nVMq7ybg0CkHRQGlOShqD5G2MePYyVNVKU4uP3knQj9eRi9NPBaUqQapOx1FLEHkQbEbeBuj6SVJWkKRoq7tfW4I0caWZx5NJS+QQakU8/nSv4fTCKlIOwVbUEgv236s7epiQiI/xB+opSviDzIrim+v8AH6bbziMywdDfkfT0tqfk8SkRNrK8v1Uc7Uv1xThHLRgCCx7tYBtfpoiVKbVPVwQfTUWfy2iSiJ5jU7G3lqB1JA5DFOFgWNmdiLaa97ObdxEZl21s37wYXFndz8HiuiK/nI+fPcaU8K9BbFOE3dLvu4Bc6+/R4jMlx+XTU/pr6cvWK4ib6g3/ALJJ6i3SvPytRuhTtuXPXm/Tl1iP2QuxULNe/oX2OlgeYG9YRG9DtXunTpoa9b8vE0YbqbbS9uYHxN4sMrqG/wBYMX7295vr25iLIp8RSK3rQemhPjfqcUAfYE9Xf4gfXaKCUW0B2DHfqyjzHKKgi66LJ8k/U/icV4W1H/MB9bRaZJ1KfeD5flJ3jkIv+e24KfrQeeuKFJGx+PwinsjpwH3X/wCWPost5dzXnJ9cLk/LmYM0xTau45D5akkznj7ayAe4tqWQsUtCqEHuqSDQg0xNIpampJTTU8+oULFMiVMmkE6AiWlREfKxbGMFy/LTOx3FcMwSStPEmdi2I0eGy1JduJMysmSUqS4ZwSHDR25B9lvtRzBsOwHZz47RrSrpcheEme321AioIU3IFAgi9dORNsfSTl7Hlh04Hi6xq6cPqyPJpB+POODT/GbwbpVmXU+KvhtTzAWKJ2eMsy1AjYpViILxFmHZl7TcsBVMOz1xxgQNftfCjPMMAACSauSNANNfDpiOdgeNUyFTKjCMSkS0h1LnUNUhKRa5UZSQPPruImpfGLwgqy1L4peHNT//AAM75bm9P3MS+jaPhorhbxWgnzDRvDPiDCRKbqh4rJ+YYZ8A2qpp2WpcAqDcgHa9McIrM4ZRw+pXR4hmnLtBWIuqlrMZw+mqEh2/FJn1KJqQ4I/Eh3Dc4+/KzxkeegTZGc8qTZRICZsrMGEzZZPILRWKST7m5REVw04m/wCzrPI/9lJ8B5gwN/T8sY/7e5GItnPKx2YY/hIF+1Xp3DlttpxnTJQ/+sMsX1bHcK67iqEUVcNeJwB/83ueBrYZSnoHWv8A1eKjrf8AOoz3kc//AFhlYnrmHCR6f5Xr9dRUZ1yTqc3ZZJ64/hdmu4/ys/HrFBXDTid/s6zyf/ZWe9dKQFR5nFRnvJH+meVBd7Zgwgt//wBdvXSL/wBt8kA/9sMrJ0/+3sKJ6v8A5WT5fh19KKuGfFC9OHeeRp/+k56TSh1/6vqaaUqAb3rq/bzIu+c8qk3d8w4Sm7uCR97e/wAGtF4zxkcm+ccsK0/+3sLa2n/zXvDM1zpEZXDHijU/+bnPZNLf/ZKff/D622+Ib1Bxd+32RR/9aZUA/wD6hwjbmTV6N59YlGeMjv8A9scqp01x/CibuP8A9LJu2gY8ndojL4YcUqEf5uM9jnTKU+PUX/Z9NCbkmo0OH7f5Ev8A/GmU+/7RYR0//bLfDTeJBnrIo/8ArHKyj1zBhQDjX/5tyNrPz5xHVws4pH/9uM9jxylPrf8A+fQYft/kTT9tMpvy/aLCP+si/wDbzIwA/wDjLKzasMfwkC77mr62t53MUzwp4ok34cZ7qf8A+pT75f6hiv7fZE/00yp/xDhHl/8ANw/bzI+2ccrB/wD94MK+JqyffH5/mp4of7Oc9f8AZKff+Aw/b7Iv+mmVP+IcI/6uKft5kfT9ssqvy/aDCf8Aq4f5qeKH+znPX/ZOff8AgMP2+yL/AKZ5U/4hwn/q4r+3mR/9Msrcv+0GE68v/wArj8/zVcTxrw6zyP8A2Tn3/gMV/b3Ix0znlU//AOw4T/1cP27yR/pjlb/iDCv+rj8/zWcTf9neeP8AspPf/AYr+3mR/wDTHK3/ABBhP/Vw/bvJH+mOVv8AiDCv+rh/ms4m/wCzzPH/AGUnv/gcP28yP/pjlb/iDCf+rh+3mR/9Mcrf8QYT/wBXH5/mt4mf7PM7/wDZWef+Bw/bvJB0zjlY/wD+fwr/AKuH7d5I/wBMcrf8QYV/1cbIXsAO0Hn/AIe52zl2SuImWc0yzJ/EBMw4g8NJpOJRN4KEk+epNL2BmjLoXGQSIZEPmvLMAicQ5+0w6IWZZViGm4eLicwrch+8fBjxPytVYqrKEjNGX66dihm1OFU1LjWH1NSuskSTMqaeRTyqhcyZ7WkkrqCJaXQaWYopV7RSk+XH9JBkDKOasCwHxkypj+X67H8uKpss5pocOxPDqqpr8vVtTMVhOJ8FPVKnKm4NitQqimgSZqp1JjEuYuZJlYYlM3a7xtFHjzDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGN72qPaW/8nDsmZxXJphEQPEDix7zhdkVyCd9zGQL0+g4hWZ8wNvodbiYL9iZUZmqoGZQgU/CZijJAlBZL4iWeG56xr+p8AqTLWpNXXvQ0pSQFJM1J9vNdwpIlSBM4VpcpnKki3FxDrnxSzJ+zmU6wyJikYhir4XQlB4Vy1VCVfeagKBC0ewpRNKJiHUioXTtw8XEnSVQBQHeh+Z/p+qY1lP5jyDX5WcjsQDbSNKlmzc/gPoRPbH1AA8AT/Qb1xESwJiFRZPYe8nX4ekUJvJ4aeyqNlUWP9DFslAXSqmHge+xEN0IIWw6EuIvRXd7iwpC1IVirYhjvbW/IcgSC1v0t254CeNWafs8+LmSfFzKE5ZxHKWLyamsw7jCabMGATx91zBluuCgZaqPHMInVVAuYU+1op82TiFHMkV1HS1MrxvMpfFSmPi5bGo93FQT62Hk1qkqQbOIVQd5t1BS40ug7za0qoK0GGoEG/rseo6cunKP23+G/iFlbxXyHlPxIyTiAxPK2c8Docfwaq4TLnCmrpQWqlrZBKlUuI4fPE6gxOjWozKPEKWppZhK5KiY7TymVVF0k1Wnn1H8w0GxFQbaUjncqaZZ5pOo+Y6/HeLwhaXEhaTUHfTxFNQQagg3BGEfSSoKSFJLg6H5dxuI54Rc50/j6cvKOQWodfHCAYWuO3Tp02Zm1vFRL1NRpyJufM2ve2twcIo3FrwnVibEPyO5OhJI6RVEQdK21IVz86inj4X1NCPXR9xrofr1tFpQk24TbdP4m7C7m+ujFoqiJHJJ8Ca6iw+IV9NeYxVn52c8++r/y6RaZY0c8xxA2bcm5BGwZ79DFURIOxGgA5+Nfz1G+9Dp8mf5j6vtFDKJdikuBfn5akaMfcGi/5akOZM5z2WZWyfl+e5rzPOohEJKMu5blMfPJ5NYtZARCy2UyxmKmEdELJHdZhodxw7IO0kimn1c2XT08ibU1Ew8EqRIlrmzpiizJly5SVLWT/dSlRc2ePlYxieEZewysxrHsUw3BMHw6SqfX4ti9fTYbhtFITdU6qrqyZKpaaUAC8yfNQkbmM4fZq9hzxrz61C5i7RWboLgzInmmH2cmyJELmziLFhdFutTJ5l85UyqlLKh7t37fmiPEQHIeNkkCW/eOdq4H4S4nWBM/G58vC5JAIpZPDUVqn1Ewp/yenYMx456+J0qlIZz5yeLv9I94eZaXOwrwpwOp8QMTQuZLXmDElTsDynI4HSmZSS5kn+u8beYCFJ+7YLS+yKJ1PiNSFlCM1/B72W3Yq4PwUC3A8G5RxAm8MlH2rMvFxR4hzGZvooRExMpm0OjJ0KuoSAzJcrSqEFEqVDl0qcX2jhvh9lbDUICcMlVkxIdU/ElGtmLP95cuYkUqTdmlU8tJ14SXJ89c9/bN+0Ln2oqFVOf63K9DO4vY4PkUfsrR0cpQP9jIrqBasfnpuXmYhjVdPuQJvBwoHviU5alUkgISUyWVS+TyqAaSxASuUy+Hl0ugmE17rEHAQTTEJCsJuUtsNIbSSaJGOWy6aVKQmXKly5ctA4US5aRLQgD91KEhKUjoAAI1rrMUrMRqZ9diFZVYhW1SzNqaytqp1ZV1Ew3MyfU1Cpk6dMNnmTJilGzqMXUS9NLNqPShNK7W7tvXpbS72Pbs5+uv00Yv3qwI5tqH+B6D6vVEvNP/AESvPvWPyPlWn1xcJI6e8/HT09YtNQzlwLWGn6dL+7nbJxlGSZigzL5/IpTPYFRJMHOJdCzKGCjUd8MR7ESyFgUIWAFA/dUKCvx8dytlzNNErDMz5fwPMeGqJKqDHsJoMYo+JgCoU2IU9RJTMG0xKAtJAKVAgEZFJjOIYbOFTh+IVeHzwwE6iqp9LNbdJmyJqFlLv+EukvcXjznnfsa8Ic1tOOS2UxeSpoe8pEblqKUiEWpQNERMmjftUuUykkqIgG5bEKJAVElACMaq+If2EvAjO0qZOwjBq/w/xg8SpeIZTrFS6GYpX5ZdZgGI/fcJVToLq4cMk4TVEkBVYZaUyx2RgXjhnTBlpTU1snHKQMDIxSUlU8C/EqVXU/saoTFCwNSuqli5EniU8eHeJ3Y64l5CRFzOTsIz1l6HBdMbI2Hm5zCw6T8Tkfl9anooe6up1cqiJs02wkxL64dtLoa85PGX7D3jJ4XSq/GcvU0rxLynSAz1YhlmlnjMFHRi8ydieVVKn1p9h+JU+ZgtRjcmXTJNZUrpJSZyJHfWU/GvKWZFyKSvmLy/ik0hH3fEJss0M2aSwTT4iyJX4yAEprJdGtUxQlSkzVlBX5ZVBFKlJU33VJUpKkkKCklJKSlQI7yVpUCFA0KTVJAqRjR+ZWqQpaFOlaFLQtKxwKStCilaFJJBCkqCkqBHEFAv+IR28JgUApLFJSOEgcQKSAQUnQgguC7KBe40/Psunwg0OtCNK7DStd9vXFhq1K0e42D+87gw4iXckcxqwvyYaahx73jiYUDVIF61vWhtvSwpzNaabYp7d9Tozv8AHX+QPnFA2zG/1p/O8cTDWNQSRfe1KVoSDoN9gLilsBOAZlalncfJreZHWzwcO4dyx2IuTvrpoTrYO9zxMPXQWsampsb+B08BauLvbANcP09LM7e97m0OfPUBm5e7kQNGtFFUPYilwRoDqNTuRUUoBvXQgYkTPUWKTbRyQLadyzfCxivPbfe7sWbpe931e4ikWCCbCt9a1PLUk3FbEC1rVteiZ16gAu2xHPld769xHJ9ma/U3G1jd79bxRUzetCa6VGx1qTYg7geoqBiQTLgnbdy+oa/qNCG82o3MHQNbk1wHNgxbXTSKC2RyAANagHQU2UaVudh43oZ0zTd1JGx0JvsHubvZvK8VDd99Brpq7kDVt9xEdbQv0PMnewoANNNetd8TIWLC+3QN3Jb0FtG0EV5sNSC7Wu12YlzyYbBthGU1f7tDXS5162t4kEcqa5CFsbkMzu/933W6DU+tL/is/YHpttpyd7ADQRlsKINUUFjsKeZBsfwsSTXEwnJ5vdiQH+Funm/Q3sQ19DdzzuHAJ33fvbS55cnc1yfmORZqkcQIWdZcm8vnkriAVqDUwlcYxGQylgKQVt+9abDrYIDjZWgkpURj7+Xcx4lljHsFzJgs00uLYBitBjGHT9RJrsNqpVZTLKUqHFL9tIT7RHEAtBUgnhURGHiFBS4pQ1uG1iPa0ldSz6Ool6ccirlLkzACXZQQslKmBSoA63G0pwzz5K+J+QMpcQJMktS/NUkg5qiGW4l1yAiXUdyPljzqUpQ5ESuYNxUviFoAQt+GcUj4CDj9Knh1nbDfEjI2Vs9YQky6HM+DUmKIp1LEyZRVE1HBXYdOmJCUrn4bXS6mgnrQAhU6mmFH4SI84Mw4LU5cxzFMDqyFT8MrJtMqYElKZ0tJ4pFQhJJKUVEhUuegEuETEg3ePucc0j40MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGn97bLj9E8T+1UzwolszRE5R4DZeh5GiFhnGnoVWes1Q8DPs4RxeaTVcSxBHLeW4mFcccEvjcvRrQSxEvRqDr54lYsa3HBQIXxU+FSkygkEFP3qelM2pU4F1BPsJKgSeBUlQDFShGo3jTjysTzSnCpc0KpMDkIkBKSlSTXVKE1FWtwLqQn7rTqSSfZrp1pZKlLBw7oFwOVB6XJ+f60x1oXuR1L8wWDeTx04vUdHLdv5RPbGh5BR8bin0odMRrNu5H6/KIl8uqU+jP8ACJzYJNtzQeQJPy08fMYq9ugfrqAPf8PWBRBHx7k3+I6946a4w5VD0KzmmDaSHYRLcLNghJCnIVS/dwsWog0UqHcKYdxSgVll1kd73cNQQrDh9xbYdS/n2Fy2jR7wf0N32qlYTjmK/ZWzjiVQrDcwLxLNXhJNqp3tZFBj0iSqvzZlGnCyqZTyMbopdRmnDaeTwUUvFMPzCsoFfjqDN88Yhj9FEVmHlMKqKlBPxoFL/wAydPj86KFjsQiaTNMpV7oV+Ycv9YdR79DF4QtK0hSCFJIqCPp0I0I1Bsb4R9EEKAUkuCHB6dtj0NxHLCKwwhDCEMIq55mPb3Yp7B3GTtr5yXLcmQ5yzw5kMbDM584qziEddy/ltDzaogy6Ww4dhl5mzVEQ6KweX4CIb9yX4SKncdJ5Y+iPPK8rZQxPNVSUUqfYUMlYTV4hNSTJkOOLgQl0mfUKTdMlBDOlU1cqWoLjXH7RH2mvD/7O2X01eYJoxnNuJ006bljJNBPloxXF1S1iV97rJxlz04NgkmcpqjFKqUr2ns58nDabEK2UqlG472TOxDwD7HmVW5Nwsyuh7NEdAQsJmziZmFEPMM+Ztcao679smvuW0SqVOxI9+1luQsy6Rsltl1cHFR7Ko13ZnLuVcHyzTiVh9ODULQlNRXzgldZUkXPFN4R7OUVXEiSESQQCUqWCs+BPjf8AaL8T/H3GlYhnbGly8FpqqdPwTJ2FKm0mWcDQt0S/u9CZi1V1ciSfZzMXxOZV4lMCpqET5NMsUyPUOac25QyHJYjMWdMwyfLMlhRV2YTeNahGlukEtwsKhxQejo100SxAwbb8XEuENQ8O44QnHNMLwbE8brJdBhGHVOI1kz8sikkKmqCRrMmFI4JMlGsyfOVLkyx+KYtKQ8a9YnjGG4LSTK7FsQpsPpJQ/FPqpyZSSrZEsE8c6as2RJkpXNmK/DLQokCPC2fvaJZClMS5AcNsqTLOTjfeQueTp45ckynP3DAwZh4ucxzX/wDIYuHkqwQQ171Cg4O7MC8A8YqZaZ2YMSp8JSpiKOkQMQrG3E6aFy6SSv8Au+ymVgILrKCOE9L4548YRTTFScAw6pxUhx98q1mgpCrYypXBMqpqP73tUUirEJCgQqPME+7cfHnMD6lwU5kOU4RRIRA5cy9BKQkfuqXGT4z2Yrc7oAcUiMabKiVJZQCEp7Ho/BjJNAgCbR1uJzAzzq+unBR3ITKovucgB9EmUpQAA4yQ567q/GTOlfMJlVlJhso/lk0NFJIA2Jm1hrJ5UwuRNQklyEAECPj3e03xyi1FbvFDNaFE1IhI5uBbv/C1BNw7aRyCUgDlufqJ8O8nSQEoy5higzEzZJnK81TStT9SX6mPlq8Qs4zi6sxYk5v/AGU72I/3ZSEJa9rAchykQ3an48S8hUPxOzE6RtHKgZmk6WKZhCxQJqBuDemhxZM8N8mVFpmXaFIvaSJ1P6ewmS+Z2b4RdL8Rs5yC6MwVym2nGTUaEa/eJUz4HQnW8dm5V9oDxly64lvMsLlbPEDX/S/b5YmSTYISPuw0fIXISAQSAQVxkkj1Kt8SSFY+FiPghlOvSVUEzEcGnN+H2NQaymc3JmSK1M2cpuUqrkAcjpH3sP8AGvNdEQmvl4fjEh/xe3kGkqW0aXPolSpIYfvTaScbOI9f8NO35wXzopmX5yEbwxnTi0Nd+dqbmGV3VOK7qFIzFCNN/Y0JNDEOzqWymEhUkKMY8gOuJ6tzD4I5swoLn4V7HMNIlJWBSJVIxFIS5KVUE1Svaqb8iaSoqZkwuPZJVwpPaGAeNOVcVKZOKe2y/VKUEvVkTsPUSWBFfKSn2QButVXIppUsX9qsBSh7Yh34OYwrEfL4uFj4KMaQ/Bx0DEsxcJFsOJC2n4SKh1uMRDLiaKQ424ttxJBQsgjHT02VNkTFyZ8qZJnSlFE2TOlrlTZa0llImS1hK0LSbKSpIUk2IBjtyVNlT5aJ0iZLnSZqQuXNkrRNlTEKDpXLmSypC0qBcKSopULgkR5m409mTJnFJuJm8A1DZXzqoe8E9goZIhJo6lBQG5/ANd1EZ3/9GlUxZSiZtdxol2KYb+yOaY/aM+xf4deOUitx7CJVLkbxKmD20vNOHUgTQY3ORLKESM2YXTezRiCZoEtKsYp0oxuR7KSVT66mknD53beQ/FrHsnLk0VSubjGXweFWGz5jzqRBVxFeGVMx1SSklRFLMUqjXxLARJmKE5OKfOvD7M3D+fROW81Sx2XTGHCXEVAchI6FUSG46XxSR7mMg3SlSUPNE9xxtyHdDUQw8y14OeJnhtnnwhzXW5Mz7gk/BMaowJ0srPtKDFKGaVCnxTBsQQBIxLDakoWhFVTqV7OfKn0lUinrqappZO52X8xYRmjDZWLYLVyqukmkoWzpnU04AKVTVUlTzKeolggqlzACUqTNlqXKmS1r+QMKeQ3Gn5DbenyxwATy91dbXLvbUv5amPtW1Z7Wsx9S3O2nmIpqhrXCqeBudvvJr4i9Lcr3ieST1JuTe3JiTr5g+QitjoAOgZ7Xct0OuvNtTSMNSlE7GwFTanMV3rod+WJkzyXdugDXHIB3HuPPSwB7gq5HQa9QSw1Go5GKCoc6AGhtTrXrSp8KX5byoneoPRr2A2uddNLQ63vo9vg+789+0UFMEmw5G9QbilqA0rtY1vcbypmszkMHZ9Oe7aNcEdRZ4DS2/m+/0Aw5RSVBuEGiDp+98Ngb2JrQVrXbUdbxUoBJVMe9+C4u1u45ctelRcsd/N376t79i7RRVBU+8oA3FBcV8SBvQ6G/PTEwqd0pJ5EkA8tA/wARaKltWLEbMNzf97e2o7XvHXDtp1BVUDU7UuDSgpcUxPLnLU9+FiQQl+l3JJfVzbaKhiLh2STe+hsz8tmiC4hIBCQEig0HI3+nmcZMskqDkm5YEk6p4tenv9BAXUz6gkPfVPPz827RAeTZQrqD8jU/W36OMxB18vn9fyipuFFtQkj69fLpFud1Pn/ynGdLLl+Y+Yin7pPQf+I/CMx/syeKSpllvOvCKZR5cictRLeb8sQjzilOJkc3eEJP2INBJDcFLp39ijXkAJH23MrjgKy6vuevH9HP4kqxHLmbvCzEK4zKjL1UnNGXKWcsqmJwXFJiafG5FIlyEUdBjCqSrmpZLVeYJkwFZmr4NT/tEZcFPiWE5op5ATLxCUcMxGahICTWUqTMoVzTqqdPoxOlJVf+yw9KbBKXyo49Lo1shhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPjeIueZFwxyBnfiRmd9UNlzIOUsw5xnjyEFx1Eqy3KYucR/uWgQp6IVDQbiYdhB777ykNNgrWkHHq6mXRUtTWTi0qlkTqiaQHIlyZapi2G54UlhqSwEYeIVsjDaCtxGpUU09BSVFZPUA5EqmlLnTOEbq4UEJSLqLAXMfzxc65vnHEHO+cM/ZheVEz/O+aMwZvnkQtRWt+b5lm0VOZm8pRCSpTsbGvLKiE94qrQVpjUarqJlXVVNVNPFNqZ86fMJOsydMVMWX1upRjz8r6udX11XXVCiufW1NTVz1EuVTqicZ0xRJAJJWsl2HYRZUfeHXX0xhfunkNOdyP0jBXqO3zMTW7U8U/8RUfwGIlmwHf69CYjUXUOpUfcf1ie1qnxUflT8TjGVv0AB8y/wCnvjHVZhzKfkfcIkuwzMXDOQsS2h6GimDDPsrAUh1l5JbebWk2KXELUlQ3BOI1WKj3j62XMyY5k/MeBZsyziNTg+Y8r41h2YMBxakWqXVYZjGD1kjEMMrqeYkhSZ1JWU0mcgggOgAukkHxRm/L7+U8wRsnd7zjKCIiXvrSUGJgHlK+zvCwQpSe6th8t1SIlh5KSe7iwpCmILdLFulgNPpo/bJ9k77Q+B/ag8DcneLGFIp6PEq+RMwfOeCU89M8ZczxhEuRLzBhBIUZiKda51PjGECpCKqdl/FsIrJ0tCqnhj54EEVH69MREMW/X5tGx8V2H1Mq3LZPxJHP+JINu9a4/eHWhwieTOMssboOo5HmOvTcdbxeEqStIUkggioI0PhphH0AQoAguDcERywisMIR779n72FM4dtrikqVh6Ny3whyY9ARvFHPUO2z7+FhIhxS4XKmWvtKXGIjN+Ym2IhuDcdYioKQwLcTPZnDxSIeDlU25lkzKFTmvEDLdcjDKUoXiFWAHSlRJTTyOIFKqmeEqCCQpElAVOmJUEplzNXftTfaYwD7OeSxW+zpsYz7mGXU02S8szVzPZz58pITPxvGPYqRNk4DhK5spVQlE2TU4nUrk4ZRTZCptRXUG7jwq4W5C4MZEy3wz4Y5Yl2UclZUgUS6TSSVtdxppAq7ExkW+sriplNZlErcjpvOJg9FTKbTB+Jj5hExEU846rarD8Po8Lo5FBQSEU1JTI4JUqWLAaqUol1LmLUSuZMWVTJiypa1KUST+dHOec80eIWZsXzjnLGavHsx45UqqsRxKsWCtamCZNPIlICZNHQ0klKKagoKWXJo6GklSqWlkypEpCE+Z+0922cpcDVReTcotwOcOKXulJiJcp1apHlBTsOlcM/mV6GWhcTHKDrb7GXYOIZi1spU5MYuVNOQZje9/DTwbxXOgk4vipnYTlkqSqXUBIFbiwTMKZkvDkTApMuQOBSFYhOQuUFkJp5NUpM32OuPiP4wYXk0zcJwtMnFcycJC5BUo0WFlaAqWvEFy1JVMnHjStFDKmImqRefNpkrkmdhczxxVz1xWzA7mXP+ZZjmKaOfAwYp1KYKXQ/xFMHKJZDpal8qg0HvK+zQMMw244px94ORDrzrm4eC5XwTLNAjDsDw6Rh9Km6xLS86fMs86qqJhVUVU02HtJ0xa0pCUJKZaUITqLjOZcZzNXKxHG8RqK+pNkmYoCTIQD+GVTU6OGRTygS/s5CEBSiqYrimLUtVnhosfCSaHSuxF/xv47jXGRNku9ut7dux+OvOMSVO27+e3TVme/UPF8YjqUv0GnkDQgiupG/LngrktqLDZgH66Hfe/aM5E4NY7Bzr6jfv8dTckTAUA71TyJJP1GvhT1xjmQHcgDn9EfwtGQJ2znycADnp11do4rmAp94Gm1TbkTc/rxxVMgA2AP10HxfSKKnvufNz6ON+vui2REb3rA13ua/971NyDTpjJRJ0tbtcctrfBvOMdc1rktuX1PTZuXwLCLBExQob358qEaX1/wANyT9CVJ6fLv2HvPpGFNmvZ7Ne79Pd07C+vcfBXtScUuAUzbXlSbrmOV3Ylt+b5HnTr0TlyZICkpfXCtFRckkyea+D9qyksPrWiHEc3MIWHEIri2b/AA2y1namUnE6UU+JJlqRS4xSJRKr6csSgTFNw1dOlX4jTVIWhIMz2KpE2YZo5RlPxEzFkqoCsNqlVFAqYldVhFWpUyhqACAsoS5VSVC02FRTFCnCPbJny0CUc7vADtJcO+0Zlpc1ynFmX5iljLJzRkyYvNieZfedUttMQO4EImcniXEK+xTiCQWHkqbZjG4CZB+XsaU568PceyFiApsTle3oKlaxhuL06Vfc65KQFFF3NNVy0qHtqScRMSypklU+n4J69y8j5/wLPdAajDJvsa6nQg4jhM9afvlEpRKQtgwqKWYpP9jVyQZagUompkT+OQj6nirwqy3xUy67JJ4wlmMYDzsknbLTao+Sx6mykOsqNC9BvlLYmEuUtLEay2kFTMSzDRcNqn4+eAeSftBZKqcq5rpk02JUyaipytmmmp5S8Xyxi65JRLqqWYsJVUYdUKTKRjGDTJsulxWmloBXTV1Nh+IUPc+TM6YvknFpeJYbMMyRMKJeI4dMWoUuIUwU5lzAHEuegFRpapKVTKaYo2mSZk+ROw/51yHPchZlmGWJ/DpZj4B0dx1rvOQ8wg3Cr7LMIJwpT76CjG0+8aKkIcQoLh4htmJZeYa/Nj4reGmbvBnPeNeH+dqRNHjGDTv7KokKUvD8YwyaVnD8cwietMtVTheJSUe1p5i5cuokrE2jrZFNX0tVSyN88t5iwzNOD0mNYTMVNpapJ4kLAE6lqEcPtqOpSCUy6inUeFaUqUhSeGdKXMkzJUxfyn7PcOjahUm6qIoO8TUg91XM1oabY66NagX4ypuTqHutf1axtH3mfbpe5vtyY3t00NjHBUtCT8ak6qr3RU1Ar9406bW8Nb0V5IHAk6BuIsNW0D9NdvOAYNvpv7jblFEwjKVAFJVcak7AkWFBTpSnOuJE1M5QP4uHnwvv3JPN7jto1bM4G6h6No7/AKxFWlKUgJSkUSLAAUvfQD9a4yEqUVB1KLvqSdjzJi17jsf/AMPw25RDcFUkdFg87/4188Zqf3fKL9xs/Dp5P7384tbopX+1+dMZksukDcAP5vFPkkg+awYtztiL6pB/Xp+qYzpX7+llfw+u5i9IfXkof+H9T6nnFtd08lYzJf50+X/gVBJuB2b/AHS/y93KID+/9/GdL38vnFdj/gHwVFucFQetL+IUPwFsZsu3D2HvDRa34f8AZPuUD+vrHofsicRUcMu0Lw8ncU4puUzeZf5ITohwNNpl+aQZS3ExClEJ+yy2ZPy+bRAIUS1AK7g953CNkvsp59R4d+OeRcXqZipeGYriX7LYuRMEtCaHMqRhcufUKUQn7th+IzqDFKgEKJl0KuAe04SOAeKmAnMOR8dpJaQqqpaYYpSOkqV7fDSqqVLlgX9pUU8ufSo/1p4c8LxsrY/QrHn3DCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYqfbLcVmuG3YfzlJGn3GZvxczRlThpK/crCXAy/Gu5un63UA+8MG7lzKc1lr6xRsPTKFZdUQ+lp3g3iJXCjyzUygWmV86RRoY6AqNRNJGpSZNPMQdnWl7Fj1d4wYoMOyVWSUkibitTS4dLbXhUs1c8kC/Aaelmy1GweYkF+LhOl+1oOfdH9fwxrirU9z8Y04V+c/7XxEXBH3h5/Q4g/d8h8VRCv8AMfL4CJze3gj6LpiGZt5/KI1apbX8TekTm9U/2V4xzqt+aYhVqny/8Bi4J0RTmj6jEStFdjECtT3PxjrXi1k85ly6Y6CaW7N5GH4uHQ2ApyJgyEmOgwnVSw2lMTDpTVZeY9y2lSnyDbLWEqY6KYatdmFnYvu/ePT7+i0+1Yn7P/jkjImbMSp6Lww8Zp2HZexeorp5p6PLmcpS1ycoZmXPV/YU1LUT6iblzG508yKeXQ4pS4rWVUqnwIJV47beFRSpGtdyCBe33hSlT941pc1BlUgKdru7jRr9dPR7PsI/WcldyCWIJBBDFwwLg7h/Lo15iHAoddeYI5jne1NdKjECkEH+e3N+ly7b8ok10+vPtcmw1iXDvllV6ltX3huk/wASf+8ka66i9kTSZxlljdB1HI8x821EXhKgoBSSCCKgjQjCPo8iLg3B5jmI7S4K8H868fOKeSeEHDyXmYZsz1O4eTy8LChBy5hQXETOeTV4f/hpNIZWxGTibRN1NQEFEFpDr5aac+hhWGVeM4hSYZRI46mrmplIeyEA3mTph/dlSZYVNmK2QhTAlgeFeIuf8ueF2Scx5+zZVfdMCyzhs3EKspY1FXNBTKosNoZZ/wA9iGKVs2nw+gk2EyqqZQWpEvjWnfR7M3Z7yH2XeDuUODXDyGUmT5dg0OzOcRDTDc1zZmWO92ufZsni2EIQ7NJzFJ75SO83AQLUDKIMol8uhGm9wcCwWjy/hdNhdCn+ykJeZNUAJlTULYzqmbwhjMmqDtcIQESk/glpA/MR4weK2Z/GnxAx7xCzZOBr8Xn8FFh8qZNXRYFg1OpacMwLDRNUpSKLD5CuHiLLqqpdTX1HFVVdRMX5r7cXbJHBeXq4XcOJgyrinPoL3s0mrKkuHIEljEVYigC2tk5nmzKlLlEOtRVK4QidRTSS9J0xmz/gj4QftjUDM2YpChlihnlNLSrBSMerZKvxyiQpKxhtKscNVMAAqpwNFLUeCrMnTPxo8WhlGQctZfnpOZa2SFVNUhl/1FRzQOCaxSUHEapBJpZZJNNK/wAsmIHHSCdgmTMYiKiHoqKiHoqKinnYiKiYl1x+JiYl9anX34iIeUt55955anXnXFrcccWVqWpR7yt41U0uVLRJky0SpUpCZcuVLQlCJctACES0S0gIloQlISlCQlISGADMNKRPVNWubNmLmTJilTJkxalTFzJi1FS5i1rJUta1EqWtRKlKJKiSXi/QsXSl+XnqDfYiu4pWm9h86bK1bX5W7HY31G73fMlzWAc2tf6056aM53N9YjQKXsDz5Wpp5mpFK6m9MJckEszHl77N52Di2gjPRN699bm+u4107aARdmo4ilVH1NfzAFfE74w10/T3DnpyPkR7gIyEzuttObHX4NoOdomJjxrc2FgTUdampr5A/OsJp+bjmwt8SImFQwDnt8AN/R/J4LjxfUE8ya15/TYbmvImm/g4+VvnA1BNweh8+lufI9NIgux381utf8fA64nRT2/L7hft9GIFzjz3332J1059zpvaIiMqCK+Vxr6UtU60BPljMlym0D6eXX16A2taMZc1t7bE69fXmWYWOxiwxEXYgHT9frpyBJxnSpJd2fv8Db3XJ3jBmzX3YPfUnkXfbn8L/iueR+JWbuFmbZPnrI07iZFmSSRAfg4tg95p5pRAiZdMIZRDMwlUwZBhphLolK4aLh1rbcTQIUmHGcuYTmXCqvBcao5dbh9YjgnSpjBSFBzLqJEwDikVMhX9pT1EsiZJWEqSRcGfCMwYplvFKXGMGq5lHX0cwLlTEE8K06TJE6USUT6acAZc+RMdExBKVB7p2V+zD2k8r9pnh0zmiVpYleapOYeXZ6yol5xbkinam1rbfhFvJS5ESKcpadi5LGVdq0h+XxLxmUsj20edviV4eYl4dY+vDagzKrC6sTKjBMUKQlNdRpUApE0JJTLraQqRKrJTJ/EZdRLQKeokKV6CeHHiBh3iDgSMRpgimxKk9nT4zhgUoqoqspJC5ZWAqZRVQSqbSTXU6QuQtRnyJwFy498K2eI2V3X5ewk5rkTb0XInUqS2uMbp72Jkjy1gJLccEn7J31tpYmHuHC61Driw752/bW+zPS/aD8NZ9ZglHLPifkilrMTyXUpVKkzMXkhIqMSyfVTZoEtcjGkSnwtU6bIl0WOoopy6qnoZ+KJqNkvCrPkzJePIlVc1X9QYtMlU+KyyFKTTLJ4JGJy0pdQXSFX+UcCVqm0ZmoEuZORTmXipiEqbUttxKkOILiVoWkoWhYJCkrSoApUlQIUkgFJBBAOPzaqlTZMybJnSlyZ0lapM2TNQqXNlTJRKFy5ktYC5cxCgUrQpIUlQKSAQQN7pagtKFJKVJWUqSpJCkqTqlSSCQQpKgQQWILiLY7tXUlR/4aflXqcZMsMA2jJ96gYfXz+ukW5f3uV9OdqfjXGXL0Pv7bfP6aA0G91F9mcAe9/SLc593+6n64zkfmHn8DFNx2PxTEBwgJPOiz1oDT8KYzkaJOw4Yv8A3k/7PwB+MWx3f+1+eM2WGSObMfJ4p/5C/fjDe6Lc7Wo6JA/Xr+r4zZTfj58R+H84vSW9CfK36Hz7iLa7p5K/XyxmS/zpPb/wGCdRzt3/ACl/l9AtAf3/AL+M6Xv5fOK7H/APgqLc4QK8xS3gCfx8dcZssPw9gfd+sW/u9gfepvkYhB52HebfYWpt5hSHmnEmim3W1d9taTspC0hQOxAOPoU02ZImyp0lZlzZM1E2UtJZSJktSVoWk7FKgCDsRCalKwqWsBSVoUlSTopJStKgehBY9I2p+EudmuI/DHIWemi2FZpypJJvFttKKm4aZRMCyZrBBRuowMyTFwaidVsKudcfpd8Mc3S8++HeSs5S/ZhWZMs4PilTLlKK0U9fUUUo4jSBRuo0deKmlUbuqSS51jzYzNhCsBzDjWDK4iMOxKrpZalhlTKeXOV92nEB29tTmVNA5LEdh451Hw4YQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEI1n/8ApA2fmnJz2b+F7EXV+Dlue8+zaBCyAlqZxUjy7l6LW2DRZWuU5nZaWoVb7jyUH/SLp034r1QKsJokqulFTVTEvstUqVKURv8A5ueByuzvGuHj1XAzcvYYlX4kSq6vmofaYunp5CiHYv7KpAcWYtqY1yWtv7I/DHTitT3PxjXZX5z/ALXxEXBH3h+tsQD8p5HQ9iP1iJevl+sTWzp/c+RUDiGZt5/XuiIg8SehIPdv4RPa1T/eH4/Sv6tjHVbi68J8hb4t6xArY8in5JPzi4I+6joGyfCo/LEa/wB7z+cQkXPVRH16xNbFU16qFPEj8sQK18h8BFFliCCRwlJBBIOgDgi452v2jxRxcycco5lVEwTRTJJ2XY6ACTVuGfKgY2ABoC2IdxxLsOhVUiEiGUJWtTLndyJS+NL/AL6fwqZn3/ERoXbTmC0frt/o1ftWD7SPgPQ4ZmbFJdV4q+FSKHKWdhNdNdjWHIplIytnRaSpaZ6sdw6lm0eLVEpQWvMmEYzUTKWjpaygRN6zaeB3OorY18wNf7QpS17UxeQ7vobOR3ex0uwY9WaPRpE0ixY6N1f6256WJic29oLm1tzToaXHPQ6A74hVL1NtfrTqGv1IfbJCgpy+t3739+nIXi4w0T7o0NS0q5H8B/iTtQ/vDwNr4iLsAdtO3Ly9xcdsiTOMshKroPqk3uLOzm/NizkRtM+wv7LjGX8kZp7VmapQj9u56ejcj8LnoxIU9BZJlMahvNeYYBskoYOZszQYkTUU4hMciCypHJhVIlk8eMfsB4R5eEijqMxVMr+2rCukw8rF00kpQFROQNvb1CfYhRAWE0ywlpc08fjV/SXeNy8XzLgfgfgOIqOF5Zl0uZs6oplNKqsxYjTKVgWFVUwMqaMGwao/rRchClUqqjHaZU5K63DJYpc0XaM43yns9cIczcSZkhiLjoJlqU5VlD7wYTPc3TJLyJJK+9X3hYC2XpnMwwHIlqSy6ZxTKFGHttB4cZJq/EHN2GZbplLlSZylVeKVaEFZocIpVINbUt+ULIXLpqb2hTLXW1NNKWoCZHjt4h5zpchZUxLMVQlE2dJSKXDKRawgVuK1KVijpncKKAULqKn2YMxNHT1M1AJlxqzZgzfPc6ZinObczzSJnOYcxTKKm04mcYtTkRGR0W4XXnFEmiEAkNsMN91mGYQ3DsIbYabQj1IocGocGw6jwnDKaXSYfh9NKpKSmlJCZcmTJSEoSANVG6lzC6psxS5kwqWtSj5mVmL1uM19XimJVMyrxCvqJlVV1M1RVMmzpquNai7gC4ShCQEIQEy0JCEpBqQsXSlT9b/IDnevXxsmSjdw40trYW3+N9riKy52jfG3lv5dxF9YjK0odafiBS3Pem40FsYK5LuWte+1tT8bgxmy52lw+vmW5NpbpvrF4ZjiKX2sL9eleYsKfLGFMp3ezuP5ae52jLROZr/WxF/oHVg4uKI8Cl6AdK032Tr6jGKqnbTXb57n0cfrOmo8+2pHy7EbG8SkzAU+9XkdKeiMWewJ5egv74k+8Nvfu/yIgqYCla08qk+qf64exV9N+sDUO+pto7fIAxDcj7WPhtz6V3voPxkTT23c67cuoHKI1Tzcgt3bydy/TYcuttejSa3+uu40rzNeY8K5SKdmLMPLS/X4a894xlzX1L7/ABbXk4BfmNWaLO/GfzbEHa3PTz6fPGdLkgWLBty3O+9ratc6xiTJ1yHNy439x9Pq1hiYsEKvzB2Op8/r+ebLlOWu3xb5dHYM55DCmTXPfcX9LF+vnpt3N2aO0TO+zhxbkOfpeqJipC481KM8yBl5xtvMGUYx9H7Rh/dijS5jL0gTSRuPIUlqawkMldIV2JbXxPxF8PqLxCypXYHPEuVXpQqrwWtWhJVQ4pKQfu6+I/iFPPJNNWJQQqZTTZhT/aJlqTyzw+z3WZBzRRY3TmZMolKTS4zRJUUiuwuatP3iWQ5SZ8hhVUalAhFTLl8X9mqYFbXkoncpzLJZPmOQxsPM5HmCUy6dyaZQi0uwswlU0hmY+XR0M6glLjEXCRLL7K0mim1pI1x5a1tHVYdWVeH10iZTVtBVVFFWU01JTNp6qlmrkVEiYkgFK5U6WuWsEOFJIj01o6ymxCkpa+inS6mjrqaRWUlRKUFS59NUykzpE6WoEhSJspaFpIJBSoGMbPagyAnKmdxmGXw6GpNnAPxxSyAlqGnkOpv9rMFAr3BGF5mZIUe6HnouMS2gJYUB+eb+kW8DZfhl4wIz5gVDKpMp+LCKzGeClliXT4fnOjXITmimVKT+GQMUVVUeYpSzwS6iqxLFZVPLRLoFpTu94HZuVj+WVYPWTlzcSy3wUrzSVLn4ZOCjh00KP5zTCXNolWKkSqenUtRVNBPll0mljWgPQ0URT1AGvM10pjQJGrczblYG3k4Md2biztfXlr8/4xbnDfvV0qa9AKbdadNcZkoWNtWB63d/QEdxa8Bo3IBPqSfSx5xb3aAm/IdKAV18CmvOlfDNQL6de72HwPrFPkHIvZy3noNLxAetrr3L15qJrptY+FqXxmgWAG5YeQ/iPQxUdNh6cIt8B/JxFsdNCd6d4/qnUXxnI0A6j3sfnA+4Aepct9PvpEB0jvEcqAfT52/DGXJdieZJPezD4+sXCwJ/1fibe74Ra3Tr0AHqfyOM6WPxDk6vcOEfP+TiFwotsCPQFvO3xi3vKNFHofqQfWn61xmIGvl8/wBQfOKmwUOQSB/GLc7qfP8A5afUj1xnS7Hyb4e9h5ttAflI6J95JHq43tFvd/e8APQ1/H9GoGXKGu9yfRI/SKq1L3ZJPpofeQR0flGwP7OzNicydmyUSsqKn8k5ozNlh8qPxFL0SzmiGUBr7tMLmRphKh8JUw4KlSVU90vsJZlTj3gBheHFRVOyjmLMGXJpUfxKTMqJWYqdQBb8CafH5UlJA4SqSsOVJWBo7464YaDP9VUD8mLYdh+IIbQFEtWHTAf9YzKBayOSwdCI9043JjpyGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNM322GcXs0duzMMnWoLa4fcOeHeToW4+FmJl8Znp1NhUd2OzpFpINSFVOhGNevEioM7Ms+WdKWjpadPZSFVJ/wCapVGoHjLVmpzvUSiXFDhtDRp3YKlqriO4XWr1MYnEG58CPmB9cdefXrHUpsR9WZ9uw+ETUH4q8yD5EAfniEuARsHA9QSfh9a2L1Fr3H6fGJ7ZoANyDToQbedfr6xr0+t7fOI16vpcH129+sTmzQ+Br6gg+la/KorUYq+fMN7wR9fpGOoFtb6+YJ3vy1+MT0EUtsDX+6dvX6YjLvfe/reIle6xHUEf+mJzRNPE19UjTxUD671xAqxblb3lvc3wixbEf7P6kX6Bvh0j5fP2UGc65YjZQQ0mPS39rk8S4e6IaZQ4Pue84EqUlmJSpUJE/CsJZeWsNrcQ2UxoX7OYTs7KB3BPY6G4PTq0bUfYx+0pin2WvHfK/iImbWzMoVswZb8SMGowJpxfJWLTZQxCbKpVqQmfieA1MqlzFg6UTaabOr8Ml4eqql0VfWy52PVxL0LEPQkS0tiJhXnId9lwd1xl5lZaeaXSoC21oUhQNgQoa4+jrd20uDrysXFyS0ftBwfGMNxvDMOxrBq6mxTB8YoaPFMKxKjX7WkxHDMQp5dXQV1LMAHtKarpZsqokTUgFcqYlRDGJLb53IpQVO2t6gXBrYEEDU4oxAIAOmm2+h5alla6MHj7CJhDEcnZ9idue+nO+jR9dk/Ls3ztmrLWTMvtpfn+b8wSfLEkZVUodm0+mMNKpc0sJClKQuMi2EKKQV0Pwg4vk0q6ufIpZABnVM6VTygQf85OmCXLfdipY1GjsdAcfGcdoMvYLi+P4osy8MwPC6/GMQmJI4kUWGUk2sq1h2SFJkSZihxEJBYKtH9Erg5wzy7wX4XcPuE2VELGX+HmUJFlGWuvJQmKj0ySXQ8G7NY4NjuGYziJbfmsyWj/AEa4+NfcSAkhKdysNoJGF4fRYdTA+xoqaTTIJbiWJSEpVMW1uOaoGYtrFa1ER+WHPWcMV8Qc55pzvjaknFM1Y9ieO1ctClKk0ysRq5tRLoaYq/F90oJK5dFSJV+JNNTykqJIJjB17U3je5m7jLJ+EcseUJDwqlbUTNQHFBEZnXNENDzGLWW0qKFNSnL65NBQ7i0pfZjYueN3ZcbK/Rr7LGR04TkyrzfUoBrs11K0Uh4Q8nBcMmzKeSOIhwqrr01s6YkEoXIlUKrLSoDza+01nNWK5wpcqUyyKHK9KhdVc8M3GMTly6iaW/KU0tAaSTLUQFonTa1LlCkmMaMNGXBB0Guvypt56W5Y2YmSm25sNdNG0OjkjXbSNcZc0Br77czYNzB3v83v0PGbVpz2rfSoFq78rDW+MCZId7DS3J92v8tthpmy51g56c72e3QbW3NhreGI2m/Pz/4aa2N+pOmMBdOQSw23D78nPLr3G2YiboxG36WOunS/J3i6NR+xPjv56Vr8r02xirk809iPncX1015CMhE9mv6nXzZm5P8ApE9EeOe24A1vShSPl+OIFSASdPRjbqSH8ifhE4qPNr2bXyPvaJAjhY1FacwD/wAtsW+wHMev/qi8VHU+/wCYMfhjrGhv0IJN/wCzh7Acx6/+qBqBrc+Z91gIjrjxc18bA1FOXdpi9MkDqOQ/V29SPhEap/lycjTe+2uwiA7Hkix6fMC1vLntSgxOiSdks+pPyY6eZ7DeBc539fI3199mDE9otT0brU1/Q2oKc+gFLiuMtFOd7/T7W6bWDNYRjLm63Gt7n3nftFliI3W+lv18NxvodqUvjPlyG2a/e4Omr+v88WZOcFiOnU353PI/DeLFExYIN9q+I2raw6dN9s2XK0DPfuzEddeml+djgLmM/LqbOG7D03jYa9k9xxdz1wczFwknDpdm/CObMrkrynCoxGSs1vRkdAQ5SpSll2TTyGncMpSfdsIlsZJodtvvMOLXoB9qjJKcDzdh+a6RITSZrpVprEBLCVjOFplSZ0xwAAisoZlFMALrNRJrJiiy0hO+H2Ys4qxnKlfleqWV1WVqpBpFlTmZhGJqmzpMsgkq4qStl1kskMgU86klpDoUVe3O0blVrNPC6fqDQVHZdT/lNAOjVv8AZgWJglVLqbdk7scFJrQuhh4gqaTjyT+3h4Z0viP9nDOc4U/tMZyCiV4hYJUJB46f9nkTTjyF8P4l09RleoxpK5RIlipRR1awpVJLEb1+DuPzMCz3hSSvhpcaJwSsQdFitUn7mQ9kzEYhLpClbE+zM2WGE1UYoXVVJ0NSdyD8NhSvXTkTQG1/zdoHw+N+Z2A5c943uIJ82H625s/MWEW9ehFrkDlfUgX8evxa2xmy0sBrufLkdd332i4/r6Cw59dz8zb3D3q21BPrWnhUX8xXQYzZQue4HmLkH0t2LavFA251IHYDUfE6Pr1eA8dRTQ0Brr3B+dqDrpTGWkXSL8/ruB7x53D947mzNuS9vQ+7WLa4b6XsPH9DXwxmpFgHsAS/v5+WsUto/wC8bi9hYH42fvFudP3tKEq+ZoKbadT90864zZQZIO5AP113frFyiW7EB35D9XL9vK3OG58b+QqfoRjNlDmNBr3NvUC/vvFAHB8gOVyPo73veLc7oRofh9bE+tDXGagWDbn5tF6jY7OT5EaevD7+l7e8bE7mtPMgD17o9dgK4zUb20a773HwP08GDs+4H+6Bvpqz6aHtFudNa1tRVPIDXGbKAAuNQfer+O3MxQ6l7hwPUj9COdgO2YP2Vk6dclfGXLy3CWoWYZOnLLP7rbkfDT6BinAP4nUyyDSroyMer/8ARu4tMXhnirgaphMqmr8rYtJlE/hRMrafGaOpmJDazE4fSpUX/wC6T0jVb7SFIlNVlavCWVNk4rSLVuUyJtHNlp7JNRNI5cZjLfj05jWSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNFb2oc9GYO312kY1CypEJm6UyNI7wUEKy5k/LcheSNQB9olzyinUKUoGmmNaM7TPbZoxdWwny5X/AN1TyZR96CLRpN4mzhPzzmBYuE1kmR/9xR09Ooa/3pZ5eseEEGhHKtvBW/qT6Y4edvQ9xZvQD1jgC7B97P3BZvQD1icjQc6fIH8K4iP5j1YPazhtOpuWvY84sWLA8j9H3RPbNxzBNPMWp/eoT/WmIVflPaIVgsez9gDp7omtn6VpzI2+vpjHWNNLFn2117W98RLAuNr3/wAQH6W1i4NEd0b1Iv0I/wDer0v1xEdebW9LfBv5xCoEsdPw6dbE+57a26RNaPWoCb73SbeZ1r0PWkKgz937vr6Ee/1sIBH1dxf0b3+s5s0ppZVL7A2+p16+NMdYu/MRCXI7Ai3MF/RtO3r5B7QuSDLJlD51lzQTBTd0Qs5S2juhmbJQSxGKCfhpM2W1BxQCVCKh1uLW45GCmdTTOMezNyi6BZ+E6jiN/wAJLdmDWj9I/wDRAfaoVnTI2JfZszhiE6dmbw3olYx4fVNZUe2mYn4eTalEqswGWZhM/wBpkrE6mUmjllcyWnL+L0FDRyqekwBQPnJp+lyanbcU1sajTc1saigOJyCNBbqGIZtRt01BtcR7YomG3a9+pfr0cMTfXSMmPskOHMHxM7evBBqZQ32uUZEjJ/xPjWSkEJjck5fmEwyrEkqCgkQed3Msxlwe/wC57ie4paVp5l4e0Ka7NuFcYKpdKqdXKSdlU0lcyQeyar2Ci9/wgAh41a+2xnCdlP7NniEqknexrsySMNyfTzAWJp8wYnS0uMygxD+3y8MXkAhmMx1AhJSreUejoeXwsTHxay3CQEM9FxK7VQxCNrfdVcjRltatQDTWhNNqpMmZUTpVPJDzZ8yXJlA7zJqwiWPNSgI/O7OnS6eVNnzS0qRLXOmHlLlpK1nUaJSTqO8aYvEHiDMuJPEPO/ECcOBUyznm3MGZ4tKVlTbC51NYmPRBsFVCmEgGXm4ODaACWoSHaaQEIQAPajLuXqXLeXcDy9RJamwXCcPwuUWZcwUVJKp1TpoDgzp65ap05bkqmzFrUSpRMeOuP47U5ix/GserFPU4zitfic0BRKZZrKmZUJky3ZpUlC0yZKABwSpaEgfh4RZ4eMpS4Btvvbr5jSopagxmTZDvbnbUaG/6nTubxhondunu59zfYkO7WvLEbpfXqK9RSmhNuh0FxjCXJPLdh27l3Yerl2N4zETnAvyZrnXfsb6ciSLxd2Y7kSQAdaX515bEVPOwOMVckFw2vkdfR9b7APyjJRP63+XJrAvfsTFybjhz6VsSa38vXQgg2virp+Y62fp5uzWfbtGQmfo5fc6/CxJJfTzG0S0R4FisAV/l6c7itNfAX1xCqmf93zYv8/jEongvsw13fyfS1vgIr/bU8x/vJxH91P8AdPof1iQT9yq/f5Ew+2pH7w9U4fdTyPof1gZ3JXdz8GMR1xw071aVp938L8tSD6YkFO23oDf0AiNU8bbhww5fz2G9ohuxwNaK8zQV01A8ufPpjITTtYB/XbU9ex6CIlT9htzOzPrfmUtvaLY9Gg1+KvmKHS1vGlR1FgLZCJLNa/Qd/IWe3axMYy5z3vytqA242Op8zZw4tL8YL3rXw6emlhoKA2JFMuXJJ2LM+40bU+rs29mvGKub1Zrtvo1ztb3RZYiMF71FtxYEm5+t+laWOM6VIfa/YhtAPdpv3uIxJk5xbqz207dOTAWHSPevswOJkXkntd5Rk6IkolfEmQ5nyLN2FKPu3veS5eZ5O4hJPcEU3P8ALcsaZeKfeJhomNYbKftS+/0V9prLcnGfCXFqwy+Kry5XYbjlItKfxIKKkYZVpJ1MpVBiNUpaPymZKkTFD+zS3d32cMwzcH8VMLpAvhpsw0WI4NVILsoKpziFKQHCRMFdh9OlKmJEuZNQktMvtIRzDEZDxMHEtpehoth2EiWXBVDzDyFNPtLFbpcQ4ttYBFQqxtjyvr6CjxWgrsLxGnl1mH4nRVWHV9JOHFJq6GukTKWrppqbcUqop5syTMDh0LUHj0xkzptPOk1Ehapc+nmy58mYgsqXOkrTMlTEk2CkLSlSSdCBGEWeQC5PNppKHCVLlcxjZctSqBRMDEuwxJFqFSmq0pqepp+SDM2X52V8z5iyxUKUufl3HsXwOctQZS5mEYhUYetSgAGUpVOSWDOWAA09MMNrE4jQUOIS0gJraOmrEAOQPvclE5IHYLsQ5F35xYHVWAGoHKt1G+96DU8iTuMfPQGfr15fAm9ttIzSwPQe/wCdztre0W9ZFSdgCTUW0oK9TfTrblmygWHPTU6na5s1hyNt3czC/T1N3HRrNfXbSLe8q/yNTuqpPjuDf+IUpjLlg8Tv5t2CW+fcPvDQe/m+wtvd+Z1Yavb3FD4vAkV5moHTc77HGYkP2JCWHJx8LesVFyOQAffqfJyduTxbnCKU0oeegFa/OtdLg6YzkAAW5W2d7fDTfTUxUnRtwT3J19zgbuG5PbnTbW/P+0aGp8KnyPPGZLDOeZDBuQAa3PSCRpbVz5AWI8z8Gi3um41p8Sjf0rz1PpjNQLpH0+vxirflDcydrEh/mNi/lFudpXlUgeBArvsCSL10vvjMRptr/D5P56CKh7O9gSW3d203Z+0W9ymh3rX+8fxOM6WLdmHp/Fj8YoG1bcm+rAA+rkHlq1tcmfstJwpnitxJkPfomZ8P2pwpupuqR5klcElVND3RP1iuo79N8ejP9HNiSpPiNn3BgpkV+SZGJqTupWE47h9MlTb8IxtSXu3Fs99eftGUwXlvL9Y15GNLpgf/AOcoKiaR5miB6tGcLHr5GoMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaAXbmjlzDtn9qp9w1LfaA4rwIIr9yW50nEtbGmqEQqRpqmg0rjVvMyuLMONl3bFK5J/2KiYgD0SI0VzuszM3ZnUdU47iiR/8A2aybLHuQ0eYknTw+mteWop05Y46oXJ6/HRvQv19Y4moO55+VlCze9+vPWJqDXyOvQ1oPWhp8qjEStQRu+mvcdxYnYREfxIPZz5XI/T6MTWySAOlvFNaV6WviM2JbTbsbiIy7DkPn59PV4ntq0PLn4UrT1tzBvXGMoaj4d+uj7P3iE2DHX5g2PoWvsUt0nMm9LA0oATuLjTzO9bU6QHy52ffXXty56M0QqFjqzvzLEXb4bMO95zaqEai4URpY2NeVNac611GI1jfmG68ww66fweIxuLdD57c309+jxObIrTb7vPw9QfzNsY6w47X+voxEoXP+8O41a29ifUxDnsjgczySZyGZpKoOawjkM8UgFxpdlMxDRWCgPwsQ2zEsKUCEvNIWQUimLULKCladUnyIL2Ouo4gbaR2H4Q+KWZ/BLxPyV4q5NnplZhyTjlPi1IiZMmyqfEKbhXTYpg1cuQpE7+rMewior8FxREtaVrw/EKlCSFEEYyswyePytPZnl6aI7sbK4pcO4ruqSl9qiXIaKbSr4vcRcMtqKhyDQsuoJNa4+ykpmJCkkjiDgg3Gx8wzGzR+1/we8VcreNXhnkvxUybUioy9nXA6fF6NJnSp8+gnlS6bE8FrlyD7MYpgWK09bg2KSgB7LEaCplFIKWjNx7AaVpmHa/4hzFxAWmRdnrNEW0sgHuxEbxA4ZyxIBuO8uGi4yhGyFihuFdneE8kKzFWLKQPZYPPWG0Cl1dFLYciQpVg4NzaNR/6SLEFU/gflikSoj+sfE7B5K0/3pVPlnNtWSf8ADNkyXIs5Ta4jaY7SWYV5X7OfHzMTDim4mTcGeJ0fBLSTUTBjJc7MuUFA1TWOMOkrp8Ne/U0rjb3wyoE4p4kZAw6YkKlVmdMryJ4LEfd143RfebHVpAmFt2bd48FfEeuVhnh7nvEJZKZtJk7Ms+SQSCKhGDVn3e4uHn+zDjR3jTVh4ugFFct/Cg+9rUeHnj2kmSX0uw110fpe4t10tHj2ic1j5X0bS/MdfIjSL1DxwtVV9zXw/mpavWhF96Ya5OxG3LvruNRfludYzETdLuH+n/XVrbxeWI3Q963j4/zWqNTzB0pXGGundh077227W69YyUzjYufWzevk2w1vFzajyP3j5n8e9Xnev0OMVdOC7i1/P3NdtBr1jJTPu+3dzppz38nuNYntzDT4r+Nr+YrQX33xjGm7nf56MRvfvdonTP2cjTr8eW7PEtEf/NalrmnpX6b761iMgvoPfoNNND9cokE4WLhvN/UW9A3KKojhuoU6G/zXi0yDsn3q/Q/CL/b21/5vr0aPwx4vRQp439Ar6bYewO6f/F+nyHSBnjmf979NfSKS4/8AmseppXwr54vTIL/lHLS/vF3iwzhzAew1fk30NIiOTDfvf8Qtp1NL03GnPEopyGd7dPSzD62aIlTxu56P6v57HybSLe7Hg/vddaC3P4q+BO+thjJRT3snW2ndtgPntYxAuft9cu55873GkWt+OF6q1qKWvborf0IrvjKRTtqNGb9NLe5g12ZsZc7mX18/JvotdtbNER1RTvAUrShPWlq8tN6W0OMyXJ5BtOvnoPXdhfWMZc2zu3NixN/Kz395YuI7a7M+a3MrdpTs/wA9Q4UIl/GnhiuKKSarlr+dJNCTNoUJJL8tfimfBw1ChUHiXiXhScT8N8/USkgmoyZmYSnGlSjBq2bSqJNv7Oplyl7XSzgsY5R4dYmrDvEPI1alRCZGb8uGaQ7mQvGKOVUpcX/HTzJqCdL3BGu6s8qhIrQiqa6WCviV531FNzapPi4LgHnHsKbEjlGHXjFDJgeKXECHAIT/AJVziJSNgiNjHI5CQOQTEhItcUqSbH8u/wBp7CRg32jvG+iQOFH/ALS811stLcIRKxfE5+Ly0JZvwol16UpAuUpTc3VHof4d1BqsiZRnk/i/qDDpKi5PEump00q1E8+KSSeSjpy6rdVtW/1JFehtS1d9TUW6SQLi1umwG3JjuNW6a8x82G/1/EXAiCtVAdBudNE17t7itxTWtNBQVzUhhroGt118tfc8XNcJ6382floBfzvFudVXTfa2/wDS3iKVtfLlJYP6a6egd9+R2vAuXv68gzORYuQ1t2YveIDyrUpvW42Gx8TWleY0qaZcoOR0D2O55dQCH7FwbRVLlyzuW2e7kt5dQO8W51Wt76b35725HWvnjNQOnXpaw+fmA2kUN3630swsOw1826mLe6dwfTS3wjTzNfDnjNlpYAer9bnTfsOtovA1HkNO6m9WsOTgNFvcNSa1pUDyFyfkeeltcZksany+vQesUNySNdr87Wba59x5vbnSb61p4/eNd+VL8wDuRjMQA4Fuemrbt6fxiuxI0sBoGAs+o3dvKLe6fvHlW3hb5E19NMZyAbdfiT+gHqYoA3MOydtTc/He4eMivsvP/wAwGcL1I4Oz8GmlRnTh+fW9D4DTG/n9Hd/+ejM+oB8L8cIfl+1mSB8ifPeOh/tEf9isM1/7VUQv0wnHD83jPJj2WjTOGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCP5+vbah1QvbK7VrSgQVdorjNEAHUJi+IWYItB8FpiAodKa41ZzICnMGOA6/1viCh1C6qaoX6Ai3UtaNFc5oKc25nBDPj+LqvuFV09Q9XfsR5+bGyKV8/Ctulhep5U1x8FYLjqG+bfBhzjiZvbl+Hu36sGHN9N5jRrbxHgbkHXX+tMQq0fl776HodxEY1IvbTkx+m7C2hia0r8xtY6+FqYiO13O937X7Fu4MRsQSPLqd/ewbvaJ7ZtS1rcyKaV2pTX+Y8jiFYv/LoPXTy7RCoXPViH0trZ+THQ2cRMaVfnvTqNjUitRYakioub4x1BvhyBB/Q63YG7MbRKDHcPbrfTt7hfoIuCToda3vQnum/Qa+FhzGIyNt/Qg/KIjY+6zgcrb6M+t+Yiag2F/ukA16Uppp3q3Na1p4YgI9/Lr35afwixYs9ufRruO2zdOV4mtquP5rgbAjXlqK7E2NKi2ICGJF/r6f9IiUHflz3bnpqDZzuw1BMeau0hkL9rShjPEsh1Lj5G39nnCWRVT8lUsrbiykUUVSp9ai4pFT9iinnXT7qCSUZtHN4VGSo/hU5SDsrcf7QHS6Wu8e0P9EP9qYZKztiX2b84YlJkZa8RKxeNeH1RWzPZIw3xAk0wl1+Ay5ymlJlZywunkGilTloCseweko6Ljr8wKlzsg//AEfSZNs9q7i9AKICo7s6TpxhRVSq4Lidwvq33eam4pxyxp3WlVrWuO4/CYgY9iCTqvB5pB6oraFw7t+8SwFmZuXpt/SRylTfBvJM9LkU3ifQIWG0TUZTzcOJ9glclKG3MwaMQdmftgQz0d2Tu0owwFKdRwP4nRoSknvKRLcoTaZutilytTMK4lCE1KyQmh7wGNw/CKoRTeKnhxOmEBAztlqWSdAajFqWnSSdAy5qSSWAZ3DR4O+LElVR4X+IctAJV+xmY5oA1Ip8KqahQDXJKZRAAuSQBrGmpDTCw+LlvQ/83T9UNfZZE7Y30DG+77i/La/dz5ClA21+vr1bYRe2I8Gnxaa1Pht3qdfHyJm/AvoX3/lZ2ufQD920KUn4fXr6Ns0XVmOpSivRWvhVW3I28K4iVI5aM7j+XxDxMmexu999O2nPf5sIuLUwI/eB89deStefyxjGQb2t2Y28rctWblE6Zw3IPMcn68vlyiciYDc8t6mg5fFpy1HzxCZAuOEvt/MD3fQmTOPPo4uOu2vqTuYkpmI/jGtqk1/5rXxEacDlbZv/AExeJwfXTQBwO+hPw0isJgCB8Z/3qfVdfXD7uOl/rk3pF3tyf3gO5L+d4GYAA0WfWv0USOuH3dOtrfWnDeHtj/efsSfgTFBUwT/HpyJ+fx4qKccgen0mLTOGxt2JY9LDXz0iM5MRoDXWwPpX4vy6YlEgacJ8wPn+sWGbu576dLcn8n3iA7MCa/FQeNetAe94/qpxOmQXDjRtveSw+fS8QKnAXfbQfT+nS0W16N1Pe3533t97XfrXUDE6ZATqG3fd32cX7huvOIFTuWvr1fbt0u+0Wp+PAr8d779P7Wg2rpXlTEjoRyJA/TsT5tzaInUv67/q3o8fdcD0vTrjtwRk0N3lxE34x8LpVDoQT31PzHPUhg2UppUhSnHUAUBNdBUEY4lnqtRS5JzlVTCEy6bKWZaiY+gRIwWumrJdgwSg23FtCI5PkqlXU5yyhTS/xTKnNWXKeWA4PHPxmilJZt3VbW7NpfeafcBUs1sVE+Ve93RvW5ruLlNBUY8TBYDsI9lzcnuYxBcbopMRxYz84gghOZItg3BHvIUNQqxufhcZWDyINDUUP5j/ALWlVLrftM+Ns6UXSjPuK0ZIL/2mGy6fDp42uJ9JMSRa4Ym0eg3hnLVK8P8AKKFAgnBaecAR+7UKmVCCO6JqdNY6gWok02H5Ene/+7S2lRQdAykjVuXrt6b7vqTHOufqRo+jX1PUbgekF1dPGmnSnwjal7kVN6m9yMtKXIFmFn2u4O9/TRj0Nb+avr36P/iEW9Zuan/E668uvLwGMxIYdrt8rfLuTqYp0Yudumo/W/TrEB1etNBpypoDqdTXzrU3NMuUki5N1HfZ+dg1m/TSLrB2/wANzoTq/kGBFrRb1qqfOlep8T/jTwGM2WASPJW2gsl/jbRuetBq/IOH3YgD9Lcm5mLe6oXPLptoNCdddKmtRYgDNQPd8d7HcaOLN5xfpzJA6n8SvoevMxAcIpTQ+e9yRroAaDn4Xy5adAe+nncd2B0taKC1xoLnTU2G578rvuGtzqt/FRFedk25HUg6UFN8ZktLnTkB9dPdA2YPoCDqe47a3HI7piA4aevyAqd/EaUJoNjjLQH13v6sBr5P5wFmfk+pFza/k515sNIyL+y6P/3gM3jnwdzAfXO3D63Sm39Mb/8A9HiG8aMz8/8A2X40PTNeSfm5PUmOhvtEf9isLF/+1FEb9cJxs3Hnt1B0jPNj2SjTSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNDL2k0jVlzt39pyXLT3DEcSo2fhOgKM0S2W5lSul7uNzYOE2BKqnXGsucJRlZmxhJH5qtS/OchE9JZtxMD7kRpH4hyPu+dcySyGKsRXP8qmXLqAR3E0E9+8eKmlbW5eVtem3hWgtji6g47X+uvLrHB1C56hx30LNu1+4D2ia2qh6n6pr+RxCRqNm9x5+vrESrEEae9iHHnt3LDWJqCAa7a+RrXzrW2ImsRvu+zaN5WGr9ALxrDEHR/lv9conNq0Olu71rqm3yvqTzocRLDjtf8AWI1cwNLjtuH5a928omoOnqKHcC9PpenkcYyxv5Hs/uboD1DREob+lvMeln0azWaJzSwoUqDbl+6RU7AWOtdqb6xkHd9WPfvEKhbvy5iwHWzswHXpNaVSx0sDrvodhrY03vYjESxf1I8mcfMctA+1mobcD1DBwednPTQagCYhR0JoTSnMEX8aEnS1AdjXEC0uH5e/6EREXIZ+VnJG4HUG76i5L713WoeLYehYpluIhYpl2HiYd5PfaeZeSpp5l1JstDralJWk17ySqoNsR31BIUCCDuORHbTzEZWF4rieAYrhuOYLX1WFYxg1fRYrhWKUM0yKzDsTw+ol1dBX0k0AmXU0lTKlVEmYx4JktCmPC0ffeyQa/wAy/tJZJkp5akS3iVw94j5ey0+64CIyDbk3+XjEMXFULkVCJyRGQTzawHHYmFDyEKbdaW52z4WVqU5mp0kgKq6SspSl2/tEShVbk8QUmlJTvcA3EfpVzb46UP2tPsCYd4oSlU6c15PzDlil8ScKp5Xsf6ozfQVErLmJTpVMCtMnDMaRmKhzBhSpUydJk4disuimTU1tFW09Pt5Z2y+3nPJGc8nPAOM5tynmTLDzZIAcZn8mjZS42SqwUpEWpJKqggmpIGNqcFxBWEYzhGLIPCvC8Uw/EkKv+FVDVyapJDXcGUCGvyjzCxnD04tg+LYUscSMUwyvw5aToUV1JOpVA90zSL25xomqefgYuJgYpK2omBiH4SJZWlTbrURDOqYfaWhRC0LbdQpKkKSFIUkgjvAg+19PVInypU6WoKlzkImy1JIUlSJiQtKgQWIKVJPECQQQQWaPGGdTrkzZkmYlSJkmYqVMSoEKTMlqKFoUCxSoFJDFiCCC1mubEwrT4q1pubaX1pawqK9K6DNTOt6nmOz97nR/UmApO4226dtG1ux7GLuzMiB962ouRUHlfYdb89sZKZ7b9Du3nzsNrFjq8RlAOmr2829wfQAcupuTUyr+9YEbn5XsfGmtgbYlEwH8wDl/kC7X2253Ooi3gIYg7WLkP21fTU/rE9EeDQFVCBzVXfrU/LkK4ueWbjm1228hcWt5PB1jc32Z3b3fyfkYkJjhaqqjf71deYJGmnlXlgZaC7Kt6A22sfrTWK+1UPgNbHqDy+jFX7cP4z6n/wB7FvsUbMfQfECK+2X09I/DHAarP/EfW5t42w9ijmPcfgkiHtl8x6RSVHUt3hfl3geupH65a4uEtAuVAD1HY2DdPf1GYouz9rm/TbqxtYxGXH0r8e/81QOu/X8dsHljYH08tBfrodWi38Z5uH6dQ4t8eWj3guzH+a3iRpY0ub1NK3F9RbFpnAaABrdbg7sTtbQ3aAQTvvq293v5adyCYtj0xN/iNthXf+9/Q7d6mIVT3cvz6XG3utfoWGl4QPVwH2tvtvztbTU2d+YG/wAXoTXexuLim1d9wMYyp2v8hps9+9xvs8XpST9dB6nRiSLesevvZ3ZbVnrtsdnyVBCnUSnO3+WrgSCot/5ASuZZ0ZeINQEtxcihrnQ0CSFUx034840MJ8Jc7z+PhVVYQcIS9nGNVMjCVpGl1SayZ3a4YFu3PAzCDi3ivkqSUlQpcW/rZVgQDg1PPxVCuQSmZRovZiRuwjc+ccJqAbU51CQb0reqj5062r5KgOWGpsI9W9IwuZ2mqJxm7NU2QrvomeY53HoWDXvJjJlFPpVW4PfS4CCTShG1MflJ8UscRmvxR8R8yyZgmycw58zdjUqY/EJsrFMfr66UsK3CkTkqcaghnBj0ny3RKw7LuA0CklKqHBsMo1I0IXT0UmUoaW4SguPXVx8e4sAEVFNT4W7oFgL+dRT7wxw5KWA17/E+T/xtH2hfl12uz7OW2Ye4mLe4v1v60pyoQB8xS9KjJloA9x67t+tub6Egix1e9y2oHfdxvzYvrEJ1VAb9COmpOoOn5igqTlITxEC3MnpozsRc+/qLVHM20bk+g12De7eLc6rb09LDTa1dj6DGchPL3bXBO9n0DPuIqeTvqOr7nnfTd76C0QHFH50Nb9SfIWqdCfGmXLSw6nTs1g30fcIqkaPsyraudB1/kNNYDqhuRa58NtNLj5DGYhOgAf17t8tyH3gdhZ7k6b3LvsNW3AHcQHVE2JAvTrcgm/oB1TyF8tA3+uXrc+RHlUc21udWAH5dHA2J5XeLc4oUr/FfrTYX5/M13Jxmy0sL9nHMuSfSw1a3aKO501sDfa537bM76teA6q5G33d/Ek11t8zfXGXLS5FtLiwO7BvMnVtAdou5aMTy2GjkdLh76DYxko9lrBOu8cM9zMD/AEEHwrj4Fw7B2Y5uyi+wOlUSt8i96G2PQf8Ao76OYvxZzfXgf2VL4dVlGthb2ldmXLM6Xf8Aw4fObnc7Rr99oqckZSweQWC5mY5E1Ox4ZGGYmhZblxVKPc8Z28ewsadQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpKe2Ty67l/2gPFiKcZLTOaJJw4zJCLUCBEsO5EkUlfeRspKZhJIyHJFfiYWKWONdvECQZeZ65TECdKpJyXGv+TS0EjW3EhY2uI078W6cyM84mtiBUyKCeg2HEDRSJJUD0mSlJ/2dWjGGhXU0018wfO2tr33xwg8+Yf683jrFQs4Fxdtbbj0iag6c/wAqC23K23gRiFQY/W7m+53vv3BiJYcdDvze4ffze4tYgxNQoEa6X8QeYG1tTppbESgxBG7D3+d+QY7lnEWH8SevwI2v6PExtexP5706Hztz2OIzr3uPP4to+8Ra/G/vv7/Vr6zkKre1TWviKWoQK2ptoKnXGOoMSNvr36/KImZ0+nY9NyCbXflyMxpVwa2NbUr4pvufDkACBiEhrcrcn1ZR2a7O78+URENbn31s2nQPZhbW8TkKvXXTTcGh57X3Oh5kYjIcN6d/r6eIiGPd/L3diLCxtExCqgdALjkN+Vq0NgdTawMJGvw+v423MWKD6WOo6d+h8+5YxKQve4071700qOVN9tCSaXhUOEg6jqPj3/VmiMh/kPeU+8ADsG1avJpo/kjiXwh4zyrvt5g4K8RssZ/h1w6HFRUykEpmsI9nDLaQ0FOOs5hy23HwBhkpIiHS1D99pDzro+zl3FDg+M4dXlREunrKebMa/wCBExPtAW2VLK5a+ctaraRuX9i3xzT4Y5xzT4a5nrly/DDx6y5U+HuaUT5qRQYHmGtlT5ORs8zETVIlyTljHapCcQqkzEmRgeIYnWexrJ9DR0x3PpfMYWYwcHMZfFsRsDHwsPHwEdCPNvwsbBxbKYiEjIaIaUpp5iIYcbeh3m1KbeaWhaFFCgRuklSVpSpJCkLSFJUCClSVAFKgRYpUCCCLEFxaO758idSz51NUSplPU006bT1EichUudInyFqlTpM2WsBcubKmJVLmS1gKQtKkqAUCI08PaS8J3+CnbB4oQTUucgMvcQ4//O1lZYQEwkTA55iYqOnggUoSENQ8vzmzmeVtwiUtmEagmm0NiGVDuOep/gJm8Zo8MsuzF1AnV2ByBlzEAS8yXNweXLk0ftiSVKmTsKVQT1TTxCaqaok8ftEp8s/HnKhyt4m5glJkGTQ43POY8PIDS1ysXmTJ9WJLAJTLk4omvp0ywB7JMpKQODgUrxGxMSACDXQnntf7vhUfIk1x3Yie36mz9y/v5ON46ZMsG/qN3521tqB2Di0XVqZbE9aG2m9adOe4qTpjJTPFr9tOfpsT3IZtozK1tz08rjmPVukXJuZDY8tPA9N9zb8MTJndX5v5an378zFnAfre/a3v8onImX83Sh/CqevLamwxKmd101Y2ctr35vr1eLeE+/49dOwfoIkomXUeGv8A3bdbYv8AbfTae/8AWLSkjZvL4bRUEzI/ePz/AARi4Tyd27kj5xRhyHoIGZE6q/XmjAzyN37En5wYch6CKS5l1B/Dy7t/Ei3mcWmfvp5fFz8IuCSRo47Dbv3+miMuZVr8VjsNP+WvyGIzO66XBJ/S53Gv6Q4SdL/XPQ+RMQXJluVeZt8u7rtobHUYiVO6/L3nyHnvF4Qfht387/7PnFsdmOtzvpoB/u/hfrTEKp/XzcHTa57ta4NokEs8r25uGAu7X7dPy2i1PzCoI71NfHW9yOVOVOgxjLn7P5u3vfk2j92iQSwO/r3udXA306sDGer2F/CByZ5s4wdoSZQDhgcvymG4T5SmEQ2DDLnU8el2Z84rgVKTaYymUQGVoVx9HdU1A5ofh+8pMW8lGl/2uc2hGG5ayXTz0+0rKleYsSkoJEwUtIifh+FpmjX2NRUz8QmJQXCp2HoWwMpBO5P2SsqmbiOZM5z5KjKo6ZGXsNnLDy1VVWuTX4mZb/8Af09NJoJalhiJNetBKhMUBn/4qZpOUuH2bJ826GImEk8SzAOlVPdTKYBEuly0/wATiY6LYcCNapOgBJ8rftF5+V4Y+B/iZnORUikxDDcrV1Jg1S7KkY/jfBgWAzpYcFUyTi+JUU5KQbmXf8IJHohkTBBmHOGX8JXL9rIqMSkzauWzhVFRvW1qVaslVLTzkk9bXaMPZPdApyAGuwoVeAGiiRy6j8v0qWEJSkCyQBzLAMB3LdbubtHoqSS5IAJuen8Tqdb2fWILrnXmQT8q/UAeKcZSEOe7cttW3sLXu+ouHbN9HRxb3+VywiEtQ3NgD40H4nnzOtaYykp5Dfyf+A2vYaM7UYmw82Nn92l/edNILi9/IX21AoBzNVG1/nmS0N1Jfb+dm0bbnaL+Tb2GvIORYluWhAG7kRAcVr00G1fl+tNaYykB29f9l99bndm90U17Cw9Q2xYk6nryBEQXFa3tz5getyRseQ2oM1Cd9rN6fIHl2La3aa8wTf8AeO3YdbaX1MW9xViTvrzp+6K6UFL389TjKQk66cje/nqTu3VtQAKC+rEncG7Wd7vyTz184DithvUA77FRJBr0uBztZOMxAuNwNeXT+Xxip0fdRDDp6+ezE6uAYgOq12r+NgOV/Gx6VIzEJsBye/vL66M3O3WKfOwu1tVGxb5MBqGBguq180jXU1JN9fTblplyk2BPfTlYBwex05jYvXY+YGmzsOz6jTmNTGXT2UErC47jZPFIBLUNkeVNOUugPu5mjH2weS/s8MpQoLtpN629QP6OPDQanxWxcoBKKfKWHS5mqkidMx6pnIB5LMiQohv3EuY1g+0jUtKynRg2MzF6hSdiUJoJaCQbgp9pMA/xG7u2ZTHqPGrMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaqX/AEgnh9+zeNPAbik2P9HnDhpPMixSUI7qUxGQczOztmIdUEgLfiYfiEWUqWorLMtQindaQMdLeKFIUYhhtaP+/o5lMWDfipZxmpJPNQqynshnEazeOtB7PFsExMWFVh06iUALcVDUKnJUS35lJrykFyWlgMAlxr/tqJGuhpsPA23Na9a2NjjqkhifUfMc7aXva4vbok3A9C/1p200OxM1pVRT/AUF9gBUeNB8o1Dfy9dO7G7e+ISGcNYctSCbW3Y9RtExtWnqNrGv631uCK4iI1B+vr+RiPRRfd+wIA6chq7dImoVQiulj5GtCeuunXnTEJFjfQ++w2G7WPe2piNQYvzv5/Xxia2r8BS1jWx5fOleSdY1Bx2/TsfgYjUN+VwNbEaef8eUTEKuPpfU/PTSo9K1xjqGrfEXGra6c2I7lmiJQcP/ADbR+4Lc9RozRNZXUAbkilTW41pXmKior5CmIiGLfTbP15hhESg4fkC458j2e/ruCIloV3SKaVoOgNa35crgDYVpixQcH6c/XRzo4ER8wfo2bnpfkdRExtehB6U6frQ6E7aYgIex+vrffa0WKB/Uc+WxuDt35l5SF0pQ22IP3a0oPMnnQaVFARCQ1iHB9/1t02YtES0pWCCAoEMoG4ULuS+zWIL3cFzrsnezs4xwnErs+SLLDzndzHwlTDZFmcKpaT3pHCMKOTI6HQmqmoIyJpMlaaVQiMy/HhCUMfZxjavwyx4YzlqRTzFk1uD8OH1AUXKpCUk0M4b8KqcCR+K5mU00/lKY3o8KM61Oc8tiZitXOrcewud9yxWqqZhm1VdxAro8SqJyiZk+fVyQUVVTPUuoqq2nqqicta5pWrpL2unZji+NvANjillCBiY7iBwJ/aWYPsUHD/aoifcPY9tg50l6GW0l9cXI0wMFmqDU2XO7BSudwbcK/ETRhxjc77OHiCjKWb14DiE5ErBs2+wozNmL4EUmMySsYZOKieAIqvazcPmghLzZ9JNMxCKdSV8D+0h4frzZlBGPYdJXNxnKRn1nspSOOZWYNOSg4nJCUjjVMpRJlYhKIJaVT1coS1rnoUjU4ZmVgQq1AQQQfOybgbHS9iNB6MpnX1vyHR9QfN36WvfznMvcfXT4W1F3eLo1MtB3vz/5fy863nTO6tbct878/PWLChQ69ouCJlTflp4f2a/S2Jkz2a5/hzccx3i0jmNemrd/oRMRMqU+Ijobjz+HEgn6OR6/Hme5iwoG1vf8b+hESEzPkR4/07oBxIKjd3POz+4xQoD2tzP8Gv6xU/af86fT/wCXD7z19/8A6oez6+7+MP2n/On0/wDlw+89ff8A+qHs+vu/jFJUz5keP6SR5YGobduelx1c6GHAL9mBd/kPRyIjrmVa/ETvyA8KJ08xiIzze7XuHJ9NLDf9Wi4JG9/QfDXzeIS5jqa3O538u7z1FOtd8Rqn63brp2Or69t4uCeQ6aefbrbvFvdmX8wFtAfHT4f1ep5QqndX7XOvM9vN9IuCC2w6fyiXluUZgzvmbL+TcqSuLnmaM1zqW5ey9JoFpb8bNJzN4tqAl8FDNIQVqciIp9ttJoEoBK1kISpSfm4jilHhdFWYlX1EuloaCmnVlXUzlBMuRT08tU2dMWolgEoQSdywAuQIzsPw2rxSuo8Nw+RNq6+vqZNHR00pJVMn1NRMTKkykJAJKlrUkDYamzxvZ9k/gFKuzBwA4dcGZdENx8dluTiJzVOGUIbTPc6TlxUzzXNWkhIUmCdm8REw0obeLkTDySFlkJEPvusLeV5OeIWcKnPmcMazNPSqVLrqkooKZSio0mGUwEjD6ck29omnQhdQUhKF1UyfMSlKVhI9ZPDzJ9NkPJ+C5ZkKTNmUNNx19SlISKvFKpRqMQqEgXEpVTMWimSoqWillyJa1LUgqPUva1z024qSZBg3ipTKk5gnaUKIbS4UuQ0ohXDWq1htcZGPtLAS2hyXup76lAteKH9Jp4uSJ83J/gphVUta6WYjO+b0yltKlT1S6mgythk4oU8yeJE3FcWqaaaAiVLn4JUpMyZNH3fdf7PWV1oTimbqmWEiYk4PhRUAVKQFInYlUIcfhTxopqaXMSSpSkVcv8ISfaeHXHK13+VdKAW+5yAuceTCU9Ow5aXNteZjZ7m3mfXkSC4+mcmGtVfM+FTt4AbD6k4yUpYNyuT/AA93xsLNO7e7X1I12A66Q3HPSnOlSB96lrbAmxFQbYyZaNzsXTzAOxLuCz22N30i4AAFzprbW4tY9nvZx1iA4utq3/O5Og150HqDjLQO3lz0AG2t9TtpaKa8uulh7hu9jctoYguKFDtb5E+f3gOQoOYOMyWgjub9reVgdD5sS4Nwt1uyR1Gp2sLgkDrreILiqn633JFE7mmldtNaWykp0G3y+F7+h3sXyFzuTqTffmObA6AiC6vTnXXruRbRI0voK7hWMxAa/wANOp897fMCoG176h9Bdk35+Rvfrb3FWN7ECnQD1N/11y5aW729duWlz1YiKOSdeg9znUPodQBbQG0QXFa62Phe3gbDnY2rcAYykJdg1vgBbfmer2OgvFddG5DoB17j3W3UIDq9dKCo2rWlztTlfx01zUi132ezM/PVvQ8gAGYddLCw01IDNawHWzt0jPh7MLKK5LwDnWZ4hkIfzrnybRUI/oXpNIoKXSOGSRStWZxDZgFakUWAAkhVfZv7AWWVYT4OYpj86UEzs1ZvxGop5o1m4ZhFJRYTISbay8TkYzoSn8dgDxE6YfaCxMVec6TDkKdGEYNTSpif7tVVzp9XMOrfjpplGW1cXOwyQY3mjomGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCMJHt3+ErmdeyVlziXAwwdmHBriTKJhMXyuhYyjneHdynNUttgd5x1zM7+SHCQoBuGh4lxQoO+jrzxJoTUYJKq0h1UFWhSjykVAMhbDcmcac9ACeo6f8acLNZlenxFCXmYTiEqYtTtw01Yk0sxhuTUKo+gSFEgxqBNK0rSlKGh/msbDwBIFfC1OhlDdnLuH5Ncb6M7G2w3jVA6sHu3Qudr7XI18zE5CqHbxrpvWt9RenhfEZ9x5/V4sUNDq23N9fSJiFbjmafiLeda0JvamIVBj2Af9flZwNHeIlBx5C+vY3207WuDExtVQPXlXmKc+XLmRrEob+Xbkeje8tZ7xYfxAhmPXY/Xu7xLbUNP0R8jblXQcq4jOr+u9/rsNWsIi6GxHx58gNtRsbtE5Cxp4UF7i1/HoKE21JFIljf1+m+tLBojUGPIPfoevIEgag3G0SkLuDrahqdQdPmefgDYDHUGdu4YaFr6bED9W1MSh8fgbjfyIdueoia2vvAdQa6Co/i1Gm513oajuxmx+v4RGoee29jo2/kNL6j96U2sjka22+IX6fevbY354jUnf6GnubkHHa0WAag7e7nblz38gYloXoQbE9TS4FDUi9Bfn40JiUl7H65Xvz2+ERqSQ/vHXRwBr1exEereyB2hIjs8cX5VmSMeilZJzAhvLefoBhZIXIol5CmZu3DkFD8blqNKJrDAJTEPQqZlLIeIh0TR5eOV5IzKrK2OyaqaVnD6kClxKWg2NMtX4agIuFTKRf8AbIFlqQJslKkCcoxzvw3zivJmZaeumKmKwqtAocYlIJPFSLWCmqCLpXOoZpFQgMFqlifIQtAqFKO0TL5hAzWAhY+CioaYSyYwcPGQcZDutRUHHS+NZQ/CxMO82pbMTCRUO6h5l9srbeaWhSFLQoE7eSpqJiJc6TMSuXMQibKmy1BSVoWAuXMQtJIUlSSFIUkkEEEFjG+kuZKqJMudKWidIny0TZUxCkrlTZU1AWhaFAlK5cxCgpKgSlSSCCQY1FvaidhaYdl7iJE8VOHUoeVwB4jzd6IgUwSHnmOGubZi69ExWSo5z3akQ0jjXPfRmSIlx0gwHv8AL7qlRUmbipn6JeBni3Lzrg0vAsaqU/tXg1OlE0zFJQrGqCSkIl4lKALzKqWOGXiiEpDzSirSOCoVLk+dfjt4STckYzMx7BaZRyljVQpcoSkqUnBMQnLK14ZNUQRLpZpKpuGLUoj2QVSKPtKZMyfipamWnxD1BvzrTQbm1+e+wYqNXJ7X/ju2jlnjXwoG1v57c9+fcARPbmRtem1QRXUgmlPClhbXniZM8XvuNN7Pq+o1a/TaLeDbvy+HL16gRMRM/wCaleov6AEeeJBP6976DZnd+ul4s9mHFhvt8mfZ9PnFYTLmpJ31A6X+Hn15ed3t3A67t/H1tFPZjRutyRZ+rRVTMzSykEf2k1+YqPD5Yu9sOnoYt9mOZ9R+kfipmd1I8O8N+dBfxpTD2w5j0MBLHXzIH6RTVMuSk+RB3HQH62162mfa9tA7X+LRd7MOLe8kdrP6fKI65nWvxC1rEVGmtRXmLH0Othn9S7dBa+mz6bfIxXgF7DVtHbqzONNx5F4iLmRv8QvzItvUig+nLxxGqf1azXPuB6A7WffaL+D46+XL+Om0W56ZgBRKwlKRVVwABrUkgUApUnQbkVtCqe+76s2rdtLizDUltRFwRvsA5fTfct0t7jGzv7HLsER+R4OD7XPGOSvQWa59KohngtleZoch4vLuXZxDFiN4hTSEdaacYm2ZpW87L8rw61qEJliNmE0fYciJ5LHJXpB9onxal4uuZkHL1UJmH0s9CsyVslQVLrKynWFS8JkzApSV09FOSJtasJBmVsuVJSpKaWcJ+8f2c/CSZhMuV4gZipVS8Qqqdact0M8KTMo6OoRwTcXnSylJTUVshSpNCglpdDNmz1IK6qSZGdrOmcZXknLc0zLN1n7HLmStDCFJDsZFuEohICHCjRcRFvqQ0ip7iQpTyyGm1qOhPit4l5d8Icg5j8Qc0TVDDMBozMl0klSE1eLYlPPscMwagEwpQqtxOsVLppJURLkpVMqp5RT086YjdXLWXq/NWN0GBYakGorZvCqaoEyqWnR+OprJzAkSaaUFTFsCVEJloBWtIOIvM+ZJlmqezXMM3eL8xm8W5GRKu8ShHfISzDtBR/0cLCsIbhodofC3DMNNpACRT8xue86Y/wCJOdMx57zRUmrx3M+KVGKVyypRlyTNZFLQUiVMZVBhlHLpsOw+QAEU1DS09OgBMsN6IYLg9Fl/CaDBcNliVRYdTS6aSGAUvhBMydMb806omqmT58xzxzpsxb/jL/MqXX9Ur0A0HIDWlq3OONpS3zLe/ctp6R9QjTo5bzdyLuW1G1nuLRHHNR5WOuthf7w3OgHzyEIduWvf0/d6G5NrMWuAaw13PLff3DzOn4YLixU3rzpudheptXw31IrlpT5W1O3Xlo7N5MA4oSNrcvdf0Jbq5ABMQ1qpv58yNiaggClyK8tbHJQjQkBnsGdurcy/PRtzaoDb2Zy+wPkWJGz3A6hoLi9aUqfDXY05AbV8NcZaUt589hydrP2HXR4uPIWLMOg7au19joLsYhrXTfrWoGlyqthcmnje1MZSEW5Hc62P6+VgAXd4pbXVrMdSdg3vJu7nsLe4uu9LU10SNrbq3000BpjLQlz2PqT/ABuf4wI0BZybn1YOdOQtpcXcRCcWTWmt7eAFL+dfG/Q5aQLcti3PU/Adh1io7ty6B9Ws3FYab2s4EBxXnqBf1PlTw8KkDLlI3LXYkXFth1Yi7+bmDtcXFrCxbtblyuAxcXEBxWo0pU+NK8jzPKtTQXuMtCXI1/m3p73AuwNwYW5P5ki51BYDfkdQA8bTfZbyO/w67PnCfKsYwuGmMNlCXzOawzqAh6Em+Yy5mKaQbyRb3kDHTV+DWampYrU64/Q19n7Kc3JPgx4c5eqZS5FZIy1RV+ISJiAibT4jjZXjdfTTUi3tKWrxCbTLIdzJdzrHnb4h4ujHM7ZkxGUtMyTMxSfT08xJdM2moeGhp5qT/dnSaZE0WH59BpHfuO4o4ZDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhHQfal4OM9oHs68ZeDiywiLz7kDMEnkcRFd4w0DmhEGuOylMYgI+NUPLczQkpjn20FK3WYdbaVJK+8PmYzQDE8Kr6CwVU001EonRM8J4pCy12ROShRa5AIj4mZMJGOYDi2EuAutop8qQpT8KKkJK6WYprlMuoRKWoAglKSAQ7x/PHeh4iBiYiCjGXIeKg33YWKhnklDrD7DpaeYdQaFLjLqFoWkmqVApobjGra0KSSlQKVJJBB2UHBB10Lg+e8aHzEKQpSFJKVJUUrSdUrS4UDyIIY2FwXZorNq2JGlzpW5of1bU1oAMY7bAEbi733Gtm5a/lDRGbjsw+PflzG7DUxNbVtWlSK7eGtRtcWsKUAxYoOH1IBYfXuiIhrbMeHU99Pdyd3tEtCqHpcX2P5Heu1MQkWv3+ux5bve0RENfo562t6aHXfUgRMQrfw9fyJrqa+PexGbWL3LCz25NbSxtba7NFqg/wCIcrjmO46ddNIltuaX011323trsa10G0ZGxuD7/r3d4jLKF7k6hu/v7D3xLQvxBHy+WljcnyAqBCtOr3d9foX36d2eIhnHNz35f7Xbm5fQykLpoTrXrtpbmTc1Ota1OIFAjt7t231AGgDbNzjKWPPUHrzHQ+49mImoWCPqOW5pXWlq8611qTZ9fXKIynceR62seV9OTNyArpWR+B/dIsBUcwNDcmwoRUYsUl/q7308zcaam0Wu7hXXa4PIeeoNuxiWlY1Hhe51III+VRWvM0OIiNjp8dD+kRlPJux0NvdZtn00u+YL2eXbFhpB+zeAHE+aoh5TERPuOGWZo95ppiWxcY8gDJMzinHG0ogo6KcW7lqIdqWI992SOvKhYmTswPdXhlndFL7LLWLzgmnWvhwirmKCUyVrUGw+ctRAEuYoqVSLU5RMUqnUrgXITK2O8GfElFH7DJ2PT+CnWvhwKunKSlEiZMUP/ddRMUpIEqbMUVUMwuUTlqpVK9mumTKzH53yZlDiZlDMOQc+yCW5pyfmqWvyjMEhmzPvoKYQMQBVLiUlDsPEsupbiIKOhXWYyXxrEPGwL8PGQ7DrexuGYniGC4hSYphdXOocQoZyZ9LVSFcMyVMTuNUqSpJKJktYVLmy1LlzELlrUk7K4pheH43h9XhWK0kmuw6vkqp6ulnp4pU2UvUFiFJWlQC5cxCkzJUxKJspaJiEqGoZ7QD2ZXEfsnTKa8ROHELOOIfZ4fiDENz2HYdmGYeGrcS86GZVn5mGQVGVw/8AooaDzy00zJ4t16Gg5uJTNYqDh4/fzwq8bcKzvJkYTjC5GFZsSkJVTqWJVJjCkJTxz8MVMLCev8S5mGqUqolhKl05nyETFyvPbxZ8D8XyHOqMXweXPxfKK1laalKVTavBkrWrhp8VShJJko/CiXiaUpp5ilIl1Ap58yWibiqbmQt8XMipBN6n+Kh9D1x3sJ3XkA77Wdx05n3R0Lwh3bn3vbXX1fozRKTM6f8ArKUO5vvWnxW11p64vE8WuwHX5FrfXN6cAt7+v6ekSBM/5/mDX/j+mLxOJFz2sD6W+NvlQy+RPZh/D5RzEyt979ep+uK+36e7+MU9mDqfUfxgZnS/eHn/AIj64e36N5em8PZtofIAfqI4GaWJ79P7wH/fP0OKGcRoX62Deo6dor7Pq/u/X4RHVNK/+srrpv4/Fiwzhzfk5e/k7esVCBvf3eUUURb8U+xCwrb0VExLzcPCw0Ohbz8REPrS0wwwy2VuvPPOLS2000kuOLUEISpRAxDMqUy0LWtSUIQlSlrUQhKEpBUpalKICUgByolkgOWiSXLUtaZctClrmKCEIQFKWtaiEpSlIdSlEkBKQ5KjYORGyH7Nf2RkyRG5f4/drvLbkE3CLhZzkPgVO4ZaIxyJ921Ey/MPFKAeUPsjcMpwOQnD2NaEaqMZBzgxDtMvZejNQ/GDx9QuVVZXyJWe0MwLp8TzLTLBlhDqROpMFmpssr4QF4rLUZfs1H7gpSlJqpe4vg59n6YmbSZpz9RmWJZl1OF5YqUELK+FK5NXjcpX5Eod5eEzEhZmJH9YISlK6SZsgTqfSjLspmU9nszgJPI5LARMym02mUUzCS6WS2AZXERcdGxb6m4eFhIVhC3nnnVoQ2hBUogfFjTmbNlyJUyfOmIlSpSFTJs2YoJRLQgFS1rUogJSlIJUSWADmNxKiokUkidU1M6VT01PKXOnz5y0y5UmVLSVzJkyYshKEISCpSlEAAEkxi34occ4vjNFQ0fL2YyXZHYWt/K0vjmFQsdMIRYUhjMs1g3FKehYucQ6vtMBARQh4mVSiIhoaNgoKcOThpXgX9uX7Qczxf8AEP8AY7L9YVZA8Paqpo6NMpajJxvNA46bF8dnMfZzU0bLwjCWSsSqeXX1Mmdw4tMSnczwByqvDMqS8011JNpcSzXJlVlLJqpIkVdHl5bTMLROlqedInYmhScUqJE0ypsqVOoKSqpZFZRTwrqNazSpvTc2rpqdNf66E40fSkbW95/Ww+nIB77Dvq5O/JtG389dgBvFW7qB1FdyK0NK2AsAdx1OuQiXoTpy5EXDsXOp79AxioHbq7Fturs+g6Pe0QXHPytsLHui/qrf0Bykp+vmbNtYb9AIP79B3a553056mzCIi161O1+g5eJ21O56zy0uXaz/AO8f0u+l9ra1A5XO5se7X25mxtsfxQ1r18Li3kBTw131NhjLQkAP6eYuer9e93eLuTB7gjVyeZO2+urcohLUdTQk20B/ui3ma0F6+GUhPuOhf1PfQt0S7uDQX+L6NcufXR9CCWEQXF6nra51FgNK90VvpS9STbGUlJsBc3c6a6k+73WiugfYAW772s52+T2hOLpb12qbeNAOXgANMZaEgAfrcC/x+FwRaKNzvufgBzLkB3I0uxiC4quluRtbcm9OtCBYmoNKjGShLntqDudh6s9+TizxUDV9f3r8hYcuhCjzd7GIDqxsRyTyA/8AmG1NLXtjMSGsNhqB723PLfQvZ4E3ex2GmrMSbaDqTz0YjtDgPw9ieLHGbh1w/YbU6zmDNMuRNSkpqxIIBwzTMcSAv4FLg5FBTGIabUU++dbQ0FAugjtXwbyPO8Q/E3JOTpUtUyXjOP0SMQI4XlYLRr+/43UAKZClU+EUtbOQhRAmzEIlghUx441nLG0ZcytjmNLVwqocPnmmd/x1s8fdqFBIuBNrJ0lClgEpC1LAZLnbCSlKEpSkBKUgJSBoEgUAHQAUGP0VJSEpCUgBKQEpAsAAGAA5AWEecBJJJNyS5PMmP3FYpDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaK/tVeAjXZ+7a/FOUyuEcg8rcRn2OMOU0KQlDSYHPkRHRU9hoRDaEMtQEtztCZqlUuh20hMPL4KFZNSgqOumdcM/q3H6xKE8MmqUK6SGAHBUlRmAMAAlFQmdLQB+VCUjYk6ZeJeBpwLN2Jy5aOGlxApxWmSQAOCtVMVOCWYBEusRUykJAZKEIBI1jHg2si9dzTmRrTlUXpyFQTbHD1JcefSxfrsdD6gPHXxsedg7aH+Btc6m+4ichWlOVddv1pXWxvfEZ9Oe1/rXk+1otIceevvHr5HXSJbaq+I86g1PiSCDStzeoFbRKHp8DoOwI100HQGIhxe12PQ7eRHuAuTrLQuljf8AEfr5ailcREOOX19fziLQ9CbbNbTr0t3OkSkKof1cfO9vl0IEZBIL837W6C40BZmsWILmxQa40PLu/ppExtelDcabVrSo1tv15bVsIdwYsIcP2foeY7+7TRnlpWDcf4G553t5UuLaQKS1tvl9Hy9CYiNj5dRyHUk3O3aJCF0p86ag6AgU89eadwDEUs/mR/EvqP46cURqBHJ9+vMdDZuvWxEtDgVy112N9SNjrSh5AVpawi7Mba9PTbraLCl9D0A30sPhY6XL6xISunXXehF6UNNRal62Fq4sKX0tz3/kbnRvnFhJFue+r77932N7xIS7XpfUHfWtrpIIJqN7g2AMZSR/LytsdR1vpFCkHr2Fx2PmOt7jWMw/Y69oWiTw0q4Xcf5o+uXsIZgMscT4pTkS7BMtobZhZXnl5S1vvwraUqahs0hLz7J9y3PW1w32idQ/dmRvEwU6JOD5kmqMpIEukxdZK1S0gAIk4iSSpSAAyKwcS0/hFSCniqE7IeGvjGKVFPgGcJ61SUBMmgx6Y61SkpCUy6fFlFRWuWACEYgApaTwpq0lHHVIzSsRUBNYFDrLsHM5ZMYULbdZcYjoCYQUU2Clba21vQsZCRLK+8hbanWX2lhQK0LBX3zLmgiXOkzAoEJmSpspYIILKRMlzEEgg2UhaSxsQdDGziVSqiUFIVKnyJ0t0qSpE2TOlTE2KVJKkTJa0lwQVJWkuCQYwtdrf2KnBTjLFR+cuz7NoXgJnyLXGRUZlxEC9H8JJ3GPqcfQUyGCpM8irXEL7jruVxGyKEgwlEFkwvNlx3YnI32h8x4AiVQZnlTMy4bLEuWirM0Sscp5aWSXqV/2WJAIDpTWezqVzLzK8pICdcc+/Zvy1mJc7EMqzZeV8UmFa5lIJSpuBVExXEoNTS2nYYVLLKVRCZTIlgCVh4UCV68nHzsCdsDs2ftCN4jcHcyRmVZc48l7P2R2XM85HTDNLKG5hGTmQIiHsvwUWO6uFObIDL8WoLS07CMxIcYRtNlnxXyTmv2UvC8epUVs1KeHDcQUMOxDjIBMpEip4U1UxFws0cypQGKkrUghR1NzT4SZ7ygZ8zFcv1cygkFROK4eP6ww72aVcKZy6im41UiJgIUkVyKaZfhUhK0qSPGH7SUhRQtSkrSSFINUlJBoQpJUCkg6g7645+KjRrvcbgjYggX90dcmUxYgg8h6aXPqY5ftP+f/AIv/AKmLvbn+6Iey6K9P4Q/af8//ABf/AFMPbn+6PUw9l0V6fwivBOR81i2JfK4WMmUfFOoZhoGBhn42MiHnVhtpmHhYZLr7zri1JQ222ha1rUlCUlSgDFMrJcpC5s2YiVLQCpa5qky5aEpDqKlrYJCQHJJYC5MXyqabOmIlSZcybNWoJRKloUuYtSiAEoQgcSlEkABIJci14yednb2R3bQ49xsrjJ5kdzgZkeMSiJi82cXWYqQTNuC7yFH9mcPwhWdY+YxDKi5L2ZlK5DKIrupMVPoBl1t9XUOafHfIuXJc5FNiIzFiCCUoosEUiolGY1va4kSKCVKSphNMmdUz0X4aaYoFMd0ZT8APEDM02VMqsNOWsOWApddjgVTzeBw/scMD4hNmKSSZQmyaenmWCqmUhQWNlPsa+zC7OPY/MtzVBQL/ABP4yQzLvveKed4aDXESmIiW/cxCch5bbMRK8nMe478OiObcmmaVMRUfDP5ldl8auAb1Mz74x5sz0J1FNnDCMBWoNg2HzJgRPQg8SP6yqyUzq9XEyzKIk0QUmWtNIJssTTuB4feC2UMgGTWyZJxnMCEEKxvEZaCuQpaQlf8AVtGOORh6SkFPtUmdWlK5yFVhkzTJHvDP3EbJfC/Ks1ztxBzLKsq5WkzPvo+bzaJ90wlSiEsQsM38URHzCMdKWICWQDMVHzCJWiHg4V95aW1dN1tdSYdTTayuqJVNTSQ65s1QSL2SlI/MuYs/hRLQFTFqIShKlECO0MSxPD8Hop2IYnVyaKjp08U2fPXwpBJZKEC65k2Ypky5MtK5s1ZCJaFKIEYK+JnaozP23+JH+RWWoOZ5Y7NeSI2GnU6l0UsQs34ix8HFuLkKM1iGedbalsXFw7cbCZTZeeh4aGg4qPmcZETUSlMq8+vtg/aMn5QyHV0OBVCqHFcyKn4TlySGNWohKRiOP1KQSmXKwqlmpVRSlGZKRitThy58upSlaJPwvBrB6z7Q/iXIoZlHUSPCzJs2mxvMkuYr2K8enSpy1YNhNcpBV/ZYpVyPaTMOlqZOGUeITZtQmr+5+y7aU4kWtSlABQeASkaDSlKUrpY08OglSiSSSol1E3JJLlSidSSSSTqbk3D+toSwAACUgAAAcKQALBhYW0AFhYABojOOa0NjyNB53qo3Jpzte2MhEvR7nYat2DNsL6EbB4v0bXoG/FyNhoLPa5a6haIi3Otdxp5c7Dbn9MhKRvzvy2t3Je/nuDFpL232AZg/Tnrf01BEVbm5Ph1roE/ncDeuJ0S31FruD11Km62YfoIqA/zL2HN2AZ3/ACuDz2iG44fACulTQ3vzJOmpqOW2UlA8tGPlq/b6Ac3WA3bS4ubWDWt01Lk6OTDWvc2poNe7X6qOw8hbXJSh9dPR2dx0axv3OwFLk/AbAf8Al5ka6C0QnXNRWnnWnofiUbaaWxkpTpuf4drfRPStrubaknU8v9nlz00d4ji9didq6culTb89MZUtDX58xqR3D8I3fyuYHrqxa+3M7Bg787toIguL1Gwsabi9h42rqdx0ykpuG1JJHd9T8B1DGFurai13L3L+4lha+xMJxeulz8VzvsN7b08dajGXLQw00H168/N2Nh6HSxYNYD3X0YFrkbiIDiya/wCFa/gNDXStDpXGVLQ5BOjB/V/0ZjsTAbbOAN7DVnve7bPZmIjKz7LHhYJvnTPHGCYNqVCZSlyMpZe77ZLbk8zAlMVN4xp7vDuxErksKzBKaKVhbOY1LV3VNoKvRz+j88PhiGZ81+JNZLeny5Qoy5g3FLPArFcZAqMRqZc1wEzaDC5EumMtlBcrHCpXCpEsnXD7Q+Yvu2F4TlmQoCZiU9WI1vCpiKSiJl00pSN0VFVNVN4iQQuhYBlKjOHj1djUmGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBz7dPs2xHFDs55e455dgWojMfAKcRD8/922RGxXDfOLsvls6WgtNrdjFZfzBDZcmyGXyGJfJ3czzBC2j75ET174h4UqswuViEpIVNw2YTMYfiVSzylExmBKjLmplLANkoM5Qa4PTvjLl9WJYDIxiQgKqMEmqVOAH410FWZcucQwJWZE9NPNAP4Zco1EwEfiCtQZKqdNDrpyPPmLjnY0v0WpLHodP0jVYjUem7g6/AO933Dhpja6U8qgD7t7baG9NDqDqaQKSQ5HvL8Q3LE6iz82sHaI+muwP11N7tve0TULof0dd+oP63BsIfqDof5aHf0MWKD3GrevToQdDziWhVdNdTpvQ1BrpfavjXWFSW7ba7DTv7vLSJQcX00u+2xtY2HLpbSShdbf189KcvG29Diwh+/wBW+tOoJBs0se199Axc66uGvqLuIlJXTz228jzoPLcWxEQbg7Al9wOXb4O4La2qDXH8nt/B997gEym3N9Ot79Dcb9RQ737xsIex+u0RkAj1t8x29d+bS0r8RSu9x9LUqbWGmthEpLdR2/if115PEZDa3vY8+/IlyHfmWe8V0r8K130NOfXba1qWAxEU8nb3ja3Q7jc6m5IsKe4PvG9xv5i3IOIlIcN6/wCGml7iwsdBqqgIMR+vrnz91osIG/8AA6+hv77OWIkJVW4qLg2F/wC8DXp/ShwI2P1tEZS389e2np7y4iqlwjfmLXTyun16VsTQA4sKOX8fX01B5i+tH5j4vfr17G3VyfXPZ37ZnFvs8uQ8rlUajNmQREpdi8h5giH3Jey2s0iFZcmKQ7HZYi3kFS0mDTESlUVSKj5LHud7vcwyznnG8sKTJkzBWYbxhS8Nq1KMoAn8f3ScxXSLIJIKOKQpbLmU8wx2HkzxLzHkxSKemmpxDB/aBUzB65ajJSD/AJw0M8BUygmEEn+zC6ZUxpk6knKcHNZwW7eXALi8xBwb+ZG+HmbX1oh3cs57fhpUhyJc7qG0ynMa3UyKZtRLqg1CNmMg5s64O67KIfvsB3vjAfEXLeNpRLVVDC61RCTSYipMkFZsPY1RP3aclRsgGZLnE2VIS6eLZ7LHi1lDMiZcpdanBcRUQhVDiy0UyVLUwT93rSoUdQlajwy0mbKqFKsqmQ6OL2o3EGxSok0+8D3hRQIpYhQBG5NFDU0OOd6x2cDyPpyP6iOjeIfZg7NfFz3q+JvAThDniLfSULmuYOHuV4+ftpqSTC5iXLET+BUa/EuCmTCiD3akKpjkWGZvzVgvCMKzHjdAhJcSabE6tFMT/rUvtTTL7LlKA2jjeKZOynjRUrFstYHiExaSkz6nDKRdUEkuQmr9kKmWCbn2c5LnWPLEx9kd7O6ZvriVdnOXwLjqitxEs4icXpfD946+7g2c/iDh0DRLcMyw0kCyBcnmMrxr8TpSAgZomzAkMDNwzBZi26rVhvGo9VKUescIneBXhVOWqYcpypalElQk4rjstBJ5ITifAkdEJSByi9Zc9lN7PTLEW3GwXZnyvMopsgp/ylzTxEzdCGhqA5KczZymkndGv/pZevvCoVUWxBV+MfiXWIMuZmusloOopKTC6NflOpaGTPHlNHSMii8E/C2hmCdJyjRzJidDV1uLVqPOTV4hOkKH+KUdS9rR7KyHwk4R8K2EwvDDhVw64cQyRQMZDyNlbKDVe73CpSMvy2XpWtSahbiwpxdSVqUVEng+I45jWLq48WxjFcUUf3sRxCrrTq4Y1M6awB0AYCzAMI59huBYHgyeHCMGwrCk3JGG4dR0Lk6lX3WTK4lH95SnKiSSSSY+1nE+lEglkbO8wTSXSSTS1hcXMpvOY6Clkrl8K3T3kTHTGOfYhIOHRUd96IebbSSApQJGPjzZsmnlLnT5sqRJlJKpk2dMRKlS0DVS5iylCEjcqIA5xn1FRIpZMypqp8mmp5KTMnVFRNlyZMpA1XNmzVJly0jdS1ADnGNTj57Urgxw3aiZPwpZc4v5uS0+hEVBLdleQpbEAKQyY2fuNiMnhS4UP/ZstwkRBxMOFtKzBL4hSSnrvG/EvB6AKk4Wk4vVAEcaCqXQylXA46gjinMWVw06ShSQR94lqaOoMzeNGXsJC6fA0nH68JUPaSiqThcldwn2lUoBdSXZXBSIVLWl0/e5S9MEnGztB8Y+0nmqGm3EfMcXPn0P/Zsu5XlrRgMtSRcW73EwkgkLK1MtREQ44lhcfFLjZzHISw1HTOLSwwEdJZgzNW4p7bEcbr0IpqSVNqFcZ9hQUFPKQqZOmhDlEtEuUlSps5ZXNKEvMmKCQ2uuM5hzLnfE6ZNdOnV9XUT5dLhuGUqCmQifUzBKk09DRoJBnT5i0SgtRmVM4mWiZNmcKWyP8F+HMPwsyJLZAUMKncUP2nmWMYqsxM4ikNh5pDyqKXCy5ptqXwlEoQtuHVFBlDsS97zxG8cvEqo8V8/4ljyJs8YDQvhOV6SaPZ+wwalmzDLqVyBZFVik5c3EarjK50sz5VGqcqVRyBL9xPs++ElN4O+G2E5dmSqc5hrmxnNtbKPtPvOO1kqUJtNLnllTaPCZCJOGUfAJciaimmViZKZ9bUKX2it3W++t6V3qa3050Jpvc9SJQBoNPXyG5uS/e7Wju1xqPU6joAC3PkNgxERVOa00/wABbfbXXoTTEyUXAZ+n6nRtBycPzgz9ty4t37WYWdrAGIy3KV15nUGtK/Edq1Fhc1rWmMhMsb3I0DeRZPYEgk6FrRcBboX6uTY8I1sAbm7PaIrjl689uelfDau2pvjIShm57W+n6e/QNXQMQP8ADfvc3fdufcMIil8zcV8rbVuoj1O9MZCUbl25cx15X9Ip7z1e3Q7gM5vdW/IxHHNem2wvfvG9SRc/7u9DkpTpzLfJuX87m7NXQdNzuS1m0tsG8m1iGtdOp9OdzS2u3XmSTkoRz/jtYXY99tTFN/gBdhfRjd9202ZrQ3F61r43tWlTcU0JAB8qb5KU9PL4DYtzPUmzxXa+hO1+yRzvq1nsLO0Ja6VPSw5DUkjnWutT51xlS0WBIB5m9zsBpYenwFb8rnQdR8SBqXANhEFxeo2uCdaVpvzqRQVobXtXGUhJJbnd32+W+wIvd7RQcjcXvqC1w3bkN9NDEUJcecQyy24666tLTTTaS4644tXcbbbQkFSlrUoAJSkqUpXdpW2M6VKXMXLlS0qmTJi0oQhCSpcxaiAlCEJBUpalEJSlIKlEhIckQJShJUtQSlKVKWoqCUpABJUSTYAAkk2sVG942meypwg/zI8C8kZJi4NmEzEuB/b+cfdhsuOZqnoRGTJqJeaUpuJdlTZhZA1EIUpLkHKIUIUpCUk/oF+z54bDwq8Jsq5VqKaXTY0qkOMZl4PZla8wYtw1NdLnzZRUifMw9Bp8IROQpSV02HSOBSkBJPnj4i5m/azN2LYtLmqm0InfcsLfiCU4dRvKp1S0KAVLTUK9pWKQQCJlTM4gFEiPROO6Y4RDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR8/mzKuXs9ZWzHkrNsqhp7lbN0im2WsxyWNCzCTaRzyBfls1l0SG1tuBmMgYl+HcU0426lLhU24hYSoRT5MqpkzaeegTJM+WuTNlq0XLmJKFpLXZSSQWIN7GIKqmkVlNUUlVLTOpqqTNp58pb8MyTOQqXMQpiCy0KKSxBD2IN4/nydq/s85k7LHaA4jcE8xtxKxlWePOZZm0QEEZkyTM/wDrDKWYW3mUIhnVzKSREIuYNw/wS+ctzKUv+7i5fFMt6z43hczCMSqsPmufYzD7JZH+ckL/ABSJoIYHjllPEB+VYWg3SY0czRgNRl3G6/CZ4U9NOV93mqb+3pJrrpagFICSZsgpMwJsicJktQCpZA8+oX4351uN0/kLX3vf4hS1j5b+Y6xx0h+mr6a87bX/ABHcMW0Imtr0Fa60J5bg21sK8tb3rCoNtaztsdiB/dufgW2sLmzX+i/8dGv1iUhfWnI10J50286XruCLSNj9fX1eLFA6i/Mcx+v10MtK6+OpB873OlBpT8cRKS3y/QsNSdC8RkAi1xt5NYsNX0LxJbXsf67XFtfn5iuIyH0sRp/H6+YMbtY3B0P6/ozcuQkpUefK96E8jp/XpUDEZ34rch06a+mmvJxaU7p76+jdtt++0lDg8KctRfUGl/xsDa2LSG10PoYsLHodxty5W87cy8SEroNSbgVpY7abWGltQSRYCIo5M1uh9bv3bbeLCkjRm0bQjz73vvpeJCVeHgb+Y+o6Gtq4iKe4PS3117MdIj4QQe7Ho/MWa/JwA/K9ZLlKUOnqB49Dfw+I3BxGUkfVn7bPbTe2hEWkH153HXt1G2rc5CXRvroaGhF7VFADbTQUOhFsWtZ/TkdN/Pl01iwh7adDdy3O/nvZxzNcLFbGpGux6Cm5/wAU4oRz0Pv+t4t4Trpy3HUvqAdtevOOXe1CiCNPiFut7AnnShO9cW8Iv1+tC4bkCGG0Uvyd9RbTtezaOGD2jubh32huNvChcOOH/E3NuXYSFAS1J0zIzXLhSP3XcsTpuY5eeoPhQp2WKW0Cr3SkE1x9vDMx4/g3D/VmL1lMhH5ZHtPa0jbA0k8TaZTXbilEh7MXMckwXOWaMvFH9T47iFFLR+WmE729CQGYKoaoT6NTbFUhRT+6Q5Mevcu+1F7RUoSy1OJbw5zYlASHXZrl2aS6LdA+8sO5fnsqhGnVCp7wgVtJJsxoBzOl8Wc0yGE+ThdaBZSptNNlLUOYNNUSUBXX2ZT/AKsdi0XjznOmCU1MjBcRAYKVPo58maobkKpKunlpV19iU/6hjt2A9rjmVpsJmfA7L8a7T4ly/iDM5W0pVqkMxWUp0sJqD8JiFWNCo0JP2pfjLWBP9rl2mWprmViUyUkm37q6OeW1txb62vyOV9oiuCQJ+VKSYprqk4xPkJJt+5Mw6pIGtuM94hzf2uGd3m1/sPgxk+Wu90lC5zm2dT9tBAJqpmAk+WVrSLVAfbJofiFbWTvGTEVAinwGjlKP5TPrZ9SBydMuTSE9WUOQiGo+0NiqwRSZYw6Qo/lNTiNVWAHqmTT0JV1AWl9ARrHQObfaedqKftOsyiZ5KyQXAoe+yxlCGiohoEEENLzfE5paSdSFqaUtBHeSpJAI+RU+J+a6lJEqZQ0JUNaWkQtQBbQ1i6sXBsWcPq4eOO13jbnmsSpMidhuFuPzUWHomKAIYkHEF14Sb2dJI1Bdo8PZ/wCKnEjiZGGN4hZ7zbnWIDyoho5ln0xmrEM4sE/6lCRT7kHANoqQ0xAw8PDsNkNMNNtpSkcQrMSxLElceIV1XWrB4gamdNnBJL2loUoolgBwlKEpSkWSkANHXmI43jONTBMxfFK/E5nEVA1tVOnpQp/+6RMWZcoDRKZaUISmyUpAAHWTqjcCxOu+lrGlLctb1roMQJDJL7/AgP8Ap6+WDcHpbcHUgHkdmFttL29edkrhkJ7mCI4iziGSuU5YeMNI232++iLzGtpK1RaQurfdksK8l5s91SxMIqDfZW27BKxpr9sDxSOXsuU/hxg9StGMZrkfeccmSJnAujywicqX92UUlMzixyrkrpVjiCFYdS18icFy6xIO/P2H/BwZkzRUeKeOUyJmC5NqDR5dlTpPtEVua1yZcw1ifaJMtScvUdQiplqIMyXilZh1TTrlzaBRORpTta79dB/gPz51PmgEXHP1N+TWHS2rdo9ZdTz6ve9rcgNQ4tY7gRQU5zNdh89BqdNrHniVMs7uOYdzrubtrtudeYB9b8+mhLkju4Fx6xHU7y1FaHU0r0000FbE0pWgnTLbZhv31Nn1c9b6u0XN/tNrqwLcrufU87xFU5yvSt+XnvcGutzXc4nCeQv8v00bowvaKO5bU3v7rat3D6Al2IiOpwXvU0ra59Nhbe1bUNcTol87nsw31LOXHqC5ZrUuegcOX8tSbs/QOPw3iItw86bVFSQL0AFTQW5m4vUaZCU8tbfp07Pb1Je5gxHIEsTcnmrTvruHawiItwjX0rpy51J3/GtTkol7n158wNttS0ULlrNZmGo67Nozbiw1LQ3HNfMmum9Sq1unXrpkJTp6MPgH15k+Z2EVA7c7G3+zyH970HSIte58QDqb6nwrYbDrplIljfXcjQdB8epvo3FUltB2Hp6FjYdb3LRCcXUa66m+nO1/C9Ba9SAMlCX25e46b7bWO2mtNr35n/8ACN9rgl9zcxBWuu+/TS+vpppTyploTwjS++/l/Kz6bRdp56bcmDchc8xexvHuf2fXAxXF3jfA5knEA5E5K4WmEzXNnXE0hYzMbcQVZSkrhqfel6Yw7s5iIdaFw8RL5HFQUXREahLu332N/CU+IvilSY5idGudlfIRpswYhMUP8mqcalzQrLmFrOkwzaySvE58kpXInUmFVFPUcKamWmZ07405v/ZrKk6gpZwRimYfa4dTgf5yXRKQ2J1SRqkJkTE0iFhQWidVSpkpzKUU7HuPbSNGoYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBj7bnsaq4x8G4TtIZFlLb/EXgZLok5vahk92NzHwiLjsdNFfC2v7TFZBj3X8ywra3IVDcgjs4LLkVFolsGvr3P8AgX3+hGK06HqsPQROAsqbRE8S9i5plEzU3S0pU+5JSk9O+L2U/wCtsKTj9HKCq/B5ahVBIHHPwskrmaj8SqJZVUJcp4ZC6supXAk6g6F+u45jkL0qK/dHOnInpBSXtuI1ZUkguNdL/WurFmN7cpTa77EEfo6W7o8DtUDSBSdjb9Hv3B626RGoOHHz5s17uTryvufxTEL05GtK2qAdx/S2oGqcQkNZrBtP3X0a1x3OzHYizXv8fkANv00lIXSnLprp4/nbS1MWkecWFLOWudrMfUG/wOu8SkLqdq8ga63r51r4eF4lJb9fgPQM/Pm9oyHG/chhYafLvze0hDlKfXTfQgfPTTFhD2P11HyMRl08yPgG56kaXANnJeJKVdetzca3v/Q68gMRkEdrafpuToP9n8TvFCkKuDfnsYrpc686nx2PKnKnLTXFpTy+trHe/Qai14s0sofR5H1O4fZ7xIS513qakkHmLXA2ppTWpAxYUg6i9x2+vdFpSD5bjb9eY1tfnFcOC1d7XNq1tfr89QNcRlBuR9a7fD6MWEEdeu/WzsQWb3aANVCxb9U5XGhtatxyxGU67H6sQdi9xZ/WLWG22p0sBexL/C7u2sVQ51oNwfiH0rXxxYUkX1N7ixc87s3v20izh1a3u52Y+bgA36sYqpdI001qDXTc94EDoKHcilK4oRq+ugDc+RBu3NvKLSDvfV3t5aE+9+fKOYeF+9SvMpKb8goGv9ByxRn0+IPus3m3KKNbQgche3MguOtn5xzDw5Vr/MT8yBQeflvijWOtuYPye/du8WlI3U1uTe6xO+g89o/fe+P+8j8cGHMe/wDSKhIOjFt2P/mb0ik89RBFTUmmqTbU6U5bm+lDi+WAVXO2z/pfXRjvFwQHcsALnX5k9/KLU65SprvXXnehA5HrW9DUC+UlgGGotcEbW7WA925idAHn2u7kWNjfS3LRyYtzihegrWvPw38a/kDUSp5M93GnY7jo3zZolFi5tqQ1n/g3q4i45Zy7NM5ZilGWZO0XZjOo1qEh6pUpDIUSuIi3wgVRDQUOhyMinKgNwzDq1KSlJOPjZozJheT8u4xmfGpwkYXglDOrqtQUhK5gQAiTSyDMISuqrahcqjo5RLzaqfKlJBUsA8syXlHGM95pwLJ+ASPbYvj+ISMPo08C5iJQmErn1lSJYKkUeH0qJ9dXTfyyKSnnzlqCEKUMyOUctSvJOWZPlWTpKYCSwaIRpa0pDsS6VKdio2IDYS2IiOi3X4t8p+H3zywkd2mPFPOuasTz3mrGs24yp6/GqxdUuSha1yqSQlKZNJQSFrPGqmoKSVJpJBUxMuSlSgFKVH6B8g5Jwfw6yfgGTMCQU4bgGHy6SXOmIlyp1ZUFSp9diNSiV+D71iNbNqK+oCTwidPWEMlKYvxdtqa+p8rCnkDeh+KluNpl2YMB+m/Vxpp+vMGsP3g9tgPLVW/N/WKCnOtTfSu/W/PT5a4kCRyf+HPbqet+TUJF9w46AAer69X5MA8da61rsLitvAml9NOulNJkoLh7X7/R7dGL6Lk31LW56bdL3LjW2sR1u089LX1vRJGwBub9AK4nTLZmt8+Rsez79dIrq79yBYP1Pm/IMdWiKtyv1IJHzpXqKG9Kg7HEyUHYWtf618t35xVw53I0DORzYdQ13Z+WkRlL2BqdK+ug+df8cZKEAbd/Tc7dtegF4tJ5+etmvazAiwFzcsSXtEW5rtz3N6aDcmvp5gzpS7W225B9eQF+vLV4u5ci1xZ+5uw2A1ewiI4v8wDvT95VPkNh1FsmXL3OulvgPgXF976Uv0J0A2Df3R8TZvIxEccvc6nzrUX6U5beNhkJS9hft+u/xJcsRqYbl+Z5HuNTsH013AiEtdev46dPufM30FcZaEcOuv0+939dnJgx1NuQ9bturvpqYQcHGzWPgpXLIWIj5lMYuGgYCBg2VxEXGxsW83DwkLCsNJU48/EPuNssNNpUtxxaUISSUg59DRVWIVdNQ0VNOq62tnyaWkpaaUufUVFTUTEyZNPIkywpc2fOmrRKlSkpKlrUlIBJaLJ06VTyps+fNlyJEiWubPnTVhEuVKlpUtcxa1EJQlCEqWpaiAEgqVYCNo7socB4Ts98HZDk9xpo5qmVMxZ6jW3Ev/ac0TGHYTFQrT6CptcDJoZmGk8F7gpYebglR/dMTHRLrvvr9nvwlpvBzw1wjLS5cs4/W/8AvnNdUhYne3x6slShPkInJKkLpcMkS5GG0xlcMmailVVhPtqqetfnx4jZwmZ0zPWYmlShh0j/ACHCJKklHs8PkLWZcxSCyhNqpiplVN43WlU0SSeCUhKfSmO744JDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEUIqFho6GiIKNh2IuDi2HoWLhIpluIhoqGiG1NPw8Qw6lbT7D7S1tPMuoU242pSFpUlRBoQFApUAUkEEEAgghiCDYgixBsRFqkpWlSFpStCklKkqAUlSVBlJUkuCkgkEEEEFjaNGr2ofYjjuxzx8jXctS58cEeKERMMzcMJg208YSRqW+XZ3w9iIhSVJTG5UiYhH7NSp11yMyxFyaLW65G/tNqG19zdl9WCYioyUn7hVlU2kUyiEX/tKYkhgqSSOAOeKSqWX4+IDT3xFygvK2NLNOg/1RiKplRhy2VwSnU86hUdPaUyikS3USunVJUT7QL4cayFX662/ep+8KnXn63sTxBSXHXY/LtHXSk7jzFuRseRvr6ixAkoWPHw31uDWgI29BUGghI2NiPrzB+tjEZD+T+WnctzuWdza6paHOtRzppU6Hp5gGtjuYiltA/MPcsC5HPtqNgx4Yt5A2+F9++xb4i8pK6Uofn15/oiugJxY3mPr663aLVJvyPMjUdRof1HSJKXARty02rptzoKWqRfc2FHL478/g/bezRlN2Otyz+8au5/2mGh1isldKX52r9PrWlaHriMgj6+Pw7uIsKSHbubWvz5GzHq+piQlwGhNa+NxWleh6bEnmcWFPJvSxbT65WDC0Wu7gjn59udm035WeuFcjtt06XvuN9dCMWNo40tv00L/qkE8ja0o5en8YrJcpT62I8frp5a4tZ9Pr5chq7lmiw21Bf60tflvYdmrJXyNOo0qLC1KDc1ArW4xaQDqP16/wAYoUgjnt8yx5cy/e0VQ5yobUtqTzodSdyTYV1xaUDbn9abfTjWLSg6Pbkbhuh1ZtGPnvHP3gFa+RNq+J08Kcji3gPft/FvreLeEjbux2vZjrzu/cbVA4RpXyuBXny61GLCgbgX9fXfyJihAGpvexSQP+X5PrHL3h518AD9AcW8CRt7z5bxRh08lN/4h8zDvj+Ef7h/LDh/1lesUbt/vD9YiPugrCR3RRO1rmta8iBz56WxNLSQkm5fRyHPLrEqE22ux1H69+e2jxDdXUG9a3pSmhFOXT/C2JAn8tmD+4uAzWfptptEnCByYG4u4D9LPzG22sQnV1qN6bnQ2pewv0pTE6UgNprctdnc8ywHN9IlDKFuTC3d9dLdC+h0j332UeGwlEqiOI02h1ImM9ZcgsvNup7q4eSIdAio8N/eC5rFMpbYccSlQgYUPMFUNMSpXnf9rzxQGKYrS+GeEVCV0GBzZWI5lmSVFSZ+NLlFVFhhmD8BRhdNPNRVS0KWn7/VS5U32dThykD1W+wz4N/1LglX4uY9SzJeJ5ikz8MylJnp4TTZflzwmuxZMpQ40TMZrJAp6SbMTLUMNo1z5BmUmLJmK9iKdJ28yQBtoB6HTnfGlIQ2gbv83u1u3nHoODqUjmx1Oh5787u2xiipyouajmfhGv6r6dMSCXe79t/5NobP0aDE9Tu2nrYP1uQ24sKK3ABbSngNxQAUJ8DTcUrQYlTLbSwfffS+453uDYaCAABbQ8gHO2pOl+TM4L7xHW6TvSwAsajwAsLHW1wQbVJlSjkH3f8AU+T3s9w1oqGYDQGzC+rC51326XuBEdTmvn1J0udQN7cieoxMmW4c307D4E9m8ooTZhYWADjXnZ+egvZ3FnjLcsbgC9tv631POu9sZCUsdH8i/pt7z20gPjdr37tYFmtu7WBDR1uHrcWpqbUqTsBU8gdhcjEqEvYWFg5u3IAXJ27b7RUb8w1rsGsDs/ndg40DxFuU8f8AhTW1BzIHoNSBbGUiWA1rnV7knr9dbXBPdtSWdxz6bbqIs/MaRDcc19bm29/QGtDypc1xOlJJtq/Ueb2HXsTcbB593c/7OlrEuNRpewiqXyr56kAine05aUJpS4tTKSgJ6n6+u1gAIq2nTQbDuemgJ05ExDW4Njf9bU+7alBc0p45CUF9L8tuTuNDdxty6HGxve521OhOvPezmMtXs0ezKcwTg9oXOkuSuSSCKiIHhtAxjCltzLMTClQ8xzWlLoDLkJl5XvZfJ3QiISqfqjItpcHG5dYW96NfYe8Cv61xH/2xZmokrwzCJ06lyTTVMpRTXYzKKpNbmAJWEyl0+DkLo8OmcE5KsXVU1MtVNVYNIVM1r8d8/fc6X9isKnlNTWoROx2bLWOKRRLAmSMOdP40rrnTPqUkoP3MSpahMk1y0oziY9UY1NhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjzd2sOzFkHtc8E808Gs/NfZ2Zq0JjlfMjMOmImOS85QLMQmQ5qlrZdYLrkA6+6zHwP2iHbm8niplJ332mI9xxHy8ZwmmxqgnUNSGCxxSpoDqkT0giXOSHDlJJCkkgLQpcskBRMfAzNl2hzRhFThVcGE0cdNUBPFMpKtAV7Gplh0uUFRC0cSRNlKmSlEJWSNBrjhwW4hdnXinm/g9xQlBk+cMmTJyBjUsl5yXTOEWkPSyfyKMfh4VcfIZ7AuMTKURyodhb8FEI+0Q0NFJiIVnXLEcPqcMq51HVo9nPkLKVM5QsaomIUQCqXMSQtC2DpUOIAvGlmMYRXYFiNVheJSvZVdLMMtRHEZc1GsudKUpKTMkzpZTMlLZJUkhwlYUkdYJXXqaXpaut9OlOgFbjT56kv0On19e5wfkqSdRY6B/W/rq3zEV0OHUE7DWnkT+OvI3riBSWsR7vg4aIyAduHXVz6ebaWLjUhhKQ5S2vNPp90ix5jQioHTEZTckWPPY/4hqORN+ZEWENrfl07jyIb0dolIXXS3+B1B8+ZsagYj9x+mZn117RQpBF7/H3dGe+7bGJCXCLE+VBTw/pqeZJAxQpBvvzGsWFN3Z+ofi7636cn0IEV0r0oeetjXal78tuZN8RlLe7TTqTa3PzYaRYQC++mgcNu4a2jt5ARWS4Rap+iqV+Y26898WEdAR6j37/VosII0uNLu3PXnpqLdLiKyXAdT+fkL1ttShtvXFhSNrdNvrrqxI0tFHB1Dd9NOZtzFu+kVAvetLc6EdOtedqb4oxGz9g4LdNBZ+V2Cd4oUDY6+n16xUDhFa7c9vMWPqcWsC2z/Wh15ai+gLXtKVDZ9NOnofTvFUOnWp9aj54o36XcX5OQ3vi09Q3ldvcPcNO8cw9pcedfnenp/TBi7Nccr/CH4eo9D+kcg7/MfJZ+hJxQpG6fURaw5D0EfvvbffV8iB/h5eWKMOQ9BFeAEOw9Db/liGtwKUpROp1qnTS9Dy1+eJQg200bR79mvy9D0ioSQOXQg+gs3a/TpEZ1YFaUqDuo/nSht09MXhNwwYPy6HRhdteY7ERIA6ebjUC769yXsd+mpj73hTkKI4kZ0luX0BaJc2r7fPolCi2qFksM419qKHBVSYmLUtqCg+6lSkxMS24pIZbdcR1z4teINJ4ZZIxTMk0y14gU/cMBo5ifaCtxyqlzfucpct0g01NwTa2tJWkfdKWclBM5cqWvuTwM8Kq3xg8RcGylKTNRhIV/WmZ66XM9kaDL1FMl/f5kubwqKaqqMyXh1BwpWfvtXImLSmnlz5svLbCswsvhIaBgmGoOCgodmEhIZhIbZhoaHbSzDsNIqSltppCW0JoKJSBUmhPjlW1VZiVbV4jX1E2srq+pnVlbVz1cU6pqqmaqdPqJqgAlUybNWpayAzqsBYD3ww/D6HCqCiwvDKWRRYdhtJTUNBRUyGk0tHSSUU9NTSUl+GXJky0S5YLnhSOIliTULxAsTfdPqTU2HjQVvrriAIG+nx+Y9T5Rltu1/wDX/Qc9h6RQU8aGhrtUVUo23JNBTkfOgOLwi/5fMhm/l0v3hbm+tk2Hazkud9L3Y2NJTnWm1jVWlN7CngKbcjKmW7O9z2B9b/A62irnQMA/zawcPudC+m7Cgp3XrW9b9d9elzyxOlDeR8vSxPu896M+rA8zfUnQX13cs7kbkxlO7ih31trap30OgN9gQDiQIvpftfyFmFwNrc4rZzs+5/Ny5MNQ2hbbcR1OnUk2qBU32Fh1NflrQHE6ZT6+nwJNnsQ3wIJhYB9ObO/m+7ka/AkCOtzrTUm9z41uNdPwFp0oA5emnbU2HdmtDkHYNtqdbgMTcc+92vEW515gAb66DkKC9TcUNqHGQmXxbW6v8u7eTgMbG0cWvawHN1N5dLdWiKpwnfyOnIXqb86WvSmoOQlITYeZ36/rc9zFQ+9zcO7atpuxO+r6BtIq3L0HrUjzPT8bUJ0nQh+XXfyHMhr8nDkB3o528zvbVhyHP0c6+k+yp2b592lOJMPl5n7VL8lyQwszz7mJgBBlsnW8oNy+AddadY/bk7LL0JKW3G3g33IqZOsPQsviEL7++z94I4r41Z1kYPKE+kyzhSpFbm3GpQAVQ4apZCKOlmzJcyWcVxQy5lPh6FomBHBUVsyTMp6Kcg8B8RM80mRcCXWr9nNxSrEyRg1AokifUhI4p05KVBRpKTiRNqFAoKuKXJStMyegp2g8vZfk2VJFJ8s5dl0PKZDIJbByiTyyFSpMPAy6AYRDQkM131LcUlpltCSt1bjrigXHXFuKUtXu3g+EYZl/CsOwPBqOTh2E4RRU2HYbQ04Ik0lFSSkyKeRL4ipZEuWhKStalzFl1zFrWpSjoFW1tViNZU19dPXU1lZPm1NTUTCCudPnLMyZMUwABUpRLJASkfhSAkAC8Y+lGLDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYxfaYez2y/22eGjc2yw3L5Hx/4fwEW7w9zM/RiHzFLwH4uI4dZmiO+hv9izeLX7+UTSIS47lidLMbDqTLZhP4OZcTzVlqXj1JxyeGXiVMlRpppsJqbk0s4uPwLVeWs3kzPxAhC5qV9e5/yPIzdh/tKcS5ONUSFGiqFfhE+X+JSqGoU4HspizxSpinNPNJWlkTJ6ZmkTmrK2ZciZmn2TM5SSY5azXleaxkkzDIJvDOQUzlE2l764aNgYyGdAW08w6hSFapWnuutqU2ptaugp8ibTzZkifLVJnSVqlzZSxwrRMSWKVJLXBfQF9RqANRKqlqKKfOpauTMp59PMVJnyZqSmbKmoUykTEG4UlTnlqzhQizpcBpU30rSlqXrzG/ysTXEBGx+vlrGKUnUBuxB30+AYvcPtaulZtXpvatToRodeorUXFcQqQR1F/o+X1dojbn1u1vP3W3ZnLtElLm9TUCtQKGo/iAtSt6i9+hOIyl7eRB25tuD006RaUkG1ntrYvsDbzB5dQIkJdFL0tao0r4W+dN/vUxGUkbE6f4m07ejtaw0i3XXU9hc6F+X0NbSEr3BtzOnz0pXela6EYo3K/Tf0/R4tKQe/MfV/OK6Xda01qK/nbb8upsKQem1rdfjFhSe40/D+nU8rbtFULHPkb9dBXXzOt9MWlH0Pi1teQZrM8WsD8wNetiz7uAwFme8VQs7Go9RbwNvlXrixiP00Pv18n6xaUtdyDqRp0diGPk/WOaXeumlDb0r+uWKFPMa8xeKMoG7abuD30P1y0ioHR0B3qKV8aW/XrbwjmRyvp27xR9iD1s4+fTn7o5hwcyOgIV9b/r1t4COR7hh6DU9T/Kn4NwB7j+o93pHLvjkf15jAJUNCPU/DT1EOFJ0PoX/WOK3KJJChWlBYi5sL1wSFOHdt7+vPbpDgHM+79Ii962iR1p/X6+eJeI8z6/Xu8orw9VHo7vFFazempNa6X5nlQg10OlOtwBtfsGc31YXdw1ri5sIvCQGLpG3UDdj2PUXLxk27PvDsZCyW1GTBhLeZM0Jh5lNCtKkvQkIEKVK5SsqAUlUKw8qIi0JSjuR0VEMKLyIZlw+WP2kvEtXiBniZhmGVKpmWMpKqcMw1KC8mtxErSnFsXCU2WmdPkpo6KYpUwKoaWXUS0yVVk+WfbH7JPg6PC7w5k4ri9GiXnHO6KXGcX4pZ+8YdhnAteCYGpawFoVTU9Quur5aUS+HEq2dTTTPTQ002O9y7zIqNKXN+psfkfGt9eBK0d9RrYa+vdie0bVObiwsAGPPewN3vZvO0Ui5YipO57xrz2FvzxIJYB08wL+pbns+8GO77asB2+G190gtFNTttQNgNNuQ100NOtMSBAvbY9T35D084MG2a/wCV92dyT19zOzg0VObabXtXmQNdK2qa7XFReEktqddLnnroH924Aitxc+4OXI322Hu0FjRU5zpy+I0HkAeZ5img5mVMon5MxvYhzZvTXswachzL/i2bX520cD8sR1O6mp318dhbnrppWuJ0ywNh5WcAHW93Gvp3dtrudLPZ3HqOrkuYjLd1ua+pp62uenia2lSglgB5D6s2+uujgiHDvd+o7sw7sSSe5/MIjLcubjpa3O3O5sRprTXGQiU11emnL9B17GKgejamxb5M3TW4cRHWvcknxNzb0FgdKV0ucTBOwsP5D5iK6aBte/Rn6mz25Bi8RHHKa6bXtYmo6n53xkIQCOXPmX07DdtbB2vFt9n7DdjuT0F99js/ZPB3hDnbjpn6UcPsjS8xc0mK/fR0e8h79k5ek7LjaI+fz6KZbd+xyuBDzaVK7qn4qKdhZdANRMxjYKFf7F8NPDbMvinmzDsoZVozPra1XtKqrmJmCgwfDZa0JqsWxSfLlzDTUFIFoBVwqmT6iZIoqWXOrKqnkTOP5nzNhWUcHqcaxeeJciQOCTIQUfeK2pUlRkUdGhak+1qJvCoi4RLlJmzppRIkzJiNofgVwSydwA4eSrh/k5gqZhv9dnc5fbCJhmXMD7DDUwnkwotwIdifs7TUPCocWzL4FiFgGFKah0qV7t+FPhflvwiydQZQy3KeXJ/yrFMSmICKvG8XmypUusxWsZSgmZP9lLlyZCVql0lLKkUsolEkKOgObs14nnLGqjGcUWApf9lSUqC8mhokKWqTSSbJdMvjUqZMKQudOXMnLAUsgdxY7IjjEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYffae+zDkPbAkERxV4VQ0sy52kctSwNsvOGHl0o4sSeXsL+z5XzPE9xDUNmaGaQ3C5SzZFuJaYbS1l7MTv7CMtmeVuFZsynKxuWayjSiVikpDAlkIrEJFpM5TMJoYCTOVYMJU0+z4VSur/EHw9k5okqxLDRLp8ekS2BJCJOJSpaTw09SWZNQkMmmqlH8IAkTz7HgXT6ZuaMr5lyLmWd5OzlI5rljNOWplFSaf5fncE/LptKJpAulqKgZhBRKEPQ8Qy4khSFpood1aCpspUroydImyJsyRPlLlTpS1omS5gKVoWk3SoKYhQYguG3cjhB1TqaSfRz51LUyJlPUyJi5U+nnJVLmSpiSUrQtCgClQ0YsNxZos6F228Dp/Sx89q944gIN20+n9Ow6sbRjEcV2Lb2v1BG9+Vr6gJiQldaU8aE32pQ1odeZ8QTQRlAOlu1h8IjKSNDyBG29tHG9iD0FhFZLnjzqCQelR1oNuovfEZSRYj57X9N/wBIsKXtp0IHm2+pJ1Poz10uEUIttavd5XBIIN9ietiTiMpfru+hfuBpszadgItIPudidRqWaxHWz7XESEu6VpytSmtNNf8Al5E1xYUkPuL3NjoCeh0O/YbxS29vX+Oupt25RVS4DodDsfnQ/QVN6Yo1+X+K3l/Gw3ihAOoB2f6uP5tFUOEU2ttY0tt5aW6EYoRzDh+4f4Rbw9X6KuP1H1rFQO+o0JF/Cv589cW8I6gcgbd2+tIt4TuLbhJt6Hfkx8tjUDg5mw0B71et7jwH+NpRybvow8rHu38KEdGvYkEfC3dwG67cu+Dv6g/UE/S3XFOA8n6gj4ED4+kU4QzFj2UG9CB8fSP0L5ECvJX5C/rinD/i/wB3+MU4B/dP+5/GOK3NB3t664uQncjoxi9EvU8I5M1/PlFJS7XVXX979XNbYv4RyHoIuUiws1xt39w38ucd89nnh5/ltnFubzFlLmXsqLYmEYlxv3jUdM+8pcqlpC6tqQXWlR0YlSXe/DQghnG0pjUOp16+0f4lHIWSZmGYdPVKzJm1NThmHLlzDLnUGHhCUYviiVIaYiZJkz5dHRrQqUtFZWS6lEx6RaVbX/ZF8G0+JviLLxnF6UTso5FmUmM4qidITNkYniypi14FgqhMHsVyZtRTzMQr5cxM6XMoaGZRzZQFfLmoyVl2orc1uTpv/NY151N/KvlqENYWbYEkegcD0HSPagu92J1/Eoqcnf4vbz1bgXTsR43J8O7oNuR+dbgg68JF+QAPnvvoDDnfk/CG31e79b6bRTLlRuB5AfmPC2pFcXiWQTpY6an5B/XR2sYNr2Aclz2a99xbUi0Ui51vb7uvmTr68rb4lEodSH/e08kjTtrrdMVt3Y6DYbizm2xte1hFFTtNKX0OppW9TX8786YkCALNowuwvpp+unckmjm2g0F9n6B9e+2gZ4oKdtqdaVrUgVv9dNR1rUSJQSzdNrXvp8m3fRnMTe5/xaciyR33Da33igpwHetR5UuLmouaDrsf3jidMrQm3x58ufPe7WAFWf0a/kbBt+bG/QMaC3K3sNegvXrfz9KWEyUgWA/X+UNOvUtqPeNOps50vHU5S9ak1t6moHpz6hN8SJS/bV9rbE+ul/8AFaGnXzs46XJNhzNjpEVbmv52Ap+8b7aXv1xkpls25ttv0GzvyfqNIaks/dtw4s/Unto7GOwuE3CbPfG7O0syFw+lDk0nMwUHop9ffZlkjlTbzLMZPp5GpbdEuk8AX2vtEQUOvvvOQ8BL4eMmUZBQcRz3w98Os1eJ+ZqHKmUcOXX4lVkTJ01XEigwuhRMly6nFcXqghaaPDqQzZftppSubNmTJVLSSamtqKemnfBzJmTCMqYTUYxjNSKelkumWkELqKyoUhapVHRyiUmfUzgg8CHCEJSudOXLkSZs1GzN2aOzVkrs1ZHby5l5CJpmWaJh4rOecoiGbZmWY5m0hQShABcXAyKXKcebkkmQ861BNOvRD7sXM42YR8X7geCXgnljwTysjBcHSmuxquEmfmXMk6QiXW4zWy0nhQkArVS4VRlc1GGYamauXSy1zJs1c+tqayrqND8956xXPWLKrq0mnoacrl4XhiFlUiikKIcqLJTOrJwSg1VUUJVNUlCEJlyJUmTL9HY7njg8MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGL/ANod7Mzhv22ZA5mmSOS/h/2gpHLwxlviAiF7sszLDQwQIfLPEWHhIdyLmkpDSFQ8qnMOlydZaccbehUzKWNxMgj+J5lyrS49LM1HBT4ihDSqhvwTgPyyqoJBUpGyJgeZJJdPGkGWrr3PGQKDNsk1Ekoosako4ZFbw/2dQlLNT1yUgqmS2HDLnJBnU5IKRMlhUlel9xo4KcUuzxxCnHC/jBlCaZMzjJVBbsvmLaVQ0wgHHn2YSdSKZMKcgJ5IpgqGiPsE5lcRFS+KUy+0h4vw77TXRlfh9XhlTMpKyQuTOl3KF7pchMyWsEpmS1MoIWglJIsXCm1SxfB8QwSum4filLMpaqTcpWPwrQSQmbJmB0TpKyDwTZalIUxD8SVJHWCHPltv5amwt5mgFcYJSNm9dLPd+V+TDmbR8oixfrcP7wPV+gd9DXS6TQVrv18bCh1JPS5rcGwjn9dO4iwpBDtbtZ78ySC3e55ERVSvkamun3SB59P8SL4sKBtaLSkjqDsb+hu7Hvy2isHDemvOlD9NgeW4r1jKSNRb1ixhZ3HQ3A8+7b9LGKqXTfTyHdPTSxI1oKVqKEXGLCkFtbc3PxO+nLpFOHy7aDvoQGO9xd3sYqh4ilSLUA7w031AIqB4E600raUHZxbYuOzEg33vyu2lGOrPva3TSxbsOji8Vg7XUUpyoR8q18KjXzxYQ3IvzdPmx9zltYpb6+vke+0cg4k6EV5Go5+JHPf8hDaggerelj5RRu3r9P5RzCzUAH5gjyrfTW1RhbmObF3+Y98UKRuPkf1+ukcu+rn6AH8PpimsU4E8vef1imVoJua0tTumg1romlb3xeEqa3qCL+/07mLwCBYkPe6v1MSIKFiZjGwcvl8O7FR0dEswcJDMtqU9ERMS4llhlpHd+JxxxSUpFdTe1SMesq6bD6KsxDEKiVSUNDTT62rqqiYmXJpqWllLnVE+bMUQlEuTJQuYtRsEpJJDRm4dhtfjGIUGE4ZSzq/EsTraXD8PoqZJnVFXXVs9FNS00iUl1TJs6fNRLlpAJKlDvGVvhrkyF4eZOleXIchyKaR9rm8UnugRk4ikIVHRAKaD3KFIRCwoNVpg4aHStS3AtavIbxWz3U+JWdcVzJOeXQqX9xwOlUCTR4LSrmCilK4i4nT+OZW1YACfvlVUcATLCEp97vBLwuofCDw7wTJ9PwT8RSj+scx1yAnhxDMNbLlHEZ6ClISqmpzLlYfQEuv+r6Kk9quZNC5ivui6L1APnX1FPDHXQQBuX6W+vJrR2yX/ALoYcym3xt6RxL19daWA89/p41xdwi5bk7kmx77ae6D3IcDRgA50e1hb17iKRdr1O+9L/KmtT1scXhJ5bW2Hbbbl0uIo3MEuBqW9Q5Ol9+3Kmp0ixIGovep2sNK2pS52G+L0ylEP9fEdi3rtFRsOmiR5am/QksxFyIoqdvzBpruDra56/Ikm2JRKAZ7+T+8/p+sVZn0Gt9fj1vq2tjrFJThoa0pTwHLT5Ct+dqAShI0AuYr2D33t19NNHc35mKCneZrQa6C/Ifha/XEgQT66b66OWH8L8oo9+dhowDc9e7P7tTHU7t6ab05U0GvI9MTJl899db93uXPaxu5NqOTZntYBwByvbRujH/ljqd1uDTao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j0IA1dgxbuQDqQQdzITE6XI5c/mBsb36YAvod22Z/cS925npEapHJJBbUFx11e783tuNqoirXWf+H8j8zio4hoW8j/5ot9iLfiUfS3v+EcDE61UTXwprbSv0p4WxQnqPJn73OnkfnFfYXdlKG/N/pvIxQXEgVv8AnflWgueQPzscEWu7fRAYA9XvtoHkEoJ2CdL66e87aBn1e8RXInrzrWvzHdqK70Sm29gcGJbb3n9A22rjXcGQIBNg5O5DcmPMjbTziC68KE10NdtfSxsa0vfWl8NGbo5Pyck9hcOddYmSjm7jQWcDS7OBrdyTYWdhFvdfrau+unyOu4qqgGwSCRhe+vXmO1rc7EvZ3sRkhOxGmgHc3L6HS5u+ju4tzjteg/x056a3oOZwbn3u2z3LFm7b31vGQiW91WcbWsdhyY77++LW8/civOvTmOnVXkL6NbnTXv1PIch5mMtCGA5gWbYWLA8mDEnXoItrjmwNSee/KprVI5epucV1udNnbWzH4gCx+EZEtBVtb3Wa3+Eb8z5AfQ5K4l594W5hhs18OM5ZlyRmSCUksTrK06j5LHlCHEuGHefgXmVRME4UAREDEh6DimiWYlh1pS2lZlFiFbhs9NTh9XU0VSj8s6mmrkrAseElChxJV+8hQUhQspJBEfLzFlTLecMMm4JmnAcJzDhU8K9rQ4xQ01fTlZSpPtUIqZcwSZ8sEmVUSjLnyVtMlTUTEhUZxOy77cfMsmdg8r9q7K4zXLVqhYdnihkKXQUszFCXDT8TmbJzSoSRzltZWIl2LywrL78G0w40xl6bvRLfuO6Mt+MdTKKabM1N95l/hAxKilolz0X4VKqKQFEmaCSCVU/sCgJIEmaVDh89PF/+j1wmvRUYx4M4wcGqkibNXlDMlVPq8Ln24kSsJx1Yn4hQKTwmWiRi4xKXPXMQuZidEiUv2mwxwo4x8LuOeUYTPfCPPOX8+5Vi1BoTSQxgeVBxZYZiVS2by95LMzkU3Zh4iHeiJPOoKAmkM2+yqIhGg4jvd64biuHYxSprMLrJFbTKLe0kr4ihbBRlzUFpkmaApJVKnIRNSCOJAcR5jZzyLm/w8xudl3O2XsSy5jEgFZpMRkcAnyeNcoVVDUyzMpMRolzJcxEquoJ9TRzVS1iVPWUKbsvH0I4nDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEW+bTeVSCVzCdz2Zy+TSWUQUTMZrN5rGQ8vlksl8G0t+LjphHxbjMLBwcKwhb0RExDrbLLSFOOLShJIjmzZUiXMnTpiJUmUhUybNmLSiXLloBUta1qIShCUglSlEAAEktGTRUVZiVZS4fh1JU19fWz5VLR0VHIm1VXV1U9aZUimpqaQhc6fPnTFJlypMpC5kxakpQkqIEa9nbW9tPCSt6bcN+yB9mmUcy5FS6a8bJzL24mVMOoSplZ4dyGPbUzNnGniS1mbMUKuUOFhZl0inEDFQk4T0Zm/wAXEyzNw/KvDMmJKpc3F5qAqWk3STQSFhprK0qZ6TJPCfZyZyVImj028AvsET6yXRZr8bva0tNMTJqqPIFBUqlVk1BImJGaMSplpXRImIACsKwucK1ImJ+9YjQz5U6iOvFmXOuac95gmebM7ZjnebczzqI+0zef5jmkbOZzMogIS2lyMmMwefinlNtNoaZ77pS0y22y0ENNoQnoWqq6qtnzKqsnzquonK45s+omrmzlq0da5hUtQAAAST+EABLAcMen2D4Dg2XMMpMFwDCsPwXB6GX7GjwzC6ORQ0NLLKisok0tMiXJlFS1KmLKUAzFqVMWVLUVRBbd3Brz1rW1lDwA0tXWmoxzcC7H909N2GhB+TxlzJb3sW+gCzNc6i+8T2n6UANvUgAV8+hHxU0BrXFH1e3I7HX07EveMZSHNwR77fDz6X0aLg3EV3vpXenKpFDXrfypUeos+vw7G+vTqIgVLcP0t7yWuxG4Fix7tPQ9epNhvvfQ01A9RS17VEPfrq4BvyI52A0Lb3jHVJbTTz6bO40a14ltxJ1rX0tShJ0PPVQB3NxamjA37uDfkp2fo4tu0QlDOW89jzfQsOxb3xJTFCl/6EaUJAOnhf5CpJ69mf4c+bkdoiMoEX89i77h2PbhIHrFYRKdK0Bvag8LUBr+umDvb8J53+THf0+Nhk9CknRiCe4uAH0ZnjmIogUqelzb5fWuKW5I9f8A0w9kf7yh0OvkygB5vH4YkDc1J3+tx60GK6ahIfkf4D+EPYF78XTi0fyMUjFDb5AgHxHdFxzGv0OSW7aDnu5JDe/0i8SgNgCGdyfh+FzvoTEZUUb6aa69TtTyJIGB1253ueQIF2G7+rXi8S3Fn7aeRuHs17u+sQ1v13qfKl6UpanQgA8hzBvdzJ+AOltz3GrzJlH1Hx3fe2rDoRq8Nx8CtTW1tdq02BO2pHhagPrqTd/K3QB+m/YmMhEoDYHk/L383vzG5D292I7wrXUa+VqUAqBsAQka1w3vci7Db5eZbpGQlDdXt7/W/IW2L2e3rdrXoRU+VgbW8BTcUBoTVuZfcC1uWwJ3+g8ZCJZOum4/W/mw6RbnnwK/FsamtzrqeQ0GpN9CMV199+WnrrsDpGSlLWDM1ybdPIDlfX1tTzwuSdLgaA0JvWlh09epn6DfuXfbzDX9L5KEaM+tz2fUPpfT1e4i3Ou/vKPgnSvIkaV5eHPSptYfm+HO/LmT+XvGQlOw03P1qdgLnSOz+C/aE4v9nTOcNnzg7nmdZLn7K2PtiYCIK5RPoSHWpxMrzLI4gOynMErJccJgZrCRLTK1/aIYMRSG32/q4RjWKYDVJrMKrJtJOSU+0KC8qelJJ9nPkl5c+WXICJqVN+ZJSr8Q4dnzwzyR4o4FOy9nrL1Dj2GLTM+7mpl8Ndh86akJNXhOISuCswyrHCl6iinSVzAn2U0zJBUhW032GPbA8Ku0a9J+GvGtuU8H+M8X3IOAiXYwscOM9xpLaGmZBNZjELfy7PYxxakM5ZnkTENRTqWmZPP5rHRaZZD7H5P8TsOx0yqDFhKwvFSyEqKuGgrF2AEiZMUTInKNhTzlEKLCVOmLUJY8fftD/Ygzj4Wors15BVW54yHJ4p9TKTI9pmnLtOONS14lR0spMvFMOkJSFLxbD5MtclBXMrsOpKeQqrm5l8dpxolDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR03x34+8KuzZw6m/FDi9mmEyzliVJ90wlX+sTefTV1KjBSDLUpbUIqczuPUhQh4OGT3GWUPx8wfgpXBxsdDfLxjGsOwGhm4jidQmnp5dh+9NnTCDwSKeUPxTZyyPwoToAVrKJaVrTzrw68Ns4+K2aKHKGSMHnYti9YeOYR/ZUOG0aCBPxLFa1Q9jQYfTAgzJ808UyYqXTU0uorJ9PTzdO/tze0t4udsmcRmW4NyN4dcC4KLBkvDWXR6vez9MJFCIgp5xCjoYtpzBNy61DRcNKAVZckDsPDCWQ0VM2ImfTLVrOWfcTzVNVTpK6HBkq/ssPlrvP4VcSJtctJHt5hZKhK/zEghJlBSwZ033I+zz9lDJfgXQyMVnIkZn8RJ8kivzVVU6eHDTOk+yqMPyxTzgo4ZRhC50mdWFsUxKXNm/e5smlmSsNpcdjbwNKkA0pWtajW4G/I89KmuOA3HbXiYeY7dN7ux12hKeVxyvppvr1G3aLg09cA69b8/MjXqAb3IwIGx9N9nYvfnbXRwLQKQDcNo2nbv1d7c9zFxaiCKGvhU263NK6mx02odLXdhcdGt1/mCzt0EYypbbB2FnsdmflewOruHie2+DS9KC9BUelPhtrSosLVqQJuxHO2r9iLG3meQa8KpbliAPL3tt5ExObf59L+OuoA8a60p3RW1GbQtfTV/W+2x0jHVKIv57nV9x73sGd9CZaIkgWOl6UH4ingbDU0OHMkEdRfr+puPe0QmW2o+Y+LbDQjTlEoRXPQWrUHahJIFwKUp3vMXwBc6g67s3kNR37veLDLB66/p79y46CJCYoGgrem4qBtyVc05+W4XOzE6nXTmxB+P6RqkhtH00e/lcevxiqIpJ/etzH+O53pvc1rioNnuG5vt3ufreIzJS7Eatbf1c66/zjl9qT/Fbyr9PxxbxD+8fT/0xd7D/ABNy4v4/KOKopINQq2p/wr+FPLFwIZxcDkL+n16Rb7BIIDeRu/m7RTVFC97EWIFBvb7oF60qT5nTFOdne4f+JLeQH6SCSOTX0vbtoD6/xjqixcjn5a3Gh0prUDY2xU6XYON767cree8XiW3IXPy9x5OGiMuJJ33ItQnfSgNeYvzA3GKO+jq06Bxv6jr5AxIEasH1976377h+8RFv6XrS177C42150NQOZw7lg2g28xf0A0bm8yZRPIX2vz3Fr3ve452MJyIFNb35gX60qdxal9b1IrYWD9h/HnzOu0TJlAbcu+2/e1rcrxAdia2FKCvLTwvSgprf0FHfcaM/y09G31EZCUGw9B0HnbkN32i2uP8AUlWo0sbm1b60+I78jQmoD6lunnz+LPvZQ0yEyxvttyNrvv0OzDqIgOvU1uaig5G/qrwA1BoK3qHOhsDrsL+TsRvfrYNOlPTqBz/QbP6RbnXtSTUn1FPW3hcU7wtfADYeZt2fQFrOdBoOpnRLe5Ftg+xOpfQdSXIJ0sItjz9KitTy5aXJGxrTQi1jW+Lm6MO5JJLOAzO/Nj0LM2WmXuQwA+hr0sN99CBbXHKVNak/oW0rTQCwHTW4czZOybXe/n0HP35aUaOGa4HwNjryH72pswGdP2eXtk828F35Jwf7Uk0nGfOEQU1LpDxFfEROM9cNYYpbZhoaaLQHphnTJ0ItJqw99qzTI4R1aJVEzeWwMsy2x3DknxPqsLMrDMwzJlXhjiXIrVAzKyhTZKEzCHXVUqSNDxVEpJPslTJaJcgedv2nPsL4LnxGIZ38IKOiy5nYhdViOVpZlUWXc0zXWubNpASmmwHHqgEfjlmTg9fNQlVZKoaqoq8VmbZWWM0Zbzrl6T5tyfPpPmjK+YIBiaSLMMgmMJNpNN5dFIC4eOl0ygXX4SMhnkmqHmHVoNCK1BA2MkVEiqkyqimnSqinnIEyVOkrTMlTEKulaFoJSpJ2IJEeMeLYRiuA4nXYNjeHVuEYvhlTMo8RwzEqWdRV1FVSVcM2nqqWoRLnSJqDZSJiEqFizEGL7iaPnQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEeZ+1b2r+E/Y+4VzHifxTmhSkl2AynlOAcZVmXPOYvcl2HkUghHVpClU7r0zmT/dl8mge/GRzqR7lp/wCDmLMWHZZw+ZiGITLXRT0yCDPq54S4kyUnXnMmH8EpDqWRYHtjwb8Gs5eN+cKXKOT6QEsipxrGqlMwYTl7C/aBE3EcSnoBYOSikpJb1NdUcMinQTxrl6Qna17Y3FztlcS4nP3EyZmHlkEuKhckZClsTEnKuQ5K+tomBk0K6sh+YxqYeFdn2YX2xMJ5GMMqe+zy+Elstl+pmZszYnmmvVW16+FCCpNJRIUv7tSSSQ6JSTZS1sj285X4pykgnhQiWhH6BPBbwMyT4F5TlZaylSe0rJ6ZM7MGY6uVK/rjMdfKStqivmy0/wBnS05mzpeG4dKUaXD5MxYl+1qZ1XV1XmRp8ineJpXWugtrffwoTelaU42bjqbkEb206sebkM4eO21oJsBe22vXQk20I25OXuLb+lTpoR4358x56d4iuLWZ/eNbuw2Fxz063aMaZLBdxcjVnO4uBr0I72ie2/sTVNvCwJNL2/AjUACre1jyPI9+h3f0JIx1oI1BP+tc8m2ueelv7zRObfI0VXoTc33FQDe9qbdKUsQAf487Eb+rEODrEJTzD9W091ux8xExESLCpr/Ca87GlajTY8t6UMRobPd+m73csW3LbjUwqlPYM2rFtQ3yDbBnB5xObiiki+m42v41pQUAI/PFuj7Nz0HZ9tLAjQWERGWRe41sz8+j+XxtEtEWDavmDQ6a2JHjYDkNsVv27HrpcaN1fvERlf6vS1yQzcrAkkgeZGsSUxQ2URcChItToFUAtpT8Kj1AO9wwA8wz+lvWIlSknu99vgzn6N7xVETWg7w61NSegCiKDl41vinCLMS3QlvrtFnsfif5flfYtr+tUxJtcX/m/JR+dMPM+QB+CYtMkjR/R/0j9+19b+Ip6Vwe373fhL/BvdFPZHr/ALp/WPz7Sb3FP7V/TvfQnDzPmAPiIqJJOpPmG/WKZiQL98a6A0VvUnu18z41G+Dbkn1Ye5ou9h138vh1vo3naiqKA1UbEaGh8RVWh8Dv5Aw0A8ruPi58+8XiSnpcht/i/u98R1RdKivKwIIpXqRbla2lBatbuddd25+evUv21iVMo8r9WsPQHvaIbkWTvTauldKam3gBbStDhq372thps47Wu5v12kEo8tG2a2w0cNfbTRrtDcitfiJPIE/SpVrrX64qxO7Cwsz3fUm3OxvpdtJ0y25AcvPn/E9ohORBpc0HKoqNdtE+JNbeJFQwsL7Wvc6ue/q+pcPKlADMG6nduXPsPSILkRYgHfXcn1uelun8ogfvf7o5B7G3qx3dyNZUIJYi1tSzXbTyO79ogOP2N9qE2BN7bACmnTkK0wPL0A6gdzy/hGQiUzNcnV9HDEkancXN9QNmtzr9ahJN979NL3I1vpzsMXAMLhydADc9xytt5xlJltzJ9dXL30Gl7WFrOIgOPU36nQ16/W50Fr2pUjdTPsAOetr7u2z94yUoGp+L2u7OB5ksAX2i2uv1qEkcqg2A3obV6k610oKYuAIDm+4HXncga792JiZKe7bM5Jt+7bf++zagbPbXXtQDrUk67XoQfnvat7YrqfhyG258tXAta5OShAdy3YPz7EsS7q8hzjKB7OX2n2f+xRmmEydmlc1zz2c59MkqzNkkRAiJlkx6MiAqNzdw7+1vNsQsyQVuRc0y4t+Fk+aauIecls2ch53C9hZIz1WZWnppqgzKvBJ0z+3pX4plOpShxVNEFKZCw/FMkcSZU+4JRNInDUX7Uf2SctePeETsdwdNFl7xQw6lIwrH/Z+ypMdRTy+GRgmZvYoVMnUiglMmkxYInV2EHgVLRV0aZmHzt2jhtxJyLxgyLlniXw0zPK845GzhK2Jvl7MMnf8AfwcbCPd5K23EqCIiCmEFEIegJrKo5mGmcnmcNFyuaQkJMISJhmtpaGupMSpJFdQz5dTS1MtM2TOll0qSrYiykLSXRMlrCZktaVS5iUrSpI8Cs1ZVzDkjMOLZUzXhNZgeYMDq5lFieGV0v2c+nnIYpUkgqlz6aolKl1FHWU65tJXUk2RV0k6dTT5U1f3GMqOPwwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR0D2mu0lwy7KHB/M3GXirNfsMhkTX2aVyuGKVzrN2Zopl9Ulyll2FUR9qnM5eYWhsrKIOXQbUZOJrEQUol0fGw/x8dxuhy9hs/E8QmcMmSGly03m1M9QJlU8lP702aQWdkoSFTZikykLWnsjwn8K82eMmd8JyLk6j+8YjiK/a1dXNdNBguEyVyxX41ic4f5mhoZcxKlBPFPqZ65FFRyp9bVU0ibofdrfte8Ue2RxcmvFPiTHFiECoiX5JyXBRLr0gyDlb7Qp2EkMoSpLSYiIKe4/O5y7DtRk9mXvIx9thhMJBQeo2Zcx4hmfEpmIVy2S6kUlMgkyaOn4iUyZYIDki82aUhU2Y61cI4EI/RV4K+CWUPAzJNFlDKsgTJxEuqx/Hp8lCMSzHjHsgifiNYQVmXKB45dBh6Zq5OH0vDIlqmTFTp8/zU0/TRVR0uR89fGxrc0GOPkP0Ojj0v31bnpHaykN08mDHUC1jrYgC2jl4uDT+l97bU3FRXcHqNyBQYt/xbaEWt31BOhdhyL6wlAILgfBux2JY80nyETm3qfdPltS9ed9qjatb4oX0Nw5Lj8wvt56t1iFUvZn6al/gQ4LNd9jE1uJA1NKW2pvSm1DtyA0xaQ9wXfbfzH6d4gVL152J/5dX3tuxc67xObiRqTre1NjXStNa1rptbFL6N5HXTby+XSMdUndiDa6R05M/YAlrA7iJjcTWlSFaa3p1uQfOu/UAGF2JBOr3A+f0LamIVSjsHblYvyIZh5gbXiSiIA/eINKUrUDmLkK8b1A3GFxdgW1Zja50u3kGB56xEUajTooN79PeLxJREkalJ5XoedQDTbS/mdcUZNthvqm/v8AePIRYZb7eYD9eo131ismKvevzpodaEjwofywZtyX5tb0+Y7RaZY7bsQ7RWEWB+/6kA/8wP8Aj6OEsCwPViG82Pu/nZ7Ht0+gB9e7mIux+Ktbgk976rA+WDbkC/Ignz3inse3qf0h9q/nT6YRb7E9fUQMXQfepzNe74aLp8geuKEbgDzLHysTF3se3qf0jgYuv71TrY1r0NCTTT8N8VYs9g7bG/mwGmnK+sV9kOmt9/K4Px9IoqijyPjp6VKRTwv47G6kX6fME+5vhF6ZYGxJPIfFr+/pFFUSdikdK6enjuQCd8Pw9SBp+8/V9fcW3FouEsD91u9hztoPSIy4kH94k6G9K6V0NbbiopvbS697Ad226aaF9ObXiQI0ABPIJHfcsB7/AIRFXE63AF6gGh13oeQ5nWtCLClupO2w9NddreRiRMpXID3qPqO2ib2iG5E9dOZpcVItW1qCtTpfTFb6Dlone7F28zyv1MTpk6G50ub2cC3TdierNpCciamxrqQa2pXx6UoK72NsG5nowufTb5d4yEyujltGc3Ggb4htr3LwXH/4j0pWg0pz2uNTbbF1+wDf49LdrdmD7ROmXpy3FidTvcB2e7nV7awnYim9AAbDXXlXrva+nOoBtw8hci7HZ929G7XmShm66276vuNXOp0dr25187qoPG5/PTpbrbFzMLa8z9CwezG0TJlk7A+Thg/+8Q5/1Q1g0W91+xJPdT6E/P6cvLAB/Q337gAENbpfZnjJTLbvsdd2Y89LAWtfrbXX6ggEhNNtTr1ubbGgvfbF2nUvp1drjnYW7XtGQlF3ZzybqGBt2HCPNtYtzr1rWGutyL0vurWh0Gmwxcx/xE2G4A30sGcdA9umQiW1zcsWcWHlt29GvGUn2YntLs0diHiI3lbOEVMswdm7PM2Y/wAussJXERj2TZlEe5hDxFydBhSgibwjDTCMxyqFbCM1SWFbhnEKm0tkUVB9g5FzpUZWrPu9Utc7BquYDV04dRplqZP32mTtMCQPbISP8plpCWMyXLWjUL7Wv2U8I8f8sqxfA5NLhvipl+jmfs7ixTLky8cpZftJ37L45OYcVFPmKmKwqsmqKsHrpy5qVCiqcRkz957KWbMt57yvl7OuTZ3L8yZTzZJpbmHLc/lMQiKlk5kk3hGo6WzKBiEfC7DRcI+080qx7qwFJSoFI2mp6iTVSJNTTTUTqeolonSZ0shSJkqYkLQtChqlSSCD1j89uM4NiuXcXxPAccoKnCsZwauqsMxTDa2UqTV0NfRTl09VS1EpV0TZE6WuWsXDpcEggn6HE0fMhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPm85Zwyxw+ynmXPWdZ1BZcyjk+RzPMmZp9MnFNwMokcmg3o+ZTCKUhK3C1CwjDrpQ02484Uhtlpx1aEKhqaiRR086qqZqZNPTylzp81ZZEuVLSVrWpnLJSCWAJOgBJAj6uB4Ji2ZcZwrL2A0FRimNY3iFJhWFYdSpCqitxCunopqSmlBRSkLnTpiEBS1IlocqmLQgKUNCX2jHb3zX25uNcTmBpcwkvBzJT0wk3CHJEWoNuQMndebTF5qn8K08/Cqzdmsw0NFzUsuPIlUEzLcvw0TFtSpcxj9Sc65sqM1Yoqc65OG0pXLwymVbhlEjiqJwSpSfvNRwpVMZ/ZpEuSlSgjjX+jX7L32ccG+z5kKVhi001dnrHkU1dnbH5IKkT66WhRk4Ph05cuXOGCYMJs6TRcaUKrKiZV4nNlyV1iaWm8AtPmxSfEHfQ2ob2pWtz1rTHDS99rs/kWdmc3Lkh+mx2SWgj8wbrz0IJ73Lgk66tFwaiATYlJ0psTa3npTX6YtKWfkb2AY7aWZ20tpoLxCpHY2azX1a+4tobsDfV5zcRzNDzGn18DyItca05vvrdxaxvt1DB/K2OqW7tf1s3kCN+mo7Tm4jrUcxep8zTzNPle0pGosfduOXw6FogVLN+Q0dgdNtAeX7pZrOLTURANP3q+up2JrfbXyIpihDM4Nt9/W2lvzDnuLxqQNhfS9jqNCwLaHcM/nKQ/yVytt08vECu+BvuCG/e18jb42di0RKl6NZnNx15gM4dtLEsWiUiJNb3puDS/M3pXpXU7YtIDaEdWcdL6t6+cRKla27FnvewIB7fuuAwsIkoi/5iP7XOo12ANL0rp4YMdmc3cH5M7jW3pERlO9nZ7FiG32dx3ZmiQmKFhUXroaevxU7vQctNiuHJfXRQf4hn9OkRGQNWHMkO/lY3625iK6YobE+RvptcW8zXyxTlZOnb1uL/reIzJ6q0u7KFy7X0Onu86iYutu95X73zWflXywYDUK9fkRaLfYm9rD+8hh/4R8Y5/aa7p/vC/4n1xUEDVS+zhvKwinsTf8AJ5cXnZwB84faerf6/u4q45r9RD2J/wBX/m/WBiqDUD+yNNd7aC9xQYtLFmKzfQkegsTf6eAkl/3OliTfubeUUzF7d+3ME19e/T+u2K8P+qfM2b0A84u9iXYv5It70/MxTMUDbvHxJoDfoTflf02o9tE69yPV+bP6xcJHPj10sB/ugac+ZHrQVF0uSOdzU7XNTfpQfWuK3szl3FgQOwt0csIvEgBrJ3D6vqG0Atvaw2JiMuLuaEnw8OqqbUNPIYMGF0jnd/cAfc8TCVsxBFyNANuQ73dtS4ERlxKq6gV5kk/M9aHWuKtbQ9XZI8+e27nnEqZVzbhboA55mwN7HQ6O1oirfF6qJNDre2umwGtaDxvXFe5A6Is5Gz8+nbmHlEseYvbp1Zz6J20MRHIrr0oLmw6HlzNNCRioBZgANn0P689eHbQOIkSgH1u2j2uTsdTcg2dtohORBvVQSBWlSQT0F9/Ac6jarC5Nz1DAHsWfu/K8TBB5dmZrvdyLtb8ovzNohLf1pbeqvL8OeK3t8dBaxtvt6guYmTK5gDoBb06PcqN3cagRAdidaVUbipNhWo56VFDtS3TFWY3ccyfl5Nbz3jITL3Nn6G45aOpujBuhvAcfuaqqemnK+tRa4237wvi/UE6AbnVruNhd9Bbn1nRLJIYMOZcFuQIFhzAuw8otzz+p73gNuVDU62+7S+ADizgalRtbcW1G/KMhCOQHU2BHpoNTYvraLe8+b1J3oPWm4AH8uvnbF4AH5fXfy09dLaF3jJRL/ugPqTy2tbfn6g7W9x4nW2thpf0t0xcNuXf+frGQEgaX5q0FtQLO9/i5a8Z/vYqe0te4C50lnZV41z/ucEuIU6LPD3MU1fQmE4V5+nMSVJg4mMeWn7DkbOse6GI/3hXBZfzREQs9UICXTXNUyT214aZ0OFVKMBxKb/7sq5rUk6YocNDVzDZJUWKaapWWXqmVPUmaQhEyomR5tfb0+yojxGwKr8YMhYaVZ/yzQBeZcMo5ZM/OOXKGUyp8qRLSfvGYcBp0cdKEAVGJYTLm4ak1NVR4NSHcxxsdHhbDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEai3t7+3/Mc0ZqhexrwtmgGQ8rRjE240TqXxDhZzZniWRKXoDh8HmSGHpTkR4Qs1n7ClRSX84vS6GeagovKCjF6/wDipmpVVO/ZuhmPS06gvEpiFEioqkKdNI4/CZdKoJXNBKuKpKEEJVTni9WP6MDJPh7mCpz/AOJ6cWoMczxknGkZLl4KkJXNyfJxPC5dbNxmaJiSr71mCSqvwegrJASink4TmGhE2dNnVsmj1wYaLS6AtKqcxXQ2sRenjoa1NjfpbZtRsDr6m++9x6AeywCVo4geJJt/rJIsQbuD63u5DRc239AbG1xr1rT71ieSq3OLWO1xuk9NAH72e2hiJUvkxHLtpbnfZ3G0TkP1ArcaVGt9PDlQ2rzoa2M+ljcN9fMWIckWiBUofu668O36HZ7A6dHnNRBtcKHXyG532Oup7tzWhGxt+unpz1vdtGgXLvcMxfdvdcc9xtyMTG4kHQ92lqbddh86HQ60xRrWsG2v/EEndw+1neFUu2ludr+YsexY9dzMREfxAa6imxPIGnlrvhd+eum/kb78tRY7RCqVt7j5PYkp5lwQ1nu0S0RPJQP9oXHrQ1rfXagoMUYEu3LQsdrFvLW/SIjLIsNfo7l2D2ZRbV9olIiik3qOWh33JHjoaaXtTFAkjQ9gRyHPTU8iSzRGUNpsNrH38OnqfjXTFUpcHx+ZFQK9L05Ypw7FI2DgttcnQn05xGqWHDtsC9m83B20F+Z3NcRA1FLjYDTyT+tcU0s5SDzct6gN5E94tMp7t1d9ttSfifS5qCI0+MgfXyNaacqdNcUtq6S/NPvtf1iwy7a6mzjb/e+UVBEqFfj+X5U/HyxUgbpHrwjyBb3WiipWmnmNNLaa8/KP37Ss/v8A1H1wb/U/5ot9l0T6fwjl9pVsoA86p+dACfXDhP8AdJ6FQ+TQ9l27Ekj0NhHH7Uv+P5HAgDVA/wB6HsuifT+EcTEGpJXbnQDXyP6NjhoHZIHV1e8P9d4v9na3nZwPcG159xpFMxFtSdaHUEb7H9a9DgaKHkken84r7K46i3l1KlbdYpqiQKmwrWlh+Vb3HP6lrzVY9A+3T0J7ReJYGoax/e1Iu9iPmxuzRHMWBeo8hWo6Gg0Ntz5UrUAuGAS3Nn63u/S45ReEMxHO4ACQH1DkgX2ILcn2jqiiRWlK0uaDoa0AFN960pSutWfUk9gQC4+nYs+0Xpl9O+7jfca7gkjQsYiLih/FU8gN6HagA06keGKhrs3xPmWtrub83IiRMpx33Oh3fZLtve3URFXEHmEjrr0008rbHBuu/c99hzt6sLRMmULFr8/n7tQDq7m8Q1xA2+Lck+PM0PhUipvsQbmA6ak6G+psGZzsWA90TiX3HxNr2AKn0OwuO8QXIiv3lVpU0BNtbbeYF6Cx5VDtYeZv0YBn32BvqREyJZuwFtCQlvIaaWu5O+rGE5EGpv3dSANd61tbxN9BYgkVAfS5e5Onf4jd2cGJkyu6j1e3635sLk7xBciDse6KG5qa602BJryoBehG1wSHc/iPJ7DTV323ubuxjITL04mJFgAAW6PfezDUb84Dj+tDpqT59La6A1rypTF2vXk2nxLs2pto14nEsMH20SOnx5+93iGtwqNvX6/4m9LYrErNbQA6b7G5bTmHd72uDSwh7oYQjdg9iV7Qd7tLcKXuzzxUnRi+N3BWRQf7GmkcqsbxD4VwqoeVS2bvxBdWuNzJk2IcgpBmV95th+YQEZlqcrdmkzjMwxUNst4Z5uONUBwivm8WJ4ZKT7OYr81ZQJaWiYS54p1MSmVOJYrQqTMJWtU5Q8FPt8/Zql+FWcUeJuT6AScg59xCf9/pKcf2GWc4ThNrKqilyglIp8LxyWioxLCpaFTJdNUyMVoUoo6SThkmbnYx2lHnlDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR4I9oz2uobshdnaeZolMQj/OhnYxOS+FUJ3YZ5UPmONg3Fxea4mGiUuodl2TZeXJutDkJFw0ZN/wBhyaMabh5suJZ4nnLMIy9g82fLI+/VRNLQJ/CSJy0ninkKcFFMh5hdKkqmeylqAExxwPxEzanKOXp9TJUP60riqiwpDJJTUrQSuqUlQUDLo5TzmKFoXO9hJWAmcVDRTz3LIvPEDNXpjFxUyn0VFRE4Eyj4hyMjY6cRDjsRFREdGRTi34l+ZvOvfa4l91Trjz5inVrcSe9q3VcU8KUtRXMWpUwrWorUpaiXKlqJUVLLlSieIkufxOY+f9hH7UVX9l/7QOCZxxSrnKyFm5UvKfihIXNqDxZcxKrQtGY2R7UzsRypiRlY7K45M6bV0cvFsKlLp1Ysupl+UWnHoR1QKVoUhRQ6y4lSFpUhRStC0qopC0KBBCgFJUCDS4x8g2JB2t6fXyj9lNDW09RIpq+gqKeso62nk1dLV0k6XU0dbSVUpM+mqqafJUuTPp6iTMROkVElSpc2UtMyWVIW6voGItLiQpCqg2IOoIoCk7VHQ1NiDocUb3db/rtfXrrH1xwTQFJs731bdiHtyPufVVwbiL6kU0HSx8fWoxQh9Q7eR+WtrWEWLlm5I4g2o131v03t1vE1ERShNb7g9AK7jzsd9NbCk3ANm/KfkSe+2u7h4gVLOgYi7A7e8aC1iNdNIloiK0FQflTexPqTWpppcYoQAzuk+ZGmo823tERlB3/KexL6eZ3/AL3SJSIihFFFJva522FjprU79MUY3txc2fs40c21YjnERlHVgW04SAbau3/l9SHiUiJJ1orS4NPqAa9KfXFGdwe1x7jv7jEJlgPqNQxGg8nHuG8SERQ5qSba3+RFaDwvinDq3xc+QN28ojMvo/bV9WsSP+XSJCYqp+8lVib21526+OKM3S/JvXr6RGZQfRux79U38vOKwiP5TpqFVJ15jrXXrrfC9tfJrdXIB+tOdipQ6HysPNhflc77mKgiqAXUOmv5fj44HdwCOxJ7/LQ84tEp9DfV+I99OJvdptFT7WLVXWlqd38e6fw6YoyW095T32vbtAylbA+/z/d9PoRzEWP4kjxA/wDcJxayb2T/ALx/T4PFplKGpV6J+bfW0fpix/Gg00sPl8GDJ5J/3z+kU9mf7yvRH6xwMWP4gPADrrRNPx64AA6AeSi/I7Rd7JXU9w3wB+to4mL0HfJF/wB2lP1/iMXAJ04fVJ+LfOK+yJ1cdywbv+FttDFNUTXdR86fh+fO2K3br0b5vAyg/Pp+a/rbyAikqJpsBY6q8b0pS16W8N6g/lzOvmAPhEnsgzufhs1/yW6Hv1igqK/n9B+NPxxViSW6ch6k+7SL0yunTzOx8/8AW5RHVEi9ATyJNB5bX6G2DDdreenLb4d4kTLY7PyAfof7xHqAbRGXFE1+IDoAdL2JtSniedMXAE6Am57efI6b9IkTKvoTrd2353N9WcX6mIi4i1bnqTrTpYEepHOmDWuW6emvTcajVr6zJl9QNdBfzOr6NfsBEVyJ5knagsPWmg2sAD0OKhJsWYC7m/u6XawfvEiZQayQANzy33AcdH0eIa4nUV7o1uTf8SKC1afndwvr+I+jC/16bXicS3L/AJjYcm215X6ekQlxHI+Zp4eA8q7Hli5voW+uu3SJghhcsP7o13735687XiIt4qJ1NdeVbeZ+XTFeXbTl8vj31iUBnAHDbuTr6dHOh0O9IknXCGjtZ9buT58ugYdI/MIQwhDCEdy9nzjnnns18ZeH/G7hzHLgs1ZAn8LOIZn3zzMJOZf8UNO8tzX3CkOOybMsnfjpHN2QauQEe+Ed10IWn6WEYpVYLiNJidGvgn0k1MwByEzUXE2RMa5lT5ZVKmDdKjoQCODeJfh9l/xUyNmTIOaKdM/B8yYbNoZq/Zy5k6hqbTaDFaP2gUlFfhVdLp8QophDIqaeWVOjiB/o5dn/AI3ZL7SHBjh1xw4exKojKfEbLkLPYBp1xhyLlcX7x2BnWX5kqGW6wmcZansHMsvzhplxxtmaS2LaQtSUBR3FwnE6bGcNo8UpCTT1klM1AJBUhTlMyUvhJHtJM1K5MwAkCYhQe0fl38ScgY94W57zP4f5llCXjOV8Um4dUrQmYiTVyeFFRQYlSialMw0WK4dPpMToVrSlS6OrkLUlJUQO4cfRjhEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpEe067Vjnam7TmZIySTB6J4YcMVxfD3huwiJLsvjIWWRixmLN8O226uFU5m+dsuxkPGtttxMRluDyzCRlXJclKNY8848cdxucqUsqoaHjpKMO6FoQr+1qAASl6mcCpKwyjJTICroAGlHibmo5nzJUzJEwqwzDOPD8NSFPLWiWtqirSASgmrngrSsAKVTIpkLvLjHs1YA+J8SbAeeOGHU/Ttv56x1voO513tt7wfq3QHFTLBl0xRPoRoiBmi+7FhNO4xMgkkqpQFKY5tKnxXvf6w3ElSk+8bRj509P4uIBn/MP9b5AtuTfYOY/Tx/RFfaqHij4VVHgFm/E5UzPfg/QSVZVVULKKzH/C+ZPFNQJSFKUipqMj1s6Rl+eqUmnEvAazKyDJnz5VfWTOq2nVMq7ybg0CkHRQGlOShqD5G2MePYyVNVKU4uP3knQj9eRi9NPBaUqQapOx1FLEHkQbEbeBuj6SVJWkKRoq7tfW4I0caWZx5NJS+QQakU8/nSv4fTCKlIOwVbUEgv236s7epiQiI/xB+opSviDzIrim+v8AH6bbziMywdDfkfT0tqfk8SkRNrK8v1Uc7Uv1xThHLRgCCx7tYBtfpoiVKbVPVwQfTUWfy2iSiJ5jU7G3lqB1JA5DFOFgWNmdiLaa97ObdxEZl21s37wYXFndz8HiuiK/nI+fPcaU8K9BbFOE3dLvu4Bc6+/R4jMlx+XTU/pr6cvWK4ib6g3/ALJJ6i3SvPytRuhTtuXPXm/Tl1iP2QuxULNe/oX2OlgeYG9YRG9DtXunTpoa9b8vE0YbqbbS9uYHxN4sMrqG/wBYMX7295vr25iLIp8RSK3rQemhPjfqcUAfYE9Xf4gfXaKCUW0B2DHfqyjzHKKgi66LJ8k/U/icV4W1H/MB9bRaZJ1KfeD5flJ3jkIv+e24KfrQeeuKFJGx+PwinsjpwH3X/wCWPost5dzXnJ9cLk/LmYM0xTau45D5akkznj7ayAe4tqWQsUtCqEHuqSDQg0xNIpampJTTU8+oULFMiVMmkE6AiWlREfKxbGMFy/LTOx3FcMwSStPEmdi2I0eGy1JduJMysmSUqS4ZwSHDR25B9lvtRzBsOwHZz47RrSrpcheEme321AioIU3IFAgi9dORNsfSTl7Hlh04Hi6xq6cPqyPJpB+POODT/GbwbpVmXU+KvhtTzAWKJ2eMsy1AjYpViILxFmHZl7TcsBVMOz1xxgQNftfCjPMMAACSauSNANNfDpiOdgeNUyFTKjCMSkS0h1LnUNUhKRa5UZSQPPruImpfGLwgqy1L4peHNT//AAM75bm9P3MS+jaPhorhbxWgnzDRvDPiDCRKbqh4rJ+YYZ8A2qpp2WpcAqDcgHa9McIrM4ZRw+pXR4hmnLtBWIuqlrMZw+mqEh2/FJn1KJqQ4I/Eh3Dc4+/KzxkeegTZGc8qTZRICZsrMGEzZZPILRWKST7m5REVw04m/wCzrPI/9lJ8B5gwN/T8sY/7e5GItnPKx2YY/hIF+1Xp3DlttpxnTJQ/+sMsX1bHcK67iqEUVcNeJwB/83ueBrYZSnoHWv8A1eKjrf8AOoz3kc//AFhlYnrmHCR6f5Xr9dRUZ1yTqc3ZZJ64/hdmu4/ys/HrFBXDTid/s6zyf/ZWe9dKQFR5nFRnvJH+meVBd7Zgwgt//wBdvXSL/wBt8kA/9sMrJ0/+3sKJ6v8A5WT5fh19KKuGfFC9OHeeRp/+k56TSh1/6vqaaUqAb3rq/bzIu+c8qk3d8w4Sm7uCR97e/wAGtF4zxkcm+ccsK0/+3sLa2n/zXvDM1zpEZXDHijU/+bnPZNLf/ZKff/D622+Ib1Bxd+32RR/9aZUA/wD6hwjbmTV6N59YlGeMjv8A9scqp01x/CibuP8A9LJu2gY8ndojL4YcUqEf5uM9jnTKU+PUX/Z9NCbkmo0OH7f5Ev8A/GmU+/7RYR0//bLfDTeJBnrIo/8ArHKyj1zBhQDjX/5tyNrPz5xHVws4pH/9uM9jxylPrf8A+fQYft/kTT9tMpvy/aLCP+si/wDbzIwA/wDjLKzasMfwkC77mr62t53MUzwp4ok34cZ7qf8A+pT75f6hiv7fZE/00yp/xDhHl/8ANw/bzI+2ccrB/wD94MK+JqyffH5/mp4of7Oc9f8AZKff+Aw/b7Iv+mmVP+IcI/6uKft5kfT9ssqvy/aDCf8Aq4f5qeKH+znPX/ZOff8AgMP2+yL/AKZ5U/4hwn/q4r+3mR/9Msrcv+0GE68v/wArj8/zVcTxrw6zyP8A2Tn3/gMV/b3Ix0znlU//AOw4T/1cP27yR/pjlb/iDCv+rj8/zWcTf9neeP8AspPf/AYr+3mR/wDTHK3/ABBhP/Vw/bvJH+mOVv8AiDCv+rh/ms4m/wCzzPH/AGUnv/gcP28yP/pjlb/iDCf+rh+3mR/9Mcrf8QYT/wBXH5/mt4mf7PM7/wDZWef+Bw/bvJB0zjlY/wD+fwr/AKuH7d5I/wBMcrf8QYV/1cbIXsAO0Hn/AIe52zl2SuImWc0yzJ/EBMw4g8NJpOJRN4KEk+epNL2BmjLoXGQSIZEPmvLMAicQ5+0w6IWZZViGm4eLicwrch+8fBjxPytVYqrKEjNGX66dihm1OFU1LjWH1NSuskSTMqaeRTyqhcyZ7WkkrqCJaXQaWYopV7RSk+XH9JBkDKOasCwHxkypj+X67H8uKpss5pocOxPDqqpr8vVtTMVhOJ8FPVKnKm4NitQqimgSZqp1JjEuYuZJlYYlM3a7xtFHjzDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGN72qPaW/8nDsmZxXJphEQPEDix7zhdkVyCd9zGQL0+g4hWZ8wNvodbiYL9iZUZmqoGZQgU/CZijJAlBZL4iWeG56xr+p8AqTLWpNXXvQ0pSQFJM1J9vNdwpIlSBM4VpcpnKki3FxDrnxSzJ+zmU6wyJikYhir4XQlB4Vy1VCVfeagKBC0ewpRNKJiHUioXTtw8XEnSVQBQHeh+Z/p+qY1lP5jyDX5WcjsQDbSNKlmzc/gPoRPbH1AA8AT/Qb1xESwJiFRZPYe8nX4ekUJvJ4aeyqNlUWP9DFslAXSqmHge+xEN0IIWw6EuIvRXd7iwpC1IVirYhjvbW/IcgSC1v0t254CeNWafs8+LmSfFzKE5ZxHKWLyamsw7jCabMGATx91zBluuCgZaqPHMInVVAuYU+1op82TiFHMkV1HS1MrxvMpfFSmPi5bGo93FQT62Hk1qkqQbOIVQd5t1BS40ug7za0qoK0GGoEG/rseo6cunKP23+G/iFlbxXyHlPxIyTiAxPK2c8Docfwaq4TLnCmrpQWqlrZBKlUuI4fPE6gxOjWozKPEKWppZhK5KiY7TymVVF0k1Wnn1H8w0GxFQbaUjncqaZZ5pOo+Y6/HeLwhaXEhaTUHfTxFNQQagg3BGEfSSoKSFJLg6H5dxuI54Rc50/j6cvKOQWodfHCAYWuO3Tp02Zm1vFRL1NRpyJufM2ve2twcIo3FrwnVibEPyO5OhJI6RVEQdK21IVz86inj4X1NCPXR9xrofr1tFpQk24TbdP4m7C7m+ujFoqiJHJJ8Ca6iw+IV9NeYxVn52c8++r/y6RaZY0c8xxA2bcm5BGwZ79DFURIOxGgA5+Nfz1G+9Dp8mf5j6vtFDKJdikuBfn5akaMfcGi/5akOZM5z2WZWyfl+e5rzPOohEJKMu5blMfPJ5NYtZARCy2UyxmKmEdELJHdZhodxw7IO0kimn1c2XT08ibU1Ew8EqRIlrmzpiizJly5SVLWT/dSlRc2ePlYxieEZewysxrHsUw3BMHw6SqfX4ti9fTYbhtFITdU6qrqyZKpaaUAC8yfNQkbmM4fZq9hzxrz61C5i7RWboLgzInmmH2cmyJELmziLFhdFutTJ5l85UyqlLKh7t37fmiPEQHIeNkkCW/eOdq4H4S4nWBM/G58vC5JAIpZPDUVqn1Ewp/yenYMx456+J0qlIZz5yeLv9I94eZaXOwrwpwOp8QMTQuZLXmDElTsDynI4HSmZSS5kn+u8beYCFJ+7YLS+yKJ1PiNSFlCM1/B72W3Yq4PwUC3A8G5RxAm8MlH2rMvFxR4hzGZvooRExMpm0OjJ0KuoSAzJcrSqEFEqVDl0qcX2jhvh9lbDUICcMlVkxIdU/ElGtmLP95cuYkUqTdmlU8tJ14SXJ89c9/bN+0Ln2oqFVOf63K9DO4vY4PkUfsrR0cpQP9jIrqBasfnpuXmYhjVdPuQJvBwoHviU5alUkgISUyWVS+TyqAaSxASuUy+Hl0ugmE17rEHAQTTEJCsJuUtsNIbSSaJGOWy6aVKQmXKly5ctA4US5aRLQgD91KEhKUjoAAI1rrMUrMRqZ9diFZVYhW1SzNqaytqp1ZV1Ew3MyfU1Cpk6dMNnmTJilGzqMXUS9NLNqPShNK7W7tvXpbS72Pbs5+uv00Yv3qwI5tqH+B6D6vVEvNP/AESvPvWPyPlWn1xcJI6e8/HT09YtNQzlwLWGn6dL+7nbJxlGSZigzL5/IpTPYFRJMHOJdCzKGCjUd8MR7ESyFgUIWAFA/dUKCvx8dytlzNNErDMz5fwPMeGqJKqDHsJoMYo+JgCoU2IU9RJTMG0xKAtJAKVAgEZFJjOIYbOFTh+IVeHzwwE6iqp9LNbdJmyJqFlLv+EukvcXjznnfsa8Ic1tOOS2UxeSpoe8pEblqKUiEWpQNERMmjftUuUykkqIgG5bEKJAVElACMaq+If2EvAjO0qZOwjBq/w/xg8SpeIZTrFS6GYpX5ZdZgGI/fcJVToLq4cMk4TVEkBVYZaUyx2RgXjhnTBlpTU1snHKQMDIxSUlU8C/EqVXU/saoTFCwNSuqli5EniU8eHeJ3Y64l5CRFzOTsIz1l6HBdMbI2Hm5zCw6T8Tkfl9anooe6up1cqiJs02wkxL64dtLoa85PGX7D3jJ4XSq/GcvU0rxLynSAz1YhlmlnjMFHRi8ydieVVKn1p9h+JU+ZgtRjcmXTJNZUrpJSZyJHfWU/GvKWZFyKSvmLy/ik0hH3fEJss0M2aSwTT4iyJX4yAEprJdGtUxQlSkzVlBX5ZVBFKlJU33VJUpKkkKCklJKSlQI7yVpUCFA0KTVJAqRjR+ZWqQpaFOlaFLQtKxwKStCilaFJJBCkqCkqBHEFAv+IR28JgUApLFJSOEgcQKSAQUnQgguC7KBe40/Psunwg0OtCNK7DStd9vXFhq1K0e42D+87gw4iXckcxqwvyYaahx73jiYUDVIF61vWhtvSwpzNaabYp7d9Tozv8AHX+QPnFA2zG/1p/O8cTDWNQSRfe1KVoSDoN9gLilsBOAZlalncfJreZHWzwcO4dyx2IuTvrpoTrYO9zxMPXQWsampsb+B08BauLvbANcP09LM7e97m0OfPUBm5e7kQNGtFFUPYilwRoDqNTuRUUoBvXQgYkTPUWKTbRyQLadyzfCxivPbfe7sWbpe931e4ikWCCbCt9a1PLUk3FbEC1rVteiZ16gAu2xHPld769xHJ9ma/U3G1jd79bxRUzetCa6VGx1qTYg7geoqBiQTLgnbdy+oa/qNCG82o3MHQNbk1wHNgxbXTSKC2RyAANagHQU2UaVudh43oZ0zTd1JGx0JvsHubvZvK8VDd99Brpq7kDVt9xEdbQv0PMnewoANNNetd8TIWLC+3QN3Jb0FtG0EV5sNSC7Wu12YlzyYbBthGU1f7tDXS5162t4kEcqa5CFsbkMzu/933W6DU+tL/is/YHpttpyd7ADQRlsKINUUFjsKeZBsfwsSTXEwnJ5vdiQH+Funm/Q3sQ19DdzzuHAJ33fvbS55cnc1yfmORZqkcQIWdZcm8vnkriAVqDUwlcYxGQylgKQVt+9abDrYIDjZWgkpURj7+Xcx4lljHsFzJgs00uLYBitBjGHT9RJrsNqpVZTLKUqHFL9tIT7RHEAtBUgnhURGHiFBS4pQ1uG1iPa0ldSz6Ool6ccirlLkzACXZQQslKmBSoA63G0pwzz5K+J+QMpcQJMktS/NUkg5qiGW4l1yAiXUdyPljzqUpQ5ESuYNxUviFoAQt+GcUj4CDj9Knh1nbDfEjI2Vs9YQky6HM+DUmKIp1LEyZRVE1HBXYdOmJCUrn4bXS6mgnrQAhU6mmFH4SI84Mw4LU5cxzFMDqyFT8MrJtMqYElKZ0tJ4pFQhJJKUVEhUuegEuETEg3ePucc0j40MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGn97bLj9E8T+1UzwolszRE5R4DZeh5GiFhnGnoVWes1Q8DPs4RxeaTVcSxBHLeW4mFcccEvjcvRrQSxEvRqDr54lYsa3HBQIXxU+FSkygkEFP3qelM2pU4F1BPsJKgSeBUlQDFShGo3jTjysTzSnCpc0KpMDkIkBKSlSTXVKE1FWtwLqQn7rTqSSfZrp1pZKlLBw7oFwOVB6XJ+f60x1oXuR1L8wWDeTx04vUdHLdv5RPbGh5BR8bin0odMRrNu5H6/KIl8uqU+jP8ACJzYJNtzQeQJPy08fMYq9ugfrqAPf8PWBRBHx7k3+I6946a4w5VD0KzmmDaSHYRLcLNghJCnIVS/dwsWog0UqHcKYdxSgVll1kd73cNQQrDh9xbYdS/n2Fy2jR7wf0N32qlYTjmK/ZWzjiVQrDcwLxLNXhJNqp3tZFBj0iSqvzZlGnCyqZTyMbopdRmnDaeTwUUvFMPzCsoFfjqDN88Yhj9FEVmHlMKqKlBPxoFL/wAydPj86KFjsQiaTNMpV7oV+Ycv9YdR79DF4QtK0hSCFJIqCPp0I0I1Bsb4R9EEKAUkuCHB6dtj0NxHLCKwwhDCEMIq55mPb3Yp7B3GTtr5yXLcmQ5yzw5kMbDM584qziEddy/ltDzaogy6Ww4dhl5mzVEQ6KweX4CIb9yX4SKncdJ5Y+iPPK8rZQxPNVSUUqfYUMlYTV4hNSTJkOOLgQl0mfUKTdMlBDOlU1cqWoLjXH7RH2mvD/7O2X01eYJoxnNuJ006bljJNBPloxXF1S1iV97rJxlz04NgkmcpqjFKqUr2ns58nDabEK2UqlG472TOxDwD7HmVW5Nwsyuh7NEdAQsJmziZmFEPMM+Ztcao679smvuW0SqVOxI9+1luQsy6Rsltl1cHFR7Ko13ZnLuVcHyzTiVh9ODULQlNRXzgldZUkXPFN4R7OUVXEiSESQQCUqWCs+BPjf8AaL8T/H3GlYhnbGly8FpqqdPwTJ2FKm0mWcDQt0S/u9CZi1V1ciSfZzMXxOZV4lMCpqET5NMsUyPUOac25QyHJYjMWdMwyfLMlhRV2YTeNahGlukEtwsKhxQejo100SxAwbb8XEuENQ8O44QnHNMLwbE8brJdBhGHVOI1kz8sikkKmqCRrMmFI4JMlGsyfOVLkyx+KYtKQ8a9YnjGG4LSTK7FsQpsPpJQ/FPqpyZSSrZEsE8c6as2RJkpXNmK/DLQokCPC2fvaJZClMS5AcNsqTLOTjfeQueTp45ckynP3DAwZh4ucxzX/wDIYuHkqwQQ171Cg4O7MC8A8YqZaZ2YMSp8JSpiKOkQMQrG3E6aFy6SSv8Au+ymVgILrKCOE9L4548YRTTFScAw6pxUhx98q1mgpCrYypXBMqpqP73tUUirEJCgQqPME+7cfHnMD6lwU5kOU4RRIRA5cy9BKQkfuqXGT4z2Yrc7oAcUiMabKiVJZQCEp7Ho/BjJNAgCbR1uJzAzzq+unBR3ITKovucgB9EmUpQAA4yQ567q/GTOlfMJlVlJhso/lk0NFJIA2Jm1hrJ5UwuRNQklyEAECPj3e03xyi1FbvFDNaFE1IhI5uBbv/C1BNw7aRyCUgDlufqJ8O8nSQEoy5higzEzZJnK81TStT9SX6mPlq8Qs4zi6sxYk5v/AGU72I/3ZSEJa9rAchykQ3an48S8hUPxOzE6RtHKgZmk6WKZhCxQJqBuDemhxZM8N8mVFpmXaFIvaSJ1P6ewmS+Z2b4RdL8Rs5yC6MwVym2nGTUaEa/eJUz4HQnW8dm5V9oDxly64lvMsLlbPEDX/S/b5YmSTYISPuw0fIXISAQSAQVxkkj1Kt8SSFY+FiPghlOvSVUEzEcGnN+H2NQaymc3JmSK1M2cpuUqrkAcjpH3sP8AGvNdEQmvl4fjEh/xe3kGkqW0aXPolSpIYfvTaScbOI9f8NO35wXzopmX5yEbwxnTi0Nd+dqbmGV3VOK7qFIzFCNN/Y0JNDEOzqWymEhUkKMY8gOuJ6tzD4I5swoLn4V7HMNIlJWBSJVIxFIS5KVUE1Svaqb8iaSoqZkwuPZJVwpPaGAeNOVcVKZOKe2y/VKUEvVkTsPUSWBFfKSn2QButVXIppUsX9qsBSh7Yh34OYwrEfL4uFj4KMaQ/Bx0DEsxcJFsOJC2n4SKh1uMRDLiaKQ424ttxJBQsgjHT02VNkTFyZ8qZJnSlFE2TOlrlTZa0llImS1hK0LSbKSpIUk2IBjtyVNlT5aJ0iZLnSZqQuXNkrRNlTEKDpXLmSypC0qBcKSopULgkR5m409mTJnFJuJm8A1DZXzqoe8E9goZIhJo6lBQG5/ANd1EZ3/9GlUxZSiZtdxol2KYb+yOaY/aM+xf4deOUitx7CJVLkbxKmD20vNOHUgTQY3ORLKESM2YXTezRiCZoEtKsYp0oxuR7KSVT66mknD53beQ/FrHsnLk0VSubjGXweFWGz5jzqRBVxFeGVMx1SSklRFLMUqjXxLARJmKE5OKfOvD7M3D+fROW81Sx2XTGHCXEVAchI6FUSG46XxSR7mMg3SlSUPNE9xxtyHdDUQw8y14OeJnhtnnwhzXW5Mz7gk/BMaowJ0srPtKDFKGaVCnxTBsQQBIxLDakoWhFVTqV7OfKn0lUinrqappZO52X8xYRmjDZWLYLVyqukmkoWzpnU04AKVTVUlTzKeolggqlzACUqTNlqXKmS1r+QMKeQ3Gn5DbenyxwATy91dbXLvbUv5amPtW1Z7Wsx9S3O2nmIpqhrXCqeBudvvJr4i9Lcr3ieST1JuTe3JiTr5g+QitjoAOgZ7Xct0OuvNtTSMNSlE7GwFTanMV3rod+WJkzyXdugDXHIB3HuPPSwB7gq5HQa9QSw1Go5GKCoc6AGhtTrXrSp8KX5byoneoPRr2A2uddNLQ63vo9vg+789+0UFMEmw5G9QbilqA0rtY1vcbypmszkMHZ9Oe7aNcEdRZ4DS2/m+/0Aw5RSVBuEGiDp+98Ngb2JrQVrXbUdbxUoBJVMe9+C4u1u45ctelRcsd/N376t79i7RRVBU+8oA3FBcV8SBvQ6G/PTEwqd0pJ5EkA8tA/wARaKltWLEbMNzf97e2o7XvHXDtp1BVUDU7UuDSgpcUxPLnLU9+FiQQl+l3JJfVzbaKhiLh2STe+hsz8tmiC4hIBCQEig0HI3+nmcZMskqDkm5YEk6p4tenv9BAXUz6gkPfVPPz827RAeTZQrqD8jU/W36OMxB18vn9fyipuFFtQkj69fLpFud1Pn/ynGdLLl+Y+Yin7pPQf+I/CMx/syeKSpllvOvCKZR5cictRLeb8sQjzilOJkc3eEJP2INBJDcFLp39ijXkAJH23MrjgKy6vuevH9HP4kqxHLmbvCzEK4zKjL1UnNGXKWcsqmJwXFJiafG5FIlyEUdBjCqSrmpZLVeYJkwFZmr4NT/tEZcFPiWE5op5ATLxCUcMxGahICTWUqTMoVzTqqdPoxOlJVf+yw9KbBKXyo49Lo1shhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPjeIueZFwxyBnfiRmd9UNlzIOUsw5xnjyEFx1Eqy3KYucR/uWgQp6IVDQbiYdhB777ykNNgrWkHHq6mXRUtTWTi0qlkTqiaQHIlyZapi2G54UlhqSwEYeIVsjDaCtxGpUU09BSVFZPUA5EqmlLnTOEbq4UEJSLqLAXMfzxc65vnHEHO+cM/ZheVEz/O+aMwZvnkQtRWt+b5lm0VOZm8pRCSpTsbGvLKiE94qrQVpjUarqJlXVVNVNPFNqZ86fMJOsydMVMWX1upRjz8r6udX11XXVCiufW1NTVz1EuVTqicZ0xRJAJJWsl2HYRZUfeHXX0xhfunkNOdyP0jBXqO3zMTW7U8U/8RUfwGIlmwHf69CYjUXUOpUfcf1ie1qnxUflT8TjGVv0AB8y/wCnvjHVZhzKfkfcIkuwzMXDOQsS2h6GimDDPsrAUh1l5JbebWk2KXELUlQ3BOI1WKj3j62XMyY5k/MeBZsyziNTg+Y8r41h2YMBxakWqXVYZjGD1kjEMMrqeYkhSZ1JWU0mcgggOgAukkHxRm/L7+U8wRsnd7zjKCIiXvrSUGJgHlK+zvCwQpSe6th8t1SIlh5KSe7iwpCmILdLFulgNPpo/bJ9k77Q+B/ag8DcneLGFIp6PEq+RMwfOeCU89M8ZczxhEuRLzBhBIUZiKda51PjGECpCKqdl/FsIrJ0tCqnhj54EEVH69MREMW/X5tGx8V2H1Mq3LZPxJHP+JINu9a4/eHWhwieTOMssboOo5HmOvTcdbxeEqStIUkggioI0PhphH0AQoAguDcERywisMIR779n72FM4dtrikqVh6Ny3whyY9ARvFHPUO2z7+FhIhxS4XKmWvtKXGIjN+Ym2IhuDcdYioKQwLcTPZnDxSIeDlU25lkzKFTmvEDLdcjDKUoXiFWAHSlRJTTyOIFKqmeEqCCQpElAVOmJUEplzNXftTfaYwD7OeSxW+zpsYz7mGXU02S8szVzPZz58pITPxvGPYqRNk4DhK5spVQlE2TU4nUrk4ZRTZCptRXUG7jwq4W5C4MZEy3wz4Y5Yl2UclZUgUS6TSSVtdxppAq7ExkW+sriplNZlErcjpvOJg9FTKbTB+Jj5hExEU846rarD8Po8Lo5FBQSEU1JTI4JUqWLAaqUol1LmLUSuZMWVTJiypa1KUST+dHOec80eIWZsXzjnLGavHsx45UqqsRxKsWCtamCZNPIlICZNHQ0klKKagoKWXJo6GklSqWlkypEpCE+Z+0922cpcDVReTcotwOcOKXulJiJcp1apHlBTsOlcM/mV6GWhcTHKDrb7GXYOIZi1spU5MYuVNOQZje9/DTwbxXOgk4vipnYTlkqSqXUBIFbiwTMKZkvDkTApMuQOBSFYhOQuUFkJp5NUpM32OuPiP4wYXk0zcJwtMnFcycJC5BUo0WFlaAqWvEFy1JVMnHjStFDKmImqRefNpkrkmdhczxxVz1xWzA7mXP+ZZjmKaOfAwYp1KYKXQ/xFMHKJZDpal8qg0HvK+zQMMw244px94ORDrzrm4eC5XwTLNAjDsDw6Rh9Km6xLS86fMs86qqJhVUVU02HtJ0xa0pCUJKZaUITqLjOZcZzNXKxHG8RqK+pNkmYoCTIQD+GVTU6OGRTygS/s5CEBSiqYrimLUtVnhosfCSaHSuxF/xv47jXGRNku9ut7dux+OvOMSVO27+e3TVme/UPF8YjqUv0GnkDQgiupG/LngrktqLDZgH66Hfe/aM5E4NY7Bzr6jfv8dTckTAUA71TyJJP1GvhT1xjmQHcgDn9EfwtGQJ2znycADnp11do4rmAp94Gm1TbkTc/rxxVMgA2AP10HxfSKKnvufNz6ON+vui2REb3rA13ua/971NyDTpjJRJ0tbtcctrfBvOMdc1rktuX1PTZuXwLCLBExQob358qEaX1/wANyT9CVJ6fLv2HvPpGFNmvZ7Ne79Pd07C+vcfBXtScUuAUzbXlSbrmOV3Ylt+b5HnTr0TlyZICkpfXCtFRckkyea+D9qyksPrWiHEc3MIWHEIri2b/AA2y1namUnE6UU+JJlqRS4xSJRKr6csSgTFNw1dOlX4jTVIWhIMz2KpE2YZo5RlPxEzFkqoCsNqlVFAqYldVhFWpUyhqACAsoS5VSVC02FRTFCnCPbJny0CUc7vADtJcO+0Zlpc1ynFmX5iljLJzRkyYvNieZfedUttMQO4EImcniXEK+xTiCQWHkqbZjG4CZB+XsaU568PceyFiApsTle3oKlaxhuL06Vfc65KQFFF3NNVy0qHtqScRMSypklU+n4J69y8j5/wLPdAajDJvsa6nQg4jhM9afvlEpRKQtgwqKWYpP9jVyQZagUompkT+OQj6nirwqy3xUy67JJ4wlmMYDzsknbLTao+Sx6mykOsqNC9BvlLYmEuUtLEay2kFTMSzDRcNqn4+eAeSftBZKqcq5rpk02JUyaipytmmmp5S8Xyxi65JRLqqWYsJVUYdUKTKRjGDTJsulxWmloBXTV1Nh+IUPc+TM6YvknFpeJYbMMyRMKJeI4dMWoUuIUwU5lzAHEuegFRpapKVTKaYo2mSZk+ROw/51yHPchZlmGWJ/DpZj4B0dx1rvOQ8wg3Cr7LMIJwpT76CjG0+8aKkIcQoLh4htmJZeYa/Nj4reGmbvBnPeNeH+dqRNHjGDTv7KokKUvD8YwyaVnD8cwietMtVTheJSUe1p5i5cuokrE2jrZFNX0tVSyN88t5iwzNOD0mNYTMVNpapJ4kLAE6lqEcPtqOpSCUy6inUeFaUqUhSeGdKXMkzJUxfyn7PcOjahUm6qIoO8TUg91XM1oabY66NagX4ypuTqHutf1axtH3mfbpe5vtyY3t00NjHBUtCT8ak6qr3RU1Ar9406bW8Nb0V5IHAk6BuIsNW0D9NdvOAYNvpv7jblFEwjKVAFJVcak7AkWFBTpSnOuJE1M5QP4uHnwvv3JPN7jto1bM4G6h6No7/AKxFWlKUgJSkUSLAAUvfQD9a4yEqUVB1KLvqSdjzJi17jsf/AMPw25RDcFUkdFg87/4188Zqf3fKL9xs/Dp5P7384tbopX+1+dMZksukDcAP5vFPkkg+awYtztiL6pB/Xp+qYzpX7+llfw+u5i9IfXkof+H9T6nnFtd08lYzJf50+X/gVBJuB2b/AHS/y93KID+/9/GdL38vnFdj/gHwVFucFQetL+IUPwFsZsu3D2HvDRa34f8AZPuUD+vrHofsicRUcMu0Lw8ncU4puUzeZf5ITohwNNpl+aQZS3ExClEJ+yy2ZPy+bRAIUS1AK7g953CNkvsp59R4d+OeRcXqZipeGYriX7LYuRMEtCaHMqRhcufUKUQn7th+IzqDFKgEKJl0KuAe04SOAeKmAnMOR8dpJaQqqpaYYpSOkqV7fDSqqVLlgX9pUU8ufSo/1p4c8LxsrY/QrHn3DCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYqfbLcVmuG3YfzlJGn3GZvxczRlThpK/crCXAy/Gu5un63UA+8MG7lzKc1lr6xRsPTKFZdUQ+lp3g3iJXCjyzUygWmV86RRoY6AqNRNJGpSZNPMQdnWl7Fj1d4wYoMOyVWSUkibitTS4dLbXhUs1c8kC/Aaelmy1GweYkF+LhOl+1oOfdH9fwxrirU9z8Y04V+c/7XxEXBH3h5/Q4g/d8h8VRCv8AMfL4CJze3gj6LpiGZt5/KI1apbX8TekTm9U/2V4xzqt+aYhVqny/8Bi4J0RTmj6jEStFdjECtT3PxjrXi1k85ly6Y6CaW7N5GH4uHQ2ApyJgyEmOgwnVSw2lMTDpTVZeY9y2lSnyDbLWEqY6KYatdmFnYvu/ePT7+i0+1Yn7P/jkjImbMSp6Lww8Zp2HZexeorp5p6PLmcpS1ycoZmXPV/YU1LUT6iblzG508yKeXQ4pS4rWVUqnwIJV47beFRSpGtdyCBe33hSlT941pc1BlUgKdru7jRr9dPR7PsI/WcldyCWIJBBDFwwLg7h/Lo15iHAoddeYI5jne1NdKjECkEH+e3N+ly7b8ok10+vPtcmw1iXDvllV6ltX3huk/wASf+8ka66i9kTSZxlljdB1HI8x821EXhKgoBSSCCKgjQjCPo8iLg3B5jmI7S4K8H868fOKeSeEHDyXmYZsz1O4eTy8LChBy5hQXETOeTV4f/hpNIZWxGTibRN1NQEFEFpDr5aac+hhWGVeM4hSYZRI46mrmplIeyEA3mTph/dlSZYVNmK2QhTAlgeFeIuf8ueF2Scx5+zZVfdMCyzhs3EKspY1FXNBTKosNoZZ/wA9iGKVs2nw+gk2EyqqZQWpEvjWnfR7M3Z7yH2XeDuUODXDyGUmT5dg0OzOcRDTDc1zZmWO92ufZsni2EIQ7NJzFJ75SO83AQLUDKIMol8uhGm9wcCwWjy/hdNhdCn+ykJeZNUAJlTULYzqmbwhjMmqDtcIQESk/glpA/MR4weK2Z/GnxAx7xCzZOBr8Xn8FFh8qZNXRYFg1OpacMwLDRNUpSKLD5CuHiLLqqpdTX1HFVVdRMX5r7cXbJHBeXq4XcOJgyrinPoL3s0mrKkuHIEljEVYigC2tk5nmzKlLlEOtRVK4QidRTSS9J0xmz/gj4QftjUDM2YpChlihnlNLSrBSMerZKvxyiQpKxhtKscNVMAAqpwNFLUeCrMnTPxo8WhlGQctZfnpOZa2SFVNUhl/1FRzQOCaxSUHEapBJpZZJNNK/wAsmIHHSCdgmTMYiKiHoqKiHoqKinnYiKiYl1x+JiYl9anX34iIeUt55955anXnXFrcccWVqWpR7yt41U0uVLRJky0SpUpCZcuVLQlCJctACES0S0gIloQlISlCQlISGADMNKRPVNWubNmLmTJilTJkxalTFzJi1FS5i1rJUta1EqWtRKlKJKiSXi/QsXSl+XnqDfYiu4pWm9h86bK1bX5W7HY31G73fMlzWAc2tf6056aM53N9YjQKXsDz5Wpp5mpFK6m9MJckEszHl77N52Di2gjPRN699bm+u4107aARdmo4ilVH1NfzAFfE74w10/T3DnpyPkR7gIyEzuttObHX4NoOdomJjxrc2FgTUdampr5A/OsJp+bjmwt8SImFQwDnt8AN/R/J4LjxfUE8ya15/TYbmvImm/g4+VvnA1BNweh8+lufI9NIgux381utf8fA64nRT2/L7hft9GIFzjz3332J1059zpvaIiMqCK+Vxr6UtU60BPljMlym0D6eXX16A2taMZc1t7bE69fXmWYWOxiwxEXYgHT9frpyBJxnSpJd2fv8Db3XJ3jBmzX3YPfUnkXfbn8L/iueR+JWbuFmbZPnrI07iZFmSSRAfg4tg95p5pRAiZdMIZRDMwlUwZBhphLolK4aLh1rbcTQIUmHGcuYTmXCqvBcao5dbh9YjgnSpjBSFBzLqJEwDikVMhX9pT1EsiZJWEqSRcGfCMwYplvFKXGMGq5lHX0cwLlTEE8K06TJE6USUT6acAZc+RMdExBKVB7p2V+zD2k8r9pnh0zmiVpYleapOYeXZ6yol5xbkinam1rbfhFvJS5ESKcpadi5LGVdq0h+XxLxmUsj20edviV4eYl4dY+vDagzKrC6sTKjBMUKQlNdRpUApE0JJTLraQqRKrJTJ/EZdRLQKeokKV6CeHHiBh3iDgSMRpgimxKk9nT4zhgUoqoqspJC5ZWAqZRVQSqbSTXU6QuQtRnyJwFy498K2eI2V3X5ewk5rkTb0XInUqS2uMbp72Jkjy1gJLccEn7J31tpYmHuHC61Driw752/bW+zPS/aD8NZ9ZglHLPifkilrMTyXUpVKkzMXkhIqMSyfVTZoEtcjGkSnwtU6bIl0WOoopy6qnoZ+KJqNkvCrPkzJePIlVc1X9QYtMlU+KyyFKTTLJ4JGJy0pdQXSFX+UcCVqm0ZmoEuZORTmXipiEqbUttxKkOILiVoWkoWhYJCkrSoApUlQIUkgFJBBAOPzaqlTZMybJnSlyZ0lapM2TNQqXNlTJRKFy5ktYC5cxCgUrQpIUlQKSAQQN7pagtKFJKVJWUqSpJCkqTqlSSCQQpKgQQWILiLY7tXUlR/4aflXqcZMsMA2jJ96gYfXz+ukW5f3uV9OdqfjXGXL0Pv7bfP6aA0G91F9mcAe9/SLc593+6n64zkfmHn8DFNx2PxTEBwgJPOiz1oDT8KYzkaJOw4Yv8A3k/7PwB+MWx3f+1+eM2WGSObMfJ4p/5C/fjDe6Lc7Wo6JA/Xr+r4zZTfj58R+H84vSW9CfK36Hz7iLa7p5K/XyxmS/zpPb/wGCdRzt3/ACl/l9AtAf3/AL+M6Xv5fOK7H/APgqLc4QK8xS3gCfx8dcZssPw9gfd+sW/u9gfepvkYhB52HebfYWpt5hSHmnEmim3W1d9taTspC0hQOxAOPoU02ZImyp0lZlzZM1E2UtJZSJktSVoWk7FKgCDsRCalKwqWsBSVoUlSTopJStKgehBY9I2p+EudmuI/DHIWemi2FZpypJJvFttKKm4aZRMCyZrBBRuowMyTFwaidVsKudcfpd8Mc3S8++HeSs5S/ZhWZMs4PilTLlKK0U9fUUUo4jSBRuo0deKmlUbuqSS51jzYzNhCsBzDjWDK4iMOxKrpZalhlTKeXOV92nEB29tTmVNA5LEdh451Hw4YQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEI1n/8ApA2fmnJz2b+F7EXV+Dlue8+zaBCyAlqZxUjy7l6LW2DRZWuU5nZaWoVb7jyUH/SLp034r1QKsJokqulFTVTEvstUqVKURv8A5ueByuzvGuHj1XAzcvYYlX4kSq6vmofaYunp5CiHYv7KpAcWYtqY1yWtv7I/DHTitT3PxjXZX5z/ALXxEXBH3h+tsQD8p5HQ9iP1iJevl+sTWzp/c+RUDiGZt5/XuiIg8SehIPdv4RPa1T/eH4/Sv6tjHVbi68J8hb4t6xArY8in5JPzi4I+6joGyfCo/LEa/wB7z+cQkXPVRH16xNbFU16qFPEj8sQK18h8BFFliCCRwlJBBIOgDgi452v2jxRxcycco5lVEwTRTJJ2XY6ACTVuGfKgY2ABoC2IdxxLsOhVUiEiGUJWtTLndyJS+NL/AL6fwqZn3/ERoXbTmC0frt/o1ftWD7SPgPQ4ZmbFJdV4q+FSKHKWdhNdNdjWHIplIytnRaSpaZ6sdw6lm0eLVEpQWvMmEYzUTKWjpaygRN6zaeB3OorY18wNf7QpS17UxeQ7vobOR3ex0uwY9WaPRpE0ixY6N1f6256WJic29oLm1tzToaXHPQ6A74hVL1NtfrTqGv1IfbJCgpy+t3739+nIXi4w0T7o0NS0q5H8B/iTtQ/vDwNr4iLsAdtO3Ly9xcdsiTOMshKroPqk3uLOzm/NizkRtM+wv7LjGX8kZp7VmapQj9u56ejcj8LnoxIU9BZJlMahvNeYYBskoYOZszQYkTUU4hMciCypHJhVIlk8eMfsB4R5eEijqMxVMr+2rCukw8rF00kpQFROQNvb1CfYhRAWE0ywlpc08fjV/SXeNy8XzLgfgfgOIqOF5Zl0uZs6oplNKqsxYjTKVgWFVUwMqaMGwao/rRchClUqqjHaZU5K63DJYpc0XaM43yns9cIczcSZkhiLjoJlqU5VlD7wYTPc3TJLyJJK+9X3hYC2XpnMwwHIlqSy6ZxTKFGHttB4cZJq/EHN2GZbplLlSZylVeKVaEFZocIpVINbUt+ULIXLpqb2hTLXW1NNKWoCZHjt4h5zpchZUxLMVQlE2dJSKXDKRawgVuK1KVijpncKKAULqKn2YMxNHT1M1AJlxqzZgzfPc6ZinObczzSJnOYcxTKKm04mcYtTkRGR0W4XXnFEmiEAkNsMN91mGYQ3DsIbYabQj1IocGocGw6jwnDKaXSYfh9NKpKSmlJCZcmTJSEoSANVG6lzC6psxS5kwqWtSj5mVmL1uM19XimJVMyrxCvqJlVV1M1RVMmzpquNai7gC4ShCQEIQEy0JCEpBqQsXSlT9b/IDnevXxsmSjdw40trYW3+N9riKy52jfG3lv5dxF9YjK0odafiBS3Pem40FsYK5LuWte+1tT8bgxmy52lw+vmW5NpbpvrF4ZjiKX2sL9eleYsKfLGFMp3ezuP5ae52jLROZr/WxF/oHVg4uKI8Cl6AdK032Tr6jGKqnbTXb57n0cfrOmo8+2pHy7EbG8SkzAU+9XkdKeiMWewJ5egv74k+8Nvfu/yIgqYCla08qk+qf64exV9N+sDUO+pto7fIAxDcj7WPhtz6V3voPxkTT23c67cuoHKI1Tzcgt3bydy/TYcuttejSa3+uu40rzNeY8K5SKdmLMPLS/X4a894xlzX1L7/ABbXk4BfmNWaLO/GfzbEHa3PTz6fPGdLkgWLBty3O+9ratc6xiTJ1yHNy439x9Pq1hiYsEKvzB2Op8/r+ebLlOWu3xb5dHYM55DCmTXPfcX9LF+vnpt3N2aO0TO+zhxbkOfpeqJipC481KM8yBl5xtvMGUYx9H7Rh/dijS5jL0gTSRuPIUlqawkMldIV2JbXxPxF8PqLxCypXYHPEuVXpQqrwWtWhJVQ4pKQfu6+I/iFPPJNNWJQQqZTTZhT/aJlqTyzw+z3WZBzRRY3TmZMolKTS4zRJUUiuwuatP3iWQ5SZ8hhVUalAhFTLl8X9mqYFbXkoncpzLJZPmOQxsPM5HmCUy6dyaZQi0uwswlU0hmY+XR0M6glLjEXCRLL7K0mim1pI1x5a1tHVYdWVeH10iZTVtBVVFFWU01JTNp6qlmrkVEiYkgFK5U6WuWsEOFJIj01o6ymxCkpa+inS6mjrqaRWUlRKUFS59NUykzpE6WoEhSJspaFpIJBSoGMbPagyAnKmdxmGXw6GpNnAPxxSyAlqGnkOpv9rMFAr3BGF5mZIUe6HnouMS2gJYUB+eb+kW8DZfhl4wIz5gVDKpMp+LCKzGeClliXT4fnOjXITmimVKT+GQMUVVUeYpSzwS6iqxLFZVPLRLoFpTu94HZuVj+WVYPWTlzcSy3wUrzSVLn4ZOCjh00KP5zTCXNolWKkSqenUtRVNBPll0mljWgPQ0URT1AGvM10pjQJGrczblYG3k4Md2biztfXlr8/4xbnDfvV0qa9AKbdadNcZkoWNtWB63d/QEdxa8Bo3IBPqSfSx5xb3aAm/IdKAV18CmvOlfDNQL6de72HwPrFPkHIvZy3noNLxAetrr3L15qJrptY+FqXxmgWAG5YeQ/iPQxUdNh6cIt8B/JxFsdNCd6d4/qnUXxnI0A6j3sfnA+4Aepct9PvpEB0jvEcqAfT52/DGXJdieZJPezD4+sXCwJ/1fibe74Ra3Tr0AHqfyOM6WPxDk6vcOEfP+TiFwotsCPQFvO3xi3vKNFHofqQfWn61xmIGvl8/wBQfOKmwUOQSB/GLc7qfP8A5afUj1xnS7Hyb4e9h5ttAflI6J95JHq43tFvd/e8APQ1/H9GoGXKGu9yfRI/SKq1L3ZJPpofeQR0flGwP7OzNicydmyUSsqKn8k5ozNlh8qPxFL0SzmiGUBr7tMLmRphKh8JUw4KlSVU90vsJZlTj3gBheHFRVOyjmLMGXJpUfxKTMqJWYqdQBb8CafH5UlJA4SqSsOVJWBo7464YaDP9VUD8mLYdh+IIbQFEtWHTAf9YzKBayOSwdCI9043JjpyGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNM322GcXs0duzMMnWoLa4fcOeHeToW4+FmJl8Znp1NhUd2OzpFpINSFVOhGNevEioM7Ms+WdKWjpadPZSFVJ/wCapVGoHjLVmpzvUSiXFDhtDRp3YKlqriO4XWr1MYnEG58CPmB9cdefXrHUpsR9WZ9uw+ETUH4q8yD5EAfniEuARsHA9QSfh9a2L1Fr3H6fGJ7ZoANyDToQbedfr6xr0+t7fOI16vpcH129+sTmzQ+Br6gg+la/KorUYq+fMN7wR9fpGOoFtb6+YJ3vy1+MT0EUtsDX+6dvX6YjLvfe/reIle6xHUEf+mJzRNPE19UjTxUD671xAqxblb3lvc3wixbEf7P6kX6Bvh0j5fP2UGc65YjZQQ0mPS39rk8S4e6IaZQ4Pue84EqUlmJSpUJE/CsJZeWsNrcQ2UxoX7OYTs7KB3BPY6G4PTq0bUfYx+0pin2WvHfK/iImbWzMoVswZb8SMGowJpxfJWLTZQxCbKpVqQmfieA1MqlzFg6UTaabOr8Ml4eqql0VfWy52PVxL0LEPQkS0tiJhXnId9lwd1xl5lZaeaXSoC21oUhQNgQoa4+jrd20uDrysXFyS0ftBwfGMNxvDMOxrBq6mxTB8YoaPFMKxKjX7WkxHDMQp5dXQV1LMAHtKarpZsqokTUgFcqYlRDGJLb53IpQVO2t6gXBrYEEDU4oxAIAOmm2+h5alla6MHj7CJhDEcnZ9idue+nO+jR9dk/Ls3ztmrLWTMvtpfn+b8wSfLEkZVUodm0+mMNKpc0sJClKQuMi2EKKQV0Pwg4vk0q6ufIpZABnVM6VTygQf85OmCXLfdipY1GjsdAcfGcdoMvYLi+P4osy8MwPC6/GMQmJI4kUWGUk2sq1h2SFJkSZihxEJBYKtH9Erg5wzy7wX4XcPuE2VELGX+HmUJFlGWuvJQmKj0ySXQ8G7NY4NjuGYziJbfmsyWj/AEa4+NfcSAkhKdysNoJGF4fRYdTA+xoqaTTIJbiWJSEpVMW1uOaoGYtrFa1ER+WHPWcMV8Qc55pzvjaknFM1Y9ieO1ctClKk0ysRq5tRLoaYq/F90oJK5dFSJV+JNNTykqJIJjB17U3je5m7jLJ+EcseUJDwqlbUTNQHFBEZnXNENDzGLWW0qKFNSnL65NBQ7i0pfZjYueN3ZcbK/Rr7LGR04TkyrzfUoBrs11K0Uh4Q8nBcMmzKeSOIhwqrr01s6YkEoXIlUKrLSoDza+01nNWK5wpcqUyyKHK9KhdVc8M3GMTly6iaW/KU0tAaSTLUQFonTa1LlCkmMaMNGXBB0Guvypt56W5Y2YmSm25sNdNG0OjkjXbSNcZc0Br77czYNzB3v83v0PGbVpz2rfSoFq78rDW+MCZId7DS3J92v8tthpmy51g56c72e3QbW3NhreGI2m/Pz/4aa2N+pOmMBdOQSw23D78nPLr3G2YiboxG36WOunS/J3i6NR+xPjv56Vr8r02xirk809iPncX1015CMhE9mv6nXzZm5P8ApE9EeOe24A1vShSPl+OIFSASdPRjbqSH8ifhE4qPNr2bXyPvaJAjhY1FacwD/wAtsW+wHMev/qi8VHU+/wCYMfhjrGhv0IJN/wCzh7Acx6/+qBqBrc+Z91gIjrjxc18bA1FOXdpi9MkDqOQ/V29SPhEap/lycjTe+2uwiA7Hkix6fMC1vLntSgxOiSdks+pPyY6eZ7DeBc539fI3199mDE9otT0brU1/Q2oKc+gFLiuMtFOd7/T7W6bWDNYRjLm63Gt7n3nftFliI3W+lv18NxvodqUvjPlyG2a/e4Omr+v88WZOcFiOnU353PI/DeLFExYIN9q+I2raw6dN9s2XK0DPfuzEddeml+djgLmM/LqbOG7D03jYa9k9xxdz1wczFwknDpdm/CObMrkrynCoxGSs1vRkdAQ5SpSll2TTyGncMpSfdsIlsZJodtvvMOLXoB9qjJKcDzdh+a6RITSZrpVprEBLCVjOFplSZ0xwAAisoZlFMALrNRJrJiiy0hO+H2Ys4qxnKlfleqWV1WVqpBpFlTmZhGJqmzpMsgkq4qStl1kskMgU86klpDoUVe3O0blVrNPC6fqDQVHZdT/lNAOjVv8AZgWJglVLqbdk7scFJrQuhh4gqaTjyT+3h4Z0viP9nDOc4U/tMZyCiV4hYJUJB46f9nkTTjyF8P4l09RleoxpK5RIlipRR1awpVJLEb1+DuPzMCz3hSSvhpcaJwSsQdFitUn7mQ9kzEYhLpClbE+zM2WGE1UYoXVVJ0NSdyD8NhSvXTkTQG1/zdoHw+N+Z2A5c943uIJ82H625s/MWEW9ehFrkDlfUgX8evxa2xmy0sBrufLkdd332i4/r6Cw59dz8zb3D3q21BPrWnhUX8xXQYzZQue4HmLkH0t2LavFA251IHYDUfE6Pr1eA8dRTQ0Brr3B+dqDrpTGWkXSL8/ruB7x53D947mzNuS9vQ+7WLa4b6XsPH9DXwxmpFgHsAS/v5+WsUto/wC8bi9hYH42fvFudP3tKEq+ZoKbadT90864zZQZIO5AP113frFyiW7EB35D9XL9vK3OG58b+QqfoRjNlDmNBr3NvUC/vvFAHB8gOVyPo73veLc7oRofh9bE+tDXGagWDbn5tF6jY7OT5EaevD7+l7e8bE7mtPMgD17o9dgK4zUb20a773HwP08GDs+4H+6Bvpqz6aHtFudNa1tRVPIDXGbKAAuNQfer+O3MxQ6l7hwPUj9COdgO2YP2Vk6dclfGXLy3CWoWYZOnLLP7rbkfDT6BinAP4nUyyDSroyMer/8ARu4tMXhnirgaphMqmr8rYtJlE/hRMrafGaOpmJDazE4fSpUX/wC6T0jVb7SFIlNVlavCWVNk4rSLVuUyJtHNlp7JNRNI5cZjLfj05jWSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNFb2oc9GYO312kY1CypEJm6UyNI7wUEKy5k/LcheSNQB9olzyinUKUoGmmNaM7TPbZoxdWwny5X/AN1TyZR96CLRpN4mzhPzzmBYuE1kmR/9xR09Ooa/3pZ5eseEEGhHKtvBW/qT6Y4edvQ9xZvQD1jgC7B97P3BZvQD1icjQc6fIH8K4iP5j1YPazhtOpuWvY84sWLA8j9H3RPbNxzBNPMWp/eoT/WmIVflPaIVgsez9gDp7omtn6VpzI2+vpjHWNNLFn2117W98RLAuNr3/wAQH6W1i4NEd0b1Iv0I/wDer0v1xEdebW9LfBv5xCoEsdPw6dbE+57a26RNaPWoCb73SbeZ1r0PWkKgz937vr6Ee/1sIBH1dxf0b3+s5s0ppZVL7A2+p16+NMdYu/MRCXI7Ai3MF/RtO3r5B7QuSDLJlD51lzQTBTd0Qs5S2juhmbJQSxGKCfhpM2W1BxQCVCKh1uLW45GCmdTTOMezNyi6BZ+E6jiN/wAJLdmDWj9I/wDRAfaoVnTI2JfZszhiE6dmbw3olYx4fVNZUe2mYn4eTalEqswGWZhM/wBpkrE6mUmjllcyWnL+L0FDRyqekwBQPnJp+lyanbcU1sajTc1saigOJyCNBbqGIZtRt01BtcR7YomG3a9+pfr0cMTfXSMmPskOHMHxM7evBBqZQ32uUZEjJ/xPjWSkEJjck5fmEwyrEkqCgkQed3Msxlwe/wC57ie4paVp5l4e0Ka7NuFcYKpdKqdXKSdlU0lcyQeyar2Ci9/wgAh41a+2xnCdlP7NniEqknexrsySMNyfTzAWJp8wYnS0uMygxD+3y8MXkAhmMx1AhJSreUejoeXwsTHxay3CQEM9FxK7VQxCNrfdVcjRltatQDTWhNNqpMmZUTpVPJDzZ8yXJlA7zJqwiWPNSgI/O7OnS6eVNnzS0qRLXOmHlLlpK1nUaJSTqO8aYvEHiDMuJPEPO/ECcOBUyznm3MGZ4tKVlTbC51NYmPRBsFVCmEgGXm4ODaACWoSHaaQEIQAPajLuXqXLeXcDy9RJamwXCcPwuUWZcwUVJKp1TpoDgzp65ap05bkqmzFrUSpRMeOuP47U5ix/GserFPU4zitfic0BRKZZrKmZUJky3ZpUlC0yZKABwSpaEgfh4RZ4eMpS4Btvvbr5jSopagxmTZDvbnbUaG/6nTubxhondunu59zfYkO7WvLEbpfXqK9RSmhNuh0FxjCXJPLdh27l3Yerl2N4zETnAvyZrnXfsb6ciSLxd2Y7kSQAdaX515bEVPOwOMVckFw2vkdfR9b7APyjJRP63+XJrAvfsTFybjhz6VsSa38vXQgg2virp+Y62fp5uzWfbtGQmfo5fc6/CxJJfTzG0S0R4FisAV/l6c7itNfAX1xCqmf93zYv8/jEongvsw13fyfS1vgIr/bU8x/vJxH91P8AdPof1iQT9yq/f5Ew+2pH7w9U4fdTyPof1gZ3JXdz8GMR1xw071aVp938L8tSD6YkFO23oDf0AiNU8bbhww5fz2G9ohuxwNaK8zQV01A8ufPpjITTtYB/XbU9ex6CIlT9htzOzPrfmUtvaLY9Gg1+KvmKHS1vGlR1FgLZCJLNa/Qd/IWe3axMYy5z3vytqA242Op8zZw4tL8YL3rXw6emlhoKA2JFMuXJJ2LM+40bU+rs29mvGKub1Zrtvo1ztb3RZYiMF71FtxYEm5+t+laWOM6VIfa/YhtAPdpv3uIxJk5xbqz207dOTAWHSPevswOJkXkntd5Rk6IkolfEmQ5nyLN2FKPu3veS5eZ5O4hJPcEU3P8ALcsaZeKfeJhomNYbKftS+/0V9prLcnGfCXFqwy+Kry5XYbjlItKfxIKKkYZVpJ1MpVBiNUpaPymZKkTFD+zS3d32cMwzcH8VMLpAvhpsw0WI4NVILsoKpziFKQHCRMFdh9OlKmJEuZNQktMvtIRzDEZDxMHEtpehoth2EiWXBVDzDyFNPtLFbpcQ4ttYBFQqxtjyvr6CjxWgrsLxGnl1mH4nRVWHV9JOHFJq6GukTKWrppqbcUqop5syTMDh0LUHj0xkzptPOk1Ehapc+nmy58mYgsqXOkrTMlTEk2CkLSlSSdCBGEWeQC5PNppKHCVLlcxjZctSqBRMDEuwxJFqFSmq0pqepp+SDM2X52V8z5iyxUKUufl3HsXwOctQZS5mEYhUYetSgAGUpVOSWDOWAA09MMNrE4jQUOIS0gJraOmrEAOQPvclE5IHYLsQ5F35xYHVWAGoHKt1G+96DU8iTuMfPQGfr15fAm9ttIzSwPQe/wCdztre0W9ZFSdgCTUW0oK9TfTrblmygWHPTU6na5s1hyNt3czC/T1N3HRrNfXbSLe8q/yNTuqpPjuDf+IUpjLlg8Tv5t2CW+fcPvDQe/m+wtvd+Z1Yavb3FD4vAkV5moHTc77HGYkP2JCWHJx8LesVFyOQAffqfJyduTxbnCKU0oeegFa/OtdLg6YzkAAW5W2d7fDTfTUxUnRtwT3J19zgbuG5PbnTbW/P+0aGp8KnyPPGZLDOeZDBuQAa3PSCRpbVz5AWI8z8Gi3um41p8Sjf0rz1PpjNQLpH0+vxirflDcydrEh/mNi/lFudpXlUgeBArvsCSL10vvjMRptr/D5P56CKh7O9gSW3d203Z+0W9ymh3rX+8fxOM6WLdmHp/Fj8YoG1bcm+rAA+rkHlq1tcmfstJwpnitxJkPfomZ8P2pwpupuqR5klcElVND3RP1iuo79N8ejP9HNiSpPiNn3BgpkV+SZGJqTupWE47h9MlTb8IxtSXu3Fs99eftGUwXlvL9Y15GNLpgf/AOcoKiaR5miB6tGcLHr5GoMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaAXbmjlzDtn9qp9w1LfaA4rwIIr9yW50nEtbGmqEQqRpqmg0rjVvMyuLMONl3bFK5J/2KiYgD0SI0VzuszM3ZnUdU47iiR/8A2aybLHuQ0eYknTw+mteWop05Y46oXJ6/HRvQv19Y4moO55+VlCze9+vPWJqDXyOvQ1oPWhp8qjEStQRu+mvcdxYnYREfxIPZz5XI/T6MTWySAOlvFNaV6WviM2JbTbsbiIy7DkPn59PV4ntq0PLn4UrT1tzBvXGMoaj4d+uj7P3iE2DHX5g2PoWvsUt0nMm9LA0oATuLjTzO9bU6QHy52ffXXty56M0QqFjqzvzLEXb4bMO95zaqEai4URpY2NeVNac611GI1jfmG68ww66fweIxuLdD57c309+jxObIrTb7vPw9QfzNsY6w47X+voxEoXP+8O41a29ifUxDnsjgczySZyGZpKoOawjkM8UgFxpdlMxDRWCgPwsQ2zEsKUCEvNIWQUimLULKCladUnyIL2Ouo4gbaR2H4Q+KWZ/BLxPyV4q5NnplZhyTjlPi1IiZMmyqfEKbhXTYpg1cuQpE7+rMewior8FxREtaVrw/EKlCSFEEYyswyePytPZnl6aI7sbK4pcO4ruqSl9qiXIaKbSr4vcRcMtqKhyDQsuoJNa4+ykpmJCkkjiDgg3Gx8wzGzR+1/we8VcreNXhnkvxUybUioy9nXA6fF6NJnSp8+gnlS6bE8FrlyD7MYpgWK09bg2KSgB7LEaCplFIKWjNx7AaVpmHa/4hzFxAWmRdnrNEW0sgHuxEbxA4ZyxIBuO8uGi4yhGyFihuFdneE8kKzFWLKQPZYPPWG0Cl1dFLYciQpVg4NzaNR/6SLEFU/gflikSoj+sfE7B5K0/3pVPlnNtWSf8ADNkyXIs5Ta4jaY7SWYV5X7OfHzMTDim4mTcGeJ0fBLSTUTBjJc7MuUFA1TWOMOkrp8Ne/U0rjb3wyoE4p4kZAw6YkKlVmdMryJ4LEfd143RfebHVpAmFt2bd48FfEeuVhnh7nvEJZKZtJk7Ms+SQSCKhGDVn3e4uHn+zDjR3jTVh4ugFFct/Cg+9rUeHnj2kmSX0uw110fpe4t10tHj2ic1j5X0bS/MdfIjSL1DxwtVV9zXw/mpavWhF96Ya5OxG3LvruNRfludYzETdLuH+n/XVrbxeWI3Q963j4/zWqNTzB0pXGGundh077227W69YyUzjYufWzevk2w1vFzajyP3j5n8e9Xnev0OMVdOC7i1/P3NdtBr1jJTPu+3dzppz38nuNYntzDT4r+Nr+YrQX33xjGm7nf56MRvfvdonTP2cjTr8eW7PEtEf/NalrmnpX6b761iMgvoPfoNNND9cokE4WLhvN/UW9A3KKojhuoU6G/zXi0yDsn3q/Q/CL/b21/5vr0aPwx4vRQp439Ar6bYewO6f/F+nyHSBnjmf979NfSKS4/8AmseppXwr54vTIL/lHLS/vF3iwzhzAew1fk30NIiOTDfvf8Qtp1NL03GnPEopyGd7dPSzD62aIlTxu56P6v57HybSLe7Hg/vddaC3P4q+BO+thjJRT3snW2ndtgPntYxAuft9cu55873GkWt+OF6q1qKWvborf0IrvjKRTtqNGb9NLe5g12ZsZc7mX18/JvotdtbNER1RTvAUrShPWlq8tN6W0OMyXJ5BtOvnoPXdhfWMZc2zu3NixN/Kz395YuI7a7M+a3MrdpTs/wA9Q4UIl/GnhiuKKSarlr+dJNCTNoUJJL8tfimfBw1ChUHiXiXhScT8N8/USkgmoyZmYSnGlSjBq2bSqJNv7Oplyl7XSzgsY5R4dYmrDvEPI1alRCZGb8uGaQ7mQvGKOVUpcX/HTzJqCdL3BGu6s8qhIrQiqa6WCviV531FNzapPi4LgHnHsKbEjlGHXjFDJgeKXECHAIT/AJVziJSNgiNjHI5CQOQTEhItcUqSbH8u/wBp7CRg32jvG+iQOFH/ALS811stLcIRKxfE5+Ly0JZvwol16UpAuUpTc3VHof4d1BqsiZRnk/i/qDDpKi5PEump00q1E8+KSSeSjpy6rdVtW/1JFehtS1d9TUW6SQLi1umwG3JjuNW6a8x82G/1/EXAiCtVAdBudNE17t7itxTWtNBQVzUhhroGt118tfc8XNcJ6382floBfzvFudVXTfa2/wDS3iKVtfLlJYP6a6egd9+R2vAuXv68gzORYuQ1t2YveIDyrUpvW42Gx8TWleY0qaZcoOR0D2O55dQCH7FwbRVLlyzuW2e7kt5dQO8W51Wt76b35725HWvnjNQOnXpaw+fmA2kUN3630swsOw1826mLe6dwfTS3wjTzNfDnjNlpYAer9bnTfsOtovA1HkNO6m9WsOTgNFvcNSa1pUDyFyfkeeltcZksany+vQesUNySNdr87Wba59x5vbnSb61p4/eNd+VL8wDuRjMQA4Fuemrbt6fxiuxI0sBoGAs+o3dvKLe6fvHlW3hb5E19NMZyAbdfiT+gHqYoA3MOydtTc/He4eMivsvP/wAwGcL1I4Oz8GmlRnTh+fW9D4DTG/n9Hd/+ejM+oB8L8cIfl+1mSB8ifPeOh/tEf9isM1/7VUQv0wnHD83jPJj2WjTOGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCP5+vbah1QvbK7VrSgQVdorjNEAHUJi+IWYItB8FpiAodKa41ZzICnMGOA6/1viCh1C6qaoX6Ai3UtaNFc5oKc25nBDPj+LqvuFV09Q9XfsR5+bGyKV8/Ctulhep5U1x8FYLjqG+bfBhzjiZvbl+Hu36sGHN9N5jRrbxHgbkHXX+tMQq0fl776HodxEY1IvbTkx+m7C2hia0r8xtY6+FqYiO13O937X7Fu4MRsQSPLqd/ewbvaJ7ZtS1rcyKaV2pTX+Y8jiFYv/LoPXTy7RCoXPViH0trZ+THQ2cRMaVfnvTqNjUitRYakioub4x1BvhyBB/Q63YG7MbRKDHcPbrfTt7hfoIuCToda3vQnum/Qa+FhzGIyNt/Qg/KIjY+6zgcrb6M+t+Yiag2F/ukA16Uppp3q3Na1p4YgI9/Lr35afwixYs9ufRruO2zdOV4mtquP5rgbAjXlqK7E2NKi2ICGJF/r6f9IiUHflz3bnpqDZzuw1BMeau0hkL9rShjPEsh1Lj5G39nnCWRVT8lUsrbiykUUVSp9ai4pFT9iinnXT7qCSUZtHN4VGSo/hU5SDsrcf7QHS6Wu8e0P9EP9qYZKztiX2b84YlJkZa8RKxeNeH1RWzPZIw3xAk0wl1+Ay5ymlJlZywunkGilTloCseweko6Ljr8wKlzsg//AEfSZNs9q7i9AKICo7s6TpxhRVSq4Lidwvq33eam4pxyxp3WlVrWuO4/CYgY9iCTqvB5pB6oraFw7t+8SwFmZuXpt/SRylTfBvJM9LkU3ifQIWG0TUZTzcOJ9glclKG3MwaMQdmftgQz0d2Tu0owwFKdRwP4nRoSknvKRLcoTaZutilytTMK4lCE1KyQmh7wGNw/CKoRTeKnhxOmEBAztlqWSdAajFqWnSSdAy5qSSWAZ3DR4O+LElVR4X+IctAJV+xmY5oA1Ip8KqahQDXJKZRAAuSQBrGmpDTCw+LlvQ/83T9UNfZZE7Y30DG+77i/La/dz5ClA21+vr1bYRe2I8Gnxaa1Pht3qdfHyJm/AvoX3/lZ2ufQD920KUn4fXr6Ns0XVmOpSivRWvhVW3I28K4iVI5aM7j+XxDxMmexu999O2nPf5sIuLUwI/eB89deStefyxjGQb2t2Y28rctWblE6Zw3IPMcn68vlyiciYDc8t6mg5fFpy1HzxCZAuOEvt/MD3fQmTOPPo4uOu2vqTuYkpmI/jGtqk1/5rXxEacDlbZv/AExeJwfXTQBwO+hPw0isJgCB8Z/3qfVdfXD7uOl/rk3pF3tyf3gO5L+d4GYAA0WfWv0USOuH3dOtrfWnDeHtj/efsSfgTFBUwT/HpyJ+fx4qKccgen0mLTOGxt2JY9LDXz0iM5MRoDXWwPpX4vy6YlEgacJ8wPn+sWGbu576dLcn8n3iA7MCa/FQeNetAe94/qpxOmQXDjRtveSw+fS8QKnAXfbQfT+nS0W16N1Pe3533t97XfrXUDE6ZATqG3fd32cX7huvOIFTuWvr1fbt0u+0Wp+PAr8d779P7Wg2rpXlTEjoRyJA/TsT5tzaInUv67/q3o8fdcD0vTrjtwRk0N3lxE34x8LpVDoQT31PzHPUhg2UppUhSnHUAUBNdBUEY4lnqtRS5JzlVTCEy6bKWZaiY+gRIwWumrJdgwSg23FtCI5PkqlXU5yyhTS/xTKnNWXKeWA4PHPxmilJZt3VbW7NpfeafcBUs1sVE+Ve93RvW5ruLlNBUY8TBYDsI9lzcnuYxBcbopMRxYz84gghOZItg3BHvIUNQqxufhcZWDyINDUUP5j/ALWlVLrftM+Ns6UXSjPuK0ZIL/2mGy6fDp42uJ9JMSRa4Ym0eg3hnLVK8P8AKKFAgnBaecAR+7UKmVCCO6JqdNY6gWok02H5Ene/+7S2lRQdAykjVuXrt6b7vqTHOufqRo+jX1PUbgekF1dPGmnSnwjal7kVN6m9yMtKXIFmFn2u4O9/TRj0Nb+avr36P/iEW9Zuan/E668uvLwGMxIYdrt8rfLuTqYp0Yudumo/W/TrEB1etNBpypoDqdTXzrU3NMuUki5N1HfZ+dg1m/TSLrB2/wANzoTq/kGBFrRb1qqfOlep8T/jTwGM2WASPJW2gsl/jbRuetBq/IOH3YgD9Lcm5mLe6oXPLptoNCdddKmtRYgDNQPd8d7HcaOLN5xfpzJA6n8SvoevMxAcIpTQ+e9yRroAaDn4Xy5adAe+nncd2B0taKC1xoLnTU2G578rvuGtzqt/FRFedk25HUg6UFN8ZktLnTkB9dPdA2YPoCDqe47a3HI7piA4aevyAqd/EaUJoNjjLQH13v6sBr5P5wFmfk+pFza/k515sNIyL+y6P/3gM3jnwdzAfXO3D63Sm39Mb/8A9HiG8aMz8/8A2X40PTNeSfm5PUmOhvtEf9isLF/+1FEb9cJxs3Hnt1B0jPNj2SjTSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNDL2k0jVlzt39pyXLT3DEcSo2fhOgKM0S2W5lSul7uNzYOE2BKqnXGsucJRlZmxhJH5qtS/OchE9JZtxMD7kRpH4hyPu+dcySyGKsRXP8qmXLqAR3E0E9+8eKmlbW5eVtem3hWgtji6g47X+uvLrHB1C56hx30LNu1+4D2ia2qh6n6pr+RxCRqNm9x5+vrESrEEae9iHHnt3LDWJqCAa7a+RrXzrW2ImsRvu+zaN5WGr9ALxrDEHR/lv9conNq0Olu71rqm3yvqTzocRLDjtf8AWI1cwNLjtuH5a928omoOnqKHcC9PpenkcYyxv5Hs/uboD1DREob+lvMeln0azWaJzSwoUqDbl+6RU7AWOtdqb6xkHd9WPfvEKhbvy5iwHWzswHXpNaVSx0sDrvodhrY03vYjESxf1I8mcfMctA+1mobcD1DBwednPTQagCYhR0JoTSnMEX8aEnS1AdjXEC0uH5e/6EREXIZ+VnJG4HUG76i5L713WoeLYehYpluIhYpl2HiYd5PfaeZeSpp5l1JstDralJWk17ySqoNsR31BIUCCDuORHbTzEZWF4rieAYrhuOYLX1WFYxg1fRYrhWKUM0yKzDsTw+ol1dBX0k0AmXU0lTKlVEmYx4JktCmPC0ffeyQa/wAy/tJZJkp5akS3iVw94j5ey0+64CIyDbk3+XjEMXFULkVCJyRGQTzawHHYmFDyEKbdaW52z4WVqU5mp0kgKq6SspSl2/tEShVbk8QUmlJTvcA3EfpVzb46UP2tPsCYd4oSlU6c15PzDlil8ScKp5Xsf6ozfQVErLmJTpVMCtMnDMaRmKhzBhSpUydJk4disuimTU1tFW09Pt5Z2y+3nPJGc8nPAOM5tynmTLDzZIAcZn8mjZS42SqwUpEWpJKqggmpIGNqcFxBWEYzhGLIPCvC8Uw/EkKv+FVDVyapJDXcGUCGvyjzCxnD04tg+LYUscSMUwyvw5aToUV1JOpVA90zSL25xomqefgYuJgYpK2omBiH4SJZWlTbrURDOqYfaWhRC0LbdQpKkKSFIUkgjvAg+19PVInypU6WoKlzkImy1JIUlSJiQtKgQWIKVJPECQQQQWaPGGdTrkzZkmYlSJkmYqVMSoEKTMlqKFoUCxSoFJDFiCCC1mubEwrT4q1pubaX1pawqK9K6DNTOt6nmOz97nR/UmApO4226dtG1ux7GLuzMiB962ouRUHlfYdb89sZKZ7b9Du3nzsNrFjq8RlAOmr2829wfQAcupuTUyr+9YEbn5XsfGmtgbYlEwH8wDl/kC7X2253Ooi3gIYg7WLkP21fTU/rE9EeDQFVCBzVXfrU/LkK4ueWbjm1228hcWt5PB1jc32Z3b3fyfkYkJjhaqqjf71deYJGmnlXlgZaC7Kt6A22sfrTWK+1UPgNbHqDy+jFX7cP4z6n/wB7FvsUbMfQfECK+2X09I/DHAarP/EfW5t42w9ijmPcfgkiHtl8x6RSVHUt3hfl3geupH65a4uEtAuVAD1HY2DdPf1GYouz9rm/TbqxtYxGXH0r8e/81QOu/X8dsHljYH08tBfrodWi38Z5uH6dQ4t8eWj3guzH+a3iRpY0ub1NK3F9RbFpnAaABrdbg7sTtbQ3aAQTvvq293v5adyCYtj0xN/iNthXf+9/Q7d6mIVT3cvz6XG3utfoWGl4QPVwH2tvtvztbTU2d+YG/wAXoTXexuLim1d9wMYyp2v8hps9+9xvs8XpST9dB6nRiSLesevvZ3ZbVnrtsdnyVBCnUSnO3+WrgSCot/5ASuZZ0ZeINQEtxcihrnQ0CSFUx034840MJ8Jc7z+PhVVYQcIS9nGNVMjCVpGl1SayZ3a4YFu3PAzCDi3ivkqSUlQpcW/rZVgQDg1PPxVCuQSmZRovZiRuwjc+ccJqAbU51CQb0reqj5062r5KgOWGpsI9W9IwuZ2mqJxm7NU2QrvomeY53HoWDXvJjJlFPpVW4PfS4CCTShG1MflJ8UscRmvxR8R8yyZgmycw58zdjUqY/EJsrFMfr66UsK3CkTkqcaghnBj0ny3RKw7LuA0CklKqHBsMo1I0IXT0UmUoaW4SguPXVx8e4sAEVFNT4W7oFgL+dRT7wxw5KWA17/E+T/xtH2hfl12uz7OW2Ye4mLe4v1v60pyoQB8xS9KjJloA9x67t+tub6Egix1e9y2oHfdxvzYvrEJ1VAb9COmpOoOn5igqTlITxEC3MnpozsRc+/qLVHM20bk+g12De7eLc6rb09LDTa1dj6DGchPL3bXBO9n0DPuIqeTvqOr7nnfTd76C0QHFH50Nb9SfIWqdCfGmXLSw6nTs1g30fcIqkaPsyraudB1/kNNYDqhuRa58NtNLj5DGYhOgAf17t8tyH3gdhZ7k6b3LvsNW3AHcQHVE2JAvTrcgm/oB1TyF8tA3+uXrc+RHlUc21udWAH5dHA2J5XeLc4oUr/FfrTYX5/M13Jxmy0sL9nHMuSfSw1a3aKO501sDfa537bM76teA6q5G33d/Ek11t8zfXGXLS5FtLiwO7BvMnVtAdou5aMTy2GjkdLh76DYxko9lrBOu8cM9zMD/AEEHwrj4Fw7B2Y5uyi+wOlUSt8i96G2PQf8Ao76OYvxZzfXgf2VL4dVlGthb2ldmXLM6Xf8Aw4fObnc7Rr99oqckZSweQWC5mY5E1Ox4ZGGYmhZblxVKPc8Z28ewsadQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpKe2Ty67l/2gPFiKcZLTOaJJw4zJCLUCBEsO5EkUlfeRspKZhJIyHJFfiYWKWONdvECQZeZ65TECdKpJyXGv+TS0EjW3EhY2uI078W6cyM84mtiBUyKCeg2HEDRSJJUD0mSlJ/2dWjGGhXU0018wfO2tr33xwg8+Yf683jrFQs4Fxdtbbj0iag6c/wAqC23K23gRiFQY/W7m+53vv3BiJYcdDvze4ffze4tYgxNQoEa6X8QeYG1tTppbESgxBG7D3+d+QY7lnEWH8SevwI2v6PExtexP5706Hztz2OIzr3uPP4to+8Ra/G/vv7/Vr6zkKre1TWviKWoQK2ptoKnXGOoMSNvr36/KImZ0+nY9NyCbXflyMxpVwa2NbUr4pvufDkACBiEhrcrcn1ZR2a7O78+URENbn31s2nQPZhbW8TkKvXXTTcGh57X3Oh5kYjIcN6d/r6eIiGPd/L3diLCxtExCqgdALjkN+Vq0NgdTawMJGvw+v423MWKD6WOo6d+h8+5YxKQve4071700qOVN9tCSaXhUOEg6jqPj3/VmiMh/kPeU+8ADsG1avJpo/kjiXwh4zyrvt5g4K8RssZ/h1w6HFRUykEpmsI9nDLaQ0FOOs5hy23HwBhkpIiHS1D99pDzro+zl3FDg+M4dXlREunrKebMa/wCBExPtAW2VLK5a+ctaraRuX9i3xzT4Y5xzT4a5nrly/DDx6y5U+HuaUT5qRQYHmGtlT5ORs8zETVIlyTljHapCcQqkzEmRgeIYnWexrJ9DR0x3PpfMYWYwcHMZfFsRsDHwsPHwEdCPNvwsbBxbKYiEjIaIaUpp5iIYcbeh3m1KbeaWhaFFCgRuklSVpSpJCkLSFJUCClSVAFKgRYpUCCCLEFxaO758idSz51NUSplPU006bT1EichUudInyFqlTpM2WsBcubKmJVLmS1gKQtKkqAUCI08PaS8J3+CnbB4oQTUucgMvcQ4//O1lZYQEwkTA55iYqOnggUoSENQ8vzmzmeVtwiUtmEagmm0NiGVDuOep/gJm8Zo8MsuzF1AnV2ByBlzEAS8yXNweXLk0ftiSVKmTsKVQT1TTxCaqaok8ftEp8s/HnKhyt4m5glJkGTQ43POY8PIDS1ysXmTJ9WJLAJTLk4omvp0ywB7JMpKQODgUrxGxMSACDXQnntf7vhUfIk1x3Yie36mz9y/v5ON46ZMsG/qN3521tqB2Di0XVqZbE9aG2m9adOe4qTpjJTPFr9tOfpsT3IZtozK1tz08rjmPVukXJuZDY8tPA9N9zb8MTJndX5v5an378zFnAfre/a3v8onImX83Sh/CqevLamwxKmd101Y2ctr35vr1eLeE+/49dOwfoIkomXUeGv8A3bdbYv8AbfTae/8AWLSkjZvL4bRUEzI/ePz/AARi4Tyd27kj5xRhyHoIGZE6q/XmjAzyN37En5wYch6CKS5l1B/Dy7t/Ei3mcWmfvp5fFz8IuCSRo47Dbv3+miMuZVr8VjsNP+WvyGIzO66XBJ/S53Gv6Q4SdL/XPQ+RMQXJluVeZt8u7rtobHUYiVO6/L3nyHnvF4Qfht387/7PnFsdmOtzvpoB/u/hfrTEKp/XzcHTa57ta4NokEs8r25uGAu7X7dPy2i1PzCoI71NfHW9yOVOVOgxjLn7P5u3vfk2j92iQSwO/r3udXA306sDGer2F/CByZ5s4wdoSZQDhgcvymG4T5SmEQ2DDLnU8el2Z84rgVKTaYymUQGVoVx9HdU1A5ofh+8pMW8lGl/2uc2hGG5ayXTz0+0rKleYsSkoJEwUtIifh+FpmjX2NRUz8QmJQXCp2HoWwMpBO5P2SsqmbiOZM5z5KjKo6ZGXsNnLDy1VVWuTX4mZb/8Af09NJoJalhiJNetBKhMUBn/4qZpOUuH2bJ826GImEk8SzAOlVPdTKYBEuly0/wATiY6LYcCNapOgBJ8rftF5+V4Y+B/iZnORUikxDDcrV1Jg1S7KkY/jfBgWAzpYcFUyTi+JUU5KQbmXf8IJHohkTBBmHOGX8JXL9rIqMSkzauWzhVFRvW1qVaslVLTzkk9bXaMPZPdApyAGuwoVeAGiiRy6j8v0qWEJSkCyQBzLAMB3LdbubtHoqSS5IAJuen8Tqdb2fWILrnXmQT8q/UAeKcZSEOe7cttW3sLXu+ouHbN9HRxb3+VywiEtQ3NgD40H4nnzOtaYykp5Dfyf+A2vYaM7UYmw82Nn92l/edNILi9/IX21AoBzNVG1/nmS0N1Jfb+dm0bbnaL+Tb2GvIORYluWhAG7kRAcVr00G1fl+tNaYykB29f9l99bndm90U17Cw9Q2xYk6nryBEQXFa3tz5getyRseQ2oM1Cd9rN6fIHl2La3aa8wTf8AeO3YdbaX1MW9xViTvrzp+6K6UFL389TjKQk66cje/nqTu3VtQAKC+rEncG7Wd7vyTz184DithvUA77FRJBr0uBztZOMxAuNwNeXT+Xxip0fdRDDp6+ezE6uAYgOq12r+NgOV/Gx6VIzEJsBye/vL66M3O3WKfOwu1tVGxb5MBqGBguq180jXU1JN9fTblplyk2BPfTlYBwex05jYvXY+YGmzsOz6jTmNTGXT2UErC47jZPFIBLUNkeVNOUugPu5mjH2weS/s8MpQoLtpN629QP6OPDQanxWxcoBKKfKWHS5mqkidMx6pnIB5LMiQohv3EuY1g+0jUtKynRg2MzF6hSdiUJoJaCQbgp9pMA/xG7u2ZTHqPGrMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaqX/AEgnh9+zeNPAbik2P9HnDhpPMixSUI7qUxGQczOztmIdUEgLfiYfiEWUqWorLMtQindaQMdLeKFIUYhhtaP+/o5lMWDfipZxmpJPNQqynshnEazeOtB7PFsExMWFVh06iUALcVDUKnJUS35lJrykFyWlgMAlxr/tqJGuhpsPA23Na9a2NjjqkhifUfMc7aXva4vbok3A9C/1p200OxM1pVRT/AUF9gBUeNB8o1Dfy9dO7G7e+ISGcNYctSCbW3Y9RtExtWnqNrGv631uCK4iI1B+vr+RiPRRfd+wIA6chq7dImoVQiulj5GtCeuunXnTEJFjfQ++w2G7WPe2piNQYvzv5/Xxia2r8BS1jWx5fOleSdY1Bx2/TsfgYjUN+VwNbEaef8eUTEKuPpfU/PTSo9K1xjqGrfEXGra6c2I7lmiJQcP/ADbR+4Lc9RozRNZXUAbkilTW41pXmKior5CmIiGLfTbP15hhESg4fkC458j2e/ruCIloV3SKaVoOgNa35crgDYVpixQcH6c/XRzo4ER8wfo2bnpfkdRExtehB6U6frQ6E7aYgIex+vrffa0WKB/Uc+WxuDt35l5SF0pQ22IP3a0oPMnnQaVFARCQ1iHB9/1t02YtES0pWCCAoEMoG4ULuS+zWIL3cFzrsnezs4xwnErs+SLLDzndzHwlTDZFmcKpaT3pHCMKOTI6HQmqmoIyJpMlaaVQiMy/HhCUMfZxjavwyx4YzlqRTzFk1uD8OH1AUXKpCUk0M4b8KqcCR+K5mU00/lKY3o8KM61Oc8tiZitXOrcewud9yxWqqZhm1VdxAro8SqJyiZk+fVyQUVVTPUuoqq2nqqicta5pWrpL2unZji+NvANjillCBiY7iBwJ/aWYPsUHD/aoifcPY9tg50l6GW0l9cXI0wMFmqDU2XO7BSudwbcK/ETRhxjc77OHiCjKWb14DiE5ErBs2+wozNmL4EUmMySsYZOKieAIqvazcPmghLzZ9JNMxCKdSV8D+0h4frzZlBGPYdJXNxnKRn1nspSOOZWYNOSg4nJCUjjVMpRJlYhKIJaVT1coS1rnoUjU4ZmVgQq1AQQQfOybgbHS9iNB6MpnX1vyHR9QfN36WvfznMvcfXT4W1F3eLo1MtB3vz/5fy863nTO6tbct878/PWLChQ69ouCJlTflp4f2a/S2Jkz2a5/hzccx3i0jmNemrd/oRMRMqU+Ijobjz+HEgn6OR6/Hme5iwoG1vf8b+hESEzPkR4/07oBxIKjd3POz+4xQoD2tzP8Gv6xU/af86fT/wCXD7z19/8A6oez6+7+MP2n/On0/wDlw+89ff8A+qHs+vu/jFJUz5keP6SR5YGobduelx1c6GHAL9mBd/kPRyIjrmVa/ETvyA8KJ08xiIzze7XuHJ9NLDf9Wi4JG9/QfDXzeIS5jqa3O538u7z1FOtd8Rqn63brp2Or69t4uCeQ6aefbrbvFvdmX8wFtAfHT4f1ep5QqndX7XOvM9vN9IuCC2w6fyiXluUZgzvmbL+TcqSuLnmaM1zqW5ey9JoFpb8bNJzN4tqAl8FDNIQVqciIp9ttJoEoBK1kISpSfm4jilHhdFWYlX1EuloaCmnVlXUzlBMuRT08tU2dMWolgEoQSdywAuQIzsPw2rxSuo8Nw+RNq6+vqZNHR00pJVMn1NRMTKkykJAJKlrUkDYamzxvZ9k/gFKuzBwA4dcGZdENx8dluTiJzVOGUIbTPc6TlxUzzXNWkhIUmCdm8REw0obeLkTDySFlkJEPvusLeV5OeIWcKnPmcMazNPSqVLrqkooKZSio0mGUwEjD6ck29omnQhdQUhKF1UyfMSlKVhI9ZPDzJ9NkPJ+C5ZkKTNmUNNx19SlISKvFKpRqMQqEgXEpVTMWimSoqWillyJa1LUgqPUva1z024qSZBg3ipTKk5gnaUKIbS4UuQ0ohXDWq1htcZGPtLAS2hyXup76lAteKH9Jp4uSJ83J/gphVUta6WYjO+b0yltKlT1S6mgythk4oU8yeJE3FcWqaaaAiVLn4JUpMyZNH3fdf7PWV1oTimbqmWEiYk4PhRUAVKQFInYlUIcfhTxopqaXMSSpSkVcv8ISfaeHXHK13+VdKAW+5yAuceTCU9Ow5aXNteZjZ7m3mfXkSC4+mcmGtVfM+FTt4AbD6k4yUpYNyuT/AA93xsLNO7e7X1I12A66Q3HPSnOlSB96lrbAmxFQbYyZaNzsXTzAOxLuCz22N30i4AAFzprbW4tY9nvZx1iA4utq3/O5Og150HqDjLQO3lz0AG2t9TtpaKa8uulh7hu9jctoYguKFDtb5E+f3gOQoOYOMyWgjub9reVgdD5sS4Nwt1uyR1Gp2sLgkDrreILiqn633JFE7mmldtNaWykp0G3y+F7+h3sXyFzuTqTffmObA6AiC6vTnXXruRbRI0voK7hWMxAa/wANOp897fMCoG176h9Bdk35+Rvfrb3FWN7ECnQD1N/11y5aW729duWlz1YiKOSdeg9znUPodQBbQG0QXFa62Phe3gbDnY2rcAYykJdg1vgBbfmer2OgvFddG5DoB17j3W3UIDq9dKCo2rWlztTlfx01zUi132ezM/PVvQ8gAGYddLCw01IDNawHWzt0jPh7MLKK5LwDnWZ4hkIfzrnybRUI/oXpNIoKXSOGSRStWZxDZgFakUWAAkhVfZv7AWWVYT4OYpj86UEzs1ZvxGop5o1m4ZhFJRYTISbay8TkYzoSn8dgDxE6YfaCxMVec6TDkKdGEYNTSpif7tVVzp9XMOrfjpplGW1cXOwyQY3mjomGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCMJHt3+ErmdeyVlziXAwwdmHBriTKJhMXyuhYyjneHdynNUttgd5x1zM7+SHCQoBuGh4lxQoO+jrzxJoTUYJKq0h1UFWhSjykVAMhbDcmcac9ACeo6f8acLNZlenxFCXmYTiEqYtTtw01Yk0sxhuTUKo+gSFEgxqBNK0rSlKGh/msbDwBIFfC1OhlDdnLuH5Ncb6M7G2w3jVA6sHu3Qudr7XI18zE5CqHbxrpvWt9RenhfEZ9x5/V4sUNDq23N9fSJiFbjmafiLeda0JvamIVBj2Af9flZwNHeIlBx5C+vY3207WuDExtVQPXlXmKc+XLmRrEob+Xbkeje8tZ7xYfxAhmPXY/Xu7xLbUNP0R8jblXQcq4jOr+u9/rsNWsIi6GxHx58gNtRsbtE5Cxp4UF7i1/HoKE21JFIljf1+m+tLBojUGPIPfoevIEgag3G0SkLuDrahqdQdPmefgDYDHUGdu4YaFr6bED9W1MSh8fgbjfyIdueoia2vvAdQa6Co/i1Gm513oajuxmx+v4RGoee29jo2/kNL6j96U2sjka22+IX6fevbY354jUnf6GnubkHHa0WAag7e7nblz38gYloXoQbE9TS4FDUi9Bfn40JiUl7H65Xvz2+ERqSQ/vHXRwBr1exEereyB2hIjs8cX5VmSMeilZJzAhvLefoBhZIXIol5CmZu3DkFD8blqNKJrDAJTEPQqZlLIeIh0TR5eOV5IzKrK2OyaqaVnD6kClxKWg2NMtX4agIuFTKRf8AbIFlqQJslKkCcoxzvw3zivJmZaeumKmKwqtAocYlIJPFSLWCmqCLpXOoZpFQgMFqlifIQtAqFKO0TL5hAzWAhY+CioaYSyYwcPGQcZDutRUHHS+NZQ/CxMO82pbMTCRUO6h5l9srbeaWhSFLQoE7eSpqJiJc6TMSuXMQibKmy1BSVoWAuXMQtJIUlSSFIUkkEEEFjG+kuZKqJMudKWidIny0TZUxCkrlTZU1AWhaFAlK5cxCgpKgSlSSCCQY1FvaidhaYdl7iJE8VOHUoeVwB4jzd6IgUwSHnmOGubZi69ExWSo5z3akQ0jjXPfRmSIlx0gwHv8AL7qlRUmbipn6JeBni3Lzrg0vAsaqU/tXg1OlE0zFJQrGqCSkIl4lKALzKqWOGXiiEpDzSirSOCoVLk+dfjt4STckYzMx7BaZRyljVQpcoSkqUnBMQnLK14ZNUQRLpZpKpuGLUoj2QVSKPtKZMyfipamWnxD1BvzrTQbm1+e+wYqNXJ7X/ju2jlnjXwoG1v57c9+fcARPbmRtem1QRXUgmlPClhbXniZM8XvuNN7Pq+o1a/TaLeDbvy+HL16gRMRM/wCaleov6AEeeJBP6976DZnd+ul4s9mHFhvt8mfZ9PnFYTLmpJ31A6X+Hn15ed3t3A67t/H1tFPZjRutyRZ+rRVTMzSykEf2k1+YqPD5Yu9sOnoYt9mOZ9R+kfipmd1I8O8N+dBfxpTD2w5j0MBLHXzIH6RTVMuSk+RB3HQH62162mfa9tA7X+LRd7MOLe8kdrP6fKI65nWvxC1rEVGmtRXmLH0Othn9S7dBa+mz6bfIxXgF7DVtHbqzONNx5F4iLmRv8QvzItvUig+nLxxGqf1azXPuB6A7WffaL+D46+XL+Om0W56ZgBRKwlKRVVwABrUkgUApUnQbkVtCqe+76s2rdtLizDUltRFwRvsA5fTfct0t7jGzv7HLsER+R4OD7XPGOSvQWa59KohngtleZoch4vLuXZxDFiN4hTSEdaacYm2ZpW87L8rw61qEJliNmE0fYciJ5LHJXpB9onxal4uuZkHL1UJmH0s9CsyVslQVLrKynWFS8JkzApSV09FOSJtasJBmVsuVJSpKaWcJ+8f2c/CSZhMuV4gZipVS8Qqqdact0M8KTMo6OoRwTcXnSylJTUVshSpNCglpdDNmz1IK6qSZGdrOmcZXknLc0zLN1n7HLmStDCFJDsZFuEohICHCjRcRFvqQ0ip7iQpTyyGm1qOhPit4l5d8Icg5j8Qc0TVDDMBozMl0klSE1eLYlPPscMwagEwpQqtxOsVLppJURLkpVMqp5RT086YjdXLWXq/NWN0GBYakGorZvCqaoEyqWnR+OprJzAkSaaUFTFsCVEJloBWtIOIvM+ZJlmqezXMM3eL8xm8W5GRKu8ShHfISzDtBR/0cLCsIbhodofC3DMNNpACRT8xue86Y/wCJOdMx57zRUmrx3M+KVGKVyypRlyTNZFLQUiVMZVBhlHLpsOw+QAEU1DS09OgBMsN6IYLg9Fl/CaDBcNliVRYdTS6aSGAUvhBMydMb806omqmT58xzxzpsxb/jL/MqXX9Ur0A0HIDWlq3OONpS3zLe/ctp6R9QjTo5bzdyLuW1G1nuLRHHNR5WOuthf7w3OgHzyEIduWvf0/d6G5NrMWuAaw13PLff3DzOn4YLixU3rzpudheptXw31IrlpT5W1O3Xlo7N5MA4oSNrcvdf0Jbq5ABMQ1qpv58yNiaggClyK8tbHJQjQkBnsGdurcy/PRtzaoDb2Zy+wPkWJGz3A6hoLi9aUqfDXY05AbV8NcZaUt589hydrP2HXR4uPIWLMOg7au19joLsYhrXTfrWoGlyqthcmnje1MZSEW5Hc62P6+VgAXd4pbXVrMdSdg3vJu7nsLe4uu9LU10SNrbq3000BpjLQlz2PqT/ABuf4wI0BZybn1YOdOQtpcXcRCcWTWmt7eAFL+dfG/Q5aQLcti3PU/Adh1io7ty6B9Ws3FYab2s4EBxXnqBf1PlTw8KkDLlI3LXYkXFth1Yi7+bmDtcXFrCxbtblyuAxcXEBxWo0pU+NK8jzPKtTQXuMtCXI1/m3p73AuwNwYW5P5ki51BYDfkdQA8bTfZbyO/w67PnCfKsYwuGmMNlCXzOawzqAh6Em+Yy5mKaQbyRb3kDHTV+DWampYrU64/Q19n7Kc3JPgx4c5eqZS5FZIy1RV+ISJiAibT4jjZXjdfTTUi3tKWrxCbTLIdzJdzrHnb4h4ujHM7ZkxGUtMyTMxSfT08xJdM2moeGhp5qT/dnSaZE0WH59BpHfuO4o4ZDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhHQfal4OM9oHs68ZeDiywiLz7kDMEnkcRFd4w0DmhEGuOylMYgI+NUPLczQkpjn20FK3WYdbaVJK+8PmYzQDE8Kr6CwVU001EonRM8J4pCy12ROShRa5AIj4mZMJGOYDi2EuAutop8qQpT8KKkJK6WYprlMuoRKWoAglKSAQ7x/PHeh4iBiYiCjGXIeKg33YWKhnklDrD7DpaeYdQaFLjLqFoWkmqVApobjGra0KSSlQKVJJBB2UHBB10Lg+e8aHzEKQpSFJKVJUUrSdUrS4UDyIIY2FwXZorNq2JGlzpW5of1bU1oAMY7bAEbi733Gtm5a/lDRGbjsw+PflzG7DUxNbVtWlSK7eGtRtcWsKUAxYoOH1IBYfXuiIhrbMeHU99Pdyd3tEtCqHpcX2P5Heu1MQkWv3+ux5bve0RENfo562t6aHXfUgRMQrfw9fyJrqa+PexGbWL3LCz25NbSxtba7NFqg/wCIcrjmO46ddNIltuaX011323trsa10G0ZGxuD7/r3d4jLKF7k6hu/v7D3xLQvxBHy+WljcnyAqBCtOr3d9foX36d2eIhnHNz35f7Xbm5fQykLpoTrXrtpbmTc1Ota1OIFAjt7t231AGgDbNzjKWPPUHrzHQ+49mImoWCPqOW5pXWlq8611qTZ9fXKIynceR62seV9OTNyArpWR+B/dIsBUcwNDcmwoRUYsUl/q7308zcaam0Wu7hXXa4PIeeoNuxiWlY1Hhe51III+VRWvM0OIiNjp8dD+kRlPJux0NvdZtn00u+YL2eXbFhpB+zeAHE+aoh5TERPuOGWZo95ppiWxcY8gDJMzinHG0ogo6KcW7lqIdqWI992SOvKhYmTswPdXhlndFL7LLWLzgmnWvhwirmKCUyVrUGw+ctRAEuYoqVSLU5RMUqnUrgXITK2O8GfElFH7DJ2PT+CnWvhwKunKSlEiZMUP/ddRMUpIEqbMUVUMwuUTlqpVK9mumTKzH53yZlDiZlDMOQc+yCW5pyfmqWvyjMEhmzPvoKYQMQBVLiUlDsPEsupbiIKOhXWYyXxrEPGwL8PGQ7DrexuGYniGC4hSYphdXOocQoZyZ9LVSFcMyVMTuNUqSpJKJktYVLmy1LlzELlrUk7K4pheH43h9XhWK0kmuw6vkqp6ulnp4pU2UvUFiFJWlQC5cxCkzJUxKJspaJiEqGoZ7QD2ZXEfsnTKa8ROHELOOIfZ4fiDENz2HYdmGYeGrcS86GZVn5mGQVGVw/8AooaDzy00zJ4t16Gg5uJTNYqDh4/fzwq8bcKzvJkYTjC5GFZsSkJVTqWJVJjCkJTxz8MVMLCev8S5mGqUqolhKl05nyETFyvPbxZ8D8XyHOqMXweXPxfKK1laalKVTavBkrWrhp8VShJJko/CiXiaUpp5ilIl1Ap58yWibiqbmQt8XMipBN6n+Kh9D1x3sJ3XkA77Wdx05n3R0Lwh3bn3vbXX1fozRKTM6f8ArKUO5vvWnxW11p64vE8WuwHX5FrfXN6cAt7+v6ekSBM/5/mDX/j+mLxOJFz2sD6W+NvlQy+RPZh/D5RzEyt979ep+uK+36e7+MU9mDqfUfxgZnS/eHn/AIj64e36N5em8PZtofIAfqI4GaWJ79P7wH/fP0OKGcRoX62Deo6dor7Pq/u/X4RHVNK/+srrpv4/Fiwzhzfk5e/k7esVCBvf3eUUURb8U+xCwrb0VExLzcPCw0Ohbz8REPrS0wwwy2VuvPPOLS2000kuOLUEISpRAxDMqUy0LWtSUIQlSlrUQhKEpBUpalKICUgByolkgOWiSXLUtaZctClrmKCEIQFKWtaiEpSlIdSlEkBKQ5KjYORGyH7Nf2RkyRG5f4/drvLbkE3CLhZzkPgVO4ZaIxyJ921Ey/MPFKAeUPsjcMpwOQnD2NaEaqMZBzgxDtMvZejNQ/GDx9QuVVZXyJWe0MwLp8TzLTLBlhDqROpMFmpssr4QF4rLUZfs1H7gpSlJqpe4vg59n6YmbSZpz9RmWJZl1OF5YqUELK+FK5NXjcpX5Eod5eEzEhZmJH9YISlK6SZsgTqfSjLspmU9nszgJPI5LARMym02mUUzCS6WS2AZXERcdGxb6m4eFhIVhC3nnnVoQ2hBUogfFjTmbNlyJUyfOmIlSpSFTJs2YoJRLQgFS1rUogJSlIJUSWADmNxKiokUkidU1M6VT01PKXOnz5y0y5UmVLSVzJkyYshKEISCpSlEAAEkxi34occ4vjNFQ0fL2YyXZHYWt/K0vjmFQsdMIRYUhjMs1g3FKehYucQ6vtMBARQh4mVSiIhoaNgoKcOThpXgX9uX7Qczxf8AEP8AY7L9YVZA8Paqpo6NMpajJxvNA46bF8dnMfZzU0bLwjCWSsSqeXX1Mmdw4tMSnczwByqvDMqS8011JNpcSzXJlVlLJqpIkVdHl5bTMLROlqedInYmhScUqJE0ypsqVOoKSqpZFZRTwrqNazSpvTc2rpqdNf66E40fSkbW95/Ww+nIB77Dvq5O/JtG389dgBvFW7qB1FdyK0NK2AsAdx1OuQiXoTpy5EXDsXOp79AxioHbq7Fturs+g6Pe0QXHPytsLHui/qrf0Bykp+vmbNtYb9AIP79B3a553056mzCIi161O1+g5eJ21O56zy0uXaz/AO8f0u+l9ra1A5XO5se7X25mxtsfxQ1r18Li3kBTw131NhjLQkAP6eYuer9e93eLuTB7gjVyeZO2+urcohLUdTQk20B/ui3ma0F6+GUhPuOhf1PfQt0S7uDQX+L6NcufXR9CCWEQXF6nra51FgNK90VvpS9STbGUlJsBc3c6a6k+73WiugfYAW772s52+T2hOLpb12qbeNAOXgANMZaEgAfrcC/x+FwRaKNzvufgBzLkB3I0uxiC4quluRtbcm9OtCBYmoNKjGShLntqDudh6s9+TizxUDV9f3r8hYcuhCjzd7GIDqxsRyTyA/8AmG1NLXtjMSGsNhqB723PLfQvZ4E3ex2GmrMSbaDqTz0YjtDgPw9ieLHGbh1w/YbU6zmDNMuRNSkpqxIIBwzTMcSAv4FLg5FBTGIabUU++dbQ0FAugjtXwbyPO8Q/E3JOTpUtUyXjOP0SMQI4XlYLRr+/43UAKZClU+EUtbOQhRAmzEIlghUx441nLG0ZcytjmNLVwqocPnmmd/x1s8fdqFBIuBNrJ0lClgEpC1LAZLnbCSlKEpSkBKUgJSBoEgUAHQAUGP0VJSEpCUgBKQEpAsAAGAA5AWEecBJJJNyS5PMmP3FYpDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaK/tVeAjXZ+7a/FOUyuEcg8rcRn2OMOU0KQlDSYHPkRHRU9hoRDaEMtQEtztCZqlUuh20hMPL4KFZNSgqOumdcM/q3H6xKE8MmqUK6SGAHBUlRmAMAAlFQmdLQB+VCUjYk6ZeJeBpwLN2Jy5aOGlxApxWmSQAOCtVMVOCWYBEusRUykJAZKEIBI1jHg2si9dzTmRrTlUXpyFQTbHD1JcefSxfrsdD6gPHXxsedg7aH+Btc6m+4ichWlOVddv1pXWxvfEZ9Oe1/rXk+1otIceevvHr5HXSJbaq+I86g1PiSCDStzeoFbRKHp8DoOwI100HQGIhxe12PQ7eRHuAuTrLQuljf8AEfr5ailcREOOX19fziLQ9CbbNbTr0t3OkSkKof1cfO9vl0IEZBIL837W6C40BZmsWILmxQa40PLu/ppExtelDcabVrSo1tv15bVsIdwYsIcP2foeY7+7TRnlpWDcf4G553t5UuLaQKS1tvl9Hy9CYiNj5dRyHUk3O3aJCF0p86ag6AgU89eadwDEUs/mR/EvqP46cURqBHJ9+vMdDZuvWxEtDgVy112N9SNjrSh5AVpawi7Mba9PTbraLCl9D0A30sPhY6XL6xISunXXehF6UNNRal62Fq4sKX0tz3/kbnRvnFhJFue+r77932N7xIS7XpfUHfWtrpIIJqN7g2AMZSR/LytsdR1vpFCkHr2Fx2PmOt7jWMw/Y69oWiTw0q4Xcf5o+uXsIZgMscT4pTkS7BMtobZhZXnl5S1vvwraUqahs0hLz7J9y3PW1w32idQ/dmRvEwU6JOD5kmqMpIEukxdZK1S0gAIk4iSSpSAAyKwcS0/hFSCniqE7IeGvjGKVFPgGcJ61SUBMmgx6Y61SkpCUy6fFlFRWuWACEYgApaTwpq0lHHVIzSsRUBNYFDrLsHM5ZMYULbdZcYjoCYQUU2Clba21vQsZCRLK+8hbanWX2lhQK0LBX3zLmgiXOkzAoEJmSpspYIILKRMlzEEgg2UhaSxsQdDGziVSqiUFIVKnyJ0t0qSpE2TOlTE2KVJKkTJa0lwQVJWkuCQYwtdrf2KnBTjLFR+cuz7NoXgJnyLXGRUZlxEC9H8JJ3GPqcfQUyGCpM8irXEL7jruVxGyKEgwlEFkwvNlx3YnI32h8x4AiVQZnlTMy4bLEuWirM0Sscp5aWSXqV/2WJAIDpTWezqVzLzK8pICdcc+/Zvy1mJc7EMqzZeV8UmFa5lIJSpuBVExXEoNTS2nYYVLLKVRCZTIlgCVh4UCV68nHzsCdsDs2ftCN4jcHcyRmVZc48l7P2R2XM85HTDNLKG5hGTmQIiHsvwUWO6uFObIDL8WoLS07CMxIcYRtNlnxXyTmv2UvC8epUVs1KeHDcQUMOxDjIBMpEip4U1UxFws0cypQGKkrUghR1NzT4SZ7ygZ8zFcv1cygkFROK4eP6ww72aVcKZy6im41UiJgIUkVyKaZfhUhK0qSPGH7SUhRQtSkrSSFINUlJBoQpJUCkg6g7645+KjRrvcbgjYggX90dcmUxYgg8h6aXPqY5ftP+f/AIv/AKmLvbn+6Iey6K9P4Q/af8//ABf/AFMPbn+6PUw9l0V6fwivBOR81i2JfK4WMmUfFOoZhoGBhn42MiHnVhtpmHhYZLr7zri1JQ222ha1rUlCUlSgDFMrJcpC5s2YiVLQCpa5qky5aEpDqKlrYJCQHJJYC5MXyqabOmIlSZcybNWoJRKloUuYtSiAEoQgcSlEkABIJci14yednb2R3bQ49xsrjJ5kdzgZkeMSiJi82cXWYqQTNuC7yFH9mcPwhWdY+YxDKi5L2ZlK5DKIrupMVPoBl1t9XUOafHfIuXJc5FNiIzFiCCUoosEUiolGY1va4kSKCVKSphNMmdUz0X4aaYoFMd0ZT8APEDM02VMqsNOWsOWApddjgVTzeBw/scMD4hNmKSSZQmyaenmWCqmUhQWNlPsa+zC7OPY/MtzVBQL/ABP4yQzLvveKed4aDXESmIiW/cxCch5bbMRK8nMe478OiObcmmaVMRUfDP5ldl8auAb1Mz74x5sz0J1FNnDCMBWoNg2HzJgRPQg8SP6yqyUzq9XEyzKIk0QUmWtNIJssTTuB4feC2UMgGTWyZJxnMCEEKxvEZaCuQpaQlf8AVtGOORh6SkFPtUmdWlK5yFVhkzTJHvDP3EbJfC/Ks1ztxBzLKsq5WkzPvo+bzaJ90wlSiEsQsM38URHzCMdKWICWQDMVHzCJWiHg4V95aW1dN1tdSYdTTayuqJVNTSQ65s1QSL2SlI/MuYs/hRLQFTFqIShKlECO0MSxPD8Hop2IYnVyaKjp08U2fPXwpBJZKEC65k2Ypky5MtK5s1ZCJaFKIEYK+JnaozP23+JH+RWWoOZ5Y7NeSI2GnU6l0UsQs34ix8HFuLkKM1iGedbalsXFw7cbCZTZeeh4aGg4qPmcZETUSlMq8+vtg/aMn5QyHV0OBVCqHFcyKn4TlySGNWohKRiOP1KQSmXKwqlmpVRSlGZKRitThy58upSlaJPwvBrB6z7Q/iXIoZlHUSPCzJs2mxvMkuYr2K8enSpy1YNhNcpBV/ZYpVyPaTMOlqZOGUeITZtQmr+5+y7aU4kWtSlABQeASkaDSlKUrpY08OglSiSSSol1E3JJLlSidSSSSTqbk3D+toSwAACUgAAAcKQALBhYW0AFhYABojOOa0NjyNB53qo3Jpzte2MhEvR7nYat2DNsL6EbB4v0bXoG/FyNhoLPa5a6haIi3Otdxp5c7Dbn9MhKRvzvy2t3Je/nuDFpL232AZg/Tnrf01BEVbm5Ph1roE/ncDeuJ0S31FruD11Km62YfoIqA/zL2HN2AZ3/ACuDz2iG44fACulTQ3vzJOmpqOW2UlA8tGPlq/b6Ac3WA3bS4ubWDWt01Lk6OTDWvc2poNe7X6qOw8hbXJSh9dPR2dx0axv3OwFLk/AbAf8Al5ka6C0QnXNRWnnWnofiUbaaWxkpTpuf4drfRPStrubaknU8v9nlz00d4ji9didq6culTb89MZUtDX58xqR3D8I3fyuYHrqxa+3M7Bg787toIguL1Gwsabi9h42rqdx0ykpuG1JJHd9T8B1DGFurai13L3L+4lha+xMJxeulz8VzvsN7b08dajGXLQw00H168/N2Nh6HSxYNYD3X0YFrkbiIDiya/wCFa/gNDXStDpXGVLQ5BOjB/V/0ZjsTAbbOAN7DVnve7bPZmIjKz7LHhYJvnTPHGCYNqVCZSlyMpZe77ZLbk8zAlMVN4xp7vDuxErksKzBKaKVhbOY1LV3VNoKvRz+j88PhiGZ81+JNZLeny5Qoy5g3FLPArFcZAqMRqZc1wEzaDC5EumMtlBcrHCpXCpEsnXD7Q+Yvu2F4TlmQoCZiU9WI1vCpiKSiJl00pSN0VFVNVN4iQQuhYBlKjOHj1djUmGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBz7dPs2xHFDs55e455dgWojMfAKcRD8/922RGxXDfOLsvls6WgtNrdjFZfzBDZcmyGXyGJfJ3czzBC2j75ET174h4UqswuViEpIVNw2YTMYfiVSzylExmBKjLmplLANkoM5Qa4PTvjLl9WJYDIxiQgKqMEmqVOAH410FWZcucQwJWZE9NPNAP4Zco1EwEfiCtQZKqdNDrpyPPmLjnY0v0WpLHodP0jVYjUem7g6/AO933Dhpja6U8qgD7t7baG9NDqDqaQKSQ5HvL8Q3LE6iz82sHaI+muwP11N7tve0TULof0dd+oP63BsIfqDof5aHf0MWKD3GrevToQdDziWhVdNdTpvQ1BrpfavjXWFSW7ba7DTv7vLSJQcX00u+2xtY2HLpbSShdbf189KcvG29Diwh+/wBW+tOoJBs0se199Axc66uGvqLuIlJXTz228jzoPLcWxEQbg7Al9wOXb4O4La2qDXH8nt/B997gEym3N9Ot79Dcb9RQ737xsIex+u0RkAj1t8x29d+bS0r8RSu9x9LUqbWGmthEpLdR2/if115PEZDa3vY8+/IlyHfmWe8V0r8K130NOfXba1qWAxEU8nb3ja3Q7jc6m5IsKe4PvG9xv5i3IOIlIcN6/wCGml7iwsdBqqgIMR+vrnz91osIG/8AA6+hv77OWIkJVW4qLg2F/wC8DXp/ShwI2P1tEZS389e2np7y4iqlwjfmLXTyun16VsTQA4sKOX8fX01B5i+tH5j4vfr17G3VyfXPZ37ZnFvs8uQ8rlUajNmQREpdi8h5giH3Jey2s0iFZcmKQ7HZYi3kFS0mDTESlUVSKj5LHud7vcwyznnG8sKTJkzBWYbxhS8Nq1KMoAn8f3ScxXSLIJIKOKQpbLmU8wx2HkzxLzHkxSKemmpxDB/aBUzB65ajJSD/AJw0M8BUygmEEn+zC6ZUxpk6knKcHNZwW7eXALi8xBwb+ZG+HmbX1oh3cs57fhpUhyJc7qG0ynMa3UyKZtRLqg1CNmMg5s64O67KIfvsB3vjAfEXLeNpRLVVDC61RCTSYipMkFZsPY1RP3aclRsgGZLnE2VIS6eLZ7LHi1lDMiZcpdanBcRUQhVDiy0UyVLUwT93rSoUdQlajwy0mbKqFKsqmQ6OL2o3EGxSok0+8D3hRQIpYhQBG5NFDU0OOd6x2cDyPpyP6iOjeIfZg7NfFz3q+JvAThDniLfSULmuYOHuV4+ftpqSTC5iXLET+BUa/EuCmTCiD3akKpjkWGZvzVgvCMKzHjdAhJcSabE6tFMT/rUvtTTL7LlKA2jjeKZOynjRUrFstYHiExaSkz6nDKRdUEkuQmr9kKmWCbn2c5LnWPLEx9kd7O6ZvriVdnOXwLjqitxEs4icXpfD946+7g2c/iDh0DRLcMyw0kCyBcnmMrxr8TpSAgZomzAkMDNwzBZi26rVhvGo9VKUescIneBXhVOWqYcpypalElQk4rjstBJ5ITifAkdEJSByi9Zc9lN7PTLEW3GwXZnyvMopsgp/ylzTxEzdCGhqA5KczZymkndGv/pZevvCoVUWxBV+MfiXWIMuZmusloOopKTC6NflOpaGTPHlNHSMii8E/C2hmCdJyjRzJidDV1uLVqPOTV4hOkKH+KUdS9rR7KyHwk4R8K2EwvDDhVw64cQyRQMZDyNlbKDVe73CpSMvy2XpWtSahbiwpxdSVqUVEng+I45jWLq48WxjFcUUf3sRxCrrTq4Y1M6awB0AYCzAMI59huBYHgyeHCMGwrCk3JGG4dR0Lk6lX3WTK4lH95SnKiSSSSY+1nE+lEglkbO8wTSXSSTS1hcXMpvOY6Clkrl8K3T3kTHTGOfYhIOHRUd96IebbSSApQJGPjzZsmnlLnT5sqRJlJKpk2dMRKlS0DVS5iylCEjcqIA5xn1FRIpZMypqp8mmp5KTMnVFRNlyZMpA1XNmzVJly0jdS1ADnGNTj57Urgxw3aiZPwpZc4v5uS0+hEVBLdleQpbEAKQyY2fuNiMnhS4UP/ZstwkRBxMOFtKzBL4hSSnrvG/EvB6AKk4Wk4vVAEcaCqXQylXA46gjinMWVw06ShSQR94lqaOoMzeNGXsJC6fA0nH68JUPaSiqThcldwn2lUoBdSXZXBSIVLWl0/e5S9MEnGztB8Y+0nmqGm3EfMcXPn0P/Zsu5XlrRgMtSRcW73EwkgkLK1MtREQ44lhcfFLjZzHISw1HTOLSwwEdJZgzNW4p7bEcbr0IpqSVNqFcZ9hQUFPKQqZOmhDlEtEuUlSps5ZXNKEvMmKCQ2uuM5hzLnfE6ZNdOnV9XUT5dLhuGUqCmQifUzBKk09DRoJBnT5i0SgtRmVM4mWiZNmcKWyP8F+HMPwsyJLZAUMKncUP2nmWMYqsxM4ikNh5pDyqKXCy5ptqXwlEoQtuHVFBlDsS97zxG8cvEqo8V8/4ljyJs8YDQvhOV6SaPZ+wwalmzDLqVyBZFVik5c3EarjK50sz5VGqcqVRyBL9xPs++ElN4O+G2E5dmSqc5hrmxnNtbKPtPvOO1kqUJtNLnllTaPCZCJOGUfAJciaimmViZKZ9bUKX2it3W++t6V3qa3050Jpvc9SJQBoNPXyG5uS/e7Wju1xqPU6joAC3PkNgxERVOa00/wABbfbXXoTTEyUXAZ+n6nRtBycPzgz9ty4t37WYWdrAGIy3KV15nUGtK/Edq1Fhc1rWmMhMsb3I0DeRZPYEgk6FrRcBboX6uTY8I1sAbm7PaIrjl689uelfDau2pvjIShm57W+n6e/QNXQMQP8ADfvc3fdufcMIil8zcV8rbVuoj1O9MZCUbl25cx15X9Ip7z1e3Q7gM5vdW/IxHHNem2wvfvG9SRc/7u9DkpTpzLfJuX87m7NXQdNzuS1m0tsG8m1iGtdOp9OdzS2u3XmSTkoRz/jtYXY99tTFN/gBdhfRjd9202ZrQ3F61r43tWlTcU0JAB8qb5KU9PL4DYtzPUmzxXa+hO1+yRzvq1nsLO0Ja6VPSw5DUkjnWutT51xlS0WBIB5m9zsBpYenwFb8rnQdR8SBqXANhEFxeo2uCdaVpvzqRQVobXtXGUhJJbnd32+W+wIvd7RQcjcXvqC1w3bkN9NDEUJcecQyy24666tLTTTaS4644tXcbbbQkFSlrUoAJSkqUpXdpW2M6VKXMXLlS0qmTJi0oQhCSpcxaiAlCEJBUpalEJSlIKlEhIckQJShJUtQSlKVKWoqCUpABJUSTYAAkk2sVG942meypwg/zI8C8kZJi4NmEzEuB/b+cfdhsuOZqnoRGTJqJeaUpuJdlTZhZA1EIUpLkHKIUIUpCUk/oF+z54bDwq8Jsq5VqKaXTY0qkOMZl4PZla8wYtw1NdLnzZRUifMw9Bp8IROQpSV02HSOBSkBJPnj4i5m/azN2LYtLmqm0InfcsLfiCU4dRvKp1S0KAVLTUK9pWKQQCJlTM4gFEiPROO6Y4RDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR8/mzKuXs9ZWzHkrNsqhp7lbN0im2WsxyWNCzCTaRzyBfls1l0SG1tuBmMgYl+HcU0426lLhU24hYSoRT5MqpkzaeegTJM+WuTNlq0XLmJKFpLXZSSQWIN7GIKqmkVlNUUlVLTOpqqTNp58pb8MyTOQqXMQpiCy0KKSxBD2IN4/nydq/s85k7LHaA4jcE8xtxKxlWePOZZm0QEEZkyTM/wDrDKWYW3mUIhnVzKSREIuYNw/wS+ctzKUv+7i5fFMt6z43hczCMSqsPmufYzD7JZH+ckL/ABSJoIYHjllPEB+VYWg3SY0czRgNRl3G6/CZ4U9NOV93mqb+3pJrrpagFICSZsgpMwJsicJktQCpZA8+oX4351uN0/kLX3vf4hS1j5b+Y6xx0h+mr6a87bX/ABHcMW0Imtr0Fa60J5bg21sK8tb3rCoNtaztsdiB/dufgW2sLmzX+i/8dGv1iUhfWnI10J50286XruCLSNj9fX1eLFA6i/Mcx+v10MtK6+OpB873OlBpT8cRKS3y/QsNSdC8RkAi1xt5NYsNX0LxJbXsf67XFtfn5iuIyH0sRp/H6+YMbtY3B0P6/ozcuQkpUefK96E8jp/XpUDEZ34rch06a+mmvJxaU7p76+jdtt++0lDg8KctRfUGl/xsDa2LSG10PoYsLHodxty5W87cy8SEroNSbgVpY7abWGltQSRYCIo5M1uh9bv3bbeLCkjRm0bQjz73vvpeJCVeHgb+Y+o6Gtq4iKe4PS3117MdIj4QQe7Ho/MWa/JwA/K9ZLlKUOnqB49Dfw+I3BxGUkfVn7bPbTe2hEWkH153HXt1G2rc5CXRvroaGhF7VFADbTQUOhFsWtZ/TkdN/Pl01iwh7adDdy3O/nvZxzNcLFbGpGux6Cm5/wAU4oRz0Pv+t4t4Trpy3HUvqAdtevOOXe1CiCNPiFut7AnnShO9cW8Iv1+tC4bkCGG0Uvyd9RbTtezaOGD2jubh32huNvChcOOH/E3NuXYSFAS1J0zIzXLhSP3XcsTpuY5eeoPhQp2WKW0Cr3SkE1x9vDMx4/g3D/VmL1lMhH5ZHtPa0jbA0k8TaZTXbilEh7MXMckwXOWaMvFH9T47iFFLR+WmE729CQGYKoaoT6NTbFUhRT+6Q5Mevcu+1F7RUoSy1OJbw5zYlASHXZrl2aS6LdA+8sO5fnsqhGnVCp7wgVtJJsxoBzOl8Wc0yGE+ThdaBZSptNNlLUOYNNUSUBXX2ZT/AKsdi0XjznOmCU1MjBcRAYKVPo58maobkKpKunlpV19iU/6hjt2A9rjmVpsJmfA7L8a7T4ly/iDM5W0pVqkMxWUp0sJqD8JiFWNCo0JP2pfjLWBP9rl2mWprmViUyUkm37q6OeW1txb62vyOV9oiuCQJ+VKSYprqk4xPkJJt+5Mw6pIGtuM94hzf2uGd3m1/sPgxk+Wu90lC5zm2dT9tBAJqpmAk+WVrSLVAfbJofiFbWTvGTEVAinwGjlKP5TPrZ9SBydMuTSE9WUOQiGo+0NiqwRSZYw6Qo/lNTiNVWAHqmTT0JV1AWl9ARrHQObfaedqKftOsyiZ5KyQXAoe+yxlCGiohoEEENLzfE5paSdSFqaUtBHeSpJAI+RU+J+a6lJEqZQ0JUNaWkQtQBbQ1i6sXBsWcPq4eOO13jbnmsSpMidhuFuPzUWHomKAIYkHEF14Sb2dJI1Bdo8PZ/wCKnEjiZGGN4hZ7zbnWIDyoho5ln0xmrEM4sE/6lCRT7kHANoqQ0xAw8PDsNkNMNNtpSkcQrMSxLElceIV1XWrB4gamdNnBJL2loUoolgBwlKEpSkWSkANHXmI43jONTBMxfFK/E5nEVA1tVOnpQp/+6RMWZcoDRKZaUISmyUpAAHWTqjcCxOu+lrGlLctb1roMQJDJL7/AgP8Ap6+WDcHpbcHUgHkdmFttL29edkrhkJ7mCI4iziGSuU5YeMNI232++iLzGtpK1RaQurfdksK8l5s91SxMIqDfZW27BKxpr9sDxSOXsuU/hxg9StGMZrkfeccmSJnAujywicqX92UUlMzixyrkrpVjiCFYdS18icFy6xIO/P2H/BwZkzRUeKeOUyJmC5NqDR5dlTpPtEVua1yZcw1ifaJMtScvUdQiplqIMyXilZh1TTrlzaBRORpTta79dB/gPz51PmgEXHP1N+TWHS2rdo9ZdTz6ve9rcgNQ4tY7gRQU5zNdh89BqdNrHniVMs7uOYdzrubtrtudeYB9b8+mhLkju4Fx6xHU7y1FaHU0r0000FbE0pWgnTLbZhv31Nn1c9b6u0XN/tNrqwLcrufU87xFU5yvSt+XnvcGutzXc4nCeQv8v00bowvaKO5bU3v7rat3D6Al2IiOpwXvU0ra59Nhbe1bUNcTol87nsw31LOXHqC5ZrUuegcOX8tSbs/QOPw3iItw86bVFSQL0AFTQW5m4vUaZCU8tbfp07Pb1Je5gxHIEsTcnmrTvruHawiItwjX0rpy51J3/GtTkol7n158wNttS0ULlrNZmGo67Nozbiw1LQ3HNfMmum9Sq1unXrpkJTp6MPgH15k+Z2EVA7c7G3+zyH970HSIte58QDqb6nwrYbDrplIljfXcjQdB8epvo3FUltB2Hp6FjYdb3LRCcXUa66m+nO1/C9Ba9SAMlCX25e46b7bWO2mtNr35n/8ACN9rgl9zcxBWuu+/TS+vpppTyploTwjS++/l/Kz6bRdp56bcmDchc8xexvHuf2fXAxXF3jfA5knEA5E5K4WmEzXNnXE0hYzMbcQVZSkrhqfel6Yw7s5iIdaFw8RL5HFQUXREahLu332N/CU+IvilSY5idGudlfIRpswYhMUP8mqcalzQrLmFrOkwzaySvE58kpXInUmFVFPUcKamWmZ07405v/ZrKk6gpZwRimYfa4dTgf5yXRKQ2J1SRqkJkTE0iFhQWidVSpkpzKUU7HuPbSNGoYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBj7bnsaq4x8G4TtIZFlLb/EXgZLok5vahk92NzHwiLjsdNFfC2v7TFZBj3X8ywra3IVDcgjs4LLkVFolsGvr3P8AgX3+hGK06HqsPQROAsqbRE8S9i5plEzU3S0pU+5JSk9O+L2U/wCtsKTj9HKCq/B5ahVBIHHPwskrmaj8SqJZVUJcp4ZC6supXAk6g6F+u45jkL0qK/dHOnInpBSXtuI1ZUkguNdL/WurFmN7cpTa77EEfo6W7o8DtUDSBSdjb9Hv3B626RGoOHHz5s17uTryvufxTEL05GtK2qAdx/S2oGqcQkNZrBtP3X0a1x3OzHYizXv8fkANv00lIXSnLprp4/nbS1MWkecWFLOWudrMfUG/wOu8SkLqdq8ga63r51r4eF4lJb9fgPQM/Pm9oyHG/chhYafLvze0hDlKfXTfQgfPTTFhD2P11HyMRl08yPgG56kaXANnJeJKVdetzca3v/Q68gMRkEdrafpuToP9n8TvFCkKuDfnsYrpc686nx2PKnKnLTXFpTy+trHe/Qai14s0sofR5H1O4fZ7xIS513qakkHmLXA2ppTWpAxYUg6i9x2+vdFpSD5bjb9eY1tfnFcOC1d7XNq1tfr89QNcRlBuR9a7fD6MWEEdeu/WzsQWb3aANVCxb9U5XGhtatxyxGU67H6sQdi9xZ/WLWG22p0sBexL/C7u2sVQ51oNwfiH0rXxxYUkX1N7ixc87s3v20izh1a3u52Y+bgA36sYqpdI001qDXTc94EDoKHcilK4oRq+ugDc+RBu3NvKLSDvfV3t5aE+9+fKOYeF+9SvMpKb8goGv9ByxRn0+IPus3m3KKNbQgche3MguOtn5xzDw5Vr/MT8yBQeflvijWOtuYPye/du8WlI3U1uTe6xO+g89o/fe+P+8j8cGHMe/wDSKhIOjFt2P/mb0ik89RBFTUmmqTbU6U5bm+lDi+WAVXO2z/pfXRjvFwQHcsALnX5k9/KLU65SprvXXnehA5HrW9DUC+UlgGGotcEbW7WA925idAHn2u7kWNjfS3LRyYtzihegrWvPw38a/kDUSp5M93GnY7jo3zZolFi5tqQ1n/g3q4i45Zy7NM5ZilGWZO0XZjOo1qEh6pUpDIUSuIi3wgVRDQUOhyMinKgNwzDq1KSlJOPjZozJheT8u4xmfGpwkYXglDOrqtQUhK5gQAiTSyDMISuqrahcqjo5RLzaqfKlJBUsA8syXlHGM95pwLJ+ASPbYvj+ISMPo08C5iJQmErn1lSJYKkUeH0qJ9dXTfyyKSnnzlqCEKUMyOUctSvJOWZPlWTpKYCSwaIRpa0pDsS6VKdio2IDYS2IiOi3X4t8p+H3zywkd2mPFPOuasTz3mrGs24yp6/GqxdUuSha1yqSQlKZNJQSFrPGqmoKSVJpJBUxMuSlSgFKVH6B8g5Jwfw6yfgGTMCQU4bgGHy6SXOmIlyp1ZUFSp9diNSiV+D71iNbNqK+oCTwidPWEMlKYvxdtqa+p8rCnkDeh+KluNpl2YMB+m/Vxpp+vMGsP3g9tgPLVW/N/WKCnOtTfSu/W/PT5a4kCRyf+HPbqet+TUJF9w46AAer69X5MA8da61rsLitvAml9NOulNJkoLh7X7/R7dGL6Lk31LW56bdL3LjW2sR1u089LX1vRJGwBub9AK4nTLZmt8+Rsez79dIrq79yBYP1Pm/IMdWiKtyv1IJHzpXqKG9Kg7HEyUHYWtf618t35xVw53I0DORzYdQ13Z+WkRlL2BqdK+ug+df8cZKEAbd/Tc7dtegF4tJ5+etmvazAiwFzcsSXtEW5rtz3N6aDcmvp5gzpS7W225B9eQF+vLV4u5ci1xZ+5uw2A1ewiI4v8wDvT95VPkNh1FsmXL3OulvgPgXF976Uv0J0A2Df3R8TZvIxEccvc6nzrUX6U5beNhkJS9hft+u/xJcsRqYbl+Z5HuNTsH013AiEtdev46dPufM30FcZaEcOuv0+939dnJgx1NuQ9bturvpqYQcHGzWPgpXLIWIj5lMYuGgYCBg2VxEXGxsW83DwkLCsNJU48/EPuNssNNpUtxxaUISSUg59DRVWIVdNQ0VNOq62tnyaWkpaaUufUVFTUTEyZNPIkywpc2fOmrRKlSkpKlrUlIBJaLJ06VTyps+fNlyJEiWubPnTVhEuVKlpUtcxa1EJQlCEqWpaiAEgqVYCNo7socB4Ts98HZDk9xpo5qmVMxZ6jW3Ev/ac0TGHYTFQrT6CptcDJoZmGk8F7gpYebglR/dMTHRLrvvr9nvwlpvBzw1wjLS5cs4/W/8AvnNdUhYne3x6slShPkInJKkLpcMkS5GG0xlcMmailVVhPtqqetfnx4jZwmZ0zPWYmlShh0j/ACHCJKklHs8PkLWZcxSCyhNqpiplVN43WlU0SSeCUhKfSmO744JDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEUIqFho6GiIKNh2IuDi2HoWLhIpluIhoqGiG1NPw8Qw6lbT7D7S1tPMuoU242pSFpUlRBoQFApUAUkEEEAgghiCDYgixBsRFqkpWlSFpStCklKkqAUlSVBlJUkuCkgkEEEEFjaNGr2ofYjjuxzx8jXctS58cEeKERMMzcMJg208YSRqW+XZ3w9iIhSVJTG5UiYhH7NSp11yMyxFyaLW65G/tNqG19zdl9WCYioyUn7hVlU2kUyiEX/tKYkhgqSSOAOeKSqWX4+IDT3xFygvK2NLNOg/1RiKplRhy2VwSnU86hUdPaUyikS3USunVJUT7QL4cayFX662/ep+8KnXn63sTxBSXHXY/LtHXSk7jzFuRseRvr6ixAkoWPHw31uDWgI29BUGghI2NiPrzB+tjEZD+T+WnctzuWdza6paHOtRzppU6Hp5gGtjuYiltA/MPcsC5HPtqNgx4Yt5A2+F9++xb4i8pK6Uofn15/oiugJxY3mPr663aLVJvyPMjUdRof1HSJKXARty02rptzoKWqRfc2FHL478/g/bezRlN2Otyz+8au5/2mGh1isldKX52r9PrWlaHriMgj6+Pw7uIsKSHbubWvz5GzHq+piQlwGhNa+NxWleh6bEnmcWFPJvSxbT65WDC0Wu7gjn59udm035WeuFcjtt06XvuN9dCMWNo40tv00L/qkE8ja0o5en8YrJcpT62I8frp5a4tZ9Pr5chq7lmiw21Bf60tflvYdmrJXyNOo0qLC1KDc1ArW4xaQDqP16/wAYoUgjnt8yx5cy/e0VQ5yobUtqTzodSdyTYV1xaUDbn9abfTjWLSg6Pbkbhuh1ZtGPnvHP3gFa+RNq+J08Kcji3gPft/FvreLeEjbux2vZjrzu/cbVA4RpXyuBXny61GLCgbgX9fXfyJihAGpvexSQP+X5PrHL3h518AD9AcW8CRt7z5bxRh08lN/4h8zDvj+Ef7h/LDh/1lesUbt/vD9YiPugrCR3RRO1rmta8iBz56WxNLSQkm5fRyHPLrEqE22ux1H69+e2jxDdXUG9a3pSmhFOXT/C2JAn8tmD+4uAzWfptptEnCByYG4u4D9LPzG22sQnV1qN6bnQ2pewv0pTE6UgNprctdnc8ywHN9IlDKFuTC3d9dLdC+h0j332UeGwlEqiOI02h1ImM9ZcgsvNup7q4eSIdAio8N/eC5rFMpbYccSlQgYUPMFUNMSpXnf9rzxQGKYrS+GeEVCV0GBzZWI5lmSVFSZ+NLlFVFhhmD8BRhdNPNRVS0KWn7/VS5U32dThykD1W+wz4N/1LglX4uY9SzJeJ5ikz8MylJnp4TTZflzwmuxZMpQ40TMZrJAp6SbMTLUMNo1z5BmUmLJmK9iKdJ28yQBtoB6HTnfGlIQ2gbv83u1u3nHoODqUjmx1Oh5787u2xiipyouajmfhGv6r6dMSCXe79t/5NobP0aDE9Tu2nrYP1uQ24sKK3ABbSngNxQAUJ8DTcUrQYlTLbSwfffS+453uDYaCAABbQ8gHO2pOl+TM4L7xHW6TvSwAsajwAsLHW1wQbVJlSjkH3f8AU+T3s9w1oqGYDQGzC+rC51326XuBEdTmvn1J0udQN7cieoxMmW4c307D4E9m8ooTZhYWADjXnZ+egvZ3FnjLcsbgC9tv631POu9sZCUsdH8i/pt7z20gPjdr37tYFmtu7WBDR1uHrcWpqbUqTsBU8gdhcjEqEvYWFg5u3IAXJ27b7RUb8w1rsGsDs/ndg40DxFuU8f8AhTW1BzIHoNSBbGUiWA1rnV7knr9dbXBPdtSWdxz6bbqIs/MaRDcc19bm29/QGtDypc1xOlJJtq/Ueb2HXsTcbB593c/7OlrEuNRpewiqXyr56kAine05aUJpS4tTKSgJ6n6+u1gAIq2nTQbDuemgJ05ExDW4Njf9bU+7alBc0p45CUF9L8tuTuNDdxty6HGxve521OhOvPezmMtXs0ezKcwTg9oXOkuSuSSCKiIHhtAxjCltzLMTClQ8xzWlLoDLkJl5XvZfJ3QiISqfqjItpcHG5dYW96NfYe8Cv61xH/2xZmokrwzCJ06lyTTVMpRTXYzKKpNbmAJWEyl0+DkLo8OmcE5KsXVU1MtVNVYNIVM1r8d8/fc6X9isKnlNTWoROx2bLWOKRRLAmSMOdP40rrnTPqUkoP3MSpahMk1y0oziY9UY1NhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjzd2sOzFkHtc8E808Gs/NfZ2Zq0JjlfMjMOmImOS85QLMQmQ5qlrZdYLrkA6+6zHwP2iHbm8niplJ332mI9xxHy8ZwmmxqgnUNSGCxxSpoDqkT0giXOSHDlJJCkkgLQpcskBRMfAzNl2hzRhFThVcGE0cdNUBPFMpKtAV7Gplh0uUFRC0cSRNlKmSlEJWSNBrjhwW4hdnXinm/g9xQlBk+cMmTJyBjUsl5yXTOEWkPSyfyKMfh4VcfIZ7AuMTKURyodhb8FEI+0Q0NFJiIVnXLEcPqcMq51HVo9nPkLKVM5QsaomIUQCqXMSQtC2DpUOIAvGlmMYRXYFiNVheJSvZVdLMMtRHEZc1GsudKUpKTMkzpZTMlLZJUkhwlYUkdYJXXqaXpaut9OlOgFbjT56kv0On19e5wfkqSdRY6B/W/rq3zEV0OHUE7DWnkT+OvI3riBSWsR7vg4aIyAduHXVz6ebaWLjUhhKQ5S2vNPp90ix5jQioHTEZTckWPPY/4hqORN+ZEWENrfl07jyIb0dolIXXS3+B1B8+ZsagYj9x+mZn117RQpBF7/H3dGe+7bGJCXCLE+VBTw/pqeZJAxQpBvvzGsWFN3Z+ofi7636cn0IEV0r0oeetjXal78tuZN8RlLe7TTqTa3PzYaRYQC++mgcNu4a2jt5ARWS4Rap+iqV+Y26898WEdAR6j37/VosII0uNLu3PXnpqLdLiKyXAdT+fkL1ttShtvXFhSNrdNvrrqxI0tFHB1Dd9NOZtzFu+kVAvetLc6EdOtedqb4oxGz9g4LdNBZ+V2Cd4oUDY6+n16xUDhFa7c9vMWPqcWsC2z/Wh15ai+gLXtKVDZ9NOnofTvFUOnWp9aj54o36XcX5OQ3vi09Q3ldvcPcNO8cw9pcedfnenp/TBi7Nccr/CH4eo9D+kcg7/MfJZ+hJxQpG6fURaw5D0EfvvbffV8iB/h5eWKMOQ9BFeAEOw9Db/liGtwKUpROp1qnTS9Dy1+eJQg200bR79mvy9D0ioSQOXQg+gs3a/TpEZ1YFaUqDuo/nSht09MXhNwwYPy6HRhdteY7ERIA6ebjUC769yXsd+mpj73hTkKI4kZ0luX0BaJc2r7fPolCi2qFksM419qKHBVSYmLUtqCg+6lSkxMS24pIZbdcR1z4teINJ4ZZIxTMk0y14gU/cMBo5ifaCtxyqlzfucpct0g01NwTa2tJWkfdKWclBM5cqWvuTwM8Kq3xg8RcGylKTNRhIV/WmZ66XM9kaDL1FMl/f5kubwqKaqqMyXh1BwpWfvtXImLSmnlz5svLbCswsvhIaBgmGoOCgodmEhIZhIbZhoaHbSzDsNIqSltppCW0JoKJSBUmhPjlW1VZiVbV4jX1E2srq+pnVlbVz1cU6pqqmaqdPqJqgAlUybNWpayAzqsBYD3ww/D6HCqCiwvDKWRRYdhtJTUNBRUyGk0tHSSUU9NTSUl+GXJky0S5YLnhSOIliTULxAsTfdPqTU2HjQVvrriAIG+nx+Y9T5Rltu1/wDX/Qc9h6RQU8aGhrtUVUo23JNBTkfOgOLwi/5fMhm/l0v3hbm+tk2Hazkud9L3Y2NJTnWm1jVWlN7CngKbcjKmW7O9z2B9b/A62irnQMA/zawcPudC+m7Cgp3XrW9b9d9elzyxOlDeR8vSxPu896M+rA8zfUnQX13cs7kbkxlO7ih31trap30OgN9gQDiQIvpftfyFmFwNrc4rZzs+5/Ny5MNQ2hbbcR1OnUk2qBU32Fh1NflrQHE6ZT6+nwJNnsQ3wIJhYB9ObO/m+7ka/AkCOtzrTUm9z41uNdPwFp0oA5emnbU2HdmtDkHYNtqdbgMTcc+92vEW515gAb66DkKC9TcUNqHGQmXxbW6v8u7eTgMbG0cWvawHN1N5dLdWiKpwnfyOnIXqb86WvSmoOQlITYeZ36/rc9zFQ+9zcO7atpuxO+r6BtIq3L0HrUjzPT8bUJ0nQh+XXfyHMhr8nDkB3o528zvbVhyHP0c6+k+yp2b592lOJMPl5n7VL8lyQwszz7mJgBBlsnW8oNy+AddadY/bk7LL0JKW3G3g33IqZOsPQsviEL7++z94I4r41Z1kYPKE+kyzhSpFbm3GpQAVQ4apZCKOlmzJcyWcVxQy5lPh6FomBHBUVsyTMp6Kcg8B8RM80mRcCXWr9nNxSrEyRg1AokifUhI4p05KVBRpKTiRNqFAoKuKXJStMyegp2g8vZfk2VJFJ8s5dl0PKZDIJbByiTyyFSpMPAy6AYRDQkM131LcUlpltCSt1bjrigXHXFuKUtXu3g+EYZl/CsOwPBqOTh2E4RRU2HYbQ04Ik0lFSSkyKeRL4ipZEuWhKStalzFl1zFrWpSjoFW1tViNZU19dPXU1lZPm1NTUTCCudPnLMyZMUwABUpRLJASkfhSAkAC8Y+lGLDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYxfaYez2y/22eGjc2yw3L5Hx/4fwEW7w9zM/RiHzFLwH4uI4dZmiO+hv9izeLX7+UTSIS47lidLMbDqTLZhP4OZcTzVlqXj1JxyeGXiVMlRpppsJqbk0s4uPwLVeWs3kzPxAhC5qV9e5/yPIzdh/tKcS5ONUSFGiqFfhE+X+JSqGoU4HspizxSpinNPNJWlkTJ6ZmkTmrK2ZciZmn2TM5SSY5azXleaxkkzDIJvDOQUzlE2l764aNgYyGdAW08w6hSFapWnuutqU2ptaugp8ibTzZkifLVJnSVqlzZSxwrRMSWKVJLXBfQF9RqANRKqlqKKfOpauTMp59PMVJnyZqSmbKmoUykTEG4UlTnlqzhQizpcBpU30rSlqXrzG/ysTXEBGx+vlrGKUnUBuxB30+AYvcPtaulZtXpvatToRodeorUXFcQqQR1F/o+X1dojbn1u1vP3W3ZnLtElLm9TUCtQKGo/iAtSt6i9+hOIyl7eRB25tuD006RaUkG1ntrYvsDbzB5dQIkJdFL0tao0r4W+dN/vUxGUkbE6f4m07ejtaw0i3XXU9hc6F+X0NbSEr3BtzOnz0pXela6EYo3K/Tf0/R4tKQe/MfV/OK6Xda01qK/nbb8upsKQem1rdfjFhSe40/D+nU8rbtFULHPkb9dBXXzOt9MWlH0Pi1teQZrM8WsD8wNetiz7uAwFme8VQs7Go9RbwNvlXrixiP00Pv18n6xaUtdyDqRp0diGPk/WOaXeumlDb0r+uWKFPMa8xeKMoG7abuD30P1y0ioHR0B3qKV8aW/XrbwjmRyvp27xR9iD1s4+fTn7o5hwcyOgIV9b/r1t4COR7hh6DU9T/Kn4NwB7j+o93pHLvjkf15jAJUNCPU/DT1EOFJ0PoX/WOK3KJJChWlBYi5sL1wSFOHdt7+vPbpDgHM+79Ii962iR1p/X6+eJeI8z6/Xu8orw9VHo7vFFazempNa6X5nlQg10OlOtwBtfsGc31YXdw1ri5sIvCQGLpG3UDdj2PUXLxk27PvDsZCyW1GTBhLeZM0Jh5lNCtKkvQkIEKVK5SsqAUlUKw8qIi0JSjuR0VEMKLyIZlw+WP2kvEtXiBniZhmGVKpmWMpKqcMw1KC8mtxErSnFsXCU2WmdPkpo6KYpUwKoaWXUS0yVVk+WfbH7JPg6PC7w5k4ri9GiXnHO6KXGcX4pZ+8YdhnAteCYGpawFoVTU9Quur5aUS+HEq2dTTTPTQ002O9y7zIqNKXN+psfkfGt9eBK0d9RrYa+vdie0bVObiwsAGPPewN3vZvO0Ui5YipO57xrz2FvzxIJYB08wL+pbns+8GO77asB2+G190gtFNTttQNgNNuQ100NOtMSBAvbY9T35D084MG2a/wCV92dyT19zOzg0VObabXtXmQNdK2qa7XFReEktqddLnnroH924Aitxc+4OXI322Hu0FjRU5zpy+I0HkAeZ5img5mVMon5MxvYhzZvTXswachzL/i2bX520cD8sR1O6mp318dhbnrppWuJ0ywNh5WcAHW93Gvp3dtrudLPZ3HqOrkuYjLd1ua+pp62uenia2lSglgB5D6s2+uujgiHDvd+o7sw7sSSe5/MIjLcubjpa3O3O5sRprTXGQiU11emnL9B17GKgejamxb5M3TW4cRHWvcknxNzb0FgdKV0ucTBOwsP5D5iK6aBte/Rn6mz25Bi8RHHKa6bXtYmo6n53xkIQCOXPmX07DdtbB2vFt9n7DdjuT0F99js/ZPB3hDnbjpn6UcPsjS8xc0mK/fR0e8h79k5ek7LjaI+fz6KZbd+xyuBDzaVK7qn4qKdhZdANRMxjYKFf7F8NPDbMvinmzDsoZVozPra1XtKqrmJmCgwfDZa0JqsWxSfLlzDTUFIFoBVwqmT6iZIoqWXOrKqnkTOP5nzNhWUcHqcaxeeJciQOCTIQUfeK2pUlRkUdGhak+1qJvCoi4RLlJmzppRIkzJiNofgVwSydwA4eSrh/k5gqZhv9dnc5fbCJhmXMD7DDUwnkwotwIdifs7TUPCocWzL4FiFgGFKah0qV7t+FPhflvwiydQZQy3KeXJ/yrFMSmICKvG8XmypUusxWsZSgmZP9lLlyZCVql0lLKkUsolEkKOgObs14nnLGqjGcUWApf9lSUqC8mhokKWqTSSbJdMvjUqZMKQudOXMnLAUsgdxY7IjjEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYffae+zDkPbAkERxV4VQ0sy52kctSwNsvOGHl0o4sSeXsL+z5XzPE9xDUNmaGaQ3C5SzZFuJaYbS1l7MTv7CMtmeVuFZsynKxuWayjSiVikpDAlkIrEJFpM5TMJoYCTOVYMJU0+z4VSur/EHw9k5okqxLDRLp8ekS2BJCJOJSpaTw09SWZNQkMmmqlH8IAkTz7HgXT6ZuaMr5lyLmWd5OzlI5rljNOWplFSaf5fncE/LptKJpAulqKgZhBRKEPQ8Qy4khSFpood1aCpspUroydImyJsyRPlLlTpS1omS5gKVoWk3SoKYhQYguG3cjhB1TqaSfRz51LUyJlPUyJi5U+nnJVLmSpiSUrQtCgClQ0YsNxZos6F228Dp/Sx89q944gIN20+n9Ow6sbRjEcV2Lb2v1BG9+Vr6gJiQldaU8aE32pQ1odeZ8QTQRlAOlu1h8IjKSNDyBG29tHG9iD0FhFZLnjzqCQelR1oNuovfEZSRYj57X9N/wBIsKXtp0IHm2+pJ1Poz10uEUIttavd5XBIIN9ietiTiMpfru+hfuBpszadgItIPudidRqWaxHWz7XESEu6VpytSmtNNf8Al5E1xYUkPuL3NjoCeh0O/YbxS29vX+Oupt25RVS4DodDsfnQ/QVN6Yo1+X+K3l/Gw3ihAOoB2f6uP5tFUOEU2ttY0tt5aW6EYoRzDh+4f4Rbw9X6KuP1H1rFQO+o0JF/Cv589cW8I6gcgbd2+tIt4TuLbhJt6Hfkx8tjUDg5mw0B71et7jwH+NpRybvow8rHu38KEdGvYkEfC3dwG67cu+Dv6g/UE/S3XFOA8n6gj4ED4+kU4QzFj2UG9CB8fSP0L5ECvJX5C/rinD/i/wB3+MU4B/dP+5/GOK3NB3t664uQncjoxi9EvU8I5M1/PlFJS7XVXX979XNbYv4RyHoIuUiws1xt39w38ucd89nnh5/ltnFubzFlLmXsqLYmEYlxv3jUdM+8pcqlpC6tqQXWlR0YlSXe/DQghnG0pjUOp16+0f4lHIWSZmGYdPVKzJm1NThmHLlzDLnUGHhCUYviiVIaYiZJkz5dHRrQqUtFZWS6lEx6RaVbX/ZF8G0+JviLLxnF6UTso5FmUmM4qidITNkYniypi14FgqhMHsVyZtRTzMQr5cxM6XMoaGZRzZQFfLmoyVl2orc1uTpv/NY151N/KvlqENYWbYEkegcD0HSPagu92J1/Eoqcnf4vbz1bgXTsR43J8O7oNuR+dbgg68JF+QAPnvvoDDnfk/CG31e79b6bRTLlRuB5AfmPC2pFcXiWQTpY6an5B/XR2sYNr2Aclz2a99xbUi0Ui51vb7uvmTr68rb4lEodSH/e08kjTtrrdMVt3Y6DYbizm2xte1hFFTtNKX0OppW9TX8786YkCALNowuwvpp+unckmjm2g0F9n6B9e+2gZ4oKdtqdaVrUgVv9dNR1rUSJQSzdNrXvp8m3fRnMTe5/xaciyR33Da33igpwHetR5UuLmouaDrsf3jidMrQm3x58ufPe7WAFWf0a/kbBt+bG/QMaC3K3sNegvXrfz9KWEyUgWA/X+UNOvUtqPeNOps50vHU5S9ak1t6moHpz6hN8SJS/bV9rbE+ul/8AFaGnXzs46XJNhzNjpEVbmv52Ap+8b7aXv1xkpls25ttv0GzvyfqNIaks/dtw4s/Unto7GOwuE3CbPfG7O0syFw+lDk0nMwUHop9ffZlkjlTbzLMZPp5GpbdEuk8AX2vtEQUOvvvOQ8BL4eMmUZBQcRz3w98Os1eJ+ZqHKmUcOXX4lVkTJ01XEigwuhRMly6nFcXqghaaPDqQzZftppSubNmTJVLSSamtqKemnfBzJmTCMqYTUYxjNSKelkumWkELqKyoUhapVHRyiUmfUzgg8CHCEJSudOXLkSZs1GzN2aOzVkrs1ZHby5l5CJpmWaJh4rOecoiGbZmWY5m0hQShABcXAyKXKcebkkmQ861BNOvRD7sXM42YR8X7geCXgnljwTysjBcHSmuxquEmfmXMk6QiXW4zWy0nhQkArVS4VRlc1GGYamauXSy1zJs1c+tqayrqND8956xXPWLKrq0mnoacrl4XhiFlUiikKIcqLJTOrJwSg1VUUJVNUlCEJlyJUmTL9HY7njg8MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGL/ANod7Mzhv22ZA5mmSOS/h/2gpHLwxlviAiF7sszLDQwQIfLPEWHhIdyLmkpDSFQ8qnMOlydZaccbehUzKWNxMgj+J5lyrS49LM1HBT4ihDSqhvwTgPyyqoJBUpGyJgeZJJdPGkGWrr3PGQKDNsk1Ekoosako4ZFbw/2dQlLNT1yUgqmS2HDLnJBnU5IKRMlhUlel9xo4KcUuzxxCnHC/jBlCaZMzjJVBbsvmLaVQ0wgHHn2YSdSKZMKcgJ5IpgqGiPsE5lcRFS+KUy+0h4vw77TXRlfh9XhlTMpKyQuTOl3KF7pchMyWsEpmS1MoIWglJIsXCm1SxfB8QwSum4filLMpaqTcpWPwrQSQmbJmB0TpKyDwTZalIUxD8SVJHWCHPltv5amwt5mgFcYJSNm9dLPd+V+TDmbR8oixfrcP7wPV+gd9DXS6TQVrv18bCh1JPS5rcGwjn9dO4iwpBDtbtZ78ySC3e55ERVSvkamun3SB59P8SL4sKBtaLSkjqDsb+hu7Hvy2isHDemvOlD9NgeW4r1jKSNRb1ixhZ3HQ3A8+7b9LGKqXTfTyHdPTSxI1oKVqKEXGLCkFtbc3PxO+nLpFOHy7aDvoQGO9xd3sYqh4ilSLUA7w031AIqB4E600raUHZxbYuOzEg33vyu2lGOrPva3TSxbsOji8Vg7XUUpyoR8q18KjXzxYQ3IvzdPmx9zltYpb6+vke+0cg4k6EV5Go5+JHPf8hDaggerelj5RRu3r9P5RzCzUAH5gjyrfTW1RhbmObF3+Y98UKRuPkf1+ukcu+rn6AH8PpimsU4E8vef1imVoJua0tTumg1romlb3xeEqa3qCL+/07mLwCBYkPe6v1MSIKFiZjGwcvl8O7FR0dEswcJDMtqU9ERMS4llhlpHd+JxxxSUpFdTe1SMesq6bD6KsxDEKiVSUNDTT62rqqiYmXJpqWllLnVE+bMUQlEuTJQuYtRsEpJJDRm4dhtfjGIUGE4ZSzq/EsTraXD8PoqZJnVFXXVs9FNS00iUl1TJs6fNRLlpAJKlDvGVvhrkyF4eZOleXIchyKaR9rm8UnugRk4ikIVHRAKaD3KFIRCwoNVpg4aHStS3AtavIbxWz3U+JWdcVzJOeXQqX9xwOlUCTR4LSrmCilK4i4nT+OZW1YACfvlVUcATLCEp97vBLwuofCDw7wTJ9PwT8RSj+scx1yAnhxDMNbLlHEZ6ClISqmpzLlYfQEuv+r6Kk9quZNC5ivui6L1APnX1FPDHXQQBuX6W+vJrR2yX/ALoYcym3xt6RxL19daWA89/p41xdwi5bk7kmx77ae6D3IcDRgA50e1hb17iKRdr1O+9L/KmtT1scXhJ5bW2Hbbbl0uIo3MEuBqW9Q5Ol9+3Kmp0ixIGovep2sNK2pS52G+L0ylEP9fEdi3rtFRsOmiR5am/QksxFyIoqdvzBpruDra56/Ikm2JRKAZ7+T+8/p+sVZn0Gt9fj1vq2tjrFJThoa0pTwHLT5Ct+dqAShI0AuYr2D33t19NNHc35mKCneZrQa6C/Ifha/XEgQT66b66OWH8L8oo9+dhowDc9e7P7tTHU7t6ab05U0GvI9MTJl899db93uXPaxu5NqOTZntYBwByvbRujH/ljqd1uDTao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-<title>$LOCATION</title>C2</text>
-<text stroke="none" x="-50" y="29" fill="green" font-size="28.999987" text-anchor="end">
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-<text stroke="none" x="-50" y="91" fill="orange" font-size="28.999987" text-anchor="end">
-<title>DIELECTRIC</title>X5R</text>
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-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="50" y="91" fill="orange" font-size="28.999987">
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-<g transform="scale(-1,1)">
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-<title>PACK_TYPE</title>0201</text>
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-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="29" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="91" fill="orange" font-size="28.999987" text-anchor="end">
-<title>DIELECTRIC</title>X7R</text>
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-<title>PACK_TYPE</title>0201</text>
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="-30" y="30" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="29" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="91" fill="orange" font-size="28.999987" text-anchor="end">
-<title>DIELECTRIC</title>X7R</text>
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-<g transform="scale(-1,1)">
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-<title>PACK_TYPE</title>0201</text>
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-<title>PACK_TYPE</title>0201</text>
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="-50" y="29" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="91" fill="orange" font-size="28.999987" text-anchor="end">
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-<g transform="scale(-1,1)">
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="-30" y="30" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="-50" y="-30" fill="green" font-size="28.999987" text-anchor="end">
-<title>$LOCATION</title>C15</text>
-<text stroke="none" x="-50" y="29" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="-50" y="91" fill="orange" font-size="28.999987" text-anchor="end">
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="-30" y="-60" fill="black" font-size="28.999987" text-anchor="end">
-<title>$LOCATION</title>R29</text>
-<text stroke="none" x="-30" y="30" fill="green" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
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-<use href="#symbol:cap.1" fill="green" stroke="green"/>
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-<title>$LOCATION</title>C10</text>
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-<title>PACK_TYPE</title>0201</text>
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-<text stroke="none" x="50" y="91" fill="orange" font-size="28.999987">
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-<g transform="translate(-60,-60)">
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-<text stroke="none" fill="black" font-size="31.999997">
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-<g transform="translate(40,-60)">
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-<text stroke="none" x="-25" y="-55" fill="black" font-size="28.999987" text-anchor="middle">
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-<text stroke="none" x="-30" y="-25" fill="orange" font-size="28.999987" text-anchor="end">
-<title>PACK_TYPE</title>0201</text>
-<text stroke="none" x="-20" y="-25" fill="orange" font-size="28.999987">
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-<g transform="scale(-1,1)">
-<use href="#symbol:res.1:m" fill="green" stroke="green"/>
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-<g transform="scale(-1,1)">
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-<text stroke="none" x="80" y="99" fill="black" font-size="28.999987">
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-<text stroke="none" x="80" y="69" fill="green" font-size="28.999987">
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-<text stroke="none" x="20" y="-75" fill="black" font-size="23.999986">
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-<text stroke="none" x="80" y="-21" fill="green" font-size="28.999987">
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-<text stroke="none" x="80" y="-81" fill="green" font-size="28.999987">
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-<text stroke="none" x="80" y="39" fill="green" font-size="28.999987">
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-<text stroke="none" x="80" y="69" fill="green" font-size="28.999987">
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-<text stroke="none" x="-101" y="-21" fill="black" font-size="23.999986">
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-<text stroke="none" x="20" y="94" fill="black" font-size="23.999986">
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-<text stroke="none" x="20" y="-75" fill="black" font-size="23.999986">
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-<text stroke="none" x="80" y="-21" fill="green" font-size="28.999987">
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-<text stroke="none" x="80" y="-81" fill="green" font-size="28.999987">
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-<text stroke="none" x="80" y="-51" fill="green" font-size="28.999987">
-<title>ID</title>-680MA</text>
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-<use href="#symbol:res.1" fill="green" stroke="green"/>
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-<title>PACK_TYPE</title>0201</text>
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-<h1>chocodile/page3: EXAMPLE USB DEVICE</h1>
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-<text stroke="none" x="260" y="640" fill="black" font-size="31.999997">
-<title>$PN</title>29</text>
-<text stroke="none" x="260" y="690" fill="black" font-size="31.999997">
-<title>$PN</title>30</text>
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-<g transform="rotate(-90)">
-<text stroke="none" fill="black" font-size="31.999997" text-anchor="end">
-<title>$PN</title>G1</text>
-</g></g>
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-<g transform="rotate(-90)">
-<text stroke="none" fill="black" font-size="31.999997" text-anchor="end">
-<title>$PN</title>G2</text>
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-<title>$PN</title>21</text>
-<text stroke="none" x="260" y="190" fill="black" font-size="31.999997">
-<title>$PN</title>20</text>
-<text stroke="none" x="260" y="140" fill="black" font-size="31.999997">
-<title>$PN</title>19</text>
-<text stroke="none" x="260" y="90" fill="black" font-size="31.999997">
-<title>$PN</title>18</text>
-<text stroke="none" x="260" y="40" fill="black" font-size="31.999997">
-<title>$PN</title>17</text>
-<text stroke="none" x="260" y="-10" fill="black" font-size="31.999997">
-<title>$PN</title>16</text>
-<text stroke="none" x="260" y="-60" fill="black" font-size="31.999997">
-<title>$PN</title>15</text>
-<text stroke="none" x="260" y="-110" fill="black" font-size="31.999997">
-<title>$PN</title>14</text>
-<text stroke="none" x="260" y="-160" fill="black" font-size="31.999997">
-<title>$PN</title>13</text>
-<text stroke="none" x="260" y="-210" fill="black" font-size="31.999997">
-<title>$PN</title>12</text>
-<text stroke="none" x="260" y="-260" fill="black" font-size="31.999997">
-<title>$PN</title>11</text>
-<text stroke="none" x="260" y="-310" fill="black" font-size="31.999997">
-<title>$PN</title>10</text>
-<text stroke="none" x="260" y="-360" fill="black" font-size="31.999997">
-<title>$PN</title>9</text>
-<text stroke="none" x="260" y="-410" fill="black" font-size="31.999997">
-<title>$PN</title>8</text>
-<text stroke="none" x="260" y="-460" fill="black" font-size="31.999997">
-<title>$PN</title>7</text>
-<text stroke="none" x="260" y="-510" fill="black" font-size="31.999997">
-<title>$PN</title>6</text>
-<text stroke="none" x="260" y="-560" fill="black" font-size="31.999997">
-<title>$PN</title>5</text>
-<text stroke="none" x="260" y="-610" fill="black" font-size="31.999997">
-<title>$PN</title>4</text>
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-<text stroke="none" x="250" y="-2650" fill="purple" font-size="48.000019">STUFF R35/R36/R49 WHEN IMPLEMENTING WITHOUT THE DEBUG PAGE</text>
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-<text stroke="none" x="5400" y="-1200" fill="purple" font-size="40.000008">0-3.3V&lt;30MS</text>
-<text stroke="none" x="1400" y="-5250" fill="purple" font-size="117.999986">EXAMPLE DEVICE: KEYBOARD/TRACKPAD CONTROLLER (HAMMER)</text>
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-<text stroke="none" x="6200" y="-3300" fill="purple" font-size="30.000006">3. DEASSERT DISAMBIGUATION SIGNAL AND WAIT FOR FALLING EDGE</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<line y2="50" stroke="goldenrod"/>
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-<g transform="translate(8200,-800)">
-<line x2="50" stroke="goldenrod"/>
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-<line x2="-100" stroke="goldenrod"/>
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-<line y2="50" stroke="goldenrod"/>
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-<line y2="50" stroke="goldenrod"/>
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-<g transform="translate(6950,-1100)">
-<line x2="1050" stroke="goldenrod"/>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR0</title>3&nbsp;</text>
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-<title>$XR1</title>2&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="-574" y="-10" fill="black" font-size="30.000006">
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-<title>$XR1</title>3&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
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-<h1>chocodile/page4: DEBUG</h1>
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diff --git a/board/chocodile_vpdmcu/ec.tasklist b/board/chocodile_vpdmcu/ec.tasklist
deleted file mode 100644
index 6753502b92..0000000000
--- a/board/chocodile_vpdmcu/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/chocodile_vpdmcu/gpio.inc b/board/chocodile_vpdmcu/gpio.inc
deleted file mode 100644
index a34c617ef1..0000000000
--- a/board/chocodile_vpdmcu/gpio.inc
+++ /dev/null
@@ -1,80 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Divided Vconn voltage sense */
-GPIO(VCONN_VSENSE,        PIN(A, 0),  GPIO_ANALOG)
-/* CC ADC, PD in comparator, or tx enable out (low) */
-GPIO(CC_VPDMCU,           PIN(A, 1),  GPIO_ANALOG)
-/* CC 0.2V comparator during charge-through, active Rd (low) or Rp3A0 (high) */
-GPIO(CC_RP3A0_RD_L,       PIN(A, 2),  GPIO_ANALOG)
-/* 0.2V resistor divider for various CC comapators */
-GPIO(RDCONNECT_REF,       PIN(A, 3),  GPIO_ANALOG)
-/* Charger CC1 0.2V comparator and ADC, drive a Rp3A0 (high) or Rd (low) */
-GPIO(CC1_RP3A0_RD_L,       PIN(A, 4),  GPIO_ANALOG)
-/* Charger CC2 0.2V comparator and ADC, drive a Rp3A0 (high) or Rd (low) */
-GPIO(CC2_RP3A0_RD_L,       PIN(A, 5),  GPIO_ANALOG)
-/* Divided host VBUS voltage sense */
-GPIO(HOST_VBUS_VSENSE,    PIN(A, 6),  GPIO_ANALOG)
-/* Divided charger VBUS voltage sense */
-GPIO(CHARGER_VBUS_VSENSE, PIN(A, 7),  GPIO_ANALOG)
-/* Charger CC1 ADC, or drive a RpUSB (high) */
-GPIO(CC1_RPUSB_ODH,       PIN(B, 0), GPIO_ANALOG)
-/* Charger CC2 ADC, or drive a RpUSB (high) */
-GPIO(CC2_RPUSB_ODH,       PIN(B, 1), GPIO_ANALOG)
-
-/* PD TX data output */
-GPIO(CC_TX_DATA,          PIN(B, 4), GPIO_INPUT)
-
-/* Enables the VBUS pass-through (high) */
-GPIO(VBUS_PASS_EN,        PIN(B, 2), GPIO_OUT_LOW)
-
-/*
- * Desired billboard state. One of "no billboard/nothing connected" (low),
- * "source connected but not in charge-through" (pull-up), or "sink connected"
- * (high)
- */
-GPIO(PRESENT_BILLBOARD,   PIN(A, 8),  GPIO_OUT_LOW)
-
-/* Enables cReceiver and the path to the PD RX/TX, RpUSB, and Rp1A5 */
-GPIO(VPDMCU_CC_EN,        PIN(A, 11),  GPIO_OUT_LOW)
-
-/* Disables dead battery Rd on host side (low) */
-GPIO(CC_DB_EN_OD,         PIN(A, 12),  GPIO_ODR_HIGH)
-
-/* RpUSB on host side (high) */
-GPIO(CC_RPUSB_ODH,        PIN(A, 13),  GPIO_INPUT)
-
-/*
- * Controls the dead-battery pull-downs on charger side; either dead battery
- * Rd (low) or Hi-Z (high)
- */
-GPIO(CC1_CC2_DB_EN_L,        PIN(A, 15),  GPIO_OUT_LOW)
-
-/* Chooses between Vconn (low) and VBUS (high) */
-GPIO(VCONN_PWR_SEL_ODL,   PIN(B, 6), GPIO_INPUT)
-
-/* Passes CC1 to the host CC (high) */
-GPIO(CC1_SEL,             PIN(F, 0), GPIO_OUT_LOW)
-/* Passes CC2 to the host CC (high) */
-GPIO(CC2_SEL,             PIN(F, 1), GPIO_OUT_LOW)
-/* Debug red LED driver (low). Keep off for power measurements */
-GPIO(DEBUG_LED_R_L,       PIN(B, 5), GPIO_ODR_HIGH)
-/* Debug green LED driver (low). Keep off for power measurements */
-GPIO(DEBUG_LED_G_L,       PIN(B, 7), GPIO_ODR_HIGH)
-
-UNIMPLEMENTED(WP_L)
-UNIMPLEMENTED(ENTERING_RW)
-
-/* SCK(PB3): PD_TX_CLK_IN - Clock input for PD TX */
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0)
-/* TIM16_CH1(PB8): PD_TX_CLK_OUT - Clock generator for PD TX */
-ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0)
-/* USART1 (PA9/PA10): TX/RX for debug and programming */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   0)
diff --git a/board/chocodile_vpdmcu/usb_pd_config.h b/board/chocodile_vpdmcu/usb_pd_config.h
deleted file mode 100644
index a6c1adbc61..0000000000
--- a/board/chocodile_vpdmcu/usb_pd_config.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "chip/stm32/registers.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "vpd_api.h"
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 16
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_TX_CCR_C0 1
-#define TIM_RX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX uses SPI1 on PB3-4 for port C0 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* SPI1_TX no remap needed */
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-
-/* EXTI line 21 is connected to the CMP1 output */
-#define EXTI_COMP1_MASK (1 << 21)
-/* EXTI line 22 is connected to the CMP1 output */
-#define EXTI_COMP2_MASK (1 << 22)
-
-#define EXTI_COMP_MASK(p) (EXTI_COMP1_MASK | EXTI_COMP2_MASK)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* TIM1_CH1 no remap needed */
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/*
-	 * 40 MHz pin speed on SPI PB3&4,
-	 * (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA)
-	 *
-	 * 40 MHz pin speed on TIM17_CH1 (PB7),
-	 * (PD_TX_CLK_OUT)
-	 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000C3C0;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= (1 << 12);
-	STM32_RCC_APB2RSTR &= ~(1 << 12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* USB_CC_TX_DATA: PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4))) /* PB4 disable ADC */
-			|  (2 << (2*4)); /* Set as SPI1_MISO */
-	/* MCU ADC PA1 pin output low */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*1))) /* PA1 disable ADC */
-			|  (1 << (2*1)); /* Set as GPO */
-	gpio_set_level(GPIO_CC_VPDMCU, 0);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* Set CC_TX_DATA to Hi-Z, PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4)));
-	/* set ADC PA1 pin to ADC function (Hi-Z) */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			|  (3 << (2*1))); /* PA1 as ADC */
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	/* Do nothing */
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   Physical layer CC transmit.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-	pd_tx_disable(0, 0);
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	return 0;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/chocodile_vpdmcu/vif_override.xml b/board/chocodile_vpdmcu/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/chocodile_vpdmcu/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/chocodile_vpdmcu/vpd_api.c b/board/chocodile_vpdmcu/vpd_api.c
deleted file mode 100644
index cdd2d9776d..0000000000
--- a/board/chocodile_vpdmcu/vpd_api.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "gpio.h"
-#include "registers.h"
-#include "vpd_api.h"
-#include "driver/tcpm/tcpm.h"
-
-/*
- * Polarity based on 'DFP Perspective' (see table 4-10 USB Type-C Cable and
- * Connector Specification Release 1.3)
- *
- * CC1    CC2    STATE             POSITION
- * ----------------------------------------
- * open   open   NC                N/A
- * Rd     open   UFP attached      1
- * open   Rd     UFP attached      2
- * open   Ra     pwr cable no UFP  N/A
- * Ra     open   pwr cable no UFP  N/A
- * Rd     Ra     pwr cable & UFP   1
- * Ra     Rd     pwr cable & UFP   2
- * Rd     Rd     dbg accessory     N/A
- * Ra     Ra     audio accessory   N/A
- *
- * Note, V(Rd) > V(Ra)
- */
-#ifndef PD_SRC_RD_THRESHOLD
-#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
-#endif
-#ifndef PD_SRC_VNC
-#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
-#endif
-
-#undef CC_RA
-#define CC_RA(cc, sel)  (cc < pd_src_rd_threshold[sel])
-#undef CC_RD
-#define CC_RD(cc, sel) ((cc >= pd_src_rd_threshold[sel]) && (cc < PD_SRC_VNC))
-
-/* (15.8K / (100K + 15.8K)) * 1000 = 136.4 */
-#define VBUS_SCALE_FACTOR 136
-/* (118K / (100K + 118K)) * 1000 = 541.3 */
-#define VCONN_SCALE_FACTOR 541
-
-#define VBUS_DETECT_THRESHOLD 2500 /* mV */
-#define VCONN_DETECT_THRESHOLD 2500 /* mV */
-
-#define SCALE(vmeas, sfactor) (((vmeas) * 1000) / (sfactor))
-
-/*
- * Type C power source charge current limits are identified by their cc
- * voltage (set by selecting the proper Rd resistor). Any voltage below
- * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
- */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
-
-/* Charge-Through pull up/down enabled */
-static int ct_cc_pull;
-/* Charge-Through pull up value */
-static int ct_cc_rp_value;
-
-/* Charge-Through pull up/down enabled */
-static int host_cc_pull;
-/* Charge-Through pull up value */
-static int host_cc_rp_value;
-
-/* Voltage thresholds for Ra attach in normal SRC mode */
-static int pd_src_rd_threshold[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_RD_THRESH_MV,
-	PD_SRC_1_5_RD_THRESH_MV,
-	PD_SRC_3_0_RD_THRESH_MV,
-};
-
-/* Convert CC voltage to CC status */
-static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
-{
-	/* If we have a pull-up, then we are source, check for Rd. */
-	if (cc_pull == TYPEC_CC_RP) {
-		if (CC_RD(cc_volt, ct_cc_rp_value))
-			return TYPEC_CC_RD;
-		else if (CC_RA(cc_volt, ct_cc_rp_value))
-			return TYPEC_CC_VOLT_RA;
-		else
-			return TYPEC_CC_VOLT_OPEN;
-	/* If we have a pull-down, then we are sink, check for Rp. */
-	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
-		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_3_0;
-		else if (cc_volt >= TYPE_C_SRC_1500_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_1_5;
-		else if (cc_volt >= TYPE_C_SRC_DEFAULT_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_DEF;
-		else
-			return TYPEC_CC_VOLT_OPEN;
-	} else {
-		/* If we are open, then always return 0 */
-		return 0;
-	}
-}
-
-void vpd_ct_set_pull(int pull, int rp_value)
-{
-	ct_cc_pull = pull;
-
-	switch (pull) {
-	case TYPEC_CC_RP:
-		ct_cc_rp_value = rp_value;
-		vpd_cc1_cc2_db_en_l(GPO_HIGH);
-		switch (rp_value) {
-		case TYPEC_RP_USB:
-			vpd_config_cc1_rp3a0_rd_l(PIN_ADC, 0);
-			vpd_config_cc2_rp3a0_rd_l(PIN_ADC, 0);
-			vpd_config_cc1_rpusb_odh(PIN_GPO, 1);
-			vpd_config_cc2_rpusb_odh(PIN_GPO, 1);
-			break;
-		case TYPEC_RP_3A0:
-			vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-			vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-			vpd_config_cc1_rp3a0_rd_l(PIN_GPO, 1);
-			vpd_config_cc2_rp3a0_rd_l(PIN_GPO, 1);
-			break;
-		}
-		break;
-	case TYPEC_CC_RD:
-		vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc1_rp3a0_rd_l(PIN_GPO, 0);
-		vpd_config_cc2_rp3a0_rd_l(PIN_GPO, 0);
-		vpd_cc1_cc2_db_en_l(GPO_HIGH);
-		break;
-	case TYPEC_CC_OPEN:
-		vpd_cc1_cc2_db_en_l(GPO_HIGH);
-		vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc1_rp3a0_rd_l(PIN_ADC, 0);
-		vpd_config_cc2_rp3a0_rd_l(PIN_ADC, 0);
-		break;
-	}
-}
-
-void vpd_ct_get_cc(int *cc1, int *cc2)
-{
-	int cc1_v = 0;
-	int cc2_v = 0;
-
-	switch (ct_cc_pull) {
-	case TYPEC_CC_RP:
-		switch (ct_cc_rp_value) {
-		case TYPEC_RP_USB:
-			cc1_v = adc_read_channel(ADC_CC1_RP3A0_RD_L);
-			cc2_v = adc_read_channel(ADC_CC2_RP3A0_RD_L);
-			break;
-		case TYPEC_RP_3A0:
-			cc1_v = adc_read_channel(ADC_CC1_RPUSB_ODH);
-			cc2_v = adc_read_channel(ADC_CC2_RPUSB_ODH);
-			break;
-		}
-		break;
-	case TYPEC_CC_RD:
-		cc1_v = adc_read_channel(ADC_CC1_RPUSB_ODH);
-		cc2_v = adc_read_channel(ADC_CC2_RPUSB_ODH);
-		break;
-	case TYPEC_CC_OPEN:
-		*cc1 = 0;
-		*cc2 = 0;
-		return;
-	}
-
-	*cc1 = vpd_cc_voltage_to_status(cc1_v, ct_cc_pull);
-	*cc2 = vpd_cc_voltage_to_status(cc2_v, ct_cc_pull);
-}
-
-void vpd_host_set_pull(int pull, int rp_value)
-{
-	host_cc_pull = pull;
-
-	switch (pull) {
-	case TYPEC_CC_RP:
-		vpd_cc_db_en_od(GPO_LOW);
-		host_cc_rp_value = rp_value;
-		switch (rp_value) {
-		case TYPEC_RP_USB:
-			vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
-			vpd_cc_rpusb_odh(GPO_HIGH);
-			break;
-		case TYPEC_RP_3A0:
-			vpd_cc_rpusb_odh(GPO_HZ);
-			vpd_config_cc_rp3a0_rd_l(PIN_GPO, 1);
-			break;
-		}
-		break;
-	case TYPEC_CC_RD:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_cc_db_en_od(GPO_LOW);
-		vpd_config_cc_rp3a0_rd_l(PIN_GPO, 0);
-		break;
-	case TYPEC_CC_RA_RD:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
-
-		/*
-		 * RA is connected to VCONN
-		 * RD is connected to CC
-		 */
-		vpd_cc_db_en_od(GPO_HIGH);
-		break;
-	case TYPEC_CC_OPEN:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
-		vpd_cc_db_en_od(GPO_LOW);
-		break;
-	}
-}
-
-void vpd_host_get_cc(int *cc)
-{
-	*cc = vpd_cc_voltage_to_status(
-		adc_read_channel(ADC_CC_VPDMCU), host_cc_pull);
-}
-
-void vpd_rx_enable(int en)
-{
-	tcpm_set_rx_enable(0, en);
-}
-
-/*
- * PA2: Configure as COMP2_INM6 or GPO
- */
-void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	if (cfg == PIN_GPO) {
-		/* Set output value in register */
-		gpio_set_level(GPIO_CC_RP3A0_RD_L, en ? 1 : 0);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*2))) /* PA2 disable ADC */
-				|  (1 << (2*2)); /* Set as GPO */
-	} else {
-		/* Set PA2 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*2))); /* PA2 in ANALOG mode */
-
-		/* Set PA3 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
-
-		/* Disable Window Mode. Select PA3 */
-		STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
-
-		/* No output selection. We will use Interrupt */
-		STM32_COMP_CSR &= ~STM32_COMP_CMP2OUTSEL_NONE;
-
-		/* Not inverting */
-		STM32_COMP_CSR &= ~STM32_COMP_CMP2POL;
-
-		/* Select COMP2_INM6 (PA2) */
-		STM32_COMP_CSR |= STM32_COMP_CMP2INSEL_INM6;
-
-		/* COMP Enable */
-		STM32_COMP_CSR |= STM32_COMP_CMP2EN;
-	}
-}
-
-/*
- * PA4: Configure as ADC, CMP, or GPO
- */
-void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	if (cfg == PIN_GPO) {
-		/* Default high. Enable cc1 Rp3A0 pullup */
-		gpio_set_level(GPIO_CC1_RP3A0_RD_L, en ? 1 : 0);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*4))) /* PA4 disable ADC */
-				|  (1 << (2*4)); /* Set as GPO */
-	}
-
-	if (cfg == PIN_ADC || cfg == PIN_CMP) {
-		/* Disable COMP2 */
-		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
-
-		/* Set PA4 pin to Analog mode */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*4))); /* PA4 in ANALOG mode */
-
-		if (cfg == PIN_CMP) {
-			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
-
-			/* Disable Window Mode. Select PA3*/
-			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
-
-			/* No output selection. We will use Interrupt */
-			STM32_COMP_CSR &= ~STM32_COMP_CMP2OUTSEL_NONE;
-
-			/* Select COMP2_INM4 (PA4) */
-			STM32_COMP_CSR |= STM32_COMP_CMP2INSEL_INM4;
-
-			/* COMP2 Enable */
-			STM32_COMP_CSR |= STM32_COMP_CMP2EN;
-		}
-	}
-}
-
-/*
- * PA5: Configure as ADC, COMP, or GPO
- */
-void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	if (cfg == PIN_GPO) {
-		/* Set output value in register */
-		gpio_set_level(GPIO_CC2_RP3A0_RD_L, en ? 1 : 0);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*5))) /* PA5 disable ADC */
-				|  (1 << (2*5)); /* Set as GPO */
-	}
-
-	if (cfg == PIN_ADC || cfg == PIN_CMP) {
-		/* Disable COMP2 */
-		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
-
-		/* Set PA5 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*5))); /* PA5 in ANALOG mode */
-
-		if (cfg == PIN_CMP) {
-			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
-
-			/* Disable Window Mode. */
-			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
-
-			/* No output selection. We will use Interrupt */
-			STM32_COMP_CSR &= ~STM32_COMP_CMP2OUTSEL_NONE;
-
-			/* Select COMP2_INM5 (PA5) */
-			STM32_COMP_CSR |= STM32_COMP_CMP2INSEL_INM5;
-
-			/* COMP2 Enable */
-			STM32_COMP_CSR |= STM32_COMP_CMP2EN;
-		}
-	}
-}
-
-/*
- * PB0: Configure as ADC or GPO
- */
-void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en)
-{
-	if (cfg == PIN_GPO) {
-		/* Set output value in register */
-		gpio_set_level(GPIO_CC1_RPUSB_ODH, en ? 1 : 0);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*0))) /* PB0 disable ADC */
-				|  (1 << (2*0)); /* Set as GPO */
-	} else {
-		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*0))); /* PB0 in ANALOG mode */
-	}
-}
-
-/*
- * PB1: Configure as ADC or GPO
- */
-void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en)
-{
-	if (cfg == PIN_GPO) {
-		/* Set output value in register */
-		gpio_set_level(GPIO_CC2_RPUSB_ODH, en ? 1 : 0);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*1))) /* PB1 disable ADC */
-				|  (1 << (2*1)); /* Set as GPO */
-	} else {
-		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*1))); /* PB1 in ANALOG mode */
-	}
-}
-
-inline int vpd_read_cc_vpdmcu(void)
-{
-	return adc_read_channel(ADC_CC_VPDMCU);
-}
-
-inline int vpd_read_host_vbus(void)
-{
-	return SCALE(adc_read_channel(ADC_HOST_VBUS_VSENSE), VBUS_SCALE_FACTOR);
-}
-
-inline int vpd_read_ct_vbus(void)
-{
-	return SCALE(adc_read_channel(ADC_CHARGE_VBUS_VSENSE),
-							VBUS_SCALE_FACTOR);
-}
-
-inline int vpd_read_vconn(void)
-{
-	return SCALE(adc_read_channel(ADC_VCONN_VSENSE), VCONN_SCALE_FACTOR);
-}
-
-inline int vpd_is_host_vbus_present(void)
-{
-	return (vpd_read_host_vbus() >= VBUS_DETECT_THRESHOLD);
-}
-
-inline int vpd_is_ct_vbus_present(void)
-{
-	return (vpd_read_ct_vbus() >= VBUS_DETECT_THRESHOLD);
-}
-
-inline int vpd_is_vconn_present(void)
-{
-	return (vpd_read_vconn() >= VCONN_DETECT_THRESHOLD);
-}
-
-inline int vpd_read_rdconnect_ref(void)
-{
-	return adc_read_channel(ADC_RDCONNECT_REF);
-}
-
-void vpd_red_led(int on)
-{
-	gpio_set_level(GPIO_DEBUG_LED_R_L, (on) ? 0 : 1);
-}
-
-void vpd_green_led(int on)
-{
-	gpio_set_level(GPIO_DEBUG_LED_G_L, (on) ? 0 : 1);
-}
-
-void vpd_vbus_pass_en(int en)
-{
-	gpio_set_level(GPIO_VBUS_PASS_EN, (en) ? 1 : 0);
-}
-
-void vpd_present_billboard(enum vpd_billboard bb)
-{
-	switch (bb) {
-	case BB_NONE:
-		gpio_set_level(GPIO_PRESENT_BILLBOARD, 0);
-		gpio_set_flags(GPIO_PRESENT_BILLBOARD, GPIO_OUTPUT);
-		break;
-	case BB_SRC:
-		gpio_set_flags(GPIO_PRESENT_BILLBOARD, GPIO_INPUT);
-		/* Enable Pull-up on PA8 */
-		STM32_GPIO_PUPDR(GPIO_A) |= (1 << (2 * 8));
-		break;
-	case BB_SNK:
-		gpio_set_level(GPIO_PRESENT_BILLBOARD, 1);
-		gpio_set_flags(GPIO_PRESENT_BILLBOARD, GPIO_OUTPUT);
-		break;
-	}
-}
-
-void vpd_mcu_cc_en(int en)
-{
-	gpio_set_level(GPIO_VPDMCU_CC_EN, (en) ? 1 : 0);
-}
-
-void vpd_ct_cc_sel(enum vpd_cc sel)
-{
-	switch (sel) {
-	case CT_OPEN:
-		gpio_set_level(GPIO_CC1_SEL, 0);
-		gpio_set_level(GPIO_CC2_SEL, 0);
-		break;
-	case CT_CC1:
-		gpio_set_level(GPIO_CC2_SEL, 0);
-		gpio_set_level(GPIO_CC1_SEL, 1);
-		break;
-	case CT_CC2:
-		gpio_set_level(GPIO_CC1_SEL, 0);
-		gpio_set_level(GPIO_CC2_SEL, 1);
-		break;
-	}
-}
-
-/* Set as GPO High, GPO Low, or High-Z */
-void vpd_cc_db_en_od(enum vpd_gpo val)
-{
-	if (val == GPO_HZ) {
-		gpio_set_flags(GPIO_CC_DB_EN_OD, GPIO_INPUT);
-	} else {
-		if (val == GPO_HIGH)
-			gpio_set_level(GPIO_CC_DB_EN_OD, 1);
-		else
-			gpio_set_level(GPIO_CC_DB_EN_OD, 0);
-
-		gpio_set_flags(GPIO_CC_DB_EN_OD, GPIO_OUTPUT);
-	}
-}
-
-void vpd_cc_rpusb_odh(enum vpd_gpo val)
-{
-	if (val == GPO_HZ) {
-		gpio_set_flags(GPIO_CC_RPUSB_ODH, GPIO_INPUT);
-	} else {
-		gpio_set_level(GPIO_CC_RPUSB_ODH, (val == GPO_HIGH) ? 1 : 0);
-		gpio_set_flags(GPIO_CC_RPUSB_ODH, GPIO_OUTPUT);
-	}
-}
-
-void vpd_cc1_cc2_db_en_l(enum vpd_gpo val)
-{
-	if (val == GPO_HZ) {
-		gpio_set_flags(GPIO_CC1_CC2_DB_EN_L, GPIO_INPUT);
-	} else {
-		gpio_set_level(GPIO_CC1_CC2_DB_EN_L, (val == GPO_HIGH) ? 1 : 0);
-		gpio_set_flags(GPIO_CC1_CC2_DB_EN_L, GPIO_OUTPUT);
-	}
-}
-
-void vpd_vconn_pwr_sel_odl(enum vpd_pwr en)
-{
-	gpio_set_level(GPIO_VCONN_PWR_SEL_ODL, (en == PWR_VBUS) ? 1 : 0);
-}
diff --git a/board/chocodile_vpdmcu/vpd_api.h b/board/chocodile_vpdmcu/vpd_api.h
deleted file mode 100644
index df50f92006..0000000000
--- a/board/chocodile_vpdmcu/vpd_api.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Vconn Power Device API module */
-
-#ifndef __CROS_EC_VPD_API_H
-#define __CROS_EC_VPD_API_H
-
-#include "adc.h"
-#include "gpio.h"
-#include "usb_pd.h"
-
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
-
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
-
-enum vpd_pwr {
-	PWR_VCONN,
-	PWR_VBUS,
-};
-
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
-
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
-
-/**
- * Set Charge-Through Rp or Rd on CC lines
- *
- * @param pull      Either TYPEC_CC_RP or TYPEC_CC_RD
- * @param rp_value  When pull is RP, set this to
- *                  TYPEC_RP_USB or TYPEC_RP_1A5. Ignored
- *                  for TYPEC_CC_RD
- */
-void vpd_ct_set_pull(int pull, int rp_value);
-
-/**
- * Get the status of the Charge-Through CC lines
- *
- * @param cc1  Either TYPEC_CC_VOLT_OPEN,
- *		      TYPEC_CC_VOLT_RA,
- *                    TYPEC_CC_VOLT_RD,
- *                    any other value is considered RP
- * @param cc2  Either TYPEC_CC_VOLT_OPEN,
- *		      TYPEC_CC_VOLT_RA,
- *		      TYPEC_CC_VOLT_RD,
- *		      any other value is considered RP
- */
-void vpd_ct_get_cc(int *cc1, int *cc2);
-
-/**
- * Set Host Rp or Rd on CC lines
- *
- * @param pull      Either TYPEC_CC_RP or TYPEC_CC_RD
- * @param rp_value  When pull is RP, set this to
- *                  TYPEC_RP_USB or TYPEC_RP_1A5. Ignored
- *                  for TYPEC_CC_RD
- */
-void vpd_host_set_pull(int pull, int rp_value);
-
-/**
- * Get the status of the Host CC line
- *
- * @param cc  Either TYPEC_CC_VOLT_SNK_DEF, TYPEC_CC_VOLT_SNK_1_5,
- *                    TYPEC_CC_VOLT_SNK_3_0, or TYPEC_CC_RD
- */
-void vpd_host_get_cc(int *cc);
-
-/**
- * Set RX Enable flag
- *
- * @param en  1 for enable, 0 for disable
- */
-void vpd_rx_enable(int en);
-
-/**
- * Configure the cc_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc1_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc2_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc1_rpusb_odh pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc2_rpusb_odh pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc_db_en_od pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_db_en_od(enum vpd_gpo val);
-
-/**
- * Configure the cc_rpusb_odh pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_rpusb_odh(enum vpd_gpo val);
-
-/**
- * Configure the cc_rp1a5_odh pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_rp1a5_odh(enum vpd_gpo val);
-
-/**
- * Configure the cc1_cc2_db_en_l pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc1_cc2_db_en_l(enum vpd_gpo val);
-
-/**
- * Get status of host vbus
- *
- * @return 1 if host vbus is present, else 0
- */
-int vpd_is_host_vbus_present(void);
-
-/**
- * Get status of charge-through vbus
- *
- * @return 1 if charge-through vbus is present, else 0
- */
-int vpd_is_ct_vbus_present(void);
-
-/**
- * Get status of vconn
- *
- * @return 1 if vconn is present, else 0
- */
-int vpd_is_vconn_present(void);
-
-/**
- * Read Host VBUS voltage. Range from 22000mV to 3000mV
- *
- * @return vbus voltage
- */
-int vpd_read_host_vbus(void);
-
-/**
- * Read Host CC voltage.
- *
- * @return cc voltage
- */
-int vpd_read_cc_host(void);
-
-/**
- * Read voltage on cc_vpdmcu pin
- *
- * @return cc_vpdmcu voltage
- */
-int vpd_read_cc_vpdmcu(void);
-
-/**
- * Read charge-through VBUS voltage. Range from 22000mV to 3000mV
- *
- * @return charge-through vbus voltage
- */
-int vpd_read_ct_vbus(void);
-
-/**
- * Read VCONN Voltage. Range from 5500mV to 3000mV
- *
- * @return vconn voltage
- */
-int vpd_read_vconn(void);
-
-/**
- * Turn ON/OFF Red LED. Should be off when performing power
- * measurements.
- *
- * @param on 0 turns LED off, any other value turns it ON
- */
-void vpd_red_led(int on);
-
-/**
- * Turn ON/OFF Green LED. Should be off when performing power
- * measurements.
- *
- * @param on 0 turns LED off, any other value turns it ON
- */
-void vpd_green_led(int on);
-
-/**
- * Connects/Disconnects the Host VBUS to the Charge-Through VBUS.
- *
- * @param en 0 disconnectes the VBUS, any other value connects VBUS.
- */
-void vpd_vbus_pass_en(int en);
-
-/**
- * Preset Billboard device
- *
- * @param bb  BB_NONE no billboard presented,
- *            BB_SRC source connected but not in charge-through
- *            BB_SNK sink connected
- */
-void vpd_present_billboard(enum vpd_billboard bb);
-
-/**
- * Enables the MCU to host cc communication
- *
- * @param en 1 enabled, 0 disabled
- */
-void vpd_mcu_cc_en(int en);
-
-/**
- * Selects which supply to power the VPD from
- *
- * @param en PWR_VCONN or PWR_VBUS
- */
-void vpd_vconn_pwr_sel_odl(enum vpd_pwr en);
-
-/**
- * Controls if the Charge-Through's CC1, CC2, or neither is
- * connected to Host CC
- *
- * @param sel CT_OPEN neither, CT_CC1 cc1, CT_CC2 cc2
- */
-void vpd_ct_cc_sel(enum vpd_cc sel);
-
-#endif /* __CROS_EC_VPD_API_H */
diff --git a/board/chronicler/battery.c b/board/chronicler/battery.c
deleted file mode 100644
index 82347953ba..0000000000
--- a/board/chronicler/battery.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Chronicler battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Fujitsu CP813907-01 Battery Information */
-	[BATTERY_FUJITSU_CP813907] = {
-		.fuel_gauge = {
-			.manuf_name = "Fujitsu",
-			.device_name = "CP813907-01",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 128,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 55,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* NVT CP813907-01 Battery Information */
-	/*
-	 *  NVT CP813907-01 Battery only use to support early
-	 *  stage battery, all battery for PVT will update
-	 *  manufacturer name to Fujitsu. See b/190685811.
-	 */
-	[BATTERY_NVT_CP813907] = {
-		.fuel_gauge = {
-			.manuf_name = "NVT",
-			.device_name = "CP813907-01",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 128,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 55,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_FUJITSU_CP813907;
diff --git a/board/chronicler/board.c b/board/chronicler/board.c
deleted file mode 100644
index c86ad462e1..0000000000
--- a/board/chronicler/board.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Chronicler board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_8042.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min   = 3000,
-	.rpm_start = 5000,
-	.rpm_max   = 5100,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (80 C)
- */
-const static struct ec_thermal_config thermal_config_without_fan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-};
-
-const static struct ec_thermal_config thermal_config_with_fan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	/* For real temperature fan_table (0 ~ 99C) */
-	.temp_fan_off = C_TO_K(0),
-	.temp_fan_max = C_TO_K(99),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_config_with_fan,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_config_without_fan,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_config_without_fan,
-	[TEMP_SENSOR_4_FAN]			= thermal_config_without_fan,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-/* Fan control table */
-static const struct fan_step fan_table0[] = {
-	{.on = 30, .off =  0, .rpm = 3150 },		/* Fan level 0 */
-	{.on = 47, .off = 43, .rpm = 3500 },		/* Fan level 1 */
-	{.on = 50, .off = 47, .rpm = 3750 },		/* Fan level 2 */
-	{.on = 53, .off = 50, .rpm = 4200 },		/* Fan level 3 */
-	{.on = 56, .off = 53, .rpm = 4500 },		/* Fan level 4 */
-	{.on = 59, .off = 56, .rpm = 5000 },		/* Fan level 5 */
-};
-
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-
-static const struct fan_step *fan_table = fan_table0;
-
-#define FAN_AVERAGE_TIME_SEC 5
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_level = NUM_FAN_LEVELS;
-	static int cnt, avg_pct, previous_pct;
-	int i;
-
-	/* Average several times to smooth fan rotating speed. */
-	avg_pct += pct;
-
-	if (++cnt != FAN_AVERAGE_TIME_SEC)
-		return fan_table[previous_level].rpm;
-
-	avg_pct = (int) avg_pct / FAN_AVERAGE_TIME_SEC;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (avg_pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (avg_pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (avg_pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (avg_pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	if (current_level != previous_level)
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	previous_pct = avg_pct;
-	previous_level = current_level;
-
-	cnt = 0;
-	avg_pct = 0;
-
-	return fan_table[current_level].rpm;
-}
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* keyboard config */
-static const struct ec_response_keybd_config main_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		/*
-		 *  Chronicler keyboard swaps T2 and T3 in the keyboard
-		 *  matrix,So swap the actions key lookup to match.
-		 *  The physical keyboard still orders the top row as
-		 *  Back, Refresh, Fullscreen, etc.
-		 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_REFRESH,		/* T2 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &main_kb;
-}
-
-/******************************************************************************/
-/* keyboard factory test */
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/chronicler/board.h b/board/chronicler/board.h
deleted file mode 100644
index 243669035a..0000000000
--- a/board/chronicler/board.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Chronicler board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Optional features */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* Sensors */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_GMR_TABLET_MODE
-#undef CONFIG_ACCEL_FIFO
-#undef CONFIG_ACCEL_FIFO_SIZE
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-#define CONFIG_USB_PD_FRS_PPC
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_TUSB422
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-#undef CONFIG_VOLUME_BUTTONS
-
-/* Fan features */
-#define CONFIG_FAN_RPM_CUSTOM
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/* Keyboard feature */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_DEBUG_ASSERT_BRIEF
-
-/* Disable volume button command in EC console */
-#undef  CONFIG_CMD_BUTTON
-
-/* Disable volume button in ectool */
-#undef CONFIG_HOSTCMD_BUTTON
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#include "usbc_config.h"
-
-enum battery_type {
-	BATTERY_FUJITSU_CP813907,
-	BATTERY_NVT_CP813907,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/chronicler/build.mk b/board/chronicler/build.mk
deleted file mode 100644
index c0daa31eaa..0000000000
--- a/board/chronicler/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=cbi.o
-board-y+=led.o
-board-y+=keyboard.o
-board-y+=usbc_config.o
diff --git a/board/chronicler/cbi.c b/board/chronicler/cbi.c
deleted file mode 100644
index 210207eeac..0000000000
--- a/board/chronicler/cbi.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Features common to ECOS and Zephyr */
-#include "common.h"
-#include "cbi.h"
-#include "cbi_ec_fw_config.h"
-#include "keyboard_raw.h"
-#include "usbc_config.h"
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Chronicler if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-__override void board_cbi_init(void)
-{
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
diff --git a/board/chronicler/ec.tasklist b/board/chronicler/ec.tasklist
deleted file mode 100644
index c7a977f0ff..0000000000
--- a/board/chronicler/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/chronicler/gpio.inc b/board/chronicler/gpio.inc
deleted file mode 100644
index dc00e3eddf..0000000000
--- a/board/chronicler/gpio.inc
+++ /dev/null
@@ -1,179 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN, 		PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* LED */
-GPIO(C0_CHARGE_LED_AMBER_L,	PIN(C, 3), GPIO_OUT_HIGH)	/* Amber C0 port */
-GPIO(C0_CHARGE_LED_WHITE_L,	PIN(C, 4), GPIO_OUT_HIGH)	/* White C0 port */
-GPIO(C1_CHARGE_LED_AMBER_L,	PIN(6, 0), GPIO_OUT_HIGH)	/* Amber C1 port */
-GPIO(C1_CHARGE_LED_WHITE_L,	PIN(C, 2), GPIO_OUT_HIGH)	/* White C1 port */
-
-/* Unused signals */
-GPIO(CHARGER_INT_L,		PIN(7, 3), GPIO_INPUT)		/* Interrupt not used from ISL9241, on board pull-up */
-GPIO(EC_GP_SEL0_ODL,		PIN(B, 6), GPIO_OUT_LOW) 	/* Cannot be configured as input, drive output low, don't rely on the default setting of PxDOUT register */
-GPIO(CPU_C10_GATE_L, 		PIN(6, 7), GPIO_INPUT)		/* Unused power sequence signal from AP. Has an on-board pull-down. */
-GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP) /* Unconnected power sequencing signal */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO93,		PIN(9, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOB5,		PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
-GPIO(UNUSED_GPIOB4,		PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
-/* Only connected to test points */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
diff --git a/board/chronicler/keyboard.c b/board/chronicler/keyboard.c
deleted file mode 100644
index b9cc378295..0000000000
--- a/board/chronicler/keyboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard config common to ECOS and zephyr */
-
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/chronicler/led.c b/board/chronicler/led.c
deleted file mode 100644
index dfa7fefa1b..0000000000
--- a/board/chronicler/led.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Chronicler
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_CYCLE_TIME_MS   (2 * 1000)
-#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS      (1 * 1000)
-#define LED_ON_TICKS        (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
-
-static void led_set_color_battery(enum led_port port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
-	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int suspend_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Chronicler, Chronicler doesn't
-	 * have power LED, blinking both two side battery white
-	 * LEDs to indicate system suspend without charging state.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
-		suspend_ticks++;
-
-		led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		return;
-	}
-
-	suspend_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/chronicler/usbc_config.c b/board/chronicler/usbc_config.c
deleted file mode 100644
index b378299f86..0000000000
--- a/board/chronicler/usbc_config.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific USB-C configuration */
-#include "common.h"
-#include "cbi_ec_fw_config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/sn5s330_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/rt1715_public.h"
-#include "driver/tcpm/tusb422_public.h"
-#include "driver/tcpm/tcpci.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-/*
- * Adjust USB3 settings to improve signal integrity.
- * See b/194985848.
- */
-__override void board_ps8xxx_tcpc_init(int port)
-{
-	int rv;
-
-	CPRINTS("%s", __func__);
-
-	/* TX1 EQ 19db / TX2 EQ 19db */
-	rv = tcpc_addr_write(port, PS8751_I2C_ADDR1_P1_FLAGS, 0x20, 0x77);
-	/* RX1 EQ 12db / RX2 EQ 13db */
-	rv |= tcpc_addr_write(port, PS8751_I2C_ADDR1_P1_FLAGS, 0x22, 0x32);
-	/* Swing level for upstream port output */
-	rv |= tcpc_addr_write(port, PS8751_I2C_ADDR1_P1_FLAGS, 0xc4, 0x03);
-
-	if (rv)
-		CPRINTS("%s fail!", __func__);
-}
-
-/* Called on AP S5 -> S0 transition */
-void board_ps8811_init(void)
-{
-	int rv;
-	const int port = I2C_PORT_USB_1_MIX;
-	const int addr = PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1;
-
-	CPRINTS("%s", __func__);
-
-	/* AEQ 12db */
-	rv = i2c_write8(port, addr, 0x01, 0x26);
-	/* ADE 2.1db */
-	rv |= i2c_write8(port, addr, 0x02, 0x60);
-	/* BEQ 10.5db */
-	rv |= i2c_write8(port, addr, 0x05, 0x16);
-	/* BDE 2.1db */
-	rv |= i2c_write8(port, addr, 0x06, 0x63);
-	/* Channel A swing level */
-	rv |= i2c_write8(port, addr, 0x66, 0x20);
-	/* Channel B swing level */
-	rv |= i2c_write8(port, addr, 0xa4, 0x03);
-	/* PS level foe B channel */
-	rv |= i2c_write8(port, addr, 0xa5, 0x83);
-	/* DE level foe B channel */
-	rv |= i2c_write8(port, addr, 0xa6, 0x14);
-
-	if (rv)
-		CPRINTS("%s fail!", __func__);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_ps8811_init, HOOK_PRIO_LAST);
-
-void board_reset_pd_mcu(void)
-{
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-/******************************************************************************/
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/chronicler/usbc_config.h b/board/chronicler/usbc_config.h
deleted file mode 100644
index 55dfce7621..0000000000
--- a/board/chronicler/usbc_config.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* volteer board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/* Configure the USB3 daughterboard type */
-void config_usb3_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/chronicler/vif_override.xml b/board/chronicler/vif_override.xml
deleted file mode 100644
index f871a543e3..0000000000
--- a/board/chronicler/vif_override.xml
+++ /dev/null
@@ -1,114 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
-  <Model_Part_Number>Volteer RT1715</Model_Part_Number>
-  <Product_Revision>0</Product_Revision>
-  <TID>0</TID>
-  <Product>
-    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
-    <USB4_Num_Internal_Host_Controllers value="1" />
-    <USB4_Num_PCIe_DN_Bridges value="0" />
-    <USB4RouterList>
-      <Usb4Router>
-        <USB4_Router_ID value="1" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="4" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="1" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="4" />
-        <USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="true" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-        <USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
-        <USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
-        <USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
-      </Usb4Router>
-      <Usb4Router>
-        <USB4_Router_ID value="0" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="2" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="0" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="0" />
-        <USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="false" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-      </Usb4Router>
-    </USB4RouterList>
-  </Product>
-  <Component>
-    <!-- Port 0 is USB3-only. -->
-    <USB4_Supported value="false">NO</USB4_Supported>
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <DFP_VDO_Port_Number value="0" />
-    <Modal_Operation_Supported_SOP value="false" />
-  </Component>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="1" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-</VIF>
diff --git a/board/coachz/base_detect.c b/board/coachz/base_detect.c
deleted file mode 100644
index 0068b37d8d..0000000000
--- a/board/coachz/base_detect.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coachz base detection code */
-
-#include "adc.h"
-#include "board.h"
-#include "base_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
-#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * Lid has 604K pull-up, base has 30.1K pull-down, so the
- * ADC value should be around 30.1/(604+30.1)*3300 = 156
- *
- * We add a significant margin on the maximum value, due to noise on the line,
- * especially when PWM is active. See b/64193554 for details.
- */
-#define BASE_DETECT_MIN_MV 120
-#define BASE_DETECT_MAX_MV 300
-
-/* Minimum ADC value to indicate base is disconnected for sure */
-#define BASE_DETECT_DISCONNECT_MIN_MV 1500
-
-/*
- * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
- * can be used to wake system from deep S3).
- */
-#define BASE_DETECT_PULSE_MIN_US 400
-#define BASE_DETECT_PULSE_MAX_US 650
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Change in power to base
- * 2. Indicate mode change to host.
- * 3. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	gpio_set_level(GPIO_EN_BASE, connected);
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-	base_set_state(connected);
-	current_base_status = status;
-}
-
-/* Measure detection pin pulse duration (used to wake AP from deep S3). */
-static uint64_t pulse_start;
-static uint32_t pulse_width;
-
-static void print_base_detect_value(int v, int tmp_pulse_width)
-{
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-	uint32_t tmp_pulse_width = pulse_width;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		return;
-
-	print_base_detect_value(v, tmp_pulse_width);
-
-	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
-		if (current_base_status != BASE_CONNECTED) {
-			base_detect_change(BASE_CONNECTED);
-		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
-			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
-			CPRINTS("Sending event to AP");
-			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-		}
-		return;
-	}
-
-	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
-		base_detect_change(BASE_DISCONNECTED);
-		return;
-	}
-
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static inline int detect_pin_connected(enum gpio_signal det_pin)
-{
-	return gpio_get_level(det_pin) == 0;
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-	int debounce_us;
-	
-	if (detect_pin_connected(signal))
-		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-        else
-		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-  
-	if (base_detect_debounce_time <= time_now) {
-		/*
-		 * Detect and measure detection pin pulse, when base is
-		 * connected. Only a single pulse is measured over a debounce
-		 * period. If no pulse, or multiple pulses are detected,
-		 * pulse_width is set to 0.
-		 */
-		if (current_base_status == BASE_CONNECTED &&
-		    !detect_pin_connected(signal)) {
-			pulse_start = time_now;
-		} else {
-			pulse_start = 0;
-		}
-		pulse_width = 0;
-
-		hook_call_deferred(&base_detect_deferred_data, debounce_us);
-	} else {
-		if (current_base_status == BASE_CONNECTED &&
-		    detect_pin_connected(signal) && !pulse_width &&
-		    pulse_start) {
-			/* First pulse within period. */
-			pulse_width = time_now - pulse_start;
-		} else {
-			pulse_start = 0;
-			pulse_width = 0;
-		}
-	}
-
-	base_detect_debounce_time = time_now + debounce_us;
-}
-
-static void base_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data, 0);
-	gpio_enable_interrupt(GPIO_BASE_DET_L);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
-
-static void base_disable(void)
-{
-	/*
-	 * Disable base detection interrupt and disable power to base.
-	 * Set the state UNKNOWN so the next startup will initialize a
-	 * correct state and notify AP.
-	 */
-	gpio_disable_interrupt(GPIO_BASE_DET_L);
-	base_detect_change(BASE_UNKNOWN);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * If we jumped to this image and chipset is already in S0, enable
-	 * base.
-	 */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		base_enable();
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		base_enable();
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/coachz/battery.c b/board/coachz/battery.c
deleted file mode 100644
index 56c89b655b..0000000000
--- a/board/coachz/battery.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all coachz battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* COSMX GH02047XL 333-1C-DA-A */
-	[BATTERY_GH02047XL_1C] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.device_name = "GH02047XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* COSMX GH02047XL */
-	[BATTERY_GH02047XL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.device_name = "GH02047XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* COSMX DS02032XL */
-	[BATTERY_DS02032XL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-13-A",
-			.device_name = "DS02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* SMP DS02032XL */
-	[BATTERY_DS02032XL_1C] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-13-A",
-			.device_name = "DS02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DS02032XL;
diff --git a/board/coachz/board.c b/board/coachz/board.c
deleted file mode 100644
index d1f31a64c3..0000000000
--- a/board/coachz/board.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coachz board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "mkbp_input_devices.h"
-#include "peripheral_charger.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "queue.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-static void ks_interrupt(enum gpio_signal s);
-
-#include "gpio_list.h"
-
-/*
- * Workaround for b/193223400. This disables the IRQ from CTN730. Fixing this
- * here (using a rather awkward way) separates the fix from the common code.
- */
-#ifdef SECTION_IS_RW
-#define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN
-#else
-#define GPIO_PCHG_P0 ARRAY_SIZE(gpio_irq_handlers)
-#endif
-
-extern struct pchg_drv ctn730_drv;
-
-struct pchg pchgs[] = {
-	[0] = {
-		.cfg = &(const struct pchg_config) {
-			.drv = &ctn730_drv,
-			.i2c_port = I2C_PORT_WLC,
-			.irq_pin = GPIO_PCHG_P0,
-			.full_percent = 96,
-			.block_size = 128,
-		},
-		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
-	},
-};
-const int pchg_count = ARRAY_SIZE(pchgs);
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static int debounced_ks_attached;
-static int debounced_ks_open;
-
-/**
- * Kickstand switch initialization
- */
-static void ks_init(void)
-{
-	debounced_ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
-	debounced_ks_open = gpio_get_level(GPIO_KS_OPEN);
-
-	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_KS_ATTACHED_L);
-	gpio_enable_interrupt(GPIO_KS_OPEN);
-}
-DECLARE_HOOK(HOOK_INIT, ks_init, HOOK_PRIO_INIT_SWITCH);
-
-/**
- * Handle debounced kickstand switch changing state.
- */
-static void ks_change_deferred(void)
-{
-	const int ks_attached = !gpio_get_level(GPIO_KS_ATTACHED_L);
-	const int ks_open = gpio_get_level(GPIO_KS_OPEN);
-	int proximity_detected;
-
-	/* If the switches haven't changed, nothing to do */
-	if (ks_attached == debounced_ks_attached &&
-	    ks_open == debounced_ks_open)
-		return;
-
-	/*
-	 * A heuristic method to use the kickstand position to approach
-	 * the human body proximity.
-	 */
-	proximity_detected = !(ks_attached && ks_open);
-	CPRINTS("ks %s %s -> proximity %s",
-		ks_attached ? "attached" : "detached",
-		ks_open ? "open" : "close",
-		proximity_detected ? "on" : "off");
-
-	debounced_ks_attached = ks_attached;
-	debounced_ks_open = ks_open;
-
-	mkbp_update_switches(EC_MKBP_FRONT_PROXIMITY, proximity_detected);
-}
-DECLARE_DEFERRED(ks_change_deferred);
-
-static void ks_interrupt(enum gpio_signal s)
-{
-	/* Reset kickstand debounce time */
-	hook_call_deferred(&ks_change_deferred_data, KS_DEBOUNCE_US);
-}
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"wlc",     I2C_PORT_WLC,    400, GPIO_EC_I2C_WLC_SCL,
-					  GPIO_EC_I2C_WLC_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Mutexes */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct bmi_drv_data_t g_bmi260_data;
-
-bool is_bmi260_present;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-struct motion_sensor_t motion_sensors_260[] = {
-	/*
-	 * Note: bmi260: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI260,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi260_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI260,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi260_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int val = -1;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	/* Check base accelgyro chip */
-	bmi_read8(motion_sensors[LID_ACCEL].port,
-		motion_sensors[LID_ACCEL].i2c_spi_addr_flags,
-		BMI260_CHIP_ID, &val);
-	if (val == BMI260_CHIP_ID_MAJOR) {
-		motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL];
-		motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO];
-		is_bmi260_present = 1;
-	} else {
-		is_bmi260_present = 0;
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (is_bmi260_present) {
-		bmi260_interrupt(signal);
-	} else {
-		bmi160_interrupt(signal);
-	}
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * The rev-1 hardware doesn't have the external pull-up fix for the bug
-	 * b/177611071. It requires rework to stuff the resistor. For people who
-	 * has difficulty to do the rework, this is a workaround, which makes
-	 * the GPIO push-pull, instead of open-drain.
-	 */
-	if (system_get_board_version() == 1)
-		gpio_set_flags(GPIO_HIBERNATE_L, GPIO_OUTPUT);
-
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__overridable uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Coachz board rev 2+ changes TCPC from 8805 to 8755*/
-	if (system_get_board_version() < 2)
-		return PS8805_PRODUCT_ID;
-
-	return PS8755_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Board rev 1+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 1)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_DA9313_GPIO0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/coachz/board.h b/board/coachz/board.h
deleted file mode 100644
index d5e69aa4b2..0000000000
--- a/board/coachz/board.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coachz board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* On-body detection */
-#define CONFIG_BODY_DETECTION
-#define CONFIG_BODY_DETECTION_SENSOR           LID_ACCEL
-#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
-#define CONFIG_GESTURE_HOST_DETECTION
-
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Save some flash space */
-#define CONFIG_LTO
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_MMAPINFO
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_ACCEL_FIFO
-#undef CONFIG_CMD_ACCEL_INFO
-#undef CONFIG_CMD_TASK_RESET
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_VENDOR_PARAM
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* BMI160 Lid accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define CONFIG_FRONT_PROXIMITY_SWITCH
-
-#define CONFIG_MKBP_INPUT_DEVICES
-
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_BASE_ATTACHED_SWITCH
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
-#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L
-#define GPIO_KS_ATTACHED_L GPIO_LID_INT_N_HALL1
-#define GPIO_KS_OPEN GPIO_LID_INT_N_HALL2
-
-/* WLC pins */
-#define CONFIG_PERIPHERAL_CHARGER
-#define CONFIG_DEVICE_EVENT
-#define CONFIG_CTN730
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_BASE_DET,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_GH02047XL_1C,
-	BATTERY_GH02047XL,
-	BATTERY_DS02032XL,
-	BATTERY_DS02032XL_1C,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Base detection */
-void base_detect_interrupt(enum gpio_signal signal);
-/* motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/coachz/build.mk b/board/coachz/build.mk
deleted file mode 100644
index 5b6ecb0398..0000000000
--- a/board/coachz/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y=battery.o board.o led.o base_detect.o
diff --git a/board/coachz/ec.tasklist b/board/coachz/ec.tasklist
deleted file mode 100644
index dc5b32b4cf..0000000000
--- a/board/coachz/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/coachz/gpio.inc b/board/coachz/gpio.inc
deleted file mode 100644
index d7ca61ac6b..0000000000
--- a/board/coachz/gpio.inc
+++ /dev/null
@@ -1,199 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-
-/* WLC interrupt. GPIO_PULL_DOWN ensures no IRQ when WLC chip is off. */
-GPIO_INT(WLC_IRQ_CONN, PIN(7, 4), GPIO_INT_RISING | GPIO_PULL_DOWN, pchg_irq)
-
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
-
-/* Sensor interrupts */
-GPIO_INT(LID_360_L,         PIN(7, 3), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(LID_INT_N_HALL1,   PIN(D, 7), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand attached (0) or detached (1) */
-GPIO_INT(LID_INT_N_HALL2,   PIN(6, 0), GPIO_INT_BOTH, ks_interrupt)  /* Kickstand close (0) or open (1) */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
- * need to be an interrupt for normal EC operations. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* TODO(waihong): Should remove it from hardware */
-GPIO(CAM_LED,               PIN(3, 0), GPIO_INPUT)
-
-/* Reset line for WLC. External pull-up is expected. */
-GPIO(WLC_NRST_CONN,         PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Base detection */
-GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_WLC_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_WLC_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. Apply PU for power saving */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(3, 1))
-UNUSED(PIN(2, 7))
-UNUSED(PIN(2, 6))
-UNUSED(PIN(2, 5))
-UNUSED(PIN(2, 4))
-UNUSED(PIN(2, 3))
-UNUSED(PIN(2, 2))
-UNUSED(PIN(2, 1))
-UNUSED(PIN(2, 0))
-UNUSED(PIN(1, 7))
-UNUSED(PIN(1, 6))
-UNUSED(PIN(1, 5))
-UNUSED(PIN(1, 4))
-UNUSED(PIN(1, 3))
-UNUSED(PIN(1, 2))
-UNUSED(PIN(1, 1))
-UNUSED(PIN(1, 0))
-UNUSED(PIN(0, 7))
-UNUSED(PIN(0, 6))
-UNUSED(PIN(0, 5))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 6))
-UNUSED(PIN(C, 0))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 6))
-UNUSED(PIN(8, 0))
-UNUSED(PIN(D, 3))
-UNUSED(PIN(7, 5))
-UNUSED(PIN(8, 6))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)             /* I2C3 (GPIOD0/D1) */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
diff --git a/board/coachz/led.c b/board/coachz/led.c
deleted file mode 100644
index 9dd8729a04..0000000000
--- a/board/coachz/led.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-#include "extpower.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-/* Battery LED blinks every per 400ms */
-#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_AMBER;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: White 1 sec, off 1 sec */
-			period = (1 + 1) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC) {
-				if (charge_get_percent() < 10)
-                                {
-                                	/* Blink amber light (1 sec on, 1 sec off) */
-					color = LED_AMBER;
-                                }
-				else
-                                {
-                                	/* Blink white light (1 sec on, 1 sec off) */
-					color = LED_BLUE;
-                                }
-			} else {
-				color = LED_OFF;
-			}
-		} else {
-			/* Discharging in S5 and S0: off */
-			/* Blink amber light (1 sec on, 1 sec off) */
-			if (charge_get_percent() < 10) {
-				period = (1 + 1) * LED_ONE_SEC;
-				battery_ticks = battery_ticks % period;
-				if (battery_ticks < 1 * LED_ONE_SEC)
-					color = LED_AMBER;
-				else
-					color = LED_OFF;
-			} else {
-				/* G3 or S5 or S0: off */
-				color = LED_OFF;
-			}
-		}
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber on 0.5 sec, off 0.5 sec */
-		period = (1 + 1) * LED_HALF_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_HALF_ONE_SEC)
-			color = LED_AMBER;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: Blue on */
-		/* S3: Blink white light (1 sec on, 1 sec off) */
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			period = (1 + 1) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_OFF;
-		} else {
-			/* Full charged: White on */
-			color = LED_BLUE;
-		}
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
-			color = LED_BLUE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_BLUE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/coachz/vif_override.xml b/board/coachz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/coachz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c
deleted file mode 100644
index 2939a65125..0000000000
--- a/board/coffeecake/board.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Coffeecake dock configuration */
-
-#include "adc.h"
-#include "charger/sy21612.h"
-#include "clock.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "mcdp28x0.h"
-#include "registers.h"
-#include "task.h"
-#include "usb_bb.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "timer.h"
-#include "util.h"
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-
-void hpd_event(enum gpio_signal signal);
-void vbus_event(enum gpio_signal signal);
-#include "gpio_list.h"
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"charger", I2C_PORT_SY21612, 400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_irq_deferred(void)
-{
-	pd_send_hpd(0, hpd_irq);
-}
-DECLARE_DEFERRED(hpd_irq_deferred);
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DP_HPD);
-
-	if (level != hpd_prev_level)
-		/* It's a glitch while in deferred or canceled action */
-		return;
-
-	pd_send_hpd(0, (level) ? hpd_high : hpd_low);
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-void hpd_event(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data, -1);
-
-	/* It's a glitch.  Previous time moves but level is the same. */
-	if (cur_delta < HPD_USTREAM_DEBOUNCE_IRQ)
-		return;
-
-	if ((!hpd_prev_level && level) &&
-	    (cur_delta < HPD_USTREAM_DEBOUNCE_LVL))
-		/* It's an irq */
-		hook_call_deferred(&hpd_irq_deferred_data, 0);
-	else if (cur_delta >= HPD_USTREAM_DEBOUNCE_LVL)
-		hook_call_deferred(&hpd_lvl_deferred_data,
-				   HPD_USTREAM_DEBOUNCE_LVL);
-
-	hpd_prev_level = level;
-}
-
-/* Proto 0 workaround */
-void vbus_event(enum gpio_signal signal)
-{
-	/* Discharge VBUS on DET_L high */
-	gpio_set_level(GPIO_PD_DISCHARGE, gpio_get_level(signal));
-}
-
-/* USB C VBUS output selection */
-void board_set_usb_output_voltage(int mv)
-{
-	const int ra = 40200;
-	const int rb = 10000;
-	const int rc = 6650;
-	int dac_mv;
-	uint32_t dac_val;
-
-	if (mv >= 0) {
-		/* vbat = 1.0 * ra/rb + 1.0 - (vdac - 1.0) * ra/rc */
-		dac_mv = 1000 + (1000 * rc / rb) + ((1000 - mv) * rc / ra);
-		if (dac_mv < 0)
-			dac_mv = 0;
-
-		/* Set voltage Vout=Vdac with Vref = 3.3v */
-		/* TODO: use Vdda instead */
-		dac_val = dac_mv * 4096 / 3300;
-		/* Start DAC channel 2 */
-		STM32_DAC_DHR12RD = dac_val << 16;
-		STM32_DAC_CR = STM32_DAC_CR_EN2;
-	} else {
-		STM32_DAC_CR = 0;
-	}
-}
-
-/* Initialize board. */
-void board_config_pre_init(void)
-{
-	/* Enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Enable DAC interface clock. */
-	STM32_RCC_APB1ENR |= BIT(29);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* Set 5Vsafe Vdac */
-	board_set_usb_output_voltage(5000);
-	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
-}
-
-#ifdef CONFIG_SPI_FLASH
-
-static void board_init_spi2(void)
-{
-	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-
-	/* Set pin NSS to general purpose output mode (01b). */
-	/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
-	STM32_GPIO_MODER(GPIO_B) &= ~0xff000000;
-	STM32_GPIO_MODER(GPIO_B) |= 0xa9000000;
-
-	/* Set all four pins to alternate function 0 */
-	STM32_GPIO_AFRH(GPIO_B) &= ~(0xffff0000);
-
-	/* Set all four pins to output push-pull */
-	STM32_GPIO_OTYPER(GPIO_B) &= ~(0xf000);
-
-	/* Set pullup on NSS */
-	STM32_GPIO_PUPDR(GPIO_B) |= 0x1000000;
-
-	/* Set all four pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= BIT(14);
-	STM32_RCC_APB1RSTR &= ~BIT(14);
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-}
-#endif /* CONFIG_SPI_FLASH */
-
-static void factory_validation_deferred(void)
-{
-	struct mcdp_info info;
-
-	mcdp_enable();
-
-	/* test mcdp via serial to validate function */
-	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
-		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
-	}
-
-	mcdp_disable();
-}
-DECLARE_DEFERRED(factory_validation_deferred);
-
-static void board_post_init(void)
-{
-	sy21612_enable_regulator(1);
-	/*
-	 * AC powered  - DRP SOURCE
-	 * DUT powered - DRP SINK
-	 */
-	pd_set_dual_role(0, gpio_get_level(GPIO_AC_PRESENT_L) ?
-			 PD_DRP_FORCE_SINK : PD_DRP_FORCE_SOURCE);
-}
-DECLARE_DEFERRED(board_post_init);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	timestamp_t now;
-#ifdef CONFIG_SPI_FLASH
-	board_init_spi2();
-#endif
-	now = get_time();
-	hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
-	hpd_prev_ts = now.val;
-	gpio_enable_interrupt(GPIO_DP_HPD);
-	gpio_enable_interrupt(GPIO_CHARGER_INT);
-	gpio_enable_interrupt(GPIO_USB_C_VBUS_DET_L);
-	/* Set PD_DISCHARGE initial state */
-	gpio_set_level(GPIO_PD_DISCHARGE, gpio_get_level(GPIO_USB_C_VBUS_DET_L));
-
-	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
-	/* Initialize buck-boost converter */
-	hook_call_deferred(&board_post_init_data, 0);
-}
-
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD]    = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_VBUS_MON]     = {"VBUS_MON", 13200, 4096, 0, STM32_AIN(2)},
-	[ADC_DAC_REF_TP28] = {"DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DAC_VOLT]     = {"DAC_VOLT", 3300, 4096, 0, STM32_AIN(5)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const void * const usb_strings[] = {
-	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
-	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/**
- * USB configuration
- * Any type-C device with alternate mode capabilities must have the following
- * set of descriptors.
- *
- * 1. Standard Device
- * 2. BOS
- *    2a. Container ID
- *    2b. Billboard Caps
- */
-struct my_bos {
-	struct usb_bos_hdr_descriptor bos;
-	struct usb_contid_caps_descriptor contid_caps;
-	struct usb_bb_caps_base_descriptor bb_caps;
-	struct usb_bb_caps_svid_descriptor bb_caps_svids[1];
-};
-
-static struct my_bos bos_desc = {
-	.bos = {
-		.bLength = USB_DT_BOS_SIZE,
-		.bDescriptorType = USB_DT_BOS,
-		.wTotalLength = (USB_DT_BOS_SIZE + USB_DT_CONTID_SIZE +
-				 USB_BB_CAPS_BASE_SIZE +
-				 USB_BB_CAPS_SVID_SIZE * 1),
-		.bNumDeviceCaps = 2,  /* contid + bb_caps */
-	},
-	.contid_caps =	{
-		.bLength = USB_DT_CONTID_SIZE,
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_CONTID,
-		.bReserved = 0,
-		.ContainerID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-	},
-	.bb_caps = {
-		.bLength = (USB_BB_CAPS_BASE_SIZE + USB_BB_CAPS_SVID_SIZE * 1),
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_BILLBOARD,
-		.iAdditionalInfoURL = USB_STR_BB_URL,
-		.bNumberOfAlternateModes = 1,
-		.bPreferredAlternateMode = 1,
-		.VconnPower = 0,
-		.bmConfigured = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-				 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-		.bReserved = 0,
-	},
-	.bb_caps_svids = {
-		{
-			.wSVID = 0xff01, /* TODO(tbroch) def'd in other CL remove hardcode */
-			.bAlternateMode = 1,
-			.iAlternateModeString = USB_STR_BB_URL, /* TODO(crosbug.com/p/32687) */
-		},
-	},
-};
-
-const struct bos_context bos_ctx = {
-	.descp = (void *)&bos_desc,
-	.size = sizeof(struct my_bos),
-};
diff --git a/board/coffeecake/board.h b/board/coffeecake/board.h
deleted file mode 100644
index d655466a14..0000000000
--- a/board/coffeecake/board.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coffee cake configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Free up flash space */
-#define CONFIG_LTO
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_ADC
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_CMD_CHARGER
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CHARGER_SY21612
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#define CONFIG_RWSIG_TYPE_USBPD1
-#define CONFIG_SHA256
-/* TODO(tbroch) Re-enable once STM spi master can be inhibited at boot so it
-   doesn't interfere with HDMI loading its f/w */
-#undef CONFIG_SPI_FLASH
-#define CONFIG_SPI_CS_GPIO GPIO_PD_MCDP_SPI_CS_L
-#define CONFIG_USB
-#define CONFIG_USB_BOS
-#define CONFIG_USB_INHIBIT_CONNECT
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_HOHO
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 2
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FLASH
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-#define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
-#define CONFIG_EVENT_LOG_SIZE 256
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_PD_VBUS_DETECT_NONE
-/* mcdp2850 serial interface */
-#define CONFIG_MCDP28X0 usart3_hw
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART3
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* USB configuration */
-#define CONFIG_USB_PID 0x502f
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-/* No Write-protect GPIO, force the write-protection */
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-
-/* Inform VIF generator that this board is an Alt Mode Adapter */
-#define CONFIG_USB_ALT_MODE_ADAPTER
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CH_CC1_PD = 0,
-	ADC_VBUS_MON,
-	ADC_DAC_REF_TP28,
-	ADC_DAC_VOLT,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_BB_URL,
-
-	USB_STR_COUNT
-};
-
-/* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
-
-/* delay necessary for the voltage transition on the power supply */
-/* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078)
- * Need to measure these and adjust for honeybuns.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       22500
-#define PD_MAX_CURRENT_MA     2500
-#define PD_MAX_VOLTAGE_MV     9000
-
-/* Board interfaces */
-void board_set_usb_output_voltage(int mv);
-
-#endif /* !__ASSEMBLER__ */
-
-/* USB Device class */
-#define USB_DEV_CLASS USB_CLASS_BILLBOARD
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
-
-/* I2C ports */
-#define I2C_PORT_SY21612 0
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/coffeecake/build.mk b/board/coffeecake/build.mk
deleted file mode 100644
index fb5a6fccdb..0000000000
--- a/board/coffeecake/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072B
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Not enough SRAM: Disable all tests
-test-list-y=
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/coffeecake/dev_key.pem b/board/coffeecake/dev_key.pem
deleted file mode 100644
index 08d5bd414c..0000000000
--- a/board/coffeecake/dev_key.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEogIBAAKCAQEApfbLqgOYIM6AfRI6SJcj1Crengsp+yjHXtwZFOH6WDVP5Q9c
-KSbwqoKHEKTbWJ90ymjqjfi382hl64L/V6J8SfIqGhrFztwXLhJOwFXRK5Jgzkk+
-YUByDzAKTKOlzvvRqk10Tq5a3wphg1SxGVLLOOsTGoKhGI93Wkf2j8AibMlVVZzz
-Q8DmVszkYZL+Kchv6h1FgSvBW0oZa5tVod+0XToWSrPEYnBWs0zZEywCusIXMy7D
-LaqMPFB4LTkDZ9Ne8jnB5xRad+ME4CgxZqUwGC7tdFdHdiiXpIwzIoxVk6xFIZUF
-uusG4RR3O2ubaPJ/Fpf3UuuCWmddk37WaC7o7QIDAQABAoIBAAG4L94AEYhte0lQ
-cggkgLuHAi1zAilW/9HMx/m+aaCWVNCTuym1/JJXrdyPSLJ/XG9obN2xsP41m7C3
-97tJtK3zc1o34srE3vycNfKqMPOZnaUlfx700vmzTrgCjgo5868nBEh4Z/qdmesJ
-aphPkklxrg39QnwFqH/n9PcCT5j+7LyCeWeGbWxKfpzP2CT6v8XxT3XY1mtFSa4j
-dfYaqb+aunYAhjEb4gqa48hyNTQAZskDOUr1TK433wbGqRughXXrQQix+FBW483u
-IGo8aGgiQsjYxHX+ynNTMKW1Oap9WZRWVxF09Ph1f3MT+k3gKqM/0AejlDfBuTDu
-aLxiKIUCgYEA1FZmfGn4RNlghv/ZCAlfWqbf5NA1/wA/Knk8u0R+kMQ71e8NFjOc
-Ym3Uix+89KcKDBIgHn1360pNvSCeTyVU28wQ2bst5s6pvu4FYDvjym2nTgXcFJX6
-DDnZfVZ+WLSFR8E76LQLJGd00DSq0/uBw3ULyRSirkuQnFI3w3u4BH8CgYEAyBdD
-UMV83kwQaDMuGgKqZtD4Ou3s/MDzMwcNgUSjLIueFdsXVnlzYQwwJXuLFkrp5COx
-Zyoha/d1QQawnYehKmHWWy7qN/l0CO+F2DGb1E6pNXJrn+zn33Mgz9ms8421eqqn
-ATQbq6ZQInk1IrkLfyZ3t09l6cyBMJuJjkoBrJMCgYA2Hfsq1FtJONnILmbjDHh4
-AzXm/EX2wtpWeeXHmLJlNQ5G/REpymeeEn3sI1+mPvhpkSkMfE/W8O4VOL4AT/Rr
-vHvC8ljFjYBnwAQwvbLVwdK1KPspZ/v9p7TNpAC5nPCnFBGvwktgsNltwy6SrnQp
-G6iwTAkWQP4PSUkbEmoZAwKBgF0OLJlQ70y3FV5Qhx1DphohD4DgjDnURoaxvf8j
-e7vIxuGlPgpSe21j7LRR65KXjoUycFvpRRfgQyDVyqfInxSF4doQTI9xrRxGwPmV
-wMIRPzKDHziGRiQud9ESjBPNENyWpwqxQDkpJNWThzm503Xz3vNasqv0FxUTEPsi
-wfqPAoGABXPl7baUkpYzppAJqRlGNxsMjpbWscDPjmPosrGs6d81DP287s/IjfDR
-ysQptvhJRK/lubM8As+d0/VLd6P8wk8dyZR1nRELwnVaPC55cS5+YIjgXK9TBmLA
-hC0BIgujJS2qbXQRQF7yX925Gg77WLN2sJqtVg1Brine056pHTA=
------END RSA PRIVATE KEY-----
diff --git a/board/coffeecake/ec.tasklist b/board/coffeecake/ec.tasklist
deleted file mode 100644
index d6686d72e9..0000000000
--- a/board/coffeecake/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(SY21612, sy21612_task, NULL, SMALLER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/coffeecake/gpio.inc b/board/coffeecake/gpio.inc
deleted file mode 100644
index bab62a6bea..0000000000
--- a/board/coffeecake/gpio.inc
+++ /dev/null
@@ -1,52 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(DP_HPD,           PIN(A, 0),  GPIO_INT_BOTH, hpd_event)
-GPIO_INT(CHARGER_INT,      PIN(C, 13), GPIO_INT_FALLING, sy21612_int)
-GPIO_INT(USB_C_VBUS_DET_L, PIN(C, 14), GPIO_INT_BOTH, vbus_event)
-
-GPIO(USB_C_CC1_PD,     PIN(A, 1),  GPIO_ANALOG)
-GPIO(VBUS_DIV4_MON,    PIN(A, 2),  GPIO_ANALOG)
-GPIO(MCDP_RESET_L,     PIN(A, 3),  GPIO_OUT_HIGH)
-GPIO(PD_DAC_REF_TP28,  PIN(A, 4),  GPIO_ANALOG)
-GPIO(DAC_VBUS_VOLT,    PIN(A, 5),  GPIO_ANALOG)
-GPIO(LED_GREEN,        PIN(A, 6),  GPIO_OUT_LOW)
-GPIO(LED_BLUE,         PIN(A, 7),  GPIO_OUT_LOW)
-
-GPIO(PD_SBU_ENABLE,    PIN(A, 8),  GPIO_OUT_LOW)
-GPIO(USB_DM,           PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,           PIN(A, 12), GPIO_ANALOG)
-GPIO(PD_DISCHARGE,     PIN(A, 13), GPIO_OUT_LOW)
-GPIO(PD_CC1_ODL,       PIN(A, 15), GPIO_OUT_LOW)
-
-GPIO(EN_PP3300,        PIN(B, 0),  GPIO_OUT_HIGH)
-GPIO(MCU_PB1,          PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(PD_MCDP_SPI_WP_L, PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(PD_CC1_TX_DATA,   PIN(B, 4),  GPIO_INPUT)
-GPIO(PD_CC1_HOST_HIGH, PIN(B, 5),  GPIO_INPUT)
-GPIO(I2C0_SCL,         PIN(B, 6),  GPIO_INPUT)
-GPIO(I2C0_SDA,         PIN(B, 7),  GPIO_INPUT)
-GPIO(LED_ORANGE,       PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(PD_MCDP_SPI_CS_L, PIN(B, 12), GPIO_INPUT)
-
-GPIO(AC_PRESENT_L,     PIN(C, 15), GPIO_INPUT)
-
-GPIO(EN_PP5000,        PIN(F,  0), GPIO_OUT_HIGH)
-GPIO(EN_USB_PD,        PIN(F,  1), GPIO_OUT_HIGH)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0)            /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0)            /* TIM16_CH1: PB9 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 4, MODULE_UART,   GPIO_PULL_UP) /* USART3: PB10/PB11 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 1, MODULE_I2C,   0)             /* I2C MASTER:PB6/7 */
diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h
deleted file mode 100644
index e2c1dbb2db..0000000000
--- a/board/coffeecake/usb_pd_config.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 16
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PB3-4 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* SPI1_TX no remap needed */
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) BIT(21)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* TIM1_CH1 no remap needed */
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 Mhz pin speed on TX_EN (PA15) */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
-	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* PB4 is SPI1_MISO */
-	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-	/* USB_C_CC1_PD: PA1 output low */
-	gpio_set_flags(GPIO_USB_C_CC1_PD, GPIO_OUTPUT);
-	gpio_set_level(GPIO_USB_C_CC1_PD, 0);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* SPI TX (PB4) Hi-Z */
-	gpio_set_flags(GPIO_PD_CC1_TX_DATA, GPIO_INPUT);
-	/* put the low level reference in Hi-Z */
-	gpio_set_flags(GPIO_USB_C_CC1_PD, GPIO_ANALOG);
-}
-
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	if (enable) {
-		gpio_set_level(GPIO_PD_CC1_ODL, 1);
-		gpio_set_flags(GPIO_PD_CC1_HOST_HIGH, GPIO_OUTPUT);
-		gpio_set_level(GPIO_PD_CC1_HOST_HIGH, 1);
-	} else {
-		gpio_set_flags(GPIO_PD_CC1_HOST_HIGH, GPIO_INPUT);
-		gpio_set_level(GPIO_PD_CC1_ODL, 0);
-	}
-}
-
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	if (cc == 0)
-		return adc_read_channel(ADC_CH_CC1_PD);
-	/*
-	 * Check HOST_HIGH Rp setting.
-	 * Return 3300mV on host mode.
-	 */
-	if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2*5))) == (1 << (2*5)))
-		return 3300;
-	else
-		return 0;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/coffeecake/usb_pd_policy.c b/board/coffeecake/usb_pd_policy.c
deleted file mode 100644
index dc19207a0e..0000000000
--- a/board/coffeecake/usb_pd_policy.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "board.h"
-#include "charger/sy21612.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_api.h"
-#include "usb_bb.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS_EXT (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-
-/* Voltage indexes for the PDOs */
-enum volt_idx {
-	PDO_IDX_5V  = 0,
-	PDO_IDX_9V  = 1,
-	/* TODO: add PPS support */
-	PDO_IDX_COUNT
-};
-
-/* PDOs */
-const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS_EXT),
-	[PDO_IDX_9V]  = PDO_FIXED(9000,  2500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-/* Holds valid object position (opos) for entered mode */
-static int alt_mode[PD_AMODE_COUNT];
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* No battery, nothing to do */
-	return;
-}
-
-int pd_is_valid_input_voltage(int mv)
-{
-	/* Any voltage less than the max is allowed */
-	return 1;
-}
-
-void pd_transition_voltage(int idx)
-{
-	/* TODO: discharge, PPS */
-	switch (idx - 1) {
-	case PDO_IDX_9V:
-		board_set_usb_output_voltage(9000);
-		break;
-	case PDO_IDX_5V:
-	default:
-		board_set_usb_output_voltage(5000);
-		break;
-	}
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Turn on DAC and adjust feedback to get 5V output */
-	board_set_usb_output_voltage(5000);
-	/* Enable Vsys to USBC Vbus charging */
-	sy21612_set_sink_mode(1);
-	sy21612_set_adc_mode(1);
-	sy21612_enable_adc(1);
-	sy21612_set_vbus_discharge(0);
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Turn off DAC output */
-	board_set_usb_output_voltage(-1);
-	/* Turn off USBC VBUS output */
-	sy21612_set_sink_mode(0);
-	/* Set boost Vsys output 9V */
-	sy21612_set_vbus_volt(SY21612_VBUS_9V);
-	/* Turn on buck-boost converter ADC */
-	sy21612_set_adc_mode(1);
-	sy21612_enable_adc(1);
-	sy21612_set_vbus_discharge(1);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return 1;
-}
-
-int pd_board_checks(void)
-{
-	return EC_SUCCESS;
-}
-
-int pd_check_power_swap(int port)
-{
-	/* Always refuse power swap */
-	return 0;
-}
-
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
-{
-	/* We can swap to UFP */
-	return data_role == PD_ROLE_DFP;
-}
-
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
-{
-	/* TODO: turn on pp5000, pp3300 */
-}
-
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
-{
-	if (pr_role == PD_ROLE_SINK && !gpio_get_level(GPIO_AC_PRESENT_L))
-		pd_request_power_swap(port);
-
-}
-
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
-{
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
-		pd_request_data_swap(port);
-}
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 1, /* Vbus power required */
-				 AMA_USBSS_BBONLY /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	/* TODO(tbroch): Do we plan to obtain TID (test ID) for hoho */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	payload[VDO_I(AMA)] = vdo_ama;
-	return VDO_I(AMA) + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, USB_VID_GOOGLE);
-	payload[2] = 0;
-	return 3;
-}
-
-#define OPOS_DP 1
-#define OPOS_GFU 1
-
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
-		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
-};
-
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes));
-		return ARRAY_SIZE(vdo_dp_modes) + 1;
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		memcpy(payload + 1, vdo_goog_modes, sizeof(vdo_goog_modes));
-		return ARRAY_SIZE(vdo_goog_modes) + 1;
-	} else {
-		return 0; /* nak */
-	}
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = gpio_get_level(GPIO_DP_HPD);
-	if (opos != OPOS_DP)
-		return 0; /* nak */
-
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
-				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
-				   0x2);
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 1);
-	return 1;
-}
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	int rv = 0; /* will generate a NAK */
-
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
-	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
-		alt_mode[PD_AMODE_DISPLAYPORT] = OPOS_DP;
-		rv = 1;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 1, NULL);
-	} else if ((PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) &&
-		   (PD_VDO_OPOS(payload[0]) == OPOS_GFU)) {
-		alt_mode[PD_AMODE_GOOGLE] = OPOS_GFU;
-		rv = 1;
-	}
-
-	if (rv)
-		/*
-		 * If we failed initial mode entry we'll have enumerated the USB
-		 * Billboard class.  If so we should disconnect.
-		 */
-		usb_disconnect();
-
-	return rv;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	if (type != TCPCI_MSG_SOP)
-		return 0;
-
-	if (svid == USB_SID_DISPLAYPORT)
-		return alt_mode[PD_AMODE_DISPLAYPORT];
-	else if (svid == USB_VID_GOOGLE)
-		return alt_mode[PD_AMODE_GOOGLE];
-	return 0;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 0);
-		alt_mode[PD_AMODE_DISPLAYPORT] = 0;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 0, NULL);
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		alt_mode[PD_AMODE_GOOGLE] = 0;
-	} else {
-		CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]);
-	}
-
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int rsize;
-
-	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE ||
-	    !alt_mode[PD_AMODE_GOOGLE])
-		return 0;
-
-	*rpayload = payload;
-
-	rsize = pd_custom_flash_vdm(port, cnt, payload);
-	if (!rsize) {
-		int cmd = PD_VDO_CMD(payload[0]);
-		switch (cmd) {
-		case VDO_CMD_GET_LOG:
-			rsize = pd_vdm_get_log_entry(payload);
-			break;
-		default:
-			/* Unknown : do not answer */
-			return 0;
-		}
-	}
-
-	/* respond (positively) to the request */
-	payload[0] |= VDO_SRC_RESPONDER;
-
-	return rsize;
-}
diff --git a/board/coffeecake/vif_override.xml b/board/coffeecake/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/coffeecake/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/collis/battery.c b/board/collis/battery.c
deleted file mode 100644
index 5da46e9caa..0000000000
--- a/board/collis/battery.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C490] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWQd3jB",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000c,
-				.disconnect_val = 0x000c,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0004,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 13200, /* mV */
-			.voltage_normal         = 11550, /* mV */
-			.voltage_min            = 9000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C490;
diff --git a/board/collis/board.c b/board/collis/board.c
deleted file mode 100644
index 42a0f1469a..0000000000
--- a/board/collis/board.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config copano_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &copano_kb;
-}
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Terrador if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_mb_retimer,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-/******************************************************************************/
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(int port)
-{
-	int val;
-	int i2c_port;
-	enum gpio_signal ps8xxx_rst_odl;
-
-	if (port == USBC_PORT_C0) {
-		ps8xxx_rst_odl = GPIO_USB_C0_RT_RST_ODL;
-		i2c_port = I2C_PORT_USB_C0;
-	} else if (port == USBC_PORT_C1) {
-		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-		i2c_port = I2C_PORT_USB_C1;
-	} else {
-		return;
-	}
-
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
-
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	ps8815_reset(USBC_PORT_C0);
-	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	ps8815_reset(USBC_PORT_C1);
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
diff --git a/board/collis/board.h b/board/collis/board.h
deleted file mode 100644
index 9bee8e2409..0000000000
--- a/board/collis/board.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-#undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0		/* GPIO C2 is not used as PWM1 */
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-
-/* BMI160 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W, the limitation of 45W is for the Collis
- * board.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_RT1715
-#undef CONFIG_USB_PD_TCPM_TUSB422
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C490,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/collis/build.mk b/board/collis/build.mk
deleted file mode 100644
index 546bcba8d2..0000000000
--- a/board/collis/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/collis/ec.tasklist b/board/collis/ec.tasklist
deleted file mode 100644
index e76bd368eb..0000000000
--- a/board/collis/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/collis/gpio.inc b/board/collis/gpio.inc
deleted file mode 100644
index 0bd40b8499..0000000000
--- a/board/collis/gpio.inc
+++ /dev/null
@@ -1,176 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C0_RT_INT_ODL,			PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,			PIN(4, 0), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-
-
-/* LED */
-GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)	/* Battery Full LED / Power LED: White */
-GPIO(LED_1_L,			PIN(C, 4), GPIO_OUT_HIGH)	/* Battery Charging LED: Amber */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
-/* Unused signals */
-GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
-
diff --git a/board/collis/led.c b/board/collis/led.c
deleted file mode 100644
index 508a5eb585..0000000000
--- a/board/collis/led.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/collis/sensors.c b/board/collis/sensors.c
deleted file mode 100644
index 24284649a7..0000000000
--- a/board/collis/sensors.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.default_range = 4, /* g */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void baseboard_sensors_init(void)
-{
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-		ccprints("LID_ACCEL is KX022");
-	} else
-		ccprints("LID_ACCEL is BMA253");
-
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE ACCEL is ICM426XX");
-	} else
-		ccprints("BASE ACCEL IS BMI160");
-
-	/* Enable interrupt for the accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/collis/vif_override.xml b/board/collis/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/collis/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/copano/battery.c b/board/copano/battery.c
deleted file mode 100644
index add2094b52..0000000000
--- a/board/copano/battery.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C433] = {
-		.fuel_gauge = {
-			.manuf_name = "AS1GVPc3KB",
-			.device_name = "C433-41",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x44,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C433;
diff --git a/board/copano/board.c b/board/copano/board.c
deleted file mode 100644
index 9a20eee45f..0000000000
--- a/board/copano/board.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config copano_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &copano_kb;
-}
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Terrador if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025015): Terrador: check USB PD reset operation */
-}
-
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-};
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration.
- */
-static void setup_mux(void)
-{
-	CPRINTS("C0 supports bb-retimer");
-	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
-}
-
-__override void board_cbi_init(void)
-{
-	/*
-	 * TODO(b/159025015): Terrador: check FW_CONFIG fields for USB DB type
-	 */
-	setup_mux();
-	/* Reassign USB_C0_RT_RST_ODL */
-	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
-	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-/******************************************************************************/
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
diff --git a/board/copano/board.h b/board/copano/board.h
deleted file mode 100644
index 1ad6a91361..0000000000
--- a/board/copano/board.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-#undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0		/* GPIO C2 is not used as PWM1 */
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-
-/* BMI160 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	15000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-#define CONFIG_USB_PD_FRS_PPC
-
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_TUSB422
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C433,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/copano/build.mk b/board/copano/build.mk
deleted file mode 100644
index 838d6a16ce..0000000000
--- a/board/copano/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/copano/ec.tasklist b/board/copano/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/copano/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/copano/gpio.inc b/board/copano/gpio.inc
deleted file mode 100644
index 3159821e94..0000000000
--- a/board/copano/gpio.inc
+++ /dev/null
@@ -1,176 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(9, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(D, 2), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C0_RT_INT_ODL,			PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,			PIN(4, 0), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-
-
-/* LED */
-GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)	/* Battery Full LED / Power LED: White */
-GPIO(LED_1_L,			PIN(C, 4), GPIO_OUT_HIGH)	/* Battery Charging LED: Amber */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
-/* Unused signals */
-GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
-
diff --git a/board/copano/led.c b/board/copano/led.c
deleted file mode 100644
index a5b535000a..0000000000
--- a/board/copano/led.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/copano/sensors.c b/board/copano/sensors.c
deleted file mode 100644
index 6a483a5671..0000000000
--- a/board/copano/sensors.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.default_range = 4, /* g */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void baseboard_sensors_init(void)
-{
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-		ccprints("LID_ACCEL is KX022");
-	} else
-		ccprints("LID_ACCEL is BMA253");
-
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE ACCEL is ICM426XX");
-	} else
-		ccprints("BASE ACCEL IS BMI160");
-
-	/* Enable interrupt for the accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/copano/vif_override.xml b/board/copano/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/copano/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/coral/battery.c b/board/coral/battery.c
deleted file mode 100644
index ebc8071c0d..0000000000
--- a/board/coral/battery.c
+++ /dev/null
@@ -1,702 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Number of writes needed to invoke battery cutoff command */
-#define SHIP_MODE_WRITES 2
-
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_LGC203,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_PANASONIC,
-	BATTERY_CELXPERT,
-	BATTERY_LGC011,
-	BATTERY_SMP011,
-	BATTERY_LGC,
-	BATTERY_BYD,
-	BATTERY_SIMPLO,
-	BATTERY_TYPE_COUNT,
-};
-
-struct ship_mode_info {
-	const uint8_t reg_addr;
-	const uint16_t reg_data[SHIP_MODE_WRITES];
-};
-
-struct fet_info {
-	const int mfgacc_support;
-	const uint8_t reg_addr;
-	const uint16_t reg_mask;
-	const uint16_t disconnect_val;
-};
-
-struct fuel_gauge_info {
-	const char *manuf_name;
-	const char *device_name;
-	const struct ship_mode_info ship_mode;
-	const struct fet_info fet;
-};
-
-struct board_batt_params {
-	const struct fuel_gauge_info fuel_gauge;
-	const struct battery_info batt_info;
-};
-
-#define DEFAULT_BATTERY_TYPE BATTERY_SANYO
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-/* Battery may delay reporting battery present */
-static int battery_report_present = 1;
-
-static int disch_on_ac;
-
-/*
- * Battery info for all Coral battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determing if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropirate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the regsister
- * address, mask, and disconnect value need to be provided.
- */
-static const struct board_batt_params info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC C203-36J Battery Information */
-	[BATTERY_LGC203] = {
-		.fuel_gauge = {
-			.manuf_name = "AS1GXXc3KB",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Celxpert Li7C3PG0 Battery Information */
-	[BATTERY_CELXPERT] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 200,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC\011 L17L3PB0 Battery Information */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 500,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP\011 L17M3PB0 Battery Information */
-	[BATTERY_SMP011] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 186,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC DELL Y07HK Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.553",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 114000, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* BYD DELL FY8XM6C Battery Information */
-	[BATTERY_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 114000, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo () Battery Information */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI3.72",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 114900, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-static inline const struct board_batt_params *board_get_batt_params(void)
-{
-	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
-}
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	char manu_name[32], device_name[32];
-	int i;
-
-	if (!battery_manufacturer_name(manu_name, sizeof(manu_name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strcasecmp(manu_name,
-				info[i].fuel_gauge.manuf_name)) {
-				if (info[i].fuel_gauge.device_name == NULL) {
-					board_battery_type = i;
-					break;
-				} else if (!battery_device_name(device_name,
-					sizeof(device_name))) {
-					if (!strcasecmp(device_name,
-					info[i].fuel_gauge.device_name)) {
-						board_battery_type = i;
-						break;
-					}
-				}
-			}
-		}
-	}
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s",
-			info[board_battery_type].fuel_gauge.manuf_name);
-	else
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return &board_get_batt_params()->batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	int cmd;
-	int data;
-
-	/* If battery type is unknown can't send ship mode command */
-	if (board_get_battery_type() == BATTERY_TYPE_COUNT)
-		return EC_RES_ERROR;
-
-	/* Ship mode command must be sent twice to take effect */
-	cmd = info[board_battery_type].fuel_gauge.ship_mode.reg_addr;
-	data = info[board_battery_type].fuel_gauge.ship_mode.reg_data[0];
-	rv = sb_write(cmd, data);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	data = info[board_battery_type].fuel_gauge.ship_mode.reg_data[1];
-	rv = sb_write(cmd, data);
-
-	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	/*
-	 * To avoid inrush current from the external charger, enable
-	 * discharge on AC till the new charger is detected and charge
-	 * detect delay has passed.
-	 */
-	if (!chg_ramp_is_detected() && curr->batt.state_of_charge > 2)
-		return 1;
-
-	return 0;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	return 0;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES;
-}
-
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/* Allow booting now that the battery has woke up */
-static void battery_now_present(void)
-{
-	CPRINTS("battery will now report present");
-	battery_report_present = 1;
-}
-DECLARE_DEFERRED(battery_now_present);
-
-/*
- * This function checks the charge/dishcarge FET status bits. Each battery type
- * supported provides the register address, mask, and disconnect value for these
- * 2 FET status bits. If the FET status matches the disconnected value, then
- * BATTERY_DISCONNECTED is returned. This function is required to handle the
- * cases when the fuel gauge is awake and will return a non-zero state of
- * charge, but is not able yet to provide power (i.e. discharge FET is not
- * active). By returning BATTERY_DISCONNECTED the AP will not be powered up
- * until either the external charger is able to provided enough power, or
- * the battery is able to provide power and thus prevent a brownout when the
- * AP is powered on by the EC.
- */
-static int battery_check_disconnect(void)
-{
-	int rv;
-	int reg;
-	uint8_t data[6];
-
-	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (board_battery_type == BATTERY_TYPE_COUNT) {
-		/* Keep trying to determine the battery type */
-		board_init_battery_type();
-		if (board_battery_type == BATTERY_TYPE_COUNT)
-			/* Still don't know, so return here */
-			return BATTERY_DISCONNECT_ERROR;
-	}
-
-	/* Read the status of charge/discharge FETs */
-	if (info[board_battery_type].fuel_gauge.fet.mfgacc_support == 1) {
-		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-		/* Get the lowest 16bits of the OperationStatus() data */
-		reg = data[2] | data[3] << 8;
-	} else
-		rv = sb_read(info[board_battery_type].fuel_gauge.fet.reg_addr,
-					&reg);
-
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	CPRINTS("Battery FET: reg 0x%04x mask 0x%04x disc 0x%04x", reg,
-		info[board_battery_type].fuel_gauge.fet.reg_mask,
-		info[board_battery_type].fuel_gauge.fet.disconnect_val);
-	reg &= info[board_battery_type].fuel_gauge.fet.reg_mask;
-	if (reg == info[board_battery_type].fuel_gauge.fet.disconnect_val)
-		return BATTERY_DISCONNECTED;
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-/*
- * Physical detection of battery.
- */
-
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-	static int battery_report_present_timer_started;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-	    (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	     battery_check_disconnect() != BATTERY_NOT_DISCONNECTED ||
-	     battery_init() == 0)) {
-		battery_report_present = 0;
-		/*
-		 * When this path is taken, the _timer_started flag must be
-		 * reset so the 'else if' path will be entered and the
-		 * battery_report_present flag can be set by the deferred
-		 * call. This handles the case of the battery being disconected
-		 * and reconnected while running or if battery_init() returns an
-		 * error due to a failed sb_read.
-		 */
-		battery_report_present_timer_started = 0;
-	}  else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
-		   !battery_report_present_timer_started) {
-		/*
-		 * Wait 1/2 second before reporting present if it was
-		 * previously reported as not present
-		 */
-		battery_report_present_timer_started = 1;
-		battery_report_present = 0;
-		hook_call_deferred(&battery_now_present_data, 500 * MSEC);
-	}
-
-	if (!battery_report_present)
-		batt_pres = BP_NO;
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
-
-int board_battery_initialized(void)
-{
-	return battery_hw_present() == batt_pres_prev;
-}
-
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-#define PARAM_LEARN_MODE	0x10001
-#define PARAM_DISCONNECT_STATE	0x10002
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	switch (param) {
-	case PARAM_LEARN_MODE:
-		*value = disch_on_ac;
-		return EC_SUCCESS;
-	case PARAM_DISCONNECT_STATE:
-		*value = battery_check_disconnect();
-		return EC_SUCCESS;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/coral/board.c b/board/coral/board.c
deleted file mode 100644
index a563071294..0000000000
--- a/board/coral/board.c
+++ /dev/null
@@ -1,1027 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coral board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/als_opt3001.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "sku.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
-
-static int sku_id;
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-#endif
-
-/*
- * enable_input_devices() is called by the tablet_mode ISR, but changes the
- * state of GPIOs, so its definition must reside after including gpio_list.
- * Use DECLARE_DEFERRED to generate enable_input_devices_data.
- */
-static void enable_input_devices(void);
-DECLARE_DEFERRED(enable_input_devices);
-
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
-void tablet_mode_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_1] = {
-		"BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_0] = {
-		"BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] =   { 4, PWM_CONFIG_DSLEEP, 100 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO,   400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   NPCX_I2C_PORT2,   400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      NPCX_I2C_PORT3,   100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST
-struct i2c_stress_test i2c_stress_tests[] = {
-/* NPCX_I2C_PORT0_0 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = NPCX_I2C_PORT0_0,
-		.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		.i2c_test = &anx74xx_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT0_1 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = NPCX_I2C_PORT0_1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.i2c_test = &ps8xxx_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT1 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_GYRO,
-		.addr_flags = BMI160_ADDR0_FLAGS,
-		.i2c_test = &bmi160_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT2 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_LID_ACCEL,
-		.addr_flags = KX022_ADDR1_FLAGS,
-		.i2c_test = &kionix_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT3 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-	{
-		.i2c_test = &battery_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-	{
-		.i2c_test = &bd9995x_i2c_stress_test_dev,
-	},
-#endif
-};
-const int i2c_test_dev_used = ARRAY_SIZE(i2c_stress_tests);
-#endif /* CONFIG_CMD_I2C_STRESS_TEST */
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BD9995X_ADDR_FLAGS,
-		.drv = &bd9995x_drv,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* 0x98 sets lower EQ of DP port (4.5db) */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-};
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX74XX)
-		return;
-
-	switch (mode) {
-	case ANX74XX_NORMAL_MODE:
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-		break;
-	case ANX74XX_STANDBY_MODE:
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset to TCPC1 (ps8751) */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-
-	/* Assert reset to TCPC0 (anx3429) */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-
-	/* TCPC1 (ps8751) requires 1ms reset down assertion */
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-
-	/* Deassert reset to TCPC1 */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	/* Disable TCPC0 power */
-	gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-
-	/*
-	 * anx3429 requires 10ms reset/power down assertion
-	 */
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
-}
-
-static void board_tcpc_init(void)
-{
-	int reg;
-	int count = 0;
-
-	/* Wait for disconnected battery to wake up */
-	while (battery_hw_present() == BP_YES &&
-	       battery_is_present() == BP_NO) {
-		usleep(100 * MSEC);
-		/* Give up waiting after 2 seconds */
-		if (++count > 20)
-			break;
-	}
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/*
-	 * TODO: Remove when Coral is updated with PS8751 A3.
-	 *
-	 * Force PS8751 A2 to wake from low power mode.
-	 * If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 *
-	 * NOTE: PS8751 A3 will wake on any I2C access.
-	 */
-	i2c_read8(NPCX_I2C_PORT0_1, 0x08, 0xA0, &reg);
-
-	/* Enable TCPC0 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable TCPC1 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-#endif
-	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_DEFAULT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && gpio_get_level(GPIO_PMIC_EN))
-		return;
-
-	/* Enable PP5000 before PP3300 due to NFC: chrome-os-partner:50807 */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-	while (!gpio_get_level(GPIO_PP5000_PG))
-		;
-
-	/*
-	 * To prevent SLP glitches, PMIC_EN (V5A_EN) should be enabled
-	 * at the same time as PP3300 (chrome-os-partner:51323).
-	 */
-	/* Enable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 1);
-	while (!gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/* Enable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 1);
-}
-
-static void board_set_tablet_mode(void)
-{
-	int tablet_mode = 0;
-
-	if (SKU_IS_CONVERTIBLE(sku_id))
-		tablet_mode = !gpio_get_level(GPIO_TABLET_MODE_L);
-
-	tablet_set_mode(tablet_mode, TABLET_TRIGGER_LID);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Ensure tablet mode is initialized according to the hardware state
-	 * so that the cached state reflects reality. */
-	board_set_tablet_mode();
-
-	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Need to read SKU ID at least once each boot */
-	sku_id = BOARD_VERSION_UNKNOWN;
-}
-/* PP3300 needs to be enabled before TCPC init hooks */
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port != 0 && port != 1)
-		panic("Invalid charge port\n");
-
-	return bd9995x_is_vbus_provided(port);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	enum bd9995x_charge_port bd9995x_port;
-	int bd9995x_port_select = 1;
-
-	switch (charge_port) {
-	case USB_PD_PORT_ANX74XX:
-	case USB_PD_PORT_PS8751:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-
-		bd9995x_port = charge_port;
-		break;
-	case CHARGE_PORT_NONE:
-		bd9995x_port_select = 0;
-		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
-
-		/*
-		 * To avoid inrush current from the external charger, enable
-		 * discharge on AC till the new charger is detected and
-		 * charge detect delay has passed.
-		 */
-		if (charge_get_percent() > 2)
-			charger_discharge_on_ac(1);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Enable charging trigger by BC1.2 detection */
-	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
-			   supplier == CHARGE_SUPPLIER_BC12_DCP ||
-			   supplier == CHARGE_SUPPLIER_BC12_SDP ||
-			   supplier == CHARGE_SUPPLIER_OTHER);
-
-	if (bd9995x_bc12_enable_charging(port, bc12_enable))
-		return;
-
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < BD9995X_BC12_MIN_VOLTAGE;
-}
-
-static void enable_input_devices(void)
-{
-	/* We need to turn on tablet mode for motion sense */
-	board_set_tablet_mode();
-
-	/* Then, we disable peripherals only when the lid reaches 360 position.
-	 * (It's probably already disabled by motion_sense_task.)
-	 * We deliberately do not enable peripherals when the lid is leaving
-	 * 360 position. Instead, we let motion_sense_task enable it once it
-	 * reaches laptop zone (180 or less). */
-	if (tablet_get_mode())
-		lid_angle_peripheral_enable(0);
-}
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	/* Enable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-
-	/* Enable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-
-	/* Disable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-	/* FIXME(dhendrix): Drive USB_PD_RST_ODL low to prevent
-	   leakage? (see comment in schematic) */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* FIXME(dhendrix): Add CHIPSET_RESUME and CHIPSET_SUSPEND
-   hooks to enable/disable sensors? */
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * FIXME(dhendrix): Weak symbol hack until we can get a better solution for
- * both Amenia and Coral.
- */
-void chipset_do_shutdown(void)
-{
-	/* Disable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 0);
-
-	/*Disable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 0);
-	while (gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/*Disable 5V rail */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	while (gpio_get_level(GPIO_PP5000_PG))
-		;
-}
-
-void board_hibernate_late(void)
-{
-	int i;
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
-
-		/*
-		 * BD99956 handles charge input automatically. We'll disable
-		 * charge output in hibernate. Charger will assert ACOK_OD
-		 * when VBUS or VCC are plugged in.
-		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-	};
-
-	/* Change GPIOs' state in hibernate for better power consumption */
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
-
-	/*
-	 * Calling gpio_config_module sets disabled alternate function pins to
-	 * GPIO_INPUT.  But to prevent keypresses causing leakage currents
-	 * while hibernating we want to enable GPIO_PULL_UP as well.
-	 */
-	gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x1, 0x7F, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP);
-	/* KBD_KSO2 needs to have a pull-down enabled instead of pull-up */
-	gpio_set_flags_by_mask(0x1, 0x80, GPIO_INPUT | GPIO_PULL_DOWN);
-}
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* FIXME(dhendrix): Copied from Amenia, probably need to tweak for Coral */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_LID_ACCEL,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-
-	/* Enable both the VBUS & VCC ports before entering PG3 */
-	bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
-
-	/* Turn BGATE OFF for saving the power */
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_MAX);
-}
-
-static void board_set_motion_sensor_count(uint8_t sku_id)
-{
-	/*
-	 * There are two possible sensor configurations. Clamshell device will
-	 * not have any of the motion sensors populated, while convertible
-	 * devices have the BMI160 Accel/Gryo and Kionx KX022 lid acceleration
-	 * sensor. If a new SKU id is used that is not in the table, then the
-	 * number of motion sensors will remain as ARRAY_SIZE(motion_sensors).
-	 */
-	motion_sensor_count = SKU_IS_CONVERTIBLE(sku_id) ?
-		ARRAY_SIZE(motion_sensors) : 0;
-
-	CPRINTS("Motion Sensor Count = %d", motion_sensor_count);
-}
-
-struct {
-	enum coral_board_version version;
-	int thresh_mv;
-} const coral_board_versions[] = {
-	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
-	/* R1 = 51.1 kOhm */
-	{ BOARD_VERSION_1, 200 },  /* 124 mV, 2.0 Kohm */
-	{ BOARD_VERSION_2, 366 },  /* 278 mV, 4.7 Kohm */
-	{ BOARD_VERSION_3, 550 },  /* 456 mV, 8.2  Kohm */
-	{ BOARD_VERSION_4, 752 },  /* 644 mV, 12.4 Kohm */
-	{ BOARD_VERSION_5, 927},   /* 860 mV, 18.0 Kohm */
-	{ BOARD_VERSION_6, 1073 }, /* 993 mV, 22.0 Kohm */
-	{ BOARD_VERSION_7, 1235 }, /* 1152 mV, 27.4 Kohm */
-	{ BOARD_VERSION_8, 1386 }, /* 1318 mV, 34.0 Kohm */
-	{ BOARD_VERSION_9, 1552 }, /* 1453 mV, 40.2 Kohm */
-	/* R1 = 10.0 kOhm */
-	{ BOARD_VERSION_10, 1739 }, /* 1650 mV, 10.0 Kohm */
-	{ BOARD_VERSION_11, 1976 }, /* 1827 mV, 12.4 Kohm */
-	{ BOARD_VERSION_12, 2197 }, /* 2121 mV, 18.0 Kohm */
-	{ BOARD_VERSION_13, 2344 }, /* 2269 mV, 22.0 Kohm */
-	{ BOARD_VERSION_14, 2484 }, /* 2418 mV, 27.4 Kohm */
-	{ BOARD_VERSION_15, 2636 }, /* 2550 mV, 34.0 Kohm */
-	{ BOARD_VERSION_16, 2823 }, /* 2721 mV, 47.0 Kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(coral_board_versions) == BOARD_VERSION_COUNT);
-
-static int board_read_version(enum adc_channel chan)
-{
-	int mv;
-	int i;
-
-	/* ID/SKU enable is active high */
-	gpio_set_flags(GPIO_EC_BRD_ID_EN, GPIO_OUT_HIGH);
-	/* Wait to allow cap charge */
-	msleep(1);
-	mv = adc_read_channel(chan);
-	CPRINTS("ID/SKU ADC %d = %d mV", chan, mv);
-	/* Disable ID/SKU circuit */
-	gpio_set_flags(GPIO_EC_BRD_ID_EN, GPIO_INPUT);
-
-	if (mv == ADC_READ_ERROR)
-		return BOARD_VERSION_UNKNOWN;
-
-	for (i = 0; i < BOARD_VERSION_COUNT; i++)
-		if (mv < coral_board_versions[i].thresh_mv)
-			return coral_board_versions[i].version;
-
-	return BOARD_VERSION_UNKNOWN;
-}
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	version = board_read_version(ADC_BOARD_ID);
-
-	CPRINTS("Board version: %d", version);
-	return version;
-}
-
-static void sku_id_init(void)
-{
-	int sku_id_lower;
-	int sku_id_higher;
-
-	if (sku_id == BOARD_VERSION_UNKNOWN) {
-		sku_id_lower = board_read_version(ADC_BOARD_SKU_0);
-		sku_id_higher = board_read_version(ADC_BOARD_SKU_1);
-		if ((sku_id_lower != BOARD_VERSION_UNKNOWN) &&
-		    (sku_id_higher != BOARD_VERSION_UNKNOWN))
-			sku_id = (sku_id_higher << 4) | sku_id_lower;
-		CPRINTS("SKU ID: %d", sku_id);
-		/* Use sku_id to set motion sensor count */
-		board_set_motion_sensor_count(sku_id);
-
-		if (0 == SKU_IS_CONVERTIBLE(sku_id)) {
-			CPRINTS("Disable tablet mode interrupt");
-			gpio_disable_interrupt(GPIO_TABLET_MODE_L);
-			/* Enfore device in laptop mode */
-			tablet_set_mode(0, TABLET_TRIGGER_LID);
-		}
-	}
-}
-/* This can't run until after the ADC module has been initialized */
-DECLARE_HOOK(HOOK_INIT, sku_id_init, HOOK_PRIO_INIT_ADC + 1);
-
-static void print_form_factor_list(int low, int high)
-{
-	int id;
-	int count = 0;
-
-	if (high > 255)
-		high = 255;
-	for (id = low; id <= high; id++) {
-		ccprintf("SKU ID %03d: %s\n", id, SKU_IS_CONVERTIBLE(id) ?
-			 "Convertible" : "Clamshell");
-		/* Don't print too many lines at once */
-		if (!(++count % 5))
-			msleep(20);
-	}
-}
-
-static int command_sku(int argc, char **argv)
-{
-	enum adc_channel chan;
-
-	if (argc < 2) {
-		system_get_sku_id();
-		ccprintf("SKU ID: %d\n", sku_id);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "form")) {
-		if (argc >= 4) {
-			char *e;
-			int low, high;
-
-			low = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			high = strtoi(argv[3], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM2;
-			print_form_factor_list(low, high);
-			return EC_SUCCESS;
-		} else {
-			return EC_ERROR_PARAM_COUNT;
-		}
-	}
-
-	if (!strcasecmp(argv[1], "board"))
-		chan = ADC_BOARD_ID;
-	else if (!strcasecmp(argv[1], "line0"))
-		chan = ADC_BOARD_SKU_0;
-	else if (!strcasecmp(argv[1], "line1"))
-		chan = ADC_BOARD_SKU_1;
-	else
-		return EC_ERROR_PARAM1;
-
-	ccprintf("sku: %s = %d, adc %d\n", argv[1], board_read_version(chan),
-		 chan);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sku, command_sku,
-			"<board|line0|line1|form [low high]>",
-			"Get board id, sku, form factor");
-
-__override uint32_t board_get_sku_id(void)
-{
-	if (sku_id == BOARD_VERSION_UNKNOWN)
-		sku_id_init();
-
-	return (uint32_t)sku_id;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	uint32_t sku = system_get_sku_id();
-
-	/*
-	 * We always compile in backlight support for coral, but only some
-	 * models come with the hardware. Therefore, check if the current
-	 * device is one of them and return the default value - with backlight
-	 * here.
-	 */
-	if (sku == 8 || sku == 11)
-		return flags0;
-
-	// Report that there is no keyboard backlight
-	flags0 &= ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB);
-
-	return flags0;
-}
diff --git a/board/coral/board.h b/board/coral/board.h
deleted file mode 100644
index 24b0ecf86e..0000000000
--- a/board/coral/board.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coral board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages except Events:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_EVENTS))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-#define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
-
-#define CONFIG_CHARGER_PSYS_READ
-#define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
-
-#define CONFIG_CMD_I2C_STRESS_TEST
-#define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-#define CONFIG_CMD_I2C_STRESS_TEST_ALS
-#define CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-#define CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-#define CONFIG_CMD_I2C_STRESS_TEST_TCPC
-
-/* Port80 */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGE_STATE_DEBUG
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BD9995X
-#define CONFIG_CHARGER_BD9995X_CHGEN
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_USB_CHARGER
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
-#define GPIO_USB_CTL1 GPIO_EN_PP5000
-
-#define CONFIG_TABLET_MODE
-
-/* USB PD config */
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
-#define CONFIG_USB_PD_TCPM_ANX3429
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_CHIPSET_APOLLOLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_FPU
-/* Region sizes are not a power of 2 so we can't use MPU */
-#undef  CONFIG_MPU
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_DPTF
-#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
-#define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-
-/*
- * During shutdown sequence TPS65094x PMIC turns off the sensor rails
- * asynchronously to the EC. If we access the sensors when the sensor power
- * rails are off we get I2C errors. To avoid this issue, defer switching
- * the sensors rate if in S3. By the time deferred function is serviced if
- * the chipset is in S5 we can back out from switching the sensor rate.
- *
- * Time taken by V1P8U rail to go down from S3 is 30ms to 60ms hence defer
- * the sensor switching after 60ms.
- */
-#undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
-#define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60)
-
-#define CONFIG_FLASH_SIZE_BYTES 524288
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-/* FIXME(dhendrix): these pins are just normal GPIOs on Coral. Do we need
- * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
-/* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_MAG_CALIBRATE
-#define CONFIG_ACCEL_KX022
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
-	ADC_BOARD_SKU_1,		/* ADC3 */
-	ADC_BOARD_SKU_0,		/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY = 0,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-#define CONFIG_HOSTCMD_SKUID
-enum coral_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_1,
-	BOARD_VERSION_2,
-	BOARD_VERSION_3,
-	BOARD_VERSION_4,
-	BOARD_VERSION_5,
-	BOARD_VERSION_6,
-	BOARD_VERSION_7,
-	BOARD_VERSION_8,
-	BOARD_VERSION_9,
-	BOARD_VERSION_10,
-	BOARD_VERSION_11,
-	BOARD_VERSION_12,
-	BOARD_VERSION_13,
-	BOARD_VERSION_14,
-	BOARD_VERSION_15,
-	BOARD_VERSION_16,
-	BOARD_VERSION_COUNT,
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/* FIXME(dhendrix): verify all of the below PD_* numbers */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-
-int board_get_version(void);
-
-void board_set_tcpc_power_mode(int port, int mode);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/coral/build.mk b/board/coral/build.mk
deleted file mode 100644
index 728d027803..0000000000
--- a/board/coral/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/coral/ec.tasklist b/board/coral/ec.tasklist
deleted file mode 100644
index eeebc0cc59..0000000000
--- a/board/coral/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc
deleted file mode 100644
index 8e52eeeed2..0000000000
--- a/board/coral/gpio.inc
+++ /dev/null
@@ -1,167 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(CHARGER_INT_L,		PIN(3, 3), GPIO_INT_FALLING, bd9995x_vbus_interrupt)		/* CHARGER_EC_INT_ODL from BD99956 */
-/*
- * TODO: The pull ups for Parade TCPC interrupt line can be removed in versions
- * of board following EVT in which daughter card (which has an external pull up)
- * will always be inserted.
- */
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING, tcpc_alert_event)			/* from Analogix TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)	/* from Parade TCPC */
-
-GPIO_INT(USB_C0_CABLE_DET,	PIN(C, 5), GPIO_INT_RISING, anx74xx_cable_det_interrupt)	/* CABLE_DET from ANX3429 */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt)				/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,		PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(6, 0), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,		PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_PWROK_OD */
-
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH, extpower_interrupt)			/* ACOK_OD from BD99956 */
-/* TODO: We might remove external pull-up for POWER_BUTTON_L in EVT */
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH, power_button_interrupt)		/* MECH_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,		PIN(6, 7), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Tablet switch is active-low. L: lid is attached (360 position) H: detached */
-GPIO_INT(TABLET_MODE_L,		PIN(3, 6), GPIO_INT_BOTH, tablet_mode_interrupt)
-
-GPIO_INT(WP_L,			PIN(4, 0), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt)	/* EC_WP_ODL */
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(9, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-	 bmi160_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(C, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* I2C GPIOs will be set to alt. function later. */
-GPIO(EC_I2C_GYRO_SDA,		PIN(8, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_GYRO_SCL,		PIN(9, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(9, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(9, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_PD_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,	PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(D, 1), GPIO_INPUT)
-
-/*
- * LPC:
- * Pins 46, 47, 51, 52, 53, 54, 55, default to LPC mode.
- * Pin 56 (CLKRUN#) defaults to GPIO mode.
- * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
- * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
- *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option.
- */
-
-GPIO(PCH_SMI_L,			PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
-GPIO(PCH_SCI_L,			PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SCI_ODL */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,              PIN(7, 5), GPIO_INPUT)				/* SLP_S0_L */
-#endif
-
-/* Enable for board and SKU ID ADCs */
-GPIO(EC_BRD_ID_EN,		PIN(3, 5), GPIO_INPUT)
-
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)			/* EC_ENTERING_RW */
-
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)
-GPIO(EC_BATT_PRES_L,		PIN(3, 4), GPIO_INPUT)
-GPIO(PMIC_EN,			PIN(8, 5), GPIO_OUT_LOW)
-GPIO(EN_PP3300,			PIN(C, 2), GPIO_OUT_LOW)
-GPIO(PP3300_PG,			PIN(6, 2), GPIO_INPUT)
-GPIO(EN_PP5000,			PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PP5000_PG,			PIN(7, 1), GPIO_INPUT)
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 2), GPIO_ODR_LOW)
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,		PIN(A, 1), GPIO_OUT_LOW)
-GPIO(PCH_SYS_PWROK,		PIN(E, 7), GPIO_OUT_LOW)		/* EC_PCH_PWROK */
-GPIO(ENABLE_BACKLIGHT,		PIN(9, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-
-GPIO(WIRELESS_GPIO_WLAN_POWER,	PIN(6, 6), GPIO_ODR_HIGH)		/* EN_PP3300_WLAN_ODL */
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,		PIN(A, 3), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-GPIO(PCH_PWRBTN_L,		PIN(0, 1), GPIO_ODR_HIGH)		/* EC_PCH_PWR_BTN_ODL */
-GPIO(PCH_WAKE_L,		PIN(8, 1), GPIO_ODR_HIGH)		/* EC_PCH_WAKE_ODL */
-GPIO(USB_C0_HPD_1P8_ODL,	PIN(9, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(USB_C1_HPD_1P8_ODL,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-
-GPIO(USB2_OTG_VBUSSENSE,	PIN(9, 5), GPIO_OUTPUT)
-
-/* EC_PCH_RTCRST is a sledgehammer for resetting SoC state and should rarely
- * be used. Set as input for now, we'll set it as an output when we want to use
- * it. Has external pull-down resistor. */
-GPIO(EC_PCH_RTCRST,		PIN(B, 7), GPIO_INPUT)
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)		/* SYS_RST_ODL */
-
-/* FIXME: What, if anything, to do about EC_RST_ODL on VCC1_RST#? */
-
-GPIO(CHARGER_RST_ODL,		PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(USB_A_CHARGE_EN_L,		PIN(8, 4), GPIO_OUT_LOW)
-GPIO(USB1_ENABLE,		PIN(0, 0), GPIO_OUT_HIGH)
-GPIO(EN_USB_TCPC_PWR,		PIN(C, 3), GPIO_OUT_LOW)
-
-GPIO(USB_C0_PD_RST_L,		PIN(0, 3), GPIO_OUT_LOW)		/* USB_C0_PD_RST_L */
-GPIO(USB_C1_PD_RST_ODL,		PIN(7, 4), GPIO_ODR_HIGH)
-
-/*
- * Configure as input to enable @ 1.5A, output-low to turn off, or output-high
- * to enable @ 3A.
- */
-GPIO(USB_C0_5V_EN,		PIN(D, 3), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C0_5V_OUT, Enable C0 */
-GPIO(USB_C1_5V_EN,		PIN(D, 2), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C1_5V_OUT, Enable C1 */
-
-GPIO(BAT_LED_BLUE,		PIN(8, 0), GPIO_OUT_HIGH)
-GPIO(BAT_LED_AMBER,		PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(POWER_LED,			PIN(0, 2), GPIO_OUT_HIGH)
-
-
-/*
- * Alternate function pins
- */
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0xfc), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(0, 0xe0), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(1, 0x7f), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2,			 PIN(1, 7), GPIO_KB_OUTPUT_COL2)
-
-/* Board and SKU ID ADC inputs (GPIO 41, 42, 43) */
-ALTERNATE(PIN_MASK(4, 0x02), 1, MODULE_ADC, 0)
-ALTERNATE(PIN_MASK(4, 0x04), 1, MODULE_ADC, 0)
-ALTERNATE(PIN_MASK(4, 0x08), 1, MODULE_ADC, 0)
-
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)	/* GPIO87 for EC_I2C_GYRO_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)	/* GPIO90 for EC_I2C_GYRO_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)	/* GPIO92-91 for EC_I2C_SENSOR_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)	/* GPIOB5-B4 for EC_I2C_USB_C0_PD_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)	/* GPOPB3-B2 for EC_I2C_USB_C1_PD_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)	/* GPIOD1-D0 for EC_I2C_POWER_SDA/SCL */
-
-ALTERNATE(PIN(B, 6), 3, MODULE_PWM, 0)		/* PWM KB Backlight */
-
-/* FIXME: Make UART RX an interrupt? */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)	/* UART from EC to Servo */
diff --git a/board/coral/led.c b/board/coral/led.c
deleted file mode 100644
index 2a1e39946c..0000000000
--- a/board/coral/led.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Coral
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-#define LED_INDEFINITE -1
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_CHARGE_LEVEL_1_DEFAULT 100
-#define LED_CHARGE_LEVEL_1_ROBO 5
-#define LED_POWER_BLINK_ON_MSEC 3000
-#define LED_POWER_BLINK_OFF_MSEC 600
-#define LED_POWER_ON_TICKS (LED_POWER_BLINK_ON_MSEC / HOOK_TICK_INTERVAL_MS)
-#define LED_POWER_OFF_TICKS (LED_POWER_BLINK_OFF_MSEC / HOOK_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-#define GPIO_LED_COLOR_1 GPIO_BAT_LED_AMBER
-#define GPIO_LED_COLOR_2 GPIO_BAT_LED_BLUE
-#define GPIO_LED_COLOR_3 GPIO_POW_LED
-
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
-
-enum led_color {
-	LED_OFF,
-	LED_COLOR_1,
-	LED_COLOR_2,
-	LED_COLOR_BOTH,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_states {
-	STATE_CHARGING_LVL_1,
-	STATE_CHARGING_LVL_2,
-	STATE_CHARGING_LVL_3,
-	STATE_DISCHARGE_S0,
-	STATE_DISCHARGE_S3,
-	STATE_DISCHARGE_S5,
-	STATE_BATTERY_ERROR,
-	STATE_FACTORY_TEST,
-	LED_NUM_STATES
-};
-
-struct led_descriptor {
-	int8_t color;
-	int8_t time;
-};
-
-struct led_info {
-	enum led_states state;
-	uint8_t charge_lvl_1;
-	const struct led_descriptor (*state_table)[LED_NUM_PHASES];
-	void (*update_power)(void);
-};
-
-/*
- * LED state tables describe the desired LED behavior for a each possible
- * state. The LED state is based on both chip power state and the battery charge
- * level. The first parameter is the color and the 2nd parameter is the time in
- * ticks, where each tick is 200 msec. If the time parameter is set to -1, that
- * means it is a non-blinking pattern.
- */
-
-/* COLOR_1 = Amber, COLOR_2 = Blue */
-static const struct led_descriptor led_default_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC }, {LED_OFF, 3 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
-};
-
-/* COLOR_1 = Green, COLOR_2 = Red */
-static const struct led_descriptor led_robo_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_BOTH, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_2, 2 * LED_ONE_SEC}, {LED_COLOR_1, 2 * LED_ONE_SEC} },
-};
-
-static const struct led_descriptor led_nasher_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
-};
-
-static struct led_info led;
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_LED_COLOR_1, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_COLOR_2, LED_OFF_LVL);
-		break;
-	case LED_COLOR_1:
-		gpio_set_level(GPIO_LED_COLOR_1, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_COLOR_2, LED_OFF_LVL);
-		break;
-	case LED_COLOR_2:
-		gpio_set_level(GPIO_LED_COLOR_1, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_COLOR_2, LED_ON_LVL);
-		break;
-	case LED_COLOR_BOTH:
-		gpio_set_level(GPIO_LED_COLOR_1, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_COLOR_2, LED_ON_LVL);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static void led_set_color_power(int level)
-{
-	gpio_set_level(GPIO_POWER_LED, level);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(LED_COLOR_2);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(LED_COLOR_1);
-	else if (brightness[EC_LED_COLOR_RED] != 0)
-		led_set_color_battery(LED_COLOR_2);
-	else if (brightness[EC_LED_COLOR_GREEN] != 0)
-		led_set_color_battery(LED_COLOR_1);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static enum led_states led_get_state(void)
-{
-	int  charge_lvl;
-	enum led_states new_state = LED_NUM_STATES;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Get percent charge */
-		charge_lvl = charge_get_percent();
-		/* Determine which charge state to use */
-		new_state = charge_lvl <= led.charge_lvl_1 ?
-			STATE_CHARGING_LVL_1 : STATE_CHARGING_LVL_2;
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			new_state = STATE_CHARGING_LVL_3;
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			new_state = STATE_DISCHARGE_S0;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_DISCHARGE_S3;
-		else
-			new_state = STATE_DISCHARGE_S5;
-		break;
-	case PWR_STATE_ERROR:
-		new_state = STATE_BATTERY_ERROR;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		new_state = STATE_CHARGING_LVL_3;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	return new_state;
-}
-
-static void led_update_battery(void)
-{
-	static int ticks;
-	int phase;
-	enum led_states desired_state = led_get_state();
-
-	/* Get updated state based on power state and charge level */
-	if (desired_state < LED_NUM_STATES && desired_state != led.state) {
-		/* State is changing */
-		led.state = desired_state;
-		/* Reset ticks counter when state changes */
-		ticks = 0;
-	}
-
-	/*
-	 * Determine the which phase of the state table to use. Assume it's
-	 * phase 0. If the time values for both phases of the current state are
-	 * not -1, then this state uses some blinking pattern. The phase is then
-	 * determined by taking the modulo of ticks by the blinking pattern
-	 * period.
-	 */
-	phase = 0;
-	if ((led.state_table[led.state][LED_PHASE_0].time != LED_INDEFINITE) &&
-	    (led.state_table[led.state][LED_PHASE_1].time != LED_INDEFINITE)) {
-		int period;
-
-		period = led.state_table[led.state][LED_PHASE_0].time +
-			led.state_table[led.state][LED_PHASE_1].time;
-		if (period)
-			phase = ticks % period <
-				led.state_table[led.state][LED_PHASE_0].time ?
-				0 : 1;
-	}
-
-	/* Set the color for the given state and phase */
-	led_set_color_battery(led.state_table[led.state][phase].color);
-	ticks++;
-}
-
-static void led_robo_update_power(void)
-{
-	int level;
-	static int ticks;
-
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* In S0 power LED is always on */
-		level = LED_ON_LVL;
-		ticks = 0;
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		   led.state <= STATE_CHARGING_LVL_3) {
-		int period;
-
-		/*
-		 * If in suspend/standby and the device is charging, then the
-		 * power LED is off for 600 msec, on for 3 seconds.
-		 */
-		period = LED_POWER_ON_TICKS + LED_POWER_OFF_TICKS;
-		level = ticks % period < LED_POWER_OFF_TICKS ?
-			LED_OFF_LVL : LED_ON_LVL;
-		ticks++;
-	} else {
-		level = LED_OFF_LVL;
-		ticks = 0;
-	}
-
-	led_set_color_power(level);
-}
-
-/* Called by hook task every hook tick (200 msec) */
-static void led_update(void)
-{
-	/* Update battery LED */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		led_update_battery();
-		if (led.update_power != NULL)
-			(*led.update_power)();
-	}
-}
-DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	int sku = system_get_sku_id();
-
-	if ((sku >= 70 && sku <= 79) || (sku >= 124 && sku <= 125) ||
-	    (sku >= 144 && sku <= 145)) {
-		led.charge_lvl_1 = LED_CHARGE_LEVEL_1_ROBO;
-		led.state_table = led_robo_state_table;
-		led.update_power = led_robo_update_power;
-	} else if (sku >= 160 && sku <= 166) {
-		led.charge_lvl_1 = LED_CHARGE_LEVEL_1_DEFAULT;
-		led.state_table = led_nasher_state_table;
-		led.update_power = NULL;
-	} else {
-		led.charge_lvl_1 = LED_CHARGE_LEVEL_1_DEFAULT;
-		led.state_table = led_default_state_table;
-		led.update_power = NULL;
-	}
-	led_set_color_battery(LED_OFF);
-}
-/* Make sure this comes after SKU ID hook */
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT + 2);
diff --git a/board/coral/sku.h b/board/coral/sku.h
deleted file mode 100644
index 4588932377..0000000000
--- a/board/coral/sku.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Coral SKU ID Table */
-
-#ifndef __CROS_EC_SKU_H
-#define __CROS_EC_SKU_H
-
-#define SKU_CONVERTIBLE(id) (1 << ((id) & 0x7))
-
-/*
- * There are 256 possible SKUs for Coral. This table is used to map a given SKU
- * ID to its form factor, which is then used to determine number of motion
- * sensors. A bit value of 0 is for clamshell and a bit value of 1 indicates a
- * convertible device. The assumption is all devices are defined as clamshells
- * unless SKU_CONVERTIBLE(id) is spelled out in the initialization.
- */
-static const uint8_t form_factor[32] = {
-	/* SKU 0 - 7 */
-	SKU_CONVERTIBLE(4) | SKU_CONVERTIBLE(5),
-	/* SKU 8 - 15 */
-	SKU_CONVERTIBLE(8) | SKU_CONVERTIBLE(9) | SKU_CONVERTIBLE(10) |
-	SKU_CONVERTIBLE(11),
-	/* SKU 16 - 23 */
-	0x00,
-	/* SKU 24 - 31 */
-	0x00,
-	/* SKU 32 - 39 */
-	0x00,
-	/* SKU 40 - 47 */
-	0x00,
-	/* SKU 48 - 55 */
-	0x00,
-	/* SKU 56 - 63 */
-	0x00,
-	/* SKU 64 - 71 */
-	SKU_CONVERTIBLE(71),
-	/* SKU 72 - 79 */
-	0x00,
-	/* SKU 80 - 87 */
-	0x00,
-	/* SKU 88 - 95 */
-	0x00,
-	/* SKU 96 - 103 */
-	0x00,
-	/* SKU 104 - 111 */
-	0x00,
-	/* SKU 112 - 119 */
-	0x00,
-	/* SKU 120 - 127 */
-	0x00,
-	/* SKU 128 - 135 */
-	0x00,
-	/* SKU 136 - 143 */
-	0x00,
-	/* SKU 144 - 151 */
-	0x00,
-	/* SKU 152 - 159 */
-	0x00,
-	/* SKU 160 - 167 */
-	SKU_CONVERTIBLE(163) | SKU_CONVERTIBLE(164) | SKU_CONVERTIBLE(165) |
-	SKU_CONVERTIBLE(166),
-	/* SKU 168 - 175 */
-	0x00,
-	/* SKU 176 - 183 */
-	0x00,
-	/* SKU 184 - 191 */
-	0x00,
-	/* SKU 192 - 199 */
-	0x00,
-	/* SKU 200 - 207 */
-	0x00,
-	/* SKU 208 - 215 */
-	0x00,
-	/* SKU 216 - 223 */
-	0x00,
-	/* SKU 224 - 231 */
-	0x00,
-	/* SKU 232 - 239 */
-	0x00,
-	/* SKU 240 - 247 */
-	0x00,
-	/* SKU 248 - 255 */
-	0x00,
-};
-
-#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id) & 0x7)) & 1)
-
-#endif /* __CROS_EC_SKU_H */
diff --git a/board/coral/usb_pd_policy.c b/board/coral/usb_pd_policy.c
deleted file mode 100644
index e071f6ae2a..0000000000
--- a/board/coral/usb_pd_policy.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
-	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
-
-	/*
-	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-	 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-	 * setting a minimum OCP current of 3186 mA.
-	 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put a 33k
-	 * resistor on ILIM, setting a minimum OCP current of 1505 mA.
-	 */
-	gpio_set_level(gpio, vbus_en[port]);
-	gpio_set_flags(gpio, flags);
-}
-
-void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Ensure we're not charging from this port */
-	bd9995x_select_input_port(port, 0);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
diff --git a/board/coral/vif_override.xml b/board/coral/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/coral/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/corori/battery.c b/board/corori/battery.c
deleted file mode 100644
index 405a69751a..0000000000
--- a/board/corori/battery.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "gpio.h"
-#include "util.h"
-
-/*
- * Battery info for lalala battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-		/* C21N2018 Battery Information
-		 * TODO(b:196506846):Need to be verified on the Proto
-		 */
-	 [BATTERY_C21N2018] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXXD3KA",
-			.device_name = "C110160",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7890,
-			.voltage_min            = 6000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C21N2018;
diff --git a/board/corori/board.c b/board/corori/board.c
deleted file mode 100644
index 323a5a8d71..0000000000
--- a/board/corori/board.c
+++ /dev/null
@@ -1,488 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config lalala_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &lalala_keybd;
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	set_5v_gpio(!!enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize THERMAL */
-	setup_thermal();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-static void board_extpower(void)
-{
-	int extpower_present;
-
-	if (pd_is_connected(0))
-		extpower_present = extpower_is_present();
-	else
-		extpower_present = 0;
-
-	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-
-#ifdef HAS_TASK_MOTIONSENSE
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
-#endif
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
-#endif
-};
diff --git a/board/corori/board.h b/board/corori/board.h
deleted file mode 100644
index 33370ecd27..0000000000
--- a/board/corori/board.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KEEBY_EC_NPCX797FC
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* Keyboard */
-
-#define CONFIG_KEYBOARD_KEYPAD
-
-/* LED defines */
-#define CONFIG_LED_COMMON
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
-#define GPIO_BAT_LED_AMBER GPIO_LED_Y_ODL
-#define GPIO_PWR_LED_WHITE GPIO_LED_W_ODL
-
-
-/* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 1
-
-/******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_C21N2018,
-	BATTERY_TYPE_COUNT,
-};
-
-int board_is_sourcing_vbus(int port);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/corori/build.mk b/board/corori/build.mk
deleted file mode 100644
index b012d8d502..0000000000
--- a/board/corori/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=keeby
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/corori/cbi_ssfc.c b/board/corori/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/corori/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/corori/cbi_ssfc.h b/board/corori/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/corori/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/corori/ec.tasklist b/board/corori/ec.tasklist
deleted file mode 100644
index 0025c2985b..0000000000
--- a/board/corori/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/corori/gpio.inc b/board/corori/gpio.inc
deleted file mode 100644
index 5f6f119648..0000000000
--- a/board/corori/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Button interrupts */
-GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
-
-/* Extra Sub-board I/O pins */
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_W_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* POWER LED */
-GPIO(LED_Y_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* BATTERY LED */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A0 5V Charging */
-
-GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
-/*
- * Lalala doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/corori/led.c b/board/corori/led.c
deleted file mode 100644
index 96a43caa76..0000000000
--- a/board/corori/led.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for lalala
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
-
-struct led_descriptor {
-	enum ec_led_colors color;
-	uint8_t time;
-};
-
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
-
-enum led_states {
-	STATE_CHARGING,
-	STATE_CHARGING_FULL_CHARGE,
-	STATE_DISCHARGE_S0,
-	STATE_DISCHARGE_S0_BAT_LOW,
-	STATE_BATTERY_S0_ERROR,
-	STATE_BATTERY_S3_BLINK,
-	STATE_BATTERY_S5_OFF,
-	STATE_FACTORY_TEST,
-	LED_NUM_STATES
-};
-
-static const struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[STATE_BATTERY_S0_ERROR]     = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_BATTERY_S3_BLINK]     = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_BATTERY_S5_OFF]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-
-static int led_get_charge_percent(void)
-{
-	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_ON_LVL);
-		gpio_set_level(GPIO_PWR_LED_WHITE, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_WHITE, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_AMBER, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_WHITE, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
-
-/* Custom led on off states control */
-static enum led_states led_get_state(void)
-{
-	enum led_states new_state = LED_NUM_STATES;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		new_state = STATE_CHARGING;
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			new_state = STATE_CHARGING_FULL_CHARGE;
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			new_state = (led_get_charge_percent() < 10) ?
-				STATE_DISCHARGE_S0_BAT_LOW : STATE_DISCHARGE_S0;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_BATTERY_S3_BLINK;
-		else
-			new_state = STATE_BATTERY_S5_OFF;
-		break;
-	case PWR_STATE_ERROR:
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			new_state = STATE_BATTERY_S0_ERROR;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_BATTERY_S3_BLINK;
-		else
-			new_state = STATE_BATTERY_S5_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	return new_state;
-}
-
-static void led_update_battery(void)
-{
-	static uint8_t ticks, period;
-	static int led_state = LED_NUM_STATES;
-	int phase;
-	enum led_states desired_state = led_get_state();
-
-	/*
-	 * We always need to check the current state since the value could
-	 * have been manually overwritten. If we're in a new valid state,
-	 * update our ticks and period info. If our new state isn't defined,
-	 * continue using the previous one.
-	 */
-	if (desired_state != led_state && desired_state < LED_NUM_STATES) {
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		led_set_color_battery(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_battery(led_bat_state_table[led_state][phase].color);
-}
-
-static void led_init(void)
-{
-	/* If battery LED is enabled, set it to "off" to start with */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_color_battery(LED_OFF);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every hook tick (200 msec) */
-static void led_update(void)
-{
-	/*
-	 * If battery LED is enabled, set its state based on our power and
-	 * charge
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_update_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/board/corori/usb_pd_policy.c b/board/corori/usb_pd_policy.c
deleted file mode 100644
index fd9018a3f0..0000000000
--- a/board/corori/usb_pd_policy.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/corori/vif_override.xml b/board/corori/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/corori/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/cozmo b/board/cozmo
deleted file mode 120000
index 9ed6f26875..0000000000
--- a/board/cozmo
+++ /dev/null
@@ -1 +0,0 @@
-icarus
\ No newline at end of file
diff --git a/board/cret/battery.c b/board/cret/battery.c
deleted file mode 100644
index f60b610a6a..0000000000
--- a/board/cret/battery.c
+++ /dev/null
@@ -1,634 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all waddledoo battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* BYD Battery Information */
-	[BATTERY_BYD_1VX1H] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL 1VX1H",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD Battery Information */
-	[BATTERY_BYD_YT39X] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL YT39X",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD Battery Information */
-	[BATTERY_BYD_X0Y5M] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL X0Y5M",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x043,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC_FDRHM] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.65",
-			.device_name = "DELL FDRHM",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11460,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC_8GHCX] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.65",
-			.device_name = "DELL 8GHCX",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11460,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-
-	/* SWD-ATL Battery Information */
-	[BATTERY_SWD_ATL_WJPC4] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.618",
-			.device_name = "DELL WJPC4",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-ATL Battery Information */
-	[BATTERY_SWD_ATL_CTGKT] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.618",
-			.device_name = "DELL CTGKT",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-COS Battery Information */
-	[BATTERY_SWD_COS_WJPC4] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-COS3.634",
-			.device_name = "DELL WJPC4",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-COS Battery Information */
-	[BATTERY_SWD_COS_CTGKT] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-COS3.634",
-			.device_name = "DELL CTGKT",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_VM732] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL VM732",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_26JGK] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL 26JGK",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_RF9H3] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL RF9H3",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x43,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_VM732] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL VM732",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_26JGK] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL 26JGK",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_RF9H3] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL RF9H3",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x43,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD 16DPHYMD Battery Information */
-	[BATTERY_BYD16] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD-BYD3.685",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC3] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.553",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO Battery Information */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI3.72",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO-LISHEN 7T0D3YMD Battery Information */
-	[BATTERY_SIMPLO_LS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LS3.66",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
diff --git a/board/cret/board.c b/board/cret/board.c
deleted file mode 100644
index 34091c0518..0000000000
--- a/board/cret/board.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_8042.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-static void fw_config_tablet_mode(void);
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-void board_init(void)
-{
-	int on;
-
-	/* Enable C0 interrupt and check if it needs processing */
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	/* Enable interrupt for passing through HPD */
-	gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	fw_config_tablet_mode();
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
-		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 0);
-		gpio_set_level(GPIO_HDMI_PP3300_EN, 1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
-		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 1);
-		gpio_set_level(GPIO_HDMI_PP3300_EN, 0);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-#ifdef BOARD_WADDLEDOO
-static void reconfigure_5v_gpio(void)
-{
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (system_get_board_version() < 0) {
-		CPRINTS("old board - remapping 5V en");
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
-#endif /* BOARD_WADDLEDOO */
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC, or send enable signal to HDMI
-	 * DB.
-	 */
-	set_5v_gpio(!!enable);
-
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dso_data lsm6dso_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-/* Keyboard scan setting */
-static const struct ec_response_keybd_config cret_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &cret_keybd;
-}
-
-static void fw_config_tablet_mode(void)
-{
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void board_extpower(void)
-{
-	int extpower_present;
-
-	if (pd_is_connected(0))
-		extpower_present = extpower_is_present();
-	else
-		extpower_present = 0;
-
-	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
diff --git a/board/cret/board.h b/board/cret/board.h
deleted file mode 100644
index d88ff2267d..0000000000
--- a/board/cret/board.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-/* Save some flash space */
-#define CONFIG_CHIP_INIT_ROM_REGION
-#define CONFIG_DEBUG_ASSERT_BRIEF
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_I2C_DEBUG
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_EC_HDMI_EN_ODL GPIO_EC_I2C_SBU_USB_C1_SCL
-#define GPIO_HDMI_PP3300_EN GPIO_SUB_USB_C1_INT_ODL
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* LED */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#define CONFIG_LED_ONOFF_STATES
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-#undef PD_POWER_SUPPLY_TURN_ON_DELAY
-#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-/* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_BYD_1VX1H,
-	BATTERY_BYD_YT39X,
-	BATTERY_BYD_X0Y5M,
-	BATTERY_LGC_FDRHM,
-	BATTERY_LGC_8GHCX,
-	BATTERY_SWD_ATL_WJPC4,
-	BATTERY_SWD_ATL_CTGKT,
-	BATTERY_SWD_COS_WJPC4,
-	BATTERY_SWD_COS_CTGKT,
-	BATTERY_SMP_ATL_VM732,
-	BATTERY_SMP_ATL_26JGK,
-	BATTERY_SMP_ATL_RF9H3,
-	BATTERY_SMP_COS_VM732,
-	BATTERY_SMP_COS_26JGK,
-	BATTERY_SMP_COS_RF9H3,
-	BATTERY_BYD16,
-	BATTERY_LGC3,
-	BATTERY_SIMPLO,
-	BATTERY_SIMPLO_LS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cret/build.mk b/board/cret/build.mk
deleted file mode 100644
index af526189dd..0000000000
--- a/board/cret/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/cret/cbi_ssfc.c b/board/cret/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/cret/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/cret/cbi_ssfc.h b/board/cret/cbi_ssfc.h
deleted file mode 100644
index 058290de8d..0000000000
--- a/board/cret/cbi_ssfc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-/*
- * Bits 9-11
- * Cret board uses SSFC bits 9-11 in coreboot for audio codec.
- */
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cret/ec.tasklist b/board/cret/ec.tasklist
deleted file mode 100644
index ee5333eb17..0000000000
--- a/board/cret/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/cret/gpio.inc b/board/cret/gpio.inc
deleted file mode 100644
index 352f689620..0000000000
--- a/board/cret/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dso_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-GPIO(SUB_USB_C1_INT_ODL,    PIN(F, 5), GPIO_OUT_LOW) /* 5V power en */
-GPIO(EC_I2C_SBU_USB_C1_SCL,	PIN(9, 2), GPIO_ODR_LOW) /* HDMI en */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-
-/* USB pins */
-GPIO(USB_A0_CHARGE_EN_L,	PIN(6, 3), GPIO_OUT_HIGH)  /* Reverse: Enable A0 1.5A Charging */
-GPIO(EN_USB_A0_VBUS,         PIN(4, 1), GPIO_OUT_LOW)  /* Enable A0 5V Charging */
-
-/*LEDs*/
-GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x04), 0, MODULE_PWM, 0)   /* PWM1 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO72_NC, PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/cret/led.c b/board/cret/led.c
deleted file mode 100644
index edfb4ac761..0000000000
--- a/board/cret/led.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 10;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Cret: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/cret/usb_pd_policy.c b/board/cret/usb_pd_policy.c
deleted file mode 100644
index 15faf41ffc..0000000000
--- a/board/cret/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/cret/vif_override.xml b/board/cret/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/cret/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dalboz/analyzestack.yaml b/board/dalboz/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/dalboz/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/dalboz/battery.c b/board/dalboz/battery.c
deleted file mode 100644
index 5a90a767c8..0000000000
--- a/board/dalboz/battery.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L19M3PG1 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* LGC  L19L3PG1 */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Celxpert  L19C3PG1 */
-	[BATTERY_CEL] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L19C3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/dalboz/board.c b/board/dalboz/board.c
deleted file mode 100644
index e4ee1bfe82..0000000000
--- a/board/dalboz/board.c
+++ /dev/null
@@ -1,672 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "button.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8740.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
-
-/* Interrupt handler varies with DB option. */
-void (*c1_tcpc_config_interrupt)(enum gpio_signal signal) = tcpc_alert_event;
-
-void c1_tcpc_interrupt(enum gpio_signal signal)
-{
-	c1_tcpc_config_interrupt(signal);
-}
-
-/* Interrupt for C1 PPC with USB-C DB, HPD with HDMI DB. */
-void (*c1_ppc_config_interrupt)(enum gpio_signal signal) = ppc_interrupt;
-
-void c1_ppc_interrupt(enum gpio_signal signal)
-{
-	c1_ppc_config_interrupt(signal);
-}
-
-static void hdmi_hpd_handler(void)
-{
-	/* Pass HPD through from DB OPT1 HDMI connector to AP's DP1. */
-	int hpd = gpio_get_level(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_set_level(GPIO_DP1_HPD, hpd);
-	ccprints("HDMI HPD %d", hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-#include "gpio_list.h"
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct stprivate_data g_lis2dwl_data;
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* These IO expander GPIOs vary with DB option. */
-enum gpio_signal IOEX_USB_A1_RETIMER_EN = IOEX_USB_A1_RETIMER_EN_OPT1;
-enum gpio_signal IOEX_USB_A1_CHARGE_EN_DB_L = IOEX_USB_A1_CHARGE_EN_DB_L_OPT1;
-
-static void pcal6408_handler(void)
-{
-	pcal6408_ioex_event_handler(IOEX_HDMI_PCAL6408);
-}
-DECLARE_DEFERRED(pcal6408_handler);
-
-void pcal6408_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&pcal6408_handler_data, 0);
-}
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS5,
-};
-
-/*****************************************************************************
- * Board suspend / resume
- */
-
-static void board_chipset_resume(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 1);
-		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 0);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		/* Enable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
-	else
-		/* Disable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
-
-	return EC_SUCCESS;
-}
-
-
-/*****************************************************************************
- * USB-C
- */
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		/*
-		 * Sensitive only to falling edges; GPIO is configured for both
-		 * because this input may be used for HDMI HPD instead.
-		 */
-		if (!gpio_get_level(signal))
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	case USBC_PORT_C1:
-		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-static void setup_fw_config(void)
-{
-	uint32_t board_version = 0;
-
-	if (cbi_get_board_version(&board_version) == EC_SUCCESS
-	    && board_version >= 2) {
-		ccprints("PS8743 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8743_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = &board_ps8743_mux_set;
-	} else {
-		ccprints("PS8740 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8740_I2C_ADDR0_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8740_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = NULL;
-	}
-
-	if (ec_config_get_usb_db() == DALBOZ_DB_D_OPT2_USBA_HDMI) {
-		ccprints("DB OPT2 HDMI");
-		ioex_config[IOEX_HDMI_PCAL6408].flags = 0;
-		ioex_init(IOEX_HDMI_PCAL6408);
-		IOEX_USB_A1_RETIMER_EN = IOEX_USB_A1_RETIMER_EN_OPT2;
-		IOEX_USB_A1_CHARGE_EN_DB_L = IOEX_USB_A1_CHARGE_EN_DB_L_OPT2;
-		usb_port_enable[USBA_PORT_A1] = IOEX_EN_USB_A1_5V_DB_OPT2;
-		c1_tcpc_config_interrupt = pcal6408_interrupt;
-		c1_ppc_config_interrupt = hdmi_hpd_interrupt;
-	} else {
-		ccprints("DB OPT1 USBC");
-		ioex_config[IOEX_C1_NCT3807].flags = 0;
-		ioex_init(IOEX_C1_NCT3807);
-		IOEX_USB_A1_RETIMER_EN = IOEX_USB_A1_RETIMER_EN_OPT1;
-		IOEX_USB_A1_CHARGE_EN_DB_L = IOEX_USB_A1_CHARGE_EN_DB_L_OPT1;
-		usb_port_enable[USBA_PORT_A1] = IOEX_EN_USB_A1_5V_DB_OPT1;
-		c1_tcpc_config_interrupt = tcpc_alert_event;
-		c1_ppc_config_interrupt = ppc_interrupt;
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
-
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-/*
- * Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init().
- */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[IOEX_C1_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_HDMI_PCAL6408] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PCAL6408_I2C_ADDR0,
-		.drv = &pcal6408_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB_OPT1,
-};
-
-static void check_v0_battery(void)
-{
-	uint32_t board_version = 0;
-
-	cbi_get_board_version(&board_version);
-
-	if (board_version == 1)
-		I2C_PORT_BATTERY = I2C_PORT_BATTERY_V0;
-}
-/*
- * Use HOOK_PRIO_INIT_I2C so we re-map before init_battery_type() and
- * charger_chips_init() want to talk to the battery.
- */
-DECLARE_HOOK(HOOK_INIT, check_v0_battery, HOOK_PRIO_INIT_I2C);
diff --git a/board/dalboz/board.h b/board/dalboz/board.h
deleted file mode 100644
index eecdc72d41..0000000000
--- a/board/dalboz/board.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_DALBOZ
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_IO_EXPANDER_PCAL6408
-
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USB_MUX_PS8740
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PORT_ENABLE_DYNAMIC
-
-/* USB-A config */
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-extern int I2C_PORT_BATTERY;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_CEL,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_HDMI_PCAL6408,
-	IOEX_PORT_COUNT
-};
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * DALBOZ_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	DALBOZ_MB_USBAC = 0,
-};
-
-/**
- * DALBOZ_DB_D_OPT1_USBAC
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8740
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- *
- * DALBOZ_DB_D_OPT2_USBA_HDMI
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  none
- *		IOEX: PCAL6408
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- */
-enum ec_cfg_usb_db_type {
-	DALBOZ_DB_D_OPT1_USBAC = 0,
-	DALBOZ_DB_D_OPT2_USBA_HDMI = 1,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBC1 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
-
-static inline bool ec_config_has_usbc1(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1);
-}
-
-#define HAS_USBC1_RETIMER_PS8740 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
-
-static inline bool ec_config_has_usbc1_retimer_ps8740(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8740);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-/* These IO expander GPIOs vary with DB option. */
-extern enum gpio_signal IOEX_USB_A1_RETIMER_EN;
-extern enum gpio_signal IOEX_USB_A1_CHARGE_EN_DB_L;
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dalboz/build.mk b/board/dalboz/build.mk
deleted file mode 100644
index 4ca0cbd96f..0000000000
--- a/board/dalboz/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/dalboz/ec.tasklist b/board/dalboz/ec.tasklist
deleted file mode 100644
index 41b83cf4f3..0000000000
--- a/board/dalboz/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/dalboz/gpio.inc b/board/dalboz/gpio.inc
deleted file mode 100644
index 74fe019b47..0000000000
--- a/board/dalboz/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			c1_tcpc_interrupt)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-/* PPC interrupts trigger on falling edge, but HDMI HPD triggers on rising edge. */
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP, 	c1_ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	lsm6dsm_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-GPIO(LED3_PWM,			PIN(C, 3), GPIO_OUT_HIGH)
-
-/*
- * Dalboz has 2 DB options, with different IO expanders. IOEX_C1_NCT3807 is the
- * OPT1 DB (USB-C1), IOEX_HDMI_PCAL6408 is the OPT2 DB (HDMI).
- */
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN_OPT1,	EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB_OPT1,	EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L_OPT1,EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-IOEX(USB_A1_RETIMER_EN_OPT2,	EXPIN(IOEX_HDMI_PCAL6408, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB_OPT2,	EXPIN(IOEX_HDMI_PCAL6408, 0, 1), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L_OPT2,EXPIN(IOEX_HDMI_PCAL6408, 0, 2), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(IOEX_HDMI_PCAL6408, 0, 3), GPIO_OUT_HIGH)	/* HDMI Retimer Enable */
-IOEX(EN_PWR_HDMI_DB,		EXPIN(IOEX_HDMI_PCAL6408, 0, 5), GPIO_OUT_LOW)	/* HDMI Retimer Power Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/dalboz/led.c b/board/dalboz/led.c
deleted file mode 100644
index 53e94e84d6..0000000000
--- a/board/dalboz/led.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-};
-
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-__override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED3_PWM, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED3_PWM, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/dalboz/vif_override.xml b/board/dalboz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dalboz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/damu/battery.c b/board/damu/battery.c
deleted file mode 100644
index c85240a108..0000000000
--- a/board/damu/battery.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/damu/board.c b/board/damu/board.c
deleted file mode 100644
index ca3979949a..0000000000
--- a/board/damu/board.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = board_set_active_charge_port(port);
-	if (ret)
-		return ret;
-	force_discharge = enable;
-
-	return charger_discharge_on_ac(enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
diff --git a/board/damu/board.h b/board/damu/board.h
deleted file mode 100644
index 6df8bb2a7a..0000000000
--- a/board/damu/board.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-/* TODO(b:135086465) led implementation */
-#undef CONFIG_LED_COMMON
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL   	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger */
-int board_get_charger_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/damu/build.mk b/board/damu/build.mk
deleted file mode 100644
index 0b3565fd84..0000000000
--- a/board/damu/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/damu/ec.tasklist b/board/damu/ec.tasklist
deleted file mode 100644
index 19d2f34687..0000000000
--- a/board/damu/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, 1024) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/damu/gpio.inc b/board/damu/gpio.inc
deleted file mode 100644
index 9ee4035917..0000000000
--- a/board/damu/gpio.inc
+++ /dev/null
@@ -1,115 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/damu/led.c b/board/damu/led.c
deleted file mode 100644
index ee376b4b41..0000000000
--- a/board/damu/led.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Damu
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if(led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if(led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if(led_id == EC_LED_ID_BATTERY_LED) {
-		if(brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if(brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if(led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/damu/vif_override.xml b/board/damu/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/damu/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dartmonkey b/board/dartmonkey
deleted file mode 120000
index 5e193ac466..0000000000
--- a/board/dartmonkey
+++ /dev/null
@@ -1 +0,0 @@
-./nocturne_fp
\ No newline at end of file
diff --git a/board/delbin/battery.c b/board/delbin/battery.c
deleted file mode 100644
index e907a3574f..0000000000
--- a/board/delbin/battery.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C536] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXAE3jB",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000c,
-				.disconnect_val = 0x000c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11880, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C536;
diff --git a/board/delbin/board.c b/board/delbin/board.c
deleted file mode 100644
index 5984c4d157..0000000000
--- a/board/delbin/board.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff,
-		0xff  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Delbin if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(65),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(65),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(int port)
-{
-	int val;
-	int i2c_port;
-	enum gpio_signal ps8xxx_rst_odl;
-
-	if (port == USBC_PORT_C0) {
-		ps8xxx_rst_odl = GPIO_USB_C0_RT_RST_ODL;
-		i2c_port = I2C_PORT_USB_C0;
-	} else if (port == USBC_PORT_C1) {
-		ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-		i2c_port = I2C_PORT_USB_C1;
-	} else {
-		return;
-	}
-
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
-
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(i2c_port,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	ps8815_reset(USBC_PORT_C0);
-	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	ps8815_reset(USBC_PORT_C1);
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-static const struct ec_response_keybd_config delbin_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &delbin_kb;
-}
-
-static void ps8811_init(void)
-{
-	int rv;
-
-	/* Set Channel A output swing to Level1 */
-	rv = i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10);
-	/* Set 50 ohm termination adjuct for B channel: -9%*/
-	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04);
-	/* Set Channel B output swing to Level3 */
-	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03);
-	/* Set PS level for B channel */
-	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84);
-	/* Set DE level for B channel */
-	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16);
-}
-
-/* Called on AP S5 -> S0ix transition */
-static void board_chipset_startup(void)
-{
-	ps8811_init();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0ix -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0ix transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_mb_retimer,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/delbin/board.h b/board/delbin/board.h
deleted file mode 100644
index 91f69a2bae..0000000000
--- a/board/delbin/board.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0	/* GPIO C2 is not used as PWM1. */
-
-/* Optional features */
-#undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X
-
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C536,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/delbin/build.mk b/board/delbin/build.mk
deleted file mode 100644
index 66ad809f59..0000000000
--- a/board/delbin/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/delbin/ec.tasklist b/board/delbin/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/delbin/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/delbin/gpio.inc b/board/delbin/gpio.inc
deleted file mode 100644
index 333c638b0a..0000000000
--- a/board/delbin/gpio.inc
+++ /dev/null
@@ -1,178 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Delbin, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-GPIO(USB_C0_RT_RST_ODL,			PIN(D, 4), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(LED_1_L,			PIN(C, 4), GPIO_OUT_HIGH)	/* Battery Full LED: White */
-GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)	/* Battery Charging LED: Amber */
-GPIO(LED_3_L,			PIN(C, 2), GPIO_OUT_HIGH)	/* Battery Power LED: White */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight */
-
-/* Unused signals */
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO72,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOA7,		PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC0,		PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/delbin/led.c b/board/delbin/led.c
deleted file mode 100644
index 27f63c9544..0000000000
--- a/board/delbin/led.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/delbin/sensors.c b/board/delbin/sensors.c
deleted file mode 100644
index 8000295554..0000000000
--- a/board/delbin/sensors.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi260_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.default_range = 4, /* g */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi260_interrupt(signal);
-}
-
-static void baseboard_sensors_init(void)
-{
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-		ccprints("LID_ACCEL is KX022");
-	} else
-		ccprints("LID_ACCEL is BMA253");
-
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE ACCEL is ICM426XX");
-	} else
-		ccprints("BASE ACCEL IS BMI260");
-
-	/* Enable interrupt for the accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/delbin/vif_override.xml b/board/delbin/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/delbin/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dewatt/battery.c b/board/dewatt/battery.c
deleted file mode 100644
index ddf3adff50..0000000000
--- a/board/dewatt/battery.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-
-/*
- * Battery info for all Guybrush battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AEC 5477109 */
-	[BATTERY_AEC] = {
-		.fuel_gauge = {
-			.manuf_name = "AEC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.sleep_mode = {
-				.sleep_supported = true,
-				.reg_addr = 0x00,
-				.reg_data = 0x0011,
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8700,	/* mV */
-			.voltage_normal       = 7600,
-			.voltage_min          = 6000,
-			.precharge_current    = 100,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 50,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 60,
-		},
-	},
-	/* AP18F4M / LIS4163ACPC */
-	[BATTERY_AP18F4M] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00404001",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8700,	/* mV */
-			.voltage_normal       = 7600,
-			.voltage_min          = 5500,
-			.precharge_current    = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* POW-TECH Battery Information */
-	[BATTERY_POWER_TECH] = {
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.sleep_mode = {
-				.sleep_supported = true,
-				.reg_addr = 0x00,
-				.reg_data = 0x0011,
-			},
-			.fet = {
-				.reg_addr       = 0x00,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8800,	/* mV */
-			.voltage_normal       = 7700,
-			.voltage_min          = 6000,
-			.precharge_current    = 88,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 45,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
diff --git a/board/dewatt/board.c b/board/dewatt/board.c
deleted file mode 100644
index 53180d39cb..0000000000
--- a/board/dewatt/board.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush board-specific configuration */
-
-#include "adc.h"
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi323.h"
-#include "driver/accel_bma422.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/temp_sensor/tmp112.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "temp_sensor/tmp112.h"
-#include "thermal.h"
-#include "usb_mux.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Motion sensor mutex */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Motion sensor private data */
-static struct bmi_drv_data_t g_bmi_data;
-static struct accelgyro_saved_data_t g_bma422_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI323,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi3xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA422,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma4_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma422_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA4_ACCEL_MIN_FREQ,
-		.max_frequency = BMA4_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, enough for laptop. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI323,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi3xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t bmi160_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref,
-	.min_frequency = BMI_ACCEL_MIN_FREQ,
-	.max_frequency = BMI_ACCEL_MAX_FREQ,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t bmi160_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref,
-	.min_frequency = BMI_GYRO_MIN_FREQ,
-	.max_frequency = BMI_GYRO_MAX_FREQ,
-};
-
-__override enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	/* Set channel A output swing */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING,
-		PS8811_CHAN_A_SWING_MASK, 0x2 << PS8811_CHAN_A_SWING_SHIFT));
-
-	/* Set channel B output swing */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_SWING,
-		PS8811_CHAN_B_SWING_MASK, 0x2 << PS8811_CHAN_B_SWING_SHIFT));
-
-	/* Set channel B de-emphasis to -6dB and pre-shoot to 1.5 dB */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
-		PS8811_CHAN_B_DE_PS_LSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_LSB));
-
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
-		PS8811_CHAN_B_DE_PS_MSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_MSB));
-
-	return EC_SUCCESS;
-}
-
-/*
- * PS8818 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- * TODO(b/179036200): Adjust PS8818 tuning for guybrush reference
- */
-__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 1);
-	} else {
-		/* Disable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 0);
-	}
-
-	return rv;
-}
-
-/*
- * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default
- * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c
- * address to 0x2A. ANX7491(A1) will stay at the default 0x29.
- */
-uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me)
-{
-	ASSERT(me->usb_port == USBC_PORT_C1);
-	return 0x2a;
-}
-
-/*
- * Base Gyro Sensor dynamic configuration
- */
-static int base_gyro_config;
-
-static void board_update_motion_sensor_config(void)
-{
-	if (board_is_convertible()) {
-		if (get_board_version() == 1) {
-			motion_sensors[BASE_ACCEL] = bmi160_base_accel;
-			motion_sensors[BASE_GYRO] = bmi160_base_gyro;
-			base_gyro_config = BASE_GYRO_BMI160;
-			ccprints("BASE GYRO is BMI160");
-		} else {
-			base_gyro_config = BASE_GYRO_BMI323;
-			ccprints("BASE GYRO is BMI323");
-		}
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel and Gyro interrupt */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case BASE_GYRO_BMI160:
-		bmi160_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI323:
-	default:
-		bmi3xx_interrupt(signal);
-		break;
-	}
-}
-
-static void board_init(void)
-{
-	board_update_motion_sensor_config();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	if (get_board_version() > 1)
-		tmp112_init();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-int board_get_soc_temp_k(int idx, int *temp_k)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_k(idx, temp_k);
-}
-
-int board_get_soc_temp_mk(int *temp_mk)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_mk(TMP112_SOC, temp_mk);
-}
-
-int board_get_ambient_temp_mk(int *temp_mk)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_mk(TMP112_AMB, temp_mk);
-}
-
-/* ADC Channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_MEMORY] = {
-		.name = "MEMORY",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_CORE_IMON1] = {
-		.name = "CORE_I",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SOC_IMON2] = {
-		.name = "SOC_I",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temp Sensors */
-static int board_get_memory_temp(int, int *);
-
-const struct tmp112_sensor_t tmp112_sensors[] = {
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS0 },
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS1 },
-};
-BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_soc_temp_k,
-		.idx = TMP112_SOC,
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.name = "Memory",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_memory_temp,
-		.idx = ADC_TEMP_SENSOR_MEMORY,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-	[TEMP_SENSOR_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = tmp112_get_val_k,
-		.idx = TMP112_AMB,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/* TODO: Setting fan off to 0 so it's allways on */
-		.temp_fan_off = C_TO_K(0),
-		.temp_fan_max = C_TO_K(70),
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/*
-		 * CPU temp sensor fan thresholds are high because they are a
-		 * backup for the SOC temp sensor fan thresholds.
-		 */
-		.temp_fan_off = C_TO_K(60),
-		.temp_fan_max = C_TO_K(90),
-	},
-	/*
-	 * Note: Leave ambient entries at 0, both as it does not represent a
-	 * hotspot and as not all boards have this sensor
-	 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static int board_get_memory_temp(int idx, int *temp_k)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
-}
diff --git a/board/dewatt/board.h b/board/dewatt/board.h
deleted file mode 100644
index f5c47718d5..0000000000
--- a/board/dewatt/board.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Motion sensing drivers */
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI3XX
-#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_BMA4XX
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_MUX_ANX7451
-#define CONFIG_USBC_RETIMER_ANX7451
-
-/* USB Type A Features */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* LED features */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-/* Battery Types */
-enum battery_type {
-	BATTERY_AEC,
-	BATTERY_AP18F4M,
-	BATTERY_POWER_TECH,
-	BATTERY_TYPE_COUNT,
-};
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_BMI323 = 2,
-};
-
-/* ADC Channels */
-enum adc_channel {
-	ADC_TEMP_SENSOR_SOC = 0,
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_MEMORY,
-	ADC_CORE_IMON1,
-	ADC_SOC_IMON2,
-	ADC_CH_COUNT
-};
-
-/* Temp Sensors */
-enum temp_sensor_id {
-	TEMP_SENSOR_SOC = 0,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_MEMORY,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dewatt/board_fw_config.c b/board/dewatt/board_fw_config.c
deleted file mode 100644
index c919d82851..0000000000
--- a/board/dewatt/board_fw_config.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-
-bool board_is_convertible(void)
-{
-	return (get_fw_config_field(FW_CONFIG_FORM_FACTOR_OFFSET,
-			FW_CONFIG_FORM_FACTOR_WIDTH)
-			== FW_CONFIG_FORM_FACTOR_CONVERTIBLE);
-}
-
-bool board_has_kblight(void)
-{
-	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
-}
-
-enum board_usb_c1_mux board_get_usb_c1_mux(void)
-{
-	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
-					 FW_CONFIG_USB_DB_WIDTH);
-	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
-		return USB_C1_MUX_PS8818;
-	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
-		return USB_C1_MUX_ANX7451;
-	return USB_C1_MUX_UNKNOWN;
-};
-
-enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
-{
-	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
-					 FW_CONFIG_USB_DB_WIDTH);
-	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
-		return USB_A1_RETIMER_PS8811;
-	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
-		return USB_A1_RETIMER_ANX7491;
-	return USB_A1_RETIMER_UNKNOWN;
-};
diff --git a/board/dewatt/board_fw_config.h b/board/dewatt/board_fw_config.h
deleted file mode 100644
index 1de417d77a..0000000000
--- a/board/dewatt/board_fw_config.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _GUYBRUSH_BOARD_FW_CONFIG__H_
-#define _GUYBRUSH_BOARD_FW_CONFIG__H_
-
-/****************************************************************************
- * Guybrush CBI FW Configuration
- */
-
-/*
- * USB Daughter Board (2 bits)
- */
-#define FW_CONFIG_USB_DB_OFFSET			0
-#define FW_CONFIG_USB_DB_WIDTH			2
-#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818	0
-#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451	1
-
-/*
- * Form Factor (1 bits)
- */
-#define FW_CONFIG_FORM_FACTOR_OFFSET		2
-#define FW_CONFIG_FORM_FACTOR_WIDTH		1
-#define FW_CONFIG_FORM_FACTOR_CLAMSHELL		0
-#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE	1
-
-/*
- * Keyboard Backlight (1 bit)
- */
-#define FW_CONFIG_KBLIGHT_OFFSET		3
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
-
-
-#endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/dewatt/build.mk b/board/dewatt/build.mk
deleted file mode 100644
index e4fdcf4afd..0000000000
--- a/board/dewatt/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-BASEBOARD:=guybrush
-
-board-y=board.o
-board-y+=board_fw_config.o led.o battery.o
diff --git a/board/dewatt/ec.tasklist b/board/dewatt/ec.tasklist
deleted file mode 100644
index 94ff657db3..0000000000
--- a/board/dewatt/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/dewatt/gpio.inc b/board/dewatt/gpio.inc
deleted file mode 100644
index 1bab89ed63..0000000000
--- a/board/dewatt/gpio.inc
+++ /dev/null
@@ -1,28 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the board GPIOs that we care about. */
-
-#include "base_gpio.inc"
-
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP, motion_interrupt)		/* 6 Axis IMU */
-GPIO_INT(TABLET_MODE,		PIN(C, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)			/* 360 Tablet Mode */
-
-/* LED Signals */
-ALTERNATE(/*EC_PWM_LED_CHRG_L*/	PIN_MASK(C, BIT(4)), 0, 			MODULE_PWM, 0)		/* Charging LED */
-ALTERNATE(/*EC_PWM_LED_FULL_L*/	PIN_MASK(8, BIT(0)), 0, 			MODULE_PWM, 0)		/* Full LED */
-
-/* Test Points */
-GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_CLK,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_DAT,		PIN(7, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
\ No newline at end of file
diff --git a/board/dewatt/led.c b/board/dewatt/led.c
deleted file mode 100644
index b17c8be488..0000000000
--- a/board/dewatt/led.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Guybrush specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-/* Note PWM LEDs are active low */
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_CHRG, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_ON_LVL);
-		break;
-	case LED_OFF:
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	default: /* Unsupported colors */
-		CPRINTS("Unsupported LED color: %d", color);
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else {
-		CPRINTS("Unsupported LED set: %d", led_id);
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/dewatt/vif_override.xml b/board/dewatt/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dewatt/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dingdong/board.c b/board/dingdong/board.c
deleted file mode 100644
index ddaf6bb928..0000000000
--- a/board/dingdong/board.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Dingdong dongle configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "usb_bb.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-
-void hpd_event(enum gpio_signal signal);
-#include "gpio_list.h"
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_irq_deferred(void)
-{
-	pd_send_hpd(0, hpd_irq);
-}
-DECLARE_DEFERRED(hpd_irq_deferred);
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DP_HPD);
-
-	if (level != hpd_prev_level)
-		/* It's a glitch while in deferred or canceled action */
-		return;
-
-	pd_send_hpd(0, (level) ? hpd_high : hpd_low);
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-void hpd_event(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data, -1);
-
-	/* It's a glitch.  Previous time moves but level is the same. */
-	if (cur_delta < HPD_USTREAM_DEBOUNCE_IRQ)
-		return;
-
-	if ((!hpd_prev_level && level) &&
-	    (cur_delta < HPD_USTREAM_DEBOUNCE_LVL))
-		/* It's an irq */
-		hook_call_deferred(&hpd_irq_deferred_data, 0);
-	else if (cur_delta >= HPD_USTREAM_DEBOUNCE_LVL)
-		hook_call_deferred(&hpd_lvl_deferred_data,
-				   HPD_USTREAM_DEBOUNCE_LVL);
-
-	hpd_prev_level = level;
-}
-
-/* Initialize board. */
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	timestamp_t now = get_time();
-	hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
-	hpd_prev_ts = now.val;
-	gpio_enable_interrupt(GPIO_DP_HPD);
-
-	gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
-}
-
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-const void * const usb_strings[] = {
-	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT] = USB_STRING_DESC("Dingdong"),
-	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/**
- * USB configuration
- * Any type-C device with alternate mode capabilities must have the following
- * set of descriptors.
- *
- * 1. Standard Device
- * 2. BOS
- *    2a. Container ID
- *    2b. Billboard Caps
- */
-struct my_bos {
-	struct usb_bos_hdr_descriptor bos;
-	struct usb_contid_caps_descriptor contid_caps;
-	struct usb_bb_caps_base_descriptor bb_caps;
-	struct usb_bb_caps_svid_descriptor bb_caps_svids[1];
-};
-
-static struct my_bos bos_desc = {
-	.bos = {
-		.bLength = USB_DT_BOS_SIZE,
-		.bDescriptorType = USB_DT_BOS,
-		.wTotalLength = (USB_DT_BOS_SIZE + USB_DT_CONTID_SIZE +
-				 USB_BB_CAPS_BASE_SIZE +
-				 USB_BB_CAPS_SVID_SIZE * 1),
-		.bNumDeviceCaps = 2,  /* contid + bb_caps */
-	},
-	.contid_caps =	{
-		.bLength = USB_DT_CONTID_SIZE,
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_CONTID,
-		.bReserved = 0,
-		.ContainerID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-	},
-	.bb_caps = {
-		.bLength = (USB_BB_CAPS_BASE_SIZE + USB_BB_CAPS_SVID_SIZE * 1),
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_BILLBOARD,
-		.iAdditionalInfoURL = USB_STR_BB_URL,
-		.bNumberOfAlternateModes = 1,
-		.bPreferredAlternateMode = 1,
-		.VconnPower = 0,
-		.bmConfigured = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-				 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-		.bReserved = 0,
-	},
-	.bb_caps_svids = {
-		{
-			.wSVID = USB_SID_DISPLAYPORT,
-			.bAlternateMode = 1,
-			.iAlternateModeString = USB_STR_BB_URL, /* TODO(crosbug.com/p/32687) */
-		},
-	},
-};
-
-const struct bos_context bos_ctx = {
-	.descp = (void *)&bos_desc,
-	.size = sizeof(struct my_bos),
-};
diff --git a/board/dingdong/board.h b/board/dingdong/board.h
deleted file mode 100644
index 64947960ba..0000000000
--- a/board/dingdong/board.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dingdong dongle configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_ADC
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_HW_CRC
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#define CONFIG_RWSIG_TYPE_USBPD1
-#define CONFIG_SHA256
-#define CONFIG_USB
-#define CONFIG_USB_BOS
-#define CONFIG_USB_INHIBIT_CONNECT
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_DINGDONG
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 2
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FLASH
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-#define CONFIG_USB_PD_VBUS_DETECT_NONE
-#define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
-#define CONFIG_EVENT_LOG_SIZE 256
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* USB configuration */
-#define CONFIG_USB_PID 0x5011
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-/* No Write-protect GPIO, force the write-protection */
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-
-/* Inform VIF generator that this board is an Alt Mode Adapter */
-#define CONFIG_USB_ALT_MODE_ADAPTER
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CH_CC1_PD = 0,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_BB_URL,
-
-	USB_STR_COUNT
-};
-
-/* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
-
-#endif /* !__ASSEMBLER__ */
-
-/* USB Device class */
-#define USB_DEV_CLASS USB_CLASS_BILLBOARD
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dingdong/build.mk b/board/dingdong/build.mk
deleted file mode 100644
index 18799c3b9f..0000000000
--- a/board/dingdong/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072B
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/dingdong/dev_key.pem b/board/dingdong/dev_key.pem
deleted file mode 100644
index e2ff6781cd..0000000000
--- a/board/dingdong/dev_key.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEpAIBAAKCAQEAqhcIe02T0+guB+QDIKTy578gwH0W0BpZM4B0scTq0ozQ6YJe
-9O74HBWYlWUkbx+/AaM50yeroqx6DC4ZLgm8PcBFpCkxhuOdP6BZbjEqEoI4nVOg
-nDsW3XpNODYueA7IpqiOjUgAcAeNTEfdxIGGh6XWwsJmGdbJCWu4SiWsKyJVThCr
-1DPh3nPEmzDpX4CYU93qFeoJptKKH0DJcMKEP3CR8H0OU9S5wLoA10s9TECsWMN9
-z7vZQaelxsFrzHPgY2amX1uruSI4BaZ8aGYTtKzcTkzSnT/jD8QTiDnSYsMXs7h4
-6af24h3SZdApB5yFYQqcS80DWgHcubeT24ulXwIDAQABAoIBAAslnUmvaNu/YJzl
-xYqzJLQpY3UZ/Y+/2k60wXERDa6kyeAzyhNVQe9dPvWzfjLGKtdpohWDiQ0NLqZz
-svTAcJS/cBD1HijP6/NKh/HfyPkTjbBJ1cHHYZU8OalQa7U0itPZQhZiPJ0a8Zip
-MRB6yJ1FMhDrepOA7wXuCFLbqy/cYcY+MdKL6Fny5FFIBMq16EeFOKBOR+DZsLEg
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-GPFkKNXeMFRcGg7rTp51L0DhG6hbWgCkck3AtcHy86LgehsDaWhEi+0CgYEAxoMi
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-1pre7E2gRVh61cS5vARn4QKBgQCNxp6jeal8LvHxI/R5Tjiur0Kc2y806BR79/ds
-HV70E8kszvpRJGp1IdXblq7hT79FmAjaPdcHxtEV201vqN7eORJ0m1/mZ1h8gBKr
-oJkGzMPj5/+V6zwMWPdEFtw9EqgeOwatMmRFOmkOx7DDEH4Ra3CF2cOoG7+BhMZq
-E3dk/QKBgQCYXqptB56sUrjnCXKEAdR96SDlVCmL7BBI893xDSAYIKhbpQsI2YY1
-dcFb02bnMbpqjkwHqpjHD8MJOWvXf8q/5FxDjHBSLSL8fM2PL9DI65c8MmwpHUSZ
-ZdcRhMrlN1iTkzw7WdfFCqb0HNl73sP5baqbRZgC+gysmDtgTZxBTQ==
------END RSA PRIVATE KEY-----
diff --git a/board/dingdong/ec.tasklist b/board/dingdong/ec.tasklist
deleted file mode 100644
index 41fc047d6a..0000000000
--- a/board/dingdong/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/dingdong/gpio.inc b/board/dingdong/gpio.inc
deleted file mode 100644
index ec1e9a7fa9..0000000000
--- a/board/dingdong/gpio.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(DP_HPD,        PIN(A, 0), GPIO_INT_BOTH, hpd_event)
-
-GPIO(USB_C_CC1_PD,      PIN(A, 1), GPIO_ANALOG)
-GPIO(STM_READY,         PIN(A, 2), GPIO_OUT_LOW)  /* factory test only */
-GPIO(PD_DAC_REF,        PIN(A, 4), GPIO_ANALOG)
-GPIO(DP_AUX_N,          PIN(A, 5), GPIO_INPUT)
-GPIO(DP_AUX_P,          PIN(A, 6), GPIO_INPUT)
-
-GPIO(PD_SBU_ENABLE,     PIN(A, 8),  GPIO_OUT_LOW)
-GPIO(USB_DM,            PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,            PIN(A, 12), GPIO_ANALOG)
-GPIO(PD_CC1_TX_EN,      PIN(A, 15), GPIO_OUT_LOW)
-
-GPIO(PD_DPSINK_PRESENT, PIN(B, 0), GPIO_INPUT)
-GPIO(PD_CC1_TX_DATA,    PIN(B, 4), GPIO_OUT_LOW)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0)            /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0)            /* TIM17_CH1: PB9 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
deleted file mode 100644
index 2f01c275a8..0000000000
--- a/board/dingdong/usb_pd_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PB3-4 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* SPI1_TX no remap needed */
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) BIT(21)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* TIM1_CH1 no remap needed */
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 Mhz pin speed on TX_EN (PA15) */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
-	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* PB4 is SPI1_MISO */
-	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 1);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
-	/* put the low level reference in Hi-Z */
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
-}
-
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable) {}
-
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	/* only one CC line, assume other one is always low */
-	return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c
deleted file mode 100644
index 50700f8a62..0000000000
--- a/board/dingdong/usb_pd_policy.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "board.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_bb.h"
-#include "usb_api.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS PDO_FIXED_COMM_CAP
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-/* Holds valid object position (opos) for entered mode */
-static int alt_mode[PD_AMODE_COUNT];
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* No battery, nothing to do */
-	return;
-}
-
-int pd_is_valid_input_voltage(int mv)
-{
-	/* Any voltage less than the max is allowed */
-	return 1;
-}
-
-void pd_transition_voltage(int idx)
-{
-	/* No operation: sink only */
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return 1;
-}
-
-int pd_board_checks(void)
-{
-	return EC_SUCCESS;
-}
-
-int pd_check_power_swap(int port)
-{
-	/* Always refuse power swap */
-	return 0;
-}
-
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
-{
-	/* Always refuse data swap */
-	return 0;
-}
-
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
-{
-	/* Do nothing */
-}
-
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
-{
-}
-
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
-{
-}
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 1, /* Vbus power required */
-				 AMA_USBSS_BBONLY /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	/* TODO(tbroch): Do we plan to obtain TID (test ID) for hoho */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	payload[VDO_I(AMA)] = vdo_ama;
-	return VDO_I(AMA) + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, USB_VID_GOOGLE);
-	payload[2] = 0;
-	return 3;
-}
-
-#define OPOS_DP 1
-#define OPOS_GFU 1
-
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,             /* UFP pin cfg supported : none */
-		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0 signalling in AMode */
-		    CABLE_PLUG,    /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
-};
-
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes));
-		return ARRAY_SIZE(vdo_dp_modes) + 1;
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		memcpy(payload + 1, vdo_goog_modes, sizeof(vdo_goog_modes));
-		return ARRAY_SIZE(vdo_goog_modes) + 1;
-	} else {
-		return 0; /* nak */
-	}
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = gpio_get_level(GPIO_DP_HPD);
-	if (opos != OPOS_DP)
-		return 0; /* nak */
-
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
-				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
-				   0x2);
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 1);
-
-	return 1;
-}
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	int rv = 0; /* will generate a NAK */
-
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
-	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
-		alt_mode[PD_AMODE_DISPLAYPORT] = OPOS_DP;
-		rv = 1;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 1, NULL);
-	} else if ((PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) &&
-		   (PD_VDO_OPOS(payload[0]) == OPOS_GFU)) {
-		alt_mode[PD_AMODE_GOOGLE] = OPOS_GFU;
-		rv = 1;
-	}
-
-	if (rv)
-		/*
-		 * If we failed initial mode entry we'll have enumerated the USB
-		 * Billboard class.  If so we should disconnect.
-		 */
-		usb_disconnect();
-
-	return rv;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	if (type != TCPCI_MSG_SOP)
-		return 0;
-
-	if (svid == USB_SID_DISPLAYPORT)
-		return alt_mode[PD_AMODE_DISPLAYPORT];
-	else if (svid == USB_VID_GOOGLE)
-		return alt_mode[PD_AMODE_GOOGLE];
-	return 0;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 0);
-		alt_mode[PD_AMODE_DISPLAYPORT] = 0;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 0, NULL);
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		alt_mode[PD_AMODE_GOOGLE] = 0;
-	} else {
-		CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]);
-	}
-
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int rsize;
-
-	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE ||
-	    !alt_mode[PD_AMODE_GOOGLE])
-		return 0;
-
-	*rpayload = payload;
-
-	rsize = pd_custom_flash_vdm(port, cnt, payload);
-	if (!rsize) {
-		int cmd = PD_VDO_CMD(payload[0]);
-		switch (cmd) {
-		case VDO_CMD_GET_LOG:
-			rsize = pd_vdm_get_log_entry(payload);
-			break;
-		default:
-			/* Unknown : do not answer */
-			return 0;
-		}
-	}
-
-	/* respond (positively) to the request */
-	payload[0] |= VDO_SRC_RESPONDER;
-
-	return rsize;
-}
diff --git a/board/dingdong/vif_override.xml b/board/dingdong/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dingdong/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dirinboz/analyzestack.yaml b/board/dirinboz/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/dirinboz/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/dirinboz/battery.c b/board/dirinboz/battery.c
deleted file mode 100644
index c148f9aa52..0000000000
--- a/board/dirinboz/battery.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Dirinboz battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Coslight Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack Coslight Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS;
diff --git a/board/dirinboz/board.c b/board/dirinboz/board.c
deleted file mode 100644
index 150c42fb17..0000000000
--- a/board/dirinboz/board.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "button.h"
-#include "cros_board_info.h"
-#include "charge_state.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_8042_sharedlib.h"
-#include "ioexpander.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
-
-#include "gpio_list.h"
-
-/*****************************************************************************
- * Retimers
- */
-
-static void retimers_on(void)
-{
-	/* usba retimer power on */
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, retimers_on, HOOK_PRIO_DEFAULT);
-
-static void retimers_off(void)
-{
-	/* usba retimer power off */
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, retimers_off, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * USB-C
- */
-
-/*
- * USB C0 port SBU mux use standalone PI3USB221
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			     bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = pi3usb221_set_mux,
-};
-
-/*
- * Since PI3USB221 is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		/*
-		 * Sensitive only to falling edges; GPIO is configured for both
-		 * because this input may be used for HDMI HPD instead.
-		 */
-		if (!gpio_get_level(signal))
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	case USBC_PORT_C1:
-		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-static void setup_fw_config(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
-
-	/*
-	 * If keyboard is US2(KB_LAYOUT_1), we need translate right ctrl
-	 * to backslash(\|) key.
-	 */
-	if (ec_config_keyboard_layout() == KB_LAYOUT_1)
-		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
-}
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[IOEX_C1_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-#define CHARGING_CURRENT_500mA 500
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	static int thermal_sensor_temp;
-	static int prev_thermal_sensor_temp;
-	static int limit_charge;
-	static int limit_usbc_power;
-	static int limit_usbc_power_backup;
-	enum tcpc_rp_value rp;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return 0;
-
-	temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor_temp);
-
-	if (thermal_sensor_temp > prev_thermal_sensor_temp) {
-		if (thermal_sensor_temp > C_TO_K(63))
-			limit_usbc_power = 1;
-
-		if (thermal_sensor_temp > C_TO_K(58)) {
-			if (curr->state == ST_CHARGE)
-				limit_charge = 1;
-		}
-	} else if (thermal_sensor_temp < prev_thermal_sensor_temp) {
-		if (thermal_sensor_temp < C_TO_K(62))
-			limit_usbc_power = 0;
-
-		if (thermal_sensor_temp < C_TO_K(57)) {
-			if (curr->state == ST_CHARGE)
-				limit_charge = 0;
-		}
-	}
-
-	if (limit_charge)
-		curr->requested_current = CHARGING_CURRENT_500mA;
-	else
-		curr->requested_current = curr->batt.desired_current;
-
-	if (limit_usbc_power != limit_usbc_power_backup) {
-		if (limit_usbc_power == 1)
-			rp = TYPEC_RP_1A5;
-		else
-			rp = TYPEC_RP_3A0;
-
-		ppc_set_vbus_source_current_limit(0, rp);
-		tcpm_select_rp_value(0, rp);
-		pd_update_contract(0);
-		limit_usbc_power_backup = limit_usbc_power;
-	}
-
-	prev_thermal_sensor_temp = thermal_sensor_temp;
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-							uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-							uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-__override struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(63),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(62),
-		}
-	},
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
-		}
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(83),
-		}
-	},
-};
diff --git a/board/dirinboz/board.h b/board/dirinboz/board.h
deleted file mode 100644
index 67e083b51f..0000000000
--- a/board/dirinboz/board.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_DALBOZ
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PORT_ENABLE_DYNAMIC
-
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
-
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* USB-A config */
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-
-/* LED */
-#undef CONFIG_LED_ONOFF_STATES
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-extern int I2C_PORT_BATTERY;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_COS,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * DALBOZ_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	DALBOZ_MB_USBAC = 0,
-};
-
-/**
- * DIRINBOZ_DB_OPT1_USBC
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: PS8719
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8743
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- */
-enum ec_cfg_usb_db_type {
-	DIRINBOZ_DB_OPT1_USBC = 0,
-};
-
-#include "cbi_ec_fw_config.h"
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return 0;
-}
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dirinboz/build.mk b/board/dirinboz/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/dirinboz/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/dirinboz/ec.tasklist b/board/dirinboz/ec.tasklist
deleted file mode 100644
index 3a08ebc972..0000000000
--- a/board/dirinboz/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/dirinboz/gpio.inc b/board/dirinboz/gpio.inc
deleted file mode 100644
index f4de7e567a..0000000000
--- a/board/dirinboz/gpio.inc
+++ /dev/null
@@ -1,134 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-
-/*
- * Dirinboz has 1 DB options.
- * IOEX_C1_NCT3807 is the DB (USB-C1).
- */
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN,	EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,	EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-IOEX(C1_CHARGER_LED_WHITE_DB,EXPIN(IOEX_C1_NCT3807, 1, 0), GPIO_OUT_HIGH)	/* C1 Charge LED White */
-IOEX(C1_CHARGER_LED_AMBER_DB,EXPIN(IOEX_C1_NCT3807, 1, 4), GPIO_OUT_HIGH)	/* C1 Charge LED Amber */
-
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/dirinboz/led.c b/board/dirinboz/led.c
deleted file mode 100644
index 3343d0f924..0000000000
--- a/board/dirinboz/led.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "cros_board_info.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_ON_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-	uint32_t board_ver = 0;
-	int led_batt_on_lvl, led_batt_off_lvl;
-
-	cbi_get_board_version(&board_ver);
-	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
-				 IOEX_C1_CHARGER_LED_AMBER_DB);
-	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
-				 IOEX_C1_CHARGER_LED_WHITE_DB);
-
-	if ((board_ver >= 3) && (port == RIGHT_PORT)) {
-		led_batt_on_lvl = 1;
-		led_batt_off_lvl = 0;
-	} else {
-		led_batt_on_lvl = 0;
-		led_batt_off_lvl = 1;
-	}
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_or_ioex_set_level(white_led, led_batt_on_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
-		break;
-	case LED_AMBER:
-		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_on_lvl);
-		break;
-	case LED_OFF:
-		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Berknip, Berknip is non-power LED
-	 * design, blinking both two side battery white LEDs to indicate
-	 * system suspend with non-charging state.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
-		power_ticks++;
-
-		led_set_color_battery(RIGHT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		return;
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/dirinboz/vif_override.xml b/board/dirinboz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dirinboz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
deleted file mode 100644
index c7099f55d1..0000000000
--- a/board/discovery-stm32f072/board.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* STM32F072-discovery board configuration */
-
-#include "common.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_gpio.h"
-#include "usb_spi.h"
-#include "usb-stream.h"
-#include "util.h"
-
-/******************************************************************************
- * Build GPIO tables and expose a subset of the GPIOs over USB.
- */
-void button_event(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-static enum gpio_signal const usb_gpio_list[] = {
-	GPIO_USER_BUTTON,
-	GPIO_LED_U,
-	GPIO_LED_D,
-	GPIO_LED_L,
-	GPIO_LED_R,
-};
-
-/*
- * This instantiates struct usb_gpio_config const usb_gpio, plus several other
- * variables, all named something beginning with usb_gpio_
- */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
-
-/******************************************************************************
- * Setup USART1 as a loopback device, it just echo's back anything sent to it.
- */
-static struct usart_config const loopback_usart;
-
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
-
-static struct usart_rx_dma const loopback_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH3, 8);
-
-static struct usart_tx_dma const loopback_tx_dma =
-	USART_TX_DMA(STM32_DMAC_CH2, 16);
-
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
-
-/******************************************************************************
- * Forward USART4 as a simple USB serial interface.
- */
-static struct usart_config const forward_usart;
-struct usb_stream_config const forward_usb;
-
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
-
-static struct usart_tx_dma const forward_tx_dma =
-	USART_TX_DMA(STM32_DMAC_CH7, 16);
-
-static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
-
-/******************************************************************************
- * Handle button presses by cycling the LEDs on the board.  Also run a tick
- * handler to cycle them when they are not actively under USB control.
- */
-void button_event(enum gpio_signal signal)
-{
-	static int count;
-
-	gpio_set_level(GPIO_LED_U, (count & 0x03) == 0);
-	gpio_set_level(GPIO_LED_R, (count & 0x03) == 1);
-	gpio_set_level(GPIO_LED_D, (count & 0x03) == 2);
-	gpio_set_level(GPIO_LED_L, (count & 0x03) == 3);
-
-	count++;
-}
-
-void usb_gpio_tick(void)
-{
-	if (usb_gpio.state->set_mask || usb_gpio.state->clear_mask)
-		return;
-
-	button_event(0);
-}
-DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("discovery-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-
-/******************************************************************************
- * Support SPI bridging over USB, this requires usb_spi_board_enable and
- * usb_spi_board_disable to be defined to enable and disable the SPI bridge.
- */
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-void usb_spi_board_enable(struct usb_spi_config const *config)
-{
-	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-
-	/* Set all four SPI pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-void usb_spi_board_disable(struct usb_spi_config const *config)
-{
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-}
-
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USER_BUTTON);
-
-	queue_init(&loopback_queue);
-	queue_init(&usart_to_usb);
-	queue_init(&usb_to_usart);
-	usart_init(&loopback_usart);
-	usart_init(&forward_usart);
-
-	usb_spi_enable(&usb_spi, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/discovery-stm32f072/board.h b/board/discovery-stm32f072/board.h
deleted file mode 100644
index d3f51f6691..0000000000
--- a/board/discovery-stm32f072/board.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32F072-discovery board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Enable USART1,3,4 and USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1
-#define CONFIG_STREAM_USART4
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* the UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x500f
-#define CONFIG_USB_CONSOLE
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
-#define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
-#define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
-
-/* Enable control of GPIOs over USB */
-#define CONFIG_USB_GPIO
-
-/* Enable control of SPI over USB */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI master port */
-
-
-#define CONFIG_USB_SPI
-
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_STREAM_NAME,
-	USB_STR_CONSOLE_NAME,
-
-	USB_STR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/discovery-stm32f072/build.mk b/board/discovery-stm32f072/build.mk
deleted file mode 100644
index c1892335ed..0000000000
--- a/board/discovery-stm32f072/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/discovery-stm32f072/ec.tasklist b/board/discovery-stm32f072/ec.tasklist
deleted file mode 100644
index cc4c2ad42d..0000000000
--- a/board/discovery-stm32f072/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/discovery-stm32f072/gpio.inc b/board/discovery-stm32f072/gpio.inc
deleted file mode 100644
index 65bdd0179b..0000000000
--- a/board/discovery-stm32f072/gpio.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USER_BUTTON, PIN(A, 0), GPIO_INT_FALLING, button_event)
-
-/* Outputs */
-GPIO(LED_U, PIN(C, 6), GPIO_OUT_LOW)
-GPIO(LED_D, PIN(C, 7), GPIO_OUT_LOW)
-GPIO(LED_L, PIN(C, 8), GPIO_OUT_LOW)
-GPIO(LED_R, PIN(C, 9), GPIO_OUT_LOW)
-
-/* Flash SPI interface */
-GPIO(SPI_WP,   PIN(C,  3), GPIO_OUT_HIGH)
-GPIO(SPI_HOLD, PIN(C,  4), GPIO_OUT_HIGH)
-GPIO(SPI_CS,   PIN(B, 12), GPIO_OUT_HIGH)
-
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH, 0)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA09/PA10 */
-ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART,  0) /* USART2: PA14/PA15 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 4, MODULE_USART, 0) /* USART3: PB10/PB11 */
-ALTERNATE(PIN_MASK(C, 0x0C00), 0, MODULE_USART, 0) /* USART4: PC10/PC11 */
diff --git a/board/discovery-stm32f072/openocd-flash.cfg b/board/discovery-stm32f072/openocd-flash.cfg
deleted file mode 100644
index ec32416934..0000000000
--- a/board/discovery-stm32f072/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/stm32f0discovery.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/discovery/board.c b/board/discovery/board.c
deleted file mode 100644
index 0d4cde2e7c..0000000000
--- a/board/discovery/board.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* STM32L-discovery board configuration */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "usart-stm32f0.h"
-#include "usart_rx_dma.h"
-#include "usart_tx_dma.h"
-#include "util.h"
-
-void button_event(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-void button_event(enum gpio_signal signal)
-{
-	static int count;
-
-	gpio_set_level(GPIO_LED_GREEN, ++count & 0x02);
-}
-
-void usb_gpio_tick(void)
-{
-	static int count;
-
-	gpio_set_level(GPIO_LED_BLUE, ++count & 0x01);
-}
-DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************
- * Setup USART2 as a loopback device, it just echo's back anything sent to it.
- */
-static struct usart_config const loopback_usart;
-
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
-
-static struct usart_rx_dma const loopback_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH6, 32);
-
-static struct usart_tx_dma const loopback_tx_dma =
-	USART_TX_DMA(STM32_DMAC_CH7, 16);
-
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart2_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USER_BUTTON);
-
-	usart_init(&loopback_usart);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/discovery/board.h b/board/discovery/board.h
deleted file mode 100644
index ddd2461a56..0000000000
--- a/board/discovery/board.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32L-discovery board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/* Enable USART2 */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART2
-#define CONFIG_CMD_USART_INFO
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK_MSB 3
-#define TIM_CLOCK_LSB 4
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/discovery/build.mk b/board/discovery/build.mk
deleted file mode 100644
index 42f9f9a0fc..0000000000
--- a/board/discovery/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32L152RCT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32l
-CHIP_VARIANT:=stm32l15x
-
-board-y=board.o
diff --git a/board/discovery/ec.tasklist b/board/discovery/ec.tasklist
deleted file mode 100644
index 3822ab3779..0000000000
--- a/board/discovery/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/discovery/gpio.inc b/board/discovery/gpio.inc
deleted file mode 100644
index 821f38ca46..0000000000
--- a/board/discovery/gpio.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USER_BUTTON, PIN(A, 0), GPIO_INT_BOTH, button_event)
-
-/* Outputs */
-GPIO(LED_BLUE,    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(LED_GREEN,   PIN(B, 7), GPIO_OUT_LOW)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART, MODULE_UART,  0) /* USART1: PA09/PA10 */
-ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART, MODULE_USART, 0) /* USART2: PA02/PA03 */
-ALTERNATE(PIN_MASK(B, 0x0C00), GPIO_ALT_USART, MODULE_USART, 0) /* USART3: PB10/PB11 */
diff --git a/board/discovery/openocd-flash.cfg b/board/discovery/openocd-flash.cfg
deleted file mode 100644
index 6426ad5473..0000000000
--- a/board/discovery/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/stm32ldiscovery.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/don b/board/don
deleted file mode 120000
index 7ca3c85ad3..0000000000
--- a/board/don
+++ /dev/null
@@ -1 +0,0 @@
-hammer/
\ No newline at end of file
diff --git a/board/dood/battery.c b/board/dood/battery.c
deleted file mode 100644
index e719ea3151..0000000000
--- a/board/dood/battery.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Dood battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo AP13J7K Battery Information */
-	[BATTERY_SMP_AP13J7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "AP13J7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AC15A3J Battery Information */
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP19A8K Battery Information */
-	[BATTERY_LGC_AP19A8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KTxxxxGxxx",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC KT0030G023 Battery Information */
-	[BATTERY_LGC_G023] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G023",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-
-	/* Simplo PC-VP-BP44 Battery Information */
-	[BATTERY_SMP_PCVPBP144] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "PC-VP-BP144",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 128,	/* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo PC-VP-BP126 Battery Information */
-	[BATTERY_SMP_PCVPBP126] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "PC-VP-BP126",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 128,	/* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo PC-VP-BP136 Battery Information */
-	[BATTERY_SMP_PCVPBP136] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "PC-VP-BP136",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 128,	/* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC15A3J;
diff --git a/board/dood/board.c b/board/dood/board.c
deleted file mode 100644
index cef4c21268..0000000000
--- a/board/dood/board.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* dood board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* Check PPC ID and board version to decide which one ppc is used. */
-static bool support_syv_ppc(void)
-{
-	uint32_t board_version = 0;
-
-	if (cbi_get_board_version(&board_version) != EC_SUCCESS)
-		CPRINTSUSB("Get board version failed.");
-
-	if ((board_version >= 5) && (gpio_get_level(GPIO_PPC_ID)))
-		return true;
-
-	return false;
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		if (support_syv_ppc())
-			syv682x_interrupt(0);
-		else
-			nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		if (support_syv_ppc())
-			syv682x_interrupt(1);
-		else
-			nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	/* Default supports convertible */
-	return true;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX)
-		return;
-	sku_id = val;
-	CPRINTSUSB("SKU: %d", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate_late(void)
-{
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static void board_setup_ppc(void)
-{
-	if (!support_syv_ppc())
-		return;
-
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
-
-	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
-	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
-}
-DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
-
-	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
-}
diff --git a/board/dood/board.h b/board/dood/board.h
deleted file mode 100644
index dcb5c93005..0000000000
--- a/board/dood/board.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dood board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LED_COMMON
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* Motion Sense Task Events */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* Additional PPC second source */
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#undef CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-
-
-#ifndef __ASSEMBLER__
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_SMP_AP13J7K,
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_LGC_AP19A8K,
-	BATTERY_LGC_G023,
-	BATTERY_SMP_PCVPBP144,
-	BATTERY_SMP_PCVPBP126,
-	BATTERY_SMP_PCVPBP136,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dood/build.mk b/board/dood/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/dood/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/dood/ec.tasklist b/board/dood/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/dood/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/dood/gpio.inc b/board/dood/gpio.inc
deleted file mode 100644
index 961acf8ee0..0000000000
--- a/board/dood/gpio.inc
+++ /dev/null
@@ -1,185 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT, 	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)            /* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,         PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
-
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L, 	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_AMBER_L,	 PIN(C, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)	/* LED_1_L */
-GPIO(BAT_LED_WHITE_L,	 PIN(C, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)	/* LED_2_L */
-GPIO(LED_3_L,		 PIN(D, 7), GPIO_OUT_HIGH)
-
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	PIN(6, 2), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		PIN(9, 4), GPIO_ODR_HIGH)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(PPC_ID,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_DOWN)	/* PPC ID Pin */
-
-/* Unused Pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(WFCAM_VSYNC,		PIN(0, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/dood/led.c b/board/dood/led.c
deleted file mode 100644
index 966f3d7a72..0000000000
--- a/board/dood/led.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Dood
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Dood: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/dood/vif_override.xml b/board/dood/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dood/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dooly/board.c b/board/dooly/board.c
deleted file mode 100644
index b28f3d41b8..0000000000
--- a/board/dooly/board.c
+++ /dev/null
@@ -1,1187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dooly board-specific configuration */
-
-#include "accelgyro.h"
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/als_tcs3400.h"
-#include "driver/ina3221.h"
-#include "driver/led/oz554.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Sensors */
-static struct mutex g_accel_mutex;
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	/*
-	 * TODO: calculate the actual coefficients and scaling factors
-	 */
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.1),
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-const mat33_fp_t screen_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[SCREEN_ACCEL] = {
-		.name = "Screen Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-		.rot_standard_ref = &screen_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-	[RGB_ALS] = {
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-/* On ECs without an FPU, the fp_t type is backed by a 32-bit fixed precision
- * representation that can only store values in the range [-32K, +32K]. Some
- * intermediary values produced in tcs3400_translate_to_xyz() do not fit in
- * that range, so we define and use a 64-bit fixed representation instead.
- */
-typedef int64_t fp64_t;
-#define INT_TO_FP64(x)   ((int64_t)(x) << 32)
-#define FP64_TO_INT(x)   ((x) >> 32)
-#define FLOAT_TO_FP64(x) ((int64_t)((x) * (float)(1LL << 32)))
-
-__override void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
-					 int32_t *crgb_data, int32_t *xyz_data)
-{
-	struct tcs_saturation_t *sat_p =
-		&(TCS3400_RGB_DRV_DATA(s+1)->saturation);
-
-	int32_t cur_gain = (1 << (2 * sat_p->again));
-	int32_t integration_time_us =
-		tcs3400_get_integration_time(sat_p->atime);
-
-	fp64_t c_coeff, r_coeff, g_coeff, b_coeff;
-	fp64_t result;
-
-	/* Use different coefficients based on n_interval = (G+B)/C */
-	fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) +
-			INT_TO_FP64(crgb_data[3]);
-	fp64_t n_interval = gb_sum / MAX(crgb_data[0], 1);
-
-	if (n_interval < FLOAT_TO_FP64(0.692)) {
-		const float scale = 799.797;
-
-		c_coeff = FLOAT_TO_FP64(0.009  * scale);
-		r_coeff = FLOAT_TO_FP64(0.056  * scale);
-		g_coeff = FLOAT_TO_FP64(2.735  * scale);
-		b_coeff = FLOAT_TO_FP64(-1.903 * scale);
-	} else if (n_interval < FLOAT_TO_FP64(1.012)) {
-		const float scale = 801.347;
-
-		c_coeff = FLOAT_TO_FP64(0.202  * scale);
-		r_coeff = FLOAT_TO_FP64(-1.1   * scale);
-		g_coeff = FLOAT_TO_FP64(8.692  * scale);
-		b_coeff = FLOAT_TO_FP64(-7.068 * scale);
-	} else {
-		const float scale = 795.574;
-
-		c_coeff = FLOAT_TO_FP64(-0.661 * scale);
-		r_coeff = FLOAT_TO_FP64(1.334  * scale);
-		g_coeff = FLOAT_TO_FP64(1.095  * scale);
-		b_coeff = FLOAT_TO_FP64(-1.821 * scale);
-	}
-
-	/* Multiply each channel by the coefficient and compute the sum.
-	 * Note: int * fp64_t = fp64_t and fp64_t + fp64_t = fp64_t.
-	 */
-	result = crgb_data[0] * c_coeff +
-		 crgb_data[1] * r_coeff +
-		 crgb_data[2] * g_coeff +
-		 crgb_data[3] * b_coeff;
-
-	/* Adjust for exposure time and sensor gain.
-	 * Note: fp64_t / int = fp64_t.
-	 */
-	result /= MAX(integration_time_us * cur_gain / 1000, 1);
-
-	/* Some C/R/G/B coefficients are negative, so the result could also be
-	 * negative and must be clamped at zero.
-	 *
-	 * The value of xyz_data[1] is stored in a 16 bit integer later on, so
-	 * it must be clamped at INT16_MAX.
-	 */
-	xyz_data[1] = MIN(MAX(FP64_TO_INT(result), 0), INT16_MAX);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_TCPC_0);
-		break;
-	case GPIO_USB_C1_TCPPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_TCPC_1);
-		break;
-	default:
-		break;
-	}
-}
-
-int ppc_get_alert_status(int port)
-{
-	int status = 0;
-
-	switch (port) {
-	case USB_PD_PORT_TCPC_0:
-		status = gpio_get_level(GPIO_USB_C0_TCPPC_INT_ODL) == 0;
-		break;
-	case USB_PD_PORT_TCPC_1:
-		status = gpio_get_level(GPIO_USB_C1_TCPPC_INT_ODL) == 0;
-		break;
-	default:
-		break;
-	}
-	return status;
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USB_PD_PORT_TCPC_0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USB_PD_PORT_TCPC_1);
-		break;
-	default:
-		break;
-	}
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int level;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_1].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-/* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Blink alert if insufficient power per system_can_boot_ap(). */
-	int insufficient_power =
-		(charge_ma * charge_mv) <
-		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
-	led_alert(insufficient_power);
-}
-
-static uint8_t usbc_0_overcurrent;
-static uint8_t usbc_1_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (usbc_0_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	if (usbc_1_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-/*
- * Barrel jack power supply handling
- *
- * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
- * barrel jack is connected, and the USB-C port can bring the EC up fine in
- * dead-battery mode. Both the USB-C and barrel jack switches do reverse
- * protection, so we're safe to turn one on then the other off- but we should
- * only do that if the system is off since it might still brown out.
- */
-
-/*
- * Barrel-jack power adapter ratings.
- */
-static const struct {
-	int voltage;
-	int current;
-} bj_power[] = {
-	{ /* 0 - 65W (also default) */
-	.voltage = 19500,
-	.current = 3200
-	},
-	{ /* 1 - 90W */
-	.voltage = 19500,
-	.current = 4600
-	},
-};
-
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
-/* Debounced connection state of the barrel jack */
-static int8_t adp_connected = -1;
-static void adp_connect_deferred(void)
-{
-	struct charge_port_info pi = { 0 };
-	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Debounce */
-	if (connected == adp_connected)
-		return;
-	if (connected) {
-		unsigned int bj = ec_config_get_bj_power();
-
-		pi.voltage = bj_power[bj].voltage;
-		pi.current = bj_power[bj].current;
-	}
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &pi);
-	adp_connected = connected;
-}
-DECLARE_DEFERRED(adp_connect_deferred);
-
-/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
-void adp_connect_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
-}
-
-static void adp_state_init(void)
-{
-	/*
-	 * Initialize all charge suppliers to 0. The charge manager waits until
-	 * all ports have reported in before doing anything.
-	 */
-	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
-		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
-			charge_manager_update_charge(j, i, NULL);
-	}
-
-	/* Report charge state from the barrel jack. */
-	adp_connect_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-};
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"ppc1",    I2C_PORT_PPC1,    400, GPIO_I2C2_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C4_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {
-		.name = "PP3300",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 2400,
-	.rpm_max = 4300,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(78),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(41),
-	.temp_fan_max = C_TO_K(72),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_ALS_GSENSOR_INT_ODL);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	/*
-	 * Workaround to restore VBUS on PPC.
-	 * PP1 is sourced from PP5000_A, and when the CPU shuts down and
-	 * this rail drops, the PPC will internally turn off PP1_EN.
-	 * When the CPU starts again, and the rail is restored, the PPC
-	 * does not turn PP1_EN on again, causing VBUS to stay turned off.
-	 * The workaround is to check whether the PPC is sourcing VBUS, and
-	 * if so, make sure it is enabled.
-	 */
-	if (ppc_is_sourcing_vbus(USB_PD_PORT_TCPC_0))
-		ppc_vbus_source_enable(USB_PD_PORT_TCPC_0, 1);
-	if (ppc_is_sourcing_vbus(USB_PD_PORT_TCPC_1))
-		ppc_vbus_source_enable(USB_PD_PORT_TCPC_1, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-/* Power Delivery and charging functions */
-static void board_tcpc_init(void)
-{
-	/*
-	 * Reset TCPC if we have had a system reset.
-	 * With EFSv2, it is possible to be in RW without
-	 * having reset the TCPC.
-	 */
-	if (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON)
-		board_reset_pd_mcu();
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	/* Enable other overcurrent interrupts */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
-
-}
-/* Make sure this is called after fw_config is initialised */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-void board_reset_pd_mcu(void)
-{
-	int level0 = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-			TCPC_FLAGS_RESET_ACTIVE_HIGH);
-	int level1 = !!(tcpc_config[USB_PD_PORT_TCPC_1].flags &
-			TCPC_FLAGS_RESET_ACTIVE_HIGH);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, level0);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST, level1);
-	msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, !level0);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST, !level1);
-	if (BOARD_TCPC_C0_RESET_POST_DELAY)
-		msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
-}
-
-int board_set_active_charge_port(int port)
-{
-	CPRINTS("Requested charge port change to %d", port);
-
-	/*
-	 * The charge manager may ask us to switch to no charger if we're
-	 * running off USB-C only but upstream doesn't support PD. It requires
-	 * that we accept this switch otherwise it triggers an assert and EC
-	 * reset; it's not possible to boot the AP anyway, but we want to avoid
-	 * resetting the EC so we can continue to do the "low power" LED blink.
-	 */
-	if (port == CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	if (port < 0 || CHARGE_PORT_COUNT <= port)
-		return EC_ERROR_INVAL;
-
-	if (port == charge_manager_get_active_charge_port())
-		return EC_SUCCESS;
-
-	/* Don't charge from a source port */
-	if (board_vbus_source_enabled(port))
-		return EC_ERROR_INVAL;
-
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		int bj_active, bj_requested;
-
-		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
-			/* Change is only permitted while the system is off */
-			return EC_ERROR_INVAL;
-
-		/*
-		 * Current setting is no charge port but the AP is on, so the
-		 * charge manager is out of sync (probably because we're
-		 * reinitializing after sysjump). Reject requests that aren't
-		 * in sync with our outputs.
-		 */
-		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
-		bj_requested = port == CHARGE_PORT_BARRELJACK;
-		if (bj_active != bj_requested)
-			return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charger p%d", port);
-
-	switch (port) {
-	case CHARGE_PORT_TYPEC0:
-	case CHARGE_PORT_TYPEC1:
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
-		break;
-	case CHARGE_PORT_BARRELJACK:
-		/* Make sure BJ adapter is sourcing power */
-		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_L))
-			return EC_ERROR_INVAL;
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USB_PD_PORT_TCPC_0:
-		usbc_0_overcurrent = is_overcurrented;
-		break;
-	case USB_PD_PORT_TCPC_1:
-		usbc_1_overcurrent = is_overcurrented;
-		break;
-	default:
-		return;
-	}
-	update_5v_usage();
-}
-
-int extpower_is_present(void)
-{
-	return adp_connected;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	return 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-}
-
-unsigned int ec_config_get_bj_power(void)
-{
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
-	/* Out of range value defaults to 0 */
-	if (bj >= ARRAY_SIZE(bj_power))
-		bj = 0;
-	return bj;
-}
-
-unsigned int ec_config_get_thermal_solution(void)
-{
-	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
-}
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-/* PROCHOT_DEFER_OFF is to extend CPU prochot long enough
- * to pass safety requirement 30 * 2ms = 60 ms
- */
-#define PROCHOT_DEFER_OFF		30
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	static uint32_t history[POWER_READINGS];
-	static uint8_t index;
-	static uint8_t prochot_linger;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-		/*
-		 * Clear the first entry of the power table so that
-		 * it is re-initilalised when the CPU starts.
-		 */
-		history[0] = 0;
-	} else {
-		int32_t charger_mw;
-
-		delay = POWER_DELAY_MS * MSEC;
-		/*
-		 * Get current charger limit (in mw).
-		 * If not configured yet, skip.
-		 */
-		charger_mw = charge_manager_get_power_limit_uw() / 1000;
-		if (charger_mw != 0) {
-			int32_t gap, total, max, power;
-			int i;
-
-			/*
-			 * Read power usage.
-			 */
-			power = (adc_read_channel(ADC_VBUS) *
-				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
-			/* Init power table */
-			if (history[0] == 0) {
-				for (i = 0; i < POWER_READINGS; i++)
-					history[i] = power;
-			}
-			/*
-			 * Update the power readings and
-			 * calculate the average and max.
-			 */
-			history[index] = power;
-			index = (index + 1) % POWER_READINGS;
-			total = 0;
-			max = history[0];
-			for (i = 0; i < POWER_READINGS; i++) {
-				total += history[i];
-				if (history[i] > max)
-					max = history[i];
-			}
-			/*
-			 * For Type-C power supplies, there is
-			 * less tolerance for exceeding the rating,
-			 * so use the max power that has been measured
-			 * over the measuring period.
-			 * For barrel-jack supplies, the rating can be
-			 * exceeded briefly, so use the average.
-			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
-				power = max;
-			else
-				power = total / POWER_READINGS;
-			/*
-			 * Calculate gap, and if negative, power
-			 * demand is exceeding configured power budget, so
-			 * throttling is required to reduce the demand.
-			 */
-			gap = charger_mw - power;
-			/*
-			 * Limiting type-A power.
-			 */
-			if (gap <= 0) {
-				new_state |= THROT_TYPE_A;
-				headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-				if (!(current_state & THROT_TYPE_A))
-					gap += POWER_GAIN_TYPE_A;
-			}
-			/*
-			 * If the type-C port is sourcing power,
-			 * check whether it should be throttled.
-			 * TODO(amcrae): selectively disable ports.
-			 */
-			if (gap <= 0 && (ppc_is_sourcing_vbus(0) ||
-					 ppc_is_sourcing_vbus(1))) {
-				new_state |= THROT_TYPE_C;
-				headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-				if (!(current_state & THROT_TYPE_C))
-					gap += POWER_GAIN_TYPE_C * 2;
-			}
-			/*
-			 * As a last resort, turn on PROCHOT to
-			 * throttle the CPU.
-			 */
-			if (gap <= 0) {
-				prochot_linger = 0;
-				new_state |= THROT_PROCHOT;
-			} else if (prochot_linger < PROCHOT_DEFER_OFF) {
-				/*
-				 * Do not turn off PROCHOT immediately.
-				 */
-				prochot_linger++;
-				new_state |= THROT_PROCHOT;
-			}
-		}
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) ||
-		       usbc_0_overcurrent || usbc_1_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
-
-		ppc_set_vbus_source_current_limit(0, rp);
-		tcpm_select_rp_value(0, rp);
-		pd_update_contract(0);
-
-		ppc_set_vbus_source_current_limit(1, rp);
-		tcpm_select_rp_value(1, rp);
-		pd_update_contract(1);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
-
-__override void oz554_board_init(void)
-{
-	int pin_status = 0;
-
-	pin_status |= gpio_get_level(GPIO_PANEL_ID0) << 0;
-	pin_status |= gpio_get_level(GPIO_PANEL_ID1) << 1;
-
-	switch (pin_status) {
-	case 0x00:
-		CPRINTS("PANEL_HAN01.10A");
-		oz554_set_config(0, 0xF3);
-		oz554_set_config(2, 0x4C);
-		oz554_set_config(5, 0xB7);
-		break;
-	case 0x02:
-		CPRINTS("PANEL_WF9_SSA2");
-		oz554_set_config(0, 0xF3);
-		oz554_set_config(2, 0x55);
-		oz554_set_config(5, 0x87);
-		break;
-	default:
-		CPRINTS("PANEL UNKNOWN");
-		break;
-	}
-}
diff --git a/board/dooly/board.h b/board/dooly/board.h
deleted file mode 100644
index 927037e357..0000000000
--- a/board/dooly/board.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dooly board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/*
- * By default, enable all console messages except HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* Sensor */
-#define CONFIG_ACCEL_INTERRUPTS
-/*
- * Reduce maximal sensor speed: lid accelerometer is not interrupt driven,
- * so EC does not timestamp sensor events as accurately as interrupt
- * driven ones.
- */
-#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
-#define CONFIG_CMD_ACCEL_INFO
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* BMA253 accelerometer */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_CMD_ACCELS
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT	1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS))
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-/* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 2
-
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
-
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-/* Less than this much blocks AP power-on. */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 30000
-#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
-
-/* USB type C */
-#define CONFIG_USB_PD_TCPMV2 /* Use TCPMv2 */
-#define CONFIG_USB_PD_REV30 /* Enable PD 3.0 functionality */
-#define CONFIG_USB_PD_DECODE_SOP
-#undef CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-#define USB_PD_PORT_TCPC_0	0
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define USB_PD_PORT_TCPC_1	1
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are two ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_SENSORS	NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_PPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT7_0
-
-/*
- * LED backlight controller
- */
-#define CONFIG_LED_DRIVER_OZ554
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_TYPEC1,
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	SCREEN_ACCEL = 0,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields - keep in sync with Puff.
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit) (not used).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-unsigned int ec_config_get_bj_power(void);
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dooly/build.mk b/board/dooly/build.mk
deleted file mode 100644
index 0f55c45f77..0000000000
--- a/board/dooly/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-board-y+=led.o
diff --git a/board/dooly/ec.tasklist b/board/dooly/ec.tasklist
deleted file mode 100644
index 72b81be8d8..0000000000
--- a/board/dooly/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/dooly/gpio.inc b/board/dooly/gpio.inc
deleted file mode 100644
index d4b06d1443..0000000000
--- a/board/dooly/gpio.inc
+++ /dev/null
@@ -1,179 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Other interrupts */
-GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPPC_INT_ODL, PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(B, 1), GPIO_INT_RISING, backlight_enable_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(ALS_GSENSOR_INT_ODL, PIN(9, 6), GPIO_INT_FALLING, tcs3400_interrupt)
-
-/*
- * Directly connected recovery button.
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
-
-/* Port power control interrupts */
-GPIO_INT(USB_A0_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(8, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A0_STATUS_L,          PIN(6, 1), GPIO_INPUT)  /* Marked as A2 */
-GPIO(USB_A1_STATUS_L,          PIN(C, 7), GPIO_INPUT)  /* Marked as A3 */
-
-/* USB type C */
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST,          PIN(D, 2), GPIO_OUT_LOW)
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_TCPPC_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_TCPPC_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_USB_C1_TCPC_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_TCPC_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-/*
- * Also used for LCM backlight.
- */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                  /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                  /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3A), 0, MODULE_ADC, 0)                  /* ADC0 - ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* PANEL ID */
-GPIO(PANEL_ID0,			PIN(0, 2), GPIO_INPUT)
-GPIO(PANEL_ID1,			PIN(C, 6), GPIO_INPUT)
-
-/* EDID write protect control */
-GPIO(EC_EDID_WP_DISABLE_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* LOW to disable EDID WP */
-
-/* Unused pins */
-UNUSED(PIN(9, 5))						/* H10 TP54 */
-UNUSED(PIN(4, 0))						/* E4  TP56 */
-UNUSED(PIN(5, 0))						/* G4 NC */
-UNUSED(PIN(0, 7))						/* E8  TP991 */
-UNUSED(PIN(0, 6))						/* B10 TP992 */
-UNUSED(PIN(D, 6))						/* F6 */
-UNUSED(PIN(3, 2))						/* E5 */
-UNUSED(PIN(B, 0))						/* G8  TP49 */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(E, 2))						/* B8  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(0, 0))						/* D11 NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/dooly/led.c b/board/dooly/led.c
deleted file mode 100644
index fefa8908fe..0000000000
--- a/board/dooly/led.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-	LED_AMBER,
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		white = 1;
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec. */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIGURE_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIGURE_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task. */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-	pwm_enable(PWM_CH_LED_RED, 1);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/dooly/usb_pd_policy.c b/board/dooly/usb_pd_policy.c
deleted file mode 100644
index a8d89130c2..0000000000
--- a/board/dooly/usb_pd_policy.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Dooly boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000_A);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	/* Ignore non-PD ports (the barrel jack). */
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return 0;
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/board/dooly/vif_override.xml b/board/dooly/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dooly/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/dratini/battery.c b/board/dratini/battery.c
deleted file mode 100644
index 77c84cd973..0000000000
--- a/board/dratini/battery.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-
-/*
- * Battery info for all Dratini/Dragonair battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Coslight 996QA182H Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-13-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* LGC MPPHPPBC031C Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "333-42-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS;
diff --git a/board/dratini/board.c b/board/dratini/board.c
deleted file mode 100644
index 53fbe4b3d5..0000000000
--- a/board/dratini/board.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void check_reboot_deferred(void);
-DECLARE_DEFERRED(check_reboot_deferred);
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void control_mst_power(void)
-{
-	baseboard_mst_enable_control(MST_HDMI,
-				     gpio_get_level(GPIO_HDMI_CONN_HPD));
-}
-DECLARE_DEFERRED(control_mst_power);
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * When the HPD goes high, enable the MST hub right away,
-	 * but debounce the low signal for 2 seconds to avoid transient low
-	 * pulses on the HPD signal.
-	 */
-	if (gpio_get_level(signal))
-		hook_call_deferred(&control_mst_power_data, 0);
-	else
-		hook_call_deferred(&control_mst_power_data, 2 * SECOND);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, enough for lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 6500,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5V Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Dratini Temperature sensors */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(70),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(70),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-/*
- * Returns true for boards that are convertible into tablet mode, and
- * false for clamshells.
- */
-bool board_is_convertible(void)
-{
-	uint8_t sku_id = get_board_sku();
-
-	/*
-	 * Dragonair (SKU 21 ,22, 23 and 24) is a convertible.
-	 * Dratini is not.
-	 * Unprovisioned SKU 255.
-	 */
-	return sku_id == 21 || sku_id == 22 || sku_id == 23 ||
-		sku_id == 24 || sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void anx7447_set_aux_switch(void)
-{
-	const int port = USB_PD_PORT_TCPC_0;
-
-	/* Debounce */
-	if (gpio_get_level(GPIO_CCD_MODE_ODL))
-		return;
-
-	CPRINTS("C%d: AUX_SW_SEL=0x%x", port, 0xc);
-	if (tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc))
-		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
-}
-DECLARE_DEFERRED(anx7447_set_aux_switch);
-
-void ccd_mode_isr(enum gpio_signal signal)
-{
-	/* Wait 2 seconds until all mux setting is done by PD task */
-	hook_call_deferred(&anx7447_set_aux_switch_data, 2 * SECOND);
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-
-	/*
-	 * If HDMI is plugged in at boot, the interrupt may have been missed,
-	 * so check if the MST hub needs to be powered now.
-	 */
-	control_mst_power();
-
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-
-	/* Trigger once to set mux in case CCD cable is already connected. */
-	ccd_mode_isr(GPIO_CCD_MODE_ODL);
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-bool board_has_kb_backlight(void)
-{
-	uint8_t sku_id = get_board_sku();
-	/*
-	 * SKUs have keyboard backlight.
-	 * Dratini: 2, 3, 5, 8
-	 * Dragonair: 22, 24
-	 * Unprovisioned: 255
-	 */
-	return sku_id == 2 || sku_id == 3 || sku_id == 5 || sku_id == 8 ||
-		sku_id == 22 || sku_id == 24 || sku_id == 255;
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	if (board_has_kb_backlight())
-		return flags0;
-	else
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-/* Disable HDMI power while AP is suspended / off */
-static void disable_hdmi(void)
-{
-	gpio_set_level(GPIO_EN_HDMI, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, disable_hdmi, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_hdmi, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI power while AP is active */
-static void enable_hdmi(void)
-{
-	gpio_set_level(GPIO_EN_HDMI, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_hdmi, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enable_hdmi, HOOK_PRIO_DEFAULT);
-
-void all_sys_pgood_check_reboot(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC);
-}
-
-__override void board_chipset_forced_shutdown(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, -1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
-
-static void check_reboot_deferred(void)
-{
-	if (!gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD))
-		system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED);
-}
diff --git a/board/dratini/board.h b/board/dratini/board.h
deleted file mode 100644
index e75865e376..0000000000
--- a/board/dratini/board.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/*
- * Dratini's battery takes several seconds to come back out of its disconnect
- * state (~4 seconds, but give it 6 for margin).
- */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 10
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SIMPLO_COS,
-	BATTERY_LGC,
-	BATTERY_TYPE_COUNT,
-};
-
-bool board_is_convertible(void);
-
-void ccd_mode_isr(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dratini/build.mk b/board/dratini/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/dratini/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/dratini/ec.tasklist b/board/dratini/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/dratini/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/dratini/gpio.inc b/board/dratini/gpio.inc
deleted file mode 100644
index c242919a89..0000000000
--- a/board/dratini/gpio.inc
+++ /dev/null
@@ -1,147 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(C, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* CCD mode line*/
-GPIO_INT(CCD_MODE_ODL,         PIN(E, 5), GPIO_INT_FALLING, ccd_mode_isr)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_AMBER_C0_L,           PIN(C, 4), GPIO_OUT_HIGH)        /* Amber C0 port */
-GPIO(LED_WHITE_C0_L,           PIN(C, 3), GPIO_OUT_HIGH)        /* White C0 port */
-GPIO(LED_AMBER_C1_L,           PIN(4, 2), GPIO_OUT_HIGH)        /* Amber C1 port */
-GPIO(LED_WHITE_C1_L,           PIN(C, 6), GPIO_OUT_HIGH)        /* White C1 port */
-GPIO(PWR_LED_WHITE_L,          PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EN_HDMI,                  PIN(B, 0), GPIO_OUT_LOW)         /* HDMI power rail */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)                             /* ADC0-2 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/dratini/led.c b/board/dratini/led.c
deleted file mode 100644
index 5cc256b2c5..0000000000
--- a/board/dratini/led.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Dratini/Dragonair
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_ON_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == 0 ? GPIO_LED_AMBER_C0_L : GPIO_LED_AMBER_C1_L);
-	white_led = (port == 0 ? GPIO_LED_WHITE_C0_L : GPIO_LED_WHITE_C1_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(1, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(1, LED_AMBER);
-		else
-			led_set_color_battery(1, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(0, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(0, LED_AMBER);
-		else
-			led_set_color_battery(0, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(1, (port == 1) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Dratini, Dratini is non-power LED
-	 * design, blinking both two side battery white LEDs to indicate
-	 * system suspend with non-charging state.
-	 */
-	if (!board_is_convertible()) {
-		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
-			power_ticks++;
-
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/dratini/vif_override.xml b/board/dratini/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/dratini/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/drawcia/battery.c b/board/drawcia/battery.c
deleted file mode 100644
index 62d6e95947..0000000000
--- a/board/drawcia/battery.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all drawcia battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack HIGHPOWER Battery Information */
-	[BATTERY_DYNAPACK_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2D-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack BYD Battery Information */
-	[BATTERY_DYNAPACK_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2E-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo CosMX Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS_2] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* ATL GB-S20-4473A9-01H&020H Battery Information
-	 * Gauge IC : RAJ240045
-	 */
-	[BATTERY_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "313-B7-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/drawcia/board.c b/board/drawcia/board.c
deleted file mode 100644
index 80f93e4d1d..0000000000
--- a/board/drawcia/board.c
+++ /dev/null
@@ -1,722 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Drawcia board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-uint32_t board_version;
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-__override void board_process_pd_alert(int port)
-{
-	/*
-	 * PD_INT task will process this alert, and that task is only needed on
-	 * C1.
-	 */
-	if (port != 1)
-		return;
-
-	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return;
-
-	sm5803_handle_interrupt(port);
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
-		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	else
-		button_interrupt(s);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-	} else {
-		/* Select AUX option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 1);
-	}
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/* Store board version for use in determining charge limits */
-	cbi_get_board_version(&board_version);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	if (board_get_charger_chip_count() > 1) {
-		/* Charger on the sub-board will be a push-pull GPIO */
-		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-static void board_suspend(void)
-{
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-
-	if (board_get_charger_chip_count() > 1) {
-		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CHARGER_NUM;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/* Limit C1 on board version 0 to 2.0 A */
-	if ((board_version == 0) && (port == 1))
-		icl = MIN(icl, 2000);
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	charger_set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 20;
-
-	*ki = 3;
-	*ki_div = 125;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/drawcia/board.h b/board/drawcia/board.h
deleted file mode 100644
index 96e6b3f14d..0000000000
--- a/board/drawcia/board.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Drawcia board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-#undef GPIO_VOLUME_UP_L
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_PWM_KBLIGHT
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_HIGHPOWER,
-	BATTERY_DYNAPACK_BYD,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_COS_2,
-	BATTERY_ATL,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/drawcia/build.mk b/board/drawcia/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/drawcia/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/drawcia/cbi_ssfc.c b/board/drawcia/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/drawcia/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/drawcia/cbi_ssfc.h b/board/drawcia/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/drawcia/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/drawcia/ec.tasklist b/board/drawcia/ec.tasklist
deleted file mode 100644
index 2edf48ee05..0000000000
--- a/board/drawcia/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/drawcia/gpio.inc b/board/drawcia/gpio.inc
deleted file mode 100644
index 2bfbb9c91b..0000000000
--- a/board/drawcia/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* LED */
-GPIO(BAT_LED_AMBER_L,	 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/drawcia/led.c b/board/drawcia/led.c
deleted file mode 100644
index 68242180fa..0000000000
--- a/board/drawcia/led.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Drawcia specific LED settings. */
-
-#include "cbi_fw_config.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	case EC_LED_ID_POWER_LED:
-		rv = led_set_color_power(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LED for Drawlet/Drawman, Drawlet/Drawman
-	 * don't have power LED, blinking battery white LED to indicate
-	 * system suspend without charging.
-	 */
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/drawcia/usb_pd_policy.c b/board/drawcia/usb_pd_policy.c
deleted file mode 100644
index 7046e25d6c..0000000000
--- a/board/drawcia/usb_pd_policy.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	prev_en = charger_is_sourcing_otg_power(port);
-
-	/* Disable Vbus */
-	charger_enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable sinking */
-	rv = sm5803_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	charger_enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return sm5803_is_vbus_present(port);
-}
diff --git a/board/drawcia/vif_override.xml b/board/drawcia/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/drawcia/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/driblee/battery.c b/board/driblee/battery.c
deleted file mode 100644
index ff67e823ff..0000000000
--- a/board/driblee/battery.c
+++ /dev/null
@@ -1,634 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for lalala battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* BYD Battery Information */
-	[BATTERY_BYD_1VX1H] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL 1VX1H",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD Battery Information */
-	[BATTERY_BYD_YT39X] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL YT39X",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD Battery Information */
-	[BATTERY_BYD_X0Y5M] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "DELL X0Y5M",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x043,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC_FDRHM] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.65",
-			.device_name = "DELL FDRHM",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11460,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC_8GHCX] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.65",
-			.device_name = "DELL 8GHCX",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11460,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-
-	/* SWD-ATL Battery Information */
-	[BATTERY_SWD_ATL_WJPC4] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.618",
-			.device_name = "DELL WJPC4",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-ATL Battery Information */
-	[BATTERY_SWD_ATL_CTGKT] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.618",
-			.device_name = "DELL CTGKT",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-COS Battery Information */
-	[BATTERY_SWD_COS_WJPC4] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-COS3.634",
-			.device_name = "DELL WJPC4",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SWD-COS Battery Information */
-	[BATTERY_SWD_COS_CTGKT] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-COS3.634",
-			.device_name = "DELL CTGKT",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_VM732] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL VM732",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_26JGK] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL 26JGK",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-ATL Battery Information */
-	[BATTERY_SMP_ATL_RF9H3] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL-3.61",
-			.device_name = "DELL RF9H3",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x43,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_VM732] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL VM732",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_26JGK] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL 26JGK",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x0,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-	/* SMP-COS Battery Information */
-	[BATTERY_SMP_COS_RF9H3] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.device_name = "DELL RF9H3",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr       = 0x43,
-				.reg_mask       = 0x0001,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,    /* mV */
-			.voltage_normal       = 11400,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,       /* mA */
-			.start_charging_min_c = -3,
-			.start_charging_max_c = 50,
-			.charging_min_c       = -3,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -5,
-			.discharging_max_c    = 70,
-		},
-	},
-
-	/* BYD 16DPHYMD Battery Information */
-	[BATTERY_BYD16] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD-BYD3.685",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC3] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.553",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO Battery Information */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI3.72",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO-LISHEN 7T0D3YMD Battery Information */
-	[BATTERY_SIMPLO_LS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LS3.66",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
diff --git a/board/driblee/board.c b/board/driblee/board.c
deleted file mode 100644
index d40ebe25a6..0000000000
--- a/board/driblee/board.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/retimer/ps8802.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_8042.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-static uint8_t new_adc_key_state;
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
-
-/* Keyboard scan setting */
-static const struct ec_response_keybd_config driblee_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &driblee_keybd;
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	set_5v_gpio(!!enable);
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-		tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize THERMAL */
-	setup_thermal();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
-		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 0);
-		gpio_set_level(GPIO_HDMI_PP3300_EN, 1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_hdmi() == HDMI_PRESENT) {
-		gpio_set_level(GPIO_EC_HDMI_EN_ODL, 1);
-		gpio_set_level(GPIO_HDMI_PP3300_EN, 0);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-int adc_to_physical_value(enum gpio_signal gpio)
-{
-	if (gpio == GPIO_VOLUME_UP_L)
-		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
-	else if (gpio == GPIO_VOLUME_DOWN_L)
-		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
-
-	CPRINTS("Not a volume up or down key");
-	return 0;
-}
-
-int button_is_adc_detected(enum gpio_signal gpio)
-{
-	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
-}
-
-static void board_extpower(void)
-{
-	int extpower_present;
-
-	if (pd_is_connected(0))
-		extpower_present = extpower_is_present();
-	else
-		extpower_present = 0;
-
-	gpio_set_level(GPIO_EC_ACOK_OTG, extpower_present);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
diff --git a/board/driblee/board.h b/board/driblee/board.h
deleted file mode 100644
index 9d4ce3b6f2..0000000000
--- a/board/driblee/board.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KEEBY_EC_NPCX797FC
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-#define CONFIG_MATH_UTIL
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_EC_HDMI_EN_ODL GPIO_EC_I2C_SBU_USB_C1_SCL
-#define GPIO_HDMI_PP3300_EN GPIO_SUB_USB_C1_INT_ODL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_PS8802
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-
-/******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Volume Button feature */
-#define CONFIG_ADC_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_BYD_1VX1H,
-	BATTERY_BYD_YT39X,
-	BATTERY_BYD_X0Y5M,
-	BATTERY_LGC_FDRHM,
-	BATTERY_LGC_8GHCX,
-	BATTERY_SWD_ATL_WJPC4,
-	BATTERY_SWD_ATL_CTGKT,
-	BATTERY_SWD_COS_WJPC4,
-	BATTERY_SWD_COS_CTGKT,
-	BATTERY_SMP_ATL_VM732,
-	BATTERY_SMP_ATL_26JGK,
-	BATTERY_SMP_ATL_RF9H3,
-	BATTERY_SMP_COS_VM732,
-	BATTERY_SMP_COS_26JGK,
-	BATTERY_SMP_COS_RF9H3,
-	BATTERY_BYD16,
-	BATTERY_LGC3,
-	BATTERY_SIMPLO,
-	BATTERY_SIMPLO_LS,
-	BATTERY_TYPE_COUNT,
-};
-
-int board_is_sourcing_vbus(int port);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/driblee/build.mk b/board/driblee/build.mk
deleted file mode 100644
index b012d8d502..0000000000
--- a/board/driblee/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=keeby
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/driblee/cbi_ssfc.c b/board/driblee/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/driblee/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/driblee/cbi_ssfc.h b/board/driblee/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/driblee/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/driblee/ec.tasklist b/board/driblee/ec.tasklist
deleted file mode 100644
index 0025c2985b..0000000000
--- a/board/driblee/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/driblee/gpio.inc b/board/driblee/gpio.inc
deleted file mode 100644
index 82ba0d67bc..0000000000
--- a/board/driblee/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* HDMI_HPD */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Button interrupts */
-GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
-GPIO(SUB_USB_C1_INT_ODL,    PIN(F, 5), GPIO_OUT_LOW) /* 5V power en */
-GPIO(EC_I2C_SBU_USB_C1_SCL,	PIN(9, 2), GPIO_ODR_LOW) /* HDMI en */
-
-/* LED */
-GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A0 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L,	PIN(6, 3), GPIO_OUT_HIGH)  /* Reverse: Enable A0 1.5A Charging */
-/*
- * Lalala doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)   /* ADC0-1 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-GPIO(EC_ACOK_OTG, PIN(C, 0), GPIO_OUT_LOW)  /* OTG-OVP protect enable */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO43_NC, PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF2_NC, PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOF3_NC, PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO72_NC, PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO75_NC, PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/driblee/led.c b/board/driblee/led.c
deleted file mode 100644
index cd34613a7c..0000000000
--- a/board/driblee/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for lalala
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 10;
-
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/driblee/usb_pd_policy.c b/board/driblee/usb_pd_policy.c
deleted file mode 100644
index 19dd01d37b..0000000000
--- a/board/driblee/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/charger/isl923x_public.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/driblee/vif_override.xml b/board/driblee/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/driblee/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/drobit/battery.c b/board/drobit/battery.c
deleted file mode 100644
index f8f3eb296f..0000000000
--- a/board/drobit/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* C490-42 Battery Information */
-	[BATTERY_C490] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWQd3jB",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000c,
-				.disconnect_val = 0x000c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C490;
diff --git a/board/drobit/board.c b/board/drobit/board.c
deleted file mode 100644
index b08294bd24..0000000000
--- a/board/drobit/board.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "charge_state_v2.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config drobit_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &drobit_kb;
-}
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN3,
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(72),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(75),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(72),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(75),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "usb_c1_mix",
-		.port = I2C_PORT_USB_C1_MIX,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C0_USB_C1_MIX_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-void board_reset_pd_mcu(void)
-{
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/* Disable FRS on boards with the SYV682A. FRS only works on the SYV682B. */
-void setup_board_ppc(void)
-{
-	uint8_t board_id = get_board_id();
-
-	if (board_id < 2) {
-		ppc_chips[USBC_PORT_C0].frs_en = 0;
-		ppc_chips[USBC_PORT_C1].frs_en = 0;
-	}
-}
-
-__override void board_cbi_init(void)
-{
-	setup_board_ppc();
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-/* Called on AP S0ix -> S0 tranition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0ix transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* Set the charge limit based upon desired maximum. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 98% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 98 / 100;
-	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
-}
diff --git a/board/drobit/board.h b/board/drobit/board.h
deleted file mode 100644
index 15f28d0971..0000000000
--- a/board/drobit/board.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensors */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_GMR_TABLET_MODE
-#undef CONFIG_ACCEL_FIFO
-#undef CONFIG_ACCEL_FIFO_SIZE
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#ifdef BOARD_DROBIT_ECMODEENTRY
-#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#endif
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USB_PD_FRS_PPC
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-#undef CONFIG_VOLUME_BUTTONS
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_USB_C1_MIX	NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C490,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/drobit/build.mk b/board/drobit/build.mk
deleted file mode 100644
index 43b40c644c..0000000000
--- a/board/drobit/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/drobit/ec.tasklist b/board/drobit/ec.tasklist
deleted file mode 100644
index 2c9a9e8e32..0000000000
--- a/board/drobit/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/drobit/gpio.inc b/board/drobit/gpio.inc
deleted file mode 100644
index bc7d625195..0000000000
--- a/board/drobit/gpio.inc
+++ /dev/null
@@ -1,184 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-
-/*
- * Lid g-sensor interrupt unused on Volteer, configure as regular input for
- * power saving.
- */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C0_RT_RST_ODL,		PIN(D, 4), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_FRS_EN,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,		PIN(9, 4), GPIO_OUT_LOW)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C0_RT_INT_ODL,		PIN(F, 2), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(LED_2_L,			PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_3_L,			PIN(C, 2), GPIO_OUT_HIGH)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC4,		PIN(C, 4), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Only connected to test points */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_USB_C1_MIX_SCL,   PIN(B, 5), GPIO_INPUT)		/* Reserved for USB4 retimer port 1 */
-GPIO(EC_I2C0_USB_C1_MIX_SDA,   PIN(B, 4), GPIO_INPUT)		/* Reserved for USB4 retimer port 1 */
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, 0) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
diff --git a/board/drobit/led.c b/board/drobit/led.c
deleted file mode 100644
index 47c3cca5b7..0000000000
--- a/board/drobit/led.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/drobit/vif_override.xml b/board/drobit/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/drobit/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/drobit_ecmodeentry b/board/drobit_ecmodeentry
deleted file mode 120000
index c3ab5c1706..0000000000
--- a/board/drobit_ecmodeentry
+++ /dev/null
@@ -1 +0,0 @@
-drobit
\ No newline at end of file
diff --git a/board/eel b/board/eel
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/eel
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/eldrid/battery.c b/board/eldrid/battery.c
deleted file mode 100644
index 3c9f2b0c21..0000000000
--- a/board/eldrid/battery.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 996QA193H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Cosmx CA407792G Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
-
-__override bool board_battery_is_initialized(void)
-{
-	bool batt_initialization_state;
-	int batt_status;
-
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
-	return batt_initialization_state;
-}
diff --git a/board/eldrid/board.c b/board/eldrid/board.c
deleted file mode 100644
index 601c23df84..0000000000
--- a/board/eldrid/board.c
+++ /dev/null
@@ -1,613 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "charge_state_v2.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "isl9241.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_raw.h"
-#include "lid_switch.h"
-#include "keyboard_scan.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-static void board_charger_config(void)
-{
-	/*
-	 * b/166728543, we configured charger setting to throttle CPU
-	 * when the system loading is at battery current limit.
-	 */
-	int reg;
-
-	/*
-	 * Set DCProchot# to 5120mA
-	 */
-	isl9241_set_dc_prochot(CHARGER_SOLO, 5120);
-
-	/*
-	 * Set Control1 bit<3> = 1, PSYS = 1
-	 */
-	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-		       ISL9241_REG_CONTROL1, &reg) == EC_SUCCESS) {
-		reg |= ISL9241_CONTROL1_PSYS;
-		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL1, reg))
-			CPRINTS("Failed to set isl9241");
-	}
-
-	/*
-	 * Set Control2 bit<10:9> = 00, PROCHOT# Debounce = 7us
-	 */
-	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-		       ISL9241_REG_CONTROL2, &reg) == EC_SUCCESS) {
-		reg &= ~ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK;
-		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL2, reg))
-			CPRINTS("Failed to set isl9241");
-	}
-
-	/*
-	 * Set Control4 bit<11> = 1, PSYS Rsense Ratio = 1:1
-	 */
-	if (i2c_read16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-		       ISL9241_REG_CONTROL4, &reg) == EC_SUCCESS) {
-		reg |= ISL9241_CONTROL4_PSYS_RSENSE_RATIO;
-		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL4, reg))
-			CPRINTS("Failed to set isl9241");
-	}
-}
-
-static void board_init(void)
-{
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 100);
-	board_charger_config();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
-	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
-}
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * b/166728543
-	 * Set different AC_PROCHOT value when using different wattage ADT.
-	 */
-	if (max_ma * charge_mv == PD_MAX_POWER_MW * 1000)
-		isl9241_set_ac_prochot(0, 3840);
-	else
-		isl9241_set_ac_prochot(0, 3328);
-
-	/*
-	 * Follow OEM request to limit the input current to
-	 * 90% negotiated limit.
-	 */
-	charge_ma = charge_ma * 90 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
-}
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/*
-		 * If using the side select to run both LEDs at the same time,
-		 * the frequency should be 1/2 of the color channel PWM
-		 * frequency to drive each LED equally.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Volteer specific USB daughter-board configuration */
-
-/* USBC TCPC configuration for USB3 daughter board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static enum gpio_signal ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL;
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(ps8xxx_rst_odl, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	if (usb_db == DB_USB3_ACTIVE) {
-		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	}
-}
-
-/*
- * Set up support for the USB3 daughterboard:
- *   Parade PS8815 TCPC (integrated retimer)
- *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
- *   Silergy SYV682A PPC (same as USB4 board)
- *   Virtual mux with stacked retimer
- */
-static void config_db_usb3_active(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
-}
-
-/*
- * Set up support for the passive USB3 daughterboard:
- *   TUSB422 TCPC (already the default)
- *   PI3USB9201 BC 1.2 chip (already the default)
- *   Silergy SYV682A PPC (already the default)
- *   Virtual mux without stacked retimer
- */
-
-static void config_db_usb3_passive(void)
-{
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
-}
-
-static void config_port_discrete_tcpc(int port)
-{
-	/*
-	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
-	 * simplicity allow either and decide which we are using.
-	 * Default to TUSB422, and switch to RT1715 after BOARD_ID >=1.
-	 */
-	if (get_board_id() >= 1) {
-		CPRINTS("C%d: RT1715", port);
-		tcpc_config[port].i2c_info.addr_flags =
-			RT1715_I2C_ADDR_FLAGS;
-		tcpc_config[port].drv = &rt1715_tcpm_drv;
-		return;
-	}
-	CPRINTS("C%d: Default to TUSB422", port);
-}
-
-static const char *db_type_prefix = "USB DB type: ";
-__override void board_cbi_init(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	config_port_discrete_tcpc(0);
-
-	switch (usb_db) {
-	case DB_USB_ABSENT:
-		CPRINTS("%sNone", db_type_prefix);
-		break;
-	case DB_USB4_GEN2:
-		CPRINTS("%sUSB4 Gen1/2", db_type_prefix);
-		break;
-	case DB_USB4_GEN3:
-		CPRINTS("%sUSB4 Gen3", db_type_prefix);
-		break;
-	case DB_USB3_ACTIVE:
-		config_db_usb3_active();
-		CPRINTS("%sUSB3 Active", db_type_prefix);
-		break;
-	case DB_USB3_PASSIVE:
-		config_db_usb3_passive();
-		CPRINTS("%sUSB3 Passive", db_type_prefix);
-		break;
-	default:
-		CPRINTS("%sID %d not supported", db_type_prefix, usb_db);
-	}
-
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() < 1)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-
-	/*
-	 * If keyboard is US2(KB_LAYOUT_1), we need translate right ctrl
-	 * to backslash(\|) key.
-	 */
-	if (ec_cfg_keyboard_layout() == KB_LAYOUT_1)
-		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/eldrid/board.h b/board/eldrid/board.h
deleted file mode 100644
index 8a78f22350..0000000000
--- a/board/eldrid/board.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* Keyboard features */
-
-/*
- * Disable VOL up/down when tablet mode.
- * TODO(b/170966461): Re-enable Vivaldi keyboard once
- * 8042 and MKBP drivers can coexist.
- */
-#undef  CONFIG_KEYBOARD_VIVALDI
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI160 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#define CONFIG_CUSTOM_FAN_CONTROL
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/eldrid/build.mk b/board/eldrid/build.mk
deleted file mode 100644
index 868a463932..0000000000
--- a/board/eldrid/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
-board-y+=thermal.o
diff --git a/board/eldrid/ec.tasklist b/board/eldrid/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/eldrid/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/eldrid/gpio.inc b/board/eldrid/gpio.inc
deleted file mode 100644
index 1006391c4e..0000000000
--- a/board/eldrid/gpio.inc
+++ /dev/null
@@ -1,182 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Volteer, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,			PIN(F, 3), GPIO_INPUT)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(LED_1_L,		        PIN(C, 4), GPIO_OUT_HIGH)	/* Battery LED: Amber */
-GPIO(LED_2_L,		        PIN(C, 3), GPIO_OUT_HIGH)	/* Battery LED: White */
-GPIO(POWER_LED_GATE,		PIN(C, 2), GPIO_OUT_LOW)	/* Power LED: White */
-
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD1,		PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD0,		PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/eldrid/led.c b/board/eldrid/led.c
deleted file mode 100644
index 3cbf06c123..0000000000
--- a/board/eldrid/led.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "pwm.h"
-
-#define BAT_LED_ON_LVL 0
-#define BAT_LED_OFF_LVL 1
-
-#define PWR_LED_ON_LVL 1
-#define PWR_LED_OFF_LVL 0
-
-/* LED_SIDESEL_4_L=1, MB BAT LED open
- * LED_SIDESEL_4_L=0, DB BAT LED open
- */
-#define LED_SIDESEL_MB_PORT 0
-#define LED_SIDESEL_DB_PORT 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {
-		{EC_LED_COLOR_WHITE, 0.4 * LED_ONE_SEC},
-		{LED_OFF,            0.4 * LED_ONE_SEC}
-	},
-	[STATE_FACTORY_TEST]         = {
-		{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-		{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           =  {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   =  {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           6 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {
-		{LED_OFF,             LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	int port;
-	int side_select_duty;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		port = charge_manager_get_active_charge_port();
-		switch (port) {
-		case LED_SIDESEL_MB_PORT:
-			side_select_duty = 0;
-			break;
-		case LED_SIDESEL_DB_PORT:
-			side_select_duty = 100;
-			break;
-		default:
-		/*
-		 * We need to turn off led here since curr.ac won't update
-		 * immediately but led will update every 200ms.
-		 */
-			side_select_duty = 50;
-			color = LED_OFF;
-		}
-
-		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, BAT_LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, BAT_LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, BAT_LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, BAT_LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, BAT_LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, BAT_LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		led_auto_control(led_id, 0);
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/eldrid/sensors.c b/board/eldrid/sensors.c
deleted file mode 100644
index aba3549cca..0000000000
--- a/board/eldrid/sensors.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the BMI160 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/eldrid/thermal.c b/board/eldrid/thermal.c
deleted file mode 100644
index 4f9ac8796b..0000000000
--- a/board/eldrid/thermal.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-
-/******************************************************************************/
-/* EC thermal management configuration */
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C).
- * TODO(b/170143672): Have different sensor placement. The temperature need to
- * be changed.
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-struct fan_step {
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-
-	/* Fan rpm */
-	uint16_t rpm[FAN_CH_COUNT];
-};
-
-/*
- * TODO(b/167931578) Only monitor sensor3 for now.
- * Will add more sensors support if needed.
- */
-static const struct fan_step fan_table[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 0, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 46, -1},
-		.off = {-1, -1, 44, -1},
-		.rpm = {3200},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 45, -1},
-		.rpm = {3600},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {4100},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 58, -1},
-		.off = {-1, -1, 53, -1},
-		.rpm = {4900},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 57, -1},
-		.rpm = {5200},
-	},
-};
-
-int fan_table_to_rpm(int fan, int *temp)
-{
-	/* current fan level */
-	static int current_level;
-	/* previous fan level */
-	static int prev_current_level;
-
-	/* previous sensor temperature */
-	static int prev_temp[TEMP_SENSOR_COUNT];
-	const int num_fan_levels = ARRAY_SIZE(fan_table);
-	int i;
-	int new_rpm = 0;
-
-	/*
-	 * Compare the current and previous temperature, we have
-	 * the three paths :
-	 *  1. decreasing path. (check the release point)
-	 *  2. increasing path. (check the trigger point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-
-	if (temp[TEMP_SENSOR_3_DDR_SOC] < prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
-		for (i = current_level; i > 0; i--) {
-			if (temp[TEMP_SENSOR_3_DDR_SOC] <
-				fan_table[i].off[TEMP_SENSOR_3_DDR_SOC])
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (temp[TEMP_SENSOR_3_DDR_SOC] >
-		prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
-		for (i = current_level; i < num_fan_levels; i++) {
-			if (temp[TEMP_SENSOR_3_DDR_SOC] >
-				fan_table[i].on[TEMP_SENSOR_3_DDR_SOC])
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	if (current_level != prev_current_level) {
-		CPRINTS("temp: %d, prev_temp: %d", temp[TEMP_SENSOR_3_DDR_SOC],
-			prev_temp[TEMP_SENSOR_3_DDR_SOC]);
-		CPRINTS("current_level: %d", current_level);
-	}
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
-		prev_temp[i] = temp[i];
-
-	prev_current_level = current_level;
-
-	switch (fan) {
-	case FAN_CH_0:
-		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
-		break;
-	default:
-		break;
-	}
-
-	return new_rpm;
-}
-
-void board_override_fan_control(int fan, int *temp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, temp));
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		/* Stop fan when enter S0ix */
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan), 0);
-	}
-}
diff --git a/board/eldrid/vif_override.xml b/board/eldrid/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/eldrid/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/elemi/battery.c b/board/elemi/battery.c
deleted file mode 100644
index 602176b718..0000000000
--- a/board/elemi/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Elemi battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 996QA193H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Cosmx CA407792G Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/elemi/board.c b/board/elemi/board.c
deleted file mode 100644
index bb59308213..0000000000
--- a/board/elemi/board.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Elemi board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Elemi if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 6500,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(70),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(58),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(60),
-};
-
-const static struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(70),
-};
-
-const static struct ec_thermal_config thermal_regulator = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(70),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(58),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_charger,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_regulator,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-__override void board_ps8xxx_tcpc_init(int port)
-{
-	/* b/189587527: Set Displayport EQ loss up to 10dB */
-	tcpc_addr_write(port, PS8751_I2C_ADDR1_P1_FLAGS,
-		PS8815_REG_DP_EQ_SETTING,
-		PS8815_DPEQ_LOSS_UP_10DB << PS8815_REG_DP_EQ_COMP_SHIFT);
-}
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-__override void board_cbi_init(void)
-{
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/elemi/board.h b/board/elemi/board.h
deleted file mode 100644
index f2ce54e83a..0000000000
--- a/board/elemi/board.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Elemi board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the NPCX797FC dose not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Optional features */
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* Keyboard features */
-
-/* Sensors */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_GMR_TABLET_MODE
-#undef CONFIG_ACCEL_FIFO
-#undef CONFIG_ACCEL_FIFO_SIZE
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-/* Experimentally determined. See b/186079130. */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US	10000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_TUSB422
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-#undef CONFIG_VOLUME_BUTTONS
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/* Keyboard feature */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/elemi/build.mk b/board/elemi/build.mk
deleted file mode 100644
index 43b40c644c..0000000000
--- a/board/elemi/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/elemi/ec.tasklist b/board/elemi/ec.tasklist
deleted file mode 100644
index 2c9a9e8e32..0000000000
--- a/board/elemi/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/elemi/gpio.inc b/board/elemi/gpio.inc
deleted file mode 100644
index 934e26ce2b..0000000000
--- a/board/elemi/gpio.inc
+++ /dev/null
@@ -1,169 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,			PIN(F, 3), GPIO_INPUT)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(C0_CHARGE_LED_AMBER_L,	PIN(C, 3), GPIO_OUT_HIGH)	/* Amber C0 port */
-GPIO(C0_CHARGE_LED_WHITE_L,	PIN(C, 4), GPIO_OUT_HIGH)	/* White C0 port */
-GPIO(C1_CHARGE_LED_AMBER_L,	PIN(6, 0), GPIO_OUT_HIGH)	/* Amber C1 port */
-GPIO(C1_CHARGE_LED_WHITE_L,	PIN(C, 2), GPIO_OUT_HIGH)	/* White C1 port */
-
-/* Unused signals */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO56,		PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD4,		PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO95,		PIN(9, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO81,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO93,		PIN(9, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOB5,		PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
-GPIO(UNUSED_GPIOB4,		PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)	/* Unused I2C port, Set input only */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/elemi/led.c b/board/elemi/led.c
deleted file mode 100644
index d8df9c92a0..0000000000
--- a/board/elemi/led.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Elemi
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_CYCLE_TIME_MS   (2 * 1000)
-#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS      (1 * 1000)
-#define LED_ON_TICKS        (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
-	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int suspend_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Elemi, Elemi doesn't have power LED,
-	 * blinking both two side battery white LEDs to indicate
-	 * system suspend without charging state.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
-		suspend_ticks++;
-
-		led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		return;
-	}
-
-	suspend_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/elemi/vif_override.xml b/board/elemi/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/elemi/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/elm/battery.c b/board/elm/battery.c
deleted file mode 100644
index de9685a89d..0000000000
--- a/board/elm/battery.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "util.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	0x3a
-#define SB_SHUTDOWN_DATA	0xC574
-
-static const struct battery_info info = {
-	.voltage_max = 13200,
-	.voltage_normal = 11550,
-	.voltage_min = 9100,
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
diff --git a/board/elm/board.c b/board/elm/board.c
deleted file mode 100644
index d62ff8afae..0000000000
--- a/board/elm/board.c
+++ /dev/null
@@ -1,532 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Oak board configuration */
-
-#include "adc.h"
-#include "atomic.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/anx7688.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "thermal.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Dispaly port hardware can connect to port 0, 1 or neither. */
-#define PD_PORT_NONE -1
-
-void pd_mcu_interrupt(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-void deferred_reset_pd_mcu(void);
-DECLARE_DEFERRED(deferred_reset_pd_mcu);
-
-void usb_evt(enum gpio_signal signal)
-{
-	if (!gpio_get_level(GPIO_BC12_WAKE_L))
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#include "gpio_list.h"
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/*
-	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
-	 * output in mW
-	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
-	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
-	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-int anx7688_passthru_allowed(const struct i2c_port_t *port,
-			     const uint16_t addr_flags)
-{
-	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
-
-	/* Allow access to 0x2c (TCPC) */
-	if (addr == 0x2c)
-		return 1;
-
-	CPRINTF("Passthru rejected on %x", addr);
-
-	return 0;
-}
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100,  GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"pd",      I2C_PORT_PD_MCU,  1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA,
-		anx7688_passthru_allowed}
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_SPI2_NSS },
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_SPI2_NSS_DB }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC,
-			.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
-		},
-		.drv = &anx7688_tcpm_drv,
-	},
-};
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-/*
- * Temperature sensors data; must be in same order as enum temp_sensor_id.
- * Sensor index and name must match those present in coreboot:
- *     src/mainboard/google/${board}/acpi/dptf.asl
- */
-const struct temp_sensor_t temp_sensors[] = {
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
-#endif
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver    = &anx7688_usb_mux_driver,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/**
- * Reset PD MCU
- *   ANX7688 needs a reset pulse of 50ms after power enable.
- */
-void deferred_reset_pd_mcu(void)
-{
-	uint8_t state = gpio_get_level(GPIO_USB_C0_PWR_EN_L) |
-			(gpio_get_level(GPIO_USB_C0_RST) << 1);
-
-	CPRINTS("%s %d", __func__, state);
-	switch (state) {
-	case 0:
-		/*
-		 * PWR_EN_L low, RST low
-		 * start reset sequence by turning off power enable
-		 * and wait for 1ms.
-		 */
-		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
-		break;
-	case 1:
-		/*
-		 * PWR_EN_L high, RST low
-		 * pull PD reset pin and wait for another 1ms
-		 */
-		gpio_set_level(GPIO_USB_C0_RST, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
-		/* on PD reset, trigger PD task to reset state */
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-		break;
-	case 3:
-		/*
-		 * PWR_EN_L high, RST high
-		 * enable power and wait for 10ms then pull RESET_N
-		 */
-		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 0);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
-		break;
-	case 2:
-		/*
-		 * PWR_EN_L low, RST high
-		 * leave reset state
-		 */
-		gpio_set_level(GPIO_USB_C0_RST, 0);
-		break;
-	}
-}
-
-static void board_power_on_pd_mcu(void)
-{
-	/* check if power is already on */
-	if (!gpio_get_level(GPIO_USB_C0_PWR_EN_L))
-		return;
-
-	gpio_set_level(GPIO_USB_C0_EXTPWR_EN, 1);
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* enable port controller's cable detection before reset */
-	anx7688_enable_cable_detection(0);
-
-	/* wait for 10ms, then start port controller's reset sequence */
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
-}
-
-int command_pd_reset(int argc, char **argv)
-{
-	board_reset_pd_mcu();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset,
-			"",
-			"Reset PD IC");
-
-/**
- * There is a level shift for AC_OK & LID_OPEN signal between AP & EC,
- * disable it (drive high) when AP is off, otherwise enable it (drive low).
- */
-static void board_extpower_buffer_to_soc(void)
-{
-	/* Drive high when AP is off (G3), else drive low */
-	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L,
-		       chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 1 : 0);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable Level shift of AC_OK & LID_OPEN signals */
-	board_extpower_buffer_to_soc();
-	/* Enable rev1 testing GPIOs */
-	gpio_set_level(GPIO_SYSTEM_POWER_H, 1);
-	/* Enable PD MCU interrupt */
-	gpio_enable_interrupt(GPIO_PD_MCU_INT);
-
-	/* Enable BC 1.2 */
-	gpio_enable_interrupt(GPIO_BC12_CABLE_INT);
-
-	/* Check if typeC is already connected, and do 7688 power on flow */
-	board_power_on_pd_mcu();
-
-	/* Update VBUS supplier */
-	usb_charger_vbus_change(0, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-
-	/* Remap SPI2 to DMA channels 6 and 7 (0011) */
-	STM32_DMA_CSELR(STM32_DMAC_CH6) |= (3 << 20) | (3 << 24);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can active at a time.
- *
- * @param charge_port    Charge port to enable.
- *
- * Return EC_SUCCESS if charge port is accepted and made active.
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source VBUS on the port */
-	int source = gpio_get_level(GPIO_USB_C0_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTF("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable charging port */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-	} else {
-		/* Enable charging port */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Limit input current 95% ratio on elm board for safety */
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-/**
- * Set AP reset.
- * AP_RESET_L (PC3, CPU_WARM_RESET_L) is connected to PMIC SYSRSTB
- */
-void board_set_ap_reset(int asserted)
-{
-	/* Signal is active-low */
-	CPRINTS("ap warm reset(%d)", asserted);
-	gpio_set_level(GPIO_AP_RESET_L, !asserted);
-}
-
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-static void tmp432_set_power_deferred(void)
-{
-	/* Shut tmp432 down if not in S0 && no external power */
-	if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
-		if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
-			CPRINTS("ERROR: Can't shutdown TMP432.");
-		return;
-	}
-
-	/*  else, turn it on. */
-	if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
-		CPRINTS("ERROR: Can't turn on TMP432.");
-}
-DECLARE_DEFERRED(tmp432_set_power_deferred);
-#endif
-
-/**
- * Hook of AC change. turn on/off tmp432 depends on AP & AC status.
- */
-static void board_extpower(void)
-{
-	board_extpower_buffer_to_soc();
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition, and before HOOK_CHIPSET_STARTUP */
-static void board_chipset_pre_init(void)
-{
-	/* Enable level shift of AC_OK when power on */
-	board_extpower_buffer_to_soc();
-
-	/* Enable SPI for KX022 */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-
-	/* Set all four SPI pins to high speed */
-	/* pins D0/D1/D3/D4 */
-	STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf;
-	/* pins F6 */
-	STM32_GPIO_OSPEEDR(GPIO_F) |= 0x00003000;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable level shift to SoC when shutting down */
-	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1);
-
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/*
-	 * Calling gpio_config_module sets disabled alternate function pins to
-	 * GPIO_INPUT.  But to prevent leakage we want to set GPIO_OUT_LOW
-	 */
-	gpio_set_flags_by_mask(GPIO_D, 0x1a, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_SPI2_NSS, 0);
-	gpio_set_level(GPIO_SPI2_NSS_DB, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_kx022_mutex[2];
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1),  0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-/* KX022 private data */
-struct kionix_accel_data g_kx022_data[2];
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_kx022_mutex[0],
-		.drv_data = &g_kx022_data[0],
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 2, /* g, enough for lid angle calculation. */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_kx022_mutex[1],
-		.drv_data = &g_kx022_data[1],
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(1),
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-__override void lid_angle_peripheral_enable(int enable)
-{
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-
-	/* enable/disable touchpad */
-	gpio_set_level(GPIO_EN_TP_INT_L, !enable);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	return gpio_get_level(GPIO_PD_MCU_INT) ? PD_STATUS_TCPC_ALERT_0 : 0;
-}
-
diff --git a/board/elm/board.h b/board/elm/board.h
deleted file mode 100644
index 40eb81eab8..0000000000
--- a/board/elm/board.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* elm board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config engineering velidation.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* Free up flash space */
-#undef CONFIG_USB_PD_TCPMV1_DEBUG
-
-/* Accelero meter and gyro sensor */
-#define CONFIG_ACCEL_KX022
-#undef CONfFIG_CMD_ACCELSPOOF
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-
-/* AC adaptor, charger, battery */
-#define CONFIG_BATTERY_CUT_OFF
-#undef CONFIG_BATTERY_PRECHARGE_TIMEOUT
-#define CONFIG_BATTERY_PRECHARGE_TIMEOUT 300
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
-#define CONFIG_BATTERY_SMART
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_ISL9237
-#define CONFIG_CHARGER_MAX_INPUT_CURRENT 3000
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHIPSET_MT817X
-#define CONFIG_CMD_TYPEC
-#define CONFIG_EXTPOWER_GPIO
-
-/* Increase tx buffer size, as we'd like to stream EC log to AP. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Wakeup pin: EC_WAKE(PA0) - WKUP1 */
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HIBERNATE
-#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1)
-
-/* Other configs */
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_COMMON
-#define CONFIG_USB_CHARGER
-#define CONFIG_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
-#define CONFIG_SWITCH
-#define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_DPTF
-
-/* Type-C */
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-
-#define CONFIG_USB_PD_LOGGING
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_ANX7688
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#undef  CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
-#define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x2C
-#define CONFIG_USB_PD_ANX7688
-
-/* UART DMA */
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 1
-
-/* Optional features */
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-/* Mark host command structs as aligned */
-#define CONFIG_HOSTCMD_ALIGNED
-/* By default, set hcdebug to off */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#define CONFIG_CMD_I2C_PROTECT
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-/*
- * Flash layout:
- *                            PSTATE(4KB)
- *                              |
- *          (124KB)             v            (132KB)
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| | |<--------RW image----------->|
- * 0        (120KB)            ^ ^           (128KB)
- *                             | |
- *                             | sector 31(132KB sector)
- *                             |
- *                             sector 30(4KB sector)
- */
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_SIZE
-#define CONFIG_RW_MEM_OFF                (128 * 1024)
-#define CONFIG_RW_SIZE                   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (128 * 1024)
-#define CONFIG_WP_STORAGE_SIZE           (128 * 1024)
-
-/* Drivers */
-#ifndef __ASSEMBLER__
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Keyboard output port list */
-#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
-
-/* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
-#define I2C_PORT_BATTERY 0
-#define I2C_PORT_CHARGER 0
-#define I2C_PORT_PERICOM 0
-#define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
-#define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI master port (SPI2) */
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 4
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
-
-#include "gpio_signal.h"
-
-enum power_signal {
-	MTK_POWER_GOOD = 0,
-	MTK_SUSPEND_ASSERTED,
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_POWER_LED = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
-	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	/* TMP432 local and remote sensors */
-	TEMP_SENSOR_I2C_TMP432_LOCAL,
-	TEMP_SENSOR_I2C_TMP432_REMOTE1,
-	TEMP_SENSOR_I2C_TMP432_REMOTE2,
-#endif
-	/* Battery temperature sensor */
-	TEMP_SENSOR_BATTERY,
-
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	BASE_ACCEL,
-	LID_ACCEL,
-	SENSOR_COUNT,
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* The lower the input voltage, the higher the power efficiency. */
-#define PD_PREFER_LOW_VOLTAGE
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-/* Set AP reset pin according to parameter */
-void board_set_ap_reset(int asserted);
-
-#endif  /* !__ASSEMBLER__ */
-
-#endif  /* __CROS_EC_BOARD_H */
diff --git a/board/elm/build.mk b/board/elm/build.mk
deleted file mode 100644
index 172a88e843..0000000000
--- a/board/elm/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#-*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# STmicro STM32F091VC
-CHIP := stm32
-CHIP_FAMILY := stm32f0
-CHIP_VARIANT:= stm32f09x
-
-board-y = board.o battery.o led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/elm/ec.tasklist b/board/elm/ec.tasklist
deleted file mode 100644
index 3ea68bf9f8..0000000000
--- a/board/elm/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
diff --git a/board/elm/gpio.inc b/board/elm/gpio.inc
deleted file mode 100644
index 0dc89269ba..0000000000
--- a/board/elm/gpio.inc
+++ /dev/null
@@ -1,113 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(AC_PRESENT,     PIN(C, 6),  GPIO_INT_BOTH,    extpower_interrupt)
-GPIO_INT(LID_OPEN,       PIN(C, 13), GPIO_INT_BOTH,    lid_interrupt)          /* LID switch detection */
-GPIO_INT(SUSPEND_L,      PIN(C, 7),  GPIO_INT_BOTH,    power_signal_interrupt) /* AP suspend/resume state */
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH,    power_signal_interrupt)
-GPIO_INT(PD_MCU_INT,     PIN(E, 0),  GPIO_INT_RISING,  pd_mcu_interrupt)       /* Signal from PD MCU, external pull-up */
-GPIO_INT(BC12_CABLE_INT, PIN(E, 1),  GPIO_INT_FALLING | GPIO_PULL_UP, usb_evt)    /* interrupt from BC12 and CABLE_DET */
-GPIO_INT(POWER_BUTTON_L, PIN(B, 5),  GPIO_INT_BOTH | GPIO_PULL_UP,  power_button_interrupt)
-GPIO_INT(SPI1_NSS,       PIN(A, 4),  GPIO_INT_BOTH | GPIO_PULL_UP,  spi_event)              /* SPI Chip Select */
-
-/* Keyboard inputs */
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-GPIO_INT(KB_IN00, PIN(C, 8),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN01, PIN(C, 9),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN07, PIN(D, 2),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW)   /* KSO2 is inverted */
-GPIO(KB_OUT03,          PIN(B, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(D, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(D, 13), GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(D, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(C, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(D, 5),  GPIO_KB_OUTPUT)
-
-
-/* Inputs without interrupt handlers */
-GPIO(5V_POWER_GOOD,      PIN(A, 1), GPIO_INPUT)
-GPIO(EC_WAKE,            PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(WP_L,               PIN(B, 4), GPIO_INPUT)      /* Write protect input */
-GPIO(BAT_PRESENT_L,      PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(USB_C0_VBUS_WAKE_L, PIN(D, 12), GPIO_INPUT)
-GPIO(EC_INT_L,           PIN(B, 9),  GPIO_ODR_HIGH)
-
-/* Board version */
-GPIO(BOARD_VERSION1, PIN(E, 10), GPIO_INPUT) /* Board ID 0 */
-GPIO(BOARD_VERSION2, PIN(E,  9), GPIO_INPUT) /* Board ID 1 */
-GPIO(BOARD_VERSION3, PIN(E, 12), GPIO_INPUT) /* Board ID 2 */
-GPIO(BOARD_VERSION4, PIN(E, 11), GPIO_INPUT) /* Board ID 3 */
-
-/* Outputs */
-GPIO(BAT_LED0,          PIN(A, 11), GPIO_OUT_LOW)   /* LED_BLUE */
-GPIO(BAT_LED1,          PIN(B, 11), GPIO_OUT_LOW)   /* LED_ORANGE   */
-GPIO(PWR_LED0,          PIN(E,  8), GPIO_OUT_LOW)   /* LED_BLUE */
-GPIO(PWR_LED1,          PIN(D,  6), GPIO_OUT_LOW)   /* LED_ORANGE   */
-
-GPIO(EC_BL_OVERRIDE,    PIN(F, 1),  GPIO_OUT_LOW)
-GPIO(ENTERING_RW,       PIN(F, 0),  GPIO_OUT_LOW)
-
-GPIO(AP_RESET_L,        PIN(C, 3),  GPIO_ODR_HIGH) /* Connect to the PMU_SYSRSTB */
-GPIO(BC12_WAKE_L,       PIN(D, 7),  GPIO_INPUT)
-GPIO(USB_C0_CABLE_DET_L,PIN(E, 7),  GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(SYSTEM_POWER_H,    PIN(B, 10), GPIO_OUT_LOW)
-GPIO(PMIC_PWRON_H,      PIN(A, 12), GPIO_OUT_LOW)
-GPIO(PMIC_WARM_RESET_H, PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(LEVEL_SHIFT_EN_L,  PIN(F, 10), GPIO_OUT_LOW)    /* LID/AC level shift */
-
-GPIO(USB_C0_5V_EN,      PIN(D, 8),  GPIO_OUT_LOW)    /* USBC port 0 5V */
-GPIO(USB_C0_CHARGE_L,   PIN(D, 9),  GPIO_OUT_LOW)    /* USBC port 0 charge */
-GPIO(USB_C0_RST,        PIN(D, 10), GPIO_ODR_HIGH)    /* ANX7688 reset */
-GPIO(USB_C0_PWR_EN_L,   PIN(B, 15), GPIO_ODR_HIGH)    /* ANX7688 power enable */
-GPIO(USB_C0_EXTPWR_EN,  PIN(F, 2),  GPIO_OUT_LOW)   /* ANX7688 3.3V ext power enable */
-GPIO(USB_DP_HPD,        PIN(F, 3),  GPIO_INPUT)
-GPIO(EN_TP_INT_L,       PIN(E, 14), GPIO_OUT_LOW)    /* touchpad interrupt enable */
-
-/* Analog pins */
-GPIO(VDC_BOOSTIN_SENSE, PIN(C, 1), GPIO_ANALOG) /* ADC_IN11 */
-GPIO(PSYS_MONITOR,      PIN(A, 2), GPIO_ANALOG) /* ADC_IN2  */
-GPIO(AMON_BMON,         PIN(C, 0), GPIO_ANALOG) /* ADC_IN10 */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL, PIN(B, 6),  GPIO_INPUT) /* EC I2C */
-GPIO(I2C0_SDA, PIN(B, 7),  GPIO_INPUT)
-GPIO(I2C1_SCL, PIN(B, 13), GPIO_INPUT) /* PD I2C */
-GPIO(I2C1_SDA, PIN(B, 14), GPIO_INPUT)
-
-/* SPI MASTER. For SPI sensor */
-GPIO(SPI2_NSS,    PIN(D, 0),  GPIO_OUT_HIGH) /* mainboard */
-GPIO(SPI2_NSS_DB, PIN(F, 6),  GPIO_OUT_HIGH) /* daughterboard */
-
-/* sensor power control */
-GPIO(SENSOR_PWR_EN_L, PIN(D, 11), GPIO_OUT_LOW)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,        0) /* I2C MASTER:PB6/7 */
-ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C,        0) /* I2C MASTER:PB13/14 */
-ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI,        0) /* SPI SLAVE:PA4/5/6/7 */
-ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PD1/3/4 */
diff --git a/board/elm/led.c b/board/elm/led.c
deleted file mode 100644
index d73cc05c1b..0000000000
--- a/board/elm/led.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED and Power LED control for Elm Board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-#include "system.h"
-
-#define CRITICAL_LOW_BATTERY_PERMILLAGE 71
-#define LOW_BATTERY_PERMILLAGE 137
-#define FULL_BATTERY_PERMILLAGE 937
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	BAT_LED_BLUE = 0,
-	BAT_LED_ORANGE,
-	PWR_LED_BLUE,
-	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
-};
-
-static int bat_led_set(enum led_color color, int on)
-{
-	switch (color) {
-	case BAT_LED_BLUE:
-		gpio_set_level(GPIO_BAT_LED0, on); /* BAT_LED_BLUE */
-		break;
-	case BAT_LED_ORANGE:
-		gpio_set_level(GPIO_BAT_LED1, on); /* BAT_LED_ORANGE */
-		break;
-	case PWR_LED_BLUE:
-		gpio_set_level(GPIO_PWR_LED0, on); /* PWR_LED_BLUE */
-		break;
-	case PWR_LED_ORANGE:
-		gpio_set_level(GPIO_PWR_LED1, on); /* PWR_LED_ORANGE */
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	/* Ignoring led_id as both leds support the same colors */
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (EC_LED_ID_BATTERY_LED == led_id) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0) {
-			bat_led_set(BAT_LED_BLUE, 1);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		} else if (brightness[EC_LED_COLOR_AMBER] != 0) {
-			bat_led_set(BAT_LED_BLUE, 0);
-			bat_led_set(BAT_LED_ORANGE, 1);
-		} else {
-			bat_led_set(BAT_LED_BLUE, 0);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		}
-		return EC_SUCCESS;
-	} else if (EC_LED_ID_POWER_LED == led_id) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0) {
-			bat_led_set(PWR_LED_BLUE, 1);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		} else if (brightness[EC_LED_COLOR_AMBER] != 0) {
-			bat_led_set(PWR_LED_BLUE, 0);
-			bat_led_set(PWR_LED_ORANGE, 1);
-		} else {
-			bat_led_set(PWR_LED_BLUE, 0);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		}
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static unsigned blink_second;
-
-static void elm_led_set_power(void)
-{
-	/*
-	 * PWR LED behavior:
-	 * Power on: Blue ON
-	 * Suspend: Orange in breeze mode ( 1 sec on/ 3 sec off)
-	 * Power off: OFF
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		bat_led_set(PWR_LED_BLUE, 0);
-		bat_led_set(PWR_LED_ORANGE, 0);
-	} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-		bat_led_set(PWR_LED_BLUE, 1);
-		bat_led_set(PWR_LED_ORANGE, 0);
-	} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-		bat_led_set(PWR_LED_BLUE, 0);
-		bat_led_set(PWR_LED_ORANGE,
-			    (blink_second & 3) ? 0 : 1);
-	}
-}
-
-static void elm_led_set_battery(void)
-{
-	/*
-	 * BAT LED behavior:
-	 * - Fully charged / normal idle: Blue ON
-	 * - Charging: Orange ON
-	 * - Battery discharging capacity<10%, Orange blink(1:3)
-	 *				 < 3%, Orange blink(1:1)
-	 * - Battery error: Orange blink(1:1)
-	 * - Factory force idle: Blue 2 sec, Orange 2 sec
-	 */
-	uint32_t charge_flags = charge_get_flags();
-	int remaining_capacity;
-	int full_charge_capacity;
-	int permillage;
-
-	/* Make the percentage approximate to UI shown */
-	remaining_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
-	full_charge_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	permillage = !full_charge_capacity ? 0 :
-		(1000 * remaining_capacity) / full_charge_capacity;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		if (permillage < FULL_BATTERY_PERMILLAGE) {
-			bat_led_set(BAT_LED_BLUE, 0);
-			bat_led_set(BAT_LED_ORANGE, 1);
-		} else {
-			bat_led_set(BAT_LED_BLUE, 1);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		}
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		bat_led_set(BAT_LED_BLUE, 1);
-		bat_led_set(BAT_LED_ORANGE, 0);
-		break;
-	case PWR_STATE_DISCHARGE:
-		bat_led_set(BAT_LED_BLUE, 0);
-		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-		    permillage <= CRITICAL_LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 1) ? 0 : 1);
-		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			 permillage <= LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 3) ? 0 : 1);
-		else
-			bat_led_set(BAT_LED_ORANGE, 0);
-		break;
-	case PWR_STATE_ERROR:
-		bat_led_set(BAT_LED_BLUE, 0);
-		bat_led_set(BAT_LED_ORANGE, (blink_second & 1) ? 0 : 1);
-		break;
-	case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
-		if (charge_flags & CHARGE_FLAG_FORCE_IDLE) {
-			bat_led_set(BAT_LED_BLUE, (blink_second & 2) ? 0 : 1);
-			bat_led_set(BAT_LED_ORANGE, (blink_second & 2) ? 1 : 0);
-		} else {
-			bat_led_set(BAT_LED_BLUE, 1);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		}
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/**
- * Called by hook task every 1 sec
- */
-static void led_second(void)
-{
-	blink_second++;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		elm_led_set_power();
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		elm_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/elm/usb_pd_policy.c b/board/elm/usb_pd_policy.c
deleted file mode 100644
index 2eeab736d9..0000000000
--- a/board/elm/usb_pd_policy.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/anx7688.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-	/* Provide VBUS */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 1);
-
-	anx7688_set_power_supply_ready(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 0);
-
-	anx7688_power_supply_reset(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since 5V power source is off */
-	return gpio_get_level(GPIO_5V_POWER_GOOD);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int cur_lvl;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	int ack = 1;
-
-	anx7688_update_hpd(port, lvl, irq);
-
-	dp_status[port] = payload[1];
-	cur_lvl = gpio_get_level(GPIO_USB_DP_HPD);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return ack;
-	}
-
-	if (!(irq & cur_lvl) && irq & !cur_lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		ack = 0; /* nak */
-	}
-	/* ack */
-	return ack;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	anx7688_hpd_disable(port);
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/elm/vif_override.xml b/board/elm/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/elm/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/endeavour/board.c b/board/endeavour/board.c
deleted file mode 100644
index f208da3819..0000000000
--- a/board/endeavour/board.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Endeavour board configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/pmic_tps650x30.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "espi.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static uint8_t board_version;
-static uint32_t oem;
-static uint32_t sku;
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* TODO: Verify fan control and mft */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_FAN_PWR_EN,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 5400,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const struct i2c_port_t i2c_ports[]  = {
-	{"pse", I2C_PORT_PSE, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_USB_C0_5V_EN,
-	GPIO_USB_FP0_5V_EN,
-	GPIO_USB_FP1_5V_EN,
-	GPIO_USB_FP3_5V_EN,
-};
-
-/*
- * TMP431 has one local and one remote sensor.
- *
- * Temperature sensors data; must be in same order as enum temp_sensor_id.
- * Sensor index and name must match those present in coreboot:
- *     src/mainboard/google/${board}/acpi/dptf.asl
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
- * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	/* {Twarn, Thigh, Thalt}, <on>
-	 * {Twarn, Thigh, X    }, <off>
-	 * fan_off, fan_max
-	 */
-	{{0, C_TO_K(81), C_TO_K(82)}, {0, C_TO_K(77), 0},
-		C_TO_K(19), C_TO_K(74)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Initialize PMIC */
-#define I2C_PMIC_READ(reg, data) \
-	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-#define I2C_PMIC_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-static void board_pmic_init(void)
-{
-	int err;
-	int error_count = 0;
-	static uint8_t pmic_initialized = 0;
-
-	if (pmic_initialized)
-		return;
-
-	/* Read vendor ID */
-	while (1) {
-		int data;
-		err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data);
-		if (!err && data == TPS650X30_VENDOR_ID)
-			break;
-		else if (error_count > 5)
-			goto pmic_error;
-		error_count++;
-	}
-
-	/*
-	 * VCCIOCNT register setting
-	 * [6] : CSDECAYEN
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * VRMODECTRL:
-	 * [4] : VCCIOLPM clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PGMASK1 : Exclude VCCIO from Power Good Tree
-	 * [7] : MVCCIOPG clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PWFAULT_MASK1 Register settings
-	 * [7] : 1b V4 Power Fault Masked
-	 * [4] : 1b V7 Power Fault Masked
-	 * [2] : 1b V9 Power Fault Masked
-	 * [0] : 1b V13 Power Fault Masked
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 4 register configuration
-	 * [7:6] : 00b Reserved
-	 * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
-	 * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
-	 * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 3 register configuration
-	 * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
-	 * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
-	 * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
-	 * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 2 register configuration
-	 * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
-	 * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
-	 * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
-	 * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 1 register configuration
-	 * [7:2] : 00b Reserved
-	 * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Increase Voltage
-	 *  [7:0] : 0x2a default
-	 *  [5:4] : 10b default
-	 *  [5:4] : 01b 5.1V (0x1a)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PBCONFIG Register configuration
-	 *   [7] :      1b Power button debounce, 0ms (no debounce)
-	 *   [6] :      0b Power button reset timer logic, no action (default)
-	 * [5:0] : 011111b Force an Emergency reset time, 31s (default)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * V3.3A_DSW (VR3) control. Default: 0x2A.
-	 * [7:6] : 00b Disabled
-	 * [5:4] : 00b Vnom + 3%. (default: 10b 0%)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V33ADSWCNT, 0x0A);
-	if (err)
-		goto pmic_error;
-
-	CPRINTS("PMIC init done");
-	pmic_initialized = 1;
-	return;
-
-pmic_error:
-	CPRINTS("PMIC init failed");
-}
-
-void chipset_pre_init_callback(void)
-{
-	board_pmic_init();
-}
-
-/**
- * Notify PCH of the AC presence.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_WHITE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  2, .rpm = 0},
-	{.on = 11, .off =  2, .rpm = 2500},
-	{.on = 38, .off = 29, .rpm = 3200},
-	{.on = 65, .off = 36, .rpm = 3500},
-	{.on = 76, .off = 64, .rpm = 3900},
-	{.on = 84, .off = 75, .rpm = 4500},
-	{.on = 91, .off = 82, .rpm = 5100},
-	{.on = 98, .off = 89, .rpm = 5400},
-};
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-
-static const struct fan_step *fan_table = fan_table0;
-
-
-static void cbi_init(void)
-{
-	uint32_t val;
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT8_MAX)
-		board_version = val;
-	CPRINTS("Board Version: 0x%02x", board_version);
-
-	if (cbi_get_oem_id(&val) == EC_SUCCESS && val < OEM_COUNT)
-		oem = val;
-	CPRINTS("OEM: %d", oem);
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku = val;
-	CPRINTS("SKU: 0x%08x", sku);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	board_extpower();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
-}
diff --git a/board/endeavour/board.h b/board/endeavour/board.h
deleted file mode 100644
index 36afe69d6c..0000000000
--- a/board/endeavour/board.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Endeavour board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#undef  CONFIG_SYSTEM_UNLOCKED
-#define CONFIG_USB_PD_COMM_LOCKED
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_LED_COMMON
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_PWM
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#define CONFIG_FANS 1
-#define CONFIG_FAN_RPM_CUSTOM
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_PWM
-
-/* EC console commands */
-#define CONFIG_CMD_BUTTON
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-#define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP432
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT 4
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_PSE		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-
-/* I2C addresses */
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	PWM_CH_FAN,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-enum OEM_ID {
-	OEM_ENDEAVOUR = 9,
-	/* Number of OEM IDs */
-	OEM_COUNT
-};
-
-/* Board specific handlers */
-void show_critical_error(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/endeavour/build.mk b/board/endeavour/build.mk
deleted file mode 100644
index 20f3f4d02c..0000000000
--- a/board/endeavour/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o
-board-y+=led.o
-board-y+=pse.o
diff --git a/board/endeavour/ec.tasklist b/board/endeavour/ec.tasklist
deleted file mode 100644
index ef58c6267a..0000000000
--- a/board/endeavour/ec.tasklist
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 2048) \
-	/* Larger stack for RW verification (i.e. sha256, rsa) */ \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/endeavour/gpio.inc b/board/endeavour/gpio.inc
deleted file mode 100644
index 85904aab0c..0000000000
--- a/board/endeavour/gpio.inc
+++ /dev/null
@@ -1,93 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(WP_L,			PIN(9, 3), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(RECOVERY_L,		PIN(8, 2), GPIO_INT_BOTH, button_interrupt)	/* Recovery button */
-
-/* TODO(jnchase): configure as interrupt when code is ready / if needed*/
-GPIO(POE_LTC_PGOOD,		PIN(C, 5), GPIO_INPUT)				/* PoE power good */
-GPIO(PSE_PWM_INT,		PIN(3, 7), GPIO_INPUT)				/* PoE LTC interrupt */
-GPIO(V3P3A_I350_PG,		PIN(4, 4), GPIO_INPUT)				/* Disconnected */
-GPIO(USB_C0_VBUS_DET_L,		PIN(9, 7), GPIO_INPUT)				/* USB-C VBUS */
-GPIO(USB_C0_POL_L,		PIN(3, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* USB-C Polarity */
-
-GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
-GPIO(PCH_ACPRESENT,		PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_ODR_HIGH)			/* H1 Reset */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
-GPIO(EC_RST_LTC4291_L,		PIN(9, 4), GPIO_OUT_HIGH)			/* PSE controller reset */
-
-GPIO(POWER_RATE,		PIN(7, 1), GPIO_INPUT)				/* High: i3/5/7. Low: Celeron */
-GPIO(PP3300_USB_PD_EN,		PIN(6, 7), GPIO_OUT_HIGH)                       /* Initialize PP3300_USB_PD_EN as output high */
-
-GPIO(LAN_PWR_EN,		PIN(8, 3), GPIO_OUT_HIGH)			/* Ethernet power enabled */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C_LTC_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C_LTC_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* TP184 */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* TP185 */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_ROP_I2C_CLK */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_ROP_I2C_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT)				/* EC_THEM_CLK */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT)				/* EC_THEM_SDA */
-
-/* 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C0 5V Enable */
-GPIO(USB_C0_VBUS_ILIM,		PIN(3, 5), GPIO_OUT_HIGH)
-GPIO(FAN_PWR_EN,		PIN(9, 5), GPIO_OUT_HIGH)			/* Fan power */
-GPIO(PI3_BC12_DET_L,		PIN(D, 3), GPIO_INPUT)				/* USB-C */
-GPIO(USB_FP3_CHARGE_EN_L,	PIN(C, 6), GPIO_OUT_LOW)			/* USB-C */
-GPIO(USB_FP0_5V_EN,		PIN(0, 0), GPIO_OUT_LOW)			/* Front port 1 */
-GPIO(USB_FP1_5V_EN,		PIN(B, 1), GPIO_OUT_LOW)			/* Front port 2 */
-GPIO(USB_FP3_5V_EN,		PIN(A, 1), GPIO_OUT_LOW)			/* Front port 3 */
-GPIO(USB_FP_CHARGE_EN_L,	PIN(A, 5), GPIO_OUT_LOW)			/* USB-A */
-GPIO(PP3300_TPU_EN,		PIN(0, 1), GPIO_OUT_HIGH)			/* TPU 3.3V enable */
-
-/* Not connected */
-GPIO(USB_C0_CHARGE_L,		PIN(C, 0), GPIO_OUT_LOW)			/* C0 Charge enable */
-GPIO(AC_JACK_CHARGE_L,		PIN(C, 3), GPIO_OUT_LOW)			/* AC jack charge enable */
-GPIO(USB_C0_PD_RST_ODL,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(TYPE_C_65W,		PIN(3, 4), GPIO_OUTPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0)		/* GPIOA6 */		/* TACH2 */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_LTC_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)		/* GPIOB6 */		/* EC_FAN_PWM */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_EEPROM_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
-/* Alternate functions for LED PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)		/* GPIO80 PWM3 Red*/
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)		/* GPOB7 PWM5 Green*/
diff --git a/board/endeavour/led.c b/board/endeavour/led.c
deleted file mode 100644
index b75de503e5..0000000000
--- a/board/endeavour/led.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Endeavour
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec. */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define LED_PULSE_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	LED_PULSE_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend, HOOK_PRIO_DEFAULT);
-
-static void led_shutdown(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task. */
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_resume();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_suspend();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		led_shutdown();
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|off|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/endeavour/pse.c b/board/endeavour/pse.c
deleted file mode 100644
index 671288ccf5..0000000000
--- a/board/endeavour/pse.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
- * controller.
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "string.h"
-#include "timer.h"
-#include "util.h"
-
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
-
-#define I2C_PSE_READ(reg, data) \
-	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define I2C_PSE_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static int pse_write_hpmd(int port, int val)
-{
-	switch (port) {
-	case 0:
-		return I2C_PSE_WRITE(HPMD1, val);
-	case 1:
-		return I2C_PSE_WRITE(HPMD2, val);
-	case 2:
-		return I2C_PSE_WRITE(HPMD3, val);
-	case 3:
-		return I2C_PSE_WRITE(HPMD4, val);
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-/*
- * Port 1: 100W
- * Port 2-4: 15W
- */
-static int pse_port_hpmd[4] = {
-	LTC4291_HPMD_MAX,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-};
-
-static int pse_port_enable(int port)
-{
-	/* Enable detection and classification */
-	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
-}
-
-static int pse_port_disable(int port)
-{
-	/* Request power off (this also disables detection/classification) */
-	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
-}
-
-static int pse_init_worker(void)
-{
-	timestamp_t deadline;
-	int err, id, devid, statpin, port;
-
-	/* Ignore errors -- may already be resetting */
-	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
-
-	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
-	while ((err = I2C_PSE_READ(ID, &id)) != 0) {
-		if (timestamp_expired(deadline, NULL))
-			return err;
-	}
-
-	err = I2C_PSE_READ(DEVID, &devid);
-	if (err != 0)
-		return err;
-
-	if (id != LTC4291_ID || devid != LTC4291_DEVID)
-		return EC_ERROR_INVAL;
-
-	err = I2C_PSE_READ(STATPIN, &statpin);
-	if (err != 0)
-		return err;
-
-	/*
-	 * We don't want to supply power until we've had a chance to set the
-	 * limits.
-	 */
-	if (statpin & LTC4291_FLD_STATPIN_AUTO)
-		CPRINTS("WARN: PSE reset in AUTO mode");
-
-	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
-	if (err != 0)
-		return err;
-
-	/* Set maximum power each port is allowed to allocate. */
-	for (port = 0; port < LTC4291_PORT_MAX; port++) {
-		err = pse_write_hpmd(port, pse_port_hpmd[port]);
-		if (err != 0)
-			return err;
-	}
-
-	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
-	if (err != 0)
-		return err;
-
-	return 0;
-}
-
-static void pse_init(void)
-{
-	int err;
-
-	err = pse_init_worker();
-	if (err != 0)
-		CPRINTS("PSE init failed: %d", err);
-	else
-		CPRINTS("PSE init done");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
-
-/* Also reset the PSE on a reboot to toggle the power. */
-DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
-
-static int command_pse(int argc, char **argv)
-{
-	int port;
-
-	/*
-	 *  TODO(b/156399232): endeavour: PSE controller reset by PLTRST
-	 *
-	 *  Initialization does not reliably work after reset because the device
-	 *  is held in reset by the AP. Running this command after boot finishes
-	 *  always succeeds. Remove once the reset signal changes.
-	 */
-	if (!strncmp(argv[1], "init", 4))
-		return pse_init_worker();
-
-	if (argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if (port < 0 || port >= LTC4291_PORT_MAX)
-		return EC_ERROR_PARAM1;
-
-	if (!strncmp(argv[2], "off", 3))
-		return pse_port_disable(port);
-	else if (!strncmp(argv[2], "on", 2))
-		return pse_port_enable(port);
-	else if (!strncmp(argv[2], "min", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
-	else if (!strncmp(argv[2], "max", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
-	else
-		return EC_ERROR_PARAM2;
-}
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
-			"Set PSE port power");
-
-static int ec_command_pse_status(int port, uint8_t *status)
-{
-	int detena, statpwr;
-	int err;
-
-	err = I2C_PSE_READ(DETENA, &detena);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_READ(STATPWR, &statpwr);
-	if (err != 0)
-		return err;
-
-	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_DISABLED;
-	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_ENABLED;
-	else
-		*status = EC_PSE_STATUS_POWERED;
-
-	return 0;
-}
-
-static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pse *p = args->params;
-	int err = 0;
-
-	if (p->port >= LTC4291_PORT_MAX)
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->cmd) {
-	case EC_PSE_STATUS: {
-		struct ec_response_pse_status *r = args->response;
-
-		args->response_size = sizeof(*r);
-		err = ec_command_pse_status(p->port, &r->status);
-		break;
-	}
-	case EC_PSE_ENABLE:
-		err = pse_port_enable(p->port);
-		break;
-	case EC_PSE_DISABLE:
-		err = pse_port_disable(p->port);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (err)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/board/eve/battery.c b/board/eve/battery.c
deleted file mode 100644
index b5fb949ffe..0000000000
--- a/board/eve/battery.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
-
-/* Vendor CTO command parameter */
-#define SB_VENDOR_PARAM_CTO_DISABLE 0
-/* Flash address of Enabled Protections C Regsiter */
-#define SB_VENDOR_ENABLED_PROTECT_C 0x482C
-/* Expected CTO disable value */
-#define EXPECTED_CTO_DISABLE_VALUE 0x05
-
-/* Vendor OTD Recovery Temperature command parameter */
-#define SB_VENDOR_PARAM_OTD_RECOVERY_TEMP 1
-/* Flash address of OTD Recovery Temperature Register */
-#define SB_VENDOR_OTD_RECOVERY_TEMP 0x486F
-/* Expected OTD recovery temperature in 0.1C */
-#define EXPECTED_OTD_RECOVERY_TEMP 400
-
-enum battery_type {
-	BATTERY_LG,
-	BATTERY_LISHEN,
-	BATTERY_SIMPLO,
-	BATTERY_TYPE_COUNT,
-};
-
-struct board_batt_params {
-	const char *manuf_name;
-	const struct battery_info *batt_info;
-};
-
-/*
- * Set LISHEN as default since the LG precharge current level could cause the
- * LISHEN battery to not accept charge when it's recovering from a fully
- * discharged state.
- */
-#define DEFAULT_BATTERY_TYPE BATTERY_LISHEN
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-/* Battery may delay reporting battery present */
-static int battery_report_present = 1;
-
-/*
- * Battery protect_c register value.
- * Because this value can only be read when the battery is unsealed, the read of
- * this register is only done if the value is changed.
- */
-static int protect_c_reg = -1;
-
-/*
- * Battery OTD recovery temperature register value.
- * Because this value can only be read when the battery is unsealed, the read of
- * this register is only done if the value is changed.
- */
-static int otd_recovery_temp_reg = -1;
-
-/*
- * Battery info for LG A50. Note that the fields start_charging_min/max and
- * charging_min/max are not used for the Eve charger. The effective temperature
- * limits are given by discharging_min/max_c.
- */
-static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
-};
-
-/*
- * Battery info for LISHEN. Note that the fields start_charging_min/max and
- * charging_min/max are not used for the Eve charger. The effective temperature
- * limits are given by discharging_min/max_c.
- */
-static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
-};
-
-static const struct board_batt_params info[] = {
-	[BATTERY_LG] = {
-		.manuf_name = "LG A50",
-		.batt_info = &batt_info_lg,
-	},
-
-	[BATTERY_LISHEN] = {
-		.manuf_name = "Lishen A50",
-		.batt_info = &batt_info_lishen,
-	},
-
-	[BATTERY_SIMPLO] = {
-		.manuf_name = "Simplo A50",
-		.batt_info = &batt_info_lishen,
-	},
-
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	char name[3];
-	int i;
-
-	if (!battery_manufacturer_name(name, sizeof(name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
-				board_battery_type = i;
-				break;
-			}
-		}
-	}
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt: %s", info[board_battery_type].manuf_name);
-	else
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* Can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	/*
-	 * To avoid inrush current from the external charger, enable
-	 * discharge on AC 2till the new charger is detected and charge
-	 * detect delay has passed.
-	 */
-	if (!chg_ramp_is_detected() && curr->batt.state_of_charge > 2)
-		return 1;
-
-	return 0;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	const struct battery_info *batt_info;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-	int disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	batt_info = battery_get_info();
-	/* Don't charge if outside of allowable temperature range */
-	if (bat_temp_c >= batt_info->charging_max_c * 10 ||
-	    bat_temp_c < batt_info->charging_min_c * 10) {
-		curr->requested_current = 0;
-		curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-	}
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATTERY_PRESENT_L) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/* Allow booting now that the battery has woke up */
-static void battery_now_present(void)
-{
-	CPRINTS("battery will now report present");
-	battery_report_present = 1;
-}
-DECLARE_DEFERRED(battery_now_present);
-
-/*
- * Check for case where XDSG bit is set indicating that even
- * though the FG can be read from the battery, the battery is not able to be
- * charged or discharged. This situation will happen if a battery disconnect was
- * intiaited via H1 setting the DISCONN signal to the battery. This will put the
- * battery pack into a sleep state and when power is reconnected, the FG can be
- * read, but the battery is still not able to provide power to the system. The
- * calling function returns batt_pres = BP_NO, which instructs the charging
- * state machine to prevent powering up the AP on battery alone which could lead
- * to a brownout event when the battery isn't able yet to provide power to the
- * system. .
- */
-static int battery_check_disconnect(void)
-{
-	int rv;
-	uint8_t data[6];
-
-	/* Check if battery discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if (data[3] & BATTERY_DISCHARGING_DISABLED)
-		return BATTERY_DISCONNECTED;
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-	static int battery_report_present_timer_started;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-	    (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	     battery_check_disconnect() != BATTERY_NOT_DISCONNECTED ||
-	     battery_init() == 0)) {
-		battery_report_present = 0;
-	} else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
-		   !battery_report_present_timer_started) {
-		/*
-		 * Wait 1 second before reporting present if it was
-		 * previously reported as not present
-		 */
-		battery_report_present_timer_started = 1;
-		battery_report_present = 0;
-		hook_call_deferred(&battery_now_present_data, SECOND);
-	}
-
-	if (!battery_report_present)
-		batt_pres = BP_NO;
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
-
-int board_battery_initialized(void)
-{
-	return battery_hw_present() == batt_pres_prev;
-}
-
-static int board_battery_sb_write(uint8_t access, int cmd)
-{
-	int rv;
-	uint8_t buf[1 + sizeof(uint16_t)];
-
-	/*
-	 * Note, the i2c_lock must be handled by the calling function. The
-	 * battery unseal operation requires two writes without any other access
-	 * taking place. Therefore the calling function handles when to
-	 * grab/release the lock.
-	 */
-
-	buf[0] = access;
-	buf[1] = cmd & 0xff;
-	buf[2] = (cmd >> 8) & 0xff;
-
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-		      buf, 1 + sizeof(uint16_t), NULL, 0);
-
-	return rv;
-}
-
-int board_battery_read_mfgacc(int offset, int access,
-				      uint8_t *buf, int len)
-{
-	int rv;
-	uint8_t block_len, reg;
-
-	/* start read */
-	i2c_lock(I2C_PORT_BATTERY, 1);
-
-	/* Send write block */
-	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS, offset);
-	if (rv) {
-		i2c_lock(I2C_PORT_BATTERY, 0);
-		return rv;
-	}
-
-	reg = access;
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, &reg, 1,
-	    &block_len, 1, I2C_XFER_START);
-	if (rv) {
-		i2c_lock(I2C_PORT_BATTERY, 0);
-		return rv;
-	}
-
-	/* Compare block length to desired read length */
-	if (len && (block_len > len))
-		block_len = len;
-
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, NULL, 0,
-	    buf, block_len, I2C_XFER_STOP);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	return rv;
-}
-
-static int board_battery_unseal(uint32_t param)
-{
-	int rv;
-	uint8_t data[6];
-
-	/* Get Operation Status */
-	rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	if ((data[3] & 0x3) == 0x3) {
-		/*
-		 * Hold the lock for both writes to ensure that no other
-		 * manufactuer access opertion can take place.
-		 */
-		i2c_lock(I2C_PORT_BATTERY, 1);
-		rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS,
-					    param & 0xffff);
-		if (rv)
-			goto unseal_fail;
-
-		rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS,
-					    (param >> 16) & 0xffff);
-		if (rv)
-			goto unseal_fail;
-
-		i2c_lock(I2C_PORT_BATTERY, 0);
-
-		/* Verify that battery is unsealed */
-		rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-		if (rv || ((data[3] & 0x3) != 0x2))
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-
-unseal_fail:
-	i2c_lock(I2C_PORT_BATTERY, 0);
-	return EC_RES_ERROR;
-}
-
-static int board_battery_seal(void)
-{
-	int rv;
-
-	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS,  0x0030);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_SUCCESS;
-}
-
-static int board_battery_write_flash(int addr, uint32_t data, int len)
-{
-	int rv;
-	uint8_t buf[sizeof(uint32_t) + 4];
-
-	if (len > 4)
-		return EC_ERROR_INVAL;
-
-	buf[0] = SB_ALT_MANUFACTURER_ACCESS;
-	/* Number of bytes to write, including the address */
-	buf[1] = len + 2;
-	/* Put in the flash address */
-	buf[2] = addr & 0xff;
-	buf[3] = (addr >> 8) & 0xff;
-
-	/* Add data to be written */
-	buf[4] = data & 0xff;
-	buf[5] = (data >> 8) & 0xff;
-	buf[6] = (data >> 16) & 0xff;
-	buf[7] = (data >> 24) & 0xff;
-	/* Account for command, length, and address */
-	len += 4;
-
-	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf,
-		      len, NULL, 0);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	return rv;
-}
-
-static int board_battery_read_flash(int block, int len, uint8_t *buf)
-{
-	uint8_t data[6];
-	int rv;
-	int i;
-
-	if (len > 4)
-		len = 4;
-	rv = board_battery_read_mfgacc(block,
-			    SB_ALT_MANUFACTURER_ACCESS, data, len + 2);
-	if (rv)
-		return EC_RES_ERROR;
-
-	for (i = 0; i < len; i++)
-		buf[i] = data[i+2];
-
-	return EC_SUCCESS;
-}
-
-static int board_battery_disable_cto(uint32_t value)
-{
-	uint8_t protect_c;
-
-	if (board_battery_unseal(value))
-		return EC_RES_ERROR;
-
-	/* Check CTO enable */
-	if (board_battery_read_flash(SB_VENDOR_ENABLED_PROTECT_C, 1,
-				     &protect_c)) {
-		board_battery_seal();
-		return EC_RES_ERROR;
-	}
-
-	if (protect_c != EXPECTED_CTO_DISABLE_VALUE) {
-		board_battery_write_flash(SB_VENDOR_ENABLED_PROTECT_C,
-					  EXPECTED_CTO_DISABLE_VALUE, 1);
-		/* After flash write, allow time for it to complete */
-		msleep(100);
-		/* Read the current protect_c register value */
-		if (board_battery_read_flash(SB_VENDOR_ENABLED_PROTECT_C, 1,
-					     &protect_c) == EC_SUCCESS)
-			protect_c_reg = protect_c;
-	} else {
-		protect_c_reg = protect_c;
-	}
-
-	if (board_battery_seal()) {
-		/* If failed, then wait one more time and seal again */
-		msleep(100);
-		if (board_battery_seal())
-			return EC_RES_ERROR;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int board_battery_fix_otd_recovery_temp(uint32_t value)
-{
-	int16_t otd_recovery_temp;
-
-	if (board_battery_unseal(value))
-		return EC_RES_ERROR;
-
-	/* Check current OTD recovery temp */
-	if (board_battery_read_flash(SB_VENDOR_OTD_RECOVERY_TEMP, 2,
-				     (uint8_t *)&otd_recovery_temp)) {
-		board_battery_seal();
-		return EC_RES_ERROR;
-	}
-
-	if (otd_recovery_temp != EXPECTED_OTD_RECOVERY_TEMP) {
-		board_battery_write_flash(SB_VENDOR_OTD_RECOVERY_TEMP,
-					  EXPECTED_OTD_RECOVERY_TEMP, 2);
-		/* After flash write, allow time for it to complete */
-		msleep(100);
-		/* Read the current OTD recovery temperature */
-		if (!board_battery_read_flash(SB_VENDOR_OTD_RECOVERY_TEMP, 2,
-					      (uint8_t *)&otd_recovery_temp))
-			otd_recovery_temp_reg = otd_recovery_temp;
-	} else {
-			otd_recovery_temp_reg = otd_recovery_temp;
-	}
-
-	if (board_battery_seal()) {
-		/* If failed, then wait one more time and seal again */
-		msleep(100);
-		if (board_battery_seal())
-			return EC_RES_ERROR;
-	}
-
-	return EC_SUCCESS;
-}
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	/*
-	 * These registers can't be read directly because the flash area
-	 * of the battery is protected, unless it's been
-	 * unsealed. The key is only able to be passed in the set
-	 * function. The get function is always called following the set
-	 * function. Therefore when the set function is called, this
-	 * register value is read and saved to protect_c_reg. If this
-	 * value is < 0, then the set function wasn't called and
-	 * therefore the value can't be known.
-	 */
-	switch (param) {
-	case SB_VENDOR_PARAM_CTO_DISABLE:
-		if (protect_c_reg >= 0) {
-			*value = protect_c_reg;
-			return EC_SUCCESS;
-		}
-		break;
-	case SB_VENDOR_PARAM_OTD_RECOVERY_TEMP:
-		if (otd_recovery_temp_reg >= 0) {
-			*value = otd_recovery_temp_reg;
-			return EC_SUCCESS;
-		}
-		break;
-	default:
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-	return EC_RES_ERROR;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	switch (param) {
-	case SB_VENDOR_PARAM_CTO_DISABLE:
-		if (board_battery_disable_cto(value))
-			return EC_ERROR_UNKNOWN;
-		break;
-	case SB_VENDOR_PARAM_OTD_RECOVERY_TEMP:
-		if (board_battery_fix_otd_recovery_temp(value))
-			return EC_ERROR_UNKNOWN;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/eve/board.c b/board/eve/board.c
deleted file mode 100644
index f73118e8f2..0000000000
--- a/board/eve/board.c
+++ /dev/null
@@ -1,981 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board-specific configuration */
-
-#include "acpi.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "device_event.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kxcj9.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_si114x.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/bd99992gw.h"
-#include "extpower.h"
-#include "gesture.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "keyboard_8042_sharedlib.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-/*
- * enable_input_devices() is called by the tablet_mode ISR, but changes the
- * state of GPIOs, so its definition must reside after including gpio_list.
- */
-static void enable_input_devices(void);
-DECLARE_DEFERRED(enable_input_devices);
-
-#define LID_DEBOUNCE_US	(30 * MSEC)
-void tablet_mode_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
-}
-
-/* Send event to wake AP based on trackpad input */
-void trackpad_interrupt(enum gpio_signal signal)
-{
-	device_set_single_event(EC_DEVICE_EVENT_TRACKPAD);
-}
-
-/* Send event to wake AP based on DSP interrupt */
-void dsp_interrupt(enum gpio_signal signal)
-{
-	device_set_single_event(EC_DEVICE_EVENT_DSP);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void anx74xx_c0_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_c0_cable_det_handler);
-
-static void anx74xx_c1_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C1_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C1_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C1, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_c1_cable_det_handler);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* Check if it is port 0 or 1, and debounce for 2 msec. */
-	if (signal == GPIO_USB_C0_CABLE_DET)
-		hook_call_deferred(&anx74xx_c0_cable_det_handler_data,
-				   (2 * MSEC));
-	else
-		hook_call_deferred(&anx74xx_c1_cable_det_handler_data,
-				   (2 * MSEC));
-}
-#endif
-
-#include "gpio_list.h"
-
-/* Keyboard scan. Increase output_settle_us to 80us from default 50us. */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]     = { 5, 0, 10000 },
-	[PWM_CH_LED_L_RED]   = { 2, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_L_GREEN] = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_L_BLUE]  = { 4, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_RED]   = { 1, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_BLUE]  = { 6, PWM_CONFIG_DSLEEP, 100 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     I2C_PORT_TCPC0,    400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     I2C_PORT_TCPC1,    400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"accelgyro", I2C_PORT_GYRO,     400, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"sensors",   I2C_PORT_LID_ACCEL, 400, GPIO_I2C2_SCL,  GPIO_I2C2_SDA},
-	{"batt",      I2C_PORT_BATTERY,  100, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BD9995X_ADDR_FLAGS,
-		.drv = &bd9995x_drv,
-	},
-};
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	switch (port) {
-	case 0:
-		if (mode) {
-			gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1);
-			msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-			gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-		} else {
-			gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-			msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-			gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
-			msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		}
-		break;
-	case 1:
-		if (mode) {
-			gpio_set_level(GPIO_USB_C1_TCPC_PWR, 1);
-			msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-			gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-		} else {
-			gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-			msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-			gpio_set_level(GPIO_USB_C1_TCPC_PWR, 0);
-			msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		}
-		break;
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-	/* Disable power */
-	gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
-	gpio_set_level(GPIO_USB_C1_TCPC_PWR, 0);
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	/* Enable power */
-	gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1);
-	gpio_set_level(GPIO_USB_C1_TCPC_PWR, 1);
-	msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-	/* Deassert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int count = 0;
-	int port;
-
-	/* Wait for disconnected battery to wake up */
-	while (battery_hw_present() == BP_YES &&
-	       battery_is_present() == BP_NO) {
-		usleep(100 * MSEC);
-		/* Give up waiting after 2 seconds */
-		if (++count > 20)
-			break;
-	}
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-	gpio_enable_interrupt(GPIO_USB_C1_CABLE_DET);
-#endif
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-static void board_pmic_init(void)
-{
-	board_report_pmic_fault("SYSJUMP");
-
-	/* Clear power source events */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x04, 0xff);
-
-	/* Disable power button shutdown timer */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x14, 0x00);
-
-	/* Disable VCCIO in ALL_SYS_PWRGD for early boards */
-	if (board_get_version() <= BOARD_VERSION_DVTB)
-		i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, 0x80);
-
-	if (system_jumped_late())
-		return;
-
-	/* DISCHGCNT2 - enable 100 ohm discharge on V3.3A and V1.8A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3d, 0x05);
-
-	/* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x04);
-
-	/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x7a);
-
-	/*
-	 * Set V100ACNT / V1.00A Control Register:
-	 * Nominal output = 1.0V.
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
-
-	/*
-	 * Set V085ACNT / V0.85A Control Register:
-	 * Lower power mode = 0.7V.
-	 * Nominal output = 1.0V.
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
-
-	/* VRMODECTRL - disable low-power mode for all rails */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x1f);
-}
-DECLARE_DEFERRED(board_pmic_init);
-
-static void board_set_tablet_mode(void)
-{
-	int flipped_360_mode = !gpio_get_level(GPIO_TABLET_MODE_L);
-
-	tablet_set_mode(flipped_360_mode, TABLET_TRIGGER_LID);
-
-	/* Update DPTF profile based on mode */
-	if (flipped_360_mode)
-		acpi_dptf_set_profile_num(DPTF_PROFILE_FLIPPED_360_MODE);
-	else
-		acpi_dptf_set_profile_num(DPTF_PROFILE_CLAMSHELL);
-}
-
-int board_has_working_reset_flags(void)
-{
-	int version = board_get_version();
-
-	/* board version P1b to EVTb will lose reset flags on power cycle */
-	if (version >= BOARD_VERSION_P1B && version <= BOARD_VERSION_EVTB)
-		return 0;
-
-	/* All other board versions should have working reset flags */
-	return 1;
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enabure tablet mode is initialized */
-	board_set_tablet_mode();
-
-	/* Enable tablet mode interrupt for input device enable */
-	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-
-#ifndef TEST_BUILD
-	if (board_get_version() == BOARD_VERSION_EVT) {
-		/* Set F13 to new defined key on EVT */
-		CPRINTS("Overriding F13 scan code");
-		set_scancode_set2(3, 9, 0xe007);
-#ifdef CONFIG_KEYBOARD_DEBUG
-		set_keycap_label(3, 9, KLLI_F13);
-#endif
-	}
-#endif
-
-	/* Initialize PMIC */
-	hook_call_deferred(&board_pmic_init_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum pd_dual_role_states pd_get_drp_state_in_suspend(void)
-{
-	/*
-	 * If board is not connected to charger it will disable VBUS
-	 * on all ports that acts as source when going to suspend.
-	 * Change DRP state to force sink, to inform TCPM about that.
-	 */
-	if (!extpower_is_present())
-		return PD_DRP_FORCE_SINK;
-
-	return PD_DRP_TOGGLE_OFF;
-}
-
-/**
- * Buffer the AC present GPIO to the PCH.
- * Set appropriate DRP state when chipset in suspend
- */
-static void board_extpower(void)
-{
-	enum pd_dual_role_states drp_state;
-	int port;
-
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND)) {
-		drp_state = pd_get_drp_state_in_suspend();
-		for (port = 0; port < board_get_usb_pd_port_count(); port++)
-			if (pd_get_dual_role(port) != drp_state)
-				pd_set_dual_role(port, drp_state);
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port != 0 && port != 1)
-		panic("Invalid charge port\n");
-
-	return bd9995x_is_vbus_provided(port);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	enum bd9995x_charge_port bd9995x_port;
-	int bd9995x_port_select = 1;
-
-	switch (charge_port) {
-	case 0:
-	case 1:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-
-		bd9995x_port = charge_port;
-		break;
-	case CHARGE_PORT_NONE:
-		bd9995x_port_select = 0;
-		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
-
-		/*
-		 * To avoid inrush current from the external charger,
-		 * enable discharge on AC until the new charger is detected
-		 * and charge detect delay has passed.
-		 */
-		if (charge_get_percent() > 2)
-			charger_discharge_on_ac(1);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Enable charging trigger by BC1.2 detection */
-	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
-			   supplier == CHARGE_SUPPLIER_BC12_DCP ||
-			   supplier == CHARGE_SUPPLIER_BC12_SDP ||
-			   supplier == CHARGE_SUPPLIER_OTHER);
-
-	if (bd9995x_bc12_enable_charging(port, bc12_enable))
-		return;
-
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < BD9995X_BC12_MIN_VOLTAGE;
-}
-
-/* Clear pending interrupts and enable DSP for wake */
-static void dsp_wake_enable(int enable)
-{
-	if (enable) {
-		gpio_clear_pending_interrupt(GPIO_MIC_DSP_IRQ_1V8_L);
-		gpio_enable_interrupt(GPIO_MIC_DSP_IRQ_1V8_L);
-	} else {
-		gpio_disable_interrupt(GPIO_MIC_DSP_IRQ_1V8_L);
-	}
-}
-
-/* Clear pending interrupts and enable trackpad for wake */
-static void trackpad_wake_enable(int enable)
-{
-	static int prev_enable = -1;
-
-	if (prev_enable == enable)
-		return;
-	prev_enable = enable;
-
-	if (enable) {
-		gpio_clear_pending_interrupt(GPIO_TRACKPAD_INT_L);
-		gpio_enable_interrupt(GPIO_TRACKPAD_INT_L);
-	} else {
-		gpio_disable_interrupt(GPIO_TRACKPAD_INT_L);
-	}
-}
-
-/* Enable or disable input devices, based upon chipset state and tablet mode */
-static void enable_input_devices(void)
-{
-	/* We need to turn on tablet mode for motion sense */
-	board_set_tablet_mode();
-
-	/*
-	 * Then, we disable peripherals only when the lid reaches 360 position.
-	 * (It's probably already disabled by motion_sense_task.)
-	 * We deliberately do not enable peripherals when the lid is leaving
-	 * 360 position. Instead, we let motion_sense_task enable it once it
-	 * reaches laptop zone (180 or less).
-	 */
-	if (tablet_get_mode())
-		lid_angle_peripheral_enable(0);
-}
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If suspended and the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard and trackpad wake.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-	   (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND)))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-
-	/* Also disable trackpad wake if not in suspend */
-	if (!chipset_in_state(CHIPSET_STATE_SUSPEND))
-		enable = 0;
-	trackpad_wake_enable(enable);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	/* Enable Trackpad */
-	gpio_set_level(GPIO_TRACKPAD_SHDN_L, 1);
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable Trackpad and DSP wake in S5 */
-	trackpad_wake_enable(0);
-	dsp_wake_enable(0);
-	gpio_set_level(GPIO_TRACKPAD_SHDN_L, 0);
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	if (lid_is_open()) {
-		/* Enable DSP wake if suspended with lid open */
-		dsp_wake_enable(1);
-
-		/* Enable trackpad wake if suspended and not in tablet mode */
-		if (!tablet_get_mode())
-			trackpad_wake_enable(1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	dsp_wake_enable(0);
-	trackpad_wake_enable(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-/* Called on lid change */
-static void board_lid_change(void)
-{
-	/* Disable trackpad and DSP wake if lid is closed */
-	if (!lid_is_open()) {
-		trackpad_wake_enable(0);
-		dsp_wake_enable(0);
-	}
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, board_lid_change, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/* Enable both the VBUS & VCC ports before entering PG3 */
-	bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
-
-	/* Turn BGATE OFF for power saving */
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_MAX);
-
-	/* Shut down PMIC */
-	CPRINTS("Triggering PMIC shutdown");
-	uart_flush_output();
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
-		/*
-		 * If we can't tell the PMIC to shutdown, instead reset
-		 * and don't start the AP. Hopefully we'll be able to
-		 * communicate with the PMIC next time.
-		 */
-		CPRINTS("PMIC I2C failed");
-		uart_flush_output();
-		system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
-	}
-	while (1)
-		;
-}
-
-int board_get_version(void)
-{
-	static int ver;
-
-	if (!ver) {
-		/*
-		 * Read the board EC ID on the tristate strappings
-		 * using ternary encoding: 0 = 0, 1 = 1, Hi-Z = 2
-		 */
-		uint8_t id0, id1, id2;
-
-		id0 = gpio_get_ternary(GPIO_BOARD_VERSION1);
-		id1 = gpio_get_ternary(GPIO_BOARD_VERSION2);
-		id2 = gpio_get_ternary(GPIO_BOARD_VERSION3);
-
-		ver = (id2 * 9) + (id1 * 3) + id0;
-		CPRINTS("Board ID = %d", ver);
-	}
-
-	return ver;
-}
-
-void sensor_board_proc_double_tap(void)
-{
-	led_register_double_tap();
-}
-
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-
-static struct kionix_accel_data g_kxcj9_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-static struct si114x_drv_data_t g_si114x_data = {
-	.state = SI114X_NOT_READY,
-	.covered = 0,
-	.type_data = {
-		/* Proximity - unused */
-		{
-		},
-		/* light */
-		{
-			.base_data_reg = SI114X_ALS_VIS_DATA0,
-			.irq_flags = SI114X_IRQ_ENABLE_ALS_IE_INT0 |
-				     SI114X_IRQ_ENABLE_ALS_IE_INT1,
-			.scale = 1,
-			.offset = -256,
-		}
-	}
-};
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KXCJ9,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kxcj9_data,
-	 .port = I2C_PORT_LID_ACCEL,
-	 .i2c_spi_addr_flags = KXCJ9_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, enough for lid angle calculation. */
-	 .min_frequency = KXCJ9_ACCEL_MIN_FREQ,
-	 .max_frequency = KXCJ9_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = TAP_ODR,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = TAP_ODR,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on in S5 for battery detection */
-		 [SENSOR_CONFIG_EC_S5] = {
-			.odr = TAP_ODR,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[BASE_MAG] = {
-	 .name = "Base Mag",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_MAG,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = BIT(11), /* 16LSB / uT, fixed */
-	 .rot_standard_ref = &mag_standard_ref,
-	 .min_frequency = BMM150_MAG_MIN_FREQ,
-	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
-
-	[LID_LIGHT] = {
-	 .name = "Light",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_SI1141,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &si114x_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_si114x_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = SI114X_ADDR_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 6000, /* 60.00%: int = 0 - frac = 6000/10000 */
-	 .min_frequency = SI114X_LIGHT_MIN_FREQ,
-	 .max_frequency = SI114X_LIGHT_MAX_FREQ,
-	 .config = {
-		 /* Run ALS sensor in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 1000,
-		 },
-	 },
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_LIGHT],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
diff --git a/board/eve/board.h b/board/eve/board.h
deleted file mode 100644
index df80e4dccf..0000000000
--- a/board/eve/board.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_DEVICE_EVENT
-#define CONFIG_DPTF
-#define CONFIG_DPTF_MULTI_PROFILE
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-/* 7 day delay before hibernate */
-#undef  CONFIG_HIBERNATE_DELAY_SEC
-#define CONFIG_HIBERNATE_DELAY_SEC (3600 * 24 * 7)
-/* 1 day delay before hibernate if battery is less than 10% */
-#define CONFIG_HIBERNATE_BATT_PCT 10
-#define CONFIG_HIBERNATE_BATT_SEC (3600 * 24)
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 256
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-
-/* EC console history configuration */
-#undef  CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 1
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_TABLET_MODE
-
-/* Battery */
-#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_VENDOR_PARAM
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BD9995X
-#define CONFIG_CHARGER_BD9995X_CHGEN
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
-#define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-
-/* Sensor */
-#define CONFIG_MKBP_EVENT
-/* Don't wake up from suspend on any MKBP event. */
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK 0
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCEL_KXCJ9
-#define CONFIG_ALS_SI114X 0x40
-#define CONFIG_ALS_SI114X_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_LIGHT)
-#define CONFIG_ALS_SI114X_POLLING
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT  /* Unused */
-#define CONFIG_MAG_CALIBRATE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_INVALID_CHECK
-#define CONFIG_LID_ANGLE_TABLET_MODE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Enable double tap detection */
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_HOST_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
-#define CONFIG_GESTURE_TAP_THRES_MG 100
-#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
-#define CONFIG_GESTURE_TAP_SENSOR 1
-
-/* USB */
-#define CONFIG_USB_PID 0x504B
-
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_TCPC_BOARD_INIT
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_ANX3429
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#undef CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
-#define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 2
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT1
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_LID_ACCEL	NPCX_I2C_PORT2
-#define I2C_PORT_ALS		NPCX_I2C_PORT2
-#define I2C_PORT_PMIC		NPCX_I2C_PORT3
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-#define I2C_PORT_MP2949		NPCX_I2C_PORT3
-
-/* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum board_version_list {
-	BOARD_VERSION_P0,
-	BOARD_VERSION_P0B,
-	BOARD_VERSION_P1,
-	BOARD_VERSION_P1B,
-	BOARD_VERSION_EVT,
-	BOARD_VERSION_EVTB,
-	BOARD_VERSION_DVT,
-	BOARD_VERSION_DVTB,
-	BOARD_VERSION_PVT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_GYRO,
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * The PWM channel enums for the LEDs need to be in Red, Green, Blue order as
- * the 'set_color()' function assumes this order. The left vs right order
- * doesn't matter as long as each side follows RGB order.
- */
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_L_RED,
-	PWM_CH_LED_L_GREEN,
-	PWM_CH_LED_L_BLUE,
-	PWM_CH_LED_R_RED,
-	PWM_CH_LED_R_GREEN,
-	PWM_CH_LED_R_BLUE,
-	PWM_CH_COUNT
-};
-
-/*
- * For backward compatibility, to report ALS via ACPI,
- * Define the number of ALS sensors: motion_sensor copy the data to the ALS
- * memmap region.
- */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	BASE_MAG,
-	LID_LIGHT,
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_CH_COUNT
-};
-
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-int board_get_version(void);
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void board_tcpc_init(void);
-void led_register_double_tap(void);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(LID_LIGHT))
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/eve/build.mk b/board/eve/build.mk
deleted file mode 100644
index f47b5d9caf..0000000000
--- a/board/eve/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/eve/ec.tasklist b/board/eve/ec.tasklist
deleted file mode 100644
index 99de365243..0000000000
--- a/board/eve/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/eve/gpio.inc b/board/eve/gpio.inc
deleted file mode 100644
index f9b0c3cfc4..0000000000
--- a/board/eve/gpio.inc
+++ /dev/null
@@ -1,126 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(CHARGER_INT_L,		PIN(3, 3), GPIO_INT_FALLING,			bd9995x_vbus_interrupt)
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(9, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(6, 7), GPIO_INT_BOTH,			lid_interrupt)
-GPIO_INT(TABLET_MODE_L,		PIN(3, 6), GPIO_INT_BOTH,			tablet_mode_interrupt)
-/* Volume buttons are swapped in the schematic */
-GPIO_INT(VOLUME_DOWN_L,		PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(WP_L,			PIN(4, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(ACCELGYRO3_INT_L,	PIN(9, 3), GPIO_INT_FALLING,			bmi160_interrupt)
-GPIO_INT(TRACKPAD_INT_L,	PIN(7, 1), GPIO_INT_FALLING,			trackpad_interrupt)
-/* DSP IRQ is active low in schematic but DSP treats as active high */
-GPIO_INT(MIC_DSP_IRQ_1V8_L,	PIN(C, 6), GPIO_INT_RISING | GPIO_SEL_1P8V,	dsp_interrupt)
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-GPIO_INT(USB_C0_CABLE_DET,      PIN(D, 2), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-GPIO_INT(USB_C1_CABLE_DET,      PIN(D, 3), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-#else
-GPIO(USB_C0_CABLE_DET,          PIN(D, 2), GPIO_INPUT)
-GPIO(USB_C1_CABLE_DET,          PIN(D, 3), GPIO_INPUT)
-#endif
-
-/* Lid KCJX9 accelerometer sensor interrupt */
-GPIO(ACCEL1_INT_L,		PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC */
-GPIO(ENABLE_BACKLIGHT,		PIN(5, 6), GPIO_OUT_LOW)			/* Enable Backlight */
-GPIO(TRACKPAD_SHDN_L,		PIN(3, 2), GPIO_OUT_LOW)			/* Enable Trackpad */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CHARGER_RST_ODL,		PIN(0, 1), GPIO_INPUT | GPIO_PULL_UP)		/* CHARGER_RST_ODL, no-connect */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_LOW)			/* PROCHOT to SOC */
-GPIO(PCH_ACOK,			PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(4, 1), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(A, 6), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(BATTERY_PRESENT_L,		PIN(3, 4), GPIO_INPUT)				/* Battery Present */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_INPUT | GPIO_PULL_UP)			/* H1 Reset, no-connect */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C00_USB_C0_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C00_USB_C0_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C01_USB_C1_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C01_USB_C1_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C1_GYRO_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C1_GYRO_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C2_SENSOR_3V3_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C2_SENSOR_3V3_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT)				/* EC_I2C3_POWER_SCL */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT)				/* EC_I2C3_POWER_SDA */
-
-/*
- * For P1 and prior: 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A
- * For P1B and later: 5V enables: OUT_LOW=VBUS Off, OUT_HIGH=VBUS On
- */
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C0 5V Enable */
-GPIO(USB_C1_5V_EN,		PIN(B, 1), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C1 5V Enable */
-GPIO(EN_USB_C0_3A,		PIN(6, 6), GPIO_OUT_LOW)			/* 1.5/3.0 C0 current limit selection */
-GPIO(EN_USB_C1_3A,		PIN(3, 5), GPIO_OUT_LOW)			/* 1.5/3.0 C1 current limit selection */
-GPIO(USB_C0_PD_RST_L,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(7, 4), GPIO_OUT_LOW)			/* C1 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(A, 5), GPIO_INPUT)				/* C1 DP Hotplug Detect */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB_C1_TCPC_PWR,		PIN(0, 0), GPIO_OUT_LOW)			/* Enable C1 TCPC Power */
-GPIO(USB2_OTG_ID,		PIN(A, 1), GPIO_OUT_LOW)			/* OTG ID */
-GPIO(USB2_OTG_VBUSSENSE,	PIN(9, 5), GPIO_OUT_LOW)			/* OTG VBUS Sense */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(4, 3), GPIO_INPUT | GPIO_PULL_UP)		/* Board ID bit0 */
-GPIO(BOARD_VERSION2,		PIN(4, 4), GPIO_INPUT | GPIO_PULL_UP)		/* Board ID bit1 */
-GPIO(BOARD_VERSION3,		PIN(4, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Board ID bit2 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_GYRO_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_GYRO_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_SENSOR_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C00_USB_C0_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C01_USB_C1_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_POWER_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)		/* GPIOB7 */		/* KBD_BL_PWM */
-/* Left LED PWM Channels */
-ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0)		/* GPIOC4 PWM2 Red*/
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)		/* GPOB6  PWM3 Green*/
-ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)		/* GPIO80 PWM4 Blue*/
-/* Right LED PWM Channels */
-ALTERNATE(PIN_MASK(C, 0x04), 1, MODULE_PWM, 0)		/* GPIOC2 PWM1 Red*/
-ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0)		/* GPIOC3 PWM0 Green */
-ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)		/* GPIOC0 PWM6 Blue */
-
-/* Set unused pins as Input+PU */
-GPIO(TP_EC_GPIO_57,   PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT		(GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT		(GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2	(GPIO_OUT_LOW)
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2,			PIN(1, 7), GPIO_KB_OUTPUT_COL2)
diff --git a/board/eve/led.c b/board/eve/led.c
deleted file mode 100644
index 91a7b24a2b..0000000000
--- a/board/eve/led.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power/Battery LED control for Eve
- */
-
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "math_util.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_PWM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-#define LED_TICK_TIME (500 * MSEC)
-#define LED_TICKS_PER_BEAT 1
-#define NUM_PHASE 2
-#define DOUBLE_TAP_TICK_LEN (LED_TICKS_PER_BEAT * 8)
-#define LED_FRAC_BITS 4
-#define LED_STEP_MSEC 45
-
-/*
- * The PWM % on levels to transition from intensity 0 (black) to intensity 1.0
- * (white) in the HSI color space converted back to RGB space (0 - 255) and
- * converted to a % for PWM. This table is used for Red <--> White and Green
- * <--> Transitions. In HSI space white = (0, 0, 1), red = (0, .5, .33), green =
- * (120, .5, .33). For the transitions of interest only S and I are changed and
- * they are changed linearly in HSI space.
- */
-static const uint8_t trans_steps[] = {0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100};
-
-/* List of LED colors used */
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_BLUE,
-	LED_WHITE,
-	LED_RED_HALF,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-/* List of supported LED patterns */
-enum led_pattern {
-	OFF = 0,
-	SOLID_GREEN,
-	WHITE_GREEN,
-	SOLID_WHITE,
-	WHITE_RED,
-	SOLID_RED,
-	PULSE_RED,
-	BLINK_RED,
-	LED_NUM_PATTERNS,
-};
-
-enum led_side {
-	LED_LEFT = 0,
-	LED_RIGHT,
-	LED_BOTH
-};
-
-struct led_info {
-	/* LED pattern manage variables */
-	int ticks;
-	int pattern_sel;
-	int tap_tick_count;
-	enum led_color color;
-	/* Color transition variables */
-	int state;
-	int step;
-	uint8_t rgb_current[3];
-	const uint8_t *rgb_target;
-	uint8_t trans[ARRAY_SIZE(trans_steps)];
-};
-
-/*
- * LED patterns are described as two phases. Each phase has an associated LED
- * color and length in beats. The length of each beat is defined by the macro
- * LED_TICKS_PER_BEAT.
- */
-struct led_phase {
-	uint8_t color[NUM_PHASE];
-	uint8_t len[NUM_PHASE];
-	uint8_t tap_len;
-};
-
-static int led_debug;
-static int double_tap;
-static int led_charge_side;
-static struct led_info led[LED_BOTH];
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * Pattern table. The len field is beats per color. 0 for len indicates that a
- * particular pattern never changes from the first phase.
- */
-static const struct led_phase pattern[LED_NUM_PATTERNS] = {
-	{ {LED_OFF, LED_OFF}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_GREEN, LED_GREEN}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_GREEN}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_WHITE}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_RED}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_RED, LED_RED}, {0, 0},  DOUBLE_TAP_TICK_LEN},
-	{ {LED_RED, LED_RED_HALF}, {4, 4}, DOUBLE_TAP_TICK_LEN * 2 +
-	  DOUBLE_TAP_TICK_LEN / 2},
-	{ {LED_RED, LED_OFF}, {1, 5}, DOUBLE_TAP_TICK_LEN * 3 +
-	  DOUBLE_TAP_TICK_LEN / 2},
-};
-
-/*
- * Brightness vs. color, in the order of off, red, green and blue. Values are
- * for % on PWM duty cycle time.
- */
-#define PWM_CHAN_PER_LED 3
-static const uint8_t color_brightness[LED_COLOR_COUNT][PWM_CHAN_PER_LED] = {
-	/* {Red, Green, Blue}, */
-	[LED_OFF]   = {0, 0, 0},
-	[LED_RED]   = {80,  0, 0},
-	[LED_GREEN] = {0, 80, 0},
-	[LED_BLUE] = {0, 0, 80},
-	[LED_WHITE]  = {100, 100, 100},
-	[LED_RED_HALF]  = {40, 0, 0},
-};
-
-/*
- * When a double tap event occurs, a LED pattern is displayed based on the
- * current battery charge level. The LED patterns used for double tap under low
- * battery conditions are same patterns displayed when the battery is not
- * charging. The table below shows what battery charge level displays which
- * pattern.
- */
-struct range_map {
-	uint8_t max;
-	uint8_t pattern;
-};
-
-#if (CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC >= 3)
-#error "LED: PULSE_RED battery level <= BLINK_RED level"
-#endif
-static const struct range_map pattern_tbl[] = {
-	{CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED},
-	{5, PULSE_RED},
-	{15, SOLID_RED},
-	{25, WHITE_RED},
-	{75, SOLID_WHITE},
-	{95, WHITE_GREEN},
-	{100, SOLID_GREEN},
-};
-
-enum led_state_change {
-	LED_STATE_INTENSITY_DOWN,
-	LED_STATE_INTENSITY_UP,
-	LED_STATE_DONE,
-};
-
-/**
- * Set LED color
- *
- * @param pwm		Pointer to 3 element RGB color level (0 -> 100)
- * @param side		Left LED, Right LED, or both LEDs
- */
-static void set_color(const uint8_t *pwm, enum led_side side)
-{
-	int i;
-	static uint8_t saved_duty[LED_BOTH][PWM_CHAN_PER_LED];
-
-	/* Set color for left LED */
-	if (side == LED_LEFT || side == LED_BOTH) {
-		for (i = 0; i < PWM_CHAN_PER_LED; i++) {
-			if (saved_duty[LED_LEFT][i] != pwm[i]) {
-				pwm_set_duty(PWM_CH_LED_L_RED + i,
-					     100 - pwm[i]);
-				saved_duty[LED_LEFT][i] = pwm[i];
-			}
-		}
-	}
-
-	/* Set color for right LED */
-	if (side == LED_RIGHT || side == LED_BOTH) {
-		for (i = 0; i < PWM_CHAN_PER_LED; i++) {
-			if (saved_duty[LED_RIGHT][i] != pwm[i]) {
-				pwm_set_duty(PWM_CH_LED_R_RED + i,
-					     100 - pwm[i]);
-				saved_duty[LED_RIGHT][i] = pwm[i];
-			}
-		}
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		/* Set brightness for left LED */
-		pwm_set_duty(PWM_CH_LED_L_RED,
-			     100 - brightness[EC_LED_COLOR_RED]);
-		pwm_set_duty(PWM_CH_LED_L_BLUE,
-			     100 - brightness[EC_LED_COLOR_BLUE]);
-		pwm_set_duty(PWM_CH_LED_L_GREEN,
-			     100 - brightness[EC_LED_COLOR_GREEN]);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		/* Set brightness for right LED */
-		pwm_set_duty(PWM_CH_LED_R_RED,
-			     100 - brightness[EC_LED_COLOR_RED]);
-		pwm_set_duty(PWM_CH_LED_R_BLUE,
-			     100 - brightness[EC_LED_COLOR_BLUE]);
-		pwm_set_duty(PWM_CH_LED_R_GREEN,
-			     100 - brightness[EC_LED_COLOR_GREEN]);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_register_double_tap(void)
-{
-	double_tap = 1;
-}
-
-static void led_setup_color_change(int old_idx, int new_idx, enum led_side side)
-{
-	int i;
-	int increase = 0;
-	/*
-	 * Using the color indices, poplulate the current and target R, G, B
-	 * arrays. The arrays are indexed R = 0, G = 1, B = 2. If the target of
-	 * any of the 3 is greater than the current, then this color change is
-	 * an increase in intensity. Otherwise, it's a decrease.
-	 */
-	led[side].rgb_target = color_brightness[new_idx];
-	for (i = 0; i < PWM_CHAN_PER_LED; i++) {
-		led[side].rgb_current[i] = color_brightness[old_idx][i];
-		if (led[side].rgb_current[i] < led[side].rgb_target[i]) {
-			/* increase in color */
-			increase = 1;
-		}
-	}
-	/* Check to see if increasing or decreasing color */
-	if (increase) {
-		led[side].state = LED_STATE_INTENSITY_UP;
-		/* First entry of transition table == current level */
-		led[side].step = 1;
-	} else {
-		/* Last entry of transition table == current level */
-		led[side].step = ARRAY_SIZE(trans_steps) - 2;
-		led[side].state = LED_STATE_INTENSITY_DOWN;
-	}
-
-	/*
-	 * Populate transition table based on the number of R, G, B components
-	 * changing. If only 1 componenet is changing, then can just do linear
-	 * steps over the range. If more than 1 component is changing, then
-	 * this is a white <--> color transition and will use
-	 * the precomputed steps which are derived by converting to HSI space
-	 * and then linearly transitioning S and I to go from the starting color
-	 * to white and vice versa.
-	 */
-	if (old_idx == LED_WHITE || new_idx == LED_WHITE) {
-		for (i = 0; i < ARRAY_SIZE(trans_steps); i++)
-			led[side].trans[i] = trans_steps[i];
-	} else {
-		int delta_per_step;
-		int step_value;
-		int start_lvl;
-		int total_change;
-		/* Assume that the R component (index = 0) is changing */
-		int rgb_index = 0;
-
-		/*
-		 * Since the new or old color is not white, then this change
-		 * must involve only either red or green. There are no red <-->
-		 * green transitions. So only 1 color is being changed in this
-		 * case. Assume it's red (index = 0), but check if it's green
-		 * (index = 1).
-		 */
-
-		if (old_idx == LED_GREEN || new_idx == LED_GREEN)
-			rgb_index = 1;
-
-		/*
-		 * Determine the total change assuming current level is higher
-		 * than target level. The transitions steps are always ordered
-		 * lower to higher. The starting index is adjusted if intensity
-		 * is decreasing.
-		 */
-		start_lvl = led[side].rgb_target[rgb_index];
-
-		if (led[side].state == LED_STATE_INTENSITY_UP)
-			/*
-			 * Increasing in intensity, current level or R/G is
-			 * the starting level.
-			 */
-			start_lvl = led[side].rgb_current[rgb_index];
-
-		/*
-		 * Compute change per step using fractional bits. The step
-		 * change accumulates fractional bits and is truncated after
-		 * rounding before being added to the starting value.
-		 */
-		total_change = ABS(led[side].rgb_current[rgb_index] -
-				   led[side].rgb_target[rgb_index]);
-		delta_per_step = (total_change << LED_FRAC_BITS)
-			/ (ARRAY_SIZE(trans_steps) - 1);
-		step_value = 0;
-		for (i = 0; i < ARRAY_SIZE(trans_steps); i++) {
-			led[side].trans[i] = start_lvl +
-				((step_value +
-				  (1 << (LED_FRAC_BITS - 1)))
-				 >> LED_FRAC_BITS);
-			step_value += delta_per_step;
-		}
-	}
-
-}
-
-static void led_adjust_color_step(int side)
-{
-	int i;
-	int change = 0;
-	uint8_t lvl = led[side].trans[led[side].step];
-	uint8_t *rgb_c = led[side].rgb_current;
-	const uint8_t *rgb_t = led[side].rgb_target;
-
-	if (led[side].state == LED_STATE_INTENSITY_DOWN) {
-		/*
-		 * Colors are going from higher to lower level. If the current
-		 * level of R, G, or B is higher than both the next step in the
-		 * transition table and and the target level, then move to
-		 * the larger of the two. The MAX is used to make sure that it
-		 * doens't drop below the target level.
-		 */
-		for (i = 0; i < PWM_CHAN_PER_LED; i++) {
-			if ((rgb_c[i] > rgb_t[i]) && (rgb_c[i] >= lvl)) {
-				rgb_c[i] = MAX(lvl, rgb_t[i]);
-				change = 1;
-			}
-		}
-		/*
-		 * If nothing changed this iteration, or if lowest table entry
-		 * has been used, then the change is complete.
-		 */
-		if (!change || --led[side].step < 0)
-			led[side].state = LED_STATE_DONE;
-
-	} else if (led[side].state == LED_STATE_INTENSITY_UP) {
-		/*
-		 * Colors are going from lower to higher level. If the current
-		 * level of R, G, B is lower than both the target level and the
-		 * transition table entry for a given color, then move up to
-		 * the MIN of next transition step and target level.
-		 */
-		for (i = 0; i < PWM_CHAN_PER_LED; i++) {
-			if ((rgb_c[i] < rgb_t[i]) && (rgb_c[i] <= lvl)) {
-				rgb_c[i] = MIN(lvl, rgb_t[i]);
-				change = 1;
-			}
-		}
-		/*
-		 * If nothing changed this iteration, or if highest table entry
-		 * has been used, then the change is complete.
-		 */
-		if (!change || ++led[side].step >= ARRAY_SIZE(trans_steps))
-			led[side].state = LED_STATE_DONE;
-	}
-	/* Apply current R, G, B levels */
-	set_color(rgb_c, side);
-}
-
-static void led_change_color(void)
-{
-	int i;
-
-	/* Will loop here until the color change is complete. */
-	while (led[LED_LEFT].state != LED_STATE_DONE ||
-	       led[LED_RIGHT].state != LED_STATE_DONE) {
-
-		for (i = 0; i < LED_BOTH; i++) {
-			if (led[i].state != LED_STATE_DONE)
-				/* Move one step in the transition table */
-				led_adjust_color_step(i);
-
-		}
-		msleep(LED_STEP_MSEC);
-	}
-}
-
-static void led_manage_patterns(enum led_pattern *pattern_desired, int tap)
-{
-	int color;
-	int phase;
-	int i;
-	int color_change = 0;
-
-	for (i = 0; i < LED_BOTH; i++) {
-		/* For each led check if the pattern needs to change */
-		if (pattern_desired[i] != led[i].pattern_sel) {
-			/*
-			 * Pattern needs to change, but if double tap sequence
-			 * is active, then need to wait until that
-			 * completes. Unless the pattern change is due to
-			 * external charger state change, make that happen
-			 * immediately.
-			 */
-			if (i == led_charge_side || !led[i].tap_tick_count) {
-				led[i].ticks = 0;
-				led[i].tap_tick_count = tap ?
-					pattern[pattern_desired[i]].tap_len : 0;
-				led[i].pattern_sel = pattern_desired[i];
-			}
-		}
-		/* Determine pattern phase and color for current phase */
-		phase = led[i].ticks < LED_TICKS_PER_BEAT *
-			pattern[led[i].pattern_sel].len[0] ? 0 : 1;
-		color = pattern[led[i].pattern_sel].color[phase];
-		/* If color is changing, then setup the transition. */
-		if (led[i].color != color) {
-			led_setup_color_change(led[i].color, color, i);
-			led[i].color = color;
-			color_change = 1;
-		}
-	}
-
-	if (color_change)
-		/* Change color is done for both LEDs simultaneously */
-		led_change_color();
-
-	for (i = 0; i < LED_BOTH; i++) {
-		/* Set color for the current phase */
-		set_color(color_brightness[led[i].color], i);
-
-		/*
-		 * Update led_ticks. If the len field is 0, then the pattern
-		 * being used is just one color so no need to increase the tick
-		 * count.
-		 */
-		if (pattern[led[i].pattern_sel].len[0])
-			if (++led[i].ticks == LED_TICKS_PER_BEAT *
-			    (pattern[led[i].pattern_sel].len[0] +
-			     pattern[led[i].pattern_sel].len[1]))
-				led[i].ticks = 0;
-
-		/* If double tap display is active, decrement its counter */
-		if (led[i].tap_tick_count)
-			led[i].tap_tick_count--;
-	}
-}
-
-static enum led_pattern led_get_double_tap_pattern(int percent_chg)
-{
-	int i;
-	enum led_pattern pattern = OFF;
-
-	for (i = 0; i < ARRAY_SIZE(pattern_tbl); i++) {
-		if (percent_chg <= pattern_tbl[i].max) {
-			pattern = pattern_tbl[i].pattern;
-			break;
-		}
-	}
-
-	return pattern;
-}
-
-static void led_select_pattern(enum led_pattern *pattern_desired, int tap)
-{
-	enum charge_state chg_state = charge_get_state();
-	int side;
-	int percent_chg;
-	enum led_pattern new_pattern;
-
-	/* Get active charge port which maps directly to left/right LED */
-	side = charge_manager_get_active_charge_port();
-	/*
-	 * Maintain a copy of the side associated with charging. If there is no
-	 * active charging port, then charge_side = -1. This value is used to
-	 * manage the double_tap tick counts on a per LED basis.
-	 */
-	led_charge_side = side;
-	/* Ensure that side can be safely used as an index */
-	if (side < 0 || side >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		side = LED_BOTH;
-
-	/* Get percent charge */
-	percent_chg = charge_get_percent();
-
-	if (side == LED_BOTH) {
-		/*
-		 * External charger is not connected. Find the pattern that
-		 * would be used for double tap event.
-		 */
-		new_pattern = led_get_double_tap_pattern(percent_chg);
-
-		/*
-		 * The patterns used for double tap and for not charging
-		 * state are the same for low battery cases. But, if
-		 * battery charge is high enough to be above SOLID_RED,
-		 * then only display LED pattern if double tap has
-		 * occurred.
-		 */
-		if (!tap && new_pattern <= WHITE_RED)
-			new_pattern = OFF;
-		/*
-		 * When external charger is not connected, always apply pattern
-		 * to both LEDs.
-		 */
-		pattern_desired[LED_LEFT] = new_pattern;
-		pattern_desired[LED_RIGHT] = new_pattern;
-
-	} else {
-		/*
-		 * External charger is connected. First determine pattern for
-		 * charging side LED.
-		 */
-		if (chg_state == PWR_STATE_CHARGE_NEAR_FULL ||
-		    ((chg_state == PWR_STATE_DISCHARGE_FULL)
-		     && extpower_is_present())) {
-			new_pattern = SOLID_GREEN;
-		} else if (chg_state == PWR_STATE_CHARGE) {
-			new_pattern = SOLID_WHITE;
-		} else {
-			new_pattern = OFF;
-		}
-		pattern_desired[side] = new_pattern;
-
-		/* Check for double tap for side not associated with charger */
-		new_pattern = led_get_double_tap_pattern(percent_chg);
-		if (!tap && new_pattern != BLINK_RED)
-			new_pattern = OFF;
-		/* Apply this pattern to the non-charging side LED */
-		pattern_desired[side ^ 1] = new_pattern;
-	}
-}
-
-static void led_init(void)
-{
-	int i;
-
-	/*
-	 * Enable PWMs and set to 0% duty cycle.  If they're disabled,
-	 * seems to ground the pins instead of letting them float.
-	 */
-	/* Initialize PWM channels for left LED */
-	pwm_enable(PWM_CH_LED_L_RED, 1);
-	pwm_enable(PWM_CH_LED_L_GREEN, 1);
-	pwm_enable(PWM_CH_LED_L_BLUE, 1);
-
-	/* Initialize PWM channels for right LED */
-	pwm_enable(PWM_CH_LED_R_RED, 1);
-	pwm_enable(PWM_CH_LED_R_GREEN, 1);
-	pwm_enable(PWM_CH_LED_R_BLUE, 1);
-
-	set_color(color_brightness[LED_OFF], LED_BOTH);
-
-	/*
-	 * Initialize LED descriptors. The members that are used for changing
-	 * colors don't neet to be initialized as they are always computed
-	 * when a color change is required.
-	 */
-	for (i = 0; i < LED_BOTH; i++) {
-		led[i].pattern_sel = OFF;
-		led[i].color = LED_OFF;
-		led[i].ticks = 0;
-		led[i].tap_tick_count = 0;
-		led[i].state = LED_STATE_DONE;
-	}
-
-}
-
-void led_task(void *u)
-{
-	uint32_t start_time;
-	uint32_t task_duration;
-
-	led_init();
-
-	usleep(SECOND);
-
-	while (1) {
-		enum led_pattern pattern_desired[LED_BOTH];
-		int tap = 0;
-
-		start_time = get_time().le.lo;
-
-		if (double_tap) {
-			/* Clear double tap indication */
-			if (!chipset_in_state(CHIPSET_STATE_ON))
-				/* If not in S0, then set tap on */
-				tap = 1;
-			double_tap = 0;
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED) &&
-		    led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED) &&
-		    led_debug != 1) {
-			/* Determine desired LED patterns for both LEDS */
-			led_select_pattern(pattern_desired, tap);
-			/* Update LED patterns/colors (if necessary) */
-			led_manage_patterns(pattern_desired, tap);
-		}
-		/* Compute time for this iteration */
-		task_duration = get_time().le.lo - start_time;
-		/*
-		 * Compute wait time required to for next desired LED tick. If
-		 * the duration exceeds the tick time, then don't sleep.
-		 */
-		if (task_duration < LED_TICK_TIME)
-			usleep(LED_TICK_TIME - task_duration);
-	}
-}
-
-/******************************************************************/
-/* Console commands */
-static int command_led(int argc, char **argv)
-{
-	int side = LED_BOTH;
-	char *e;
-	enum led_color color;
-
-	if (argc > 1) {
-		if (argc > 2) {
-			side = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM2;
-			if (side > 1)
-				return EC_ERROR_PARAM2;
-		}
-
-		if (!strcasecmp(argv[1], "debug")) {
-			led_debug ^= 1;
-			CPRINTF("led_debug = %d\n", led_debug);
-			return EC_SUCCESS;
-		}
-
-		if (!strcasecmp(argv[1], "off"))
-			color = LED_OFF;
-		else if (!strcasecmp(argv[1], "red"))
-			color = LED_RED;
-		else if (!strcasecmp(argv[1], "green"))
-			color = LED_GREEN;
-		else if (!strcasecmp(argv[1], "blue"))
-			color = LED_BLUE;
-		else if (!strcasecmp(argv[1], "white"))
-			color = LED_WHITE;
-		else
-			return EC_ERROR_PARAM1;
-
-		set_color(color_brightness[color], side);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|blue|white|amber|off <0|1>]",
-			"Change LED color");
diff --git a/board/eve/usb_pd_policy.c b/board/eve/usb_pd_policy.c
deleted file mode 100644
index d6dd5ad1be..0000000000
--- a/board/eve/usb_pd_policy.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
-	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
-	int flags;
-
-	if (system_get_board_version() >= BOARD_VERSION_P1B) {
-		/*
-		 * For P1B and beyond, 1.5 vs 3.0 A limit is controlled by a
-		 * dedicated gpio where high = 3.0A and low = 1.5A. VBUS on/off
-		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
-		 * can remain outputs.
-		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-			       1 : 0);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-	} else {
-		/*
-		 * For P1 and earlier board revs, a single gpio signal is
-		 * used to both enable VBUS and set the current limit.
-		 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-		 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-		 * setting a minimum OCP current of 3186 mA.
-		 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put
-		 * a 33k resistor on ILIM, setting a minimum OCP current of
-		 * 1505 mA.
-		 */
-		flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-		gpio_set_flags(gpio_5v_en, flags);
-	}
-}
-
-void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Ensure we're not charging from this port */
-	bd9995x_select_input_port(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-}
diff --git a/board/eve/vif_override.xml b/board/eve/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/eve/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/ezkinil/analyzestack.yaml b/board/ezkinil/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/ezkinil/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/ezkinil/battery.c b/board/ezkinil/battery.c
deleted file mode 100644
index 8c5ec9e1d7..0000000000
--- a/board/ezkinil/battery.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* AP18C7M */
-	[BATTERY_AP18C7M] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP KT00407008",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 17600,
-			.voltage_normal       = 15400,
-			.voltage_min          = 12000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/ezkinil/board.c b/board/ezkinil/board.c
deleted file mode 100644
index 14f8e6e915..0000000000
--- a/board/ezkinil/board.c
+++ /dev/null
@@ -1,827 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charge_state_v2.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-
-#include "gpio_list.h"
-
-static int board_ver;
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t base_standard_ref_1 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_standard_ref_1,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_1,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS5,
-};
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-	return EC_SUCCESS;
-}
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-/*****************************************************************************
- * Base Gyro Sensor dynamic configuration
- */
-
-static int base_gyro_config;
-
-static void setup_base_gyro_config(void)
-{
-	base_gyro_config = ec_config_has_base_gyro_sensor();
-
-	if (base_gyro_config == BASE_GYRO_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE GYRO is ICM426XX");
-	} else if (base_gyro_config == BASE_GYRO_BMI160)
-		ccprints("BASE GYRO is BMI160");
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration
- */
-
-int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-
-static void setup_mux(void)
-{
-	enum ec_ssfc_c1_mux mux = get_cbi_ssfc_c1_mux();
-
-	if (mux == SSFC_C1_MUX_NONE && ec_config_has_usbc1_retimer_tusb544())
-		mux = SSFC_C1_MUX_TUSB544;
-
-	if (mux == SSFC_C1_MUX_PS8818) {
-		ccprints("C1 PS8818 detected");
-		/*
-		 * Main MUX is FP5, secondary MUX is PS8818
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-	} else if (mux == SSFC_C1_MUX_TUSB544) {
-		ccprints("C1 TUSB544 detected");
-		/*
-		 * Main MUX is FP5, secondary MUX is TUSB544
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
-	} else if (ec_config_has_usbc1_retimer_ps8743()) {
-		ccprints("C1 PS8743 detected");
-		/*
-		 * Main MUX is PS8743, secondary MUX is modified FP5
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
-		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-		/* Don't have the AMD FP5 flip */
-		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
-	}
-}
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		/* Filled in dynamically at startup */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Enable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
-	} else {
-		/* Disable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
-	}
-	return EC_SUCCESS;
-}
-
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		/* Enable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
-	else
-		/* Disable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usbc1_tusb544 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS1,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_mux_set,
-};
-const struct usb_mux usbc1_ps8743 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-	.driver = &ps8743_usb_mux_driver,
-	.board_set = &board_ps8743_mux_set,
-};
-
-/*****************************************************************************
- * PPC
- */
-
-static int ppc_id;
-
-static void setup_c1_ppc_config(void)
-{
-	/*
-	 * Read USB_C1_POWER_SWITCH_ID to choose DB ppc chip
-	 * 0: NX20P3483UK
-	 * 1: AOZ1380DI
-	 */
-
-	ioex_get_level(IOEX_USB_C1_POWER_SWITCH_ID, &ppc_id);
-
-	ccprints("C1: PPC is %s", ppc_id ? "AOZ1380DI" : "NX20P3483UK");
-
-	if (ppc_id) {
-		ppc_chips[USBC_PORT_C1].drv = &aoz1380_drv;
-		ioex_set_flags(IOEX_USB_C1_PPC_ILIM_3A_EN, GPIO_OUT_LOW);
-	}
-}
-
-__override void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		if (ppc_id)
-			aoz1380_interrupt(USBC_PORT_C1);
-		else
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv;
-
-	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN
-				: IOEX_USB_C0_PPC_ILIM_3A_EN,
-				(rp == TYPEC_RP_3A0) ? 1 : 0);
-
-	return rv;
-}
-
-/*****************************************************************************
- * Use FW_CONFIG to set correct configuration.
- */
-
-static void setup_v0_charger(void)
-{
-	int rv;
-
-	rv = cbi_get_board_version(&board_ver);
-	if (rv) {
-		ccprints("Fail to get board_ver");
-		/* Default for v3 */
-		board_ver = 3;
-	}
-
-	if (board_ver == 1)
-		chg_chips[0].i2c_port = I2C_PORT_CHARGER_V0;
-}
-/*
- * Use HOOK_PRIO_INIT_I2C so we re-map before charger_chips_init()
- * talks to the charger.
- */
-DECLARE_HOOK(HOOK_INIT, setup_v0_charger, HOOK_PRIO_INIT_I2C);
-
-static void setup_fw_config(void)
-{
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-
-	setup_mux();
-
-	if (board_ver >= 3)
-		setup_c1_ppc_config();
-
-	if (ec_config_has_hdmi_conn_hpd()) {
-		if (board_ver < 3)
-			ioex_enable_interrupt(IOEX_HDMI_CONN_HPD_3V3_DB);
-		else
-			gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
-	}
-
-	setup_base_gyro_config();
-}
-/* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-static int check_hdmi_hpd_status(void)
-{
-	int hpd = 0;
-
-	if (board_ver < 3)
-		ioex_get_level(IOEX_HDMI_CONN_HPD_3V3_DB, &hpd);
-	else
-		hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
-
-	return hpd;
-}
-
-static void hdmi_hpd_handler(void)
-{
-	/* Pass HPD through from DB OPT1 HDMI connector to AP's DP1. */
-	int hpd = check_hdmi_hpd_status();
-
-	gpio_set_level(GPIO_DP1_HPD, hpd);
-	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-void hdmi_hpd_interrupt_v2(enum ioex_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-/*****************************************************************************
- * Board suspend / resume
- */
-
-static void board_chipset_resume(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 1);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
-		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  check_hdmi_hpd_status());
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
-	}
-
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * Fan
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3200,
-	.rpm_start = 3200,
-	.rpm_max = 6000,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-	case TEMP_SENSOR_SOC:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_SOC;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_SOC,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(95),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
-
-const static struct ec_thermal_config thermal_soc = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(32),
-	.temp_fan_max = C_TO_K(75),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on =  9, .off =  1, .rpm = 3200},
-	{.on = 21, .off =  7, .rpm = 3500},
-	{.on = 28, .off = 16, .rpm = 3900},
-	{.on = 37, .off = 26, .rpm = 4200},
-	{.on = 47, .off = 35, .rpm = 4600},
-	{.on = 56, .off = 44, .rpm = 5100},
-	{.on = 72, .off = 60, .rpm = 5500},
-};
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-
-static const struct fan_step *fan_table = fan_table0;
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_CHARGER] = thermal_thermistor;
-	thermal_params[TEMP_SENSOR_SOC] = thermal_soc;
-}
-DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_pct;
-	int i;
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan))) {
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-		board_print_temps();
-	}
-
-	return fan_table[current_level].rpm;
-}
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 95% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 95 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT),
-				charge_mv);
-}
diff --git a/board/ezkinil/board.h b/board/ezkinil/board.h
deleted file mode 100644
index e3ec10d456..0000000000
--- a/board/ezkinil/board.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_TREMBYLE
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_FAN_RPM_CUSTOM
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Type C mux/retimer */
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USBC_RETIMER_TUSB544
-#define TUSB544_I2C_ADDR_FLAGS1 0x0F
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_DP1_HPD			GPIO_EC_DP1_HPD
-#define IOEX_HDMI_CONN_HPD_3V3_DB	IOEX_USB_C1_PPC_ILIM_3A_EN
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_AP18C7M,
-	BATTERY_TYPE_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * EZKINIL_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	EZKINIL_MB_USBAC = 0,
-};
-
-/**
- * EZKINIL_DB_T_OPT1_USBC_HDMI
- *	USB-A1  none
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: TUSB544
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- *
- * EZKINIL_DB_T_OPT2_USBAC
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8743
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- */
-enum ec_cfg_usb_db_type {
-	EZKINIL_DB_T_OPT1_USBC_HDMI = 0,
-	EZKINIL_DB_T_OPT2_USBAC = 1,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBA1_RETIMER_TUSB522 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
-
-static inline bool ec_config_has_usba1_retimer_tusb522(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBA1_RETIMER_TUSB522);
-}
-
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
-
-static inline bool ec_config_has_usbc1_retimer_ps8743(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
-}
-
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
-
-static inline bool ec_config_has_usbc1_retimer_tusb544(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-#define HAS_HDMI_CONN_HPD \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
-
-static inline bool ec_config_has_hdmi_conn_hpd(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
-}
-
-/* TODO: Fill in with GPIO values */
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8743()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
-
-extern const struct usb_mux usbc1_tusb544;
-extern const struct usb_mux usbc1_ps8818;
-extern const struct usb_mux usbc1_ps8743;
-extern struct usb_mux usbc1_amd_fp5_usb_mux;
-
-void motion_interrupt(enum gpio_signal signal);
-void hdmi_hpd_interrupt(enum gpio_signal signal);
-void hdmi_hpd_interrupt_v2(enum ioex_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ezkinil/build.mk b/board/ezkinil/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/ezkinil/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/ezkinil/ec.tasklist b/board/ezkinil/ec.tasklist
deleted file mode 100644
index d9c1606eb2..0000000000
--- a/board/ezkinil/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/ezkinil/gpio.inc b/board/ezkinil/gpio.inc
deleted file mode 100644
index 8e75ec9975..0000000000
--- a/board/ezkinil/gpio.inc
+++ /dev/null
@@ -1,137 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
-GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, 	sbu_fault_interrupt)
-IOEX_INT(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 0), GPIO_INT_BOTH,	hdmi_hpd_interrupt_v2)	/* v3:C1 3A Current Limit Enable; v2:HDMI_CONN_HPD_3V3_DB */
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_C1_POWER_SWITCH_ID,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_INPUT)		/* C1 PPC ID, 0: NX20P34, 1: AOZ1380 */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(HDMI_POWER_EN_DB,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)	/* HDMI retimer power enable */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_LOW)	/* HDMI Retimer Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,		EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/ezkinil/led.c b/board/ezkinil/led.c
deleted file mode 100644
index 7c425fa138..0000000000
--- a/board/ezkinil/led.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{LED_OFF,	     1 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/ezkinil/vif_override.xml b/board/ezkinil/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/ezkinil/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/felwinter/battery.c b/board/felwinter/battery.c
deleted file mode 100644
index e0c1213130..0000000000
--- a/board/felwinter/battery.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Brya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C536] = {
-		/* BQ40Z50 Fuel Gauge */
-		.fuel_gauge = {
-			.manuf_name = "AS3GXAE3jB",
-			.device_name = "C536-49",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0054,
-				.reg_mask = 0x0006,		/* XDSG */
-				.disconnect_val = 0x0006,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11800, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C536;
diff --git a/board/felwinter/board.c b/board/felwinter/board.c
deleted file mode 100644
index c4dfe8e530..0000000000
--- a/board/felwinter/board.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-__override void board_cbi_init(void)
-{
-	config_usb_db_type();
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO(b/181508008): tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-	batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
-
-static void board_init(void)
-{
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		db_update_usb4_config_from_config();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/felwinter/board.h b/board/felwinter/board.h
deleted file mode 100644
index d9fb63c789..0000000000
--- a/board/felwinter/board.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/*
- * Early brya boards are not set up for vivaldi
- */
-#undef CONFIG_KEYBOARD_VIVALDI
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#define GPIO_PWR_LED_WHITE_L	GPIO_LED_1_L
-#define GPIO_BAT_LED_AMBER_L	GPIO_LED_3_L
-#define GPIO_BAT_LED_WHITE_L	GPIO_LED_4_L
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-/* Lid accel */
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
-#define CONFIG_USB_PD_TCPM_PS8815
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/*
- *
- */
-#define USBC_PORT_BB_RETIMER_I2C_ADDR	0x57
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/*
- * TODO(b/181271666): no fan control loop until sensors are tuned
- */
-/* #define CONFIG_FANS			FAN_CH_COUNT */
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_FAN,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_FAN,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C2_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_C536,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,	/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/felwinter/build.mk b/board/felwinter/build.mk
deleted file mode 100644
index df453187bf..0000000000
--- a/board/felwinter/build.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brya board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/felwinter/charger.c b/board/felwinter/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/felwinter/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/felwinter/ec.tasklist b/board/felwinter/ec.tasklist
deleted file mode 100644
index 290c17c748..0000000000
--- a/board/felwinter/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/felwinter/fans.c b/board/felwinter/fans.c
deleted file mode 100644
index d966056331..0000000000
--- a/board/felwinter/fans.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/180681346): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/felwinter/fw_config.c b/board/felwinter/fw_config.c
deleted file mode 100644
index 7afdae3837..0000000000
--- a/board/felwinter/fw_config.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union brya_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union brya_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Brya FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-}
-
-union brya_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
diff --git a/board/felwinter/fw_config.h b/board/felwinter/fw_config.h
deleted file mode 100644
index f9de98a93f..0000000000
--- a/board/felwinter/fw_config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for felwinter board.
- *
- * Source of truth is the project/brya/felwinter/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB3_PS8815 = 1,
-	DB_USB4_NCT3807 = 2
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union brya_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union brya_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/felwinter/gpio.inc b/board/felwinter/gpio.inc
deleted file mode 100644
index ba7116847a..0000000000
--- a/board/felwinter/gpio.inc
+++ /dev/null
@@ -1,151 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C2_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RST_ODL,                 PIN(9, 6), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* LED */
-GPIO(LED_4_L,                        PIN(6, 0), GPIO_OUT_HIGH) /* battery led white */
-GPIO(LED_3_L,                        PIN(C, 2), GPIO_OUT_HIGH) /* battery led amber */
-GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH) /* power led white */
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-UNUSED(PIN(C, 3))       /* GPIOC3 */
-UNUSED(PIN(E, 1))       /* GPIOE1 */
-UNUSED(PIN(D, 4))       /* GPIOD4 */
-UNUSED(PIN(C, 6))       /* GPIOC6 */
-UNUSED(PIN(6, 2))       /* GPIO62 */
-UNUSED(PIN(B, 1))       /* GPIOB1 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-/* GPIO02_P2 to PU */
-/* GPIO03_P2 to PU */
-
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-
-IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
-/* GPIO07_P2 to PU */
diff --git a/board/felwinter/i2c.c b/board/felwinter/i2c.c
deleted file mode 100644
index b54cc98de8..0000000000
--- a/board/felwinter/i2c.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc2",
-		.port = I2C_PORT_USB_C2_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc2",
-		.port = I2C_PORT_USB_C2_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer2",
-		.port = I2C_PORT_USB_C2_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/felwinter/keyboard.c b/board/felwinter/keyboard.c
deleted file mode 100644
index a9f033130d..0000000000
--- a/board/felwinter/keyboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/felwinter/led.c b/board/felwinter/led.c
deleted file mode 100644
index 3b7e649470..0000000000
--- a/board/felwinter/led.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for felwinter
- */
-
-#include "chipset.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "system.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 94;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/felwinter/pwm.c b/board/felwinter/pwm.c
deleted file mode 100644
index 985305449b..0000000000
--- a/board/felwinter/pwm.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/felwinter/sensors.c b/board/felwinter/sensors.c
deleted file mode 100644
index 87025c017e..0000000000
--- a/board/felwinter/sensors.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc_chip.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "hooks.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_FAN] = {
-		.name = "TEMP_FAN",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-static struct stprivate_data g_lis2dw12_data;
-static struct lsm6dso_data lsm6dso_data;
-
-/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DW12,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dw12_data,
-		.int_signal = GPIO_EC_ACCEL_INT_R_L,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DW12_ADDR0,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSO_ST_DATA(lsm6dso_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void baseboard_sensors_init(void)
-{
-	/* Enable gpio interrupt for lid accel sensor */
-	gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_fan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_FAN]	= thermal_fan,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/felwinter/usbc_config.c b/board/felwinter/usbc_config.c
deleted file mode 100644
index a301826c6a..0000000000
--- a/board/felwinter/usbc_config.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-struct tcpc_config_t tcpc_config_c1 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1_TCPC,
-		.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-	},
-	.drv = &nct38xx_tcpm_drv,
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-		TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-};
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		/* Compatible with Silicon Mitus SM536A0 */
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-struct ppc_config_t ppc_chips_c1 = {
-	.i2c_port = I2C_PORT_USB_C1_PPC,
-	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-	.drv = &syv682x_drv,
-};
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set
- * to the virtual_usb_mux_driver so the AP gets notified of mux changes
- * and updates the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct usb_mux usb_muxes_c1 = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-};
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C2 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C1_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-void config_usb_db_type(void)
-{
-	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
-
-	/*
-	 * TODO(b/180434685): implement multiple DB types
-	 */
-
-	CPRINTS("Configured USB DB type number is %d", db_type);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C1)
-		rst_signal = GPIO_USB_C1_RT_RST_R_ODL;
-	else if (me->usb_port == USBC_PORT_C2)
-		rst_signal = IOEX_USB_C2_RT_RST_ODL;
-	else
-		return EC_ERROR_INVAL;
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b/179648104): figure out correct timing
-	 */
-
-	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
-
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-static void enable_ioex(int ioex)
-{
-	ioex_config[ioex].flags &= ~IOEX_FLAGS_DISABLED;
-	ioex_init(ioex);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		/*
-		 * These IO expander pins are implemented using the
-		 * C0/C2 TCPC, so they must be set up after the TCPC has
-		 * been taken out of reset.
-		 */
-		if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-			enable_ioex(IOEX_C1_NCT38XX);
-		enable_ioex(IOEX_C2_NCT38XX);
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C2)
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C2_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C2);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C1_PPC_INT_ODL:
-		switch (ec_cfg_usb_db_type()) {
-		case DB_USB3_PS8815:
-			nx20p348x_interrupt(USBC_PORT_C1);
-			break;
-		case DB_USB4_NCT3807:
-			syv682x_interrupt(USBC_PORT_C1);
-			break;
-		}
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C2;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	if ((port == USBC_PORT_C2) ||
-		((port == USBC_PORT_C1) &&
-		(ec_cfg_usb_db_type() == DB_USB4_NCT3807)))
-		return true;
-
-	return false;
-}
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	if (!board_is_tbt_usb4_port(port))
-		return TBT_SS_RES_0;
-
-	return TBT_SS_TBT_GEN3;
-}
-
-void db_update_usb4_config_from_config(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_c1;
-	ppc_chips[USBC_PORT_C1] = ppc_chips_c1;
-	usb_muxes[USBC_PORT_C1] = usb_muxes_c1;
-}
diff --git a/board/felwinter/usbc_config.h b/board/felwinter/usbc_config.h
deleted file mode 100644
index cea53dcaa2..0000000000
--- a/board/felwinter/usbc_config.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-enum usbc_port {
-	USBC_PORT_C2 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-void db_update_usb4_config_from_config(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/felwinter/vif_override.xml b/board/felwinter/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/felwinter/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/fennel/battery.c b/board/fennel/battery.c
deleted file mode 100644
index cfd17a136f..0000000000
--- a/board/fennel/battery.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,   /* mV */
-			.voltage_normal		= 11400,   /* mV */
-			.voltage_min		= 9000,    /* mV */
-			.precharge_current	= 256,     /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -40,
-			.discharging_max_c	= 73,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/fennel/board.c b/board/fennel/board.c
deleted file mode 100644
index 0706813592..0000000000
--- a/board/fennel/board.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "keyboard_backlight.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	/* Pull SPI_NSS pin to low to prevent a leakage. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm42607_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-static enum base_accelgyro_type base_accelgyro_config;
-
-struct motion_sensor_t icm42607_base_accel = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = NULL,
-	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	 },
-};
-
-struct motion_sensor_t icm42607_base_gyro = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (base_accelgyro_config != BASE_GYRO_NONE)
-		return;
-	/* Check base accelgyro chip */
-	ret = icm_read8(&icm42607_base_accel,
-				ICM42607_REG_WHO_AM_I, &val);
-	if (ret)
-		ccprints("Get ICM fail.");
-	if (val == ICM42607_CHIP_ICM42607P) {
-		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
-		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
-	}
-	base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P)
-			? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	ccprints("BASE Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P)
-			? "ICM42607" : "BMI160");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-/*
- * board_spi_enable() will be called in the board_init() when sysjump to rw
- * the board_init() is DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT)
- * the board_detect_motionsensor() reads data via sensor SPI
- * so the priority of board_detect_motionsensor should be HOOK_PRIO_DEFAULT+1
- */
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_accelgyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm42607_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
-};
-
-void board_kblight_init(void)
-{
-	kblight_register(&kblight_it8801);
-}
-
-bool board_has_kb_backlight(void)
-{
-	/* Default enable keyboard backlight */
-	return true;
-}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Battery functions */
-#define SB_SMARTCHARGE				0x26
-/* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
-/* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_SMARTCHARGE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_SMARTCHARGE, val);
-}
-
-/* Called on AP S0iX -> S0 transition */
-static void board_chipset_resume(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 1);
-#endif
-
-	/* Normal charge mode */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void board_chipset_suspend(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 0);
-#endif
-
-	/* Quick charge mode */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
-
-int board_get_battery_i2c(void)
-{
-	return board_get_version() >= 1 ? 2 : 1;
-}
-
-#ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
-{
-	switch (type) {
-	case EC_PWM_TYPE_GENERIC:
-		*channel = index;
-		break;
-	default:
-		return -1;
-	}
-
-	return *channel >= 1;
-}
-
-static enum ec_status
-host_command_pwm_set_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_duty *p = args->params;
-	enum pwm_channel channel;
-	uint16_t duty;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	duty = (uint32_t) p->duty * 255 / 65535;
-	it8801_pwm_set_raw_duty(channel, duty);
-	it8801_pwm_enable(channel, p->duty > 0);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_pwm_get_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_get_duty *p = args->params;
-	struct ec_response_pwm_get_duty *r = args->response;
-
-	enum pwm_channel channel;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
-		     EC_VER_MASK(0));
-#endif
diff --git a/board/fennel/board.h b/board/fennel/board.h
deleted file mode 100644
index 697480770c..0000000000
--- a/board/fennel/board.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Fennel */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-#undef CONFIG_CMD_MFALLOW
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-#undef CONFIG_SYSTEM_UNLOCKED
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM42607	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#ifdef SECTION_IS_RW
-#define CONFIG_IO_EXPANDER_IT8801_PWM
-#define CONFIG_KEYBOARD_BACKLIGHT
-#endif
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	IT8801_PWM_CH_KBLIGHT = 0,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-void motion_interrupt(enum gpio_signal signal);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/fennel/build.mk b/board/fennel/build.mk
deleted file mode 100644
index a6e1c010d7..0000000000
--- a/board/fennel/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/fennel/ec.tasklist b/board/fennel/ec.tasklist
deleted file mode 100644
index c1330b86f8..0000000000
--- a/board/fennel/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/fennel/gpio.inc b/board/fennel/gpio.inc
deleted file mode 100644
index 29518fbc4e..0000000000
--- a/board/fennel/gpio.inc
+++ /dev/null
@@ -1,121 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         motion_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/fennel/led.c b/board/fennel/led.c
deleted file mode 100644
index 7d95c4807e..0000000000
--- a/board/fennel/led.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Fennel
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/fennel/vif_override.xml b/board/fennel/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/fennel/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/fizz/board.c b/board/fizz/board.c
deleted file mode 100644
index 5b830b9150..0000000000
--- a/board/fizz/board.c
+++ /dev/null
@@ -1,834 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fizz board-specific configuration */
-
-#include "adc.h"
-#include "als.h"
-#include "battery.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/pmic_tps650x30.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "espi.h"
-#include "extpower.h"
-#include "espi.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static uint16_t board_version;
-static uint8_t oem;
-static uint8_t sku;
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
-/*
- * ADP_IN pin state. It's initialized to 1 (=unplugged) because the IRQ won't
- * be triggered if BJ is the power source.
- */
-static int adp_in_state = 1;
-
-static void adp_in_deferred(void);
-DECLARE_DEFERRED(adp_in_deferred);
-static void adp_in_deferred(void)
-{
-	struct charge_port_info pi = { 0 };
-	int level = gpio_get_level(GPIO_ADP_IN_L);
-
-	/* Debounce */
-	if (level == adp_in_state)
-		return;
-	if (!level) {
-		/* BJ is inserted but the voltage isn't effective because PU3
-		 * is still disabled. */
-		pi.voltage = 19500;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			/*
-			 * It doesn't matter what we set here because we'll
-			 * brown out anyway when charge_manager switches
-			 * input.
-			 */
-			pi.current = 3330;
-	}
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &pi);
-	/*
-	 * Explicitly notifies the host that BJ is plugged or unplugged
-	 * (when running on a type-c adapter).
-	 */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-	adp_in_state = level;
-}
-
-/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
-void adp_in(enum gpio_signal signal)
-{
-	if (adp_in_state == gpio_get_level(GPIO_ADP_IN_L))
-		return;
-	hook_call_deferred(&adp_in_deferred_data, ADP_DEBOUNCE_MS * MSEC);
-}
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C0);
-}
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_FAN_PWR_EN,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 5600,
-};
-
-const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 2800,
-	.rpm_start = 2800,
-	.rpm_max = 5600,
-};
-
-struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"eeprom", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger", NPCX_I2C_PORT1, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"pmic", NPCX_I2C_PORT2, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", NPCX_I2C_PORT3, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = I2C_ADDR_TCPC0_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* 0x98 sets lower EQ of DP port (4.5db) */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-	GPIO_USB2_ENABLE,
-	GPIO_USB3_ENABLE,
-	GPIO_USB4_ENABLE,
-	GPIO_USB5_ENABLE,
-};
-
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
-	msleep(1);
-	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int reg;
-
-	/* This needs to be executed only once per boot. It could be run by RO
-	 * if we boot in recovery mode. It could be run by RW if we boot in
-	 * normal or dev mode. Note EFS makes RO jump to RW before HOOK_INIT. */
-	board_reset_pd_mcu();
-
-	/*
-	 * Wake up PS8751. If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 * Note PS8751 A3 will wake on any I2C access.
-	 */
-	i2c_read8(I2C_PORT_TCPC0, I2C_ADDR_TCPC0_FLAGS, 0xA0, &reg);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	return status;
-}
-
-/*
- * TMP431 has one local and one remote sensor.
- *
- * Temperature sensors data; must be in same order as enum temp_sensor_id.
- * Sensor index and name must match those present in coreboot:
- *     src/mainboard/google/${board}/acpi/dptf.asl
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
- * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	/* {Twarn, Thigh, Thalt}, <on>
-	 * {Twarn, Thigh, X    }, <off>
-	 * fan_off, fan_max
-	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Initialize PMIC */
-#define I2C_PMIC_READ(reg, data) \
-	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-#define I2C_PMIC_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
-
-static void board_pmic_init(void)
-{
-	int err;
-	int error_count = 0;
-	static uint8_t pmic_initialized = 0;
-
-	if (pmic_initialized)
-		return;
-
-	/* Read vendor ID */
-	while (1) {
-		int data;
-		err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data);
-		if (!err && data == TPS650X30_VENDOR_ID)
-			break;
-		else if (error_count > 5)
-			goto pmic_error;
-		error_count++;
-	}
-
-	/*
-	 * VCCIOCNT register setting
-	 * [6] : CSDECAYEN
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * VRMODECTRL:
-	 * [4] : VCCIOLPM clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PGMASK1 : Exclude VCCIO from Power Good Tree
-	 * [7] : MVCCIOPG clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PWFAULT_MASK1 Register settings
-	 * [7] : 1b V4 Power Fault Masked
-	 * [4] : 1b V7 Power Fault Masked
-	 * [2] : 1b V9 Power Fault Masked
-	 * [0] : 1b V13 Power Fault Masked
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 4 register configuration
-	 * [7:6] : 00b Reserved
-	 * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
-	 * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
-	 * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 3 register configuration
-	 * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
-	 * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
-	 * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
-	 * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 2 register configuration
-	 * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
-	 * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
-	 * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
-	 * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 1 register configuration
-	 * [7:2] : 00b Reserved
-	 * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Increase Voltage
-	 *  [7:0] : 0x2a default
-	 *  [5:4] : 10b default
-	 *  [5:4] : 01b 5.1V (0x1a)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PBCONFIG Register configuration
-	 *   [7] :      1b Power button debounce, 0ms (no debounce)
-	 *   [6] :      0b Power button reset timer logic, no action (default)
-	 * [5:0] : 011111b Force an Emergency reset time, 31s (default)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * V3.3A_DSW (VR3) control. Default: 0x2A.
-	 * [7:6] : 00b Disabled
-	 * [5:4] : 00b Vnom + 3%. (default: 10b 0%)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V33ADSWCNT, 0x0A);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * V100ACNT Register Field Description. Default: 0x2A
-	 * [1:0] : 11b Forced PWM Operation.
-	 * [5:4] : 01b Output Voltage Select Vnom (1V)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V100ACNT, 0x1B);
-	if (err)
-		goto pmic_error;
-
-	CPRINTS("PMIC init done");
-	pmic_initialized = 1;
-	return;
-
-pmic_error:
-	CPRINTS("PMIC init failed");
-}
-
-void chipset_pre_init_callback(void)
-{
-	board_pmic_init();
-}
-
-/**
- * Notify the AC presence GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/* Mapping to the old schematics */
-#define GPIO_U42_P GPIO_TYPE_C_60W
-#define GPIO_U22_C GPIO_TYPE_C_65W
-
-/*
- * Board version 2.1 or before uses a different current monitoring circuitry.
- */
-static void set_charge_limit(int charge_ma)
-{
-	/*
-	 * We have two FETs connected to two registers: PR257 & PR258.
-	 * These control thresholds of the over current monitoring system.
-	 *
-	 *                              PR257, PR258
-	 * For 4.62A (90W BJ adapter),     on,   off
-	 * For 3.33A (65W BJ adapter),    off,    on
-	 * For 3.00A (Type-C adapter),    off,   off
-	 *
-	 * The over current monitoring system doesn't support less than 3A
-	 * (e.g. 2.25A, 2.00A). These current most likely won't be enough to
-	 * power the system. However, if they're needed, EC can monitor
-	 * PMON_PSYS and trigger H_PROCHOT by itself.
-	 */
-	if (charge_ma >= 4620) {
-		gpio_set_level(GPIO_U42_P, 1);
-		gpio_set_level(GPIO_U22_C, 0);
-	} else if (charge_ma >= 3330) {
-		gpio_set_level(GPIO_U42_P, 0);
-		gpio_set_level(GPIO_U22_C, 1);
-	} else if (charge_ma >= 3000) {
-		gpio_set_level(GPIO_U42_P, 0);
-		gpio_set_level(GPIO_U22_C, 0);
-	} else {
-		/* TODO(http://crosbug.com/p/65013352) */
-		CPRINTS("Current %dmA not supported", charge_ma);
-	}
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int p87w = 0, p65w = 0, p60w = 0;
-
-	/*
-	 * Turn on/off power shortage alert. Performs the same check as
-	 * system_can_boot_ap(). It's repeated here because charge_manager
-	 * hasn't updated charge_current/voltage when board_set_charge_limit
-	 * is called.
-	 */
-	led_alert(charge_ma * charge_mv <
-			CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
-
-	/*
-	 * In terms of timing, this should always work because
-	 * HOOK_PRIO_CHARGE_MANAGER_INIT is notified after HOOK_PRIO_INIT_I2C.
-	 * If CBI isn't initialized or contains invalid data, we assume it's
-	 * a new board.
-	 */
-	if (0 < board_version && board_version < 0x0202)
-		return set_charge_limit(charge_ma);
-	/*
-	 * We have three FETs connected to three registers: PR257, PR258,
-	 * PR7824. These control the thresholds of the current monitoring
-	 * system.
-	 *
-	 *                               PR257  PR7824 PR258
-	 *   For BJ (65W or 90W)           off     off   off
-	 *   For 4.35A (87W)                on     off   off
-	 *   For 3.25A (65W)               off     off    on
-	 *   For 3.00A (60W)               off      on   off
-	 *
-	 * The system power consumption is capped by PR259, which is stuffed
-	 * differently depending on the SKU (65W v.s. 90W or U42 v.s. U22).
-	 * So, we only need to monitor type-c adapters. For example:
-	 *
-	 *   a 90W system powered by 65W type-c charger
-	 *   b 65W system powered by 60W type-c charger
-	 *   c 65W system powered by 87W type-c charger
-	 *
-	 * In a case such as (c), we actually do not need to monitor the current
-	 * because the max is capped by PR259.
-	 *
-	 * AP is expected to read type-c adapter wattage from EC and control
-	 * power consumption to avoid over-current or system browns out.
-	 *
-	 */
-	if (supplier != CHARGE_SUPPLIER_DEDICATED) {
-		/* Apple 87W charger offers 4.3A @20V. */
-		if (charge_ma >= 4300) {
-			p87w = 1;
-		} else if (charge_ma >= 3250) {
-			p65w = 1;
-		} else if (charge_ma >= 3000) {
-			p60w = 1;
-		} else {
-			/*
-			 * TODO:http://crosbug.com/p/65013352.
-	 		 * The current monitoring system doesn't support lower
-	 		 * current. These currents are most likely not enough to
-	 		 * power the system. However, if they're needed, EC can
-	 		 * monitor PMON_PSYS and trigger H_PROCHOT by itself.
-	 		 */
-			p60w = 1;
-			CPRINTS("Current %dmA not supported", charge_ma);
-		}
-	}
-
-	gpio_set_level(GPIO_TYPE_C_87W, p87w);
-	gpio_set_level(GPIO_TYPE_C_65W, p65w);
-	gpio_set_level(GPIO_TYPE_C_60W, p60w);
-}
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]   = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_GREEN] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct fan_step {
-	int on;
-	int off;
-	int rpm;
-};
-
-static const struct fan_step *fan_table;
-
-/* Note: Do not make the fan on/off point equal to 0 or 100 */
-static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 58, .off = 58, .rpm = 3200},
-	{.on = 66, .off = 61, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
-};
-static const struct fan_step fan_table1[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 62, .off = 58, .rpm = 3200},
-	{.on = 68, .off = 63, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
-};
-static const struct fan_step fan_table2[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2200},
-	{.on = 63, .off = 56, .rpm = 2900},
-	{.on = 69, .off = 65, .rpm = 3000},
-	{.on = 75, .off = 70, .rpm = 3300},
-	{.on = 80, .off = 76, .rpm = 3600},
-	{.on = 87, .off = 81, .rpm = 3900},
-	{.on = 98, .off = 91, .rpm = 5000},
-};
-static const struct fan_step fan_table3[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off = 22, .rpm = 2500},
-	{.on = 54, .off = 49, .rpm = 3200},
-	{.on = 61, .off = 56, .rpm = 3500},
-	{.on = 68, .off = 63, .rpm = 3900},
-	{.on = 75, .off = 69, .rpm = 4500},
-	{.on = 82, .off = 76, .rpm = 5100},
-	{.on = 92, .off = 85, .rpm = 5400},
-};
-/* All fan tables must have the same number of levels */
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
-BUILD_ASSERT(ARRAY_SIZE(fan_table1) == NUM_FAN_LEVELS);
-BUILD_ASSERT(ARRAY_SIZE(fan_table2) == NUM_FAN_LEVELS);
-BUILD_ASSERT(ARRAY_SIZE(fan_table3) == NUM_FAN_LEVELS);
-
-static void setup_fan(void)
-{
-	/* Configure Fan */
-	switch (oem) {
-	case OEM_KENCH:
-	case OEM_TEEMO:
-	case OEM_BLEEMO:
-	default:
-		fans[FAN_CH_0].rpm = &fan_rpm_1;
-		fan_table = fan_table0;
-		break;
-	case OEM_SION:
-		fans[FAN_CH_0].rpm = &fan_rpm_1;
-		fan_table = fan_table1;
-		break;
-	case OEM_WUKONG_N:
-	case OEM_WUKONG_A:
-	case OEM_WUKONG_M:
-		fans[FAN_CH_0].rpm = &fan_rpm_0;
-		fan_table = fan_table2;
-		break;
-	case OEM_JAX:
-		fan_set_count(0);
-		break;
-	case OEM_EXCELSIOR:
-		fans[FAN_CH_0].rpm = &fan_rpm_0;
-		fan_table = fan_table3;
-		break;
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	CPRINTS("Board Version: 0x%04x", board_version);
-
-	if (cbi_get_oem_id(&val) == EC_SUCCESS && val < OEM_COUNT)
-		oem = val;
-	CPRINTS("OEM: %d", oem);
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS && val <= UINT8_MAX)
-		sku = val;
-	CPRINTS("SKU: 0x%02x", sku);
-
-	setup_fan();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* List of BJ adapters shipped with Fizz or its variants */
-enum bj_adapter {
-	BJ_65W_19V,
-	BJ_90W_19V,
-	BJ_65W_19P5V,
-	BJ_90W_19P5V,
-};
-
-/* BJ adapter specs */
-static const struct charge_port_info bj_adapters[] = {
-	[BJ_65W_19V] = { .current = 3420, .voltage = 19000 },
-	[BJ_90W_19V] = { .current = 4740, .voltage = 19000 },
-	[BJ_65W_19P5V] = { .current = 3330, .voltage = 19500 },
-	[BJ_90W_19P5V] = { .current = 4620, .voltage = 19500 },
-};
-
-/*
- * Bit masks to map SKU ID to BJ adapter wattage. 1:90W 0:65W
- * KBL-R i7 8550U	4	90
- * KBL-R i5 8250U	5	90
- * KBL-R i3 8130U	6	90
- * KBL-U i7 7600	3	65
- * KBL-U i5 7500	2	65
- * KBL-U i3  7100	1	65
- * KBL-U Celeron 3965	7	65
- * KBL-U Celeron 3865	0	65
- */
-#define BJ_ADAPTER_90W_MASK (BIT(4) | BIT(5) | BIT(6))
-
-static void setup_bj(void)
-{
-	enum bj_adapter bj;
-
-	switch (oem) {
-	case OEM_KENCH:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
-		break;
-	case OEM_TEEMO:
-	case OEM_BLEEMO:
-	case OEM_SION:
-	case OEM_WUKONG_N:
-	case OEM_WUKONG_A:
-	case OEM_WUKONG_M:
-	case OEM_EXCELSIOR:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19V : BJ_65W_19V;
-		break;
-	case OEM_JAX:
-		bj = BJ_65W_19V;
-		break;
-	default:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
-		break;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &bj_adapters[bj]);
-}
-
-/*
- * Since fizz has no battery, it must source all of its power from either
- * USB-C or the barrel jack (preferred). Fizz operates in continuous safe
- * mode (charge_manager_leave_safe_mode() will never be called), which
- * modifies port / ILIM selection as follows:
- *
- * - Dual-role / dedicated capability of the port partner is ignored.
- * - Charge ceiling on PD voltage transition is ignored.
- * - CHARGE_PORT_NONE will never be selected.
- */
-static void board_charge_manager_init(void)
-{
-	enum charge_port port;
-	int i, j;
-
-	/* Initialize all charge suppliers to 0 */
-	for (i = 0; i < CHARGE_PORT_COUNT; i++) {
-		for (j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
-			charge_manager_update_charge(j, i, NULL);
-	}
-
-	port = gpio_get_level(GPIO_ADP_IN_L) ?
-			CHARGE_PORT_TYPEC0 : CHARGE_PORT_BARRELJACK;
-	CPRINTS("Power source is p%d (%s)", port,
-		port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ");
-
-	/* Initialize the power source supplier */
-	switch (port) {
-	case CHARGE_PORT_TYPEC0:
-		typec_set_input_current_limit(port, 3000, 5000);
-		break;
-	case CHARGE_PORT_BARRELJACK:
-		setup_bj();
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_charge_manager_init,
-	     HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
-static void board_init(void)
-{
-	/* Provide AC status to the PCH */
-	board_extpower();
-
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int fan_percent_to_rpm(int fan, int pct)
-{
-	static int current_level;
-	static int previous_pct;
-	int i;
-
-	/*
-	 * Compare the pct and previous pct, we have the three paths :
-	 *  1. decreasing path. (check the off point)
-	 *  2. increasing path. (check the on point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (pct < previous_pct) {
-		for (i = current_level; i >= 0; i--) {
-			if (pct <= fan_table[i].off)
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (pct > previous_pct) {
-		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
-			if (pct >= fan_table[i].on)
-				current_level = i;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	previous_pct = pct;
-
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		cprints(CC_THERMAL, "Setting fan RPM to %d",
-			fan_table[current_level].rpm);
-
-	return fan_table[current_level].rpm;
-}
diff --git a/board/fizz/board.h b/board/fizz/board.h
deleted file mode 100644
index d0cccd09ac..0000000000
--- a/board/fizz/board.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#undef  CONFIG_SYSTEM_UNLOCKED
-#define CONFIG_USB_PD_COMM_LOCKED
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_CRC8
-#define CONFIG_CEC
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_LED_COMMON
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_PWM
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
-#define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
-#define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_FAN_DYNAMIC
-#define CONFIG_FAN_RPM_CUSTOM
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_PWM
-
-/* EC console commands */
-#define CONFIG_CMD_BUTTON
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP432
-
-/* USB */
-#undef  CONFIG_USB_CHARGER		/* dnojiri: verify */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 1
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_DUMB
-#define USB_PORT_COUNT 5
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-
-/* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS		0x0b
-#define I2C_ADDR_EEPROM_FLAGS		0x50
-
-/* Verify and jump to RW image on boot */
-#define CONFIG_VBOOT_EFS
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/*
- * Flash layout. Since config_flash_layout.h is included before board.h,
- * we can only overwrite (=undef/define) these parameters here.
- *
- * Flash stores 3 images: RO, RW_A, RW_B. We divide the flash by 4.
- * A public key is stored at the end of RO. Signatures are stored at the
- * end of RW_A and RW_B, respectively.
- */
-#define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-
-#define CONFIG_RWSIG
-#define CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RSA
-#ifdef SECTION_IS_RO
-#define CONFIG_RSA_OPTIMIZED
-#endif
-#define CONFIG_SHA256
-#ifdef SECTION_IS_RO
-#define CONFIG_SHA256_UNROLLED
-#endif
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_FAN,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-enum OEM_ID {
-	OEM_KENCH = 0,
-	OEM_TEEMO = 1,
-	OEM_SION = 2,
-	OEM_WUKONG_N = 3,
-	OEM_WUKONG_A = 4,
-	OEM_WUKONG_M = 5,
-	OEM_BLEEMO = 6,
-	OEM_JAX = 8,
-	OEM_EXCELSIOR = 10,
-	/* Number of OEM IDs */
-	OEM_COUNT
-};
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power. Since Fizz doesn't have a battery to charge,
- * we're not interested in any power lower than the AP power-on threshold. */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void led_critical(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/fizz/build.mk b/board/fizz/build.mk
deleted file mode 100644
index 74094ac834..0000000000
--- a/board/fizz/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-board-y+=led.o
diff --git a/board/fizz/dev_key.pem b/board/fizz/dev_key.pem
deleted file mode 100644
index b72c787613..0000000000
--- a/board/fizz/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4gIBAAKCAYEAseZZZlXXDP+KrjqV+XhP0ZgPlU5mX4GCm27yzTqcKiFWLlHZ
-3f8seGG0lKNiL7WvHim8uSEDaPbp2us4uaJ6nTHEpbSGi2QVp90tE3aJG34HyKlg
-jcaE1r/0n6ynG/bf0Xx4O63Plp3Czi3TBYW49vT6+T/Jyfl2JpGQ9KNcD0umafsv
-uaEmdrLGrzjN8w1mFZfwscFkfVDh0cdiFNJ+UkTSpO9/yPapXbo4/lOMwdO9xILF
-cEZV9I7K7lBSvQ5Uep+w0SqNPTh2cGhoeEeDyH+Ce0LA8H7ZwbVnwLe1RswF9Wek
-uzqp9lMSNkkwMtTkumTuJLLGJX9rc0MVQTKgNV8wIzizf5lkCCBCJLf7aRBaeWCJ
-cXjKiavSPOZXDcnqCWqRJT3jN4ibAsU1GQtqLa8pTAi2wkE0fjuvAWK3NYuvpukg
-qNq2LI+BJkF4+dCZoeB1PDNyFNzdOFvkxj2+ImS3DLlPYVng4vHsTK1HRUUpL5Ag
-jjfMhMs4NC7HMOCTAgEDAoIBgHaZkO7j5LNVBx7RuVD63+EQCmOJmZUBAbz0od4n
-EsbA5B7hO+lUyFBBIw3CQXUjyhQb0yYWAkX58Tyc0HvBpxN2gxkjBFztY8U+Hgz5
-sLz+r9sblbPZreR/+GpzGhKklTZS+tJz37m+gd7JN1kD0KSjUft/29v7pBm2YKMX
-krTdGZv8ynvAxE8h2col3qII7rkP9cvWQv416+EvlriMVDbYjG30/9tPG5PRe1Q3
-syvifoMB2PWEOU20h0mK4dNe4d7E96s1Q+RTmTUtyipxUp6d4PIufAjMtM8yfkb0
-/0z81IsWQ0NOhefrMAi8TEcDkbyNSBPqHqbqH2FosFWo2cU3r6TXv2LdvFzc5BA+
-U6c+fXz7BDjv+NT3Bh98whKvTdJYcIgSg6vqzW7ZWJWWllZQtpJnQccIq4sPaL4S
-osFg8jd1kcbjVakCN0wYtfvMa/+WBZNNsZLUHoeIJvO7qnT7VKzhceoKHCJCMxNR
-Ypu5eELxCwebTXiImDqmFsKIawKBwQDpDjff6eatHbjmGV1elTyV5MLi95Tc0T7P
-FZHC1KLXkA/mEuXjAGfoZuLB5a3WmrA8r8fWNZoKV+0RBKIs3at1JFxZn9YiA0Hy
-5qmnYkXjMaY4p5AyO3eJsc2kbsh9r0cy2cb5GdwFDApeoVICoQh+dW9FpvIS+9AF
-0DVc2/Rg//cuXLlCMonF+PZVmDxRNhjBvwvRjxeowiu2ntI4sa83nHMhXI/RfvV4
-xcSng8gSIvabUmunDcPKvqO3rnpHzVECgcEAw2oFcHDAuZ1Xuopb2ghLRK3uLQVy
-BnqLu9QYk3OTe8C3PrNZ80R5MgtnZ0kP8bTZ4uE6MJ3+IMhPUCFqk9euGGdMUlU+
-SUmHie5CZPg4CwD4BUBy6dVdwId7aTxrdBOuGwwhYAhBsJxcfd3eNgiALcCoKsbi
-BLhjJ9Rch2rOsnpNJVwMvFMr6RM33oQrrufe4MBhDa/QD9yDtnDYH/KPO09E6AqU
-sMvBNsjbCC9rSYv+L9QkW8EUhT+wJIcqxUajAoHBAJtez+qb7x4T0JlmPj8OKGPt
-10H6Yz3g1IoOYSyNweUKtUQMmUIARUWZ7IFDyTm8dX3KhTl5EVw6ngtYbB3pHPjC
-6Du/5Bas1qHvG8TsLpd2btBvtXbST7EhM8L0hakfhMyRL1C76ANdXD8WNqxrWv74
-9NkZ9rdSiq6Kzj3n+ECqpMmTJiwhsS6l+Y5lfYt5ZdZ/XTZfZRssHSRp4XshH3po
-TMDoX+D/TlCD2G+tMAwXTxI28m9egocpwnp0UYUziwKBwQCCRq5K9dXRE4/RsZKR
-WtzYc/QeA6FZpwfSjWW3omJSgHopzOaiLaYhXO+aMLVLzeaXQNF1vqlrMDTgFkcN
-OnQQRN2MONQw26+xSYGYpXqyAKVY1aHxOOkrBPzw0vJNYnQSCBZABYEgaD2pPpQk
-BarJKxrHL0FYeuzFOD2vnInMUYjDkrMoN3KbYiU/AsfJ7+nrKutedTVf6FfO9eVq
-obTSNNiasbh13St52zywH5zbsql1OBg9K2MDf8rDBMcuLxcCgcBfM9FWZivdG2tJ
-5REvL0vPAQfcjVi4HUHvnaCuwMYEuF5T2Xf9P8d8ZflfWHaGlkl/qPvE897fns2l
-PZvvhRnr9GlHKt940ZOTI2v+hjlwcHGAAQc+p7BcKeUYLChwhVK/cZ9f6ZCotZNh
-543ecG4KZiJaqBZ/mDRaW7Py0w6lbOAzprrHF3ChvQ6VAllajoWx4CeINRcxX2vP
-bAPZxvt0gwpoHtUAsZo/bKEF0sM5qM/fK43gH5KhJeunq/xHO7E=
------END RSA PRIVATE KEY-----
diff --git a/board/fizz/ec.tasklist b/board/fizz/ec.tasklist
deleted file mode 100644
index 75a09a43df..0000000000
--- a/board/fizz/ec.tasklist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 2048) \
-	/* Larger stack for RW verification (i.e. sha256, rsa) */ \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CEC, cec_task, NULL, TASK_STACK_SIZE)
diff --git a/board/fizz/gpio.inc b/board/fizz/gpio.inc
deleted file mode 100644
index 7da0bfce71..0000000000
--- a/board/fizz/gpio.inc
+++ /dev/null
@@ -1,114 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(WP_L,			PIN(9, 3), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(ADP_IN_L,		PIN(C, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	adp_in)	/* Low: BJ detected */
-GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus0_evt)
-GPIO_INT(RECOVERY_L,		PIN(8, 2), GPIO_INT_BOTH, button_interrupt)	/* Recovery button */
-GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
-GPIO(PCH_ACPRESENT,		PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_ODR_HIGH)			/* H1 Reset */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
-GPIO(TYPE_C_60W,		PIN(3, 3), GPIO_OUTPUT | GPIO_PULL_DOWN)
-GPIO(TYPE_C_65W,		PIN(3, 4), GPIO_OUTPUT | GPIO_PULL_DOWN)
-GPIO(TYPE_C_87W,		PIN(4, 4), GPIO_OUTPUT | GPIO_PULL_DOWN)
-GPIO(POWER_RATE,		PIN(7, 1), GPIO_INPUT)				/* High: i3/5/7. Low: Celeron */
-
-/* Fizz specific pins */
-GPIO(LAN_PWR_EN,		PIN(8, 3), GPIO_OUT_HIGH)			/* Ethernet power enabled */
-
-GPIO(PP5000_DX_NFC,		PIN(1, 5), GPIO_OUTPUT)
-
-GPIO(PP3300_DX_CAM,		PIN(1, 0), GPIO_OUT_HIGH)
-GPIO(CAM_PMIC_RST_L,		PIN(0, 7), GPIO_INPUT)
-
-GPIO(WLAN_PE_RST,		PIN(1, 2), GPIO_OUTPUT)
-GPIO(PP3300_DX_LTE,		PIN(0, 5), GPIO_OUT_LOW)
-GPIO(PP3300_DX_BASE,		PIN(1, 1), GPIO_OUT_LOW)
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_BAT_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_BAT_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_ROP_I2C_CLK */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_ROP_I2C_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT)				/* EC_THEM_CLK */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT)				/* EC_THEM_SDA */
-
-/* 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C0 5V Enable */
-GPIO(USB_C0_CHARGE_L,		PIN(C, 0), GPIO_OUT_LOW)			/* C0 Charge enable */
-GPIO(AC_JACK_CHARGE_L,		PIN(C, 3), GPIO_OUT_LOW)			/* AC jack charge enable */
-GPIO(USB_C0_PD_RST_ODL,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(FAN_PWR_EN,		PIN(9, 5), GPIO_OUT_HIGH)			/* Fan power */
-GPIO(USB1_ENABLE,		PIN(3, 2), GPIO_OUT_LOW)			/* Rear port, bottom */
-GPIO(USB2_ENABLE,		PIN(C, 6), GPIO_OUT_LOW)			/* Rear port, top */
-GPIO(USB3_ENABLE,		PIN(A, 1), GPIO_OUT_LOW)			/* Rear port, single */
-GPIO(USB4_ENABLE,		PIN(0, 0), GPIO_OUT_LOW)			/* Front port 1 */
-GPIO(USB5_ENABLE,		PIN(B, 1), GPIO_OUT_LOW)			/* Front port 2 */
-GPIO(USB_A_CHARGE_EN_L,		PIN(A, 5), GPIO_OUT_LOW)
-
-GPIO(CEC_OUT,			PIN(3, 6), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
-GPIO(CEC_IN,			PIN(4, 0), GPIO_INPUT)
-GPIO(CEC_PULL_UP,		PIN(D, 3), GPIO_OUT_HIGH)
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 4), GPIO_INPUT)	/* Board ID bit0 */
-GPIO(BOARD_VERSION2,		PIN(C, 2), GPIO_INPUT)	/* Board ID bit1 */
-GPIO(BOARD_VERSION3,		PIN(0, 1), GPIO_INPUT)	/* Board ID bit2 */
-
-/* Test points */
-GPIO(TP248,			PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)		/* EC_GPIO57 */
-GPIO(TP249,			PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)		/* EC_GPO66_ARM_L */
-GPIO(TP250,			PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)		/* EC_GPIO35_TEST_L */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0)		/* GPIOA6 */		/* TACH2 */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_USBC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)		/* GPIOB6 */		/* EC_FAN_PWM */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
-/* Alternate functions for LED PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)		/* GPIO80 PWM3 Red*/
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)		/* GPOB7 PWM5 Green*/
diff --git a/board/fizz/led.c b/board/fizz/led.c
deleted file mode 100644
index 9b6942d241..0000000000
--- a/board/fizz/led.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Fizz
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int green = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_GREEN:
-		green = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		green = 1;
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (green)
-		pwm_set_duty(PWM_CH_LED_GREEN, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_GREEN, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec. */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-	static uint8_t pwm_enabled = 0;
-
-	if (!pwm_enabled) {
-		pwm_enable(PWM_CH_LED_RED, 1);
-		pwm_enable(PWM_CH_LED_GREEN, 1);
-		pwm_enabled = 1;
-	}
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
-	led_tick();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend, HOOK_PRIO_DEFAULT);
-
-static void led_shutdown(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task. */
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown();
-	}
-}
-
-void led_critical(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "green")) {
-		set_color(id, LED_GREEN, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		led_critical();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/fizz/usb_pd_policy.c b/board/fizz/usb_pd_policy.c
deleted file mode 100644
index 5de57f3c9b..0000000000
--- a/board/fizz/usb_pd_policy.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4750, 21000, 50000),
-	PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-int board_vbus_source_enabled(int port)
-{
-	if (port != 0)
-		return 0;
-	return gpio_get_level(GPIO_USB_C0_5V_EN);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-
-	/* Enable VBUS source */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS source */
-	gpio_set_level(GPIO_USB_C0_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/* If type-c port is supplying power, we never swap PR (to source) */
-	if (port == charge_manager_get_active_charge_port())
-		return 0;
-	/*
-	 * Allow power swap as long as we are acting as a dual role device,
-	 * otherwise assume our role is fixed (not in S0 or console command
-	 * to fix our role).
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-int board_set_active_charge_port(int port)
-{
-	const int active_port = charge_manager_get_active_charge_port();
-
-	if (port < 0 || CHARGE_PORT_COUNT <= port)
-		return EC_ERROR_INVAL;
-
-	if (port == active_port)
-		return EC_SUCCESS;
-
-	/* Don't charge from a source port */
-	if (board_vbus_source_enabled(port))
-		return EC_ERROR_INVAL;
-
-	CPRINTS("New charger p%d", port);
-
-	switch (port) {
-	case CHARGE_PORT_TYPEC0:
-		/* This is connected to TP on board version 2.2+ thus no-op */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 0);
-		gpio_set_level(GPIO_AC_JACK_CHARGE_L, 1);
-		gpio_enable_interrupt(GPIO_ADP_IN_L);
-		break;
-	case CHARGE_PORT_BARRELJACK:
-		/* Make sure BJ adapter is sourcing power */
-		if (gpio_get_level(GPIO_ADP_IN_L))
-			return EC_ERROR_INVAL;
-		/* This will cause brown out when switching from type-c on
-		 * board version 2.2+ thus the rest of the code is no-op. */
-		gpio_set_level(GPIO_AC_JACK_CHARGE_L, 0);
-		/* If type-c voltage > BJ voltage, we'll brown out due to the
-		 * reverse current protection of PU3 but it's intended. */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-		gpio_disable_interrupt(GPIO_ADP_IN_L);
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_get_battery_soc(void)
-{
-	return 100;
-}
diff --git a/board/fizz/vif_override.xml b/board/fizz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/fizz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/fleex/analyzestack.yaml b/board/fleex/analyzestack.yaml
deleted file mode 100644
index 08c8ba93a9..0000000000
--- a/board/fleex/analyzestack.yaml
+++ /dev/null
@@ -1,278 +0,0 @@
-# Size of extra stack frame needed by exception context switch.
-# See core/cortex-m/switch.S
-exception_frame_size: 224
-# Missing calls
-add:
-  # TCPC stack
-  tcpm_set_cc[driver/tcpm/tcpm.h:139]:
-    - tcpci_tcpm_set_cc
-  tcpm_set_rx_enable[driver/tcpm/tcpm.h:160]:
-    - tcpci_tcpm_set_rx_enable
-  tcpm_set_snk_ctrl[driver/tcpm/tcpm.h:179]:
-    - tcpci_tcpm_set_snk_ctrl
-  tcpm_get_cc[driver/tcpm/tcpm.h:124]:
-    - tcpci_tcpm_get_cc
-  enter_low_power_mode[driver/usb_mux.c:42]:
-    - tcpci_enter_low_power_mode
-  svdm_exit_dp_mode[baseboard/octopus/usb_pd_policy.c:346]:
-    - anx7447_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  tcpm_set_src_ctrl[driver/tcpm/tcpm.h:187]:
-    - tcpci_tcpm_set_src_ctrl
-  tcpm_init[driver/tcpm/tcpm.h:106]:
-    - anx7447_init
-    - tcpci_tcpm_init
-  tcpm_get_vbus_level[driver/tcpm/tcpm.h:129]:
-    - anx7447_tcpm_get_vbus_level
-    - tcpci_tcpm_get_vbus_level
-  baseboard_tcpc_init[baseboard/octopus/baseboard.c:212]:
-    - anx7447_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  tcpm_get_chip_info[driver/tcpm/tcpm.h:240]:
-    - tcpci_get_chip_info
-    - ps8xxx_get_chip_info
-  tcpm_transmit[driver/tcpm/tcpm.h:172]:
-    - tcpci_tcpm_transmit
-    - ps8xxx_tcpm_transmit
-  tcpc_alert[driver/tcpm/tcpm.h:195]:
-    - anx7447_tcpc_alert
-    - tcpci_tcpc_alert
-  tcpm_set_msg_header[driver/tcpm/tcpm.h:154]:
-    - tcpci_tcpm_set_msg_header
-  tcpm_set_vconn[driver/tcpm/tcpm.h:149]:
-    - tcpci_tcpm_set_vconn
-  tcpm_select_rp_value[driver/tcpm/tcpm.h:134]:
-    - tcpci_tcpm_select_rp_value
-  tcpm_enqueue_message[driver/tcpm/tcpci.c:404]:
-    - tcpci_tcpm_get_message_raw
-  svdm_dp_post_config[baseboard/octopus/usb_pd_policy.c:320]:
-    - anx7447_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  svdm_dp_attention[baseboard/octopus/usb_pd_policy.c:335]:
-    - anx7447_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  tcpm_release[driver/tcpm/tcpm.h:119]:
-    - anx7447_release
-    - ps8xxx_tcpm_release
-  tcpm_set_polarity[driver/tcpm/tcpm.h:144]:
-    - tcpci_tcpm_set_polarity
-  tcpm_enable_drp_toggle[driver/tcpm/tcpm.h:211]:
-    - tcpci_tcpc_drp_toggle
-  tcpm_enter_low_power_mode[driver/tcpm/tcpm.h:218]:
-    - tcpci_enter_low_power_mode
-  # USB mux
-  usb_mux_flip[driver/usb_mux.c:163]:
-    - anx7447_mux_get
-    - tcpci_tcpm_mux_get
-  usb_mux_flip[driver/usb_mux.c:174]:
-    - anx7447_mux_set
-    - tcpci_tcpm_mux_set
-  usb_mux_set[driver/usb_mux.c:112]:
-    - anx7447_mux_set
-    - tcpci_tcpm_mux_set
-  usb_mux_init[driver/usb_mux.c:64]:
-    - anx7447_mux_init
-    - tcpci_tcpm_mux_init
-  usb_mux_get[driver/usb_mux.c:140]:
-    - anx7447_mux_get
-    - tcpci_tcpm_mux_get
-  hc_usb_pd_mux_info[driver/usb_mux.c:240]:
-    - anx7447_mux_get
-    - tcpci_tcpm_mux_get
-  # PPC
-  ppc_is_sourcing_vbus[common/usbc_ppc.c:42]:
-    - nx20p348x_is_sourcing_vbus
-  ppc_init[common/usbc_ppc.c:26]:
-    - nx20p348x_init
-  ppc_vbus_sink_enable[common/usbc_ppc.c:86]:
-    - nx20p348x_vbus_sink_enable
-  ppc_discharge_vbus[common/usbc_ppc.c:68]:
-    - nx20p348x_discharge_vbus
-  ppc_vbus_source_enable[common/usbc_ppc.c:107]:
-    - nx20p348x_vbus_source_enable
-  ppc_set_vbus_source_current_limit[common/usbc_ppc.c:60]:
-    - nx20p348x_set_vbus_source_current_limit
-  command_ppc_dump[common/usbc_ppc.c:135]:
-    - nx20p348x_dump
-  # Motion sensors
-  command_accelrange[common/motion_sense.c:1513]:
-    - set_range[driver/accel_lis2dh.c]
-    - set_range[driver/accelgyro_lsm6dsm.c]
-  command_accelrange[common/motion_sense.c:1519]:
-    - get_range[driver/accel_lis2dh.c]
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  motion_sensor_time_to_read[common/motion_sense.c:213]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  motion_sense_read[common/motion_sense.c:694]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  motion_sense_read[common/motion_sense.c:707]:
-    - read[driver/accel_lis2dh.c]
-    - read[driver/accelgyro_lsm6dsm.c]
-  motion_sense_process[common/motion_sense.c:719]:
-    - irq_handler[driver/accelgyro_lsm6dsm.c]
-  sensor_init_done[common/motion_sense.c:468]:
-    - set_range[driver/accel_lis2dh.c]
-    - set_range[driver/accelgyro_lsm6dsm.c]
-  sensor_init_done[common/motion_sense.c:471]:
-    - get_range[driver/accel_lis2dh.c]
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  motion_sense_set_ec_rate_from_ap[common/motion_sense.c:305]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  host_cmd_motion_sense[common/motion_sense.c:1242]:
-    - set_range[driver/accel_lis2dh.c]
-    - set_range[driver/accelgyro_lsm6dsm.c]
-  host_cmd_motion_sense[common/motion_sense.c:1253]:
-    - get_range[driver/accel_lis2dh.c]
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  host_cmd_motion_sense[common/motion_sense.c:1268]:
-    - st_set_offset[driver/stm_mems_common.c]
-  host_cmd_motion_sense[common/motion_sense.c:1303]:
-    - None
-  host_cmd_motion_sense[common/motion_sense.c:1306]:
-    - st_get_offset[driver/stm_mems_common.c]
-  motion_sense_init[common/motion_sense.c:447]:
-    - init[driver/accel_lis2dh.c]
-    - init[driver/accelgyro_lsm6dsm.c]
-  motion_sense_set_data_rate[common/motion_sense.c:267]:
-    - set_data_rate[driver/accel_lis2dh.c]
-    - set_data_rate[driver/accelgyro_lsm6dsm.c]
-  motion_sense_set_data_rate[common/motion_sense.c:287]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  motion_sense_set_motion_intervals[common/motion_sense.c:411]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  calculate_lid_angle[common/motion_lid.c:385]:
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  calculate_lid_angle[common/motion_lid.c:386]:
-    - get_range[driver/accel_lis2dh.c]
-  motion_sense_set_data_rate[common/motion_sense.c:286]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  command_accel_read_xyz[common/motion_sense.c:1657]:
-    - read[driver/accel_lis2dh.c]
-    - read[driver/accelgyro_lsm6dsm.c]
-  host_cmd_motion_sense[common/motion_sense.c:1294]:
-    - None
-  host_cmd_motion_sense[common/motion_sense.c:1297]:
-    - st_get_offset[driver/stm_mems_common.c]
-  command_accelresolution[common/motion_sense.c:1562]:
-    - None
-  command_accelresolution[common/motion_sense.c:1566]:
-    - st_get_resolution[driver/stm_mems_common.c]
-  command_accelrange[common/motion_sense.c:1518]:
-    - get_range[driver/accel_lis2dh.c]
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  st_normalize[driver/stm_mems_common.c:137]:
-    - get_range[driver/accel_lis2dh.c]
-    - get_range[driver/accelgyro_lsm6dsm.c]
-  command_accel_data_rate[common/motion_sense.c:1621]:
-    - st_get_data_rate[driver/stm_mems_common.c]
-  # Misc.
-  host_send_response[common/host_command.c:153]:
-    - host_packet_respond
-  pd_dfp_enter_mode[common/usb_pd_policy.c:465]:
-    - svdm_enter_dp_mode[baseboard/octopus/usb_pd_policy.c]
-    - svdm_enter_gfu_mode[baseboard/octopus/usb_pd_policy.c]
-  pd_svdm[common/usb_pd_policy.c:773]:
-    - svdm_dp_status[baseboard/octopus/usb_pd_policy.c]
-    - svdm_gfu_status[baseboard/octopus/usb_pd_policy.c]
-  pd_svdm[common/usb_pd_policy.c:784]:
-    - svdm_dp_config[baseboard/octopus/usb_pd_policy.c]
-    - svdm_gfu_config[baseboard/octopus/usb_pd_policy.c]
-  pd_svdm[common/usb_pd_policy.c:790]:
-    - svdm_dp_post_config[baseboard/octopus/usb_pd_policy.c]
-  dfp_consume_attention[common/usb_pd_policy.c:503]:
-    - svdm_dp_attention[baseboard/octopus/usb_pd_policy.c]
-    - svdm_gfu_attention[baseboard/octopus/usb_pd_policy.c]
-  kblight_set_deferred[common/keyboard_backlight.c:35]:
-    - kblight_pwm_set
-  temp_sensor_read[common/temp_sensor.c:26]:
-    - charge_get_battery_temp
-    - get_temp_3v3_51k1_47k_4050b
-    - get_temp_3v3_13k7_47k_4050b
-  kblight_enable[common/keyboard_backlight.c:61]:
-    - kblight_pwm_enable
-  host_packet_respond[common/host_command.c:240]:
-    - lpc_send_response
-  kblight_init[common/keyboard_backlight.c:28]:
-    - kblight_pwm_init
-  vfnprintf[common/printf.c:75]:
-    - __tx_char
-  vfnprintf[common/printf.c:88]:
-    - __tx_char
-  vfnprintf[common/printf.c:96]:
-    - __tx_char
-  vfnprintf[common/printf.c:171]:
-    - __tx_char
-  vfnprintf[common/printf.c:172]:
-    - __tx_char
-  vfnprintf[common/printf.c:310]:
-    - __tx_char
-  vfnprintf[common/printf.c:315]:
-    - __tx_char
-  vfnprintf[common/printf.c:318]:
-    - __tx_char
-  pd_dfp_exit_mode[common/usb_pd_policy.c:569]:
-    - svdm_exit_dp_mode[baseboard/octopus/usb_pd_policy.c]
-    - svdm_exit_gfu_mode[baseboard/octopus/usb_pd_policy.c]
-  pd_dfp_exit_mode[common/usb_pd_policy.c:586]:
-    - svdm_exit_dp_mode[baseboard/octopus/usb_pd_policy.c]
-    - svdm_exit_gfu_mode[baseboard/octopus/usb_pd_policy.c]
-  # Indirect callsites in common structures - likely common for all boards
-  handle_command[common/console.c:248]:
-    - { name: __cmds, stride: 16, offset: 4 }
-  host_command_process[common/host_command.c:704]:
-    - { name: __hcmds, stride: 12, offset: 0 }
-  mkbp_get_next_event[common/mkbp_event.c:160]:
-    - { name:  __mkbp_evt_srcs, stride: 8, offset: 4 }
-  hook_task[common/hooks.c:199]:
-    - { name: __deferred_funcs, stride: 4, offset: 0 }
-  # Note: This assumes worse case, where all hook functions can be called from
-  # any hook_notify call
-  # Generate using `grep hooks_.*_end build/$BOARD/R*/ec.R*.smap |
-  #   sed -e 's/.*\(__hooks.*\)_end/    - { name: \1, stride: 8, offset: 0 }/' |
-  #   sort -u`
-  hook_notify[common/hooks.c:129]:
-    - { name: __hooks_ac_change, stride: 8, offset: 0 }
-    - { name: __hooks_base_attached_change, stride: 8, offset: 0 }
-    - { name: __hooks_battery_soc_change, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_pre_init, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_reset, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_resume, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_shutdown, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_startup, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_suspend, stride: 8, offset: 0 }
-    - { name: __hooks_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_init, stride: 8, offset: 0 }
-    - { name: __hooks_lid_change, stride: 8, offset: 0 }
-    - { name: __hooks_pre_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_pwrbtn_change, stride: 8, offset: 0 }
-    - { name: __hooks_second, stride: 8, offset: 0 }
-    - { name: __hooks_sysjump, stride: 8, offset: 0 }
-    - { name: __hooks_tablet_mode_change, stride: 8, offset: 0 }
-    - { name: __hooks_tick, stride: 8, offset: 0 }
-    - { name: __hooks_usb_pd_disconnect, stride: 8, offset: 0 }
-  # NULL function pointers
-  i2c_command_passthru[common/i2c_master.c:678]:
-    - None
-  pd_svdm[common/usb_pd_policy.c:720]:
-    - None
-  usb_mux_init[driver/usb_mux.c:75]:
-    - None
-remove:
-# Remove panic callsites.  Once panicking, we no longer care about stack usage
-- panic_assert_fail
-# Remove reset_device_and_notify for all non-PD analysis since it can only be called from PD task IDs.  Comment this out for the PD tasks
-- reset_device_and_notify
-# Remove the LPM path because the PD_FLAGS_LPM_TRANSITION flag presents this loop
-- [ reset_device_and_notify, tcpci_tcpm_init, [ tcpc_read, tcpc_write16 ], pd_wait_for_wakeup ]
-# Remove nonesense hook paths that come from the general hook_notify above (Note: these are not a comprehensive list, but a list of
-# paths that came up as longest during analysis
-# These functions do not call HOOK_INIT
-- [ [ s0ix_transition, charger_task, power_button_change_deferred, jump_to_image, tablet_set_mode, pd_set_suspend, set_state, extpower_deferred, lid_switch_open, lid_switch_close, espi_chipset_reset, lpc_chipset_reset ], hook_notify, [ usb_charger_init, baseboard_tcpc_init, motion_sense_startup, gmr_tablet_switch_init, powerbtn_x86_init, cbi_init  ] ]
-# These functions do not call HOOK_CHIPSET_SHUTDOWN
-- [ [ s0ix_transition, charger_task, power_button_change_deferred, jump_to_image, tablet_set_mode, pd_set_suspend, set_state, extpower_deferred, lid_switch_open, lid_switch_close, hook_task, espi_chipset_reset, lpc_chipset_reset ], hook_notify, [ system_common_shutdown, motion_sense_shutdown, board_disable_a1_redriver ] ]
-# These functions do not call HOOK_LID_CHANGE
-- [ [ s0ix_transition, charger_task, power_button_change_deferred, jump_to_image, tablet_set_mode, pd_set_suspend, set_state, extpower_deferred, hook_task, espi_chipset_reset, lpc_chipset_reset ], hook_notify, powerbtn_x86_lid_change ]
-# These functions do not call HOOK_BATTERY_SOC_CHANGE
-- [ [ s0ix_transition, power_button_change_deferred, jump_to_image, tablet_set_mode, pd_set_suspend, set_state, extpower_deferred, lid_switch_open, lid_switch_close, hook_task, espi_chipset_reset, lpc_chipset_reset ], hook_notify, power_up_inhibited_cb ]
-# These functions do not call HOOK_CHIPSET_STARTUP
-- [ [ charger_task, power_button_change_deferred, jump_to_image, tablet_set_mode, pd_set_suspend, set_state, extpower_deferred, lid_switch_open, lid_switch_close, hook_task, espi_chipset_reset, lpc_chipset_reset ], hook_notify, board_enable_a1_redriver ]
diff --git a/board/fleex/battery.c b/board/fleex/battery.c
deleted file mode 100644
index 57a5246052..0000000000
--- a/board/fleex/battery.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all fleex battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* BYD Battery Information */
-	[BATTERY_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* BYD 16DPHYMD Battery Information */
-	[BATTERY_BYD16] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD-BYD3.685",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* LGC Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.553",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* LGC JPFMRYMD Battery Information */
-	[BATTERY_LGC3] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC-LGC3.685",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO Battery Information */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI3.72",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO-ATL 7T0D3YMD Battery Information */
-	[BATTERY_SIMPLO_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-ATL3.61",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO-LISHEN 7T0D3YMD Battery Information */
-	[BATTERY_SIMPLO_LS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LS3.66",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SIMPLO-COSMX 7T0D3YMD Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-COS3.63",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x043,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SWD-ATL 65N6HYMD Battery Information */
-	[BATTERY_SWD_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.618",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SWD-COSLIGHT 65N6HYMD Battery Information */
-	[BATTERY_SWD_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD-COS3.634",
-			.ship_mode = {
-				.wb_support = 1,
-				.reg_addr = 0x44,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
diff --git a/board/fleex/board.c b/board/fleex/board.c
deleted file mode 100644
index 7e11d671c6..0000000000
--- a/board/fleex/board.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fleex board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-static int is_support_syv_ppc;
-
-const struct ppc_config_t ppc_syv682x_port0 = {
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-	.drv = &syv682x_drv,
-};
-
-const struct ppc_config_t ppc_syv682x_port1 = {
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-	.drv = &syv682x_drv,
-};
-
-/* Check PPC_ID pin status to decide which one ppc is used. */
-static int board_is_syv_ppc(void)
-{
-	return gpio_get_level(GPIO_PPC_ID);
-}
-
-static void board_update_ppc_config_from_board(void)
-{
-	if (!is_support_syv_ppc)
-		return;
-
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-	       &ppc_syv682x_port0,
-	       sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-	       &ppc_syv682x_port1,
-	       sizeof(struct ppc_config_t));
-
-	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
-	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		if (is_support_syv_ppc)
-			syv682x_interrupt(0);
-		else
-			nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		if (is_support_syv_ppc)
-			syv682x_interrupt(1);
-		else
-			nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C0] = {"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
- const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
- };
-
-/* sensor private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23
-		|| sku_id == 0xff;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-static void charger_set_buck_boost_mode(void)
-{
-	int reg;
-	/* Reduce Buck-boost mode switching frequency to improve power efficiency. */
-	if (i2c_read16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
-		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
-		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-				ISL9238_REG_CONTROL3, reg))
-			ccprints("Failed to set isl9238");
-	}
-}
-
-static void board_init(void)
-{
-	charger_set_buck_boost_mode();
-
-	is_support_syv_ppc = board_is_syv_ppc();
-
-	board_update_ppc_config_from_board();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
-
-	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
-}
diff --git a/board/fleex/board.h b/board/fleex/board.h
deleted file mode 100644
index cd04f31687..0000000000
--- a/board/fleex/board.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fleex board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/*
- * Some fuel gagues will return 1% immediately, without the battery being
- * charged to the point of being able to withstand Vbus loss, so re-set
- * allowable Try.SRC level and reset level to 2%
- */
-#undef CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
-#define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 2
-
-#define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* Volume button */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* TI gauge IC 500ms WDT timeout setting under battery sleep mode
- * induced battery cut-off, under the following conditions:
- * 1. SMBus communication on FC is once per minute which allows
- * battery entering sleep mode;
- * 2. System load < 10mA and accumulate 5 hours will trigger battery
- * simulation and result in a 500ms WDT timeout. So change charge
- * max sleep time from once/minute to once/10 seconds to prevent
- * battery entering sleep mode. See b/133375756.
- */
-#define CHARGE_MAX_SLEEP_USEC (10 * SECOND)
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Additional PPC second source */
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_DEDICATED_INT
-/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_BYD,
-	BATTERY_BYD16,
-	BATTERY_LGC,
-	BATTERY_LGC3,
-	BATTERY_SIMPLO,
-	BATTERY_SIMPLO_ATL,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_LS,
-	BATTERY_SWD_ATL,
-	BATTERY_SWD_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/fleex/build.mk b/board/fleex/build.mk
deleted file mode 100644
index 7e806f4667..0000000000
--- a/board/fleex/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/fleex/ec.tasklist b/board/fleex/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/fleex/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
deleted file mode 100644
index efedd6989b..0000000000
--- a/board/fleex/gpio.inc
+++ /dev/null
@@ -1,193 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT, 	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,	 PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L, 	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	 PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Camera */
-GPIO(EC_GPIO03, 	 PIN(0, 3), GPIO_INPUT)		/* TP only */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-GPIO(PPC_ID,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_DOWN)	/* PPC ID Pin */
-
-/* Unused Pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(LED_3_L,		PIN(D, 7), GPIO_INPUT)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/fleex/led.c b/board/fleex/led.c
deleted file mode 100644
index 4d89f657cd..0000000000
--- a/board/fleex/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Fleex
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 10;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Fleex: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_PWR_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_CHG_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/fleex/usb_pd_policy.c b/board/fleex/usb_pd_policy.c
deleted file mode 100644
index 82922f9a4d..0000000000
--- a/board/fleex/usb_pd_policy.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-/* TODO(b/78638238): Remove file if still unused after DVT */
diff --git a/board/fleex/vif_override.xml b/board/fleex/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/fleex/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/fluffy/board.c b/board/fluffy/board.c
deleted file mode 100644
index a4de29a160..0000000000
--- a/board/fluffy/board.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fluffy configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "usb_descriptor.h"
-#include "registers.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Fluffy"),
-	/* This gets filled in at runtime. */
-	[USB_STR_SERIALNO]     = USB_STRING_DESC(""),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Fluffy Shell"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Sensing the VBUS voltage at the DUT side.  Converted to mV. */
-	[ADC_PPVAR_VBUS_DUT] = {
-		.name = "PPVAR_VBUS_DUT",
-		.factor_mul = 3300,
-		.factor_div = 4096,
-		.shift = 0,
-		.channel = STM32_AIN(0),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = 1,
-		.kbps = 400,
-		.scl = GPIO_I2C_SCL,
-		.sda = GPIO_I2C_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-static enum gpio_signal enabled_port = GPIO_EN_C0;
-static uint8_t output_en;
-
-static void print_port_status(void)
-{
-	if (!output_en)
-		CPRINTS("No ports enabled. zZZ");
-	else
-		CPRINTS("Port %d is ON", enabled_port - GPIO_EN_C0);
-
-	CPRINTS("CC Flip: %s", gpio_get_level(GPIO_EN_CC_FLIP) ? "YES" : "NO");
-	CPRINTS("USB MUX: %s", gpio_get_level(GPIO_EN_USB_MUX2) ? "ON" : "OFF");
-}
-
-static int command_cc_flip(int argc, char *argv[])
-{
-	int enable;
-
-	if (argc != 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!parse_bool(argv[1], &enable))
-		return EC_ERROR_INVAL;
-
-	if (output_en) {
-		gpio_set_level(enabled_port, 0);
-		gpio_set_level(GPIO_EN_USB_MUX2, 0);
-		/* Wait long enough for CC to discharge. */
-		usleep(500 * MSEC);
-	}
-
-	gpio_set_level(GPIO_EN_CC_FLIP, enable);
-	/* Allow some time for new CC configuration to settle. */
-	usleep(500 * MSEC);
-
-	if (output_en) {
-		gpio_set_level(enabled_port, 1);
-		gpio_set_level(GPIO_EN_USB_MUX2, 1);
-	}
-
-	print_port_status();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip,
-			"<enable/disable>",
-			"enable or disable flipping CC orientation");
-/*
- * Support tca6416 I2C ioexpander.
- */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-#define I2C_PORT_MASTER		1
-
-static void i2c_expander_init(void)
-{
-	gpio_set_level(GPIO_XP_RESET_L, 1);
-
-	/*
-	 * Setup P00, P02, P04, P10, and P12 on the I/O expander as an output.
-	 */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_A, 0xea);
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_B, 0xfa);
-}
-DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C+1);
-
-/* Write to a GPIO register on the tca6416 I2C ioexpander. */
-static void write_ioexpander(int bank, int gpio, int reg, int val)
-{
-	int tmp;
-
-	/* Read output port register */
-	i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		  reg + bank, &tmp);
-	if (val)
-		tmp |= BIT(gpio);
-	else
-		tmp &= ~BIT(gpio);
-	/* Write back modified output port register */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   reg + bank, tmp);
-}
-
-enum led_ch {
-	LED_5V = 0,
-	LED_9V,
-	LED_12V,
-	LED_15V,
-	LED_20V,
-	LED_COUNT,
-};
-
-static void set_led(enum led_ch led, int enable)
-{
-	int bank;
-	int gpio;
-
-	switch (led) {
-	case LED_5V:
-		bank = 0;
-		gpio = 0;
-		break;
-
-	case LED_9V:
-		bank = 0;
-		gpio = 2;
-		break;
-
-	case LED_12V:
-		bank = 0;
-		gpio = 4;
-		break;
-
-	case LED_15V:
-		bank = 1;
-		gpio = 0;
-		break;
-
-	case LED_20V:
-		bank = 1;
-		gpio = 2;
-		break;
-
-	default:
-		return;
-	}
-
-	/*
-	 * Setup the LED as an output if enabled, otherwise as an input to keep
-	 * the LEDs off.
-	 */
-	write_ioexpander(bank, gpio, GPIOX_DIR_PORT_A, !enable);
-
-	/* The LEDs are active low. */
-	if (enable)
-		write_ioexpander(bank, gpio, GPIOX_OUT_PORT_A, 0);
-}
-
-void show_output_voltage_on_leds(void);
-DECLARE_DEFERRED(show_output_voltage_on_leds);
-
-static void board_init(void)
-{
-	/* Do a sweeping LED dance. */
-	for (enum led_ch led = 0; led < LED_COUNT; led++) {
-		set_led(led, 1);
-		msleep(100);
-	}
-
-	msleep(500);
-
-	for (enum led_ch led = 0; led < LED_COUNT; led++)
-		set_led(led, 0);
-
-	show_output_voltage_on_leds();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-
-enum usb_mux {
-	USB_MUX0 = 0,
-	USB_MUX1,
-	USB_MUX2,
-	USB_MUX_COUNT,
-};
-
-static void set_mux(enum usb_mux mux, uint8_t val)
-{
-	enum gpio_signal c0;
-	enum gpio_signal c1;
-	enum gpio_signal c2;
-
-	switch (mux) {
-	case USB_MUX0:
-		c0 = GPIO_USB_MUX0_C0;
-		c1 = GPIO_USB_MUX0_C1;
-		c2 = GPIO_USB_MUX0_C2;
-		break;
-
-	case USB_MUX1:
-		c0 = GPIO_USB_MUX1_C0;
-		c1 = GPIO_USB_MUX1_C1;
-		c2 = GPIO_USB_MUX1_C2;
-		break;
-
-	case USB_MUX2:
-		c0 = GPIO_USB_MUX2_C0;
-		c1 = GPIO_USB_MUX2_C1;
-		c2 = GPIO_USB_MUX2_C2;
-		break;
-
-	default:
-		break;
-	}
-
-	val &= 0x7;
-
-	gpio_set_level(c0, val & BIT(0));
-	gpio_set_level(c1, val & BIT(1));
-	gpio_set_level(c2, val & BIT(2));
-}
-
-/* This function assumes only 1 port works at a time. */
-static int command_portctl(int argc, char **argv)
-{
-	int port;
-	int enable;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if ((port < 0) || (port > 19) || !parse_bool(argv[2], &enable))
-		return EC_ERROR_INVAL;
-
-	gpio_set_level(GPIO_EN_USB_MUX2, 0);
-
-	/*
-	 * For each port, we must configure the USB 2.0 muxes and make sure that
-	 * the power enables are configured as desired.
-	 */
-
-	gpio_set_level(enabled_port, 0);
-	if (enabled_port != GPIO_EN_C0 + port)
-		CPRINTS("Port %d: disabled", enabled_port-GPIO_EN_C0);
-
-	/* Allow time for an "unplug" to allow VBUS and CC to fall. */
-	usleep(1 * SECOND);
-
-	/*
-	 * The USB 2.0 lines are arranged using 3x 8:1 muxes.  Ports 0-7 are
-	 * handled by the first mux, ports 8-15 are handled by the 2nd mux, then
-	 * the outputs of those muxes are fed into the third mux along with
-	 * ports 16-19.  The schematic contains the truth table.
-	 */
-	if (enable) {
-		enabled_port = GPIO_EN_C0 + port;
-		gpio_set_level(enabled_port, 1);
-
-		if (port < 8) {
-			set_mux(USB_MUX0, 7-port);
-			set_mux(USB_MUX2, 3);
-		} else if (port < 16) {
-			if (port < 14)
-				set_mux(USB_MUX1, 5-(port-8));
-			else
-				set_mux(USB_MUX1, 7-(port-14));
-
-			set_mux(USB_MUX2, 1);
-		} else {
-			set_mux(USB_MUX2, 7-(port-16));
-		}
-
-		gpio_set_level(GPIO_EN_USB_MUX2, 1);
-		output_en = 1;
-	} else {
-		gpio_set_level(enabled_port, 0);
-		output_en = 0;
-	}
-
-	print_port_status();
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(portctl, command_portctl,
-			"<port# 0-19> <enable/disable>",
-			"enable or disable a port");
-
-static int command_status(int argc, char **argv)
-{
-	int vbus_mv = adc_read_channel(ADC_PPVAR_VBUS_DUT);
-
-	CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv*7692/1000,
-		vbus_mv);
-	print_port_status();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(status, command_status, NULL, "show current status");
-
-/*
- * According to the USB PD Spec, the minimum voltage for a fixed source is 95%
- * of the new source voltage with an additional 500mV drop.
- *
- * vSrcNew |    min   | vSrcNew(min) + vSrcValid
- *     5V  |   4.75V  | 4.25V  | 553mV
- *     9V  |   8.55V  | 8.05V  | 1047mV
- *    12V  |  11.4V   | 10.9V  | 1417mV
- *    15V  |  14.25V  | 13.75V | 1788mV
- *    20V  |  19V     | 18.5V  | 2405mV
- *
- * With the resistor divider that fluffy has, the ADC is only seeing 0.13 of the
- * actual voltage.
- */
-void show_output_voltage_on_leds(void)
-{
-	int read = adc_read_channel(ADC_PPVAR_VBUS_DUT);
-	uint32_t vbus_mv = (uint32_t)read;
-	static int prev_vbus_mv;
-	int i;
-	int act;
-	enum led_ch max_on_exclusive = LED_5V;
-
-	if (read != ADC_READ_ERROR) {
-		if (vbus_mv >= 2405)
-			max_on_exclusive = LED_COUNT;
-		else if (vbus_mv >= 1788)
-			max_on_exclusive = LED_20V;
-		else if (vbus_mv >= 1417)
-			max_on_exclusive = LED_15V;
-		else if (vbus_mv >= 1047)
-			max_on_exclusive = LED_12V;
-		else if (vbus_mv >= 553)
-			max_on_exclusive = LED_9V;
-
-		for (i = 0; i < LED_COUNT; i++)
-			set_led(i, i < max_on_exclusive);
-
-		act = (vbus_mv * 76667) / 10000;
-		if ((vbus_mv > prev_vbus_mv+2) || (vbus_mv < prev_vbus_mv-2)) {
-			CPRINTS("PPVAR_VBUS_DUT: %d mV (raw: %d)", act,
-				vbus_mv);
-			prev_vbus_mv = vbus_mv;
-		}
-	}
-
-	/*
-	 * The reason we reschedule this ourselves as opposed to declaring it as
-	 * a hook with a HOOK_TICK period is to allow the LED sweep sequence
-	 * when the board boots up.
-	 */
-	hook_call_deferred(&show_output_voltage_on_leds_data,
-			   500 * MSEC);
-}
diff --git a/board/fluffy/board.h b/board/fluffy/board.h
deleted file mode 100644
index 75e9843b83..0000000000
--- a/board/fluffy/board.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fluffy configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* This is not an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_PID 0x503b
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_COUNT		1
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_COUNT		2
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-
-#define CONFIG_ADC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_COUNT
-};
-
-enum adc_channel {
-	ADC_PPVAR_VBUS_DUT,
-	ADC_CH_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/fluffy/build.mk b/board/fluffy/build.mk
deleted file mode 100644
index b6761a4692..0000000000
--- a/board/fluffy/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072CBU6TR
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE_arm,\
-	$(CROSS_COMPILE_coreboot_sdk_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
-board-y=board.o
diff --git a/board/fluffy/ec.tasklist b/board/fluffy/ec.tasklist
deleted file mode 100644
index c732944a23..0000000000
--- a/board/fluffy/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/fluffy/gpio.inc b/board/fluffy/gpio.inc
deleted file mode 100644
index 4c802554f9..0000000000
--- a/board/fluffy/gpio.inc
+++ /dev/null
@@ -1,60 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Misc */
-GPIO(XP_RESET_L,         PIN(A, 10), GPIO_OUT_LOW)
-GPIO(EN_CC_FLIP,         PIN(A, 4),  GPIO_OUT_LOW)
-GPIO(ADC_PPVAR_VBUS_DUT, PIN(A, 0),  GPIO_ANALOG)
-
-/* Port Enables */
-GPIO(EN_C0,		PIN(B, 0),  GPIO_OUT_LOW)
-GPIO(EN_C1,		PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(EN_C2,		PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(EN_C3,		PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(EN_C4,		PIN(B, 4),  GPIO_OUT_LOW)
-GPIO(EN_C5,		PIN(B, 5),  GPIO_OUT_LOW)
-GPIO(EN_C6,		PIN(B, 6),  GPIO_OUT_LOW)
-GPIO(EN_C7,		PIN(B, 7),  GPIO_OUT_LOW)
-GPIO(EN_C8,		PIN(B, 8),  GPIO_OUT_LOW)
-GPIO(EN_C9,		PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(EN_C10,		PIN(B, 10), GPIO_OUT_LOW)
-GPIO(EN_C11,		PIN(B, 11), GPIO_OUT_LOW)
-GPIO(EN_C12,		PIN(B, 12), GPIO_OUT_LOW)
-GPIO(EN_C13,		PIN(A, 8),  GPIO_OUT_LOW)
-GPIO(EN_C14,		PIN(A, 9),  GPIO_OUT_LOW)
-GPIO(EN_C15,		PIN(B, 15), GPIO_OUT_LOW)
-GPIO(EN_C16,		PIN(C, 13), GPIO_OUT_LOW)
-GPIO(EN_C17,		PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EN_C18,		PIN(C, 15), GPIO_OUT_LOW)
-GPIO(EN_C19,		PIN(F, 0),  GPIO_OUT_LOW)
-
-/* I2C Port for I/O expander */
-GPIO(I2C_SCL,           PIN(B, 13), GPIO_INPUT)
-GPIO(I2C_SDA,           PIN(B, 14), GPIO_INPUT)
-
-/* USB 2.0 Muxes */
-GPIO(USB_MUX0_C0,	PIN(A, 1),  GPIO_OUT_LOW)
-GPIO(USB_MUX0_C1,	PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(USB_MUX0_C2,	PIN(A, 3),  GPIO_OUT_LOW)
-
-GPIO(USB_MUX1_C0,	PIN(A, 5),  GPIO_OUT_LOW)
-GPIO(USB_MUX1_C1,	PIN(A, 6),  GPIO_OUT_LOW)
-GPIO(USB_MUX1_C2,	PIN(A, 7),  GPIO_OUT_LOW)
-
-GPIO(EN_USB_MUX2,	PIN(A, 13), GPIO_OUT_LOW)
-GPIO(USB_MUX2_C0,	PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_MUX2_C1,	PIN(A, 15), GPIO_OUT_LOW)
-GPIO(USB_MUX2_C2,	PIN(F, 1),  GPIO_OUT_LOW)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C, GPIO_ODR_HIGH) /* PB13/14 I2C2 */
diff --git a/board/foob/battery.c b/board/foob/battery.c
deleted file mode 100644
index 01a6654920..0000000000
--- a/board/foob/battery.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all phaser battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* SMP 5B10Q13163 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC 5B10Q13162  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 181,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* GF Battery Information */
-	[BATTERY_GF] = {
-		.fuel_gauge = {
-			.manuf_name = "GF",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 200,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* GuoGuang 50Wh/38Wh Battery Information */
-	[BATTERY_AEC] = {
-		.fuel_gauge = {
-			.manuf_name = "AEC",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 200,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/foob/board.c b/board/foob/board.c
deleted file mode 100644
index 3e7725ac2e..0000000000
--- a/board/foob/board.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Phaser board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "util.h"
-#include "battery_smart.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		/* We only use 2g because its resolution is only 8-bits */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &standard_rot_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	return sku_id == 9 || sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return board_is_convertible();
-}
-
-/* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
-/* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
-/* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_BATTERY_MODE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	rv = sb_read(SB_OPTIONALMFG_FUNCTION2, &val);
-	if (rv)
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_OPTIONALMFG_FUNCTION2, val);
-}
-
-/* Called on AP S3/S0ix -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Normal charge current */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3/S0ix transition */
-static void board_chipset_suspend(void)
-{
-	/* Quick charge current */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
diff --git a/board/foob/board.h b/board/foob/board.h
deleted file mode 100644
index c20c1ad33b..0000000000
--- a/board/foob/board.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Phaser board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_LED_COMMON
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_PANASONIC,
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_GF,
-	BATTERY_AEC,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/foob/build.mk b/board/foob/build.mk
deleted file mode 100644
index 137e208b53..0000000000
--- a/board/foob/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/foob/ec.tasklist b/board/foob/ec.tasklist
deleted file mode 100644
index 6eac78a042..0000000000
--- a/board/foob/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/foob/gpio.inc b/board/foob/gpio.inc
deleted file mode 100644
index ad6773a211..0000000000
--- a/board/foob/gpio.inc
+++ /dev/null
@@ -1,199 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,  PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,    PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	    PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_RED_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_GREEN_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(PWR_LED_WHITE_L,	 PIN(D, 7), GPIO_OUT_HIGH)	/* LED_3_L */
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,           PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,           PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,           PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Camera */
-GPIO(EC_GPIO_03,	 PIN(0, 3), GPIO_INPUT)		/* TP only */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	 PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL,	PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Unused pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)         /* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)         /* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/foob/led.c b/board/foob/led.c
deleted file mode 100644
index c08203ccda..0000000000
--- a/board/foob/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Phaser
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/foob/vif_override.xml b/board/foob/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/foob/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/fusb307bgevb/board.c b/board/fusb307bgevb/board.c
deleted file mode 100644
index 41b12d5a82..0000000000
--- a/board/fusb307bgevb/board.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* FUSB307BGEVB configuration */
-
-#include "common.h"
-#include "ec_version.h"
-#include "fusb307.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lcd.h"
-#include "printf.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_gpio.h"
-#include "usb-stream.h"
-#include "usb_common.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0);
-}
-
-/******************************************************************************
- * Handle button presses. Press BUTTON REFRESH to refresh pdos shown on lcd.
- * Press BUTTON DOWN to select pdo. Prss BUTTON ENTER to confirm selection.
- */
-static int count;
-
-static void button_enter_event_deferred(void)
-{
-	uint32_t ma, mv, unused;
-
-	CPRINTS("Button enter event");
-
-	if (count >= 0 && count < pd_get_src_cap_cnt(0)) {
-		pd_extract_pdo_power(pd_get_src_caps(0)[count], &ma, &mv,
-				     &unused);
-		pd_request_source_voltage(0, mv);
-	} else {
-		CPRINTS("ERROR: button counter weird value.");
-		return;
-	}
-}
-DECLARE_DEFERRED(button_enter_event_deferred);
-
-void button_enter_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&button_enter_event_deferred_data, 100 * MSEC);
-}
-
-static void button_refresh_event_deferred(void)
-{
-	int i;
-	uint32_t ma, mv, unused;
-	char c[20];
-
-	CPRINTS("Button refresh event");
-	count = 0;
-
-	/* Display supply voltage on first page. */
-	lcd_clear();
-	for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
-		pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused);
-		snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-		lcd_set_cursor(0, i);
-		lcd_print_string(c);
-	}
-
-	/* Display selector */
-	lcd_set_cursor(19, 0);
-	lcd_print_string("V");
-}
-DECLARE_DEFERRED(button_refresh_event_deferred);
-
-void button_refresh_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&button_refresh_event_deferred_data, 100 * MSEC);
-}
-
-static void button_down_event_deferred(void)
-{
-	int i;
-	uint32_t ma, mv, unused;
-	char c[20];
-
-	CPRINTS("Button down event");
-	if (pd_get_src_cap_cnt(0) > 0)
-		count = (count + 1) % pd_get_src_cap_cnt(0);
-	else {
-		/* Hasn't plug in adaptor yet, do nothing. */
-		return;
-	}
-
-	/* Display all supply voltage, count will never be greater than 7 */
-	if (count == 0) {
-		lcd_clear();
-		for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
-			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
-					     &unused);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i);
-			lcd_print_string(c);
-		}
-	}
-	if (count == 4) {
-		lcd_clear();
-		for (i = 4; i < pd_get_src_cap_cnt(0); i++) {
-			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
-					     &unused);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i - 4);
-			lcd_print_string(c);
-		}
-	}
-
-	/* Clear last col on LCD */
-	for (i = 0; i < 4; i++) {
-		lcd_set_cursor(19, i);
-		lcd_print_string(" ");
-	}
-	/* Display selector */
-	lcd_set_cursor(19, count % 4);
-	lcd_print_string("V");
-}
-DECLARE_DEFERRED(button_down_event_deferred);
-
-void button_down_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&button_down_event_deferred_data, 100 * MSEC);
-}
-
-/******************************************************************************
- * Build GPIO tables and expose a subset of the GPIOs over USB.
- */
-#include "gpio_list.h"
-
-static enum gpio_signal const usb_gpio_list[] = {
-	GPIO_USER_BUTTON_ENTER,
-	GPIO_USER_BUTTON_REFRESH,
-	GPIO_USER_BUTTON_DOWN,
-};
-
-/*
- * This instantiates struct usb_gpio_config const usb_gpio, plus several other
- * variables, all named something beginning with usb_gpio_
- */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
-
-/******************************************************************************
- * Setup USART1 as a loopback device, it just echo's back anything sent to it.
- */
-static struct usart_config const loopback_usart;
-
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
-
-static struct usart_rx_dma const loopback_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH3, 8);
-
-static struct usart_tx_dma const loopback_tx_dma =
-	USART_TX_DMA(STM32_DMAC_CH2, 16);
-
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
-
-/******************************************************************************
- * Forward USART4 as a simple USB serial interface.
- */
-static struct usart_config const forward_usart;
-struct usb_stream_config const forward_usb;
-
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
-
-static struct usart_tx_dma const forward_tx_dma =
-	USART_TX_DMA(STM32_DMAC_CH7, 16);
-
-static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("fusb307bgevb"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/******************************************************************************
- * I2C interface.
- */
-const struct i2c_port_t i2c_ports[] = {
-	{"tcpc", I2C_PORT_TCPC, 400 /* kHz */, GPIO_I2C2_SCL, GPIO_I2C2_SDA}
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************
- * PD
- */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC,
-			.addr_flags = FUSB307_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb307_tcpm_drv,
-	},
-};
-
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-void board_reset_pd_mcu(void)
-{
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* No battery, nothing to do */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	fusb307_power_supply_reset(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	return EC_SUCCESS;
-}
-
-int pd_board_checks(void)
-{
-	return EC_SUCCESS;
-}
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	/* Enable button interrupts */
-	gpio_enable_interrupt(GPIO_USER_BUTTON_ENTER);
-	gpio_enable_interrupt(GPIO_USER_BUTTON_REFRESH);
-	gpio_enable_interrupt(GPIO_USER_BUTTON_DOWN);
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	lcd_init(20, 4, 0);
-	lcd_set_cursor(0, 0);
-	lcd_print_string("USB-C");
-	lcd_set_cursor(0, 1);
-	lcd_print_string("Sink Advertiser");
-	queue_init(&loopback_queue);
-	queue_init(&usart_to_usb);
-	queue_init(&usb_to_usart);
-	usart_init(&loopback_usart);
-	usart_init(&forward_usart);
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h
deleted file mode 100644
index 3495f7125f..0000000000
--- a/board/fusb307bgevb/board.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fusb307bgevb configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Debug Congifuation */
-#define DEBUG_GET_CC
-#define DEBUG_ROLE_CTRL_UPDATES
-
-/* Enable USART1,3,4 and USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1
-#define CONFIG_STREAM_USART4
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* the UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x1234
-#define CONFIG_USB_CONSOLE
-
-/* USB Power Delivery configuration */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USBC_VCONN
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPM_FUSB307
-
-/* delay to turn on/off vconn */
-/* Define operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_VOLTAGE_MV 20000
-#define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-
-/* Degine board specific type-C power constants */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000  /* us */
-
-/* I2C master port connected to the TCPC */
-#define I2C_PORT_TCPC 1
-
-/* LCD Configuration */
-#define LCD_SLAVE_ADDR 0x27
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
-#define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
-#define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
-
-/* Enable control of GPIOs over USB */
-#define CONFIG_USB_GPIO
-
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_STREAM_NAME,
-	USB_STR_CONSOLE_NAME,
-
-	USB_STR_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/fusb307bgevb/build.mk b/board/fusb307bgevb/build.mk
deleted file mode 100644
index 1372562107..0000000000
--- a/board/fusb307bgevb/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o lcd.o
diff --git a/board/fusb307bgevb/ec.tasklist b/board/fusb307bgevb/ec.tasklist
deleted file mode 100644
index e25b8f7a68..0000000000
--- a/board/fusb307bgevb/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/fusb307bgevb/gpio.inc b/board/fusb307bgevb/gpio.inc
deleted file mode 100644
index 16a845576d..0000000000
--- a/board/fusb307bgevb/gpio.inc
+++ /dev/null
@@ -1,31 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(A, 8), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
-GPIO_INT(USER_BUTTON_ENTER, PIN(A, 0), GPIO_INT_FALLING, button_enter_event)
-GPIO_INT(USER_BUTTON_REFRESH, PIN(A, 1), GPIO_INT_FALLING, button_refresh_event)
-GPIO_INT(USER_BUTTON_DOWN, PIN(A, 2), GPIO_INT_FALLING, button_down_event)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C2_SCL,	PIN(B, 10),  GPIO_INPUT)
-GPIO(I2C2_SDA,	PIN(B, 11),  GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_I2C, GPIO_ODR_HIGH ) /* I2C MASTER: PB10/11 */
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA09/PA10 */
-ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART, 0)  /* USART2: PA14/PA15 */
-ALTERNATE(PIN_MASK(C, 0x0C00), 0, MODULE_USART, 0) /* USART4: PC10/PC11 */
diff --git a/board/fusb307bgevb/lcd.c b/board/fusb307bgevb/lcd.c
deleted file mode 100644
index 892888329e..0000000000
--- a/board/fusb307bgevb/lcd.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LCD driver for I2C LCD 2004.
- */
-
-#include "i2c.h"
-#include "lcd.h"
-#include "timer.h"
-
-struct lcd_state_info {
-	uint8_t addr;
-	uint8_t displayfunction;
-	uint8_t displaycontrol;
-	uint8_t backlightval;
-};
-
-static struct lcd_state_info state = {
-	.addr = LCD_SLAVE_ADDR,
-	.backlightval = LCD_BACKLIGHT,
-	.displayfunction = LCD_4BITMODE | LCD_1LINE | LCD_5X8DOTS,
-};
-
-/************ low level data pushing commands **********/
-/* write either command or data */
-static void expander_write(uint8_t data)
-{
-	i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00, data |
-		state.backlightval);
-}
-
-static void pulse_enable(uint8_t data)
-{
-	expander_write(data | LCD_EN);/* En high */
-	usleep(1);	/* enable pulse must be >450ns */
-
-	expander_write(data & ~LCD_EN);/* En low */
-	usleep(50);	/* commands need > 37us to settle */
-}
-
-static void write_4bits(uint8_t value)
-{
-	expander_write(value);
-	pulse_enable(value);
-}
-
-static void send(uint8_t value, uint8_t mode)
-{
-	uint8_t highnib = value & 0xf0;
-	uint8_t lownib = (value << 4) & 0xf0;
-
-	write_4bits(highnib | mode);
-	write_4bits(lownib | mode);
-}
-
-/*********** mid level commands, for sending data/cmds */
-static void command(uint8_t value)
-{
-	send(value, 0);
-}
-
-/********** high level commands, for the user! */
-void lcd_clear(void)
-{
-	command(LCD_CLEAR_DISPLAY);/* clear display, set cursor to zero */
-	usleep(2000);	/* this command takes a long time! */
-}
-
-void lcd_set_cursor(uint8_t col, uint8_t row)
-{
-	int row_offsets[] = { 0x00, 0x40, 0x14, 0x54 };
-
-	command(LCD_SET_DDRAMADDR | (col + row_offsets[row]));
-}
-
-void lcd_print_char(char data)
-{
-	send(data, LCD_RS);
-}
-
-void lcd_print_string(const char *str)
-{
-	while (*str)
-		lcd_print_char(*str++);
-}
-
-/* Turn the display on/off (quickly) */
-void lcd_disable_display(void)
-{
-	state.displaycontrol &= ~LCD_DISPLAY_ON;
-	command(LCD_DISPLAY_CONTROL | state.displaycontrol);
-}
-void lcd_enable_display(void)
-{
-	state.displaycontrol |= LCD_DISPLAY_ON;
-	command(LCD_DISPLAY_CONTROL | state.displaycontrol);
-}
-
-/* Turn the (optional) backlight off/on */
-void lcd_disable_backlight(void)
-{
-	state.backlightval = LCD_NO_BACKLIGHT;
-	expander_write(0);
-}
-
-void lcd_enable_backlight(void)
-{
-	state.backlightval = LCD_BACKLIGHT;
-	expander_write(0);
-}
-
-void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize)
-{
-	if (rows > 1)
-		state.displayfunction |= LCD_2LINE;
-
-	/* for some 1 line displays you can select a 10 pixel high font */
-	if ((dotsize != 0) && (rows == 1))
-		state.displayfunction |= LCD_5X10DOTS;
-
-	/* SEE PAGE 45/46 FOR INITIALIZATION SPECIFICATION!
-	 * according to datasheet, we need at least 40ms after power rises
-	 * above 2.7V before sending commands. Arduino can turn on way
-	 * before 4.5V so we'll wait 50
-	 */
-	usleep(50);
-
-	/* Now we pull both RS and R/W low to begin commands */
-	/* reset expanderand turn backlight off (Bit 8 =1) */
-	expander_write(state.backlightval);
-	usleep(1000);
-
-	/* put the LCD into 4 bit mode
-	 * this is according to the hitachi HD44780 datasheet
-	 * figure 24, pg 46
-	 * we start in 8bit mode, try to set 4 bit mode
-	 */
-	write_4bits(0x03 << 4);
-	usleep(4500); /* wait min 4.1ms */
-	/*second try */
-	write_4bits(0x03 << 4);
-	usleep(4500); /* wait min 4.1ms */
-	/* third go! */
-	write_4bits(0x03 << 4);
-	usleep(150);
-	/* finally, set to 4-bit interface */
-	write_4bits(0x02 << 4);
-
-	/* set # lines, font size, etc. */
-	command(LCD_FUNCTION_SET | state.displayfunction);
-
-	/* turn the display on with no cursor or blinking default */
-	state.displaycontrol = LCD_DISPLAY_ON | LCD_CURSOR_OFF | LCD_BLINK_OFF;
-	lcd_enable_display();
-
-	/* clear it off */
-	lcd_clear();
-
-	/* Initialize to default text direction (for roman languages)
-	 * and set the entry mode
-	 */
-	command(LCD_ENTRYMODE_SET | LCD_ENTRY_LEFT | LCD_ENTRY_SHIFT_DECREMENT);
-
-	lcd_set_cursor(0, 0);
-}
diff --git a/board/fusb307bgevb/lcd.h b/board/fusb307bgevb/lcd.h
deleted file mode 100644
index 21b0ee9ce9..0000000000
--- a/board/fusb307bgevb/lcd.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LCD driver for I2C LCD 2004.
- */
-
-#ifndef __CROS_EC_LCD_H
-#define __CROS_EC_LCD_H
-
-#include "common.h"
-
-/* commands */
-#define LCD_CLEAR_DISPLAY	BIT(0)
-#define LCD_RETURN_HOME		BIT(1)
-#define LCD_ENTRYMODE_SET	BIT(2)
-#define LCD_DISPLAY_CONTROL	BIT(3)
-#define LCD_CURSOR_SHIFT	BIT(4)
-#define LCD_FUNCTION_SET	BIT(5)
-#define LCD_SET_CGRAMADDR	BIT(6)
-#define LCD_SET_DDRAMADDR	BIT(7)
-
-/* flags for display entry mode */
-#define LCD_ENTRY_RIGHT			0x00
-#define LCD_ENTRY_LEFT			BIT(1)
-#define LCD_ENTRY_SHIFT_INCREMENT	BIT(0)
-#define LCD_ENTRY_SHIFT_DECREMENT	0x00
-
-/* flags for display on/off control */
-#define LCD_DISPLAY_ON	BIT(2)
-#define LCD_DISPLAY_OFF	0x00
-#define LCD_CURSOR_ON	BIT(1)
-#define LCD_CURSOR_OFF	0x00
-#define LCD_BLINK_ON	BIT(0)
-#define LCD_BLINK_OFF	0x00
-
-/* flags for display/cursor shift */
-#define LCD_DISPLAY_MOVE	BIT(3)
-#define LCD_CURSOR_MOVE		0x00
-#define LCD_MOVE_RIGHT		BIT(2)
-#define LCD_MOVE_LEFT		0x00
-
-/* flags for function set */
-#define LCD_8BITMODE	BIT(4)
-#define LCD_4BITMODE	0x00
-#define LCD_2LINE	BIT(3)
-#define LCD_1LINE	0x00
-#define LCD_5X10DOTS	BIT(2)
-#define LCD_5X8DOTS	0x00
-
-/* flags for backlight control */
-#define LCD_BACKLIGHT		BIT(3)
-#define LCD_NO_BACKLIGHT	0x00
-
-#define LCD_EN	BIT(2) /* Enable bit */
-#define LCD_RW	BIT(1) /* Read/Write bit */
-#define LCD_RS	BIT(0) /* Register select bit */
-
-void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize);
-void lcd_set_cursor(uint8_t col, uint8_t row);
-void lcd_set_char(char data);
-void lcd_print_string(const char *str);
-void lcd_clear(void);
-void lcd_enable_display(void);
-void lcd_disable_display(void);
-void lcd_enable_backlight(void);
-void lcd_disable_backlight(void);
-
-#endif /*__CROS_EC_LCD_H */
diff --git a/board/fusb307bgevb/vif_override.xml b/board/fusb307bgevb/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/fusb307bgevb/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/galtic/battery.c b/board/galtic/battery.c
deleted file mode 100644
index 765b2af926..0000000000
--- a/board/galtic/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all waddledee battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C140254] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXXE3KA",
-			.device_name = "C140254",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000C,
-				.disconnect_val = 0x000C,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8900, /* mV */
-			.voltage_normal		= 7970, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_C340184] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXXH3KD",
-			.device_name = "C340184",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000C,
-				.disconnect_val = 0x000C,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0004,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8900, /* mV */
-			.voltage_normal         = 7960, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C140254;
diff --git a/board/galtic/board.c b/board/galtic/board.c
deleted file mode 100644
index 2c3cb41d17..0000000000
--- a/board/galtic/board.c
+++ /dev/null
@@ -1,892 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
-
-static int board_tusb544_set(const struct usb_mux *me,
-		mux_state_t mux_state)
-{
-	int  rv = EC_SUCCESS;
-	enum tusb544_conf usb_mode = 0;
-	/* USB */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
-		}
-		/* USB without DP */
-		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
-		}
-	}
-	/* DP without USB */
-	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
-	}
-	/* Nothing enabled */
-	else
-		return EC_SUCCESS;
-	/* Write the retimer config byte */
-	if (usb_mode == USB_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x15);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x11);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB_DP_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1F);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB_DP) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1B);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == DP_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1E);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-	} else if (usb_mode == DP) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1A);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-	}
-
-	return rv;
-}
-
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_set,
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	},
-};
-
-static const struct ec_response_keybd_config galith_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-static const struct ec_response_keybd_config galtic_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_PRESENT)
-		return &galith_kb;
-	else
-		return &galtic_kb;
-}
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable Base Accel interrupt */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT) {
-		/* Disable scanning KSO13 and 14 if keypad isn't present. */
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-	} else {
-		/* Setting scan mask KSO11, KSO12, KSO13 and KSO14 */
-		keyscan_config.actual_key_mask[11] = 0xfe;
-		keyscan_config.actual_key_mask[12] = 0xff;
-		keyscan_config.actual_key_mask[13] = 0xff;
-		keyscan_config.actual_key_mask[14] = 0xff;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	raa489000_hibernate(CHARGER_PRIMARY, true);
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(CHARGER_SECONDARY, true);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-}
-
-int board_set_active_charge_port(int port)
-{
-		int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (port == i)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data  g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_bmi = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t bma253_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA255,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma2x2_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_bma253_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.default_range = 2, /* g */
-	/* We only use 2g because its resolution is only 8-bits */
-	.min_frequency = BMA255_ACCEL_MIN_FREQ,
-	.max_frequency = BMA255_ACCEL_MAX_FREQ,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t bmi160_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi160_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_bmi,
-	.default_range = 4,  /* g */
-	.min_frequency = BMI_ACCEL_MIN_FREQ,
-	.max_frequency = BMI_ACCEL_MAX_FREQ,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t bmi160_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi160_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_bmi,
-	.min_frequency = BMI_GYRO_MIN_FREQ,
-	.max_frequency = BMI_GYRO_MAX_FREQ,
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_icm426xx_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref_icm,
-		.default_range = 4,  /* g */
-		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_icm426xx_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref_icm,
-		.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-		.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI160)
-		bmi160_interrupt(signal);
-	else
-		icm426xx_interrupt(signal);
-}
-
-static void board_sensors_init(void)
-{
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA255) {
-		motion_sensors[LID_ACCEL] = bma253_lid_accel;
-		ccprints("LID_ACCEL is BMA253");
-	} else
-		ccprints("LID_ACCEL is KX022");
-
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BMI160) {
-		motion_sensors[BASE_ACCEL] = bmi160_base_accel;
-		motion_sensors[BASE_GYRO] = bmi160_base_gyro;
-		ccprints("BASE_ACCEL is BMI160");
-	} else
-		ccprints("BASE_ACCEL is ICM426XX");
-}
-DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Vcore",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(98),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-};
-const static struct ec_thermal_config thermal_vcore = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-};
-const static struct ec_thermal_config thermal_ambient = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-};
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_charger,
-	[TEMP_SENSOR_2] = thermal_vcore,
-	[TEMP_SENSOR_3] = thermal_ambient,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default. This cause Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
diff --git a/board/galtic/board.h b/board/galtic/board.h
deleted file mode 100644
index 1098281868..0000000000
--- a/board/galtic/board.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000	/* C0 and C1: Charger */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI_COMM_I2C
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel */
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM_COMM_I2C
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_KEYPAD
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_C140254,
-	BATTERY_C340184,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/galtic/build.mk b/board/galtic/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/galtic/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/galtic/cbi_ssfc.c b/board/galtic/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/galtic/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/galtic/cbi_ssfc.h b/board/galtic/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/galtic/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/galtic/ec.tasklist b/board/galtic/ec.tasklist
deleted file mode 100644
index 762325a825..0000000000
--- a/board/galtic/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/galtic/gpio.inc b/board/galtic/gpio.inc
deleted file mode 100644
index bd8787acb3..0000000000
--- a/board/galtic/gpio.inc
+++ /dev/null
@@ -1,145 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_R_ODL,                 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(LED_G_ODL,                 PIN(A, 2), GPIO_OUT_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		/* ADC15: TEMP_SENSOR_3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
diff --git a/board/galtic/led.c b/board/galtic/led.c
deleted file mode 100644
index ecd40dc973..0000000000
--- a/board/galtic/led.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	/* Battery error LED behavior as below:
-	 * S0: Blinking Amber LED, 1s on/ 1s off
-	 * S3/S5: following S3/S5 behavior
-	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
-	 */
-
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/galtic/usb_pd_policy.c b/board/galtic/usb_pd_policy.c
deleted file mode 100644
index dde6d5c318..0000000000
--- a/board/galtic/usb_pd_policy.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/galtic/vif_override.xml b/board/galtic/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/galtic/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/garg/battery.c b/board/garg/battery.c
deleted file mode 100644
index 046a9b2d56..0000000000
--- a/board/garg/battery.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all garg battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo SDI 916Q2286H battery information */
-	[BATTERY_SIMPLO_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI3320",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = TARGET_WITH_MARGIN(13050, 5),	/* mV */
-			.voltage_normal = 11460,
-			.voltage_min = 9000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 60,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo BYD 916Q2294H battery information */
-	[BATTERY_SIMPLO_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LP485780",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = TARGET_WITH_MARGIN(13200, 5),	/* mV */
-			.voltage_normal = 11550,
-			.voltage_min = 9000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo CA475778G 916QA141H battery information */
-	[BATTERY_SIMPLO_CA475778G] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-CA475778G",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13050,		/* mV */
-			.voltage_normal = 11430,
-			.voltage_min = 9000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SDI;
diff --git a/board/garg/board.c b/board/garg/board.c
deleted file mode 100644
index c5e4b4b83f..0000000000
--- a/board/garg/board.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Garg board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm426xx_base_accel = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_icm_ref,
-	 .default_range = 4,  /* g */
-	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_icm_ref,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int board_is_convertible(void)
-{
-	/*
-	 * Garg360: 37, 38, 39
-	 * Unprovisioned: 255
-	 */
-	return sku_id == 37 || sku_id == 38 || sku_id == 39 || sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		if (get_cbi_ssfc_sensor() == SSFC_SENSOR_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE GYRO is ICM426XX");
-		} else
-			ccprints("BASE GYRO is BMI160");
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-void sensor_interrupt(enum gpio_signal signal)
-{
-	switch (motion_sensors[BASE_ACCEL].chip) {
-	case MOTIONSENSE_CHIP_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case MOTIONSENSE_CHIP_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-/* Read CBI from i2c eeprom and initialize variables for board variants */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX)
-		return;
-	sku_id = val;
-	CPRINTSUSB("SKU: %d", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate_late(void)
-{
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	/* HDMI SKU has one USB PD port */
-	if (sku_id == 9 || sku_id == 19 || sku_id == 50 || sku_id == 52)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
diff --git a/board/garg/board.h b/board/garg/board.h
deleted file mode 100644
index 273601824c..0000000000
--- a/board/garg/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Garg board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Free up flash space */
-#define CONFIG_LTO
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LED_COMMON
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* 2nd Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* Motion Sense Task Events */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#ifndef __ASSEMBLER__
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SIMPLO_SDI,
-	BATTERY_SIMPLO_BYD,
-	BATTERY_SIMPLO_CA475778G,
-	BATTERY_TYPE_COUNT,
-};
-
-void sensor_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/garg/build.mk b/board/garg/build.mk
deleted file mode 100644
index 137e208b53..0000000000
--- a/board/garg/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/garg/ec.tasklist b/board/garg/ec.tasklist
deleted file mode 100644
index 6eac78a042..0000000000
--- a/board/garg/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/garg/gpio.inc b/board/garg/gpio.inc
deleted file mode 100644
index 995986d600..0000000000
--- a/board/garg/gpio.inc
+++ /dev/null
@@ -1,188 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT, 	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)            /* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,         PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, sensor_interrupt)
-
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L, 	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_ORANGE_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_BLUE_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(LED_3_L,		 PIN(D, 7), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		PIN(9, 4), GPIO_ODR_HIGH)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Unused Pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(WFCAM_VSYNC,	PIN(0, 3), GPIO_INPUT)
-GPIO(KB_BL_PWR_EN,	PIN(6, 2), GPIO_INPUT)
-GPIO(EC_GPIO80,		PIN(8, 0), GPIO_INPUT)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/garg/led.c b/board/garg/led.c
deleted file mode 100644
index 6e0306edd9..0000000000
--- a/board/garg/led.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Garg
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Garg: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/garg/vif_override.xml b/board/garg/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/garg/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/genesis/board.c b/board/genesis/board.c
deleted file mode 100644
index 6f397bf1ab..0000000000
--- a/board/genesis/board.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/ina3221.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_common.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-static uint8_t usbc_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1500)
-#define PWR_FRONT_LOW	(5*900)
-#define PWR_REAR	(5*1500)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (usbc_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"pse",     I2C_PORT_PSE,     400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CORE] = {
-		.name = "Core",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(84),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	/*
-	 * For board version < 2, the directly connected recovery
-	 * button is not available.
-	 */
-	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-int extpower_is_present(void)
-{
-	/* genesis: If the EC is running, then there is external power */
-	return 1;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	return 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-}
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-	} else {
-		delay = POWER_DELAY_MS * MSEC;
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A3_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
diff --git a/board/genesis/board.h b/board/genesis/board.h
deleted file mode 100644
index 14d1a8475d..0000000000
--- a/board/genesis/board.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-/* TODO: (b/143496253) re-enable CEC */
-/* #define CONFIG_CEC */
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 0
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are five ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_PSE		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
-
-/* Board specific handlers */
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/genesis/build.mk b/board/genesis/build.mk
deleted file mode 100644
index 2785133e11..0000000000
--- a/board/genesis/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-y+=led.o
-board-y+=pse.o
diff --git a/board/genesis/ec.tasklist b/board/genesis/ec.tasklist
deleted file mode 100644
index 3828142c55..0000000000
--- a/board/genesis/ec.tasklist
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/genesis/gpio.inc b/board/genesis/gpio.inc
deleted file mode 100644
index 6a905fdf04..0000000000
--- a/board/genesis/gpio.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/*
- * Directly connected recovery button (not available on some boards).
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP)
-
-/* Port power control interrupts */
-GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A3_LOW_PWR_OD,        PIN(5, 0), GPIO_ODR_LOW)
-GPIO(USB_A1_STATUS_L,          PIN(6, 1), GPIO_INPUT)
-GPIO(USB_A2_STATUS_L,          PIN(C, 7), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,          PIN(D, 2), GPIO_INPUT)
-
-/* USB type C */
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
-
-/* TPU */
-GPIO(PP3300_TPU_EN,            PIN(E, 4), GPIO_OUT_HIGH)
-
-/* PSE controller */
-GPIO(EC_PSE_PWM_INT,           PIN(B, 0), GPIO_INPUT)		/* PSE controller interrupt */
-GPIO(EC_RST_LTC4291_L,         PIN(9, 6), GPIO_OUT_HIGH)	/* PSE controller reset */
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-
-/* HDMI/CEC */
-GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
-GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_LTC_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_LTC_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                  /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* Unused pins */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(8, 0))						/* LED_BLUE_L */
-UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(9, 2))						/* K8  NC */
-UNUSED(PIN(9, 1))						/* L8  NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(C, 6))						/* B11 NC */
-UNUSED(PIN(E, 2))						/* B8  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(3, 2))						/* E5  NC */
-UNUSED(PIN(D, 6))						/* F6  NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(9, 3))						/* M11 NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/genesis/led.c b/board/genesis/led.c
deleted file mode 100644
index c562dff27e..0000000000
--- a/board/genesis/led.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		red = 1;
-		white = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec.
- */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task.
-	 */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_resume();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_suspend();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		led_shutdown();
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/genesis/pse.c b/board/genesis/pse.c
deleted file mode 100644
index 671288ccf5..0000000000
--- a/board/genesis/pse.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
- * controller.
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "string.h"
-#include "timer.h"
-#include "util.h"
-
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
-
-#define I2C_PSE_READ(reg, data) \
-	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define I2C_PSE_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static int pse_write_hpmd(int port, int val)
-{
-	switch (port) {
-	case 0:
-		return I2C_PSE_WRITE(HPMD1, val);
-	case 1:
-		return I2C_PSE_WRITE(HPMD2, val);
-	case 2:
-		return I2C_PSE_WRITE(HPMD3, val);
-	case 3:
-		return I2C_PSE_WRITE(HPMD4, val);
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-/*
- * Port 1: 100W
- * Port 2-4: 15W
- */
-static int pse_port_hpmd[4] = {
-	LTC4291_HPMD_MAX,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-};
-
-static int pse_port_enable(int port)
-{
-	/* Enable detection and classification */
-	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
-}
-
-static int pse_port_disable(int port)
-{
-	/* Request power off (this also disables detection/classification) */
-	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
-}
-
-static int pse_init_worker(void)
-{
-	timestamp_t deadline;
-	int err, id, devid, statpin, port;
-
-	/* Ignore errors -- may already be resetting */
-	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
-
-	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
-	while ((err = I2C_PSE_READ(ID, &id)) != 0) {
-		if (timestamp_expired(deadline, NULL))
-			return err;
-	}
-
-	err = I2C_PSE_READ(DEVID, &devid);
-	if (err != 0)
-		return err;
-
-	if (id != LTC4291_ID || devid != LTC4291_DEVID)
-		return EC_ERROR_INVAL;
-
-	err = I2C_PSE_READ(STATPIN, &statpin);
-	if (err != 0)
-		return err;
-
-	/*
-	 * We don't want to supply power until we've had a chance to set the
-	 * limits.
-	 */
-	if (statpin & LTC4291_FLD_STATPIN_AUTO)
-		CPRINTS("WARN: PSE reset in AUTO mode");
-
-	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
-	if (err != 0)
-		return err;
-
-	/* Set maximum power each port is allowed to allocate. */
-	for (port = 0; port < LTC4291_PORT_MAX; port++) {
-		err = pse_write_hpmd(port, pse_port_hpmd[port]);
-		if (err != 0)
-			return err;
-	}
-
-	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
-	if (err != 0)
-		return err;
-
-	return 0;
-}
-
-static void pse_init(void)
-{
-	int err;
-
-	err = pse_init_worker();
-	if (err != 0)
-		CPRINTS("PSE init failed: %d", err);
-	else
-		CPRINTS("PSE init done");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
-
-/* Also reset the PSE on a reboot to toggle the power. */
-DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
-
-static int command_pse(int argc, char **argv)
-{
-	int port;
-
-	/*
-	 *  TODO(b/156399232): endeavour: PSE controller reset by PLTRST
-	 *
-	 *  Initialization does not reliably work after reset because the device
-	 *  is held in reset by the AP. Running this command after boot finishes
-	 *  always succeeds. Remove once the reset signal changes.
-	 */
-	if (!strncmp(argv[1], "init", 4))
-		return pse_init_worker();
-
-	if (argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if (port < 0 || port >= LTC4291_PORT_MAX)
-		return EC_ERROR_PARAM1;
-
-	if (!strncmp(argv[2], "off", 3))
-		return pse_port_disable(port);
-	else if (!strncmp(argv[2], "on", 2))
-		return pse_port_enable(port);
-	else if (!strncmp(argv[2], "min", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
-	else if (!strncmp(argv[2], "max", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
-	else
-		return EC_ERROR_PARAM2;
-}
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
-			"Set PSE port power");
-
-static int ec_command_pse_status(int port, uint8_t *status)
-{
-	int detena, statpwr;
-	int err;
-
-	err = I2C_PSE_READ(DETENA, &detena);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_READ(STATPWR, &statpwr);
-	if (err != 0)
-		return err;
-
-	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_DISABLED;
-	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_ENABLED;
-	else
-		*status = EC_PSE_STATUS_POWERED;
-
-	return 0;
-}
-
-static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pse *p = args->params;
-	int err = 0;
-
-	if (p->port >= LTC4291_PORT_MAX)
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->cmd) {
-	case EC_PSE_STATUS: {
-		struct ec_response_pse_status *r = args->response;
-
-		args->response_size = sizeof(*r);
-		err = ec_command_pse_status(p->port, &r->status);
-		break;
-	}
-	case EC_PSE_ENABLE:
-		err = pse_port_enable(p->port);
-		break;
-	case EC_PSE_DISABLE:
-		err = pse_port_disable(p->port);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (err)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/board/gimble/battery.c b/board/gimble/battery.c
deleted file mode 100644
index 235503a6f1..0000000000
--- a/board/gimble/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Brya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 996QA193H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Cosmx CA407792G Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/gimble/board.c b/board/gimble/board.c
deleted file mode 100644
index 6483d8ca6d..0000000000
--- a/board/gimble/board.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/charger/bq25710.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accel_bma2x2_public.h"
-#include "driver/accel_bma422.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-__override void board_cbi_init(void)
-{
-	config_usb_db_type();
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-
-	/* TODO(b/190783131)
-	 * Need to implement specific keyboard backlight control method.
-	 */
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-
-	/* TODO(b/190783131)
-	 * Need to implement specific keyboard backlight control method.
-	 */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO(b/181508008): tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-
-	batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
-
-static void board_init(void)
-{
-	/* The PPVAR_SYS must same as battery voltage(3 cells * 4.4V) */
-	if (extpower_is_present() && battery_hw_present()) {
-		bq25710_set_min_system_voltage(CHARGER_SOLO, 9200);
-	} else {
-		bq25710_set_min_system_voltage(CHARGER_SOLO, 13200);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, board_init, HOOK_PRIO_DEFAULT);
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Follow OEM request to limit the input current to
-	 * 90% negotiated limit.
-	 */
-	charge_ma = charge_ma * 90 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
-}
diff --git a/board/gimble/board.h b/board/gimble/board.h
deleted file mode 100644
index 9b01e09ad3..0000000000
--- a/board/gimble/board.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* Sensors */
-/* BMA253 accelerometer in lid */
-#define CONFIG_ACCEL_BMA255
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* BMA422 accelerometer in lid */
-#define CONFIG_ACCEL_BMA4XX
-
-#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel/gyro */
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* Lid accel */
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		1
-
-#define CONFIG_USB_PD_TCPM_PS8815
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* measure and check these values on gimble */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-/* define this to aviod error on CONFIG_ACCELGYRO_BMI_COMM_I2C */
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/* Disabling Thunderbolt-compatible mode */
-#undef CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#undef CONFIG_USB_PD_USB4
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_FANS FAN_CH_COUNT
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/*
- * TODO(b/181271666): no fan control loop until sensors are tuned
- */
-/* Fan features */
-#define CONFIG_CUSTOM_FAN_CONTROL
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_FAN,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_FAN,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED3,			/* PWM1 (orange on DB) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (white on DB) */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gimble/build.mk b/board/gimble/build.mk
deleted file mode 100644
index c43f37b4dd..0000000000
--- a/board/gimble/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brya board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=thermal.o
-board-y+=usbc_config.o
diff --git a/board/gimble/charger.c b/board/gimble/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/gimble/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/gimble/ec.tasklist b/board/gimble/ec.tasklist
deleted file mode 100644
index 290c17c748..0000000000
--- a/board/gimble/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/gimble/fans.c b/board/gimble/fans.c
deleted file mode 100644
index d966056331..0000000000
--- a/board/gimble/fans.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/180681346): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/gimble/fw_config.c b/board/gimble/fw_config.c
deleted file mode 100644
index fb8acb635d..0000000000
--- a/board/gimble/fw_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union brya_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union brya_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Brya FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
-}
-
-union brya_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
diff --git a/board/gimble/fw_config.h b/board/gimble/fw_config.h
deleted file mode 100644
index 6e4eb3ef58..0000000000
--- a/board/gimble/fw_config.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Brya board.
- *
- * Source of truth is the project/brya/brya/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1,
-	DB_USB_ABSENT2 = 15
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union brya_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union brya_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/gimble/gpio.inc b/board/gimble/gpio.inc
deleted file mode 100644
index faec39af08..0000000000
--- a/board/gimble/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_LOCK,                     PIN(0, 4), GPIO_INPUT)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(E, 1), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(POWER_LED_GATE,		         PIN(B, 6), GPIO_OUT_LOW)	/* Power LED: White */
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
-UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
-UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
-UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
-UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
-UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
-UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
-UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
-UNUSED(PIN(A, 0))       /* F_CS0_L/GPIOA0 */
-UNUSED(PIN(9, 6))       /* F_DIO1/GPIO96 */
-UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0 */
-UNUSED(PIN(8, 1))       /* PECI DATA/GPIO81 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
diff --git a/board/gimble/i2c.c b/board/gimble/i2c.c
deleted file mode 100644
index ed763fffca..0000000000
--- a/board/gimble/i2c.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1
-		 * TODO(b/194264003) Need to check the signals with a scope
-		 * before raising to 1MHz.
-		 */
-		/* I2C1 */
-		.name = "tcpc0",
-		.port = I2C_PORT_USB_C0_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0",
-		.port = I2C_PORT_USB_C0_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
-	},
-	{
-		/* I2C4
-		 * TODO(b/194264003) Need to check the signals with a scope
-		 * before raising to 1MHz.
-		 */
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/gimble/keyboard.c b/board/gimble/keyboard.c
deleted file mode 100644
index cec70e3d97..0000000000
--- a/board/gimble/keyboard.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config gimble_kb = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
-		TK_PLAY_PAUSE,		/* T9 */
-		TK_MICMUTE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &gimble_kb;
-}
diff --git a/board/gimble/led.c b/board/gimble/led.c
deleted file mode 100644
index 924aa53aff..0000000000
--- a/board/gimble/led.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "pwm.h"
-#include "util.h"
-
-#define BAT_LED_ON_LVL 100
-#define BAT_LED_OFF_LVL 0
-
-#define PWR_LED_ON_LVL 1
-#define PWR_LED_OFF_LVL 0
-
-#define LED_SIDESEL_MB_PORT 0
-#define LED_SIDESEL_DB_PORT 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {
-					{EC_LED_COLOR_WHITE, 0.5 * LED_ONE_SEC},
-					{LED_OFF,            0.5 * LED_ONE_SEC}
-	},
-	[STATE_FACTORY_TEST]         = {
-					{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           =  {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   =  {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {
-		{LED_OFF,             LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	int port;
-
-	/* There are four battery leds, LED1/LED2 are on MB side and
-	 * LED3/LED4 are on DB side. All leds are OFF by default.
-	 */
-	int led1_duty, led2_duty, led3_duty, led4_duty;
-
-	led1_duty = led2_duty = led3_duty = led4_duty = BAT_LED_OFF_LVL;
-
-	/* Check which port is the charging port,
-	 * and turn on the corresponding led.
-	 */
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case LED_SIDESEL_MB_PORT:
-		switch (color) {
-		case EC_LED_COLOR_AMBER:
-			led1_duty = BAT_LED_ON_LVL;
-			break;
-		case EC_LED_COLOR_WHITE:
-			led2_duty = BAT_LED_ON_LVL;
-			break;
-		default: /* LED_OFF and other unsupported colors */
-			break;
-		}
-		break;
-	case LED_SIDESEL_DB_PORT:
-		switch (color) {
-		case EC_LED_COLOR_AMBER:
-			led3_duty = BAT_LED_ON_LVL;
-			break;
-		case EC_LED_COLOR_WHITE:
-			led4_duty = BAT_LED_ON_LVL;
-			break;
-		default: /* LED_OFF and other unsupported colors */
-			break;
-		}
-		break;
-	default: /* Unknown charging port */
-		break;
-	}
-
-	pwm_set_duty(PWM_CH_LED1, led1_duty);
-	pwm_set_duty(PWM_CH_LED2, led2_duty);
-	pwm_set_duty(PWM_CH_LED3, led3_duty);
-	pwm_set_duty(PWM_CH_LED4, led4_duty);
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_POWER_LED_GATE, PWR_LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		led_auto_control(led_id, 0);
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/gimble/pwm.c b/board/gimble/pwm.c
deleted file mode 100644
index 73f63821e0..0000000000
--- a/board/gimble/pwm.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED2] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED3] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED1] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_LED4] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn off LED1 to LED4.
-	 * Turn on KB LED at 50%.
-	 */
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_set_duty(PWM_CH_LED1, 0);
-	pwm_enable(PWM_CH_LED2, 1);
-	pwm_set_duty(PWM_CH_LED2, 0);
-	pwm_enable(PWM_CH_LED3, 1);
-	pwm_set_duty(PWM_CH_LED3, 0);
-	pwm_enable(PWM_CH_LED4, 1);
-	pwm_set_duty(PWM_CH_LED4, 0);
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c
deleted file mode 100644
index 24c7215900..0000000000
--- a/board/gimble/sensors.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc_chip.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_bma2x2_public.h"
-#include "driver/accel_bma422.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_FAN] = {
-		.name = "TEMP_FAN",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* LSM6DSM private data */
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* BMA422 private data */
-static struct accelgyro_saved_data_t g_bma422_data;
-
-/* TODO(b/192477578): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref_id_1 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TODO(b/192477578): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref_id_1 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t bma422_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA422,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma4_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_bma422_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMA4_I2C_ADDR_SECONDARY,
-	.rot_standard_ref = &lid_standard_ref_id_1,
-	.min_frequency = BMA4_ACCEL_MIN_FREQ,
-	.max_frequency = BMA4_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, enough for laptop. */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t lsm6dsm_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_accel_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_EC_IMU_INT_R_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_id_1,
-	.default_range = 4,  /* g */
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t lsm6dsm_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_accel_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_EC_IMU_INT_R_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	.rot_standard_ref = &base_standard_ref_id_1,
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_board_id() >= 1)
-		lsm6dsm_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void update_sensor_array(void)
-{
-	if (get_board_id() >= 1) {
-		motion_sensors[LID_ACCEL] = bma422_lid_accel;
-		motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
-		motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro;
-		ccprints("LID ACCEL is BMA422");
-		ccprints("BASE IMU is LSM6DSM");
-	} else {
-		ccprints("LID ACCEL is BMA253");
-		ccprints("BASE IMU is BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_INIT, update_sensor_array, HOOK_PRIO_INIT_I2C);
-
-static void baseboard_sensors_init(void)
-{
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "Fan",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/194318801): confirm thermal limits setting for gimble
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/194318801): confirm thermal limits setting for gimble
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	/* TODO(b/194318801): confirm thermal limits setting for gimble */
-	[TEMP_SENSOR_2_FAN]	= thermal_inductor,
-	[TEMP_SENSOR_3_CHARGER]	= thermal_inductor,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gimble/thermal.c b/board/gimble/thermal.c
deleted file mode 100644
index 101c436886..0000000000
--- a/board/gimble/thermal.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-
-
-struct fan_step {
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-	/* Fan rpm */
-	uint16_t rpm[FAN_CH_COUNT];
-};
-/*
- * TODO(b/167931578) Only monitor sensor3 for now.
- * Will add more sensors support if needed.
- */
-static const struct fan_step fan_table[] = {
-	{
-		/* level 0 */
-		.on = {44, -1, -1},
-		.off = {0, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {46, -1, -1},
-		.off = {44, -1, -1},
-		.rpm = {3200},
-	},
-	{
-		/* level 2 */
-		.on = {50, -1, -1},
-		.off = {45, -1, -1},
-		.rpm = {3600},
-	},
-	{
-		/* level 3 */
-		.on = {54, -1, -1},
-		.off = {49, -1, -1},
-		.rpm = {4100},
-	},
-	{
-		/* level 4 */
-		.on = {58, -1, -1},
-		.off = {53, -1, -1},
-		.rpm = {4900},
-	},
-	{
-		/* level 5 */
-		.on = {60, -1, -1},
-		.off = {57, -1, -1},
-		.rpm = {5200},
-	},
-};
-const int num_fan_levels = ARRAY_SIZE(fan_table);
-
-int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
-{
-	/* current fan level */
-	static int current_level;
-	/* previous fan level */
-	static int prev_current_level;
-
-	/* previous sensor temperature */
-	static int prev_temp[TEMP_SENSOR_COUNT];
-	int i;
-	int new_rpm = 0;
-
-	/*
-	 * Compare the current and previous temperature, we have
-	 * the three paths :
-	 *  1. decreasing path. (check the release point)
-	 *  2. increasing path. (check the trigger point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
-		for (i = current_level; i > 0; i--) {
-			if (temp[temp_sensor] <
-				fan_table[i].off[temp_sensor])
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (temp[temp_sensor] >
-		prev_temp[temp_sensor]) {
-		for (i = current_level; i < num_fan_levels; i++) {
-			if (temp[temp_sensor] >
-				fan_table[i].on[temp_sensor])
-				current_level = i + 1;
-			else
-				break;
-		}
-	}
-	if (current_level < 0)
-		current_level = 0;
-
-	if (current_level != prev_current_level) {
-		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
-			prev_temp[temp_sensor]);
-		CPRINTS("current_level: %d", current_level);
-	}
-
-	prev_temp[temp_sensor] = temp[temp_sensor];
-	prev_current_level = current_level;
-
-	switch (fan) {
-	case FAN_CH_0:
-		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
-		break;
-	default:
-		break;
-	}
-	return new_rpm;
-}
-void board_override_fan_control(int fan, int *temp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_1_DDR_SOC));
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		/* Stop fan when enter S0ix */
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan), 0);
-	}
-}
diff --git a/board/gimble/usbc_config.c b/board/gimble/usbc_config.c
deleted file mode 100644
index 9f9f702364..0000000000
--- a/board/gimble/usbc_config.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		/* Compatible with Silicon Mitus SM536A0 */
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set
- * to the virtual_usb_mux_driver so the AP gets notified of mux changes
- * and updates the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-void config_usb_db_type(void)
-{
-	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
-
-	/*
-	 * TODO(b/180434685): implement multiple DB types
-	 */
-
-	CPRINTS("Configured USB DB type number is %d", db_type);
-}
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* Port0 */
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-	/* wait for chips to come up */
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/* Port1 */
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-static void board_tcpc_init(void)
-{
-	int i;
-
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i) {
-			ioex_config[i].flags &= ~IOEX_FLAGS_DISABLED;
-			ioex_init(i);
-		}
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/gimble/usbc_config.h b/board/gimble/usbc_config.h
deleted file mode 100644
index 87e601ee3e..0000000000
--- a/board/gimble/usbc_config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/gimble/vif_override.xml b/board/gimble/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/gimble/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/gingerbread/board.c b/board/gingerbread/board.c
deleted file mode 100644
index 6a2ae0c683..0000000000
--- a/board/gingerbread/board.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Gingerbread board-specific configuration */
-
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/stm32gx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/tusb1064.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "mp4245.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "usb_descriptor.h"
-#include "usb_pd_dp_ufp.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define QUICHE_PD_DEBUG_LVL 1
-
-#ifdef SECTION_IS_RW
-#define CROS_EC_SECTION "RW"
-#else
-#define CROS_EC_SECTION "RO"
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * C1 port on gingerbread does not have a PPC. However, C0 port does have a PPC
- * and therefore PPC related config options are defined. Defining a null driver
- * here so that functions from usbc_ppc.c will correctly dereference to a NULL
- * function pointer.
- */
-const struct ppc_drv board_ppc_null_drv = {};
-
-static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	PD_DRP_TOGGLE_ON,
-	PD_DRP_FORCE_SOURCE,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_HOST_USBC_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_HOST);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = -1;
-
-	switch (s) {
-	case GPIO_USBC_DP_MUX_ALERT_ODL:
-		port = USB_PD_PORT_DP;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void hpd_interrupt(enum gpio_signal signal)
-{
-	usb_pd_hpd_edge_event(signal);
-}
-
-static void board_pwr_btn_interrupt(enum gpio_signal signal)
-{
-	baseboard_power_button_evt(gpio_get_level(signal));
-}
-#endif /* SECTION_IS_RW */
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/*
- * Table GPIO signals control both power rails and reset lines to various chips
- * on the board. The order the signals are changed and the delay between GPIO
- * signals is driven by USB/MST hub power sequencing requirements.
- */
-const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_EN_PP3300_A,              1, 135},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1100_A,              1, 30},
-	{GPIO_EN_PP1000_A,              1, 20},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_LP_CTL_L,             1, 80},
-	{GPIO_MST_RST_L,                1, 41},
-	{GPIO_EC_HUB1_RESET_L,          1, 41},
-	{GPIO_EC_HUB2_RESET_L,          1, 33},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 1},
-};
-
-const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
-
-/*
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Gingerbread"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-#ifndef SECTION_IS_RW
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-	},
-};
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * TCPCs: 2 USBC/PD ports
- *     port 0 -> host port              -> STM32G4 UCPD
- *     port 1 -> user data/display port -> PS8805
- */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &stm32gx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_I2C3,
-			.addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = TUSB1064_I2C_ADDR0_FLAGS,
-		.driver = &tusb1064_usb_mux_driver,
-	},
-	[USB_PD_PORT_DP] = {
-		.usb_port = USB_PD_PORT_DP,
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_DP] = {
-		.drv = &board_ppc_null_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct hpd_to_pd_config_t hpd_config = {
-	.port = USB_PD_PORT_HOST,
-	.signal = GPIO_DDI_MST_IN_HPD,
-};
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_SYSTEM, "Resetting TCPCs...");
-	cflush();
-	/*
-	 * Reset all TCPCs.
-	 *   C0 -> ucpd (on chip TCPC)
-	 *   C1 -> PS8805 TCPC -> USBC_DP_PD_RST_L
-	 *   C2 -> PS8803 TCPC -> USBC_UF_RESET_L
-	 */
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 0);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 1);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-
-/* Power Delivery and charging functions */
-void board_enable_usbc_interrupts(void)
-{
-	board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-
-	/* Enable HPD interrupt */
-	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
-
-}
-
-/* Power Delivery and charging functions */
-void board_disable_usbc_interrupts(void)
-{
-	/* Disable PPC interrupts. */
-	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-
-	/* Disable TCPC interrupts. */
-	gpio_disable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-
-	/* Disable HPD interrupt */
-	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
-
-}
-
-void board_tcpc_init(void)
-{
-	board_reset_pd_mcu();
-
-	/* Enable board usbc interrupts */
-	board_enable_usbc_interrupts();
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
-{
-	return pd_dual_role_init[port];
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USB_PD_PORT_HOST)
-		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USBC_DP_MUX_ALERT_ODL) &&
-	    gpio_get_level(GPIO_USBC_DP_PD_RST_L))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO: b/ - check correct operation for honeybuns */
-}
-
-int dock_get_mf_preference(void)
-{
-	int rv;
-	uint32_t fw_config;
-	int mf = MF_OFF;
-
-	/*
-	 * MF (multi function) preferece is indicated by bit 0 of the fw_config
-	 * data field. If this data field does not exist, then default to 4 lane
-	 * mode.
-	 */
-	rv = cbi_get_fw_config(&fw_config);
-	if (!rv)
-		mf = CBI_FW_MF_PREFERENCE(fw_config);
-
-	return mf;
-}
-
-#endif /* SECTION_IS_RW */
-
-static void board_init(void)
-{
-#ifdef SECTION_IS_RW
-
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_debug_gpio_1_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_1, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_1_pulse);
-
-static void board_debug_gpio_2_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_2, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_2_pulse);
-
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
-{
-	switch (trigger) {
-	case TRIGGER_1:
-		gpio_set_level(GPIO_TRIGGER_1, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_1_pulse_data,
-					   pulse_usec);
-		break;
-	case TRIGGER_2:
-		gpio_set_level(GPIO_TRIGGER_2, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_2_pulse_data,
-					   pulse_usec);
-		break;
-	default:
-		CPRINTS("bad debug gpio selection");
-		break;
-	}
-}
diff --git a/board/gingerbread/board.h b/board/gingerbread/board.h
deleted file mode 100644
index cfc5bbf0a0..0000000000
--- a/board/gingerbread/board.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Gingerbread board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-/*
- * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
- * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
- * using option bytes WRP registers.
- */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
-
-
-#define CONFIG_WP_ACTIVE_HIGH
-
-/* Console */
-#define CONFIG_UART_CONSOLE 3
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART3_TX
-#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
-
-/* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP   1
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_MUX_TUSB1064
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define BOARD_C1_NO_PPC
-#define BOARD_C1_1A5_LIMIT
-
-#define CONFIG_USB_PID 0x5049
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-
-/* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
-/* Required symbolic I2C port names */
-#define I2C_PORT_MP4245 I2C_PORT_I2C3
-#define I2C_PORT_EEPROM I2C_PORT_I2C1
-#define MP4245_I2C_ADDR_FLAGS  MP4245_I2C_ADDR_0_FLAGS
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-#define GPIO_WP		GPIO_EC_WP_L
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "registers.h"
-
-#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
-#define GPIO_BPWR_DET GPIO_TP71
-#define GPIO_PWR_BUTTON_RED GPIO_EC_STATUS_LED1
-#define GPIO_PWR_BUTTON_GREEN GPIO_EC_STATUS_LED2
-
-#define BUTTON_PRESSED_LEVEL 0
-#define BUTTON_RELEASED_LEVEL 1
-
-#define GPIO_TRIGGER_1 GPIO_USB3_A1_CDP_EN
-#define GPIO_TRIGGER_2 GPIO_USB3_A2_CDP_EN
-
-enum  debug_gpio {
-	TRIGGER_1 = 0,
-	TRIGGER_2,
-};
-
-/*
- * Function used to control GPIO signals as a timing marker. This is intended to
- * be used for development/debugging purposes.
- *
- * @param trigger GPIO debug signal selection
- * @param level desired level of the debug gpio signal
- * @param pulse_usec pulse width if non-zero
- */
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
-
-/*
- * Function called in power on case to enable usbc related interrupts
- */
-void board_enable_usbc_interrupts(void);
-
-/*
- * Function called in power off case to disable usbc related interrupts
- */
-void board_disable_usbc_interrupts(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gingerbread/build.mk b/board/gingerbread/build.mk
deleted file mode 100644
index f994cc1434..0000000000
--- a/board/gingerbread/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=stm32
-# TODO(b/148493929): The chip family for honeybuns is STM32G4. The chip
-# variant is STM32G431x. Support for this chip is not yet in the Cros EC
-# codebase. Currently, using a variant of the F family so the project will
-# build properly.
-CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g473xc
-BASEBOARD:=honeybuns
-
-board-y=board.o
diff --git a/board/gingerbread/dev_key.pem b/board/gingerbread/dev_key.pem
deleted file mode 100644
index 7b1df5d805..0000000000
--- a/board/gingerbread/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG5AIBAAKCAYEA2hyGIDxIS/jWNh3Nhg7V4/5Ce8KT4CIb1XaLd0mR2gWCkYdZ
-iRWSjAjMsMCLSLM0gUDnFU5xJgbUdg1GeafXdPlRQojG2ztZ/z+JBNgQvsWtdJhR
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-gP3rVQqToekdsIuPGXGV/KEMEveyKBi9mveWzhEad6QnW/4rAoHBAM1TgJVVYCKl
-tmUf8XcC8+bNQ+dlqPdBQa3cAPFlQdRZUzDIYU+ZHa66GWUWb2uuD2hFCDDEpC1l
-Ke34tNROiruDfj9lfD6UmJv8vw/wPG3m52Qb5iWdA+B1512MK8p7KZg9YQJot/Yj
-B2rNxv1O+IjWPxxtUEVsFpx/XGoEemc85iS+icjNXvtOwyEGdNliRFiQtVkh2mtX
-7uKbkUAL2HKzxfnJ/LbWZwDlW45x/qDQtncp93sTcM3k8FVE+MtLbw==
------END RSA PRIVATE KEY-----
diff --git a/board/gingerbread/ec.tasklist b/board/gingerbread/ec.tasklist
deleted file mode 100644
index cc36bf5a74..0000000000
--- a/board/gingerbread/ec.tasklist
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/gingerbread/gpio.inc b/board/gingerbread/gpio.inc
deleted file mode 100644
index 5b7b3a9619..0000000000
--- a/board/gingerbread/gpio.inc
+++ /dev/null
@@ -1,99 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#ifdef SECTION_IS_RW
-GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(C, 1),       GPIO_INT_FALLING | GPIO_PULL_UP,  ppc_interrupt)
-GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(C, 12),       GPIO_INT_FALLING | GPIO_PULL_UP,   tcpc_alert_event)
-GPIO_INT(DDI_MST_IN_HPD,         PIN(C, 14),      GPIO_INT_BOTH, hpd_interrupt)
-GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
-#endif
-
-/* Power sequencing signals */
-GPIO(EN_AC_JACK,                    PIN(A, 1),  GPIO_OUT_LOW)
-GPIO(EN_BB,                         PIN(C, 0),  GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,                   PIN(C, 10), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,                   PIN(C, 2),  GPIO_OUT_LOW)
-GPIO(EN_PP1200_A,                   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EN_PP1100_A,                   PIN(C, 4),  GPIO_OUT_LOW)
-GPIO(EN_PP1000_A,                   PIN(C, 5),  GPIO_OUT_LOW)
-GPIO(EN_PP1050_A,                   PIN(C, 6),  GPIO_OUT_LOW)
-GPIO(EN_PP5000_HSPORT,              PIN(C, 7),  GPIO_OUT_LOW)
-GPIO(EC_STATUS_LED1,                PIN(A, 2),  GPIO_OUT_HIGH)
-GPIO(EC_STATUS_LED2,                PIN(B, 12), GPIO_OUT_HIGH)
-
-/* MST Hub signals */
-GPIO(MST_LP_CTL_L,                  PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(MST_RST_L,                     PIN(B, 3),  GPIO_ODR_LOW)
-GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
-
-/* Display Demux signals */
-GPIO(DEMUX_DUAL_DP_MODE,            PIN(D, 8),  GPIO_OUT_LOW)
-GPIO(DEMUX_DP_HDMI_MODE,            PIN(D, 10), GPIO_OUT_LOW)
-GPIO(DEMUX_DUAL_DP_RESET_N,         PIN(B, 14), GPIO_ODR_HIGH)
-GPIO(DEMUX_DUAL_DP_PD_N,            PIN(D, 2),  GPIO_ODR_HIGH)
-GPIO(DEMUX_DP_HDMI_PD_N,            PIN(D, 9),  GPIO_ODR_HIGH)
-
-/* USBC Mux and Demux Signals */
-GPIO(EN_DP_SINK,                    PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(DP_SINK_RESET,                 PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(USBC_DP_PD_RST_L,              PIN(C, 13), GPIO_ODR_LOW)
-GPIO(USBC_UF_RESET_L,               PIN(C, 11), GPIO_ODR_LOW)
-
-/* USB Hubs signals */
-GPIO(EC_HUB1_RESET_L,               PIN(E, 13), GPIO_ODR_LOW)
-GPIO(EC_HUB2_RESET_L,               PIN(E, 14), GPIO_ODR_LOW)
-
-/* DEBUG signals */
-GPIO(DEBUG_GPIO1,                   PIN(B, 13),      GPIO_OUT_LOW)
-
-/* Configure as output to enable @1.5A on USBA Ports
-* USB CDP enables. */
-GPIO(USB3_A1_CDP_EN,                PIN(E, 7),       GPIO_OUT_LOW)
-GPIO(USB3_A2_CDP_EN,                PIN(E, 8),       GPIO_OUT_LOW)
-GPIO(USB3_P3_CDP_EN,                PIN(D, 1),      GPIO_OUT_LOW)
-GPIO(USB3_P4_CDP_EN,                PIN(E, 12),      GPIO_OUT_LOW)
-
-/* Write protect */
-GPIO(EC_FLASH_WP_ODL,               PIN(A, 3),       GPIO_ODR_HIGH)
-GPIO(EC_WP_L,                       PIN(E, 11),      GPIO_INT_BOTH)
-
-
-/* SPI Bus */
-GPIO(FLASH_SPI1_NSS,                PIN(A, 4),       GPIO_INT_FALLING)
-GPIO(FLASH_SPI1_SCK,                PIN(A, 5),       GPIO_INT_BOTH)
-GPIO(FLASH_SPI1_MISO,               PIN(A, 6),       GPIO_INT_BOTH)
-GPIO(FLASH_SPI1_MOSI,               PIN(A, 7),       GPIO_INT_BOTH)
-
-/* misc signals */
-GPIO(EC_DFU_MUX_CTRL,               PIN(A, 8),       GPIO_OUT_HIGH)
-GPIO(TP71,               PIN(B, 0),       GPIO_OUT_LOW)
-
-/*
- * I2C SCL/SDA pins. These will normally be under control of the peripheral from
- * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
- * these signals as regular GPIOs.
- */
-GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
-GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
-
-UNIMPLEMENTED(EC_ENTERING_RW)
-
-ALTERNATE(PIN_MASK(B, 0x0C00), GPIO_ALT_USART,   MODULE_UART,     GPIO_PULL_UP) /* GPIOB 10-11:USART3_TX/RX */
-ALTERNATE(PIN_MASK(A, 0x00F0),      5,           MODULE_SPI,      0) /* GPIOA4-7: SPI Signals */
-/* I2C Ports
- *   I2C1: SDA/SCL -> PB7/PA15
- *   I2C2: SDA/SCL -> PA8/PA9
- *   I2C3: SDA/SCL -> PC8/PC9
- */
-ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
diff --git a/board/gooey/battery.c b/board/gooey/battery.c
deleted file mode 100644
index c40e0d7ec7..0000000000
--- a/board/gooey/battery.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all gooey battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L18D3PG1 Battery Information */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* LGC L17L3PB0 Battery Information */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Sunwoda L17M3PB0 Battery Information */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x0018,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/gooey/board.c b/board/gooey/board.c
deleted file mode 100644
index 518e159f9d..0000000000
--- a/board/gooey/board.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Gooey board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "keyboard_8042.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	gpio_set_level(GPIO_USB_C1_DP_HPD, !gpio_get_level(s));
-}
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/**
- * Deferred function to handle pen detect change
- */
-static void pendetect_deferred(void)
-{
-	static int debounced_pen_detect;
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	if (pen_detect == debounced_pen_detect)
-		return;
-
-	debounced_pen_detect = pen_detect;
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, debounced_pen_detect);
-	gpio_set_level(GPIO_PEN_DET_PCH, !debounced_pen_detect);
-}
-DECLARE_DEFERRED(pendetect_deferred);
-
-void pen_detect_interrupt(enum gpio_signal s)
-{
-	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Charger IC need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(0, false);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-};
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
-
-void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-	/* Enable gpio interrupt for pen detect */
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-	if (gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_PEN_DET_PCH, 1);
-
-	/* Set LEDs luminance */
-	pwm_set_duty(PWM_CH_LED_RED, 70);
-	pwm_set_duty(PWM_CH_LED_GREEN, 70);
-	pwm_set_duty(PWM_CH_LED_WHITE, 70);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	if (port != 0 && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	CPRINTUSB("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
-		raa489000_enable_asgate(0, false);
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTUSB("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTUSB("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_WHITE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	}
-
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* Sensor Data */
-static struct stprivate_data g_lis2dwl_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-static const struct ec_response_keybd_config gooey_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &gooey_keybd;
-}
diff --git a/board/gooey/board.h b/board/gooey/board.h
deleted file mode 100644
index bf7f36c0b9..0000000000
--- a/board/gooey/board.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Gooey board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_KEEBY_EC_IT8320
-#include "baseboard.h"
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* DAC for PSYS */
-#define CONFIG_DAC
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux */
-#define CONFIG_USB_MUX_IT5205
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_WHITE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-void pen_detect_interrupt(enum gpio_signal s);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gooey/build.mk b/board/gooey/build.mk
deleted file mode 100644
index ff15b3e8e4..0000000000
--- a/board/gooey/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=keeby
-
-board-y=board.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/gooey/ec.tasklist b/board/gooey/ec.tasklist
deleted file mode 100644
index bdcbcdf074..0000000000
--- a/board/gooey/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/gooey/gpio.inc b/board/gooey/gpio.inc
deleted file mode 100644
index 1eaae9e354..0000000000
--- a/board/gooey/gpio.inc
+++ /dev/null
@@ -1,146 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(E, 7), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Used by baseboard z-state enable, but not present on gooey */
-UNIMPLEMENTED(USB_C1_INT_ODL)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_A1_VBUS,		PIN(E, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-GPIO(EN_PP5000_PEN,	    	PIN(B, 5), GPIO_OUT_LOW)
-GPIO(PEN_DET_PCH,	    	PIN(F, 1), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(EC_CBI_WP,			PIN(H, 5), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH1_NC, PIN(H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL2_NC, PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* DAC */
-ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0) | BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* KB_BL_PWM, LED_[R,G,B]_ODL */
diff --git a/board/gooey/led.c b/board/gooey/led.c
deleted file mode 100644
index 6d55ce2932..0000000000
--- a/board/gooey/led.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Gooey specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		pwm_enable(PWM_CH_LED_WHITE, LED_ON_LVL);
-	else
-		pwm_enable(PWM_CH_LED_WHITE, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_RED, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_enable(PWM_CH_LED_RED, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_GREEN, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/gooey/usb_pd_policy.c b/board/gooey/usb_pd_policy.c
deleted file mode 100644
index b7c0ca21df..0000000000
--- a/board/gooey/usb_pd_policy.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	if (port != 0)
-		return;
-
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port != 0)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
diff --git a/board/gooey/vif_override.xml b/board/gooey/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/gooey/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/goroh/battery.c b/board/goroh/battery.c
deleted file mode 100644
index f07c38e1b8..0000000000
--- a/board/goroh/battery.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "usb_pd.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
diff --git a/board/goroh/board.c b/board/goroh/board.c
deleted file mode 100644
index b28322eca0..0000000000
--- a/board/goroh/board.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Goroh board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/it5205.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable motion sensor interrupt */
-	gpio_enable_interrupt(GPIO_BASE_IMU_INT_L);
-	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Sensor */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct stprivate_data g_lis2dwl_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)},
-};
-
-static void update_rotation_matrix(void)
-{
-	if (board_get_version() >= 2) {
-		motion_sensors[BASE_ACCEL].rot_standard_ref =
-			&base_standard_ref;
-		motion_sensors[BASE_GYRO].rot_standard_ref =
-			&base_standard_ref;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = NULL, /* identity matrix */
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = NULL, /* identity matrix */
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.int_signal = GPIO_LID_ACCEL_INT_L,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = NULL, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
-	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM */
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED3] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-int board_accel_force_mode_mask(void)
-{
-	int version = board_get_version();
-
-	if (version == -1 || version >= 2)
-		return 0;
-	return BIT(LID_ACCEL);
-}
-
-static void board_suspend(void)
-{
-	if (board_get_version() >= 3)
-		gpio_set_level(GPIO_EN_5V_USM, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	if (board_get_version() >= 3)
-		gpio_set_level(GPIO_EN_5V_USM, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-__override int syv682x_board_is_syv682c(int port)
-{
-	return board_get_version() > 2;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-enum adc_channel board_get_vbus_adc(int port)
-{
-	if (port == 0)
-		return  ADC_VBUS_C0;
-	if (port == 1)
-		return  ADC_VBUS_C1;
-	CPRINTSUSB("Unknown vbus adc port id: %d", port);
-	return ADC_VBUS_C0;
-}
-#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
diff --git a/board/goroh/board.h b/board/goroh/board.h
deleted file mode 100644
index 29334c9d7e..0000000000
--- a/board/goroh/board.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Goroh board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Chipset config */
-#define CONFIG_BRINGUP
-
-/* Optional features */
-#define CONFIG_LTO
-
-/*
- * TODO: Remove this option once the VBAT no longer keeps high when
- * system's power isn't presented.
- */
-#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-
-/* BC12 */
-/* TODO(b/159583342): remove after rev0 deprecated */
-#define CONFIG_MT6360_BC12_GPIO
-
-/* LED */
-#define CONFIG_LED_POWER_LED
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* PD / USB-C / PPC */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-
-/* Optional console commands */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
-
-/* Sensor */
-#define CONFIG_GMR_TABLET_MODE
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-/* TODO(b/171931139): remove this after rev1 board deprecated */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (board_accel_force_mode_mask())
-
-/* SPI / Host Command */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* USB-A */
-#define USBA_PORT_COUNT 1
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_TYPE_COUNT,
-};
-
-enum sensor_id {
-	BASE_ACCEL = 0,
-	BASE_GYRO,
-	LID_ACCEL,
-
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_VBUS,                /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_VBUS_C1,             /* ADC 5 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
-
-	/* Number of ADC channels */
-	ADC_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1,
-	PWM_CH_LED2,
-	PWM_CH_LED3,
-	PWM_CH_COUNT,
-};
-
-int board_accel_force_mode_mask(void);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/goroh/build.mk b/board/goroh/build.mk
deleted file mode 100644
index 468d9ad365..0000000000
--- a/board/goroh/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=goroh
-
-board-y+=battery.o board.o led.o
diff --git a/board/goroh/ec.tasklist b/board/goroh/ec.tasklist
deleted file mode 100644
index 75dbb1a828..0000000000
--- a/board/goroh/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, 1024) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
-
diff --git a/board/goroh/gpio.inc b/board/goroh/gpio.inc
deleted file mode 100644
index 8ffbb16414..0000000000
--- a/board/goroh/gpio.inc
+++ /dev/null
@@ -1,154 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
-	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* H1_EC_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         lid_interrupt)
-GPIO_INT(TABLET_MODE_L,      PIN(J, 7), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Chipset interrupts */
-GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_IMU_INT_L,     PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         bmi160_interrupt)
-GPIO_INT(LID_ACCEL_INT_L,    PIN(J, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         lis2dw12_interrupt)
-GPIO(ALS_RGB_INT_ODL,        PIN(F, 0), GPIO_INPUT)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_L,  PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-
-/* Other interrupts */
-GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
-GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         switch_interrupt) /* EC_FLASH_WP_OD */
-GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-GPIO_INT(X_EC_GPIO2,         PIN(B, 2), GPIO_ODR_HIGH, x_ec_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
-GPIO(PG_MT6315_PROC_ODL,     PIN(E, 1), GPIO_INPUT)
-GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
-GPIO(PG_PP5000_A_ODL,        PIN(A, 6), GPIO_INPUT)
-GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
-GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
-
-/* USB and USBC Signals */
-GPIO(DP_AUX_PATH_SEL,        PIN(G, 0), GPIO_OUT_HIGH)
-GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_USB_A0_VBUS,  PIN(B, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,          PIN(H, 3), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
-GPIO(BC12_DET_EN,            PIN(J, 5), GPIO_OUT_LOW) /* EN_USB_C0_BC12_DET */
-GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
-GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
-GPIO(EN_5V_USM,              PIN(D, 7), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
-GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
-
-/* SPI pins - Alternate function below configures SPI module on these pins */
-
-/* NC / TP */
-
-/* Keyboard pins */
-
-/* Subboards HDMI/TYPEC */
-GPIO(EC_X_GPIO1,             PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EC_X_GPIO3,             PIN(J, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, 0x07), 1, MODULE_PWM, 0) /* PWM 0~2 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0x6F), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,5,6 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
-
-/* Unimplemented Pins  */
-GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-GPIO(EN_PP3000_VMC_PMU,      PIN(D, 2), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-GPIO(PACKET_MODE_EN,         PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-/* b/160218054: behavior not defined */
-/* *_ODL pin has external pullup so don't pull it down. */
-GPIO(USB_A0_FAULT_ODL,       PIN(A, 7), GPIO_INPUT)
-GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3), GPIO_INPUT)
-GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
-GPIO(EN_PP3000_SD_U,         PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-/* reserved for future use */
-GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
-/*
- * ADC pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPI7,                PIN(I, 7), GPIO_OUT_LOW)
-/* NC pins, enable internal pull-up/down to avoid floating state. */
-GPIO(NC_GPM2,                PIN(M, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPM3,                PIN(M, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-/*
- * These 4 pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPG3,                PIN(G, 3), GPIO_OUT_LOW)
-GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
-GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
-GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/goroh/led.c b/board/goroh/led.c
deleted file mode 100644
index c06fdef0cb..0000000000
--- a/board/goroh/led.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-#include "driver/bc12/mt6360.h"
-
-const int led_charge_lvl_1 = 5;
-const int led_charge_lvl_2 = 95;
-
-struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB2, 50);
-	mt6360_led_set_brightness(MT6360_LED_RGB3, 50);
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 1);
-		break;
-	case EC_LED_COLOR_WHITE:
-		mt6360_led_enable(MT6360_LED_RGB2, 1);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		mt6360_led_enable(MT6360_LED_RGB2, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB1, 1);
-	mt6360_led_enable(MT6360_LED_RGB1, color == EC_LED_COLOR_WHITE);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] =
-				MT6360_LED_BRIGHTNESS_MAX;
-		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/goroh/vif_override.xml b/board/goroh/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/goroh/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/grunt/analyzestack.yaml b/board/grunt/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/grunt/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/grunt/battery.c b/board/grunt/battery.c
deleted file mode 100644
index 359ec9785b..0000000000
--- a/board/grunt/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Grunt battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP15O5L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/grunt/board.c b/board/grunt/board.c
deleted file mode 100644
index 45aa4f4421..0000000000
--- a/board/grunt/board.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Grunt board-specific configuration */
-
-#include "button.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/led/lm3630a.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED1_AMBER] = {
-		.channel = 0,
-		.flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW
-			  | PWM_CONFIG_DSLEEP),
-		.freq = 100,
-	},
-	[PWM_CH_LED2_BLUE] =   {
-		.channel = 2,
-		.flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW
-			  | PWM_CONFIG_DSLEEP),
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-void board_update_sensor_config_from_sku(void)
-{
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-}
-
-static void board_kblight_init(void)
-{
-	/*
-	 * Enable keyboard backlight. This needs to be done here because
-	 * the chip doesn't have power until PP3300_S0 comes up.
-	 */
-	gpio_set_level(GPIO_KB_BL_EN, 1);
-	lm3630a_poweron();
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
diff --git a/board/grunt/board.h b/board/grunt/board.h
deleted file mode 100644
index 2585db17fd..0000000000
--- a/board/grunt/board.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Grunt board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3429
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-#define CONFIG_MKBP_USE_HOST_EVENT
-
-/* Work around Grunt KSI03 HW bug and rework (b/79758966) */
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
-
-/* Power and battery LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_BLUE
-#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_BLUE
-
-#define CONFIG_LED_PWM_COUNT 1
-
-#define I2C_PORT_KBLIGHT NPCX_I2C_PORT5_0
-
-/* KB backlight driver */
-#define CONFIG_LED_DRIVER_LM3630A
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-/*
- * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
- */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
-#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
-
-#ifndef __ASSEMBLER__
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_LED1_AMBER,
-	PWM_CH_LED2_BLUE,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_PANASONIC,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/grunt/build.mk b/board/grunt/build.mk
deleted file mode 100644
index c808e65aed..0000000000
--- a/board/grunt/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/grunt/ec.tasklist b/board/grunt/ec.tasklist
deleted file mode 100644
index dc898c4502..0000000000
--- a/board/grunt/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/grunt/gpio.inc b/board/grunt/gpio.inc
deleted file mode 100644
index 97f5afabfd..0000000000
--- a/board/grunt/gpio.inc
+++ /dev/null
@@ -1,115 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(0, 2), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_APU_RST,		PIN(E, 4), GPIO_INPUT)				/* Reset to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(KB_BL_EN,			PIN(F, 2), GPIO_OUT_LOW)			/* Enable KB Backlight */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
-										   EC_I2C_KB_BL_SCL */
-GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
-										   EC_I2C_KB_BL_SDA */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-GPIO(PCH_SLP_S0_L,		PIN(A, 4), GPIO_INPUT)
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(EN_USB_C0_TCPC_PWR,	PIN(6, 0), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST_L,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP)	/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)					/* KB Backlight */
-ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) 					/* LED 1 & 2 */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0)					/* GPIO00, GPIO01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 */
diff --git a/board/grunt/led.c b/board/grunt/led.c
deleted file mode 100644
index 824ec55f6c..0000000000
--- a/board/grunt/led.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * We only have a blue and an amber LED, so setting any other colour results in
- * both LEDs being off.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, Blue */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,   0 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
-};
-
-/* One logical LED with amber and blue channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1_AMBER,
-		.ch1 = PWM_CH_LED2_BLUE,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/grunt/vif_override.xml b/board/grunt/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/grunt/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/gumboz/analyzestack.yaml b/board/gumboz/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/gumboz/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/gumboz/battery.c b/board/gumboz/battery.c
deleted file mode 100644
index 7d1831fdbc..0000000000
--- a/board/gumboz/battery.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Gumboz battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Coslight Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack Cosmx Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Cosmx Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_COS;
diff --git a/board/gumboz/board.c b/board/gumboz/board.c
deleted file mode 100644
index 4428819415..0000000000
--- a/board/gumboz/board.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "button.h"
-#include "cros_board_info.h"
-#include "charge_state.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
-
-#include "gpio_list.h"
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data  g_kx022_data;
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_6AXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	  .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_6AXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*****************************************************************************
- * Retimers
- */
-
-static void retimers_on(void)
-{
-	/* usba retimer power on */
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, retimers_on, HOOK_PRIO_DEFAULT);
-
-static void retimers_off(void)
-{
-	/* usba retimer power off */
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, retimers_off, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * USB-C
- */
-
-/*
- * USB C0 port SBU mux use standalone PI3USB221
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int pi3usb221_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			     bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = pi3usb221_set_mux,
-};
-
-/*
- * Since PI3USB221 is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		/*
-		 * Sensitive only to falling edges; GPIO is configured for both
-		 * because this input may be used for HDMI HPD instead.
-		 */
-		if (!gpio_get_level(signal))
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	case USBC_PORT_C1:
-		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-static void setup_fw_config(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
-
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[IOEX_C1_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-#define CHARGING_CURRENT_500MA 500
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int rv;
-	static int thermal_sensor_temp;
-	static int prev_thermal_sensor_temp;
-	static int limit_charge;
-	static int limit_usbc_power;
-	static int limit_usbc_power_backup;
-	enum tcpc_rp_value rp;
-
-	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor_temp);
-
-	if (rv != EC_SUCCESS)
-		return 0;
-
-	if (thermal_sensor_temp > prev_thermal_sensor_temp) {
-		if (thermal_sensor_temp > C_TO_K(63))
-			limit_usbc_power = 1;
-
-		else if (thermal_sensor_temp > C_TO_K(58)) {
-			if (curr->state == ST_CHARGE)
-				limit_charge = 1;
-		}
-	} else if (thermal_sensor_temp < prev_thermal_sensor_temp) {
-		if (thermal_sensor_temp < C_TO_K(57)) {
-			if (curr->state == ST_CHARGE)
-				limit_charge = 0;
-
-		} else if (thermal_sensor_temp < C_TO_K(62))
-			limit_usbc_power = 0;
-	}
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return 0;
-
-	curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA
-						 : curr->batt.desired_current;
-
-	if (limit_usbc_power != limit_usbc_power_backup) {
-		rp = (limit_usbc_power) ? TYPEC_RP_1A5
-					: TYPEC_RP_3A0;
-
-		ppc_set_vbus_source_current_limit(0, rp);
-		tcpm_select_rp_value(0, rp);
-		pd_update_contract(0);
-		limit_usbc_power_backup = limit_usbc_power;
-	}
-
-	prev_thermal_sensor_temp = thermal_sensor_temp;
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-							uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-							uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-__override struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(63),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(62),
-		}
-	},
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(77),
-		}
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(83),
-		}
-	},
-};
diff --git a/board/gumboz/board.h b/board/gumboz/board.h
deleted file mode 100644
index 0cf51b5166..0000000000
--- a/board/gumboz/board.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_DALBOZ
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PORT_ENABLE_DYNAMIC
-
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
-
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* USB-A config */
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-
-/* LED */
-#undef CONFIG_LED_ONOFF_STATES
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-extern int I2C_PORT_BATTERY;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_COS,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * DALBOZ_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	DALBOZ_MB_USBAC = 0,
-};
-
-/**
- * GUMBOZ_DB_OPT1_USBC
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: PS8719
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8743
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- */
-enum ec_cfg_usb_db_type {
-	GUMBOZ_DB_OPT1_USBC = 0,
-};
-
-#include "cbi_ec_fw_config.h"
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return 0;
-}
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/gumboz/build.mk b/board/gumboz/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/gumboz/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/gumboz/ec.tasklist b/board/gumboz/ec.tasklist
deleted file mode 100644
index d9c1606eb2..0000000000
--- a/board/gumboz/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/gumboz/gpio.inc b/board/gumboz/gpio.inc
deleted file mode 100644
index 9beaecc17a..0000000000
--- a/board/gumboz/gpio.inc
+++ /dev/null
@@ -1,138 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(TABLET_MODE_L,		PIN(4, 4), GPIO_INT_BOTH,			gmr_tablet_switch_isr)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	lsm6dsm_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,		PIN(C, 3), GPIO_OUT_HIGH)
-
-/*
- * Gumboz has 1 DB options.
- * IOEX_C1_NCT3807 is the DB (USB-C1).
- */
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN,	EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,	EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-IOEX(C1_CHARGER_LED_WHITE_DB,EXPIN(IOEX_C1_NCT3807, 1, 0), GPIO_OUT_HIGH)	/* C1 Charge LED White */
-IOEX(C1_CHARGER_LED_AMBER_DB,EXPIN(IOEX_C1_NCT3807, 1, 4), GPIO_OUT_HIGH)	/* C1 Charge LED Amber */
-
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/gumboz/led.c b/board/gumboz/led.c
deleted file mode 100644
index 0640a6cd21..0000000000
--- a/board/gumboz/led.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "cros_board_info.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_ON_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-	uint32_t board_ver = 0;
-	int led_batt_on_lvl, led_batt_off_lvl;
-
-	cbi_get_board_version(&board_ver);
-	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
-				 IOEX_C1_CHARGER_LED_AMBER_DB);
-	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
-				 IOEX_C1_CHARGER_LED_WHITE_DB);
-
-	if ((board_ver >= 2) && (port == RIGHT_PORT)) {
-		led_batt_on_lvl = 1;
-		led_batt_off_lvl = 0;
-	} else {
-		led_batt_on_lvl = 0;
-		led_batt_off_lvl = 1;
-	}
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_or_ioex_set_level(white_led, led_batt_on_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
-		break;
-	case LED_AMBER:
-		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_on_lvl);
-		break;
-	case LED_OFF:
-		gpio_or_ioex_set_level(white_led, led_batt_off_lvl);
-		gpio_or_ioex_set_level(amber_led, led_batt_off_lvl);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/gumboz/vif_override.xml b/board/gumboz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/gumboz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/guybrush/battery.c b/board/guybrush/battery.c
deleted file mode 100644
index ddf3adff50..0000000000
--- a/board/guybrush/battery.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-
-/*
- * Battery info for all Guybrush battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AEC 5477109 */
-	[BATTERY_AEC] = {
-		.fuel_gauge = {
-			.manuf_name = "AEC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.sleep_mode = {
-				.sleep_supported = true,
-				.reg_addr = 0x00,
-				.reg_data = 0x0011,
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8700,	/* mV */
-			.voltage_normal       = 7600,
-			.voltage_min          = 6000,
-			.precharge_current    = 100,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 50,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 60,
-		},
-	},
-	/* AP18F4M / LIS4163ACPC */
-	[BATTERY_AP18F4M] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00404001",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8700,	/* mV */
-			.voltage_normal       = 7600,
-			.voltage_min          = 5500,
-			.precharge_current    = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* POW-TECH Battery Information */
-	[BATTERY_POWER_TECH] = {
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.sleep_mode = {
-				.sleep_supported = true,
-				.reg_addr = 0x00,
-				.reg_data = 0x0011,
-			},
-			.fet = {
-				.reg_addr       = 0x00,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8800,	/* mV */
-			.voltage_normal       = 7700,
-			.voltage_min          = 6000,
-			.precharge_current    = 88,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 45,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
diff --git a/board/guybrush/board.c b/board/guybrush/board.c
deleted file mode 100644
index 75fb5a8607..0000000000
--- a/board/guybrush/board.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush board-specific configuration */
-
-#include "adc.h"
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi323.h"
-#include "driver/accel_bma422.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/temp_sensor/tmp112.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "temp_sensor/tmp112.h"
-#include "thermal.h"
-#include "usb_mux.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Motion sensor mutex */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Motion sensor private data */
-static struct bmi_drv_data_t g_bmi_data;
-static struct accelgyro_saved_data_t g_bma422_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA422,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma4_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma422_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA4_ACCEL_MIN_FREQ,
-		.max_frequency = BMA4_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, enough for laptop. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI323,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi3xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI323,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi3xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t bmi160_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref,
-	.min_frequency = BMI_ACCEL_MIN_FREQ,
-	.max_frequency = BMI_ACCEL_MAX_FREQ,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t bmi160_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI160,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi160_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref,
-	.min_frequency = BMI_GYRO_MIN_FREQ,
-	.max_frequency = BMI_GYRO_MAX_FREQ,
-};
-
-__override enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	/* Set channel A output swing */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING,
-		PS8811_CHAN_A_SWING_MASK, 0x2 << PS8811_CHAN_A_SWING_SHIFT));
-
-	/* Set channel B output swing */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_SWING,
-		PS8811_CHAN_B_SWING_MASK, 0x2 << PS8811_CHAN_B_SWING_SHIFT));
-
-	/* Set channel B de-emphasis to -6dB and pre-shoot to 1.5 dB */
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_LSB,
-		PS8811_CHAN_B_DE_PS_LSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_LSB));
-
-	RETURN_ERROR(ps8811_i2c_field_update(
-		me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
-		PS8811_CHAN_B_DE_PS_MSB_MASK, PS8811_CHAN_B_DE_6_PS_1_5_MSB));
-
-	return EC_SUCCESS;
-}
-
-/*
- * PS8818 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- * TODO(b/179036200): Adjust PS8818 tuning for guybrush reference
- */
-__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 1);
-	} else {
-		/* Disable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 0);
-	}
-
-	return rv;
-}
-
-/*
- * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default
- * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c
- * address to 0x2A. ANX7491(A1) will stay at the default 0x29.
- */
-uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me)
-{
-	ASSERT(me->usb_port == USBC_PORT_C1);
-	return 0x2a;
-}
-
-/*
- * Base Gyro Sensor dynamic configuration
- */
-static int base_gyro_config;
-
-static void board_update_motion_sensor_config(void)
-{
-	if (board_is_convertible()) {
-		if (get_board_version() == 1) {
-			motion_sensors[BASE_ACCEL] = bmi160_base_accel;
-			motion_sensors[BASE_GYRO] = bmi160_base_gyro;
-			base_gyro_config = BASE_GYRO_BMI160;
-			ccprints("BASE GYRO is BMI160");
-		} else {
-			base_gyro_config = BASE_GYRO_BMI323;
-			ccprints("BASE GYRO is BMI323");
-		}
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel and Gyro interrupt */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case BASE_GYRO_BMI160:
-		bmi160_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI323:
-	default:
-		bmi3xx_interrupt(signal);
-		break;
-	}
-}
-
-static void board_init(void)
-{
-	board_update_motion_sensor_config();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	if (get_board_version() > 1)
-		tmp112_init();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-int board_get_soc_temp_k(int idx, int *temp_k)
-{
-	uint32_t board_version = get_board_version();
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	if (board_version == 1)
-		return get_temp_3v3_30k9_47k_4050b(ADC_TEMP_SENSOR_SOC, temp_k);
-
-	return tmp112_get_val_k(idx, temp_k);
-}
-
-int board_get_soc_temp_mk(int *temp_mk)
-{
-	uint32_t board_version = get_board_version();
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	if (board_version == 1)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return tmp112_get_val_mk(TMP112_SOC, temp_mk);
-}
-
-int board_get_ambient_temp_mk(int *temp_mk)
-{
-	uint32_t board_version = get_board_version();
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	if (board_version == 1)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return tmp112_get_val_mk(TMP112_AMB, temp_mk);
-}
-
-/* ADC Channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_MEMORY] = {
-		.name = "MEMORY",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_CORE_IMON1] = {
-		.name = "CORE_I",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SOC_IMON2] = {
-		.name = "SOC_I",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temp Sensors */
-static int board_get_memory_temp(int, int *);
-
-const struct tmp112_sensor_t tmp112_sensors[] = {
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS0 },
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS1 },
-};
-BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_soc_temp_k,
-		.idx = TMP112_SOC,
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.name = "Memory",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_memory_temp,
-		.idx = ADC_TEMP_SENSOR_MEMORY,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-	[TEMP_SENSOR_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = tmp112_get_val_k,
-		.idx = TMP112_AMB,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/* TODO: Setting fan off to 0 so it's allways on */
-		.temp_fan_off = C_TO_K(0),
-		.temp_fan_max = C_TO_K(70),
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/*
-		 * CPU temp sensor fan thresholds are high because they are a
-		 * backup for the SOC temp sensor fan thresholds.
-		 */
-		.temp_fan_off = C_TO_K(60),
-		.temp_fan_max = C_TO_K(90),
-	},
-	/*
-	 * Note: Leave ambient entries at 0, both as it does not represent a
-	 * hotspot and as not all boards have this sensor
-	 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static int board_get_memory_temp(int idx, int *temp_k)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
-}
diff --git a/board/guybrush/board.h b/board/guybrush/board.h
deleted file mode 100644
index 39adbc2ec7..0000000000
--- a/board/guybrush/board.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Motion sensing drivers */
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI3XX
-#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_BMA4XX
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_MUX_ANX7451
-#define CONFIG_USBC_RETIMER_ANX7451
-
-/* USB Type A Features */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* LED features */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-/* Battery Types */
-enum battery_type {
-	BATTERY_AEC,
-	BATTERY_AP18F4M,
-	BATTERY_POWER_TECH,
-	BATTERY_TYPE_COUNT,
-};
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_BMI323 = 2,
-};
-
-/* ADC Channels */
-enum adc_channel {
-	ADC_TEMP_SENSOR_SOC = 0,
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_MEMORY,
-	ADC_CORE_IMON1,
-	ADC_SOC_IMON2,
-	ADC_CH_COUNT
-};
-
-/* Temp Sensors */
-enum temp_sensor_id {
-	TEMP_SENSOR_SOC = 0,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_MEMORY,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/guybrush/board_fw_config.c b/board/guybrush/board_fw_config.c
deleted file mode 100644
index c919d82851..0000000000
--- a/board/guybrush/board_fw_config.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-
-bool board_is_convertible(void)
-{
-	return (get_fw_config_field(FW_CONFIG_FORM_FACTOR_OFFSET,
-			FW_CONFIG_FORM_FACTOR_WIDTH)
-			== FW_CONFIG_FORM_FACTOR_CONVERTIBLE);
-}
-
-bool board_has_kblight(void)
-{
-	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
-}
-
-enum board_usb_c1_mux board_get_usb_c1_mux(void)
-{
-	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
-					 FW_CONFIG_USB_DB_WIDTH);
-	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
-		return USB_C1_MUX_PS8818;
-	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
-		return USB_C1_MUX_ANX7451;
-	return USB_C1_MUX_UNKNOWN;
-};
-
-enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
-{
-	int usb_db = get_fw_config_field(FW_CONFIG_USB_DB_OFFSET,
-					 FW_CONFIG_USB_DB_WIDTH);
-	if (usb_db == FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818)
-		return USB_A1_RETIMER_PS8811;
-	if (usb_db == FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451)
-		return USB_A1_RETIMER_ANX7491;
-	return USB_A1_RETIMER_UNKNOWN;
-};
diff --git a/board/guybrush/board_fw_config.h b/board/guybrush/board_fw_config.h
deleted file mode 100644
index 1de417d77a..0000000000
--- a/board/guybrush/board_fw_config.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _GUYBRUSH_BOARD_FW_CONFIG__H_
-#define _GUYBRUSH_BOARD_FW_CONFIG__H_
-
-/****************************************************************************
- * Guybrush CBI FW Configuration
- */
-
-/*
- * USB Daughter Board (2 bits)
- */
-#define FW_CONFIG_USB_DB_OFFSET			0
-#define FW_CONFIG_USB_DB_WIDTH			2
-#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818	0
-#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451	1
-
-/*
- * Form Factor (1 bits)
- */
-#define FW_CONFIG_FORM_FACTOR_OFFSET		2
-#define FW_CONFIG_FORM_FACTOR_WIDTH		1
-#define FW_CONFIG_FORM_FACTOR_CLAMSHELL		0
-#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE	1
-
-/*
- * Keyboard Backlight (1 bit)
- */
-#define FW_CONFIG_KBLIGHT_OFFSET		3
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
-
-
-#endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/guybrush/build.mk b/board/guybrush/build.mk
deleted file mode 100644
index 5c8bde1a2b..0000000000
--- a/board/guybrush/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-BASEBOARD:=guybrush
-
-board-y=board.o
-board-y+=board_fw_config.o led.o battery.o
diff --git a/board/guybrush/ec.tasklist b/board/guybrush/ec.tasklist
deleted file mode 100644
index f7cf0f7205..0000000000
--- a/board/guybrush/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/guybrush/gpio.inc b/board/guybrush/gpio.inc
deleted file mode 100644
index b7381f588d..0000000000
--- a/board/guybrush/gpio.inc
+++ /dev/null
@@ -1,28 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the board GPIOs that we care about. */
-
-#include "base_gpio.inc"
-
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP, motion_interrupt)		/* 6 Axis IMU */
-GPIO_INT(TABLET_MODE,		PIN(C, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)			/* 360 Tablet Mode */
-
-/* LED Signals */
-ALTERNATE(/*EC_PWM_LED_CHRG_L*/	PIN_MASK(C, BIT(4)), 0, 			MODULE_PWM, 0)		/* Charging LED */
-ALTERNATE(/*EC_PWM_LED_FULL_L*/	PIN_MASK(8, BIT(0)), 0, 			MODULE_PWM, 0)		/* Full LED */
-
-/* Test Points */
-GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_CLK,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_DAT,		PIN(7, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
\ No newline at end of file
diff --git a/board/guybrush/led.c b/board/guybrush/led.c
deleted file mode 100644
index b17c8be488..0000000000
--- a/board/guybrush/led.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Guybrush specific PWM LED settings.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-#include "pwm.h"
-
-/* Note PWM LEDs are active low */
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		pwm_enable(PWM_CH_LED_CHRG, LED_ON_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_ON_LVL);
-		break;
-	case LED_OFF:
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	default: /* Unsupported colors */
-		CPRINTS("Unsupported LED color: %d", color);
-		pwm_enable(PWM_CH_LED_CHRG, LED_OFF_LVL);
-		pwm_enable(PWM_CH_LED_FULL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else {
-		CPRINTS("Unsupported LED set: %d", led_id);
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/guybrush/vif_override.xml b/board/guybrush/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/guybrush/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/haboki/battery.c b/board/haboki/battery.c
deleted file mode 100644
index 551ff1cbc0..0000000000
--- a/board/haboki/battery.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all haboki battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack HIGHPOWER Battery Information */
-	[BATTERY_DYNAPACK_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2D-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack BYD Battery Information */
-	[BATTERY_DYNAPACK_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2E-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo CosMX Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS_2] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* ATL GB-S20-4473A9-01H&020H Battery Information
-	 * Gauge IC : RAJ240045
-	 */
-	[BATTERY_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "313-B7-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/haboki/board.c b/board/haboki/board.c
deleted file mode 100644
index f748cf90a6..0000000000
--- a/board/haboki/board.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Haboki board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-uint32_t board_version;
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-__override void board_process_pd_alert(int port)
-{
-	/*
-	 * PD_INT task will process this alert, and that task is only needed on
-	 * C1.
-	 */
-	if (port != 1)
-		return;
-
-	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return;
-
-	sm5803_handle_interrupt(port);
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
-		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	else
-		button_interrupt(s);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-	} else {
-		/* Select AUX option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 1);
-	}
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/* Store board version for use in determining charge limits */
-	cbi_get_board_version(&board_version);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	if (board_get_charger_chip_count() > 1) {
-		/* Charger on the sub-board will be a push-pull GPIO */
-		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-static void board_suspend(void)
-{
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-
-	if (board_get_charger_chip_count() > 1) {
-		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CHARGER_NUM;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/* Limit C1 on board version 0 to 2.0 A */
-	if ((board_version == 0) && (port == 1))
-		icl = MIN(icl, 2000);
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	charger_set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 20;
-
-	*ki = 3;
-	*ki_div = 125;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/haboki/board.h b/board/haboki/board.h
deleted file mode 100644
index 8e9d78bc02..0000000000
--- a/board/haboki/board.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Haboki board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_KEEBY_EC_IT8320
-#include "baseboard.h"
-
-#undef GPIO_VOLUME_UP_L
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_PWM_KBLIGHT
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_HIGHPOWER,
-	BATTERY_DYNAPACK_BYD,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_COS_2,
-	BATTERY_ATL,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/haboki/build.mk b/board/haboki/build.mk
deleted file mode 100644
index aa0e3b766e..0000000000
--- a/board/haboki/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=keeby
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/haboki/cbi_ssfc.c b/board/haboki/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/haboki/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/haboki/cbi_ssfc.h b/board/haboki/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/haboki/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/haboki/ec.tasklist b/board/haboki/ec.tasklist
deleted file mode 100644
index 5c9a2d1a01..0000000000
--- a/board/haboki/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/haboki/gpio.inc b/board/haboki/gpio.inc
deleted file mode 100644
index c1a03bfd56..0000000000
--- a/board/haboki/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
-GPIO(EC_CBI_WP,			PIN(H, 5), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG0_NC, PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH1_NC, PIN(H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* LED */
-GPIO(BAT_LED_AMBER_L,	 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/haboki/led.c b/board/haboki/led.c
deleted file mode 100644
index 18b875b85f..0000000000
--- a/board/haboki/led.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Haboki specific LED settings. */
-
-#include "cbi_fw_config.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	case EC_LED_ID_POWER_LED:
-		rv = led_set_color_power(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LED for Drawlet/Drawman, Drawlet/Drawman
-	 * don't have power LED, blinking battery white LED to indicate
-	 * system suspend without charging.
-	 */
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/haboki/usb_pd_policy.c b/board/haboki/usb_pd_policy.c
deleted file mode 100644
index 3ff7152541..0000000000
--- a/board/haboki/usb_pd_policy.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	prev_en = charger_is_sourcing_otg_power(port);
-
-	/* Disable Vbus */
-	charger_enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable sinking */
-	rv = sm5803_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	charger_enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return sm5803_is_vbus_present(port);
-}
diff --git a/board/haboki/vif_override.xml b/board/haboki/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/haboki/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/hadoken/board.c b/board/hadoken/board.c
deleted file mode 100644
index d9c8ed322f..0000000000
--- a/board/hadoken/board.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "gpio.h"
-#include "registers.h"
-#include "util.h"
-
-
-/* To define the gpio_list[] instance. */
-#include "gpio_list.h"
-
diff --git a/board/hadoken/board.h b/board/hadoken/board.h
deleted file mode 100644
index ef4b45640d..0000000000
--- a/board/hadoken/board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hadoken board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#ifndef __ASSEMBLER__
-
-#undef CONFIG_FLASH_CROS /* TODO: implement me */
-#undef CONFIG_FLASH_PHYSICAL /* TODO: implement me */
-#undef CONFIG_FMAP /* TODO: implement me */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_LID_SWITCH
-
-/*
- *  nRF51 board specific configuration.
- */
-#define NRF51_UART_TX_PIN 24
-#define NRF51_UART_RX_PIN 28
-
-#define BATTERY_VOLTAGE_MAX         4425 /* mV */
-#define BATTERY_VOLTAGE_NORMAL      3800 /* mV */
-#define BATTERY_VOLTAGE_MIN         3000 /* mV */
-
-#define CONFIG_BLUETOOTH_LE
-#define CONFIG_BLUETOOTH_LE_STACK
-#define CONFIG_BLUETOOTH_LE_RADIO_TEST
-#define CONFIG_BLUETOOTH_LL_DEBUG
-#define CONFIG_BLUETOOTH_HCI_DEBUG
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
-
diff --git a/board/hadoken/build.mk b/board/hadoken/build.mk
deleted file mode 100644
index b2fee56f23..0000000000
--- a/board/hadoken/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is Nordic nRF51822
-CHIP:=nrf51
-CHIP_FAMILY:=nrf51x22
-CHIP_VARIANT:=nrf51822
-
-# Hadoken does not support scratchpad
-test-list-y=
-
-board-y=board.o
diff --git a/board/hadoken/ec.tasklist b/board/hadoken/ec.tasklist
deleted file mode 100644
index 0bb461ecb8..0000000000
--- a/board/hadoken/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(BLE_LL, bluetooth_ll_task, NULL, TASK_STACK_SIZE)
-
diff --git a/board/hadoken/gpio.inc b/board/hadoken/gpio.inc
deleted file mode 100644
index ac4127992c..0000000000
--- a/board/hadoken/gpio.inc
+++ /dev/null
@@ -1,59 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-/* Keyboard inputs */
-/*
- * TODO(yjlou): call keyboard_raw_gpio_interrupt() in chip/nrf51/keyboard_raw.c
- */
-GPIO(KB_IN00, PIN(0, 6),  GPIO_KB_INPUT)
-GPIO(KB_IN01, PIN(0, 23), GPIO_KB_INPUT)
-GPIO(KB_IN02, PIN(0, 1),  GPIO_KB_INPUT)
-GPIO(KB_IN03, PIN(0, 4),  GPIO_KB_INPUT)
-GPIO(KB_IN04, PIN(0, 0),  GPIO_KB_INPUT)
-GPIO(KB_IN05, PIN(0, 29), GPIO_KB_INPUT)
-GPIO(KB_IN06, PIN(0, 22), GPIO_KB_INPUT)
-GPIO(KB_IN07, PIN(0, 25), GPIO_KB_INPUT)
-
-/* Other inputs */
-GPIO(LID_PRESENT_L, PIN(0, 30), GPIO_INPUT)    /* Hall sensor */
-
-/* Useful for test software */
-GPIO(IND_CHRG_DISABLE, PIN(0, 20), GPIO_INPUT)
-
-/* Outputs */
-GPIO(KB_OUT00, PIN(0, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01, PIN(0, 10), GPIO_KB_OUTPUT)
-GPIO(KB_OUT02, PIN(0, 7),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT03, PIN(0, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04, PIN(0, 3),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05, PIN(0, 9),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06, PIN(0, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07, PIN(0, 27), GPIO_KB_OUTPUT)
-GPIO(KB_OUT08, PIN(0, 18), GPIO_KB_OUTPUT)
-GPIO(KB_OUT09, PIN(0, 16), GPIO_KB_OUTPUT)
-GPIO(KB_OUT10, PIN(0, 12), GPIO_KB_OUTPUT)
-GPIO(KB_OUT11, PIN(0, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT12, PIN(0, 11), GPIO_KB_OUTPUT)
-
-/* SPI */
-GPIO(MCU_SPI_MOSI, PIN(0, 13), GPIO_OUTPUT)
-GPIO(MCU_SPI_MISO, PIN(0, 14), GPIO_INPUT)
-GPIO(MCU_SPI_SCLK, PIN(0, 17), GPIO_OUTPUT)
-GPIO(MCU_SPI_CS_L, PIN(0, 19), GPIO_OUT_HIGH)
-
-/* VBATT_SENSE */
-GPIO(VBATT_SENSE, PIN(0, 26), GPIO_ANALOG)
-GPIO(VBATT_SENSE_EN, PIN(0, 21), GPIO_OUT_LOW)
-
-/* Unimplemented */
-UNIMPLEMENTED(ENTERING_RW)
diff --git a/board/halvor/battery.c b/board/halvor/battery.c
deleted file mode 100644
index 828220fd49..0000000000
--- a/board/halvor/battery.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AEC AEC335181 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/162908664, comment #4
-	 */
-	[BATTERY_AEC] = {
-		.fuel_gauge = {
-			.manuf_name = "AEC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8700, /* mV */
-			.voltage_normal		= 7600, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AEC;
diff --git a/board/halvor/board.c b/board/halvor/board.c
deleted file mode 100644
index 53828b5318..0000000000
--- a/board/halvor/board.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "accelgyro.h"
-#include "assert.h"
-#include "button.h"
-#include "common.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_pd_tbt.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_mux.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff,
-		0xa0, 0xff, 0xfe, 0x41, 0xfa, 0xc0, 0x02,
-		0x08, /* full set */
-	},
-};
-
-/******************************************************************************/
-static const struct ec_response_keybd_config halvor_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_BRIGHTNESS_DOWN,	/* T5 */
-		TK_BRIGHTNESS_UP,	/* T6 */
-		TK_PLAY_PAUSE,		/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &halvor_kb;
-}
-
-/*
- * FW_CONFIG defaults for Halvor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	/* Set all FW_CONFIG fields default to 0 */
-	.raw_value = 0,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/153995632): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Halvor.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On the volteer reference board 1 only port 1 supports TBT & USB4
-	 *
-	 * TODO (b/153995632): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Halvor.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_0_SCL,
-		.sda = GPIO_EC_I2C_0_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_1_SCL,
-		.sda = GPIO_EC_I2C_1_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_2_SCL,
-		.sda = GPIO_EC_I2C_2_SDA,
-	},
-	{
-		.name = "usb_bb_retimer",
-		.port = I2C_PORT_USB_BB_RETIMER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_3_SCL,
-		.sda = GPIO_EC_I2C_3_SDA,
-	},
-	{
-		.name = "usb_c2",
-		.port = I2C_PORT_USB_C2,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_4_SCL,
-		.sda = GPIO_EC_I2C_4_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_5_SCL,
-		.sda = GPIO_EC_I2C_5_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_7_SCL,
-		.sda = GPIO_EC_I2C_7_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-void halvor_tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = USBC_PORT_C0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = USBC_PORT_C1;
-		break;
-	case GPIO_USB_C2_TCPC_INT_ODL:
-		port = USBC_PORT_C2;
-		break;
-	default:
-		return;
-	}
-
-	ASSERT(port != -1);
-	schedule_deferred_pd_interrupt(port);
-}
-
-void halvor_ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
-	default:
-		break;
-	}
-}
-
-void halvor_bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P2, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO (b/153705222): Need to implement three USB-C function */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO (b/153705222): Check FW_CONFIG for USB DB options */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C2,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C2,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.next_mux = &usbc2_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-	[USBC_PORT_C2] = {
-		.usb_ls_en_gpio = GPIO_USB_C2_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C2_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_usb_chip_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_usb_chip_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-	if (!gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_2;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
-}
diff --git a/board/halvor/board.h b/board/halvor/board.h
deleted file mode 100644
index 818b4b79e5..0000000000
--- a/board/halvor/board.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			3
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x42
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0 C1 C2 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_USB_C0_BC12_INT_ODL	GPIO_USB_C0_MIX_INT_ODL
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_USB_C2_BC12_INT_ODL	GPIO_USB_C2_MIX_INT_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-#undef CONFIG_FANS
-#undef CONFIG_VOLUME_BUTTONS
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_BB_RETIMER	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C2		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-#define I2C_PORT_USB_1_MIX	I2C_PORT_USB_BB_RETIMER
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_AEC,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
-
-/* Definition for Halvor USB PD interrupt handlers. */
-void halvor_tcpc_alert_event(enum gpio_signal signal);
-void halvor_ppc_interrupt(enum gpio_signal signal);
-void halvor_bc12_interrupt(enum gpio_signal signal);
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/halvor/build.mk b/board/halvor/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/halvor/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/halvor/ec.tasklist b/board/halvor/ec.tasklist
deleted file mode 100644
index 936a4276e6..0000000000
--- a/board/halvor/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C2, pd_interrupt_handler_task, 2, TASK_STACK_SIZE)
diff --git a/board/halvor/gpio.inc b/board/halvor/gpio.inc
deleted file mode 100644
index fdf9402f27..0000000000
--- a/board/halvor/gpio.inc
+++ /dev/null
@@ -1,183 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-GPIO_INT(USB_C2_TCPC_INT_ODL,	PIN(A, 0), GPIO_INT_BOTH, halvor_tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, halvor_ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, halvor_ppc_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,	PIN(A, 4), GPIO_INT_BOTH, halvor_ppc_interrupt)
-
-GPIO_INT(USB_C0_MIX_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, halvor_bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, halvor_bc12_interrupt)
-GPIO_INT(USB_C2_MIX_INT_ODL,	PIN(6, 1), GPIO_INT_BOTH, halvor_bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-
-/* Unused signals */
-GPIO(EN_PP1050_STG,		PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(CPU_C10_GATE_L,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_PP1050_ST_S0,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,	       PIN(4, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_OUT_HIGH)
-
-/* The EC does not buffer this signal on Halvor. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-UNIMPLEMENTED(EN_PP5000_A)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C0_RT_RST_ODL,        PIN(6, 6), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,        PIN(8, 6), GPIO_ODR_LOW)
-GPIO(USB_C2_RT_RST_ODL,        PIN(9, 6), GPIO_ODR_LOW)
-
-GPIO(USB_C0_OC_ODL,            PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,            PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C2_OC_ODL,            PIN(3, 2), GPIO_ODR_HIGH)
-
-
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-UNIMPLEMENTED(USB_C2_LS_EN)
-UNIMPLEMENTED(USB_C0_BC12_INT_ODL)
-UNIMPLEMENTED(USB_C1_BC12_INT_ODL)
-
-/* Other input pins */
-GPIO(CCD_MODE_ODL,		PIN(E, 5),  GPIO_INPUT)
-GPIO(EC_PROCHOT_IN_L,		PIN(F, 0),  GPIO_INPUT)
-GPIO(CHARGER_INT_L,		PIN(7, 3),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_PPEXT_EN1,		PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_I2CBUFFER_EN,		PIN(9, 3), GPIO_OUT_LOW)
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)
-
-/* LED Signals */
-GPIO(LED_1_L,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(LED_2_L,		PIN(C, 3), GPIO_OUT_LOW)
-
-/* Misc Signals */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_0_SCL,       PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_0_SDA,       PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_1_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_1_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_2_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_2_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_3_SCL,       PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_3_SDA,       PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_4_SCL,       PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_4_SDA,       PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_5_SCL,       PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_5_SDA,       PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_7_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_7_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-GPIO(USB_C2_DP_HPD,		PIN(B, 7), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, 0)                            /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14-15 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/halvor/led.c b/board/halvor/led.c
deleted file mode 100644
index 1e25e3e666..0000000000
--- a/board/halvor/led.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Halvor
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 1
-#define LED_OFF_LVL 0
-
-__override const int led_charge_lvl_1 = 10;
-
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{LED_OFF,	     2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	gpio_set_level(GPIO_LED_2_L,
-		(color == EC_LED_COLOR_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	gpio_set_level(GPIO_LED_1_L,
-		(color == EC_LED_COLOR_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED)
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	else if (led_id == EC_LED_ID_POWER_LED)
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/halvor/sensors.c b/board/halvor/sensors.c
deleted file mode 100644
index b2795ee904..0000000000
--- a/board/halvor/sensors.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-/* TODO: b/146144170 - the accelerometer is on the motherboard for proto1
- * for testing. Once the sensor moves to the lid, the rotation matrix needs
- * to be updated for correct behavior.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/halvor/vif_override.xml b/board/halvor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/halvor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/hammer/analyzestack.yaml b/board/hammer/analyzestack.yaml
deleted file mode 100644
index 1294546b17..0000000000
--- a/board/hammer/analyzestack.yaml
+++ /dev/null
@@ -1,96 +0,0 @@
-# Size of extra stack frame needed by exception context switch.
-exception_frame_size: 64
-# Add some missing calls.
-add:
-  # usb_ep_event: grep ep_._evt -A 1 build/hammer/RW/ec.RW.smap
-  usb_reset[chip/stm32/usb.c:370]:
-    - hid_touchpad_event
-    - hid_keyboard_event
-    - usb_update_ep_event
-    - i2c_usb__ep_event
-  usb_interrupt_handle_wake[chip/stm32/usb.c:608]:
-    - hid_touchpad_event
-    - hid_keyboard_event
-    - usb_update_ep_event
-    - i2c_usb__ep_event
-  # usb_ep_tx/rx: grep ep_._[rt]x -B 1 -A 1 build/hammer/RW/ec.RW.smap
-  usb_interrupt[chip/stm32/usb.c:640]:
-    - ep0_rx
-    - hid_keyboard_rx
-    - usb_update_ep_rx
-    - i2c_usb__ep_rx
-    - ep0_tx
-    - hid_touchpad_tx
-    - hid_keyboard_tx
-    - usb_update_ep_tx
-    - i2c_usb__ep_tx
-  # usb_interface_request
-  ep0_tx[chip/stm32/usb.c:337]:
-    - hid_touchpad_iface_request
-    - hid_keyboard_iface_request
-  ep0_rx[chip/stm32/usb.c:193]:
-    - hid_touchpad_iface_request
-    - hid_keyboard_iface_request
-  # Queue functions
-  queue_advance_tail[common/queue.c:116]:
-    - queue_add_direct
-  queue_add_memcpy[common/queue.c:152]:
-    - memcpy
-  queue_add_memcpy[common/queue.c:157]:
-    - memcpy
-  queue_read_safe.lto_priv.98[common/queue.c:174]:
-    - memcpy
-  queue_read_safe.lto_priv.98[common/queue.c:179]:
-    - memcpy
-  queue_advance_head[common/queue.c:105]:
-    - queue_remove_direct
-  queue_add_direct[common/queue_policies.c:18]:
-    - usb_i2c_written
-    - usb_written
-    - update_out_handler
-  queue_remove_direct[common/queue_policies.c:27]:
-    - usb_read
-  vfnprintf:
-    # This covers all the addchar in vfnprintf, but stackanalyzer does not
-    # realize that...
-    - __tx_char
-#  gpio_interrupt[chip/stm32/gpio.c:146]:
-#  TODO: All GPIO interrupt handlers should follow here
-  handle_command[common/console.c:248]:
-    - { name: __cmds, stride: 16, offset: 4 }
-  hook_task[common/hooks.c:197]:
-    - { name: __deferred_funcs, stride: 4, offset: 0 }
-    - { name: __hooks_second, stride: 8, offset: 0 }
-    - { name: __hooks_tick, stride: 8, offset: 0 }
-  # Note: This assumes worse case, where all hook functions can be called from
-  # any hook_notify call
-  hook_notify[common/hooks.c:127]:
-    - { name: __hooks_pre_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_pre_init, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_resume, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_startup, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_suspend, stride: 8, offset: 0 }
-    - { name: __hooks_sysjump, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_shutdown, stride: 8, offset: 0 }
-    - { name: __hooks_ac_change, stride: 8, offset: 0 }
-    - { name: __hooks_battery_soc_change, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_reset, stride: 8, offset: 0 }
-    - { name: __hooks_lid_change, stride: 8, offset: 0 }
-    - { name: __hooks_pwrbtn_change, stride: 8, offset: 0 }
-    - { name: __hooks_tablet_mode_change, stride: 8, offset: 0 }
-    - { name: __hooks_usb_change, stride: 8, offset: 0 }
-  jump_to_image.lto_priv.135[common/system.c:568]:
-    - None
-  irq_4_handler[core/cortex-m0/init.S:165]:
-    - exception_panic
-remove:
-  - panic_assert_fail
-  - [queue_add_direct, update_out_handler, [queue_add_unit, queue_add_memcpy], queue_add_direct, update_out_handler]
-  # set_touchpad_report/keyboard_state_changed add elements to a queue, but
-  # _not_ the queue that would call update_out handler
-  - [ touchpad_task, queue_add_unit, queue_add_direct, update_out_handler]
-  - [ keyboard_scan_task, queue_add_unit, queue_add_direct, update_out_handler]
-  # keyboard_raw_drive_column can't recurse more than once
-  - [keyboard_raw_drive_column, keyboard_raw_drive_column, keyboard_raw_drive_column]
-  - [system_common_shutdown, system_run_image_copy, jump_to_image.lto_priv.135, hook_notify, system_common_shutdown]
diff --git a/board/hammer/battery.c b/board/hammer/battery.c
deleted file mode 100644
index 4025a08b14..0000000000
--- a/board/hammer/battery.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "util.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA        0x0010
-
-static const struct battery_info info = {
-	.voltage_max = 8800,
-	.voltage_normal = 7700,
-	.voltage_min = 6000,
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
-
-/* TODO(b:66575472): Do we need to define functions like battery_is_present? */
diff --git a/board/hammer/board.c b/board/hammer/board.c
deleted file mode 100644
index b68498acfb..0000000000
--- a/board/hammer/board.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Hammer board configuration */
-
-#include "charger.h"
-#include "clock.h"
-#include "common.h"
-#include "driver/charger/isl923x.h"
-#include "driver/led/lm3630a.h"
-#include "ec_version.h"
-#include "ec_ec_comm_server.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "printf.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "rollback.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "touchpad.h"
-#include "timer.h"
-#include "update_fw.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_i2c.h"
-#include "usb_spi.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-#ifdef SECTION_IS_RW
-#define CROS_EC_SECTION "RW"
-#else
-#define CROS_EC_SECTION "RO"
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Hammer"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-#ifdef CONFIG_USB_ISOCHRONOUS
-	[USB_STR_HEATMAP_NAME] = USB_STRING_DESC("Heatmap"),
-#endif
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-#ifdef SECTION_IS_RW
-#ifdef HAS_SPI_TOUCHPAD
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	[SPI_ST_TP_DEVICE_ID] = { CONFIG_SPI_TOUCHPAD_PORT, 2, GPIO_SPI1_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-USB_SPI_CONFIG(usb_spi, USB_IFACE_I2C_SPI, USB_EP_I2C_SPI, 0);
-/* SPI interface is always enabled, no need to do anything. */
-void usb_spi_board_enable(struct usb_spi_config const *config) {}
-void usb_spi_board_disable(struct usb_spi_config const *config) {}
-#endif  /* !HAS_SPI_TOUCHPAD */
-
-#ifdef CONFIG_I2C
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 400,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-#ifdef BOARD_WAND
-	{"charger", I2C_PORT_CHARGER, 100,
-		GPIO_CHARGER_I2C_SCL, GPIO_CHARGER_I2C_SDA},
-#endif
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-#endif
-
-#ifdef CONFIG_CHARGER_ISL9238
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-#endif
-
-#ifdef HAS_BACKLIGHT
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-#endif /* HAS_BACKLIGHT */
-
-int usb_i2c_board_is_enabled(void)
-{
-	/* Disable I2C passthrough when the system is locked */
-	return !system_is_locked();
-}
-
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 50,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-#endif
-
-#if defined(BOARD_WAND) && defined(SECTION_IS_RW)
-struct consumer const ec_ec_usart_consumer;
-static struct usart_config const ec_ec_usart;
-
-struct queue const ec_ec_comm_server_input = QUEUE_DIRECT(64, uint8_t,
-				ec_ec_usart.producer, ec_ec_usart_consumer);
-struct queue const ec_ec_comm_server_output = QUEUE_DIRECT(64, uint8_t,
-				null_producer, ec_ec_usart.consumer);
-
-struct consumer const ec_ec_usart_consumer = {
-	.queue = &ec_ec_comm_server_input,
-	.ops   = &((struct consumer_ops const) {
-		.written = ec_ec_comm_server_written,
-	}),
-};
-
-static struct usart_config const ec_ec_usart =
-	USART_CONFIG(EC_EC_UART,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		USART_CONFIG_FLAG_HDSEL,
-		ec_ec_comm_server_input,
-		ec_ec_comm_server_output);
-#endif /* BOARD_WAND && SECTION_IS_RW */
-
-/******************************************************************************
- * Initialize board.
- */
-static int has_keyboard_backlight;
-
-#ifdef SECTION_IS_RW
-static void board_init(void)
-{
-#ifdef HAS_BACKLIGHT
-	/* Detect keyboard backlight: pull-down means it is present. */
-	has_keyboard_backlight = !gpio_get_level(GPIO_KEYBOARD_BACKLIGHT);
-
-	CPRINTS("Backlight%s present", has_keyboard_backlight ? "" : " not");
-#endif /* HAS_BACKLIGHT */
-
-#ifdef BOARD_WAND
-	/* USB to serial queues */
-	queue_init(&ec_ec_comm_server_input);
-	queue_init(&ec_ec_comm_server_output);
-
-	/* UART init */
-	usart_init(&ec_ec_usart);
-#endif /* BOARD_WAND */
-
-#ifdef CONFIG_LED_DRIVER_LM3630A
-	lm3630a_poweron();
-#endif
-
-#ifdef HAS_SPI_TOUCHPAD
-	spi_enable(&spi_devices[SPI_ST_TP_DEVICE_ID], 0);
-
-	/* Disable SPI passthrough when the system is locked */
-	usb_spi_enable(&usb_spi, system_is_locked());
-
-	/* Set all four SPI pins to high speed */
-	/* pins B3/5, A15 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000cc0;
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xc0000000;
-
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1;
-	STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1;
-	/* Enable clocks to SPI1 module */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* Enable SPI for touchpad */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	spi_enable(&spi_devices[SPI_ST_TP_DEVICE_ID], 1);
-#endif /* HAS_SPI_TOUCHPAD */
-}
-/* This needs to happen before PWM is initialized. */
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_PWM - 1);
-#endif /* SECTION_IS_RW */
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-
-	/* Remap USART DMA to match the USART driver */
-	/*
-	 * the DMA mapping is :
-	 *  Chan 4 : USART1_TX
-	 *  Chan 5 : USART1_RX
-	 */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
-}
-
-int board_has_keyboard_backlight(void)
-{
-	return has_keyboard_backlight;
-}
-
-#ifndef HAS_NO_TOUCHPAD
-/* Reset the touchpad, mainly used to recover it from malfunction. */
-void board_touchpad_reset(void)
-{
-#ifdef HAS_EN_PP3300_TP_ACTIVE_HIGH
-	gpio_set_level(GPIO_EN_PP3300_TP, 0);
-	msleep(100);
-	gpio_set_level(GPIO_EN_PP3300_TP, 1);
-	msleep(100);
-#else
-	gpio_set_level(GPIO_EN_PP3300_TP_ODL, 1);
-	msleep(10);
-	gpio_set_level(GPIO_EN_PP3300_TP_ODL, 0);
-	msleep(10);
-#endif
-}
-#endif /* !HAS_NO_TOUCHPAD */
-
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-static void board_tablet_mode_change(void)
-{
-	/*
-	 * Turn off key scanning in tablet mode.
-	 */
-	if (tablet_get_mode())
-		keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	else
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-}
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, board_tablet_mode_change,
-		HOOK_PRIO_DEFAULT);
-/* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT+1);
-#endif
-
-/*
- * Get entropy based on Clock Recovery System, which is enabled on hammer to
- * synchronize USB SOF with internal oscillator.
- */
-int board_get_entropy(void *buffer, int len)
-{
-	int i = 0;
-	uint8_t *data = buffer;
-	uint32_t start;
-	/* We expect one SOF per ms, so wait at most 2ms. */
-	const uint32_t timeout = 2*MSEC;
-
-	for (i = 0; i < len; i++) {
-		STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC;
-		start = __hw_clock_source_read();
-		while (!(STM32_CRS_ISR & STM32_CRS_ISR_SYNCOKF)) {
-			if ((__hw_clock_source_read() - start) > timeout)
-				return 0;
-			usleep(500);
-		}
-		/* Pick 8 bits, including FEDIR and 7 LSB of FECAP. */
-		data[i] = STM32_CRS_ISR >> 15;
-	}
-
-	return 1;
-}
-
-/*
- * Generate a USB serial number from unique chip ID.
- */
-__override const char *board_read_serial(void)
-{
-	static char str[CONFIG_SERIALNO_LEN];
-
-	if (str[0] == '\0') {
-		uint8_t *id;
-		int pos = 0;
-		int idlen = system_get_chip_unique_id(&id);
-		int i;
-
-		for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) {
-			snprintf(&str[pos], sizeof(str)-pos,
-				"%02x", id[i]);
-		}
-	}
-
-	return str;
-}
-
-__override int board_write_serial(const char *serialno)
-{
-	return 0;
-}
-
-static const struct ec_response_keybd_config zed_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,
-		TK_REFRESH,
-		TK_FULLSCREEN,
-		TK_OVERVIEW,
-		TK_SNAPSHOT,
-		TK_BRIGHTNESS_DOWN,
-		TK_BRIGHTNESS_UP,
-		TK_VOL_MUTE,
-		TK_VOL_DOWN,
-		TK_VOL_UP,
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config bland_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,
-		TK_REFRESH,
-		TK_FULLSCREEN,
-		TK_OVERVIEW,
-		TK_BRIGHTNESS_DOWN,
-		TK_BRIGHTNESS_UP,
-		TK_MICMUTE,
-		TK_VOL_MUTE,
-		TK_VOL_DOWN,
-		TK_VOL_UP,
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
-{
-	if (IS_ENABLED(BOARD_ZED) || IS_ENABLED(BOARD_STAR))
-		return &zed_kb;
-	if (IS_ENABLED(BOARD_BLAND) || IS_ENABLED(BOARD_EEL))
-		return &bland_kb;
-
-	return NULL;
-}
diff --git a/board/hammer/board.h b/board/hammer/board.h
deleted file mode 100644
index 3282425d9e..0000000000
--- a/board/hammer/board.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hammer configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "variants.h"
-
-/* TODO: Remove CONFIG_SYSTEM_UNLOCKED prior to building MP FW. */
-#define CONFIG_SYSTEM_UNLOCKED
-/* TODO(b:63378217): Define FLASH_PSTATE_LOCKED prior to building MP FW. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/*
- * Flash layout: we redefine the sections offsets and sizes as we want to
- * include a rollback region, and will use RO/RW regions of different sizes.
- */
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_FLASH_PSTATE
-/* Do not use a dedicated PSTATE bank */
-#undef CONFIG_FLASH_PSTATE_BANK
-
-#define CONFIG_SHAREDLIB_SIZE	0
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(44*1024)
-
-/* EC rollback protection block */
-#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* The UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-/*
- * TODO(b:65697962): Reenable low-power-idle on wand without breaking EC-EC
- * communication
- */
-#ifndef BOARD_WAND
-#define CONFIG_LOW_POWER_IDLE
-#endif
-#define CONFIG_LTO
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_MATH_UTIL
-#define CONFIG_STM_HWTIMER32
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_STREAM_USB
-#define CONFIG_USB_UPDATE
-
-#undef CONFIG_UPDATE_PDU_SIZE
-#if defined(BOARD_WAND) || defined(BOARD_ZED)
-/* Wand/Zed does not have enough space to fit 4k PDU. */
-#define CONFIG_UPDATE_PDU_SIZE 2048
-#else
-#define CONFIG_UPDATE_PDU_SIZE 4096
-#endif
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 100
-
-#define CONFIG_USB_REMOTE_WAKEUP
-#define CONFIG_USB_SUSPEND
-
-#define CONFIG_USB_SERIALNO
-/* Replaced at runtime (board_read_serial) by chip unique-id-based number. */
-#define DEFAULT_SERIALNO ""
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#ifdef SECTION_IS_RW
-#define USB_IFACE_HID_KEYBOARD	0
-#define USB_IFACE_UPDATE	1
-#ifdef HAS_NO_TOUCHPAD
-#define USB_IFACE_COUNT		2
-#else /* !HAS_NO_TOUCHPAD */
-#define USB_IFACE_HID_TOUCHPAD	2
-/* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_IFACE_I2C_SPI	3
-#if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_IFACE_ST_TOUCHPAD	4
-#define USB_IFACE_COUNT		5
-#else  /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_IFACE_COUNT		4
-#endif  /* CONFIG_USB_ISOCHRONOUS */
-#endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_IFACE_UPDATE	0
-#define USB_IFACE_COUNT		1
-#endif  /* SECTION_IS_RW */
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
-#ifdef SECTION_IS_RW
-#define USB_EP_HID_KEYBOARD	2
-#ifdef HAS_NO_TOUCHPAD
-#define USB_EP_COUNT		3
-#else /* !HAS_NO_TOUCHPAD */
-#define USB_EP_HID_TOUCHPAD	3
-/* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_EP_I2C_SPI		4
-#if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_EP_ST_TOUCHPAD	5
-#define USB_EP_ST_TOUCHPAD_INT	6
-#define USB_EP_COUNT		7
-#else /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_EP_COUNT		5
-#endif /* CONFIG_USB_ISOCHRONOUS */
-#endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_EP_COUNT		2
-#endif  /* SECTION_IS_RW */
-
-/* Optional features */
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_WATCHDOG_HELP
-
-/* No need to hibernate, remove console commands that are not very useful. */
-#undef CONFIG_HIBERNATE
-#undef CONFIG_CONSOLE_CHANNEL
-#undef CONFIG_CONSOLE_HISTORY
-#undef CONFIG_CMD_GETTIME
-#undef CONFIG_CMD_MD
-#undef CONFIG_CMD_RW
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_CMD_WAITMS
-
-/*
- * Enlarge the allowed write / read count for trackpad debug
- * In the extended I2C reading over I2C ( >= 128 bytes ), the header size
- * have to be 6 bytes instead of 4 bytes for receiving packets. Moreover,
- * buffer size have to be power of two.
- */
-#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
-#ifdef BOARD_ZED
-/* Zed requires 516 byte per packet for touchpad update */
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT (1024 - 4) /* 4 is maximum header size */
-#else
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size */
-#endif
-
-#undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size */
-
-#define CONFIG_I2C_XFER_LARGE_TRANSFER
-
-/* No lid switch */
-#undef CONFIG_LID_SWITCH
-
-#ifdef SECTION_IS_RW
-#define CONFIG_USB_HID
-#define CONFIG_USB_HID_KEYBOARD
-#ifdef HAS_BACKLIGHT
-#define CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-#endif
-
-#ifndef HAS_NO_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD
-
-/* Virtual address for touchpad FW in USB updater. */
-#define CONFIG_TOUCHPAD_VIRTUAL_OFF	0x80000000
-
-/* Include touchpad FW hashes in image */
-#define CONFIG_TOUCHPAD_HASH_FW
-#endif /* !HAS_NO_TOUCHPAD */
-
-#define CONFIG_KEYBOARD_DEBUG
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-/* Keyboard output port list */
-#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_F
-
-#if defined(HAS_I2C_TOUCHPAD) || defined(CONFIG_LED_DRIVER_LM3630A)
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 0
-#define I2C_PORT_KBLIGHT 0
-#define I2C_PORT_CHARGER 1
-#endif
-
-/* Enable PWM */
-#ifdef HAS_BACKLIGHT
-#define CONFIG_PWM
-#endif
-
-#ifdef CONFIG_GMR_TABLET_MODE
-#define CONFIG_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#define CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#endif
-
-#ifdef HAS_SPI_TOUCHPAD
-/* Enable control of SPI over USB */
-#define CONFIG_USB_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_HALFDUPLEX
-#define CONFIG_STM32_SPI1_CONTROLLER
-#define CONFIG_SPI_TOUCHPAD_PORT 0
-#define SPI_ST_TP_DEVICE_ID 0
-/* Enable SPI controller xfer command */
-#define CONFIG_CMD_SPI_XFER
-#define CONFIG_TOUCHPAD
-#define CONFIG_TOUCHPAD_ST
-#elif defined(HAS_I2C_TOUCHPAD) /* HAS_SPI_TOUCHPAD */
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define USB_IFACE_I2C USB_IFACE_I2C_SPI
-#define USB_EP_I2C USB_EP_I2C_SPI
-/* Enable Elan touchpad driver */
-#define CONFIG_TOUCHPAD
-#define CONFIG_TOUCHPAD_ELAN
-#define CONFIG_TOUCHPAD_I2C_PORT I2C_PORT_MASTER
-#define CONFIG_TOUCHPAD_I2C_ADDR_FLAGS 0x15
-#endif /* HAS_I2C_TOUCHPAD */
-
-#define CONFIG_CURVE25519
-
-#define CONFIG_USB_PAIRING
-
-#define CONFIG_USB_CONSOLE_READ
-
-#ifdef BOARD_WAND
-/* Battery and charger options. */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_INPUT_CURRENT 128
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_OTG
-
-#define CONFIG_CHARGE_RAMP_HW
-
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_SMART
-
-#define I2C_PORT_BATTERY I2C_PORT_CHARGER
-
-#define EC_EC_UART usart2_hw
-#define CONFIG_STREAM_USART2
-#define CONFIG_STREAM_USART
-
-#define CONFIG_EC_EC_COMM_SERVER
-#define CONFIG_EC_EC_COMM_BATTERY
-#define CONFIG_CRC8
-#endif /* BOARD_WAND */
-
-#else /* SECTION_IS_RO */
-/* Sign and switch to RW partition on boot. */
-#define CONFIG_RWSIG
-#define CONFIG_RSA
-#endif
-
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-
-#define CONFIG_SHA256
-#ifdef SECTION_IS_RO
-#define CONFIG_SHA256_UNROLLED
-#endif
-
-#define CONFIG_RWSIG_TYPE_RWSIG
-
-/*
- * Add rollback protection, and independent RW region protection.
- */
-#define CONFIG_ROLLBACK
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-#define CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE 32
-#define CONFIG_FLASH_PROTECT_RW
-#ifdef SECTION_IS_RW
-#undef CONFIG_ROLLBACK_UPDATE
-#endif
-
-/* Maximum current to draw. */
-#define MAX_CURRENT_MA			2000
-/* Maximum current/voltage to provide over OTG. */
-#define MAX_OTG_CURRENT_MA		2000
-#define MAX_OTG_VOLTAGE_MV		20000
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 16
-#define TIM_KBLIGHT 17
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_UPDATE_NAME,
-#ifdef CONFIG_USB_ISOCHRONOUS
-	USB_STR_HEATMAP_NAME,
-#endif
-	USB_STR_COUNT
-};
-
-#ifdef SECTION_IS_RW
-#ifdef HAS_BACKLIGHT
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-#endif /* HAS_BACKLIGHT */
-
-enum adc_channel {
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-#endif /* SECTION_IS_RW */
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hammer/build.mk b/board/hammer/build.mk
deleted file mode 100644
index b32a6b768a..0000000000
--- a/board/hammer/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Build tests that we care about for hammer
-test-list-y=entropy rsa3 sha256 sha256_unrolled x25519
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/hammer/dev_key.pem b/board/hammer/dev_key.pem
deleted file mode 100644
index b72c787613..0000000000
--- a/board/hammer/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4gIBAAKCAYEAseZZZlXXDP+KrjqV+XhP0ZgPlU5mX4GCm27yzTqcKiFWLlHZ
-3f8seGG0lKNiL7WvHim8uSEDaPbp2us4uaJ6nTHEpbSGi2QVp90tE3aJG34HyKlg
-jcaE1r/0n6ynG/bf0Xx4O63Plp3Czi3TBYW49vT6+T/Jyfl2JpGQ9KNcD0umafsv
-uaEmdrLGrzjN8w1mFZfwscFkfVDh0cdiFNJ+UkTSpO9/yPapXbo4/lOMwdO9xILF
-cEZV9I7K7lBSvQ5Uep+w0SqNPTh2cGhoeEeDyH+Ce0LA8H7ZwbVnwLe1RswF9Wek
-uzqp9lMSNkkwMtTkumTuJLLGJX9rc0MVQTKgNV8wIzizf5lkCCBCJLf7aRBaeWCJ
-cXjKiavSPOZXDcnqCWqRJT3jN4ibAsU1GQtqLa8pTAi2wkE0fjuvAWK3NYuvpukg
-qNq2LI+BJkF4+dCZoeB1PDNyFNzdOFvkxj2+ImS3DLlPYVng4vHsTK1HRUUpL5Ag
-jjfMhMs4NC7HMOCTAgEDAoIBgHaZkO7j5LNVBx7RuVD63+EQCmOJmZUBAbz0od4n
-EsbA5B7hO+lUyFBBIw3CQXUjyhQb0yYWAkX58Tyc0HvBpxN2gxkjBFztY8U+Hgz5
-sLz+r9sblbPZreR/+GpzGhKklTZS+tJz37m+gd7JN1kD0KSjUft/29v7pBm2YKMX
-krTdGZv8ynvAxE8h2col3qII7rkP9cvWQv416+EvlriMVDbYjG30/9tPG5PRe1Q3
-syvifoMB2PWEOU20h0mK4dNe4d7E96s1Q+RTmTUtyipxUp6d4PIufAjMtM8yfkb0
-/0z81IsWQ0NOhefrMAi8TEcDkbyNSBPqHqbqH2FosFWo2cU3r6TXv2LdvFzc5BA+
-U6c+fXz7BDjv+NT3Bh98whKvTdJYcIgSg6vqzW7ZWJWWllZQtpJnQccIq4sPaL4S
-osFg8jd1kcbjVakCN0wYtfvMa/+WBZNNsZLUHoeIJvO7qnT7VKzhceoKHCJCMxNR
-Ypu5eELxCwebTXiImDqmFsKIawKBwQDpDjff6eatHbjmGV1elTyV5MLi95Tc0T7P
-FZHC1KLXkA/mEuXjAGfoZuLB5a3WmrA8r8fWNZoKV+0RBKIs3at1JFxZn9YiA0Hy
-5qmnYkXjMaY4p5AyO3eJsc2kbsh9r0cy2cb5GdwFDApeoVICoQh+dW9FpvIS+9AF
-0DVc2/Rg//cuXLlCMonF+PZVmDxRNhjBvwvRjxeowiu2ntI4sa83nHMhXI/RfvV4
-xcSng8gSIvabUmunDcPKvqO3rnpHzVECgcEAw2oFcHDAuZ1Xuopb2ghLRK3uLQVy
-BnqLu9QYk3OTe8C3PrNZ80R5MgtnZ0kP8bTZ4uE6MJ3+IMhPUCFqk9euGGdMUlU+
-SUmHie5CZPg4CwD4BUBy6dVdwId7aTxrdBOuGwwhYAhBsJxcfd3eNgiALcCoKsbi
-BLhjJ9Rch2rOsnpNJVwMvFMr6RM33oQrrufe4MBhDa/QD9yDtnDYH/KPO09E6AqU
-sMvBNsjbCC9rSYv+L9QkW8EUhT+wJIcqxUajAoHBAJtez+qb7x4T0JlmPj8OKGPt
-10H6Yz3g1IoOYSyNweUKtUQMmUIARUWZ7IFDyTm8dX3KhTl5EVw6ngtYbB3pHPjC
-6Du/5Bas1qHvG8TsLpd2btBvtXbST7EhM8L0hakfhMyRL1C76ANdXD8WNqxrWv74
-9NkZ9rdSiq6Kzj3n+ECqpMmTJiwhsS6l+Y5lfYt5ZdZ/XTZfZRssHSRp4XshH3po
-TMDoX+D/TlCD2G+tMAwXTxI28m9egocpwnp0UYUziwKBwQCCRq5K9dXRE4/RsZKR
-WtzYc/QeA6FZpwfSjWW3omJSgHopzOaiLaYhXO+aMLVLzeaXQNF1vqlrMDTgFkcN
-OnQQRN2MONQw26+xSYGYpXqyAKVY1aHxOOkrBPzw0vJNYnQSCBZABYEgaD2pPpQk
-BarJKxrHL0FYeuzFOD2vnInMUYjDkrMoN3KbYiU/AsfJ7+nrKutedTVf6FfO9eVq
-obTSNNiasbh13St52zywH5zbsql1OBg9K2MDf8rDBMcuLxcCgcBfM9FWZivdG2tJ
-5REvL0vPAQfcjVi4HUHvnaCuwMYEuF5T2Xf9P8d8ZflfWHaGlkl/qPvE897fns2l
-PZvvhRnr9GlHKt940ZOTI2v+hjlwcHGAAQc+p7BcKeUYLChwhVK/cZ9f6ZCotZNh
-543ecG4KZiJaqBZ/mDRaW7Py0w6lbOAzprrHF3ChvQ6VAllajoWx4CeINRcxX2vP
-bAPZxvt0gwpoHtUAsZo/bKEF0sM5qM/fK43gH5KhJeunq/xHO7E=
------END RSA PRIVATE KEY-----
diff --git a/board/hammer/ec.tasklist b/board/hammer/ec.tasklist
deleted file mode 100644
index b568619065..0000000000
--- a/board/hammer/ec.tasklist
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#ifdef BOARD_WAND
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS   (HOOKS,    hook_task,    NULL, 2048) \
-	TASK_ALWAYS_RW(TOUCHPAD, touchpad_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(CHARGER,  charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024) \
-	TASK_ALWAYS_RW(ECCOMM,   ec_ec_comm_server_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST_RW(KEYSCAN,  keyboard_scan_task, NULL, TASK_STACK_SIZE)
-#elif defined(CONFIG_USB_ISOCHRONOUS)
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS   (HOOKS,    hook_task,    NULL, 2048) \
-	TASK_ALWAYS_RW(TOUCHPAD, touchpad_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(HEATMAP,  heatmap_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024) \
-	TASK_NOTEST_RW(KEYSCAN,  keyboard_scan_task, NULL, TASK_STACK_SIZE)
-#elif !defined(HAS_NO_TOUCHPAD)
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS   (HOOKS,    hook_task,    NULL, 2048) \
-	TASK_ALWAYS_RW(TOUCHPAD, touchpad_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024) \
-	TASK_NOTEST_RW(KEYSCAN,  keyboard_scan_task, NULL, TASK_STACK_SIZE)
-#else
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS   (HOOKS,    hook_task,    NULL, 2048) \
-	TASK_ALWAYS   (CONSOLE,  console_task, NULL, 1024) \
-	TASK_NOTEST_RW(KEYSCAN,  keyboard_scan_task, NULL, TASK_STACK_SIZE)
-#endif
diff --git a/board/hammer/gpio.inc b/board/hammer/gpio.inc
deleted file mode 100644
index 8372d4fc4b..0000000000
--- a/board/hammer/gpio.inc
+++ /dev/null
@@ -1,138 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#ifdef SECTION_IS_RW
-#ifndef HAS_NO_TOUCHPAD
-GPIO_INT(TOUCHPAD_INT, PIN(B, 8), GPIO_INT_FALLING, touchpad_interrupt)
-#endif /* !HAS_NO_TOUCHPAD */
-#ifdef CONFIG_GMR_TABLET_MODE
-GPIO_INT(TABLET_MODE_L, PIN(B, 11), GPIO_PULL_UP | GPIO_INT_BOTH, gmr_tablet_switch_isr)
-#endif /* CONFIG_GMR_TABLET_MODE */
-#endif /* SECTION_IS_RW */
-
-/* Keyboard inputs */
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-#ifdef BOARD_MASTERBALL
-GPIO_INT(KB_IN00, PIN(B, 2),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN01, PIN(B, 13), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN02, PIN(B, 1),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN03, PIN(A, 6),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN04, PIN(B, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN05, PIN(B, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN06, PIN(A, 7),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN07, PIN(B, 0),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-
-/* Do not forget to update KB_OUT_PORT_LIST to match this. */
-GPIO(KB_OUT00,			PIN(C, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,			PIN(C, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,			PIN(A, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT03,			PIN(A, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,			PIN(F, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,			PIN(A, 3),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,			PIN(A, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,			PIN(F, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,			PIN(A, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,			PIN(A, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,			PIN(B, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,			PIN(B, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,			PIN(A, 8),  GPIO_KB_OUTPUT)
-#else /* !BOARD_MASTERBALL */
-GPIO_INT(KB_IN00, PIN(A, 4),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-#ifdef BOARD_WHISKERS
-GPIO_INT(KB_IN01, PIN(B, 10),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-#else
-GPIO_INT(KB_IN01, PIN(B, 3),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-#endif
-GPIO_INT(KB_IN02, PIN(B, 0),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN03, PIN(A, 7),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN04, PIN(B, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN05, PIN(B, 2),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN06, PIN(B, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN07, PIN(B, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-
-/* Do not forget to update KB_OUT_PORT_LIST to match this. */
-GPIO(KB_OUT00,			PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,			PIN(A, 5),  GPIO_KB_OUTPUT)
-#ifdef BOARD_WAND
-GPIO(KB_OUT02,			PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT03,			PIN(B, 4),  GPIO_KB_OUTPUT)
-#else
-GPIO(KB_OUT02,			PIN(A, 3),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT03,			PIN(A, 2),  GPIO_KB_OUTPUT)
-#endif
-GPIO(KB_OUT04,			PIN(A, 6),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,			PIN(A, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,			PIN(A, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,			PIN(B, 13), GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,			PIN(C, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,			PIN(C, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,			PIN(F, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,			PIN(F, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,			PIN(C, 13), GPIO_KB_OUTPUT)
-#endif /* !BOARD_MASTERBALL */
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(MASTER_I2C_SCL,		PIN(B, 6), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,		PIN(B, 7), GPIO_INPUT)
-#ifndef HAS_NO_TOUCHPAD
-/* TODO(crosbug.com/p/59083): Disable trackpad when appropriate */
-#ifdef HAS_EN_PP3300_TP_ACTIVE_HIGH
-GPIO(EN_PP3300_TP,		PIN(A, 14), GPIO_OUT_HIGH)
-#else
-GPIO(EN_PP3300_TP_ODL,		PIN(A, 14), GPIO_OUT_LOW)
-#endif
-#endif /* !HAS_NO_TOUCHPAD */
-
-#ifdef HAS_BACKLIGHT
-GPIO(KEYBOARD_BACKLIGHT,	PIN(B, 9), GPIO_INPUT)
-#endif
-
-GPIO(WP_L,			PIN(A, 13), GPIO_INPUT | GPIO_PULL_UP)
-
-#ifdef BOARD_WAND
-GPIO(BASE_UART_TX_RX,		PIN(A, 2), GPIO_ODR_HIGH)
-
-GPIO(CHARGER_I2C_SCL,		PIN(B, 10), GPIO_INPUT)
-GPIO(CHARGER_I2C_SDA,		PIN(B, 11), GPIO_INPUT)
-
-GPIO(SWITCH_STATUS,		PIN(A, 15), GPIO_INPUT)
-GPIO(EN_OTG,			PIN(B, 5), GPIO_INPUT)
-#elif defined(BOARD_WHISKERS)
-GPIO(DETECT_PATH_DISABLE_L,	PIN(A, 8), GPIO_ODR_LOW)
-GPIO(SPI1_NSS,			PIN(A, 15), GPIO_OUT_HIGH)
-GPIO(BACKLIGHT_EN,		PIN(B, 4), GPIO_ODR_HIGH | GPIO_PULL_UP)
-#else
-GPIO(BASE_DET,			PIN(A, 15), GPIO_INPUT)
-#endif
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA09/PA10 - Servo stm32 console UART */
-
-#ifdef BOARD_WAND
-ALTERNATE(PIN_MASK(A, 0x0004), 1, MODULE_USART, GPIO_ODR_HIGH) /* USART2: PA2 - EC-EC UART */
-ALTERNATE(PIN_MASK(B, 0x0c00), 1, MODULE_I2C, 0) /* I2C CHARGER: PB10/11  GPIO_ODR_HIGH */
-#endif
-
-#ifdef HAS_SPI_TOUCHPAD
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PB3/4/5 */
-#endif
-
-#ifdef CONFIG_I2C
-ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C TOUCHPAD: PB6/7 GPIO_ODR_HIGH */
-#endif
-
-#ifdef HAS_BACKLIGHT
-ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_PWM, GPIO_PULL_DOWN) /* PWM: PB9 */
-#endif
diff --git a/board/hammer/variants.h b/board/hammer/variants.h
deleted file mode 100644
index 2a8c831ef5..0000000000
--- a/board/hammer/variants.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Hammer variants configuration, there should be no/little BOARD_ checks
- * in the rest of the files. If this grows out of control, we can create
- * variant_*.h files.
- */
-
-#ifndef __CROS_EC_VARIANTS_H
-#define __CROS_EC_VARIANTS_H
-
-/* USB ID */
-#ifdef BOARD_HAMMER
-#define CONFIG_USB_PID 0x5022
-#elif defined(BOARD_BLAND)
-#define CONFIG_USB_PID 0x5056
-#elif defined(BOARD_DON)
-#define CONFIG_USB_PID 0x5050
-#elif defined(BOARD_EEL)
-#define CONFIG_USB_PID 0x5057
-#elif defined(BOARD_MAGNEMITE)
-#define CONFIG_USB_PID 0x503d
-#elif defined(BOARD_MASTERBALL)
-#define CONFIG_USB_PID 0x503c
-#elif defined(BOARD_MOONBALL)
-#define CONFIG_USB_PID 0x5044
-#elif defined(BOARD_STAFF)
-#define CONFIG_USB_PID 0x502b
-#elif defined(BOARD_STAR)
-#define CONFIG_USB_PID 0x5052
-#elif defined(BOARD_WAND)
-#define CONFIG_USB_PID 0x502d
-#elif defined(BOARD_WHISKERS)
-#define CONFIG_USB_PID 0x5030
-#elif defined(BOARD_ZED)
-#define CONFIG_USB_PID 0x504c
-#else
-#error "Invalid board"
-#endif
-
-#ifdef SECTION_IS_RW
-
-/* Touchpad interface, firmware size and physical dimension. */
-#if defined(BOARD_HAMMER) || defined(BOARD_WAND)
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3207
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1783
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 566 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48*1024)
-#elif defined(BOARD_BLAND)
-#define CONFIG_USB_HID_KEYBOARD_VIVALDI
-#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
-#define HAS_I2C_TOUCHPAD
-/* TODO: update correct parameters */
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3282
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1793
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
-#elif defined(BOARD_DON)
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
-#elif defined(BOARD_EEL)
-#define CONFIG_USB_HID_KEYBOARD_VIVALDI
-#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
-#define HAS_I2C_TOUCHPAD
-/* TODO: update correct parameters */
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3282
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1793
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
-#elif defined(BOARD_MAGNEMITE)
-#define HAS_NO_TOUCHPAD
-#elif defined(BOARD_MASTERBALL)
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2644
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
-#elif defined(BOARD_MOONBALL)
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1440
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
-#elif defined(BOARD_STAFF)
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3206
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1832
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 582 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
-#elif defined(BOARD_STAR)
-#define CONFIG_USB_HID_KEYBOARD_VIVALDI
-#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3282
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1793
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
-#elif defined(BOARD_WHISKERS)
-#define HAS_SPI_TOUCHPAD
-#define HAS_EN_PP3300_TP_ACTIVE_HIGH
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2160
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1573
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 255
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1031 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 751 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128*1024)
-/* Enable to send heatmap to AP */
-#define CONFIG_USB_ISOCHRONOUS
-#elif defined(BOARD_ZED)
-#define CONFIG_USB_HID_KEYBOARD_VIVALDI
-#define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
-
-/* TODO: update correct parameters */
-#define HAS_I2C_TOUCHPAD
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3340
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y 1811
-#define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */
-#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
-#else
-#error "No touchpad information for board."
-#endif
-
-/* Assistant key */
-#if defined(BOARD_HAMMER) || defined(BOARD_WAND) || defined(BOARD_WHISKERS)
-
-#define CONFIG_KEYBOARD_ASSISTANT_KEY
-#endif
-
-/* Backlight */
-#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || \
-    defined(BOARD_WAND) || defined(BOARD_WHISKERS)
-/*
- * Even with this option, we detect the backlight presence using a PU/PD on the
- * PWM pin. Not defining this totally disables support.
- */
-#define HAS_BACKLIGHT
-
-#ifdef BOARD_WHISKERS
-#define CONFIG_LED_DRIVER_LM3630A
-#endif
-
-#ifdef BOARD_STAFF
-#define KBLIGHT_PWM_FREQ 100 /* Hz */
-#else
-#define KBLIGHT_PWM_FREQ 50000 /* Hz */
-#endif
-
-#endif /* BOARD_HAMMER/WAND/WHISKERS */
-
-/* GMR sensor for tablet mode detection */
-#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) || \
-    defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \
-    defined(BOARD_EEL)
-#define CONFIG_GMR_TABLET_MODE
-#endif
-
-#endif /* SECTION_IS_RW */
-
-#endif /* __CROS_EC_VARIANTS_H */
diff --git a/board/hatch/battery.c b/board/hatch/battery.c
deleted file mode 100644
index b81fa795b9..0000000000
--- a/board/hatch/battery.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Hatch battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP LIS Dell FMXMT Battery Information */
-	[BATTERY_SMP_LIS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LIS3.78",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7660, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP SDI Dell FMXMT Battery Information */
-	[BATTERY_SMP_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI-3727",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7660, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_SDI;
diff --git a/board/hatch/board.c b/board/hatch/board.c
deleted file mode 100644
index 75f3b5f6cb..0000000000
--- a/board/hatch/board.c
+++ /dev/null
@@ -1,500 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	baseboard_mst_enable_control(MST_HDMI, gpio_get_level(signal));
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/*
- * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
- * matrix can't be tested properly. This needs to be revisited after EVT to make
- * sure the rotaiton matrix for the lid sensor is correct.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_ALS,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Hatch Temperature sensors */
-/*
- * TODO(b/124316213): These setting need to be reviewed and set appropriately
- * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-/* Sets the gpio flags correct taking into account warm resets */
-static void reset_gpio_flags(enum gpio_signal signal, int flags)
-{
-	/*
-	 * If the system was already on, we cannot set the value otherwise we
-	 * may change the value from the previous image which could cause a
-	 * brownout.
-	 */
-	if (system_is_reboot_warm() || system_jumped_late())
-		flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-	gpio_set_flags(signal, flags);
-}
-
-/* Runtime GPIO defaults */
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A_V1;
-
-static void board_gpio_set_pp5000(void)
-{
-	uint32_t board_id = 0;
-
-	/* Errors will count as board_id 0 */
-	cbi_get_board_version(&board_id);
-
-	if (board_id == 0) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V0, GPIO_OUT_LOW);
-		/* Change runtime default for V0 */
-		gpio_en_pp5000_a = GPIO_EN_PP5000_A_V0;
-	} else if (board_id >= 1) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
-	}
-
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_TCS3400_INT_ODL);
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-	/* Select correct gpio signal for PP5000_A control */
-	board_gpio_set_pp5000();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255);
-}
diff --git a/board/hatch/board.h b/board/hatch/board.h
deleted file mode 100644
index 057475cb55..0000000000
--- a/board/hatch/board.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-/* TC3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_CMD_BUTTON
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-#define GPIO_EN_PP5000_A gpio_en_pp5000_a
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP_LIS,
-	BATTERY_SMP_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hatch/build.mk b/board/hatch/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/hatch/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/hatch/ec.tasklist b/board/hatch/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/hatch/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/hatch/gpio.inc b/board/hatch/gpio.inc
deleted file mode 100644
index cd241f15f5..0000000000
--- a/board/hatch/gpio.inc
+++ /dev/null
@@ -1,134 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-GPIO_INT(TCS3400_INT_ODL,      PIN(F, 1), GPIO_INT_FALLING, tcs3400_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* SYS_RESET_L should be set to GPIOC5 per schematics, but was never built, so leaving as GPIO02 */
-GPIO(SYS_RESET_L,              PIN(0, 2), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A_V1,           PIN(A, 4), GPIO_DEFAULT)
-GPIO(EN_PP5000_A_V0,           PIN(7, 3), GPIO_DEFAULT)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(LED_4_L,                  PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)                             /* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/hatch/led.c b/board/hatch/led.c
deleted file mode 100644
index 1c44d12d89..0000000000
--- a/board/hatch/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Hatch
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/hatch/vif_override.xml b/board/hatch/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/hatch/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/hatch_fp/OWNERS b/board/hatch_fp/OWNERS
deleted file mode 100644
index ba92c193e0..0000000000
--- a/board/hatch_fp/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../common/fpsensor/OWNERS
diff --git a/board/hatch_fp/board.c b/board/hatch_fp/board.c
deleted file mode 100644
index b48dce2b7e..0000000000
--- a/board/hatch_fp/board.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "usart_host_command.h"
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#include "gpio_list.h"
-
-/*
- * Some platforms have a broken SLP_S0_L signal (stuck to 0 in S0)
- * if set, ignore it and only uses SLP_S3_L for the AP state.
- */
-static bool broken_slp;
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is 1 and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
-		      (gpio_get_level(GPIO_SLP_L) || broken_slp);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-static void board_init_transport(void)
-{
-	enum fp_transport_type ret_transport = get_fp_transport_type();
-
-	ccprints("TRANSPORT_SEL: %s", fp_transport_type_to_str(ret_transport));
-
-	/* Initialize transport based on bootstrap */
-	switch (ret_transport) {
-	case FP_TRANSPORT_TYPE_UART:
-		/*
-		 * The Zork variants currently have a broken SLP_S0_L signal
-		 * (stuck to 0 in S0). For now, unconditionally ignore it here
-		 * as they are the only UART users and the AP has no S0ix state.
-		 * TODO(b/174695987) once the RW AP firmware has been updated
-		 * on all those machines, remove this workaround.
-		 */
-		broken_slp = true;
-
-		/* Check if CONFIG_USART_HOST_COMMAND is enabled. */
-		if (IS_ENABLED(CONFIG_USART_HOST_COMMAND))
-			usart_host_command_init();
-		else
-			ccprints("ERROR: UART not supported in fw build.");
-
-		/* Disable SPI interrupt to disable SPI transport layer */
-		gpio_disable_interrupt(GPIO_SPI1_NSS);
-		break;
-
-	case FP_TRANSPORT_TYPE_SPI:
-		/* SPI transport is enabled. SPI1_NSS interrupt will process
-		 * incoming request/
-		 */
-		break;
-	default:
-		ccprints("ERROR: Selected transport is not valid.");
-	}
-
-	ccprints("TRANSPORT_SEL: %s",
-		 fp_transport_type_to_str(get_fp_transport_type()));
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Run until the first S3 entry */
-	disable_sleep(SLEEP_MASK_AP_RUN);
-
-	board_init_transport();
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_SLP_ALT_L);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	if (IS_ENABLED(SECTION_IS_RW))
-		board_init_rw();
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h
deleted file mode 100644
index aa097d8b7e..0000000000
--- a/board/hatch_fp/board.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * STM32F412 + FPC 1025 Fingerprint MCU configuration
- *
- * Alternate names that share this same board file:
- *   hatch_fp
- *   bloonchipper
- *   dragonclaw
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*-------------------------------------------------------------------------*
- * Flash layout:
- *
- * +++++++++++++
- * |    RO     |
- * | ......... |
- * |  Rollback | (two sectors)
- * +-----------+
- * |    RW     |
- * |           |
- * |           |
- * |           |
- * |           |
- * +++++++++++++
- *
- * We adjust the following macros to accommodate a for a rollback, RO,
- * and RW region of different sizes.
- *
- *-------------------------------------------------------------------------*/
-
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-#define CONFIG_SHAREDLIB_SIZE   0
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
-
-/* EC rollback protection block */
-#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * We want to prevent flash readout, and use it as indicator of protection
- * status.
- */
-#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-
-/*-------------------------------------------------------------------------*
- * USART Transport Setup
- *-------------------------------------------------------------------------*/
-/* Enable USART host commands */
-#define CONFIG_USART_HOST_COMMAND
-/* Enable USART and USART1 stream */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1
-/* Allocate and configure hw instance of USART */
-#undef CONFIG_UART_HOST_COMMAND_HW
-#define CONFIG_UART_HOST_COMMAND_HW usart1_hw
-/* Set baud rate of USART */
-#undef CONFIG_UART_HOST_COMMAND_BAUD_RATE
-#define CONFIG_UART_HOST_COMMAND_BAUD_RATE 3000000
-
-/*-------------------------------------------------------------------------*
- * UART Console Setup
- *-------------------------------------------------------------------------*/
-
-/* The UART console is on USART2 */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-/* We don't currently use DMA. */
-#undef CONFIG_UART_TX_DMA_PH
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-#undef CONFIG_UART_TX_REQ_CH
-#undef CONFIG_UART_RX_REQ_CH
-
-/*-------------------------------------------------------------------------*
- * Console Commands
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IDLE_STATS
-
-#ifdef SECTION_IS_RW
-#define CONFIG_CMD_SPI_XFER
-/* TODO(b/130249462): remove for release */
-#define CONFIG_CMD_FPSENSOR_DEBUG
-#endif
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/*-------------------------------------------------------------------------*
- * Rollback Block
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_ROLLBACK
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-#define CONFIG_MPU
-#define CONFIG_ROLLBACK_MPU_PROTECT
-
-/*
- * We do not use any "locally" generated entropy: this is normally used
- * to add local entropy when the main source of entropy is remote.
- */
-#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-#ifdef SECTION_IS_RW
-#undef CONFIG_ROLLBACK_UPDATE
-#endif
-
-/*-------------------------------------------------------------------------*
- * RW Signature Verification
- *-------------------------------------------------------------------------*/
-
-#ifdef SECTION_IS_RO
-/* RO verifies the RW partition signature */
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#endif /* SECTION_IS_RO */
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_RWSIG_TYPE_RWSIG
-
-/*-------------------------------------------------------------------------*
- * Watchdog
- *-------------------------------------------------------------------------*/
-
-/*
- * RW does slow compute, RO does slow flash erase.
- */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 10000
-#define CONFIG_WATCHDOG_HELP
-
-/*-------------------------------------------------------------------------*
- * Fingerprint Specific
- *-------------------------------------------------------------------------*/
-
-/* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  0 /* SPI2: first master config */
-#define CONFIG_FINGERPRINT_MCU
-#ifdef SECTION_IS_RW
-#define CONFIG_FP_SENSOR_FPC1025
-/*
- * Use the malloc code only in the RW section (for the private library),
- * we cannot enable it in RO since it is not compatible with the RW verification
- * (shared_mem_init done too late).
- */
-#define CONFIG_MALLOC
-/*
- * FP buffers are allocated in regular SRAM on STM32F4.
- * TODO(b/124773209): Instead of defining to empty, #undef once all CLs that
- * depend on FP_*_SECTION have landed. Also rename the variables to CONFIG_*.
- */
-#define FP_FRAME_SECTION
-#define FP_TEMPLATE_SECTION
-#endif /* SECTION_IS_RW */
-
-/*-------------------------------------------------------------------------*
- * Disable Features
- *-------------------------------------------------------------------------*/
-
-#undef CONFIG_ADC
-#undef CONFIG_HIBERNATE
-#undef CONFIG_I2C
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/*-------------------------------------------------------------------------*
- * Other
- *-------------------------------------------------------------------------*/
-
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_DMA
-#define CONFIG_FPU
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
-#define CONFIG_RNG
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_WP_ACTIVE_HIGH
-#define CONFIG_PANIC_STRIP_GPR
-
-#ifdef SECTION_IS_RW
-#define CONFIG_LOW_POWER_IDLE
-#endif /* SECTION_IS_RW */
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 9
-
-#include "gpio_signal.h"
-#include "board_rw.h"
-
-void slp_event(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __BOARD_H */
diff --git a/board/hatch_fp/board_rw.c b/board/hatch_fp/board_rw.c
deleted file mode 100644
index 4c83c8723c..0000000000
--- a/board/hatch_fp/board_rw.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "usart_host_command.h"
-#include "util.h"
-
-#ifndef SECTION_IS_RW
-#error "This file should only be built for RW."
-#endif
-
-/* SPI devices */
-struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI2_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-static void configure_fp_sensor_spi(void)
-{
-	/* The dragonclaw development board needs this enabled to enable the
-	 * AND gate (U10) to CS. Production boards could disable this to save
-	 * power since it's only needed for initial detection on those boards.
-	 */
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-
-	/* Set all SPI master signal pins to very high speed: B12/13/14/15 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module (master) */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-void board_init_rw(void)
-{
-	/*
-	 * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH
-	 * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset
-	 * default), but RW doesn't initialize this pin to 1 because sysjump
-	 * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c).
-	 * Explicitly reset FP_RST_ODL pin to default value.
-	 */
-	gpio_reset(GPIO_FP_RST_ODL);
-
-	/* Configure and enable SPI as master for FP sensor */
-	configure_fp_sensor_spi();
-}
diff --git a/board/hatch_fp/board_rw.h b/board/hatch_fp/board_rw.h
deleted file mode 100644
index 1bee6c947d..0000000000
--- a/board/hatch_fp/board_rw.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
-#define __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H
-
-void fps_event(enum gpio_signal signal);
-
-void board_init_rw(void);
-
-#endif /* __CROS_EC_BOARD_HATCH_FP_BOARD_RW_H */
diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk
deleted file mode 100644
index bb7f738704..0000000000
--- a/board/hatch_fp/build.mk
+++ /dev/null
@@ -1,53 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F412
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f412
-
-# Don't forget that the board build.mk is included more than once to allow
-# conditional variables to be realized. This means that we need to redefine all
-# variable or the "+=" lines will compound.
-board-rw=board_rw.o
-board-y=board.o
-
-# If we're mocking the sensor detection for testing (so we can test
-# sensor/transport permutations in the unit tests), don't build the real sensor
-# detection.
-ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
-	board-y+=fpsensor_detect.o
-	board-rw+=fpsensor_detect_rw.o
-endif
-
-# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
-# will fail on device.
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       fpsensor \
-       fpsensor_hw \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       stm32f_rtc \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/hatch_fp/dev_key.pem b/board/hatch_fp/dev_key.pem
deleted file mode 100644
index e3273cbccf..0000000000
--- a/board/hatch_fp/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAwVaB9PsLDGaHIMGp+uouwQvQGhNbIifTTX40aO7Sh00Pw9va
-tqggEe7AyeEKQLy7uxCfwLFkUABCmEIusLpsp7iGvAXz3R1N80pyszNGhsqV2UQH
-WW/M5L/3nPNjqjffje0ZMwoCNeE4YBqn+puiKEBEZXnnZsPV/f5lOn6v4GP7wzkF
-lTEq9InLhoWEKjuyL6gwfVZiEvNs52umzjSx/OaY9ux1SrnR6768xQdCRpah/RDC
-DAdL1v7lnzagBXq1p5WFFkAsIQhgSk7FhC0MX3BPqGE2c68t/g5AkyT1M7SZk4+5
-sY6oor7vVmfzUsShJOP1xb/Gv91cgRMOIU4y6mnQcf7YO68ex9YpnTnL2JGpZj/j
-MHzocI9l9a6R0PX17UOvXfVg2tQg+mU+zLqCG2xMe8R7+sA893/wgQdSXDiB5Nvh
-Vbp+89WxrX2vQK5lIObCUlKNLABsdeAMiTBN9IXMLdK5EP3gbL+wKG+/82DgAwaz
-l6hJZ2TLhV+BWdE3AgEDAoIBgQCA5FajUgddma9rK8anRsnWB+ARYjzBb+IzqXhF
-9IxaM1/X5+ckcBVhSdXb61wrKH0nYGqAdkLgACxlgXR10Z3FJa8oA/fovjP3hvci
-Ii8Ehw6Q2ATmSoiYf/pookJxepUJSLt3XAF5QNBAEcVRvRbFgC2Y+++Z1+P+qZjR
-qcqVl/0s0K5jdhyjBoevA61xfSF1Gsr+OZa3TPNE8m80IyFTRGX58vjce+FH1H3Y
-r4GEZGv+CywIBN05/0O/ecADpyKZ1m8PYrkpCwuNc+BK+BkEeEary61Y/IoQLVUx
-ntb4Y2meciFj5yr7PtRLcuwllWjEU5IfKPl2bB96fxITC6ALZVI9ksC6YDfCBXuU
-rWQNG1UFC6Ux//g1BdXhuPgl9MHS0nA37oJ8BxhdIgbQ1OxLlkY+VLwWN0IrC3vp
-+MDTufSPh7sR7r4sMVTYcncyc4kE0pnXQw+LHg3lnwadwlFeKP2mJKAyeveMqTWd
-GdB0eMuyv2cp77/nrESWYDUa9ysCgcEA/dwIdGjXmhz9T4zleZUTM9/D+uzW5kG0
-eB/br+ztzP/9YC+W0+DDlHVG2bdrsJsooZEyuzDaiGd/JiW9wPTjdjtSpCksJUEE
-KImymQ2GFbs7If1ZCgcxFqdywjk8WVqxCcv/Bqhsa7lcIGOFiV9X8x067xpwNU3t
-yw8IRXchfUK80BKFPf8quP4RoYy6o4rkos28+Q+zIPSZlBaZXKsSKPQElyN0SysN
-UwGSpOJ4b9TOH88GZFLymKOY4DUhvSJXAoHBAML31grDPsla0aaUD5oj06TcIavC
-24fyqm2qZRjJxPIffcW08MfTJJVraguEJWnJW1zVZ9vRdgXTriMutUPH32MWgnF5
-iv7dxvxEPaUoL68tbryxElt1wwpfMmDf4T6sIic8CANnMLUQIE5Orwobx7btqC8q
-8aQfa+vfrlybD6Fe1j19w3zVNviNoMdFQdF2MvbdHpZeQrpevgla6T/hwb5USx14
-VHoaX8bATRfmjtTW4FcYknRttvM+y8OaD/Q8IQKBwQCpPVr4ReURaKjfs0OmY2Ii
-lS1R8znu1nhQFT0f80kzVVOVdQ836y0No4SRJPJ1vMXBC3cndecFmlTEGSkrTez5
-fOHCxh1uK1gbBncQs665J3zBU5CxWiC5xPcsJig7kctb3VSvGvLye5LAQlkGP4/3
-aNH0vErOM/PctLAuT2uo1yiKtwN+qhx7VAvBCHxtB0MXM9NQtSIV+GZiubuTHLbF
-+AMPbPgyHLOMq7cYlvr1OIlqigRC4fcQbRCVeMEowY8CgcEAgfqOsdd/MOc2bw1f
-vBfibegWcoHnr/ccSRxDZdvYoWpT2SNLL+IYY5zxXQLDm9uSPeOakoukA+J0F3R4
-19qU7LmsS6ZcqekvUtgpGMV1H3OfKHYMPPkssZTMQJVA1HLBb31arO91zgrANDR0
-sWfaefPFdMdLwr+dR+p0Pby1Fj85flPXqI4kpbPAhNjWi6Qh+ei/DumB0ZR+sOdG
-KpaBKY2HaPri/BGVLyreD+8J4znq5LsMTZ55938ygma1TX1rAoHASPiGXtnpXS5d
-TH2LAGcvUyopOMgdEHbm9Xvkdet3rLrNPkJ+tuTsv7MwUprnoQQhCowbVwQ8IzS0
-MHSMcqBT68dJsq9Y3OB7tYHtSYDEcHEpbdIt1oRHO0tWo/XMC/qRvTSTiEqCv4LQ
-x2buZlD4KfmQOHh24EwuZMB7MsyvdMvY56LWrJExx+Cb1VcItGme9pxf5Tir0ho/
-xzKyVSGh59GI0weB/PQl1queFbSYDWeKF6Ra74appkWF1cb9z8P4
------END RSA PRIVATE KEY-----
diff --git a/board/hatch_fp/ec.tasklist b/board/hatch_fp/ec.tasklist
deleted file mode 100644
index ed1e6ed294..0000000000
--- a/board/hatch_fp/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
-	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/hatch_fp/fpsensor_detect.c b/board/hatch_fp/fpsensor_detect.c
deleted file mode 100644
index 638b5fbfe0..0000000000
--- a/board/hatch_fp/fpsensor_detect.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "timer.h"
-
-enum fp_transport_type get_fp_transport_type(void)
-{
-	enum fp_transport_type ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_TRANSPORT_SEL)) {
-	case 0:
-		ret = FP_TRANSPORT_TYPE_UART;
-		break;
-	case 1:
-		ret = FP_TRANSPORT_TYPE_SPI;
-		break;
-	default:
-		ret = FP_TRANSPORT_TYPE_UNKNOWN;
-		break;
-	}
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
-	return ret;
-}
diff --git a/board/hatch_fp/fpsensor_detect_rw.c b/board/hatch_fp/fpsensor_detect_rw.c
deleted file mode 100644
index 274cfee054..0000000000
--- a/board/hatch_fp/fpsensor_detect_rw.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "timer.h"
-
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	enum fp_sensor_type ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
-	case 0:
-		ret = FP_SENSOR_TYPE_ELAN;
-		break;
-	case 1:
-		ret = FP_SENSOR_TYPE_FPC;
-		break;
-	default:
-		ret = FP_SENSOR_TYPE_UNKNOWN;
-		break;
-	}
-	/* We leave GPIO_DIVIDER_HIGHSIDE enabled, since the dragonclaw
-	 * development board use it to enable the AND gate (U10) to CS.
-	 * Production boards could disable this to save power since it's
-	 * only needed for initial detection on those boards.
-	 */
-	return ret;
-}
-
-enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
-{
-	return FP_SENSOR_SPI_SELECT_PRODUCTION;
-}
diff --git a/board/hatch_fp/gpio.inc b/board/hatch_fp/gpio.inc
deleted file mode 100644
index c5319c2bee..0000000000
--- a/board/hatch_fp/gpio.inc
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(SLP_L,           PIN(A, 8), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SLP_ALT_L,       PIN(B, 6), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
-
-/* Inputs */
-GPIO(TRANSPORT_SEL,       PIN(B, 1), GPIO_INPUT)
-GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
-
-/* Outputs */
-GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
-
-/*
- * Unused pins.
- * Configuring unused pins as ANALOG INPUT to save power. For more info
- * look at "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY"
- * ("AN4365") section 1.2.6 and STM32F412 reference manual section 7.3.12.
- */
-UNUSED(PIN(B, 2))
-UNUSED(PIN(B, 5))
-UNUSED(PIN(C, 13))
-UNUSED(PIN(C, 14))
-UNUSED(PIN(C, 15))
-UNUSED(PIN(H, 0))
-UNUSED(PIN(H, 1))
-
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART1: PA9/PA10 (TX/RX) to AP */
-ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* USART2: PA2/PA3 (TX/RX) to servo */
-ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-
-#ifdef SECTION_IS_RW
-#include "gpio_rw.inc"
-#endif
diff --git a/board/hatch_fp/gpio_rw.inc b/board/hatch_fp/gpio_rw.inc
deleted file mode 100644
index 3dfe890c12..0000000000
--- a/board/hatch_fp/gpio_rw.inc
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef SECTION_IS_RW
-#error "This file should only be included in RW."
-#endif
-
-/* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
-
-/* Inputs */
-GPIO(FP_SENSOR_SEL,       PIN(B, 0), GPIO_INPUT)
-
-/* Outputs */
-GPIO(FP_RST_ODL,          PIN(B,10),  GPIO_OUT_HIGH)
-GPIO(SPI2_NSS,            PIN(B,12),  GPIO_OUT_HIGH)
-GPIO(USER_PRES_L,         PIN(B, 9),  GPIO_ODR_HIGH)
-
-/*
- * SPI2 master to sensor: PB13/14/15 (CLK/MISO/MOSI)
- * Note that we're not configuring NSS (PB12) here because we have already
- * configured it as a GPIO above and the SPI_MASTER module expects to use it
- * in software NSS management mode, not hardware management mode.
- */
-ALTERNATE(PIN_MASK(B, 0xE000), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER, GPIO_PULL_DOWN)
diff --git a/board/hayato b/board/hayato
deleted file mode 120000
index e143ffc00f..0000000000
--- a/board/hayato
+++ /dev/null
@@ -1 +0,0 @@
-asurada
\ No newline at end of file
diff --git a/board/helios/battery.c b/board/helios/battery.c
deleted file mode 100644
index c7168caf8a..0000000000
--- a/board/helios/battery.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Helios battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Battery Information */
-	[BATTERY_SIMPLO_C424] = {
-		.fuel_gauge = {
-			.manuf_name = "AS2GVID3jB",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_SIMPLO_C436] = {
-		.fuel_gauge = {
-			.manuf_name = "AS2GVUb3jB",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_C424;
diff --git a/board/helios/board.c b/board/helios/board.c
deleted file mode 100644
index cd2fb7e798..0000000000
--- a/board/helios/board.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helios board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/als_opt3001.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void board_lid_interrupt(enum gpio_signal signal)
-{
-	static int board_id = -1;
-
-	if (board_id == -1) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) == EC_SUCCESS)
-			board_id = val;
-	}
-
-	/*
-	 * This is a workaround with board version #1 where lid open can be
-	 * incorrectly triggered in 360-degree mode.
-	 */
-	if ((board_id == 1) && tablet_get_mode())
-		return;
-
-	lid_interrupt(signal);
-}
-
-static void board_gmr_tablet_switch_isr(enum gpio_signal signal)
-{
-	/*
-	 * For board version more than 2, the DUT support GMR sensor.
-	 * Else, blocked tablet_mode interrupt.
-	 */
-	if (get_board_id() < 2)
-		return;
-
-	gmr_tablet_switch_isr(signal);
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-static enum base_accelgyro_type base_accelgyro_config;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (base_accelgyro_config == BASE_GYRO_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void board_detect_motionsense(void)
-{
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (base_accelgyro_config != BASE_GYRO_NONE)
-		return;
-
-	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
-	if (val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		base_accelgyro_config = BASE_GYRO_ICM426XX;
-		ccprints("Base Accelgyro: ICM40608");
-	} else {
-		base_accelgyro_config = BASE_GYRO_BMI160;
-		ccprints("Base Accelgyro: BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Helios temperature control thresholds */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(65),
-	.temp_fan_max = C_TO_K(80),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-int board_tcpc_post_init(int port)
-{
-	int rv = EC_SUCCESS;
-
-	if (port == USB_PD_PORT_TCPC_0)
-		/* Set MUX_DP_EQ to 3.6dB (0x98) */
-		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	else if (port == USB_PD_PORT_TCPC_1)
-		rv = tcpc_write(port,
-				PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD, 0x80);
-
-	return rv;
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255) || (sku == 1);
-}
diff --git a/board/helios/board.h b/board/helios/board.h
deleted file mode 100644
index 1534b69c48..0000000000
--- a/board/helios/board.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helios board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(LID_ALS))
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY 0
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/*
- * Helios' battery takes several seconds to come back out of its disconnect
- * state (~4.2 seconds on the unit I have, so give it a little more for margin).
- */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* DPTF */
-#define CONFIG_DPTF_MULTI_PROFILE
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SIMPLO_C424,
-	BATTERY_SIMPLO_C436,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/helios/build.mk b/board/helios/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/helios/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/helios/ec.tasklist b/board/helios/ec.tasklist
deleted file mode 100644
index 63d366a33b..0000000000
--- a/board/helios/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/helios/gpio.inc b/board/helios/gpio.inc
deleted file mode 100644
index d16e1643be..0000000000
--- a/board/helios/gpio.inc
+++ /dev/null
@@ -1,136 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, board_lid_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(C, 7), GPIO_INT_BOTH, board_gmr_tablet_switch_isr)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, motion_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(NC_94,                    PIN(9, 4), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-12 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)                             /* ADC0, ADC1, ADC2, ADC3 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/helios/led.c b/board/helios/led.c
deleted file mode 100644
index 94f5bdb973..0000000000
--- a/board/helios/led.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Helios
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/helios/vif_override.xml b/board/helios/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/helios/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/herobrine_npcx9/battery.c b/board/herobrine_npcx9/battery.c
deleted file mode 100644
index f6622f11ee..0000000000
--- a/board/herobrine_npcx9/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all herobrine_npcx9 battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* AP16L5J */
-	[BATTERY_AP16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP16L5J;
diff --git a/board/herobrine_npcx9/board.c b/board/herobrine_npcx9/board.c
deleted file mode 100644
index f63f5c7991..0000000000
--- a/board/herobrine_npcx9/board.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-static uint8_t sku_id;
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_RTC_EC_WAKE_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
-	 * as it still uses the legacy location (KSO_01/KSI_00).
-	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"rtc",     I2C_PORT_RTC,    400, GPIO_EC_I2C_RTC_SCL,
-					  GPIO_EC_I2C_RTC_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Read SKU ID from GPIO and initialize variables for board variants */
-static void sku_id_init(void)
-{
-	int bits[3];
-
-	bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
-	bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
-	bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
-
-	sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
-	CPRINTS("SKU ID: %u", sku_id);
-}
-DECLARE_HOOK(HOOK_INIT, sku_id_init, HOOK_PRIO_INIT_I2C + 1);
-
-__override uint32_t board_get_sku_id(void)
-{
-	return sku_id;
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable interrupt for BMI260 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi260_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: BMI260: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI260,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi260_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI260,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi260_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/herobrine_npcx9/board.h b/board/herobrine_npcx9/board.h
deleted file mode 100644
index e0ca39fac0..0000000000
--- a/board/herobrine_npcx9/board.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-/* BMI260 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_WP_L		GPIO_EC_WP_ODL
-#define GPIO_SWITCHCAP_PG	GPIO_SRC_VPH_PWR_PG
-#define GPIO_ACOK_OD		GPIO_CHG_ACOK_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_S5
-#define GPIO_POWER_GOOD		GPIO_MB_POWER_GOOD
-#define GPIO_EC_INT_L		GPIO_AP_EC_INT_L
-#define GPIO_DP_HOT_PLUG_DET	GPIO_DP_HOT_PLUG_DET_R
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_AP16L5J,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/herobrine_npcx9/build.mk b/board/herobrine_npcx9/build.mk
deleted file mode 100644
index 601c45a042..0000000000
--- a/board/herobrine_npcx9/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=herobrine
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=led.o
-board-y+=switchcap.o
-board-y+=usbc_config.o
diff --git a/board/herobrine_npcx9/ec.tasklist b/board/herobrine_npcx9/ec.tasklist
deleted file mode 100644
index 5beeb38feb..0000000000
--- a/board/herobrine_npcx9/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/herobrine_npcx9/gpio.inc b/board/herobrine_npcx9/gpio.inc
deleted file mode 100644
index 239bedd95d..0000000000
--- a/board/herobrine_npcx9/gpio.inc
+++ /dev/null
@@ -1,177 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(F, 4), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)  /* ACOK */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(6, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(D, 3), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(5, 1), GPIO_INT_BOTH, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low.
- */
-GPIO_INT(MB_POWER_GOOD,     PIN(3, 7), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* PP1800_L18B from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 3), GPIO_INT_FALLING, bmi260_interrupt)  /* Accelerometer/gyro interrupt */
-
-GPIO(RTC_EC_WAKE_ODL ,      PIN(0, 2), GPIO_INPUT)     /* RTC interrupt */
-GPIO(EC_ENTERING_RW,        PIN(7, 2), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(CCD_MODE_ODL,          PIN(6, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-GPIO(EC_GSC_PACKET_MODE,    PIN(8, 3), GPIO_OUT_LOW)   /* GSC Packet Mode */
-
-/* PMIC/AP 1.8V */
-GPIO(PMIC_RESIN_L,          PIN(A, 0), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(A, 2), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(AP_EC_INT_L,           PIN(5, 6), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-
-/* Power enables */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-GPIO(EN_PP5000_S5,          PIN(7, 3), GPIO_OUT_HIGH)  /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(A, 1), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TP_INT_GATE,           PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(B, 1), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET_R,     PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(F, 0), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_RTC_SCL,        PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_RTC_SDA,        PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(9, 4), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 7), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(A, 5), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(6, 7), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(7, 0), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(E, 1), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(SRC_VPH_PWR_PG,        PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 2))
-UNUSED(PIN(5, 4))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(D, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(E, 3))
-UNUSED(PIN(C, 1))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(D, 6))
-UNUSED(PIN(3, 2))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(8, 6))
-UNUSED(PIN(D, 4))
-UNUSED(PIN(4, 1))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 7))
-UNUSED(PIN(A, 4))
-UNUSED(PIN(9, 6))
-UNUSED(PIN(9, 3))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(5, 0))
-UNUSED(PIN(8, 1))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(F, 0x0C), 1, MODULE_I2C, 0)             /* I2C4 (GPIOF2/F3) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - ACOK_OD */
-ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - EC_PWR_BTN_ODL */
-ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - LID_OPEN_EC */
-ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - RTC_EC_WAKE_ODL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/herobrine_npcx9/led.c b/board/herobrine_npcx9/led.c
deleted file mode 100644
index 295c8effeb..0000000000
--- a/board/herobrine_npcx9/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_LEFT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_LEFT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/board/herobrine_npcx9/switchcap.c b/board/herobrine_npcx9/switchcap.c
deleted file mode 100644
index 16b0db6ef6..0000000000
--- a/board/herobrine_npcx9/switchcap.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "power/qcom.h"
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_PG);
-}
diff --git a/board/herobrine_npcx9/usbc_config.c b/board/herobrine_npcx9/usbc_config.c
deleted file mode 100644
index 3662b966e0..0000000000
--- a/board/herobrine_npcx9/usbc_config.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine board-specific USB-C configuration */
-
-#include "bc12/pi3usb9201_public.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ppc/sn5s330_public.h"
-#include "system.h"
-#include "tcpm/ps8xxx_public.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_config.h"
-#include "usb_mux.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Initialize board USC-C things */
-static void board_init_usbc(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/board/herobrine_npcx9/usbc_config.h b/board/herobrine_npcx9/usbc_config.h
deleted file mode 100644
index 69f546ef85..0000000000
--- a/board/herobrine_npcx9/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#include "gpio.h"
-
-void tcpc_alert_event(enum gpio_signal signal);
-void usb0_evt(enum gpio_signal signal);
-void usb1_evt(enum gpio_signal signal);
-void usba_oc_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/herobrine_npcx9/vif_override.xml b/board/herobrine_npcx9/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/herobrine_npcx9/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/hoho/board.c b/board/hoho/board.c
deleted file mode 100644
index 07b772c826..0000000000
--- a/board/hoho/board.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Hoho dongle configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "mcdp28x0.h"
-#include "registers.h"
-#include "task.h"
-#include "usb_bb.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "timer.h"
-#include "util.h"
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-
-void hpd_event(enum gpio_signal signal);
-#include "gpio_list.h"
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_irq_deferred(void)
-{
-	pd_send_hpd(0, hpd_irq);
-}
-DECLARE_DEFERRED(hpd_irq_deferred);
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DP_HPD);
-
-	if (level != hpd_prev_level)
-		/* It's a glitch while in deferred or canceled action */
-		return;
-
-	pd_send_hpd(0, (level) ? hpd_high : hpd_low);
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-void hpd_event(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data, -1);
-
-	/* It's a glitch.  Previous time moves but level is the same. */
-	if (cur_delta < HPD_USTREAM_DEBOUNCE_IRQ)
-		return;
-
-	if ((!hpd_prev_level && level) &&
-	    (cur_delta < HPD_USTREAM_DEBOUNCE_LVL))
-		/* It's an irq */
-		hook_call_deferred(&hpd_irq_deferred_data, 0);
-	else if (cur_delta >= HPD_USTREAM_DEBOUNCE_LVL)
-		hook_call_deferred(&hpd_lvl_deferred_data,
-				   HPD_USTREAM_DEBOUNCE_LVL);
-
-	hpd_prev_level = level;
-}
-
-/* Initialize board. */
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
-}
-
-#ifdef CONFIG_SPI_FLASH
-
-static void board_init_spi2(void)
-{
-	/* Remap SPI2 to DMA channels 6 and 7 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-
-	/* Set pin NSS to general purpose output mode (01b). */
-	/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
-	STM32_GPIO_MODER(GPIO_B) &= ~0xff000000;
-	STM32_GPIO_MODER(GPIO_B) |= 0xa9000000;
-
-	/* Set all four pins to alternate function 0 */
-	STM32_GPIO_AFRH(GPIO_B) &= ~(0xffff0000);
-
-	/* Set all four pins to output push-pull */
-	STM32_GPIO_OTYPER(GPIO_B) &= ~(0xf000);
-
-	/* Set pullup on NSS */
-	STM32_GPIO_PUPDR(GPIO_B) |= 0x1000000;
-
-	/* Set all four pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= BIT(14);
-	STM32_RCC_APB1RSTR &= ~BIT(14);
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-}
-#endif /* CONFIG_SPI_FLASH */
-
-static void factory_validation_deferred(void)
-{
-	struct mcdp_info info;
-
-	mcdp_enable();
-
-	/* test mcdp via serial to validate function */
-	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
-		gpio_set_level(GPIO_MCDP_READY, 1);
-		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
-	}
-
-	mcdp_disable();
-}
-DECLARE_DEFERRED(factory_validation_deferred);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	timestamp_t now;
-#ifdef CONFIG_SPI_FLASH
-	board_init_spi2();
-#endif
-	now = get_time();
-	hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
-	hpd_prev_ts = now.val;
-	gpio_enable_interrupt(GPIO_DP_HPD);
-
-	gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
-	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
-}
-
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const void * const usb_strings[] = {
-	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
-	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/**
- * USB configuration
- * Any type-C device with alternate mode capabilities must have the following
- * set of descriptors.
- *
- * 1. Standard Device
- * 2. BOS
- *    2a. Container ID
- *    2b. Billboard Caps
- */
-struct my_bos {
-	struct usb_bos_hdr_descriptor bos;
-	struct usb_contid_caps_descriptor contid_caps;
-	struct usb_bb_caps_base_descriptor bb_caps;
-	struct usb_bb_caps_svid_descriptor bb_caps_svids[1];
-};
-
-static struct my_bos bos_desc = {
-	.bos = {
-		.bLength = USB_DT_BOS_SIZE,
-		.bDescriptorType = USB_DT_BOS,
-		.wTotalLength = (USB_DT_BOS_SIZE + USB_DT_CONTID_SIZE +
-				 USB_BB_CAPS_BASE_SIZE +
-				 USB_BB_CAPS_SVID_SIZE * 1),
-		.bNumDeviceCaps = 2,  /* contid + bb_caps */
-	},
-	.contid_caps =	{
-		.bLength = USB_DT_CONTID_SIZE,
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_CONTID,
-		.bReserved = 0,
-		.ContainerID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-	},
-	.bb_caps = {
-		.bLength = (USB_BB_CAPS_BASE_SIZE + USB_BB_CAPS_SVID_SIZE * 1),
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_BILLBOARD,
-		.iAdditionalInfoURL = USB_STR_BB_URL,
-		.bNumberOfAlternateModes = 1,
-		.bPreferredAlternateMode = 1,
-		.VconnPower = 0,
-		.bmConfigured = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-				 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-		.bReserved = 0,
-	},
-	.bb_caps_svids = {
-		{
-			.wSVID = 0xff01, /* TODO(tbroch) def'd in other CL remove hardcode */
-			.bAlternateMode = 1,
-			.iAlternateModeString = USB_STR_BB_URL, /* TODO(crosbug.com/p/32687) */
-		},
-	},
-};
-
-const struct bos_context bos_ctx = {
-	.descp = (void *)&bos_desc,
-	.size = sizeof(struct my_bos),
-};
diff --git a/board/hoho/board.h b/board/hoho/board.h
deleted file mode 100644
index 8e6ec34b3d..0000000000
--- a/board/hoho/board.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hoho dongle configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_ADC
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_HW_CRC
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#define CONFIG_RWSIG_TYPE_USBPD1
-#define CONFIG_SHA256
-/* TODO(tbroch) Re-enable once STM spi master can be inhibited at boot so it
-   doesn't interfere with HDMI loading its f/w */
-#undef CONFIG_SPI_FLASH
-#define CONFIG_SPI_CS_GPIO GPIO_PD_MCDP_SPI_CS_L
-#define CONFIG_USB
-#define CONFIG_USB_BOS
-#define CONFIG_USB_INHIBIT_CONNECT
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_HOHO
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 2
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_FLASH
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-#define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
-#define CONFIG_EVENT_LOG_SIZE 256
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_PD_VBUS_DETECT_NONE
-/* mcdp2850 serial interface */
-#define CONFIG_MCDP28X0 usart3_hw
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART3
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* USB configuration */
-#define CONFIG_USB_PID 0x5010
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-/* No Write-protect GPIO, force the write-protection */
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-
-/* Inform VIF generator that this board is an Alt Mode Adapter */
-#define CONFIG_USB_ALT_MODE_ADAPTER
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CH_CC1_PD = 0,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_BB_URL,
-
-	USB_STR_COUNT
-};
-
-/* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
-
-#endif /* !__ASSEMBLER__ */
-
-/* USB Device class */
-#define USB_DEV_CLASS USB_CLASS_BILLBOARD
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hoho/build.mk b/board/hoho/build.mk
deleted file mode 100644
index 18799c3b9f..0000000000
--- a/board/hoho/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072B
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/hoho/dev_key.pem b/board/hoho/dev_key.pem
deleted file mode 100644
index 08d5bd414c..0000000000
--- a/board/hoho/dev_key.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEogIBAAKCAQEApfbLqgOYIM6AfRI6SJcj1Crengsp+yjHXtwZFOH6WDVP5Q9c
-KSbwqoKHEKTbWJ90ymjqjfi382hl64L/V6J8SfIqGhrFztwXLhJOwFXRK5Jgzkk+
-YUByDzAKTKOlzvvRqk10Tq5a3wphg1SxGVLLOOsTGoKhGI93Wkf2j8AibMlVVZzz
-Q8DmVszkYZL+Kchv6h1FgSvBW0oZa5tVod+0XToWSrPEYnBWs0zZEywCusIXMy7D
-LaqMPFB4LTkDZ9Ne8jnB5xRad+ME4CgxZqUwGC7tdFdHdiiXpIwzIoxVk6xFIZUF
-uusG4RR3O2ubaPJ/Fpf3UuuCWmddk37WaC7o7QIDAQABAoIBAAG4L94AEYhte0lQ
-cggkgLuHAi1zAilW/9HMx/m+aaCWVNCTuym1/JJXrdyPSLJ/XG9obN2xsP41m7C3
-97tJtK3zc1o34srE3vycNfKqMPOZnaUlfx700vmzTrgCjgo5868nBEh4Z/qdmesJ
-aphPkklxrg39QnwFqH/n9PcCT5j+7LyCeWeGbWxKfpzP2CT6v8XxT3XY1mtFSa4j
-dfYaqb+aunYAhjEb4gqa48hyNTQAZskDOUr1TK433wbGqRughXXrQQix+FBW483u
-IGo8aGgiQsjYxHX+ynNTMKW1Oap9WZRWVxF09Ph1f3MT+k3gKqM/0AejlDfBuTDu
-aLxiKIUCgYEA1FZmfGn4RNlghv/ZCAlfWqbf5NA1/wA/Knk8u0R+kMQ71e8NFjOc
-Ym3Uix+89KcKDBIgHn1360pNvSCeTyVU28wQ2bst5s6pvu4FYDvjym2nTgXcFJX6
-DDnZfVZ+WLSFR8E76LQLJGd00DSq0/uBw3ULyRSirkuQnFI3w3u4BH8CgYEAyBdD
-UMV83kwQaDMuGgKqZtD4Ou3s/MDzMwcNgUSjLIueFdsXVnlzYQwwJXuLFkrp5COx
-Zyoha/d1QQawnYehKmHWWy7qN/l0CO+F2DGb1E6pNXJrn+zn33Mgz9ms8421eqqn
-ATQbq6ZQInk1IrkLfyZ3t09l6cyBMJuJjkoBrJMCgYA2Hfsq1FtJONnILmbjDHh4
-AzXm/EX2wtpWeeXHmLJlNQ5G/REpymeeEn3sI1+mPvhpkSkMfE/W8O4VOL4AT/Rr
-vHvC8ljFjYBnwAQwvbLVwdK1KPspZ/v9p7TNpAC5nPCnFBGvwktgsNltwy6SrnQp
-G6iwTAkWQP4PSUkbEmoZAwKBgF0OLJlQ70y3FV5Qhx1DphohD4DgjDnURoaxvf8j
-e7vIxuGlPgpSe21j7LRR65KXjoUycFvpRRfgQyDVyqfInxSF4doQTI9xrRxGwPmV
-wMIRPzKDHziGRiQud9ESjBPNENyWpwqxQDkpJNWThzm503Xz3vNasqv0FxUTEPsi
-wfqPAoGABXPl7baUkpYzppAJqRlGNxsMjpbWscDPjmPosrGs6d81DP287s/IjfDR
-ysQptvhJRK/lubM8As+d0/VLd6P8wk8dyZR1nRELwnVaPC55cS5+YIjgXK9TBmLA
-hC0BIgujJS2qbXQRQF7yX925Gg77WLN2sJqtVg1Brine056pHTA=
------END RSA PRIVATE KEY-----
diff --git a/board/hoho/ec.tasklist b/board/hoho/ec.tasklist
deleted file mode 100644
index 41fc047d6a..0000000000
--- a/board/hoho/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/hoho/gpio.inc b/board/hoho/gpio.inc
deleted file mode 100644
index 6d0701ded1..0000000000
--- a/board/hoho/gpio.inc
+++ /dev/null
@@ -1,37 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(DP_HPD,       PIN(A, 0),  GPIO_INT_BOTH, hpd_event)
-
-GPIO(USB_C_CC1_PD,     PIN(A, 1),  GPIO_ANALOG)
-GPIO(STM_READY,        PIN(A, 2),  GPIO_OUT_LOW) /* factory test only */
-GPIO(MCDP_RESET_L,     PIN(A, 3),  GPIO_OUT_HIGH)
-GPIO(PD_DAC_REF,       PIN(A, 4),  GPIO_ANALOG)
-
-GPIO(MCDP_READY,       PIN(A, 7),  GPIO_OUT_LOW) /* factory test only */
-GPIO(PD_SBU_ENABLE,    PIN(A, 8),  GPIO_OUT_LOW)
-GPIO(USB_DM,           PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,           PIN(A, 12), GPIO_ANALOG)
-GPIO(PD_CC1_TX_EN,     PIN(A, 15), GPIO_OUT_LOW)
-
-GPIO(MCDP_GPIO1,       PIN(B, 0),  GPIO_INPUT)
-GPIO(MCDP_CONFIG1,     PIN(B, 1),  GPIO_INPUT)
-GPIO(PD_MCDP_SPI_WP_L, PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(PD_CC1_TX_DATA,   PIN(B, 4),  GPIO_OUT_LOW)
-GPIO(PD_MCDP_SPI_CS_L, PIN(B, 12), GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0)            /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0)            /* TIM17_CH1: PB9 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 4, MODULE_UART,   GPIO_PULL_UP) /* USART3: PB10/PB11 */
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h
deleted file mode 100644
index 2f01c275a8..0000000000
--- a/board/hoho/usb_pd_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PB3-4 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* SPI1_TX no remap needed */
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) BIT(21)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* TIM1_CH1 no remap needed */
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 Mhz pin speed on TX_EN (PA15) */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
-	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* PB4 is SPI1_MISO */
-	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 1);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
-	/* put the low level reference in Hi-Z */
-	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
-}
-
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/*
-	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
-	 * use VrefInt / 2 as INM (about 600mV)
-	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable) {}
-
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	/* only one CC line, assume other one is always low */
-	return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c
deleted file mode 100644
index 2ee83d32aa..0000000000
--- a/board/hoho/usb_pd_policy.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "board.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_api.h"
-#include "usb_bb.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-/* Holds valid object position (opos) for entered mode */
-static int alt_mode[PD_AMODE_COUNT];
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* No battery, nothing to do */
-	return;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return 1;
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/* Always refuse power swap */
-	return 0;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/* Always refuse data swap */
-	return 0;
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-}
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 1, /* Vbus power required */
-				 AMA_USBSS_BBONLY /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	/* TODO(tbroch): Do we plan to obtain TID (test ID) for hoho */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	payload[VDO_I(AMA)] = vdo_ama;
-	return VDO_I(AMA) + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, USB_VID_GOOGLE);
-	payload[2] = 0;
-	return 3;
-}
-
-#define OPOS_DP 1
-#define OPOS_GFU 1
-
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
-		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
-};
-
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes));
-		return ARRAY_SIZE(vdo_dp_modes) + 1;
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		memcpy(payload + 1, vdo_goog_modes, sizeof(vdo_goog_modes));
-		return ARRAY_SIZE(vdo_goog_modes) + 1;
-	} else {
-		return 0; /* nak */
-	}
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = gpio_get_level(GPIO_DP_HPD);
-	if (opos != OPOS_DP)
-		return 0; /* nak */
-
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
-				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
-				   0x2);
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 1);
-	return 1;
-}
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	int rv = 0; /* will generate a NAK */
-
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
-	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
-		alt_mode[PD_AMODE_DISPLAYPORT] = OPOS_DP;
-		rv = 1;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 1, NULL);
-	} else if ((PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) &&
-		   (PD_VDO_OPOS(payload[0]) == OPOS_GFU)) {
-		alt_mode[PD_AMODE_GOOGLE] = OPOS_GFU;
-		rv = 1;
-	}
-
-	if (rv)
-		/*
-		 * If we failed initial mode entry we'll have enumerated the USB
-		 * Billboard class.  If so we should disconnect.
-		 */
-		usb_disconnect();
-
-	return rv;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	if (type != TCPCI_MSG_SOP)
-		return 0;
-
-	if (svid == USB_SID_DISPLAYPORT)
-		return alt_mode[PD_AMODE_DISPLAYPORT];
-	else if (svid == USB_VID_GOOGLE)
-		return alt_mode[PD_AMODE_GOOGLE];
-	return 0;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) {
-		gpio_set_level(GPIO_PD_SBU_ENABLE, 0);
-		alt_mode[PD_AMODE_DISPLAYPORT] = 0;
-		pd_log_event(PD_EVENT_VIDEO_DP_MODE, 0, 0, NULL);
-	} else if (PD_VDO_VID(payload[0]) == USB_VID_GOOGLE) {
-		alt_mode[PD_AMODE_GOOGLE] = 0;
-	} else {
-		CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]);
-	}
-
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int rsize;
-
-	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE ||
-	    !alt_mode[PD_AMODE_GOOGLE])
-		return 0;
-
-	*rpayload = payload;
-
-	rsize = pd_custom_flash_vdm(port, cnt, payload);
-	if (!rsize) {
-		int cmd = PD_VDO_CMD(payload[0]);
-		switch (cmd) {
-		case VDO_CMD_GET_LOG:
-			rsize = pd_vdm_get_log_entry(payload);
-			break;
-		default:
-			/* Unknown : do not answer */
-			return 0;
-		}
-	}
-
-	/* respond (positively) to the request */
-	payload[0] |= VDO_SRC_RESPONDER;
-
-	return rsize;
-}
diff --git a/board/hoho/vif_override.xml b/board/hoho/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/hoho/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/homestar/base_detect.c b/board/homestar/base_detect.c
deleted file mode 100644
index b08784357b..0000000000
--- a/board/homestar/base_detect.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Homestar base detection code */
-
-#include "adc.h"
-#include "base_state.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
-#define BASE_DETECT_EN_LATER_US (600 * MSEC)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
-#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * Lid has 604K pull-up, base has 30.1K pull-down, so the
- * ADC value should be around 30.1/(604+30.1)*3300 = 156
- *
- * We add a significant margin on the maximum value, due to noise on the line,
- * especially when PWM is active. See b/64193554 for details.
- */
-#define BASE_DETECT_MIN_MV 120
-#define BASE_DETECT_MAX_MV 300
-
-/* Minimum ADC value to indicate base is disconnected for sure */
-#define BASE_DETECT_DISCONNECT_MIN_MV 1500
-
-/*
- * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
- * can be used to wake system from deep S3).
- */
-#define BASE_DETECT_PULSE_MIN_US 400
-#define BASE_DETECT_PULSE_MAX_US 650
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Change in power to base
- * 2. Indicate mode change to host.
- * 3. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	gpio_set_level(GPIO_EN_BASE, connected);
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-	base_set_state(connected);
-	current_base_status = status;
-}
-
-/* Measure detection pin pulse duration (used to wake AP from deep S3). */
-static uint64_t pulse_start;
-static uint32_t pulse_width;
-
-static void print_base_detect_value(int v, int tmp_pulse_width)
-{
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-	uint32_t tmp_pulse_width = pulse_width;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		return;
-
-	print_base_detect_value(v, tmp_pulse_width);
-
-	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
-		if (current_base_status != BASE_CONNECTED) {
-			base_detect_change(BASE_CONNECTED);
-		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
-			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
-			CPRINTS("Sending event to AP");
-			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-		}
-		return;
-	}
-
-	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
-		base_detect_change(BASE_DISCONNECTED);
-		return;
-	}
-
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static inline int detect_pin_connected(enum gpio_signal det_pin)
-{
-	return gpio_get_level(det_pin) == 0;
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-	int debounce_us;
-
-	if (detect_pin_connected(signal))
-		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-	else
-		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-
-	if (base_detect_debounce_time <= time_now) {
-		/*
-		 * Detect and measure detection pin pulse, when base is
-		 * connected. Only a single pulse is measured over a debounce
-		 * period. If no pulse, or multiple pulses are detected,
-		 * pulse_width is set to 0.
-		 */
-		if (current_base_status == BASE_CONNECTED &&
-		    !detect_pin_connected(signal)) {
-			pulse_start = time_now;
-		} else {
-			pulse_start = 0;
-		}
-		pulse_width = 0;
-
-		hook_call_deferred(&base_detect_deferred_data, debounce_us);
-	} else {
-		if (current_base_status == BASE_CONNECTED &&
-		    detect_pin_connected(signal) && !pulse_width &&
-		    pulse_start) {
-			/* First pulse within period. */
-			pulse_width = time_now - pulse_start;
-		} else {
-			pulse_start = 0;
-			pulse_width = 0;
-		}
-	}
-
-	base_detect_debounce_time = time_now + debounce_us;
-}
-
-static void base_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
-	gpio_enable_interrupt(GPIO_BASE_DET_L);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
-
-static void base_disable(void)
-{
-	/*
-	 * Disable base detection interrupt and disable power to base.
-	 * Set the state UNKNOWN so the next startup will initialize a
-	 * correct state and notify AP.
-	 */
-	gpio_disable_interrupt(GPIO_BASE_DET_L);
-	base_detect_change(BASE_UNKNOWN);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * If we jumped to this image and chipset is already in S0, enable
-	 * base.
-	 */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		base_enable();
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		base_enable();
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/homestar/battery.c b/board/homestar/battery.c
deleted file mode 100644
index b1a05809f0..0000000000
--- a/board/homestar/battery.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all homestar battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* COSMX GH02047XL 333-1C-DA-A */
-	[BATTERY_GH02047XL_1C] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.device_name = "GH02047XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* COSMX GH02047XL */
-	[BATTERY_GH02047XL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.device_name = "GH02047XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* COSMX DS02032XL */
-	[BATTERY_DS02032XL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-13-A",
-			.device_name = "DS02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* SMP DS02032XL */
-	[BATTERY_DS02032XL_1C] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-13-A",
-			.device_name = "DS02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* Sunwoda L21D4PG0 */
-	[BATTERY_L21D4PG0] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L21D4PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8900, /* mV */
-			.voltage_normal         = 7720, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 274,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* SMP L21M4PG0 */
-	[BATTERY_L21M4PG0] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L21M4PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8900, /* mV */
-			.voltage_normal         = 7720, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 274,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D4PG0;
diff --git a/board/homestar/board.c b/board/homestar/board.c
deleted file mode 100644
index 22f940eec2..0000000000
--- a/board/homestar/board.c
+++ /dev/null
@@ -1,698 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Homestar board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/ln9310.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peripheral_charger.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "queue.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-static void switchcap_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void switchcap_interrupt(enum gpio_signal signal)
-{
-	ln9310_interrupt(signal);
-}
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* LN9310 switchcap */
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
-};
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Mutexes */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm42607_data;
-
-enum lid_accelgyro_type {
-	LID_GYRO_NONE = 0,
-	LID_GYRO_BMI160 = 1,
-	LID_GYRO_ICM42607 = 2,
-};
-
-static enum lid_accelgyro_type lid_accelgyro_config;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t icm42607_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm42607_lid_gyro = {
-	.name = "Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.min_frequency = ICM42607_GYRO_MIN_FREQ,
-	.max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int val = -1;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (lid_accelgyro_config != LID_GYRO_NONE)
-		return;
-
-	/* Check base accelgyro chip */
-	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
-	if (val == ICM42607_CHIP_ICM42607P) {
-		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
-		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
-		lid_accelgyro_config = LID_GYRO_ICM42607;
-		CPRINTS("LID Accelgyro: ICM42607");
-	} else {
-		lid_accelgyro_config = LID_GYRO_BMI160;
-		CPRINTS("LID Accelgyro: BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (lid_accelgyro_config) {
-	case LID_GYRO_ICM42607:
-		icm42607_interrupt(signal);
-		break;
-	case LID_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-enum battery_cell_type board_get_battery_cell_type(void)
-{
-	return BATTERY_CELL_TYPE_2S;
-}
-
-static void board_switchcap_init(void)
-{
-	CPRINTS("Use switchcap: LN9310");
-
-	/* Configure and enable interrupt for LN9310 */
-	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
-	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
-
-	/* Only configure the switchcap if not sysjump */
-	if (!system_jumped_late()) {
-		ln9310_init();
-	}
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-
-	board_switchcap_init();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__overridable uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Check if the chip is PS8755 for rev-0, rev-1 and rev-2 */
-	if (system_get_board_version() < 3 && check_ps8755_chip(port))
-		return PS8755_PRODUCT_ID;
-
-	return PS8805_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Board rev 1+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 1)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
-	ln9310_software_enable(enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return ln9310_power_good();
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/homestar/board.h b/board/homestar/board.h
deleted file mode 100644
index 650ba638ec..0000000000
--- a/board/homestar/board.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Homestar board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Switchcap */
-#define CONFIG_LN9310
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_VENDOR_PARAM
-
-/* Enable PD3.0 */
-#define CONFIG_USB_PD_REV30
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* Lid accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-#define CONFIG_ACCELGYRO_ICM42607
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_FRONT_PROXIMITY_SWITCH
-
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_BASE_ATTACHED_SWITCH
-
-/*
- * Oled panel need to setup both vcc and backlight, AP will ctrl them.
- * BL_DISABLE does not need to be controlled by ec.
- */
-#ifdef CONFIG_BACKLIGHT_LID
-#undef CONFIG_BACKLIGHT_LID
-#endif
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
-#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
-
-#define CONFIG_MKBP_INPUT_DEVICES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_BASE_DET,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_GH02047XL_1C,
-	BATTERY_GH02047XL,
-	BATTERY_DS02032XL,
-	BATTERY_DS02032XL_1C,
-	BATTERY_L21D4PG0,
-	BATTERY_L21M4PG0,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Base detection */
-void base_detect_interrupt(enum gpio_signal signal);
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/homestar/build.mk b/board/homestar/build.mk
deleted file mode 100644
index 74b6b95e4d..0000000000
--- a/board/homestar/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y=battery.o board.o led.o base_detect.o
diff --git a/board/homestar/ec.tasklist b/board/homestar/ec.tasklist
deleted file mode 100644
index ea2aaa97f5..0000000000
--- a/board/homestar/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/homestar/gpio.inc b/board/homestar/gpio.inc
deleted file mode 100644
index 77a69a5faa..0000000000
--- a/board/homestar/gpio.inc
+++ /dev/null
@@ -1,196 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
-
-/* Sensor interrupts */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
-GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
-
-/*
- * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
- * need to be an interrupt for normal EC operations. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Base detection */
-GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
-
-/* POGO */
-GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
-GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. Apply PU for power saving */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(3, 1))
-UNUSED(PIN(3, 0))
-UNUSED(PIN(2, 7))
-UNUSED(PIN(2, 6))
-UNUSED(PIN(2, 5))
-UNUSED(PIN(2, 4))
-UNUSED(PIN(2, 3))
-UNUSED(PIN(2, 2))
-UNUSED(PIN(2, 1))
-UNUSED(PIN(2, 0))
-UNUSED(PIN(1, 7))
-UNUSED(PIN(1, 6))
-UNUSED(PIN(1, 5))
-UNUSED(PIN(1, 4))
-UNUSED(PIN(1, 3))
-UNUSED(PIN(1, 2))
-UNUSED(PIN(1, 1))
-UNUSED(PIN(1, 0))
-UNUSED(PIN(0, 7))
-UNUSED(PIN(0, 6))
-UNUSED(PIN(0, 5))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(C, 6))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 6))
-UNUSED(PIN(8, 0))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(D, 1))
-UNUSED(PIN(D, 3))
-UNUSED(PIN(7, 5))
-UNUSED(PIN(8, 6))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(7, 4))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(8, 5))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-/* TODO(Camera?) should have a poper config for this, PWM or not */
-ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
-ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
-
-
diff --git a/board/homestar/led.c b/board/homestar/led.c
deleted file mode 100644
index 3950ce1ec0..0000000000
--- a/board/homestar/led.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-#include "extpower.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-/* Battery LED blinks every per 400ms */
-#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
-	if (color == LED_AMBER) {
-		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
-		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED] != 0)
-		led_set_color(LED_RED);
-	else if (brightness[EC_LED_COLOR_GREEN] != 0)
-		led_set_color(LED_GREEN);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
-			if (percent <= BATTERY_LEVEL_CRITICAL) {
-				/* battery capa <= 5%, Red */
-				color = LED_RED;
-			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
-				/* 5% < battery capa < 97%, Orange */
-				color = LED_AMBER;
-			} else {
-				/* battery capa >= 97%, Green */
-				color = LED_GREEN;
-			}
-		}
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* Always indicate off on when discharging */
-		color = LED_OFF;
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error, Red on 1sec off 1sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_RED;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
-			color = LED_RED;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_RED : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/homestar/vif_override.xml b/board/homestar/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/homestar/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/host/battery.c b/board/host/battery.c
deleted file mode 100644
index 1228485ab7..0000000000
--- a/board/host/battery.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery driver.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "console.h"
-#include "test_util.h"
-#include "util.h"
-
-static uint16_t mock_smart_battery[SB_MANUFACTURER_DATA + 1];
-
-int sb_i2c_xfer(int port, uint16_t slave_addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
-{
-	if (out_size == 0)
-		return EC_SUCCESS;
-
-	if (port != I2C_PORT_BATTERY || slave_addr_flags != BATTERY_ADDR_FLAGS)
-		return EC_ERROR_INVAL;
-	if (out[0]  >= ARRAY_SIZE(mock_smart_battery))
-		return EC_ERROR_UNIMPLEMENTED;
-	if (out_size == 1) {
-		/* Read */
-		if (in_size != 2)
-			/* We are not doing a read16, assume read string */
-			return EC_SUCCESS;
-		else
-			*(uint16_t *)in = mock_smart_battery[out[0]];
-	} else {
-		/* write */
-		if (out_size != 3)
-			/* We are only expecting write 16 */
-			return EC_ERROR_UNIMPLEMENTED;
-		else
-			mock_smart_battery[out[0]] = (out[2] << 8) | out[1];
-	}
-	return EC_SUCCESS;
-}
-DECLARE_TEST_I2C_XFER(sb_i2c_xfer);
-
-int battery_time_at_rate(int rate, int *minutes)
-{
-	return EC_SUCCESS;
-}
-
-static const struct battery_info bat_info = {
-	/*
-	 * Design voltage
-	 *   max    = 8.4V
-	 *   normal = 7.4V
-	 *   min    = 6.0V
-	 */
-	.voltage_max    = 8400,
-	.voltage_normal = 7400,
-	.voltage_min    = 6000,
-
-	/* Pre-charge current: I <= 0.01C */
-	.precharge_current  = 64, /* mA */
-
-	/*
-	 * Operational temperature range
-	 *   0 <= T_charge    <= 50 deg C
-	 * -20 <= T_discharge <= 60 deg C
-	 */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c       = 0,
-	.charging_max_c       = 50,
-	.discharging_min_c    = -20,
-	.discharging_max_c    = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &bat_info;
-}
diff --git a/board/host/board.c b/board/host/board.c
deleted file mode 100644
index 191fd832e1..0000000000
--- a/board/host/board.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Emulator board-specific configuration */
-
-#include "battery.h"
-#include "button.h"
-#include "cros_board_info.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "inductive_charging.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "power_button.h"
-#include "spi.h"
-#include "temp_sensor.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * GPIO_0 is the name generated by the gpio.inc GPIO macros for all of the host
- * GPIO ports.  This maps back to 0, which is then ignored by the host GPIO mock
- * code.
- */
-#define GPIO_0  0
-
-#include "gpio_list.h"
-
-test_mockable enum battery_present battery_is_present(void)
-{
-	return BP_YES;
-}
-
-test_mockable_static int mock_temp_get_val(int idx, int *temp_ptr)
-{
-	*temp_ptr = 0;
-	return EC_SUCCESS;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0},
-	{"Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1},
-	{"Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2},
-	{"Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-test_mockable void button_interrupt(enum gpio_signal signal)
-{
-}
-
-test_mockable void fps_event(enum gpio_signal signal)
-{
-}
-
-#ifdef CONFIG_I2C
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-#ifdef I2C_PORT_BATTERY
-	{"battery", I2C_PORT_BATTERY, 100,  0, 0},
-#elif defined I2C_PORT_LIGHTBAR
-	{"lightbar", I2C_PORT_LIGHTBAR, 100,  0, 0},
-#elif defined I2C_PORT_HOST_TCPC
-	{"tcpc", I2C_PORT_HOST_TCPC, 100,  0, 0},
-#elif defined I2C_PORT_EEPROM
-	{"eeprom", I2C_PORT_EEPROM, 100, 0, 0},
-#elif defined I2C_PORT_WLC
-	{"wlc", I2C_PORT_WLC, 100, 0, 0},
-#endif
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-#endif
-
-#ifdef CONFIG_SPI_CONTROLLER
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ CONFIG_SPI_FP_PORT, 3, GPIO_SPI1_NSS },
-};
-
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-#endif
-
-#ifdef TEST_BUILD
-/* Poor source of entropy for testing purpose. */
-int board_get_entropy(void *buffer, int len)
-{
-	static uint32_t seed = 0xcafecafe;
-	int i = 0;
-	uint8_t *data = buffer;
-
-	for (i = 0; i < len; i++) {
-		seed *= 7;
-		data[i] = seed + (seed >> 24);
-	}
-
-	return 1;
-}
-#endif
-
-static uint8_t eeprom[CBI_IMAGE_SIZE];
-
-int eeprom_i2c_xfer(int port, uint16_t addr_flags,
-		    const uint8_t *out, int out_size,
-		    uint8_t *in, int in_size, int flags)
-{
-	static int offset;
-
-	if (port != I2C_PORT_EEPROM || addr_flags != I2C_ADDR_EEPROM_FLAGS)
-		return EC_ERROR_INVAL;
-
-	if (out_size == 1 && (flags & I2C_XFER_START)) {
-		offset = *out;
-	} else {
-		if (offset + out_size > sizeof(eeprom))
-			return EC_ERROR_OVERFLOW;
-		memcpy(&eeprom[offset], out, out_size);
-	}
-
-	if (in) {
-		if (offset + in_size > sizeof(eeprom))
-			return EC_ERROR_OVERFLOW;
-		memcpy(in, &eeprom[offset], in_size);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_TEST_I2C_XFER(eeprom_i2c_xfer);
diff --git a/board/host/board.h b/board/host/board.h
deleted file mode 100644
index f9d00961e7..0000000000
--- a/board/host/board.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-/* Default-yes, override to no by including fake_battery module. */
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#undef CONFIG_CMD_PD
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_FMAP
-#define CONFIG_POWER_BUTTON
-#undef CONFIG_WATCHDOG
-#define CONFIG_SWITCH
-#define CONFIG_INDUCTIVE_CHARGING
-
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 4
-
-#define CONFIG_WP_ACTIVE_HIGH
-
-#define CONFIG_LIBCRYPTOC
-
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-
-#include "gpio_signal.h"
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CPU = 0,
-	TEMP_SENSOR_BOARD,
-	TEMP_SENSOR_CASE,
-	TEMP_SENSOR_BATTERY,
-
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_CH_CHARGER_CURRENT,
-	ADC_AC_ADAPTER_ID_VOLTAGE,
-
-	ADC_CH_COUNT
-};
-
-/* Fake test charge suppliers */
-enum {
-	CHARGE_SUPPLIER_TEST1,
-	CHARGE_SUPPLIER_TEST2,
-	CHARGE_SUPPLIER_TEST3,
-	CHARGE_SUPPLIER_TEST4,
-	CHARGE_SUPPLIER_TEST5,
-	CHARGE_SUPPLIER_TEST6,
-	CHARGE_SUPPLIER_TEST7,
-	CHARGE_SUPPLIER_TEST8,
-	CHARGE_SUPPLIER_TEST9,
-	CHARGE_SUPPLIER_TEST10,
-	CHARGE_SUPPLIER_TEST_COUNT
-};
-
-/* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
-
-/* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  20000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-#define PD_MIN_CURRENT_MA     500
-#define PD_MIN_POWER_MW       7500
-
-/* Configuration for fake Fingerprint Sensor */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT    1 /* SPI1: third master config */
-
-#define CONFIG_RNG
-void fps_event(enum gpio_signal signal);
-
-#define CONFIG_CRC8
-
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_EEPROM		0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/host/build.mk b/board/host/build.mk
deleted file mode 100644
index 241f197342..0000000000
--- a/board/host/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=host
-
-board-y=board.o
-board-$(HAS_TASK_CHIPSET)+=chipset.o
-board-$(CONFIG_BATTERY_MOCK)+=battery.o charger.o
-board-$(CONFIG_FANS)+=fan.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_config.o
diff --git a/board/host/charger.c b/board/host/charger.c
deleted file mode 100644
index 4db1f44351..0000000000
--- a/board/host/charger.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock battery charger driver.
- */
-
-#include "battery_smart.h"
-#include "charger.h"
-#include "console.h"
-#include "common.h"
-#include "util.h"
-
-static const struct charger_info mock_charger_info = {
-	.name         = "MockCharger",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
-	.voltage_step = 16,
-	.current_max  = 8192,
-	.current_min  = 128,
-	.current_step = 128,
-	.input_current_max  = 8064,
-	.input_current_min  = 128,
-	.input_current_step = 128,
-};
-
-#define OPTION_CHARGE_INHIBIT BIT(0)
-
-static uint32_t mock_option;
-static uint32_t mock_mode;
-static uint32_t mock_current;
-static uint32_t mock_voltage;
-static uint32_t mock_input_current;
-
-static const struct charger_info *mock_get_info(int chgnum)
-{
-	return &mock_charger_info;
-}
-
-
-static enum ec_error_list mock_get_status(int chgnum, int *status)
-{
-	*status = CHARGER_LEVEL_2;
-	if (mock_mode & CHARGE_FLAG_INHIBIT_CHARGE)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_set_mode(int chgnum, int mode)
-{
-	if (mode & CHARGE_FLAG_INHIBIT_CHARGE)
-		mock_mode |= OPTION_CHARGE_INHIBIT;
-	else
-		mock_mode &= ~OPTION_CHARGE_INHIBIT;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_get_current(int chgnum, int *current)
-{
-	*current = mock_current;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_set_current(int chgnum, int current)
-{
-	const struct charger_info *info = mock_get_info(chgnum);
-
-	if (current > 0 && current < info->current_min)
-		current = info->current_min;
-	if (current > info->current_max)
-		current = info->current_max;
-
-	if (mock_current != current)
-		ccprintf("Charger set current: %d\n", current);
-	mock_current = current;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list mock_get_voltage(int chgnum, int *voltage)
-{
-	*voltage = mock_voltage;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_set_voltage(int chgnum, int voltage)
-{
-	mock_voltage = voltage;
-	ccprintf("Charger set voltage: %d\n", voltage);
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_get_option(int chgnum, int *option)
-{
-	*option = mock_option;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_set_option(int chgnum, int option)
-{
-	mock_option = option;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_manufacturer_id(int chgnum, int *id)
-{
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_device_id(int chgnum, int *id)
-{
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list mock_get_input_current_limit(int chgnum,
-						       int *input_current)
-{
-	*input_current = mock_input_current;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_set_input_current_limit(int chgnum, int current)
-{
-	const struct charger_info *info = mock_get_info(chgnum);
-
-	if (current < info->input_current_min)
-		current = info->input_current_min;
-	if (current > info->input_current_max)
-		current = info->input_current_max;
-
-	if (mock_input_current != current)
-		ccprintf("Charger set input current: %d\n", current);
-
-	mock_input_current = current;
-	return EC_SUCCESS;
-}
-
-
-static enum ec_error_list mock_post_init(int chgnum)
-{
-	mock_current = mock_input_current = CONFIG_CHARGER_INPUT_CURRENT;
-	return EC_SUCCESS;
-}
-
-const struct charger_drv mock_drv = {
-	.post_init = &mock_post_init,
-	.get_info = &mock_get_info,
-	.get_status = &mock_get_status,
-	.set_mode = &mock_set_mode,
-	.get_current = &mock_get_current,
-	.set_current = &mock_set_current,
-	.get_voltage = &mock_get_voltage,
-	.set_voltage = &mock_set_voltage,
-	.set_input_current_limit = &mock_set_input_current_limit,
-	.get_input_current_limit = &mock_get_input_current_limit,
-	.manufacturer_id = &mock_manufacturer_id,
-	.device_id = &mock_device_id,
-	.get_option = &mock_get_option,
-	.set_option = &mock_set_option,
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.drv = &mock_drv,
-	},
-};
diff --git a/board/host/chipset.c b/board/host/chipset.c
deleted file mode 100644
index 3cb859eb29..0000000000
--- a/board/host/chipset.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Chipset module for emulator */
-
-#include <stdio.h>
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "task.h"
-#include "test_util.h"
-
-static int chipset_state = CHIPSET_STATE_SOFT_OFF;
-static int power_on_req;
-static int power_off_req;
-
-test_mockable void chipset_reset(enum chipset_reset_reason reason)
-{
-	fprintf(stderr, "Chipset reset: %d!\n", reason);
-}
-
-test_mockable void chipset_throttle_cpu(int throttle)
-{
-	/* Do nothing */
-}
-
-test_mockable void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	/* Do nothing */
-}
-
-test_mockable int chipset_in_state(int state_mask)
-{
-	return state_mask & chipset_state;
-}
-
-test_mockable int chipset_in_or_transitioning_to_state(int state_mask)
-{
-	return state_mask & chipset_state;
-}
-
-void test_chipset_on(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		return;
-	power_on_req = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void test_chipset_off(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	power_off_req = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-test_mockable void chipset_task(void)
-{
-	while (1) {
-		while (!power_on_req)
-			task_wait_event(-1);
-		power_on_req = 0;
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-		chipset_state = CHIPSET_STATE_ON;
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		while (!power_off_req)
-			task_wait_event(-1);
-		power_off_req = 0;
-		chipset_state = CHIPSET_STATE_SOFT_OFF;
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-	}
-}
diff --git a/board/host/ec.tasklist b/board/host/ec.tasklist
deleted file mode 100644
index c056c51e8a..0000000000
--- a/board/host/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/host/fan.c b/board/host/fan.c
deleted file mode 100644
index 1e1001f1cd..0000000000
--- a/board/host/fan.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mocked fan implementation for tests */
-
-#include "fan.h"
-#include "util.h"
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1500,
-	.rpm_max = 5000,
-};
-
-const struct fan_t fans[CONFIG_FANS] = {
-	{ .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-static int mock_enabled;
-void fan_set_enabled(int ch, int enabled)
-{
-	mock_enabled = enabled;
-}
-int fan_get_enabled(int ch)
-{
-	return mock_enabled;
-}
-
-static int mock_percent;
-void fan_set_duty(int ch, int percent)
-{
-	mock_percent = percent;
-}
-int fan_get_duty(int ch)
-{
-	return mock_percent;
-}
-
-static int mock_rpm_mode;
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	mock_rpm_mode = rpm_mode;
-}
-int fan_get_rpm_mode(int ch)
-{
-	return mock_rpm_mode;
-}
-
-int mock_rpm;
-void fan_set_rpm_target(int ch, int rpm)
-{
-	mock_rpm = rpm;
-}
-int fan_get_rpm_actual(int ch)
-{
-	return mock_rpm;
-}
-int fan_get_rpm_target(int ch)
-{
-	return mock_rpm;
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	return 0;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/* nothing to do */
-}
diff --git a/board/host/gpio.inc b/board/host/gpio.inc
deleted file mode 100644
index ce69385259..0000000000
--- a/board/host/gpio.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(LID_OPEN,             PIN(0, 0), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(AC_PRESENT,           PIN(0, 2), GPIO_INT_BOTH, extpower_interrupt)
-GPIO_INT(VOLUME_DOWN_L,        PIN(0, 3), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(VOLUME_UP_L,          PIN(0, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(CHARGE_DONE,          PIN(0, 5), GPIO_INT_BOTH, inductive_charging_interrupt)
-/* Fingerprint */
-GPIO_INT(FPS_INT,              PIN(0, 14), GPIO_INT_RISING, fps_event)
-
-GPIO(EC_INT_L,             PIN(0, 6), 0)
-GPIO(WP,                   PIN(0, 7), 0)
-GPIO(ENTERING_RW,          PIN(0, 8), 0)
-GPIO(PCH_BKLTEN,           PIN(0, 9), 0)
-GPIO(ENABLE_BACKLIGHT,     PIN(0, 10), 0)
-
-/* Inductive charging */
-GPIO(CHARGE_EN,            PIN(0, 11), 0)
-GPIO(BASE_CHG_VDD_EN,      PIN(0, 12), 0)
-
-/* Fingerprint */
-GPIO(SPI1_NSS,              PIN(0, 13), GPIO_OUT_HIGH)
-
-GPIO(USB_C0_DISCHARGE,     PIN(0, 15), 0)
-
-GPIO(I2C_SCL,             PIN(0, 16),  GPIO_INPUT)
-GPIO(I2C_SDA,             PIN(0, 17),  GPIO_INPUT)
-
-GPIO(EC_CBI_WP,           PIN(0, 18), GPIO_OUT_LOW)
diff --git a/board/host/usb_pd_config.c b/board/host/usb_pd_config.c
deleted file mode 100644
index 91c30d1755..0000000000
--- a/board/host/usb_pd_config.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#include "test_util.h"
-
-test_mockable void pd_select_polarity(int port, int polarity)
-{
-	/* Not implemented */
-}
-
-test_mockable void pd_tx_init(void)
-{
-	/* Not implemented */
-}
-
-test_mockable void pd_set_host_mode(int port, int enable)
-{
-	/* Not implemented */
-}
-
-test_mockable void pd_config_init(int port, uint8_t power_role)
-{
-	/* Not implemented */
-}
-
-test_mockable int pd_adc_read(int port, int cc)
-{
-	/* Not implemented */
-	return 0;
-}
-
diff --git a/board/host/usb_pd_config.h b/board/host/usb_pd_config.h
deleted file mode 100644
index fb12b2ce7d..0000000000
--- a/board/host/usb_pd_config.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Use software CRC */
-#define CONFIG_SW_CRC
-
-void pd_select_polarity(int port, int polarity);
-
-void pd_tx_init(void);
-
-void pd_set_host_mode(int port, int enable);
-
-void pd_config_init(int port, uint8_t power_role);
-
-int pd_adc_read(int port, int cc);
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/host/usb_pd_policy.c b/board/host/usb_pd_policy.c
deleted file mode 100644
index 23285f4838..0000000000
--- a/board/host/usb_pd_policy.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,   900, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-test_mockable int pd_set_power_supply_ready(int port)
-{
-	/* Not implemented */
-	return EC_SUCCESS;
-}
-
-test_mockable void pd_power_supply_reset(int port)
-{
-	/* Not implemented */
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* Not implemented */
-}
-
-test_mockable int pd_snk_is_vbus_provided(int port)
-{
-	/* Not implemented */
-	return 1;
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/* Always allow power swap */
-	return 1;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/* Always allow data swap */
-	return 1;
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-}
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-			     uint32_t **rpayload)
-{
-	return 0;
-}
diff --git a/board/host/vif_override.xml b/board/host/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/host/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/icarus/battery.c b/board/icarus/battery.c
deleted file mode 100644
index 6f6b49899a..0000000000
--- a/board/icarus/battery.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* Panasonic AP19B5K Battery Information */
-	[BATTERY_PANASONIC_AP19B5K_KT00305011] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305011",
-			.device_name = "AP19B5K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP19B8K Battery Information */
-	 [BATTERY_LGC_AP19B8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G022",
-			.device_name = "AP19B8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* COSMX AP20CBL Battery Information */
-	 [BATTERY_COSMX_AP20CBL] = {
-		.fuel_gauge = {
-			.manuf_name = "COSMX KT0030B002",
-			.device_name = "AP20CBL",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* SMP AP18C7K Battery Information */
-	 [BATTERY_SMP_AP18C7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP KT00307010",
-			.device_name = "AP18C7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/icarus/board.c b/board/icarus/board.c
deleted file mode 100644
index bffad091fa..0000000000
--- a/board/icarus/board.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1},
-	{GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3},
-	{GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4},
-	{GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5},
-	{GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7},
-	{GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1},
-	{GPIO_KSO_H, 6}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH1},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH2},
-	[ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec",   IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"other",   IT83XX_I2C_CH_B, 100, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"battery", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-#define VBUS_THRESHOLD_MV 4200
-int pd_snk_is_vbus_provided(int port)
-{
-	/* This board has only one port. */
-	if (!port)
-		return adc_read_channel(ADC_VBUS) > VBUS_THRESHOLD_MV ? 1 : 0;
-	else
-		return 0;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/icarus/board.h b/board/icarus/board.h
deleted file mode 100644
index b9232d65a5..0000000000
--- a/board/icarus/board.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_IT81202
-
-#include "baseboard.h"
-
-/* TODO: remove me once we fix IT83XX_ILM_BLOCK_SIZE out of space issue */
-#undef CONFIG_LTO
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#undef CONFIG_ACCEL_FIFO
-#undef CONFIG_ACCEL_FIFO_SIZE
-#undef CONFIG_ACCEL_FIFO_THRES
-
-/* I2C ports */
-#define I2C_PORT_BC12               IT83XX_I2C_CH_C
-#define I2C_PORT_TCPC0              IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX            IT83XX_I2C_CH_C
-#define I2C_PORT_CHARGER            IT83XX_I2C_CH_A
-#define I2C_PORT_SENSORS            IT83XX_I2C_CH_B
-#define I2C_PORT_ACCEL              I2C_PORT_SENSORS
-#define I2C_PORT_BATTERY            IT83XX_I2C_CH_A
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_LED_ONOFF_STATES
-
-#undef CONFIG_GMR_TABLET_MODE
-#undef GMR_TABLET_MODE_GPIO_L
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_PANASONIC_AP19B5K_KT00305011,
-	BATTERY_LGC_AP19B8K,
-	BATTERY_COSMX_AP20CBL,
-	BATTERY_SMP_AP18C7K,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for AP jump to BL */
-void emmc_ap_jump_to_bl(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/icarus/build.mk b/board/icarus/build.mk
deleted file mode 100644
index 9ca7933e2a..0000000000
--- a/board/icarus/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# IC is ITE IT81202
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/icarus/ec.tasklist b/board/icarus/ec.tasklist
deleted file mode 100644
index e8ad538bc2..0000000000
--- a/board/icarus/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280)
diff --git a/board/icarus/gpio.inc b/board/icarus/gpio.inc
deleted file mode 100644
index a3a097c17b..0000000000
--- a/board/icarus/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(POWER_BUTTON_L,    PIN(E, 4), GPIO_INT_BOTH,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(F, 3), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(D, 3), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-GPIO_INT_RO(BOOTBLOCK_EN_L, PIN(J, 1), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         emmc_ap_jump_to_bl)
-GPIO_INT(SPI0_CS,           PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(E, 2), GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(E, 5), GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(J, 6), GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 7), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(UART1_RX,          PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-/* Unimplemented interrupts */
-GPIO(ACCEL_INT_ODL,         PIN(J, 2), GPIO_INPUT)
-GPIO(TABLET_MODE_L,         PIN(J, 7), GPIO_INPUT)
-GPIO(VOLUME_DOWN_L,         PIN(D, 5), GPIO_INPUT)
-GPIO(VOLUME_UP_L,           PIN(D, 6), GPIO_INPUT)
-GPIO(ALS_RGB_INT_ODL,       PIN(F, 0), GPIO_INPUT)
-GPIO(LID_ACCEL_INT_ODL,     PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,          PIN(B, 6), GPIO_OUT_LOW)
-/* 1.8V PP or 1.8V OD output with external 10K PU  */
-GPIO(PMIC_WATCHDOG_L,       PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-/* OD output with 5VT (there is 5V internal PU on PWRKEY of MT6358) */
-GPIO(PMIC_EN_ODL,           PIN(E, 1), GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-/* EC programming */
-GPIO(I2C_E_SCL,              PIN(A, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_E_SDA,              PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-/* battery and charger */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT)
-/* sensor */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-/* typec */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT)
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT)
-
-/* Other input pins */
-/* TODO(WP_L): change to interrupt pin ? */
-GPIO(WP_L,                 PIN(I, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_FLASH_WP_ODL */
-GPIO(CCD_MODE_ODL,         PIN(C, 4), GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(C, 0), GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EN_USBA_5V,           PIN(B, 7), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 5), GPIO_ODR_HIGH)  /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(H, 5), GPIO_ODR_HIGH)  /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(J, 0), GPIO_ODR_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(H, 3), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,  PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,  PIN(H, 2), GPIO_OUT_LOW)
-
-/* LEDs */
-GPIO(LED_BLUE,             PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(LED_GREEN,            PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(LED_ORANGE,           PIN(A, 0), GPIO_OUT_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(D, 0), GPIO_OUT_LOW)
-
-/* Unimplemented Pins  */
-GPIO(PG_PP5000_A_OD,       PIN(A, 6), GPIO_INPUT)
-GPIO(USB_A0_OC_ODL,        PIN(A, 7), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,       PIN(C, 3), GPIO_INPUT)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C0_PD_INT_ODL,    PIN(D, 1), GPIO_INPUT) /* no used on this board */
-GPIO(EN_PP5000A_USM,       PIN(D, 7), GPIO_INPUT)
-GPIO(EN_USBC_CHARGE_L,     PIN(F, 1), GPIO_INPUT)
-GPIO(EN_PP5000_USBC,       PIN(H, 4), GPIO_INPUT)
-GPIO(PP1800_H1_PG,         PIN(H, 6), GPIO_INPUT)
-
-/* NC pins, ensure they aren't in floating state. */
-GPIO(NC_GPA3,              PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPB2,              PIN(B, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPD2,              PIN(D, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPD4,              PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE0,              PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE3,              PIN(E, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE7,              PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-/*
- * ADC pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPI5,              PIN(I, 5), GPIO_OUT_LOW)
-GPIO(NC_GPI7,              PIN(I, 7), GPIO_OUT_LOW)
-
-GPIO(NC_GPJ4,              PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPJ5,              PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-/*
- * GPG3,4,5,7 don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPG0,              PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-/* Don't touch GPG1 and GPG2 */
-GPIO(NC_GPG3,              PIN(G, 3), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_MOSI,    PIN(G, 4), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_MISO,    PIN(G, 5), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_CLK,     PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_SPI_FLASH_CS_L,    PIN(G, 7), GPIO_OUT_LOW)
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_LOW)	     /* KSO2 inverted */
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0x4F), 0, MODULE_ADC, 0)  /* ADC 0,1,2,3,6 */
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-/* EMMC SPI SLAVE M2:CLK, M3:CMD, M6:DATA0 */
-ALTERNATE(PIN_MASK(M, 0x4C), 0, MODULE_SPI_FLASH,  0)
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI for communication */
diff --git a/board/icarus/led.c b/board/icarus/led.c
deleted file mode 100644
index 076199b2ed..0000000000
--- a/board/icarus/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Jacuzzi
- */
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_ORANGE, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_BLUE, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_GREEN, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		break;
-	}
-}
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	}
-}
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/icarus/vif_override.xml b/board/icarus/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/icarus/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/it83xx_evb/board.c b/board/it83xx_evb/board.c
deleted file mode 100644
index a18b8b3b70..0000000000
--- a/board/it83xx_evb/board.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* IT83xx development board configuration */
-
-#include "adc_chip.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWM_HW_CH_DCR7,
-		.flags = 0,
-		.freq_hz = 30000,
-		.pcfsr_sel = PWM_PRESCALER_C4,
-	},
-	[PWM_CH_WITH_DSLEEP_FLAG] = {
-		.channel = PWM_HW_CH_DCR0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 100,
-		.pcfsr_sel = PWM_PRESCALER_C6,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	[ADC_VBUSSA] = {
-		.name = "ADC_VBUSSA",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0, /* GPI0, ADC0 */
-	},
-	[ADC_VBUSSB] = {
-		.name = "ADC_VBUSSB",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH1, /* GPI1, ADC1 */
-	},
-	[ADC_EVB_CH_13] = {
-		.name = "ADC_EVB_CH_13",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13, /* GPL0, ADC13 */
-	},
-	[ADC_EVB_CH_14] = {
-		.name = "ADC_EVB_CH_14",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH14, /* GPL1, ADC14 */
-	},
-	[ADC_EVB_CH_15] = {
-		.name = "ADC_EVB_CH_15",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15, /* GPL2, ADC15 */
-	},
-	[ADC_EVB_CH_16] = {
-		.name = "ADC_EVB_CH_16",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16, /* GPL3, ADC16 */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h
deleted file mode 100644
index 754474174c..0000000000
--- a/board/it83xx_evb/board.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx development board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_DAC
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_WITH_DSLEEP_FLAG,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUSSA,
-	ADC_VBUSSB,
-	ADC_EVB_CH_13,
-	ADC_EVB_CH_14,
-	ADC_EVB_CH_15,
-	ADC_EVB_CH_16,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/it83xx_evb/build.mk b/board/it83xx_evb/build.mk
deleted file mode 100644
index e4c8c01b89..0000000000
--- a/board/it83xx_evb/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8390/IT8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=ite_evb
-
-board-y=board.o
diff --git a/board/it83xx_evb/ec.tasklist b/board/it83xx_evb/ec.tasklist
deleted file mode 100644
index 3ca78d55db..0000000000
--- a/board/it83xx_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc
deleted file mode 100644
index 52df89e5cb..0000000000
--- a/board/it83xx_evb/gpio.inc
+++ /dev/null
@@ -1,76 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
-#endif
-GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
-GPIO_INT(WP_L,           PIN(E, 1), GPIO_INT_BOTH,                  switch_interrupt)         /* Write protect input */
-#ifdef CONFIG_LOW_POWER_IDLE
-GPIO_INT(UART1_RX,       PIN(B, 0), GPIO_INT_FALLING,               uart_deepsleep_interrupt) /* UART1 RX input */
-#endif
-
-GPIO(PCH_SMI_L,      PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(PCH_SCI_L,      PIN(D, 4), GPIO_OUT_HIGH)
-GPIO(GATE_A20_H,     PIN(B, 5), GPIO_OUT_HIGH)
-GPIO(SYS_RESET_L,    PIN(B, 6), GPIO_OUT_HIGH)
-GPIO(LPC_CLKRUN_L,   PIN(H, 0), GPIO_OUT_LOW)
-GPIO(PCH_WAKE_L,     PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */
-
-GPIO(I2C_A_SCL,      PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,      PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,      PIN(C, 2), GPIO_INPUT)
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-GPIO(I2C_C_SCL,      PIN(C, 7), GPIO_INPUT)
-#else
-GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
-#endif
-GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
-
-GPIO(I2C_E_SCL,      PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,      PIN(E, 7), GPIO_INPUT)
-
-#ifdef CONFIG_UART_HOST
-GPIO(UART2_SIN1,     PIN(H, 1), GPIO_INPUT)
-GPIO(UART2_SOUT1,    PIN(H, 2), GPIO_INPUT)
-#endif
-
-/* KSO/KSI pins can be used as GPIO input. */
-GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT)
-GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
-#ifdef CONFIG_UART_HOST
-ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
-#endif
-ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCK of SPI */
-ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_CONTROLLER, 0)  /* SMOSI/SMISO of SPI */
-ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE1# of SPI */
-ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE0# of SPI */
-ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0)             /* PWM7 for FAN1 */
-ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0)             /* TACH0A for FAN1 */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-ALTERNATE(PIN_MASK(C, 0x86), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA, C SCL */
-ALTERNATE(PIN_MASK(F, 0x80), 1, MODULE_I2C, 0)             /* I2C C SDA */
-#else
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
-#endif
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(I, 0x03), 1, MODULE_ADC, 0)             /* ADC CH0, CH1 */
-ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0)             /* ADC CH13-CH16 */
-ALTERNATE(PIN_MASK(J, 0x3C), 1, MODULE_DAC, 0)             /* DAC CH2.3.4.5 */
diff --git a/board/it8xxx2_evb/board.c b/board/it8xxx2_evb/board.c
deleted file mode 100644
index 0daa3d48cd..0000000000
--- a/board/it8xxx2_evb/board.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* IT8xxx2 development board configuration */
-
-#include "adc_chip.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = PWM_HW_CH_DCR7,
-		.flags = 0,
-		.freq_hz = 30000,
-		.pcfsr_sel = PWM_PRESCALER_C4,
-	},
-	[PWM_CH_WITH_DSLEEP_FLAG] = {
-		.channel = PWM_HW_CH_DCR0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 100,
-		.pcfsr_sel = PWM_PRESCALER_C6,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	[ADC_VBUSSA] = {
-		.name = "ADC_VBUSSA",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0, /* GPI0, ADC0 */
-	},
-	[ADC_VBUSSB] = {
-		.name = "ADC_VBUSSB",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH1, /* GPI1, ADC1 */
-	},
-	[ADC_EVB_CH_13] = {
-		.name = "ADC_EVB_CH_13",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13, /* GPL1, ADC13 */
-	},
-	[ADC_EVB_CH_14] = {
-		.name = "ADC_EVB_CH_14",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH14, /* GPL2, ADC14 */
-	},
-	[ADC_EVB_CH_15] = {
-		.name = "ADC_EVB_CH_15",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15, /* GPL3, ADC15 */
-	},
-	[ADC_EVB_CH_16] = {
-		.name = "ADC_EVB_CH_16",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16, /* GPL0, ADC16 */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/it8xxx2_evb/board.h b/board/it8xxx2_evb/board.h
deleted file mode 100644
index 1369e43496..0000000000
--- a/board/it8xxx2_evb/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT8xxx2 development board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#include "baseboard.h"
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_WITH_DSLEEP_FLAG,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUSSA,
-	ADC_VBUSSB,
-	ADC_EVB_CH_13,
-	ADC_EVB_CH_14,
-	ADC_EVB_CH_15,
-	ADC_EVB_CH_16,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/it8xxx2_evb/build.mk b/board/it8xxx2_evb/build.mk
deleted file mode 100644
index b54a2fcbb6..0000000000
--- a/board/it8xxx2_evb/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202ax_1024
-BASEBOARD:=ite_evb
-
-board-y=board.o
diff --git a/board/it8xxx2_evb/ec.tasklist b/board/it8xxx2_evb/ec.tasklist
deleted file mode 100644
index ff184489e3..0000000000
--- a/board/it8xxx2_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc
deleted file mode 100644
index 8a7f593ab6..0000000000
--- a/board/it8xxx2_evb/gpio.inc
+++ /dev/null
@@ -1,75 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
-#endif
-GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,   lid_interrupt)
-GPIO_INT(WP_L,           PIN(I, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   switch_interrupt)         /* Write protect input */
-#ifdef CONFIG_LOW_POWER_IDLE
-GPIO_INT(UART1_RX,       PIN(B, 0), GPIO_INT_FALLING | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART1 RX input */
-#endif
-
-GPIO(PCH_SMI_L,      PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(PCH_SCI_L,      PIN(D, 4), GPIO_OUT_HIGH)
-GPIO(GATE_A20_H,     PIN(B, 5), GPIO_OUT_HIGH)
-GPIO(SYS_RESET_L,    PIN(B, 6), GPIO_OUT_HIGH)
-GPIO(LPC_CLKRUN_L,   PIN(H, 0), GPIO_OUT_LOW)
-GPIO(PCH_WAKE_L,     PIN(B, 7), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */
-
-GPIO(I2C_A_SCL,      PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,      PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,      PIN(C, 2), GPIO_INPUT)
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-GPIO(I2C_C_SCL,      PIN(C, 7), GPIO_INPUT)
-#else
-GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
-#endif
-GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
-
-GPIO(I2C_E_SCL,      PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,      PIN(E, 7), GPIO_INPUT)
-
-#ifdef CONFIG_UART_HOST
-GPIO(UART2_SIN1,     PIN(H, 1), GPIO_INPUT)
-GPIO(UART2_SOUT1,    PIN(H, 2), GPIO_INPUT)
-#endif
-
-/* KSO/KSI pins can be used as GPIO input. */
-GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT)
-GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
-#ifdef CONFIG_UART_HOST
-ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
-#endif
-ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCK of SPI */
-ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI_CONTROLLER, 0)  /* SMOSI/SMISO of SPI */
-ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE1# of SPI */
-ALTERNATE(PIN_MASK(G, 0x04), 3, MODULE_SPI_CONTROLLER, 0)  /* SSCE0# of SPI */
-ALTERNATE(PIN_MASK(A, 0x80), 1, MODULE_PWM, 0)             /* PWM7 for FAN1 */
-ALTERNATE(PIN_MASK(D, 0x40), 3, MODULE_PWM, 0)             /* TACH0A for FAN1 */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-ALTERNATE(PIN_MASK(C, 0x86), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA, C SCL */
-ALTERNATE(PIN_MASK(F, 0x80), 1, MODULE_I2C, 0)             /* I2C C SDA */
-#else
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
-#endif
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(I, 0x03), 1, MODULE_ADC, 0)             /* ADC CH0, CH1 */
-ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0)             /* ADC CH13-CH16 */
diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c
deleted file mode 100644
index 7c239866f0..0000000000
--- a/board/it8xxx2_pdevb/board.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* IT8xxx2 PD development board configuration */
-
-#include "adc_chip.h"
-#include "battery.h"
-#include "console.h"
-#include "it83xx_pd.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define USB_PD_PORT_ITE_0   0
-#define USB_PD_PORT_ITE_1   1
-#define USB_PD_PORT_ITE_2   2
-#define RESISTIVE_DIVIDER   11
-
-int board_get_battery_soc(void)
-{
-	CPRINTS("%s", __func__);
-	return 100;
-}
-
-enum battery_present battery_is_present(void)
-{
-	CPRINTS("%s", __func__);
-	return BP_NO;
-}
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so needn't i2c config */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so needn't i2c config */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	int cc1_enabled = 0, cc2_enabled = 0;
-
-	if (cc_pin != USBPD_CC_PIN_1)
-		cc2_enabled = enabled;
-	else
-		cc1_enabled = enabled;
-
-	if (port == USBPD_PORT_A) {
-		gpio_set_level(GPIO_USBPD_PORTA_CC2_VCONN, cc2_enabled);
-		gpio_set_level(GPIO_USBPD_PORTA_CC1_VCONN, cc1_enabled);
-	} else if (port == USBPD_PORT_B) {
-		gpio_set_level(GPIO_USBPD_PORTB_CC2_VCONN, cc2_enabled);
-		gpio_set_level(GPIO_USBPD_PORTB_CC1_VCONN, cc1_enabled);
-	} else if (port == USBPD_PORT_C) {
-		gpio_set_level(GPIO_USBPD_PORTC_CC2_VCONN, cc2_enabled);
-		gpio_set_level(GPIO_USBPD_PORTC_CC1_VCONN, cc1_enabled);
-	}
-
-	CPRINTS("p%d Vconn cc1 %d, cc2 %d (On/Off)", port, cc1_enabled,
-		cc2_enabled);
-}
-
-void board_pd_vbus_ctrl(int port, int enabled)
-{
-	CPRINTS("p%d Vbus %d(En/Dis)", port, enabled);
-
-	if (port == USBPD_PORT_A) {
-		gpio_set_level(GPIO_USBPD_PORTA_VBUS_INPUT, !enabled);
-		gpio_set_level(GPIO_USBPD_PORTA_VBUS_OUTPUT, enabled);
-		if (!enabled) {
-			gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
-		}
-		gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 0);
-	} else if (port == USBPD_PORT_B) {
-		gpio_set_level(GPIO_USBPD_PORTB_VBUS_INPUT, !enabled);
-		gpio_set_level(GPIO_USBPD_PORTB_VBUS_OUTPUT, enabled);
-		if (!enabled) {
-			gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
-		}
-		gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 0);
-	} else if (port == USBPD_PORT_C) {
-		gpio_set_level(GPIO_USBPD_PORTC_VBUS_INPUT, !enabled);
-		gpio_set_level(GPIO_USBPD_PORTC_VBUS_OUTPUT, enabled);
-		if (!enabled) {
-			gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
-		}
-		gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 0);
-	}
-
-	if (enabled)
-		udelay(10*MSEC); /* 10ms is a try and error value */
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	CPRINTS("p%d %s", port, __func__);
-}
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/*
-	 * The register value of ADC reading convert to mV (= register value *
-	 * reading max mV / 10 bit solution 1024).
-	 * NOTE: If the ADC channel measure VBUS:
-	 *       the max reading mv value is the result of resistive divider,
-	 *       so VBUS = reading max mv * resistive divider
-	 *       (check HW schematic).
-	 */
-	[ADC_VBUSSA] = {
-		.name = "ADC_VBUSSA",
-		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH7, /* GPI7, ADC7 */
-	},
-	[ADC_VBUSSB] = {
-		.name = "ADC_VBUSSB",
-		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3, /* GPI3, ADC3 */
-	},
-	[ADC_VBUSSC] = {
-		.name = "ADC_VBUSSC",
-		.factor_mul = ADC_MAX_MVOLT * RESISTIVE_DIVIDER,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16, /* GPL0, ADC16 */
-	},
-	[ADC_EVB_CH_13] = {
-		.name = "ADC_EVB_CH_13",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13, /* GPL1, ADC13 */
-	},
-	[ADC_EVB_CH_14] = {
-		.name = "ADC_EVB_CH_14",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH14, /* GPL2, ADC14 */
-	},
-	[ADC_EVB_CH_15] = {
-		.name = "ADC_EVB_CH_15",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15, /* GPL3, ADC15 */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h
deleted file mode 100644
index 8646c6c7b3..0000000000
--- a/board/it8xxx2_pdevb/board.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT8xxx2 PD development board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#include "baseboard.h"
-
-/*
- * Enable PD in RO image for TCPMv2, otherwise there is only Type-c functions.
- * NOTE: This configuration is only for development board and will never be
- *       released on a chrome os device.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* EC configurations, unnecessarily for PD */
-#undef CONFIG_FANS
-#undef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-#undef CONFIG_IT83XX_SMCLK2_ON_GPC7
-#undef CONFIG_KEYBOARD_PROTOCOL_8042
-#undef CONFIG_PECI
-#undef CONFIG_PECI_COMMON
-#undef CONFIG_PECI_TJMAX
-#undef CONFIG_POWER_BUTTON
-#undef CONFIG_PWM
-#undef CONFIG_SPI_CONTROLLER
-#undef CONFIG_SPI_FLASH_PORT
-#undef CONFIG_UART_HOST
-#undef CONFIG_HOSTCMD_LPC
-#undef CONFIG_CMD_MMAPINFO
-#undef CONFIG_SWITCH
-
-/* PD */
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_3A_PORTS 0
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT    2
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   2
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_VBOOT_HASH
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum pwm_channel {
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUSSA,
-	ADC_VBUSSB,
-	ADC_VBUSSC,
-	ADC_EVB_CH_13,
-	ADC_EVB_CH_14,
-	ADC_EVB_CH_15,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-/* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
-/* TODO: determine the following board specific type-C power constants */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-void board_pd_vbus_ctrl(int port, int enabled);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/it8xxx2_pdevb/build.mk b/board/it8xxx2_pdevb/build.mk
deleted file mode 100644
index b54a2fcbb6..0000000000
--- a/board/it8xxx2_pdevb/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202ax_1024
-BASEBOARD:=ite_evb
-
-board-y=board.o
diff --git a/board/it8xxx2_pdevb/ec.tasklist b/board/it8xxx2_pdevb/ec.tasklist
deleted file mode 100644
index 41fc733526..0000000000
--- a/board/it8xxx2_pdevb/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/it8xxx2_pdevb/gpio.inc b/board/it8xxx2_pdevb/gpio.inc
deleted file mode 100644
index afc83a82c3..0000000000
--- a/board/it8xxx2_pdevb/gpio.inc
+++ /dev/null
@@ -1,74 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(WP_L,           PIN(I, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   switch_interrupt)          /* Write protect input */
-#ifdef CONFIG_LOW_POWER_IDLE
-GPIO_INT(UART1_RX,       PIN(B, 0), GPIO_INT_FALLING | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART1 RX input */
-#endif
-
-/*
- * Because HW port0 and port1 cc pin order invert, FW invert it again.
- * ex. FW portA pins are mapping to: HW port1 GPF4, GPF5, ADC7, Vbus, Vconn.
- *     FW portB pins are mapping to: HW port0 GPH1, GPH2, ADC3, Vbus, Vconn.
- *     FW portC pins are mapping to: HW port3 GPP0, GPP1, ADC16, Vbus, Vconn.
- */
-GPIO(USBPD_PORTA_VBUS_SEN1P1, PIN(J, 0), GPIO_OUT_LOW)  /* VBUSSEN1P1 */
-GPIO(USBPD_PORTA_VBUS_DROP,   PIN(F, 3), GPIO_OUT_LOW)  /* VBUSDISP1 */
-GPIO(USBPD_PORTA_VBUS_OUTPUT, PIN(F, 1), GPIO_OUT_LOW)  /* VBUSOUTSWENP1 */
-GPIO(USBPD_PORTA_VBUS_INPUT,  PIN(E, 3), GPIO_OUT_HIGH) /* VBUSINSWENP1 */
-GPIO(USBPD_PORTA_VBUS_OV_OC,  PIN(C, 3), GPIO_INPUT)    /* VSWFLTP1 1? */
-GPIO(USBPD_PORTA_CC1_VCONN,   PIN(E, 1), GPIO_OUT_LOW)
-GPIO(USBPD_PORTA_CC2_VCONN,   PIN(J, 5), GPIO_OUT_LOW)
-GPIO(USBPD_PORTA_VCONN_OV_OC, PIN(B, 5), GPIO_INPUT)    /* VCONSWFLTP1 1? */
-GPIO(USBPD_PORTB_VBUS_SEN1P0, PIN(H, 0), GPIO_OUT_LOW)  /* VBUSSEN1P0 */
-GPIO(USBPD_PORTB_VBUS_DROP,   PIN(D, 5), GPIO_OUT_LOW)  /* VBUSDISP0 */
-GPIO(USBPD_PORTB_VBUS_OUTPUT, PIN(A, 6), GPIO_OUT_LOW)  /* VBUSOUTSWENP0 */
-GPIO(USBPD_PORTB_VBUS_INPUT,  PIN(A, 7), GPIO_OUT_HIGH) /* VBUSINSWENP0 */
-GPIO(USBPD_PORTB_VBUS_OV_OC,  PIN(D, 2), GPIO_INPUT)    /* VSWFLTP0 */
-GPIO(USBPD_PORTB_CC1_VCONN,   PIN(A, 5), GPIO_OUT_LOW)
-GPIO(USBPD_PORTB_CC2_VCONN,   PIN(A, 4), GPIO_OUT_LOW)
-GPIO(USBPD_PORTB_VCONN_OV_OC, PIN(D, 4), GPIO_INPUT)    /* VCONSWFLTP0 */
-GPIO(USBPD_PORTC_VBUS_SEN1P3, PIN(P, 2), GPIO_OUT_LOW)  /* VBUSSEN1P3 */
-GPIO(USBPD_PORTC_VBUS_DROP,   PIN(P, 3), GPIO_OUT_LOW)  /* VBUSDISP3 */
-GPIO(USBPD_PORTC_VBUS_OUTPUT, PIN(P, 4), GPIO_OUT_LOW)  /* VBUSOUTSWENP3 */
-GPIO(USBPD_PORTC_VBUS_INPUT,  PIN(P, 5), GPIO_OUT_HIGH) /* VBUSINSWENP3 */
-GPIO(USBPD_PORTC_VBUS_OV_OC,  PIN(P, 6), GPIO_INPUT)    /* VSWFLTP3 */
-GPIO(USBPD_PORTC_CC1_VCONN,   PIN(O, 0), GPIO_OUT_LOW)
-GPIO(USBPD_PORTC_CC2_VCONN,   PIN(O, 1), GPIO_OUT_LOW)
-GPIO(USBPD_PORTC_VCONN_OV_OC, PIN(O, 2), GPIO_INPUT)    /* VCONSWFLTP3 */
-
-GPIO(I2C_A_SCL,      PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,      PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,      PIN(C, 2), GPIO_INPUT)
-GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
-GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,      PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,      PIN(E, 7), GPIO_INPUT)
-
-/* KSO/KSI pins can be used as GPIO input. */
-GPIO(BOARD_VERSION1, PIN(KSO_H, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION2, PIN(KSO_H, 6), GPIO_INPUT)
-GPIO(BOARD_VERSION3, PIN(KSO_H, 7), GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(PCH_SCI_L)
-UNIMPLEMENTED(PCH_WAKE_L)
-UNIMPLEMENTED(POWER_BUTTON_L)
-UNIMPLEMENTED(LID_OPEN)
-
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(I, 0x88), 1, MODULE_ADC, 0)             /* ADC CH3, CH7 */
-ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0)             /* ADC CH13-CH16 */
diff --git a/board/it8xxx2_pdevb/vif_override.xml b/board/it8xxx2_pdevb/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/it8xxx2_pdevb/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/jacuzzi/battery.c b/board/jacuzzi/battery.c
deleted file mode 100644
index 443bf1e98a..0000000000
--- a/board/jacuzzi/battery.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11580,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_PANASONIC_AC16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-        [BATTERY_LGC_AC16L8J] = {
-                .fuel_gauge = {
-                        .manuf_name = "LGC KT0020G010",
-                        .device_name = "AP16L8J",
-                        .ship_mode = {
-                                .reg_addr = 0x3A,
-                                .reg_data = { 0xC574, 0xC574 },
-                        },
-                        .fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-                        }
-                },
-                .batt_info = {
-                        .voltage_max            = 8700,
-                        .voltage_normal         = 7500,
-                        .voltage_min            = 6000,
-                        .precharge_current      = 256,
-                        .start_charging_min_c   = 0,
-                        .start_charging_max_c   = 50,
-                        .charging_min_c         = 0,
-                        .charging_max_c         = 60,
-                        .discharging_min_c      = -20,
-                        .discharging_max_c      = 75,
-                },
-        },
-	[BATTERY_PANASONIC_AC16L5J_KT00205009] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00205009",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J_KT00205009;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/jacuzzi/board.c b/board/jacuzzi/board.c
deleted file mode 100644
index ec6515544d..0000000000
--- a/board/jacuzzi/board.c
+++ /dev/null
@@ -1,571 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-#ifdef BOARD_JACUZZI
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-#else /* Juniper */
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-#endif
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	int board_version;
-
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-
-	board_version = board_get_version();
-	if (board_version == 8 || board_version == 9) {
-		/* Disable motion sense. */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-		motion_sensor_count = 0;
-		gpio_disable_interrupt(GPIO_ACCEL_INT_ODL);
-		gpio_set_flags(GPIO_ACCEL_INT_ODL,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-		/* Disable tablet mode. */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		gmr_tablet_switch_disable();
-		gpio_set_flags(GPIO_TABLET_MODE_L,
-			       GPIO_INPUT | GPIO_PULL_UP);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_bmi160_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_icm426xx_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, enough to calculate lid angle. */
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_bmi160_ref,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_bmi160_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = CONFIG_SPI_ACCEL_PORT,
-	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm426xx_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = CONFIG_SPI_ACCEL_PORT,
-	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm426xx_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int base_accelgyro_config;
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_accelgyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static void board_detect_motionsensor(void)
-{
-	int val;
-	/* Check base accelgyro chip */
-	if (base_accelgyro_config != BASE_GYRO_NONE)
-		return;
-
-	icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
-	if (val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-	}
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
-}
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT);
-
-int board_sensor_at_360(void)
-{
-	int board_version;
-
-	board_version = board_get_version();
-	if (board_version == 8 || board_version == 9)
-		return 0;
-	else
-		return !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
-}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
-
-int board_get_battery_i2c(void)
-{
-	return board_get_version() >= 1 ? 2 : 1;
-}
diff --git a/board/jacuzzi/board.h b/board/jacuzzi/board.h
deleted file mode 100644
index ef8a02a3dc..0000000000
--- a/board/jacuzzi/board.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-#undef CONFIG_CMD_MFALLOW
-
-/* Free up flash space */
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#ifdef BOARD_JUNIPER
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#undef CONFIG_SYSTEM_UNLOCKED
-#endif
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* ICM426XX Base accel/gyro */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_GMR_TABLET_MODE_CUSTOM
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#ifdef BOARD_JACUZZI
-#define I2C_PORT_BATTERY            1
-#else /* Juniper */
-#define I2C_PORT_BATTERY            2
-#endif
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_LED_ONOFF_STATES
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_PANASONIC_AC16L5J,
-	BATTERY_LGC_AC16L8J,
-	BATTERY_PANASONIC_AC16L5J_KT00205009,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jacuzzi/build.mk b/board/jacuzzi/build.mk
deleted file mode 100644
index e449fce9fc..0000000000
--- a/board/jacuzzi/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/jacuzzi/ec.tasklist b/board/jacuzzi/ec.tasklist
deleted file mode 100644
index b695d05a71..0000000000
--- a/board/jacuzzi/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/jacuzzi/gpio.inc b/board/jacuzzi/gpio.inc
deleted file mode 100644
index 60288e7195..0000000000
--- a/board/jacuzzi/gpio.inc
+++ /dev/null
@@ -1,126 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         motion_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(LED_BLUE,             EXPIN(0, 1, 4), GPIO_OUT_HIGH)      /* LED BLUE */
-IOEX(LED_GREEN,            EXPIN(0, 1, 3), GPIO_OUT_HIGH)      /* LED GREEN */
-IOEX(LED_ORANGE,           EXPIN(0, 1, 2), GPIO_OUT_HIGH)      /* LED ORANGE */
-
-#ifdef BOARD_JACUZZI
-GPIO(LID_ACCEL_INT_ODL, PIN(A, 14), GPIO_INPUT)
-/* Jacuzzi doesn't have EN_PP1800_S5_L. */
-UNIMPLEMENTED(EN_PP1800_S5_L)
-#else
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-#endif
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/jacuzzi/led.c b/board/jacuzzi/led.c
deleted file mode 100644
index e76b73bc9a..0000000000
--- a/board/jacuzzi/led.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Jacuzzi
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_LED_ORANGE, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		ioex_set_level(IOEX_LED_BLUE, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		ioex_set_level(IOEX_LED_GREEN, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		break;
-	}
-}
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	}
-}
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/jacuzzi/vif_override.xml b/board/jacuzzi/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/jacuzzi/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/jinlon/battery.c b/board/jinlon/battery.c
deleted file mode 100644
index 12c2e38d84..0000000000
--- a/board/jinlon/battery.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-
-/*
- * Battery info for all Jinlon battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-14-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/jinlon/board.c b/board/jinlon/board.c
deleted file mode 100644
index 470ff37f65..0000000000
--- a/board/jinlon/board.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/oti502.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_8042.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void check_reboot_deferred(void);
-DECLARE_DEFERRED(check_reboot_deferred);
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	baseboard_mst_enable_control(MST_HDMI, gpio_get_level(signal));
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-const struct fan_conf fan_conf_1 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN2,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-	[FAN_CH_1] = { .conf = &fan_conf_1, .rpm = &fan_rpm_1, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5v Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IR Sensor",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = oti502_get_val,
-				 .idx = OTI502_IDX_OBJECT},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Dratini Temperature sensors */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(70),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(86),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	motion_sensor_count = ARRAY_SIZE(motion_sensors);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_KBD_BKLIGHT_DOWN,	/* T8 */
-		TK_KBD_BKLIGHT_UP,	/* T9 */
-		TK_PLAY_PAUSE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config keybd2 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_PRIVACY_SCRN_TOGGLE,	/* T8 */
-		TK_KBD_BKLIGHT_DOWN,	/* T9 */
-		TK_KBD_BKLIGHT_UP,	/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	/*
-	 * Future boards should use fw_config instead of SKU ID
-	 * to make such decisions.
-	 */
-	switch (get_board_sku()) {
-	case 1:
-	case 21:
-		return &keybd1;
-	case 2:
-	case 22:
-		return &keybd2;
-	default:
-		cprints(CC_KEYBOARD,
-			"Error! Bad SKU ID, Using default VIVLADI keyboard!");
-		return &keybd1;
-	}
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 21) ||
-		(sku == 22);
-}
-
-
-void all_sys_pgood_check_reboot(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC);
-}
-
-__override void board_chipset_forced_shutdown(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, -1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
-
-static void check_reboot_deferred(void)
-{
-	if (!gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD))
-		system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED);
-}
diff --git a/board/jinlon/board.h b/board/jinlon/board.h
deleted file mode 100644
index beb30c8e12..0000000000
--- a/board/jinlon/board.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_DPTF_MULTI_PROFILE
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/*
- * Jinlon's battery takes several seconds to come back out of its disconnect
- * state (~4 seconds, but give it 6 for margin).
- */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY 0
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 2
-#define CONFIG_CUSTOM_FAN_CONTROL
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define RPM_DEVIATION 1
-#define CONFIG_TEMP_SENSOR_OTI502
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_1,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_1,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jinlon/build.mk b/board/jinlon/build.mk
deleted file mode 100644
index 2d6118ea70..0000000000
--- a/board/jinlon/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o thermal.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/jinlon/ec.tasklist b/board/jinlon/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/jinlon/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/jinlon/gpio.inc b/board/jinlon/gpio.inc
deleted file mode 100644
index f57a331436..0000000000
--- a/board/jinlon/gpio.inc
+++ /dev/null
@@ -1,150 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(C, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_AMBER_C0_L,           PIN(C, 4), GPIO_OUT_HIGH)        /* Amber C0 port */
-GPIO(LED_WHITE_C0_L,           PIN(C, 3), GPIO_OUT_HIGH)        /* White C0 port */
-GPIO(LED_AMBER_C1_L,           PIN(4, 2), GPIO_OUT_HIGH)        /* Amber C1 port */
-GPIO(LED_WHITE_C1_L,           PIN(C, 6), GPIO_OUT_HIGH)        /* White C1 port */
-GPIO(PWR_LED_WHITE_L,          PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_FAN2,           PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_THERMAL_SENSOR_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_THERMAL_SENSOR_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                             /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(C, 0x01), 0, MODULE_PWM, 0)                             /* PWM6 - FAN2 */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                             /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)                             /* ADC0-2*/
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/jinlon/led.c b/board/jinlon/led.c
deleted file mode 100644
index 18dfb67f78..0000000000
--- a/board/jinlon/led.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Jinlon
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_ON_TICKS 5
-#define POWER_LED_ON_TICKS 2
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == 0 ? GPIO_LED_AMBER_C0_L : GPIO_LED_AMBER_C1_L);
-	white_led = (port == 0 ? GPIO_LED_WHITE_C0_L : GPIO_LED_WHITE_C1_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(1, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(1, LED_AMBER);
-		else
-			led_set_color_battery(1, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(0, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(0, LED_AMBER);
-		else
-			led_set_color_battery(0, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(1, (port == 1) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < POWER_LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/jinlon/thermal.c b/board/jinlon/thermal.c
deleted file mode 100644
index 4d75f70738..0000000000
--- a/board/jinlon/thermal.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-struct fan_step {
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-
-	/* Fan 1~2 rpm */
-	uint16_t rpm[FAN_CH_COUNT];
-};
-
-static const struct fan_step *fan_step_table;
-
-static const struct fan_step fan_table_clamshell[] = {
-	{
-		/* level 0 */
-		.on = {0, -1, 54, 34},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
-	},
-	{
-		/* level 1 */
-		.on = {0, -1, 57, 35},
-		.off = {99, -1, 54, 34},
-		.rpm = {3950, 3850},
-	},
-	{
-		/* level 2 */
-		.on = {0, -1, 58, 36},
-		.off = {99, -1, 57, 35},
-		.rpm = {4200, 4100},
-	},
-	{
-		/* level 3 */
-		.on = {0, -1, 59, 37},
-		.off = {99, -1, 58, 36},
-		.rpm = {4550, 4450},
-	},
-	{
-		/* level 4 */
-		.on = {60, -1, 60, 38},
-		.off = {58, -1, 59, 37},
-		.rpm = {4900, 4800},
-	},
-	{
-		/* level 5 */
-		.on = {62, -1, 61, 39},
-		.off = {60, -1, 60, 38},
-		.rpm = {5250, 5150},
-	},
-	{
-		/* level 6 */
-		.on = {65, -1, 64, 40},
-		.off = {62, -1, 61, 39},
-		.rpm = {5400, 5300},
-	},
-	{
-		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 62, 40},
-		.rpm = {6000, 6150},
-	},
-};
-
-static const struct fan_step fan_table_tablet[] = {
-	{
-		/* level 0 */
-		.on = {0, -1, 55, 39},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
-	},
-	{
-		/* level 1 */
-		.on = {0, -1, 56, 40},
-		.off = {99, -1, 55, 39},
-		.rpm = {0, 0},
-	},
-	{
-		/* level 2 */
-		.on = {0, -1, 57, 41},
-		.off = {99, -1, 56, 40},
-		.rpm = {4000, 3350},
-	},
-	{
-		/* level 3 */
-		.on = {0, -1, 58, 42},
-		.off = {99, -1, 57, 41},
-		.rpm = {4200, 3400},
-	},
-	{
-		/* level 4 */
-		.on = {60, -1, 59, 43},
-		.off = {58, -1, 58, 42},
-		.rpm = {4400, 3500},
-	},
-	{
-		/* level 5 */
-		.on = {62, -1, 60, 44},
-		.off = {60, -1, 59, 43},
-		.rpm = {4800, 4350},
-	},
-	{
-		/* level 6 */
-		.on = {65, -1, 61, 45},
-		.off = {62, -1, 60, 44},
-		.rpm = {5000, 4500},
-	},
-	{
-		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 61, 45},
-		.rpm = {5200, 5100},
-	},
-};
-
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
-
-BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) ==
-	ARRAY_SIZE(fan_table_tablet));
-
-int fan_table_to_rpm(int fan, int *temp)
-{
-	static int current_level;
-	static int prev_tmp[TEMP_SENSOR_COUNT];
-	static int new_rpm;
-	int i;
-
-	if (tablet_get_mode())
-		fan_step_table = fan_table_tablet;
-	else
-		fan_step_table = fan_table_clamshell;
-
-	/*
-	 * Compare the current and previous temperature, we have
-	 * the three paths :
-	 *  1. decreasing path. (check the release point)
-	 *  2. increasing path. (check the trigger point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-
-	if (temp[TEMP_SENSOR_1] < prev_tmp[TEMP_SENSOR_1] ||
-		temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] ||
-		temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) {
-		for (i = current_level; i > 0; i--) {
-			if (temp[TEMP_SENSOR_1] < fan_step_table[i].off[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] < fan_step_table[i].off[TEMP_SENSOR_4] &&
-				 temp[TEMP_SENSOR_3] < fan_step_table[i].off[TEMP_SENSOR_3])
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (temp[TEMP_SENSOR_1] > prev_tmp[TEMP_SENSOR_1] ||
-		   temp[TEMP_SENSOR_3] > prev_tmp[TEMP_SENSOR_3] ||
-		   temp[TEMP_SENSOR_4] > prev_tmp[TEMP_SENSOR_4]) {
-		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
-			if ((temp[TEMP_SENSOR_1] > fan_step_table[i].on[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] > fan_step_table[i].on[TEMP_SENSOR_4]) ||
-				 temp[TEMP_SENSOR_3] > fan_step_table[i].on[TEMP_SENSOR_3])
-				current_level = i + 1;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
-		prev_tmp[i] = temp[i];
-
-	ASSERT(current_level < NUM_FAN_LEVELS);
-
-	switch (fan) {
-	case FAN_CH_0:
-		new_rpm = fan_step_table[current_level].rpm[FAN_CH_0];
-		break;
-	case FAN_CH_1:
-		new_rpm = fan_step_table[current_level].rpm[FAN_CH_1];
-		break;
-	default:
-		break;
-	}
-
-	return new_rpm;
-}
-
-void board_override_fan_control(int fan, int *tmp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
-	}
-}
diff --git a/board/jinlon/vif_override.xml b/board/jinlon/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/jinlon/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/jslrvp_ite/battery.c b/board/jslrvp_ite/battery.c
deleted file mode 100644
index 3584aec56d..0000000000
--- a/board/jslrvp_ite/battery.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Simplo Battery (SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50
-	 */
-	[BATTERY_SIMPLO_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-HHP-408",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,        /* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 204,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-	/*
-	 * Simplo Battery (SMP-CA-445) Information
-	 * Fuel gauge: BQ30Z554
-	 */
-	[BATTERY_SIMPLO_SMP_CA_445] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-CA-445",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,		/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 150,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SMP_CA_445;
-
diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c
deleted file mode 100644
index eb654140a6..0000000000
--- a/board/jslrvp_ite/board.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-#include "anx7440.h"
-#include "button.h"
-#include "charger.h"
-#include "driver/charger/isl923x.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/icelake.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* TCPC gpios */
-const struct tcpc_gpio_config_t tcpc_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.vbus = {
-			.pin = GPIO_USB_C0_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C0_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C0_SNK_EN_L,
-			.pin_pol = 0,
-		},
-	},
-	[TYPE_C_PORT_1] = {
-		.vbus = {
-			.pin = GPIO_USB_C1_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C1_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C1_SNK_EN_L,
-			.pin_pol = 0,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-	},
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-const struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = I2C_ADDR_USB_MUX0_FLAGS,
-		.driver = &anx7440_usb_mux_driver,
-	},
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = I2C_ADDR_USB_MUX1_FLAGS,
-		.driver = &anx7440_usb_mux_driver,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	/* Flash EC */
-	[I2C_CHAN_FLASH] = {
-		.name = "chan-A",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_I2C_A_SCL,
-		.sda = GPIO_I2C_A_SDA,
-	},
-	/*
-	 * Port-80 Display, Charger, Battery, IO-expanders, EEPROM,
-	 * IMVP9, AUX-rail, power-monitor.
-	 */
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA,
-	},
-	/* Retimers, PDs */
-	[I2C_CHAN_RETIMER] = {
-		.name = "retimer",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On JSLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-int board_get_version(void)
-{
-	int fab_id;
-	int board_id;
-	int bom_id;
-
-	if (ioexpander_read_intelrvp_version(&fab_id, &board_id))
-		return -1;
-	/*
-	 * Port0: bit 1:0 - FAB ID(1:0) + 1
-	 * Port1: bit 7:5 - BOM ID(2:0)
-	 *        bit 4:0 - BOARD ID(4:0)
-	 */
-	fab_id = (fab_id & 0x03) + 1;
-	bom_id = ((board_id & 0xE0) >> 5);
-	board_id &= 0x1F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	return board_id | (fab_id << 8);
-}
diff --git a/board/jslrvp_ite/board.h b/board/jslrvp_ite/board.h
deleted file mode 100644
index e733a30240..0000000000
--- a/board/jslrvp_ite/board.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_IT8320
-
-/* MECC config */
-#define CONFIG_INTEL_RVP_MECC_VERSION_0_9
-
-#define CONFIG_CHIPSET_JASPERLAKE
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_L_PGOOD
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-#define GPIO_BAT_LED_RED_L		GPIO_BAT_LED_GREEN_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_AC_LED_GREEN_L
-
-/* Fan features */
-#define CONFIG_FANS 1
-#define BOARD_FAN_MIN_RPM 3000
-#define BOARD_FAN_MAX_RPM 10000
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-#include "baseboard.h"
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9238
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-
-/* USB ports */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define DEDICATED_CHARGE_PORT 2
-
-/* USB PD config */
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-
-/* USB MUX */
-#define CONFIG_USB_MUX_ANX7440
-
-/* USB HPD */
-#define CONFIG_USB_PD_DP_HPD_GPIO
-
-/* Thermal configs */
-
-/* I2C ports */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
-#define I2C_PORT_USB_MUX    IT83XX_I2C_CH_E
-
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-#define PORT80_I2C_ADDR			MAX695X_I2C_ADDR1_FLAGS
-
-#ifndef __ASSEMBLER__
-
-enum jslrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-};
-
-enum jslrvp_i2c_channel {
-	I2C_CHAN_FLASH,
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_RETIMER,
-	I2C_CHAN_COUNT,
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_SMP_HHP_408,
-	BATTERY_SIMPLO_SMP_CA_445,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Define max power */
-#define PD_MAX_POWER_MW        45000
-
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jslrvp_ite/build.mk b/board/jslrvp_ite/build.mk
deleted file mode 100644
index 4903661c30..0000000000
--- a/board/jslrvp_ite/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel Jasperlake RVP with ITE EC board specific configuration
-#
-
-#it8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/jslrvp_ite/ec.tasklist b/board/jslrvp_ite/ec.tasklist
deleted file mode 100644
index 768211c95f..0000000000
--- a/board/jslrvp_ite/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc
deleted file mode 100644
index 5c0219263e..0000000000
--- a/board/jslrvp_ite/gpio.inc
+++ /dev/null
@@ -1,184 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel Jasperlake RVP with ITE EC board specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_EC_DSW_PWROK,	PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PWRGD,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,	PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,PIN(L, 3), GPIO_INT_BOTH, power_button_interrupt)
-
-GPIO_INT(AC_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)
-
-GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART1 RX input */
-
-GPIO_INT(WP_L,      PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)     /* EC_WP_ODL */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-GPIO_INT(TABLET_MODE_L,	PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(DC_JACK_PRESENT,   PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt)
-
-/* Type-C interrupts */
-GPIO_INT(USB_C0_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-
-/* Power sequencing GPIOs */
-GPIO(CPU_PROCHOT,	PIN(B, 2), GPIO_INPUT)
-GPIO(SYS_RESET_L,	PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N,	PIN(I, 2), GPIO_OUT_LOW)
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(NC_PCH_SYS_PWROK,	PIN(K, 4), GPIO_INPUT)
-GPIO(EN_PP5000, 	PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
-
-UNIMPLEMENTED(EN_VCCIO_EXT)
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-/* Battery present */
-GPIO(EC_BATT_PRES_L,	PIN(K, 0), GPIO_INPUT)
-
-/* Type-C GPIOs */
-GPIO(USB_C0_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_DP_HPD,	PIN(E, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_DP_HPD,	PIN(D, 3), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-/*
- * Type-C USB MUX GPIOs
- * TODO(b/146683781): drive initial level to low and
- * handle the low power mode
- */
-GPIO(USB_C0_LS_EN,		PIN(J, 1), GPIO_OUT_HIGH)
-GPIO(USB_C1_LS_EN,		PIN(C, 4), GPIO_OUT_HIGH)
-
-/* Type-C BC1.2 GPIOs */
-GPIO(USB_C0_BC12_CHG_DET_L,	PIN(A, 1), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON_ODL,	PIN(H, 4), GPIO_ODR_HIGH)
-
-GPIO(USB_C1_BC12_CHG_DET_L,	PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_BC12_VBUS_ON_ODL,	PIN(J, 6), GPIO_ODR_HIGH)
-
-/* USB-A GPIOs */
-GPIO(USB_A_5V_EN,	PIN(K, 3), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_GREEN_L,	PIN(A, 6), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(AC_LED_GREEN_L,	PIN(A, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-
-/* FAN control pins */
-GPIO(FAN_POWER_EN,	PIN(K, 6), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO(CCD_MODE_ODL,	PIN(B, 5), GPIO_INPUT)
-GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUT_LOW)
-
-/* Used if Type-A ports have BC1.2 */
-GPIO(NC_USB_A_CHG_EN,		PIN(D, 1), GPIO_INPUT)
-
-/* Used if dead battery LDO present */
-GPIO(NC_USBC_LDO_ENABLE,	PIN(G, 2), GPIO_INPUT)
-
-/* Used with Discreate TBT and or with PD on RVP */
-GPIO(NC_TBT_C0_RESET_N,		PIN(KSO_H, 7), GPIO_INPUT)
-GPIO(NC_TBT_C1_RESET_N,		PIN(K, 7), GPIO_INPUT)
-GPIO(NC_USB_C0_RETIMER_ALRT,	PIN(I, 7), GPIO_INPUT)
-GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
-
-/* Used if PMIC is used */
-GPIO(NC_PMIC_EN,		PIN(H, 3), GPIO_INPUT)
-
-/* Used if Base EC is present */
-GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
-#endif
-
-/* Unused pins */
-GPIO(NC_SUSWARN,		PIN(E, 1), GPIO_INPUT)
-GPIO(NC_SD_CARD_DETECT,		PIN(E, 5), GPIO_INPUT)
-GPIO(NC_BATT_DISABLE,		PIN(H, 0), GPIO_INPUT)
-GPIO(NC_SLP_S0_CS_N,		PIN(I, 0), GPIO_INPUT)
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(I2C_C_SCL,	PIN(C, 7), GPIO_INPUT)
-GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(I2C_F_SCL,	PIN(A, 4), GPIO_INPUT)
-GPIO(I2C_F_SDA,	PIN(A, 5), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SDA F7 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* TACH1A D7 */
diff --git a/board/jslrvp_ite/vif_override.xml b/board/jslrvp_ite/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/jslrvp_ite/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/juniper b/board/juniper
deleted file mode 120000
index 39d9d53d64..0000000000
--- a/board/juniper
+++ /dev/null
@@ -1 +0,0 @@
-jacuzzi
\ No newline at end of file
diff --git a/board/kakadu/analyzestack.yaml b/board/kakadu/analyzestack.yaml
deleted file mode 100644
index 4a057ce818..0000000000
--- a/board/kakadu/analyzestack.yaml
+++ /dev/null
@@ -1,3 +0,0 @@
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
diff --git a/board/kakadu/board.c b/board/kakadu/board.c
deleted file mode 100644
index dd36672bfe..0000000000
--- a/board/kakadu/board.c
+++ /dev/null
@@ -1,522 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "charger_mt6370.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/mt6370.h"
-#include "driver/usb_mux/it5205.h"
-#include "extpower.h"
-#include "gesture.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_policy.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void gauge_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
-		},
-		.drv = &mt6370_tcpm_drv,
-	},
-};
-
-struct mt6370_thermal_bound thermal_bound = {
-	.target = 80,
-	.err = 4,
-};
-
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-__override const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	static const struct rt946x_init_setting battery_init_setting = {
-		.eoc_current = 140,
-		.mivr = 4000,
-		.ircmp_vclamp = 32,
-		.ircmp_res = 25,
-		.boost_voltage = 5050,
-		.boost_current = 1500,
-	};
-
-	return &battery_init_setting;
-}
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 0);
-		break;
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	case CHARGE_PORT_POGO:
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
-		break;
-#endif
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	if (force_discharge && !enable)
-		rt946x_toggle_bc12_detection();
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int extpower_is_present(void)
-{
-	/*
-	 * The charger will indicate VBUS presence if we're sourcing 5V,
-	 * so exclude such ports.
-	 */
-	int usb_c_extpower_present;
-
-	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
-		usb_c_extpower_present = 0;
-	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
-
-	return usb_c_extpower_present;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
-
-#ifdef SECTION_IS_RW
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-#endif /* SECTION_IS_RW */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable gauge interrupt from max17055 */
-	gpio_enable_interrupt(GPIO_GAUGE_INT_ODL);
-
-	/*
-	 * Fix backlight led maximum current:
-	 * tolerance 120mA * 0.75 = 90mA.
-	 * (b/133655155)
-	 */
-	mt6370_backlight_set_dim(MT6370_BLDIM_DEFAULT * 3 / 4);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_rev_init(void)
-{
-	/* Board revision specific configs. */
-
-	/*
-	 * It's a P1 pin BOOTBLOCK_MUX_OE, also a P2 pin BC12_DET_EN.
-	 * Keep this pin defaults to P1 setting since that eMMC enabled with
-	 * High-Z stat.
-	 */
-	/* TODO */
-	/* Put initial code here for different EC board reversion */
-	return;
-}
-DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
-
-void sensor_board_proc_double_tap(void)
-{
-	CPRINTS("Detect double tap");
-}
-
-/* Motion sensors */
-/* Mutexes */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm42607_data;
-
-enum lid_accelgyro_type {
-	LID_GYRO_NONE = 0,
-	LID_GYRO_BMI160 = 1,
-	LID_GYRO_ICM426XX = 2,
-};
-
-static enum lid_accelgyro_type lid_accelgyro_config;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-struct motion_sensor_t icm42607_lid_accel = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &lid_standard_ref_icm42607,
-	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-};
-
-struct motion_sensor_t icm42607_lid_gyro = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref_icm42607,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-		 /* For double tap detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (lid_accelgyro_config != LID_GYRO_NONE)
-		return;
-	/* Check base accelgyro chip */
-	ret = icm_read8(&icm42607_lid_accel,
-				ICM42607_REG_WHO_AM_I, &val);
-	if (ret)
-		ccprints("Get ICM fail.");
-	if (val == ICM42607_CHIP_ICM42607P) {
-		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
-		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
-	}
-	lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P)
-			? LID_GYRO_ICM426XX : LID_GYRO_BMI160;
-	ccprints("LID Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P)
-			? "ICM42607" : "BMI160");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_INIT_ADC + 2);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (lid_accelgyro_config) {
-	case LID_GYRO_ICM426XX:
-		icm42607_interrupt(signal);
-		break;
-	case LID_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/*
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-	/*
-	 * Though we have a more tolerant range (3.9V~13.4V), setting 4400 to
-	 * prevent from a bad charger crashed.
-	 *
-	 * TODO(b:131284131): mt6370 VBUS reading is not accurate currently.
-	 * Vendor will provide a workaround solution to fix the gap between ADC
-	 * reading and actual voltage.  After the workaround applied, we could
-	 * try to raise this value to 4600.  (when it says it read 4400, it is
-	 * actually close to 4600)
-	 */
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < 4400;
-}
-
-__override int board_charge_port_is_sink(int port)
-{
-	/* TODO(b:128386458): Check POGO_ADC_INT_L */
-	return 1;
-}
-
-__override int board_charge_port_is_connected(int port)
-{
-	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
-}
-
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
-{
-	r->meas.voltage_now = 3300;
-	r->meas.voltage_max = 3300;
-	r->meas.current_max = 1500;
-	r->meas.current_lim = 1500;
-	r->max_power = r->meas.voltage_now * r->meas.current_max;
-}
-
diff --git a/board/kakadu/board.h b/board/kakadu/board.h
deleted file mode 100644
index 4e054dac93..0000000000
--- a/board/kakadu/board.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kakadu */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define BQ27541_ADDR	0x55
-#define VARIANT_KUKUI_BATTERY_BQ27541
-#define VARIANT_KUKUI_POGO_KEYBOARD
-
-#define VARIANT_KUKUI_CHARGER_MT6370
-#define VARIANT_KUKUI_EC_STM32F098
-#define VARIANT_KUKUI_TABLET_PWRBTN
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#define CONFIG_USB_MUX_IT5205
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
-
-#define CONFIG_CHARGER_MT6370_BACKLIGHT
-
-
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ACCELGYRO_ICM42607	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#endif /* SECTION_IS_RW */
-
-/* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-
-/* Route sbs host requests to virtual battery driver */
-#define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
-
-/* MKBP */
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
-
-#define PD_OPERATING_POWER_MW 15000
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_BATT_ID,
-	ADC_POGO_ADC_INT_L,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-void pogo_adc_interrupt(enum gpio_signal signal);
-int board_discharge_on_ac(int enable);
-void motion_interrupt(enum gpio_signal signal);
-
-/* Enable double tap detection */
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-#define CONFIG_GESTURE_TAP_SENSOR 0
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
-#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
-#define CONFIG_GESTURE_TAP_THRES_MG 100
-#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kakadu/build.mk b/board/kakadu/build.mk
deleted file mode 100644
index 7a3953b8bb..0000000000
--- a/board/kakadu/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=board.o led.o
diff --git a/board/kakadu/ec.tasklist b/board/kakadu/ec.tasklist
deleted file mode 100644
index fc26f445b2..0000000000
--- a/board/kakadu/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
-
diff --git a/board/kakadu/gpio.inc b/board/kakadu/gpio.inc
deleted file mode 100644
index f52f2b7f2f..0000000000
--- a/board/kakadu/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         motion_interrupt)
-GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event)
-GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(HALL_INT_L,        PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(GAUGE_INT_ODL,     PIN(C, 9),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         gauge_interrupt)
-GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
-         pogo_adc_interrupt)
-
-/* unused */
-GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
-/* unused after board rev 5 */
-GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_INPUT)
-GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_INPUT)
-
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BATT_ID,              PIN(A, 7),  GPIO_ANALOG)
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP3300_POGO,     PIN(A, 13), GPIO_OUT_LOW)
-GPIO(EN_POGO_CHARGE_L,   PIN(B, 6),  GPIO_OUT_HIGH)
-GPIO(EN_USBC_CHARGE_L,   PIN(C, 7),  GPIO_OUT_LOW)
-GPIO(EN_PP5000_USBC,     PIN(D, 2),  GPIO_OUT_LOW)
-GPIO(BC12_DET_EN,        PIN(C, 4),  GPIO_OUT_LOW)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
-#endif
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/kakadu/led.c b/board/kakadu/led.c
deleted file mode 100644
index 504bdf0d2f..0000000000
--- a/board/kakadu/led.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Kakadu board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "driver/charger/rt946x.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "power.h"
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_AMBER	MT6370_LED_ID1
-#define LED_WHITE	MT6370_LED_ID2
-
-#define LED_MASK_OFF	0
-#define LED_MASK_AMBER	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK2DIM_EN
-
-static void kakadu_led_set_battery(void)
-{
-	enum charge_state chstate;
-	enum power_state powerstate;
-	static uint8_t prv_white, prv_amber;
-	static uint8_t time_cnt;
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	chstate = charge_get_state();
-	powerstate = power_get_state();
-
-	switch (chstate) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (charge_get_percent() < 94) {
-			br[EC_LED_COLOR_AMBER] = 1;
-			br[EC_LED_COLOR_WHITE] = 0;
-			break;
-		}
-		br[EC_LED_COLOR_WHITE] = 1;
-		br[EC_LED_COLOR_AMBER] = 0;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (powerstate == POWER_S0) {
-			/* display SoC 10% = real battery SoC 13%*/
-			if (charge_get_percent() < 14) {
-				if (time_cnt < 1) {
-					time_cnt++;
-					br[EC_LED_COLOR_WHITE] = 0;
-					br[EC_LED_COLOR_AMBER] = 1;
-				} else {
-					time_cnt++;
-					br[EC_LED_COLOR_WHITE] = 0;
-					br[EC_LED_COLOR_AMBER] = 0;
-					if (time_cnt > 3)
-						time_cnt = 0;
-				}
-				break;
-			}
-			br[EC_LED_COLOR_WHITE] = 1;
-			br[EC_LED_COLOR_AMBER] = 0;
-			break;
-		} else if (powerstate == POWER_S3) {
-			if (time_cnt < 2) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 1;
-				br[EC_LED_COLOR_AMBER] = 0;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 3)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
-			br[EC_LED_COLOR_WHITE] = 0;
-			br[EC_LED_COLOR_AMBER] = 0;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		if (powerstate == POWER_S0) {
-			if (time_cnt < 1) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 1;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 1)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S3) {
-			if (time_cnt < 2) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 1;
-				br[EC_LED_COLOR_AMBER] = 0;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 3)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
-			br[EC_LED_COLOR_WHITE] = 0;
-			br[EC_LED_COLOR_AMBER] = 0;
-		}
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		return;
-	}
-
-	if (prv_white == br[EC_LED_COLOR_WHITE] &&
-	    prv_amber == br[EC_LED_COLOR_AMBER])
-		return;
-
-	prv_white = br[EC_LED_COLOR_WHITE];
-	prv_amber = br[EC_LED_COLOR_AMBER];
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return;
-
-	brightness_range[EC_LED_COLOR_WHITE] = MT6370_LED_BRIGHTNESS_MAX;
-	brightness_range[EC_LED_COLOR_AMBER] = MT6370_LED_BRIGHTNESS_MAX;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	uint8_t white, amber;
-
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return EC_ERROR_INVAL;
-
-	white = brightness[EC_LED_COLOR_WHITE];
-	amber = brightness[EC_LED_COLOR_AMBER];
-
-	mt6370_led_set_brightness(LED_WHITE, white);
-	mt6370_led_set_brightness(LED_AMBER, amber);
-
-	/* Enables LED sink power if necessary. */
-	mt6370_led_set_color((white ? LED_MASK_WHITE : 0) |
-			     (amber ? LED_MASK_AMBER : 0));
-	return EC_SUCCESS;
-}
-
-static void kakadu_led_init(void)
-{
-	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
-	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-	mt6370_led_set_color(0);
-	mt6370_led_set_dim_mode(LED_WHITE, dim);
-	mt6370_led_set_dim_mode(LED_AMBER, dim);
-	mt6370_led_set_pwm_frequency(LED_WHITE, freq);
-	mt6370_led_set_pwm_frequency(LED_AMBER, freq);
-	mt6370_led_set_pwm_dim_duty(LED_WHITE, 255);
-	mt6370_led_set_pwm_dim_duty(LED_AMBER, 255);
-}
-DECLARE_HOOK(HOOK_INIT, kakadu_led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		kakadu_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
-__override void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		return;
-	}
-
-	if (state)
-		br[EC_LED_COLOR_WHITE] = 1;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
diff --git a/board/kakadu/vif_override.xml b/board/kakadu/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kakadu/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kano/battery.c b/board/kano/battery.c
deleted file mode 100644
index a18ab029b6..0000000000
--- a/board/kano/battery.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Brya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* POW-TECH GQA05 Battery Information */
-	[BATTERY_POWER_TECH] = {
-		/* BQ40Z50 Fuel Gauge */
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.device_name = "BATGQA05L22",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,		/* XDSG */
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 280,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -10,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
diff --git a/board/kano/board.c b/board/kano/board.c
deleted file mode 100644
index 07dfc2cd5a..0000000000
--- a/board/kano/board.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-
-	gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-
-	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO(b/181508008): tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-
-	batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
diff --git a/board/kano/board.h b/board/kano/board.h
deleted file mode 100644
index 3372c5f3d2..0000000000
--- a/board/kano/board.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/*
- * Early brya boards are not set up for vivaldi
- */
-#undef CONFIG_KEYBOARD_VIVALDI
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 1
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-#undef CONFIG_LED_PWM_LOW_BATT_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
-
-/* Sensors */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel */
-#define CONFIG_ACCELGYRO_ICM_COMM_I2C
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* Lid accel */
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-#define CONFIG_ACCEL_KX022
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-
-#undef CONFIG_USB_PD_TCPM_NCT38XX
-#define CONFIG_USB_PD_TCPM_RT1715
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/*
- * see b/174768555#comment22
- */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x54
-/* SOC facing Burnside Bridge retimer */
-#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR    0x55
-/* Type-C connector facing Burnside Bridge retimer */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x56
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/*
- * TODO(b/181271666): no fan control loop until sensors are tuned
- */
-/* #define CONFIG_FANS			FAN_CH_COUNT */
-
-/* Charger defines */
-#define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_FAN,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_FAN,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kano/build.mk b/board/kano/build.mk
deleted file mode 100644
index 6d1303a15a..0000000000
--- a/board/kano/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Brya board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=tune_mp2964.o
-board-y+=usbc_config.o
diff --git a/board/kano/charger.c b/board/kano/charger.c
deleted file mode 100644
index 9f7c760858..0000000000
--- a/board/kano/charger.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/charger/isl9241.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "util.h"
-
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = board_is_usb_pd_port_present(port);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-					  int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
diff --git a/board/kano/ec.tasklist b/board/kano/ec.tasklist
deleted file mode 100644
index 7574c1839d..0000000000
--- a/board/kano/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/kano/fans.c b/board/kano/fans.c
deleted file mode 100644
index d966056331..0000000000
--- a/board/kano/fans.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/180681346): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/kano/fw_config.c b/board/kano/fw_config.c
deleted file mode 100644
index fb8acb635d..0000000000
--- a/board/kano/fw_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union brya_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union brya_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Brya FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
-}
-
-union brya_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
diff --git a/board/kano/fw_config.h b/board/kano/fw_config.h
deleted file mode 100644
index 6e4eb3ef58..0000000000
--- a/board/kano/fw_config.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Brya board.
- *
- * Source of truth is the project/brya/brya/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1,
-	DB_USB_ABSENT2 = 15
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union brya_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union brya_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/kano/generated-gpio.inc b/board/kano/generated-gpio.inc
deleted file mode 100644
index d65d64feca..0000000000
--- a/board/kano/generated-gpio.inc
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file was auto-generated.
- */
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-
-/* Pre-configured PSL balls:  J8  K6 */
diff --git a/board/kano/gpio.inc b/board/kano/gpio.inc
deleted file mode 100644
index 465f0fd4db..0000000000
--- a/board/kano/gpio.inc
+++ /dev/null
@@ -1,35 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/*
- * Generated-gpio.inc is produced using a Brya specific tool that
- * parses the GPIO definitions derived from the board schematics and
- * EC pinout descriptions derived form the chip datasheets to generate
- * the Chrome EC GPIO pinout definitions. Due to the confidential
- * nature of schematics and datasheets, they are not provided here.
- *
- * Variants that do not auto-generate their GPIO definitions should
- * combine the Brya gpio.inc and generated-gpio.inc into their
- * gpio.inc and customize as appropriate.
- */
-
-#include "generated-gpio.inc"
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-GPIO(USB_C0_OC_ODL,     PIN(D, 4), GPIO_ODR_HIGH)
-GPIO(USB_C0_FRS_EN,     PIN(6, 0), GPIO_LOW)
-GPIO(USB_C0_RT_RST_ODL, PIN(C, 2), GPIO_ODR_LOW)
-
-GPIO(USB_C1_OC_ODL,     PIN(E, 1), GPIO_ODR_HIGH)
diff --git a/board/kano/i2c.c b/board/kano/i2c.c
deleted file mode 100644
index bb55b13d0c..0000000000
--- a/board/kano/i2c.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0,2",
-		.port = I2C_PORT_USB_C0_C2_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0,2",
-		.port = I2C_PORT_USB_C0_C2_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0,2",
-		.port = I2C_PORT_USB_C0_C2_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/kano/keyboard.c b/board/kano/keyboard.c
deleted file mode 100644
index a9f033130d..0000000000
--- a/board/kano/keyboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/kano/led.c b/board/kano/led.c
deleted file mode 100644
index ab1021b845..0000000000
--- a/board/kano/led.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya specific PWM LED settings: there are 2 LEDs on each side of the board,
- * each one can be controlled separately. The LED colors are white or amber,
- * and the default behavior is tied to the charging process: both sides are
- * amber while charging the battery and white when the battery is charged.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * We only have a white and an amber LED, so setting any other color results in
- * both LEDs being off.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
-};
-
-/* Two logical LEDs with amber and white channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1,
-		.ch1 = PWM_CH_LED2,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		pwm_id = PWM_LED0;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/kano/pwm.c b/board/kano/pwm.c
deleted file mode 100644
index 66239d606f..0000000000
--- a/board/kano/pwm.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED2] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED1] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn on all the LED at 50%.
-	 * Turn on the fan at 100%.
-	 */
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_set_duty(PWM_CH_LED1, 50);
-	pwm_enable(PWM_CH_LED2, 1);
-	pwm_set_duty(PWM_CH_LED2, 50);
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kano/sensors.c b/board/kano/sensors.c
deleted file mode 100644
index 0859e9082c..0000000000
--- a/board/kano/sensors.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc_chip.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accel_kionix.h"
-#include "hooks.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_FAN] = {
-		.name = "TEMP_FAN",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-static struct kionix_accel_data g_kx022_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/*
- * TODO:(b/197200940): Verify lid and base orientation
- * matrix on proto board.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &g_icm426xx_data,
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &g_icm426xx_data,
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-		.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void baseboard_sensors_init(void)
-{
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	icm426xx_interrupt(signal);
-}
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_fan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_FAN]	= thermal_fan,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/kano/tune_mp2964.c b/board/kano/tune_mp2964.c
deleted file mode 100644
index 198f06d8eb..0000000000
--- a/board/kano/tune_mp2964.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tune the MP2964 IMVP9.1 parameters for brya */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "mp2964.h"
-
-const static struct mp2964_reg_val rail_a[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-const static struct mp2964_reg_val rail_b[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-
-static void mp2964_on_startup(void)
-{
-	static int chip_updated;
-	int status;
-
-	if (get_board_id() != 1)
-		return;
-
-	if (chip_updated)
-		return;
-
-	chip_updated = 1;
-
-	ccprintf("%s: attempting to tune PMIC\n", __func__);
-
-	status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a),
-			     rail_b, ARRAY_SIZE(rail_b));
-	if (status != EC_SUCCESS)
-		ccprintf("%s: could not update all settings\n", __func__);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup,
-	     HOOK_PRIO_FIRST);
diff --git a/board/kano/usbc_config.c b/board/kano/usbc_config.c
deleted file mode 100644
index 8f41a325b1..0000000000
--- a/board/kano/usbc_config.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		/* Compatible with Silicon Mitus SM536A0 */
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux soc_side_bb_retimer_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_C1_MUX,
-	.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
-	.next_mux = &usbc1_tcss_usb_mux,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &soc_side_bb_retimer_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum gpio_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = GPIO_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C1) {
-		rst_signal = GPIO_USB_C1_RT_RST_R_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		gpio_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		gpio_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b/179648104): figure out correct timing
-	 */
-
-	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(GPIO_USB_C0_RT_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_C2_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/kano/usbc_config.h b/board/kano/usbc_config.h
deleted file mode 100644
index 87e601ee3e..0000000000
--- a/board/kano/usbc_config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Brya board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kano/vif_override.xml b/board/kano/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kano/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kappa/battery.c b/board/kappa/battery.c
deleted file mode 100644
index 5ae6dc9b91..0000000000
--- a/board/kappa/battery.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* Dynapack HIGHPOWER DAK124960-W110703HT Battery Information */
-	[BATTERY_DYNAPACK_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2D-14-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8700,		/* mV */
-			.voltage_normal = 7600,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	/* Dynapack CosMX DAK124960-W0P0707HT Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-14-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8700,		/* mV */
-			.voltage_normal = 7600,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_HIGHPOWER;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/kappa/board.c b/board/kappa/board.c
deleted file mode 100644
index a0d7cf6a4e..0000000000
--- a/board/kappa/board.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-/* TODO: to be added once sensors land via CL:1714436 */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-	force_discharge = enable;
-
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/kappa/board.h b/board/kappa/board.h
deleted file mode 100644
index 287f22416e..0000000000
--- a/board/kappa/board.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#define VARIANT_KUKUI_NO_SENSORS
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_VENDOR_PARAM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#undef CONFIG_GMR_TABLET_MODE
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	LID_MAG,
-	CLEAR_ALS,
-	RGB_ALS,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_HIGHPOWER,
-	BATTERY_DYNAPACK_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger */
-int board_get_charger_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kappa/build.mk b/board/kappa/build.mk
deleted file mode 100644
index e449fce9fc..0000000000
--- a/board/kappa/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/kappa/ec.tasklist b/board/kappa/ec.tasklist
deleted file mode 100644
index c41e203780..0000000000
--- a/board/kappa/ec.tasklist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/kappa/gpio.inc b/board/kappa/gpio.inc
deleted file mode 100644
index 0e01d54f10..0000000000
--- a/board/kappa/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_HIGH)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-#endif
diff --git a/board/kappa/led.c b/board/kappa/led.c
deleted file mode 100644
index 5b65d7b948..0000000000
--- a/board/kappa/led.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Kappa
- */
-
-#include "charge_state.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "led_common.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_OFF);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_ON);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, BAT_LED_OFF);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
-	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x2 ?
-				      LED_WHITE : LED_OFF);
-		return;
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/kappa/vif_override.xml b/board/kappa/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kappa/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/karma/board.c b/board/karma/board.c
deleted file mode 100644
index 7bac35bd64..0000000000
--- a/board/karma/board.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "gpio.h"
-#include "oz554.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-__override void oz554_board_init(void)
-{
-	int pin_status = 0;
-
-	pin_status |= gpio_get_level(GPIO_PANEL_ID_0) << 0;
-	pin_status |= gpio_get_level(GPIO_PANEL_ID_1) << 1;
-	pin_status |= gpio_get_level(GPIO_PANEL_ID_2) << 2;
-
-	switch (pin_status) {
-	case 0x04:
-		CPRINTS("PANEL_LM_SSE2");
-		break;
-	case 0x05:
-		CPRINTS("PANEL_LM_SSK1");
-		/* Reigster 0x02: Setting LED current: 55(mA) */
-		if (oz554_set_config(2, 0x55))
-			CPRINTS("oz554 config failed");
-		break;
-	case 0x06:
-		CPRINTS("PANEL_LM_SSM1");
-		if (oz554_set_config(2, 0x46))
-			CPRINTS("oz554 config failed");
-		if (oz554_set_config(5, 0x87))
-			CPRINTS("oz554 config failed");
-		break;
-	default:
-		CPRINTS("PANEL_UNKNOWN");
-		break;
-	}
-}
diff --git a/board/karma/board.h b/board/karma/board.h
deleted file mode 100644
index 372b18509b..0000000000
--- a/board/karma/board.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Karma board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/karma/build.mk b/board/karma/build.mk
deleted file mode 100644
index 2554425920..0000000000
--- a/board/karma/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-BASEBOARD:=kalista
-
-board-y=board.o
diff --git a/board/karma/dev_key.pem b/board/karma/dev_key.pem
deleted file mode 100644
index b72c787613..0000000000
--- a/board/karma/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4gIBAAKCAYEAseZZZlXXDP+KrjqV+XhP0ZgPlU5mX4GCm27yzTqcKiFWLlHZ
-3f8seGG0lKNiL7WvHim8uSEDaPbp2us4uaJ6nTHEpbSGi2QVp90tE3aJG34HyKlg
-jcaE1r/0n6ynG/bf0Xx4O63Plp3Czi3TBYW49vT6+T/Jyfl2JpGQ9KNcD0umafsv
-uaEmdrLGrzjN8w1mFZfwscFkfVDh0cdiFNJ+UkTSpO9/yPapXbo4/lOMwdO9xILF
-cEZV9I7K7lBSvQ5Uep+w0SqNPTh2cGhoeEeDyH+Ce0LA8H7ZwbVnwLe1RswF9Wek
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-cXjKiavSPOZXDcnqCWqRJT3jN4ibAsU1GQtqLa8pTAi2wkE0fjuvAWK3NYuvpukg
-qNq2LI+BJkF4+dCZoeB1PDNyFNzdOFvkxj2+ImS3DLlPYVng4vHsTK1HRUUpL5Ag
-jjfMhMs4NC7HMOCTAgEDAoIBgHaZkO7j5LNVBx7RuVD63+EQCmOJmZUBAbz0od4n
-EsbA5B7hO+lUyFBBIw3CQXUjyhQb0yYWAkX58Tyc0HvBpxN2gxkjBFztY8U+Hgz5
-sLz+r9sblbPZreR/+GpzGhKklTZS+tJz37m+gd7JN1kD0KSjUft/29v7pBm2YKMX
-krTdGZv8ynvAxE8h2col3qII7rkP9cvWQv416+EvlriMVDbYjG30/9tPG5PRe1Q3
-syvifoMB2PWEOU20h0mK4dNe4d7E96s1Q+RTmTUtyipxUp6d4PIufAjMtM8yfkb0
-/0z81IsWQ0NOhefrMAi8TEcDkbyNSBPqHqbqH2FosFWo2cU3r6TXv2LdvFzc5BA+
-U6c+fXz7BDjv+NT3Bh98whKvTdJYcIgSg6vqzW7ZWJWWllZQtpJnQccIq4sPaL4S
-osFg8jd1kcbjVakCN0wYtfvMa/+WBZNNsZLUHoeIJvO7qnT7VKzhceoKHCJCMxNR
-Ypu5eELxCwebTXiImDqmFsKIawKBwQDpDjff6eatHbjmGV1elTyV5MLi95Tc0T7P
-FZHC1KLXkA/mEuXjAGfoZuLB5a3WmrA8r8fWNZoKV+0RBKIs3at1JFxZn9YiA0Hy
-5qmnYkXjMaY4p5AyO3eJsc2kbsh9r0cy2cb5GdwFDApeoVICoQh+dW9FpvIS+9AF
-0DVc2/Rg//cuXLlCMonF+PZVmDxRNhjBvwvRjxeowiu2ntI4sa83nHMhXI/RfvV4
-xcSng8gSIvabUmunDcPKvqO3rnpHzVECgcEAw2oFcHDAuZ1Xuopb2ghLRK3uLQVy
-BnqLu9QYk3OTe8C3PrNZ80R5MgtnZ0kP8bTZ4uE6MJ3+IMhPUCFqk9euGGdMUlU+
-SUmHie5CZPg4CwD4BUBy6dVdwId7aTxrdBOuGwwhYAhBsJxcfd3eNgiALcCoKsbi
-BLhjJ9Rch2rOsnpNJVwMvFMr6RM33oQrrufe4MBhDa/QD9yDtnDYH/KPO09E6AqU
-sMvBNsjbCC9rSYv+L9QkW8EUhT+wJIcqxUajAoHBAJtez+qb7x4T0JlmPj8OKGPt
-10H6Yz3g1IoOYSyNweUKtUQMmUIARUWZ7IFDyTm8dX3KhTl5EVw6ngtYbB3pHPjC
-6Du/5Bas1qHvG8TsLpd2btBvtXbST7EhM8L0hakfhMyRL1C76ANdXD8WNqxrWv74
-9NkZ9rdSiq6Kzj3n+ECqpMmTJiwhsS6l+Y5lfYt5ZdZ/XTZfZRssHSRp4XshH3po
-TMDoX+D/TlCD2G+tMAwXTxI28m9egocpwnp0UYUziwKBwQCCRq5K9dXRE4/RsZKR
-WtzYc/QeA6FZpwfSjWW3omJSgHopzOaiLaYhXO+aMLVLzeaXQNF1vqlrMDTgFkcN
-OnQQRN2MONQw26+xSYGYpXqyAKVY1aHxOOkrBPzw0vJNYnQSCBZABYEgaD2pPpQk
-BarJKxrHL0FYeuzFOD2vnInMUYjDkrMoN3KbYiU/AsfJ7+nrKutedTVf6FfO9eVq
-obTSNNiasbh13St52zywH5zbsql1OBg9K2MDf8rDBMcuLxcCgcBfM9FWZivdG2tJ
-5REvL0vPAQfcjVi4HUHvnaCuwMYEuF5T2Xf9P8d8ZflfWHaGlkl/qPvE897fns2l
-PZvvhRnr9GlHKt940ZOTI2v+hjlwcHGAAQc+p7BcKeUYLChwhVK/cZ9f6ZCotZNh
-543ecG4KZiJaqBZ/mDRaW7Py0w6lbOAzprrHF3ChvQ6VAllajoWx4CeINRcxX2vP
-bAPZxvt0gwpoHtUAsZo/bKEF0sM5qM/fK43gH5KhJeunq/xHO7E=
------END RSA PRIVATE KEY-----
diff --git a/board/karma/ec.tasklist b/board/karma/ec.tasklist
deleted file mode 100644
index ca4e3b5ee6..0000000000
--- a/board/karma/ec.tasklist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 2048) \
-	/* Larger stack for RW verification (i.e. sha256, rsa) */ \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CEC, cec_task, NULL, TASK_STACK_SIZE)
diff --git a/board/karma/gpio.inc b/board/karma/gpio.inc
deleted file mode 100644
index 1b265ed6ca..0000000000
--- a/board/karma/gpio.inc
+++ /dev/null
@@ -1,108 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(4, 4), GPIO_INT_RISING, backlight_enable_interrupt)
-
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(WP_L,			PIN(9, 3), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus0_evt)
-GPIO_INT(RECOVERY_L,		PIN(8, 2), GPIO_INT_BOTH, button_interrupt)	/* Recovery button */
-GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
-GPIO(PCH_ACPRESENT,		PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_ODR_HIGH)			/* H1 Reset */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
-GPIO(U22_90W,			PIN(3, 4), GPIO_OUTPUT | GPIO_PULL_DOWN)
-GPIO(POWER_RATE,		PIN(7, 1), GPIO_INPUT)				/* High: i3/5/7. Low: Celeron */
-GPIO(PP3300_USB_PD_EN,		PIN(6, 7), GPIO_OUT_HIGH)                       /* Initialize PP3300_USB_PD_EN as output high */
-
-GPIO(LAN_PWR_EN,		PIN(8, 3), GPIO_OUT_HIGH)			/* Ethernet power enabled */
-
-GPIO(PP5000_DX_NFC,		PIN(1, 5), GPIO_OUTPUT)
-
-GPIO(PP3300_DX_CAM,		PIN(1, 0), GPIO_OUT_HIGH)
-GPIO(CAM_PMIC_RST_L,		PIN(0, 7), GPIO_INPUT)
-
-GPIO(WLAN_PE_RST,		PIN(1, 2), GPIO_OUTPUT)
-GPIO(PP3300_DX_LTE,		PIN(0, 5), GPIO_OUT_LOW)
-GPIO(PP3300_DX_BASE,		PIN(1, 1), GPIO_OUT_LOW)
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_BAT_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_BAT_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_ROP_I2C_CLK */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_ROP_I2C_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT)				/* EC_THEM_CLK */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT)				/* EC_THEM_SDA */
-
-/* 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C0 5V Enable */
-GPIO(USB_C0_VBUS_ILIM,		PIN(3, 5), GPIO_OUT_HIGH)
-GPIO(USB_C0_PD_RST_ODL,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(FAN_PWR_EN,		PIN(9, 5), GPIO_OUT_HIGH)			/* Fan power */
-GPIO(USB1_ENABLE,		PIN(3, 2), GPIO_OUT_LOW)			/* Rear port, bottom */
-GPIO(USB2_ENABLE,		PIN(C, 6), GPIO_OUT_LOW)			/* Rear port, top */
-GPIO(USB3_ENABLE,		PIN(A, 1), GPIO_OUT_LOW)			/* Rear port, single */
-GPIO(USB4_ENABLE,		PIN(0, 0), GPIO_OUT_LOW)			/* Front port 1 */
-GPIO(USB_A_CHARGE_EN_L,		PIN(A, 5), GPIO_OUT_LOW)
-
-GPIO(CEC_OUT,			PIN(3, 6), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
-GPIO(CEC_IN,			PIN(4, 0), GPIO_INPUT)
-GPIO(CEC_PULL_UP,		PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_EDID_WRITE_EN_L,	PIN(C, 3), GPIO_OUT_HIGH)			/* LOW to write EDID */
-
-/* Speaker */
-GPIO(SPKR5,			PIN(C, 2), GPIO_INPUT)				/* No function */
-
-GPIO(PANEL_ID_0,		PIN(C, 5), GPIO_INPUT)
-GPIO(PANEL_ID_1,		PIN(0, 1), GPIO_INPUT)
-GPIO(PANEL_ID_2,		PIN(B, 1), GPIO_INPUT)
-
-/* Test points */
-GPIO(TP121,			PIN(3, 3), GPIO_INPUT)
-GPIO(TP127,			PIN(6, 6), GPIO_INPUT)
-GPIO(TP128,			PIN(C, 4), GPIO_INPUT)
-GPIO(TP248,			PIN(5, 7), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0)		/* GPIOA6 */		/* TACH2 */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_USBC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)		/* GPIOB6 */		/* EC_FAN_PWM */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
-/* Alternate functions for LED PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)		/* GPIO80 PWM3 Red*/
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)		/* GPOB7 PWM5 Green*/
diff --git a/board/karma/vif_override.xml b/board/karma/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/karma/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/katsu/board.c b/board/katsu/board.c
deleted file mode 100644
index e487538180..0000000000
--- a/board/katsu/board.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "charger_mt6370.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/mt6370.h"
-#include "driver/usb_mux/it5205.h"
-#include "extpower.h"
-#include "gesture.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_policy.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void gauge_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
-		},
-		.drv = &mt6370_tcpm_drv,
-	},
-};
-
-struct mt6370_thermal_bound thermal_bound = {
-	.target = 80,
-	.err = 4,
-};
-
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-__override const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	static const struct rt946x_init_setting battery_init_setting = {
-		.eoc_current = 140,
-		.mivr = 4000,
-		.ircmp_vclamp = 32,
-		.ircmp_res = 25,
-		.boost_voltage = 5050,
-		.boost_current = 1500,
-	};
-
-	return &battery_init_setting;
-}
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 0);
-		break;
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	case CHARGE_PORT_POGO:
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
-		break;
-#endif
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	if (force_discharge && !enable)
-		rt946x_toggle_bc12_detection();
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int extpower_is_present(void)
-{
-	/*
-	 * The charger will indicate VBUS presence if we're sourcing 5V,
-	 * so exclude such ports.
-	 */
-	int usb_c_extpower_present;
-
-	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
-		usb_c_extpower_present = 0;
-	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
-
-	return usb_c_extpower_present;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
-
-#ifdef SECTION_IS_RW
-	/* Enable interrupts from ICM40608 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-#endif /* SECTION_IS_RW */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable gauge interrupt from max17055 */
-	gpio_enable_interrupt(GPIO_GAUGE_INT_ODL);
-
-	/*
-	 * Fix backlight led maximum current:
-	 * tolerance 120mA * 0.75 = 90mA.
-	 * (b/133655155)
-	 */
-	mt6370_backlight_set_dim(MT6370_BLDIM_DEFAULT * 3 / 4);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_rev_init(void)
-{
-	/* Board revision specific configs. */
-
-	/*
-	 * It's a P1 pin BOOTBLOCK_MUX_OE, also a P2 pin BC12_DET_EN.
-	 * Keep this pin defaults to P1 setting since that eMMC enabled with
-	 * High-Z stat.
-	 */
-	/* TODO */
-	/* Put initial code here for different EC board reversion */
-}
-DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
-
-void sensor_board_proc_double_tap(void)
-{
-	CPRINTS("Detect double tap");
-}
-
-/* Motion sensors */
-/* Mutexes */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static struct mutex g_lid_mutex;
-
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: ICM40608: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-		 /* For double tap detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/*
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-	/*
-	 * Though we have a more tolerant range (3.9V~13.4V), setting 4400 to
-	 * prevent from a bad charger crashed.
-	 *
-	 * TODO(b:131284131): mt6370 VBUS reading is not accurate currently.
-	 * Vendor will provide a workaround solution to fix the gap between ADC
-	 * reading and actual voltage.  After the workaround applied, we could
-	 * try to raise this value to 4600.  (when it says it read 4400, it is
-	 * actually close to 4600)
-	 */
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < 4400;
-}
-
-__override int board_charge_port_is_sink(int port)
-{
-	/* TODO(b:128386458): Check POGO_ADC_INT_L */
-	return 1;
-}
-
-__override int board_charge_port_is_connected(int port)
-{
-	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
-}
-
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
-{
-	r->meas.voltage_now = 3300;
-	r->meas.voltage_max = 3300;
-	r->meas.current_max = 1500;
-	r->meas.current_lim = 1500;
-	r->max_power = r->meas.voltage_now * r->meas.current_max;
-}
-
diff --git a/board/katsu/board.h b/board/katsu/board.h
deleted file mode 100644
index aa6e386d8f..0000000000
--- a/board/katsu/board.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Katsu */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define BQ27541_ADDR	0x55
-#define VARIANT_KUKUI_BATTERY_BQ27541
-#define VARIANT_KUKUI_POGO_KEYBOARD
-
-#define VARIANT_KUKUI_CHARGER_MT6370
-#define VARIANT_KUKUI_EC_STM32F098
-#define VARIANT_KUKUI_TABLET_PWRBTN
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#define CONFIG_USB_MUX_IT5205
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
-
-#define CONFIG_CHARGER_MT6370_BACKLIGHT
-
-
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#endif /* SECTION_IS_RW */
-
-/* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-
-/* Route sbs host requests to virtual battery driver */
-#define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
-
-/* MKBP */
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
-
-#define PD_OPERATING_POWER_MW 15000
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_BATT_ID,
-	ADC_POGO_ADC_INT_L,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-void pogo_adc_interrupt(enum gpio_signal signal);
-int board_discharge_on_ac(int enable);
-
-/* Enable double tap detection */
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-#define CONFIG_GESTURE_TAP_SENSOR 0
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
-#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
-#define CONFIG_GESTURE_TAP_THRES_MG 100
-#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/katsu/build.mk b/board/katsu/build.mk
deleted file mode 100644
index 7a3953b8bb..0000000000
--- a/board/katsu/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=board.o led.o
diff --git a/board/katsu/ec.tasklist b/board/katsu/ec.tasklist
deleted file mode 100644
index fc26f445b2..0000000000
--- a/board/katsu/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
-
diff --git a/board/katsu/gpio.inc b/board/katsu/gpio.inc
deleted file mode 100644
index f938153045..0000000000
--- a/board/katsu/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         icm426xx_interrupt)
-GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event)
-GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(HALL_INT_L,        PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(GAUGE_INT_ODL,     PIN(C, 9),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         gauge_interrupt)
-GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
-         pogo_adc_interrupt)
-
-/* unused */
-GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
-/* unused after board rev 5 */
-GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_INPUT)
-GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_INPUT)
-
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BATT_ID,              PIN(A, 7),  GPIO_ANALOG)
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP3300_POGO,     PIN(A, 13), GPIO_OUT_LOW)
-GPIO(EN_POGO_CHARGE_L,   PIN(B, 6),  GPIO_OUT_HIGH)
-GPIO(EN_USBC_CHARGE_L,   PIN(C, 7),  GPIO_OUT_LOW)
-GPIO(EN_PP5000_USBC,     PIN(D, 2),  GPIO_OUT_LOW)
-GPIO(BC12_DET_EN,        PIN(C, 4),  GPIO_OUT_LOW)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
-#endif
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/katsu/led.c b/board/katsu/led.c
deleted file mode 100644
index c72f5e4cdb..0000000000
--- a/board/katsu/led.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Katsu board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "driver/charger/rt946x.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "power.h"
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_AMBER	MT6370_LED_ID1
-#define LED_WHITE	MT6370_LED_ID2
-
-#define LED_MASK_OFF	0
-#define LED_MASK_AMBER	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK2DIM_EN
-
-static void katsu_led_set_battery(void)
-{
-	enum charge_state chstate;
-	enum power_state powerstate;
-	static uint8_t prv_white, prv_amber;
-	static uint8_t time_cnt;
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	chstate = charge_get_state();
-	powerstate = power_get_state();
-
-	switch (chstate) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (charge_get_percent() < 94) {
-			br[EC_LED_COLOR_AMBER] = 1;
-			br[EC_LED_COLOR_WHITE] = 0;
-			break;
-		}
-		br[EC_LED_COLOR_WHITE] = 1;
-		br[EC_LED_COLOR_AMBER] = 0;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (powerstate == POWER_S0) {
-			/* display SoC 10% = real battery SoC 13%*/
-			if (charge_get_percent() < 14) {
-				if (time_cnt < 1) {
-					time_cnt++;
-					br[EC_LED_COLOR_WHITE] = 0;
-					br[EC_LED_COLOR_AMBER] = 1;
-				} else {
-					time_cnt++;
-					br[EC_LED_COLOR_WHITE] = 0;
-					br[EC_LED_COLOR_AMBER] = 0;
-					if (time_cnt > 3)
-						time_cnt = 0;
-				}
-				break;
-			}
-			br[EC_LED_COLOR_WHITE] = 1;
-			br[EC_LED_COLOR_AMBER] = 0;
-			break;
-		} else if (powerstate == POWER_S3) {
-			if (time_cnt < 2) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 1;
-				br[EC_LED_COLOR_AMBER] = 0;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 3)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
-			br[EC_LED_COLOR_WHITE] = 0;
-			br[EC_LED_COLOR_AMBER] = 0;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		if (powerstate == POWER_S0) {
-			if (time_cnt < 1) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 1;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 1)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S3) {
-			if (time_cnt < 2) {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 1;
-				br[EC_LED_COLOR_AMBER] = 0;
-			} else {
-				time_cnt++;
-				br[EC_LED_COLOR_WHITE] = 0;
-				br[EC_LED_COLOR_AMBER] = 0;
-				if (time_cnt > 3)
-					time_cnt = 0;
-			}
-			break;
-		} else if (powerstate == POWER_S5 || powerstate == POWER_G3) {
-			br[EC_LED_COLOR_WHITE] = 0;
-			br[EC_LED_COLOR_AMBER] = 0;
-		}
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		return;
-	}
-
-	if (prv_white == br[EC_LED_COLOR_WHITE] &&
-	    prv_amber == br[EC_LED_COLOR_AMBER])
-		return;
-
-	prv_white = br[EC_LED_COLOR_WHITE];
-	prv_amber = br[EC_LED_COLOR_AMBER];
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return;
-
-	brightness_range[EC_LED_COLOR_WHITE] = MT6370_LED_BRIGHTNESS_MAX;
-	brightness_range[EC_LED_COLOR_AMBER] = MT6370_LED_BRIGHTNESS_MAX;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	uint8_t white, amber;
-
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return EC_ERROR_INVAL;
-
-	white = brightness[EC_LED_COLOR_WHITE];
-	amber = brightness[EC_LED_COLOR_AMBER];
-
-	mt6370_led_set_brightness(LED_WHITE, white);
-	mt6370_led_set_brightness(LED_AMBER, amber);
-
-	/* Enables LED sink power if necessary. */
-	mt6370_led_set_color((white ? LED_MASK_WHITE : 0) |
-			     (amber ? LED_MASK_AMBER : 0));
-	return EC_SUCCESS;
-}
-
-static void katsu_led_init(void)
-{
-	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
-	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-
-	mt6370_led_set_color(0);
-	mt6370_led_set_dim_mode(LED_WHITE, dim);
-	mt6370_led_set_dim_mode(LED_AMBER, dim);
-	mt6370_led_set_pwm_frequency(LED_WHITE, freq);
-	mt6370_led_set_pwm_frequency(LED_AMBER, freq);
-	mt6370_led_set_pwm_dim_duty(LED_WHITE, 255);
-	mt6370_led_set_pwm_dim_duty(LED_AMBER, 255);
-}
-DECLARE_HOOK(HOOK_INIT, katsu_led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		katsu_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
-__override void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		return;
-	}
-
-	if (state)
-		br[EC_LED_COLOR_WHITE] = 1;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
diff --git a/board/katsu/vif_override.xml b/board/katsu/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/katsu/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kindred/battery.c b/board/kindred/battery.c
deleted file mode 100644
index 9db25ac059..0000000000
--- a/board/kindred/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Hatch battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/kindred/board.c b/board/kindred/board.c
deleted file mode 100644
index c17ddb1b8a..0000000000
--- a/board/kindred/board.c
+++ /dev/null
@@ -1,661 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static int lid_device_id;
-static int base_device_id;
-
-static void check_reboot_deferred(void);
-DECLARE_DEFERRED(check_reboot_deferred);
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-		{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	baseboard_mst_enable_control(MST_HDMI, gpio_get_level(signal));
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		.flags = 0,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-static struct kionix_accel_data g_kx022_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_icm_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 2, /* g, enough for laptop */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3200,
-	.rpm_start = 3200,
-	.rpm_max = 6500,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Hatch Temperature sensors */
-/*
- * TODO(b/124316213): These setting need to be reviewed and set appropriately
- * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(75),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(55),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(55),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-/* Sets the gpio flags correct taking into account warm resets */
-static void reset_gpio_flags(enum gpio_signal signal, int flags)
-{
-	/*
-	 * If the system was already on, we cannot set the value otherwise we
-	 * may change the value from the previous image which could cause a
-	 * brownout.
-	 */
-	if (system_is_reboot_warm() || system_jumped_late())
-		flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-	gpio_set_flags(signal, flags);
-}
-
-/* Runtime GPIO defaults */
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A_V1;
-
-static void board_gpio_set_pp5000(void)
-{
-	uint32_t board_id = 0;
-
-	/* Errors will count as board_id 0 */
-	cbi_get_board_version(&board_id);
-
-	if (board_id == 0) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V0, GPIO_OUT_LOW);
-		/* Change runtime default for V0 */
-		gpio_en_pp5000_a = GPIO_EN_PP5000_A_V0;
-	} else if (board_id >= 1) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
-	}
-
-}
-
-bool board_is_convertible(void)
-{
-	uint8_t sku_id = get_board_sku();
-	/* SKU ID of Kled : 1, 2, 3, 4 */
-	return (sku_id >= 1) && (sku_id <= 4);
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	/*
-	 * There are two possible sensor configurations. Clamshell device will
-	 * not have any of the motion sensors populated, while convertible
-	 * devices have the BMI160 Accel/Gryo lid acceleration sensor.
-	 * If a new SKU id is used that is not in the threshold, then the
-	 * number of motion sensors will remain as ARRAY_SIZE(motion_sensors).
-	 */
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-		CPRINTS("Motion Sensor Count = %d", motion_sensor_count);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void anx7447_set_aux_switch(void)
-{
-	const int port = USB_PD_PORT_TCPC_0;
-
-	/* Debounce */
-	if (gpio_get_level(GPIO_CCD_MODE_ODL))
-		return;
-
-	/*
-	 * Expect to set AUX_SWITCH to 0, but 0xc isolates the DP_AUX
-	 * signal from SBU.
-	 */
-	CPRINTS("C%d: AUX_SW_SEL=0x%x", port, 0xc);
-	if (tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc))
-		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
-}
-DECLARE_DEFERRED(anx7447_set_aux_switch);
-
-void ccd_mode_isr(enum gpio_signal signal)
-{
-	/* Wait 2 seconds until all mux setting is done by PD task */
-	hook_call_deferred(&anx7447_set_aux_switch_data, 2 * SECOND);
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-	/* Trigger once to set mux in case CCD cable is already connected. */
-	ccd_mode_isr(GPIO_CCD_MODE_ODL);
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-	/* Select correct gpio signal for PP5000_A control */
-	board_gpio_set_pp5000();
-	/* Use sku_id to set motion sensor count */
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void determine_accel_devices(void)
-{
-	static uint8_t read_time;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	if (read_time == 0 && board_is_convertible()) {
-		/* Read g sensor chip id*/
-		i2c_read8(I2C_PORT_ACCEL,
-			  KX022_ADDR0_FLAGS, KX022_WHOAMI, &lid_device_id);
-		/* Read gyro sensor id*/
-		i2c_read8(I2C_PORT_ACCEL,
-			  ICM426XX_ADDR0_FLAGS,
-			    ICM426XX_REG_WHO_AM_I, &base_device_id);
-
-		CPRINTS("Motion Sensor Base id = %d Lid id =%d",
-			  base_device_id, lid_device_id);
-
-		if (lid_device_id == KX022_WHO_AM_I_VAL) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			ccprints("Lid Accel is KX022");
-		} else
-			ccprints("Lid Accel is BMA255");
-
-		if (base_device_id == ICM426XX_CHIP_ICM40608) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE Accel is ICM426XX");
-		} else
-			ccprints("BASE Accel is BMI160");
-
-		read_time++;
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, determine_accel_devices, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, determine_accel_devices, HOOK_PRIO_INIT_ADC + 2);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_device_id) {
-	case ICM426XX_CHIP_ICM40608:
-		icm426xx_interrupt(signal);
-		break;
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-bool board_has_kb_backlight(void)
-{
-	uint8_t sku_id = get_board_sku();
-	/* SKU ID of Kled with KB backlight: 1, 2, 3, 4 */
-	return (sku_id >= 1) && (sku_id <= 4);
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	if (board_has_kb_backlight())
-		return flags0;
-	else
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-}
-
-void all_sys_pgood_check_reboot(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC);
-}
-
-__override void board_chipset_forced_shutdown(void)
-{
-	hook_call_deferred(&check_reboot_deferred_data, -1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, HOOK_PRIO_DEFAULT);
-
-static void check_reboot_deferred(void)
-{
-	if (!gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD))
-		system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED);
-}
diff --git a/board/kindred/board.h b/board/kindred/board.h
deleted file mode 100644
index 79fc7c0642..0000000000
--- a/board/kindred/board.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hatch board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-#define GPIO_EN_PP5000_A gpio_en_pp5000_a
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-
-void motion_interrupt(enum gpio_signal signal);
-
-void ccd_mode_isr(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kindred/build.mk b/board/kindred/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/kindred/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/kindred/ec.tasklist b/board/kindred/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/kindred/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/kindred/gpio.inc b/board/kindred/gpio.inc
deleted file mode 100644
index 2adb08f564..0000000000
--- a/board/kindred/gpio.inc
+++ /dev/null
@@ -1,146 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, motion_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* CCD mode line*/
-GPIO_INT(CCD_MODE_ODL,         PIN(E, 5), GPIO_INT_FALLING, ccd_mode_isr)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A_V1,           PIN(A, 4), GPIO_DEFAULT)
-GPIO(EN_PP5000_A_V0,           PIN(7, 3), GPIO_DEFAULT)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue (kindred) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Yellow (kindred) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(LED_4_L,                  PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)                             /* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/kindred/led.c b/board/kindred/led.c
deleted file mode 100644
index 9eb195d0b6..0000000000
--- a/board/kindred/led.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Hatch
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/kindred/vif_override.xml b/board/kindred/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kindred/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kingoftown/battery.c b/board/kingoftown/battery.c
deleted file mode 100644
index c039fb3e45..0000000000
--- a/board/kingoftown/battery.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all kingoftown battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack HIGHPOWER Battery Information */
-	[BATTERY_DYNAPACK_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2D-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack BYD Battery Information */
-	[BATTERY_DYNAPACK_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2E-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* ATL GB-S20-4473A9-01H&020H Battery Information
-	 * Gauge IC : RAJ240045
-	 */
-	[BATTERY_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "313-B7-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_HIGHPOWER;
diff --git a/board/kingoftown/board.c b/board/kingoftown/board.c
deleted file mode 100644
index cc0005d775..0000000000
--- a/board/kingoftown/board.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kingoftown board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
-	 * as it still uses the legacy location (KSO_01/KSI_00).
-	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable interrupt for BMI160 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/kingoftown/board.h b/board/kingoftown/board.h
deleted file mode 100644
index b1d9cc3c5c..0000000000
--- a/board/kingoftown/board.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kingoftown board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
-#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_HIGHPOWER,
-	BATTERY_DYNAPACK_BYD,
-	BATTERY_COS,
-	BATTERY_ATL,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kingoftown/build.mk b/board/kingoftown/build.mk
deleted file mode 100644
index 5415d90b29..0000000000
--- a/board/kingoftown/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=hibernate.o
-board-y+=led.o
-board-y+=switchcap.o
-board-y+=usbc_config.o
diff --git a/board/kingoftown/ec.tasklist b/board/kingoftown/ec.tasklist
deleted file mode 100644
index 5beeb38feb..0000000000
--- a/board/kingoftown/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/kingoftown/gpio.inc b/board/kingoftown/gpio.inc
deleted file mode 100644
index fcc863c77b..0000000000
--- a/board/kingoftown/gpio.inc
+++ /dev/null
@@ -1,187 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
- * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 0))
-UNUSED(PIN(D, 3))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/kingoftown/hibernate.c b/board/kingoftown/hibernate.c
deleted file mode 100644
index 504a295463..0000000000
--- a/board/kingoftown/hibernate.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-
-void board_hibernate(void)
-{
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-}
diff --git a/board/kingoftown/led.c b/board/kingoftown/led.c
deleted file mode 100644
index 295c8effeb..0000000000
--- a/board/kingoftown/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_LEFT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_LEFT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/board/kingoftown/switchcap.c b/board/kingoftown/switchcap.c
deleted file mode 100644
index 16b0db6ef6..0000000000
--- a/board/kingoftown/switchcap.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "power/qcom.h"
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_PG);
-}
diff --git a/board/kingoftown/usbc_config.c b/board/kingoftown/usbc_config.c
deleted file mode 100644
index 81a63be9b3..0000000000
--- a/board/kingoftown/usbc_config.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kingoftown board-specific USB-C configuration */
-
-#include "bc12/pi3usb9201_public.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ppc/sn5s330_public.h"
-#include "system.h"
-#include "tcpm/ps8xxx_public.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_config.h"
-#include "usb_mux.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Initialize board USC-C things */
-static void board_init_usbc(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/board/kingoftown/usbc_config.h b/board/kingoftown/usbc_config.h
deleted file mode 100644
index 654da35f74..0000000000
--- a/board/kingoftown/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kingoftown board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#include "gpio.h"
-
-void tcpc_alert_event(enum gpio_signal signal);
-void usb0_evt(enum gpio_signal signal);
-void usb1_evt(enum gpio_signal signal);
-void usba_oc_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kingoftown/vif_override.xml b/board/kingoftown/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kingoftown/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kodama/analyzestack.yaml b/board/kodama/analyzestack.yaml
deleted file mode 100644
index 4a057ce818..0000000000
--- a/board/kodama/analyzestack.yaml
+++ /dev/null
@@ -1,3 +0,0 @@
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
diff --git a/board/kodama/battery.c b/board/kodama/battery.c
deleted file mode 100644
index 1dbff92a00..0000000000
--- a/board/kodama/battery.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "charger_mt6370.h"
-#include "console.h"
-#include "driver/charger/rt946x.h"
-#include "gpio.h"
-#include "power.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 4400,
-			.voltage_normal		= 3840,
-			.voltage_min		= 3000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_CELXPERT] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L19C3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 4400,
-			.voltage_normal		= 3840,
-			.voltage_min		= 2800,
-			.precharge_current	= 404,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	const struct battery_info *batt_info = battery_get_info();
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-
-#ifdef VARIANT_KUKUI_CHARGER_MT6370
-	mt6370_charger_profile_override(curr);
-#endif /* CONFIG_CHARGER_MT6370 */
-
-	/*
-	 * When smart battery temperature is more than 45 deg C, the max
-	 * charging voltage is 4100mV.
-	 */
-	if (curr->state == ST_CHARGE && bat_temp_c >= 450
-		&& !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE))
-		curr->requested_voltage	= 4100;
-	else
-		curr->requested_voltage = batt_info->voltage_max;
-
-	/*
-	 * mt6370's minimum regulated current is 500mA REG17[7:2] 0b100,
-	 * values below 0b100 are preserved. In the other hand, it makes sure
-	 * mt6370's VOREG set as 4400mV and minimum value of mt6370's ICHG
-	 * is limited as 500mA.
-	 */
-	curr->requested_current = MAX(500, curr->requested_current);
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/kodama/board.c b/board/kodama/board.c
deleted file mode 100644
index 33ecbba384..0000000000
--- a/board/kodama/board.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "charger_mt6370.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/mt6370.h"
-#include "driver/usb_mux/it5205.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA,
-		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
-		},
-		.drv = &mt6370_tcpm_drv,
-	},
-};
-
-struct mt6370_thermal_bound thermal_bound = {
-	.target = 75,
-	.err = 4,
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-
-__override const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	static const struct rt946x_init_setting battery_init_setting = {
-		.eoc_current = 150,
-		.mivr = 4000,
-		.ircmp_vclamp = 32,
-		.ircmp_res = 25,
-		.boost_voltage = 5050,
-		.boost_current = 1500,
-	};
-
-	return &battery_init_setting;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	if (force_discharge && !enable)
-		rt946x_toggle_bc12_detection();
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int extpower_is_present(void)
-{
-	/*
-	 * The charger will indicate VBUS presence if we're sourcing 5V,
-	 * so exclude such ports.
-	 */
-	int usb_c_extpower_present;
-
-	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
-		usb_c_extpower_present = 0;
-	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
-
-	return usb_c_extpower_present;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-#define CHARGER_I2C_ADDR_FLAGS RT946X_ADDR_FLAGS
-
-static void board_init(void)
-{
-#ifdef SECTION_IS_RW
-	int val;
-
-	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-			RT946X_REG_CHGCTRL1, &val);
-	val &= RT946X_MASK_OPA_MODE;
-	i2c_write8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-		RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
-#endif
-
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
-
-#ifdef SECTION_IS_RW
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-#endif /* SECTION_IS_RW */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* reduce mt6370 db and bl driving capacity */
-	mt6370_reduce_db_bl_driving();
-
-	/* Display bias settings. */
-	mt6370_db_set_voltages(6000, 5800, 5800);
-
-	/*
-	 * Fix backlight led maximum current:
-	 * tolerance 120mA * 0.75 = 90mA.
-	 * (b/133655155)
-	 */
-	mt6370_backlight_set_dim(MT6370_BLDIM_DEFAULT * 3 / 4);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/*
- * Re-configure i2c-2 to 100kHz for EVT devices, this must execute after
- * i2c_init (in main()) and before battery fuel gauge access the battery
- * (i.e. HOOK_PRIO_I2C + 1).
- *
- * Note that stm32f0 don't run adc_init in hooks, so we can safely call
- * board_get_version() before HOOK_PRIO_INIT_ADC(=HOOK_PRIO_DEFAULT).
- */
-static void board_i2c_init(void)
-{
-	if (board_get_version() < 2)
-		i2c_set_freq(1,  I2C_FREQ_100KHZ);
-}
-DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C);
-
-/* Motion sensors */
-/* Mutexes */
-#ifdef SECTION_IS_RW
-static struct mutex g_lid_mutex;
-
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_ACCEL_INT_ODL,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 13000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#endif /* SECTION_IS_RW */
-
-/*
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-	/*
-	 * Though we have a more tolerant range (3.9V~13.4V), setting 4400 to
-	 * prevent from a bad charger crashed.
-	 *
-	 * TODO(b:131284131): mt6370 VBUS reading is not accurate currently.
-	 * Vendor will provide a workaround solution to fix the gap between ADC
-	 * reading and actual voltage.  After the workaround applied, we could
-	 * try to raise this value to 4600.  (when it says it read 4400, it is
-	 * actually close to 4600)
-	 */
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < 4400;
-}
-
-int board_get_battery_i2c(void)
-{
-	return board_get_version() >= 2 ? 2 : 1;
-}
diff --git a/board/kodama/board.h b/board/kodama/board.h
deleted file mode 100644
index 48e39b2300..0000000000
--- a/board/kodama/board.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_MT6370
-#define VARIANT_KUKUI_EC_STM32F098
-#define VARIANT_KUKUI_POGO_KEYBOARD
-#define VARIANT_KUKUI_TABLET_PWRBTN
-#undef CONFIG_CMD_MFALLOW
-
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#define CONFIG_DEBUG_ASSERT_BRIEF
-
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 3
-#define CONFIG_SMBUS_PEC
-
-/* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
-
-#define CONFIG_CHARGER_MT6370_BACKLIGHT
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#endif /* SECTION_IS_RW */
-
-/* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BATTERY  board_get_battery_i2c()
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_INPUT_DEVICES
-
-#define PD_OPERATING_POWER_MW 15000
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_POGO_ADC_INT_L,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_SIMPLO,
-	BATTERY_CELXPERT,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-void pogo_adc_interrupt(enum gpio_signal signal);
-int board_discharge_on_ac(int enable);
-/* returns the i2c port number of battery */
-int board_get_battery_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kodama/build.mk b/board/kodama/build.mk
deleted file mode 100644
index 0b3565fd84..0000000000
--- a/board/kodama/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/kodama/ec.tasklist b/board/kodama/ec.tasklist
deleted file mode 100644
index f71a208dd6..0000000000
--- a/board/kodama/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
-
diff --git a/board/kodama/gpio.inc b/board/kodama/gpio.inc
deleted file mode 100644
index 75a3db7d20..0000000000
--- a/board/kodama/gpio.inc
+++ /dev/null
@@ -1,106 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         lsm6dsm_interrupt)
-GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event)
-GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(HALL_INT_L,        PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
-         pogo_adc_interrupt)
-
-/* unused */
-GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
-
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(B, 6),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(D, 2),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(BATT_CUTOFF_INDICATOR, PIN(A, 5),  GPIO_OUT_LOW)
-GPIO(EN_PP3300_POGO,       PIN(A, 13), GPIO_OUT_LOW)
-GPIO(BC12_DET_EN,          PIN(C, 4),  GPIO_OUT_LOW)
-
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
-#endif
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/kodama/led.c b/board/kodama/led.c
deleted file mode 100644
index d96b340d73..0000000000
--- a/board/kodama/led.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Kukui board.
- */
-#include "charge_state.h"
-#include "driver/charger/rt946x.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "ec_commands.h"
-
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_WHITE	MT6370_LED_ID3
-
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK3DIM_EN
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   LED_ONE_SEC / 2} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static int led_mask = LED_MASK_OFF;
-
-static void led_set_color(int mask)
-{
-	static int new_mask = LED_MASK_OFF;
-
-	if (new_mask == mask)
-		return;
-	else
-		new_mask = mask;
-
-	mt6370_led_set_color(led_mask);
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		led_mask |= LED_MASK_WHITE;
-	else
-		led_mask &= ~LED_MASK_WHITE;
-	led_set_color(led_mask);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		led_mask |= LED_MASK_RED;
-		led_mask &= ~LED_MASK_GREEN;
-		break;
-	case EC_LED_COLOR_AMBER:
-		led_mask |= LED_MASK_RED;
-		led_mask |= LED_MASK_GREEN;
-		break;
-	case EC_LED_COLOR_GREEN:
-		led_mask &= ~LED_MASK_RED;
-		led_mask |= LED_MASK_GREEN;
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		led_mask &= ~LED_MASK_RED;
-		led_mask &= ~LED_MASK_GREEN;
-		break;
-	}
-	led_set_color(led_mask);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void kodama_led_init(void)
-{
-	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
-	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-
-	mt6370_led_set_color(LED_MASK_RED | LED_MASK_GREEN | LED_MASK_WHITE);
-	mt6370_led_set_dim_mode(LED_RED, dim);
-	mt6370_led_set_dim_mode(LED_GREEN, dim);
-	mt6370_led_set_dim_mode(LED_WHITE, dim);
-	mt6370_led_set_pwm_frequency(LED_RED, freq);
-	mt6370_led_set_pwm_frequency(LED_GREEN, freq);
-	mt6370_led_set_pwm_frequency(LED_WHITE, freq);
-	mt6370_led_set_pwm_dim_duty(LED_RED, 12);
-	mt6370_led_set_pwm_dim_duty(LED_GREEN, 31);
-	mt6370_led_set_pwm_dim_duty(LED_WHITE, 12);
-	mt6370_led_set_brightness(LED_MASK_RED, 7);
-	mt6370_led_set_brightness(LED_MASK_GREEN, 7);
-	mt6370_led_set_brightness(LED_MASK_WHITE, 7);
-}
-DECLARE_HOOK(HOOK_INIT, kodama_led_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kodama/vif_override.xml b/board/kodama/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kodama/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kohaku/battery.c b/board/kohaku/battery.c
deleted file mode 100644
index 8d35008f6e..0000000000
--- a/board/kohaku/battery.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-#include "system.h"
-#include "util.h"
-
-/*
- * Battery info for all Hatch battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-/* charging current is limited to 0.45C */
-#define CHARGING_CURRENT_45C 2804
-
-const struct board_batt_params board_battery_info[] = {
-	/* Dyna Battery Information */
-	[BATTERY_DYNA] = {
-		.fuel_gauge = {
-			.manuf_name = "Dyna",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8700,
-			.voltage_normal		= 7600, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 150,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4404D62",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 55,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-enum battery_present variant_battery_present(void)
-{
-	if (system_get_board_version() != 1)
-		return BP_NOT_SURE;
-
-	/*
-	 * For board version 1, there is a known issue with battery present
-	 * signal. So, always return BP_YES indicating battery is
-	 * present. battery_status() later should fail to talk to the battery in
-	 * case the battery is not really present.
-	 */
-	return BP_YES;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return 0;
-
-	if (curr->requested_current > CHARGING_CURRENT_45C)
-		curr->requested_current = CHARGING_CURRENT_45C;
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/kohaku/board.c b/board/kohaku/board.c
deleted file mode 100644
index 0204cdd87f..0000000000
--- a/board/kohaku/board.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kohaku board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_bh1730.h"
-#include "driver/als_tcs3400.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/bc12/max14637.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC 1.2 chip Configuration */
-const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
-		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* BH1730 private data */
-struct bh1730_drv_data_t g_bh1730_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(0.74),     /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 3, /* 3.0350726 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.34710205),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(1.72064361),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-0.95427326),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.20677441),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(0.5)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 7, /* 6.50411397 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.40729596),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(1.82527267),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(-1.01523751),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.20903764),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = -4, /* -4.13932233 */
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-2.35802533),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.19742447),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.13837045),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.07436207),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.44)
-		}
-	},
-	.calibration.irt = FLOAT_TO_FP(0.35),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[BASE_ALS] = {
-		.name = "Light",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_BH1730,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bh1730_drv,
-		.drv_data = &g_bh1730_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BH1730_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 65535,
-		.min_frequency = BH1730_MIN_FREQ,
-		.max_frequency = BH1730_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = BH1730_10000_MHZ,
-			},
-		},
-	},
-
-	[VSYNC] = {
-		.name = "Camera VSYNC",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_GPIO,
-		.type = MOTIONSENSE_TYPE_SYNC,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &sync_drv,
-		.default_range = 0,
-		.min_frequency = 0,
-		.max_frequency = 1,
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_ALS,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[BASE_ALS],
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-/**********************************************************************/
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Kohaku Temperature sensors */
-/*
- * TODO(b/138578073): These setting need to be reviewed and set appropriately
- * for Kohaku. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-	[TEMP_SENSOR_2] = thermal_a,
-	[TEMP_SENSOR_3] = thermal_a,
-	[TEMP_SENSOR_4] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A;
-
-static void board_init(void)
-{
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable gpio interrupt for camera vsync */
-	gpio_enable_interrupt(GPIO_WFCAM_VSYNC);
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_TCS3400_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-int board_tcpc_post_init(int port)
-{
-	int rv = EC_SUCCESS;
-
-	if (port == USB_PD_PORT_TCPC_0)
-		/* Set MUX_DP_EQ to 3.6dB (0x98) */
-		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-
-	return rv;
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255) || (sku == 1);
-}
diff --git a/board/kohaku/board.h b/board/kohaku/board.h
deleted file mode 100644
index 895a30f0d2..0000000000
--- a/board/kohaku/board.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kohaku board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
-#define CONFIG_DPTF_MULTI_PROFILE
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-/* BH1730 and TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 2
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
-#define CONFIG_ALS_BH1730
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(BASE_ALS) | BIT(CLEAR_ALS))
-
-/* Parameter to calculate LUX on Kohaku */
-#define CONFIG_ALS_BH1730_LUXTH_PARAMS
-/*
- * Calulation formula depends on characteristic of optical window.
- * In case of kohaku, we can select two different formula
- * as characteristic of optical window.
- * BH1730_LUXTH1_1K is charateristic of optical window.
- * 1. d1_1K/d0_1K * 1000 <  BH1730_LUXTH1_1K
- * 2. d1_1K/d0_1K * 1000 >= BH1730_LUXTH1_1K
- * d0 and d1 are unsigned 16 bit. So, d1/d0 max is 65535
- * To meet 2nd condition, make BH1730_LUXTH2_1K to (max+1)*1000
- * Kohaku will not use both BH1730_LUXTH3_1K condition
- * and BH1730_LUXTH4_1K condition.
- */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY 0
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_3_L
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_2_L
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_MAX14637
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set via experimentation by finding how high it can be set and still boot
- * the AP successfully, then backing off to provide margin.
- *
- * TODO(b/133444665): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Thermal features */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
-	ADC_TEMP_SENSOR_4,	/* ADC3 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	BASE_ALS,
-	VSYNC,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNA,
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kohaku/build.mk b/board/kohaku/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/kohaku/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/kohaku/ec.tasklist b/board/kohaku/ec.tasklist
deleted file mode 100644
index 63d366a33b..0000000000
--- a/board/kohaku/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/kohaku/gpio.inc b/board/kohaku/gpio.inc
deleted file mode 100644
index 742a570cf8..0000000000
--- a/board/kohaku/gpio.inc
+++ /dev/null
@@ -1,163 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-GPIO_INT(WFCAM_VSYNC,          PIN(B, 7), GPIO_INT_RISING , sync_interrupt)
-GPIO_INT(TCS3400_INT_ODL,      PIN(7, 2), GPIO_INT_FALLING, tcs3400_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(USB_C0_BC12_CHG_DET_L,    PIN(6, 0), GPIO_INPUT)
-GPIO(USB_C1_BC12_CHG_DET_L,    PIN(9, 6), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON,      PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_BC12_VBUS_ON,      PIN(C, 6), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(LID_ACCEL_INT_L,          PIN(5, 0), GPIO_INPUT |          /* Lid accelerometer */
-                                          GPIO_SEL_1P8V)
-
-/*
- * TODO: b/130822500
- * Configured as if it were NC for now
- */
-GPIO(M2_SD_PLN,                PIN(A, 0), GPIO_INPUT |          /* Provide SSD a shutdown warning */
-                                          GPIO_PULL_UP)
-
-/*
- * TODO: b/130824532
- * Configured as if it were NC for now (but has external 1K pulldown)
- */
-GPIO(IMVP8_PE,                 PIN(A, 7), GPIO_INPUT)          /* Pull high to flash MPS part */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* NC / TP */
-GPIO(TP58,                     PIN(0, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP73,                     PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP18,                     PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP54,                     PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP56,                     PIN(6, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP57,                     PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP55,                     PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP59,                     PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)                             /* ADC0-3 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/kohaku/led.c b/board/kohaku/led.c
deleted file mode 100644
index 029cf5c315..0000000000
--- a/board/kohaku/led.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Kohaku
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Kohaku : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	if (color == EC_LED_COLOR_BLUE)
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	/* Battery leds must be turn off when blue led is on
-	 * because kohaku has 3-in-1 led.
-	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/kohaku/vif_override.xml b/board/kohaku/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kohaku/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kracko/battery.c b/board/kracko/battery.c
deleted file mode 100644
index 13faf9f12b..0000000000
--- a/board/kracko/battery.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all kracko battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Battery Information */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-4473A9PU",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO;
diff --git a/board/kracko/board.c b/board/kracko/board.c
deleted file mode 100644
index 99dcd56810..0000000000
--- a/board/kracko/board.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kracko board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-uint32_t board_version;
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-__override void board_process_pd_alert(int port)
-{
-	/*
-	 * PD_INT task will process this alert, and that task is only needed on
-	 * C1.
-	 */
-	if (port != 1)
-		return;
-
-	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return;
-
-	sm5803_handle_interrupt(port);
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
-		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	else
-		button_interrupt(s);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-static struct kionix_accel_data g_kx022_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_kx022_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Drivers */
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_kx022_ref,
-		.default_range = 2, /* g, enough for laptop. */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100,
-			},
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-	} else {
-		/* Select AUX option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 1);
-	}
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/* Store board version for use in determining charge limits */
-	cbi_get_board_version(&board_version);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Second source LID ACCEL */
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			ccprints("LID ACCEL is KX022");
-		} else
-			ccprints("LID ACCEL is BMA253");
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	if (board_get_charger_chip_count() > 1) {
-		/* Charger on the sub-board will be a push-pull GPIO */
-		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-static void board_suspend(void)
-{
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-
-	if (board_get_charger_chip_count() > 1) {
-		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CHARGER_NUM;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/* Limit C1 on board version 0 to 2.0 A */
-	if ((board_version == 0) && (port == 1))
-		icl = MIN(icl, 2000);
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	charger_set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 20;
-
-	*ki = 3;
-	*ki_div = 125;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/kracko/board.h b/board/kracko/board.h
deleted file mode 100644
index ce26c90b70..0000000000
--- a/board/kracko/board.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kracko board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-#undef GPIO_VOLUME_UP_L
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/* PWM */
-#define CONFIG_PWM
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_PWM_KBLIGHT
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SIMPLO,
-	BATTERY_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kracko/build.mk b/board/kracko/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/kracko/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/kracko/cbi_ssfc.c b/board/kracko/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/kracko/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/kracko/cbi_ssfc.h b/board/kracko/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/kracko/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/kracko/ec.tasklist b/board/kracko/ec.tasklist
deleted file mode 100644
index 5c9a2d1a01..0000000000
--- a/board/kracko/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/kracko/gpio.inc b/board/kracko/gpio.inc
deleted file mode 100644
index cdcf8834c7..0000000000
--- a/board/kracko/gpio.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA3_NC,	PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* LED */
-GPIO(BAT_LED_ORANGE_L,	 PIN(A, 1), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_BLUE_L,	 PIN(A, 2), GPIO_OUT_HIGH)	/* LED_2_L */
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/kracko/led.c b/board/kracko/led.c
deleted file mode 100644
index af78cfa883..0000000000
--- a/board/kracko/led.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power and battery LED control for Kracko. */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Kracko: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/kracko/usb_pd_policy.c b/board/kracko/usb_pd_policy.c
deleted file mode 100644
index 3ff7152541..0000000000
--- a/board/kracko/usb_pd_policy.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	prev_en = charger_is_sourcing_otg_power(port);
-
-	/* Disable Vbus */
-	charger_enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable sinking */
-	rv = sm5803_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	charger_enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return sm5803_is_vbus_present(port);
-}
diff --git a/board/kracko/vif_override.xml b/board/kracko/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kracko/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/krane b/board/krane
deleted file mode 120000
index 0b14d5a383..0000000000
--- a/board/krane
+++ /dev/null
@@ -1 +0,0 @@
-kukui
\ No newline at end of file
diff --git a/board/kukui/analyzestack.yaml b/board/kukui/analyzestack.yaml
deleted file mode 100644
index 4a057ce818..0000000000
--- a/board/kukui/analyzestack.yaml
+++ /dev/null
@@ -1,3 +0,0 @@
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
diff --git a/board/kukui/board.c b/board/kukui/board.c
deleted file mode 100644
index 9abcc08cdc..0000000000
--- a/board/kukui/board.c
+++ /dev/null
@@ -1,611 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "charger_mt6370.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/mt6370.h"
-#include "driver/usb_mux/it5205.h"
-#include "extpower.h"
-#include "gesture.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_policy.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void gauge_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#define BC12_I2C_ADDR_FLAGS PI3USB9201_I2C_ADDR_3_FLAGS
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = MT6370_TCPC_I2C_ADDR_FLAGS,
-		},
-		.drv = &mt6370_tcpm_drv,
-	},
-};
-
-struct mt6370_thermal_bound thermal_bound = {
-	.target = 80,
-	.err = 4,
-};
-
-void board_set_dp_mux_control(int output_enable, int polarity)
-{
-	if (board_get_version() >= 5)
-		return;
-
-	gpio_set_level(GPIO_USB_C0_DP_OE_L, !output_enable);
-	if (output_enable)
-		gpio_set_level(GPIO_USB_C0_DP_POLARITY, polarity);
-}
-
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-__override const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	static const struct rt946x_init_setting battery_init_setting = {
-		.eoc_current = 140,
-		.mivr = 4000,
-		.ircmp_vclamp = 32,
-		.ircmp_res = 25,
-		.boost_voltage = 5050,
-		.boost_current = 1500,
-	};
-
-	return &battery_init_setting;
-}
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 0);
-		break;
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	case CHARGE_PORT_POGO:
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 0);
-		break;
-#endif
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		gpio_set_level(GPIO_EN_POGO_CHARGE_L, 1);
-		gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	if (force_discharge && !enable)
-		rt946x_toggle_bc12_detection();
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-#ifndef VARIANT_KUKUI_POGO_KEYBOARD
-int kukui_pogo_extpower_present(void)
-{
-	return 0;
-}
-#endif
-
-int extpower_is_present(void)
-{
-	/*
-	 * The charger will indicate VBUS presence if we're sourcing 5V,
-	 * so exclude such ports.
-	 */
-	int usb_c_extpower_present;
-
-	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
-		usb_c_extpower_present = 0;
-	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
-
-	return usb_c_extpower_present || kukui_pogo_extpower_present();
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-#if defined(BOARD_KUKUI) || defined(BOARD_KODAMA)
-/* fake interrupt function for kukui */
-void pogo_adc_interrupt(enum gpio_signal signal)
-{
-}
-#endif
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_ODL);
-
-#ifdef SECTION_IS_RW
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-#endif /* SECTION_IS_RW */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable gauge interrupt from max17055 */
-	gpio_enable_interrupt(GPIO_GAUGE_INT_ODL);
-
-	if (IS_ENABLED(BOARD_KRANE)) {
-		/*
-		 * Fix backlight led maximum current:
-		 * tolerance 120mA * 0.75 = 90mA.
-		 * (b/133655155)
-		 */
-		mt6370_backlight_set_dim(MT6370_BLDIM_DEFAULT * 3 / 4);
-	}
-
-	/* Enable pogo charging signal */
-	gpio_enable_interrupt(GPIO_POGO_VBUS_PRESENT);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_rev_init(void)
-{
-	/* Board revision specific configs. */
-
-	/*
-	 * It's a P1 pin BOOTBLOCK_MUX_OE, also a P2 pin BC12_DET_EN.
-	 * Keep this pin defaults to P1 setting since that eMMC enabled with
-	 * High-Z stat.
-	 */
-	if (IS_ENABLED(BOARD_KUKUI) && board_get_version() == 1)
-		gpio_set_flags(GPIO_BC12_DET_EN, GPIO_ODR_HIGH);
-
-	if (board_get_version() >= 2 && board_get_version() < 4) {
-		/* Display bias settings. */
-		mt6370_db_set_voltages(6000, 5800, 5800);
-
-		/*
-		 * Enable MT6370 DB_POSVOUT/DB_NEGVOUT (controlled by _EN pins).
-		 */
-		mt6370_db_external_control(1);
-	}
-
-	if (board_get_version() == 2) {
-		/* configure PI3USB9201 to USB Path ON Mode */
-		i2c_write8(I2C_PORT_BC12, BC12_I2C_ADDR_FLAGS,
-			   PI3USB9201_REG_CTRL_1,
-			   (PI3USB9201_USB_PATH_ON <<
-			    PI3USB9201_REG_CTRL_1_MODE_SHIFT));
-	}
-
-	if (board_get_version() < 5) {
-		gpio_set_flags(GPIO_USB_C0_DP_OE_L, GPIO_OUT_HIGH);
-		gpio_set_flags(GPIO_USB_C0_DP_POLARITY, GPIO_OUT_LOW);
-		usb_muxes[0].driver = &virtual_usb_mux_driver;
-		usb_muxes[0].hpd_update = &virtual_hpd_update;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
-
-void sensor_board_proc_double_tap(void)
-{
-	CPRINTS("Detect double tap");
-}
-
-/* Motion sensors */
-/* Mutexes */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	/*
-	 * TODO(b:139366662): calculates the actual coefficients and scaling
-	 * factors
-	 */
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.1),
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Matrix to rotate accelerometer into standard reference frame */
-#ifdef BOARD_KUKUI
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-#else
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-#endif /* BOARD_KUKUI */
-
-#ifdef CONFIG_MAG_BMI_BMM150
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t mag_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-#endif /* CONFIG_MAG_BMI_BMM150 */
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-		 /* For double tap detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = TAP_ODR,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-#ifdef CONFIG_MAG_BMI_BMM150
-	[LID_MAG] = {
-	 .name = "Lid Mag",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_MAG,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = BIT(11), /* 16LSB / uT, fixed */
-	 .rot_standard_ref = &mag_standard_ref,
-	 .min_frequency = BMM150_MAG_MIN_FREQ,
-	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
-#endif /* CONFIG_MAG_BMI_BMM150 */
-	[CLEAR_ALS] = {
-	 .name = "Clear Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_TCS3400,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &tcs3400_drv,
-	 .drv_data = &g_tcs3400_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	 .min_frequency = TCS3400_LIGHT_MIN_FREQ,
-	 .max_frequency = TCS3400_LIGHT_MAX_FREQ,
-	 .config = {
-		 /* Run ALS sensor in S0 */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-	[RGB_ALS] = {
-	.name = "RGB Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_TCS3400,
-	 .type = MOTIONSENSE_TYPE_LIGHT_RGB,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &tcs3400_rgb_drv,
-	 .drv_data = &g_tcs3400_rgb_data,
-	 /*.port = I2C_PORT_ALS,*/ /* Unused. RGB channels read by CLEAR_ALS. */
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	 .min_frequency = 0, /* 0 indicates we should not use sensor directly */
-	 .max_frequency = 0, /* 0 indicates we should not use sensor directly */
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/*
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-	/*
-	 * Though we have a more tolerant range (3.9V~13.4V), setting 4400 to
-	 * prevent from a bad charger crashed.
-	 *
-	 * TODO(b:131284131): mt6370 VBUS reading is not accurate currently.
-	 * Vendor will provide a workaround solution to fix the gap between ADC
-	 * reading and actual voltage.  After the workaround applied, we could
-	 * try to raise this value to 4600.  (when it says it read 4400, it is
-	 * actually close to 4600)
-	 */
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < 4400;
-}
-
-__override int board_charge_port_is_sink(int port)
-{
-	/* TODO(b:128386458): Check POGO_ADC_INT_L */
-	return 1;
-}
-
-__override int board_charge_port_is_connected(int port)
-{
-	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
-}
-
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
-{
-	r->meas.voltage_now = 3300;
-	r->meas.voltage_max = 3300;
-	r->meas.current_max = 1500;
-	r->meas.current_lim = 1500;
-	r->max_power = r->meas.voltage_now * r->meas.current_max;
-}
-
-__override int board_has_virtual_mux(void)
-{
-	return board_get_version() < 5;
-}
diff --git a/board/kukui/board.h b/board/kukui/board.h
deleted file mode 100644
index e771c9891d..0000000000
--- a/board/kukui/board.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#ifdef BOARD_KRANE
-#define VARIANT_KUKUI_BATTERY_MM8013
-#define VARIANT_KUKUI_POGO_KEYBOARD
-#else
-#define VARIANT_KUKUI_BATTERY_MAX17055
-#endif
-
-#define VARIANT_KUKUI_CHARGER_MT6370
-#define VARIANT_KUKUI_EC_STM32F098
-#define VARIANT_KUKUI_DP_MUX_GPIO
-#define VARIANT_KUKUI_TABLET_PWRBTN
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#define CONFIG_USB_MUX_IT5205
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Battery */
-#ifdef BOARD_KRANE
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
-#else
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
-#endif /* BOARD_KRANE */
-
-#ifdef BOARD_KRANE
-#define CONFIG_CHARGER_MT6370_BACKLIGHT
-#endif /* BOARD_KRANE */
-
-#ifdef BOARD_KUKUI
-/* kukui doesn't have BC12_DET_EN pin */
-#undef CONFIG_CHARGER_MT6370_BC12_GPIO
-#endif
-
-/* Motion Sensors */
-#ifdef SECTION_IS_RW
-#ifndef BOARD_KRANE
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_MAG_CALIBRATE
-#endif /* !BOARD_KRANE */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ALS
-
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#endif /* SECTION_IS_RW */
-
-/* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-#define I2C_PORT_ALS      1
-
-/* Route sbs host requests to virtual battery driver */
-#define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
-
-/* MKBP */
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
-
-#define PD_OPERATING_POWER_MW 15000
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_BATT_ID,
-	ADC_POGO_ADC_INT_L,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-#ifdef CONFIG_MAG_BMI_BMM150
-	LID_MAG,
-#endif /* CONFIG_MAG_BMI_BMM150 */
-	CLEAR_ALS,
-	RGB_ALS,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	CHARGE_PORT_POGO,
-#endif
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-void pogo_adc_interrupt(enum gpio_signal signal);
-int board_discharge_on_ac(int enable);
-
-/* Enable double tap detection */
-#define CONFIG_GESTURE_DETECTION
-#define CONFIG_GESTURE_HOST_DETECTION
-#define CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-#define CONFIG_GESTURE_TAP_FOR_HOST
-#define CONFIG_GESTURE_SAMPLING_INTERVAL_MS 5
-#define CONFIG_GESTURE_TAP_THRES_MG 100
-#define CONFIG_GESTURE_TAP_MAX_INTERSTICE_T 500
-#define CONFIG_GESTURE_TAP_SENSOR 0
-#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_GESTURE_TAP_SENSOR)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kukui/build.mk b/board/kukui/build.mk
deleted file mode 100644
index 694879cee6..0000000000
--- a/board/kukui/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=board.o led.o
diff --git a/board/kukui/ec.tasklist b/board/kukui/ec.tasklist
deleted file mode 100644
index 9ba564ce52..0000000000
--- a/board/kukui/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
-
diff --git a/board/kukui/gpio.inc b/board/kukui/gpio.inc
deleted file mode 100644
index 1f17a24bcd..0000000000
--- a/board/kukui/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,       PIN(B, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-GPIO_INT(VOLUME_DOWN_L,     PIN(B, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT(CHARGER_INT_ODL,   PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event)
-GPIO_INT_RW(SYNC_INT,       PIN(A, 8),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(HALL_INT_L,        PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(GAUGE_INT_ODL,     PIN(C, 9),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         gauge_interrupt)
-GPIO_INT(POGO_ADC_INT_L,    PIN(A, 6),  GPIO_INT_BOTH,
-         pogo_adc_interrupt)
-
-/* unused */
-GPIO(POGO_VBUS_PRESENT, PIN(A, 14), GPIO_INPUT)
-/* unused after board rev 5 */
-GPIO(USB_C0_DP_POLARITY,   PIN(C, 14), GPIO_INPUT)
-GPIO(USB_C0_DP_OE_L,       PIN(A, 5),  GPIO_INPUT)
-
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(C, 10), GPIO_ODR_HIGH)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-GPIO(MT6370_RST_L,         PIN(F, 0),  GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BATT_ID,              PIN(A, 7),  GPIO_ANALOG)
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(B, 12), GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP3300_POGO,     PIN(A, 13), GPIO_OUT_LOW)
-GPIO(EN_POGO_CHARGE_L,   PIN(B, 6),  GPIO_OUT_HIGH)
-GPIO(EN_USBC_CHARGE_L,   PIN(C, 7),  GPIO_OUT_LOW)
-GPIO(EN_PP5000_USBC,     PIN(D, 2),  GPIO_OUT_LOW)
-GPIO(BC12_DET_EN,        PIN(C, 4),  GPIO_OUT_LOW)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-#ifdef SECTION_IS_RO
-/* SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,        0)
-#endif
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
diff --git a/board/kukui/led.c b/board/kukui/led.c
deleted file mode 100644
index 59f7681754..0000000000
--- a/board/kukui/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Kukui board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "driver/charger/rt946x.h"
-#include "hooks.h"
-#include "led_common.h"
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static enum charge_state prv_chstate = PWR_STATE_INIT;
-
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_BLUE	MT6370_LED_ID3
-
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_BLUE	MT6370_MASK_RGB_ISNK3DIM_EN
-
-static void kukui_led_set_battery(void)
-{
-	enum charge_state chstate;
-	static uint8_t prv_r, prv_g, prv_b;
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	chstate = charge_get_state();
-
-	if (prv_chstate == chstate &&
-		chstate != PWR_STATE_DISCHARGE)
-		return;
-
-	prv_chstate = chstate;
-
-	switch (chstate) {
-	case PWR_STATE_CHARGE:
-		/* RGB(current, duty) = (4mA,1/32)*/
-		br[EC_LED_COLOR_BLUE] = 1;
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* display SoC 10% = real battery SoC 13%*/
-		if (charge_get_percent() <= 13)
-			br[EC_LED_COLOR_RED] = 1;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		br[EC_LED_COLOR_GREEN] = 1;
-		break;
-	case PWR_STATE_ERROR:
-		br[EC_LED_COLOR_RED] = 1;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		return;
-	}
-
-	if (prv_r == br[EC_LED_COLOR_RED] &&
-	    prv_g == br[EC_LED_COLOR_GREEN] &&
-	    prv_b == br[EC_LED_COLOR_BLUE])
-		return;
-
-	prv_r = br[EC_LED_COLOR_RED];
-	prv_g = br[EC_LED_COLOR_GREEN];
-	prv_b = br[EC_LED_COLOR_BLUE];
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return;
-
-	brightness_range[EC_LED_COLOR_RED] = MT6370_LED_BRIGHTNESS_MAX;
-	brightness_range[EC_LED_COLOR_GREEN] = MT6370_LED_BRIGHTNESS_MAX;
-	brightness_range[EC_LED_COLOR_BLUE] = MT6370_LED_BRIGHTNESS_MAX;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	uint8_t red, green, blue;
-
-	if (led_id != EC_LED_ID_BATTERY_LED)
-		return EC_ERROR_INVAL;
-
-	red = brightness[EC_LED_COLOR_RED];
-	green = brightness[EC_LED_COLOR_GREEN];
-	blue = brightness[EC_LED_COLOR_BLUE];
-
-	mt6370_led_set_brightness(LED_RED, red);
-	mt6370_led_set_brightness(LED_GREEN, green);
-	mt6370_led_set_brightness(LED_BLUE, blue);
-
-	/* Enables LED sink power if necessary. */
-	mt6370_led_set_color((red ? LED_MASK_RED : 0) |
-			     (blue ? LED_MASK_BLUE : 0) |
-			     (green ? LED_MASK_GREEN : 0));
-	return EC_SUCCESS;
-}
-
-/*
- * Reset prv_chstate so that led can be updated immediately once
- * auto-controlled.
- */
-static void led_reset_auto_control(void)
-{
-	prv_chstate = PWR_STATE_INIT;
-}
-
-static void krane_led_init(void)
-{
-	const enum mt6370_led_dim_mode dim = MT6370_LED_DIM_MODE_PWM;
-	const enum mt6370_led_pwm_freq freq = MT6370_LED_PWM_FREQ1000;
-	mt6370_led_set_color(0);
-	mt6370_led_set_dim_mode(LED_RED, dim);
-	mt6370_led_set_dim_mode(LED_GREEN, dim);
-	mt6370_led_set_dim_mode(LED_BLUE, dim);
-	mt6370_led_set_pwm_frequency(LED_RED, freq);
-	mt6370_led_set_pwm_frequency(LED_GREEN, freq);
-	mt6370_led_set_pwm_frequency(LED_BLUE, freq);
-	mt6370_led_set_pwm_dim_duty(LED_RED, 0);
-	mt6370_led_set_pwm_dim_duty(LED_GREEN, 0);
-	mt6370_led_set_pwm_dim_duty(LED_BLUE, 0);
-}
-DECLARE_HOOK(HOOK_INIT, krane_led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		kukui_led_set_battery();
-	else
-		led_reset_auto_control();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
-__override void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	uint8_t br[EC_LED_COLOR_COUNT] = { 0 };
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_reset_auto_control();
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		return;
-	}
-
-	if (state)
-		br[EC_LED_COLOR_GREEN] = 1;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-	led_set_brightness(EC_LED_ID_BATTERY_LED, br);
-}
diff --git a/board/kukui/vif_override.xml b/board/kukui/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/kukui/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/kukui_scp/board.c b/board/kukui_scp/board.c
deleted file mode 100644
index e5c4f0c760..0000000000
--- a/board/kukui_scp/board.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Kukui SCP configuration */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Build GPIO tables */
-#include "gpio_list.h"
-
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h
deleted file mode 100644
index 4847cdf939..0000000000
--- a/board/kukui_scp/board.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kukui SCP configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI)))
-
-#define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */
-#undef  CONFIG_LID_SWITCH
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_MKBP_EVENT
-/* Sent MKBP event via IPI. */
-#define CONFIG_MKBP_USE_CUSTOM
-#define CONFIG_FPU
-#define CONFIG_PRESERVE_LOGS
-
-#define CONFIG_HOSTCMD_ALIGNED
-
-/*
- * RW only, no flash
- * +-------------------- 0x0
- * | ROM vectortable, .text, .rodata, .data LMA
- * +-------------------- 0x10000
- * | RAM .bss, .data
- * +-------------------- 0x7BDB0
- * | IPI shared buffer with AP (288 + 8) * 2
- * +-------------------- 0x7C000
- * | 8KB I-CACHE
- * +-------------------- 0x7E000
- * | 8KB D-CACHE
- * +-------------------- 0x80000
- */
-#define ICACHE_BASE 0x7C000
-#define CONFIG_ROM_BASE 0x0
-#define CONFIG_RAM_BASE 0x58000
-#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE)
-#define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE
-#define CONFIG_DATA_RAM_SIZE (ICACHE_BASE - CONFIG_RAM_BASE)
-#define CONFIG_RO_MEM_OFF 0
-
-/* Access DRAM through cached access */
-#define CONFIG_DRAM_BASE 0x10000000
-/* Shared memory address in AP physical address space. */
-#define CONFIG_DRAM_BASE_LOAD 0x50000000
-#define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
-
-/* IPI configs */
-#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(ICACHE_BASE -                                                         \
-	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
-#define CONFIG_IPI
-#define CONFIG_RPMSG_NAME_SERVICE
-
-#define CONFIG_LTO
-
-/* IPI ID should be in sync across kernel and EC. */
-#define IPI_SCP_INIT 0
-#define IPI_VDEC_H264 1
-#define IPI_VDEC_VP8 2
-#define IPI_VDEC_VP9 3
-#define IPI_VENC_H264 4
-#define IPI_VENC_VP8 5
-#define IPI_MDP_INIT 6
-#define IPI_MDP_DEINIT 7
-#define IPI_MDP_FRAME 8
-#define IPI_DIP 9
-#define IPI_ISP_CMD 10
-#define IPI_ISP_FRAME 11
-#define IPI_FD_CMD 12
-#define IPI_HOST_COMMAND 13
-#define IPI_COUNT 14
-
-#define IPI_NS_SERVICE 0xFF
-
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-#undef  CONFIG_UART_CONSOLE
-/*
- * CONFIG_UART_CONSOLE
- *   0 - SCP UART0
- *   1 - SCP UART1
- *   2 - share with AP UART0
- */
-#define CONFIG_UART_CONSOLE 0
-
-/* We let AP setup the correct pinmux. */
-#undef    UART0_PINMUX_11_12
-#undef    UART0_PINMUX_110_112
-
-/* Track AP power state */
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Debugging features */
-#define CONFIG_DEBUG_EXCEPTIONS
-#define CONFIG_DEBUG_STACK_OVERFLOW
-#define CONFIG_CMD_GPIO_EXTENDED
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kukui_scp/build.mk b/board/kukui_scp/build.mk
deleted file mode 100644
index 19355b5af5..0000000000
--- a/board/kukui_scp/build.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-CHIP:=mt_scp
-CHIP_VARIANT:=mt8183
-
-board-y=board.o
-board-$(HAS_TASK_VDEC_SERVICE)+=vdec.o
-board-$(HAS_TASK_VENC_SERVICE)+=venc.o
-
-# ISP P1
-board-$(HAS_TASK_ISP_SERVICE)+=isp_p1_srv.o
-# FD
-board-$(HAS_TASK_FD_SERVICE)+=fd.o
-
-# ISP P2
-board-$(HAS_TASK_DIP_SERVICE)+=isp_p2_srv.o
-# MDP3
-board-$(HAS_TASK_MDP_SERVICE)+=mdp_ipi_message.o
diff --git a/board/kukui_scp/ec.tasklist b/board/kukui_scp/ec.tasklist
deleted file mode 100644
index 935d409b00..0000000000
--- a/board/kukui_scp/ec.tasklist
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-/* We don't need uart_task when using scp uart (uart0, uart1). */
-#if CONFIG_UART_CONSOLE == 2
-#define UART_TASK TASK_ALWAYS(APUART, uart_task, NULL, LARGER_TASK_STACK_SIZE)
-#else
-#define UART_TASK
-#endif
-
-#define S3_SUSPEND_TASK_LIST \
-	TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(FD_SERVICE, fd_service_task, NULL, 760) \
-	TASK_ALWAYS(DIP_SERVICE, dip_service_task, NULL, 6400) \
-	TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 1800) \
-	TASK_ALWAYS(ISP_SERVICE, isp_service_task, NULL, 880)
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	UART_TASK \
-	S3_SUSPEND_TASK_LIST \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/kukui_scp/fd.c b/board/kukui_scp/fd.c
deleted file mode 100644
index 237f15ca94..0000000000
--- a/board/kukui_scp/fd.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "fd.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_fd_consumer;
-static void event_fd_written(struct consumer const *consumer, size_t count);
-
-static struct queue const fd_queue = QUEUE_DIRECT(4, struct fd_msg,
-						  null_producer,
-						  event_fd_consumer);
-static struct consumer const event_fd_consumer = {
-	.queue = &fd_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_fd_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-// Jerry TODO implement private part and remove this
-#ifndef HAVE_PRIVATE_MT8183
-void fd_ipi_msg_handler(void *data) {}
-#endif
-
-static void event_fd_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_FD_SERVICE);
-}
-
-static void fd_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct fd_msg rsv_msg;
-
-	if (!len)
-		return;
-
-	rsv_msg.type = IPI_FD_CMD;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&fd_queue, &rsv_msg))
-		CPRINTS("Could not send fd %d to the queue.", rsv_msg.type);
-}
-DECLARE_IPI(IPI_FD_CMD, fd_ipi_handler, 0);
-
-/* This function renames from fd_service_entry. */
-void fd_service_task(void *u)
-{
-	struct fd_msg rsv_msg;
-	size_t size;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&fd_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			fd_ipi_msg_handler(rsv_msg.msg);
-	}
-}
diff --git a/board/kukui_scp/fd.h b/board/kukui_scp/fd.h
deleted file mode 100644
index 3f70387400..0000000000
--- a/board/kukui_scp/fd.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_FD_H
-#define __CROS_EC_SCP_FD_H
-
-#include "compile_time_macros.h"
-#include "queue.h"
-#include "registers.h"
-
-enum fd_msg_type {
-	FD_IPI_MSG,
-	FD_MAX,
-};
-
-enum fd_cmd_type {
-	FD_CMD_INIT,
-	FD_CMD_ENQ,
-	FD_CMD_EXIT,
-};
-
-typedef void (*fd_msg_handler)(void *msg);
-
-struct fd_msg {
-	enum fd_msg_type type;
-	unsigned char msg[110];
-};
-BUILD_ASSERT(member_size(struct fd_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void fd_ipi_msg_handler(void *data);
-
-#endif /* __CROS_EC_SCP_FD_H */
diff --git a/board/kukui_scp/gpio.inc b/board/kukui_scp/gpio.inc
deleted file mode 100644
index b186904aad..0000000000
--- a/board/kukui_scp/gpio.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-/*
- * GPIOn = port * 32 + bit
- *
- * EINT ALT function:
- *   GPIO[0-3]: Alt3
- *   GPIO[4-7]: Alt6
- * UART0 ALT function:
- *   GPIO[110]: Alt3 TP_URXD1_AO
- *   GPIO[112]: Alt3 TP_UTXD1_AO
- */
-ALTERNATE(PIN_MASK(0, 0x00000070), 6, MODULE_GPIO, 0) /* GPIO 5,6,7 as SCP EINT */
-#if CONFIG_UART_CONSOLE == 0
-#ifdef UART0_PINMUX_110_112
-/* Use SCP debug UART. */
-ALTERNATE(PIN_MASK(3, 0x00014000), 3, MODULE_UART, 0) /* GPIO 110,112 as UART0 */
-#endif /* UART0_PINMUX_110_112 */
-#ifdef UART0_PINMUX_11_12
-/* Use H1(AP->H1) rework UART. */
-ALTERNATE(PIN_MASK(0, 0x00001800), 1, MODULE_UART, 0) /* GPIO 11,12 as UART0 */
-#endif /* UART0_PINMUX_11_12 */
-#endif /* CONFIG_UART_CONSOLE == 0 */
diff --git a/board/kukui_scp/isp_p1_srv.c b/board/kukui_scp/isp_p1_srv.c
deleted file mode 100644
index 5c2ae7c2e9..0000000000
--- a/board/kukui_scp/isp_p1_srv.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "isp_p1_srv.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_isp_consumer;
-static void event_isp_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_isp_queue = QUEUE_DIRECT(8,
-	struct isp_msg, null_producer, event_isp_consumer);
-
-static struct consumer const event_isp_consumer = {
-	.queue = &event_isp_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_isp_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT8183
-void isp_msg_handler(void *data) {}
-#endif
-
-static void event_isp_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_ISP_SERVICE);
-}
-
-static void isp_ipi_msg_handler(int id, void *data, uint32_t len)
-{
-	struct isp_msg rsv_msg;
-
-	if (!len)
-		return;
-
-	rsv_msg.id = id;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_isp_queue, &rsv_msg))
-		CPRINTS("Could not send isp %d to the queue", id);
-}
-DECLARE_IPI(IPI_ISP_CMD, isp_ipi_msg_handler, 0);
-DECLARE_IPI(IPI_ISP_FRAME, isp_ipi_msg_handler, 0);
-
-/* This function renames from isp_service_entry. */
-void isp_service_task(void *u)
-{
-	struct isp_msg rsv_msg;
-	size_t size;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&event_isp_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			isp_msg_handler(&rsv_msg);
-	}
-}
diff --git a/board/kukui_scp/isp_p1_srv.h b/board/kukui_scp/isp_p1_srv.h
deleted file mode 100644
index ba6fa7d110..0000000000
--- a/board/kukui_scp/isp_p1_srv.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISP_P1_SRV_H
-#define __CROS_EC_ISP_P1_SRV_H
-
-#include "ipi_chip.h"
-
-struct isp_msg {
-	unsigned char id;
-	unsigned char msg[140];
-};
-
-BUILD_ASSERT(member_size(struct isp_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void isp_msg_handler(void *data);
-
-#endif /* __CROS_EC_ISP_P1_SRV_H */
diff --git a/board/kukui_scp/isp_p2_srv.c b/board/kukui_scp/isp_p2_srv.c
deleted file mode 100755
index dba330c6a8..0000000000
--- a/board/kukui_scp/isp_p2_srv.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "isp_p2_srv.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_dip_consumer;
-static void event_dip_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_dip_queue = QUEUE_DIRECT(4,
-	struct dip_msg_service, null_producer, event_dip_consumer);
-
-static struct consumer const event_dip_consumer = {
-	.queue = &event_dip_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_dip_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT8183
-void dip_msg_handler(void *data) {}
-#endif
-
-static void event_dip_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_DIP_SERVICE);
-}
-
-static void dip_scp_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct dip_msg_service rsv_msg;
-
-	if (!len)
-		return;
-	rsv_msg.id = id;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_dip_queue, &rsv_msg))
-		CPRINTS("Could not send dip %d to the queue.", id);
-}
-DECLARE_IPI(IPI_DIP, dip_scp_ipi_handler, 0);
-
-/* This function renames from dip_service_entry. */
-void dip_service_task(void *u)
-{
-	struct dip_msg_service rsv_msg;
-	size_t size;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&event_dip_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			dip_msg_handler(&rsv_msg);
-	}
-}
diff --git a/board/kukui_scp/isp_p2_srv.h b/board/kukui_scp/isp_p2_srv.h
deleted file mode 100644
index 70fb0673de..0000000000
--- a/board/kukui_scp/isp_p2_srv.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ISP_P2_SRV_H
-#define __CROS_EC_ISP_P2_SRV_H
-
-#include "ipi_chip.h"
-
-struct dip_msg_service {
-	unsigned char id;
-	unsigned char msg[288];
-};
-
-BUILD_ASSERT(member_size(struct dip_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void dip_msg_handler(void *data);
-
-#endif /* __CROS_EC_ISP_P2_SRV_H */
diff --git a/board/kukui_scp/mdp_ipi_message.c b/board/kukui_scp/mdp_ipi_message.c
deleted file mode 100644
index eca40b741b..0000000000
--- a/board/kukui_scp/mdp_ipi_message.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "ipi_chip.h"
-#include "mdp_ipi_message.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_mdp_consumer;
-static void event_mdp_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_mdp_queue = QUEUE_DIRECT(4,
-	struct mdp_msg_service, null_producer, event_mdp_consumer);
-static struct consumer const event_mdp_consumer = {
-	.queue = &event_mdp_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_mdp_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT8183
-void mdp_common_init(void) {}
-void mdp_ipi_task_handler(void *pvParameters) {}
-#endif
-
-static void event_mdp_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_MDP_SERVICE);
-}
-
-static void mdp_ipi_handler(int id, void *data, unsigned int len)
-{
-	struct mdp_msg_service cmd;
-
-	cmd.id = id;
-	memcpy(cmd.msg, data, MIN(len, sizeof(cmd.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_mdp_queue, &cmd))
-		CPRINTS("Could not send mdp id: %d to the queue.", id);
-}
-DECLARE_IPI(IPI_MDP_INIT, mdp_ipi_handler, 0);
-DECLARE_IPI(IPI_MDP_FRAME, mdp_ipi_handler, 0);
-DECLARE_IPI(IPI_MDP_DEINIT, mdp_ipi_handler, 0);
-
-/* This function renames from mdp_service_entry. */
-void mdp_service_task(void *u)
-{
-	struct mdp_msg_service rsv_msg;
-	size_t size;
-
-	mdp_common_init();
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&event_mdp_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else
-			mdp_ipi_task_handler(&rsv_msg);
-	}
-}
diff --git a/board/kukui_scp/mdp_ipi_message.h b/board/kukui_scp/mdp_ipi_message.h
deleted file mode 100644
index bcedb58504..0000000000
--- a/board/kukui_scp/mdp_ipi_message.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _MDP_IPI_MESSAGE_H
-#define _MDP_IPI_MESSAGE_H
-
-struct mdp_msg_service {
-	int id;
-	unsigned char msg[20];
-};
-
-BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-void mdp_common_init(void);
-void mdp_ipi_task_handler(void *pvParameters);
-
-#endif  // _MDP_IPI_MESSAGE_H
diff --git a/board/kukui_scp/update_scp b/board/kukui_scp/update_scp
deleted file mode 100755
index 846095a7f9..0000000000
--- a/board/kukui_scp/update_scp
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-usage() {
-  echo "Usage: $0 [IP] [bin/elf]" >&2
-  echo >&2
-  echo "Deploy kukui_scp image to DUT, and restart the remoteproc driver" >&2
-  exit 2
-}
-
-if [[ -z "$1" ]]; then
-   usage
-fi
-
-KUKUI_IP="$1"
-INFILE="build/kukui_scp/ec.bin"
-
-case "$2" in
-bin)
-  ;;
-elf|"") # Default
-  # ec.obj is an elf file that has the right memory layout to be loaded
-  # from the AP/kernel.
-  INFILE="build/kukui_scp/ec.obj"
-  ;;
-*)
-  usage
-  ;;
-esac
-
-scp "$INFILE" "$KUKUI_IP":/lib/firmware/scp.img
-
-ssh "$KUKUI_IP" sh -x -c "'
-    sync;
-    echo stop > /sys/class/remoteproc/remoteproc0/state;
-    echo start > /sys/class/remoteproc/remoteproc0/state'"
diff --git a/board/kukui_scp/vdec.c b/board/kukui_scp/vdec.c
deleted file mode 100644
index eb4f1f8fa1..0000000000
--- a/board/kukui_scp/vdec.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "vdec.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_vdec_consumer;
-static void event_vdec_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_vdec_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_consumer);
-static struct consumer const event_vdec_consumer = {
-	.queue = &event_vdec_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_vdec_written,
-	}),
-};
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT8183
-void vdec_h264_service_init(void) {}
-void vdec_h264_msg_handler(void *data) {}
-#endif
-
-static vdec_msg_handler mtk_vdec_msg_handle[VDEC_MAX];
-
-static void event_vdec_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_VDEC_SERVICE);
-}
-
-static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct vdec_msg rsv_msg;
-
-	if (!len)
-		return;
-
-	rsv_msg.type = VDEC_H264;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_vdec_queue, &rsv_msg))
-		CPRINTS("Could not send vdec %d to the queue.", rsv_msg.type);
-}
-DECLARE_IPI(IPI_VDEC_H264, vdec_h264_ipi_handler, 0);
-
-/* This function renames from vdec_service_entry. */
-void vdec_service_task(void *u)
-{
-	struct vdec_msg rsv_msg;
-	size_t size;
-
-	vdec_h264_service_init();
-	mtk_vdec_msg_handle[VDEC_H264] = vdec_h264_msg_handler;
-
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&event_vdec_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else if (mtk_vdec_msg_handle[rsv_msg.type])
-			vdec_h264_msg_handler(rsv_msg.msg);
-		else
-			CPRINTS("vdec handler %d not exists.", rsv_msg.type);
-	}
-}
diff --git a/board/kukui_scp/vdec.h b/board/kukui_scp/vdec.h
deleted file mode 100644
index 9cfb877e12..0000000000
--- a/board/kukui_scp/vdec.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_VDEC_H
-#define __CROS_EC_SCP_VDEC_H
-
-#include "compile_time_macros.h"
-#include "queue.h"
-#include "registers.h"
-
-enum vdec_type {
-	VDEC_H264,
-	VDEC_VP8,
-	VDEC_VP9,
-	VDEC_MAX,
-};
-
-typedef void (*vdec_msg_handler)(void *msg);
-
-struct vdec_msg {
-	enum vdec_type type;
-	unsigned char msg[48];
-};
-
-BUILD_ASSERT(member_size(struct vdec_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void vdec_h264_service_init(void);
-void vdec_h264_msg_handler(void *data);
-
-#endif /* __CROS_EC_SCP_VDEC_H */
diff --git a/board/kukui_scp/venc.c b/board/kukui_scp/venc.c
deleted file mode 100644
index c7e19d120c..0000000000
--- a/board/kukui_scp/venc.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "ipi_chip.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "venc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-/* Forwad declaration. */
-static struct consumer const event_venc_consumer;
-static void event_venc_written(struct consumer const *consumer, size_t count);
-
-static struct queue const event_venc_queue = QUEUE_DIRECT(8,
-	struct venc_msg, null_producer, event_venc_consumer);
-static struct consumer const event_venc_consumer = {
-	.queue = &event_venc_queue,
-	.ops = &((struct consumer_ops const) {
-		.written = event_venc_written,
-	}),
-};
-
-static venc_msg_handler mtk_venc_msg_handle[VENC_MAX];
-
-/* Stub functions only provided by private overlays. */
-#ifndef HAVE_PRIVATE_MT8183
-void venc_h264_msg_handler(void *data) {}
-#endif
-
-static void event_venc_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_VENC_SERVICE);
-}
-
-static void venc_h264_ipi_handler(int id, void *data, uint32_t len)
-{
-	struct venc_msg rsv_msg;
-
-	if (!len)
-		return;
-	rsv_msg.type = VENC_H264;
-	memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
-
-	/*
-	 * If there is no other IPI handler touch this queue, we don't need to
-	 * interrupt_disable() or task_disable_irq().
-	 */
-	if (!queue_add_unit(&event_venc_queue, &rsv_msg))
-		CPRINTS("Could not send venc %d to the queue.", rsv_msg.type);
-}
-DECLARE_IPI(IPI_VENC_H264, venc_h264_ipi_handler, 0);
-
-/* This function renames from venc_service_entry. */
-void venc_service_task(void *u)
-{
-	struct venc_msg rsv_msg;
-	size_t size;
-
-	mtk_venc_msg_handle[VENC_H264] = venc_h264_msg_handler;
-	while (1) {
-		/*
-		 * Queue unit is added in IPI handler, which is in ISR context.
-		 * Disable IRQ to prevent a clobbered queue.
-		 */
-		ipi_disable_irq(SCP_IRQ_IPC0);
-		size = queue_remove_unit(&event_venc_queue, &rsv_msg);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-
-		if (!size)
-			task_wait_event(-1);
-		else if (mtk_venc_msg_handle[rsv_msg.type])
-			venc_h264_msg_handler(rsv_msg.msg);
-		else
-			CPRINTS("venc handler %d not exists.", rsv_msg.type);
-	}
-}
diff --git a/board/kukui_scp/venc.h b/board/kukui_scp/venc.h
deleted file mode 100644
index 7046633046..0000000000
--- a/board/kukui_scp/venc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SCP_VENC_H
-#define __CROS_EC_SCP_VENC_H
-
-#include "compile_time_macros.h"
-#include "queue.h"
-#include "registers.h"
-
-enum venc_type {
-	VENC_H264,
-	VENC_MAX,
-};
-
-typedef void (*venc_msg_handler)(void *msg);
-
-struct venc_msg {
-	enum venc_type type;
-	unsigned char msg[288];
-};
-
-BUILD_ASSERT(member_size(struct venc_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Functions provided by private overlay. */
-void venc_h264_msg_handler(void *data);
-
-#endif /* __CROS_EC_SCP_VENC_H */
diff --git a/board/lalala/battery.c b/board/lalala/battery.c
deleted file mode 100644
index 326ac93a6b..0000000000
--- a/board/lalala/battery.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "gpio.h"
-#include "util.h"
-
-/*
- * Battery info for lalala battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-		/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/lalala/board.c b/board/lalala/board.c
deleted file mode 100644
index 3065c5b9bd..0000000000
--- a/board/lalala/board.c
+++ /dev/null
@@ -1,851 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/retimer/ps8802.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-static uint8_t new_adc_key_state;
-
-static void ps8762_chaddr_deferred(void);
-DECLARE_DEFERRED(ps8762_chaddr_deferred);
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-	GPIO_EN_USB_A1_VBUS,
-};
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config lalala_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &lalala_keybd;
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void ps8762_chaddr_deferred(void)
-{
-	/* Switch PS8762 I2C Address to 0x50*/
-	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
-		CPRINTS("Switch PS8762 address to 0x50 success");
-	else
-		CPRINTS("Switch PS8762 address to 0x50 failed");
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
-
-	if (!enable)
-		return;
-	/*
-	 * Port C1 the PP3300_USB_C1  assert, delay 15ms
-	 * colud be accessed PS8762 by I2C.
-	 */
-	hook_call_deferred(&ps8762_chaddr_deferred_data, 15 * MSEC);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* ICM426 private data */
-static struct icm_drv_data_t g_icm426xx_data;
-/* KX022 private data */
-static struct kionix_accel_data g_kx022_data;
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
-	check_c0_line();
-	check_c1_line();
-
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	if (get_cbi_fw_config_tablet_mode()) {
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			cprints(CC_SYSTEM, "BASE GYRO is ICM426XX");
-		} else
-			cprints(CC_SYSTEM, "BASE GYRO is BMI160");
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			cprints(CC_SYSTEM, "LID_ACCEL is KX022");
-		} else
-			cprints(CC_SYSTEM, "LID_ACCEL is BMA253");
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize THERMAL */
-	setup_thermal();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
-	}
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-int adc_to_physical_value(enum gpio_signal gpio)
-{
-	if (gpio == GPIO_VOLUME_UP_L)
-		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
-	else if (gpio == GPIO_VOLUME_DOWN_L)
-		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
-
-	CPRINTS("Not a volume up or down key");
-	return 0;
-}
-
-int button_is_adc_detected(enum gpio_signal gpio)
-{
-	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
-}
-
-static void adc_vol_key_press_check(void)
-{
-	int volt = adc_read_channel(ADC_SUB_ANALOG);
-	static uint8_t old_adc_key_state;
-	uint8_t adc_key_state_change;
-
-	if (volt > 2400 && volt < 2490) {
-		/* volume-up is pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK;
-	} else if (volt > 2600 && volt < 2690) {
-		/* volume-down is pressed */
-		new_adc_key_state = ADC_VOL_DOWN_MASK;
-	} else if (volt < 2290) {
-		/* both volumn-up and volume-down are pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
-	} else if (volt > 2700) {
-		/* both volumn-up and volume-down are released */
-		new_adc_key_state = 0;
-	}
-	if (new_adc_key_state != old_adc_key_state) {
-		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
-		if (adc_key_state_change && ADC_VOL_UP_MASK)
-			button_interrupt(GPIO_VOLUME_UP_L);
-		if (adc_key_state_change && ADC_VOL_DOWN_MASK)
-			button_interrupt(GPIO_VOLUME_DOWN_L);
-
-		old_adc_key_state = new_adc_key_state;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/lalala/board.h b/board/lalala/board.h
deleted file mode 100644
index 1cbb6bf7e2..0000000000
--- a/board/lalala/board.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lalala board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KEEBY_EC_NPCX797FC
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* GPIO for C1 interrupts, for baseboard use */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* Keyboard */
-
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_PWM_KBLIGHT
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_PS8802
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
-
-/******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Volume Button feature */
-#define CONFIG_ADC_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_TYPE_COUNT,
-};
-
-int board_is_sourcing_vbus(int port);
-void motion_interrupt(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lalala/build.mk b/board/lalala/build.mk
deleted file mode 100644
index b012d8d502..0000000000
--- a/board/lalala/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=keeby
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/lalala/cbi_ssfc.c b/board/lalala/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/lalala/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/lalala/cbi_ssfc.h b/board/lalala/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/lalala/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lalala/ec.tasklist b/board/lalala/ec.tasklist
deleted file mode 100644
index d4fb416bce..0000000000
--- a/board/lalala/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/lalala/gpio.inc b/board/lalala/gpio.inc
deleted file mode 100644
index 3d81cd089d..0000000000
--- a/board/lalala/gpio.inc
+++ /dev/null
@@ -1,145 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_USB_C1_INT_ODL,	 PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt)
-
-/* Button interrupts */
-GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
-
-/* Extra Sub-board I/O pins */
-
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
-GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
-GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-/*
- * Lalala doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/lalala/led.c b/board/lalala/led.c
deleted file mode 100644
index cfe6f9eb6a..0000000000
--- a/board/lalala/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for lalala
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/lalala/usb_pd_policy.c b/board/lalala/usb_pd_policy.c
deleted file mode 100644
index fd9018a3f0..0000000000
--- a/board/lalala/usb_pd_policy.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/lalala/vif_override.xml b/board/lalala/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lalala/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lantis/battery.c b/board/lantis/battery.c
deleted file mode 100644
index 94a9128e37..0000000000
--- a/board/lantis/battery.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all lantis battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo CosMX Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/lantis/board.c b/board/lantis/board.c
deleted file mode 100644
index a64d8fa17a..0000000000
--- a/board/lantis/board.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lantis board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_8042.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-uint32_t board_version;
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-__override void board_process_pd_alert(int port)
-{
-	/*
-	 * PD_INT task will process this alert, and that task is only needed on
-	 * C1.
-	 */
-	if (port != 1)
-		return;
-
-	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return;
-
-	sm5803_handle_interrupt(port);
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE)
-		gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	else
-		button_interrupt(s);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad and no screenlock key */
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &keybd1;
-}
-
-void board_init(void)
-{
-	int on;
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-	} else {
-		/* Select AUX option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 1);
-	}
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/* Store board version for use in determining charge limits */
-	cbi_get_board_version(&board_version);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	if (board_get_charger_chip_count() > 1) {
-		/* Charger on the sub-board will be a push-pull GPIO */
-		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-static void board_suspend(void)
-{
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-
-	if (board_get_charger_chip_count() > 1) {
-		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CHARGER_NUM;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	charger_set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 20;
-
-	*ki = 3;
-	*ki_div = 125;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/lantis/board.h b/board/lantis/board.h
deleted file mode 100644
index df209187ac..0000000000
--- a/board/lantis/board.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lantis board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-#undef GPIO_VOLUME_UP_L
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_PWM_KBLIGHT
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lantis/build.mk b/board/lantis/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/lantis/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/lantis/cbi_ssfc.c b/board/lantis/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/lantis/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/lantis/cbi_ssfc.h b/board/lantis/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/lantis/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lantis/ec.tasklist b/board/lantis/ec.tasklist
deleted file mode 100644
index 2edf48ee05..0000000000
--- a/board/lantis/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/lantis/gpio.inc b/board/lantis/gpio.inc
deleted file mode 100644
index c24e20d5ec..0000000000
--- a/board/lantis/gpio.inc
+++ /dev/null
@@ -1,146 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* LED */
-GPIO(BAT_LED_AMBER_C0,	 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_C0,	 PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(BAT_LED_AMBER_C1,	 PIN(F, 1), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_C1,	 PIN(F, 0), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/lantis/led.c b/board/lantis/led.c
deleted file mode 100644
index c4868de740..0000000000
--- a/board/lantis/led.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lantis specific LED settings. */
-
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
-
-static int led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_BAT_LED_AMBER_C1 :
-				 GPIO_BAT_LED_AMBER_C0);
-	white_led = (port == RIGHT_PORT ? GPIO_BAT_LED_WHITE_C1 :
-				 GPIO_BAT_LED_WHITE_C0);
-
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		rv = led_set_color_battery(RIGHT_PORT, color);
-		break;
-	case EC_LED_ID_LEFT_LED:
-		rv = led_set_color_battery(LEFT_PORT, color);
-		break;
-	case EC_LED_ID_POWER_LED:
-		rv = led_set_color_power(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LED for clamshell SKU, which doesn't have power
-	 * LED, blinking battery white LED to indicate system suspend without
-	 * charging.
-	 */
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(RIGHT_PORT, power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(LEFT_PORT, power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			set_active_port_color(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(RIGHT_PORT,
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			set_active_port_color(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/lantis/usb_pd_policy.c b/board/lantis/usb_pd_policy.c
deleted file mode 100644
index 7046e25d6c..0000000000
--- a/board/lantis/usb_pd_policy.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	prev_en = charger_is_sourcing_otg_power(port);
-
-	/* Disable Vbus */
-	charger_enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable sinking */
-	rv = sm5803_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	charger_enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return sm5803_is_vbus_present(port);
-}
diff --git a/board/lantis/vif_override.xml b/board/lantis/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lantis/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lazor/battery.c b/board/lazor/battery.c
deleted file mode 100644
index 6cad716e2c..0000000000
--- a/board/lazor/battery.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all lazor battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* AP16L5J */
-	[BATTERY_AP16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* AP16L5J with PN version */
-	[BATTERY_AP16L5J_009] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00205009",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* AP16L8J */
-	[BATTERY_AP16L8J] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0020G010",
-			.device_name = "AP16L8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8700,
-			.voltage_normal         = 7500, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP16L5J;
diff --git a/board/lazor/board.c b/board/lazor/board.c
deleted file mode 100644
index 1118f3a845..0000000000
--- a/board/lazor/board.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lazor board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/ln9310.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "sku.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
-	 * as it still uses the legacy location (KSO_01/KSI_00).
-	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-	{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref_bmi160 = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref_bma255 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref_kx022 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref_bma255,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref_bmi160,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref_bmi160,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref_kx022,
-	.default_range = 2, /* g, enough for laptop. */
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_standard_ref_icm426xx,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm426xx,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int base_accelgyro_config;
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_accelgyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	/* Check lid accel chip */
-	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
-		BMA2x2_CHIP_ID_ADDR, &val);
-	if (ret)
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-
-	CPRINTS("Lid Accel: %s", ret ? "KX022" : "BMA255");
-
-	/* Check base accelgyro chip */
-	ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
-	if (val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-	}
-
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_clamshell()) {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* The sensors are not stuffed; don't allow lines to float */
-		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	} else {
-		board_detect_motionsensor();
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable interrupt for the base accel sensor */
-		gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
-	     HOOK_PRIO_INIT_I2C + 2);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-__override uint32_t board_get_sku_id(void)
-{
-	static int sku_id = -1;
-
-	if (sku_id == -1) {
-		int bits[3];
-
-		bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
-		bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
-		bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
-		sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
-	}
-
-	return (uint32_t)sku_id;
-}
diff --git a/board/lazor/board.h b/board/lazor/board.h
deleted file mode 100644
index d045c13cb5..0000000000
--- a/board/lazor/board.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lazor board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Switchcap */
-#define CONFIG_LN9310
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* ICM426XX Base accel/gyro */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* KX022 lid accel */
-#define CONFIG_ACCEL_KX022
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-#define GPIO_SWITCHCAP_PG_INT_L GPIO_DA9313_GPIO0
-#define GPIO_SWITCHCAP_ON_L GPIO_SWITCHCAP_ON
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-#include "sku.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_AP16L5J,
-	BATTERY_AP16L5J_009,
-	BATTERY_AP16L8J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_TYPE_COUNT,
-};
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lazor/build.mk b/board/lazor/build.mk
deleted file mode 100644
index 8cf8679e35..0000000000
--- a/board/lazor/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=hibernate.o
-board-y+=led.o
-board-y+=sku.o
-board-y+=switchcap.o
-board-y+=usbc_config.o
diff --git a/board/lazor/ec.tasklist b/board/lazor/ec.tasklist
deleted file mode 100644
index 2b55c26c20..0000000000
--- a/board/lazor/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/lazor/gpio.inc b/board/lazor/gpio.inc
deleted file mode 100644
index b5c15b3729..0000000000
--- a/board/lazor/gpio.inc
+++ /dev/null
@@ -1,188 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/* Switchcap
- *
- * For DA9313 SKUs, it is GPIO0 of DA9313. The GPIO0 is configured as PVC_PG.
- * For LN9310 SKUs, it is the interrupt line of LN9310.
- */
-GPIO_INT(DA9313_GPIO0,      PIN(E, 2), GPIO_INT_FALLING, ln9310_interrupt)
-
-/*
- * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
- * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
-/* TODO(waihong): Remove it. The VBOB switch is for backup. */
-GPIO(VBOB_EN,               PIN(D, 3), GPIO_OUT_LOW)   /* Enable VBOB */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN,     PIN(7, 5), GPIO_OUT_HIGH)  /* H: CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_B_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(C, 0))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(6, 0))
-UNUSED(PIN(7, 2))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/lazor/hibernate.c b/board/lazor/hibernate.c
deleted file mode 100644
index 1187348e31..0000000000
--- a/board/lazor/hibernate.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "sku.h"
-#include "system.h"
-#include "usbc_ppc.h"
-
-void board_hibernate(void)
-{
-	int i;
-
-	if (!board_is_clamshell()) {
-		/*
-		 * Sensors are unpowered in hibernate. Apply PD to the
-		 * interrupt lines such that they don't float.
-		 */
-		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * Board rev 5+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 5)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
diff --git a/board/lazor/led.c b/board/lazor/led.c
deleted file mode 100644
index f9c91c1c6a..0000000000
--- a/board/lazor/led.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_AMBER;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: Amber 1 sec, off 3 sec */
-			period = (1 + 3) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_AMBER;
-			else
-				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* Discharging in S5: off */
-			color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* Discharging in S0: Blue on */
-			color = LED_BLUE;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber 1 sec, off 1 sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_AMBER;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: Blue on */
-		color = LED_BLUE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
-			color = LED_BLUE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_BLUE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/lazor/sku.c b/board/lazor/sku.c
deleted file mode 100644
index 815295d9f5..0000000000
--- a/board/lazor/sku.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "driver/ln9310.h"
-#include "tcpm/ps8xxx_public.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "sku.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static uint8_t sku_id;
-
-enum board_model {
-	LAZOR,
-	LIMOZEEN,
-	UNKNOWN,
-};
-
-static const char *const model_name[] = {
-	"LAZOR",
-	"LIMOZEEN",
-	"UNKNOWN",
-};
-
-static enum board_model get_model(void)
-{
-	if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3)
-		return LAZOR;
-	if (sku_id == 4 || sku_id == 5 || sku_id == 6)
-		return LIMOZEEN;
-	return UNKNOWN;
-}
-
-/* Read SKU ID from GPIO and initialize variables for board variants */
-static void sku_init(void)
-{
-	sku_id = system_get_sku_id();
-	CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]);
-}
-DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_INIT_I2C + 1);
-
-enum battery_cell_type board_get_battery_cell_type(void)
-{
-	switch (get_model()) {
-	case LIMOZEEN:
-		return BATTERY_CELL_TYPE_3S;
-	default:
-		return BATTERY_CELL_TYPE_UNKNOWN;
-	}
-}
-
-int board_is_clamshell(void)
-{
-	return get_model() == LIMOZEEN;
-}
-
-__override uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/*
-	 * Lazor (SKU_ID: 0, 1, 2, 3) rev 3+ changes TCPC from PS8751 to
-	 * PS8805.
-	 *
-	 * Limozeen (SKU_ID: 4, 5, 6) all-rev uses PS8805.
-	 */
-	if (get_model() == LAZOR && system_get_board_version() < 3)
-		return PS8751_PRODUCT_ID;
-
-	return PS8805_PRODUCT_ID;
-}
-
-int board_has_da9313(void)
-{
-	return get_model() == LAZOR;
-}
-
-int board_has_buck_ic(void)
-{
-	return get_model() == LIMOZEEN && system_get_board_version() >= 8;
-}
-
-int board_has_ln9310(void)
-{
-	return get_model() == LIMOZEEN && system_get_board_version() < 8;
-}
diff --git a/board/lazor/sku.h b/board/lazor/sku.h
deleted file mode 100644
index 96eaf2bb92..0000000000
--- a/board/lazor/sku.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lazor board-specific SKU configuration */
-
-#ifndef __CROS_EC_SKU_H
-#define __CROS_EC_SKU_H
-
-int board_get_version(void);
-int board_is_clamshell(void);
-int board_has_da9313(void);
-int board_has_ln9310(void);
-int board_has_buck_ic(void);
-
-#endif /* __CROS_EC_SKU_H */
diff --git a/board/lazor/switchcap.c b/board/lazor/switchcap.c
deleted file mode 100644
index 16f4a54c79..0000000000
--- a/board/lazor/switchcap.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "driver/ln9310.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "power/qcom.h"
-#include "system.h"
-#include "sku.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-/* LN9310 switchcap */
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
-};
-
-static void switchcap_init(void)
-{
-	if (board_has_da9313()) {
-		CPRINTS("Use switchcap: DA9313");
-
-		/*
-		 * When the chip in power down mode, it outputs high-Z.
-		 * Set pull-down to avoid floating.
-		 */
-		gpio_set_flags(GPIO_DA9313_GPIO0, GPIO_INPUT | GPIO_PULL_DOWN);
-
-		/*
-		 * Configure DA9313 enable, push-pull output. Don't set the
-		 * level here; otherwise, it will override its value and
-		 * shutdown the switchcap when sysjump to RW.
-		 */
-		gpio_set_flags(GPIO_SWITCHCAP_ON, GPIO_OUTPUT);
-	} else if (board_has_ln9310()) {
-		CPRINTS("Use switchcap: LN9310");
-
-		/* Configure and enable interrupt for LN9310 */
-		gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
-		gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
-
-		/*
-		 * Configure LN9310 enable, open-drain output. Don't set the
-		 * level here; otherwise, it will override its value and
-		 * shutdown the switchcap when sysjump to RW.
-		 *
-		 * Note that the gpio.inc configures it GPIO_OUT_LOW. When
-		 * sysjump to RW, will output push-pull a short period of
-		 * time. As it outputs LOW, should be fine.
-		 *
-		 * This GPIO changes like:
-		 * (1) EC boots from RO -> high-Z
-		 * (2) GPIO init according to gpio.inc -> push-pull LOW
-		 * (3) This function configures it -> open-drain HIGH
-		 * (4) Power sequence turns on the switchcap -> open-drain LOW
-		 * (5) EC sysjumps to RW
-		 * (6) GPIO init according to gpio.inc -> push-pull LOW
-		 * (7) This function configures it -> open-drain LOW
-		 */
-		gpio_set_flags(GPIO_SWITCHCAP_ON_L,
-			       GPIO_OUTPUT | GPIO_OPEN_DRAIN);
-
-		/* Only configure the switchcap if not sysjump */
-		if (!system_jumped_late()) {
-			/*
-			 * Deassert the enable pin (set it HIGH), so the
-			 * switchcap won't be enabled after the switchcap is
-			 * configured from standby mode to switching mode.
-			 */
-			gpio_set_level(GPIO_SWITCHCAP_ON_L, 1);
-			ln9310_init();
-		}
-	} else if (board_has_buck_ic()) {
-		CPRINTS("Use Buck IC");
-	} else {
-		CPRINTS("ERROR: No switchcap solution");
-	}
-}
-DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	if (board_has_da9313()) {
-		gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-	} else if (board_has_ln9310()) {
-		gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
-		ln9310_software_enable(enable);
-	} else if (board_has_buck_ic()) {
-		gpio_set_level(GPIO_VBOB_EN, enable);
-	}
-}
-
-int board_is_switchcap_enabled(void)
-{
-	if (board_has_da9313())
-		return gpio_get_level(GPIO_SWITCHCAP_ON);
-	else if (board_has_ln9310())
-		return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
-
-	/* Board has buck ic*/
-	return gpio_get_level(GPIO_VBOB_EN);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	if (board_has_da9313())
-		return gpio_get_level(GPIO_DA9313_GPIO0);
-	else if (board_has_ln9310())
-		return ln9310_power_good();
-
-	/* Board has buck ic no way to check POWER GOOD */
-	return 1;
-}
diff --git a/board/lazor/usbc_config.c b/board/lazor/usbc_config.c
deleted file mode 100644
index f8c9662136..0000000000
--- a/board/lazor/usbc_config.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lazor board-specific USB-C configuration */
-
-#include "battery_fuel_gauge.h"
-#include "bc12/pi3usb9201_public.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "config.h"
-#include "driver/ln9310.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ppc/sn5s330_public.h"
-#include "system.h"
-#include "tcpm/ps8xxx_public.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_config.h"
-#include "usb_mux.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-__override int board_get_default_battery_type(void)
-{
-	/*
-	 * A 2S battery is set as default. If the board is configured to use
-	 * a 3S battery, according to its SKU_ID, return a 3S battery as
-	 * default. It helps to configure the charger to output a correct
-	 * voltage in case the battery is not attached.
-	 */
-	if (board_get_battery_cell_type() == BATTERY_CELL_TYPE_3S)
-		return BATTERY_LGC_AP18C8K;
-
-	return DEFAULT_BATTERY_TYPE;
-}
-
-/* Initialize board USC-C things */
-static void board_init_usbc(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/board/lazor/usbc_config.h b/board/lazor/usbc_config.h
deleted file mode 100644
index 9c1d8d1e74..0000000000
--- a/board/lazor/usbc_config.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* lazor board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#include "gpio.h"
-
-void tcpc_alert_event(enum gpio_signal signal);
-void usb0_evt(enum gpio_signal signal);
-void usb1_evt(enum gpio_signal signal);
-void usba_oc_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void board_connect_c0_sbu(enum gpio_signal s);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/lazor/vif_override.xml b/board/lazor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lazor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/liara/analyzestack.yaml b/board/liara/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/liara/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/liara/battery.c b/board/liara/battery.c
deleted file mode 100644
index bf244125b0..0000000000
--- a/board/liara/battery.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-
-/*
- * Battery info for all Liara battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Panasonic AP15O5L battery information from the Grunt reference
-	 * design.
-	 */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			},
-			.imbalance_mv = battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-	/*
-	 * Sunwoda 2018 Battery Information for Liara.
-	 * Gauge IC: TI BQ40Z697A
-	 */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda 2018",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = battery_bq4050_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-	/*
-	 * Simplo 2018 Battery Information for Liara
-	 * Gauge IC: TI BQ40Z695A
-	 */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP2018",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-			.imbalance_mv = battery_bq4050_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 247,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-	/*
-	 * LGC 2018 Battery Information for Liara
-	 * Gauge IC: Renesas RAJ240047A20DNP
-	 */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC2018",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0010,
-				.disconnect_val = 0x0,
-			},
-			.imbalance_mv = battery_default_imbalance_mv,
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/liara/board.c b/board/liara/board.c
deleted file mode 100644
index 4f8b552d1f..0000000000
--- a/board/liara/board.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Liara board-specific configuration */
-
-#include "button.h"
-#include "driver/led/lm3630a.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED1_WHITE] = {
-		.channel = 0,
-		.flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW
-			  | PWM_CONFIG_DSLEEP),
-		.freq = 100,
-	},
-	[PWM_CH_LED2_AMBER] =   {
-		.channel = 2,
-		.flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW
-			  | PWM_CONFIG_DSLEEP),
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_kblight_init(void)
-{
-	/*
-	 * Enable keyboard backlight. This needs to be done here because
-	 * the chip doesn't have power until PP3300_S0 comes up.
-	 */
-	gpio_set_level(GPIO_KB_BL_EN, 1);
-	lm3630a_poweron();
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
diff --git a/board/liara/board.h b/board/liara/board.h
deleted file mode 100644
index ae4494115b..0000000000
--- a/board/liara/board.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Liara board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3429
-#define VARIANT_GRUNT_NO_SENSORS
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-#define CONFIG_MKBP_USE_HOST_EVENT
-
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
-
-/* Power and battery LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_PWM_CHARGE_STATE_ONLY
-#define CONFIG_CMD_LEDTEST
-
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
-
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER
-
-#define CONFIG_LED_PWM_COUNT 1
-
-#define I2C_PORT_KBLIGHT NPCX_I2C_PORT5_0
-
-/* KB backlight driver */
-#define CONFIG_LED_DRIVER_LM3630A
-
-#define CONFIG_BATTERY_BQ4050
-#define CONFIG_BATTERY_MEASURE_IMBALANCE
-
-#ifndef __ASSEMBLER__
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_LED1_WHITE,
-	PWM_CH_LED2_AMBER,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_PANASONIC,
-	BATTERY_SUNWODA,
-	BATTERY_SIMPLO,
-	BATTERY_LGC,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/liara/build.mk b/board/liara/build.mk
deleted file mode 100644
index c808e65aed..0000000000
--- a/board/liara/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/liara/ec.tasklist b/board/liara/ec.tasklist
deleted file mode 100644
index b562761311..0000000000
--- a/board/liara/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/liara/gpio.inc b/board/liara/gpio.inc
deleted file mode 100644
index 343c50f503..0000000000
--- a/board/liara/gpio.inc
+++ /dev/null
@@ -1,118 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(E, 4), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(KB_BL_EN,			PIN(F, 2), GPIO_OUT_LOW)			/* Enable KB Backlight */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
-										   EC_I2C_KB_BL_SCL */
-GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
-										   EC_I2C_KB_BL_SDA */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-GPIO(PCH_SLP_S0_L,		PIN(A, 4), GPIO_INPUT)
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(EN_USB_C0_TCPC_PWR,	PIN(6, 0), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST_L,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH| GPIO_PULL_UP)		/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)					/* KB Backlight */
-ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) 					/* LED 1 & 2 */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)					/* GPIO00 = AC_PRESENT,
-										   GPIO01 = POWER_BUTTON_L,
-										   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 = LID_OPEN */
diff --git a/board/liara/led.c b/board/liara/led.c
deleted file mode 100644
index 371c08ce40..0000000000
--- a/board/liara/led.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * We only have a blue and an amber LED, so setting any other colour results in
- * both LEDs being off.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* White, Amber */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = { 100,   0 },
-	[EC_LED_COLOR_AMBER]  = {   0, 100 },
-};
-
-/* One logical LED with amber and blue channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1_WHITE,
-		.ch1 = PWM_CH_LED2_AMBER,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/liara/vif_override.xml b/board/liara/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/liara/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lick/battery.c b/board/lick/battery.c
deleted file mode 100644
index fa746a8c9f..0000000000
--- a/board/lick/battery.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all lick battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 5B10Q13163 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC 5B10Q13162  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 181,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/lick/board.c b/board/lick/board.c
deleted file mode 100644
index 4b5608b7b0..0000000000
--- a/board/lick/board.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lick board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "util.h"
-#include "battery_smart.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		/* We only use 2g because its resolution is only 8-bits */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &standard_rot_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	return sku_id != 255 && sku_id != 1;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return board_is_convertible();
-}
-
-/* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
-/* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
-/* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_BATTERY_MODE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	rv = sb_read(SB_OPTIONALMFG_FUNCTION2, &val);
-	if (rv)
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_OPTIONALMFG_FUNCTION2, val);
-}
-
-/* Called on AP S3/S0ix -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Normal charge current */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3/S0ix transition */
-static void board_chipset_suspend(void)
-{
-	/* Quick charge current */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
diff --git a/board/lick/board.h b/board/lick/board.h
deleted file mode 100644
index f377662111..0000000000
--- a/board/lick/board.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lick board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_LED_COMMON
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lick/build.mk b/board/lick/build.mk
deleted file mode 100644
index 137e208b53..0000000000
--- a/board/lick/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/lick/ec.tasklist b/board/lick/ec.tasklist
deleted file mode 100644
index 6eac78a042..0000000000
--- a/board/lick/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/lick/gpio.inc b/board/lick/gpio.inc
deleted file mode 100644
index ad6773a211..0000000000
--- a/board/lick/gpio.inc
+++ /dev/null
@@ -1,199 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,  PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,    PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	    PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_RED_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_GREEN_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(PWR_LED_WHITE_L,	 PIN(D, 7), GPIO_OUT_HIGH)	/* LED_3_L */
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,           PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,           PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,           PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Camera */
-GPIO(EC_GPIO_03,	 PIN(0, 3), GPIO_INPUT)		/* TP only */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	 PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL,	PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Unused pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_GPIO97,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)         /* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)         /* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/lick/led.c b/board/lick/led.c
deleted file mode 100644
index a55a3e989e..0000000000
--- a/board/lick/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Lick
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/lick/vif_override.xml b/board/lick/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lick/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lindar/battery.c b/board/lindar/battery.c
deleted file mode 100644
index 503b2f11c0..0000000000
--- a/board/lindar/battery.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			/*
-			 * voltage min value and precharge current value are
-			 * specified by LGC directly and not shown in the SPEC.
-			 */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L19D4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 333,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
-
-__override bool board_battery_is_initialized(void)
-{
-	bool batt_initialization_state;
-	int batt_status;
-
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
-	return batt_initialization_state;
-}
-
diff --git a/board/lindar/board.c b/board/lindar/board.c
deleted file mode 100644
index 030940cfb1..0000000000
--- a/board/lindar/board.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* lindar board-specific configuration */
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Malefor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_NO_A,
-};
-
-static void board_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * TODO: b/154447182 - Malefor will control power LED and battery LED
-	 * independently, and keep the max brightness of power LED and battery
-	 * LED as 50%.
-	 */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_i2c_port_powered(int port)
-{
-	if (port != I2C_PORT_LIGHTBAR)
-		return 1;
-
-	/*
-	 * Lightbar rails are off in S5/G3
-	 * Refer CL-2739008.
-	 */
-	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
-}
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_cfg_has_tabletmode();
-}
-
-/* Enable or disable input devices, based on tablet mode or chipset state */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-/******************************************************************************/
-/* Sensors */
-/* Lid and base Sensor mutex */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid and base accel private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (100 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(100),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-	},
-	.temp_fan_off = C_TO_K(30),
-	.temp_fan_max = C_TO_K(60),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 100c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(100),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-	},
-	.temp_fan_off = C_TO_K(30),
-	.temp_fan_max = C_TO_K(60),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "lightbar",
-		.port = I2C_PORT_LIGHTBAR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C3_LEDBAR_SCL,
-		.sda = GPIO_EC_I2C3_LEDBAR_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void kb_backlight_enable(void)
-{
-	if (ec_cfg_has_keyboard_backlight() == 1)
-		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	if (ec_cfg_has_keyboard_backlight() == 1)
-		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0
-		 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = NULL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	if (get_board_id() <= 1) {
-		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags =
-			TUSB422_I2C_ADDR_FLAGS;
-		tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv;
-		tcpc_config[USBC_PORT_C0].flags = 0;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/lindar/board.h b/board/lindar/board.h
deleted file mode 100644
index d89d33582e..0000000000
--- a/board/lindar/board.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_MUTE_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_LIGHTBAR	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lindar/build.mk b/board/lindar/build.mk
deleted file mode 100644
index 43b40c644c..0000000000
--- a/board/lindar/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/lindar/ec.tasklist b/board/lindar/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/lindar/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/lindar/gpio.inc b/board/lindar/gpio.inc
deleted file mode 100644
index 246b83cd3f..0000000000
--- a/board/lindar/gpio.inc
+++ /dev/null
@@ -1,179 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,		PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(EC_ACCEL_INT_L,		PIN(8, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO_INT(TABLET_MODE_L,		PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_MUTE_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* HW_ID PIN */
-GPIO(HW_ID,		PIN(D, 4), GPIO_INPUT)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-
-
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknoledgement */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_LEDBAR_SCL,     PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_LEDBAR_SDA,     PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)     /* Keyboard backlight */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
-/* Unused signals */
-GPIO(UNUSED_GPIO60,    PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,    PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,    PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,    PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF3,    PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/lindar/ktd20xx.h b/board/lindar/ktd20xx.h
deleted file mode 100644
index ad93ee3de8..0000000000
--- a/board/lindar/ktd20xx.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Public header for Kinetic 36-Channel RGB LED Drivers with I2C control,
- * including KTD2061/58/59/60.
- */
-
-#ifndef __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H
-#define __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H
-
-/*
- * KTD20xx Register Definition
- *
- * Reg0x00: ID Data Register
- *   skip...
- * Reg0x01: MONITOR Status Register
- *   skip...
- * Reg0x02: CONTROL Configuration Register
- *   BIT7:6 is EN_MODE[1:0]
- *     00 = global off, 01 = Night mode,
- *     10 = Normal mode, 11 = reset as default
- *   BIT5 is BrightExtendTM Enable
- *     0 = disable/1 = enable
- *   BIT4:3 is CoolExtendTM Temperature Setting
- *     00 = 135°C rising, 01 = 120°C
- *     10 = 105°C, 11 = 90°C
- *   BIT2:0 is Fade Rate Exponential Time-Constant Setting
- *     000 = 31ms, 001 = 63ms, 010 = 125ms, 011 = 250ms
- *     100 = 500ms, 101 = 1s, 110 = 2s, 111 = 4s
- *
- * Reg0x03: IRED0 Color Configuration Register
- *   IRED_SET0[7:0] Red Current Setting 0
- *     0000 0000 = 0μA
- *     0000 0001 = 125μA
- *     ...
- *     0010 1000 = 5mA
- *     ...
- *     1100 0000 = 24mA
- *     1100 0001 = 24mA (reads back as 1100 0000)
- *     ...
- *     1111 1111 = 24mA (reads back as 1100 0000)
- * Reg0x04: IGRN0 Color Configuration Register
- *   IGRN_SET0[7:0] Green Current Setting 0
- * Reg0x05: IBLU0 Color Configuration Register
- *   IBLU_SET0[7:0] Blue Current Setting 0
- * Reg0x06: IRED1 Color Configuration Register
- *   IRED_SET1[7:0] Red Current Setting 1
- * Reg0x07: IGRN1 Color Configuration Register
- *   IGRN_SET1[7:0] Green Current Setting 1
- * Reg0x08: IBLU1 Color Configuration Register
- *   IBLU_SET1[7:0] Blue Current Setting 1
- *
- * Reg0x09: ISELA12 Selection Configuration Register
- *   BIT7 is ENA1, Enable RGB with anode connected to LEDA1 pin
- *     0 = use 0μA for these LEDs (includes fade to 0μA)
- *     1 = use the settings selected by RGBA1_SEL[2:0]
- *   BIT6:4 is RGBA1_SEL[2:0]
- *     Current Selection for RGB with anode connected to LEDA1 pin
- *     0XX = I LEDA3 selects IRED_SET0[7:0]
- *     1XX = I LEDA3 selects IRED_SET1[7:0]
- *     X0X = I LEDA2 selects IGRN_SET0[7:0]
- *     X1X = I LEDA2 selects IGRN_SET1[7:0]
- *     XX0 = I LEDA4 selects IBLU_SET0[7:0]
- *     XX1 = I LEDA4 selects IBLU_SET1[7:0]
- *   BIT3 IS ENA2
- *     0 = use 0μA for these LEDs (includes fade to 0μA)
- *     1 = use the settings selected by RGBA2_SEL[2:0]
- *   BIT2:0 is RGBA2_SEL[2:0]
- *     Current Selection for RGB with anode connected to LEDA2 pin
- *     0XX = I LEDA4 selects IRED_SET0[7:0]
- *     1XX = I LEDA4 selects IRED_SET1[7:0]
- *     X0X = I LEDA3 selects IGRN_SET0[7:0]
- *     X1X = I LEDA3 selects IGRN_SET1[7:0]
- *     XX0 = I LEDA1 selects IBLU_SET0[7:0]
- *     XX1 = I LEDA1 selects IBLU_SET1[7:0]
- * Reg0x0A: ISELA34 Selection Configuration Register
- *   BIT7 is ENA3, Enable RGB with anode connected to LEDA3 pin
- *     0 = use 0μA for these LEDs (includes fade to 0μA)
- *     1 = use the settings selected by RGBA3_SEL[2:0]
- *   BIT6:4 is RGBA3_SEL[2:0]
- *     Current Selection for RGB with anode connected to LEDA3 pin
- *     0XX = I LEDA1 selects IRED_SET0[7:0]
- *     1XX = I LEDA1 selects IRED_SET1[7:0]
- *     X0X = I LEDA4 selects IGRN_SET0[7:0]
- *     X1X = I LEDA4 selects IGRN_SET1[7:0]
- *     XX0 = I LEDA2 selects IBLU_SET0[7:0]
- *     XX1 = I LEDA2 selects IBLU_SET1[7:0]
- *   BIT3 IS ENA4
- *     0 = use 0μA for these LEDs (includes fade to 0μA)
- *     1 = use the settings selected by RGBA4_SEL[2:0]
- *   BIT2:0 is RGBA4_SEL[2:0]
- *     Current Selection for RGB with anode connected to LEDA4 pin
- *     0XX = I LEDA2 selects IRED_SET0[7:0]
- *     1XX = I LEDA2 selects IRED_SET1[7:0]
- *     X0X = I LEDA1 selects IGRN_SET0[7:0]
- *     X1X = I LEDA1 selects IGRN_SET1[7:0]
- *     XX0 = I LEDA3 selects IBLU_SET0[7:0]
- *     XX1 = I LEDA3 selects IBLU_SET1[7:0]
- * Reg0x0B: ISELB12 Selection Configuration Register
- *     BIT7 is ENB1, Enable RGB with anode connected to LEDB1 pin
- *     0 = use 0μA for these LEDs (includes fade to 0μA)
- *     1 = use the settings selected by RGB1_SEL[2:0]
- *   BIT6:4 is RGBB1_SEL[2:0]
- *     Current Selection for RGB with anode connected to LEDB1 pin
- *     0XX = I LEDB3 selects IRED_SET0[7:0]
- *     1XX = I LEDB3 selects IRED_SET1[7:0]
- *     X0X = I LEDB2 selects IGRN_SET0[7:0]
- *     X1X = I LEDB2 selects IGRN_SET1[7:0]
- *     XX0 = I LEDB4 selects IBLU_SET0[7:0]
- *     XX1 = I LEDB4 selects IBLU_SET1[7:0]
- *   BIT3 IS ENB2
- *     ...
- * Reg0x0C: ISELB34 Selection Configuration Register
- *   ...
- * Reg0x0D: ISELC12 Selection Configuration Register
- *   ...
- * Reg0x0E: ISELC34 Selection Configuration Register
- *   ...
- */
-
-enum ktd20xx_register {
-	KTD20XX_ID_DATA     = 0x00,
-	KTD20XX_STATUS_REG  = 0x01,
-	KTD20XX_CTRL_CFG    = 0x02,
-	KTD20XX_IRED_SET0   = 0x03,
-	KTD20XX_IGRN_SET0   = 0x04,
-	KTD20XX_IBLU_SET0   = 0x05,
-	KTD20XX_IRED_SET1   = 0x06,
-	KTD20XX_IGRN_SET1   = 0x07,
-	KTD20XX_IBLU_SET1   = 0x08,
-	KTD20XX_ISEL_A12    = 0x09,
-	KTD20XX_ISEL_A34    = 0x0A,
-	KTD20XX_ISEL_B12    = 0x0B,
-	KTD20XX_ISEL_B34    = 0x0C,
-	KTD20XX_ISEL_C12    = 0x0D,
-	KTD20XX_ISEL_C34    = 0x0E,
-	KTD20XX_TOTOAL_REG
-};
-
-#endif /* __CROS_EC_DRIVER_RGB_LED_DRIVER_KTD20XX_PUBLIC_H */
diff --git a/board/lindar/led.c b/board/lindar/led.c
deleted file mode 100644
index 6d602d5c4e..0000000000
--- a/board/lindar/led.c
+++ /dev/null
@@ -1,793 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Malefor
- */
-
-#include "cbi_ssfc.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "ktd20xx.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "lid_switch.h"
-#include "stdbool.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-static const uint16_t ktd2061_i2c_addr = 0x68;
-static void controller_write(uint8_t reg, uint8_t val)
-{
-	uint8_t buf[2];
-
-	buf[0] = reg;
-	buf[1] = val;
-
-	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr,
-			buf, 2, 0, 0,
-			I2C_XFER_SINGLE);
-}
-
-enum lightbar_states {
-	LB_STATE_OFF,
-	LB_STATE_LID_CLOSE,
-	LB_STATE_SLEEP_AC_ONLY,
-	LB_STATE_SLEEP_AC_BAT_LOW,
-	LB_STATE_SLEEP_AC_BAT_LV1,
-	LB_STATE_SLEEP_AC_BAT_LV2,
-	LB_STATE_SLEEP_AC_BAT_LV3,
-	LB_STATE_SLEEP_AC_BAT_LV4,
-	LB_STATE_SLEEP_BAT_LOW,
-	LB_STATE_SLEEP_BAT_ONLY,
-	LB_STATE_S0_AC_ONLY,
-	LB_STATE_S0_BAT_LOW,
-	LB_STATE_S0_BAT_LV1,
-	LB_STATE_S0_BAT_LV2,
-	LB_STATE_S0_BAT_LV3,
-	LB_STATE_S0_BAT_LV4,
-	LB_NUM_STATES
-};
-
-/*
- * All lightbar states should have one phase defined,
- * and an additional phase can be defined for blinking
- */
-enum lightbar_phase {
-	LIGHTBAR_PHASE_0 = 0,
-	LIGHTBAR_PHASE_1 = 1,
-	LIGHTBAR_NUM_PHASES
-};
-
-enum ec_lightbar_colors {
-	BAR_RESET,
-	BAR_OFF,
-	BAR_COLOR_ORG_20_PERCENT,
-	BAR_COLOR_GRN_40_PERCENT,
-	BAR_COLOR_GRN_60_PERCENT,
-	BAR_COLOR_GRN_80_PERCENT,
-	BAR_COLOR_GRN_FULL,
-	BAR_COLOR_ORG_FULL,
-	LIGHTBAR_COLOR_TOTAL
-};
-
-struct lightbar_descriptor {
-	enum ec_lightbar_colors color;
-	uint8_t ticks;
-};
-
-#define BAR_INFINITE      UINT8_MAX
-#define LIGHTBAR_ONE_SEC  (1000 / HOOK_TICK_INTERVAL_MS)
-#define LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP (3 * LIGHTBAR_ONE_SEC)
-int lightbar_resume_tick;
-
-const struct lightbar_descriptor
-	lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = {
-	[LB_STATE_OFF]              = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_LID_CLOSE]        = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_ONLY]    = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LOW] = {{BAR_COLOR_ORG_20_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV1] = {{BAR_COLOR_GRN_40_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV2] = {{BAR_COLOR_GRN_60_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV3] = {{BAR_COLOR_GRN_80_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV4] = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} },
-	[LB_STATE_SLEEP_BAT_LOW]    = {{BAR_OFF, 5 * LIGHTBAR_ONE_SEC},
-				{BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC} },
-	[LB_STATE_SLEEP_BAT_ONLY]   = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_S0_AC_ONLY]       = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LOW]       = {{BAR_COLOR_ORG_20_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV1]       = {{BAR_COLOR_GRN_40_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV2]       = {{BAR_COLOR_GRN_60_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV3]       = {{BAR_COLOR_GRN_80_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV4]       = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} },
-};
-
-#define DISABLE_LIGHTBAR         0x00
-#define ENABLE_LIGHTBAR          0x80
-#define I_OFF                    0x00
-#define GRN_I_ON                 0x1E
-#define ORG_I_ON                 0x28
-#define SEL_OFF                  0x00
-#define SEL_1ST_LED              BIT(7)
-#define SEL_2ND_LED              BIT(3)
-#define SEL_BOTH                 (SEL_1ST_LED | SEL_2ND_LED)
-#define SKU_ID_NONE              0x00
-#define SKU_ID_INVALID           0x01
-#define LB_SUPPORTED_SKUID_LOWER 458700
-#define LB_SUPPORTED_SKUID_UPPER 458800
-
-static bool lightbar_is_supported(void)
-{
-	static uint32_t skuid = SKU_ID_NONE;
-	bool result;
-
-	/* lindar add SSFC tag to cbi image from "board_id = 3". */
-	if (get_board_id() >= 3) {
-		if (get_cbi_ssfc_lightbar() == SSFC_LIGHTBAR_NONE)
-			return false;
-		return true;
-	}
-
-	if (skuid == SKU_ID_NONE) {
-		if (cbi_get_sku_id(&skuid)) {
-			CPRINTS("Cannot get skuid for lightbar supported");
-			skuid = SKU_ID_INVALID;
-		}
-	}
-
-	/*
-	 * If board_id = 1 or 2, it needs to check sku_id to know
-	 * if system support lightbar or not.
-	 */
-	if (skuid >= LB_SUPPORTED_SKUID_LOWER &&
-		skuid <= LB_SUPPORTED_SKUID_UPPER)
-		result = true;
-	else
-		result = false;
-
-	return result;
-}
-
-/*
- * lightbar_enter_s0ix_s3:
- * This flag is used to know if system ever enter S0ix/S3.
- * Lightbar V9 SPEC define lightbar resuming behavior, "S0ix/S3 -> S0",
- * but not include "G3/S5/S4 -> S0". "G3/S5/S4 -> S0" need to keep off.
- */
-static bool lightbar_enter_s0ix_s3;
-
-/*
- * lightbar_auto_control:
- * We need some command for testing lightbar in factory.
- * So, create this flag to stop regular action in lightbar_update().
- *
- * lightbar_demo_state:
- * It's used for testing lightbar via executing command under
- * console.
- */
-static bool lightbar_auto_control;
-static enum lightbar_states lightbar_demo_state;
-
-static void lightbar_set_auto_control(bool state)
-{
-	lightbar_auto_control = state;
-}
-
-static bool lightbar_is_auto_control(void)
-{
-	return lightbar_auto_control;
-}
-
-static void lightbar_set_demo_state(enum lightbar_states tmp_state)
-{
-	if (tmp_state >= LB_NUM_STATES || tmp_state < LB_STATE_OFF) {
-		lightbar_demo_state = LB_NUM_STATES;
-		lightbar_resume_tick = 0;
-	} else {
-		lightbar_demo_state = tmp_state;
-
-		if (lightbar_demo_state >= LB_STATE_S0_AC_ONLY)
-			lightbar_resume_tick =
-				LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP;
-	}
-	ccprintf("lightbar_demo_state = %d; lightbar_resume_tick %d.\n",
-			lightbar_demo_state,
-			lightbar_resume_tick);
-}
-
-static enum lightbar_states lightbar_get_demo_state(void)
-{
-	/*
-	 * Once tick count to zero, it needs to return LB_STATE_OFF to
-	 * simulate lightbar off.
-	 */
-	if ((lightbar_demo_state != LB_NUM_STATES) &&
-		(lightbar_demo_state >= LB_STATE_S0_AC_ONLY) &&
-		(lightbar_resume_tick == 0))
-		return LB_STATE_OFF;
-
-	return lightbar_demo_state;
-}
-
-static bool lightbar_is_enabled(void)
-{
-	if (!lightbar_is_supported())
-		return false;
-
-	/*
-	 * Lightbar's I2C is powered by PP3300_A, and its power will be turn
-	 * when system enter S4/S5. It may get I2C error if EC keep polling
-	 * lightbar. We should stop it when EC doesn't turn on PP330_A.
-	 */
-	if (!board_is_i2c_port_powered(I2C_PORT_LIGHTBAR))
-		return false;
-
-	return true;
-}
-
-/*
- * From "board_id = 3", HW change lightbar circuit, and it only support
- * two colors, orange (amber) and green. It connects KTD20xx's red-channel
- * green color led, and green-channel to orange color led.
- * Blue-channel is unused.
- *
- * The configuration format of lightbar_xx_led_cfg's is as below.
- * ID_DAT, STATUS_REG, CTRL_CFG
- * IRED_SET0, IGRN_SET0, IBLU_SET0, IRED_SET1, IGRN_SET1, IBLU_SET1
- * ISEL_A12, ISEL_A34, ISEL_B12, ISEL_B34, ISEL_C12, ISEL_C34
- */
-const uint8_t lightbar_10_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
-	[BAR_RESET] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_OFF] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_ORG_20_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_40_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_60_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_80_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF
-	},
-	[BAR_COLOR_ORG_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF
-	}
-};
-
-const uint8_t lightbar_12_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
-	[BAR_RESET] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_OFF] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_ORG_20_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_40_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_60_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_80_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED
-	},
-	[BAR_COLOR_GRN_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH
-	},
-	[BAR_COLOR_ORG_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH
-	}
-};
-
-/*
- * lightbar_ctrl is a pointer to 2-dimension lightbar configuration. It's used
- * to base on DUT type to load different cfg.
- * Default is lightbar_10_led_cfg.
- */
-const uint8_t (*lightbar_ctrl)[KTD20XX_TOTOAL_REG] = lightbar_10_led_cfg;
-
-static void lightbar_set_color(enum ec_lightbar_colors color)
-{
-	enum ktd20xx_register i;
-
-	if (color >= LIGHTBAR_COLOR_TOTAL) {
-		CPRINTS("Lightbar Error! Incorrect lightbard color %d", color);
-		color = BAR_RESET;
-	}
-
-	i2c_lock(I2C_PORT_LIGHTBAR, 1);
-	for (i = KTD20XX_IRED_SET0; i <= KTD20XX_ISEL_C34; i++)
-		controller_write(i, lightbar_ctrl[color][i]);
-
-	controller_write(KTD20XX_CTRL_CFG,
-					lightbar_ctrl[color][KTD20XX_CTRL_CFG]);
-
-	i2c_lock(I2C_PORT_LIGHTBAR, 0);
-}
-
-static void lightbar_init(void)
-{
-	if (!lightbar_is_enabled())
-		return;
-
-	if (get_cbi_ssfc_lightbar() == SSFC_LIGHTBAR_12_LED)
-		lightbar_ctrl = lightbar_12_led_cfg;
-	else
-		lightbar_ctrl = lightbar_10_led_cfg;
-
-	/* Clear this flag if system doesn't enter S0ix/S3 */
-	lightbar_enter_s0ix_s3 = false;
-	lightbar_resume_tick = 0;
-
-	lightbar_set_color(BAR_RESET);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, lightbar_init, HOOK_PRIO_DEFAULT);
-
-static void lightbar_sleep_entry(void)
-{
-	if (!lightbar_is_enabled())
-		return;
-
-	lightbar_set_auto_control(true);
-	/*
-	 * Set this flag, then EC'll base on it to set resume tick after
-	 * S0ix/S3 exit.
-	 */
-	lightbar_enter_s0ix_s3 = true;
-	lightbar_resume_tick = 0;
-
-	lightbar_set_color(BAR_RESET);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, lightbar_sleep_entry, HOOK_PRIO_DEFAULT);
-
-static void lightbar_sleep_exit(void)
-{
-	if (!lightbar_is_enabled())
-		return;
-
-	lightbar_set_auto_control(true);
-	if (lightbar_enter_s0ix_s3)
-		lightbar_resume_tick = LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP;
-	else
-		lightbar_resume_tick = 0;
-	lightbar_enter_s0ix_s3 = false;
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, lightbar_sleep_exit, HOOK_PRIO_DEFAULT);
-
-#define LB_BAT_THRESHOLD_1	16
-#define LB_BAT_THRESHOLD_2	40
-#define LB_BAT_THRESHOLD_3	60
-#define LB_BAT_THRESHOLD_4	80
-
-static enum lightbar_states lightbar_get_state(void)
-{
-	enum lightbar_states new_state = LB_NUM_STATES;
-	int cur_bat_percent;
-
-	cur_bat_percent = charge_get_percent();
-
-	if (!lid_is_open())
-		return LB_STATE_LID_CLOSE;
-
-	if (lightbar_resume_tick) {
-		if ((battery_is_present() == BP_YES) &&
-			charge_get_display_charge()) {
-			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
-				new_state = LB_STATE_S0_BAT_LOW;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
-				new_state = LB_STATE_S0_BAT_LV1;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_3)
-				new_state = LB_STATE_S0_BAT_LV2;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_4)
-				new_state = LB_STATE_S0_BAT_LV3;
-			else
-				new_state = LB_STATE_S0_BAT_LV4;
-		} else
-			new_state = LB_STATE_S0_AC_ONLY;
-		return new_state;
-	}
-
-	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		return LB_STATE_OFF;
-
-	if (extpower_is_present()) {
-		if ((battery_is_present() == BP_YES) &&
-			charge_get_display_charge()) {
-			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
-				new_state = LB_STATE_SLEEP_AC_BAT_LOW;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
-				new_state = LB_STATE_SLEEP_AC_BAT_LV1;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_3)
-				new_state = LB_STATE_SLEEP_AC_BAT_LV2;
-			else if (cur_bat_percent < LB_BAT_THRESHOLD_4)
-				new_state = LB_STATE_SLEEP_AC_BAT_LV3;
-			else
-				new_state = LB_STATE_SLEEP_AC_BAT_LV4;
-		} else
-			new_state = LB_STATE_SLEEP_AC_ONLY;
-	} else {
-		if (cur_bat_percent < LB_BAT_THRESHOLD_1)
-			new_state = LB_STATE_SLEEP_BAT_LOW;
-		else
-			new_state = LB_STATE_SLEEP_BAT_ONLY;
-	}
-
-	return new_state;
-}
-
-#define LIGHTBAR_DEBOUNCE_TICKS 1
-static void lightbar_update(void)
-{
-	static uint8_t ticks, period;
-	static enum lightbar_states lb_cur_state = LB_NUM_STATES;
-	static int debounce_lightbar_state_update;
-	enum lightbar_states desired_state;
-	int phase;
-
-	if (!lightbar_is_enabled())
-		return;
-
-	if (lightbar_is_auto_control())
-		desired_state = lightbar_get_state();
-	else {
-		desired_state = lightbar_get_demo_state();
-		/*
-		 * Stop to update lb_cur_state if desired_state is equal to
-		 * LB_NUM_STATES.
-		 */
-		if (desired_state == LB_NUM_STATES)
-			return;
-	}
-
-	if (lightbar_resume_tick)
-		lightbar_resume_tick--;
-
-	if (desired_state != lb_cur_state &&
-		desired_state < LB_NUM_STATES) {
-		/* State is changing */
-		lb_cur_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks +
-			lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks;
-
-		/*
-		 * System will be waken up when AC status change in S0ix. Due to
-		 * EC may be late to update chipset state and cause lightbar
-		 * flash a while when system transfer to S0. We add to debounce
-		 * for any lightbar status change.
-		 * It can make sure lightbar state is ready to to update.
-		 */
-		debounce_lightbar_state_update = LIGHTBAR_DEBOUNCE_TICKS;
-	}
-
-	/* If this state is undefined, turn lightbar off */
-	if (period == 0) {
-		CPRINTS("Undefined lightbar behavior for lightbar state %d,"
-			"turning off lightbar", lb_cur_state);
-		lightbar_set_color(BAR_OFF);
-		return;
-	}
-
-	if (debounce_lightbar_state_update != 0) {
-		debounce_lightbar_state_update--;
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks ? 0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	lightbar_set_color(lb_table[lb_cur_state][phase].color);
-
-}
-
-DECLARE_HOOK(HOOK_TICK, lightbar_update, HOOK_PRIO_DEFAULT);
-
-/****************************************************************************/
-/* EC console commands for lightbar */
-/****************************************************************************/
-static void lightbar_dump_status(void)
-{
-	uint32_t cbi_bid, cbi_skuid;
-	int cbi_ssfc_lightbar;
-
-	ccprintf("lightbar is %ssupported, %sabled, auto_control: %sabled\n",
-			lightbar_is_supported()?"":"un-",
-			lightbar_is_enabled()?"en":"dis",
-			lightbar_is_auto_control()?"en":"dis");
-
-	cbi_bid = get_board_id();
-	cbi_get_sku_id(&cbi_skuid);
-	cbi_ssfc_lightbar = get_cbi_ssfc_lightbar();
-	ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n",
-			cbi_bid,
-			cbi_skuid,
-			cbi_ssfc_lightbar);
-}
-
-#ifdef CONFIG_CONSOLE_CMDHELP
-static int help(const char *cmd)
-{
-	ccprintf("Usage:\n");
-	ccprintf("  %s                       - dump lightbar status\n", cmd);
-	ccprintf("  %s on                    - set on lightbar auto control\n",
-				cmd);
-	ccprintf("  %s off                   - set off lightbar auto control\n",
-				cmd);
-	ccprintf("  %s demo [%x - %x]          - demo lightbar state\n",
-				cmd, LB_STATE_OFF, (LB_NUM_STATES - 1));
-	return EC_SUCCESS;
-}
-#endif
-
-static int command_lightbar(int argc, char **argv)
-{
-	/* no args = dump lightbar status */
-	if (argc == 1) {
-		lightbar_dump_status();
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "help")) {
-	#ifdef CONFIG_CONSOLE_CMDHELP
-		help(argv[0]);
-	#endif
-		return EC_SUCCESS;
-	}
-
-	if (!lightbar_is_enabled()) {
-		lightbar_dump_status();
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	if (!strcasecmp(argv[1], "on")) {
-		lightbar_set_auto_control(true);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "off")) {
-		lightbar_set_auto_control(false);
-		lightbar_set_demo_state(LB_NUM_STATES);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "demo")) {
-		int lb_demo_state;
-		char *e;
-
-		/* Need to disable auto_control before demo */
-		if (lightbar_is_auto_control()) {
-			ccprintf("Please set off auto control before demo.\n");
-			return EC_ERROR_ACCESS_DENIED;
-		}
-
-		lb_demo_state = 0xff & strtoi(argv[2], &e, 16);
-		lightbar_set_demo_state(lb_demo_state);
-		return EC_SUCCESS;
-	}
-
-#ifdef CONFIG_CONSOLE_CMDHELP
-	help(argv[0]);
-#endif
-
-	return EC_ERROR_INVAL;
-}
-
-DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar,
-			"[help | on | off | demo]",
-			"get/set lightbar status");
-
-/****************************************************************************/
-/* EC host commands (ectool) for lightbar */
-/****************************************************************************/
-static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_lightbar *in = args->params;
-	int lb_demo_state;
-
-	/*
-	 * HOST_CMD is binded with ectool. From ectool.c, it already define
-	 * command format.
-	 * We only base on "off", "on", and "seq" to do what we can do
-	 * now.
-	 * Originally, I expect to use "demo", but it limit "in->demo.num"
-	 * within 0~1. So, adopt "seq" command for basic testing.
-	 */
-	switch (in->cmd) {
-	case LIGHTBAR_CMD_OFF:
-		lightbar_set_auto_control(false);
-		lightbar_set_demo_state(LB_NUM_STATES);
-		break;
-	case LIGHTBAR_CMD_ON:
-		lightbar_set_auto_control(true);
-		break;
-	case LIGHTBAR_CMD_SEQ:
-		lb_demo_state = in->seq.num;
-		if (lightbar_is_auto_control()) {
-			CPRINTS("Please set off auto control before demo.");
-			return EC_RES_ACCESS_DENIED;
-		}
-		lightbar_set_demo_state(lb_demo_state);
-		break;
-	default:
-		CPRINTS("LB bad cmd 0x%x", in->cmd);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD,
-		     lpc_cmd_lightbar,
-		     EC_VER_MASK(0));
diff --git a/board/lindar/vif_override.xml b/board/lindar/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lindar/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lingcod/battery.c b/board/lingcod/battery.c
deleted file mode 100644
index 7f37c6fe10..0000000000
--- a/board/lingcod/battery.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			/*
-			 * voltage min value and precharge current value are
-			 * specified by LGC directly and not shown in the SPEC.
-			 */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L19D4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 333,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/lingcod/board.c b/board/lingcod/board.c
deleted file mode 100644
index c294100b02..0000000000
--- a/board/lingcod/board.c
+++ /dev/null
@@ -1,542 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Malefor board-specific configuration */
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Malefor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_NO_A,
-};
-
-static void board_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * TODO: b/154447182 - Malefor will control power LED and battery LED
-	 * independently, and keep the max brightness of power LED and battery
-	 * LED as 50%.
-	 */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_cfg_has_tabletmode();
-}
-
-/* Enable or disable input devices, based on tablet mode or chipset state */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-/******************************************************************************/
-/* Sensors */
-/* Lid and base Sensor mutex */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid and base accel private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159024035): Malefor: check USB PD reset operation */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO(b/159024035): Malefor: check FW_CONFIG fields for USB DB type */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/lingcod/board.h b/board/lingcod/board.h
deleted file mode 100644
index c2cef9c50b..0000000000
--- a/board/lingcod/board.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Enabling USB4 mode */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lingcod/build.mk b/board/lingcod/build.mk
deleted file mode 100644
index 279b2e559e..0000000000
--- a/board/lingcod/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/lingcod/ec.tasklist b/board/lingcod/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/lingcod/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/lingcod/gpio.inc b/board/lingcod/gpio.inc
deleted file mode 100644
index 52bce7b2ce..0000000000
--- a/board/lingcod/gpio.inc
+++ /dev/null
@@ -1,163 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/lingcod/led.c b/board/lingcod/led.c
deleted file mode 100644
index 0f7d37723b..0000000000
--- a/board/lingcod/led.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Malefor
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/lingcod/vif_override.xml b/board/lingcod/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/lingcod/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/lux b/board/lux
deleted file mode 120000
index e61be5c7db..0000000000
--- a/board/lux
+++ /dev/null
@@ -1 +0,0 @@
-poppy
\ No newline at end of file
diff --git a/board/madoo/battery.c b/board/madoo/battery.c
deleted file mode 100644
index 92afe149f3..0000000000
--- a/board/madoo/battery.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack information
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "extpower.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_CosMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/madoo/board.c b/board/madoo/board.c
deleted file mode 100644
index 1c989b859e..0000000000
--- a/board/madoo/board.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Madoo board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/nb7v904m.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "keyboard_8042_sharedlib.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-	if (get_cbi_fw_config_keyboard() == CUST_UK2_KB) {
-		/*
-		 * Observed on Shyvana with UK keyboard,
-		 *   \|:     0x0061->0x61->0x56
-		 *   r-ctrl: 0xe014->0x14->0x1d
-		 */
-		uint16_t tmp = get_scancode_set2(4, 0);
-
-		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
-		set_scancode_set2(2, 7, tmp);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(1, true);
-	raa489000_hibernate(0, false);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 reduce
-	 * our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usbc0_retimer = {
-	.usb_port = 0,
-	.i2c_port = I2C_PORT_USB_C0,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-};
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-};
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	}
-};
-
-static void reconfigure_usbmux(void)
-{
-	if (system_get_board_version() < 2) {
-		CPRINTS("add redriver at usbc0");
-		usb_muxes[0].next_mux = &usbc0_retimer;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/madoo/board.h b/board/madoo/board.h
deleted file mode 100644
index 7528f256c0..0000000000
--- a/board/madoo/board.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Madoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* GPIO for C1 interrupts, for baseboard use */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* Keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_NB7V904M
-
-/* LED */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_SIMPLO_COS,
-	BATTERY_CosMX,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Keyboard type */
-enum fw_config_keyboard_type {
-	COMMON_KB = 0,
-	CUST_UK2_KB = 1,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/madoo/build.mk b/board/madoo/build.mk
deleted file mode 100644
index cd002a20e7..0000000000
--- a/board/madoo/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/madoo/cbi_ssfc.c b/board/madoo/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/madoo/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/madoo/cbi_ssfc.h b/board/madoo/cbi_ssfc.h
deleted file mode 100644
index 873b90f993..0000000000
--- a/board/madoo/cbi_ssfc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t usb_ss_mux : 3;
-		uint32_t reserved_2 : 23;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/madoo/ec.tasklist b/board/madoo/ec.tasklist
deleted file mode 100644
index 0aba1fabeb..0000000000
--- a/board/madoo/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/madoo/gpio.inc b/board/madoo/gpio.inc
deleted file mode 100644
index b26c7814ce..0000000000
--- a/board/madoo/gpio.inc
+++ /dev/null
@@ -1,145 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_USB_C1_INT_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(A, 2), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-
-/*LEDs*/
-GPIO(BAT_LED_AMBER_L,  PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_L,  PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_CHG_LED_R_Y,  PIN(F, 2), GPIO_OUT_HIGH)
-GPIO(EC_CHG_LED_R_W,  PIN(F, 3), GPIO_OUT_HIGH)
-
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO34_NC, PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO37_NC, PIN(3, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO41_NC, PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/madoo/led.c b/board/madoo/led.c
deleted file mode 100644
index d6bed74e4b..0000000000
--- a/board/madoo/led.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for madoo
- */
-
-#include "charge_state.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "hooks.h"
-#include "system.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* madoo: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-/*
- * Turn off battery LED, if AC is present but battery is not charging.
- * It could be caused by battery's protection like OTP.
- */
-int battery_safety_check(void)
-{
-	uint8_t data[6];
-	int rv;
-
-	/* ignore battery in error state because it has other behavior */
-	if (charge_get_state() == PWR_STATE_ERROR)
-		return false;
-
-	/* turn off LED due to a safety fault */
-	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return false;
-	/*
-	 * Each bit represents for one safey status, and normally they should
-	 * all be 0. Data reads from LSB to MSB.
-	 * data[2] - BIT 7-0
-	 * AOLDL, AOLD, OCD2, OCD1, OCC2, OCC1, COV, CUV
-	 *
-	 * data[3] - BIT 15-8
-	 * RSVD, CUVC, OTD, OTC, ASCDL, ASCD, ASCCL, ASCC
-	 *
-	 * data[4] - BIT 23-16
-	 * CHGC, OC, RSVD, CTO, RSVD, PTO, RSVD, OTF
-	 *
-	 * data[5] - BIT 31-24
-	 * RSVD, RSVD, OCDL, COVL, UTD, UTC, PCHGC, CHGV
-	 */
-	if (data[2] || data[3] || data[4] || data[5])
-		return true;
-
-	return false;
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		/* Ports are controlled by different GPIO */
-		if (battery_safety_check()) {
-			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
-		} else if (charge_manager_get_active_charge_port() == 1 ||
-			system_get_board_version() < 3) {
-			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
-			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		} else if (charge_manager_get_active_charge_port() == 0) {
-			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_ON_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
-		}
-		break;
-	case EC_LED_COLOR_AMBER:
-		/* Ports are controlled by different GPIO */
-		if (battery_safety_check()) {
-			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
-		} else if (charge_get_state() == PWR_STATE_ERROR &&
-				system_get_board_version() >= 3) {
-			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
-		} else if (charge_manager_get_active_charge_port() == 1 ||
-				system_get_board_version() < 3) {
-			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
-		} else if (charge_manager_get_active_charge_port() == 0) {
-			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
-		} else if (charge_get_percent() <
-				CONFIG_LED_ONOFF_STATES_BAT_LOW) {
-			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
-			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
-		}
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
-		gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/madoo/usb_pd_policy.c b/board/madoo/usb_pd_policy.c
deleted file mode 100644
index 02bb449f60..0000000000
--- a/board/madoo/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/madoo/vif_override.xml b/board/madoo/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/madoo/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/magnemite b/board/magnemite
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/magnemite
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/magolor/battery.c b/board/magolor/battery.c
deleted file mode 100644
index 84f75732ec..0000000000
--- a/board/magolor/battery.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "gpio.h"
-#include "util.h"
-
-/*
- * Battery info for magolor battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-		/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* AP18C7M */
-	[BATTERY_AP18C7M] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP KT00407008",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 17600,
-			.voltage_normal       = 15400,
-			.voltage_min          = 12000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 70,
-		},
-	},
-	/* COSMX AP20CBL Battery Information */
-	 [BATTERY_COSMX_AP20CBL] = {
-		.fuel_gauge = {
-			.manuf_name = "COSMX KT0030B002",
-			.device_name = "AP20CBL",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/magolor/board.c b/board/magolor/board.c
deleted file mode 100644
index 8ecabb551d..0000000000
--- a/board/magolor/board.c
+++ /dev/null
@@ -1,1100 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/retimer/ps8802.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-static uint8_t new_adc_key_state;
-
-static void ps8762_chaddr_deferred(void);
-DECLARE_DEFERRED(ps8762_chaddr_deferred);
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-	GPIO_EN_USB_A1_VBUS,
-};
-
-#ifdef BOARD_MAGOLOR
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config magolor_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config magister_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config magpie_keybd = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-static const struct ec_response_keybd_config magma_keybd = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override
-uint8_t board_keyboard_row_refresh(void)
-{
-	if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
-		return 3;
-	else
-		return 2;
-}
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	if (get_cbi_fw_config_numeric_pad()) {
-		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
-			return &magma_keybd;
-		else
-			return &magpie_keybd;
-	}
-	else {
-		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
-			return &magister_keybd;
-		else
-			return &magolor_keybd;
-	}
-}
-#endif
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-#ifdef BOARD_MAGOLOR
-static void board_update_no_keypad_by_fwconfig(void)
-{
-	if (!get_cbi_fw_config_numeric_pad()) {
-#ifndef TEST_BUILD
-		/* Disable scanning KSO13 & 14 if keypad isn't present. */
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-		keyscan_config.actual_key_mask[11] = 0xfa;
-		keyscan_config.actual_key_mask[12] = 0xca;
-#endif
-	}
-}
-#endif
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-#ifdef BOARD_WADDLEDOO
-static void reconfigure_5v_gpio(void)
-{
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (system_get_board_version() < 0) {
-		CPRINTS("old board - remapping 5V en");
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
-#endif /* BOARD_WADDLEDOO */
-
-static void set_5v_gpio(int level)
-{
-	int version;
-	enum gpio_signal gpio = GPIO_EN_PP5000;
-
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (IS_ENABLED(BOARD_WADDLEDOO)) {
-		version = system_get_board_version();
-
-		/*
-		 * If the CBI EEPROM wasn't formatted, assume it's a very early
-		 * board.
-		 */
-		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
-	}
-
-	gpio_set_level(gpio, level);
-}
-
-static void ps8762_chaddr_deferred(void)
-{
-	/* Switch PS8762 I2C Address to 0x50*/
-	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
-		CPRINTS("Switch PS8762 address to 0x50 success");
-	else
-		CPRINTS("Switch PS8762 address to 0x50 failed");
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
-	} else {
-		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-
-		if (!enable)
-			return;
-		/*
-		 * Port C1 the PP3300_USB_C1  assert, delay 15ms
-		 * colud be accessed PS8762 by I2C.
-		 */
-		hook_call_deferred(&ps8762_chaddr_deferred_data, 15 * MSEC);
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CHARGER_NUM - 1;
-	else
-		return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Matrices to rotate accelerometers into the magister reference. */
-static const mat33_fp_t lid_magister_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-#ifdef BOARD_MAGOLOR
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* ICM426 private data */
-static struct icm_drv_data_t g_icm426xx_data;
-/* KX022 private data */
-static struct kionix_accel_data g_kx022_data;
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-#endif
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-
-		/* Set HDMI and sub-rail enables to output */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
-			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
-
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-
-		/* Enable interrupt for passing through HPD */
-		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	} else {
-		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
-
-		/* Enable C1 interrupt and check if it needs processing */
-		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
-		check_c1_line();
-	}
-
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	if (get_cbi_fw_config_tablet_mode()) {
-#ifdef BOARD_MAGOLOR
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE GYRO is ICM426XX");
-		} else
-			ccprints("BASE GYRO is BMI160");
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			ccprints("LID_ACCEL is KX022");
-		} else {
-			if (system_get_board_version() >= 5) {
-				motion_sensors[LID_ACCEL]
-				.rot_standard_ref = &lid_magister_ref;
-			}
-			ccprints("LID_ACCEL is BMA253");
-		}
-#endif
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize THERMAL */
-	setup_thermal();
-
-#ifdef BOARD_MAGOLOR
-	/* Support Keyboard Pad */
-		board_update_no_keypad_by_fwconfig();
-#endif
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-#ifdef BOARD_MAGOLOR
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
-	#else
-		bmi160_interrupt(signal);
-#endif
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
-	}
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-int adc_to_physical_value(enum gpio_signal gpio)
-{
-	if (gpio == GPIO_VOLUME_UP_L)
-		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
-	else if (gpio == GPIO_VOLUME_DOWN_L)
-		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
-
-	CPRINTS("Not a volume up or down key");
-	return 0;
-}
-
-int button_is_adc_detected(enum gpio_signal gpio)
-{
-	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
-}
-
-static void adc_vol_key_press_check(void)
-{
-	int volt = adc_read_channel(ADC_SUB_ANALOG);
-	static uint8_t old_adc_key_state;
-	uint8_t adc_key_state_change;
-
-	if (volt > 2400 && volt < 2540) {
-		/* volume-up is pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK;
-	} else if (volt > 2600 && volt < 2740) {
-		/* volume-down is pressed */
-		new_adc_key_state = ADC_VOL_DOWN_MASK;
-	} else if (volt < 2300) {
-		/* both volumn-up and volume-down are pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
-	} else if (volt > 2780) {
-		/* both volumn-up and volume-down are released */
-		new_adc_key_state = 0;
-	}
-	if (new_adc_key_state != old_adc_key_state) {
-		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
-		if (adc_key_state_change && ADC_VOL_UP_MASK)
-			button_interrupt(GPIO_VOLUME_UP_L);
-		if (adc_key_state_change && ADC_VOL_DOWN_MASK)
-			button_interrupt(GPIO_VOLUME_DOWN_L);
-
-		old_adc_key_state = new_adc_key_state;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/magolor/board.h b/board/magolor/board.h
deleted file mode 100644
index c1ef73cc64..0000000000
--- a/board/magolor/board.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-#ifdef BOARD_MAGOLOR_LEGACY
-/* this change saves 1656 bytes of RW flash space */
-#define CONFIG_CHIP_INIT_ROM_REGION
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#else
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
-
-/* Remove default commands to free flash space */
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_BATTFAKE
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* GPIO for C1 interrupts, for baseboard use */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#ifdef BOARD_MAGOLOR
-
-#define CONFIG_KEYBOARD_KEYPAD
-#endif
-#define CONFIG_PWM_KBLIGHT
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_PS8802
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
-
-/*******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/*
- * I2C pin names for baseboard
- *
- * Note: these lines will be set as i2c on start-up, but this should be
- * okay since they're ODL.
- */
-#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
-#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-
-#ifdef BOARD_MAGOLOR
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#endif
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#ifdef BOARD_MAGOLOR
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#endif
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Volume Button feature */
-#define CONFIG_ADC_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_AP18C7M,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_COSMX_AP20CBL,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/magolor/build.mk b/board/magolor/build.mk
deleted file mode 100644
index fcf5dec3ed..0000000000
--- a/board/magolor/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-# A limited Magolor_legacy boards are reworked with NPCX796FC variant.
-# Set the modify the variant type to match.
-ifeq ($(BOARD),magolor_legacy)
-CHIP_VARIANT:=npcx7m6fc
-else
-CHIP_VARIANT:=npcx7m7fc
-endif
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/magolor/cbi_ssfc.c b/board/magolor/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/magolor/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/magolor/cbi_ssfc.h b/board/magolor/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/magolor/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/magolor/ec.tasklist b/board/magolor/ec.tasklist
deleted file mode 100644
index 0aba1fabeb..0000000000
--- a/board/magolor/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/magolor/gpio.inc b/board/magolor/gpio.inc
deleted file mode 100644
index b7b692ca56..0000000000
--- a/board/magolor/gpio.inc
+++ /dev/null
@@ -1,147 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,	PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
-
-/* Extra Sub-board I/O pins */
-
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_VIVALDIKEYBOARD_ID,	PIN(4, 0), GPIO_INPUT + GPIO_PULL_DOWN)	/* keyboard ID */
-
-/* LED */
-GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
-GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
-GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/magolor/led.c b/board/magolor/led.c
deleted file mode 100644
index 5206244073..0000000000
--- a/board/magolor/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Magolor
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/magolor/usb_pd_policy.c b/board/magolor/usb_pd_policy.c
deleted file mode 100644
index 02bb449f60..0000000000
--- a/board/magolor/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/magolor/vif_override.xml b/board/magolor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/magolor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/makomo/battery.c b/board/makomo/battery.c
deleted file mode 100644
index 1b162e93c7..0000000000
--- a/board/makomo/battery.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,   /* mV */
-			.voltage_normal		= 11400,   /* mV */
-			.voltage_min		= 9000,    /* mV */
-			.precharge_current	= 256,     /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -40,
-			.discharging_max_c	= 73,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/makomo/board.c b/board/makomo/board.c
deleted file mode 100644
index 1bb6b134a7..0000000000
--- a/board/makomo/board.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "keyboard_backlight.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
-};
-
-void board_kblight_init(void)
-{
-	kblight_register(&kblight_it8801);
-}
-
-bool board_has_kb_backlight(void)
-{
-	/* Default enable keyboard backlight */
-	return true;
-}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Battery functions */
-#define SB_SMARTCHARGE				0x26
-/* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
-/* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_SMARTCHARGE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_SMARTCHARGE, val);
-}
-
-/* Called on AP S0iX -> S0 transition */
-static void board_chipset_resume(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 1);
-#endif
-
-	/* Normal charge mode */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void board_chipset_suspend(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 0);
-#endif
-
-	/* Quick charge mode */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
-
-int board_get_battery_i2c(void)
-{
-	return board_get_version() >= 1 ? 2 : 1;
-}
-
-#ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
-{
-	switch (type) {
-	case EC_PWM_TYPE_GENERIC:
-		*channel = index;
-		break;
-	default:
-		return -1;
-	}
-
-	return *channel >= 1;
-}
-
-static enum ec_status
-host_command_pwm_set_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_duty *p = args->params;
-	enum pwm_channel channel;
-	uint16_t duty;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	duty = (uint32_t) p->duty * 255 / 65535;
-	it8801_pwm_set_raw_duty(channel, duty);
-	it8801_pwm_enable(channel, p->duty > 0);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_pwm_get_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_get_duty *p = args->params;
-	struct ec_response_pwm_get_duty *r = args->response;
-
-	enum pwm_channel channel;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
-		     EC_VER_MASK(0));
-#endif
diff --git a/board/makomo/board.h b/board/makomo/board.h
deleted file mode 100644
index 844fd95292..0000000000
--- a/board/makomo/board.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Makomo */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#undef CONFIG_CMD_MFALLOW
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-#undef CONFIG_SYSTEM_UNLOCKED
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#ifdef SECTION_IS_RW
-#define CONFIG_IO_EXPANDER_IT8801_PWM
-#define CONFIG_KEYBOARD_BACKLIGHT
-#endif
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	IT8801_PWM_CH_KBLIGHT = 0,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/makomo/build.mk b/board/makomo/build.mk
deleted file mode 100644
index 04b88d3d79..0000000000
--- a/board/makomo/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/makomo/ec.tasklist b/board/makomo/ec.tasklist
deleted file mode 100644
index e943459024..0000000000
--- a/board/makomo/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/makomo/gpio.inc b/board/makomo/gpio.inc
deleted file mode 100644
index 287ebbda1f..0000000000
--- a/board/makomo/gpio.inc
+++ /dev/null
@@ -1,121 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/makomo/led.c b/board/makomo/led.c
deleted file mode 100644
index 140c31babe..0000000000
--- a/board/makomo/led.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Makomo
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/makomo/vif_override.xml b/board/makomo/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/makomo/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/malefor/battery.c b/board/malefor/battery.c
deleted file mode 100644
index 7f37c6fe10..0000000000
--- a/board/malefor/battery.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 332,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			/*
-			 * voltage min value and precharge current value are
-			 * specified by LGC directly and not shown in the SPEC.
-			 */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L19D4PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 333,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/malefor/board.c b/board/malefor/board.c
deleted file mode 100644
index 663c5bace9..0000000000
--- a/board/malefor/board.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Malefor board-specific configuration */
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "common.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Malefor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_NO_A,
-};
-
-static void board_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/*
-	 * TODO: b/154447182 - Malefor will control power LED and battery LED
-	 * independently, and keep the max brightness of power LED and battery
-	 * LED as 50%.
-	 */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return ec_cfg_has_tabletmode();
-}
-
-/* Enable or disable input devices, based on tablet mode or chipset state */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
-			enable = 0;
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-/******************************************************************************/
-/* Sensors */
-/* Lid and base Sensor mutex */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid and base accel private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* USBC TCPC configuration for port 1 on USB3 board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-};
-
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3 = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-void board_reset_pd_mcu(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-__override void board_cbi_init(void)
-{
-	/* Config DB USB3 */
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3;
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/malefor/board.h b/board/malefor/board.h
deleted file mode 100644
index e21984350d..0000000000
--- a/board/malefor/board.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Enabling USB4 mode */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED4_SIDESEL = 0,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/malefor/build.mk b/board/malefor/build.mk
deleted file mode 100644
index 279b2e559e..0000000000
--- a/board/malefor/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
diff --git a/board/malefor/ec.tasklist b/board/malefor/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/malefor/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/malefor/gpio.inc b/board/malefor/gpio.inc
deleted file mode 100644
index 6f770eb17a..0000000000
--- a/board/malefor/gpio.inc
+++ /dev/null
@@ -1,163 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-UNIMPLEMENTED(EC_PROCHOT_IN_L)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/malefor/led.c b/board/malefor/led.c
deleted file mode 100644
index 0f7d37723b..0000000000
--- a/board/malefor/led.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Malefor
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF,            LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/malefor/vif_override.xml b/board/malefor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/malefor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/marzipan/battery.c b/board/marzipan/battery.c
deleted file mode 100644
index 3a9a1cbaf1..0000000000
--- a/board/marzipan/battery.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all marzipan battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* COSMX DM02032XL 333-AC-13-A */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-13-A",
-			.device_name = "DM02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* Simplo DM02032XL 333-AC-13-A */
-	[BATTERY_SIMPLO] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-13-A",
-			.device_name = "DM02032XL",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 45,
-			.discharging_min_c      = -10,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_COSMX;
diff --git a/board/marzipan/board.c b/board/marzipan/board.c
deleted file mode 100644
index 915f96743d..0000000000
--- a/board/marzipan/board.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Marzipan board-specific configuration */
-
-#include "adc_chip.h"
-#include "battery_fuel_gauge.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_config.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
-	 * as it still uses the legacy location (KSO_01/KSI_00).
-	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-enum base_accelgyro_type {
-	BASE_GYRO_NONE = 0,
-	BASE_GYRO_BMI160 = 1,
-	BASE_GYRO_ICM426XX = 2,
-};
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref_bmi160 = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref_bma255 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref_kx022 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref_bma255,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref_bmi160,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref_bmi160,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref_kx022,
-	.default_range = 2, /* g, enough for laptop. */
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_standard_ref_icm426xx,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm426xx,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int base_accelgyro_config;
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_accelgyro_config) {
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case BASE_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	/* Check lid accel chip */
-	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
-		BMA2x2_CHIP_ID_ADDR, &val);
-	if (ret)
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-
-	CPRINTS("Lid Accel: %s", ret ? "KX022" : "BMA255");
-
-	/* Check base accelgyro chip */
-	ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, &val);
-	if (val == ICM426XX_CHIP_ICM40608) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-	}
-
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-
-	board_detect_motionsensor();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/board/marzipan/board.h b/board/marzipan/board.h
deleted file mode 100644
index 3ef8952ee5..0000000000
--- a/board/marzipan/board.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Marzipan board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* ICM426XX Base accel/gyro */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* KX022 lid accel */
-#define CONFIG_ACCEL_KX022
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_COSMX,
-	BATTERY_SIMPLO,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/marzipan/build.mk b/board/marzipan/build.mk
deleted file mode 100644
index 09853a26d7..0000000000
--- a/board/marzipan/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=led.o
-board-y+=switchcap.o
-board-y+=usbc_config.o
diff --git a/board/marzipan/ec.tasklist b/board/marzipan/ec.tasklist
deleted file mode 100644
index 5beeb38feb..0000000000
--- a/board/marzipan/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/marzipan/gpio.inc b/board/marzipan/gpio.inc
deleted file mode 100644
index 11fa6b5a53..0000000000
--- a/board/marzipan/gpio.inc
+++ /dev/null
@@ -1,185 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-
-/* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
- * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap; will be configured in the board init */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_B_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(C, 0))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(6, 0))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(D, 3))
-UNUSED(PIN(8, 6))
-UNUSED(PIN(7, 5))
-UNUSED(PIN(D, 1))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/marzipan/led.c b/board/marzipan/led.c
deleted file mode 100644
index e4b34576c8..0000000000
--- a/board/marzipan/led.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_AMBER;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: Amber 1 sec, off 3 sec */
-			period = (1 + 3) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_AMBER;
-			else
-				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* Discharging in S5: off */
-			color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* Discharging in S0: Blue on */
-			color = LED_BLUE;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber 1 sec, off 1 sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_AMBER;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: Blue on */
-		color = LED_BLUE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
-			color = LED_BLUE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_BLUE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/marzipan/switchcap.c b/board/marzipan/switchcap.c
deleted file mode 100644
index 26009d55d8..0000000000
--- a/board/marzipan/switchcap.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "power/qcom.h"
-#include "system.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_DA9313_GPIO0);
-}
diff --git a/board/marzipan/usbc_config.c b/board/marzipan/usbc_config.c
deleted file mode 100644
index 3704a94197..0000000000
--- a/board/marzipan/usbc_config.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Marzipan board-specific USB-C configuration */
-
-#include "usb_pd.h"
-#include "usbc_config.h"
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
diff --git a/board/marzipan/usbc_config.h b/board/marzipan/usbc_config.h
deleted file mode 100644
index 7f72b01700..0000000000
--- a/board/marzipan/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Marzipan board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#include "gpio.h"
-
-void tcpc_alert_event(enum gpio_signal signal);
-void usb0_evt(enum gpio_signal signal);
-void usb1_evt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void board_connect_c0_sbu(enum gpio_signal s);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/marzipan/vif_override.xml b/board/marzipan/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/marzipan/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/masterball b/board/masterball
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/masterball
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/max32660-eval/board.c b/board/max32660-eval/board.c
deleted file mode 100644
index 15a856ab4e..0000000000
--- a/board/max32660-eval/board.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 EvalKit Board Specific Configuration */
-
-#include "i2c.h"
-#include "board.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "registers.h"
-#include "util.h"
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/max32660-eval/board.h b/board/max32660-eval/board.h
deleted file mode 100644
index bcca57f18a..0000000000
--- a/board/max32660-eval/board.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_FPU
-
-/* Modules we want to exclude */
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_PECI
-#undef CONFIG_SWITCH
-#define CONFIG_CMD_HOSTCMD
-
-#undef CONFIG_HOSTCMD_EVENTS
-#define CONFIG_I2C
-
-#define CONFIG_I2C_PERIPHERAL
-#define CONFIG_HOSTCMD_I2C_ADDR_FLAGS (0x51) /* 7 bit right-aligned */
-
-/* Slave I2C port configuration */
-#define I2C_PORT_SLAVE 1
-#define I2C_PORT_EC I2C_PORT_SLAVE
-
-/* Write protect is active high */
-#define CONFIG_WP_ACTIVE_HIGH
-
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 2240
-
-#ifndef __ASSEMBLER__
-
-/* Second UART port */
-#define CONFIG_UART_HOST 1
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/max32660-eval/build.mk b/board/max32660-eval/build.mk
deleted file mode 100644
index a613922cd2..0000000000
--- a/board/max32660-eval/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# MAX32660 Device
-CHIP:=max32660
-
-board-y=board.o
diff --git a/board/max32660-eval/ec.tasklist b/board/max32660-eval/ec.tasklist
deleted file mode 100644
index 5e58b9dea8..0000000000
--- a/board/max32660-eval/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * List of enabled tasks in the priority order
- *
- * The first one has the lowest priority.
- *
- * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
- * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
- * where :
- * 'n' in the name of the task
- * 'r' in the main routine of the task
- * 'd' in an opaque parameter passed to the routine at startup
- * 's' is the stack size in bytes; must be a multiple of 8
- * 	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, TASK_STACK_SIZE) \
- */
-#define CONFIG_TASK_LIST                                                       \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE)                   \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/max32660-eval/gpio.inc b/board/max32660-eval/gpio.inc
deleted file mode 100644
index 3ced37a77f..0000000000
--- a/board/max32660-eval/gpio.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/*
- * Signals which aren't implemented on Board but we'll emulate anyway, to
- * make it more convenient to debug other code.
- */
-UNIMPLEMENTED(WP)	  /* Write protect input */
-UNIMPLEMENTED(ENTERING_RW) /* EC entering RW code */
-
-ALTERNATE(PIN_MASK(0, 0x0C00), 2, MODULE_UART, 0) /* Alt 2, P0.10 (UART1_TX), P0.11 (UART1_RX) */
-ALTERNATE(PIN_MASK(0, 0x000C), 1, MODULE_I2C, 0)  /* Alt 1, P0.2  (I2C1_SCL), P0.3  (I2C1_SDA) */
diff --git a/board/mchpevb1/battery.c b/board/mchpevb1/battery.c
deleted file mode 100644
index fcc09994bf..0000000000
--- a/board/mchpevb1/battery.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "util.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
-#define PARAM_CUT_OFF_HIGH 0x00
-
-/* Battery info for BQ40Z55 */
-static const struct battery_info info = {
-	.voltage_max = 8700,        /* mV */
-	.voltage_normal = 7600,
-	.voltage_min = 6000,
-	.precharge_current = 256,   /* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 46,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	uint8_t buf[3];
-
-	/* Ship mode command must be sent twice to take effect */
-	buf[0] = SB_MANUFACTURER_ACCESS & 0xff;
-	buf[1] = PARAM_CUT_OFF_LOW;
-	buf[2] = PARAM_CUT_OFF_HIGH;
-
-	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	return rv;
-}
-
-#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
-
-static int fast_charging_allowed = 1;
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* temp in 0.1 deg C */
-	int temp_c = curr->batt.temperature - 2731;
-	/* keep track of last temperature range for hysteresis */
-	static enum {
-		TEMP_RANGE_1,
-		TEMP_RANGE_2,
-		TEMP_RANGE_3,
-		TEMP_RANGE_4,
-		TEMP_RANGE_5,
-	} temp_range = TEMP_RANGE_3;
-	/* keep track of last voltage range for hysteresis */
-	static enum {
-		VOLTAGE_RANGE_LOW,
-		VOLTAGE_RANGE_HIGH,
-	} voltage_range = VOLTAGE_RANGE_LOW;
-
-	/* Current and previous battery voltage */
-	int batt_voltage;
-	static int prev_batt_voltage;
-
-	/*
-	 * Determine temperature range. The five ranges are:
-	 *   < 10C
-	 *   10-15C
-	 *   15-23C
-	 *   23-45C
-	 *   > 45C
-	 *
-	 * Add 0.2 degrees of hysteresis.
-	 * If temp reading was bad, use last range.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) {
-		if (temp_c < 99)
-			temp_range = TEMP_RANGE_1;
-		else if (temp_c > 101 && temp_c < 149)
-			temp_range = TEMP_RANGE_2;
-		else if (temp_c > 151 && temp_c < 229)
-			temp_range = TEMP_RANGE_3;
-		else if (temp_c > 231 && temp_c < 449)
-			temp_range = TEMP_RANGE_4;
-		else if (temp_c > 451)
-			temp_range = TEMP_RANGE_5;
-	}
-
-	/*
-	 * If battery voltage reading is bad, use the last reading. Otherwise,
-	 * determine voltage range with hysteresis.
-	 */
-	if (curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) {
-		batt_voltage = prev_batt_voltage;
-	} else {
-		batt_voltage = prev_batt_voltage = curr->batt.voltage;
-		if (batt_voltage < 8200)
-			voltage_range = VOLTAGE_RANGE_LOW;
-		else if (batt_voltage > 8300)
-			voltage_range = VOLTAGE_RANGE_HIGH;
-	}
-
-	/*
-	 * If we are not charging or we aren't using fast charging profiles,
-	 * then do not override desired current and voltage.
-	 */
-	if (curr->state != ST_CHARGE || !fast_charging_allowed)
-		return 0;
-
-	/*
-	 * Okay, impose our custom will:
-	 * When battery is 0-10C:
-	 * CC at 486mA @ 8.7V
-	 * CV at 8.7V
-	 *
-	 * When battery is <15C:
-	 * CC at 1458mA @ 8.7V
-	 * CV at 8.7V
-	 *
-	 * When battery is <23C:
-	 * CC at 3402mA until 8.3V @ 8.7V
-	 * CC at 2430mA @ 8.7V
-	 * CV at 8.7V
-	 *
-	 * When battery is <45C:
-	 * CC at 4860mA until 8.3V @ 8.7V
-	 * CC at 2430mA @ 8.7V
-	 * CV at 8.7V until current drops to 450mA
-	 *
-	 * When battery is >45C:
-	 * CC at 2430mA @ 8.3V
-	 * CV at 8.3V (when battery is hot we don't go to fully charged)
-	 */
-	switch (temp_range) {
-	case TEMP_RANGE_1:
-		curr->requested_current = 486;
-		curr->requested_voltage = 8700;
-		break;
-	case TEMP_RANGE_2:
-		curr->requested_current = 1458;
-		curr->requested_voltage = 8700;
-		break;
-	case TEMP_RANGE_3:
-		curr->requested_voltage = 8700;
-		if (voltage_range == VOLTAGE_RANGE_HIGH)
-			curr->requested_current = 2430;
-		else
-			curr->requested_current = 3402;
-		break;
-	case TEMP_RANGE_4:
-		curr->requested_voltage = 8700;
-		if (voltage_range == VOLTAGE_RANGE_HIGH)
-			curr->requested_current = 2430;
-		else
-			curr->requested_current = 4860;
-		break;
-	case TEMP_RANGE_5:
-		curr->requested_current = 2430;
-		curr->requested_voltage = 8300;
-		break;
-	}
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		*value = fast_charging_allowed;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		fast_charging_allowed = value;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-static int command_fastcharge(int argc, char **argv)
-{
-	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
-		return EC_ERROR_PARAM1;
-
-	ccprintf("fastcharge %s\n", fast_charging_allowed ? "on" : "off");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
-			"Get or set fast charging profile");
-
-#endif	/* CONFIG_CHARGER_PROFILE_OVERRIDE */
diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c
deleted file mode 100644
index 73cec110bb..0000000000
--- a/board/mchpevb1/board.c
+++ /dev/null
@@ -1,984 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Microchip Evaluation Board(EVB) with
- * MEC1701H 144-pin processor card.
- * EVB connected to Intel SKL RVP3 configured
- * for eSPI with Kabylake silicon.
- */
-
-#include "adc.h"
-#include "als.h"
-#include "bd99992gw.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/als_opt3001.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/tcpm/tcpci.h"
-#include "extpower.h"
-#include "gpio_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "espi.h"
-#include "lpc_chip.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "spi_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-#include "battery_smart.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-
-/* NOTE: MEC17xx EVB + SKL RVP3 does not use BD99992 PMIC.
- * RVP3 PMIC controlled by RVP3 logic.
- */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-
-/*
- * Maxim DS1624 I2C temperature sensor used for testing I2C.
- * DS1624 contains one internal temperature sensor
- * and EEPROM. It has no external temperature inputs.
- */
-#define DS1624_I2C_ADDR_FLAGS	(0x48 | I2C_FLAG_BIG_ENDIAN)
-#define DS1624_IDX_LOCAL	0
-#define DS1624_READ_TEMP16	0xAA	/* read 16-bit temperature */
-#define DS1624_ACCESS_CFG	0xAC	/* read/write 8-bit config */
-#define DS1624_CMD_START	0xEE
-#define DS1624_CMD_STOP		0x22
-
-/*
- * static global and routine to return smart battery
- * temperature when we do not build with charger task.
- */
-static int smart_batt_temp;
-static int ds1624_temp;
-static int sb_temp(int idx, int *temp_ptr);
-static int ds1624_get_val(int idx, int *temp_ptr);
-static void board_spi_enable(void);
-static void board_spi_disable(void);
-
-#ifdef CONFIG_BOARD_PRE_INIT
-/*
- * Used to enable JTAG debug during development.
- * NOTE: If ARM Serial Wire Viewer not used then SWV pin can be
- * be disabled and used for another purpose. Change mode to
- * MCHP_JTAG_MODE_SWD.
- * For low power idle testing enable GPIO060 as function 2(48MHZ_OUT)
- * to check PLL is turning off in heavy sleep. Note, do not put GPIO060
- * in gpio.inc
- * GPIO060 is port 1 bit[16].
- */
-void board_config_pre_init(void)
-{
-	smart_batt_temp = 0;
-	ds1624_temp = 0;
-
-#ifdef CONFIG_CHIPSET_DEBUG
-	MCHP_EC_JTAG_EN = MCHP_JTAG_ENABLE + MCHP_JTAG_MODE_SWD_SWV;
-#endif
-
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_MCHP_48MHZ_OUT)
-	gpio_set_alternate_function(1, 0x10000, 2);
-#endif
-}
-#endif /* #ifdef CONFIG_BOARD_PRE_INIT */
-
-
-/*
- * Use EC to handle ALL_SYS_PWRGD signal.
- * MEC17xx connected to SKL/KBL RVP3 reference board
- * is required to monitor ALL_SYS_PWRGD and drive SYS_RESET_L
- * after a 10 to 100 ms delay.
- */
-#ifdef CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD
-
-static void board_all_sys_pwrgd(void)
-{
-	int allsys_in = gpio_get_level(GPIO_ALL_SYS_PWRGD);
-	int allsys_out = gpio_get_level(GPIO_SYS_RESET_L);
-
-	if (allsys_in == allsys_out)
-		return;
-
-	CPRINTS("ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, allsys_out);
-
-	trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d",
-			allsys_in, allsys_out);
-
-	/*
-	 * Wait at least 10 ms between power signals going high
-	 */
-	if (allsys_in)
-		msleep(100);
-
-	if (!allsys_out) {
-		/* CPRINTS("Set SYS_RESET_L = %d", allsys_in); */
-		trace1(0, BRD, 0, "Set SYS_RESET_L=%d", allsys_in);
-		gpio_set_level(GPIO_SYS_RESET_L, allsys_in);
-		/* Force fan on for kabylake RVP */
-		gpio_set_level(GPIO_EC_FAN1_PWM, 1);
-	}
-}
-DECLARE_DEFERRED(board_all_sys_pwrgd);
-
-void all_sys_pwrgd_interrupt(enum gpio_signal signal)
-{
-	trace0(0, ISR, 0, "ALL_SYS_PWRGD Edge");
-	hook_call_deferred(&board_all_sys_pwrgd_data, 0);
-}
-#endif /* #ifdef CONFIG_BOARD_HAS_ALL_SYS_PWRGD */
-
-
-#ifdef HAS_TASK_PDCMD
-/* Exchange status with PD MCU. */
-static void pd_mcu_interrupt(enum gpio_signal signal)
-{
-	/* Exchange status with PD MCU to determine interrupt cause */
-	host_command_pd_send_status(0);
-
-}
-#endif
-
-#ifdef CONFIG_USB_POWER_DELIVERY
-void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-#endif
-
-/*
- * enable_input_devices() is called by the tablet_mode ISR, but changes the
- * state of GPIOs, so its definition must reside after including gpio_list.
- */
-static void enable_input_devices(void);
-DECLARE_DEFERRED(enable_input_devices);
-
-void tablet_mode_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels
- * name, factor multiplier, factor divider, shift, channel
- */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
-	[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
-	/* Adapter current output or battery discharging current */
-	[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
-	/* System current consumption */
-	[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
-	[ADC_CASE] = {"CASE", 1, 1, 0, 7},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/*
- * MCHP EVB connected to KBL RVP3
- */
-const struct i2c_port_t i2c_ports[]  = {
-	{"sensors",  MCHP_I2C_PORT4, 100,  GPIO_SMB04_SCL, GPIO_SMB04_SDA},
-	{"batt",     MCHP_I2C_PORT5, 100,  GPIO_SMB05_SCL, GPIO_SMB05_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*
- * Map ports to controller.
- * Ports may map to the same controller.
- */
-const uint16_t i2c_port_to_ctrl[I2C_PORT_COUNT] = {
-	(MCHP_I2C_CTRL0 << 8) + MCHP_I2C_PORT4,
-	(MCHP_I2C_CTRL1 << 8) + MCHP_I2C_PORT5
-};
-
-/*
- * default to I2C0 because callers may not check
- * return value if we returned an error code.
- */
-int board_i2c_p2c(int port)
-{
-	int i;
-
-	for (i = 0; i < I2C_PORT_COUNT; i++)
-		if ((i2c_port_to_ctrl[i] & 0xFF) == port)
-			return (int)(i2c_port_to_ctrl[i] >> 8);
-
-	return -1;
-}
-
-#ifdef CONFIG_USB_POWER_DELIVERY
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
-	 &tcpci_tcpm_drv},
-
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
-	 &tcpci_tcpm_drv},
-};
-#endif
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
-#if defined(CONFIG_SPI_ACCEL_PORT)
-	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
-#endif
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-
-/*
- * Deep sleep support, called by chip level.
- */
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_BOARD_DEEP_SLEEP)
-
-/*
- * Perform any board level prepare for sleep actions.
- * For example, disabling pin/pads to further reduce
- * current during sleep.
- */
-void board_prepare_for_deep_sleep(void)
-{
-#if defined(CONFIG_GPIO_POWER_DOWN) && \
-	defined(CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN)
-	gpio_power_down_module(MODULE_SPI_FLASH);
-	gpio_power_down_module(MODULE_SPI_CONTROLLER);
-	gpio_power_down_module(MODULE_I2C);
-	/* powering down keyscan is causing an issue with keyscan task
-	 * probably due to spurious interrupts on keyscan pins.
-	 * gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
-	 */
-
-#ifndef CONFIG_POWER_S0IX
-	gpio_power_down_module(MODULE_LPC);
-#endif
-#endif
-}
-
-/*
- * Perform any board level resume from sleep actions.
- * For example, re-enabling pins powered off in
- * board_prepare_for_deep_sleep().
- */
-void board_resume_from_deep_sleep(void)
-{
-#if defined(CONFIG_GPIO_POWER_DOWN) && \
-	defined(CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN)
-#ifndef CONFIG_POWER_S0IX
-	gpio_config_module(MODULE_LPC, 1);
-#endif
-	/* gpio_config_module(MODULE_KEYBOARD_SCAN, 1); */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	gpio_config_module(MODULE_I2C, 1);
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_MUX_PI3USB30532
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_1,
-		.mux_lock = NULL,
-	},
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_2,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
-	}
-};
-#endif
-
-/**
- * Reset PD MCU
- */
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_PD_RST_L, 0);
-	usleep(100);
-	gpio_set_level(GPIO_PD_RST_L, 1);
-}
-
-/*
- *
- */
-static int therm_get_val(int idx, int *temp_ptr)
-{
-	if (temp_ptr != NULL) {
-		*temp_ptr = adc_read_channel(idx);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_PARAM2;
-}
-
-#ifdef CONFIG_TEMP_SENSOR
-#if 0 /* Chromebook design uses ADC in BD99992GW PMIC */
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0, 4},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-		BD99992GW_ADC_CHANNEL_SYSTHERM0, 4},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-		BD99992GW_ADC_CHANNEL_SYSTHERM1, 4},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-		BD99992GW_ADC_CHANNEL_SYSTHERM2, 4},
-	{"Wifi", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-		BD99992GW_ADC_CHANNEL_SYSTHERM3, 4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-#else /* mec1701_evb test I2C and EC ADC */
-/*
- * battery charge_get_battery_temp requires charger task running.
- * OR can we call into driver/battery/smart.c
- * int sb_read(int cmd, int *param)
- * sb_read(SB_TEMPERATURE, &batt_new.temperature)
- * Issue is functions in this table return a value from a memory array.
- * There's a task or hook that is actually reading the temperature.
- * We could implement a one second hook to call sb_read() and fill in
- * a static global in this module.
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0},
-	{"Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-#endif
-#endif
-
-#ifdef CONFIG_ALS
-/* ALS instances. Must be in same order as enum als_id. */
-struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
-};
-BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
-#endif
-
-const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
-	{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
-	 30 * MSEC, 0},
-	{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
-	 30 * MSEC, 0},
-};
-
-/* MCHP mec1701_evb connected to Intel SKL RVP3 with Kabylake
- * processor we do not control the PMIC on SKL.
- */
-static void board_pmic_init(void)
-{
-	int rv, cfg;
-
-	/* No need to re-init PMIC since settings are sticky across sysjump */
-	if (system_jumped_late())
-		return;
-
-#if 0 /* BD99992GW PMIC on a real Chromebook */
-	/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x30, 0x4a);
-
-	/*
-	 * Set V100ACNT / V1.00A Control Register:
-	 * Nominal output = 1.0V.
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x37, 0x1a);
-
-	/*
-	 * Set V085ACNT / V0.85A Control Register:
-	 * Lower power mode = 0.7V.
-	 * Nominal output = 1.0V.
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x38, 0x7a);
-
-	/* VRMODECTRL - enable low-power mode for VCCIO and V0.85A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x3b, 0x18);
-#else
-	CPRINTS("HOOK_INIT - called board_pmic_init");
-	trace0(0, HOOK, 0, "HOOK_INIT - call board_pmic_init");
-
-	/* Config DS1624 temperature sensor for continuous conversion */
-	cfg = 0x66;
-	rv = i2c_read8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
-		       DS1624_ACCESS_CFG, &cfg);
-	trace2(0, BRD, 0, "Read DS1624 Config rv = %d  cfg = 0x%02X",
-	       rv, cfg);
-
-	if ((rv == EC_SUCCESS) && (cfg & (1u << 0))) {
-		/* one-shot mode switch to continuous */
-		rv = i2c_write8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
-				DS1624_ACCESS_CFG, 0);
-		trace1(0, BRD, 0, "Write DS1624 Config to 0, rv = %d", rv);
-		/* writes to config require 10ms until next I2C command */
-		if (rv == EC_SUCCESS)
-			udelay(10000);
-	}
-
-	/* Send start command */
-	rv = i2c_write8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
-			DS1624_CMD_START, 1);
-	trace1(0, BRD, 0, "Send Start command to DS1624 rv = %d", rv);
-
-	return;
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	CPRINTS("MEC1701 HOOK_INIT - called board_init");
-	trace0(0, HOOK, 0, "HOOK_INIT - call board_init");
-
-#ifdef CONFIG_USB_POWER_DELIVERY
-	/* Enable PD MCU interrupt */
-	gpio_enable_interrupt(GPIO_PD_MCU_INT);
-	/* Enable VBUS interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
-
-	/* Enable pericom BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-#endif
-	/* Enable tablet mode interrupt for input device enable */
-	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-
-	if (system_jumped_late() &&
-	    chipset_in_state(CHIPSET_STATE_ON)) {
-		trace0(0, BRD, 0, "board_init: S0 call board_spi_enable");
-		board_spi_enable();
-	}
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-
-/**
- * Buffer the AC present GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	CPRINTS("MEC1701 HOOK_AC_CHANGE - called board_extpower");
-	trace0(0, HOOK, 0, "HOOK_AC_CHANGET - call board_extpower");
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGER
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a realy physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source vbus on that port */
-	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
-						       GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTS("MEC1701 Skip enable p%d", charge_port);
-		trace1(0, BOARD, 0, "Skip enable charge port %d",
-			charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("MEC1701 New chg p%d", charge_port);
-	trace1(0, BOARD, 0, "New charge port %d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
-					     GPIO_USB_C1_CHARGE_EN_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
-					     GPIO_USB_C0_CHARGE_EN_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-#else
-/*
- * TODO HACK providing functions from common/charge_state_v2.c
- * which is not compiled in when no charger
- */
-int charge_prevent_power_on(int power_button_pressed)
-{
-	return 0;
-}
-
-
-#endif
-
-/*
- * Enable or disable input devices,
- * based upon chipset state and tablet mode
- */
-static void enable_input_devices(void)
-{
-	int kb_enable = 1;
-	int tp_enable = 1;
-
-	/* Disable both TP and KB in tablet mode */
-	if (!gpio_get_level(GPIO_TABLET_MODE_L))
-		kb_enable = tp_enable = 0;
-	/* Disable TP if chipset is off */
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		tp_enable = 0;
-
-	keyboard_scan_enable(kb_enable, KB_SCAN_DISABLE_LID_ANGLE);
-	gpio_set_level(GPIO_ENABLE_TOUCHPAD, tp_enable);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	CPRINTS("MEC1701 HOOK_CHIPSET_STARTUP - called board_chipset_startup");
-	trace0(0, HOOK, 0, "HOOK_CHIPSET_STARTUP - board_chipset_startup");
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-	gpio_set_level(GPIO_USB2_ENABLE, 1);
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-		board_chipset_startup,
-		HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	CPRINTS("MEC1701 HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
-	trace0(0, HOOK, 0,
-	       "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-	gpio_set_level(GPIO_USB2_ENABLE, 0);
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		board_chipset_shutdown,
-		HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	CPRINTS("MEC1701_EVG HOOK_CHIPSET_RESUME");
-	trace0(0, HOOK, 0, "HOOK_CHIPSET_RESUME - board_chipset_resume");
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-#if 0 /* TODO not implemented in gpio.inc */
-	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
-	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 1);
-#endif
-
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume,
-	     MOTION_SENSE_HOOK_PRIO-1);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	CPRINTS("MEC1701 HOOK_CHIPSET_SUSPEND - called board_chipset_resume");
-	trace0(0, HOOK, 0, "HOOK_CHIPSET_SUSPEND - board_chipset_suspend");
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-#if 0 /* TODO not implemented in gpio.inc */
-	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 0);
-	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
-		board_chipset_suspend,
-		HOOK_PRIO_DEFAULT);
-
-void board_hibernate_late(void)
-{
-	/* put host chipset into reset */
-	gpio_set_level(GPIO_SYS_RESET_L, 0);
-
-	/* Turn off LEDs in hibernate */
-	gpio_set_level(GPIO_CHARGE_LED_1, 0);
-	gpio_set_level(GPIO_CHARGE_LED_2, 0);
-
-	/*
-	 * Set PD wake low so that it toggles high to generate a wake
-	 * event once we leave hibernate.
-	 */
-	gpio_set_level(GPIO_USB_PD_WAKE, 0);
-
-#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
-	/*
-	 * Leave USB-C charging enabled in hibernate, in order to
-	 * allow wake-on-plug. 5V enable must be pulled low.
-	 */
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 0
-	gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-	gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
-#endif
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-	gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
-#endif
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */
-}
-
-/* Any glados boards post version 2 should have ROP_LDO_EN stuffed. */
-#define BOARD_MIN_ID_LOD_EN 2
-/* Make the pmic re-sequence the power rails under these conditions. */
-#define PMIC_RESET_FLAGS \
-	(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD)
-static void board_handle_reboot(void)
-{
-#if 0 /* MEC17xx EVB + SKL-RVP3 does not use chromebook PMIC design */
-	int flags;
-#endif
-	CPRINTS("MEC HOOK_INIT - called board_handle_reboot");
-	trace0(0, HOOK, 0, "HOOK_INIT - board_handle_reboot");
-
-	if (system_jumped_late())
-		return;
-
-	if (system_get_board_version() < BOARD_MIN_ID_LOD_EN)
-		return;
-
-#if 0 /* TODO MCHP KBL hack not PMIC system */
-	/* Interrogate current reset flags from previous reboot. */
-	flags = system_get_reset_flags();
-
-	if (!(flags & PMIC_RESET_FLAGS))
-		return;
-
-	/* Preserve AP off request. */
-	if (flags & EC_RESET_FLAG_AP_OFF)
-		chip_save_reset_flags(EC_RESET_FLAG_AP_OFF);
-
-	ccprintf("Restarting system with PMIC.\n");
-	/* Flush console */
-	cflush();
-
-	/* Bring down all rails but RTC rail (including EC power). */
-	gpio_set_flags(GPIO_BATLOW_L_PMIC_LDO_EN, GPIO_OUT_HIGH);
-	while (1)
-		; /* wait here */
-#else
-	return;
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
-
-
-static int sb_temp(int idx, int *temp_ptr)
-{
-	if (idx != 0)
-		return EC_ERROR_PARAM1;
-
-	if (temp_ptr == NULL)
-		return EC_ERROR_PARAM2;
-
-	*temp_ptr = smart_batt_temp;
-
-	return EC_SUCCESS;
-}
-
-static int ds1624_get_val(int idx, int *temp_ptr)
-{
-	if (idx != 0)
-		return EC_ERROR_PARAM1;
-
-	if (temp_ptr == NULL)
-		return EC_ERROR_PARAM2;
-
-	*temp_ptr = ds1624_temp;
-
-	return EC_SUCCESS;
-}
-
-/* call smart battery code to get its temperature
- * output is in tenth degrees C
- */
-static void sb_update(void)
-{
-	int rv __attribute__((unused));
-
-	rv = sb_read(SB_TEMPERATURE, &smart_batt_temp);
-	smart_batt_temp = smart_batt_temp / 10;
-
-	trace12(0, BRD, 0, "sb_read temperature rv=%d  temp=%d K",
-		rv, smart_batt_temp);
-}
-
-/*
- * Read temperature from Maxim DS1624 sensor. It only has internal sensor
- * and is configured for continuous reading mode by default.
- * DS1624 does not implement temperature limits or other features of
- * sensors like the TMP411.
- * Output format is 16-bit MSB first signed celcius temperature in units
- * of 0.0625 degree Celsius.
- * b[15]=sign bit
- * b[14]=2^6, b[13]=2^5, ..., b[8]=2^0
- * b[7]=1/2, b[6]=1/4, b[5]=1/8, b[4]=1/16
- * b[3:0]=0000b
- *
- */
-static void ds1624_update(void)
-{
-	uint32_t d;
-	int temp;
-	int rv __attribute__((unused));
-
-	rv = i2c_read16(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
-			DS1624_READ_TEMP16, &temp);
-
-	d = (temp & 0x7FFF) >> 8;
-	if ((uint32_t)temp & BIT(7))
-		d++;
-
-	if ((uint32_t)temp & BIT(15))
-		d |= (1u << 31);
-
-	ds1624_temp = (int32_t)d;
-
-	trace3(0, BRD, 0, "ds1624_update: rv=%d raw temp = 0x%04X tempC = %d",
-	       rv, temp, ds1624_temp);
-}
-
-/* Indicate scheduler is alive by blinking an LED.
- * Test I2C by reading a smart battery and temperature sensor.
- * Smart battery 16 bit temperature is in units of 1/10 degree C.
- */
-static void board_one_sec(void)
-{
-	trace0(0, BRD, 0, "HOOK_SECOND");
-
-	if (gpio_get_level(GPIO_CHARGE_LED_2))
-		gpio_set_level(GPIO_CHARGE_LED_2, 0);
-	else
-		gpio_set_level(GPIO_CHARGE_LED_2, 1);
-
-	sb_update();
-	ds1624_update();
-}
-DECLARE_HOOK(HOOK_SECOND, board_one_sec, HOOK_PRIO_DEFAULT);
-
-/* Motion sensors */
-
-static struct mutex g_base_mutex;
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-#ifdef CONFIG_ACCEL_KX022
-static struct mutex g_lid_mutex;
-/* KX022 private data */
-static struct kionix_accel_data g_kx022_data;
-#endif
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(
-			CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = NULL, /* Identity matrix. */
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(
-			CONFIG_SPI_ACCEL_PORT),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = NULL, /* Identity Matrix. */
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-#ifdef CONFIG_ACCEL_KX022
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = NULL, /* Identity matrix. */
-		.default_range = 2, /* g, enough for laptop. */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-#endif /* #ifdef CONFIG_ACCEL_KX022 */
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_spi_enable(void)
-{
-	trace0(0, BRD, 0, "HOOK_CHIPSET_STARTUP - board_spi_enable");
-
-	spi_enable(&spi_devices[1], 1);
-
-	/* Toggle SPI chip select to switch BMI160 from I2C mode
-	 * to SPI mode
-	 */
-	gpio_set_level(GPIO_SPI0_CS0, 0);
-	udelay(10);
-	gpio_set_level(GPIO_SPI0_CS0, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	trace0(0, BRD, 0, "HOOK_CHIPSET_SHUTDOWN - board_spi_disable");
-	spi_enable(&spi_devices[1], 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-
-#ifdef MEC1701_EVB_TACH_TEST /* PWM/TACH test */
-void tach0_isr(void)
-{
-	MCHP_INT_DISABLE(MCHP_TACH_GIRQ) = MCHP_TACH_GIRQ_BIT(0);
-	MCHP_INT_SOURCE(MCHP_TACH_GIRQ) = MCHP_TACH_GIRQ_BIT(0);
-}
-DECLARE_IRQ(MCHP_IRQ_TACH_0, tach0_isr, 1);
-#endif
diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h
deleted file mode 100644
index 98ab333b67..0000000000
--- a/board/mchpevb1/board.h
+++ /dev/null
@@ -1,487 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Microchip Evaluation Board (EVB) with
- * MEC1701H 144-pin processor card.
- * EVB connected to Intel SKL RVP3 configured
- * for eSPI with Kabylake silicon.
- */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Initial board bringup and prevent power button task from
- * generating event to exit G3 state.
- *
- * #define CONFIG_BRINGUP
- */
-
-/*
- * Debug on EVB with CONFIG_CHIPSET_DEBUG
- * Keep WDG disabled and JTAG enabled.
- * CONFIG_BOARD_PRE_INIT enables JTAG early
- */
-/* #define CONFIG_CHIPSET_DEBUG */
-
-#ifdef CONFIG_CHIPSET_DEBUG
-#ifndef CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_PRE_INIT
-#endif
-#endif
-
-/*
- * DEBUG: Add CRC32 in last 4 bytes of EC_RO/RW binaries
- * in SPI. LFW will use DMA CRC32 HW to check data integrity.
- * #define CONFIG_MCHP_LFW_DEBUG
- */
-
-/*
- * EC UART console on UART 0 or 1
- */
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Override Boot-ROM JTAG mode
- * 0x01 = 4-pin standard JTAG
- * 0x03 = ARM 2-pin SWD + 1-pin SWV
- * 0x05 = ARM 2-pin SWD no SWV
- */
-#define CONFIG_MCHP_JTAG_MODE 0x03
-
-/*
- * Enable Trace FIFO Debug port
- * When this is undefined all TRACEn() and tracen()
- * macros are defined as blank.
- * Uncomment this define to enable these messages.
- * Only enable if GPIO's 0171 & 0171 are available therefore
- * define this at the board level.
- */
-/* #define CONFIG_MCHP_TFDP */
-
-/*
- * Enable MCHP specific GPIO EC UART commands
- * for debug.
- */
-/* #define CONFIG_MEC_GPIO_EC_CMDS */
-
-/*
- * Enable CPRINT in chip eSPI module
- * and EC UART test command.
- */
-/* #define CONFIG_MCHP_ESPI_DEBUG */
-
-/*
- * Enable board specific ISR on ALL_SYS_PWRGD signal.
- * Requires for handling Kabylake/Skylake RVP3 board's
- * ALL_SYS_PWRGD signal.
- */
-#define CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD
-
-/*
- * EVB eSPI test mode (no eSPI master connected)
- */
-/*
- * #define EVB_NO_ESPI_TEST_MODE
- */
-
-
-/*
- * DEBUG
- * Disable ARM Cortex-M4 write buffer so
- * exceptions become synchronous.
- *
- * #define CONFIG_DEBUG_DISABLE_WRITE_BUFFER
- */
-
-/* New eSPI configuration items */
-
-/*
- * Maximum clock frequence eSPI EC advertises
- * Values in MHz are 20, 25, 33, 50, and 66
- */
-/* KBL + EVB fly-wire hook up only supports 20MHz */
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ	MCHP_ESPI_CAP1_MAX_FREQ_20M
-
-/*
- * EC eSPI advertises IO lanes
- * 0 = Single
- * 1 = Single and Dual
- * 2 = Single and Quad
- * 3 = Single, Dual, and Quad
- */
-/* KBL + EVB fly-wire hook up only support Single mode */
-#define CONFIG_HOSTCMD_ESPI_EC_MODE	MCHP_ESPI_CAP1_SINGLE_MODE
-
-/*
- * Bit map of eSPI channels EC advertises
- * bit[0] = 1 Peripheral channel
- * bit[1] = 1 Virtual Wire channel
- * bit[2] = 1 OOB channel
- * bit[3] = 1 Flash channel
- */
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	MCHP_ESPI_CAP0_ALL_CHAN_SUPP
-
-#define CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-
-/*
- * Allow dangerous commands.
- * TODO(shawnn): Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* Optional features */
-#define CONFIG_ACCELGYRO_BMI160
-/* #define CONFIG_ACCEL_KX022 */
-/* #define CONFIG_ALS */
-/* #define CONFIG_ALS_OPT3001 */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_BUTTON_COUNT 2
-/* #define CONFIG_CHARGE_MANAGER */
-/* #define CONFIG_CHARGE_RAMP_SW */
-
-
-/* #define CONFIG_CHARGER */
-
-/* #define CONFIG_CHARGER_DISCHARGE_ON_AC */
-/* #define CONFIG_CHARGER_ISL9237 */
-/* #define CONFIG_CHARGER_ILIM_PIN_DISABLED */
-/* #define CONFIG_CHARGER_INPUT_CURRENT 512 */
-
-/* #define CONFIG_CHARGER_NARROW_VDC */
-/* #define CONFIG_CHARGER_PROFILE_OVERRIDE */
-/* #define CONFIG_CHARGER_SENSE_RESISTOR 10 */
-/* #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 */
-/* #define CONFIG_CMD_CHARGER_ADC_AMON_BMON */
-
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-#define CONFIG_CLOCK_CRYSTAL
-#define CONFIG_EXTPOWER_GPIO
-/* #define CONFIG_HOSTCMD_PD */
-/* #define CONFIG_HOSTCMD_PD_PANIC */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-
-#ifdef CONFIG_ACCEL_KX022
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#endif /* CONFIG_ACCEL_KX022 */
-
-#define CONFIG_LID_SWITCH
-/*
- * Enable MCHP Low Power Idle support
- * and API to power down pins
- * #define CONFIG_LOW_POWER_IDLE
- */
-
-
-/* #define CONFIG_GPIO_POWER_DOWN */
-
-/*
- * Turn off pin modules during deep sleep.
- * Requires CONFIG_GPIO_POWER_DOWN
- */
-/* #define CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN */
-
-/*
- * DEBUG: Configure MEC17xx GPIO060 as 48MHZ_OUT to
- * verify & debug clock is shutdown in heavy sleep.
- */
-#define CONFIG_MCHP_48MHZ_OUT
-
-/*
- * DEBUG: Save and print out PCR sleep enables,
- * clock required, and interrupt aggregator result
- * registers.
- */
-#define CONFIG_MCHP_DEEP_SLP_DEBUG
-
-/*
- * MCHP debug EC code turn off GCC link-time-optimization
- * #define CONFIG_LTO
- */
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-
-/*
- * MEC1701H SCI is virtual wire on eSPI
- *#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
- */
-
-#if 0 /* MCHP EVB + KBL/SKL RVP3 no USB charging hardware */
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_MUX_PI3USB30532
-#define CONFIG_USB_MUX_PS8740
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_TCPCI
-#endif
-/*
- * #define CONFIG_USB_PD_TCPC
- * #define CONFIG_USB_PD_TCPM_STUB
- */
-#if 0
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#endif
-
-#define CONFIG_VBOOT_HASH
-
-/*
- * MEC1701H loads firmware using QMSPI controller
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-/*
- * Google uses smaller flashes on chromebook boards
- * MCHP SPI test dongle for EVB uses 16MB W25Q128F
- * Configure for smaller flash is OK for testing except
- * for SPI flash lock bit.
- */
- #define CONFIG_FLASH_SIZE_BYTES 524288
- #define CONFIG_SPI_FLASH_W25X40
-/*
- * #define CONFIG_FLASH_SIZE_BYTES 0x1000000
- * #define CONFIG_SPI_FLASH_W25Q128
- */
-
-/*
- * Enable extra SPI flash and generic SPI
- * commands via EC UART
- */
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SPI_XFER
-
-/* common software SHA256 required by vboot and rollback */
-#define CONFIG_SHA256
-
-/*
- * Enable MCHP SHA256 hardware accelerator module.
- * API is same as software SHA256 but prefixed with "chip_"
- * #define CONFIG_SHA256_HW
- */
-
-/* enable console command to test HW Hash engine
- * #define CONFIG_CMD_SHA256_TEST
- */
-
-/*
- * MEC17xx EVB + SKL/KBL RVP3 does not have
- * BD99992GW PMIC with NCP15WB thermistor.
- * We have connected a Maxim DS1624 I2C temperature
- * sensor. The sensor board has a thermistor on it
- * we connect to an EC ADC channel.
- */
-#if 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_DPTF
-#else
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_DPTF
-#endif
-
-/* Enable GPSPI0 controller and port for
- * SPI Accelerometer.
- * bit[0] == 1 GPSPI0
- * bit[1] == 0 board does not use GPSPI1
- * Make sure to not include GPSPI in little-firmware(LFW)
- */
-#ifndef LFW
-#define CONFIG_MCHP_GPSPI	0x01
-#endif
-
-/* SPI Accelerometer
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_ACCEL_PORT 1
-
-/*
- * Enable EC UART commands to read/write
- * motion sensor.
- */
-#define CONFIG_CMD_ACCELS
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#define CONFIG_WATCHDOG_HELP
-
-#if 0 /* TODO - No wireless on EVB */
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-
-/* Wireless signals */
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
-#endif
-
-/* LED signals */
-#define GPIO_BAT_LED_RED GPIO_CHARGE_LED_1
-#define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
-
-/* I2C ports */
-#define I2C_CONTROLLER_COUNT	2
-#define I2C_PORT_COUNT		2
-
-
-/*
- * Map I2C Ports to Controllers for this board.
- *
- * I2C Controller 0 ---- Port 0 -> PMIC, USB Charger 2
- *                   |-- Port 2 -> USB Charger 1, USB Mux
- *
- * I2C Controller 1 ---- Port 3 -> PD MCU, TCPC
- * I2C Controller 2 ---- Port 4 -> ALS, Accel
- * I2C Controller 3 ---- Port 5 -> Battery, Charger
- *
- * All other ports set to 0xff (not used)
- */
-
-#define I2C_PORT_PMIC           MCHP_I2C_PORT10
-#define I2C_PORT_USB_CHARGER_1	MCHP_I2C_PORT2
-#define I2C_PORT_USB_MUX        MCHP_I2C_PORT2
-#define I2C_PORT_USB_CHARGER_2	MCHP_I2C_PORT2
-#define I2C_PORT_PD_MCU         MCHP_I2C_PORT3
-#define I2C_PORT_TCPC           MCHP_I2C_PORT3
-#define I2C_PORT_ALS            MCHP_I2C_PORT4
-#define I2C_PORT_ACCEL          MCHP_I2C_PORT4
-#define I2C_PORT_BATTERY        MCHP_I2C_PORT5
-#define I2C_PORT_CHARGER        MCHP_I2C_PORT5
-
-/* Thermal sensors read through PMIC ADC interface */
-#if 0
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-#else
-#define I2C_PORT_THERMAL	MCHP_I2C_PORT4
-#endif
-
-/* Ambient Light Sensor address */
-#define OPT3001_I2C_ADDR_FLAGS	OPT3001_I2C_ADDR1_FLAGS
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_TEMP_SENSOR
-#undef CONFIG_CMD_TIMERINFO
-/* #undef CONFIG_CONSOLE_CMDHELP */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CASE,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-
-	/* These temp sensors are only readable in S0 */
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CASE,
-/*	TEMP_SENSOR_CHARGER, */
-/*	TEMP_SENSOR_DRAM, */
-/*	TEMP_SENSOR_WIFI, */
-
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	BASE_ACCEL,
-	BASE_GYRO,
-#ifdef CONFIG_ACCEL_KX022
-	LID_ACCEL,
-#endif
-	SENSOR_COUNT,
-};
-
-/* Light sensors */
-enum als_id {
-	ALS_OPT3001 = 0,
-
-	ALS_COUNT
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-
-/* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
-
-/*
- * include TFDP macros from mchp chip level
- */
-#include "tfdp_chip.h"
-
-
-/* Map I2C port to controller */
-int board_i2c_p2c(int port);
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void board_prepare_for_deep_sleep(void);
-void board_resume_from_deep_sleep(void);
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mchpevb1/build.mk b/board/mchpevb1/build.mk
deleted file mode 100644
index 412b04d46b..0000000000
--- a/board/mchpevb1/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Microchip MEC1701
-# external SPI is 512KB
-# external clock is crystal
-CHIP:=mchp
-CHIP_FAMILY:=mec170x
-CHIP_VARIANT:=mec1701
-CHIP_SPI_SIZE_KB:=512
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/mchpevb1/ec.tasklist b/board/mchpevb1/ec.tasklist
deleted file mode 100644
index 6fcd5faa98..0000000000
--- a/board/mchpevb1/ec.tasklist
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
-
diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
deleted file mode 100644
index 8be1099fbd..0000000000
--- a/board/mchpevb1/gpio.inc
+++ /dev/null
@@ -1,450 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * mec1701h_evb board GPIO pins
- * !!!!!!!!!!!!!!!!!!!!!!! IMPORTANT !!!!!!!!!!!!!!!!!!!!!!!!!!!!
- * MEC1701 and MEC1322 data sheets GPIO numbers are OCTAL.
- * Original glados MEC1322 used these octal numbers as base 10.
- * mec1701 and its boards will use OCTAL therefore make sure all
- * numbers used below are written as C OCTAL with a leading 0.
- * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- *
- */
-/* NOTE: We use JTAG on MEC1701H on EVB.
- * GPIO_0145 is JTAG_TDI
- * GPIO_0146 is JTAG_TDO
- * GPIO_0147 is JTAG_CLK
- * GPIO_0150 is JTAG_TMS
- */
-
-/* include common gpio.inc under chip/mchp/lfw/... */
-#include "chip/mchp/lfw/gpio.inc"
-
-#define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
-
-/* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_BOTH_EDGES_PU, lpcrst_interrupt)
-#endif
-
-/* MEC1701H GPIO_0015/PWM7 OK */
-GPIO_INT(LID_OPEN, PIN(015), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-/* MEC1701H GPIO_0014/PWM6/GPTP-IN6 OK */
-GPIO_INT(AC_PRESENT, PIN(014), GPIO_INT_BOTH, extpower_interrupt)
-
-/* MEC1701H GPIO_0036/RC_ID2 OK */
-/* Kabylake bringup move to gpio input */
-/* GPIO_INT(WP_L, PIN(036), GPIO_INT_BOTH, switch_interrupt) */
-
-/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
-/* MEC1701H GPIO_0023/GPTP-IN1/MVP_VR_ON OK */
-GPIO_INT(POWER_BUTTON_L, PIN(023), GPIO_INT_BOTH, power_button_interrupt)
-
-/* RSMRST from PMIC */
-/* MEC1701H GPIO_0057/VCC_PWRGD OK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(0126), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Remove. SLP_S3,S4 are eSPI virtual wires
-GPIO_INT(PCH_SLP_S4_L, PIN(0200), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S3_L, PIN(0206), GPIO_INT_BOTH, power_signal_interrupt)
-*/
-
-/* MEC1701H GPIO_0175/KSO17 OK */
-GPIO_INT(PCH_SLP_SUS_L, PIN(0175), GPIO_INT_BOTH, power_signal_interrupt)
-
-/*
- * Handle ALL_SYS_PWRGD from SKL RVP3 board
- */
-GPIO_INT(ALL_SYS_PWRGD, PIN(057), GPIO_INT_BOTH, all_sys_pwrgd_interrupt)
-
-/* Kabylake bring up move to ordinary GPIO input */
-/* MEC1701H GPIO_0034/RC_ID1/SPI0_CLK */
-/*
- *GPIO_INT(VOLUME_UP_L, PIN(034), \
- *GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
- */
-/* MEC1701H GPIO_035/PWM8/CTOUT1 OK */
-/*
- *GPIO_INT(VOLUME_DOWN_L, PIN(035), GPIO_INT_BOTH | GPIO_PULL_UP, \
- *	 button_interrupt)
- */
-
-/* MEC1701H GPIO_0161/VCI_IN2# OK */
-GPIO_INT(PMIC_INT_L, PIN(0161), GPIO_INT_FALLING, power_signal_interrupt)
-
- /* MEC1701H GPIO_0162/VCI_IN1# OK */
-/* GPIO_INT(PD_MCU_INT,        PIN(0162), \
-	 GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt) */
-/* MEC1701H GPIO_0242/ISPI_CLK OK */
-/* GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(0242), GPIO_INT_BOTH, vbus0_evt) */
-/* MEC1701H GPIO_0243/ISPI_IO0 OK */
-/* GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(0243), GPIO_INT_BOTH, vbus1_evt) */
-/* MEC1701H GPIO_0240/INT_IO3 OK */
-/* GPIO_INT(USB_C0_BC12_INT_L, PIN(0240), GPIO_INT_FALLING, usb0_evt) */
-/* MEC1701H GPIO_0241/ISPI_CS# OK */
-/* GPIO_INT(USB_C1_BC12_INT_L, PIN(0241), GPIO_INT_FALLING, usb1_evt) */
-/* MEC1701H GPIO_0100/nEC_SCI OK */
-GPIO_INT(TABLET_MODE_L, PIN(0100), GPIO_INT_BOTH | GPIO_PULL_UP, \
-	 tablet_mode_interrupt)
-/* Delayed PWR_OK from PMIC */
-/* MEC1701H GPIO_0151/ICT4/KSO15 OK */
-GPIO_INT(PMIC_DPWROK, PIN(0151), GPIO_INT_BOTH, power_signal_interrupt)
-/* UART input */
-/* MEC1701H GPIO_0105/UART0_RX OK */
-GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, \
-	 uart_deepsleep_interrupt)
-
-
-/* GPIO Pins not interrupt enabled */
-
-/* Kabylake bring up move to ordinary GPIO input */
-GPIO(VOLUME_UP_L,       PIN(034), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(VOLUME_DOWN_L,     PIN(035), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(WP_L,              PIN(036), GPIO_INPUT)
-/*
- * TODO GP-SPI0 for testing SPI accelerometer
- * GPIO_0003 Func 2 = SPI0_CS#,  func 1 = smbus00_sda
- * GPIO_0034 Func 2 = SPI0_CLK
- * GPIO_0004 Func 2 = SPI0_MOSI, func 1 = smbus00_scl
- * GPIO_0036 Func 2 = SPI0_MISO
- */
-
-
-
-/* PCH and CPU pins */
-
-/* Kabylake bringup using MECC board */
-/*
- *GPIO(ALL_SYS_PWRGD, PIN(057), GPIO_INPUT)
- */
-
-/*
- * This pulldown should be removed and SLP_S0 should be enabled as a power
- * signal interrupt in future hardware followers. The signal is pulled up
- * in the SoC when the primary rails are on and/or ramping.
- * In order to not get interrupt storms there should be external logic
- * which makes this a true binary signal into the EC.
- */
-/* MEC1701H GPIO_0222 Func1 SER_IRQ OK */
-GPIO(PCH_SLP_S0_L,          PIN(0222), GPIO_INPUT | GPIO_PULL_DOWN)
-/* MEC170H GPIO_0043 Func1 SB-TSI_CLK OK */
-GPIO(PCH_PWRBTN_L,          PIN(043),  GPIO_OUTPUT)
-/*
- *CONFLICT with KSI3. SCI becomes eSPI Virtual Wire, remove
- *GPIO(PCH_SCI_L,             PIN(026),  GPIO_ODR_HIGH)
- */
-/* When asserted, ME does not lock security descriptor */
-/* MEC1701H GPIO_0022/GPTP-IN0 OK */
-GPIO(PCH_SEC_DISABLE_L,     PIN(022),  GPIO_OUT_HIGH)
-/* MEC1701H GPIO_0016/GPTP-IN7/SHD_IO3 OK */
-GPIO(PCH_WAKE_L,            PIN(016),  GPIO_ODR_HIGH)
-/* MEC1701H GPIO_0110/PS2_CLK2 OK */
-GPIO(PCH_ACOK,              PIN(0110), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0012/SMB07_DATA OK */
-GPIO(PCH_RSMRST_L,          PIN(012), GPIO_OUT_LOW)
-/*
- * !!! Don't use GPIO_0024 if testing on MEC51xx parts because
- * it is connected in the package to nRESET_IN# and will reset
- * the part when driven low.
- * !!!
- *GPIO(PCH_RTCRST,            PIN(024), GPIO_OUT_LOW)
- */
-GPIO(PCH_RTCRST,            PIN(052), GPIO_OUT_LOW)
-
-/*
- * MEC1322 Func1=nSMI, is code switching pin to Func1?
- * Conflicts with KSO04 on MEC1701H
- * eSPI replaces this signal with eSPI Virtual Wire.
- * GPIO(PCH_SMI_L,             PIN(044),  GPIO_ODR_HIGH)
- */
-
-/*
- * RCIN# line to PCH for 8042 emulation. Becomes VWire on eSPI
- * GPIO(PCH_RCIN_L,            PIN(0135), GPIO_ODR_HIGH)
- */
-
-/* MEC1701H GPIO_0111/PS2_DAT2 OK */
-GPIO(CPU_PROCHOT,           PIN(0111), GPIO_OUT_LOW)
-
-/* MEC1701H GPIO_0025/TIN0/nEM_INT/UART_CLK OK
- * Kabylake with MECC board change to GPIO_OUT_LOW
- * GPIO(SYS_RESET_L,           PIN(025), GPIO_ODR_HIGH)
- */
-GPIO(SYS_RESET_L,           PIN(025), GPIO_OUT_LOW)
-
-/* PMIC pins */
-/* GPIO_0033/RC_ID0 OK */
-GPIO(PMIC_SLP_SUS_L,        PIN(033), GPIO_OUT_LOW)
-
-/*
- * BATLOW_L and ROP_LDO_EN are stuffing options. Set as input to
- * dynamically handle the stuffing option based on board id.
- * As both signals have external pulls setting this pin as input
- * won't harm anything.
- */
-/* MEC1701H GPIO_0163/VCI_IN0# OK */
-GPIO(BATLOW_L_PMIC_LDO_EN,  PIN(0163),  GPIO_INPUT)
-
-
-/* I2C pins - these will be reconfigured for alternate function below */
-/* MEC1701H */
-/* Using these pins as function 2 (GP-SPI0)
- * GPIO(SMB00_SCL,             PIN(004),  GPIO_INPUT)
- * GPIO(SMB00_SDA,             PIN(003),  GPIO_INPUT)
- */
-GPIO(SMB02_SCL, PIN(0155), GPIO_INPUT)
-GPIO(SMB02_SDA, PIN(0154), GPIO_INPUT)
-GPIO(SMB03_SCL, PIN(010),  GPIO_INPUT)
-GPIO(SMB03_SDA, PIN(007),  GPIO_INPUT)
-GPIO(SMB04_SCL, PIN(0144), GPIO_INPUT)
-GPIO(SMB04_SDA, PIN(0143), GPIO_INPUT)
-GPIO(SMB05_SCL, PIN(0142), GPIO_INPUT)
-GPIO(SMB05_SDA,	PIN(0141), GPIO_INPUT)
-GPIO(SMB10_SCL, PIN(0131), GPIO_INPUT)
-GPIO(SMB10_SDA, PIN(0130), GPIO_INPUT)
-
-/* USB and USB-PD related pins */
-/* MEC1701H GPIO_0153/LED2 OK */
-GPIO(PD_RST_L,              PIN(0153), GPIO_ODR_HIGH)
-/* MEC1701H GPIO_0013/SMB07_CLK/TOUT2 OK */
-GPIO(USB2_OTG_ID,           PIN(013),  GPIO_ODR_LOW)
-/* MEC1701H GPIO_0042/PECI_DAT/SB-TSI_DAT */
-GPIO(USB1_ENABLE,           PIN(042),  GPIO_OUT_LOW)
-/* MEC1701H GPIO_0067/CLKRUN# OK */
-GPIO(USB2_ENABLE,           PIN(067),  GPIO_OUT_LOW)
-/* MEC1701H GPIO_0101/BGP01 OK */
-GPIO(USB_C0_DP_HPD,         PIN(0101), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0102/BGP02 OK */
-GPIO(USB_C1_DP_HPD,         PIN(0102), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0202/ADC02 OK */
-GPIO(USB_PD_WAKE,           PIN(0202), GPIO_OUT_HIGH)
-/* MEC1701H GPIO_0140/SMB06_CLK OK */
-GPIO(USB2_OTG_VBUSSENSE,    PIN(0140), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0205/ADC05 OK */
-GPIO(USB_C0_5V_EN,          PIN(0205), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0205/ADC06 OK */
-GPIO(USB_C1_5V_EN,          PIN(0206), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0165/32KHZ_IN/CTOUT0/TRACECLK OK */
-GPIO(USB_C0_CHARGE_EN_L,    PIN(0165),  GPIO_OUT_LOW)
-/* MEC1701H GPIO_0152/GPTP-OUT/KSO16 OK */
-GPIO(USB_C1_CHARGE_EN_L,    PIN(0152),  GPIO_OUT_LOW)
-
-/* Fan PWM output and TACH input. PROCHOT input */
-/* MEC1701H GPIO_0050/FAN_TACH0 OK */
-GPIO(EC_FAN1_TTACH,         PIN(050), GPIO_INPUT | GPIO_PULL_UP)
-/* Fan PWM output - NC / testing only */
-/* MEC1701H GPIO_0053/PWM0 OK */
-GPIO(EC_FAN1_PWM,           PIN(053), GPIO_OUT_LOW)
-/* prochot input from devices */
-/* MEC1701H GPIO_0051/FAN_TACH1 OK */
-GPIO(PLATFORM_EC_PROCHOT,   PIN(051), GPIO_INPUT | GPIO_PULL_UP)
-
-
-/* Miscellaneous */
-/* KB BL PWM, only connected to TP */
-/* MEC1701H GPIO_0002/PWM5 OK */
-GPIO(PWM_KBLIGHT,           PIN(02),   GPIO_OUT_LOW)
-/* MEC1701H GPIO_0041/SYS_SHDN# OK */
-GPIO(ENTERING_RW,           PIN(041),  GPIO_OUT_LOW)
-/* MEC1701H GPIO_0115/PS2_DATA0A OK */
-GPIO(ENABLE_TOUCHPAD,       PIN(0115), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0200/ADC00 OK */
-GPIO(BAT_PRESENT_L,         PIN(0200), GPIO_INPUT)
-/* MEC1701H GPIO_0164/VCI_OVRD_IN OK */
-GPIO(WLAN_OFF_L,            PIN(0164), GPIO_OUT_LOW)
-
-/* From lid sensor */
-/* MEC1701H GPIO_0000/VCI_IN3# OK */
-GPIO(ENABLE_BACKLIGHT,      PIN(00), GPIO_OUT_LOW)
-
-/* Interrupts from accelerometer / gyro -- not yet implemented */
-/*
- * GPIO(ACCEL1_INT,            PIN(0161), GPIO_INPUT)
- * GPIO(ACCEL2_INT,            PIN(0127), GPIO_INPUT)
- * MEC1701H must move. GPIO_0147 is JTAG_CLK
- * GPIO(ACCEL3_INT,            PIN(0147), GPIO_INPUT)
- * GPIO(ACCEL4_INT,            PIN(0126), GPIO_INPUT)
- */
-
-/* MEC1701H GPIO_0011/nSMI OK */
-/* Move to board ver GPIO(PP1800_DX_SENSOR_EN, PIN(011), GPIO_OUT_LOW) */
- /* MEC1701H GPIO_0207/ADC07 OK */
-/* Move to board ver GPIO(PP3300_WLAN_EN, PIN(0207), GPIO_OUT_LOW)*/
-/* MEC1701H GPIO_0114/PS2_CLK0A/nEC_SCI OK */
-/* Move to board version
- * GPIO(PP1800_DX_AUDIO_EN, PIN(0114), GPIO_OUT_LOW)
- */
-
-
-/* Board Version */
-/*
- * MEC1701H
- * GPIO_0130/SMB10_DATA
- * GPIO_0131/SMB10_CLK
- * GPIO_0132/SMB06_DATA
- */
-/*
- * GPIO(BOARD_VERSION1,        PIN(0130),  GPIO_INPUT)
- * GPIO(BOARD_VERSION2,        PIN(0131),  GPIO_INPUT)
- * GPIO(BOARD_VERSION3,        PIN(0132),  GPIO_INPUT)
- */
-GPIO(BOARD_VERSION1,        PIN(0114),  GPIO_INPUT)
-GPIO(BOARD_VERSION2,        PIN(0207),  GPIO_INPUT)
-GPIO(BOARD_VERSION3,        PIN(0011),  GPIO_INPUT)
-
-/*
- * MEC1701H GP-SPI0 chip select is GPIO_0003
- * It is used as GPIO output. GPSPI chip level
- * code drives chip select.
- */
-GPIO(SPI0_CS0,		PIN(03),  GPIO_ODR_HIGH)
-
-
-/*
- * TODO(crosbug.com/p/40848): These LEDs should be under control of the
- * mec1701 LED control unit. Remove these GPIO definitions once the LED
- * control unit is functional.
- */
-/* MEC1701H GPIO_0156/LED0 OK */
-GPIO(CHARGE_LED_1,	PIN(0156), GPIO_OUT_LOW)
-/* MEC1701H GPIO_0157/LED1 OK */
-GPIO(CHARGE_LED_2,	PIN(0157), GPIO_OUT_LOW)
-
-/*
- * MCHP TFDP
- */
-GPIO(TFDP_CLOCK,	PIN(0170), GPIO_INPUT)
-GPIO(TFDP_DATA,		PIN(0171), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-
-/* KB pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-
-/* KB pins */
-/*
- * MEC1704H (144 pin package)
- * KSO00 = GPIO_0040 Func3 bank 1 bit 0
- * KSO01 = GPIO_0045 Func3 bank 1 bit 5
- * KSO02 = GPIO_0046 Func3 bank 1 bit 6
- * KSO03 = GPIO_0047 Func3 bank 1 bit 7
- * KSO04 = GPIO_0107 Func3 bank 2 bit 7
- * KSO05 = GPIO_0112 Func3 bank 2 bit 10
- * KSO06 = GPIO_0113 Func3 bank 2 bit 11
- * KSO07 = GPIO_0120 Func3 bank 2 bit 16
- * KSO08 = GPIO_0121 Func3 bank 2 bit 17
- * KSO09 = GPIO_0122 Func3 bank 2 bit 18
- * KSO10 = GPIO_0123 Func3 bank 2 bit 19
- * KSO11 = GPIO_0124 Func3 bank 2 bit 20
- * KSO12 = GPIO_0125 Func3 bank 2 bit 21
- * For 8x16 test keyboard add KSO13 - KSO15
- * KSO13 = GPIO_0126 Func3 bank 2 bit 22
- * KSO14 = GPIO_0132 Func3 bank 2 bit 26
- * KSO15 = GPIO_0151 Func3 bank 3 bit 9
- *
- * KSI0 = GPIO_0017 Func3 bank 0 bit 15
- * KSI1 = GPIO_0020 Func3 bank 0 bit 16
- * KSI2 = GPIO_0021 Func3 bank 0 bit 17
- * KSI3 = GPIO_0026 Func3 bank 0 bit 22
- * KSI4 = GPIO_0027 Func3 bank 0 bit 23
- * KSI5 = GPIO_0030 Func3 bank 0 bit 24
- * KSI6 = GPIO_0031 Func3 bank 0 bit 25
- * KSI7 = GPIO_0032 Func3 bank 0 bit 26
- */
-/* KSI 0-7, Bank 0, Func3, bits 15-17, 22-26 */
-ALTERNATE(PIN_MASK(0, 0x07C38000), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-
-/* KSO 0-3 Bank 1, Func3, bits 0, 5-7 */
-ALTERNATE(PIN_MASK(1, 0xE1), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-/* KSO 4-12, Bank 2, Func3, bits 7, 10-11, 16-21 */
-ALTERNATE(PIN_MASK(2, 0x003F0C80), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-/* Add KSO13-15 for 8x16 test matrix */
-/* KSO 13-14, Bank 2, Func3, bits 22, 26 */
-/*ALTERNATE(PIN_MASK(2, 0x04400000), 3, MODULE_KEYBOARD_SCAN, \
- * GPIO_KB_OUTPUT)
- */
-/* KSO 15, Bank 3, Func3, bit 9 */
-/*ALTERNATE(PIN_MASK(3, 0x00000200), 3, MODULE_KEYBOARD_SCAN, \
- * GPIO_KB_OUTPUT)
- */
-
-/* eSPI pins */
-/* ESPI_RESET# - GPIO_0061 Function 2, Bank 1 bit[17] */
-ALTERNATE(PIN_MASK(1, 0x20000), 2, MODULE_LPC, 0)
-/* ESPI_ALERT# - GPIO_0063 Function 2, Bank 1 bit[19] */
-ALTERNATE(PIN_MASK(1, 0x80000), 2, MODULE_LPC, 0)
-/* ESPI_CS# - GPIO_0066 Function 2, Bank 1 bit[22] */
-ALTERNATE(PIN_MASK(1, 0x400000), 2, MODULE_LPC, 0)
-/* ESPI_CLK - GPIO_0065 Function 2, Bank 1 bit[21] */
-ALTERNATE(PIN_MASK(1, 0x200000), 2, MODULE_LPC, 0)
-/* ESPI_IO{0,1,2,3} - GPIO_0070-GPIO_0073 Function 2, Bank 1 bits[24:27] */
-ALTERNATE(PIN_MASK(1, 0xf000000), 2, MODULE_LPC, 0)
-
-/* LPC LRESET# GPIO_0064/LRESET#
- * Function 1, Bank 1 bit[20] */
-ALTERNATE(PIN_MASK(1, 0x100000), 1, MODULE_LPC, GPIO_PULL_UP)
-
-/*
- * MEC1701H GP-SPI0 Master
- * SPI0_CS# = GPIO_0003 Func 0(GPIO) Bank 0, bit 3
- * SPI0_CLK = GPIO_0034 Func 2	Bank 0, bit 28
- * SPI0_MISO = GPIO_0036 Func 2	Bank 0, bit 30
- * SPI0_MOSI = GPIO_0004 Func 2	Bank 0, bit 4
- */
-ALTERNATE(PIN_MASK(0,  0x00000008), 0, MODULE_SPI_CONTROLLER, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(0,  0x50000010), 2, MODULE_SPI_CONTROLLER, 0)
-
-/* I2C pins */
-/* Using SMB00 as function 2 GP-SPI0
- * SMB00_DAT - GPIO_0003 Func1, SMB00_CLK - GPIO_0004 Func1
- * SMB03_DAT - GPIO_0007 Func1, SMB03_CLK - GPIO_0010 Func1
- * Bank 0 bits[3:4,7:8]
-*/
-/* ALTERNATE(PIN_MASK(0,  0x0198), 1, MODULE_I2C, GPIO_ODR_HIGH) */
-ALTERNATE(PIN_MASK(0,  0x0180), 1, MODULE_I2C, GPIO_ODR_HIGH)
-
-/*
- * SMB05_DAT - GPIO_0141 Func1, SMB05_CLK - GPIO_0142 Func1
- * SMB04_DAT - GPIO_0143 Func1, SMB04_CLK - GPIO_0144 Func1
- * SMB02_DAT - GPIO_0154 Func1, SMB02_CLK - GPIO_0155 Func1
- * Bank 3 bits[1:4,12:13]
-*/
-ALTERNATE(PIN_MASK(3,  0x301e), 1, MODULE_I2C, GPIO_ODR_HIGH)
-
-/* ADC pins */
-/* ADC01 - GPIO_0201 / PPVAR_BOOSTIN_SENSE. Func1 Bank 4 bit[1]
- * ADC03 - GPIO_0203 / IADP_ACMON_BMON. Func1 Bank 4 bit[3]
- * ADC04 - GPIO_0204 / PMON_PSYS. Func1 Bank 4 bit[4]
- * ADC07 - GPIO_0207 / Thermistor call it ADC_CASE
- */
-ALTERNATE(PIN_MASK(4,  0x009a), 1, MODULE_ADC, GPIO_ANALOG)
-
-/* LED0 - GPIO_0156 Func1 Bank 3 bit[14]
- * LED1 - GPIO_0157 Func1 Bank 3 bit[15]
- */
-ALTERNATE(PIN_MASK(3, 0xc000), 1, MODULE_POWER_LED, 0)
-
-/*
- * nRESET_OUT functionality is PWROK signal from MEC1701H
- * nRESET_OUT - GPIO121 Bank 2 bit[17]
- * MEC1701H nRESET_OUT is GPIO_0106/PWROK func1
- * Bank 2 bit[6]
- */
-/*
- * Not using nRESET_OUT on Kabylake RVP3 plus MEC170x EVB
- * ALTERNATE(PIN_MASK(2, 0x40), 1, MODULE_PMU, 0)
- */
-
-/*
- * MCHP TFDP alternate function configuration
- * GPIO 0170 = clock, 0171 = data both function 1
- * Port = 3 bits[24:25]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_TFDP, 0)
diff --git a/board/mchpevb1/led.c b/board/mchpevb1/led.c
deleted file mode 100644
index 7b9f7646cb..0000000000
--- a/board/mchpevb1/led.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for MEC1701 EVB.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
-#define LOW_BATTERY_PERCENTAGE 10
-
-#define LED_TOTAL_4SECS_TICKS 4
-#define LED_TOTAL_2SECS_TICKS 2
-#define LED_ON_1SEC_TICKS 1
-#define LED_ON_2SECS_TICKS 2
-
-/*
- * NOTE: GPIO_BAT_LED_xxx defined in board.h
- */
-
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_AMBER,
-	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int bat_led_set_color(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		break;
-	case LED_RED:
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		break;
-	case LED_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id,
-		uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-}
-
-static int board_led_set_color_battery(enum led_color color)
-{
-	return bat_led_set_color(color);
-}
-
-static int board_led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	led_auto_control(led_id, 0);
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = board_led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED] != 0 &&
-	    brightness[EC_LED_COLOR_GREEN] != 0)
-		board_led_set_color(led_id, LED_AMBER);
-	else if (brightness[EC_LED_COLOR_RED] != 0)
-		board_led_set_color(led_id, LED_RED);
-	else if (brightness[EC_LED_COLOR_GREEN] != 0)
-		board_led_set_color(led_id, LED_GREEN);
-	else
-		board_led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-#ifdef CONFIG_CHARGER
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/* BAT LED behavior:
-	 * Same as the chromeos spec
-	 * Green/Amber for CHARGE_FLAG_FORCE_IDLE
-	 */
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		board_led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* Less than 3%, blink one second every two second */
-		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
-			board_led_set_color_battery(
-				(battery_ticks % LED_TOTAL_2SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
-		/* Less than 10%, blink one second every four seconds */
-		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < LOW_BATTERY_PERCENTAGE)
-			board_led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
-		else
-			board_led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		board_led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_RED : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		board_led_set_color_battery(LED_GREEN);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			board_led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_GREEN : LED_AMBER);
-		else
-			board_led_set_color_battery(LED_GREEN);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-#endif
-}
-
-
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/mchpevb1/lfw/vif_override.xml b/board/mchpevb1/lfw/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/mchpevb1/lfw/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/mchpevb1/usb_pd_policy.c b/board/mchpevb1/usb_pd_policy.c
deleted file mode 100644
index 690f8b8a3c..0000000000
--- a/board/mchpevb1/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
-			      GPIO_USB_C0_CHARGE_EN_L, 1);
-	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
-				      GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
diff --git a/board/meep/battery.c b/board/meep/battery.c
deleted file mode 100644
index ca9fc531b3..0000000000
--- a/board/meep/battery.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all meep battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack Coslight Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack SDI Battery Information */
-	[BATTERY_DYNAPACK_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-24-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo Coslight Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo ATL Battery Information */
-	[BATTERY_SIMPLO_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-17-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/meep/board.c b/board/meep/board.c
deleted file mode 100644
index daac19a89a..0000000000
--- a/board/meep/board.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Meep/Mimrock board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-#ifdef CONFIG_KEYBOARD_KEYPAD
-#error "KSO_14 was repurposed to PPC_ID pin so CONFIG_KEYBOARD_KEYPAD \
-should not be defined."
-#endif
-
-static uint8_t sku_id;
-static int c0_port_ppc;
-static int c1_port_ppc;
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		if (c0_port_ppc == PPC_SYV682X)
-			syv682x_interrupt(0);
-		else
-			nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		if (c1_port_ppc == PPC_SYV682X)
-			syv682x_interrupt(1);
-		else
-			nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_standrd_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standrd_ref,
-		.default_range = 2, /* g */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*
- * Returns 1 for boards that are convertible into tablet mode, and
- * zero for clamshells.
- */
-int board_is_convertible(void)
-{
-	/*
-	 * Meep: 1, 2, 3, 4
-	 * Vortininja: 49, 50, 51, 52
-	 * Unprovisioned: 255
-	 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 ||
-	       sku_id == 4 || sku_id == 49 || sku_id == 50 ||
-	       sku_id == 51 || sku_id == 52 || sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static int get_ppc_port_config(uint32_t board_version, int port)
-{
-	switch (port) {
-	/*
-	 * Meep C0 port PPC was configrated by PPC ID pin only.
-	 */
-	case USB_PD_PORT_TCPC_0:
-		if ((board_version >= 6) && gpio_get_level(GPIO_PPC_ID))
-			return PPC_SYV682X;
-		else
-			return PPC_NX20P348X;
-	/*
-	 * Meep C1 port PPC was configrated by PPC ID pin or SSFC,
-	 * The first of all we should check SSFC with priority one,
-	 * then check PPC ID if board is unalbe to get SSFC.
-	 */
-	case USB_PD_PORT_TCPC_1:
-		switch (get_cbi_ssfc_ppc_p1()) {
-		case SSFC_PPC_P1_DEFAULT:
-			if ((board_version >= 6) && gpio_get_level(GPIO_PPC_ID))
-				return PPC_SYV682X;
-			else
-				return PPC_NX20P348X;
-		case SSFC_PPC_P1_SYV682X:
-			return PPC_SYV682X;
-		case SSFC_PPC_P1_NX20P348X:
-		default:
-			return PPC_NX20P348X;
-		}
-	default:
-		return PPC_NX20P348X;
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS)
-		ccprints("Board Version: %d", val);
-
-	c0_port_ppc = get_ppc_port_config(val, USB_PD_PORT_TCPC_0);
-	c1_port_ppc = get_ppc_port_config(val, USB_PD_PORT_TCPC_1);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate_late(void)
-{
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * We always compile in backlight support for Meep/Dorp, but only some
-	 * SKUs come with the hardware. Therefore, check if the current
-	 * device is one of them and return the default value - with backlight
-	 * here.
-	 */
-	if (sku_id == 34 || sku_id == 36)
-		return flags0;
-
-	/* Report that there is no keyboard backlight */
-	return (flags0 &= ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-}
-
-__override uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Meep variant doesn't have ps8xxx product in the port 0 */
-	if (port == 0)
-		return 0;
-
-	switch (get_cbi_ssfc_tcpc_p1()) {
-	case SSFC_TCPC_P1_PS8755:
-		return PS8755_PRODUCT_ID;
-	case SSFC_TCPC_P1_DEFAULT:
-	case SSFC_TCPC_P1_PS8751:
-	default:
-		return PS8751_PRODUCT_ID;
-	}
-}
-
-static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static void board_setup_ppc(void)
-{
-	if (c0_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-			   &ppc_syv682x_port0,
-			   sizeof(struct ppc_config_t));
-
-		gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
-	}
-
-	if (c1_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-			   &ppc_syv682x_port1,
-			   sizeof(struct ppc_config_t));
-
-		gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
-
-	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
-}
diff --git a/board/meep/board.h b/board/meep/board.h
deleted file mode 100644
index 013237e2d7..0000000000
--- a/board/meep/board.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Meep/Mimrock board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LED_COMMON
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Additional PPC second source */
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#undef CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-
-/* Additional TCPC second source in Port 1 */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_SDI,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_ATL,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_TYPE_COUNT,
-};
-
-enum ppc_type {
-	PPC_NX20P348X,
-	PPC_SYV682X,
-	PPC_TYPE_COUNT,
-};
-
-int board_is_convertible(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/meep/build.mk b/board/meep/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/meep/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/meep/ec.tasklist b/board/meep/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/meep/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc
deleted file mode 100644
index ebb69bdf53..0000000000
--- a/board/meep/gpio.inc
+++ /dev/null
@@ -1,197 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,  PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)	/* EN_PP3300_TRACKPAD_ODL */
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_AMBER_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_WHITE_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(PWR_LED_WHITE_L,	 PIN(D, 7), GPIO_OUT_HIGH)	/* LED_3_L */
-
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	 PIN(6, 2), GPIO_OUT_LOW)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,       PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP) /* GPO66_ARM_L_X86 */
-GPIO(GPOB6_NC,       PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP) /* EC_GP_SEL_ODL */
-
-/* Misc */
-GPIO(CCD_MODE_EC_L,   	   PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL, PIN(9, 3), GPIO_INPUT)
-GPIO(EC_GPIO_03,	   PIN(0, 3), GPIO_INPUT)	/* TP only */
-GPIO(PPC_ID,		   PIN(8, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* PPC ID pin */
-
-/* Unused pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_WOV_DMIC_DATA,	PIN(9, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)					/* EC_KSO_02_INV */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)		/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)		/* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/meep/led.c b/board/meep/led.c
deleted file mode 100644
index 5494f11361..0000000000
--- a/board/meep/led.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Meep/Mimrock
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "hooks.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Meep: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_WHITE, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-static void s3_led_init(void)
-{
-	if (!board_is_convertible()) {
-		led_bat_state_table[STATE_DISCHARGE_S3][LED_PHASE_0].color =
-			EC_LED_COLOR_WHITE;
-		led_bat_state_table[STATE_DISCHARGE_S3][LED_PHASE_0].time =
-			1 * LED_ONE_SEC;
-
-		led_bat_state_table[STATE_DISCHARGE_S3][LED_PHASE_1].color =
-			LED_OFF;
-		led_bat_state_table[STATE_DISCHARGE_S3][LED_PHASE_1].time =
-			1 * LED_ONE_SEC;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, s3_led_init, HOOK_PRIO_DEFAULT);
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/meep/vif_override.xml b/board/meep/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/meep/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/metaknight/battery.c b/board/metaknight/battery.c
deleted file mode 100644
index 943771ffa4..0000000000
--- a/board/metaknight/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all metaknight battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo PC-VP-BP44 Battery Information */
-	[BATTERY_SMP_PCVPBP144] = {
-		.fuel_gauge = {
-			.manuf_name  = "SIMPLO",
-			.device_name = "PC-VP-BP144",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr       = 0x00,
-				.reg_mask       = 0x10,
-				.disconnect_val = 0x00,
-				.cfet_mask      = 0x08,
-				.cfet_off_val   = 0x00,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 13050,  /* mV */
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 128,    /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_PCVPBP144;
diff --git a/board/metaknight/board.c b/board/metaknight/board.c
deleted file mode 100644
index 8f54536d7f..0000000000
--- a/board/metaknight/board.c
+++ /dev/null
@@ -1,906 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* metaknight board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/nb7v904m.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-static uint8_t new_adc_key_state;
-
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-	GPIO_EN_USB_A1_VBUS,
-};
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_HDMI_HPD_SUB_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-
-	cprints(CC_SYSTEM, "HDMI plug-%s", !hdmi_hpd_odl ? "in" : "out");
-}
-
-/**
- * Handle debounced pen input changing state.
- */
-static void pen_input_deferred(void)
-{
-	int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) &&
-			!chipset_in_state(CHIPSET_STATE_ANY_OFF);
-
-	if (pen_charge_enable)
-		gpio_set_level(GPIO_EN_PP3300_PEN, 1);
-	else
-		gpio_set_level(GPIO_EN_PP3300_PEN, 0);
-
-	CPRINTS("Pen charge %sable", pen_charge_enable ? "en" : "dis");
-}
-DECLARE_DEFERRED(pen_input_deferred);
-
-void pen_input_interrupt(enum gpio_signal signal)
-{
-	/* pen input debounce time */
-	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
-}
-
-static void pen_charge_check(void)
-{
-	hook_call_deferred(&pen_input_deferred_data, (100 * MSEC));
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST);
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-
-	[TEMP_SENSOR_MEMORY] = {
-		.name = "Memory",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_51k1_47k_4050b,
-		.idx  = ADC_TEMP_SENSOR_1
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_51k1_47k_4050b,
-		.idx  = ADC_TEMP_SENSOR_2
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_memory = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_MEMORY] = thermal_memory;
-	thermal_params[TEMP_SENSOR_CPU]    = thermal_cpu;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-#ifdef BOARD_WADDLEDOO
-static void reconfigure_5v_gpio(void)
-{
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (system_get_board_version() < 0) {
-		CPRINTS("old board - remapping 5V en");
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
-#endif /* BOARD_WADDLEDOO */
-
-static void set_5v_gpio(int level)
-{
-	int version;
-	enum gpio_signal gpio = GPIO_EN_PP5000;
-
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (IS_ENABLED(BOARD_WADDLEDOO)) {
-		version = system_get_board_version();
-
-		/*
-		 * If the CBI EEPROM wasn't formatted, assume it's a very early
-		 * board.
-		 */
-		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
-	}
-
-	gpio_set_level(gpio, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC, or send enable signal to HDMI
-	 * DB.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
-		get_cbi_fw_config_db() == DB_LTE_HDMI) {
-		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
-	}
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_lsm6dsm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct kionix_accel_data g_kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-static struct icm_drv_data_t g_icm426xx_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t lsm6dsm_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DS3,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.rot_standard_ref = &base_lsm6dsm_ref,
-	.default_range = 4,  /* g */
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t lsm6dsm_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DS3,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	.rot_standard_ref = &base_lsm6dsm_ref,
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-};
-
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, enough for laptop */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-static int base_gyro_config;
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
-		get_cbi_fw_config_db() == DB_LTE_HDMI) {
-		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C, GPIO_HDMI_HPD_SUB_ODL, 0);
-		gpio_config_pin(MODULE_I2C, GPIO_GPIO92_NC, 0);
-
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
-
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-
-		/* Enable interrupt for passing through HPD */
-		gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
-	} else {
-		/* Set SDA as an input */
-		gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL,
-			       GPIO_INPUT);
-	}
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Enable gpio interrupt for pen detect */
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize g-sensor */
-	base_gyro_config = get_cbi_ssfc_base_sensor();
-
-	if (base_gyro_config == SSFC_SENSOR_LSM6DSM) {
-		motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
-		motion_sensors[BASE_GYRO]  = lsm6dsm_base_gyro;
-		cprints(CC_SYSTEM, "SSFC: BASE GYRO is LSM6DSM");
-	} else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO]  = icm426xx_base_gyro;
-		cprints(CC_SYSTEM, "SSFC: BASE GYRO is ICM426XX");
-	} else
-		cprints(CC_SYSTEM, "SSFC: BASE GYRO is BMI160");
-
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-		cprints(CC_SYSTEM, "SSFC: LID ACCEL is KX022");
-	} else
-		cprints(CC_SYSTEM, "SSFC: LID ACCEL is BMA253");
-
-	/* Initial thermal */
-	setup_thermal();
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-int adc_to_physical_value(enum gpio_signal gpio)
-{
-	if (gpio == GPIO_VOLUME_UP_L)
-		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
-	else if (gpio == GPIO_VOLUME_DOWN_L)
-		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
-
-	CPRINTS("Not a volume up or down key");
-	return 0;
-}
-
-int button_is_adc_detected(enum gpio_signal gpio)
-{
-	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
-}
-
-static void adc_vol_key_press_check(void)
-{
-	int volt = adc_read_channel(ADC_SUB_ANALOG);
-	static uint8_t old_adc_key_state;
-	uint8_t adc_key_state_change;
-
-	if (volt > 2400 && volt < 2540) {
-		/* volume-up is pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK;
-	} else if (volt > 2600 && volt < 2740) {
-		/* volume-down is pressed */
-		new_adc_key_state = ADC_VOL_DOWN_MASK;
-	} else if (volt < 2300) {
-		/* both volumn-up and volume-down are pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
-	} else if (volt > 2780) {
-		/* both volumn-up and volume-down are released */
-		new_adc_key_state = 0;
-	}
-	if (new_adc_key_state != old_adc_key_state) {
-		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
-		if (adc_key_state_change && ADC_VOL_UP_MASK)
-			button_interrupt(GPIO_VOLUME_UP_L);
-		if (adc_key_state_change && ADC_VOL_DOWN_MASK)
-			button_interrupt(GPIO_VOLUME_DOWN_L);
-
-		old_adc_key_state = new_adc_key_state;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-#ifndef TEST_BUILD
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case SSFC_SENSOR_LSM6DSM:
-		lsm6dsm_interrupt(signal);
-		break;
-	case SSFC_SENSOR_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case SSFC_SENSOR_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		"eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-		GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL,
-		GPIO_EC_I2C_BATTERY_SDA
-	},
-
-	{
-		"sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-		GPIO_EC_I2C_SENSOR_SDA
-	},
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL,
-		GPIO_EC_I2C_USB_C0_SDA
-	},
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		"sub_usbc1", I2C_PORT_SUB_USB_C1, 1000,
-		GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
-#endif
-};
-
-#endif
diff --git a/board/metaknight/board.h b/board/metaknight/board.h
deleted file mode 100644
index c8c6b6e0e6..0000000000
--- a/board/metaknight/board.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* metaknight board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
-
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_NB7V904M
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/*
- * I2C pin names for baseboard
- *
- * Note: these lines will be set as i2c on start-up, but this should be
- * okay since they're ODL.
- */
-#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_GPIO92_NC
-#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_HDMI_HPD_SUB_ODL
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_BMA255         /* Lid accel */
-#define CONFIG_ACCEL_KX022          /* Lid accel second source */
-#define CONFIG_ACCELGYRO_BMI160     /* Base accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel second source */
-#define CONFIG_ACCELGYRO_ICM426XX   /* Base accel second source */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Volume Button feature */
-#define CONFIG_ADC_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifdef BOARD_METAKNIGHT_LEGACY
-/* this change saves 1656 bytes of RW flash space */
-#define CONFIG_CHIP_INIT_ROM_REGION
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#else
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_MEMORY,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_COUNT,
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP_PCVPBP144,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/metaknight/build.mk b/board/metaknight/build.mk
deleted file mode 100644
index cd002a20e7..0000000000
--- a/board/metaknight/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/metaknight/cbi_ssfc.c b/board/metaknight/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/metaknight/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/metaknight/cbi_ssfc.h b/board/metaknight/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/metaknight/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/metaknight/ec.tasklist b/board/metaknight/ec.tasklist
deleted file mode 100644
index dc4065cf98..0000000000
--- a/board/metaknight/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/metaknight/gpio.inc b/board/metaknight/gpio.inc
deleted file mode 100644
index dee2e2dadf..0000000000
--- a/board/metaknight/gpio.inc
+++ /dev/null
@@ -1,152 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(PEN_DET_ODL,    PIN(5, 0), GPIO_INT_BOTH, pen_input_interrupt)
-GPIO_INT(HDMI_HPD_SUB_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* HDMI_HPD */
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-
-/* Extra Sub-board I/O pins */
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,				PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,			PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,			PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,			PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,				PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,				PIN(D, 3), GPIO_ODR_LOW)
-GPIO(ECH1_PACKET_MODE,			PIN(7, 5), GPIO_OUT_LOW)
-GPIO(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_ODR_LOW)/* 5V power en */
-
-/* LED */
-GPIO(LED_W_ODL,         PIN(C, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN) /* LED White */
-GPIO(LED_Y_ODL,         PIN(C, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN) /* LED Amber */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-
-/*
- * metaknight doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO92_NC, PIN(9, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC2_NC, PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/metaknight/led.c b/board/metaknight/led.c
deleted file mode 100644
index 10edf9068e..0000000000
--- a/board/metaknight/led.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Metaknight
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_W_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_Y_ODL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_W_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_Y_ODL, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_W_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_Y_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
-
-
diff --git a/board/metaknight/usb_pd_policy.c b/board/metaknight/usb_pd_policy.c
deleted file mode 100644
index 3190595596..0000000000
--- a/board/metaknight/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/metaknight/vif_override.xml b/board/metaknight/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/metaknight/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/minimuffin b/board/minimuffin
deleted file mode 120000
index caf3ff6e0a..0000000000
--- a/board/minimuffin
+++ /dev/null
@@ -1 +0,0 @@
-zinger/
\ No newline at end of file
diff --git a/board/moonball b/board/moonball
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/moonball
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/moonbuggy/board.c b/board/moonbuggy/board.c
deleted file mode 100644
index 8322f2ef82..0000000000
--- a/board/moonbuggy/board.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/ina3221.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_common.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-static uint8_t usbc_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1500)
-#define PWR_FRONT_LOW	(5*900)
-#define PWR_REAR	(5*1500)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (usbc_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"pse",     I2C_PORT_PSE,     400, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CORE] = {
-		.name = "Core",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 5300,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(89),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	/*
-	 * For board version < 2, the directly connected recovery
-	 * button is not available.
-	 */
-	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-int extpower_is_present(void)
-{
-	/* genesis: If the EC is running, then there is external power */
-	return 1;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	return 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-}
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-	} else {
-		delay = POWER_DELAY_MS * MSEC;
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A3_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
diff --git a/board/moonbuggy/board.h b/board/moonbuggy/board.h
deleted file mode 100644
index 23ad02dc4d..0000000000
--- a/board/moonbuggy/board.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-/* TODO: (b/143496253) re-enable CEC */
-/* #define CONFIG_CEC */
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_S0IX_FAILURE_DETECTION
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 0
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are five ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_PSE		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
-
-/* Board specific handlers */
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/moonbuggy/build.mk b/board/moonbuggy/build.mk
deleted file mode 100644
index 0acd315b39..0000000000
--- a/board/moonbuggy/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-y+=led.o
-board-y+=pse.o
diff --git a/board/moonbuggy/ec.tasklist b/board/moonbuggy/ec.tasklist
deleted file mode 100644
index 3828142c55..0000000000
--- a/board/moonbuggy/ec.tasklist
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/moonbuggy/gpio.inc b/board/moonbuggy/gpio.inc
deleted file mode 100644
index 6a905fdf04..0000000000
--- a/board/moonbuggy/gpio.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/*
- * Directly connected recovery button (not available on some boards).
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP)
-
-/* Port power control interrupts */
-GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A3_LOW_PWR_OD,        PIN(5, 0), GPIO_ODR_LOW)
-GPIO(USB_A1_STATUS_L,          PIN(6, 1), GPIO_INPUT)
-GPIO(USB_A2_STATUS_L,          PIN(C, 7), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,          PIN(D, 2), GPIO_INPUT)
-
-/* USB type C */
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
-
-/* TPU */
-GPIO(PP3300_TPU_EN,            PIN(E, 4), GPIO_OUT_HIGH)
-
-/* PSE controller */
-GPIO(EC_PSE_PWM_INT,           PIN(B, 0), GPIO_INPUT)		/* PSE controller interrupt */
-GPIO(EC_RST_LTC4291_L,         PIN(9, 6), GPIO_OUT_HIGH)	/* PSE controller reset */
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-
-/* HDMI/CEC */
-GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
-GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_LTC_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_LTC_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                  /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* Unused pins */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(8, 0))						/* LED_BLUE_L */
-UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(9, 2))						/* K8  NC */
-UNUSED(PIN(9, 1))						/* L8  NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(C, 6))						/* B11 NC */
-UNUSED(PIN(E, 2))						/* B8  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(3, 2))						/* E5  NC */
-UNUSED(PIN(D, 6))						/* F6  NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(9, 3))						/* M11 NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/moonbuggy/led.c b/board/moonbuggy/led.c
deleted file mode 100644
index a9f70d2d40..0000000000
--- a/board/moonbuggy/led.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		red = 1;
-		white = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec.
- */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task.
-	 */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_resume();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_suspend();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		led_shutdown();
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/moonbuggy/pse.c b/board/moonbuggy/pse.c
deleted file mode 100644
index 1c1b6bb41b..0000000000
--- a/board/moonbuggy/pse.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE)
- * controller.
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "string.h"
-#include "timer.h"
-#include "util.h"
-
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
-
-#define I2C_PSE_READ(reg, data) \
-	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define I2C_PSE_WRITE(reg, data) \
-	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static int pse_write_hpmd(int port, int val)
-{
-	switch (port) {
-	case 0:
-		return I2C_PSE_WRITE(HPMD1, val);
-	case 1:
-		return I2C_PSE_WRITE(HPMD2, val);
-	case 2:
-		return I2C_PSE_WRITE(HPMD3, val);
-	case 3:
-		return I2C_PSE_WRITE(HPMD4, val);
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-/*
- * Port 1: 100W
- * Port 2-4: 15W
- */
-static int pse_port_hpmd[4] = {
-	LTC4291_HPMD_MAX,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-	LTC4291_HPMD_MIN,
-};
-
-static int pse_port_enable(int port)
-{
-	/* Enable detection and classification */
-	return I2C_PSE_WRITE(DETPB, LTC4291_DETPB_EN_PORT(port));
-}
-
-static int pse_port_disable(int port)
-{
-	/* Request power off (this also disables detection/classification) */
-	return I2C_PSE_WRITE(PWRPB, LTC4291_PWRPB_OFF_PORT(port));
-}
-
-static int pse_init_worker(void)
-{
-	timestamp_t deadline;
-	int err, id, devid, statpin, port;
-
-	/* Ignore errors -- may already be resetting */
-	I2C_PSE_WRITE(RSTPB, LTC4291_FLD_RSTPB_RSTALL);
-
-	deadline.val = get_time().val + LTC4291_RESET_DELAY_US;
-	while ((err = I2C_PSE_READ(ID, &id)) != 0) {
-		if (timestamp_expired(deadline, NULL))
-			return err;
-	}
-
-	err = I2C_PSE_READ(DEVID, &devid);
-	if (err != 0)
-		return err;
-
-	if (id != LTC4291_ID || devid != LTC4291_DEVID)
-		return EC_ERROR_INVAL;
-
-	err = I2C_PSE_READ(STATPIN, &statpin);
-	if (err != 0)
-		return err;
-
-	/*
-	 * We don't want to supply power until we've had a chance to set the
-	 * limits.
-	 */
-	if (statpin & LTC4291_FLD_STATPIN_AUTO)
-		CPRINTS("WARN: PSE reset in AUTO mode");
-
-	err = I2C_PSE_WRITE(OPMD, LTC4291_OPMD_AUTO);
-	if (err != 0)
-		return err;
-
-	/* Set maximum power each port is allowed to allocate. */
-	for (port = 0; port < LTC4291_PORT_MAX; port++) {
-		err = pse_write_hpmd(port, pse_port_hpmd[port]);
-		if (err != 0)
-			return err;
-	}
-
-	err = I2C_PSE_WRITE(DISENA, LTC4291_DISENA_ALL);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_WRITE(DETENA, LTC4291_DETENA_ALL);
-	if (err != 0)
-		return err;
-
-	return 0;
-}
-
-static void pse_init(void)
-{
-	int err;
-
-	err = pse_init_worker();
-	if (err != 0)
-		CPRINTS("PSE init failed: %d", err);
-	else
-		CPRINTS("PSE init done");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
-
-/* Also reset the PSE on a reboot to toggle the power. */
-DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
-
-static int command_pse(int argc, char **argv)
-{
-	int port;
-
-	/*
-	 *  TODO(b/156399232): endeavour: PSE controller reset by PLTRST
-	 *
-	 *  Initialization does not reliably work after reset because the device
-	 *  is held in reset by the AP. Running this command after boot finishes
-	 *  always succeeds. Remove once the reset signal changes.
-	 */
-	if (!strncmp(argv[1], "init", 4))
-		return pse_init_worker();
-
-	if (argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if (port < 0 || port >= LTC4291_PORT_MAX)
-		return EC_ERROR_PARAM1;
-
-	if (!strncmp(argv[2], "off", 3))
-		return pse_port_disable(port);
-	else if (!strncmp(argv[2], "on", 2))
-		return pse_port_enable(port);
-	else if (!strncmp(argv[2], "min", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MIN);
-	else if (!strncmp(argv[2], "max", 3))
-		return pse_write_hpmd(port, LTC4291_HPMD_MAX);
-	else
-		return EC_ERROR_PARAM2;
-}
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
-			"Set PSE port power");
-
-static int ec_command_pse_status(int port, uint8_t *status)
-{
-	int detena, statpwr;
-	int err;
-
-	err = I2C_PSE_READ(DETENA, &detena);
-	if (err != 0)
-		return err;
-
-	err = I2C_PSE_READ(STATPWR, &statpwr);
-	if (err != 0)
-		return err;
-
-	if ((detena & LTC4291_DETENA_EN_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_DISABLED;
-	else if ((statpwr & LTC4291_STATPWR_ON_PORT(port)) == 0)
-		*status = EC_PSE_STATUS_ENABLED;
-	else
-		*status = EC_PSE_STATUS_POWERED;
-
-	return 0;
-}
-
-static enum ec_status ec_command_pse(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pse *p = args->params;
-	int err = 0;
-
-	if (p->port >= LTC4291_PORT_MAX)
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->cmd) {
-	case EC_PSE_STATUS: {
-		struct ec_response_pse_status *r = args->response;
-
-		args->response_size = sizeof(*r);
-		err = ec_command_pse_status(p->port, &r->status);
-		break;
-	}
-	case EC_PSE_ENABLE:
-		err = pse_port_enable(p->port);
-		break;
-	case EC_PSE_DISABLE:
-		err = pse_port_disable(p->port);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (err)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSE, ec_command_pse, EC_VER_MASK(0));
diff --git a/board/morphius/analyzestack.yaml b/board/morphius/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/morphius/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/morphius/battery.c b/board/morphius/battery.c
deleted file mode 100644
index 6d8a8190b2..0000000000
--- a/board/morphius/battery.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Morphius battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP SB10x63140 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000,  /* mV */
-			.precharge_current	= 332,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7680, /* mV */
-			.voltage_min		= 6000,  /* mV */
-			.precharge_current	= 333,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LG L19L4PG2  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-};
-
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
diff --git a/board/morphius/board.c b/board/morphius/board.c
deleted file mode 100644
index 48712ffb0c..0000000000
--- a/board/morphius/board.c
+++ /dev/null
@@ -1,890 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Morphius board configuration */
-
-#include "adc.h"
-#include "battery_smart.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charger.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/pi3dpx1207.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "hooks.h"
-#include "keyboard_8042.h"
-#include "lid_switch.h"
-#include "mkbp_event.h"
-#include "power.h"
-#include "power_button.h"
-#include "ps2_chip.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usb_charge.h"
-#include "usbc_ppc.h"
-
-static void hdmi_hpd_interrupt_v2(enum ioex_signal signal);
-static void hdmi_hpd_interrupt_v3(enum gpio_signal signal);
-static void board_gmr_tablet_switch_isr(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-static bool support_aoz_ppc;
-static bool ignore_c1_dp;
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t base_standard_ref_1 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = (const mat33_fp_t *)&lid_standard_ref,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = (const mat33_fp_t *)&base_standard_ref,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = (const mat33_fp_t *)&base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_standard_ref_1,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_1,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-	[PWM_CH_POWER_LED] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS7,
-};
-
-/*****************************************************************************
- * Base Gyro Sensor dynamic configuration
- */
-static enum ec_cfg_base_gyro_sensor_type base_gyro_config;
-
-enum ec_cfg_base_gyro_sensor_type get_base_gyro_sensor(void)
-{
-	switch (get_cbi_ssfc_base_sensor()) {
-	case SSFC_BASE_GYRO_NONE:
-		return ec_config_has_base_gyro_sensor();
-	default:
-		return get_cbi_ssfc_base_sensor();
-	}
-}
-
-static void setup_base_gyro_config(void)
-{
-	base_gyro_config = get_base_gyro_sensor();
-
-	switch (base_gyro_config) {
-	case BASE_GYRO_BMI160:
-		ccprints("BASE GYRO is BMI160");
-		break;
-	case BASE_GYRO_ICM426XX:
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE GYRO is ICM426XX");
-		break;
-	default:
-		break;
-	}
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (base_gyro_config) {
-	case BASE_GYRO_BMI160:
-		bmi160_interrupt(signal);
-		break;
-	case BASE_GYRO_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	default:
-		break;
-	}
-}
-
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration
- */
-static void setup_mux(void)
-{
-	if (ec_config_has_usbc1_retimer_ps8802()) {
-		ccprints("C1 PS8802 detected");
-
-		/*
-		 * Main MUX is PS8802, secondary MUX is modified FP5
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
-
-		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-
-		/* Don't have the AMD FP5 flip */
-		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
-
-	} else if (ec_config_has_usbc1_retimer_ps8818()) {
-		ccprints("C1 PS8818 detected");
-
-		/*
-		 * Main MUX is FP5, secondary MUX is PS8818
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-
-		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-	}
-}
-
-const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
-	[USBC_PORT_C0] = {
-		.enable_gpio = IOEX_USB_C0_DATA_EN,
-		.dp_enable_gpio = GPIO_USB_C0_IN_HPD,
-	},
-	[USBC_PORT_C1] = {
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
-
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
-	},
-	[USBC_PORT_C1] = {
-		/* Filled in dynamically at startup */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/*****************************************************************************
- * Use FW_CONFIG to set correct configuration.
- */
-static uint32_t board_ver;
-enum gpio_signal gpio_ec_ps2_reset = GPIO_EC_PS2_RESET_V1;
-int board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB_V1;
-
-static void setup_v0_charger(void)
-{
-	cbi_get_board_version(&board_ver);
-
-	if (board_ver <= 2)
-		chg_chips[0].i2c_port = I2C_PORT_CHARGER_V0;
-}
-/*
- * Use HOOK_PRIO_INIT_I2C so we re-map before charger_chips_init()
- * talks to the charger.
- */
-DECLARE_HOOK(HOOK_INIT, setup_v0_charger, HOOK_PRIO_INIT_I2C);
-
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
-{
-	/* USB-C0 always uses USB_C0_HPD (= DP3_HPD). */
-	if (port == 0)
-		return GPIO_USB_C0_HPD;
-
-	/*
-	 * USB-C1 OPT3 DB
-	 *    version_2 uses EC_DP1_HPD
-	 *    version_3 uses DP1_HPD via RTD2141B MST hub to drive AP
-	 *    HPD, EC drives MST hub HPD input from USB-PD messages.
-	 *
-	 * This would have been ec_config_has_usbc1_retimer_ps8802
-	 * on version_2 hardware but the result is the same and
-	 * this will be removed when version_2 hardware is retired.
-	 */
-	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 4)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: (board_ver == 3)
-					? IOEX_USB_C1_HPD_IN_DB
-					: GPIO_EC_DP1_HPD;
-
-	/* USB-C1 OPT1 DB uses DP2_HPD. */
-	return GPIO_DP2_HPD;
-}
-
-static void board_remap_gpio(void)
-{
-	int ppc_id = 0;
-
-	if (board_ver >= 3) {
-		int rv;
-
-		gpio_ec_ps2_reset = GPIO_EC_PS2_RESET_V1;
-		ccprintf("GPIO_EC_PS2_RESET_V1\n");
-
-		/*
-		 * TODO(dbrockus@): remove code when older version_2
-		 * hardware is retired and no longer needed
-		 */
-		rv = ioex_set_flags(IOEX_HDMI_POWER_EN_DB, GPIO_OUT_LOW);
-		rv |= ioex_set_flags(IOEX_USB_C1_PPC_ILIM_3A_EN, GPIO_OUT_LOW);
-		if (rv)
-			ccprintf("IOEX Board>=3 Remap FAILED\n");
-
-		if (ec_config_has_hdmi_retimer_pi3hdx1204())
-			gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
-	} else {
-		gpio_ec_ps2_reset = GPIO_EC_PS2_RESET_V0;
-		ccprintf("GPIO_EC_PS2_RESET_V0\n");
-
-		/*
-		 * TODO(dbrockus@): remove code when older version_2
-		 * hardware is retired and no longer needed
-		 */
-		if (ec_config_has_mst_hub_rtd2141b())
-			ioex_enable_interrupt(IOEX_MST_HPD_OUT);
-
-		if (ec_config_has_hdmi_retimer_pi3hdx1204())
-			ioex_enable_interrupt(IOEX_HDMI_CONN_HPD_3V3_DB);
-	}
-
-	if (board_ver >= 4)
-		board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB_V1;
-	else
-		board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-
-	ioex_get_level(IOEX_PPC_ID, &ppc_id);
-
-	support_aoz_ppc = (board_ver == 3) || ((board_ver >= 4) && !ppc_id);
-	if (support_aoz_ppc) {
-		ccprintf("DB USBC PPC aoz1380\n");
-		ppc_chips[USBC_PORT_C1].drv = &aoz1380_drv;
-	}
-}
-
-static void setup_fw_config(void)
-{
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-
-	/* Enable PS2 power interrupts */
-	gpio_enable_interrupt(GPIO_EN_PWR_TOUCHPAD_PS2);
-
-	ps2_enable_channel(NPCX_PS2_CH0, 1, send_aux_data_to_host_interrupt);
-
-	setup_mux();
-
-	board_remap_gpio();
-
-	setup_base_gyro_config();
-}
-/* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-/*****************************************************************************
- * Fan
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1800,
-	.rpm_start = 3000,
-	.rpm_max = 5200,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-
-	case TEMP_SENSOR_5V_REGULATOR:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_5V_REGULATOR;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_5V_REGULATOR,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-	[TEMP_SENSOR_SSD] = {
-		.name = "SSD",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = tmp432_get_val,
-		.idx = TMP432_IDX_LOCAL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(98),
-	.temp_fan_max = C_TO_K(99),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
-}
-DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
-
-/* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define SMART_CHARGE_SUPPORT            0x01
-#define SMART_CHARGE_ENABLE             0x02
-#define SB_SMART_CHARGE_ENABLE          1
-#define SB_SMART_CHARGE_DISABLE         0
-
-static void sb_smart_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_OPTIONALMFG_FUNCTION2, &val);
-	if (rv)
-		return;
-	if (val & SMART_CHARGE_SUPPORT) {
-		if (enable)
-			val |= SMART_CHARGE_ENABLE;
-		else
-			val &= ~SMART_CHARGE_ENABLE;
-		sb_write(SB_OPTIONALMFG_FUNCTION2, val);
-	}
-}
-
-__override void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		if (support_aoz_ppc)
-			aoz1380_interrupt(USBC_PORT_C1);
-		else
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv;
-
-	/* Use the TCPC to set the current limit */
-	if (port == 0) {
-		rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-	} else if (board_ver >= 3) {
-		rv = ioex_set_level(IOEX_USB_C1_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-	} else {
-		rv = 1;
-	}
-
-	return rv;
-}
-
-static void trackpoint_reset_deferred(void)
-{
-	gpio_set_level(gpio_ec_ps2_reset, 1);
-	msleep(2);
-	gpio_set_level(gpio_ec_ps2_reset, 0);
-	msleep(10);
-}
-DECLARE_DEFERRED(trackpoint_reset_deferred);
-
-void send_aux_data_to_device(uint8_t data)
-{
-	ps2_transmit_byte(NPCX_PS2_CH0, data);
-}
-
-void ps2_pwr_en_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&trackpoint_reset_deferred_data, MSEC);
-}
-
-static int check_hdmi_hpd_status(void)
-{
-	int hpd = 0;
-
-	if (board_ver < 3)
-		ioex_get_level(IOEX_HDMI_CONN_HPD_3V3_DB, &hpd);
-	else
-		hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
-
-	return hpd;
-}
-
-/*****************************************************************************
- * Board suspend / resume
- */
-
-static void board_chipset_resume(void)
-{
-	/* Normal charge current */
-	sb_smart_charge_mode(SB_SMART_CHARGE_DISABLE);
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 1);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		if (board_ver >= 3) {
-			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
-			msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		}
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  check_hdmi_hpd_status());
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend_delay(void)
-{
-	ignore_c1_dp = false;
-}
-DECLARE_DEFERRED(board_chipset_suspend_delay);
-
-static void board_chipset_suspend(void)
-{
-	/* SMART charge current */
-	sb_smart_charge_mode(SB_SMART_CHARGE_ENABLE);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-		if (board_ver >= 3)
-			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
-	}
-
-	/* Wait 500ms before allowing DP event to cause resume. */
-	if (ec_config_has_mst_hub_rtd2141b()
-	    && (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) {
-		ignore_c1_dp = true;
-		hook_call_deferred(&board_chipset_suspend_delay_data,
-				   500 * MSEC);
-	}
-
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * Power signals
- */
-
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-		{3, 0}, {2, 2}, {2, 3}, {1, 2}, {2, 5},
-		{2, 4}, {2, 1}, {2, 7}, {2, 6}, {1, 5},
-		{2, 0}, {3, 1}, {1, 7}, {1, 6}, {-1, -1},
-		{1, 3}, {1, 4}, {-1, -1}, {-1, -1}, {0, 7},
-		{0, 6}, {1, 0}, {1, 1}, {0, 5},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
-
-/*****************************************************************************
- * MST hub
- *
- * TODO(dbrockus@): remove VERSION_2 code when older version of hardware is
- * retired and no longer needed
- */
-static void mst_hpd_handler(void)
-{
-	int hpd = 0;
-
-	/*
-	 * Ensure level on GPIO_EC_DP1_HPD matches IOEX_MST_HPD_OUT, in case
-	 * we got out of sync.
-	 */
-	ioex_get_level(IOEX_MST_HPD_OUT, &hpd);
-	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
-	ccprints("MST HPD %d", hpd);
-}
-DECLARE_DEFERRED(mst_hpd_handler);
-
-void mst_hpd_interrupt(enum ioex_signal signal)
-{
-	/*
-	 * Goal is to pass HPD through from DB OPT3 MST hub to AP's DP1.
-	 * Immediately invert GPIO_EC_DP1_HPD, to pass through the edge on
-	 * IOEX_MST_HPD_OUT. Then check level after 2 msec debounce.
-	 */
-	int hpd = !gpio_get_level(GPIO_EC_DP1_HPD);
-
-	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
-	hook_call_deferred(&mst_hpd_handler_data, (2 * MSEC));
-}
-
-static void hdmi_hpd_handler(void)
-{
-	/* Pass HPD through from DB OPT1 HDMI connector to AP's DP1. */
-	int hpd = check_hdmi_hpd_status();
-
-	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
-	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-static void hdmi_hpd_interrupt_v2(enum ioex_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-static void hdmi_hpd_interrupt_v3(enum gpio_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-static void board_gmr_tablet_switch_isr(enum gpio_signal signal)
-{
-	/* Board version more than 3, DUT support GMR sensor */
-	if (board_ver >= 3)
-		gmr_tablet_switch_isr(signal);
-}
-
-int board_sensor_at_360(void)
-{
-	/*
-	 * Board version >= 3 supports GMR sensor. For older boards return 0
-	 * indicating not in 360-degree mode and rely on lid angle for tablet
-	 * mode.
-	 */
-	if (board_ver >= 3)
-		return !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
-
-	return 0;
-}
-
-/*
- * b/167949458: Suppress setting the host event for 500ms after entering S3.
- * Otherwise turning off the MST hub in S3 (via IOEX_HDMI_DATA_EN_DB) causes
- * a VDM:Attention that immediately wakes us back up from S3.
- */
-__override void pd_notify_dp_alt_mode_entry(int port)
-{
-	if (port == USBC_PORT_C1 && ignore_c1_dp)
-		return;
-	cprints(CC_USBPD, "Notifying AP of DP Alt Mode Entry...");
-	mkbp_send_event(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED);
-}
diff --git a/board/morphius/board.h b/board/morphius/board.h
deleted file mode 100644
index 603bcec69b..0000000000
--- a/board/morphius/board.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Morphius board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_TREMBYLE
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USBC_RETIMER_PI3DPX1207
-#define CONFIG_8042_AUX
-#define CONFIG_PS2
-#define CONFIG_CMD_PS2
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_DEVICE_EVENT
-#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-
-#undef CONFIG_LED_ONOFF_STATES
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 91
-
-#undef ZORK_PS8818_RX_INPUT_TERM
-#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_85_OHM
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CUSTOM_FAN_CONTROL
-#define CONFIG_TABLET_MODE
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP432
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PWR_A
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_GMR_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE_CUSTOM
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE
-#define RPM_DEVIATION 1
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-/* I2C mapping from board specific function*/
-#define I2C_PORT_THERMAL	I2C_PORT_AP_HDMI
-
-#ifndef __ASSEMBLER__
-
-
-void ps2_pwr_en_interrupt(enum gpio_signal signal);
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_5V_REGULATOR,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_SUNWODA,
-	BATTERY_LGC,
-	BATTERY_TYPE_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_POWER_LED,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_5V_REGULATOR,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_SSD,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * MORPHIUS_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: PI3DPX1207
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	MORPHIUS_MB_USBAC = 0,
-};
-
-/**
- * MORPHIUS_DB_T_OPT1_USBC_HDMI
- *	USB-A1  none
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8818
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- *
- * MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB
- *	USB-A1  none
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8802
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: none
- *		MST Hub: RTD2141B
- */
-enum ec_cfg_usb_db_type {
-	MORPHIUS_DB_T_OPT1_USBC_HDMI = 0,
-	MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB = 1,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_usbc1_retimer_ps8802(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
-}
-
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
-
-static inline bool ec_config_has_usbc1_retimer_ps8818(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_mst_hub_rtd2141b(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
-}
-
-void motion_interrupt(enum gpio_signal signal);
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
-#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio(port)
-
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
-extern const struct usb_mux usbc1_ps8818;
-extern struct usb_mux usbc1_amd_fp5_usb_mux;
-
-#endif /* !__ASSEMBLER__ */
-
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/morphius/build.mk b/board/morphius/build.mk
deleted file mode 100644
index 4c2a6c5546..0000000000
--- a/board/morphius/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o thermal.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/morphius/ec.tasklist b/board/morphius/ec.tasklist
deleted file mode 100644
index 41b83cf4f3..0000000000
--- a/board/morphius/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/morphius/gpio.inc b/board/morphius/gpio.inc
deleted file mode 100644
index f14c56c66f..0000000000
--- a/board/morphius/gpio.inc
+++ /dev/null
@@ -1,175 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(TABLET_MODE,		PIN(4, 4), GPIO_INT_BOTH,			board_gmr_tablet_switch_isr)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
-GPIO_INT(EN_PWR_TOUCHPAD_PS2,	PIN(C, 2), GPIO_INT_RISING,			ps2_pwr_en_interrupt)
-GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt_v3)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_ODR_HIGH)			/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
-GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_PS2_RESET_V0,		PIN(3, 2), GPIO_OUT_LOW)			/* Trackpoint reset pin V0*/
-GPIO(EC_PS2_RESET_V1,		PIN(4, 5), GPIO_OUT_LOW)			/* Trackpoint reset pin V1 */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-GPIO(FAN_ID,			PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)		/* Fan ID*/
-GPIO(USB_C1_HPD_IN_DB_V1,	PIN(B, 1), GPIO_OUT_LOW)			/* C1 HPD V1 */
-
-UNIMPLEMENTED(NO_HPD)
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_LOW)
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, 	sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-
-IOEX(USB_A0_RETIMER_EN,		EXPIN(USBC_PORT_C0, 0, 0), GPIO_OUT_LOW)	/* A0 Retimer Enable */
-IOEX(USB_A0_RETIMER_RST,	EXPIN(USBC_PORT_C0, 0, 1), GPIO_OUT_LOW)	/* A0 Retimer Reset */
-IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(PPC_ID,			EXPIN(USBC_PORT_C1, 0, 1), GPIO_INPUT)		/* PPC ID */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-
-/*
- * TODO(dbrockus@): remove code when older version_2 of hardware is
- * retired and no longer needed
- */
-#if 0
-IOEX(HDMI_POWER_EN_DB,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)	/* HDMI retimer power enable */
-#else
-#define IOEX_HDMI_POWER_EN_DB		IOEX_MST_HPD_OUT
-IOEX_INT(MST_HPD_OUT,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_INT_BOTH,	mst_hpd_interrupt)
-#endif
-
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-
-/*
- * TODO(dbrockus@): remove code when older version_2 of hardware is
- * retired and no longer needed
- */
-#if 0
-IOEX(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_LOW)	/* C1 3A Current Limit Enable */
-#else
-#define IOEX_USB_C1_PPC_ILIM_3A_EN	IOEX_HDMI_CONN_HPD_3V3_DB
-IOEX_INT(HDMI_CONN_HPD_3V3_DB,	EXPIN(USBC_PORT_C1, 1, 0), GPIO_INT_BOTH,	hdmi_hpd_interrupt_v2)
-#endif
-
-IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_LOW)	/* HDMI Retimer Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,		EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(C, BIT(3)), 0, MODULE_PWM, 0)				/* PWM0 LED */
-ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
-
-/* PS/2 channel 0 for aux device */
-ALTERNATE(PIN_MASK(6, 0x80), 1,  MODULE_PS2, 0) /* PS2_CLK0 GPIO67 */
-ALTERNATE(PIN_MASK(7, 0x01), 1,  MODULE_PS2, 0) /* PS2_DAT0 GPIO70 */
diff --git a/board/morphius/led.c b/board/morphius/led.c
deleted file mode 100644
index fc57b46d6b..0000000000
--- a/board/morphius/led.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "cros_board_info.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define LED_BAT_OFF_LVL	0
-#define LED_BAT_ON_LVL	1
-#define LED_BAT_S3_OFF_TIME_MS 3000
-#define LED_BAT_S3_PWM_RESCALE 5
-#define LED_BAT_S3_TICK_MS 50
-
-#define LED_TOTAL_TICKS 2
-#define LED_ON_TICKS 1
-
-#define LED_PWR_TICKS_PER_CYCLE 7
-
-#define TICKS_STEP1_BRIGHTER 0
-#define TICKS_STEP2_DIMMER 20
-#define TICKS_STEP3_OFF 40
-
-static int ticks;
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_WHITE,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-/* PWM brightness vs. color, in the order of off, white */
-static const uint8_t color_brightness[2] = {
-	[LED_OFF]   = 0,
-	[LED_WHITE]   = 100,
-};
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	pwm_set_duty(PWM_CH_POWER_LED, color_brightness[color]);
-}
-
-void led_set_color_battery(enum ec_led_colors color)
-{
-	uint32_t board_ver = 0;
-	int led_batt_on_lvl, led_batt_off_lvl;
-
-	cbi_get_board_version(&board_ver);
-	if (board_ver >= 3) {
-		led_batt_on_lvl = LED_BAT_ON_LVL;
-		led_batt_off_lvl = LED_BAT_OFF_LVL;
-	} else {
-		led_batt_on_lvl = !LED_BAT_ON_LVL;
-		led_batt_off_lvl = !LED_BAT_OFF_LVL;
-	}
-
-	switch (color) {
-	case LED_AMBER:
-		gpio_set_level(GPIO_LED_FULL_L, led_batt_off_lvl);
-		gpio_set_level(GPIO_LED_CHRG_L, led_batt_on_lvl);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_LED_FULL_L, led_batt_on_lvl);
-		gpio_set_level(GPIO_LED_CHRG_L, led_batt_off_lvl);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, led_batt_off_lvl);
-		gpio_set_level(GPIO_LED_CHRG_L, led_batt_off_lvl);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 100;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LED_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LED_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_WHITE]);
-		else
-			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_OFF]);
-	}
-
-	return EC_SUCCESS;
-}
-
-static void suspend_led_update_deferred(void);
-DECLARE_DEFERRED(suspend_led_update_deferred);
-
-static void suspend_led_update_deferred(void)
-{
-	int delay = LED_BAT_S3_TICK_MS * MSEC;
-
-	ticks++;
-
-	/* 1s gradual on, 1s gradual off, 3s off */
-	if (ticks <= TICKS_STEP2_DIMMER) {
-		pwm_set_duty(PWM_CH_POWER_LED, ticks * LED_BAT_S3_PWM_RESCALE);
-	} else if (ticks <= TICKS_STEP3_OFF) {
-		pwm_set_duty(PWM_CH_POWER_LED,
-					(TICKS_STEP3_OFF - ticks) * LED_BAT_S3_PWM_RESCALE);
-	} else {
-		ticks = TICKS_STEP1_BRIGHTER;
-		delay = LED_BAT_S3_OFF_TIME_MS * MSEC;
-	}
-
-	hook_call_deferred(&suspend_led_update_deferred_data, delay);
-}
-
-static void suspend_led_init(void)
-{
-	ticks = TICKS_STEP2_DIMMER;
-
-	hook_call_deferred(&suspend_led_update_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, suspend_led_init, HOOK_PRIO_DEFAULT);
-
-static void suspend_led_deinit(void)
-{
-	hook_call_deferred(&suspend_led_update_deferred_data, -1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, suspend_led_deinit, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, suspend_led_deinit, HOOK_PRIO_DEFAULT);
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static int power_ticks;
-	static int previous_state_suspend;
-	static int blink_ticks;
-
-	power_ticks++;
-
-	/* Blink 3 times (0.25s on/0.25s off, repeat 3 times) */
-	if (extpower_is_present()) {
-		blink_ticks++;
-		if (!previous_state_suspend)
-			power_ticks = 0;
-
-		while (blink_ticks < LED_PWR_TICKS_PER_CYCLE) {
-			led_set_color_power(
-				(power_ticks % LED_TOTAL_TICKS) < LED_ON_TICKS ?
-				LED_WHITE : LED_OFF);
-
-			previous_state_suspend = 1;
-			return;
-		}
-	}
-	if (!extpower_is_present())
-		blink_ticks = 0;
-
-	previous_state_suspend = 0;
-
-	if (chipset_in_state(CHIPSET_STATE_SOFT_OFF))
-		led_set_color_power(LED_OFF);
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-}
-
-static void pwr_led_init(void)
-{
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_PWM, 1);
-
-	/*
-	 * Enable PWMs and set to 0% duty cycle.  If they're disabled,
-	 * seems to ground the pins instead of letting them float.
-	 */
-	pwm_enable(PWM_CH_POWER_LED, 1);
-	led_set_color_power(LED_OFF);
-}
-DECLARE_HOOK(HOOK_INIT, pwr_led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every 200 ms */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/morphius/thermal.c b/board/morphius/thermal.c
deleted file mode 100644
index 449fd92d5d..0000000000
--- a/board/morphius/thermal.c
+++ /dev/null
@@ -1,522 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "motion_lid.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-struct fan_step {
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-
-	/* Fan 1~2 rpm */
-	uint16_t rpm[FAN_CH_COUNT];
-};
-
-static const struct fan_step *fan_step_table;
-
-static const struct fan_step fan1_table_clamshell[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 40, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1900},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 45, -1},
-		.off = {-1, -1, 43, -1},
-		.rpm = {2900},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 48, -1},
-		.off = {-1, -1, 46, -1},
-		.rpm = {3200},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {3550},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3950},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {4250},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {4650},
-	},
-};
-
-static const struct fan_step fan1_table_tablet[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2100},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2600},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {2800},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3300},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3800},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4000},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4300},
-	},
-};
-
-static const struct fan_step fan1_table_stand[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1850},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2550},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2900},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3350},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3700},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {3900},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4250},
-	},
-};
-
-static const struct fan_step fan0_table_clamshell[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2350},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 42, -1},
-		.rpm = {3300},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 47, -1},
-		.off = {-1, -1, 45, -1},
-		.rpm = {3600},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {4050},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {4450},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 56, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4750},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 59, -1},
-		.off = {-1, -1, 57, -1},
-		.rpm = {5150},
-	},
-};
-
-static const struct fan_step fan0_table_tablet[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2850},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {3100},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3500},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3900},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4150},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4400},
-	},
-};
-
-static const struct fan_step fan0_table_stand[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2800},
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {3150},
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3550},
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3900},
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4150},
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4400},
-	},
-};
-
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan1_table_clamshell)
-
-#define lid_angle_tablet	340
-static int throttle_on;
-
-BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) ==
-	ARRAY_SIZE(fan1_table_tablet));
-
-#define average_time 60
-int fan_table_to_rpm(int fan, int *temp)
-{
-	static int current_level;
-	static int avg_tmp[TEMP_SENSOR_COUNT];
-	static int avg_calc_tmp[TEMP_SENSOR_COUNT][average_time];
-	static int prev_tmp[TEMP_SENSOR_COUNT];
-	static int new_rpm;
-	int i, j, avg_sum = 0;
-	int lid_angle = motion_lid_get_angle();
-	static int fan_up_count, fan_down_count;
-	static int temp_count;
-
-	/*
-	 * Select different fan curve table
-	 * by mode: clamshell, tent/stand, tablet and fan id
-	 */
-	if (tablet_get_mode()) {
-		if (gpio_get_level(GPIO_FAN_ID))
-			fan_step_table = fan1_table_stand;
-		else
-			fan_step_table = fan0_table_stand;
-
-		if (lid_angle >= lid_angle_tablet) {
-			if (gpio_get_level(GPIO_FAN_ID))
-				fan_step_table = fan1_table_tablet;
-			else
-				fan_step_table = fan0_table_tablet;
-		}
-	} else {
-		if (gpio_get_level(GPIO_FAN_ID))
-			fan_step_table = fan1_table_clamshell;
-		else
-			fan_step_table = fan0_table_clamshell;
-	}
-
-	/*
-	 * Average temp 60 sec timing average
-	 */
-	if (temp_count < average_time) {
-		avg_calc_tmp[TEMP_SENSOR_CPU][temp_count] =
-			temp[TEMP_SENSOR_CPU];
-		temp_count++;
-	} else
-		temp_count = 0;
-
-	for (j = 0; j < average_time; j++)
-		avg_sum = avg_sum + avg_calc_tmp[TEMP_SENSOR_CPU][j];
-
-	avg_tmp[TEMP_SENSOR_CPU] = avg_sum/average_time;
-
-	/*
-	 * Compare the current and previous temperature, we have
-	 * the three paths :
-	 *  1. decreasing path. (check the release point)
-	 *  2. increasing path. (check the trigger point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (avg_tmp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
-		for (i = current_level; i >= 0; i--) {
-			if (avg_tmp[TEMP_SENSOR_CPU] <
-				fan_step_table[i].off[TEMP_SENSOR_CPU]) {
-			/*
-			 * fan step down debounce
-			 */
-				if (fan_down_count < 10) {
-					fan_down_count++;
-					fan_up_count = 0;
-
-					return new_rpm;
-				}
-				fan_down_count = 0;
-				fan_up_count = 0;
-
-				current_level = i - 1;
-			} else
-				break;
-		}
-	} else if (avg_tmp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
-		for (i = current_level+1; i < NUM_FAN_LEVELS; i++) {
-			if ((avg_tmp[TEMP_SENSOR_CPU] >
-				 fan_step_table[i].on[TEMP_SENSOR_CPU])) {
-			/*
-			 * fan step up debounce
-			 */
-				if (fan_up_count < 10) {
-					fan_up_count++;
-					fan_down_count = 0;
-
-					return new_rpm;
-				}
-				fan_down_count = 0;
-				fan_up_count = 0;
-
-				current_level = i;
-			} else
-				break;
-		}
-	} else {
-		fan_down_count = 0;
-		fan_up_count = 0;
-	}
-
-	if (current_level < 1)
-		current_level = 1;
-
-	if (current_level >= 7)
-		current_level = 7;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
-		prev_tmp[i] = avg_tmp[i];
-
-	ASSERT(current_level < NUM_FAN_LEVELS);
-
-	switch (fan) {
-	case FAN_CH_0:
-		new_rpm = fan_step_table[current_level].rpm[FAN_CH_0];
-		break;
-	default:
-		break;
-	}
-
-	return new_rpm;
-}
-
-void board_override_fan_control(int fan, int *tmp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
-		int new_rpm = fan_table_to_rpm(fan, tmp);
-
-		if (new_rpm != fan_get_rpm_target(FAN_CH(fan))) {
-			cprints(CC_THERMAL, "Setting fan RPM to %d", new_rpm);
-			board_print_temps();
-			fan_set_rpm_mode(FAN_CH(fan), 1);
-			fan_set_rpm_target(FAN_CH(fan), new_rpm);
-		}
-	}
-}
-
-void thermal_protect(void)
-{
-	if ((!lid_is_open()) && (!extpower_is_present())) {
-		int rv1, rv2;
-		int thermal_sensor1, thermal_sensor2;
-
-		rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR,
-				       &thermal_sensor1);
-		rv2 = temp_sensor_read(TEMP_SENSOR_CPU,
-				       &thermal_sensor2);
-
-		if (rv2 == EC_SUCCESS) {
-			if (thermal_sensor2 > C_TO_K(70)) {
-				chipset_throttle_cpu(1);
-				throttle_on = 1;
-			} else if (thermal_sensor2 < C_TO_K(60) &&
-				   throttle_on) {
-				chipset_throttle_cpu(0);
-				throttle_on = 0;
-			}
-		}
-		if (rv1 == EC_SUCCESS &&
-		    thermal_sensor1 > C_TO_K(51))
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, thermal_protect, HOOK_PRIO_DEFAULT);
diff --git a/board/morphius/vif_override.xml b/board/morphius/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/morphius/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/mrbland/base_detect.c b/board/mrbland/base_detect.c
deleted file mode 100644
index 85bc04c4c2..0000000000
--- a/board/mrbland/base_detect.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mrbland base detection code */
-
-#include "adc.h"
-#include "base_state.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
-#define BASE_DETECT_EN_LATER_US (600 * MSEC)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
-#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * Lid has 604K pull-up, base has 30.1K pull-down, so the
- * ADC value should be around 30.1/(604+30.1)*3300 = 156
- *
- * We add a significant margin on the maximum value, due to noise on the line,
- * especially when PWM is active. See b/64193554 for details.
- */
-#define BASE_DETECT_MIN_MV 120
-#define BASE_DETECT_MAX_MV 300
-
-/* Minimum ADC value to indicate base is disconnected for sure */
-#define BASE_DETECT_DISCONNECT_MIN_MV 1500
-
-/*
- * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
- * can be used to wake system from deep S3).
- */
-#define BASE_DETECT_PULSE_MIN_US 400
-#define BASE_DETECT_PULSE_MAX_US 650
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Change in power to base
- * 2. Indicate mode change to host.
- * 3. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	gpio_set_level(GPIO_EN_BASE, connected);
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-	base_set_state(connected);
-	current_base_status = status;
-}
-
-/* Measure detection pin pulse duration (used to wake AP from deep S3). */
-static uint64_t pulse_start;
-static uint32_t pulse_width;
-
-static void print_base_detect_value(int v, int tmp_pulse_width)
-{
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-	uint32_t tmp_pulse_width = pulse_width;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		return;
-
-	print_base_detect_value(v, tmp_pulse_width);
-
-	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
-		if (current_base_status != BASE_CONNECTED) {
-			base_detect_change(BASE_CONNECTED);
-		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
-			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
-			CPRINTS("Sending event to AP");
-			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-		}
-		return;
-	}
-
-	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
-		base_detect_change(BASE_DISCONNECTED);
-		return;
-	}
-
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static inline int detect_pin_connected(enum gpio_signal det_pin)
-{
-	return gpio_get_level(det_pin) == 0;
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-	int debounce_us;
-
-	if (detect_pin_connected(signal))
-		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-	else
-		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-
-	if (base_detect_debounce_time <= time_now) {
-		/*
-		 * Detect and measure detection pin pulse, when base is
-		 * connected. Only a single pulse is measured over a debounce
-		 * period. If no pulse, or multiple pulses are detected,
-		 * pulse_width is set to 0.
-		 */
-		if (current_base_status == BASE_CONNECTED &&
-		    !detect_pin_connected(signal)) {
-			pulse_start = time_now;
-		} else {
-			pulse_start = 0;
-		}
-		pulse_width = 0;
-
-		hook_call_deferred(&base_detect_deferred_data, debounce_us);
-	} else {
-		if (current_base_status == BASE_CONNECTED &&
-		    detect_pin_connected(signal) && !pulse_width &&
-		    pulse_start) {
-			/* First pulse within period. */
-			pulse_width = time_now - pulse_start;
-		} else {
-			pulse_start = 0;
-			pulse_width = 0;
-		}
-	}
-
-	base_detect_debounce_time = time_now + debounce_us;
-}
-
-static void base_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
-	gpio_enable_interrupt(GPIO_BASE_DET_L);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
-
-static void base_disable(void)
-{
-	/*
-	 * Disable base detection interrupt and disable power to base.
-	 * Set the state UNKNOWN so the next startup will initialize a
-	 * correct state and notify AP.
-	 */
-	gpio_disable_interrupt(GPIO_BASE_DET_L);
-	base_detect_change(BASE_UNKNOWN);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * If we jumped to this image and chipset is already in S0, enable
-	 * base.
-	 */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		base_enable();
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		base_enable();
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/mrbland/battery.c b/board/mrbland/battery.c
deleted file mode 100644
index a99d71e7f4..0000000000
--- a/board/mrbland/battery.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all mrbland battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* Celxpert L21C2PG1 */
-	[BATTERY_L21C2PG1] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "LNV-5B11F38374",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7680, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 384,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-	/* Sunwoda L21D2PG1 */
-	[BATTERY_L21D2PG1] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "LNV-5B11F38370",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7680, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 63,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 63,
-		},
-	},
-	/* SMP L21M2PG1 */
-	[BATTERY_L21M2PG1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "LNV-5B11F38381",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800, /* mV */
-			.voltage_normal         = 7680, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 128,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D2PG1;
diff --git a/board/mrbland/board.c b/board/mrbland/board.c
deleted file mode 100644
index fc48888a55..0000000000
--- a/board/mrbland/board.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mrbland board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/ln9310.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peripheral_charger.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "queue.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-static void switchcap_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void switchcap_interrupt(enum gpio_signal signal)
-{
-	ln9310_interrupt(signal);
-}
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* LN9310 switchcap */
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
-};
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Mutexes */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm42607_data;
-
-enum lid_accelgyro_type {
-	LID_GYRO_NONE = 0,
-	LID_GYRO_BMI160 = 1,
-	LID_GYRO_ICM42607 = 2,
-};
-
-static enum lid_accelgyro_type lid_accelgyro_config;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t icm42607_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm42607_lid_gyro = {
-	.name = "Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.min_frequency = ICM42607_GYRO_MIN_FREQ,
-	.max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int val = -1;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (lid_accelgyro_config != LID_GYRO_NONE)
-		return;
-
-	/* Check base accelgyro chip */
-	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
-	if (val == ICM42607_CHIP_ICM42607P) {
-		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
-		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
-		lid_accelgyro_config = LID_GYRO_ICM42607;
-		CPRINTS("LID Accelgyro: ICM42607");
-	} else {
-		lid_accelgyro_config = LID_GYRO_BMI160;
-		CPRINTS("LID Accelgyro: BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (lid_accelgyro_config) {
-	case LID_GYRO_ICM42607:
-		icm42607_interrupt(signal);
-		break;
-	case LID_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-enum battery_cell_type board_get_battery_cell_type(void)
-{
-	return BATTERY_CELL_TYPE_2S;
-}
-
-static void board_switchcap_init(void)
-{
-	CPRINTS("Use switchcap: LN9310");
-
-	/* Configure and enable interrupt for LN9310 */
-	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
-	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
-
-	/* Only configure the switchcap if not sysjump */
-	if (!system_jumped_late())
-		ln9310_init();
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-
-	board_switchcap_init();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__overridable uint16_t board_get_ps8xxx_product_id(int port)
-{
-	return PS8805_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Board rev 1+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 1)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
-	ln9310_software_enable(enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return ln9310_power_good();
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/mrbland/board.h b/board/mrbland/board.h
deleted file mode 100644
index f4cb398c50..0000000000
--- a/board/mrbland/board.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mrbland board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Switchcap */
-#define CONFIG_LN9310
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_VENDOR_PARAM
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Enable PD3.0 */
-#define CONFIG_USB_PD_REV30
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-
-/* I2C */
-#undef I2C_PORT_TCPC0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT2_0
-
-/* Lid accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-#define CONFIG_ACCELGYRO_ICM42607
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_FRONT_PROXIMITY_SWITCH
-
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_BASE_ATTACHED_SWITCH
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
-#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
-
-#define CONFIG_MKBP_INPUT_DEVICES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_BASE_DET,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_L21C2PG1,
-	BATTERY_L21D2PG1,
-	BATTERY_L21M2PG1,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Base detection */
-void base_detect_interrupt(enum gpio_signal signal);
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mrbland/build.mk b/board/mrbland/build.mk
deleted file mode 100644
index 74b6b95e4d..0000000000
--- a/board/mrbland/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y=battery.o board.o led.o base_detect.o
diff --git a/board/mrbland/ec.tasklist b/board/mrbland/ec.tasklist
deleted file mode 100644
index 493c39dc6c..0000000000
--- a/board/mrbland/ec.tasklist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/mrbland/gpio.inc b/board/mrbland/gpio.inc
deleted file mode 100644
index 6d09e87688..0000000000
--- a/board/mrbland/gpio.inc
+++ /dev/null
@@ -1,195 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
-
-/* Sensor interrupts */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
-GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
-
-/*
- * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
- * need to be an interrupt for normal EC operations. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Base detection */
-GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
-
-/* POGO */
-GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
-GPIO(EC_PWRBTN_LED,         PIN(7, 3), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
-GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. Apply PU for power saving */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(3, 1))
-UNUSED(PIN(3, 0))
-UNUSED(PIN(2, 7))
-UNUSED(PIN(2, 6))
-UNUSED(PIN(2, 5))
-UNUSED(PIN(2, 4))
-UNUSED(PIN(2, 3))
-UNUSED(PIN(2, 2))
-UNUSED(PIN(2, 1))
-UNUSED(PIN(2, 0))
-UNUSED(PIN(1, 7))
-UNUSED(PIN(1, 6))
-UNUSED(PIN(1, 5))
-UNUSED(PIN(1, 4))
-UNUSED(PIN(1, 3))
-UNUSED(PIN(1, 2))
-UNUSED(PIN(1, 1))
-UNUSED(PIN(1, 0))
-UNUSED(PIN(0, 7))
-UNUSED(PIN(0, 6))
-UNUSED(PIN(0, 5))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(C, 6))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 6))
-UNUSED(PIN(8, 0))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(D, 1))
-UNUSED(PIN(D, 3))
-UNUSED(PIN(7, 5))
-UNUSED(PIN(8, 6))
-UNUSED(PIN(7, 4))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(8, 5))
-UNUSED(PIN(E, 0))
-UNUSED(PIN(0, 3))
-UNUSED(PIN(6, 1))
-UNUSED(PIN(F, 1))
-UNUSED(PIN(9, 0))
-UNUSED(PIN(8, 7))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)             /* I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-/* TODO(Camera?) should have a poper config for this, PWM or not */
-ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
-ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
-
-
diff --git a/board/mrbland/led.c b/board/mrbland/led.c
deleted file mode 100644
index a8d2fcda30..0000000000
--- a/board/mrbland/led.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-#include "extpower.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-/* Battery LED blinks every per 400ms */
-#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color_battery(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
-	if (color == LED_AMBER) {
-		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
-		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
-	}
-}
-
-static void led_set_color_power(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_PWRBTN_LED,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(LED_RED);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(LED_GREEN);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LED_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
-			if (percent <= BATTERY_LEVEL_CRITICAL) {
-				/* battery capa <= 5%, Red */
-				color = LED_RED;
-			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
-				/* 5% < battery capa < 97%, Orange */
-				color = LED_AMBER;
-			} else {
-				/* battery capa >= 97%, Green */
-				color = LED_GREEN;
-			}
-		}
-		break;
-	case PWR_STATE_DISCHARGE:
-		color = LED_OFF;
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error, Red on 1sec off 1sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_RED;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
-			color = LED_RED;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color_battery(color);
-}
-
-static void board_led_set_power(void)
-{
-	static int power_ticks;
-	int color = LED_OFF;
-	int period = 0;
-
-	power_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* S0, White (soild on) */
-			color = LED_WHITE;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* S3, white (3s on 500ms off) */
-			period = 1 * LED_HALF_ONE_SEC + 3 * LED_ONE_SEC;
-			power_ticks = power_ticks % period;
-			if (power_ticks < 3 * LED_ONE_SEC)
-				color = LED_WHITE;
-			else
-				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* S5, off */
-			color = LED_OFF;
-		}
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color_power(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		board_led_set_power();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_RED : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color_battery(color);
-}
diff --git a/board/mrbland/vif_override.xml b/board/mrbland/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/mrbland/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/munna/battery.c b/board/munna/battery.c
deleted file mode 100644
index 1b162e93c7..0000000000
--- a/board/munna/battery.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC L20L3PG2, Gauge IC: RAJ240047A20DNP. */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,   /* mV */
-			.voltage_normal		= 11400,   /* mV */
-			.voltage_min		= 9000,    /* mV */
-			.precharge_current	= 256,     /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L20D3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SIMPLO L20M3PG2, Gauge IC: BQ40Z697A. */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,   /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -40,
-			.discharging_max_c	= 73,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/munna/board.c b/board/munna/board.c
deleted file mode 100644
index f31c7a7e39..0000000000
--- a/board/munna/board.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "keyboard_backlight.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(5),
-			   STM32_RANK(1)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15),
-			    STM32_RANK(2)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 2, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 3, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 2,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-#ifdef CHIP_FAMILY_STM32L4
-	/* Set I/O speed before AF configured */
-	/* EMMC SPI SLAVE: PB13/14/15 */
-	/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xFF300000;
-	STM32_GPIO_OSPEEDR(GPIO_C) |= 0x000000F0;
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2;
-#else
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-#endif
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
-#else
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
-};
-
-void board_kblight_init(void)
-{
-	kblight_register(&kblight_it8801);
-}
-
-bool board_has_kb_backlight(void)
-{
-	/* Default enable keyboard backlight */
-	return true;
-}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Battery functions */
-#define SB_SMARTCHARGE				0x26
-/* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
-/* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_SMARTCHARGE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_SMARTCHARGE, val);
-}
-
-/* Called on AP S0iX -> S0 transition */
-static void board_chipset_resume(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 1);
-#endif
-
-	/* Normal charge mode */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void board_chipset_suspend(void)
-{
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	if (board_has_kb_backlight())
-		ioex_set_level(IOEX_KB_BL_EN, 0);
-#endif
-
-	/* Quick charge mode */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return I2C_PORT_CHARGER;
-}
-
-int board_get_battery_i2c(void)
-{
-	return I2C_PORT_BATTERY;
-}
-
-#ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
-{
-	switch (type) {
-	case EC_PWM_TYPE_GENERIC:
-		*channel = index;
-		break;
-	default:
-		return -1;
-	}
-
-	return *channel >= 1;
-}
-
-static enum ec_status
-host_command_pwm_set_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_duty *p = args->params;
-	enum pwm_channel channel;
-	uint16_t duty;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	duty = (uint32_t) p->duty * 255 / 65535;
-	it8801_pwm_set_raw_duty(channel, duty);
-	it8801_pwm_enable(channel, p->duty > 0);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_pwm_get_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_get_duty *p = args->params;
-	struct ec_response_pwm_get_duty *r = args->response;
-
-	enum pwm_channel channel;
-
-	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
-		     EC_VER_MASK(0));
-#endif
diff --git a/board/munna/board.h b/board/munna/board.h
deleted file mode 100644
index baf68470e4..0000000000
--- a/board/munna/board.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Munna */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32L431
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/* PLL configuration. Freq = STM32_HSE_CLOCK or HSI (16MHz) * n/m/r */
-#undef STM32_PLLM
-#undef STM32_PLLN
-#undef STM32_PLLR
-#define STM32_PLLM	1
-#ifdef STM32_HSE_CLOCK
-#define STM32_PLLN	12
-#else
-#define STM32_PLLN	10
-#endif
-#define STM32_PLLR	2
-
-#define STM32_USE_PLL
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_POWER_LED
-
-#undef	CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 4000
-
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#ifdef SECTION_IS_RW
-#define CONFIG_IO_EXPANDER_IT8801_PWM
-#define CONFIG_KEYBOARD_BACKLIGHT
-#endif
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            2
-#define I2C_PORT_SENSORS            2
-#define IT8801_KEYBOARD_PWM_I2C_PORT 2
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            3
-#define I2C_PORT_TCPC0              0
-
-#undef I2C_CONTROLLER_COUNT
-#undef I2C_PORT_COUNT
-#define I2C_CONTROLLER_COUNT        3
-#define I2C_PORT_COUNT              3
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-/* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-#undef CONFIG_GMR_TABLET_MODE
-#undef GMR_TABLET_MODE_GPIO_L
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	IT8801_PWM_CH_KBLIGHT = 0,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/munna/build.mk b/board/munna/build.mk
deleted file mode 100644
index 594bac4de9..0000000000
--- a/board/munna/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32L431RCI
-CHIP:=stm32
-CHIP_FAMILY:=stm32l4
-CHIP_VARIANT:=stm32l431x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/munna/ec.tasklist b/board/munna/ec.tasklist
deleted file mode 100644
index 6b29595620..0000000000
--- a/board/munna/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/munna/gpio.inc b/board/munna/gpio.inc
deleted file mode 100644
index 50e5ee3a47..0000000000
--- a/board/munna/gpio.inc
+++ /dev/null
@@ -1,120 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 11),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4),  GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-GPIO(TABLET_MODE_L,        PIN(B, 11), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(H, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(C, 0),  GPIO_INPUT)
-GPIO(I2C3_SDA,             PIN(C, 1),  GPIO_INPUT)
-GPIO(I2C4_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C4_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(A, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(H, 3),  GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(H, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(A, 12), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_GREEN_FULL_L, EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_RED_L,        EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(KB_BL_EN,             EXPIN(0, 0, 7), GPIO_OUT_LOW)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PC0/C1 */
-ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 5, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 5, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 5, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 5, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/munna/led.c b/board/munna/led.c
deleted file mode 100644
index fa4f46b6ab..0000000000
--- a/board/munna/led.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Munna
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_GREEN_FULL_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_RED_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/munna/vif_override.xml b/board/munna/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/munna/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/mushu/battery.c b/board/mushu/battery.c
deleted file mode 100644
index 7e48dfdc19..0000000000
--- a/board/mushu/battery.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-/*
- * Battery info for all Mushu battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* POW-TECH Battery Information */
-	[BATTERY_POWER_TECH] = {
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP SDI Dell FMXMT Battery Information */
-	[BATTERY_SMP_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI-3727",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
diff --git a/board/mushu/board.c b/board/mushu/board.c
deleted file mode 100644
index 353875e9f5..0000000000
--- a/board/mushu/board.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mushu board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/amd_r19me4070.h"
-#include "driver/temp_sensor/f75303.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	baseboard_mst_enable_control(MST_HDMI, gpio_get_level(signal));
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/*
- * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
- * matrix can't be tested properly. This needs to be revisited after EVT to make
- * sure the rotation matrix for the lid sensor is correct.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-	  .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_ALS,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-const struct fan_conf fan_conf_1 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2000,
-	.rpm_start = 2000,
-	.rpm_max = 4100,
-};
-
-const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 2000,
-	.rpm_start = 2000,
-	.rpm_max = 4100,
-};
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-	[FAN_CH_1] = { .conf = &fan_conf_1, .rpm = &fan_rpm_1, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1
-	},
-	[TEMP_5V] = {
-		.name = "5V",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2
-	},
-	[TEMP_GPU] = {
-		.name = "GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_R19ME4070,
-		.idx = R19ME4070_LOCAL
-	},
-	[TEMP_F75303_LOCAL] = {
-		.name = "F75303_Local",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_LOCAL
-	},
-	[TEMP_F75303_GPU] = {
-		.name = "F75303_GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE1
-	},
-	[TEMP_F75303_GPU_POWER] = {
-		.name = "F75303_GPU_Power",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE2
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Hatch Temperature sensors */
-/*
- * TODO(b/124316213): These setting need to be reviewed and set appropriately
- * for Hatch. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(0),
-	.temp_fan_max = C_TO_K(70),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(0),
-	.temp_fan_max = C_TO_K(70),
-};
-
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_CHARGER] = thermal_a;
-	thermal_params[TEMP_5V] = thermal_a;
-	thermal_params[TEMP_GPU] = thermal_b;
-}
-
-/* Sets the gpio flags correct taking into account warm resets */
-static void reset_gpio_flags(enum gpio_signal signal, int flags)
-{
-	/*
-	 * If the system was already on, we cannot set the value otherwise we
-	 * may change the value from the previous image which could cause a
-	 * brownout.
-	 */
-	if (system_is_reboot_warm() || system_jumped_late())
-		flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-	gpio_set_flags(signal, flags);
-}
-
-/* Runtime GPIO defaults */
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A_V1;
-
-static void board_gpio_set_pp5000(void)
-{
-	uint32_t board_id = 0;
-
-	/* Errors will count as board_id 0 */
-	cbi_get_board_version(&board_id);
-
-	if (board_id == 0) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V0, GPIO_OUT_LOW);
-		/* Change runtime default for V0 */
-		gpio_en_pp5000_a = GPIO_EN_PP5000_A_V0;
-	} else if (board_id >= 1) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
-	}
-
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_TCS3400_INT_ODL);
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-	/* Select correct gpio signal for PP5000_A control */
-	board_gpio_set_pp5000();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255);
-}
diff --git a/board/mushu/board.h b/board/mushu/board.h
deleted file mode 100644
index 1bd58abbba..0000000000
--- a/board/mushu/board.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mushu board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Reduce flash usage */
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-#undef  CONFIG_CMD_ACCELSPOOF
-#undef  CONFIG_CMD_CHARGER_DUMP
-#undef  CONFIG_CMD_PPC_DUMP
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-#undef CONFIG_CMD_MFALLOW
-
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-/* TC3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
-#define CONFIG_TEMP_SENSOR
-/* AMD SMBUS Temp sensors */
-#define CONFIG_TEMP_SENSOR_AMD_R19ME4070
-/* F75303 on I2C bus */
-#define CONFIG_TEMP_SENSOR_F75303
-/* Temp sensor is on port 4 on baseboard but on port 0 on Mushu */
-#undef I2C_PORT_THERMAL
-#define I2C_PORT_THERMAL I2C_PORT_SENSOR
-
-/* GPU features */
-#define I2C_PORT_GPU                    NPCX_I2C_PORT4_1
-
-/* USB Type C and USB PD defines */
-#undef CONFIG_USB_PD_TCPMV1
-/*
- * Enable TCPMv2. Use default PD 2.0 operation because we have a
- * parade PS8751 TCPC
- */
-#define CONFIG_USB_PD_TCPMV2
-#undef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-#define CONFIG_USB_PID 0x5047
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 2
-#define CONFIG_CUSTOM_FAN_CONTROL
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-#define GPIO_EN_PP5000_A gpio_en_pp5000_a
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_1,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_1,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_CHARGER,
-	TEMP_5V,
-	TEMP_GPU,
-	TEMP_F75303_LOCAL,
-	TEMP_F75303_GPU,
-	TEMP_F75303_GPU_POWER,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_SMP_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-
-#undef PD_OPERATING_POWER_MW
-#define PD_OPERATING_POWER_MW	15000
-#undef PD_MAX_POWER_MW
-#define PD_MAX_POWER_MW		100000
-#undef PD_MAX_CURRENT_MA
-#define PD_MAX_CURRENT_MA	5000
-#undef PD_MAX_VOLTAGE_MV
-#define PD_MAX_VOLTAGE_MV	20000
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mushu/build.mk b/board/mushu/build.mk
deleted file mode 100644
index 2d6118ea70..0000000000
--- a/board/mushu/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o thermal.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/mushu/ec.tasklist b/board/mushu/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/mushu/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/mushu/gpio.inc b/board/mushu/gpio.inc
deleted file mode 100644
index cc8c7a0154..0000000000
--- a/board/mushu/gpio.inc
+++ /dev/null
@@ -1,135 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-GPIO_INT(TCS3400_INT_ODL,      PIN(F, 1), GPIO_INT_FALLING, tcs3400_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A_V1,           PIN(A, 4), GPIO_DEFAULT)
-GPIO(EN_PP5000_A_V0,           PIN(0, 2), GPIO_DEFAULT)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C4_SCL,                 PIN(F, 3), GPIO_INPUT)           /* EC_I2C_GPU_TEMPERATURE_SCL */
-GPIO(I2C4_SDA,                 PIN(F, 2), GPIO_INPUT)           /* EC_I2C_GPU_TEMPERATURE_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)                             /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(C, 0x01), 0, MODULE_PWM, 0)                             /* PWM6 - FAN2 */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                             /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)                             /* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL */
diff --git a/board/mushu/led.c b/board/mushu/led.c
deleted file mode 100644
index 18600ee245..0000000000
--- a/board/mushu/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Mushu
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/mushu/thermal.c b/board/mushu/thermal.c
deleted file mode 100644
index b61f36ab8a..0000000000
--- a/board/mushu/thermal.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-static int fan_control[FAN_CH_COUNT];
-
-void fan_set_percent(int fan, int pct)
-{
-	int actual_rpm;
-	int new_rpm;
-	const int min_rpm = fans[fan].rpm->rpm_min * 9 / 10;
-
-	new_rpm = fan_percent_to_rpm(fan, pct);
-	actual_rpm = fan_get_rpm_actual(FAN_CH(fan));
-
-	if (new_rpm &&
-	    actual_rpm < min_rpm &&
-	    new_rpm < fans[fan].rpm->rpm_start)
-		new_rpm = fans[fan].rpm->rpm_start;
-
-	fan_set_rpm_target(FAN_CH(fan), new_rpm);
-}
-
-void board_override_fan_control(int fan, int *tmp)
-{
-	int i, f;
-	int fmax = 0;
-	int temp_fan_configured = 0;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		tmp[i] = C_TO_K(tmp[i]);
-
-		/* figure out the max fan needed */
-		if (thermal_params[i].temp_fan_off &&
-		    thermal_params[i].temp_fan_max) {
-			f = thermal_fan_percent(thermal_params[i].temp_fan_off,
-						thermal_params[i].temp_fan_max,
-						tmp[i]);
-			if (i == TEMP_GPU)
-				fan_control[FAN_CH_1] = f;
-			else {
-				if (f > fmax) {
-					fan_control[FAN_CH_0] = f;
-					fmax = f;
-				} else
-					fan_control[FAN_CH_0] = fmax;
-			}
-			temp_fan_configured = 1;
-		}
-	}
-	/* transfer percent to rpm */
-	if (temp_fan_configured)
-		fan_set_percent(fan, fan_control[fan]);
-}
diff --git a/board/mushu/vif_override.xml b/board/mushu/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/mushu/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nami/battery.c b/board/nami/battery.c
deleted file mode 100644
index 149272c8c1..0000000000
--- a/board/nami/battery.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "board.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Default, Nami, Vayne */
-static const struct battery_info info_0 = {
-	.voltage_max = 8800,
-	.voltage_normal = 7600,
-	.voltage_min = 6000,
-	.precharge_current = 256,
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 70,
-};
-
-/* Sona */
-static const struct battery_info info_1 = {
-	.voltage_max = 13200,
-	.voltage_normal = 11550,
-	.voltage_min = 9000,
-	.precharge_current = 256,
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = -10,
-	.discharging_max_c = 60,
-};
-
-/* Pantheon */
-static const struct battery_info info_2 = {
-	.voltage_max = 8700,
-	.voltage_normal = 7500,
-	.voltage_min = 6000,
-	.precharge_current = 200,
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 60,
-};
-
-/* Panasonic AP15O5L (Akali) */
-static const struct battery_info info_3 = {
-	.voltage_max = 13200,
-	.voltage_normal = 11550,
-	.voltage_min = 9000,
-	.precharge_current = 256,
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-/* Panasonic AP18F4M (Bard/Ekko) */
-static const struct battery_info info_4 = {
-	.voltage_max = 8700,
-	.voltage_normal = 7600,
-	.voltage_min = 5500,
-	.precharge_current = 256,
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-enum battery_type {
-	BATTERY_TYPE_AP15 = 0,
-	BATTERY_TYPE_AP18,
-	BATTERY_TYPE_COUNT,
-};
-
-enum gauge_type {
-	GAUGE_TYPE_UNKNOWN = 0,
-	GAUGE_TYPE_TI_BQ40Z50,
-	GAUGE_TYPE_RENESAS_RAJ240,
-	GAUGE_TYPE_AKALI,
-};
-
-static const struct battery_info *info = &info_0;
-static int sb_ship_mode_reg = SB_MANUFACTURER_ACCESS;
-static int sb_shutdown_data = 0x0010;
-static enum gauge_type fuel_gauge;
-
-const struct battery_info *battery_get_info(void)
-{
-	return info;
-}
-
-/*
- * Read a value from the Manufacturer Access System (MAC).
- */
-static int sb_get_mac(uint16_t cmd, uint8_t *data, int len)
-{
-	int rv;
-
-	rv = sb_write(SB_MANUFACTURER_ACCESS, cmd);
-	if (rv)
-		return rv;
-
-	return sb_read_string(SB_MANUFACTURER_DATA, data, len);
-}
-
-static enum gauge_type get_gauge_ic(void)
-{
-	uint8_t data[11];
-
-	if (oem == PROJECT_AKALI)
-		return GAUGE_TYPE_AKALI;
-
-	/* 0x0002 is for 'Firmware Version' (p91 in BQ40Z50-R2 TRM).
-	 * We can't use sb_read_mfgacc because the command won't be included
-	 * in the returned block. */
-	if (sb_get_mac(0x0002, data, sizeof(data)))
-		return GAUGE_TYPE_UNKNOWN;
-
-	/* BQ40Z50 returns something while Renesus gauge returns all zeros. */
-	if (data[2] == 0 && data[3] == 0)
-		return GAUGE_TYPE_RENESAS_RAJ240;
-	else
-		return GAUGE_TYPE_TI_BQ40Z50;
-}
-
-static enum battery_type get_akali_battery_type(void)
-{
-	return CBI_SKU_CUSTOM_FIELD(sku);
-}
-
-void board_battery_init(void)
-{
-	/* Only static config because gauge may not be initialized yet */
-	switch (oem) {
-	case PROJECT_AKALI:
-		if (get_akali_battery_type() == BATTERY_TYPE_AP15)
-			info = &info_3;
-		else if (get_akali_battery_type() == BATTERY_TYPE_AP18)
-			info = &info_4;
-		sb_ship_mode_reg = 0x3A;
-		sb_shutdown_data = 0xC574;
-		break;
-	case PROJECT_SONA:
-		info = &info_1;
-		break;
-	case PROJECT_PANTHEON:
-		info = &info_2;
-		break;
-	default:
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_battery_init, HOOK_PRIO_DEFAULT);
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(sb_ship_mode_reg, sb_shutdown_data);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(sb_ship_mode_reg, sb_shutdown_data);
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	const struct battery_info *batt_info;
-	int bat_temp_c;
-
-	batt_info = battery_get_info();
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_ANY) == BATT_FLAG_BAD_ANY) {
-		curr->requested_current = batt_info->precharge_current;
-		curr->requested_voltage = batt_info->voltage_max;
-		return 1000;
-	}
-
-	/* battery temp in 0.1 deg C */
-	bat_temp_c = curr->batt.temperature - 2731;
-
-	/* Don't charge if outside of allowable temperature range */
-	if (bat_temp_c >= batt_info->charging_max_c * 10 ||
-	    bat_temp_c < batt_info->charging_min_c * 10) {
-		curr->requested_current = 0;
-		curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-	}
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATTERY_PRESENT_L) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	static int batt_status;
-
-	if (batt_status & STATUS_INITIALIZED)
-		return 1;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-enum battery_disconnect_grace_period {
-	BATTERY_DISCONNECT_GRACE_PERIOD_OFF,
-	BATTERY_DISCONNECT_GRACE_PERIOD_ON,
-	BATTERY_DISCONNECT_GRACE_PERIOD_OVER,
-};
-static enum battery_disconnect_grace_period disconnect_grace_period;
-
-static void battery_disconnect_timer(void)
-{
-	disconnect_grace_period = BATTERY_DISCONNECT_GRACE_PERIOD_OVER;
-}
-DECLARE_DEFERRED(battery_disconnect_timer);
-
-/*
- * Check for case where both XCHG and XDSG bits are set indicating that even
- * though the FG can be read from the battery, the battery is not able to be
- * charged or discharged. This situation will happen if a battery disconnect was
- * initiated via H1 setting the DISCONN signal to the battery. This will put the
- * battery pack into a sleep state and when power is reconnected, the FG can be
- * read, but the battery is still not able to provide power to the system. The
- * calling function returns batt_pres = BP_NO, which instructs the charging
- * state machine to prevent powering up the AP on battery alone which could lead
- * to a brownout event when the battery isn't able yet to provide power to the
- * system. .
- */
-static int battery_check_disconnect_ti_bq40z50(void)
-{
-	int rv;
-	uint8_t data[6];
-
-	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
-	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) {
-		if (oem != PROJECT_SONA)
-			return BATTERY_DISCONNECTED;
-		/*
-		 * For Sona, we need a workaround to wake up a battery from
-		 * cutoff. We return DISCONNECT_ERROR for the 5 seconds after
-		 * the first call BP_NOT_SURE is reported to chgstv2. It will
-		 * supply precharge current and wakes up the battery from
-		 * cutoff. If the battery is good, we won't come back here.
-		 * If not, after 5 seconds, we will return DISCONNECTED to
-		 * stop charging and avoid damaging the battery.
-		 */
-		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OVER)
-			return BATTERY_DISCONNECTED;
-		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OFF)
-			hook_call_deferred(&battery_disconnect_timer_data,
-					   5 * SECOND);
-		ccprintf("Battery disconnect grace period\n");
-		disconnect_grace_period = BATTERY_DISCONNECT_GRACE_PERIOD_ON;
-		return BATTERY_DISCONNECT_ERROR;
-	}
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-static int battery_check_disconnect_renesas_raj240(void)
-{
-	int data;
-	int rv;
-
-	rv = sb_read(0x41, &data);
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if (data != 0x1E /* 1E: Power down */)
-		return BATTERY_NOT_DISCONNECTED;
-
-	return BATTERY_DISCONNECTED;
-}
-
-static int battery_check_disconnect_1(void)
-{
-	int batt_discharge_fet;
-
-	if (sb_read(SB_MANUFACTURER_ACCESS, &batt_discharge_fet))
-		return BATTERY_DISCONNECT_ERROR;
-
-	if (get_akali_battery_type() == BATTERY_TYPE_AP15) {
-		/* Bit 15: Discharge FET status (1: On, 0: Off) */
-		if (batt_discharge_fet & 0x4000)
-			return BATTERY_NOT_DISCONNECTED;
-	} else if (get_akali_battery_type() == BATTERY_TYPE_AP18) {
-		/* Bit 13: Discharge FET status (1: Off, 0: On) */
-		if (!(batt_discharge_fet & 0x2000))
-			return BATTERY_NOT_DISCONNECTED;
-	}
-
-	return BATTERY_DISCONNECTED;
-}
-
-static int battery_check_disconnect(void)
-{
-	if (!battery_init())
-		return BATTERY_DISCONNECT_ERROR;
-
-	if (fuel_gauge == GAUGE_TYPE_UNKNOWN) {
-		fuel_gauge = get_gauge_ic();
-		CPRINTS("fuel_gauge=%d", fuel_gauge);
-	}
-
-	switch (fuel_gauge) {
-	case GAUGE_TYPE_AKALI:
-		return battery_check_disconnect_1();
-	case GAUGE_TYPE_TI_BQ40Z50:
-		return battery_check_disconnect_ti_bq40z50();
-	case GAUGE_TYPE_RENESAS_RAJ240:
-		return battery_check_disconnect_renesas_raj240();
-	default:
-		return BATTERY_DISCONNECT_ERROR;
-	}
-}
-
-static enum battery_present batt_pres_prev; /* Default BP_NO (=0) */
-
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-	int batt_disconnect_status;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Check battery disconnect status. If we are unable to read battery
-	 * disconnect status, then return BP_NOT_SURE. Battery could be in ship
-	 * mode and might require pre-charge current to wake it up. BP_NO is not
-	 * returned here because charger state machine will not provide
-	 * pre-charge current assuming that battery is not present.
-	 */
-	batt_disconnect_status = battery_check_disconnect();
-	if (batt_disconnect_status == BATTERY_DISCONNECT_ERROR)
-		return BP_NOT_SURE;
-
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Not disconnected
-	 * 3. Initialized
-	 */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	    batt_disconnect_status != BATTERY_NOT_DISCONNECTED)
-		return BP_NO;
-
-	return BP_YES;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/board/nami/board.c b/board/nami/board.c
deleted file mode 100644
index c45d11bd25..0000000000
--- a/board/nami/board.c
+++ /dev/null
@@ -1,1133 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Poppy board-specific configuration */
-
-#include "adc.h"
-#include "anx7447.h"
-#include "battery.h"
-#include "board_config.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/pmic_tps650x30.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/baro_bmp280.h"
-#include "driver/charger/isl923x.h"
-#include "driver/led/lm3509.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/f75303.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "isl923x.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_backlight.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-#include "fan.h"
-#include "fan_chip.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_PS8751	0
-#define USB_PD_PORT_ANX7447	1
-
-uint16_t board_version;
-uint8_t oem = PROJECT_NAMI;
-uint32_t sku;
-uint8_t model;
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-	{-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-/* Set PD discharge whenever VBUS detection is high (i.e. below threshold). */
-static void vbus_discharge_handler(void)
-{
-	pd_set_vbus_discharge(0, gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-	pd_set_vbus_discharge(1, gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
-}
-DECLARE_DEFERRED(vbus_discharge_handler);
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing (10x voltage divider). PPVAR_BOOSTIN_SENSE */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-/* Default, Nami, Vayne */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-/* Sona */
-const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 2700,
-	.rpm_start = 2700,
-	.rpm_max = 6000,
-};
-
-/* Pantheon */
-const struct fan_rpm fan_rpm_2 = {
-	.rpm_min = 2100,
-	.rpm_start = 2300,
-	.rpm_max = 5100,
-};
-
-/* Akali */
-const struct fan_rpm fan_rpm_3 = {
-	.rpm_min = 2700,
-	.rpm_start = 2700,
-	.rpm_max = 5500,
-};
-
-const struct fan_rpm fan_rpm_4 = {
-	.rpm_min = 2400,
-	.rpm_start = 2400,
-	.rpm_max = 4500,
-};
-
-struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"battery",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"charger",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-	[USB_PD_PORT_ANX7447] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = AN7447_TCPC3_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* 0x98 sets lower EQ of DP port (3.6db) */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	return EC_SUCCESS;
-}
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	}
-};
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_0,
-		.mux_lock = NULL,
-	},
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_1,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-	if (oem == PROJECT_AKALI && board_version < 0x0200) {
-		if (anx7447_flash_erase(USB_PD_PORT_ANX7447))
-			CPRINTS("Failed to erase OCM flash");
-
-	}
-
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST, 1);
-	msleep(1);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST, 0);
-	/* After TEST_R release, anx7447/3447 needs 2ms to finish eFuse
-	 * loading. */
-	msleep(2);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	if (oem == PROJECT_SONA && model != MODEL_SYNDRA)
-		usb_muxes[USB_PD_PORT_PS8751].board_init = ps8751_tune_mux;
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (!gpio_get_level(GPIO_USB_C1_PD_RST))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-/*
- * F75303_Remote1 is near CPU, and F75303_Remote2 is near 5V power IC.
- */
-const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = {
-	{"F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_LOCAL},
-	{"F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val,
-		F75303_IDX_REMOTE1},
-	{"F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_REMOTE2},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-/* Nami/Vayne Remote 1, 2 */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(39),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/* Sona Remote 1 */
-const static struct ec_thermal_config thermal_b1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(82),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(89),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(72),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(58),
-};
-
-/* Sona Remote 2 */
-const static struct ec_thermal_config thermal_b2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(84),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(91),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(60),
-};
-
-/* Pantheon Remote 1 */
-const static struct ec_thermal_config thermal_c1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(66),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(56),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(61),
-};
-
-/* Pantheon Remote 2 */
-const static struct ec_thermal_config thermal_c2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(74),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(82),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(64),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(38),
-	.temp_fan_max = C_TO_K(61),
-};
-
-/* Akali Local */
-const static struct ec_thermal_config thermal_d0 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(79),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = C_TO_K(81),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(80),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = C_TO_K(82),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(70),
-};
-
-/* Akali Remote 1 */
-const static struct ec_thermal_config thermal_d1 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(59),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(60),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
-
-/* Akali Remote 2 */
-const static struct ec_thermal_config thermal_d2 = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(59),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = C_TO_K(60),
-		[EC_TEMP_THRESH_HIGH] = 0,
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = 0,
-	.temp_fan_max = 0,
-};
-
-#define I2C_PMIC_READ(reg, data) \
-		i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			  (reg), (data))
-#define I2C_PMIC_WRITE(reg, data) \
-		i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			   (reg), (data))
-
-static void board_pmic_init(void)
-{
-	int err;
-	int error_count = 0;
-	static uint8_t pmic_initialized = 0;
-
-	if (pmic_initialized)
-		return;
-
-	/* Read vendor ID */
-	while (1) {
-		int data;
-		err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data);
-		if (!err && data == TPS650X30_VENDOR_ID)
-			break;
-		else if (error_count > 5)
-			goto pmic_error;
-		error_count++;
-	}
-
-	/*
-	 * VCCIOCNT register setting
-	 * [6] : CSDECAYEN
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * VRMODECTRL:
-	 * [4] : VCCIOLPM clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PGMASK1 : Exclude VCCIO from Power Good Tree
-	 * [7] : MVCCIOPG clear
-	 * otherbits: default
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PWFAULT_MASK1 Register settings
-	 * [7] : 1b V4 Power Fault Masked
-	 * [4] : 1b V7 Power Fault Masked
-	 * [2] : 1b V9 Power Fault Masked
-	 * [0] : 1b V13 Power Fault Masked
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 4 register configuration
-	 * [7:6] : 00b Reserved
-	 * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
-	 * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
-	 * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 3 register configuration
-	 * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
-	 * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
-	 * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
-	 * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 2 register configuration
-	 * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
-	 * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
-	 * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
-	 * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Discharge control 1 register configuration
-	 * [7:2] : 00b Reserved
-	 * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * Increase Voltage
-	 *  [7:0] : 0x2a default
-	 *  [5:4] : 10b default
-	 *  [5:4] : 01b 5.1V (0x1a)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a);
-	if (err)
-		goto pmic_error;
-
-	/*
-	 * PBCONFIG Register configuration
-	 *   [7] :      1b Power button debounce, 0ms (no debounce)
-	 *   [6] :      0b Power button reset timer logic, no action (default)
-	 * [5:0] : 011111b Force an Emergency reset time, 31s (default)
-	 */
-	err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F);
-	if (err)
-		goto pmic_error;
-
-	CPRINTS("PMIC init done");
-	pmic_initialized = 1;
-	return;
-
-pmic_error:
-	CPRINTS("PMIC init failed: %d", err);
-}
-
-void chipset_pre_init_callback(void)
-{
-	board_pmic_init();
-}
-
-/**
- * Buffer the AC present GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/* Set active charge port -- only one port can be active at a time. */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are sourcing VBUS on the port */
-	/* dnojiri: revisit */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && is_source) {
-		CPRINTF("No charging on source port p%d is ", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		/* dnojiri: revisit. there is always this assumption that
-		 * battery is present. If not, this may cause brownout. */
-		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 96% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	int factor = 96;
-
-	if (oem == PROJECT_AKALI &&
-		(model == MODEL_EKKO || model == MODEL_BARD))
-		factor = 95;
-	charge_ma = charge_ma * factor / 100;
-	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
-}
-
-void board_hibernate(void)
-{
-	CPRINTS("Triggering PMIC shutdown.");
-	uart_flush_output();
-	gpio_set_level(GPIO_EC_HIBERNATE, 1);
-	while (1)
-		;
-}
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1]   = { 3, PWM_CONFIG_DSLEEP, 1200 },
-	[PWM_CH_LED2] = { 5, PWM_CONFIG_DSLEEP, 1200 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
-	/*
-	 * 1.2kHz is a multiple of both 50 and 60. So a video recorder
-	 * (generally designed to ignore either 50 or 60 Hz flicker) will not
-	 * alias with refresh rate.
-	 */
-	[PWM_CH_KBLIGHT] = { 2, 0, 1200 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Lid accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct kionix_accel_data g_kx022_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t rotation_x180_z90 = {
-	{ 0, FLOAT_TO_FP(-1), 0 },
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-const struct motion_sensor_t lid_accel_1 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &rotation_x180_z90,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support lid angle calculation. */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0);
-	gpio_set_level(GPIO_USB3_POWER_DOWN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1);
-	gpio_set_level(GPIO_USB3_POWER_DOWN_L, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static void setup_motion_sensors(void)
-{
-	switch (oem) {
-	case PROJECT_AKALI:
-		if (sku & SKU_ID_MASK_CONVERTIBLE) {
-			/* Rotate axis for Akali 360 */
-			motion_sensors[LID_ACCEL] = lid_accel_1;
-			motion_sensors[BASE_ACCEL].rot_standard_ref = NULL;
-			motion_sensors[BASE_GYRO].rot_standard_ref = NULL;
-		} else {
-			/* Clamshell Akali has no accel/gyro */
-			motion_sensor_count = ARRAY_SIZE(motion_sensors) - 2;
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static void setup_fans(void)
-{
-	switch (oem) {
-	case PROJECT_SONA:
-		if (model == MODEL_SYNDRA)
-			fans[FAN_CH_0].rpm = &fan_rpm_4;
-		else
-			fans[FAN_CH_0].rpm = &fan_rpm_1;
-		thermal_params[TEMP_SENSOR_REMOTE1] = thermal_b1;
-		thermal_params[TEMP_SENSOR_REMOTE2] = thermal_b2;
-		break;
-	case PROJECT_PANTHEON:
-		fans[FAN_CH_0].rpm = &fan_rpm_2;
-		thermal_params[TEMP_SENSOR_REMOTE1] = thermal_c1;
-		thermal_params[TEMP_SENSOR_REMOTE2] = thermal_c2;
-		break;
-	case PROJECT_AKALI:
-		fans[FAN_CH_0].rpm = &fan_rpm_3;
-		thermal_params[TEMP_SENSOR_LOCAL] = thermal_d0;
-		thermal_params[TEMP_SENSOR_REMOTE1] = thermal_d1;
-		thermal_params[TEMP_SENSOR_REMOTE2] = thermal_d2;
-		break;
-	case PROJECT_NAMI:
-	case PROJECT_VAYNE:
-	default:
-		thermal_params[TEMP_SENSOR_REMOTE1] = thermal_a;
-		thermal_params[TEMP_SENSOR_REMOTE2] = thermal_a;
-	}
-}
-
-/*
- * Read CBI from i2c eeprom and initialize variables for board variants
- */
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	CPRINTS("Board Version: 0x%04x", board_version);
-
-	if (cbi_get_oem_id(&val) == EC_SUCCESS && val < PROJECT_COUNT)
-		oem = val;
-	CPRINTS("OEM: %d", oem);
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku = val;
-	CPRINTS("SKU: 0x%08x", sku);
-
-	if (cbi_get_model_id(&val) == EC_SUCCESS)
-		model = val;
-	CPRINTS("MODEL: 0x%08x", model);
-
-	if (board_version < 0x300)
-		/* Previous boards have GPIO42 connected to TP_INT_CONN */
-		gpio_set_flags(GPIO_USB2_ID, GPIO_INPUT);
-
-	setup_motion_sensors();
-
-	setup_fans();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
-	},
-};
-
-static void anx7447_set_aux_switch(void)
-{
-	const int port = USB_PD_PORT_ANX7447;
-
-	/* Debounce */
-	if (gpio_get_level(GPIO_CCD_MODE_ODL))
-		return;
-
-	CPRINTS("C%d: AUX_SW_SEL=0x%x", port, 0xc);
-	if (tcpc_write(port, ANX7447_REG_TCPC_AUX_SWITCH, 0xc))
-		CPRINTS("C%d: Setting AUX_SW_SEL failed", port);
-}
-DECLARE_DEFERRED(anx7447_set_aux_switch);
-
-void ccd_mode_isr(enum gpio_signal signal)
-{
-	/* Wait 2 seconds until all mux setting is done by PD task */
-	hook_call_deferred(&anx7447_set_aux_switch_data, 2 * SECOND);
-}
-
-static void board_init(void)
-{
-	int reg;
-
-	/*
-	 * This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
-	 * whenever the EC is not doing SPI flash transactions. This avoids
-	 * floating SPI buffer input (MISO), which causes power leakage (see
-	 * b/64797021).
-	 */
-	NPCX_PUPD_EN1 |= BIT(NPCX_DEVPU1_F_SPI_PUD_EN);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-
-	/* Reduce Buck-boost mode switching frequency to reduce heat */
-	if (i2c_read16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-		       ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
-		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
-		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			    ISL9238_REG_CONTROL3, reg))
-			CPRINTF("Failed to set isl9238\n");
-	}
-
-	/* Enable VBUS interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
-
-	/* Enable pericom BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Trigger once to set mux in case CCD cable is already connected. */
-	ccd_mode_isr(GPIO_CCD_MODE_ODL);
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Enable Accel/Gyro interrupt for convertibles. */
-	if (sku & SKU_ID_MASK_CONVERTIBLE)
-		gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
-
-#ifndef TEST_BUILD
-	/* Disable scanning KSO13 & 14 if keypad isn't present. */
-	if (!(sku & SKU_ID_MASK_KEYPAD)) {
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-		keyscan_config.actual_key_mask[11] = 0xfa;
-		keyscan_config.actual_key_mask[12] = 0xca;
-	}
-	if (oem == PROJECT_AKALI && model == MODEL_BARD) {
-		/* Search key is moved to col=0,row=3 */
-		keyscan_config.actual_key_mask[0] = 0x1c;
-		keyscan_config.actual_key_mask[1] = 0xfe;
-		/* No need to swap scancode_set2[0][3] and [1][0] because both
-		 * are mapped to search key. */
-	}
-	if (sku & SKU_ID_MASK_UK2) {
-		/*
-		 * Observed on Shyvana with UK keyboard,
-		 *   \|:     0x0061->0x61->0x56
-		 *   r-ctrl: 0xe014->0x14->0x1d
-		 */
-		uint16_t tmp = get_scancode_set2(4, 0);
-		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
-		set_scancode_set2(2, 7, tmp);
-	}
-#endif
-
-	isl923x_set_ac_prochot(CHARGER_SOLO, 3328 /* mA */);
-
-	switch (oem) {
-	case PROJECT_VAYNE:
-		isl923x_set_dc_prochot(CHARGER_SOLO, 11008 /* mA */);
-		break;
-	case PROJECT_PANTHEON:
-		isl923x_set_dc_prochot(CHARGER_SOLO, 9984 /* mA */);
-		break;
-	case PROJECT_SONA:
-		isl923x_set_dc_prochot(CHARGER_SOLO, 5888 /* mA */);
-		break;
-	case PROJECT_NAMI:
-	case PROJECT_AKALI:
-	/* default 4096mA 0x1000 */
-	default:
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	/* Boards with no GMR sensor use lid angles to detect tablet mode. */
-	return oem != PROJECT_AKALI;
-}
-
-void board_kblight_init(void)
-{
-	if (!(sku & SKU_ID_MASK_KBLIGHT))
-		return;
-
-	switch (oem) {
-	default:
-	case PROJECT_NAMI:
-	case PROJECT_AKALI:
-	case PROJECT_VAYNE:
-	case PROJECT_PANTHEON:
-		kblight_register(&kblight_lm3509);
-		break;
-	case PROJECT_SONA:
-		kblight_register(&kblight_pwm);
-		break;
-	}
-}
-
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
-{
-	if (oem == PROJECT_VAYNE)
-		return CRITICAL_SHUTDOWN_CUTOFF;
-	else
-		return CRITICAL_SHUTDOWN_HIBERNATE;
-
-}
-
-uint8_t board_set_battery_level_shutdown(void)
-{
-	if (oem == PROJECT_VAYNE)
-		/* We match the shutdown threshold with Powerd's.
-		 * 4 + 1 = 5% because Powerd uses '<=' while EC uses '<'. */
-		return CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE + 1;
-	else
-		return BATTERY_LEVEL_SHUTDOWN;
-}
diff --git a/board/nami/board.h b/board/nami/board.h
deleted file mode 100644
index 6d340af1df..0000000000
--- a/board/nami/board.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages except ACPI and host event because
- * the sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
-#define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_PWM
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#undef CONFIG_SUPPORT_CHIP_HIBERNATION
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_FAN_DYNAMIC
-#define CONFIG_THROTTLE_AP
-#define CONFIG_PWM_KBLIGHT
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* Port80 */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW /* This, or just RAMP? */
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		27000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-/* AP's thresholds. */
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_F75303
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-/* KB backlight driver */
-#define CONFIG_LED_DRIVER_LM3509
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* USB */
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT 4500
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_KBLIGHT	NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-#define I2C_PORT_ALS		NPCX_I2C_PORT3
-
-/* I2C addresses */
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#ifndef __ASSEMBLER__
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum temp_sensor_id {
-	TEMP_SENSOR_LOCAL = 0,
-	TEMP_SENSOR_REMOTE1,
-	TEMP_SENSOR_REMOTE2,
-	TEMP_SENSOR_COUNT,
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1,
-	PWM_CH_LED2,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT,
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum oem_id {
-	PROJECT_AKALI = 1,
-	PROJECT_VAYNE = 3,
-	PROJECT_SONA,
-	PROJECT_PANTHEON,
-	PROJECT_NAMI,
-	PROJECT_COUNT,
-};
-
-enum model_id {
-	/* Sona variants */
-	MODEL_SYNDRA = 1,
-	/* Akali variants */
-	MODEL_EKKO = 1,
-	MODEL_BARD = 2,
-};
-
-#define SKU_ID_MASK_KBLIGHT	BIT(0)
-#define SKU_ID_MASK_CONVERTIBLE	BIT(9)
-#define SKU_ID_MASK_KEYPAD	BIT(15)
-#define SKU_ID_MASK_UK2		BIT(18)
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			70000
-#define PD_MAX_CURRENT_MA		3500
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(LID_ALS))
-
-/* These should be referenced only after  HOOK_INIT:HOOK_PRIO_INIT_I2C+1. */
-extern uint16_t board_version;
-extern uint8_t oem;
-extern uint32_t sku;
-extern uint8_t model;
-
-/* SKU_ID[24:31] are dedicated to OEM customization */
-#define CBI_SKU_CUSTOM_FIELD(val)	((val) >> 24)
-
-void ccd_mode_isr(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nami/build.mk b/board/nami/build.mk
deleted file mode 100644
index f4bf21113d..0000000000
--- a/board/nami/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/nami/ec.tasklist b/board/nami/ec.tasklist
deleted file mode 100644
index 93fcda9f91..0000000000
--- a/board/nami/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/nami/gpio.inc b/board/nami/gpio.inc
deleted file mode 100644
index f4119c96a6..0000000000
--- a/board/nami/gpio.inc
+++ /dev/null
@@ -1,120 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/*
- * ADCs are not configured in this file but listed below for reference.
- *
- * PIN(4, 4) ADC1: IADP_AMON_BMON
- * PIN(4, 3) ADC2: PPVAR_BOOSTIN_SENSE
- */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING,		tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(7, 1), GPIO_INT_FALLING,		tcpc_alert_event)
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,		power_signal_interrupt)
-#endif
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,		power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,		power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,		power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP,power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(8, 3), GPIO_INT_BOTH,		lid_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP,button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(8, 6), GPIO_INT_BOTH | GPIO_PULL_UP,button_interrupt)
-GPIO_INT(WP_L,			PIN(9, 3), GPIO_INT_BOTH,		switch_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,		extpower_interrupt)
-GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,vbus0_evt)
-GPIO_INT(USB_C1_VBUS_WAKE_L,	PIN(C, 5), GPIO_INT_BOTH | GPIO_PULL_UP,vbus1_evt)
-GPIO_INT(USB_C0_BC12_INT_L,	PIN(D, 2), GPIO_INT_FALLING,		usb0_evt)
-GPIO_INT(USB_C1_BC12_INT_L,	PIN(D, 3), GPIO_INT_FALLING,		usb1_evt)
-GPIO_INT(ACCELGYRO3_INT_L,	PIN(3, 6), GPIO_INT_FALLING | GPIO_PULL_UP, bmi160_interrupt)
-GPIO_INT(TABLET_MODE_L,		PIN(7, 2), GPIO_INT_BOTH,		gmr_tablet_switch_isr)
-GPIO_INT(CCD_MODE_ODL,		PIN(6, 3), GPIO_INT_FALLING,		ccd_mode_isr)
-
-GPIO(ENABLE_BACKLIGHT_L,		PIN(6, 7), GPIO_OUT_LOW)	/* LCD backlight */
-GPIO(PP3300_DX_WLAN,		PIN(B, 1), GPIO_OUT_LOW)	/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)	/* PROCHOT# to SOC */
-GPIO(PCH_ACPRESENT,		PIN(5, 0), GPIO_ODR_LOW)	/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)	/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)	/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(7, 4), GPIO_ODR_HIGH)	/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)	/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)	/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)	/* SLP_SUS# to PMIC */
-GPIO(BATTERY_PRESENT_L,		PIN(3, 4), GPIO_INPUT)		/* Battery Present */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)		/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)		/* PMIC interrupt */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INPUT)
-#endif
-GPIO(CR50_RESET_ODL,		PIN(0, 2), GPIO_ODR_HIGH)	/* Cr50 Reset. dnojiri: unused. */
-GPIO(GPP_B14,			PIN(C, 2), GPIO_INPUT) /* Used for Intel's experimental uCode/P-unit update */
-/* Will be used to shut down EC on board_hibernate. */
-GPIO(EC_HIBERNATE,		PIN(0, 1), GPIO_OUT_LOW)
-/* GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_INPUT) dnojiri: Revisit */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)		/* EC_I2C0_0_USBC_3V3_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)		/* EC_I2C0_0_USBC_3V3_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)		/* EC_I2C0_1_USBC_3V3_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)		/* EC_I2C0_1_USBC_3V3_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)		/* EC_I2C1_3V3_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)		/* EC_I2C1_3V3_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)		/* EC_I2C2_PMIC_3V3_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)		/* EC_I2C2_PMIC_3V3_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)	/* EC_I2C3_SENSOR_1V8_SCL */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)	/* EC_I2C3_SENSOR_1V8_SDA */
-
-/* rev0: 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(USB_C0_5V_EN,		PIN(4, 0), GPIO_OUT_LOW)	/* C0 5V Enable */
-GPIO(USB_C0_3A_EN,		PIN(3, 5), GPIO_OUT_LOW)	/* C0 Enable 3A */
-GPIO(USB_C0_CHARGE_L,		PIN(C, 0), GPIO_OUT_LOW)	/* C0 Charge enable. Active low. */
-GPIO(USB_C1_5V_EN,		PIN(3, 3), GPIO_OUT_LOW)	/* C1 5V Enable */
-GPIO(USB_C1_3A_EN,		PIN(6, 6), GPIO_OUT_LOW)	/* C1 3A Enable */
-GPIO(USB_C1_CHARGE_L,		PIN(C, 3), GPIO_OUT_LOW)	/* C1 Charge enable. Active low. */
-GPIO(USB_C0_PD_RST_L,		PIN(C, 6), GPIO_ODR_HIGH)	/* C0 PD Reset */
-GPIO(USB_C1_PD_RST,		PIN(0, 0), GPIO_OUT_LOW)	/* C1 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)		/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(A, 5), GPIO_INPUT)		/* C1 DP Hotplug Detect */
-GPIO(USB_PP3300_USB_PD,		PIN(8, 4), GPIO_INPUT)		/* Reserved. Currently, has no effect. */
-GPIO(USB2_ID,			PIN(4, 2), GPIO_OUT_HIGH)	/* USB OTG ID */
-GPIO(USB3_POWER_DOWN_L,		PIN(3, 2), GPIO_OUT_LOW)	/* USB3 Redriver Power control. Only used by Sona. */
-
-/* Sensors */
-
-/* Trackpad */
-GPIO(TP_INT_EN,			PIN(A, 1), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED1,			PIN(A, 7), GPIO_OUT_LOW)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)	/* GPIO64-65 UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)	/* GPIO87 EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)	/* GPIO90 EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)	/* GPIO91-92 EC_I2C2_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)	/* GPIOB4-B5 EC_I2C0_0_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)	/* GPOPB2-B3 EC_I2C0_1_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)	/* GPIOD0-D1 EC_I2C3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)	/* GPIOB6 PWM1 Fan control */
-ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)	/* GPIO80 PWM3 LED White */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)	/* GPIOB7 PWM5 LED Yellow */
-ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0)	/* GPIOA6 TA2 */
-ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0)	/* GPIOC4 PWM2 */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2,			PIN(1, 7), GPIO_OUT_LOW)
diff --git a/board/nami/led.c b/board/nami/led.c
deleted file mode 100644
index 17af4d5f82..0000000000
--- a/board/nami/led.c
+++ /dev/null
@@ -1,613 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Nami and its variants
- *
- * This is an event-driven LED control library. It does not use tasks or
- * periodical hooks (HOOK_TICK, HOOK_SECOND), thus, it's more resource
- * efficient.
- *
- * The library defines LED states and assigns an LED behavior to each state.
- * The state space consists of tuple of (charge state, power state).
- * In each LED state, a color and a pulse interval can be defined.
- *
- * Charging states are queried each time there is a state transition, thus, not
- * stored. We hook power state transitions (e.g. s0->s3) and save the
- * destination states (e.g. s3) in power_state.
- *
- * When system is suspending and AC is unplugged, there will be race condition
- * between a power state hook and a charge state hook but whichever is called
- * first or last the result will be the same.
- *
- * Currently, it supports two LEDs, called 'battery LED' and 'power LED'.
- * It assumes the battery LED is connected to a PWM pin and the power LED is
- * connected to a regular GPIO pin.
- */
-
-#include "cros_board_info.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "power.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-		EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-	LED_WHITE,
-	LED_WARM_WHITE,
-	LED_FACTORY,
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-/* Charging states of LED's interests */
-enum led_charge_state {
-	LED_STATE_DISCHARGE = 0,
-	LED_STATE_CHARGE,
-	LED_STATE_FULL,
-	LED_CHARGE_STATE_COUNT,
-};
-
-/* Power states of LED's interests */
-enum led_power_state {
-	LED_STATE_S0 = 0,
-	LED_STATE_S3,
-	LED_STATE_S5,
-	LED_POWER_STATE_COUNT,
-};
-
-/* Defines a LED pattern for a single state */
-struct led_pattern {
-	uint8_t color;
-	/* Bit 0-5: Interval in 100 msec. 0=solid. Max is 3.2 sec.
-	 * Bit 6: 1=alternate (on-off-off-off), 0=regular (on-off-on-off)
-	 * Bit 7: 1=pulse, 0=blink */
-	uint8_t pulse;
-};
-
-#define PULSE_NO		0
-#define PULSE(interval)		(BIT(7) | (interval))
-#define BLINK(interval) 	(interval)
-#define ALTERNATE(interval)	(BIT(6) | (interval))
-#define IS_PULSING(pulse)	((pulse) & 0x80)
-#define IS_ALTERNATE(pulse)	((pulse) & 0x40)
-#define PULSE_INTERVAL(pulse)	(((pulse) & 0x3f) * 100 * MSEC)
-
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT]
-					[LED_POWER_STATE_COUNT];
-
-/*
- * Nami/Vayne - One dual color LED:
- * Charging               Amber on (S0/S3/S5)
- * Charging (full)        White on (S0/S3/S5)
- * Discharge in S0        White on
- * Discharge in S3/S0ix   Pulsing (rising for 2 sec , falling for 2 sec)
- * Discharge in S5        Off
- * Battery Error          Amber on 1sec off 1sec
- * Factory mode	          White on 2sec, Amber on 2sec
- */
-const static led_patterns battery_pattern_0 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(10)}, {LED_OFF,  PULSE_NO}},
-	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
-};
-
-/*
- * Sona - Battery LED (dual color)
- */
-const static led_patterns battery_pattern_1 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
-	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
-};
-
-/*
- * Pantheon - AC In/Battery LED(dual color):
- * Connected to AC power / Charged (100%)        White (solid on)
- * Connected to AC power / Charging(1% -99%)     Amber (solid on)
- * Not connected to AC power                     Off
- */
-const static led_patterns battery_pattern_2 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
-	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
-};
-
-/*
- * Sona - Power LED (single color)
- */
-const static led_patterns power_pattern_1 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
-	/* charging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
-};
-
-/*
- * Pantheon - Power LED
- * S0:        White on
- * S3/S0ix:   White 1 second on, 3 second off
- * S5:        Off
- */
-const static led_patterns power_pattern_2 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
-	/* charging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
-};
-
-/*
- * Akali - battery LED
- * Charge:           Amber on (s0/s3/s5)
- * Full:             Blue on (s0/s3/s5)
- * Discharge in S0:  Blue on
- * Discharge in S3:  Amber on 1 sec off 3 sec
- * Discharge in S5:  Off
- * Battery Error:    Amber on 1sec off 1sec
- * Factory mode :    Blue on 2sec, Amber on 2sec
- */
-const static led_patterns battery_pattern_3 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_AMBER, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
-	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER,  PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE,  PULSE_NO}},
-};
-
-const static led_patterns battery_pattern_4 = {
-	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
-	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO},  {LED_AMBER, PULSE_NO}},
-	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO},  {LED_WHITE, PULSE_NO}},
-};
-
-/* Patterns for battery LED and power LED. Initialized at run-time. */
-static led_patterns const *patterns[2];
-/* Pattern for battery error. Only blinking battery LED is supported. */
-static struct led_pattern battery_error = {LED_AMBER, BLINK(10)};
-/* Pattern for low state of charge. Only battery LED is supported. */
-static struct led_pattern low_battery = {LED_WHITE, BLINK(10)};
-/* Pattern for factory mode. Blinking 2-color battery LED. */
-static struct led_pattern battery_factory = {LED_FACTORY, BLINK(20)};
-static int low_battery_soc;
-static void led_charge_hook(void);
-static enum led_power_state power_state;
-
-static void led_init(void)
-{
-	switch (oem) {
-	case PROJECT_NAMI:
-	case PROJECT_VAYNE:
-		patterns[0] = &battery_pattern_0;
-		break;
-	case PROJECT_SONA:
-		if (model == MODEL_SYNDRA) {
-			/* Syndra doesn't have power LED */
-			patterns[0] = &battery_pattern_4;
-		} else {
-			patterns[0] = &battery_pattern_1;
-			patterns[1] = &power_pattern_1;
-		}
-		battery_error.pulse = BLINK(5);
-		low_battery_soc = 100;  /* 10.0% */
-		break;
-	case PROJECT_PANTHEON:
-		patterns[0] = &battery_pattern_2;
-		patterns[1] = &power_pattern_2;
-		battery_error.color = LED_OFF;
-		battery_error.pulse = 0;
-		break;
-	case PROJECT_AKALI:
-		patterns[0] = &battery_pattern_3;
-		break;
-	default:
-		break;
-	}
-
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_enable(PWM_CH_LED2, 1);
-
-	/* After sysjump, power_state is cleared. Thus, we need to actively
-	 * retrieve it. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		power_state = LED_STATE_S5;
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		power_state = LED_STATE_S3;
-	else
-		power_state = LED_STATE_S0;
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-static int set_color_battery(enum led_color color, int duty)
-{
-	int led1 = 0;
-	int led2 = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_AMBER:
-		led2 = 1;
-		break;
-	case LED_WHITE:
-		led1 = 1;
-		break;
-	case LED_WARM_WHITE:
-		led1 = 1;
-		led2 = 1;
-		break;
-	case LED_FACTORY:
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (color != LED_FACTORY) {
-		pwm_set_duty(PWM_CH_LED1, led1 ? duty : 0);
-		pwm_set_duty(PWM_CH_LED2, led2 ? duty : 0);
-	} else {
-		pwm_set_duty(PWM_CH_LED1, duty ? 100 : 0);
-		pwm_set_duty(PWM_CH_LED2, duty ? 0 : 100);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int set_color_power(enum led_color color, int duty)
-{
-	if (color == LED_OFF)
-		duty = 0;
-	gpio_set_level(GPIO_LED1, !duty /* Reversed logic */);
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_BATTERY_LED:
-		return set_color_battery(color, duty);
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-	int alternate;
-	uint8_t pulse;
-} tick[2];
-
-static void tick_battery(void);
-DECLARE_DEFERRED(tick_battery);
-static void tick_power(void);
-DECLARE_DEFERRED(tick_power);
-static void cancel_tick(enum ec_led_id id)
-{
-	if (id == EC_LED_ID_BATTERY_LED)
-		hook_call_deferred(&tick_battery_data, -1);
-	else
-		hook_call_deferred(&tick_power_data, -1);
-}
-
-static int config_tick(enum ec_led_id id, const struct led_pattern *pattern)
-{
-	static const struct led_pattern *patterns[2];
-	uint32_t stride;
-
-	if (pattern == patterns[id])
-		/* This pattern was already set */
-		return -1;
-
-	patterns[id] = pattern;
-
-	if (!pattern->pulse) {
-		/* This is a steady pattern. cancel the tick */
-		cancel_tick(id);
-		set_color(id, pattern->color, 100);
-		return 1;
-	}
-
-	stride = PULSE_INTERVAL(pattern->pulse);
-	if (IS_PULSING(pattern->pulse)) {
-		tick[id].interval = LED_PULSE_TICK_US;
-		tick[id].duty_inc = 100 / (stride / LED_PULSE_TICK_US);
-	} else {
-		tick[id].interval = stride;
-		tick[id].duty_inc = 100;
-	}
-	tick[id].color = pattern->color;
-	tick[id].duty = 0;
-	tick[id].alternate = 0;
-	tick[id].pulse = pattern->pulse;
-
-	return 0;
-}
-
-/*
- * When pulsing, brightness is incremented by <duty_inc> every <interval> usec
- * from 0 to 100%. Then it's decremented from 100% to 0.
- */
-static void pulse_led(enum ec_led_id id)
-{
-	if (tick[id].duty + tick[id].duty_inc > 100) {
-		tick[id].duty_inc = tick[id].duty_inc * -1;
-	} else if (tick[id].duty + tick[id].duty_inc < 0) {
-		if (IS_ALTERNATE(tick[id].pulse)) {
-			/* Falling phase landing. Flip the alternate flag. */
-			tick[id].alternate = !tick[id].alternate;
-			if (tick[id].alternate)
-				return;
-		}
-		tick[id].duty_inc = tick[id].duty_inc * -1;
-	}
-	tick[id].duty += tick[id].duty_inc;
-	set_color(id, tick[id].color, tick[id].duty);
-}
-
-static uint32_t tick_led(enum ec_led_id id)
-{
-	uint32_t elapsed;
-	uint32_t start = get_time().le.lo;
-	uint32_t next;
-
-	if (led_auto_control_is_enabled(id))
-		pulse_led(id);
-	if (tick[id].alternate)
-		/* Skip 2 phases (rising & falling) */
-		next = PULSE_INTERVAL(tick[id].pulse) * 2;
-	else
-		next = tick[id].interval;
-	elapsed = get_time().le.lo - start;
-	return next > elapsed ? next - elapsed : 0;
-}
-
-static void tick_battery(void)
-{
-	hook_call_deferred(&tick_battery_data, tick_led(EC_LED_ID_BATTERY_LED));
-}
-
-static void tick_power(void)
-{
-	hook_call_deferred(&tick_power_data, tick_led(EC_LED_ID_POWER_LED));
-}
-
-static void start_tick(enum ec_led_id id, const struct led_pattern *pattern)
-{
-	if (config_tick(id, pattern))
-		/*
-		 * If this pattern is already active, ticking must have started
-		 * already. So, we don't re-start ticking to prevent LED from
-		 * blinking at every SOC change.
-		 *
-		 * If this pattern is static, we skip ticking as well.
-		 */
-		return;
-
-	if (id == EC_LED_ID_BATTERY_LED)
-		tick_battery();
-	else
-		tick_power();
-}
-
-static void led_alert(int enable)
-{
-	if (enable)
-		start_tick(EC_LED_ID_BATTERY_LED, &battery_error);
-	else
-		led_charge_hook();
-}
-
-static void led_factory(int enable)
-{
-	if (enable)
-		start_tick(EC_LED_ID_BATTERY_LED, &battery_factory);
-	else
-		led_charge_hook();
-}
-
-void config_led(enum ec_led_id id, enum led_charge_state charge)
-{
-	const led_patterns *pattern;
-
-	pattern = patterns[id];
-	if (!pattern)
-		return;	/* This LED isn't present */
-
-	start_tick(id, &(*pattern)[charge][power_state]);
-}
-
-void config_leds(enum led_charge_state charge)
-{
-	config_led(EC_LED_ID_BATTERY_LED, charge);
-	config_led(EC_LED_ID_POWER_LED, charge);
-}
-
-static void call_handler(void)
-{
-	int soc;
-	enum charge_state cs;
-
-	if (!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		return;
-
-	cs = charge_get_state();
-	soc = charge_get_display_charge();
-	if (soc < 0)
-		cs = PWR_STATE_ERROR;
-
-	switch (cs) {
-	case PWR_STATE_DISCHARGE:
-	case PWR_STATE_DISCHARGE_FULL:
-		if (soc < low_battery_soc)
-			start_tick(EC_LED_ID_BATTERY_LED, &low_battery);
-		else
-			config_led(EC_LED_ID_BATTERY_LED, LED_STATE_DISCHARGE);
-		config_led(EC_LED_ID_POWER_LED, LED_STATE_DISCHARGE);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_CHARGE:
-		if (soc >= 1000)
-			config_leds(LED_STATE_FULL);
-		else
-			config_leds(LED_STATE_CHARGE);
-		break;
-	case PWR_STATE_ERROR:
-		/* It doesn't matter what 'charge' state we pass because power
-		 * LED (if it exists) is orthogonal to battery state. */
-		config_led(EC_LED_ID_POWER_LED, 0);
-		led_alert(1);
-		break;
-	case PWR_STATE_IDLE:
-		/* External power connected in IDLE. This is also used to show
-		 * factory mode when 'ectool chargecontrol idle' is run during
-		 * factory process. */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_factory(1);
-		break;
-	default:
-		;
-	}
-}
-
-/* LED state transition handlers */
-static void s0(void)
-{
-	power_state = LED_STATE_S0;
-	call_handler();
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, s0, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, s0, HOOK_PRIO_DEFAULT);
-
-static void s3(void)
-{
-	power_state = LED_STATE_S3;
-	call_handler();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, s3, HOOK_PRIO_DEFAULT);
-
-static void s5(void)
-{
-	power_state = LED_STATE_S5;
-	call_handler();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, s5, HOOK_PRIO_DEFAULT);
-
-static void led_charge_hook(void)
-{
-	call_handler();
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, led_charge_hook, HOOK_PRIO_DEFAULT);
-
-static void print_config(enum ec_led_id id)
-{
-	ccprintf("ID:%d\n", id);
-	ccprintf("  Color:%d\n", tick[id].color);
-	ccprintf("  Duty:%d\n", tick[id].duty);
-	ccprintf("  Duty Increment:%d\n", tick[id].duty_inc);
-	ccprintf("  Interval:%d\n", tick[id].interval);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_BATTERY_LED;
-	static int alert = 0;
-	static int factory;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		alert = !alert;
-		led_alert(alert);
-	} else if (!strcasecmp(argv[1], "s0")) {
-		s0();
-	} else if (!strcasecmp(argv[1], "s3")) {
-		s3();
-	} else if (!strcasecmp(argv[1], "s5")) {
-		s5();
-	} else if (!strcasecmp(argv[1], "conf")) {
-		print_config(id);
-	} else if (!strcasecmp(argv[1], "factory")) {
-		factory = !factory;
-		led_factory(factory);
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	/*
-	 * We return amber=100, white=100 regardless of OEM ID or led_id. This
-	 * function is for ectool led command, which is used to test LED
-	 * functionality.
-	 */
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/nami/usb_pd_policy.c b/board/nami/usb_pd_policy.c
deleted file mode 100644
index c1d5591d7c..0000000000
--- a/board/nami/usb_pd_policy.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	gpio_set_level(port ? GPIO_USB_C1_3A_EN : GPIO_USB_C0_3A_EN,
-		       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN,
-		       vbus_en[port]);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
-				      GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_ID, (data_role == PD_ROLE_UFP) ? 0 : 1);
-}
diff --git a/board/nami/vif_override.xml b/board/nami/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nami/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nami_fp b/board/nami_fp
deleted file mode 120000
index 1095b5f7b4..0000000000
--- a/board/nami_fp
+++ /dev/null
@@ -1 +0,0 @@
-./nocturne_fp/
\ No newline at end of file
diff --git a/board/nautilus/analyzestack.yaml b/board/nautilus/analyzestack.yaml
deleted file mode 100644
index c9004e6376..0000000000
--- a/board/nautilus/analyzestack.yaml
+++ /dev/null
@@ -1,211 +0,0 @@
-# Size of extra stack frame needed by exception context switch.
-# See core/cortex-m/switch.S
-exception_frame_size: 224
-# Add some missing calls.
-add:
-  # TCPC stuff:
-  tcpm_init.lto_priv.255[driver/tcpm/tcpm.h:77]:
-    - tcpci_tcpm_init
-  tcpm_release[driver/tcpm/tcpm.h:90]:
-    - ps8xxx_tcpm_release
-  tcpm_get_cc.lto_priv.246[driver/tcpm/tcpm.h:95]:
-    - tcpci_tcpm_get_cc
-  tcpm_select_rp_value[driver/tcpm/tcpm.h:105]:
-    - tcpci_tcpm_select_rp_value
-  tcpm_set_cc.lto_priv.239[driver/tcpm/tcpm.h:110]:
-    - tcpci_tcpm_set_cc
-  tcpm_set_polarity[driver/tcpm/tcpm.h:115]:
-    - tcpci_tcpm_set_polarity
-  tcpm_set_vconn.lto_priv.249[driver/tcpm/tcpm.h:120]:
-    - tcpci_tcpm_set_vconn
-  tcpm_set_msg_header[driver/tcpm/tcpm.h:125]:
-    - tcpci_tcpm_set_msg_header
-  tcpm_set_rx_enable.lto_priv.252[driver/tcpm/tcpm.h:131]:
-    - tcpci_tcpm_set_rx_enable
-  tcpm_get_message[driver/tcpm/tcpm.h:136]:
-    - tcpci_tcpm_get_message
-  tcpm_transmit[driver/tcpm/tcpm.h:142]:
-    - ps8xxx_tcpm_transmit
-  tcpc_alert[driver/tcpm/tcpm.h:147]:
-    - tcpci_tcpc_alert
-  tcpc_discharge_vbus[driver/tcpm/tcpm.h:152]:
-    - tcpci_tcpc_discharge_vbus
-  tcpm_set_drp_toggle[driver/tcpm/tcpm.h:163]:
-    - tcpci_tcpc_drp_toggle
-  tcpm_get_chip_info[driver/tcpm/tcpm.h:185]:
-    - tcpci_get_chip_info
-  board_tcpc_init[board/nautilus/board.c:233]:
-    - ps8xxx_tcpc_update_hpd_status
-  tcpci_tcpc_drp_toggle[driver/tcpm/tcpci.c:148]:
-    - None
-  # USB mux stuff
-  usb_mux_init[driver/usb_mux.c:25]:
-    - tcpci_tcpm_mux_init
-  usb_mux_init[driver/usb_mux.c:31]:
-    - None
-  usb_mux_set[driver/usb_mux.c:52]:
-    - tcpci_tcpm_mux_set
-  usb_mux_get[driver/usb_mux.c:71]:
-    - tcpci_tcpm_mux_get
-  usb_mux_flip[driver/usb_mux.c:92]:
-    - tcpci_tcpm_mux_get
-  usb_mux_flip[driver/usb_mux.c:103]:
-    - tcpci_tcpm_mux_set
-  hc_usb_pd_mux_info[driver/usb_mux.c:169]:
-    - tcpci_tcpm_mux_get
-  svdm_dp_post_config.lto_priv.271[board/nautilus/usb_pd_policy.c:363]:
-    - ps8xxx_tcpc_update_hpd_status
-  svdm_dp_attention.lto_priv.272[board/nautilus/usb_pd_policy.c:378]:
-    - ps8xxx_tcpc_update_hpd_status
-  svdm_exit_dp_mode.lto_priv.273[board/nautilus/usb_pd_policy.c:389]:
-    - ps8xxx_tcpc_update_hpd_status
-  # pd_svdm
-  pd_dfp_enter_mode[common/usb_pd_policy.c:459]:
-    - svdm_enter_dp_mode
-  dfp_consume_attention.lto_priv.259[common/usb_pd_policy.c:497]:
-    - svdm_dp_attention
-  pd_dfp_exit_mode[common/usb_pd_policy.c:563]:
-    - svdm_exit_dp_mode
-  pd_dfp_exit_mode[common/usb_pd_policy.c:580]:
-    - svdm_exit_dp_mode
-  pd_svdm[common/usb_pd_policy.c:767]:
-    - svdm_dp_status
-  pd_svdm[common/usb_pd_policy.c:778]:
-    - svdm_dp_config
-  pd_svdm[common/usb_pd_policy.c:784]:
-    - svdm_dp_post_config
-  # Motion sense
-  queue_advance_head[common/queue.c:105]:
-    - queue_action_null
-  queue_advance_tail[common/queue.c:116]:
-    - queue_action_null
-  motion_sense_set_data_rate[common/motion_sense.c:270]:
-    - set_data_rate[driver/accelgyro_bmi160.c]
-    - set_data_rate[driver/accel_bma2x2.c]
-  motion_sense_set_data_rate[common/motion_sense.c:289]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - get_data_rate[driver/accel_bma2x2.c]
-  motion_sense_set_ec_rate_from_ap[common/motion_sense.c:308]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - get_data_rate[driver/accel_bma2x2.c]
-  motion_sense_set_motion_intervals.lto_priv.303[common/motion_sense.c:414]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - get_data_rate[driver/accel_bma2x2.c]
-  motion_sense_init[common/motion_sense.c:450]:
-    - init[driver/accelgyro_bmi160.c]
-    - init[driver/accel_bma2x2.c]
-  sensor_init_done[common/motion_sense.c:471]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - set_range[driver/accel_bma2x2.c]
-  sensor_init_done[common/motion_sense.c:474]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  motion_sense_process.isra.9[common/motion_sense.c:721]:
-    - irq_handler[driver/accelgyro_bmi160.c]
-  host_cmd_motion_sense[common/motion_sense.c:1251]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - set_range[driver/accel_bma2x2.c]
-  host_cmd_motion_sense[common/motion_sense.c:1259]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  host_cmd_motion_sense[common/motion_sense.c:1274]:
-    - set_offset[driver/accelgyro_bmi160.c]
-    - set_offset[driver/accel_bma2x2.c]
-  host_cmd_motion_sense[common/motion_sense.c:1297]:
-    - perform_calib[driver/accelgyro_bmi160.c]
-  host_cmd_motion_sense[common/motion_sense.c:1300]:
-    - get_offset[driver/accelgyro_bmi160.c]
-    - get_offset[driver/accel_bma2x2.c]
-  command_accelrange[common/motion_sense.c:1515]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - set_range[driver/accel_bma2x2.c]
-  command_accelrange[common/motion_sense.c:1520]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  host_cmd_motion_sense[common/motion_sense.c:1520]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  command_accelresolution[common/motion_sense.c:1564]:
-    - None
-  command_accelresolution[common/motion_sense.c:1568]:
-    - get_resolution[driver/accelgyro_bmi160.c]
-    - get_resolution[driver/accel_bma2x2.c]
-  command_accel_data_rate[common/motion_sense.c:1623]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - get_data_rate[driver/accel_bma2x2.c]
-  command_accel_read_xyz[common/motion_sense.c:1659]:
-    - read[driver/accelgyro_bmi160.c]
-    - read[driver/accel_bma2x2.c]
-  calculate_lid_angle[common/motion_lid.c:255]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  calculate_lid_angle[common/motion_lid.c:256]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - get_range[driver/accel_bma2x2.c]
-  # Temp (see temp_sensors array in board file)
-  temp_sensor_read[common/temp_sensor.c:26]:
-    - charge_get_battery_temp
-    - bd99992gw_get_val
-  # Misc
-  jump_to_image[common/system.c:568]:
-    - None
-  system_download_from_flash[chip/npcx/system-npcx5.c:257]:
-    - None
-  __hibernate_npcx_series[chip/npcx/system-npcx5.c:144]:
-    - None
-  handle_command[common/console.c:248]:
-    - { name: __cmds, stride: 16, offset: 4 }
-  hook_task[common/hooks.c:197]:
-    - { name: __deferred_funcs, stride: 4, offset: 0 }
-    - { name: __hooks_second, stride: 8, offset: 0 }
-    - { name: __hooks_tick, stride: 8, offset: 0 }
-  # Note: This assumes worse case, where all hook functions can be called from
-  # any hook_notify call
-  # Generate using `grep hooks_.*_end build/nautilus/R*/ec.R*.smap |
-  #   sed -e 's/.*\(__hooks.*\)_end/    - { name: \1, stride: 8, offset: 0 }/' |
-  #   sort -u`
-  hook_notify[common/hooks.c:127]:
-    - { name: __hooks_ac_change, stride: 8, offset: 0 }
-    - { name: __hooks_battery_soc_change, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_pre_init, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_reset, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_resume, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_shutdown, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_startup, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_suspend, stride: 8, offset: 0 }
-    - { name: __hooks_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_lid_change, stride: 8, offset: 0 }
-    - { name: __hooks_pre_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_pwrbtn_change, stride: 8, offset: 0 }
-    - { name: __hooks_sysjump, stride: 8, offset: 0 }
-    - { name: __hooks_tablet_mode_change, stride: 8, offset: 0 }
-  mkbp_get_next_event[common/mkbp_event.c:130]:
-    - { name:  __mkbp_evt_srcs, stride: 8, offset: 4 }
-  host_send_response[common/host_command.c:153]:
-    - lpc_send_response
-  host_packet_respond[common/host_command.c:240]:
-    - lpc_send_response
-  host_command_process[common/host_command.c:704]:
-    - { name: __hcmds, stride: 12, offset: 0 }
-  # gpio_interrupt.lto_priv.407[chip/npcx/gpio.c:479]
-  vfnprintf:
-    # This covers all the addchar in vfnprintf, but stackanalyzer does not
-    # realize that...
-    - __tx_char
-  i2c_command_passthru[common/i2c_master.c:597]:
-    - None
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
-# Remove hook paths that don't make sense
-- [ [ common_intel_x86_power_handle_state, power_button_change_deferred, hook_task, lpc_chipset_reset, espi_chipset_reset ], hook_notify, powerbtn_x86_lid_change ]
-- [ system_common_shutdown, hook_notify, system_run_image_copy ]
-- [ jump_to_image, hook_notify, [ powerbtn_x86_lid_change, system_common_shutdown, power_up_inhibited_cb, motion_sense_shutdown, motion_sense_resume ] ]
-- [ [ extpower_deferred, charger_task, motion_sense_switch_sensor_rate, lid_switch_open, lid_switch_close, motion_sense_task ], hook_notify, [ powerbtn_x86_lid_change, power_up_inhibited_cb, system_common_shutdown, motion_sense_shutdown, motion_sense_resume ] ]
-- [ common_intel_x86_power_handle_state, hook_notify, power_up_inhibited_cb ]
-# pd_request_power_swap calls set_state with either PD_STATE_SRC_SWAP_INIT or
-# PD_STATE_SNK_SWAP_INIT as parameters, which cannot call any of the
-# charge_manager functions.
-- [ [ pd_request_power_swap, pd_execute_hard_reset, pd_request_data_swap, pd_request_vconn_swap.lto_priv.237, pd_send_request_msg.lto_priv.250 ], set_state.lto_priv.236, [ typec_set_input_current_limit, charge_manager_update_charge, pd_power_supply_reset, pd_dfp_exit_mode, usb_mux_set ] ]
-# Debug prints that do not actually need a 64 uint division, of the time
-- [ [i2c_reset, i2c_abort_data, i2c_xfer], cprintf, vfnprintf, [uint64divmod.part.3.lto_priv.141, get_time] ]
diff --git a/board/nautilus/battery.c b/board/nautilus/battery.c
deleted file mode 100644
index 642497cdfe..0000000000
--- a/board/nautilus/battery.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "util.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-/* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-
-/*
- * Unlike other smart batteries, Nautilus battery uses different bit fields
- * in manufacturer access register for the conditions of the CHG/DSG FETs.
- */
-#define BATFETS_SHIFT		(14)
-#define BATFETS_MASK		(0x3)
-#define BATFETS_DISABLED	(0x2)
-
-#define CHARGING_VOLTAGE_MV_SAFE	8400
-#define CHARGING_CURRENT_MA_SAFE	1500
-
-static const struct battery_info info = {
-	.voltage_max = 8700,
-	.voltage_normal = 7700,
-	.voltage_min = 6000,
-	/* Pre-charge values. */
-	.precharge_current = 200, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 50,
-	.discharging_min_c = -20,
-	.discharging_max_c = 70,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int current;
-	int voltage;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
-	 * ---+------+--------+--------+------+--- Temperature (C)
-	 *    0      5        12       45     50
-	 */
-	enum {
-		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
-		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
-		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
-		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
-		TEMP_ZONE_COUNT,
-		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
-	} temp_zone;
-
-	current = curr->requested_current;
-	voltage = curr->requested_voltage;
-	bat_temp_c = curr->batt.temperature - 2731;
-
-	/*
-	 * If the temperature reading is bad, assume the temperature
-	 * is out of allowable range.
-	 */
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < 0) || (bat_temp_c > 500))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else if (bat_temp_c <= 50)
-		temp_zone = TEMP_ZONE_0;
-	else if (bat_temp_c <= 120)
-		temp_zone = TEMP_ZONE_1;
-	else if (bat_temp_c <= 450)
-		temp_zone = TEMP_ZONE_2;
-	else
-		temp_zone = TEMP_ZONE_3;
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-	case TEMP_ZONE_1:
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-	case TEMP_ZONE_2:
-		break;
-	case TEMP_ZONE_3:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		/* Don't charge if outside of allowable temperature range */
-		current = 0;
-		voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-		break;
-	}
-
-	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
-	curr->requested_current = MIN(curr->requested_current, current);
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATTERY_PRESENT_L) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Check for case where both XCHG and XDSG bits are set indicating that even
- * though the FG can be read from the battery, the battery is not able to be
- * charged or discharged. This situation might happen when power is reconnected
- * to a battery pack in sleep mode. In this transient siuation, the FG can be
- * read, but the battery is still not able to provide power to the system. The
- * calling function returns batt_pres = BP_NO, which instructs the charging
- * state machine to prevent powering up the AP on battery alone which could lead
- * to a brownout event when the battery isn't able yet to provide power to the
- * system.
- */
-static int battery_check_disconnect(void)
-{
-	int rv;
-	int batt_mfgacc;
-
-	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read(SB_MANUFACTURER_ACCESS, &batt_mfgacc);
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) ==
-	    BATFETS_DISABLED)
-		return BATTERY_DISCONNECTED;
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * successful & the battery status is initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-	    (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	     battery_check_disconnect() != BATTERY_NOT_DISCONNECTED ||
-	     battery_init() == 0)) {
-		batt_pres = BP_NO;
-	}
-
-	batt_pres_prev = batt_pres;
-	return batt_pres;
-}
-
diff --git a/board/nautilus/board.c b/board/nautilus/board.c
deleted file mode 100644
index bcdaf568e7..0000000000
--- a/board/nautilus/board.c
+++ /dev/null
@@ -1,781 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Poppy board-specific configuration */
-
-#include "adc.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "battery_smart.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/baro_bmp280.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/bd99992gw.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	if ((signal == GPIO_USB_C0_PD_INT_ODL) &&
-	    !gpio_get_level(GPIO_USB_C0_PD_RST_L))
-		return;
-	else if ((signal == GPIO_USB_C1_PD_INT_ODL) &&
-		 !gpio_get_level(GPIO_USB_C1_PD_RST_L))
-		return;
-
-#ifdef HAS_TASK_PDCMD
-	/* Exchange status with TCPCs */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-#endif
-}
-
-/* Set PD discharge whenever VBUS detection is high (i.e. below threshold). */
-static void vbus_discharge_handler(void)
-{
-	if (system_get_board_version() >= 2) {
-		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
-	}
-}
-DECLARE_DEFERRED(vbus_discharge_handler);
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_0,
-		.mux_lock = NULL,
-	},
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_1,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-        GPIO_USB1_ENABLE,
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(1);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-	}
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-static void board_pmic_disable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (0)   - Disable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x3a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x2a);
-
-	/*
-	 * V100ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (01) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x3a);
-}
-
-static void board_pmic_enable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (1)   - Enable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x7a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x6a);
-
-	/*
-	 * V100ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (01) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x5a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
-}
-
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
-		board_pmic_enable_slp_s0_vr_decay();
-	else if (state == HOST_SLEEP_EVENT_S0IX_RESUME)
-		board_pmic_disable_slp_s0_vr_decay();
-}
-
-static void board_pmic_init(void)
-{
-	board_report_pmic_fault("SYSJUMP");
-
-	if (system_jumped_late())
-		return;
-
-	/* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x04);
-
-	board_pmic_disable_slp_s0_vr_decay();
-
-	/* VRMODECTRL - disable low-power mode for all rails */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x1f);
-}
-DECLARE_DEFERRED(board_pmic_init);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
-	 * whenever the EC is not doing SPI flash transactions. This avoids
-	 * floating SPI buffer input (MISO), which causes power leakage (see
-	 * b/64797021).
-	 */
-	NPCX_PUPD_EN1 |= BIT(NPCX_DEVPU1_F_SPI_PUD_EN);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-
-	/* Enable VBUS interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
-
-	/* Enable pericom BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Level of sensor's I2C and interrupt are 3.3V on proto board */
-	if(system_get_board_version() < 2) {
-		/* ACCELGYRO3_INT_L */
-		gpio_set_flags(GPIO_ACCELGYRO3_INT_L, GPIO_INT_FALLING);
-		/* I2C3_SCL / I2C3_SDA */
-		gpio_set_flags(GPIO_I2C3_SCL, GPIO_INPUT);
-		gpio_set_flags(GPIO_I2C3_SDA, GPIO_INPUT);
-        }
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
-
-	/* Initialize PMIC */
-	hook_call_deferred(&board_pmic_init_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Buffer the AC present GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source VBUS on the port */
-	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
-						       GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTF("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-        /*
-         * Limit the input current to 96% negotiated limit,
-         * to account for the charger chip margin.
-         */
-	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return the maximum allowed input current
- */
-int board_get_ramp_current_limit(int supplier, int sup_curr)
-{
-	switch (supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-		return 2000;
-	case CHARGE_SUPPLIER_BC12_SDP:
-		return 1000;
-	case CHARGE_SUPPLIER_BC12_CDP:
-	case CHARGE_SUPPLIER_PROPRIETARY:
-		return sup_curr;
-	default:
-		return 500;
-	}
-}
-
-void board_hibernate(void)
-{
-	CPRINTS("Triggering PMIC shutdown.");
-	uart_flush_output();
-
-    /* Trigger PMIC shutdown. */
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
-		/*
-		 * If we can't tell the PMIC to shutdown, instead reset
-		 * and don't start the AP. Hopefully we'll be able to
-		 * communicate with the PMIC next time.
-		 */
-		CPRINTS("PMIC i2c failed.");
-		system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
-	}
-
-	/* Await shutdown. */
-	while (1)
-		;
-}
-
-int board_get_version(void)
-{
-	static int ver = -1;
-	uint8_t id3;
-
-	if (ver != -1)
-		return ver;
-
-	ver = 0;
-
-	/* First 2 strappings are binary. */
-	if (gpio_get_level(GPIO_BOARD_VERSION1))
-		ver |= 0x01;
-	if (gpio_get_level(GPIO_BOARD_VERSION2))
-		ver |= 0x02;
-
-	/*
-	 * The 3rd strapping pin is tristate.
-	 * id3 = 2 if Hi-Z, id3 = 1 if high, and id3 = 0 if low.
-	 */
-	id3 = gpio_get_ternary(GPIO_BOARD_VERSION3);
-	ver |= id3 * 0x04;
-
-	CPRINTS("Board ID = %d", ver);
-
-	return ver;
-}
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	/* Enable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-
-	gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
-
-	gpio_set_level(GPIO_PP1800_DX_SENSOR, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_shutdown(void)
-{
-	/* Disable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-
-	gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
-
-	gpio_set_level(GPIO_PP1800_DX_SENSOR, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_has_working_reset_flags(void)
-{
-	int version = system_get_board_version();
-
-	/* Boards Rev1, Rev2 and Rev3 will lose reset flags on power cycle. */
-	if ((version == 1) || (version == 2) || (version == 3))
-		return 0;
-
-	/* All other board versions should have working reset flags */
-	return 1;
-}
-
-/*
- * I2C callbacks to ensure bus free time for battery I2C transactions is at
- * least 5ms.
- */
-#define BATTERY_FREE_MIN_DELTA_US		(5 * MSEC)
-static timestamp_t battery_last_i2c_time;
-
-static int is_battery_i2c(const int port, const uint16_t slave_addr_flags)
-{
-	return (port == I2C_PORT_BATTERY)
-		&& (slave_addr_flags == BATTERY_ADDR_FLAGS);
-}
-
-void i2c_start_xfer_notify(const int port, const uint16_t slave_addr_flags)
-{
-	unsigned int time_delta_us;
-
-	if (!is_battery_i2c(port, slave_addr_flags))
-		return;
-
-	time_delta_us = time_since32(battery_last_i2c_time);
-	if (time_delta_us >= BATTERY_FREE_MIN_DELTA_US)
-		return;
-
-	usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
-}
-
-void i2c_end_xfer_notify(const int port, const uint16_t slave_addr_flags)
-{
-	if (!is_battery_i2c(port, slave_addr_flags))
-		return;
-
-	battery_last_i2c_time = get_time();
-}
diff --git a/board/nautilus/board.h b/board/nautilus/board.h
deleted file mode 100644
index 88389956b9..0000000000
--- a/board/nautilus/board.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
-#define CONFIG_DPTF
-#define CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
-#define CONFIG_DPTF_MULTI_PROFILE
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_XFER_BOARD_CALLBACK
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* Port80 */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW /* This, or just RAMP? */
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_ILIM_SEL
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/* USB */
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-
-/* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Nautilus doesn't have systherm0 and systherm3 */
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-int board_get_version(void);
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nautilus/build.mk b/board/nautilus/build.mk
deleted file mode 100644
index f4bf21113d..0000000000
--- a/board/nautilus/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/nautilus/ec.tasklist b/board/nautilus/ec.tasklist
deleted file mode 100644
index 8257734572..0000000000
--- a/board/nautilus/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 800) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, 720) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, 720) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, 800) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, 768) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, 800) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, 600) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, 800) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 840) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, 880) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, 800) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, 600) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1000) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1000)
diff --git a/board/nautilus/gpio.inc b/board/nautilus/gpio.inc
deleted file mode 100644
index 9cfc1e0bfd..0000000000
--- a/board/nautilus/gpio.inc
+++ /dev/null
@@ -1,125 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-/* Use VW signals instead of GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(6, 7), GPIO_INT_BOTH,			lid_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(WP_L,			PIN(4, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus0_evt)
-GPIO_INT(USB_C1_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus1_evt)
-GPIO_INT(USB_C0_BC12_INT_L,	PIN(D, 3), GPIO_INT_FALLING,			usb0_evt)
-GPIO_INT(USB_C1_BC12_INT_L,	PIN(3, 3), GPIO_INT_FALLING,			usb1_evt)
-GPIO_INT(ACCELGYRO3_INT_L,	PIN(3, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
-
-GPIO(ENABLE_TOUCHPAD,		PIN(4, 5), GPIO_OUT_LOW)
-GPIO(PCH_RTCRST,		PIN(2, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC (>= rev4) */
-GPIO(ENABLE_BACKLIGHT,		PIN(5, 6), GPIO_OUT_LOW)			/* Enable Backlight */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
-GPIO(PCH_ACOK,			PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(4, 1), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(A, 6), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(BATTERY_PRESENT_L,		PIN(3, 4), GPIO_INPUT)				/* Battery Present */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INPUT)
-#endif
-
-/* NC pins */
-GPIO(GPIO02_NC,			PIN(0, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO32_NC,			PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO71_NC,			PIN(7, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO80_NC,			PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD2_NC,			PIN(D, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Sensor Power */
-GPIO(PP1800_DX_SENSOR,		PIN(E, 7), GPIO_OUT_LOW)
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C0_0_USBC_3V3_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C0_0_USBC_3V3_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C0_1_USBC_3V3_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C0_1_USBC_3V3_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C1_3V3_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C1_3V3_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C2_PMIC_3V3_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C2_PMIC_3V3_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C3_SENSOR_1V8_SCL */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C3_SENSOR_1V8_SDA */
-
-/* rev0: 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW)			/* C0 5V Enable */
-GPIO(USB_C0_3A_EN,		PIN(6, 6), GPIO_OUT_LOW)			/* C0 Enable 3A */
-GPIO(USB_C0_CHARGE_L,		PIN(C, 0), GPIO_OUT_LOW)			/* C0 Charge enable */
-GPIO(USB_C1_5V_EN,		PIN(B, 1), GPIO_OUT_LOW)			/* C1 5V Enable */
-GPIO(USB_C1_3A_EN,		PIN(3, 5), GPIO_OUT_LOW)			/* C1 3A Enable */
-GPIO(USB_C1_CHARGE_L,		PIN(C, 3), GPIO_OUT_LOW)			/* C1 Charge enable */
-GPIO(USB_C0_PD_RST_L,		PIN(0, 3), GPIO_ODR_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(A, 5), GPIO_INPUT)				/* C1 DP Hotplug Detect */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB2_OTG_ID,		PIN(A, 1), GPIO_ODR_LOW)			/* OTG ID */
-GPIO(USB2_OTG_VBUSSENSE,	PIN(9, 5), GPIO_OUT_LOW)			/* OTG VBUS Sense */
-
-/* USB Type-A control */
-GPIO(USB_A_ILIM_SEL,		PIN(0, 0), GPIO_OUT_LOW)
-GPIO(USB1_ENABLE,		PIN(0, 1), GPIO_OUT_LOW)
-
-/* LEDs (2 colors on each port) */
-GPIO(LED_ACIN,			PIN(B, 6), GPIO_OUT_HIGH)			/* ACIN LED */
-GPIO(POWER_LED,			PIN(B, 7), GPIO_OUT_HIGH)			/* Power LED */
-GPIO(LED_CHARGE,		PIN(C, 6), GPIO_OUT_HIGH)			/* Charge LED */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(8, 6), GPIO_INPUT)				/* Board ID bit0 */
-GPIO(BOARD_VERSION2,		PIN(C, 2), GPIO_INPUT)				/* Board ID bit1 */
-GPIO(BOARD_VERSION3,		PIN(C, 4), GPIO_INPUT)				/* Board ID bit2 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_USBC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, 0)
-GPIO(KBD_KSO2,			PIN(1, 7), GPIO_OUT_LOW)
diff --git a/board/nautilus/led.c b/board/nautilus/led.c
deleted file mode 100644
index 86567701f0..0000000000
--- a/board/nautilus/led.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-#define LED_TOTAL_TICKS 16
-#define LED_ON_TICKS 8
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_BLUE,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-/**
- * Set LED color
- *
- * @param color         Enumerated color value
- */
-static void set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_POWER_LED, !(color == LED_BLUE));
-	gpio_set_level(GPIO_LED_ACIN, !(color == LED_GREEN));
-	gpio_set_level(GPIO_LED_CHARGE, !(color == LED_RED));
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	gpio_set_level(GPIO_POWER_LED, !brightness[EC_LED_COLOR_BLUE]);
-	gpio_set_level(GPIO_LED_ACIN, !brightness[EC_LED_COLOR_GREEN]);
-	gpio_set_level(GPIO_LED_CHARGE, !brightness[EC_LED_COLOR_RED]);
-
-	return EC_SUCCESS;
-}
-
-
-static void nautilus_led_set_power_battery(void)
-{
-	static unsigned int power_ticks;
-	enum led_color cur_led_color = LED_RED;
-	enum charge_state chg_state = charge_get_state();
-	int charge_percent = charge_get_percent();
-
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		set_color(LED_BLUE);
-		return;
-	}
-
-	/* Flash red on critical battery, which usually inhibits AP power-on. */
-	if (battery_is_present() != BP_YES ||
-		charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-			set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
-						  LED_RED : LED_OFF);
-		return;
-	}
-
-	/* CHIPSET_STATE_OFF */
-	switch (chg_state) {
-	case PWR_STATE_DISCHARGE:
-		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
-			cur_led_color = LED_GREEN;
-		else
-			cur_led_color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE:
-		cur_led_color = LED_RED;
-		break;
-	case PWR_STATE_ERROR:
-		cur_led_color = ((power_ticks++ % LED_TOTAL_TICKS)
-					  < LED_ON_TICKS) ? LED_RED : LED_GREEN;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			cur_led_color = LED_GREEN;
-		else
-			cur_led_color = LED_OFF;
-		break;
-	default:
-		cur_led_color = LED_RED;
-		break;
-	}
-
-	set_color(cur_led_color);
-
-	if (chg_state != PWR_STATE_ERROR)
-		power_ticks = 0;
-}
-
-/**
- * Called by hook task every 250 ms
- */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED) &&
-		led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-			nautilus_led_set_power_battery();
-	}
-}
-
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/nautilus/usb_pd_policy.c b/board/nautilus/usb_pd_policy.c
deleted file mode 100644
index be4716b860..0000000000
--- a/board/nautilus/usb_pd_policy.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-					     GPIO_USB_C0_5V_EN;
-	enum gpio_signal gpio_3a_en = port ? GPIO_USB_C1_3A_EN :
-					     GPIO_USB_C0_3A_EN;
-
-	if (system_get_board_version() >= 1) {
-		/*
-		 * For rev1 and beyond, 1.5 vs 3.0 A limit is controlled by a
-		 * dedicated gpio where high = 3.0A and low = 1.5A. VBUS on/off
-		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
-		 * can remain outputs.
-		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-	} else {
-		/*
-		 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-		 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-		 * setting a minimum OCP current of 3186 mA.
-		 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put
-		 * a 33k resistor on ILIM, setting a minimum OCP current of
-		 * 1505 mA.
-		 */
-		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-		gpio_set_flags(gpio_5v_en, flags);
-	}
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	if (system_get_board_version() >= 2)
-		pd_set_vbus_discharge(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (system_get_board_version() >= 2 && prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
-				      GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-}
diff --git a/board/nautilus/vif_override.xml b/board/nautilus/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nautilus/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nightfury/battery.c b/board/nightfury/battery.c
deleted file mode 100644
index a3b251229b..0000000000
--- a/board/nightfury/battery.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-#include "system.h"
-#include "util.h"
-
-/*
- * Battery info for all Nightfury battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-/* charging current is limited to 0.45C */
-#define CHARGING_CURRENT_45C 2804
-
-const struct board_batt_params board_battery_info[] = {
-	/* Dyna Battery Information */
-	[BATTERY_DYNA] = {
-		.fuel_gauge = {
-			.manuf_name = "Dyna",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8700,
-			.voltage_normal		= 7600, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 150,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4404D57",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 55,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-enum battery_present variant_battery_present(void)
-{
-	/*
-	 * For board version 1, there is a known issue with battery present
-	 * signal. So, always return BP_YES indicating battery is
-	 * present. battery_status() later should fail to talk to the battery in
-	 * case the battery is not really present.
-	 */
-	return BP_YES;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	if(chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return 0;
-
-	if(curr->requested_current > CHARGING_CURRENT_45C)
-		curr->requested_current = CHARGING_CURRENT_45C;
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-                                                  uint32_t *value)
-{
-        return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-                                                  uint32_t value)
-{
-        return EC_RES_INVALID_PARAM;
-}
diff --git a/board/nightfury/board.c b/board/nightfury/board.c
deleted file mode 100644
index bed17b834c..0000000000
--- a/board/nightfury/board.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nightfury board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2ds.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_opt3001.h"
-#include "driver/als_tcs3400.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		.freq = 10000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC 1.2 chip Configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-        [USB_PD_PORT_TCPC_0] = {
-                .i2c_port = I2C_PORT_PPC0,
-                .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-        },
-
-        [USB_PD_PORT_TCPC_1] = {
-                .i2c_port = I2C_PORT_TCPC1,
-                .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-        },
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* Base light sensor private data */
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* LIS2DS private data */
-static struct stprivate_data g_lis2ds_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/*
- * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
- * matrix can't be tested properly. This needs to be revisited after EVT to make
- * sure the rotation matrix for the lid sensor is correct.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DS,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2ds_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2ds_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = LIS2DS_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = LIS2DS_ODR_MIN_VAL,
-		.max_frequency = LIS2DS_ODR_MAX_VAL,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[BASE_ALS] = {
-		.name = "Light",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_OPT3001,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &opt3001_drv,
-		.drv_data = &g_opt3001_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = OPT3001_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0xd0000, /* scale = 13; uscale = 0 */
-		.min_frequency = OPT3001_LIGHT_MIN_FREQ,
-		.max_frequency = OPT3001_LIGHT_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-				.ec_rate = 0,
-			},
-		},
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[BASE_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 80,
-	.debounce_down_us = 30 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0, /* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/**********************************************************************/
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Nightfury Temperature sensors */
-/*
- * TODO(b/138578073): These setting need to be reviewed and set appropriately
- * for Nightfury. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_a,
-	[TEMP_SENSOR_2] = thermal_a,
-	[TEMP_SENSOR_3] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A;
-
-static void board_init(void)
-{
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable gpio interrupt for lid accel sensor */
-	gpio_enable_interrupt(GPIO_LID_ACCEL_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-int board_tcpc_post_init(int port)
-{
-	int rv = EC_SUCCESS;
-
-	if (port == USB_PD_PORT_TCPC_0)
-		/* Set MUX_DP_EQ to 3.6dB (0x98) */
-		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-
-	return rv;
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255) || (sku == 1) || (sku == 2);
-}
diff --git a/board/nightfury/board.h b/board/nightfury/board.h
deleted file mode 100644
index 31207b2a52..0000000000
--- a/board/nightfury/board.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nightfury board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
-#define CONFIG_DPTF_MULTI_PROFILE
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* LIS2DS Lid accel */
-#define CONFIG_ACCEL_LIS2DS
-#define CONFIG_ACCEL_LIS2DS_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-/* BH1730 and TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
-#define CONFIG_ALS_OPT3001
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(BASE_ALS))
-
-/* Parameter to calculate LUX on Nightfury */
-#define CONFIG_ALS_BH1730_LUXTH_PARAMS
-/*
- * Calculation formula depends on characteristic of optical window.
- * In case of Nightfury, we can select two different formula
- * as characteristic of optical window.
- * BH1730_LUXTH1_1K is charateristic of optical window.
- * 1. d1_1K/d0_1K * 1000 <  BH1730_LUXTH1_1K
- * 2. d1_1K/d0_1K * 1000 >= BH1730_LUXTH1_1K
- * d0 and d1 are unsigned 16 bit. So, d1/d0 max is 65535
- * To meet 2nd condition, make BH1730_LUXTH2_1K to (max+1)*1000
- * Nightfury will not use both BH1730_LUXTH3_1K condition
- * and BH1730_LUXTH4_1K condition.
- */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY 0
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_3_L
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_2_L
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set via experimentation by finding how high it can be set and still boot
- * the AP successfully, then backing off to provide margin.
- *
- * TODO(b/133444665): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Thermal features */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	BASE_ALS,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNA,
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nightfury/build.mk b/board/nightfury/build.mk
deleted file mode 100644
index e91262fd43..0000000000
--- a/board/nightfury/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/nightfury/ec.tasklist b/board/nightfury/ec.tasklist
deleted file mode 100644
index 101713dc6e..0000000000
--- a/board/nightfury/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/nightfury/gpio.inc b/board/nightfury/gpio.inc
deleted file mode 100644
index 68d847fe92..0000000000
--- a/board/nightfury/gpio.inc
+++ /dev/null
@@ -1,162 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-GPIO_INT(LID_ACCEL_INT_L,      PIN(5, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lis2ds_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(USB_C0_BC12_CHG_DET_L,    PIN(6, 0), GPIO_INPUT)
-GPIO(USB_C1_BC12_CHG_DET_L,    PIN(9, 6), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON,      PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_BC12_VBUS_ON,      PIN(C, 6), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-
-/*
- * TODO: b/130822500
- * Configured as if it were NC for now
- */
-GPIO(M2_SD_PLN,                PIN(A, 0), GPIO_INPUT |          /* Provide SSD a shutdown warning */
-                                          GPIO_PULL_UP)
-
-/*
- * TODO: b/130824532
- * Configured as if it were NC for now (but has external 1K pulldown)
- */
-GPIO(IMVP8_PE,                 PIN(A, 7), GPIO_INPUT)          /* Pull high to flash MPS part */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* NC / TP */
-GPIO(TP58,                     PIN(0, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP73,                     PIN(8, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP18,                     PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP54,                     PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP57,                     PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP55,                     PIN(7, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP59,                     PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)                             /* ADC0-3 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/nightfury/led.c b/board/nightfury/led.c
deleted file mode 100644
index dce39acfd6..0000000000
--- a/board/nightfury/led.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Nightfury
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Nightfury : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-                                        {LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	if (color == EC_LED_COLOR_BLUE)
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	/* Battery leds must be turn off when blue led is on
-	 * because Nightfury has 3-in-1 led.
-	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/nightfury/vif_override.xml b/board/nightfury/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nightfury/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nipperkin/battery.c b/board/nipperkin/battery.c
deleted file mode 100644
index 5a3656c734..0000000000
--- a/board/nipperkin/battery.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-
-/*
- * Battery info for all Guybrush battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 996QA193H Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-/* Cosmx CA407792G Battery Information */
-	[BATTERY_COSMX] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-11-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 13200,		/* mV */
-			.voltage_normal = 11550,	/* mV */
-			.voltage_min = 9000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_HIGHPOWER;
diff --git a/board/nipperkin/board.c b/board/nipperkin/board.c
deleted file mode 100644
index 42df3c312b..0000000000
--- a/board/nipperkin/board.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nipperkin board-specific configuration */
-
-#include "adc.h"
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-#include "button.h"
-#include "chipset.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/temp_sensor/tmp112.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "temp_sensor/tmp112.h"
-#include "thermal.h"
-#include "usb_mux.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-__override enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-/*
- * PS8818 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- * TODO(b/179036200): Adjust PS8818 tuning for guybrush reference
- */
-__override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 1);
-	} else {
-		/* Disable HPD on the DB */
-		gpio_set_level(GPIO_USB_C1_HPD, 0);
-	}
-
-	return rv;
-}
-
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	if (get_board_version() > 1)
-		tmp112_init();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-int board_get_soc_temp_k(int idx, int *temp_k)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_k(idx, temp_k);
-}
-
-int board_get_soc_temp_mk(int *temp_mk)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_mk(TMP112_SOC, temp_mk);
-}
-
-int board_get_ambient_temp_mk(int *temp_mk)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return tmp112_get_val_mk(TMP112_AMB, temp_mk);
-}
-
-/* ADC Channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_MEMORY] = {
-		.name = "MEMORY",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_CORE_IMON1] = {
-		.name = "CORE_I",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SOC_IMON2] = {
-		.name = "SOC_I",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temp Sensors */
-static int board_get_temp(int, int *);
-
-const struct tmp112_sensor_t tmp112_sensors[] = {
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS0 },
-	{ I2C_PORT_SENSOR, TMP112_I2C_ADDR_FLAGS1 },
-};
-BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_soc_temp_k,
-		.idx = TMP112_SOC,
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.name = "Memory",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = ADC_TEMP_SENSOR_MEMORY,
-	},
-	[TEMP_SENSOR_5V_REGULATOR] = {
-		.name = "5V_REGULATOR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = ADC_TEMP_SENSOR_5V_REGULATOR,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-	[TEMP_SENSOR_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = tmp112_get_val_k,
-		.idx = TMP112_AMB,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
-	[TEMP_SENSOR_SOC] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/* TODO: Setting fan off to 0 so it's allways on */
-		.temp_fan_off = C_TO_K(0),
-		.temp_fan_max = C_TO_K(70),
-	},
-	[TEMP_SENSOR_CHARGER] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_MEMORY] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		.temp_fan_off = 0,
-		.temp_fan_max = 0,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.temp_host = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100),
-			[EC_TEMP_THRESH_HALT] = C_TO_K(105),
-		},
-		.temp_host_release = {
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		},
-		/*
-		 * CPU temp sensor fan thresholds are high because they are a
-		 * backup for the SOC temp sensor fan thresholds.
-		 */
-		.temp_fan_off = C_TO_K(60),
-		.temp_fan_max = C_TO_K(90),
-	},
-	/*
-	 * Note: Leave ambient entries at 0, both as it does not represent a
-	 * hotspot and as not all boards have this sensor
-	 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static int board_get_temp(int idx, int *temp_k)
-{
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
-}
-
-/* Called on AP resume to S0 */
-static void board_chipset_resume(void)
-{
-	ioex_set_level(IOEX_HDMI_DATA_EN, 1);
-	ioex_set_level(IOEX_EN_PWR_HDMI, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP suspend */
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_EN_PWR_HDMI, 0);
-	ioex_set_level(IOEX_HDMI_DATA_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/nipperkin/board.h b/board/nipperkin/board.h
deleted file mode 100644
index df57cade06..0000000000
--- a/board/nipperkin/board.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Motion sensing drivers */
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-
-/* EC console commands */
-#define CONFIG_CMD_BUTTON
-
-/* USB Type C and USB PD defines */
-
-/* USB Type A Features */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* LED features */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Battery Types */
-enum battery_type {
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COSMX,
-	BATTERY_TYPE_COUNT,
-};
-
-/* ADC Channels */
-enum adc_channel {
-	ADC_TEMP_SENSOR_MEMORY = 0,
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_5V_REGULATOR,
-	ADC_CORE_IMON1,
-	ADC_SOC_IMON2,
-	ADC_CH_COUNT
-};
-
-/* Temp Sensors */
-enum temp_sensor_id {
-	TEMP_SENSOR_SOC = 0,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_MEMORY,
-	TEMP_SENSOR_5V_REGULATOR,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nipperkin/board_fw_config.c b/board/nipperkin/board_fw_config.c
deleted file mode 100644
index c9fa01bc7a..0000000000
--- a/board/nipperkin/board_fw_config.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "base_fw_config.h"
-#include "board_fw_config.h"
-
-bool board_has_kblight(void)
-{
-	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
-}
-
-enum board_usb_c1_mux board_get_usb_c1_mux(void)
-{
-	return USB_C1_MUX_PS8818;
-};
-
-enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
-{
-	return USB_A1_RETIMER_PS8811;
-};
-
-bool board_has_privacy_panel(void)
-{
-	return (get_fw_config_field(FW_CONFIG_KEYBOARD_OFFSET,
-			FW_CONFIG_KEYBOARD_WIDTH) ==
-			FW_CONFIG_KEYBOARD_PRIVACY_YES);
-}
diff --git a/board/nipperkin/board_fw_config.h b/board/nipperkin/board_fw_config.h
deleted file mode 100644
index 77306ccb6f..0000000000
--- a/board/nipperkin/board_fw_config.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _NIPPERKIN_BOARD_FW_CONFIG__H_
-#define _NIPPERKIN_BOARD_FW_CONFIG__H_
-
-/****************************************************************************
- * Nipperkin CBI FW Configuration
- */
-
-/*
- * Keyboard Backlight (1 bit)
- */
-#define FW_CONFIG_KBLIGHT_OFFSET		0
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
-
-/*
- * Bit 1 ~ 6 not related to EC function
- */
-
-/*
- * Keyboard (1 bit)
- */
-#define FW_CONFIG_KEYBOARD_OFFSET		7
-#define FW_CONFIG_KEYBOARD_WIDTH		1
-#define FW_CONFIG_KEYBOARD_PRIVACY_YES		0
-#define FW_CONFIG_KEYBOARD_PRIVACY_NO		1
-
-bool board_has_privacy_panel(void);
-
-#endif /* _NIPPERKIN_BOARD_FW_CONFIG__H_ */
diff --git a/board/nipperkin/build.mk b/board/nipperkin/build.mk
deleted file mode 100644
index e4fdcf4afd..0000000000
--- a/board/nipperkin/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-BASEBOARD:=guybrush
-
-board-y=board.o
-board-y+=board_fw_config.o led.o battery.o
diff --git a/board/nipperkin/ec.tasklist b/board/nipperkin/ec.tasklist
deleted file mode 100644
index ccdff9847c..0000000000
--- a/board/nipperkin/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/nipperkin/gpio.inc b/board/nipperkin/gpio.inc
deleted file mode 100644
index ec35ce6c2c..0000000000
--- a/board/nipperkin/gpio.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the board GPIOs that we care about. */
-
-#include "base_gpio.inc"
-
-/* LED Signals */
-GPIO(C0_CHARGE_LED_AMBER_L,		PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(C0_CHARGE_LED_WHITE_L,		PIN(8, 0), GPIO_OUT_HIGH)
-GPIO(C1_CHARGE_LED_AMBER_L,		PIN(6, 7), GPIO_OUT_HIGH)
-GPIO(C1_CHARGE_LED_WHITE_L,		PIN(7, 0), GPIO_OUT_HIGH)
-
-/* HDMI */
-IOEX(EN_PWR_HDMI,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_OUT_LOW)
-IOEX(HDMI_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)
-
-/* Test Points */
-GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/nipperkin/led.c b/board/nipperkin/led.c
deleted file mode 100644
index 68a9d11b62..0000000000
--- a/board/nipperkin/led.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "hooks.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICKS_PER_CYCLE 10
-#define LED_TICKS_PER_CYCLE_S3 10
-#define LED_ON_TICKS 5
-#define POWER_LED_ON_S3_TICKS 5
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LED_RIGHT_PORT = 0,
-	LED_LEFT_PORT
-};
-
-static void led_set_color_battery(enum led_port port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == LED_RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
-	white_led = (port == LED_RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LED_LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LED_LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LED_LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LED_RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LED_RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LED_RIGHT_PORT, LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(LED_RIGHT_PORT,
-				(port == LED_RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LED_LEFT_PORT,
-				(port == LED_LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LEDs for Nipperkin, Nipperkin is non-power LED
-	 * design, blinking both two side battery white LEDs to indicate
-	 * system suspend with non-charging state.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
-		power_ticks++;
-
-		led_set_color_battery(LED_RIGHT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		led_set_color_battery(LED_LEFT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		return;
-	}
-
-	power_ticks = 0;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(LED_RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(LED_RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LED_LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/nipperkin/vif_override.xml b/board/nipperkin/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nipperkin/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nocturne/base_detect.c b/board/nocturne/base_detect.c
deleted file mode 100644
index 48c7b1f9dd..0000000000
--- a/board/nocturne/base_detect.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Nocturne base detection code.
- *
- * Nocturne has two analog detection pins with which it monitors to determine
- * the base status: the attach, and detach pins.
- *
- * When the voltages cross a certain threshold, after some debouncing, the base
- * is deemed connected.  Nocturne then applies the base power and monitors for
- * power faults from the eFuse as well as base disconnection.  Similarly, once
- * the voltages cross a different threshold, after some debouncing, the base is
- * deemed disconnected.  At this point, Nocturne disables the base power.
- */
-
-#include "adc.h"
-#include "base_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#define DEFAULT_POLL_TIMEOUT_US (250 * MSEC)
-#define DEBOUNCE_TIMEOUT_US (20 * MSEC)
-#define RAPID_DEBOUNCE_TIMEOUT_US (4 * MSEC)
-#define POWER_FAULT_RETRY_INTERVAL_US (15 * MSEC)
-
-/*
- * Number of times to attempt re-applying power within 1s when a fault occurs.
- */
-#define POWER_FAULT_MAX_RETRIES 3
-
-/* Thresholds for attach pin reading when power is not applied. */
-#define ATTACH_MIN_MV 300
-#define ATTACH_MAX_MV 900
-
-/* Threshold for attach pin reading when power IS applied. */
-#define PWREN_ATTACH_MIN_MV 2300
-
-/* Threshold for detach pin reading. */
-#define DETACH_MIN_MV 10
-
-/*
- * For the base to be considered detached, the average detach pin readings must
- * be below this value.  The reason that this is higher than DETACH_MIN_MV is
- * that due to leakage current, sometimes the readings bounce under and over
- * DETACH_MIN_MV.
- */
-#define DETACH_MIN_AVG_MV 20
-
-/*
- * The number of recent samples used to determine average detach pin readings.
- */
-#define WINDOW_SIZE 5
-
-
-enum base_detect_state {
-	BASE_DETACHED = 0,
-	BASE_ATTACHED_DEBOUNCE,
-	BASE_ATTACHED,
-	BASE_DETACHED_DEBOUNCE,
-	// Default for |forced_state|. Should be set only on |forced_state|.
-	BASE_NO_FORCED_STATE,
-};
-
-static int debug;
-static enum base_detect_state forced_state = BASE_NO_FORCED_STATE;
-static enum base_detect_state state;
-static int detach_avg[WINDOW_SIZE]; /* Rolling buffer of detach pin readings. */
-static uint8_t last_idx; /* last insertion index into the buffer. */
-static timestamp_t detached_decision_deadline;
-
-static void enable_base_interrupts(int enable)
-{
-	int (*fn)(enum gpio_signal) = enable ? gpio_enable_interrupt :
-		gpio_disable_interrupt;
-
-	/* This pin is present on boards newer than rev 0. */
-	if (board_get_version() > 0)
-		fn(GPIO_BASE_USB_FAULT_ODL);
-
-	fn(GPIO_BASE_PWR_FAULT_ODL);
-}
-
-static void base_power_enable(int enable)
-{
-	/* Nothing to do if the state is the same. */
-	if (gpio_get_level(GPIO_BASE_PWR_EN) == enable)
-		return;
-
-	if (enable) {
-		/* Apply power to the base only if the AP is on or sleeping. */
-		if (chipset_in_state(CHIPSET_STATE_ON |
-				     CHIPSET_STATE_ANY_SUSPEND)) {
-			gpio_set_level(GPIO_BASE_PWR_EN, 1);
-			/* Allow time for the fault line to rise. */
-			msleep(1);
-			/* Monitor for base power faults. */
-			enable_base_interrupts(1);
-		}
-	} else {
-		/*
-		 * Disable power fault interrupt.  It will read low when base
-		 * power is removed.
-		 */
-		enable_base_interrupts(0);
-		/* Now, remove power to the base. */
-		gpio_set_level(GPIO_BASE_PWR_EN, 0);
-	}
-
-	CPRINTS("BP: %d", enable);
-}
-
-static void base_detect_changed(void)
-{
-	switch (state) {
-	case BASE_DETACHED:
-		base_set_state(0);
-		base_power_enable(0);
-		break;
-
-	case BASE_ATTACHED:
-		base_set_state(1);
-		base_power_enable(1);
-		break;
-
-	default:
-		return;
-	};
-}
-
-static int base_seems_attached(int attach_pin_mv, int detach_pin_mv)
-{
-	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
-		return 0;
-
-	if (gpio_get_level(GPIO_BASE_PWR_EN))
-		return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-			(detach_pin_mv >= DETACH_MIN_MV);
-	else
-		return (attach_pin_mv <= ATTACH_MAX_MV) &&
-			(attach_pin_mv >= ATTACH_MIN_MV) &&
-			(detach_pin_mv <= DETACH_MIN_MV);
-}
-
-static int base_seems_detached(int attach_pin_mv, int detach_pin_mv)
-{
-	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
-		return 0;
-
-	return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-		(detach_pin_mv <= DETACH_MIN_MV);
-}
-
-static void set_state(enum base_detect_state new_state)
-{
-	if (new_state != state) {
-		CPRINTS("BD: st%d", new_state);
-		state = new_state;
-	}
-}
-
-static int average_detach_mv(void)
-{
-	int i;
-	int sum = 0;
-
-	for (i = 0; i < WINDOW_SIZE; i++)
-		sum += detach_avg[i];
-
-	return sum / WINDOW_SIZE;
-}
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-static void base_detect_deferred(void)
-{
-	int attach_reading;
-	int detach_reading;
-	int timeout = DEFAULT_POLL_TIMEOUT_US;
-
-	if (forced_state != BASE_NO_FORCED_STATE) {
-		if (state != forced_state) {
-			CPRINTS("BD forced  %s",
-				forced_state == BASE_ATTACHED ?
-				"attached" : "detached");
-			set_state(forced_state);
-			base_detect_changed();
-		}
-		return;
-	}
-
-	attach_reading = adc_read_channel(ADC_BASE_ATTACH);
-	detach_reading = adc_read_channel(ADC_BASE_DETACH);
-
-	/* Update the detach_avg */
-	detach_avg[last_idx] = detach_reading;
-
-	if (debug) {
-		int i;
-
-		CPRINTS("BD st%d: att: %dmV det: %dmV", state,
-			attach_reading,
-			detach_reading);
-		CPRINTF("det readings = [");
-		for (i = 0; i < WINDOW_SIZE; i++)
-			CPRINTF("%d%s ", detach_avg[i],
-				i == last_idx ? "*" : " ");
-		CPRINTF("]\n");
-	}
-	last_idx = (last_idx + 1) % WINDOW_SIZE;
-
-	switch (state) {
-	case BASE_DETACHED:
-		/* Check to see if a base may be attached. */
-		if (base_seems_attached(attach_reading, detach_reading)) {
-			timeout = DEBOUNCE_TIMEOUT_US;
-			set_state(BASE_ATTACHED_DEBOUNCE);
-		}
-		break;
-
-	case BASE_ATTACHED_DEBOUNCE:
-		/* Check to see if it's still attached. */
-		if (base_seems_attached(attach_reading, detach_reading)) {
-			CPRINTS("BD: att: %dmV det: %dmV", attach_reading,
-				detach_reading);
-			set_state(BASE_ATTACHED);
-			base_detect_changed();
-		} else if (base_seems_detached(attach_reading,
-					       detach_reading)) {
-			set_state(BASE_DETACHED);
-		}
-		break;
-
-	case BASE_ATTACHED:
-		/* Check to see if a base may be detached. */
-		if (base_seems_detached(attach_reading, detach_reading)) {
-			/*
-			 * The base seems detached based off of one reading.
-			 * Let's pay closer attention to the pins and then
-			 * decide if it really is detached or not.  It could
-			 * have been just a spurious low reading.
-			 */
-			timeout = RAPID_DEBOUNCE_TIMEOUT_US;
-
-			/*
-			 * Set a deadline to make a call about actually being
-			 * detached.  In the meantime, we'll collect samples
-			 * and calculate an average.
-			 */
-			detached_decision_deadline = get_time();
-			detached_decision_deadline.val += DEBOUNCE_TIMEOUT_US;
-			set_state(BASE_DETACHED_DEBOUNCE);
-		}
-		break;
-
-	case BASE_DETACHED_DEBOUNCE:
-		/* Check to see if a base is still detached.
-		 *
-		 * We look at rolling average of the detach readings to make
-		 * sure one or two consecutive low samples don't result in a
-		 * false detach.
-		 */
-		CPRINTS("BD: det avg: %d", average_detach_mv());
-		if (timestamp_expired(detached_decision_deadline, NULL)) {
-			/* Alright, time's up, time to decide. */
-			if (average_detach_mv() < DETACH_MIN_AVG_MV) {
-				set_state(BASE_DETACHED);
-				base_detect_changed();
-			} else {
-				set_state(BASE_ATTACHED);
-			}
-		}
-
-		/*
-		 * Shorten the timeout to collect more samples before the
-		 * deadline.
-		 */
-		timeout = RAPID_DEBOUNCE_TIMEOUT_US;
-		break;
-		/* TODO(b/74239259): do you want to add an interrupt? */
-
-	default:
-		break;
-	};
-
-	/* Check again in the appropriate time only if the AP is on. */
-	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND))
-		hook_call_deferred(&base_detect_deferred_data, timeout);
-};
-DECLARE_HOOK(HOOK_INIT, base_detect_deferred, HOOK_PRIO_INIT_ADC + 1);
-
-static void restart_state_machine(void)
-{
-	/*
-	 * Since we do not poll in anything lower than S3, the base may or may
-	 * not be connected, therefore intentionally set the state to detached
-	 * such that we can detect and power on the base if necessary.
-	 */
-	set_state(BASE_DETACHED);
-	hook_call_deferred(&base_detect_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, restart_state_machine, HOOK_PRIO_DEFAULT);
-
-static void power_off_base(void)
-{
-	base_power_enable(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, power_off_base, HOOK_PRIO_DEFAULT);
-
-static uint8_t base_power_on_attempts;
-static void clear_base_power_on_attempts_deferred(void)
-{
-	base_power_on_attempts = 0;
-}
-DECLARE_DEFERRED(clear_base_power_on_attempts_deferred);
-
-static void check_and_reapply_base_power_deferred(void)
-{
-	if (state != BASE_ATTACHED)
-		return;
-
-	if (base_power_on_attempts < POWER_FAULT_MAX_RETRIES) {
-		CPRINTS("Reapply base pwr");
-		base_power_enable(1);
-		base_power_on_attempts++;
-
-		hook_call_deferred(&clear_base_power_on_attempts_deferred_data,
-				   SECOND);
-	}
-
-}
-DECLARE_DEFERRED(check_and_reapply_base_power_deferred);
-
-void base_pwr_fault_interrupt(enum gpio_signal s)
-{
-	/* Inverted because active low. */
-	int pwr_fault_detected = !gpio_get_level(GPIO_BASE_PWR_FAULT_ODL);
-	int usb_fault_detected = s == GPIO_BASE_USB_FAULT_ODL;
-
-	if (pwr_fault_detected | usb_fault_detected) {
-		/* Turn off base power. */
-		CPRINTS("Base Pwr Flt! %s%s", pwr_fault_detected ? "p" : "-",
-			usb_fault_detected ? "u" : "-");
-		base_power_enable(0);
-
-		/*
-		 * Try and apply power in a bit if maybe it was just a temporary
-		 * condition.
-		 */
-		hook_call_deferred(&check_and_reapply_base_power_deferred_data,
-				   POWER_FAULT_RETRY_INTERVAL_US);
-	}
-}
-
-static int command_basedetectdebug(int argc, char **argv)
-{
-	if ((argc > 1) && !parse_bool(argv[1], &debug))
-		return EC_ERROR_PARAM1;
-
-	CPRINTS("BD: %sst%d", forced_state != BASE_NO_FORCED_STATE ?
-						  "forced " : "", state);
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(basedebug, command_basedetectdebug, "[ena|dis]",
-			"En/Disable base detection debug");
-
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH)
-		forced_state = BASE_ATTACHED;
-	else if (state == EC_SET_BASE_STATE_DETACH)
-		forced_state = BASE_DETACHED;
-	else
-		forced_state = BASE_NO_FORCED_STATE;
-
-	hook_call_deferred(&base_detect_deferred_data, 0);
-}
diff --git a/board/nocturne/battery.c b/board/nocturne/battery.c
deleted file mode 100644
index ff3f16fa33..0000000000
--- a/board/nocturne/battery.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "charge_state_v2.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "temp_sensor.h"
-#include "usb_pd.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
-
-/*
- * We need to stop charging the battery when the DRAM temperature sensor gets
- * over 47 C (320 K), and resume charging once it cools back down.
- */
-#define DRAM_STOPCHARGE_TEMP_K	320
-
-/* Battery info */
-static const struct battery_info info = {
-	.voltage_max		= 8880,
-	.voltage_normal		= 7700,
-	.voltage_min		= 6000,
-	.precharge_current	= 160,
-	.start_charging_min_c	= 10,
-	.start_charging_max_c	= 50,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= -20,
-	.discharging_max_c	= 60,
-};
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
-	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	uint8_t data[6];
-	int rv;
-
-	/*
-	 * Take note if we find that the battery isn't in disconnect state,
-	 * and always return NOT_DISCONNECTED without probing the battery.
-	 * This assumes the battery will not go to disconnect state during
-	 * runtime.
-	 */
-	static int not_disconnected;
-
-	if (not_disconnected)
-		return BATTERY_NOT_DISCONNECTED;
-
-	/* Check if battery discharge FET is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-	if (~data[3] & (BATTERY_DISCHARGING_DISABLED)) {
-		not_disconnected = 1;
-		return BATTERY_NOT_DISCONNECTED;
-	}
-
-	/*
-	 * Battery discharge FET is disabled.  Verify that we didn't enter this
-	 * state due to a safety fault.
-	 */
-	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv || data[2] || data[3] || data[4] || data[5])
-		return BATTERY_DISCONNECT_ERROR;
-
-	/* No safety fault, battery is disconnected */
-	return BATTERY_DISCONNECTED;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-static int should_stopcharge(void)
-{
-	int t_dram;
-
-	/* We can only stop charging on AC, if AC is plugged in. */
-	if (!gpio_get_level(GPIO_AC_PRESENT))
-		return 0;
-
-	/*
-	 * The DRAM temperature sensor is only available when the AP is on,
-	 * therefore only inhibit charging when we can actually read a
-	 * temperature.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ON) &&
-	    !temp_sensor_read(TEMP_SENSOR_DRAM, &t_dram) &&
-	    (t_dram >= DRAM_STOPCHARGE_TEMP_K))
-		return 1;
-	else
-		return 0;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	static uint8_t stopcharge_on_ac;
-	int enable_stopcharge;
-
-	enable_stopcharge = should_stopcharge();
-	if (enable_stopcharge != stopcharge_on_ac) {
-		stopcharge_on_ac = enable_stopcharge;
-		if (enable_stopcharge) {
-			chgstate_set_manual_current(0);
-		} else {
-			chgstate_set_manual_current(-1);
-		}
-	}
-
-	return 0;
-}
diff --git a/board/nocturne/board.c b/board/nocturne/board.c
deleted file mode 100644
index 5987bae025..0000000000
--- a/board/nocturne/board.c
+++ /dev/null
@@ -1,810 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nocturne board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "compile_time_macros.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_opt3001.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/temp_sensor/bd99992gw.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "mkbp_event.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "system_chip.h"
-#include "switch.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = -1;
-
-	switch (s) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-/*
- * Nocturne shares the TCPC Alert# line with the TI SN5S330's interrupt line.
- * Therefore, we need to also check on that part.
- */
-static void usb_c_interrupt(enum gpio_signal s)
-{
-	int port = (s == GPIO_USB_C0_PD_INT_ODL) ? 0 : 1;
-
-	tcpc_alert_event(s);
-	sn5s330_interrupt(port);
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-const struct adc_t adc_channels[] = {
-	[ADC_BASE_ATTACH] = {
-		"BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-
-	[ADC_BASE_DETACH] = {
-		"BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_DB0_LED_RED] =   { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB0_LED_GREEN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB0_LED_BLUE] =  { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB1_LED_RED] =   { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB1_LED_BLUE] =  { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		"battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C4_BATTERY_SCL,
-		GPIO_EC_I2C4_BATTERY_SDA
-	},
-
-	{
-		"power", I2C_PORT_POWER, 100, GPIO_EC_I2C0_POWER_SCL,
-		GPIO_EC_I2C0_POWER_SDA
-	},
-
-	{
-		"als_gyro", I2C_PORT_ALS_GYRO, 400, GPIO_EC_I2C5_ALS_GYRO_SCL,
-		GPIO_EC_I2C5_ALS_GYRO_SDA
-	},
-
-	{
-		"usbc0", I2C_PORT_USB_C0, 100, GPIO_USB_C0_SCL, GPIO_USB_C0_SDA
-	},
-
-	{
-		"usbc1", I2C_PORT_USB_C1, 100, GPIO_USB_C1_SCL, GPIO_USB_C1_SDA
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
-/*
- * Motion Sense
- */
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-
-/* Sensor driver data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* Matrix to rotate accel/gyro into standard reference frame. */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "BMI160 ACC",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bmi160_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ALS_GYRO,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC setup accel for chrome usage */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[LID_GYRO] = {
-		.name = "BMI160 GYRO",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bmi160_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ALS_GYRO,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 1000, /* dps */
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[LID_ALS] = {
-		.name = "Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_OPT3001,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &opt3001_drv,
-		.drv_data = &g_opt3001_data,
-		.port = I2C_PORT_ALS_GYRO,
-		.i2c_spi_addr_flags = OPT3001_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		/* scale = 43.4513 http://b/111528815#comment14 */
-		.default_range = 0x2b11a1,
-		.min_frequency = OPT3001_LIGHT_MIN_FREQ,
-		.max_frequency = OPT3001_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[VSYNC] = {
-		.name = "Camera VSYNC",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_GPIO,
-		.type = MOTIONSENSE_TYPE_SYNC,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &sync_drv,
-		.default_range = 0,
-		.min_frequency = 0,
-		.max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void disable_sensor_irqs(void)
-{
-	/*
-	 * In S5, sensors are unpowered, therefore disable their interrupts on
-	 * shutdown.
-	 */
-	gpio_disable_interrupt(GPIO_ACCELGYRO3_INT_L);
-	gpio_disable_interrupt(GPIO_RCAM_VSYNC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_sensor_irqs, HOOK_PRIO_DEFAULT);
-
-static void enable_sensor_irqs(void)
-{
-	/*
-	 * Re-enable the sensor interrupts when entering S0.
-	 */
-	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
-	gpio_enable_interrupt(GPIO_RCAM_VSYNC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_sensor_irqs, HOOK_PRIO_DEFAULT);
-
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void imvp8_tune_deferred(void)
-{
-	/* For the IMVP8, reduce the steps during decay from 3 to 1. */
-	if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS,
-			0xFA, 0x0AC5))
-		CPRINTS("Failed to change step decay!");
-}
-DECLARE_DEFERRED(imvp8_tune_deferred);
-
-void board_chipset_resume(void)
-{
-	/* Write to the IMVP8 after 250ms. */
-	hook_call_deferred(&imvp8_tune_deferred_data, 250 * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_version(void)
-{
-	static int board_version = -1;
-
-	if (board_version == -1) {
-		board_version = 0;
-		/* BRD_ID0 is LSb. */
-		if (gpio_get_level(GPIO_EC_BRD_ID0))
-			board_version |= 0x1;
-		if (gpio_get_level(GPIO_EC_BRD_ID1))
-			board_version |= 0x2;
-		if (gpio_get_level(GPIO_EC_BRD_ID2))
-			board_version |= 0x4;
-		if (gpio_get_level(GPIO_EC_BRD_ID3))
-			board_version |= 0x8;
-	}
-
-	return board_version;
-}
-
-void board_hibernate(void)
-{
-	int p;
-
-	/* Configure PSL pins */
-	for (p = 0; p < hibernate_wake_pins_used; p++)
-		system_config_psl_mode(hibernate_wake_pins[p]);
-
-	/*
-	 * Enter PSL mode.  Note that on Nocturne, simply enabling PSL mode does
-	 * not cut the EC's power.  Therefore, we'll need to cut off power via
-	 * the ROP PMIC afterwards.
-	 */
-	system_enter_psl_mode();
-
-	/* Cut off DSW power via the ROP PMIC. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x1);
-
-	/* Wait for power to be cut. */
-	while (1)
-		;
-}
-
-static void board_init(void)
-{
-	/* Enable USB Type-C interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/* Enable sensor IRQs if we're in S0. */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		enable_sensor_irqs();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-int board_is_i2c_port_powered(int port)
-{
-	if (port != I2C_PORT_ALS_GYRO)
-		return 1;
-
-	/* The sensors are not powered in anything lower than S5. */
-	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
-}
-
-static void board_lid_change(void)
-{
-	/* This is done in hardware on old revisions. */
-	if (board_get_version() <= 1)
-		return;
-
-	if (lid_is_open())
-		gpio_set_level(GPIO_UHALL_PWR_EN, 1);
-	else
-		gpio_set_level(GPIO_UHALL_PWR_EN, 0);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, board_lid_change, HOOK_PRIO_DEFAULT);
-
-static void board_pmic_disable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (0)   - Disable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x3a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x2a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage 0.85V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x2a);
-}
-
-static void board_pmic_enable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (1)   - Enable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x7a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x6a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage 0.85V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x6a);
-}
-
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
-		board_pmic_enable_slp_s0_vr_decay();
-	else if (state == HOST_SLEEP_EVENT_S0IX_RESUME)
-		board_pmic_disable_slp_s0_vr_decay();
-}
-
-static void board_pmic_init(void)
-{
-	int pgmask1;
-
-	/* Mask V5A_DS3_PG from PMIC PGMASK1. */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		      0x18, &pgmask1))
-		return;
-	pgmask1 |= BIT(2);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, pgmask1);
-
-	board_pmic_disable_slp_s0_vr_decay();
-
-	/* Enable active discharge (100 ohms) on V33A_PCH and V1.8A. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3D, 0x5);
-
-	/* Enable active discharge (500 ohms) on 1.8U and (100 ohms) 1.2U. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3E, 0xD0);
-}
-DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
-
-static void board_quirks(void)
-{
-	/*
-	 * Newer board revisions have external pull ups stuffed, so remove the
-	 * internal pulls.
-	 */
-	if (board_get_version() > 0) {
-		gpio_set_flags(GPIO_USB_C0_PD_INT_ODL, GPIO_INT_FALLING);
-		gpio_set_flags(GPIO_USB_C1_PD_INT_ODL, GPIO_INT_FALLING);
-	}
-
-	/*
-	 * Older boards don't have the SBU bypass circuitry needed for CCD, so
-	 * enable the CCD_MODE_ODL interrupt such that we can help in making
-	 * sure the SBU FETs are connected.
-	 */
-	if (board_get_version() < 2)
-		gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_quirks, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	int lvl;
-
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the levels are inverted because the pin is active low. */
-	lvl = is_overcurrented ? 0 : 1;
-
-	switch (port) {
-	case 0:
-		gpio_set_level(GPIO_USB_C0_OC_ODL, lvl);
-		break;
-
-	case 1:
-		gpio_set_level(GPIO_USB_C1_OC_ODL, lvl);
-		break;
-
-	default:
-		return;
-	};
-}
-
-static int read_gyro_sensor_temp(int idx, int *temp_ptr)
-{
-	/*
-	 * The gyro is only powered in S0, so don't go and read it if the AP is
-	 * off.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	return bmi160_get_sensor_temp(idx, temp_ptr);
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-	/* The Gyro temperature sensor is only readable in S0. */
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO}
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor. All temps are in degrees K. Must be in
- * same order as enum temp_sensor_id. To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Battery */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Ambient */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Charger */
-	{{0, C_TO_K(52), 0}, {0, 0, 0}, 0, 0}, /* DRAM */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* eMMC */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}  /* Gyro */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-	/* GPIO_USB_PD_RST_L resets all the TCPCs. */
-	gpio_set_level(GPIO_USB_PD_RST_L, 0);
-	msleep(10); /* TODO(aaboagye): Verify min hold time. */
-	gpio_set_level(GPIO_USB_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int rv;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	if (port == CHARGE_PORT_NONE) {
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			rv = ppc_vbus_sink_enable(i, 0);
-			/*
-			 * Deliberately ignoring this error since it may cause
-			 * an assertion error.
-			 */
-			if (rv)
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTF("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * Nocturne seems to overdraw its set input current limit by about 5%.
-	 * Request at most 95% of what's desired.
-	 */
-	icl = icl * 95 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and PPC.  Therefore, go
-	 * out and actually read the alert registers to report the alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI spec says to ignore bits 14:12. */
-			regval &= ~(BIT(14) | BIT(13) | BIT(12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec says to ignore bits 14:12. */
-			regval &= ~(BIT(14) | BIT(13) | BIT(12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
deleted file mode 100644
index 95f8d14403..0000000000
--- a/board/nocturne/board.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nocturne board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define CONFIG_HIBERNATE_PSL
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC modules */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_I2C
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_PWM
-#define CONFIG_THROTTLE_AP
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#define CONFIG_DETACHABLE_BASE
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-#define CONFIG_CMD_CHARGEN
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_PPC_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
-
-/* Buttons / Switches */
-#define CONFIG_BASE_ATTACHED_SWITCH
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_VOLUME_BUTTONS
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 128
-#define CONFIG_CHARGER_ISL9238
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_EXTPOWER_GPIO
-
-/* LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
-#define CONFIG_LED_PWM_COUNT 2
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-
-/* MKBP */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1<<EC_MKBP_EVENT_SWITCH)
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-
-/* Sensors */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_OPT3001
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-
-/* SoC */
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_DPTF
-#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-#define CONFIG_USB_PID 0x5045
-
-/* USB PD */
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_3A_PORTS 0
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_PE_SM
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_TYPEC_SM
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
-#define PD_OPERATING_POWER_MW 15000
-
-/* TODO(aaboagye): Verify these timings. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
-
-/* I2C config */
-#define I2C_PORT_CHARGER  I2C_PORT_POWER
-#define I2C_PORT_PMIC     I2C_PORT_POWER
-#define I2C_PORT_POWER    NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY  NPCX_I2C_PORT4_1
-#define I2C_PORT_ALS_GYRO NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL    I2C_PORT_ALS_GYRO
-#define I2C_PORT_USB_C0   NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1   NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL  I2C_PORT_PMIC
-
-#define GPIO_USB_C0_SCL GPIO_EC_I2C1_USB_C0_SCL
-#define GPIO_USB_C0_SDA GPIO_EC_I2C1_USB_C0_SDA
-#define GPIO_USB_C1_SCL GPIO_EC_I2C2_USB_C1_SCL
-#define GPIO_USB_C1_SDA GPIO_EC_I2C2_USB_C1_SDA
-
-#define I2C_ADDR_MP2949_FLAGS  0x20
-#define I2C_ADDR_BD99992_FLAGS 0x30
-
-/*
- * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
- * in the EC code base.
- */
-#define GPIO_AC_PRESENT       GPIO_ACOK_OD
-#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_ODL
-#define GPIO_BAT_PRESENT_L    GPIO_EC_BATT_PRES_L
-#define GPIO_ENTERING_RW      GPIO_EC_ENTERING_RW
-#define GPIO_PCH_PWRBTN_L     GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L     GPIO_RSMRST_L
-#define GPIO_PCH_RTCRST       GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L     GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L     GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L     GPIO_SLP_S4_L
-#define GPIO_PCH_SLP_SUS_L    GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L       GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK      GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L   GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L   GPIO_EC_PWR_BTN_IN_ODL
-#define GPIO_CPU_PROCHOT      GPIO_EC_PROCHOT_ODL
-#define GPIO_RSMRST_L_PGOOD   GPIO_ROP_EC_RSMRST_L
-#define GPIO_VOLUME_UP_L      GPIO_H1_EC_VOL_UP_ODL
-#define GPIO_VOLUME_DOWN_L    GPIO_H1_EC_VOL_DOWN_ODL
-#define GPIO_WP_L             GPIO_EC_WP_L
-
-#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_BASE_ATTACH,
-	ADC_BASE_DETACH,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_GYRO,	/* BMI160 */
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_DB0_LED_RED = 0,
-	PWM_CH_DB0_LED_GREEN,
-	PWM_CH_DB0_LED_BLUE,
-	PWM_CH_DB1_LED_RED,
-	PWM_CH_DB1_LED_GREEN,
-	PWM_CH_DB1_LED_BLUE,
-	PWM_CH_COUNT
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel and gyro sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL,
-	LID_GYRO,
-	LID_ALS,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS)
-
-void base_pwr_fault_interrupt(enum gpio_signal s);
-int board_get_version(void);
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nocturne/build.mk b/board/nocturne/build.mk
deleted file mode 100644
index 1c2e1e04f2..0000000000
--- a/board/nocturne/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-
-board-y=base_detect.o battery.o board.o led.o usb_pd_policy.o
diff --git a/board/nocturne/ec.tasklist b/board/nocturne/ec.tasklist
deleted file mode 100644
index 4fb7a035a9..0000000000
--- a/board/nocturne/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc
deleted file mode 100644
index 75d2275424..0000000000
--- a/board/nocturne/gpio.inc
+++ /dev/null
@@ -1,121 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,  PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c_interrupt)
-GPIO_INT(USB_C1_PD_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c_interrupt)
-
-/* Power Sequencing interrupts */
-GPIO_INT(ROP_DSW_PWROK_EC,   PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ROP_EC_RSMRST_L,    PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_IN_ODL,  PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(SLP_S0_L,           PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S4_L,           PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,           PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L_PCH,      PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ACOK_OD,            PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(ROP_INT_L,          PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
-
-/* Misc. interrupts */
-GPIO_INT(H1_EC_VOL_DOWN_ODL, PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(H1_EC_VOL_UP_ODL,   PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_L,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(LID_OPEN,           PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(ACCELGYRO3_INT_L,   PIN(4, 1), GPIO_INT_FALLING, bmi160_interrupt)
-GPIO_INT(BASE_USB_FAULT_ODL, PIN(2, 3), GPIO_INT_FALLING, base_pwr_fault_interrupt)
-GPIO_INT(BASE_PWR_FAULT_ODL, PIN(2, 4), GPIO_INT_FALLING, base_pwr_fault_interrupt)
-GPIO_INT(RCAM_VSYNC,         PIN(E, 4), GPIO_INT_RISING, sync_interrupt)
-GPIO_INT(CCD_MODE_ODL,       PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)
-
-/* SoC */
-GPIO(RSMRST_L,               PIN(C, 2), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_L,       PIN(C, 1), GPIO_OUT_HIGH)
-GPIO(EC_PCH_RTCRST,          PIN(7, 6), GPIO_OUT_LOW)
-GPIO(SLP_SUS_L_PMIC,         PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_L,          PIN(7, 4), GPIO_ODR_HIGH | GPIO_PULL_UP)
-GPIO(EC_PROCHOT_ODL,         PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(SYS_RESET_L,            PIN(0, 2), GPIO_ODR_HIGH)
-GPIO(USB_C0_DP_HPD,          PIN(C, 5), GPIO_OUT_LOW)
-GPIO(USB_C1_DP_HPD,          PIN(C, 6), GPIO_OUT_LOW)
-
-/* Power Sequencing */
-GPIO(EC_PCH_ACPRESENT,       PIN(7, 3), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_OC_ODL,          PIN(6, 7), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,          PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EN_5V,                  PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_3A,           PIN(6, 2), GPIO_OUT_LOW)
-GPIO(EN_USB_C1_3A,           PIN(8, 3), GPIO_OUT_LOW)
-
-/* Misc */
-GPIO(EC_BRD_ID0,             PIN(4, 0), GPIO_INPUT)
-GPIO(EC_BRD_ID1,             PIN(9, 6), GPIO_INPUT)
-GPIO(EC_BRD_ID2,             PIN(9, 3), GPIO_INPUT)
-GPIO(EC_BRD_ID3,             PIN(F, 0), GPIO_INPUT)
-GPIO(EC_INT_L,               PIN(9, 5), GPIO_OUT_HIGH)
-GPIO(UHALL_PWR_EN,           PIN(E, 0), GPIO_OUT_HIGH)
-GPIO(USB2_VBUSSENSE,         PIN(A, 2), GPIO_OUT_LOW)
-GPIO(USB2_ID,                PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_PD_RST_L,           PIN(F, 1), GPIO_OUT_HIGH)
-GPIO(ALS_INT_L,              PIN(5, 0), GPIO_INPUT)
-GPIO(EC_BATT_PRES_L,         PIN(E, 5), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,         PIN(E, 1), GPIO_OUT_LOW)
-GPIO(EC_BL_DISABLE_ODL,      PIN(D, 3), GPIO_ODR_HIGH)
-GPIO(EC_PLATFORM_RST,        PIN(8, 6), GPIO_OUT_LOW)
-GPIO(EC_GPIO31,              PIN(3, 1), GPIO_OUT_LOW)
-GPIO(BASE_PWR_EN,            PIN(2, 2), GPIO_OUT_LOW)
-GPIO(PP3300_NVME_EN,         PIN(2, 1), GPIO_INPUT | GPIO_PULL_DOWN) /*NC*/
-GPIO(PP1800_NVME_EN,         PIN(2, 0), GPIO_INPUT | GPIO_PULL_DOWN) /*NC*/
-GPIO(PPVAR_NVME_CORE_EN,     PIN(1, 7), GPIO_INPUT | GPIO_PULL_DOWN) /*NC*/
-GPIO(EC_GPIO16,              PIN(1, 6), GPIO_OUT_LOW)
-GPIO(EC_GPIO15,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(EC_GPIO14,              PIN(1, 4), GPIO_OUT_LOW)
-
-/* I2C pins */
-GPIO(EC_I2C1_USB_C0_SCL,     PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,     PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,     PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,     PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C5_ALS_GYRO_SCL,   PIN(3, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C5_ALS_GYRO_SDA,   PIN(3, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C0_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C4_BATTERY_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_BATTERY_SDA,    PIN(F, 2), GPIO_INPUT)
-
-/* Strap pins */
-GPIO(GPO66_NC,       PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,       PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Alternate mode configuration */
-/* UART pins */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-/* I2C ports */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL, I2C 2 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, GPIO_INPUT | GPIO_SEL_1P8V) /* 1.8V I2C5 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0) /* PWM7 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* PWM5 */
-ALTERNATE(PIN_MASK(C, 0x19), 0, MODULE_PWM, 0) /* PWM0,2, 6 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0,1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0) /* GPIO00, GPIO01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 */
diff --git a/board/nocturne/led.c b/board/nocturne/led.c
deleted file mode 100644
index b214a8df84..0000000000
--- a/board/nocturne/led.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nocturne specific PWM LED settings. */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map_v3[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  36,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  15,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  36,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  30,   9,  15 },
-	[EC_LED_COLOR_AMBER]  = {  30,   1,   0 },
-};
-
-/* Map for board rev 2 */
-struct pwm_led_color_map led_color_map_v2[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  62,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  31,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = { 100,  54,   0 },
-	[EC_LED_COLOR_WHITE]  = {  70,  54, 100 },
-	[EC_LED_COLOR_AMBER]  = { 100,  15,   0 },
-};
-
-/* Map for board rev 0 and 1 */
-struct pwm_led_color_map led_color_map_v0_1[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {   1,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   1,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0,   1 },
-	[EC_LED_COLOR_YELLOW] = {   1,   1,   0 },
-	[EC_LED_COLOR_WHITE]  = {   9,  15,  15 },
-	[EC_LED_COLOR_AMBER]  = {  15,   1,   0 },
-};
-
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { { 0 } };
-
-/* Two tri-color LEDs with red, green, and blue channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_DB0_LED_RED,
-		.ch1 = PWM_CH_DB0_LED_GREEN,
-		.ch2 = PWM_CH_DB0_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-
-	{
-		.ch0 = PWM_CH_DB1_LED_RED,
-		.ch1 = PWM_CH_DB1_LED_GREEN,
-		.ch2 = PWM_CH_DB1_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_YELLOW] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_LEFT_LED)
-		pwm_id = PWM_LED0;
-	else if (led_id == EC_LED_ID_RIGHT_LED)
-		pwm_id = PWM_LED1;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
-
-static void fill_led_color_map(struct pwm_led_color_map map[])
-{
-	memcpy(led_color_map, map,
-	       EC_LED_COLOR_COUNT * sizeof(struct pwm_led_color_map));
-}
-
-static void select_color_map(void)
-{
-	switch (board_get_version()) {
-	case 0:
-	case 1:
-		fill_led_color_map(led_color_map_v0_1);
-		break;
-
-	case 2:
-		fill_led_color_map(led_color_map_v2);
-		break;
-
-	default:
-		fill_led_color_map(led_color_map_v3);
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM-1);
diff --git a/board/nocturne/usb_pd_policy.c b/board/nocturne/usb_pd_policy.c
deleted file mode 100644
index 14329b61b3..0000000000
--- a/board/nocturne/usb_pd_policy.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Do not allow VCONN swap is 5V is off. */
-	return gpio_get_level(GPIO_EN_5V);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	int level;
-
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	level = (data_role == PD_ROLE_UFP) ? 1 : 0;
-
-	gpio_set_level(GPIO_USB2_ID, level);
-	gpio_set_level(GPIO_USB2_VBUSSENSE, level);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/*
-	 * Disable VBUS and discharge to vSafe0V.
-	 *
-	 * The PPC will automatically disable the discharge circuitry once it
-	 * reaches vSafe0V.
-	 */
-	ppc_vbus_source_enable(port, 0);
-	ppc_discharge_vbus(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= ppc_cnt)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* The 5V rail used for sourcing is not powered when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-__override void svdm_safe_dp_mode(int port)
-{
-	/* make DP interface safe until configure */
-	usb_mux_set(port, USB_PD_MUX_NONE,
-		USB_SWITCH_CONNECT,
-		polarity_rm_dts(pd_get_polarity(port)));
-
-	/*
-	 * Isolate the SBU lines.
-	 *
-	 * Older boards don't have the SBU line bypass needed for CCD, so never
-	 * disable the SBU lines for port 0.
-	 */
-	if ((board_get_version() < 2) && (port == 0))
-		CPRINTS("Skip disable SBU lines for C0.");
-	else
-		ppc_set_sbu(port, 0);
-}
diff --git a/board/nocturne/vif_override.xml b/board/nocturne/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nocturne/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/nocturne_fp/OWNERS b/board/nocturne_fp/OWNERS
deleted file mode 100644
index ba92c193e0..0000000000
--- a/board/nocturne_fp/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../common/fpsensor/OWNERS
diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h
deleted file mode 100644
index 1f89c631eb..0000000000
--- a/board/nocturne_fp/board.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * STM32H743 + FPC 1145 Fingerprint MCU configuration
- *
- * Alternate names that share this same board file:
- *   nocturne_fp
- *   nami_fp
- *   dartmonkey
- *   dragontalon
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/*
- * Flash layout: we redefine the sections offsets and sizes as we want to
- * include a rollback region, and will use RO/RW regions of different sizes.
- */
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_SHAREDLIB_SIZE   0
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (768*1024)
-
-/* EC rollback protection block */
-#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2)
-
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * We want to prevent flash readout, and use it as indicator of protection
- * status.
- */
-#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-
-/* the UART console is on USART1 */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_TX_DMA
-#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART1_TX
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Optional features */
-#undef CONFIG_ADC
-#define CONFIG_CMD_IDLE_STATS
-#define CONFIG_DMA
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_FPU
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOST_COMMAND_STATUS
-#undef CONFIG_I2C
-#undef CONFIG_LID_SWITCH
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_SPI
-#define CONFIG_STM_HWTIMER32
-#undef CONFIG_TASK_PROFILING
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WP_ACTIVE_HIGH
-#define CONFIG_PANIC_STRIP_GPR
-
-/* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
-
-#define CONFIG_FINGERPRINT_MCU
-#ifdef SECTION_IS_RW
-#define CONFIG_FP_SENSOR_FPC1145
-#define CONFIG_CMD_FPSENSOR_DEBUG
-/*
- * Use the malloc code only in the RW section (for the private library),
- * we cannot enable it in RO since it is not compatible with the RW verification
- * (shared_mem_init done too late).
- */
-#define CONFIG_MALLOC
-/* Special memory regions to store large arrays */
-#define FP_FRAME_SECTION    __SECTION(ahb4)
-#define FP_TEMPLATE_SECTION __SECTION(ahb)
-
-#else /* SECTION_IS_RO */
-/* RO verifies the RW partition signature */
-#define CONFIG_RSA
-#define CONFIG_RWSIG
-#endif
-
-#define CONFIG_RSA_KEY_SIZE 3072
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_RWSIG_TYPE_RWSIG
-
-/* RW does slow compute, RO does slow flash erase. */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 10000
-
-/*
- * Add rollback protection
- */
-#define CONFIG_ROLLBACK
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-
-#define CONFIG_ROLLBACK_MPU_PROTECT
-
-/*
- * We do not use any "locally" generated entropy: this is normally used
- * to add local entropy when the main source of entropy is remote.
- */
-#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-#ifdef SECTION_IS_RW
-#undef CONFIG_ROLLBACK_UPDATE
-#endif
-
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-
-#define CONFIG_RNG
-
-#define CONFIG_CMD_FLASH
-
-#ifdef SECTION_IS_RW
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_CMD_SPI_XFER
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * Mitigating the effects of b/146428434.
- */
-#define APPLY_RESET_LOOP_FIX
-#endif
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 16
-
-#include "gpio_signal.h"
-#include "board_rw.h"
-
-void slp_event(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __BOARD_H */
diff --git a/board/nocturne_fp/board_ro.c b/board/nocturne_fp/board_ro.c
deleted file mode 100644
index 7f20002435..0000000000
--- a/board/nocturne_fp/board_ro.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Meowth Fingerprint MCU configuration */
-
-#include "common.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-
-#ifndef SECTION_IS_RO
-#error "This file should only be built for RO."
-#endif
-
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#include "gpio_list.h"
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
-		      gpio_get_level(GPIO_SLP_L);
-
-	if (running) { /* AP is S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* AP is suspend/S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-void board_init(void)
-{
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_SLP_ALT_L);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.c b/board/nocturne_fp/board_rw.c
deleted file mode 100644
index 0a7b38b97d..0000000000
--- a/board/nocturne_fp/board_rw.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "board_rw.h"
-
-#ifndef SECTION_IS_RW
-#error "This file should only be built for RW."
-#endif
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-#include "gpio_list.h"
-
-/* SPI devices */
-struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI4_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/* Allow changing the signal used for alt sleep depending on the board being
- * used: http://b/179946521.
- */
-static int gpio_slp_alt_l = GPIO_SLP_ALT_L;
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(gpio_slp_alt_l) &&
-		      gpio_get_level(GPIO_SLP_L);
-
-	if (running) { /* AP is S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* AP is suspend/S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-static void spi_configure(enum fp_sensor_spi_select spi_select)
-{
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT) {
-		/* SPI4 master to sensor: PE12/13/14 (CLK/MISO/MOSI) */
-		gpio_set_flags_by_mask(GPIO_E, 0x7000, 0);
-		gpio_set_alternate_function(GPIO_E, 0x7000, GPIO_ALT_SPI);
-	} else {
-		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	}
-
-	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
-	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
-	/* Enable clocks to SPI4 module (master) */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
-
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
-		spi_devices[0].gpio_cs = GPIO_SPI4_ALT_NSS;
-	spi_enable(&spi_devices[0], 1);
-}
-
-void board_init(void)
-{
-	enum fp_sensor_spi_select spi_select = get_fp_sensor_spi_select();
-
-	/*
-	 * FP_RST_ODL pin is defined in gpio_rw.inc (with GPIO_OUT_HIGH
-	 * flag) but not in gpio.inc, so RO leaves this pin set to 0 (reset
-	 * default), but RW doesn't initialize this pin to 1 because sysjump
-	 * to RW is a warm reset (see gpio_pre_init() in chip/stm32/gpio.c).
-	 * Explicitly reset FP_RST_ODL pin to default value.
-	 */
-	gpio_reset(GPIO_FP_RST_ODL);
-
-	ccprints("FP_SPI_SEL: %s", fp_sensor_spi_select_to_str(spi_select));
-
-	spi_configure(spi_select);
-
-	ccprints("TRANSPORT_SEL: %s",
-		 fp_transport_type_to_str(get_fp_transport_type()));
-
-	/* Use SPI select as a proxy for running on the icetower dev board. */
-	if (spi_select == FP_SENSOR_SPI_SELECT_DEVELOPMENT)
-		gpio_slp_alt_l = GPIO_SLP_ALT_DEV_L;
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(gpio_slp_alt_l);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nocturne_fp/board_rw.h b/board/nocturne_fp/board_rw.h
deleted file mode 100644
index 6ef7cc29b4..0000000000
--- a/board/nocturne_fp/board_rw.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
-#define __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H
-
-void fps_event(enum gpio_signal signal);
-
-/* Defined in ro_workarounds.c */
-void wp_event(enum gpio_signal signal);
-
-#endif /* __CROS_EC_BOARD_NOCTURNE_FP_BOARD_RW_H */
diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk
deleted file mode 100644
index 2091acc101..0000000000
--- a/board/nocturne_fp/build.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32H743
-CHIP:=stm32
-CHIP_FAMILY:=stm32h7
-CHIP_VARIANT:=stm32h7x3
-
-# Don't forget that the board build.mk is included more than once to allow
-# conditional variables to be realized. This means that we need to redefine all
-# variable or the "+=" lines will compound.
-board-y=
-board-rw=ro_workarounds.o board_rw.o
-board-ro=board_ro.o
-# If we're mocking the sensor detection for testing (so we can test
-# sensor/transport permutations in the unit tests), don't build the real sensor
-# detection.
-ifeq ($(HAS_MOCK_FPSENSOR_DETECT),)
-	board-rw+=fpsensor_detect_rw.o
-	board-y+=fpsensor_detect.o
-endif
-
-# Do not build rsa test because this board uses RSA exponent 3 and the rsa test
-# will fail on device.
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       fpsensor \
-       fpsensor_hw \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/nocturne_fp/dev_key.pem b/board/nocturne_fp/dev_key.pem
deleted file mode 100644
index 35c0035b20..0000000000
--- a/board/nocturne_fp/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAoxINZU5fQAiABFm4xT83HUQx/WvRlyZ3ZfRqTyMlMxw7U0cU
-DEw7fOY0oj20bkpmVJRfwkm4k7BwOuTt3nl5UuKgeztL4gW+h++ptIIzfT2/a4KL
-BnHsuNfgXZ+yzJ5RSKlJwVOibJr5CNfsmESX4Lwe3LudFc7iE/yfgsOyU/9Ha/jB
-mgLywyWObwpfAt+viOCIF4mYeEI5bLpDHqwk6EnEq0jWaNpcEsLA/twhDf2Qxc7I
-7Zds3f6C3iA1N/d0Zmva4UvdAGnFzQlq9mmgnCenIjwEb4jxqcFXaMgk88jkcheY
-q7MQANRt+iYOX2MiUNtigUoDoJTMBiV3bRs47sSiH+lS6hZHdOsmjMyF30bV5IJD
-k+x1Zoxsd2jYR1PXgxZ+pxLoKx/m9KIV8onbqgl0Jx4+JkABH5eYp/KAhObCenLS
-CySFi7OLbi915yydzFJ3C34pgWVN077GVCXGqglxDcNMacqXqHCwOUoNuAGXjxyF
-XH33G9a/TJDzQhZFAgEDAoIBgGy2s5je6iqwVVg70IN/ehOCy/5H4Q9u+kP4Rt9s
-w3doJ4zaDV2IJ6iZeGwpIvQxmY24P9bb0GJ1oCdDST77pjdBwFInh+wD1FqfxnhW
-zP4pKkesXK72ndCP6ukVId2+4NsbhoDibEhnULCP8xAtupXSvz3SaLk0lrf9v6yC
-duKqL51QgRFXTIIZCZ9cP1c/yltAWrpbuvrW0PMm12nIGJrb2HIwjvCRkrcsgKno
-FglTtdk0hfO6SJP/AelqziVPod5DxP4Gcws0JWnWjIKtYmNpIrI/sfVD29DNLYYS
-Pn1Vgxi5UcwfEbcxkwxMKoJOUb1WSPkvjpQTlQUPiBLX3sLpLvxaOVrEjNXy+V13
-Jl7bc2dGbDIsQMXkFiodTHsqwAq1diFOUL9oE6VeES2hmX63f7lHSXMb92phmvs4
-BylzoTK64ew8oUkufLTX/ys0LGiGvPXCrdfDxdsO2Rx90XB5YPcvvQKge0eCfDck
-kCX4C/6j7V3y/nS5GzpLCFshqwKBwQDVaKdjlpzAKKu+hfBRaujZsrgXd2i4LTuI
-r+sclHl4aII0HJbSolsiV8Pc+jcFtvzLDUnSh4Pjza/6qtYF0q3fxAXQCmBAq8Xc
-AF2sYmZJmMT4OajMS0LG7nhYgm5OpXpyvgc+ndBnDtqXVPQy/wpo8dBV8G1QtXbj
-OsvrTeQ8ZaFcUA4jOuyz+VNpONOUzvxx/jVwuEDVl7xB5/6TayNbCrecqd6CsSur
-S3Z21lelrCV/CjIJqkPZQlgwsKE31CUCgcEAw52MAKuTr3Lh78Gn4PqkLVc6/2UQ
-x3XsZ92oAxhNv2AdmOUHJuIaS7JNirmXljaq6cyrOPsp3qm8g+NVSwS86qLV1Vec
-oUOuV/5S1DdmB2Tj0V74fF7RdsfS37p3P+49AEhGNn+epPTu5UAH+xhrAwRkO0Li
-qOCXHMpkQ9CRilOvUgpxBY6m6fR89bKjkY9evYomKiHj6CfoyUCCFf3pJkin/lHS
-YyizEeF/b7zd2WFgEhxvRec1k36+RG/FgY+hAoHBAI5FxO0PEyrFx9RZSuDx8JEh
-0A+k8HrI0lsf8hMNplBFrCK9ueHBkhblLT38JK55/dyzhoxaV+0zyqccjq6Mc+qC
-roqxlYByg+gAPnLsRDEQg1AmcIgyLISe+uWsSYnDpvcpWim+iu9fPGTjTXdUsZtL
-4DlK84sjpJd8h/Iz7X2ZFj2KtBd8nc1Q4kYl4mM0qEv+zkslgI5lKCvv/wzyF5IH
-JRMb6ax2HRzc+aSO5RkdblSxdrEcLTuBkCB1wM/iwwKBwQCCaQgAcmJ090FKgRqV
-/G1zj3yqQ2CE+UhFPnACEDPU6r5l7gTElrwydt5ce7pkJHHxMxzQp3E/G9MCl44y
-AyicbI6OOmhrgnQ6qYyNekQE7e02P1BS6eD52oyVJvoqntNVhYQkVRRt+J9DgAVS
-EEdXWELSLJcbQGS93ELX4GEG4nThXEtZCcSb+FNOdxe2X5R+XBlxa+1Fb/CGKwFj
-/ptu2xqpi+GXcHdhQP+f0z6Q65VhaEoumiO3qdQtn9kBCmsCgcEA0/VwBz03FMcv
-2SM6zDbL2Kf4PnnLJuDHFzItWH8smrBNVfOOuJ5KGhuIHAAJxaQoWBxeYeaPPqme
-5rQRl58XEb5h3FswAKPx2U77NUROtObOVffV5Tid1E+iBQYhlUUkxtE5b+Said3u
-LqkP8K5n1ai2xuvHusuL6vcp/5T+WrSG5GDiGU+27c2Uf/NePbFYggLl3P9rmDM8
-/1xGGpxMGV2OrOhXtPk7LykEdJRuN+7YhNX5dW1LwWcicOLkFVOG
------END RSA PRIVATE KEY-----
diff --git a/board/nocturne_fp/ec.tasklist b/board/nocturne_fp/ec.tasklist
deleted file mode 100644
index ed1e6ed294..0000000000
--- a/board/nocturne_fp/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
-	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/nocturne_fp/fpsensor_detect.c b/board/nocturne_fp/fpsensor_detect.c
deleted file mode 100644
index 5a4b95e64c..0000000000
--- a/board/nocturne_fp/fpsensor_detect.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-
-enum fp_transport_type get_fp_transport_type(void)
-{
-	return FP_TRANSPORT_TYPE_SPI;
-}
diff --git a/board/nocturne_fp/fpsensor_detect_rw.c b/board/nocturne_fp/fpsensor_detect_rw.c
deleted file mode 100644
index e4a670e211..0000000000
--- a/board/nocturne_fp/fpsensor_detect_rw.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "timer.h"
-
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	return FP_SENSOR_TYPE_FPC;
-}
-
-enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
-{
-	enum fp_sensor_spi_select ret;
-
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
-	usleep(1);
-	switch (gpio_get_level(GPIO_FP_SPI_SEL)) {
-	case 0:
-		ret = FP_SENSOR_SPI_SELECT_DEVELOPMENT;
-		break;
-	case 1:
-		ret = FP_SENSOR_SPI_SELECT_PRODUCTION;
-		break;
-	default:
-		ret = FP_SENSOR_SPI_SELECT_UNKNOWN;
-		break;
-	}
-	gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 0);
-	return ret;
-}
diff --git a/board/nocturne_fp/gpio.inc b/board/nocturne_fp/gpio.inc
deleted file mode 100644
index dc15ab0ef0..0000000000
--- a/board/nocturne_fp/gpio.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(SLP_L,           PIN(D,13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SLP_ALT_L,       PIN(A,11), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SPI1_NSS,        PIN(A, 4), GPIO_INPUT, spi_event)
-
-/* Inputs */
-#ifndef APPLY_RESET_LOOP_FIX
-GPIO(WP,                  PIN(B, 7), GPIO_INPUT)
-#endif
-
-/* Outputs */
-GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
-
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART1: PA9/PA10 (TX/RX) */
-ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
-/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
-
-#ifdef SECTION_IS_RW
-#include "gpio_rw.inc"
-#endif
diff --git a/board/nocturne_fp/gpio_rw.inc b/board/nocturne_fp/gpio_rw.inc
deleted file mode 100644
index 2de4c3e92a..0000000000
--- a/board/nocturne_fp/gpio_rw.inc
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef SECTION_IS_RW
-#error "This file should only be included in RW."
-#endif
-
-/* Interrupts */
-GPIO_INT(FPS_INT,         PIN(A, 0), GPIO_INT_RISING, fps_event)
-
-#ifdef APPLY_RESET_LOOP_FIX
-GPIO_INT(WP,              PIN(B, 7), GPIO_INT_BOTH, wp_event)
-#endif
-
-/* Inputs */
-GPIO_INT(SLP_ALT_DEV_L,   PIN(D,14), GPIO_INT_BOTH, slp_event)
-/*
- * The S4 and SUS sleep lines are unused in code, but are maintained in this
- * gpio list to ensure that they are not repurposed. This is because these
- * inputs are driven on nocturne.
- */
-GPIO(PCH_SLP_S4_L,        PIN(D, 8), GPIO_INPUT)
-GPIO(PCH_SLP_SUS_L,       PIN(D, 3), GPIO_INPUT)
-/* TODO(b/178808871): Only enable pull up when doing detection. */
-GPIO(FP_SPI_SEL,          PIN(E, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Outputs */
-GPIO(DIVIDER_HIGHSIDE,    PIN(B, 8),  GPIO_OUT_LOW)
-GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
-GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
-GPIO(SPI4_ALT_NSS,        PIN(E, 11), GPIO_OUT_HIGH)
-GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
-
-/* Default SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER,  0)
-
-/* See board_rw.c for the alternate configuration that we use on
- * development boards, which overrides the UNUSED values below.
- */
-UNUSED(PIN(E, 12))  /* Alternate SPI4 master to sensor CLK */
-UNUSED(PIN(E, 13))  /* Alternate SPI4 master to sensor MISO */
-UNUSED(PIN(E, 14))  /* Alternate SPI4 master to sensor MOSI */
diff --git a/board/nocturne_fp/ro_workarounds.c b/board/nocturne_fp/ro_workarounds.c
deleted file mode 100644
index e980d14877..0000000000
--- a/board/nocturne_fp/ro_workarounds.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* A place to organize workarounds for legacy RO */
-
-#include <assert.h>
-#include <stdbool.h>
-
-#include "bkpdata.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h" /* Reset cause */
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/*
- * We only patch RW to ensure that future ROs have correct behavior.
- */
-#if defined(APPLY_RESET_LOOP_FIX) && defined(SECTION_IS_RW)
-
-/*
- * Add in ap-off flag to be able to detect on next boot.
- * No other code in this build uses this ap-off reset flag.
- */
-#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON|EC_RESET_FLAG_AP_OFF)
-
-static void wp_change_deferred(void)
-{
-	/*
-	 * The normal state of the reset backup register is 0, but
-	 * we know that our override version of bkpdata_write_reset_flags
-	 * will adjust it based on GPIO_WP's status.
-	 */
-	bkpdata_write_reset_flags(0);
-}
-DECLARE_DEFERRED(wp_change_deferred);
-
-/*
- * We respond to changes in the hardware write protect line in order to
- * ensure this workaround is installed when it is needed and uninstalled
- * when it is not needed. This ensures that we are protected during
- * unexpected resets, such as pin resets or double faults.
- *
- * Furthermore, installing and uninstalling when needed minimizes the
- * difference between our normal operating conditions and normal operating
- * conditions with this ro_workaround source being included. That is to say,
- * the system behavior is only altered in the less likely state, when hardware
- * write protect deasserted.
- */
-void wp_event(enum gpio_signal signal)
-{
-	/*
-	 * We must use a deferred function to call bkpdata_write_reset_flags,
-	 * since the underlying bkpdata_write uses a mutex.
-	 */
-	hook_call_deferred(&wp_change_deferred_data, 0);
-}
-
-/*
- * We intercept all changes to the reset backup register to ensure that
- * our reset loop patch stays in place.
- *
- * This function will be called once in check_reset_cause during
- * startup, which ensures proper behavior even when unexpected
- * resets occurs (pin reset or exception).
- *
- * This function is also called from system_reset to set the final save
- * reset flags, before an actual planned reset.
- */
-__override
-void bkpdata_write_reset_flags(uint32_t save_flags)
-{
-	/* Preserve flags in case a reset pulse occurs */
-	if (!gpio_get_level(GPIO_WP))
-		save_flags |= FORGE_PORFLAG_FLAGS;
-
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-}
-
-/*
- * We do not need to explicitly invoke bkpdata_write_reset_flags
- * on boot, since check_reset_cause will already invoke it once on boot.
- */
-static void board_init_workarounds(void)
-{
-	gpio_disable_interrupt(GPIO_WP);
-	gpio_clear_pending_interrupt(GPIO_WP);
-
-	/*
-	 * Detect our forged power-on flag and correct the current
-	 * system reset flags.
-	 * This does not ensure that all init functions will see
-	 * the corrected system reset flags, so care should be taken.
-	 */
-	if ((system_get_reset_flags() & FORGE_PORFLAG_FLAGS) ==
-	    FORGE_PORFLAG_FLAGS) {
-		CPRINTS("WARNING: Reset flags power-on + ap-off were forged.");
-		system_clear_reset_flags(FORGE_PORFLAG_FLAGS);
-	}
-
-	gpio_enable_interrupt(GPIO_WP);
-}
-/* Run one priority level higher than the main board_init in board.c */
-DECLARE_HOOK(HOOK_INIT, board_init_workarounds, HOOK_PRIO_DEFAULT - 1);
-
-#endif /* APPLY_RESET_LOOP_FIX && SECTION_IS_RW */
diff --git a/board/npcx7_evb/board.c b/board/npcx7_evb/board.c
deleted file mode 100644
index 9ddaf9bd51..0000000000
--- a/board/npcx7_evb/board.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nuvoton M4 EB board-specific configuration */
-
-#include "adc.h"
-#include "backlight.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/temp_sensor/tmp006.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
-	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_PGOOD_FAN,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0},
-	{"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0},
-	{"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0},
-	{"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 40,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
-	},
-};
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
deleted file mode 100644
index 4bad61b152..0000000000
--- a/board/npcx7_evb/board.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Nuvoton M4 EB */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * npcx7 EVB version:
- * 1 - EVB version 1 supports: npcx7m6g
- * 2 - EVB version 2 supports:
- *     npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc
- */
-#if defined(CHIP_VARIANT_NPCX7M6G)
-#define BOARD_VERSION  1
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define BOARD_VERSION  2
-#endif
-
-/* EC modules */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_SPI
-#define CONFIG_I2C
-/* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Optional features */
-#define CONFIG_ENABLE_JTAG_SELECTION
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
-#define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
-
-/* EC console commands */
-#define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
-#define CONFIG_CMD_JUMPTAGS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_I2CWEDGE
-
-/* I2C port for CONFIG_CMD_I2CWEDGE */
-#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
-
-/* Fans for testing */
-#define CONFIG_FANS 1
-
-/* Internal spi-flash on npcx7 ec */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_REGS
-#if defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
-#else
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB internal spi flash */
-#endif
-
-/* New features on npcx7 ec */
-#define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
-#if (BOARD_VERSION == 2)
-#define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
-#define CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
-#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_AUDIO_CODEC
-#define CONFIG_AUDIO_CODEC_DMIC
-#define CONFIG_AUDIO_CODEC_I2S_RX /* Use Audio front-end for Wake-on-Voice */
-#endif
-#undef CONFIG_FANS /* Remove fan application */
-#else
-#undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
-#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
-#endif
-
-/* Optional feature to configure npcx7 chip */
-
-/* Select which UART Controller is the Console UART */
-#undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
-/*
- * This definition below actually doesn't define which UART controller to be
- * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
- * connected to "UART1" controller.
- */
-#if (BOARD_VERSION == 2)
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
-#else
-#define NPCX_UART_MODULE2  0 /* 0:GPIO10/11 as UART1 */
-#endif
-#define NPCX_JTAG_MODULE2  0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_3,
-	ADC_CH_4,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/npcx7_evb/build.mk b/board/npcx7_evb/build.mk
deleted file mode 100644
index 4bd829202c..0000000000
--- a/board/npcx7_evb/build.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Nuvoton NPCX7 M-Series EC (npcx7m6g, npcx7m6f, npcx7m6fb, npcx7m6fc,
-# npcx7m7fc, npcx7m7wb, npcx7m7wc)
-# CHIP_VARIANT:
-#    npcx7m6g  - for npcx7 ec without internal flash
-#    npcx7m6f  - for npcx7 ec with internal flash
-#    npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
-#    npcx7m6fc - the same as npcx7m6fb but internal flash size is 512 Kbytes.
-#    npcx7m7fc - the same as npcx7m6fc but more RAM sizes.
-#    npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.
-#    npcx7m7wc - the same as npcx7m7wb but internal flash size is 512 Kbytes.
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wb
-
-board-y=board.o
diff --git a/board/npcx7_evb/ec.tasklist b/board/npcx7_evb/ec.tasklist
deleted file mode 100644
index 88b5ffaa62..0000000000
--- a/board/npcx7_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/npcx7_evb/gpio.inc b/board/npcx7_evb/gpio.inc
deleted file mode 100644
index 145a48de85..0000000000
--- a/board/npcx7_evb/gpio.inc
+++ /dev/null
@@ -1,114 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Pins for internal flash testing */
-GPIO_INT(RECOVERY_L,       PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-GPIO_INT(WP_L,             PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-
-/* Pins for hibernate testing */
-#ifdef CONFIG_HIBERNATE_PSL
-/*
- * Please notice internal PU/PD is gone if IOs are selected to PSL_INx. The
- * power consumption of PSL is ultra-low and sensitive. Putting a large
- * external PU/PD resistance for PSL input pins is recommended.
- */
-GPIO_INT(AC_PRESENT,       PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt)                 /* PSL_IN1# (Low Active) */
-GPIO_INT(POWER_BUTTON_L,   PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)             /* PSL_IN2# (Low Active) */
-GPIO_INT(LID_OPEN,         PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) /* PSL_IN3# (High Active) */
-#else
-GPIO_INT(AC_PRESENT,       PIN(7, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L,   PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-GPIO_INT(LID_OPEN,         PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
-#endif
-
-/* Pins for SPI/FAN/LPC modules testing */
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_OUT_LOW )
-GPIO(PCH_WAKE_L,           PIN(5, 0), GPIO_OUT_HIGH)
-GPIO(PGOOD_FAN,            PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(SPI_CS_L,             PIN(A, 5), GPIO_OUT_HIGH)
-
-/* Pins for I2C module testing */
-GPIO(I2C0_SCL0,            PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA0,            PIN(B, 4), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL0,            PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA0,            PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL0,            PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA0,            PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL0,            PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA0,            PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(I2C7_SDA0,            PIN(B, 2), GPIO_ODR_HIGH)
-GPIO(I2C7_SCL0,            PIN(B, 3), GPIO_ODR_HIGH)
-
-/* Pins for board version command */
-GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)
-GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)
-
-/*********************** Alternate pins for npcx7 series **********************/
-#if (CONFIG_CONSOLE_UART == 0)
-/* UART1 Tx/Rx */
-#if NPCX_UART_MODULE2
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO64/65 */
-#else
-ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO10/11 */
-#endif
-#else
-/* UART2 Tx/Rx */
-ALTERNATE(PIN_MASK(7, 0x20), 1, MODULE_UART, 0) /* CR_SIN2  GPIO75 */
-ALTERNATE(PIN_MASK(8, 0x40), 1, MODULE_UART, 0) /* CR_SOUT2 GPIO86 */
-#endif
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3E), 1, MODULE_ADC, 0) /* ADC0/1/2/3/4 GPIO45/44/43/42/41 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
-ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO           GPIO95    */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0) /* PWM2 for KBLIGHT Test - GPIOC4 */
-
-/* Fan (Tachometer) */
-#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for FAN Test - GPIOC3    */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* TA1_SL1 for FAN Test - GPIO93 */
-#else
-ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* TA1_SL2 for FAN Test - GPIO40 */
-#endif
-#endif
-
-/* I2C Ports */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/SCL0          GPIOB4/B5    */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA0               GPIO87       */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL0/I2C2SDA0/SCL0 GPIO90/91/92 */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA0/SCL0          GPIOD0/D1    */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C7SDA0/SCL0          GPIOB2/B3    */
-
-/* Keyboard Columns */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* Keyboard Rows */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* PSL for hibernating */
-#ifdef CONFIG_HIBERNATE_PSL
-ALTERNATE(PIN_MASK(D, 0x04), 1,  MODULE_PMU, 0) /* PSL_IN1     GPIOD2 */
-ALTERNATE(PIN_MASK(0, 0x07), 1,  MODULE_PMU, 0) /* PSL_IN2/3/4 GPIO00/01/02 */
-#endif
-
-#if defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV)
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) /* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) /* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) /* DMIC_CLK/DMIC_IN   GPIO94/97 */
-#endif
diff --git a/board/npcx9_evb/board.c b/board/npcx9_evb/board.c
deleted file mode 100644
index 8bfc053fa5..0000000000
--- a/board/npcx9_evb/board.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nuvoton M4 EB board-specific configuration */
-
-#include "adc.h"
-#include "backlight.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/temp_sensor/tmp112.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_5] = {"ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_6] = {"ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_7] = {"ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_8] = {"ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_9] = {"ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_10] = {"ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_11] = {"ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
-	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_PGOOD_FAN,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* TMP112 sensors. Must be in the exactly same order as in enum tmp112_sensor */
-const struct tmp112_sensor_t tmp112_sensors[] = {
-	{ I2C_PORT_THERMAL, TMP112_I2C_ADDR_FLAGS0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(tmp112_sensors) == TMP112_COUNT);
-
-/******************************************************************************/
-/* Temperature sensor. */
-const struct temp_sensor_t temp_sensors[] = {
-	{ "System", TEMP_SENSOR_TYPE_BOARD, tmp112_get_val_k, TMP112_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master1-0", NPCX_I2C_PORT1_0, 100, GPIO_I2C1_SCL0, GPIO_I2C1_SDA0},
-	{"master2-0", NPCX_I2C_PORT2_0, 100, GPIO_I2C2_SCL0, GPIO_I2C2_SDA0},
-	{"master3-0", NPCX_I2C_PORT3_0, 100, GPIO_I2C3_SCL0, GPIO_I2C3_SDA0},
-	{"master7-0", NPCX_I2C_PORT7_0, 100, GPIO_I2C7_SCL0, GPIO_I2C7_SDA0},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 40,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
-	},
-};
diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h
deleted file mode 100644
index e7e1190480..0000000000
--- a/board/npcx9_evb/board.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Nuvoton M4 EB */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* EC modules */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_I2C
-/* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Optional features */
-#define CONFIG_ENABLE_JTAG_SELECTION
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
-#define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
-
-/* EC console commands */
-#define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
-#define CONFIG_CMD_JUMPTAGS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_RTC
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_I2CWEDGE
-
-/* I2C port for CONFIG_CMD_I2CWEDGE */
-#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
-
-/* Fans for testing */
-#define CONFIG_FANS 1
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP112
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT2_0
-
-#define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
-#define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
-#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
-
-/* Optional feature to configure npcx9 chip */
-
-/* Select which UART Controller is the Console UART */
-#undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
-/*
- * This definition below actually doesn't define which UART controller to be
- * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
- * connected to "UART1" controller.
- */
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX9_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_3,
-	ADC_CH_4,
-	ADC_CH_5,
-	ADC_CH_6,
-	ADC_CH_7,
-	ADC_CH_8,
-	ADC_CH_9,
-	ADC_CH_10,
-	ADC_CH_11,
-	ADC_CH_COUNT
-};
-
-enum tmp112_sensor {
-	TMP112_0,
-	TMP112_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_SYSTHERM0,	/* TMP100 */
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/npcx9_evb/build.mk b/board/npcx9_evb/build.mk
deleted file mode 100644
index 92bcc84144..0000000000
--- a/board/npcx9_evb/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Nuvoton NPCX9 M-Series EC (npcx9m3f, npcx9m6f)
-# CHIP_VARIANT:
-#    npcx9m6f  - for npcx9 ec with 512 KByte internal flash.
-#    npcx9m3f  - for npcx9 ec with 512 KByte internal flash, more RAM.
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-
-board-y=board.o
diff --git a/board/npcx9_evb/ec.tasklist b/board/npcx9_evb/ec.tasklist
deleted file mode 100644
index 9560b43561..0000000000
--- a/board/npcx9_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/npcx9_evb/gpio.inc b/board/npcx9_evb/gpio.inc
deleted file mode 100644
index ec57c1afc5..0000000000
--- a/board/npcx9_evb/gpio.inc
+++ /dev/null
@@ -1,112 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Pins for internal flash testing */
-GPIO_INT(RECOVERY_L,       PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-GPIO_INT(WP_L,             PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, switch_interrupt)
-
-/* Pins for hibernate testing */
-#ifdef CONFIG_HIBERNATE_PSL
-/*
- * Please notice internal PU/PD is gone if IOs are selected to PSL_INx. The
- * power consumption of PSL is ultra-low and sensitive. Putting a large
- * external PU/PD resistance for PSL input pins is recommended.
- */
-GPIO_INT(AC_PRESENT,       PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt)                 /* PSL_IN1# (Low Active) */
-GPIO_INT(POWER_BUTTON_L,   PIN(0, 0), GPIO_INT_BOTH, power_button_interrupt)             /* PSL_IN2# (Low Active) */
-GPIO_INT(LID_OPEN,         PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) /* PSL_IN3# (High Active) */
-#else
-GPIO_INT(AC_PRESENT,       PIN(7, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L,   PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-GPIO_INT(LID_OPEN,         PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
-#endif
-
-/* Pins for SPI/FAN/LPC modules testing */
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_OUT_LOW )
-GPIO(PCH_WAKE_L,           PIN(5, 0), GPIO_OUT_HIGH)
-GPIO(PGOOD_FAN,            PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(SPI_CS_L,             PIN(A, 5), GPIO_OUT_HIGH)
-
-/* Pins for I2C module testing */
-GPIO(I2C0_SCL0,            PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA0,            PIN(B, 4), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL0,            PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA0,            PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL0,            PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA0,            PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL0,            PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA0,            PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(I2C7_SDA0,            PIN(B, 2), GPIO_ODR_HIGH)
-GPIO(I2C7_SCL0,            PIN(B, 3), GPIO_ODR_HIGH)
-
-/* Pins for board version command */
-GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)
-GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)
-GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)
-
-/*********************** Alternate pins for npcx7 series **********************/
-#if (CONFIG_CONSOLE_UART == 0)
-/* UART1 Tx/Rx */
-#if NPCX_UART_MODULE2
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO64/65 */
-#else
-ALTERNATE(PIN_MASK(1, 0x03), 1, MODULE_UART, 0) /* CR_SIN/SOUT  GPIO10/11 */
-#endif
-#else
-/* UART2 Tx/Rx */
-ALTERNATE(PIN_MASK(7, 0x20), 1, MODULE_UART, 0) /* CR_SIN2  GPIO75 */
-ALTERNATE(PIN_MASK(8, 0x40), 1, MODULE_UART, 0) /* CR_SOUT2 GPIO86 */
-#endif
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3E), 1, MODULE_ADC, 0) /* ADC0/1/2/3/4 GPIO45/44/43/42/41 */
-ALTERNATE(PIN_MASK(3, 0x90), 1, MODULE_ADC, 0) /* ADC5/6 GPIO37/34 */
-ALTERNATE(PIN_MASK(E, 0x03), 1, MODULE_ADC, 0) /* ADC7/10 GPIOE1/E0 */
-ALTERNATE(PIN_MASK(F, 0x03), 1, MODULE_ADC, 0) /* ADC8/9 GPIOF1/F0 */
-ALTERNATE(PIN_MASK(C, 0x80), 1, MODULE_ADC, 0) /* ADC11 GPIOC7 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
-ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO           GPIO95    */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0) /* PWM2 for KBLIGHT Test - GPIOC4 */
-
-/* Fan (Tachometer) */
-#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for FAN Test - GPIOC3    */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* TA1_SL1 for FAN Test - GPIO93 */
-#else
-ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* TA1_SL2 for FAN Test - GPIO40 */
-#endif
-#endif
-
-/* I2C Ports */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/SCL0          GPIOB4/B5    */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA0               GPIO87       */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL0/I2C2SDA0/SCL0 GPIO90/91/92 */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA0/SCL0          GPIOD0/D1    */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C7SDA0/SCL0          GPIOB2/B3    */
-
-/* Keyboard Columns */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* Keyboard Rows */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
-
-/* PSL for hibernating */
-#ifdef CONFIG_HIBERNATE_PSL
-ALTERNATE(PIN_MASK(D, 0x04), 1,  MODULE_PMU, 0) /* PSL_IN1     GPIOD2 */
-ALTERNATE(PIN_MASK(0, 0x03), 1,  MODULE_PMU, 0) /* PSL_IN2/3/4 GPIO00/01/02 */
-#endif
diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c
deleted file mode 100644
index 61e0665b7f..0000000000
--- a/board/npcx_evb/board.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* EC for Nuvoton M4 EB configuration */
-
-#include "adc.h"
-#include "backlight.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/temp_sensor/tmp006.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
-#if (CONFIG_FANS == 2)
-	[PWM_CH_FAN2] = { 2, 0, 25000 },
-#endif
-	[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_PGOOD_FAN,
-	.enable_gpio = -1,
-};
-
-const struct fan_conf fan_conf_1 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 1,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 5200,
-};
-
-const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 4300,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-#if (CONFIG_FANS == 2)
-	[FAN_CH_1] = { .conf = &fan_conf_1, .rpm = &fan_rpm_1, },
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-#if (CONFIG_FANS == 2)
-	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master0-1", NPCX_I2C_PORT0_1, 100, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
-	{"master1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"master2",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"master3",   NPCX_I2C_PORT3,   100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 40,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
-	},
-};
diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h
deleted file mode 100644
index fc12b6d80a..0000000000
--- a/board/npcx_evb/board.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Nuvoton M4 EB */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional modules */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_SPI
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_PECI
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-#define CONFIG_FLASH_SIZE_BYTES          0x00800000 /* 8MB spi flash */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q64
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_POWER_BUTTON
-#define CONFIG_VBOOT_HASH
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_ENABLE_JTAG_SELECTION
-
-/* Optional features for test commands */
-#define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
-#define CONFIG_CMD_JUMPTAGS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_I2CWEDGE
-
-#define CONFIG_FANS                     1
-
-/* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
-
-/* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-#if (CONFIG_FANS == 2)
-	PWM_CH_FAN2,
-#endif
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-#if (CONFIG_FANS == 2)
-	FAN_CH_1,
-#endif
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-#if (CONFIG_FANS == 2)
-	MFT_CH_1,
-#endif
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/npcx_evb/build.mk b/board/npcx_evb/build.mk
deleted file mode 100644
index 7dfc4544f2..0000000000
--- a/board/npcx_evb/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Nuvoton NPCX5 M-Series EC (npcx5m5g, npcx5m6g)
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx5
-CHIP_VARIANT:=npcx5m5g
-
-board-y=board.o
diff --git a/board/npcx_evb/ec.tasklist b/board/npcx_evb/ec.tasklist
deleted file mode 100644
index b0d584174e..0000000000
--- a/board/npcx_evb/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
deleted file mode 100644
index c4e673fd25..0000000000
--- a/board/npcx_evb/gpio.inc
+++ /dev/null
@@ -1,99 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/********************** Inputs with interrupt handlers  **********************/
-/* TODO: Redefine debug 2 inputs */
-GPIO_INT(RECOVERY_L,       PIN(0, 0), GPIO_PULL_UP   | GPIO_INT_BOTH, switch_interrupt)       /* Recovery signal from servo */
-GPIO_INT(WP_L,             PIN(9, 3), GPIO_PULL_UP   | GPIO_INT_BOTH, switch_interrupt)       /* Write protect input */
-
-/* For testing keyboard commands, we need the following 4 GPIOs */
-/* TODO: Redefine 4 inputs */
-GPIO_INT(POWER_BUTTON_L,   PIN(0, 2), GPIO_PULL_UP   | GPIO_INT_BOTH, power_button_interrupt) /* Power button */
-GPIO_INT(LID_OPEN,         PIN(3, 3), GPIO_PULL_DOWN | GPIO_INT_BOTH, lid_interrupt)          /* Lid switch */
-
-/**************************** Need a empty line between GPIO_INT and GPIO ****************************/
-#ifdef CONFIG_TEST_1P8V
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_ODR_LOW | GPIO_SEL_1P8V)                    /* Indicate when EC is entering RW code */
-#else
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_OUT_LOW )                                   /* Indicate when EC is entering RW code */
-#endif
-GPIO(PCH_WAKE_L,           PIN(5, 0), GPIO_OUT_HIGH)                                   /* Wake signal output to PCH */
-
-/* Used for module testing */
-GPIO(PGOOD_FAN,            PIN(C, 7), GPIO_PULL_UP	| GPIO_INPUT)                  /* Power Good for FAN test */
-GPIO(SPI_CS_L,             PIN(A, 5), GPIO_OUT_HIGH)                                   /* SPI_CS Ready, Low Active. */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-#ifdef CONFIG_TEST_1P8V
-GPIO(I2C0_SCL0,     PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(I2C0_SDA0,     PIN(B, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-#else
-GPIO(I2C0_SCL0,     PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA0,     PIN(B, 4), GPIO_ODR_HIGH)
-#endif
-GPIO(I2C0_SCL1,     PIN(B, 3), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA1,     PIN(B, 2), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL,      PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA,      PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL,      PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA,      PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL,      PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,      PIN(D, 0), GPIO_ODR_HIGH)
-
-/* Used for board version command */
-GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)    /* Board version stuffing resistor 1 */
-GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)    /* Board version stuffing resistor 2 */
-GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)    /* Board version stuffing resistor 3 */
-
-/**************************** Alternate pins for UART/I2C/ADC/SPI/PWM/MFT ****************************/
-/* Alternate pins for UART/I2C/ADC/SPI/PWM/MFT */
-#if NPCX_UART_MODULE2
-ALTERNATE(PIN_MASK(6, 0x30), 1,  MODULE_UART,        0)    /* CR_SIN/SOUT             GPIO64/65    */
-#else
-ALTERNATE(PIN_MASK(1, 0x03), 1,  MODULE_UART,        0)    /* CR_SIN/SOUT             GPIO10/11    */
-#endif
-ALTERNATE(PIN_MASK(B, 0x0C), 1,  MODULE_I2C,         0)    /* I2C0SDA1/I2C0SCL1       GPIOB2/B3	   */
-ALTERNATE(PIN_MASK(B, 0x30), 1,  MODULE_I2C,         0)    /* I2C0SDA0/I2C0SCL0       GPIOB4/B5	   */
-ALTERNATE(PIN_MASK(8, 0x80), 1,  MODULE_I2C,         0)    /* I2C1SDA                 GPIO87       */
-ALTERNATE(PIN_MASK(9, 0x07), 1,  MODULE_I2C,         0)    /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
-ALTERNATE(PIN_MASK(D, 0x03), 1,  MODULE_I2C,         0)    /* I2C3SDA/I2C3SCL         GPIOD0/D1    */
-ALTERNATE(PIN_MASK(4, 0x38), 1,  MODULE_ADC,         0)    /* ADC                     GPIO45/44/43 */
-ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,         0)    /* SPIP_MOSI/SPIP_SCLK     GPIOA3/A1	   */
-ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,         0)    /* SPIP_MISO               GPIO95       */
-ALTERNATE(PIN_MASK(C, 0x04), 1,  MODULE_PWM,         0)    /* PWM1 for PWM/KBLIGHT Test GPIOC2     */
-/* Alternative functionality for FANS */
-#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 1,  MODULE_PWM,         0)    /* PWM0 for PWM/FAN Test GPIOC3 */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 1,  MODULE_PWM,         0)    /* TA1_SL2 GPIO93 for tachometer input */
-#else
-ALTERNATE(PIN_MASK(4, 0x01), 1,  MODULE_PWM,         0)    /* TA1_SL1 GPIO40 for tachometer input */
-#endif /* NPCX_TACH_SEL2 */
-#if (CONFIG_FANS == 2)
-ALTERNATE(PIN_MASK(C, 0x10), 1,  MODULE_PWM,         0)    /* PWM2 for PWM/FAN Test GPIOC4 */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(A, 0x40), 1,  MODULE_PWM,         0)    /* TA2_SL2 GPIOA6 for tachometer input */
-#else
-ALTERNATE(PIN_MASK(7, 0x08), 1,  MODULE_PWM,         0)    /* TA2_SL1 GPIO73 for tachometer input */
-#endif /* NPCX_TACH_SEL2 */
-#endif /* (CONFIG_FANS == 2) */
-#endif /* CONFIG_FANS */
-
-/* Keyboard Columns */
-ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
-
-/* Keyboard Rows */
-ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/board/npcx_evb_arm/board.c b/board/npcx_evb_arm/board.c
deleted file mode 100644
index 4ee03e7a00..0000000000
--- a/board/npcx_evb_arm/board.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* EC for Nuvoton M4 EB configuration */
-
-#include "adc.h"
-#include "backlight.h"
-#include "chipset.h"
-#include "common.h"
-#include "driver/temp_sensor/tmp006.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peci.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "util.h"
-#include "shi_chip.h"
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
-	[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_PGOOD_FAN,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 5200,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master0-0", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
-	{"master0-1", NPCX_I2C_PORT0_1, 100, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
-	{"master1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"master2",   NPCX_I2C_PORT2,   100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"master3",   NPCX_I2C_PORT3,   100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = 40,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
-	},
-};
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h
deleted file mode 100644
index c3fd341365..0000000000
--- a/board/npcx_evb_arm/board.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Nuvoton M4 EB */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional modules */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_HOSTCMD_SHI /* Used in ARM-based platform for host interface */
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-#define CONFIG_FLASH_SIZE_BYTES          0x00800000 /* 8MB spi flash */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q64
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_VBOOT_HASH
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_BOARD_VERSION_GPIO
-#define CONFIG_ENABLE_JTAG_SELECTION
-
-/* Optional features for test commands */
-#define CONFIG_CMD_TASKREADY
-#define CONFIG_CMD_STACKOVERFLOW
-#define CONFIG_CMD_JUMPTAGS
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SPI_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_I2CWEDGE
-
-#define CONFIG_UART_HOST                0
-#define CONFIG_FANS                     1
-
-/* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-/* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */
-#define NPCX_SHI_CS_PU
-/* Enable bypass since shi outputs invalid data when across 256B boundary */
-#define NPCX_SHI_BYPASS_OVER_256B
-
-/* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
-
-/* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT
-};
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/npcx_evb_arm/build.mk b/board/npcx_evb_arm/build.mk
deleted file mode 100644
index 48116c5454..0000000000
--- a/board/npcx_evb_arm/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-# the IC is Nuvoton NPCX5 M-Series EC (npcx5m5g, npcx5m6g)
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx5
-CHIP_VARIANT:=npcx5m5g
-
-board-y=board.o
diff --git a/board/npcx_evb_arm/ec.tasklist b/board/npcx_evb_arm/ec.tasklist
deleted file mode 100644
index a014b86350..0000000000
--- a/board/npcx_evb_arm/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/npcx_evb_arm/gpio.inc b/board/npcx_evb_arm/gpio.inc
deleted file mode 100644
index 1cdda98300..0000000000
--- a/board/npcx_evb_arm/gpio.inc
+++ /dev/null
@@ -1,92 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/********************** Inputs with interrupt handlers  **********************/
-/* TODO: Redefine debug 2 inputs */
-GPIO_INT(RECOVERY_L,       PIN(0, 0), GPIO_PULL_UP   | GPIO_INT_BOTH, switch_interrupt)       /* Recovery signal from servo */
-GPIO_INT(WP_L,             PIN(9, 3), GPIO_PULL_UP   | GPIO_INT_BOTH, switch_interrupt)       /* Write protect input */
-/* Used for ARM based platform */
-GPIO_INT(SHI_CS_L,         PIN(5, 3), GPIO_INT_FALLING,shi_cs_event)                          /* SHI CS Ready, Low Active. */
-/* For testing keyboard commands, we need the following 4 GPIOs */
-/* TODO: Redefine 4 inputs */
-GPIO_INT(POWER_BUTTON_L,   PIN(0, 2), GPIO_PULL_UP   | GPIO_INT_BOTH, power_button_interrupt) /* Power button */
-GPIO_INT(LID_OPEN,         PIN(3, 3), GPIO_PULL_DOWN | GPIO_INT_BOTH, lid_interrupt)          /* Lid switch */
-
-/**************************** Need a empty line between GPIO_INT and GPIO ****************************/
-#ifdef CONFIG_TEST_1P8V
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_ODR_LOW | GPIO_SEL_1P8V)                    /* Indicate when EC is entering RW code */
-#else
-GPIO(ENTERING_RW,          PIN(3, 6), GPIO_OUT_LOW )                                   /* Indicate when EC is entering RW code */
-#endif
-GPIO(PCH_WAKE_L,           PIN(5, 0), GPIO_OUT_HIGH)                /* Wake signal output to PCH */
-/* For testing keyboard mkbp */
-GPIO(EC_INT_L,             PIN(7, 4), GPIO_ODR_HIGH)                /* Interrupt pin for keyboard mkbp */
-/* Used for module testing */
-GPIO(PGOOD_FAN,            PIN(C, 7), GPIO_PULL_UP   | GPIO_INPUT)  /* Power Good for FAN test */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-#ifdef CONFIG_TEST_1P8V
-GPIO(I2C0_SCL0,     PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(I2C0_SDA0,     PIN(B, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-#else
-GPIO(I2C0_SCL0,     PIN(B, 5), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA0,     PIN(B, 4), GPIO_ODR_HIGH)
-#endif
-GPIO(I2C0_SCL1,     PIN(B, 3), GPIO_ODR_HIGH)
-GPIO(I2C0_SDA1,     PIN(B, 2), GPIO_ODR_HIGH)
-GPIO(I2C1_SCL,      PIN(9, 0), GPIO_ODR_HIGH)
-GPIO(I2C1_SDA,      PIN(8, 7), GPIO_ODR_HIGH)
-GPIO(I2C2_SCL,      PIN(9, 2), GPIO_ODR_HIGH)
-GPIO(I2C2_SDA,      PIN(9, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SCL,      PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,      PIN(D, 0), GPIO_ODR_HIGH)
-
-/* Used for board version command */
-GPIO(BOARD_VERSION1,       PIN(6, 4), GPIO_INPUT)    /* Board version stuffing resistor 1 */
-GPIO(BOARD_VERSION2,       PIN(6, 5), GPIO_INPUT)    /* Board version stuffing resistor 2 */
-GPIO(BOARD_VERSION3,       PIN(6, 6), GPIO_INPUT)    /* Board version stuffing resistor 3 */
-
-/**************************** Alternate pins for UART/I2C/ADC/SPI/PWM/MFT ****************************/
-/* Alternate pins for UART/I2C/ADC/SPI/PWM/MFT */
-#if NPCX_UART_MODULE2
-ALTERNATE(PIN_MASK(6, 0x30), 1,  MODULE_UART,        0)    /* CR_SIN/SOUT             GPIO64/65    */
-#else
-ALTERNATE(PIN_MASK(1, 0x03), 1,  MODULE_UART,        0)    /* CR_SIN/SOUT             GPIO10/11    */
-#endif
-ALTERNATE(PIN_MASK(B, 0x0C), 1,  MODULE_I2C,         0)    /* I2C0SDA1/I2C0SCL1       GPIOB2/B3	   */
-ALTERNATE(PIN_MASK(B, 0x30), 1,  MODULE_I2C,         0)    /* I2C0SDA0/I2C0SCL0       GPIOB4/B5	   */
-ALTERNATE(PIN_MASK(8, 0x80), 1,  MODULE_I2C,         0)    /* I2C1SDA                 GPIO87       */
-ALTERNATE(PIN_MASK(9, 0x07), 1,  MODULE_I2C,         0)    /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
-ALTERNATE(PIN_MASK(D, 0x03), 1,  MODULE_I2C,         0)    /* I2C3SDA/I2C3SCL         GPIOD0/D1    */
-ALTERNATE(PIN_MASK(4, 0x38), 1,  MODULE_ADC,         0)    /* ADC                     GPIO45/44/43 */
-ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,         0)    /* SPIP_MOSI/SPIP_SCLK     GPIOA3/A1	   */
-ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,         0)    /* SPIP_MISO               GPIO95       */
-ALTERNATE(PIN_MASK(C, 0x04), 1,  MODULE_PWM,         0)    /* PWM1 for PWM/KBLIGHT Test GPIOC2     */
-/* Alternative functionality for FANS */
-#ifdef CONFIG_FANS
-ALTERNATE(PIN_MASK(C, 0x08), 1,  MODULE_PWM,         0)    /* PWM0 for PWM/FAN Test   GPIOC3       */
-#if NPCX_TACH_SEL2
-ALTERNATE(PIN_MASK(9, 0x08), 1,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN GPIO93       */
-#else
-ALTERNATE(PIN_MASK(4, 0x01), 1,  MODULE_PWM,         0)    /* MFT-1/TA1_TACH1 for FAN Test GPIO40  */
-#endif
-#endif
-
-/* Keyboard Columns */
-ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
-
-/* Keyboard Rows */
-ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
-ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/board/nucleo-dartmonkey/board.c b/board/nucleo-dartmonkey/board.c
deleted file mode 100644
index a7851ec00b..0000000000
--- a/board/nucleo-dartmonkey/board.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor_detect.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-static void ap_deferred(void)
-{
-	/*
-	 * Behavior:
-	 * AP Active  (ex. Intel S0):   SLP_L is 1
-	 * AP Suspend (ex. Intel S0ix): SLP_L is 0
-	 * The alternative SLP_ALT_L should be pulled high at all the times.
-	 *
-	 * Legacy Intel behavior:
-	 * in S3:   SLP_ALT_L is 0 and SLP_L is X.
-	 * in S0ix: SLP_ALT_L is X and SLP_L is 0.
-	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_SLP_ALT_L)
-			&& gpio_get_level(GPIO_SLP_L);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-static void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-#ifndef HAS_TASK_FPSENSOR
-void fps_event(enum gpio_signal signal)
-{
-}
-#endif
-
-#include "gpio_list.h"
-
-/* SPI devices */
-struct spi_device_t spi_devices[] = {
-	/* Fingerprint sensor (SCLK at 4Mhz) */
-	{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_SPI4_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-static void spi_configure(void)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	/* Set all SPI master signal pins to very high speed: pins E2/4/5/6 */
-	STM32_GPIO_OSPEEDR(GPIO_E) |= 0x00003f30;
-	/* Enable clocks to SPI4 module (master) */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI4;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	spi_configure();
-
-	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
-
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_SLP_ALT_L);
-	gpio_enable_interrupt(GPIO_SLP_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-dartmonkey/board.h b/board/nucleo-dartmonkey/board.h
deleted file mode 100644
index 9e220db7dc..0000000000
--- a/board/nucleo-dartmonkey/board.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * STM32H743 + FPC 1145 Fingerprint MCU configuration
- *
- * This board is designed to have nucleo-h743zi support (uart+btn+leds) with
- * dartmonkey configuration (fingerprint support).
- * This allows for proxy testing of dartmonkey on the Nucleo-H743ZI.
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* Baseboard features */
-#include "base-board.h"
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/* Fingerprint needs to store a secrect in the anti-rollback block */
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-
-/* SPI configuration for the fingerprint sensor */
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
-
-#define CONFIG_FINGERPRINT_MCU
-
-#ifdef SECTION_IS_RW
-	/* Select fingerprint sensor */
-#	define CONFIG_FP_SENSOR_FPC1145
-#	define CONFIG_CMD_FPSENSOR_DEBUG
-	/* Special memory regions to store large arrays */
-#	define FP_FRAME_SECTION    __SECTION(ahb4)
-#	define FP_TEMPLATE_SECTION __SECTION(ahb)
-	/*
-	 * Use the malloc code only in the RW section (for the private library),
-	 * we cannot enable it in RO since it is not compatible with the RW
-	 * verification (shared_mem_init done too late).
-	 */
-#	define CONFIG_MALLOC
-#endif /* SECTION_IS_RW */
-
-#ifndef __ASSEMBLER__
-	void fps_event(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __BOARD_H */
diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk
deleted file mode 100644
index 4bc677e7e0..0000000000
--- a/board/nucleo-dartmonkey/build.mk
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-BASEBOARD:=nucleo-h743zi
-
-board-y=board.o
-board-y+=fpsensor_detect.o
-
-# Enable on device tests
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       fpsensor \
-       fpsensor_hw \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/nucleo-dartmonkey/dev_key.pem b/board/nucleo-dartmonkey/dev_key.pem
deleted file mode 100644
index 5b3a7ab290..0000000000
--- a/board/nucleo-dartmonkey/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAshjw6IqptVQZ/ysb0Z5hwABKpJVjgfezpqcaeXA6Cjy97UMh
-fy7C9lghQDBlE2ykiXrVICTxpKuWdonbvNgBbhCR/VBkvakBYzYdTl94VCeajguu
-39PqBQmROaWmDmaFxxMfC+IV2K8TFP9rPl+g2ILxgZqXhEcZLizpn7oF494xSeLG
-xH2bWkuYVeF/kFkgoTldC2gA3l98cF1mUFQ7kjq1G/VHCKAPjetZWpdUw+5vbZJQ
-/Yk+UtAyHwi+v5MoEnlnEcSJE9YJu4ISxWkl4OWhDElFibDNOs+Zievj4QvKhjO5
-eISyD6HxphGBLm4wfdnCgxLJrDpMWDqy+lRus4JpTt3Cxvm2LhIqZ3X9SWtVgGZ3
-u9W7IEBVsGY3Juxend5q0vgF6KBGgPSScKseq9GazVUbs5g/Bm+NAH+UTNHOJDbf
-VU7WfyCJXY/5vmgQcLyxRi0RKJRLrClGm6uIgTmpo4UKfb8Uo02BE+AIF7f5SdKh
-/w+jsW8/T9gufzZBAgEDAoIBgHa7S0Wxxnjiu/9yEou+69VVhxhjl6v6d8RvZvug
-JrF90/OCFlTJ107la4AgQ2JIbbD8jhVt9m3HuaRb59M6q561tqjgQykbVkIkE4mU
-+uLFEbQHyeqNRq4GYNEZGV7vA9oMv11BY+XKDLiqR37qazsB9lZnD62Eu3Qd8RUm
-rpfpdjFB2dhTvObdEDlA/7WQwGt7k1zwAJQ/qEro7uA4J7bRzhKjhLBqtQlHkOcP
-jdf0SkkMNf5bfuHgIWoF1H+3bu+clx8IpiGvfZGRTmWOErxhYhyUOLdvPIruoCaa
-NRcjxa/KO6PrSQeTpl9/Pf8Wu/2HHmQRTNv2VuCvmtvgd/RQEdXZET2Q28BYJqp5
-U0qB4YC1Y3Ef5aMCPevmxsWC5aoX7vwSlfjF/Ni4jBVV+nVlFFldiTOWQXOWnbhl
-ahIk4+h42X+SRPzTR67JcM1JGrLGSh7P+LLZNGXICXJyKu2y58+ABLfQybdgvBv4
-MpiBt5h09WtFbXKHaw07lYJGywKBwQDWt/nuS551Q8n4wDs30mIKn5OJZgZcM9iS
-MSB4HFLE6tOWbZyIwRWWT2CoK3F50JwSFKZsz24oUe7hULCOBu45s21tjvWk3oiH
-JSWLKPKr8gEwu6PQ3LqOs+qXOH66+7Bq/ozvRmCu/m3OKZQ1oY7bxnonkqNT7qj6
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-Bbq/96wVJBxhhXfqAG/EtwlFVT8hjcOIkc0E2aET5rNrEzyUtvghA1QUuU7y/oNH
-T4rych0oX5oSiDDX/uAKjvQCtaV9RjlVHtu8rHGb2mPw9zMCgcEAkTZ4izUWm58A
-nzEeiqYrqb6Cmdg70YfK/bsW0GNcp+TLdA7ZZ2kg3sFaCTo4s4NZEruDMC0ecLng
-Y7JYGOhhzJRzLDFpW1g2qNWJx+ndmAR36fAbz5m7sEKxIPCKukfxlOOzH56uy8xK
-8L2I+KEHZMOYu8NeebCbLBgWBHzO5fvPXEQyNVSFAvBbbmzLHh4LvhlYg2y/mUB0
-zNpCrc1vaob1YLuaTfusXDm6blWvPr4MVKnn5iChZQBogfBrPCHc
------END RSA PRIVATE KEY-----
diff --git a/board/nucleo-dartmonkey/ec.tasklist b/board/nucleo-dartmonkey/ec.tasklist
deleted file mode 100644
index 80e226637b..0000000000
--- a/board/nucleo-dartmonkey/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #include "base-ec.tasklist"
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST BASEBOARD_CONFIG_TASK_LIST \
-	TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096)
diff --git a/board/nucleo-dartmonkey/fpsensor_detect.c b/board/nucleo-dartmonkey/fpsensor_detect.c
deleted file mode 100644
index 72b9b89e11..0000000000
--- a/board/nucleo-dartmonkey/fpsensor_detect.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fpsensor_detect.h"
-
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	return FP_SENSOR_TYPE_FPC;
-}
-
-enum fp_transport_type get_fp_transport_type(void)
-{
-	return FP_TRANSPORT_TYPE_SPI;
-}
diff --git a/board/nucleo-dartmonkey/gpio.inc b/board/nucleo-dartmonkey/gpio.inc
deleted file mode 100644
index 11709fe738..0000000000
--- a/board/nucleo-dartmonkey/gpio.inc
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Note that these pins map to the Nucleo-H743ZI V2 and are only slightly
- * compatible with the original version.
- *
- * The V2 is denoted by "Nucleo-H743ZI2" vs. "Nucleo-H743ZI".
- */
-
-#include "base-gpio.inc"
-
-/* Interrupts */
-GPIO_INT(SLP_L,           PIN(D, 13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(SLP_ALT_L,       PIN(A, 11), GPIO_INT_BOTH, slp_event)
-
-/* Output for User Presence */
-GPIO(USER_PRES_L,         PIN(C, 5),  GPIO_ODR_HIGH)
-
-/* Fingerprint Sensor */
-GPIO_INT(FPS_INT,         PIN(A, 0),  GPIO_INT_RISING, fps_event)
-GPIO(FP_RST_ODL,          PIN(E, 0),  GPIO_OUT_HIGH)
-GPIO(SPI4_NSS,            PIN(E, 4),  GPIO_OUT_HIGH)
-/* SPI4 master to sensor: PE2/5/6 (CLK/MISO/MOSI) */
-ALTERNATE(PIN_MASK(E, 0x0064), GPIO_ALT_SPI, MODULE_SPI_CONTROLLER,  0)
diff --git a/board/nucleo-dartmonkey/openocd-flash.cfg b/board/nucleo-dartmonkey/openocd-flash.cfg
deleted file mode 120000
index 904ee459ab..0000000000
--- a/board/nucleo-dartmonkey/openocd-flash.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-h743zi/openocd-flash.cfg
\ No newline at end of file
diff --git a/board/nucleo-dartmonkey/openocd.cfg b/board/nucleo-dartmonkey/openocd.cfg
deleted file mode 120000
index b3fc5796c5..0000000000
--- a/board/nucleo-dartmonkey/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-h743zi/openocd.cfg
\ No newline at end of file
diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c
deleted file mode 100644
index 66e8960ce7..0000000000
--- a/board/nucleo-f072rb/board.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "i2c.h"
-#include "timer.h"
-
-void button_event(enum gpio_signal signal)
-{
-	gpio_set_level(GPIO_LED_U, 1);
-}
-
-#ifdef CTS_MODULE
-/*
- * Mock interrupt handler. It's supposed to be overwritten by each suite
- * if needed.
- */
-__attribute__((weak)) void cts_irq1(enum gpio_signal signal) {}
-__attribute__((weak)) void cts_irq2(enum gpio_signal signal) {}
-#endif
-
-#include "gpio_list.h"
-
-void tick_event(void)
-{
-	static int count;
-
-	gpio_set_level(GPIO_LED_U, (count & 0x07) == 0);
-
-	count++;
-}
-DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
-
-#ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{"test", STM32_I2C1_PORT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-#endif
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USER_BUTTON);
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f072rb/board.h b/board/nucleo-f072rb/board.h
deleted file mode 100644
index 0ec675ab61..0000000000
--- a/board/nucleo-f072rb/board.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nucleo-F072RB board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-
-#ifdef CTS_MODULE
-#undef STM32_IRQ_EXT2_3_PRIORITY
-#define STM32_IRQ_EXT2_3_PRIORITY	2
-#ifdef CTS_MODULE_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#endif
-#endif
-
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nucleo-f072rb/build.mk b/board/nucleo-f072rb/build.mk
deleted file mode 100644
index 0e069a31ad..0000000000
--- a/board/nucleo-f072rb/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/nucleo-f072rb/ec.tasklist b/board/nucleo-f072rb/ec.tasklist
deleted file mode 100644
index a6385530b5..0000000000
--- a/board/nucleo-f072rb/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/nucleo-f072rb/gpio.inc b/board/nucleo-f072rb/gpio.inc
deleted file mode 100644
index 6f3b592845..0000000000
--- a/board/nucleo-f072rb/gpio.inc
+++ /dev/null
@@ -1,47 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USER_BUTTON, PIN(C, 13), GPIO_INT_FALLING, button_event)
-#ifdef CTS_MODULE
-#ifndef CTS_MODULE_GPIO
-/* Overload C1 for interrupt. Enabled only for non-GPIO suites as
- * GPIO tests don't require a separate notification line. */
-GPIO_INT(CTS_IRQ1, PIN(C, 1), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq1)
-/* Used to disable interrupt. This IRQ# has to match the number used for the
- * pin set above */
-#define CTS_IRQ_NUMBER STM32_IRQ_EXTI0_1
-#endif
-GPIO_INT(CTS_IRQ2, PIN(C, 2), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq2)
-#endif
-
-/* Outputs */
-GPIO(LED_U, PIN(A, 5), GPIO_OUT_LOW)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x000C), 1, MODULE_UART,  0) /* USART2: PA2/PA3 */
-
-GPIO(I2C1_SCL, PIN(B, 6), GPIO_ODR_HIGH) /* I2C port 1 SCL */
-GPIO(I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH) /* I2C port 1 SDA */
-
-/* I2C1: PB6/7*/
-ALTERNATE(PIN_MASK(B, 0x00C0), GPIO_ALT_F1, MODULE_I2C, GPIO_PULL_UP)
-
-#ifdef CTS_MODULE
-/* CTS Signals */
-GPIO(HANDSHAKE_INPUT, PIN(A, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(HANDSHAKE_OUTPUT, PIN(B, 0), GPIO_ODR_LOW)
-#ifdef CTS_MODULE_GPIO
-GPIO(INPUT_TEST, PIN(C, 1), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-GPIO(OUTPUT_TEST, PIN(C, 0), GPIO_ODR_LOW)
-#endif
diff --git a/board/nucleo-f072rb/openocd-flash.cfg b/board/nucleo-f072rb/openocd-flash.cfg
deleted file mode 100644
index 91e3805c74..0000000000
--- a/board/nucleo-f072rb/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_f0.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/nucleo-f411re/board.c b/board/nucleo-f411re/board.c
deleted file mode 100644
index a177a793ab..0000000000
--- a/board/nucleo-f411re/board.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* nucleo-f411re development board configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "motion_sense.h"
-
-#include "gpio.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void user_button_evt(enum gpio_signal signal)
-{
-	ccprintf("Button %d, %d!\n", signal, gpio_get_level(signal));
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USER_BUTTON_L);
-
-	/* No power control yet */
-	/* Go to S3 state */
-	hook_notify(HOOK_CHIPSET_STARTUP);
-
-	/* Go to S0 state */
-	hook_notify(HOOK_CHIPSET_RESUME);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Arduino connectors analog pins */
-	[ADC1_0] = {"ADC1_0",  3000, 4096, 0, STM32_AIN(0)},
-	[ADC1_1] = {"ADC1_1",  3000, 4096, 0, STM32_AIN(1)},
-	[ADC1_4] = {"ADC1_4",  3000, 4096, 0, STM32_AIN(4)},
-	[ADC1_8] = {"ADC1_8",  3000, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-	 GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#ifdef CONFIG_DMA_HELP
-#include "dma.h"
-int command_dma_help(int argc, char **argv)
-{
-	dma_dump(STM32_DMA2_STREAM0);
-	dma_test(STM32_DMA2_STREAM0);
-	dma_dump(STM32_DMA2_STREAM0);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help,
-			NULL, "Run DMA test");
-#endif
diff --git a/board/nucleo-f411re/board.h b/board/nucleo-f411re/board.h
deleted file mode 100644
index 56d2ad41d0..0000000000
--- a/board/nucleo-f411re/board.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nucleo-F411RE development board configuration */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* 84 MHz CPU/AHB/APB2 clock frequency (APB1 = 42 Mhz) */
-#define CPU_CLOCK 84000000
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-
-/* the UART console is on USART2 (PA2/PA3) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_HIBERNATE
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_TASK_PROFILING
-
-#undef CONFIG_ADC
-#define CONFIG_DMA_HELP
-#define CONFIG_I2C
-
-#undef CONFIG_UART_RX_DMA
-#define CONFIG_UART_TX_DMA_CH STM32_DMAS_USART2_TX
-#define CONFIG_UART_RX_DMA_CH STM32_DMAS_USART2_RX
-#define CONFIG_UART_TX_REQ_CH STM32_REQ_USART2_TX
-#define CONFIG_UART_RX_REQ_CH STM32_REQ_USART2_RX
-
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_FLASH
-
-/* I2C ports configuration */
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_DEBUG
-#define I2C_PORT_MASTER 1
-#define I2C_PORT_SLAVE 0        /* needed for DMAC macros (ugh) */
-#define I2C_PORT_ACCEL I2C_PORT_MASTER
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 11
-
-#define CONFIG_WP_ALWAYS
-#define CONFIG_FLASH_READOUT_PROTECTION
-
-/* ADC signal */
-enum adc_channel {
-	ADC1_0 = 0,
-	ADC1_1,
-	ADC1_4,
-	ADC1_8,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	BASE_ACCEL = 0,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __BOARD_H */
diff --git a/board/nucleo-f411re/build.mk b/board/nucleo-f411re/build.mk
deleted file mode 100644
index 3a5fc28558..0000000000
--- a/board/nucleo-f411re/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F411RE
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f411
-
-board-y=board.o
diff --git a/board/nucleo-f411re/ec.tasklist b/board/nucleo-f411re/ec.tasklist
deleted file mode 100644
index b5e3cb82b2..0000000000
--- a/board/nucleo-f411re/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/nucleo-f411re/gpio.inc b/board/nucleo-f411re/gpio.inc
deleted file mode 100644
index 83a9e51a08..0000000000
--- a/board/nucleo-f411re/gpio.inc
+++ /dev/null
@@ -1,31 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupts */
-GPIO_INT(USER_BUTTON_L,   PIN(C, 13), GPIO_INT_BOTH, user_button_evt)
-
-/* User LED */
-GPIO(USER_LED,            PIN(A,  5), GPIO_OUT_LOW)
-
-GPIO(BMI160_INT2_L,       PIN(C, 10), GPIO_OUT_LOW)
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(MASTER_I2C_SCL,      PIN(B, 10), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,      PIN(B,  3), GPIO_INPUT)
-GPIO(SLAVE_I2C_SCL,       PIN(B,  8), GPIO_INPUT)
-GPIO(SLAVE_I2C_SDA,       PIN(B,  9), GPIO_INPUT)
-
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP) /* USART2: PA2/PA3 */
-ALTERNATE(PIN_MASK(B, 0x0400), GPIO_ALT_I2C,    MODULE_I2C,  0) /* I2C MASTER:PB10 */
-ALTERNATE(PIN_MASK(B, 0x0008), GPIO_ALT_I2C_23, MODULE_I2C,  0) /* I2C MASTER:PB3 */
-ALTERNATE(PIN_MASK(B, 0x0200), GPIO_ALT_I2C,    MODULE_I2C,  0) /* I2C SLAVE:PB9 */
-ALTERNATE(PIN_MASK(B, 0x0100), GPIO_ALT_I2C,    MODULE_I2C,  0) /* I2C SLAVE:PB8 */
diff --git a/board/nucleo-f411re/openocd-flash.cfg b/board/nucleo-f411re/openocd-flash.cfg
deleted file mode 100644
index 7a6ea6316c..0000000000
--- a/board/nucleo-f411re/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/st_nucleo_f4.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase unlock $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/nucleo-f412zg/README.md b/board/nucleo-f412zg/README.md
deleted file mode 100644
index f2fa682e6f..0000000000
--- a/board/nucleo-f412zg/README.md
+++ /dev/null
@@ -1,83 +0,0 @@
-# Nucleo F412ZG
-
-This is a simpler EC example for the ST Nucleo F412ZG development board.
-
-# Quick Start
-
-The Nucleo dev boards have lots of developer friendly features, like an
-in-circuit debugger/programmer/UART-bridge, programmable LEDs, and a button, to
-name a few.
-
-The built-in debugger can be connected to using a Micro USB cable. It provides
-three great interfaces to the host. 1. Mass storage interface for drag-drop
-programming 2. Full ST-Link in-circuit debugger 3. UART bridge for logs/consoles
-
-We will use a few of these interfaces below to program and interact with out
-Nucleo dev board.
-
-## Build
-
-```bash
-make BOARD=nucleo-f412zg -j
-```
-
-## Program
-
-The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop the
-firmware image onto the exposed mass storage drive.
-
-Open a file browser and `Copy` the file in `build/nucleo-f412zg/ec.bin`. Now,
-find the removable storage that the Nucleo device has presented, and `Paste` the
-file into the directory.
-
-## Interact
-
-After the Nucleo finishes programming, you can open the EC console. On
-GNU/Linux, this is mapped to `/dev/ttyACM0`.
-
-Install `minicom` and issue the following command:
-
-```bash
-minicom -D/dev/ttyACM0
-```
-
-# Unit Testing
-
-A fun EC feature is that unit tests can be run on-device.
-
-This is made possible by an alternative build rule that generates a test image
-per unit test. These test images use a unit test specific taskset and console
-command to trigger them.
-
-## Create
-
-To enable an existing unit test, add it to the [build.mk](build.mk)'s
-`test-list-y` variable.
-
-See the main [README.md](/README.md) on how to write a new unit test.
-
-## Build
-
-To build all unit test images for this board, run the following command:
-
-```bash
-make BOARD=nucleo-f412zg tests
-```
-
-You can build a specific unit test image by changing `tests` to `test-aes`, for
-the `aes` unit test.
-
-## Flash
-
-Copy/paste the `build/nucleo-f412zg/${TEST}/${TEST}.bin` file to the Nucleo's
-mass storage drive, where `${TEST}` is the name of the unit test, like `aes`.
-
-## Run
-
-1.  Connect to UART console
-
-```bash
-minicom -D/dev/ttyACM0
-```
-
-1.  Run the `runtest` command
diff --git a/board/nucleo-f412zg/board.c b/board/nucleo-f412zg/board.c
deleted file mode 100644
index 4324101da9..0000000000
--- a/board/nucleo-f412zg/board.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-static void ap_deferred(void)
-{
-	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-static void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f412zg/board.h b/board/nucleo-f412zg/board.h
deleted file mode 100644
index f6e1368847..0000000000
--- a/board/nucleo-f412zg/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32F412 */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* Baseboard features */
-#include "base-board.h"
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/*
- * Enable the blink example that exercises the LEDs.
- */
-#define CONFIG_BLINK
-#define CONFIG_BLINK_LEDS    GPIO_LED1, GPIO_LED2, GPIO_LED3
-
-#endif /* __BOARD_H */
diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk
deleted file mode 100644
index 6d46b6c289..0000000000
--- a/board/nucleo-f412zg/build.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-BASEBOARD:=nucleo-f412zg
-
-board-y=board.o
-
-# Enable on device tests
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       stm32f_rtc \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/nucleo-f412zg/dev_key.pem b/board/nucleo-f412zg/dev_key.pem
deleted file mode 100644
index 1eb0d88b78..0000000000
--- a/board/nucleo-f412zg/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAwLY2WYJasnLc/5iNin8L7Sxv/JkAwGWwEc3gJDMbHwgDYmm0
-V0pA1yKIKdcMsCLEh8VmI9JClgOdn9G9H0UXjtfWmszF8a9TtnrDcSJFBV/cxNs5
-CwxhQrcHmjSqpvhiDBFNyPEECPzg/s+Us7HHw9LaR61TBCY8/KDSHZoULx5m2n74
-xW5cJsxCmK/q8vQXYy+dhJzsCkgYOmubFyuHYn2CoNPBGaBLCiysD3ZbyxcJ+gl4
-NFN6MvD/fK0AufailWIskGJvDQmsJn+KBdNERaU31rHf6xqsq8wviYvSDtZk/QaI
-r9rWf7o48mQhDgB3o/3GEpL1ptWetmT1ZquqisCH0vh180jPDCmJl6t9xR2piJr8
-Hudq4STiE1++olFmwx/T6GCfy2fYMH8UD9ZrWvmD46V/2HGOJYfyWig0VyHN+QPr
-ZKtCbjgCyJCzxRQ8NTdmHyqyguwEcsHB20gpOVLknA3QB8VFIWzz4ZdNqksP6nxB
-PDZVKrIQNmUEkJZnAgEDAoIBgQCAeXmRAZHMTJNVEF5cVLKeHZ/9u1XVmSAL3pVt
-d2dqBVeW8SLk3Cs6FwVxOgh1bIMFLkQX4YG5V75qi9NqLg+0j+RnMy6hH40kUdeg
-wYNY6pMt53tcsuuBz1pmzccZ+uwIC4kwoK1bU0Cp37h3y9qCjJGFHjdYGX39wIwT
-vA10vu88VKXY9D1vMtcQdUdMorpCH75YaJ1cMBAm8mdkx6+W/lcV4oC7wDIGyHK0
-+ZKHZLFRW6V4N6bMoKpTHgB7+cCQfQaycUvp0eFq2Y1FMiFGcJmg1VXxn0DVtMfp
-6EMZSb6vEsFt5xR7twVKgdKVWMErchvkFR0G1r4p2c83MknQgml34TfmDRIhO9O6
-Vz914sZPK4DiGejYQlyGxm2bcKd9OpBFRZKAdEKYyPbJPTxjwY1ZcmiMaWju3YGa
-MLuT+ixkoV+aeusm/oEfha9h0HF7CuCplFo2onP7L/9myyAkC6GsAyeZICMZV5yn
-xNXR4UHDyMI6TWoo1ui8RY8Fg8sCgcEA6AqRnCJhc1WZL9O+JxmzYVok0sgvzqRw
-N6ZhDMC4vaIVHxzPsVBRXgqA+67mA8d7afNzN6uzO+gnkkKwrdPDpUeLcs1M72wK
-mps1iRFl7jKV/QVlUOTbd1bh0DTWkF3QCOinloueLqh7DAZ8Yewjw+Svg8esQVD6
-6g68PlegGnCLMTPN29G2al+4ucNJ8PflulOdzzodU4dZf/8EnUsXxGaluJrv0vz2
-oRCsClqXeJ0yu1Vuh2/fcSCPz3hjTi9PAoHBANScEOiWG7r5QNZld/buXvqiLJKp
-rzIHWzOWop3utKtFsddNltmv5mgdMAbyfyoz2njfKQTHluCrWeVbjeYMeCy1XixZ
-VSrJKT+0lncXOKYW6hTUVXrbsiVqdXkBQ6jKm35fU+nspdwQ+T9LJYAObQFygFmy
-NsSCddUs87SHet66ADDeDiEhK0laiF+E4sFjrEJTd1GSDd1w/Pn6viPMYT7azGFu
-JM8YGdpY3NuVdXbb+ol5r11SVnxPI0yESrohaQKBwQCasbZoFuuiORDKjSlvZneW
-PBiMhXU0baAlGZYIgHspFri/aIp2NYuUBwCnye6tL6eb96IlHSIn8BphgcsejS0Y
-2lz3M4ifnVxnEiOwtkP0IblTWO417eek5JaKzeRgPoqwmxpkXRQfGvyyrv2WnW0t
-Qx+tL8gri1HxXygpj8ARoFzLd96Si87xlSXRLNv1+pkm4mk00WjiWjuqqgMTh2Ut
-mcPQZ0qMqKRrYHKxkbpQaMx8458E9T+gwF/fpZeJdN8CgcEAjb1gmw69J1DV5EOl
-T0mUpxbIYcZ0zATnd7nBvp8jHNkhOjO55nVERWjKr0xUxs08UJTGAy+56xzmmOez
-7rL6yHjpcuY4xzDGKnhkT2TQbrnxYzg4/JJ2w5xOUKuCcIcSVD+NRp3D6AtQ1NzD
-qrRIq6Gq5nbPLaxOjh33za+nPyaqyz60FhYc25GwP63sgO0dgYz6NmFek6Copqcp
-bTLrfzyIQPQYihARPDs957j4+ef8W6Z06OGO/YoXiFgx0WubAoHAYEw+laK7DHcu
-83aIYtzAMqo15axtIyxfb0RTAKqzBrtlhNO/7TfHTrSuGpIj9DWXbPj8X8UZZkZH
-O8w5NIrQB6fo5OmS1NnZCWDYEd7yGO/8vARvDLriVZ1lykIrP3ZkCEuRo+mVMtcP
-9J3otNKcnnyAlTqZnHgqlW0upMQXiHCWKHHqXUTG0KsGFu6qHPQBqwQ/k5qD+Osv
-tJS8v/ziA33WUHm2OyFgsLNW1tBjkLCDiYJD24/B+3Rc5/fic31r
------END RSA PRIVATE KEY-----
diff --git a/board/nucleo-f412zg/ec.tasklist b/board/nucleo-f412zg/ec.tasklist
deleted file mode 100644
index 896eb2fdb3..0000000000
--- a/board/nucleo-f412zg/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/nucleo-f412zg/gpio.inc b/board/nucleo-f412zg/gpio.inc
deleted file mode 100644
index 57f78203ba..0000000000
--- a/board/nucleo-f412zg/gpio.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "base-gpio.inc"
-
-/* Interrupts */
-GPIO_INT(PCH_SLP_S0_L,    PIN(A, 8), GPIO_INT_BOTH, slp_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(B, 6), GPIO_INT_BOTH, slp_event)
diff --git a/board/nucleo-f412zg/openocd-flash.cfg b/board/nucleo-f412zg/openocd-flash.cfg
deleted file mode 120000
index bafbe75704..0000000000
--- a/board/nucleo-f412zg/openocd-flash.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-f412zg/openocd-flash.cfg
\ No newline at end of file
diff --git a/board/nucleo-f412zg/openocd.cfg b/board/nucleo-f412zg/openocd.cfg
deleted file mode 120000
index 29e0be4ba2..0000000000
--- a/board/nucleo-f412zg/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-f412zg/openocd.cfg
\ No newline at end of file
diff --git a/board/nucleo-g431rb/board.c b/board/nucleo-g431rb/board.c
deleted file mode 100644
index 01f8a55629..0000000000
--- a/board/nucleo-g431rb/board.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32G431 Nucleo-64 board-specific configuration */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-
-static void board_init(void)
-{
-	/*
-	 * Using alt-function to send system clock to MCO pin (PA8). The alt
-	 * function for module clock will not get configured unless the module
-	 * is configured here.
-	 */
-	gpio_config_module(MODULE_CLOCK, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void led_second(void)
-{
-	static int count;
-
-	/* Blink user LED on nucleo board */
-	gpio_set_level(GPIO_LED1, count++ & 0x1);
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
diff --git a/board/nucleo-g431rb/board.h b/board/nucleo-g431rb/board.h
deleted file mode 100644
index a65daa4364..0000000000
--- a/board/nucleo-g431rb/board.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32G431 Nucleo-64 board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CPU_CLOCK 48000000
-#define CONFIG_STM_HWTIMER32
-#define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
-#define TIM_CLOCK_LSB 15
-#define TIM_WATCHDOG 7
-
-/* Nucelo platform does not have a lid switch */
-#undef CONFIG_LID_SWITCH
-
-
-/* Setup UART console */
-/*
- * The STM32G431 Nucleo-64 has two UARTs which can be connected to the virtual
- * com port(VCP) of the STLINK chip. The VCP to STM32G4 connection depends on
- * solder bridge configuration. The default configuration is VCP to LUPAURT
- * (PA2/PA3). In order to reuse existing stm32 uart drivers, UART9 is used to
- * indicate that lpuart is being used.
- *
- * The STM32G4 has a DMAMUX and so both the DMA channel and DMAMUX request
- * numbers need to be specified here.
- */
-#define STM32G431_EVAL_USE_LPUART_CONSOLE
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_TX_DMA
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-#ifdef STM32G431_EVAL_USE_LPUART_CONSOLE
-#define CONFIG_UART_CONSOLE 9
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_LPUART_TX
-#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_UART9_TX
-#else
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
-#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART1_TX
-#endif
-
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nucleo-g431rb/build.mk b/board/nucleo-g431rb/build.mk
deleted file mode 100644
index 8140048cdd..0000000000
--- a/board/nucleo-g431rb/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g431xb
-
-board-y=board.o
diff --git a/board/nucleo-g431rb/ec.tasklist b/board/nucleo-g431rb/ec.tasklist
deleted file mode 100644
index c272906fc7..0000000000
--- a/board/nucleo-g431rb/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/nucleo-g431rb/gpio.inc b/board/nucleo-g431rb/gpio.inc
deleted file mode 100644
index 4dd4a6d966..0000000000
--- a/board/nucleo-g431rb/gpio.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Outputs */
-GPIO(LED1,                     PIN(A, 5),  GPIO_OUT_LOW) /* Green */
-
-/* Misc Signals */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(EC_WP_L)
-
-/* LPUART1: A2/A3 */
-ALTERNATE(PIN_MASK(A, 0x000C), GPIO_ALT_LPUART,  MODULE_UART, GPIO_PULL_UP)
-/* MCO A8 */
-ALTERNATE(PIN_MASK(A, 0x0100), 0,  MODULE_CLOCK, 0)
diff --git a/board/nucleo-h743zi/README.md b/board/nucleo-h743zi/README.md
deleted file mode 100644
index 7ba8a143a3..0000000000
--- a/board/nucleo-h743zi/README.md
+++ /dev/null
@@ -1,83 +0,0 @@
-# Nucleo H743ZI
-
-This is a simpler EC example for the ST Nucleo H743ZI development board.
-
-# Quick Start
-
-The Nucleo dev boards have lots of developer friendly features, like an
-in-circuit debugger/programmer/UART-bridge, programmable LEDs, and a button, to
-name a few.
-
-The built-in debugger can be connected to using a Micro USB cable. It provides
-three great interfaces to the host. 1. Mass storage interface for drag-drop
-programming 2. Full ST-Link in-circuit debugger 3. UART bridge for logs/consoles
-
-We will use a few of these interfaces below to program and interact with out
-Nucleo dev board.
-
-## Build
-
-```bash
-make BOARD=nucleo-h743zi -j
-```
-
-## Program
-
-The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop the
-firmware image onto the exposed mass storage drive.
-
-Open a file browser and `Copy` the file in `build/nucleo-h743zi/ec.bin`. Now,
-find the removable storage that the Nucleo device has presented, and `Paste` the
-file into the directory.
-
-## Interact
-
-After the Nucleo finishes programming, you can open the EC console. On
-GNU/Linux, this is mapped to `/dev/ttyACM0`.
-
-Install `minicom` and issue the following command:
-
-```bash
-minicom -D/dev/ttyACM0
-```
-
-# Unit Testing
-
-A fun EC feature is that unit tests can be run on-device.
-
-This is made possible by an alternative build rule that generates a test image
-per unit test. These test images use a unit test specific taskset and console
-command to trigger them.
-
-## Create
-
-To enable an existing unit test, add it to the [build.mk](build.mk)'s
-`test-list-y` variable.
-
-See the main [README.md](/README.md) on how to write a new unit test.
-
-## Build
-
-To build all unit test images for this board, run the following command:
-
-```bash
-make BOARD=nucleo-h743zi tests
-```
-
-You can build a specific unit test image by changing `tests` to `test-aes`, for
-the `aes` unit test.
-
-## Flash
-
-Copy/paste the `build/nucleo-h743zi/${TEST}/${TEST}.bin` file to the Nucleo's
-mass storage drive, where `${TEST}` is the name of the unit test, like `aes`.
-
-## Run
-
-1.  Connect to UART console
-
-```bash
-minicom -D/dev/ttyACM0
-```
-
-1.  Run the `runtest` command
diff --git a/board/nucleo-h743zi/board.c b/board/nucleo-h743zi/board.c
deleted file mode 100644
index f1493658aa..0000000000
--- a/board/nucleo-h743zi/board.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/**
- * Disable restricted commands when the system is locked.
- *
- * @see console.h system.c
- */
-int console_is_restricted(void)
-{
-	return system_is_locked();
-}
-
-static void ap_deferred(void)
-{
-	/*
-	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
-	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
-	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
-	 * in S5/G3, the FP MCU should not be running.
-	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
-
-	if (running) { /* S0 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		hook_notify(HOOK_CHIPSET_RESUME);
-	} else { /* S0ix/S3 */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-DECLARE_DEFERRED(ap_deferred);
-
-/* PCH power state changes */
-static void slp_event(enum gpio_signal signal)
-{
-	hook_call_deferred(&ap_deferred_data, 0);
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable interrupt on PCH power signals */
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
-
-	/*
-	 * Enable the SPI slave interface if the PCH is up.
-	 * Do not use hook_call_deferred(), because ap_deferred() will be
-	 * called after tasks with priority higher than HOOK task (very late).
-	 */
-	ap_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-h743zi/board.h b/board/nucleo-h743zi/board.h
deleted file mode 100644
index 966f2a8c94..0000000000
--- a/board/nucleo-h743zi/board.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * STM32H743 MCU configuration
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* Baseboard features */
-#include "base-board.h"
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-/*
- * These allow console commands to be flagged as restricted.
- * Restricted commands will only be permitted to run when
- * console_is_restricted() returns false.
- * See console_is_restricted's definition in board.c.
- */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-
-/*
- * Enable the blink example that exercises the LEDs.
- */
-#define CONFIG_BLINK
-#define CONFIG_BLINK_LEDS    GPIO_LED1, GPIO_LED2, GPIO_LED3
-
-#endif /* __BOARD_H */
diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk
deleted file mode 100644
index 1230d9b334..0000000000
--- a/board/nucleo-h743zi/build.mk
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-BASEBOARD:=nucleo-h743zi
-
-board-y=board.o
-
-# Enable on device tests
-test-list-y=\
-       aes \
-       cec \
-       compile_time_macros \
-       crc \
-       flash_physical \
-       flash_write_protect \
-       mpu \
-       mutex \
-       pingpong \
-       printf \
-       queue \
-       rollback \
-       rollback_entropy \
-       rsa3 \
-       rtc \
-       scratchpad \
-       sha256 \
-       sha256_unrolled \
-       static_if \
-       timer_dos \
-       utils \
-       utils_str \
diff --git a/board/nucleo-h743zi/dev_key.pem b/board/nucleo-h743zi/dev_key.pem
deleted file mode 100644
index cb402c9c68..0000000000
--- a/board/nucleo-h743zi/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAnWlGtHyWlAntpuFtoK4ukTuqnvaPiZrr7I8S+9cVpwGJXa7A
-yqK5bp8kmZiUDZEMpFA6+f6OGT8dOS5e07vUcIPaZXc1tbaXADywqI04BdCgPsPP
-pKNnKSUglkkgH2WQ/3aqPrT8IJ17+rCUNLysbvcNy3g0CAj0BGzY/s/2mn50C155
-R+6FsQ47jfBS1vOm3s6bOik73VZMutUyBXu5+Sy6HS0kiuAuL3g9tgslqlVaPWS/
-B6+Pd2ednqTp027z9ZJiY40OdXsTzqoD5iwkkcA391thkfsYASVloLplfFtbymWM
-QaqGyaXeuXmeVXr5NUvpeLwgpA1/spX6BfBhmEK/yJ2FeYaKoBWSLz3UztZMG/FK
-glupYLcV3FTJ6zHzy0LOqsdIZKpQivazHfTD5HsKuokNDZVQjtn+Oga8LWEAA8TQ
-ZB+vEpYxSxi2AHwSjEQaXv8dBgnyTl173qFy4RlZ3d9qpZP3bntVpMGQlIjuYAIM
-cbKoLO69rEED+zr7AgEDAoIBgGjw2c2oZGKxSRnrnmseybYnxxSkX7ER8p20t1KP
-Y8SrsOkfKzHB0PRqGGZluAkLXcLgJ1FUXrt/aNDJlI0n4vWtPEOkznkkZKrTIHBe
-JVk1wCnX38MXmhtuFbmGFWpDtf+kcX8jUsBo/VHLDXh9yEn6CTJQIrAF+ALzO1SK
-pGb++AeUUNqfA8te0l6gNzn3xJSJvNFw0pOO3dHjdq5Se/tzJr4eGFyVdB+lfnlc
-w8bjkX5DKgUftPpFE78Ym+JJ9u1XgVtetZBUAeVl39X+cZZZHXIIu84JtF23qb77
-iHJa85zWKqBXChg3aOReLbbF1tg+HPATDzlXPk0wq9l+HEERkkM7WdsjlBtH/so6
-euQ5mGE8vx/TaggY4gBtVjvsgKe89bzxmIGhLMdKjmwZOYqZKNd4ZujPfj8Mh9cu
-LCsjEwv1WgXBoSI+vDEscV9aSjEU/AkWryc/k/Zo0wfYjRF5+faw9csAl3NSGwOs
-hCiWya8+2z390d+Sc3k3FUH/awKBwQDMq/VieSR08kpSvbakKqxvamrCfeJ0qHA4
-H0scQgVwAwNaFAZptJwdACHNj/XS+AkIWG4ycLL/o2PvbOvcQMJ+2ga0j1iFLixJ
-uFaMi7sUJKIe7+5/cqtoFWhfW3wRildjBRXKxf4GBYrn6eMUjlxSs8pY/j2eLqEc
-zTJzzYoFffI54Ck/tyry0JJR6Jv5hAxS4Acu/ip2zf20lfTOM8Kvt1jYJ4S6Nc1n
-pkx7RUmroALms20u3qZHBu45Pe2FWlECgcEAxOMq+AXZqArGo9N9gQPNwNAhCdBl
-aEQZPHKb5f8TYM/rBRBF53NbiFKflVxj8Fot6JZP3i7Wzmc+T2AMY3J0t85drzUm
-K6MALXE9c1phZFtFayY9Uyve7HxafFVMf8TbbKJIRJblnDMCeBz6Z0CRQeGDHlY1
-Ei9yE3oAA3Pv5y5xN/SgG8YSbGeEr21v9/CW78SZIl7r1FyWqCpKhKjclysKE651
-Ot1G2dngo/mArAa88nBWZddHFowiPTB2kuGLAoHBAIhyo5b7baNMMYx+ecLHHZ+c
-RyxT7E3FoCVqMhLWrkqsrOa4BEZ4aBNVa95f+TdQBgWQSXb1zKps7UpInT2Aganm
-ryMKOwN0HYZ65F2yfLgYbBSf9FT3HPAORZTnqAuxj5dYuTHZVAQDse/xQg20PYx3
-3DtUKRQfFhMzdvfeXAOpTCaVcNUkx0yLDDabEqZYCDdABMn+xvneqSMOozQigcp6
-OzrFAybOiO/EMvzY28fAAe8iSMnpxC9Z9CYpSQORiwKBwQCDQhylWTvFXIRtN6kA
-rTPV4BYGiu5Fgrt9ob1D/2JAipyuCtlE95Ja4b+46EKgPB6bDt/pdI80RNQ06rLs
-9vh6iZPKI27HwgAeS35M5uuYPNjyGX43cpSdqDxS44hVLeedwYWDD0O9d1b6vfxE
-1bYr66y+5CNhdPa3pqqs9/VEyaDP+Gq9Lrby763KSPVP9bn1LbtsP0fi6GRwHDGt
-xehkx1wNHvjR6NnmkUBtUQByryihoDmZOi9kXWwoyvm3QQcCgcEAw8zqXhE7phhN
-WZZeYjZYYC295VQxktUM7RT2ld2wnE6sFKrBBPtipgZC9o5bgajjNOUQEmkoGkw0
-+TzUwrrB3awzAh9+83XVtT1BiQP3rDdBXuWPnHEe5v/7Zzg06YHfxVOi0WlohqoV
-RrUsbxLRn83Z+5HhhRlIKEuUq5cIkPR/QJDyxNfxmykC9eS7LrAdaBU9dDF6uZYI
-6mxZaz6MAmYRNlFyQA3BMBJIcykQU10Jxil68yOrYLz7o1zARFxZ
------END RSA PRIVATE KEY-----
diff --git a/board/nucleo-h743zi/ec.tasklist b/board/nucleo-h743zi/ec.tasklist
deleted file mode 100644
index 9c37e0b58b..0000000000
--- a/board/nucleo-h743zi/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #include "base-ec.tasklist"
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST BASEBOARD_CONFIG_TASK_LIST
diff --git a/board/nucleo-h743zi/gpio.inc b/board/nucleo-h743zi/gpio.inc
deleted file mode 100644
index 0f2bb32d75..0000000000
--- a/board/nucleo-h743zi/gpio.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Note that these pins map to the Nucleo-H743ZI V2 and are only slightly
- * compatible with the original version.
- *
- * The V2 is denoted by "Nucleo-H743ZI2" vs. "Nucleo-H743ZI".
- */
-
-#include "base-gpio.inc"
-
-/* Interrupts */
-GPIO_INT(PCH_SLP_S0_L,    PIN(D, 13), GPIO_INT_BOTH, slp_event)
-GPIO_INT(PCH_SLP_S3_L,    PIN(A, 11), GPIO_INT_BOTH, slp_event)
diff --git a/board/nucleo-h743zi/openocd-flash.cfg b/board/nucleo-h743zi/openocd-flash.cfg
deleted file mode 120000
index 904ee459ab..0000000000
--- a/board/nucleo-h743zi/openocd-flash.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-h743zi/openocd-flash.cfg
\ No newline at end of file
diff --git a/board/nucleo-h743zi/openocd.cfg b/board/nucleo-h743zi/openocd.cfg
deleted file mode 120000
index b3fc5796c5..0000000000
--- a/board/nucleo-h743zi/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/nucleo-h743zi/openocd.cfg
\ No newline at end of file
diff --git a/board/nuwani/analyzestack.yaml b/board/nuwani/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/nuwani/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/nuwani/battery.c b/board/nuwani/battery.c
deleted file mode 100644
index 5cbbeb5123..0000000000
--- a/board/nuwani/battery.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Treeya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 5B10Q13163 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L17M3PB0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC 5B10Q13162  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L17L3PB0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 181,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L18D3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP L19M3PG1 */
-	[BATTERY_SMP_1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* LGC  L19L3PG1 */
-	[BATTERY_LGC_1] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Celxpert  L19C3PG1 */
-	[BATTERY_CEL_1] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L19C3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_1;
diff --git a/board/nuwani/board.c b/board/nuwani/board.c
deleted file mode 100644
index 8004e25b37..0000000000
--- a/board/nuwani/board.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Treeya board-specific configuration */
-
-#include "button.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "system.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Motion sensors */
-static struct mutex g_lid_mutex_1;
-static struct mutex g_base_mutex_1;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t lid_accel_1 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LIS2DWL,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &lis2dw12_drv,
-	.mutex = &g_lid_mutex_1,
-	.drv_data = &g_lis2dwl_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	.rot_standard_ref = NULL,
-	.default_range = 2, /* g */
-	.min_frequency = LIS2DW12_ODR_MIN_VAL,
-	.max_frequency = LIS2DW12_ODR_MAX_VAL,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t base_accel_1 = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.rot_standard_ref = &lsm6dsm_base_standard_ref,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t base_gyro_1 = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	.rot_standard_ref = &lsm6dsm_base_standard_ref,
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-};
-
-static int board_use_st_sensor(void)
-{
-	/* sku_id 0xa8-0xa9 use ST sensors */
-	uint32_t sku_id = system_get_sku_id();
-
-	return sku_id == 0xa8 || sku_id == 0xa9;
-}
-
-/* treeya board will use two sets of lid/base sensor, we need update
- * sensors info according to sku id.
- */
-void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		/* sku_id a8-a9 use ST sensors */
-		if (board_use_st_sensor()) {
-			motion_sensors[LID_ACCEL] = lid_accel_1;
-			motion_sensors[BASE_ACCEL] = base_accel_1;
-			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
-			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
-		}
-
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-/* bmi160 or lsm6dsm need different interrupt function */
-void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal)
-{
-	if (board_use_st_sensor())
-		lsm6dsm_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
diff --git a/board/nuwani/board.h b/board/nuwani/board.h
deleted file mode 100644
index 780e1cd852..0000000000
--- a/board/nuwani/board.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Treeya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3447
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Power and battery LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-
-#define CONFIG_LED_ONOFF_STATES
-
-/* Disable keyboard backlight */
-#undef CONFIG_PWM
-#undef CONFIG_PWM_KBLIGHT
-
-#define CONFIG_MKBP_USE_GPIO
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-/*
- * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
- */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
-#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
-
-/* Second set of sensor drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LIS2DWL
-
-#ifndef __ASSEMBLER__
-
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP_1,
-	BATTERY_LGC_1,
-	BATTERY_CEL_1,
-	BATTERY_TYPE_COUNT,
-};
-
-void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nuwani/build.mk b/board/nuwani/build.mk
deleted file mode 100644
index 85b141b15d..0000000000
--- a/board/nuwani/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/nuwani/ec.tasklist b/board/nuwani/ec.tasklist
deleted file mode 100644
index 2874dff927..0000000000
--- a/board/nuwani/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/nuwani/gpio.inc b/board/nuwani/gpio.inc
deleted file mode 100644
index 18c72c8125..0000000000
--- a/board/nuwani/gpio.inc
+++ /dev/null
@@ -1,119 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	board_bmi160_lsm6dsm_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(E, 4), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(EC_INT_L,			PIN(A, 4), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
-										   EC_I2C_KB_BL_SCL */
-GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
-										   EC_I2C_KB_BL_SDA */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP)	/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_1_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(BAT_LED_2_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(POWER_LED_3_L,	 PIN(B, 7), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)					/* GPIO00 = AC_PRESENT,
-										   GPIO01 = POWER_BUTTON_L,
-										   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 = LID_OPEN */
diff --git a/board/nuwani/led.c b/board/nuwani/led.c
deleted file mode 100644
index 76156d66d4..0000000000
--- a/board/nuwani/led.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_POWER_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_POWER_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/nuwani/vif_override.xml b/board/nuwani/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/nuwani/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/oak/battery.c b/board/oak/battery.c
deleted file mode 100644
index fffd2f7763..0000000000
--- a/board/oak/battery.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "i2c.h"
-#include "util.h"
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
-#define PARAM_CUT_OFF_HIGH 0x00
-
-static const struct battery_info info = {
-#if (BOARD_REV >= OAK_REV3)
-	.voltage_max = 13050,
-	.voltage_normal = 11400,
-	/*
-	 * TODO(crosbug.com/p/44428):
-	 * In order to compatible with 2S battery, set min voltage as 6V rather
-         * than 9V. Should set voltage_min to 9V, when 2S battery
-	 * phased out.
-	 */
-	.voltage_min = 6000,
-#else /* BOARD_REV < OAK_REV3 */
-	.voltage_max = 8700,
-	.voltage_normal = 7600,
-	.voltage_min = 6000,
-#endif
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-static int cutoff(void)
-{
-	int rv;
-	uint8_t buf[3];
-
-	/* Ship mode command must be sent twice to take effect */
-	buf[0] = SB_MANUFACTURER_ACCESS & 0xff;
-	buf[1] = PARAM_CUT_OFF_LOW;
-	buf[2] = PARAM_CUT_OFF_HIGH;
-
-	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	i2c_lock(I2C_PORT_BATTERY, 0);
-
-	return rv;
-}
-
-int board_cut_off_battery(void)
-{
-	return cutoff();
-}
diff --git a/board/oak/board.c b/board/oak/board.c
deleted file mode 100644
index e8eba6d45b..0000000000
--- a/board/oak/board.c
+++ /dev/null
@@ -1,732 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Oak board configuration */
-
-#include "adc.h"
-#include "als.h"
-#include "atomic.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_opt3001.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "thermal.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Dispaly port hardware can connect to port 0, 1 or neither. */
-#define PD_PORT_NONE -1
-
-void pd_mcu_interrupt(enum gpio_signal signal)
-{
-	/* Exchange status with PD MCU to determine interrupt cause */
-	host_command_pd_send_status(0);
-}
-
-#if BOARD_REV >= OAK_REV4
-void usb_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_INTR);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_INTR);
-}
-#endif /* BOARD_REV >= OAK_REV4 */
-
-#include "gpio_list.h"
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/*
-	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
-	 * output in mW
-	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
-	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
-	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"battery", I2C_PORT_BATTERY, 100,  GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"pd",      I2C_PORT_PD_MCU,  1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA}
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#ifdef CONFIG_ACCELGYRO_BMI160
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI2_NSS }
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-#endif
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC,
-			.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC,
-			.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-};
-
-struct mutex pericom_mux_lock;
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_gpio = GPIO_USB_C_BC12_SEL,
-		.mux_gpio_level = 0,
-		.mux_lock = &pericom_mux_lock,
-	},
-	{
-		.i2c_port = I2C_PORT_PERICOM,
-		.mux_gpio = GPIO_USB_C_BC12_SEL,
-		.mux_gpio_level = 1,
-		.mux_lock = &pericom_mux_lock,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-#if BOARD_REV == OAK_REV1
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = I2C_ADDR_CHARGER_FLAGS,
-		.drv = &bq2477x_drv,
-	},
-};
-#else
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-#endif /* OAK_REV1 */
-
-/*
- * Temperature sensors data; must be in same order as enum temp_sensor_id.
- * Sensor index and name must match those present in coreboot:
- *     src/mainboard/google/${board}/acpi/dptf.asl
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-#ifdef HAS_TASK_ALS
-/* ALS instances. Must be in same order as enum als_id. */
-struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
-};
-BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
-#endif
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver    = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-#if (BOARD_REV <= OAK_REV4)
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR1,
-		.driver    = &pi3usb3x532_usb_mux_driver,
-#else
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
-#endif
-	},
-};
-
-/**
- * Store the current DP hardware route.
- */
-static int dp_hw_port = PD_PORT_NONE;
-static struct mutex dp_hw_lock;
-
-/**
- * Reset PD MCU
- */
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_PD_RST_L, 0);
-	usleep(100);
-	gpio_set_level(GPIO_USB_PD_RST_L, 1);
-}
-
-/**
- * There is a level shift for AC_OK & LID_OPEN signal between AP & EC,
- * disable it (drive high) when AP is off, otherwise enable it (drive low).
- */
-static void board_extpower_buffer_to_soc(void)
-{
-	/* Drive high when AP is off (G3), else drive low */
-	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L,
-		       chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 1 : 0);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * Assert wake GPIO to PD MCU to wake it from hibernate.
-	 * This cannot be done from board_pre_init() (or from any function
-	 * called before system_pre_init()), otherwise a spurious wake will
-	 * occur -- see stm32 check_reset_cause() WORKAROUND comment.
-	 */
-	gpio_set_level(GPIO_USB_PD_VBUS_WAKE, 1);
-
-	/* Enable Level shift of AC_OK & LID_OPEN signals */
-	board_extpower_buffer_to_soc();
-	/* Enable rev1 testing GPIOs */
-	gpio_set_level(GPIO_SYSTEM_POWER_H, 1);
-	/* Enable PD MCU interrupt */
-	gpio_enable_interrupt(GPIO_PD_MCU_INT);
-
-#if BOARD_REV >= OAK_REV4
-	/* Enable BC 1.2 interrupt */
-	gpio_enable_interrupt(GPIO_USB_BC12_INT);
-#endif /* BOARD_REV >= OAK_REV4 */
-
-#if BOARD_REV >= OAK_REV3
-	/* Update VBUS supplier */
-	usb_charger_vbus_change(0, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-	usb_charger_vbus_change(1, !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
-#else
-	usb_charger_vbus_change(0, 0);
-	usb_charger_vbus_change(1, 0);
-#endif
-
-#ifdef CONFIG_ACCELGYRO_BMI160
-	/* SPI sensors: put back the GPIO in its expected state */
-	gpio_set_level(GPIO_SPI2_NSS, 1);
-
-	/* Remap SPI2 to DMA channels 6 and 7 (0011) */
-	STM32_DMA_CSELR(STM32_DMAC_CH6) |= (3 << 20) | (3 << 24);
-
-	/* Enable SPI for BMI160 */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-
-	/* Set all four SPI pins to high speed */
-	/* pins D0/D1/D3/D4 */
-	STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-	CPRINTS("Board using SPI sensors");
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can active at a time.
- *
- * @param charge_port    Charge port to enable.
- *
- * Return EC_SUCCESS if charge port is accepted and made active.
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source VBUS on the port */
-	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
-						       GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTF("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.
- */
-static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static void board_typec_set_dp_hpd(int port, int level)
-{
-#if BOARD_REV >= OAK_REV5
-	if (1 == dp_hw_port)
-		gpio_set_level(GPIO_C1_DP_HPD, level);
-#endif
-
-	gpio_set_level(GPIO_USB_DP_HPD, level);
-}
-
-/**
- * Turn on DP hardware on type-C port.
- */
-void board_typec_dp_on(int port)
-{
-	mutex_lock(&dp_hw_lock);
-
-	if (dp_hw_port != !port) {
-		/* Get control of DP hardware */
-		dp_hw_port = port;
-#if BOARD_REV == OAK_REV2 || BOARD_REV >= OAK_REV5
-		/* Rev2 or Rev5 later board has DP switch */
-		gpio_set_level(GPIO_DP_SWITCH_CTL, port);
-#endif
-		if (!gpio_get_level(GPIO_USB_DP_HPD)) {
-			board_typec_set_dp_hpd(port, 1);
-		} else {
-			uint64_t now = get_time().val;
-			/* wait for the minimum spacing between IRQ_HPD */
-			if (now < hpd_deadline[port])
-				usleep(hpd_deadline[port] - now);
-
-			board_typec_set_dp_hpd(port, 0);
-			usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-			board_typec_set_dp_hpd(port, 1);
-		}
-	}
-	/* enforce 2-ms delay between HPD pulses */
-	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-
-	mutex_unlock(&dp_hw_lock);
-}
-
-/**
- * Turn off a PD port's DP output.
- */
-void board_typec_dp_off(int port, int *dp_flags)
-{
-	mutex_lock(&dp_hw_lock);
-
-	if (dp_hw_port == !port) {
-		mutex_unlock(&dp_hw_lock);
-		return;
-	}
-
-	dp_hw_port = PD_PORT_NONE;
-	board_typec_set_dp_hpd(port, 0);
-
-	mutex_unlock(&dp_hw_lock);
-
-	/* Enable the other port if its dp flag is on */
-	if (dp_flags[!port] & DP_FLAGS_DP_ON)
-		board_typec_dp_on(!port);
-}
-
-/**
- * Set DP hotplug detect level.
- */
-void board_typec_dp_set(int port, int level)
-{
-	mutex_lock(&dp_hw_lock);
-
-	if (dp_hw_port == PD_PORT_NONE) {
-		dp_hw_port = port;
-#if BOARD_REV == OAK_REV2 || BOARD_REV >= OAK_REV5
-		/* Rev2 or Rev5 later board has DP switch */
-		gpio_set_level(GPIO_DP_SWITCH_CTL, port);
-#endif
-	}
-
-	if (dp_hw_port == port)
-		board_typec_set_dp_hpd(port, level);
-
-	mutex_unlock(&dp_hw_lock);
-}
-
-#if BOARD_REV < OAK_REV3
-#ifndef CONFIG_AP_WARM_RESET_INTERRUPT
-/* Using this hook if system doesn't have enough external line. */
-static void check_ap_reset_second(void)
-{
-	/* Check the warm reset signal from servo board */
-	static int warm_reset, last;
-
-	warm_reset = !gpio_get_level(GPIO_AP_RESET_L);
-
-	if (last == warm_reset)
-		return;
-
-	if (warm_reset)
-		chipset_reset(); /* Warm reset AP */
-
-	last = warm_reset;
-}
-DECLARE_HOOK(HOOK_SECOND, check_ap_reset_second, HOOK_PRIO_DEFAULT);
-#endif
-#endif
-
-/**
- * Set AP reset.
- *
- * PMIC_WARM_RESET_H (PB3) is connected to PMIC RESET before rev < 3.
- * AP_RESET_L (PC3, CPU_WARM_RESET_L) is connected to PMIC SYSRSTB
- * after rev >= 3.
- */
-void board_set_ap_reset(int asserted)
-{
-	if (system_get_board_version() < 3) {
-		/* Signal is active-high */
-		CPRINTS("pmic warm reset(%d)", asserted);
-		gpio_set_level(GPIO_PMIC_WARM_RESET_H, asserted);
-	} else {
-		/* Signal is active-low */
-		CPRINTS("ap warm reset(%d)", asserted);
-		gpio_set_level(GPIO_AP_RESET_L, !asserted);
-	}
-}
-
-#if BOARD_REV < OAK_REV4
-/**
- * Check VBUS state and trigger USB BC1.2 charger.
- */
-void vbus_task(void *u)
-{
-	struct {
-		uint8_t interrupt;
-		uint8_t device_type;
-		uint8_t charger_status;
-		uint8_t vbus;
-	} bc12[CONFIG_USB_PD_PORT_MAX_COUNT];
-	uint8_t port, vbus, reg, wake;
-
-	while (1) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
-#if BOARD_REV == OAK_REV3
-			vbus = !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
-						      GPIO_USB_C0_VBUS_WAKE_L);
-#else
-			vbus = tcpm_check_vbus_level(port, VBUS_PRESENT);
-#endif
-			/* check if VBUS changed */
-			if (((bc12[port].vbus >> port) & 1) == vbus)
-				continue;
-			/* wait 1.2 seconds and check BC 1.2 status */
-			msleep(1200);
-
-			if (vbus)
-				bc12[port].vbus |= 1 << port;
-			else
-				bc12[port].vbus &= ~BIT(port);
-
-			wake = 0;
-			reg = pi3usb9281_get_interrupts(port);
-			if (reg != bc12[port].interrupt) {
-				bc12[port].interrupt = reg;
-				wake++;
-			}
-
-			reg = pi3usb9281_get_device_type(port);
-			if (reg != bc12[port].device_type) {
-				bc12[port].device_type = reg;
-				wake++;
-			}
-
-			reg = pi3usb9281_get_charger_status(port);
-			if (reg != bc12[port].charger_status) {
-				bc12[port].charger_status = reg;
-				wake++;
-			}
-
-			if (wake)
-				task_set_event(port ? TASK_ID_USB_CHG_P1 :
-						      TASK_ID_USB_CHG_P0,
-					       USB_CHG_EVENT_BC12);
-		}
-		task_wait_event(-1);
-	}
-}
-#else
-void vbus_task(void *u)
-{
-	while (1)
-		task_wait_event(-1);
-}
-#endif /* BOARD_REV < OAK_REV4 */
-
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-static void tmp432_set_power_deferred(void)
-{
-       /* Shut tmp432 down if not in S0 && no external power */
-       if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
-               if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
-			CPRINTS("ERROR: Can't shutdown TMP432.");
-               return;
-       }
-
-       /*  else, turn it on. */
-       if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
-		CPRINTS("ERROR: Can't turn on TMP432.");
-}
-DECLARE_DEFERRED(tmp432_set_power_deferred);
-#endif
-
-/**
- * Hook of AC change. turn on/off tmp432 depends on AP & AC status.
- */
-static void board_extpower(void)
-{
-	board_extpower_buffer_to_soc();
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition, and before HOOK_CHIPSET_STARTUP */
-static void board_chipset_pre_init(void)
-{
-	/* Enable level shift of AC_OK when power on */
-	board_extpower_buffer_to_soc();
-#if BOARD_REV >= OAK_REV5
-	/* Enable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 0);
-	gpio_set_level(GPIO_PARADE_MUX_EN, 1);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable level shift to SoC when shutting down */
-	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1);
-#if BOARD_REV >= OAK_REV5
-	/* Disable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 1);
-	gpio_set_level(GPIO_PARADE_MUX_EN, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-	hook_call_deferred(&tmp432_set_power_deferred_data, 0);
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef HAS_TASK_MOTIONSENSE
-/* Motion sensors */
-/* Mutexes */
-#ifdef CONFIG_ACCEL_KX022
-static struct mutex g_lid_mutex;
-#endif
-#ifdef CONFIG_ACCELGYRO_BMI160
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0,  FLOAT_TO_FP(1)}
-};
-#endif
-
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-#ifdef CONFIG_ACCELGYRO_BMI160
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(0),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-#endif
-#ifdef CONFIG_ACCEL_KX022
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = NULL, /* Identity matrix. */
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-#endif
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-__override void lid_angle_peripheral_enable(int enable)
-{
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-#endif /* defined(HAS_TASK_MOTIONSENSE) */
diff --git a/board/oak/board.h b/board/oak/board.h
deleted file mode 100644
index e82907a508..0000000000
--- a/board/oak/board.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* oak board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* board revision */
-#include "board_revs.h"
-
-/* Free up some flash space */
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#define CONFIG_USB_PD_DEBUG_LEVEL 0
-
-#define CONFIG_LTO
-
-#if BOARD_REV >= OAK_REV5
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#endif
-
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-
-#if BOARD_REV >= OAK_REV5
-/* Add for Ambient Light Sensor */
-#define CONFIG_ALS_OPT3001
-#define CONFIG_CMD_ALS
-#endif
-
-/* Add for AC adaptor, charger, battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
-#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#define CONFIG_BATTERY_SMART
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-
-#if BOARD_REV == OAK_REV1
-#define CONFIG_CHARGER_BQ24773
-#define CONFIG_CHARGER_MAX_INPUT_CURRENT 2150
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#else
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_ISL9237
-#define CONFIG_CHARGER_MAX_INPUT_CURRENT 2250
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#endif /* BOARD_REV */
-
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHIPSET_MT817X
-#define CONFIG_CMD_TYPEC
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_FORCE_CONSOLE_RESUME
-
-/*
- * EC_WAKE: PA0 - WKUP1
- * POWER_BUTTON_L: PB5 - WKUP6
- */
-#define CONFIG_HIBERNATE
-#if BOARD_REV <= OAK_REV4
-#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP6)
-#else
-#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1)
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-#endif /* BOARD_REV */
-#define CONFIG_HOST_COMMAND_STATUS
-#define CONFIG_HOSTCMD_PD
-#define CONFIG_HOSTCMD_PD_PANIC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_COMMON
-#define CONFIG_USB_CHARGER
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
-#define CONFIG_SWITCH
-#define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_TMP432
-#define CONFIG_DPTF
-
-/* UART DMA */
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* Optional features */
-#define CONFIG_CMD_HOSTCMD
-#undef CONFIG_CMD_MFALLOW
-
-/* Drivers */
-/* USB Mux */
-#define CONFIG_USB_MUX_PI3USB30532
-#if BOARD_REV >= OAK_REV5
-#define CONFIG_USB_MUX_PS8740
-#endif
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-#ifndef __ASSEMBLER__
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Keyboard output port list */
-#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
-
-/* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
-#define I2C_PORT_ALS     0
-#define I2C_PORT_BATTERY 0
-#define I2C_PORT_CHARGER 0
-#define I2C_PORT_PERICOM 0
-#define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
-#define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI master port (SPI2) */
-
-/* Ambient Light Sensor address */
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_WATCHDOG 4
-
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
-
-#include "gpio_signal.h"
-
-enum power_signal {
-	MTK_POWER_GOOD = 0,
-	MTK_SUSPEND_ASSERTED,
-	/* Number of power signals */
-	POWER_SIGNAL_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_POWER_LED = 0,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
-	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	/* TMP432 local and remote sensors */
-	TEMP_SENSOR_I2C_TMP432_LOCAL,
-	TEMP_SENSOR_I2C_TMP432_REMOTE1,
-	TEMP_SENSOR_I2C_TMP432_REMOTE2,
-
-	/* Battery temperature sensor */
-	TEMP_SENSOR_BATTERY,
-
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-#ifdef CONFIG_ACCELGYRO_BMI160
-	BASE_ACCEL,
-	BASE_GYRO,
-#endif
-#ifdef CONFIG_ACCEL_KX022
-	LID_ACCEL,
-#endif
-	SENSOR_COUNT,
-};
-
-/* Light sensors */
-enum als_id {
-	ALS_OPT3001 = 0,
-
-	ALS_COUNT
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-/* Set AP reset pin according to parameter */
-void board_set_ap_reset(int asserted);
-
-/* Control type-C DP route and hotplug detect signal */
-void board_typec_dp_on(int port);
-void board_typec_dp_off(int port, int *dp_flags);
-void board_typec_dp_set(int port, int level);
-
-#endif  /* !__ASSEMBLER__ */
-
-#endif  /* __CROS_EC_BOARD_H */
diff --git a/board/oak/board_revs.h b/board/oak/board_revs.h
deleted file mode 100644
index 34fc4bfc88..0000000000
--- a/board/oak/board_revs.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_REVS_H
-#define __CROS_EC_BOARD_REVS_H
-
-#define OAK_REV0 0
-#define OAK_REV1 1
-#define OAK_REV2 2
-#define OAK_REV3 3
-#define OAK_REV4 4
-#define OAK_REV5 5
-#define OAK_REV_LAST    OAK_REV5
-#define OAK_REV_DEFAULT OAK_REV5
-
-#if !defined(BOARD_REV)
-#define BOARD_REV OAK_REV_DEFAULT
-#endif
-
-#if BOARD_REV < OAK_REV1 || BOARD_REV > OAK_REV_LAST
-#error "Board revision out of range"
-#endif
-
-#endif /* __CROS_EC_BOARD_REVS_H */
diff --git a/board/oak/build.mk b/board/oak/build.mk
deleted file mode 100644
index dc21970df0..0000000000
--- a/board/oak/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#-*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# STmicro STM32F091VC
-CHIP := stm32
-CHIP_FAMILY := stm32f0
-CHIP_VARIANT:= stm32f09x
-
-board-y = board.o battery.o led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/oak/ec.tasklist b/board/oak/ec.tasklist
deleted file mode 100644
index 2af7da77eb..0000000000
--- a/board/oak/ec.tasklist
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#include "board_revs.h"
-
-
-#if BOARD_REV >= OAK_REV5
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VBUS, vbus_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(ALS, als_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
-
-#else  /* BOARD_REV >= OAK_REV5 */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(VBUS, vbus_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
-
-#endif  /* BOARD_REV >= OAK_REV5 */
diff --git a/board/oak/gpio.inc b/board/oak/gpio.inc
deleted file mode 100644
index 3789f3ec35..0000000000
--- a/board/oak/gpio.inc
+++ /dev/null
@@ -1,214 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(AC_PRESENT,     PIN(C, 6),  GPIO_INT_BOTH,                     extpower_interrupt)
-GPIO_INT(POWER_BUTTON_L, PIN(B, 5),  GPIO_INT_BOTH | GPIO_PULL_UP,      power_button_interrupt)
-GPIO_INT(LID_OPEN,       PIN(C, 13), GPIO_INT_BOTH,                     lid_interrupt)          /* LID switch detection */
-#if BOARD_REV <= OAK_REV3
-GPIO_INT(SUSPEND_L,      PIN(C, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,    power_signal_interrupt) /* AP suspend/resume state */
-#else
-GPIO_INT(SUSPEND_L,      PIN(C, 7),  GPIO_INT_BOTH,                     power_signal_interrupt) /* AP suspend/resume state */
-#endif
-GPIO_INT(PD_MCU_INT,     PIN(E, 0),  GPIO_INT_FALLING,                  pd_mcu_interrupt)       /* Signal from PD MCU, external pull-up */
-GPIO_INT(SPI1_NSS,       PIN(A, 4),  GPIO_INT_BOTH | GPIO_PULL_UP,      spi_event)              /* SPI Chip Select */
-
-/* Keyboard inputs */
-#define GPIO_KB_INPUT  (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
-
-GPIO_INT(KB_IN00, PIN(C, 8),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN01, PIN(C, 9),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-GPIO_INT(KB_IN07, PIN(D, 2),  GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
-
-/* Board specific interrupt and input */
-#if BOARD_REV <= OAK_REV1
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH | GPIO_PULL_DOWN,    power_signal_interrupt)
-GPIO(EC_INT_L,           PIN(B, 9),  GPIO_OUT_HIGH)
-#elif BOARD_REV == OAK_REV2
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH | GPIO_PULL_DOWN,    power_signal_interrupt)
-GPIO(EC_INT_L,           PIN(B, 9),  GPIO_OUT_HIGH)
-GPIO(USB_VBUS_WAKE_L,    PIN(E, 1),  GPIO_INPUT)
-#elif BOARD_REV == OAK_REV3
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH | GPIO_PULL_DOWN,    power_signal_interrupt)
-GPIO(EC_INT_L,           PIN(B, 9),  GPIO_OUT_HIGH)
-GPIO(USB_C0_VBUS_WAKE_L, PIN(E, 1),  GPIO_INPUT)
-GPIO(USB_C1_VBUS_WAKE_L, PIN(F, 2),  GPIO_INPUT)
-#elif BOARD_REV >= OAK_REV4
-GPIO_INT(SOC_POWER_GOOD, PIN(A, 3),  GPIO_INT_BOTH                 ,    power_signal_interrupt)
-GPIO_INT(USB_BC12_INT,   PIN(E, 1),  GPIO_INT_FALLING, usb_evt)
-GPIO(USB_C0_VBUS_WAKE_L, PIN(D, 12), GPIO_INPUT)
-GPIO(USB_C1_VBUS_WAKE_L, PIN(F, 2),  GPIO_INPUT)
-GPIO(EC_INT_L,           PIN(B, 9),  GPIO_ODR_HIGH)
-#endif
-
-/* Inputs without interrupt handlers */
-GPIO(5V_POWER_GOOD, PIN(A, 1), GPIO_INPUT)
-GPIO(EC_WAKE,       PIN(A, 0), GPIO_INPUT|GPIO_PULL_DOWN)
-GPIO(WP_L,          PIN(B, 4), GPIO_INPUT)      /* Write protect input */
-GPIO(BAT_PRESENT_L, PIN(E, 3), GPIO_INPUT|GPIO_PULL_UP)
-
-/* Board version */
-GPIO(BOARD_VERSION1, PIN(E, 10), GPIO_INPUT) /* Board ID 0 */
-GPIO(BOARD_VERSION2, PIN(E,  9), GPIO_INPUT) /* Board ID 1 */
-GPIO(BOARD_VERSION3, PIN(E, 12), GPIO_INPUT) /* Board ID 2 */
-GPIO(BOARD_VERSION4, PIN(E, 11), GPIO_INPUT) /* Board ID 3 */
-
-/* Outputs */
-#if BOARD_REV < OAK_REV5
-GPIO(BAT_LED0,          PIN(B, 11), GPIO_OUT_LOW)   /* LED_GREEN */
-GPIO(BAT_LED1,          PIN(A, 11), GPIO_OUT_LOW)   /* LED_ORANGE or LED_RED(>rev3)*/
-#else
-GPIO(BAT_LED0,          PIN(A, 11), GPIO_OUT_LOW)   /* LED_GREEN */
-GPIO(BAT_LED1,          PIN(B, 11), GPIO_OUT_LOW)   /* LED_ORANGE or LED_RED(>rev3)*/
-#endif
-
-#if (BOARD_REV == OAK_REV3) || (BOARD_REV == OAK_REV4)
-GPIO(PWR_LED0,          PIN(F, 10), GPIO_OUT_LOW)   /* LED_GREEN */
-GPIO(PWR_LED1,          PIN(F,  9), GPIO_OUT_LOW)   /* LED_ORANGE */
-#else
-UNIMPLEMENTED(PWR_LED0)
-UNIMPLEMENTED(PWR_LED1)
-#endif
-GPIO(EC_BL_OVERRIDE,    PIN(F, 1),  GPIO_OUT_LOW)
-GPIO(ENTERING_RW,       PIN(F, 0),  GPIO_OUT_LOW)
-
-
-#if BOARD_REV == OAK_REV1
-GPIO(AP_RESET_L,        PIN(C, 3),  GPIO_INPUT|GPIO_PULL_UP) /* AP reset signal from servo board */
-GPIO(USB_C_BC12_SEL,    PIN(A, 14), GPIO_OUT_LOW)
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW)   /* KSO2 is inverted */
-GPIO(KB_OUT03,          PIN(B, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(D, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(D, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(D, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(C, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(A, 13), GPIO_KB_OUTPUT)
-UNIMPLEMENTED(DP_SWITCH_CTL)
-
-#elif BOARD_REV == OAK_REV2
-GPIO(AP_RESET_L,        PIN(C, 3),  GPIO_INPUT|GPIO_PULL_UP) /* AP reset signal from servo board */
-GPIO(USB_C_BC12_SEL,    PIN(D, 7),  GPIO_OUT_LOW)
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW)   /* KSO2 is inverted */
-GPIO(KB_OUT03,          PIN(B, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(D, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(D, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(D, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(C, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(D, 5),  GPIO_KB_OUTPUT)
-GPIO(DP_MUX_EN_L,       PIN(E, 6),  GPIO_OUT_LOW)
-GPIO(DP_SWITCH_CTL,     PIN(E, 5),  GPIO_OUT_LOW)
-
-#elif BOARD_REV <= OAK_REV4 /* BOARD_REV 3 or 4 */
-GPIO(AP_RESET_L,        PIN(C, 3),  GPIO_ODR_HIGH) /* Connect to the PMU_SYSRSTB */
-GPIO(USB_C_BC12_SEL,    PIN(D, 7),  GPIO_OUT_LOW)
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW)   /* KSO2 is inverted */
-GPIO(KB_OUT03,          PIN(D, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(D, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(B, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(D, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(D, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(C, 2),  GPIO_KB_OUTPUT)
-UNIMPLEMENTED(DP_SWITCH_CTL)
-
-#else /* >= OAK_REV5 */
-GPIO(AP_RESET_L,        PIN(C, 3),  GPIO_ODR_HIGH) /* Connect to the PMU_SYSRSTB */
-GPIO(USB_C_BC12_SEL,    PIN(D, 7),  GPIO_OUT_LOW)
-GPIO(KB_OUT00,          PIN(B, 0),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT01,          PIN(B, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT02,          PIN(B, 12), GPIO_OUT_LOW)   /* KSO2 is inverted */
-GPIO(KB_OUT03,          PIN(B, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT04,          PIN(A, 8),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT05,          PIN(D, 14), GPIO_KB_OUTPUT)
-GPIO(KB_OUT06,          PIN(D, 13), GPIO_KB_OUTPUT)
-GPIO(KB_OUT07,          PIN(D, 15), GPIO_KB_OUTPUT)
-GPIO(KB_OUT08,          PIN(C, 2),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT09,          PIN(B, 1),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT10,          PIN(C, 5),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT11,          PIN(C, 4),  GPIO_KB_OUTPUT)
-GPIO(KB_OUT12,          PIN(D, 5),  GPIO_KB_OUTPUT)
-GPIO(C1_DP_HPD,         PIN(E,15),  GPIO_OUT_LOW)   /* inform PS8740 to exit from idle mode. */
-GPIO(DP_SWITCH_CTL,     PIN(E, 5),  GPIO_OUT_LOW)
-GPIO(EN_OTG_USB_A_PWR,  PIN(E, 4),  GPIO_OUT_HIGH)
-GPIO(OTG_USB_A_ILIM_SEL,PIN(E, 2),  GPIO_OUT_HIGH)
-GPIO(EC_IDDIG,          PIN(E,13),  GPIO_OUT_LOW)
-GPIO(DP_MUX_EN_L,       PIN(E, 6),  GPIO_OUT_LOW)
-GPIO(PARADE_MUX_EN,     PIN(E, 7),  GPIO_OUT_HIGH)
-#endif /* BOARD_REV */
-
-GPIO(SYSTEM_POWER_H,    PIN(B, 10), GPIO_OUT_LOW)
-GPIO(PMIC_PWRON_H,      PIN(A, 12), GPIO_OUT_LOW)
-GPIO(PMIC_WARM_RESET_H, PIN(B, 3),  GPIO_OUT_LOW)
-#if BOARD_REV <= OAK_REV4
-GPIO(LEVEL_SHIFT_EN_L,  PIN(D, 3),  GPIO_OUT_LOW)    /* LID/AC level shift */
-GPIO(USB_C0_DEVMODE_L,  PIN(E, 4),  GPIO_OUT_HIGH)   /* set HSD2 (host mode) path as default */
-GPIO(USB_C1_DEVMODE,    PIN(E, 2),  GPIO_OUT_LOW)    /* set HSD1 (host mode) path as default */
-#else /* >= OAK_REV5 */
-GPIO(LEVEL_SHIFT_EN_L,  PIN(F, 10), GPIO_OUT_LOW)    /* LID/AC level shift */
-/* SPI MASTER. For SPI sensor */
-GPIO(SPI2_NSS, PIN(D, 0),  GPIO_OUT_LOW)
-
-#endif
-GPIO(USB_PD_RST_L,      PIN(A, 15), GPIO_OUT_HIGH)   /* PD reset */
-GPIO(USB_C0_5V_EN,      PIN(D, 8),  GPIO_OUT_LOW)    /* USBC port 0 5V */
-GPIO(USB_C0_CHARGE_L,   PIN(D, 9),  GPIO_OUT_LOW)    /* USBC port 0 charge */
-GPIO(USB_C1_5V_EN,      PIN(D, 10), GPIO_OUT_LOW)    /* USBC port 1 5V */
-GPIO(USB_C1_CHARGE_L,   PIN(D, 11), GPIO_OUT_LOW)    /* USBC port 1 charge */
-GPIO(USB_PD_VBUS_WAKE,  PIN(B, 15), GPIO_OUT_LOW)    /* PD MCU wake */
-GPIO(USB_DP_HPD,        PIN(F, 3),  GPIO_OUT_LOW)
-
-#if (BOARD_REV < OAK_REV5)
-GPIO(TYPEC0_MUX_EN_L,   PIN(E, 13), GPIO_OUT_LOW)
-GPIO(TYPEC1_MUX_EN_L,   PIN(E, 14), GPIO_OUT_LOW)
-#endif
-
-/* Analog pins */
-GPIO(VDC_BOOSTIN_SENSE, PIN(C, 1), GPIO_ANALOG) /* ADC_IN11 */
-GPIO(PSYS_MONITOR,      PIN(A, 2), GPIO_ANALOG) /* ADC_IN2  */
-GPIO(AMON_BMON,         PIN(C, 0), GPIO_ANALOG) /* ADC_IN10 */
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL, PIN(B, 6),  GPIO_INPUT) /* EC I2C */
-GPIO(I2C0_SDA, PIN(B, 7),  GPIO_INPUT)
-GPIO(I2C1_SCL, PIN(B, 13), GPIO_INPUT) /* PD I2C */
-GPIO(I2C1_SDA, PIN(B, 14), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,        0) /* I2C MASTER:PB6/7 */
-ALTERNATE(PIN_MASK(B, 0x6000), 5, MODULE_I2C,        0) /* I2C MASTER:PB13/14 */
-ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI,        0) /* SPI SLAVE:PA4/5/6/7 */
-#if BOARD_REV >= OAK_REV5
-ALTERNATE(PIN_MASK(D, 0x001A), 1, MODULE_SPI_CONTROLLER, 0) /* SPI MASTER:PD1/3/4 */
-#endif
diff --git a/board/oak/led.c b/board/oak/led.c
deleted file mode 100644
index 877f115a12..0000000000
--- a/board/oak/led.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED and Power LED control for Oak Board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "util.h"
-#include "system.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	BAT_LED_GREEN = 0,
-	BAT_LED_ORANGE,
-	BAT_LED_RED,
-	BAT_LED_AMBER,
-	PWR_LED_GREEN,
-	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
-};
-
-static int bat_led_set(enum led_color color, int on)
-{
-	/* Before Rev5, it's active low; After that, it's active high */
-	if (system_get_board_version() < OAK_REV5)
-		on = !on;
-
-	switch (color) {
-	case BAT_LED_GREEN:
-		gpio_set_level(GPIO_BAT_LED0, on); /* BAT_LED_GREEN */
-		break;
-	case BAT_LED_ORANGE:
-		/* for rev2 or before */
-		gpio_set_level(GPIO_BAT_LED1, on); /* BAT_LED_ORANGE */
-		break;
-	case BAT_LED_RED:
-		/* for rev3 or later */
-		gpio_set_level(GPIO_BAT_LED1, on); /* BAT_LED_RED */
-		break;
-	case BAT_LED_AMBER:
-		/* for rev3 or later */
-		gpio_set_level(GPIO_BAT_LED0, on); /* BAT_LED_AMBER */
-		gpio_set_level(GPIO_BAT_LED1, on);
-		break;
-	case PWR_LED_GREEN:
-		gpio_set_level(GPIO_PWR_LED0, on); /* PWR_LED_GREEN */
-		break;
-	case PWR_LED_ORANGE:
-		gpio_set_level(GPIO_PWR_LED1, on); /* PWR_LED_ORANGE */
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	/* Ignoring led_id as both leds support the same colors */
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-	brightness_range[EC_LED_COLOR_YELLOW] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (EC_LED_ID_BATTERY_LED == led_id) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0) {
-			bat_led_set(BAT_LED_GREEN, 1);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		} else if (brightness[EC_LED_COLOR_YELLOW] != 0) {
-			bat_led_set(BAT_LED_GREEN, 1);
-			bat_led_set(BAT_LED_ORANGE, 1);
-		} else if (brightness[EC_LED_COLOR_RED] != 0) {
-			bat_led_set(BAT_LED_GREEN, 0);
-			bat_led_set(BAT_LED_RED, 1);
-		} else {
-			bat_led_set(BAT_LED_GREEN, 0);
-			bat_led_set(BAT_LED_ORANGE, 0);
-		}
-		return EC_SUCCESS;
-	} else if (EC_LED_ID_POWER_LED == led_id) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0) {
-			bat_led_set(PWR_LED_GREEN, 1);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		} else if (brightness[EC_LED_COLOR_YELLOW] != 0) {
-			bat_led_set(PWR_LED_GREEN, 1);
-			bat_led_set(PWR_LED_ORANGE, 1);
-		} else {
-			bat_led_set(PWR_LED_GREEN, 0);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		}
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static void oak_led_set_power(int board_version)
-{
-	static int power_second;
-
-	power_second++;
-
-	switch(board_version) {
-	case OAK_REV3:
-	case OAK_REV4:
-		/*
-		 * For Rev3 and Rev4 revision.
-		 * PWR LED behavior:
-		 * Power on: Green ON
-		 * Suspend: Orange in breeze mode ( 1 sec on/ 3 sec off)
-		 * Power off: OFF
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			bat_led_set(PWR_LED_GREEN, 0);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			bat_led_set(PWR_LED_GREEN, 1);
-			bat_led_set(PWR_LED_ORANGE, 0);
-		} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-			bat_led_set(PWR_LED_GREEN, 0);
-			bat_led_set(PWR_LED_ORANGE,
-				    (power_second & 3) ? 0 : 1);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static void oak_led_set_battery(int board_version)
-{
-	static int battery_second;
-
-	battery_second++;
-
-	switch(board_version) {
-	case OAK_REV3:
-	case OAK_REV4:
-		/*
-		 * For Rev3 and Rev4 revision:
-		 * BAT LED behavior:
-		 * - Fully charged / idle: Green ON
-		 * - Charging: Amber ON (BAT_LED_RED && BAT_LED_GREEN)
-		 * - Battery discharging capacity<10%, red blink
-		 * - Battery error: Red ON
-		 */
-		switch (charge_get_state()) {
-		case PWR_STATE_CHARGE:
-			bat_led_set(BAT_LED_AMBER, 1);
-			break;
-		case PWR_STATE_CHARGE_NEAR_FULL:
-			bat_led_set(BAT_LED_GREEN, 1);
-			bat_led_set(BAT_LED_RED, 0);
-			break;
-		case PWR_STATE_DISCHARGE:
-			bat_led_set(BAT_LED_GREEN, 0);
-			if (charge_get_percent() < 3)
-				bat_led_set(BAT_LED_RED,
-					  (battery_second & 1) ? 0 : 1);
-			else if (charge_get_percent() < 10)
-				bat_led_set(BAT_LED_RED,
-					  (battery_second & 3) ? 0 : 1);
-			else
-				bat_led_set(BAT_LED_RED, 0);
-			break;
-		case PWR_STATE_ERROR:
-			bat_led_set(BAT_LED_RED, 1);
-			break;
-		case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
-			bat_led_set(BAT_LED_GREEN, 1);
-			bat_led_set(BAT_LED_RED, 0);
-			break;
-		default:
-			/* Other states don't alter LED behavior */
-			break;
-		}
-		break; /* End of case OAK_REV3 & OAK_REV4 */
-	default:
-		/*
-		 * Put power control here since we are using the "battery" LED.
-		 * This allows LED autocontrol to be turned off by cmd during factory test.
-		 *
-		 * PWR LED behavior:
-		 * Power on: Green
-		 * Suspend: Green in breeze mode ( 1 sec on/ 3 sec off)
-		 * Power off: OFF
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			bat_led_set(BAT_LED_GREEN, 0);
-		else if (chipset_in_state(CHIPSET_STATE_ON))
-			bat_led_set(BAT_LED_GREEN, 1);
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-			int cycle_time = 4;
-			/* Oak rev5 with GlaDOS ID has a extremely power
-			 * comsuming LED. Increase LED blink cycle time to reduce
-			 * S3 power comsuption. */
-			if (board_version >= OAK_REV5)
-				cycle_time = 10;
-			bat_led_set(BAT_LED_GREEN,
-				    (battery_second % cycle_time) ? 0 : 1);
-		}
-
-		/* BAT LED behavior:
-		 * Fully charged / idle: Off
-		 * Under charging: Orange
-		 * Bat. low (10%): Orange in breeze mode (1s on, 3s off)
-		 * Bat. critical low (less than 3%) or abnormal battery
-		 *   situation: Orange in blinking mode (1s on, 1s off)
-		 * Using battery or not connected to AC power: OFF
-		 */
-		switch (charge_get_state()) {
-		case PWR_STATE_CHARGE:
-			bat_led_set(BAT_LED_ORANGE, 1);
-			break;
-		case PWR_STATE_CHARGE_NEAR_FULL:
-			bat_led_set(BAT_LED_ORANGE, 1);
-			break;
-		case PWR_STATE_DISCHARGE:
-			if (charge_get_percent() < 3)
-				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 1) ? 0 : 1);
-			else if (charge_get_percent() < 10)
-				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 3) ? 0 : 1);
-			else
-				bat_led_set(BAT_LED_ORANGE, 0);
-			break;
-		case PWR_STATE_ERROR:
-			bat_led_set(BAT_LED_ORANGE,
-				    (battery_second & 1) ? 0 : 1);
-			break;
-		case PWR_STATE_IDLE: /* Ext. power connected in IDLE. */
-			bat_led_set(BAT_LED_ORANGE, 0);
-			break;
-		default:
-			/* Other states don't alter LED behavior */
-			break;
-		}
-		break; /* End of default */
-	}
-}
-
-/**
- * Called by hook task every 1 sec
- */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		oak_led_set_power(system_get_board_version());
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		oak_led_set_battery(system_get_board_version());
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/oak/usb_pd_policy.c b/board/oak/usb_pd_policy.c
deleted file mode 100644
index a4e62ebe88..0000000000
--- a/board/oak/usb_pd_policy.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
-	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-__override int pd_board_checks(void)
-{
-#if BOARD_REV <= OAK_REV3
-	/* wake up VBUS task to check vbus change */
-	task_wake(TASK_ID_VBUS);
-#endif
-	return EC_SUCCESS;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since 5V power source is off */
-	return gpio_get_level(GPIO_5V_POWER_GOOD);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-	board_typec_dp_set(port, 1);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int cur_lvl;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-
-	dp_status[port] = payload[1];
-	cur_lvl = gpio_get_level(GPIO_USB_DP_HPD);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-	if (irq & cur_lvl) {
-		board_typec_dp_on(port);
-	} else if (irq & !cur_lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	} else {
-		board_typec_dp_set(port, lvl);
-	}
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	board_typec_dp_off(port, dp_flags);
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/oak/vif_override.xml b/board/oak/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/oak/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/palkia/battery.c b/board/palkia/battery.c
deleted file mode 100644
index 76e58aa618..0000000000
--- a/board/palkia/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Palkia battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Simplo Battery Information */
-	[BATTERY_DYNAPACK_UX48144] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GVQC3KC",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 17600, /* mV */
-			.voltage_normal		= 15400, /* mV */
-			.voltage_min		= 12000,  /* mV */
-			.precharge_current	= 444,   /* mA */
-			.start_charging_min_c	= 1,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 1,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_UX48144;
diff --git a/board/palkia/board.c b/board/palkia/board.c
deleted file mode 100644
index 7586478724..0000000000
--- a/board/palkia/board.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Palkia board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static const uint8_t actual_key_mask[KEYBOARD_COLS_MAX] = {
-	0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff,
-	0xff, 0xff, 0x03, 0xfd, 0x48, 0x03, 0xff,
-	0xf7, 0x16  /* full set */
-};
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-void board_config_pre_init(void)
-{
-	int i;
-
-	/* override the keyscan key mask */
-	for (i = 0; i < KEYBOARD_COLS_MAX; ++i)
-		keyscan_config.actual_key_mask[i] = actual_key_mask[i];
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void board_lid_interrupt(enum gpio_signal signal)
-{
-	static int board_id = -1;
-
-	if (board_id == -1) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) == EC_SUCCESS)
-			board_id = val;
-	}
-
-	lid_interrupt(signal);
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	}
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Palkia temperature control thresholds */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(60),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(65),
-	.temp_fan_max = C_TO_K(80),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-int board_tcpc_post_init(int port)
-{
-	int rv = EC_SUCCESS;
-
-	if (port == USB_PD_PORT_TCPC_0)
-		/* Set MUX_DP_EQ to 3.6dB (0x98) */
-		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-
-	return rv;
-}
-
-bool board_is_convertible(void)
-{
-	return false;
-}
diff --git a/board/palkia/board.h b/board/palkia/board.h
deleted file mode 100644
index 3e1baf8a4f..0000000000
--- a/board/palkia/board.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Palkia board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_KEYBOARD_CUSTOMIZATION
-
-/* Enable board_config_pre_init() */
-#define CONFIG_BOARD_PRE_INIT
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY 0
-#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_LOW_PWR_ODL
-
-/*
- * Palkia' battery takes several seconds to come back out of its disconnect
- * state (~4.2 seconds on the unit I have, so give it a little more for margin).
- */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* DPTF */
-#define CONFIG_DPTF_MULTI_PROFILE
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_4,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_UX48144,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/palkia/build.mk b/board/palkia/build.mk
deleted file mode 100644
index cf0939b776..0000000000
--- a/board/palkia/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_KEYBOARD_CUSTOMIZATION)+=keyboard_customization.o
diff --git a/board/palkia/ec.tasklist b/board/palkia/ec.tasklist
deleted file mode 100644
index be39ae64a2..0000000000
--- a/board/palkia/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-
diff --git a/board/palkia/gpio.inc b/board/palkia/gpio.inc
deleted file mode 100644
index ec7ce25538..0000000000
--- a/board/palkia/gpio.inc
+++ /dev/null
@@ -1,119 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, board_lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,      PIN(9, 7), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_HIGH)
-GPIO(USB_A_LOW_PWR_ODL,        PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO4,                 PIN(1, 5), GPIO_OUT_LOW)        /* KSO_04 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0xDF), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_02-03,05-09 */
-ALTERNATE(PIN_MASK(0, 0xE8), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x0C), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14-15 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                             /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)                             /* ADC0, ADC1, ADC2, ADC3 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/palkia/keyboard_customization.c b/board/palkia/keyboard_customization.c
deleted file mode 100644
index 706ad18a4e..0000000000
--- a/board/palkia/keyboard_customization.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "keyboard_customization.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "keyboard_raw.h"
-
-static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c},
-	{0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000},
-	{0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076},
-	{0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b},
-	{0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b},
-	{0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b},
-	{0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042},
-	{0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000},
-	{0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c},
-	{0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023},
-	{0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-};
-
-uint16_t get_scancode_set2(uint8_t row, uint8_t col)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		return scancode_set2[col][row];
-	return 0;
-}
-
-void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		scancode_set2[col][row] = val;
-}
-
-void board_keyboard_drive_col(int col)
-{
-	/* Drive all lines to high */
-	if (col == KEYBOARD_COLUMN_NONE)
-		gpio_set_level(GPIO_KBD_KSO4, 0);
-
-	/* Set KBSOUT to zero to detect key-press */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		gpio_set_level(GPIO_KBD_KSO4, 1);
-
-	/* Drive one line for detection */
-	else {
-		if (col == 4)
-			gpio_set_level(GPIO_KBD_KSO4, 1);
-		else
-			gpio_set_level(GPIO_KBD_KSO4, 0);
-	}
-}
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{'c',        KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'q',        KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB,   '`',
-		'1',        KLLI_UNKNO, 'a'},
-	{KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_SPACE, 'e',        KLLI_F4,
-		KLLI_SEARC, '3',        KLLI_F3,    KLLI_UNKNO},
-	{'x',        'z',        KLLI_F2,    KLLI_F1,
-		's',        '2',        'w',        KLLI_ESC},
-	{'v',        'b',        'g',        't',
-		'5',        '4',        'r',        'f'},
-	{'m',        'n',        'h',        'y',
-		'6',        '7',        'u',        'j'},
-	{'.',        KLLI_DOWN,  '\\',       'o',
-		KLLI_F10,   '9',        KLLI_UNKNO, 'l'},
-	{KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{',',        KLLI_UNKNO, KLLI_F7,    KLLI_F6,
-		KLLI_F5,    '8',        'i',        'k'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT,  KLLI_UNKNO},
-	{KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'/',        KLLI_UP,    '-',        KLLI_UNKNO,
-		'0',        'p',        '[',        ';'},
-	{'\'',       KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO,
-		'=',        KLLI_B_SPC, ']',        'd'},
-	{KLLI_UNKNO, KLLI_F8,    KLLI_RIGHT, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-};
-
-char get_keycap_label(uint8_t row, uint8_t col)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		return keycap_label[col][row];
-	return KLLI_UNKNO;
-}
-
-void set_keycap_label(uint8_t row, uint8_t col, char val)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		keycap_label[col][row] = val;
-}
-#endif
diff --git a/board/palkia/keyboard_customization.h b/board/palkia/keyboard_customization.h
deleted file mode 100644
index 37ce1cf61f..0000000000
--- a/board/palkia/keyboard_customization.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard configuration */
-
-#ifndef __KEYBOARD_CUSTOMIZATION_H
-#define __KEYBOARD_CUSTOMIZATION_H
-
-/*
- * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
- * exact spaces for arrays. Actual keyboard scanning is done using
- * keyboard_cols, which holds a runtime column size.
- */
-#define KEYBOARD_COLS_MAX 16
-#define KEYBOARD_ROWS 8
-
-/*
- * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
- * instead. It checks whether you're eligible or not.
- */
-extern uint8_t keyboard_cols;
-
-#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
-
-/* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	8
-#define KEYBOARD_ROW_DOWN	1
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	5
-#define KEYBOARD_ROW_ESC	7
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	7
-#define KEYBOARD_ROW_KEY_H	2
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	6
-#define KEYBOARD_ROW_KEY_R	6
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	3
-#define KEYBOARD_ROW_LEFT_ALT	1
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	4
-#define KEYBOARD_ROW_REFRESH	6
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	3
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	8
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	4
-#define KEYBOARD_COL_LEFT_CTRL  12
-#define KEYBOARD_ROW_LEFT_CTRL  1
-#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
-#define KEYBOARD_COL_RIGHT_CTRL 12
-#define KEYBOARD_ROW_RIGHT_CTRL 0
-#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     2
-#define KEYBOARD_ROW_SEARCH     3
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      13
-#define KEYBOARD_ROW_KEY_0      4
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      2
-#define KEYBOARD_ROW_KEY_1      5
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      5
-#define KEYBOARD_ROW_KEY_2      5
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
-#define KEYBOARD_COL_LEFT_SHIFT 9
-#define KEYBOARD_ROW_LEFT_SHIFT 1
-#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
-
-#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/palkia/led.c b/board/palkia/led.c
deleted file mode 100644
index c7607960e5..0000000000
--- a/board/palkia/led.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Palkia
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/palkia/vif_override.xml b/board/palkia/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/palkia/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/pazquel/battery.c b/board/pazquel/battery.c
deleted file mode 100644
index 88a38255d0..0000000000
--- a/board/pazquel/battery.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* GanFeng SG20 Battery Information */
-	[BATTERY_GANFENG] = {
-		.fuel_gauge = {
-			.manuf_name = "Ganfeng",
-			.device_name = "SG20",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max        = 8700, /* mV */
-			.voltage_normal     = 7600, /* mV */
-			.voltage_min        = 6000, /* mV */
-			.precharge_current  = 256,  /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c     = 0,
-			.charging_max_c     = 60,
-			.discharging_min_c  = -20,
-			.discharging_max_c  = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GANFENG;
diff --git a/board/pazquel/board.c b/board/pazquel/board.c
deleted file mode 100644
index 8d7e679190..0000000000
--- a/board/pazquel/board.c
+++ /dev/null
@@ -1,616 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void usba_oc_interrupt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-static void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * 1. launcher key mapped to (KSI_3, KSO_0):
-	 *    change actual_key_mask[0] = 0x14 to 0x1c
-	 * 2. T11 key not in keyboard (KSI_0,KSO_1):
-	 *    change actual_key_mask[1] from 0xff to 0xfe
-	 */
-	 .actual_key_mask = {
-         0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-	 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	 },
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-static void board_update_sensor_config_clamshell(void)
-{
-	motion_sensor_count = 0;
-	gmr_tablet_switch_disable();
-	/* The sensors are not stuffed; don't allow lines to float */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-}
-DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_clamshell,
-	     HOOK_PRIO_INIT_I2C + 2);
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-
-	/* Enable interrupt for BMI160 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_PG);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/pazquel/board.h b/board/pazquel/board.h
deleted file mode 100644
index 98f7ff2499..0000000000
--- a/board/pazquel/board.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
-#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_GANFENG,
-	BATTERY_TYPE_COUNT,
-};
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pazquel/build.mk b/board/pazquel/build.mk
deleted file mode 100644
index f03287a2ee..0000000000
--- a/board/pazquel/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=led.o
diff --git a/board/pazquel/ec.tasklist b/board/pazquel/ec.tasklist
deleted file mode 100644
index 5beeb38feb..0000000000
--- a/board/pazquel/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/pazquel/gpio.inc b/board/pazquel/gpio.inc
deleted file mode 100644
index 0d7e73fca2..0000000000
--- a/board/pazquel/gpio.inc
+++ /dev/null
@@ -1,187 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
- * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_OUT_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 0))
-UNUSED(PIN(D, 3))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/pazquel/led.c b/board/pazquel/led.c
deleted file mode 100644
index aabf33f3f0..0000000000
--- a/board/pazquel/led.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_W_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(LED_BLUE);
-	else if (brightness[EC_LED_COLOR_RED] != 0)
-		led_set_color(LED_RED);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	enum led_color color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_RED;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: Red 1 sec, off 3 sec */
-			period = (1 + 3) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* Discharging in S5: off */
-			color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* Discharging in S0: Blue on */
-			color = LED_BLUE;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Red 1 sec, off 1 sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_RED;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: Blue on */
-		color = LED_BLUE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Red 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_RED;
-		} else
-			color = LED_BLUE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_BLUE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/pazquel/vif_override.xml b/board/pazquel/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/pazquel/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md
deleted file mode 100644
index 4f1c8636c6..0000000000
--- a/board/pdeval-stm32f072/PD_evaluation.md
+++ /dev/null
@@ -1,177 +0,0 @@
-# USB PD chip evaluation configuration
-
-This board configuration implements a USB Power Delivery TCPM in order to
-evaluate various TCPC chips. The code tries to follow the preliminary USB PD
-interface standard but for TCPC chip implementing proprietary I2C protocol, a
-new TCPM file can be implemented as explained in the
-[Updating the code](#Updating-the-code) section below.
-
-## Building
-
-### Chromium OS chroot
-
-All the following instructions have been verified in a ChromiumOS chroot. You
-can find how to set one up on the Chromium development:
-[http://dev.chromium.org/chromium-os/quick-start-guide](http://dev.chromium.org/chromium-os/quick-start-guide)
-
-### Build the TCPM code
-
-`cd src/platform/ec`
-
-`make BOARD=pdeval-stm32f072`
-
-## Updating the code
-
-### TCPC Communication code
-
-Please duplicate [driver/tcpm/tcpci.c](../../driver/tcpm/tcpci.c) into
-**driver/tcpm/##chip#name##.c**. Then update the control logic through I2C
-there.
-
-In order for your new code to compile, you need to update
-[driver/build.mk](../../driver/build.mk) with the new file :
-`driver-$(CONFIG_USB_PD_TCPM_##CHIP#NAME##)+=tcpm/##chip#name##.o` then document
-the new `CONFIG_USB_PD_TCPM_` variable in the
-[include/config.h](../../include/config.h) file and define it in the board
-configuration in [board/pdeval-stm32f072/board.h](board.h).
-
-### Board configuration
-
-In [board/pdeval-stm32f072/board.h](board.h), you can update
-`CONFIG_USB_PD_PORT_MAX_COUNT` to the actual number of ports on your board. You
-also need to create/delete the corresponding `PD_Cx` tasks in
-[board/pdeval-stm32f072/ec.tasklist](ec.tasklist).
-
-By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running
-with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and
-0x9e. To change the pins or speed, you need to edit `i2c_ports` in
-[board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in
-[board/pdeval-stm32f072/board.h](board.h) with the right controller number, and
-change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change
-TCPC i2c slave addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
-[board/pdeval-stm32f072/board.h](board.h).
-
-The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have
-external pull-ups on those lines, you can activate the chip internal pull-ups
-(but they are a bit weak for I2C) by editing
-[board/pdeval-stm32f072/gpio.inc](gpio.inc) and updating the alternate mode
-configuration flags with `GPIO_PULL_UP` e.g. : `ALTERNATE(PIN_MASK(B, 0x00c0),
-1, MODULE_I2C, GPIO_PULL_UP) /* I2C MASTER:PB6/7 */`
-
-An interrupt line, PA1, is configured to be used for the TCPC to get the
-attention of the TCPM. The GPIO is configured to trigger an interrupt on the
-falling edge and will call `tcpc_alert()`, which must be implemented in
-**driver/tcpm/<vendor>.c**, and should determine the cause of the interrupt and
-take action. The GPIO can be changed in
-[board/pdeval-stm32f072/gpio.inc](gpio.inc).
-
-## Flashing and Running
-
-### Flashing the firmware binary
-
-To flash through JTAG with OpenOCD, you can just run:
-
-`sudo make flash BOARD=pdeval-stm32f072`
-
-Note: you need to do that with your USB mini-B cable is connected to the **USB
-ST-LINK** plug on the discovery board.
-
-### Connecting to the firmware console
-
-Connect a USB cable to the **USB USER** mini-B receptacle on the board. `lsusb`
-should show you a device with the following ID : 18d1:500f
-
-You can get a console over USB by issuing the following command on a Linux
-computer:
-
-`echo '18d1 500f' | sudo tee /sys/bus/usb-serial/drivers/generic/new_id`
-
-## Testing
-
-Currently, the TCPM is expecting to have a GPIO to detect VBUS, but to minimize
-the HW setup with the discovery board the alternative is to fake VBUS detection
-using either the **USER** button on the discovery board, or the `vbus` console
-command, both of which toggle the state of VBUS detected. For example, to make
-get a PD contract with a power adapter, plug in the adapter and then toggle VBUS
-on. When a PD contract above 6V is made, LED5 on the discovery board will light.
-To disconnect, toggle VBUS off.
-
-EC command line commands
-
--   `help` List all available EC console commands
--   `vbus` Toggle VBUS on/off
--   `pd <port> state` Print PD protocol state information
--   `pd <port> swap data` Request data role swap on port
--   `pd <port> swap power` Request power role swap on port
--   `i2cscan` Scan i2c bus for any responsive devices
--   `i2cxfer` Perform an i2c transaction
-
-On the console, you will the PD state machine transitioning through its states
-with traces like `C0 st5`. You can always the human readable name of the current
-state by doing `pd 0 state` returning something like : `Port C0 CC1, Ena - Role:
-SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608` else the numbering of the state is
-defined in [include/usb_pd.h](../../include/us_pd.h) by the `PD_STATE_`
-constants. It should be by default :
-
-```
-[0] DISABLED
-[1] SUSPENDED
-[2] SNK_DISCONNECTED
-[3] SNK_DISCONNECTED_DEBOUNCE
-[4] SNK_HARD_RESET_RECOVER
-[5] SNK_DISCOVERY
-[6] SNK_REQUESTED
-[7] SNK_TRANSITION
-[8] SNK_READY
-[9] SNK_SWAP_INIT
-[10] SNK_SWAP_SNK_DISABLE
-[11] SNK_SWAP_SRC_DISABLE
-[12] SNK_SWAP_STANDBY
-[13] SNK_SWAP_COMPLETE
-[14] SRC_DISCONNECTED
-[15] SRC_DISCONNECTED_DEBOUNCE
-[16] SRC_ACCESSORY
-[17] SRC_HARD_RESET_RECOVER
-[18] SRC_STARTUP
-[19] SRC_DISCOVERY
-[20] SRC_NEGOCIATE
-[21] SRC_ACCEPTED
-[22] SRC_POWERED
-[23] SRC_TRANSITION
-[24] SRC_READY
-[25] SRC_GET_SINK_CAP
-[26] DR_SWAP
-[27] SRC_SWAP_INIT
-[28] SRC_SWAP_SNK_DISABLE
-[29] SRC_SWAP_SRC_DISABLE
-[30] SRC_SWAP_STANDBY
-[31] SOFT_RESET
-[32] HARD_RESET_SEND
-[33] HARD_RESET_EXECUTE
-[34] BIST_RX
-[35] BIST_TX
-```
-
-## Known Issues
-
-1.  This doc is not finished yet ...
-
-2.  You might need a ChromeOS chroot ...
-
-## Troubleshooting
-
-1.  OpenOCD is not finding the device.
-
-    1.  Check that your USB mini-B cable is connected to the **USB ST-LINK**
-        plug on the discovery board.
-    2.  What color is the LD1 LED on the board ?
-
-1.  On the I2C bus, SDA/SCL lines are staying always low
-
-    1.  You might be missing some pull-up resistors on the bus.
-    1.  Check the [Board configuration](#Board-configuration) section if you
-        cannot add external pull-ups.
-
-1.  You got black smoke
-
-    1.  Time to buy a new one.
diff --git a/board/pdeval-stm32f072/board.c b/board/pdeval-stm32f072/board.c
deleted file mode 100644
index 8c62c10b79..0000000000
--- a/board/pdeval-stm32f072/board.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* STM32F072-discovery board based USB PD evaluation configuration */
-
-#include "common.h"
-#include "anx7447.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "usb_descriptor.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-void button_event(enum gpio_signal signal);
-
-void alert_event(enum gpio_signal signal)
-{
-	/* Exchange status with PD MCU. */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-}
-
-#include "gpio_list.h"
-
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("PDeval-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	gpio_enable_interrupt(GPIO_USER_BUTTON);
-	gpio_enable_interrupt(GPIO_PD_MCU_INT);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-}
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"tcpc", I2C_PORT_TCPC, 400 /* kHz */, GPIO_I2C0_SCL, GPIO_I2C0_SDA}
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC,
-			.addr_flags = AN7447_TCPC3_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_PD_MCU_INT)) {
-		status = PD_STATUS_TCPC_ALERT_0;
-	}
-
-	return status;
-}
diff --git a/board/pdeval-stm32f072/board.h b/board/pdeval-stm32f072/board.h
deleted file mode 100644
index e0b364e2c9..0000000000
--- a/board/pdeval-stm32f072/board.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32F072-discovery board based USB PD evaluation configuration */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-/* USB Power Delivery configuration */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_MUX
-
-#undef CONFIG_USB_PD_INITIAL_DRP_STATE
-#define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_TOGGLE_ON
-
-#undef CONFIG_USB_PD_PULLUP
-#define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
-
-/* fake board specific type-C power constants */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 650000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* I2C master port connected to the TCPC */
-#define I2C_PORT_TCPC 0
-#define I2C_PORT_PD_MCU 0
-
-/* Timer selection */
-
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-/* delay to turn on/off vconn */
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x500f
-#define CONFIG_USB_CONSOLE
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL 0
-#define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
-
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-
-	USB_STR_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __BOARD_H */
diff --git a/board/pdeval-stm32f072/build.mk b/board/pdeval-stm32f072/build.mk
deleted file mode 100644
index ef1346d534..0000000000
--- a/board/pdeval-stm32f072/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o usb_pd_policy.o
diff --git a/board/pdeval-stm32f072/ec.tasklist b/board/pdeval-stm32f072/ec.tasklist
deleted file mode 100644
index 5003fc7ba1..0000000000
--- a/board/pdeval-stm32f072/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PDCMD, pd_command_task,NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/pdeval-stm32f072/gpio.inc b/board/pdeval-stm32f072/gpio.inc
deleted file mode 100644
index 5409077c34..0000000000
--- a/board/pdeval-stm32f072/gpio.inc
+++ /dev/null
@@ -1,36 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USER_BUTTON, PIN(A, 0), GPIO_INT_FALLING, button_event)
-GPIO_INT(PD_MCU_INT,  PIN(A, 1), GPIO_INT_FALLING, alert_event)
-
-/* Outputs */
-GPIO(LED_U, PIN(C, 6), GPIO_OUT_LOW)
-GPIO(LED_D, PIN(C, 7), GPIO_OUT_LOW)
-GPIO(LED_L, PIN(C, 8), GPIO_OUT_LOW)
-GPIO(LED_R, PIN(C, 9), GPIO_OUT_LOW)
-GPIO(USB_C0_DVDDIO, PIN(C, 14), GPIO_OUT_HIGH)
-GPIO(USB_C0_AVDD33, PIN(C, 15), GPIO_OUT_HIGH)
-GPIO(VBUS_PMIC_CTRL, PIN(A, 4), GPIO_OUT_LOW)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL, PIN(B, 6),  GPIO_INPUT)
-GPIO(I2C0_SDA, PIN(B, 7),  GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA09/PA10 */
-ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART,  0) /* USART2: PA14/PA15 */
-ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,   0) /* I2C MASTER:PB6/7 */
diff --git a/board/pdeval-stm32f072/openocd-flash.cfg b/board/pdeval-stm32f072/openocd-flash.cfg
deleted file mode 100644
index ec32416934..0000000000
--- a/board/pdeval-stm32f072/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/stm32f0discovery.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/pdeval-stm32f072/usb_pd_policy.c b/board/pdeval-stm32f072/usb_pd_policy.c
deleted file mode 100644
index 2f7941321b..0000000000
--- a/board/pdeval-stm32f072/usb_pd_policy.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "anx7447.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
-
-/* Used to fake VBUS presence since no GPIO is available to read VBUS */
-static int vbus_present;
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 900, PDO_FIXED_FLAGS),
-		PDO_BATT(5000, 21000, 30000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver    = &anx7447_usb_mux_driver,
-	},
-};
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	anx7447_board_charging_enable(port, 0);
-
-	/* Provide VBUS */
-	gpio_set_level(GPIO_VBUS_PMIC_CTRL, 1);
-	anx7447_set_power_supply_ready(port);
-
-	/* notify host of power info change */
-
-	CPRINTS("Enable VBUS, port%d", port);
-
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	anx7447_power_supply_reset(port);
-	gpio_set_level(GPIO_VBUS_PMIC_CTRL, 0);
-	CPRINTS("Disable VBUS, port%d", port);
-
-	/* Enable charging */
-	anx7447_board_charging_enable(port, 1);
-}
-#else
-int pd_set_power_supply_ready(int port)
-{
-	/* Turn on the "up" LED when we output VBUS */
-	gpio_set_level(GPIO_LED_U, 1);
-	CPRINTS("Power supply ready/%d", port);
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Turn off the "up" LED when we shutdown VBUS */
-	gpio_set_level(GPIO_LED_U, 0);
-	/* Disable VBUS */
-	CPRINTS("Disable VBUS", port);
-}
-#endif /* CONFIG_USB_PD_TCPM_ANX7447 */
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	CPRINTS("USBPD current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
-	/* do some LED coding of the power we can sink */
-	if (max_ma) {
-		if (supply_voltage > 6500)
-			gpio_set_level(GPIO_LED_R, 1);
-		else
-			gpio_set_level(GPIO_LED_L, 1);
-	} else {
-		gpio_set_level(GPIO_LED_L, 0);
-		gpio_set_level(GPIO_LED_R, 0);
-	}
-}
-
-__override void typec_set_input_current_limit(int port, uint32_t max_ma,
-					      uint32_t supply_voltage)
-{
-	CPRINTS("TYPEC current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
-	gpio_set_level(GPIO_LED_R, !!max_ma);
-}
-
-void button_event(enum gpio_signal signal)
-{
-	vbus_present = !vbus_present;
-	CPRINTS("VBUS %d", vbus_present);
-}
-
-static int command_vbus_toggle(int argc, char **argv)
-{
-	vbus_present = !vbus_present;
-	CPRINTS("VBUS %d", vbus_present);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle,
-			"",
-			"Toggle VBUS detected");
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return vbus_present;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/* Always allow data swap */
-	return 1;
-}
-
-#ifdef CONFIG_USBC_VCONN_SWAP
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * Allow vconn swap as long as we are acting as a dual role device,
-	 * otherwise assume our role is fixed (not in S0 or console command
-	 * to fix our role).
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON;
-}
-#endif
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-}
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(1, /* data caps as USB host */
-				 0, /* data caps as USB device */
-				 IDH_PTYPE_PERIPH,
-				 0, /* supports alt modes */
-				 0x0000);
-
-const uint32_t vdo_product = VDO_PRODUCT(0x0000, 0x0000);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	return VDO_I(PRODUCT) + 1;
-}
-
-__override const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override void svdm_safe_dp_mode(int port)
-{
-	/* make DP interface safe until configure */
-	dp_flags[port] = 0;
-	/*
-	 * board_set_usb_mux(port, USB_PD_MUX_NONE,
-	 * polarity_rm_dts(pd_get_polarity(port)));
-	 */
-}
-
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	bool unused;
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-	const struct usb_mux *mux = &usb_muxes[port];
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-	mux_state_t mux_state = USB_PD_MUX_NONE;
-	if (polarity_rm_dts(pd_get_polarity(port)))
-		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-#endif
-
-	CPRINTS("pin_mode = %d", pin_mode);
-	if (!pin_mode)
-		return 0;
-
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-	switch (pin_mode) {
-	case MODE_DP_PIN_A:
-	case MODE_DP_PIN_C:
-	case MODE_DP_PIN_E:
-		mux_state |= USB_PD_MUX_DP_ENABLED;
-		/*
-		 * Note: Direct mux driver calls are deprecated.  Calls
-		 * should go through the usb_mux APIs instead.
-		 */
-		mux->driver->set(mux, mux_state, &unused);
-		break;
-	case MODE_DP_PIN_B:
-	case MODE_DP_PIN_D:
-	case MODE_DP_PIN_F:
-		mux_state |= USB_PD_MUX_DOCK;
-		mux->driver->set(mux, mux_state, &unused);
-		break;
-	}
-#endif
-
-	/*
-	 * board_set_usb_mux(port, USB_PD_MUX_DP_ENABLED,
-	 * polarity_rm_dts(pd_get_polarity(port)));
-	 */
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-}
-
-__override void svdm_dp_post_config(int port)
-{
-	const struct usb_mux *mux = &usb_muxes[port];
-
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-	/* Note: Usage is deprecated, use usb_mux_hpd_update instead */
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_ANX7447))
-		anx7447_tcpc_update_hpd_status(mux, USB_PD_MUX_HPD_LVL |
-					       USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	const struct usb_mux *mux = &usb_muxes[port];
-	mux_state_t mux_state = (lvl ? USB_PD_MUX_HPD_LVL :
-				 USB_PD_MUX_HPD_LVL_DEASSERTED) |
-				(irq ? USB_PD_MUX_HPD_IRQ :
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-
-	/* Note: Usage is deprecated, use usb_mux_hpd_update instead */
-	CPRINTS("Attention: 0x%x", payload[1]);
-	anx7447_tcpc_update_hpd_status(mux, mux_state);
-#endif
-	dp_status[port] = payload[1];
-
-	/* ack */
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-	anx7447_tcpc_clear_hpd_status(port);
-#endif
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/pdeval-stm32f072/vif_override.xml b/board/pdeval-stm32f072/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/pdeval-stm32f072/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/phaser/battery.c b/board/phaser/battery.c
deleted file mode 100644
index 2e1f77d552..0000000000
--- a/board/phaser/battery.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all phaser battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* SMP 5B10Q13163 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC 5B10Q13162  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 181,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/phaser/board.c b/board/phaser/board.c
deleted file mode 100644
index 488880c1fc..0000000000
--- a/board/phaser/board.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Phaser board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/anx7447.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usbc_ppc.h"
-#include "util.h"
-#include "battery_smart.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
-
-static uint8_t sku_id;
-static bool support_syv_ppc;
-
-/* Check PPC ID and board version to decide which one ppc is used. */
-static bool board_is_support_syv_ppc(void)
-{
-	uint32_t board_version = 0;
-
-	if (cbi_get_board_version(&board_version) != EC_SUCCESS)
-		CPRINTSUSB("Get board version failed.");
-
-	if ((board_version >= 5) && (gpio_get_level(GPIO_PPC_ID)))
-		return true;
-
-	return false;
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		if (support_syv_ppc)
-			syv682x_interrupt(0);
-		else
-			nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		if (support_syv_ppc)
-			syv682x_interrupt(1);
-		else
-			nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		/* We only use 2g because its resolution is only 8-bits */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &standard_rot_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &standard_rot_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int board_is_convertible(void)
-{
-	return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 || \
-		sku_id == 255;
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-static void cbi_init(void)
-{
-	uint32_t val;
-
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	ccprints("SKU: 0x%04x", sku_id);
-
-	board_update_sensor_config_from_sku();
-
-	support_syv_ppc = board_is_support_syv_ppc();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (board_is_convertible())
-		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-int board_is_lid_angle_tablet_mode(void)
-{
-	return board_is_convertible();
-}
-
-/* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
-/* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
-/* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
-
-static void sb_quick_charge_mode(int enable)
-{
-	int val, rv;
-
-	rv = sb_read(SB_BATTERY_MODE, &val);
-	if (rv || !(val & MODE_QUICK_CHARGE_SUPPORT))
-		return;
-
-	rv = sb_read(SB_OPTIONALMFG_FUNCTION2, &val);
-	if (rv)
-		return;
-
-	if (enable)
-		val |= SMART_QUICK_CHARGE;
-	else
-		val &= ~SMART_QUICK_CHARGE;
-
-	sb_write(SB_OPTIONALMFG_FUNCTION2, val);
-}
-
-/* Called on AP S3/S0ix -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Normal charge current */
-	sb_quick_charge_mode(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3/S0ix transition */
-static void board_chipset_suspend(void)
-{
-	/* Quick charge current */
-	sb_quick_charge_mode(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
-
-static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-};
-
-static void board_setup_ppc(void)
-{
-	if (!support_syv_ppc)
-		return;
-
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
-
-	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
-	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
-}
-DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
-
-int ppc_get_alert_status(int port)
-{
-	if (port == 0)
-		return gpio_get_level(GPIO_USB_PD_C0_INT_ODL) == 0;
-
-	return gpio_get_level(GPIO_USB_PD_C1_INT_ODL) == 0;
-}
diff --git a/board/phaser/board.h b/board/phaser/board.h
deleted file mode 100644
index 33a84373f6..0000000000
--- a/board/phaser/board.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Phaser board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-#define CONFIG_LED_COMMON
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Additional PPC second source */
-#define CONFIG_USBC_PPC_SYV682X
-#define	CONFIG_USBC_PPC_DEDICATED_INT
-#undef	CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-/* SYV682 isn't connected to CC, so TCPC must provide VCONN */
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
-	ADC_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_PANASONIC,
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/phaser/build.mk b/board/phaser/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/phaser/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/phaser/ec.tasklist b/board/phaser/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/phaser/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
deleted file mode 100644
index 639ed914b6..0000000000
--- a/board/phaser/gpio.inc
+++ /dev/null
@@ -1,199 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL, PIN(4, 0), GPIO_INT_BOTH, button_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,  PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,    PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_PD_RST,	    PIN(8, 3), GPIO_OUT_LOW)	/* C0 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* LED */
-GPIO(BAT_LED_RED_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_GREEN_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(PWR_LED_WHITE_L,	 PIN(D, 7), GPIO_OUT_HIGH)	/* LED_3_L */
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(KB_BL_PWR_EN)
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,           PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,           PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,           PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Camera */
-GPIO(EC_GPIO_03,	 PIN(0, 3), GPIO_INPUT)		/* TP only */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Misc. */
-GPIO(CCD_MODE_EC_L,	 PIN(E, 3), GPIO_INPUT)
-GPIO(TRACKPAD_INT_1V8_ODL,	PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(PPC_ID,		PIN(9, 7), GPIO_INPUT | GPIO_PULL_DOWN)	/* PPC ID Pin */
-
-/* Unused pins */
-GPIO(CHARGER_PMON,	PIN(4, 2), GPIO_INPUT)
-GPIO(CHARGER_IADP,	PIN(4, 3), GPIO_INPUT)
-GPIO(EC_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)	/* TP Only */
-GPIO(EC_I2S_SFRM,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_SCLK,	PIN(A, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2S_TX_PCH_RX,	PIN(B, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_14 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)         /* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)         /* ADC9 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* PWM3: KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/phaser/led.c b/board/phaser/led.c
deleted file mode 100644
index 6ef2d786c0..0000000000
--- a/board/phaser/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Phaser
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/phaser/vif_override.xml b/board/phaser/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/phaser/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/pico/battery.c b/board/pico/battery.c
deleted file mode 100644
index 6f6b49899a..0000000000
--- a/board/pico/battery.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* Panasonic AP19B5K Battery Information */
-	[BATTERY_PANASONIC_AP19B5K_KT00305011] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305011",
-			.device_name = "AP19B5K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP19B8K Battery Information */
-	 [BATTERY_LGC_AP19B8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G022",
-			.device_name = "AP19B8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* COSMX AP20CBL Battery Information */
-	 [BATTERY_COSMX_AP20CBL] = {
-		.fuel_gauge = {
-			.manuf_name = "COSMX KT0030B002",
-			.device_name = "AP20CBL",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* SMP AP18C7K Battery Information */
-	 [BATTERY_SMP_AP18C7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP KT00307010",
-			.device_name = "AP18C7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/pico/board.c b/board/pico/board.c
deleted file mode 100644
index e930c7c998..0000000000
--- a/board/pico/board.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .default_range = 2, /* g, enough to calculate lid angle. */
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static bool board_is_convertible(void)
-{
-	int sku = system_get_sku_id();
-
-	return sku == 1 || sku == 2;
-}
-
-int board_sensor_at_360(void)
-{
-	if (board_is_convertible())
-		return !gpio_get_level(GMR_TABLET_MODE_GPIO_L);
-
-	return 0;
-}
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1},
-	{GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3},
-	{GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4},
-	{GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5},
-	{GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7},
-	{GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1},
-	{GPIO_KSO_H, 6}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH1},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH2},
-	[ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec",   IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA},
-	{"sensor",  IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA},
-	{"battery", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/******************************************************************************/
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it8xxx2_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-#define VBUS_THRESHOLD_MV 4200
-int pd_snk_is_vbus_provided(int port)
-{
-	/* This board has only one port. */
-	if (!port)
-		return adc_read_channel(ADC_VBUS) > VBUS_THRESHOLD_MV ? 1 : 0;
-	else
-		return 0;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_motion_init(void)
-{
-	if (!board_is_convertible()) {
-		/* Disable motion sense. */
-		motion_sensor_count = 0;
-		gpio_disable_interrupt(GPIO_ACCEL_INT_ODL);
-		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT);
-		/* Disable tablet mode. */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		gmr_tablet_switch_disable();
-		gpio_set_flags(GPIO_TABLET_MODE_L,
-				GPIO_INPUT | GPIO_PULL_UP);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_motion_init, HOOK_PRIO_DEFAULT + 1);
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/pico/board.h b/board/pico/board.h
deleted file mode 100644
index ff02019f42..0000000000
--- a/board/pico/board.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_IT81202
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-/* TODO: remove me once we fix IT83XX_ILM_BLOCK_SIZE out of space issue */
-#undef CONFIG_LTO
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_KX022      /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_GMR_TABLET_MODE_CUSTOM
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               IT83XX_I2C_CH_C
-#define I2C_PORT_TCPC0              IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX            IT83XX_I2C_CH_C
-#define I2C_PORT_CHARGER            IT83XX_I2C_CH_A
-#define I2C_PORT_SENSORS            IT83XX_I2C_CH_B
-#define I2C_PORT_ACCEL              I2C_PORT_SENSORS
-#define I2C_PORT_BATTERY            IT83XX_I2C_CH_A
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_LED_ONOFF_STATES
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_PANASONIC_AP19B5K_KT00305011,
-	BATTERY_LGC_AP19B8K,
-	BATTERY_COSMX_AP20CBL,
-	BATTERY_SMP_AP18C7K,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* support factory keyboard test */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
-extern const int keyboard_factory_scan_pins[][2];
-extern const int keyboard_factory_scan_pins_used;
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for AP jump to BL */
-void emmc_ap_jump_to_bl(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-/* Motion sensor interrupt */
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pico/build.mk b/board/pico/build.mk
deleted file mode 100644
index 9ca7933e2a..0000000000
--- a/board/pico/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# IC is ITE IT81202
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/pico/ec.tasklist b/board/pico/ec.tasklist
deleted file mode 100644
index 5c272d04f4..0000000000
--- a/board/pico/ec.tasklist
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280)
diff --git a/board/pico/gpio.inc b/board/pico/gpio.inc
deleted file mode 100644
index 34ac5cf7af..0000000000
--- a/board/pico/gpio.inc
+++ /dev/null
@@ -1,150 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(POWER_BUTTON_L,    PIN(E, 4), GPIO_INT_BOTH,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(F, 3), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(D, 3), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(J, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-	 bmi160_interrupt)
-GPIO_INT_RO(BOOTBLOCK_EN_L, PIN(J, 1), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         emmc_ap_jump_to_bl)
-GPIO_INT(SPI0_CS,           PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(E, 2), GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(E, 5), GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(J, 6), GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(C, 7), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(UART1_RX,          PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(TABLET_MODE_L,     PIN(J, 7), GPIO_INT_BOTH,
-	 gmr_tablet_switch_isr)
-/* Unimplemented interrupts */
-GPIO(VOLUME_DOWN_L,         PIN(D, 5), GPIO_INPUT)
-GPIO(VOLUME_UP_L,           PIN(D, 6), GPIO_INPUT)
-GPIO(ALS_RGB_INT_ODL,       PIN(F, 0), GPIO_INPUT)
-GPIO(LID_ACCEL_INT_ODL,     PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,          PIN(B, 6), GPIO_OUT_LOW)
-/* 1.8V PP or 1.8V OD output with external 10K PU  */
-GPIO(PMIC_WATCHDOG_L,       PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-/* OD output with 5VT (there is 5V internal PU on PWRKEY of MT6358) */
-GPIO(PMIC_EN_ODL,           PIN(E, 1), GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-/* EC programming */
-GPIO(I2C_E_SCL,              PIN(A, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_E_SDA,              PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-/* battery and charger */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT)
-/* sensor */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-/* typec */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT)
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT)
-
-/* Other input pins */
-/* TODO(WP_L): change to interrupt pin ? */
-GPIO(WP_L,                 PIN(I, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_FLASH_WP_ODL */
-GPIO(CCD_MODE_ODL,         PIN(C, 4), GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(C, 0), GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EN_USBA_5V,           PIN(B, 7), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 5), GPIO_ODR_HIGH)  /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)  /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(H, 5), GPIO_ODR_HIGH)  /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(J, 0), GPIO_ODR_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(H, 3), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC1_VCONN,  PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,  PIN(H, 2), GPIO_OUT_LOW)
-
-/* LEDs */
-GPIO(LED_BLUE,             PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(LED_GREEN,            PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(LED_ORANGE,           PIN(A, 0), GPIO_OUT_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(D, 0), GPIO_OUT_LOW)
-
-/* Unimplemented Pins  */
-GPIO(PG_PP5000_A_OD,       PIN(A, 6), GPIO_INPUT)
-GPIO(USB_A0_OC_ODL,        PIN(A, 7), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,       PIN(C, 3), GPIO_INPUT)
-GPIO(PMIC_FORCE_RESET_ODL, PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C0_PD_INT_ODL,    PIN(D, 1), GPIO_INPUT) /* no used on this board */
-GPIO(EN_PP5000A_USM,       PIN(D, 7), GPIO_INPUT)
-GPIO(EN_USBC_CHARGE_L,     PIN(F, 1), GPIO_INPUT)
-GPIO(EN_PP5000_USBC,       PIN(H, 4), GPIO_INPUT)
-GPIO(PP1800_H1_PG,         PIN(H, 6), GPIO_INPUT)
-
-/* NC pins, ensure they aren't in floating state. */
-GPIO(NC_GPA3,              PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPB2,              PIN(B, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPD2,              PIN(D, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPD4,              PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE0,              PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE3,              PIN(E, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPE7,              PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-/*
- * ADC pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPI5,              PIN(I, 5), GPIO_OUT_LOW)
-GPIO(NC_GPI7,              PIN(I, 7), GPIO_OUT_LOW)
-
-GPIO(NC_GPJ4,              PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPJ5,              PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-/*
- * GPG3,4,5,7 don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(NC_GPG0,              PIN(G, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-/* Don't touch GPG1 and GPG2 */
-GPIO(NC_GPG3,              PIN(G, 3), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_MOSI,    PIN(G, 4), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_MISO,    PIN(G, 5), GPIO_OUT_LOW)
-GPIO(EC_SPI_FLASH_CLK,     PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_SPI_FLASH_CS_L,    PIN(G, 7), GPIO_OUT_LOW)
-
-/* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO0-1, 3-7 */
-GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_LOW)	     /* KSO2 inverted */
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0x4F), 0, MODULE_ADC, 0)  /* ADC 0,1,2,3,6 */
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-/* EMMC SPI SLAVE M2:CLK, M3:CMD, M6:DATA0 */
-ALTERNATE(PIN_MASK(M, 0x4C), 0, MODULE_SPI_FLASH,  0)
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI for communication */
diff --git a/board/pico/led.c b/board/pico/led.c
deleted file mode 100644
index 076199b2ed..0000000000
--- a/board/pico/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Jacuzzi
- */
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_ORANGE, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_BLUE, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_GREEN, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_GREEN, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_BLUE, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_ORANGE, LED_OFF_LVL);
-		break;
-	}
-}
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	}
-}
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/pico/vif_override.xml b/board/pico/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/pico/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/pirika/battery.c b/board/pirika/battery.c
deleted file mode 100644
index 2da3296106..0000000000
--- a/board/pirika/battery.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all waddledee battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/*COSMX  CA14J43 Battery Information */
-	[BATTERY_CA14J43] = {
-		.fuel_gauge = {
-			.manuf_name = "PG01LJ3353",
-			.device_name = "CA14J43",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/*COSMX CA11J58 Battery Information */
-	[BATTERY_CA11J58] = {
-		.fuel_gauge = {
-			.manuf_name = "PG01NL3353",
-			.device_name = "CA11J58",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800, /* mV */
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_CA14J43;
diff --git a/board/pirika/board.c b/board/pirika/board.c
deleted file mode 100644
index a17d19bf88..0000000000
--- a/board/pirika/board.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-/* Use default keyboard scan config, because board didn't supply one */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * CONFIG_KEYBOARD_COL2_INVERTED is defined for passing the column 2
-	 * to H1 which inverts the signal. The signal passing through H1
-	 * adds more delay. Need a larger delay value. Otherwise, pressing
-	 * Refresh key will also trigger T key, which is in the next scanning
-	 * column line. See http://b/156007029.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config pirika_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &pirika_kb;
-}
-
-static void notify_c0_chips(void)
-{
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
-
-static int board_tusb544_set(const struct usb_mux *me,
-		mux_state_t mux_state)
-{
-	int  rv = EC_SUCCESS;
-	enum tusb544_conf usb_mode = 0;
-	/* USB */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
-		}
-		/* USB without DP */
-		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
-		}
-	}
-	/* DP without USB */
-	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
-	}
-	/* Nothing enabled */
-	else
-		return EC_SUCCESS;
-	/* Write the retimer config byte */
-	if (usb_mode == USB_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x15);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x11);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB_DP_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1F);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == USB_DP) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1B);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x33);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0x22);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0x22);
-	} else if (usb_mode == DP_INV) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1E);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-	} else if (usb_mode == DP) {
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1A);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x99);
-		rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x99);
-	}
-
-	return rv;
-}
-
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_set,
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	},
-};
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable Base Accel interrupt */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	raa489000_hibernate(CHARGER_PRIMARY, true);
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(CHARGER_SECONDARY, true);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-}
-
-int board_set_active_charge_port(int port)
-{
-		int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (port == i)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct kionix_accel_data  g_kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Vcore",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-};
-const static struct ec_thermal_config thermal_vcore = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(53),
-	},
-};
-const static struct ec_thermal_config thermal_ambient = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(50),
-	},
-};
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1] = thermal_charger,
-	[TEMP_SENSOR_2] = thermal_vcore,
-	[TEMP_SENSOR_3] = thermal_ambient,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default. This cause Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
diff --git a/board/pirika/board.h b/board/pirika/board.h
deleted file mode 100644
index db119d5191..0000000000
--- a/board/pirika/board.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* System unlocked in early development */
-#undef CONFIG_SYSTEM_UNLOCKED
-
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000	/* C0 and C1: Charger */
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_THROTTLE_AP
-#define CONFIG_CHIPSET_CAN_THROTTLE
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_CA14J43,
-	BATTERY_CA11J58,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pirika/build.mk b/board/pirika/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/pirika/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/pirika/cbi_ssfc.c b/board/pirika/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/pirika/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/pirika/cbi_ssfc.h b/board/pirika/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/pirika/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/pirika/ec.tasklist b/board/pirika/ec.tasklist
deleted file mode 100644
index d6fa610141..0000000000
--- a/board/pirika/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/pirika/gpio.inc b/board/pirika/gpio.inc
deleted file mode 100644
index 90e6de2607..0000000000
--- a/board/pirika/gpio.inc
+++ /dev/null
@@ -1,145 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_R_ODL,                 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(LED_G_ODL,                 PIN(A, 2), GPIO_OUT_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)		/* ADC15: TEMP_SENSOR_3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
diff --git a/board/pirika/led.c b/board/pirika/led.c
deleted file mode 100644
index 2fe70f5fe8..0000000000
--- a/board/pirika/led.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_G_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	/* Battery error LED behavior as below:
-	 * S0: Blinking Amber LED, 1s on/ 1s off
-	 * S3/S5: following S3/S5 behavior
-	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
-	 */
-
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/pirika/usb_pd_policy.c b/board/pirika/usb_pd_policy.c
deleted file mode 100644
index b0e1098e4d..0000000000
--- a/board/pirika/usb_pd_policy.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/pirika/vif_override.xml b/board/pirika/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/pirika/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/plankton/board.c b/board/plankton/board.c
deleted file mode 100644
index a361f5fff3..0000000000
--- a/board/plankton/board.c
+++ /dev/null
@@ -1,798 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Plankton board configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ina2xx.h"
-#include "pca9534.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-void button_event(enum gpio_signal signal);
-void hpd_event(enum gpio_signal signal);
-void vbus_event(enum gpio_signal signal);
-#include "gpio_list.h"
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-static volatile int hpd_possible_irq;
-
-/* Detect the type of cable used (either single CC or double) */
-enum typec_cable {
-	TYPEC_CABLE_NONE,
-	TYPEC_CABLE_CHECK,
-	TYPEC_CABLE_SINGLE_CC,
-	TYPEC_CABLE_DOUBLE_CC
-};
-static enum typec_cable cable;
-
-static int active_cc;
-static int host_mode;
-static int drp_enable;
-
-static int sn75dp130_dpcd_init(void);
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DPSRC_HPD);
-	int dp_mode = !gpio_get_level(GPIO_USBC_SS_USB_MODE);
-
-	if (level != hpd_prev_level) {
-		/* Stable level changed. Send HPD event */
-		hpd_prev_level = level;
-		if (dp_mode)
-			pd_send_hpd(0, level ? hpd_high : hpd_low);
-		/* Configure redriver's back side */
-		if (level)
-			sn75dp130_dpcd_init();
-
-	}
-
-	/* Send queued IRQ if the cable is attached */
-	if (hpd_possible_irq && level && dp_mode)
-		pd_send_hpd(0, hpd_irq);
-	hpd_possible_irq = 0;
-
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-void hpd_event(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* Record low pulse */
-	if (cur_delta >= HPD_USTREAM_DEBOUNCE_IRQ && level)
-		hpd_possible_irq = 1;
-
-	/* store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data,
-			   HPD_USTREAM_DEBOUNCE_LVL);
-}
-
-/* Debounce time for voltage buttons */
-#define BUTTON_DEBOUNCE_US (100 * MSEC)
-
-static enum gpio_signal button_pressed;
-
-static int fake_pd_disconnected;
-static int fake_pd_host_mode;
-static int fake_pd_disconnect_duration_us;
-
-enum usbc_action {
-	USBC_ACT_5V_TO_DUT,
-	USBC_ACT_12V_TO_DUT,
-	USBC_ACT_20V_TO_DUT,
-	USBC_ACT_DEVICE,
-	USBC_ACT_USBDP_TOGGLE,
-	USBC_ACT_USB_EN,
-	USBC_ACT_DP_EN,
-	USBC_ACT_MUX_FLIP,
-	USBC_ACT_CABLE_POLARITY0,
-	USBC_ACT_CABLE_POLARITY1,
-	USBC_ACT_CCD_EN,
-	USBC_ACT_DRP_TOGGLE,
-
-	/* Number of USBC actions */
-	USBC_ACT_COUNT
-};
-
-enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] =
-{
-	[USBC_ACT_5V_TO_DUT] = SRC_CAP_5V,
-	[USBC_ACT_12V_TO_DUT] = SRC_CAP_12V,
-	[USBC_ACT_20V_TO_DUT] = SRC_CAP_20V,
-};
-
-/**
- * Set the active CC line. The non-active CC line will be left in
- * High-Z, and we will fake the ADC reading for it.
- */
-static void set_active_cc(int cc)
-{
-	active_cc = cc;
-
-	/*
-	 * If DRP mode is enabled, then set both CC lines based
-	 * on the current value of host_mode. If DRP mode is
-	 * disabled then only set the active CC line.
-	 */
-	/* Pull-up on CC2 */
-	gpio_set_flags(GPIO_USBC_CC2_HOST,
-		       ((cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
-	/* Pull-down on CC2 */
-	gpio_set_flags(GPIO_USBC_CC2_DEVICE_ODL,
-		       ((cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
-	/* Pull-up on CC1 */
-	gpio_set_flags(GPIO_USBC_CC1_HOST,
-		       ((!cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
-	/* Pull-down on CC1 */
-	gpio_set_flags(GPIO_USBC_CC1_DEVICE_ODL,
-		       ((!cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
-}
-
-/**
- * Detect type-C cable type. Toggle the active CC line until a type-C connection
- * is detected. If a type-C connection can be made in both polarities, then we
- * have a double CC cable, otherwise we have a single CC cable.
- */
-static void detect_cc_cable(void);
-DECLARE_DEFERRED(detect_cc_cable);
-
-static void detect_cc_cable(void)
-{
-	/*
-	 * Delay long enough to guarantee a type-C disconnect will be seen and
-	 * a new connection will be made made.
-	 */
-	hook_call_deferred(&detect_cc_cable_data,
-			   PD_T_CC_DEBOUNCE + PD_T_SAFE_0V);
-
-	switch (cable) {
-	case TYPEC_CABLE_NONE:
-		/* When no cable attached, toggle active CC line */
-		if (pd_is_connected(0))
-			cable = TYPEC_CABLE_CHECK;
-		set_active_cc(!active_cc);
-		break;
-	case TYPEC_CABLE_CHECK:
-		/* If we still have a connection, we have a double CC cable */
-		cable = pd_is_connected(0) ? TYPEC_CABLE_DOUBLE_CC :
-					     TYPEC_CABLE_SINGLE_CC;
-		/* Flip back to original polarity and enable PD comms */
-		set_active_cc(!active_cc);
-		pd_comm_enable(0, 1);
-		break;
-	case TYPEC_CABLE_SINGLE_CC:
-	case TYPEC_CABLE_DOUBLE_CC:
-		/* Check for disconnection and disable PD comms */
-		if (!pd_is_connected(0)) {
-			cable = TYPEC_CABLE_NONE;
-			pd_comm_enable(0, 0);
-		}
-		break;
-	}
-}
-
-static void fake_disconnect_end(void)
-{
-	fake_pd_disconnected = 0;
-	board_pd_set_host_mode(fake_pd_host_mode);
-
-	/* Restart CC cable detection */
-	hook_call_deferred(&detect_cc_cable_data, 500*MSEC);
-}
-DECLARE_DEFERRED(fake_disconnect_end);
-
-static void fake_disconnect_start(void)
-{
-	/* Cancel detection of CC cable */
-	hook_call_deferred(&detect_cc_cable_data, -1);
-
-	/* Record the current host mode */
-	fake_pd_host_mode = !gpio_get_level(GPIO_USBC_CHARGE_EN);
-	/* Disable VBUS */
-	gpio_set_level(GPIO_VBUS_CHARGER_EN, 0);
-	gpio_set_level(GPIO_USBC_VSEL_0, 0);
-	gpio_set_level(GPIO_USBC_VSEL_1, 0);
-	/* High Z for no pull-up or pull-down resistor on CC1 and CC2 */
-	gpio_set_flags(GPIO_USBC_CC2_HOST, GPIO_INPUT);
-	gpio_set_flags(GPIO_USBC_CC2_DEVICE_ODL, GPIO_INPUT);
-	gpio_set_flags(GPIO_USBC_CC1_HOST, GPIO_INPUT);
-	gpio_set_flags(GPIO_USBC_CC1_DEVICE_ODL, GPIO_INPUT);
-
-	fake_pd_disconnected = 1;
-
-	hook_call_deferred(&fake_disconnect_end_data,
-			   fake_pd_disconnect_duration_us);
-}
-DECLARE_DEFERRED(fake_disconnect_start);
-
-/**
- * Enable or disable dualrole mode operation. By default Plankton has
- * dualrole mode disabled and attempts to connect in a sink role. Console
- * commands/button presses can cause it to switch to source_only/sink_only
- * modes.
- */
-static void update_usbc_dual_role(int dual_role)
-{
-	if (dual_role == PD_DRP_TOGGLE_ON) {
-		drp_enable = 1;
-		/*
-		 * Cable detect is not needed when operating in dualrole mode
-		 * since both CC lines are used and SRC/SNK changes are dictated
-		 * by the USB PD protocol state machine.
-		 */
-		hook_call_deferred(&detect_cc_cable_data, -1);
-		/* Need to make sure both CC lines are set for SNK or SRC. */
-		set_active_cc(host_mode);
-		/* Ensure that PD communication is enabled. */
-		pd_comm_enable(0, 1);
-	} else {
-		drp_enable = 0;
-		/*
-		 * Dualrole mode is not active, resume cable detect function
-		 * which controls which CC line is active.
-		 */
-		hook_call_deferred(&detect_cc_cable_data, 0);
-	}
-	/* Update dual role setting used in USB PD protocol state machine */
-	pd_set_dual_role(0, dual_role);
-	cprintf(CC_USBPD, "DRP = %d, host_mode = %d\n", drp_enable, host_mode);
-}
-
-static void set_usbc_action(enum usbc_action act)
-{
-	int need_soft_reset;
-	int was_usb_mode;
-
-	switch (act) {
-	case USBC_ACT_5V_TO_DUT:
-	case USBC_ACT_12V_TO_DUT:
-	case USBC_ACT_20V_TO_DUT:
-		need_soft_reset = gpio_get_level(GPIO_VBUS_CHARGER_EN);
-		board_set_source_cap(src_cap_mapping[act]);
-		update_usbc_dual_role(PD_DRP_FORCE_SOURCE);
-		if (need_soft_reset)
-			pd_soft_reset();
-		break;
-	case USBC_ACT_DEVICE:
-		update_usbc_dual_role(PD_DRP_FORCE_SINK);
-		break;
-	case USBC_ACT_USBDP_TOGGLE:
-		was_usb_mode = gpio_get_level(GPIO_USBC_SS_USB_MODE);
-		gpio_set_level(GPIO_USBC_SS_USB_MODE, !was_usb_mode);
-		gpio_set_level(GPIO_CASE_CLOSE_EN, !was_usb_mode);
-		if (!gpio_get_level(GPIO_DPSRC_HPD))
-			break;
-		/*
-		 * DP cable is connected. Send HPD event according to USB/DP
-		 * mux state.
-		 */
-		if (!was_usb_mode) {
-			pd_send_hpd(0, hpd_low);
-		} else {
-			pd_send_hpd(0, hpd_high);
-			pd_send_hpd(0, hpd_irq);
-		}
-		break;
-	case USBC_ACT_USB_EN:
-		gpio_set_level(GPIO_USBC_SS_USB_MODE, 1);
-		break;
-	case USBC_ACT_DP_EN:
-		gpio_set_level(GPIO_USBC_SS_USB_MODE, 0);
-		break;
-	case USBC_ACT_MUX_FLIP:
-		/*
-		 * For a single CC cable, send custom VDM to flip
-		 * USB polarity only. For double CC cable, actually
-		 * disconnect and reconnect with opposite polarity.
-		 */
-		if (cable == TYPEC_CABLE_SINGLE_CC) {
-			pd_send_vdm(0, USB_VID_GOOGLE, VDO_CMD_FLIP, NULL, 0);
-			gpio_set_level(GPIO_USBC_POLARITY,
-				       !gpio_get_level(GPIO_USBC_POLARITY));
-		} else if (cable == TYPEC_CABLE_DOUBLE_CC) {
-			/*
-			 * Fake a disconnection for long enough to guarantee
-			 * that we disconnect.
-			 */
-			hook_call_deferred(&fake_disconnect_start_data, -1);
-			hook_call_deferred(&fake_disconnect_end_data, -1);
-			fake_pd_disconnect_duration_us = PD_T_SAFE_0V;
-			hook_call_deferred(&fake_disconnect_start_data, 0);
-			set_active_cc(!active_cc);
-		}
-		break;
-	case USBC_ACT_CABLE_POLARITY0:
-		gpio_set_level(GPIO_USBC_POLARITY, 0);
-		break;
-	case USBC_ACT_CABLE_POLARITY1:
-		gpio_set_level(GPIO_USBC_POLARITY, 1);
-		break;
-	case USBC_ACT_CCD_EN:
-		pd_send_vdm(0, USB_VID_GOOGLE, VDO_CMD_CCD_EN, NULL, 0);
-		/* Switch to USB mode when enable CCD. */
-		gpio_set_level(GPIO_USBC_SS_USB_MODE, 1);
-		/* Reset RFU polarity MUX */
-		gpio_set_level(GPIO_CASE_CLOSE_EN, 0);
-		gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 0);
-		gpio_set_level(GPIO_CASE_CLOSE_EN, 1);
-		gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 1);
-		break;
-	case  USBC_ACT_DRP_TOGGLE:
-		/* Toggle dualrole mode setting. */
-		update_usbc_dual_role(drp_enable ?
-				      PD_DRP_TOGGLE_OFF : PD_DRP_TOGGLE_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-/* has Pull-up */
-static int prev_dbg20v = 1;
-
-static void button_dbg20v_deferred(void);
-DECLARE_DEFERRED(button_dbg20v_deferred);
-
-static void enable_dbg20v_poll(void)
-{
-	hook_call_deferred(&button_dbg20v_deferred_data, 10 * MSEC);
-}
-
-/* Handle debounced button press */
-static void button_deferred(void)
-{
-	if (button_pressed == GPIO_DBG_20V_TO_DUT_L) {
-		enable_dbg20v_poll();
-		if (gpio_get_level(GPIO_DBG_20V_TO_DUT_L) == prev_dbg20v)
-			return;
-		else
-			prev_dbg20v = !prev_dbg20v;
-	}
-	/* bounce ? */
-	if (gpio_get_level(button_pressed) != 0)
-		return;
-
-	switch (button_pressed) {
-	case GPIO_DBG_5V_TO_DUT_L:
-		set_usbc_action(USBC_ACT_5V_TO_DUT);
-		break;
-	case GPIO_DBG_12V_TO_DUT_L:
-		set_usbc_action(USBC_ACT_12V_TO_DUT);
-		break;
-	case GPIO_DBG_20V_TO_DUT_L:
-		set_usbc_action(USBC_ACT_20V_TO_DUT);
-		break;
-	case GPIO_DBG_CHG_TO_DEV_L:
-		set_usbc_action(USBC_ACT_DEVICE);
-		break;
-	case GPIO_DBG_USB_TOGGLE_L:
-		set_usbc_action(USBC_ACT_USBDP_TOGGLE);
-		if (gpio_get_level(GPIO_USBC_SS_USB_MODE))
-			board_maybe_reset_usb_hub();
-		break;
-	case GPIO_DBG_MUX_FLIP_L:
-		set_usbc_action(USBC_ACT_MUX_FLIP);
-		break;
-	case GPIO_DBG_CASE_CLOSE_EN_L:
-		set_usbc_action(USBC_ACT_CCD_EN);
-		break;
-	default:
-		break;
-	}
-
-	ccprintf("Button %d = %d\n",
-		 button_pressed, gpio_get_level(button_pressed));
-}
-DECLARE_DEFERRED(button_deferred);
-
-void button_event(enum gpio_signal signal)
-{
-	button_pressed = signal;
-	/* reset debounce time */
-	hook_call_deferred(&button_deferred_data, BUTTON_DEBOUNCE_US);
-}
-
-static void button_dbg20v_deferred(void)
-{
-	if (gpio_get_level(GPIO_DBG_20V_TO_DUT_L) == 0)
-		button_event(GPIO_DBG_20V_TO_DUT_L);
-	else
-		enable_dbg20v_poll();
-}
-
-void vbus_event(enum gpio_signal signal)
-{
-	ccprintf("VBUS! =%d\n", gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-}
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master",  I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* 8-bit address */
-#define SN75DP130_I2C_ADDR_FLAGS 0x2e
-/*
- * Pin number for active-high reset from PCA9534 to CMOS pull-down to
- * SN75DP130's RSTN (active-low)
- */
-#define REDRIVER_RST_PIN  0x1
-
-static int sn75dp130_i2c_write(uint8_t index, uint8_t value)
-{
-	return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS,
-			  index, value);
-}
-
-/**
- * Reset redriver.
- *
- * Note, MUST set SW15 to 'PD' in order to control i2c from PD-MCU.  This can
- * NOT be done via software.
- */
-static int sn75dp130_reset(void)
-{
-	int rv;
-
-	rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, PCA9534_OUTPUT);
-	/* Assert (its active high) */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 1);
-	/* datasheet recommends > 100usec */
-	usleep(200);
-
-	/* De-assert */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 0);
-	/* datasheet recommends > 400msec */
-	usleep(450 * MSEC);
-	return rv;
-}
-
-static int sn75dp130_dpcd_init(void)
-{
-	int i, rv;
-
-	/* set upper & middle DPCD addr ... constant for writes below */
-	rv = sn75dp130_i2c_write(0x1c, 0x0);
-	rv |= sn75dp130_i2c_write(0x1d, 0x1);
-
-	/* link_bw_set: 5.4gbps */
-	rv |= sn75dp130_i2c_write(0x1e, 0x0);
-	rv |= sn75dp130_i2c_write(0x1f, 0x14);
-
-	/* lane_count_set: 4 */
-	rv |= sn75dp130_i2c_write(0x1e, 0x1);
-	rv |= sn75dp130_i2c_write(0x1f, 0x4);
-
-	/*
-	 * Force Link voltage level & pre-emphasis by writing each of the lane's
-	 * DPCD config registers 103-106h accordingly.
-	 */
-	for (i = 0x3; i < 0x7; i++) {
-		rv |= sn75dp130_i2c_write(0x1e, i);
-		rv |= sn75dp130_i2c_write(0x1f, 0x3);
-	}
-	return rv;
-}
-
-static int sn75dp130_redriver_init(void)
-{
-	int rv;
-
-	rv = sn75dp130_reset();
-
-	/* Disable squelch detect */
-	rv |= sn75dp130_i2c_write(0x3, 0x1a);
-	/* Disable link training on re-driver source side */
-	rv |= sn75dp130_i2c_write(0x4, 0x0);
-
-	/* Can only configure DPCD portion of redriver in presence of an HPD */
-	if (gpio_get_level(GPIO_DPSRC_HPD))
-		sn75dp130_dpcd_init();
-
-	return rv;
-}
-
-static int cmd_usbc_action(int argc, char *argv[])
-{
-	enum usbc_action act;
-
-	if (argc != 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "5v"))
-		act = USBC_ACT_5V_TO_DUT;
-	else if (!strcasecmp(argv[1], "12v"))
-		act = USBC_ACT_12V_TO_DUT;
-	else if (!strcasecmp(argv[1], "20v"))
-		act = USBC_ACT_20V_TO_DUT;
-	else if (!strcasecmp(argv[1], "ccd"))
-		act = USBC_ACT_CCD_EN;
-	else if (!strcasecmp(argv[1], "dev"))
-		act = USBC_ACT_DEVICE;
-	else if (!strcasecmp(argv[1], "usb"))
-		act = USBC_ACT_USB_EN;
-	else if (!strcasecmp(argv[1], "dp"))
-		act = USBC_ACT_DP_EN;
-	else if (!strcasecmp(argv[1], "flip"))
-		act = USBC_ACT_MUX_FLIP;
-	else if (!strcasecmp(argv[1], "pol0"))
-		act = USBC_ACT_CABLE_POLARITY0;
-	else if (!strcasecmp(argv[1], "pol1"))
-		act = USBC_ACT_CABLE_POLARITY1;
-	else if (!strcasecmp(argv[1], "drp"))
-		act = USBC_ACT_DRP_TOGGLE;
-	else
-		return EC_ERROR_PARAM1;
-
-	set_usbc_action(act);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(usbc_action, cmd_usbc_action,
-			"<5v|12v|20v|ccd|dev|usb|dp|flip|pol0|pol1|drp>",
-			"Set Plankton type-C port state");
-
-int board_in_hub_mode(void)
-{
-	int ret;
-	int level;
-
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 6, PCA9534_INPUT);
-	if (ret)
-		return -1;
-	ret = pca9534_get_level(I2C_PORT_MASTER, 0x20,
-				6, &level);
-	if (ret)
-		return -1;
-	return level;
-}
-
-static int board_usb_hub_reset(void)
-{
-	int ret;
-
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 7, PCA9534_OUTPUT);
-	if (ret)
-		return ret;
-	ret = pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				7, 0);
-	if (ret)
-		return ret;
-	usleep(100 * MSEC);
-	return pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				 7, 1);
-}
-
-void board_maybe_reset_usb_hub(void)
-{
-	if (board_in_hub_mode() == 1)
-		board_usb_hub_reset();
-}
-
-static int cmd_usb_hub_reset(int argc, char *argv[])
-{
-	return board_usb_hub_reset();
-}
-DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset,
-			NULL, "Reset USB hub");
-
-static void board_usb_hub_reset_no_return(void)
-{
-	board_usb_hub_reset();
-}
-DECLARE_DEFERRED(board_usb_hub_reset_no_return);
-
-static int board_pd_fake_disconnected(void)
-{
-	return fake_pd_disconnected;
-}
-
-int board_fake_pd_adc_read(int cc)
-{
-	if (fake_pd_disconnected) {
-		/* Always disconnected */
-		return fake_pd_host_mode ? 3000 : 0;
-	} else {
-		if (drp_enable) {
-			/* Always read the req CC line when in drp mode */
-			return adc_read_channel(cc ? ADC_CH_CC2_PD :
-						     ADC_CH_CC1_PD);
-		} else {
-			/*
-			 * Only read the active CC line, fake disconnected
-			 * on other CC line. */
-			if (active_cc == cc)
-				return adc_read_channel(cc ? ADC_CH_CC2_PD :
-							ADC_CH_CC1_PD);
-			else
-				return host_mode ? 3000 : 0;
-		}
-	}
-}
-
-/* Set fake PD pull-up/pull-down */
-static void board_update_fake_adc_value(int host_mode)
-{
-	fake_pd_host_mode = host_mode;
-}
-
-void board_pd_set_host_mode(int enable)
-{
-	if (!drp_enable)
-		cprintf(CC_USBPD, "Host mode: %d\n", enable);
-
-	if (board_pd_fake_disconnected()) {
-		board_update_fake_adc_value(enable);
-		return;
-	}
-
-	/* if host mode changed, reset cable type */
-	if (host_mode != enable) {
-		host_mode = enable;
-		cable = TYPEC_CABLE_NONE;
-	}
-
-	if (enable) {
-		/* Source mode, disable charging */
-		gpio_set_level(GPIO_USBC_CHARGE_EN, 0);
-
-		/* Set CC lines */
-		set_active_cc(active_cc);
-	} else {
-		/* Device mode, disable VBUS */
-		gpio_set_level(GPIO_VBUS_CHARGER_EN, 0);
-		gpio_set_level(GPIO_USBC_VSEL_0, 0);
-		gpio_set_level(GPIO_USBC_VSEL_1, 0);
-
-		/* Set CC lines */
-		set_active_cc(active_cc);
-
-		/* Enable charging */
-		gpio_set_level(GPIO_USBC_CHARGE_EN, 1);
-	}
-}
-
-static void board_init(void)
-{
-	timestamp_t now = get_time();
-	hpd_prev_level = gpio_get_level(GPIO_DPSRC_HPD);
-	hpd_prev_ts = now.val;
-	gpio_enable_interrupt(GPIO_DPSRC_HPD);
-
-	/* Start up with dualrole mode off */
-	drp_enable = 0;
-
-	/* Enable interrupts on VBUS transitions. */
-	gpio_enable_interrupt(GPIO_VBUS_WAKE);
-
-	/* Enable button interrupts. */
-	gpio_enable_interrupt(GPIO_DBG_5V_TO_DUT_L);
-	gpio_enable_interrupt(GPIO_DBG_12V_TO_DUT_L);
-	gpio_enable_interrupt(GPIO_DBG_CHG_TO_DEV_L);
-	gpio_enable_interrupt(GPIO_DBG_USB_TOGGLE_L);
-	gpio_enable_interrupt(GPIO_DBG_MUX_FLIP_L);
-	gpio_enable_interrupt(GPIO_DBG_CASE_CLOSE_EN_L);
-
-	/* TODO(crosbug.com/33761): poll DBG_20V_TO_DUT_L */
-	enable_dbg20v_poll();
-
-	ina2xx_init(0, 0x399f, INA2XX_CALIB_1MA(10 /* mOhm */));
-	sn75dp130_redriver_init();
-
-	/* Initialize USB hub */
-	if (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON)
-		hook_call_deferred(&board_usb_hub_reset_no_return_data,
-				   500 * MSEC);
-
-	/* Start detecting CC cable type */
-	hook_call_deferred(&detect_cc_cable_data, SECOND);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static int cmd_fake_disconnect(int argc, char *argv[])
-{
-	int delay_ms, duration_ms;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	delay_ms = strtoi(argv[1], &e, 0);
-	if (*e || delay_ms < 0)
-		return EC_ERROR_PARAM1;
-	duration_ms = strtoi(argv[2], &e, 0);
-	if (*e || duration_ms < 0)
-		return EC_ERROR_PARAM2;
-
-	/* Cancel any pending function calls */
-	hook_call_deferred(&fake_disconnect_start_data, -1);
-	hook_call_deferred(&fake_disconnect_end_data, -1);
-
-	fake_pd_disconnect_duration_us = duration_ms * MSEC;
-	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
-
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		 duration_ms, delay_ms);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
-			"<delay_ms> <duration_ms>", NULL);
-
-static void trigger_dfu_release(void)
-{
-	gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 1);
-	ccprintf("Deasserting CASE_CLOSE_DFU_L.\n");
-}
-DECLARE_DEFERRED(trigger_dfu_release);
-
-static int cmd_trigger_dfu(int argc, char *argv[])
-{
-	gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 0);
-	ccprintf("Asserting CASE_CLOSE_DFU_L.\n");
-	ccprintf("If you expect to see DFU debug but it doesn't show up,\n");
-	ccprintf("try flipping the USB type-C cable.\n");
-	hook_call_deferred(&trigger_dfu_release_data, 1500 * MSEC);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dfu, cmd_trigger_dfu, NULL, NULL);
diff --git a/board/plankton/board.h b/board/plankton/board.h
deleted file mode 100644
index 39ab706cd2..0000000000
--- a/board/plankton/board.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Plankton board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART2 (PA14/PA15) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_COMM_DISABLED
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DYNAMIC_SRC_CAP
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_ADC
-#define CONFIG_HW_CRC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_INA219
-#define CONFIG_IO_EXPANDER_PCA9534
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* I2C ports configuration */
-#define I2C_PORT_MASTER 1
-
-/* USB configuration */
-#define CONFIG_USB_PID 0x500c
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CH_CC1_PD = 0,
-	ADC_CH_CC2_PD,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum board_src_cap {
-	SRC_CAP_5V = 0,
-	SRC_CAP_12V,
-	SRC_CAP_20V,
-};
-
-/* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SNK_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
-
-/* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 5000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Set USB PD source capability */
-void board_set_source_cap(enum board_src_cap cap);
-
-/* Reset USB hub if USB hub is switched to type-C port */
-void board_maybe_reset_usb_hub(void);
-
-/* Get fake ADC reading */
-int board_fake_pd_adc_read(int cc);
-
-/* Set pull-up/pull-down on CC lines */
-void board_pd_set_host_mode(int enable);
-
-/*
- * Whether the board is in USB hub mode or not
- *
- * @return 1 when in hub mode, 0 when not, and -1 on error.
- */
-int board_in_hub_mode(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/plankton/build.mk b/board/plankton/build.mk
deleted file mode 100644
index 89a01e629b..0000000000
--- a/board/plankton/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072CBU6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/plankton/ec.tasklist b/board/plankton/ec.tasklist
deleted file mode 100644
index 41fc047d6a..0000000000
--- a/board/plankton/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/plankton/gpio.inc b/board/plankton/gpio.inc
deleted file mode 100644
index 9c618dbaa6..0000000000
--- a/board/plankton/gpio.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(VBUS_WAKE,           PIN(B, 5),  GPIO_INT_BOTH,    vbus_event)
-GPIO_INT(DPSRC_HPD,           PIN(B, 13), GPIO_INT_BOTH,    hpd_event)
-GPIO_INT(DBG_12V_TO_DUT_L,    PIN(B, 14), GPIO_INT_FALLING, button_event)
-GPIO_INT(DBG_5V_TO_DUT_L,     PIN(B, 8),  GPIO_INT_FALLING, button_event)
-GPIO_INT(DBG_CHG_TO_DEV_L,    PIN(F, 1),  GPIO_INT_FALLING, button_event)
-GPIO_INT(DBG_USB_TOGGLE_L,    PIN(F, 0),  GPIO_INT_FALLING, button_event)
-GPIO_INT(DBG_CASE_CLOSE_EN_L, PIN(B, 12), GPIO_INT_FALLING, button_event)
-GPIO_INT(DBG_MUX_FLIP_L,      PIN(B, 15), GPIO_INT_FALLING, button_event)
-
-/* TODO(crosbug.com/p/33761) : This interrupt is double booked w/ HPD */
-GPIO(DBG_20V_TO_DUT_L,    PIN(C, 13), GPIO_INPUT)
-
-/* PD RX/TX */
-GPIO(USBC_PD_REF,         PIN(A, 1),  GPIO_ANALOG)
-GPIO(USBC_CC1_PD,         PIN(A, 0),  GPIO_ANALOG)
-GPIO(USBC_CC1_TX_EN,      PIN(A, 3),  GPIO_OUT_LOW)
-GPIO(USBC_CC2_PD,         PIN(A, 4),  GPIO_ANALOG)
-GPIO(USBC_CC2_TX_EN,      PIN(B, 2),  GPIO_OUT_LOW)
-GPIO(USBC_CC_TX_DATA,     PIN(A, 6),  GPIO_OUT_LOW)
-
-#if 0
-/* Alternate functions */
-GPIO(USBC_TX_CLKOUT,      PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(USBC_TX_CLKIN,       PIN(A, 5),  GPIO_OUT_LOW)
-#endif
-
-/* USB-C Power and muxes control */
-GPIO(USBC_CHARGE_EN,      PIN(A, 8),  GPIO_OUT_HIGH)
-GPIO(USBC_CC1_DEVICE_ODL, PIN(A, 9),  GPIO_OUT_LOW)
-GPIO(USBC_CC1_HOST,       PIN(A, 2),  GPIO_INPUT)
-GPIO(USBC_CC2_DEVICE_ODL, PIN(B, 7),  GPIO_OUT_LOW)
-GPIO(USBC_CC2_HOST,       PIN(B, 6),  GPIO_INPUT)
-GPIO(USBC_POLARITY,       PIN(B, 1),  GPIO_OUT_HIGH)
-GPIO(USBC_SS_USB_MODE,    PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(USB_CC1_VCONN_EN_L,  PIN(A, 11), GPIO_OUT_HIGH)
-GPIO(USB_CC2_VCONN_EN_L,  PIN(A, 12), GPIO_OUT_HIGH)
-
-GPIO(VBUS_CHARGER_EN,     PIN(B, 0),  GPIO_OUT_LOW)
-/* VSEL_0/1: 0/0 = 5V, 1/0 = 12V, 1/1 = 20V */
-GPIO(USBC_VSEL_1,         PIN(A, 10), GPIO_OUT_LOW)
-GPIO(USBC_VSEL_0,         PIN(C, 14), GPIO_OUT_LOW)
-
-/* Case closed debugging */
-GPIO(CASE_CLOSE_EN,       PIN(A, 7),  GPIO_OUT_LOW)
-GPIO(CASE_CLOSE_DFU_L,    PIN(A, 13), GPIO_OUT_HIGH)
-GPIO(DEBUG_TOGGLE,        PIN(B, 4),  GPIO_OUT_LOW)
-
-/* Alternate functions */
-#if 0
-GPIO(UART_TX,             PIN(A, 14), GPIO_OUT_LOW)
-GPIO(UART_RX,             PIN(A, 15), GPIO_OUT_LOW)
-#endif
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(MASTER_I2C_SCL,       PIN(B, 10), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,       PIN(B, 11), GPIO_INPUT)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0020), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PA5) */
-ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0) /* TIM17_CH1: (PB9) */
-ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART,   0) /* USART2: PA14/PA15 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_I2C,    0) /* I2C MASTER:PB10/11 */
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h
deleted file mode 100644
index fca6484069..0000000000
--- a/board/plankton/usb_pd_config.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-#include "board.h"
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PA4-7 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is using COMP1 triggering TIM1 CH1 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL 0
-
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) BIT(21)
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 MHz pin speed on SPI1 (PA5/6) and CC1_TX_EN (PA3) */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003CC0;
-	/* 40 MHz pin speed on TIM17_CH1 (PB9) and CC2_TX_EN (PB2) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0030;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* put SPI function on TX pin */
-	/* PA6 is SPI1 MISO */
-	gpio_set_alternate_function(GPIO_A, 0x0040, 0);
-
-	/* set the polarity */
-	gpio_set_level(GPIO_USBC_CC1_TX_EN, !polarity);
-	gpio_set_level(GPIO_USBC_CC2_TX_EN, polarity);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* output low on SPI TX to disable the FET */
-	/* PA6 is SPI1_MISO */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				   & ~(3 << (2*6)))
-				   |  (1 << (2*6));
-	/* put the low level reference in Hi-Z */
-	gpio_set_level(GPIO_USBC_CC1_TX_EN, 0);
-	gpio_set_level(GPIO_USBC_CC2_TX_EN, 0);
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/* use the right comparator non inverted input for COMP1 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-			| STM32_COMP_CMP1EN
-			| (polarity ?
-			   STM32_COMP_CMP1INSEL_INM4 :
-			   STM32_COMP_CMP1INSEL_INM6);
-	gpio_set_level(GPIO_USBC_POLARITY, polarity);
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	/* Configure SCK pin */
-	gpio_config_module(MODULE_USB_PD, 1);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	board_pd_set_host_mode(enable);
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   VBUS, charge path based on power role.
- *   Physical layer CC transmit.
- *   VCONNs disabled.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/*
-	 * Set CC pull resistors, and charge_en and vbus_en GPIOs to match
-	 * the initial role.
-	 */
-	pd_set_host_mode(port, power_role);
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-
-	gpio_set_level(GPIO_USB_CC1_VCONN_EN_L, 1);
-	gpio_set_level(GPIO_USB_CC2_VCONN_EN_L, 1);
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	return board_fake_pd_adc_read(cc);
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/plankton/usb_pd_policy.c b/board/plankton/usb_pd_policy.c
deleted file mode 100644
index 8cb24372a0..0000000000
--- a/board/plankton/usb_pd_policy.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "board.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Acceptable margin between requested VBUS and measured value */
-#define MARGIN_MV 400 /* mV */
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED |\
-			 PDO_FIXED_COMM_CAP)
-
-/* Source PDOs */
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
-};
-static const int pd_src_pdo_cnts[] = {
-		[SRC_CAP_5V] = 1,
-		[SRC_CAP_12V] = 2,
-		[SRC_CAP_20V] = 3,
-};
-
-static int pd_src_pdo_idx;
-
-/* Fake PDOs : we just want our pre-defined voltages */
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  500, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000,  500, PDO_FIXED_FLAGS),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-/* Whether alternate mode has been entered or not */
-static int alt_mode;
-
-void board_set_source_cap(enum board_src_cap cap)
-{
-	pd_src_pdo_idx = cap;
-}
-
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnts[pd_src_pdo_idx];
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	/* No battery, nothing to do */
-	return;
-}
-
-__override void pd_transition_voltage(int idx)
-{
-	gpio_set_level(GPIO_USBC_VSEL_0, idx >= 2);
-	gpio_set_level(GPIO_USBC_VSEL_1, idx >= 3);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Output the correct voltage */
-	gpio_set_level(GPIO_VBUS_CHARGER_EN, 1);
-
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Kill VBUS */
-	gpio_set_level(GPIO_VBUS_CHARGER_EN, 0);
-	gpio_set_level(GPIO_USBC_VSEL_0, 0);
-	gpio_set_level(GPIO_USBC_VSEL_1, 0);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return gpio_get_level(GPIO_VBUS_WAKE);
-}
-
-__override int pd_board_checks(void)
-{
-	static int was_connected = -1;
-	if (was_connected != 1 && pd_is_connected(0))
-		board_maybe_reset_usb_hub();
-	was_connected = pd_is_connected(0);
-	return EC_SUCCESS;
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/* Always allow power swap */
-	return 1;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/* Always allow data swap */
-	return 1;
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-	/* If Plankton is in USB hub mode, always act as UFP */
-	if (board_in_hub_mode() && dr_role == PD_ROLE_DFP &&
-	    (flags & PD_FLAGS_PARTNER_DR_DATA))
-		pd_request_data_swap(port);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 0, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 1, /* Vbus power required */
-				 AMA_USBSS_BBONLY /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	payload[VDO_I(AMA)] = vdo_ama;
-	return VDO_I(AMA) + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, 0);
-	return 2;
-}
-
-/*
- * Will only ever be a single mode for this UFP_D device as it has no real USB
- * support making it only PIN_E configureable
- */
-#define MODE_CNT 1
-#define OPOS 1
-
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
-		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (gpio_get_level(GPIO_USBC_SS_USB_MODE))
-		return 0; /* nak */
-
-	if (PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT)
-		return 0; /* nak */
-
-	memcpy(payload + 1, vdo_dp_mode, sizeof(vdo_dp_mode));
-	return MODE_CNT + 1;
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = gpio_get_level(GPIO_DPSRC_HPD);
-	if (opos != OPOS)
-		return 0; /* nak */
-
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
-				   !gpio_get_level(GPIO_USBC_SS_USB_MODE),
-				   0,		     /* power low */
-				   0x2);
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		gpio_set_level(GPIO_USBC_SS_USB_MODE, 0);
-	return 1;
-}
-
-int svdm_enter_mode(int port, uint32_t *payload)
-{
-	int usb_mode = gpio_get_level(GPIO_USBC_SS_USB_MODE);
-
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
-	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0; /* will generate NAK */
-
-	if (usb_mode) {
-		CPRINTS("Toggle USB_MODE if you want DP & re-connect");
-		return 0;
-	}
-
-	alt_mode = OPOS;
-	return 1;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	return alt_mode;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	alt_mode = 0;
-	/*
-	 * Don't actually toggle GPIO_USBC_SS_USB_MODE since its manually
-	 * controlled by operator.
-	 */
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-__override const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-			     uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-	int rsize = 1;
-	CPRINTF("VDM/%d [%d] %08x\n", cnt, cmd, payload[0]);
-
-	*rpayload = payload;
-	switch (cmd) {
-	case VDO_CMD_VERSION:
-		memcpy(payload + 1, &current_image_data.version, 24);
-		rsize = 7;
-		break;
-	default:
-		rsize = 0;
-	}
-
-	CPRINTS("DONE");
-	/* respond (positively) to the request */
-	payload[0] |= VDO_SRC_RESPONDER;
-
-	return rsize;
-}
diff --git a/board/plankton/vif_override.xml b/board/plankton/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/plankton/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/polyberry/board.c b/board/polyberry/board.c
deleted file mode 100644
index 5bb811f82c..0000000000
--- a/board/polyberry/board.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Polyberry board configuration */
-
-#include "common.h"
-#include "dma.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "gpio_list.h"
-#include "hooks.h"
-#include "registers.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "update_fw.h"
-#include "usb_descriptor.h"
-#include "util.h"
-#include "usb_dwc_console.h"
-#include "usb_dwc_update.h"
-#include "usb_hw.h"
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Polyberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Polyberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-struct dwc_usb usb_ctl = {
-	.ep = {
-		&ep0_ctl,
-		&ep_console_ctl,
-		&usb_update_ep_ctl,
-	},
-	.speed = USB_SPEED_FS,
-	.phy_type = USB_PHY_ULPI,
-	.dma_en = 1,
-	.irq = STM32_IRQ_OTG_HS,
-};
-
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
-
-void board_config_post_gpio_init(void)
-{
-	/* We use MCO2 clock passthrough to provide a clock to USB HS */
-	gpio_config_module(MODULE_MCO, 1);
-	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
-
-	if (usb_ctl.phy_type == USB_PHY_ULPI)
-		gpio_set_level(GPIO_USB_MUX_SEL, 0);
-	else
-		gpio_set_level(GPIO_USB_MUX_SEL, 1);
-
-	/* Set USB GPIO to high speed */
-	GPIO_SET_HS(A, 11);
-	GPIO_SET_HS(A, 12);
-
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
-
-	GPIO_SET_HS(B,  5);
-	GPIO_SET_HS(B, 13);
-	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
-	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
-}
-
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/polyberry/board.h b/board/polyberry/board.h
deleted file mode 100644
index 8e55967bf5..0000000000
--- a/board/polyberry/board.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Polyberry configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-/* Use external clock */
-#define CONFIG_STM32_CLOCK_HSE_HZ 24000000
-
-#define CONFIG_BOARD_POST_GPIO_INIT
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* The UART console is on test points USART3 (PC10/PC11) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 3
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-/* Don't waste precious DMA channels on console. */
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-#define CONFIG_UART_TX_REQ_CH 4
-#define CONFIG_UART_RX_REQ_CH 4
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x5020
-#define CONFIG_USB_CONSOLE
-#define CONFIG_STREAM_USB
-#define CONFIG_USB_UPDATE
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 100
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_COUNT		2
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_COUNT		3
-
-/* This is not actually a Chromium EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 5
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_UPDATE_NAME,
-	USB_STR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/polyberry/build.mk b/board/polyberry/build.mk
deleted file mode 100644
index 6b06f2bb8f..0000000000
--- a/board/polyberry/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f446
-
-board-y=board.o
diff --git a/board/polyberry/ec.tasklist b/board/polyberry/ec.tasklist
deleted file mode 100644
index c1fb169118..0000000000
--- a/board/polyberry/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/polyberry/gpio.inc b/board/polyberry/gpio.inc
deleted file mode 100644
index 536dccc5ff..0000000000
--- a/board/polyberry/gpio.inc
+++ /dev/null
@@ -1,82 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Outputs */
-GPIO(PM_RESET_L,		PIN(D, 0),  GPIO_OUT_HIGH)
-GPIO(PM_KPD_PWR_L,		PIN(D, 1),  GPIO_OUT_HIGH)
-GPIO(AP_RESET_L,		PIN(D, 2),  GPIO_OUT_HIGH)
-GPIO(AP_FORCED_USB_BOOT,	PIN(D, 3),  GPIO_OUT_LOW)
-GPIO(AP_PS_HOLD,		PIN(D, 4),  GPIO_OUT_HIGH)
-
-GPIO(MUX_EN_L,			PIN(A, 7),  GPIO_INPUT)
-GPIO(USB_MUX_SEL,		PIN(A, 6),  GPIO_OUT_HIGH)
-GPIO(PHY_RESET,			PIN(C, 4),  GPIO_INPUT)
-GPIO(LED_BLUE,			PIN(A, 2),  GPIO_ODR_LOW)
-GPIO(LED_GRN,			PIN(B, 8),  GPIO_ODR_LOW)
-GPIO(LED_RED,			PIN(B, 15), GPIO_ODR_LOW)
-
-/* Clock function */
-GPIO(MCU_TO_PHY_MCO,		PIN(C, 9), GPIO_INPUT)
-
-
-/* These pin assignments aren't used as GPIO. Let's note them here
- * for readability but not initialize them.
- * USART1 TX/RX - AP
- * GPIO(MCU_UART1_TX,		PIN(A, 9), GPIO_INPUT)
- * GPIO(MCU_UART1_RX,		PIN(A, 10), GPIO_INPUT)
- * USART2 TX/RX - Sensor Hub
- * GPIO(MCU_UART2_TX,		PIN(D, 5), GPIO_INPUT)
- * GPIO(MCU_UART2_RX,		PIN(D, 6), GPIO_INPUT)
-
- * USART3 TX/RX - Console
- * GPIO(MCU_UART3_TX,		PIN(C, 10), GPIO_INPUT)
- * GPIO(MCU_UART3_RX,		PIN(C, 11), GPIO_INPUT)
- * USART5 TX/RX - SSC (?)
- * GPIO(MCU_UART5_TX,		PIN(E, 7), GPIO_INPUT)
- * GPIO(MCU_UART5_RX,		PIN(E, 8), GPIO_INPUT)
- */
-
-/* USB pins */
-GPIO(USB_FS_DM,			PIN(A, 11), GPIO_INPUT)
-GPIO(USB_FS_DP,			PIN(A, 12), GPIO_INPUT)
-
-GPIO(USB_HS_ULPI_NXT,		PIN(C, 3), GPIO_INPUT)
-GPIO(USB_HS_ULPI_DIR,		PIN(C, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_STP,		PIN(C, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_CK,		PIN(A, 5), GPIO_INPUT)
-
-GPIO(USB_HS_ULPI_D7,		PIN(B, 5), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D6,		PIN(B,13), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D5,		PIN(B,12), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D4,		PIN(B, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D3,		PIN(B,10), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D2,		PIN(B, 1), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D1,		PIN(B, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D0,		PIN(A, 3), GPIO_INPUT)
-
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-
-ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART, 0) /* USART1: PA9/PA10 - AP */
-ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, 0) /* USART2: PD5/PD6 - SH */
-ALTERNATE(PIN_MASK(C, 0x0c00), 7, MODULE_UART, 0) /* USART3: PC10/PC11 - Console */
-ALTERNATE(PIN_MASK(D, 0x00c0), 8, MODULE_UART, 0) /* USART5: PE7/PE8 - SSC */
-
-/* OTG FS */
-ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* DWC USB OTG: PA11/12 */
-
-/* OTG HS */
-ALTERNATE(PIN_MASK(A, 0x0028), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(B, 0x3427), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(C, 0x000d), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(C, 0x0200), 0, MODULE_MCO, 0) /* MCO2: PC9 */
diff --git a/board/pompom/battery.c b/board/pompom/battery.c
deleted file mode 100644
index 7ce8eec202..0000000000
--- a/board/pompom/battery.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max        = 8800, /* mV */
-			.voltage_normal     = 7700, /* mV */
-			.voltage_min        = 6000, /* mV */
-			.precharge_current  = 256,  /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c     = 0,
-			.charging_max_c     = 60,
-			.discharging_min_c  = -20,
-			.discharging_max_c  = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD;
diff --git a/board/pompom/board.c b/board/pompom/board.c
deleted file mode 100644
index 855a8c305d..0000000000
--- a/board/pompom/board.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Pompom board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usba_oc_interrupt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-static void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x01 in [1] (KSO_01/KSI_00, the old location of Search key);
-	 * as it uses the new location (KSO_00/KSI_03). And T11 key, which maps
-	 * to KSO_01/KSI_00, is not there.
-	 */
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 20000 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * The rev-2 hardware doesn't have the external pull-up fix for the bug
-	 * b/164256614. It requires rework to stuff the resistor. For people who
-	 * has difficulty to do the rework, this is a workaround, which makes
-	 * the GPIO push-pull, instead of open-drain.
-	 */
-	if (system_get_board_version() == 2)
-		gpio_set_flags(GPIO_HIBERNATE_L, GPIO_OUTPUT);
-
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-
-	/* Enable interrupt for BMI160 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Board rev 2+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 2)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-__override uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Pompom rev 2+ changes TCPC from PS8805 to PS8755 */
-	if (system_get_board_version() == 0)
-		return PS8751_PRODUCT_ID;
-	else if (system_get_board_version() == 1)
-		return PS8805_PRODUCT_ID;
-
-	return PS8755_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_DA9313_GPIO0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-static struct stprivate_data g_lis2dwl_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t lis2dwl_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LIS2DWL,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &lis2dw12_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_lis2dwl_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LIS2DWL_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.default_range = 2, /* g */
-	.min_frequency = LIS2DW12_ODR_MIN_VAL,
-	.max_frequency = LIS2DW12_ODR_MAX_VAL,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-static void board_detect_motionsensor(void)
-{
-	int val = 0;
-
-	/*
-	 * BMA253 and LIS2DWL have same slave address, so we check the
-	 * LIS2DWL WHO AM I register to check the lid accel type
-	 */
-	i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS,
-		LIS2DW12_WHO_AM_I_REG, &val);
-
-	if (val == LIS2DW12_WHO_AM_I) {
-		motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
-		CPRINTS("Lid Accel: LIS2DWL");
-	}
-}
-
-static void board_update_sensor_config_from_sku(void)
-{
-	board_detect_motionsensor();
-}
-DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
-	     HOOK_PRIO_INIT_I2C + 2);
diff --git a/board/pompom/board.h b/board/pompom/board.h
deleted file mode 100644
index 3f35d7ceab..0000000000
--- a/board/pompom/board.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Pompom board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-#include "board_revs.h"
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_PWM_KBLIGHT
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_EC_RST_ODL GPIO_EC_RST_ODL_GPIO02
-#define GPIO_PMIC_RESIN_L GPIO_PM7180_RESIN_D_L
-
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_BYD,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/pompom/board_revs.h b/board/pompom/board_revs.h
deleted file mode 100644
index 1ac5ee1337..0000000000
--- a/board/pompom/board_revs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_REVS_H
-#define __CROS_EC_BOARD_REVS_H
-
-#define POMPOM_REV0 0
-#define POMPOM_REV1 1
-#define POMPOM_REV_LAST    POMPOM_REV1
-#define POMPOM_REV_DEFAULT POMPOM_REV1
-
-#if !defined(BOARD_REV)
-#define BOARD_REV POMPOM_REV_DEFAULT
-#endif
-
-#if BOARD_REV < POMPOM_REV0 || BOARD_REV > POMPOM_REV_LAST
-#error "Board revision out of range"
-#endif
-
-
-#endif /* __CROS_EC_BOARD_REVS_H */
diff --git a/board/pompom/build.mk b/board/pompom/build.mk
deleted file mode 100644
index a044fa58cb..0000000000
--- a/board/pompom/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y=battery.o board.o led.o
diff --git a/board/pompom/ec.tasklist b/board/pompom/ec.tasklist
deleted file mode 100644
index 7ec8b46059..0000000000
--- a/board/pompom/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/pompom/gpio.inc b/board/pompom/gpio.inc
deleted file mode 100644
index 531452eae3..0000000000
--- a/board/pompom/gpio.inc
+++ /dev/null
@@ -1,183 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(ACOK_OD,           PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(LID_360_L,         PIN(7, 2), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
- * need to be an interrupt for normal EC operations. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL_GPIO02,     PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM7180_RESIN_D_L,      PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN,     PIN(7, 5), GPIO_OUT_HIGH)  /* H: CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 4), GPIO_OUT_LOW)
-GPIO(EC_PWR_LED_W,          PIN(6, 0), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(DA9313_GPIO0,          PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(C, 0))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(C, 6))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(E, 4))
-UNUSED(PIN(F, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(D, 3))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/pompom/led.c b/board/pompom/led.c
deleted file mode 100644
index db571a067c..0000000000
--- a/board/pompom/led.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ON_LVL 1
-#define LED_OFF_LVL 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color_battery(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
-	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-void led_set_color_power(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_PWR_LED_W,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LED_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_AMBER;
-		break;
-	case PWR_STATE_DISCHARGE:
-		/* Discharging : off */
-		color = LED_OFF;
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber 1 sec, off 1 sec */
-		period = (1 + 1);
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1)
-			color = LED_AMBER;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: White on */
-		color = LED_WHITE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: White 2 sec, Amber 2 sec */
-			period = (2 + 2);
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2)
-				color = LED_WHITE;
-			else
-				color = LED_AMBER;
-		} else
-			color = LED_WHITE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color_battery(color);
-}
-
-static void board_led_set_power(void)
-{
-	static int power_ticks;
-	int color = LED_OFF;
-	int period = 0;
-
-	power_ticks++;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		/* S3: On 1 sec, Off 3 sec */
-		period = (1 + 3);
-		power_ticks = power_ticks % period;
-		if (power_ticks < 1)
-			color = LED_WHITE;
-		else
-			color = LED_OFF;
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		/* S5: LED off */
-		color = LED_OFF;
-	} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* S0: LED on */
-		color = LED_WHITE;
-	}
-
-	led_set_color_power(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		board_led_set_power();
-}
-DECLARE_HOOK(HOOK_SECOND, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color_battery(color);
-}
diff --git a/board/pompom/vif_override.xml b/board/pompom/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/pompom/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/poppy/analyzestack.yaml b/board/poppy/analyzestack.yaml
deleted file mode 100644
index 59e0f9de4c..0000000000
--- a/board/poppy/analyzestack.yaml
+++ /dev/null
@@ -1,230 +0,0 @@
-# Size of extra stack frame needed by exception context switch.
-# See core/cortex-m/switch.S
-exception_frame_size: 224
-# Add some missing calls.
-add:
-  # TCPC stuff:
-  tcpm_init.lto_priv.255[driver/tcpm/tcpm.h:77]:
-    - anx74xx_tcpm_init
-    - tcpci_tcpm_init
-  tcpm_release[driver/tcpm/tcpm.h:90]:
-    - anx74xx_tcpm_release
-    - ps8xxx_tcpm_release
-  tcpm_get_cc.lto_priv.246[driver/tcpm/tcpm.h:95]:
-    - anx74xx_tcpm_get_cc
-    - tcpci_tcpm_get_cc
-  tcpm_select_rp_value[driver/tcpm/tcpm.h:105]:
-    - anx74xx_tcpm_select_rp_value
-    - tcpci_tcpm_select_rp_value
-  tcpm_set_cc.lto_priv.239[driver/tcpm/tcpm.h:110]:
-    - anx74xx_tcpm_set_cc
-    - tcpci_tcpm_set_cc
-  tcpm_set_polarity[driver/tcpm/tcpm.h:115]:
-    - anx74xx_tcpm_set_polarity
-    - tcpci_tcpm_set_polarity
-  tcpm_set_vconn.lto_priv.249[driver/tcpm/tcpm.h:120]:
-    - anx74xx_tcpm_set_vconn
-    - tcpci_tcpm_set_vconn
-  tcpm_set_msg_header[driver/tcpm/tcpm.h:125]:
-    - anx74xx_tcpm_set_msg_header
-    - tcpci_tcpm_set_msg_header
-  tcpm_set_rx_enable.lto_priv.252[driver/tcpm/tcpm.h:131]:
-    - anx74xx_tcpm_set_rx_enable
-    - tcpci_tcpm_set_rx_enable
-  tcpm_get_message[driver/tcpm/tcpm.h:136]:
-    - anx74xx_tcpm_get_message
-    - tcpci_tcpm_get_message
-  tcpm_transmit[driver/tcpm/tcpm.h:142]:
-    - anx74xx_tcpm_transmit
-    - ps8xxx_tcpm_transmit
-  tcpc_alert[driver/tcpm/tcpm.h:147]:
-    - anx74xx_tcpc_alert
-    - tcpci_tcpc_alert
-  tcpc_discharge_vbus[driver/tcpm/tcpm.h:152]:
-    - anx74xx_tcpc_discharge_vbus
-    - tcpci_tcpc_discharge_vbus
-  tcpm_set_drp_toggle[driver/tcpm/tcpm.h:163]:
-    - anx74xx_tcpc_drp_toggle
-    - tcpci_tcpc_drp_toggle
-  tcpm_get_chip_info[driver/tcpm/tcpm.h:185]:
-    - tcpci_get_chip_info
-  board_tcpc_init[board/poppy/board.c:336]:
-    - anx74xx_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  tcpci_tcpc_drp_toggle[driver/tcpm/tcpci.c:148]:
-    - None
-  # USB mux stuff
-  usb_mux_init[driver/usb_mux.c:25]:
-    - anx74xx_tcpm_mux_init
-    - tcpci_tcpm_mux_init
-  usb_mux_init[driver/usb_mux.c:31]:
-    - None
-  usb_mux_set[driver/usb_mux.c:52]:
-    - anx74xx_tcpm_mux_set
-    - tcpci_tcpm_mux_set
-  usb_mux_get[driver/usb_mux.c:71]:
-    - anx74xx_tcpm_mux_get
-    - tcpci_tcpm_mux_get
-  usb_mux_flip[driver/usb_mux.c:92]:
-    - anx74xx_tcpm_mux_get
-    - tcpci_tcpm_mux_get
-  usb_mux_flip[driver/usb_mux.c:103]:
-    - anx74xx_tcpm_mux_set
-    - tcpci_tcpm_mux_set
-  hc_usb_pd_mux_info[driver/usb_mux.c:169]:
-    - anx74xx_tcpm_mux_get
-    - tcpci_tcpm_mux_get
-  svdm_dp_post_config.lto_priv.271[board/poppy/usb_pd_policy.c:364]:
-    - anx74xx_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  svdm_dp_attention.lto_priv.272[board/poppy/usb_pd_policy.c:379]:
-    - anx74xx_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  svdm_exit_dp_mode.lto_priv.273[board/poppy/usb_pd_policy.c:390]:
-    - anx74xx_tcpc_update_hpd_status
-    - ps8xxx_tcpc_update_hpd_status
-  # pd_svdm
-  pd_dfp_enter_mode[common/usb_pd_policy.c:459]:
-    - svdm_enter_dp_mode
-  dfp_consume_attention.lto_priv.259[common/usb_pd_policy.c:497]:
-    - svdm_dp_attention
-  pd_dfp_exit_mode[common/usb_pd_policy.c:563]:
-    - svdm_exit_dp_mode
-  pd_dfp_exit_mode[common/usb_pd_policy.c:580]:
-    - svdm_exit_dp_mode
-  pd_svdm[common/usb_pd_policy.c:767]:
-    - svdm_dp_status
-  pd_svdm[common/usb_pd_policy.c:778]:
-    - svdm_dp_config
-  pd_svdm[common/usb_pd_policy.c:784]:
-    - svdm_dp_post_config
-  # Motion sense
-  queue_advance_head[common/queue.c:105]:
-    - queue_action_null
-  queue_advance_tail[common/queue.c:116]:
-    - queue_action_null
-  motion_sense_set_data_rate[common/motion_sense.c:270]:
-    - set_data_rate[driver/accelgyro_bmi160.c]
-    - opt3001_set_data_rate
-  motion_sense_set_data_rate[common/motion_sense.c:289]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - opt3001_get_data_rate
-  motion_sense_set_ec_rate_from_ap[common/motion_sense.c:308]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - opt3001_get_data_rate
-  motion_sense_set_motion_intervals.lto_priv.303[common/motion_sense.c:414]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - opt3001_get_data_rate
-  motion_sense_init[common/motion_sense.c:450]:
-    - init[driver/accelgyro_bmi160.c]
-    - opt3001_init
-  sensor_init_done[common/motion_sense.c:471]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - opt3001_set_range
-  sensor_init_done[common/motion_sense.c:474]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - opt3001_get_range
-  motion_sense_process.isra.9[common/motion_sense.c:721]:
-    - irq_handler[driver/accelgyro_bmi160.c]
-  host_cmd_motion_sense[common/motion_sense.c:1251]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - opt3001_set_range
-  host_cmd_motion_sense[common/motion_sense.c:1259]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - opt3001_get_range
-  host_cmd_motion_sense[common/motion_sense.c:1274]:
-    - set_offset[driver/accelgyro_bmi160.c]
-    - opt3001_set_offset
-  host_cmd_motion_sense[common/motion_sense.c:1297]:
-    - perform_calib[driver/accelgyro_bmi160.c]
-  host_cmd_motion_sense[common/motion_sense.c:1300]:
-    - get_offset[driver/accelgyro_bmi160.c]
-    - opt3001_get_offset
-  command_accelrange[common/motion_sense.c:1515]:
-    - set_range[driver/accelgyro_bmi160.c]
-    - opt3001_set_range
-  command_accelrange[common/motion_sense.c:1520]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - opt3001_get_range
-  host_cmd_motion_sense[common/motion_sense.c:1520]:
-    - get_range[driver/accelgyro_bmi160.c]
-    - opt3001_get_range
-  command_accelresolution[common/motion_sense.c:1564]:
-    - None
-  command_accelresolution[common/motion_sense.c:1568]:
-    - get_resolution[driver/accelgyro_bmi160.c]
-  command_accel_data_rate[common/motion_sense.c:1623]:
-    - get_data_rate[driver/accelgyro_bmi160.c]
-    - opt3001_get_data_rate
-  command_accel_read_xyz[common/motion_sense.c:1659]:
-    - read[driver/accelgyro_bmi160.c]
-    - opt3001_read_lux
-  # Temp (see temp_sensors array in board file)
-  temp_sensor_read[common/temp_sensor.c:26]:
-    - charge_get_battery_temp
-    - bd99992gw_get_val
-  # Misc
-  jump_to_image[common/system.c:568]:
-    - None
-  system_download_from_flash[chip/npcx/system-npcx5.c:257]:
-    - None
-  __hibernate_npcx_series[chip/npcx/system-npcx5.c:144]:
-    - None
-  handle_command[common/console.c:248]:
-    - { name: __cmds, stride: 16, offset: 4 }
-  hook_task[common/hooks.c:197]:
-    - { name: __deferred_funcs, stride: 4, offset: 0 }
-    - { name: __hooks_second, stride: 8, offset: 0 }
-    - { name: __hooks_tick, stride: 8, offset: 0 }
-  # Note: This assumes worse case, where all hook functions can be called from
-  # any hook_notify call
-  # Generate using `grep hooks_.*_end build/soraka/R*/ec.R*.smap |
-  #   sed -e 's/.*\(__hooks.*\)_end/    - { name: \1, stride: 8, offset: 0 }/' |
-  #   sort -u`
-  hook_notify[common/hooks.c:127]:
-    - { name: __hooks_ac_change, stride: 8, offset: 0 }
-    - { name: __hooks_battery_soc_change, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_pre_init, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_reset, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_resume, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_shutdown, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_startup, stride: 8, offset: 0 }
-    - { name: __hooks_chipset_suspend, stride: 8, offset: 0 }
-    - { name: __hooks_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_lid_change, stride: 8, offset: 0 }
-    - { name: __hooks_pre_freq_change, stride: 8, offset: 0 }
-    - { name: __hooks_pwrbtn_change, stride: 8, offset: 0 }
-    - { name: __hooks_sysjump, stride: 8, offset: 0 }
-    - { name: __hooks_tablet_mode_change, stride: 8, offset: 0 }
-  mkbp_get_next_event[common/mkbp_event.c:130]:
-    - { name:  __mkbp_evt_srcs, stride: 8, offset: 4 }
-  host_send_response[common/host_command.c:153]:
-    - lpc_send_response
-  host_packet_respond[common/host_command.c:240]:
-    - lpc_send_response
-  host_command_process[common/host_command.c:704]:
-    - { name: __hcmds, stride: 12, offset: 0 }
-  # gpio_interrupt.lto_priv.407[chip/npcx/gpio.c:479]
-  vfnprintf:
-    # This covers all the addchar in vfnprintf, but stackanalyzer does not
-    # realize that...
-    - __tx_char
-  i2c_command_passthru[common/i2c_master.c:597]:
-    - None
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
-# Remove hook paths that don't make sense
-- [ common_intel_x86_power_handle_state, hook_notify, powerbtn_x86_lid_change ]
-- [ base_disable, hook_notify, handle_pending_reboot.lto_priv.290 ]
-- [ system_common_shutdown, hook_notify, system_run_image_copy ]
-- [ base_detect_change, hook_notify, [ powerbtn_x86_lid_change, jump_to_image, power_up_inhibited_cb, motion_sense_shutdown, motion_sense_resume, system_common_shutdown, base_disable ] ]
-- [ jump_to_image, hook_notify, [ powerbtn_x86_lid_change, system_common_shutdown, power_up_inhibited_cb, motion_sense_shutdown, motion_sense_resume, base_disable ] ]
-- [ [ extpower_deferred, charger_task ], hook_notify, [ powerbtn_x86_lid_change, system_common_shutdown ] ]
-- [ common_intel_x86_power_handle_state, hook_notify, power_up_inhibited_cb ]
-# pd_request_power_swap calls set_state with either PD_STATE_SRC_SWAP_INIT or
-# PD_STATE_SNK_SWAP_INIT as parameters, which cannot call any of the
-# charge_manager functions.
-- [ [ pd_request_power_swap, pd_execute_hard_reset, pd_request_data_swap, pd_request_vconn_swap.lto_priv.237, pd_send_request_msg.lto_priv.250 ], set_state.lto_priv.236, [ typec_set_input_current_limit, charge_manager_update_charge, pd_power_supply_reset, pd_dfp_exit_mode, usb_mux_set ] ]
-# Debug prints that do not actually need a 64 uint division, of the time
-- [ [i2c_reset, i2c_abort_data, i2c_xfer], cprintf, vfnprintf, [uint64divmod.part.3.lto_priv.141, get_time] ]
diff --git a/board/poppy/base_detect_lux.c b/board/poppy/base_detect_lux.c
deleted file mode 100644
index c348eb681d..0000000000
--- a/board/poppy/base_detect_lux.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lux base detection code */
-
-#include "adc.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * When base is disconnected, and gets connected:
- * Lid has 1M pull-up, base has 200K pull-down, so the ADC
- * value should be around 200/(200+1000)*3300 = 550.
- *
- * Idle value should be ~3300: lid has 1M pull-up, and nothing else (i.e. ADC
- * maxing out at 2813).
- */
-#define BASE_DISCONNECTED_CONNECT_MIN_MV 450
-#define BASE_DISCONNECTED_CONNECT_MAX_MV 600
-
-#define BASE_DISCONNECTED_MIN_MV 2800
-#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT+1)
-
-/*
- * When base is connected, then gets disconnected:
- * Lid has 1M pull-up, lid has 10.0K pull-down, so the ADC
- * value should be around 10.0/(10.0+1000)*3300 = 33.
- *
- * Idle level when connected should be:
- * Lid has 10K pull-down, base has 5.1K pull-up, so the ADC value should be
- * around 10.0/(10.0+5.1)*3300 = 2185 (actual value is 2153 as there is still
- * a 1M pull-up on lid, and 200K pull-down on base).
- */
-#define BASE_CONNECTED_DISCONNECT_MIN_MV 20
-#define BASE_CONNECTED_DISCONNECT_MAX_MV 40
-
-#define BASE_CONNECTED_MIN_MV 2050
-#define BASE_CONNECTED_MAX_MV 2300
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/**
- * Board-specific routine to indicate if the base is connected.
- */
-int board_is_base_connected(void)
-{
-	return current_base_status == BASE_CONNECTED;
-}
-
-/**
- * Board-specific routine to enable power distribution between lid and base
- * (current can flow both ways).
- *
- * We only allow the base power to be enabled if the detection code knows that
- * the base is connected.
- */
-void board_enable_base_power(int enable)
-{
-	gpio_set_level(GPIO_PPVAR_VAR_BASE,
-		enable && current_base_status == BASE_CONNECTED);
-}
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Enable/disable pull-down on half-duplex UART line
- * 2. Disable power transfer between lid and base when unplugged.
- * 3. Indicate mode change to host.
- * 4. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	current_base_status = status;
-
-	/* Enable pull-down if connected. */
-	gpio_set_level(GPIO_EC_COMM_PD, !connected);
-	/* Disable power to/from base as quickly as possible. */
-	if (!connected)
-		board_enable_base_power(0);
-
-	/*
-	 * Wake the charger task (it is responsible for enabling power to the
-	 * base, and providing OTG power to the base if required).
-	 */
-	task_wake(TASK_ID_CHARGER);
-
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-}
-
-static void print_base_detect_value(const char *str, int v)
-{
-	CPRINTS("Base %s. ADC: %d", str, v);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		goto retry;
-
-	if (current_base_status == BASE_CONNECTED) {
-		if (v >= BASE_CONNECTED_DISCONNECT_MIN_MV &&
-		    v <= BASE_CONNECTED_DISCONNECT_MAX_MV) {
-			print_base_detect_value("disconnected", v);
-			base_detect_change(BASE_DISCONNECTED);
-			return;
-		} else if (v >= BASE_CONNECTED_MIN_MV &&
-			   v <= BASE_CONNECTED_MAX_MV) {
-			/* Still connected. */
-			return;
-		}
-	} else { /* Disconnected or unknown. */
-		if (v >= BASE_DISCONNECTED_CONNECT_MIN_MV &&
-		    v <= BASE_DISCONNECTED_CONNECT_MAX_MV) {
-			print_base_detect_value("connected", v);
-			base_detect_change(BASE_CONNECTED);
-			return;
-		} else if (v >= BASE_DISCONNECTED_MIN_MV &&
-			   v <= BASE_DISCONNECTED_MAX_MV) {
-			if (current_base_status == BASE_UNKNOWN) {
-				print_base_detect_value("disconnected", v);
-				base_detect_change(BASE_DISCONNECTED);
-			}
-			/* Still disconnected. */
-			return;
-		}
-	}
-
-retry:
-	print_base_detect_value("status unclear", v);
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_RETRY_US);
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-
-	if (base_detect_debounce_time <= time_now)
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
-
-	base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US;
-}
-
-void board_base_reset(void)
-{
-	CPRINTS("Resetting base.");
-	base_detect_change(BASE_UNKNOWN);
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static void base_init(void)
-{
-	/*
-	 * Make sure base power and pull-down are off. This will reset the base
-	 * if it is already connected.
-	 */
-	board_enable_base_power(0);
-	gpio_set_level(GPIO_EC_COMM_PD, 1);
-
-	/* Enable base detection interrupt. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_DEBOUNCE_US);
-	gpio_enable_interrupt(GPIO_BASE_DET_A);
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_A);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_A);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_DEBOUNCE_US);
-		gpio_enable_interrupt(GPIO_BASE_DET_A);
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/poppy/base_detect_poppy.c b/board/poppy/base_detect_poppy.c
deleted file mode 100644
index 0fde6fb8e6..0000000000
--- a/board/poppy/base_detect_poppy.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Poppy/Soraka base detection code */
-
-#include "acpi.h"
-#include "adc.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * rev0: Lid has 100K pull-up, base has 5.1K pull-down, so the ADC
- * value should be around 5.1/(100+5.1)*3300 = 160.
- * >=rev1: Lid has 604K pull-up, base has 30.1K pull-down, so the
- * ADC value should be around 30.1/(604+30.1)*3300 = 156
- *
- * We add a significant marging on the maximum value, due to noise on the line,
- * especially when PWM is active. See b/64193554 for details.
- */
-#define BASE_DETECT_MIN_MV 120
-#define BASE_DETECT_MAX_MV 300
-
-/*
- * When the base is connected in reverse, it presents a 100K pull-down,
- * so the ADC value should be around 100/(604+100)*3300 = 469
- *
- * TODO(b:64370797): Do something with these values.
- */
-#define BASE_DETECT_REVERSE_MIN_MV 450
-#define BASE_DETECT_REVERSE_MAX_MV 500
-
-/* Minimum ADC value to indicate base is disconnected for sure */
-#define BASE_DETECT_DISCONNECT_MIN_MV 1500
-
-/*
- * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
- * can be used to wake system from deep S3).
- */
-#define BASE_DETECT_PULSE_MIN_US 400
-#define BASE_DETECT_PULSE_MAX_US 650
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-	BASE_CONNECTED_REVERSE = 3,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Change in power to base
- * 2. Indicate mode change to host.
- * 3. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	CPRINTS("Base %sconnected", connected ? "" : "not ");
-	gpio_set_level(GPIO_PP3300_DX_BASE, connected);
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-	current_base_status = status;
-
-	if (connected)
-		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_ATTACHED);
-	else
-		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_DETACHED);
-
-}
-
-/* Measure detection pin pulse duration (used to wake AP from deep S3). */
-static uint64_t pulse_start;
-static uint32_t pulse_width;
-
-static void print_base_detect_value(int v, int tmp_pulse_width)
-{
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-	uint32_t tmp_pulse_width = pulse_width;
-	static int reverse_debounce = 1;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		return;
-
-	print_base_detect_value(v, tmp_pulse_width);
-
-	if (v >= BASE_DETECT_REVERSE_MIN_MV &&
-	    v <= BASE_DETECT_REVERSE_MAX_MV) {
-		/*
-		 * If we are unlucky when we sample the ADC, we may think that
-		 * the base is connected in reverse, while this may just be a
-		 * transient. Force debouncing a little longer in that case.
-		 */
-		if (current_base_status == BASE_CONNECTED_REVERSE)
-			return;
-
-		if (reverse_debounce == 0) {
-			base_detect_change(BASE_CONNECTED_REVERSE);
-			return;
-		}
-
-		reverse_debounce = 0;
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
-		return;
-	}
-	/* Reset reverse debounce */
-	reverse_debounce = 1;
-
-	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
-		if (current_base_status != BASE_CONNECTED) {
-			base_detect_change(BASE_CONNECTED);
-		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
-			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
-			CPRINTS("Sending event to AP");
-			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-		}
-		return;
-	}
-
-	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
-		base_detect_change(BASE_DISCONNECTED);
-		return;
-	}
-
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static inline int detect_pin_connected(enum gpio_signal det_pin)
-{
-	return gpio_get_level(det_pin) == 0;
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-
-	if (base_detect_debounce_time <= time_now) {
-		/*
-		 * Detect and measure detection pin pulse, when base is
-		 * connected. Only a single pulse is measured over a debounce
-		 * period. If no pulse, or multiple pulses are detected,
-		 * pulse_width is set to 0.
-		 */
-		if (current_base_status == BASE_CONNECTED &&
-		    !detect_pin_connected(signal)) {
-			pulse_start = time_now;
-		} else {
-			pulse_start = 0;
-		}
-		pulse_width = 0;
-
-		hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_DEBOUNCE_US);
-	} else {
-		if (current_base_status == BASE_CONNECTED &&
-		    detect_pin_connected(signal) && !pulse_width &&
-		    pulse_start) {
-			/* First pulse within period. */
-			pulse_width = time_now - pulse_start;
-		} else {
-			pulse_start = 0;
-			pulse_width = 0;
-		}
-	}
-
-	base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US;
-}
-
-static void base_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data, 0);
-	gpio_enable_interrupt(GPIO_BASE_DET_A);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
-
-static void base_disable(void)
-{
-	/* Disable base detection interrupt and disable power to base. */
-	gpio_disable_interrupt(GPIO_BASE_DET_A);
-	base_detect_change(BASE_DISCONNECTED);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * If we jumped to this image and chipset is already in S0, enable
-	 * base.
-	 */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		base_enable();
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_A);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_A);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		base_enable();
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/poppy/battery.c b/board/poppy/battery.c
deleted file mode 100644
index 3f6c4e273d..0000000000
--- a/board/poppy/battery.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-/* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-#define SB_REVIVE_DATA		0x23a7
-
-#if defined(BOARD_SORAKA) || defined(BOARD_LUX)
-static const struct battery_info info = {
-	.voltage_max = 8800,
-	.voltage_normal = 7700,
-	.voltage_min = 6100,
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = -10,
-	.discharging_max_c = 60,
-};
-#elif defined(BOARD_POPPY)
-
-static const struct battery_info info = {
-	.voltage_max = 13200,
-	.voltage_normal = 11550,
-	.voltage_min = 9100,
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-#else
-#error "Battery information not available for board"
-#endif
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATTERY_PRESENT_L) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Check for case where both XCHG and XDSG bits are set indicating that even
- * though the FG can be read from the battery, the battery is not able to be
- * charged or discharged. This situation will happen if a battery disconnect was
- * intiaited via H1 setting the DISCONN signal to the battery. This will put the
- * battery pack into a sleep state and when power is reconnected, the FG can be
- * read, but the battery is still not able to provide power to the system. The
- * calling function returns batt_pres = BP_NO, which instructs the charging
- * state machine to prevent powering up the AP on battery alone which could lead
- * to a brownout event when the battery isn't able yet to provide power to the
- * system. .
- */
-static int battery_check_disconnect(void)
-{
-	int rv;
-	uint8_t data[6];
-
-	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
-	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
-		return BATTERY_DISCONNECTED;
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-#ifdef BOARD_SORAKA
-/*
- * In case of soraka, battery enters an "emergency shutdown" mode when hardware
- * button combo is used to cutoff battery. In order to get out of this mode, EC
- * needs to send SB_REVIVE_DATA.
- *
- * Do not send revive data if:
- * 1. It has already been sent during this boot or
- * 2. Battery was/is in a state other than "BATTERY_DISCONNECTED".
- *
- * Try upto ten times to send the revive data command and if it fails every
- * single time, give up and continue booting on AC power.
- */
-static void battery_revive(void)
-{
-#define MAX_REVIVE_TRIES 10
-	static int battery_revive_done;
-	int tries = MAX_REVIVE_TRIES;
-
-	if (battery_revive_done)
-		return;
-
-	battery_revive_done = 1;
-
-	while (tries--) {
-		if (battery_check_disconnect() != BATTERY_DISCONNECTED)
-			return;
-
-		CPRINTS("Battery is disconnected! Try#%d to revive",
-			MAX_REVIVE_TRIES - tries);
-
-		if (sb_write(SB_MANUFACTURER_ACCESS, SB_REVIVE_DATA) ==
-		    EC_SUCCESS)
-			return;
-	}
-
-	if (battery_check_disconnect() == BATTERY_DISCONNECTED)
-		CPRINTS("Battery is still disconnected! Giving up!");
-}
-#endif
-
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-	int batt_disconnect_status;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Check battery disconnect status. If we are unable to read battery
-	 * disconnect status, then return BP_NOT_SURE. Battery could be in ship
-	 * mode and might require pre-charge current to wake it up. BP_NO is not
-	 * returned here because charger state machine will not provide
-	 * pre-charge current assuming that battery is not present.
-	 */
-	batt_disconnect_status = battery_check_disconnect();
-	if (batt_disconnect_status == BATTERY_DISCONNECT_ERROR)
-		return BP_NOT_SURE;
-
-#ifdef BOARD_SORAKA
-	/*
-	 * Since battery just changed status to present and we are able to read
-	 * disconnect status, try reviving it if necessary.
-	 */
-	battery_revive();
-#endif
-
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Not disconnected
-	 * 3. Initialized
-	 */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	    batt_disconnect_status != BATTERY_NOT_DISCONNECTED ||
-	    battery_init() == 0) {
-		batt_pres = BP_NO;
-	}
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
-
diff --git a/board/poppy/board.c b/board/poppy/board.c
deleted file mode 100644
index 2124faa421..0000000000
--- a/board/poppy/board.c
+++ /dev/null
@@ -1,894 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Poppy board-specific configuration */
-
-#include "adc.h"
-#include "als.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_opt3001.h"
-#include "driver/baro_bmp280.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/bd99992gw.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define USB_PD_PORT_ANX74XX	0
-
-/* Minimum input current limit. */
-#define ILIM_MIN_MA 472
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	if ((signal == GPIO_USB_C0_PD_INT_ODL) &&
-	    !gpio_get_level(GPIO_USB_C0_PD_RST_L))
-		return;
-	else if ((signal == GPIO_USB_C1_PD_INT_ODL) &&
-		 !gpio_get_level(GPIO_USB_C1_PD_RST_L))
-		return;
-
-#ifdef HAS_TASK_PDCMD
-	/* Exchange status with TCPCs */
-	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
-#endif
-}
-
-/* Set PD discharge whenever VBUS detection is high (i.e. below threshold). */
-static void vbus_discharge_handler(void)
-{
-	if (system_get_board_version() >= 2) {
-		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
-	}
-}
-DECLARE_DEFERRED(vbus_discharge_handler);
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-#endif
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
-#ifdef BOARD_LUX
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
-	 * 0.8V @ 45 W, i.e. 56250 uW/mV. Using ADC_MAX_VOLT*56250 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {"PSYS", NPCX_ADC_CH3,
-		      ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1), 2, 0},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc",      NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"als",       NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"charger",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"pmic",      NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"accelgyro", NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_0,
-		.mux_lock = NULL,
-	},
-	{
-		.i2c_port = I2C_PORT_USB_CHARGER_1,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX74XX)
-		return;
-
-	if (mode) {
-		gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	} else {
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	/* Disable TCPC0 (anx3429) power */
-	gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
-
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int reg;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		gpio_set_level(GPIO_PP3300_USB_PD, 1);
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		msleep(10);
-		board_reset_pd_mcu();
-	}
-
-	/*
-	 * TODO: Remove when Poppy is updated with PS8751 A3.
-	 *
-	 * Force PS8751 A2 to wake from low power mode.
-	 * If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 *
-	 * NOTE: PS8751 A3 will wake on any I2C access.
-	 */
-	i2c_read8(NPCX_I2C_PORT0_1, 0x08, 0xA0, &reg);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-#endif
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-static void board_pmic_disable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (0)   - Disable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (00)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x3a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x2a);
-
-	/*
-	 * V100ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (01) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x3a);
-}
-
-static void board_pmic_enable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (1)   - Enable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (00)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x7a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x6a);
-
-	/*
-	 * V100ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (01) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x5a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
-}
-
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
-		board_pmic_enable_slp_s0_vr_decay();
-	else if (state == HOST_SLEEP_EVENT_S0IX_RESUME)
-		board_pmic_disable_slp_s0_vr_decay();
-}
-
-static void board_pmic_init(void)
-{
-	board_report_pmic_fault("SYSJUMP");
-
-	if (system_jumped_late())
-		return;
-
-	/* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x04);
-
-	board_pmic_disable_slp_s0_vr_decay();
-
-	/* VRMODECTRL - disable low-power mode for all rails */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x1f);
-
-	/* Disable power button shutdown timer. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x14, 0x00);
-}
-DECLARE_DEFERRED(board_pmic_init);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
-	 * whenever the EC is not doing SPI flash transactions. This avoids
-	 * floating SPI buffer input (MISO), which causes power leakage (see
-	 * b/64797021).
-	 */
-	NPCX_PUPD_EN1 |= BIT(NPCX_DEVPU1_F_SPI_PUD_EN);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-
-	/* Enable sensors power supply */
-	gpio_set_level(GPIO_PP1800_DX_SENSOR, 1);
-	gpio_set_level(GPIO_PP3300_DX_SENSOR, 1);
-
-	/* Enable VBUS interrupt */
-	if (system_get_board_version() == 0) {
-		/*
-		 * crosbug.com/p/61929: rev0 does not have VBUS detection,
-		 * force detection on both ports.
-		 */
-		gpio_set_flags(GPIO_USB_C0_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
-		gpio_set_flags(GPIO_USB_C1_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
-
-		vbus0_evt(GPIO_USB_C0_VBUS_WAKE_L);
-		vbus1_evt(GPIO_USB_C1_VBUS_WAKE_L);
-	} else {
-		gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
-		gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
-	}
-
-	/* Enable pericom BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/*
-	 * Set unused GPIO_LED_YELLO_C0[_OLD] as INPUT | PULL_UP
-	 * for better S0ix/S3 power
-	 */
-	if (system_get_board_version() >= 5)
-		gpio_set_flags(GPIO_LED_YELLOW_C0_OLD,
-			GPIO_INPUT | GPIO_PULL_UP);
-	else
-		gpio_set_flags(GPIO_LED_YELLOW_C0,
-			GPIO_INPUT | GPIO_PULL_UP);
-
-#ifdef BOARD_SORAKA
-	/*
-	 * TODO(b/64503543): Add proper options(#ifdef ) for Non-LTE SKU
-	 * Set unused LTE related pins as INPUT | PULL_UP
-	 * for better S0ix/S3 power
-	 */
-	if (system_get_board_version() >= 4) {
-		gpio_set_flags(GPIO_WLAN_PE_RST,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_PP3300_DX_LTE,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_GPS_OFF_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_BODY_SAR_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_OFF_ODL,
-			GPIO_INPUT | GPIO_PULL_UP);
-	}
-#endif
-
-#ifndef BOARD_LUX
-	/*
-	 * see (b/111215677): setting the internal PU/PD of the unused pin
-	 * GPIO10 affects the ball K10 when it is selected to CR_SIN.
-	 * Disabing the WKINEN bit of GPIO10 insteading setting its PU/PD to
-	 * bypass this issue.
-	 */
-	NPCX_WKINEN(MIWU_TABLE_1, MIWU_GROUP_2) &= 0xFE;
-#endif
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
-
-	/* Initialize PMIC */
-	hook_call_deferred(&board_pmic_init_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Buffer the AC present GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source VBUS on the port */
-	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
-						       GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTF("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_USB_C0_CHARGE_L, 1);
-		gpio_set_level(GPIO_USB_C1_CHARGE_L, 1);
-	} else {
-#ifdef BOARD_LUX
-		/* Disable cross-power with base, charger task will reenable. */
-		board_enable_base_power(0);
-#endif
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Adjust ILIM according to measurements to eliminate overshoot. */
-	charge_ma = (charge_ma - 500) * 31 / 32 + 472;
-	/* 5V is significantly more accurate than other voltages. */
-	if (charge_mv > 5000)
-		charge_ma -= 52;
-
-	charge_set_input_current_limit(MAX(charge_ma, ILIM_MIN_MA), charge_mv);
-}
-
-void board_hibernate(void)
-{
-	CPRINTS("Triggering PMIC shutdown.");
-	uart_flush_output();
-
-	/* Trigger PMIC shutdown. */
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		       0x49, 0x01)) {
-		/*
-		 * If we can't tell the PMIC to shutdown, instead reset
-		 * and don't start the AP. Hopefully we'll be able to
-		 * communicate with the PMIC next time.
-		 */
-		CPRINTS("PMIC i2c failed.");
-		system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
-	}
-
-	/* Await shutdown. */
-	while (1)
-		;
-}
-
-int board_get_version(void)
-{
-	static int ver = -1;
-	uint8_t id4;
-
-	if (ver != -1)
-		return ver;
-
-	ver = 0;
-
-	/* First 3 strappings are binary. */
-	if (gpio_get_level(GPIO_BOARD_VERSION1))
-		ver |= 0x01;
-	if (gpio_get_level(GPIO_BOARD_VERSION2))
-		ver |= 0x02;
-	if (gpio_get_level(GPIO_BOARD_VERSION3))
-		ver |= 0x04;
-
-	/*
-	 * 4th bit is using tristate strapping, ternary encoding:
-	 * Hi-Z (id4=2) => 0, (id4=0) => 1, (id4=1) => 2
-	 */
-	id4 = gpio_get_ternary(GPIO_BOARD_VERSION4);
-	ver |= ((id4 + 1) % 3) * 0x08;
-
-	CPRINTS("Board ID = %d", ver);
-
-	return ver;
-}
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-#ifdef BOARD_SORAKA
-const mat33_fp_t lid_standard_ref = {
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{FLOAT_TO_FP(1),  0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-/* For rev3 and older */
-const mat33_fp_t lid_standard_ref_old = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-#else
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-#endif
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[LID_GYRO] = {
-	 .name = "Lid Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-	[LID_MAG] = {
-	 .name = "Lid Mag",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_MAG,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = BIT(11), /* 16LSB / uT, fixed */
-	 .rot_standard_ref = &mag_standard_ref,
-	 .min_frequency = BMM150_MAG_MIN_FREQ,
-	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
-	[LID_ALS] = {
-	 .name = "Light",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_OPT3001,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &opt3001_drv,
-	 .drv_data = &g_opt3001_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = OPT3001_I2C_ADDR_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1; uscale = 0 */
-	 .min_frequency = OPT3001_LIGHT_MIN_FREQ,
-	 .max_frequency = OPT3001_LIGHT_MAX_FREQ,
-	 .config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-#ifdef BOARD_SORAKA
-static void board_sensor_init(void)
-{
-	/* Old soraka use a different reference matrix */
-	if (system_get_board_version() <= 3) {
-		motion_sensors[LID_ACCEL].rot_standard_ref =
-			&lid_standard_ref_old;
-		motion_sensors[LID_GYRO].rot_standard_ref =
-			&lid_standard_ref_old;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_sensor_init, HOOK_PRIO_DEFAULT);
-#endif
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-int board_has_working_reset_flags(void)
-{
-	int version = system_get_board_version();
-
-	/* Boards Rev1 and Rev2 will lose reset flags on power cycle. */
-	if ((version == 1) || (version == 2))
-		return 0;
-
-	/* All other board versions should have working reset flags */
-	return 1;
-}
diff --git a/board/poppy/board.h b/board/poppy/board.h
deleted file mode 100644
index bf4acfe8ff..0000000000
--- a/board/poppy/board.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Eve board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Remove this config before production.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_DPTF
-#ifndef BOARD_LUX
-#define CONFIG_DPTF_MULTI_PROFILE
-#endif
-#define CONFIG_EMULATED_SYSRQ
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
-#define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* Port80 */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-#ifdef BOARD_LUX
-#define CONFIG_UART_PAD_SWITCH
-
-#define CONFIG_EC_EC_COMM_CLIENT
-#define CONFIG_EC_EC_COMM_BATTERY
-#define CONFIG_CRC8
-#endif
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW /* This, or just RAMP? */
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#ifdef BOARD_LUX
-#define CONFIG_CHARGER_OTG
-#define CONFIG_CHARGER_PSYS_READ
-#endif
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* Sensor */
-#define CONFIG_ALS
-#define CONFIG_ALS_OPT3001
-#define ALS_COUNT 1
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_MAG_CALIBRATE
-/* Lower maximal ODR to 100Hz */
-#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 100000
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* USB */
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_ANX3429
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_0
-#define I2C_PORT_ALS		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-
-/* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	LID_MAG,
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-#ifdef BOARD_LUX
-	ADC_PSYS,
-#endif
-	ADC_CH_COUNT
-};
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-int board_get_version(void);
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-void base_detect_interrupt(enum gpio_signal signal);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/poppy/build.mk b/board/poppy/build.mk
deleted file mode 100644
index df32a7ca8f..0000000000
--- a/board/poppy/build.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-board-$(BOARD_LUX)+=base_detect_lux.o
-board-$(BOARD_POPPY)+=base_detect_poppy.o
-board-$(BOARD_SORAKA)+=base_detect_poppy.o
diff --git a/board/poppy/ec.tasklist b/board/poppy/ec.tasklist
deleted file mode 100644
index 7591137bc9..0000000000
--- a/board/poppy/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, 800) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, 800) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, 800) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, 800) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, 768) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, 800) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, 880) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 840) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, 960) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, 800) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1000) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1000)
diff --git a/board/poppy/gpio.inc b/board/poppy/gpio.inc
deleted file mode 100644
index 286085d39c..0000000000
--- a/board/poppy/gpio.inc
+++ /dev/null
@@ -1,174 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#ifdef BOARD_LUX
-GPIO_INT(PCH_SLP_S3_L,		PIN(2, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-#else
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-#endif /* CONFIG_HOSTCMD_ESPI_VW_SLP_S3 */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-#endif
-GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(6, 7), GPIO_INT_BOTH,			lid_interrupt)
-/* TODO(b/35585396): Make use of reverse dock signal. */
-GPIO_INT(REVERSE_DOCK,		PIN(B, 7), GPIO_INT_BOTH,			lid_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(WP_L,			PIN(4, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
-GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus0_evt)
-GPIO_INT(USB_C1_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus1_evt)
-GPIO_INT(USB_C0_BC12_INT_L,	PIN(D, 3), GPIO_INT_FALLING,			usb0_evt)
-GPIO_INT(USB_C1_BC12_INT_L,	PIN(3, 3), GPIO_INT_FALLING,			usb1_evt)
-#ifdef BOARD_LUX
-GPIO_INT(ACCELGYRO3_INT_L,	PIN(7, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
-#else
-GPIO_INT(ACCELGYRO3_INT_L,	PIN(3, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
-#endif
-GPIO_INT(BASE_DET_A,		PIN(4, 5), GPIO_INT_BOTH,			base_detect_interrupt)
-GPIO_INT(USB_C0_CABLE_DET,      PIN(D, 2), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
-#ifdef BOARD_LUX
-GPIO_INT(UART_MAIN_RX,		PIN(6, 4), GPIO_INT_FALLING,			uart_default_pad_rx_interrupt)
-#endif
-
-GPIO(PCH_RTCRST,		PIN(2, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC (>= rev4) */
-GPIO(ENABLE_BACKLIGHT,		PIN(2, 6), GPIO_OUT_LOW)			/* Enable Backlight */
-GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
-GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
-GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
-GPIO(PCH_ACOK,			PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
-GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(4, 1), GPIO_ODR_HIGH)			/* Power Button to SOC */
-GPIO(EC_PLATFORM_RST,		PIN(A, 6), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
-GPIO(BATTERY_PRESENT_L,		PIN(3, 4), GPIO_INPUT)				/* Battery Present */
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_INPUT | GPIO_PULL_UP)		/* H1 Reset (unused) */
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
-GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)		/* PMIC interrupt */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INPUT)
-#endif
-
-/* Sensor interrupts, not implemented yet */
-GPIO(ALS_INT_L,			PIN(2, 5), GPIO_INPUT)
-
-/* TODO(b/35585396): Make use of these GPIOs */
-GPIO(PP1800_DX_SENSOR,		PIN(1, 4), GPIO_OUTPUT)
-GPIO(PP3300_DX_SENSOR,		PIN(2, 1), GPIO_OUTPUT)
-GPIO(PP3300_USB_PD,		PIN(2, 0), GPIO_OUTPUT)
-/* end of TODO */
-
-GPIO(PP3300_DX_LTE,		PIN(0, 5), GPIO_OUT_LOW)
-
-#ifndef BOARD_LUX
-GPIO(WLAN_PE_RST,		PIN(1, 2), GPIO_OUTPUT)
-GPIO(LTE_GPS_OFF_L,		PIN(0, 0), GPIO_ODR_HIGH)
-GPIO(LTE_BODY_SAR_L,		PIN(0, 1), GPIO_ODR_HIGH)
-GPIO(LTE_OFF_ODL,		PIN(8, 0), GPIO_ODR_LOW)
-GPIO(LTE_WAKE_L,		PIN(7, 1), GPIO_INPUT)
-#endif
-
-#ifdef BOARD_LUX
-GPIO(WFCAM_VSYNC,		PIN(7, 1), GPIO_INPUT)
-#endif
-
-/* Set unused pins as Input+PU */
-#ifdef BOARD_LUX
-GPIO(TP_EC_GPIO_00,		PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_01,		PIN(0, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_36,		PIN(3, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_80,		PIN(8, 0), GPIO_INPUT | GPIO_PULL_UP)
-#else
-GPIO(TP_EC_GPIO_06,		PIN(0, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_22,		PIN(2, 2), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-GPIO(TP_EC_GPIO_16,		PIN(1, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_23,		PIN(2, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_B6,		PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-#ifdef BOARD_LUX
-GPIO(UART_ALT_RX,		PIN(1, 0), GPIO_INPUT)
-GPIO(UART_ALT_TX,		PIN(1, 1), GPIO_INPUT)
-GPIO(EC_COMM_PD,		PIN(1, 5), GPIO_ODR_HIGH)
-GPIO(EC_COMM_PU,		PIN(0, 7), GPIO_INPUT)
-GPIO(PPVAR_VAR_BASE,		PIN(1, 2), GPIO_OUT_LOW)
-#else
-GPIO(PP3300_DX_BASE,		PIN(1, 1), GPIO_OUT_LOW)
-GPIO(TP_EC_GPIO_07,		PIN(0, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(TP_EC_GPIO_10,		PIN(1, 0), GPIO_INPUT)
-GPIO(TP_EC_GPIO_15,		PIN(1, 5), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C0_0_USBC_3V3_SCL */
-GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C0_0_USBC_3V3_SDA */
-GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C0_1_3V3_SCL */
-GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C0_1_3V3_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C1_3V3_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C1_3V3_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C2_PMIC_3V3_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C2_PMIC_3V3_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)				/* EC_I2C3_SENSOR_1V8_SCL */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)				/* EC_I2C3_SENSOR_1V8_SDA */
-
-#ifdef BOARD_LUX
-GPIO(USB_C0_5V_EN,		PIN(0, 6), GPIO_OUT_LOW)			/* C0 5V Enable */
-#else
-GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW)			/* C0 5V Enable */
-#endif
-GPIO(USB_C0_3A_EN,		PIN(6, 6), GPIO_OUT_LOW)			/* C0 Enable 3A */
-GPIO(USB_C0_CHARGE_L,		PIN(C, 0), GPIO_OUT_LOW)			/* C0 Charge enable */
-GPIO(USB_C1_5V_EN,		PIN(B, 1), GPIO_OUT_LOW)			/* C1 5V Enable */
-GPIO(USB_C1_3A_EN,		PIN(3, 5), GPIO_OUT_LOW)			/* C1 3A Enable */
-GPIO(USB_C1_CHARGE_L,		PIN(C, 3), GPIO_OUT_LOW)			/* C1 Charge enable */
-GPIO(USB_C0_PD_RST_L,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(A, 5), GPIO_INPUT)				/* C1 DP Hotplug Detect */
-GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
-GPIO(USB2_OTG_ID,		PIN(A, 1), GPIO_OUT_LOW)			/* OTG ID */
-GPIO(USB2_OTG_VBUSSENSE,	PIN(9, 5), GPIO_OUT_LOW)			/* OTG VBUS Sense */
-
-/* LEDs (2 colors on each port) */
-GPIO(LED_YELLOW_C0,		PIN(2, 4), GPIO_OUT_LOW)			/* This is from rev5 */
-GPIO(LED_YELLOW_C0_OLD,		PIN(3, 2), GPIO_OUT_LOW)			/* This is for rev1 to rev4 */
-GPIO(LED_WHITE_C0,		PIN(C, 6), GPIO_OUT_LOW)
-GPIO(LED_YELLOW_C1,		PIN(3, 1), GPIO_OUT_LOW)
-GPIO(LED_WHITE_C1,		PIN(3, 0), GPIO_OUT_LOW)
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 4), GPIO_INPUT)				/* Board ID bit0 */
-GPIO(BOARD_VERSION2,		PIN(C, 2), GPIO_INPUT)				/* Board ID bit1 */
-GPIO(BOARD_VERSION3,		PIN(1, 3), GPIO_INPUT)				/* Board ID bit2 */
-GPIO(BOARD_VERSION4,		PIN(1, 7), GPIO_INPUT)				/* Board ID strap 3 (ternary) */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_USBC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
diff --git a/board/poppy/led.c b/board/poppy/led.c
deleted file mode 100644
index 0c2d7f1832..0000000000
--- a/board/poppy/led.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	int yellow_c0 = (system_get_board_version() >= 5) ?
-			GPIO_LED_YELLOW_C0 : GPIO_LED_YELLOW_C0_OLD;
-	gpio_set_level(port ? GPIO_LED_YELLOW_C1 : yellow_c0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_LED_WHITE_C1 : GPIO_LED_WHITE_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/board/poppy/usb_pd_policy.c b/board/poppy/usb_pd_policy.c
deleted file mode 100644
index a32b77bbe7..0000000000
--- a/board/poppy/usb_pd_policy.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-					     GPIO_USB_C0_5V_EN;
-	enum gpio_signal gpio_3a_en = port ? GPIO_USB_C1_3A_EN :
-					     GPIO_USB_C0_3A_EN;
-
-	if (system_get_board_version() >= 1) {
-		/*
-		 * For rev1 and beyond, 1.5 vs 3.0 A limit is controlled by a
-		 * dedicated gpio where high = 3.0A and low = 1.5A. VBUS on/off
-		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
-		 * can remain outputs.
-		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-	} else {
-		/*
-		 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-		 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-		 * setting a minimum OCP current of 3186 mA.
-		 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put
-		 * a 33k resistor on ILIM, setting a minimum OCP current of
-		 * 1505 mA.
-		 */
-		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
-		gpio_set_level(gpio_5v_en, vbus_en[port]);
-		gpio_set_flags(gpio_5v_en, flags);
-	}
-}
-
-void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	if (system_get_board_version() >= 2)
-		pd_set_vbus_discharge(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (system_get_board_version() >= 2 && prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
-				      GPIO_USB_C0_VBUS_WAKE_L);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-}
diff --git a/board/poppy/vif_override.xml b/board/poppy/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/poppy/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/primus/battery.c b/board/primus/battery.c
deleted file mode 100644
index e9e822f2e8..0000000000
--- a/board/primus/battery.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Primus battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "LNV-5B11F21946",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 251,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "LNV-5B11F21953",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 250,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	[BATTERY_CELXPERT] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "LNV-5B11F21941",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 487,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SUNWODA;
diff --git a/board/primus/board.c b/board/primus/board.c
deleted file mode 100644
index 0881ab1c86..0000000000
--- a/board/primus/board.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "charge_state_v2.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "keyboard_8042_sharedlib.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "pwm.h"
-#include "registers.h"
-#include "switch.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-#define KBLIGHT_LED_ON_LVL 100
-#define KBLIGHT_LED_OFF_LVL 0
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-__override void board_cbi_init(void)
-{
-	config_usb_db_type();
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-	pwm_set_duty(PWM_CH_KBLIGHT, KBLIGHT_LED_ON_LVL);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-	pwm_set_duty(PWM_CH_KBLIGHT, KBLIGHT_LED_OFF_LVL);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO(b/181508008): tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-
-	batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
-
-static void keyboard_init(void)
-{
-	/*
-	 * Set T15(KSI0/KSO11) to Lock key(KSI3/KSO9)
-	 */
-	set_scancode_set2(0, 11, get_scancode_set2(3, 9));
-}
-DECLARE_HOOK(HOOK_INIT, keyboard_init, HOOK_PRIO_DEFAULT);
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Follow OEM request to limit the input current to
-	 * 97% negotiated limit.
-	 */
-	charge_ma = charge_ma * 97 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
-}
diff --git a/board/primus/board.h b/board/primus/board.h
deleted file mode 100644
index 96562ec7a4..0000000000
--- a/board/primus/board.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Primus board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* Sensors */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-#undef CONFIG_GMR_TABLET_MODE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#undef  CONFIG_USB_PD_TCPM_NCT38XX
-#define CONFIG_USB_PD_TCPM_RT1715
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_USB_C0_TCPC		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC		NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_C1_PPC_BC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_C1_BC12		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_C1_RT		NPCX_I2C_PORT3_0
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT5_0
-#define I2C_PORT_USB_A0_A1_MIX		NPCX_I2C_PORT6_1
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* LED */
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 91
-
-#define CONFIG_FANS			FAN_CH_COUNT
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* PS2 defines */
-#define CONFIG_8042_AUX
-#define CONFIG_PS2
-#define CONFIG_CMD_PS2
-/* Button */
-#undef CONFIG_VOLUME_BUTTONS
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_SSD,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_MEMORY,
-	ADC_TEMP_SENSOR_5_USBC,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_SSD,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_MEMORY,
-	TEMP_SENSOR_5_USBC,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT
-};
-
-enum battery_type {
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_CELXPERT,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED2_WHITE = 0,	/* PWM0 (white charger) */
-	PWM_CH_TKP_A_LED_N,		/* PWM1 (LOGO led on A cover) */
-	PWM_CH_LED1_AMBER,		/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (power) */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/primus/build.mk b/board/primus/build.mk
deleted file mode 100644
index d6fe9b4808..0000000000
--- a/board/primus/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Primus board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=ps2.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/primus/charger.c b/board/primus/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/primus/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/primus/ec.tasklist b/board/primus/ec.tasklist
deleted file mode 100644
index c0a5194e89..0000000000
--- a/board/primus/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) \
-	TASK_NOTEST(LOGOLED, logoled_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/primus/fans.c b/board/primus/fans.c
deleted file mode 100644
index d966056331..0000000000
--- a/board/primus/fans.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/180681346): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/primus/fw_config.c b/board/primus/fw_config.c
deleted file mode 100644
index 9506e778b5..0000000000
--- a/board/primus/fw_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union primus_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for primus if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union primus_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Primus FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
-}
-
-union primus_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
diff --git a/board/primus/fw_config.h b/board/primus/fw_config.h
deleted file mode 100644
index cbccbd07a9..0000000000
--- a/board/primus/fw_config.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_PRIMUS_FW_CONFIG_H_
-#define __BOARD_PRIMUS_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Primus board.
- *
- * Source of truth is the project/brya/primus/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1,
-	DB_USB_ABSENT2 = 15
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union primus_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union primus_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_PRIMUS_FW_CONFIG_H_ */
diff --git a/board/primus/gpio.inc b/board/primus/gpio.inc
deleted file mode 100644
index 4aa00b9ac0..0000000000
--- a/board/primus/gpio.inc
+++ /dev/null
@@ -1,138 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(A, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-/* USB C1 gpio pins are mapped to schematic USB C2 */
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(0, 2), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_RT_INT_ODL,              PIN(9, 7), GPIO_INT_FALLING, retimer_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(E, 1), GPIO_INPUT)
-GPIO(KBD_BL_DTCT_N,                  PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_RT_SCL,        PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_RT_SDA,        PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_A1_MIX_SCL,       PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_A1_MIX_SDA,       PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(9, 5), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_RT_RST_ODL,              PIN(A, 7), GPIO_ODR_LOW)
-GPIO(PDEV_STP_N,                     PIN(9, 6), GPIO_ODR_HIGH)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,              PIN(5, 0), GPIO_ODR_LOW)
-GPIO(USB_C0_FRS_EN,                  PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,               PIN(B, 5), GPIO_ODR_LOW)
-GPIO(TBT_PWR_EN,                     PIN(D, 4), GPIO_OUT_LOW)
-GPIO(TP4_RESET,                      PIN(9, 3), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(FAN_ID,                         PIN(4, 1), GPIO_INPUT)
-GPIO(USB_C0_OC_ODL,                  PIN(5, 6), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,                  PIN(B, 4), GPIO_ODR_HIGH)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x3C), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2, GPIO42/ADC3/RI_L */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)               /* GPIOF0/ADC9 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* PS2 function */
-/* PS/2 channel 1 for aux device */
-ALTERNATE(PIN_MASK(6, 0x0C), 0, MODULE_PS2, 0)               /* PS2_CLK1/GPIO62, PS2_DAT1/GPIO63 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS# */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST# */
-UNUSED(PIN(6, 6))       /* GPO66/ARM#_X86 */
-UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
-/* Pre-configured PSL balls:  J8  K6 */
-
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
diff --git a/board/primus/i2c.c b/board/primus/i2c.c
deleted file mode 100644
index 3a4fe69b0c..0000000000
--- a/board/primus/i2c.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C1
-		 * TODO(b/191178381) Need to check the signals with a scope
-		 * before raising to 1MHz.
-		 */
-		.name = "tcpc0",
-		.port = I2C_PORT_USB_C0_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0,1",
-		.port = I2C_PORT_USB_C0_C1_PPC_BC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0,2",
-		.port = I2C_PORT_USB_C0_C1_RT,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
-	},
-	{
-		/* I2C4
-		 * TODO(b/191178381) Need to check the signals with a scope
-		 * before raising to 1MHz.
-		 */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "usb_mix0,1",
-		.port = I2C_PORT_USB_A0_A1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_USB_A0_A1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_A0_A1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/primus/keyboard.c b/board/primus/keyboard.c
deleted file mode 100644
index 5b45b60b19..0000000000
--- a/board/primus/keyboard.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfb, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config primus_kb = {
-	.num_top_row_keys = 14,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_PREV_TRACK,		/* T8 */
-		TK_PLAY_PAUSE,		/* T9 */
-		TK_NEXT_TRACK,		/* T10 */
-		TK_MICMUTE,		/* T11 */
-		TK_VOL_MUTE,		/* T12 */
-		TK_VOL_DOWN,		/* T13 */
-		TK_VOL_UP,		/* T14 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config *
-board_vivaldi_keybd_config(void)
-{
-	return &primus_kb;
-}
diff --git a/board/primus/led.c b/board/primus/led.c
deleted file mode 100644
index 3a8da5ac32..0000000000
--- a/board/primus/led.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Primus specific PWM LED settings. */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "power.h"
-#include "pwm.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ## args)
-
-#define LED_ON_LVL		100
-#define LED_OFF_LVL		0
-#define LED_BAT_S3_OFF_TIME_MS	3000
-#define LED_BAT_S3_TICK_MS	50
-#define LED_BAT_S3_PWM_RESCALE	5
-#define LED_TOTAL_TICKS		6
-#define TICKS_STEP1_BRIGHTER	0
-#define TICKS_STEP2_DIMMER	(1000 / LED_BAT_S3_TICK_MS)
-#define TICKS_STEP3_OFF		(2 * TICKS_STEP2_DIMMER)
-#define LED_ONE_SEC		(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_LOGO_TICK_SEC	(LED_ONE_SEC / 4)
-/* Total on/off duration in a period */
-#define PERIOD			(LED_LOGO_TICK_SEC * 2)
-#define LED_ON			1
-#define LED_OFF			EC_LED_COLOR_COUNT
-#define LED_EVENT_SUSPEND	TASK_EVENT_CUSTOM_BIT(0)
-#define LED_EVENT_200MS_TICK	TASK_EVENT_CUSTOM_BIT(1)
-
-static int tick;
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		pwm_set_duty(PWM_CH_LED1_AMBER, LED_ON_LVL);
-		pwm_set_duty(PWM_CH_LED2_WHITE, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		pwm_set_duty(PWM_CH_LED2_WHITE, LED_ON_LVL);
-		pwm_set_duty(PWM_CH_LED1_AMBER, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		pwm_set_duty(PWM_CH_LED1_AMBER, LED_OFF_LVL);
-		pwm_set_duty(PWM_CH_LED2_WHITE, LED_OFF_LVL);
-		break;
-	}
-}
-
-static void led_set_battery(void)
-{
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(EC_LED_COLOR_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-void led_set_color_power(int onoff_status)
-{
-	/* primus logo led and power led have same behavior. */
-	if (onoff_status == LED_ON) {
-		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_ON_LVL);
-		pwm_set_duty(PWM_CH_LED4,        LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_OFF_LVL);
-		pwm_set_duty(PWM_CH_LED4,        LED_OFF_LVL);
-	}
-}
-
-#define AC_DISCONNECTED (-1)
-
-static void led_set_power(void)
-{
-	static int plug_ac_countdown;
-	static int ticks;
-
-	if (plug_ac_countdown > 0) {
-		ticks = (ticks + 1) % PERIOD;
-		plug_ac_countdown--;
-		if (ticks < LED_LOGO_TICK_SEC)
-			led_set_color_power(LED_OFF);
-		else
-			led_set_color_power(LED_ON);
-	} else if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_ON);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		led_set_color_power(LED_OFF);
-
-	/* Check AC_PRESENT */
-	if (!extpower_is_present())
-		plug_ac_countdown = AC_DISCONNECTED;
-	else if (plug_ac_countdown == AC_DISCONNECTED)
-		/* AC power was plugged in (previous state was "disconnected"),
-		 * set plug_ac_countdown for amount of ticks left
-		 */
-		plug_ac_countdown = LED_TOTAL_TICKS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_power(LED_ON);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Called by hook task every 200 ms */
-static void led_tick(void)
-{
-	task_set_event(TASK_ID_LOGOLED, LED_EVENT_200MS_TICK);
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-static void suspend_led_update(void)
-{
-	while (1) {
-		tick++;
-
-		/* HOOK_CHIPSET_SUSPEND will be called when POWER_S0S0ix,
-		 * if we are not transitioning to suspend, we should break here.
-		 */
-		if (!chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_ANY_SUSPEND))
-			break;
-
-		/* 1s gradual on, 1s gradual off, 3s off */
-		if (tick <= TICKS_STEP2_DIMMER) {
-			/* increase 5 duty every 50ms until PWM=100
-			 * enter here 20 times, total duartion is 1sec
-			 * A-cover and power button led are shared same
-			 * behavior.
-			 */
-			pwm_set_duty(PWM_CH_TKP_A_LED_N,
-				tick * LED_BAT_S3_PWM_RESCALE);
-			pwm_set_duty(PWM_CH_LED4,
-				tick * LED_BAT_S3_PWM_RESCALE);
-			msleep(LED_BAT_S3_TICK_MS);
-		} else if (tick <= TICKS_STEP3_OFF) {
-			/* decrease 5 duty every 50ms until PWM=0
-			 * enter here 20 times, total duartion is 1sec
-			 * A-cover and power button led are shared same
-			 * behavior.
-			 */
-			pwm_set_duty(PWM_CH_TKP_A_LED_N, (TICKS_STEP3_OFF
-				- tick) * LED_BAT_S3_PWM_RESCALE);
-			pwm_set_duty(PWM_CH_LED4, (TICKS_STEP3_OFF
-				- tick) * LED_BAT_S3_PWM_RESCALE);
-			msleep(LED_BAT_S3_TICK_MS);
-		} else {
-			tick = TICKS_STEP1_BRIGHTER;
-			msleep(LED_BAT_S3_OFF_TIME_MS);
-		}
-	}
-}
-
-static void suspend_led_init(void)
-{
-	task_set_event(TASK_ID_LOGOLED, LED_EVENT_SUSPEND);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, suspend_led_init, HOOK_PRIO_DEFAULT);
-
-void logoled_task(void *u)
-{
-	uint32_t evt;
-
-	while (1) {
-		evt = task_wait_event(-1);
-
-		if (evt & LED_EVENT_SUSPEND) {
-			tick = TICKS_STEP2_DIMMER;
-			suspend_led_update();
-		}
-
-		if (evt & LED_EVENT_200MS_TICK) {
-			if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-				led_set_power();
-			if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-				led_set_battery();
-		}
-	}
-}
diff --git a/board/primus/ps2.c b/board/primus/ps2.c
deleted file mode 100644
index 2a605b37e5..0000000000
--- a/board/primus/ps2.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "hooks.h"
-#include "keyboard_8042.h"
-#include "ps2_chip.h"
-
-void send_aux_data_to_device(uint8_t data)
-{
-	ps2_transmit_byte(NPCX_PS2_CH1, data);
-}
-
-static void board_init(void)
-{
-	ps2_enable_channel(NPCX_PS2_CH1, 1, send_aux_data_to_host_interrupt);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/primus/pwm.c b/board/primus/pwm.c
deleted file mode 100644
index 6529443651..0000000000
--- a/board/primus/pwm.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED2_WHITE] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_TKP_A_LED_N] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED1_AMBER] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_LED4] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn off LOGO/power/battery led
-	 */
-	pwm_enable(PWM_CH_LED1_AMBER, 1);
-	pwm_set_duty(PWM_CH_LED1_AMBER, 0);
-	pwm_enable(PWM_CH_LED2_WHITE, 1);
-	pwm_set_duty(PWM_CH_LED2_WHITE, 0);
-	pwm_enable(PWM_CH_TKP_A_LED_N, 1);
-	pwm_set_duty(PWM_CH_TKP_A_LED_N, 0);
-	pwm_enable(PWM_CH_LED4, 1);
-	pwm_set_duty(PWM_CH_LED4, 0);
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	/* TODO(b/190518315)
-	 * Check if need to turn to 100% after with chassis.
-	 */
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/primus/sensors.c b/board/primus/sensors.c
deleted file mode 100644
index 33ea302a2a..0000000000
--- a/board/primus/sensors.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "adc_chip.h"
-#include "hooks.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_SSD] = {
-		.name = "TEMP_SSD",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_MEMORY] = {
-		.name = "TEMP_MEMORY",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_5_USBC] = {
-		.name = "TEMP_USBC",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_SSD] = {
-		.name = "SSD",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SSD
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_MEMORY] = {
-		.name = "MEMORY",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_MEMORY
-	},
-	[TEMP_SENSOR_5_USBC] = {
-		.name = "USBC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_5_USBC
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/195901486): update for Alder Lake/primus
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-static const struct ec_thermal_config thermal_ssd = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/*
- * TODO(b/195901486): update for Alder Lake/primus
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/*
- * TODO(b/195901486): Thermal table need to be fine tuned.
- */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_SSD]	= thermal_ssd,
-	[TEMP_SENSOR_3_CHARGER]	= thermal_inductor,
-	[TEMP_SENSOR_4_MEMORY]	= thermal_inductor,
-	[TEMP_SENSOR_5_USBC]	= thermal_inductor,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/primus/usbc_config.c b/board/primus/usbc_config.c
deleted file mode 100644
index 6e5c14bb0d..0000000000
--- a/board/primus/usbc_config.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_TCPC,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_RT,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_RT,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC_BC,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-void config_usb_db_type(void)
-{
-	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
-
-	/*
-	 * TODO(b/180434685): implement multiple DB types
-	 */
-
-	CPRINTS("Configured USB DB type number is %d", db_type);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = GPIO_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C1) {
-		rst_signal = GPIO_USB_C1_RT_RST_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		gpio_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-
-		/* This will allow power saving on BB retimer */
-		gpio_set_level(GPIO_TBT_PWR_EN, 1);
-	} else {
-		gpio_set_level(rst_signal, 0);
-		msleep(1);
-		gpio_set_level(GPIO_TBT_PWR_EN, 0);
-	}
-	return EC_SUCCESS;
-}
-
-__override int bb_retimer_reset(const struct usb_mux *me)
-{
-	/*
-	 * TODO(b/200194309): Remove this once transition to
-         * QS Silicon is complete
-	 */
-	bb_retimer_power_enable(me, false);
-	msleep(5);
-	bb_retimer_power_enable(me, true);
-	msleep(25);
-
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* Using RT1716, no reset available for TCPC on port 0/ port 2 */
-}
-
-static void board_tcpc_init(void)
-{
-
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/primus/usbc_config.h b/board/primus/usbc_config.h
deleted file mode 100644
index 8bc1918c02..0000000000
--- a/board/primus/usbc_config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Primus board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/primus/vif_override.xml b/board/primus/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/primus/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/puff/board.c b/board/puff/board.c
deleted file mode 100644
index b71d6670aa..0000000000
--- a/board/puff/board.c
+++ /dev/null
@@ -1,937 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/ina3221.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_TCPPC_INT_ODL)
-		sn5s330_interrupt(0);
-}
-
-int ppc_get_alert_status(int port)
-{
-	return gpio_get_level(GPIO_USB_C0_TCPPC_INT_ODL) == 0;
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	if (signal == GPIO_USB_C0_TCPC_INT_ODL)
-		schedule_deferred_pd_interrupt(0);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int level;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-			   TCPC_FLAGS_RESET_ACTIVE_HIGH);
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	return status;
-}
-
-/* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Blink alert if insufficient power per system_can_boot_ap(). */
-	int insufficient_power =
-		(charge_ma * charge_mv) <
-		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
-	led_alert(insufficient_power);
-}
-
-static uint8_t usbc_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (!gpio_get_level(GPIO_USB_A2_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_USB_A3_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (ec_config_get_usb4_present() && !gpio_get_level(GPIO_USB_A4_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (usbc_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-/*
- * Barrel jack power supply handling
- *
- * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
- * barrel jack is connected, and the USB-C port can bring the EC up fine in
- * dead-battery mode. Both the USB-C and barrel jack switches do reverse
- * protection, so we're safe to turn one on then the other off- but we should
- * only do that if the system is off since it might still brown out.
- */
-
-/*
- * Barrel-jack power adapter ratings.
- */
-static const struct {
-	int voltage;
-	int current;
-} bj_power[] = {
-	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
-	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
-};
-
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
-/* Debounced connection state of the barrel jack */
-static int8_t adp_connected = -1;
-static void adp_connect_deferred(void)
-{
-	struct charge_port_info pi = { 0 };
-	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Debounce */
-	if (connected == adp_connected)
-		return;
-	if (connected) {
-		unsigned int bj = ec_config_get_bj_power();
-
-		pi.voltage = bj_power[bj].voltage;
-		pi.current = bj_power[bj].current;
-	}
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &pi);
-	adp_connected = connected;
-}
-DECLARE_DEFERRED(adp_connect_deferred);
-
-/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
-void adp_connect_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
-}
-
-static void adp_state_init(void)
-{
-	/*
-	 * Initialize all charge suppliers to 0. The charge manager waits until
-	 * all ports have reported in before doing anything.
-	 */
-	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
-		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
-			charge_manager_update_charge(j, i, NULL);
-	}
-
-	/* Report charge state from the barrel jack. */
-	adp_connect_deferred();
-}
-DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_GREEN]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* USB-C TCPC Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-};
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CORE] = {
-		.name = "Core",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 2400,
-	.rpm_max = 4300,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(78),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(58),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(41),
-	.temp_fan_max = C_TO_K(72),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	/*
-	 * For board version < 2, the directly connected recovery
-	 * button is not available.
-	 */
-	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_startup(void)
-{
-	/*
-	 * Workaround to restore VBUS on PPC.
-	 * PP1 is sourced from PP5000_A, and when the CPU shuts down and
-	 * this rail drops, the PPC will internally turn off PP1_EN.
-	 * When the CPU starts again, and the rail is restored, the PPC
-	 * does not turn PP1_EN on again, causing VBUS to stay turned off.
-	 * The workaround is to check whether the PPC is sourcing VBUS, and
-	 * if so, make sure it is enabled.
-	 */
-	if (ppc_is_sourcing_vbus(0))
-		ppc_vbus_source_enable(0, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-/* Power Delivery and charging functions */
-static void board_tcpc_init(void)
-{
-	/*
-	 * Reset TCPC if we have had a system reset.
-	 * With EFSv2, it is possible to be in RW without
-	 * having reset the TCPC.
-	 */
-	if (system_get_reset_flags() & EC_RESET_FLAG_POWER_ON)
-		board_reset_pd_mcu();
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	/* Enable other overcurrent interrupts */
-	gpio_enable_interrupt(GPIO_HDMI_CONN0_OC_ODL);
-	gpio_enable_interrupt(GPIO_HDMI_CONN1_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
-	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
-	if (ec_config_get_usb4_present()) {
-		/*
-		 * By default configured as output low.
-		 */
-		gpio_set_flags(GPIO_USB_A4_OC_ODL,
-			       GPIO_INPUT | GPIO_INT_BOTH);
-		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
-	} else {
-		/* Ensure no interrupts from pin */
-		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
-	}
-
-}
-/* Make sure this is called after fw_config is initialised */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-void board_reset_pd_mcu(void)
-{
-	int level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags &
-		       TCPC_FLAGS_RESET_ACTIVE_HIGH);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, level);
-	msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
-	gpio_set_level(GPIO_USB_C0_TCPC_RST, !level);
-	if (BOARD_TCPC_C0_RESET_POST_DELAY)
-		msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
-}
-
-int board_set_active_charge_port(int port)
-{
-	CPRINTS("Requested charge port change to %d", port);
-
-	/*
-	 * The charge manager may ask us to switch to no charger if we're
-	 * running off USB-C only but upstream doesn't support PD. It requires
-	 * that we accept this switch otherwise it triggers an assert and EC
-	 * reset; it's not possible to boot the AP anyway, but we want to avoid
-	 * resetting the EC so we can continue to do the "low power" LED blink.
-	 */
-	if (port == CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	if (port < 0 || CHARGE_PORT_COUNT <= port)
-		return EC_ERROR_INVAL;
-
-	if (port == charge_manager_get_active_charge_port())
-		return EC_SUCCESS;
-
-	/* Don't charge from a source port */
-	if (board_vbus_source_enabled(port))
-		return EC_ERROR_INVAL;
-
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		int bj_active, bj_requested;
-
-		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
-			/* Change is only permitted while the system is off */
-			return EC_ERROR_INVAL;
-
-		/*
-		 * Current setting is no charge port but the AP is on, so the
-		 * charge manager is out of sync (probably because we're
-		 * reinitializing after sysjump). Reject requests that aren't
-		 * in sync with our outputs.
-		 */
-		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
-		bj_requested = port == CHARGE_PORT_BARRELJACK;
-		if (bj_active != bj_requested)
-			return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charger p%d", port);
-
-	switch (port) {
-	case CHARGE_PORT_TYPEC0:
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
-		break;
-	case CHARGE_PORT_BARRELJACK:
-		/* Make sure BJ adapter is sourcing power */
-		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_L))
-			return EC_ERROR_INVAL;
-		/* TODO(b/143975429) need to touch the PD controller? */
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-	usbc_overcurrent = is_overcurrented;
-	update_5v_usage();
-}
-
-int extpower_is_present(void)
-{
-	return adp_connected;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	/*
-	 * Puff proto drives EN_PP5000_HDMI from EN_S0_RAILS so we cannot gate
-	 * core rails while in S0 because HDMI should remain powered.
-	 * EN_PP5000_HDMI is a separate EC output on all other boards.
-	 */
-	return board_version != 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-	/* This output isn't connected on protos; safe to set anyway. */
-	gpio_set_level(GPIO_EN_PP5000_HDMI, enable);
-}
-
-unsigned int ec_config_get_bj_power(void)
-{
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
-	/* Out of range value defaults to 0 */
-	if (bj >= ARRAY_SIZE(bj_power))
-		bj = 0;
-	return bj;
-}
-
-int ec_config_get_usb4_present(void)
-{
-	return !(fw_config & EC_CFG_NO_USB4_MASK);
-}
-
-unsigned int ec_config_get_thermal_solution(void)
-{
-	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
-}
-
-static void setup_thermal(void)
-{
-	unsigned int table = ec_config_get_thermal_solution();
-	/* Configure Fan */
-	switch (table) {
-	/* Default and table0 use single fan */
-	case 0:
-	default:
-		thermal_params[TEMP_SENSOR_CORE] = thermal_a;
-		break;
-	/* Table1 is fanless */
-	case 1:
-		fan_set_count(0);
-		thermal_params[TEMP_SENSOR_CORE] = thermal_b;
-		break;
-	}
-}
-/* fan_set_count should be called before  HOOK_INIT/HOOK_PRIO_DEFAULT */
-DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	static uint32_t history[POWER_READINGS];
-	static uint8_t index;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-		/*
-		 * Clear the first entry of the power table so that
-		 * it is re-initilalised when the CPU starts.
-		 */
-		history[0] = 0;
-	} else {
-		int32_t charger_mw;
-
-		delay = POWER_DELAY_MS * MSEC;
-		/*
-		 * Get current charger limit (in mw).
-		 * If not configured yet, skip.
-		 */
-		charger_mw = charge_manager_get_power_limit_uw() / 1000;
-		if (charger_mw != 0) {
-			int32_t gap, total, max, power;
-			int i;
-
-			/*
-			 * Read power usage.
-			 */
-			power = (adc_read_channel(ADC_VBUS) *
-				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
-			/* Init power table */
-			if (history[0] == 0) {
-				for (i = 0; i < POWER_READINGS; i++)
-					history[i] = power;
-			}
-			/*
-			 * Update the power readings and
-			 * calculate the average and max.
-			 */
-			history[index] = power;
-			index = (index + 1) % POWER_READINGS;
-			total = 0;
-			max = history[0];
-			for (i = 0; i < POWER_READINGS; i++) {
-				total += history[i];
-				if (history[i] > max)
-					max = history[i];
-			}
-			/*
-			 * For Type-C power supplies, there is
-			 * less tolerance for exceeding the rating,
-			 * so use the max power that has been measured
-			 * over the measuring period.
-			 * For barrel-jack supplies, the rating can be
-			 * exceeded briefly, so use the average.
-			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
-				power = max;
-			else
-				power = total / POWER_READINGS;
-			/*
-			 * Calculate gap, and if negative, power
-			 * demand is exceeding configured power budget, so
-			 * throttling is required to reduce the demand.
-			 */
-			gap = charger_mw - power;
-			/*
-			 * Limiting type-A power.
-			 */
-			if (gap <= 0) {
-				new_state |= THROT_TYPE_A;
-				headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-				if (!(current_state & THROT_TYPE_A))
-					gap += POWER_GAIN_TYPE_A;
-			}
-			/*
-			 * If the type-C port is sourcing power,
-			 * check whether it should be throttled.
-			 */
-			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
-				new_state |= THROT_TYPE_C;
-				headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-				if (!(current_state & THROT_TYPE_C))
-					gap += POWER_GAIN_TYPE_C;
-			}
-			/*
-			 * As a last resort, turn on PROCHOT to
-			 * throttle the CPU.
-			 */
-			if (gap <= 0)
-				new_state |= THROT_PROCHOT;
-		}
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
-
-		ppc_set_vbus_source_current_limit(0, rp);
-		tcpm_select_rp_value(0, rp);
-		pd_update_contract(0);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
diff --git a/board/puff/board.h b/board/puff/board.h
deleted file mode 100644
index fedba00f7a..0000000000
--- a/board/puff/board.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-/* TODO: (b/143496253) re-enable CEC */
-/* #define CONFIG_CEC */
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-/* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define DEDICATED_CHARGE_PORT 1
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
-
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-/* Less than this much blocks AP power-on. */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 30000
-#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
-
-/* USB type C */
-#define CONFIG_USB_PD_TCPMV2 /* Use TCPMv2 */
-#define CONFIG_USB_PD_REV30 /* Enable PD 3.0 functionality */
-#define CONFIG_USB_PD_DECODE_SOP
-#undef CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-#define USB_PD_PORT_TCPC_0	0
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are five ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum charge_port {
-	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_BARRELJACK,
-};
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-unsigned int ec_config_get_bj_power(void);
-int ec_config_get_usb4_present(void);
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/puff/build.mk b/board/puff/build.mk
deleted file mode 100644
index e9968d5710..0000000000
--- a/board/puff/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-board-y+=led.o
diff --git a/board/puff/ec.tasklist b/board/puff/ec.tasklist
deleted file mode 100644
index ae10417dff..0000000000
--- a/board/puff/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
diff --git a/board/puff/gpio.inc b/board/puff/gpio.inc
deleted file mode 100644
index 7e62488cee..0000000000
--- a/board/puff/gpio.inc
+++ /dev/null
@@ -1,169 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Other interrupts */
-GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-/*
- * Directly connected recovery button (not available on some boards).
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
-
-/* Port power control interrupts */
-GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A0_OC_ODL,        PIN(E, 4), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-/* May be reconfigured as input */
-GPIO_INT(USB_A4_OC_ODL,        PIN(B, 0), GPIO_OUT_LOW | GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A2_STATUS_L,          PIN(6, 1), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,          PIN(C, 7), GPIO_INPUT)
-
-/* USB type C */
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(EN_PP_MST_OD,             PIN(9, 6), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-
-/* HDMI/CEC */
-GPIO(EN_PP5000_HDMI,           PIN(5, 0), GPIO_OUT_LOW)
-GPIO(HDMI_CONN0_CEC_OUT,       PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
-GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - Green Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x2A), 0, MODULE_ADC, 0)                  /* ADC0, ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* Unused pins */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(F, 2))						/* EC_I2C_RFU_SDA */
-UNUSED(PIN(F, 3))						/* EC_I2C_RFU_SCL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(8, 0))						/* LED_BLUE_L */
-UNUSED(PIN(4, 4))						/* ADC1/TEMP_SENSOR_2 */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(9, 2))						/* K8  NC */
-UNUSED(PIN(9, 1))						/* L8  NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(C, 6))						/* B11 NC */
-UNUSED(PIN(E, 2))						/* B8  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(0, 0))						/* D11 NC */
-UNUSED(PIN(3, 2))						/* E5  NC */
-UNUSED(PIN(D, 6))						/* F6  NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(D, 2))						/* C11 NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(9, 3))						/* M11 NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
diff --git a/board/puff/led.c b/board/puff/led.c
deleted file mode 100644
index ba87f05460..0000000000
--- a/board/puff/led.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int green = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_GREEN:
-		green = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		green = 1;
-		red = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (green)
-		pwm_set_duty(PWM_CH_LED_GREEN, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_GREEN, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec. */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task. */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_GREEN, 1);
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "green")) {
-		set_color(id, LED_GREEN, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/puff/usb_pd_policy.c b/board/puff/usb_pd_policy.c
deleted file mode 100644
index 9b0a372400..0000000000
--- a/board/puff/usb_pd_policy.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Puff boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000_A);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	/* Ignore non-PD ports (the barrel jack). */
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return 0;
-	return ppc_is_sourcing_vbus(port);
-}
diff --git a/board/puff/vif_override.xml b/board/puff/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/puff/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/quiche/board.c b/board/quiche/board.c
deleted file mode 100644
index e49b2e1b1a..0000000000
--- a/board/quiche/board.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Quiche board-specific configuration */
-
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/stm32gx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/ps8822.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "usb_descriptor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "usb_pd_dp_ufp.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define QUICHE_PD_DEBUG_LVL 1
-
-#ifdef SECTION_IS_RW
-#define CROS_EC_SECTION "RW"
-#else
-#define CROS_EC_SECTION "RO"
-#endif
-
-#ifdef SECTION_IS_RW
-static int pd_dual_role_init[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	PD_DRP_TOGGLE_ON,
-	PD_DRP_FORCE_SOURCE,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_HOST_USBC_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_HOST);
-		break;
-	case GPIO_USBC_DP_PPC_INT_ODL:
-		sn5s330_interrupt(USB_PD_PORT_DP);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal s)
-{
-	int port = -1;
-
-	switch (s) {
-	case GPIO_USBC_DP_MUX_ALERT_ODL:
-		port = USB_PD_PORT_DP;
-		break;
-	default:
-		return;
-	}
-	schedule_deferred_pd_interrupt(port);
-}
-
-void hpd_interrupt(enum gpio_signal signal)
-{
-	usb_pd_hpd_edge_event(signal);
-}
-
-static void board_uf_manage_vbus_interrupt(enum gpio_signal signal)
-{
-	baseboard_usb3_check_state();
-}
-
-static void board_pwr_btn_interrupt(enum gpio_signal signal)
-{
-	baseboard_power_button_evt(gpio_get_level(signal));
-}
-
-static void board_usbc_usb3_interrupt(enum gpio_signal signal)
-{
-	baseboard_usbc_usb3_irq();
-}
-#endif /* SECTION_IS_RW */
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/*
- * Table GPIO signals control both power rails and reset lines to various chips
- * on the board. The order the signals are changed and the delay between GPIO
- * signals is driven by USB/MST hub power sequencing requirements.
- */
-const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
-};
-const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
-
-/*
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Quiche"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-#ifndef SECTION_IS_RW
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-	},
-};
-#endif
-
-#ifdef SECTION_IS_RW
-/*
- * PS8802 set mux board tuning.
- * Adds in board specific gain and DP lane count configuration
- */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		rv = ps8822_set_dp_rx_eq(me, PS8822_DPEQ_LEVEL_UP_20DB);
-
-	return rv;
-}
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &stm32gx_tcpm_drv,
-	},
-	[USB_PD_PORT_DP] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_I2C1,
-			.addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
-	},
-	[USB_PD_PORT_DP] = {
-		.usb_port = USB_PD_PORT_DP,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8751_I2C_ADDR2_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_DP] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR2_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct hpd_to_pd_config_t hpd_config = {
-	.port = USB_PD_PORT_HOST,
-	.signal = GPIO_DDI_MST_IN_HPD,
-};
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_SYSTEM, "Resetting TCPCs...");
-	cflush();
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 0);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-	gpio_set_level(GPIO_USBC_DP_PD_RST_L, 1);
-	gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_enable_usbc_interrupts(void)
-{
-	/* Enable C0 PPC interrupt */
-	gpio_enable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Enable C1 PPC interrupt */
-	gpio_enable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
-	/* Enable C0 HPD interrupt */
-	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Enable C1 TCPC interrupt */
-	gpio_enable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-}
-
-void board_disable_usbc_interrupts(void)
-{
-	/* Disable C0 PPC interrupt */
-	gpio_disable_interrupt(GPIO_HOST_USBC_PPC_INT_ODL);
-	/* Disable C1 PPC interrupt */
-	gpio_disable_interrupt(GPIO_USBC_DP_PPC_INT_ODL);
-	/* Disable C0 HPD interrupt */
-	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
-	/* Disable C1 TCPC interrupt */
-	gpio_disable_interrupt(GPIO_USBC_DP_MUX_ALERT_ODL);
-	/* Disable VBUS control interrupt for C2 */
-	gpio_disable_interrupt(GPIO_USBC_UF_MUX_VBUS_EN);
-}
-
-void board_tcpc_init(void)
-{
-	board_reset_pd_mcu();
-
-	/* Enable board usbc interrupts */
-	board_enable_usbc_interrupts();
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
-
-enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
-{
-	return pd_dual_role_init[port];
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	/*
-	 * CONFIG_USB_PD_PORT_MAX_COUNT must be defined to account for C0, C1,
-	 * and C2, but TCPMv2 only knows about C0 and C1, as C2 is a type-c only
-	 * port that is managed directly by the PS8803 TCPC.
-	 */
-	return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USB_PD_PORT_HOST)
-		return gpio_get_level(GPIO_HOST_USBC_PPC_INT_ODL) == 0;
-	else if (port == USB_PD_PORT_DP)
-		return gpio_get_level(GPIO_USBC_DP_PPC_INT_ODL) == 0;
-
-	return 0;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USBC_DP_MUX_ALERT_ODL) &&
-	    gpio_get_level(GPIO_USBC_DP_PD_RST_L))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-static void board_usb_pd_dp_ocp_reset(void)
-{
-	gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, 1);
-}
-DECLARE_DEFERRED(board_usb_pd_dp_ocp_reset);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	if (port == USB_PD_PORT_DP) {
-		gpio_set_level(GPIO_USBC_ALTMODE_OCP_NOTIFY, !is_overcurrented);
-		hook_call_deferred(&board_usb_pd_dp_ocp_reset_data,
-				   USB_HUB_OCP_RESET_MSEC);
-	}
-}
-
-int dock_get_mf_preference(void)
-{
-	int rv;
-	uint32_t fw_config;
-	int mf = MF_OFF;
-
-	/*
-	 * MF (multi function) preferece is indicated by bit 0 of the fw_config
-	 * data field. If this data field does not exist, then default to 4 lane
-	 * mode.
-	 */
-	rv = cbi_get_fw_config(&fw_config);
-	if (!rv)
-		mf = CBI_FW_MF_PREFERENCE(fw_config);
-
-	return mf;
-}
-
-#endif /* SECTION_IS_RW */
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_debug_gpio_1_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_1, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_1_pulse);
-
-static void board_debug_gpio_2_pulse(void)
-{
-	gpio_set_level(GPIO_TRIGGER_2, 0);
-}
-DECLARE_DEFERRED(board_debug_gpio_2_pulse);
-
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
-{
-	switch (trigger) {
-	case TRIGGER_1:
-		gpio_set_level(GPIO_TRIGGER_1, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_1_pulse_data,
-					   pulse_usec);
-		break;
-	case TRIGGER_2:
-		gpio_set_level(GPIO_TRIGGER_2, level);
-		if (pulse_usec)
-			hook_call_deferred(&board_debug_gpio_2_pulse_data,
-					   pulse_usec);
-		break;
-	default:
-		CPRINTS("bad debug gpio selection");
-		break;
-	}
-}
-
-static int command_dplane(int argc, char **argv)
-{
-	char *e;
-	int lane;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	lane = strtoi(argv[1], &e, 10);
-
-	if ((lane != 2) && (lane != 4))
-		return EC_ERROR_PARAM1;
-
-	/* put MST into reset */
-	gpio_set_level(GPIO_MST_RST_L, 0);
-	msleep(1);
-	/* Set lane control to requested level */
-	gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
-	msleep(1);
-	/* Take MST out of reset */
-	gpio_set_level(GPIO_MST_RST_L, 1);
-
-	ccprintf("MST lane set:  %s, lane_ctrl = %d\n",
-		 lane == 2 ? "2 lane" : "4 lane",
-		 gpio_get_level(GPIO_MST_HUB_LANE_SWITCH));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
diff --git a/board/quiche/board.h b/board/quiche/board.h
deleted file mode 100644
index 98feab31f6..0000000000
--- a/board/quiche/board.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Quiche board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-/*
- * For MP release, CONFIG_SYSTEM_UNLOCKED must be undefined, and
- * CONFIG_FLASH_PSTATE_LOCKED must be defined in order to enable write protect
- * using option bytes WRP registers.
- */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-#undef CONFIG_FLASH_PSTATE_LOCKED
-
-
-/* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP     1
-#define USB_PD_PORT_USB3   2
-
-/*
- * The host (C0) and display (C1) usbc ports are usb-pd capable. There is
- * also a type-c only port (C2). C2 must be accounted for in PORT_MAX_COUNT so
- * the PPC config table is correctly sized and the PPC driver can be used to
- * control VBUS on/off.
- */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#define CONFIG_USB_MUX_PS8822
-
-#define CONFIG_USB_PID 0x5048
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-
-/* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
-
-/* Required symbolic I2C port names */
-#define I2C_PORT_MP4245 I2C_PORT_I2C3
-#define I2C_PORT_EEPROM I2C_PORT_I2C3
-#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
-
-/* Include math_util for bitmask_uint64 used in pd_timers */
-#define CONFIG_MATH_UTIL
-
-#ifndef __ASSEMBLER__
-
-#include "registers.h"
-
-#define GPIO_DP_HPD GPIO_DDI_MST_IN_HPD
-#define GPIO_USBC_UF_ATTACHED_SRC GPIO_USBC_UF_MUX_VBUS_EN
-#define GPIO_BPWR_DET GPIO_TP73
-#define GPIO_USB_HUB_OCP_NOTIFY GPIO_USBC_DATA_OCP_NOTIFY
-#define GPIO_UFP_PLUG_DET GPIO_MST_UFP_PLUG_DET
-#define GPIO_PWR_BUTTON_RED GPIO_EC_STATUS_LED1
-#define GPIO_PWR_BUTTON_GREEN GPIO_EC_STATUS_LED2
-
-#define BUTTON_PRESSED_LEVEL 1
-#define BUTTON_RELEASED_LEVEL 0
-
-#define GPIO_TRIGGER_1 GPIO_EC_STATUS_LED1
-#define GPIO_TRIGGER_2 GPIO_EC_STATUS_LED2
-
-enum  debug_gpio {
-	TRIGGER_1 = 0,
-	TRIGGER_2,
-};
-
-/*
- * Function used to control GPIO signals as a timing marker. This is intended to
- * be used for development/debugging purposes.
- *
- * @param trigger GPIO debug signal selection
- * @param level desired level of the debug gpio signal
- * @param pulse_usec pulse width if non-zero
- */
-void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec);
-
-/*
- * Function called in power on case to enable usbc related interrupts
- */
-void board_enable_usbc_interrupts(void);
-
-/*
- * Function called in power off case to disable usbc related interrupts
- */
-void board_disable_usbc_interrupts(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/quiche/build.mk b/board/quiche/build.mk
deleted file mode 100644
index 1a8ec0d625..0000000000
--- a/board/quiche/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32g4
-CHIP_VARIANT:=stm32g473xc
-BASEBOARD:=honeybuns
-
-board-y=board.o
diff --git a/board/quiche/dev_key.pem b/board/quiche/dev_key.pem
deleted file mode 100644
index 4897ceb44e..0000000000
--- a/board/quiche/dev_key.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEAyiT9PsD2wW3mhfuxMtihnLDKC+PY9l6j+j405G5Wd3BBtLLl
-2uEoSD8cFQfnVTeFH7wggVf+SMAP3Y2aTnXIfdTX3N0skAdq/kYNUlQAK0xsa3Z7
-bRZ8puvzu+XNqsSS/tvsdYbNE5WC5sXtt7Wkm3mKn7PAti7oQrKbW1beFD0FgdAq
-JoweIdpkuOwDYtFBcF92LWWGziDcEXlc2v5Xj3qvixMLnhy+Ny1Byr2ApVaYZ56H
-JfjHKxbirNj4IrgmhdzfBIKxDf4mGibG0K1aC1io+SixtRV1cS6JRB0D+GS4QIcq
-y9bCMkBeVQLHhSo1UYZqbB7Qef0blQ2sxsXklo8Q5EIQOd6yiXiTelApOWDn3zTi
-uTkUo+99SPDLw/S3sR3uESxt+OYO2Yt6BWe2JSYBhHWB0Xc0PGItq7DUpm2cEWke
-vS91I/lBfqhOxQOvnEx5NM97/RBQMa3jJ5Jv/72X5oU6OcGmaliBJy3Tv0CSiI06
-qgRgWxMym/XA0ui/AgEDAoIBgQCGw1N/K08rnpmup8t3OxZoddwH7TtO6cKm1CNC
-9Dmk9YEjIe6R63AwKhK4r++OJQNqfWsA5VQwgAqTs7w0ToWpOI/ok3MKr5yphAjh
-jVVyMvLyTvzzZFMZ8qJ9Q95x2GH/PUhOWd4NDldEg/PPzm28+7G/zSskH0WBzGeS
-Oeli01kBNXFvCBQWkZh7SAJB4NZK6k7I7lnewJK2UOiR/uUKUcpct10UEyl6Hivc
-flXDjxBFFFoZUITHZJcd5frB0Bh+EiqJ3CnkSIjD4sTnZs/TP8CKhmYriabfBHdH
-j6ffcr5y8VhqDJK/ISSmWQO1c/rSziJLhx/ZrWvWp1FAbRg+kdh+RmV8hYIdEOq8
-PYOiERihd+eHVhtzsc74+cRGxPbaFJ2rpuJt+xk1Zp7IfGyyPWDmvXFKZgX+vo2s
-vJL6q9pPR57uUHL0xsxDrMH3HFxkl1ta5PsiBGXs+zG0EUzNKGtoRTCi176xUWyo
-NG+eWiL9ddeZVBzWeKfJGfwQ53sCgcEA+JE2E5kjvVCasSqERfDfIkSeOKoqWdZ2
-sAvTHibq6+vMBkRubNA0glHcUrMEBblDg3ds2z1A9YvwjwEUq9UFpVH3qfX9vaTX
-lLYFRZjcA3PkCJvFAt5eIlVXp+vgaEo6OcodLjDiqkYKzbMC13k5uM1wsEEwo2vI
-38vhHQlH1PHVTd8pt2Y7mOpDgxOOJLrvwuew7Lj9QSBRZ0EJxqv+1QA4EQ1cPr1H
-hGqggtL0ChLRV7KBHiLz9ggS5vHTEkFNAoHBANAwaSIfTnpAvkMoGy+iQyw0afC0
-7hnwhHKcAzqenT1Mzo3Yt7/zsZE8ywjKPe9C+ZHZyh+W373tCUQRnjpNOpNiVHzi
-ekFxl8kpLhpbB8LTXuRlQmtZjVQPbyuORPGDCzA05GGBN6mnXju+iQEz2WD8f3oY
-Jz5yYl54eAuMsFl5/0yehqBQjRvky5YRna2eNUKBvz+/BgjpZeb0DtLMffcAvrkQ
-FQbAwNvzvagMOEemjLSp9iXjQSNWJAdc86dMOwKBwQCltiQNEMJ+Nbx2HFguoJTB
-gxQlxsbmjvnKsoy+xJydR91ZgvRIis2sNpLhzK1ZJi0CT53nfitOXUsKALhyjgPD
-i/pxTqkpGI+4eVjZEJKs9+1bEoNXPulsOOUanUBFhtF73BN0IJccLrHed1c6UNEl
-3ksgK3XCR9s/3UC+Bi/jS+OJP3Ek7tJl8YJXYl7DJ0qB78tIe1OAwDZE1gaEcqnj
-VXq2COgp04UC8cBXN01cDIuPzFYUF01OsAyZ9oy21jMCgcEAisrwwWo0UYB+13AS
-H8GCHXhGoHieu/Wtob1XfGm+KN3fCTslKqJ2YNMyBdwpSiymYTvcFQ8/0/NbgrZp
-fDN8YkGNqJb8K6EP23DJZudageI/Qu4sR5EI4rT0x7Qt9ldcys3tllYlG8TpfSmw
-q3fmQKhU/BAaKaGW6aWlXQh1kPv/iGmvFYsIvUMyZAu+c77OLFZ/f9SusJuZRKK0
-jIhT+gB/Jgq4rysrPU0pGrLQL8RdzcakGUIrbOQYBOiib4gnAoHAVrvbmZGxyeeA
-oDE2QlXXmd1higPaQe3u+7vmh6itVpJ71n9wmu9xei7IiTOtGDYjHLXa8Qg0y37/
-FVCUiFxhOz05hpnB1ts70tuIWUJbWttMnhZPTpKa1dzZFB6qrlk2o/ONaSfNzpOZ
-FgKxBURFVzNMTlIh7QOZGoOeRg5BkFG5z21g8egYQ/1cY61BhaxJTz93HGKb0jYn
-QnC0WfVF9amWNGwocKATkwjoSVC7rQRsB2FMbY/WCqgE92lXsU9W
------END RSA PRIVATE KEY-----
diff --git a/board/quiche/ec.tasklist b/board/quiche/ec.tasklist
deleted file mode 100644
index cc36bf5a74..0000000000
--- a/board/quiche/ec.tasklist
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS_RO(RWSIG,    rwsig_task,   NULL, 1280) \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(POWER_BUTTON, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(UCPD, ucpd_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc
deleted file mode 100644
index 9514858ca7..0000000000
--- a/board/quiche/gpio.inc
+++ /dev/null
@@ -1,100 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-#ifdef SECTION_IS_RW
-GPIO_INT(HOST_USBC_PPC_INT_ODL,  PIN(D,  9),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
-GPIO_INT(USBC_DP_MUX_ALERT_ODL,  PIN(B,  1),      GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
-GPIO_INT(USBC_DP_PPC_INT_ODL,    PIN(E,  7),      GPIO_INT_FALLING | GPIO_PULL_UP, ppc_interrupt)
-GPIO_INT(DDI_MST_IN_HPD,         PIN(C,  14),     GPIO_INT_BOTH, hpd_interrupt)
-GPIO_INT(USBC_UF_MUX_VBUS_EN,    PIN(C,  12),     GPIO_INT_BOTH, board_uf_manage_vbus_interrupt)
-GPIO_INT(PWR_BTN,                PIN(A,  0),      GPIO_INT_BOTH, board_pwr_btn_interrupt)
-GPIO_INT(USBC_UF_PPC_INT_ODL,    PIN(B,  5),      GPIO_INT_FALLING | GPIO_PULL_UP, board_usbc_usb3_interrupt)
-#endif
-
-/* Power sequencing signals */
-GPIO(EN_AC_JACK,                    PIN(A,  1), GPIO_OUT_LOW)
-GPIO(EN_BB,                         PIN(A,  8), GPIO_OUT_LOW)
-GPIO(EN_PP3300_B,                   PIN(B,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,                   PIN(C,  6), GPIO_OUT_LOW)
-GPIO(EN_PP1200_A,                   PIN(E,  8), GPIO_OUT_LOW)
-GPIO(EN_PP1100_A,                   PIN(C,  7), GPIO_OUT_LOW)
-GPIO(EN_PP1050_A,                   PIN(A,  2), GPIO_OUT_LOW)
-GPIO(EN_PP5000_C,                   PIN(D,  1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_HSPORT,              PIN(D,  0), GPIO_OUT_LOW)
-
-/* MST Hub signals */
-GPIO(MST_LP_CTL_L,                  PIN(D, 10), GPIO_ODR_LOW)
-GPIO(MST_RST_L,                     PIN(E, 14), GPIO_ODR_LOW)
-GPIO(MST_HUB_LANE_SWITCH,           PIN(C, 15), GPIO_OUT_HIGH)
-GPIO(MST_UFP_PLUG_DET,              PIN(B, 12), GPIO_OUT_HIGH)
-
-/* Display Demux signals */
-GPIO(DEMUX_DUAL_DP_MODE,            PIN(B,  0), GPIO_OUT_LOW)
-GPIO(DEMUX_DP_HDMI_MODE,            PIN(E, 15), GPIO_OUT_LOW)
-GPIO(DEMUX_DUAL_DP_RESET_N,         PIN(E, 13), GPIO_ODR_LOW)
-GPIO(DEMUX_DUAL_DP_PD_N,            PIN(E, 12), GPIO_ODR_LOW)
-GPIO(DEMUX_DP_HDMI_PD_N,            PIN(B, 13), GPIO_ODR_LOW)
-
-/* USBC Mux and Demux Signals */
-GPIO(EN_DP_SINK,                    PIN(B, 14), GPIO_OUT_LOW)
-GPIO(DP_SINK_RESET,                 PIN(B, 15), GPIO_OUT_LOW)
-GPIO(USBC_DP_PD_RST_L,              PIN(E,  9), GPIO_ODR_LOW)
-GPIO(USBC_UF_RESET_L,               PIN(D,  2), GPIO_ODR_LOW)
-
-/* USB Hubs signals */
-GPIO(EC_HUB2_RESET_L,               PIN(C,  5), GPIO_ODR_LOW)
-GPIO(EC_HUB3_RESET_L,               PIN(B, 10), GPIO_ODR_LOW)
-GPIO(USBC_ALTMODE_OCP_NOTIFY,       PIN(F,  0), GPIO_OUT_HIGH)
-GPIO(USBC_DATA_OCP_NOTIFY,          PIN(F,  1), GPIO_OUT_HIGH)
-
-/* USB-A Current limit switches, set default to 1.5A */
-GPIO(TP73,                          PIN(C,  0), GPIO_OUT_LOW)
-GPIO(EC_DFU_MUX_CTRL,               PIN(C,  3), GPIO_OUT_HIGH)
-GPIO(EC_STATUS_LED1,                PIN(C,  1), GPIO_OUT_HIGH)
-GPIO(EC_STATUS_LED2,                PIN(C,  2), GPIO_OUT_HIGH)
-GPIO(USB3_A5_CDP_EN,                PIN(B,  9), GPIO_OUT_LOW)
-GPIO(USB3_A6_CDP_EN,                PIN(C, 13), GPIO_OUT_LOW)
-
-/* Write protect */
-GPIO(EC_FLASH_WP_ODL,               PIN(A,  3), GPIO_ODR_HIGH)
-GPIO(EC_WP_L,                       PIN(E, 11), GPIO_INT_BOTH)
-
-/* UART Bus */
-GPIO(EC_UART_TX,                    PIN(C, 10), GPIO_INT_BOTH)
-GPIO(EC_UART_RX,                    PIN(C, 11), GPIO_INT_BOTH)
-
-/*
- * I2C SCL/SDA pins. These will normally be under control of the peripheral from
- * alt fucntion setting below. But if a port gets wedged, the unwedge code uses
- * these signals as regular GPIOs.
- */
-GPIO(EC_I2C1_SCL,                   PIN(A, 15),  GPIO_ODR_HIGH)
-GPIO(EC_I2C1_SDA,                   PIN(B,  7),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SCL,                   PIN(C,  8),  GPIO_ODR_HIGH)
-GPIO(EC_I2C3_SDA,                   PIN(C,  9),  GPIO_ODR_HIGH)
-
-/* misc signals */
-GPIO(BOOT0,                         PIN(B,  8),  GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-
-/* USART3_TX/RX GPIOC 10-11*/
-ALTERNATE(PIN_MASK(C, 0x0C00),  7, MODULE_UART,  GPIO_PULL_UP)
-/* I2C Ports
- *   I2C1: SDA/SCL -> PB7/PA15
- *   I2C2: SDA/SCL -> PA8/PA9
- *   I2C3: SDA/SCL -> PC8/PC9
- */
-ALTERNATE(PIN_MASK(B, 0x0080),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(A, 0X8000),  4, MODULE_I2C,   GPIO_OPEN_DRAIN)
-ALTERNATE(PIN_MASK(C, 0x0300),  8, MODULE_I2C,   GPIO_OPEN_DRAIN)
-/* GPIOA4-7: SPI Signals */
-ALTERNATE(PIN_MASK(A, 0x00F0),  5, MODULE_SPI,   0)
diff --git a/board/rainier/board.c b/board/rainier/board.c
deleted file mode 100644
index 0f9c388399..0000000000
--- a/board/rainier/board.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "chipset.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/baro_bmp280.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void overtemp_interrupt(enum gpio_signal signal)
-{
-	CPRINTS("AP wants shutdown");
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
-}
-
-static void warm_reset_request_interrupt(enum gpio_signal signal)
-{
-	CPRINTS("AP wants warm reset");
-	chipset_reset(CHIPSET_RESET_AP_REQ);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 16, 4096, 0, STM32_AIN(10)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"tcpc0",   I2C_PORT_TCPC0,     1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor. All temps are in degrees K. Must be in
- * same order as enum temp_sensor_id. To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-#endif
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI_ACCEL_CS_L },
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI_BARO_CS_L },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_CHARGER_INT_L
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_L))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	/*
-	 * NOP because there is no internal power therefore no charging.
-	 * Placeholder so common/charge_manager.c is built.
-	 */
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			     int max_ma, int charge_mv)
-{
-	/*
-	 * NOP because there is no internal power therefore no charging.
-	 * Placeholder so common/charge_manager.c is built.
-	 */
-}
-
-int extpower_is_present(void)
-{
-	/* There is no internal power on this board. */
-	return 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-  /* Must be, if we're at a stage where this function is called. */
-	return 1;
-}
-
-static void board_spi_enable(void)
-{
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		 board_spi_disable,
-		 MOTION_SENSE_HOOK_PRIO + 1);
-
-static void board_init(void)
-{
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_L);
-
-	/* Enable reboot / shutdown control inputs from AP */
-	gpio_enable_interrupt(GPIO_WARM_RESET_REQ);
-	gpio_enable_interrupt(GPIO_AP_OVERTEMP);
-
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_L);
-
-	/* Set SPI2 pins to high speed */
-	/* pins D0/D1/D3/D4 */
-	STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf;
-
-	/* Sensor Init */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		board_spi_enable();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_config_pre_init(void)
-{
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-	/*
-	 * Remap USART1 and SPI2 DMA:
-	 *
-	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
-	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
-	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
-}
-
-void board_hibernate(void)
-{
-	int rv;
-
-	/*
-	 * Disable the power enables for the TCPCs since we're going into
-	 * hibernate.  The charger VBUS interrupt will wake us up and reset the
-	 * EC.  Upon init, we'll reinitialize the TCPCs to be at full power.
-	 */
-	CPRINTS("Set TCPCs to low power");
-	rv = tcpc_write(0, TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW);
-	if (rv)
-		CPRINTS("Error setting TCPC %d", 0);
-
-	cflush();
-}
-
-enum rainier_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_REV0 = 0,
-	BOARD_VERSION_REV1 = 1,
-	BOARD_VERSION_REV2 = 2,
-	BOARD_VERSION_REV3 = 3,
-	BOARD_VERSION_REV4 = 4,
-	BOARD_VERSION_REV5 = 5,
-	BOARD_VERSION_REV6 = 6,
-	BOARD_VERSION_REV7 = 7,
-	BOARD_VERSION_REV8 = 8,
-	BOARD_VERSION_REV9 = 9,
-	BOARD_VERSION_REV10 = 10,
-	BOARD_VERSION_REV11 = 11,
-	BOARD_VERSION_REV12 = 12,
-	BOARD_VERSION_REV13 = 13,
-	BOARD_VERSION_REV14 = 14,
-	BOARD_VERSION_REV15 = 15,
-	BOARD_VERSION_COUNT,
-};
-
-struct {
-	enum rainier_board_version version;
-	int expect_mv;
-} const rainier_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
-	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
-	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
-	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
-	{ BOARD_VERSION_REV13, 1576 }, /* 47K   , 330K ohm */
-	{ BOARD_VERSION_REV14, 1684 }, /* 47K   , 680K ohm */
-	{ BOARD_VERSION_REV15, 1800 }, /* 56K   , NC */
-};
-BUILD_ASSERT(ARRAY_SIZE(rainier_boards) == BOARD_VERSION_COUNT);
-
-#define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv;
-	int i;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
-	/* Wait to allow cap charge */
-	msleep(10);
-	mv = adc_read_channel(ADC_BOARD_ID);
-
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ADC_BOARD_ID);
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 1);
-
-	for (i = 0; i < BOARD_VERSION_COUNT; ++i) {
-		if (mv < rainier_boards[i].expect_mv + THRESHOLD_MV) {
-			version = rainier_boards[i].version;
-			break;
-		}
-	}
-
-	return version;
-}
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_base_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-static struct bmp280_drv_data_t bmp280_drv_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[LID_BARO] = {
-	 .name = "Baro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMP280,
-	 .type = MOTIONSENSE_TYPE_BARO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmp280_drv,
-	 .drv_data = &bmp280_drv_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
-	 .min_frequency = BMP280_BARO_MIN_FREQ,
-	 .max_frequency = BMP280_BARO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-int board_allow_i2c_passthru(int port)
-{
-	/*
-	 * Battery port is the only port passthru is allowed on and this board
-	 * does not have a battery, therefore always return false.
-	 */
-	return 0;
-}
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	/* Assume there is always sufficient power from charger to power on. */
-	return 0;
-}
diff --git a/board/rainier/board.h b/board/rainier/board.h
deleted file mode 100644
index a323a90889..0000000000
--- a/board/rainier/board.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Rainier */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Optional modules */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_CHIPSET_RK3399
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_RTC
-#define CONFIG_HOSTCMD_RTC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-/* Source RTCCLK from external 32.768kHz source on PC15/OSC32_IN. */
-#define CONFIG_STM32_CLOCK_LSE
-#define CONFIG_SWITCH
-#define CONFIG_WATCHDOG_HELP
-
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-
-/* Region sizes are no longer a power of 2 so we can't enable MPU */
-#undef  CONFIG_MPU
-
-/* Enable a different power-on sequence than the one on gru */
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-/* Optional features */
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HOST_COMMAND_STATUS
-
-/* By default, set hcdebug to off */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_LTO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_USB_MUX_VIRTUAL
-
-/* Increase tx buffer size, as we'd like to stream EC log to AP. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Motion Sensors */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_BARO_BMP280
-
-/* To be able to indicate the device is in tablet mode. */
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode. */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_BARO)
-
-/* USB PD config */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
-
-/* Timer selection */
-#define TIM_CLOCK32  2
-#define TIM_WATCHDOG 7
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
-
-#define CONFIG_TASK_PROFILING
-
-#define I2C_PORT_TCPC0 1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	PP1250_S3_PWR_GOOD = 0,
-	PP900_S0_PWR_GOOD,
-	AP_PWR_GOOD,
-	SUSPEND_DEASSERTED,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	LID_BARO,
-	SENSOR_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/rainier/build.mk b/board/rainier/build.mk
deleted file mode 100644
index b77a900d56..0000000000
--- a/board/rainier/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-
-board-y=board.o usb_pd_policy.o
diff --git a/board/rainier/ec.tasklist b/board/rainier/ec.tasklist
deleted file mode 100644
index ed574a1d6a..0000000000
--- a/board/rainier/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
-
diff --git a/board/rainier/gpio.inc b/board/rainier/gpio.inc
deleted file mode 100644
index f5a4f360b3..0000000000
--- a/board/rainier/gpio.inc
+++ /dev/null
@@ -1,93 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-GPIO_INT(SPI1_NSS,         PIN(A, 15), GPIO_INT_BOTH,
-         spi_event)
-GPIO_INT(USB_C0_PD_INT_L,  PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,      PIN(D, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,    PIN(E, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt)
-GPIO_INT(POWER_BUTTON_L,   PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt)
-GPIO_INT(PP1250_S3_PG,     PIN(D, 8),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_signal_interrupt)
-GPIO_INT(PP900_S0_PG,      PIN(D, 9),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_signal_interrupt)
-GPIO_INT(AP_EC_S3_S0_L,    PIN(C, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,   PIN(E, 1),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         warm_reset_request_interrupt)
-GPIO_INT(AP_OVERTEMP,      PIN(E, 4),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         overtemp_interrupt)
-GPIO_INT(ACCEL_INT_L,      PIN(D, 14), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         bmi160_interrupt)
-
-/* Voltage rails control pins */
-GPIO(PP1800_S0_EN,         PIN(D, 11), GPIO_OUT_LOW)
-GPIO(AP_CORE_EN,           PIN(C, 1),  GPIO_OUT_LOW)
-GPIO(PP3300_S0_EN,         PIN(E, 12), GPIO_OUT_LOW)
-GPIO(PP1800_USB_EN,        PIN(C, 4),  GPIO_OUT_LOW)
-GPIO(PP900_S0_EN,          PIN(E, 8),  GPIO_OUT_LOW)
-GPIO(PP1250_S3_EN,         PIN(D, 13), GPIO_OUT_LOW)
-GPIO(PP1800_S3_EN,         PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PP3300_S3_EN,         PIN(E, 2),  GPIO_OUT_LOW)
-GPIO(PP900_S3_EN,          PIN(E, 10), GPIO_OUT_LOW)
-
-GPIO(PP3300_REDUCE_EFF_L,  PIN(D, 12), GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C0_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C1_SCL,             PIN(B, 10), GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 11), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-
-/* SPI sensors */
-GPIO(SPI_BARO_CS_L,        PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(SPI_ACCEL_CS_L,       PIN(D, 0),  GPIO_OUT_HIGH)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(E, 5),  GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(C, 5),  GPIO_INPUT | GPIO_PULL_UP)
-GPIO(CHARGER_INT_L,        PIN(E, 6),  GPIO_INPUT | GPIO_PULL_UP)
-/* Non-INT power signal pin */
-GPIO(AP_CORE_PG,           PIN(D, 7),  GPIO_INPUT | GPIO_PULL_UP)
-
-
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH)
-GPIO(SYS_RST_L,            PIN(C, 8),  GPIO_ODR_HIGH)
-GPIO(EC_INT_L,             PIN(E, 3),  GPIO_ODR_HIGH)
-GPIO(EC_BOARD_ID_EN_L,     PIN(F, 1),  GPIO_ODR_HIGH)
-GPIO(USB_C0_DISCHARGE,     PIN(A, 11), GPIO_OUT_LOW)
-GPIO(PCA9468_EN,           PIN(E, 15), GPIO_OUT_LOW)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        0)
-/* I2C MASTER: PB10/11 */
-ALTERNATE(PIN_MASK(B, 0x0c00), 1, MODULE_I2C,        0)
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-/* SPI MASTER: PD1/3/4 */
-ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/rainier/usb_pd_policy.c b/board/rainier/usb_pd_policy.c
deleted file mode 100644
index 6de1dc9271..0000000000
--- a/board/rainier/usb_pd_policy.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en;
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en = 1;
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en;
-	/* Disable VBUS */
-	vbus_en = 0;
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * VCONN is provided directly by the battery (PPVAR_SYS)
-	 * but use the same rules as power swap.
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
diff --git a/board/rainier/vif_override.xml b/board/rainier/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/rainier/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/rammus/battery.c b/board/rammus/battery.c
deleted file mode 100644
index 916aac5fd3..0000000000
--- a/board/rammus/battery.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Placeholder values for temporary battery pack.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "util.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-/* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-
-static const struct battery_info info = {
-	.voltage_max = 13200,
-	.voltage_normal = 11550,
-	.voltage_min = 9000,
-	/* Pre-charge values. */
-	.precharge_current = 256, /* mA */
-
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	return &info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_BATT_PRES_L) ? BP_NO : BP_YES;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Check for case where both XCHG and XDSG bits are set indicating that even
- * though the FG can be read from the battery, the battery is not able to be
- * charged or discharged. This situation will happen if a battery disconnect was
- * intiaited via H1 setting the DISCONN signal to the battery. This will put the
- * battery pack into a sleep state and when power is reconnected, the FG can be
- * read, but the battery is still not able to provide power to the system. The
- * calling function returns batt_pres = BP_NO, which instructs the charging
- * state machine to prevent powering up the AP on battery alone which could lead
- * to a brownout event when the battery isn't able yet to provide power to the
- * system. .
- */
-static int battery_check_disconnect(void)
-{
-	int rv;
-	uint8_t data[6];
-
-	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
-	if (rv)
-		return BATTERY_DISCONNECT_ERROR;
-
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
-	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
-		return BATTERY_DISCONNECTED;
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * successful & the battery status is initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-	    (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	     battery_check_disconnect() != BATTERY_NOT_DISCONNECTED ||
-	     battery_init() == 0)) {
-		batt_pres = BP_NO;
-	}
-
-	batt_pres_prev = batt_pres;
-	return batt_pres;
-}
-
diff --git a/board/rammus/board.c b/board/rammus/board.c
deleted file mode 100644
index c4e32a9791..0000000000
--- a/board/rammus/board.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Rammus board-specific configuration */
-
-#include "adc.h"
-#include "anx7447.h"
-#include "bd99992gw.h"
-#include "board_config.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/temp_sensor/bd99992gw.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "pi3usb9281.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-#include "espi.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define USB_PD_PORT_PS8751	1
-#define USB_PD_PORT_ANX7447	0
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-/* Set PD discharge whenever VBUS detection is high (i.e. below threshold). */
-static void vbus_discharge_handler(void)
-{
-	pd_set_vbus_discharge(0, gpio_get_level(GPIO_USB_C0_VBUS_DET_L));
-	pd_set_vbus_discharge(1, gpio_get_level(GPIO_USB_C1_VBUS_DET_L));
-}
-DECLARE_DEFERRED(vbus_discharge_handler);
-
-void vbus0_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(0, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C0);
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void vbus1_evt(enum gpio_signal signal)
-{
-	/* VBUS present GPIO is inverted */
-	usb_charger_vbus_change(1, !gpio_get_level(signal));
-	task_wake(TASK_ID_PD_C1);
-	hook_call_deferred(&vbus_discharge_handler_data, 0);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-#include "gpio_list.h"
-
-/* Hibernate wake configuration */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{"i2c_0_0", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
-	{"i2c_0_1", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
-	{"i2c_1",   NPCX_I2C_PORT1,   100, GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
-	{"i2c_2",   NPCX_I2C_PORT2,   400, GPIO_I2C2_SCL,   GPIO_I2C2_SDA},
-	{"i2c_3",   NPCX_I2C_PORT3,   400, GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPC mux configuration */
-struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	[USB_PD_PORT_ANX7447] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			/* Verified on v1.1 */
-			.addr_flags = AN7447_TCPC3_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	}
-};
-
-struct pi3usb9281_config pi3usb9281_chips[] = {
-	[USB_PD_PORT_PS8751] = {
-		.i2c_port = I2C_PORT_USB_CHARGER_1,
-		.mux_lock = NULL,
-	},
-	[USB_PD_PORT_ANX7447] = {
-		.i2c_port = I2C_PORT_USB_CHARGER_0,
-		.mux_lock = NULL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
-	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset */
-	gpio_set_level(GPIO_USB_PD_RST_C0, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-	msleep(1);
-	gpio_set_level(GPIO_USB_PD_RST_C0, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	/* After TEST_R release, anx7447/3447 needs 2ms to finish eFuse
-	 * loading.
-	 */
-	msleep(2);
-}
-
-/*
- * Read CBI data from EEPROM via i2c and remap the ps8751 i2c port
- */
-static void ps8751_i2c_remap(void)
-{
-	uint32_t board_version;
-
-	if (cbi_get_board_version(&board_version) != EC_SUCCESS ||
-		board_version > 1)
-		return;
-	/*
-	 * Due to b/118063849, we separate the ps8751 and anx3447 to
-	 * different i2c bus which start from board_version >= 2.
-	 * For the board_version <= 1, the ps8751 and anx3447 TCPC
-	 * use the same i2c bus. Thus, reconfig the ps8751 i2c port
-	 * to i2c_0_0.
-	 */
-	tcpc_config[USB_PD_PORT_PS8751].i2c_info.port = I2C_PORT_TCPC0;
-}
-
-void board_tcpc_init(void)
-{
-	ps8751_i2c_remap();
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-	}
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (!gpio_get_level(GPIO_USB_PD_RST_C0))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-
-	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Check if PMIC fault registers indicate VR fault. If yes, print out fault
- * register info to console. Additionally, set panic reason so that the OS can
- * check for fault register info by looking at offset 0x14(PWRSTAT1) and
- * 0x15(PWRSTAT2) in cros ec panicinfo.
- */
-static void board_report_pmic_fault(const char *str)
-{
-	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
-	uint32_t info;
-
-	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
-		return;
-
-	if (!(vrfault & BIT(4)))
-		return;
-
-	/* VRFAULT has occurred, print VRFAULT status bits. */
-
-	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, &pwrstat1);
-
-	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, &pwrstat2);
-
-	CPRINTS("PMIC VRFAULT: %s", str);
-	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
-		pwrstat2);
-
-	/* Clear all faults -- Write 1 to clear. */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, BIT(4));
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x16, pwrstat1);
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x17, pwrstat2);
-
-	/*
-	 * Status of the fault registers can be checked in the OS by looking at
-	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
-	 */
-	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
-	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
-}
-
-static void board_pmic_disable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (0)   - Disable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x3a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x2a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x3a);
-}
-
-static void board_pmic_enable_slp_s0_vr_decay(void)
-{
-	/*
-	 * VCCIOCNT:
-	 * Bit 6    (1)   - Enable decay of VCCIO on SLP_S0# assertion
-	 * Bits 5:4 (11)  - Nominal output voltage: 0.850V
-	 * Bits 3:2 (10)  - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10)  - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x7a);
-
-	/*
-	 * V18ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (10) - Nominal voltage set to 1.8V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x34, 0x6a);
-
-	/*
-	 * V085ACNT:
-	 * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion
-	 * Bits 5:4 (11) - Nominal voltage 1.0V
-	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
-	 * Bits 1:0 (10) - VR set to AUTO operating mode
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
-}
-
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
-		board_pmic_enable_slp_s0_vr_decay();
-	else if (state == HOST_SLEEP_EVENT_S0IX_RESUME)
-		board_pmic_disable_slp_s0_vr_decay();
-}
-
-static void board_pmic_init(void)
-{
-	board_report_pmic_fault("SYSJUMP");
-
-	if (system_jumped_late())
-		return;
-
-	/*
-	 * DISCHGCNT2 - enable 100 ohm discharge on
-	 * V5A_DS3/V33A_DSW/V33A_PCH/V1.8A
-	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3d, 0x55);
-	/* DISCHGCNT3 - enable 100 ohm discharge on V1.8U_25U/V1.00A */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x44);
-	/* DISCHGCNT4 - enable 100 ohm discharge on v1.8S */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3f, 0x04);
-
-	board_pmic_disable_slp_s0_vr_decay();
-
-	/* VRMODECTRL - disable low-power mode for all rails */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x1f);
-}
-DECLARE_DEFERRED(board_pmic_init);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/*
-	 * This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
-	 * whenever the EC is not doing SPI flash transactions. This avoids
-	 * floating SPI buffer input (MISO), which causes power leakage (see
-	 * b/64797021).
-	 */
-	NPCX_PUPD_EN1 |= BIT(NPCX_DEVPU1_F_SPI_PUD_EN);
-
-	/* Provide AC status to the PCH */
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-
-	/* Enable sensors power supply */
-	gpio_set_level(GPIO_EN_PP1800_DX_SENSOR, 1);
-
-	/* Enable VBUS interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_VBUS_DET_L);
-	gpio_enable_interrupt(GPIO_USB_C1_VBUS_DET_L);
-
-	/* Enable pericom BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Initialize PMIC */
-	hook_call_deferred(&board_pmic_init_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void usb_charge_mode_init(void)
-{
-	/*
-	 * By default, turn the charging off when system suspends.
-	 * If system power on with connecting a USB device,
-	 * the OS must send an event to EC to clear the
-	 * inhibit_charging_in_suspend.
-	 */
-	usb_charge_set_mode(0, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			USB_DISALLOW_SUSPEND_CHARGE);
-}
-DECLARE_HOOK(HOOK_INIT, usb_charge_mode_init, HOOK_PRIO_DEFAULT + 1);
-
-/**
- * Buffer the AC present GPIO to the PCH.
- */
-static void board_extpower(void)
-{
-	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	/* charge port is a physical port */
-	int is_real_port = (charge_port >= 0 &&
-			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/* check if we are source VBUS on the port */
-	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
-						       GPIO_USB_C1_5V_EN);
-
-	if (is_real_port && source) {
-		CPRINTF("Skip enable p%d", charge_port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTF("New chg p%d", charge_port);
-
-	if (charge_port == CHARGE_PORT_NONE) {
-		/* Disable both ports */
-		gpio_set_level(GPIO_EN_USB_C0_CHARGE_EC_L, 1);
-		gpio_set_level(GPIO_EN_USB_C1_CHARGE_EC_L, 1);
-	} else {
-		/* Make sure non-charging port is disabled */
-		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_EC_L :
-					     GPIO_EN_USB_C1_CHARGE_EC_L, 1);
-		/* Enable charging port */
-		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-					     GPIO_EN_USB_C0_CHARGE_EC_L, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 96% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
-}
-
-void board_hibernate(void)
-{
-	CPRINTS("Triggering PMIC shutdown.");
-	uart_flush_output();
-
-	/* Trigger PMIC shutdown. */
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
-		/*
-		 * If we can't tell the PMIC to shutdown, instead reset
-		 * and don't start the AP. Hopefully we'll be able to
-		 * communicate with the PMIC next time.
-		 */
-		CPRINTS("PMIC i2c failed.");
-		system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
-	}
-
-	/* Await shutdown. */
-	while (1)
-		;
-}
-
-const struct pwm_t pwm_channels[] = {
-	/*
-	 * 1.2kHz is a multiple of both 50 and 60. So a video recorder
-	 * (generally designed to ignore either 50 or 60 Hz flicker) will not
-	 * alias with refresh rate.
-	 */
-	[PWM_CH_KBLIGHT] = { 4, 0, 1200 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Lid Sensor mutex */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-static struct kionix_accel_data g_kx022_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(-1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0 },
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
-
-struct motion_sensor_t base_accel_icm = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t base_gyro_icm = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t lid_accel_kx022 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support lid angle calculation. */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 0,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-static void board_detect_motionsense(void)
-{
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-		motion_sensors[LID_ACCEL] = lid_accel_kx022;
-		ccprints("LID_ACCEL is KX022");
-	} else
-		ccprints("LID_ACCEL is BMA253");
-
-	if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = base_accel_icm;
-		motion_sensors[BASE_GYRO] = base_gyro_icm;
-		ccprints("BASE_ACCEL is ICM426XX");
-	} else
-		ccprints("BASE_ACCEL is BMI160");
-}
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT);
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-static void board_chipset_reset(void)
-{
-	board_report_pmic_fault("CHIPSET RESET");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	gpio_set_level(GPIO_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	gpio_set_level(GPIO_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_PP3300_TRACKPAD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_PP3300_TRACKPAD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/board/rammus/board.h b/board/rammus/board.h
deleted file mode 100644
index dc2ae71de8..0000000000
--- a/board/rammus/board.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Rammus board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_BOARD_FORCE_RESET_PIN
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_DPTF
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_CHIP_PANIC_BACKUP
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25X40
-#define CONFIG_VBOOT_HASH
-#define CONFIG_SHA256_UNROLLED
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_WATCHDOG_HELP
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND \
-	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
-#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
-#define WIRELESS_GPIO_WLAN_POWER GPIO_EN_PP3300_DX_WLAN
-
-/* EC console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BUTTON
-
-/* Port80 */
-#undef CONFIG_PORT80_HISTORY_LEN
-#define CONFIG_PORT80_HISTORY_LEN 256
-
-/* SOC */
-#define CONFIG_CHIPSET_SKYLAKE
-#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-
-/* Battery */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW /* This, or just RAMP? */
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_ISL9238
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_PSYS
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
-
-/* Sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_BD99992GW
-#define CONFIG_THERMISTOR_NCP15WB
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#undef CONFIG_SENSOR_TIGHT_TIMESTAMPS
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE
-
-/* USB */
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-/* TODO(b:121222079): Remove the config before FSI */
-#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* BC 1.2 charger */
-#define CONFIG_BC12_DETECT_PI3USB9281
-#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
-
-/* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-
-/* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/* Rename GPIOs */
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_RSMRST_L_PGOOD	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK
-#define GPIO_POWER_BUTTON_L	GPIO_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_ENABLE_BACKLIGHT	GPIO_BL_DISABLE_L
-#define GPIO_CPU_PROCHOT	GPIO_PCH_PROCHOT
-#define GPIO_PCH_PWRBTN_L	GPIO_PCH_PWR_BTN_L
-#define GPIO_EC_PLATFORM_RST	GPIO_PLATFORM_RST
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* Smart Battery Temperature */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-/* TODO(crosbug.com/p/61098): Verify the numbers below. */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void motion_interrupt(enum gpio_signal signal);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/rammus/build.mk b/board/rammus/build.mk
deleted file mode 100644
index 5a9cabdcae..0000000000
--- a/board/rammus/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o cbi_ssfc.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_LED_COMMON)+=led.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/rammus/cbi_ssfc.c b/board/rammus/cbi_ssfc.c
deleted file mode 100644
index e1f6fa4bd2..0000000000
--- a/board/rammus/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union rammus_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C+1);
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return cached_ssfc.lid_sensor;
-}
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return cached_ssfc.base_sensor;
-}
diff --git a/board/rammus/cbi_ssfc.h b/board/rammus/cbi_ssfc.h
deleted file mode 100644
index 2ca20f2376..0000000000
--- a/board/rammus/cbi_ssfc.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _RAMMUS_CBI_SSFC__H_
-#define _RAMMUS_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Rammus CBI Second Source Factory Cache
- */
-
-/*
- * Lid Sensor (Bits 2-0)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_LID_BMA255 = 1,
-	SSFC_SENSOR_LID_KX022 = 2
-};
-
-/*
- * Base Sensor (Bits 5-3)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BASE_BMI160 = 1,
-	SSFC_SENSOR_BASE_ICM426XX = 2,
-};
-
-union rammus_cbi_ssfc {
-	struct {
-		enum ec_ssfc_lid_sensor lid_sensor : 3;
-		enum ec_ssfc_base_sensor base_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-/**
- * Get the base sensor type form SSFC_CONFIG.
- *
- * @return the base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-#endif /* _RAMMUS_CBI_SSFC__H_ */
diff --git a/board/rammus/ec.tasklist b/board/rammus/ec.tasklist
deleted file mode 100644
index f708a41386..0000000000
--- a/board/rammus/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/rammus/gpio.inc b/board/rammus/gpio.inc
deleted file mode 100644
index 1e05cbe9a7..0000000000
--- a/board/rammus/gpio.inc
+++ /dev/null
@@ -1,125 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,  PIN(3, 7), GPIO_INT_FALLING,                tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,  PIN(C, 5), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(SLP_S0_L,           PIN(7, 5), GPIO_INT_BOTH,                    power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L_PCH,      PIN(6, 2), GPIO_INT_BOTH,                    power_signal_interrupt)
-GPIO_INT(ROP_EC_RSMRST_L,    PIN(B, 0), GPIO_INT_BOTH,                    power_signal_interrupt)
-GPIO_INT(ROP_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH,                    power_signal_interrupt)
-GPIO_INT(PWR_BTN_ODL,        PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,     power_button_interrupt)
-GPIO_INT(LID_OPEN,           PIN(6, 7), GPIO_INT_BOTH,                    lid_interrupt)
-GPIO_INT(VOLDN_BTN,          PIN(8, 3), GPIO_INT_BOTH,                    button_interrupt)
-GPIO_INT(VOLUP_BTN,          PIN(3, 6), GPIO_INT_BOTH,                    button_interrupt)
-GPIO_INT(WP_L,               PIN(4, 0), GPIO_INT_BOTH,                    switch_interrupt)
-GPIO_INT(ROP_EC_ACOK,        PIN(C, 1), GPIO_INT_BOTH,                    extpower_interrupt)
-GPIO_INT(USB_C0_VBUS_DET_L,  PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP,     vbus0_evt)
-GPIO_INT(USB_C1_VBUS_DET_L,  PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,     vbus1_evt)
-GPIO_INT(USB_C0_BC12_INT_L,  PIN(D, 3), GPIO_INT_FALLING,                 usb0_evt)
-GPIO_INT(USB_C1_BC12_INT_L,  PIN(3, 3), GPIO_INT_FALLING,                 usb1_evt)
-GPIO_INT(BASE_SIXAXIS_INT_L, PIN(7, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(TABLET_MODE,        PIN(C, 6), GPIO_INT_BOTH,                    gmr_tablet_switch_isr)
-
-GPIO(EN_PP3300_TRACKPAD,     PIN(4, 5), GPIO_OUT_LOW)                /* Enable TouchPad */
-GPIO(PCH_RTCRST,             PIN(8, 2), GPIO_OUT_LOW)                /* RTCRST# to SOC */
-GPIO(BL_DISABLE_L,           PIN(5, 6), GPIO_OUT_LOW)                /* Enable Backlight */
-GPIO(WLAN_OFF_L,             PIN(7, 2), GPIO_OUT_LOW)                /* Disable WLAN */
-GPIO(EN_PP3300_DX_WLAN,      PIN(A, 7), GPIO_OUT_LOW)                /* Enable WLAN 3.3V Power */
-GPIO(PCH_PROCHOT,            PIN(8, 1), GPIO_OUT_HIGH)               /* PROCHOT# to SOC */
-GPIO(PCH_ACPRESENT,          PIN(5, 0), GPIO_ODR_LOW)                /* ACOK to SOC */
-GPIO(PCH_WAKE_L,             PIN(A, 3), GPIO_ODR_HIGH)               /* Wake SOC */
-GPIO(PCH_RSMRST_L,           PIN(7, 0), GPIO_OUT_LOW)                /* RSMRST# to SOC */
-GPIO(PCH_PWR_BTN_L,          PIN(C, 4), GPIO_ODR_HIGH)               /* Power Button to SOC */
-GPIO(PLATFORM_RST,           PIN(A, 6), GPIO_OUT_LOW)                /* EC Reset to LDO_EN */
-GPIO(SYS_RESET_L,            PIN(6, 1), GPIO_ODR_HIGH)               /* Cold Reset to SOC */
-GPIO(SLP_SUS_L_PMIC,         PIN(8, 5), GPIO_OUT_LOW)                /* SLP_SUS# to PMIC */
-GPIO(BATT_PRES_L,            PIN(3, 4), GPIO_INPUT)                  /* Battery Present */
-GPIO(CCD_MODE_ODL,           PIN(6, 3), GPIO_INPUT)                  /* Case Closed Debug Mode */
-GPIO(ENTERING_RW,            PIN(7, 6), GPIO_OUTPUT)                 /* EC Entering RW */
-GPIO(ROP_EC_INT_L,           PIN(6, 0), GPIO_INPUT)                  /* PMIC interrupt */
-GPIO(KB_BL_EN,               PIN(7, 1), GPIO_OUT_LOW)                /* Keyboard backlight enable */
-#ifndef CONFIG_POWER_S0IX
-GPIO(SLP_S0_L,               PIN(7, 5), GPIO_INPUT)
-#endif
-
-/* Sensor Power */
-GPIO(EN_PP1800_DX_SENSOR,    PIN(E, 7), GPIO_OUT_LOW)
-
-/* Reserved, no function */
-GPIO(EN_PP3300_USB_PD,       PIN(0, 1), GPIO_INPUT)
-/* Reserved, output low to disable Board ID ADC by default */
-GPIO(BRD_ID_EN,              PIN(0, 2), GPIO_OUT_LOW)                /* Enable for board ID ADC */
-/* Reserved, for the lid accelerator interrupt */
-GPIO(LID_ACCEL_INT_L,        PIN(D, 2), GPIO_INPUT | GPIO_SEL_1P8V | GPIO_PULL_UP)  /* LID Accelerator interrupt */
-/* Reserved, changing touchpad interrupt behavior for wakeup */
-GPIO(TP_INT_CONN,            PIN(C, 2), GPIO_INPUT)                  /* Touchpad interrupt */
-/* Reserved, output low to enable touchpad interrupt by default */
-GPIO(TP_INT_EN,              PIN(A, 1), GPIO_OUT_LOW)                /* Enable Touchpad interrupt */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_0_SCL,             PIN(B, 5), GPIO_INPUT)                  /* EC_I2C0_0_USBC_3V3_SCL */
-GPIO(I2C0_0_SDA,             PIN(B, 4), GPIO_INPUT)                  /* EC_I2C0_0_USBC_3V3_SDA */
-GPIO(I2C0_1_SCL,             PIN(B, 3), GPIO_INPUT)                  /* EC_I2C0_1_USBC_3V3_SCL */
-GPIO(I2C0_1_SDA,             PIN(B, 2), GPIO_INPUT)                  /* EC_I2C0_1_USBC_3V3_SDA */
-GPIO(I2C1_SCL,               PIN(9, 0), GPIO_INPUT)                  /* EC_I2C1_3V3_SCL */
-GPIO(I2C1_SDA,               PIN(8, 7), GPIO_INPUT)                  /* EC_I2C1_3V3_SDA */
-GPIO(I2C2_SCL,               PIN(9, 2), GPIO_INPUT)                  /* EC_I2C2_PMIC_3V3_SCL */
-GPIO(I2C2_SDA,               PIN(9, 1), GPIO_INPUT)                  /* EC_I2C2_PMIC_3V3_SDA */
-GPIO(I2C3_SCL,               PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)  /* EC_I2C3_SENSOR_1V8_SCL */
-GPIO(I2C3_SDA,               PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)  /* EC_I2C3_SENSOR_1V8_SDA */
-
-/* rev0: 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
-GPIO(EN_USB_C0_5V_OUT,       PIN(3, 2), GPIO_OUT_LOW)                /* C0 5V Enable */
-GPIO(EN_USB_C0_3A,           PIN(6, 6), GPIO_OUT_LOW)                /* C0 Enable 3A */
-GPIO(EN_USB_C0_CHARGE_EC_L,  PIN(C, 0), GPIO_OUT_LOW)                /* C0 Charge enable */
-GPIO(EN_USB_C1_5V_OUT,       PIN(B, 1), GPIO_OUT_LOW)                /* C1 5V Enable */
-GPIO(EN_USB_C1_3A,           PIN(3, 5), GPIO_OUT_LOW)                /* C1 3A Enable */
-GPIO(EN_USB_C1_CHARGE_EC_L,  PIN(C, 3), GPIO_OUT_LOW)                /* C1 Charge enable */
-GPIO(USB_PD_RST_C0,          PIN(0, 3), GPIO_OUT_LOW)                /* C0 PD Reset */
-GPIO(USB_C1_PD_RST_ODL,      PIN(7, 4), GPIO_ODR_HIGH)               /* C1 PD Reset */
-GPIO(USB_C0_DP_HPD,          PIN(9, 4), GPIO_INPUT)                  /* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,          PIN(A, 5), GPIO_INPUT)                  /* C1 DP Hotplug Detect */
-GPIO(USB2_ID2,               PIN(9, 5), GPIO_OUT_LOW)                /* USB OTG ID */
-
-/* USB Type-A control */
-GPIO(USB_A_CHARGE_EN_L,      PIN(0, 0), GPIO_OUT_LOW)
-GPIO(EN_USB_A_5V,            PIN(8, 4), GPIO_OUT_LOW)
-
-/* LEDs */
-GPIO(CHG_LED1,               PIN(8, 0), GPIO_OUT_LOW)
-GPIO(CHG_LED2,               PIN(B, 7), GPIO_OUT_LOW)
-GPIO(PWR_LED,                PIN(8, 6), GPIO_OUT_LOW)
-
-/* Alternate functions GPIO definitions */
-/* UART pins */
-ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)     /* GPIO64-65 */  /* UART from EC to Servo */
-
-/* I2C pins */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)      /* GPIO87 */     /* EC_I2C1_3V3_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)      /* GPIO90 */     /* EC_I2C1_3V3_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)      /* GPIO91-92 */  /* EC_I2C2_PMIC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)      /* GPIOB4-B5 */  /* EC_I2C0_0_USBC_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)      /* GPOPB2-B3 */  /* EC_I2C0_1_3V3_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)      /* GPIOD0-D1 */  /* EC_I2C3_SENSOR_1V8_SDA/SCL */
-
-/* PWM pins */
-ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)      /* GPIOB6 */     /* PWM KB Backlight */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)    /* GPIO30-31 */     /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)    /* GPIO22-27 */     /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)   /* GPIO20-21 */     /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)   /* GPIO10-16 */     /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)   /* GPIO05-07 */     /* KSO_10-12 */
-GPIO(KBD_KSO2,               PIN(1, 7), GPIO_OUT_LOW)                /* EC_KSO_02_INV */
diff --git a/board/rammus/led.c b/board/rammus/led.c
deleted file mode 100644
index a86e11e3a0..0000000000
--- a/board/rammus/led.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ON 1
-#define LED_OFF 0
-#define LED_TOTAL_TICKS 20
-#define LED_CHARGE_PULSE 10
-#define LED_POWER_PULSE 15
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_charge_state {
-	LED_STATE_DISCHARGE = 0,
-	LED_STATE_CHARGE,
-	LED_STATE_FULL,
-	LED_STATE_ERROR_PHASE0,
-	LED_STATE_ERROR_PHASE1,
-	LED_CHARGE_STATE_COUNT
-};
-
-enum led_power_state {
-	LED_STATE_S0 = 0,
-	LED_STATE_S3_PHASE0,
-	LED_STATE_S3_PHASE1,
-	LED_STATE_S5,
-	LED_POWER_STATE_COUNT
-};
-
-static const struct {
-	uint8_t led1:1;
-	uint8_t led2:1;
-} led_chg_state_table[] = {
-	[LED_STATE_DISCHARGE] = {LED_OFF, LED_OFF},
-	[LED_STATE_CHARGE] = {LED_OFF, LED_ON},
-	[LED_STATE_FULL] = {LED_ON, LED_OFF},
-	[LED_STATE_ERROR_PHASE0] = {LED_OFF, LED_OFF},
-	[LED_STATE_ERROR_PHASE1] = {LED_OFF, LED_ON}
-};
-
-static const struct {
-	uint8_t led:1;
-} led_pwr_state_table[] = {
-	[LED_STATE_S0] = {LED_ON},
-	[LED_STATE_S3_PHASE0] = {LED_OFF},
-	[LED_STATE_S3_PHASE1] = {LED_ON},
-	[LED_STATE_S5] = {LED_OFF}
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	gpio_set_level(GPIO_PWR_LED, brightness[EC_LED_COLOR_WHITE]);
-	gpio_set_level(GPIO_CHG_LED1, brightness[EC_LED_COLOR_GREEN]);
-	gpio_set_level(GPIO_CHG_LED2, brightness[EC_LED_COLOR_AMBER]);
-
-	return EC_SUCCESS;
-}
-
-void config_power_led(enum led_power_state state)
-{
-	gpio_set_level(GPIO_PWR_LED, led_pwr_state_table[state].led);
-}
-
-void config_battery_led(enum led_charge_state state)
-{
-	gpio_set_level(GPIO_CHG_LED1, led_chg_state_table[state].led1);
-	gpio_set_level(GPIO_CHG_LED2, led_chg_state_table[state].led2);
-}
-
-static void rammus_led_set_power(void)
-{
-	static unsigned int power_ticks;
-	int chipset_state;
-
-	chipset_state = chipset_in_state(CHIPSET_STATE_HARD_OFF) |
-			(chipset_in_state(CHIPSET_STATE_SOFT_OFF) << 1) |
-			(chipset_in_state(CHIPSET_STATE_SUSPEND)  << 2) |
-			(chipset_in_state(CHIPSET_STATE_ON) << 3) |
-			(chipset_in_state(CHIPSET_STATE_STANDBY) << 4);
-
-	switch (chipset_state) {
-	case CHIPSET_STATE_ON:
-		config_power_led(LED_STATE_S0);
-		power_ticks = 0;
-		break;
-	case CHIPSET_STATE_SUSPEND:
-	case CHIPSET_STATE_STANDBY:
-		if ((power_ticks++ % LED_TOTAL_TICKS) < LED_POWER_PULSE)
-			config_power_led(LED_STATE_S3_PHASE0);
-		else
-			config_power_led(LED_STATE_S3_PHASE1);
-		break;
-	case CHIPSET_STATE_HARD_OFF:
-	case CHIPSET_STATE_SOFT_OFF:
-		config_power_led(LED_STATE_S5);
-		power_ticks = 0;
-		break;
-	default:
-		break;
-	}
-}
-
-static void rammus_led_set_battery(void)
-{
-	enum charge_state chg_state = charge_get_state();
-	int charge_percent = charge_get_percent();
-	static unsigned int charge_ticks;
-
-	/* CHIPSET_STATE_OFF */
-	switch (chg_state) {
-	case PWR_STATE_DISCHARGE:
-		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
-			config_battery_led(LED_STATE_FULL);
-		else
-			config_battery_led(LED_STATE_DISCHARGE);
-		charge_ticks = 0;
-		break;
-	case PWR_STATE_CHARGE:
-		config_battery_led(LED_STATE_CHARGE);
-		charge_ticks = 0;
-		break;
-	case PWR_STATE_ERROR:
-		if ((charge_ticks++ % LED_TOTAL_TICKS) < LED_CHARGE_PULSE)
-			config_battery_led(LED_STATE_ERROR_PHASE0);
-		else
-			config_battery_led(LED_STATE_ERROR_PHASE1);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			config_battery_led(LED_STATE_FULL);
-		else
-			config_battery_led(LED_STATE_OFF);
-		charge_ticks = 0;
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Called by hook task every 200 ms
- */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		rammus_led_set_power();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		rammus_led_set_battery();
-}
-
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/rammus/usb_pd_policy.c b/board/rammus/usb_pd_policy.c
deleted file mode 100644
index 652c9bb259..0000000000
--- a/board/rammus/usb_pd_policy.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	gpio_set_level(port ? GPIO_EN_USB_C1_3A : GPIO_EN_USB_C0_3A,
-		       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN,
-		       vbus_en[port]);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-			      GPIO_EN_USB_C0_CHARGE_EC_L, 1);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_DET_L :
-				      GPIO_USB_C0_VBUS_DET_L);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_SLP_SUS_L_PMIC);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* Only port 0 supports device mode. */
-	if (port != 0)
-		return;
-
-	gpio_set_level(GPIO_USB2_ID2,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-}
diff --git a/board/rammus/vif_override.xml b/board/rammus/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/rammus/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/redrix/battery.c b/board/redrix/battery.c
deleted file mode 100644
index 4e74b92acb..0000000000
--- a/board/redrix/battery.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-
-/*
- * Battery info for all Redrix battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-14-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/redrix/board.c b/board/redrix/board.c
deleted file mode 100644
index 3c0f48f2bd..0000000000
--- a/board/redrix/board.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/als_tcs3400.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "peripheral_charger.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* PCHG control */
-#ifdef SECTION_IS_RW
-extern struct pchg_drv ctn730_drv;
-
-struct pchg pchgs[] = {
-	[0] = {
-		.cfg = &(const struct pchg_config) {
-			.drv = &ctn730_drv,
-			.i2c_port = I2C_PORT_WLC,
-			.irq_pin = GPIO_PEN_INT_ODL,
-			.full_percent = 96,
-			.block_size = 128,
-		},
-		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
-	},
-};
-const int pchg_count = ARRAY_SIZE(pchgs);
-#endif
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/redrix/board.h b/board/redrix/board.h
deleted file mode 100644
index 091d4e7318..0000000000
--- a/board/redrix/board.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Redrix board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* WLC pins */
-#ifdef SECTION_IS_RW
-#define CONFIG_PERIPHERAL_CHARGER
-#define CONFIG_DEVICE_EVENT
-#define CONFIG_CTN730
-#endif
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* TODO: b/193452481 - measure and check these values on redrix */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_WLC_NRST_CONN		GPIO_PEN_RST_L
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_USB_C0_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_WLC		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/*
- * see b/174768555#comment22
- */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x58
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* Fan features */
-#define CONFIG_FANS		FAN_CH_COUNT
-#define CONFIG_CUSTOM_FAN_CONTROL
-#define RPM_DEVIATION	1
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR,
-	ADC_TEMP_SENSOR_2_SOC,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_REGULATOR,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR,
-	TEMP_SENSOR_2_SOC,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_REGULATOR,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_FAN2,			/* PWM7 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_1,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_1,
-	MFT_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/redrix/build.mk b/board/redrix/build.mk
deleted file mode 100644
index 0c5e8e6182..0000000000
--- a/board/redrix/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Redrix board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=thermal.o
-board-y+=usbc_config.o
diff --git a/board/redrix/charger.c b/board/redrix/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/redrix/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/redrix/ec.tasklist b/board/redrix/ec.tasklist
deleted file mode 100644
index 937fe97ae0..0000000000
--- a/board/redrix/ec.tasklist
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/redrix/fans.c b/board/redrix/fans.c
deleted file mode 100644
index afa735e929..0000000000
--- a/board/redrix/fans.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-	[MFT_CH_1] = {
-		.module = NPCX_MFT_MODULE_2,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN2,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-static const struct fan_conf fan_conf_1 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN2,
-};
-
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 2900,
-	.rpm_max = 7300,
-};
-
-static const struct fan_rpm fan_rpm_1 = {
-	.rpm_min = 1900,
-	.rpm_start = 2900,
-	.rpm_max = 7300,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-	[FAN_CH_1] = {
-		.conf = &fan_conf_1,
-		.rpm = &fan_rpm_1,
-	},
-};
-
diff --git a/board/redrix/fw_config.c b/board/redrix/fw_config.c
deleted file mode 100644
index e59688b17d..0000000000
--- a/board/redrix/fw_config.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union redrix_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for redrix if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union redrix_cbi_fw_config fw_config_defaults = {
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Redrix FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		}
-	}
-}
-
-union redrix_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-bool ec_cfg_has_eps(void)
-{
-	return (fw_config.eps == EPS_ENABLED);
-}
diff --git a/board/redrix/fw_config.h b/board/redrix/fw_config.h
deleted file mode 100644
index 6480f07b35..0000000000
--- a/board/redrix/fw_config.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_BRYA_FW_CONFIG_H_
-#define __BOARD_BRYA_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Redrix board.
- *
- * Source of truth is the project/brya/redrix/config.star configuration file.
- */
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-enum ec_cfg_eps_type {
-	EPS_DISABLED = 0,
-	EPS_ENABLED = 1
-};
-
-union redrix_cbi_fw_config {
-	struct {
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				lte_db : 2;
-		uint32_t				ufc : 2;
-		enum ec_cfg_eps_type			eps : 1;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union redrix_cbi_fw_config get_fw_config(void);
-
-/**
- * Check if the FW_CONFIG has enabled privacy screen.
- *
- * @return true if board supports privacy screen, false if the board
- * doesn't support it.
- */
-bool ec_cfg_has_eps(void);
-
-#endif /* __BOARD_BRYA_FW_CONFIG_H_ */
diff --git a/board/redrix/gpio.inc b/board/redrix/gpio.inc
deleted file mode 100644
index 21f8b51ee1..0000000000
--- a/board/redrix/gpio.inc
+++ /dev/null
@@ -1,152 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dsm_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* WLC interrupt. GPIO_PULL_DOWN ensures no IRQ when WLC chip is off. */
-#ifdef SECTION_IS_RW
-GPIO_INT(PEN_INT_ODL, PIN(F, 5), GPIO_INT_RISING | GPIO_PULL_DOWN, pchg_irq)
-#endif
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(9, 6), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN,                    PIN(8, 6), GPIO_OUT_LOW)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_FAN2,                 PIN(5, 0), GPIO_OUT_HIGH)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,            PIN(A, 0), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-GPIO(PEN_RST_L,                      PIN(0, 2), GPIO_ODR_HIGH)
-
-/* LED */
-GPIO(C0_CHARGE_LED_AMBER_L,          PIN(C, 4), GPIO_OUT_HIGH)	/* Amber C0 port */
-GPIO(C0_CHARGE_LED_WHITE_L,          PIN(C, 3), GPIO_OUT_HIGH)	/* White C0 port */
-GPIO(C1_CHARGE_LED_AMBER_L,          PIN(5, 7), GPIO_OUT_HIGH)	/* Amber C1 port */
-GPIO(C1_CHARGE_LED_WHITE_L,          PIN(9, 4), GPIO_OUT_HIGH)	/* White C1 port */
-GPIO(PWR_LED_WHITE_L,                PIN(C, 2), GPIO_OUT_HIGH)	/* Power LED */
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
-ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0)               /* GPIO60/PWM7 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPO66/ARM_L_x86 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
-
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW)
diff --git a/board/redrix/i2c.c b/board/redrix/i2c.c
deleted file mode 100644
index b993a7978e..0000000000
--- a/board/redrix/i2c.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0",
-		.port = I2C_PORT_USB_C0_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0",
-		.port = I2C_PORT_USB_C0_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0",
-		.port = I2C_PORT_USB_C0_MUX,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_RT_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1,retimer1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/redrix/keyboard.c b/board/redrix/keyboard.c
deleted file mode 100644
index 90506163d9..0000000000
--- a/board/redrix/keyboard.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
-		TK_PLAY_PAUSE,		/* T9 */
-		TK_MICMUTE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config keybd2 = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_PRIVACY_SCRN_TOGGLE,	/* T8 */
-		TK_KBD_BKLIGHT_TOGGLE,	/* T9 */
-		TK_MICMUTE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config *
-board_vivaldi_keybd_config(void)
-{
-	if (ec_cfg_has_eps() == 0)
-		return &keybd1;
-	else
-		return &keybd2;
-}
diff --git a/board/redrix/led.c b/board/redrix/led.c
deleted file mode 100644
index bd088bfe97..0000000000
--- a/board/redrix/led.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Redrix
- */
-
-#include <stdint.h>
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "task.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-
-#define LED_TICK_INTERVAL_MS (500 * MSEC)
-#define LED_CYCLE_TIME_MS    (2000 * MSEC)
-#define LED_TICKS_PER_CYCLE  (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS       (1000 * MSEC)
-#define LED_ON_TICKS         (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
-
-static void led_set_color_battery(int port, enum led_color color)
-{
-	enum gpio_signal amber_led, white_led;
-
-	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
-				 GPIO_C0_CHARGE_LED_AMBER_L);
-	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
-				 GPIO_C0_CHARGE_LED_WHITE_L);
-
-	switch (color) {
-	case LED_WHITE:
-		gpio_set_level(white_led, BAT_LED_ON);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_ON);
-		break;
-	case LED_OFF:
-		gpio_set_level(white_led, BAT_LED_OFF);
-		gpio_set_level(amber_led, BAT_LED_OFF);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON);
-		break;
-	default:
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(LEFT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(LEFT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_RIGHT_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(RIGHT_PORT, LED_AMBER);
-		else
-			led_set_color_battery(RIGHT_PORT, LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(LED_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
-}
-
-static void led_set_battery(void)
-{
-	static unsigned int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
-			else
-				led_set_color_battery(RIGHT_PORT, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			led_set_color_battery(LEFT_PORT, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x1) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-static void led_set_power(void)
-{
-	static unsigned int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
-	else
-		led_set_color_power(LED_OFF);
-}
-
-void led_task(void *u)
-{
-	uint32_t start_time;
-	uint32_t task_duration;
-
-	while (1) {
-		start_time = get_time().le.lo;
-
-		if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-			led_set_power();
-
-		led_set_battery();
-
-		/* Compute time for this iteration */
-		task_duration = get_time().le.lo - start_time;
-		/*
-		 * Compute wait time required to for next desired LED tick. If
-		 * the duration exceeds the tick time, then don't sleep.
-		 */
-		if (task_duration < LED_TICK_INTERVAL_MS)
-			usleep(LED_TICK_INTERVAL_MS - task_duration);
-	}
-}
diff --git a/board/redrix/pwm.c b/board/redrix/pwm.c
deleted file mode 100644
index 8e3d9c4022..0000000000
--- a/board/redrix/pwm.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_FAN2] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/redrix/sensors.c b/board/redrix/sensors.c
deleted file mode 100644
index f720a7cd32..0000000000
--- a/board/redrix/sensors.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc_chip.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/als_tcs3400_public.h"
-#include "hooks.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR] = {
-		.name = "TEMP_DDR",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_SOC] = {
-		.name = "TEMP_SOC",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_REGULATOR] = {
-		.name = "TEMP_REGULATOR",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/184702900 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void board_sensors_init(void)
-{
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_R_L);
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR] = {
-		.name = "DDR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR
-	},
-	[TEMP_SENSOR_2_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SOC
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_REGULATOR] = {
-		.name = "Regulator",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_REGULATOR
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_ddr = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to SOC, so we need to use the lower
- * SOC temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_charger = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/*
- * TODO(b/195673113): Need to update for Alder Lake/redrix
- */
-static const struct ec_thermal_config thermal_regulator = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR] = thermal_ddr,
-	[TEMP_SENSOR_2_SOC] = thermal_cpu,
-	[TEMP_SENSOR_3_CHARGER] = thermal_charger,
-	[TEMP_SENSOR_4_REGULATOR] = thermal_regulator,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/redrix/thermal.c b/board/redrix/thermal.c
deleted file mode 100644
index 39d9a49c3a..0000000000
--- a/board/redrix/thermal.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "tablet_mode.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-struct fan_step {
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-
-	/*
-	 * Sensor 1~4 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-
-	/* Fan 1~2 rpm */
-	uint16_t rpm[FAN_CH_COUNT];
-};
-
-static const struct fan_step *fan_step_table;
-
-static const struct fan_step fan_table_clamshell[] = {
-	{
-		/* level 0 */
-		.on = {44, 46, 0, -1},
-		.off = {99, 99, 99, -1},
-		.rpm = {0, 0},
-	},
-	{
-		/* level 1 */
-		.on = {45, 47, 0, -1},
-		.off = {44, 46, 99, -1},
-		.rpm = {3400, 3900},
-	},
-	{
-		/* level 2 */
-		.on = {46, 48, 0, -1},
-		.off = {45, 47, 99, -1},
-		.rpm = {3700, 4200},
-	},
-	{
-		/* level 3 */
-		.on = {47, 49, 0, -1},
-		.off = {46, 48, 99, -1},
-		.rpm = {4100, 4500},
-	},
-	{
-		/* level 4 */
-		.on = {48, 50, 50, -1},
-		.off = {47, 49, 48, -1},
-		.rpm = {4200, 4600},
-	},
-	{
-		/* level 5 */
-		.on = {49, 51, 52, -1},
-		.off = {48, 50, 50, -1},
-		.rpm = {4600, 4900},
-	},
-	{
-		/* level 6 */
-		.on = {100, 100, 100, -1},
-		.off = {49, 51, 52, -1},
-		.rpm = {4900, 5200},
-	},
-};
-
-static const struct fan_step fan_table_tablet[] = {
-	{
-		/* level 0 */
-		.on = {44, 46, 0, -1},
-		.off = {99, 99, 99, -1},
-		.rpm = {0, 0},
-	},
-	{
-		/* level 1 */
-		.on = {45, 47, 0, -1},
-		.off = {44, 46, 99, -1},
-		.rpm = {3400, 3900},
-	},
-	{
-		/* level 2 */
-		.on = {46, 48, 0, -1},
-		.off = {45, 47, 99, -1},
-		.rpm = {3700, 4200},
-	},
-	{
-		/* level 3 */
-		.on = {47, 49, 0, -1},
-		.off = {46, 48, 99, -1},
-		.rpm = {4100, 4500},
-	},
-	{
-		/* level 4 */
-		.on = {48, 50, 50, -1},
-		.off = {47, 49, 48, -1},
-		.rpm = {4200, 4600},
-	},
-	{
-		/* level 5 */
-		.on = {49, 51, 52, -1},
-		.off = {48, 50, 50, -1},
-		.rpm = {4600, 4900},
-	},
-	{
-		/* level 6 */
-		.on = {100, 100, 100, -1},
-		.off = {49, 51, 52, -1},
-		.rpm = {4900, 5200},
-	},
-};
-
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
-
-BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) ==
-	ARRAY_SIZE(fan_table_tablet));
-
-int fan_table_to_rpm(int fan, int *temp)
-{
-	static int current_level;
-	static int prev_tmp[TEMP_SENSOR_COUNT];
-	int new_rpm = 0;
-	int i;
-
-	if (tablet_get_mode())
-		fan_step_table = fan_table_tablet;
-	else
-		fan_step_table = fan_table_clamshell;
-
-	/*
-	 * Compare the current and previous temperature, we have
-	 * the three paths :
-	 *  1. decreasing path. (check the release point)
-	 *  2. increasing path. (check the trigger point)
-	 *  3. invariant path. (return the current RPM)
-	 */
-	if (temp[TEMP_SENSOR_1_DDR] < prev_tmp[TEMP_SENSOR_1_DDR] ||
-	    temp[TEMP_SENSOR_2_SOC] < prev_tmp[TEMP_SENSOR_2_SOC] ||
-	    temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) {
-		for (i = current_level; i > 0; i--) {
-			if (temp[TEMP_SENSOR_1_DDR] <
-				fan_step_table[i].off[TEMP_SENSOR_1_DDR] &&
-			    temp[TEMP_SENSOR_3_CHARGER] <
-				fan_step_table[i].off[TEMP_SENSOR_3_CHARGER] &&
-			    temp[TEMP_SENSOR_2_SOC] <
-				fan_step_table[i].off[TEMP_SENSOR_2_SOC])
-				current_level = i - 1;
-			else
-				break;
-		}
-	} else if (temp[TEMP_SENSOR_1_DDR] > prev_tmp[TEMP_SENSOR_1_DDR] ||
-		   temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] ||
-		   temp[TEMP_SENSOR_3_CHARGER] >
-			prev_tmp[TEMP_SENSOR_3_CHARGER]) {
-		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
-			if ((temp[TEMP_SENSOR_1_DDR] >
-				fan_step_table[i].on[TEMP_SENSOR_1_DDR] &&
-			    temp[TEMP_SENSOR_3_CHARGER] >
-				fan_step_table[i].on[TEMP_SENSOR_3_CHARGER]) ||
-			    temp[TEMP_SENSOR_2_SOC] >
-				fan_step_table[i].on[TEMP_SENSOR_2_SOC])
-				current_level = i + 1;
-			else
-				break;
-		}
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
-		prev_tmp[i] = temp[i];
-
-	ASSERT(current_level < NUM_FAN_LEVELS);
-
-	switch (fan) {
-	case FAN_CH_0:
-		new_rpm = fan_step_table[current_level].rpm[FAN_CH_0];
-		break;
-	case FAN_CH_1:
-		new_rpm = fan_step_table[current_level].rpm[FAN_CH_1];
-		break;
-	default:
-		break;
-	}
-
-	return new_rpm;
-}
-
-void board_override_fan_control(int fan, int *tmp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
-	}
-}
diff --git a/board/redrix/usbc_config.c b/board/redrix/usbc_config.c
deleted file mode 100644
index 73a7b402cc..0000000000
--- a/board/redrix/usbc_config.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C1 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-	[IOEX_C1_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C1_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_4_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C1) {
-		rst_signal = IOEX_USB_C1_RT_RST_ODL;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 1);
-
-	nct38xx_reset_notify(USBC_PORT_C0);
-	nct38xx_reset_notify(USBC_PORT_C1);
-
-	/* wait for chips to come up */
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-static void board_tcpc_init(void)
-{
-	int i;
-
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i) {
-			ioex_config[i].flags &= ~IOEX_FLAGS_DISABLED;
-			ioex_init(i);
-		}
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/179513527): add USB-C support
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/redrix/usbc_config.h b/board/redrix/usbc_config.h
deleted file mode 100644
index dcaa52d7a9..0000000000
--- a/board/redrix/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Redrix board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/redrix/vif_override.xml b/board/redrix/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/redrix/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/reef/battery.c b/board/reef/battery.c
deleted file mode 100644
index 83a3679b26..0000000000
--- a/board/reef/battery.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger_profile_override.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SONY_CORP,
-	BATTERY_PANASONIC,
-	BATTERY_SMP_COS4870,
-	BATTERY_SMP_C22N1626,
-	BATTERY_CPT_C22N1626,
-	BATTERY_TYPE_COUNT,
-};
-
-enum fast_chg_voltage_ranges {
-	VOLTAGE_RANGE_0,
-	VOLTAGE_RANGE_1,
-	VOLTAGE_RANGE_2,
-};
-
-enum temp_range {
-	TEMP_RANGE_0,
-	TEMP_RANGE_1,
-	TEMP_RANGE_2,
-	TEMP_RANGE_3,
-	TEMP_RANGE_4,
-};
-
-struct ship_mode_info {
-	const int ship_mode_reg;
-	const int ship_mode_data;
-	int (*batt_init)(void);
-};
-
-struct board_batt_params {
-	const char *manuf_name;
-	const struct ship_mode_info *ship_mode_inf;
-	const struct battery_info *batt_info;
-	const struct fast_charge_params *fast_chg_params;
-};
-
-#define DEFAULT_BATTERY_TYPE BATTERY_SONY_CORP
-#define SONY_DISCHARGE_DISABLE_FET_BIT (0x01 << 13)
-#define PANASONIC_DISCHARGE_ENABLE_FET_BIT (0x01 << 14)
-#define C22N1626_DISCHARGE_ENABLE_FET_BIT (0x01 << 0)
-
-/* keep track of previous charge profile info */
-static const struct fast_charge_profile *prev_chg_profile_info;
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-static const struct fast_charge_profile fast_charge_smp_cos4870_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <=15C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(15),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 944,
-			[VOLTAGE_RANGE_1] = 472,
-		},
-	},
-
-	/* 15C > && <=20C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(20),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1416,
-			[VOLTAGE_RANGE_1] = 1416,
-		},
-	},
-
-	/* 20C > && <=45C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3300,
-			[VOLTAGE_RANGE_1] = 3300,
-		},
-	},
-
-	/* > 45C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_cos4870 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_cos4870_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_cos4870_info[0],
-};
-
-const struct battery_info batt_info_smp_cos4870 = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 46,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static const struct fast_charge_profile fast_charge_sonycorp_info[] = {
-	/* < 10C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(9),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1200,
-			[VOLTAGE_RANGE_1] = 1200,
-		},
-	},
-
-	/* >= 10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2250,
-			[VOLTAGE_RANGE_1] = 2250,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_sonycorp = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_sonycorp_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_sonycorp_info[0],
-};
-
-const struct battery_info batt_info_sonycorp = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_panasonic_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <= 60C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3072,
-			[VOLTAGE_RANGE_1] = 3072,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_panasonic = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_panasonic_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_panasonic_info[0],
-};
-
-const struct battery_info batt_info_panasoic = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_smp_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4672,
-			[VOLTAGE_RANGE_1] = 4672,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_c22n1626_info[0],
-};
-
-static const struct fast_charge_profile fast_charge_cpt_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4600,
-			[VOLTAGE_RANGE_1] = 4600,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_cpt_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_cpt_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_cpt_c22n1626_info[0],
-};
-
-const struct battery_info batt_info_c22n1626 = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static int batt_smp_cos4870_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
-}
-
-static int batt_sony_corp_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [13] : Discharging Disabled
-	 *      : 0b - Allowed to Discharge
-	 *      : 1b - Not Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
-}
-
-static int batt_panasonic_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [14] : Discharging Disabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static int batt_c22n1626_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_PACK_STATUS:
-	 * [0] : Discharging Enabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_smp_cos4870_init,
-};
-
-static const struct ship_mode_info ship_mode_info_sonycorp = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_sony_corp_init,
-};
-
-static const struct ship_mode_info ship_mode_info_panasonic = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_panasonic_init,
-};
-
-static const struct ship_mode_info ship_mode_info_c22n1626= {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_c22n1626_init,
-};
-
-static const struct board_batt_params info[] = {
-	/* BQ40Z555 SONY CORP BATTERY battery specific configurations */
-	[BATTERY_SONY_CORP] = {
-		.manuf_name = "SONYCorp",
-		.ship_mode_inf = &ship_mode_info_sonycorp,
-		.fast_chg_params = &fast_chg_params_sonycorp,
-		.batt_info = &batt_info_sonycorp,
-	},
-
-	/* RAJ240045 Panasoic battery specific configurations */
-	[BATTERY_PANASONIC] = {
-		.manuf_name = "PANASONIC",
-		.ship_mode_inf = &ship_mode_info_panasonic,
-		.fast_chg_params = &fast_chg_params_panasonic,
-		.batt_info = &batt_info_panasoic,
-	},
-
-	/* BQ40Z55 SMP COS4870 BATTERY battery specific configurations */
-	[BATTERY_SMP_COS4870] = {
-		.manuf_name = "SMP-COS4870",
-		.ship_mode_inf = &ship_mode_info_smp_cos4870,
-		.fast_chg_params = &fast_chg_params_smp_cos4870,
-		.batt_info = &batt_info_smp_cos4870,
-	},
-
-	/* BQ40Z55 SMP C22N1626 BATTERY battery specific configurations */
-	[BATTERY_SMP_C22N1626] = {
-		.manuf_name = "AS1FNZD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_smp_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-
-	/* BQ40Z55 CPT C22N1626 BATTERY battery specific configurations */
-	[BATTERY_CPT_C22N1626] = {
-		.manuf_name = "AS1FOAD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_cpt_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-static inline const struct board_batt_params *board_get_batt_params(void)
-{
-	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES;
-}
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	const struct fast_charge_params *chg_params;
-	char name[32];
-	int i;
-
-	if (!battery_manufacturer_name(name, sizeof(name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strcasecmp(name, info[i].manuf_name)) {
-				board_battery_type = i;
-				break;
-			}
-		}
-	}
-
-	/* Initialize fast charging parameters */
-	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s", info[board_battery_type].manuf_name);
-	else
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return board_get_batt_params()->batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	/*
-	 * To avoid inrush current from the external charger, enable
-	 * discharge on AC till the new charger is detected and charge
-	 * detect delay has passed.
-	 */
-	if (!chg_ramp_is_detected() && curr->batt.state_of_charge > 2)
-		return 1;
-
-	return 0;
-}
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
-		/* Re-init board battery if battery presence status changes */
-		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
-			if (bd9995x_get_battery_voltage() >=
-			    board_get_batt_params()->batt_info->voltage_min)
-				batt_pres = BP_NO;
-		} else if (!board_get_batt_params()->ship_mode_inf->batt_init())
-			batt_pres = BP_NO;
-	}
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
-
-int board_battery_initialized(void)
-{
-	return battery_hw_present() == batt_pres_prev;
-}
diff --git a/board/reef/board.c b/board/reef/board.c
deleted file mode 100644
index ed8e83d0a8..0000000000
--- a/board/reef/board.c
+++ /dev/null
@@ -1,932 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Reef board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/als_opt3001.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/baro_bmp280.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-#endif
-
-/*
- * enable_input_devices() is called by the tablet_mode ISR, but changes the
- * state of GPIOs, so its definition must reside after including gpio_list.
- * Use DECLARE_DEFERRED to generate enable_input_devices_data.
- */
-static void enable_input_devices(void);
-DECLARE_DEFERRED(enable_input_devices);
-
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
-void tablet_mode_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = { 2, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_RED] =   { 3, PWM_CONFIG_DSLEEP, 100 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     NPCX_I2C_PORT0_0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     NPCX_I2C_PORT0_1, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO,   400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   NPCX_I2C_PORT2,   400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      NPCX_I2C_PORT3,   100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST
-struct i2c_stress_test i2c_stress_tests[] = {
-/* NPCX_I2C_PORT0_0 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = NPCX_I2C_PORT0_0,
-		.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		.i2c_test = &anx74xx_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT0_1 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = NPCX_I2C_PORT0_1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		.i2c_test = &ps8xxx_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT1 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_GYRO,
-		.addr_flags = BMI160_ADDR0_FLAGS,
-		.i2c_test = &bmi160_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT2 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_BARO,
-		.addr_flags = BMP280_I2C_ADDRESS1_FLAGS,
-		.i2c_test = &bmp280_i2c_stress_test_dev,
-	},
-	{
-		.port = I2C_PORT_LID_ACCEL,
-		.addr_flags = KX022_ADDR1_FLAGS,
-		.i2c_test = &kionix_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ALS
-	{
-		.port = I2C_PORT_ALS,
-		.addr_flags = OPT3001_I2C_ADDR1_FLAGS,
-		.i2c_test = &opt3001_i2c_stress_test_dev,
-	},
-#endif
-
-/* NPCX_I2C_PORT3 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-	{
-		.i2c_test = &battery_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-	{
-		.i2c_test = &bd9995x_i2c_stress_test_dev,
-	},
-#endif
-};
-const int i2c_test_dev_used = ARRAY_SIZE(i2c_stress_tests);
-#endif /* CONFIG_CMD_I2C_STRESS_TEST */
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_0,
-			.addr_flags = ANX74XX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = NPCX_I2C_PORT0_1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BD9995X_ADDR_FLAGS,
-		.drv = &bd9995x_drv,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	/* 0x98 sets lower EQ of DP port (4.5db) */
-	mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-};
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX74XX)
-		return;
-
-	switch (mode) {
-	case ANX74XX_NORMAL_MODE:
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-		break;
-	case ANX74XX_STANDBY_MODE:
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset to TCPC1 (ps8751) */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-
-	/* Assert reset to TCPC0 (anx3429) */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	/* TCPC1 (ps8751) requires 1ms reset down assertion */
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-
-	/* Deassert reset to TCPC1 */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	/* Disable TCPC0 power */
-	gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-
-	/*
-	 * anx3429 requires 10ms reset/power down assertion
-	 */
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int reg;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/*
-	 * TODO: Remove when Reef is updated with PS8751 A3.
-	 *
-	 * Force PS8751 A2 to wake from low power mode.
-	 * If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 *
-	 * NOTE: PS8751 A3 will wake on any I2C access.
-	 */
-	i2c_read8(NPCX_I2C_PORT0_1, 0x08, 0xA0, &reg);
-
-	/* Enable TCPC0 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable TCPC1 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-#endif
-	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && gpio_get_level(GPIO_PMIC_EN))
-		return;
-
-	/* Enable PP5000 before PP3300 due to NFC: chrome-os-partner:50807 */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-	while (!gpio_get_level(GPIO_PP5000_PG))
-		;
-
-	/*
-	 * To prevent SLP glitches, PMIC_EN (V5A_EN) should be enabled
-	 * at the same time as PP3300 (chrome-os-partner:51323).
-	 */
-	/* Enable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 1);
-	while (!gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/* Enable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 1);
-}
-
-static void board_set_tablet_mode(void)
-{
-	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L),
-			TABLET_TRIGGER_LID);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Ensure tablet mode is initialized according to the hardware state
-	 * so that the cached state reflects reality. */
-	board_set_tablet_mode();
-
-	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-/* PP3300 needs to be enabled before TCPC init hooks */
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port != 0 && port != 1)
-		panic("Invalid charge port\n");
-
-	return bd9995x_is_vbus_provided(port);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	enum bd9995x_charge_port bd9995x_port;
-	int bd9995x_port_select = 1;
-
-	switch (charge_port) {
-	case USB_PD_PORT_ANX74XX:
-	case USB_PD_PORT_PS8751:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-
-		bd9995x_port = charge_port;
-		break;
-	case CHARGE_PORT_NONE:
-		bd9995x_port_select = 0;
-		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
-
-		/*
-		 * To avoid inrush current from the external charger, enable
-		 * discharge on AC till the new charger is detected and
-		 * charge detect delay has passed.
-		 */
-		if (charge_get_percent() > 2)
-			charger_discharge_on_ac(1);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Enable charging trigger by BC1.2 detection */
-	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
-			   supplier == CHARGE_SUPPLIER_BC12_DCP ||
-			   supplier == CHARGE_SUPPLIER_BC12_SDP ||
-			   supplier == CHARGE_SUPPLIER_OTHER);
-
-	if (bd9995x_bc12_enable_charging(port, bc12_enable))
-		return;
-
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < BD9995X_BC12_MIN_VOLTAGE;
-}
-
-static void enable_input_devices(void)
-{
-	/* We need to turn on tablet mode for motion sense */
-	board_set_tablet_mode();
-
-	/* Then, we disable peripherals only when the lid reaches 360 position.
-	 * (It's probably already disabled by motion_sense_task.)
-	 * We deliberately do not enable peripherals when the lid is leaving
-	 * 360 position. Instead, we let motion_sense_task enable it once it
-	 * reaches laptop zone (180 or less). */
-	if (tablet_get_mode())
-		lid_angle_peripheral_enable(0);
-}
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	/* Enable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-
-	/* Enable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-
-	/* Disable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-	/* FIXME(dhendrix): Drive USB_PD_RST_ODL low to prevent
-	   leakage? (see comment in schematic) */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* FIXME(dhendrix): Add CHIPSET_RESUME and CHIPSET_SUSPEND
-   hooks to enable/disable sensors? */
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * FIXME(dhendrix): Weak symbol hack until we can get a better solution for
- * both Amenia and Reef.
- */
-void chipset_do_shutdown(void)
-{
-	/* Disable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 0);
-
-	/*Disable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 0);
-	while (gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/*Disable 5V rail */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	while (gpio_get_level(GPIO_PP5000_PG))
-		;
-}
-
-void board_hibernate_late(void)
-{
-	int i;
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
-
-		/*
-		 * BD99956 handles charge input automatically. We'll disable
-		 * charge output in hibernate. Charger will assert ACOK_OD
-		 * when VBUS or VCC are plugged in.
-		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-	};
-
-	/* Change GPIOs' state in hibernate for better power consumption */
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
-
-	/*
-	 * Calling gpio_config_module sets disabled alternate function pins to
-	 * GPIO_INPUT.  But to prevent keypresses causing leakage currents
-	 * while hibernating we want to enable GPIO_PULL_UP as well.
-	 */
-	gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x1, 0x7F, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP);
-	/* KBD_KSO2 needs to have a pull-down enabled instead of pull-up */
-	gpio_set_flags_by_mask(0x1, 0x80, GPIO_INPUT | GPIO_PULL_DOWN);
-}
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct bmp280_drv_data_t bmp280_drv_data;
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* FIXME(dhendrix): Copied from Amenia, probably need to tweak for Reef */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_LID_ACCEL,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[BASE_MAG] = {
-	 .name = "Base Mag",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_MAG,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = BIT(11), /* 16LSB / uT, fixed */
-	 .rot_standard_ref = &mag_standard_ref,
-	 .min_frequency = BMM150_MAG_MIN_FREQ,
-	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
-	[BASE_BARO] = {
-	 .name = "Base Baro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMP280,
-	 .type = MOTIONSENSE_TYPE_BARO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmp280_drv,
-	 .drv_data = &bmp280_drv_data,
-	 .port = I2C_PORT_BARO,
-	 .i2c_spi_addr_flags = BMP280_I2C_ADDRESS1_FLAGS,
-	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
-	 .min_frequency = BMP280_BARO_MIN_FREQ,
-	 .max_frequency = BMP280_BARO_MAX_FREQ,
-	},
-	[LID_ALS] = {
-	 .name = "Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_OPT3001,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &opt3001_drv,
-	 .drv_data = &g_opt3001_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = OPT3001_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1; uscale = 0 */
-	 .min_frequency = OPT3001_LIGHT_MIN_FREQ,
-	 .max_frequency = OPT3001_LIGHT_MAX_FREQ,
-	 .config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-
-	/* Enable both the VBUS & VCC ports before entering PG3 */
-	bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
-
-	/* Turn BGATE OFF for saving the power */
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_MAX);
-}
-
-struct {
-	enum reef_board_version version;
-	int thresh_mv;
-} const reef_board_versions[] = {
-	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
-	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
-	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
-	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
-	{ BOARD_VERSION_6, 2020 * 1.03 }, /* 73.2 Kohm */
-	{ BOARD_VERSION_7, 2352 * 1.03 }, /* 115 Kohm */
-	{ BOARD_VERSION_8, 2802 * 1.03 }, /* 261 Kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(reef_board_versions) == BOARD_VERSION_COUNT);
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv, i;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	/* FIXME(dhendrix): enable ADC */
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_ODR_HIGH);
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 0);
-	/* Wait to allow cap charge */
-	msleep(1);
-	mv = adc_read_channel(ADC_BOARD_ID);
-	/* FIXME(dhendrix): disable ADC */
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 1);
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_INPUT);
-
-	if (mv == ADC_READ_ERROR) {
-		version = BOARD_VERSION_UNKNOWN;
-		return version;
-	}
-
-	for (i = 0; i < BOARD_VERSION_COUNT; i++) {
-		if (mv < reef_board_versions[i].thresh_mv) {
-			version = reef_board_versions[i].version;
-			break;
-		}
-	}
-
-	CPRINTS("Board version: %d", version);
-	return version;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/reef/board.h b/board/reef/board.h
deleted file mode 100644
index cc599ce1ba..0000000000
--- a/board/reef/board.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Reef board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-#define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
-
-#define CONFIG_CHARGER_PSYS_READ
-#define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
-
-#define CONFIG_CMD_I2C_STRESS_TEST
-#define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-#define CONFIG_CMD_I2C_STRESS_TEST_ALS
-#define CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-#define CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-#define CONFIG_CMD_I2C_STRESS_TEST_TCPC
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BD9995X
-#define CONFIG_CHARGER_BD9995X_CHGEN
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_USB_CHARGER
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-#define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
-#define GPIO_USB_CTL1 GPIO_EN_PP5000
-
-#define CONFIG_TABLET_MODE
-
-/* USB PD config */
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
-#define CONFIG_USB_PD_TCPM_ANX3429
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_CHIPSET_APOLLOLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_FPU
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_PWM
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_DPTF
-#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define CONFIG_VBOOT_HASH
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
-#define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 512
-
-/*
- * During shutdown sequence TPS65094x PMIC turns off the sensor rails
- * asynchronously to the EC. If we access the sensors when the sensor power
- * rails are off we get I2C errors. To avoid this issue, defer switching
- * the sensors rate if in S3. By the time deferred function is serviced if
- * the chipset is in S5 we can back out from switching the sensor rate.
- *
- * Time taken by V1P8U rail to go down from S3 is 30ms to 60ms hence defer
- * the sensor switching after 60ms.
- */
-#undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
-#define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60)
-
-#define CONFIG_FLASH_SIZE_BYTES 524288
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-/* FIXME(dhendrix): these pins are just normal GPIOs on Reef. Do we need
- * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-
-/* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_ALS			NPCX_I2C_PORT2
-#define I2C_PORT_BARO			NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
-/* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_MAG_CALIBRATE
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ALS_OPT3001
-#define CONFIG_BARO_BMP280
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_GREEN = 0,
-	PWM_CH_LED_RED,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY = 0,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/*
- * For backward compatibility, to report ALS via ACPI,
- * Define the number of ALS sensors: motion_sensor copy the data to the ALS
- * memmap region.
- */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	BASE_MAG,
-	BASE_BARO,
-	LID_ALS,
-	SENSOR_COUNT,
-};
-
-enum reef_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_1,
-	BOARD_VERSION_2,
-	BOARD_VERSION_3,
-	BOARD_VERSION_4,
-	BOARD_VERSION_5,
-	BOARD_VERSION_6,
-	BOARD_VERSION_7,
-	BOARD_VERSION_8,
-	BOARD_VERSION_COUNT,
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/* FIXME(dhendrix): verify all of the below PD_* numbers */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-
-int board_get_version(void);
-
-void board_set_tcpc_power_mode(int port, int mode);
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(BASE_BARO) | BIT(LID_ALS))
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/reef/build.mk b/board/reef/build.mk
deleted file mode 100644
index 728d027803..0000000000
--- a/board/reef/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_VARIANT:=npcx5m6g
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/reef/ec.tasklist b/board/reef/ec.tasklist
deleted file mode 100644
index eeebc0cc59..0000000000
--- a/board/reef/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
deleted file mode 100644
index 5bf83f88bc..0000000000
--- a/board/reef/gpio.inc
+++ /dev/null
@@ -1,177 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(CHARGER_INT_L,		PIN(3, 3), GPIO_INT_FALLING, bd9995x_vbus_interrupt)		/* CHARGER_EC_INT_ODL from BD99956 */
-/*
- * TODO: The pull ups for Parade TCPC interrupt line can be removed in versions
- * of board following EVT in which daughter card (which has an external pull up)
- * will always be inserted.
- */
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING, tcpc_alert_event)			/* from Analogix TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)	/* from Parade TCPC */
-
-GPIO_INT(USB_C0_CABLE_DET,	PIN(C, 5), GPIO_INT_RISING, anx74xx_cable_det_interrupt)	/* CABLE_DET from ANX3429 */
-
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,		PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(6, 0), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,		PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_PWROK_OD */
-
-GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH, extpower_interrupt)			/* ACOK_OD from BD99956 */
-/* TODO: We might remove external pull-up for POWER_BUTTON_L in EVT */
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH, power_button_interrupt)		/* MECH_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,		PIN(6, 7), GPIO_INT_BOTH, lid_interrupt)
-/* Volume up and down buttons need to be swapped. The one closer to the hinge
- * should be volume up and the one closer to the user should be volume down.
- * (cros.bug/p/60057) */
-GPIO_INT(EC_VOLDN_BTN_ODL_SWAPPED,	PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL_SWAPPED,	PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-#define GPIO_EC_VOLDN_BTN_ODL GPIO_EC_VOLUP_BTN_ODL_SWAPPED
-#define GPIO_EC_VOLUP_BTN_ODL GPIO_EC_VOLDN_BTN_ODL_SWAPPED
-/* Tablet switch is active-low. L: lid is attached (360 position) H: detached */
-GPIO_INT(TABLET_MODE_L,		PIN(3, 6), GPIO_INT_BOTH, tablet_mode_interrupt)
-
-GPIO_INT(WP_L,			PIN(4, 0), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt)	/* EC_WP_ODL */
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(9, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-	 bmi160_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(C, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* I2C GPIOs will be set to alt. function later. */
-GPIO(EC_I2C_GYRO_SDA,		PIN(8, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_GYRO_SCL,		PIN(9, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(9, 1), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(9, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_PD_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,	PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(D, 1), GPIO_INPUT)
-
-/*
- * LPC:
- * Pins 46, 47, 51, 52, 53, 54, 55, default to LPC mode.
- * Pin 56 (CLKRUN#) defaults to GPIO mode.
- * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
- * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
- *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option.
- */
-
-GPIO(PCH_SMI_L,			PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
-GPIO(PCH_SCI_L,			PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SCI_ODL */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,              PIN(7, 5), GPIO_INPUT)				/* SLP_S0_L */
-#endif
-
-/*
- * BRD_ID1 is a an ADC pin which will be used to measure multiple values.
- * Assert EC_BRD_ID_EN_ODL and then read BRD_ID1.
- */
-ALTERNATE(PIN_MASK(4, 0x08), 1, MODULE_ADC, 0)
-GPIO(EC_BRD_ID_EN_ODL,		PIN(3, 5), GPIO_INPUT)
-
-GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)
-GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_ODR_HIGH)
-GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)			/* EC_ENTERING_RW */
-
-GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)
-GPIO(EC_BATT_PRES_L,		PIN(3, 4), GPIO_INPUT)
-GPIO(PMIC_EN,			PIN(8, 5), GPIO_OUT_LOW)
-GPIO(EN_PP3300,			PIN(C, 2), GPIO_OUT_LOW)
-GPIO(PP3300_PG,			PIN(6, 2), GPIO_INPUT)
-GPIO(EN_PP5000,			PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PP5000_PG,			PIN(7, 1), GPIO_INPUT)
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 2), GPIO_ODR_LOW)
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,		PIN(A, 1), GPIO_OUT_LOW)
-GPIO(PCH_SYS_PWROK,		PIN(E, 7), GPIO_OUT_LOW)		/* EC_PCH_PWROK */
-GPIO(ENABLE_BACKLIGHT,		PIN(9, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-
-GPIO(WIRELESS_GPIO_WLAN_POWER,	PIN(6, 6), GPIO_ODR_HIGH)		/* EN_PP3300_WLAN_ODL */
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,		PIN(A, 3), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-GPIO(PCH_PWRBTN_L,		PIN(0, 1), GPIO_ODR_HIGH)		/* EC_PCH_PWR_BTN_ODL */
-GPIO(PCH_WAKE_L,		PIN(8, 1), GPIO_ODR_HIGH)		/* EC_PCH_WAKE_ODL */
-GPIO(USB_C0_HPD_1P8_ODL,	PIN(9, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(USB_C1_HPD_1P8_ODL,	PIN(A, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-
-GPIO(USB2_OTG_VBUSSENSE,	PIN(9, 5), GPIO_OUTPUT)
-
-/* EC_PCH_RTCRST is a sledgehammer for resetting SoC state and should rarely
- * be used. Set as input for now, we'll set it as an output when we want to use
- * it. Has external pull-down resistor. */
-GPIO(EC_PCH_RTCRST,		PIN(B, 7), GPIO_INPUT)
-GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)		/* SYS_RST_ODL */
-
-/* FIXME: What, if anything, to do about EC_RST_ODL on VCC1_RST#? */
-
-GPIO(CHARGER_RST_ODL,		PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(USB_A_CHARGE_EN_L,		PIN(4, 2), GPIO_OUT_LOW)
-GPIO(EN_USB_TCPC_PWR,		PIN(C, 3), GPIO_OUT_LOW)
-GPIO(USB1_ENABLE,		PIN(4, 1), GPIO_OUT_LOW)
-
-GPIO(USB_C0_PD_RST_L,		PIN(0, 3), GPIO_OUT_LOW)		/* USB_C0_PD_RST_L */
-GPIO(USB_C1_PD_RST_ODL,		PIN(7, 4), GPIO_ODR_LOW)
-
-/*
- * Configure as input to enable @ 1.5A, output-low to turn off, or output-high
- * to enable @ 3A.
- */
-GPIO(USB_C0_5V_EN,		PIN(D, 3), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C0_5V_OUT, Enable C0 */
-GPIO(USB_C1_5V_EN,		PIN(D, 2), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C1_5V_OUT, Enable C1 */
-
-/* Clear for non-HDI breakout, must be pulled high */
-GPIO(NC1,			PIN(0, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_SEL_1P8V)
-GPIO(NC2,			PIN(8, 4), GPIO_INPUT | GPIO_PULL_UP | GPIO_SEL_1P8V)
-
-GPIO(ENG_STRAP,			PIN(B, 6), GPIO_INPUT)
-
-GPIO(BAT_LED_BLUE,		PIN(8,  0), GPIO_OUT_HIGH)
-GPIO(BAT_LED_AMBER,		PIN(C,  4), GPIO_OUT_HIGH)
-
-/*
- * Alternate function pins
- */
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0xfc), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(0, 0xe0), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-ALTERNATE(PIN_MASK(1, 0x7f), 0,  MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2,			 PIN(1, 7), GPIO_KB_OUTPUT_COL2)
-
-ALTERNATE(PIN(4, 4), 6, MODULE_ADC, 0)		/* TEMP_SENSOR_AMB (FIXME: alt function 6?) */
-ALTERNATE(PIN(4, 5), 6, MODULE_ADC, 0)		/* TEMP_SENSOR_CHARGER (FIXME: alt function?) */
-
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)	/* GPIO87 for EC_I2C_GYRO_SDA */
-ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)	/* GPIO90 for EC_I2C_GYRO_SCL */
-ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)	/* GPIO92-91 for EC_I2C_SENSOR_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)	/* GPIOB5-B4 for EC_I2C_USB_C0_PD_SDA/SCL */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)	/* GPOPB3-B2 for EC_I2C_USB_C1_PD_SDA/SCL */
-ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)	/* GPIOD1-D0 for EC_I2C_POWER_SDA/SCL */
-
-/* FIXME: Make UART RX an interrupt? */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)	/* UART from EC to Servo */
diff --git a/board/reef/led.c b/board/reef/led.c
deleted file mode 100644
index 807b1c109c..0000000000
--- a/board/reef/led.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Reef
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
-#define LOW_BATTERY_PERCENTAGE 10
-
-#define LED_TOTAL_4SECS_TICKS 4
-#define LED_TOTAL_2SECS_TICKS 2
-#define LED_ON_1SEC_TICKS 1
-#define LED_ON_2SECS_TICKS 2
-
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_BLUE,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(led_id, LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int suspend_ticks;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_BLUE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON)) {
-			led_set_color_battery(LED_BLUE);
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Blink once every four seconds. */
-			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
-		} else {
-			led_set_color_battery(LED_OFF);
-		}
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_BLUE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-	battery_ticks++;
-	suspend_ticks++;
-}
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	/*
-	 * Reference board only has one LED, so overload it to act as both
-	 * power LED and battery LED.
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/reef/usb_pd_policy.c b/board/reef/usb_pd_policy.c
deleted file mode 100644
index 2d2ef416b2..0000000000
--- a/board/reef/usb_pd_policy.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
-	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
-
-	/*
-	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-	 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-	 * setting a minimum OCP current of 3186 mA.
-	 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put a 33k
-	 * resistor on ILIM, setting a minimum OCP current of 1505 mA.
-	 */
-	gpio_set_level(gpio, vbus_en[port]);
-	gpio_set_flags(gpio, flags);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Ensure we're not charging from this port */
-	bd9995x_select_input_port(port, 0);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
diff --git a/board/reef/vif_override.xml b/board/reef/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/reef/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/reef_it8320/battery.c b/board/reef_it8320/battery.c
deleted file mode 100644
index 1b16a672b2..0000000000
--- a/board/reef_it8320/battery.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger_profile_override.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SONY_CORP,
-	BATTERY_PANASONIC,
-	BATTERY_SMP_COS4870,
-	BATTERY_SMP_C22N1626,
-	BATTERY_CPT_C22N1626,
-	BATTERY_TYPE_COUNT,
-};
-
-enum fast_chg_voltage_ranges {
-	VOLTAGE_RANGE_0,
-	VOLTAGE_RANGE_1,
-	VOLTAGE_RANGE_2,
-};
-
-enum temp_range {
-	TEMP_RANGE_0,
-	TEMP_RANGE_1,
-	TEMP_RANGE_2,
-	TEMP_RANGE_3,
-	TEMP_RANGE_4,
-};
-
-struct ship_mode_info {
-	const int ship_mode_reg;
-	const int ship_mode_data;
-	int (*batt_init)(void);
-};
-
-struct board_batt_params {
-	const char *manuf_name;
-	const struct ship_mode_info *ship_mode_inf;
-	const struct battery_info *batt_info;
-	const struct fast_charge_params *fast_chg_params;
-};
-
-#define DEFAULT_BATTERY_TYPE BATTERY_SONY_CORP
-#define SONY_DISCHARGE_DISABLE_FET_BIT (0x01 << 13)
-#define PANASONIC_DISCHARGE_ENABLE_FET_BIT (0x01 << 14)
-#define C22N1626_DISCHARGE_ENABLE_FET_BIT (0x01 << 0)
-
-/* keep track of previous charge profile info */
-static const struct fast_charge_profile *prev_chg_profile_info;
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-static const struct fast_charge_profile fast_charge_smp_cos4870_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <=15C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(15),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 944,
-			[VOLTAGE_RANGE_1] = 472,
-		},
-	},
-
-	/* 15C > && <=20C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(20),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1416,
-			[VOLTAGE_RANGE_1] = 1416,
-		},
-	},
-
-	/* 20C > && <=45C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3300,
-			[VOLTAGE_RANGE_1] = 3300,
-		},
-	},
-
-	/* > 45C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_cos4870 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_cos4870_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_cos4870_info[0],
-};
-
-const struct battery_info batt_info_smp_cos4870 = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 46,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static const struct fast_charge_profile fast_charge_sonycorp_info[] = {
-	/* < 10C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(9),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1200,
-			[VOLTAGE_RANGE_1] = 1200,
-		},
-	},
-
-	/* >= 10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2250,
-			[VOLTAGE_RANGE_1] = 2250,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_sonycorp = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_sonycorp_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_sonycorp_info[0],
-};
-
-const struct battery_info batt_info_sonycorp = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_panasonic_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <= 60C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3072,
-			[VOLTAGE_RANGE_1] = 3072,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_panasonic = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_panasonic_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_panasonic_info[0],
-};
-
-const struct battery_info batt_info_panasoic = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_smp_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4672,
-			[VOLTAGE_RANGE_1] = 4672,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_c22n1626_info[0],
-};
-
-static const struct fast_charge_profile fast_charge_cpt_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4600,
-			[VOLTAGE_RANGE_1] = 4600,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_cpt_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_cpt_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_cpt_c22n1626_info[0],
-};
-
-const struct battery_info batt_info_c22n1626 = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static int batt_smp_cos4870_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
-}
-
-static int batt_sony_corp_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [13] : Discharging Disabled
-	 *      : 0b - Allowed to Discharge
-	 *      : 1b - Not Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
-}
-
-static int batt_panasonic_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [14] : Discharging Disabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static int batt_c22n1626_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_PACK_STATUS:
-	 * [0] : Discharging Enabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_smp_cos4870_init,
-};
-
-static const struct ship_mode_info ship_mode_info_sonycorp = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_sony_corp_init,
-};
-
-static const struct ship_mode_info ship_mode_info_panasonic = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_panasonic_init,
-};
-
-static const struct ship_mode_info ship_mode_info_c22n1626 = {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_c22n1626_init,
-};
-
-static const struct board_batt_params info[] = {
-	/* BQ40Z555 SONY CORP BATTERY battery specific configurations */
-	[BATTERY_SONY_CORP] = {
-		.manuf_name = "SONYCorp",
-		.ship_mode_inf = &ship_mode_info_sonycorp,
-		.fast_chg_params = &fast_chg_params_sonycorp,
-		.batt_info = &batt_info_sonycorp,
-	},
-
-	/* RAJ240045 Panasoic battery specific configurations */
-	[BATTERY_PANASONIC] = {
-		.manuf_name = "PANASONIC",
-		.ship_mode_inf = &ship_mode_info_panasonic,
-		.fast_chg_params = &fast_chg_params_panasonic,
-		.batt_info = &batt_info_panasoic,
-	},
-
-	/* BQ40Z55 SMP COS4870 BATTERY battery specific configurations */
-	[BATTERY_SMP_COS4870] = {
-		.manuf_name = "SMP-COS4870",
-		.ship_mode_inf = &ship_mode_info_smp_cos4870,
-		.fast_chg_params = &fast_chg_params_smp_cos4870,
-		.batt_info = &batt_info_smp_cos4870,
-	},
-
-	/* BQ40Z55 SMP C22N1626 BATTERY battery specific configurations */
-	[BATTERY_SMP_C22N1626] = {
-		.manuf_name = "AS1FNZD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_smp_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-
-	/* BQ40Z55 CPT C22N1626 BATTERY battery specific configurations */
-	[BATTERY_CPT_C22N1626] = {
-		.manuf_name = "AS1FOAD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_cpt_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-static inline const struct board_batt_params *board_get_batt_params(void)
-{
-	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
-}
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES;
-}
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	const struct fast_charge_params *chg_params;
-	char name[32];
-	int i;
-
-	if (!battery_manufacturer_name(name, sizeof(name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strcasecmp(name, info[i].manuf_name)) {
-				board_battery_type = i;
-				break;
-			}
-		}
-	}
-
-	/* Initialize fast charging parameters */
-	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s", info[board_battery_type].manuf_name);
-	else
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return board_get_batt_params()->batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	return sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	/*
-	 * To avoid inrush current from the external charger, enable
-	 * discharge on AC till the new charger is detected and charge
-	 * detect delay has passed.
-	 */
-	if (!chg_ramp_is_detected() && curr->batt.state_of_charge > 2)
-		return 1;
-
-	return 0;
-}
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
-		/* Re-init board battery if battery presence status changes */
-		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
-			if (bd9995x_get_battery_voltage() >=
-			    board_get_batt_params()->batt_info->voltage_min)
-				batt_pres = BP_NO;
-		} else if (!board_get_batt_params()->ship_mode_inf->batt_init())
-			batt_pres = BP_NO;
-	}
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
-
-int board_battery_initialized(void)
-{
-	return battery_hw_present() == batt_pres_prev;
-}
diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c
deleted file mode 100644
index 92fdc66806..0000000000
--- a/board/reef_it8320/board.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* reef_it8320 board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-
-#include "gpio_list.h"
-
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"CHARGER",     3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1 */
-	{"AMBIENT",     3000, 1024, 0, CHIP_ADC_CH2}, /* GPI2 */
-	{"BRD_ID",      3000, 1024, 0, CHIP_ADC_CH3}, /* GPI3 */
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct i2c_port_t i2c_ports[]  = {
-	{"mux",       IT83XX_I2C_CH_C, 400,
-		GPIO_EC_I2C_C_SCL, GPIO_EC_I2C_C_SDA},
-	{"batt",      IT83XX_I2C_CH_E, 100,
-		GPIO_EC_I2C_E_SCL, GPIO_EC_I2C_E_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
-};
-
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	int cc1_enabled = 0, cc2_enabled = 0;
-
-	if (cc_pin != USBPD_CC_PIN_1)
-		cc2_enabled = enabled;
-	else
-		cc1_enabled = enabled;
-
-	if (port) {
-		gpio_set_level(GPIO_USB_C1_CC2_VCONN_EN, cc2_enabled);
-		gpio_set_level(GPIO_USB_C1_CC1_VCONN_EN, cc1_enabled);
-	} else {
-		gpio_set_level(GPIO_USB_C0_CC2_VCONN_EN, !cc2_enabled);
-		gpio_set_level(GPIO_USB_C0_CC1_VCONN_EN, !cc1_enabled);
-	}
-}
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me,
-					  mux_state_t mux_state)
-{
-	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
-	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-	enum gpio_signal gpio =
-		me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL
-			     : GPIO_USB_C0_HPD_1P8_ODL;
-
-	hpd_lvl = !hpd_lvl;
-
-	gpio_set_level(gpio, hpd_lvl);
-	if (hpd_irq) {
-		gpio_set_level(gpio, 1);
-		msleep(1);
-		gpio_set_level(gpio, hpd_lvl);
-	}
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
-	},
-};
-
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-};
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BD9995X_ADDR_FLAGS,
-		.drv = &bd9995x_drv,
-	},
-};
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && gpio_get_level(GPIO_PMIC_EN))
-		return;
-
-	/* Enable PP5000 before PP3300 due to NFC: chrome-os-partner:50807 */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-	while (!gpio_get_level(GPIO_PP5000_PG))
-		;
-
-	/*
-	 * To prevent SLP glitches, PMIC_EN (V5A_EN) should be enabled
-	 * at the same time as PP3300 (chrome-os-partner:51323).
-	 */
-	/* Enable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 1);
-	while (!gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/* Enable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 1);
-}
-
-static void board_set_tablet_mode(void)
-{
-	/*
-	 * Always report device isn't in tablet mode because
-	 * our id is clamshell and no TABLET_MODE_L pin
-	 */
-	tablet_set_mode(0, TABLET_TRIGGER_LID);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	board_set_tablet_mode();
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C + 1);
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port != 0 && port != 1)
-		panic("Invalid charge port\n");
-
-	return bd9995x_is_vbus_provided(port);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	enum bd9995x_charge_port bd9995x_port = 0;
-	int bd9995x_port_select = 1;
-
-	switch (charge_port) {
-	case 0:
-	case 1:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-
-		bd9995x_port = charge_port;
-		break;
-	case CHARGE_PORT_NONE:
-		bd9995x_port_select = 0;
-		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
-
-		/*
-		 * To avoid inrush current from the external charger, enable
-		 * discharge on AC till the new charger is detected and
-		 * charge detect delay has passed.
-		 */
-		if (charge_get_percent() > 2)
-			charger_discharge_on_ac(1);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-
-	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Enable charging trigger by BC1.2 detection */
-	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
-			   supplier == CHARGE_SUPPLIER_BC12_DCP ||
-			   supplier == CHARGE_SUPPLIER_BC12_SDP ||
-			   supplier == CHARGE_SUPPLIER_OTHER);
-
-	if (bd9995x_bc12_enable_charging(port, bc12_enable))
-		return;
-
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < BD9995X_BC12_MIN_VOLTAGE;
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	/* Enable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-
-	/* Enable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-
-	/* Disable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1);
-
-	/* FIXME(dhendrix): Drive USB_PD_RST_ODL low to prevent
-	 * leakage? (see comment in schematic)
-	 */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* FIXME(dhendrix): Add CHIPSET_RESUME and CHIPSET_SUSPEND
- * hooks to enable/disable sensors?
- */
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * FIXME(dhendrix): Weak symbol hack until we can get a better solution for
- * both Amenia and Reef.
- */
-void chipset_do_shutdown(void)
-{
-	/* Disable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 0);
-
-	/*Disable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 0);
-	while (gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/*Disable 5V rail */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	while (gpio_get_level(GPIO_PP5000_PG))
-		;
-}
-
-void board_hibernate_late(void)
-{
-	int i;
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
-
-		/*
-		 * BD99956 handles charge input automatically. We'll disable
-		 * charge output in hibernate. Charger will assert ACOK_OD
-		 * when VBUS or VCC are plugged in.
-		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-	};
-
-	/* Change GPIOs' state in hibernate for better power consumption */
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-
-	/* Enable both the VBUS & VCC ports before entering PG3 */
-	bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
-
-	/* Turn BGATE OFF for saving the power */
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_MAX);
-}
-
-struct {
-	enum reef_it8320_board_version version;
-	int thresh_mv;
-} const reef_it8320_board_versions[] = {
-	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
-	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
-	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
-	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
-	{ BOARD_VERSION_6, 2020 * 1.03 }, /* 73.2 Kohm */
-	{ BOARD_VERSION_7, 2352 * 1.03 }, /* 115 Kohm */
-	{ BOARD_VERSION_8, 2802 * 1.03 }, /* 261 Kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(reef_it8320_board_versions) == BOARD_VERSION_COUNT);
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv, i;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	/* FIXME(dhendrix): enable ADC */
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_ODR_HIGH);
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 0);
-	/* Wait to allow cap charge */
-	msleep(1);
-	mv = adc_read_channel(ADC_BOARD_ID);
-	/* FIXME(dhendrix): disable ADC */
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 1);
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_INPUT);
-
-	if (mv == ADC_READ_ERROR) {
-		version = BOARD_VERSION_UNKNOWN;
-		return version;
-	}
-
-	for (i = 0; i < BOARD_VERSION_COUNT; i++) {
-		if (mv < reef_it8320_board_versions[i].thresh_mv) {
-			version = reef_it8320_board_versions[i].version;
-			break;
-		}
-	}
-
-	CPRINTS("Board version: %d", version);
-	return version;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h
deleted file mode 100644
index 510aff4792..0000000000
--- a/board/reef_it8320/board.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* reef_it8320 board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Enable PD in RO image for TCPMv2, otherwise there is only Type-c functions.
- * NOTE: This configuration is only for development board and will never be
- *       released on a chrome os device.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console commands  */
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-#define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
-
-#define CONFIG_CHARGER_PSYS_READ
-#define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BD9995X
-#define CONFIG_CHARGER_BD9995X_CHGEN
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_USB_CHARGER
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-#define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
-#define GPIO_USB_CTL1 GPIO_EN_PP5000
-
-/* USB PD config */
-#define CONFIG_USB_MUX_PI3USB30532
-#define CONFIG_USB_MUX_PS8740
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_CHIPSET_APOLLOLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_IT83XX_VCC_3P3V
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_TABLET_MODE
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-#define CONFIG_DPTF
-#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
-#define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-#undef CONFIG_KEYBOARD_VIVALDI
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-#undef CONFIG_UART_RX_BUF_SIZE
-#define CONFIG_UART_RX_BUF_SIZE 512
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* I2C ports */
-#define I2C_PORT_USB_MUX		IT83XX_I2C_CH_C
-#define I2C_PORT_BATTERY		IT83XX_I2C_CH_E
-#define I2C_PORT_CHARGER		IT83XX_I2C_CH_E
-
-/* ADC signal */
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC CH1 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC CH2 */
-	ADC_BOARD_ID,			/* ADC CH3 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY = 0,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum reef_it8320_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_1,
-	BOARD_VERSION_2,
-	BOARD_VERSION_3,
-	BOARD_VERSION_4,
-	BOARD_VERSION_5,
-	BOARD_VERSION_6,
-	BOARD_VERSION_7,
-	BOARD_VERSION_8,
-	BOARD_VERSION_COUNT,
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/* FIXME(dhendrix): verify all of the below PD_* numbers */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/reef_it8320/build.mk b/board/reef_it8320/build.mk
deleted file mode 100644
index e5c12f9090..0000000000
--- a/board/reef_it8320/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-# the IC is ITE IT8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/reef_it8320/ec.tasklist b/board/reef_it8320/ec.tasklist
deleted file mode 100644
index fdaf792a17..0000000000
--- a/board/reef_it8320/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, TRENTA_TASK_STACK_SIZE)
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc
deleted file mode 100644
index 9882065d50..0000000000
--- a/board/reef_it8320/gpio.inc
+++ /dev/null
@@ -1,124 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-GPIO_INT(CHARGER_INT_L,		PIN(A, 6), GPIO_INT_FALLING, bd9995x_vbus_interrupt)	/* CHARGER_EC_INT_ODL from BD99956 */
-GPIO_INT(AC_PRESENT,		PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)		/* ACOK_OD from BD99956 */
-#ifdef CONFIG_LOW_POWER_IDLE
-GPIO_INT(UART1_RX,		PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART_SERVO_TX_EC_RX */
-#endif
-GPIO_INT(EC_VOLUP_BTN_ODL,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)	/* EC_VOLUP_BTN_ODL */
-GPIO_INT(EC_VOLDN_BTN_ODL,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)	/* EC_VOLDN_BTN_ODL */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,		PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt)				/* SLP_S0_L */
-#endif
-GPIO_INT(SUSPWRDNACK,		PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRNACK */
-GPIO_INT(LID_OPEN,		PIN(E, 2), GPIO_INT_BOTH, lid_interrupt)		/* LID_OPEN */
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(PCH_PLTRST_L,   	PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,  lpcrst_interrupt)	/* PLT_RST_L */
-#endif
-GPIO_INT(POWER_BUTTON_L,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(ALL_SYS_PGOOD,		PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-GPIO_INT(RSMRST_L_PGOOD,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(WP_L,			PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt)	/* EC_WP_ODL_R */
-
-GPIO(EN_USB_C0_3A,		PIN(A, 0), GPIO_ODR_LOW)			/* 1.5/3.0 C0 current limit selection */
-GPIO(EN_USB_C1_3A,		PIN(A, 1), GPIO_ODR_LOW)			/* 1.5/3.0 C1 current limit selection */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(A, 2), GPIO_ODR_HIGH)			/* EN_PP3300_TRACKPAD_ODL */
-GPIO(EC_HAVEN_RESET_ODL,	PIN(A, 3), GPIO_ODR_HIGH)			/* EC_HAVEN_RST_ODL */
-/* Pin A.4 A.5 (I2C) for iteflash (servo board) */
-GPIO(WIRELESS_GPIO_WLAN_POWER,	PIN(B, 2), GPIO_ODR_HIGH)			/* EN_PP3300_WLAN_ODL */
-/* I2C GPIOs will be set to ALT function later. */
-GPIO(EC_I2C_A_SCL,		PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_GYRO_SCL */
-GPIO(EC_I2C_A_SDA,		PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_GYRO_SDA */
-GPIO(ENABLE_BACKLIGHT,		PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(SYS_RESET_L,		PIN(B, 6), GPIO_ODR_HIGH)			/* SYS_RST_ODL */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,		PIN(B, 7), GPIO_INPUT)				/* SLP_S0_L */
-#endif
-GPIO(EC_BATT_PRES_L,		PIN(C, 0), GPIO_INPUT)				/* EC_BATT_PRES_L */
-GPIO(EC_I2C_B_SCL,		PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_U_SCL */
-GPIO(EC_I2C_B_SDA,		PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_U_SDA */
-/*
- * BRD_ID1 is a an ADC pin which will be used to measure multiple values.
- * Assert EC_BRD_ID_EN_ODL and then read BRD_ID1.
- */
-GPIO(EC_BRD_ID_EN_ODL,		PIN(C, 3), GPIO_INPUT)				/* EC_BRD_ID_EN_ODL */
-GPIO(CCD_MODE_ODL,		PIN(C, 4), GPIO_INPUT)				/* CCD_MODE_ODL */
-GPIO(ENTERING_RW,		PIN(C, 5), GPIO_OUT_LOW)			/* EC_ENTERING_RW */
-GPIO(PCH_RSMRST_L,		PIN(C, 6), GPIO_OUT_LOW)			/* PCH_RSMRST_L */
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,		PIN(C, 7), GPIO_INPUT | GPIO_SEL_1P8V)		/* PCH_PROCHOT_ODL */
-GPIO(PCH_PWRBTN_L,		PIN(D, 0), GPIO_ODR_HIGH)			/* EC_PCH_PWR_BTN_ODL */
-GPIO(PCH_WAKE_L,		PIN(D, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_PCH_WAKE_ODL */
-GPIO(DP_MUX_EN,			PIN(D, 2), GPIO_OUT_HIGH)			/* DB_MUX_EN */
-GPIO(PCH_SCI_L,			PIN(D, 3), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SCI_ODL */
-GPIO(PCH_SMI_L,			PIN(D, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
-GPIO(PMIC_EN,			PIN(D, 7), GPIO_OUT_LOW)			/* PMIC_A_RAILS_EN */
-GPIO(EC_I2C_E_SCL,		PIN(E, 0), GPIO_INPUT)				/* EC_I2C_POWER_3V3_SCL */
-/* FIXME: this pin doesn't support 1.8v */
-#if 0
-GPIO(KBD_IRQ_L, 		PIN(E, 5), GPIO_ODR_HIGH)			/* EC_PCH_KB_INT_ODL */
-#endif
-GPIO(CHARGER_RST_ODL,		PIN(E, 6), GPIO_ODR_HIGH)			/* CHARGER_RST_ODL */
-GPIO(EC_I2C_E_SDA,		PIN(E, 7), GPIO_INPUT)				/* EC_I2C_POWER_3V3_SDA */
-/* F.5 F.4 are cc pins of PD0 */
-GPIO(EC_I2C_C_SCL,		PIN(F, 6), GPIO_INPUT)				/* EC_I2C_USBC_MUX_SCL */
-GPIO(EC_I2C_C_SDA,		PIN(F, 7), GPIO_INPUT)				/* EC_I2C_USBC_MUX_SDA */
-GPIO(LPC_CLKRUN_L,		PIN(H, 0), GPIO_OUT_LOW)			/* LPC_CLKRUN_L */
-/* H.1 H.2 are cc pins of PD1 */
-GPIO(TRACKPAD_INT_GATE, 	PIN(H, 3), GPIO_OUT_LOW)
-GPIO(USB2_OTG_VBUSSENSE,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD_1P8_ODL,	PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* USB_C0_HPD_1V8_ODL */
-GPIO(USB_C1_HPD_1P8_ODL,	PIN(J, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* USB_C1_HPD_1V8_ODL */
-GPIO(LID_ACCEL_INT_L,		PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* LID_ACCEL_INT_L */
-/* NOTE: Active low */
-GPIO(USB_C0_CC1_VCONN_EN,	PIN(J, 4), GPIO_ODR_HIGH)			/* USB_C0_CC1_VCONN_EN_ODL */
-GPIO(USB_C0_CC2_VCONN_EN,	PIN(J, 5), GPIO_ODR_HIGH)			/* USB_C0_CC2_VCONN_EN_ODL */
-
-GPIO(EN_PP3300,			PIN(K, 0), GPIO_OUT_LOW)			/* EN_PP3300 */
-GPIO(PP3300_PG,			PIN(K, 1), GPIO_INPUT)				/* PP3300_PG_OD */
-GPIO(EN_PP5000,			PIN(K, 2), GPIO_OUT_LOW)			/* EN_PP5000 */
-GPIO(PP5000_PG,			PIN(K, 3), GPIO_INPUT)				/* PP5000_PG_OD */
-GPIO(PCH_SYS_PWROK,		PIN(K, 4), GPIO_OUT_LOW)			/* EC_PCH_PWROK */
-/* NOTE: These two pins are reserved on this test board. */
-GPIO(USB_C1_CC1_VCONN_EN,	PIN(K, 5), GPIO_INPUT | GPIO_PULL_DOWN)		/* USB_C1_CC1_VCONN_EN */
-GPIO(USB_C1_CC2_VCONN_EN,	PIN(K, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* USB_C1_CC2_VCONN_EN */
-/* EC_PCH_RTCRST is a sledgehammer for resetting SoC state and should rarely
- * be used. Set as input for now, we'll set it as an output when we want to use
- * it. Has external pull-down resistor. */
-GPIO(EC_PCH_RTCRST,		PIN(K, 7), GPIO_INPUT)				/* EC_PCH_RTCRST */
-GPIO(USB_A_CHARGE_EN_L, 	PIN(L, 0), GPIO_OUT_LOW)			/* USB_A_CHARGE_EN_L */
-GPIO(USB1_ENABLE,		PIN(L, 1), GPIO_OUT_LOW)			/* EN_USB_A_5V */
-/*
- * Configure as input to enable @ 1.5A, output-low to turn off, or output-high
- * to enable @ 3A.
- */
-GPIO(USB_C0_5V_EN,		PIN(L, 2), GPIO_OUT_LOW)		        /* EN_USB_C0_5V_OUT, Enable C0 */
-GPIO(USB_C1_5V_EN,		PIN(L, 3), GPIO_OUT_LOW)		        /* EN_USB_C1_5V_OUT, Enable C1 */
-GPIO(BAT_LED_BLUE,		PIN(L, 4), GPIO_OUT_HIGH)			/* BLUE_PWR_LED */
-GPIO(BAT_LED_AMBER,		PIN(L, 5), GPIO_OUT_HIGH)			/* ORANGE_CHG_LED */
-GPIO(USB_C0_DISCHARGE,		PIN(L, 6), GPIO_OUT_LOW)			/* USB_C0_DISCHARGE */
-GPIO(USB_C1_DISCHARGE, 		PIN(L, 7), GPIO_OUT_LOW)			/* USB_C1_DISCHARGE */
-
-/*
- * Alternate function pins
- */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0)            /* UART1 */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0)             /* I2C A SCL/SDA */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0)             /* I2C B SCL/SDA */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0)             /* I2C E SCL/SDA */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0)             /* I2C C SCL/SDA */
-ALTERNATE(PIN_MASK(I, 0x0E), 1, MODULE_ADC, 0)             /* ADC CH1-CH3 */
diff --git a/board/reef_it8320/led.c b/board/reef_it8320/led.c
deleted file mode 100644
index a1ea5964a8..0000000000
--- a/board/reef_it8320/led.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Reef
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
-#define LOW_BATTERY_PERCENTAGE 10
-
-#define LED_TOTAL_4SECS_TICKS 4
-#define LED_TOTAL_2SECS_TICKS 2
-#define LED_ON_1SEC_TICKS 1
-#define LED_ON_2SECS_TICKS 2
-
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_BLUE,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(led_id, LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int suspend_ticks;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_BLUE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON)) {
-			led_set_color_battery(LED_BLUE);
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Blink once every four seconds. */
-			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
-		} else {
-			led_set_color_battery(LED_OFF);
-		}
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_BLUE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-	battery_ticks++;
-	suspend_ticks++;
-}
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	/*
-	 * Reference board only has one LED, so overload it to act as both
-	 * power LED and battery LED.
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/reef_it8320/usb_pd_policy.c b/board/reef_it8320/usb_pd_policy.c
deleted file mode 100644
index 7fec6bc975..0000000000
--- a/board/reef_it8320/usb_pd_policy.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
-	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
-
-	gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
-	gpio_set_level(gpio, vbus_en[port]);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Ensure we're not charging from this port */
-	bd9995x_select_input_port(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
diff --git a/board/reef_it8320/vif_override.xml b/board/reef_it8320/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/reef_it8320/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/reef_mchp/battery.c b/board/reef_mchp/battery.c
deleted file mode 100644
index c557533c9d..0000000000
--- a/board/reef_mchp/battery.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger_profile_override.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum battery_type {
-	BATTERY_SONY_CORP,
-	BATTERY_PANASONIC,
-	BATTERY_SMP_COS4870,
-	BATTERY_SMP_C22N1626,
-	BATTERY_CPT_C22N1626,
-	BATTERY_TYPE_COUNT,
-};
-
-enum fast_chg_voltage_ranges {
-	VOLTAGE_RANGE_0,
-	VOLTAGE_RANGE_1,
-	VOLTAGE_RANGE_2,
-};
-
-enum temp_range {
-	TEMP_RANGE_0,
-	TEMP_RANGE_1,
-	TEMP_RANGE_2,
-	TEMP_RANGE_3,
-	TEMP_RANGE_4,
-};
-
-struct ship_mode_info {
-	const int ship_mode_reg;
-	const int ship_mode_data;
-	int (*batt_init)(void);
-};
-
-struct board_batt_params {
-	const char *manuf_name;
-	const struct ship_mode_info *ship_mode_inf;
-	const struct battery_info *batt_info;
-	const struct fast_charge_params *fast_chg_params;
-};
-
-#define DEFAULT_BATTERY_TYPE BATTERY_SONY_CORP
-#define SONY_DISCHARGE_DISABLE_FET_BIT (0x01 << 13)
-#define PANASONIC_DISCHARGE_ENABLE_FET_BIT (0x01 << 14)
-#define C22N1626_DISCHARGE_ENABLE_FET_BIT (0x01 << 0)
-
-/* keep track of previous charge profile info */
-static const struct fast_charge_profile *prev_chg_profile_info;
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-static enum battery_type board_battery_type = BATTERY_TYPE_COUNT;
-
-static const struct fast_charge_profile fast_charge_smp_cos4870_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <=15C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(15),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 944,
-			[VOLTAGE_RANGE_1] = 472,
-		},
-	},
-
-	/* 15C > && <=20C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(20),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1416,
-			[VOLTAGE_RANGE_1] = 1416,
-		},
-	},
-
-	/* 20C > && <=45C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3300,
-			[VOLTAGE_RANGE_1] = 3300,
-		},
-	},
-
-	/* > 45C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_cos4870 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_cos4870_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_cos4870_info[0],
-};
-
-const struct battery_info batt_info_smp_cos4870 = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 46,
-	.charging_min_c = 0,
-	.charging_max_c = 45,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static const struct fast_charge_profile fast_charge_sonycorp_info[] = {
-	/* < 10C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(9),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1200,
-			[VOLTAGE_RANGE_1] = 1200,
-		},
-	},
-
-	/* >= 10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2250,
-			[VOLTAGE_RANGE_1] = 2250,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_sonycorp = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_sonycorp_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_sonycorp_info[0],
-};
-
-const struct battery_info batt_info_sonycorp = {
-	.voltage_max = TARGET_WITH_MARGIN(8700, 5),
-	.voltage_normal = 7600,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_panasonic_info[] = {
-	/* < 0C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(-1),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-
-	/* 0C >= && <= 60C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 3072,
-			[VOLTAGE_RANGE_1] = 3072,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_panasonic = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_panasonic_info),
-	.default_temp_range_profile = TEMP_RANGE_1,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8000,
-		[VOLTAGE_RANGE_1] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_panasonic_info[0],
-};
-
-const struct battery_info batt_info_panasoic = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 50,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = -20,
-	.discharging_max_c = 75,
-};
-
-static const struct fast_charge_profile fast_charge_smp_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4672,
-			[VOLTAGE_RANGE_1] = 4672,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* > 60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_smp_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_smp_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_smp_c22n1626_info[0],
-};
-
-static const struct fast_charge_profile fast_charge_cpt_c22n1626_info[] = {
-	/* < 1C */
-	[TEMP_RANGE_0] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(0),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >=1C && <=10C */
-	[TEMP_RANGE_1] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(10),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 1752,
-			[VOLTAGE_RANGE_1] = 1752,
-			[VOLTAGE_RANGE_2] = 1752,
-		},
-	},
-
-	/* 10C > && <=45C */
-	[TEMP_RANGE_2] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(45),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 4600,
-			[VOLTAGE_RANGE_1] = 4600,
-			[VOLTAGE_RANGE_2] = 2920,
-		},
-	},
-
-	/* 45C > && <=60C */
-	[TEMP_RANGE_3] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(60),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 2920,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-
-	/* >60C */
-	[TEMP_RANGE_4] = {
-		.temp_c = TEMPC_TENTHS_OF_DEG(CHARGER_PROF_TEMP_C_LAST_RANGE),
-		.current_mA = {
-			[VOLTAGE_RANGE_0] = 0,
-			[VOLTAGE_RANGE_1] = 0,
-			[VOLTAGE_RANGE_2] = 0,
-		},
-	},
-};
-
-static const struct fast_charge_params fast_chg_params_cpt_c22n1626 = {
-	.total_temp_ranges = ARRAY_SIZE(fast_charge_cpt_c22n1626_info),
-	.default_temp_range_profile = TEMP_RANGE_2,
-	.voltage_mV = {
-		[VOLTAGE_RANGE_0] = 8200,
-		[VOLTAGE_RANGE_1] = 8500,
-		[VOLTAGE_RANGE_2] = CHARGER_PROF_VOLTAGE_MV_LAST_RANGE,
-	},
-	.chg_profile_info = &fast_charge_cpt_c22n1626_info[0],
-};
-
-const struct battery_info batt_info_c22n1626 = {
-	.voltage_max = TARGET_WITH_MARGIN(8800, 5),
-	.voltage_normal = 7700,
-
-	/*
-	 * Actual value 6000mV, added 100mV for charger accuracy so that
-	 * unwanted low VSYS_Prochot# assertion can be avoided.
-	 */
-	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
-	.start_charging_min_c = 0,
-	.start_charging_max_c = 45,
-	.charging_min_c = 0,
-	.charging_max_c = 60,
-	.discharging_min_c = 0,
-	.discharging_max_c = 60,
-};
-
-static int batt_smp_cos4870_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
-}
-
-static int batt_sony_corp_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [13] : Discharging Disabled
-	 *      : 0b - Allowed to Discharge
-	 *      : 1b - Not Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
-}
-
-static int batt_panasonic_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_MANUFACTURER_ACCESS:
-	 * [14] : Discharging Disabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static int batt_c22n1626_init(void)
-{
-	int batt_status;
-
-	/*
-	 * SB_PACK_STATUS:
-	 * [0] : Discharging Enabled
-	 *      : 0b - Not Allowed to Discharge
-	 *      : 1b - Allowed to Discharge
-	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
-}
-
-static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_smp_cos4870_init,
-};
-
-static const struct ship_mode_info ship_mode_info_sonycorp = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_sony_corp_init,
-};
-
-static const struct ship_mode_info ship_mode_info_panasonic = {
-	.ship_mode_reg = 0x3A,
-	.ship_mode_data = 0xC574,
-	.batt_init = batt_panasonic_init,
-};
-
-static const struct ship_mode_info ship_mode_info_c22n1626 = {
-	.ship_mode_reg = 0x00,
-	.ship_mode_data = 0x0010,
-	.batt_init = batt_c22n1626_init,
-};
-
-static const struct board_batt_params info[] = {
-	/* BQ40Z555 SONY CORP BATTERY battery specific configurations */
-	[BATTERY_SONY_CORP] = {
-		.manuf_name = "SONYCorp",
-		.ship_mode_inf = &ship_mode_info_sonycorp,
-		.fast_chg_params = &fast_chg_params_sonycorp,
-		.batt_info = &batt_info_sonycorp,
-	},
-
-	/* RAJ240045 Panasoic battery specific configurations */
-	[BATTERY_PANASONIC] = {
-		.manuf_name = "PANASONIC",
-		.ship_mode_inf = &ship_mode_info_panasonic,
-		.fast_chg_params = &fast_chg_params_panasonic,
-		.batt_info = &batt_info_panasoic,
-	},
-
-	/* BQ40Z55 SMP COS4870 BATTERY battery specific configurations */
-	[BATTERY_SMP_COS4870] = {
-		.manuf_name = "SMP-COS4870",
-		.ship_mode_inf = &ship_mode_info_smp_cos4870,
-		.fast_chg_params = &fast_chg_params_smp_cos4870,
-		.batt_info = &batt_info_smp_cos4870,
-	},
-
-	/* BQ40Z55 SMP C22N1626 BATTERY battery specific configurations */
-	[BATTERY_SMP_C22N1626] = {
-		.manuf_name = "AS1FNZD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_smp_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-
-	/* BQ40Z55 CPT C22N1626 BATTERY battery specific configurations */
-	[BATTERY_CPT_C22N1626] = {
-		.manuf_name = "AS1FOAD3KD",
-		.ship_mode_inf = &ship_mode_info_c22n1626,
-		.fast_chg_params = &fast_chg_params_cpt_c22n1626,
-		.batt_info = &batt_info_c22n1626,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
-
-static inline const struct board_batt_params *board_get_batt_params(void)
-{
-	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
-}
-
-enum battery_present battery_hw_present(void)
-{
-	int bp;
-
-	/* The GPIO is low when the battery is physically present */
-	bp = gpio_get_level(GPIO_EC_BATT_PRES_L);
-	return bp ? BP_NO : BP_YES;
-}
-
-/* Get type of the battery connected on the board */
-static int board_get_battery_type(void)
-{
-	const struct fast_charge_params *chg_params;
-	char name[32];
-	int i;
-
-	if (!battery_manufacturer_name(name, sizeof(name))) {
-		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-			if (!strcasecmp(name, info[i].manuf_name)) {
-				board_battery_type = i;
-				break;
-			}
-		}
-	}
-
-	/* Initialize fast charging parameters */
-	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-			chg_params->default_temp_range_profile];
-
-	return board_battery_type;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * Very first battery info is called by the charger driver to initialize
- * the charger parameters hence initialize the battery type for the board
- * as soon as the I2C is initialized.
- */
-static void board_init_battery_type(void)
-{
-	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s",
-			info[board_battery_type].manuf_name);
-	else
-		CPUTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-const struct battery_info *battery_get_info(void)
-{
-	return board_get_batt_params()->batt_info;
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
-
-	/* Ship mode command must be sent twice to take effect */
-	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
-
-	return rv;
-}
-
-static int charger_should_discharge_on_ac(struct charge_state_data *curr)
-{
-	/* can not discharge on AC without battery */
-	if (curr->batt.is_present != BP_YES)
-		return 0;
-
-	/* Do not discharge on AC if the battery is still waking up */
-	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			!(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 0;
-
-	/*
-	 * In light load (<450mA being withdrawn from VSYS) the DCDC of the
-	 * charger operates intermittently i.e. DCDC switches continuously
-	 * and then stops to regulate the output voltage and current, and
-	 * sometimes to prevent reverse current from flowing to the input.
-	 * This causes a slight voltage ripple on VSYS that falls in the
-	 * audible noise frequency (single digit kHz range). This small
-	 * ripple generates audible noise in the output ceramic capacitors
-	 * (caps on VSYS and any input of DCDC under VSYS).
-	 *
-	 * To overcome this issue enable the battery learning operation
-	 * and suspend USB charging and DC/DC converter.
-	 */
-	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			(curr->batt.status & STATUS_FULLY_CHARGED))
-		return 1;
-
-	/*
-	 * To avoid inrush current from the external charger, enable
-	 * discharge on AC till the new charger is detected and charge
-	 * detect delay has passed.
-	 */
-	if (!chg_ramp_is_detected() && curr->batt.state_of_charge > 2)
-		return 1;
-
-	return 0;
-}
-
-/*
- * This can override the smart battery's charging profile. To make a change,
- * modify one or more of requested_voltage, requested_current, or state.
- * Leave everything else unchanged.
- *
- * Return the next poll period in usec, or zero to use the default (which is
- * state dependent).
- */
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int disch_on_ac = charger_should_discharge_on_ac(curr);
-
-	charger_discharge_on_ac(disch_on_ac);
-
-	if (disch_on_ac) {
-		curr->state = ST_DISCHARGE;
-		return 0;
-	}
-
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
-}
-
-/*
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * Make sure battery status is implemented, I2C transactions are
-	 * success & the battery status is Initialized to find out if it
-	 * is a working battery and it is not in the cut-off mode.
-	 *
-	 * If battery I2C fails but VBATT is high, battery is booting from
-	 * cut-off mode.
-	 *
-	 * FETs are turned off after Power Shutdown time.
-	 * The device will wake up when a voltage is applied to PACK.
-	 * Battery status will be inactive until it is initialized.
-	 */
-	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
-		/* Re-init board battery if battery presence status changes */
-		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
-			if (bd9995x_get_battery_voltage() >=
-			    board_get_batt_params()->batt_info->voltage_min)
-				batt_pres = BP_NO;
-		} else if (!board_get_batt_params()->ship_mode_inf->batt_init())
-			batt_pres = BP_NO;
-	}
-
-	batt_pres_prev = batt_pres;
-
-	return batt_pres;
-}
-
-int board_battery_initialized(void)
-{
-	return (battery_hw_present() == batt_pres_prev);
-}
diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c
deleted file mode 100644
index b934264510..0000000000
--- a/board/reef_mchp/board.c
+++ /dev/null
@@ -1,1172 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Reef board-specific configuration */
-
-#include "adc.h"
-#include "als.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/als_opt3001.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/baro_bmp280.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_lid.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "lpc_chip.h"
-#include "spi.h"
-#include "spi_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "tfdp_chip.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-
-#define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
-
-#ifdef CONFIG_BOARD_PRE_INIT
-/*
- * reefmchp - requires changing
- * VTR1 pin domain = 3.3V
- * VTR2 pin domain = 1.8V
- * VTR3 pin domain = 3.3V
- */
-void board_config_pre_init(void)
-{
-	MCHP_EC_GPIO_BANK_PWR = MCHP_EC_GPIO_BANK_PWR_VTR2_18;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/* DEBUG - GPIO_0060 becomes 48MHZ_OUT
-	 * MEC1701 interposer J47-7
-	 */
-	gpio_config_module(MODULE_CHIPSET, 1);
-#endif
-}
-#endif
-
-/*
- * NOTES: The PD GPIO's are armed for falling edge.
- * There is a potential race condition in this routine.
- * ISR calls this routine and it reads state of GPIO pin.
- * If GPIO is still asserted low, this routine will do nothing.
- * If this routine samples GPIO after it returns high then it
- * will wake the PDCMD task.
- */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static void anx74xx_cable_det_handler(void)
-{
-	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
-	int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L);
-
-	/*
-	 * A cable_det low->high transition was detected. If following the
-	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
-	 * currently in standby mode and needs to be woken up. Set the
-	 * TCPC_RESET event which will bring the ANX3429 out of standby
-	 * mode. Setting this event is gated on reset_n being low because the
-	 * ANX3429 will always set cable_det when transitioning to normal mode
-	 * and if in normal mode, then there is no need to trigger a tcpc reset.
-	 */
-	if (cable_det && !reset_n)
-		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
-}
-DECLARE_DEFERRED(anx74xx_cable_det_handler);
-/* from firmware-reef-9042.B */
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, anx74xx_cable_det_handler, HOOK_PRIO_LAST);
-
-void anx74xx_cable_det_interrupt(enum gpio_signal signal)
-{
-	/* debounce for 2 msec */
-	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
-}
-#endif
-
-/*
- * enable_input_devices() is called by the tablet_mode ISR, but changes the
- * state of GPIOs, so its definition must reside after including gpio_list.
- * Use DECLARE_DEFERRED to generate enable_input_devices_data.
- */
-static void enable_input_devices(void);
-DECLARE_DEFERRED(enable_input_devices);
-
-#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
-void tablet_mode_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&enable_input_devices_data, LID_DEBOUNCE_US);
-}
-
-#include "gpio_list.h"
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
-#if defined(CONFIG_SPI_ACCEL_PORT)
-	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
-#endif
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/* ADC channels */
-/* chip/mchp defined adc_t
- * name, factor_mul, factor_div, shift, channel
- * Signals routed through interposer to MEC17xx ADC channels.
- */
-const struct adc_t adc_channels[] = {
-	/* Vref = 3.000V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", 3000, 1024, 0, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", 3000, 1024, 0, 1
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", 3000, 1024, 0, 2
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-#ifdef CONFIG_PWM
-const struct pwm_t pwm_channels[] = {
-	/* channel, flags */
-	[PWM_CH_LED_GREEN] = { 4, PWM_CONFIG_DSLEEP },
-	[PWM_CH_LED_RED] =   { 5, PWM_CONFIG_DSLEEP },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-#endif /* #ifdef CONFIG_PWM */
-
-/*
- * Using Ports 3, 6, 7 from board.h
- * Using Ports 0, 2 from board.c
- * Due to added RC of interposer board temporarily reduce
- * 400 to 100 kHz.
- */
-const struct i2c_port_t i2c_ports[]  = {
-	{"tcpc0",     MCHP_I2C_PORT0, 400,
-		GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",     MCHP_I2C_PORT2, 400,
-		GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"accelgyro", I2C_PORT_GYRO, 400,
-		GPIO_EC_I2C_GYRO_SCL,      GPIO_EC_I2C_GYRO_SDA},
-	{"sensors",   MCHP_I2C_PORT7, 400,
-		GPIO_EC_I2C_SENSOR_SCL,    GPIO_EC_I2C_SENSOR_SDA},
-	{"batt",      MCHP_I2C_PORT3, 100,
-		GPIO_EC_I2C_POWER_SCL,     GPIO_EC_I2C_POWER_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*
- * Map ports to controller.
- * Ports may map to the same controller.
- * Both USB PD ports are mapped to CTRL0.
- */
-const uint16_t i2c_port_to_ctrl[I2C_PORT_COUNT] = {
-	(MCHP_I2C_CTRL0 << 8) + MCHP_I2C_PORT0,
-	(MCHP_I2C_CTRL0 << 8) + MCHP_I2C_PORT2,
-	(MCHP_I2C_CTRL1 << 8) + I2C_PORT_GYRO,
-	(MCHP_I2C_CTRL2 << 8) + MCHP_I2C_PORT3,
-	(MCHP_I2C_CTRL3 << 8) + MCHP_I2C_PORT7,
-};
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BD9995X_ADDR_FLAGS,
-		.drv = &bd9995x_drv,
-	},
-};
-
-/*
- * default to I2C0 because callers may not check
- * return value if we returned an error code.
- */
-int board_i2c_p2c(int port)
-{
-	int i;
-
-	for (i = 0; i < I2C_PORT_COUNT; i++)
-		if ((i2c_port_to_ctrl[i] & 0xFF) == port)
-			return (int)(i2c_port_to_ctrl[i] >> 8);
-
-	return -1;
-}
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST
-struct i2c_stress_test i2c_stress_tests[] = {
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = MCHP_I2C_PORT0,
-		.addr_flags = 0x28,
-		.i2c_test = &anx74xx_i2c_stress_test_dev,
-	},
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-	{
-		.port = MCHP_I2C_PORT2,
-		.addr_flags = 0x0B,
-		.i2c_test = &ps8xxx_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_GYRO,
-		.addr_flags = BMI160_ADDR0_FLAGS,
-		.i2c_test = &bmi160_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-	{
-		.port = I2C_PORT_BARO,
-		.addr_flags = BMP280_I2C_ADDRESS1_FLAGS,
-		.i2c_test = &bmp280_i2c_stress_test_dev,
-	},
-	{
-		.port = I2C_PORT_LID_ACCEL,
-		.addr_flags = KX022_ADDR1_FLAGS,
-		.i2c_test = &kionix_i2c_stress_test_dev,
-	},
-#endif
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ALS
-	{
-		.port = I2C_PORT_ALS,
-		.addr_flags = OPT3001_I2C_ADDR1_FLAGS,
-		.i2c_test = &opt3001_i2c_stress_test_dev,
-	},
-#endif
-/* MCHP_I2C_PORT3 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-	{
-		.i2c_test = &battery_i2c_stress_test_dev,
-	},
-#endif
-/* MCHP_I2C_PORT3 */
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-	{
-		.i2c_test = &bd9995x_i2c_stress_test_dev,
-	},
-#endif
-};
-const int i2c_test_dev_used = ARRAY_SIZE(i2c_stress_tests);
-#endif /* CONFIG_CMD_I2C_STRESS_TEST */
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = MCHP_I2C_PORT0,
-			.addr_flags = 0x28,
-		},
-		.drv = &anx74xx_tcpm_drv,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = MCHP_I2C_PORT2,
-			.addr_flags = 0x0B,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL))
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_AC_PRESENT,
-	GPIO_LID_OPEN,
-	GPIO_POWER_BUTTON_L,
-};
-
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/*
- * PS8751 TCPM DRP low power idle behavour is causing I2C errors.
- * Upon receiving DRP low power idle command, PS8751 holds SCL and
- * SDA low for ~480us. It simultaneously releases both pins which is
- * defined as a bus error condition by I2C spec. No ACK received.
- * TCPCI spec. states waking any TCPM requires sending any fake
- * I2C command which the TCPM will NACK. The I2C master MUST wait
- * a minimum of 5 ms after the NACK before sending another I2C
- * command. We observe the PD task and TCPCI state machines do not
- * follow the TCPCI spec. Sometimes this routine is called to wake
- * the PS8751 after it has been put into low power idle and sometimes
- * the PD/TCPCI state machine doesn't call this routine and tries
- * communicating with PS8751. This results in lots of I2C retries and
- * results taking up to 10ms before I2C communication with PS8751
- * is stable. Don't know how to fix this.
- */
-static int ps8751_tune_mux(const struct usb_mux *me)
-{
-	int rv;
-
-	/* 0x98 sets lower EQ of DP port (4.5db) */
-	rv = mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
-
-	/* TCPCI spec. delay msleep(6); */
-
-	return rv;
-}
-
-/*
- * USB_PD_PORT_ANX74XX and USB_PD_PORT_PS8751 are zero based indices into
- * tcpc_config array. The tcpc_config array contains the actual EC I2C
- * port, device address, and a function pointer into the driver code.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
-
-/* MCHP
- * New, not in firmware-reef-9042.B
- */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-};
-
-/**
- * Power on (or off) a single TCPC.
- * minimum on/off delays are included.
- *
- * @param port	Port number of TCPC.
- * @param mode	0: power off, 1: power on.
- */
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	if (port != USB_PD_PORT_ANX74XX)
-		return;
-
-	switch (mode) {
-	case ANX74XX_NORMAL_MODE:
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 1);
-		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-		break;
-	case ANX74XX_STANDBY_MODE:
-		gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
-		gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-	/* Assert reset to TCPC1 */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
-
-	/* Assert reset to TCPC0 (anx3429) */
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	/* TCPC1 (ps8751) requires 1ms reset down assertion */
-	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
-
-	/* Deassert reset to TCPC1 */
-	gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
-	/* Disable TCPC0 power */
-	gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
-
-	/*
-	 * anx3429 requires 10ms reset/power down assertion
-	 */
-	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
-	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
-}
-
-void board_tcpc_init(void)
-{
-	int reg;
-
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/*
-	 * TODO: Remove when Reef is updated with PS8751 A3.
-	 *
-	 * Force PS8751 A2 to wake from low power mode.
-	 * If PS8751 remains in low power mode after sysjump,
-	 * TCPM_INIT will fail due to not able to access PS8751.
-	 *
-	 * NOTE: PS8751 A3 will wake on any I2C access.
-	 */
-	reg = 0;
-	/* TODO MCHP:
-	 * PS8751 is at I2C address 0x16. Original reef using
-	 * address 0x10. Is this another attempt at waking PS8751
-	 * from DRP low power idle mode?
-	 */
-	i2c_read8(MCHP_I2C_PORT2, 0x08, 0xA0, &reg);
-
-	/* Enable TCPC0 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-	/* Enable TCPC1 interrupt */
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
-	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
-#endif
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
-
-/*
- * Data derived from Seinhart-Hart equation in a resistor divider circuit with
- * Vdd=3300mV, R = 13.7Kohm, and Murata NCP15WB-series thermistor (B = 4050,
- * T0 = 298.15, nominal resistance (R0) = 47Kohm).
- */
-#define CHARGER_THERMISTOR_SCALING_FACTOR 13
-static const struct thermistor_data_pair charger_thermistor_data[] = {
-	{ 3044 / CHARGER_THERMISTOR_SCALING_FACTOR, 0 },
-	{ 2890 / CHARGER_THERMISTOR_SCALING_FACTOR, 10 },
-	{ 2680 / CHARGER_THERMISTOR_SCALING_FACTOR, 20 },
-	{ 2418 / CHARGER_THERMISTOR_SCALING_FACTOR, 30 },
-	{ 2117 / CHARGER_THERMISTOR_SCALING_FACTOR, 40 },
-	{ 1800 / CHARGER_THERMISTOR_SCALING_FACTOR, 50 },
-	{ 1490 / CHARGER_THERMISTOR_SCALING_FACTOR, 60 },
-	{ 1208 / CHARGER_THERMISTOR_SCALING_FACTOR, 70 },
-	{ 966 / CHARGER_THERMISTOR_SCALING_FACTOR, 80 },
-	{ 860 / CHARGER_THERMISTOR_SCALING_FACTOR, 85 },
-	{ 766 / CHARGER_THERMISTOR_SCALING_FACTOR, 90 },
-	{ 679 / CHARGER_THERMISTOR_SCALING_FACTOR, 95 },
-	{ 603 / CHARGER_THERMISTOR_SCALING_FACTOR, 100 },
-};
-
-static const struct thermistor_info charger_thermistor_info = {
-	.scaling_factor = CHARGER_THERMISTOR_SCALING_FACTOR,
-	.num_pairs = ARRAY_SIZE(charger_thermistor_data),
-	.data = charger_thermistor_data,
-};
-
-int board_get_charger_temp(int idx, int *temp_ptr)
-{
-	int mv = adc_read_channel(MCHP_ADC_CH(0));
-
-	if (mv < 0)
-		return -1;
-
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&charger_thermistor_info);
-	*temp_ptr = C_TO_K(*temp_ptr);
-	return 0;
-}
-
-/*
- * Data derived from Seinhart-Hart equation in a resistor divider circuit with
- * Vdd=3300mV, R = 51.1Kohm, and Murata NCP15WB-series thermistor (B = 4050,
- * T0 = 298.15, nominal resistance (R0) = 47Kohm).
- */
-#define AMB_THERMISTOR_SCALING_FACTOR 11
-static const struct thermistor_data_pair amb_thermistor_data[] = {
-	{ 2512 / AMB_THERMISTOR_SCALING_FACTOR, 0 },
-	{ 2158 / AMB_THERMISTOR_SCALING_FACTOR, 10 },
-	{ 1772 / AMB_THERMISTOR_SCALING_FACTOR, 20 },
-	{ 1398 / AMB_THERMISTOR_SCALING_FACTOR, 30 },
-	{ 1070 / AMB_THERMISTOR_SCALING_FACTOR, 40 },
-	{ 803 / AMB_THERMISTOR_SCALING_FACTOR, 50 },
-	{ 597 / AMB_THERMISTOR_SCALING_FACTOR, 60 },
-	{ 443 / AMB_THERMISTOR_SCALING_FACTOR, 70 },
-	{ 329 / AMB_THERMISTOR_SCALING_FACTOR, 80 },
-	{ 285 / AMB_THERMISTOR_SCALING_FACTOR, 85 },
-	{ 247 / AMB_THERMISTOR_SCALING_FACTOR, 90 },
-	{ 214 / AMB_THERMISTOR_SCALING_FACTOR, 95 },
-	{ 187 / AMB_THERMISTOR_SCALING_FACTOR, 100 },
-};
-
-static const struct thermistor_info amb_thermistor_info = {
-	.scaling_factor = AMB_THERMISTOR_SCALING_FACTOR,
-	.num_pairs = ARRAY_SIZE(amb_thermistor_data),
-	.data = amb_thermistor_data,
-};
-
-int board_get_ambient_temp(int idx, int *temp_ptr)
-{
-	int mv = adc_read_channel(MCHP_ADC_CH(1));
-
-	if (mv < 0)
-		return -1;
-
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&amb_thermistor_info);
-	*temp_ptr = C_TO_K(*temp_ptr);
-	return 0;
-}
-
-/*
- * name, sensor type, read function,
- * index of sensor passed to read function,
- * delay from read to taking action
- */
-const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	/*
-	 * No need to re-init PMIC since settings are sticky across sysjump.
-	 * However, be sure to check that PMIC is already enabled. If it is
-	 * then there's no need to re-sequence the PMIC.
-	 */
-	if (system_jumped_to_this_image() && gpio_get_level(GPIO_PMIC_EN))
-		return;
-
-	/* Enable PP5000 before PP3300 due to NFC: chrome-os-partner:50807 */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-	while (!gpio_get_level(GPIO_PP5000_PG))
-		;
-
-	/*
-	 * To prevent SLP glitches, PMIC_EN (V5A_EN) should be enabled
-	 * at the same time as PP3300 (chrome-os-partner:51323).
-	 */
-	/* Enable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 1);
-	while (!gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/* Enable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 1);
-}
-
-static void board_set_tablet_mode(void)
-{
-	tablet_set_mode(!gpio_get_level(GPIO_TABLET_MODE_L),
-			TABLET_TRIGGER_LID);
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Ensure tablet mode is initialized according to the hardware state
-	 * so that the cached state reflects reality.
-	 */
-	board_set_tablet_mode();
-
-	gpio_enable_interrupt(GPIO_TABLET_MODE_L);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-/* PP3300 needs to be enabled before TCPC init hooks */
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
-
-/*
- * MCHP - new version of this routine.
- * firmware-reef-9042.B must do port lookup here
- * before calling bd9995x_is_vbus_provided
- */
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port != 0 && port != 1)
-		panic("Invalid charge port\n");
-
-	return bd9995x_is_vbus_provided(port);
-}
-
-/**
- * Set active charge port -- only one port can be active at a time.
- *
- * @param charge_port   Charge port to enable.
- *
- * Returns EC_SUCCESS if charge port is accepted and made active,
- * EC_ERROR_* otherwise.
- */
-int board_set_active_charge_port(int charge_port)
-{
-	enum bd9995x_charge_port bd9995x_port;
-	int bd9995x_port_select = 1;
-
-	switch (charge_port) {
-	case USB_PD_PORT_ANX74XX:
-	case USB_PD_PORT_PS8751:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-
-		bd9995x_port = charge_port;
-		break;
-	case CHARGE_PORT_NONE:
-		bd9995x_port_select = 0;
-		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
-
-		/*
-		 * To avoid inrush current from the external charger, enable
-		 * discharge on AC till the new charger is detected and
-		 * charge detect delay has passed.
-		 */
-		if (charge_get_percent() > 2)
-			charger_discharge_on_ac(1);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	CPRINTS("New chg p%d", charge_port);
-	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
-}
-
-/**
- * Set the charge limit based upon desired maximum.
- *
- * @param port          Port number.
- * @param supplier      Charge supplier type.
- * @param charge_ma     Desired charge limit (mA).
- * @param charge_mv     Negotiated charge voltage (mV).
- */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/* Enable charging trigger by BC1.2 detection */
-	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
-			   supplier == CHARGE_SUPPLIER_BC12_DCP ||
-			   supplier == CHARGE_SUPPLIER_BC12_SDP ||
-			   supplier == CHARGE_SUPPLIER_OTHER);
-
-	if (bd9995x_bc12_enable_charging(port, bc12_enable))
-		return;
-
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-/**
- * Return if board is consuming full amount of input current
- */
-int board_is_consuming_full_charge(void)
-{
-	int chg_perc = charge_get_percent();
-
-	return chg_perc > 2 && chg_perc < 95;
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	return voltage < BD9995X_BC12_MIN_VOLTAGE;
-}
-
-static void enable_input_devices(void)
-{
-	/* We need to turn on tablet mode for motion sense */
-	board_set_tablet_mode();
-
-	/* Then, we disable peripherals only when the lid reaches 360 position.
-	 * (It's probably already disabled by motion_sense_task.)
-	 * We deliberately do not enable peripherals when the lid is leaving
-	 * 360 position. Instead, we let motion_sense_task enable it once it
-	 * reaches laptop zone (180 or less).
-	 */
-	if (tablet_get_mode())
-		lid_angle_peripheral_enable(0);
-}
-
-/* Enable or disable input devices, based on chipset state and tablet mode */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	/* If the lid is in 360 position, ignore the lid angle,
-	 * which might be faulty. Disable keyboard.
-	 */
-	if (tablet_get_mode() || chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		enable = 0;
-	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
-}
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	/* Enable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 1);
-
-	/* Enable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	/* Disable USB-A port. */
-	gpio_set_level(GPIO_USB1_ENABLE, 0);
-
-	/* Disable Trackpad */
-	gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1);
-
-	hook_call_deferred(&enable_input_devices_data, 0);
-	/* FIXME(dhendrix): Drive USB_PD_RST_ODL low to prevent
-	 * leakage? (see comment in schematic)
-	 */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-/* FIXME(dhendrix): Add CHIPSET_RESUME and CHIPSET_SUSPEND
- * hooks to enable/disable sensors?
- */
-/*
- * MCHP: Next two routines not present in firmware-reef-9042.B
- */
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * FIXME(dhendrix): Weak symbol hack until we can get a better solution for
- * both Amenia and Reef.
- */
-void chipset_do_shutdown(void)
-{
-	/* Disable PMIC */
-	gpio_set_level(GPIO_PMIC_EN, 0);
-
-	/*Disable 3.3V rail */
-	gpio_set_level(GPIO_EN_PP3300, 0);
-	while (gpio_get_level(GPIO_PP3300_PG))
-		;
-
-	/*Disable 5V rail */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	while (gpio_get_level(GPIO_PP5000_PG))
-		;
-}
-
-void board_hibernate_late(void)
-{
-	int i;
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
-
-		/*
-		 * BD99956 handles charge input automatically. We'll disable
-		 * charge output in hibernate. Charger will assert ACOK_OD
-		 * when VBUS or VCC are plugged in.
-		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-	};
-
-	/* Change GPIOs' state in hibernate for better power consumption */
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
-
-	/*
-	 * Calling gpio_config_module sets disabled alternate function pins to
-	 * GPIO_INPUT.  But to prevent keypresses causing leakage currents
-	 * while hibernating we want to enable GPIO_PULL_UP as well.
-	 */
-	gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x1, 0x7F, GPIO_INPUT | GPIO_PULL_UP);
-	gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP);
-	/* KBD_KSO2 needs to have a pull-down enabled instead of pull-up */
-	gpio_set_flags_by_mask(0x1, 0x80, GPIO_INPUT | GPIO_PULL_DOWN);
-}
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct bmp280_drv_data_t bmp280_drv_data;
-/* MCHP: struct not present in firmware-reef-9042.B */
-static struct opt3001_drv_data_t g_opt3001_data = {
-	.scale = 1,
-	.uscale = 0,
-	.offset = 0,
-};
-
-/* MCHP: differences in structure initializatio from
- * firmware-reef-9042.B
- */
-/* FIXME(dhendrix): Copied from Amenia, probably need to tweak for Reef */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_LID_ACCEL,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[BASE_MAG] = {
-	 .name = "Base Mag",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_MAG,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_GYRO,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = BIT(11), /* 16LSB / uT, fixed */
-	 .rot_standard_ref = &mag_standard_ref,
-	 .min_frequency = BMM150_MAG_MIN_FREQ,
-	 .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
-	},
-	[BASE_BARO] = {
-	 .name = "Base Baro",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_BMP280,
-	 .type = MOTIONSENSE_TYPE_BARO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmp280_drv,
-	 .drv_data = &bmp280_drv_data,
-	 .port = I2C_PORT_BARO,
-	 .i2c_spi_addr_flags = BMP280_I2C_ADDRESS1_FLAGS,
-	 .default_range = BIT(18), /*  1bit = 4 Pa, 16bit ~= 2600 hPa */
-	 .min_frequency = BMP280_BARO_MIN_FREQ,
-	 .max_frequency = BMP280_BARO_MAX_FREQ,
-	},
-	[LID_ALS] = {
-	 .name = "Light",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_OPT3001,
-	 .type = MOTIONSENSE_TYPE_LIGHT,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &opt3001_drv,
-	 .drv_data = &g_opt3001_data,
-	 .port = I2C_PORT_ALS,
-	 .i2c_spi_addr_flags = OPT3001_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 0x10000, /* scale = 1; uscale = 0 */
-	 .min_frequency = OPT3001_LIGHT_MIN_FREQ,
-	 .max_frequency = OPT3001_LIGHT_MAX_FREQ,
-	 .config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 1000,
-		},
-	 },
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*
- * MCHP: difference from firmware-reef-9042.B
- * New code doesn't have TASK_ALS
- */
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[LID_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-void board_hibernate(void)
-{
-	/*
-	 * To support hibernate called from console commands, ectool commands
-	 * and key sequence, shutdown the AP before hibernating.
-	 */
-	chipset_do_shutdown();
-
-	/* Added delay to allow AP to settle down */
-	msleep(100);
-
-	/* Enable both the VBUS & VCC ports before entering PG3 */
-	bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
-
-	/* Turn BGATE OFF for saving the power */
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_MAX);
-}
-
-struct {
-	enum reef_board_version version;
-	int thresh_mv;
-} const reef_board_versions[] = {
-	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
-	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
-	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
-	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
-	{ BOARD_VERSION_6, 2020 * 1.03 }, /* 73.2 Kohm */
-	{ BOARD_VERSION_7, 2352 * 1.03 }, /* 115 Kohm */
-	{ BOARD_VERSION_8, 2802 * 1.03 }, /* 261 Kohm */
-};
-BUILD_ASSERT(ARRAY_SIZE(reef_board_versions) == BOARD_VERSION_COUNT);
-
-/*
- * Checkpatch claims msleep(n) for n < 20 can sleep up to 20 ms.
- * Loop up to 10 times sampling every 100 us. If 5 or more consecutive
- * samples are the same exit sample loop.
- */
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv, i, prev, cnt;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	/* FIXME(dhendrix): enable ADC */
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_ODR_HIGH);
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 0);
-	/* Wait to allow cap charge */
-	prev = 0;
-	cnt = 0;
-	for (i = 0; i < 10; i++) {
-		udelay(100);
-		mv = adc_read_channel(ADC_BOARD_ID);
-		if (mv != prev) {
-			prev = mv;
-			cnt = 0;
-		} else {
-			cnt++;
-		}
-		if (cnt >= 5)
-			break;
-	}
-	/* FIXME(dhendrix): disable ADC */
-	gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 1);
-	gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_INPUT);
-
-	if (mv == ADC_READ_ERROR) {
-		version = BOARD_VERSION_UNKNOWN;
-		return version;
-	}
-
-	for (i = 0; i < BOARD_VERSION_COUNT; i++) {
-		if (mv < reef_board_versions[i].thresh_mv) {
-			version = reef_board_versions[i].version;
-			break;
-		}
-	}
-
-	CPRINTS("Board version: %d", version);
-	return version;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h
deleted file mode 100644
index c9b2704530..0000000000
--- a/board/reef_mchp/board.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Reef board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* EC console on UART 0 */
-#define CONFIG_UART_CONSOLE 0
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_BATT_MFG_ACCESS
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-#define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
-
-#define CONFIG_CHARGER_PSYS_READ
-#define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
-
-#define CONFIG_CMD_I2C_STRESS_TEST
-#define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-#define CONFIG_CMD_I2C_STRESS_TEST_ALS
-#define CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-#define CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-#define CONFIG_CMD_I2C_STRESS_TEST_TCPC
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_SMART
-
-/* Charger */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BD9995X
-#define CONFIG_CHARGER_BD9995X_CHGEN
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-#define CONFIG_USB_CHARGER
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-#define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
-#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-
-/* USB-A config */
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
-#define GPIO_USB_CTL1 GPIO_EN_PP5000
-
-#define CONFIG_TABLET_MODE
-
-/* USB PD config */
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
-#define CONFIG_USB_PD_TCPM_ANX3429 /* Silicon on Reef is ANX3429 */
-#define CONFIG_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-/* SoC / PCH */
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_CHIPSET_APOLLOLAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-/* EC */
-#define CONFIG_ADC
-#define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
-#define CONFIG_FPU
-#define CONFIG_HOSTCMD_FLASH_SPI_INFO
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define CONFIG_LED_COMMON
-#define CONFIG_LID_SWITCH
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LTO
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_PWM
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_DPTF
-#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define CONFIG_VBOOT_HASH
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_WIRELESS
-#define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
-#define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
-#define CONFIG_PWR_STATE_DISCHARGE_FULL
-
-/*
- * During shutdown sequence TPS65094x PMIC turns off the sensor rails
- * asynchronously to the EC. If we access the sensors when the sensor power
- * rails are off we get I2C errors. To avoid this issue, defer switching
- * the sensors rate if in S3. By the time deferred function is serviced if
- * the chipset is in S5 we can back out from switching the sensor rate.
- *
- * Time taken by V1P8U rail to go down from S3 is 30ms to 60ms hence defer
- * the sensor switching after 60ms.
- */
-#undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
-#define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60)
-
-/*
- * MEC1701H loads firmware using QMSPI controller
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-
-#define CONFIG_FLASH_SIZE_BYTES 524288
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
-
-/*
- * Enable 1 slot of secure temporary storage to support
- * suspend/resume with read/write memory training.
- */
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* Optional feature - used by MCHP */
-#define CONFIG_CLOCK_CRYSTAL /* interposer board uses parallel crystal */
-#define CONFIG_WATCHDOG_HELP /* required for MCHP MEC17xx */
-#define CONFIG_BOARD_PRE_INIT
-
-/* I2C ports */
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-#define I2C_PORT_GYRO			MCHP_I2C_PORT6
-#define I2C_PORT_LID_ACCEL		MCHP_I2C_PORT7
-#define I2C_PORT_ALS			MCHP_I2C_PORT7
-#define I2C_PORT_BARO			MCHP_I2C_PORT7
-#define I2C_PORT_BATTERY		MCHP_I2C_PORT3
-#define I2C_PORT_CHARGER		MCHP_I2C_PORT3
-/* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
-
-/* Sensors */
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_MAG_BMI_BMM150
-#define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_MAG_CALIBRATE
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ALS_OPT3001
-#define CONFIG_BARO_BMP280
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 1024
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED_GREEN = 0,
-	PWM_CH_LED_RED,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY = 0,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-/* MCHP - new Reef code not using TASK_ALS */
-/*
- * For backward compatibility, to report ALS via ACPI,
- * Define the number of ALS sensors: motion_sensor copy the data to the ALS
- * memmap region.
- */
-#define CONFIG_ALS
-#define ALS_COUNT 1
-
-/*
- * Motion sensors:
- * When reading through IO memory is set up for sensors (LPC is used),
- * the first 2 entries must be accelerometers, then gyroscope.
- * For BMI160, accel, gyro and compass sensors must be next to each other.
- */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	BASE_MAG,
-	BASE_BARO,
-	LID_ALS,	/* firmware-reef-9042.B doesn't have this */
-	SENSOR_COUNT,
-};
-
-enum reef_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_1,
-	BOARD_VERSION_2,
-	BOARD_VERSION_3,
-	BOARD_VERSION_4,
-	BOARD_VERSION_5,
-	BOARD_VERSION_6,
-	BOARD_VERSION_7,
-	BOARD_VERSION_8,
-	BOARD_VERSION_COUNT,
-};
-
-/* TODO: determine the following board specific type-C power constants */
-/* FIXME(dhendrix): verify all of the below PD_* numbers */
-/*
- * delay to turn on the power supply max is ~16ms.
- * delay to turn off the power supply max is about ~180ms.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-
-/* delay to turn on/off vconn */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Reset PD MCU */
-void board_reset_pd_mcu(void);
-
-int board_get_version(void);
-
-void board_set_tcpc_power_mode(int port, int mode);
-void board_print_tcpc_fw_version(int port);
-
-/* Map I2C port to controller */
-int board_i2c_p2c(int port);
-
-/* MCHP - firwmare-reef-9042.B does have LID_ALS bit
- * because its using TASK_ALS ?
- */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(BASE_BARO) | BIT(LID_ALS))
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/reef_mchp/build.mk b/board/reef_mchp/build.mk
deleted file mode 100644
index 19fffbaf0d..0000000000
--- a/board/reef_mchp/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=mchp
-CHIP_FAMILY:=mec170x
-CHIP_VARIANT:=mec1701
-CHIP_SPI_SIZE_KB:=512
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/reef_mchp/ec.tasklist b/board/reef_mchp/ec.tasklist
deleted file mode 100644
index adf63fae62..0000000000
--- a/board/reef_mchp/ec.tasklist
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- * These 3 go after HOOKS and before MOTIONSENSE. Remember to add backslashes!
- * TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE)
- * TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE)
- * TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE)
- *
- * These 2 go at the end of the list. Remember proper backslashes
- * TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
- * TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc
deleted file mode 100644
index 0385d82102..0000000000
--- a/board/reef_mchp/gpio.inc
+++ /dev/null
@@ -1,311 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* include common gpio.inc under chip/mchp/lfw/... */
-#include "chip/mchp/lfw/gpio.inc"
-
-/* MEC1701H GPIO_0105/UART0_RX OK */
-GPIO_INT(UART0_RX, PIN(0105), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, \
-	 uart_deepsleep_interrupt)
-
-GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_INT_BOTH | GPIO_PULL_UP, lpcrst_interrupt)
-
-GPIO_INT(CHARGER_INT_L,	PIN(0143), GPIO_INT_FALLING, bd9995x_vbus_interrupt)
-/* CHARGER_EC_INT_ODL from BD99956 */
-/*
- * TODO: The pull ups for Parade TCPC interrupt line can be removed in versions
- * of board following EVT in which daughter card (which has an external pull up)
- * will always be inserted.
- */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(0175), GPIO_INT_FALLING, tcpc_alert_event)
-/* from Analogix TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL, PIN(0126), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event)
-/* from Parade TCPC */
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-GPIO_INT(USB_C0_CABLE_DET, PIN(0246), GPIO_INT_RISING, anx74xx_cable_det_interrupt)
-/* CABLE_DET from ANX3429 */
-#endif
-
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L, PIN(050), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L, PIN(033), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L, PIN(035), GPIO_INT_BOTH, power_signal_interrupt)		/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,   PIN(057), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD, PIN(0243), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	PIN(0240), GPIO_INT_BOTH, power_signal_interrupt)		/* PMIC_EC_PWROK_OD */
-
-/* ACOK_OD from BD99956 */
-GPIO_INT(AC_PRESENT, PIN(0242), GPIO_INT_BOTH, extpower_interrupt)
-
-/* TODO: We might remove external pull-up for POWER_BUTTON_L in EVT */
-GPIO_INT(POWER_BUTTON_L, PIN(0241), GPIO_INT_BOTH, power_button_interrupt)		/* MECH_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN, PIN(0206), GPIO_INT_BOTH, lid_interrupt)
-/* Volume up and down buttons need to be swapped. The one closer to the hinge
- * should be volume up and the one closer to the user should be volume down.
- * (cros.bug/p/60057) */
-GPIO_INT(EC_VOLDN_BTN_ODL_SWAPPED,	PIN(042), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL_SWAPPED,	PIN(044), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-#define GPIO_EC_VOLDN_BTN_ODL GPIO_EC_VOLUP_BTN_ODL_SWAPPED
-#define GPIO_EC_VOLUP_BTN_ODL GPIO_EC_VOLDN_BTN_ODL_SWAPPED
-/* Tablet switch is active-low. L: lid is attached (360 position) H: detached */
-GPIO_INT(TABLET_MODE_L,		PIN(0207), GPIO_INT_BOTH, tablet_mode_interrupt)
-
-GPIO_INT(WP_L,			PIN(0152), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt)	/* EC_WP_ODL */
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(0131), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-	 bmi160_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(014), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* I2C GPIOs will be set to alt. function later. */
-GPIO(EC_I2C_GYRO_SDA,		PIN(0132), GPIO_INPUT) /* original reef | GPIO_SEL_1P8V */
-GPIO(EC_I2C_GYRO_SCL,		PIN(0140), GPIO_INPUT) /* original reef | GPIO_SEL_1P8V */
-GPIO(EC_I2C_SENSOR_SDA,		PIN(012), GPIO_INPUT) /* original reef | GPIO_SEL_1P8V */
-GPIO(EC_I2C_SENSOR_SCL,		PIN(013), GPIO_INPUT) /* original reef | GPIO_SEL_1P8V */
-GPIO(EC_I2C_USB_C0_PD_SDA,	PIN(003), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,	PIN(004), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,	PIN(0154), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,	PIN(0155), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(007), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(010), GPIO_INPUT)
-
-/*
- * LPC:
- * Pins 46, 47, 51, 52, 53, 54, 55, default to LPC mode.
- * Pin 56 (CLKRUN#) defaults to GPIO mode.
- * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL
- * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case).
- *
- * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option.
- */
-
-GPIO(PCH_SMI_L,			PIN(0227), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SMI_ODL */
-GPIO(PCH_SCI_L,			PIN(0222), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_SCI_ODL */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,              PIN(050), GPIO_INPUT)				/* SLP_S0_L */
-#endif
-
-/*
- * BRD_ID1 is a an ADC pin which will be used to measure multiple values.
- * Assert EC_BRD_ID_EN_ODL and then read BRD_ID1.
- */
-ALTERNATE(PIN_MASK(4, 0x04), 1, MODULE_ADC, 0) /* GPIO 0202 bank=4 bit=2 func=1 ADC02 */
-GPIO(EC_BRD_ID_EN_ODL,		PIN(0221), GPIO_INPUT)
-
-GPIO(CCD_MODE_ODL,		PIN(0203), GPIO_INPUT)
-GPIO(EC_HAVEN_RESET_ODL,	PIN(034), GPIO_ODR_HIGH)
-GPIO(ENTERING_RW,		PIN(0254), GPIO_OUTPUT)			/* EC_ENTERING_RW */
-
-GPIO(PCH_RSMRST_L,		PIN(0165), GPIO_OUT_LOW | GPIO_PULL_UP)
-GPIO(EC_BATT_PRES_L,		PIN(0204), GPIO_INPUT)
-GPIO(PMIC_EN,			PIN(0245), GPIO_OUT_LOW)
-GPIO(EN_PP3300,			PIN(023), GPIO_OUT_LOW)
-GPIO(PP3300_PG,			PIN(0156), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_PP5000,			PIN(051), GPIO_OUT_LOW)
-GPIO(PP5000_PG,			PIN(0157), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(043), GPIO_ODR_LOW)
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,		PIN(054), GPIO_OUT_LOW)
-GPIO(PCH_SYS_PWROK,		PIN(0106), GPIO_OUT_LOW)	/* EC_PCH_PWROK */
-GPIO(ENABLE_BACKLIGHT,		PIN(002), GPIO_ODR_HIGH | GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-
-GPIO(WIRELESS_GPIO_WLAN_POWER,	PIN(0142), GPIO_ODR_HIGH)		/* EN_PP3300_WLAN_ODL */
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,		PIN(0114), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-GPIO(PCH_PWRBTN_L,		PIN(0244), GPIO_ODR_HIGH)		/* EC_PCH_PWR_BTN_ODL */
-GPIO(PCH_WAKE_L,		PIN(0115), GPIO_ODR_HIGH)		/* EC_PCH_WAKE_ODL */
-GPIO(USB_C0_HPD_1P8_ODL,	PIN(052), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(USB_C1_HPD_1P8_ODL,	PIN(0151), GPIO_INPUT | GPIO_SEL_1P8V)
-
-GPIO(USB2_OTG_VBUSSENSE,	PIN(053), GPIO_OUTPUT)
-
-/* EC_PCH_RTCRST is a sledgehammer for resetting SoC state and should rarely
- * be used. Set as input for now, we'll set it as an output when we want to use
- * it. Has external pull-down resistor. */
-GPIO(EC_PCH_RTCRST,		PIN(0205), GPIO_INPUT)
-/* Latest code (2018-03-28) in power/intel_x86.c uses SYS_RESET_L signal name
- * Previous Reef used PCH_RCIN_L
- */
-GPIO(SYS_RESET_L,		PIN(036), GPIO_ODR_HIGH) /* SYS_RST_ODL */
-
-/* FIXME: What, if anything, to do about EC_RST_ODL on VCC1_RST#? */
-
-GPIO(CHARGER_RST_ODL,		PIN(0141), GPIO_ODR_HIGH)
-GPIO(USB_A_CHARGE_EN_L,		PIN(022), GPIO_OUT_LOW)
-GPIO(EN_USB_TCPC_PWR,		PIN(0100), GPIO_OUT_LOW)
-GPIO(USB1_ENABLE,		PIN(0144), GPIO_OUT_LOW)
-
-GPIO(USB_C0_PD_RST_L,		PIN(024), GPIO_OUT_LOW)		/* USB_C0_PD_RST_L */
-GPIO(USB_C1_PD_RST_ODL,		PIN(0127), GPIO_ODR_LOW)
-
-/*
- * Configure as input to enable @ 1.5A, output-low to turn off, or output-high
- * to enable @ 3A.
- */
-GPIO(USB_C0_5V_EN,		PIN(011), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C0_5V_OUT, Enable C0 */
-GPIO(USB_C1_5V_EN,		PIN(061), GPIO_OUT_LOW | GPIO_PULL_UP)	/* EN_USB_C1_5V_OUT, Enable C1 */
-
-/* Clear for non-HDI breakout, must be pulled high */
-/* reefmchp board note: following 3 GPIOs are not NC on reef board, which are not mapping to MEC1701 */
-//GPIO(NC1,			PIN(0154), GPIO_INPUT | GPIO_PULL_UP | GPIO_SEL_1P8V)
-//GPIO(NC2,			PIN(0155), GPIO_INPUT | GPIO_PULL_UP | GPIO_SEL_1P8V)
-
-//GPIO(ENG_STRAP,			PIN(0156), GPIO_INPUT)
-
-GPIO(BAT_LED_BLUE,		PIN(0153), GPIO_OUT_HIGH)
-GPIO(BAT_LED_AMBER,		PIN(0226), GPIO_OUT_HIGH)
-
-/*
- * Alternate function pins
- */
-
-/* MEC1701H LPC all alternate function 1
- *			bank	bit
- * GPIO061 LPCPD#	1	17
- * GPIO063 SER_IRQ	1	19
- * GPIO064 LRESET#	1	20 need internal pull-up
- * GPIO065 PCI_CLK	1	21
- * GPIO066 LFRAME#	1	22
- * GPIO067 CLKRUN#	1	23
- * GPIO070 LAD0		1	24
- * GPIO071 LAD1		1	25
- * GPIO072 LAD2		1	26
- * GPIO073 LAD3		1	27
- */
-ALTERNATE(PIN_MASK(1, 0x0FF80000), 1, MODULE_LPC, 0)
-ALTERNATE(PIN_MASK(1, 0x00100000), 1, MODULE_LPC, GPIO_PULL_UP | GPIO_INT_BOTH)
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
-
-/*
- * 8 x 13 key scan matrix
- * MEC1704H (144 pin package)
- *
- * KSI0 = GPIO_0017 Func3 bank 0 bit 15
- * KSI1 = GPIO_0020 Func3 bank 0 bit 16
- * KSI2 = GPIO_0021 Func3 bank 0 bit 17
- * KSI3 = GPIO_0026 Func3 bank 0 bit 22
- * KSI4 = GPIO_0027 Func3 bank 0 bit 23
- * KSI5 = GPIO_0030 Func3 bank 0 bit 24
- * KSI6 = GPIO_0031 Func3 bank 0 bit 25
- * KSI7 = GPIO_0032 Func3 bank 0 bit 26
- *
- * KSO00 = GPIO_0040 Func3 bank 1 bit 0
- * KSO01 = GPIO_0045 Func3 bank 1 bit 5
- * KSO02 = GPIO_0046 Func3 bank 1 bit 6
- * KSO03 = GPIO_0047 Func3 bank 1 bit 7
- * KSO04 = GPIO_0107 Func3 bank 2 bit 7
- * KSO05 = GPIO_0112 Func3 bank 2 bit 10
- * KSO06 = GPIO_0113 Func3 bank 2 bit 11
- * KSO07 = GPIO_0120 Func3 bank 2 bit 16
- * KSO08 = GPIO_0121 Func3 bank 2 bit 17
- * KSO09 = GPIO_0122 Func3 bank 2 bit 18
- * KSO10 = GPIO_0123 Func3 bank 2 bit 19
- * KSO11 = GPIO_0124 Func3 bank 2 bit 20
- * KSO12 = GPIO_0125 Func3 bank 2 bit 21
- */
-/* KSI 0-7, Bank 0, Func3, bits 15-17, 22-26 */
-ALTERNATE(PIN_MASK(0, 0x07C38000), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
-/* KSO 4-12, Bank 2, Func3, bits 7, 10-11, 16-21 */
-ALTERNATE(PIN_MASK(2, 0x003F0C80), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-/* KSO 0,1,3 Bank 1, Func3, bits 0, 5-7 */
-ALTERNATE(PIN_MASK(1, 0xA1), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-GPIO(KBD_KSO2, PIN(046), GPIO_KB_OUTPUT_COL2)
-#else
-/* KSO 0-3 Bank 1, Func3, bits 0, 5-7 */
-ALTERNATE(PIN_MASK(1, 0xE1), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
-#endif
-
-
-/* MEC1701H ADC01=GPIO201 Func1, ADC00=GPIO200 Func 1
- * Bank 1 bits[1:0]
- * TEMP_SENSOR_AMB (GPIO201) and TEMP_SENSOR_CHARGER (GPIO200)
- */
-ALTERNATE(PIN_MASK(4, 0x03), 1, MODULE_ADC, 0)
-
-/* MEC1701H implements I2C[0,2,3,6,7]
- * We need 5 ports.
- * I2C00_SDA is GPIO003 Func1, I2C00_SCL is GPIO004 Func1 bank 0 bits[3:4]
- * I2C03_SDA is GPIO007 Func1, I2C03_SCL is GPIO010 Func1 bank 0 bits[7:8]
- * I2C07_SDA is GPIO012 Func1, I2C07_SCL is GPIO013 Func1 bank 0 bits[10:11]
- * I2C06_SDA is GPIO132 Func1, I2C06_SCL is GPIO140 Func1 bank 2 bits[26]; bank 3 bits[0]
- * I2C02_SDA is GPIO154 Func1, I2C02_SCL is GPIO155 Func1 bank 3 bits[12:13]
- */
-/* GPIO003-004 for EC_I2C_USB_C0_PD_SDA/SCL */
-/* GPIO007-010 for EC_I2C_POWER_SDA/SCL */
-/* GPIO012-013 for EC_I2C_SENSOR_SDA/SCL */
-ALTERNATE(PIN_MASK(0, 0x00000D98), 1, MODULE_I2C, 0)
-/* GPIO132 for EC_I2C_GYRO_SDA */
-ALTERNATE(PIN_MASK(2, 0x04000000), 1, MODULE_I2C, 0)
-/* GPIO140 for EC_I2C_GYRO_SCL */
-/* GPIO154-155 for EC_I2C_USB_C1_PD_SDA/SCL */
-ALTERNATE(PIN_MASK(3, 0x00003001), 1, MODULE_I2C, 0)
-
-/*
- * PWM4 = GPIO001 Func1
- * PWM5 = GPIO002 Func1
- */
-/* reefmchp board note: not PWM in reef or reedmchp boards design?? */
-//ALTERNATE(PIN_MASK(0, 0x00000006), 1, MODULE_PWM, 0)
-
-/*
- * MCHP TFDP alternate function configuration
- * GPIO 0170 = clock, 0171 = data both function 1
- * Port = 3 bits[24:25]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_TFDP, 0)
-
-/* reefmchp board note: specific for reedmchp board only */
-
-/* GPIO101 - enable high accurate reference voltage regulator MAX6070
-   1 - enable regulator, in normal runtime
-   0 - disable regulator, in low power mode
- */
-GPIO(VOL_REGULATOR_EN,	PIN(0101), GPIO_OUT_HIGH)
-
-/* GPIO015 - enable 3.3V / 1.8V level switch TXS0108
-   1 - enable level switch, in normal runtime
-   0 - disable level switch, in low power mode
- */
-GPIO(LEVEL_SW_EN,	PIN(015), GPIO_OUT_HIGH | GPIO_SEL_1P8V)
-
-/* DEBUG I2C */
-GPIO(GP025, PIN(025), GPIO_OUT_HIGH | GPIO_PULL_UP)
-
-/* Low power deep sleep test. GPIO_0060 Function 2 48MHZ_OUT */
-ALTERNATE(PIN_MASK(1, 0x10000), 2, MODULE_CHIPSET, 0)
-
-/* Unused pins - on test header J47 */
-/* Clear for non-HDI breakout, must be pulled high */
-GPIO(NC1_UNUSED,    PIN(062), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC2_UNUSED,    PIN(0102), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC3_UNUSED,    PIN(000), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC4_UNUSED,    PIN(0130), GPIO_INPUT | GPIO_PULL_UP)
-/* GPIO(NC5_UNUSED,    PIN(060), GPIO_INPUT | GPIO_PULL_UP) */
-/* use this for low power mode test */
-/* ALTERNATE(PIN_MASK(1, 0x00010000), 2, MODULE_GPIO, 0) */
-GPIO(NC6_UNUSED,    PIN(0161), GPIO_INPUT | GPIO_PULL_UP)
-/* GPIO(NC7_UNUSED,    PIN(025), GPIO_INPUT | GPIO_PULL_UP) */
-GPIO(NC8_UNUSED,    PIN(0162), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC9_UNUSED,    PIN(0172), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(NC10_UNUSED,   PIN(0163), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/reef_mchp/led.c b/board/reef_mchp/led.c
deleted file mode 100644
index ca49fe4ed5..0000000000
--- a/board/reef_mchp/led.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Reef
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
-#define LOW_BATTERY_PERCENTAGE 10
-
-#define LED_TOTAL_4SECS_TICKS 4
-#define LED_TOTAL_2SECS_TICKS 2
-#define LED_ON_1SEC_TICKS 1
-#define LED_ON_2SECS_TICKS 2
-
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_BLUE,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-static int led_set_color(enum ec_led_id led_id, enum led_color color)
-{
-	int rv;
-
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return rv;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(led_id, LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void led_set_battery(void)
-{
-	static int battery_ticks;
-	static int suspend_ticks;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_BLUE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON)) {
-			led_set_color_battery(LED_BLUE);
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Blink once every four seconds. */
-			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
-		} else {
-			led_set_color_battery(LED_OFF);
-		}
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_BLUE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	battery_ticks++;
-	suspend_ticks++;
-}
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	/*
-	 * Reference board only has one LED, so overload it to act as both
-	 * power LED and battery LED.
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
diff --git a/board/reef_mchp/lfw/vif_override.xml b/board/reef_mchp/lfw/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/reef_mchp/lfw/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/reef_mchp/usb_pd_policy.c b/board/reef_mchp/usb_pd_policy.c
deleted file mode 100644
index 90f44f8580..0000000000
--- a/board/reef_mchp/usb_pd_policy.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "extpower.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/tcpm/anx74xx.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#include "tfdp_chip.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-static void board_vbus_update_source_current(int port)
-{
-	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
-	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
-
-	/*
-	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
-	 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
-	 * setting a minimum OCP current of 3186 mA.
-	 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put a 33k
-	 * resistor on ILIM, setting a minimum OCP current of 1505 mA.
-	 */
-	gpio_set_level(gpio, vbus_en[port]);
-	gpio_set_flags(gpio, flags);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-
-	/* change the GPIO driving the load switch if needed */
-	board_vbus_update_source_current(port);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Ensure we're not charging from this port */
-	bd9995x_select_input_port(port, 0);
-
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/* in G3, do not allow vconn swap since pp5000_A rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
diff --git a/board/reef_mchp/vif_override.xml b/board/reef_mchp/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/reef_mchp/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/sasuke/battery.c b/board/sasuke/battery.c
deleted file mode 100644
index ad7ea9c2fe..0000000000
--- a/board/sasuke/battery.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-#include "hooks.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CHARGING_CURRENT_REDUCE	4000
-/*
- * Battery info for all sasuke battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- *
- * Battery FET Status in Manufacture Access : bit15 & bit14
- *  b'00 - dfet : on / cfet : on
- *  b'01 - dfet : on / cfet : off
- *  b'10 - dfet : off / cfet : off
- *  b'11 - dfet : off / cfet : on
- *  The value b'10 is disconnect_val, so we can use b'01 for cfet_off_val
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SDI Battery Information */
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4432D53",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0xc000,
-				.cfet_off_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8760,
-			.voltage_normal         = 7720, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 50,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-	/* SWD(Sunwoda) Battery Information */
-	[BATTERY_SWD] = {
-		.fuel_gauge = {
-			.manuf_name = "SWD",
-			.device_name = "4432W53",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0xc000,
-				.cfet_off_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8760,
-			.voltage_normal         = 7720, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 45,
-			.charging_min_c         = 0,
-			.charging_max_c         = 50,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int current;
-	int voltage;
-
-	current = curr->requested_current;
-	voltage = curr->requested_voltage;
-
-	voltage -= 100;
-	if (current > CHARGING_CURRENT_REDUCE)
-		current -= (current / 10);
-
-	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
-	curr->requested_current = MIN(curr->requested_current, current);
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-/* Lower our input voltage to 5V in S0iX when battery is full. */
-#define PD_VOLTAGE_WHEN_FULL 5000
-static void reduce_input_voltage_when_full(void)
-{
-	static int saved_input_voltage = -1;
-	int max_pd_voltage_mv = pd_get_max_voltage();
-	int port;
-
-	if (charge_get_percent() == 100 &&
-			chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
-			saved_input_voltage = max_pd_voltage_mv;
-			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
-		}
-	} else if (saved_input_voltage != -1) {
-		if (max_pd_voltage_mv == PD_VOLTAGE_WHEN_FULL)
-			max_pd_voltage_mv = saved_input_voltage;
-		saved_input_voltage = -1;
-	}
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv) {
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full,
-             HOOK_PRIO_DEFAULT);
diff --git a/board/sasuke/board.c b/board/sasuke/board.c
deleted file mode 100644
index 21631c0323..0000000000
--- a/board/sasuke/board.c
+++ /dev/null
@@ -1,789 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "cros_board_info.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/nb7v904m.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_8042.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
-}
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-        [TEMP_SENSOR_1] = {.name = "Memory",
-                           .type = TEMP_SENSOR_TYPE_BOARD,
-                           .read = get_temp_3v3_51k1_47k_4050b,
-                           .idx = ADC_TEMP_SENSOR_1},
-        [TEMP_SENSOR_2] = {.name = "Charger",
-                           .type = TEMP_SENSOR_TYPE_BOARD,
-                           .read = get_temp_3v3_51k1_47k_4050b,
-                           .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-static int board_id = -1;
-static int mux_c1 = SSFC_USB_SS_MUX_DEFAULT;
-
-extern const struct usb_mux usbc0_retimer;
-extern const struct usb_mux usbmux_ps8743;
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-
-		/* Set HDMI and sub-rail enables to output */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
-			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
-
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-
-		/* Enable interrupt for passing through HPD */
-		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-	} else {
-		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
-
-		/* Enable C1 interrupts */
-		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
-		check_c1_line();
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	if (board_id == -1) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) == EC_SUCCESS) {
-			board_id = val;
-			if (board_id == 2) {
-				nb7v904m_lpm_disable = 1;
-				nb7v904m_set_aux_ch_switch(&usbc0_retimer,
-						NB7V904M_AUX_CH_FLIPPED);
-			}
-		}
-	}
-
-	mux_c1 = get_cbi_ssfc_usb_ss_mux();
-
-	if (mux_c1 == SSFC_USB_SS_MUX_PS8743)
-		memcpy(&usb_muxes[1],
-				&usbmux_ps8743,
-				sizeof(struct usb_mux));
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, false);
-}
-
-/* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-};
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void set_5v_gpio(int level)
-{
-	gpio_set_level(GPIO_EN_PP5000, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC, or send enable signal to HDMI
-	 * DB.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
-	} else {
-		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
-	}
-
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CHARGER_NUM - 1;
-	else
-		return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
-						mux_state_t mux_state);
-static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state);
-static int ps8743_tune_mux(const struct usb_mux *me);
-
-const struct usb_mux usbc0_retimer = {
-	.usb_port = 0,
-	.i2c_port = I2C_PORT_USB_C0,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-	.board_set = &board_nb7v904m_mux_set_c0,
-};
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-	.board_set = &board_nb7v904m_mux_set,
-};
-
-const struct usb_mux usbmux_ps8743 = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-	.driver = &ps8743_usb_mux_driver,
-	.board_init = &ps8743_tune_mux,
-};
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc0_retimer,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	}
-};
-/* USB Mux C1 : board_init of PS8743 */
-static int ps8743_tune_mux(const struct usb_mux *me)
-{
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
-
-	return EC_SUCCESS;
-}
-
-/* USB Mux C0 */
-static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
-						mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
-
-	if (board_id == -1) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) == EC_SUCCESS)
-			board_id = val;
-		if (board_id == 2)
-			nb7v904m_lpm_disable = 1;
-	}
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			/* USB with DP */
-			if (flipped) {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_10_DB,
-							NB7V904M_CH_B_EQ_0_DB,
-							NB7V904M_CH_C_EQ_2_DB,
-							NB7V904M_CH_D_EQ_2_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_A_GAIN_0_DB,
-							NB7V904M_CH_B_GAIN_1P5_DB,
-							NB7V904M_CH_C_GAIN_0_DB,
-							NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_C);
-			}
-			else {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_2_DB,
-							NB7V904M_CH_B_EQ_2_DB,
-							NB7V904M_CH_C_EQ_0_DB,
-							NB7V904M_CH_D_EQ_10_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_A_GAIN_0_DB,
-							NB7V904M_CH_B_GAIN_0_DB,
-							NB7V904M_CH_C_GAIN_1P5_DB,
-							NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A);
-			}
-		} else {
-			/* USB only */
-			if (board_id == 2)
-				rv |= nb7v904m_set_aux_ch_switch(me,
-						NB7V904M_AUX_CH_FLIPPED);
-
-			rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_10_DB,
-						NB7V904M_CH_B_EQ_0_DB,
-						NB7V904M_CH_C_EQ_0_DB,
-						NB7V904M_CH_D_EQ_10_DB);
-			rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_A_GAIN_0_DB,
-						NB7V904M_CH_B_GAIN_1P5_DB,
-						NB7V904M_CH_C_GAIN_1P5_DB,
-						NB7V904M_CH_D_GAIN_0_DB);
-			rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A);
-		}
-
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* 4 lanes DP */
-		rv |= nb7v904m_tune_usb_set_eq(me,
-					NB7V904M_CH_A_EQ_2_DB,
-					NB7V904M_CH_B_EQ_2_DB,
-					NB7V904M_CH_C_EQ_2_DB,
-					NB7V904M_CH_D_EQ_2_DB);
-		rv |= nb7v904m_tune_usb_flat_gain(me,
-					NB7V904M_CH_A_GAIN_0_DB,
-					NB7V904M_CH_B_GAIN_0_DB,
-					NB7V904M_CH_C_GAIN_0_DB,
-					NB7V904M_CH_D_GAIN_0_DB);
-		rv |= nb7v904m_set_loss_profile_match(me,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C);
-	}
-
-	return rv;
-}
-
-/* USB Mux */
-static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			if (flipped) {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_10_DB,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_D_EQ_4_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_ALL_SKIP_GAIN,
-							NB7V904M_CH_B_GAIN_3P5_DB,
-							NB7V904M_CH_C_GAIN_0_DB,
-							NB7V904M_CH_ALL_SKIP_GAIN);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_D);
-			}
-			else {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_4_DB,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_D_EQ_10_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_ALL_SKIP_GAIN,
-							NB7V904M_CH_B_GAIN_0_DB,
-							NB7V904M_CH_C_GAIN_3P5_DB,
-							NB7V904M_CH_ALL_SKIP_GAIN);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A);
-			}
-		} else {
-			/* USB only */
-			rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_10_DB,
-						NB7V904M_CH_ALL_SKIP_EQ,
-						NB7V904M_CH_ALL_SKIP_EQ,
-						NB7V904M_CH_D_EQ_10_DB);
-			rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_ALL_SKIP_GAIN,
-						NB7V904M_CH_B_GAIN_3P5_DB,
-						NB7V904M_CH_C_GAIN_3P5_DB,
-						NB7V904M_CH_ALL_SKIP_GAIN);
-			rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A);
-		}
-
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* 4 lanes DP */
-		rv |= nb7v904m_tune_usb_set_eq(me,
-					NB7V904M_CH_A_EQ_4_DB,
-					NB7V904M_CH_ALL_SKIP_EQ,
-					NB7V904M_CH_ALL_SKIP_EQ,
-					NB7V904M_CH_D_EQ_4_DB);
-		rv |= nb7v904m_tune_usb_flat_gain(me,
-					NB7V904M_CH_ALL_SKIP_GAIN,
-					NB7V904M_CH_B_GAIN_0_DB,
-					NB7V904M_CH_C_GAIN_0_DB,
-					NB7V904M_CH_ALL_SKIP_GAIN);
-		rv |= nb7v904m_set_loss_profile_match(me,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D);
-	}
-
-	return rv;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-static const struct ec_response_keybd_config keybd1 = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad and no screenlock key */
-};
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	/*
-	 * Future boards should use fw_config if needed.
-	 */
-
-	return &keybd1;
-}
diff --git a/board/sasuke/board.h b/board/sasuke/board.h
deleted file mode 100644
index 4d70cda5ab..0000000000
--- a/board/sasuke/board.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-#undef GPIO_VOLUME_UP_L
-#undef GPIO_VOLUME_DOWN_L
-#undef CONFIG_VOLUME_BUTTONS
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGE_RAMP_HW
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
-
-/* Keyboard */
-
-/* LED */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
-
-
-/* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_NB7V904M
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_PS8743
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-#define CONFIG_USB_PD_COMM_LOCKED
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-#undef PD_POWER_SUPPLY_TURN_ON_DELAY
-#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-/* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
-/* USB Type A Features */
-#define USB_PORT_COUNT 1
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A0_5V_SUB
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/*
- * I2C pin names for baseboard
- *
- * Note: these lines will be set as i2c on start-up, but this should be
- * okay since they're ODL.
- */
-#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
-#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
-
-#define CONFIG_MATH_UTIL
-
-/*
- * There is ccd connection issue on board id = 2.
- * NB7V904M is needed to be active to resolve this.
- */
-#define CONFIG_NB7V904M_LPM_OVERRIDE
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum temp_sensor_id {
-        TEMP_SENSOR_1,
-        TEMP_SENSOR_2,
-        TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SDI,
-	BATTERY_SWD,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/sasuke/build.mk b/board/sasuke/build.mk
deleted file mode 100644
index cd002a20e7..0000000000
--- a/board/sasuke/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/sasuke/cbi_ssfc.c b/board/sasuke/cbi_ssfc.c
deleted file mode 100644
index de5568005e..0000000000
--- a/board/sasuke/cbi_ssfc.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
-
-enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.usb_ss_mux;
-}
diff --git a/board/sasuke/cbi_ssfc.h b/board/sasuke/cbi_ssfc.h
deleted file mode 100644
index af47a1c2cd..0000000000
--- a/board/sasuke/cbi_ssfc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-/*
- * USB SuperSpeed Mux (Bits 6-8)
- */
-enum ec_ssfc_usb_ss_mux {
-	SSFC_USB_SS_MUX_DEFAULT = 0,
-	SSFC_USB_SS_MUX_PS8743 = 1,
-	SSFC_USB_SS_MUX_PI3USBX532 = 2,
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t usb_ss_mux : 3;
-		uint32_t reserved_2 : 23;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-/**
- * Get the USB SuperSpeed Mux type from SSFC_CONFIG
- *
- * @return the USB SuperSpeed Mux type
- */
-enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasuke/ec.tasklist b/board/sasuke/ec.tasklist
deleted file mode 100644
index a867bdbbae..0000000000
--- a/board/sasuke/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/sasuke/gpio.inc b/board/sasuke/gpio.inc
deleted file mode 100644
index 4b970f9798..0000000000
--- a/board/sasuke/gpio.inc
+++ /dev/null
@@ -1,142 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
-
-/* Extra Sub-board I/O pins */
-GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-GPIO(LED_R_ODL,		PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(LED_G_ODL,		PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(LED_B_ODL,		PIN(C, 2), GPIO_OUT_HIGH)
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-GPIO(EN_USB_A0_5V_SUB,       PIN(9, 7), GPIO_OUT_LOW) /* Don't limit USB-A charging by default - all ports */
-GPIO(EN_USB_A0_VBUS,         PIN(4, 1), GPIO_OUT_LOW) /* Enable USB-A charging - all ports */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)   /* I2C7 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO00_NC, PIN(0, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO50_NC, PIN(5, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO56_NC, PIN(5, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO60_NC, PIN(6, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO63_NC, PIN(6, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO73_NC, PIN(7, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO80_NC, PIN(8, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIO95_NC, PIN(9, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOA2_NC, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_DOWN)
diff --git a/board/sasuke/led.c b/board/sasuke/led.c
deleted file mode 100644
index 67d0889831..0000000000
--- a/board/sasuke/led.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for sasuke 
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* sasuke : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-       					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-        }
-
-	if (color == EC_LED_COLOR_BLUE)
-	{
-                gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-        }
-
-	/* Battery leds must be turn off when blue led is on
-	 * because casta has 3-in-1 led.
-	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/sasuke/usb_pd_policy.c b/board/sasuke/usb_pd_policy.c
deleted file mode 100644
index 3190595596..0000000000
--- a/board/sasuke/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/sasuke/vif_override.xml b/board/sasuke/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/sasuke/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/sasukette/battery.c b/board/sasukette/battery.c
deleted file mode 100644
index 652c04a651..0000000000
--- a/board/sasukette/battery.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "common.h"
-#include "util.h"
-
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
-
-/*
- * Battery info for all sasukette battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SDI Battery Information */
-	[BATTERY_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SDI",
-			.device_name = "4402D51",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x00,
-				.reg_mask = 0xc000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0xc000,
-				.cfet_off_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 200,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int current;
-	int voltage;
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c;
-	const struct battery_info *batt_info;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *     ZONE_0  ZONE_1   ZONE_2  ZONE_3
-	 * ---+------+--------+--------+------+--- Temperature (C)
-	 *    0      5        12       45     50
-	 */
-	enum {
-		TEMP_ZONE_0, /* 0 <= bat_temp_c <= 5 */
-		TEMP_ZONE_1, /* 5 < bat_temp_c <= 12 */
-		TEMP_ZONE_2, /* 12 < bat_temp_c <= 45 */
-		TEMP_ZONE_3, /* 45 < bat_temp_c <= 50 */
-		TEMP_ZONE_COUNT,
-		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
-	} temp_zone;
-
-	/*
-	 * Precharge must be executed when communication is failed on
-	 * dead battery.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-		return 0;
-
-	current = curr->requested_current;
-	voltage = curr->requested_voltage;
-	bat_temp_c = curr->batt.temperature - 2731;
-	batt_info = battery_get_info();
-
-	/*
-	 * If the temperature reading is bad, assume the temperature
-	 * is out of allowable range.
-	 */
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < 0) || (bat_temp_c > 500))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else if (bat_temp_c <= 50)
-		temp_zone = TEMP_ZONE_0;
-	else if (bat_temp_c <= 120)
-		temp_zone = TEMP_ZONE_1;
-	else if (bat_temp_c <= 450)
-		temp_zone = TEMP_ZONE_2;
-	else
-		temp_zone = TEMP_ZONE_3;
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-
-	case TEMP_ZONE_1:
-		voltage += 100;
-		current = CHARGING_CURRENT_MA_SAFE;
-		break;
-
-	case TEMP_ZONE_2:
-		voltage += 100;
-		break;
-
-	case TEMP_ZONE_3:
-		voltage = CHARGING_VOLTAGE_MV_SAFE;
-		break;
-
-	case TEMP_OUT_OF_RANGE:
-		/* Don't charge if outside of allowable temperature range */
-		current = 0;
-		voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		if (curr->state != ST_DISCHARGE)
-			curr->state = ST_IDLE;
-		break;
-	}
-
-	if (voltage > batt_info->voltage_max)
-		voltage = batt_info->voltage_max;
-
-	curr->requested_voltage = voltage;
-	curr->requested_current = MIN(curr->requested_current, current);
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-				uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-				uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/sasukette/board.c b/board/sasukette/board.c
deleted file mode 100644
index a55967d816..0000000000
--- a/board/sasukette/board.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Sasukette configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cros_board_info.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "math_util.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	}
-};
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	}
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	}
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	}
-};
-
-static uint32_t board_id;
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* modify AC DC prochot value */
-	isl923x_set_ac_prochot(CHARGER_SOLO, 4096);
-	isl923x_set_dc_prochot(CHARGER_SOLO, 6000);
-
-	cbi_get_board_version(&board_id);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 *
-	 * b:186335659: In order to solve the power consumption problem of
-	 * hibernate，HW solution is adopted after board id 3 to solve the
-	 * problem that AC cannot wake up hibernate mode.
-	 */
-	if (board_id > 2)
-		raa489000_hibernate(0, true);
-	else
-		raa489000_hibernate(0, false);
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-	raa489000_set_output_current(port, rp);
-}
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/sasukette/board.h b/board/sasukette/board.h
deleted file mode 100644
index a1d987aaf3..0000000000
--- a/board/sasukette/board.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Sasukette board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-#undef GPIO_VOLUME_UP_L
-#undef GPIO_VOLUME_DOWN_L
-#undef CONFIG_VOLUME_BUTTONS
-#undef CONFIG_I2C_DEBUG
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* LED */
-#define CONFIG_LED_COMMON
-#define CONFIG_LED_ONOFF_STATES
-#define GPIO_BAT_LED_RED_L GPIO_LED_R_ODL
-#define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
-#define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15*/
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/sasukette/build.mk b/board/sasukette/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/sasukette/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/sasukette/cbi_ssfc.c b/board/sasukette/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/sasukette/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/sasukette/cbi_ssfc.h b/board/sasukette/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/sasukette/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasukette/ec.tasklist b/board/sasukette/ec.tasklist
deleted file mode 100644
index bb4d9c6a61..0000000000
--- a/board/sasukette/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE)
diff --git a/board/sasukette/gpio.inc b/board/sasukette/gpio.inc
deleted file mode 100644
index 396a5595fa..0000000000
--- a/board/sasukette/gpio.inc
+++ /dev/null
@@ -1,139 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 	PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,		PIN(L, 5), GPIO_ODR_HIGH)
-
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-GPIO(LTE_EN, 			PIN(C, 3), GPIO_OUT_LOW)
-GPIO(WWAN_CONFIG, 		PIN(A, 0), GPIO_INPUT |GPIO_PULL_UP)
-
-/* LED */
-GPIO(LED_R_ODL,			PIN(A, 1), GPIO_ODR_HIGH)
-GPIO(LED_G_ODL,			PIN(A, 2), GPIO_ODR_HIGH)
-GPIO(LED_B_ODL,			PIN(A, 3), GPIO_ODR_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOB5_NC, PIN(B, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE6_NC, PIN(E, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOE7_NC, PIN(E, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF6_NC, PIN(F, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF7_NC, PIN(F, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOI6_NC, PIN(I, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOI7_NC, PIN(I, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ0_NC, PIN(J, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 EEPROM */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 BATTERY */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 USB_C0 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)    /* ADC15:TEMP_SENSOR3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
diff --git a/board/sasukette/led.c b/board/sasukette/led.c
deleted file mode 100644
index 28643a7b87..0000000000
--- a/board/sasukette/led.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Sasukette
- *
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Sasukette : There are 3 leds for AC, Battery and Power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-			{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	if (color == EC_LED_COLOR_BLUE) {
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
-	} else {
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	/* Don't set led if led_auto_control is disabled. */
-	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-		return;
-	}
-
-	/* Battery leds must be turn off when blue led is on
-	 * because the led is 3-in-1 led.
-	 */
-	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		return;
-	}
-
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_ON_LVL); /*green*/
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-			!brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L,
-			!brightness[EC_LED_COLOR_RED]);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-			!brightness[EC_LED_COLOR_BLUE]);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/sasukette/usb_pd_policy.c b/board/sasukette/usb_pd_policy.c
deleted file mode 100644
index b0e1098e4d..0000000000
--- a/board/sasukette/usb_pd_policy.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/sasukette/vif_override.xml b/board/sasukette/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/sasukette/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/scarlet/battery.c b/board/scarlet/battery.c
deleted file mode 100644
index 0be4cc93e2..0000000000
--- a/board/scarlet/battery.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/battery/max17055.h"
-#include "driver/charger/rt946x.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "util.h"
-
-/*
- * AE-Tech battery pack has two charging phases when operating
- * between 10 and 20C
- */
-#define CHARGE_PHASE_CHANGE_TRIP_VOLTAGE_MV 4200
-#define CHARGE_PHASE_CHANGE_HYSTERESIS_MV 50
-#define CHARGE_PHASE_CHANGED_CURRENT_MA 1800
-
-#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT
-
-static uint8_t batt_id = 0xff;
-
-/* Do not change the enum values. We directly use strap gpio level to index. */
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_AETECH,
-	BATTERY_COUNT
-};
-
-static const struct battery_info info[] = {
-	[BATTERY_SIMPLO] = {
-		.voltage_max		= 4400,
-		.voltage_normal		= 3840,
-		.voltage_min		= 3000,
-		.precharge_current	= 256,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 60,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 60,
-	},
-	[BATTERY_AETECH] = {
-		.voltage_max		= 4350,
-		.voltage_normal		= 3800,
-		.voltage_min		= 3000,
-		.precharge_current	= 700,
-		.start_charging_min_c	= 0,
-		.start_charging_max_c	= 45,
-		.charging_min_c		= 0,
-		.charging_max_c		= 45,
-		.discharging_min_c	= -20,
-		.discharging_max_c	= 55,
-	}
-};
-
-static const struct max17055_batt_profile batt_profile[] = {
-	[BATTERY_SIMPLO] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x221e, /* 8734mAh */
-		.ichg_term		= 0x589, /* 443 mA */
-		/* Empty voltage = 3000mV, Recovery voltage = 3600mV */
-		.v_empty_detect		= 0x965a,
-		.learn_cfg		= 0x4406,
-		.dpacc			= 0x0c7a,
-		.rcomp0			= 0x0062,
-		.tempco			= 0x1327,
-		.qr_table00		= 0x1680,
-		.qr_table10		= 0x0900,
-		.qr_table20		= 0x0280,
-		.qr_table30		= 0x0280,
-	},
-	[BATTERY_AETECH] = {
-		.is_ez_config		= 0,
-		.design_cap		= 0x232f, /* 9007mAh */
-		.ichg_term		= 0x0240, /* 180mA */
-		/* Empty voltage = 2700mV, Recovery voltage = 3280mV */
-		.v_empty_detect		= 0x8752,
-		.learn_cfg		= 0x4476,
-		.dpacc			= 0x0c7b,
-		.rcomp0			= 0x0077,
-		.tempco			= 0x1d3f,
-		.qr_table00		= 0x1200,
-		.qr_table10		= 0x0900,
-		.qr_table20		= 0x0480,
-		.qr_table30		= 0x0480,
-	},
-};
-
-const struct battery_info *battery_get_info(void)
-{
-	if (batt_id >= BATTERY_COUNT)
-		batt_id = gpio_get_level(GPIO_BATT_ID);
-
-	return &info[batt_id];
-}
-
-const struct max17055_batt_profile *max17055_get_batt_profile(void)
-{
-	if (batt_id >= BATTERY_COUNT)
-		batt_id = gpio_get_level(GPIO_BATT_ID);
-
-	return &batt_profile[batt_id];
-}
-
-int board_cut_off_battery(void)
-{
-	return rt946x_cutoff_battery();
-}
-
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	if (battery_is_present() == BP_YES)
-		return BATTERY_NOT_DISCONNECTED;
-	return BATTERY_DISCONNECTED;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/* battery temp in 0.1 deg C */
-	int bat_temp_c = curr->batt.temperature - 2731;
-
-	/*
-	 * Keep track of battery temperature range:
-	 *
-	 *        ZONE_0   ZONE_1     ZONE_2
-	 * -----+--------+--------+------------+----- Temperature (C)
-	 *      t0       t1       t2           t3
-	 */
-	enum {
-		TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */
-		TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */
-		TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */
-		TEMP_ZONE_COUNT
-	} temp_zone;
-
-	static struct {
-		int temp_min; /* 0.1 deg C */
-		int temp_max; /* 0.1 deg C */
-		int desired_current; /* mA */
-		int desired_voltage; /* mV */
-	} temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = {
-		[BATTERY_SIMPLO] = {
-			{0, 150, 1772, 4376}, /* TEMP_ZONE_0 */
-			{150, 450, 4000, 4376}, /* TEMP_ZONE_1 */
-			{450, 600, 4000, 4100}, /* TEMP_ZONE_2 */
-		},
-		[BATTERY_AETECH] = {
-			{0, 100, 900, 4200}, /* TEMP_ZONE_0 */
-			{100, 200, 2700, 4350}, /* TEMP_ZONE_1 */
-			/*
-			 * TODO(b:70287349): Limit the charging current to
-			 * 2A unless AE-Tech fix their battery pack.
-			 */
-			{200, 450, 2000, 4350}, /* TEMP_ZONE_2 */
-		}
-	};
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT);
-
-	static int charge_phase = 1;
-	static uint8_t quirk_batt_update;
-
-	/*
-	 * This is a quirk for old Simplo battery to clamp
-	 * charging current to 3A.
-	 */
-	if ((board_get_version() <= 4) && !quirk_batt_update) {
-		temp_zones[BATTERY_SIMPLO][TEMP_ZONE_1].desired_current = 3000;
-		temp_zones[BATTERY_SIMPLO][TEMP_ZONE_2].desired_current = 3000;
-		quirk_batt_update = 1;
-	}
-
-	if (batt_id >= BATTERY_COUNT)
-		batt_id = gpio_get_level(GPIO_BATT_ID);
-
-	if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) ||
-	    (bat_temp_c < temp_zones[batt_id][0].temp_min) ||
-	    (bat_temp_c >= temp_zones[batt_id][TEMP_ZONE_COUNT - 1].temp_max))
-		temp_zone = TEMP_OUT_OF_RANGE;
-	else {
-		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
-			if (bat_temp_c <
-				temp_zones[batt_id][temp_zone].temp_max)
-				break;
-		}
-	}
-
-	if (curr->state != ST_CHARGE) {
-		charge_phase = 1;
-		return 0;
-	}
-
-	switch (temp_zone) {
-	case TEMP_ZONE_0:
-	case TEMP_ZONE_2:
-		curr->requested_current =
-			temp_zones[batt_id][temp_zone].desired_current;
-		curr->requested_voltage =
-			temp_zones[batt_id][temp_zone].desired_voltage;
-		break;
-	case TEMP_ZONE_1:
-		/* No phase change for Simplo battery pack */
-		if (batt_id == BATTERY_SIMPLO)
-			charge_phase = 0;
-		/*
-		 * If AE-Tech battery pack is used and the voltage reading
-		 * is bad, let's be conservative and assume change_phase == 1.
-		 */
-		else if (curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)
-			charge_phase = 1;
-		else {
-			if (curr->batt.voltage <
-			    (CHARGE_PHASE_CHANGE_TRIP_VOLTAGE_MV -
-			     CHARGE_PHASE_CHANGE_HYSTERESIS_MV))
-				charge_phase = 0;
-			else if (curr->batt.voltage >
-				 CHARGE_PHASE_CHANGE_TRIP_VOLTAGE_MV)
-				charge_phase = 1;
-		}
-
-		curr->requested_voltage =
-			temp_zones[batt_id][temp_zone].desired_voltage;
-
-		curr->requested_current = (charge_phase) ?
-			CHARGE_PHASE_CHANGED_CURRENT_MA :
-			temp_zones[batt_id][temp_zone].desired_current;
-		break;
-	case TEMP_OUT_OF_RANGE:
-		curr->requested_current = curr->requested_voltage = 0;
-		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-		curr->state = ST_IDLE;
-		break;
-	}
-
-	/*
-	 * When the charger says it's done charging, even if fuel gauge says
-	 * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with
-	 * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI
-	 * and battery LED indicate full charge.
-	 */
-	if (rt946x_is_charge_done()) {
-		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
-						 curr->batt.state_of_charge);
-		/*
-		 * This is a workaround for b:78792296. When AP is off and
-		 * charge termination is detected, we disable idle mode.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			disable_idle();
-		else
-			enable_idle();
-	}
-
-	return 0;
-}
-
-static void board_enable_idle(void)
-{
-	enable_idle();
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, board_enable_idle, HOOK_PRIO_DEFAULT);
-
-static void board_charge_termination(void)
-{
-	static uint8_t te;
-	/* Enable charge termination when we are sure battery is present. */
-	if (!te && battery_is_present() == BP_YES) {
-		if (!rt946x_enable_charge_termination(1))
-			te = 1;
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
-	     HOOK_PRIO_DEFAULT);
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/scarlet/board.c b/board/scarlet/board.c
deleted file mode 100644
index f109d0ada3..0000000000
--- a/board/scarlet/board.c
+++ /dev/null
@@ -1,459 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/charger/rt946x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/temp_sensor/tmp432.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "temp_sensor.h"
-#include "temp_sensor_chip.h"
-#include "timer.h"
-#include "thermal.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-static void overtemp_interrupt(enum gpio_signal signal)
-{
-	CPRINTS("AP wants shutdown");
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
-}
-
-static void warm_reset_request_interrupt(enum gpio_signal signal)
-{
-	CPRINTS("AP wants warm reset");
-	chipset_reset(CHIPSET_RESET_AP_REQ);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"charger", I2C_PORT_CHARGER,   400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,     1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = RT946X_ADDR_FLAGS,
-		.drv = &rt946x_drv,
-	},
-};
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-#ifdef CONFIG_TEMP_SENSOR_TMP432
-/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
-const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * Thermal limits for each temp sensor. All temps are in degrees K. Must be in
- * same order as enum temp_sensor_id. To always ignore any temp, use 0.
- */
-struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-#endif
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI_ACCEL_CS_L },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-
-void board_reset_pd_mcu(void)
-{
-}
-
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
-{
-	if ((curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
-		(curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH))
-		return CRITICAL_SHUTDOWN_CUTOFF;
-	else
-		return CRITICAL_SHUTDOWN_IGNORE;
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_L))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	switch (charge_port) {
-	case 0:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int extpower_is_present(void)
-{
-	/*
-	 * The charger will indicate VBUS presence if we're sourcing 5V,
-	 * so exclude such ports.
-	 */
-	if (board_vbus_source_enabled(0))
-		return 0;
-	else
-		return tcpm_check_vbus_level(0, VBUS_PRESENT);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	if (port)
-		panic("Invalid charge port\n");
-
-	return rt946x_is_vbus_ready();
-}
-
-static void board_spi_enable(void)
-{
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-
-static void board_init(void)
-{
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_L);
-
-	/* Enable charger interrupts */
-	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
-
-	/* Enable reboot / shutdown control inputs from AP */
-	gpio_enable_interrupt(GPIO_WARM_RESET_REQ);
-	gpio_enable_interrupt(GPIO_AP_OVERTEMP);
-
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_L);
-
-	/* Enable interrupt for the camera vsync. */
-	gpio_enable_interrupt(GPIO_SYNC_INT);
-
-	/* Set SPI2 pins to high speed */
-	/* pins D0/D1/D3/D4 */
-	STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf;
-
-	/* Sensor Init */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		board_spi_enable();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_config_pre_init(void)
-{
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-	/*
-	 * Remap USART1 and SPI2 DMA:
-	 *
-	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
-	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
-	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
-}
-
-enum scarlet_board_version {
-	BOARD_VERSION_UNKNOWN = -1,
-	BOARD_VERSION_REV0 = 0,
-	BOARD_VERSION_REV1 = 1,
-	BOARD_VERSION_REV2 = 2,
-	BOARD_VERSION_REV3 = 3,
-	BOARD_VERSION_REV4 = 4,
-	BOARD_VERSION_REV5 = 5,
-	BOARD_VERSION_REV6 = 6,
-	BOARD_VERSION_REV7 = 7,
-	BOARD_VERSION_REV8 = 8,
-	BOARD_VERSION_REV9 = 9,
-	BOARD_VERSION_REV10 = 10,
-	BOARD_VERSION_REV11 = 11,
-	BOARD_VERSION_REV12 = 12,
-	BOARD_VERSION_REV13 = 13,
-	BOARD_VERSION_REV14 = 14,
-	BOARD_VERSION_REV15 = 15,
-	BOARD_VERSION_COUNT,
-};
-
-struct {
-	enum scarlet_board_version version;
-	int expect_mv;
-} const scarlet_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
-	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
-	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
-	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
-	{ BOARD_VERSION_REV13, 1576 }, /* 47K   , 330K ohm */
-	{ BOARD_VERSION_REV14, 1684 }, /* 47K   , 680K ohm */
-	{ BOARD_VERSION_REV15, 1800 }, /* 56K   , NC */
-};
-BUILD_ASSERT(ARRAY_SIZE(scarlet_boards) == BOARD_VERSION_COUNT);
-
-#define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
-
-int board_get_version(void)
-{
-	static int version = BOARD_VERSION_UNKNOWN;
-	int mv;
-	int i;
-
-	if (version != BOARD_VERSION_UNKNOWN)
-		return version;
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
-	/* Wait to allow cap charge */
-	msleep(10);
-	mv = adc_read_channel(ADC_BOARD_ID);
-
-	if (mv == ADC_READ_ERROR)
-		mv = adc_read_channel(ADC_BOARD_ID);
-
-	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 1);
-
-	for (i = 0; i < BOARD_VERSION_COUNT; ++i) {
-		if (mv < scarlet_boards[i].expect_mv + THRESHOLD_MV) {
-			version = scarlet_boards[i].version;
-			break;
-		}
-	}
-
-	/*
-	 * Disable ADC module after we detect the board version,
-	 * since this is the only thing ADC module needs to do
-	 * for this board.
-	 */
-	if (version != BOARD_VERSION_UNKNOWN)
-		adc_disable();
-
-	return version;
-}
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_base_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* Enable accel in S0 */
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-			 .ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[VSYNC] = {
-	 .name = "Camera vsync",
-	 .active_mask = SENSOR_ACTIVE_S0,
-	 .chip = MOTIONSENSE_CHIP_GPIO,
-	 .type = MOTIONSENSE_TYPE_SYNC,
-	 .location = MOTIONSENSE_LOC_CAMERA,
-	 .drv = &sync_drv,
-	 .default_range = 0,
-	 .min_frequency = 0,
-	 .max_frequency = 1,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-int board_allow_i2c_passthru(int port)
-{
-	return (port == I2C_PORT_VIRTUAL_BATTERY);
-}
diff --git a/board/scarlet/board.h b/board/scarlet/board.h
deleted file mode 100644
index 2880968ddc..0000000000
--- a/board/scarlet/board.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Scarlet */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Free up flash space */
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#define CONFIG_USB_PD_DEBUG_LEVEL 0
-
-/* Optional modules */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_CHIPSET_RK3399
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_RTC
-#define CONFIG_EMULATED_SYSRQ
-#undef  CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_RTC
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_IDLE_LIMITED
-#define CONFIG_POWER_COMMON
-#define CONFIG_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_STM_HWTIMER32
-/* Source RTCCLK from external 32.768kHz source on PC15/OSC32_IN. */
-#define CONFIG_STM32_CLOCK_LSE
-#define CONFIG_SWITCH
-#define CONFIG_WATCHDOG_HELP
-
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-
-#undef  CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_RX_DMA
-
-/* Enable a different power-on sequence than the one on gru */
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-/* Optional features */
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-#define CONFIG_CHARGER_ILIM_PIN_DISABLED
-#define CONFIG_FORCE_CONSOLE_RESUME
-#define CONFIG_HOST_COMMAND_STATUS
-
-/* Required for FAFT */
-#define CONFIG_CMD_BUTTON
-
-/* By default, set hcdebug to off */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_LTO
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_SOFTWARE_PANIC
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VOLUME_BUTTONS
-
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_RT9467
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_OTG
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_MUX_VIRTUAL
-
-/* Increase tx buffer size, as we'd like to stream EC log to AP. */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Motion Sensors */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-/* Camera VSYNC */
-#define CONFIG_SYNC
-#define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-/* To be able to indicate the device is in tablet mode. */
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES 10
-
-/* USB PD config */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_COMM_LOCKED
-
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_RETRY_NACK
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_MAX17055
-
-/* Battery parameters for max17055 ModelGauge m5 algorithm. */
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
-#define BATTERY_DESIRED_CHARGING_CURRENT    4000  /* mA */
-
-#define CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-#define BAT_MAX_DISCHG_CURRENT	5000 /* mA */
-
-#define CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-#define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */
-
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
-
-/* Timer selection */
-#define TIM_CLOCK32  2
-#define TIM_WATCHDOG 7
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_BATTFAKE
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_MD
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_TIMERINFO
-
-#define CONFIG_TASK_PROFILING
-
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_BATTERY  0
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_TCPC0    1
-
-/* Route sbs host requests to virtual battery driver */
-#define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-/* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	PP1250_S3_PWR_GOOD = 0,
-	PP900_S0_PWR_GOOD,
-	AP_PWR_GOOD,
-	SUSPEND_DEASSERTED,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	VSYNC,
-	SENSOR_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/scarlet/build.mk b/board/scarlet/build.mk
deleted file mode 100644
index f2966fea6a..0000000000
--- a/board/scarlet/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-
-board-y=battery.o board.o usb_pd_policy.o led.o
diff --git a/board/scarlet/ec.tasklist b/board/scarlet/ec.tasklist
deleted file mode 100644
index 1548272184..0000000000
--- a/board/scarlet/ec.tasklist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE)
-
diff --git a/board/scarlet/gpio.inc b/board/scarlet/gpio.inc
deleted file mode 100644
index 9c45295a7f..0000000000
--- a/board/scarlet/gpio.inc
+++ /dev/null
@@ -1,102 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-GPIO_INT(SPI1_NSS,         PIN(A, 15), GPIO_INT_BOTH,
-         spi_event)
-GPIO_INT(USB_C0_PD_INT_L,  PIN(C, 13), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(VOLUME_UP_L,      PIN(D, 10), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,    PIN(E, 11), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt)
-GPIO_INT(POWER_BUTTON_L,   PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt)
-GPIO_INT(PP1250_S3_PG,     PIN(D, 8),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_signal_interrupt)
-GPIO_INT(PP900_S0_PG,      PIN(D, 9),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_signal_interrupt)
-GPIO_INT(AP_EC_S3_S0_L,    PIN(C, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,   PIN(E, 1),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         warm_reset_request_interrupt)
-GPIO_INT(AP_OVERTEMP,      PIN(E, 4),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         overtemp_interrupt)
-GPIO_INT(ACCEL_INT_L,      PIN(D, 14), GPIO_INT_FALLING | GPIO_SEL_1P8V,
-         bmi160_interrupt)
-GPIO_INT(SYNC_INT,         PIN(A, 12), GPIO_INT_RISING | GPIO_PULL_DOWN,
-         sync_interrupt)
-GPIO_INT(CHARGER_INT_L,    PIN(E, 6),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         rt946x_interrupt)
-
-/* Voltage rails control pins */
-GPIO(PP1800_S0_EN,         PIN(D, 11), GPIO_OUT_LOW)
-GPIO(AP_CORE_EN,           PIN(C, 1),  GPIO_OUT_LOW)
-GPIO(PP3300_S0_EN,         PIN(E, 12), GPIO_OUT_LOW)
-GPIO(PP1800_USB_EN,        PIN(C, 4),  GPIO_OUT_LOW)
-GPIO(PP900_S0_EN,          PIN(E, 8),  GPIO_OUT_LOW)
-GPIO(PP1250_S3_EN,         PIN(D, 13), GPIO_OUT_LOW)
-GPIO(PP1800_S3_EN,         PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(PP3300_S3_EN,         PIN(E, 2),  GPIO_OUT_LOW)
-GPIO(PP900_S3_EN,          PIN(E, 10), GPIO_OUT_LOW)
-
-GPIO(PP3300_REDUCE_EFF_L,  PIN(D, 12), GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C0_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C0_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C1_SCL,             PIN(B, 10), GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 11), GPIO_INPUT)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-
-/* SPI sensors */
-GPIO(SPI_ACCEL_CS_L,       PIN(D, 0),  GPIO_OUT_HIGH)
-
-/* Scarlet LEDs */
-GPIO(BAT_LED_GREEN,        PIN(E, 9),  GPIO_ODR_HIGH)
-GPIO(BAT_LED_RED,          PIN(E, 13), GPIO_ODR_HIGH)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(E, 5),  GPIO_INPUT)
-/* TODO(philipchen): Add an interrupt handler once CCD is fully developed. */
-GPIO(CCD_MODE_ODL,         PIN(C, 5),  GPIO_INPUT | GPIO_PULL_UP)
-/* Non-INT power signal pin */
-GPIO(AP_CORE_PG,           PIN(D, 7),  GPIO_INPUT | GPIO_PULL_UP)
-/* Battery ID strap pin */
-GPIO(BATT_ID,              PIN(C, 2),  GPIO_INPUT | GPIO_PULL_UP)
-
-
-
-/* Other output pins */
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH)
-GPIO(SYS_RST_L,            PIN(C, 8),  GPIO_ODR_LOW)
-GPIO(EC_INT_L,             PIN(E, 3),  GPIO_ODR_HIGH)
-GPIO(EC_BOARD_ID_EN_L,     PIN(F, 1),  GPIO_ODR_HIGH)
-GPIO(USB_C0_DISCHARGE,     PIN(A, 11), GPIO_OUT_LOW)
-GPIO(PCA9468_EN,           PIN(E, 15), GPIO_OUT_LOW)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        0)
-/* I2C MASTER: PB10/11 */
-ALTERNATE(PIN_MASK(B, 0x0c00), 1, MODULE_I2C,        0)
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-/* SPI MASTER: PD1/3/4 */
-ALTERNATE(PIN_MASK(D, 0x001a), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/scarlet/led.c b/board/scarlet/led.c
deleted file mode 100644
index d4c758cdcc..0000000000
--- a/board/scarlet/led.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Scarlet board.
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "lid_switch.h"
-#include "pwm.h"
-#include "util.h"
-
-/* LEDs on Scarlet are active low. */
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_AMBER,
-	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int bat_led_set_color(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		break;
-	case LED_RED:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		break;
-	case LED_GREEN:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static void scarlet_led_set_battery(void)
-{
-	static int battery_second;
-	uint32_t chflags = charge_get_flags();
-
-	battery_second++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		bat_led_set_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
-		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
-		else if (charge_get_percent() >= BATTERY_LEVEL_NEAR_FULL &&
-		    (chflags & CHARGE_FLAG_EXTERNAL_POWER))
-			bat_led_set_color(LED_GREEN);
-		else
-			bat_led_set_color(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		bat_led_set_color(LED_RED);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		bat_led_set_color(LED_GREEN);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		gpio_set_level(GPIO_BAT_LED_RED,
-			       (brightness[EC_LED_COLOR_RED] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_GREEN,
-			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
-		return EC_SUCCESS;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-/* Called by hook task every 1 sec */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		scarlet_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		return;
-	}
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-	bat_led_set_color(state ? LED_AMBER : LED_OFF);
-}
diff --git a/board/scarlet/usb_pd_policy.c b/board/scarlet/usb_pd_policy.c
deleted file mode 100644
index cba4540ecd..0000000000
--- a/board/scarlet/usb_pd_policy.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charger.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/rt946x.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint8_t vbus_en;
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-
-	pd_set_vbus_discharge(port, 0);
-	/* Provide VBUS */
-	vbus_en = 1;
-	charger_enable_otg_power(CHARGER_SOLO, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en;
-	/* Disable VBUS */
-	vbus_en = 0;
-	charger_enable_otg_power(CHARGER_SOLO, 0);
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * VCONN is provided directly by the battery (PPVAR_SYS)
-	 * but use the same rules as power swap.
-	 */
-	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
-}
diff --git a/board/scarlet/vif_override.xml b/board/scarlet/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/scarlet/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/scout/board.c b/board/scout/board.c
deleted file mode 100644
index 7c87f97ec8..0000000000
--- a/board/scout/board.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "chipset.h"
-#include "common.h"
-#include "core/cortex-m/cpu.h"
-#include "cros_board_info.h"
-#include "driver/ina3221.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/cometlake-discrete.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_common.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-static void power_monitor(void);
-DECLARE_DEFERRED(power_monitor);
-
-static uint8_t usbc_overcurrent;
-static int32_t base_5v_power;
-
-/*
- * Power usage for each port as measured or estimated.
- * Units are milliwatts (5v x ma current)
- */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
-
-/*
- * Update the 5V power usage, assuming no throttling,
- * and invoke the power monitoring.
- */
-static void update_5v_usage(void)
-{
-	int front_ports = 0;
-	/*
-	 * Recalculate the 5V load, assuming no throttling.
-	 */
-	base_5v_power = PWR_BASE_LOAD;
-	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
-		front_ports++;
-		base_5v_power += PWR_FRONT_LOW;
-	}
-	/*
-	 * Only 1 front port can run higher power at a time.
-	 */
-	if (front_ports > 0)
-		base_5v_power += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-	if (!gpio_get_level(GPIO_USB_A2_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_USB_A3_OC_ODL))
-		base_5v_power += PWR_REAR;
-	if (!gpio_get_level(GPIO_HDMI_CONN0_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (!gpio_get_level(GPIO_HDMI_CONN1_OC_ODL))
-		base_5v_power += PWR_HDMI;
-	if (usbc_overcurrent)
-		base_5v_power += PWR_C_HIGH;
-	/*
-	 * Invoke the power handler immediately.
-	 */
-	hook_call_deferred(&power_monitor_data, 0);
-}
-DECLARE_DEFERRED(update_5v_usage);
-/*
- * Start power monitoring after ADCs have been initialised.
- */
-DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
-
-static void port_ocp_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&update_5v_usage_data, 0);
-}
-
-/******************************************************************************/
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-};
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{"ina",     I2C_PORT_INA,     400, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"ppc0",    I2C_PORT_PPC0,    400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"scaler",  I2C_PORT_SCALER,  400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"power",   I2C_PORT_POWER,   400, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct adc_t adc_channels[] = {
-	[ADC_SNS_PP3300] = {
-		/*
-		 * 4700/5631 voltage divider: can take the value out of range
-		 * for 32-bit signed integers, so truncate to 470/563 yielding
-		 * <0.1% error and a maximum intermediate value of 1623457792,
-		 * which comfortably fits in int32.
-		 */
-		.name = "SNS_PP3300",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT * 563,
-		.factor_div = (ADC_READ_MAX + 1) * 470,
-	},
-	[ADC_SNS_PP1050] = {
-		.name = "SNS_PP1050",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_VBUS] = {  /* 5/39 voltage divider */
-		.name = "VBUS",
-		.input_ch = NPCX_ADC_CH4,
-		.factor_mul = ADC_MAX_VOLT * 39,
-		.factor_div = (ADC_READ_MAX + 1) * 5,
-	},
-	[ADC_PPVAR_IMON] = {  /* 500 mV/A */
-		.name = "PPVAR_IMON",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT * 2, /* Milliamps */
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR_1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR_2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CORE] = {
-		.name = "Core",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1,
-	},
-	[TEMP_SENSOR_WIFI] = {
-		.name = "Wifi",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2500,
-	.rpm_start = 2500,
-	.rpm_max = 5300,
-};
-
-const struct fan_t fans[] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* Thermal control; drive fan based on temperature sensors. */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(85),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(90),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(89),
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(78),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_CORE] = thermal_a,
-	[TEMP_SENSOR_WIFI] = thermal_a,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/* Power sensors */
-const struct ina3221_t ina3221[] = {
-	{ I2C_PORT_INA, 0x40, { "PP3300_G", "PP5000_A", "PP3300_WLAN" } },
-	{ I2C_PORT_INA, 0x42, { "PP3300_A", "PP3300_SSD", "PP3300_LAN" } },
-	{ I2C_PORT_INA, 0x43, { NULL, "PP1200_U", "PP2500_DRAM" } }
-};
-const unsigned int ina3221_count = ARRAY_SIZE(ina3221);
-
-static uint16_t board_version;
-static uint32_t sku_id;
-static uint32_t fw_config;
-
-static void cbi_init(void)
-{
-	/*
-	 * Load board info from CBI to control per-device configuration.
-	 *
-	 * If unset it's safe to treat the board as a proto, just C10 gating
-	 * won't be enabled.
-	 */
-	uint32_t val;
-
-	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT16_MAX)
-		board_version = val;
-	if (cbi_get_sku_id(&val) == EC_SUCCESS)
-		sku_id = val;
-	if (cbi_get_fw_config(&val) == EC_SUCCESS)
-		fw_config = val;
-	CPRINTS("Board Version: %d, SKU ID: 0x%08x, F/W config: 0x%08x",
-		board_version, sku_id, fw_config);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_init(void)
-{
-	uint8_t *memmap_batt_flags;
-
-	/* Override some GPIO interrupt priorities.
-	 *
-	 * These interrupts are timing-critical for AP power sequencing, so we
-	 * increase their NVIC priority from the default of 3. This affects
-	 * whole MIWU groups of 8 GPIOs since they share an IRQ.
-	 *
-	 * Latency at the default priority level can be hundreds of
-	 * microseconds while other equal-priority IRQs are serviced, so GPIOs
-	 * requiring faster response must be higher priority.
-	 */
-	/* CPU_C10_GATE_L on GPIO6.7: must be ~instant for ~60us response. */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTH_1, 1);
-	/*
-	 * slp_s3_interrupt (GPIOA.5 on WKINTC_0) must respond within 200us
-	 * (tPLT18); less critical than the C10 gate.
-	 */
-	cpu_set_interrupt_priority(NPCX_IRQ_WKINTC_0, 2);
-
-	/* Always claim AC is online, because we don't have a battery. */
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	/*
-	 * For board version < 2, the directly connected recovery
-	 * button is not available.
-	 */
-	if (board_version < 2)
-		button_disable_gpio(GPIO_EC_RECOVERY_BTN_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USB_VBUS,
-};
-
-int64_t get_time_dsw_pwrok(void)
-{
-	/* DSW_PWROK is turned on before EC was powered. */
-	return -20 * MSEC;
-}
-
-int extpower_is_present(void)
-{
-	/* genesis: If the EC is running, then there is external power */
-	return 1;
-}
-
-int board_is_c10_gate_enabled(void)
-{
-	/*
-	 * Puff proto drives EN_PP5000_HDMI from EN_S0_RAILS so we cannot gate
-	 * core rails while in S0 because HDMI should remain powered.
-	 * EN_PP5000_HDMI is a separate EC output on all other boards.
-	 */
-	return board_version != 0;
-}
-
-void board_enable_s0_rails(int enable)
-{
-	/* This output isn't connected on protos; safe to set anyway. */
-	gpio_set_level(GPIO_EN_PP5000_HDMI, enable);
-
-	/*
-	 * Toggle scaler power and its downstream USB devices.
-	 */
-	gpio_set_level(GPIO_EC_SCALER_EN, enable);
-	gpio_set_level(GPIO_PWR_CTRL, enable);
-	gpio_set_level(GPIO_EC_MX8M_ONOFF, enable);
-	gpio_set_level(GPIO_EC_CAM_V3P3_EN, enable);
-
-	gpio_set_level(GPIO_PP3300_TPU_A_EN, enable);
-}
-
-int ec_config_get_usb4_present(void)
-{
-	return !(fw_config & EC_CFG_NO_USB4_MASK);
-}
-
-unsigned int ec_config_get_thermal_solution(void)
-{
-	return (fw_config & EC_CFG_THERMAL_MASK) >> EC_CFG_THERMAL_L;
-}
-
-static void setup_thermal(void)
-{
-	unsigned int table = ec_config_get_thermal_solution();
-	/* Configure Fan */
-	switch (table) {
-	/* Default and table0 use single fan */
-	case 0:
-	default:
-		thermal_params[TEMP_SENSOR_CORE] = thermal_a;
-		thermal_params[TEMP_SENSOR_WIFI] = thermal_a;
-		break;
-	/* Table1 is fanless */
-	case 1:
-		fan_set_count(0);
-		thermal_params[TEMP_SENSOR_CORE] = thermal_b;
-		break;
-	}
-}
-/* fan_set_count should be called before  HOOK_INIT/HOOK_PRIO_DEFAULT */
-DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
-
-/*
- * Power monitoring and management.
- *
- * The overall goal is to gracefully manage the power demand so that
- * the power budgets are met without letting the system fall into
- * power deficit (perhaps causing a brownout).
- *
- * There are 2 power budgets that need to be managed:
- *  - overall system power as measured on the main power supply rail.
- *  - 5V power delivered to the USB and HDMI ports.
- *
- * The actual system power demand is calculated from the VBUS voltage and
- * the input current (read from a shunt), averaged over 5 readings.
- * The power budget limit is from the charge manager.
- *
- * The 5V power cannot be read directly. Instead, we rely on overcurrent
- * inputs from the USB and HDMI ports to indicate that the port is in use
- * (and drawing maximum power).
- *
- * There are 3 throttles that can be applied (in priority order):
- *
- *  - Type A BC1.2 front port restriction (3W)
- *  - Type C PD (throttle to 1.5A if sourcing)
- *  - Turn on PROCHOT, which immediately throttles the CPU.
- *
- *  The first 2 throttles affect both the system power and the 5V rails.
- *  The third is a last resort to force an immediate CPU throttle to
- *  reduce the overall power use.
- *
- *  The strategy is to determine what the state of the throttles should be,
- *  and to then turn throttles off or on as needed to match this.
- *
- *  This function runs on demand, or every 2 ms when the CPU is up,
- *  and continually monitors the power usage, applying the
- *  throttles when necessary.
- *
- *  All measurements are in milliwatts.
- */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
-
-/*
- * Power gain if front USB A ports are limited.
- */
-#define POWER_GAIN_TYPE_A	3200
-/*
- * Power gain if Type C port is limited.
- */
-#define POWER_GAIN_TYPE_C	8800
-/*
- * Power is averaged over 10 ms, with a reading every 2 ms.
- */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
-
-static void power_monitor(void)
-{
-	static uint32_t current_state;
-	int32_t delay;
-	uint32_t new_state = 0, diff;
-	int32_t headroom_5v = PWR_MAX - base_5v_power;
-
-	/*
-	 * If CPU is off or suspended, no need to throttle
-	 * or restrict power.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
-		/*
-		 * Slow down monitoring, assume no throttling required.
-		 */
-		delay = 20 * MSEC;
-	} else {
-		delay = POWER_DELAY_MS * MSEC;
-	}
-	/*
-	 * Check the 5v power usage and if necessary,
-	 * adjust the throttles in priority order.
-	 *
-	 * Either throttle may have already been activated by
-	 * the overall power control.
-	 *
-	 * We rely on the overcurrent detection to inform us
-	 * if the port is in use.
-	 *
-	 *  - If type C not already throttled:
-	 *	* If not overcurrent, prefer to limit type C [1].
-	 *	* If in overcurrentuse:
-	 *		- limit type A first [2]
-	 *		- If necessary, limit type C [3].
-	 *  - If type A not throttled, if necessary limit it [2].
-	 */
-	if (headroom_5v < 0) {
-		/*
-		 * Check whether type C is not throttled,
-		 * and is not overcurrent.
-		 */
-		if (!((new_state & THROT_TYPE_C) || usbc_overcurrent)) {
-			/*
-			 * [1] Type C not in overcurrent, throttle it.
-			 */
-			headroom_5v += PWR_C_HIGH - PWR_C_LOW;
-			new_state |= THROT_TYPE_C;
-		}
-		/*
-		 * [2] If type A not already throttled, and power still
-		 * needed, limit type A.
-		 */
-		if (!(new_state & THROT_TYPE_A) && headroom_5v < 0) {
-			headroom_5v += PWR_FRONT_HIGH - PWR_FRONT_LOW;
-			new_state |= THROT_TYPE_A;
-		}
-		/*
-		 * [3] If still under-budget, limit type C.
-		 * No need to check if it is already throttled or not.
-		 */
-		if (headroom_5v < 0)
-			new_state |= THROT_TYPE_C;
-	}
-	/*
-	 * Turn the throttles on or off if they have changed.
-	 */
-	diff = new_state ^ current_state;
-	current_state = new_state;
-	if (diff & THROT_PROCHOT) {
-		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
-
-		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
-	}
-	if (diff & THROT_TYPE_A) {
-		int typea_bc = (new_state & THROT_TYPE_A) ? 1 : 0;
-
-		gpio_set_level(GPIO_USB_A_LOW_PWR_OD, typea_bc);
-	}
-	hook_call_deferred(&power_monitor_data, delay);
-}
diff --git a/board/scout/board.h b/board/scout/board.h
deleted file mode 100644
index 2b398119c2..0000000000
--- a/board/scout/board.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Puff board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Internal SPI flash on NPCX796FC is 512 kB */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_BOARD_HAS_RTC_RESET
-#define CONFIG_BOARD_VERSION_CBI
-#define CONFIG_DEDICATED_RECOVERY_BUTTON
-#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-/* TODO: (b/143496253) re-enable CEC */
-/* #define CONFIG_CEC */
-#define CONFIG_CRC8
-#define CONFIG_CBI_EEPROM
-#define CONFIG_EMULATED_SYSRQ
-#undef CONFIG_KEYBOARD_BOOT_KEYS
-#define CONFIG_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_KEYBOARD_RUNTIME_KEYS
-#undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_PWM
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define CONFIG_SHA256
-
-/* EC Commands */
-#define CONFIG_CMD_BUTTON
-/* Include CLI command needed to support CCD testing. */
-#define CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_KEYBOARD
-#define CONFIG_HOSTCMD_PD_CONTROL
-#undef CONFIG_CMD_PWR_AVG
-#define CONFIG_CMD_PPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#ifdef SECTION_IS_RO
-/* Reduce RO size by removing less-relevant commands. */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_CHARGEN
-#undef CONFIG_CMD_HCDEBUG
-#undef CONFIG_CMD_MMAPINFO
-#endif
-
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Don't generate host command debug by default */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Enable AP Reset command for TPM with old firmware version to detect it. */
-#define CONFIG_CMD_AP_RESET_LOG
-#define CONFIG_HOSTCMD_AP_RESET
-
-/* Chipset config */
-#define CONFIG_CHIPSET_COMETLAKE_DISCRETE
-/* check */
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_IGNORE_LID
-#define CONFIG_POWER_BUTTON_X86
-/* Check: */
-#define CONFIG_POWER_BUTTON_INIT_IDLE
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
-#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-#define CONFIG_POWER_PP5000_CONTROL
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define CONFIG_INA3221
-
-/* Fan and temp. */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 0
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_ROA_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 0
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_DUMB
-/* There are five ports, but power enable is ganged across all of them. */
-#define USB_PORT_COUNT 1
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_SCALER		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	ADC_TEMP_SENSOR_2,  /* ADC1 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_WHITE,
-	/* Number of PWM channels */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_WIFI,
-	TEMP_SENSOR_COUNT
-};
-
-
-/* Board specific handlers */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-void led_alert(int enable);
-void show_critical_error(void);
-
-/*
- * firmware config fields
- */
-/*
- * Barrel-jack power (4 bits).
- */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
-#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
-/*
- * USB Connector 4 not present (1 bit).
- */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
-#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
-/*
- * Thermal solution config (3 bits).
- */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
-#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
-
-int ec_config_get_usb4_present(void);
-unsigned int ec_config_get_thermal_solution(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
-
-/*
- * There is no RSMRST input, so alias it to the output. This short-circuits
- * common_intel_x86_handle_rsmrst.
- */
-#define GPIO_RSMRST_L_PGOOD	GPIO_PCH_RSMRST_L
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/scout/build.mk b/board/scout/build.mk
deleted file mode 100644
index cf964a2d15..0000000000
--- a/board/scout/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-
-board-y=board.o
-board-y+=led.o
diff --git a/board/scout/ec.tasklist b/board/scout/ec.tasklist
deleted file mode 100644
index 787ffbf479..0000000000
--- a/board/scout/ec.tasklist
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/scout/gpio.inc b/board/scout/gpio.inc
deleted file mode 100644
index af8fbfb25b..0000000000
--- a/board/scout/gpio.inc
+++ /dev/null
@@ -1,173 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Pin names follow the schematic, and are aliased to other names if necessary.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Latency on this interrupt is extremely critical, so it comes first to ensure
- * it gets placed first in gpio_wui_table so gpio_interrupt() needs to do
- * minimal scanning. */
-GPIO_INT(CPU_C10_GATE_L,       PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt)
-
-/* Wake Source interrupts */
-GPIO_INT(EC_WP_ODL,            PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_PP5000_A_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1800_A_OD,       PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
-/* EC output, but also interrupt so this can be polled as a power signal */
-GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
-#endif
-GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(IMVP8_VRRDY_OD,       PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt)
-
-/*
- * Directly connected recovery button (not available on some boards).
- */
-GPIO_INT(EC_RECOVERY_BTN_ODL,  PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
-/*
- * Recovery button input from H1.
- */
-GPIO_INT(H1_EC_RECOVERY_BTN_ODL, PIN(2, 4), GPIO_INT_BOTH, button_interrupt)
-GPIO(BJ_ADP_PRESENT_L,     PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP)
-
-/* Port power control interrupts */
-GPIO_INT(HDMI_CONN0_OC_ODL,    PIN(0, 7), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(HDMI_CONN1_OC_ODL,    PIN(0, 6), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A0_OC_ODL,        PIN(E, 4), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A1_OC_ODL,        PIN(A, 2), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A2_OC_ODL,        PIN(F, 5), GPIO_INT_BOTH, port_ocp_interrupt)
-GPIO_INT(USB_A3_OC_ODL,        PIN(0, 3), GPIO_INT_BOTH, port_ocp_interrupt)
-
-/* PCH/CPU signals */
-GPIO(EC_PCH_PWROK,             PIN(0, 5), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_ODR_HIGH)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-/* i.MX8 soundbar signals */
-GPIO(BOOT_IND_EC,              PIN(E, 2), GPIO_INPUT)
-
-/* TSUM scaler signals */
-GPIO(TSUM_WAKEUP_EC,           PIN(B, 1), GPIO_INPUT)
-
-/* ALS signals */
-GPIO(EC_RGB_INT_L,             PIN(9, 7), GPIO_INPUT)
-
-/* Power control outputs */
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_INA_H1_EC_ODL,  PIN(5, 7), GPIO_ODR_HIGH)
-GPIO(EN_PP1800_A,              PIN(1, 5), GPIO_OUT_LOW)
-GPIO(VCCST_PG_OD,              PIN(1, 4), GPIO_ODR_LOW)
-GPIO(EN_S0_RAILS,              PIN(1, 1), GPIO_OUT_LOW)
-GPIO(EN_ROA_RAILS,             PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP950_VCCIO,           PIN(1, 0), GPIO_OUT_LOW)
-GPIO(EC_IMVP8_PE,              PIN(A, 7), GPIO_OUT_LOW)
-GPIO(EN_IMVP8_VR,              PIN(F, 4), GPIO_OUT_LOW)
-GPIO(EC_CAM_V3P3_EN,           PIN(C, 6), GPIO_OUT_LOW)
-GPIO(EC_MX8M_ONOFF,            PIN(9, 3), GPIO_OUT_LOW)
-GPIO(EC_SCALER_EN,             PIN(E, 0), GPIO_OUT_LOW)
-GPIO(PP3300_TPU_A_EN,          PIN(B, 0), GPIO_OUT_LOW)
-GPIO(PWR_CTRL,                 PIN(6, 2), GPIO_OUT_LOW)
-
-/* Barreljack */
-GPIO(EN_PPVAR_BJ_ADP_L,        PIN(0, 4), GPIO_OUT_LOW)
-
-/* USB type A */
-GPIO(EN_PP5000_USB_VBUS,       PIN(8, 3), GPIO_OUT_LOW)
-GPIO(USB_A_LOW_PWR_OD,         PIN(9, 4), GPIO_ODR_LOW)
-GPIO(USB_A2_STATUS_L,          PIN(6, 1), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,          PIN(C, 7), GPIO_INPUT)
-
-/* USB type C */
-GPIO(USB_C0_POL_L,             PIN(0, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* USB-C Polarity */
-
-/* Misc. */
-GPIO(M2_SSD_PLN,               PIN(A, 0), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,             PIN(E, 5), GPIO_ODR_HIGH)
-GPIO(PACKET_MODE_EN,           PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EN_PP_MST_OD,             PIN(9, 6), GPIO_OUT_HIGH)
-
-/* HDMI/CEC */
-GPIO(EN_PP5000_HDMI,           PIN(5, 0), GPIO_OUT_LOW)
-GPIO(HDMI_CONN0_CEC_IN,        PIN(4, 0), GPIO_INPUT)
-GPIO(HDMI_CONN1_CEC_OUT,       PIN(9, 5), GPIO_ODR_HIGH)
-GPIO(HDMI_CONN1_CEC_IN,        PIN(D, 3), GPIO_INPUT)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT)           /* EC_I2C_INA_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT)           /* EC_I2C_INA_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPPC_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_DDR_SCALER_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_DDR_SCALER_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_ALS_SCL */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_ALS_SDA */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_IMVP8_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_IMVP8_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)                  /* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x01), 0, MODULE_I2C, 0)                  /* I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                  /* I2C1 SDA */
-ALTERNATE(PIN_MASK(9, 0x03), 0, MODULE_I2C, 0)                  /* I2C2 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                  /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                  /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                  /* I2C7 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x08), 0, MODULE_PWM, 0)                  /* PWM0 - Red Led */
-ALTERNATE(PIN_MASK(C, 0x10), 0, MODULE_PWM, 0)                  /* PWM2 - White Led */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                  /* PWM5 - Fan 1 */
-ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)                  /* TA2 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x3E), 0, MODULE_ADC, 0)                  /* ADC0, ADC1, ADC2, ADC4 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)                  /* ADC7 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)                  /* ADC9 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                 /* UART from EC to Servo */
-
-/* Unused pins */
-UNUSED(PIN(1, 3))						/* EC_GP_SEL1_ODL */
-UNUSED(PIN(C, 0))						/* FAN_PWM_2 */
-UNUSED(PIN(8, 0))						/* LED_BLUE_L */
-UNUSED(PIN(4, 2))						/* ADC3/TEMP_SENSOR_3 */
-UNUSED(PIN(C, 2))						/* A12 NC */
-UNUSED(PIN(1, 2))						/* C6  NC */
-UNUSED(PIN(6, 6))						/* H4  NC */
-UNUSED(PIN(8, 1))						/* L6  NC */
-UNUSED(PIN(8, 5))						/* L7  NC */
-UNUSED(PIN(3, 2))						/* E5  NC */
-UNUSED(PIN(D, 6))						/* F6  NC */
-UNUSED(PIN(3, 5))						/* F5  NC */
-UNUSED(PIN(5, 6))						/* M2  NC */
-UNUSED(PIN(D, 2))						/* C11 NC */
-UNUSED(PIN(8, 6))						/* J8  NC */
-UNUSED(PIN(7, 2))						/* H6  NC */
-UNUSED(PIN(F, 2))						/* E11 NC */
-UNUSED(PIN(F, 3))						/* F7  NC */
diff --git a/board/scout/led.c b/board/scout/led.c
deleted file mode 100644
index a9f70d2d40..0000000000
--- a/board/scout/led.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power LED control for Puff.
- * Solid green - active power
- * Green flashing - suspended
- * Red flashing - alert
- * Solid red - critical
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Due to the CSME-Lite processing, upon startup the CPU transitions through
- * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
- * delay turning off the LED during suspend/shutdown.
- */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
-
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_WHITE,
-	LED_AMBER,
-
-	/* Number of colors, not a color itself */
-	LED_COLOR_COUNT
-};
-
-static int set_color_power(enum led_color color, int duty)
-{
-	int white = 0;
-	int red = 0;
-
-	if (duty < 0 || 100 < duty)
-		return EC_ERROR_UNKNOWN;
-
-	switch (color) {
-	case LED_OFF:
-		break;
-	case LED_WHITE:
-		white = 1;
-		break;
-	case LED_RED:
-		red = 1;
-		break;
-	case LED_AMBER:
-		red = 1;
-		white = 1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (red)
-		pwm_set_duty(PWM_CH_LED_RED, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_RED, 0);
-
-	if (white)
-		pwm_set_duty(PWM_CH_LED_WHITE, duty);
-	else
-		pwm_set_duty(PWM_CH_LED_WHITE, 0);
-
-	return EC_SUCCESS;
-}
-
-static int set_color(enum ec_led_id id, enum led_color color, int duty)
-{
-	switch (id) {
-	case EC_LED_ID_POWER_LED:
-		return set_color_power(color, duty);
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
-
-/* When pulsing is enabled, brightness is incremented by <duty_inc> every
- * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
- * likewise in LED_PULSE_US usec.
- */
-static struct {
-	uint32_t interval;
-	int duty_inc;
-	enum led_color color;
-	int duty;
-} led_pulse;
-
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
-
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
-{
-	led_pulse.interval = interval;
-	led_pulse.duty_inc = duty_inc;
-	led_pulse.color = color;
-	led_pulse.duty = 0;
-}
-
-static void pulse_power_led(enum led_color color)
-{
-	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
-	if (led_pulse.duty + led_pulse.duty_inc > 100)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	else if (led_pulse.duty + led_pulse.duty_inc < 0)
-		led_pulse.duty_inc = led_pulse.duty_inc * -1;
-	led_pulse.duty += led_pulse.duty_inc;
-}
-
-static void led_tick(void);
-DECLARE_DEFERRED(led_tick);
-static void led_tick(void)
-{
-	uint32_t elapsed;
-	uint32_t next = 0;
-	uint32_t start = get_time().le.lo;
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pulse_power_led(led_pulse.color);
-	elapsed = get_time().le.lo - start;
-	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
-	hook_call_deferred(&led_tick_data, next);
-}
-
-static void led_suspend(void)
-{
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_WHITE);
-	led_tick();
-}
-DECLARE_DEFERRED(led_suspend);
-
-static void led_shutdown(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
-}
-DECLARE_DEFERRED(led_shutdown);
-
-static void led_shutdown_hook(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
-
-static void led_suspend_hook(void)
-{
-	hook_call_deferred(&led_shutdown_data, -1);
-	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
-
-static void led_resume(void)
-{
-	/* Assume there is no race condition with led_tick, which also
-	 * runs in hook_task.
-	 */
-	hook_call_deferred(&led_tick_data, -1);
-	/*
-	 * Avoid invoking the suspend/shutdown delayed hooks.
-	 */
-	hook_call_deferred(&led_suspend_data, -1);
-	hook_call_deferred(&led_shutdown_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_WHITE, 100);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
-
-static void led_init(void)
-{
-	pwm_enable(PWM_CH_LED_RED, 1);
-	pwm_enable(PWM_CH_LED_WHITE, 1);
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_resume();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_suspend();
-	else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		led_shutdown();
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_INIT_PWM + 1);
-
-void led_alert(int enable)
-{
-	if (enable) {
-		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_RED);
-		led_tick();
-	} else {
-		/* Restore the previous signal */
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			led_resume();
-		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			led_suspend_hook();
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			led_shutdown_hook();
-	}
-}
-
-void show_critical_error(void)
-{
-	hook_call_deferred(&led_tick_data, -1);
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
-}
-
-static int command_led(int argc, char **argv)
-{
-	enum ec_led_id id = EC_LED_ID_POWER_LED;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		led_auto_control(id, !led_auto_control_is_enabled(id));
-		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
-	} else if (!strcasecmp(argv[1], "off")) {
-		set_color(id, LED_OFF, 0);
-	} else if (!strcasecmp(argv[1], "red")) {
-		set_color(id, LED_RED, 100);
-	} else if (!strcasecmp(argv[1], "white")) {
-		set_color(id, LED_WHITE, 100);
-	} else if (!strcasecmp(argv[1], "amber")) {
-		set_color(id, LED_AMBER, 100);
-	} else if (!strcasecmp(argv[1], "alert")) {
-		led_alert(1);
-	} else if (!strcasecmp(argv[1], "crit")) {
-		show_critical_error();
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|amber|off|alert|crit]",
-			"Turn on/off LED.");
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED])
-		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		return set_color(id, LED_WHITE, brightness[EC_LED_COLOR_WHITE]);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
-	else
-		return set_color(id, LED_OFF, 0);
-}
diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c
deleted file mode 100644
index 8074ba38ab..0000000000
--- a/board/servo_micro/board.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Servo micro board configuration */
-
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_ite_flash_support.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "update_fw.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_hw.h"
-#include "usb_i2c.h"
-#include "usb_spi.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
-
-	/*
-	 * the DMA mapping is :
-	 *  Chan 3 : USART3_RX
-	 *  Chan 5 : USART2_RX
-	 *  Chan 6 : USART4_RX (Disable)
-	 *  Chan 6 : SPI2_RX
-	 *  Chan 7 : SPI2_TX
-	 *
-	 *  i2c : no dma
-	 *  tim16/17: no dma
-	 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
-
-	/* Remap SPI2 to DMA channels 6 and 7 */
-	/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
-	/* but cros_ec hardcodes a 6/7 assumption in registers.h */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-
-}
-
-/******************************************************************************
- * Forward UARTs as a USB serial interface.
- */
-
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
-
-/******************************************************************************
- * Forward USART2 (EC) as a simple USB serial interface.
- */
-
-static struct usart_config const usart2;
-struct usb_stream_config const usart2_usb;
-
-static struct queue const usart2_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart2.producer, usart2_usb.consumer);
-static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t,
-	usart2_usb.producer, usart2.consumer);
-
-static struct usart_rx_dma const usart2_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH5, 32);
-
-static struct usart_config const usart2 =
-	USART_CONFIG(usart2_hw,
-		usart2_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart2_to_usb,
-		usb_to_usart2);
-
-USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
-	USB_IFACE_USART2_STREAM,
-	USB_STR_USART2_STREAM_NAME,
-	USB_EP_USART2_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart2,
-	usart2_to_usb,
-	usart2)
-
-
-/******************************************************************************
- * Forward USART3 (CPU) as a simple USB serial interface.
- */
-
-static struct usart_config const usart3;
-struct usb_stream_config const usart3_usb;
-
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
-
-static struct usart_rx_dma const usart3_rx_dma =
-	USART_RX_DMA(STM32_DMAC_CH3, 32);
-
-static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
-
-
-/******************************************************************************
- * Forward USART4 (cr50) as a simple USB serial interface.
- *  We cannot enable DMA due to lack of DMA channels.
- */
-
-static struct usart_config const usart4;
-struct usb_stream_config const usart4_usb;
-
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
-
-static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
-
-/******************************************************************************
- * Check parity setting on usarts.
- */
-static int command_uart_parity(int argc, char **argv)
-{
-	int parity = 0, newparity;
-	struct usart_config const *usart;
-	char *e;
-
-	if ((argc < 2) || (argc > 3))
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart2"))
-		usart = &usart2;
-	else if (!strcasecmp(argv[1], "usart3"))
-		usart = &usart3;
-	else if (!strcasecmp(argv[1], "usart4"))
-		usart = &usart4;
-	else
-		return EC_ERROR_PARAM1;
-
-	if (argc == 3) {
-		parity = strtoi(argv[2], &e, 0);
-		if (*e || (parity < 0) || (parity > 2))
-			return EC_ERROR_PARAM2;
-
-		usart_set_parity(usart, parity);
-	}
-
-	newparity = usart_get_parity(usart);
-	ccprintf("Parity on %s is %d.\n", argv[1], newparity);
-
-	if ((argc == 3) && (newparity != parity))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
-			"Set parity on uart");
-
-/******************************************************************************
- * Set baud rate setting on usarts.
- */
-static int command_uart_baud(int argc, char **argv)
-{
-	int baud = 0;
-	struct usart_config const *usart;
-	char *e;
-
-	if ((argc < 2) || (argc > 3))
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart2"))
-		usart = &usart2;
-	else if (!strcasecmp(argv[1], "usart3"))
-		usart = &usart3;
-	else if (!strcasecmp(argv[1], "usart4"))
-		usart = &usart4;
-	else
-		return EC_ERROR_PARAM1;
-
-	baud = strtoi(argv[2], &e, 0);
-	if (*e || baud < 0)
-		return EC_ERROR_PARAM2;
-
-	usart_set_baud(usart, baud);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
-			"Set baud rate on uart");
-
-/******************************************************************************
- * Hold the usart pins low while disabling it, or return it to normal.
- */
-static int command_hold_usart_low(int argc, char **argv)
-{
-	/* Each bit represents if that port rx is being held low */
-	static int usart_status;
-
-	int usart_mask;
-	enum gpio_signal rx;
-
-	if (argc > 3 || argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "usart2")) {
-		usart_mask = 1 << 2;
-		rx = GPIO_USART2_SERVO_RX_DUT_TX;
-	} else if (!strcasecmp(argv[1], "usart3")) {
-		usart_mask = 1 << 3;
-		rx = GPIO_USART3_SERVO_RX_DUT_TX;
-	} else if (!strcasecmp(argv[1], "usart4")) {
-		usart_mask = 1 << 4;
-		rx = GPIO_USART4_SERVO_RX_DUT_TX;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	/* Updating the status of this port */
-	if (argc == 3) {
-		char *e;
-		const int hold_low = strtoi(argv[2], &e, 0);
-
-		if (*e || (hold_low < 0) || (hold_low > 1))
-			return EC_ERROR_PARAM2;
-
-		if (!!(usart_status & usart_mask) == hold_low) {
-			/* Do nothing since there is no change */
-		} else if (hold_low) {
-			/*
-			 * No need to shutdown UART, just de-mux the RX pin from
-			 * UART and change it to a GPIO temporarily.
-			 */
-			gpio_config_pin(MODULE_USART, rx, 0);
-			gpio_set_flags(rx, GPIO_OUT_LOW);
-
-			/* Update global uart state */
-			usart_status |= usart_mask;
-		} else {
-			/*
-			 * Mux the RX pin back to GPIO mode
-			 */
-			gpio_config_pin(MODULE_USART, rx, 1);
-
-			/* Update global uart state */
-			usart_status &= ~usart_mask;
-		}
-	}
-
-	/* Print status for get and set case. */
-	ccprintf("USART status: %s\n",
-			usart_status & usart_mask ? "held low" : "normal");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
-			"usart[2|3|4] [0|1]?",
-			"Get/set the hold-low state for usart port");
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo Micro"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("UART3"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("CPU"),
-	[USB_STR_USART2_STREAM_NAME]  = USB_STRING_DESC("EC"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/******************************************************************************
- * Support SPI bridging over USB, this requires usb_spi_board_enable and
- * usb_spi_board_disable to be defined to enable and disable the SPI bridge.
- */
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-void usb_spi_board_enable(struct usb_spi_config const *config)
-{
-	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 1);
-
-	/* Set all four SPI pins to high speed */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
-
-	/* Enable clocks to SPI2 module */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	spi_enable(&spi_devices[0], 1);
-}
-
-void usb_spi_board_disable(struct usb_spi_config const *config)
-{
-	spi_enable(&spi_devices[0], 0);
-
-	/* Disable clocks to SPI2 module */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-}
-
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-/* Configure ITE flash support module */
-const struct ite_dfu_config_t ite_dfu_config = {
-	.i2c_port = I2C_PORT_MASTER,
-	.scl = GPIO_MASTER_I2C_SCL,
-	.sda = GPIO_MASTER_I2C_SDA,
-};
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	/* USB to serial queues */
-	queue_init(&usart2_to_usb);
-	queue_init(&usb_to_usart2);
-	queue_init(&usart3_to_usb);
-	queue_init(&usb_to_usart3);
-	queue_init(&usart4_to_usb);
-	queue_init(&usb_to_usart4);
-
-	/* UART init */
-	usart_init(&usart2);
-	usart_init(&usart3);
-	usart_init(&usart4);
-
-	/* Enable GPIO expander. */
-	gpio_set_level(GPIO_TCA6416_RESET_L, 1);
-
-	/* Structured enpoints */
-	usb_spi_enable(&usb_spi, 1);
-
-	/* Enable UARTs by default. */
-	gpio_set_level(GPIO_UART1_EN_L, 0);
-	gpio_set_level(GPIO_UART2_EN_L, 0);
-	/* Disable power output. */
-	gpio_set_level(GPIO_SPI1_VREF_18, 0);
-	gpio_set_level(GPIO_SPI1_VREF_33, 0);
-	gpio_set_level(GPIO_SPI2_VREF_18, 0);
-	gpio_set_level(GPIO_SPI2_VREF_33, 0);
-	/* Enable UART3 routing. */
-	gpio_set_level(GPIO_SPI1_MUX_SEL, 1);
-	gpio_set_level(GPIO_SPI1_BUF_EN_L, 1);
-	gpio_set_level(GPIO_JTAG_BUFIN_EN_L, 0);
-	gpio_set_level(GPIO_SERVO_JTAG_TDO_BUFFER_EN, 1);
-	gpio_set_level(GPIO_SERVO_JTAG_TDO_SEL, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************
- * Turn down USART before jumping to RW.
- */
-static void board_jump(void)
-{
-	/*
-	 * If we don't shutdown the USARTs before jumping to RW, then when early
-	 * RW tries to set the GPIOs to input (or anything other than alternate)
-	 * the jump fail on some servo micros.
-	 *
-	 * It also make sense to shut them down since RW will reinitialize them
-	 * in board_init above.
-	 */
-	usart_shutdown(&usart2);
-	usart_shutdown(&usart3);
-	usart_shutdown(&usart4);
-
-	/* Shutdown other hardware modules and let RW reinitialize them */
-	usb_spi_enable(&usb_spi, 0);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, board_jump, HOOK_PRIO_DEFAULT);
diff --git a/board/servo_micro/board.h b/board/servo_micro/board.h
deleted file mode 100644
index 306bc0e5d7..0000000000
--- a/board/servo_micro/board.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Servo micro configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_LTO
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-#define CONFIG_BOARD_PRE_INIT
-
-/* Enable USART1,3,4 and USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART2
-#define CONFIG_STREAM_USART3
-#define CONFIG_STREAM_USART4
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* The UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-#define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x501a
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_UPDATE
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 100
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_USART4_STREAM	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5
-#define USB_IFACE_USART2_STREAM	6
-#define USB_IFACE_COUNT		7
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART2_STREAM	7
-#define USB_EP_COUNT		8
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* Enable control of SPI over USB */
-#define CONFIG_USB_SPI
-#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI master port */
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 0
-
-/* See i2c_ite_flash_support.c for more information about these values */
-#define CONFIG_ITE_FLASH_SUPPORT
-#define CONFIG_I2C_XFER_LARGE_TRANSFER
-#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
-#undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-
-#include "gpio_signal.h"
-
-/* GPIO signal mapping */
-#define GPIO_USART4_SERVO_TX_DUT_RX GPIO_UART3_TX_SERVO_JTAG_TCK
-#define GPIO_USART4_SERVO_RX_DUT_TX GPIO_UART3_RX_JTAG_BUFFER_TO_SERVO_TDO
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_USART4_STREAM_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_USART3_STREAM_NAME,
-	USB_STR_USART2_STREAM_NAME,
-	USB_STR_UPDATE_NAME,
-
-	USB_STR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/servo_micro/build.mk b/board/servo_micro/build.mk
deleted file mode 100644
index 0e069a31ad..0000000000
--- a/board/servo_micro/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/servo_micro/ccd.md b/board/servo_micro/ccd.md
deleted file mode 100644
index 267da66776..0000000000
--- a/board/servo_micro/ccd.md
+++ /dev/null
@@ -1,168 +0,0 @@
-<!--
- Copyright 2018 The Chromium OS Authors. All rights reserved.
- Use of this source code is governed by a BSD-style license that can be
- found in the LICENSE file.
--->
-
-# Case-Closed Debug in Chromebooks and Servo Micro
-
-The Servo debug/test-automation connector has been required on all chromebooks.
-It has proved essential to performing the required testing to meet the six week
-OS release cycle, for bringing up new systems and qualifying new components. In
-newer form-factors it is becoming hard to fit the Servo connector (and related
-flex) and in some designs the thermal solution stops working when the connector
-is used. The secure Case-Closed Debugging solution provides the same
-capabilities and can take advantage of the Debug Mode detection available on the
-USB-C connector. This application note gives an overview of Case-Closed Debug
-(CCD) but does not address the related security issues.
-
-## Introduction to Case-Closed Debug
-
-Case-Closed Debug provides the same set of features as are available on the
-Servo connector:
-
-*   Access to console UART connections to AP, EC and on some systems a third MCU
-*   Ability to reprogram firmware/BIOS SPI flash used by the AP
-*   Ability to reprogram SPI flash used by the EC or use a firmware update mode
-    to reprogram the internal flash on the EC (using UART or I2C)
-*   GPIOs for holding the EC (and thus entire system) or AP in reset
-*   Act as master on a debug I2C that is primarily used for power measurements.
-    This bus normally contains INA voltage/current monitors and temperature
-    monitors that will not be populated on final MP systems.
-*   JTAG/SWD could be provided but has not been implemented on any existing
-    system.
-
-When the Servo connector is used these interfaces are presented on well defined
-pins of the board-to-board connector and a flex is used to attach to the
-external Servo controller. The height needed for the mated board-to-board
-connector is not available in newer slim designs, and the disruption caused by
-the flex may interfere with thermal solutions. In a system using Case-Closed
-Debug the interfaces are gathered by a part on the board into a single USB
-interface that can come out of the system on an existing connector. In
-particular, the USB-C connector has two SideBand Use pins (SBU1, SBU2) that can
-be used for the debug USB while the main link on the connector continues to be
-available. (The SBU pins are also used by some Alternate Modes, so the connector
-cannot be used for video out at the same time as debugging.)
-
-## Servo Micro: Using CCD with existing boards
-
-The Servo Micro implements the CCD functions in a way that can connect to
-existing boards and thus can also serve as an easy introduction to the CCD
-implementation. The debug USB interface is expanded by a STM32F072 into an
-existing Servo flex connector that can be plugged into the target board.
-
-![block diagram](servo_micro.png)
-
-The Servo Micro includes the voltage level buffering between the microcontroller
-and the device under test (DUT), making use of the DUT supplied reference
-voltages. To allow use with all the existing designs a third UART (not on the
-original Servo connector, but on some designs) can be connected to either the
-JTAG pins or the SPI pins. It is capable of providing the SPI flash supply
-voltages.
-
-The schematics for Servo Micro are available
-[as a pdf](servo_micro_sch_20180404.pdf).
-
-Servo Micro has a USB micro-B connector and acts as a USB device.
-
-Schematic sheet 2 shows the STM32 powered from the uB connector. The UART3 pins
-can also be used as GPIO pins when driving the JTAG interface. As a useful but
-non-compliant hack if the ID pin on the uB is low then Q4 will force the STM32
-to boot in programming mode. This allows initial programming of the part with
-USB DFU using an illegal USB-A plug to USB-A plug cable and a USB-A receptacle
-to uB plug adapter. Alternatively the initial programming can be done using a
-UART connection on CN2.
-
-Schematic sheet 3 shows the I2C GPIO expander and the buffers for JTAG/SWD. The
-buffers adapt to the voltage needed on the DUT that is provided on
-`PPDUT_JTAG_VREF`. In the SWD case the TDI becomes the bidirectional SWDIO but
-the STM32 continues to use a discrete input and output pin. The DUT signal is
-received through U55 and a selection made with U1 to determine if to forward TDO
-from the DUT or the TDI/SWDIO. Because of the shared pins on the STM32 the JTAG
-interface can alternatively be used to connect UART3 to the DUT for a few
-chromebook models.
-
-Schematic sheet 4 shows the buffers for the SPI interfaces. Again the
-`PPDUT_SPIn_VREF` sets the voltage level required from the DUT. However, I61 and
-I62 (which are expanded on sheets 7 and 8) allow the Servo Micro to supply 3.3V
-or 1.8V for cases where the DUT does not provide the reference (care is needed
-to select the correct voltage for the given DUT). Only one of the SPI interfaces
-can be used at any time, so the buffers are also used to select which connects
-to the STM32 SPI pins. Certain chromebook models connect the UART3 in place of
-SPI1 which is enabled using U5 to select between the STM32 UART3 (TX,RX) and SPI
-(CLK, MISO).
-
-Schematic sheet 5 shows the buffers for the UART interfaces. The
-`PPDUT_UARTn_VREF` sets the voltage level required from the DUT.
-
-Schematic sheet 6 shows the board-to-board connector that mates with the servo
-connector on the DUT.
-
-Schematic sheets 7 and 8 are the expansion of blocks I61 and I62 on sheet 4. The
-load switches are carefully selected to have reverse blocking (protecting
-against a DUT providing a voltage or both being enabled).
-
-The code for the STM32 in Servo Micro is open source as the
-[`servo_micro`](../../board/servo_micro) board in the
-[Chromium EC codebase](https://chromium.googlesource.com/chromiumos/platform/ec/).
-Essentially it is a USB device that provides the standard control endpoint and 7
-function endpoints defined in [`board.h`](board.h).
-
-<!-- does not work in emacs/markdown preview but should in gitlies -->
-
-```c
-#define USB_EP_USART4_STREAM    1
-#define USB_EP_UPDATE           2
-#define USB_EP_SPI              3
-#define USB_EP_CONSOLE          4
-#define USB_EP_I2C              5
-#define USB_EP_USART3_STREAM    6
-#define USB_EP_USART2_STREAM    7
-```
-
-The USART endpoints use the simple `GOOGLE_SERIAL` vendor class to connect the
-STM32 UARTs. The CONSOLE endpoint also uses `GOOGLE_STREAM` to connect to the
-console of the code running on the STM32. `GOOGLE_STREAM` provides simple byte
-streams on the IN and OUT of the endpoint and host support is included in the
-standard Linux `drivers/usb/serial/usb-serial-simple.c`
-
-The SPI endpoint is described in
-[`chip/stm32/usb_spi.h`](../../chip/stm32/usb_spi.h) and provides a simple
-connection to the SPI port. The host support is provided as a
-[driver in flashrom](https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/HEAD/raiden_debug_spi.c).
-
-The I2C endpoint is described in [`include/usb_i2c.h`](../../include/usb_i2c.h)
-and provides a simple connection to the I2C bus. The host support is provided in
-the
-[hdctools servo support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/servo/stm32i2c.py).
-
-The GPIO endpoint is cryptically described in
-[`chip/stm32/usb_gpio.h`](../../chip/stm32/usb_gpio.h) and provides simple
-access to set/clear and read the GPIO pins. The host support is provided in the
-[hdctools servo support](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/servo/stm32gpio.py).
-
-The UPDATE endpoint is not part of CCD. It provides a method for updating the
-STM32 without needing the special boot modes. This uses the
-[Chromium EC update over USB](../../docs/usb_updater.md) method. The STM32 runs
-the code in [`common/usb_update.c`](../../common/usb_update.c). The host side
-code is in
-[`extra/usb_updater/usb_updater2.c`](../../extra/usb_updater/usb_updater2.c) and
-the [`extra/usb_updater`](../../extra/usb_updater/) directory contains
-additional scripts.
-
-## Using CCD on new designs
-
-New chromebook designs implement the CCD in a similar way to Servo Micro. There
-are two changes to the Servo Micro:
-
-*   The USB microB connector is replaced with the USB connection being carried
-    on the SBU pins of one of the devices USB-C ports. This will only be
-    activated when the USB-C port detects a debug accessory or a debug alternate
-    mode is entered. Use of the debug connection precludes use of the Display
-    Port alternate mode (which also uses the SBU pins) but allows full USB3 and
-    USB2 functions including both host and gadget mode.
-*   The system security chip will normally lock out debug access. Using secure
-    transactions, user authorization and proof of user physical presence it can
-    unlock various degrees of debug access.
-
-The full details are part of the Cr50 firmware specification.
diff --git a/board/servo_micro/ec.tasklist b/board/servo_micro/ec.tasklist
deleted file mode 100644
index c1fb169118..0000000000
--- a/board/servo_micro/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/servo_micro/gpio.inc b/board/servo_micro/gpio.inc
deleted file mode 100644
index 10e411c5f2..0000000000
--- a/board/servo_micro/gpio.inc
+++ /dev/null
@@ -1,75 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Outputs */
-GPIO(UART1_EN_L,		PIN(A, 8), GPIO_OUT_LOW)
-GPIO(SERVO_JTAG_TRST_L,		PIN(A, 13), GPIO_OUT_LOW)
-GPIO(SPI1_BUF_EN_L,		PIN(A, 14), GPIO_OUT_HIGH)
-GPIO(SPI2_BUF_EN_L,		PIN(A, 15), GPIO_OUT_HIGH)
-
-GPIO(UART2_EN_L,		PIN(B, 0), GPIO_OUT_LOW)
-GPIO(SPI1_VREF_33,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(SPI1_VREF_18,		PIN(B, 3), GPIO_OUT_LOW)
-GPIO(SPI2_VREF_33,		PIN(B, 4), GPIO_OUT_LOW)
-GPIO(SPI2_VREF_18,		PIN(B, 5), GPIO_OUT_LOW)
-GPIO(SERVO_JTAG_TRST_DIR,	PIN(B, 6), GPIO_OUT_HIGH)
-GPIO(SERVO_JTAG_TDI_DIR,	PIN(B, 7), GPIO_OUT_HIGH)
-
-GPIO(TCA6416_RESET_L,		PIN(C, 13), GPIO_OUT_LOW)
-GPIO(SPI1_MUX_SEL,		PIN(A, 5), GPIO_OUT_HIGH)
-GPIO(SERVO_JTAG_TMS_DIR,	PIN(C, 14), GPIO_OUT_LOW)
-GPIO(SERVO_JTAG_TDO_SEL,	PIN(C, 15), GPIO_OUT_HIGH)
-GPIO(JTAG_BUFOUT_EN_L,		PIN(F, 0), GPIO_OUT_HIGH)
-GPIO(JTAG_BUFIN_EN_L,		PIN(F, 1), GPIO_OUT_LOW)
-
-/* Inputs */
-GPIO(SERVO_JTAG_TMS,		PIN(A, 4), GPIO_INPUT)
-GPIO(SERVO_JTAG_TDO_BUFFER_EN,	PIN(A, 6), GPIO_OUT_HIGH)
-GPIO(SERVO_JTAG_TDI,		PIN(A, 7), GPIO_INPUT)
-
-GPIO(SERVO_JTAG_RTCK,		PIN(B, 1), GPIO_INPUT)
-
-/* Flash SPI interface */
-GPIO(SPI_CS,			PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(SPI_CLK,			PIN(B, 13), GPIO_INPUT)
-GPIO(SPI_MISO,			PIN(B, 14), GPIO_INPUT)
-GPIO(SPI_MOSI,			PIN(B, 15), GPIO_INPUT)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(MASTER_I2C_SCL,		PIN(B, 8), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,		PIN(B, 9), GPIO_INPUT)
-
-/* These pins are used for USART and are set to alternate mode below */
-GPIO(USART2_SERVO_TX_DUT_RX,    PIN(A, 2),  GPIO_INPUT)
-GPIO(USART2_SERVO_RX_DUT_TX,    PIN(A, 3),  GPIO_INPUT)
-GPIO(USART3_SERVO_TX_DUT_RX,    PIN(B, 10), GPIO_INPUT)
-GPIO(USART3_SERVO_RX_DUT_TX,    PIN(B, 11), GPIO_INPUT)
-/*
- * The USART4 (UART3) names are already in use by dut-controls, so they can't
- * be easily updated. They are aliased in board.h though.
- *
- * Also, these need to be GPIO_ALTERNATE until all servo micro RO images have
- * the board_jump USART shutdown. After ~2020/06/01 they can move to GPIO_INPUT.
- * See b/144356961 for more background.
- */
-GPIO(UART3_TX_SERVO_JTAG_TCK,              PIN(A, 0),  GPIO_ALTERNATE)
-GPIO(UART3_RX_JTAG_BUFFER_TO_SERVO_TDO,    PIN(A, 1),  GPIO_ALTERNATE)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA09/PA10 - Servo stm32 console UART*/
-ALTERNATE(PIN_MASK(A, 0x000C), 1, MODULE_USART, 0) /* USART2: PA2/PA3 - Servo UART1 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 4, MODULE_USART, 0) /* USART3: PB10/PB11 - Servo UART2 */
-ALTERNATE(PIN_MASK(A, 0x0003), 4, MODULE_USART, 0) /* USART4: PA0/PA1 - Servo UART3 */
-
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C, 0) /* I2C MASTER:PB8/PB9 GPIO_ODR_HIGH */
-ALTERNATE(PIN_MASK(B, 0x0300), 2, MODULE_I2C_TIMERS, 0) /* I2C MASTER:PB8/PB9 TIM16_CH1/TIM17_CH1 */
-
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH, 0) /* SPI: PB15 - PB12 MOSI, MISO, CLK, CS */
diff --git a/board/servo_micro/servo_micro.png b/board/servo_micro/servo_micro.png
deleted file mode 100644
index e3591d41c7..0000000000
--- a/board/servo_micro/servo_micro.png
+++ /dev/null
diff --git a/board/servo_micro/servo_micro_sch_20180404.pdf b/board/servo_micro/servo_micro_sch_20180404.pdf
deleted file mode 100644
index d9f643a11b..0000000000
--- a/board/servo_micro/servo_micro_sch_20180404.pdf
+++ /dev/null
diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c
deleted file mode 100644
index 8540de710f..0000000000
--- a/board/servo_v4/board.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Servo V4 configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-/* Just want the .h file for PS8742 definitions, not the large object file. */
-#define CONFIG_USB_MUX_PS8742
-#include "ps8740.h"
-#undef CONFIG_USB_MUX_PS8742
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "update_fw.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_gpio.h"
-#include "usb_i2c.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "usb_spi.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/******************************************************************************
- * GPIO interrupt handlers.
- */
-
-static void vbus0_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C0);
-}
-
-static void vbus1_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C1);
-}
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_irq_deferred(void)
-{
-	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	if (dp_mode) {
-		pd_send_hpd(DUT, hpd_irq);
-		CPRINTS("HPD IRQ");
-	}
-}
-DECLARE_DEFERRED(hpd_irq_deferred);
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DP_HPD);
-	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	if (level != hpd_prev_level) {
-		/* It's a glitch while in deferred or canceled action */
-		return;
-	}
-
-	if (dp_mode) {
-		pd_send_hpd(DUT, level ? hpd_high : hpd_low);
-		CPRINTS("HPD: %d", level);
-	}
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-void hpd_evt(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* Store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data, -1);
-
-	/* It's a glitch.  Previous time moves but level is the same. */
-	if (cur_delta < HPD_USTREAM_DEBOUNCE_IRQ)
-		return;
-
-	if ((!hpd_prev_level && level) &&
-	    (cur_delta < HPD_USTREAM_DEBOUNCE_LVL)) {
-		/* It's an irq */
-		hook_call_deferred(&hpd_irq_deferred_data, 0);
-	} else if (cur_delta >= HPD_USTREAM_DEBOUNCE_LVL) {
-		hook_call_deferred(&hpd_lvl_deferred_data,
-				   HPD_USTREAM_DEBOUNCE_LVL);
-	}
-
-	hpd_prev_level = level;
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************
- * Board pre-init function.
- */
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-
-	/*
-	 * the DMA mapping is :
-	 *  Chan 2 : TIM1_CH1  (CHG RX) - Default mapping
-	 *  Chan 3 : SPI1_TX   (CHG TX) - Default mapping
-	 *  Chan 4 : USART1 TX - Remapped from default Chan 2
-	 *  Chan 5 : USART1 RX - Remapped from default Chan 3
-	 *  Chan 6 : TIM3_CH1  (DUT RX) - Remapped from default Chan 4
-	 *  Chan 7 : SPI2_TX   (DUT TX) - Remapped from default Chan 5
-	 *
-	 * As described in the comments above, both USART1 TX/RX and DUT Tx/RX
-	 * channels must be remapped from the defulat locations. Remapping is
-	 * acoomplished by setting the following bits in the STM32_SYSCFG_CFGR1
-	 * register. Information about this register and its settings can be
-	 * found in section 11.3.7 DMA Request Mapping of the STM RM0091
-	 * Reference Manual
-	 */
-	/* Remap USART1 Tx from DMA channel 2 to channel 4 */
-	STM32_SYSCFG_CFGR1 |= BIT(9);
-	/* Remap USART1 Rx from DMA channel 3 to channel 5 */
-	STM32_SYSCFG_CFGR1 |= BIT(10);
-	/* Remap TIM3_CH1 from DMA channel 4 to channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(30);
-	/* Remap SPI2 Tx from DMA channel 5 to channel 7 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-}
-
-/******************************************************************************
- * Set up USB PD
- */
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-
-/******************************************************************************
- * Forward UARTs as a USB serial interface.
- */
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-/******************************************************************************
- * Forward USART3 as a simple USB serial interface.
- */
-
-static struct usart_config const usart3;
-struct usb_stream_config const usart3_usb;
-
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
-
-static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
-
-
-/******************************************************************************
- * Forward USART4 as a simple USB serial interface.
- */
-
-static struct usart_config const usart4;
-struct usb_stream_config const usart4_usb;
-
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
-
-static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb)
-
-/*
- * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
- * UEFI and kernel requirements (see b/183857501).
- */
-const struct usb_interface_descriptor
-USB_IFACE_DESC(USB_IFACE_EMPTY) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_EMPTY,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 0,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = 0,
-	.bInterfaceProtocol = 0,
-	.iInterface         = 0,
-};
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-/******************************************************************************
- * Initialize board.
- */
-
-/*
- * Support tca6416 I2C ioexpander.
- */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-
-
-/* Write a GPIO output on the tca6416 I2C ioexpander. */
-static void write_ioexpander(int bank, int gpio, int val)
-{
-	int tmp;
-
-	/* Read output port register */
-	i2c_read8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_OUT_PORT_A + bank, &tmp);
-	if (val)
-		tmp |= BIT(gpio);
-	else
-		tmp &= ~BIT(gpio);
-	/* Write back modified output port register */
-	i2c_write8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_OUT_PORT_A + bank, tmp);
-}
-
-/* Read a single GPIO input on the tca6416 I2C ioexpander. */
-static int read_ioexpander_bit(int bank, int bit)
-{
-	int tmp;
-	int mask = 1 << bit;
-
-	/* Read input port register */
-	i2c_read8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_IN_PORT_A + bank, &tmp);
-
-	return (tmp & mask) >> bit;
-}
-
-/* Enable uservo USB. */
-static void init_uservo_port(void)
-{
-	/* Write USERVO_POWER_EN */
-	write_ioexpander(0, 7, 1);
-	/* Write USERVO_FASTBOOT_MUX_SEL */
-	write_ioexpander(1, 0, 0);
-}
-
-/* Enable blue USB port to DUT. */
-static void init_usb3_port(void)
-{
-	/* Write USB3.0_TYPEA_MUX_SEL */
-	write_ioexpander(0, 3, 1);
-	/* Write USB3.0_TYPEA_MUX_EN_L */
-	write_ioexpander(0, 4, 0);
-	/* Write USB3.0_TYPE_A_PWR_EN */
-	write_ioexpander(0, 5, 1);
-}
-
-/* Enable all ioexpander outputs. */
-static void init_ioexpander(void)
-{
-	/* Write all GPIO to output 0 */
-	i2c_write8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_OUT_PORT_A, 0x0);
-	i2c_write8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_OUT_PORT_B, 0x0);
-
-	/*
-	 * Write GPIO direction: strap resistors to input,
-	 * all others to output.
-	 */
-	i2c_write8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_A, 0x0);
-	i2c_write8(1, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_B, 0x18);
-}
-
-/*
- * Define voltage thresholds for SBU USB detection.
- *
- * Max observed USB low across sampled systems: 666mV
- * Min observed USB high across sampled systems: 3026mV
- */
-#define GND_MAX_MV	700
-#define USB_HIGH_MV	2500
-#define SBU_DIRECT	0
-#define SBU_FLIP	1
-
-#define MODE_SBU_DISCONNECT	0
-#define MODE_SBU_CONNECT	1
-#define MODE_SBU_FLIP		2
-#define MODE_SBU_OTHER		3
-
-static void ccd_measure_sbu(void);
-DECLARE_DEFERRED(ccd_measure_sbu);
-static void ccd_measure_sbu(void)
-{
-	int sbu1;
-	int sbu2;
-	int mux_en;
-	static int count /* = 0 */;
-	static int last /* = 0 */;
-	static int polarity /* = 0 */;
-
-	/* Read sbu voltage levels */
-	sbu1 = adc_read_channel(ADC_SBU1_DET);
-	sbu2 = adc_read_channel(ADC_SBU2_DET);
-	mux_en = gpio_get_level(GPIO_SBU_MUX_EN);
-
-	/*
-	 * While SBU_MUX is disabled (SuzyQ unplugged), we'll poll the SBU lines
-	 * to check if an idling, unconfigured USB device is present.
-	 * USB FS pulls one line high for connect request.
-	 * If so, and it persists for 500ms, we'll enable the SuzyQ in that
-	 * orientation.
-	 */
-	if ((!mux_en) && (sbu1 > USB_HIGH_MV) && (sbu2 < GND_MAX_MV)) {
-		/* Check flip connection polarity. */
-		if (last != MODE_SBU_FLIP) {
-			last = MODE_SBU_FLIP;
-			polarity = SBU_FLIP;
-			count = 0;
-		} else {
-			count++;
-		}
-	} else if ((!mux_en) && (sbu2 > USB_HIGH_MV) && (sbu1 < GND_MAX_MV)) {
-		/* Check direct connection polarity. */
-		if (last != MODE_SBU_CONNECT) {
-			last = MODE_SBU_CONNECT;
-			polarity = SBU_DIRECT;
-			count = 0;
-		} else {
-			count++;
-		}
-	/*
-	 * If SuzyQ is enabled, we'll poll for a persistent no-signal for
-	 * 500ms. Since USB is differential, we should never see GND/GND
-	 * while the device is connected.
-	 * If disconnected, electrically remove SuzyQ.
-	 */
-	} else if ((mux_en) && (sbu1 < GND_MAX_MV) && (sbu2 < GND_MAX_MV)) {
-		/* Check for SBU disconnect if connected. */
-		if (last != MODE_SBU_DISCONNECT) {
-			last = MODE_SBU_DISCONNECT;
-			count = 0;
-		} else {
-			count++;
-		}
-	} else {
-		/* Didn't find anything, reset state. */
-		last = MODE_SBU_OTHER;
-		count = 0;
-	}
-
-	/*
-	 * We have seen a new state continuously for 500ms.
-	 * Let's update the mux to enable/disable SuzyQ appropriately.
-	 */
-	if (count > 5) {
-		if (mux_en) {
-			/* Disable mux as it's disconnected now. */
-			gpio_set_level(GPIO_SBU_MUX_EN, 0);
-			msleep(10);
-			CPRINTS("CCD: disconnected.");
-		} else {
-			/* SBU flip = polarity */
-			write_ioexpander(0, 2, polarity);
-			gpio_set_level(GPIO_SBU_MUX_EN, 1);
-			msleep(10);
-			CPRINTS("CCD: connected %s",
-				polarity ? "flip" : "noflip");
-		}
-	}
-
-	/* Measure every 100ms, forever. */
-	hook_call_deferred(&ccd_measure_sbu_data, 100 * MSEC);
-}
-
-void ext_hpd_detection_enable(int enable)
-{
-	if (enable) {
-		timestamp_t now = get_time();
-
-		hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
-		hpd_prev_ts = now.val;
-		gpio_enable_interrupt(GPIO_DP_HPD);
-	} else {
-		gpio_disable_interrupt(GPIO_DP_HPD);
-	}
-}
-
-void ccd_enable(int enable)
-{
-	if (enable) {
-		hook_call_deferred(&ccd_measure_sbu_data, 0);
-	} else {
-		gpio_set_level(GPIO_SBU_MUX_EN, 0);
-		hook_call_deferred(&ccd_measure_sbu_data, -1);
-	}
-}
-
-int board_get_version(void)
-{
-	static int ver = -1;
-
-	if (ver < 0) {
-		uint8_t id0, id1;
-
-		id0 = read_ioexpander_bit(1, 3);
-		id1 = read_ioexpander_bit(1, 4);
-
-		ver = (id1 * 2) + id0;
-		CPRINTS("Board ID = %d", ver);
-	}
-
-	return ver;
-}
-
-static void board_init(void)
-{
-	/* USB to serial queues */
-	queue_init(&usart3_to_usb);
-	queue_init(&usb_to_usart3);
-	queue_init(&usart4_to_usb);
-	queue_init(&usb_to_usart4);
-
-	/* UART init */
-	usart_init(&usart3);
-	usart_init(&usart4);
-
-	/* Delay DUT hub to avoid brownout. */
-	usleep(1000);
-	gpio_set_flags(GPIO_DUT_HUB_USB_RESET_L, GPIO_OUT_HIGH);
-
-	/*
-	 * Disable USB3 mode in PS8742 USB/DP Mux.
-	 */
-	i2c_write8(I2C_PORT_MASTER, PS8740_I2C_ADDR0_FLAG, PS8740_REG_MODE, 0);
-
-	/* Enable uservo USB by default. */
-	init_ioexpander();
-	init_uservo_port();
-	init_usb3_port();
-
-	/* Clear BBRAM, we don't want any PD state carried over on reset. */
-	system_set_bbram(SYSTEM_BBRAM_IDX_PD0, 0);
-	system_set_bbram(SYSTEM_BBRAM_IDX_PD1, 0);
-
-	/*
-	 * Disable SBU mux. The polarity is set each time a presense is detected
-	 * on SBU, and wired thorugh. On missing voltage on SBU. SBU wires are
-	 * disconnected.
-	 */
-	gpio_set_level(GPIO_SBU_MUX_EN, 0);
-
-	/*
-	 * Voltage transition needs to occur in lockstep between the CHG and
-	 * DUT ports, so initially limit voltage to 5V.
-	 */
-	pd_set_max_voltage(PD_MIN_MV);
-
-	/* Enable VBUS detection to wake PD tasks fast enough */
-	gpio_enable_interrupt(GPIO_USB_DET_PP_CHG);
-	gpio_enable_interrupt(GPIO_USB_DET_PP_DUT);
-
-	hook_call_deferred(&ccd_measure_sbu_data, 1000 * MSEC);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/servo_v4/board.h b/board/servo_v4/board.h
deleted file mode 100644
index f932752ef4..0000000000
--- a/board/servo_v4/board.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Servo V4 configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_LTO
-
-/* Free up flash space */
-#ifdef SECTION_IS_RO
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#endif
-
-/*
- * Board Versions:
- * Versions are designated by the PCB color and consist of red, blue, and
- * black. Only the black version has pullup resistors to distinguish its board
- * id from previous versions.
- */
-#define BOARD_VERSION_BLACK 3
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Enable USART1,3,4 and USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART3
-#define CONFIG_STREAM_USART4
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-#define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x501b
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_UPDATE
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-
-#define CONFIG_USB_SELF_POWERED
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-#define CONFIG_MAC_ADDR
-#define DEFAULT_MAC_ADDR "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_HIBERNATE
-
-/* Remove console commands / features for flash / RAM savings */
-#undef CONFIG_USB_PD_HOST_CMD
-#undef CONFIG_CONSOLE_CMDHELP
-#undef CONFIG_CONSOLE_HISTORY
-#undef CONFIG_CMD_CRASH
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_FLASH_WP
-#undef CONFIG_CMD_GETTIME
-#undef CONFIG_CMD_MEM
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_CMD_SYSLOCK
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_CMD_WAITMS
-#undef CONFIG_CMD_USART_INFO
-#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
-
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 1
-
-/* PD features */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_BOARD_PRE_INIT
-/*
- * If task profiling is enabled then the rx falling edge detection interrupts
- * can't be processed in time and can't support USB PD messaging.
- */
-#undef CONFIG_TASK_PROFILING
-
-#define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_CMD_PD
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DYNAMIC_SRC_CAP
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#undef CONFIG_USB_PD_PULLUP
-#define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_PD_ONLY_FIXED_PDOS
-
-/* Don't automatically change roles */
-#undef CONFIG_USB_PD_INITIAL_DRP_STATE
-#define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
-
-/* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
-
-/*
- * TODO(crosbug.com/p/60792): The delay values are currently just place holders
- * and the delay will need to be relative to the circuitry that allows VBUS to
- * be supplied to the DUT port from the CHG port.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-/*
- * Define PDO selection logic for SourceCap.
- * On a 45W PD charger, it might provide PDOs with 15V/3A and 20V/2.25A.
- * In this case, pd_find_pdo_index() would always prefer 15V/3A rather than
- * 20V/2.25A and such that the 20V PDO will be disappeared when servo-v4
- * advertise the SrcCap. We define PD_PREFER_HIGH_VOLTAGE so that all the
- * PDOs could be advertised by servo-v4.
- */
-#define PD_PREFER_HIGH_VOLTAGE
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_USART3_STREAM_NAME,
-	USB_STR_USART4_STREAM_NAME,
-	USB_STR_UPDATE_NAME,
-	USB_STR_COUNT
-};
-
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CHG_CC1_PD,
-	ADC_CHG_CC2_PD,
-	ADC_DUT_CC1_PD,
-	ADC_DUT_CC2_PD,
-	ADC_SBU1_DET,
-	ADC_SBU2_DET,
-	ADC_SUB_C_REF,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/**
- * Compare cc_voltage to disconnect threshold
- *
- * This function can be used for boards that support variable Rp settings and
- * require a different voltage threshold based on the Rp value attached to a
- * given cc line.
- *
- * @param port USB-C port number
- * @param cc_volt voltage measured in mV of the CC line
- * @param cc_sel cc1 or cc2 selection
- * @return 1 if voltage is >= threshold value for disconnect
- */
-int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel);
-
-/**
- * Compare cc_voltage to Ra threshold
- *
- * This function can be used for boards that support variable Rp settings and
- * require a different voltage threshold based on the Rp value attached to a
- * given cc line.
- *
- * @param port USB-C port number
- * @param cc_volt voltage measured in mV of the CC line
- * @param cc_sel cc1 or cc2 selection
- * @return 1 if voltage is < threshold value for Ra attach
- */
-int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel);
-
-/**
- * Set Rp or Rd resistor for CC lines
- *
- * This function is used to configure the CC pullup or pulldown resistor to
- * the requested value.
- *
- * @param port USB-C port number
- * @param cc_pull 1 for Rp and 0 for Rd
- * @param rp_value If cc_pull == 1, the value of Rp to use
- * @return 1 if cc_pull == 1 and Rp is invalid, otherwise 0
- */
-int pd_set_rp_rd(int port, int cc_pull, int rp_value);
-
-/**
- * Get board HW ID version
- *
- * @return HW ID version
- */
-int board_get_version(void);
-
-/**
- * Enable or disable external HPD detection
- *
- * @param enable Enable external HPD detection if true, otherwise disable
- */
-void ext_hpd_detection_enable(int enable);
-
-/**
- * Enable or disable CCD
- *
- * @param enable Enable CCD if true, otherwise disable
- */
-void ccd_enable(int enable);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/servo_v4/build.mk b/board/servo_v4/build.mk
deleted file mode 100644
index 6336bbfab6..0000000000
--- a/board/servo_v4/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Not enough SRAM: Disable all tests
-test-list-y=
-
-board-y=board.o
-board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-
-all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/servo_v4/ec.tasklist b/board/servo_v4/ec.tasklist
deleted file mode 100644
index 2111c6b761..0000000000
--- a/board/servo_v4/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, TRENTA_TASK_STACK_SIZE)
diff --git a/board/servo_v4/gpio.inc b/board/servo_v4/gpio.inc
deleted file mode 100644
index 76b9a06d0f..0000000000
--- a/board/servo_v4/gpio.inc
+++ /dev/null
@@ -1,81 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-GPIO_INT(USB_DET_PP_CHG,	PIN(C, 13), GPIO_INT_BOTH, vbus0_evt)
-GPIO_INT(USB_DET_PP_DUT,	PIN(C, 12), GPIO_INT_BOTH, vbus1_evt)
-GPIO_INT(DP_HPD,                PIN(A, 14), GPIO_INT_BOTH, hpd_evt)
-
-/* Outputs */
-GPIO(DUT_CHG_EN,		PIN(A, 10), GPIO_OUT_LOW)
-GPIO(HOST_OR_CHG_CTL,		PIN(A, 13), GPIO_OUT_HIGH)
-GPIO(SBU_UART_SEL,		PIN(A, 15), GPIO_OUT_LOW)
-GPIO(HOST_USB_HUB_RESET_L,	PIN(D, 2),  GPIO_OUT_HIGH)
-GPIO(FASTBOOT_DUTHUB_MUX_SEL,	PIN(B, 5),  GPIO_OUT_HIGH)
-GPIO(SBU_MUX_EN,		PIN(B, 6),  GPIO_OUT_LOW)
-GPIO(FASTBOOT_DUTHUB_MUX_EN_L,	PIN(B, 7),  GPIO_OUT_LOW)
-/* Power on init has reset asserted, we will pull the hub out of reset
- * in the board init to help avoid brownout.
- */
-GPIO(DUT_HUB_USB_RESET_L,	PIN(B, 9),  GPIO_OUT_LOW)
-GPIO(ATMEL_HWB_L,		PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(CMUX_EN,			PIN(C, 14), GPIO_OUT_HIGH)
-GPIO(EMMC_MUX_EN_L,		PIN(F, 0),  GPIO_OUT_HIGH)
-GPIO(EMMC_PWR_EN,		PIN(F, 1),  GPIO_OUT_LOW)
-
-/* Inputs */
-GPIO(USERVO_FAULT_L,		PIN(A, 8),  GPIO_INPUT)
-GPIO(USB_FAULT_L,		PIN(A, 9),  GPIO_INPUT)
-GPIO(DONGLE_DET,		PIN(C, 15), GPIO_INPUT)
-
-/* Type-C */
-/* PD RX/TX */
-GPIO(USB_C_REF,			PIN(A, 1),  GPIO_ANALOG)
-GPIO(USB_CHG_CC1_PD,		PIN(A, 2),  GPIO_ANALOG)
-GPIO(USB_CHG_CC2_PD,		PIN(A, 4),  GPIO_ANALOG)
-GPIO(USB_DUT_CC1_PD,		PIN(A, 0),  GPIO_ANALOG)
-GPIO(USB_DUT_CC2_PD,		PIN(A, 5),  GPIO_ANALOG)
-
-GPIO(USB_CHG_CC1_TX_DATA,	PIN(B, 4),  GPIO_INPUT)
-GPIO(USB_CHG_CC2_TX_DATA,	PIN(A, 6),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_TX_DATA,	PIN(B, 14), GPIO_INPUT)
-GPIO(USB_DUT_CC2_TX_DATA,	PIN(C, 2),  GPIO_INPUT)
-
-GPIO(USB_DUT_CC1_RP3A0,		PIN(C, 0),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RP1A5,		PIN(C, 1),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RPUSB,		PIN(C, 3),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RD,		PIN(C, 6),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RA,		PIN(C, 7),  GPIO_INPUT)
-
-GPIO(USB_DUT_CC2_RP3A0,		PIN(C, 8),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RP1A5,		PIN(C, 9),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RPUSB,		PIN(B, 0),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RD,		PIN(B, 1),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RA,		PIN(B, 2),  GPIO_INPUT)
-
-/* Alternate PD functions */
-GPIO(USB_CHG_TX_CLKOUT,       PIN(B, 8),  GPIO_INPUT)
-GPIO(USB_CHG_TX_CLKIN,        PIN(B, 3),  GPIO_INPUT)
-GPIO(USB_DUT_TX_CLKOUT,       PIN(B, 15), GPIO_INPUT)
-GPIO(USB_DUT_TX_CLKIN,        PIN(B, 13), GPIO_INPUT)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(MASTER_I2C_SCL,		PIN(B, 10), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,		PIN(B, 11), GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(C, 0x0030), 1, MODULE_USART, 0) /* USART3: PC4/PC5 - Servo DUT UART */
-ALTERNATE(PIN_MASK(C, 0x0C00), 0, MODULE_USART, 0) /* USART4: PC10/PC11 - Servo UART3 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_I2C, GPIO_ODR_HIGH) /* I2C MASTER:PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1_SCK:  PB3   */
-ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2_SCK:  PB13  */
-ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8   */
-ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15  */
-
diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h
deleted file mode 100644
index b865057618..0000000000
--- a/board/servo_v4/usb_pd_config.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "chip/stm32/registers.h"
-#include "console.h"
-#include "gpio.h"
-#include "ec_commands.h"
-#include "usb_pd_tcpm.h"
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* NOTES: Servo V4 and glados equivalents:
- *	Glados		Servo V4
- *	C0		CHG
- *	C1		DUT
- *
- */
-#define CHG 0
-#define DUT 1
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_CHG 16
-#define TIM_CLOCK_PD_RX_CHG 1
-#define TIM_CLOCK_PD_TX_DUT 15
-#define TIM_CLOCK_PD_RX_DUT 3
-
-/* Timer channel */
-#define TIM_TX_CCR_CHG 1
-#define TIM_RX_CCR_CHG 1
-#define TIM_TX_CCR_DUT 2
-#define TIM_RX_CCR_DUT 1
-
-#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_DUT : TIM_CLOCK_PD_TX_CHG)
-#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_DUT : TIM_CLOCK_PD_RX_CHG)
-
-/* RX timer capture/compare register */
-#define TIM_CCR_CHG (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_CHG, TIM_RX_CCR_CHG))
-#define TIM_CCR_DUT (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_DUT, TIM_RX_CCR_DUT))
-#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_DUT : TIM_CCR_CHG)
-
-/* TX and RX timer register */
-#define TIM_REG_TX_CHG (STM32_TIM_BASE(TIM_CLOCK_PD_TX_CHG))
-#define TIM_REG_RX_CHG (STM32_TIM_BASE(TIM_CLOCK_PD_RX_CHG))
-#define TIM_REG_TX_DUT (STM32_TIM_BASE(TIM_CLOCK_PD_TX_DUT))
-#define TIM_REG_RX_DUT (STM32_TIM_BASE(TIM_CLOCK_PD_RX_DUT))
-#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_DUT : TIM_REG_TX_CHG)
-#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_DUT : TIM_REG_RX_CHG)
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
-
-/* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_PIN_E		BIT(3)   /* Pin assignment E supported */
-#define ALT_DP_MF_PREF		BIT(4)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(5)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(6)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(7)   /* HPD level if overridden */
-
-/* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
-#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
-static inline void spi_enable_clock(int port)
-{
-	if (port == 0)
-		STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-	else
-		STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-}
-
-/* DMA for transmit uses DMA CH3 for CHG and DMA_CH7 for DUT */
-#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH7 : STM32_DMAC_CH3)
-
-/* RX uses COMP1 and TIM1_CH1 on port CHG and COMP2 and TIM3_CH1 for port DUT*/
-/* DUT RX use CMP1, TIM3_CH1, DMA_CH6 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
-/* CHG RX use CMP2, TIM1_CH1, DMA_CH2 */
-#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
-
-#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
-#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
-
-/*
- * EXTI line 21 is connected to the CMP1 output,
- * EXTI line 22 is connected to the CMP2 output,
- * CHG uses CMP2, and DUT uses CMP1.
- */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
-
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* DMA for receive uses DMA_CH2 for CHG and DMA_CH6 for DUT */
-#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH6 : STM32_DMAC_CH2)
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	if (port == 0) {
-		/* 40 MHz pin speed on SPI PB3&4,
-		 * (USB_CHG_TX_CLKIN & USB_CHG_CC1_TX_DATA)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
-		/* 40 MHz pin speed on TIM16_CH1 (PB8),
-		 * (USB_CHG_TX_CLKOUT)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
-	} else {
-		/* 40 MHz pin speed on SPI PB13/14,
-		 * (USB_DUT_TX_CLKIN & USB_DUT_CC1_TX_DATA)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
-		/* 40 MHz pin speed on TIM15_CH2 (PB15) */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
-	}
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	if (port == 0) {
-		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= BIT(12);
-		STM32_RCC_APB2RSTR &= ~BIT(12);
-	} else {
-		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= BIT(14);
-		STM32_RCC_APB1RSTR &= ~BIT(14);
-	}
-}
-
-static const uint8_t tx_gpio[2 /* port */][2 /* polarity */] = {
-	{ GPIO_USB_CHG_CC1_TX_DATA, GPIO_USB_CHG_CC2_TX_DATA },
-	{ GPIO_USB_DUT_CC1_TX_DATA, GPIO_USB_DUT_CC2_TX_DATA },
-};
-static const uint8_t ref_gpio[2 /* port */][2 /* polarity */] = {
-	{ GPIO_USB_CHG_CC1_PD, GPIO_USB_CHG_CC2_PD },
-	{ GPIO_USB_DUT_CC1_PD, GPIO_USB_DUT_CC2_PD },
-};
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-#ifndef VIF_BUILD /* genvif doesn't like tricks with GPIO macros */
-	const struct gpio_info *tx = gpio_list + tx_gpio[port][polarity];
-	const struct gpio_info *ref = gpio_list + ref_gpio[port][polarity];
-
-	/* use directly GPIO registers, latency before the PD preamble is key */
-
-	/* switch the TX pin Mode from Input (00) to Alternate (10) for SPI */
-	STM32_GPIO_MODER(tx->port) |= 2 << ((31 - __builtin_clz(tx->mask)) * 2);
-	/* switch the ref pin Mode from analog (11) to Out (01) for low level */
-	STM32_GPIO_MODER(ref->port) &=
-		~(2 << ((31 - __builtin_clz(ref->mask)) * 2));
-#endif /* !VIF_BUILD */
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	const struct gpio_info *tx = gpio_list + tx_gpio[port][polarity];
-	const struct gpio_info *ref = gpio_list + ref_gpio[port][polarity];
-
-	gpio_set_flags_by_mask(tx->port, tx->mask, GPIO_INPUT);
-	gpio_set_flags_by_mask(ref->port, ref->mask, GPIO_ANALOG);
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	uint32_t val = STM32_COMP_CSR;
-
-	/* Use window mode so that COMP1 and COMP2 share non-inverting input */
-	val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
-
-	if (port == 0) {
-		/* CHG use the right comparator inverted input for COMP2 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
-	} else {
-		/* DUT use the right comparator inverted input for COMP1 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
-	}
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	const struct gpio_info *c2 = gpio_list + GPIO_USB_CHG_CC2_TX_DATA;
-	const struct gpio_info *c1 = gpio_list + GPIO_USB_CHG_CC1_TX_DATA;
-	const struct gpio_info *d2 = gpio_list + GPIO_USB_DUT_CC2_TX_DATA;
-	const struct gpio_info *d1 = gpio_list + GPIO_USB_DUT_CC1_TX_DATA;
-
-	gpio_config_module(MODULE_USB_PD, 1);
-	/* Select the proper alternate SPI function on TX_DATA pins */
-	/* USB_CHG_CC2_TX_DATA: PA6 is SPI1 MISO (AF0) */
-	gpio_set_alternate_function(c2->port, c2->mask, 0);
-	gpio_set_flags_by_mask(c2->port, c2->mask, GPIO_INPUT);
-	/* USB_CHG_CC1_TX_DATA: PB4 is SPI1 MISO (AF0) */
-	gpio_set_alternate_function(c1->port, c1->mask, 0);
-	gpio_set_flags_by_mask(c1->port, c1->mask, GPIO_INPUT);
-	/* USB_DUT_CC2_TX_DATA: PC2 is SPI2 MISO (AF1) */
-	gpio_set_alternate_function(d2->port, d2->mask, 1);
-	gpio_set_flags_by_mask(d2->port, d2->mask, GPIO_INPUT);
-	/* USB_DUT_CC1_TX_DATA: PB14 is SPI2 MISO (AF0) */
-	gpio_set_alternate_function(d1->port, d1->mask, 0);
-	gpio_set_flags_by_mask(d1->port, d1->mask, GPIO_INPUT);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	/*
-	 * CHG (port == 0) port has fixed Rd attached and therefore can only
-	 * present as a SNK device. If port != DUT (port == 1), then nothing to
-	 * do in this function.
-	 */
-	if (!port)
-		return;
-
-	if (enable) {
-		/*
-		 * Servo_v4 in SRC mode acts as a DTS (debug test
-		 * accessory) and needs to present Rp on both CC
-		 * lines. In order to support orientation detection, and
-		 * advertise the correct TypeC current level, the
-		 * values of Rp1/Rp2 need to asymmetric with Rp1 > Rp2. This
-		 * function is called without a specified Rp value so assume the
-		 * servo_v4 default of USB level current. If a higher current
-		 * can be supported, then the Rp value will get adjusted when
-		 * VBUS is enabled.
-		 */
-		pd_set_rp_rd(port, TYPEC_CC_RP, TYPEC_RP_USB);
-
-		gpio_set_flags(GPIO_USB_DUT_CC1_TX_DATA, GPIO_INPUT);
-		gpio_set_flags(GPIO_USB_DUT_CC2_TX_DATA, GPIO_INPUT);
-	} else {
-		/* Select Rd, the Rp value is a don't care */
-		pd_set_rp_rd(port, TYPEC_CC_RD, TYPEC_RP_RESERVED);
-	}
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   VBUS, charge path based on power role.
- *   Physical layer CC transmit.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/*
-	 * Set CC pull resistors. The PD state machine will then transit and
-	 * enable VBUS after it detects valid voltages on CC lines.
-	 */
-	pd_set_host_mode(port, power_role);
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-
-}
-
-int pd_adc_read(int port, int cc);
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/servo_v4/usb_pd_policy.c b/board/servo_v4/usb_pd_policy.c
deleted file mode 100644
index 00eaa1e628..0000000000
--- a/board/servo_v4/usb_pd_policy.c
+++ /dev/null
@@ -1,1419 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-/* Just want the .h file for PS8742 definitions, not the large object file. */
-#define CONFIG_USB_MUX_PS8742
-#include "ps8740.h"
-#undef CONFIG_USB_MUX_PS8742
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
-
-#define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
-
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
-
-/* Macros to config the PD role */
-#define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-
-/* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
-		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
-		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
-		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
-		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
-	} while (0)
-
-#define DUT_ACTIVE_CC_PU(r) DUT_ACTIVE_CC_SET(r, GPIO_OUT_HIGH)
-#define DUT_INACTIVE_CC_PU(r) DUT_INACTIVE_CC_SET(r, GPIO_OUT_HIGH)
-#define DUT_ACTIVE_CC_PD(r) DUT_ACTIVE_CC_SET(r, GPIO_OUT_LOW)
-#define DUT_BOTH_CC_PD(r) DUT_BOTH_CC_SET(r, GPIO_OUT_LOW)
-#define DUT_BOTH_CC_OPEN(r) DUT_BOTH_CC_SET(r, GPIO_INPUT)
-
-/*
- * Dynamic PDO that reflects capabilities present on the CHG port. Allow for
- * multiple entries so that we can offer greater than 5V charging. The 1st
- * entry will be fixed 5V, but its current value may change based on the CHG
- * port vbus info. Subsequent entries are used for when offering vbus greater
- * than 5V.
- */
-static const uint16_t pd_src_voltages_mv[] = {
-		5000, 9000, 10000, 12000, 15000, 20000,
-};
-static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
-static uint8_t chg_pdo_cnt;
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-struct vbus_prop {
-	int mv;
-	int ma;
-};
-static struct vbus_prop vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
-static int active_charge_port = CHARGE_PORT_NONE;
-static enum charge_supplier active_charge_supplier;
-static uint8_t vbus_rp = TYPEC_RP_RESERVED;
-
-static int cc_config = CC_ALLOW_SRC;
-
-/* Voltage thresholds for no connect in DTS mode */
-static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
-};
-/* Voltage thresholds for Ra attach in DTS mode */
-static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-};
-/* Voltage thresholds for no connect in normal SRC mode */
-static int pd_src_vnc[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_VNC_MV,
-	PD_SRC_1_5_VNC_MV,
-	PD_SRC_3_0_VNC_MV,
-};
-/* Voltage thresholds for Ra attach in normal SRC mode */
-static int pd_src_rd_threshold[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_RD_THRESH_MV,
-	PD_SRC_1_5_RD_THRESH_MV,
-	PD_SRC_3_0_RD_THRESH_MV,
-};
-
-/* Saved value for the duration of faking PD disconnect */
-static int fake_pd_disconnect_duration_us;
-
-/* Shadow what would be in TCPC register state. */
-static int rp_value_stored = TYPEC_RP_USB;
-static int cc_pull_stored = TYPEC_CC_RD;
-
-/*
- * Set the USB PD max voltage to value appropriate for the board version.
- * The red/blue versions of servo_v4 have an ESD between VBUS and CC1/CC2
- * that has a breakdown voltage of 11V.
- */
-#define MAX_MV_RED_BLUE 9000
-
-static int user_limited_max_mv = 20000;
-
-static uint8_t allow_pr_swap = 1;
-static uint8_t allow_dr_swap = 1;
-
-static uint32_t max_supported_voltage(void)
-{
-	int board_max_mv = board_get_version() >= BOARD_VERSION_BLACK ?
-		PD_MAX_VOLTAGE_MV : MAX_MV_RED_BLUE;
-
-	return board_max_mv < user_limited_max_mv ? board_max_mv :
-						    user_limited_max_mv;
-}
-
-static int charge_port_is_active(void)
-{
-	return active_charge_port == CHG && vbus[CHG].mv > 0;
-}
-
-static int is_charge_through_allowed(void)
-{
-	return charge_port_is_active() && cc_config & CC_ALLOW_SRC;
-}
-
-static int get_dual_role_of_src(void)
-{
-	return cc_config & CC_ENABLE_DRP ? PD_DRP_TOGGLE_ON :
-					   PD_DRP_FORCE_SOURCE;
-}
-
-static void dut_allow_charge(void)
-{
-	/*
-	 * Update to charge enable if charger still present and not
-	 * already charging.
-	 */
-	if (is_charge_through_allowed() &&
-	    pd_get_dual_role(DUT) != PD_DRP_FORCE_SOURCE &&
-	    pd_get_dual_role(DUT) != PD_DRP_TOGGLE_ON) {
-		CPRINTS("Enable DUT charge through");
-		pd_set_dual_role(DUT, get_dual_role_of_src());
-		/*
-		 * If DRP role, don't set any CC pull resistor, the PD
-		 * state machine will toggle and set the pull resistors
-		 * when needed.
-		 */
-		if (!(cc_config & CC_ENABLE_DRP))
-			pd_set_host_mode(DUT, 1);
-
-		/*
-		 * Enable PD comm. The PD comm may be disabled during
-		 * the power charge-through was detached.
-		 */
-		pd_comm_enable(DUT, 1);
-
-		pd_update_contract(DUT);
-	}
-}
-DECLARE_DEFERRED(dut_allow_charge);
-
-static void board_manage_dut_port(void)
-{
-	enum pd_dual_role_states allowed_role;
-	enum pd_dual_role_states current_role;
-
-	/*
-	 * This function is called by the CHG port whenever there has been a
-	 * change in its vbus voltage or current. That change may necessitate
-	 * that the DUT port present a different Rp value or renogiate its PD
-	 * contract if it is connected.
-	 */
-
-	/* Assume the default value of Rd */
-	allowed_role = PD_DRP_FORCE_SINK;
-
-	/* If VBUS charge through is available, mark as such. */
-	if (is_charge_through_allowed())
-		allowed_role = get_dual_role_of_src();
-
-	current_role = pd_get_dual_role(DUT);
-	if (current_role != allowed_role) {
-		/* Update role. */
-		if (allowed_role == PD_DRP_FORCE_SINK) {
-			/* We've lost charge through. Disable VBUS. */
-			gpio_set_level(GPIO_DUT_CHG_EN, 0);
-
-			/* Mark as SNK only. */
-			pd_set_dual_role(DUT, PD_DRP_FORCE_SINK);
-			pd_set_host_mode(DUT, 0);
-
-			/*
-			 * Disable PD comm. It matches the user expectation that
-			 * unplugging the power charge-through makes servo v4 as
-			 * a passive hub, without any PD support.
-			 *
-			 * There is an exception that servo v4 is explicitly set
-			 * to have PD, like the "pnsnk" mode.
-			 */
-			pd_comm_enable(DUT, cc_config & CC_SNK_WITH_PD ? 1 : 0);
-		} else {
-			/* Allow charge through after PD negotiate. */
-			hook_call_deferred(&dut_allow_charge_data, 2000 * MSEC);
-		}
-	}
-
-	/*
-	 * Update PD contract to reflect new available CHG
-	 * voltage/current values.
-	 */
-	pd_update_contract(DUT);
-}
-
-static void update_ports(void)
-{
-	int pdo_index, src_index, snk_index, i;
-	uint32_t pdo, max_ma, max_mv, unused;
-
-	/*
-	 * CHG Vbus has changed states, update PDO that reflects CHG port
-	 * state
-	 */
-	if (!charge_port_is_active()) {
-		/* CHG Vbus has dropped, so become SNK. */
-		chg_pdo_cnt = 0;
-	} else {
-		/* Advertise the 'best' PDOs at various discrete voltages */
-		if (active_charge_supplier == CHARGE_SUPPLIER_PD) {
-			src_index = 0;
-			snk_index = -1;
-
-			for (i = 0; i < ARRAY_SIZE(pd_src_voltages_mv); ++i) {
-				/* Adhere to board voltage limits */
-				if (pd_src_voltages_mv[i] >
-				    max_supported_voltage())
-					break;
-
-				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
-					pd_get_src_caps(CHG),
-					pd_src_voltages_mv[i], &pdo);
-				/* Don't duplicate PDOs */
-				if (pdo_index == snk_index)
-					continue;
-				/* Skip battery / variable PDOs */
-				if ((pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-					continue;
-
-				snk_index = pdo_index;
-				pd_extract_pdo_power(pdo, &max_ma, &max_mv,
-						     &unused);
-				pd_src_chg_pdo[src_index++] =
-					PDO_FIXED_VOLT(max_mv) |
-					PDO_FIXED_CURR(max_ma) |
-					DUT_PDO_FIXED_FLAGS |
-					PDO_FIXED_UNCONSTRAINED;
-			}
-			chg_pdo_cnt = src_index;
-		} else {
-			/* 5V PDO */
-			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
-
-			chg_pdo_cnt = 1;
-		}
-	}
-
-	/* Call DUT port manager to update Rp and possible PD contract */
-	board_manage_dut_port();
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	if (charge_port == DUT)
-		return -1;
-
-	active_charge_port = charge_port;
-	update_ports();
-
-	if (!charge_port_is_active())
-		/* Don't negotiate > 5V, except in lockstep with DUT */
-		pd_set_external_voltage_limit(CHG, PD_MIN_MV);
-
-	return 0;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	if (port != CHG)
-		return;
-
-	active_charge_supplier = supplier;
-
-	/* Update the voltage/current values for CHG port */
-	vbus[CHG].ma = charge_ma;
-	vbus[CHG].mv = charge_mv;
-	update_ports();
-}
-
-__override uint8_t board_get_src_dts_polarity(int port)
-{
-	/*
-	 * When servo configured as srcdts, the CC polarity is based
-	 * on the flags.
-	 */
-	if (port == DUT)
-		return !!(cc_config & CC_POLARITY);
-
-	return 0;
-}
-
-int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
-{
-	int rp_index;
-	int nc;
-
-	/* Can never be called from CHG port as it's sink only */
-	if (port == CHG)
-		return 0;
-
-	rp_index = vbus_rp;
-	/*
-	 * If rp_index > 2, then always return not connected. This case should
-	 * only happen when all Rp GPIO controls are tri-stated.
-	 */
-	if (rp_index >= TYPEC_RP_RESERVED)
-		return 1;
-
-	/* Select the correct voltage threshold for current Rp and DTS mode */
-	if (cc_config & CC_DISABLE_DTS)
-		nc = cc_volt >= pd_src_vnc[rp_index];
-	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
-
-	return nc;
-}
-
-int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
-{
-	int rp_index;
-	int ra;
-
-	/* Can never be called from CHG port as it's sink only */
-	if (port == CHG)
-		return 0;
-
-	rp_index = vbus_rp;
-	/*
-	 * If rp_index > 2, then can't be Ra. This case should
-	 * only happen when all Rp GPIO controls are tri-stated.
-	 */
-	if (rp_index >= TYPEC_RP_RESERVED)
-		return 0;
-
-	/* Select the correct voltage threshold for current Rp and DTS mode */
-	if (cc_config & CC_DISABLE_DTS)
-		ra = cc_volt < pd_src_rd_threshold[rp_index];
-	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
-
-	return ra;
-}
-
-/* DUT CC readings aren't valid if we aren't applying CC pulls */
-bool cc_is_valid(void)
-{
-	if ((cc_config & CC_DETACH) || (cc_pull_stored == TYPEC_CC_OPEN) ||
-	    ((cc_pull_stored == TYPEC_CC_RP) &&
-	     (rp_value_stored == TYPEC_RP_RESERVED)))
-		return false;
-	return true;
-}
-
-int pd_adc_read(int port, int cc)
-{
-	int mv;
-	if (port == 0)
-		mv = adc_read_channel(cc ? ADC_CHG_CC2_PD : ADC_CHG_CC1_PD);
-	else if (cc_is_valid()) {
-		/*
-		 * In servo v4 hardware logic, both CC lines are wired directly
-		 * to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
-		 * (CC1 if polarity flip) and make the voltage high as vRd-3.0,
-		 * which makes the PD state mess up. As the PD state machine
-		 * doesn't handle this case. It assumes that CC2 (CC1 if
-		 * polarity flip) is separated by a Type-C cable, resulting a
-		 * voltage lower than the max of vRa.
-		 *
-		 * It fakes the voltage within vRa.
-		 */
-		if ((cc_config & CC_DISABLE_DTS) &&
-		    cc_pull_stored == TYPEC_CC_RD && port == DUT &&
-		    cc == (cc_config & CC_POLARITY ? 0 : 1))
-			mv = 0;
-		else
-			mv = adc_read_channel(cc ? ADC_DUT_CC2_PD :
-						   ADC_DUT_CC1_PD);
-	} else {
-		/*
-		 * When emulating detach, fake the voltage on CC to 0 to avoid
-		 * triggering some debounce logic.
-		 *
-		 * The servo v4 makes Rd/Rp open but the DUT may present Rd/Rp
-		 * alternatively that makes the voltage on CC falls into some
-		 * unexpected range and triggers the PD state machine switching
-		 * between SNK_DISCONNECTED and SNK_DISCONNECTED_DEBOUNCE.
-		 */
-		mv = 0;
-	}
-	return mv;
-}
-
-static int board_set_rp(int rp)
-{
-	if (cc_config & CC_DISABLE_DTS) {
-		/*
-		 * DTS mode is disabled, so only present the requested Rp value
-		 * on CC1 (active) and leave all Rp/Rd resistors on CC2
-		 * (inactive) disconnected.
-		 */
-		switch (rp) {
-		case TYPEC_RP_USB:
-			DUT_ACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_1A5:
-			DUT_ACTIVE_CC_PU(RP1A5);
-			break;
-		case TYPEC_RP_3A0:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			break;
-		case TYPEC_RP_RESERVED:
-			/*
-			 * This case can be used to force a detach event since
-			 * all values are set to inputs above. Nothing else to
-			 * set.
-			 */
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-	} else {
-		/* DTS mode is enabled. The rp parameter is used to select the
-		 * Type C current limit to advertise. The combinations of Rp on
-		 * each CC line is shown in the table below.
-		 *
-		 * CC values for Debug sources (DTS)
-		 *
-		 * Source type  Mode of Operation   CC1    CC2
-		 * ---------------------------------------------
-		 * DTS          Default USB Power   Rp3A0  Rp1A5
-		 * DTS          USB-C @ 1.5 A       Rp1A5  RpUSB
-		 * DTS          USB-C @ 3 A         Rp3A0  RpUSB
-		 */
-		switch (rp) {
-		case TYPEC_RP_USB:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			DUT_INACTIVE_CC_PU(RP1A5);
-			break;
-		case TYPEC_RP_1A5:
-			DUT_ACTIVE_CC_PU(RP1A5);
-			DUT_INACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_3A0:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			DUT_INACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_RESERVED:
-			/*
-			 * This case can be used to force a detach event since
-			 * all values are set to inputs above. Nothing else to
-			 * set.
-			 */
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-	}
-	/* Save new Rp value for DUT port */
-	vbus_rp = rp;
-
-	return EC_SUCCESS;
-}
-
-int pd_set_rp_rd(int port, int cc_pull, int rp_value)
-{
-	int rv = EC_SUCCESS;
-
-	if (port != 1)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* CC is disabled for emulating detach. Don't change Rd/Rp. */
-	if (cc_config & CC_DETACH)
-		return EC_SUCCESS;
-
-	/* By default disconnect all Rp/Rd resistors from both CC lines */
-	/* Set Rd for CC1/CC2 to High-Z. */
-	DUT_BOTH_CC_OPEN(RD);
-	/* Set Rp for CC1/CC2 to High-Z. */
-	DUT_BOTH_CC_OPEN(RP3A0);
-	DUT_BOTH_CC_OPEN(RP1A5);
-	DUT_BOTH_CC_OPEN(RPUSB);
-	/* Set TX Hi-Z */
-	DUT_BOTH_CC_OPEN(TX_DATA);
-
-	if (cc_pull == TYPEC_CC_RP) {
-		rv = board_set_rp(rp_value);
-	} else if (cc_pull == TYPEC_CC_RD) {
-		/*
-		 * The DUT port uses a captive cable. It can present Rd on both
-		 * CC1 and CC2. If DTS mode is enabled, then present Rd on both
-		 * CC lines. However, if DTS mode is disabled only present Rd on
-		 * CC1 (active).
-		 */
-		if (cc_config & CC_DISABLE_DTS)
-			DUT_ACTIVE_CC_PD(RD);
-		else
-			DUT_BOTH_CC_PD(RD);
-
-	}
-
-	rp_value_stored = rp_value;
-	cc_pull_stored = cc_pull;
-
-	return rv;
-}
-
-int board_select_rp_value(int port, int rp)
-{
-	if (port != 1)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/*
-	 * Update Rp value to indicate non-pd power available.
-	 * Do not change pull direction though.
-	 */
-	if ((rp != rp_value_stored) && (cc_pull_stored == TYPEC_CC_RP)) {
-		rp_value_stored = rp;
-		return pd_set_rp_rd(port, TYPEC_CC_RP, rp);
-	}
-
-	return EC_SUCCESS;
-}
-
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	int pdo_cnt = 0;
-
-	/*
-	 * If CHG is providing VBUS, then advertise what's available on the CHG
-	 * port, otherwise we provide no power.
-	 */
-	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
-		pdo_cnt = chg_pdo_cnt;
-	}
-
-	return pdo_cnt;
-}
-
-__override void pd_transition_voltage(int idx)
-{
-	timestamp_t deadline;
-	uint32_t ma, mv, unused;
-
-	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv, &unused);
-	/* Is this a transition to a new voltage? */
-	if (charge_port_is_active() && vbus[CHG].mv != mv) {
-		/*
-		 * Alter voltage limit on charge port, this should cause
-		 * the port to select the desired PDO.
-		 */
-		pd_set_external_voltage_limit(CHG, mv);
-
-		/* Wait for CHG transition */
-		deadline.val = get_time().val + PD_T_PS_TRANSITION;
-		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
-		       get_time().val < deadline.val)
-			msleep(10);
-
-		if (vbus[CHG].mv != mv) {
-			CPRINTS("Missed CHG transition, resetting DUT");
-			pd_power_supply_reset(DUT);
-			return;
-		}
-
-		CPRINTS("CHG transitioned");
-	}
-
-	vbus[DUT].mv = vbus[CHG].mv;
-	vbus[DUT].ma = vbus[CHG].ma;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return EC_ERROR_INVAL;
-
-	if (charge_port_is_active()) {
-		/* Enable VBUS */
-		gpio_set_level(GPIO_DUT_CHG_EN, 1);
-
-		if (vbus[CHG].mv != PD_MIN_MV)
-			CPRINTS("ERROR, CHG port voltage %d != PD_MIN_MV",
-				vbus[CHG].mv);
-
-		vbus[DUT].mv = vbus[CHG].mv;
-		vbus[DUT].ma = vbus[CHG].mv;
-		pd_set_dual_role(DUT, get_dual_role_of_src());
-	} else {
-		vbus[DUT].mv = 0;
-		vbus[DUT].ma = 0;
-		gpio_set_level(GPIO_DUT_CHG_EN, 0);
-		pd_set_dual_role(DUT, PD_DRP_FORCE_SINK);
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return;
-
-	/* Disable VBUS */
-	gpio_set_level(GPIO_DUT_CHG_EN, 0);
-
-	/* DUT is lost, back to 5V limit on CHG */
-	pd_set_external_voltage_limit(CHG, PD_MIN_MV);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/*
-	 * When only host VBUS is available, then servo_v4 is not setting
-	 * PDO_FIXED_UNCONSTRAINED in the src_pdo sent to the DUT. When this bit
-	 * is not set, the DUT will always attempt to swap its power role to
-	 * SRC. Let servo_v4 have more control over its power role by always
-	 * rejecting power swap requests from the DUT.
-	 */
-
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return 0;
-
-	if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC))
-		return 0;
-
-	if (pd_snk_is_vbus_provided(CHG))
-		return allow_pr_swap;
-
-	return 0;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/*
-	 * Servo should allow data role swaps to let DUT see the USB hub, but
-	 * doing it on CHG port is a waste as its data lines is unconnected.
-	 */
-	if (port == CHG)
-		return 0;
-
-	return allow_dr_swap;
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/*
-	 * TODO(b/137887386): Turn on the fastboot/DFU path when data swap to
-	 * DFP?
-	 */
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-	/*
-	 * Don't define any policy to initiate power role swap.
-	 *
-	 * CHG port is SNK only. DUT port requires a user to switch its
-	 * role by commands. So don't do anything implicitly.
-	 */
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-	if (port == CHG)
-		return;
-
-	/* If DFP, try to switch to UFP, to let DUT see the USB hub. */
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
-		pd_request_data_swap(port);
-}
-
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/*
- * DP alt-mode config, user configurable.
- * Default is the mode disabled, supporting the C and D pin assignment,
- * multi-function preferred, and a plug.
- */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
-
-/**
- * Get the pins based on the user config.
- */
-static int alt_dp_config_pins(void)
-{
-	int pins = 0;
-
-	if (alt_dp_config & ALT_DP_PIN_C)
-		pins |= MODE_DP_PIN_C;
-	if (alt_dp_config & ALT_DP_PIN_D)
-		pins |= MODE_DP_PIN_D;
-	if (alt_dp_config & ALT_DP_PIN_E)
-		pins |= MODE_DP_PIN_E;
-	return pins;
-}
-
-/**
- * Get the cable outlet value (plug or receptacle) based on the user config.
- */
-static int alt_dp_config_cable(void)
-{
-	return (alt_dp_config & ALT_DP_PLUG) ? CABLE_PLUG : CABLE_RECEPTACLE;
-}
-
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 0, /* Vbus power required */
-				 AMA_USBSS_U31_GEN1 /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	int dp_supported = (alt_dp_config & ALT_DP_ENABLE) != 0;
-
-	if (dp_supported) {
-		payload[VDO_I(IDH)] = vdo_idh;
-		payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-		payload[VDO_I(PRODUCT)] = vdo_product;
-		payload[VDO_I(AMA)] = vdo_ama;
-		return VDO_I(AMA) + 1;
-	} else {
-		return 0;
-	}
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, 0);
-	return 2;
-}
-
-#define MODE_CNT 1
-#define OPOS 1
-
-/*
- * The Type-C demux PS8742 supports pin assignment C, D, and E. Response the DP
- * capabilities with supporting all of them.
- */
-uint32_t vdo_dp_mode[MODE_CNT];
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
-
-	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
-	if (!(cc_config & CC_DISABLE_DTS))
-		return 0; /* NAK */
-
-	if (PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT)
-		return 0; /* NAK */
-
-	memcpy(payload + 1, vdo_dp_mode, sizeof(vdo_dp_mode));
-	return MODE_CNT + 1;
-}
-
-static int is_typec_dp_muxed(void)
-{
-	int value;
-
-	i2c_read8(I2C_PORT_MASTER, PS8740_I2C_ADDR0_FLAG, PS8740_REG_MODE,
-		  &value);
-	return value & PS8740_MODE_DP_ENABLED ? 1 : 0;
-}
-
-static void set_typec_mux(int pin_cfg)
-{
-	int value;
-
-	switch (pin_cfg) {
-	case 0:
-		value = 0;
-		CPRINTS("PinCfg:off");
-		break;
-	case MODE_DP_PIN_C:
-		value = PS8740_MODE_DP_ENABLED;
-		CPRINTS("PinCfg:C");
-		break;
-	case MODE_DP_PIN_D:
-		value = PS8740_MODE_DP_ENABLED | PS8740_MODE_USB_ENABLED;
-		CPRINTS("PinCfg:D");
-		break;
-	case MODE_DP_PIN_E:
-		value = PS8740_MODE_DP_ENABLED | PS8740_MODE_CE_DP_ENABLED;
-		CPRINTS("PinCfg:E");
-		break;
-	default:
-		CPRINTS("PinCfg not supported: %d", pin_cfg);
-		return;
-	}
-	if (value && cc_config & CC_POLARITY)
-		value |= PS8740_MODE_POLARITY_INVERTED;
-	i2c_write8(I2C_PORT_MASTER, PS8740_I2C_ADDR0_FLAG, PS8740_REG_MODE,
-		   value);
-}
-
-static int get_hpd_level(void)
-{
-	if (alt_dp_config & ALT_DP_OVERRIDE_HPD)
-		return (alt_dp_config & ALT_DP_HPD_LVL) != 0;
-	else
-		return gpio_get_level(GPIO_DP_HPD);
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = get_hpd_level();
-
-	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		is_typec_dp_muxed(),
-		0,                /* power low */
-		hpd ? 0x2 : 0);
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		set_typec_mux(PD_DP_CFG_PIN(payload[1]));
-
-	return 1;
-}
-
-/* Whether alternate mode has been entered or not */
-static int alt_mode;
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
-	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
-
-	alt_mode = OPOS;
-	return 1;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	if (type == TCPCI_MSG_SOP && svid == USB_SID_DISPLAYPORT)
-		return alt_mode;
-
-	return 0;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT)
-		set_typec_mux(0);
-
-	alt_mode = 0;
-
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-
-	/* make sure we have some payload */
-	if (cnt == 0)
-		return 0;
-
-	switch (cmd) {
-	case VDO_CMD_VERSION:
-		/* guarantee last byte of payload is null character */
-		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
-		break;
-	case VDO_CMD_CURRENT:
-		CPRINTF("Current: %dmA\n", payload[1]);
-		break;
-	}
-
-	return 0;
-}
-
-__override const struct svdm_amode_fx supported_modes[] = {};
-__override const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
-
-static void print_cc_mode(void)
-{
-	/* Get current CCD status */
-	ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on");
-	ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on");
-	ccprintf("chg mode: %s\n",
-		 gpio_get_level(GPIO_DUT_CHG_EN) ? "on" : "off");
-	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
-	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
-	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
-}
-
-
-static void do_cc(int cc_config_new)
-{
-	int chargeable;
-	int dualrole;
-
-	if (cc_config_new != cc_config) {
-		if (!(cc_config & CC_DETACH)) {
-			/* Force detach */
-			gpio_set_level(GPIO_DUT_CHG_EN, 0);
-			/* Always set to 0 here so both CC lines are changed */
-			cc_config &= ~(CC_DISABLE_DTS & CC_ALLOW_SRC);
-
-			/* Remove Rp/Rd on both CC lines */
-			pd_comm_enable(DUT, 0);
-			pd_set_rp_rd(DUT, TYPEC_CC_RP, TYPEC_RP_RESERVED);
-
-			/*
-			 * If just changing mode (cc keeps enabled), give some
-			 * time for DUT to detach, use tErrorRecovery.
-			 */
-			if (!(cc_config_new & CC_DETACH))
-				usleep(PD_T_ERROR_RECOVERY);
-		}
-
-		if ((cc_config & ~cc_config_new) & CC_DISABLE_DTS) {
-			/* DTS-disabled -> DTS-enabled */
-			ccd_enable(1);
-			ext_hpd_detection_enable(0);
-		} else if ((cc_config_new & ~cc_config) & CC_DISABLE_DTS) {
-			/* DTS-enabled -> DTS-disabled */
-			ccd_enable(0);
-			if (!(alt_dp_config & ALT_DP_OVERRIDE_HPD))
-				ext_hpd_detection_enable(1);
-		}
-
-		/* Accept new cc_config value */
-		cc_config = cc_config_new;
-
-		if (!(cc_config & CC_DETACH)) {
-			/* Can we source? */
-			chargeable = is_charge_through_allowed();
-			dualrole = chargeable ? get_dual_role_of_src() :
-						PD_DRP_FORCE_SINK;
-			pd_set_dual_role(DUT, dualrole);
-			/*
-			 * If force_source or force_sink role, explicitly set
-			 * the Rp or Rd resistors on CC lines.
-			 *
-			 * If DRP role, don't set any CC pull resistor, the PD
-			 * state machine will toggle and set the pull resistors
-			 * when needed.
-			 */
-			if (dualrole != PD_DRP_TOGGLE_ON)
-				pd_set_host_mode(DUT, chargeable);
-
-			/*
-			 * For the normal lab use, emulating a sink has no PD
-			 * comm, like a passive hub. For the PD FAFT use, we
-			 * need to validate some PD behavior, so a flag
-			 * CC_SNK_WITH_PD to force enabling PD comm.
-			 */
-			if (cc_config & CC_SNK_WITH_PD)
-				pd_comm_enable(DUT, 1);
-			else
-				pd_comm_enable(DUT, chargeable);
-		}
-	}
-}
-
-static int command_cc(int argc, char **argv)
-{
-	int cc_config_new = cc_config;
-
-	if (argc < 2) {
-		print_cc_mode();
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "off")) {
-		cc_config_new |= CC_DETACH;
-	} else if (!strcasecmp(argv[1], "on")) {
-		cc_config_new &= ~CC_DETACH;
-	} else {
-		cc_config_new &= ~CC_DETACH;
-		if (!strcasecmp(argv[1], "src"))
-			cc_config_new = CONF_SRC(cc_config_new);
-		else if (!strcasecmp(argv[1], "snk"))
-			cc_config_new = CONF_SNK(cc_config_new);
-		else if (!strcasecmp(argv[1], "pdsnk"))
-			cc_config_new = CONF_PDSNK(cc_config_new);
-		else if (!strcasecmp(argv[1], "drp"))
-			cc_config_new = CONF_DRP(cc_config_new);
-		else if (!strcasecmp(argv[1], "srcdts"))
-			cc_config_new = CONF_SRCDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "snkdts"))
-			cc_config_new = CONF_SNKDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "pdsnkdts"))
-			cc_config_new = CONF_PDSNKDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "drpdts"))
-			cc_config_new = CONF_DRPDTS(cc_config_new);
-		else
-			return EC_ERROR_PARAM2;
-	}
-
-	if (!strcasecmp(argv[2], "cc1"))
-		cc_config_new &= ~CC_POLARITY;
-	else if (!strcasecmp(argv[2], "cc2"))
-		cc_config_new |= CC_POLARITY;
-	else if (argc >= 3)
-		return EC_ERROR_PARAM3;
-
-	do_cc(cc_config_new);
-	print_cc_mode();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(cc, command_cc,
-			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts] [cc1|cc2]",
-			"Servo_v4 DTS and CHG mode");
-
-static void fake_disconnect_end(void)
-{
-	/* Reenable CC lines with previous dts and src modes */
-	do_cc(cc_config & ~CC_DETACH);
-}
-DECLARE_DEFERRED(fake_disconnect_end);
-
-static void fake_disconnect_start(void)
-{
-	/* Disable CC lines */
-	do_cc(cc_config | CC_DETACH);
-
-	hook_call_deferred(&fake_disconnect_end_data,
-			   fake_pd_disconnect_duration_us);
-}
-DECLARE_DEFERRED(fake_disconnect_start);
-
-static int cmd_fake_disconnect(int argc, char *argv[])
-{
-	int delay_ms, duration_ms;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	delay_ms = strtoi(argv[1], &e, 0);
-	if (*e || delay_ms < 0)
-		return EC_ERROR_PARAM1;
-	duration_ms = strtoi(argv[2], &e, 0);
-	if (*e || duration_ms < 0)
-		return EC_ERROR_PARAM2;
-
-	/* Cancel any pending function calls */
-	hook_call_deferred(&fake_disconnect_start_data, -1);
-	hook_call_deferred(&fake_disconnect_end_data, -1);
-
-	fake_pd_disconnect_duration_us = duration_ms * MSEC;
-	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
-
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
-			"<delay_ms> <duration_ms>", NULL);
-
-static int cmd_ada_srccaps(int argc, char *argv[])
-{
-	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
-
-	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
-		uint32_t max_ma, max_mv, unused;
-
-		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
-		    (ada_srccaps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-			continue;
-
-		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv, &unused);
-		ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
-			"Print adapter SrcCap");
-
-static int cmd_dp_action(int argc, char *argv[])
-{
-	int i;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (argc == 1) {
-		CPRINTS("DP alt-mode: %s",
-			(alt_dp_config & ALT_DP_ENABLE) ? "enable" : "disable");
-	}
-
-	if (!strcasecmp(argv[1], "enable")) {
-		alt_dp_config |= ALT_DP_ENABLE;
-	} else if (!strcasecmp(argv[1], "disable")) {
-		alt_dp_config &= ~ALT_DP_ENABLE;
-	} else if (!strcasecmp(argv[1], "pins")) {
-		if (argc >= 3) {
-			alt_dp_config &= ~(ALT_DP_PIN_C | ALT_DP_PIN_D |
-					   ALT_DP_PIN_E);
-			for (i = 0; i < 3; i++) {
-				if (!argv[2][i])
-					break;
-
-				switch (argv[2][i]) {
-				case 'c':
-				case 'C':
-					alt_dp_config |= ALT_DP_PIN_C;
-					break;
-				case 'd':
-				case 'D':
-					alt_dp_config |= ALT_DP_PIN_D;
-					break;
-				case 'e':
-				case 'E':
-					alt_dp_config |= ALT_DP_PIN_E;
-					break;
-				}
-			}
-		}
-		CPRINTS("Pins: %s%s%s",
-			(alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
-			(alt_dp_config & ALT_DP_PIN_D) ? "D" : "",
-			(alt_dp_config & ALT_DP_PIN_E) ? "E" : "");
-	} else if (!strcasecmp(argv[1], "mf")) {
-		if (argc >= 3) {
-			i = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			if (i)
-				alt_dp_config |= ALT_DP_MF_PREF;
-			else
-				alt_dp_config &= ~ALT_DP_MF_PREF;
-		}
-		CPRINTS("MF pref: %d", (alt_dp_config & ALT_DP_MF_PREF) != 0);
-	} else if (!strcasecmp(argv[1], "plug")) {
-		if (argc >= 3) {
-			i = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			if (i)
-				alt_dp_config |= ALT_DP_PLUG;
-			else
-				alt_dp_config &= ~ALT_DP_PLUG;
-		}
-		CPRINTS("Plug or receptacle: %d",
-			(alt_dp_config & ALT_DP_PLUG) != 0);
-	} else if (!strcasecmp(argv[1], "hpd")) {
-		if (argc >= 3) {
-			if (!strncasecmp(argv[2], "ext", 3)) {
-				alt_dp_config &= ~ALT_DP_OVERRIDE_HPD;
-				ext_hpd_detection_enable(1);
-			} else if (!strncasecmp(argv[2], "h", 1)) {
-				alt_dp_config |= ALT_DP_OVERRIDE_HPD;
-				alt_dp_config |= ALT_DP_HPD_LVL;
-				/*
-				 * Modify the HPD to high. Need to enable the
-				 * external HPD signal monitoring. A monitor
-				 * may send a IRQ at any time to notify DUT.
-				 */
-				ext_hpd_detection_enable(1);
-				pd_send_hpd(DUT, hpd_high);
-			} else if (!strncasecmp(argv[2], "l", 1)) {
-				alt_dp_config |= ALT_DP_OVERRIDE_HPD;
-				alt_dp_config &= ~ALT_DP_HPD_LVL;
-				ext_hpd_detection_enable(0);
-				pd_send_hpd(DUT, hpd_low);
-			} else if (!strcasecmp(argv[2], "irq")) {
-				pd_send_hpd(DUT, hpd_irq);
-			}
-		}
-		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
-		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
-		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
-			"plug]");
-	}
-
-	return EC_SUCCESS;
-}
-
-static int cmd_usbc_action(int argc, char *argv[])
-{
-	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
-		return cmd_dp_action(argc - 1, &argv[1]);
-
-	if (argc != 2 && argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* TODO(b:140256624): drop *v command if we migrate to chg cmd. */
-	if (!strcasecmp(argv[1], "5v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 5000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "12v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 12000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "20v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 20000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "dev")) {
-		/* Set the limit back to original */
-		user_limited_max_mv = 20000;
-		do_cc(CONF_PDSNK(cc_config));
-	} else if (!strcasecmp(argv[1], "pol0")) {
-		do_cc(cc_config & ~CC_POLARITY);
-	} else if (!strcasecmp(argv[1], "pol1")) {
-		do_cc(cc_config | CC_POLARITY);
-	} else if (!strcasecmp(argv[1], "drp")) {
-		/* Toggle the DRP state, compatible with Plankton. */
-		do_cc(cc_config ^ CC_ENABLE_DRP);
-		CPRINTF("DRP = %d, host_mode = %d\n",
-			!!(cc_config & CC_ENABLE_DRP),
-			!!(cc_config & CC_ALLOW_SRC));
-	} else if (!strcasecmp(argv[1], "chg")) {
-		int sink_v;
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		sink_v = atoi(argv[2]);
-		if (!sink_v)
-			return EC_ERROR_PARAM2;
-
-		user_limited_max_mv = sink_v * 1000;
-		do_cc(CONF_SRC(cc_config));
-		update_ports();
-		/*
-		 * TODO(b:140256624): servod captures 'chg SRC' keyword to
-		 * recognize if this command is supported in the firmware.
-		 * Drop this message if when we phase out the usbc_role control.
-		 */
-		ccprintf("CHG SRC %dmV\n", user_limited_max_mv);
-	} else if (!strcasecmp(argv[1], "drswap")) {
-		if (argc == 2) {
-			CPRINTF("allow_dr_swap = %d\n", allow_dr_swap);
-			return EC_SUCCESS;
-		}
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		allow_dr_swap = !!atoi(argv[2]);
-
-	} else if (!strcasecmp(argv[1], "prswap")) {
-		if (argc == 2) {
-			CPRINTF("allow_pr_swap = %d\n", allow_pr_swap);
-			return EC_SUCCESS;
-		}
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		allow_pr_swap = !!atoi(argv[2]);
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(usbc_action, cmd_usbc_action,
-			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)|"
-			"drswap [1|0]|prswap [1|0]",
-			"Set Servo v4 type-C port state");
diff --git a/board/servo_v4/vif_override.xml b/board/servo_v4/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/servo_v4/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c
deleted file mode 100644
index d8616ce340..0000000000
--- a/board/servo_v4p1/board.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Servo V4p1 configuration */
-
-#include "adc.h"
-#include "ccd_measure_sbu.h"
-#include "chg_control.h"
-#include "common.h"
-#include "console.h"
-#include "dacs.h"
-#include <driver/gl3590.h>
-#include "driver/ioexpander/tca64xxa.h"
-#include "ec_version.h"
-#include "fusb302b.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ina231s.h"
-#include "ioexpanders.h"
-#include "pathsel.h"
-#include "pi3usb9201.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "tusb1064.h"
-#include "update_fw.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_gpio.h"
-#include "usb_i2c.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_spi.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#ifdef SECTION_IS_RO
-#define CROS_EC_SECTION "RO"
-#else
-#define CROS_EC_SECTION "RW"
-#endif
-
-/******************************************************************************
- * GPIO interrupt handlers.
- */
-#ifdef SECTION_IS_RO
-static void vbus0_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C0);
-}
-
-static void vbus1_evt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_PD_C1);
-}
-
-static void tca_evt(enum gpio_signal signal)
-{
-	irq_ioexpanders();
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[CHG] = { /* CHG port connected directly to USB 3.0 hub, no mux */ },
-	[DUT] = { /* DUT port with UFP mux */
-		.usb_port = DUT,
-		.i2c_port = I2C_PORT_MASTER,
-		.i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS,
-		.driver = &tusb1064_usb_mux_driver,
-	}
-};
-
-static volatile uint64_t hpd_prev_ts;
-static volatile int hpd_prev_level;
-
-/**
- * Hotplug detect deferred task
- *
- * Called after level change on hpd GPIO to evaluate (and debounce) what event
- * has occurred.  There are 3 events that occur on HPD:
- *    1. low  : downstream display sink is deattached
- *    2. high : downstream display sink is attached
- *    3. irq  : downstream display sink signalling an interrupt.
- *
- * The debounce times for these various events are:
- *   HPD_USTREAM_DEBOUNCE_LVL : min pulse width of level value.
- *   HPD_USTREAM_DEBOUNCE_IRQ : min pulse width of IRQ low pulse.
- *
- * lvl(n-2) lvl(n-1)  lvl   prev_delta  now_delta event
- * ----------------------------------------------------
- * 1        0         1     <IRQ        n/a       low glitch (ignore)
- * 1        0         1     >IRQ        <LVL      irq
- * x        0         1     n/a         >LVL      high
- * 0        1         0     <LVL        n/a       high glitch (ignore)
- * x        1         0     n/a         >LVL      low
- */
-
-void hpd_irq_deferred(void)
-{
-	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	if (dp_mode) {
-		pd_send_hpd(DUT, hpd_irq);
-		ccprintf("HPD IRQ");
-	}
-}
-DECLARE_DEFERRED(hpd_irq_deferred);
-
-void hpd_lvl_deferred(void)
-{
-	int level = gpio_get_level(GPIO_DP_HPD);
-	int dp_mode = pd_alt_mode(1, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	if (level != hpd_prev_level) {
-		/* It's a glitch while in deferred or canceled action */
-		return;
-	}
-
-	if (dp_mode) {
-		pd_send_hpd(DUT, level ? hpd_high : hpd_low);
-		ccprintf("HPD: %d", level);
-	}
-}
-DECLARE_DEFERRED(hpd_lvl_deferred);
-
-static void dp_evt(enum gpio_signal signal)
-{
-	timestamp_t now = get_time();
-	int level = gpio_get_level(signal);
-	uint64_t cur_delta = now.val - hpd_prev_ts;
-
-	/* Store current time */
-	hpd_prev_ts = now.val;
-
-	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data, -1);
-
-	/* It's a glitch.  Previous time moves but level is the same. */
-	if (cur_delta < HPD_USTREAM_DEBOUNCE_IRQ)
-		return;
-
-	if ((!hpd_prev_level && level) &&
-	    (cur_delta < HPD_USTREAM_DEBOUNCE_LVL)) {
-		/* It's an irq */
-		hook_call_deferred(&hpd_irq_deferred_data, 0);
-	} else if (cur_delta >= HPD_USTREAM_DEBOUNCE_LVL) {
-		hook_call_deferred(&hpd_lvl_deferred_data,
-				   HPD_USTREAM_DEBOUNCE_LVL);
-	}
-
-	hpd_prev_level = level;
-}
-
-static void tcpc_evt(enum gpio_signal signal)
-{
-	update_status_fusb302b();
-}
-
-#define HOST_HUB		0
-struct uhub_i2c_iface_t uhub_config[] = {
-	{I2C_PORT_MASTER, GL3590_I2C_ADDR0},
-};
-
-static void host_hub_evt(void)
-{
-	gl3590_irq_handler(HOST_HUB);
-}
-DECLARE_DEFERRED(host_hub_evt);
-
-static void hub_evt(enum gpio_signal signal)
-{
-	hook_call_deferred(&host_hub_evt_data, 0);
-}
-
-static void dut_pwr_evt(enum gpio_signal signal)
-{
-	ccprintf("dut_pwr_evt\n");
-}
-
-/* Enable uservo USB. */
-static void init_uservo_port(void)
-{
-	/* Enable USERVO_POWER_EN */
-	ec_uservo_power_en(1);
-
-	gl3590_enable_ports(0, GL3590_DFP4, 1);
-
-	/* Connect uservo to host hub */
-	uservo_fastboot_mux_sel(0);
-}
-
-void ext_hpd_detection_enable(int enable)
-{
-	if (enable) {
-		timestamp_t now = get_time();
-
-		hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
-		hpd_prev_ts = now.val;
-		gpio_enable_interrupt(GPIO_DP_HPD);
-	} else {
-		gpio_disable_interrupt(GPIO_DP_HPD);
-	}
-}
-#endif /* SECTION_IS_RO */
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/******************************************************************************
- * Board pre-init function.
- */
-
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-
-	/*
-	 * the DMA mapping is :
-	 *  Chan 2 : TIM1_CH1  (CHG RX) - Default mapping
-	 *  Chan 3 : SPI1_TX   (CHG TX) - Default mapping
-	 *  Chan 4 : USART1 TX - Remapped from default Chan 2
-	 *  Chan 5 : USART1 RX - Remapped from default Chan 3
-	 *  Chan 6 : TIM3_CH1  (DUT RX) - Remapped from default Chan 4
-	 *  Chan 7 : SPI2_TX   (DUT TX) - Remapped from default Chan 5
-	 *
-	 * As described in the comments above, both USART1 TX/RX and DUT Tx/RX
-	 * channels must be remapped from the defulat locations. Remapping is
-	 * acoomplished by setting the following bits in the STM32_SYSCFG_CFGR1
-	 * register. Information about this register and its settings can be
-	 * found in section 11.3.7 DMA Request Mapping of the STM RM0091
-	 * Reference Manual
-	 */
-	/* Remap USART1 Tx from DMA channel 2 to channel 4 */
-	STM32_SYSCFG_CFGR1 |= BIT(9);
-	/* Remap USART1 Rx from DMA channel 3 to channel 5 */
-	STM32_SYSCFG_CFGR1 |= BIT(10);
-	/* Remap TIM3_CH1 from DMA channel 4 to channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(30);
-	/* Remap SPI2 Tx from DMA channel 5 to channel 7 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);
-}
-
-/******************************************************************************
- * Set up USB PD
- */
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-
-/******************************************************************************
- * Forward UARTs as a USB serial interface.
- */
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-/******************************************************************************
- * Forward USART3 as a simple USB serial interface.
- */
-
-static struct usart_config const usart3;
-struct usb_stream_config const usart3_usb;
-
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
-
-static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
-
-
-/******************************************************************************
- * Forward USART4 as a simple USB serial interface.
- */
-
-static struct usart_config const usart4;
-struct usb_stream_config const usart4_usb;
-
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
-
-static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
-
-
-/*
- * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
- * UEFI and kernel requirements (see b/183857501).
- */
-const struct usb_interface_descriptor
-USB_IFACE_DESC(USB_IFACE_EMPTY) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_EMPTY,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 0,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = 0,
-	.bInterfaceProtocol = 0,
-	.iInterface         = 0,
-};
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4p1"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-
-/******************************************************************************
- * Initialize board.
- */
-
-int board_get_version(void)
-{
-	return board_id_det();
-}
-
-#ifdef SECTION_IS_RO
-/* Forward declaration */
-static void evaluate_input_power_def(void);
-DECLARE_DEFERRED(evaluate_input_power_def);
-
-static void evaluate_input_power_def(void)
-{
-	int state;
-	static int retry = 3;
-
-	/* Wait until host hub INTR# signal is asserted */
-	state = gpio_get_level(GPIO_USBH_I2C_BUSY_INT);
-	if ((state == 0) && retry--) {
-		hook_call_deferred(&evaluate_input_power_def_data, 100 * MSEC);
-		return;
-	}
-
-	if (retry == 0)
-		CPRINTF("Host hub I2C isn't online, expect issues with its "
-			"behaviour\n");
-
-	gpio_enable_interrupt(GPIO_USBH_I2C_BUSY_INT);
-
-	gl3590_init(HOST_HUB);
-
-	init_uservo_port();
-	init_pathsel();
-}
-#endif
-
-static void board_init(void)
-{
-	/* USB to serial queues */
-	queue_init(&usart3_to_usb);
-	queue_init(&usb_to_usart3);
-	queue_init(&usart4_to_usb);
-	queue_init(&usb_to_usart4);
-
-	/* UART init */
-	usart_init(&usart3);
-	usart_init(&usart4);
-
-	/* Delay DUT hub to avoid brownout. */
-	usleep(MSEC);
-
-	init_pi3usb9201();
-
-	/* Clear BBRAM, we don't want any PD state carried over on reset. */
-	system_set_bbram(SYSTEM_BBRAM_IDX_PD0, 0);
-	system_set_bbram(SYSTEM_BBRAM_IDX_PD1, 0);
-
-#ifdef SECTION_IS_RO
-	init_ioexpanders();
-	CPRINTS("Board ID is %d", board_id_det());
-
-	init_dacs();
-	init_uservo_port();
-	init_pathsel();
-	init_ina231s();
-	init_fusb302b(1);
-	vbus_dischrg_en(0);
-
-	/* Bring atmel part out of reset */
-	atmel_reset_l(1);
-
-	/*
-	 * Get data about available input power. Defer this check, since we need
-	 * to wait for USB2/USB3 enumeration on host hub as well as I2C
-	 * interface of this hub needs to be initialized. Genesys recommends at
-	 * least 100ms.
-	 */
-	hook_call_deferred(&evaluate_input_power_def_data, 100 * MSEC);
-
-	/* Enable DUT USB2.0 pair. */
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
-
-	/* Enable VBUS detection to wake PD tasks fast enough */
-	gpio_enable_interrupt(GPIO_USB_DET_PP_CHG);
-	gpio_enable_interrupt(GPIO_USB_DET_PP_DUT);
-
-	gpio_enable_interrupt(GPIO_STM_FAULT_IRQ_L);
-	gpio_enable_interrupt(GPIO_DP_HPD);
-	gpio_enable_interrupt(GPIO_DUT_PWR_IRQ_ODL);
-
-	/* Disable power to DUT by default */
-	chg_power_select(CHG_POWER_OFF);
-
-	/*
-	 * Voltage transition needs to occur in lockstep between the CHG and
-	 * DUT ports, so initially limit voltage to 5V.
-	 */
-	pd_set_max_voltage(PD_MIN_MV);
-
-	/* Start SuzyQ detection */
-	start_ccd_meas_sbu_cycle();
-#else /* SECTION_IS_RO */
-	CPRINTS("Board ID is %d", board_id_det());
-#endif /* SECTION_IS_RO */
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifdef SECTION_IS_RO
-void tick_event(void)
-{
-	static int i = 0;
-
-	i++;
-	switch (i) {
-	case 1:
-		tca_gpio_dbg_led_k_odl(1);
-		break;
-	case 2:
-		break;
-	case 3:
-		tca_gpio_dbg_led_k_odl(0);
-		break;
-	case 4:
-		i = 0;
-		break;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[0] = {
-		.drv = &tca64xxa_ioexpander_drv,
-		.i2c_host_port = TCA6416A_PORT,
-		.i2c_addr_flags = TCA6416A_ADDR,
-		.flags = TCA64XXA_FLAG_VER_TCA6416A
-	},
-	[1] = {
-		.drv = &tca64xxa_ioexpander_drv,
-		.i2c_host_port = TCA6424A_PORT,
-		.i2c_addr_flags = TCA6424A_ADDR,
-		.flags = TCA64XXA_FLAG_VER_TCA6424A
-	}
-};
-
-#endif /* SECTION_IS_RO */
diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h
deleted file mode 100644
index daf450ded2..0000000000
--- a/board/servo_v4p1/board.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Servo V4p1 configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Use Link-Time Optimizations to try to reduce the firmware code size */
-#define CONFIG_LTO
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Servo V4.1 Ports:
- *  CHG - port 0
- *  DUT - port 1
- */
-#define CHG 0
-#define DUT 1
-
-/*
- * IO expanders I2C addresses and ports
- */
-#define TCA6416A_PORT 1
-#define TCA6416A_ADDR 0x21
-#define TCA6424A_PORT 1
-#define TCA6424A_ADDR 0x23
-
-/*
- * Flash layout: we redefine the sections offsets and sizes as we want to
- * include a pstate region, and will use RO/RW regions of different sizes.
- * RO has size 92K and usb_updater along with the majority of code is placed
- *    here.
- * RW has size 40K and usb_updater and other relevant code is placed here.
- */
-#undef _IMAGE_SIZE
-#undef CONFIG_ROLLBACK_OFF
-#undef CONFIG_ROLLBACK_SIZE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FW_PSTATE_SIZE
-#undef CONFIG_FW_PSTATE_OFF
-#undef CONFIG_SHAREDLIB_SIZE
-#undef CONFIG_RO_MEM_OFF
-#undef CONFIG_RO_STORAGE_OFF
-#undef CONFIG_RO_SIZE
-#undef CONFIG_RW_MEM_OFF
-#undef CONFIG_RW_STORAGE_OFF
-#undef CONFIG_RW_SIZE
-#undef CONFIG_EC_PROTECTED_STORAGE_OFF
-#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#undef CONFIG_EC_WRITABLE_STORAGE_OFF
-#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#undef CONFIG_WP_STORAGE_OFF
-#undef CONFIG_WP_STORAGE_SIZE
-
-#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
-
-
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FLASH_PSTATE_BANK
-
-#define CONFIG_SHAREDLIB_SIZE   0
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (92*1024)
-
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-
-#define CONFIG_RW_MEM_OFF       (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF   0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE_BYTES - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
-
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* Enable USART1,3,4 and USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART3
-#define CONFIG_STREAM_USART4
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* The UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-#define CONFIG_PVD
-/*
- * See 'Programmable voltage detector characteristics' in the
- * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a
- * falling voltage threshold of min:2.09V, max:2.27V.
- */
-#define PVD_THRESHOLD     (1)
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x520d
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_UPDATE
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-
-#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
-#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
-#define CONFIG_USB_SELF_POWERED
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-#define CONFIG_MAC_ADDR
-#define DEFAULT_MAC_ADDR "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* Enable I/O expander */
-#ifdef SECTION_IS_RO
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-#define CONFIG_IO_EXPANDER_TCA64XXA
-#define CONFIG_IO_EXPANDER_PORT_COUNT 2
-#endif
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_HIBERNATE
-
-/* Remove console commands / features for flash / RAM savings */
-#undef CONFIG_USB_PD_HOST_CMD
-#undef CONFIG_CONSOLE_CMDHELP
-#undef CONFIG_CONSOLE_HISTORY
-#undef CONFIG_CMD_CRASH
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_FASTCHARGE
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_GETTIME
-#undef CONFIG_CMD_MEM
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_CMD_SYSLOCK
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_CMD_WAITMS
-
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 1
-
-/* PD features */
-#define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
-#define CONFIG_BOARD_PRE_INIT
-/*
- * If task profiling is enabled then the rx falling edge detection interrupts
- * can't be processed in time and can't support USB PD messaging.
- */
-#undef CONFIG_TASK_PROFILING
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-#ifdef SECTION_IS_RO
-#define CONFIG_USB_HUB_GL3590
-#define CONFIG_INA231
-#define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
-#define CONFIG_USB_MUX_TUSB1064
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_CMD_PD
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DYNAMIC_SRC_CAP
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#undef CONFIG_USB_PD_PULLUP
-/* Default pull-up should not be Rp3a0 due to Cr50 */
-#define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_PD_ONLY_FIXED_PDOS
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_UFP_ONLY
-
-/* Don't automatically change roles */
-#undef CONFIG_USB_PD_INITIAL_DRP_STATE
-#define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
-
-/* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
-
-/*
- * These power-supply timing values are now set towards maximum spec limit,
- * to give the upstream charger the maximum time to respond.
- *
- * Currently tuned with the Apple 96W adapter.
- */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  (161*MSEC)
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461*MSEC)
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       100000
-#define PD_MAX_CURRENT_MA     5000
-#define PD_MAX_VOLTAGE_MV     20000
-
-/* Add the raw option to the i2c_xfer command */
-#define CONFIG_CMD_I2C_XFER_RAW
-
-/* Enable command for managing host hub */
-#define CONFIG_CMD_GL3590
-#else
-#undef CONFIG_CMD_I2C_XFER
-#undef CONFIG_USB_POWER_DELIVERY
-#endif /* SECTION_IS_RO */
-
-/*
- * If task profiling is enabled then the rx falling edge detection interrupts
- * can't be processed in time and can't support USB PD messaging.
- */
-#undef CONFIG_TASK_PROFILING
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_USART3_STREAM_NAME,
-	USB_STR_USART4_STREAM_NAME,
-	USB_STR_UPDATE_NAME,
-	USB_STR_COUNT
-};
-
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CHG_CC1_PD,
-	ADC_CHG_CC2_PD,
-	ADC_DUT_CC1_PD,
-	ADC_DUT_CC2_PD,
-	ADC_SBU1_DET,
-	ADC_SBU2_DET,
-	ADC_SUB_C_REF,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* Servo V4.1 Board ID mappings */
-enum servo_board_id {
-	BOARD_ID_UNSET = -1,
-	BOARD_ID_REV0 = 0, /* Proto */
-	BOARD_ID_REV1 = 1, /* EVT */
-	BOARD_ID_REV2 = 2, /* DVT */
-};
-
-/**
- * Compare cc_voltage to disconnect threshold
- *
- * This function can be used for boards that support variable Rp settings and
- * require a different voltage threshold based on the Rp value attached to a
- * given cc line.
- *
- * @param port USB-C port number
- * @param cc_volt voltage measured in mV of the CC line
- * @param cc_sel cc1 or cc2 selection
- * @return 1 if voltage is >= threshold value for disconnect
- */
-int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel);
-
-/**
- * Compare cc_voltage to Ra threshold
- *
- * This function can be used for boards that support variable Rp settings and
- * require a different voltage threshold based on the Rp value attached to a
- * given cc line.
- *
- * @param port USB-C port number
- * @param cc_volt voltage measured in mV of the CC line
- * @param cc_sel cc1 or cc2 selection
- * @return 1 if voltage is < threshold value for Ra attach
- */
-int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel);
-
-/**
- * Set Rp or Rd resistor for CC lines
- *
- * This function is used to configure the CC pullup or pulldown resistor to
- * the requested value.
- *
- * @param port USB-C port number
- * @param cc_pull 1 for Rp and 0 for Rd
- * @param rp_value If cc_pull == 1, the value of Rp to use
- * @return 1 if cc_pull == 1 and Rp is invalid, otherwise 0
- */
-int pd_set_rp_rd(int port, int cc_pull, int rp_value);
-
-/**
- * Get board HW ID version
- *
- * @return HW ID version
- */
-int board_get_version(void);
-
-/**
- * Enable or disable external HPD detection
- *
- * @param enable Enable external HPD detection if true, otherwise disable
- */
-void ext_hpd_detection_enable(int enable);
-
-/**
- * Enable or disable CCD
- *
- * @param enable Enable CCD if true, otherwise disable
- */
-void ccd_enable(int enable);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/servo_v4p1/build.mk b/board/servo_v4p1/build.mk
deleted file mode 100644
index 872b4d4281..0000000000
--- a/board/servo_v4p1/build.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072RBT6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-# Not enough SRAM: Disable all tests
-test-list-y=
-
-# These files are compiled into RO and RW
-board-y=board.o
-board-y+=ioexpanders.o
-board-y+=dacs.o
-board-y+=pi3usb9201.o
-
-# These files are compiled into RO only
-board-ro+=ccd_measure_sbu.o
-board-ro+=pathsel.o
-board-ro+=chg_control.o
-board-ro+=ina231s.o
-board-ro+=usb_pd_policy.o
-board-ro+=fusb302b.o
-board-ro+=usb_sm.o
-board-ro+=usb_tc_snk_sm.o
-
-all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/servo_v4p1/ccd_measure_sbu.c b/board/servo_v4p1/ccd_measure_sbu.c
deleted file mode 100644
index b9c9680cc9..0000000000
--- a/board/servo_v4p1/ccd_measure_sbu.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* CCD Measure SBU */
-
-#include "adc.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpanders.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/*
- * Define voltage thresholds for SBU USB detection.
- *
- * Max observed USB low across sampled systems: 666mV
- * Min observed USB high across sampled systems: 3026mV
- */
-#define GND_MAX_MV      700
-#define USB_HIGH_MV     2500
-#define SBU_DIRECT      0
-#define SBU_FLIP        1
-
-#define MODE_SBU_DISCONNECT     0
-#define MODE_SBU_CONNECT        1
-#define MODE_SBU_FLIP           2
-#define MODE_SBU_OTHER          3
-
-static void ccd_measure_sbu(void);
-DECLARE_DEFERRED(ccd_measure_sbu);
-static void ccd_measure_sbu(void)
-{
-	int sbu1;
-	int sbu2;
-	int mux_en;
-	static int count /* = 0 */;
-	static int last /* = 0 */;
-	static int polarity /* = 0 */;
-
-	/* Read sbu voltage levels */
-	sbu1 = adc_read_channel(ADC_SBU1_DET);
-	sbu2 = adc_read_channel(ADC_SBU2_DET);
-	mux_en = gpio_get_level(GPIO_SBU_MUX_EN);
-
-	/*
-	 * While SBU_MUX is disabled (SuzyQ unplugged), we'll poll the SBU lines
-	 * to check if an idling, unconfigured USB device is present.
-	 * USB FS pulls one line high for connect request.
-	 * If so, and it persists for 500ms, we'll enable the SuzyQ in that
-	 * orientation.
-	 */
-	if ((!mux_en) && (sbu1 > USB_HIGH_MV) && (sbu2 < GND_MAX_MV)) {
-		/* Check flip connection polarity. */
-		if (last != MODE_SBU_FLIP) {
-			last = MODE_SBU_FLIP;
-			polarity = SBU_FLIP;
-			count = 0;
-		} else {
-			count++;
-		}
-	} else if ((!mux_en) && (sbu2 > USB_HIGH_MV) && (sbu1 < GND_MAX_MV)) {
-		/* Check direct connection polarity. */
-		if (last != MODE_SBU_CONNECT) {
-			last = MODE_SBU_CONNECT;
-			polarity = SBU_DIRECT;
-			count = 0;
-		} else {
-			count++;
-		}
-		/*
-		 * If SuzyQ is enabled, we'll poll for a persistent no-signal
-		 * for 500ms. Since USB is differential, we should never see
-		 * GND/GND while the device is connected.
-		 * If disconnected, electrically remove SuzyQ.
-		 */
-	} else if ((mux_en) && (sbu1 < GND_MAX_MV) && (sbu2 < GND_MAX_MV)) {
-		/* Check for SBU disconnect if connected. */
-		if (last != MODE_SBU_DISCONNECT) {
-			last = MODE_SBU_DISCONNECT;
-			count = 0;
-		} else {
-			count++;
-		}
-	} else {
-		/* Didn't find anything, reset state. */
-		last = MODE_SBU_OTHER;
-		count = 0;
-	}
-
-	/*
-	 * We have seen a new state continuously for 500ms.
-	 * Let's update the mux to enable/disable SuzyQ appropriately.
-	 */
-	if (count > 5) {
-		if (mux_en) {
-			/* Disable mux as it's disconnected now. */
-			gpio_set_level(GPIO_SBU_MUX_EN, 0);
-			msleep(10);
-			CPRINTS("CCD: disconnected.");
-		} else {
-			/* SBU flip = polarity */
-			sbu_flip_sel(polarity);
-			gpio_set_level(GPIO_SBU_MUX_EN, 1);
-			msleep(10);
-			CPRINTS("CCD: connected %s",
-				polarity ? "flip" : "noflip");
-		}
-	}
-
-	/* Measure every 100ms, forever. */
-	hook_call_deferred(&ccd_measure_sbu_data, 100 * MSEC);
-}
-
-void ccd_enable(int enable)
-{
-	if (enable) {
-		hook_call_deferred(&ccd_measure_sbu_data, 0);
-	} else {
-		gpio_set_level(GPIO_SBU_MUX_EN, 0);
-		hook_call_deferred(&ccd_measure_sbu_data, -1);
-	}
-}
-
-void start_ccd_meas_sbu_cycle(void)
-{
-	hook_call_deferred(&ccd_measure_sbu_data, 1000 * MSEC);
-}
diff --git a/board/servo_v4p1/ccd_measure_sbu.h b/board/servo_v4p1/ccd_measure_sbu.h
deleted file mode 100644
index 0dd1ce0de7..0000000000
--- a/board/servo_v4p1/ccd_measure_sbu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CCD_MEASURE_SBU_H
-#define __CROS_EC_CCD_MEASURE_SBU_H
-
-/**
- * Enables or disables CCD for use with SuzyQ cable
- *
- * @param en    0 - Disable CCD
- *              1 - Enable CCD
- */
-void ccd_enable(int enable);
-
-/**
- * Triggers the detection of a SuzyQ cable every 100mS
- */
-void start_ccd_meas_sbu_cycle(void);
-
-#endif /* __CROS_EC_CCD_MEASURE_SBU_H */
diff --git a/board/servo_v4p1/chg_control.c b/board/servo_v4p1/chg_control.c
deleted file mode 100644
index 19be03a755..0000000000
--- a/board/servo_v4p1/chg_control.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chg_control.h"
-#include "gpio.h"
-#include "ioexpanders.h"
-#include "registers.h"
-#include "timer.h"
-#include "usb_pd.h"
-
-#define CHG_P5V_POWER  0
-#define CHG_VBUS_POWER 1
-
-void chg_reset(void)
-{
-	/* Disconnect DUT Power */
-	chg_power_select(CHG_POWER_OFF);
-
-	/* Disconnect CHG CC1(Rd) and CC2(Rd) */
-	chg_attach_cc_rds(0);
-
-	/* Give time for CHG to detach, use tErrorRecovery. */
-	msleep(PD_T_ERROR_RECOVERY);
-
-	/* Connect CHG CC1(Rd) and CC2(Rd) to detect charger */
-	chg_attach_cc_rds(1);
-}
-
-void chg_power_select(enum chg_power_select_t type)
-{
-	switch (type) {
-	case CHG_POWER_OFF:
-		dut_chg_en(0);
-		vbus_dischrg_en(1);
-		break;
-	case CHG_POWER_PP5000:
-		vbus_dischrg_en(0);
-		host_or_chg_ctl(CHG_P5V_POWER);
-		dut_chg_en(1);
-		break;
-	case CHG_POWER_VBUS:
-		vbus_dischrg_en(0);
-		host_or_chg_ctl(CHG_VBUS_POWER);
-		dut_chg_en(1);
-		break;
-	}
-}
-
-void chg_attach_cc_rds(bool en)
-{
-	if (en) {
-		/*
-		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as
-		 * ANALOG input
-		 */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			| (3 << (2*2)) | /* PA2 in ANALOG mode */
-			  (3 << (2*4))); /* PA4 in ANALOG mode */
-	} else {
-		/*
-		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as GPIO and
-		 * drive high to trigger disconnect.
-		 * NOTE: The CC line has an external fixed Rd pull-down.
-		 * Driving the CC line High overrides the pull down and this
-		 * triggers a disconnection.
-		 */
-		/* Set level high */
-		gpio_set_level(GPIO_USB_CHG_CC1_MCU, 1);
-		gpio_set_level(GPIO_USB_CHG_CC2_MCU, 1);
-
-		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*2) | /* PA2 disable ADC */
-			    3 << (2*4))) /* PA4 disable ADC */
-			|  (1 << (2*2) | /* Set as GPO */
-			    1 << (2*4)); /* Set as GPO */
-	}
-}
diff --git a/board/servo_v4p1/chg_control.h b/board/servo_v4p1/chg_control.h
deleted file mode 100644
index 8b81708ccc..0000000000
--- a/board/servo_v4p1/chg_control.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CHG_CONTROL_H
-#define __CROS_EC_CHG_CONTROL_H
-
-#include <stdbool.h>
-
-enum chg_cc_t {
-	CHG_OPEN,
-	CHG_CC1,
-	CHG_CC2
-};
-
-enum chg_power_select_t {
-	CHG_POWER_OFF,
-	CHG_POWER_PP5000,
-	CHG_POWER_VBUS,
-};
-
-/*
- * Triggers a disconnect and reconnect on the DUT Charger port
- */
-void chg_reset(void);
-
-/*
- * Disables or selects the DUT Charger Power source
- *
- * @param type Power source used for DUT
- */
-void chg_power_select(enum chg_power_select_t type);
-
-/*
- * Attaches or Removes the DUT Charger Ports CC1 and CC2 Rd resistors
- *
- * @param en True the CC RDs are attached else they are removed
- */
-void chg_attach_cc_rds(bool en);
-
-#endif /* __CROS_EC_CHG_CONTROL_H */
diff --git a/board/servo_v4p1/dacs.c b/board/servo_v4p1/dacs.c
deleted file mode 100644
index 087a334873..0000000000
--- a/board/servo_v4p1/dacs.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dacs.h"
-#include "i2c.h"
-#include "ioexpanders.h"
-#include "util.h"
-
-#define MAX_MV 5000
-
-#define CC1_DAC_ADDR 0x48
-#define CC2_DAC_ADDR 0x49
-
-#define REG_NOOP    0
-#define REG_DEVID   1
-#define REG_SYNC    2
-#define REG_CONFIG  3
-#define REG_GAIN    4
-#define REG_TRIGGER 5
-#define REG_STATUS  7
-#define REG_DAC     8
-
-#define DAC1	BIT(0)
-#define DAC2	BIT(1)
-
-static uint8_t dac_enabled;
-
-void init_dacs(void)
-{
-	/* Disable both DACS by default */
-	enable_dac(CC1_DAC, 0);
-	enable_dac(CC2_DAC, 0);
-	dac_enabled = 0;
-}
-
-void enable_dac(enum dac_t dac, uint8_t en)
-{
-	switch (dac) {
-	case CC1_DAC:
-		if (en) {
-			fault_clear_cc(1);
-			fault_clear_cc(0);
-			en_vout_buf_cc1(1);
-			/* Power ON DAC */
-			i2c_write8(1, CC1_DAC_ADDR, REG_CONFIG, 0);
-			dac_enabled |= DAC1;
-		} else {
-			en_vout_buf_cc1(0);
-			/* Power OFF DAC */
-			i2c_write8(1, CC1_DAC_ADDR, REG_CONFIG, 1);
-			dac_enabled &= ~DAC1;
-		}
-		break;
-	case CC2_DAC:
-		if (en) {
-			fault_clear_cc(1);
-			fault_clear_cc(0);
-			en_vout_buf_cc2(1);
-			i2c_write8(1, CC2_DAC_ADDR, REG_CONFIG, 0);
-			dac_enabled |= DAC2;
-		} else {
-			en_vout_buf_cc2(0);
-			/* Power down DAC */
-			i2c_write8(1, CC2_DAC_ADDR, REG_CONFIG, 1);
-			dac_enabled &= ~DAC2;
-		}
-		break;
-	}
-}
-
-int write_dac(enum dac_t dac, uint16_t value)
-{
-	uint16_t tmp;
-
-	/*
-	 * Data are MSB aligned in straight binary format, and
-	 * use the following format: DATA[13:0], 0, 0
-	 */
-	tmp = (value << 8) & 0xff00;
-	tmp |= (value >> 8) & 0xff;
-	tmp <<= 2;
-
-	switch (dac) {
-	case CC1_DAC:
-		if (!(dac_enabled & DAC1)) {
-			ccprintf("CC1_DAC is disabled\n");
-			return EC_ERROR_ACCESS_DENIED;
-		}
-		i2c_write16(1, CC1_DAC_ADDR, REG_DAC, tmp);
-		break;
-	case CC2_DAC:
-		if (!(dac_enabled & DAC2)) {
-			ccprintf("CC2_DAC is disabled\n");
-			return EC_ERROR_ACCESS_DENIED;
-		}
-		i2c_write16(1, CC2_DAC_ADDR, REG_DAC, tmp);
-		break;
-	}
-	return EC_SUCCESS;
-}
-
-#ifdef SECTION_IS_RO
-static int cmd_cc_dac(int argc, char *argv[])
-{
-	uint8_t dac;
-	uint64_t mv;
-	uint64_t round_up;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	dac = strtoi(argv[1], &e, 10);
-	if (*e || (dac != CC1_DAC && dac != CC2_DAC))
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(argv[2], "on")) {
-		enable_dac(dac, 1);
-	} else if (!strcasecmp(argv[2], "off")) {
-		enable_dac(dac, 0);
-	} else {
-		/* get value in mV */
-		mv = strtoi(argv[2], &e, 10);
-		/* 5000 mV max */
-		if (*e || mv > MAX_MV)
-			return EC_ERROR_PARAM3;
-		/* 305176 = (5V / 2^14) * 1000000 */
-		/* 152588 = 305176 / 2 : used for round up after division */
-		round_up = (((mv * 1000000) + 152588) / 305176);
-		if (!write_dac(dac, (uint16_t)round_up))
-			ccprintf("Setting DAC to %lld counts\n", round_up);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac,
-			"dac <\"on\"|\"off\"|mv>",
-			"Set Servo v4.1 CC dacs");
-#endif
diff --git a/board/servo_v4p1/dacs.h b/board/servo_v4p1/dacs.h
deleted file mode 100644
index bd0ecd67da..0000000000
--- a/board/servo_v4p1/dacs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_DACS_H
-#define __CROS_EC_DACS_H
-
-#include <stdint.h>
-
-enum dac_t {
-	CC1_DAC = 1,
-	CC2_DAC,
-};
-
-/*
- * Initialize the DACs
- */
-void init_dacs(void);
-
-/*
- * Enable/Disable one of the DACs
- *
- * @param dac DAC to enable or disable
- * @param en 0 to disable or 1 to enable
- */
-void enable_dac(enum dac_t dac, uint8_t en);
-
-/*
- * Write a value to the DAC
- *
- * @param dac DAC to write to
- * @param value to write to the DAC in mV. (0 to 5000mV)
- * @return EC_SUCCESS or EC_ERROR_ACCESS_DENIED on failure
- */
-int write_dac(enum dac_t dac, uint16_t value);
-
-#endif /* __CROS_EC_DACS_H */
diff --git a/board/servo_v4p1/ec.tasklist b/board/servo_v4p1/ec.tasklist
deleted file mode 100644
index 07250f018e..0000000000
--- a/board/servo_v4p1/ec.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,    hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE,  console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RO(PD_C0, pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RO(PD_C1, pd_task,      NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RO(PD_C2, snk_task,     NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/servo_v4p1/fusb302b.c b/board/servo_v4p1/fusb302b.c
deleted file mode 100644
index 4e144dec05..0000000000
--- a/board/servo_v4p1/fusb302b.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "fusb302b.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpanders.h"
-#include "util.h"
-#include "task.h"
-#include "time.h"
-#include "usb_pd.h"
-
-static int port;
-static int status0;
-static int status1;
-static int interrupt;
-static struct mutex measure_lock;
-
-static int tcpc_write(int reg, int val)
-{
-	return i2c_write8(port, FUSB302_I2C_ADDR_FLAGS, reg, val);
-}
-
-static int tcpc_read(int reg, int *val)
-{
-	return i2c_read8(port, FUSB302_I2C_ADDR_FLAGS, reg, val);
-}
-
-int init_fusb302b(int p)
-{
-	int ret;
-	int reg;
-	int interrupta;
-	int interruptb;
-
-	/* Configure fusb302b for SNK only operation */
-	port = p;
-
-	ret = tcpc_write(TCPC_REG_RESET, TCPC_REG_RESET_SW_RESET);
-	if (ret)
-		return ret;
-
-	/* Create interrupt masks */
-	reg = 0xFF;
-	/* CC level changes */
-	reg &= ~TCPC_REG_MASK_BC_LVL;
-	/* misc alert */
-	reg &= ~TCPC_REG_MASK_ALERT;
-	/* VBUS threshold crossed (~4.0V) */
-	reg &= ~TCPC_REG_MASK_VBUSOK;
-	tcpc_write(TCPC_REG_MASK, reg);
-
-	/* Interrupt Enable */
-	ret = tcpc_read(TCPC_REG_CONTROL0, &reg);
-	if (ret)
-		return ret;
-
-	reg &= ~TCPC_REG_CONTROL0_INT_MASK;
-	ret = tcpc_write(TCPC_REG_CONTROL0, reg);
-	if (ret)
-		return ret;
-
-	ret = tcpc_write(TCPC_REG_POWER, TCPC_REG_POWER_PWR_ALL);
-	if (ret)
-		return ret;
-
-	/* reading interrupt registers clears them */
-	ret = tcpc_read(TCPC_REG_INTERRUPT, &interrupt);
-	if (ret)
-		return ret;
-
-
-	ret = tcpc_read(TCPC_REG_INTERRUPTA, &interrupta);
-	if (ret)
-		return ret;
-
-	ret = tcpc_read(TCPC_REG_INTERRUPTB, &interruptb);
-	if (ret)
-		return ret;
-
-	/* Call this, will detect a charger that's already plugged in */
-	update_status_fusb302b();
-
-	/* Enable interrupt */
-	gpio_enable_interrupt(GPIO_CHGSRV_TCPC_INT_ODL);
-
-	return EC_SUCCESS;
-}
-
-void fusb302b_irq(void)
-{
-	tcpc_read(TCPC_REG_INTERRUPT, &interrupt);
-	tcpc_read(TCPC_REG_STATUS0, &status0);
-	tcpc_read(TCPC_REG_STATUS1, &status1);
-
-	task_wake(TASK_ID_PD_C2);
-}
-DECLARE_DEFERRED(fusb302b_irq);
-
-int update_status_fusb302b(void)
-{
-	hook_call_deferred(&fusb302b_irq_data, 0);
-	return EC_SUCCESS;
-}
-
-int is_vbus_present(void)
-{
-	return (status0 & 0x80);
-}
-
-/* Convert BC LVL values (in FUSB302) to Type-C CC Voltage Status */
-static int convert_bc_lvl(int bc_lvl)
-{
-	int ret;
-
-	switch (bc_lvl) {
-	case 1:
-		ret = TYPEC_CC_VOLT_RP_DEF;
-		break;
-	case 2:
-		ret = TYPEC_CC_VOLT_RP_1_5;
-		break;
-	case 3:
-		ret = TYPEC_CC_VOLT_RP_3_0;
-		break;
-	default:
-		ret = TYPEC_CC_VOLT_OPEN;
-	}
-
-	return ret;
-}
-
-int get_cc(int *cc1, int *cc2)
-{
-	int reg;
-	int orig_meas_cc1;
-	int orig_meas_cc2;
-	int bc_lvl_cc1;
-	int bc_lvl_cc2;
-
-	mutex_lock(&measure_lock);
-
-	/*
-	 * Measure CC1 first.
-	 */
-	tcpc_read(TCPC_REG_SWITCHES0, &reg);
-
-	/* save original state to be returned to later... */
-	if (reg & TCPC_REG_SWITCHES0_MEAS_CC1)
-		orig_meas_cc1 = 1;
-	else
-		orig_meas_cc1 = 0;
-
-	if (reg & TCPC_REG_SWITCHES0_MEAS_CC2)
-		orig_meas_cc2 = 1;
-	else
-		orig_meas_cc2 = 0;
-
-
-	/* Disable CC2 measurement switch, enable CC1 measurement switch */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-
-	tcpc_write(TCPC_REG_SWITCHES0, reg);
-
-	/* CC1 is now being measured by FUSB302. */
-
-	/* Wait on measurement */
-	usleep(250);
-
-	tcpc_read(TCPC_REG_STATUS0, &bc_lvl_cc1);
-
-	/* mask away unwanted bits */
-	bc_lvl_cc1 &= (TCPC_REG_STATUS0_BC_LVL0 | TCPC_REG_STATUS0_BC_LVL1);
-
-	/*
-	 * Measure CC2 next.
-	 */
-
-	tcpc_read(TCPC_REG_SWITCHES0, &reg);
-
-	/* Disable CC1 measurement switch, enable CC2 measurement switch */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	tcpc_write(TCPC_REG_SWITCHES0, reg);
-
-	/* CC2 is now being measured by FUSB302. */
-
-	/* Wait on measurement */
-	usleep(250);
-
-	tcpc_read(TCPC_REG_STATUS0, &bc_lvl_cc2);
-
-	/* mask away unwanted bits */
-	bc_lvl_cc2 &= (TCPC_REG_STATUS0_BC_LVL0 | TCPC_REG_STATUS0_BC_LVL1);
-
-	*cc1 = convert_bc_lvl(bc_lvl_cc1);
-	*cc2 = convert_bc_lvl(bc_lvl_cc2);
-
-	/* return MEAS_CC1/2 switches to original state */
-	tcpc_read(TCPC_REG_SWITCHES0, &reg);
-	if (orig_meas_cc1)
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-	else
-		reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	if (orig_meas_cc2)
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-	else
-		reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	tcpc_write(TCPC_REG_SWITCHES0, reg);
-
-	mutex_unlock(&measure_lock);
-	return 0;
-}
diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h
deleted file mode 100644
index ec89c0c207..0000000000
--- a/board/servo_v4p1/fusb302b.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-/* For Fairchild FUSB302 */
-#ifndef __CROS_EC_DRIVER_TCPM_FUSB302_H
-#define __CROS_EC_DRIVER_TCPM_FUSB302_H
-
-/* Chip Device ID - 302A or 302B */
-#define FUSB302_DEVID_302A 0x08
-#define FUSB302_DEVID_302B 0x09
-
-/* I2C address varies by part number */
-/* FUSB302BUCX / FUSB302BMPX */
-#define FUSB302_I2C_ADDR_FLAGS 0x22
-/* FUSB302B01MPX */
-#define FUSB302_I2C_ADDR_B01_FLAGS 0x23
-/* FUSB302B10MPX */
-#define FUSB302_I2C_ADDR_B10_FLAGS 0x24
-/* FUSB302B11MPX */
-#define FUSB302_I2C_ADDR_B11_FLAGS 0x25
-
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
-/*
- * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
- * maximum error, which also matches suggested thresholds in datasheet
- * (Table 3. Host Interrupt Summary).
- */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
-/* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
-/* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
-/* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
-
-/* Tokens defined for the FUSB302 TX FIFO */
-enum fusb302_txfifo_tokens {
-	FUSB302_TKN_TXON = 0xA1,
-	FUSB302_TKN_SYNC1 = 0x12,
-	FUSB302_TKN_SYNC2 = 0x13,
-	FUSB302_TKN_SYNC3 = 0x1B,
-	FUSB302_TKN_RST1 = 0x15,
-	FUSB302_TKN_RST2 = 0x16,
-	FUSB302_TKN_PACKSYM = 0x80,
-	FUSB302_TKN_JAMCRC = 0xFF,
-	FUSB302_TKN_EOP = 0x14,
-	FUSB302_TKN_TXOFF = 0xFE,
-};
-
-/**
- * Initializes the FUSB302 to operate
- * as a SNK only.
- *
- * @param port  The i2c bus of the FUSB302B
- *
- * @returns EC_SUCCESS or EC_XXX on error
- */
-int init_fusb302b(int port);
-
-/**
- * Should be called from the interrupt generated
- * by the FUSB302. This function reads status
- * and interrupt registers in the FUSB302.
- */
-int update_status_fusb302b(void);
-
-/**
- * Returns true if VBUS is present, else false
- */
-int is_vbus_present(void);
-
-/*
- * Reads the status of the CC lines
- *
- * @returns EC_SUCCESS or EC_XXX on failure
- */
-int get_cc(int *cc1, int *cc2);
-
-#endif /* __CROS_EC_DRIVER_TCPM_FUSB302_H */
diff --git a/board/servo_v4p1/gpio.inc b/board/servo_v4p1/gpio.inc
deleted file mode 100644
index 070aa90098..0000000000
--- a/board/servo_v4p1/gpio.inc
+++ /dev/null
@@ -1,127 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef SECTION_IS_RO
-GPIO_INT(USB_DET_PP_CHG,	PIN(C, 13), GPIO_INT_BOTH, vbus0_evt)
-GPIO_INT(USB_DET_PP_DUT,	PIN(C, 12), GPIO_INT_BOTH, vbus1_evt)
-GPIO_INT(STM_FAULT_IRQ_L,	PIN(A, 8),  GPIO_INT_FALLING, tca_evt)
-GPIO_INT(DP_HPD,		PIN(A, 15), GPIO_INT_BOTH, dp_evt)
-GPIO_INT(CHGSRV_TCPC_INT_ODL,	PIN(C, 0),  GPIO_INT_FALLING, tcpc_evt)
-GPIO_INT(USBH_I2C_BUSY_INT,	PIN(C, 9),  GPIO_INT_FALLING, hub_evt)
-GPIO_INT(DUT_PWR_IRQ_ODL,	PIN(F, 1),  GPIO_INT_FALLING, dut_pwr_evt)
-#endif /* SECTION_IS_RO */
-
-/* Outputs */
-GPIO(HOST_USB_HUB_RESET_L,	PIN(D, 2),  GPIO_ODR_HIGH)
-GPIO(FASTBOOT_DUTHUB_MUX_SEL,	PIN(B, 5),  GPIO_OUT_HIGH)
-GPIO(SBU_MUX_EN,		PIN(B, 6),  GPIO_OUT_LOW)
-GPIO(FASTBOOT_DUTHUB_MUX_EN_L,	PIN(B, 7),  GPIO_OUT_LOW)
-/* Power on init has reset asserted, we will pull the hub out of reset
- * in the board init to help avoid brownout.
- */
-GPIO(DUT_HUB_USB_RESET_L,	PIN(B, 9), GPIO_ODR_HIGH)
-GPIO(ATMEL_HWB_L,		PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(USB3_A1_MUX_EN_L,		PIN(F, 0),  GPIO_OUT_HIGH)
-
-/* Inputs */
-
-/* Type-C */
-/* PD RX/TX */
-GPIO(USB_C_REF,			PIN(A, 1),  GPIO_ANALOG)
-GPIO(USB_CHG_CC1_MCU,		PIN(A, 2),  GPIO_ANALOG)
-GPIO(USB_CHG_CC2_MCU,		PIN(A, 4),  GPIO_ANALOG)
-GPIO(USB_DUT_CC1_MCU,		PIN(A, 0),  GPIO_ANALOG)
-GPIO(USB_DUT_CC2_MCU,		PIN(A, 5),  GPIO_ANALOG)
-
-GPIO(USB_CHG_CC1_TX_DATA,	PIN(B, 4),  GPIO_INPUT)
-GPIO(USB_CHG_CC2_TX_DATA,	PIN(A, 6),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_TX_DATA,	PIN(B, 14), GPIO_INPUT)
-GPIO(USB_DUT_CC2_TX_DATA,	PIN(C, 2),  GPIO_INPUT)
-
-GPIO(USB_DUT_CC1_RPUSB,		PIN(C, 3),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RD,		PIN(C, 6),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RA,		PIN(C, 7),  GPIO_INPUT)
-GPIO(USB_DUT_CC1_RP3A0,		PIN(C, 14), GPIO_INPUT)
-GPIO(USB_DUT_CC1_RP1A5,		PIN(C, 15), GPIO_INPUT)
-
-GPIO(USB_DUT_CC2_RPUSB,		PIN(B, 0),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RD,		PIN(B, 1),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RA,		PIN(B, 2),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RP1A5,		PIN(C, 1),  GPIO_INPUT)
-GPIO(USB_DUT_CC2_RP3A0,		PIN(C, 8),  GPIO_INPUT)
-
-/* Alternate PD functions */
-GPIO(USB_CHG_TX_CLKOUT,       PIN(B, 8),  GPIO_INPUT)
-GPIO(USB_CHG_TX_CLKIN,        PIN(B, 3),  GPIO_INPUT)
-GPIO(USB_DUT_TX_CLKOUT,       PIN(B, 15), GPIO_INPUT)
-GPIO(USB_DUT_TX_CLKIN,        PIN(B, 13), GPIO_INPUT)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(MASTER_I2C_SCL,		PIN(B, 10), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,		PIN(B, 11), GPIO_INPUT)
-
-/* IOEX */
-#ifdef SECTION_IS_RO
-
-IOEX(SBU_UART_SEL, 		EXPIN(0, 0, 0), GPIO_OUT_LOW)
-IOEX(ATMEL_RESET_L, 		EXPIN(0, 0, 1), GPIO_OUT_LOW)
-IOEX(SBU_FLIP_SEL, 		EXPIN(0, 0, 2), GPIO_OUT_HIGH)
-IOEX(USB3_A0_MUX_SEL, 		EXPIN(0, 0, 3), GPIO_OUT_HIGH)
-IOEX(USB3_A0_MUX_EN_L, 		EXPIN(0, 0, 4), GPIO_OUT_LOW)
-IOEX(USB3_A0_PWR_EN, 		EXPIN(0, 0, 5), GPIO_OUT_LOW)
-IOEX(UART_18_SEL, 		EXPIN(0, 0, 6), GPIO_OUT_LOW)
-IOEX(USERVO_POWER_EN, 		EXPIN(0, 0, 7), GPIO_OUT_LOW)
-IOEX(USERVO_FASTBOOT_MUX_SEL, 	EXPIN(0, 1, 0), GPIO_OUT_LOW)
-IOEX(USB3_A1_PWR_EN, 		EXPIN(0, 1, 1), GPIO_OUT_LOW)
-IOEX(USB3_A1_MUX_SEL, 		EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-IOEX(BOARD_ID_DET0, 		EXPIN(0, 1, 3), GPIO_INPUT)
-IOEX(BOARD_ID_DET1, 		EXPIN(0, 1, 4), GPIO_INPUT)
-IOEX(BOARD_ID_DET2, 		EXPIN(0, 1, 5), GPIO_INPUT)
-IOEX(VBUS_DISCHRG_EN, 		EXPIN(0, 1, 6), GPIO_OUT_LOW)
-IOEX(DONGLE_DET, 		EXPIN(0, 1, 7), GPIO_INPUT)
-
-IOEX(EN_PP5000_ALT_3P3, 	EXPIN(1, 0, 0), GPIO_OUT_LOW)
-IOEX(EN_PP3300_ETH, 		EXPIN(1, 0, 1), GPIO_OUT_HIGH)
-IOEX(EN_PP3300_DP, 		EXPIN(1, 0, 2), GPIO_OUT_HIGH)
-IOEX(FAULT_CLEAR_CC, 		EXPIN(1, 0, 3), GPIO_OUT_LOW)
-IOEX(EN_VOUT_BUF_CC1, 		EXPIN(1, 0, 4), GPIO_OUT_LOW)
-IOEX(EN_VOUT_BUF_CC2, 		EXPIN(1, 0, 5), GPIO_OUT_LOW)
-IOEX(DUT_CHG_EN, 		EXPIN(1, 0, 6), GPIO_OUT_LOW)
-IOEX(HOST_OR_CHG_CTL, 		EXPIN(1, 0, 7), GPIO_OUT_LOW)
-IOEX(USERVO_FAULT_L, 		EXPIN(1, 1, 0), GPIO_INPUT)
-IOEX(USB3_A0_FAULT_L, 		EXPIN(1, 1, 1), GPIO_INPUT)
-IOEX(USB3_A1_FAULT_L, 		EXPIN(1, 1, 2), GPIO_INPUT)
-IOEX(USB_DUTCHG_FLT_ODL, 	EXPIN(1, 1, 3), GPIO_INPUT)
-IOEX(PP3300_DP_FAULT_L, 	EXPIN(1, 1, 4), GPIO_INPUT)
-IOEX(DAC_BUF1_LATCH_FAULT_L, 	EXPIN(1, 1, 5), GPIO_INPUT)
-IOEX(DAC_BUF2_LATCH_FAULT_L, 	EXPIN(1, 1, 6), GPIO_INPUT)
-IOEX(PP5000_SRC_SEL, 		EXPIN(1, 1, 7), GPIO_INPUT)
-IOEX(HOST_CHRG_DET, 		EXPIN(1, 2, 0), GPIO_INPUT)
-IOEX(USBH_PWRDN_L, 		EXPIN(1, 2, 1), GPIO_OUT_HIGH)
-IOEX(ATMEL_SS,			EXPIN(1, 2, 2), GPIO_INPUT)
-IOEX(ATMEL_SCLK,		EXPIN(1, 2, 3), GPIO_INPUT)
-IOEX(ATMEL_MOSI,		EXPIN(1, 2, 4), GPIO_INPUT)
-IOEX(ATMEL_MISO,		EXPIN(1, 2, 5), GPIO_INPUT)
-IOEX(SYS_PWR_IRQ_ODL, 		EXPIN(1, 2, 6), GPIO_INPUT)
-IOEX(TCA_GPIO_DBG_LED_K_ODL, 	EXPIN(1, 2, 7), GPIO_OUT_LOW)
-
-#endif
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA9/PA10 - Servo DBG UART1 */
-ALTERNATE(PIN_MASK(C, 0x0030), 1, MODULE_USART, 0) /* USART3: PC4/PC5 - Servo DUT UART3 */
-ALTERNATE(PIN_MASK(C, 0x0C00), 0, MODULE_USART, 0) /* USART4: PC10/PC11 - Servo UART4 */
-ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_I2C, GPIO_ODR_HIGH) /* I2C MASTER:PB10/11 */
-ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1_SCK:  PB3   */
-ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2_SCK:  PB13  */
-ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8   */
-ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15  */
-
diff --git a/board/servo_v4p1/ina231s.c b/board/servo_v4p1/ina231s.c
deleted file mode 100644
index 3382686f3f..0000000000
--- a/board/servo_v4p1/ina231s.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "ina2xx.h"
-#include "util.h"
-
-#define PP_DUT_IDX	0
-#define PP_CHG_IDX	1
-#define SR_CHG_IDX	2
-
-void init_ina231s(void)
-{
-	/* Calibrate INA0 (PP DUT) with 1mA/LSB scale */
-	ina2xx_init(PP_DUT_IDX, 0x8000, INA2XX_CALIB_1MA(5 /*mOhm*/));
-
-	/* Calibrate INA1 (PP CHG) with 1mA/LSB scale */
-	ina2xx_init(PP_CHG_IDX, 0x8000, INA2XX_CALIB_1MA(5 /*mOhm*/));
-
-	/* Calibrate INA2 (SR CHG) with 1mA/LSB scale*/
-	ina2xx_init(SR_CHG_IDX, 0x8000, INA2XX_CALIB_1MA(5 /*mOhm*/));
-}
-
-int pp_dut_voltage(void)
-{
-	return ina2xx_get_voltage(PP_DUT_IDX);
-}
-
-int pp_dut_current(void)
-{
-	return ina2xx_get_current(PP_DUT_IDX);
-}
-
-int pp_dut_power(void)
-{
-	return ina2xx_get_power(PP_DUT_IDX);
-}
-
-int pp_chg_voltage(void)
-{
-	return ina2xx_get_voltage(PP_CHG_IDX);
-}
-
-int pp_chg_current(void)
-{
-	return ina2xx_get_current(PP_CHG_IDX);
-}
-
-int pp_chg_power(void)
-{
-	return ina2xx_get_power(PP_CHG_IDX);
-}
-
-int sr_chg_voltage(void)
-{
-	return ina2xx_get_voltage(SR_CHG_IDX);
-}
-
-int sr_chg_current(void)
-{
-	return ina2xx_get_current(SR_CHG_IDX);
-}
-
-int sr_chg_power(void)
-{
-	return ina2xx_get_power(SR_CHG_IDX);
-}
diff --git a/board/servo_v4p1/ina231s.h b/board/servo_v4p1/ina231s.h
deleted file mode 100644
index 9c3804e769..0000000000
--- a/board/servo_v4p1/ina231s.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INA231S_H
-#define __CROS_EC_INA231S_H
-
-/*
- * Initialize the INA231s
- */
-void init_ina231s(void);
-
-/*
- * Return dut vbus voltage in milliVolts
- */
-int pp_dut_voltage(void);
-
-/*
- * Return current in milliAmps
- */
-int pp_dut_current(void);
-
-/*
- * Return power in milliWatts
- */
-int pp_dut_power(void);
-
-/*
- * Return bus voltage in milliVolts
- */
-int pp_chg_voltage(void);
-
-/*
- * Return current in milliAmps
- */
-int pp_chg_current(void);
-
-/*
- * Return power in milliWatts
- */
-int pp_chg_power(void);
-
-/*
- * Return bus voltage in milliVolts
- */
-int sr_chg_voltage(void);
-
-/*
- * Return current in milliAmps
- */
-int sr_chg_current(void);
-
-/*
- * Return power in milliWatts
- */
-int sr_chg_power(void);
-
-#endif /* __CROS_EC_INA231S_H */
diff --git a/board/servo_v4p1/ioexpanders.c b/board/servo_v4p1/ioexpanders.c
deleted file mode 100644
index 7482038879..0000000000
--- a/board/servo_v4p1/ioexpanders.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "hooks.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "ioexpanders.h"
-
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/******************************************************************************
- * Initialize IOExpanders.
- */
-
-static enum servo_board_id board_id_val = BOARD_ID_UNSET;
-
-#ifdef SECTION_IS_RO
-
-static int dut_chg_en_state;
-static int bc12_charger;
-
-/* Enable all ioexpander outputs. */
-int init_ioexpanders(void)
-{
-	/* Clear any faults and other IRQs*/
-	read_faults();
-	read_irqs();
-
-	/*
-	 * Cache initial value for BC1.2 indicator. This is the only pin, which
-	 * notifies about event on both low and high levels, while notification
-	 * should happen only when state has changed.
-	 */
-	ioex_get_level(IOEX_HOST_CHRG_DET, &bc12_charger);
-
-	return EC_SUCCESS;
-}
-
-static void ioexpanders_irq(void)
-{
-	int fault, irqs;
-
-	fault = read_faults();
-	irqs = read_irqs();
-
-	if (!(fault & USERVO_FAULT_L)) {
-		ec_uservo_power_en(0);
-		CPRINTF("FAULT: Microservo USB A port load switch\n");
-	}
-
-	if (!(fault & USB3_A0_FAULT_L)) {
-		ec_usb3_a0_pwr_en(0);
-		CPRINTF("FAULT: USB3 A0 port load switch\n");
-	}
-
-	if (!(fault & USB3_A1_FAULT_L)) {
-		ec_usb3_a1_pwr_en(0);
-		CPRINTF("FAULT: USB3 A1 port load switch\n");
-	}
-
-	if (!(fault & USB_DUTCHG_FLT_ODL)) {
-		CPRINTF("FAULT: Overcurrent on Charger or DUT CC/SBU lines\n");
-	}
-
-	if (!(fault & PP3300_DP_FAULT_L)) {
-		CPRINTF("FAULT: Overcurrent on DisplayPort\n");
-	}
-
-	if (!(fault & DAC_BUF1_LATCH_FAULT_L)) {
-		CPRINTF("FAULT: CC1 drive circuitry has exceeded thermal "
-			"or current limits. The CC1 DAC has been disabled "
-			"and disconnected.\n");
-
-		en_vout_buf_cc1(0);
-	}
-
-	if (!(fault & DAC_BUF2_LATCH_FAULT_L)) {
-		CPRINTF("FAULT: CC2 drive circuitry has exceeded thermal "
-			"or current limits. The CC2 DAC has been disabled "
-			"and disconnected.\n");
-
-		en_vout_buf_cc2(0);
-	}
-
-	/*
-	 * In case of both DACs' faults, we should clear them only after
-	 * disabling both DACs.
-	 */
-	if ((fault & (DAC_BUF1_LATCH_FAULT_L | DAC_BUF2_LATCH_FAULT_L)) !=
-	    (DAC_BUF1_LATCH_FAULT_L | DAC_BUF2_LATCH_FAULT_L)) {
-		fault_clear_cc(1);
-		fault_clear_cc(0);
-	}
-
-	if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) &&
-	    (board_id_det() <= BOARD_ID_REV1)) {
-		CPRINTF("BC1.2 charger %s\n",
-			(irqs & HOST_CHRG_DET) ? "plugged" : "unplugged");
-		bc12_charger = !!(irqs & HOST_CHRG_DET);
-	}
-
-	if (!(irqs & SYS_PWR_IRQ_ODL)) {
-		CPRINTF("System full power threshold exceeded\n");
-	}
-}
-DECLARE_DEFERRED(ioexpanders_irq);
-
-int irq_ioexpanders(void)
-{
-	hook_call_deferred(&ioexpanders_irq_data, 0);
-	return 0;
-}
-
-inline int sbu_uart_sel(int en)
-{
-	return ioex_set_level(IOEX_SBU_UART_SEL, en);
-}
-
-inline int atmel_reset_l(int en)
-{
-	return ioex_set_level(IOEX_ATMEL_RESET_L, en);
-}
-
-inline int sbu_flip_sel(int en)
-{
-	return ioex_set_level(IOEX_SBU_FLIP_SEL, en);
-}
-
-inline int usb3_a0_mux_sel(int en)
-{
-	return ioex_set_level(IOEX_USB3_A0_MUX_SEL, en);
-}
-
-inline int usb3_a0_mux_en_l(int en)
-{
-	return ioex_set_level(IOEX_USB3_A0_MUX_EN_L, en);
-}
-
-inline int ec_usb3_a0_pwr_en(int en)
-{
-	return ioex_set_level(IOEX_USB3_A0_PWR_EN, en);
-}
-
-inline int uart_18_sel(int en)
-{
-	return ioex_set_level(IOEX_UART_18_SEL, en);
-}
-
-inline int ec_uservo_power_en(int en)
-{
-	return ioex_set_level(IOEX_USERVO_POWER_EN, en);
-}
-
-inline int uservo_fastboot_mux_sel(enum uservo_fastboot_mux_sel_t sel)
-{
-	return ioex_set_level(IOEX_USERVO_FASTBOOT_MUX_SEL, (int)sel);
-}
-
-inline int ec_usb3_a1_pwr_en(int en)
-{
-	return ioex_set_level(IOEX_USB3_A1_PWR_EN, en);
-}
-
-inline int usb3_a1_mux_sel(int en)
-{
-	return ioex_set_level(IOEX_USB3_A1_MUX_SEL, en);
-}
-
-inline int board_id_det(void)
-{
-	if (board_id_val == BOARD_ID_UNSET) {
-		int id;
-
-		/* Cache board ID at init */
-		if (ioex_get_port(IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->ioex,
-		    IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port,
-		    &id))
-			return id;
-
-		/* Board ID consists of bits 5, 4, and 3 */
-		board_id_val = (id >> BOARD_ID_DET_OFFSET) & BOARD_ID_DET_MASK;
-	}
-
-	return board_id_val;
-}
-
-inline int dongle_det(void)
-{
-	int val;
-	ioex_get_level(IOEX_DONGLE_DET, &val);
-	return val;
-}
-
-inline int get_host_chrg_det(void)
-{
-	int val;
-	ioex_get_level(IOEX_HOST_CHRG_DET, &val);
-	return val;
-}
-
-inline int en_pp5000_alt_3p3(int en)
-{
-	return ioex_set_level(IOEX_EN_PP5000_ALT_3P3, en);
-}
-
-inline int en_pp3300_eth(int en)
-{
-	return ioex_set_level(IOEX_EN_PP3300_ETH, en);
-}
-
-inline int en_pp3300_dp(int en)
-{
-	return ioex_set_level(IOEX_EN_PP3300_DP, en);
-}
-
-inline int fault_clear_cc(int en)
-{
-	return ioex_set_level(IOEX_FAULT_CLEAR_CC, en);
-}
-
-inline int en_vout_buf_cc1(int en)
-{
-	return ioex_set_level(IOEX_EN_VOUT_BUF_CC1, en);
-}
-
-inline int en_vout_buf_cc2(int en)
-{
-	return ioex_set_level(IOEX_EN_VOUT_BUF_CC2, en);
-}
-
-int dut_chg_en(int en)
-{
-	dut_chg_en_state = en;
-	return ioex_set_level(IOEX_DUT_CHG_EN, en);
-}
-
-int get_dut_chg_en(void)
-{
-	return dut_chg_en_state;
-}
-
-inline int host_or_chg_ctl(int en)
-{
-	return ioex_set_level(IOEX_HOST_OR_CHG_CTL, en);
-}
-
-inline int read_faults(void)
-{
-	int val;
-
-	ioex_get_port(IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->ioex,
-		      IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port,
-		      &val);
-
-	return val;
-}
-
-inline int read_irqs(void)
-{
-	int val;
-
-	ioex_get_port(IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->ioex,
-		      IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port,
-		      &val);
-
-	return val;
-}
-
-inline int vbus_dischrg_en(int en)
-{
-	return ioex_set_level(IOEX_VBUS_DISCHRG_EN, en);
-}
-
-inline int usbh_pwrdn_l(int en)
-{
-	return ioex_set_level(IOEX_USBH_PWRDN_L, en);
-}
-
-inline int tca_gpio_dbg_led_k_odl(int en)
-{
-	return ioex_set_level(IOEX_TCA_GPIO_DBG_LED_K_ODL, !en);
-}
-
-#else /* SECTION_IS_RO */
-
-/*
- * Due to lack of flash in RW section, it is not possible to use IOEX subsystem
- * in it. Instead, RO section uses IOEX, and RW implements only required
- * function with raw i2c operation. This function is required by 'version'
- * console command and should work without any special initialization.
- */
-inline int board_id_det(void)
-{
-	if (board_id_val == BOARD_ID_UNSET) {
-		int id;
-		int res;
-
-		/* Cache board ID at init */
-		res = i2c_read8(TCA6416A_PORT,
-				TCA6416A_ADDR,
-				BOARD_ID_DET_PORT,
-				&id);
-		if (res != EC_SUCCESS)
-			return res;
-
-		/* Board ID consists of bits 5, 4, and 3 */
-		board_id_val = (id >> BOARD_ID_DET_OFFSET) & BOARD_ID_DET_MASK;
-	}
-
-	/* Board ID consists of bits 5, 4, and 3 */
-	return board_id_val;
-}
-
-#endif /* SECTION_IS_RO */
diff --git a/board/servo_v4p1/ioexpanders.h b/board/servo_v4p1/ioexpanders.h
deleted file mode 100644
index 6565992857..0000000000
--- a/board/servo_v4p1/ioexpanders.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IOEXPANDERS_H
-#define __CROS_EC_IOEXPANDERS_H
-
-#define BOARD_ID_DET_MASK 0x7
-#define BOARD_ID_DET_OFFSET 3
-#define BOARD_ID_DET_PORT 1
-
-enum uservo_fastboot_mux_sel_t {
-	MUX_SEL_USERVO = 0,
-	MUX_SEL_FASTBOOT = 1
-};
-
-/*
- * Initialize Ioexpanders
- */
-int init_ioexpanders(void);
-
-/*
- * Calls the Ioexpanders Deferred handler for interrupts
- * Should be called from the ioexpanders IRQ handler
- */
-int irq_ioexpanders(void);
-
-/**
- * SBU Crosspoint select
- *
- * @param en	0 - HOST SBU to DUT SBU connected
- *		1 - STM UART to DUT SBU connected
- * @return EC_SUCCESS or EC_xxx on error
- */
-int sbu_uart_sel(int en);
-
-/**
- * Host KBC Controller reset
- *
- * @param en	0 - Assert reset
- *		1 - Deassert reset
- * @return EC_SUCCESS or EC_xxx on error
- */
-int atmel_reset_l(int en);
-
-/**
- * SBU Crosspoint polarity flip for DTU SBU to STM USART/Host SBU
- *
- * @param en	0 - Retain polarity (no inversion)
- *		1 - Swap P for N polarity
- * @return EC_SUCCESS or EC_xxx on error
- */
-int sbu_flip_sel(int en);
-
-/**
- * USB data path for general USB type A port
- *
- * @param en	0 - Host hub
- *		1 - DUT hub
- * @return EC_SUCCESS or EC_xxx on error
- */
-int usb3_a0_mux_sel(int en);
-
-/**
- * USB data path enable for general USB type A port, first on J2
- *
- * @param en	0 - Data connected / enabled
- *		1 - Data disconnected
- * @return EC_SUCCESS or EC_xxx on error
- */
-int usb3_a0_mux_en_l(int en);
-
-/**
- * Controls load switches for 5V to general USB type A.
- *
- * @param en	0 - Disable power
- *		1 - Enable power
- * @return EC_SUCCESS or EC_xxx on error
- */
-int ec_usb3_a0_pwr_en(int en);
-
-/**
- * Controls logic to select 1.8V or 3.3V UART from STM to DUT on SBU lines
- *
- * @param en	0 - 3.3V level
- *		1 - 1.8V level
- * @return EC_SUCCESS or EC_xxx on error
- */
-int uart_18_sel(int en);
-
-/**
- * Controls load switches for 5V to uservo USB type A port
- *
- * @param en	0 - Disable power
- *		1 - Enable power
- * @return EC_SUCCESS or EC_xxx on error
- */
-int ec_uservo_power_en(int en);
-
-/**
- * USB data path enable from host hub to downstream userv or DUT peripheral
- *
- * @param sel	MUX_SEL_USERVO - hub connected to uservo
- *		MUX_SEL_FASTBOOT - hub connected to DUT
- * @return EC_SUCCESS or EC_xxx on error
- */
-int uservo_fastboot_mux_sel(enum uservo_fastboot_mux_sel_t sel);
-
-/**
- * Controls load switches for 5V to general USB type A second port
- *
- * @param en	0 - power off
- *		1 - power enabled
- * @return EC_SUCCESS or EC_xxx on error
- */
-int ec_usb3_a1_pwr_en(int en);
-
-/**
- * USB data path for general USB type A port, second on J2
- *
- * @param en	0 - Host hub
- *		1 - DUT hub
- * @return EC_SUCCESS or EC_xxx on error
- */
-int usb3_a1_mux_sel(int en);
-
-/**
- * Reads the 3-bit Servo V4.1 version ID
- *
- * @return version ID
- */
-int board_id_det(void);
-
-/**
- * Reads the TypeA/TypeC DUT cable assembly pigtail
- *
- * @return	0 - for TypeA
- *		1 - for TypeC
- */
-int dongle_det(void);
-
-/**
- * Reads state of BC1.2 on host connection
- *
- * @return	0 - BC1.2 not present
- * 		1 - BC1.2 present
- */
-int get_host_chrg_det(void);
-
-/**
- * Enable signal for supplemental power supply. This supply will support higher
- * wattage servo needs. 10ms after enabling this bit, the server supply should
- * switch over from the host supply and the higher wattage will be available
- *
- * @param en	0 - Alternate supply disabled
- *		1 - Supply enabled
- * @return EC_SUCCESS or EC_xxx on error
- */
-int en_pp5000_alt_3p3(int en);
-
-/**
- * Controls load switches for the RTL8153. By default, ethernet is enabled but
- * power can be removed as a way to clear any bad conditions
- *
- * @param en	0 - disable power
- *		1 - enable power
- * @return EC_SUCCESS or EC_xxx on error
- */
-int en_pp3300_eth(int en);
-
-/**
- * Controls load switches that enables 3.3V supply on the Display Port
- * connector. On by default
- *
- * @param en	0 - disable 3.3V to DP connector
- *		1 - enable 3.3V to DP connector
- * @return EC_SUCCESS or EC_xxx on error
- */
-int en_pp3300_dp(int en);
-
-/**
- * The rising edge of this signal clears the latched condition when thermal
- * or overcurrent fault has occurred from both CC1 and CC2 channels. Note
- * that if the CC drive circuitry continues to be overheated, it will reset
- * the fault regardless of the FAULT_CLEAR_CC signal.
- *
- * @param en	0 to 1 transition - clear fault
- *		1 to 0 transition, 0, or 1 - No change in fault
- * @return EC_SUCCESS or EC_xxx on error
- */
-int fault_clear_cc(int en);
-
-/**
- * CC1 Drive circuitry enable
- *
- * @param en	0 - disable CC1 high output drive (normal CC Operation by STM)
- *		1 - enable CC1 high drive output
- * @return EC_SUCCESS or EC_xxx on error
- */
-int en_vout_buf_cc1(int en);
-
-/**
- * CC2 Drive circuitry enable
- *
- * @param en	0 - disable CC2 high output drive (normal CC Operation by STM)
- *		1 - enable CC2 high drive output
- * @return EC_SUCCESS or EC_xxx on error
- */
-int en_vout_buf_cc2(int en);
-
-/**
- * Controls load switches for servo to power DUT Vusb
- *
- * @param en	0 - disable power
- *		1 - enable power
- * @return EC_SUCCESS or EC_xxx on error
- */
-int dut_chg_en(int en);
-
-/**
- * Get state of DUT Vusb
- *
- * @return	0 - power is disabled
- *		1 - power is enabled
- * @return EC_SUCCESS or EC_xxx on error
- */
-int get_dut_chg_en(void);
-
-/**
- * Selects power source for DUT Vusb from servo
- *
- * @param en	0 - 5V
- *		1 - charger Vbus
- * @return EC_SUCCESS or EC_xxx on error
- */
-int host_or_chg_ctl(int en);
-
-#define USERVO_FAULT_L		BIT(0)
-#define USB3_A0_FAULT_L		BIT(1)
-#define USB3_A1_FAULT_L		BIT(2)
-#define USB_DUTCHG_FLT_ODL	BIT(3)
-#define PP3300_DP_FAULT_L	BIT(4)
-#define DAC_BUF1_LATCH_FAULT_L	BIT(5)
-#define DAC_BUF2_LATCH_FAULT_L	BIT(6)
-#define PP5000_SRC_SEL		BIT(7)
-
-/**
- * Read any faults that may have occurred. A fault has occurred if the
- * corresponding bit is 0.
- *
- * BIT:
- *   0 (USERVO_FAULT_L) - Fault for port microservo USB A load switch
- *   1 (USB3_A0_FAULT_L) - Fault for general port USB A load switch
- *   2 (USB3_A1_FAULT_L) - Fault for general port USB A load switch
- *   3 (USB_DUTCHG_FLT_ODL) - Overcurrent fault on Charger or DUB CC/SBU lines
- *   4 (PP3300_DP_FAULT_L) - Overcurrent fault on DisplayPort
- *   5 (DAC_BUF1_LATCH_FAULT_L) - Fault to indicate CC drive circuitry has
- *				  exceeded thermal limits or exceeded current
- *				  limits; when faults occur, the driver is
- *				  disabled and needs to be reset.
- *   6 (DAC_BUF2_LATCH_FAULT_L) - Fault to indicate CC drive circuitry has
- *				  exceeded thermal limits or exceeded current
- *				  limits; when faults occur, the driver is
- *				  disabled and needs to be reset.
- *   7 (PP5000_SRC_SEL) - Used to monitor whether Host power or Servo Charger
- *			  USBC is providing source to PP5000. This may flip
- *			  sources upon fault and should be monitored.
- *			  0 - USBC Servo charger is source
- *			  1 - host cable is source
- */
-int read_faults(void);
-
-#define HOST_CHRG_DET	BIT(0)
-#define SYS_PWR_IRQ_ODL	BIT(6)
-
-/**
- * Read irqs which indicate some system event.
- *
- * BIT
- * 0 (HOST_CHRG_DET)   - Change of state of BC1.2 on host connection
- *                       0 - BC1.2 not present
- *                       1 - BC1.2 present
- * 6 (SYS_PWR_IRQ_ODL) - IRQ from system full power INA231 monitor. IRQ can be
- *                       programmed to trip on wattage threshold.
- *                       0 - IRQ asserted
- *                       1 - no IRQ
- */
-int read_irqs(void);
-
-/**
- * Enables active discharge for USB DUT Charger
- *
- * @param en	0 - disable active discharge (default)
- *		1 - enable active discharge circuitry
- * @return EC_SUCCESS or EC_xxx on error
- */
-int vbus_dischrg_en(int en);
-
-/**
- * Enables Hub
- *
- * @param en	0 - place hub in suspend (low power state)
- *		1 - enable hub activity (including i2c)
- * @return EC_SUCCESS or EC_xxx on error
- */
-int usbh_pwrdn_l(int en);
-
-/**
- * Debug LED
- *
- * @param en	0 - LED is OFF
- *		1 - LED is ON
- * @return EC_SUCCESS or EC_xxx on error
- */
-int tca_gpio_dbg_led_k_odl(int en);
-
-#endif /* __CROS_EC_IOEXPANDERS_H */
diff --git a/board/servo_v4p1/pathsel.c b/board/servo_v4p1/pathsel.c
deleted file mode 100644
index 7b71fba169..0000000000
--- a/board/servo_v4p1/pathsel.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gl3590.h"
-#include "gpio.h"
-#include "ioexpanders.h"
-#include "pathsel.h"
-
-static void hh_usb3_a0_pwr_en(int en)
-{
-	gl3590_enable_ports(0, GL3590_DFP2, en);
-}
-
-static void hh_usb3_a1_pwr_en(int en)
-{
-	gl3590_enable_ports(0, GL3590_DFP1, en);
-}
-
-void init_pathsel(void)
-{
-	/* Connect TypeA port to DUT hub */
-	usb3_a0_to_dut();
-	/* Connect data lines */
-	usb3_a0_mux_en_l(0);
-
-	/* Enable power */
-	ec_usb3_a0_pwr_en(1);
-
-	hh_usb3_a0_pwr_en(1);
-
-	/* Connect TypeA port to DUT hub */
-	usb3_a1_to_dut();
-	/* Connect data lines */
-	gpio_set_level(GPIO_USB3_A1_MUX_EN_L, 0);
-
-	/* Enable power */
-	ec_usb3_a1_pwr_en(1);
-
-	hh_usb3_a1_pwr_en(1);
-}
-
-void usb3_a0_to_dut(void)
-{
-	usb3_a0_mux_sel(1);
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 1);
-}
-
-void usb3_a1_to_dut(void)
-{
-	usb3_a1_mux_sel(1);
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 1);
-}
-
-void usb3_a0_to_host(void)
-{
-	usb3_a0_mux_sel(0);
-}
-
-void usb3_a1_to_host(void)
-{
-	usb3_a1_mux_sel(0);
-}
-
-void dut_to_host(void)
-{
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 0);
-	gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
-	uservo_fastboot_mux_sel(MUX_SEL_FASTBOOT);
-}
-
-void uservo_to_host(void)
-{
-	uservo_fastboot_mux_sel(MUX_SEL_USERVO);
-}
diff --git a/board/servo_v4p1/pathsel.h b/board/servo_v4p1/pathsel.h
deleted file mode 100644
index 7365d3adf3..0000000000
--- a/board/servo_v4p1/pathsel.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PATHSEL_H
-#define __CROS_EC_PATHSEL_H
-
-/**
- * Both USB3_TypeA0 and USB3_TypeA1 are routed to the DUT by default.
- */
-void init_pathsel(void);
-
-/**
- * Routes USB3_TypeA0 port to DUT
- */
-void usb3_a0_to_dut(void);
-
-/**
- * Routes USB3_TypeA1 port to DUT
- */
-void usb3_a1_to_dut(void);
-
-/**
- * Routes USB3_TypeA0 port to HOST
- */
-void usb3_a0_to_host(void);
-
-/**
- * Routes USB3_TypeA1 port to HOST
- */
-void usb3_a1_to_host(void);
-
-/**
- * Routes the DUT to the HOST. Used for fastboot
- */
-void dut_to_host(void);
-
-/**
- * Routes the Micro Servo to the Host
- */
-void uservo_to_host(void);
-
-#endif /* __CROS_EC_PATHSEL_H */
diff --git a/board/servo_v4p1/pi3usb9201.c b/board/servo_v4p1/pi3usb9201.c
deleted file mode 100644
index 102eaf790d..0000000000
--- a/board/servo_v4p1/pi3usb9201.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "pi3usb9201.h"
-
-#define PI3USB9201_ADDR	0x5f
-
-inline void init_pi3usb9201(void)
-{
-	/*
-	 * Write 0x08 (Client mode detection and Enable USB switch auto ON) to
-	 *	control Reg 2
-	 * Write 0x08 (Client Mode) to Control Reg 1
-	 */
-	i2c_write16(1, PI3USB9201_ADDR, CTRL_REG1, 0x0808);
-}
-
-inline void write_pi3usb9201(enum pi3usb9201_reg_t reg,
-					enum pi3usb9201_dat_t dat)
-{
-	i2c_write8(1, PI3USB9201_ADDR, reg, dat);
-}
-
-inline uint8_t read_pi3usb9201(enum pi3usb9201_reg_t reg)
-{
-	int tmp;
-
-	i2c_read8(1, PI3USB9201_ADDR, reg, &tmp);
-
-	return tmp;
-}
diff --git a/board/servo_v4p1/pi3usb9201.h b/board/servo_v4p1/pi3usb9201.h
deleted file mode 100644
index 826db8b871..0000000000
--- a/board/servo_v4p1/pi3usb9201.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PI3USB9201_H
-#define __CROS_EC_PI3USB9201_H
-
-enum pi3usb9201_reg_t {
-	CTRL_REG1,
-	CTRL_REG2,
-	CLIENT_STATUS,
-	HOST_STATUS
-};
-
-enum pi3usb9201_dat_t {
-	POWER_DOWN	= 0x0,
-	SDP_HOST_MODE	= 0x2,
-	DCP_HOST_MODE	= 0x4,
-	CDP_HOST_MODE	= 0x6,
-	CLIENT_MODE	= 0x8,
-	USB_PATH_ON	= 0xe
-};
-
-
-/* Client Status bits */
-#define CS_DCP			BIT(7)
-#define CS_SDP			BIT(6)
-#define CS_CDP			BIT(5)
-#define CS_1A_CHARGER		BIT(3)
-#define CS_2A_CHARGER		BIT(2)
-#define CS_2_4A_CHARGER		BIT(1)
-
-/* Host Status bits */
-#define HS_USB_UNPLUGGED	BIT(2)
-#define HS_USB_PLUGGED		BIT(1)
-#define HS_BC1_2		BIT(0)
-
-/**
- * Selects Client Mode and client mode detection
- */
-void init_pi3usb9201(void);
-
-/**
- * Write a byte to the pi3usb9201
- *
- * @param reg	register to write
- * @param dat	data to write to the register
- */
-void write_pi3usb9201(enum pi3usb9201_reg_t reg, enum pi3usb9201_dat_t dat);
-
-/**
- * Read a byte from the pi3usb9201
- *
- * @param return	data byte read from pi3usb9201
- */
-uint8_t read_pi3usb9201(enum pi3usb9201_reg_t reg);
-
-#endif /* __CROS_EC_PI3USB9201_H */
diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h
deleted file mode 100644
index 63fb6b5728..0000000000
--- a/board/servo_v4p1/usb_pd_config.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "chip/stm32/registers.h"
-#include "console.h"
-#include "gpio.h"
-#include "ec_commands.h"
-#include "usb_pd_tcpm.h"
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_CHG 16
-#define TIM_CLOCK_PD_RX_CHG 1
-#define TIM_CLOCK_PD_TX_DUT 15
-#define TIM_CLOCK_PD_RX_DUT 3
-
-/* Timer channel */
-#define TIM_TX_CCR_CHG 1
-#define TIM_RX_CCR_CHG 1
-#define TIM_TX_CCR_DUT 2
-#define TIM_RX_CCR_DUT 1
-
-#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_DUT : TIM_CLOCK_PD_TX_CHG)
-#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_DUT : TIM_CLOCK_PD_RX_CHG)
-
-/* RX timer capture/compare register */
-#define TIM_CCR_CHG (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_CHG, TIM_RX_CCR_CHG))
-#define TIM_CCR_DUT (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_DUT, TIM_RX_CCR_DUT))
-#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_DUT : TIM_CCR_CHG)
-
-/* TX and RX timer register */
-#define TIM_REG_TX_CHG (STM32_TIM_BASE(TIM_CLOCK_PD_TX_CHG))
-#define TIM_REG_RX_CHG (STM32_TIM_BASE(TIM_CLOCK_PD_RX_CHG))
-#define TIM_REG_TX_DUT (STM32_TIM_BASE(TIM_CLOCK_PD_TX_DUT))
-#define TIM_REG_RX_DUT (STM32_TIM_BASE(TIM_CLOCK_PD_RX_DUT))
-#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_DUT : TIM_REG_TX_CHG)
-#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_DUT : TIM_REG_RX_CHG)
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
-#define CC_EMCA_SERVO	BIT(6)   /*
-				  * Emulate Electronically Marked Cable Assembly
-				  * (EMCA) servo (or non-EMCA)
-				  */
-#define CC_FASTBOOT_DFP	BIT(7)   /* Allow mux uServo->Fastboot on DFP */
-
-/* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_MF_PREF		BIT(3)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(4)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(5)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(6)   /* HPD level if overridden */
-
-/* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
-#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
-static inline void spi_enable_clock(int port)
-{
-	if (port == CHG)
-		STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-	else
-		STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-}
-
-/* DMA for transmit uses DMA CH3 for CHG and DMA_CH7 for DUT */
-#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH7 : STM32_DMAC_CH3)
-
-/* RX uses COMP1 and TIM1_CH1 on port CHG and COMP2 and TIM3_CH1 for port DUT*/
-/* DUT RX use CMP1, TIM3_CH1, DMA_CH6 */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
-/* CHG RX use CMP2, TIM1_CH1, DMA_CH2 */
-#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
-
-#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
-#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
-
-/*
- * EXTI line 21 is connected to the CMP1 output,
- * EXTI line 22 is connected to the CMP2 output,
- * CHG uses CMP2, and DUT uses CMP1.
- */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
-
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* DMA for receive uses DMA_CH2 for CHG and DMA_CH6 for DUT */
-#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH6 : STM32_DMAC_CH2)
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	if (port == CHG) {
-		/* 40 MHz pin speed on SPI PB3&4,
-		 * (USB_CHG_TX_CLKIN & USB_CHG_CC1_TX_DATA)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
-		/* 40 MHz pin speed on TIM16_CH1 (PB8),
-		 * (USB_CHG_TX_CLKOUT)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
-	} else {
-		/* 40 MHz pin speed on SPI PB13/14,
-		 * (USB_DUT_TX_CLKIN & USB_DUT_CC1_TX_DATA)
-		 */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
-		/* 40 MHz pin speed on TIM15_CH2 (PB15) */
-		STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
-	}
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	if (port == CHG) {
-		/* Reset SPI1 */
-		STM32_RCC_APB2RSTR |= BIT(12);
-		STM32_RCC_APB2RSTR &= ~BIT(12);
-	} else {
-		/* Reset SPI2 */
-		STM32_RCC_APB1RSTR |= BIT(14);
-		STM32_RCC_APB1RSTR &= ~BIT(14);
-	}
-}
-
-static const uint8_t tx_gpio[2 /* port */][2 /* polarity */] = {
-	{ GPIO_USB_CHG_CC1_TX_DATA, GPIO_USB_CHG_CC2_TX_DATA },
-	{ GPIO_USB_DUT_CC1_TX_DATA, GPIO_USB_DUT_CC2_TX_DATA },
-};
-static const uint8_t ref_gpio[2 /* port */][2 /* polarity */] = {
-	{ GPIO_USB_CHG_CC1_MCU, GPIO_USB_CHG_CC2_MCU },
-	{ GPIO_USB_DUT_CC1_MCU, GPIO_USB_DUT_CC2_MCU },
-};
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-#ifndef VIF_BUILD /* genvif doesn't like tricks with GPIO macros */
-	const struct gpio_info *tx = gpio_list + tx_gpio[port][polarity];
-	const struct gpio_info *ref = gpio_list + ref_gpio[port][polarity];
-
-	/* use directly GPIO registers, latency before the PD preamble is key */
-
-	/* switch the TX pin Mode from Input (00) to Alternate (10) for SPI */
-	STM32_GPIO_MODER(tx->port) |= 2 << ((31 - __builtin_clz(tx->mask)) * 2);
-	/* switch the ref pin Mode from analog (11) to Out (01) for low level */
-	STM32_GPIO_MODER(ref->port) &=
-		~(2 << ((31 - __builtin_clz(ref->mask)) * 2));
-#endif /* !VIF_BUILD */
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	const struct gpio_info *tx = gpio_list + tx_gpio[port][polarity];
-	const struct gpio_info *ref = gpio_list + ref_gpio[port][polarity];
-
-	gpio_set_flags_by_mask(tx->port, tx->mask, GPIO_INPUT);
-	gpio_set_flags_by_mask(ref->port, ref->mask, GPIO_ANALOG);
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	uint32_t val = STM32_COMP_CSR;
-
-	/* Use window mode so that COMP1 and COMP2 share non-inverting input */
-	val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
-
-	if (port == CHG) {
-		/* CHG use the right comparator inverted input for COMP2 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
-	} else {
-		/* DUT use the right comparator inverted input for COMP1 */
-		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
-	}
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	const struct gpio_info *c2 = gpio_list + GPIO_USB_CHG_CC2_TX_DATA;
-	const struct gpio_info *c1 = gpio_list + GPIO_USB_CHG_CC1_TX_DATA;
-	const struct gpio_info *d2 = gpio_list + GPIO_USB_DUT_CC2_TX_DATA;
-	const struct gpio_info *d1 = gpio_list + GPIO_USB_DUT_CC1_TX_DATA;
-
-	gpio_config_module(MODULE_USB_PD, 1);
-	/* Select the proper alternate SPI function on TX_DATA pins */
-	/* USB_CHG_CC2_TX_DATA: PA6 is SPI1 MISO (AF0) */
-	gpio_set_alternate_function(c2->port, c2->mask, 0);
-	gpio_set_flags_by_mask(c2->port, c2->mask, GPIO_INPUT);
-	/* USB_CHG_CC1_TX_DATA: PB4 is SPI1 MISO (AF0) */
-	gpio_set_alternate_function(c1->port, c1->mask, 0);
-	gpio_set_flags_by_mask(c1->port, c1->mask, GPIO_INPUT);
-	/* USB_DUT_CC2_TX_DATA: PC2 is SPI2 MISO (AF1) */
-	gpio_set_alternate_function(d2->port, d2->mask, 1);
-	gpio_set_flags_by_mask(d2->port, d2->mask, GPIO_INPUT);
-	/* USB_DUT_CC1_TX_DATA: PB14 is SPI2 MISO (AF0) */
-	gpio_set_alternate_function(d1->port, d1->mask, 0);
-	gpio_set_flags_by_mask(d1->port, d1->mask, GPIO_INPUT);
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	/*
-	 * CHG (port == 0) port has fixed Rd attached and therefore can only
-	 * present as a SNK device. If port != DUT (port == 1), then nothing to
-	 * do in this function.
-	 */
-	if (port != DUT)
-		return;
-
-	if (enable) {
-		/*
-		 * Servo_v4 in SRC mode acts as a DTS (debug test
-		 * accessory) and needs to present Rp on both CC
-		 * lines. In order to support orientation detection, and
-		 * advertise the correct TypeC current level, the
-		 * values of Rp1/Rp2 need to asymmetric with Rp1 > Rp2. This
-		 * function is called without a specified Rp value so assume the
-		 * servo_v4 default of USB level current. If a higher current
-		 * can be supported, then the Rp value will get adjusted when
-		 * VBUS is enabled.
-		 */
-		pd_set_rp_rd(port, TYPEC_CC_RP, TYPEC_RP_USB);
-
-		gpio_set_flags(GPIO_USB_DUT_CC1_TX_DATA, GPIO_INPUT);
-		gpio_set_flags(GPIO_USB_DUT_CC2_TX_DATA, GPIO_INPUT);
-	} else {
-		/* Select Rd, the Rp value is a don't care */
-		pd_set_rp_rd(port, TYPEC_CC_RD, TYPEC_RP_RESERVED);
-	}
-}
-
-/**
- * Initialize various GPIOs and interfaces to safe state at start of pd_task.
- *
- * These include:
- *   VBUS, charge path based on power role.
- *   Physical layer CC transmit.
- *
- * @param port        USB-C port number
- * @param power_role  Power role of device
- */
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-	/*
-	 * Set CC pull resistors. The PD state machine will then transit and
-	 * enable VBUS after it detects valid voltages on CC lines.
-	 */
-	pd_set_host_mode(port, power_role);
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-
-}
-
-int pd_adc_read(int port, int cc);
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
-
diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c
deleted file mode 100644
index c4d7c239a1..0000000000
--- a/board/servo_v4p1/usb_pd_policy.c
+++ /dev/null
@@ -1,1516 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "chg_control.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "ioexpanders.h"
-#include "pathsel.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
-
-#define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
-
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
-
-/* Macros to config the PD role */
-#define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-
-/* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
-		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
-		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
-		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
-		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
-	} while (0)
-
-#define DUT_ACTIVE_CC_PU(r) DUT_ACTIVE_CC_SET(r, GPIO_OUT_HIGH)
-#define DUT_INACTIVE_CC_PU(r) DUT_INACTIVE_CC_SET(r, GPIO_OUT_HIGH)
-#define DUT_ACTIVE_CC_PD(r) DUT_ACTIVE_CC_SET(r, GPIO_OUT_LOW)
-#define DUT_INACTIVE_CC_PD(r) DUT_INACTIVE_CC_SET(r, GPIO_OUT_LOW)
-#define DUT_BOTH_CC_PD(r) DUT_BOTH_CC_SET(r, GPIO_OUT_LOW)
-#define DUT_BOTH_CC_OPEN(r) DUT_BOTH_CC_SET(r, GPIO_INPUT)
-#define DUT_ACTIVE_CC_OPEN(r) DUT_ACTIVE_CC_SET(r, GPIO_INPUT)
-#define DUT_INACTIVE_CC_OPEN(r) DUT_INACTIVE_CC_SET(r, GPIO_INPUT)
-
-/*
- * Dynamic PDO that reflects capabilities present on the CHG port. Allow for
- * multiple entries so that we can offer greater than 5V charging. The 1st
- * entry will be fixed 5V, but its current value may change based on the CHG
- * port vbus info. Subsequent entries are used for when offering vbus greater
- * than 5V.
- */
-static const uint16_t pd_src_voltages_mv[] = {
-		5000, 9000, 10000, 12000, 15000, 20000,
-};
-static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
-static uint8_t chg_pdo_cnt;
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-struct vbus_prop {
-	int mv;
-	int ma;
-};
-static struct vbus_prop vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
-static int active_charge_port = CHARGE_PORT_NONE;
-static enum charge_supplier active_charge_supplier;
-static uint8_t vbus_rp = TYPEC_RP_RESERVED;
-
-static int cc_config = CC_ALLOW_SRC | CC_EMCA_SERVO;
-
-/* Voltage thresholds for no connect in DTS mode */
-static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
-};
-/* Voltage thresholds for Ra attach in DTS mode */
-static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-};
-/* Voltage thresholds for no connect in normal SRC mode */
-static int pd_src_vnc[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_VNC_MV,
-	PD_SRC_1_5_VNC_MV,
-	PD_SRC_3_0_VNC_MV,
-};
-/* Voltage thresholds for Ra attach in normal SRC mode */
-static int pd_src_rd_threshold[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_RD_THRESH_MV,
-	PD_SRC_1_5_RD_THRESH_MV,
-	PD_SRC_3_0_RD_THRESH_MV,
-};
-
-/* Saved value for the duration of faking PD disconnect */
-static int fake_pd_disconnect_duration_us;
-
-/* Shadow what would be in TCPC register state. */
-static int rp_value_stored = TYPEC_RP_USB;
-/*
- * Make sure the below matches CC_EMCA_SERVO
- * otherwise you'll have a bad time.
- */
-static int cc_pull_stored = TYPEC_CC_RD;
-
-static int user_limited_max_mv = 20000;
-
-static uint8_t allow_pr_swap = 1;
-static uint8_t allow_dr_swap = 1;
-
-static uint32_t max_supported_voltage(void)
-{
-	return user_limited_max_mv;
-}
-
-static int charge_port_is_active(void)
-{
-	return active_charge_port == CHG && vbus[CHG].mv > 0;
-}
-
-static int is_charge_through_allowed(void)
-{
-	return charge_port_is_active() && cc_config & CC_ALLOW_SRC;
-}
-
-static int get_dual_role_of_src(void)
-{
-	return cc_config & CC_ENABLE_DRP ? PD_DRP_TOGGLE_ON :
-					   PD_DRP_FORCE_SOURCE;
-}
-
-static void dut_allow_charge(void)
-{
-	/*
-	 * Update to charge enable if charger still present and not
-	 * already charging.
-	 */
-	if (is_charge_through_allowed() &&
-	    pd_get_dual_role(DUT) != PD_DRP_FORCE_SOURCE &&
-	    pd_get_dual_role(DUT) != PD_DRP_TOGGLE_ON) {
-		CPRINTS("Enable DUT charge through");
-		pd_set_dual_role(DUT, get_dual_role_of_src());
-		/*
-		 * If DRP role, don't set any CC pull resistor, the PD
-		 * state machine will toggle and set the pull resistors
-		 * when needed.
-		 */
-		if (!(cc_config & CC_ENABLE_DRP))
-			pd_set_host_mode(DUT, 1);
-
-		/*
-		 * Enable PD comm. The PD comm may be disabled during
-		 * the power charge-through was detached.
-		 */
-		pd_comm_enable(DUT, 1);
-
-		pd_update_contract(DUT);
-	}
-}
-DECLARE_DEFERRED(dut_allow_charge);
-
-static void board_manage_dut_port(void)
-{
-	enum pd_dual_role_states allowed_role;
-	enum pd_dual_role_states current_role;
-
-	/*
-	 * This function is called by the CHG port whenever there has been a
-	 * change in its vbus voltage or current. That change may necessitate
-	 * that the DUT port present a different Rp value or renogiate its PD
-	 * contract if it is connected.
-	 */
-
-	/* Assume the default value of Rd */
-	allowed_role = PD_DRP_FORCE_SINK;
-
-	/* If VBUS charge through is available, mark as such. */
-	if (is_charge_through_allowed())
-		allowed_role = get_dual_role_of_src();
-
-	current_role = pd_get_dual_role(DUT);
-	if (current_role != allowed_role) {
-		/* Update role. */
-		if (allowed_role == PD_DRP_FORCE_SINK) {
-			/* We've lost charge through. Disable VBUS. */
-			chg_power_select(CHG_POWER_OFF);
-			dut_chg_en(0);
-
-			/* Mark as SNK only. */
-			pd_set_dual_role(DUT, PD_DRP_FORCE_SINK);
-			pd_set_host_mode(DUT, 0);
-
-			/*
-			 * Disable PD comm. It matches the user expectation that
-			 * unplugging the power charge-through makes servo v4 as
-			 * a passive hub, without any PD support.
-			 *
-			 * There is an exception that servo v4 is explicitly set
-			 * to have PD, like the "pnsnk" mode.
-			 */
-			pd_comm_enable(DUT, cc_config & CC_SNK_WITH_PD ? 1 : 0);
-		} else {
-			/* Allow charge through after PD negotiate. */
-			hook_call_deferred(&dut_allow_charge_data, 2000 * MSEC);
-		}
-	}
-
-	/*
-	 * Update PD contract to reflect new available CHG
-	 * voltage/current values.
-	 */
-	pd_update_contract(DUT);
-}
-
-static void update_ports(void)
-{
-	int pdo_index, src_index, snk_index, i;
-	uint32_t pdo, max_ma, max_mv, unused;
-
-	/*
-	 * CHG Vbus has changed states, update PDO that reflects CHG port
-	 * state
-	 */
-	if (!charge_port_is_active()) {
-		/* CHG Vbus has dropped, so become SNK. */
-		chg_pdo_cnt = 0;
-	} else {
-		/* Advertise the 'best' PDOs at various discrete voltages */
-		if (active_charge_supplier == CHARGE_SUPPLIER_PD) {
-			src_index = 0;
-			snk_index = -1;
-
-			for (i = 0; i < ARRAY_SIZE(pd_src_voltages_mv); ++i) {
-				/* Adhere to board voltage limits */
-				if (pd_src_voltages_mv[i] >
-				    max_supported_voltage())
-					break;
-
-				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
-					pd_get_src_caps(CHG),
-					pd_src_voltages_mv[i], &pdo);
-				/* Don't duplicate PDOs */
-				if (pdo_index == snk_index)
-					continue;
-				/* Skip battery / variable PDOs */
-				if ((pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-					continue;
-
-				snk_index = pdo_index;
-				pd_extract_pdo_power(pdo, &max_ma, &max_mv,
-						     &unused);
-				pd_src_chg_pdo[src_index++] =
-					PDO_FIXED_VOLT(max_mv) |
-					PDO_FIXED_CURR(max_ma) |
-					DUT_PDO_FIXED_FLAGS |
-					PDO_FIXED_UNCONSTRAINED;
-			}
-			chg_pdo_cnt = src_index;
-		} else {
-			/* 5V PDO */
-			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
-
-			chg_pdo_cnt = 1;
-		}
-	}
-
-	/* Call DUT port manager to update Rp and possible PD contract */
-	board_manage_dut_port();
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	if (charge_port == DUT)
-		return -1;
-
-	active_charge_port = charge_port;
-	update_ports();
-
-	if (!charge_port_is_active())
-		/* Don't negotiate > 5V, except in lockstep with DUT */
-		pd_set_external_voltage_limit(CHG, PD_MIN_MV);
-
-	return 0;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	if (port != CHG)
-		return;
-
-	active_charge_supplier = supplier;
-
-	/* Update the voltage/current values for CHG port */
-	vbus[CHG].ma = charge_ma;
-	vbus[CHG].mv = charge_mv;
-	update_ports();
-}
-
-__override uint8_t board_get_src_dts_polarity(int port)
-{
-	/*
-	 * When servo configured as srcdts, the CC polarity is based
-	 * on the flags.
-	 */
-	if (port == DUT)
-		return !!(cc_config & CC_POLARITY);
-
-	return 0;
-}
-
-int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
-{
-	int rp_index;
-	int nc;
-
-	/* Can never be called from CHG port as it's sink only */
-	if (port != DUT)
-		return 0;
-
-	rp_index = vbus_rp;
-	/*
-	 * If rp_index > 2, then always return not connected. This case should
-	 * only happen when all Rp GPIO controls are tri-stated.
-	 */
-	if (rp_index >= TYPEC_RP_RESERVED)
-		return 1;
-
-	/* Select the correct voltage threshold for current Rp and DTS mode */
-	if (cc_config & CC_DISABLE_DTS)
-		nc = cc_volt >= pd_src_vnc[rp_index];
-	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
-
-	return nc;
-}
-
-int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
-{
-	int rp_index;
-	int ra;
-
-	/* Can never be called from CHG port as it's sink only */
-	if (port != DUT)
-		return 0;
-
-	rp_index = vbus_rp;
-	/*
-	 * If rp_index > 2, then can't be Ra. This case should
-	 * only happen when all Rp GPIO controls are tri-stated.
-	 */
-	if (rp_index >= TYPEC_RP_RESERVED)
-		return 0;
-
-	/* Select the correct voltage threshold for current Rp and DTS mode */
-	if (cc_config & CC_DISABLE_DTS)
-		ra = cc_volt < pd_src_rd_threshold[rp_index];
-	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
-
-	return ra;
-}
-
-/* DUT CC readings aren't valid if we aren't applying CC pulls */
-bool cc_is_valid(void)
-{
-	if ((cc_config & CC_DETACH) || (cc_pull_stored == TYPEC_CC_OPEN) ||
-	    ((cc_pull_stored == TYPEC_CC_RP) &&
-	     (rp_value_stored == TYPEC_RP_RESERVED)))
-		return false;
-	return true;
-}
-
-int pd_adc_read(int port, int cc)
-{
-	int mv = -1;
-
-	if (port == CHG)
-		mv = adc_read_channel(cc ? ADC_CHG_CC2_PD : ADC_CHG_CC1_PD);
-	else if (cc_is_valid()) {
-		/*
-		 * In servo v4 hardware logic, both CC lines are wired directly
-		 * to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
-		 * (CC1 if polarity flip) and make the voltage high as vRd-3.0,
-		 * which makes the PD state mess up. As the PD state machine
-		 * doesn't handle this case. It assumes that CC2 (CC1 if
-		 * polarity flip) is separated by a Type-C cable, resulting a
-		 * voltage lower than the max of vRa.
-		 *
-		 * It fakes the voltage within vRa.
-		 */
-
-		/*
-		 * TODO(b/161260559): Fix this logic because of leakage
-		 * "phantom detects" Or flat-out mis-detects..... talking on
-		 * leaking CC2 line. And Vconn-swap case... and Ra on second
-		 * line (SERVO_EMCA)...
-		 *
-		 * This is basically a hack faking "vOpen" from TCPCI spec.
-		 */
-		if ((cc_config & CC_DISABLE_DTS) &&
-		    port == DUT &&
-		    cc == ((cc_config & CC_POLARITY) ? 0 : 1)) {
-
-			if ((cc_pull_stored == TYPEC_CC_RD)  ||
-				(cc_pull_stored == TYPEC_CC_RA) ||
-				(cc_pull_stored == TYPEC_CC_RA_RD))
-				mv = -1;
-			else if (cc_pull_stored == TYPEC_CC_RP)
-				mv = 3301;
-		} else
-			mv = adc_read_channel(cc ? ADC_DUT_CC2_PD :
-						   ADC_DUT_CC1_PD);
-	} else {
-		/*
-		 * When emulating detach, fake the voltage on CC to 0 to avoid
-		 * triggering some debounce logic.
-		 *
-		 * The servo v4 makes Rd/Rp open but the DUT may present Rd/Rp
-		 * alternatively that makes the voltage on CC falls into some
-		 * unexpected range and triggers the PD state machine switching
-		 * between SNK_DISCONNECTED and SNK_DISCONNECTED_DEBOUNCE.
-		 */
-		mv = -1;
-	}
-
-	return mv;
-}
-
-static int board_set_rp(int rp)
-{
-	if (cc_config & CC_DISABLE_DTS) {
-		/* TODO: Add SRC-EMCA mode (CC_EMCA_SERVO=1) */
-		/* TODO: Add SRC-nonEMCA mode (CC_EMCA_SERVO=0)*/
-
-		/*
-		 * DTS mode is disabled, so only present the requested Rp value
-		 * on CC1 (active) and leave all Rp/Rd resistors on CC2
-		 * (inactive) disconnected.
-		 */
-		switch (rp) {
-		case TYPEC_RP_USB:
-			DUT_ACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_1A5:
-			DUT_ACTIVE_CC_PU(RP1A5);
-			break;
-		case TYPEC_RP_3A0:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			break;
-		case TYPEC_RP_RESERVED:
-			/*
-			 * This case can be used to force a detach event since
-			 * all values are set to inputs above. Nothing else to
-			 * set.
-			 */
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-
-		/* TODO: Verify this (CC_EMCA_SERVO) statement works */
-		if (cc_config & CC_EMCA_SERVO)
-			DUT_INACTIVE_CC_PD(RA);
-		else
-			DUT_INACTIVE_CC_OPEN(RA);
-	} else {
-		/* DTS mode is enabled. The rp parameter is used to select the
-		 * Type C current limit to advertise. The combinations of Rp on
-		 * each CC line is shown in the table below.
-		 *
-		 * CC values for Debug sources (DTS)
-		 *
-		 * Source type  Mode of Operation   CC1    CC2
-		 * ---------------------------------------------
-		 * DTS          Default USB Power   Rp3A0  Rp1A5
-		 * DTS          USB-C @ 1.5 A       Rp1A5  RpUSB
-		 * DTS          USB-C @ 3 A         Rp3A0  RpUSB
-		 */
-		switch (rp) {
-		case TYPEC_RP_USB:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			DUT_INACTIVE_CC_PU(RP1A5);
-			break;
-		case TYPEC_RP_1A5:
-			DUT_ACTIVE_CC_PU(RP1A5);
-			DUT_INACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_3A0:
-			DUT_ACTIVE_CC_PU(RP3A0);
-			DUT_INACTIVE_CC_PU(RPUSB);
-			break;
-		case TYPEC_RP_RESERVED:
-			/*
-			 * This case can be used to force a detach event since
-			 * all values are set to inputs above. Nothing else to
-			 * set.
-			 */
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-	}
-	/* Save new Rp value for DUT port */
-	vbus_rp = rp;
-
-	return EC_SUCCESS;
-}
-
-int pd_set_rp_rd(int port, int cc_pull, int rp_value)
-{
-	int rv = EC_SUCCESS;
-
-	if (port != DUT)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* CC is disabled for emulating detach. Don't change Rd/Rp. */
-	if (cc_config & CC_DETACH)
-		return EC_SUCCESS;
-
-	/* By default disconnect all Rp/Rd resistors from both CC lines */
-	/* Set Rd for CC1/CC2 to High-Z. */
-	DUT_BOTH_CC_OPEN(RD);
-	/* Set Ra for CC1/CC2 to High-Z. */
-	DUT_BOTH_CC_OPEN(RA);
-	/* Set Rp for CC1/CC2 to High-Z. */
-	DUT_BOTH_CC_OPEN(RP3A0);
-	DUT_BOTH_CC_OPEN(RP1A5);
-	DUT_BOTH_CC_OPEN(RPUSB);
-	/* Set TX Hi-Z */
-	DUT_BOTH_CC_OPEN(TX_DATA);
-
-	if (cc_pull == TYPEC_CC_RP) {
-		rv = board_set_rp(rp_value);
-	} else if ((cc_pull == TYPEC_CC_RD) || (cc_pull == TYPEC_CC_RA_RD) ||
-				(cc_pull == TYPEC_CC_RA)) {
-		/*
-		 * The DUT port uses a captive cable. It can present Rd on both
-		 * CC1 and CC2. If DTS mode is enabled, then present Rd on both
-		 * CC lines. However, if DTS mode is disabled only present Rd on
-		 * CC1 (active).
-		 *
-		 * TODO: EXCEPT if you have Ra_Rd or are "faking" an EMCA.....
-		 * ... or are applying RA+RA....can't make assumptions with
-		 * test equipment!
-		 */
-		if (cc_config & CC_DISABLE_DTS) {
-			if (cc_pull == TYPEC_CC_RD) {
-				DUT_ACTIVE_CC_PD(RD);
-				/*
-				 * TODO: Verify this (CC_EMCA_SERVO)
-				 * statement works
-				 */
-				if (cc_config & CC_EMCA_SERVO)
-					DUT_INACTIVE_CC_PD(RA);
-				else
-					DUT_INACTIVE_CC_OPEN(RA);
-			} else if (cc_pull == TYPEC_CC_RA) {
-				DUT_ACTIVE_CC_PD(RA);
-				/*
-				 * TODO: Verify this (CC_EMCA_SERVO)
-				 * statement works
-				 */
-				if (cc_config & CC_EMCA_SERVO)
-					DUT_INACTIVE_CC_PD(RA);
-				else
-					DUT_INACTIVE_CC_OPEN(RA);
-			} else if (cc_pull == TYPEC_CC_RA_RD) {
-				/*
-				 * TODO: Verify this silly (TYPEC_CC_RA_RD)
-				 * from TCPMv  works
-				 */
-				DUT_ACTIVE_CC_PD(RD);
-				DUT_INACTIVE_CC_PD(RA);
-			}
-		} else
-			DUT_BOTH_CC_PD(RD);
-
-		rv = EC_SUCCESS;
-	} else
-		return EC_ERROR_UNIMPLEMENTED;
-
-	rp_value_stored = rp_value;
-	cc_pull_stored = cc_pull;
-
-	return rv;
-}
-
-int board_select_rp_value(int port, int rp)
-{
-	if (port != DUT)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/*
-	 * Update Rp value to indicate non-pd power available.
-	 * Do not change pull direction though.
-	 */
-	if ((rp != rp_value_stored) && (cc_pull_stored == TYPEC_CC_RP)) {
-		rp_value_stored = rp;
-		return pd_set_rp_rd(port, TYPEC_CC_RP, rp);
-	}
-
-	return EC_SUCCESS;
-}
-
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	int pdo_cnt = 0;
-
-	/*
-	 * If CHG is providing VBUS, then advertise what's available on the CHG
-	 * port, otherwise we provide no power.
-	 */
-	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
-		pdo_cnt = chg_pdo_cnt;
-	}
-
-	return pdo_cnt;
-}
-
-__override void pd_transition_voltage(int idx)
-{
-	timestamp_t deadline;
-	uint32_t ma, mv, unused;
-
-	pd_extract_pdo_power(pd_src_chg_pdo[idx - 1], &ma, &mv, &unused);
-	/* Is this a transition to a new voltage? */
-	if (charge_port_is_active() && vbus[CHG].mv != mv) {
-		/*
-		 * Alter voltage limit on charge port, this should cause
-		 * the port to select the desired PDO.
-		 */
-		pd_set_external_voltage_limit(CHG, mv);
-
-		/* Wait for CHG transition */
-		deadline.val = get_time().val + PD_T_PS_TRANSITION;
-		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
-		       get_time().val < deadline.val)
-			msleep(10);
-
-		if (vbus[CHG].mv != mv) {
-			CPRINTS("Missed CHG transition, resetting DUT");
-			pd_power_supply_reset(DUT);
-			return;
-		}
-
-		CPRINTS("CHG transitioned");
-	}
-
-	vbus[DUT].mv = vbus[CHG].mv;
-	vbus[DUT].ma = vbus[CHG].ma;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return EC_ERROR_INVAL;
-
-	if (charge_port_is_active()) {
-		/* Enable VBUS */
-		chg_power_select(CHG_POWER_VBUS);
-		dut_chg_en(1);
-
-		if (vbus[CHG].mv != PD_MIN_MV)
-			CPRINTS("ERROR, CHG port voltage %d != PD_MIN_MV",
-				vbus[CHG].mv);
-
-		vbus[DUT].mv = vbus[CHG].mv;
-		vbus[DUT].ma = vbus[CHG].mv;
-		pd_set_dual_role(DUT, get_dual_role_of_src());
-	} else {
-		vbus[DUT].mv = 0;
-		vbus[DUT].ma = 0;
-		dut_chg_en(0);
-		pd_set_dual_role(DUT, PD_DRP_FORCE_SINK);
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return;
-
-	/* Disable VBUS */
-	chg_power_select(CHG_POWER_OFF);
-	dut_chg_en(0);
-
-	/* DUT is lost, back to 5V limit on CHG */
-	pd_set_external_voltage_limit(CHG, PD_MIN_MV);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/*
-	 * When only host VBUS is available, then servo_v4 is not setting
-	 * PDO_FIXED_UNCONSTRAINED in the src_pdo sent to the DUT. When this bit
-	 * is not set, the DUT will always attempt to swap its power role to
-	 * SRC. Let servo_v4 have more control over its power role by always
-	 * rejecting power swap requests from the DUT.
-	 */
-
-	/* Port 0 can never provide vbus. */
-	if (port == CHG)
-		return 0;
-
-	if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC))
-		return 0;
-
-	if (pd_snk_is_vbus_provided(CHG))
-		return allow_pr_swap;
-
-	return 0;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/*
-	 * Servo should allow data role swaps to let DUT see the USB hub, but
-	 * doing it on CHG port is a waste as its data lines is unconnected.
-	 */
-	if (port == CHG)
-		return 0;
-
-	return allow_dr_swap;
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	if (port == CHG)
-		return;
-
-	switch (data_role) {
-	case PD_ROLE_DFP:
-		if (cc_config & CC_FASTBOOT_DFP) {
-			dut_to_host();
-		} else {
-			/* Disable USB2 lines from DUT */
-			gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 1);
-			uservo_to_host();
-		}
-		break;
-	case PD_ROLE_UFP:
-		/* Ensure that FASTBOOT is disabled */
-		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_SEL, 1);
-
-		/* Enable USB2 lines */
-		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 0);
-
-		/*
-		 * By default, uServo port will be enabled. Only if the user
-		 * explicitly enable CC_FASTBOOT_DFP then uServo is disabled.
-		 */
-		if (!(cc_config & CC_FASTBOOT_DFP))
-			uservo_to_host();
-		break;
-	case PD_ROLE_DISCONNECTED:
-		/* Disable USB2 lines */
-		gpio_set_level(GPIO_FASTBOOT_DUTHUB_MUX_EN_L, 1);
-
-		if (!(cc_config & CC_FASTBOOT_DFP))
-			uservo_to_host();
-		break;
-	default:
-		CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__,  data_role);
-	}
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-	/*
-	 * Don't define any policy to initiate power role swap.
-	 *
-	 * CHG port is SNK only. DUT port requires a user to switch its
-	 * role by commands. So don't do anything implicitly.
-	 */
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-	if (port == CHG)
-		return;
-
-	/* If DFP, try to switch to UFP, to let DUT see the USB hub. */
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
-		pd_request_data_swap(port);
-}
-
-
-/* ----------------- Vendor Defined Messages ------------------ */
-/*
- * DP alt-mode config, user configurable.
- * Default is the mode disabled, supporting the C and D pin assignment,
- * multi-function preferred, and a plug.
- */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
-
-/**
- * Get the pins based on the user config.
- */
-static int alt_dp_config_pins(void)
-{
-	int pins = 0;
-
-	if (alt_dp_config & ALT_DP_PIN_C)
-		pins |= MODE_DP_PIN_C;
-	if (alt_dp_config & ALT_DP_PIN_D)
-		pins |= MODE_DP_PIN_D;
-	return pins;
-}
-
-/**
- * Get the cable outlet value (plug or receptacle) based on the user config.
- */
-static int alt_dp_config_cable(void)
-{
-	return (alt_dp_config & ALT_DP_PLUG) ? CABLE_PLUG : CABLE_RECEPTACLE;
-}
-
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 1, /* data caps as USB device */
-				 IDH_PTYPE_AMA, /* Alternate mode */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
-				 0, /* Vconn power */
-				 0, /* Vconn power required */
-				 0, /* Vbus power required */
-				 AMA_USBSS_U31_GEN1 /* USB SS support */);
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	int dp_supported = (alt_dp_config & ALT_DP_ENABLE) != 0;
-
-	if (dp_supported) {
-		payload[VDO_I(IDH)] = vdo_idh;
-		payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-		payload[VDO_I(PRODUCT)] = vdo_product;
-		payload[VDO_I(AMA)] = vdo_ama;
-		return VDO_I(AMA) + 1;
-	} else {
-		return 0;
-	}
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_SID_DISPLAYPORT, 0);
-	return 2;
-}
-
-#define MODE_CNT 1
-#define OPOS 1
-
-/*
- * The Type-C demux TUSB1064 supports pin assignment C and D. Response the DP
- * capabilities with supporting all of them.
- */
-uint32_t vdo_dp_mode[MODE_CNT];
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
-
-	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
-	if (!(cc_config & CC_DISABLE_DTS))
-		return 0; /* NAK */
-
-	if (PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT)
-		return 0; /* NAK */
-
-	memcpy(payload + 1, vdo_dp_mode, sizeof(vdo_dp_mode));
-	return MODE_CNT + 1;
-}
-
-static void set_typec_mux(int pin_cfg)
-{
-	mux_state_t mux_mode = USB_PD_MUX_NONE;
-
-	switch (pin_cfg) {
-	case 0: /* return to USB3 only */
-		mux_mode = USB_PD_MUX_USB_ENABLED;
-		CPRINTS("PinCfg:off");
-		break;
-	case MODE_DP_PIN_C: /* DisplayPort 4 lanes */
-		mux_mode = USB_PD_MUX_DP_ENABLED;
-		CPRINTS("PinCfg:C");
-		break;
-	case MODE_DP_PIN_D: /* DP + USB */
-		mux_mode = USB_PD_MUX_DOCK;
-		CPRINTS("PinCfg:D");
-		break;
-	default:
-		CPRINTS("PinCfg not supported: %d", pin_cfg);
-		return;
-	}
-
-	usb_mux_set(DUT, mux_mode, USB_SWITCH_CONNECT,
-		    !!(cc_config & CC_POLARITY));
-}
-
-static int get_hpd_level(void)
-{
-	if (alt_dp_config & ALT_DP_OVERRIDE_HPD)
-		return (alt_dp_config & ALT_DP_HPD_LVL) != 0;
-	else
-		return gpio_get_level(GPIO_DP_HPD);
-}
-
-static int dp_status(int port, uint32_t *payload)
-{
-	int opos = PD_VDO_OPOS(payload[0]);
-	int hpd = get_hpd_level();
-	mux_state_t state = usb_mux_get(DUT);
-	int dp_enabled = !!(state & USB_PD_MUX_DP_ENABLED);
-
-	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		dp_enabled,
-		0,                /* power low */
-		hpd ? 0x2 : 0);
-
-	return 2;
-}
-
-static int dp_config(int port, uint32_t *payload)
-{
-	if (PD_DP_CFG_DPON(payload[1]))
-		set_typec_mux(PD_DP_CFG_PIN(payload[1]));
-
-	return 1;
-}
-
-/* Whether alternate mode has been entered or not */
-static int alt_mode;
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
-	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
-
-	alt_mode = OPOS;
-	return 1;
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	if (type != TCPCI_MSG_SOP)
-		return 0;
-
-	if (svid == USB_SID_DISPLAYPORT)
-		return alt_mode;
-
-	return 0;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT)
-		set_typec_mux(0);
-
-	alt_mode = 0;
-
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = &dp_status,
-	.config = &dp_config,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-
-	/* make sure we have some payload */
-	if (cnt == 0)
-		return 0;
-
-	switch (cmd) {
-	case VDO_CMD_VERSION:
-		/* guarantee last byte of payload is null character */
-		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
-		break;
-	case VDO_CMD_CURRENT:
-		CPRINTF("Current: %dmA\n", payload[1]);
-		break;
-	}
-
-	return 0;
-}
-
-__override const struct svdm_amode_fx supported_modes[] = {};
-__override const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
-
-static void print_cc_mode(void)
-{
-	/* Get current CCD status */
-	ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on");
-	ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on");
-	ccprintf("chg mode: %s\n",
-		 get_dut_chg_en() ? "on" : "off");
-	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
-	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
-	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
-	ccprintf("emca: %s\n", cc_config & CC_EMCA_SERVO ?
-					"emarked" : "non-emarked");
-}
-
-
-static void do_cc(int cc_config_new)
-{
-	int chargeable;
-	int dualrole;
-
-	if (cc_config_new != cc_config) {
-		if (!(cc_config & CC_DETACH)) {
-			/* Force detach */
-			pd_power_supply_reset(DUT);
-			/* Always set to 0 here so both CC lines are changed */
-			cc_config &= ~(CC_DISABLE_DTS & CC_ALLOW_SRC);
-
-			/* Remove Rp/Rd on both CC lines */
-			pd_comm_enable(DUT, 0);
-			pd_set_rp_rd(DUT, TYPEC_CC_RP, TYPEC_RP_RESERVED);
-
-			/*
-			 * If just changing mode (cc keeps enabled), give some
-			 * time for DUT to detach, use tErrorRecovery.
-			 */
-			if (!(cc_config_new & CC_DETACH))
-				usleep(PD_T_ERROR_RECOVERY);
-		}
-
-		if ((cc_config & ~cc_config_new) & CC_DISABLE_DTS) {
-			/* DTS-disabled -> DTS-enabled */
-			ccd_enable(1);
-			ext_hpd_detection_enable(0);
-		} else if ((cc_config_new & ~cc_config) & CC_DISABLE_DTS) {
-			/* DTS-enabled -> DTS-disabled */
-			ccd_enable(0);
-			if (!(alt_dp_config & ALT_DP_OVERRIDE_HPD))
-				ext_hpd_detection_enable(1);
-		}
-
-		/* Accept new cc_config value */
-		cc_config = cc_config_new;
-
-		if (!(cc_config & CC_DETACH)) {
-			/* Can we source? */
-			chargeable = is_charge_through_allowed();
-			dualrole = chargeable ? get_dual_role_of_src() :
-						PD_DRP_FORCE_SINK;
-			pd_set_dual_role(DUT, dualrole);
-			/*
-			 * If force_source or force_sink role, explicitly set
-			 * the Rp or Rd resistors on CC lines.
-			 *
-			 * If DRP role, don't set any CC pull resistor, the PD
-			 * state machine will toggle and set the pull resistors
-			 * when needed.
-			 */
-			if (dualrole != PD_DRP_TOGGLE_ON)
-				pd_set_host_mode(DUT, chargeable);
-
-			/*
-			 * For the normal lab use, emulating a sink has no PD
-			 * comm, like a passive hub. For the PD FAFT use, we
-			 * need to validate some PD behavior, so a flag
-			 * CC_SNK_WITH_PD to force enabling PD comm.
-			 */
-			if (cc_config & CC_SNK_WITH_PD)
-				pd_comm_enable(DUT, 1);
-			else
-				pd_comm_enable(DUT, chargeable);
-		}
-	}
-}
-
-static int command_cc(int argc, char **argv)
-{
-	int cc_config_new = cc_config;
-
-	if (argc < 2) {
-		print_cc_mode();
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "off")) {
-		cc_config_new |= CC_DETACH;
-	} else if (!strcasecmp(argv[1], "on")) {
-		cc_config_new &= ~CC_DETACH;
-	} else {
-		cc_config_new &= ~CC_DETACH;
-		if (!strcasecmp(argv[1], "src"))
-			cc_config_new = CONF_SRC(cc_config_new);
-		else if (!strcasecmp(argv[1], "snk"))
-			cc_config_new = CONF_SNK(cc_config_new);
-		else if (!strcasecmp(argv[1], "pdsnk"))
-			cc_config_new = CONF_PDSNK(cc_config_new);
-		else if (!strcasecmp(argv[1], "drp"))
-			cc_config_new = CONF_DRP(cc_config_new);
-		else if (!strcasecmp(argv[1], "srcdts"))
-			cc_config_new = CONF_SRCDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "snkdts"))
-			cc_config_new = CONF_SNKDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "pdsnkdts"))
-			cc_config_new = CONF_PDSNKDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "drpdts"))
-			cc_config_new = CONF_DRPDTS(cc_config_new);
-		else if (!strcasecmp(argv[1], "emca"))
-			cc_config_new |= CC_EMCA_SERVO;
-		else if (!strcasecmp(argv[1], "nonemca"))
-			cc_config_new &= ~CC_EMCA_SERVO;
-		else
-			return EC_ERROR_PARAM2;
-	}
-
-	if (!strcasecmp(argv[2], "cc1"))
-		cc_config_new &= ~CC_POLARITY;
-	else if (!strcasecmp(argv[2], "cc2"))
-		cc_config_new |= CC_POLARITY;
-	else if (argc >= 3)
-		return EC_ERROR_PARAM3;
-
-	do_cc(cc_config_new);
-	print_cc_mode();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(cc, command_cc,
-			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts|emca|nonemca] [cc1|cc2]",
-			"Servo_v4 DTS and CHG mode");
-
-static void fake_disconnect_end(void)
-{
-	/* Reenable CC lines with previous dts and src modes */
-	do_cc(cc_config & ~CC_DETACH);
-}
-DECLARE_DEFERRED(fake_disconnect_end);
-
-static void fake_disconnect_start(void)
-{
-	/* Disable CC lines */
-	do_cc(cc_config | CC_DETACH);
-
-	hook_call_deferred(&fake_disconnect_end_data,
-			   fake_pd_disconnect_duration_us);
-}
-DECLARE_DEFERRED(fake_disconnect_start);
-
-static int cmd_fake_disconnect(int argc, char *argv[])
-{
-	int delay_ms, duration_ms;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	delay_ms = strtoi(argv[1], &e, 0);
-	if (*e || delay_ms < 0)
-		return EC_ERROR_PARAM1;
-	duration_ms = strtoi(argv[2], &e, 0);
-	if (*e || duration_ms < 0)
-		return EC_ERROR_PARAM2;
-
-	/* Cancel any pending function calls */
-	hook_call_deferred(&fake_disconnect_start_data, -1);
-	hook_call_deferred(&fake_disconnect_end_data, -1);
-
-	fake_pd_disconnect_duration_us = duration_ms * MSEC;
-	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
-
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
-			"<delay_ms> <duration_ms>", NULL);
-
-static int cmd_ada_srccaps(int argc, char *argv[])
-{
-	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
-
-	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
-		uint32_t max_ma, max_mv, unused;
-
-		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
-		    (ada_srccaps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-			continue;
-
-		pd_extract_pdo_power(ada_srccaps[i], &max_ma, &max_mv, &unused);
-
-		ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
-			"Print adapter SrcCap");
-
-static int cmd_dp_action(int argc, char *argv[])
-{
-	int i;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (argc == 1) {
-		CPRINTS("DP alt-mode: %s",
-			(alt_dp_config & ALT_DP_ENABLE) ? "enable" : "disable");
-	}
-
-	if (!strcasecmp(argv[1], "enable")) {
-		alt_dp_config |= ALT_DP_ENABLE;
-	} else if (!strcasecmp(argv[1], "disable")) {
-		alt_dp_config &= ~ALT_DP_ENABLE;
-	} else if (!strcasecmp(argv[1], "pins")) {
-		if (argc >= 3) {
-			alt_dp_config &= ~(ALT_DP_PIN_C | ALT_DP_PIN_D);
-			for (i = 0; i < 3; i++) {
-				if (!argv[2][i])
-					break;
-
-				switch (argv[2][i]) {
-				case 'c':
-				case 'C':
-					alt_dp_config |= ALT_DP_PIN_C;
-					break;
-				case 'd':
-				case 'D':
-					alt_dp_config |= ALT_DP_PIN_D;
-					break;
-				}
-			}
-		}
-		CPRINTS("Pins: %s%s",
-			(alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
-			(alt_dp_config & ALT_DP_PIN_D) ? "D" : "");
-	} else if (!strcasecmp(argv[1], "mf")) {
-		if (argc >= 3) {
-			i = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			if (i)
-				alt_dp_config |= ALT_DP_MF_PREF;
-			else
-				alt_dp_config &= ~ALT_DP_MF_PREF;
-		}
-		CPRINTS("MF pref: %d", (alt_dp_config & ALT_DP_MF_PREF) != 0);
-	} else if (!strcasecmp(argv[1], "plug")) {
-		if (argc >= 3) {
-			i = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			if (i)
-				alt_dp_config |= ALT_DP_PLUG;
-			else
-				alt_dp_config &= ~ALT_DP_PLUG;
-		}
-		CPRINTS("Plug or receptacle: %d",
-			(alt_dp_config & ALT_DP_PLUG) != 0);
-	} else if (!strcasecmp(argv[1], "hpd")) {
-		if (argc >= 3) {
-			if (!strncasecmp(argv[2], "ext", 3)) {
-				alt_dp_config &= ~ALT_DP_OVERRIDE_HPD;
-				ext_hpd_detection_enable(1);
-			} else if (!strncasecmp(argv[2], "h", 1)) {
-				alt_dp_config |= ALT_DP_OVERRIDE_HPD;
-				alt_dp_config |= ALT_DP_HPD_LVL;
-				/*
-				 * Modify the HPD to high. Need to enable the
-				 * external HPD signal monitoring. A monitor
-				 * may send a IRQ at any time to notify DUT.
-				 */
-				ext_hpd_detection_enable(1);
-				pd_send_hpd(DUT, hpd_high);
-			} else if (!strncasecmp(argv[2], "l", 1)) {
-				alt_dp_config |= ALT_DP_OVERRIDE_HPD;
-				alt_dp_config &= ~ALT_DP_HPD_LVL;
-				ext_hpd_detection_enable(0);
-				pd_send_hpd(DUT, hpd_low);
-			} else if (!strcasecmp(argv[2], "irq")) {
-				pd_send_hpd(DUT, hpd_irq);
-			}
-		}
-		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
-		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
-		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
-			"plug]");
-	}
-
-	return EC_SUCCESS;
-}
-
-static int cmd_usbc_action(int argc, char *argv[])
-{
-	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
-		return cmd_dp_action(argc - 1, &argv[1]);
-
-	if (argc != 2 && argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* TODO(b:140256624): drop *v command if we migrate to chg cmd. */
-	if (!strcasecmp(argv[1], "5v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 5000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "12v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 12000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "20v")) {
-		do_cc(CONF_SRC(cc_config));
-		user_limited_max_mv = 20000;
-		update_ports();
-	} else if (!strcasecmp(argv[1], "dev")) {
-		/* Set the limit back to original */
-		user_limited_max_mv = 20000;
-		do_cc(CONF_PDSNK(cc_config));
-	} else if (!strcasecmp(argv[1], "pol0")) {
-		do_cc(cc_config & ~CC_POLARITY);
-	} else if (!strcasecmp(argv[1], "pol1")) {
-		do_cc(cc_config | CC_POLARITY);
-	} else if (!strcasecmp(argv[1], "drp")) {
-		/* Toggle the DRP state, compatible with Plankton. */
-		do_cc(cc_config ^ CC_ENABLE_DRP);
-		CPRINTF("DRP = %d, host_mode = %d\n",
-			!!(cc_config & CC_ENABLE_DRP),
-			!!(cc_config & CC_ALLOW_SRC));
-	} else if (!strcasecmp(argv[1], "chg")) {
-		int sink_v;
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		sink_v = atoi(argv[2]);
-		if (!sink_v)
-			return EC_ERROR_PARAM2;
-
-		user_limited_max_mv = sink_v * 1000;
-		do_cc(CONF_SRC(cc_config));
-		update_ports();
-		/*
-		 * TODO(b:140256624): servod captures 'chg SRC' keyword to
-		 * recognize if this command is supported in the firmware.
-		 * Drop this message if when we phase out the usbc_role control.
-		 */
-		ccprintf("CHG SRC %dmV\n", user_limited_max_mv);
-	} else if (!strcasecmp(argv[1], "drswap")) {
-		if (argc == 2) {
-			CPRINTF("allow_dr_swap = %d\n", allow_dr_swap);
-			return EC_SUCCESS;
-		}
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		allow_dr_swap = !!atoi(argv[2]);
-
-	} else if (!strcasecmp(argv[1], "prswap")) {
-		if (argc == 2) {
-			CPRINTF("allow_pr_swap = %d\n", allow_pr_swap);
-			return EC_SUCCESS;
-		}
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		allow_pr_swap = !!atoi(argv[2]);
-	} else if (!strcasecmp(argv[1], "fastboot")) {
-		if (argc == 2) {
-			CPRINTF("fastboot = %d\n",
-				!!(cc_config & CC_FASTBOOT_DFP));
-			return EC_SUCCESS;
-		}
-
-		if (argc != 3)
-			return EC_ERROR_PARAM2;
-
-		if (!!atoi(argv[2]))
-			cc_config |= CC_FASTBOOT_DFP;
-		else
-			cc_config &= ~CC_FASTBOOT_DFP;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(usbc_action, cmd_usbc_action,
-			"5v|12v|20v|dev|pol0|pol1|drp|dp|chg x(x=voltage)|"
-			"drswap [1|0]|prswap [1|0]",
-			"Set Servo v4 type-C port state");
diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c
deleted file mode 100644
index 94b5e0c08d..0000000000
--- a/board/servo_v4p1/usb_sm.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "stdbool.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* Private structure (to this file) used to track state machine context */
-struct internal_ctx {
-	usb_state_ptr last_entered;
-	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
-};
-BUILD_ASSERT(sizeof(struct internal_ctx) ==
-	     member_size(struct sm_ctx, internal));
-
-/* Gets the first shared parent state between a and b (inclusive) */
-static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
-{
-	const usb_state_ptr orig_b = b;
-
-	/* There are no common ancestors */
-	if (b == NULL)
-		return NULL;
-
-	/* This assumes that both A and B are NULL terminated without cycles */
-	while (a != NULL) {
-		/* We found a match return */
-		if (a == b)
-			return a;
-
-		/*
-		 * Otherwise, increment b down the list for comparison until we
-		 * run out, then increment a and start over on b for comparison
-		 */
-		if (b->parent == NULL) {
-			a = a->parent;
-			b = orig_b;
-		} else {
-			b = b->parent;
-		}
-	}
-
-	return NULL;
-}
-
-/*
- * Call all entry functions of parents before children. If set_state is called
- * during one of the entry functions, then do not call any remaining entry
- * functions.
- */
-static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
-{
-	if (current == stop)
-		return;
-
-	call_entry_functions(port, internal, stop, current->parent);
-
-	/*
-	 * If the previous entry function called set_state, then don't enter
-	 * remaining states.
-	 */
-	if (!internal->enter)
-		return;
-
-	/* Track the latest state that was entered, so we can exit properly. */
-	internal->last_entered = current;
-	if (current->entry)
-		current->entry(port);
-}
-
-/*
- * Call all exit functions of children before parents. Note set_state is ignored
- * during an exit function.
- */
-static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
-{
-	if (current == stop)
-		return;
-
-	if (current->exit)
-		current->exit(port);
-
-	call_exit_functions(port, stop, current->parent);
-}
-
-void set_state(const int port, struct sm_ctx *const ctx,
-	       const usb_state_ptr new_state)
-{
-	struct internal_ctx * const internal = (void *) ctx->internal;
-	usb_state_ptr last_state;
-	usb_state_ptr shared_parent;
-
-	/*
-	 * It does not make sense to call set_state in an exit phase of a state
-	 * since we are already in a transition; we would always ignore the
-	 * intended state to transition into.
-	 */
-	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
-		return;
-	}
-
-	/*
-	 * Determine the last state that was entered. Normally it is current,
-	 * but we could have called set_state within an entry phase, so we
-	 * shouldn't exit any states that weren't fully entered.
-	 */
-	last_state = internal->enter ? internal->last_entered : ctx->current;
-
-	/* We don't exit and re-enter shared parent states */
-	shared_parent = shared_parent_state(last_state, new_state);
-
-	/*
-	 * Exit all of the non-common states from the last state.
-	 */
-	internal->exit = true;
-	call_exit_functions(port, shared_parent, last_state);
-	internal->exit = false;
-
-	ctx->previous = ctx->current;
-	ctx->current = new_state;
-
-	/*
-	 * Enter all new non-common states. last_entered will contain the last
-	 * state that successfully entered before another set_state was called.
-	 */
-	internal->last_entered = NULL;
-	internal->enter = true;
-	call_entry_functions(port, internal, shared_parent, ctx->current);
-	/*
-	 * Setting enter to false ensures that all pending entry calls will be
-	 * skipped (in the case of a parent state calling set_state, which means
-	 * we should not enter any child states)
-	 */
-	internal->enter = false;
-
-	/*
-	 * If we set_state while we are running a child state, then stop running
-	 * any remaining parent states.
-	 */
-	internal->running = false;
-}
-
-/*
- * Call all run functions of children before parents. If set_state is called
- * during one of the entry functions, then do not call any remaining entry
- * functions.
- */
-static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
-{
-	if (!current)
-		return;
-
-	/* If set_state is called during run, don't call remain functions. */
-	if (!internal->running)
-		return;
-
-	if (current->run)
-		current->run(port);
-
-	call_run_functions(port, internal, current->parent);
-}
-
-void run_state(const int port, struct sm_ctx *const ctx)
-{
-	struct internal_ctx * const internal = (void *) ctx->internal;
-
-	internal->running = true;
-	call_run_functions(port, internal, ctx->current);
-	internal->running = false;
-}
diff --git a/board/servo_v4p1/usb_tc_snk_sm.c b/board/servo_v4p1/usb_tc_snk_sm.c
deleted file mode 100644
index f9a3966434..0000000000
--- a/board/servo_v4p1/usb_tc_snk_sm.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fusb302b.h"
-#include "ioexpanders.h"
-#include "system.h"
-#include "task.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-
-#define EVT_TIMEOUT_NEVER  (-1)
-#define EVT_TIMEOUT_5MS    (5 * MSEC)
-
-/*
- * USB Type-C Sink
- *   See Figure 4-13 in Release 1.4 of USB Type-C Spec.
- */
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Type-C Layer Flags */
-
-/* List of all TypeC-level states */
-enum usb_tc_state {
-	TC_UNATTACHED_SNK,
-	TC_ATTACH_WAIT_SNK,
-	TC_ATTACHED_SNK,
-};
-/* Forward declare the full list of states. This is indexed by usb_tc_state */
-static const struct usb_state tc_states[];
-
-/* TypeC Power strings */
-static const char * const pwr2_5_str = "5V/0.5A";
-static const char * const pwr7_5_str = "5V/1.5A";
-static const char * const pwr15_str  = "5V/3A";
-
-static struct type_c {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* Port polarity */
-	enum tcpc_cc_polarity polarity;
-	/* event timeout */
-	uint64_t evt_timeout;
-	/* Time a port shall wait before it can determine it is attached */
-	uint64_t cc_debounce;
-	/*
-	 * Time a Sink port shall wait before it can determine it is detached
-	 * due to the potential for USB PD signaling on CC as described in
-	 * the state definitions.
-	 */
-	uint64_t pd_debounce;
-	/* The cc state */
-	enum pd_cc_states cc_state;
-	/* Generic timer */
-	uint64_t timeout;
-	/* Voltage on CC pin */
-	enum tcpc_cc_voltage_status cc_voltage;
-	/* Current CC1 value */
-	int cc1;
-	/* Current CC2 value */
-	int cc2;
-} tc;
-
-/* Forward declare common, private functions */
-static void set_state_tc(const enum usb_tc_state new_state);
-
-static void restart_tc_sm(enum usb_tc_state start_state)
-{
-	int res;
-
-	res = init_fusb302b(1);
-	CPRINTS("FUSB302b init %s", res ? "failed" : "ready");
-
-	/* State machine is disabled if init_fusb302b fails */
-	if (!res)
-		set_state_tc(start_state);
-
-	/* Disable timeout. Task will wake on interrupt */
-	tc.evt_timeout = EVT_TIMEOUT_NEVER;
-}
-
-/*
- * Private Functions
- */
-
-/* Set the TypeC state machine to a new state. */
-static void set_state_tc(const enum usb_tc_state new_state)
-{
-	set_state(0, &tc.ctx, &tc_states[new_state]);
-}
-
-static void print_alt_power(void)
-{
-	enum tcpc_cc_voltage_status cc;
-	char const *pwr;
-
-	cc = tc.polarity ? tc.cc2 : tc.cc1;
-	if (cc == TYPEC_CC_VOLT_OPEN ||
-		cc == TYPEC_CC_VOLT_RA || cc == TYPEC_CC_VOLT_RD) {
-		/* Supply removed or not detected */
-		return;
-	}
-
-	if (cc == TYPEC_CC_VOLT_RP_1_5)
-		pwr = pwr7_5_str;
-	else if (cc == TYPEC_CC_VOLT_RP_3_0)
-		pwr = pwr15_str;
-	else
-		pwr = pwr2_5_str;
-
-	CPRINTS("ALT: Switching to alternate supply @ %s", pwr);
-}
-
-static void sink_power_sub_states(void)
-{
-	enum tcpc_cc_voltage_status cc;
-	enum tcpc_cc_voltage_status new_cc_voltage;
-
-	cc = tc.polarity ? tc.cc2 : tc.cc1;
-
-	if (cc == TYPEC_CC_VOLT_RP_DEF)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_DEF;
-	else if (cc == TYPEC_CC_VOLT_RP_1_5)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_1_5;
-	else if (cc == TYPEC_CC_VOLT_RP_3_0)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_3_0;
-	else
-		new_cc_voltage = TYPEC_CC_VOLT_OPEN;
-
-	/* Debounce the cc state */
-	if (new_cc_voltage != tc.cc_voltage) {
-		tc.cc_voltage = new_cc_voltage;
-		tc.cc_debounce = get_time().val + PD_T_RP_VALUE_CHANGE;
-		return;
-	}
-
-	if (tc.cc_debounce == 0 || get_time().val < tc.cc_debounce)
-		return;
-
-	tc.cc_debounce = 0;
-	print_alt_power();
-}
-
-/*
- * TYPE-C State Implementations
- */
-
-/**
- * Unattached.SNK
- */
-static void tc_unattached_snk_entry(int port)
-{
-	tc.evt_timeout = EVT_TIMEOUT_NEVER;
-}
-
-static void tc_unattached_snk_run(int port)
-{
-	/*
-	 * The port shall transition to AttachWait.SNK when a Source
-	 * connection is detected, as indicated by the SNK.Rp state
-	 * on at least one of its CC pins.
-	 */
-	if (cc_is_rp(tc.cc1) || cc_is_rp(tc.cc2))
-		set_state_tc(TC_ATTACH_WAIT_SNK);
-}
-
-/**
- * AttachWait.SNK
- */
-static void tc_attach_wait_snk_entry(int port)
-{
-	tc.evt_timeout = EVT_TIMEOUT_5MS;
-	tc.cc_state = PD_CC_UNSET;
-}
-
-static void tc_attach_wait_snk_run(int port)
-{
-	enum pd_cc_states new_cc_state;
-
-	if (cc_is_rp(tc.cc1) && cc_is_rp(tc.cc2))
-		new_cc_state = PD_CC_DFP_DEBUG_ACC;
-	else if (cc_is_rp(tc.cc1) || cc_is_rp(tc.cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		new_cc_state = PD_CC_NONE;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc.cc_state) {
-		tc.cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
-		tc.pd_debounce = get_time().val + PD_T_PD_DEBOUNCE;
-		tc.cc_state = new_cc_state;
-		return;
-	}
-
-	/* Wait for CC debounce */
-	if (get_time().val < tc.cc_debounce)
-		return;
-
-	/*
-	 * The port shall transition to Attached.SNK after the state of only
-	 * one of the CC1 or CC2 pins is SNK.Rp for at least tCCDebounce and
-	 * VBUS is detected.
-	 */
-	if (is_vbus_present() && (new_cc_state == PD_CC_DFP_ATTACHED))
-		set_state_tc(TC_ATTACHED_SNK);
-	else
-		set_state_tc(TC_UNATTACHED_SNK);
-}
-
-/**
- * Attached.SNK
- */
-static void tc_attached_snk_entry(int port)
-{
-	print_alt_power();
-
-	tc.evt_timeout = EVT_TIMEOUT_NEVER;
-	tc.cc_debounce = 0;
-
-	/* Switch over to alternate supply */
-	en_pp5000_alt_3p3(1);
-}
-
-static void tc_attached_snk_run(int port)
-{
-	/* Detach detection */
-	if (!is_vbus_present()) {
-		set_state_tc(TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Run Sink Power Sub-State */
-	sink_power_sub_states();
-}
-
-static void tc_attached_snk_exit(int port)
-{
-	/* Alternate charger removed. Switch back to host power */
-	en_pp5000_alt_3p3(0);
-}
-
-/*
- * Type-C State
- *
- * TC_UNATTACHED_SNK
- * TC_ATTACH_WAIT_SNK
- * TC_TRY_WAIT_SNK
- * TC_ATTACHED_SNK
- */
-static const struct usb_state tc_states[] = {
-	[TC_UNATTACHED_SNK] = {
-		.entry	= tc_unattached_snk_entry,
-		.run	= tc_unattached_snk_run,
-	},
-	[TC_ATTACH_WAIT_SNK] = {
-		.entry	= tc_attach_wait_snk_entry,
-		.run	= tc_attach_wait_snk_run,
-	},
-	[TC_ATTACHED_SNK] = {
-		.entry	= tc_attached_snk_entry,
-		.run	= tc_attached_snk_run,
-		.exit	= tc_attached_snk_exit,
-	},
-};
-
-void snk_task(void *u)
-{
-	/* Unattached.SNK is the default starting state. */
-	restart_tc_sm(TC_UNATTACHED_SNK);
-
-	while (1) {
-		/* wait for next event or timeout expiration */
-		task_wait_event(tc.evt_timeout);
-
-		/* Sample CC lines */
-		get_cc(&tc.cc1, &tc.cc2);
-
-		/* Detect polarity */
-		tc.polarity = (tc.cc1 > tc.cc2) ? POLARITY_CC1 : POLARITY_CC2;
-
-		/* Run TypeC state machine */
-		run_state(0, &tc.ctx);
-	}
-}
-
diff --git a/board/shuboz/analyzestack.yaml b/board/shuboz/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/shuboz/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/shuboz/battery.c b/board/shuboz/battery.c
deleted file mode 100644
index 155cadab41..0000000000
--- a/board/shuboz/battery.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "common.h"
-#include "hooks.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* CM1500 50Wh */
-	[BATTERY_CM1500] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXXD3KB",
-			.device_name = "C140243",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000c,
-				.disconnect_val = 0x000c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11880, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_CM1500;
-
-static uint16_t current_table[] = {
-	2200,
-	1800,
-	1700,
-	1600,
-};
-#define NUM_CURRENT_LEVELS ARRAY_SIZE(current_table)
-
-#define TEMP_THRESHOLD 54
-static int current_level;
-
-/* Called by hook task every hook second (1 sec) */
-static void current_update(void)
-{
-	int t, temp;
-	int rv;
-	static int Uptime;
-	static int Dntime;
-
-	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &t);
-	if (rv != EC_SUCCESS)
-		return;
-
-	temp = K_TO_C(t);
-
-	if (temp > TEMP_THRESHOLD) {
-		Dntime = 0;
-		if (Uptime < 5)
-			Uptime++;
-		else {
-			Uptime = 0;
-			current_level++;
-		}
-	} else if (current_level != 0 && temp < TEMP_THRESHOLD) {
-		Uptime = 0;
-		if (Dntime < 5)
-			Dntime++;
-		else {
-			Dntime = 0;
-			current_level--;
-		}
-	} else {
-		Uptime = 0;
-		Dntime = 0;
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-	else if (current_level > NUM_CURRENT_LEVELS)
-		current_level = NUM_CURRENT_LEVELS;
-}
-DECLARE_HOOK(HOOK_SECOND, current_update, HOOK_PRIO_DEFAULT);
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	/*
-	 * Precharge must be executed when communication is failed on
-	 * dead battery.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-		return 0;
-
-	if (current_level != 0) {
-		if (curr->requested_current > current_table[current_level-1])
-			curr->requested_current =
-				current_table[current_level - 1];
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/shuboz/board.c b/board/shuboz/board.c
deleted file mode 100644
index 84e2249e44..0000000000
--- a/board/shuboz/board.c
+++ /dev/null
@@ -1,629 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "button.h"
-#include "cbi_ssfc.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "driver/usb_mux/ps8740.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "thermal.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
-
-#include "gpio_list.h"
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0, FLOAT_TO_FP(-1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) },
-};
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-static const mat33_fp_t base_standard_ref_icm = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)},
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void setup_base_gyro_config(void)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE GYRO is ICM426XX");
-	} else
-		ccprints("BASE GYRO is BMI160");
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-/*****************************************************************************
- * Board suspend / resume
- */
-
-static void board_chipset_resume(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
-{
-	int res;
-
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		/* Enable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
-	else
-		/* Disable IN_HPD on the DB */
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
-
-	res = ps8743_write(me, PS8743_REG_USB_EQ_RX, 0xB0);
-	return res;
-}
-
-
-/*****************************************************************************
- * USB-C
- */
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_set = &board_ps8743_mux_set,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		/*
-		 * Sensitive only to falling edges; GPIO is configured for both
-		 * because this input may be used for HDMI HPD instead.
-		 */
-		if (!gpio_get_level(signal))
-			nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	case USBC_PORT_C1:
-		ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-static void setup_fw_config(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL);
-
-	/* Config Thermal params */
-	thermal_params[0].temp_host[EC_TEMP_THRESH_HIGH] = C_TO_K(72);
-	thermal_params[0].temp_host[EC_TEMP_THRESH_HALT] = C_TO_K(80);
-	thermal_params[0].temp_host_release[EC_TEMP_THRESH_HIGH] = C_TO_K(67);
-	thermal_params[1].temp_host[EC_TEMP_THRESH_HIGH] = C_TO_K(72);
-	thermal_params[1].temp_host[EC_TEMP_THRESH_HALT] = C_TO_K(80);
-	thermal_params[1].temp_host_release[EC_TEMP_THRESH_HIGH] = C_TO_K(67);
-
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		setup_base_gyro_config();
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-/*
- * Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init().
- */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[IOEX_C1_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
diff --git a/board/shuboz/board.h b/board/shuboz/board.h
deleted file mode 100644
index 6c64cf5dda..0000000000
--- a/board/shuboz/board.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_DALBOZ
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USB_MUX_PS8740
-#define CONFIG_USB_MUX_PS8743
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PORT_ENABLE_DYNAMIC
-
-#undef  PD_MAX_CURRENT_MA
-#define PD_MAX_CURRENT_MA	3000
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
-
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-/* USB-A config */
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-
-/* Power  LEDs */
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/*
- * Jelboz's battery takes several seconds to come back out of its disconnect
- * state (~4 seconds on the unit I have, so give it a little more for margin).
- */
-#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-extern int I2C_PORT_BATTERY;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_CM1500,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-/**
- * SHUBOZ_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	SHUBOZ_MB_USBAC = 0,
-};
-
-/**
- * SHUBOZ_DB_D_OPT1_USBAC
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: TUSB522
- *	USB-C1  Speed: 5 Gbps
- *		Retimer: PS8740
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- */
-enum ec_cfg_usb_db_type {
-	SHUBOZ_DB_D_OPT1_USBAC = 0,
-};
-
-#include "cbi_ec_fw_config.h"
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/shuboz/build.mk b/board/shuboz/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/shuboz/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/shuboz/ec.tasklist b/board/shuboz/ec.tasklist
deleted file mode 100644
index d9c1606eb2..0000000000
--- a/board/shuboz/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/shuboz/gpio.inc b/board/shuboz/gpio.inc
deleted file mode 100644
index b093a7e6d6..0000000000
--- a/board/shuboz/gpio.inc
+++ /dev/null
@@ -1,134 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-/* PPC interrupts trigger on falling edge, but HDMI HPD triggers on rising edge. */
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP, 	ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-
-/*
- * Dalboz has 2 DB options, with different IO expanders. IOEX_C1_NCT3807 is the
- * OPT1 DB (USB-C1), IOEX_HDMI_PCAL6408 is the OPT2 DB (HDMI).
- */
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(IOEX_C1_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(IOEX_C0_NCT3807, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-
-IOEX(USB_A1_RETIMER_EN,		EXPIN(IOEX_C1_NCT3807, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(IOEX_C1_NCT3807, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C1_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(IOEX_C1_NCT3807, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(IOEX_C1_NCT3807, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,		EXPIN(IOEX_C1_NCT3807, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(IOEX_C1_NCT3807, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/shuboz/led.c b/board/shuboz/led.c
deleted file mode 100644
index af91f32ec6..0000000000
--- a/board/shuboz/led.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/shuboz/vif_override.xml b/board/shuboz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/shuboz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/soraka b/board/soraka
deleted file mode 120000
index e61be5c7db..0000000000
--- a/board/soraka
+++ /dev/null
@@ -1 +0,0 @@
-poppy
\ No newline at end of file
diff --git a/board/spherion/battery.c b/board/spherion/battery.c
deleted file mode 100644
index 3613a4750c..0000000000
--- a/board/spherion/battery.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "gpio.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305013",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AP15O5L;
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int charger_temp, charger_temp_c;
-	int on;
-
-	/* charge confrol if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON);
-	if (!on)
-		return 0;
-
-	/* charge control if outside of allowable temperature range */
-	if (curr->state == ST_CHARGE) {
-		temp_sensor_read(TEMP_SENSOR_CHARGER, &charger_temp);
-		charger_temp_c = K_TO_C(charger_temp);
-		if (charger_temp_c > 52)
-			curr->requested_current = MIN(curr->requested_current,
-			    2200);
-		else if (charger_temp_c > 48)
-			curr->requested_current = MIN(curr->requested_current,
-			    CONFIG_CHARGER_MAX_INPUT_CURRENT);
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/spherion/board.c b/board/spherion/board.c
deleted file mode 100644
index 1119b1f077..0000000000
--- a/board/spherion/board.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Spherion board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/mt6360.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/usb_mux/it5205.h"
-#include "driver/usb_mux/ps8743.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "regulator.h"
-#include "spi.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	/* Convert to mV (3000mV/1024). */
-	{"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
-	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-	{"TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH7},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* PWM */
-
-/*
- * PWM channels. Must be in the exactly same order as in enum pwm_channel.
- * There total three 16 bits clock prescaler registers for all pwm channels,
- * so use the same frequency and prescaler register setting is required if
- * number of pwm channel greater than three.
- */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = PWM_HW_CH_DCR2,
-		.flags = 0,
-		.freq_hz = 10000,
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-void board_usb_mux_init(void)
-{
-	if (board_get_sub_board() == SUB_BOARD_TYPEC)
-		ps8743_tune_usb_eq(&usb_muxes[1],
-				   PS8743_USB_EQ_TX_12_8_DB,
-				   PS8743_USB_EQ_RX_12_8_DB);
-}
-DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void board_suspend(void)
-{
-	gpio_set_level(GPIO_EN_5V_USM, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	gpio_set_level(GPIO_EN_5V_USM, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
diff --git a/board/spherion/board.h b/board/spherion/board.h
deleted file mode 100644
index a27258bc94..0000000000
--- a/board/spherion/board.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Spherion board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* Chipset config */
-
-/* Optional features */
-#define CONFIG_LTO
-#undef CONFIG_LOW_POWER_S0
-
-/*
- * TODO: Remove this option once the VBAT no longer keeps high when
- * system's power isn't presented.
- */
-#define CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Keyboard backliht */
-#define CONFIG_PWM_KBLIGHT
-
-/* Charger*/
-#define CONFIG_CHARGER_MAX_INPUT_CURRENT 3100
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-/* PD / USB-C / PPC */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define PD_MAX_POWER_MW 65000
-#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV 20000
-#define PD_OPERATING_POWER_MW 15000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#undef CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-
-/* Optional console commands */
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SCRATCHPAD
-#define CONFIG_CMD_STACKOVERFLOW
-
-/* Sensor */
-
-/* SPI / Host Command */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* USB-A */
-#define USBA_PORT_COUNT 1
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_TYPE_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum adc_channel {
-	ADC_VBUS_C0,             /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_VBUS_C1,             /* ADC 5 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
-	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
-	/* Number of ADC channels */
-	ADC_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/spherion/build.mk b/board/spherion/build.mk
deleted file mode 100644
index 4dc5a3e62e..0000000000
--- a/board/spherion/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is ITE IT8xxx2
-CHIP:=it83xx
-CHIP_FAMILY:=it8xxx2
-CHIP_VARIANT:=it81202bx_1024
-BASEBOARD:=asurada
-
-board-y+=battery.o board.o led.o
diff --git a/board/spherion/ec.tasklist b/board/spherion/ec.tasklist
deleted file mode 100644
index c92920ade6..0000000000
--- a/board/spherion/ec.tasklist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(PDCMD, pd_command_task, NULL, 1024) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, 1280) \
-
diff --git a/board/spherion/gpio.inc b/board/spherion/gpio.inc
deleted file mode 100644
index b618911e02..0000000000
--- a/board/spherion/gpio.inc
+++ /dev/null
@@ -1,149 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(POWER_BUTTON_L,     PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP |
-	 GPIO_HIB_WAKE_HIGH, power_button_interrupt) /* H1_EC_PWR_BTN_ODL */
-GPIO_INT(LID_OPEN,           PIN(E, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         lid_interrupt)
-
-/* Chipset interrupts */
-GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
-         chipset_reset_request_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         chipset_watchdog_interrupt)
-GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
-         GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
-
-/* Sensor Interrupts */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL, PIN(D, 1), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,PIN(J, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_L,  PIN(J, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(VOLUME_DOWN_L,      PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLDN_BTN_ODL */
-GPIO_INT(VOLUME_UP_L,        PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP,
-         button_interrupt) /* EC_VOLUP_BTN_ODL */
-
-/* Other interrupts */
-GPIO_INT(AP_XHCI_INIT_DONE,  PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
-         usb_a0_interrupt)
-GPIO_INT(AC_PRESENT,         PIN(E, 5), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,
-         extpower_interrupt) /* AC_OK / AC_PRESENT in rev1+ */
-GPIO_INT(UART1_RX,           PIN(B, 0), GPIO_INT_FALLING,
-         uart_deepsleep_interrupt) /* UART_DEBUG_TX_EC_RX */
-GPIO_INT(WP,                 PIN(I, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V,
-         switch_interrupt) /* EC_FLASH_WP_OD */
-GPIO_INT(SPI0_CS,            PIN(M, 5), GPIO_INT_FALLING,
-         spi_event)        /* SPI slave Chip Select -- AP_SPI_EC_CS_L */
-GPIO_INT(X_EC_GPIO2,         PIN(B, 2), GPIO_ODR_HIGH, x_ec_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EC_PMIC_EN_ODL,         PIN(D, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_PMIC_WATCHDOG_L,     PIN(H, 0), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_A,            PIN(C, 6), GPIO_OUT_HIGH)
-GPIO(PG_MT6315_PROC_ODL,     PIN(E, 1), GPIO_INPUT)
-GPIO(PG_MT6360_ODL,          PIN(F, 1), GPIO_INPUT)
-GPIO(PG_PP5000_A_ODL,        PIN(A, 6), GPIO_INPUT)
-GPIO(EN_SLP_Z,               PIN(E, 3), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,            PIN(B, 6), GPIO_ODR_LOW)
-GPIO(EC_BL_EN_OD,            PIN(B, 5), GPIO_ODR_LOW | GPIO_SEL_1P8V)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,               PIN(E, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_AP_INT_ODL */
-
-/* USB and USBC Signals */
-GPIO(DP_AUX_PATH_SEL,        PIN(G, 0), GPIO_OUT_HIGH)
-GPIO(EC_DPBRDG_HPD_ODL,      PIN(J, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EN_PP5000_USB_A0_VBUS,  PIN(B, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS_EN,          PIN(H, 3), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,       PIN(C, 0), GPIO_INPUT)
-GPIO(BC12_DET_EN,            PIN(J, 5), GPIO_OUT_LOW) /* EN_USB_C0_BC12_DET */
-GPIO(EN_EC_ID_ODL,           PIN(H, 5), GPIO_ODR_LOW)
-GPIO(ENTERING_RW,            PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
-GPIO(EC_KB_BL_EN,            PIN(G, 3), GPIO_OUT_LOW) /* Keyboard backlight enable */
-GPIO(EN_5V_USM,              PIN(D, 7), GPIO_OUT_LOW)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C_A_SCL,              PIN(B, 3), GPIO_INPUT) /* I2C_CHG_BATT_SCL */
-GPIO(I2C_A_SDA,              PIN(B, 4), GPIO_INPUT) /* I2C_CHG_BATT_SDA */
-GPIO(I2C_B_SCL,              PIN(C, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SCL */
-GPIO(I2C_B_SDA,              PIN(C, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* I2C_SENSOR_SDA */
-GPIO(I2C_C_SCL,              PIN(F, 6), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_C_SDA,              PIN(F, 7), GPIO_INPUT) /* I2C_USB_C0_SCL */
-GPIO(I2C_E_SCL,              PIN(E, 0), GPIO_INPUT) /* I2C_USB_C1_SCL */
-GPIO(I2C_E_SDA,              PIN(E, 7), GPIO_INPUT) /* I2C_USB_C1_SDA */
-
-/* SPI pins - Alternate function below configures SPI module on these pins */
-
-/* NC / TP */
-
-/* Keyboard pins */
-
-/* Subboards HDMI/TYPEC */
-GPIO(EC_X_GPIO1,             PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EC_X_GPIO3,             PIN(J, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A */
-ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C B */
-ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C */
-ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E */
-
-/* UART */
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, 0) /* EC to Servo */
-
-/* ADC */
-ALTERNATE(PIN_MASK(I, 0xEF), 0, MODULE_ADC, 0) /* ADC 0,1,2,3,5,6,7 */
-
-/* SPI */
-ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
-
-/* Unimplemented Pins  */
-GPIO(SET_VMC_VOLT_AT_1V8,    PIN(D, 4), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-GPIO(PACKET_MODE_EN,         PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(UNUSED_GPIOA0,          PIN(A, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOA1,          PIN(A, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOA2,          PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(UNUSED_GPIOF0,          PIN(F, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOJ2,          PIN(J, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOJ3,          PIN(J, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOJ7,          PIN(J, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/* b/160218054: behavior not defined */
-/* *_ODL pin has external pullup so don't pull it down. */
-GPIO(USB_A0_FAULT_ODL,       PIN(A, 7), GPIO_INPUT)
-GPIO(CHARGER_PROCHOT_ODL,    PIN(C, 3), GPIO_INPUT)
-GPIO(PG_MT6315_GPU_ODL,      PIN(H, 6), GPIO_INPUT)
-GPIO(EN_PP3000_SD_U,         PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN | GPIO_SEL_1P8V)
-/* reserved for future use */
-GPIO(CCD_MODE_ODL,           PIN(C, 4), GPIO_INPUT)
-
-/* NC pins, enable internal pull-up/down to avoid floating state. */
-GPIO(NC_GPM2,                PIN(M, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPM3,                PIN(M, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(NC_GPM6,                PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CLK_GPG6,           PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP)
-/*
- * These 3 pins don't have internal pull-down capability,
- * so we set them as output low.
- */
-GPIO(SPI_MOSI_GPG4,          PIN(G, 4), GPIO_OUT_LOW)
-GPIO(SPI_MISO_GPG5,          PIN(G, 5), GPIO_OUT_LOW)
-GPIO(SPI_CS_GPG7,            PIN(G, 7), GPIO_OUT_LOW)
diff --git a/board/spherion/led.c b/board/spherion/led.c
deleted file mode 100644
index aad85d02c1..0000000000
--- a/board/spherion/led.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for Spherion
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-#include "driver/bc12/mt6360.h"
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	mt6360_led_set_brightness(MT6360_LED_RGB1, 50);
-	mt6360_led_set_brightness(MT6360_LED_RGB3, 50);
-
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		mt6360_led_enable(MT6360_LED_RGB1, 1);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	case EC_LED_COLOR_BLUE:
-		mt6360_led_enable(MT6360_LED_RGB1, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 1);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		mt6360_led_enable(MT6360_LED_RGB1, 0);
-		mt6360_led_enable(MT6360_LED_RGB3, 0);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] =
-				MT6360_LED_BRIGHTNESS_MAX;
-		brightness_range[EC_LED_COLOR_BLUE] =
-				MT6360_LED_BRIGHTNESS_MAX;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/spherion/vif_override.xml b/board/spherion/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/spherion/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/staff b/board/staff
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/staff
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/star b/board/star
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/star
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/stern/battery.c b/board/stern/battery.c
deleted file mode 100644
index 50d2bf397c..0000000000
--- a/board/stern/battery.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/stern/board.c b/board/stern/board.c
deleted file mode 100644
index 609dfdf7e5..0000000000
--- a/board/stern/board.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = board_set_active_charge_port(port);
-	if (ret)
-		return ret;
-	force_discharge = enable;
-
-	return charger_discharge_on_ac(enable);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
-
-/* sensor private data */
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSORS,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-		.name = "Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = CONFIG_SPI_ACCEL_PORT,
-		.i2c_spi_addr_flags =
-				ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
diff --git a/board/stern/board.h b/board/stern/board.h
deleted file mode 100644
index 5bf23a6733..0000000000
--- a/board/stern/board.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Kukui */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-/* TODO(b:135086465) led implementation */
-#undef CONFIG_LED_COMMON
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#undef I2C_BITBANG_PORT_COUNT
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_COMMON
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_C235,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger */
-int board_get_charger_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/stern/build.mk b/board/stern/build.mk
deleted file mode 100644
index a6e1c010d7..0000000000
--- a/board/stern/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/stern/ec.tasklist b/board/stern/ec.tasklist
deleted file mode 100644
index 36be2e96a4..0000000000
--- a/board/stern/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, 1024) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/stern/gpio.inc b/board/stern/gpio.inc
deleted file mode 100644
index 3a162d6124..0000000000
--- a/board/stern/gpio.inc
+++ /dev/null
@@ -1,115 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-GPIO_INT(TABLET_MODE_L,     PIN(B, 11), GPIO_INT_BOTH,
-         gmr_tablet_switch_isr)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(PWR_LED_WHITE_L,      EXPIN(0, 1, 4), GPIO_OUT_HIGH)
-IOEX(BAT_LED_WHITE_L,      EXPIN(0, 1, 3), GPIO_OUT_HIGH)
-IOEX(BAT_LED_AMBER_L,      EXPIN(0, 1, 2), GPIO_OUT_HIGH)
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/stern/led.c b/board/stern/led.c
deleted file mode 100644
index ac4813c8c0..0000000000
--- a/board/stern/led.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Damu
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_ON_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_BAT_LED_WHITE_L, LED_OFF_LVL);
-		ioex_set_level(IOEX_BAT_LED_AMBER_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_ON_LVL);
-		break;
-	default:
-		ioex_set_level(IOEX_PWR_LED_WHITE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	} else {
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/stern/vif_override.xml b/board/stern/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/stern/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/stm32f446e-eval/board.c b/board/stm32f446e-eval/board.c
deleted file mode 100644
index fc796464e2..0000000000
--- a/board/stm32f446e-eval/board.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "gpio_list.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "stm32-dma.h"
-#include "usb_descriptor.h"
-#include "usb_dwc_console.h"
-#include "usb_hw.h"
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("stm32f446-eval"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("EC Shell"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-struct dwc_usb usb_ctl = {
-	.ep = {
-		&ep0_ctl,
-		&ep_console_ctl,
-	},
-	.speed = USB_SPEED_FS,
-	.phy_type = USB_PHY_ULPI,
-	.dma_en = 1,
-	.irq = STM32_IRQ_OTG_HS,
-};
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"i2c1", I2C_PORT_0, 100,
-		GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"fmpi2c4", FMPI2C_PORT_3, 100,
-		GPIO_FMPI2C_SCL, GPIO_FMPI2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
-
-void board_config_post_gpio_init(void)
-{
-	/* We use MCO2 clock passthrough to provide a clock to USB HS */
-	gpio_config_module(MODULE_MCO, 1);
-	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C, 9);
-
-	/* Set USB GPIO to high speed */
-	GPIO_SET_HS(A, 11);
-	GPIO_SET_HS(A, 12);
-
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
-
-	GPIO_SET_HS(B,  5);
-	GPIO_SET_HS(B, 13);
-	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
-	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
-
-	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
-}
-
diff --git a/board/stm32f446e-eval/board.h b/board/stm32f446e-eval/board.h
deleted file mode 100644
index aa498d6caa..0000000000
--- a/board/stm32f446e-eval/board.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32F446E-Eval board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Use external clock */
-#define CONFIG_STM32_CLOCK_HSE_HZ 8000000
-
-#define CONFIG_BOARD_POST_GPIO_INIT
-
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* The UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 1
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-#define CONFIG_UART_TX_REQ_CH 4
-#define CONFIG_UART_RX_REQ_CH 4
-
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_0 0
-#define FMPI2C_PORT_3 3
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x500f
-#define CONFIG_USB_CONSOLE
-
-#define CONFIG_USB_SELF_POWERED
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL 0
-#define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_DMA_HELP
-#define CONFIG_FLASH_CROS
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 5
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/stm32f446e-eval/build.mk b/board/stm32f446e-eval/build.mk
deleted file mode 100644
index 6b06f2bb8f..0000000000
--- a/board/stm32f446e-eval/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f446
-
-board-y=board.o
diff --git a/board/stm32f446e-eval/ec.tasklist b/board/stm32f446e-eval/ec.tasklist
deleted file mode 100644
index 2a1ffbf652..0000000000
--- a/board/stm32f446e-eval/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/stm32f446e-eval/gpio.inc b/board/stm32f446e-eval/gpio.inc
deleted file mode 100644
index afc8d1e486..0000000000
--- a/board/stm32f446e-eval/gpio.inc
+++ /dev/null
@@ -1,62 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Outputs */
-GPIO(PD11,			PIN(D, 11), GPIO_OUT_HIGH)
-
-GPIO(I2C1_SCL,			PIN(B, 8), GPIO_INPUT)
-GPIO(I2C1_SDA,			PIN(B, 9), GPIO_INPUT)
-GPIO(FMPI2C_SCL,		PIN(C, 6), GPIO_INPUT)
-GPIO(FMPI2C_SDA,		PIN(C, 7), GPIO_INPUT)
-
-/* USART3 TX/RX */
-GPIO(MCU_UART1_TX,		PIN(A, 9), GPIO_INPUT)
-GPIO(MCU_UART1_RX,		PIN(A, 10), GPIO_INPUT)
-GPIO(MCU_UART3_TX,		PIN(C, 10), GPIO_INPUT)
-GPIO(MCU_UART3_RX,		PIN(C, 11), GPIO_INPUT)
-
-GPIO(USB_FS_DM,			PIN(A, 11), GPIO_INPUT)
-GPIO(USB_FS_DP,			PIN(A, 12), GPIO_INPUT)
-
-
-GPIO(USB_HS_ULPI_NXT,		PIN(C, 3), GPIO_INPUT)
-GPIO(USB_HS_ULPI_DIR,		PIN(C, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_STP,		PIN(C, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_CK,		PIN(A, 5), GPIO_INPUT)
-
-GPIO(USB_HS_ULPI_D7,		PIN(B, 5), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D6,		PIN(B,13), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D5,		PIN(B,12), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D4,		PIN(B, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D3,		PIN(B,10), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D2,		PIN(B, 1), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D1,		PIN(B, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D0,		PIN(A, 3), GPIO_INPUT)
-
-
-
-/* Unimplemented signals since this is a dev board */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART, 0) /* USART1: PA9/PA10 - Console */
-ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART, 0) /* USART3: PC10/PC11 - NOT Console */
-ALTERNATE(PIN_MASK(A, 0x0100), 0, MODULE_MCO, 0) /* MCO1: PA8 */
-ALTERNATE(PIN_MASK(C, 0x0200), 0, MODULE_MCO, 0) /* MCO2: PC9 */
-
-ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C1: PB8-9 */
-ALTERNATE(PIN_MASK(D, 0x3000), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* FMPI2C MASTER:PD12/13 */
-
-ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* DWC USB OTG: PA11/12 */
-
-/* OTG HS */
-ALTERNATE(PIN_MASK(A, 0x0028), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(B, 0x3427), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(C, 0x000d), 10, MODULE_USB, 0) /* DWC USB OTG HS */
diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c
deleted file mode 100644
index c7ebc2c6b8..0000000000
--- a/board/stm32l476g-eval/board.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "i2c.h"
-
-#ifdef CTS_MODULE
-/*
- * Mock interrupt handler. It's supposed to be overwritten by each suite
- * if needed.
- */
-__attribute__((weak)) void cts_irq(enum gpio_signal signal)
-{
-}
-#endif
-
-#include "gpio_list.h"
-
-void tick_event(void)
-{
-	static int count;
-
-	gpio_set_level(GPIO_LED_GREEN, (count & 0x03) == 0);
-
-	count++;
-}
-DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
-
-#ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{"test", STM32_I2C2_PORT, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-#endif
diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h
deleted file mode 100644
index e8ce99845f..0000000000
--- a/board/stm32l476g-eval/board.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32L476G-Eval board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#ifdef CTS_MODULE
-/* CTS tests are small. We can use smaller size to expedite flash time. */
-#undef  CONFIG_FLASH_SIZE_BYTES
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000	/* 256k */
-#endif
-
-/* Optional features */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/* Console is on LPUART (PG7/8). Undef it to use USART1 (PB6/7). */
-#define STM32L476G_EVAL_USE_LPUART_CONSOLE
-#undef CONFIG_UART_CONSOLE
-
-#ifdef STM32L476G_EVAL_USE_LPUART_CONSOLE
-#define CONFIG_UART_CONSOLE 9
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_CH14
-#define CONFIG_UART_TX_DMA_PH 4
-#else
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
-#define CONFIG_UART_TX_DMA_PH 2
-#endif
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-
-#ifdef CTS_MODULE_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_PERIPHERAL
-#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c
-#define I2C_PORT_EC STM32_I2C2_PORT
-#endif
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-
-/* Timer selection */
-#define TIM_CLOCK32	5
-
-/* External clock speeds (8 MHz) */
-#define STM32_HSE_CLOCK 8000000
-
-/* PLL configuration. Freq = STM32_HSE_CLOCK * n/m/r */
-#undef STM32_PLLM
-#define STM32_PLLM	1
-#undef STM32_PLLN
-#define STM32_PLLN	10
-#undef STM32_PLLR
-#define STM32_PLLR	2
-
-#include "gpio_signal.h"
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/stm32l476g-eval/build.mk b/board/stm32l476g-eval/build.mk
deleted file mode 100644
index 23c7cd9d38..0000000000
--- a/board/stm32l476g-eval/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32l4
-CHIP_VARIANT:=stm32l476
-
-board-y=board.o
diff --git a/board/stm32l476g-eval/ec.tasklist b/board/stm32l476g-eval/ec.tasklist
deleted file mode 100644
index adfd7c7e92..0000000000
--- a/board/stm32l476g-eval/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
-
diff --git a/board/stm32l476g-eval/gpio.inc b/board/stm32l476g-eval/gpio.inc
deleted file mode 100644
index 9cf5bc0aa4..0000000000
--- a/board/stm32l476g-eval/gpio.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-#ifdef CTS_MODULE
-#ifndef CTS_MODULE_GPIO
-/* Overload C10 for notification. Enabled only for non-GPIO suites as
- * GPIO tests don't require a separate notification line. */
-GPIO_INT(CTS_NOTIFY, PIN(C, 10), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq)
-#endif
-#endif
-
-/* Outputs */
-GPIO(LED_GREEN,   PIN(B, 2), GPIO_OUT_LOW)
-GPIO(LED_RED,    PIN(C, 1), GPIO_OUT_LOW)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(B, 0xC0), GPIO_ALT_F7, MODULE_UART,  0) /* USART1: PB6/7 */
-ALTERNATE(PIN_MASK(G, 0x0180), GPIO_ALT_F8, MODULE_UART,  0) /* LPUART: PG7/8 */
-
-#ifdef CTS_MODULE
-/* CTS Signals */
-GPIO(HANDSHAKE_OUTPUT, PIN(A, 9), GPIO_ODR_LOW)
-GPIO(HANDSHAKE_INPUT, PIN(A, 8), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(OUTPUT_TEST, PIN(C, 11), GPIO_ODR_LOW)
-GPIO(CTS_IRQ2, PIN(C, 12), GPIO_ODR_LOW)
-#ifdef CTS_MODULE_GPIO
-GPIO(INPUT_TEST, PIN(C, 10), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-GPIO(I2C2_SCL, PIN(B, 10), GPIO_ODR_HIGH) /* I2C port 2 SCL */
-GPIO(I2C2_SDA, PIN(B, 11), GPIO_ODR_HIGH) /* I2C port 2 SDA */
-
-ALTERNATE(PIN_MASK(B, 0x0C00), GPIO_ALT_F4, MODULE_I2C,  GPIO_ODR_HIGH) /* I2C2: PB10/11 */
-#endif
\ No newline at end of file
diff --git a/board/stm32l476g-eval/openocd-flash.cfg b/board/stm32l476g-eval/openocd-flash.cfg
deleted file mode 100644
index a347f88b79..0000000000
--- a/board/stm32l476g-eval/openocd-flash.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-source [find board/stm32l4discovery.cfg]
-
-# For flashing, force the board into reset on connect, this ensures that
-# code running on the core can't interfere with programming.
-reset_config connect_assert_srst
-
-gdb_port 0
-tcl_port 0
-telnet_port 0
-init
-reset init
-flash write_image erase $BUILD_DIR/ec.bin 0x08000000
-reset halt
-resume
-shutdown
diff --git a/board/storo/battery.c b/board/storo/battery.c
deleted file mode 100644
index d273b391e7..0000000000
--- a/board/storo/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all Storo battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* C21N2018 Battery Information */
-	[BATTERY_C21N2018] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXXD3KA",
-			.device_name = "C110160",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000C,
-				.disconnect_val = 0x000C,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0004
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7890, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C21N2018;
diff --git a/board/storo/board.c b/board/storo/board.c
deleted file mode 100644
index 4981bedc8e..0000000000
--- a/board/storo/board.c
+++ /dev/null
@@ -1,897 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Storo configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cros_board_info.h"
-#include "cbi_ssfc.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
-
-	gpio_set_level(GPIO_EN_PP3300_PEN, pen_detect);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-/* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
-
-static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
-{
-	int  rv = EC_SUCCESS;
-	int reg;
-	enum tusb544_conf usb_mode = 0;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			/* USB with DP */
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
-		} else {
-			/* USB without DP */
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
-		}
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* DP without USB */
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
-	} else {
-		return EC_SUCCESS;
-	}
-
-	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			TUSB544_REG_GENERAL6, &reg);
-	if (rv)
-		return rv;
-
-	reg |= TUSB544_VOD_DCGAIN_OVERRIDE;
-	reg &= ~TUSB544_VOD_DCGAIN_SEL;
-	reg |= (TUSB544_VOD_DCGAIN_SETTING_5 << 2);
-
-	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			TUSB544_REG_GENERAL6, reg);
-	if (rv)
-		return rv;
-
-	/* Write the retimer config byte */
-	if (usb_mode == USB_INV) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x15);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
-	} else if (usb_mode == USB) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x11);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
-	} else if (usb_mode == USB_DP_INV) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1F);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
-	} else if (usb_mode == USB_DP) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1B);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
-	} else if (usb_mode == DP_INV) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1E);
-	} else if (usb_mode == DP) {
-		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1A);
-	}
-
-	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x66);
-	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x66);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	else
-		return EC_SUCCESS;
-}
-
-/* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_set,
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	},
-};
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	raa489000_hibernate(CHARGER_PRIMARY, true);
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(CHARGER_SECONDARY, true);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-__override void board_pulse_entering_rw(void)
-{
-	/*
-	 * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin
-	 * which is active high by default.  This causes Cr50 to think that the
-	 * EC has jumped to its RW image even though this may not be the case.
-	 * The pin is changed to GPIO_EC_ENTERING_RW2.
-	 */
-	gpio_set_level(GPIO_EC_ENTERING_RW, 1);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
-	usleep(MSEC);
-	gpio_set_level(GPIO_EC_ENTERING_RW, 0);
-	gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	/* If the port is not changing, we should do nothing */
-	if (old_port == port)
-		return EC_SUCCESS;
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 14;
-
-	*ki = 3;
-	*ki_div = 500;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static const mat33_fp_t lid_lis2dwl_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-struct motion_sensor_t lis2dwl_lid_accel = {
-
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DWL,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dwl_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_lis2dwl_ref,
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-};
-
-static const mat33_fp_t lid_KX022_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static struct kionix_accel_data g_kx022_data;
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	.rot_standard_ref = &lid_KX022_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-static struct icm_drv_data_t g_icm42607_data;
-const mat33_fp_t based_ref_icm42607 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-struct motion_sensor_t icm42607_base_accel = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &based_ref_icm42607,
-	 .min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	 .max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-};
-
-struct motion_sensor_t icm42607_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &based_ref_icm42607,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-void board_init(void)
-{
-	int on;
-	uint32_t board_id;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
-		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable Base Accel interrupt */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable gpio interrupt for pen detect */
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP3300_PEN, 1);
-
-	cbi_get_board_version(&board_id);
-
-	if (board_id > 2) {
-		if (get_cbi_fw_config_tablet_mode()) {
-			if (get_cbi_ssfc_base_sensor() ==
-						SSFC_SENSOR_ICM42607) {
-				motion_sensors[BASE_ACCEL] =
-						icm42607_base_accel;
-				motion_sensors[BASE_GYRO] = icm42607_base_gyro;
-				CPRINTF("BASE GYRO is ICM42607");
-			} else {
-				CPRINTF("BASE GYRO is BMI160");
-			}
-
-			if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LIS2DWL) {
-				motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
-				CPRINTF("LID_ACCEL is LIS2DWL");
-			} else if (get_cbi_ssfc_lid_sensor() ==
-						SSFC_SENSOR_KX022) {
-				motion_sensors[LID_ACCEL] = kx022_lid_accel;
-				CPRINTF("LID_ACCEL is KX022");
-			} else {
-				CPRINTF("LID_ACCEL is BMA253");
-			}
-		} else {
-			motion_sensor_count = 0;
-			gmr_tablet_switch_disable();
-			/*
-			 * Base accel is not stuffed, don't allow
-			 * line to float.
-			 */
-			gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-					GPIO_INPUT | GPIO_PULL_DOWN);
-		}
-	} else {
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) {
-			motion_sensors[BASE_ACCEL] = icm42607_base_accel;
-			motion_sensors[BASE_GYRO] = icm42607_base_gyro;
-			CPRINTF("BASE GYRO is ICM42607");
-		} else {
-			CPRINTF("BASE GYRO is BMI160");
-		}
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LIS2DWL) {
-			motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
-			CPRINTF("LID_ACCEL is LIS2DWL");
-		} else if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			CPRINTF("LID_ACCEL is KX022");
-		} else {
-			CPRINTF("LID_ACCEL is BMA253");
-		}
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM42607:
-			icm42607_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
-}
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/storo/board.h b/board/storo/board.h
deleted file mode 100644
index a89bde6fcf..0000000000
--- a/board/storo/board.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Storo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* EC console commands */
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
-
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_KX022
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_ACCELGYRO_ICM42607
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15*/
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_3,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_C21N2018,
-	BATTERY_TYPE_COUNT,
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/storo/build.mk b/board/storo/build.mk
deleted file mode 100644
index 8167ca9966..0000000000
--- a/board/storo/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/storo/cbi_ssfc.c b/board/storo/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/storo/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/storo/cbi_ssfc.h b/board/storo/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/storo/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/storo/ec.tasklist b/board/storo/ec.tasklist
deleted file mode 100644
index d6fa610141..0000000000
--- a/board/storo/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/storo/gpio.inc b/board/storo/gpio.inc
deleted file mode 100644
index b7541c5259..0000000000
--- a/board/storo/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 	PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(SUB_USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt)
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,		PIN(L, 5), GPIO_ODR_HIGH)
-
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,		PIN(B, 5), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_COLOR_AMBER,		PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(LED_COLOR_WHITE,		PIN(A, 2), GPIO_OUT_HIGH)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC4_NC, PIN(C, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC6_NC, PIN(C, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF0_NC, PIN(F, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF1_NC, PIN(F, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF4_NC, PIN(F, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOF5_NC, PIN(F, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH2_NC, PIN(H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ3_NC, PIN(J, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL0_NC, PIN(L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 EEPROM */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 BATTERY */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V SENSOR */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 SUB_USB_C1 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 USB_C0 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(2)), 0, MODULE_ADC, 0)    /* ADC15:TEMP_SENSOR3 */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
diff --git a/board/storo/led.c b/board/storo/led.c
deleted file mode 100644
index d5094f1f30..0000000000
--- a/board/storo/led.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Storo
- */
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_COLOR_AMBER, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_COLOR_WHITE, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
-
-__override enum led_states board_led_get_state(enum led_states desired_state)
-{
-	/*
-	 * Battery error LED behavior as below:
-	 * S0: Blinking Amber LED, 1s on/ 1s off
-	 * S3/S5: following S3/S5 behavior
-	 * Add function to let battery error LED follow S3/S5 behavior in S3/S5.
-	 */
-
-	if (desired_state == STATE_BATTERY_ERROR) {
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			return desired_state;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			return STATE_DISCHARGE_S3;
-		else
-			return STATE_DISCHARGE_S5;
-	}
-	return desired_state;
-}
diff --git a/board/storo/usb_pd_policy.c b/board/storo/usb_pd_policy.c
deleted file mode 100644
index b0e1098e4d..0000000000
--- a/board/storo/usb_pd_policy.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/storo/vif_override.xml b/board/storo/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/storo/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/stryke/battery.c b/board/stryke/battery.c
deleted file mode 100644
index 0144c049b5..0000000000
--- a/board/stryke/battery.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Stryke battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP LIS Dell FMXMT Battery Information */
-	[BATTERY_SMP_LIS] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-LIS3.78",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7660, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP SDI Dell FMXMT Battery Information */
-	[BATTERY_SMP_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-SDI-3727",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7660, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_SDI;
diff --git a/board/stryke/board.c b/board/stryke/board.c
deleted file mode 100644
index 3275ff7fa9..0000000000
--- a/board/stryke/board.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Stryke board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "spi.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO to enable/disable the USB Type-A port. */
-const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	baseboard_mst_enable_control(MST_HDMI, gpio_get_level(signal));
-}
-
-static void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/******************************************************************************/
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-/* Sensors */
-/* Base Sensor mutex */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-/* Base accel private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* BMA255 private data */
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-/*
- * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
- * matrix can't be tested properly. This needs to be revisited after EVT to make
- * sure the rotaiton matrix for the lid sensor is correct.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma255_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support lid angle calculation. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/* Default */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3100,
-	.rpm_start = 3100,
-	.rpm_max = 6900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
-};
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-
-/* Stryke Temperature sensors */
-/*
- * TODO(b/124316213): These setting need to be reviewed and set appropriately
- * for Stryke. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
- */
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(50),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_a;
-}
-
-/* Sets the gpio flags correct taking into account warm resets */
-static void reset_gpio_flags(enum gpio_signal signal, int flags)
-{
-	/*
-	 * If the system was already on, we cannot set the value otherwise we
-	 * may change the value from the previous image which could cause a
-	 * brownout.
-	 */
-	if (system_is_reboot_warm() || system_jumped_late())
-		flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-	gpio_set_flags(signal, flags);
-}
-
-/* Runtime GPIO defaults */
-enum gpio_signal gpio_en_pp5000_a = GPIO_EN_PP5000_A_V1;
-
-static void board_gpio_set_pp5000(void)
-{
-	uint32_t board_id = 0;
-
-	/* Errors will count as board_id 0 */
-	cbi_get_board_version(&board_id);
-
-	if (board_id == 0) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V0, GPIO_OUT_LOW);
-		/* Change runtime default for V0 */
-		gpio_en_pp5000_a = GPIO_EN_PP5000_A_V0;
-	} else if (board_id >= 1) {
-		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
-	}
-
-}
-
-static void board_init(void)
-{
-	/* Initialize Fans */
-	setup_fans();
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	/* Enable HDMI HPD interrupt. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD);
-	/* Select correct gpio signal for PP5000_A control */
-	board_gpio_set_pp5000();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC_ODL, !is_overcurrented);
-}
-
-bool board_is_convertible(void)
-{
-	const uint8_t sku = get_board_sku();
-
-	return (sku == 255);
-}
diff --git a/board/stryke/board.h b/board/stryke/board.h
deleted file mode 100644
index 4bc1839787..0000000000
--- a/board/stryke/board.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Stryke board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_POWER_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_LED_COMMON
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_HOSTCMD_ESPI
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Keyboard features */
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_COMM_LOCKED
-#define CONFIG_USB_PD_TCPM_ANX7447
-#define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-#define CONFIG_USB_PD_TCPM_PS8751
-#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS
-#define BOARD_TCPC_C1_RESET_POST_DELAY 0
-#define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL
-
-/* USB Type A Features */
-#define CONFIG_USB_PORT_POWER_SMART
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A_LOW_PWR_OD
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger features */
-/*
- * The IDCHG current limit is set in 512 mA steps. The value set here is
- * somewhat specific to the battery pack being currently used. The limit here
- * was set based on the battery's discharge current limit and what was tested to
- * prevent the AP rebooting with low charge level batteries.
- *
- * TODO(b/133447140): Revisit this threshold once peak power consumption tuning
- * for the AP is completed.
- */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
-
-/* Volume Button feature */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
-
-/* Fan features */
-#define CONFIG_FANS 1
-#undef CONFIG_FAN_INIT_SPEED
-#define CONFIG_FAN_INIT_SPEED 50
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_A_RAILS
-#define CONFIG_THERMISTOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* MST */
-/*
- * TDOD (b/124068003): This inherently assumes the MST chip is connected to only
- * one Type C port. This will need to be chagned to support 2 Type C ports
- * connected to the same MST chip.
- */
-#define USB_PD_PORT_TCPC_MST USB_PD_PORT_TCPC_1
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_RSMRST_L_PGOOD	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* GPIO signals updated base on board version. */
-#define GPIO_EN_PP5000_A gpio_en_pp5000_a
-extern enum gpio_signal gpio_en_pp5000_a;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_SMP_LIS,
-	BATTERY_SMP_SDI,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/stryke/build.mk b/board/stryke/build.mk
deleted file mode 100644
index 733912454f..0000000000
--- a/board/stryke/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=hatch
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/stryke/ec.tasklist b/board/stryke/ec.tasklist
deleted file mode 100644
index 4a1024a091..0000000000
--- a/board/stryke/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
-
diff --git a/board/stryke/gpio.inc b/board/stryke/gpio.inc
deleted file mode 100644
index 8b241b2850..0000000000
--- a/board/stryke/gpio.inc
+++ /dev/null
@@ -1,144 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,             PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(WP_L,                 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)              /* EC_WP_ODL */
-GPIO_INT(POWER_BUTTON_L,       PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)        /* MECH_PWR_BTN_ODL */
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD,       PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(BASE_SIXAXIS_INT_L,   PIN(5, 6), GPIO_INT_FALLING, bmi160_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PPC_INT_ODL,   PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,   PIN(A, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,  PIN(6, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,  PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_BC12_INT_ODL,  PIN(9, 5), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,  PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt)
-
-GPIO_INT(HDMI_CONN_HPD,        PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt)
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,     PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,     PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-
-GPIO(SYS_RESET_L,              PIN(C, 5), GPIO_ODR_HIGH)        /* SYS_RST_ODL */
-GPIO(ENTERING_RW,              PIN(E, 3), GPIO_OUT_LOW)         /* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,               PIN(7, 4), GPIO_ODR_HIGH)        /* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,             PIN(C, 1), GPIO_ODR_HIGH)        /* EC_PCH_PWR_BTN_ODL */
-
-/* Power Sequencing Signals */
-GPIO(EN_PP5000_A_V1,           PIN(A, 4), GPIO_DEFAULT)
-GPIO(EN_PP5000_A_V0,           PIN(7, 3), GPIO_DEFAULT)
-GPIO(EN_A_RAILS,               PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_L,          PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_IN_OD,         PIN(3, 4), GPIO_INPUT)
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,                 PIN(7, 0), GPIO_ODR_HIGH)
-
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					               GPIO_HIB_WAKE_HIGH |
-					               GPIO_LOCKED)
-
-/* USB and USBC Signals */
-GPIO(USB_C_OC_ODL,             PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST,          PIN(9, 7), GPIO_OUT_LOW)
-GPIO(USB_C1_TCPC_RST_ODL,      PIN(3, 2), GPIO_ODR_HIGH)
-GPIO(EN_USB_A_5V,              PIN(3, 5), GPIO_OUT_LOW)
-GPIO(EN_USB_A_LOW_PWR_OD,      PIN(9, 4), GPIO_OUT_LOW)
-
-/* Misc Signals */
-GPIO(EC_BATT_PRES_ODL,         PIN(E, 1), GPIO_INPUT)
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Yellow (hatch) */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* White (hatch) */
-GPIO(LED_3_L,                  PIN(C, 2), GPIO_OUT_HIGH)
-GPIO(LED_4_L,                  PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(EC_KB_BL_EN,              PIN(8, 6), GPIO_OUT_LOW)         /* Keyboard backlight */
-GPIO(EDP_BKLTEN_OD,            PIN(D, 3), GPIO_ODR_HIGH)        /* Display backlight */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_MST,                   PIN(9, 6), GPIO_OUT_LOW)
-
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,                 PIN(B, 5), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SCL */
-GPIO(I2C0_SDA,                 PIN(B, 4), GPIO_INPUT |
-                                          GPIO_SEL_1P8V)        /* EC_I2C_SENSOR_1V8_SDA */
-GPIO(I2C1_SCL,                 PIN(9, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,                 PIN(8, 7), GPIO_INPUT)           /* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,                 PIN(9, 2), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,                 PIN(9, 1), GPIO_INPUT)           /* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,                 PIN(D, 1), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SDA */
-GPIO(I2C3_SDA,                 PIN(D, 0), GPIO_INPUT)           /* EC_I2C_USB_C0_TCPC_SCL */
-GPIO(I2C5_SCL,                 PIN(3, 3), GPIO_INPUT)           /* EC_I2C_POWER_SCL */
-GPIO(I2C5_SDA,                 PIN(3, 6), GPIO_INPUT)           /* EC_I2C_POWER_SDA */
-GPIO(I2C7_SCL,                 PIN(B, 3), GPIO_INPUT)           /* EC_I2C_EEPROM_SCL */
-GPIO(I2C7_SDA,                 PIN(B, 2), GPIO_INPUT)           /* EC_I2C_EEPROM_SDA */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-GPIO(KBD_KSO2,                 PIN(1, 7), GPIO_OUT_LOW)        /* KSO_02 inverted */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)       /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)       /* KSO_14 */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))  /* I2C0 1.8V */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)                             /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)                             /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)                             /* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)                             /* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)                             /* I2C7 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)                            /* UART from EC to Servo */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)                             /* PWM3 - Keyboard backlight */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)                             /* PWM5 - FAN */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)                             /* TA1 - Fan Tachometer */
-
-/* ADC */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)                             /* ADC0-1 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)                             /* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)                             /* GPIO00 = ACOK_OD,
-                                                                              GPIO01 = MECH_PWR_BTN_ODL
-                                                                              GPIO02 = EC_RST_ODL */
diff --git a/board/stryke/led.c b/board/stryke/led.c
deleted file mode 100644
index f68b39361e..0000000000
--- a/board/stryke/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Stryke
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/stryke/vif_override.xml b/board/stryke/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/stryke/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/sweetberry/board.c b/board/sweetberry/board.c
deleted file mode 100644
index 66b21a81b9..0000000000
--- a/board/sweetberry/board.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Sweetberry board configuration */
-
-#include "common.h"
-#include "dma.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "gpio_list.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "update_fw.h"
-#include "usb_descriptor.h"
-#include "usb_dwc_console.h"
-#include "usb_dwc_i2c.h"
-#include "usb_dwc_stream.h"
-#include "usb_dwc_update.h"
-#include "usb_hw.h"
-#include "usb_power.h"
-#include "util.h"
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Sweetberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]	= USB_STRING_DESC("I2C"),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Sweetberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/* USB power interface. */
-USB_POWER_CONFIG(sweetberry_power, USB_IFACE_POWER, USB_EP_POWER);
-
-struct dwc_usb usb_ctl = {
-	.ep = {
-		&ep0_ctl,
-		&ep_console_ctl,
-		&usb_update_ep_ctl,
-		&sweetberry_power_ep_ctl,
-		&i2c_usb__ep_ctl,
-	},
-	.speed = USB_SPEED_FS,
-	.phy_type = USB_PHY_ULPI,
-	.dma_en = 1,
-	.irq = STM32_IRQ_OTG_HS,
-};
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"i2c1", I2C_PORT_0, 400,
-		GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"i2c2", I2C_PORT_1, 400,
-		GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"i2c3", I2C_PORT_2, 400,
-		GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"fmpi2c4", FMPI2C_PORT_3, 900,
-		GPIO_FMPI2C_SCL, GPIO_FMPI2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
-
-void board_config_post_gpio_init(void)
-{
-	/* We use MCO2 clock passthrough to provide a clock to USB HS */
-	gpio_config_module(MODULE_MCO, 1);
-	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
-
-	if (usb_ctl.phy_type == USB_PHY_ULPI)
-		gpio_set_level(GPIO_USB_MUX_SEL, 0);
-	else
-		gpio_set_level(GPIO_USB_MUX_SEL, 1);
-
-	/* Set USB GPIO to high speed */
-	GPIO_SET_HS(A, 11);
-	GPIO_SET_HS(A, 12);
-
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
-
-	GPIO_SET_HS(B,  5);
-	GPIO_SET_HS(B, 13);
-	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
-	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
-
-	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
-}
-
-static void board_init(void)
-{
-	uint8_t tmp;
-
-	/* i2c 0 has a tendancy to get wedged. TODO(nsanders): why? */
-	i2c_xfer(0, 0, NULL, 0, &tmp, 1);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/sweetberry/board.h b/board/sweetberry/board.h
deleted file mode 100644
index 55aab7d1ee..0000000000
--- a/board/sweetberry/board.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Sweetberry configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_LTO
-
-/* Use external clock */
-#define CONFIG_STM32_CLOCK_HSE_HZ 24000000
-
-#define CONFIG_BOARD_POST_GPIO_INIT
-
-#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* The UART console can be on flex USART3 (PC10/PC11) */
-/* The UART console can be on header USART4 (PA0/PA1) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 4
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-/* Don't waste precious DMA channels on console. */
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-#define CONFIG_UART_TX_REQ_CH 4
-#define CONFIG_UART_RX_REQ_CH 4
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x5020
-#define CONFIG_USB_CONSOLE
-#define CONFIG_STREAM_USB
-#define CONFIG_USB_UPDATE
-#define CONFIG_USB_POWER
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 100
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_POWER		2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_POWER		3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
-
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_0	0
-#define I2C_PORT_1	1
-#define I2C_PORT_2	2
-#define FMPI2C_PORT_3	3
-#define I2C_PORT_COUNT	4
-
-/* This is not actually a Chromium EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 5
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_UPDATE_NAME,
-	USB_STR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/sweetberry/build.mk b/board/sweetberry/build.mk
deleted file mode 100644
index 6b06f2bb8f..0000000000
--- a/board/sweetberry/build.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-CHIP:=stm32
-CHIP_FAMILY:=stm32f4
-CHIP_VARIANT:=stm32f446
-
-board-y=board.o
diff --git a/board/sweetberry/ec.tasklist b/board/sweetberry/ec.tasklist
deleted file mode 100644
index c1fb169118..0000000000
--- a/board/sweetberry/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/sweetberry/gpio.inc b/board/sweetberry/gpio.inc
deleted file mode 100644
index cfab7fc1f3..0000000000
--- a/board/sweetberry/gpio.inc
+++ /dev/null
@@ -1,94 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Outputs */
-GPIO(MUX_EN_L,			PIN(A, 7),  GPIO_INPUT)
-GPIO(USB_MUX_SEL,		PIN(A, 6),  GPIO_OUT_HIGH)
-GPIO(PHY_RESET,			PIN(C, 4),  GPIO_INPUT)
-GPIO(LED_BLUE,			PIN(A, 2),  GPIO_ODR_LOW)
-GPIO(LED_GRN,			PIN(B, 8),  GPIO_ODR_LOW)
-GPIO(LED_RED,			PIN(B, 15), GPIO_ODR_LOW)
-
-/* Inputs */
-GPIO(GPIO_1,  			PIN(A, 1), GPIO_INPUT)
-GPIO(GPIO_2,  			PIN(A, 0), GPIO_INPUT)
-
-/* Clock function */
-GPIO(MCU_TO_PHY_MCO,		PIN(C, 9), GPIO_INPUT)
-
-
-/* GPIO to DUT */
-GPIO(DUT_XTAL_STATUS_3V3,	PIN(D, 8), GPIO_INPUT)
-GPIO(DUT_TO_MCU_1_3V3,		PIN(D, 9), GPIO_INPUT)
-GPIO(DUT_TO_MCU_2_3V3,		PIN(D, 10), GPIO_INPUT)
-GPIO(MCU_TO_DUT_INT_3V3,	PIN(D, 12), GPIO_INPUT)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(I2C1_SCL,			PIN(B, 6), GPIO_INPUT)
-GPIO(I2C1_SDA,			PIN(B, 7), GPIO_INPUT)
-GPIO(I2C2_SCL,			PIN(F, 1), GPIO_INPUT)
-GPIO(I2C2_SDA,			PIN(F, 0), GPIO_INPUT)
-GPIO(I2C3_SCL,			PIN(A, 8), GPIO_INPUT)
-GPIO(I2C3_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(FMPI2C_SCL,		PIN(C, 6), GPIO_INPUT)
-GPIO(FMPI2C_SDA,		PIN(C, 7), GPIO_INPUT)
-
-/* These pin assignments aren't used as GPIO. Let's note them here
- * for readability but not initialize them.
- * USART3 TX/RX
- * GPIO(MCU_UART3_TX,		PIN(C, 10), GPIO_INPUT)
- * GPIO(MCU_UART3_RX,		PIN(C, 11), GPIO_INPUT)
- * USART4 TX/RX
- * GPIO(MCU_UART4_TX,		PIN(A, 0), GPIO_INPUT)
- * GPIO(MCU_UART4_RX,		PIN(A, 1), GPIO_INPUT)
- */
-
-/* USB pins */
-GPIO(USB_FS_DM,			PIN(A, 11), GPIO_INPUT)
-GPIO(USB_FS_DP,			PIN(A, 12), GPIO_INPUT)
-
-GPIO(USB_HS_ULPI_NXT,		PIN(C, 3), GPIO_INPUT)
-GPIO(USB_HS_ULPI_DIR,		PIN(C, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_STP,		PIN(C, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_CK,		PIN(A, 5), GPIO_INPUT)
-
-GPIO(USB_HS_ULPI_D7,		PIN(B, 5), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D6,		PIN(B,13), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D5,		PIN(B,12), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D4,		PIN(B, 2), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D3,		PIN(B,10), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D2,		PIN(B, 1), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D1,		PIN(B, 0), GPIO_INPUT)
-GPIO(USB_HS_ULPI_D0,		PIN(A, 3), GPIO_INPUT)
-
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-
-ALTERNATE(PIN_MASK(C, 0x0c00), 7, MODULE_UART, 0) /* USART3: PC10/PC11 - Console */
-ALTERNATE(PIN_MASK(A, 0x0003), 8, MODULE_UART, 0) /* USART4: PA0/PA1 - Console */
-
-ALTERNATE(PIN_MASK(B, 0x00c0), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C1 MASTER:PB6/7 */
-ALTERNATE(PIN_MASK(F, 0x0003), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C2 MASTER:PF1/0 */
-ALTERNATE(PIN_MASK(A, 0x0100), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C3 MASTER:PA8 */
-ALTERNATE(PIN_MASK(B, 0x0010), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C3 MASTER:PB4 */
-ALTERNATE(PIN_MASK(C, 0x00c0), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* FMPI2C MASTER:PC6/7 */
-
-/* OTG FS */
-ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* DWC USB OTG: PA11/12 */
-
-/* OTG HS */
-ALTERNATE(PIN_MASK(A, 0x0028), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(B, 0x3427), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(C, 0x000d), 10, MODULE_USB, 0) /* DWC USB OTG HS */
-ALTERNATE(PIN_MASK(C, 0x0200), 0, MODULE_MCO, 0) /* MCO2: PC9 */
diff --git a/board/taeko/battery.c b/board/taeko/battery.c
deleted file mode 100644
index 09f9ec46c7..0000000000
--- a/board/taeko/battery.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-/*
- * Battery info for all Taeko battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L21M4PG4",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8900, /* mV */
-			.voltage_normal		= 7720, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 330,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L21D4PG4",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8900, /* mV */
-			.voltage_normal		= 7720, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 330,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
-
-__override bool board_battery_is_initialized(void)
-{
-	bool batt_initialization_state;
-	int batt_status;
-
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
-	return batt_initialization_state;
-}
diff --git a/board/taeko/board.c b/board/taeko/board.c
deleted file mode 100644
index d7fe4e4399..0000000000
--- a/board/taeko/board.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "button.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "driver/als_tcs3400.h"
-#include "fw_config.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "registers.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "usbc_config.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA_R,
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
-
-/******************************************************************************/
-
-__override void board_cbi_init(void)
-{
-	config_usb_db_type();
-}
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-
-	if (ec_cfg_has_keyboard_backlight() == 1)
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-	else
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-
-	if (ec_cfg_has_keyboard_backlight() == 1)
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
-	else
-		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-
-/*
- * TODO: tune this threshold
- */
-
-#define BC12_MIN_VOLTAGE 4400
-
-/**
- * Return true if VBUS is too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage;
-
-	if (charger_get_vbus_voltage(port, &voltage))
-		voltage = 0;
-
-	if (voltage == 0) {
-		CPRINTS("%s: must be disconnected", __func__);
-		return 1;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
-		return 1;
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_CHARGE_RAMP_SW */
-
-enum battery_present battery_hw_present(void)
-{
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/taeko/board.h b/board/taeko/board.h
deleted file mode 100644
index 7b7995f001..0000000000
--- a/board/taeko/board.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Taeko board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/*
- * Taeko boards are set up for vivaldi
- */
-#define CONFIG_KEYBOARD_VIVALDI
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * This will happen automatically on NPCX9 ES2 and later. Do not remove
- * until we can confirm all earlier chips are out of service.
- */
-#define CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-
-#define CONFIG_MP2964
-
-/* LED */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Sensors */
-
-/* TODO(b/194765820)
- * Check if project support dynamic motion sensor count
- */
-/* #define	CONFIG_DYNAMIC_MOTION_SENSOR_COUNT */
-
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
-#define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
-
-/* Lid accel */
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-#define CONFIG_ACCEL_BMA4XX
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Sensor console commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		1
-
-#define CONFIG_USB_PD_TCPM_PS8815
-
-#define CONFIG_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_NX20P3483
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* Fan */
-#define CONFIG_FANS			FAN_CH_COUNT
-
-/* Charger defines */
-#define CONFIG_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_FAN,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_CPUCHOKE,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_FAN,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_CPUCHOKE,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_COUNT
-};
-
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/taeko/build.mk b/board/taeko/build.mk
deleted file mode 100644
index 442d30718f..0000000000
--- a/board/taeko/build.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Taeko board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
-
-board-y=
-board-y+=battery.o
-board-y+=board.o
-board-y+=charger.o
-board-y+=fans.o
-board-y+=fw_config.o
-board-y+=i2c.o
-board-y+=keyboard.o
-board-y+=led.o
-board-y+=pwm.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/taeko/charger.c b/board/taeko/charger.c
deleted file mode 120000
index 476ce97df2..0000000000
--- a/board/taeko/charger.c
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
diff --git a/board/taeko/ec.tasklist b/board/taeko/ec.tasklist
deleted file mode 100644
index 290c17c748..0000000000
--- a/board/taeko/ec.tasklist
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/taeko/fans.c b/board/taeko/fans.c
deleted file mode 100644
index e6273ec210..0000000000
--- a/board/taeko/fans.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-static const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * TOOD(b/194774929): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/194774929): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 100;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/taeko/fw_config.c b/board/taeko/fw_config.c
deleted file mode 100644
index 4e450b7dfa..0000000000
--- a/board/taeko/fw_config.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static union taeko_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for Taeko if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union taeko_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PS8815,
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Taeko FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
-}
-
-union taeko_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
-
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void)
-{
-	return fw_config.usb_db;
-}
-
-bool ec_cfg_has_keyboard_backlight(void)
-{
-	return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED);
-}
diff --git a/board/taeko/fw_config.h b/board/taeko/fw_config.h
deleted file mode 100644
index db4c6d60c0..0000000000
--- a/board/taeko/fw_config.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_TAEKO_FW_CONFIG_H_
-#define __BOARD_TAEKO_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/****************************************************************************
- * CBI FW_CONFIG layout for Taeko board.
- *
- * Source of truth is the project/taeko/taeko/config.star configuration file.
- */
-
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1,
-	DB_USB_ABSENT2 = 15
-};
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union taeko_cbi_fw_config {
-	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union taeko_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-/**
- * Check if the FW_CONFIG has enabled keyboard backlight.
- *
- * @return true if board supports keyboard backlight, false if the board
- * doesn't support it.
- */
-bool ec_cfg_has_keyboard_backlight(void);
-
-#endif /* __BOARD_TAEKO_FW_CONFIG_H_ */
diff --git a/board/taeko/gpio.inc b/board/taeko/gpio.inc
deleted file mode 100644
index 7e97007af6..0000000000
--- a/board/taeko/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C0_TCPC_INT_ODL,            PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,            PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,            PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_VAP_OTG_EN,             PIN(7, 3), GPIO_OUT_LOW)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(D, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_PPC_BC_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PPC_BC_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SCL,         PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_TCPC_SDA,         PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
-GPIO(EC_KB_BL_EN_L,                  PIN(8, 6), GPIO_OUT_HIGH)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO14/GPIO82 */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* Unused Pins */
-UNUSED(PIN(B, 1))       /* KSO17/GPIOB1/CR_SIN4 */
-UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-/* GPIO02_P2 to PU */
-/* GPIO03_P2 to PU */
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-
-/* LED */
-GPIO(LED_1_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* Battery - Red LED */
-GPIO(LED_2_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* Battery - Green LED */
-GPIO(LED_3_L,	 PIN(C, 2), GPIO_OUT_HIGH)	/* Power - White LED */
diff --git a/board/taeko/i2c.c b/board/taeko/i2c.c
deleted file mode 100644
index 0a32a502ab..0000000000
--- a/board/taeko/i2c.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0",
-		.port = I2C_PORT_USB_C0_TCPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0",
-		.port = I2C_PORT_USB_C0_PPC,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C_USB_C0_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_PPC_BC_SDA,
-	},
-	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "ppc1",
-		.port = I2C_PORT_USB_C1_PPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/taeko/keyboard.c b/board/taeko/keyboard.c
deleted file mode 100644
index a9f033130d..0000000000
--- a/board/taeko/keyboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/taeko/led.c b/board/taeko/led.c
deleted file mode 100644
index 35d4fe4146..0000000000
--- a/board/taeko/led.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Taeko specific PWM LED settings: there are 2 LEDs on each side of the board,
- * each one can be controlled separately. The LED colors are white or amber,
- * and the default behavior is tied to the charging process: both sides are
- * amber while charging the battery and white when the battery is charged.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/taeko/pwm.c b/board/taeko/pwm.c
deleted file mode 100644
index b5fef384f9..0000000000
--- a/board/taeko/pwm.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/taeko/sensors.c b/board/taeko/sensors.c
deleted file mode 100644
index 0d4c85f0df..0000000000
--- a/board/taeko/sensors.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "adc_chip.h"
-#include "driver/accel_bma422.h"
-#include "driver/accel_bma4xx.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dso.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "motion_sense.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "temp_sensor/thermistor.h"
-
-#if 0
-#define CPRINTS(format, args...) ccprints(format, ## args)
-#define CPRINTF(format, args...) ccprintf(format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-/* ADC configuration */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_FAN] = {
-		.name = "TEMP_FAN",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_CPUCHOKE] = {
-		.name = "CPU_CHOKE",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_accel_mutex);
-static struct stprivate_data g_lis2dw12_data;
-static struct lsm6dso_data lsm6dso_data;
-static struct accelgyro_saved_data_t g_bma422_data;
-
-/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-
-struct motion_sensor_t bma422_lid_accel = {
-	.name = "Lid Accel - BMA",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA422,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma4_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_bma422_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY, /* 0x18 */
-	.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-	.default_range = 2, /* g, enough for laptop. */
-	.min_frequency = BMA4_ACCEL_MIN_FREQ,
-	.max_frequency = BMA4_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel - ST",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DW12,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dw12_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_lis2dw12_data,
-		.int_signal = GPIO_EC_ACCEL_INT_R_L,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DW12_ADDR1, /* 0x19 */
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.rot_standard_ref = &lid_standard_ref, /* identity matrix */
-		.default_range = 2, /* g */
-		.min_frequency = LIS2DW12_ODR_MIN_VAL,
-		.max_frequency = LIS2DW12_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 12500 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &lsm6dso_data,
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSO,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dso_drv,
-		.mutex = &g_base_accel_mutex,
-		.drv_data = &lsm6dso_data,
-		.int_signal = GPIO_EC_IMU_INT_R_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSO_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSO_ODR_MIN_VAL,
-		.max_frequency = LSM6DSO_ODR_MAX_VAL,
-	},
-
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int ret;
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	/*
-	 * TODO:b/194765820 - Dynamic motion sensor count
-	 * Clamshell un-support motion sensor.
-	 * We should ignore to detect motion sensor for clamshell.
-	 * List this TODO item until we know how to identify DUT type.
-	 */
-
-	/* Check lid accel chip */
-	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1,
-			LIS2DW12_WHO_AM_I_REG, &val);
-	if (ret == 0 && val == LIS2DW12_WHO_AM_I) {
-		CPRINTS("LID_ACCEL is IS2DW12");
-		/* Enable gpio interrupt for lid accel sensor */
-		gpio_enable_interrupt(GPIO_EC_ACCEL_INT_R_L);
-		return;
-	}
-
-	ret = i2c_read8(I2C_PORT_SENSOR, BMA4_I2C_ADDR_PRIMARY,
-			BMA4_CHIP_ID_ADDR, &val);
-	if (ret == 0 && val == BMA422_CHIP_ID) {
-		CPRINTS("LID_ACCEL is BMA422");
-		motion_sensors[LID_ACCEL] = bma422_lid_accel;
-		/*
-		 * The driver for BMA422 doesn't have code to support
-		 * INT1. So, it doesn't need to enable interrupt.
-		 * Vendor recommend to configure EC gpio as high-z if
-		 * we don't use INT1. Keep this pin as input w/o enable
-		 * interrupt.
-		 */
-		return;
-	}
-
-	/* Lid accel is not stuffed, don't allow line to float */
-	gpio_disable_interrupt(GPIO_EC_ACCEL_INT_R_L);
-	gpio_set_flags(GPIO_EC_ACCEL_INT_R_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	CPRINTS("No LID_ACCEL");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-		HOOK_PRIO_DEFAULT);
-
-
-static void baseboard_sensors_init(void)
-{
-	CPRINTS("baseboard_sensors_init");
-	/*
-	 * GPIO_EC_ACCEL_INT_R_L
-	 * The interrupt of lid accel is disabled by default.
-	 * We'll enable it later if lid accel is LIS2DW12.
-	 */
-
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (motion_sensors[LID_ACCEL].chip == MOTIONSENSE_CHIP_LIS2DW12) {
-		lis2dw12_interrupt(signal);
-		CPRINTS("IS2DW12 interrupt");
-		return;
-	}
-
-	/*
-	 * From other project, ex. guybrush, it seem BMA422 doesn't have
-	 * interrupt handler when EC_ACCEL_INT_R_L is asserted.
-	 * However, I don't see BMA422 assert EC_ACCEL_INT_R_L when it has
-	 * power. That could be the reason EC code doesn't register any
-	 * interrupt handler.
-	 */
-	CPRINTS("BMA422 interrupt");
-
-}
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_CPUCHOKE] = {
-		.name = "CPU CHOKE",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_CPUCHOKE
-	},
-};
-
-
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-static const struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-static const struct ec_thermal_config thermal_fan = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-/* this should really be "const" */
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_FAN]	= thermal_fan,
-	[TEMP_SENSOR_3_CHARGER]	= thermal_fan,
-	[TEMP_SENSOR_4_CPUCHOKE] = thermal_fan,
-};
-
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/taeko/usbc_config.c b/board/taeko/usbc_config.c
deleted file mode 100644
index 993b10c99f..0000000000
--- a/board/taeko/usbc_config.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "ec_commands.h"
-#include "fw_config.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		/* Compatible with Silicon Mitus SM536A0 */
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set
- * to the virtual_usb_mux_driver so the AP gets notified of mux changes
- * and updates the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C2 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-void config_usb_db_type(void)
-{
-	enum ec_cfg_usb_db_type db_type = ec_cfg_usb_db_type();
-
-	/*
-	 * TODO(b/194515356): implement multiple DB types
-	 */
-
-	CPRINTS("Configured USB DB type number is %d", db_type);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b/194618663): figure out correct timing
-	 */
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late()) {
-		board_reset_pd_mcu();
-
-		/*
-		 * These IO expander pins are implemented using the
-		 * C0/C2 TCPC, so they must be set up after the TCPC has
-		 * been taken out of reset.
-		 */
-		ioex_config[0].flags &= ~IOEX_FLAGS_DISABLED;
-		ioex_init(0);
-	}
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
-
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
diff --git a/board/taeko/usbc_config.h b/board/taeko/usbc_config.h
deleted file mode 100644
index 89fb1863c8..0000000000
--- a/board/taeko/usbc_config.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Taeko board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void config_usb_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
-
diff --git a/board/taeko/vif_override.xml b/board/taeko/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/taeko/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/terrador/battery.c b/board/terrador/battery.c
deleted file mode 100644
index d129ede528..0000000000
--- a/board/terrador/battery.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/terrador/board.c b/board/terrador/board.c
deleted file mode 100644
index 5adc65fc70..0000000000
--- a/board/terrador/board.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/als_tcs3400.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Terrador if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_RED] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_GREEN] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025015): Terrador: check USB PD reset operation */
-}
-
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-};
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration.
- */
-static void setup_mux(void)
-{
-	CPRINTS("C0 supports bb-retimer");
-	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
-}
-
-__override void board_cbi_init(void)
-{
-	/*
-	 * TODO(b/159025015): Terrador: check FW_CONFIG fields for USB DB type
-	 */
-	setup_mux();
-	/* Reassign USB_C0_RT_RST_ODL */
-	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
-	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
diff --git a/board/terrador/board.h b/board/terrador/board.h
deleted file mode 100644
index 90e13a45aa..0000000000
--- a/board/terrador/board.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_RED,
-	PWM_CH_LED3_GREEN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/terrador/build.mk b/board/terrador/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/terrador/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/terrador/ec.tasklist b/board/terrador/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/terrador/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/terrador/gpio.inc b/board/terrador/gpio.inc
deleted file mode 100644
index 3ec22924f9..0000000000
--- a/board/terrador/gpio.inc
+++ /dev/null
@@ -1,172 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C0_RT_INT_ODL,			PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,			PIN(4, 0), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/terrador/led.c b/board/terrador/led.c
deleted file mode 100644
index 640312bd64..0000000000
--- a/board/terrador/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map[] = {
-				/* Green, Red, Blue */
-	[EC_LED_COLOR_GREEN] =  {    100,   0,    0 },
-	[EC_LED_COLOR_RED] =    {      0, 100,    0 },
-	[EC_LED_COLOR_BLUE] =   {      0,   0,  100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {     70, 100,    0 },
-	[EC_LED_COLOR_WHITE] =  {     70, 100,  100 },
-	[EC_LED_COLOR_AMBER] =  {     20, 100,    0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_GREEN,
-		.ch1 = PWM_CH_LED2_RED,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/terrador/sensors.c b/board/terrador/sensors.c
deleted file mode 100644
index 9997591cb6..0000000000
--- a/board/terrador/sensors.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/terrador/vif_override.xml b/board/terrador/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/terrador/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/tglrvp_ish/board.c b/board/tglrvp_ish/board.c
deleted file mode 100644
index a0584410b3..0000000000
--- a/board/tglrvp_ish/board.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TGL RVP ISH board-specific configuration */
-
-#include "accelgyro_lsm6dsm.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "task.h"
-
-#include "gpio_list.h" /* has to be included last */
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Sensor config */
-static struct mutex g_base_mutex;
-/* sensor private data */
-static struct lsm6dsm_data lsm6dsm_a_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_LSM6DS3,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_a_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR1_FLAGS,
-		.rot_standard_ref = NULL, /* TODO rotate correctly */
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-int chipset_in_state(int state_mask)
-{
-	return state_mask & CHIPSET_STATE_ON;
-}
-
-int chipset_in_or_transitioning_to_state(int state_mask)
-{
-	return state_mask & CHIPSET_STATE_ON;
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-}
-
-int board_idle_task(void *unused)
-{
-	while (1)
-		task_wait_event(-1);
-}
diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h
deleted file mode 100644
index 03044a5bb8..0000000000
--- a/board/tglrvp_ish/board.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TGL RVP ISH board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Don't use this on production systems.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * By default, enable all console messages except HC, ACPI and event
- * The sensor stack is generating a lot of activity.
- */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
-#define CONFIG_CLOCK_CRYSTAL
-#define CONFIG_ISH_UART_0
-/* EC */
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_ACCELGYRO_LSM6DSM	/* For LSM6DS3 */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(BASE_ACCEL)
-
-/* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
-
-/* I2C ports */
-#define I2C_PORT_SENSOR ISH_I2C1
-#define CONFIG_CMD_I2C_XFER
-
-/* EC Console Commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_TIMERINFO
-
-/* Undefined features */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_KEYBOARD
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_EXTPOWER
-#undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FMAP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_TEMP_SENSOR
-#undef CONFIG_ADC
-#undef CONFIG_SHA256
-
-/* DMA paging between SRAM and DRAM */
-#define CONFIG_DMA_PAGING
-
-/* power management definitions */
-#define CONFIG_LOW_POWER_IDLE
-
-#define CONFIG_ISH_PM_D0I1
-#define CONFIG_ISH_PM_D0I2
-#define CONFIG_ISH_PM_D0I3
-#define CONFIG_ISH_PM_D3
-#define CONFIG_ISH_PM_RESET_PREP
-
-#define CONFIG_ISH_IPAPG
-
-#define CONFIG_ISH_D0I2_MIN_USEC	(15*MSEC)
-#define CONFIG_ISH_D0I3_MIN_USEC	(50*MSEC)
-
-#define CONFIG_ISH_NEW_PM
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Motion sensors */
-enum sensor_id {
-	BASE_ACCEL,
-	SENSOR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/tglrvp_ish/build.mk b/board/tglrvp_ish/build.mk
deleted file mode 100644
index 74ec3c865f..0000000000
--- a/board/tglrvp_ish/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=ish
-CHIP_FAMILY:=ish5
-CHIP_VARIANT:=ish5p4
-
-board-y=board.o
diff --git a/board/tglrvp_ish/ec.tasklist b/board/tglrvp_ish/ec.tasklist
deleted file mode 100644
index a4db486e9a..0000000000
--- a/board/tglrvp_ish/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_NOTEST(CHIPSET, board_idle_task, NULL, IDLE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(HECI_RX, heci_rx_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(IPC_MNG, ipc_mng_task, NULL, LARGER_TASK_STACK_SIZE, 0)
diff --git a/board/tglrvp_ish/gpio.inc b/board/tglrvp_ish/gpio.inc
deleted file mode 100644
index 286309e388..0000000000
--- a/board/tglrvp_ish/gpio.inc
+++ /dev/null
@@ -1,12 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * We don't have a ENTERING_RW signal wired to the cr50 but common code needs
- * it to be defined.
- */
-UNIMPLEMENTED(ENTERING_RW)
diff --git a/board/tglrvpu_ite/battery.c b/board/tglrvpu_ite/battery.c
deleted file mode 100644
index d529f7677e..0000000000
--- a/board/tglrvpu_ite/battery.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "util.h"
-
-const struct board_batt_params board_battery_info[] = {
-	/*
-	 * Simplo Battery (SMP-HHP-408) Information
-	 * Fuel gauge: BQ40Z50
-	 */
-	[BATTERY_SIMPLO_SMP_HHP_408] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-HHP-408",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,        /* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 204,   /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = 0,
-			.discharging_max_c = 60,
-		},
-	},
-	/*
-	 * Simplo Battery (SMP-CA-445) Information
-	 * Fuel gauge: BQ30Z554
-	 */
-	[BATTERY_SIMPLO_SMP_CA_445] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP-CA-445",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = SB_BATTERY_STATUS,
-				.reg_mask = STATUS_INITIALIZED,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max = 8700,		/* mV */
-			.voltage_normal = 7600,
-			.voltage_min = 6100,
-			.precharge_current = 150,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -20,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SMP_HHP_408;
diff --git a/board/tglrvpu_ite/board.c b/board/tglrvpu_ite/board.c
deleted file mode 100644
index 4c96576b28..0000000000
--- a/board/tglrvpu_ite/board.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-#include "button.h"
-#include "charger.h"
-#include "driver/charger/isl9241.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/icelake.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#include "gpio_list.h"
-
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-
-/* Mutex for shared NVM access */
-static struct mutex bb_nvm_mutex;
-
-/* TCPC gpios */
-const struct tcpc_gpio_config_t tcpc_gpios[] = {
-	[TYPE_C_PORT_0] = {
-		.vbus = {
-			.pin = GPIO_USB_C0_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C0_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C0_SNK_EN_L,
-			.pin_pol = 0,
-		},
-		.vconn = {
-			.cc1_pin = GPIO_USB_C0_CC1_VCONN_EN,
-			.cc2_pin = GPIO_USB_C0_CC2_VCONN_EN,
-			.pin_pol = 1,
-		},
-		.src_ilim = {
-			.pin = GPIO_USB_C0_SRC_HI_ILIM,
-			.pin_pol = 1,
-		},
-	},
-	[TYPE_C_PORT_1] = {
-		.vbus = {
-			.pin = GPIO_USB_C1_VBUS_INT,
-			.pin_pol = 1,
-		},
-		.src = {
-			.pin = GPIO_USB_C1_SRC_EN,
-			.pin_pol = 1,
-		},
-		.snk = {
-			.pin = GPIO_USB_C1_SNK_EN_L,
-			.pin_pol = 0,
-		},
-		.vconn = {
-			.cc1_pin = GPIO_USB_C1_CC1_VCONN_EN,
-			.cc2_pin = GPIO_USB_C1_CC2_VCONN_EN,
-			.pin_pol = 1,
-		},
-		.src_ilim = {
-			.pin = GPIO_USB_C1_SRC_HI_ILIM,
-			.pin_pol = 1,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[TYPE_C_PORT_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-	},
-	[TYPE_C_PORT_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* BB Retimers configuration */
-const struct bb_usb_control bb_controls[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RETIMER_RST,
-	},
-	[TYPE_C_PORT_1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RETIMER_RST,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* USB retimer Configuration */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/* USB muxes Configuration */
-const struct usb_mux usb_muxes[] = {
-	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT0_BB_RETIMER,
-		.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
-	},
-	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT1_BB_RETIMER,
-		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	/* Flash EC */
-	[I2C_CHAN_FLASH] = {
-		.name = "chan-A",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl = GPIO_I2C_A_SCL,
-		.sda = GPIO_I2C_A_SDA,
-	},
-	/*
-	 * Port-80 Display, Charger, Battery, IO-expanders, EEPROM,
-	 * IMVP9, AUX-rail, power-monitor.
-	 */
-	[I2C_CHAN_BATT_CHG] = {
-		.name = "batt_chg",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA,
-	},
-	/* Retimers, PDs */
-	[I2C_CHAN_RETIMER] = {
-		.name = "retimer",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On TGLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/*
- * Returns board information (board id[7:0] and Fab id[15:8]) on success
- * -1 on error.
- */
-int board_get_version(void)
-{
-	int port0, port1;
-	int fab_id, board_id, bom_id;
-
-	if (ioexpander_read_intelrvp_version(&port0, &port1))
-		return -1;
-	/*
-	 * Port0: bit 0   - BOM ID(2)
-	 *        bit 2:1 - FAB ID(1:0) + 1
-	 * Port1: bit 7:6 - BOM ID(1:0)
-	 *        bit 5:0 - BOARD ID(5:0)
-	 */
-	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
-	fab_id = ((port0 & 0x06) >> 1) + 1;
-	board_id = port1 & 0x3F;
-
-	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
-
-	return board_id | (fab_id << 8);
-}
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	const struct bb_usb_control *control = &bb_controls[me->usb_port];
-
-	/*
-	 * LSx based F/W updating is a POR, however to avoid the rework on
-	 * RVP retain the FORCE_PWR GPIO with EC.
-	 */
-	enum gpio_signal force_power_gpio = me->usb_port ?
-		GPIO_USB_C1_RETIMER_FORCE_PWR : GPIO_USB_C0_RETIMER_FORCE_PWR;
-
-	/* handle retimer's power domain */
-	if (enable) {
-		/*
-		 * BB retimer NVM can be shared between multiple ports, hence
-		 * lock enabling the retimer until the current retimer request
-		 * is complete.
-		 */
-		mutex_lock(&bb_nvm_mutex);
-
-		gpio_set_level(control->usb_ls_en_gpio, 1);
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		msleep(1);
-		gpio_set_level(control->retimer_rst_gpio, 1);
-		msleep(10);
-		gpio_set_level(force_power_gpio, 1);
-
-		/* Allow 20ms time for the retimer to be initialized. */
-		msleep(20);
-
-		mutex_unlock(&bb_nvm_mutex);
-	} else {
-		gpio_set_level(force_power_gpio, 0);
-		msleep(1);
-		gpio_set_level(control->retimer_rst_gpio, 0);
-		msleep(1);
-		gpio_set_level(control->usb_ls_en_gpio, 0);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h
deleted file mode 100644
index 9351fe5982..0000000000
--- a/board/tglrvpu_ite/board.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* ITE EC variant */
-#define VARIANT_INTELRVP_EC_IT8320
-
-/* MECC config */
-#define CONFIG_INTEL_RVP_MECC_VERSION_0_9
-
-/* USB MUX */
-#define CONFIG_USB_MUX_VIRTUAL
-
-#define CONFIG_USBC_VCONN
-
-/* FAN configs */
-#define CONFIG_FANS 1
-#define BOARD_FAN_MIN_RPM 3000
-#define BOARD_FAN_MAX_RPM 10000
-
-/* Temperature sensor */
-#define CONFIG_TEMP_SENSOR
-
-/* Support early firmware selection */
-#define CONFIG_VBOOT_EFS2
-#define GPIO_PACKET_MODE_EN		GPIO_ME_G3_TO_ME_EC
-
-#include "baseboard.h"
-
-#define CONFIG_CHIPSET_TIGERLAKE
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_L_PGOOD
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_L
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-#define GPIO_BAT_LED_RED_L		GPIO_BAT_LED_GREEN_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_AC_LED_GREEN_L
-
-/* Charger */
-#define CONFIG_CHARGER_ISL9241
-
-/* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-
-/* USB ports */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define DEDICATED_CHARGE_PORT 2
-
-/* USB PD config */
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-/* Config BB retimer */
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-/* Thermal configs */
-
-/* I2C ports */
-#define CONFIG_IT83XX_SMCLK2_ON_GPC7
-
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
-#define I2C_PORT0_BB_RETIMER	IT83XX_I2C_CH_E
-#define I2C_PORT1_BB_RETIMER	IT83XX_I2C_CH_E
-
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
-#define PORT80_I2C_ADDR			MAX695X_I2C_ADDR1_FLAGS
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-	#define I2C_PORT0_BB_RETIMER_ADDR	0x42
-	#define I2C_PORT1_BB_RETIMER_ADDR	0x43
-#else /* BOARD_TGLRVPY_ITE */
-	#define I2C_PORT0_BB_RETIMER_ADDR	0x42
-	#define I2C_PORT1_BB_RETIMER_ADDR	0x41
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Enabling SOP* communication */
-#define CONFIG_USB_PD_DECODE_SOP
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-#ifndef __ASSEMBLER__
-
-enum tglrvp_charge_ports {
-	TYPE_C_PORT_0,
-	TYPE_C_PORT_1,
-};
-
-enum tglrvp_i2c_channel {
-	I2C_CHAN_FLASH,
-	I2C_CHAN_BATT_CHG,
-	I2C_CHAN_RETIMER,
-	I2C_CHAN_COUNT,
-};
-
-enum battery_type {
-	BATTERY_SIMPLO_SMP_HHP_408,
-	BATTERY_SIMPLO_SMP_CA_445,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Define max power */
-#define PD_MAX_POWER_MW        60000
-
-int board_get_version(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/tglrvpu_ite/build.mk b/board/tglrvpu_ite/build.mk
deleted file mode 100644
index 4d8fd44fdf..0000000000
--- a/board/tglrvpu_ite/build.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Intel TGL-U-RVP-ITE board-specific configuration
-#
-
-#it8320
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=intelrvp
-
-board-y=board.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/tglrvpu_ite/ec.tasklist b/board/tglrvpu_ite/ec.tasklist
deleted file mode 100644
index 4e65a446e4..0000000000
--- a/board/tglrvpu_ite/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Intel TGL-U-RVP-ITE board-specific configuration.
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc
deleted file mode 100644
index e0bce1ddd8..0000000000
--- a/board/tglrvpu_ite/gpio.inc
+++ /dev/null
@@ -1,209 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel TGL-U-RVP-ITE board-specific configuration */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power sequencing interrupts */
-GPIO_INT(PG_EC_DSW_PWROK,	PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(C, 3), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(ALL_SYS_PWRGD,		PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_L_PGOOD,	PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PCH_SLP_S0_L,		PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-
-/* Button interrupts */
-GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
-GPIO_INT(POWER_BUTTON_L,PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)
-
-GPIO_INT(AC_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)
-
-GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART1 RX input */
-
-GPIO_INT(WP_L,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-
-#ifdef CONFIG_HOSTCMD_ESPI
-/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
-#endif
-
-GPIO_INT(TABLET_MODE_L,	PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* DC Jack presence coming from +VADP_OUT */
-GPIO_INT(DC_JACK_PRESENT,	PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt)
-
-/* Type-C interrupts */
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-GPIO_INT(USB_C0_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-#else /* BOARD_TGLRVPY_ITE */
-GPIO_INT(USB_C0_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event)
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Power sequencing GPIOs */
-GPIO(CPU_PROCHOT,	PIN(B, 2), GPIO_INPUT)
-GPIO(SYS_RESET_L,	PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
-GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
-GPIO(EC_SPI_OE_N,	PIN(I, 2), GPIO_OUT_LOW)
-/*
- * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
- * power sequencing expects that PCH_SYS_PWROK is an output and will drive
- * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
- * so that state can be monitored using the console.
- */
-GPIO(NC_PCH_SYS_PWROK,	PIN(K, 4), GPIO_INPUT)
-GPIO(EN_PP5000,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
-
-/* Host communication GPIOs */
-GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-
-/* Battery present */
-GPIO(EC_BATT_PRES_L,	PIN(K, 0), GPIO_INPUT)
-
-/* Type-C GPIOs */
-#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1)
-GPIO(USB_C0_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD,	PIN(E, 6), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_HPD,	PIN(D, 3), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-/* Retimer GPIOs */
-GPIO(USB_C0_LS_EN,		PIN(J, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_RST,	PIN(J, 5), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_FORCE_PWR,	PIN(J, 3), GPIO_OUT_LOW)
-
-GPIO(USB_C1_LS_EN,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_RST,	PIN(J, 4), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_FORCE_PWR,	PIN(H, 5), GPIO_OUT_LOW)
-#else /* BOARD_TGLRVPY_ITE */
-GPIO(USB_C0_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW | GPIO_PULL_DOWN)
-GPIO(USB_C0_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
-GPIO(USB_C0_HPD,	PIN(D, 3), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,	PIN(K, 5), GPIO_INPUT)
-
-GPIO(USB_C1_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW | GPIO_PULL_DOWN)
-GPIO(USB_C1_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
-GPIO(USB_C1_HPD,	PIN(E, 6), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN,	PIN(L, 7), GPIO_INPUT)
-
-/* Retimer GPIOs */
-GPIO(USB_C0_LS_EN,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_RST,	PIN(J, 4), GPIO_OUT_LOW)
-GPIO(USB_C0_RETIMER_FORCE_PWR,	PIN(H, 5), GPIO_OUT_LOW)
-
-GPIO(USB_C1_LS_EN,		PIN(J, 1), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_RST,	PIN(J, 5), GPIO_OUT_LOW)
-GPIO(USB_C1_RETIMER_FORCE_PWR,	PIN(J, 3), GPIO_OUT_LOW)
-#endif /* BOARD_TGLRVPU_ITE */
-
-/* Type-C BC1.2 GPIOs */
-GPIO(USB_C0_BC12_CHG_DET_L,	PIN(A, 1), GPIO_INPUT)
-GPIO(USB_C0_BC12_VBUS_ON_ODL,	PIN(H, 4), GPIO_ODR_HIGH)
-
-GPIO(USB_C1_BC12_CHG_DET_L,	PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_BC12_VBUS_ON_ODL,	PIN(J, 6), GPIO_ODR_HIGH)
-
-/* VCONN enable pins */
-GPIO(USB_C0_CC1_VCONN_EN,	PIN(D, 1), GPIO_OUT_LOW)
-GPIO(USB_C0_CC2_VCONN_EN,	PIN(G, 2), GPIO_OUT_LOW)
-GPIO(USB_C1_CC1_VCONN_EN,	PIN(E, 5), GPIO_OUT_LOW)
-GPIO(USB_C1_CC2_VCONN_EN,	PIN(I, 0), GPIO_OUT_LOW)
-
-/* USB-A GPIOs */
-GPIO(USB_A_5V_EN,	PIN(K, 3), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_GREEN_L,	PIN(A, 6), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(AC_LED_GREEN_L,	PIN(A, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-
-/* FAN control pins */
-GPIO(FAN_POWER_EN,	PIN(K, 6), GPIO_OUT_LOW)
-
-/* H1 pins */
-GPIO(CCD_MODE_ODL,	PIN(B, 5), GPIO_INPUT)
-GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUT_LOW)
-/* ME_GE_TO_ME_EC pin is re-purposed for H1 Packet Mode indication */
-GPIO(ME_G3_TO_ME_EC,	PIN(H, 3), GPIO_OUT_LOW)
-
-/* Used with Discrete TBT and or with PD on RVP */
-GPIO(NC_TBT_C0_RESET_N,		PIN(KSO_H, 7), GPIO_INPUT)
-GPIO(NC_TBT_C1_RESET_N,		PIN(K, 7), GPIO_INPUT)
-GPIO(NC_USB_C0_RETIMER_ALRT,	PIN(I, 7), GPIO_INPUT)
-GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
-
-/* Used if Base EC is present */
-GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
-
-#ifndef CONFIG_HOSTCMD_ESPI
-GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
-#endif
-
-/* Unused pins */
-GPIO(NC_SUSWARN,		PIN(E, 1), GPIO_INPUT)
-GPIO(NC_BATT_DISABLE,		PIN(H, 0), GPIO_INPUT)
-GPIO(NC_SMC_ONOFF_N,		PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */
-
-/*
- * I2C pins should be configure as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(I2C_C_SCL,	PIN(C, 7), GPIO_INPUT)
-GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
-GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(I2C_F_SCL,	PIN(A, 4), GPIO_INPUT)
-GPIO(I2C_F_SDA,	PIN(A, 5), GPIO_INPUT)
-
-/* Alternate pins for I2C */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
-ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SCL C7 */
-ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SDA F7 */
-
-/* Alternate pins for UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
-
-/* Alternate pins for ADC */
-ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
-ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
-
-/* Alternate pins for FAN */
-ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* PWM2 A2 */
-ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* TACH1A D7 */
diff --git a/board/tglrvpu_ite/vif_override.xml b/board/tglrvpu_ite/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/tglrvpu_ite/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/tglrvpu_ite_tcpmv1 b/board/tglrvpu_ite_tcpmv1
deleted file mode 120000
index 05edd4d22f..0000000000
--- a/board/tglrvpu_ite_tcpmv1
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpu_ite
\ No newline at end of file
diff --git a/board/tglrvpy_ite b/board/tglrvpy_ite
deleted file mode 120000
index 05edd4d22f..0000000000
--- a/board/tglrvpy_ite
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpu_ite
\ No newline at end of file
diff --git a/board/tglrvpy_ite_tcpmv1 b/board/tglrvpy_ite_tcpmv1
deleted file mode 120000
index 560115c8ab..0000000000
--- a/board/tglrvpy_ite_tcpmv1
+++ /dev/null
@@ -1 +0,0 @@
-tglrvpy_ite
\ No newline at end of file
diff --git a/board/tigertail/board.c b/board/tigertail/board.c
deleted file mode 100644
index f4d0382b9c..0000000000
--- a/board/tigertail/board.c
+++ /dev/null
@@ -1,514 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tigertail board configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ina2xx.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "update_fw.h"
-#include "usart-stm32f0.h"
-#include "usart_tx_dma.h"
-#include "usart_rx_dma.h"
-#include "usb_i2c.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#include "gpio_list.h"
-
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-/******************************************************************************
- * Forward UARTs as a USB serial interface.
- */
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-/******************************************************************************
- * Forward USART1 as a simple USB serial interface.
- */
-static struct usart_config const usart1;
-struct usb_stream_config const usart1_usb;
-
-static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
-
-static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb)
-
-
-/******************************************************************************
- * Define the strings used in our USB descriptors.
- */
-const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Tigertail"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART1_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Tigertail Console"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-};
-
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-
-/******************************************************************************
- * ADC support for SBU flip detect.
- */
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_SBU1] = {"SBU1", 3300, 4096, 0, STM32_AIN(6)},
-	[ADC_SBU2] = {"SBU2", 3300, 4096, 0, STM32_AIN(7)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-
-
-/******************************************************************************
- * Support I2C bridging over USB.
- */
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100,
-		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-int usb_i2c_board_is_enabled(void) { return 1; }
-
-/******************************************************************************
- * Console commands.
- */
-
-/* State to indicate current GPIO config. */
-static int uart_state = UART_OFF;
-/* State to indicate current autodetect mode. */
-static int uart_detect = UART_DETECT_AUTO;
-
-const char *const uart_state_names[] = {
-	[UART_OFF] = "off",
-	[UART_ON_PP1800] = "on @ 1.8v",
-	[UART_FLIP_PP1800] = "flip @ 1.8v",
-	[UART_ON_PP3300] = "on @ 3.3v",
-	[UART_FLIP_PP3300] = "flip @ 3.3v",
-	[UART_AUTO] = "auto",
-};
-
-/* Set GPIOs to configure UART mode. */
-static void set_uart_gpios(int state)
-{
-	int uart = GPIO_INPUT;
-	int dir = 0;
-	int voltage = 1;  /* 1: 1.8v, 0: 3.3v */
-	int enabled = 0;
-
-	gpio_set_level(GPIO_ST_UART_LVL_DIS, 1);
-
-	switch (state) {
-	case UART_ON_PP1800:
-		uart = GPIO_ALTERNATE;
-		dir = 1;
-		voltage = 1;
-		enabled = 1;
-		break;
-
-	case UART_FLIP_PP1800:
-		uart = GPIO_ALTERNATE;
-		dir = 0;
-		voltage = 1;
-		enabled = 1;
-		break;
-
-	case UART_ON_PP3300:
-		uart = GPIO_ALTERNATE;
-		dir = 1;
-		voltage = 0;
-		enabled = 1;
-		break;
-
-	case UART_FLIP_PP3300:
-		uart = GPIO_ALTERNATE;
-		dir = 0;
-		voltage = 0;
-		enabled = 1;
-		break;
-
-	default:
-		/* Default to UART_OFF. */
-		uart = GPIO_INPUT;
-		dir = 0;
-		enabled = 0;
-	}
-
-	/* Set level shifter direction and voltage. */
-	gpio_set_level(GPIO_ST_UART_VREF, voltage);
-	gpio_set_level(GPIO_ST_UART_TX_DIR, dir);
-	gpio_set_level(GPIO_ST_UART_TX_DIR_N, !dir);
-
-	/* Enable STM pinmux */
-	gpio_set_flags(GPIO_USART1_TX, uart);
-	gpio_set_flags(GPIO_USART1_RX, uart);
-
-	/* Flip uart orientation if necessary. */
-	STM32_USART_CR1(STM32_USART1_BASE) &= ~(STM32_USART_CR1_UE);
-	if (dir)
-		STM32_USART_CR2(STM32_USART1_BASE) &= ~(STM32_USART_CR2_SWAP);
-	else
-		STM32_USART_CR2(STM32_USART1_BASE) |= (STM32_USART_CR2_SWAP);
-	STM32_USART_CR1(STM32_USART1_BASE) |= STM32_USART_CR1_UE;
-
-	/* Enable level shifter. */
-	usleep(1000);
-	gpio_set_level(GPIO_ST_UART_LVL_DIS, !enabled);
-}
-
-/*
- * Detect if a UART is plugged into SBU. Tigertail UART must be off
- * for this to return useful info.
- */
-static int is_low(int mv)
-{
-	return (mv < 190);
-}
-
-static int is_3300(int mv)
-{
-	return ((mv > 3000) && (mv < 3400));
-}
-
-static int is_1800(int mv)
-{
-	return ((mv > 1600) && (mv < 1900));
-}
-
-static int detect_uart_orientation(void)
-{
-	int sbu1 = adc_read_channel(ADC_SBU1);
-	int sbu2 = adc_read_channel(ADC_SBU2);
-	int state = UART_OFF;
-
-	/*
-	 * Here we check if one or the other SBU is 1.8v, as DUT
-	 * TX should idle high.
-	 */
-	if (is_low(sbu1) && is_1800(sbu2))
-		state = UART_ON_PP1800;
-	else if (is_low(sbu2) && is_1800(sbu1))
-		state = UART_FLIP_PP1800;
-	else if (is_low(sbu1) && is_3300(sbu2))
-		state = UART_ON_PP3300;
-	else if (is_low(sbu2) && is_3300(sbu1))
-		state = UART_FLIP_PP3300;
-	else
-		state = UART_OFF;
-
-	return state;
-}
-
-/*
- * Detect if UART has been unplugged. Normal UARTs should
- * have both lines idling high at 1.8v.
- */
-static int detect_uart_idle(void)
-{
-	int sbu1 = adc_read_channel(ADC_SBU1);
-	int sbu2 = adc_read_channel(ADC_SBU2);
-	int enabled = 0;
-
-	if (is_1800(sbu1) && is_1800(sbu2))
-		enabled = 1;
-
-	if (is_3300(sbu1) && is_3300(sbu2))
-		enabled = 1;
-
-	return enabled;
-}
-
-/* Set the UART state and gpios, and autodetect if necessary. */
-void set_uart_state(int state)
-{
-	if (state == UART_AUTO) {
-		set_uart_gpios(UART_OFF);
-		msleep(10);
-
-		uart_detect = UART_DETECT_AUTO;
-		state = detect_uart_orientation();
-	} else {
-		uart_detect = UART_DETECT_OFF;
-	}
-
-	uart_state = state;
-	set_uart_gpios(state);
-}
-
-/*
- * Autodetect UART state:
- * We will check every 250ms, and change state if 1 second has passed
- * in the new state.
- */
-void uart_sbu_tick(void)
-{
-	static int debounce;  /* = 0 */
-
-	if (uart_detect != UART_DETECT_AUTO)
-		return;
-
-	if (uart_state == UART_OFF) {
-		int state = detect_uart_orientation();
-
-		if (state != UART_OFF) {
-			debounce++;
-			if (debounce > 4) {
-				debounce = 0;
-				CPRINTS("UART autoenable %s",
-					uart_state_names[state]);
-				uart_state = state;
-				set_uart_gpios(state);
-			}
-			return;
-		}
-	} else {
-		int enabled = detect_uart_idle();
-
-		if (!enabled) {
-			debounce++;
-			if (debounce > 4) {
-				debounce = 0;
-				CPRINTS("UART autodisable");
-				uart_state = UART_OFF;
-				set_uart_gpios(UART_OFF);
-			}
-			return;
-		}
-	}
-	debounce = 0;
-}
-DECLARE_HOOK(HOOK_TICK, uart_sbu_tick, HOOK_PRIO_DEFAULT);
-
-static int command_uart(int argc, char **argv)
-{
-	const char *uart_state_str = "off";
-	const char *uart_detect_str = "manual";
-
-	if (argc > 1) {
-		if (!strcasecmp("off", argv[1]))
-			set_uart_state(UART_OFF);
-		else if (!strcasecmp("on18", argv[1]))
-			set_uart_state(UART_ON_PP1800);
-		else if (!strcasecmp("on33", argv[1]))
-			set_uart_state(UART_ON_PP3300);
-		else if (!strcasecmp("flip18", argv[1]))
-			set_uart_state(UART_FLIP_PP1800);
-		else if (!strcasecmp("flip33", argv[1]))
-			set_uart_state(UART_FLIP_PP3300);
-		else if (!strcasecmp("auto", argv[1]))
-			set_uart_state(UART_AUTO);
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	uart_state_str = uart_state_names[uart_state];
-	if (uart_detect == UART_DETECT_AUTO)
-		uart_detect_str = "auto";
-	ccprintf("UART mux is: %s, setting: %s\n",
-		uart_state_str, uart_detect_str);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(uart, command_uart,
-	"[off|on18|on33|flip18|flip33|auto]",
-	"Set the sbu uart state\n"
-	"WARNING: 3.3v may damage 1.8v devices.\n");
-
-static void set_led_a(int r, int g, int b)
-{
-	/* LEDs are active low */
-	gpio_set_level(GPIO_LED_R_L, !r);
-	gpio_set_level(GPIO_LED_G_L, !g);
-	gpio_set_level(GPIO_LED_B_L, !b);
-}
-
-static void set_led_b(int r, int g, int b)
-{
-	gpio_set_level(GPIO_LED2_R_L, !r);
-	gpio_set_level(GPIO_LED2_G_L, !g);
-	gpio_set_level(GPIO_LED2_B_L, !b);
-}
-
-/* State we intend the mux GPIOs to be set. */
-static int mux_state = MUX_OFF;
-static int last_mux_state = MUX_OFF;
-
-/* Set the state variable and GPIO configs to mux as requested. */
-void set_mux_state(int state)
-{
-	int enabled = (state == MUX_A) || (state == MUX_B);
-	/* dir: 0 -> A, dir: 1 -> B */
-	int dir = (state == MUX_B);
-
-	if (mux_state != state)
-		last_mux_state = mux_state;
-
-	/* Disconnect first. */
-	gpio_set_level(GPIO_USB_C_OE_N, 1);
-	gpio_set_level(GPIO_SEL_RELAY_A, 0);
-	gpio_set_level(GPIO_SEL_RELAY_B, 0);
-
-	/* Let USB disconnect. */
-	msleep(100);
-
-	/* Reconnect VBUS/CC in the requested direction. */
-	gpio_set_level(GPIO_SEL_RELAY_A, !dir && enabled);
-	gpio_set_level(GPIO_SEL_RELAY_B, dir && enabled);
-
-	/* Reconnect data. */
-	msleep(10);
-
-	gpio_set_level(GPIO_USB_C_SEL_B, dir);
-	gpio_set_level(GPIO_USB_C_OE_N, !enabled);
-
-	if (!enabled)
-		mux_state = MUX_OFF;
-	else
-		mux_state = state;
-
-	if (state == MUX_A)
-		set_led_a(0, 1, 0);
-	else
-		set_led_a(1, 0, 0);
-
-	if (state == MUX_B)
-		set_led_b(0, 1, 0);
-	else
-		set_led_b(1, 0, 0);
-}
-
-
-/* On button press, toggle between mux A, B, off. */
-static int button_ready = 1;
-void button_interrupt_deferred(void)
-{
-	switch (mux_state) {
-	case MUX_OFF:
-		if (last_mux_state == MUX_A)
-			set_mux_state(MUX_B);
-		else
-			set_mux_state(MUX_A);
-		break;
-
-	case MUX_A:
-	case MUX_B:
-	default:
-		set_mux_state(MUX_OFF);
-		break;
-	}
-
-	button_ready = 1;
-}
-DECLARE_DEFERRED(button_interrupt_deferred);
-
-/* On button press, toggle between mux A, B, off. */
-void button_interrupt(enum gpio_signal signal)
-{
-	if (!button_ready)
-		return;
-
-	button_ready = 0;
-	/*
-	 * button_ready is not set until set_mux_state completes,
-	 * which has ~100ms settle time for the mux, which also
-	 * provides for debouncing.
-	 */
-	hook_call_deferred(&button_interrupt_deferred_data, 0);
-}
-
-static int command_mux(int argc, char **argv)
-{
-	char *mux_state_str = "off";
-
-	if (argc > 1) {
-		if (!strcasecmp("off", argv[1]))
-			set_mux_state(MUX_OFF);
-		else if (!strcasecmp("a", argv[1]))
-			set_mux_state(MUX_A);
-		else if (!strcasecmp("b", argv[1]))
-			set_mux_state(MUX_B);
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	if (mux_state == MUX_A)
-		mux_state_str = "A";
-	if (mux_state == MUX_B)
-		mux_state_str = "B";
-	ccprintf("TYPE-C mux is %s\n", mux_state_str);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(mux, command_mux,
-	"[off|A|B]",
-	"Get/set the mux and enable state of the TYPE-C mux");
-
-/******************************************************************************
- * Initialize board.
- */
-static void board_init(void)
-{
-	/* USB to serial queues */
-	queue_init(&usart1_to_usb);
-	queue_init(&usb_to_usart1);
-
-	/* UART init */
-	usart_init(&usart1);
-
-	/*
-	 * Default to port A, to allow easier charging and
-	 * detection of unconfigured devices.
-	 */
-	set_mux_state(MUX_A);
-
-	/* Note that we can't enable AUTO until after init. */
-	set_uart_gpios(UART_OFF);
-
-	/* Calibrate INA0 (VBUS) with 1mA/LSB scale */
-	ina2xx_init(0, 0x8000, INA2XX_CALIB_1MA(15 /*mOhm*/));
-	ina2xx_init(1, 0x8000, INA2XX_CALIB_1MA(15 /*mOhm*/));
-	ina2xx_init(4, 0x8000, INA2XX_CALIB_1MA(15 /*mOhm*/));
-
-	gpio_enable_interrupt(GPIO_BUTTON_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/tigertail/board.h b/board/tigertail/board.h
deleted file mode 100644
index 3b15c4c774..0000000000
--- a/board/tigertail/board.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tigertail configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* Enable USART1 USB streams */
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1
-#define CONFIG_STREAM_USB
-#define CONFIG_CMD_USART_INFO
-
-/* The UART console is on USART1 (PA9/PA10) */
-#undef CONFIG_UART_CONSOLE
-#define CONFIG_UART_CONSOLE 2
-#undef CONFIG_UART_TX_DMA
-#undef CONFIG_UART_RX_DMA
-
-/* Optional features */
-#define CONFIG_STM_HWTIMER32
-#define CONFIG_HW_CRC
-
-/* USB Configuration */
-#define CONFIG_USB
-#define CONFIG_USB_PID 0x5027
-#define CONFIG_USB_CONSOLE
-#define CONFIG_USB_UPDATE
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 100
-
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "Uninitialized"
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_USART1_STREAM	2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_USART1_STREAM	3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
-
-/* Enable console recasting of GPIO type. */
-#define CONFIG_CMD_GPIO_EXTENDED
-
-/* This is not actually an EC so disable some features. */
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-
-/* Enable control of I2C over USB */
-#define CONFIG_USB_I2C
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 0
-#define CONFIG_INA231
-
-/* Enable ADC */
-#define CONFIG_ADC
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-
-#ifndef __ASSEMBLER__
-
-/* Timer selection */
-#define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_SERIALNO,
-	USB_STR_VERSION,
-	USB_STR_I2C_NAME,
-	USB_STR_USART1_STREAM_NAME,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_UPDATE_NAME,
-
-	USB_STR_COUNT
-};
-
-/* ADC signal */
-enum adc_channel {
-	ADC_SBU1 = 0,
-	ADC_SBU2,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-void set_uart_state(int state);
-
-enum uart_states {
-	UART_OFF = 0,
-	UART_ON_PP1800,
-	UART_FLIP_PP1800,
-	UART_ON_PP3300,
-	UART_FLIP_PP3300,
-	UART_AUTO,
-};
-
-enum uart_detect_states {
-	UART_DETECT_OFF = 0,
-	UART_DETECT_AUTO,
-};
-
-void set_mux_state(int state);
-enum mux_states {
-	MUX_OFF = 0,
-	MUX_A,
-	MUX_B,
-};
-
-void button_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/tigertail/build.mk b/board/tigertail/build.mk
deleted file mode 100644
index 9e7fae1c07..0000000000
--- a/board/tigertail/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072CBU6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o
diff --git a/board/tigertail/ec.tasklist b/board/tigertail/ec.tasklist
deleted file mode 100644
index afdb5dedc7..0000000000
--- a/board/tigertail/ec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/tigertail/gpio.inc b/board/tigertail/gpio.inc
deleted file mode 100644
index 107d3b2a2e..0000000000
--- a/board/tigertail/gpio.inc
+++ /dev/null
@@ -1,65 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt enables. */
-GPIO_INT(BUTTON_L,			PIN(C, 13), \
-	 GPIO_INT_RISING | GPIO_PULL_UP, button_interrupt)
-
-/* Outputs */
-GPIO(SEL_CC2_A,			PIN(A, 14), GPIO_OUT_LOW)
-GPIO(SEL_VBUS_A,		PIN(A, 15), GPIO_OUT_LOW)
-GPIO(SEL_CC2_B,			PIN(B,  0), GPIO_OUT_LOW)
-GPIO(SEL_VBUS_B,		PIN(B,  1), GPIO_OUT_LOW)
-GPIO(SEL_RELAY_A,		PIN(B,  2), GPIO_OUT_LOW)
-GPIO(SEL_RELAY_B,		PIN(B,  3), GPIO_OUT_LOW)
-GPIO(USB_C_SEL_B,		PIN(B,  4), GPIO_OUT_LOW)
-GPIO(USB_C_OE_N,		PIN(B,  5), GPIO_OUT_HIGH)
-
-GPIO(ST_UART_LVL_DIS,		PIN(B, 10), GPIO_OUT_HIGH)
-GPIO(ST_UART_TX_DIR,		PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(ST_UART_TX_DIR_N,		PIN(B, 15), GPIO_OUT_LOW)
-/* SBU_VSET, 1=1.8V, 0=3.3V */
-GPIO(ST_UART_VREF,		PIN(B,  7), GPIO_OUT_HIGH)
-
-GPIO(LED2_G_L,			PIN(A,  5), GPIO_OUT_HIGH)
-GPIO(LED2_B_L, 			PIN(A,  8), GPIO_OUT_HIGH)
-GPIO(LED2_R_L,			PIN(A, 13), GPIO_OUT_LOW)
-
-GPIO(LED_G_L,			PIN(B, 11), GPIO_OUT_HIGH)
-GPIO(LED_R_L,			PIN(B, 13), GPIO_OUT_LOW)
-GPIO(LED_B_L,			PIN(B, 14), GPIO_OUT_HIGH)
-
-/* Inputs */
-GPIO(USB_C_SBU1_DET,		PIN(A,  6), GPIO_INPUT)
-GPIO(USB_C_SBU2_DET,		PIN(A,  7), GPIO_INPUT)
-
-/* USART interface */
-GPIO(USART2_CTS,		PIN(A,  0), GPIO_INPUT)
-GPIO(USART2_RTS,		PIN(A,  1), GPIO_INPUT)
-GPIO(USART2_TX,			PIN(A,  2), GPIO_INPUT)
-GPIO(USART2_RX,			PIN(A,  3), GPIO_INPUT)
-GPIO(USART2_CK,			PIN(A,  4), GPIO_INPUT)
-
-GPIO(USART1_TX,			PIN(A,  9), GPIO_INPUT)
-GPIO(USART1_RX,			PIN(A, 10), GPIO_INPUT)
-
-/* I2C pins should be configured as inputs until I2C module is    */
-/* initialized. This will avoid driving the lines unintentionally.*/
-GPIO(MASTER_I2C_SCL,		PIN(B,  8), GPIO_INPUT)
-GPIO(MASTER_I2C_SDA,		PIN(B,  9), GPIO_INPUT)
-
-/* Unimplemented signals since we are not an EC */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-/* USART2: PA2/PA3 - Console UART */
-ALTERNATE(PIN_MASK(A, 0x000C), 1, MODULE_UART, 0)
-/* USART1: PA09/PA10 - AP/SBU UART */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0)
-
-/* I2C MASTER:PB8/9 GPIO_ODR_HIGH */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C, 0)
diff --git a/board/todor/battery.c b/board/todor/battery.c
deleted file mode 100644
index d129ede528..0000000000
--- a/board/todor/battery.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/todor/board.c b/board/todor/board.c
deleted file mode 100644
index c4e2395adc..0000000000
--- a/board/todor/board.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Todor if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On Proto-1 only Port 1 supports TBT & USB4
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_0_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_0_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025015): Terrador: check USB PD reset operation */
-}
-
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-};
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration.
- */
-static void setup_mux(void)
-{
-	CPRINTS("C0 supports bb-retimer");
-	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
-}
-
-__override void board_cbi_init(void)
-{
-	/*
-	 * TODO(b/159025015): Terrador: check FW_CONFIG fields for USB DB type
-	 */
-	setup_mux();
-	/* Reassign USB_C0_RT_RST_ODL */
-	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
-	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/todor/board.h b/board/todor/board.h
deleted file mode 100644
index dd63c5c04b..0000000000
--- a/board/todor/board.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/todor/build.mk b/board/todor/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/todor/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/todor/ec.tasklist b/board/todor/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/todor/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/todor/gpio.inc b/board/todor/gpio.inc
deleted file mode 100644
index 606a17fcb6..0000000000
--- a/board/todor/gpio.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(6, 1), GPIO_ODR_LOW) /* USB_C0 Reset */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_FRS_EN,			PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(UART2_EC_RX,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_0_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(B, 7), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/todor/led.c b/board/todor/led.c
deleted file mode 100644
index 31d1c6fe20..0000000000
--- a/board/todor/led.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/todor/sensors.c b/board/todor/sensors.c
deleted file mode 100644
index 9997591cb6..0000000000
--- a/board/todor/sensors.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/todor/vif_override.xml b/board/todor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/todor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/tomato b/board/tomato
deleted file mode 120000
index e96f559c72..0000000000
--- a/board/tomato
+++ /dev/null
@@ -1 +0,0 @@
-cherry
\ No newline at end of file
diff --git a/board/treeya/analyzestack.yaml b/board/treeya/analyzestack.yaml
deleted file mode 120000
index 9873122a08..0000000000
--- a/board/treeya/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/grunt/analyzestack.yaml
\ No newline at end of file
diff --git a/board/treeya/battery.c b/board/treeya/battery.c
deleted file mode 100644
index a98a38d3e9..0000000000
--- a/board/treeya/battery.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Treeya battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP 5B10Q13163 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L17M3PB0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 186,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	/* LGC 5B10Q13162  */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L17L3PB0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 181,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-	/* Sunwoda L18D3PG1  */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "SUNWODA",
-			.device_name = "L18D3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050, /* mV */
-			.voltage_normal		= 11250, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SMP L19M3PG1 */
-	[BATTERY_SMP_1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* LGC  L19L3PG1 */
-	[BATTERY_LGC_1] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* Celxpert  L19C3PG1 */
-	[BATTERY_CEL_1] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L19C3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP_1;
diff --git a/board/treeya/board.c b/board/treeya/board.c
deleted file mode 100644
index 4583d89d7c..0000000000
--- a/board/treeya/board.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Treeya board-specific configuration */
-
-#include "button.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "extpower.h"
-#include "i2c.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "system.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-
-#include "gpio_list.h"
-
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-	GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map. */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"thermal", I2C_PORT_THERMAL_AP, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
-	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Motion sensors */
-static struct mutex g_lid_mutex_1;
-static struct mutex g_base_mutex_1;
-
-/* Lid accel private data */
-static struct stprivate_data g_lis2dwl_data;
-/* Base accel private data */
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t lid_accel_1 = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LIS2DWL,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &lis2dw12_drv,
-	.mutex = &g_lid_mutex_1,
-	.drv_data = &g_lis2dwl_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	.rot_standard_ref = NULL,
-	.default_range = 2, /* g */
-	.min_frequency = LIS2DW12_ODR_MIN_VAL,
-	.max_frequency = LIS2DW12_ODR_MAX_VAL,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t base_accel_1 = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.rot_standard_ref = &lsm6dsm_base_standard_ref,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t base_gyro_1 = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_LSM6DSM,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &lsm6dsm_drv,
-	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	.rot_standard_ref = &lsm6dsm_base_standard_ref,
-	.min_frequency = LSM6DSM_ODR_MIN_VAL,
-	.max_frequency = LSM6DSM_ODR_MAX_VAL,
-};
-
-static int board_use_st_sensor(void)
-{
-	/* sku_id 0xa8-0xa9 use ST sensors */
-	uint32_t sku_id = system_get_sku_id();
-
-	return sku_id == 0xa8 || sku_id == 0xa9;
-}
-
-/* treeya board will use two sets of lid/base sensor, we need update
- * sensors info according to sku id.
- */
-void board_update_sensor_config_from_sku(void)
-{
-	if (board_is_convertible()) {
-		/* sku_id a8-a9 use ST sensors */
-		if (board_use_st_sensor()) {
-			motion_sensors[LID_ACCEL] = lid_accel_1;
-			motion_sensors[BASE_ACCEL] = base_accel_1;
-			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
-			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
-		}
-
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-
-/* bmi160 or lsm6dsm need differenct interrupt function */
-void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal)
-{
-	if (board_use_st_sensor())
-		lsm6dsm_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
diff --git a/board/treeya/board.h b/board/treeya/board.h
deleted file mode 100644
index 339929a873..0000000000
--- a/board/treeya/board.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Treeya board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_GRUNT_TCPC_0_ANX3447
-
-#include "baseboard.h"
-
-/*
- * By default, enable all console messages excepted HC, ACPI and event:
- * The sensor stack is generating a lot of activity.
- */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* Power and battery LEDs */
-#define CONFIG_LED_COMMON
-#define CONFIG_CMD_LEDTEST
-
-#define CONFIG_LED_ONOFF_STATES
-
-/* Disable keyboard backlight */
-#undef CONFIG_PWM
-#undef CONFIG_PWM_KBLIGHT
-
-#define CONFIG_MKBP_USE_GPIO
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-/*
- * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
- */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
-#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
-
-/* Second set of sensor drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LIS2DWL
-
-#ifndef __ASSEMBLER__
-
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_LGC,
-	BATTERY_SUNWODA,
-	BATTERY_SMP_1,
-	BATTERY_LGC_1,
-	BATTERY_CEL_1,
-	BATTERY_TYPE_COUNT,
-};
-
-void board_bmi160_lsm6dsm_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/treeya/build.mk b/board/treeya/build.mk
deleted file mode 100644
index 250abe6712..0000000000
--- a/board/treeya/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6f
-BASEBOARD:=grunt
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/treeya/ec.tasklist b/board/treeya/ec.tasklist
deleted file mode 100644
index fb6e2f75a1..0000000000
--- a/board/treeya/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/treeya/gpio.inc b/board/treeya/gpio.inc
deleted file mode 100644
index 70e2e1b29c..0000000000
--- a/board/treeya/gpio.inc
+++ /dev/null
@@ -1,119 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_SWCTL_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
-GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP,	lid_interrupt)
-GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	board_bmi160_lsm6dsm_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-
-GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(SYS_RESET_L,		PIN(E, 4), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_BATT_PRES_L,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
-GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
-GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
-GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
-GPIO(EC_INT_L,			PIN(A, 4), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
-GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
-GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
-GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
-GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
-GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
-GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
-GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
-GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
-										   EC_I2C_KB_BL_SCL */
-GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
-										   EC_I2C_KB_BL_SDA */
-GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
-GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
-
-/*
- * The NPCX LPC driver configures and controls SCI and SMI,
- * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
- * not defined here as GPIOs.
- */
-
-GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
-GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
-GPIO(USB_C1_OC_L,		PIN(7, 2), GPIO_OUT_HIGH)			/* C1 Over Current */
-GPIO(USB_C0_PD_RST,		PIN(3, 2), GPIO_OUT_HIGH)			/* C0 PD Reset */
-GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
-GPIO(USB_C0_BC12_VBUS_ON_L,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
-GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP)	/* C1 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
-GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN)		/* C1 BC1.2 Detect */
-GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-
-/* Board ID */
-GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
-GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
-GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
-GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
-
-/* LED */
-GPIO(BAT_LED_1_L,	 PIN(C, 3), GPIO_OUT_HIGH)
-GPIO(BAT_LED_2_L,	 PIN(C, 4), GPIO_OUT_HIGH)
-GPIO(POWER_LED_3_L,	 PIN(B, 7), GPIO_OUT_HIGH)
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)					/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)					/* I2C3 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)					/* I2C5 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0)					/* I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)					/* ADC0-1 */
-ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0)					/* ADC4 */
-ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0)					/* ADC8 */
-ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0)					/* ADC9 */
-
-/* Keyboard Pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)					/* GPIO00 = AC_PRESENT,
-										   GPIO01 = POWER_BUTTON_L,
-										   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)					/* GPIOD2 = LID_OPEN */
diff --git a/board/treeya/led.c b/board/treeya/led.c
deleted file mode 100644
index 9647b45e74..0000000000
--- a/board/treeya/led.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "led_onoff_states.h"
-#include "led_common.h"
-#include "gpio.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_POWER_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_POWER_LED_3_L, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/treeya/vif_override.xml b/board/treeya/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/treeya/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/trembyle/analyzestack.yaml b/board/trembyle/analyzestack.yaml
deleted file mode 120000
index 4c09084128..0000000000
--- a/board/trembyle/analyzestack.yaml
+++ /dev/null
@@ -1 +0,0 @@
-../../baseboard/zork/analyzestack.yaml
\ No newline at end of file
diff --git a/board/trembyle/battery.c b/board/trembyle/battery.c
deleted file mode 100644
index 33e4e9ce5d..0000000000
--- a/board/trembyle/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AP18F4M */
-	[BATTERY_AP18F4M] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00404001",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8700,
-			.voltage_normal       = 7600,
-			.voltage_min          = 5500,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
diff --git a/board/trembyle/board.c b/board/trembyle/board.c
deleted file mode 100644
index 89a62f3411..0000000000
--- a/board/trembyle/board.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "charger.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/retimer/pi3dpx1207.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-
-#include "gpio_list.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = NULL,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	IOEX_EN_USB_A1_5V_DB,
-};
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS5,
-};
-
-/*****************************************************************************
- * Board suspend / resume
- */
-#define PS8811_ACCESS_RETRIES 2
-
-static void board_chipset_resume(void)
-{
-	int rv;
-	int retry;
-
-	/* Turn on the retimers */
-	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 1);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-
-	/* USB-A0 can run with default settings */
-	for (retry = 0; retry < PS8811_ACCESS_RETRIES; ++retry) {
-		int val;
-
-		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
-		if (!rv)
-			break;
-	}
-	if (rv) {
-		ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
-		CPRINTSUSB("A0: PS8811 not detected");
-	}
-
-	/* USB-A1 needs to increase gain to get over MB/DB connector */
-	for (retry = 0; retry < PS8811_ACCESS_RETRIES; ++retry) {
-		rv = i2c_write8(I2C_PORT_USBA1,
-				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL,
-				PS8811_BEQ_I2C_LEVEL_UP_13DB |
-				PS8811_BEQ_PIN_LEVEL_UP_18DB);
-		if (!rv)
-			break;
-	}
-	if (rv) {
-		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-		CPRINTSUSB("A1: PS8811 not detected");
-	}
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration
- */
-static void setup_mux(void)
-{
-	if (ec_config_has_usbc1_retimer_ps8802()) {
-		/*
-		 * Main MUX is PS8802, secondary MUX is modified FP5
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
-
-		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-
-		/* Don't have the AMD FP5 flip */
-		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
-
-	} else if (ec_config_has_usbc1_retimer_ps8818()) {
-		/*
-		 * Main MUX is FP5, secondary MUX is PS8818
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-
-		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-	}
-}
-
-const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
-	[USBC_PORT_C0] = {
-		.enable_gpio = IOEX_USB_C0_DATA_EN,
-		.dp_enable_gpio = GPIO_USB_C0_IN_HPD,
-	},
-	[USBC_PORT_C1] = {
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
-
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
-	},
-	[USBC_PORT_C1] = {
-		/* Filled in dynamically at startup */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/*****************************************************************************
- * Use FW_CONFIG to set correct configuration.
- */
-
-int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-
-static void setup_v0_charger(void)
-{
-	chg_chips[0].i2c_port = I2C_PORT_CHARGER_V0;
-}
-/*
- * Use HOOK_PRIO_INIT_I2C so we re-map before charger_chips_init()
- * talks to the charger.
- */
-DECLARE_HOOK(HOOK_INIT, setup_v0_charger, HOOK_PRIO_INIT_I2C);
-
-static void setup_fw_config(void)
-{
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-
-	setup_mux();
-
-	if (ec_config_has_mst_hub_rtd2141b())
-		ioex_enable_interrupt(IOEX_MST_HPD_OUT);
-
-	if (ec_config_has_hdmi_conn_hpd())
-		ioex_enable_interrupt(IOEX_HDMI_CONN_HPD_3V3_DB);
-}
-/* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-/*****************************************************************************
- * Fan
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3000,
-	.rpm_start = 3000,
-	.rpm_max = 4900,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-	case TEMP_SENSOR_SOC:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_SOC;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_SOC,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(92),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_CHARGER] = thermal_thermistor;
-	thermal_params[TEMP_SENSOR_SOC] = thermal_thermistor;
-	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
-}
-DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * MST hub
- */
-
-static void mst_hpd_handler(void)
-{
-	int hpd = 0;
-
-	/*
-	 * Ensure level on GPIO_DP1_HPD matches IOEX_MST_HPD_OUT, in case
-	 * we got out of sync.
-	 */
-	ioex_get_level(IOEX_MST_HPD_OUT, &hpd);
-	gpio_set_level(GPIO_DP1_HPD, hpd);
-	ccprints("MST HPD %d", hpd);
-}
-DECLARE_DEFERRED(mst_hpd_handler);
-
-void mst_hpd_interrupt(enum ioex_signal signal)
-{
-	/*
-	 * Goal is to pass HPD through from DB OPT3 MST hub to AP's DP1.
-	 * Immediately invert GPIO_DP1_HPD, to pass through the edge on
-	 * IOEX_MST_HPD_OUT. Then check level after 2 msec debounce.
-	 */
-	int hpd = !gpio_get_level(GPIO_DP1_HPD);
-
-	gpio_set_level(GPIO_DP1_HPD, hpd);
-	hook_call_deferred(&mst_hpd_handler_data, (2 * MSEC));
-}
-
-static void hdmi_hpd_handler(void)
-{
-	int hpd = 0;
-
-	/* Pass HPD through from DB OPT1 HDMI connector to AP's DP1. */
-	ioex_get_level(IOEX_HDMI_CONN_HPD_3V3_DB, &hpd);
-	gpio_set_level(GPIO_DP1_HPD, hpd);
-	ccprints("HDMI HPD %d", hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-void hdmi_hpd_interrupt(enum ioex_signal signal)
-{
-	/* Debounce for 2 msec. */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
diff --git a/board/trembyle/board.h b/board/trembyle/board.h
deleted file mode 100644
index bfbd829ac1..0000000000
--- a/board/trembyle/board.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_TREMBYLE
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USBC_RETIMER_PI3DPX1207
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_AP18F4M,
-	BATTERY_TYPE_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * TREMBYLE_MB_USBAC
- *	USB-A0  Speed: 10 Gbps
- *		Retimer: PS8811
- *	USB-C0  Speed: 10 Gbps
- *		Retimer: PI3DPX1207
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	TREMBYLE_MB_USBAC = 0,
-};
-
-/**
- * TREMBYLE_DB_T_OPT1_USBAC_HMDI
- *	USB-A1  Speed: 10 Gbps
- *		Retimer: PS8811
- *	USB-C1  Speed: 10 Gbps
- *		Retimer: PS8818
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- *
- * TREMBYLE_DB_T_OPT2_USBAC
- *	USB-A1  Speed: 10 Gbps
- *		Retimer: PS8811
- *	USB-C1  Speed: 10 Gbps
- *		Retimer: PS8802
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: no
- *		Retimer: none
- *		MST Hub: none
- *
- * TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB
- *	USB-A1  Speed: 10 Gbps
- *		Retimer: PS8811
- *	USB-C1  Speed: 10 Gbps
- *		Retimer: PS8802
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: none
- *		MST Hub: RTD2141B
- */
-enum ec_cfg_usb_db_type {
-	TREMBYLE_DB_T_OPT1_USBAC_HMDI = 0,
-	TREMBYLE_DB_T_OPT2_USBAC = 1,
-	TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB = 2,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(TREMBYLE_DB_T_OPT2_USBAC) | \
-			 BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_usbc1_retimer_ps8802(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
-}
-
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_usbc1_retimer_ps8818(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_mst_hub_rtd2141b(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
-}
-
-#define HAS_HDMI_CONN_HPD \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_hdmi_conn_hpd(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
-}
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8802()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
-
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
-extern const struct usb_mux usbc1_ps8818;
-extern struct usb_mux usbc1_amd_fp5_usb_mux;
-
-void hdmi_hpd_interrupt(enum ioex_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/trembyle/build.mk b/board/trembyle/build.mk
deleted file mode 100644
index 4ca0cbd96f..0000000000
--- a/board/trembyle/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/trembyle/ec.tasklist b/board/trembyle/ec.tasklist
deleted file mode 100644
index 41b83cf4f3..0000000000
--- a/board/trembyle/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/trembyle/gpio.inc b/board/trembyle/gpio.inc
deleted file mode 100644
index 6cc3e6fe09..0000000000
--- a/board/trembyle/gpio.inc
+++ /dev/null
@@ -1,141 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	bmi160_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-GPIO(EN_PWR_TOUCHPAD_PS2,	PIN(C, 2), GPIO_INPUT)				/* Touchpad Power */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, 	sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-IOEX_INT(HDMI_CONN_HPD_3V3_DB,	EXPIN(USBC_PORT_C1, 1, 0), GPIO_INT_BOTH,	hdmi_hpd_interrupt)
-IOEX_INT(MST_HPD_OUT,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_INT_BOTH,	mst_hpd_interrupt)
-
-IOEX(USB_A0_RETIMER_EN,		EXPIN(USBC_PORT_C0, 0, 0), GPIO_OUT_LOW)	/* A0 Retimer Enable */
-IOEX(USB_A0_RETIMER_RST,	EXPIN(USBC_PORT_C0, 0, 1), GPIO_OUT_LOW)	/* A0 Retimer Reset */
-IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)	/* A1 Retimer Enable */
-IOEX(USB_A1_RETIMER_RST_DB,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)	/* A1 Retimer Reset */
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_HIGH)	/* HDMI Retimer Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-IOEX(EN_USB_A1_5V_DB,		EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
-IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(C, BIT(3)), 0, MODULE_PWM, 0)				/* PWM0 LED */
-ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/trembyle/led.c b/board/trembyle/led.c
deleted file mode 100644
index 3e2d195a06..0000000000
--- a/board/trembyle/led.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 100;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,           3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,           LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_RED] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_RED] != 0)
-		led_set_color_battery(EC_LED_COLOR_RED);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
diff --git a/board/trembyle/vif_override.xml b/board/trembyle/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/trembyle/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/trogdor/battery.c b/board/trogdor/battery.c
deleted file mode 100644
index e95735eda7..0000000000
--- a/board/trogdor/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all trogdor battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* AP16L5J */
-	[BATTERY_AP16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8800,
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP16L5J;
diff --git a/board/trogdor/board.c b/board/trogdor/board.c
deleted file mode 100644
index 0261ada9ff..0000000000
--- a/board/trogdor/board.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#include "gpio_list.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Use 80 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/*
-	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
-	 * as it still uses the legacy location (KSO_01/KSI_00).
-	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-};
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable interrupt for BMI160 sensor */
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Mutexes */
-static struct mutex g_base_mutex;
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
diff --git a/board/trogdor/board.h b/board/trogdor/board.h
deleted file mode 100644
index 346b135ea4..0000000000
--- a/board/trogdor/board.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-
-#define CONFIG_PWM_KBLIGHT
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* USB-A */
-#define USB_PORT_COUNT 1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* Sensors */
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_LID_ANGLE_UPDATE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_ACOK_OD
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_SWITCHCAP_PG GPIO_SWITCHCAP_GPIO_1
-#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_AP16L5J,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/trogdor/build.mk b/board/trogdor/build.mk
deleted file mode 100644
index 7fe4452669..0000000000
--- a/board/trogdor/build.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y+=battery.o
-board-y+=board.o
-board-y+=hibernate.o
-board-y+=led.o
-board-y+=switchcap.o
-board-y+=usbc_config.o
diff --git a/board/trogdor/ec.tasklist b/board/trogdor/ec.tasklist
deleted file mode 100644
index eb14fab204..0000000000
--- a/board/trogdor/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/trogdor/gpio.inc b/board/trogdor/gpio.inc
deleted file mode 100644
index aaac15839e..0000000000
--- a/board/trogdor/gpio.inc
+++ /dev/null
@@ -1,187 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_interrupt)
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-/* Sensor interrupts */
-GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
-
-/*
- * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
- * the PSL mode. This GPIO does nothing now. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PMIC_RESIN_L,          PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON,          PIN(D, 5), GPIO_OUT_LOW)   /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Sensors */
-GPIO(LID_ACCEL_INT_L,       PIN(5, 6), GPIO_INPUT)     /* Lid accel sensor interrupt */
-/* Control the gate for trackpad IRQ. High closes the gate.
- * This is always set low so that the OS can manage the trackpad. */
-GPIO(TRACKPAD_INT_GATE,     PIN(7, 4), GPIO_OUT_LOW)
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_OUT_HIGH)  /* Port-0 TCPC chip reset */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_OUT_HIGH)  /* Port-1 TCPC chip reset */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* USB-A */
-GPIO(EN_USB_A_5V,           PIN(8, 6), GPIO_OUT_LOW)
-GPIO(USB_A_CDP_ILIM_EN_L,   PIN(7, 5), GPIO_OUT_HIGH)  /* H:CDP, L:SDP. Only one USB-A port, always CDP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_Y_C0,       PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C0,       PIN(C, 0), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_Y_C1,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_W_C1,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(KB_BL_PWM,             PIN(8, 0), GPIO_INPUT)     /* PWM3 */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Switchcap */
-/*
- * GPIO0 is configured as PVC_PG. When the chip in power down mode, it outputs
- * high-Z. Set pull-down to avoid floating.
- */
-GPIO(SWITCHCAP_GPIO_1,      PIN(E, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* Switchcap GPIO0 */
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(3, 7))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(6, 2))
-UNUSED(PIN(0, 4))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 0))
-UNUSED(PIN(D, 3))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)             /* PWM3 (GPIO80) - KB_BL_PWM */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-
-/* Keyboard */
-#define GPIO_KB_INPUT           (GPIO_INPUT | GPIO_PULL_UP)
-#define GPIO_KB_OUTPUT          (GPIO_ODR_HIGH)
-#define GPIO_KB_OUTPUT_COL2     (GPIO_OUT_LOW)
-
-/* Keyboard alternate functions */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO10 (GPIO07), KSO11 (GPIO06), KSO12 (GPIO05) */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO03 (GPIO16), KSO04 (GPIO15), KSO05 (GPIO14), KSO06 (GPIO13), KSO07 (GPIO12), KSO08 (GPIO11), KSO09 (GPIO10) */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)  /* KSO00 (GPIO21), KSO01 (GPIO20) */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI2 (GPIO27), KSI3 (GPIO26), KSI4 (GPIO25), KSI5 (GPIO24), KSI6 (GPIO23), KSI7 (GPIO22) */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)   /* KSI0 (GPIO31), KSI1 (GPIO30) */
-GPIO(EC_KSO_02_INV,       PIN(1, 7), GPIO_KB_OUTPUT_COL2)              /* KSO02 (GPIO17) */
diff --git a/board/trogdor/hibernate.c b/board/trogdor/hibernate.c
deleted file mode 100644
index 504a295463..0000000000
--- a/board/trogdor/hibernate.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-
-void board_hibernate(void)
-{
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-}
diff --git a/board/trogdor/led.c b/board/trogdor/led.c
deleted file mode 100644
index 3af5776e12..0000000000
--- a/board/trogdor/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_LEFT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_LEFT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/board/trogdor/switchcap.c b/board/trogdor/switchcap.c
deleted file mode 100644
index 16b0db6ef6..0000000000
--- a/board/trogdor/switchcap.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "power/qcom.h"
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_PG);
-}
diff --git a/board/trogdor/usbc_config.c b/board/trogdor/usbc_config.c
deleted file mode 100644
index dddc1d87a6..0000000000
--- a/board/trogdor/usbc_config.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board-specific USB-C configuration */
-
-#include "bc12/pi3usb9201_public.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ppc/sn5s330_public.h"
-#include "system.h"
-#include "tcpm/ps8xxx_public.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_config.h"
-#include "usb_mux.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Initialize board USC-C things */
-static void board_init_usbc(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/board/trogdor/usbc_config.h b/board/trogdor/usbc_config.h
deleted file mode 100644
index 75adf93b3c..0000000000
--- a/board/trogdor/usbc_config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trogdor board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-#include "gpio.h"
-
-void tcpc_alert_event(enum gpio_signal signal);
-void usb0_evt(enum gpio_signal signal);
-void usb1_evt(enum gpio_signal signal);
-void usba_oc_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/trogdor/vif_override.xml b/board/trogdor/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/trogdor/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/trondo/battery.c b/board/trondo/battery.c
deleted file mode 100644
index 9b356a8efd..0000000000
--- a/board/trondo/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/trondo/board.c b/board/trondo/board.c
deleted file mode 100644
index 0493c603e0..0000000000
--- a/board/trondo/board.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Trondo if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_PASSIVE,
-};
-
-static void board_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	/* Routing length exceeds 205mm prior to connection to re-timer */
-	if (port == USBC_PORT_C1)
-		return TBT_SS_U32_GEN1_GEN2;
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	/*
-	 * On Proto-1 only Port 1 supports TBT & USB4
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return port == USBC_PORT_C1;
-}
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2400,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/* Run at a higher frequency than the color PWM signals to avoid
-		 * timing-based color shifts.
-		 */
-		.freq = 4800,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-void board_reset_pd_mcu(void)
-{
-	/* TODO(b/159025023): Trondo: check USB PD reset operation */
-}
-
-__override void board_cbi_init(void)
-{
-	/* TODO(b/159025023): Trondo: check FW_CONFIG fields for USB DB type */
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/trondo/board.h b/board/trondo/board.h
deleted file mode 100644
index ea0453ee82..0000000000
--- a/board/trondo/board.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-/* Reduce flash usage */
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-/*
- * TODO (b/149858568): remove CONFIG_BUTTONS_RUNTIME_CONFIG once board ID=0
- * support is stripped.
- */
-#define CONFIG_BUTTONS_RUNTIME_CONFIG
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/trondo/build.mk b/board/trondo/build.mk
deleted file mode 100644
index b78172d3cf..0000000000
--- a/board/trondo/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/trondo/ec.tasklist b/board/trondo/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/trondo/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/trondo/gpio.inc b/board/trondo/gpio.inc
deleted file mode 100644
index eee76df08b..0000000000
--- a/board/trondo/gpio.inc
+++ /dev/null
@@ -1,160 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(DSW_PWROK,            PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-/* The EC does not buffer this signal on Volteer. */
-UNIMPLEMENTED(PCH_DSW_PWROK)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Physical HPD pins are not needed on EC as these are configured by PMC */
-GPIO(USB_C0_DP_HPD,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_DP_HPD,		PIN(7, 0), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/trondo/led.c b/board/trondo/led.c
deleted file mode 100644
index 981469af53..0000000000
--- a/board/trondo/led.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-struct pwm_led_color_map led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
-
-/* Illuminates the LED on the side of the active charging port. If not charging,
- * illuminates both LEDs.
- */
-static void led_set_charge_port_tick(void)
-{
-	int port;
-	int side_select_duty;
-
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case 0:
-		side_select_duty = 100;
-		break;
-	case 1:
-		side_select_duty = 0;
-		break;
-	default:
-		side_select_duty = 50;
-	}
-
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
-}
-DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/trondo/sensors.c b/board/trondo/sensors.c
deleted file mode 100644
index e9169abaae..0000000000
--- a/board/trondo/sensors.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-/* TODO: b/146144170 - the accelerometer is on the motherboard for proto1
- * for testing. Once the sensor moves to the lid, the rotation matrix needs
- * to be updated for correct behavior.
- */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/trondo/vif_override.xml b/board/trondo/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/trondo/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/twinkie/board.c b/board/twinkie/board.c
deleted file mode 100644
index 6572f27281..0000000000
--- a/board/twinkie/board.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Twinkie dongle configuration */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_version.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ina2xx.h"
-#include "registers.h"
-#include "task.h"
-#include "usb_descriptor.h"
-#include "util.h"
-
-void cc2_event(enum gpio_signal signal)
-{
-	ccprintf("INA!\n");
-}
-
-void vbus_event(enum gpio_signal signal)
-{
-	ccprintf("INA!\n");
-}
-
-#include "gpio_list.h"
-
-/* Initialize board. */
-void board_config_pre_init(void)
-{
-	/* enable SYSCFG clock */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Remap USART DMA to match the USART driver and TIM2 DMA */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
-			   |  BIT(29);/* Remap TIM2 DMA */
-	/* 40 MHz pin speed on UART PA9/PA10 */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
-	/* 40 MHz pin speed on TX clock out PB9 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0000;
-}
-
-static void board_init(void)
-{
-	/* Enable interrupts for INAs. */
-	gpio_enable_interrupt(GPIO_CC2_ALERT_L);
-	gpio_enable_interrupt(GPIO_VBUS_ALERT_L);
-
-	/* Calibrate INA0 (VBUS) with 1mA/LSB scale */
-	ina2xx_init(0, 0x8000, INA2XX_CALIB_1MA(15 /*mOhm*/));
-	/* Disable INA1 (VCONN2) to avoid leaking current */
-	ina2xx_init(1, 0, INA2XX_CALIB_1MA(15 /*mOhm*/));
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(3)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"master", I2C_PORT_MASTER, 100, GPIO_I2C_SCL, GPIO_I2C_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const void * const usb_strings[] = {
-	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT] = USB_STRING_DESC("Twinkie"),
-	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_SNIFFER] = USB_STRING_DESC("USB-PD Sniffer"),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
diff --git a/board/twinkie/board.h b/board/twinkie/board.h
deleted file mode 100644
index 3d601ee979..0000000000
--- a/board/twinkie/board.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Twinkie dongle configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#define CONFIG_UART_CONSOLE 1
-
-/* Optional features */
-#define CONFIG_USB
-#define CONFIG_USB_BOS
-#define CONFIG_USB_CONSOLE
-#define CONFIG_WEBUSB_URL "storage.googleapis.com/webtwinkie.org/tool.html"
-
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_CUSTOM_PDO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_PD_USE_DAC_AS_REF
-#define CONFIG_HW_CRC
-
-#ifndef HAS_TASK_PD_C0 /* PD sniffer mode */
-#undef CONFIG_DMA_DEFAULT_HANDLERS
-#define CONFIG_USB_PD_TX_PHY_ONLY
-/* override the comparator interrupt handler */
-#undef CONFIG_USB_PD_RX_COMP_IRQ
-#endif
-
-#define CONFIG_ADC
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_INA231
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_TASK_PROFILING
-
-/* I2C ports configuration */
-#define I2C_PORT_MASTER 0
-
-/* USB configuration */
-#define CONFIG_USB_PID 0x500A
-/* By default, enable all console messages excepted USB */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_USB))
-
-/*
- * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-void sniffer_init(void);
-
-int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us);
-
-int expect_packet(int pol, uint8_t cmd, uint32_t timeout_us);
-
-uint8_t recording_enable(uint8_t mask);
-
-void trace_packets(void);
-
-void set_trace_mode(int mode);
-
-/* Timer selection */
-#define TIM_CLOCK_MSB  3
-#define TIM_CLOCK_LSB 15
-#define TIM_ADC       16
-
-#include "gpio_signal.h"
-
-/* ADC signal */
-enum adc_channel {
-	ADC_CH_CC1_PD = 0,
-	ADC_CH_CC2_PD,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_SNIFFER,
-	USB_STR_CONSOLE_NAME,
-
-	USB_STR_COUNT
-};
-
-/* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
-
-/* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-/* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
-
-#endif /* !__ASSEMBLER__ */
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE 0
-#define USB_IFACE_VENDOR  1
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_CONSOLE   1
-
-/*
- * Endpoint 2 is missing because the console used to use two bidirectional
- * endpoints.  It now uses a single bidirectional endpoint relying on the
- * direction bit as an additional bit identifying the endpoint used.  It is
- * safe to reallocate endpoint 2 in the future.
- */
-
-#ifdef HAS_TASK_SNIFFER
-#define USB_EP_SNIFFER   3
-#define USB_EP_COUNT     4
-#define USB_IFACE_COUNT  2
-#else
-#define USB_EP_COUNT     2
-/* No IFACE_VENDOR for the sniffer */
-#define USB_IFACE_COUNT  1
-#endif
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/twinkie/build.mk b/board/twinkie/build.mk
deleted file mode 100644
index 6fc2067d8f..0000000000
--- a/board/twinkie/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F072B
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f07x
-
-board-y=board.o usb_pd_policy.o injector.o simpletrace.o
-board-$(HAS_TASK_SNIFFER)+=sniffer.o
diff --git a/board/twinkie/ec.tasklist b/board/twinkie/ec.tasklist
deleted file mode 100644
index 600df47c60..0000000000
--- a/board/twinkie/ec.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RO(SNIFFER, sniffer_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/twinkie/gpio.inc b/board/twinkie/gpio.inc
deleted file mode 100644
index 551cb73748..0000000000
--- a/board/twinkie/gpio.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(CC2_ALERT_L,  PIN(A, 7),  GPIO_INT_BOTH | GPIO_PULL_UP, cc2_event)
-GPIO_INT(VBUS_ALERT_L, PIN(B, 2),  GPIO_INT_BOTH | GPIO_PULL_UP, vbus_event)
-
-GPIO(CC1_EN,       PIN(A, 0),  GPIO_OUT_HIGH)
-GPIO(CC1_PD,       PIN(A, 1),  GPIO_ANALOG)
-GPIO(CC2_EN,       PIN(A, 2),  GPIO_OUT_HIGH)
-GPIO(CC2_PD,       PIN(A, 3),  GPIO_ANALOG)
-GPIO(DAC,          PIN(A, 4),  GPIO_ANALOG)
-GPIO(CC2_TX_DATA,  PIN(A, 6),  GPIO_OUT_LOW)
-
-GPIO(CC1_RA,       PIN(A, 8),  GPIO_ODR_HIGH)
-GPIO(USB_DM,       PIN(A, 11), GPIO_ANALOG)
-GPIO(USB_DP,       PIN(A, 12), GPIO_ANALOG)
-GPIO(CC1_RPUSB,    PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(CC1_RP1A5,    PIN(A, 14), GPIO_ODR_HIGH)
-GPIO(CC1_RP3A0,    PIN(A, 15), GPIO_ODR_HIGH)
-GPIO(CC2_RPUSB,    PIN(B, 0),  GPIO_ODR_HIGH)
-
-GPIO(CC1_TX_EN,    PIN(B, 1),  GPIO_OUT_LOW)
-GPIO(CC2_TX_EN,    PIN(B, 3),  GPIO_OUT_LOW)
-GPIO(CC1_TX_DATA,  PIN(B, 4),  GPIO_OUT_LOW)
-GPIO(CC1_RD,       PIN(B, 5),  GPIO_ODR_HIGH)
-GPIO(I2C_SCL,      PIN(B, 6),  GPIO_INPUT)
-GPIO(I2C_SDA,      PIN(B, 7),  GPIO_INPUT)
-GPIO(CC2_RD,       PIN(B, 8),  GPIO_ODR_HIGH)
-GPIO(LED_G_L,      PIN(B, 11), GPIO_ODR_HIGH)
-GPIO(LED_R_L,      PIN(B, 13), GPIO_ODR_HIGH)
-GPIO(LED_B_L,      PIN(B, 14), GPIO_ODR_HIGH)
-GPIO(CC2_RA,       PIN(B, 15), GPIO_ODR_HIGH)
-GPIO(CC2_RP1A5,    PIN(C, 14), GPIO_ODR_HIGH)
-GPIO(CC2_RP3A0,    PIN(C, 15), GPIO_ODR_HIGH)
-
-/* Unimplemented signals which we need to emulate for now */
-UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
-
-ALTERNATE(PIN_MASK(A, 0x0020), 0, MODULE_USB_PD, 0)            /* SPI1: SCK(PA5) */
-ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0)            /* TIM17_CH1: PB9 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 1, MODULE_I2C,    0)            /* I2C1 MASTER:PB6/7 */
diff --git a/board/twinkie/injector.c b/board/twinkie/injector.c
deleted file mode 100644
index cae1d3557f..0000000000
--- a/board/twinkie/injector.c
+++ /dev/null
@@ -1,603 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "injector.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* FSM command/data buffer */
-static uint32_t inj_cmds[INJ_CMD_COUNT];
-
-/* Current polarity for sending operations */
-static enum inj_pol inj_polarity = INJ_POL_CC1;
-
-/*
- * CCx Resistors control definition
- *
- * Resistor control GPIOs :
- * CC1_RA       A8
- * CC1_RPUSB    A13
- * CC1_RP1A5    A14
- * CC1_RP3A0    A15
- * CC2_RPUSB    B0
- * CC1_RD       B5
- * CC2_RD       B8
- * CC2_RA       B15
- * CC2_RP1A5    C14
- * CC2_RP3A0    C15
- */
-static const struct res_cfg {
-	const char *name;
-	struct config {
-		enum gpio_signal signal;
-		uint32_t flags;
-	} cfgs[2];
-} res_cfg[] = {
-	[INJ_RES_NONE]  = {"NONE"},
-	[INJ_RES_RA]    = {"RA", {{GPIO_CC1_RA, GPIO_ODR_LOW},
-				  {GPIO_CC2_RA, GPIO_ODR_LOW} } },
-	[INJ_RES_RD]    = {"RD", {{GPIO_CC1_RD, GPIO_ODR_LOW},
-				  {GPIO_CC2_RD, GPIO_ODR_LOW} } },
-	[INJ_RES_RPUSB] = {"RPUSB", {{GPIO_CC1_RPUSB, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RPUSB, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP1A5] = {"RP1A5", {{GPIO_CC1_RP1A5, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP1A5, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP3A0] = {"RP3A0", {{GPIO_CC1_RP3A0, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP3A0, GPIO_OUT_HIGH} } },
-};
-
-#define CC_RA(cc)  (cc < PD_SRC_RD_THRESHOLD)
-#define CC_RD(cc) ((cc > PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
-#define GET_POLARITY(cc1, cc2) (CC_RD(cc2) || CC_RA(cc1))
-
-#ifdef HAS_TASK_SNIFFER
-/* we don't have the default DMA handlers */
-void dma_event_interrupt_channel_3(void)
-{
-	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH3)) {
-		dma_clear_isr(STM32_DMAC_CH3);
-		task_wake(TASK_ID_CONSOLE);
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_3, 3);
-#endif
-
-static void twinkie_init(void)
-{
-	/* configure TX clock pins */
-	gpio_config_module(MODULE_USB_PD, 1);
-	/* Initialize physical layer */
-	pd_hw_init(0, PD_ROLE_SINK);
-}
-DECLARE_HOOK(HOOK_INIT, twinkie_init, HOOK_PRIO_DEFAULT);
-
-/* ------ Helper functions ------ */
-
-static inline int disable_tracing_save(void)
-{
-	int tr_enabled = STM32_EXTI_IMR & EXTI_COMP_MASK(0);
-
-	if (tr_enabled)
-		pd_rx_disable_monitoring(0);
-	return tr_enabled;
-}
-
-static inline void enable_tracing_ifneeded(int flag)
-{
-	if (flag)
-		pd_rx_enable_monitoring(0);
-}
-
-static int send_message(int polarity, uint16_t header,
-			uint8_t cnt, const uint32_t *data)
-{
-	int bit_len;
-
-	/* Don't get preempted by the tracing */
-	int flag = disable_tracing_save();
-
-	bit_len = prepare_message(0, header, cnt, data);
-	/* Transmit the packet */
-	pd_start_tx(0, polarity, bit_len);
-	pd_tx_done(0, polarity);
-
-	enable_tracing_ifneeded(flag);
-
-	return bit_len;
-}
-
-static int send_hrst(int polarity)
-{
-	int off;
-	int flag = disable_tracing_save();
-	/* 64-bit preamble */
-	off = pd_write_preamble(0);
-	/* Hard-Reset: 3x RST-1 + 1x RST-2 */
-	off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
-	off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
-	off = pd_write_sym(0, off, 0b0011010101); /* RST-1 = 00111 */
-	off = pd_write_sym(0, off, 0b0101001101); /* RST-2 = 11001 */
-	/* Ensure that we have a final edge */
-	off = pd_write_last_edge(0, off);
-	/* Transmit the packet */
-	pd_start_tx(0, polarity, off);
-	pd_tx_done(0, polarity);
-	enable_tracing_ifneeded(flag);
-
-	return off;
-}
-
-static void set_resistor(int pol, enum inj_res res)
-{
-	/* reset everything on one CC to high impedance */
-	gpio_set_flags(res_cfg[INJ_RES_RA].cfgs[pol].signal, GPIO_ODR_HIGH);
-	gpio_set_flags(res_cfg[INJ_RES_RD].cfgs[pol].signal, GPIO_ODR_HIGH);
-	gpio_set_flags(res_cfg[INJ_RES_RPUSB].cfgs[pol].signal, GPIO_ODR_HIGH);
-	gpio_set_flags(res_cfg[INJ_RES_RP1A5].cfgs[pol].signal, GPIO_ODR_HIGH);
-	gpio_set_flags(res_cfg[INJ_RES_RP3A0].cfgs[pol].signal, GPIO_ODR_HIGH);
-
-	/* connect the resistor if needed */
-	if (res != INJ_RES_NONE)
-		gpio_set_flags(res_cfg[res].cfgs[pol].signal,
-			       res_cfg[res].cfgs[pol].flags);
-}
-
-static enum inj_pol guess_polarity(enum inj_pol pol)
-{
-	int cc1_volt, cc2_volt;
-	/* polarity forced by the user */
-	if (pol == INJ_POL_CC1 || pol == INJ_POL_CC2)
-		return pol;
-	/* Auto-detection */
-	cc1_volt = pd_adc_read(0, 0);
-	cc2_volt = pd_adc_read(0, 1);
-	return GET_POLARITY(cc1_volt, cc2_volt);
-}
-
-/* ------ FSM commands ------ */
-
-static void fsm_send(uint32_t w)
-{
-	uint16_t header = INJ_ARG0(w);
-	int idx = INJ_ARG1(w);
-	uint8_t cnt = INJ_ARG2(w);
-
-	/* Buffer overflow */
-	if (idx > INJ_CMD_COUNT)
-		return;
-
-	send_message(inj_polarity, header, cnt, inj_cmds + idx);
-}
-
-static void fsm_wave(uint32_t w)
-{
-	uint16_t bit_len = INJ_ARG0(w);
-	int idx = INJ_ARG1(w);
-	int off = 0;
-	int nbwords = DIV_ROUND_UP(bit_len, 32);
-	int i;
-	int flag;
-
-	/* Buffer overflow */
-	if (idx + nbwords > INJ_CMD_COUNT)
-		return;
-
-	flag = disable_tracing_save();
-
-	for (i = idx; i < idx + nbwords; i++)
-		off = encode_word(0, off, inj_cmds[i]);
-	/* Ensure that we have a final edge */
-	off = pd_write_last_edge(0, bit_len);
-	/* Transmit the packet */
-	pd_start_tx(0, inj_polarity, off);
-	pd_tx_done(0, inj_polarity);
-	enable_tracing_ifneeded(flag);
-}
-
-static void fsm_wait(uint32_t w)
-{
-#ifdef HAS_TASK_SNIFFER
-	uint32_t timeout_ms = INJ_ARG0(w);
-	uint32_t min_edges = INJ_ARG12(w);
-
-	wait_packet(inj_polarity,  min_edges, timeout_ms * 1000);
-#endif
-}
-
-static void fsm_expect(uint32_t w)
-{
-	uint32_t timeout_ms = INJ_ARG0(w);
-	uint8_t cmd = INJ_ARG2(w);
-
-	expect_packet(inj_polarity,  cmd, timeout_ms * 1000);
-}
-static void fsm_get(uint32_t w)
-{
-	int store_idx = INJ_ARG0(w);
-	int param_idx = INJ_ARG1(w);
-	uint32_t *store_ptr = inj_cmds + store_idx;
-
-	/* Buffer overflow */
-	if (store_idx > INJ_CMD_COUNT)
-		return;
-
-	switch (param_idx) {
-	case INJ_GET_CC:
-		*store_ptr = pd_adc_read(0, 0) | (pd_adc_read(0, 1) << 16);
-		break;
-	case INJ_GET_VBUS:
-		*store_ptr = (ina2xx_get_voltage(0) & 0xffff) |
-			 ((ina2xx_get_current(0) & 0xffff) << 16);
-		break;
-	case INJ_GET_VCONN:
-		*store_ptr = (ina2xx_get_voltage(1) & 0xffff) |
-			 ((ina2xx_get_current(1) & 0xffff) << 16);
-		break;
-	case INJ_GET_POLARITY:
-		*store_ptr = inj_polarity;
-		break;
-	default:
-		/* Do nothing */
-		break;
-	}
-}
-
-static void fsm_set(uint32_t w)
-{
-	int val = INJ_ARG0(w);
-	int idx = INJ_ARG1(w);
-
-	switch (idx) {
-	case INJ_SET_RESISTOR1:
-	case INJ_SET_RESISTOR2:
-		set_resistor(idx - INJ_SET_RESISTOR1, val);
-		break;
-	case INJ_SET_RECORD:
-#ifdef HAS_TASK_SNIFFER
-		recording_enable(val);
-#endif
-		break;
-	case INJ_SET_TX_SPEED:
-		pd_set_clock(0, val * 1000);
-		break;
-	case INJ_SET_RX_THRESH:
-		/* set DAC voltage (Vref = 3.3V) */
-		STM32_DAC_DHR12RD = val * 4096 / 3300;
-		break;
-	case INJ_SET_POLARITY:
-		inj_polarity = guess_polarity(val);
-		break;
-	case INJ_SET_TRACE:
-		set_trace_mode(val);
-		break;
-	default:
-		/* Do nothing */
-		break;
-	}
-}
-
-static int fsm_run(int index)
-{
-	while (index < INJ_CMD_COUNT) {
-		uint32_t w = inj_cmds[index];
-		int cmd = INJ_CMD(w);
-		switch (cmd) {
-		case INJ_CMD_END:
-			return index;
-		case INJ_CMD_SEND:
-			fsm_send(w);
-			break;
-		case INJ_CMD_WAVE:
-			fsm_wave(w);
-			break;
-		case INJ_CMD_HRST:
-			send_hrst(inj_polarity);
-			break;
-		case INJ_CMD_WAIT:
-			fsm_wait(w);
-			break;
-		case INJ_CMD_GET:
-			fsm_get(w);
-			break;
-		case INJ_CMD_SET:
-			fsm_set(w);
-			break;
-		case INJ_CMD_JUMP:
-			index = INJ_ARG0(w);
-			continue; /* do not increment index */
-		case INJ_CMD_EXPCT:
-			fsm_expect(w);
-			break;
-		case INJ_CMD_NOP:
-		default:
-			/* Do nothing */
-			break;
-		}
-		index += 1;
-		watchdog_reload();
-	}
-	return index;
-}
-
-/* ------ Console commands ------ */
-
-static int hex8tou32(char *str, uint32_t *val)
-{
-	char *ptr = str;
-	uint32_t tmp = 0;
-
-	while (*ptr) {
-		char c = *ptr++;
-		if (c >= '0' && c <= '9')
-			tmp = (tmp << 4) + (c - '0');
-		else if (c >= 'A' && c <= 'F')
-			tmp = (tmp << 4) + (c - 'A' + 10);
-		else if (c >= 'a' && c <= 'f')
-			tmp = (tmp << 4) + (c - 'a' + 10);
-		else
-			return EC_ERROR_INVAL;
-	}
-	if (ptr != str + 8)
-		return EC_ERROR_INVAL;
-	*val = tmp;
-	return EC_SUCCESS;
-}
-
-static int cmd_fsm(int argc, char **argv)
-{
-	int index;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM2;
-
-	index = strtoi(argv[0], &e, 10);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	index = fsm_run(index);
-	ccprintf("FSM Done %d\n", index);
-
-	return EC_SUCCESS;
-}
-
-
-static int cmd_send(int argc, char **argv)
-{
-	int pol, cnt, i;
-	uint16_t header;
-	uint32_t data[VDO_MAX_SIZE];
-	char *e;
-	int bit_len;
-
-	cnt = argc - 2;
-	if (argc < 2 || cnt > VDO_MAX_SIZE)
-		return EC_ERROR_PARAM_COUNT;
-
-	pol = strtoi(argv[0], &e, 10) - 1;
-	if (*e || pol > 1 || pol < 0)
-		return EC_ERROR_PARAM2;
-	header = strtoi(argv[1], &e, 16);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+2], data + i))
-			return EC_ERROR_INVAL;
-
-	bit_len = send_message(pol, header, cnt, data);
-	ccprintf("Sent CC%d %04x + %d = %d\n", pol + 1, header, cnt, bit_len);
-
-	return EC_SUCCESS;
-}
-
-static int cmd_cc_level(int argc, char **argv)
-{
-	ccprintf("CC1 = %d mV ; CC2 = %d mV\n",
-		pd_adc_read(0, 0), pd_adc_read(0, 1));
-
-	return EC_SUCCESS;
-}
-
-static int cmd_resistor(int argc, char **argv)
-{
-	int p, r;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	for (p = 0; p < 2; p++) {
-		int is_set = 0;
-		for (r = 0; r < ARRAY_SIZE(res_cfg); r++)
-			if (strcasecmp(res_cfg[r].name, argv[p]) == 0) {
-				set_resistor(p, r);
-				is_set = 1;
-				break;
-			}
-		/* Unknown name : set to No resistor */
-		if (!is_set)
-			set_resistor(p, INJ_RES_NONE);
-	}
-	return EC_SUCCESS;
-}
-
-static int cmd_tx_clock(int argc, char **argv)
-{
-	int freq;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM2;
-
-	freq = strtoi(argv[0], &e, 10);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	pd_set_clock(0, freq);
-	ccprintf("TX frequency = %d Hz\n", freq);
-
-	return EC_SUCCESS;
-}
-
-static int cmd_rx_threshold(int argc, char **argv)
-{
-	int mv;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM2;
-
-	mv = strtoi(argv[0], &e, 10);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	/* set DAC voltage (Vref = 3.3V) */
-	STM32_DAC_DHR12RD = mv * 4096 / 3300;
-	ccprintf("RX threshold = %d mV\n", mv);
-
-	return EC_SUCCESS;
-}
-
-static int cmd_ina_dump(int argc, char **argv, int index)
-{
-	if (index == 1) { /* VCONN INA is off by default, switch it on */
-		ina2xx_write(index, INA2XX_REG_CONFIG, 0x4123);
-		/*
-		 * wait for the end of conversion : 2x 1.1ms as defined
-		 * by the Vb and Vsh CT bits in the CONFIG register above.
-		 */
-		udelay(2200);
-	}
-
-	ccprintf("%s = %d mV ; %d mA\n", index == 0 ? "VBUS" : "VCONN",
-		ina2xx_get_voltage(index), ina2xx_get_current(index));
-
-	if (index == 1) /* power off VCONN INA */
-		ina2xx_write(index, INA2XX_REG_CONFIG, 0);
-
-	return EC_SUCCESS;
-}
-
-static int cmd_bufwr(int argc, char **argv)
-{
-	int idx, cnt, i;
-	char *e;
-
-	cnt = argc - 1;
-	if (argc < 2 || cnt > INJ_CMD_COUNT)
-		return EC_ERROR_PARAM_COUNT;
-
-	idx = strtoi(argv[0], &e, 10);
-	if (*e || idx + cnt > INJ_CMD_COUNT)
-		return EC_ERROR_PARAM2;
-
-	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+1], inj_cmds + idx + i))
-			return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-static int cmd_bufrd(int argc, char **argv)
-{
-	int idx, i;
-	int cnt = 1;
-	char *e;
-
-	if (argc < 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	idx = strtoi(argv[0], &e, 10);
-	if (*e || idx > INJ_CMD_COUNT)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 2)
-		cnt = strtoi(argv[1], &e, 10);
-
-	if (*e || idx + cnt > INJ_CMD_COUNT)
-		return EC_ERROR_PARAM3;
-
-	for (i = idx; i < idx + cnt; i++)
-		ccprintf("%08x ", inj_cmds[i]);
-	ccprintf("\n");
-
-	return EC_SUCCESS;
-}
-
-static int cmd_sink(int argc, char **argv)
-{
-	/*
-	 * Jump to the RW section which should contain a firmware acting
-	 * as a USB PD sink
-	 */
-	system_run_image_copy(EC_IMAGE_RW);
-
-	return EC_SUCCESS;
-}
-
-static int cmd_trace(int argc, char **argv)
-{
-	if (argc < 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[0], "on") ||
-	    !strcasecmp(argv[0], "1"))
-		set_trace_mode(TRACE_MODE_ON);
-	else if (!strcasecmp(argv[0], "raw"))
-		set_trace_mode(TRACE_MODE_RAW);
-	else if (!strcasecmp(argv[0], "off") ||
-		 !strcasecmp(argv[0], "0"))
-		set_trace_mode(TRACE_MODE_OFF);
-	else
-		return EC_ERROR_PARAM2;
-
-	return EC_SUCCESS;
-}
-
-static int command_tw(int argc, char **argv)
-{
-	if (!strcasecmp(argv[1], "send"))
-		return cmd_send(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "fsm"))
-		return cmd_fsm(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "bufwr"))
-		return cmd_bufwr(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "bufrd"))
-		return cmd_bufrd(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "cc"))
-		return cmd_cc_level(argc - 2, argv + 2);
-	else if (!strncasecmp(argv[1], "resistor", 3))
-		return cmd_resistor(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "sink"))
-		return cmd_sink(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "trace"))
-		return cmd_trace(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "txclock"))
-		return cmd_tx_clock(argc - 2, argv + 2);
-	else if (!strncasecmp(argv[1], "rxthresh", 8))
-		return cmd_rx_threshold(argc - 2, argv + 2);
-	else if (!strcasecmp(argv[1], "vbus"))
-		return cmd_ina_dump(argc - 2, argv + 2, 0);
-	else if (!strcasecmp(argv[1], "vconn"))
-		return cmd_ina_dump(argc - 2, argv + 2, 1);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(twinkie, command_tw,
-			"[send|fsm|cc|resistor|txclock|rxthresh|vbus|vconn]",
-			"Manual Twinkie tweaking");
diff --git a/board/twinkie/injector.h b/board/twinkie/injector.h
deleted file mode 100644
index 4a33f8ecf0..0000000000
--- a/board/twinkie/injector.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INJECTOR_H
-#define __CROS_EC_INJECTOR_H
-
-/*
- * Finite state machine definition for sending complex sequences
- *
- * the 32-bit commands have the following definition :
- *    [31:28]   [27:0]
- *    Command    arg
- *   INJ_CMD_x
- *                  [27:16]     [15:0]
- *                   arg12       arg0
- *              [27:24] [23:16] [15:0]
- *               arg2     arg1   arg0
- */
-
-/* Macros to extract values from FSM command words */
-#define INJ_CMD(w) ((w) >> 28)
-#define INJ_ARG(w) ((w) & 0x0FFFFFFF)
-#define INJ_ARG0(w) ((w) & 0x0000FFFF)
-#define INJ_ARG1(w) (((w) >> 16) & 0xFF)
-#define INJ_ARG2(w) (((w) >> 24) & 0xF)
-#define INJ_ARG12(w) (((w) >> 16) & 0xFFF)
-
-enum inj_cmd {
-	INJ_CMD_END   = 0x0, /* stop the FSM */
-	INJ_CMD_SEND  = 0x1, /* Send message on CCx */
-			     /* arg0: header arg1/2:payload index/count  */
-	INJ_CMD_WAVE  = 0x2, /* Send arbitrary waveform */
-			     /* stored at index arg1 of len arg0 */
-	INJ_CMD_HRST  = 0x3, /* Send Hard Reset on CCx */
-	INJ_CMD_WAIT  = 0x4, /* Wait for arg12 edges if arg12 != 0 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_GET   = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */
-	INJ_CMD_SET   = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */
-	INJ_CMD_JUMP  = 0x8, /* Jump to index (as arg0) */
-	INJ_CMD_EXPCT = 0xC, /* Expect a packet with command arg2 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_NOP   = 0xF, /* No-Operation */
-};
-
-enum inj_set {
-	INJ_SET_RESISTOR1  = 0, /* CC1 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RESISTOR2  = 1, /* CC2 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RECORD     = 2, /* Recording on/off */
-	INJ_SET_TX_SPEED   = 3, /* TX frequency is arg0 kHz */
-	INJ_SET_RX_THRESH  = 4, /* RX voltage threshold is arg0 mV */
-	INJ_SET_POLARITY   = 5, /* Polarity for other operations (INJ_POL_CC) */
-	INJ_SET_TRACE      = 6, /* Text packet trace on/raw/off */
-};
-
-enum inj_get {
-	INJ_GET_CC       = 0,  /* CC1/CC2 voltages in mV */
-	INJ_GET_VBUS     = 1,  /* VBUS voltage in mV and current in mA */
-	INJ_GET_VCONN    = 2, /* VCONN voltage in mV and current in mA */
-	INJ_GET_POLARITY = 3, /* Current polarity (INJ_POL_CC) */
-};
-
-enum inj_res {
-	INJ_RES_NONE  = 0,
-	INJ_RES_RA    = 1,
-	INJ_RES_RD    = 2,
-	INJ_RES_RPUSB = 3,
-	INJ_RES_RP1A5 = 4,
-	INJ_RES_RP3A0 = 5,
-};
-
-enum inj_pol {
-	INJ_POL_CC1 = 0,
-	INJ_POL_CC2 = 1,
-	INJ_POL_AUTO = 0xffff,
-};
-
-enum trace_mode {
-	TRACE_MODE_OFF = 0,
-	TRACE_MODE_RAW = 1,
-	TRACE_MODE_ON  = 2,
-};
-
-/* Number of words in the FSM command/data buffer  */
-#define INJ_CMD_COUNT 128
-
-#endif /* __CROS_EC_INJECTOR_H */
diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c
deleted file mode 100644
index 9f151f761f..0000000000
--- a/board/twinkie/simpletrace.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "injector.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "util.h"
-
-/* PD packet text tracing state : TRACE_MODE_OFF/RAW/ON */
-int trace_mode;
-
-/* The FSM is waiting for the following command (0 == None) */
-uint8_t expected_cmd;
-
-static const char * const ctrl_msg_name[] = {
-	[0]                      = "RSVD-C0",
-	[PD_CTRL_GOOD_CRC]       = "GOODCRC",
-	[PD_CTRL_GOTO_MIN]       = "GOTOMIN",
-	[PD_CTRL_ACCEPT]         = "ACCEPT",
-	[PD_CTRL_REJECT]         = "REJECT",
-	[PD_CTRL_PING]           = "PING",
-	[PD_CTRL_PS_RDY]         = "PSRDY",
-	[PD_CTRL_GET_SOURCE_CAP] = "GSRCCAP",
-	[PD_CTRL_GET_SINK_CAP]   = "GSNKCAP",
-	[PD_CTRL_DR_SWAP]        = "DRSWAP",
-	[PD_CTRL_PR_SWAP]        = "PRSWAP",
-	[PD_CTRL_VCONN_SWAP]     = "VCONNSW",
-	[PD_CTRL_WAIT]           = "WAIT",
-	[PD_CTRL_SOFT_RESET]     = "SFT-RST",
-	[14]                     = "RSVD-C14",
-	[15]                     = "RSVD-C15",
-};
-
-static const char * const data_msg_name[] = {
-	[0]                      = "RSVD-D0",
-	[PD_DATA_SOURCE_CAP]     = "SRCCAP",
-	[PD_DATA_REQUEST]        = "REQUEST",
-	[PD_DATA_BIST]           = "BIST",
-	[PD_DATA_SINK_CAP]       = "SNKCAP",
-	/* 5-14 Reserved */
-	[PD_DATA_VENDOR_DEF]     = "VDM",
-};
-
-static const char * const svdm_cmd_name[] = {
-	[CMD_DISCOVER_IDENT]     = "DISCID",
-	[CMD_DISCOVER_SVID]	 = "DISCSVID",
-	[CMD_DISCOVER_MODES]	 = "DISCMODE",
-	[CMD_ENTER_MODE]	 = "ENTER",
-	[CMD_EXIT_MODE]		 = "EXIT",
-	[CMD_ATTENTION]		 = "ATTN",
-	[CMD_DP_STATUS]          = "DPSTAT",
-	[CMD_DP_CONFIG]          = "DPCFG",
-};
-
-static const char * const svdm_cmdt_name[] = {
-	[CMDT_INIT]     = "INI",
-	[CMDT_RSP_ACK]  = "ACK",
-	[CMDT_RSP_NAK]  = "NAK",
-	[CMDT_RSP_BUSY] = "BSY",
-};
-
-static void print_pdo(uint32_t word)
-{
-	if ((word & PDO_TYPE_MASK) == PDO_TYPE_BATTERY)
-		ccprintf(" %dmV/%dmW", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*250);
-	else
-		ccprintf(" %dmV/%dmA", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*10);
-}
-
-static void print_rdo(uint32_t word)
-{
-	ccprintf("{%d} %08x", RDO_POS(word), word);
-}
-
-static void print_vdo(int idx, uint32_t word)
-{
-	if (idx == 0 && (word & VDO_SVDM_TYPE)) {
-		const char *cmd = svdm_cmd_name[PD_VDO_CMD(word)];
-		const char *cmdt = svdm_cmdt_name[PD_VDO_CMDT(word)];
-		uint16_t vid = PD_VDO_VID(word);
-		if (!cmd)
-			cmd = "????";
-		ccprintf(" V%04x:%s,%s:%08x", vid, cmd, cmdt, word);
-	} else {
-		ccprintf(" %08x", word);
-	}
-}
-
-static void print_packet(int head, uint32_t *payload)
-{
-	int i;
-	int cnt = PD_HEADER_CNT(head);
-	int typ = PD_HEADER_TYPE(head);
-	int id = PD_HEADER_ID(head);
-	const char *name;
-	const char *prole;
-
-	if (trace_mode == TRACE_MODE_RAW) {
-		ccprintf("%pT[%04x]", PRINTF_TIMESTAMP_NOW, head);
-		for (i = 0; i < cnt; i++)
-			ccprintf(" %08x", payload[i]);
-		ccputs("\n");
-		return;
-	}
-	name = cnt ? data_msg_name[typ] : ctrl_msg_name[typ];
-	prole = head & (PD_ROLE_SOURCE << 8) ? "SRC" : "SNK";
-	ccprintf("%pT %s/%d [%04x]%s",
-		 PRINTF_TIMESTAMP_NOW, prole, id, head, name);
-	if (!cnt) { /* Control message : we are done */
-		ccputs("\n");
-		return;
-	}
-	/* Print payload for data message */
-	for (i = 0; i < cnt; i++)
-		switch (typ) {
-		case PD_DATA_SOURCE_CAP:
-		case PD_DATA_SINK_CAP:
-			print_pdo(payload[i]);
-			break;
-		case PD_DATA_REQUEST:
-			print_rdo(payload[i]);
-			break;
-		case PD_DATA_BIST:
-			ccprintf("mode %d cnt %04x", payload[i] >> 28,
-				 payload[i] & 0xffff);
-			break;
-		case PD_DATA_VENDOR_DEF:
-			print_vdo(i, payload[i]);
-			break;
-		default:
-			ccprintf(" %08x", payload[i]);
-	}
-	ccputs("\n");
-}
-
-static void print_error(enum pd_rx_errors err)
-{
-	if (err == PD_RX_ERR_INVAL)
-		ccprintf("%pT TMOUT\n", PRINTF_TIMESTAMP_NOW);
-	else if (err == PD_RX_ERR_HARD_RESET)
-		ccprintf("%pT HARD-RST\n", PRINTF_TIMESTAMP_NOW);
-	else if (err == PD_RX_ERR_UNSUPPORTED_SOP)
-		ccprintf("%pT SOP*\n", PRINTF_TIMESTAMP_NOW);
-	else
-		ccprintf("ERR %d\n", err);
-}
-
-/* keep track of RX edge timing in order to trigger receive */
-static timestamp_t rx_edge_ts[2][PD_RX_TRANSITION_COUNT];
-static int rx_edge_ts_idx[2];
-
-void rx_event(void)
-{
-	int pending, i;
-	int next_idx;
-	pending = STM32_EXTI_PR;
-
-	/* Iterate over the 2 CC lines */
-	for (i = 0; i < 2; i++) {
-		if (pending & (1 << (21 + i))) {
-			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
-			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
-
-			/*
-			 * If we have seen enough edges in a certain amount of
-			 * time, then trigger RX start.
-			 */
-			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
-				/* acquire the message only on the active CC */
-				STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN
-						      : STM32_COMP_CMP2EN);
-				/* start sampling */
-				pd_rx_start(0);
-				/*
-				 * ignore the comparator IRQ until we are done
-				 * with current message
-				 */
-				pd_rx_disable_monitoring(0);
-				/* trigger the analysis in the task */
-#ifdef HAS_TASK_SNIFFER
-				task_set_event(TASK_ID_SNIFFER, 1 << i);
-#endif
-				/* start reception only one CC line */
-				break;
-			} else {
-				/* do not trigger RX start, just clear int */
-				STM32_EXTI_PR = EXTI_COMP_MASK(0);
-			}
-			rx_edge_ts_idx[i] = next_idx;
-		}
-	}
-}
-#ifdef HAS_TASK_SNIFFER
-DECLARE_IRQ(STM32_IRQ_COMP, rx_event, 1);
-#endif
-
-void trace_packets(void)
-{
-	int head;
-	uint32_t payload[7];
-
-#ifdef HAS_TASK_SNIFFER
-	/* Disable sniffer DMA configuration */
-	dma_disable(STM32_DMAC_CH6);
-	dma_disable(STM32_DMAC_CH7);
-	task_disable_irq(STM32_IRQ_DMA_CHANNEL_4_7);
-	/* remove TIM1 CH1/2/3 DMA remapping */
-	STM32_SYSCFG_CFGR1 &= ~BIT(28);
-#endif
-
-	/* "classical" PD RX configuration */
-	pd_hw_init_rx(0);
-	pd_select_polarity(0, 0);
-	/* detect messages on both CCx lines */
-	STM32_COMP_CSR |= STM32_COMP_CMP2EN | STM32_COMP_CMP1EN;
-	/* Enable the RX interrupts */
-	pd_rx_enable_monitoring(0);
-
-	while (1) {
-		task_wait_event(-1);
-		if (trace_mode == TRACE_MODE_OFF)
-			break;
-		/* incoming packet processing */
-		head = pd_analyze_rx(0, payload);
-		pd_rx_complete(0);
-		/* re-enabled detection on both CCx lines */
-		STM32_COMP_CSR |= STM32_COMP_CMP2EN | STM32_COMP_CMP1EN;
-		pd_rx_enable_monitoring(0);
-		/* print the last packet content */
-		if (head > 0)
-			print_packet(head, payload);
-		else
-			print_error(head);
-		if (head > 0 && expected_cmd == PD_HEADER_TYPE(head))
-			task_wake(TASK_ID_CONSOLE);
-	}
-
-	task_disable_irq(STM32_IRQ_COMP);
-	/* Disable tracer DMA configuration */
-	dma_disable(STM32_DMAC_CH2);
-	/* Put back : sniffer RX hardware configuration */
-#ifdef HAS_TASK_SNIFFER
-	sniffer_init();
-#endif
-}
-
-int expect_packet(int pol, uint8_t cmd, uint32_t timeout_us)
-{
-	uint32_t evt;
-
-	expected_cmd = cmd;
-	evt = task_wait_event(timeout_us);
-
-	return !(evt == TASK_EVENT_TIMER);
-}
-
-void set_trace_mode(int mode)
-{
-	/* No change */
-	if (mode == trace_mode)
-		return;
-
-	trace_mode = mode;
-	/* kick the task to take into account the new value */
-#ifdef HAS_TASK_SNIFFER
-	task_wake(TASK_ID_SNIFFER);
-#endif
-}
diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c
deleted file mode 100644
index 00effb8539..0000000000
--- a/board/twinkie/sniffer.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "injector.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "util.h"
-#include "ina2xx.h"
-
-/* Size of one USB packet buffer */
-#define EP_BUF_SIZE 64
-
-#define EP_PACKET_HEADER_SIZE 4
-/* Size of the payload (packet minus the header) */
-#define EP_PAYLOAD_SIZE (EP_BUF_SIZE - EP_PACKET_HEADER_SIZE)
-
-/* Buffer enough to avoid overflowing due to USB latencies on both sides */
-#define RX_COUNT (16 * EP_PAYLOAD_SIZE)
-
-/* Task event for the USB transfer interrupt */
-#define USB_EVENT TASK_EVENT_CUSTOM_BIT(0)
-
-/* Bitmap of enabled capture channels : CC1+CC2 by default */
-static uint8_t channel_mask = 0x3;
-
-/* edge timing samples */
-static uint8_t samples[2][RX_COUNT];
-/* bitmap of the samples sub-buffer filled with DMA data */
-static volatile uint32_t filled_dma;
-/* timestamps of the beginning of DMA buffers */
-static uint16_t sample_tstamp[4];
-/* sequence number of the beginning of DMA buffers */
-static uint16_t sample_seq[4];
-
-/* Bulk endpoint double buffer */
-static usb_uint ep_buf[2][EP_BUF_SIZE / 2] __usb_ram;
-/* USB Buffers not used, ready to be filled */
-static volatile uint32_t free_usb = 3;
-
-static inline void led_set_activity(int ch)
-{
-	static int accumul[2];
-	static uint32_t last_ts[2];
-	uint32_t now = __hw_clock_source_read();
-	int delta = now - last_ts[ch];
-	last_ts[ch] = now;
-	accumul[ch] = MAX(0, accumul[ch] + (30000 - delta));
-	gpio_set_level(ch ? GPIO_LED_R_L : GPIO_LED_G_L, !accumul[ch]);
-}
-
-static inline void led_set_record(void)
-{
-	gpio_set_level(GPIO_LED_B_L, 0);
-}
-
-static inline void led_reset_record(void)
-{
-	gpio_set_level(GPIO_LED_B_L, 1);
-}
-
-/* USB descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_VENDOR) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_VENDOR,
-	.bAlternateSetting = 0,
-	.bNumEndpoints = 1,
-	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceProtocol = 0,
-	.iInterface = USB_STR_SNIFFER,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_VENDOR,
-						 USB_EP_SNIFFER) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_SNIFFER,
-	.bmAttributes = 0x02 /* Bulk IN */,
-	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
-	.bInterval = 1
-};
-
-/* USB callbacks */
-static void ep_tx(void)
-{
-	static int b; /* current buffer index */
-	if (btable_ep[USB_EP_SNIFFER].tx_count) {
-		/* we have transmitted the previous buffer, toggle it */
-		free_usb |= 1 << b;
-		b = b ? 0 : 1;
-		btable_ep[USB_EP_SNIFFER].tx_addr = usb_sram_addr(ep_buf[b]);
-	}
-	/* re-enable data transmission if we have available data */
-	btable_ep[USB_EP_SNIFFER].tx_count = (free_usb & (1<<b)) ? 0
-								 : EP_BUF_SIZE;
-	STM32_TOGGLE_EP(USB_EP_SNIFFER, EP_TX_MASK, EP_TX_VALID, 0);
-	/* wake up the processing */
-	task_set_event(TASK_ID_SNIFFER, USB_EVENT);
-}
-
-static void ep_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	/* Bulk IN endpoint */
-	btable_ep[USB_EP_SNIFFER].tx_addr = usb_sram_addr(ep_buf[0]);
-	btable_ep[USB_EP_SNIFFER].tx_count = EP_BUF_SIZE;
-	STM32_USB_EP(USB_EP_SNIFFER) = (USB_EP_SNIFFER << 0) /*Endpoint Num*/ |
-				       (3 << 4) /* TX Valid */ |
-				       (0 << 9) /* Bulk EP */ |
-				       (0 << 12) /* RX Disabled */;
-}
-USB_DECLARE_EP(USB_EP_SNIFFER, ep_tx, ep_tx, ep_event);
-
-
-/* --- RX operation using comparator linked to timer --- */
-/* RX on CC1 is using COMP1 triggering TIM1 CH1 */
-#define TIM_RX1 1
-#define DMAC_TIM_RX1 STM32_DMAC_CH6
-#define TIM_RX1_CCR_IDX 1
-/* RX on CC1 is using COMP2 triggering TIM2 CH4 */
-#define TIM_RX2 2
-#define DMAC_TIM_RX2 STM32_DMAC_CH7
-#define TIM_RX2_CCR_IDX 4
-
-/* Clock divider for RX edges timings (2.4Mhz counter from 48Mhz clock) */
-#define RX_CLOCK_DIV (20 - 1)
-
-static const struct dma_option dma_tim_cc1 = {
-	DMAC_TIM_RX1, (void *)&STM32_TIM_CCRx(TIM_RX1, TIM_RX1_CCR_IDX),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
-};
-
-static const struct dma_option dma_tim_cc2 = {
-	DMAC_TIM_RX2, (void *)&STM32_TIM_CCRx(TIM_RX2, TIM_RX2_CCR_IDX),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
-};
-
-/* sequence number for sample buffers */
-static volatile uint32_t seq;
-/* Buffer overflow count */
-static uint32_t oflow;
-
-#define SNIFFER_CHANNEL_CC1 0
-#define SNIFFER_CHANNEL_CC2 1
-
-#define get_channel(b)   (((b) >> 12) & 0x1)
-
-void tim_rx1_handler(uint32_t stat)
-{
-	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
-	int idx = !(stat & STM32_DMA_ISR_HTIF(DMAC_TIM_RX1));
-	uint32_t mask = idx ? 0xFF00 : 0x00FF;
-	uint32_t next = idx ? 0x0001 : 0x0100;
-
-	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC1<<12);
-	if (filled_dma & next) {
-		oflow++;
-		sample_seq[idx] |= 0x8000;
-	} else {
-		led_set_record();
-	}
-	filled_dma |= mask;
-	dma->ifcr = STM32_DMA_ISR_ALL(DMAC_TIM_RX1);
-	led_set_activity(0);
-}
-
-void tim_rx2_handler(uint32_t stat)
-{
-	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
-	int idx = !(stat & STM32_DMA_ISR_HTIF(DMAC_TIM_RX2));
-	uint32_t mask = idx ? 0xFF000000 : 0x00FF0000;
-	uint32_t next = idx ? 0x00010000 : 0x01000000;
-
-	idx += 2;
-	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC2<<12);
-	if (filled_dma & next) {
-		oflow++;
-		sample_seq[idx] |= 0x8000;
-	} else {
-		led_set_record();
-	}
-	filled_dma |= mask;
-	dma->ifcr = STM32_DMA_ISR_ALL(DMAC_TIM_RX2);
-	led_set_activity(1);
-}
-
-void tim_dma_handler(void)
-{
-	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
-	uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_HTIF(DMAC_TIM_RX2)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX2));
-	if (stat & STM32_DMA_ISR_ALL(DMAC_TIM_RX2))
-		tim_rx2_handler(stat);
-	else
-		tim_rx1_handler(stat);
-	/* time to process the samples */
-	task_set_event(TASK_ID_SNIFFER, USB_EVENT);
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, tim_dma_handler, 1);
-
-static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
-{
-	int bit_idx = 8 * ((ch_idx - 1) % 2);
-	/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
-	__hw_timer_enable_clock(tim_id, 1);
-	/* Timer configuration */
-	tim->cr1 = 0x0004;
-	tim->cr2 = 0x0000;
-	/* Auto-reload value : 8-bit free running counter */
-	tim->arr = 0xFF;
-	/* Counter reloading event after 106us */
-	tim->ccr[1] = 0xFF;
-	/* Timer ICx input configuration */
-	if (ch_idx <= 2)
-		tim->ccmr1 = 1 << bit_idx;
-	else
-		tim->ccmr2 = 1 << bit_idx;
-	tim->ccer = 0xB << ((ch_idx - 1) * 4);
-	/* TODO: add input filtering */
-	/* configure DMA request on CCRx update and overflow/update event */
-	tim->dier = (1 << (8 + ch_idx)) | (1 << (8 + up_idx));
-	/* set prescaler to /26 (F=2.4Mhz, T=0.4us) */
-	tim->psc = RX_CLOCK_DIV;
-	/* Reload the pre-scaler and reset the counter, clear CCRx */
-	tim->egr = 0x001F;
-	/* clear update event from reloading */
-	tim->sr = 0;
-}
-
-
-
-void sniffer_init(void)
-{
-	/* remap TIM1 CH1/2/3 to DMA channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(28);
-
-	/* TIM1 CH1 for CC1 RX */
-	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
-		      TIM_RX1_CCR_IDX, 2);
-	/* TIM3 CH4 for CC2 RX */
-	rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2),
-		      TIM_RX2_CCR_IDX, 2);
-
-	/* turn on COMP/SYSCFG */
-	STM32_RCC_APB2ENR |= BIT(0);
-	STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
-			 STM32_COMP_CMP1INSEL_VREF12 |
-			 STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2EN | STM32_COMP_CMP2MODE_HSPEED |
-			 STM32_COMP_CMP2INSEL_VREF12 |
-			 STM32_COMP_CMP2OUTSEL_TIM2_IC4 |
-			 STM32_COMP_CMP2HYST_HI;
-
-	/* start sampling the edges on the CC lines using the RX timers */
-	dma_start_rx(&dma_tim_cc1, RX_COUNT, samples[0]);
-	dma_start_rx(&dma_tim_cc2, RX_COUNT, samples[1]);
-	task_enable_irq(STM32_IRQ_DMA_CHANNEL_4_7);
-	/* start RX timers on CC1 and CC2 */
-	STM32_TIM_CR1(TIM_RX1) |= 1;
-	STM32_TIM_CR1(TIM_RX2) |= 1;
-}
-DECLARE_HOOK(HOOK_INIT, sniffer_init, HOOK_PRIO_DEFAULT);
-
-/* state of the simple text tracer */
-extern int trace_mode;
-
-/* Task to post-process the samples and copy them the USB endpoint buffer */
-void sniffer_task(void)
-{
-	int u = 0; /* current USB buffer index */
-	int d = 0; /* current DMA buffer index */
-	int off = 0; /* DMA buffer offset */
-
-	while (1) {
-		/* Wait for a new buffer of samples or a new USB free buffer */
-		task_wait_event(-1);
-		/* send the available samples over USB if we have a buffer*/
-		while (filled_dma && free_usb) {
-			while (!(filled_dma & BIT(d))) {
-				d = (d + 1) & 31;
-				off += EP_PAYLOAD_SIZE;
-				if (off >= RX_COUNT)
-					off = 0;
-			}
-
-			ep_buf[u][0] = sample_seq[d >> 3] | (d & 7);
-			ep_buf[u][1] = sample_tstamp[d >> 3];
-
-			memcpy_to_usbram(
-					((void *)usb_sram_addr(ep_buf[u]
-						+ (EP_PACKET_HEADER_SIZE>>1))),
-					samples[d >> 4]+off,
-					EP_PAYLOAD_SIZE);
-			atomic_clear_bits((uint32_t *)&free_usb, 1 << u);
-			u = !u;
-			atomic_clear_bits((uint32_t *)&filled_dma, 1 << d);
-		}
-		led_reset_record();
-
-		if (trace_mode != TRACE_MODE_OFF) {
-			uint8_t curr = recording_enable(0);
-			trace_packets();
-			recording_enable(curr);
-		}
-	}
-}
-
-int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(pol ? DMAC_TIM_RX2
-						     : DMAC_TIM_RX1);
-	uint32_t t0 = __hw_clock_source_read();
-	uint32_t c0 = chan->cndtr;
-	uint32_t t_gap = t0;
-	uint32_t c_gap = c0;
-	uint32_t total_edges = 0;
-
-	while (1) {
-		uint32_t t = __hw_clock_source_read();
-		uint32_t c = chan->cndtr;
-		if (t - t0 > timeout_us) /* Timeout */
-			break;
-		if (min_edges) { /* real packet detection */
-			int nb = (int)c_gap - (int)c;
-			if (nb < 0)
-				nb = RX_COUNT - nb;
-			if (nb > 3) { /* NOT IDLE */
-				t_gap = t;
-				c_gap = c;
-				total_edges += nb;
-			} else {
-				if ((t - t_gap) > 20 &&
-				    (total_edges - (t - t0)/256) >= min_edges)
-					/* real gap after the packet */
-					break;
-			}
-		}
-	}
-	return (__hw_clock_source_read() - t0 > timeout_us);
-}
-
-uint8_t recording_enable(uint8_t new_mask)
-{
-	uint8_t old_mask = channel_mask;
-	uint8_t diff = channel_mask ^ new_mask;
-	/* start/stop RX timers according to the channel mask */
-	if (diff & 1) {
-		if (new_mask & 1)
-			STM32_TIM_CR1(TIM_RX1) |= 1;
-		else
-			STM32_TIM_CR1(TIM_RX1) &= ~1;
-	}
-	if (diff & 2) {
-		if (new_mask & 2)
-			STM32_TIM_CR1(TIM_RX2) |= 1;
-		else
-			STM32_TIM_CR1(TIM_RX2) &= ~1;
-	}
-	channel_mask = new_mask;
-	return old_mask;
-}
-
-static void sniffer_sysjump(void)
-{
-	/* Stop DMA before jumping to avoid memory corruption */
-	recording_enable(0);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, sniffer_sysjump, HOOK_PRIO_DEFAULT);
-
-static int command_sniffer(int argc, char **argv)
-{
-	ccprintf("Seq number:%d Overflows: %d\n", seq, oflow);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer,
-			"[]", "Buffering status");
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
deleted file mode 100644
index 1c20a9df77..0000000000
--- a/board/twinkie/usb_pd_config.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-#include "ina2xx.h"
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 17
-#define TIM_CLOCK_PD_RX_C0 1
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PA6/PB4 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-static inline void spi_enable_clock(int port)
-{
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-}
-
-/* RX is using COMP1 or COMp2 triggering TIM1 CH1  */
-#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
-#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
-
-#define DMAC_TIM_RX(p) STM32_DMAC_CH2
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_CCR_CS  1
-#define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
-#define IRQ_COMP STM32_IRQ_COMP
-/* triggers packet detection on comparator falling edge */
-#define EXTI_XTSR STM32_EXTI_FTSR
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* 40 MHz pin speed on SPI TX PB4 */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000300;
-	/* 40 MHz pin speed on SPI TX PA6 */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003000;
-	/* 40 MHz pin speed on TIM17_CH1 (PB9) */
-	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0000;
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-#if 0 /* Transmit only on the active CC line */
-	if (polarity) {
-		gpio_set_level(GPIO_CC2_TX_EN, 1);
-		/* TX_DATA on PA6 is now connected to SPI1 */
-		gpio_set_alternate_function(GPIO_A, 0x0040, 0);
-	} else {
-		gpio_set_level(GPIO_CC1_TX_EN, 1);
-		/* TX_DATA on PB4 is now connected to SPI1 */
-		gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-	}
-#else /* Transmit on both CC lines */
-	gpio_set_level(GPIO_CC2_TX_EN, 1);
-	gpio_set_level(GPIO_CC1_TX_EN, 1);
-	/* TX_DATA on PA6 is now connected to SPI1 */
-	gpio_set_alternate_function(GPIO_A, 0x0040, 0);
-	/* TX_DATA on PB4 is now connected to SPI1 */
-	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
-#endif
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* TX_DATA on PB4 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4)))
-							     |  (1 << (2*4));
-	/* TX_DATA on PA6 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2*6)))
-							     |  (1 << (2*6));
-	/*
-	 * Tri-state the low side after the high side
-	 * to ensure we are not going above Vnc
-	 */
-	gpio_set_level(GPIO_CC1_TX_EN, 0);
-	gpio_set_level(GPIO_CC2_TX_EN, 0);
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/* use the right comparator */
-	STM32_COMP_CSR = (STM32_COMP_CSR
-		& ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
-		  |STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
-		| STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4
-		| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
-}
-
-/* Initialize pins used for clocking */
-static inline void pd_tx_init(void)
-{
-	gpio_config_module(MODULE_USB_PD, 1);
-
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* Detect when VBUS crosses the 4.5V threshold (1.25mV/bit) */
-	ina2xx_write(0, INA2XX_REG_ALERT, 4500 * 100 / 125);
-	ina2xx_write(0, INA2XX_REG_MASK, INA2XX_MASK_EN_BOL);
-	/* start as a power consumer */
-	gpio_set_level(GPIO_CC1_RD, 0);
-	gpio_set_level(GPIO_CC2_RD, 0);
-#endif /* CONFIG_USB_PD_TX_PHY_ONLY */
-}
-
-static inline void pd_set_host_mode(int port, int enable)
-{
-	if (enable) {
-		gpio_set_level(GPIO_CC1_RD, 1);
-		gpio_set_level(GPIO_CC2_RD, 1);
-		/* set Rp by driving high RPUSB GPIO */
-		gpio_set_flags(GPIO_CC1_RPUSB, GPIO_OUT_HIGH);
-		gpio_set_flags(GPIO_CC2_RPUSB, GPIO_OUT_HIGH);
-	} else {
-		/* put back RPUSB GPIO in the default state and set Rd */
-		gpio_set_flags(GPIO_CC1_RPUSB, GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_CC2_RPUSB, GPIO_ODR_HIGH);
-		gpio_set_level(GPIO_CC1_RD, 0);
-		gpio_set_level(GPIO_CC2_RD, 0);
-	}
-}
-
-static inline void pd_config_init(int port, uint8_t power_role)
-{
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* Set CC pull resistors */
-	pd_set_host_mode(port, power_role);
-#endif /* CONFIG_USB_PD_TX_PHY_ONLY */
-
-	/* Initialize TX pins and put them in Hi-Z */
-	pd_tx_init();
-}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	if (cc == 0)
-		return adc_read_channel(ADC_CH_CC1_PD);
-	else
-		return adc_read_channel(ADC_CH_CC2_PD);
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/twinkie/usb_pd_policy.c b/board/twinkie/usb_pd_policy.c
deleted file mode 100644
index 62ecd6e0db..0000000000
--- a/board/twinkie/usb_pd_policy.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
-
-const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-
-const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	int red = supply_voltage == 20000;
-	int green = supply_voltage == 5000;
-	int blue = supply_voltage && !(red || green);
-	gpio_set_level(GPIO_LED_R_L, !red);
-	gpio_set_level(GPIO_LED_G_L, !green);
-	gpio_set_level(GPIO_LED_B_L, !blue);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* assume the alert was programmed to detect bus voltage above 4.5V */
-	return (gpio_get_level(GPIO_VBUS_ALERT_L) == 0);
-}
-
-__override int pd_check_power_swap(int port)
-{
-	/* Always refuse power swap */
-	return 0;
-}
-
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
-{
-	/* Always allow data swap */
-	return 1;
-}
-
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
-				 int flags)
-{
-}
-
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
-{
-}
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	return 0;
-}
diff --git a/board/twinkie/vif_override.xml b/board/twinkie/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/twinkie/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/vilboz/analyzestack.yaml b/board/vilboz/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/vilboz/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/vilboz/battery.c b/board/vilboz/battery.c
deleted file mode 100644
index 6f6bca7662..0000000000
--- a/board/vilboz/battery.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "common.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* SMP L19M3PG1 */
-	[BATTERY_SMP] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L19M3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* SMP L20M3PG1 57W
-	 * Gauge IC: TI BQ40Z696A
-	 */
-	[BATTERY_SMP_1] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG1",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 247,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SMP L20M3PG0 47W
-	 * Gauge IC: TI BQ40Z696A
-	 */
-	[BATTERY_SMP_2] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG0",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SMP L20M3PG3 47W
-	 * Gauge IC: Renesas RAJ240047
-	 */
-	[BATTERY_SMP_3] = {
-		.fuel_gauge = {
-			.manuf_name = "SMP",
-			.device_name = "L20M3PG3",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0010,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200, /* mV */
-			.voltage_normal         = 11520, /* mV */
-			.voltage_min            = 9000,  /* mV */
-			.precharge_current      = 256,   /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 70,
-		},
-	},
-
-	/* LGC  L19L3PG1 */
-	[BATTERY_LGC] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L19L3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 73,
-		},
-	},
-
-	/* LGC L20L3PG1 57W
-	 * Gauge IC: Renesas
-	 */
-	[BATTERY_LGC_1] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0010,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11580, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* LGC L20L3PG0 47W
-	 * Gauge IC: Renesas
-	 */
-	[BATTERY_LGC_2] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "L20L3PG0",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x0010,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11580, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 256,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* Celxpert  L19C3PG1 */
-	[BATTERY_CEL] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L19C3PG1",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0100,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 50,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* Celxpert L20C3PG0 57W
-	 * Gauge IC: TI
-	 */
-	[BATTERY_CEL_1] = {
-		.fuel_gauge = {
-			.manuf_name = "Celxpert",
-			.device_name = "L20C3PG0",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 200,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SUNWODA L20D3PG1 57W
-	 * Gauge IC: TI
-	 */
-	[BATTERY_SUNWODA] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG1",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 250,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-
-	/* SUNWODA L20D3PG0 47W
-	 * Gauge IC: TI
-	 */
-	[BATTERY_SUNWODA_1] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L20D3PG0",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0000,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200, /* mV */
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000,  /* mV */
-			.precharge_current	= 205,	 /* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 70,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SMP;
-
-struct chg_curr_step {
-	int on;
-	int off;
-	int curr_ma;
-};
-
-static const struct chg_curr_step chg_curr_table[] = {
-	{.on = 0, .off = 35, .curr_ma = 2800},
-	{.on = 36, .off = 35, .curr_ma = 1500},
-	{.on = 39, .off = 38, .curr_ma = 1000},
-};
-
-/* All charge current tables must have the same number of levels */
-#define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table)
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int rv;
-	int chg_temp_c;
-	int current;
-	int thermal_sensor0;
-	static int current_level;
-	static int prev_tmp;
-
-	/*
-	 * Precharge must be executed when communication is failed on
-	 * dead battery.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-		return 0;
-
-	current = curr->requested_current;
-
-	rv = temp_sensor_read(TEMP_SENSOR_CHARGER, &thermal_sensor0);
-	chg_temp_c = K_TO_C(thermal_sensor0);
-
-	if (rv != EC_SUCCESS)
-		return 0;
-
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		if (chg_temp_c < prev_tmp) {
-			if (chg_temp_c <= chg_curr_table[current_level].off)
-				current_level = current_level - 1;
-		} else if (chg_temp_c > prev_tmp) {
-			if (chg_temp_c >= chg_curr_table[current_level + 1].on)
-				current_level = current_level + 1;
-		}
-		/*
-		 * Prevent level always minus 0 or over table steps.
-		 */
-		if (current_level < 0)
-			current_level = 0;
-		else if (current_level >= NUM_CHG_CURRENT_LEVELS)
-			current_level = NUM_CHG_CURRENT_LEVELS - 1;
-
-		prev_tmp = chg_temp_c;
-		current = chg_curr_table[current_level].curr_ma;
-
-		curr->requested_current = MIN(curr->requested_current, current);
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}
diff --git a/board/vilboz/board.c b/board/vilboz/board.c
deleted file mode 100644
index a39d46cbcd..0000000000
--- a/board/vilboz/board.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "button.h"
-#include "charge_state_v2.h"
-#include "cros_board_info.h"
-#include "driver/accel_lis2dw12.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
-
-void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	gpio_set_level(GPIO_DP1_HPD, gpio_get_level(signal));
-}
-
-#include "gpio_list.h"
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct stprivate_data g_lis2dwl_data;
-static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LIS2DWL,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &lis2dw12_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_lis2dwl_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LIS2DWL_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = LIS2DW12_ODR_MIN_VAL,
-	 .max_frequency = LIS2DW12_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_ACCEL),
-	 .int_signal = GPIO_6AXIS_INT_L,
-	 .flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	 .config = {
-		 /* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_LSM6DSM,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &lsm6dsm_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
-	.int_signal = GPIO_6AXIS_INT_L,
-	.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-	 .default_range = 1000 | ROUND_UP_FLAG, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = LSM6DSM_ODR_MIN_VAL,
-	 .max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it need a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-const struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_FAULT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	default:
-		break;
-	}
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-		ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	return status;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-int board_pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	/* Use the TCPC to enable fast switch when FRS included */
-	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
-	}
-
-	return rv;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-static void setup_fw_config(void)
-{
-	/* Enable DB HDMI interrupts. */
-	gpio_enable_interrupt(GPIO_HDMI_CONN_HPD_3V3);
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-
-	if (ec_config_has_lid_angle_tablet_mode()) {
-		/* Enable Gyro interrupts */
-		gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		/* Device is clamshell only */
-		tablet_set_mode(0, TABLET_TRIGGER_LID);
-		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-static void lte_usb3_mux_init(void)
-{
-	/*
-	 * the USB_C1 port might be used for the LTE modem if it is not used
-	 * for type-C, we need to keep the superspeed mux in USB 3 position.
-	 */
-	if (ec_config_lte_present() == LTE_PRESENT) {
-		const struct usb_mux usb_c1 = {
-			.usb_port = 1 /* USBC_PORT_C1 */,
-			.i2c_port = I2C_PORT_USB_AP_MUX,
-			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-			.driver = &amd_fp5_usb_mux_driver,
-		};
-		bool unused;
-		/*
-		 * Note: Direct mux driver calls are deprecated.  Calls
-		 * should go through the usb_mux APIs instead.
-		 */
-		/* steer the mux to connect the USB 3 superspeed pairs */
-		usb_c1.driver->set(&usb_c1, USB_PD_MUX_USB_ENABLED, &unused);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, lte_usb3_mux_init, HOOK_PRIO_DEFAULT);
-
-static void lte_function_resume(void)
-{
-	gpio_set_level(GPIO_LTE_FCPO, 1);
-}
-DECLARE_DEFERRED(lte_function_resume);
-
-static void lte_power_resume(void)
-{
-	gpio_set_level(GPIO_LTE_EN, 1);
-	gpio_set_level(GPIO_LTE_W_DISABLE_L, 1);
-}
-DECLARE_DEFERRED(lte_power_resume);
-
-static void lte_power_suspend(void)
-{
-	gpio_set_level(GPIO_LTE_EN, 0);
-	gpio_set_level(GPIO_LTE_W_DISABLE_L, 0);
-}
-DECLARE_DEFERRED(lte_power_suspend);
-
-static void lte_function_suspend(void)
-{
-	gpio_set_level(GPIO_LTE_FCPO, 0);
-	hook_call_deferred(&lte_power_suspend_data, 100 * MSEC);
-}
-DECLARE_DEFERRED(lte_function_suspend);
-
-static void wwan_lte_resume_hook(void)
-{
-	/* Turn on WWAN LTE function as we go into S0 from S3/S5. */
-	hook_call_deferred(&lte_function_suspend_data, -1);
-	hook_call_deferred(&lte_power_suspend_data, -1);
-	lte_power_resume();
-	hook_call_deferred(&lte_function_resume_data, 10 * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, wwan_lte_resume_hook, HOOK_PRIO_DEFAULT);
-
-static void wwan_lte_suspend_hook(void)
-{
-	/* Turn off WWAN LTE function as we go into S3/S5 from S0. */
-	hook_call_deferred(&lte_power_resume_data, -1);
-	hook_call_deferred(&lte_function_resume_data, -1);
-	hook_call_deferred(&lte_function_suspend_data, 20 * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, wwan_lte_suspend_hook, HOOK_PRIO_DEFAULT);
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		.freq = 15000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT3807] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-	GPIO_EN_USB_A1_5V,
-};
-
-__override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			int max_ma, int charge_mv)
-{
-	/*
-	 * Limit the input current to 95% negotiated limit,
-	 * to account for the charger chip margin.
-	 */
-	charge_ma = charge_ma * 95 / 100;
-
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT),
-				charge_mv);
-}
diff --git a/board/vilboz/board.h b/board/vilboz/board.h
deleted file mode 100644
index 16cea08c1e..0000000000
--- a/board/vilboz/board.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_DALBOZ
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-
-/* USB-A config */
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_DB_L
-
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_LSM6DSM
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_LIS2DWL
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/*
- * Vilboz's battery takes ~3 seconds to come back out of its disconnect state,
- * so give it a little more for margin.
- */
-#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 4
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-
-#ifndef __ASSEMBLER__
-
-/* This I2C moved. Temporarily detect and support the V0 HW. */
-extern int I2C_PORT_BATTERY;
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_SMP,
-	BATTERY_SMP_1,
-	BATTERY_SMP_2,
-	BATTERY_SMP_3,
-	BATTERY_LGC,
-	BATTERY_LGC_1,
-	BATTERY_LGC_2,
-	BATTERY_CEL,
-	BATTERY_CEL_1,
-	BATTERY_SUNWODA,
-	BATTERY_SUNWODA_1,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_PORT_COUNT
-};
-
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * VILBOZ_MB_USBAC
- *	USB-A0  Speed: 5 Gbps
- *		Retimer: none
- *	USB-C0  Speed: 5 Gbps
- *		Retimer: none
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	VILBOZ_MB_USBAC = 0,
-};
-
-/**
- * VILBOZ_DB_D_OPT1_USBA_HDMI
- *	USB-A1  Speed: 5 Gbps
- *		Retimer: None
- *	HDMI    Retimer: PS8203
- *		MST Hub: none
- *	P-Sensor SX9324
- */
-enum ec_cfg_usb_db_type {
-	VILBOZ_DB_D_OPT1_USBA_HDMI = 0,
-};
-
-#include "cbi_ec_fw_config.h"
-
-void board_reset_pd_mcu(void);
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/vilboz/build.mk b/board/vilboz/build.mk
deleted file mode 100644
index 1c0cbc4f63..0000000000
--- a/board/vilboz/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/vilboz/ec.tasklist b/board/vilboz/ec.tasklist
deleted file mode 100644
index 08801d1786..0000000000
--- a/board/vilboz/ec.tasklist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE)
diff --git a/board/vilboz/gpio.inc b/board/vilboz/gpio.inc
deleted file mode 100644
index 78baa0eccc..0000000000
--- a/board/vilboz/gpio.inc
+++ /dev/null
@@ -1,126 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	lsm6dsm_interrupt)
-GPIO_INT(HDMI_CONN_HPD_3V3,	PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	hdmi_hpd_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 7), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(7, 0), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(EN_USB_A1_5V,		PIN(F, 0), GPIO_OUT_LOW)			/* A1 5V Source Enable */
-GPIO(USB3_C0_DP2_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(DP1_HPD,			PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-GPIO(LED3_PWM,			PIN(C, 3), GPIO_OUT_HIGH)
-
-/* LTE control */
-GPIO(LTE_EN,            PIN(6, 2), GPIO_OUT_LOW)           /* WWAN LTE Function enable */
-GPIO(LTE_W_DISABLE_L,   PIN(4, 0), GPIO_OUT_LOW)           /* WWAN LTE flight mode */
-GPIO(LTE_FCPO,          PIN(7, 3), GPIO_OUT_LOW)           /* WWAN LTE Full Card Power ON OFF */
-
-/*
- * Vilboz has only 1 HDMI DB option
- */
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(IOEX_C0_NCT3807, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt)
-
-IOEX(USB_C0_FAULT_ODL,		EXPIN(IOEX_C0_NCT3807, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(IOEX_C0_NCT3807, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(IOEX_C0_NCT3807, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(IOEX_C0_NCT3807, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(IOEX_C0_NCT3807, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-UNIMPLEMENTED(USB_A0_CHARGE_EN_L)
-IOEX(USB_C0_SBU_FLIP,		EXPIN(IOEX_C0_NCT3807, 1, 7), GPIO_OUT_LOW)	/* C0 SBU Flip */
-UNIMPLEMENTED(USB_A1_CHARGE_EN_DB_L)
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(I2C_AUDIO_USB_HUB_SCL,	PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(I2C_AUDIO_USB_HUB_SDA,	PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_BATT_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/vilboz/led.c b/board/vilboz/led.c
deleted file mode 100644
index 4e9697ddbb..0000000000
--- a/board/vilboz/led.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
-
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-__override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED3_PWM, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED3_PWM, LED_OFF_LVL);
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_GREEN:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_RED:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else if (brightness[EC_LED_COLOR_RED] != 0)
-			led_set_color_battery(EC_LED_COLOR_RED);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/vilboz/vif_override.xml b/board/vilboz/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/vilboz/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/voema/battery.c b/board/voema/battery.c
deleted file mode 100644
index d345cb72ec..0000000000
--- a/board/voema/battery.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305013",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AP15O5L;
diff --git a/board/voema/board.c b/board/voema/board.c
deleted file mode 100644
index ef428089a4..0000000000
--- a/board/voema/board.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config voema_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &voema_kb;
-}
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB3_ACTIVE,
-};
-
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-__override void board_cbi_init(void)
-{
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
-
-static void kb_backlight_enable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
diff --git a/board/voema/board.h b/board/voema/board.h
deleted file mode 100644
index ce91eab712..0000000000
--- a/board/voema/board.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-#ifdef BOARD_VOEMA
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_KX022
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#ifdef BOARD_VOEMA_NPCX796FC
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS) | BIT(BASE_ACCEL))
-#else
-#define CONFIG_ACCEL_FORCE_MODE_MASK (board_accel_force_mode_mask())
-#endif
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#undef CONFIG_SYV682X_HV_ILIM
-#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-#define CONFIG_USB_PD_FRS_PPC
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_TUSB422
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-#undef CONFIG_FANS
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-#ifndef BOARD_VOEMA_NPCX796FC
-void motion_interrupt(enum gpio_signal signal);
-int board_accel_force_mode_mask(void);
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/voema/build.mk b/board/voema/build.mk
deleted file mode 100644
index 0a0929babc..0000000000
--- a/board/voema/build.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-# Limited boards with 796 variant and will use 797 moving forward. Set the
-# modify the variant type to match.
-ifeq ($(BOARD),voema_npcx796fc)
-CHIP_VARIANT:=npcx7m6fc
-else
-CHIP_VARIANT:=npcx7m7fc
-endif
-
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/voema/ec.tasklist b/board/voema/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/voema/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/voema/gpio.inc b/board/voema/gpio.inc
deleted file mode 100644
index 8379e5f12a..0000000000
--- a/board/voema/gpio.inc
+++ /dev/null
@@ -1,184 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-#ifndef BOARD_VOEMA_NPCX796FC
-GPIO_INT(EC_MB_ACCEL_INT_L,    PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-#else
-GPIO(EC_MB_ACCEL_INT_L,	       PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
-#endif
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/*
- * Base / Lid g-sensor interrupt unused on Voema, configure as regular input
- * for power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_FRS_EN,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,		PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO72,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF3,		PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO57,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOC2,		PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO61,		PIN(6, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOB7,		PIN(B, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO40,		PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD1,		PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD0,		PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
- /* LED */
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Amber */
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
diff --git a/board/voema/led.c b/board/voema/led.c
deleted file mode 100644
index 25e71c262d..0000000000
--- a/board/voema/led.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for voema
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/board/voema/sensors.c b/board/voema/sensors.c
deleted file mode 100644
index 005bad5af8..0000000000
--- a/board/voema/sensors.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accel_kionix.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_base_data;
-static struct accelgyro_saved_data_t g_bma253_lid_data;
-
-static struct icm_drv_data_t g_icm426xx_data;
-
-static struct kionix_accel_data g_kx022_lid_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_lid_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_lid_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bma253_base_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR2_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t icm_base_accel = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_icm426xx_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.rot_standard_ref = &base_icm_ref,
-		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-};
-
-struct motion_sensor_t icm_base_gyro = {
-		 .name = "Base Gyro",
-		 .active_mask = SENSOR_ACTIVE_S0_S3,
-		 .chip = MOTIONSENSE_CHIP_ICM426XX,
-		 .type = MOTIONSENSE_TYPE_GYRO,
-		 .location = MOTIONSENSE_LOC_BASE,
-		 .drv = &icm426xx_drv,
-		 .mutex = &g_base_mutex,
-		 .drv_data = &g_icm426xx_data,
-		 .port = I2C_PORT_SENSOR,
-		 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		 .default_range = 1000, /* dps */
-		 .rot_standard_ref = &base_icm_ref,
-		 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-		 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-
-	/*
-	 * TODO: If a SSFC for the base sensor is added, add the check
-	 * here.
-	 */
-	if (IS_ENABLED(BOARD_VOEMA) && get_cbi_ssfc_base_sensor() ==
-			SSFC_SENSOR_BASE_ICM426XX) {
-		gpio_enable_interrupt(GPIO_EC_MB_ACCEL_INT_L);
-		motion_sensors[BASE_ACCEL] = icm_base_accel;
-		motion_sensors[BASE_GYRO] = icm_base_gyro;
-		ccprints("BASE ACCEL/GYRO is ICM426XX");
-	} else
-		ccprints("BASE_ACCEL is BMA253");
-
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-		motion_sensors[LID_ACCEL] = kx022_lid_accel;
-		ccprints("LID_ACCEL is KX022");
-	} else
-		ccprints("LID_ACCEL is BMA253");
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
-
-#ifndef BOARD_VOEMA_NPCX796FC
-void motion_interrupt(enum gpio_signal signal)
-{
-	icm426xx_interrupt(signal);
-}
-
-int board_accel_force_mode_mask(void)
-{
-	if (system_get_board_version() <= 2)
-		return (BIT(LID_ACCEL) | BIT(CLEAR_ALS) | BIT(BASE_ACCEL));
-	else
-		return (BIT(LID_ACCEL) | BIT(CLEAR_ALS));
-}
-#endif
diff --git a/board/voema/vif_override.xml b/board/voema/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/voema/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/voema_npcx796fc b/board/voema_npcx796fc
deleted file mode 120000
index 172bf9e9be..0000000000
--- a/board/voema_npcx796fc
+++ /dev/null
@@ -1 +0,0 @@
-voema
\ No newline at end of file
diff --git a/board/volet/battery.c b/board/volet/battery.c
deleted file mode 100644
index 2e4fb7dc71..0000000000
--- a/board/volet/battery.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* COSMX AP20CBL Battery Information */
-	 [BATTERY_COSMX_AP20CBL] = {
-		.fuel_gauge = {
-			.manuf_name = "COSMX KT0030B002",
-			.device_name = "AP20CBL",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/volet/board.c b/board/volet/board.c
deleted file mode 100644
index a47bd3d8c6..0000000000
--- a/board/volet/board.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/tcpm/tcpci.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static const struct ec_response_keybd_config volet_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config volet_kb_num = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	if (!ec_cfg_has_numeric_pad())
-		return &volet_kb;
-	else
-		return &volet_kb_num;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff,
-		0xff, /* full set */
-	},
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (!ec_cfg_has_keyboard_backlight())
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Voxel if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN3,
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- * reference that temperature and fan settings
- * are derived from data in b/167523658#39
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2100,
-	.rpm_start = 2100,
-	.rpm_max = 5800,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Reference that temperature and fan settings
- * are derived from data in b/167523658#39
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(90),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_cpu,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_cpu,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void kb_backlight_enable(void)
-{
-	if (ec_cfg_has_keyboard_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	if (ec_cfg_has_keyboard_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Only the Burnside Bridge retimers provide a reset pin, but this is
-	 * already handled by the bb_retimer.c driver.
-	 */
-	ps8815_reset();
-	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-__override void board_cbi_init(void)
-{
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad())) {
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-		/* Search key is moved back to col=1,row=0 */
-		keyscan_config.actual_key_mask[0] = 0x14;
-		keyscan_config.actual_key_mask[1] = 0xff;
-		keyscan_config.actual_key_mask[11] = 0xfa;
-		keyscan_config.actual_key_mask[12] = 0xca;
-	}
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-const struct  tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/volet/board.h b/board/volet/board.h
deleted file mode 100644
index 56285989be..0000000000
--- a/board/volet/board.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#undef NPCX7_PWM1_SEL
-#define NPCX7_PWM1_SEL    0    /* GPIO C2 is not used as PWM1. */
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Keyboard backliht */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#ifdef BOARD_VOXEL_ECMODEENTRY
-#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#endif
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-#define CONFIG_USB_PD_FRS_PPC
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_PD_TCPM_TUSB422
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/* Retimer */
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_COSMX_AP20CBL,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/volet/build.mk b/board/volet/build.mk
deleted file mode 100644
index 546bcba8d2..0000000000
--- a/board/volet/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/volet/ec.tasklist b/board/volet/ec.tasklist
deleted file mode 100644
index e76bd368eb..0000000000
--- a/board/volet/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/volet/gpio.inc b/board/volet/gpio.inc
deleted file mode 100644
index ed4b426a86..0000000000
--- a/board/volet/gpio.inc
+++ /dev/null
@@ -1,184 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO(EC_ALS_RGB_INT_L,         PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)	/* unused */
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Voxel, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(3, 5), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(4, 1), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_RT_INT_ODL,			PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,			PIN(9, 6), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,			PIN(C, 2), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Yellow */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-
-GPIO(M2_SSD_PLN,        PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,        PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,      PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,       PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO34,     PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO60,     PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOA7,     PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD0,     PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOD1,     PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,     PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF3,     PIN(F, 3), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/volet/led.c b/board/volet/led.c
deleted file mode 100644
index ba4af36163..0000000000
--- a/board/volet/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/volet/sensors.c b/board/volet/sensors.c
deleted file mode 100644
index 49e879ea94..0000000000
--- a/board/volet/sensors.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_sensors_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE GYRO is ICM426XX");
-		} else
-			ccprints("BASE GYRO is BMI160");
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			ccprints("LID_ACCEL is KX022");
-		} else
-			ccprints("LID_ACCEL is BMA253");
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable interrupt for the accel/gyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (get_cbi_ssfc_base_sensor()) {
-	case SSFC_SENSOR_BASE_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case SSFC_SENSOR_BASE_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
diff --git a/board/volet/vif_override.xml b/board/volet/vif_override.xml
deleted file mode 100644
index 3fc41630da..0000000000
--- a/board/volet/vif_override.xml
+++ /dev/null
@@ -1,158 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
-  <Model_Part_Number>Voxel</Model_Part_Number>
-  <Product_Revision>0</Product_Revision>
-  <TID>0</TID>
-  <Product>
-    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
-    <USB4_Num_Internal_Host_Controllers value="1" />
-    <USB4_Num_PCIe_DN_Bridges value="0" />
-    <USB4RouterList>
-      <Usb4Router>
-        <USB4_Router_ID value="1" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="4" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="1" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="4" />
-        <USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="true" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-        <USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
-        <USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
-        <USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
-      </Usb4Router>
-      <Usb4Router>
-        <USB4_Router_ID value="0" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="2" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="0" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="0" />
-        <USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="false" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-      </Usb4Router>
-    </USB4RouterList>
-  </Product>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="0" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="1" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-</VIF>
diff --git a/board/volteer/battery.c b/board/volteer/battery.c
deleted file mode 100644
index 1c24e1ec24..0000000000
--- a/board/volteer/battery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
diff --git a/board/volteer/board.c b/board/volteer/board.c
deleted file mode 100644
index 8c1be1bf64..0000000000
--- a/board/volteer/board.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/als_tcs3400.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "uart.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1900,
-	.rpm_start = 1900,
-	.rpm_max = 5900,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(35),
-	.temp_fan_max = C_TO_K(50),
-};
-
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-const static struct ec_thermal_config thermal_inductor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(80),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-	},
-	.temp_fan_off = C_TO_K(40),
-	.temp_fan_max = C_TO_K(55),
-};
-
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_inductor,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_inductor,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_BATTERY_SCL,
-		.sda = GPIO_EC_I2C5_BATTERY_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_PWR_SCL_R,
-		.sda = GPIO_EC_I2C7_EEPROM_PWR_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED2_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED3_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED4_SIDESEL] = {
-		.channel = 7,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		/*
-		 * If using the side select to run both LEDs at the same time,
-		 * the frequency should be 1/2 of the color channel PWM
-		 * frequency to drive each LED equally.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/volteer/board.h b/board/volteer/board.h
deleted file mode 100644
index bd527510f2..0000000000
--- a/board/volteer/board.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * Create an EC build that requires AP-driven mode entry to facilitate debugging
- * b/177105656.
- */
-#ifdef BOARD_VOLTEER_APMODEENTRY
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#endif
-
-#ifdef BOARD_VOLTEER_NPCX797FC
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-#endif
-
-/* Optional features */
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
-
-/* Remove PRL state names to free flash space */
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_PWM
-/* Although there are 2 LEDs, they are both controlled by the same lines. */
-#define CONFIG_LED_PWM_COUNT 1
-
-/* Keyboard features */
-
-/* Sensors */
-/* BMA253 accelerometer in base */
-#define CONFIG_ACCEL_BMA255
-
-/* BMI260 accel/gyro in base */
-#define CONFIG_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* TCS3400 ALS */
-#define CONFIG_ALS
-#define ALS_COUNT		1
-#define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
-#define CONFIG_USB_PD_FRS_PPC
-
-/* BC 1.2 */
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-#define CONFIG_DEBUG_ASSERT_BRIEF
-
-/* Disable console commands to help save space */
-#undef CONFIG_CMD_APTHROTTLE
-#undef CONFIG_CMD_BUTTON
-#undef CONFIG_CONSOLE_CMDHELP
-
-/* Disable volume button in ectool */
-#undef CONFIG_HOSTCMD_BUTTON
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#include "usbc_config.h"
-
-enum battery_type {
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_LED1_BLUE = 0,
-	PWM_CH_LED2_GREEN,
-	PWM_CH_LED3_RED,
-	PWM_CH_LED4_SIDESEL,
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	CLEAR_ALS,
-	RGB_ALS,
-	SENSOR_COUNT,
-};
-
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/volteer/build.mk b/board/volteer/build.mk
deleted file mode 100644
index 5adcffff56..0000000000
--- a/board/volteer/build.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-# A limited Volteer boards are reworked with NPCX797FC variant. Set the
-# modify the variant type to match.
-ifeq ($(BOARD),volteer_npcx797fc)
-CHIP_VARIANT:=npcx7m7fc
-else
-CHIP_VARIANT:=npcx7m6fc
-endif
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=cbi.o
-board-y+=led.o
-board-y+=sensors.o
-board-y+=usbc_config.o
diff --git a/board/volteer/cbi.c b/board/volteer/cbi.c
deleted file mode 100644
index b39f0d7d2f..0000000000
--- a/board/volteer/cbi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Features common to ECOS and Zephyr */
-#include "common.h"
-#include "cbi.h"
-#include "cbi_ec_fw_config.h"
-#include "keyboard_raw.h"
-#include "usbc_config.h"
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Volteer if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN2,
-};
-
-__override void board_cbi_init(void)
-{
-	config_usb3_db_type();
-	if ((!IS_ENABLED(TEST_BUILD) && !ec_cfg_has_numeric_pad()) ||
-	    get_board_id() <= 2)
-		keyboard_raw_set_cols(KEYBOARD_COLS_NO_KEYPAD);
-}
diff --git a/board/volteer/ec.tasklist b/board/volteer/ec.tasklist
deleted file mode 100644
index ec9e64e850..0000000000
--- a/board/volteer/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc
deleted file mode 100644
index 33d04741d3..0000000000
--- a/board/volteer/gpio.inc
+++ /dev/null
@@ -1,188 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi260_interrupt)
-GPIO_INT(EC_ALS_RGB_INT_L,     PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Volteer, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(C, 6), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-GPIO(USB_C1_RT_RST_ODL,		PIN(8, 3), GPIO_ODR_LOW)
-GPIO(USB_C0_OC_ODL,		PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,		PIN(5, 0), GPIO_ODR_HIGH)
-/* There is currently no need to service this interrupt. */
-GPIO(USB_C1_RT_INT_ODL,		PIN(F, 3), GPIO_INPUT)
-GPIO(USB_C1_FRS_EN, 		PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-/*
- * Despite their names, M2_SSD_PLN and M2_SSD_PLA are active-low, and M2_SSD_PLN
- * is open-drain.
- * TODO(b/138954381): Change these names when they change on the schematic.
- */
-GPIO(M2_SSD_PLN,		PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,		PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,		PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,		PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Unused signals */
-GPIO(CHARGER_INT_L,		PIN(7, 3), GPIO_INPUT)		/* Interrupt not used from ISL9241, on board pull-up */
-GPIO(EC_GP_SEL0_ODL,		PIN(B, 6), GPIO_OUT_LOW) 	/* Cannot be configured as input, drive output low, don't rely on the default setting of PxDOUT register */
-GPIO(CPU_C10_GATE_L, 		PIN(6, 7), GPIO_INPUT)		/* Unused power sequence signal from AP. Has an on-board pull-down. */
-GPIO(EN_PP5000_USB_AG,		PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP) /* Unconnected power sequencing signal */
-GPIO(UNUSED_GPIO41,		PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOF2,		PIN(F, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO96,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO34,		PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-/* Only connected to test points */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EC_ESPI_ALERT_L,		PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SCL_R, PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_PWR_SDA_R, PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* This selects between an LED module on the motherboard and one on the daughter
- * board, to be controlled by LED_{1,2,3}_L. PWM allows driving both modules at
- * the same time. */
-ALTERNATE(PIN_MASK(6, BIT(0)), 0, MODULE_PWM, 0)                                     /* LED_SIDESEL_4_L */
-ALTERNATE(PIN_MASK(C, BIT(2) | BIT(3) | BIT(4)), 0, MODULE_PWM, 0)                   /* LED_{3,2,1}_L */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
-
diff --git a/board/volteer/led.c b/board/volteer/led.c
deleted file mode 100644
index 6b09d5b4a0..0000000000
--- a/board/volteer/led.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-#ifndef CONFIG_ZEPHYR
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
-	/* The green LED seems to be brighter than the others, so turn down
-	 * green from its natural level for these secondary colors.
-	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
-};
-
-struct pwm_led pwm_leds[] = {
-	/* 2 RGB diffusers controlled by 1 set of 3 channels. */
-	[PWM_LED0] = {
-		.ch0 = PWM_CH_LED3_RED,
-		.ch1 = PWM_CH_LED2_GREEN,
-		.ch2 = PWM_CH_LED1_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 255;
-	brightness_range[EC_LED_COLOR_GREEN] = 255;
-	brightness_range[EC_LED_COLOR_BLUE] = 255;
-}
-#endif
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
-
-/* Illuminates the LED on the side of the active charging port. If not charging,
- * illuminates both LEDs.
- */
-static void led_set_charge_port_tick(void)
-{
-	int port;
-	int side_select_duty;
-
-	port = charge_manager_get_active_charge_port();
-	switch (port) {
-	case 0:
-		side_select_duty = 100;
-		break;
-	case 1:
-		side_select_duty = 0;
-		break;
-	default:
-		side_select_duty = 50;
-	}
-
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pwm_set_duty(PWM_CH_LED4_SIDESEL, side_select_duty);
-}
-DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
-
-static void board_led_init(void)
-{
-	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_enable(PWM_CH_LED4_SIDESEL, 1);
-	pwm_set_duty(PWM_CH_LED4_SIDESEL, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
diff --git a/board/volteer/sensors.c b/board/volteer/sensors.c
deleted file mode 100644
index 5f7e197924..0000000000
--- a/board/volteer/sensors.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_bma2x2_public.h"
-#include "driver/accelgyro_bmi_common_public.h"
-#include "driver/accelgyro_bmi260_public.h"
-#include "driver/als_tcs3400_public.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-/******************************************************************************/
-/* Sensors */
-K_MUTEX_DEFINE(g_lid_accel_mutex);
-K_MUTEX_DEFINE(g_base_mutex);
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI260 private data */
-static struct bmi_drv_data_t g_bmi260_data;
-
-/* TCS3400 private data */
-static struct als_drv_data_t g_tcs3400_data = {
-	.als_cal.scale = 1,
-	.als_cal.uscale = 0,
-	.als_cal.offset = 0,
-	.als_cal.channel_scale = {
-		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
-	},
-};
-
-/*
- * TODO: b/146166425 need to calibrate ALS/RGB sensor. At default settings,
- * shining phone flashlight on sensor pegs all readings at 0xFFFF.
- */
-static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
-	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		},
-	},
-	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0),
-		.scale = {
-			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
-		}
-	},
-	.calibration.irt = INT_TO_FP(1),
-	.saturation.again = TCS_DEFAULT_AGAIN,
-	.saturation.atime = TCS_DEFAULT_ATIME,
-};
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI260,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi260_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi260_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-	[CLEAR_ALS] = {
-		.name = "Clear Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_drv,
-		.drv_data = &g_tcs3400_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = TCS3400_I2C_ADDR_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-		.min_frequency = TCS3400_LIGHT_MIN_FREQ,
-		.max_frequency = TCS3400_LIGHT_MAX_FREQ,
-		.config = {
-			/* Run ALS sensor in S0 */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 1000,
-			},
-		},
-	},
-
-	[RGB_ALS] = {
-		/*
-		 * RGB channels read by CLEAR_ALS and so the i2c port and
-		 * address do not need to be defined for RGB_ALS.
-		 */
-		.name = "RGB Light",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_TCS3400,
-		.type = MOTIONSENSE_TYPE_LIGHT_RGB,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &tcs3400_rgb_drv,
-		.drv_data = &g_tcs3400_rgb_data,
-		.rot_standard_ref = NULL,
-		.default_range = 0x10000, /* scale = 1x, uscale = 0 */
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
-const struct motion_sensor_t *motion_als_sensors[] = {
-	&motion_sensors[CLEAR_ALS],
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-
-static void baseboard_sensors_init(void)
-{
-	/* Note - BMA253 interrupt unused by EC */
-
-	/* Enable interrupt for the TCS3400 color light sensor */
-	gpio_enable_interrupt(GPIO_EC_ALS_RGB_INT_L);
-	/* Enable interrupt for the BMI260 accel/gyro sensor */
-	gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/volteer/usbc_config.c b/board/volteer/usbc_config.c
deleted file mode 100644
index 0adfe98107..0000000000
--- a/board/volteer/usbc_config.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific USB-C configuration */
-#include "common.h"
-#include "cbi_ec_fw_config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "driver/bc12/pi3usb9201_public.h"
-#include "driver/ppc/sn5s330_public.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/ps8xxx_public.h"
-#include "driver/tcpm/rt1715_public.h"
-#include "driver/tcpm/tusb422_public.h"
-#include "driver/tcpm/tcpci.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* USBC TCPC configuration for USB3 daughter board */
-static const struct tcpc_config_t tcpc_config_p1_usb3 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1,
-		.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-	},
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 | TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V,
-	.drv = &ps8xxx_tcpm_drv,
-};
-
-/*
- * USB3 DB mux configuration - the top level mux still needs to be set to the
- * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
- * the TCSS configuration on state changes.
- */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
-};
-
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
-};
-
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-/*
- * Set up support for the USB3 daughterboard:
- *   Parade PS8815 TCPC (integrated retimer)
- *   Diodes PI3USB9201 BC 1.2 chip (same as USB4 board)
- *   Silergy SYV682A PPC (same as USB4 board)
- *   Virtual mux with stacked retimer
- */
-static void config_db_usb3_active(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_p1_usb3;
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_active;
-}
-
-/*
- * Set up support for the passive USB3 daughterboard:
- *   TUSB422 TCPC (already the default)
- *   PI3USB9201 BC 1.2 chip (already the default)
- *   Silergy SYV682A PPC (already the default)
- *   Virtual mux without stacked retimer
- */
-
-static void config_db_usb3_passive(void)
-{
-	usb_muxes[USBC_PORT_C1] = mux_config_p1_usb3_passive;
-}
-
-static void config_port_discrete_tcpc(int port)
-{
-	/*
-	 * Support 2 Pin-to-Pin compatible parts: TUSB422 and RT1715, for
-	 * simplicity allow either and decide at runtime which we are using.
-	 * Default to TUSB422, and switch to RT1715 if it is on the I2C bus and
-	 * the VID matches.
-	 */
-
-	int regval;
-
-	if (i2c_read16(port ? I2C_PORT_USB_C1 : I2C_PORT_USB_C0,
-		       RT1715_I2C_ADDR_FLAGS, TCPC_REG_VENDOR_ID,
-		       &regval) == EC_SUCCESS) {
-		if (regval == RT1715_VENDOR_ID) {
-			CPRINTS("C%d: RT1715 detected", port);
-			tcpc_config[port].i2c_info.addr_flags =
-				RT1715_I2C_ADDR_FLAGS;
-			tcpc_config[port].drv = &rt1715_tcpm_drv;
-			return;
-		}
-	}
-	CPRINTS("C%d: Default to TUSB422", port);
-}
-
-static const char *db_type_prefix = "USB DB type: ";
-void config_usb3_db_type(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	config_port_discrete_tcpc(0);
-	switch (usb_db) {
-	case DB_USB_ABSENT:
-		CPRINTS("%sNone", db_type_prefix);
-		break;
-	case DB_USB4_GEN2:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen1/2", db_type_prefix);
-		break;
-	case DB_USB4_GEN3:
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB4 Gen3", db_type_prefix);
-		break;
-	case DB_USB3_ACTIVE:
-		config_db_usb3_active();
-		CPRINTS("%sUSB3 Active", db_type_prefix);
-		break;
-	case DB_USB3_PASSIVE:
-		config_db_usb3_passive();
-		config_port_discrete_tcpc(1);
-		CPRINTS("%sUSB3 Passive", db_type_prefix);
-		break;
-	default:
-		CPRINTS("%sID %d not supported", db_type_prefix, usb_db);
-	}
-}
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		sn5s330_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	if (port == USBC_PORT_C1) {
-		if (usb_db == DB_USB4_GEN2) {
-			/*
-			 * Older boards violate 205mm trace length prior
-			 * to connection to the re-timer and only support up
-			 * to GEN2 speeds.
-			 */
-			return TBT_SS_U32_GEN1_GEN2;
-		} else if (usb_db == DB_USB4_GEN3) {
-			return TBT_SS_TBT_GEN3;
-		}
-	}
-
-	/*
-	 * Thunderbolt-compatible mode not supported
-	 *
-	 * TODO (b/147726366): All the USB-C ports need to support same speed.
-	 * Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return TBT_SS_RES_0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/*
-	 * Volteer reference design only supports TBT & USB4 on port 1
-	 * if the USB4 DB is present.
-	 *
-	 * TODO (b/147732807): All the USB-C ports need to support same
-	 * features. Need to fix once USB-C feature set is known for Volteer.
-	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
-}
-
-static void ps8815_reset(void)
-{
-	int val;
-
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
-	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
-	msleep(PS8815_FW_INIT_DELAY_MS);
-
-	/*
-	 * b/144397088
-	 * ps8815 firmware 0x01 needs special configuration
-	 */
-
-	CPRINTS("%s: patching ps8815 registers", __func__);
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f was %02x", val);
-
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f set to 0x31");
-
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8751_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
-		CPRINTS("ps8815: reg 0x0f now %02x", val);
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum ec_cfg_usb_db_type usb_db = ec_cfg_usb_db_type();
-
-	/* No reset available for TCPC on port 0 */
-	/* Daughterboard specific reset for port 1 */
-	if (usb_db == DB_USB3_ACTIVE) {
-		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	}
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-/******************************************************************************/
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/volteer/usbc_config.h b/board/volteer/usbc_config.h
deleted file mode 100644
index 55dfce7621..0000000000
--- a/board/volteer/usbc_config.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* volteer board-specific USB-C configuration */
-
-#ifndef __CROS_EC_USBC_CONFIG_H
-#define __CROS_EC_USBC_CONFIG_H
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/* Configure the USB3 daughterboard type */
-void config_usb3_db_type(void);
-
-#endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/volteer/vif_override.xml b/board/volteer/vif_override.xml
deleted file mode 100644
index f871a543e3..0000000000
--- a/board/volteer/vif_override.xml
+++ /dev/null
@@ -1,114 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
-  <Model_Part_Number>Volteer RT1715</Model_Part_Number>
-  <Product_Revision>0</Product_Revision>
-  <TID>0</TID>
-  <Product>
-    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
-    <USB4_Num_Internal_Host_Controllers value="1" />
-    <USB4_Num_PCIe_DN_Bridges value="0" />
-    <USB4RouterList>
-      <Usb4Router>
-        <USB4_Router_ID value="1" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="4" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="1" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="4" />
-        <USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="true" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-        <USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
-        <USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
-        <USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
-      </Usb4Router>
-      <Usb4Router>
-        <USB4_Router_ID value="0" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="2" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="0" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="0" />
-        <USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="false" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-      </Usb4Router>
-    </USB4RouterList>
-  </Product>
-  <Component>
-    <!-- Port 0 is USB3-only. -->
-    <USB4_Supported value="false">NO</USB4_Supported>
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <DFP_VDO_Port_Number value="0" />
-    <Modal_Operation_Supported_SOP value="false" />
-  </Component>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="1" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-</VIF>
diff --git a/board/volteer_apmodeentry b/board/volteer_apmodeentry
deleted file mode 120000
index f2f3e1d253..0000000000
--- a/board/volteer_apmodeentry
+++ /dev/null
@@ -1 +0,0 @@
-volteer
\ No newline at end of file
diff --git a/board/volteer_ish/board.c b/board/volteer_ish/board.c
deleted file mode 100644
index 76c127056b..0000000000
--- a/board/volteer_ish/board.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer ISH board-specific configuration */
-
-#include "console.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accel_bma2x2.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "task.h"
-
-#include "gpio_list.h" /* has to be included last */
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Sensor config */
-static struct mutex g_lid_mutex;
-
-/* sensor private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* Drivers */
-/* TODO(b/146144170): Implement rotation matrix once sensor moves to lid */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = NULL, /* Update when matrix available */
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-int chipset_in_state(int state_mask)
-{
-	return state_mask & CHIPSET_STATE_ON;
-}
-
-int chipset_in_or_transitioning_to_state(int state_mask)
-{
-	return state_mask & CHIPSET_STATE_ON;
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-}
-
-int board_idle_task(void *unused)
-{
-	while (1)
-		task_wait_event(-1);
-}
diff --git a/board/volteer_ish/board.h b/board/volteer_ish/board.h
deleted file mode 100644
index 097ee25750..0000000000
--- a/board/volteer_ish/board.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer ISH board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/*
- * Allow dangerous commands.
- * TODO: Don't use this on production systems.
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/*
- * By default, enable all console messages except HC, ACPI and event
- * The sensor stack is generating a lot of activity.
- */
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-
-/* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
-#define CONFIG_CLOCK_CRYSTAL
-#define CONFIG_ISH_UART_0
-/* EC */
-#define CONFIG_FLASH_SIZE_BYTES 0x80000
-#define CONFIG_FPU
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_BMA255
-
-/* Host command over HECI */
-#define CONFIG_HOSTCMD_HECI
-
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HECI
-
-#define CONFIG_ACCEL_INTERRUPTS
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is in power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 512
-/* Depends on how fast the AP boots and typical ODRs */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
-
-/* I2C ports */
-#define I2C_PORT_SENSOR ISH_I2C1
-#define CONFIG_CMD_I2C_XFER
-
-/* EC Console Commands */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_CMD_TIMERINFO
-
-/* Undefined features */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_KEYBOARD
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_CMD_SHMEM
-#undef CONFIG_EXTPOWER
-#undef CONFIG_KEYBOARD_KSO_BASE
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FMAP
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_SWITCH
-#undef CONFIG_WATCHDOG
-
-/* Modules we want to exclude */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_TEMP_SENSOR
-#undef CONFIG_ADC
-#undef CONFIG_SHA256
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	SENSOR_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/volteer_ish/build.mk b/board/volteer_ish/build.mk
deleted file mode 100644
index 74ec3c865f..0000000000
--- a/board/volteer_ish/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=ish
-CHIP_FAMILY:=ish5
-CHIP_VARIANT:=ish5p4
-
-board-y=board.o
diff --git a/board/volteer_ish/ec.tasklist b/board/volteer_ish/ec.tasklist
deleted file mode 100644
index a4db486e9a..0000000000
--- a/board/volteer_ish/ec.tasklist
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_NOTEST(CHIPSET, board_idle_task, NULL, IDLE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(HECI_RX, heci_rx_task, NULL, HUGE_TASK_STACK_SIZE, 0) \
-	TASK_ALWAYS(IPC_MNG, ipc_mng_task, NULL, LARGER_TASK_STACK_SIZE, 0)
diff --git a/board/volteer_ish/gpio.inc b/board/volteer_ish/gpio.inc
deleted file mode 100644
index 286309e388..0000000000
--- a/board/volteer_ish/gpio.inc
+++ /dev/null
@@ -1,12 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * We don't have a ENTERING_RW signal wired to the cr50 but common code needs
- * it to be defined.
- */
-UNIMPLEMENTED(ENTERING_RW)
diff --git a/board/volteer_npcx797fc b/board/volteer_npcx797fc
deleted file mode 120000
index f2f3e1d253..0000000000
--- a/board/volteer_npcx797fc
+++ /dev/null
@@ -1 +0,0 @@
-volteer
\ No newline at end of file
diff --git a/board/voxel/battery.c b/board/voxel/battery.c
deleted file mode 100644
index 4f51b79ad9..0000000000
--- a/board/voxel/battery.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Volteer battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* COSMX AP20CBL Battery Information */
-	 [BATTERY_COSMX_AP20CBL] = {
-		.fuel_gauge = {
-			.manuf_name = "COSMX KT0030B002",
-			.device_name = "AP20CBL",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP19B8M;
diff --git a/board/voxel/board.c b/board/voxel/board.c
deleted file mode 100644
index 830300620f..0000000000
--- a/board/voxel/board.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board-specific configuration */
-#include "button.h"
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/als_tcs3400.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tusb422.h"
-#include "driver/tcpm/rt1715.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/sync.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "throttle_ap.h"
-#include "uart.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static const struct ec_response_keybd_config zbu_new_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,
-		TK_REFRESH,
-		TK_FULLSCREEN,
-		TK_OVERVIEW,
-		TK_SNAPSHOT,
-		TK_BRIGHTNESS_DOWN,
-		TK_BRIGHTNESS_UP,
-		TK_VOL_MUTE,
-		TK_VOL_DOWN,
-		TK_VOL_UP,
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-static const struct ec_response_keybd_config zbu_old_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
-{
-	if (get_board_id() > 2)
-		return &zbu_new_kb;
-	else
-		return &zbu_old_kb;
-}
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/*
- * We have total 30 pins for keyboard connecter {-1, -1} mean
- * the N/A pin that don't consider it and reserve index 0 area
- * that we don't have pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
-};
-const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
-
-__override uint32_t board_override_feature_flags0(uint32_t flags0)
-{
-	/*
-	 * Remove keyboard backlight feature for devices that don't support it.
-	 */
-	if (!ec_cfg_has_keyboard_backlight())
-		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
-	else
-		return flags0;
-}
-
-/******************************************************************************/
-/*
- * FW_CONFIG defaults for Voxel if the CBI data is not initialized.
- */
-union volteer_cbi_fw_config fw_config_defaults = {
-	.usb_db = DB_USB4_GEN3,
-};
-
-/******************************************************************************/
-/* Physical fans. These are logically separate from pwm_channels. */
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = GPIO_EN_PP5000_FAN,
-};
-
-/*
- * Fan specs from datasheet:
- * Max speed 5900 rpm (+/- 7%), minimum duty cycle 30%.
- * Minimum speed not specified by RPM. Set minimum RPM to max speed (with
- * margin) x 30%.
- *    5900 x 1.07 x 0.30 = 1894, round up to 1900
- * reference that temperature and fan settings
- * are derived from data in b/167523658#39
- */
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2100,
-	.rpm_start = 2100,
-	.rpm_max = 5800,
-};
-
-const struct fan_t fans[FAN_CH_COUNT] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-
-/******************************************************************************/
-/* EC thermal management configuration */
-
-/*
- * Reference that temperature and fan settings
- * are derived from data in b/167523658#39
- */
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(75),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(68),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(90),
-};
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_CHARGER]			= thermal_cpu,
-	[TEMP_SENSOR_2_PP3300_REGULATOR]	= thermal_cpu,
-	[TEMP_SENSOR_3_DDR_SOC]			= thermal_cpu,
-	[TEMP_SENSOR_4_FAN]			= thermal_cpu,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-/******************************************************************************/
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-/******************************************************************************/
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C0_SENSOR_SCL,
-		.sda = GPIO_EC_I2C0_SENSOR_SDA,
-	},
-	{
-		.name = "usb_c0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda = GPIO_EC_I2C1_USB_C0_SDA,
-	},
-	{
-		.name = "usb_c1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 1000,
-		.scl = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda = GPIO_EC_I2C2_USB_C1_SDA,
-	},
-	{
-		.name = "usb_0_mix",
-		.port = I2C_PORT_USB_0_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-	},
-	{
-		.name = "usb_1_mix",
-		.port = I2C_PORT_USB_1_MIX,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C4_USB_1_MIX_SCL,
-		.sda = GPIO_EC_I2C4_USB_1_MIX_SDA,
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C5_POWER_SCL,
-		.sda = GPIO_EC_I2C5_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C7_EEPROM_SCL,
-		.sda = GPIO_EC_I2C7_EEPROM_SDA,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/******************************************************************************/
-/* PWM configuration */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void kb_backlight_enable(void)
-{
-	if (ec_cfg_has_keyboard_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kb_backlight_enable, HOOK_PRIO_DEFAULT);
-
-static void kb_backlight_disable(void)
-{
-	if (ec_cfg_has_keyboard_backlight())
-		gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
-
-/* Config TCPC dynamic by Board version */
-static void setup_board_tcpc(void)
-{
-	uint8_t board_id = get_board_id();
-
-	if (board_id == 0) {
-		/* config typec C0 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
-		tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv;
-		/* config typec C1 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C1].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
-		tcpc_config[USBC_PORT_C1].drv = &tusb422_tcpm_drv;
-	}
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Only the Burnside Bridge retimers provide a reset pin, but this is
-	 * already handled by the bb_retimer.c driver.
-	 */
-}
-
-/******************************************************************************/
-/* USB-A charging control */
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_PP5000_USBA,
-};
-
-/******************************************************************************/
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C0_FRS_EN,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-		.frs_en = GPIO_USB_C1_FRS_EN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/******************************************************************************/
-/* PPC support routines */
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-	default:
-		break;
-	}
-}
-
-/* Disable FRS on boards with the SYV682A. FRS only works on the SYV682B. */
-void setup_board_ppc(void)
-{
-	uint8_t board_id = get_board_id();
-
-	if (board_id < 2) {
-		ppc_chips[USBC_PORT_C0].frs_en = 0;
-		ppc_chips[USBC_PORT_C1].frs_en = 0;
-	}
-}
-
-__override void board_cbi_init(void)
-{
-	setup_board_tcpc();
-	setup_board_ppc();
-}
-
-/******************************************************************************/
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC TCPC configuration */
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = RT1715_I2C_ADDR_FLAGS,
-		},
-		.drv = &rt1715_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-/* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_0_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		.usb_ls_en_gpio = GPIO_USB_C0_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL,
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC1.2 interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-/******************************************************************************/
-/* TCPC support routines */
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-}
diff --git a/board/voxel/board.h b/board/voxel/board.h
deleted file mode 100644
index b02716088e..0000000000
--- a/board/voxel/board.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/* Optional features */
-#undef NPCX7_PWM1_SEL
-#define NPCX7_PWM1_SEL    0    /* GPIO C2 is not used as PWM1. */
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-#define CONFIG_VBOOT_EFS2
-
-#define CONFIG_POWER_BUTTON
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Chipset features */
-#define CONFIG_POWER_PP5000_CONTROL
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* Keyboard features */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-
-/* Keyboard backliht */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-
-/* Sensors */
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-/* BMA253 Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCEL_BMA255
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-/*
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#ifdef BOARD_VOXEL_ECMODEENTRY
-#undef CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-#endif
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
-
-/* USB Type A Features */
-#define USB_PORT_COUNT			1
-#define CONFIG_USB_PORT_POWER_DUMB
-
-/* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
-#define CONFIG_USB_PD_FRS_PPC
-
-/* BC 1.2 */
-
-/* TCPC */
-#define CONFIG_USB_PD_TCPM_RT1715
-
-/* Volume Button feature */
-
-/* Fan features */
-
-/* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_RSMRST_L_PGOOD		GPIO_PG_EC_RSMRST_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define CONFIG_I2C_CONTROLLER
-
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_COSMX_AP20CBL,
-	BATTERY_TYPE_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-void board_reset_pd_mcu(void);
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/voxel/build.mk b/board/voxel/build.mk
deleted file mode 100644
index 838d6a16ce..0000000000
--- a/board/voxel/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=volteer
-
-board-y=board.o
-board-y+=battery.o
-board-y+=led.o
-board-y+=sensors.o
diff --git a/board/voxel/ec.tasklist b/board/voxel/ec.tasklist
deleted file mode 100644
index 292de51cdb..0000000000
--- a/board/voxel/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/voxel/gpio.inc b/board/voxel/gpio.inc
deleted file mode 100644
index fa3d0ffe7d..0000000000
--- a/board/voxel/gpio.inc
+++ /dev/null
@@ -1,186 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* Power sequencing interrupts */
-GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#endif
-GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_RSMRST_ODL,     PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_DSW_PWROK,      PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD,  PIN(F, 4),  GPIO_INT_BOTH, power_signal_interrupt)
-
-/* Sensor Interrupts */
-GPIO_INT(EC_IMU_INT_L,         PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO(EC_ALS_RGB_INT_L,         PIN(D, 4), GPIO_INPUT | GPIO_PULL_UP)	/* unused */
-GPIO_INT(TABLET_MODE_L,        PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-/*
- * Lid g-sensor interrupt unused on Voxel, configure as regular input for
- * power saving.
- */
-GPIO(EC_ACCEL_INT,		PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_BOTH, tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(A, 2), GPIO_INT_BOTH, tcpc_alert_event)
-
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(6, 2), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(F, 5), GPIO_INT_BOTH, ppc_interrupt)
-
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(E, 4), GPIO_INT_BOTH, bc12_interrupt)
-GPIO_INT(USB_C1_MIX_INT_ODL,	PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt)
-
-/* HDMI interrupts */
-
-/* Volume button interrupts */
-GPIO_INT(EC_VOLDN_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,		PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Power Sequencing Signals */
-GPIO(EN_PP3300_A,              PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_A,              PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_PPVAR_VCCIN,           PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */
-GPIO(EC_PCH_DSW_PWROK,         PIN(C, 0), GPIO_OUT_LOW)
-
-/* Other wake sources */
-/*
- * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an
- * interrupt handler because it is automatically handled by the PSL.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH |
-					   GPIO_HIB_WAKE_HIGH |
-					   GPIO_LOCKED)
-
-/* AP/PCH Signals */
-GPIO(EC_PCH_SYS_PWROK,         PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_RSMRST_ODL,        PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */
-GPIO(EC_PCH_PWR_BTN_ODL,       PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RTCRST,            PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_ODL,          PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,           PIN(6, 3), GPIO_ODR_HIGH)
-GPIO_INT(EC_PROCHOT_IN_L,      PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-
-GPIO(EC_PCH_INT_ODL,           PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(CPU_C10_GATE_L,           PIN(6, 7), GPIO_INPUT)
-
-/* USB and USBC Signals */
-GPIO(EN_PP5000_USBA,		PIN(3, 5), GPIO_OUT_LOW)	/* Enable USB-A charging - all ports */
-GPIO(USB_A_LOW_PWR_OD,		PIN(6, 6), GPIO_ODR_LOW)	/* Don't limit USB-A charging by default - all ports */
-
-/*
- * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1.
- * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1
- * so it's safe to define GPIOs compatible with both designs.
- * TODO (b/149858568): remove board ID=0 support.
- */
-GPIO(USB_C0_RT_RST_ODL,			PIN(4, 1), GPIO_ODR_LOW)
-GPIO(USB_C1_RT_RST_ODL,			PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */
-GPIO(USB_C0_OC_ODL,			PIN(B, 1), GPIO_ODR_HIGH)
-GPIO(USB_C1_OC_ODL,			PIN(5, 0), GPIO_ODR_HIGH)
-GPIO(USB_C0_RT_INT_ODL,			PIN(C, 6), GPIO_INPUT)
-GPIO(USB_C1_RT_INT_ODL,			PIN(9, 6), GPIO_INPUT)
-GPIO(USB_C0_FRS_EN,			PIN(C, 2), GPIO_OUT_LOW)
-GPIO(USB_C1_FRS_EN,			PIN(9, 4), GPIO_OUT_LOW)
-
-/* Don't have a load switch for retimer */
-UNIMPLEMENTED(USB_C0_LS_EN)
-UNIMPLEMENTED(USB_C1_LS_EN)
-
-/* Misc Signals */
-GPIO(EC_H1_PACKET_MODE,		PIN(7, 5), GPIO_OUT_LOW)	/* H1 Packet Mode */
-GPIO(LED_1_L,                  PIN(C, 4), GPIO_OUT_HIGH)        /* Blue */
-GPIO(LED_2_L,                  PIN(C, 3), GPIO_OUT_HIGH)        /* Yellow */
-GPIO(EC_KB_BL_EN,		PIN(8, 6), GPIO_OUT_LOW)	/* Keyboard backlight enable*/
-
-GPIO(M2_SSD_PLN,        PIN(A, 0), GPIO_ODR_HIGH)	/* SSD power-loss notification */
-GPIO(M2_SSD_PLA,        PIN(7, 0), GPIO_INPUT)		/* SSD power-loss acknowledgment */
-GPIO(CCD_MODE_ODL,      PIN(E, 5), GPIO_INPUT)		/* Case Closed Debug Mode */
-GPIO(EC_SLP_S0IX,       PIN(7, 2), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Unused signals */
-GPIO(UNUSED_GPIO34,     PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIO60,     PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(UNUSED_GPIOA7,     PIN(A, 7), GPIO_INPUT | GPIO_PULL_UP)
-
-/*
- * eDP backlight - both PCH and EC have enable pins that must be high
- * for the backlight to turn on. Default state is high, and can be turned
- * off during sleep states.
- */
-GPIO(EC_EDP_BL_EN,             PIN(D, 3), GPIO_OUT_HIGH)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SCL,    PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C4_USB_1_MIX_SDA,    PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Battery signals */
-GPIO(EC_BATT_PRES_ODL, 		PIN(E, 1), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-
-/* Fan signals */
-GPIO(EN_PP5000_FAN,            PIN(6, 1), GPIO_OUT_LOW)
-ALTERNATE(PIN_MASK(B, BIT(7)), 0, MODULE_PWM, 0)	/* FAN_PWM */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)	/* FAN_SPEED_TACH */
-
-/* Keyboard pins */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7),                        GPIO_OUT_LOW)  /* KSO_02 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)                     /* EC_KB_BL_PWM */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, BIT(5) | BIT(4)), 0, MODULE_UART, 0)                           /* UART from EC to Servo */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)                    /* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)  /* GPIO00 = ACOK_OD,
-                                                                       GPIO01 = H1_EC_PWR_BTN_ODL
-                                                                       GPIO02 = EC_RST_ODL */
-
-/* Temperature sensors */
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* TEMP_SENSOR1,2,4 */
-ALTERNATE(PIN(F, 1), 0, MODULE_ADC, 0) /* TEMP_SENSOR3 */
diff --git a/board/voxel/led.c b/board/voxel/led.c
deleted file mode 100644
index 4be69689f7..0000000000
--- a/board/voxel/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Volteer
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_2_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_1_L, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_1_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_2_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/voxel/sensors.c b/board/voxel/sensors.c
deleted file mode 100644
index 9652463ae2..0000000000
--- a/board/voxel/sensors.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Volteer family-specific sensor configuration */
-#include "common.h"
-#include "accelgyro.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/als_tcs3400.h"
-#include "driver/sync.h"
-#include "keyboard_scan.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-/******************************************************************************/
-/* Sensors */
-static struct mutex g_lid_accel_mutex;
-static struct mutex g_base_mutex;
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data g_kx022_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_accel_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_accel_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.default_range = 2, /* g, to support tablet mode */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.default_range = 4, /* g */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on in S3 */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_sensors_init(void)
-{
-	if (ec_cfg_has_tabletmode()) {
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_BASE_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			ccprints("BASE GYRO is ICM426XX");
-		} else
-			ccprints("BASE GYRO is BMI160");
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_LID_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			ccprints("LID_ACCEL is KX022");
-		} else
-			ccprints("LID_ACCEL is BMA253");
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable interrupt for the accel/gyro sensor */
-		gpio_enable_interrupt(GPIO_EC_IMU_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (get_cbi_ssfc_base_sensor()) {
-	case SSFC_SENSOR_BASE_ICM426XX:
-		icm426xx_interrupt(signal);
-		break;
-	case SSFC_SENSOR_BASE_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
diff --git a/board/voxel/vif_override.xml b/board/voxel/vif_override.xml
deleted file mode 100644
index 3fc41630da..0000000000
--- a/board/voxel/vif_override.xml
+++ /dev/null
@@ -1,158 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
-  <Model_Part_Number>Voxel</Model_Part_Number>
-  <Product_Revision>0</Product_Revision>
-  <TID>0</TID>
-  <Product>
-    <!-- Information about TGL USB4 provided by Intel. See b/172963736 -->
-    <USB4_Num_Internal_Host_Controllers value="1" />
-    <USB4_Num_PCIe_DN_Bridges value="0" />
-    <USB4RouterList>
-      <Usb4Router>
-        <USB4_Router_ID value="1" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="4" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="1" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="4" />
-        <USB4_TBT3_Not_Supported value="0">TBT3 Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="true" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-        <USB4_TBT3_VID value="32903">8087</USB4_TBT3_VID>
-        <USB4_PCIe_Switch_Vendor_ID value="32902">8086</USB4_PCIe_Switch_Vendor_ID>
-        <USB4_PCIe_Switch_Device_ID value="39451">9A1B</USB4_PCIe_Switch_Device_ID>
-      </Usb4Router>
-      <Usb4Router>
-        <USB4_Router_ID value="0" />
-        <USB4_Silicon_VID value="32903">8087</USB4_Silicon_VID>
-        <USB4_Num_Lane_Adapters value="2" />
-        <USB4_Num_USB3_DN_Adapters value="1" />
-        <USB4_Num_DP_IN_Adapters value="0" />
-        <USB4_Num_DP_OUT_Adapters value="0" />
-        <USB4_Num_PCIe_DN_Adapters value="0" />
-        <USB4_TBT3_Not_Supported value="1">Not TBT3-Compatible</USB4_TBT3_Not_Supported>
-        <USB4_PCIe_Wake_Supported value="false" />
-        <USB4_USB3_Wake_Supported value="false" />
-        <USB4_Num_Unused_Adapters value="0" />
-      </Usb4Router>
-    </USB4RouterList>
-  </Product>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="0" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-  <Component>
-    <USB4_Max_Speed value="1">Gen 3 (40Gb)</USB4_Max_Speed>
-    <USB4_DFP_Supported value="true" />
-    <USB4_UFP_Supported value="false" />
-    <USB4_USB3_Tunneling_Supported value="true" />
-    <USB4_DP_Tunneling_Supported value="true" />
-    <USB4_PCIe_Tunneling_Supported value="true" />
-    <USB4_TBT3_Compatibility_Supported value="true" />
-    <USB4_CL1_State_Supported value="true" />
-    <USB4_CL2_State_Supported value="true" />
-    <USB4_Num_Retimers value="1" />
-    <USB4_DP_Bit_Rate value="3">HBR3</USB4_DP_Bit_Rate>
-    <USB4_Num_DP_Lanes value="4">4 Lanes</USB4_Num_DP_Lanes>
-    <USB4_Lane_0_Adapter value="1" />
-    <Host_Supports_USB_Data value="true" />
-    <Host_Speed value="2">USB 3.2 Gen 2x1</Host_Speed>
-    <Host_Contains_Captive_Retimer value="true" />
-    <Host_Truncates_DP_For_tDHPResponse value="false" />
-    <Host_Suspend_Supported value="true" />
-    <Is_DFP_On_Hub value="false" />
-    <USB_Suspend_May_Be_Cleared value="true" />
-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="3">3A @ 5V</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
-    <FR_Swap_Supported_As_Initial_Sink value="true" />
-    <SrcPdoList>
-      <SrcPDO>
-        <!-- Add in missing fields for SrcPdo0, derived from SYV682B datasheet. -->
-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>
-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>
-      </SrcPDO>
-    </SrcPdoList>
-    <Data_Capable_As_USB_Host_SOP value="true" />
-    <Data_Capable_As_USB_Device_SOP value="false" />
-    <!-- TODO(b/173028252): Figure out the appropriate Discover Identity ACK for
-         Volteer and update the EC and VIF accordingly. -->
-    <Product_Type_UFP_SOP value="3">PSD</Product_Type_UFP_SOP>
-    <Product_Type_DFP_SOP value="4">Alternate Mode Controller (AMC)</Product_Type_DFP_SOP>
-    <DFP_VDO_Port_Number value="1" />
-    <Modal_Operation_Supported_SOP value="true" />
-    <USB_VID_SOP value="6353">18D1</USB_VID_SOP>
-    <bcdDevice_SOP value="0">0000</bcdDevice_SOP>
-    <SVID_Fixed_SOP value="true" />
-    <Num_SVIDs_Min_SOP value="1" />
-    <Num_SVIDs_Max_SOP value="1" />
-    <SOPSVIDList>
-      <SOPSVID>
-        <SVID_SOP value="32903">8087</SVID_SOP>
-        <SVID_Modes_Fixed_SOP value="true" />
-        <SVID_Num_Modes_Min_SOP value="1" />
-        <SVID_Num_Modes_Max_SOP value="1" />
-        <SOPSVIDModeList>
-          <SOPSVIDMode>
-            <SVID_Mode_Enter_SOP value="true" />
-            <SVID_Mode_Recog_Value_SOP value="0">00000000</SVID_Mode_Recog_Value_SOP>
-          </SOPSVIDMode>
-        </SOPSVIDModeList>
-      </SOPSVID>
-    </SOPSVIDList>
-  </Component>
-</VIF>
diff --git a/board/voxel_ecmodeentry b/board/voxel_ecmodeentry
deleted file mode 120000
index 082df00bc3..0000000000
--- a/board/voxel_ecmodeentry
+++ /dev/null
@@ -1 +0,0 @@
-voxel
\ No newline at end of file
diff --git a/board/voxel_npcx797fc b/board/voxel_npcx797fc
deleted file mode 120000
index 082df00bc3..0000000000
--- a/board/voxel_npcx797fc
+++ /dev/null
@@ -1 +0,0 @@
-voxel
\ No newline at end of file
diff --git a/board/waddledee/battery.c b/board/waddledee/battery.c
deleted file mode 100644
index 6b77248624..0000000000
--- a/board/waddledee/battery.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all waddledee battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo AP13J7K Battery Information */
-	[BATTERY_SMP_AP13J7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "AP13J7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AC15A3J Battery Information */
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP19A8K Battery Information */
-	[BATTERY_LGC_AP19A8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KTxxxxGxxx",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC KT0030G023 Battery Information */
-	[BATTERY_LGC_G023] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G023",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC15A3J;
diff --git a/board/waddledee/board.c b/board/waddledee/board.c
deleted file mode 100644
index 1e4f8a387c..0000000000
--- a/board/waddledee/board.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C1 interrupt line swapped between board versions, track it in a variable */
-static enum gpio_signal c1_int_line;
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(1);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(c1_int_line)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-
-/* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	},
-};
-
-void board_init(void)
-{
-	int on;
-
-	if (system_get_board_version() <= 0) {
-		pd_set_max_voltage(5000);
-		c1_int_line = GPIO_USB_C1_INT_V0_ODL;
-	} else {
-		c1_int_line = GPIO_USB_C1_INT_V1_ODL;
-	}
-
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(c1_int_line);
-
-	/*
-	 * If interrupt lines are already low, schedule them to be processed
-	 * after inits are completed.
-	 */
-	check_c0_line();
-	check_c1_line();
-
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-	/* Enable Base Accel interrupt */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	/* Charger on the sub-board will be a push-pull GPIO */
-	sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-static void board_resume(void)
-{
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
-
-static void board_suspend(void)
-{
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-	if (sm5803_set_gpio0_level(1, !!enable))
-		CPRINTUSB("Failed to %sable sub rails!", enable ? "en" : "dis");
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(c1_int_line)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 14;
-
-	*ki = 3;
-	*ki_div = 500;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > CONFIG_USB_PD_PORT_MAX_COUNT)
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	charger_set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_BLUE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	}
-
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct kionix_accel_data  g_kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/waddledee/board.h b/board/waddledee/board.h
deleted file mode 100644
index 259786f95c..0000000000
--- a/board/waddledee/board.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this will only be valid for board revision 1
- */
-#define GPIO_USB_C1_INT_ODL GPIO_USB_C1_INT_V1_ODL
-
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 1
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_BLUE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_SMP_AP13J7K,
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_LGC_AP19A8K,
-	BATTERY_LGC_G023,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledee/build.mk b/board/waddledee/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/waddledee/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/waddledee/cbi_ssfc.c b/board/waddledee/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/waddledee/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/waddledee/cbi_ssfc.h b/board/waddledee/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/waddledee/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledee/ec.tasklist b/board/waddledee/ec.tasklist
deleted file mode 100644
index 2edf48ee05..0000000000
--- a/board/waddledee/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/waddledee/gpio.inc b/board/waddledee/gpio.inc
deleted file mode 100644
index 63e0055199..0000000000
--- a/board/waddledee/gpio.inc
+++ /dev/null
@@ -1,138 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_V0_ODL,	PIN(B, 5), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12  - board version 0 */
-GPIO_INT(USB_C1_INT_V1_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12  - board version 1 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-GPIO(EN_USB_A0_VBUS,		PIN(L, 6), GPIO_OUT_LOW) /* Board rev 1, NC board rev 0 */
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_1, PIN(L, 3), GPIO_INPUT)
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(PEN_DET_ODL,		PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0)), 0, MODULE_ADC, 0)			/* ADC13: EC_SUB_ANALOG */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0) | BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* KB_BL_PWM, LED_[R,G,B]_ODL */
diff --git a/board/waddledee/led.c b/board/waddledee/led.c
deleted file mode 100644
index 058d23d761..0000000000
--- a/board/waddledee/led.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledee specific PWM LED settings. */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * Board has one physical LED with red, green, and blue
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
-};
-
-/* One logical LED with red, green, and blue channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED_RED,
-		.ch1 = PWM_CH_LED_GREEN,
-		.ch2 = PWM_CH_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_YELLOW] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/waddledee/usb_pd_policy.c b/board/waddledee/usb_pd_policy.c
deleted file mode 100644
index 7046e25d6c..0000000000
--- a/board/waddledee/usb_pd_policy.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	prev_en = charger_is_sourcing_otg_power(port);
-
-	/* Disable Vbus */
-	charger_enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable sinking */
-	rv = sm5803_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	charger_enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return sm5803_is_vbus_present(port);
-}
diff --git a/board/waddledee/vif_override.xml b/board/waddledee/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/waddledee/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/waddledoo/battery.c b/board/waddledoo/battery.c
deleted file mode 100644
index 64af3b4302..0000000000
--- a/board/waddledoo/battery.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all waddledoo battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* POW-TECH Battery Information */
-	[BATTERY_POWER_TECH] = {
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr       = 0x00,
-				.reg_mask       = 0x2000,
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 8800,    /* mV */
-			.voltage_normal       = 7700,
-			.voltage_min          = 6000,
-			.precharge_current    = 160,       /* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 45,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 60,
-		},
-
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
diff --git a/board/waddledoo/board.c b/board/waddledoo/board.c
deleted file mode 100644
index f2eea52701..0000000000
--- a/board/waddledoo/board.c
+++ /dev/null
@@ -1,681 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/retimer/nb7v904m.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
-}
-
-static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
-{
-	int hdmi_hpd_odl = gpio_get_level(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-
-	gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, !hdmi_hpd_odl);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-void board_init(void)
-{
-	int on;
-
-	/* Enable C0 interrupt and check if it needs processing */
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	check_c0_line();
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-
-		/* Set HDMI and sub-rail enables to output */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
-			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
-
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-
-		/* Enable interrupt for passing through HPD */
-		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
-	} else {
-		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
-
-		/* Enable C1 interrupt and check if it needs processing */
-		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
-		check_c1_line();
-	}
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/* Enable HDMI any time the SoC is on */
-static void hdmi_enable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hdmi_enable, HOOK_PRIO_DEFAULT);
-
-static void hdmi_disable(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		gpio_set_level(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	if (board_get_charger_chip_count() > 1)
-		raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-#ifdef BOARD_WADDLEDOO
-static void reconfigure_5v_gpio(void)
-{
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (system_get_board_version() < 0) {
-		CPRINTS("old board - remapping 5V en");
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
-#endif /* BOARD_WADDLEDOO */
-
-static void set_5v_gpio(int level)
-{
-	int version;
-	enum gpio_signal gpio = GPIO_EN_PP5000;
-
-	/*
-	 * b/147257497: On early waddledoo boards, GPIO_EN_PP5000 was swapped
-	 * with GPIO_VOLUP_BTN_ODL. Therefore, we'll actually need to set that
-	 * GPIO instead for those boards.  Note that this breaks the volume up
-	 * button functionality.
-	 */
-	if (IS_ENABLED(BOARD_WADDLEDOO)) {
-		version = system_get_board_version();
-
-		/*
-		 * If the CBI EEPROM wasn't formatted, assume it's a very early
-		 * board.
-		 */
-		gpio = version < 0 ? GPIO_VOLUP_BTN_ODL : GPIO_EN_PP5000;
-	}
-
-	gpio_set_level(gpio, level);
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC, or send enable signal to HDMI
-	 * DB.
-	 */
-	set_5v_gpio(!!enable);
-
-	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
-		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
-	} else {
-		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
-	}
-
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__override uint8_t board_get_charger_chip_count(void)
-{
-	if (get_cbi_fw_config_db() == DB_1A_HDMI)
-		return CHARGER_NUM - 1;
-	else
-		return CHARGER_NUM;
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-			raa489000_enable_asgate(i, false);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-
-	[PWM_CH_LED1_AMBER] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq = 2400,
-	},
-
-	[PWM_CH_LED2_WHITE] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq = 2400,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-};
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	}
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h
deleted file mode 100644
index bf253e65d4..0000000000
--- a/board/waddledoo/board.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_DEDEDE_EC_NPCX796FC
-#include "baseboard.h"
-
-/*
- * Keep the system unlocked in early development.
- * TODO(b/151264302): Make sure to remove this before production!
- */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* Save some flash space */
-#define CONFIG_CHIP_INIT_ROM_REGION
-#undef  CONFIG_CONSOLE_CMDHELP
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#define CONFIG_USB_PD_DEBUG_LEVEL 2
-
-/* EC console commands */
-#define CONFIG_CMD_CHARGER_DUMP
-
-/* Remove default commands to free flash space */
-#undef CONFIG_CMD_ACCELSPOOF
-#undef CONFIG_CMD_BATTFAKE
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/*
- * GPIO for C1 interrupts, for baseboard use
- *
- * Note this line might already have its pull up disabled for HDMI DBs, but
- * it should be fine to set again before z-state.
- */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
-
-/* Keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 1
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-#undef CONFIG_LED_PWM_LOW_BATT_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_NB7V904M
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-#undef PD_POWER_SUPPLY_TURN_ON_DELAY
-#undef PD_POWER_SUPPLY_TURN_OFF_DELAY
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-/* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
-#undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/*
- * I2C pin names for baseboard
- *
- * Note: these lines will be set as i2c on start-up, but this should be
- * okay since they're ODL.
- */
-#define GPIO_EC_I2C_SUB_USB_C1_SCL GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL
-#define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED1_AMBER,
-	PWM_CH_LED2_WHITE,
-	PWM_CH_COUNT,
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledoo/build.mk b/board/waddledoo/build.mk
deleted file mode 100644
index d467fee6e6..0000000000
--- a/board/waddledoo/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=dedede
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/waddledoo/cbi_ssfc.c b/board/waddledoo/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/waddledoo/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/waddledoo/cbi_ssfc.h b/board/waddledoo/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/waddledoo/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo/ec.tasklist b/board/waddledoo/ec.tasklist
deleted file mode 100644
index 0aba1fabeb..0000000000
--- a/board/waddledoo/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/waddledoo/gpio.inc b/board/waddledoo/gpio.inc
deleted file mode 100644
index 69f6bc6307..0000000000
--- a/board/waddledoo/gpio.inc
+++ /dev/null
@@ -1,139 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 		PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_C1_INT_EN_RAILS_ODL,		PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt) /* C1 interrupt OR 5V power en */
-GPIO_INT(EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,	PIN(9, 1), GPIO_INT_BOTH, sub_hdmi_hpd_interrupt) /* C1 I2C SDA OR HDMI_HPD */
-
-/* Button interrupts */
-GPIO_INT(H1_EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		 PIN(4, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		 PIN(7, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,			PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,			PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,			PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,			PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,			PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,			PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,	PIN(9, 2), GPIO_INPUT) /* C1 I2C SCL OR HDMI en */
-
-/* Extra Sub-board I/O pins */
-GPIO(EC_SUB_IO_1,  PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(IMVP9_PE,		PIN(E, 0), GPIO_OUT_LOW)
-GPIO(ECH1_PACKET_MODE,	PIN(7, 5), GPIO_OUT_LOW)
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(CCD_MODE_ODL,	     PIN(E, 5), GPIO_ODR_HIGH)
-
-GPIO(USB_C0_RST_ODL,	     PIN(9, 7), GPIO_OUT_HIGH) /* currently unused */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-
-/*
- * Waddledoo doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(C, 0x1C), 0, MODULE_PWM, 0)   /* PWM0-2 */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO41_NC, PIN(4, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/waddledoo/led.c b/board/waddledoo/led.c
deleted file mode 100644
index b9ff2e74e8..0000000000
--- a/board/waddledoo/led.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo specific PWM LED settings. */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-/*
- * We only have a white and an amber LED, so setting any other colour results in
- * both LEDs being off.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
-};
-
-/* One logical LED with amber and white channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1_AMBER,
-		.ch1 = PWM_CH_LED2_WHITE,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/waddledoo/usb_pd_policy.c b/board/waddledoo/usb_pd_policy.c
deleted file mode 100644
index 3190595596..0000000000
--- a/board/waddledoo/usb_pd_policy.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x_public.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	rv = raa489000_enable_asgate(port, true);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/waddledoo/vif_override.xml b/board/waddledoo/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/waddledoo/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/waddledoo2/battery.c b/board/waddledoo2/battery.c
deleted file mode 100644
index 887c66e355..0000000000
--- a/board/waddledoo2/battery.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "gpio.h"
-#include "util.h"
-
-/*
- * Battery info for Waddledoo2 battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-		/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-				.cfet_mask = 0x4000,
-				.cfet_off_val = 0x4000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* AP19B8M */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC_AP18C8K;
diff --git a/board/waddledoo2/board.c b/board/waddledoo2/board.c
deleted file mode 100644
index 68b5783ba8..0000000000
--- a/board/waddledoo2/board.c
+++ /dev/null
@@ -1,851 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo2 board-specific configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cbi_fw_config.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "temp_sensor.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/raa489000.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/usb_mux/pi3usb3x532.h"
-#include "driver/retimer/ps8802.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "stdbool.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define INT_RECHECK_US 5000
-
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
-static uint8_t new_adc_key_state;
-
-static void ps8762_chaddr_deferred(void);
-DECLARE_DEFERRED(ps8762_chaddr_deferred);
-
-/******************************************************************************/
-/* USB-A Configuration */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS,
-	GPIO_EN_USB_A1_VBUS,
-};
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff,  /* full set */
-	},
-};
-
-static const struct ec_response_keybd_config waddledoo2_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &waddledoo2_keybd;
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void check_c0_line(void);
-DECLARE_DEFERRED(check_c0_line);
-
-static void notify_c0_chips(void)
-{
-	/*
-	 * The interrupt line is shared between the TCPC and BC 1.2 detection
-	 * chip.  Therefore we'll need to check both ICs.
-	 */
-	schedule_deferred_pd_interrupt(0);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void check_c0_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		notify_c0_chips();
-		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-	}
-}
-
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c0_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c0_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
-
-static void sub_usb_c1_interrupt(enum gpio_signal s)
-{
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
-
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
-
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
-
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.input_ch = NPCX_ADC_CH9,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_a = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(70),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-const static struct ec_thermal_config thermal_b = {
-	.temp_host = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(73),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(85),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_WARN] = 0,
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(65),
-		[EC_TEMP_THRESH_HALT] = 0,
-	},
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_thermal(void)
-{
-	thermal_params[TEMP_SENSOR_1] = thermal_a;
-	thermal_params[TEMP_SENSOR_2] = thermal_b;
-}
-
-void board_hibernate(void)
-{
-	/*
-	 * Both charger ICs need to be put into their "low power mode" before
-	 * entering the Z-state.
-	 */
-	raa489000_hibernate(1, true);
-	raa489000_hibernate(0, true);
-}
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * TODO(b:147316511): Here we could issue a digital reset to the IC,
-	 * unsure if we actually want to do that or not yet.
-	 */
-}
-
-static void ps8762_chaddr_deferred(void)
-{
-	/* Switch PS8762 I2C Address to 0x50*/
-	if (ps8802_chg_i2c_addr(I2C_PORT_SUB_USB_C1) == EC_SUCCESS)
-		CPRINTS("Switch PS8762 address to 0x50 success");
-	else
-		CPRINTS("Switch PS8762 address to 0x50 failed");
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Port 0 simply has a GPIO to turn on the 5V regulator, however, 5V is
-	 * generated locally on the sub board and we need to set the comparator
-	 * polarity on the sub board charger IC.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
-
-	if (!enable)
-		return;
-	/*
-	 * Port C1 the PP3300_USB_C1  assert, delay 15ms
-	 * colud be accessed PS8762 by I2C.
-	 */
-	hook_call_deferred(&ps8762_chaddr_deferred_data, 15 * MSEC);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	int regval;
-
-	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
-	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int old_port;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	old_port = charge_manager_get_active_charge_port();
-
-	CPRINTS("New chg p%d", port);
-
-	/* Disable all ports. */
-	if (port == CHARGE_PORT_NONE) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-			tcpc_write(i, TCPC_REG_COMMAND,
-				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
-		charger_discharge_on_ac(1);
-
-	/* Enable requested charge port. */
-	if (tcpc_write(port, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		charger_discharge_on_ac(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Allow the charger IC to begin/continue switching. */
-	charger_discharge_on_ac(0);
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * b/147463641: The charger IC seems to overdraw ~4%, therefore we
-	 * reduce our target accordingly.
-	 */
-	icl = icl * 96 / 100;
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	if (port < 0 || port > board_get_usb_pd_port_count())
-		return;
-
-	raa489000_set_output_current(port, rp);
-}
-
-/* Sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-
-/* BMA253 private data */
-static struct accelgyro_saved_data_t g_bma253_data;
-
-/* BMI160 private data */
-static struct bmi_drv_data_t g_bmi160_data;
-
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* ICM426 private data */
-static struct icm_drv_data_t g_icm426xx_data;
-/* KX022 private data */
-static struct kionix_accel_data g_kx022_data;
-
-struct motion_sensor_t kx022_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_KX022,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &kionix_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_kx022_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = KX022_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref,
-	.min_frequency = KX022_ACCEL_MIN_FREQ,
-	.max_frequency = KX022_ACCEL_MAX_FREQ,
-	.default_range = 2, /* g, to support tablet mode */
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 13000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_icm_ref,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,
-		.min_frequency = BMI_ACCEL_MIN_FREQ,
-		.max_frequency = BMI_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMI160,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &bmi160_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = &g_bmi160_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-		.default_range = 1000, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = BMI_GYRO_MIN_FREQ,
-		.max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_SUB_USB_C1_INT_ODL);
-	check_c0_line();
-	check_c1_line();
-
-	/* Enable gpio interrupt for base accelgyro sensor */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	if (get_cbi_fw_config_tablet_mode()) {
-		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
-			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-			cprints(CC_SYSTEM, "BASE GYRO is ICM426XX");
-		} else
-			cprints(CC_SYSTEM, "BASE GYRO is BMI160");
-
-		if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_KX022) {
-			motion_sensors[LID_ACCEL] = kx022_lid_accel;
-			cprints(CC_SYSTEM, "LID_ACCEL is KX022");
-		} else
-			cprints(CC_SYSTEM, "LID_ACCEL is BMA253");
-
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable gpio interrupt for base accelgyro sensor */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	/* Turn on 5V if the system is on, otherwise turn it off. */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
-			      CHIPSET_STATE_SOFT_OFF);
-	board_power_5v_enable(on);
-
-	/* Initialize THERMAL */
-	setup_thermal();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 1;
-	*kp_div = 20;
-	*ki = 1;
-	*ki_div = 250;
-	*kd = 0;
-	*kd_div = 1;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 10000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
-		},
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-		.drv = &raa489000_tcpm_drv,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
-	}
-};
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	int regval;
-
-	/*
-	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
-	 * Therefore, go out and actually read the alert registers to report the
-	 * alert status.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) {
-		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
-			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
-			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_0;
-		}
-	}
-
-	if (!gpio_get_level(GPIO_SUB_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
-			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
-				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
-
-			if (regval)
-				status |= PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-int adc_to_physical_value(enum gpio_signal gpio)
-{
-	if (gpio == GPIO_VOLUME_UP_L)
-		return !!(new_adc_key_state & ADC_VOL_UP_MASK);
-	else if (gpio == GPIO_VOLUME_DOWN_L)
-		return !!(new_adc_key_state & ADC_VOL_DOWN_MASK);
-
-	CPRINTS("Not a volume up or down key");
-	return 0;
-}
-
-int button_is_adc_detected(enum gpio_signal gpio)
-{
-	return (gpio == GPIO_VOLUME_DOWN_L) || (gpio == GPIO_VOLUME_UP_L);
-}
-
-static void adc_vol_key_press_check(void)
-{
-	int volt = adc_read_channel(ADC_SUB_ANALOG);
-	static uint8_t old_adc_key_state;
-	uint8_t adc_key_state_change;
-
-	if (volt > 2400 && volt < 2490) {
-		/* volume-up is pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK;
-	} else if (volt > 2600 && volt < 2690) {
-		/* volume-down is pressed */
-		new_adc_key_state = ADC_VOL_DOWN_MASK;
-	} else if (volt < 2290) {
-		/* both volumn-up and volume-down are pressed */
-		new_adc_key_state = ADC_VOL_UP_MASK | ADC_VOL_DOWN_MASK;
-	} else if (volt > 2700) {
-		/* both volumn-up and volume-down are released */
-		new_adc_key_state = 0;
-	}
-	if (new_adc_key_state != old_adc_key_state) {
-		adc_key_state_change = old_adc_key_state ^ new_adc_key_state;
-		if (adc_key_state_change && ADC_VOL_UP_MASK)
-			button_interrupt(GPIO_VOLUME_UP_L);
-		if (adc_key_state_change && ADC_VOL_DOWN_MASK)
-			button_interrupt(GPIO_VOLUME_DOWN_L);
-
-		old_adc_key_state = new_adc_key_state;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, adc_vol_key_press_check, HOOK_PRIO_DEFAULT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/waddledoo2/board.h b/board/waddledoo2/board.h
deleted file mode 100644
index aefad9b213..0000000000
--- a/board/waddledoo2/board.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Waddledoo2 board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KEEBY_EC_NPCX797FC
-#include "baseboard.h"
-
-/*
- * The RAM and flash size combination on the the NPCX797FC does not leave
- * any unused flash space that can be used to store the .init_rom section.
- */
-#undef CONFIG_CHIP_INIT_ROM_REGION
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* Charger */
-#define CONFIG_CHARGER_RAA489000
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
-#define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#undef CONFIG_CMD_CHARGER_DUMP
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
-
-/* GPIO for C1 interrupts, for baseboard use */
-#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL
-
-/* Keyboard */
-
-#define CONFIG_KEYBOARD_KEYPAD
-#define CONFIG_PWM_KBLIGHT
-
-/* LED defines */
-#define CONFIG_LED_ONOFF_STATES
-
-/* PWM */
-#define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-
-/* Temp sensor */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_THERMISTOR_NCP15WB
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB */
-#define CONFIG_BC12_DETECT_PI3USB9201
-#define CONFIG_USBC_RETIMER_PS8802
-
-/* Common USB-A defines */
-#define USB_PORT_COUNT 2
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L
-#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L
-
-/******************************************************************************/
-
-/* USB PD */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_RAA489000
-
-/* USB defines specific to external TCPCs */
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* Variant references the TCPCs to determine Vbus sourcing */
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-
-/* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-/* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
-
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
-
-#define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
-
-/* Sensors */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-
-/* Lid operates in forced mode, base in FIFO */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Volume Button feature */
-#define CONFIG_ADC_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_TYPE_COUNT,
-};
-
-int board_is_sourcing_vbus(int port);
-void motion_interrupt(enum gpio_signal signal);
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/waddledoo2/build.mk b/board/waddledoo2/build.mk
deleted file mode 100644
index b012d8d502..0000000000
--- a/board/waddledoo2/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7fc
-BASEBOARD:=keeby
-
-board-y=board.o battery.o cbi_ssfc.o led.o usb_pd_policy.o
diff --git a/board/waddledoo2/cbi_ssfc.c b/board/waddledoo2/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/waddledoo2/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/waddledoo2/cbi_ssfc.h b/board/waddledoo2/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/waddledoo2/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo2/ec.tasklist b/board/waddledoo2/ec.tasklist
deleted file mode 100644
index d4fb416bce..0000000000
--- a/board/waddledoo2/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/waddledoo2/gpio.inc b/board/waddledoo2/gpio.inc
deleted file mode 100644
index f0e345a81c..0000000000
--- a/board/waddledoo2/gpio.inc
+++ /dev/null
@@ -1,145 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Power Interrupts */
-GPIO_INT(SLP_S0_L,		 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		 PIN(A, 5), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S4_L,		 PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		 PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	 PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	 PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	 PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	 PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	 PIN(B, 0), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP5000_U_OD,	 PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		 PIN(E, 4), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	 PIN(4, 2), GPIO_INT_BOTH, power_signal_interrupt)
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	 PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt)
-GPIO_INT(SUB_USB_C1_INT_ODL,	 PIN(F, 5), GPIO_INT_FALLING | GPIO_PULL_UP, sub_usb_c1_interrupt)
-
-/* Button interrupts */
-GPIO_INT(EC_PWR_BTN_ODL,	 PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		 PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(EC_WP_OD,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	 PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, motion_interrupt)
-GPIO_INT(LID_360_L,		 PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-/* I2C Ports */
-GPIO(EC_I2C_EEPROM_SCL,	      PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,	      PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,      PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,      PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,	      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SDA,	      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,	      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,	      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SCL,   PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,   PIN(9, 1), GPIO_INPUT)
-
-/* Extra Sub-board I/O pins */
-
-GPIO(EC_SUB_IO_2,  PIN(3, 4), GPIO_OUT_LOW)
-
-/* Misc Enables */
-GPIO(EN_VCCIO_EXT,   PIN(6, 1), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,		PIN(A, 7), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,	PIN(6, 3), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,	PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000_U,	PIN(A, 4), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,		PIN(8, 3), GPIO_OUT_LOW)
-GPIO(EN_KB_BL,		PIN(6, 0), GPIO_OUT_LOW)
-GPIO(EN_BL_OD,		PIN(D, 3), GPIO_ODR_LOW)
-GPIO(EC_CBI_WP,		PIN(E, 5), GPIO_OUT_LOW)
-
-/* LED */
-GPIO(LED_B_ODL,                  PIN(C, 2), GPIO_OUT_HIGH)        /* PWM_CH_LED2_BLUE */
-GPIO(LED_G_ODL,                  PIN(C, 3), GPIO_OUT_HIGH)        /* PWM_CH_LED1_GREEN */
-GPIO(LED_R_ODL,                  PIN(C, 4), GPIO_OUT_HIGH)        /* PWM_CH_LED2_ORANGE */
-
-/* Power Sequencing */
-GPIO(EC_AP_PSYS,	     PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,         PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,      PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_RTCRST,           PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,         PIN(7, 4), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,	     PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,     PIN(9, 4), GPIO_ODR_LOW)
-GPIO(EC_AP_VCCST_PWRGD_OD,   PIN(B, 1), GPIO_ODR_LOW)
-GPIO(EC_AP_SYS_PWROK,	     PIN(0, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_MKBP_INT_L,	     PIN(7, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,	     PIN(F, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_ENTERING_RW,	     PIN(E, 3), GPIO_OUT_LOW)
-GPIO(ALL_SYS_PWRGD,	     PIN(A, 0), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,	     PIN(C, 5), GPIO_ODR_HIGH)
-
-/* USB pins */
-GPIO(EC_AP_USB_C1_HDMI_HPD,  PIN(9, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,	     PIN(9, 3), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,	     PIN(7, 2), GPIO_OUT_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,    PIN(E, 1), GPIO_INPUT)
-GPIO(USB_A0_CHARGE_EN_L, PIN(3, 7), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(F, 3), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(EN_USB_A0_VBUS,	 PIN(4, 1), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-GPIO(EN_USB_A1_VBUS,	 PIN(F, 2), GPIO_OUT_LOW)		/* Enable A1 5V Charging */
-/*
- * Waddledoo2 doesn't have these physical pins coming to the EC but uses other
- * logic.
- */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-UNIMPLEMENTED(VOLDN_BTN_ODL)
-UNIMPLEMENTED(VOLUP_BTN_ODL)
-
-/* Alternate Functions */
-/* ADC */
-ALTERNATE(PIN_MASK(F, BIT(0)), 0, MODULE_ADC, 0) /* ADC9 */
-ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)   /* ADC0-2 */
-
-/* Keyboard */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI0, KSI1 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT | GPIO_PULL_UP) /* KSI2-7 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO0, KSO1 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO3-9 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		 /* KSO14 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)	/* KSO2 inverted */
-
-/* PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0) /* PWM3 */
-
-/* UART */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)  /* UART1 */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, 0x3C), 0, MODULE_I2C, 0)   /* I2C7,I2C0 */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)   /* I2C5 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)   /* I2C2, I2C1 SCL */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)   /* I2C1 SDA */
-
-/* NC pins, enable internal pull-up to avoid floating state. */
-GPIO(GPIO32_NC, PIN(3, 2), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO35_NC, PIN(3, 5), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO57_NC, PIN(5, 7), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO81_NC, PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO86_NC, PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD0_NC, PIN(D, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD1_NC, PIN(D, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOD6_NC, PIN(D, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIOE0_NC, PIN(E, 0), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPIO40_NC, PIN(4, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/board/waddledoo2/led.c b/board/waddledoo2/led.c
deleted file mode 100644
index 85bd75ce99..0000000000
--- a/board/waddledoo2/led.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for waddledoo2
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_R_ODL, LED_ON_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_R_ODL, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_B_ODL, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/waddledoo2/usb_pd_policy.c b/board/waddledoo2/usb_pd_policy.c
deleted file mode 100644
index fd9018a3f0..0000000000
--- a/board/waddledoo2/usb_pd_policy.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on. */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS */
-	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable charging. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
-	if (rv)
-		return rv;
-
-	/* Our policy is not to source VBUS when the AP is off. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Provide Vbus. */
-	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
diff --git a/board/waddledoo2/vif_override.xml b/board/waddledoo2/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/waddledoo2/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/wand b/board/wand
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/wand
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/wheelie/battery.c b/board/wheelie/battery.c
deleted file mode 100644
index c9770124cd..0000000000
--- a/board/wheelie/battery.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all wheelie battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC_AP15O5L] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP15O5L",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Simplo AP13J7K Battery Information */
-	[BATTERY_SMP_AP13J7K] = {
-		.fuel_gauge = {
-			.manuf_name = "SIMPLO",
-			.device_name = "AP13J7K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AC15A3J Battery Information */
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP18C8K Battery Information */
-	[BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13050,
-			.voltage_normal		= 11250,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC AP19A8K Battery Information */
-	[BATTERY_LGC_AP19A8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KTxxxxGxxx",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-
-	/* LGC KT0030G023 Battery Information */
-	[BATTERY_LGC_G023] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G023",
-			.device_name = "AP19A8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13200,
-			.voltage_normal         = 11550,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC15A3J;
diff --git a/board/wheelie/board.c b/board/wheelie/board.c
deleted file mode 100644
index 198dbda284..0000000000
--- a/board/wheelie/board.c
+++ /dev/null
@@ -1,487 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wheelie board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "driver/accel_lis2dh.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/sm5803.h"
-#include "driver/sync.h"
-#include "driver/retimer/tusb544.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/usb_mux/it5205.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "uart.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* C0 interrupt line shared by BC 1.2 and charger */
-static void usb_c0_interrupt(enum gpio_signal s)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(0);
-}
-
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void usb_c1_interrupt(enum gpio_signal s)
-{
-	schedule_deferred_pd_interrupt(1);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-	sm5803_interrupt(1);
-}
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
-{
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-/* Must come after other header files and interrupt handler declarations */
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
-
-/* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-
-/* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-};
-
-/* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
-	},
-};
-
-void board_init(void)
-{
-	int on;
-
-	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
-
-	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	/* Charger on the sub-board will be a push-pull GPIO */
-	sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-
-	/* Turn on 5V if the system is on, otherwise turn it off */
-	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND);
-	board_power_5v_enable(on);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
-	 */
-}
-
-__override void board_power_5v_enable(int enable)
-{
-	/*
-	 * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board
-	 * sets it through the charger GPIO.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, !!enable);
-	if (sm5803_set_gpio0_level(1, !!enable))
-		CPRINTUSB("Failed to %sable sub rails!", enable ? "en" : "dis");
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
-
-	uint16_t status = 0;
-	int regval;
-
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
-
-	return status;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
-	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int p0_otg, p1_otg;
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	/* TODO(b/147440290): charger functions should take chgnum */
-	p0_otg = chg_chips[0].drv->is_sourcing_otg_power(0, 0);
-	p1_otg = chg_chips[1].drv->is_sourcing_otg_power(1, 1);
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
-
-		if (!p0_otg)
-			chg_chips[0].drv->set_mode(0,
-						   CHARGE_FLAG_INHIBIT_CHARGE);
-		if (!p1_otg)
-			chg_chips[1].drv->set_mode(1,
-						   CHARGE_FLAG_INHIBIT_CHARGE);
-
-		return EC_SUCCESS;
-	}
-
-	CPRINTUSB("New chg p%d", port);
-
-	/*
-	 * Charger task will take care of enabling charging on the new charge
-	 * port.  Here, we ensure the other port is not charging by changing
-	 * CHG_EN
-	 */
-	if (port == 0) {
-		if (p0_otg) {
-			CPRINTUSB("Skip enable p%d", port);
-			return EC_ERROR_INVAL;
-		}
-		if (!p1_otg) {
-			chg_chips[1].drv->set_mode(1,
-						   CHARGE_FLAG_INHIBIT_CHARGE);
-		}
-	} else {
-		if (p1_otg) {
-			CPRINTUSB("Skip enable p%d", port);
-			return EC_ERROR_INVAL;
-		}
-		if (!p0_otg) {
-			chg_chips[0].drv->set_mode(0,
-						   CHARGE_FLAG_INHIBIT_CHARGE);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Vconn control for integrated ITE TCPC */
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/* Vconn control is only for port 0 */
-	if (port)
-		return;
-
-	if (cc_pin == USBPD_CC_PIN_1)
-		gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled);
-	else
-		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int current;
-
-	if (port < 0 || port > CONFIG_USB_PD_PORT_MAX_COUNT)
-		return;
-
-	current = (rp == TYPEC_RP_3A0) ? 3000 : 1500;
-
-	chg_chips[port].drv->set_otg_current_voltage(port, current, 5000);
-}
-
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	},
-
-	[PWM_CH_LED_RED] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_GREEN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	},
-
-	[PWM_CH_LED_BLUE] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 2400,
-	}
-
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct stprivate_data g_lis2dh_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LIS2DE,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &lis2dh_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_lis2dh_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LIS2DH_ADDR1_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 2, /* g */
-		/* We only use 2g because its resolution is only 8-bits */
-		.min_frequency = LIS2DH_ODR_MIN_VAL,
-		.max_frequency = LIS2DH_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = NULL,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = NULL,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-	[VSYNC] = {
-		.name = "Camera VSYNC",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_GPIO,
-		.type = MOTIONSENSE_TYPE_SYNC,
-		.location = MOTIONSENSE_LOC_CAMERA,
-		.drv = &sync_drv,
-		.default_range = 0,
-		.min_frequency = 0,
-		.max_frequency = 1,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Thermistors */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
diff --git a/board/wheelie/board.h b/board/wheelie/board.h
deleted file mode 100644
index dfbc4e7845..0000000000
--- a/board/wheelie/board.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wheelie board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_DEDEDE_EC_IT8320
-#include "baseboard.h"
-
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_FPU			/* For charger calculations */
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_5V_CHARGER_CTRL
-#define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 1
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_SYNC			/* Camera VSYNC */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_ACCEL_INTERRUPTS
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
-
-/* Thermistors */
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-/* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_RED,
-	PWM_CH_LED_GREEN,
-	PWM_CH_LED_BLUE,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
-
-/* ADC channels */
-enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_PANASONIC_AP15O5L,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_SMP_AP13J7K,
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_LGC_AP19A8K,
-	BATTERY_LGC_G023,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/wheelie/build.mk b/board/wheelie/build.mk
deleted file mode 100644
index 806168ea0d..0000000000
--- a/board/wheelie/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=it83xx
-CHIP_FAMILY:=it8320
-CHIP_VARIANT:=it8320dx
-BASEBOARD:=dedede
-
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/wheelie/cbi_ssfc.c b/board/wheelie/cbi_ssfc.c
deleted file mode 100644
index c4b859f133..0000000000
--- a/board/wheelie/cbi_ssfc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi_ssfc.h"
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
-BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
-
-static void cbi_ssfc_init(void)
-{
-	if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS)
-		/* Default to 0 when CBI isn't populated */
-		cached_ssfc.raw_value = 0;
-
-	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
-}
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
-
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
-{
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
-}
-
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
-{
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
-}
diff --git a/board/wheelie/cbi_ssfc.h b/board/wheelie/cbi_ssfc.h
deleted file mode 100644
index 935049b6ae..0000000000
--- a/board/wheelie/cbi_ssfc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
-
-#include "stdint.h"
-
-/****************************************************************************
- * Dedede CBI Second Source Factory Cache
- */
-
-/*
- * Base Sensor (Bits 0-2)
- */
-enum ec_ssfc_base_sensor {
-	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
-	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
-};
-
-/*
- * Lid Sensor (Bits 3-5)
- */
-enum ec_ssfc_lid_sensor {
-	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_KX022 = 2,
-	SSFC_SENSOR_LIS2DWL = 3
-};
-
-union dedede_cbi_ssfc {
-	struct {
-		uint32_t base_sensor : 3;
-		uint32_t lid_sensor : 3;
-		uint32_t reserved_2 : 26;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Get the Base sensor type from SSFC_CONFIG.
- *
- * @return the Base sensor board type.
- */
-enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
-
-/**
- * Get the Lid sensor type from SSFC_CONFIG.
- *
- * @return the Lid sensor board type.
- */
-enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
-
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/wheelie/ec.tasklist b/board/wheelie/ec.tasklist
deleted file mode 100644
index 75181a4531..0000000000
--- a/board/wheelie/ec.tasklist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/wheelie/gpio.inc b/board/wheelie/gpio.inc
deleted file mode 100644
index 8979ca6ab9..0000000000
--- a/board/wheelie/gpio.inc
+++ /dev/null
@@ -1,142 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Power State interrupts */
-GPIO_INT(SLP_S4_L,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(SLP_S0_L,		PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,		PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID0,	PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(RSMRST_PWRGD_L,	PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(CPU_C10_GATE_L,	PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_DRAM_OD,		PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(PG_PP1050_ST_OD,	PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(VCCIN_AUX_VID1,	PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_VCCIO_EXT_OD,	PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt)
-GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt)
-
-GPIO_INT(H1_EC_PWR_BTN_ODL,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Used to wake up the EC from Deep Doze mode when writing to console */
-GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_DBG_TX_EC_RX */
-#endif
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(B, 5), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
-GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
-
-/* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(I, 7), GPIO_INT_BOTH, button_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO_INT(CAM_EC_VSYNC,		PIN(C, 7), GPIO_INT_RISING, sync_interrupt)
-GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-
-/* Power sequence GPIOs */
-GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
-GPIO(EC_AP_PWR_BTN_ODL,		PIN(B, 6), GPIO_ODR_HIGH)
-GPIO(EC_AP_DPWROK,		PIN(L, 7), GPIO_OUT_LOW)
-GPIO(EC_AP_RSMRST_L,		PIN(H, 0), GPIO_OUT_LOW)
-GPIO(EC_AP_WAKE_ODL,		PIN(D, 5), GPIO_ODR_HIGH)
-GPIO(SYS_RST_ODL,		PIN(D, 1), GPIO_ODR_HIGH)
-GPIO(EC_AP_SYS_PWROK,		PIN(F, 2), GPIO_OUT_LOW)
-GPIO(PG_PP5000_U_OD,		PIN(E, 3), GPIO_INPUT)
-GPIO(EN_PP3300_PEN,		PIN(E, 6), GPIO_OUT_LOW)
-GPIO(EN_PP3300_A,		PIN(C, 5), GPIO_OUT_LOW)
-GPIO(EC_AP_PCH_PWROK_OD,	PIN(D, 6), GPIO_ODR_LOW)
-GPIO(EN_PP5000_U,		PIN(K, 5), GPIO_OUT_LOW)
-/* TODO(b:149775160) - Modify if needed if we ever use this signal. */
-GPIO(EN_VCCST,			PIN(D, 4), GPIO_INPUT)
-GPIO(EN_VCCIO_EXT,		PIN(B, 2), GPIO_OUT_LOW)
-GPIO(EC_PROCHOT_ODL,		PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_AP_VCCST_PWRGD_OD,	PIN(E, 5), GPIO_ODR_LOW)
-GPIO(ALL_SYS_PWRGD,		PIN(B, 7), GPIO_OUT_LOW)
-GPIO(EN_SLP_Z,			PIN(K, 3), GPIO_OUT_LOW)
-
-/* Required for icelake chipset code, but implemented through other means for dedede */
-UNIMPLEMENTED(AC_PRESENT)
-UNIMPLEMENTED(PG_EC_DSW_PWROK)
-UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD)
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C_EEPROM_SCL,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,		PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SCL,	PIN(C, 1), GPIO_INPUT)
-GPIO(EC_I2C_BATTERY_SDA,	PIN(C, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SUB_USB_C1_SCL,	PIN(E, 0), GPIO_INPUT)
-GPIO(EC_I2C_SUB_USB_C1_SDA,	PIN(E, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SCL,		PIN(A, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_SDA,		PIN(A, 5), GPIO_INPUT)
-
-/* USB pins */
-GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
-GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
-GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
-GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
-
-/* MKBP event synchronization */
-GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
-
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_1, PIN(L, 3), GPIO_INPUT)
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_2, PIN(L, 2), GPIO_INPUT)
-
-/* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_OUT_LOW)
-GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
-GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(PEN_DET_ODL,		PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
-GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-
-/* NC pins, enable internal pull-down to avoid floating state. */
-GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOL6_NC, PIN(L, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* Alternate functions GPIO definitions */
-/* UART */
-ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0)		/* UART for debug */
-
-/* I2C */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 */
-ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V)	/* I2C2 - 1.8V */
-ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
-
-/* ADC */
-ALTERNATE(PIN_MASK(L, BIT(0)), 0, MODULE_ADC, 0)			/* ADC13: EC_SUB_ANALOG */
-ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* DAC */
-ALTERNATE(PIN_MASK(J, BIT(2)), 0, MODULE_DAC, 0)			/* DAC2: EC_AP_PSYS */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0) | BIT(1) | BIT(2) | BIT(3)), 0, MODULE_PWM, 0) /* KB_BL_PWM, LED_[R,G,B]_ODL */
diff --git a/board/wheelie/led.c b/board/wheelie/led.c
deleted file mode 100644
index 9524a68a84..0000000000
--- a/board/wheelie/led.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wheelie specific PWM LED settings. */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-/*
- * Board has one physical LED with red, green, and blue
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
-};
-
-/* One logical LED with red, green, and blue channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED_RED,
-		.ch1 = PWM_CH_LED_GREEN,
-		.ch2 = PWM_CH_LED_BLUE,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_RED] = 100;
-	brightness_range[EC_LED_COLOR_GREEN] = 100;
-	brightness_range[EC_LED_COLOR_BLUE] = 100;
-	brightness_range[EC_LED_COLOR_YELLOW] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
-	if (led_id == EC_LED_ID_POWER_LED)
-		pwm_id = PWM_LED0;
-	else
-		return EC_ERROR_UNKNOWN;
-
-	if (brightness[EC_LED_COLOR_RED])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
-	else if (brightness[EC_LED_COLOR_GREEN])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
-	else if (brightness[EC_LED_COLOR_BLUE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_YELLOW])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
-	else if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
-	return EC_SUCCESS;
-}
diff --git a/board/wheelie/usb_pd_policy.c b/board/wheelie/usb_pd_policy.c
deleted file mode 100644
index 02ae21a420..0000000000
--- a/board/wheelie/usb_pd_policy.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/sm5803.h"
-#include "driver/tcpm/tcpci.h"
-#include "usb_pd.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Allow VCONN swaps if the AP is on */
-	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return;
-
-	/* TODO(b/147440290): charger functions should take chgnum */
-	prev_en = chg_chips[port].drv->is_sourcing_otg_power(port, port);
-
-	/* Disable Vbus */
-	chg_chips[port].drv->enable_otg_power(port, 0);
-
-	/* Discharge Vbus if previously enabled */
-	if (prev_en)
-		sm5803_set_vbus_disch(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	enum ec_error_list rv;
-
-	/* Disable charging */
-	rv = chg_chips[port].drv->set_mode(port, CHARGE_FLAG_INHIBIT_CHARGE);
-	if (rv)
-		return rv;
-
-	/* Disable Vbus discharge */
-	sm5803_set_vbus_disch(port, 0);
-
-	/* Provide Vbus */
-	chg_chips[port].drv->enable_otg_power(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	int chg_det = 0;
-
-	sm5803_get_chg_det(port, &chg_det);
-
-	return chg_det;
-}
diff --git a/board/wheelie/vif_override.xml b/board/wheelie/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/wheelie/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/whiskers b/board/whiskers
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/whiskers
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/willow/battery.c b/board/willow/battery.c
deleted file mode 100644
index cc97838f48..0000000000
--- a/board/willow/battery.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "gpio.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_PANASONIC_AC15A3J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AC15A3J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11580,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-	[BATTERY_PANASONIC_AC16L5J] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-        [BATTERY_LGC_AC16L8J] = {
-                .fuel_gauge = {
-                        .manuf_name = "LGC KT0020G010",
-                        .device_name = "AP16L8J",
-                        .ship_mode = {
-                                .reg_addr = 0x3A,
-                                .reg_data = { 0xC574, 0xC574 },
-                        },
-                        .fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-                        }
-                },
-                .batt_info = {
-                        .voltage_max            = 8700,
-                        .voltage_normal         = 7500,
-                        .voltage_min            = 6000,
-                        .precharge_current      = 256,
-                        .start_charging_min_c   = 0,
-                        .start_charging_max_c   = 50,
-                        .charging_min_c         = 0,
-                        .charging_max_c         = 60,
-                        .discharging_min_c      = -20,
-                        .discharging_max_c      = 75,
-                },
-        },
-	[BATTERY_PANASONIC_AC16L5J_KT00205009] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00205009",
-			.device_name = "AP16L5J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP18C8K Battery Information */
-	 [BATTERY_LGC_AP18C8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G020",
-			.device_name = "AP18C8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-	/* Murata AP18C4K Battery Information */
-	[BATTERY_MURATA_AP18C4K] = {
-		.fuel_gauge = {
-			.manuf_name = "Murata KT00304012",
-			.device_name = "AP18C4K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x2000,
-				.disconnect_val = 0x2000,
-			},
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11400,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	[BATTERY_PANASONIC_AP19B5K_KT00305011] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC KT00305011",
-			.device_name = "AP19B5K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550,
-			.voltage_min		= 9000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 75,
-		},
-	},
-	/* LGC AP19B8K Battery Information */
-	 [BATTERY_LGC_AP19B8K] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G022",
-			.device_name = "AP19B8K",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max            = 13050,
-			.voltage_normal         = 11250,
-			.voltage_min            = 9000,
-			.precharge_current      = 256,
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC15A3J;
-
-enum battery_present battery_hw_present(void)
-{
-	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-}
diff --git a/board/willow/board.c b/board/willow/board.c
deleted file mode 100644
index ba467fddc2..0000000000
--- a/board/willow/board.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "backlight.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/battery/max17055.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl923x.h"
-#include "driver/tcpm/fusb302.h"
-#include "driver/usb_mux/it5205.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "it8801.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	schedule_deferred_pd_interrupt(0 /* port */);
-}
-
-#include "gpio_list.h"
-
-/******************************************************************************/
-/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
-const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/******************************************************************************/
-/* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{"typec", 0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"other", 1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"battery", 2, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA, .drv = &bitbang_drv},
-};
-const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
-
-#define BC12_I2C_ADDR PI3USB9201_I2C_ADDR_3
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * TODO(b/133200075): Tune this once we have the final performance
-	 * out of the driver and the i2c bus.
-	 */
-	.output_settle_us = 35,
-	.debounce_down_us = 5 * MSEC,
-	.debounce_up_us = 40 * MSEC,
-	.scan_period_us = 10 * MSEC,
-	.min_post_scan_delay_us = 10 * MSEC,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	[0] = {
-		.i2c_host_port = IT8801_KEYBOARD_PWM_I2C_PORT,
-		.i2c_addr_flags = IT8801_I2C_ADDR1,
-		.drv = &it8801_ioexpander_drv,
-	},
-};
-
-/******************************************************************************/
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 2, GPIO_EC_SENSOR_SPI_NSS },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/******************************************************************************/
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = FUSB302_I2C_ADDR_FLAGS,
-		},
-		.drv = &fusb302_tcpm_drv,
-	},
-};
-
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state)
-{
-	/*
-	 * svdm_dp_attention() did most of the work, we only need to notify
-	 * host here.
-	 */
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-}
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
-	},
-};
-
-/* Charger config.  Start i2c address at 1, update during runtime */
-struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = 1,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
-
-/* Board version depends on ADCs, so init i2c port after ADC */
-static void charger_config_complete(void)
-{
-	chg_chips[0].i2c_port = board_get_charger_i2c();
-}
-DECLARE_HOOK(HOOK_INIT, charger_config_complete, HOOK_PRIO_INIT_ADC + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		status |= PD_STATUS_TCPC_ALERT_0;
-
-	return status;
-}
-
-static int force_discharge;
-
-int board_set_active_charge_port(int charge_port)
-{
-	CPRINTS("New chg p%d", charge_port);
-
-	/* ignore all request when discharge mode is on */
-	if (force_discharge && charge_port != CHARGE_PORT_NONE)
-		return EC_SUCCESS;
-
-	switch (charge_port) {
-	case CHARGE_PORT_USB_C:
-		/* Don't charge from a source port */
-		if (board_vbus_source_enabled(charge_port))
-			return -1;
-		break;
-	case CHARGE_PORT_NONE:
-		/*
-		 * To ensure the fuel gauge (max17055) is always powered
-		 * even when battery is disconnected, keep VBAT rail on but
-		 * set the charging current to minimum.
-		 */
-		charger_set_current(CHARGER_SOLO, 0);
-		break;
-	default:
-		panic("Invalid charge port\n");
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
-int board_discharge_on_ac(int enable)
-{
-	int ret, port;
-
-	if (enable) {
-		port = CHARGE_PORT_NONE;
-	} else {
-		/* restore the charge port state */
-		port = charge_manager_get_override();
-		if (port == OVERRIDE_OFF)
-			port = charge_manager_get_active_charge_port();
-	}
-
-	ret = charger_discharge_on_ac(enable);
-	if (ret)
-		return ret;
-
-	force_discharge = enable;
-	return board_set_active_charge_port(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	/* TODO(b:138352732): read IT8801 GPIO EN_USBC_CHARGE_L */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-static void board_spi_enable(void)
-{
-	/*
-	 * Pin mux spi peripheral away from emmc, since RO might have
-	 * left them there.
-	 */
-	gpio_config_module(MODULE_SPI_FLASH, 0);
-
-	/* Enable clocks to SPI2 module. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
-
-	/* Reset SPI2 to clear state left over from the emmc slave. */
-	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
-	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
-
-	/* Reinitialize spi peripheral. */
-	spi_enable(&spi_devices[0], 1);
-
-	/* Pin mux spi peripheral toward the sensor. */
-	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
-	     MOTION_SENSE_HOOK_PRIO - 1);
-
-static void board_spi_disable(void)
-{
-	/* Set pins to a state calming the sensor down. */
-	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
-	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
-	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-
-	/* Disable spi peripheral and clocks. */
-	spi_enable(&spi_devices[0], 0);
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
-	     MOTION_SENSE_HOOK_PRIO + 1);
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-static void board_init(void)
-{
-	/* If the reset cause is external, pulse PMIC force reset. */
-	if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-		msleep(100);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-	}
-
-	/* Enable TCPC alert interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-	/* Enable interrupts from BMI160 sensor. */
-	gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-
-	/* For some reason we have to do this again in case of sysjump */
-	board_spi_enable();
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-	/* Enable interrupt from PMIC. */
-	gpio_enable_interrupt(GPIO_PMIC_EC_RESETB);
-
-	/* Enable BC12 interrupt */
-	gpio_enable_interrupt(GPIO_BC12_EC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-#ifndef VARIANT_KUKUI_NO_SENSORS
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSORS,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = NULL, /* Identity matrix. */
-	 .default_range = 2, /* g, enough to calculate lid angle. */
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		 /* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[BASE_ACCEL] = {
-	 .name = "Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-		 /* Sensor on for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		 },
-	 },
-	},
-	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#endif /* !VARIANT_KUKUI_NO_SENSORS */
-
-/* Called on AP S5 -> S3 transition */
-static void board_chipset_startup(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void board_chipset_shutdown(void)
-{
-	gpio_set_level(GPIO_EN_USBA_5V, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-int board_get_charger_i2c(void)
-{
-	/* TODO(b:138415463): confirm the bus allocation for future builds */
-	return board_get_version() == 1 ? 2 : 1;
-}
-
-int board_get_battery_i2c(void)
-{
-	return board_get_version() >= 1 ? 2 : 1;
-}
diff --git a/board/willow/board.h b/board/willow/board.h
deleted file mode 100644
index a6907b9a9e..0000000000
--- a/board/willow/board.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Configuration for Willow */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_KUKUI_JACUZZI
-#define VARIANT_KUKUI_BATTERY_SMART
-#define VARIANT_KUKUI_CHARGER_ISL9238
-#define VARIANT_KUKUI_EC_STM32F098
-
-#ifndef SECTION_IS_RW
-#define VARIANT_KUKUI_NO_SENSORS
-#endif /* SECTION_IS_RW */
-
-#include "baseboard.h"
-
-#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
-
-#undef CONFIG_SYSTEM_UNLOCKED
-
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-
-#define CONFIG_CHARGER_PSYS
-
-#define CONFIG_CHARGER_RUNTIME_CONFIG
-
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_EXTPOWER_GPIO
-#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#undef CONFIG_I2C_NACK_RETRY_COUNT
-#define CONFIG_I2C_NACK_RETRY_COUNT 10
-#define CONFIG_SMBUS_PEC
-
-#define CONFIG_USB_PD_TCPM_FUSB302
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-
-#define CONFIG_USB_MUX_IT5205
-
-/* Motion Sensors */
-#ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ALS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#endif /* VARIANT_KUKUI_NO_SENSORS */
-
-/* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define IT8801_KEYBOARD_PWM_I2C_PORT 1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
-
-/* IT8801 I2C address */
-#define IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS    IT8801_I2C_ADDR1
-
-/* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI master port (SPI2) */
-
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-
-#define CONFIG_LED_ONOFF_STATES
-
-#undef CONFIG_GMR_TABLET_MODE
-#undef GMR_TABLET_MODE_GPIO_L
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	/* Real ADC channels begin here */
-	ADC_BOARD_ID = 0,
-	ADC_EC_SKU_ID,
-	ADC_CH_COUNT
-};
-
-/* power signal definitions */
-enum power_signal {
-	AP_IN_S3_L,
-	PMIC_PWR_GOOD,
-
-	/* Number of signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT,
-};
-
-enum charge_port {
-	CHARGE_PORT_USB_C,
-};
-
-enum battery_type {
-	BATTERY_PANASONIC_AC15A3J,
-	BATTERY_PANASONIC_AC16L5J,
-	BATTERY_LGC_AC16L8J,
-	BATTERY_PANASONIC_AC16L5J_KT00205009,
-	BATTERY_LGC_AP18C8K,
-	BATTERY_MURATA_AP18C4K,
-	BATTERY_PANASONIC_AP19B5K_KT00305011,
-	BATTERY_LGC_AP19B8K,
-	BATTERY_TYPE_COUNT,
-};
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-#ifdef SECTION_IS_RO
-/* Interrupt handler for emmc task */
-void emmc_cmd_interrupt(enum gpio_signal signal);
-#endif
-
-void bc12_interrupt(enum gpio_signal signal);
-void board_reset_pd_mcu(void);
-int board_get_version(void);
-
-/* returns the i2c port number of charger/battery */
-int board_get_charger_i2c(void);
-int board_get_battery_i2c(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/willow/build.mk b/board/willow/build.mk
deleted file mode 100644
index a6e1c010d7..0000000000
--- a/board/willow/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-#
-# STmicro STM32F098VC
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f09x
-BASEBOARD:=kukui
-
-board-y=battery.o board.o led.o
diff --git a/board/willow/ec.tasklist b/board/willow/ec.tasklist
deleted file mode 100644
index c1330b86f8..0000000000
--- a/board/willow/ec.tasklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 1024) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, 1280) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, 1024) \
-	TASK_ALWAYS_RO(EMMC, emmc_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/willow/gpio.inc b/board/willow/gpio.inc
deleted file mode 100644
index 9c1bffe194..0000000000
--- a/board/willow/gpio.inc
+++ /dev/null
@@ -1,120 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first.
- */
-
-/* Interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP,
-         tcpc_alert_event)
-GPIO_INT(POWER_BUTTON_L,    PIN(A, 0),  GPIO_INT_BOTH | GPIO_PULL_UP,
-         power_button_interrupt) /* EC_PWR_BTN_ODL */
-GPIO_INT(AP_IN_SLEEP_L,     PIN(C, 12), GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(PMIC_EC_RESETB,    PIN(B, 7),  GPIO_INT_BOTH | GPIO_PULL_DOWN,
-         power_signal_interrupt)
-GPIO_INT(WARM_RESET_REQ,    PIN(A, 3),  GPIO_INT_RISING | GPIO_PULL_DOWN,
-         chipset_reset_request_interrupt)
-GPIO_INT_RW(ACCEL_INT_ODL,  PIN(A, 4), GPIO_INT_FALLING | GPIO_SEL_1P8V | GPIO_PULL_UP,
-         bmi160_interrupt)
-GPIO_INT_RO(EMMC_CMD,       PIN(B, 15), GPIO_INT_FALLING,
-         emmc_cmd_interrupt)
-GPIO_INT(SPI1_NSS,          PIN(A, 15), GPIO_INT_BOTH | GPIO_PULL_UP,
-         spi_event) /* SPI_AP_EC_CS_L */
-GPIO_INT(LID_OPEN,          PIN(C, 5),  GPIO_INT_BOTH,
-         lid_interrupt)
-GPIO_INT(AC_PRESENT,        PIN(A, 6),  GPIO_INT_BOTH,
-         extpower_interrupt) /* ACOK_OD */
-GPIO_INT(BC12_EC_INT_ODL,   PIN(C, 9),  GPIO_INT_FALLING,
-         bc12_interrupt)
-GPIO_INT(IT8801_SMB_INT,    PIN(A, 8),  GPIO_INT_FALLING | GPIO_PULL_UP,
-         io_expander_it8801_interrupt) /* KB_INT_ODL */
-GPIO_INT(AP_EC_WATCHDOG_L,  PIN(D, 2),  GPIO_INT_FALLING,
-         chipset_watchdog_interrupt)
-
-/* Unimplemented interrupts */
-GPIO(ALS_RGB_INT_ODL,      PIN(C, 10), GPIO_INPUT)
-GPIO(TABLET_MODE_L,        PIN(B, 11), GPIO_INPUT)
-
-/* Reset pins */
-GPIO(AP_SYS_RST_L,         PIN(C, 11), GPIO_OUT_LOW)
-GPIO(PMIC_WATCHDOG_L,      PIN(A, 2),  GPIO_OUT_LOW)
-GPIO(PMIC_EN_ODL,          PIN(F, 0),  GPIO_ODR_HIGH)
-
-/*
- * I2C pins should be configured as inputs until I2C module is
- * initialized. This will avoid driving the lines unintentionally.
- */
-GPIO(I2C1_SCL,             PIN(B, 8),  GPIO_INPUT)
-GPIO(I2C1_SDA,             PIN(B, 9),  GPIO_INPUT)
-GPIO(I2C2_SCL,             PIN(A, 11), GPIO_INPUT)
-GPIO(I2C2_SDA,             PIN(A, 12), GPIO_INPUT)
-GPIO(I2C3_SCL,             PIN(A, 5),  GPIO_ODR_HIGH)
-GPIO(I2C3_SDA,             PIN(C, 4),  GPIO_ODR_HIGH)
-
-/* Analog pins */
-GPIO(BOARD_ID,             PIN(C, 0),  GPIO_ANALOG)
-GPIO(EC_SKU_ID,            PIN(B, 0),  GPIO_ANALOG)
-
-/* Other input pins */
-GPIO(WP_L,                 PIN(C, 8),  GPIO_INPUT) /* EC_FLASH_WP_ODL */
-GPIO(BOOT0,                PIN(F, 11), GPIO_INPUT)
-GPIO(CCD_MODE_ODL,         PIN(A, 1),  GPIO_INPUT)
-
-/* Other output pins */
-GPIO(EC_BATT_PRES_ODL,     PIN(A, 7),  GPIO_INPUT)
-GPIO(EC_BL_EN_OD,          PIN(A, 13), GPIO_ODR_HIGH)
-GPIO(EN_USBA_5V,           PIN(C, 14), GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_MISO,   PIN(C, 2),  GPIO_INPUT)
-GPIO(EC_SENSOR_SPI_MOSI,   PIN(C, 3),  GPIO_OUT_LOW)
-GPIO(EC_SENSOR_SPI_NSS,    PIN(B, 12), GPIO_OUT_HIGH)
-GPIO(EC_SENSOR_SPI_CK,     PIN(B, 10), GPIO_OUT_LOW)
-GPIO(ENTERING_RW,          PIN(C, 6),  GPIO_ODR_HIGH) /* EC_ENTERING_RW_ODL */
-GPIO(EC_INT_L,             PIN(C, 7),  GPIO_ODR_HIGH) /* EC_AP_INT_ODL */
-GPIO(EC_BOARD_ID_EN_L,     PIN(C, 15), GPIO_ODR_HIGH) /* EC_BOARD_ID_EN_ODL */
-GPIO(USB_C0_HPD_OD,        PIN(F, 1),  GPIO_ODR_LOW)
-GPIO(BOOTBLOCK_EN_L,       PIN(C, 1),  GPIO_ODR_HIGH)
-GPIO(USB_C0_DISCHARGE,     PIN(B, 6),  GPIO_OUT_LOW)
-
-IOEX(LED_BLUE,             EXPIN(0, 1, 4), GPIO_OUT_HIGH)      /* LED BLUE */
-IOEX(LED_GREEN,            EXPIN(0, 1, 3), GPIO_OUT_HIGH)      /* LED GREEN */
-IOEX(LED_ORANGE,           EXPIN(0, 1, 2), GPIO_OUT_HIGH)      /* LED ORANGE */
-
-GPIO(EN_PP1800_S5_L,       PIN(A, 14), GPIO_OUT_LOW)
-
-/*
- * TODO(b:138352732): On IT88801 expander, To be readded once IT8801 driver and
- * gpio expander framework has landed.
- */
-UNIMPLEMENTED(EN_PP5000_USBC)
-UNIMPLEMENTED(PMIC_FORCE_RESET_ODL)
-UNIMPLEMENTED(EN_USBC_CHARGE_L)
-
-/* USART1: PA9/PA10 */
-ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,       0)
-/* I2C MASTER: PB8/9 */
-ALTERNATE(PIN_MASK(B, 0x0300), 1, MODULE_I2C,        GPIO_ODR_HIGH )
-/* I2C MASTER: PA11/12 */
-ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C,        GPIO_ODR_HIGH )
-
-
-/* SPI1 */
-/* SPI SLAVE: PB3/4/5 */
-ALTERNATE(PIN_MASK(B, 0x0038), 0, MODULE_SPI,        0)
-/* SPI SLAVE CS: PA15 */
-ALTERNATE(PIN_MASK(A, 0x8000), 0, MODULE_SPI,        0)
-
-/* SPI2 */
-/* Shared between slave for emmc and master for bmi160 */
-/* They're mutually exclusive with gpio_config_module. */
-/* EMMC SPI SLAVE: PB13/14/15 */
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH,  0)
-/* SENSORS SPI MASTER: PB10, PB12, PC2, PC3 */
-ALTERNATE(PIN_MASK(B, 0x0400), 5, MODULE_SPI_CONTROLLER, 0)
-ALTERNATE(PIN_MASK(C, 0x000C), 1, MODULE_SPI_CONTROLLER, 0)
diff --git a/board/willow/led.c b/board/willow/led.c
deleted file mode 100644
index c579cb6165..0000000000
--- a/board/willow/led.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Willow
- */
-#include "common.h"
-#include "ioexpander.h"
-#include "driver/ioexpander/it8801.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		ioex_set_level(IOEX_LED_ORANGE, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_BLUE:
-		ioex_set_level(IOEX_LED_BLUE, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_GREEN:
-		ioex_set_level(IOEX_LED_GREEN, LED_ON_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		ioex_set_level(IOEX_LED_GREEN, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_BLUE, LED_OFF_LVL);
-		ioex_set_level(IOEX_LED_ORANGE, LED_OFF_LVL);
-		break;
-	}
-}
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_BLUE] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-	}
-}
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_BLUE] != 0)
-			led_set_color_battery(EC_LED_COLOR_BLUE);
-		else if (brightness[EC_LED_COLOR_GREEN] != 0)
-			led_set_color_battery(EC_LED_COLOR_GREEN);
-		else
-			led_set_color_battery(LED_OFF);
-	}
-	return EC_SUCCESS;
-}
diff --git a/board/willow/vif_override.xml b/board/willow/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/willow/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/woomax/analyzestack.yaml b/board/woomax/analyzestack.yaml
deleted file mode 100644
index 7ff5f39644..0000000000
--- a/board/woomax/analyzestack.yaml
+++ /dev/null
@@ -1,2 +0,0 @@
-remove:
-- panic_assert_fail
diff --git a/board/woomax/battery.c b/board/woomax/battery.c
deleted file mode 100644
index bd46c51cc7..0000000000
--- a/board/woomax/battery.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all Zork battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* AP18F4M */
-	[BATTERY_C536] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GXAE3jB",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x000c,
-				.disconnect_val = 0x000c,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13200,
-			.voltage_normal       = 11880,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = 0,
-			.discharging_max_c    = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C536;
diff --git a/board/woomax/board.c b/board/woomax/board.c
deleted file mode 100644
index 7770804402..0000000000
--- a/board/woomax/board.c
+++ /dev/null
@@ -1,858 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#include "adc.h"
-#include "button.h"
-#include "cbi_ec_fw_config.h"
-#include "cbi_ssfc.h"
-#include "cros_board_info.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "driver/accel_kionix.h"
-#include "driver/accel_kx022.h"
-#include "driver/retimer/pi3dpx1207.h"
-#include "driver/retimer/pi3hdx1204.h"
-#include "driver/retimer/ps8802.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/temp_sensor/sb_tsi.h"
-#include "driver/usb_mux/amd_fp5.h"
-#include "extpower.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-
-#include "gpio_list.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Motion sensors */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm426xx_data;
-
-/* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0, FLOAT_TO_FP(-1), 0 },
-	{ 0, 0, FLOAT_TO_FP(1) },
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
-};
-
-static const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
-};
-
-/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
-struct motion_sensor_t icm426xx_base_accel = {
-	.name = "Base Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		},
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm426xx_base_gyro = {
-	.name = "Base Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM426XX,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &icm426xx_drv,
-	.mutex = &g_base_mutex,
-	.drv_data = &g_icm426xx_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &base_standard_ref_icm,
-	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_KX022,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &kionix_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_kx022_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, enough for laptop. */
-	 .min_frequency = KX022_ACCEL_MIN_FREQ,
-	 .max_frequency = KX022_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	 },
-	},
-
-	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100,
-		 },
-		 /* EC use accel for angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-
-	[BASE_GYRO] = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void setup_base_gyro_config(void)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX) {
-		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		ccprints("BASE GYRO is ICM426XX");
-	} else
-		ccprints("BASE GYRO is BMI160");
-}
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	if (get_cbi_ssfc_base_sensor() == SSFC_BASE_GYRO_ICM426XX)
-		icm426xx_interrupt(signal);
-	else
-		bmi160_interrupt(signal);
-}
-
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* MFT channels. These are logically separate from pwm_channels. */
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_USB_A0_5V,
-};
-
-const struct pi3hdx1204_tuning pi3hdx1204_tuning = {
-	.eq_ch0_ch1_offset = PI3HDX1204_EQ_DB710,
-	.eq_ch2_ch3_offset = PI3HDX1204_EQ_DB710,
-	.vod_offset = PI3HDX1204_VOD_130_ALL_CHANNELS,
-	.de_offset = PI3HDX1204_DE_DB_MINUS5,
-};
-
-/*****************************************************************************
- * Board suspend / resume
- */
-#define PS8811_ACCESS_RETRIES 2
-
-static void board_chipset_resume(void)
-{
-	int rv;
-	int retry;
-	int hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
-
-	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 1);
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 1);
-
-	/* USB-A0 can run with default settings */
-	for (retry = 0; retry < PS8811_ACCESS_RETRIES; ++retry) {
-		int val;
-
-		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
-		if (!rv)
-			break;
-	}
-	if (rv) {
-		ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
-		CPRINTSUSB("A0: PS8811 not detected");
-	}
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
-		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  hpd);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void board_chipset_suspend(void)
-{
-	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
-
-	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
-		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
-	}
-
-	ioex_set_level(IOEX_HDMI_DATA_EN_DB, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************
- * USB-C MUX/Retimer dynamic configuration
- */
-static int woomax_ps8818_mux_set(const struct usb_mux *me,
-				 mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_18DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_18DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	} else {
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
-	}
-
-	if (!(mux_state & USB_PD_MUX_POLARITY_INVERTED)) {
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_CRX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
-		rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1,
-					PS8818_REG1_APRX1_DE_LEVEL, 0x02);
-	}
-
-	/* set the RX input termination */
-	rv |= ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE1,
-				PS8818_REG1_RX_PHY,
-				PS8818_RX_INPUT_TERM_MASK,
-				PS8818_RX_INPUT_TERM_85_OHM);
-	/* set register 0x40 ICP1 for 1G PD loop */
-	rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1, 0x40, 0x84);
-
-	return rv;
-}
-
-static int woomax_ps8802_mux_set(const struct usb_mux *me,
-				 mux_state_t mux_state)
-{
-	int rv = EC_SUCCESS;
-
-	/* Make sure the PS8802 is awake */
-	rv = ps8802_i2c_wake(me);
-	if (rv)
-		return rv;
-
-	/* USB specific config */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Boost the USB gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-	}
-
-	/* DP specific config */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/*Boost the DP gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB);
-		if (rv)
-			return rv;
-
-		/* Enable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1);
-	} else {
-		/* Disable IN_HPD on the DB */
-		gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0);
-	}
-
-	/* Set extra swing level tuning at 800mV/P0 */
-	rv = ps8802_i2c_field_update8(me,
-				PS8802_REG_PAGE1,
-				PS8802_800MV_LEVEL_TUNING,
-				PS8802_EXTRA_SWING_LEVEL_P0_MASK,
-				PS8802_EXTRA_SWING_LEVEL_P0_UP_1);
-
-	return rv;
-}
-
-const struct usb_mux usbc1_woomax_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &woomax_ps8818_mux_set,
-};
-
-static void setup_mux(void)
-{
-	if (ec_config_has_usbc1_retimer_ps8802()) {
-		ccprints("C1 PS8802 detected");
-
-		/*
-		 * Main MUX is PS8802, secondary MUX is modified FP5
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
-
-		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-		usb_muxes[USBC_PORT_C1].board_set = &woomax_ps8802_mux_set;
-
-		/* Don't have the AMD FP5 flip */
-		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
-
-	} else if (ec_config_has_usbc1_retimer_ps8818()) {
-		ccprints("C1 PS8818 detected");
-
-		/*
-		 * Main MUX is FP5, secondary MUX is PS8818
-		 *
-		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
-		 * table entry.
-		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
-
-		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_woomax_ps8818;
-	}
-}
-
-enum pi3dpx1207_usb_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
-
-static uint8_t pi3dpx1207_picasso_eq[] = {
-	/*usb_dp*/
-	0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B,
-	0x07, 0x03, 0x40, 0xFC, 0x42, 0x71,
-	/*usb_dp_inv */
-	0x13, 0x11, 0x20, 0x72, 0x06, 0x03, 0x07,
-	0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71,
-	/*usb*/
-	0x13, 0x11, 0x20, 0x42, 0x00, 0x03, 0x07,
-	0x07, 0x03, 0x00, 0x42, 0x42, 0x71,
-	/*usb_inv*/
-	0x13, 0x11, 0x20, 0x52, 0x00, 0x03, 0x07,
-	0x07, 0x03, 0x02, 0x42, 0x42, 0x71,
-	/*dp*/
-	0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71,
-	/*dp_inv*/
-	0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71,
-};
-static uint8_t pi3dpx1207_dali_eq[] = {
-	/*usb_dp*/
-	0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B,
-	0x07, 0x07, 0x40, 0xFC, 0x42, 0x71,
-	/*usb_dp_inv*/
-	0x13, 0x11, 0x20, 0x72, 0x06, 0x07, 0x07,
-	0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71,
-	/*usb*/
-	0x13, 0x11, 0x20, 0x42, 0x00, 0x07, 0x07,
-	0x07, 0x07, 0x00, 0x42, 0x42, 0x71,
-	/*usb_inv*/
-	0x13, 0x11, 0x20, 0x52, 0x00, 0x07, 0x07,
-	0x07, 0x07, 0x02, 0x42, 0x42, 0x71,
-	/*dp*/
-	0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71,
-	/*dp_inv*/
-	0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71,
-};
-
-static int board_pi3dpx1207_mux_set(const struct usb_mux *me,
-		mux_state_t mux_state)
-{
-	int  rv = EC_SUCCESS;
-	enum pi3dpx1207_usb_conf usb_mode = 0;
-
-	/* USB */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
-		}
-		/* USB without DP */
-		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
-		}
-	}
-	/* DP without USB */
-	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
-	}
-	/* Nothing enabled */
-	else
-		return EC_SUCCESS;
-
-	/* Write the retimer config byte */
-	if (ec_config_has_usbc1_retimer_ps8802())
-		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-			&pi3dpx1207_dali_eq[usb_mode*13], 13, NULL, 0);
-	else
-		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-			&pi3dpx1207_picasso_eq[usb_mode*13], 13, NULL, 0);
-
-	return rv;
-}
-
-const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
-	[USBC_PORT_C0] = {
-		.enable_gpio = IOEX_USB_C0_DATA_EN,
-		.dp_enable_gpio = GPIO_USB_C0_IN_HPD,
-	},
-	[USBC_PORT_C1] = {
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
-
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
-	.board_set = &board_pi3dpx1207_mux_set,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
-	},
-	[USBC_PORT_C1] = {
-		/* Filled in dynamically at startup */
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-/*****************************************************************************
- * Use FW_CONFIG to set correct configuration.
- */
-
-int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
-static uint32_t board_ver;
-static void setup_fw_config(void)
-{
-	cbi_get_board_version(&board_ver);
-
-	if (board_ver >= 2)
-		board_usbc1_retimer_inhpd = GPIO_USB_C1_HPD_IN_DB;
-
-	/* Enable Gyro interrupts */
-	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
-
-	/* Enable DP1_HPD_EC_IN interrupt */
-	if (ec_config_has_hdmi_retimer_pi3hdx1204())
-		gpio_enable_interrupt(GPIO_DP1_HPD_EC_IN);
-
-	setup_base_gyro_config();
-	setup_mux();
-}
-/* Use HOOK_PRIO_INIT_I2C + 2 to be after ioex_init(). */
-DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
-
-/*****************************************************************************
- * Fan
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = -1,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1100,
-	.rpm_start = 1100,
-	.rpm_max = 5120,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-int board_get_temp(int idx, int *temp_k)
-{
-	int mv;
-	int temp_c;
-	enum adc_channel channel;
-
-	/* idx is the sensor index set in board temp_sensors[] */
-	switch (idx) {
-	case TEMP_SENSOR_CHARGER:
-		channel = ADC_TEMP_SENSOR_CHARGER;
-		break;
-	case TEMP_SENSOR_SOC:
-		/* thermistor is not powered in G3 */
-		if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			return EC_ERROR_NOT_POWERED;
-
-		channel = ADC_TEMP_SENSOR_SOC;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mv = adc_read_channel(channel);
-	if (mv < 0)
-		return EC_ERROR_INVAL;
-
-	temp_c = thermistor_linear_interpolate(mv, &thermistor_info);
-	*temp_k = C_TO_K(temp_c);
-	return EC_SUCCESS;
-}
-
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		.name = "CHARGER",
-		.input_ch = NPCX_ADC_CH2,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.input_ch = NPCX_ADC_CH3,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_CHARGER,
-	},
-	[TEMP_SENSOR_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = board_get_temp,
-		.idx = TEMP_SENSOR_SOC,
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_CPU,
-		.read = sb_tsi_get_val,
-		.idx = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-const static struct ec_thermal_config thermal_thermistor = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(95),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(100),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
-
-const static struct ec_thermal_config thermal_cpu = {
-	.temp_host = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(95),
-		[EC_TEMP_THRESH_HALT] = C_TO_K(100),
-	},
-	.temp_host_release = {
-		[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
-	},
-	.temp_fan_off = C_TO_K(25),
-	.temp_fan_max = C_TO_K(58),
-};
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-static void setup_fans(void)
-{
-	thermal_params[TEMP_SENSOR_CHARGER] = thermal_thermistor;
-	thermal_params[TEMP_SENSOR_SOC] = thermal_thermistor;
-	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
-}
-DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
-
-static const struct ec_response_keybd_config woomax_kb = {
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &woomax_kb;
-}
-
-static void keyboard_init(void)
-{
-	keyscan_config.actual_key_mask[1] = 0xfe;
-	keyscan_config.actual_key_mask[11] = 0xfe;
-	keyscan_config.actual_key_mask[12] = 0xff;
-	keyscan_config.actual_key_mask[13] = 0xff;
-	keyscan_config.actual_key_mask[14] = 0xff;
-}
-DECLARE_HOOK(HOOK_INIT, keyboard_init, HOOK_PRIO_INIT_I2C + 1);
-
-static void hdmi_hpd_handler(void)
-{
-	int hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
-
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
-}
-DECLARE_DEFERRED(hdmi_hpd_handler);
-
-void hdmi_hpd_interrupt(enum gpio_signal signal)
-{
-	/* Debounce 2 msec */
-	hook_call_deferred(&hdmi_hpd_handler_data, (2 * MSEC));
-}
-
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
-{
-	/* USB-C0 always uses USB_C0_HPD */
-	if (port == 0)
-		return GPIO_USB_C0_HPD;
-	/*
-	 * USB-C1 OPT3 DB use IOEX_USB_C1_HPD_IN_DB for board version 1
-	 * USB-C1 OPT3 DB use GPIO_USB_C1_HPD_IN_DB for board version 2
-	 */
-	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 2)
-			? GPIO_USB_C1_HPD_IN_DB
-			: IOEX_USB_C1_HPD_IN_DB;
-
-	/* USB-C1 OPT1 DB use DP2_HPD. */
-	return GPIO_DP2_HPD;
-}
diff --git a/board/woomax/board.h b/board/woomax/board.h
deleted file mode 100644
index d81c82f181..0000000000
--- a/board/woomax/board.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Trembyle board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define VARIANT_ZORK_TREMBYLE
-
-#include <stdbool.h>
-#include "baseboard.h"
-
-#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
-#define CONFIG_USBC_RETIMER_PI3DPX1207
-
-/* Motion sensing drivers */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_KX022
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-#define CONFIG_TABLET_MODE
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_KEYPAD
-
-/*
- * Woomax's battery takes several seconds to come back out of its disconnect
- * state (~4 seconds on the unit I have, so give it a little more for margin).
- */
-#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5
-
-/* Thermal */
-#define CONFIG_CUSTOM_FAN_CONTROL
-
-/* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE_L
-
-#ifndef __ASSEMBLER__
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
-
-enum battery_type {
-	BATTERY_C536,
-	BATTERY_TYPE_COUNT,
-};
-
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER = 0,
-	TEMP_SENSOR_SOC,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
-
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_COUNT
-};
-
-/*****************************************************************************
- * CBI EC FW Configuration
- */
-
-/**
- * WOOMAX_MB_USBAC
- *	USB-A0  Speed: 10 Gbps
- *		Retimer: PS8811
- *	USB-C0  Speed: 10 Gbps
- *		Retimer: PI3DPX1207
- *		TCPC: NCT3807
- *		PPC: AOZ1380
- *		IOEX: TCPC
- */
-enum ec_cfg_usb_mb_type {
-	WOOMAX_MB_USBAC = 0,
-};
-
-/**
- * WOOMAX_DB_T_OPT1_USBAC_HMDI
- *	USB-C1  Speed: 10 Gbps
- *		Retimer: PS8818
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: PI3HDX1204
- *		MST Hub: none
- *
- * WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB
- *	USB-C1  Speed: 10 Gbps
- *		Retimer: PS8802
- *		TCPC: NCT3807
- *		PPC: NX20P3483
- *		IOEX: TCPC
- *	HDMI    Exists: yes
- *		Retimer: none
- *		MST Hub: RTD2141B
- */
-enum ec_cfg_usb_db_type {
-	WOOMAX_DB_T_OPT1_USBAC_HMDI = 0,
-	WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB = 1,
-};
-
-#include "cbi_ec_fw_config.h"
-
-#define HAS_USBC1_RETIMER_PS8802 \
-			 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_usbc1_retimer_ps8802(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
-}
-
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_usbc1_retimer_ps8818(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
-}
-
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
-
-static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
-}
-
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
-
-static inline bool ec_config_has_mst_hub_rtd2141b(void)
-{
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
-}
-
-/*
- * USB-C0 always uses USB_C0_HPD (= DP3_HPD).
- * USB-C1 OPT1 DB uses DP2_HPD.
- * USB-C1 OPT3 DB uses DP1_HPD via RTD2141B MST hub to drive AP
- *    HPD, EC drives MST hub HPD input from USB-PD messages.
- */
-
-enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
-#define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio(port)
-
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
-extern const struct usb_mux usbc1_ps8818;
-extern struct usb_mux usbc1_amd_fp5_usb_mux;
-void hdmi_hpd_interrupt(enum gpio_signal signal);
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/woomax/build.mk b/board/woomax/build.mk
deleted file mode 100644
index a674573a4d..0000000000
--- a/board/woomax/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m7wc
-BASEBOARD:=zork
-
-board-y=board.o led.o thermal.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/woomax/ec.tasklist b/board/woomax/ec.tasklist
deleted file mode 100644
index d9c1606eb2..0000000000
--- a/board/woomax/ec.tasklist
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/woomax/gpio.inc b/board/woomax/gpio.inc
deleted file mode 100644
index ade15d3d4a..0000000000
--- a/board/woomax/gpio.inc
+++ /dev/null
@@ -1,140 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
-GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
-GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	motion_interrupt)
-GPIO_INT(TABLET_MODE_L,		PIN(4, 4), GPIO_INT_BOTH,			gmr_tablet_switch_isr)
-GPIO_INT(DP1_HPD_EC_IN,		PIN(7, 5), GPIO_INT_BOTH,			hdmi_hpd_interrupt)
-
-/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
-GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
-
-GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN)		/* 3 Axis Accel */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
-GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
-GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
-GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
-GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
-GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
-GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
-GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
-GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
-GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
-GPIO(EC_FCH_SCI_ODL,		PIN(7, 6), GPIO_ODR_HIGH)			/* SCI to SOC */
-GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
-GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
-GPIO(EC_DP1_HPD,		PIN(F, 4), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
-GPIO(EC_H1_PACKET_MODE,		PIN(8, 6), GPIO_OUT_LOW)			/* H1 Packet Mode */
-GPIO(EN_PWR_TOUCHPAD_PS2,	PIN(C, 2), GPIO_INPUT)				/* Touchpad Power */
-GPIO(USB_C1_HPD_IN_DB,		PIN(B, 1), GPIO_OUT_LOW)			/* C1 HPD for board version 2 */
-
-UNIMPLEMENTED(NO_HPD)
-UNIMPLEMENTED(PCH_SMI_L)
-
-GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
-GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
-GPIO(LED_3_L,			PIN(C, 3), GPIO_OUT_HIGH)			/* Power LED */
-
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, 	sbu_fault_interrupt)
-IOEX_INT(USB_C1_SBU_FAULT_DB_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-
-IOEX(USB_A0_RETIMER_EN,		EXPIN(USBC_PORT_C0, 0, 0), GPIO_OUT_LOW)	/* A0 Retimer Enable */
-IOEX(USB_A0_RETIMER_RST,	EXPIN(USBC_PORT_C0, 0, 1), GPIO_OUT_LOW)	/* A0 Retimer Reset */
-IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
-IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
-IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
-IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable */
-IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
-IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
-
-IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD for board version 1*/
-IOEX(HDMI_POWER_EN_DB,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)	/* HDMI retimer power enable */
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
-IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
-IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_LOW)	/* HDMI Retimer Enable */
-IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
-
-/*
- * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
- * is not defined here as GPIO.
- */
-
-/* I2C pins - these will be reconfigured for alternate function below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(FCH_SIC_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(FCH_SID_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
-GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
-GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
-
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
-ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
-ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
-ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
-
-ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
-
-ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
-ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
-ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
-
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
-GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
-
-ALTERNATE(PIN_MASK(A, 0xA0), 1,  MODULE_WOV, 0) 				/* I2S_SYNC/I2S_SCLK  GPIOA5/A7 */
-ALTERNATE(PIN_MASK(B, 0x01), 1,  MODULE_WOV, 0) 				/* I2S_SDAT           GPIOB0    */
-ALTERNATE(PIN_MASK(9, 0x90), 1,  MODULE_WOV, 0) 				/* DMIC_CLK/DMIC_IN   GPIO94/97 */
diff --git a/board/woomax/led.c b/board/woomax/led.c
deleted file mode 100644
index e1091c92f3..0000000000
--- a/board/woomax/led.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "chipset.h"
-
-#define LED_ON_LVL 0
-#define LED_OFF_LVL 1
-
-__override const int led_charge_lvl_1 = 5;
-
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
-		break;
-	case EC_LED_COLOR_WHITE:
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	if (color == EC_LED_COLOR_WHITE)
-		gpio_set_level(GPIO_LED_3_L, LED_ON_LVL);
-	else
-		/* LED_OFF and unsupported colors */
-		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0)
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_battery(LED_OFF);
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0)
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		else
-			led_set_color_power(LED_OFF);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/woomax/thermal.c b/board/woomax/thermal.c
deleted file mode 100644
index 2517a361e6..0000000000
--- a/board/woomax/thermal.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-struct fan_step {
-	/*
-	 * Sensor 1~3 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t on[TEMP_SENSOR_COUNT];
-
-	/*
-	 * Sensor 1~3 trigger point, set -1 if we're not using this
-	 * sensor to determine fan speed.
-	 */
-	int8_t off[TEMP_SENSOR_COUNT];
-
-	/* Fan rpm */
-	uint16_t rpm;
-};
-
-static const struct fan_step fan_step_table[] = {
-	{
-		/* level 0 */
-		.on = {-1, -1, 36},
-		.off = {-1, -1, 99},
-		.rpm = 0,
-	},
-	{
-		/* level 1 */
-		.on = {-1, -1, 40},
-		.off = {-1, -1, 32},
-		.rpm = 2244,
-	},
-	{
-		/* level 2 */
-		.on = {-1, -1, 45},
-		.off = {-1, -1, 35},
-		.rpm = 2580,
-	},
-	{
-		/* level 3 */
-		.on = {-1, -1, 50},
-		.off = {-1, -1, 40},
-		.rpm = 2824,
-	},
-	{
-		/* level 4 */
-		.on = {-1, -1, 55},
-		.off = {-1, -1, 45},
-		.rpm = 3120,
-	},
-	{
-		/* level 5 */
-		.on = {-1, -1, 60},
-		.off = {-1, -1, 50},
-		.rpm = 3321,
-	},
-	{
-		/* level 6 */
-		.on = {-1, -1, 70},
-		.off = {-1, -1, 55},
-		.rpm = 3780,
-	},
-	{
-		/* level 7 */
-		.on = {-1, -1, 80},
-		.off = {-1, -1, 60},
-		.rpm = 4330,
-	},
-	{
-		/* level 8 */
-		.on = {-1, -1, 99},
-		.off = {-1, -1, 74},
-		.rpm = 4915,
-	},
-};
-
-#define NUM_FAN_LEVELS ARRAY_SIZE(fan_step_table)
-
-int fan_table_to_rpm(int fan, int *temp)
-{
-	static int current_level;
-	static int prev_tmp[TEMP_SENSOR_COUNT];
-	int i;
-
-	/*
-	 * Comopare the current and previous temperature, we have
-	 * the three path:
-	 * 1. decreasing path. (check the release point)
-	 * 2. increasing path. (check the trigger point)
-	 * 3. invariant path. (return the current RPM)
-	 */
-	if (temp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
-		if (temp[TEMP_SENSOR_CPU] <
-			fan_step_table[current_level].off[TEMP_SENSOR_CPU])
-			current_level = current_level - 1;
-	} else if (temp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
-		if (temp[TEMP_SENSOR_CPU] >
-			fan_step_table[current_level].on[TEMP_SENSOR_CPU])
-			current_level = current_level + 1;
-	}
-
-	if (current_level < 0)
-		current_level = 0;
-	else if (current_level > NUM_FAN_LEVELS)
-		current_level = NUM_FAN_LEVELS;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; i++)
-		prev_tmp[i] = temp[i];
-
-	return fan_step_table[current_level].rpm;
-}
-
-void board_override_fan_control(int fan, int *tmp)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
-	}
-}
-
diff --git a/board/woomax/vif_override.xml b/board/woomax/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/woomax/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/wormdingler/base_detect.c b/board/wormdingler/base_detect.c
deleted file mode 100644
index 73c28e4bc9..0000000000
--- a/board/wormdingler/base_detect.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wormdingler base detection code */
-
-#include "adc.h"
-#include "base_state.h"
-#include "board.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
-#define BASE_DETECT_EN_LATER_US (600 * MSEC)
-
-/* Base detection and debouncing */
-#define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
-#define BASE_DETECT_DIS_DEBOUNCE_US (20 * MSEC)
-
-/*
- * If the base status is unclear (i.e. not within expected ranges, read
- * the ADC value again every 500ms.
- */
-#define BASE_DETECT_RETRY_US (500 * MSEC)
-
-/*
- * Lid has 604K pull-up, base has 30.1K pull-down, so the
- * ADC value should be around 30.1/(604+30.1)*3300 = 156
- *
- * We add a significant margin on the maximum value, due to noise on the line,
- * especially when PWM is active. See b/64193554 for details.
- */
-#define BASE_DETECT_MIN_MV 120
-#define BASE_DETECT_MAX_MV 300
-
-/* Minimum ADC value to indicate base is disconnected for sure */
-#define BASE_DETECT_DISCONNECT_MIN_MV 1500
-
-/*
- * Base EC pulses detection pin for 500 us to signal out of band USB wake (that
- * can be used to wake system from deep S3).
- */
-#define BASE_DETECT_PULSE_MIN_US 400
-#define BASE_DETECT_PULSE_MAX_US 650
-
-static uint64_t base_detect_debounce_time;
-
-static void base_detect_deferred(void);
-DECLARE_DEFERRED(base_detect_deferred);
-
-enum base_status {
-	BASE_UNKNOWN = 0,
-	BASE_DISCONNECTED = 1,
-	BASE_CONNECTED = 2,
-};
-
-static enum base_status current_base_status;
-
-/*
- * This function is called whenever there is a change in the base detect
- * status. Actions taken include:
- * 1. Change in power to base
- * 2. Indicate mode change to host.
- * 3. Indicate tablet mode to host. Current assumption is that if base is
- * disconnected then the system is in tablet mode, else if the base is
- * connected, then the system is not in tablet mode.
- */
-static void base_detect_change(enum base_status status)
-{
-	int connected = (status == BASE_CONNECTED);
-
-	if (current_base_status == status)
-		return;
-
-	gpio_set_level(GPIO_EN_BASE, connected);
-	tablet_set_mode(!connected, TABLET_TRIGGER_BASE);
-	base_set_state(connected);
-	current_base_status = status;
-}
-
-/* Measure detection pin pulse duration (used to wake AP from deep S3). */
-static uint64_t pulse_start;
-static uint32_t pulse_width;
-
-static void print_base_detect_value(int v, int tmp_pulse_width)
-{
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
-}
-
-static void base_detect_deferred(void)
-{
-	uint64_t time_now = get_time().val;
-	int v;
-	uint32_t tmp_pulse_width = pulse_width;
-
-	if (base_detect_debounce_time > time_now) {
-		hook_call_deferred(&base_detect_deferred_data,
-				   base_detect_debounce_time - time_now);
-		return;
-	}
-
-	v = adc_read_channel(ADC_BASE_DET);
-	if (v == ADC_READ_ERROR)
-		return;
-
-	print_base_detect_value(v, tmp_pulse_width);
-
-	if (v >= BASE_DETECT_MIN_MV && v <= BASE_DETECT_MAX_MV) {
-		if (current_base_status != BASE_CONNECTED) {
-			base_detect_change(BASE_CONNECTED);
-		} else if (tmp_pulse_width >= BASE_DETECT_PULSE_MIN_US &&
-			   tmp_pulse_width <= BASE_DETECT_PULSE_MAX_US) {
-			CPRINTS("Sending event to AP");
-			host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-		}
-		return;
-	}
-
-	if (v >= BASE_DETECT_DISCONNECT_MIN_MV) {
-		base_detect_change(BASE_DISCONNECTED);
-		return;
-	}
-
-	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
-}
-
-static inline int detect_pin_connected(enum gpio_signal det_pin)
-{
-	return gpio_get_level(det_pin) == 0;
-}
-
-void base_detect_interrupt(enum gpio_signal signal)
-{
-	uint64_t time_now = get_time().val;
-	int debounce_us;
-
-	if (detect_pin_connected(signal))
-		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-	else
-		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-
-	if (base_detect_debounce_time <= time_now) {
-		/*
-		 * Detect and measure detection pin pulse, when base is
-		 * connected. Only a single pulse is measured over a debounce
-		 * period. If no pulse, or multiple pulses are detected,
-		 * pulse_width is set to 0.
-		 */
-		if (current_base_status == BASE_CONNECTED &&
-		    !detect_pin_connected(signal)) {
-			pulse_start = time_now;
-		} else {
-			pulse_start = 0;
-		}
-		pulse_width = 0;
-
-		hook_call_deferred(&base_detect_deferred_data, debounce_us);
-	} else {
-		if (current_base_status == BASE_CONNECTED &&
-		    detect_pin_connected(signal) && !pulse_width &&
-		    pulse_start) {
-			/* First pulse within period. */
-			pulse_width = time_now - pulse_start;
-		} else {
-			pulse_start = 0;
-			pulse_width = 0;
-		}
-	}
-
-	base_detect_debounce_time = time_now + debounce_us;
-}
-
-static void base_enable(void)
-{
-	/* Enable base detection interrupt. */
-	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
-	gpio_enable_interrupt(GPIO_BASE_DET_L);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
-
-static void base_disable(void)
-{
-	/*
-	 * Disable base detection interrupt and disable power to base.
-	 * Set the state UNKNOWN so the next startup will initialize a
-	 * correct state and notify AP.
-	 */
-	gpio_disable_interrupt(GPIO_BASE_DET_L);
-	base_detect_change(BASE_UNKNOWN);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, base_disable, HOOK_PRIO_DEFAULT);
-
-static void base_init(void)
-{
-	/*
-	 * If we jumped to this image and chipset is already in S0, enable
-	 * base.
-	 */
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-		base_enable();
-}
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
-
-void base_force_state(enum ec_set_base_state_cmd state)
-{
-	if (state == EC_SET_BASE_STATE_ATTACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_CONNECTED);
-		CPRINTS("BD forced connected");
-	} else if (state == EC_SET_BASE_STATE_DETACH) {
-		gpio_disable_interrupt(GPIO_BASE_DET_L);
-		base_detect_change(BASE_DISCONNECTED);
-		CPRINTS("BD forced disconnected");
-	} else {
-		base_enable();
-		CPRINTS("BD forced reset");
-	}
-}
diff --git a/board/wormdingler/battery.c b/board/wormdingler/battery.c
deleted file mode 100644
index c76bb48031..0000000000
--- a/board/wormdingler/battery.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all wormdingler battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-
-const struct board_batt_params board_battery_info[] = {
-	/* Sunwoda L21D2PG2 */
-	[BATTERY_L21D2PG2] = {
-		.fuel_gauge = {
-			.manuf_name = "Sunwoda",
-			.device_name = "L21D2PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8860, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 200,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 63,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 63,
-		},
-	},
-	/* BYD L21B2PG2 */
-	[BATTERY_L21B2PG2] = {
-		.fuel_gauge = {
-			.manuf_name = "BYD",
-			.device_name = "L21B2PG2",
-			.ship_mode = {
-				.reg_addr = 0x34,
-				.reg_data = { 0x0000, 0x1000 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x34,
-				.reg_mask = 0x0100,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max            = 8860, /* mV */
-			.voltage_normal         = 7700, /* mV */
-			.voltage_min            = 6000, /* mV */
-			.precharge_current      = 256,  /* mA */
-			.start_charging_min_c   = 0,
-			.start_charging_max_c   = 50,
-			.charging_min_c         = 0,
-			.charging_max_c         = 60,
-			.discharging_min_c      = -20,
-			.discharging_max_c      = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_L21D2PG2;
diff --git a/board/wormdingler/board.c b/board/wormdingler/board.c
deleted file mode 100644
index 796409cb80..0000000000
--- a/board/wormdingler/board.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wormdingler board-specific configuration */
-
-#include "adc_chip.h"
-#include "button.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "extpower.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "driver/ln9310.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "peripheral_charger.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "queue.h"
-#include "system.h"
-#include "shi_chip.h"
-#include "switch.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
-
-/* Forward declaration */
-static void tcpc_alert_event(enum gpio_signal signal);
-static void usb0_evt(enum gpio_signal signal);
-static void usb1_evt(enum gpio_signal signal);
-static void ppc_interrupt(enum gpio_signal signal);
-static void board_connect_c0_sbu(enum gpio_signal s);
-static void switchcap_interrupt(enum gpio_signal signal);
-
-#include "gpio_list.h"
-
-/* GPIO Interrupt Handlers */
-static void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-static void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-static void board_connect_c0_sbu_deferred(void)
-{
-	/*
-	 * If CCD_MODE_ODL asserts, it means there's a debug accessory connected
-	 * and we should enable the SBU FETs.
-	 */
-	ppc_set_sbu(0, 1);
-}
-DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
-
-static void board_connect_c0_sbu(enum gpio_signal s)
-{
-	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
-}
-
-static void switchcap_interrupt(enum gpio_signal signal)
-{
-	ln9310_interrupt(signal);
-}
-
-/* I2C port map */
-const struct i2c_port_t i2c_ports[] = {
-	{"power",   I2C_PORT_POWER,  100, GPIO_EC_I2C_POWER_SCL,
-					  GPIO_EC_I2C_POWER_SDA},
-	{"tcpc0",   I2C_PORT_TCPC0, 1000, GPIO_EC_I2C_USB_C0_PD_SCL,
-					  GPIO_EC_I2C_USB_C0_PD_SDA},
-	{"tcpc1",   I2C_PORT_TCPC1, 1000, GPIO_EC_I2C_USB_C1_PD_SCL,
-					  GPIO_EC_I2C_USB_C1_PD_SDA},
-	{"eeprom",  I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL,
-					  GPIO_EC_I2C_EEPROM_SDA},
-	{"sensor",  I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL,
-					  GPIO_EC_I2C_SENSOR_SDA},
-};
-
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * Adapter current output or battery charging/discharging current (uV)
-	 * 18x amplification on charger side.
-	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
-	/*
-	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
-	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
-	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
-	 * only divide by 2 (enough to avoid precision issues).
-	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
-	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct pwm_t pwm_channels[] = {
-	/* TODO(waihong): Assign a proper frequency. */
-	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 4800 },
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-/* LN9310 switchcap */
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = I2C_PORT_POWER,
-	.i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS,
-};
-
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Mutexes */
-static struct mutex g_lid_mutex;
-
-static struct bmi_drv_data_t g_bmi160_data;
-static struct icm_drv_data_t g_icm42607_data;
-
-enum lid_accelgyro_type {
-	LID_GYRO_NONE = 0,
-	LID_GYRO_BMI160 = 1,
-	LID_GYRO_ICM42607 = 2,
-};
-
-static enum lid_accelgyro_type lid_accelgyro_config;
-
-/* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
-
-struct motion_sensor_t icm42607_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
-	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
-	.config = {
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-	},
-};
-
-struct motion_sensor_t icm42607_lid_gyro = {
-	.name = "Gyro",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_ICM42607,
-	.type = MOTIONSENSE_TYPE_GYRO,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &icm42607_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_icm42607_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	.default_range = 1000, /* dps */
-	.rot_standard_ref = &lid_standard_ref_icm42607,
-	.min_frequency = ICM42607_GYRO_MIN_FREQ,
-	.max_frequency = ICM42607_GYRO_MAX_FREQ,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
-	 * Requirement: accelerometer sensor must init before gyro sensor
-	 * DO NOT change the order of the following table.
-	 */
-	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
-	},
-	[LID_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void board_detect_motionsensor(void)
-{
-	int val = -1;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-	if (lid_accelgyro_config != LID_GYRO_NONE)
-		return;
-
-	/* Check base accelgyro chip */
-	icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
-	if (val == ICM42607_CHIP_ICM42607P) {
-		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
-		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
-		lid_accelgyro_config = LID_GYRO_ICM42607;
-		CPRINTS("LID Accelgyro: ICM42607");
-	} else {
-		lid_accelgyro_config = LID_GYRO_BMI160;
-		CPRINTS("LID Accelgyro: BMI160");
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT + 1);
-
-void motion_interrupt(enum gpio_signal signal)
-{
-	switch (lid_accelgyro_config) {
-	case LID_GYRO_ICM42607:
-		icm42607_interrupt(signal);
-		break;
-	case LID_GYRO_BMI160:
-	default:
-		bmi160_interrupt(signal);
-		break;
-	}
-}
-
-enum battery_cell_type board_get_battery_cell_type(void)
-{
-	return BATTERY_CELL_TYPE_2S;
-}
-
-static void board_switchcap_init(void)
-{
-	CPRINTS("Use switchcap: LN9310");
-
-	/* Configure and enable interrupt for LN9310 */
-	gpio_set_flags(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_FALLING);
-	gpio_enable_interrupt(GPIO_SWITCHCAP_PG_INT_L);
-
-	/* Only configure the switchcap if not sysjump */
-	if (!system_jumped_late())
-		ln9310_init();
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
-
-	/*
-	 * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs
-	 * for SBU may be disconnected after DP alt mode is off. Should enable
-	 * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected.
-	 */
-	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
-
-	/* Set the backlight duty cycle to 0. AP will override it later. */
-	pwm_set_duty(PWM_CH_DISPLIGHT, 0);
-
-	board_switchcap_init();
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-__overridable uint16_t board_get_ps8xxx_product_id(int port)
-{
-	return PS8805_PRODUCT_ID;
-}
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_hibernate(void)
-{
-	int i;
-
-	/*
-	 * Sensors are unpowered in hibernate. Apply PD to the
-	 * interrupt lines such that they don't float.
-	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-
-	/*
-	 * Board rev 1+ has the hardware fix. Don't need the following
-	 * workaround.
-	 */
-	if (system_get_board_version() >= 1)
-		return;
-
-	/*
-	 * Enable the PPC power sink path before EC enters hibernate;
-	 * otherwise, ACOK won't go High and can't wake EC up. Check the
-	 * bug b/170324206 for details.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		ppc_vbus_sink_enable(i, 1);
-}
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/*
-	 * Turn off display backlight in S3. AP has its own control. The EC's
-	 * and the AP's will be AND'ed together in hardware.
-	 */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
-	pwm_enable(PWM_CH_DISPLIGHT, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Turn on display and keyboard backlight in S0. */
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
-	if (pwm_get_duty(PWM_CH_DISPLIGHT))
-		pwm_enable(PWM_CH_DISPLIGHT, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(GPIO_SWITCHCAP_ON_L, !enable);
-	ln9310_software_enable(enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return !gpio_get_level(GPIO_SWITCHCAP_ON_L);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return ln9310_power_good();
-}
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int battery_get_vendor_param(uint32_t param, uint32_t *value)
-{
-	int rv;
-	uint8_t data[16] = {};
-
-	/* only allow reading 0x70~0x7F, 16 byte data */
-	if (param < 0x70 || param >= 0x80)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = sb_read_string(0x70, data, sizeof(data));
-	if (rv)
-		return rv;
-
-	*value = data[param - 0x70];
-	return EC_SUCCESS;
-}
-
-int battery_set_vendor_param(uint32_t param, uint32_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/board/wormdingler/board.h b/board/wormdingler/board.h
deleted file mode 100644
index af0b5ee80d..0000000000
--- a/board/wormdingler/board.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wormdingler board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "baseboard.h"
-
-/* TODO(waihong): Remove the following bringup features */
-#define CONFIG_BRINGUP
-#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_CMD_GPIO_EXTENDED
-#define CONFIG_CMD_POWERINDEBUG
-#define CONFIG_I2C_DEBUG
-
-#define CONFIG_BUTTON_TRIGGERED_RECOVERY
-
-/* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
-
-/* Switchcap */
-#define CONFIG_LN9310
-
-/* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_VENDOR_PARAM
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-
-/* Enable PD3.0 */
-#define CONFIG_USB_PD_REV30
-
-/* BC 1.2 Charger */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* USB */
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_PS8755
-#define CONFIG_USB_PD_TCPM_PS8805
-#define CONFIG_USBC_PPC_SN5S330
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-
-/* Lid accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCEL_INTERRUPTS
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
-#define CONFIG_ACCELGYRO_ICM42607
-#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_FRONT_PROXIMITY_SWITCH
-
-#define CONFIG_DETACHABLE_BASE
-#define CONFIG_BASE_ATTACHED_SWITCH
-
-/* GPIO alias */
-#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD
-#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
-#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L
-#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT
-
-#define CONFIG_MKBP_INPUT_DEVICES
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_BASE_DET,
-	ADC_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL = 0,
-	LID_GYRO,
-	SENSOR_COUNT,
-};
-
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_L21D2PG2,
-	BATTERY_L21B2PG2,
-	BATTERY_TYPE_COUNT,
-};
-
-/* Reset all TCPCs. */
-void board_reset_pd_mcu(void);
-void board_set_tcpc_power_mode(int port, int mode);
-/* Base detection */
-void base_detect_interrupt(enum gpio_signal signal);
-
-void motion_interrupt(enum gpio_signal signal);
-
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/wormdingler/build.mk b/board/wormdingler/build.mk
deleted file mode 100644
index 74b6b95e4d..0000000000
--- a/board/wormdingler/build.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fc
-BASEBOARD:=trogdor
-
-board-y=battery.o board.o led.o base_detect.o
diff --git a/board/wormdingler/ec.tasklist b/board/wormdingler/ec.tasklist
deleted file mode 100644
index ea2aaa97f5..0000000000
--- a/board/wormdingler/ec.tasklist
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, ULTRA_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
diff --git a/board/wormdingler/gpio.inc b/board/wormdingler/gpio.inc
deleted file mode 100644
index 77a69a5faa..0000000000
--- a/board/wormdingler/gpio.inc
+++ /dev/null
@@ -1,196 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_PD_INT_ODL,    PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-0 TCPC */
-GPIO_INT(USB_C1_PD_INT_ODL,    PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)  /* Interrupt from port-1 TCPC */
-GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-0 PPC */
-GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(4, 0), GPIO_INT_FALLING, ppc_interrupt)  /* Interrupt from port-1 PPC */
-GPIO_INT(USB_C0_BC12_INT_L,    PIN(6, 1), GPIO_INT_FALLING | GPIO_PULL_UP, usb0_evt)  /* Interrupt from port-0 BC1.2 */
-GPIO_INT(USB_C1_BC12_INT_L,    PIN(8, 2), GPIO_INT_FALLING | GPIO_PULL_UP, usb1_evt)  /* Interrupt from port-1 BC1.2 */
-
-/* System interrupts */
-GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
-GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
-GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
-GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
-GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
-GPIO_INT(EC_FLASH_WP_ODL,   PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
-GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
-GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
-GPIO_INT(PS_HOLD,           PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)  /* Indicate when AP triggers reset/shutdown */
-GPIO_INT(AP_SUSPEND,        PIN(5, 7), GPIO_INT_BOTH, power_signal_interrupt)  /* Suspend signal from PMIC */
-GPIO_INT(DEPRECATED_AP_RST_REQ, PIN(C, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt) /* Deprecated AP initiated reset indicator */
-
-/*
- * When switch-cap is off, the POWER_GOOD signal is floating. Need a pull-down
- * to make it low. Overload the interrupt function chipset_warm_reset_interrupt
- * for not only signalling power_signal_interrupt but also handling the logic
- * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD.
- */
-GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_power_good_interrupt)  /* SRC_PP1800_S10A from PMIC */
-GPIO_INT(WARM_RESET_L,      PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt)  /* AP warm reset */
-GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event)  /* EC SPI Chip Select */
-
-GPIO_INT(BASE_DET_L,        PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt)  /* Detachable base attached? */
-
-/* Sensor interrupts */
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, motion_interrupt)  /* Accelerometer/gyro interrupt */
-
-/* Switchcap, for LN9310, it is the interrupt line of LN9310. */
-GPIO_INT(LN9310_INT,      PIN(E, 2), GPIO_INT_FALLING, switchcap_interrupt)
-
-/*
- * EC_RST_ODL acts as a wake source from hibernate mode. However, it does not
- * need to be an interrupt for normal EC operations. Simply set it an INPUT.
- */
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* EC reset */
-GPIO(EC_ENTERING_RW,        PIN(E, 1), GPIO_OUT_LOW)   /* Indicate when EC is entering RW code */
-GPIO(EC_BATT_PRES_ODL,      PIN(E, 5), GPIO_INPUT)     /* Battery Present */
-
-/* PMIC/AP 1.8V */
-GPIO(PM845_RESIN_L,         PIN(3, 2), GPIO_ODR_HIGH)  /* PMIC reset trigger */
-GPIO(PMIC_KPD_PWR_ODL,      PIN(D, 6), GPIO_ODR_HIGH)  /* PMIC power button */
-GPIO(EC_INT_L,              PIN(A, 2), GPIO_ODR_HIGH)  /* Interrupt line between AP and EC */
-GPIO(QSIP_ON,               PIN(5, 0), GPIO_OUT_LOW)   /* Not used, for non-switchcap testing */
-
-/* Power enables */
-GPIO(HIBERNATE_L,           PIN(5, 2), GPIO_ODR_HIGH)  /* EC hibernate */
-GPIO(SWITCHCAP_ON_L,        PIN(D, 5), GPIO_ODR_HIGH)  /* Enable switch cap */
-GPIO(EN_PP3300_A,           PIN(A, 6), GPIO_OUT_LOW)   /* Enable PP3300 */
-GPIO(EN_PP5000_A,           PIN(6, 7), GPIO_OUT_LOW)   /* Enable PP5000 */
-GPIO(EC_BL_DISABLE_L,       PIN(B, 6), GPIO_OUT_LOW)   /* Backlight disable signal from EC */
-
-/* Base detection */
-GPIO(EN_BASE,               PIN(0, 4), GPIO_OUT_LOW)   /* Enable power to detachable base */
-
-/* POGO */
-GPIO(POGO_VBUS_PRESENT,     PIN(6, 2), GPIO_INPUT)    /* POGO PIN */
-
-/* USB-C */
-GPIO(USB_C0_PD_RST_L,       PIN(F, 1), GPIO_ODR_HIGH)  /* Port-0 TCPC chip reset, actaully Open-Drain */
-GPIO(USB_C1_PD_RST_L,       PIN(E, 4), GPIO_ODR_HIGH)  /* Port-1 TCPC chip reset, actually Open-Drain */
-GPIO(DP_MUX_OE_L,           PIN(9, 6), GPIO_ODR_HIGH)  /* DP mux enable, actually Open-Drain */
-GPIO(DP_MUX_SEL,            PIN(4, 5), GPIO_OUT_LOW)   /* DP mux selection: L:C0, H:C1 */
-GPIO(DP_HOT_PLUG_DET,       PIN(9, 5), GPIO_OUT_LOW)   /* DP HPD to AP */
-
-/* LEDs */
-GPIO(EC_CHG_LED_R_C0,       PIN(C, 3), GPIO_OUT_LOW)
-GPIO(EC_CHG_LED_G_C0,       PIN(C, 4), GPIO_OUT_LOW)
-
-/*
- * SPI host interface - enable PDs by default. These will be made functional
- * by the SHI driver when the AP powers up, and restored back to GPIO when
- * the AP powers down.
- */
-GPIO(AP_EC_SPI_MOSI,        PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_MISO,        PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(AP_EC_SPI_CLK,         PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* PWM */
-GPIO(EDP_BKLTCTL,           PIN(B, 7), GPIO_INPUT)     /* PWM5 */
-GPIO(WCAM_EC_VSYNC,         PIN(C, 0), GPIO_INPUT)     /* PWM6 */
-GPIO(FCAM_EC_VSYNC,         PIN(6, 0), GPIO_INPUT)     /* PWM7 */
-
-/* ADC */
-GPIO(PPVAR_BOOSTIN_SENSE,   PIN(4, 4), GPIO_INPUT)     /* ADC1 */
-GPIO(CHARGER_IADP,          PIN(4, 3), GPIO_INPUT)     /* ADC2 */
-GPIO(CHARGER_PMON,          PIN(4, 2), GPIO_INPUT)     /* ADC3 */
-
-/* I2C */
-GPIO(EC_I2C_POWER_SCL,      PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,      PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SCL,  PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_PD_SDA,  PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SCL,  PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_PD_SDA,  PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SCL,     PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_EEPROM_SDA,     PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,     PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,     PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Board/SKU IDs */
-GPIO(BRD_ID0,               PIN(C, 7), GPIO_INPUT)
-GPIO(BRD_ID1,               PIN(9, 3), GPIO_INPUT)
-GPIO(BRD_ID2,               PIN(6, 3), GPIO_INPUT)
-GPIO(SKU_ID0,               PIN(F, 0), GPIO_INPUT)
-GPIO(SKU_ID1,               PIN(4, 1), GPIO_INPUT)
-GPIO(SKU_ID2,               PIN(D, 4), GPIO_INPUT)
-
-/* Special straps */
-GPIO(ARM_X86,               PIN(6, 6), GPIO_OUT_LOW)  /* NC, low for power saving */
-
-/* Unused GPIOs, NC. Apply PU for power saving */
-UNUSED(PIN(5, 1))
-UNUSED(PIN(F, 3))
-UNUSED(PIN(3, 1))
-UNUSED(PIN(3, 0))
-UNUSED(PIN(2, 7))
-UNUSED(PIN(2, 6))
-UNUSED(PIN(2, 5))
-UNUSED(PIN(2, 4))
-UNUSED(PIN(2, 3))
-UNUSED(PIN(2, 2))
-UNUSED(PIN(2, 1))
-UNUSED(PIN(2, 0))
-UNUSED(PIN(1, 7))
-UNUSED(PIN(1, 6))
-UNUSED(PIN(1, 5))
-UNUSED(PIN(1, 4))
-UNUSED(PIN(1, 3))
-UNUSED(PIN(1, 2))
-UNUSED(PIN(1, 1))
-UNUSED(PIN(1, 0))
-UNUSED(PIN(0, 7))
-UNUSED(PIN(0, 6))
-UNUSED(PIN(0, 5))
-UNUSED(PIN(9, 4))
-UNUSED(PIN(9, 7))
-UNUSED(PIN(A, 7))
-UNUSED(PIN(B, 0))
-UNUSED(PIN(A, 5))
-UNUSED(PIN(3, 5))
-UNUSED(PIN(7, 2))
-UNUSED(PIN(8, 1))
-UNUSED(PIN(7, 6))
-UNUSED(PIN(3, 4))
-UNUSED(PIN(C, 5))
-UNUSED(PIN(C, 6))
-UNUSED(PIN(A, 3))
-UNUSED(PIN(8, 3))
-UNUSED(PIN(B, 1))
-UNUSED(PIN(5, 6))
-UNUSED(PIN(8, 0))
-UNUSED(PIN(D, 0))
-UNUSED(PIN(D, 1))
-UNUSED(PIN(D, 3))
-UNUSED(PIN(7, 5))
-UNUSED(PIN(8, 6))
-UNUSED(PIN(7, 3))
-UNUSED(PIN(7, 4))
-UNUSED(PIN(D, 7))
-UNUSED(PIN(8, 5))
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
-ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)             /* I2C0 (GPIOB4/B5) */
-ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)             /* I2C1 SDA (GPIO90), I2C2 (GPIO91/92) */
-ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)             /* I2C1 SCL (GPIO87) */
-ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)             /* I2C5 (GPIO33/36) */
-ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */
-ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */
-ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
-ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
-ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) - EDP_BKLTCTL */
-/* TODO(Camera?) should have a poper config for this, PWM or not */
-ALTERNATE(PIN_MASK(C, 0x01), 1, MODULE_PWM, 0)             /* PWM6 (GPIOC0) - WCAM_EC_VSYNC */
-ALTERNATE(PIN_MASK(6, 0x01), 1, MODULE_PWM, 0)             /* PWM7 (GPIO60) - FCAM_EC_VSYNC */
-
-
diff --git a/board/wormdingler/led.c b/board/wormdingler/led.c
deleted file mode 100644
index 40de6257fa..0000000000
--- a/board/wormdingler/led.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-#include "extpower.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-/* Battery LED blinks every per 400ms */
-#define LED_HALF_ONE_SEC (500 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_GREEN,
-	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
-	if (color == LED_AMBER) {
-		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
-		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_RED] = 1;
-	brightness_range[EC_LED_COLOR_GREEN] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_RED] != 0)
-		led_set_color(LED_RED);
-	else if (brightness[EC_LED_COLOR_GREEN] != 0)
-		led_set_color(LED_GREEN);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
-			if (percent <= BATTERY_LEVEL_CRITICAL) {
-				/* battery capa <= 5%, Red */
-				color = LED_RED;
-			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
-				/* 5% < battery capa < 97%, Orange */
-				color = LED_AMBER;
-			} else {
-				/* battery capa >= 97%, Green */
-				color = LED_GREEN;
-			}
-		}
-		break;
-	case PWR_STATE_DISCHARGE:
-			/* Always indicate off on when discharging */
-			color = LED_OFF;
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error, Red on 1sec off 1sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_RED;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
-			color = LED_RED;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_RED : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/board/wormdingler/vif_override.xml b/board/wormdingler/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/wormdingler/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/yorp/battery.c b/board/yorp/battery.c
deleted file mode 100644
index 1d8ec33d3d..0000000000
--- a/board/yorp/battery.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * Battery info for all yorp battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* LGC AC15A8J Battery Information */
-	[BATTERY_LGC15] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.device_name = "AC15A8J",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0002,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11520, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Panasonic AP1505L Battery Information */
-	[BATTERY_PANASONIC] = {
-		.fuel_gauge = {
-			.manuf_name = "PANASONIC",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 13200,
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* SANYO AC15A3J Battery Information */
-	[BATTERY_SANYO] = {
-		.fuel_gauge = {
-			.manuf_name = "SANYO",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x4000,
-				.disconnect_val = 0x0,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-
-	/* Sony Ap13J4K Battery Information */
-	[BATTERY_SONY] = {
-		.fuel_gauge = {
-			.manuf_name = "SONYCorp",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x8000,
-				.disconnect_val = 0x8000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 50,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC;
diff --git a/board/yorp/board.c b/board/yorp/board.c
deleted file mode 100644
index 625db5d0b7..0000000000
--- a/board/yorp/board.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Yorp board-specific configuration */
-
-#include "adc.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "driver/accel_kionix.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/charger/bd9995x.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/tcpm/anx7447.h"
-#include "driver/tcpm/ps8xxx.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "power.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "tcpm/tcpci.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_PD_C0_INT_ODL:
-		nx20p348x_interrupt(0);
-		break;
-
-	case GPIO_USB_PD_C1_INT_ODL:
-		nx20p348x_interrupt(1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/* Must come after other header files and GPIO interrupts*/
-#include "gpio_list.h"
-
-/* ADC channels */
-const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* Motion sensors */
-/* Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-/* sensor private data */
-static struct kionix_accel_data g_kx022_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KX022,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &kionix_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_kx022_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
-		.rot_standard_ref = NULL, /* Identity matrix. */
-		.default_range = 2, /* g */
-		.min_frequency = KX022_ACCEL_MIN_FREQ,
-		.max_frequency = KX022_ACCEL_MAX_FREQ,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			/* Sensor on for lid angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			/* Sensor on for angle detection */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-		},
-	},
-
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.int_signal = GPIO_BASE_SIXAXIS_INT_L,
-		.flags = MOTIONSENSE_FLAG_INT_SIGNAL,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Initialize board. */
-static void board_init(void)
-{
-	/* Enable Base Accel interrupt */
-	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-void board_hibernate_late(void) {
-
-	int i;
-
-	const uint32_t hibernate_pins[][2] = {
-		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
-		gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
-}
-
-#ifndef TEST_BUILD
-static void post_old_board_warning(void)
-{
-	uint32_t board_id = 0;
-
-	cbi_get_board_version(&board_id);
-
-	if (board_id != 0)
-		return;
-
-	/*
-	 * BOARD ID 0 is officially deprecated. Indicate this by posting a
-	 * warning.
-	 */
-	CPRINTS("\n\n\n ***** BOARD ID 0 is not officially supported!!! *****"
-			"\n\n\n");
-}
-DECLARE_HOOK(HOOK_INIT, post_old_board_warning, HOOK_PRIO_INIT_I2C + 1);
-#endif
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Check that port number is valid. */
-	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
-		return;
-
-	/* Note that the level is inverted because the pin is active low. */
-	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
-}
diff --git a/board/yorp/board.h b/board/yorp/board.h
deleted file mode 100644
index 01f701184a..0000000000
--- a/board/yorp/board.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Yorp board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* Select Baseboard features */
-#define VARIANT_OCTOPUS_EC_NPCX796FB
-#define VARIANT_OCTOPUS_CHARGER_ISL9238
-#include "baseboard.h"
-
-/* EC console commands  */
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-#define CONFIG_LED_COMMON
-
-/* USB PD */
-#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-
-/* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THERMISTOR
-#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,
-	TEMP_SENSOR_AMBIENT,
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_LGC15,
-	BATTERY_PANASONIC,
-	BATTERY_SANYO,
-	BATTERY_SONY,
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/yorp/build.mk b/board/yorp/build.mk
deleted file mode 100644
index 3d04b75731..0000000000
--- a/board/yorp/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx7
-CHIP_VARIANT:=npcx7m6fb
-BASEBOARD:=octopus
-
-board-y=board.o led.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/yorp/ec.tasklist b/board/yorp/ec.tasklist
deleted file mode 100644
index d98db145e7..0000000000
--- a/board/yorp/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
deleted file mode 100644
index 9edd6107c6..0000000000
--- a/board/yorp/gpio.inc
+++ /dev/null
@@ -1,193 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/* Wake Source interrupts */
-GPIO_INT(LID_OPEN,	 PIN(D, 2), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
-/*
- * High-to-low transition on POWER_BUTTON_L is treated as a wake event from
- * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on
- * high-to-low edge.
- */
-GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
-GPIO_INT(AC_PRESENT,	 PIN(0, 0), GPIO_INT_BOTH |
-				    GPIO_HIB_WAKE_HIGH, extpower_interrupt)	/* ACOK_OD */
-
-/* USB-C interrupts */
-GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_PD_C0_INT_ODL,  PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_PD_C1_INT_ODL,  PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt)
-
-/* Power State interrupts */
-#ifdef CONFIG_POWER_S0IX
-GPIO_INT(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S0_L */
-#endif
-GPIO_INT(PCH_SLP_S4_L,	 PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S4_L */
-GPIO_INT(PCH_SLP_S3_L,	 PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt)	/* SLP_S3_L */
-GPIO_INT(SUSPWRDNACK,	 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRDNACK */
-GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_RSMRST_ODL */
-GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
-
-/* Other interrupts */
-GPIO_INT(WP_L,		 PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
-GPIO_INT(TABLET_MODE_L,	 PIN(8, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(5, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
-GPIO(LID_ACCEL_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)
-
-/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */
-#ifndef CONFIG_POWER_S0IX
-GPIO(PCH_SLP_S0_L,	 PIN(A, 4), GPIO_INPUT)		/* SLP_S0_L */
-#endif
-
-/*
- * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here
- * only for debugging purposes.
- */
-GPIO(PLT_RST_L,		 PIN(C, 7), GPIO_INPUT)		/* Platform Reset from SoC */
-GPIO(SYS_RESET_L,	 PIN(3, 4), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
-GPIO(PCH_RTCRST,	 PIN(7, 6), GPIO_OUT_LOW)	/* EC_PCH_RTCRST */
-
-GPIO(ENTERING_RW,	 PIN(E, 1), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
-GPIO(PCH_WAKE_L,	 PIN(7, 4), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
-GPIO(PCH_PWRBTN_L,	 PIN(C, 1), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */
-
-GPIO(EN_PP5000,		 PIN(7, 3), GPIO_OUT_LOW)	/* EN_PP5000_A */
-GPIO(PP5000_PG,		 PIN(C, 0), GPIO_INPUT)		/* PP5000_PG_OD */
-GPIO(EN_PP3300,		 PIN(D, 4), GPIO_OUT_LOW)	/* EN_PP3300_A */
-GPIO(PP3300_PG,		 PIN(6, 0), GPIO_INPUT)		/* PP3300_PG_OD */
-GPIO(PMIC_EN,		 PIN(7, 2), GPIO_OUT_LOW)	/* Enable A Rails via PMIC */
-GPIO(PCH_RSMRST_L,	 PIN(C, 2), GPIO_OUT_LOW)	/* RSMRST# to SOC. All _A rails now up. */
-GPIO(PCH_SYS_PWROK,	 PIN(B, 7), GPIO_OUT_LOW)	/* EC_PCH_PWROK. All S0 rails now up. */
-
-/* Peripheral rails */
-GPIO(ENABLE_BACKLIGHT,		PIN(D, 3), GPIO_ODR_HIGH |
-					   GPIO_SEL_1P8V)	/* EC_BL_EN_OD */
-GPIO(EN_P3300_TRACKPAD_ODL,	PIN(3, 3), GPIO_ODR_HIGH)
-
-GPIO(EC_BATT_PRES_L,	 PIN(E, 5), GPIO_INPUT)
-
-/*
- * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
- * not need to be an interrupt for normal EC operations. Thus, configure it as
- * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL
- * common code can configure PSL_IN correctly.
- *
- * Reason for choosing low-to-high edge for waking from hibernate is to avoid
- * the double reset - one because of PSL_IN wake and other because of VCC1_RST
- * being asserted. Also, it should be fine to have the EC in hibernate when H1
- * or servo wants to hold the EC in reset since VCC1 will be down and so entire
- * EC logic (except PSL) as well as AP will be in reset.
- *
- * We need to lock the setting so this gpio can't be reconfigured to overdrive
- * the real reset signal. (This is the PSL input pin not the real reset pin).
- */
-GPIO(EC_RST_ODL,	PIN(0, 2), GPIO_INT_BOTH |
-				   GPIO_HIB_WAKE_HIGH |
-				   GPIO_LOCKED)
-
-/*
- * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
- * normally driven by the PMIC. The EC can also drive this signal in the event
- * that the ambient or charger temperature sensors exceeds their thresholds.
- */
-GPIO(CPU_PROCHOT,	 PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V)	/* PCH_PROCHOT_ODL */
-
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(I2C0_SCL,		 PIN(B, 5), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SCL */
-GPIO(I2C0_SDA,		 PIN(B, 4), GPIO_INPUT)		/* EC_I2C_BATTERY_3V3_SDA */
-GPIO(I2C1_SCL,		 PIN(9, 0), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SCL */
-GPIO(I2C1_SDA,		 PIN(8, 7), GPIO_INPUT)		/* EC_I2C_USB_C0_MUX_SDA */
-GPIO(I2C2_SCL,		 PIN(9, 2), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SCL */
-GPIO(I2C2_SDA,		 PIN(9, 1), GPIO_INPUT)		/* EC_I2C_USB_C1_MUX_SDA */
-GPIO(I2C3_SCL,		 PIN(D, 1), GPIO_INPUT)		/* EC_I2C_EEPROM_SCL */
-GPIO(I2C3_SDA,		 PIN(D, 0), GPIO_INPUT)		/* EC_I2C_EEPROM_SDA */
-GPIO(I2C4_SCL,		 PIN(F, 3), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SCL */
-GPIO(I2C4_SDA,		 PIN(F, 2), GPIO_INPUT)		/* EC_I2C_CHARGER_3V3_SDA */
-GPIO(I2C7_SCL,		 PIN(B, 3), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SCL */
-GPIO(I2C7_SDA,		 PIN(B, 2), GPIO_INPUT |
-				    GPIO_SEL_1P8V)	/* EC_I2C_SENSOR_U_SDA */
-
-/* USB pins */
-GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
-GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
-GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
-GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
-GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
-GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
-GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-GPIO(USB_C1_PD_RST_ODL,	 PIN(7, 0), GPIO_ODR_HIGH)	/* C1 PD Reset */
-GPIO(USB_C1_BC12_VBUS_ON,   PIN(B, 1), GPIO_OUT_LOW)	/* C1 BC1.2 Power */
-GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
-GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
-				    GPIO_SEL_1P8V)
-
-/* Not implemented in hardware */
-UNIMPLEMENTED(USB_C0_PD_RST)
-
-/*
- * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it
- * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it
- * high.
- */
-GPIO(USB2_OTG_ID,	 PIN(8, 3), GPIO_ODR_LOW)	/* OTG ID */
-
-/* LED */
-GPIO(BAT_LED_ORANGE_L,	 PIN(C, 3), GPIO_OUT_HIGH)	/* LED_1_L */
-GPIO(BAT_LED_BLUE_L,	 PIN(C, 4), GPIO_OUT_HIGH)	/* LED_2_L */
-GPIO(LED_3_L,		 PIN(D, 7), GPIO_OUT_HIGH)
-
-/* Keyboard Backlight */
-GPIO(KB_BL_PWR_EN,	 PIN(6, 2), GPIO_OUT_LOW)
-
-/* Camera */
-GPIO(WFCAM_VSYNC,	 PIN(0, 3), GPIO_INPUT)	/* TP only */
-
-/* MKBP event synchronization */
-GPIO(EC_INT_L,		 PIN(9, 4), GPIO_ODR_HIGH)	/* EC_AP_INT_ODL */
-
-/* Overcurrent event to host */
-GPIO(USB_C_OC,      PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-
-/* Strap pins */
-GPIO(GPO66_NC,       PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP)
-GPIO(GPOB6_NC,       PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP)
-
-/* Misc. */
-GPIO(CCD_MODE_ODL,   PIN(E, 3), GPIO_INPUT)
-
-/* Keyboard pins */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)	/* KSO_10-12 */
-GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)	/* KSO_02 inverted */
-
-/* Alternate functions GPIO definitions */
-/* Cr50 requires no pull-ups on UART pins. */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)		/* UART from EC to Servo */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)		/* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* 1.8V I2C7 */
-ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0)		/* ADC0-1 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)		/* KB_BL_PWM */
-
-/* Power Switch Logic (PSL) inputs */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0)		/* GPIOD2 = LID_OPEN */
-ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0)		/* GPIO00 = ACOK_OD,
-							   GPIO01 = MECH_PWR_BTN_ODL
-							   GPIO02 = EC_RST_ODL */
diff --git a/board/yorp/led.c b/board/yorp/led.c
deleted file mode 100644
index 888b74fa12..0000000000
--- a/board/yorp/led.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control for Yorp
- */
-
-#include "ec_commands.h"
-#include "gpio.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
-
-__override const int led_charge_lvl_1;
-
-__override const int led_charge_lvl_2 = 100;
-
-/* Yorp: Note there is only LED for charge / power */
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
-BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
-
-const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_BLUE:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_ON_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	case EC_LED_COLOR_AMBER:
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_ON_LVL);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		gpio_set_level(GPIO_BAT_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_ORANGE_L, LED_OFF_LVL);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color_battery(EC_LED_COLOR_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color_battery(EC_LED_COLOR_AMBER);
-	else
-		led_set_color_battery(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
diff --git a/board/yorp/vif_override.xml b/board/yorp/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/yorp/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/board/zed b/board/zed
deleted file mode 120000
index 7f4a914148..0000000000
--- a/board/zed
+++ /dev/null
@@ -1 +0,0 @@
-hammer
\ No newline at end of file
diff --git a/board/zinger/board.c b/board/zinger/board.c
deleted file mode 100644
index b3784fde33..0000000000
--- a/board/zinger/board.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Tiny charger configuration */
-
-#include "common.h"
-#include "cros_version.h"
-#include "debug_printf.h"
-#include "ec_commands.h"
-#include "registers.h"
-#include "rsa.h"
-#include "rwsig.h"
-#include "sha256.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Large 768-Byte buffer for RSA computation : could be re-use afterwards... */
-static uint32_t rsa_workbuf[3 * RSANUMWORDS];
-
-extern void pd_rx_handler(void);
-
-/* RW firmware reset vector */
-static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4);
-
-/* External interrupt EXTINT7 for external comparator on PA7 */
-void pd_rx_interrupt(void)
-{
-	/* trigger reception handling */
-	pd_rx_handler();
-}
-DECLARE_IRQ(STM32_IRQ_EXTI4_15, pd_rx_interrupt, 1);
-
-static void jump_to_rw(void)
-{
-	void (*jump_rw_rst)(void) = (void *)*rw_rst;
-
-	debug_printf("Jump to RW\n");
-	/* Disable interrupts */
-	asm volatile("cpsid i");
-	/* Call RW firmware reset vector */
-	jump_rw_rst();
-}
-
-int is_ro_mode(void)
-{
-	return (uint32_t)&jump_to_rw < (uint32_t)rw_rst;
-}
-
-static int check_rw_valid(void *rw_hash)
-{
-	int good;
-
-	/* Check if we have a RW firmware flashed */
-	if (*rw_rst == 0xffffffff)
-		return 0;
-
-	good = rsa_verify((const struct rsa_public_key *)CONFIG_RO_PUBKEY_ADDR,
-			  (const uint8_t *)CONFIG_RW_SIG_ADDR,
-			  rw_hash, rsa_workbuf);
-	if (!good) {
-		debug_printf("RSA FAILED\n");
-		pd_log_event(PD_EVENT_ACC_RW_FAIL, 0, 0, NULL);
-		return 0;
-	}
-
-	return 1;
-}
-
-extern void pd_task(void *u);
-
-int main(void)
-{
-	void *rw_hash;
-
-	hardware_init();
-	debug_printf("%s started\n",
-		is_ro_mode() ? "RO" : "RW");
-
-	/* the RO partition protection is not enabled : do it */
-	if (!flash_physical_is_permanently_protected())
-		flash_physical_permanent_protect();
-
-	/*
-	 * calculate the hash of the RW partition
-	 *
-	 * Also pre-cache it so we can answer Discover Identity VDM
-	 * fast enough (in less than 30ms).
-	 */
-	rw_hash = flash_hash_rw();
-
-	/* Verify RW firmware and use it if valid */
-	if (is_ro_mode() && check_rw_valid(rw_hash))
-		jump_to_rw();
-
-	/* background loop for PD events */
-	pd_task(NULL);
-
-	debug_printf("EXIT!\n");
-	/* we should never reach that point */
-	system_reset(0);
-	return 0;
-}
diff --git a/board/zinger/board.h b/board/zinger/board.h
deleted file mode 100644
index 82fb29f29e..0000000000
--- a/board/zinger/board.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Tiny charger configuration. This config is used for multiple boards
- * including zinger and minimuffin.
- */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
-/* the UART console is on USART1 (PA9/PA10) */
-#define CONFIG_UART_CONSOLE 1
-
-#ifdef BOARD_ZINGER
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_ZINGER
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 1
-#elif defined(BOARD_MINIMUFFIN)
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR USB_PD_HW_DEV_ID_MINIMUFFIN
-#define CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR 0
-#else
-#error "Board does not have a USB-PD HW Device ID"
-#endif
-
-/* Optional features */
-#undef CONFIG_COMMON_GPIO
-#undef CONFIG_COMMON_PANIC_OUTPUT
-#undef CONFIG_COMMON_RUNTIME
-#undef CONFIG_COMMON_TIMER
-#define CONFIG_LOW_POWER_IDLE
-#undef CONFIG_CONSOLE_CMDHELP
-#undef CONFIG_DEBUG_ASSERT
-#undef CONFIG_DEBUG_EXCEPTIONS
-#undef CONFIG_DEBUG_STACK_OVERFLOW
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-/* Not using pstate but keep some space for the public key */
-#undef  CONFIG_FW_PSTATE_SIZE
-#define CONFIG_FW_PSTATE_SIZE 544
-#define CONFIG_HIBERNATE
-#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1
-#define CONFIG_HW_CRC
-#undef CONFIG_LID_SWITCH
-#define CONFIG_LTO
-#define CONFIG_RSA
-#define CONFIG_RWSIG_TYPE_USBPD1
-#define CONFIG_SHA256
-#undef CONFIG_TASK_PROFILING
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_CUSTOM_PDO
-#undef CONFIG_USB_PD_DUAL_ROLE
-#undef CONFIG_USB_PD_INTERNAL_COMP
-#define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
-#define CONFIG_EVENT_LOG_SIZE 256
-#define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#undef CONFIG_USB_PD_RX_COMP_IRQ
-#define CONFIG_USB_PD_SIMPLE_DFP
-#define CONFIG_USB_PD_VBUS_DETECT_GPIO
-#define CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
-#undef CONFIG_WATCHDOG_HELP
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 2300
-
-/* debug printf flash footprinf is about 1400 bytes */
-#define CONFIG_DEBUG_PRINTF
-#define UARTN CONFIG_UART_CONSOLE
-#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
-
-/* USB configuration */
-#if defined(BOARD_ZINGER)
-#define CONFIG_USB_PID 0x5012
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#elif defined(BOARD_MINIMUFFIN)
-#define CONFIG_USB_PID 0x5013
-#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include "common.h"
-
-/* No GPIO abstraction layer */
-
-enum adc_channel {
-	ADC_CH_CC1_PD = 1,
-	ADC_CH_A_SENSE = 2,
-	ADC_CH_V_SENSE = 3,
-	/* Number of ADC channels */
-	ADC_CH_COUNT
-};
-/* captive cable : no CC2 */
-#define ADC_CH_CC2_PD ADC_CH_CC1_PD
-
-/* 3.0A Rp */
-#define PD_SRC_VNC (PD_SRC_3_0_VNC_MV * 4096 / 3300/* 12-bit ADC, 3.3V range */)
-
-/* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
-
-/* Initialize all useful registers */
-void hardware_init(void);
-
-/* last interrupt event */
-extern volatile uint32_t last_event;
-
-/* RW section flashing */
-int flash_erase_rw(void);
-int flash_write_rw(int offset, int size, const char *data);
-void flash_physical_permanent_protect(void);
-int flash_physical_is_permanently_protected(void);
-uint8_t *flash_hash_rw(void);
-int is_ro_mode(void);
-
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/zinger/build.mk b/board/zinger/build.mk
deleted file mode 100644
index 566cf34ce0..0000000000
--- a/board/zinger/build.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board specific files build
-
-# the IC is STmicro STM32F031F6
-CHIP:=stm32
-CHIP_FAMILY:=stm32f0
-CHIP_VARIANT:=stm32f03x
-
-board-y=board.o hardware.o runtime.o usb_pd_policy.o
diff --git a/board/zinger/dev_key.pem b/board/zinger/dev_key.pem
deleted file mode 100644
index 6912b1f44e..0000000000
--- a/board/zinger/dev_key.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEpgIBAAKCAQEAvI3KBubudlZyX1oBNzWhQ+bNemHNVC5bO7TjJMTYTIJeKTaW
-IyHCFLF9ztpe8tT9Y+ga4VO9PEktP1WJpdU0ecG6VwK3951/cElosfnIPmIY7dVp
-PQtGtGS/Zih1nTMRV5hqtGa9SRg0i2kdph+quFXGQoMriTl0StmvNVtD51nRPGwc
-ZsG9+P0yfnyo7l3qXtKu5gBx/jDne2kl5/isPHkKfl9le+aNQaNjWeJyB4XDqHXM
-AjuW1G7FxoKlU4b363gQbE84Q80X1Qd9iAoRj/HLmDrx9h6FDFs+HbKDfCYtg2fK
-upEHr1bFUCxjc6AWuFglSq0yn5kyp1Bh5CD3PQIDAQABAoIBAQCNO2NlEhrx9sSK
-mX8pnHkjxECK97D16hcaPN6azvr5K/ldw25n+ERIfb4vb7AJEfKOn+9qce/ftSw4
-MVj+Jxm8TZjGzdmAlq87KzFJhkAwQghMNTszpzuZqZEX8xxN2E+YHilm4UHM+114
-Qw8bPMMCefUcIuY8ThXGbxFm1Oqi4YHHfqE6waRc0XXnLZOYr7NDCmhgyUG1dpAH
-kW0EYuJ1UNGaKE4LsWKvi0SYBQ48Mqh1XPkyiL/5I2whewsU2K4KEjynZp0+ULUG
-Dxfv3uCywsSsLuNR+EV5tTUp4eY1BLKULJQTMH3hyV1Xf1qEt2YN/3ZHsv7MPQzS
-sPIdN+LhAoGBAN6wbcxPnfkJROOVRUzE05IEEBalVULLo1cA1ss/7RjIeUvdRCAa
-12OxF4LSNzrSxcPCLsDnYq+j4HoS6KZ31c1TbaKcaUOPfRohrtGBZMxPgDTZgEBa
-JlsVtD2vzYvfUIpVQFz6Tnix3F29Gq5RaZdW5/qwOYyx0wtUrPf+pwZ5AoGBANjC
-MjgoGtcubR6chDhZcFU4vopdL7IEhMOZ1qxLFTQnINGXXDJpgVvdJRKdDV29DjNZ
-zF9wgmoiVm+uM/344bquUV7KHl5bEsZ+4KH6EA4y3IKVgxaxU7dpF6Q6L+rAuYp/
-j0N9XoVnS3aq30HkTkt+jQe0Hl6eEDOJqHEjolXlAoGBAJbMqs3cbIGkQT5May1d
-bFhI4Aw10dL1y5qzOsFQfOJ3f4xcPjHve0RLPDye1j/DU6EI8lg3WKDQPMbt3xY7
-uFDe2jNv7+iMVo9Hl/bPxM6GV69ySmNJqQetXu0XC/5YL1Y9/OP5rQIWj7/6uwKo
-pvSRKW6dv5sDIINfx/H4RGshAoGBAMIs7Tn7S1gaoev7QEMOdCAT7jUbF3/8pkZn
-SLUdqcgHiVHYquIKO7TknbJX+MJReygrOHcC3gFf81imkLLiQqyuPfyRSbUzFtW0
-kVzpG3rsuzdL4pvwjNNQFLqs2YIN1eipLtjBtWwCRcrvdYKcmDrvCj2tcEtIg7D3
-j2qTBni1AoGBAI58xPHxB0cNclhWiFHPNgk98GkwADWxfeTZduoyfpraSrpbseu8
-Cfgq1p5E2nM9jWx4jdKA/fxdD40bneupPi5w5SE2gmwtmQFR3TehI8gxNbEL2Gq6
-6ZkgxnGNxFaE6saHVDHKU8Q2bgzCI8JlOOtSjzKvbr+hsQMYHcEJxom6
------END RSA PRIVATE KEY-----
diff --git a/board/zinger/ec.irqlist b/board/zinger/ec.irqlist
deleted file mode 100644
index 690fa950fc..0000000000
--- a/board/zinger/ec.irqlist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * List of enabled IRQ. To enable an IRQ, use ENABLE_IRQ(irq_num). Any
- * IRQ that is not listed here is disabled.
- */
-
-ENABLE_IRQ(STM32_IRQ_EXTI4_15)
-ENABLE_IRQ(STM32_IRQ_ADC_COMP)
-ENABLE_IRQ(STM32_IRQ_TIM2)
-ENABLE_IRQ(STM32_IRQ_RTC_WAKEUP)
diff --git a/board/zinger/ec.tasklist b/board/zinger/ec.tasklist
deleted file mode 100644
index 091eb90a22..0000000000
--- a/board/zinger/ec.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c
deleted file mode 100644
index c19e6f0f6b..0000000000
--- a/board/zinger/hardware.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Hardware initialization and common functions */
-
-#include "adc.h"
-#include "common.h"
-#include "cpu.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-static void system_init(void)
-{
-	/* Enable access to RCC CSR register and RTC backup registers */
-	STM32_PWR_CR |= BIT(8);
-
-	/* switch on LSI */
-	STM32_RCC_CSR |= BIT(0);
-	/* Wait for LSI to be ready */
-	while (!(STM32_RCC_CSR & BIT(1)))
-		;
-	/* re-configure RTC if needed */
-	if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) {
-		/* the RTC settings are bad, we need to reset it */
-		STM32_RCC_BDCR |= 0x00010000;
-		/* Enable RTC and use LSI as clock source */
-		STM32_RCC_BDCR = (STM32_RCC_BDCR & ~0x00018300) | 0x00008200;
-	}
-}
-
-static void power_init(void)
-{
-	/* enable SYSCFG, COMP, ADC, SPI1, USART1 */
-	STM32_RCC_APB2ENR = 0x00005201;
-	/* enable TIM2, TIM3, TIM14, PWR */
-	STM32_RCC_APB1ENR = 0x10000103;
-	/* enable DMA, SRAM, CRC, GPA, GPB, GPF */
-	STM32_RCC_AHBENR  = 0x460045;
-}
-
-/* GPIO setting helpers */
-#define OUT(n) (1 << ((n) * 2))
-#define AF(n) (2 << ((n) * 2))
-#define ANALOG(n) (3 << ((n) * 2))
-#define HIGH(n) (1 << (n))
-#define ODR(n) (1 << (n))
-#define HISPEED(n) (3 << ((n) * 2))
-#define AFx(n, x) (x << (((n) % 8) * 4))
-
-static void pins_init(void)
-{
-	/* Pin usage:
-	 * PA0  (OUT - GPIO)       : Wakeup on Vnc / Threshold
-	 * PA1  (ANALOG - ADC_IN1) : CC sense
-	 * PA2  (ANALOG - ADC_IN2) : Current sense
-	 * PA3  (ANALOG - ADC_IN3) : Voltage sense
-	 * PA4  (OUT - OD GPIO)    : PD TX enable
-	 * PA5  (AF0 - SPI1_SCK)   : TX clock in
-	 * PA6  (AF0 - SPI1_MISO)  : PD TX
-	 * PA7  (AF5 - TIM3_CH2)   : PD RX
-	 * PA9  (AF1 - UART1_TX)   : [DEBUG] UART TX
-	 * PA10 (AF1 - UART1_RX)   : [DEBUG] UART RX
-	 * PA13 (OUT - GPIO)       : voltage select[0]
-	 * PA14 (OUT - GPIO)       : voltage select[1]
-	 * PB1  (AF0 - TIM14_CH1)  : TX clock out
-	 * PF0  (OUT - GPIO)       : LM5050 FET driver off
-	 * PF1  (OUT - GPIO)       : discharge FET
-	 */
-
-	/*
-	 * Clear power control/status register to disable wakeup
-	 * pin A0, so that we can change it to an output.
-	 */
-	STM32_PWR_CSR = 0;
-	STM32_PWR_CR |= 0xc;
-
-	STM32_GPIO_ODR(GPIO_A) = HIGH(0) | HIGH(4);
-	STM32_GPIO_AFRL(GPIO_A) = AFx(7, 1);
-	STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1);
-	STM32_GPIO_OTYPER(GPIO_A) = ODR(4);
-	STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7);
-	STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3)
-				 | OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9)
-				 | AF(10) | OUT(13) | OUT(14);
-	/* set PF0 / PF1 as output */
-	STM32_GPIO_ODR(GPIO_F) = 0;
-	STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1);
-	STM32_GPIO_OTYPER(GPIO_F) = 0;
-
-	/* Set PB1 as AF0 (TIM14_CH1) */
-	STM32_GPIO_OSPEEDR(GPIO_B) = HISPEED(1);
-	STM32_GPIO_MODER(GPIO_B) = AF(1);
-}
-
-static void adc_init(void)
-{
-	/* Only do the calibration if the ADC is off  */
-	if (!(STM32_ADC_CR & 1)) {
-		/* ADC calibration */
-		STM32_ADC_CR = STM32_ADC_CR_ADCAL; /* set ADCAL = 1, ADC off */
-		/* wait for the end of calibration */
-		while (STM32_ADC_CR & STM32_ADC_CR_ADCAL)
-			;
-	}
-	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */;
-	/* clock is ADCCLK (ADEN must be off when writing this reg) */
-	STM32_ADC_CFGR2 = 0;
-	/* Sampling time : 71.5 ADC clock cycles, about 5us */
-	STM32_ADC_SMPR = 6;
-
-	/*
-	 * ADC enable (note: takes 4 ADC clocks between end of calibration
-	 * and setting ADEN).
-	 */
-	STM32_ADC_CR = STM32_ADC_CR_ADEN;
-	while (!(STM32_ADC_ISR & STM32_ADC_ISR_ADRDY))
-		STM32_ADC_CR = STM32_ADC_CR_ADEN;
-	/* Disable interrupts */
-	STM32_ADC_IER = 0;
-	/* Analog watchdog IRQ */
-	task_enable_irq(STM32_IRQ_ADC_COMP);
-}
-
-static void uart_init(void)
-{
-	/* set baudrate */
-	STM32_USART_BRR(UARTN_BASE) =
-		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
-	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN_BASE) = 0x0000;
-	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN_BASE) = 0x0000;
-}
-
-static void timers_init(void)
-{
-	/* TIM2 is a 32-bit free running counter with 1Mhz frequency */
-	STM32_TIM_CR2(2) = 0x0000;
-	STM32_TIM32_ARR(2) = 0xFFFFFFFF;
-	STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1;
-	STM32_TIM_EGR(2) = 0x0001; /* Reload the pre-scaler */
-	STM32_TIM_CR1(2) = 1;
-	STM32_TIM32_CNT(2) = 0x00000000;
-	STM32_TIM_SR(2) = 0; /* Clear pending interrupts */
-	STM32_TIM_DIER(2) = 1; /* Overflow interrupt */
-	task_enable_irq(STM32_IRQ_TIM2);
-}
-
-static void irq_init(void)
-{
-	/* clear all pending interrupts */
-	CPU_NVIC_UNPEND(0) = 0xffffffff;
-	/* enable global interrupts */
-	asm("cpsie i");
-}
-
-extern void runtime_init(void);
-void hardware_init(void)
-{
-	uint32_t raw_cause = STM32_RCC_CSR;
-	uint32_t pwr_status = STM32_PWR_CSR;
-
-	power_init();
-
-	/* Clear the hardware reset cause by setting the RMVF bit */
-	STM32_RCC_CSR |= BIT(24);
-	/* Clear SBF in PWR_CSR */
-	STM32_PWR_CR |= BIT(3);
-
-	/*
-	 * WORKAROUND: as we cannot de-activate the watchdog during
-	 * long hibernation, we are woken-up once by the watchdog and
-	 * go back to hibernate if we detect that condition, without
-	 * watchdog initialized this time.
-	 * The RTC deadline (if any) is already set.
-	 */
-	if ((pwr_status & 0x2) && (raw_cause & 0x60000000))
-		__enter_hibernate(0, 0);
-
-	system_init();
-	runtime_init(); /* sets clock */
-	pins_init();
-	uart_init();
-	timers_init();
-	watchdog_init();
-	adc_init();
-	irq_init();
-}
-
-static int watchdog_ain_id, watchdog_ain_high, watchdog_ain_low;
-
-static int adc_enable_last_watchdog(void)
-{
-	return adc_enable_watchdog(watchdog_ain_id, watchdog_ain_high,
-			    watchdog_ain_low);
-}
-
-static inline int adc_watchdog_enabled(void)
-{
-	return STM32_ADC_CFGR1 & BIT(23);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	int value;
-	int watchdog_enabled = adc_watchdog_enabled();
-
-	if (watchdog_enabled)
-		adc_disable_watchdog();
-
-	/* Select channel to convert */
-	STM32_ADC_CHSELR = 1 << ch;
-	/* Clear flags */
-	STM32_ADC_ISR = 0x8e;
-	/* Start conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-	/* Wait for end of conversion */
-	while (!(STM32_ADC_ISR & BIT(2)))
-		;
-	/* read converted value */
-	value = STM32_ADC_DR;
-
-	if (watchdog_enabled)
-		adc_enable_last_watchdog();
-
-	return value;
-}
-
-int adc_enable_watchdog(int ch, int high, int low)
-{
-	/* store last watchdog setup */
-	watchdog_ain_id = ch;
-	watchdog_ain_high = high;
-	watchdog_ain_low = low;
-
-	/* Set thresholds */
-	STM32_ADC_TR = ((high & 0xfff) << 16) | (low & 0xfff);
-	/* Select channel to convert */
-	STM32_ADC_CHSELR = 1 << ch;
-	/* Clear flags */
-	STM32_ADC_ISR = 0x8e;
-	/* Set Watchdog enable bit on a single channel / continuous mode */
-	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22)
-			|  BIT(13) | BIT(12);
-	/* Enable watchdog interrupt */
-	STM32_ADC_IER = BIT(7);
-	/* Start continuous conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-
-	return EC_SUCCESS;
-}
-
-int adc_disable_watchdog(void)
-{
-	/* Stop on-going conversion */
-	STM32_ADC_CR |= BIT(4); /* ADSTP */
-	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & BIT(4))
-		;
-	/* CONT=0 -> continuous mode off / Clear Watchdog enable */
-	STM32_ADC_CFGR1 = BIT(12);
-	/* Disable interrupt */
-	STM32_ADC_IER = 0;
-	/* Clear flags */
-	STM32_ADC_ISR = 0x8e;
-
-	return EC_SUCCESS;
-}
-
-/* ---- flash handling ---- */
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_TIMEOUT_US 16000
-#define FLASH_TIMEOUT_LOOP \
-	(FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP)
-
-/* Flash unlocking keys */
-#define KEY1    0x45670123
-#define KEY2    0xCDEF89AB
-
-/* Lock bits for FLASH_CR register */
-#define PG       BIT(0)
-#define PER      BIT(1)
-#define OPTPG    BIT(4)
-#define OPTER    BIT(5)
-#define STRT     BIT(6)
-#define CR_LOCK  BIT(7)
-#define OPTWRE   BIT(9)
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int res = EC_SUCCESS;
-	int i;
-
-	if ((uint32_t)address >
-	    CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* unlock CR if needed */
-	if (STM32_FLASH_CR & CR_LOCK) {
-		STM32_FLASH_KEYR = KEY1;
-		STM32_FLASH_KEYR = KEY2;
-	}
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0x34;
-	/* set the ProGram bit */
-	STM32_FLASH_CR |= PG;
-
-	for (; size > 0; size -= sizeof(uint16_t)) {
-		/* wait to be ready  */
-		for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP);
-		     i++)
-			;
-		/* write the half word */
-		*address++ = data[0] + (data[1] << 8);
-		data += 2;
-		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP);
-		     i++)
-			;
-		if (i == FLASH_TIMEOUT_LOOP) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (STM32_FLASH_SR & 0x14) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	STM32_FLASH_CR &= ~PG;
-	STM32_FLASH_CR = CR_LOCK;
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-
-	/* unlock CR if needed */
-	if (STM32_FLASH_CR & CR_LOCK) {
-		STM32_FLASH_KEYR = KEY1;
-		STM32_FLASH_KEYR = KEY2;
-	}
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0x34;
-	/* set PER bit */
-	STM32_FLASH_CR |= PER;
-
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     offset += CONFIG_FLASH_ERASE_SIZE) {
-		int i;
-		/* select page to erase */
-		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR |= STRT;
-
-
-		/* Wait for erase to complete */
-		for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP);
-		     i++)
-			;
-		if (i == FLASH_TIMEOUT_LOOP) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & 0x14) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	STM32_FLASH_CR &= ~PER;
-	STM32_FLASH_CR = CR_LOCK;
-
-	return res;
-}
-
-static void unlock_erase_optb(void)
-{
-	int i;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0x34;
-
-	/* wait to be ready  */
-	for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++)
-		;
-
-	/* Unlock the option bytes access */
-	if (STM32_FLASH_CR & CR_LOCK) {
-		STM32_FLASH_KEYR = KEY1;
-		STM32_FLASH_KEYR = KEY2;
-	}
-	if (!(STM32_FLASH_CR & OPTWRE)) {
-		STM32_FLASH_OPTKEYR = KEY1;
-		STM32_FLASH_OPTKEYR = KEY2;
-	}
-	/* Must be set in 2 separate lines. */
-	STM32_FLASH_CR |= OPTER;
-	STM32_FLASH_CR |= STRT;
-
-	/* wait to be ready  */
-	for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++)
-		;
-	/* reset erasing bits */
-	STM32_FLASH_CR = OPTWRE;
-}
-
-
-static void write_optb(int byte, uint8_t value)
-{
-	volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
-	int i;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0x34;
-
-	/* set OPTPG bit */
-	STM32_FLASH_CR |= OPTPG;
-
-	*hword = ((~value) << STM32_OPTB_COMPL_SHIFT) | value;
-
-	/* reset OPTPG bit */
-	STM32_FLASH_CR = OPTWRE;
-
-	/* wait to be ready  */
-	for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++)
-		;
-}
-
-void flash_physical_permanent_protect(void)
-{
-	unlock_erase_optb();
-	/* protect the 16KB RO partition against write/erase in WRP0 */
-	write_optb(8, 0xF0);
-	/* Set RDP to level 1 to prevent disabling the protection */
-	write_optb(0, 0x11);
-	/* Reset by using OBL_LAUNCH to take changes into account */
-	asm volatile("cpsid i");
-	STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int flash_physical_is_permanently_protected(void)
-{
-	/* if RDP is still at level 0, the flash protection is not in place */
-	return (STM32_FLASH_OBR & STM32_FLASH_OBR_RDP_MASK) &&
-		/* the low 16KB (RO partition) are write-protected */
-		!(STM32_FLASH_WRPR & 0xF);
-}
diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c
deleted file mode 100644
index 5d17bfda04..0000000000
--- a/board/zinger/runtime.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* tiny substitute of the runtime layer */
-
-#include "chip/stm32/clock-f.h"
-#include "clock.h"
-#include "common.h"
-#include "cpu.h"
-#include "debug_printf.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-volatile uint32_t last_event;
-uint32_t sleep_mask;
-
-/* High word of the 64-bit timestamp counter  */
-static volatile uint32_t clksrc_high;
-
-timestamp_t get_time(void)
-{
-	timestamp_t t;
-
-	t.le.lo = STM32_TIM32_CNT(2);
-	t.le.hi = clksrc_high;
-	return t;
-}
-
-void force_time(timestamp_t ts)
-{
-	STM32_TIM32_CNT(2) = ts.le.lo;
-}
-
-void udelay(unsigned us)
-{
-	unsigned t0 = STM32_TIM32_CNT(2);
-	while ((STM32_TIM32_CNT(2) - t0) < us)
-		;
-}
-
-void task_enable_irq(int irq)
-{
-	CPU_NVIC_EN(0) = 1 << irq;
-}
-
-void task_disable_irq(int irq)
-{
-	CPU_NVIC_DIS(0) = 1 << irq;
-}
-
-void task_clear_pending_irq(int irq)
-{
-	CPU_NVIC_UNPEND(0) = 1 << irq;
-}
-
-void interrupt_disable(void)
-{
-	asm("cpsid i");
-}
-
-void interrupt_enable(void)
-{
-	asm("cpsie i");
-}
-
-uint32_t task_set_event(task_id_t tskid, uint32_t event)
-{
-	last_event = event;
-
-	return 0;
-}
-
-void tim2_interrupt(void)
-{
-	uint32_t stat = STM32_TIM_SR(2);
-
-	if (stat & 2) { /* Event match */
-		/* disable match interrupt but keep update interrupt */
-		STM32_TIM_DIER(2) = 1;
-		last_event = TASK_EVENT_TIMER;
-	}
-	if (stat & 1) /* Counter overflow */
-		clksrc_high++;
-
-	STM32_TIM_SR(2) = ~stat & 3; /* clear interrupt flags */
-	task_clear_pending_irq(STM32_IRQ_TIM2);
-}
-DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
-
-static void zinger_config_hispeed_clock(void)
-{
-	/* Ensure that HSI8 is ON */
-	if (!(STM32_RCC_CR & BIT(1))) {
-		/* Enable HSI */
-		STM32_RCC_CR |= BIT(0);
-		/* Wait for HSI to be ready */
-		while (!(STM32_RCC_CR & BIT(1)))
-			;
-	}
-	/* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */
-	STM32_RCC_CFGR = 0x00288000;
-	/* Enable PLL */
-	STM32_RCC_CR |= BIT(24);
-	/* Wait for PLL to be ready */
-	while (!(STM32_RCC_CR & BIT(25)))
-			;
-
-	/* switch SYSCLK to PLL */
-	STM32_RCC_CFGR = 0x00288002;
-	/* wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-}
-
-void runtime_init(void)
-{
-	/*
-	 * put 1 Wait-State for flash access to ensure proper reads at 48Mhz
-	 * and enable prefetch buffer.
-	 */
-	STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN;
-
-	config_hispeed_clock();
-
-	rtc_init();
-}
-
-/*
- * minimum delay to enter stop mode
- * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low
- * power mode is 5 us + PLL locking time is 200us.
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. if we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- */
-#define STOP_MODE_LATENCY 300   /* us */
-#define SET_RTC_MATCH_DELAY 200 /* us */
-#define MAX_LATENCY (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY)
-
-uint32_t task_wait_event(int timeout_us)
-{
-	uint32_t evt;
-	timestamp_t t0, t1;
-	struct rtc_time_reg rtc0, rtc1;
-
-	t1.val = get_time().val + timeout_us;
-
-	asm volatile("cpsid i");
-	/* the event already happened */
-	if (last_event || !timeout_us) {
-		evt = last_event;
-		last_event = 0;
-
-		asm volatile("cpsie i ; isb");
-		return evt;
-	}
-
-	/* loop until an event is triggered */
-	while (1) {
-		/* set timeout on timer */
-		if (timeout_us < 0) {
-			asm volatile ("wfi");
-		} else if (timeout_us <= MAX_LATENCY ||
-			  t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY ||
-			  !DEEP_SLEEP_ALLOWED) {
-			STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us;
-			STM32_TIM_DIER(2) = 3; /*  match interrupt and UIE */
-
-			asm volatile("wfi");
-
-			STM32_TIM_DIER(2) = 1; /* disable match, keep UIE */
-		} else {
-			t0 = get_time();
-
-			/* set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY,
-				      &rtc0, 0);
-
-			asm volatile("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			zinger_config_hispeed_clock();
-
-			/* fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			t0.val += get_rtc_diff(&rtc0, &rtc1);
-			force_time(t0);
-		}
-
-		asm volatile("cpsie i ; isb");
-		/* note: interrupt that woke us up will run here */
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		/* check for timeout if timeout was set */
-		if (timeout_us >= 0 && t0.val >= t1.val)
-			last_event = TASK_EVENT_TIMER;
-		/* break from loop when event has triggered */
-		if (last_event)
-			break;
-		/* recalculate timeout if timeout was set */
-		if (timeout_us >= 0)
-			timeout_us = t1.val - t0.val;
-	}
-
-	evt = last_event;
-	last_event = 0;
-	asm volatile("cpsie i ; isb");
-	return evt;
-}
-
-uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint32_t evt = 0;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	/* Wait until an event matching event_mask */
-	do {
-		evt |= task_wait_event(timeout_us);
-	} while (!(evt & event_mask));
-
-	/* Restore any pending events not in the event_mask */
-	if (evt & ~event_mask)
-		task_set_event(0, evt & ~event_mask);
-
-	return evt & event_mask;
-}
-
-noreturn
-void __keep cpu_reset(void)
-{
-	/* Disable interrupts */
-	asm volatile("cpsid i");
-	/* reboot the CPU */
-	CPU_NVIC_APINT = 0x05fa0004;
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	cpu_reset();
-}
-/**
- * Default exception handler, which reports a panic.
- *
- * Declare this as a naked call so we can extract the real LR and SP.
- */
-void exception_panic(void) __attribute__((naked));
-void exception_panic(void)
-{
-#ifdef CONFIG_DEBUG_PRINTF
-	asm volatile(
-		"mov r0, %0\n"
-		/* TODO: Should this be SP_process instead of SP_main? */
-		"mov r3, sp\n"
-		"ldr r1, [r3, #6*4]\n" /* retrieve exception PC */
-		"ldr r2, [r3, #5*4]\n" /* retrieve exception LR */
-		"bl debug_printf\n"
-	: : "r"("PANIC PC=%08x LR=%08x\n\n"));
-#endif
-	cpu_reset();
-}
-
-void panic_reboot(void)
-{ /* for div / 0 */
-	debug_printf("DIV0 PANIC\n\n");
-	cpu_reset();
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	if (is_ro_mode())
-		return EC_IMAGE_RO;
-	else
-		return EC_IMAGE_RW;
-}
-
-/* --- stubs --- */
-void __hw_timer_enable_clock(int n, int enable)
-{ /* Done in hardware init */ }
-
-void usleep(unsigned us)
-{ /* Used only as a workaround */ }
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
deleted file mode 100644
index d0797b3d80..0000000000
--- a/board/zinger/usb_pd_config.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery board configuration */
-
-#ifndef __CROS_EC_USB_PD_CONFIG_H
-#define __CROS_EC_USB_PD_CONFIG_H
-
-/* Timer selection for baseband PD communication */
-#define TIM_CLOCK_PD_TX_C0 14
-#define TIM_CLOCK_PD_RX_C0  3
-
-#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
-#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
-
-/* Timer channel */
-#define TIM_RX_CCR_C0 1
-#define TIM_TX_CCR_C0 1
-
-/* RX timer capture/compare register */
-#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
-#define TIM_RX_CCR_REG(p) TIM_CCR_C0
-
-/* TX and RX timer register */
-#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
-#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
-#define TIM_REG_TX(p) TIM_REG_TX_C0
-#define TIM_REG_RX(p) TIM_REG_RX_C0
-
-/* use the hardware accelerator for CRC */
-#define CONFIG_HW_CRC
-
-/* TX is using SPI1 on PA4-6 */
-#define SPI_REGS(p) STM32_SPI1_REGS
-
-static inline void spi_enable_clock(int port)
-{
-	/* Already done in hardware_init() */
-}
-
-#define DMAC_SPI_TX(p) STM32_DMAC_CH3
-
-/* RX is on TIM3 CH1 connected to TIM3 CH2 pin (PA7, not internal COMP) */
-#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-/* connect TIM3 CH1 to TIM3_CH2 input */
-#define TIM_CCR_CS  2
-#define EXTI_COMP_MASK(p) BIT(7)
-#define IRQ_COMP STM32_IRQ_EXTI4_15
-/* the RX is inverted, triggers on rising edge */
-#define EXTI_XTSR STM32_EXTI_RTSR
-
-#define DMAC_TIM_RX(p) STM32_DMAC_CH4
-
-/* the pins used for communication need to be hi-speed */
-static inline void pd_set_pins_speed(int port)
-{
-	/* Already done in hardware_init() */
-}
-
-/* Reset SPI peripheral used for TX */
-static inline void pd_tx_spi_reset(int port)
-{
-	/* Reset SPI1 */
-	STM32_RCC_APB2RSTR |= BIT(12);
-	STM32_RCC_APB2RSTR &= ~BIT(12);
-}
-
-/* Drive the CC line from the TX block */
-static inline void pd_tx_enable(int port, int polarity)
-{
-	/* Drive SPI MISO on PA6 by putting it in AF mode  */
-	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2*6);
-	/* Drive TX GND on PA4 */
-	STM32_GPIO_BSRR(GPIO_A) = 1 << (4 + 16 /* Reset */);
-}
-
-/* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(int port, int polarity)
-{
-	/* Put TX GND (PA4) in Hi-Z state */
-	STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
-	/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode  */
-	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
-}
-
-/* we know the plug polarity, do the right configuration */
-static inline void pd_select_polarity(int port, int polarity)
-{
-	/* captive cable : no polarity */
-}
-
-/* Initialize pins used for TX and put them in Hi-Z */
-static inline void pd_tx_init(void)
-{
-	/* Already done in hardware_init() */
-}
-
-static inline void pd_config_init(int port, uint8_t power_role) {}
-
-static inline int pd_adc_read(int port, int cc)
-{
-	/* only one CC line, assume other one is always high */
-	return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 4096;
-}
-
-#endif /* __CROS_EC_USB_PD_CONFIG_H */
diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c
deleted file mode 100644
index f47789e063..0000000000
--- a/board/zinger/usb_pd_policy.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "debug_printf.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-
-/* ------------------------- Power supply control ------------------------ */
-
-/* GPIO level setting helpers through BSRR register */
-#define GPIO_SET(n)   (1 << (n))
-#define GPIO_RESET(n) (1 << ((n) + 16))
-
-/* Output voltage selection */
-enum volt {
-	VO_5V  = GPIO_RESET(13) | GPIO_RESET(14),
-	VO_12V = GPIO_SET(13)   | GPIO_RESET(14),
-	VO_13V = GPIO_RESET(13) | GPIO_SET(14),
-	VO_20V = GPIO_SET(13)   | GPIO_SET(14),
-};
-
-static inline void set_output_voltage(enum volt v)
-{
-	/* set voltage_select on PA13/PA14 */
-	STM32_GPIO_BSRR(GPIO_A) = v;
-}
-
-static inline void output_enable(void)
-{
-	/* GPF0 (enable OR'ing FETs) = 1 */
-	STM32_GPIO_BSRR(GPIO_F) = GPIO_SET(0);
-}
-
-static inline void output_disable(void)
-{
-	/* GPF0 (disable OR'ing FETs) = 0 */
-	STM32_GPIO_BSRR(GPIO_F) = GPIO_RESET(0);
-}
-
-static inline int output_is_enabled(void)
-{
-	/* GPF0 = enable output FET */
-	return STM32_GPIO_ODR(GPIO_F) & 1;
-}
-
-/* ----- fault conditions ----- */
-
-enum faults {
-	FAULT_OK = 0,
-	FAULT_OCP, /* Over-Current Protection */
-	FAULT_FAST_OCP, /* Over-Current Protection for interrupt context */
-	FAULT_OVP, /* Under or Over-Voltage Protection */
-	FAULT_DISCHARGE, /* Discharge was ineffective */
-};
-
-/* current fault condition */
-static enum faults fault;
-/* expiration date of the last fault condition */
-static timestamp_t fault_deadline;
-
-/* ADC in 12-bit mode */
-#define ADC_SCALE BIT(12)
-/* ADC power supply : VDDA = 3.3V */
-#define VDDA_MV   3300
-/* Current sense resistor : 5 milliOhm */
-#define R_SENSE   5
-/* VBUS voltage is measured through 10k / 100k voltage divider = /11 */
-#define VOLT_DIV  ((10+100)/10)
-/* The current sensing op-amp has a x100 gain */
-#define CURR_GAIN 100
-/* convert VBUS voltage in raw ADC value */
-#define VBUS_MV(mv) ((mv)*ADC_SCALE/VOLT_DIV/VDDA_MV)
-/* convert VBUS current in raw ADC value */
-#define VBUS_MA(ma) ((ma)*ADC_SCALE*R_SENSE/1000*CURR_GAIN/VDDA_MV)
-/* convert raw ADC value to mA */
-#define ADC_TO_CURR_MA(vbus) ((vbus)*1000/(ADC_SCALE*R_SENSE)*VDDA_MV/CURR_GAIN)
-/* convert raw ADC value to mV */
-#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV*VDDA_MV/ADC_SCALE)
-
-/* Max current */
-#if defined(BOARD_ZINGER)
-#define RATED_CURRENT 3000
-#elif defined(BOARD_MINIMUFFIN)
-#define RATED_CURRENT 2250
-#endif
-
-/* Max current : 20% over rated current */
-#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6/5)
-/* Fast short circuit protection : 50% over rated current */
-#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3/2)
-/* reset over-current after 1 second */
-#define OCP_TIMEOUT SECOND
-
-/* Threshold below which we stop fast OCP to save power */
-#define SINK_IDLE_CURRENT VBUS_MA(500 /* mA */)
-
-/* Under-voltage limit is 0.8x Vnom */
-#define UVP_MV(mv)  VBUS_MV((mv) * 8 / 10)
-/* Over-voltage limit is 1.2x Vnom */
-#define OVP_MV(mv)  VBUS_MV((mv) * 12 / 10)
-/* Over-voltage recovery threshold is 1.1x Vnom */
-#define OVP_REC_MV(mv)  VBUS_MV((mv) * 11 / 10)
-
-/* Maximum discharging delay */
-#define DISCHARGE_TIMEOUT (275*MSEC)
-/* Voltage overshoot below the OVP threshold for discharging to avoid OVP */
-#define DISCHARGE_OVERSHOOT_MV VBUS_MV(200)
-
-/* Time to wait after last RX edge interrupt before allowing deep sleep */
-#define PD_RX_SLEEP_TIMEOUT (100*MSEC)
-
-/* ----- output voltage discharging ----- */
-
-/* expiration date of the discharge */
-static timestamp_t discharge_deadline;
-
-static inline void discharge_enable(void)
-{
-	STM32_GPIO_BSRR(GPIO_F) = GPIO_SET(1);
-}
-
-static inline void discharge_disable(void)
-{
-	STM32_GPIO_BSRR(GPIO_F) = GPIO_RESET(1);
-	adc_disable_watchdog();
-}
-
-static inline int discharge_is_enabled(void)
-{
-	/* GPF1 = enable discharge FET */
-	return STM32_GPIO_ODR(GPIO_F) & 2;
-}
-
-static void discharge_voltage(int target_volt)
-{
-	discharge_enable();
-	discharge_deadline.val = get_time().val + DISCHARGE_TIMEOUT;
-	/* Monitor VBUS voltage */
-	target_volt -= DISCHARGE_OVERSHOOT_MV;
-	disable_sleep(SLEEP_MASK_USB_PWR);
-	adc_enable_watchdog(ADC_CH_V_SENSE, 0xFFF, target_volt);
-}
-
-/* ----------------------- USB Power delivery policy ---------------------- */
-
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
-
-/* Voltage indexes for the PDOs */
-enum volt_idx {
-	PDO_IDX_5V  = 0,
-	PDO_IDX_12V = 1,
-	PDO_IDX_20V = 2,
-
-	PDO_IDX_COUNT
-};
-
-/* Power Delivery Objects */
-const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  RATED_CURRENT, PDO_FIXED_FLAGS),
-	[PDO_IDX_12V] = PDO_FIXED(12000, RATED_CURRENT, PDO_FIXED_FLAGS),
-	[PDO_IDX_20V] = PDO_FIXED(20000, RATED_CURRENT, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
-
-/* PDO voltages (should match the table above) */
-static const struct {
-	enum volt select; /* GPIO configuration to select the voltage */
-	int       uvp;    /* under-voltage limit in mV */
-	int       ovp;    /* over-voltage limit in mV */
-	int       ovp_rec;/* over-voltage recovery threshold in mV */
-} voltages[ARRAY_SIZE(pd_src_pdo)] = {
-	[PDO_IDX_5V]  = {VO_5V,  UVP_MV(5000),  OVP_MV(5000),
-						OVP_REC_MV(5000)},
-	[PDO_IDX_12V] = {VO_12V, UVP_MV(12000), OVP_MV(12000),
-						OVP_REC_MV(12000)},
-	[PDO_IDX_20V] = {VO_20V, UVP_MV(20000), OVP_MV(20000),
-						OVP_REC_MV(20000)},
-};
-
-/* current and previous selected PDO entry */
-static int volt_idx;
-static int last_volt_idx;
-/* target voltage at the end of discharge */
-static int discharge_volt_idx;
-
-/* output current measurement */
-int vbus_amp;
-
-__override int pd_board_check_request(uint32_t rdo, int pdo_cnt)
-{
-	/* fault condition or output disabled: reject transitions */
-	if (fault != FAULT_OK || !output_is_enabled())
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-void pd_transition_voltage(int idx)
-{
-	last_volt_idx = volt_idx;
-	volt_idx = idx - 1;
-	if (volt_idx < last_volt_idx) { /* down voltage transition */
-		/* Stop OCP monitoring */
-		adc_disable_watchdog();
-
-		discharge_volt_idx = volt_idx;
-		/* from 20V : do an intermediate step at 12V */
-		if (volt_idx == PDO_IDX_5V && last_volt_idx == PDO_IDX_20V)
-			volt_idx = PDO_IDX_12V;
-		discharge_voltage(voltages[volt_idx].ovp);
-	} else if (volt_idx > last_volt_idx) { /* up voltage transition */
-		if (discharge_is_enabled()) {
-			/* Make sure discharging is disabled */
-			discharge_disable();
-			/* Enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
-		}
-	}
-	set_output_voltage(voltages[volt_idx].select);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* fault condition not cleared : do not turn on power */
-	if ((fault != FAULT_OK) || discharge_is_enabled())
-		return EC_ERROR_INVAL;
-
-	output_enable();
-	/* Over-current monitoring */
-	adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, 0);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-void pd_power_supply_reset(int port)
-{
-	int need_discharge = (volt_idx > 0) || discharge_is_enabled();
-
-	output_disable();
-	last_volt_idx = volt_idx;
-	/* from 20V : do an intermediate step at 12V */
-	volt_idx = volt_idx == PDO_IDX_20V ? PDO_IDX_12V : PDO_IDX_5V;
-	set_output_voltage(voltages[volt_idx].select);
-	/* TODO transition delay */
-
-	/* Stop OCP monitoring to save power */
-	adc_disable_watchdog();
-
-	/* discharge voltage to 5V ? */
-	if (need_discharge) {
-		/* final target : 5V  */
-		discharge_volt_idx = PDO_IDX_5V;
-		discharge_voltage(voltages[volt_idx].ovp);
-	}
-}
-
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
-{
-	/* Allow data swap if we are a DFP, otherwise don't allow */
-	return (data_role == PD_ROLE_DFP) ? 1 : 0;
-}
-
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
-{
-	/* Do nothing */
-}
-
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
-{
-}
-
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
-{
-	/* If DFP, try to switch to UFP */
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
-		pd_request_data_swap(port);
-}
-
-int pd_board_checks(void)
-{
-#ifdef CONFIG_HIBERNATE
-	static timestamp_t hib_to;
-	static int hib_to_ready;
-#endif
-	int vbus_volt;
-	int ovp_idx;
-
-	/* Reload the watchdog */
-	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-
-#ifdef CONFIG_HIBERNATE
-	/* If output is disabled for long enough, then hibernate */
-	if (!pd_is_connected(0) && hib_to_ready) {
-		if (get_time().val >= hib_to.val) {
-			debug_printf("hib\n");
-			__enter_hibernate(0, 0);
-		}
-	} else {
-		hib_to.val = get_time().val + 60*SECOND;
-		hib_to_ready = 1;
-	}
-#endif
-
-	/* if it's been a while since last RX edge, then allow deep sleep */
-	if (get_time_since_last_edge(0) > PD_RX_SLEEP_TIMEOUT)
-		enable_sleep(SLEEP_MASK_USB_PD);
-
-	vbus_volt = adc_read_channel(ADC_CH_V_SENSE);
-	vbus_amp = adc_read_channel(ADC_CH_A_SENSE);
-
-	if (fault == FAULT_FAST_OCP) {
-		debug_printf("Fast OCP\n");
-		pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_FAST_OCP, NULL);
-		fault = FAULT_OCP;
-		/* reset over-current after 1 second */
-		fault_deadline.val = get_time().val + OCP_TIMEOUT;
-		return EC_ERROR_INVAL;
-	}
-
-	if (vbus_amp > MAX_CURRENT) {
-		/* 3 more samples to check whether this is just a transient */
-		int count;
-		for (count = 0; count < 3; count++)
-			if (adc_read_channel(ADC_CH_A_SENSE) < MAX_CURRENT)
-				break;
-		/* trigger the slow OCP iff all 4 samples are above the max */
-		if (count == 3) {
-			debug_printf("OCP %d mA\n",
-			  vbus_amp * VDDA_MV / CURR_GAIN * 1000
-				   / R_SENSE / ADC_SCALE);
-			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OCP, NULL);
-			fault = FAULT_OCP;
-			/* reset over-current after 1 second */
-			fault_deadline.val = get_time().val + OCP_TIMEOUT;
-			return EC_ERROR_INVAL;
-		}
-	}
-	/*
-	 * Optimize power consumption when the sink is idle :
-	 * Enable STOP mode while we are connected,
-	 * this kills fast OCP as the actual ADC conversion for the analog
-	 * watchdog will happen on the next wake-up (x0 ms latency).
-	 */
-	if (vbus_amp < SINK_IDLE_CURRENT && !discharge_is_enabled())
-		/* override the PD state machine sleep mask */
-		enable_sleep(SLEEP_MASK_USB_PWR);
-	else if (vbus_amp > SINK_IDLE_CURRENT)
-		disable_sleep(SLEEP_MASK_USB_PWR);
-
-	/*
-	 * Set the voltage index to use for checking OVP. During a down step
-	 * transition, use the previous voltage index to check for OVP.
-	 */
-	ovp_idx = discharge_is_enabled() ? last_volt_idx : volt_idx;
-
-	if ((output_is_enabled() && (vbus_volt > voltages[ovp_idx].ovp)) ||
-	    (fault && (vbus_volt > voltages[ovp_idx].ovp_rec))) {
-		if (!fault) {
-			debug_printf("OVP %d mV\n",
-				     ADC_TO_VOLT_MV(vbus_volt));
-			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OVP, NULL);
-		}
-		fault = FAULT_OVP;
-		/* no timeout */
-		fault_deadline.val = get_time().val;
-		return EC_ERROR_INVAL;
-	}
-
-	/* the discharge did not work properly */
-	if (discharge_is_enabled() &&
-		(get_time().val > discharge_deadline.val)) {
-		/* ensure we always finish a 2-step discharge */
-		volt_idx = discharge_volt_idx;
-		set_output_voltage(voltages[volt_idx].select);
-		/* stop it */
-		discharge_disable();
-		/* enable over-current monitoring */
-		adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, 0);
-		debug_printf("Disch FAIL %d mV\n",
-			     ADC_TO_VOLT_MV(vbus_volt));
-		pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_DISCH, NULL);
-		fault = FAULT_DISCHARGE;
-		/* reset it after 1 second */
-		fault_deadline.val = get_time().val + OCP_TIMEOUT;
-		return EC_ERROR_INVAL;
-	}
-
-	/* everything is good *and* the error condition has expired */
-	if ((fault != FAULT_OK) && (get_time().val > fault_deadline.val)) {
-		fault = FAULT_OK;
-		debug_printf("Reset fault\n");
-		/*
-		 * Reset the PD state and communication on both side,
-		 * so we can now re-negociate a voltage.
-		 */
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-
-}
-
-void pd_adc_interrupt(void)
-{
-	/* Clear flags */
-	STM32_ADC_ISR = 0x8e;
-
-	if (discharge_is_enabled()) {
-		if (discharge_volt_idx != volt_idx) {
-			/* first step of the discharge completed: now 12V->5V */
-			volt_idx = PDO_IDX_5V;
-			set_output_voltage(VO_5V);
-			discharge_voltage(voltages[PDO_IDX_5V].ovp);
-		} else { /* discharge complete */
-			discharge_disable();
-			/* enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
-		}
-	} else {/* Over-current detection */
-		/* cut the power output */
-		pd_power_supply_reset(0);
-		/* record a special fault */
-		fault = FAULT_FAST_OCP;
-		/* pd_board_checks() will record the timeout later */
-	}
-
-	/* clear ADC irq so we don't get a second interrupt */
-	task_clear_pending_irq(STM32_IRQ_ADC_COMP);
-}
-DECLARE_IRQ(STM32_IRQ_ADC_COMP, pd_adc_interrupt, 1);
-
-/* ----------------- Vendor Defined Messages ------------------ */
-const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
-				 0, /* data caps as USB device */
-				 IDH_PTYPE_UNDEF, /* Undefined */
-				 1, /* supports alt modes */
-				 USB_VID_GOOGLE);
-
-const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
-
-/* When set true, we are in GFU mode */
-static int gfu_mode;
-
-static int svdm_response_identity(int port, uint32_t *payload)
-{
-	payload[VDO_I(IDH)] = vdo_idh;
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-	return VDO_I(PRODUCT) + 1;
-}
-
-static int svdm_response_svids(int port, uint32_t *payload)
-{
-	payload[1] = VDO_SVID(USB_VID_GOOGLE, 0);
-	return 2;
-}
-
-/* Will only ever be a single mode for this device */
-#define MODE_CNT 1
-#define OPOS 1
-
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
-
-static int svdm_response_modes(int port, uint32_t *payload)
-{
-	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE)
-		return 0; /* nak */
-
-	memcpy(payload + 1, vdo_dp_mode, sizeof(vdo_dp_mode));
-	return MODE_CNT + 1;
-}
-
-static int svdm_enter_mode(int port, uint32_t *payload)
-{
-	/* SID & mode request is valid */
-	if ((PD_VDO_VID(payload[0]) != USB_VID_GOOGLE) ||
-	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0; /* will generate NAK */
-
-	gfu_mode = 1;
-	debug_printf("GFU\n");
-	return 1;
-}
-
-static int svdm_exit_mode(int port, uint32_t *payload)
-{
-	gfu_mode = 0;
-	return 1; /* Must return ACK */
-}
-
-static struct amode_fx dp_fx = {
-	.status = NULL,
-	.config = NULL,
-};
-
-const struct svdm_response svdm_rsp = {
-	.identity = &svdm_response_identity,
-	.svids = &svdm_response_svids,
-	.modes = &svdm_response_modes,
-	.enter_mode = &svdm_enter_mode,
-	.amode = &dp_fx,
-	.exit_mode = &svdm_exit_mode,
-};
-
-__override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-	int rsize;
-
-	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE || !gfu_mode)
-		return 0;
-
-	debug_printf("%pT] VDM/%d [%d] %08x\n",
-		     PRINTF_TIMESTAMP_NOW, cnt, cmd, payload[0]);
-	*rpayload = payload;
-
-	rsize = pd_custom_flash_vdm(port, cnt, payload);
-	if (!rsize) {
-		switch (cmd) {
-		case VDO_CMD_PING_ENABLE:
-			pd_ping_enable(0, payload[1]);
-			rsize = 1;
-			break;
-		case VDO_CMD_CURRENT:
-			/* return last measured current */
-			payload[1] = ADC_TO_CURR_MA(vbus_amp);
-			rsize = 2;
-			break;
-		case VDO_CMD_GET_LOG:
-			rsize = pd_vdm_get_log_entry(payload);
-			break;
-		default:
-			/* Unknown : do not answer */
-			return 0;
-		}
-	}
-
-	/* respond (positively) to the request */
-	payload[0] |= VDO_SRC_RESPONDER;
-
-	return rsize;
-}
diff --git a/board/zinger/vif_override.xml b/board/zinger/vif_override.xml
deleted file mode 100644
index 32736caf64..0000000000
--- a/board/zinger/vif_override.xml
+++ /dev/null
@@ -1,3 +0,0 @@
-<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
-     Definition from the USB-IF.
--->
diff --git a/chip/host/adc_chip.h b/chip/host/adc_chip.h
deleted file mode 100644
index 8754be266e..0000000000
--- a/chip/host/adc_chip.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Host-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Place-holder data structure to define ADC channels. */
-struct adc_t {
-	int unused;
-};
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/host/build.mk b/chip/host/build.mk
deleted file mode 100644
index 6f8ea250ca..0000000000
--- a/chip/host/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# emulator specific files build
-#
-
-CORE:=host
-
-chip-y=system.o gpio.o uart.o persistence.o flash.o lpc.o reboot.o \
-	clock.o spi_controller.o trng.o
-
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
-
-dirs-y += chip/host/dcrypto
-
-chip-$(CONFIG_I2C)+= i2c.o
diff --git a/chip/host/clock.c b/chip/host/clock.c
deleted file mode 100644
index 2c3c48661e..0000000000
--- a/chip/host/clock.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock clock driver for unit test.
- */
-
-#include "clock.h"
-
-int clock_get_freq(void)
-{
-	return 16000000;
-}
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
deleted file mode 100644
index 84e254d8a0..0000000000
--- a/chip/host/config_chip.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Chip config header file */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* Memory mapping */
-#if !defined(TEST_NVMEM) && !defined(TEST_CR50_FUZZ)
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE 0x1000
-#else
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#define CONFIG_FLASH_BANK_SIZE 0x800
-#endif
-
-extern char __host_flash[CONFIG_FLASH_SIZE_BYTES];
-
-#define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash)
-#define CONFIG_FLASH_ERASE_SIZE 0x0010	     /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002	     /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
-#define CONFIG_RAM_BASE 0x0		     /* Not supported */
-#define CONFIG_RAM_SIZE                0x0 /* Not supported */
-
-#define CONFIG_FPU
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Do NOT use common panic code (designed to output information on the UART) */
-#undef CONFIG_COMMON_PANIC_OUTPUT
-/* Do NOT use common timer code which is designed for hardware counters. */
-#undef CONFIG_COMMON_TIMER
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#define I2C_PORT_COUNT 1
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/host/flash.c b/chip/host/flash.c
deleted file mode 100644
index 75212737e0..0000000000
--- a/chip/host/flash.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash module for emulator */
-
-#include <stdio.h>
-
-#include "common.h"
-#include "config_chip.h"
-#include "flash.h"
-#include "persistence.h"
-#include "util.h"
-
-/* This needs to be aligned to the erase bank size for NVCTR. */
-__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE_BYTES];
-uint8_t __host_flash_protect[PHYSICAL_BANKS];
-
-/* Override this function to make flash erase/write operation fail */
-test_mockable int flash_pre_op(void)
-{
-	return EC_SUCCESS;
-}
-
-static int flash_check_protect(int offset, int size)
-{
-	int first_bank = offset / CONFIG_FLASH_BANK_SIZE;
-	int last_bank = DIV_ROUND_UP(offset + size,
-				     CONFIG_FLASH_BANK_SIZE);
-	int bank;
-
-	for (bank = first_bank; bank < last_bank; ++bank)
-		if (__host_flash_protect[bank])
-			return 1;
-	return 0;
-}
-
-static void flash_set_persistent(void)
-{
-	FILE *f = get_persistent_storage("flash", "wb");
-	int sz;
-
-	ASSERT(f != NULL);
-
-	sz = fwrite(__host_flash, sizeof(__host_flash), 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-static void flash_get_persistent(void)
-{
-	FILE *f = get_persistent_storage("flash", "rb");
-	int sz;
-
-	if (f == NULL) {
-		fprintf(stderr,
-			"No flash storage found. Initializing to 0xff.\n");
-		memset(__host_flash, 0xff, sizeof(__host_flash));
-		return;
-	}
-
-	sz = fread(__host_flash, sizeof(__host_flash), 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	ASSERT((size & (CONFIG_FLASH_WRITE_SIZE - 1)) == 0);
-
-	if (flash_pre_op() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_check_protect(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	memcpy(__host_flash + offset, data, size);
-	flash_set_persistent();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	ASSERT((size & (CONFIG_FLASH_ERASE_SIZE - 1)) == 0);
-
-	if (flash_pre_op() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_check_protect(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	memset(__host_flash + offset, 0xff, size);
-	flash_set_persistent();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	return __host_flash_protect[bank];
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	int i;
-	uint32_t flags = EC_FLASH_PROTECT_ALL_NOW;
-
-	for (i = 0; i < PHYSICAL_BANKS; ++i)
-		if (__host_flash_protect[i] == 0)
-			flags = 0;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : WP_BANK_COUNT);
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t prot_flags;
-
-	flash_get_persistent();
-
-	prot_flags = crec_flash_get_protect();
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/host/gpio.c b/chip/host/gpio.c
deleted file mode 100644
index 3c15205ad5..0000000000
--- a/chip/host/gpio.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for emulator */
-
-#include "console.h"
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "timer.h"
-#include "util.h"
-
-static int gpio_values[GPIO_COUNT];
-static int gpio_interrupt_enabled[GPIO_COUNT];
-
-/* Create a dictionary of names for debug console print */
-#define GPIO_INT(name, pin, flags, signal) #name,
-#define GPIO(name, pin, flags) #name,
-const char * gpio_names[GPIO_COUNT] = {
-	#include "gpio.wrap"
-};
-#undef GPIO
-#undef GPIO_INT
-
-test_mockable void gpio_pre_init(void)
-{
-	/* Nothing */
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return gpio_values[signal];
-}
-
-static int gpio_interrupt_check(uint32_t flags, int old, int new)
-{
-	if ((flags & GPIO_INT_F_RISING) && old == 0 && new == 1)
-		return 1;
-	if ((flags & GPIO_INT_F_FALLING) && old == 1 && new == 0)
-		return 1;
-	if ((flags & GPIO_INT_F_LOW) && new == 0)
-		return 1;
-	if ((flags & GPIO_INT_F_HIGH) && new == 1)
-		return 1;
-	return 0;
-}
-
-test_mockable void gpio_set_level(enum gpio_signal signal, int value)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	const uint32_t flags = g->flags;
-	const int old_value = gpio_values[signal];
-	void (*ih)(enum gpio_signal signal);
-
-	gpio_values[signal] = value;
-
-	ccprints("Setting GPIO_%s to %d", gpio_names[signal], value);
-
-	if (signal >= GPIO_IH_COUNT || !gpio_interrupt_enabled[signal])
-		return;
-
-	ih = gpio_irq_handlers[signal];
-
-	if (gpio_interrupt_check(flags, old_value, value))
-		ih(signal);
-}
-
-test_mockable int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	gpio_interrupt_enabled[signal] = 1;
-	return EC_SUCCESS;
-}
-
-test_mockable int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	gpio_interrupt_enabled[signal] = 0;
-	return EC_SUCCESS;
-}
-
-test_mockable int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable void gpio_set_flags_by_mask(uint32_t port, uint32_t mask,
-					  uint32_t flags)
-{
-	/* Nothing */
-}
-
-test_mockable void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-						enum gpio_alternate_func func)
-{
-	/* Nothing */
-}
diff --git a/chip/host/host_test.h b/chip/host/host_test.h
deleted file mode 100644
index e2bf5448c3..0000000000
--- a/chip/host/host_test.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Unit testing for Chrome EC */
-
-#ifndef __CROS_EC_HOST_TEST_H
-#define __CROS_EC_HOST_TEST_H
-
-/* Emulator exit codes */
-#define EXIT_CODE_HIBERNATE BIT(7)
-
-/* Get emulator executable name */
-const char *__get_prog_name(void);
-
-#endif  /* __CROS_EC_HOST_TEST_H */
diff --git a/chip/host/i2c.c b/chip/host/i2c.c
deleted file mode 100644
index ba4ab376d2..0000000000
--- a/chip/host/i2c.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock I2C driver for unit test.
- */
-
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_private.h"
-#include "link_defs.h"
-#include "test_util.h"
-
-#define MAX_DETACHED_DEV_COUNT 3
-
-struct i2c_dev {
-	int port;
-	uint16_t addr_flags;
-	int valid;
-};
-
-static struct i2c_dev detached_devs[MAX_DETACHED_DEV_COUNT];
-
-static void detach_init(void)
-{
-	int i;
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		detached_devs[i].valid = 0;
-}
-DECLARE_HOOK(HOOK_INIT, detach_init, HOOK_PRIO_FIRST);
-
-int test_detach_i2c(const int port, const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid == 0)
-			break;
-
-	if (i == MAX_DETACHED_DEV_COUNT)
-		return EC_ERROR_OVERFLOW;
-
-	detached_devs[i].port = port;
-	detached_devs[i].addr_flags = addr_flags;
-	detached_devs[i].valid = 1;
-
-	return EC_SUCCESS;
-}
-
-int test_attach_i2c(const int port, const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].addr_flags == addr_flags)
-			break;
-
-	if (i == MAX_DETACHED_DEV_COUNT)
-		return EC_ERROR_INVAL;
-
-	detached_devs[i].valid = 0;
-	return EC_SUCCESS;
-}
-
-static int test_check_detached(const int port,
-			       const uint16_t addr_flags)
-{
-	int i;
-
-	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
-		    detached_devs[i].addr_flags == addr_flags)
-			return 1;
-	return 0;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	const struct test_i2c_xfer *p;
-	int rv;
-
-	if (test_check_detached(port, addr_flags))
-		return EC_ERROR_UNKNOWN;
-	for (p = __test_i2c_xfer; p < __test_i2c_xfer_end; ++p) {
-		rv = p->routine(port, addr_flags,
-				out, out_size,
-				in, in_size, flags);
-		if (rv != EC_ERROR_INVAL)
-			return rv;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-int chip_i2c_set_freq(int port, enum i2c_freq freq)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum i2c_freq chip_i2c_get_freq(int port)
-{
-	switch (i2c_ports[port].kbps) {
-	case 1000:
-		return I2C_FREQ_1000KHZ;
-	case 400:
-		return I2C_FREQ_400KHZ;
-	case 100:
-		return I2C_FREQ_100KHZ;
-	}
-
-	/* fallback to 100k */
-	return I2C_FREQ_100KHZ;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return 0;
-}
-
-void i2c_init(void)
-{
-	/* We don't actually need to initialize anything here for host tests */
-}
diff --git a/chip/host/keyboard_raw.c b/chip/host/keyboard_raw.c
deleted file mode 100644
index 3e1f755f7f..0000000000
--- a/chip/host/keyboard_raw.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Raw keyboard I/O layer for emulator */
-
-#include "common.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "task.h"
-#include "util.h"
-
-test_mockable void keyboard_raw_init(void)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_task_start(void)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* Nothing */
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Nothing pressed */
-	return 0;
-}
-
-test_mockable void keyboard_raw_enable_interrupt(int enable)
-{
-	/* Nothing */
-}
-
-test_mockable void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-#ifdef HAS_TASK_KEYSCAN
-	task_wake(TASK_ID_KEYSCAN);
-#endif
-}
diff --git a/chip/host/lpc.c b/chip/host/lpc.c
deleted file mode 100644
index dd64be9275..0000000000
--- a/chip/host/lpc.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC emulator */
-
-#include "lpc.h"
-
-test_mockable int lpc_keyboard_has_char(void)
-{
-	return 0;
-}
-
-test_mockable int lpc_keyboard_input_pending(void)
-{
-	return 0;
-}
-
-test_mockable void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	/* Do nothing */
-}
-
-test_mockable void lpc_keyboard_clear_buffer(void)
-{
-	/* Do nothing */
-}
-
-test_mockable void lpc_keyboard_resume_irq(void)
-{
-	/* Do nothing */
-}
diff --git a/chip/host/persistence.c b/chip/host/persistence.c
deleted file mode 100644
index 44d60f1bb8..0000000000
--- a/chip/host/persistence.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Persistence module for emulator */
-
-/* This provides storage that can be opened, closed and reopened by the
- * current process at will, whose naming even remains stable across multiple
- * invocations of the same executable, while providing a unique name for
- * each executable (as determined by path) that uses these routines.
- *
- * Useful when semi-permanent storage is required even with many
- * similar processes running in parallel (e.g. in a highly parallel
- * test suite run.
- *
- * mkstemp and friends don't provide these properties which is why we have
- * this homegrown implementation of something similar-yet-different.
- */
-
-#include <linux/limits.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "util.h"
-
-/* The longest path in a chroot seems to be about 280 characters (as of
- * April 2021) so define a cut-off instead of just hoping for the best:
- * If we were to run into a path that is nearly PATH_MAX bytes long,
- * file names could end up being reused inadvertedly because the various
- * snprintf calls would cut off the trailing characters, so the "tag" (and
- * maybe more) is gone even though it only exists for differentiation.
- *
- * Instead bail out if we encounter a path (to an executable using these
- * routines) that is longer than we expect.
- *
- * Round up for some spare room because why not?
- */
-static const int max_len = 300;
-
-/* This must be at least the size of the prefix added in get_storage_path */
-static const int max_prefix_len = 25;
-
-static void get_storage_path(char *out)
-{
-	char buf[PATH_MAX];
-	int sz;
-	char *current;
-
-	sz = readlink("/proc/self/exe", buf, PATH_MAX - 1);
-	buf[sz] = '\0';
-
-	ASSERT(sz <= max_len);
-
-	/* replace / by underscores in the path to get the shared memory name */
-	current = strchr(buf, '/');
-	while (current) {
-		*current = '_';
-		current = strchr(current, '/');
-	}
-
-
-	sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s",
-		max_len, buf);
-	out[PATH_MAX - 1] = '\0';
-
-	ASSERT(sz <= max_len + max_prefix_len);
-}
-
-FILE *get_persistent_storage(const char *tag, const char *mode)
-{
-	char buf[PATH_MAX];
-	char path[PATH_MAX];
-
-	/* There's no longer tag in use right now, and there shouldn't be. */
-	ASSERT(strlen(tag) < 32);
-
-	/*
-	 * The persistent storage with tag 'foo' for test 'bar' would
-	 * be named 'bar_persist_foo'
-	 */
-	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
-	path[PATH_MAX - 1] = '\0';
-
-	return fopen(path, mode);
-}
-
-void release_persistent_storage(FILE *ps)
-{
-	fclose(ps);
-}
-
-void remove_persistent_storage(const char *tag)
-{
-	char buf[PATH_MAX];
-	char path[PATH_MAX];
-
-	/* There's no longer tag in use right now, and there shouldn't be. */
-	ASSERT(strlen(tag) < 32);
-
-	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
-	path[PATH_MAX - 1] = '\0';
-
-	unlink(path);
-}
diff --git a/chip/host/persistence.h b/chip/host/persistence.h
deleted file mode 100644
index a473f8dfb0..0000000000
--- a/chip/host/persistence.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Persistence module for emulator */
-
-#ifndef __CROS_EC_PERSISTENCE_H
-#define __CROS_EC_PERSISTENCE_H
-
-#include <stdio.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-FILE *get_persistent_storage(const char *tag, const char *mode);
-
-void release_persistent_storage(FILE *ps);
-
-void remove_persistent_storage(const char *tag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CROS_EC_PERSISTENCE_H */
diff --git a/chip/host/reboot.c b/chip/host/reboot.c
deleted file mode 100644
index e932c5f11a..0000000000
--- a/chip/host/reboot.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator self-reboot procedure */
-
-#include <string.h>
-#include <unistd.h>
-
-#include "console.h"
-#include "host_test.h"
-#include "reboot.h"
-#include "test_util.h"
-
-#ifdef TEST_FUZZ
-/* reboot breaks fuzzing, let's just not do it. */
-void emulator_reboot(void)
-{
-	ccprints("Emulator would reboot here. Fuzzing: doing nothing.");
-}
-#else /* !TEST_FUZZ */
-noreturn
-void emulator_reboot(void)
-{
-	char *argv[] = {strdup(__get_prog_name()), NULL};
-	emulator_flush();
-	execv(__get_prog_name(), argv);
-	while (1)
-		;
-}
-#endif /* !TEST_FUZZ */
diff --git a/chip/host/reboot.h b/chip/host/reboot.h
deleted file mode 100644
index 1c1201f451..0000000000
--- a/chip/host/reboot.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator self-reboot procedure */
-
-#ifndef __CROS_EC_REBOOT_H
-#define __CROS_EC_REBOOT_H
-
-#include <stdnoreturn.h>
-
-#ifndef TEST_FUZZ
-noreturn
-#endif
-void emulator_reboot(void);
-
-#endif
diff --git a/chip/host/registers.h b/chip/host/registers.h
deleted file mode 100644
index 7347ce04d3..0000000000
--- a/chip/host/registers.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Empty registers header for emulator */
-
-/*
- * There is no register for emulator, but this file exists to prevent
- * compilation failure if any file includes registers.h
- */
diff --git a/chip/host/spi_controller.c b/chip/host/spi_controller.c
deleted file mode 100644
index c7afea5d39..0000000000
--- a/chip/host/spi_controller.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock SPI Controller driver for unit test.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "gpio.h"
-
-#include "spi.h"
-
-test_mockable int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction(const struct spi_device_t *spi_device,
-				  const uint8_t *txdata, int txlen,
-				  uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_async(const struct spi_device_t *spi_device,
-					const uint8_t *txdata, int txlen,
-					uint8_t *rxdata, int rxlen)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
-
-test_mockable int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return EC_SUCCESS;
-}
diff --git a/chip/host/system.c b/chip/host/system.c
deleted file mode 100644
index 60d765deab..0000000000
--- a/chip/host/system.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for emulator */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "host_test.h"
-#include "panic.h"
-#include "persistence.h"
-#include "reboot.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-// Forward declaration from <stdlib.h> to avoid declaration conflicts.
-void exit(int);
-
-#define SHARED_MEM_SIZE 0x2000 /* bytes */
-#define RAM_DATA_SIZE (sizeof(struct panic_data) + 512) /* bytes */
-uint8_t __shared_mem_buf[SHARED_MEM_SIZE + RAM_DATA_SIZE];
-
-static char *__ram_data = __shared_mem_buf + SHARED_MEM_SIZE;
-
-static enum ec_image __running_copy;
-
-static void ramdata_set_persistent(void)
-{
-	FILE *f = get_persistent_storage("ramdata", "wb");
-	int sz;
-
-	ASSERT(f != NULL);
-
-	sz = fwrite(__ram_data, RAM_DATA_SIZE, 1, f);
-	ASSERT(sz == 1);
-
-	release_persistent_storage(f);
-}
-
-static void ramdata_get_persistent(void)
-{
-	FILE *f = get_persistent_storage("ramdata", "rb");
-
-	if ((f == NULL) || (fread(__ram_data, RAM_DATA_SIZE, 1, f) != 1)) {
-		fprintf(stderr,
-			"No RAM data found. Initializing to 0x00.\n");
-		memset(__ram_data, 0, RAM_DATA_SIZE);
-		return;
-	}
-
-	release_persistent_storage(f);
-
-	/*
-	 * Assumes RAM data doesn't preserve across reboot except for sysjump.
-	 * Clear persistent data once it's read.
-	 */
-	remove_persistent_storage("ramdata");
-}
-
-static void set_image_copy(uint32_t copy)
-{
-	FILE *f = get_persistent_storage("image_copy", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&copy, sizeof(copy), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static uint32_t get_image_copy(void)
-{
-	FILE *f = get_persistent_storage("image_copy", "rb");
-	uint32_t ret;
-
-	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
-		return EC_IMAGE_UNKNOWN;
-	release_persistent_storage(f);
-	remove_persistent_storage("image_copy");
-
-	return ret;
-}
-
-static void save_reset_flags(uint32_t flags)
-{
-	FILE *f = get_persistent_storage("reset_flags", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&flags, sizeof(flags), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static uint32_t load_reset_flags(void)
-{
-	FILE *f = get_persistent_storage("reset_flags", "rb");
-	uint32_t ret;
-
-	if ((f == NULL) || (fread(&ret, sizeof(ret), 1, f) != 1))
-		return EC_RESET_FLAG_POWER_ON;
-	release_persistent_storage(f);
-	remove_persistent_storage("reset_flags");
-
-	return ret;
-}
-
-static void save_time(timestamp_t t)
-{
-	FILE *f = get_persistent_storage("time", "wb");
-
-	ASSERT(f != NULL);
-	ASSERT(fwrite(&t, sizeof(t), 1, f) == 1);
-
-	release_persistent_storage(f);
-}
-
-static int load_time(timestamp_t *t)
-{
-	FILE *f = get_persistent_storage("time", "rb");
-
-	if ((f == NULL) || (fread(t, sizeof(*t), 1, f) != 1))
-		return 0;
-	release_persistent_storage(f);
-	remove_persistent_storage("time");
-
-	return 1;
-}
-
-test_mockable struct panic_data *panic_get_data(void)
-{
-	return (struct panic_data *)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
-}
-
-test_mockable uintptr_t get_panic_data_start()
-{
-	return (uintptr_t)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
-}
-
-test_mockable void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	if (save_flags)
-		save_reset_flags(save_flags);
-	emulator_reboot();
-}
-
-test_mockable void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	uint32_t i;
-
-	if (board_hibernate)
-		board_hibernate();
-
-	save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-
-	if (!seconds && !microseconds)
-		exit(EXIT_CODE_HIBERNATE);
-
-	for (i = 0; i < seconds; ++i)
-		udelay(SECOND);
-	udelay(microseconds);
-	emulator_reboot();
-}
-
-test_mockable int system_is_locked(void)
-{
-	return 0;
-}
-
-#ifdef TEST_FUZZ
-/* When fuzzing, do not allow sysjumps. */
-int system_run_image_copy(enum ec_image copy)
-{
-	ccprints("Emulator would sysjump here. Fuzzing: doing nothing.");
-	return EC_ERROR_UNKNOWN;
-}
-#endif
-
-const char *system_get_chip_vendor(void)
-{
-	return "chromeos";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "emu";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return __running_copy;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	FILE *f = get_persistent_storage("scratchpad", "w");
-
-	fprintf(f, "%u", value);
-	release_persistent_storage(f);
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	FILE *f = get_persistent_storage("scratchpad", "r");
-	int success;
-
-	if (f == NULL)
-		return EC_ERROR_UNKNOWN;
-
-	success = fscanf(f, "%u", value);
-	release_persistent_storage(f);
-
-	if (success)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-static void __jump_resetvec(void)
-{
-	save_time(get_time());
-	ramdata_set_persistent();
-	emulator_reboot();
-}
-
-static void __ro_jump_resetvec(void)
-{
-	set_image_copy(EC_IMAGE_RO);
-	__jump_resetvec();
-}
-
-static void __rw_jump_resetvec(void)
-{
-	set_image_copy(EC_IMAGE_RW);
-	__jump_resetvec();
-}
-
-void system_pre_init(void)
-{
-	timestamp_t t;
-
-	if (load_time(&t))
-		force_time(t);
-
-	ramdata_get_persistent();
-	__running_copy = get_image_copy();
-	if (__running_copy == EC_IMAGE_UNKNOWN) {
-		__running_copy = EC_IMAGE_RO;
-		system_set_reset_flags(load_reset_flags());
-	}
-
-	*(uintptr_t *)(__host_flash + CONFIG_RO_MEM_OFF + 4) =
-		(uintptr_t)__ro_jump_resetvec;
-	*(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) =
-		(uintptr_t)__rw_jump_resetvec;
-}
diff --git a/chip/host/trng.c b/chip/host/trng.c
deleted file mode 100644
index 8407aa6ea1..0000000000
--- a/chip/host/trng.c
+++ /dev/null
@@ -1,40 +0,0 @@
-
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock TRNG driver for unit test.
- *
- * Although a TRNG is designed to be anything but predictable,
- * this implementation strives to be as predictable and defined
- * as possible to allow reproducing unit tests and fuzzer crashes.
- */
-
-#ifndef TEST_BUILD
-#error "This fake trng driver must not be used in non-test builds."
-#endif
-
-#include <stdint.h>
-#include <stdlib.h> /* Only valid for host */
-
-#include "common.h"
-
-static unsigned int seed;
-
-test_mockable void init_trng(void)
-{
-	seed = 0;
-	srand(seed);
-}
-
-test_mockable void exit_trng(void)
-{
-}
-
-test_mockable void rand_bytes(void *buffer, size_t len)
-{
-	uint8_t *b, *end;
-
-	for (b = buffer, end = b+len; b != end; b++)
-		*b = (uint8_t)rand_r(&seed);
-}
diff --git a/chip/host/uart.c b/chip/host/uart.c
deleted file mode 100644
index 578924612f..0000000000
--- a/chip/host/uart.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART driver for emulator */
-
-#include <pthread.h>
-#include <signal.h>
-#include <stdio.h>
-#include <termio.h>
-#include <unistd.h>
-
-#include "common.h"
-#include "queue.h"
-#include "task.h"
-#include "test_util.h"
-#include "uart.h"
-#include "util.h"
-
-static int stopped = 1;
-static int init_done;
-
-#ifndef TEST_FUZZ
-static pthread_t input_thread;
-#endif
-
-#define INPUT_BUFFER_SIZE 16
-static int char_available;
-
-static struct queue const cached_char = QUEUE_NULL(INPUT_BUFFER_SIZE, char);
-
-#define CONSOLE_CAPTURE_SIZE 2048
-static char capture_buf[CONSOLE_CAPTURE_SIZE];
-static int capture_size;
-static int capture_enabled;
-
-void test_capture_console(int enabled)
-{
-	if (enabled == capture_enabled)
-		return;
-
-	if (enabled)
-		capture_size = 0;
-	else
-		capture_buf[capture_size] = '\0';
-
-	capture_enabled = enabled;
-}
-
-static void test_capture_char(char c)
-{
-	if (capture_size == CONSOLE_CAPTURE_SIZE)
-		return;
-	capture_buf[capture_size++] = c;
-}
-
-
-const char *test_get_captured_console(void)
-{
-	return (const char *)capture_buf;
-}
-
-static void uart_interrupt(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	stopped = 0;
-	task_trigger_test_interrupt(uart_interrupt);
-}
-
-void uart_tx_stop(void)
-{
-	stopped = 1;
-}
-
-int uart_tx_stopped(void)
-{
-	return stopped;
-}
-
-void uart_tx_flush(void)
-{
-	/* Nothing */
-}
-
-int uart_tx_ready(void)
-{
-	return 1;
-}
-
-int uart_rx_available(void)
-{
-	return char_available;
-}
-
-void uart_write_char(char c)
-{
-	if (capture_enabled)
-		test_capture_char(c);
-	printf("%c", c);
-	fflush(stdout);
-}
-
-int uart_read_char(void)
-{
-	char ret;
-	ASSERT(in_interrupt_context());
-	queue_remove_unit(&cached_char, &ret);
-	--char_available;
-	return ret;
-}
-
-void uart_inject_char(char *s, int sz)
-{
-	int i;
-	int num_char;
-
-	for (i = 0; i < sz; i += INPUT_BUFFER_SIZE - 1) {
-		num_char = MIN(INPUT_BUFFER_SIZE - 1, sz - i);
-		if (queue_space(&cached_char) < num_char)
-			return;
-		queue_add_units(&cached_char, s + i, num_char);
-		char_available = num_char;
-		task_trigger_test_interrupt(uart_interrupt);
-	}
-}
-
-/*
- * We do not really need console input when fuzzing, and having it enabled
- * breaks terminal when an error is detected.
- */
-#ifndef TEST_FUZZ
-static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
-static pthread_cond_t uart_monitor_initialized = PTHREAD_COND_INITIALIZER;
-
-void *uart_monitor_stdin(void *d)
-{
-	struct termios org_settings, new_settings;
-	char buf[INPUT_BUFFER_SIZE];
-	int rv;
-
-	pthread_mutex_lock(&mutex);
-	tcgetattr(0, &org_settings);
-	new_settings = org_settings;
-	new_settings.c_lflag &= ~(ECHO | ICANON);
-	new_settings.c_cc[VTIME] = 0;
-	new_settings.c_cc[VMIN] = 1;
-
-	printf("Console input initialized\n");
-	/* Allow uart_init to proceed now that UART monitor is initialized. */
-	pthread_cond_signal(&uart_monitor_initialized);
-	pthread_mutex_unlock(&mutex);
-	while (1) {
-		tcsetattr(0, TCSANOW, &new_settings);
-		rv = read(0, buf, INPUT_BUFFER_SIZE);
-		if (queue_space(&cached_char) >= rv) {
-			queue_add_units(&cached_char, buf, rv);
-			char_available = rv;
-		}
-		tcsetattr(0, TCSANOW, &org_settings);
-		/*
-		 * Trigger emulated interrupt to process input. Keyboard
-		 * input while interrupt handler runs is queued by the
-		 * system.
-		 */
-		task_trigger_test_interrupt(uart_interrupt);
-	}
-
-	return 0;
-}
-#endif /* !TEST_FUZZ */
-
-void uart_init(void)
-{
-#ifndef TEST_FUZZ
-	/* Create UART monitor thread and wait for it to initialize. */
-	pthread_mutex_lock(&mutex);
-	pthread_create(&input_thread, NULL, uart_monitor_stdin, NULL);
-	pthread_cond_wait(&uart_monitor_initialized, &mutex);
-	pthread_mutex_unlock(&mutex);
-#endif
-
-	stopped = 1;  /* Not transmitting yet */
-	init_done = 1;
-}
diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c
deleted file mode 100644
index ba81b986ad..0000000000
--- a/chip/host/usb_pd_phy.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "util.h"
-
-#define PREAMBLE_OFFSET 60 /* Any number should do */
-
-/*
- * Maximum size of a Power Delivery packet (in bits on the wire) :
- *    16-bit header + 0..7 32-bit data objects  (+ 4b5b encoding)
- * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b)
- * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5
- */
-#define PD_BIT_LEN 429
-
-static struct pd_physical {
-	int hw_init_done;
-
-	uint8_t bits[PD_BIT_LEN];
-	int total;
-	int has_preamble;
-	int rx_started;
-	int rx_monitoring;
-
-	int preamble_written;
-	int has_msg;
-	int last_edge_written;
-	uint8_t out_msg[PD_BIT_LEN / 5];
-	int verified_idx;
-} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static const uint16_t enc4b5b[] = {
-	0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16,
-	0x17, 0x1A, 0x1B, 0x1C, 0x1D};
-
-/* Test utilities */
-static void pd_test_reset_phy(int port)
-{
-	int i;
-	int enc_len = PD_BIT_LEN / 5;
-
-	for (i = 0; i < PD_BIT_LEN; i++)
-		pd_phy[port].bits[i] = 0;
-
-	for (i = 0; i < enc_len; i++)
-		pd_phy[port].out_msg[i] = 0;
-
-	pd_phy[port].total = 0;
-	pd_phy[port].has_preamble = 0;
-	pd_phy[port].rx_started = 0;
-	pd_phy[port].rx_monitoring = 0;
-	pd_phy[port].preamble_written = 0;
-	pd_phy[port].has_msg = 0;
-	pd_phy[port].last_edge_written = 0;
-	pd_phy[port].verified_idx = 0;
-}
-
-void pd_test_rx_set_preamble(int port, int has_preamble)
-{
-	pd_phy[port].total = 0;
-	pd_phy[port].has_preamble = has_preamble;
-}
-
-void pd_test_rx_msg_append_bits(int port, uint32_t bits, int nb)
-{
-	int i;
-
-	for (i = 0; i < nb; ++i) {
-		pd_phy[port].bits[pd_phy[port].total++] = bits & 1;
-		bits >>= 1;
-	}
-}
-
-void pd_test_rx_msg_append_kcode(int port, uint8_t kcode)
-{
-	pd_test_rx_msg_append_bits(port, kcode, 5);
-}
-
-void pd_test_rx_msg_append_sop(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC2);
-}
-
-void pd_test_rx_msg_append_sop_prime(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-}
-
-void pd_test_rx_msg_append_sop_prime_prime(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC1);
-	pd_test_rx_msg_append_kcode(port, PD_SYNC3);
-}
-
-void pd_test_rx_msg_append_eop(int port)
-{
-	pd_test_rx_msg_append_kcode(port, PD_EOP);
-}
-
-void pd_test_rx_msg_append_last_edge(int port)
-{
-	/* end with 1, 1, 0 similar to pd_write_last_edge() */
-	pd_test_rx_msg_append_bits(port, 3, 6);
-}
-
-void pd_test_rx_msg_append_4b(int port, uint8_t val)
-{
-	pd_test_rx_msg_append_bits(port, enc4b5b[val & 0xF], 5);
-}
-
-void pd_test_rx_msg_append_short(int port, uint16_t val)
-{
-	pd_test_rx_msg_append_4b(port, (val >> 0) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 4) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 8) & 0xF);
-	pd_test_rx_msg_append_4b(port, (val >> 12) & 0xF);
-}
-
-void pd_test_rx_msg_append_word(int port, uint32_t val)
-{
-	pd_test_rx_msg_append_short(port, val & 0xFFFF);
-	pd_test_rx_msg_append_short(port, val >> 16);
-}
-
-void pd_simulate_rx(int port)
-{
-	if (!pd_phy[port].rx_monitoring)
-		return;
-
-	pd_phy[port].rx_started = 1;
-	pd_rx_disable_monitoring(port);
-	pd_rx_event(port);
-}
-
-static int pd_test_tx_msg_verify(int port, uint8_t raw)
-{
-	int verified_idx = pd_phy[port].verified_idx++;
-	return pd_phy[port].out_msg[verified_idx] == raw;
-}
-
-int pd_test_tx_msg_verify_kcode(int port, uint8_t kcode)
-{
-	return pd_test_tx_msg_verify(port, kcode);
-}
-
-int pd_test_tx_msg_verify_sop(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC2);
-}
-
-int pd_test_tx_msg_verify_sop_prime(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3);
-}
-
-int pd_test_tx_msg_verify_sop_prime_prime(int port)
-{
-	crc32_init();
-	return pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC1) &&
-	       pd_test_tx_msg_verify_kcode(port, PD_SYNC3);
-}
-
-int pd_test_tx_msg_verify_eop(int port)
-{
-	return pd_test_tx_msg_verify_kcode(port, PD_EOP);
-}
-
-int pd_test_tx_msg_verify_4b5b(int port, uint8_t b4)
-{
-	return pd_test_tx_msg_verify(port, enc4b5b[b4]);
-}
-
-int pd_test_tx_msg_verify_short(int port, uint16_t val)
-{
-	crc32_hash16(val);
-	return pd_test_tx_msg_verify_4b5b(port, (val >> 0) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 4) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 8) & 0xF) &&
-	       pd_test_tx_msg_verify_4b5b(port, (val >> 12) & 0xF);
-}
-
-int pd_test_tx_msg_verify_word(int port, uint32_t val)
-{
-	return pd_test_tx_msg_verify_short(port, val & 0xFFFF) &&
-	       pd_test_tx_msg_verify_short(port, val >> 16);
-}
-
-int pd_test_tx_msg_verify_crc(int port)
-{
-	return pd_test_tx_msg_verify_word(port, crc32_result());
-}
-
-
-/* Mock functions */
-
-void pd_init_dequeue(int port)
-{
-}
-
-int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
-{
-	int i;
-
-	/* Rx must have started to receive message */
-	ASSERT(pd_phy[port].rx_started);
-
-	if (pd_phy[port].total <= off + len - PREAMBLE_OFFSET)
-		return -1;
-	*val = 0;
-	for (i = 0; i < len; ++i)
-		*val |= pd_phy[port].bits[off + i - PREAMBLE_OFFSET] << i;
-	return off + len;
-}
-
-int pd_find_preamble(int port)
-{
-	return pd_phy[port].has_preamble ? PREAMBLE_OFFSET : -1;
-}
-
-int pd_write_preamble(int port)
-{
-	ASSERT(pd_phy[port].preamble_written == 0);
-	pd_phy[port].preamble_written = 1;
-	ASSERT(pd_phy[port].has_msg == 0);
-	return 0;
-}
-
-static uint8_t decode_bmc(uint32_t val10)
-{
-	uint8_t ret = 0;
-	int i;
-
-	for (i = 0; i < 5; ++i)
-		if (!!(val10 & (1 << (2 * i))) !=
-		    !!(val10 & (1 << (2 * i + 1))))
-			ret |= BIT(i);
-	return ret;
-}
-
-int pd_write_sym(int port, int bit_off, uint32_t val10)
-{
-	pd_phy[port].out_msg[bit_off] = decode_bmc(val10);
-	pd_phy[port].has_msg = 1;
-	return bit_off + 1;
-}
-
-int pd_write_last_edge(int port, int bit_off)
-{
-	pd_phy[port].last_edge_written = 1;
-	return bit_off;
-}
-
-void pd_dump_packet(int port, const char *msg)
-{
-	/* Not implemented */
-}
-
-void pd_tx_set_circular_mode(int port)
-{
-	/* Not implemented */
-}
-
-void pd_tx_clear_circular_mode(int port)
-{
-	/* Not implemented */
-}
-
-int pd_start_tx(int port, int polarity, int bit_len)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_phy[port].has_msg = 0;
-	pd_phy[port].preamble_written = 0;
-	pd_phy[port].verified_idx = 0;
-	pd_phy[port].total = 0;
-
-	/*
-	 * Hand over to test runner. The test runner must wake us after
-	 * processing the packet.
-	 */
-	task_wake(TASK_ID_TEST_RUNNER);
-	task_wait_event(-1);
-
-	return bit_len;
-}
-
-void pd_tx_done(int port, int polarity)
-{
-	pd_test_reset_phy(port);
-}
-
-void pd_rx_start(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-
-	task_wake(TASK_ID_TEST_RUNNER);
-	task_wait_event(-1);
-
-	pd_phy[port].rx_started = 1;
-}
-
-void pd_rx_complete(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_test_reset_phy(port);
-}
-
-int pd_rx_started(int port)
-{
-	return pd_phy[port].rx_started;
-}
-
-void pd_rx_enable_monitoring(int port)
-{
-	ASSERT(pd_phy[port].hw_init_done);
-	pd_phy[port].rx_monitoring = 1;
-}
-
-void pd_rx_disable_monitoring(int port)
-{
-	/*
-	 * We disabled RX monitoring in TCPMv1 in set_state when
-	 * transitioning from suspended to disconnected, but we only
-	 * reinitialize after we have fully transitioned to disconnected. Don't
-	 * assert that hw_init_done here since we have "valid" code that
-	 * requires hw_init_done to be false when a port is suspended.
-	 */
-	pd_phy[port].rx_monitoring = 0;
-}
-
-void pd_hw_release(int port)
-{
-	pd_phy[port].hw_init_done = 0;
-}
-
-void pd_hw_init(int port, enum pd_power_role role)
-{
-	pd_config_init(port, role);
-	pd_phy[port].hw_init_done = 1;
-}
-
-void pd_set_clock(int port, int freq)
-{
-	/* Not implemented */
-}
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c
deleted file mode 100644
index 2839da5af2..0000000000
--- a/chip/it83xx/adc.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx ADC module for Chrome EC */
-
-#include "adc.h"
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/* Global variables */
-static struct mutex adc_lock;
-static int adc_init_done;
-static volatile task_id_t task_waiting;
-
-/* Data structure of ADC channel control registers. */
-const struct adc_ctrl_t adc_ctrl_regs[] = {
-	{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL},
-	{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL},
-	{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL},
-	{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL},
-	{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL},
-	{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL},
-	{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL},
-	{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL},
-	{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL},
-	{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL},
-	{&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL},
-	{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT);
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-#define VCMP_ADC_CH_MASK_H           BIT(3)
-#define VCMP_ADC_CH_MASK_L           0x7
-/* 10-bits resolution */
-#define VCMP_RESOLUTION              BIT(10)
-#define VCMP_MAX_MVOLT               3000
-
-/* Data structure of voltage comparator control registers. */
-const struct vcmp_ctrl_t vcmp_ctrl_regs[] = {
-	{&IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
-		&IT83XX_ADC_CMP0THRDATL},
-	{&IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
-		&IT83XX_ADC_CMP1THRDATL},
-	{&IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
-		&IT83XX_ADC_CMP2THRDATL},
-	{&IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
-		&IT83XX_ADC_CMP3THRDATL},
-	{&IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
-		&IT83XX_ADC_CMP4THRDATL},
-	{&IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
-		&IT83XX_ADC_CMP5THRDATL},
-};
-BUILD_ASSERT(ARRAY_SIZE(vcmp_ctrl_regs) == CHIP_VCMP_COUNT);
-#endif
-
-static void adc_enable_channel(int ch)
-{
-	if (ch < CHIP_ADC_CH4)
-		/*
-		 * for channel 0, 1, 2, and 3
-		 * bit4 ~ bit0 : indicates voltage channel[x]
-		 *               input is selected for measurement (enable)
-		 * bit5 : data valid interrupt of adc.
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0xa0 + ch;
-	else
-		/*
-		 * for channel 4 ~ 7 and 13 ~ 16.
-		 * bit4 : voltage channel enable (ch 4~7 and 13 ~ 16)
-		 * bit5 : data valid interrupt of adc.
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0xb0;
-
-	task_clear_pending_irq(IT83XX_IRQ_ADC);
-	task_enable_irq(IT83XX_IRQ_ADC);
-
-	/* bit 0 : adc module enable */
-	IT83XX_ADC_ADCCFG |= 0x01;
-}
-
-static void adc_disable_channel(int ch)
-{
-	if (ch < CHIP_ADC_CH4)
-		/*
-		 * for channel 0, 1, 2, and 3
-		 * bit4 ~ bit0 : indicates voltage channel[x]
-		 *               input is selected for measurement (disable)
-		 * bit 7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0x9F;
-	else
-		/*
-		 * for channel 4 ~ 7 and 13 ~ 16.
-		 * bit4 : voltage channel disable (ch 4~7 and 13 ~ 16)
-		 * bit7 : W/C data valid flag
-		 */
-		*adc_ctrl_regs[ch].adc_ctrl = 0x80;
-
-	/* bit 0 : adc module disable */
-	IT83XX_ADC_ADCCFG &= ~0x01;
-
-	task_disable_irq(IT83XX_IRQ_ADC);
-}
-
-static int adc_data_valid(enum chip_adc_channel adc_ch)
-{
-	return (adc_ch <= CHIP_ADC_CH7) ?
-		(IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
-		(IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	uint32_t events;
-	/* voltage 0 ~ 3v = adc data register raw data 0 ~ 3FFh (10-bit ) */
-	uint16_t adc_raw_data;
-	int valid = 0;
-	int adc_ch, mv;
-
-	if (!adc_init_done)
-		return ADC_READ_ERROR;
-
-	mutex_lock(&adc_lock);
-
-	disable_sleep(SLEEP_MASK_ADC);
-	task_waiting = task_get_current();
-	adc_ch = adc_channels[ch].channel;
-	adc_enable_channel(adc_ch);
-	/* Wait for interrupt */
-	events = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
-	task_waiting = TASK_ID_INVALID;
-	/*
-	 * Ensure EC won't post the adc done event which is set after getting
-	 * events (events |= __wait_evt() in task_wait_event_mask()) to next
-	 * adc read.
-	 * NOTE: clear TASK_EVENT_ADC_DONE event must happen after setting
-	 * task_waiting to invalid. So TASK_EVENT_ADC_DONE would not set until
-	 * next read.
-	 */
-	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-		TASK_EVENT_ADC_DONE);
-
-	/* data valid of adc channel[x] */
-	if (adc_data_valid(adc_ch)) {
-		/* read adc raw data msb and lsb */
-		adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
-			*adc_ctrl_regs[adc_ch].adc_datl;
-
-		/* W/C data valid flag */
-		if (adc_ch <= CHIP_ADC_CH7)
-			IT83XX_ADC_ADCDVSTS = BIT(adc_ch);
-		else
-			IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13));
-
-		mv = adc_raw_data * adc_channels[ch].factor_mul /
-			adc_channels[ch].factor_div + adc_channels[ch].shift;
-		valid = 1;
-	}
-
-	if (!valid) {
-		CPRINTS("ADC failed to read!!! (regs=%x, %x, ch=%d, evt=%x)",
-			IT83XX_ADC_ADCDVSTS,
-			IT83XX_ADC_ADCDVSTS2,
-			adc_ch, events);
-	}
-
-	adc_disable_channel(adc_ch);
-	enable_sleep(SLEEP_MASK_ADC);
-
-	mutex_unlock(&adc_lock);
-
-	return valid ? mv : ADC_READ_ERROR;
-}
-
-void adc_interrupt(void)
-{
-	/*
-	 * Clear the interrupt status.
-	 *
-	 * NOTE:
-	 * The ADC interrupt pending flag won't be cleared unless
-	 * we W/C data valid flag of ADC module as well.
-	 * (If interrupt type setting is high-level triggered)
-	 */
-	task_clear_pending_irq(IT83XX_IRQ_ADC);
-	/*
-	 * We disable ADC interrupt here, because current setting of
-	 * interrupt type is high-level triggered.
-	 * The interrupt will be triggered again and again until
-	 * we W/C data valid flag if we don't disable it.
-	 */
-	task_disable_irq(IT83XX_IRQ_ADC);
-	/* Wake up the task which was waiting for the interrupt */
-	if (task_waiting != TASK_ID_INVALID)
-		task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
-}
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-/* Clear voltage comparator interrupt status */
-void clear_vcmp_status(int vcmp_x)
-{
-	if (vcmp_x <= CHIP_VCMP2)
-		IT83XX_ADC_VCMPSTS = BIT(vcmp_x);
-	else
-		IT83XX_ADC_VCMPSTS2 = BIT(vcmp_x - CHIP_VCMP3);
-}
-
-/* Enable/Disable voltage comparator interrupt */
-void vcmp_enable(int idx, int enable)
-{
-	if (enable) {
-		/* Enable comparator interrupt */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_CMPINTEN;
-		/* Start voltage comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_CMPEN;
-	} else {
-		/* Stop voltage comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_CMPEN;
-		/* Disable comparator interrupt */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_CMPINTEN;
-	}
-}
-
-/* Set voltage comparator conditions */
-void set_voltage_comparator_condition(int idx)
-{
-	int val;
-
-	/* CMPXTHRDAT[9:0] = threshold(mv) * 1024 / 3000(mv) */
-	val = vcmp_list[idx].threshold * VCMP_RESOLUTION / VCMP_MAX_MVOLT;
-	*vcmp_ctrl_regs[idx].vcmp_datl = (uint8_t)(val & 0xff);
-	*vcmp_ctrl_regs[idx].vcmp_datm = (uint8_t)((val >> 8) & 0xff);
-
-	/* Select greater or less equal than threshold */
-	if (vcmp_list[idx].flag & GREATER_THRESHOLD)
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |= ADC_VCMP_GREATER_THRESHOLD;
-	else
-		*vcmp_ctrl_regs[idx].vcmp_ctrl &= ~ADC_VCMP_GREATER_THRESHOLD;
-}
-
-/* Voltage comparator interrupt, handle one channel at a time. */
-void voltage_comparator_interrupt(void)
-{
-	int idx, status;
-
-	/* Find out which voltage comparator triggered */
-	status = IT83XX_ADC_VCMPSTS & 0x07;
-	status |= (IT83XX_ADC_VCMPSTS2 & 0x07) << 3;
-
-	for (idx = CHIP_VCMP0; idx < VCMP_COUNT; idx++) {
-		if (status & BIT(idx)) {
-			/* Called back to board-level function */
-			if (vcmp_list[idx].vcmp_thresh_cb)
-				vcmp_list[idx].vcmp_thresh_cb();
-			/* Clear voltage comparator interrupt status */
-			clear_vcmp_status(idx);
-		}
-	}
-
-	/* Clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_V_COMP);
-}
-
-/* Voltage comparator initialization */
-static void voltage_comparator_init(void)
-{
-	int idx;
-
-	/* No voltage comparator is declared */
-	if (!VCMP_COUNT)
-		return;
-
-	for (idx = CHIP_VCMP0; idx < VCMP_COUNT; idx++) {
-		/*
-		 * Select voltage comparator:
-		 * vcmp_list[i] use voltage comparator i, i = 0 ~ 5.
-		 */
-
-		/* Select which ADC channel output voltage into comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |=
-			vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_L;
-		if (vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_H)
-			*vcmp_ctrl_regs[idx].vcmp_adc_chm |= ADC_VCMP_VCMPCSELM;
-
-		/* Set "all voltage comparator" scan period */
-		IT83XX_ADC_VCMPSCP = vcmp_list[idx].scan_period;
-		/* Set voltage comparator conditions */
-		set_voltage_comparator_condition(idx);
-		/* Clear voltage comparator interrupt status */
-		clear_vcmp_status(idx);
-		/* Enable comparator interrupt and start */
-		vcmp_enable(idx, 1);
-	}
-
-	/* Clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_V_COMP);
-	/* Enable voltage comparator to interrupt MCU */
-	task_enable_irq(IT83XX_IRQ_V_COMP);
-}
-#endif
-
-/*
- * ADC analog accuracy initialization (only once after VSTBY power on)
- *
- * Write 1 to this bit and write 0 to this bit immediately once and
- * only once during the firmware initialization and do not write 1 again
- * after initialization since IT83xx takes much power consumption
- * if this bit is set as 1
- */
-static void adc_accuracy_initialization(void)
-{
-	/* bit3 : start adc accuracy initialization */
-	IT83XX_ADC_ADCSTS |= 0x08;
-	/* Enable automatic HW calibration. */
-	IT83XX_ADC_KDCTL |= IT83XX_ADC_AHCE;
-	/* short delay for adc accuracy initialization */
-	IT83XX_GCTRL_WNCKR = 0;
-	/* bit3 : stop adc accuracy initialization */
-	IT83XX_ADC_ADCSTS &= ~0x08;
-}
-
-/* ADC module Initialization */
-static void adc_init(void)
-{
-	/* ADC analog accuracy initialization */
-	adc_accuracy_initialization();
-
-	/* Enable alternate function */
-	gpio_config_module(MODULE_ADC, 1);
-	/*
-	 * bit7@ADCSTS     : ADCCTS1 = 0
-	 * bit5@ADCCFG     : ADCCTS0 = 0
-	 * bit[5-0]@ADCCTL : SCLKDIV
-	 * The ADC channel conversion time is 30.8*(SCLKDIV+1) us.
-	 * (Current setting is 61.6us)
-	 *
-	 * NOTE: A sample time delay (60us) also need to be included in
-	 * conversion time, so the final result is ~= 121.6us.
-	 */
-	IT83XX_ADC_ADCSTS &= ~BIT(7);
-	IT83XX_ADC_ADCCFG &= ~BIT(5);
-	IT83XX_ADC_ADCCTL = 1;
-	/*
-	 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
-	 * kept until data valid is cleared.
-	 */
-	IT83XX_ADC_ADCGCR |= IT83XX_ADC_DBKEN;
-
-	task_waiting = TASK_ID_INVALID;
-	/* disable adc interrupt */
-	task_disable_irq(IT83XX_IRQ_ADC);
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-	/*
-	 * Init voltage comparator
-	 * NOTE:ADC channel signal output to voltage comparator,
-	 *      so we need set the channel to ADC alternate mode first.
-	 */
-	voltage_comparator_init();
-#endif
-
-	adc_init_done = 1;
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h
deleted file mode 100644
index 15a8e68e94..0000000000
--- a/chip/it83xx/adc_chip.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include <stdint.h>
-
-#include "common.h"
-
-/*
- * Maximum time we allow for an ADC conversion.
- * NOTE:
- * Because this setting greater than "SLEEP_SET_HTIMER_DELAY_USEC" in clock.c,
- * so we enabled sleep mask to prevent going in to deep sleep while ADC
- * converting.
- */
-#define ADC_TIMEOUT_US MSEC
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-#define ADC_MAX_MVOLT 3000
-
-/* List of ADC channels. */
-enum chip_adc_channel {
-	CHIP_ADC_CH0 = 0,
-	CHIP_ADC_CH1,
-	CHIP_ADC_CH2,
-	CHIP_ADC_CH3,
-	CHIP_ADC_CH4,
-	CHIP_ADC_CH5,
-	CHIP_ADC_CH6,
-	CHIP_ADC_CH7,
-	CHIP_ADC_CH13,
-	CHIP_ADC_CH14,
-	CHIP_ADC_CH15,
-	CHIP_ADC_CH16,
-	CHIP_ADC_COUNT,
-};
-
-/* List of voltage comparator. */
-enum chip_vcmp {
-	CHIP_VCMP0 = 0,
-	CHIP_VCMP1,
-	CHIP_VCMP2,
-	CHIP_VCMP3,
-	CHIP_VCMP4,
-	CHIP_VCMP5,
-	CHIP_VCMP_COUNT,
-};
-
-/* List of voltage comparator scan period times. */
-enum vcmp_scan_period {
-	VCMP_SCAN_PERIOD_100US = 0x10,
-	VCMP_SCAN_PERIOD_200US = 0x20,
-	VCMP_SCAN_PERIOD_400US = 0x30,
-	VCMP_SCAN_PERIOD_600US = 0x40,
-	VCMP_SCAN_PERIOD_800US = 0x50,
-	VCMP_SCAN_PERIOD_1MS   = 0x60,
-	VCMP_SCAN_PERIOD_1_5MS = 0x70,
-	VCMP_SCAN_PERIOD_2MS   = 0x80,
-	VCMP_SCAN_PERIOD_2_5MS = 0x90,
-	VCMP_SCAN_PERIOD_3MS   = 0xA0,
-	VCMP_SCAN_PERIOD_4MS   = 0xB0,
-	VCMP_SCAN_PERIOD_5MS   = 0xC0,
-};
-
-/* Data structure to define ADC channel control registers. */
-struct adc_ctrl_t {
-	volatile uint8_t *adc_ctrl;
-	volatile uint8_t *adc_datm;
-	volatile uint8_t *adc_datl;
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	enum chip_adc_channel channel;
-};
-
-/* Data structure to define voltage comparator control registers. */
-struct vcmp_ctrl_t {
-	volatile uint8_t *vcmp_ctrl;
-	volatile uint8_t *vcmp_adc_chm;
-	volatile uint8_t *vcmp_datm;
-	volatile uint8_t *vcmp_datl;
-};
-
-/* supported flags (member "flag" in struct vcmp_t) for voltage comparator */
-#define GREATER_THRESHOLD         BIT(0)
-#define LESS_EQUAL_THRESHOLD      BIT(1)
-
-/* Data structure for board to define voltage comparator list. */
-struct vcmp_t {
-	const char *name;
-	int threshold;
-	/*
-	 * Select greater/less equal threshold.
-	 * NOTE: once edge trigger interrupt fires, we need disable the voltage
-	 *       comparator, or the matching threshold level will infinitely
-	 *       triggers interrupt.
-	 */
-	char flag;
-	/* Called when the interrupt fires */
-	void (*vcmp_thresh_cb)(void);
-	/*
-	 * Select "all voltage comparator" scan period time.
-	 * The power consumption is positively relative with scan frequency.
-	 */
-	enum vcmp_scan_period scan_period;
-	/*
-	 * Select which ADC channel output voltage into comparator and we
-	 * should set the ADC channel pin in alternate mode via adc_channels[].
-	 */
-	enum chip_adc_channel adc_ch;
-};
-
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-/*
- * Boards must provide this list of voltage comparator definitions.
- * This must match the enum board_vcmp list provided by the board.
- */
-extern const struct vcmp_t vcmp_list[];
-#endif
-void vcmp_enable(int index, int enable);
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
deleted file mode 100644
index bbff9f009b..0000000000
--- a/chip/it83xx/build.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# IT83xx chip specific files build
-#
-
-# IT8xxx1 and IT83xx are Andes N8 core.
-# IT8xxx2 is RISC-V core.
-ifeq ($(CHIP_FAMILY), it8xxx2)
-CORE:=riscv-rv32i
-else
-CORE:=nds32
-endif
-
-# Required chip modules
-chip-y=hwtimer.o uart.o gpio.o system.o clock.o irq.o intc.o
-
-# Optional chip modules
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(CONFIG_FANS)+=fan.o pwm.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-# IT8xxx2 series use the FPU instruction set of RISC-V (single-precision only).
-ifneq ($(CHIP_FAMILY), it8xxx2)
-chip-$(CONFIG_FPU)+=it83xx_fpu.o
-endif
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_DAC)+=dac.o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_PECI)+=peci.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_I2C_CONTROLLER)+=i2c.o
-chip-$(CONFIG_I2C_PERIPHERAL)+=i2c_peripheral.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
deleted file mode 100644
index 41f800721a..0000000000
--- a/chip/it83xx/clock.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "adc_chip.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "it83xx_pd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros. */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-#define SLEEP_SET_HTIMER_DELAY_USEC 250
-#define SLEEP_FTIMER_SKIP_USEC      (HOOK_TICK_INTERVAL * 2)
-
-static timestamp_t sleep_mode_t0;
-static timestamp_t sleep_mode_t1;
-static int idle_doze_cnt;
-static int idle_sleep_cnt;
-static uint64_t total_idle_sleep_time_us;
-static uint32_t ec_sleep;
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the heavy sleep mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 5;
-static timestamp_t console_expire_time;
-
-/* clock source is 32.768KHz */
-#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768)
-#define TIMER_CNT_8M_32P768K(cnt)    (((cnt) / (8000000 / 32768)) + 1)
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq;
-
-struct clock_gate_ctrl {
-	volatile uint8_t *reg;
-	uint8_t mask;
-};
-
-static void clock_module_disable(void)
-{
-	/* bit0: FSPI interface tri-state */
-	IT83XX_SMFI_FLHCTRL3R |= BIT(0);
-	/* bit7: USB pad power-on disable */
-	IT83XX_GCTRL_PMER2 &= ~BIT(7);
-	/* bit7: USB debug disable */
-	IT83XX_GCTRL_MCCR &= ~BIT(7);
-	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
-		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
-		CGC_OFFSET_SMBF), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI |
-		CGC_OFFSET_USB), 0, 0);
-}
-
-enum pll_freq_idx {
-	PLL_24_MHZ = 1,
-	PLL_48_MHZ = 2,
-	PLL_96_MHZ = 4,
-};
-
-static const uint8_t pll_to_idx[8] = {
-	0,
-	0,
-	PLL_24_MHZ,
-	0,
-	PLL_48_MHZ,
-	0,
-	0,
-	PLL_96_MHZ
-};
-
-struct clock_pll_t {
-	int     pll_freq;
-	uint8_t pll_setting;
-	uint8_t div_fnd;
-	uint8_t div_uart;
-	uint8_t div_usb;
-	uint8_t div_smb;
-	uint8_t div_sspi;
-	uint8_t div_ec;
-	uint8_t div_jtag;
-	uint8_t div_pwm;
-	uint8_t div_usbpd;
-};
-
-const struct clock_pll_t clock_pll_ctrl[] = {
-	/*
-	 * UART:  24MHz
-	 * SMB:   24MHz
-	 * EC:     8MHz
-	 * JTAG:  24MHz
-	 * USBPD:  8MHz
-	 * USB:   48MHz(no support if PLL=24MHz)
-	 * SSPI:  48MHz(24MHz if PLL=24MHz)
-	 */
-	/* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */
-	[PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2},
-#ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-	/* PLL:48MHz, MCU:48MHz, Fnd:48MHz */
-	[PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5},
-	/* PLL:96MHz, MCU:96MHz, Fnd:48MHz */
-	[PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb},
-#else
-	/* PLL:48MHz, MCU:48MHz, Fnd:24MHz */
-	[PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5},
-	/* PLL:96MHz, MCU:96MHz, Fnd:32MHz */
-	[PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb},
-#endif
-};
-
-static uint8_t pll_div_fnd;
-static uint8_t pll_div_ec;
-static uint8_t pll_div_jtag;
-static uint8_t pll_setting;
-
-void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
-{
-	volatile uint8_t _pll_ctrl __unused;
-
-	IT83XX_ECPM_PLLCTRL = mode;
-	/*
-	 * for deep doze / sleep mode
-	 * This load operation will ensure PLL setting is taken into
-	 * control register before wait for interrupt instruction.
-	 */
-	_pll_ctrl = IT83XX_ECPM_PLLCTRL;
-
-#ifdef IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN
-	/*
-	 * WORKAROUND: this workaround is used to fix EC gets stuck in low power
-	 * mode when WRST# is asserted.
-	 *
-	 * By default, flash will go into deep power down mode automatically
-	 * when EC is in low power mode. But we got an issue on IT83202BX that
-	 * flash won't be able to wake up correctly when WRST# is asserted
-	 * under this condition.
-	 * This issue might cause cold reset failure so we fix it.
-	 *
-	 * NOTE: this fix will increase power number about 40uA in low power
-	 * mode.
-	 */
-	if (mode == EC_PLL_DOZE)
-		IT83XX_SMFI_SMECCS &= ~IT83XX_SMFI_MASK_HOSTWA;
-	else
-		/*
-		 * Don't send deep power down mode command to flash when EC in
-		 * low power mode.
-		 */
-		IT83XX_SMFI_SMECCS |= IT83XX_SMFI_MASK_HOSTWA;
-#endif
-	/*
-	 * barrier: ensure low power mode setting is taken into control
-	 * register before standby instruction.
-	 */
-	data_serialization_barrier();
-}
-
-void __ram_code clock_pll_changed(void)
-{
-	IT83XX_GCTRL_SSCR &= ~BIT(0);
-	/*
-	 * Update PLL settings.
-	 * Writing data to this register doesn't change the
-	 * PLL frequency immediately until the status is changed
-	 * into wakeup from the sleep mode.
-	 * The following code is intended to make the system
-	 * enter sleep mode, and set up a HW timer to wakeup EC to
-	 * complete PLL update.
-	 */
-	IT83XX_ECPM_PLLFREQR = pll_setting;
-	/* Pre-set FND clock frequency = PLL / 3 */
-	IT83XX_ECPM_SCDCR0 = (2 << 4);
-	/* JTAG and EC */
-	IT83XX_ECPM_SCDCR3 = (pll_div_jtag << 4) | pll_div_ec;
-	/* EC sleep after standby instruction */
-	clock_ec_pll_ctrl(EC_PLL_SLEEP);
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		/* Global interrupt enable */
-		asm volatile ("setgie.e");
-		/* EC sleep */
-		asm("standby wake_grant");
-		/* Global interrupt disable */
-		asm volatile ("setgie.d");
-	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		/* Global interrupt enable */
-		asm volatile ("csrsi mstatus, 0x8");
-		/* EC sleep */
-		asm("wfi");
-		/* Global interrupt disable */
-		asm volatile ("csrci mstatus, 0x8");
-	}
-	/* New FND clock frequency */
-	IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
-	/* EC doze after standby instruction */
-	clock_ec_pll_ctrl(EC_PLL_DOZE);
-}
-
-/* NOTE: Don't use this function in other place. */
-static void clock_set_pll(enum pll_freq_idx idx)
-{
-	int pll;
-
-	pll_div_fnd  = clock_pll_ctrl[idx].div_fnd;
-	pll_div_ec   = clock_pll_ctrl[idx].div_ec;
-	pll_div_jtag = clock_pll_ctrl[idx].div_jtag;
-	pll_setting  = clock_pll_ctrl[idx].pll_setting;
-
-	/* Update PLL settings or not */
-	if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) ||
-		((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
-		((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
-		/* Enable hw timer to wakeup EC from the sleep mode */
-		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
-				1, 1, 5, 1, 0);
-		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
-		/*
-		 * Workaround for (b:70537592):
-		 * We have to set chip select pin as input mode in order to
-		 * change PLL.
-		 */
-		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7);
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-		/*
-		 * On DX version, we have to disable eSPI pad before changing
-		 * PLL sequence or sequence will fail if CS# pin is low.
-		 */
-		espi_enable_pad(0);
-#endif
-#endif
-		/* Update PLL settings. */
-		clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-		/* Enable eSPI pad after changing PLL sequence. */
-		espi_enable_pad(1);
-#endif
-		/* (b:70537592) Change back to ESPI CS# function. */
-		IT83XX_GPIO_GPCRM5 &= ~0xc0;
-#endif
-	}
-
-	/* Get new/current setting of PLL frequency */
-	pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf];
-	/* USB and UART */
-	IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) |
-				clock_pll_ctrl[pll].div_uart;
-	/* SSPI and SMB */
-	IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) |
-				clock_pll_ctrl[pll].div_smb;
-	/* USBPD and PWM */
-	IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) |
-				clock_pll_ctrl[pll].div_pwm;
-	/* Current PLL frequency  */
-	freq = clock_pll_ctrl[pll].pll_freq;
-}
-
-void clock_init(void)
-{
-	uint32_t image_type = (uint32_t)clock_init;
-
-	/* To change interrupt vector base if at RW image */
-	if (image_type > CONFIG_RW_MEM_OFF)
-		/* Interrupt Vector Table Base Address, in 64k Byte unit */
-		IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
-
-#if (PLL_CLOCK == 24000000)     || \
-	(PLL_CLOCK == 48000000) || \
-	(PLL_CLOCK == 96000000)
-	/* Set PLL frequency */
-	clock_set_pll(PLL_CLOCK / 24000000);
-#else
-#error "Support only for PLL clock speed of 24/48/96MHz."
-#endif
-	/*
-	 * The VCC power status is treated as power-on.
-	 * The VCC supply of LPC and related functions (EC2I,
-	 * KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI).
-	 * It means VCC (pin 11) should be logic high before using
-	 * these functions, or firmware treats VCC logic high
-	 * as following setting.
-	 */
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
-
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Because we don't support eSPI HW reset function (b/111480168) on DX
-	 * version, so we have to reset eSPI configurations during init to
-	 * ensure Host and EC are synchronized (especially for the field of
-	 * I/O mode)
-	 */
-	if (!system_jumped_to_this_image())
-		espi_fw_reset_module();
-#endif
-	/* Turn off auto clock gating. */
-	IT83XX_ECPM_AUTOCG = 0x00;
-
-	/* Default doze mode */
-	clock_ec_pll_ctrl(EC_PLL_DOZE);
-
-	clock_module_disable();
-
-#ifdef CONFIG_HOSTCMD_X86
-	IT83XX_WUC_WUESR4 = BIT(2);
-	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
-	/* bit2, wake-up enable for LPC access */
-	IT83XX_WUC_WUENR4 |= BIT(2);
-#endif
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-/**
- * Enable clock to specified peripheral
- *
- * @param offset Should be element of clock_gate_offsets enum.
- *               Bits 8-15 specify the ECPM offset of the specific clock reg.
- *               Bits 0-7 specify the mask for the clock register.
- * @param mask   Unused
- * @param mode   Unused
- */
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
-	uint8_t reg_mask = offset & 0xff;
-
-	/*
-	 * Note: CGCTRL3R, bit 6, must always write 1, but since there is no
-	 * offset argument that addresses this bit, then we are guaranteed
-	 * that this line will write a 1 to that bit.
-	 */
-	*reg &= ~reg_mask;
-}
-
-/**
- * Disable clock to specified peripheral
- *
- * @param offset Should be element of clock_gate_offsets enum.
- *               Bits 8-15 specify the ECPM offset of the specific clock reg.
- *               Bits 0-7 specify the mask for the clock register.
- * @param mask   Unused
- * @param mode   Unused
- */
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
-	uint8_t reg_mask = offset & 0xff;
-	uint8_t tmp_mask = 0;
-
-	/* CGCTRL3R, bit 6, must always write a 1. */
-	tmp_mask |= ((offset >> 8) == IT83XX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00;
-
-	*reg |= reg_mask | tmp_mask;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void clock_refresh_console_in_use(void)
-{
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
-					uint32_t count)
-{
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
-	IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
-	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count;
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3;
-}
-
-static void clock_htimer_enable(void)
-{
-	uint32_t c;
-
-	/* change event timer clock source to 32.768 KHz */
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER));
-#else
-	c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#endif
-	clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c);
-}
-
-static int clock_allow_low_power_idle(void)
-{
-	/*
-	 * Avoiding using low frequency clock run the same count as awaken in
-	 * sleep mode, so don't go to sleep mode before timer reload count.
-	 */
-	if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)))
-		return 0;
-
-	/* If timer interrupt status is set, don't go to sleep mode. */
-	if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
-		et_ctrl_regs[EVENT_EXT_TIMER].mask)
-		return 0;
-
-	/*
-	 * If timer is less than 250us to expire, then we don't go to sleep
-	 * mode.
-	 */
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
-#else
-	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
-#endif
-		SLEEP_SET_HTIMER_DELAY_USEC)
-		return 0;
-
-	/*
-	 * We calculate 32bit free clock overflow counts for 64bit value,
-	 * if clock almost reach overflow, we don't go to sleep mode for
-	 * avoiding miss overflow count.
-	 */
-	sleep_mode_t0 = get_time();
-	if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) ||
-		(sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
-		return 0;
-
-	/* If we are waked up by console, then keep awake at least 5s. */
-	if (sleep_mode_t0.val < console_expire_time.val)
-		return 0;
-
-	return 1;
-}
-
-int clock_ec_wake_from_sleep(void)
-{
-	return ec_sleep;
-}
-
-void __ram_code clock_cpu_standby(void)
-{
-	/* standby instruction */
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		asm("standby wake_grant");
-	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		if (!IS_ENABLED(IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED))
-			/*
-			 * we have to enable interrupts before
-			 * standby instruction on IT83202 bx version.
-			 */
-			interrupt_enable();
-
-		asm("wfi");
-	}
-}
-
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	/* disable all interrupts */
-	interrupt_disable();
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		chip_disable_irq(i);
-		chip_clear_pending_irq(i);
-	}
-	/* bit5: watchdog is disabled. */
-	IT83XX_ETWD_ETWCTRL |= BIT(5);
-
-	/*
-	 * Setup GPIOs for hibernate.  On some boards, it's possible that this
-	 * may not return at all.  On those boards, power to the EC is likely
-	 * being turn off entirely.
-	 */
-	if (board_hibernate_late) {
-		/*
-		 * Set reset flag in case board_hibernate_late() doesn't
-		 * return.
-		 */
-		chip_save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-		board_hibernate_late();
-	}
-
-	if (seconds || microseconds) {
-		/* At least 1 ms for hibernate. */
-		uint64_t c = (seconds * 1000 + microseconds / 1000 + 1) * 1024;
-
-		uint64divmod(&c, 1000);
-		/* enable a 56-bit timer and clock source is 1.024 KHz */
-		ext_timer_stop(FREE_EXT_TIMER_L, 1);
-		ext_timer_stop(FREE_EXT_TIMER_H, 1);
-		IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_L) = EXT_PSR_1P024K_HZ;
-		IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_H) = EXT_PSR_1P024K_HZ;
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_L) = c & 0xffffff;
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = (c >> 24) & 0xffffffff;
-		ext_timer_start(FREE_EXT_TIMER_H, 1);
-		ext_timer_start(FREE_EXT_TIMER_L, 0);
-	}
-
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)) {
-		/*
-		 * Disable active cc and pd modules and only left Rd_5.1k (Not
-		 * Rd_DB) alive in hibernate for better power consumption.
-		 */
-		for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; i++)
-			it83xx_Rd_5_1K_only_for_hibernate(i);
-	}
-
-	if (IS_ENABLED(CONFIG_ADC_VOLTAGE_COMPARATOR)) {
-		/*
-		 * Disable all voltage comparator modules in hibernate
-		 * for better power consumption.
-		 */
-		for (i = CHIP_VCMP0; i < CHIP_VCMP_COUNT; i++)
-			vcmp_enable(i, 0);
-	}
-
-	for (i = 0; i < hibernate_wake_pins_used; ++i)
-		gpio_enable_interrupt(hibernate_wake_pins[i]);
-
-	/* EC sleep */
-	ec_sleep = 1;
-#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
-	/* Disable eSPI pad. */
-	espi_enable_pad(0);
-#endif
-	clock_ec_pll_ctrl(EC_PLL_SLEEP);
-	interrupt_enable();
-	/* standby instruction */
-	clock_cpu_standby();
-
-	/* we should never reach that point */
-	__builtin_unreachable();
-}
-
-/* use data type int here not bool to get better instruction number. */
-static volatile int wait_interrupt_fired;
-void clock_sleep_mode_wakeup_isr(void)
-{
-	uint32_t st_us, c;
-
-	/* Clear flag on each interrupt. */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		wait_interrupt_fired = 0;
-
-	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
-	if (clock_ec_wake_from_sleep()) {
-#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
-		/*
-		 * Enable eSPI pad.
-		 * We will not need to enable eSPI pad here if Dx is able to
-		 * enable watchdog hardware reset function. But the function is
-		 * failed (b:111264984), so the following system reset is
-		 * software reset (PLL setting is not reset).
-		 * We will not go into the change PLL sequence on reboot if PLL
-		 * setting is the same, so the operation of enabling eSPI pad we
-		 * added in clock_set_pll() will not be applied.
-		 */
-		espi_enable_pad(1);
-#endif
-		system_reset(SYSTEM_RESET_HARD);
-	}
-
-	if (IT83XX_ECPM_PLLCTRL == EC_PLL_DEEP_DOZE) {
-		clock_ec_pll_ctrl(EC_PLL_DOZE);
-		/* update free running timer */
-		c = LOW_POWER_TIMER_MASK -
-			IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
-		st_us = TIMER_32P768K_CNT_TO_US(c);
-		sleep_mode_t1.val = sleep_mode_t0.val + st_us;
-		__hw_clock_source_set(sleep_mode_t1.le.lo);
-
-		/* reset event timer and clock source is 8 MHz */
-		clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff);
-		task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-		process_timers(0);
-#ifdef CONFIG_HOSTCMD_X86
-		/* disable lpc access wui */
-		task_disable_irq(IT83XX_IRQ_WKINTAD);
-		IT83XX_WUC_WUESR4 = BIT(2);
-		task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
-#endif
-		/* disable uart wui */
-		uart_exit_dsleep();
-		/* Record time spent in sleep. */
-		total_idle_sleep_time_us += st_us;
-	}
-}
-
-void __keep __idle_init(void)
-{
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-	/* init hw timer and clock source is 32.768 KHz */
-	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0,
-		0xffffffff, 1, 1);
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-}
-
-/**
- * Low power idle task. Executed when no tasks are ready to be scheduled.
- */
-void __ram_code __idle(void)
-{
-	/*
-	 * There is not enough space from ram code section to cache entire idle
-	 * function, hence pull initialization function out of the section.
-	 */
-	__idle_init();
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-		/* Check if the EC can enter deep doze mode or not */
-		if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
-			/* reset low power mode hw timer */
-			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1);
-			sleep_mode_t0 = get_time();
-#ifdef CONFIG_HOSTCMD_X86
-			/* enable lpc access wui */
-			task_enable_irq(IT83XX_IRQ_WKINTAD);
-#endif
-			/* enable uart wui */
-			uart_enter_dsleep();
-			/* enable hw timer for deep doze / sleep mode wake-up */
-			clock_htimer_enable();
-			/* deep doze mode */
-			clock_ec_pll_ctrl(EC_PLL_DEEP_DOZE);
-			idle_sleep_cnt++;
-		} else {
-			/* doze mode */
-			clock_ec_pll_ctrl(EC_PLL_DOZE);
-			idle_doze_cnt++;
-		}
-		/* Set flag before entering low power mode. */
-		if (IS_ENABLED(CHIP_CORE_RISCV))
-			wait_interrupt_fired = 1;
-		clock_cpu_standby();
-		interrupt_enable();
-		/*
-		 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
-		 * register is non-zero.
-		 * If the wait_interrupt_fired flag is true at this point,
-		 * it means that EC waked-up by the above issue not an
-		 * interrupt. Hence we loop running wfi instruction here until
-		 * wfi success.
-		 */
-		while (IS_ENABLED(CHIP_CORE_RISCV) && wait_interrupt_fired)
-			clock_cpu_standby();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-#ifdef CONFIG_LOW_POWER_IDLE
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that doze:            %d\n", idle_doze_cnt);
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-
-	ccprintf("Total Time spent in sleep(sec):      %.6lld(s)\n",
-						total_idle_sleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
deleted file mode 100644
index 2f552c794a..0000000000
--- a/chip/it83xx/config_chip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-#include "config_chip_it8320.h"
-#elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */
-#include "config_chip_it8xxx2.h"
-#else
-#error "Unsupported chip family!"
-#endif
-
-/* Number of IRQ vectors on the IVIC */
-#define CONFIG_IRQ_COUNT IT83XX_IRQ_COUNT
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default PLL frequency. */
-#define PLL_CLOCK 48000000
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 6
-
-/* I2C ports on chip
- * IT83xx - There are three i2c standard ports.
- *          There are three i2c enhanced ports.
- */
-#define I2C_STANDARD_PORT_COUNT 3
-#define I2C_ENHANCED_PORT_COUNT 3
-
-/* System stack size */
-#define CONFIG_STACK_SIZE           1024
-
-/* non-standard task stack sizes */
-#define SMALLER_TASK_STACK_SIZE     (384 + CHIP_EXTRA_STACK_SPACE)
-#define IDLE_TASK_STACK_SIZE        (512 + CHIP_EXTRA_STACK_SPACE)
-#define LARGER_TASK_STACK_SIZE      (768 + CHIP_EXTRA_STACK_SPACE)
-#define VENTI_TASK_STACK_SIZE       (896 + CHIP_EXTRA_STACK_SPACE)
-#define ULTRA_TASK_STACK_SIZE       (1056 + CHIP_EXTRA_STACK_SPACE)
-#define TRENTA_TASK_STACK_SIZE      (1184 + CHIP_EXTRA_STACK_SPACE)
-
-/* Default task stack size */
-#define TASK_STACK_SIZE             (512 + CHIP_EXTRA_STACK_SPACE)
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-#define CONFIG_FLASH_BANK_SIZE      0x00001000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00001000  /* erase bank size */
-#else
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#endif
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-
-/*
- * This is the block size of the ILM on the it83xx chip.
- * The ILM for static code cache, CPU fetch instruction from
- * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
- */
-#define IT83XX_ILM_BLOCK_SIZE       0x00001000
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-/*
- * One page program instruction allows maximum 256 bytes (a page) of data
- * to be programmed.
- */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
-#else
-/*
- * The AAI program instruction allows continue write flash
- * until write disable instruction.
- */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE
-#endif
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* H2RAM memory mapping */
-
-/*
- * Only it839x series and IT838x DX support mapping LPC I/O cycle 800h ~ 9FFh
- * to 0x8D800h ~ 0x8D9FFh of DLM13.
- *
- * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh
- * to 0x80081800 ~ 0x800819FF of DLM1.
- */
-#define CONFIG_H2RAM_BASE               (CHIP_H2RAM_BASE)
-#define CONFIG_H2RAM_SIZE               0x00001000
-#define CONFIG_H2RAM_HOST_LPC_IO_BASE   0x800
-
-/****************************************************************************/
-/* Customize the build */
-
-#define CONFIG_FW_RESET_VECTOR
-
-/* Optional features present on this chip */
-#define CHIP_FAMILY_IT83XX
-#define CONFIG_ADC
-#define CONFIG_SWITCH
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#define __RAM_CODE_SECTION_NAME ".ram_code"
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
deleted file mode 100644
index 53f4a1cbd3..0000000000
--- a/chip/it83xx/config_chip_it8320.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_IT8320_H
-#define __CROS_EC_CONFIG_CHIP_IT8320_H
-
-/* CPU core BFD configuration */
-#include "core/nds32/config_core.h"
-
-/* N8 core */
-#define CHIP_CORE_NDS32
-/* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F01100
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CHIP_H2RAM_BASE             0x0008D000 /* 0x0008D000~0x0008DFFF */
-#define CHIP_RAMCODE_BASE           0x0008E000 /* 0x0008E000~0x0008EFFF */
-#define CHIP_EXTRA_STACK_SPACE      0
-
-#define CONFIG_RAM_BASE             0x00080000
-#define CONFIG_RAM_SIZE             0x0000C000
-
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
-
-/****************************************************************************/
-/* Chip IT8320 is used with IT83XX TCPM driver */
-#define CONFIG_USB_PD_TCPM_DRIVER_IT83XX
-
-#if defined(CHIP_VARIANT_IT8320BX)
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA.
- */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000
-/* For IT8320BX, we have to reload cc parameters after ec softreset. */
-#define IT83XX_USBPD_CC_PARAMETER_RELOAD
-/*
- * The voltage detector of CC1 and CC2 is enabled/disabled by different bit
- * of the control register (bit1 and bit5 at register IT83XX_USBPD_CCCSR).
- */
-#define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-/* Chip IT8320BX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-/* For IT8320BX, we have to write 0xff to clear pending bit.*/
-#define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
-/* For IT8320BX, we have to read observation register of external timer two
- * times to get correct time.
- */
-#define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-#elif defined(CHIP_VARIANT_IT8320DX)
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/*
- * TODO(b/111480168): eSPI HW reset can't be used because the DMA address
- * gets set incorrectly resulting in a memory access exception.
- */
-#define IT83XX_ESPI_RESET_MODULE_BY_FW
-/* Watchdog reset supports hardware reset. */
-/* TODO(b/111264984): watchdog hardware reset function failed. */
-#undef IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * (b/112452221):
- * Floating-point multiplication single-precision is failed on DX version,
- * so we use the formula "A/(1/B)" to replace a multiplication operation
- * (A*B = A/(1/B)).
- */
-#define IT83XX_FPU_MUL_BY_DIV
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable interrupts of group 21 and 22. */
-#define IT83XX_INTC_GROUP_21_22_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Chip Dx transmit status bit of PD register is different from Bx. */
-#define IT83XX_PD_TX_ERROR_STATUS_BIT5
-/* Chip IT8320DX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-#else
-#error "Unsupported chip variant!"
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8320_H */
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
deleted file mode 100644
index a5b4096c8b..0000000000
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H
-#define __CROS_EC_CONFIG_CHIP_IT8XXX2_H
-
-/* CPU core BFD configuration */
-#include "core/riscv-rv32i/config_core.h"
-
-/* RISCV core */
-#define CHIP_CORE_RISCV
-#define CHIP_ILM_DLM_ORDER
-/* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F03F00
-#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-/*
- * ILM/DLM size register.
- * bit[3-0] ILM size:
- *     7: 512K byte (default setting), 8: 1M byte
- */
-#define IT83XX_GCTRL_EIDSR 0xf02031
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CHIP_ILM_BASE               0x80000000
-#define CHIP_EXTRA_STACK_SPACE      128
-/* We reserve 12KB space for ramcode, h2ram, and immu sections. */
-#define CHIP_RAM_SPACE_RESERVED     0x3000
-#define CONFIG_PROGRAM_MEMORY_BASE  (CHIP_ILM_BASE)
-
-/****************************************************************************/
-/* Chip IT83202 is used with IT8XXX2 TCPM driver */
-#define CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-
-#if defined(CHIP_VARIANT_IT83202BX)
-/* TODO(b/133460224): enable properly chip config option. */
-#define CONFIG_FLASH_SIZE_BYTES           0x00080000
-#define CONFIG_RAM_BASE             0x80080000
-#define CONFIG_RAM_SIZE             0x00010000
-
-/* Embedded flash is KGD */
-#define IT83XX_CHIP_FLASH_IS_KGD
-/* Don't let internal flash go into deep power down mode. */
-#define IT83XX_CHIP_FLASH_NO_DEEP_POWER_DOWN
-/* chip id is 3 bytes */
-#define IT83XX_CHIP_ID_3BYTES
-/*
- * The bit19 of ram code base address is controlled by bit7 of register SCARxH
- * instead of bit3.
- */
-#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/* Watchdog reset supports hardware reset. */
-#define IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Remap host I/O cycles to base address of H2RAM section. */
-#define IT83XX_H2RAM_REMAPPING
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Chip IT83202BX actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    3
-#elif defined(CHIP_VARIANT_IT81302AX_1024) \
-|| defined(CHIP_VARIANT_IT81202AX_1024) \
-|| defined(CHIP_VARIANT_IT81302BX_1024) \
-|| defined(CHIP_VARIANT_IT81202BX_1024)
-#define CONFIG_FLASH_SIZE_BYTES           0x00100000
-#define CONFIG_RAM_BASE             0x80100000
-#define CONFIG_RAM_SIZE             0x0000f000
-
-/* Embedded flash is KGD */
-#define IT83XX_CHIP_FLASH_IS_KGD
-/* Set ILM (instruction local memory) size up to 1M bytes */
-#define IT83XX_CHIP_FLASH_SIZE_1MB
-/* chip id is 3 bytes */
-#define IT83XX_CHIP_ID_3BYTES
-/*
- * The bit19 of ram code base address is controlled by bit7 of register SCARxH
- * instead of bit3.
- */
-#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-/*
- * Disable eSPI pad, then PLL change
- * (include EC clock frequency) is succeed even CS# is low.
- */
-#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/*
- * The peripheral frequency is adjustable
- * (bit[2-0] at register IT83XX_ESPI_GCAC1)
- */
-#define IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-/* Watchdog reset supports hardware reset. */
-#define IT83XX_ETWD_HW_RESET_SUPPORT
-/*
- * More GPIOs can be set as 1.8v input.
- * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
- */
-#define IT83XX_GPIO_1P8V_PIN_EXTENDED
-#if defined(CHIP_VARIANT_IT81202AX_1024) || defined(CHIP_VARIANT_IT81202BX_1024)
-/* Pins of group K and L are set as internal pull-down at initialization. */
-#define IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
-#endif
-/* GPIOH7 is set as output low at initialization. */
-#define IT83XX_GPIO_H7_DEFAULT_OUTPUT_LOW
-/* All GPIOs support interrupt on rising, falling, and either edge. */
-#define IT83XX_GPIO_INT_FLEXIBLE
-/* Remap host I/O cycles to base address of H2RAM section. */
-#define IT83XX_H2RAM_REMAPPING
-/* Enable FRS detection interrupt. */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-/* Enable detect type-c plug in and out interrupt. */
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-/* Wake up CPU from low power mode even if interrupts are disabled */
-#define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED
-/* Individual setting CC1 and CC2 resistance. */
-#define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
-/* Chip actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-#else
-#error "Unsupported chip variant!"
-#endif
-
-#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0)      /* base+0000h~base+0FFF */
-#define CHIP_H2RAM_BASE   (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
-#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */
-
-#ifdef BASEBOARD_KUKUI
-/*
- * Reserved 0x80000~0xfffff 512kb on flash for saving EC logs (8kb space is
- * enough to save the logs). This configuration reduces EC FW binary size to
- * 512kb. With this config, we still have 4x kb space on RO and 6x kb space on
- * RW.
- */
-#define CHIP_FLASH_PRESERVE_LOGS_BASE 0x80000
-#define CHIP_FLASH_PRESERVE_LOGS_SIZE 0x2000
-#undef CONFIG_FLASH_SIZE_BYTES
-#define CONFIG_FLASH_SIZE_BYTES CHIP_FLASH_PRESERVE_LOGS_BASE
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
diff --git a/chip/it83xx/dac.c b/chip/it83xx/dac.c
deleted file mode 100644
index 695d1cbc68..0000000000
--- a/chip/it83xx/dac.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx DAC module for Chrome EC */
-
-#include "console.h"
-#include "dac_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-/* DAC module enable */
-void dac_enable_channel(enum chip_dac_channel ch)
-{
-	IT83XX_DAC_DACPDREG &= ~IT83XX_DAC_POWDN(ch);
-}
-
-/* DAC module disable */
-void dac_disable_channel(enum chip_dac_channel ch)
-{
-	IT83XX_DAC_DACPDREG |= IT83XX_DAC_POWDN(ch);
-}
-
-/* Set DAC output voltage */
-void dac_set_output_voltage(enum chip_dac_channel ch, int mv)
-{
-	IT83XX_DAC_DACDAT(ch) = mv * DAC_RAW_DATA / DAC_AVCC;
-}
-
-/* Get DAC output voltage */
-int dac_get_output_voltage(enum chip_dac_channel ch)
-{
-	return IT83XX_DAC_DACDAT(ch) * DAC_AVCC / DAC_RAW_DATA;
-}
-
-/* DAC module Initialization */
-static void dac_init(void)
-{
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_DAC, 1);
-}
-DECLARE_HOOK(HOOK_INIT, dac_init, HOOK_PRIO_INIT_DAC);
-
-static int command_dac(int argc, char **argv)
-{
-	char *e;
-	int ch, mv, rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	if (ch < 2 || ch > 5) {
-		ccprintf("ch%d is not supported\n", ch);
-		return EC_ERROR_PARAM1;
-	}
-
-	if (argc == 2) {
-		if (!(IT83XX_DAC_DACPDREG & IT83XX_DAC_POWDN(ch))) {
-			/* Get DAC output voltage */
-			rv = dac_get_output_voltage(ch);
-			ccprintf("DAC ch%d VOLT=%dmV\n", ch, rv);
-		} else
-			ccprintf("The DAC ch%d is powered down.\n", ch);
-	} else {
-		/*
-		 * DAC data register raw data
-		 * 0 ~ 0xFF(8-bit) = voltage 0 ~ 3300mV
-		 */
-		mv = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (mv) {
-			/* Set DAC output voltage */
-			dac_set_output_voltage(ch, mv);
-			dac_enable_channel(ch);
-		} else
-			dac_disable_channel(ch);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dac, command_dac,
-			"[ch2-5] [0-3300mV]",
-			"Enable or disable(0mV) DAC output voltage.");
diff --git a/chip/it83xx/dac_chip.h b/chip/it83xx/dac_chip.h
deleted file mode 100644
index fa50769c85..0000000000
--- a/chip/it83xx/dac_chip.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IT83xx DAC module for Chrome EC */
-
-#ifndef __CROS_EC_DAC_CHIP_H
-#define __CROS_EC_DAC_CHIP_H
-
-#define DAC_AVCC 3300
-/*
- * Each channel generates an output ranging
- * from 0V to AVCC with 8-bit resolution.
- */
-#define DAC_RAW_DATA (BIT(8) - 1)
-
-/* List of DAC channels. */
-enum chip_dac_channel {
-	CHIP_DAC_CH2 = 2,
-	CHIP_DAC_CH3,
-	CHIP_DAC_CH4,
-	CHIP_DAC_CH5,
-};
-
-/**
- * DAC module enable.
- *
- * @param ch		Channel to enable.
- */
-void dac_enable_channel(enum chip_dac_channel ch);
-
-/**
- * DAC module disable.
- *
- * @param ch		Channel to disable.
- */
-void dac_disable_channel(enum chip_dac_channel ch);
-
-/**
- * Set DAC output voltage.
- *
- * @param ch		Channel to set.
- * @param mv		Setting ch output voltage.
- */
-void dac_set_output_voltage(enum chip_dac_channel ch, int mv);
-
-/**
- * Get DAC output voltage.
- *
- * @param ch		Channel to get.
- *
- * @return		Getting ch output voltage.
- */
-int dac_get_output_voltage(enum chip_dac_channel ch);
-
-#endif /* __CROS_EC_DAC_CHIP_H */
-
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
deleted file mode 100644
index be02a8f813..0000000000
--- a/chip/it83xx/ec2i.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EC2I control module for IT83xx. */
-
-#include "common.h"
-#include "console.h"
-#include "ec2i_chip.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-static const struct ec2i_t keyboard_settings[] = {
-	/* Select logical device 06h(keyboard) */
-	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
-	/* Set IRQ=01h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x01},
-	/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Interrupt request type select (IRQTP) for KBC.
-	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
-	 *        1: IRQ request is inverted before being applied to SERIRQ
-	 * bit 0, 0: Edge triggered mode
-	 *        1: Level triggered mode
-	 *
-	 * SERIRQ# is by default deasserted level high. However, when using
-	 * eSPI, SERIRQ# is routed over virtual wire as interrupt event. As
-	 * per eSPI base spec (doc#327432), all virtual wire interrupt events
-	 * are deasserted level low. Thus, it is necessary to configure this
-	 * interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
-	 * signal appropriately over eSPI / LPC depending upon the selected
-	 * mode.
-	 *
-	 * Additionally, this interrupt is configured as edge-triggered on the
-	 * host side. So, match the trigger mode on the EC side as well.
-	 */
-	{HOST_INDEX_IRQTP, 0x02},
-#endif
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-static const struct ec2i_t mouse_settings[] = {
-	/* Select logical device 05h(mouse) */
-	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
-	/* Set IRQ=0Ch for logical device */
-	{HOST_INDEX_IRQNUMX, 0x0C},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-#endif
-
-static const struct ec2i_t pm1_settings[] = {
-	/* Select logical device 11h(PM1 ACPI) */
-	{HOST_INDEX_LDN, LDN_PMC1},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-static const struct ec2i_t pm2_settings[] = {
-	/* Select logical device 12h(PM2) */
-	{HOST_INDEX_LDN, LDN_PMC2},
-	/* I/O Port Base Address 200h/204h */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0x00},
-	{HOST_INDEX_IOBAD1_MSB, 0x02},
-	{HOST_INDEX_IOBAD1_LSB, 0x04},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-static const struct ec2i_t smfi_settings[] = {
-	/* Select logical device 0Fh(SMFI) */
-	{HOST_INDEX_LDN, LDN_SMFI},
-	/* H2RAM LPC I/O cycle Dxxx */
-	{HOST_INDEX_DSLDC6, 0x00},
-	/* Enable H2RAM LPC I/O cycle */
-	{HOST_INDEX_DSLDC7, 0x01},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-/*
- * PM3 is enabled and base address is set to 80h so that we are able to get an
- * interrupt when host outputs data to port 80.
- */
-static const struct ec2i_t pm3_settings[] = {
-	/* Select logical device 17h(PM3) */
-	{HOST_INDEX_LDN, LDN_PMC3},
-	/* I/O Port Base Address 80h */
-	{HOST_INDEX_IOBAD0_MSB, 0x00},
-	{HOST_INDEX_IOBAD0_LSB, 0x80},
-	{HOST_INDEX_IOBAD1_MSB, 0x00},
-	{HOST_INDEX_IOBAD1_LSB, 0x00},
-	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-
-/*
- * This logical device is not enabled, however P80L* settings need to be
- * performed on this logical device to ensure that port80 BRAM index is
- * initialized correctly.
- */
-static const struct ec2i_t rtct_settings[] = {
-	/* Select logical device 10h(RTCT) */
-	{HOST_INDEX_LDN, LDN_RTCT},
-	/* P80L Begin Index */
-	{HOST_INDEX_DSLDC4, P80L_P80LB},
-	/* P80L End Index */
-	{HOST_INDEX_DSLDC5, P80L_P80LE},
-	/* P80L Current Index */
-	{HOST_INDEX_DSLDC6, P80L_P80LC},
-};
-
-#ifdef CONFIG_UART_HOST
-static const struct ec2i_t uart2_settings[] = {
-	/* Select logical device 2h(UART2) */
-	{HOST_INDEX_LDN, LDN_UART2},
-	/*
-	 * I/O port base address is 2F8h.
-	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
-	 * See specification 7.24.4 for more detial.
-	 */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0xF8},
-	/* IRQ number is 3 */
-	{HOST_INDEX_IRQNUMX, 0x03},
-	/*
-	 * Interrupt Request Type Select
-	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
-	 *       1: IRQ request is inverted before being applied to SERIRQ.
-	 * bit0, 0: Edge triggered mode.
-	 *       1: Level triggered mode.
-	 */
-	{HOST_INDEX_IRQTP, 0x02},
-	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
-};
-#endif
-
-/* EC2I access index/data port */
-enum ec2i_access {
-	/* index port */
-	EC2I_ACCESS_INDEX = 0,
-	/* data port */
-	EC2I_ACCESS_DATA = 1,
-};
-
-enum ec2i_status_mask {
-	/* 1: EC read-access is still processing. */
-	EC2I_STATUS_CRIB = BIT(1),
-	/* 1: EC write-access is still processing with IHD register. */
-	EC2I_STATUS_CWIB = BIT(2),
-	EC2I_STATUS_ALL  = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
-};
-
-static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask)
-{
-	/* delay ~15.25us */
-	IT83XX_GCTRL_WNCKR = 0;
-
-	return (IT83XX_EC2I_IBCTL & mask);
-}
-
-static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
-{
-	int rv = EC_ERROR_UNKNOWN;
-
-	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
-		/*
-		 * Wait that both CRIB and CWIB bits in IBCTL register
-		 * are cleared.
-		 */
-		rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
-		if (!rv) {
-			/* Set indirect host I/O offset. */
-			IT83XX_EC2I_IHIOA = sel;
-			/* Write the data to IHD register */
-			IT83XX_EC2I_IHD = data;
-			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= BIT(0);
-			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= BIT(0);
-			/* Wait the CWIB bit in IBCTL cleared. */
-			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB);
-			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~BIT(0);
-			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~BIT(0);
-		}
-	}
-
-	return rv ? EC2I_WRITE_ERROR : EC2I_WRITE_SUCCESS;
-}
-
-static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
-{
-	int rv = EC_ERROR_UNKNOWN;
-	uint8_t ihd = 0;
-
-	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
-		/*
-		 * Wait that both CRIB and CWIB bits in IBCTL register
-		 * are cleared.
-		 */
-		rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL);
-		if (!rv) {
-			/* Set indirect host I/O offset. */
-			IT83XX_EC2I_IHIOA = sel;
-			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= BIT(0);
-			/* bit1: a read-action */
-			IT83XX_EC2I_IBCTL |= BIT(1);
-			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= BIT(0);
-			/* Wait the CRIB bit in IBCTL cleared. */
-			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB);
-			/* Read the data from IHD register */
-			ihd = IT83XX_EC2I_IHD;
-			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~BIT(0);
-			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~BIT(0);
-		}
-	}
-
-	return rv ? EC2I_READ_ERROR : (EC2I_READ_SUCCESS + ihd);
-}
-
-/* EC2I read */
-enum ec2i_message ec2i_read(enum host_pnpcfg_index index)
-{
-	enum ec2i_message ret = EC2I_READ_ERROR;
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* Set index */
-	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
-		/* read data port */
-		ret = ec2i_read_pnpcfg(EC2I_ACCESS_DATA);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	return ret;
-}
-
-/* EC2I write */
-enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data)
-{
-	enum ec2i_message ret = EC2I_WRITE_ERROR;
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* Set index */
-	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
-		/* Set data */
-		ret = ec2i_write_pnpcfg(EC2I_ACCESS_DATA, data);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	return ret;
-}
-
-static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries)
-{
-	size_t i;
-
-	for (i = 0; i < entries; i++) {
-		if (ec2i_write(settings[i].index_port, settings[i].data_port) ==
-		    EC2I_WRITE_ERROR) {
-			ccprints("Failed to apply %zd", i);
-			break;
-		}
-	}
-}
-
-#define PNPCFG(_s)						\
-	pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
-
-static void pnpcfg_init(void)
-{
-	/* Host access is disabled */
-	IT83XX_EC2I_LSIOHA |= 0x3;
-
-	PNPCFG(keyboard);
-#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-	PNPCFG(mouse);
-#endif
-	PNPCFG(pm1);
-	PNPCFG(pm2);
-	PNPCFG(smfi);
-	PNPCFG(pm3);
-	PNPCFG(rtct);
-#ifdef CONFIG_UART_HOST
-	PNPCFG(uart2);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, pnpcfg_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
deleted file mode 100644
index c8069f4ff5..0000000000
--- a/chip/it83xx/ec2i_chip.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EC2I control module for IT83xx. */
-
-#ifndef __CROS_EC_EC2I_CHIP_H
-#define __CROS_EC_EC2I_CHIP_H
-
-#define P80L_P80LB               0
-#define P80L_P80LE               0x3F
-#define P80L_P80LC               0
-#define P80L_BRAM_BANK1_SIZE_MASK 0x3F
-
-/* Index list of the host interface registers of PNPCFG */
-enum host_pnpcfg_index {
-	/* Logical Device Number */
-	HOST_INDEX_LDN = 0x07,
-	/* Chip ID Byte 1 */
-	HOST_INDEX_CHIPID1 = 0x20,
-	/* Chip ID Byte 2 */
-	HOST_INDEX_CHIPID2 = 0x21,
-	/* Chip Version */
-	HOST_INDEX_CHIPVER = 0x22,
-	/* Super I/O Control */
-	HOST_INDEX_SIOCTRL = 0x23,
-	/* Super I/O IRQ Configuration */
-	HOST_INDEX_SIOIRQ = 0x25,
-	/* Super I/O General Purpose */
-	HOST_INDEX_SIOGP = 0x26,
-	/* Super I/O Power Mode */
-	HOST_INDEX_SIOPWR = 0x2D,
-	/* Depth 2 I/O Address */
-	HOST_INDEX_D2ADR = 0x2E,
-	/* Depth 2 I/O Data */
-	HOST_INDEX_D2DAT = 0x2F,
-	/* Logical Device Activate Register */
-	HOST_INDEX_LDA = 0x30,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_MSB = 0x60,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_LSB = 0x61,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_MSB = 0x62,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_LSB = 0x63,
-	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
-	HOST_INDEX_IRQNUMX = 0x70,
-	/* Interrupt Request Type Select */
-	HOST_INDEX_IRQTP = 0x71,
-	/* DMA Channel Select 0 */
-	HOST_INDEX_DMAS0 = 0x74,
-	/* DMA Channel Select 1 */
-	HOST_INDEX_DMAS1 = 0x75,
-	/* Device Specific Logical Device Configuration 1 to 10 */
-	HOST_INDEX_DSLDC1 = 0xF0,
-	HOST_INDEX_DSLDC2 = 0xF1,
-	HOST_INDEX_DSLDC3 = 0xF2,
-	HOST_INDEX_DSLDC4 = 0xF3,
-	HOST_INDEX_DSLDC5 = 0xF4,
-	HOST_INDEX_DSLDC6 = 0xF5,
-	HOST_INDEX_DSLDC7 = 0xF6,
-	HOST_INDEX_DSLDC8 = 0xF7,
-	HOST_INDEX_DSLDC9 = 0xF8,
-	HOST_INDEX_DSLDC10 = 0xF9,
-};
-
-/* List of logical device number (LDN) assignments */
-enum logical_device_number {
-	/* Serial Port 1 */
-	LDN_UART1 = 0x01,
-	/* Serial Port 2 */
-	LDN_UART2 = 0x02,
-	/* System Wake-Up Control */
-	LDN_SWUC = 0x04,
-	/* KBC/Mouse Interface */
-	LDN_KBC_MOUSE = 0x05,
-	/* KBC/Keyboard Interface */
-	LDN_KBC_KEYBOARD = 0x06,
-	/* Consumer IR */
-	LDN_CIR = 0x0A,
-	/* Shared Memory/Flash Interface */
-	LDN_SMFI = 0x0F,
-	/* RTC-like Timer */
-	LDN_RTCT = 0x10,
-	/* Power Management I/F Channel 1 */
-	LDN_PMC1 = 0x11,
-	/* Power Management I/F Channel 2 */
-	LDN_PMC2 = 0x12,
-	/* Serial Peripheral Interface */
-	LDN_SSPI = 0x13,
-	/* Platform Environment Control Interface */
-	LDN_PECI = 0x14,
-	/* Power Management I/F Channel 3 */
-	LDN_PMC3 = 0x17,
-	/* Power Management I/F Channel 4 */
-	LDN_PMC4 = 0x18,
-	/* Power Management I/F Channel 5 */
-	LDN_PMC5 = 0x19,
-};
-
-/* EC2I read/write message */
-enum ec2i_message {
-	/* EC2I write success */
-	EC2I_WRITE_SUCCESS = 0x00,
-	/* EC2I write error */
-	EC2I_WRITE_ERROR = 0x01,
-	/* EC2I read success */
-	EC2I_READ_SUCCESS = 0x8000,
-	/* EC2I read error */
-	EC2I_READ_ERROR = 0x8100,
-};
-
-/* Data structure for initializing PNPCFG via ec2i. */
-struct ec2i_t {
-	/* index port */
-	enum host_pnpcfg_index index_port;
-	/* data port */
-	uint8_t data_port;
-};
-
-/* EC2I write */
-enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);
-
-/* EC2I read */
-enum ec2i_message ec2i_read(enum host_pnpcfg_index index);
-
-#endif /* __CROS_EC_EC2I_CHIP_H */
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
deleted file mode 100644
index 7385e83a93..0000000000
--- a/chip/it83xx/espi.c
+++ /dev/null
@@ -1,624 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "console.h"
-#include "espi.h"
-#include "hooks.h"
-#include "port80.h"
-#include "power.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-struct vw_channel_t {
-	uint8_t  index;         /* VW index of signal */
-	uint8_t  level_mask;    /* level bit of signal */
-	uint8_t  valid_mask;    /* valid bit of signal */
-};
-
-/* VW settings after the controller enables the VW channel. */
-static const struct vw_channel_t en_vw_setting[] = {
-	/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
-#ifndef CONFIG_CHIPSET_GEMINILAKE
-	{ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)},
-#endif
-};
-
-/* VW settings after the controller enables the OOB channel. */
-static const struct vw_channel_t en_oob_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)},
-};
-
-/* VW settings after the controller enables the flash channel. */
-static const struct vw_channel_t en_flash_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)},
-};
-
-/* VW settings at host startup */
-static const struct vw_channel_t vw_host_startup_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)},
-};
-
-#define VW_CHAN(name, idx, level, valid) \
-	[(name - VW_SIGNAL_START)] = {idx, level, valid}
-
-/* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */
-static const struct vw_channel_t vw_channel_list[] = {
-	/* index 02h: controller to peripheral. */
-	VW_CHAN(VW_SLP_S3_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S3),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S3)),
-	VW_CHAN(VW_SLP_S4_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S4),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S4)),
-	VW_CHAN(VW_SLP_S5_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
-		VW_LEVEL_FIELD(VW_IDX_2_SLP_S5),
-		VW_VALID_FIELD(VW_IDX_2_SLP_S5)),
-	/* index 03h: controller to peripheral. */
-	VW_CHAN(VW_SUS_STAT_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT),
-		VW_VALID_FIELD(VW_IDX_3_SUS_STAT)),
-	VW_CHAN(VW_PLTRST_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_PLTRST),
-		VW_VALID_FIELD(VW_IDX_3_PLTRST)),
-	VW_CHAN(VW_OOB_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
-		VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN),
-		VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)),
-	/* index 04h: peripheral to controller. */
-	VW_CHAN(VW_OOB_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)),
-	VW_CHAN(VW_WAKE_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_WAKE),
-		VW_VALID_FIELD(VW_IDX_4_WAKE)),
-	VW_CHAN(VW_PME_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_PME),
-		VW_VALID_FIELD(VW_IDX_4_PME)),
-	/* index 05h: peripheral to controller. */
-	VW_CHAN(VW_ERROR_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_FATAL)),
-	VW_CHAN(VW_ERROR_NON_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_NON_FATAL)),
-	VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)),
-	/* index 06h: peripheral to controller. */
-	VW_CHAN(VW_SCI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI),
-		VW_VALID_FIELD(VW_IDX_6_SCI)),
-	VW_CHAN(VW_SMI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SMI),
-		VW_VALID_FIELD(VW_IDX_6_SMI)),
-	VW_CHAN(VW_RCIN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_RCIN),
-		VW_VALID_FIELD(VW_IDX_6_RCIN)),
-	VW_CHAN(VW_HOST_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)),
-	/* index 07h: controller to peripheral. */
-	VW_CHAN(VW_HOST_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_7,
-		VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN),
-		VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)),
-	/* index 40h: peripheral to controller. */
-	VW_CHAN(VW_SUS_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)),
-	/* index 41h: controller to peripheral. */
-	VW_CHAN(VW_SUS_WARN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN),
-		VW_VALID_FIELD(VW_IDX_41_SUS_WARN)),
-	VW_CHAN(VW_SUS_PWRDN_ACK_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK),
-		VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)),
-	VW_CHAN(VW_SLP_A_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
-		VW_LEVEL_FIELD(VW_IDX_41_SLP_A),
-		VW_VALID_FIELD(VW_IDX_41_SLP_A)),
-	/* index 42h: controller to peripheral. */
-	VW_CHAN(VW_SLP_LAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
-		VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN),
-		VW_VALID_FIELD(VW_IDX_42_SLP_LAN)),
-	VW_CHAN(VW_SLP_WLAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
-		VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN),
-		VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)),
-};
-BUILD_ASSERT(ARRAY_SIZE(vw_channel_list) == VW_SIGNAL_COUNT);
-
-/* Get vw index & value information by signal */
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	uint32_t i = event - VW_SIGNAL_START;
-
-	return (i < ARRAY_SIZE(vw_channel_list)) ? i : -1;
-}
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	/* Get index of vw signal list by signale name */
-	int i = espi_vw_get_signal_index(signal);
-
-	if (i < 0)
-		return EC_ERROR_PARAM1;
-
-	/* critical section with interrupts off */
-	interrupt_disable();
-	if (level)
-		IT83XX_ESPI_VWIDX(vw_channel_list[i].index) |=
-			vw_channel_list[i].level_mask;
-	else
-		IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &=
-			~vw_channel_list[i].level_mask;
-	/* restore interrupts */
-	interrupt_enable();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	/* Get index of vw signal list by signale name */
-	int i = espi_vw_get_signal_index(signal);
-
-	if (i < 0)
-		return 0;
-
-	/* Not valid */
-	if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].valid_mask))
-		return 0;
-
-	return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].level_mask);
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	/*
-	 * Common code calls this function to enable VW interrupt of power
-	 * sequence signal.
-	 * IT83xx only use a bit (bit7@IT83XX_ESPI_VWCTRL0) to enable VW
-	 * interrupt.
-	 * VW interrupt will be triggerd with any updated VW index flag
-	 * if this control bit is set.
-	 * So we will always return success here.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	/*
-	 * We can't disable VW interrupt of power sequence signal
-	 * individually.
-	 */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-/* Configure virtual wire outputs */
-static void espi_configure_vw(const struct vw_channel_t *settings,
-						size_t entries)
-{
-	size_t i;
-
-	for (i = 0; i < entries; i++)
-		IT83XX_ESPI_VWIDX(settings[i].index) |=
-			(settings[i].level_mask | settings[i].valid_mask);
-}
-
-static void espi_vw_host_startup(void)
-{
-	espi_configure_vw(vw_host_startup_setting,
-				ARRAY_SIZE(vw_host_startup_setting));
-}
-
-static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)",
-								vw_evt);
-}
-
-#ifndef CONFIG_CHIPSET_GEMINILAKE
-static void espi_vw_idx41_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN))
-		espi_vw_set_wire(VW_SUS_ACK, espi_vw_get_wire(VW_SUS_WARN_L));
-}
-#endif
-
-static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN))
-		espi_vw_set_wire(VW_HOST_RST_ACK,
-			espi_vw_get_wire(VW_HOST_RST_WARN));
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_PLTRST)) {
-		int pltrst = espi_vw_get_wire(VW_PLTRST_L);
-
-		if (pltrst) {
-			espi_vw_host_startup();
-		} else {
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-		}
-
-		CPRINTS("VW PLTRST_L %sasserted", pltrst ? "de" : "");
-	}
-
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN))
-		espi_vw_set_wire(VW_OOB_RST_ACK,
-			espi_vw_get_wire(VW_OOB_RST_WARN));
-}
-
-static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt)
-{
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S3))
-		power_signal_interrupt(VW_SLP_S3_L);
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S4))
-		power_signal_interrupt(VW_SLP_S4_L);
-	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S5))
-		power_signal_interrupt(VW_SLP_S5_L);
-}
-
-struct vw_interrupt_t {
-	void (*vw_isr)(uint8_t flag_changed, uint8_t vw_evt);
-	uint8_t vw_index;
-};
-
-/*
- * The ISR of espi VW interrupt in array needs to match bit order in
- * IT83XX_ESPI_VWCTRL1 register.
- */
-#ifdef CONFIG_CHIPSET_GEMINILAKE
-static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
-};
-#else
-static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
-};
-#endif
-
-/*
- * This is used to record the previous VW valid / level field state to discover
- * changes. Then do following sequence only when state is changed.
- */
-static uint8_t vw_index_flag[ARRAY_SIZE(vw_isr_list)];
-
-void espi_vw_interrupt(void)
-{
-	int i;
-	uint8_t vwidx_updated = IT83XX_ESPI_VWCTRL1;
-
-#ifdef IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
-	/* For IT8320BX, we have to write 0xff to clear pending bit.*/
-	IT83XX_ESPI_VWCTRL1 = 0xff;
-#else
-	/* write-1 to clear */
-	IT83XX_ESPI_VWCTRL1 = vwidx_updated;
-#endif
-	task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
-
-	for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++) {
-		if (vwidx_updated & BIT(i)) {
-			uint8_t idx_flag;
-
-			idx_flag = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index);
-			vw_isr_list[i].vw_isr(vw_index_flag[i] ^ idx_flag, i);
-			vw_index_flag[i] = idx_flag;
-		}
-	}
-}
-
-static void espi_reset_vw_index_flags(void)
-{
-	int i;
-
-	/* reset vw_index_flag */
-	for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++)
-		vw_index_flag[i] = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index);
-}
-
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-void __ram_code espi_fw_reset_module(void)
-{
-	/*
-	 * (b/111480168): Force a reset of logic VCC domain in EC. This will
-	 * reset both LPC and eSPI blocks. The IT8320DX spec describes the
-	 * purpose of these bits as deciding whether VCC power status is used as
-	 * an internal "power good" signal. However, toggling this field while
-	 * VCC is applied results in resettig VCC domain logic in EC. This code
-	 * must reside in SRAM to prevent DMA address corruption.
-	 *
-	 * bit[7-6]:
-	 * 00b: The VCC power status is treated as power-off.
-	 * 01b: The VCC power status is treated as power-on.
-	 */
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0);
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6);
-}
-#endif
-
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal)
-{
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-	espi_fw_reset_module();
-	/*
-	 * bit[7], enable P80L function.
-	 * bit[6], accept port 80h cycle.
-	 * bit[1-0], 10b: I2EC is read-only.
-	 */
-	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
-#endif
-	/* reset vw_index_flag when espi_reset# asserted. */
-	espi_reset_vw_index_flags();
-}
-
-static int espi_get_reset_enable_config(void)
-{
-	uint8_t config;
-	const struct gpio_info *espi_rst = gpio_list + GPIO_ESPI_RESET_L;
-
-	/*
-	 * Determine if eSPI HW reset is connected to eiter B7 or D2.
-	 * bit[2-1]:
-	 * 00b: reserved.
-	 * 01b: espi_reset# is enabled on GPB7.
-	 * 10b: espi_reset# is enabled on GPD2.
-	 * 11b: reset is disabled.
-	 */
-	if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) {
-		config = IT83XX_GPIO_GCR_LPC_RST_D2;
-	} else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) {
-		config = IT83XX_GPIO_GCR_LPC_RST_B7;
-	} else {
-		config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
-		CPRINTS("EC's espi_reset pin is not enabled correctly");
-	}
-
-	return config;
-}
-
-static void espi_enable_reset(void)
-{
-	int config = espi_get_reset_enable_config();
-
-#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW
-	/*
-	 * Need to overwrite the config to ensure that eSPI HW reset is
-	 * disabled. The reset function is instead handled by FW in the
-	 * interrupt handler.
-	 */
-	config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
-	CPRINTS("EC's espi_reset pin hw auto reset is disabled");
-
-#endif
-	IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) |
-		(config << IT83XX_GPIO_GCR_LPC_RST_POS);
-
-	/* enable interrupt of EC's espi_reset pin */
-	gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L);
-	gpio_enable_interrupt(GPIO_ESPI_RESET_L);
-}
-
-/* Interrupt event of controller enables the VW channel. */
-static void espi_vw_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the VW channel.
-	 */
-	espi_configure_vw(en_vw_setting, ARRAY_SIZE(en_vw_setting));
-}
-
-/* Interrupt event of controller enables the OOB channel. */
-static void espi_oob_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the OOB channel.
-	 */
-	espi_configure_vw(en_oob_setting, ARRAY_SIZE(en_oob_setting));
-}
-
-/* Interrupt event of controller enables the flash channel. */
-static void espi_flash_en_asserted(uint8_t evt)
-{
-	/*
-	 * Configure peripheral to controller virtual wire outputs after
-	 * receiving the event of controller enables the flash channel.
-	 */
-	espi_configure_vw(en_flash_setting, ARRAY_SIZE(en_flash_setting));
-}
-
-static void espi_no_isr(uint8_t evt)
-{
-	CPRINTS("espi interrupt event is ignored! (bit%d at ESGCTRL0)", evt);
-}
-
-/*
- * The ISR of espi interrupt event in array need to be matched bit order in
- * IT83XX_ESPI_ESGCTRL0 register.
- */
-static void (*espi_isr[])(uint8_t evt) = {
-	[0] = espi_no_isr,
-	[1] = espi_vw_en_asserted,
-	[2] = espi_oob_en_asserted,
-	[3] = espi_flash_en_asserted,
-	[4] = espi_no_isr,
-	[5] = espi_no_isr,
-	[6] = espi_no_isr,
-	[7] = espi_no_isr,
-};
-
-void espi_interrupt(void)
-{
-	int i;
-	/* get espi interrupt events */
-	uint8_t espi_event = IT83XX_ESPI_ESGCTRL0;
-
-	/* write-1 to clear */
-	IT83XX_ESPI_ESGCTRL0 = espi_event;
-	/* process espi interrupt events */
-	for (i = 0; i < ARRAY_SIZE(espi_isr); i++) {
-		if (espi_event & BIT(i))
-			espi_isr[i](i);
-	}
-	/*
-	 * bit7: the peripheral has received a peripheral posted/completion.
-	 * This bit indicates the peripheral has received a packet from eSPI
-	 * peripheral channel. We can check cycle type (bit[3-0] at ESPCTRL0)
-	 * and make corresponding modification if needed.
-	 */
-	if (IT83XX_ESPI_ESPCTRL0 & ESPI_INTERRUPT_EVENT_PUT_PC) {
-		/* write-1-clear to release PC_FREE */
-		IT83XX_ESPI_ESPCTRL0 = ESPI_INTERRUPT_EVENT_PUT_PC;
-		CPRINTS("A packet from peripheral channel is ignored!");
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_ESPI);
-}
-
-#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
-/* Enable/Disable eSPI pad */
-void espi_enable_pad(int enable)
-{
-	if (enable)
-		/* Enable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 &= ~BIT(6);
-	else
-		/* Disable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 |= BIT(6);
-}
-#endif
-
-void espi_init(void)
-{
-	/*
-	 * bit[2-0], the maximum frequency of operation supported by peripheral:
-	 * 000b: 20MHz
-	 * 001b: 25MHz
-	 * 010b: 33MHz
-	 * 011b: 50MHz
-	 * 100b: 66MHz
-	 */
-#ifdef IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE
-	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2);
-#endif
-	/* reset vw_index_flag at initialization */
-	espi_reset_vw_index_flags();
-
-	/*
-	 * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH
-	 * register and WRST#.
-	 */
-	IT83XX_GCTRL_RSTS &= ~BIT(3);
-	task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
-	/* bit7: VW interrupt enable */
-	IT83XX_ESPI_VWCTRL0 |= BIT(7);
-	task_enable_irq(IT83XX_IRQ_ESPI_VW);
-
-	/* bit7: eSPI interrupt enable */
-	IT83XX_ESPI_ESGCTRL1 |= BIT(7);
-	/* bit4: eSPI to WUC enable */
-	IT83XX_ESPI_ESGCTRL2 |= BIT(4);
-	task_enable_irq(IT83XX_IRQ_ESPI);
-
-	/* enable interrupt and reset from eSPI_reset# */
-	espi_enable_reset();
-}
diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c
deleted file mode 100644
index adb3985025..0000000000
--- a/chip/it83xx/fan.c
+++ /dev/null
@@ -1,478 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fan control module. */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer_chip.h"
-#include "math_util.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define TACH_EC_FREQ                8000000
-#define FAN_CTRL_BASED_MS           10
-#define FAN_CTRL_INTERVAL_MAX_MS    60
-
-/* The sampling rate (fs) is FreqEC / 128 */
-#define TACH_DATA_VALID_TIMEOUT_MS  (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
-
-/*
- * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P)
- * n denotes 1 or 2.
- * P denotes the numbers of square pulses per revolution.
- * And {FnTMRR, FnTLRR} = 0000h denotes Fan Speed is zero.
- * The sampling rate (fs) is FreqEC / 128.
- */
-/* pulse, the numbers of square pulses per revolution. */
-#define TACH0_TO_RPM(pulse, raw) (60 * TACH_EC_FREQ / 128 / pulse / raw)
-#define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2))
-
-enum fan_output_s {
-	FAN_DUTY_I  = 0x01,
-	FAN_DUTY_R  = 0x02,
-	FAN_DUTY_OV = 0x03,
-	FAN_DUTY_DONE = 0x04,
-};
-
-struct fan_info {
-	unsigned int    flags;
-	int             fan_mode;
-	int             fan_p;
-	int             rpm_target;
-	int             rpm_actual;
-	int             tach_valid_ms;
-	int             rpm_re;
-	int             fan_ms;
-	int             fan_ms_idx;
-	int             startup_duty;
-	enum fan_status fan_sts;
-	int             enabled;
-};
-static struct fan_info fan_info_data[TACH_CH_COUNT];
-
-static enum tach_ch_sel tach_bind(int ch)
-{
-	return fan_tach[pwm_channels[ch].channel].ch_tach;
-}
-
-static void fan_set_interval(int ch)
-{
-	int diff, fan_ms;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	diff = ABS(fan_info_data[tach_ch].rpm_target -
-		fan_info_data[tach_ch].rpm_actual) / 100;
-
-	fan_ms = FAN_CTRL_INTERVAL_MAX_MS;
-
-	fan_ms -= diff;
-	if (fan_ms < FAN_CTRL_BASED_MS)
-		fan_ms = FAN_CTRL_BASED_MS;
-
-	fan_info_data[tach_ch].fan_ms = fan_ms;
-}
-
-static void fan_init_start(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_set_duty(ch, fan_info_data[tach_ch].startup_duty);
-}
-
-static int fan_all_disabled(void)
-{
-	int fan, all_disabled = 0;
-
-	for (fan = 0; fan < fan_get_count(); fan++) {
-		if (!fan_get_enabled(FAN_CH(fan)))
-			all_disabled++;
-	}
-
-	if (all_disabled >= fan_get_count())
-		return 1;
-
-	return 0;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	/* enable */
-	if (enabled) {
-		if (tach_ch < TACH_CH_COUNT)
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING;
-
-		disable_sleep(SLEEP_MASK_FAN);
-		/* enable timer interrupt for fan control */
-		ext_timer_start(FAN_CTRL_EXT_TIMER, 1);
-	/* disable */
-	} else {
-		fan_set_duty(ch, 0);
-
-		if (tach_ch < TACH_CH_COUNT) {
-			fan_info_data[tach_ch].rpm_actual = 0;
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED;
-		}
-	}
-
-	/* on/off */
-	if (tach_ch < TACH_CH_COUNT) {
-		fan_info_data[tach_ch].enabled = enabled;
-		fan_info_data[tach_ch].tach_valid_ms = 0;
-	}
-
-	pwm_enable(ch, enabled);
-
-	if (!enabled) {
-		/* disable timer interrupt if all fan off. */
-		if (fan_all_disabled()) {
-			ext_timer_stop(FAN_CTRL_EXT_TIMER, 1);
-			enable_sleep(SLEEP_MASK_FAN);
-		}
-	}
-}
-
-int fan_get_enabled(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return pwm_get_enabled(ch) && fan_info_data[tach_ch].enabled;
-	else
-		return 0;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	pwm_set_duty(ch, percent);
-}
-
-int fan_get_duty(int ch)
-{
-	return pwm_get_duty(ch);
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].fan_mode;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].fan_mode = rpm_mode;
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].rpm_actual;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-int fan_get_rpm_target(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].rpm_target;
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-test_mockable void fan_set_rpm_target(int ch, int rpm)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].rpm_target = rpm;
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		return fan_info_data[tach_ch].fan_sts;
-	else
-		return FAN_STATUS_STOPPED;
-}
-
-/**
- * Return non-zero if fan is enabled but stalled.
- */
-int fan_is_stalled(int ch)
-{
-	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) ||
-		fan_get_rpm_target(ch) == 0 ||
-		!fan_get_duty(ch))
-		return 0;
-
-	/* Check for stall condition */
-	return fan_get_status(ch) == FAN_STATUS_STOPPED;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	if (tach_ch < TACH_CH_COUNT)
-		fan_info_data[tach_ch].flags = flags;
-}
-
-static void fan_ctrl(int ch)
-{
-	int status = -1, adjust = 0;
-	int rpm_actual, rpm_target, rpm_re, duty;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS;
-	if (fan_info_data[tach_ch].fan_ms_idx >
-		fan_info_data[tach_ch].fan_ms) {
-		fan_info_data[tach_ch].fan_ms_idx = 0x00;
-		adjust = 1;
-	}
-
-	if (adjust) {
-		/* get current pwm output duty */
-		duty = fan_get_duty(ch);
-
-		/* rpm mode */
-		if (fan_info_data[tach_ch].fan_mode) {
-			rpm_actual = fan_info_data[tach_ch].rpm_actual;
-			rpm_target = fan_info_data[tach_ch].rpm_target;
-			rpm_re = fan_info_data[tach_ch].rpm_re;
-
-			if (rpm_actual < (rpm_target - rpm_re)) {
-				if (duty == 100) {
-					status = FAN_DUTY_OV;
-				} else {
-					if (duty == 0)
-						fan_init_start(ch);
-
-					pwm_duty_inc(ch);
-					status = FAN_DUTY_I;
-				}
-			} else if (rpm_actual > (rpm_target + rpm_re)) {
-				if (duty == 0) {
-					status = FAN_DUTY_OV;
-				} else {
-					pwm_duty_reduce(ch);
-					status = FAN_DUTY_R;
-				}
-			} else {
-				status = FAN_DUTY_DONE;
-			}
-		} else {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED;
-		}
-
-		if (status == FAN_DUTY_DONE) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED;
-		} else if ((status == FAN_DUTY_I) || (status == FAN_DUTY_R)) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING;
-		} else if (status == FAN_DUTY_OV) {
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_FRUSTRATED;
-
-			if (!fan_info_data[tach_ch].rpm_actual && duty)
-				fan_info_data[tach_ch].fan_sts =
-					FAN_STATUS_STOPPED;
-		}
-	}
-}
-
-static int tach_ch_valid(enum tach_ch_sel tach_ch)
-{
-	int valid = 0;
-
-	switch (tach_ch) {
-	case TACH_CH_TACH0A:
-		if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x08)
-			valid = 1;
-		break;
-	case TACH_CH_TACH1A:
-		if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x02)
-			valid = 1;
-		break;
-	case TACH_CH_TACH0B:
-		if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x0C)
-			valid = 1;
-		break;
-	case TACH_CH_TACH1B:
-		if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x03)
-			valid = 1;
-		break;
-	default:
-		break;
-	}
-
-	return valid;
-}
-
-static int get_tach0_rpm(int fan_p)
-{
-	uint16_t rpm;
-
-	/* TACH0A / TACH0B data is valid */
-	if (IT83XX_PWM_TSWCTRL & 0x08) {
-		rpm = (IT83XX_PWM_F1TMRR << 8) | IT83XX_PWM_F1TLRR;
-
-		if (rpm)
-			rpm = TACH0_TO_RPM(fan_p, rpm);
-
-		/* W/C */
-		IT83XX_PWM_TSWCTRL |= 0x08;
-		return rpm;
-	}
-	return -1;
-}
-
-static int get_tach1_rpm(int fan_p)
-{
-	uint16_t rpm;
-
-	/* TACH1A / TACH1B data is valid */
-	if (IT83XX_PWM_TSWCTRL & 0x02) {
-		rpm = (IT83XX_PWM_F2TMRR << 8) | IT83XX_PWM_F2TLRR;
-
-		if (rpm)
-			rpm = TACH1_TO_RPM(fan_p, rpm);
-
-		/* W/C */
-		IT83XX_PWM_TSWCTRL |= 0x02;
-		return rpm;
-	}
-	return -1;
-}
-
-static void proc_tach(int ch)
-{
-	int t_rpm;
-	enum tach_ch_sel tach_ch;
-
-	tach_ch = tach_bind(ch);
-
-	/* tachometer data valid */
-	if (tach_ch_valid(tach_ch)) {
-		if ((tach_ch == TACH_CH_TACH0A) || (tach_ch == TACH_CH_TACH0B))
-			t_rpm = get_tach0_rpm(fan_info_data[tach_ch].fan_p);
-		else
-			t_rpm = get_tach1_rpm(fan_info_data[tach_ch].fan_p);
-
-		fan_info_data[tach_ch].rpm_actual = t_rpm;
-		fan_set_interval(ch);
-		fan_info_data[tach_ch].tach_valid_ms = 0;
-	} else {
-		fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS;
-		if (fan_info_data[tach_ch].tach_valid_ms >
-			TACH_DATA_VALID_TIMEOUT_MS)
-			fan_info_data[tach_ch].rpm_actual = 0;
-	}
-}
-
-void fan_ext_timer_interrupt(void)
-{
-	int fan;
-
-	task_clear_pending_irq(et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq);
-
-	for (fan = 0; fan < fan_get_count(); fan++) {
-		if (fan_get_enabled(FAN_CH(fan))) {
-			proc_tach(FAN_CH(fan));
-			fan_ctrl(FAN_CH(fan));
-		}
-	}
-}
-
-static void fan_init(void)
-{
-	int ch, rpm_re, fan_p, s_duty;
-	enum tach_ch_sel tach_ch;
-
-	for (ch = 0; ch < fan_get_count(); ch++) {
-
-		rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re;
-		fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p;
-		s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty;
-		tach_ch = tach_bind(FAN_CH(ch));
-
-		if (tach_ch < TACH_CH_COUNT) {
-
-			if (tach_ch == TACH_CH_TACH0B) {
-				/* GPJ2 will select TACH0B as its alt. */
-				IT83XX_GPIO_GRC5 |= 0x01;
-				/* bit2, to select TACH0B */
-				IT83XX_PWM_TSWCTRL |= 0x04;
-			} else if (tach_ch == TACH_CH_TACH1B) {
-				/* GPJ3 will select TACH1B as its alt. */
-				IT83XX_GPIO_GRC5 |= 0x02;
-				/* bit0, to select TACH1B */
-				IT83XX_PWM_TSWCTRL |= 0x01;
-			}
-
-			fan_info_data[tach_ch].flags = 0;
-			fan_info_data[tach_ch].fan_mode = 0;
-			fan_info_data[tach_ch].rpm_target = 0;
-			fan_info_data[tach_ch].rpm_actual = 0;
-			fan_info_data[tach_ch].tach_valid_ms = 0;
-			fan_info_data[tach_ch].fan_ms_idx = 0;
-			fan_info_data[tach_ch].enabled = 0;
-			fan_info_data[tach_ch].fan_p = fan_p;
-			fan_info_data[tach_ch].rpm_re = rpm_re;
-			fan_info_data[tach_ch].fan_ms = FAN_CTRL_BASED_MS;
-			fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED;
-			fan_info_data[tach_ch].startup_duty = s_duty;
-		}
-	}
-
-	/* init external timer for fan control */
-	ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0,
-			FAN_CTRL_BASED_MS, 1, 0);
-}
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
deleted file mode 100644
index ed02aa882f..0000000000
--- a/chip/it83xx/flash.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "flash_chip.h"
-#include "host_command.h"
-#include "intc.h"
-#include "system.h"
-#include "util.h"
-#include "watchdog.h"
-#include "registers.h"
-#include "task.h"
-#include "shared_mem.h"
-#include "uart.h"
-
-#define FLASH_DMA_START ((uint32_t) &__flash_dma_start)
-#define FLASH_DMA_CODE __attribute__((section(".flash_direct_map")))
-#define FLASH_ILM0_ADDR ((uint32_t) &__ilm0_ram_code)
-
-/* erase size of sector is 1KB or 4KB */
-#define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE
-
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-/* page program command  */
-#define FLASH_CMD_PAGE_WRITE    0x2
-/* ector erase command (erase size is 4KB) */
-#define FLASH_CMD_SECTOR_ERASE  0x20
-/* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_PAGE_WRITE
-#else
-/* Auto address increment programming */
-#define FLASH_CMD_AAI_WORD      0xAD
-/* Flash sector erase (1K bytes) command */
-#define FLASH_CMD_SECTOR_ERASE  0xD7
-/* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_AAI_WORD
-#endif
-/* Write status register */
-#define FLASH_CMD_WRSR         0x01
-/* Write disable */
-#define FLASH_CMD_WRDI         0x04
-/* Write enable */
-#define FLASH_CMD_WREN         0x06
-/* Read status register */
-#define FLASH_CMD_RS           0x05
-
-#if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32)
-#define FLASH_TEXT_START ((uint32_t) &__flash_text_start)
-/* Apply workaround of the issue (b:111808417) */
-#define IMMU_CACHE_TAG_INVALID
-/* The default tag index of immu. */
-#define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000
-/* immu cache size is 8K bytes. */
-#define IMMU_SIZE                 0x2000
-#endif
-
-static int stuck_locked;
-static int inconsistent_locked;
-static int all_protected;
-static int flash_dma_code_enabled;
-
-#define FWP_REG(bank) (bank / 8)
-#define FWP_MASK(bank) (1 << (bank % 8))
-
-enum flash_wp_interface {
-	FLASH_WP_HOST = 0x01,
-	FLASH_WP_DBGR = 0x02,
-	FLASH_WP_EC = 0x04,
-};
-
-enum flash_wp_status {
-	FLASH_WP_STATUS_PROTECT_RO = EC_FLASH_PROTECT_RO_NOW,
-	FLASH_WP_STATUS_PROTECT_ALL = EC_FLASH_PROTECT_ALL_NOW,
-};
-
-enum flash_status_mask {
-	FLASH_SR_NO_BUSY = 0,
-	/* Internal write operation is in progress */
-	FLASH_SR_BUSY = 0x01,
-	/* Device is memory Write enabled */
-	FLASH_SR_WEL = 0x02,
-
-	FLASH_SR_ALL = (FLASH_SR_BUSY | FLASH_SR_WEL),
-};
-
-enum dlm_address_view {
-	SCAR0_ILM0_DLM13   = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
-	SCAR1_ILM1_DLM11   = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
-	SCAR2_ILM2_DLM14   = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
-	SCAR3_ILM3_DLM6    = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
-	SCAR4_ILM4_DLM7    = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
-	SCAR5_ILM5_DLM8    = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
-	SCAR6_ILM6_DLM9    = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
-	SCAR7_ILM7_DLM10   = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
-	SCAR8_ILM8_DLM4    = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
-	SCAR9_ILM9_DLM5    = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
-	SCAR10_ILM10_DLM2  = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
-	SCAR11_ILM11_DLM3  = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
-	SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */
-};
-
-void FLASH_DMA_CODE dma_reset_immu(int fill_immu)
-{
-	/* Immu tag sram reset */
-	IT83XX_GCTRL_MCCR |= 0x10;
-	/* Make sure the immu(dynamic cache) is reset */
-	data_serialization_barrier();
-
-	IT83XX_GCTRL_MCCR &= ~0x10;
-	data_serialization_barrier();
-
-#ifdef IMMU_CACHE_TAG_INVALID
-	/*
-	 * Workaround for (b:111808417):
-	 * After immu reset, we will fill the immu cache with 8KB data
-	 * that are outside address 0x7e000 ~ 0x7ffff.
-	 * When CPU tries to fetch contents from address 0x7e000 ~ 0x7ffff,
-	 * immu will re-fetch the missing contents inside 0x7e000 ~ 0x7ffff.
-	 */
-	if (fill_immu) {
-		volatile int immu __unused;
-		const uint32_t *ptr = (uint32_t *)FLASH_TEXT_START;
-		int i = 0;
-
-		while (i < IMMU_SIZE) {
-			immu = *ptr++;
-			i += sizeof(*ptr);
-		}
-	}
-#endif
-}
-
-void FLASH_DMA_CODE dma_flash_follow_mode(void)
-{
-	/*
-	 * ECINDAR3-0 are EC-indirect memory address registers.
-	 *
-	 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register,
-	 * and set high nibble as 0x4 to select internal flash.
-	 */
-	IT83XX_SMFI_ECINDAR3 = (EC_INDIRECT_READ_INTERNAL_FLASH | 0xf);
-	/* Set FSCE# as high level by writing 0 to address xfff_fe00h */
-	IT83XX_SMFI_ECINDAR2 = 0xFF;
-	IT83XX_SMFI_ECINDAR1 = 0xFE;
-	IT83XX_SMFI_ECINDAR0 = 0x00;
-	/* EC-indirect memory data register */
-	IT83XX_SMFI_ECINDDR = 0x00;
-}
-
-void FLASH_DMA_CODE dma_flash_follow_mode_exit(void)
-{
-	/* Exit follow mode, and keep the setting of selecting internal flash */
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	IT83XX_SMFI_ECINDAR2 = 0x00;
-}
-
-void FLASH_DMA_CODE dma_flash_fsce_high(void)
-{
-	/* FSCE# high level */
-	IT83XX_SMFI_ECINDAR1 = 0xFE;
-	IT83XX_SMFI_ECINDDR = 0x00;
-}
-
-uint8_t FLASH_DMA_CODE dma_flash_read_dat(void)
-{
-	/* Read data from FMISO */
-	return IT83XX_SMFI_ECINDDR;
-}
-
-void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata)
-{
-	/* Write data to FMOSI */
-	IT83XX_SMFI_ECINDDR = wdata;
-}
-
-void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
-					int rlen, uint8_t *rbuf, int cmd_end)
-{
-	int i;
-
-	/*  FSCE# with low level */
-	IT83XX_SMFI_ECINDAR1 = 0xFD;
-	/* Write data to FMOSI */
-	for (i = 0; i < wlen; i++)
-		IT83XX_SMFI_ECINDDR = wbuf[i];
-	/* Read data from FMISO */
-	for (i = 0; i < rlen; i++)
-		rbuf[i] = IT83XX_SMFI_ECINDDR;
-
-	/* FSCE# high level if transaction done */
-	if (cmd_end)
-		dma_flash_fsce_high();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
-						enum flash_status_mask target)
-{
-	uint8_t status[1];
-	uint8_t cmd_rs[] = {FLASH_CMD_RS};
-
-	/*
-	 * We prefer no timeout here. We can always get the status
-	 * we want, or wait for watchdog triggered to check
-	 * e-flash's status instead of breaking loop.
-	 * This will avoid fetching unknown instruction from e-flash
-	 * and causing exception.
-	 */
-	while (1) {
-		/* read status */
-		dma_flash_transaction(sizeof(cmd_rs), cmd_rs, 1, status, 1);
-		/* only bit[1:0] valid */
-		if ((status[0] & mask) == target)
-			break;
-	}
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
-{
-	uint8_t cmd_we[] = {FLASH_CMD_WREN};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send write enable command */
-	dma_flash_transaction(sizeof(cmd_we), cmd_we, 0, NULL, 1);
-	/* read status and make sure busy bit cleared and write enabled. */
-	dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
-{
-	uint8_t cmd_wd[] = {FLASH_CMD_WRDI};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send write disable command */
-	dma_flash_transaction(sizeof(cmd_wd), cmd_wd, 0, NULL, 1);
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_NO_BUSY);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
-{
-	uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send erase command */
-	dma_flash_transaction(sizeof(cmd_erase), cmd_erase, 0, NULL, 1);
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
-{
-	int i;
-	uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
-
-	/* enter EC-indirect follow mode */
-	dma_flash_follow_mode();
-	/* send flash write command (aai word or page program) */
-	dma_flash_transaction(sizeof(flash_write), flash_write, 0, NULL, 0);
-#ifdef IT83XX_CHIP_FLASH_IS_KGD
-	for (i = 0; i < wlen; i++) {
-		/* send data byte */
-		dma_flash_write_dat(wbuf[i]);
-
-		/*
-		 * we want to restart the write sequence every IDEAL_SIZE
-		 * chunk worth of data.
-		 */
-		if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) {
-			uint8_t w_en[] = {FLASH_CMD_WREN};
-
-			dma_flash_fsce_high();
-			/* make sure busy bit cleared. */
-			dma_flash_cmd_read_status(FLASH_SR_BUSY,
-							FLASH_SR_NO_BUSY);
-			/* send write enable command */
-			dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1);
-			/* make sure busy bit cleared and write enabled. */
-			dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
-			/* re-send write command */
-			flash_write[1] = (addr >> 16) & 0xff;
-			flash_write[2] = (addr >> 8) & 0xff;
-			flash_write[3] = addr & 0xff;
-			dma_flash_transaction(sizeof(flash_write), flash_write,
-				0, NULL, 0);
-		}
-	}
-	dma_flash_fsce_high();
-	/* make sure busy bit cleared. */
-	dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-#else
-	for (i = 0; i < wlen; i += 2) {
-		dma_flash_write_dat(wbuf[i]);
-		dma_flash_write_dat(wbuf[i + 1]);
-		dma_flash_fsce_high();
-		/* make sure busy bit cleared. */
-		dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
-		/* resend aai word command without address field */
-		if ((i + 2) < wlen)
-			dma_flash_transaction(1, flash_write, 0, NULL, 0);
-	}
-#endif
-	/* exit EC-indirect follow mode */
-	dma_flash_follow_mode_exit();
-}
-
-uint8_t FLASH_DMA_CODE dma_flash_indirect_fast_read(int addr)
-{
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	IT83XX_SMFI_ECINDAR2 = (addr >> 16) & 0xFF;
-	IT83XX_SMFI_ECINDAR1 = (addr >> 8) & 0xFF;
-	IT83XX_SMFI_ECINDAR0 = (addr & 0xFF);
-
-	return IT83XX_SMFI_ECINDDR;
-}
-
-int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data)
-{
-	int i;
-	uint8_t *wbuf = (uint8_t *)data;
-	uint8_t *flash = (uint8_t *)addr;
-
-	/* verify for erase */
-	if (data == NULL) {
-		for (i = 0; i < size; i++) {
-			if (flash[i] != 0xFF)
-				return EC_ERROR_UNKNOWN;
-		}
-	/* verify for write */
-	} else {
-		for (i = 0; i < size; i++) {
-			if (flash[i] != wbuf[i])
-				return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-void FLASH_DMA_CODE dma_flash_write(int addr, int wlen, const char *wbuf)
-{
-	dma_flash_cmd_write_enable();
-	dma_flash_cmd_write(addr, wlen, (uint8_t *)wbuf);
-	dma_flash_cmd_write_disable();
-}
-
-void FLASH_DMA_CODE dma_flash_erase(int addr, int cmd)
-{
-	dma_flash_cmd_write_enable();
-	dma_flash_cmd_erase(addr, cmd);
-	dma_flash_cmd_write_disable();
-}
-
-static enum flash_wp_status flash_check_wp(void)
-{
-	enum flash_wp_status wp_status;
-	int all_bank_count, bank;
-
-	all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE;
-
-	for (bank = 0; bank < all_bank_count; bank++) {
-		if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank)))
-			break;
-	}
-
-	if (bank == WP_BANK_COUNT)
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == (WP_BANK_COUNT + PSTATE_BANK_COUNT))
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == all_bank_count)
-		wp_status = FLASH_WP_STATUS_PROTECT_ALL;
-	else
-		wp_status = 0;
-
-	return wp_status;
-}
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void flash_protect_banks(int start_bank,
-				int bank_count,
-				enum flash_wp_interface wp_if)
-{
-	int bank;
-
-	for (bank = start_bank; bank < start_bank + bank_count; bank++) {
-		if (wp_if & FLASH_WP_EC)
-			IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_HOST)
-			IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_DBGR)
-			IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank);
-	}
-}
-
-int FLASH_DMA_CODE crec_flash_physical_read(int offset, int size, char *data)
-{
-	int i;
-
-	for (i = 0; i < size; i++) {
-		data[i] = dma_flash_indirect_fast_read(offset);
-		offset++;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int FLASH_DMA_CODE crec_flash_physical_write(int offset, int size,
-					     const char *data)
-{
-	int ret = EC_ERROR_UNKNOWN;
-
-	if (flash_dma_code_enabled == 0)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	watchdog_reload();
-
-	/*
-	 * CPU can't fetch instruction from flash while use
-	 * EC-indirect follow mode to access flash, interrupts need to be
-	 * disabled.
-	 */
-	interrupt_disable();
-
-	dma_flash_write(offset, size, data);
-#ifdef IMMU_CACHE_TAG_INVALID
-	dma_reset_immu((offset + size) >= IMMU_TAG_INDEX_BY_DEFAULT);
-#else
-	dma_reset_immu(0);
-#endif
-	/*
-	 * Internal flash of N8 or RISC-V core is ILM(Instruction Local Memory)
-	 * mapped, but RISC-V's ILM base address is 0x80000000.
-	 *
-	 * Ensure that we will get the ILM address of a flash offset.
-	 */
-	offset |= CONFIG_MAPPED_STORAGE_BASE;
-	ret = dma_flash_verify(offset, size, data);
-
-	interrupt_enable();
-
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int FLASH_DMA_CODE crec_flash_physical_erase(int offset, int size)
-{
-	int v_size = size, v_addr = offset, ret = EC_ERROR_UNKNOWN;
-
-	if (flash_dma_code_enabled == 0)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * CPU can't fetch instruction from flash while use
-	 * EC-indirect follow mode to access flash, interrupts need to be
-	 * disabled.
-	 */
-	interrupt_disable();
-
-	/* Always use sector erase command (1K or 4K bytes) */
-	for (; size > 0; size -= FLASH_SECTOR_ERASE_SIZE) {
-		dma_flash_erase(offset, FLASH_CMD_SECTOR_ERASE);
-		offset += FLASH_SECTOR_ERASE_SIZE;
-		/*
-		 * If requested erase size is too large at one time on KGD
-		 * flash, we need to reload watchdog to prevent the reset.
-		 */
-		if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD) && (size > 0x10000))
-			watchdog_reload();
-		/*
-		 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command
-		 * during erasing.
-		 */
-#ifdef IT83XX_IRQ_SPI_PERIPHERAL
-		if (IS_ENABLED(CONFIG_SPI) &&
-		    IS_ENABLED(HAS_TASK_HOSTCMD) &&
-		    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
-			if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI)
-				task_trigger_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-		}
-#endif
-	}
-#ifdef IMMU_CACHE_TAG_INVALID
-	dma_reset_immu((v_addr + v_size) >= IMMU_TAG_INDEX_BY_DEFAULT);
-#else
-	dma_reset_immu(0);
-#endif
-	/* get the ILM address of a flash offset. */
-	v_addr |= CONFIG_MAPPED_STORAGE_BASE;
-	ret = dma_flash_verify(v_addr, v_size, NULL);
-
-	interrupt_enable();
-
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank);
-}
-
-/**
- * Protect flash now.
- *
- * @param all      Protect all (=1) or just read-only and pstate (=0).
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_EC);
-		all_protected = 1;
-	} else {
-		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
-#ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
-#endif
-	}
-
-	/*
-	 * bit[0], eflash protect lock register which can only be write 1 and
-	 * only be cleared by power-on reset.
-	 */
-	IT83XX_GCTRL_EPLR |= 0x01;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	flags |= flash_check_wp();
-
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	/* Check if flash protection is in inconsistent state at pre-init */
-	if (inconsistent_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-static void flash_enable_second_ilm(void)
-{
-#ifdef CHIP_CORE_RISCV
-	/* Make sure no interrupt while enable static cache */
-	interrupt_disable();
-
-	/* Invalid ILM0 */
-	IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE;
-	IT83XX_SMFI_SCAR0H = BIT(3);
-	/* copy code to ram */
-	memcpy((void *)CHIP_RAMCODE_ILM0,
-		(const void *)FLASH_ILM0_ADDR,
-		IT83XX_ILM_BLOCK_SIZE);
-	/*
-	 * Set the logic memory address(flash code of RO/RW) in flash
-	 * by programming the register SCAR0x bit19-bit0.
-	 */
-	IT83XX_SMFI_SCAR0L = FLASH_ILM0_ADDR & GENMASK(7, 0);
-	IT83XX_SMFI_SCAR0M = (FLASH_ILM0_ADDR >> 8) & GENMASK(7, 0);
-	IT83XX_SMFI_SCAR0H = (FLASH_ILM0_ADDR >> 16) & GENMASK(2, 0);
-	if (FLASH_ILM0_ADDR & BIT(19))
-		IT83XX_SMFI_SCAR0H |= BIT(7);
-	else
-		IT83XX_SMFI_SCAR0H &= ~BIT(7);
-	/* Enable ILM 0 */
-	IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM0_ENABLE;
-
-	interrupt_enable();
-#endif
-}
-
-static void flash_code_static_dma(void)
-{
-
-	/* Make sure no interrupt while enable static DMA */
-	interrupt_disable();
-
-	/* invalid static DMA first */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM2_ENABLE;
-	IT83XX_SMFI_SCAR2H = 0x08;
-
-	/* Enable DLM 56k~60k region and than copy data into it */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE;
-	memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START,
-		IT83XX_ILM_BLOCK_SIZE);
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE;
-	/* Disable DLM 56k~60k region and be the ram code section */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_GCTRL_MCCR2 &= ~IT83XX_DLM14_ENABLE;
-
-	/*
-	 * Enable ILM
-	 * Set the logic memory address(flash code of RO/RW) in eflash
-	 * by programming the register SCARx bit19-bit0.
-	 */
-	IT83XX_SMFI_SCAR2L = FLASH_DMA_START & 0xFF;
-	IT83XX_SMFI_SCAR2M = (FLASH_DMA_START >> 8) & 0xFF;
-#ifdef IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
-	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x7;
-	if (FLASH_DMA_START & BIT(19))
-		IT83XX_SMFI_SCAR2H |= BIT(7);
-	else
-		IT83XX_SMFI_SCAR2H &= ~BIT(7);
-#else
-	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x0F;
-#endif
-	/*
-	 * Validate Direct-map SRAM function by programming
-	 * register SCARx bit20=0
-	 */
-	IT83XX_SMFI_SCAR2H &= ~0x10;
-
-	flash_dma_code_enabled = 0x01;
-
-	interrupt_enable();
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	int32_t reset_flags, prot_flags, unwanted_prot_flags;
-
-	/* By default, select internal flash for indirect fast read. */
-	IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
-	if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD))
-		IT83XX_SMFI_FLHCTRL6R |= IT83XX_SMFI_MASK_ECINDPP;
-	flash_code_static_dma();
-	/*
-	 * Enable second ilm (ILM0 of it8xxx2 series), so we can pull more code
-	 * (4kB) into static cache to save latency of fetching code from flash.
-	 */
-	flash_enable_second_ilm();
-
-	reset_flags = system_get_reset_flags();
-	prot_flags = crec_flash_get_protect();
-	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_HOST);
-		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_DBGR);
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	} else {
-		/*
-		 * Set inconsistent flag, because there is no software
-		 * reset can clear write-protect.
-		 */
-		inconsistent_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h
deleted file mode 100644
index c1262da116..0000000000
--- a/chip/it83xx/flash_chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FLASH_CHIP_H
-#define __CROS_EC_FLASH_CHIP_H
-
-/*
- * This symbol is defined in linker script and used to provide the begin
- * address of the ram code section. With this address, we can enable a ILM
- * (4K bytes static code cache) for ram code section.
- */
-extern const char __flash_dma_start;
-
-/* This symbol is the begin address of the __ilm0_ram_code section. */
-extern const char __ilm0_ram_code;
-
-/* This symbol is the begin address of the text section. */
-extern const char __flash_text_start;
-
-#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
deleted file mode 100644
index c0e2367720..0000000000
--- a/chip/it83xx/gpio.c
+++ /dev/null
@@ -1,906 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "kmsc_chip.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Data structure to define KSI/KSO GPIO mode control registers. */
-struct kbs_gpio_ctrl_t {
-	/* GPIO mode control register. */
-	volatile uint8_t *gpio_mode;
-	/* GPIO output enable register. */
-	volatile uint8_t *gpio_out;
-};
-
-static const struct kbs_gpio_ctrl_t kbs_gpio_ctrl_regs[] = {
-	/* KSI pins 7:0 */
-	{&IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN},
-	/* KSO pins 15:8 */
-	{&IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN},
-	/* KSO pins 7:0 */
-	{&IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN},
-};
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up edge
- * sense register (WUESR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUESR register.
- */
-static volatile uint8_t *wuesr(uint8_t grp)
-{
-	/*
-	 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5));
-}
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up edge
- * mode register (WUEMR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUEMR register.
- */
-static volatile uint8_t *wuemr(uint8_t grp)
-{
-	/*
-	 * From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5));
-}
-
-/**
- * Convert wake-up controller (WUC) group to the corresponding wake-up both edge
- * mode register (WUBEMR). Return pointer to the register.
- *
- * @param grp  WUC group.
- *
- * @return Pointer to corresponding WUBEMR register.
- */
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-static volatile uint8_t *wubemr(uint8_t grp)
-{
-	/*
-	 * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
-	 * the address increases by fours.
-	 */
-	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5));
-}
-#endif
-
-/*
- * Array to store the corresponding GPIO port and mask, and WUC group and mask
- * for each WKO interrupt. This allows GPIO interrupts coming in through WKO
- * to easily identify which pin caused the interrupt.
- * Note: Using designated initializers here in addition to using the array size
- * assert because many rows are purposely skipped. Not all IRQs are WKO IRQs,
- * so the IRQ index skips around. But, we still want the entire array to take
- * up the size of the total number of IRQs because the index to the array could
- * be any IRQ number.
- */
-static const struct {
-	uint8_t gpio_port;
-	uint8_t gpio_mask;
-	uint8_t wuc_group;
-	uint8_t wuc_mask;
-} gpio_irqs[] = {
-	/*     irq           gpio_port,gpio_mask,wuc_group,wuc_mask */
-	[IT83XX_IRQ_WKO20] =    {GPIO_D, BIT(0),        2, BIT(0)},
-	[IT83XX_IRQ_WKO21] =    {GPIO_D, BIT(1),        2, BIT(1)},
-	[IT83XX_IRQ_WKO22] =    {GPIO_C, BIT(4),        2, BIT(2)},
-	[IT83XX_IRQ_WKO23] =    {GPIO_C, BIT(6),        2, BIT(3)},
-	[IT83XX_IRQ_WKO24] =    {GPIO_D, BIT(2),        2, BIT(4)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO40] =    {GPIO_E, BIT(5),        4, BIT(0)},
-	[IT83XX_IRQ_WKO45] =    {GPIO_E, BIT(6),        4, BIT(5)},
-	[IT83XX_IRQ_WKO46] =    {GPIO_E, BIT(7),        4, BIT(6)},
-#endif
-	[IT83XX_IRQ_WKO50] =    {GPIO_K, BIT(0),        5, BIT(0)},
-	[IT83XX_IRQ_WKO51] =    {GPIO_K, BIT(1),        5, BIT(1)},
-	[IT83XX_IRQ_WKO52] =    {GPIO_K, BIT(2),        5, BIT(2)},
-	[IT83XX_IRQ_WKO53] =    {GPIO_K, BIT(3),        5, BIT(3)},
-	[IT83XX_IRQ_WKO54] =    {GPIO_K, BIT(4),        5, BIT(4)},
-	[IT83XX_IRQ_WKO55] =    {GPIO_K, BIT(5),        5, BIT(5)},
-	[IT83XX_IRQ_WKO56] =    {GPIO_K, BIT(6),        5, BIT(6)},
-	[IT83XX_IRQ_WKO57] =    {GPIO_K, BIT(7),        5, BIT(7)},
-	[IT83XX_IRQ_WKO60] =    {GPIO_H, BIT(0),        6, BIT(0)},
-	[IT83XX_IRQ_WKO61] =    {GPIO_H, BIT(1),        6, BIT(1)},
-	[IT83XX_IRQ_WKO62] =    {GPIO_H, BIT(2),        6, BIT(2)},
-	[IT83XX_IRQ_WKO63] =    {GPIO_H, BIT(3),        6, BIT(3)},
-	[IT83XX_IRQ_WKO64] =    {GPIO_F, BIT(4),        6, BIT(4)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(5),        6, BIT(5)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(6),        6, BIT(6)},
-	[IT83XX_IRQ_WKO67] =    {GPIO_F, BIT(7),        6, BIT(7)},
-	[IT83XX_IRQ_WKO70] =    {GPIO_E, BIT(0),        7, BIT(0)},
-	[IT83XX_IRQ_WKO71] =    {GPIO_E, BIT(1),        7, BIT(1)},
-	[IT83XX_IRQ_WKO72] =    {GPIO_E, BIT(2),        7, BIT(2)},
-	[IT83XX_IRQ_WKO73] =    {GPIO_E, BIT(3),        7, BIT(3)},
-	[IT83XX_IRQ_WKO74] =    {GPIO_I, BIT(4),        7, BIT(4)},
-	[IT83XX_IRQ_WKO75] =    {GPIO_I, BIT(5),        7, BIT(5)},
-	[IT83XX_IRQ_WKO76] =    {GPIO_I, BIT(6),        7, BIT(6)},
-	[IT83XX_IRQ_WKO77] =    {GPIO_I, BIT(7),        7, BIT(7)},
-	[IT83XX_IRQ_WKO80] =    {GPIO_A, BIT(3),        8, BIT(0)},
-	[IT83XX_IRQ_WKO81] =    {GPIO_A, BIT(4),        8, BIT(1)},
-	[IT83XX_IRQ_WKO82] =    {GPIO_A, BIT(5),        8, BIT(2)},
-	[IT83XX_IRQ_WKO83] =    {GPIO_A, BIT(6),        8, BIT(3)},
-	[IT83XX_IRQ_WKO84] =    {GPIO_B, BIT(2),        8, BIT(4)},
-	[IT83XX_IRQ_WKO85] =    {GPIO_C, BIT(0),        8, BIT(5)},
-	[IT83XX_IRQ_WKO86] =    {GPIO_C, BIT(7),        8, BIT(6)},
-	[IT83XX_IRQ_WKO87] =    {GPIO_D, BIT(7),        8, BIT(7)},
-	[IT83XX_IRQ_WKO88] =    {GPIO_H, BIT(4),        9, BIT(0)},
-	[IT83XX_IRQ_WKO89] =    {GPIO_H, BIT(5),        9, BIT(1)},
-	[IT83XX_IRQ_WKO90] =    {GPIO_H, BIT(6),        9, BIT(2)},
-	[IT83XX_IRQ_WKO91] =    {GPIO_A, BIT(0),        9, BIT(3)},
-	[IT83XX_IRQ_WKO92] =    {GPIO_A, BIT(1),        9, BIT(4)},
-	[IT83XX_IRQ_WKO93] =    {GPIO_A, BIT(2),        9, BIT(5)},
-	[IT83XX_IRQ_WKO94] =    {GPIO_B, BIT(4),        9, BIT(6)},
-	[IT83XX_IRQ_WKO95] =    {GPIO_C, BIT(2),        9, BIT(7)},
-	[IT83XX_IRQ_WKO96] =    {GPIO_F, BIT(0),        10, BIT(0)},
-	[IT83XX_IRQ_WKO97] =    {GPIO_F, BIT(1),        10, BIT(1)},
-	[IT83XX_IRQ_WKO98] =    {GPIO_F, BIT(2),        10, BIT(2)},
-	[IT83XX_IRQ_WKO99] =    {GPIO_F, BIT(3),        10, BIT(3)},
-	[IT83XX_IRQ_WKO100] =   {GPIO_A, BIT(7),        10, BIT(4)},
-	[IT83XX_IRQ_WKO101] =   {GPIO_B, BIT(0),        10, BIT(5)},
-	[IT83XX_IRQ_WKO102] =   {GPIO_B, BIT(1),        10, BIT(6)},
-	[IT83XX_IRQ_WKO103] =   {GPIO_B, BIT(3),        10, BIT(7)},
-	[IT83XX_IRQ_WKO104] =   {GPIO_B, BIT(5),        11, BIT(0)},
-	[IT83XX_IRQ_WKO105] =   {GPIO_B, BIT(6),        11, BIT(1)},
-	[IT83XX_IRQ_WKO106] =   {GPIO_B, BIT(7),        11, BIT(2)},
-	[IT83XX_IRQ_WKO107] =   {GPIO_C, BIT(1),        11, BIT(3)},
-	[IT83XX_IRQ_WKO108] =   {GPIO_C, BIT(3),        11, BIT(4)},
-	[IT83XX_IRQ_WKO109] =   {GPIO_C, BIT(5),        11, BIT(5)},
-	[IT83XX_IRQ_WKO110] =   {GPIO_D, BIT(3),        11, BIT(6)},
-	[IT83XX_IRQ_WKO111] =   {GPIO_D, BIT(4),        11, BIT(7)},
-	[IT83XX_IRQ_WKO112] =   {GPIO_D, BIT(5),        12, BIT(0)},
-	[IT83XX_IRQ_WKO113] =   {GPIO_D, BIT(6),        12, BIT(1)},
-	[IT83XX_IRQ_WKO114] =   {GPIO_E, BIT(4),        12, BIT(2)},
-	[IT83XX_IRQ_WKO115] =   {GPIO_G, BIT(0),        12, BIT(3)},
-	[IT83XX_IRQ_WKO116] =   {GPIO_G, BIT(1),        12, BIT(4)},
-	[IT83XX_IRQ_WKO117] =   {GPIO_G, BIT(2),        12, BIT(5)},
-	[IT83XX_IRQ_WKO118] =   {GPIO_G, BIT(6),        12, BIT(6)},
-	[IT83XX_IRQ_WKO119] =   {GPIO_I, BIT(0),        12, BIT(7)},
-	[IT83XX_IRQ_WKO120] =   {GPIO_I, BIT(1),        13, BIT(0)},
-	[IT83XX_IRQ_WKO121] =   {GPIO_I, BIT(2),        13, BIT(1)},
-	[IT83XX_IRQ_WKO122] =   {GPIO_I, BIT(3),        13, BIT(2)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO123] =   {GPIO_G, BIT(3),        13, BIT(3)},
-	[IT83XX_IRQ_WKO124] =   {GPIO_G, BIT(4),        13, BIT(4)},
-	[IT83XX_IRQ_WKO125] =   {GPIO_G, BIT(5),        13, BIT(5)},
-	[IT83XX_IRQ_WKO126] =   {GPIO_G, BIT(7),        13, BIT(6)},
-#endif
-	[IT83XX_IRQ_WKO128] =   {GPIO_J, BIT(0),        14, BIT(0)},
-	[IT83XX_IRQ_WKO129] =   {GPIO_J, BIT(1),        14, BIT(1)},
-	[IT83XX_IRQ_WKO130] =   {GPIO_J, BIT(2),        14, BIT(2)},
-	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
-	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
-	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
-	[IT83XX_IRQ_WKO134] =   {GPIO_J, BIT(6),        14, BIT(6)},
-	[IT83XX_IRQ_WKO135] =   {GPIO_J, BIT(7),        14, BIT(7)},
-	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
-	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
-	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
-	[IT83XX_IRQ_WKO139] =   {GPIO_L, BIT(3),        15, BIT(3)},
-	[IT83XX_IRQ_WKO140] =   {GPIO_L, BIT(4),        15, BIT(4)},
-	[IT83XX_IRQ_WKO141] =   {GPIO_L, BIT(5),        15, BIT(5)},
-	[IT83XX_IRQ_WKO142] =   {GPIO_L, BIT(6),        15, BIT(6)},
-	[IT83XX_IRQ_WKO143] =   {GPIO_L, BIT(7),        15, BIT(7)},
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO144] =   {GPIO_M, BIT(0),        16, BIT(0)},
-	[IT83XX_IRQ_WKO145] =   {GPIO_M, BIT(1),        16, BIT(1)},
-	[IT83XX_IRQ_WKO146] =   {GPIO_M, BIT(2),        16, BIT(2)},
-	[IT83XX_IRQ_WKO147] =   {GPIO_M, BIT(3),        16, BIT(3)},
-	[IT83XX_IRQ_WKO148] =   {GPIO_M, BIT(4),        16, BIT(4)},
-	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
-	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
-#endif
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[IT83XX_IRQ_GPO0]   =   {GPIO_O, BIT(0),        19, BIT(0)},
-	[IT83XX_IRQ_GPO1]   =   {GPIO_O, BIT(1),        19, BIT(1)},
-	[IT83XX_IRQ_GPO2]   =   {GPIO_O, BIT(2),        19, BIT(2)},
-	[IT83XX_IRQ_GPO3]   =   {GPIO_O, BIT(3),        19, BIT(3)},
-	[IT83XX_IRQ_GPP0]   =   {GPIO_P, BIT(0),        20, BIT(0)},
-	[IT83XX_IRQ_GPP1]   =   {GPIO_P, BIT(1),        20, BIT(1)},
-	[IT83XX_IRQ_GPP2]   =   {GPIO_P, BIT(2),        20, BIT(2)},
-	[IT83XX_IRQ_GPP3]   =   {GPIO_P, BIT(3),        20, BIT(3)},
-	[IT83XX_IRQ_GPP4]   =   {GPIO_P, BIT(4),        20, BIT(4)},
-	[IT83XX_IRQ_GPP5]   =   {GPIO_P, BIT(5),        20, BIT(5)},
-	[IT83XX_IRQ_GPP6]   =   {GPIO_P, BIT(6),        20, BIT(6)},
-	[IT83XX_IRQ_GPQ0]   =   {GPIO_Q, BIT(0),        21, BIT(0)},
-	[IT83XX_IRQ_GPQ1]   =   {GPIO_Q, BIT(1),        21, BIT(1)},
-	[IT83XX_IRQ_GPQ2]   =   {GPIO_Q, BIT(2),        21, BIT(2)},
-	[IT83XX_IRQ_GPQ3]   =   {GPIO_Q, BIT(3),        21, BIT(3)},
-	[IT83XX_IRQ_GPQ4]   =   {GPIO_Q, BIT(4),        21, BIT(4)},
-	[IT83XX_IRQ_GPQ5]   =   {GPIO_Q, BIT(5),        21, BIT(5)},
-	[IT83XX_IRQ_GPR0]   =   {GPIO_R, BIT(0),        22, BIT(0)},
-	[IT83XX_IRQ_GPR1]   =   {GPIO_R, BIT(1),        22, BIT(1)},
-	[IT83XX_IRQ_GPR2]   =   {GPIO_R, BIT(2),        22, BIT(2)},
-	[IT83XX_IRQ_GPR3]   =   {GPIO_R, BIT(3),        22, BIT(3)},
-	[IT83XX_IRQ_GPR4]   =   {GPIO_R, BIT(4),        22, BIT(4)},
-	[IT83XX_IRQ_GPR5]   =   {GPIO_R, BIT(5),        22, BIT(5)},
-#endif
-	[IT83XX_IRQ_COUNT]  =   {     0,      0,         0,      0},
-};
-BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1);
-
-/**
- * Given a GPIO port and mask, find the corresponding WKO interrupt number.
- *
- * @param port  GPIO port
- * @param mask  GPIO mask
- *
- * @return IRQ for the WKO interrupt on the corresponding input pin.
- */
-static int gpio_to_irq(uint8_t port, uint8_t mask)
-{
-	int i;
-
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		if (gpio_irqs[i].gpio_port == port &&
-				gpio_irqs[i].gpio_mask == mask)
-			return i;
-	}
-
-	return -1;
-}
-
-struct gpio_1p8v_t {
-	volatile uint8_t *reg;
-	uint8_t sel;
-};
-
-static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
-#ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
-	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [4] = {&IT83XX_GPIO_GRC24, BIT(2)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(3)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GRC22, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(6)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(2)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
-	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR27, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(2)},
-		     [7] = {&IT83XX_GPIO_GCR33, BIT(2)} },
-	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR26, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR26, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR26, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR26, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR26, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR26, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
-	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR25, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR25, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR25, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR25, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR31, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR31, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR31, BIT(3)} },
-	[GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR32, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR32, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR32, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR32, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR32, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR32, BIT(6)} },
-#endif
-#else
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
-	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
-	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
-#endif
-};
-
-static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v)
-{
-	volatile uint8_t *reg_1p8v = gpio_1p8v_sel[port][pin].reg;
-	uint8_t sel = gpio_1p8v_sel[port][pin].sel;
-
-	if (reg_1p8v == NULL)
-		return;
-
-	if (sel_1p8v)
-		*reg_1p8v |= sel;
-	else
-		*reg_1p8v &= ~sel;
-}
-
-static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin,
-				enum gpio_alternate_func func)
-{
-	/*
-	 * If func is not ALT_FUNC_NONE, set for alternate function.
-	 * Otherwise, turn the pin into an input as it's default.
-	 */
-	if (func != GPIO_ALT_FUNC_NONE)
-		IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT |
-			GPCR_PORT_PIN_MODE_INPUT);
-	else
-		IT83XX_GPIO_CTRL(port, pin) =
-			(IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT)
-			& ~GPCR_PORT_PIN_MODE_OUTPUT;
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t pin = 0;
-
-	/* Alternate function configuration for KSI/KSO pins */
-	if (port > GPIO_PORT_COUNT) {
-		port -= GPIO_KSI;
-		/*
-		 * If func is non-negative, set for keyboard scan function.
-		 * Otherwise, turn the pin into a GPIO input.
-		 */
-		if (func >= GPIO_ALT_FUNC_DEFAULT) {
-			/* KBS mode */
-			*kbs_gpio_ctrl_regs[port].gpio_mode &= ~mask;
-		} else {
-			/* input */
-			*kbs_gpio_ctrl_regs[port].gpio_out &= ~mask;
-			/* GPIO mode */
-			*kbs_gpio_ctrl_regs[port].gpio_mode |= mask;
-		}
-		return;
-	}
-
-	/* For each bit high in the mask, set that pin to use alt. func. */
-	while (mask > 0) {
-		if (mask & 1)
-			it83xx_set_alt_func(port, pin, func);
-		pin++;
-		mask >>= 1;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return (IT83XX_GPIO_DATA_MIRROR(gpio_list[signal].port) &
-			gpio_list[signal].mask) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	/* critical section with interrupts off */
-	uint32_t int_mask = read_clear_int_mask();
-
-	if (value)
-		IT83XX_GPIO_DATA(gpio_list[signal].port) |=
-				 gpio_list[signal].mask;
-	else
-		IT83XX_GPIO_DATA(gpio_list[signal].port) &=
-				~gpio_list[signal].mask;
-	/* restore interrupts */
-	set_int_mask(int_mask);
-}
-
-void gpio_kbs_pin_gpio_mode(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t idx = port - GPIO_KSI;
-
-	/* Set GPIO mode */
-	*kbs_gpio_ctrl_regs[idx].gpio_mode |= mask;
-
-	/* Set input or output */
-	if (flags & GPIO_OUTPUT) {
-		/*
-		 * Select open drain first, so that we don't glitch the signal
-		 * when changing the line to an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			/*
-			 * it83xx: need external pullup for output data high
-			 * it8xxx2: this pin is always internal pullup
-			 */
-			IT83XX_GPIO_GPOT(port) |= mask;
-		else
-			/*
-			 * it8xxx2: this pin is not internal pullup
-			 */
-			IT83XX_GPIO_GPOT(port) &= ~mask;
-
-		/* Set level before change to output. */
-		if (flags & GPIO_HIGH)
-			IT83XX_GPIO_DATA(port) |= mask;
-		else if (flags & GPIO_LOW)
-			IT83XX_GPIO_DATA(port) &= ~mask;
-		*kbs_gpio_ctrl_regs[idx].gpio_out |= mask;
-	} else {
-		*kbs_gpio_ctrl_regs[idx].gpio_out &= ~mask;
-		if (flags & GPIO_PULL_UP)
-			IT83XX_GPIO_GPOT(port) |= mask;
-		else
-			/* No internal pullup and pulldown */
-			IT83XX_GPIO_GPOT(port) &= ~mask;
-	}
-}
-
-#ifndef IT83XX_GPIO_INT_FLEXIBLE
-/* Returns true when the falling trigger bit actually mean both trigger. */
-static int group_falling_is_both(const int group)
-{
-	return group == 7 || group == 10 || group == 12;
-}
-
-static const char *get_gpio_string(const int port, const int mask)
-{
-	static char buffer[3];
-	int i;
-
-	buffer[0] = port - GPIO_A + 'A';
-	buffer[1] = '!';
-
-	for (i = 0; i < 8; ++i) {
-		if (mask & BIT(i)) {
-			buffer[1] = i + '0';
-			break;
-		}
-	}
-	return buffer;
-}
-#endif /* IT83XX_GPIO_INT_FLEXIBLE */
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t pin = 0;
-	uint32_t mask_copy = mask;
-
-	/* Set GPIO mode for KSI/KSO pins */
-	if (port > GPIO_PORT_COUNT) {
-		gpio_kbs_pin_gpio_mode(port, mask, flags);
-		return;
-	}
-
-	/*
-	 * Select open drain first, so that we don't glitch the signal
-	 * when changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		IT83XX_GPIO_GPOT(port) |= mask;
-	else
-		IT83XX_GPIO_GPOT(port) &= ~mask;
-
-	/* If output, set level before changing type to an output. */
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			IT83XX_GPIO_DATA(port) |= mask;
-		else if (flags & GPIO_LOW)
-			IT83XX_GPIO_DATA(port) &= ~mask;
-	}
-
-	/* For each bit high in the mask, set input/output and pullup/down. */
-	while (mask_copy > 0) {
-		if (mask_copy & 1) {
-			/* Set input or output. */
-			if (flags & GPIO_OUTPUT)
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_OUTPUT) &
-				~GPCR_PORT_PIN_MODE_INPUT;
-			else
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_INPUT) &
-				~GPCR_PORT_PIN_MODE_OUTPUT;
-
-			/* Handle pullup / pulldown */
-			if (flags & GPIO_PULL_UP) {
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLUP) &
-				~GPCR_PORT_PIN_MODE_PULLDOWN;
-			} else if (flags & GPIO_PULL_DOWN) {
-				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLDOWN) &
-				~GPCR_PORT_PIN_MODE_PULLUP;
-			} else {
-				/* No pull up/down */
-				IT83XX_GPIO_CTRL(port, pin) &=
-					~(GPCR_PORT_PIN_MODE_PULLUP |
-					  GPCR_PORT_PIN_MODE_PULLDOWN);
-			}
-
-			/* To select 1.8v or 3.3v support. */
-			gpio_1p8v_3p3v_sel_by_pin(port, pin,
-						(flags & GPIO_SEL_1P8V));
-		}
-
-		pin++;
-		mask_copy >>= 1;
-	}
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) {
-		int irq, wuc_group, wuc_mask;
-		irq = gpio_to_irq(port, mask);
-		wuc_group = gpio_irqs[irq].wuc_group;
-		wuc_mask = gpio_irqs[irq].wuc_mask;
-
-		/*
-		 * Set both edges interrupt.
-		 * The WUBEMR register is valid on IT8320 DX version.
-		 * And the setting (falling or rising edge) of WUEMR register is
-		 * invalid if this mode is set.
-		 */
-#ifdef IT83XX_GPIO_INT_FLEXIBLE
-		if ((flags & GPIO_INT_BOTH) == GPIO_INT_BOTH)
-			*(wubemr(wuc_group)) |= wuc_mask;
-		else
-			*(wubemr(wuc_group)) &= ~wuc_mask;
-#endif
-
-		if (flags & GPIO_INT_F_FALLING) {
-#ifndef IT83XX_GPIO_INT_FLEXIBLE
-			if (!!(flags & GPIO_INT_F_RISING) !=
-			    group_falling_is_both(wuc_group)) {
-				ccprintf("!!Fix GPIO %s interrupt config!!\n",
-					 get_gpio_string(port, mask));
-			}
-#endif
-			*(wuemr(wuc_group)) |= wuc_mask;
-		} else {
-			*(wuemr(wuc_group)) &= ~wuc_mask;
-		}
-		/*
-		 * Always write 1 to clear the WUC status register after
-		 * modifying edge mode selection register (WUBEMR and WUEMR).
-		 */
-		*(wuesr(wuc_group)) = wuc_mask;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-	else
-		task_enable_irq(irq);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-	else
-		task_disable_irq(irq);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
-
-	if (irq == -1)
-		return EC_ERROR_UNKNOWN;
-
-	*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
-	task_clear_pending_irq(irq);
-	return EC_SUCCESS;
-}
-
-/* To prevent cc pins leakage, disables integrated cc module. */
-void it83xx_disable_cc_module(int port)
-{
-	/* Power down all CC, and disable CC voltage detector */
-	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC;
-#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-	IT83XX_USBPD_CCCSR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-	IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-#endif
-	/*
-	 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
-	 * disconnect CC 5.1K to GND
-	 */
-	IT83XX_USBPD_CCCSR(port) |= (USBPD_REG_MASK_CC2_DISCONNECT |
-				     USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND |
-				     USBPD_REG_MASK_CC1_DISCONNECT |
-				     USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND);
-	/* Disconnect CC 5V tolerant */
-	IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC2 |
-				     USBPD_REG_MASK_DISCONNECT_POWER_CC1);
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = system_is_reboot_warm();
-	int flags;
-	int i;
-
-	IT83XX_GPIO_GCR = 0x06;
-
-#if !defined(CONFIG_IT83XX_VCC_1P8V) && !defined(CONFIG_IT83XX_VCC_3P3V)
-#error Please select voltage level of VCC for EC.
-#endif
-
-#if defined(CONFIG_IT83XX_VCC_1P8V) && defined(CONFIG_IT83XX_VCC_3P3V)
-#error Must select only one voltage level of VCC for EC.
-#endif
-	/* The power level of GPM6 follows VCC */
-	IT83XX_GPIO_GCR29 |= BIT(0);
-
-	/* The power level (VCC) of GPM0~6 is 1.8V */
-	if (IS_ENABLED(CONFIG_IT83XX_VCC_1P8V))
-		IT83XX_GPIO_GCR30 |= BIT(4);
-
-	/* The power level (VCC) of GPM0~6 is 3.3V */
-	if (IS_ENABLED(CONFIG_IT83XX_VCC_3P3V))
-		IT83XX_GPIO_GCR30 &= ~BIT(4);
-
-#if IT83XX_USBPD_PHY_PORT_COUNT < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
-#error "ITE pd active port count should be less than physical port count !"
-#endif
-	/*
-	 * To prevent cc pins leakage and cc pins can be used as gpio,
-	 * disable board not active ITE TCPC port cc modules.
-	 */
-	for (i = CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT;
-	     i < IT83XX_USBPD_PHY_PORT_COUNT; i++) {
-		it83xx_disable_cc_module(i);
-		/* Dis-connect 5.1K dead battery resistor to CC */
-		IT83XX_USBPD_CCPSR(i) |=
-			(USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB |
-			 USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
-	}
-
-#ifndef CONFIG_USB
-	/*
-	 * We need to enable USB's clock so we can config USB control register.
-	 * This is important for a software reset as the hardware clock may
-	 * already be disabled from the previous run.
-	 * We will disable clock to USB module in clock_module_disable() later.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_USB, 0, 0);
-	/*
-	 * Disable default pull-down of USB controller (GPH5 and GPH6) if we
-	 * don't use this module.
-	 */
-	IT83XX_USB_P0MCR &= ~USB_DP_DM_PULL_DOWN_EN;
-#endif
-
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	/* Q group pins are default GPI mode, clear alternate setting. */
-	IT83XX_VBATPC_XLPIER = 0x0;
-	/*
-	 * R group pins are default alternate output low, we clear alternate
-	 * setting (sink power switch from VBAT to VSTBY) to become GPO output
-	 * low.
-	 * NOTE: GPR0~5 pins are output low by default. It should consider
-	 *       that if output low signal effect external circuit or not,
-	 *       until we reconfig these pins in gpio.inc.
-	 */
-	IT83XX_VBATPC_BGPOPSCR = 0x0;
-#endif
-
-	/*
-	 * On IT81202 (128-pins package), the pins of GPIO group K and L aren't
-	 * bonding with pad. So we configure these pins as internal pull-down
-	 * at default to prevent leakage current due to floating.
-	 */
-	if (IS_ENABLED(IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
-		for (i = 0; i < 8; i++) {
-			IT83XX_GPIO_CTRL(GPIO_K, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-			IT83XX_GPIO_CTRL(GPIO_L, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-		}
-	}
-
-	/*
-	 * On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
-	 * floating internally. We need to enable internal pull-down for the pin
-	 * to prevent leakage current, but IT81202/IT81302 doesn't have the
-	 * capability to pull it down. We can only set it as output low,
-	 * so we enable output low for it at initialization to prevent leakage.
-	 */
-	if (IS_ENABLED(IT83XX_GPIO_H7_DEFAULT_OUTPUT_LOW)) {
-		IT83XX_GPIO_CTRL(GPIO_H, 7) = GPCR_PORT_PIN_MODE_OUTPUT;
-		IT83XX_GPIO_DATA(GPIO_H) &= ~BIT(7);
-	}
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/**
- * Handle a GPIO interrupt by calling the pins corresponding handler if
- * one exists.
- *
- * @param port		GPIO port (GPIO_*)
- * @param mask		GPIO mask
- */
-static void gpio_interrupt(int port, uint8_t mask)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT; i++, g++) {
-		if (port == g->port && (mask & g->mask)) {
-			gpio_irq_handlers[i](i);
-			return;
-		}
-	}
-}
-
-/**
- * Define one IRQ function to handle all GPIO interrupts. The IRQ determines
- * the interrupt number which was triggered, calls the master handler above,
- * and clears status registers.
- */
-static void __gpio_irq(void)
-{
-	/* Determine interrupt number. */
-	int irq = intc_get_ec_int();
-
-	/* assert failure if interrupt number is zero */
-	ASSERT(irq);
-
-#if defined(HAS_TASK_KEYSCAN) && !defined(CONFIG_KEYBOARD_NOT_RAW)
-	if (irq == IT83XX_IRQ_WKINTC) {
-		keyboard_raw_interrupt();
-		return;
-	}
-#endif
-
-#ifdef CONFIG_HOSTCMD_X86
-	if (irq == IT83XX_IRQ_WKINTAD)
-		return;
-#endif
-
-	/*
-	 * Clear the WUC status register. Note the external pin first goes
-	 * to the WUC module and is always edge triggered.
-	 */
-	*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
-
-	/*
-	 * Clear the interrupt controller  status register. Note the interrupt
-	 * controller is level triggered from the WUC status.
-	 */
-	task_clear_pending_irq(irq);
-
-	/* Run the GPIO master handler above with corresponding port/mask. */
-	gpio_interrupt(gpio_irqs[irq].gpio_port, gpio_irqs[irq].gpio_mask);
-}
-
-/* Route all WKO interrupts coming from INT#2 into __gpio_irq. */
-DECLARE_IRQ(CPU_INT_2_ALL_GPIOS, __gpio_irq, 1);
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
deleted file mode 100644
index 291751a1cb..0000000000
--- a/chip/it83xx/hwtimer.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "cpu.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * The IT839X series support combinational mode for combining specific pairs of
- * timers: 3(24-bit) and 4(32-bit) / timer 5(24-bit) and 6(32-bit) /
- * timer 7(24-bit) and 8(32-bit).
- *
- * 32-bit MHz free-running counter: We combine (bit3@IT83XX_ETWD_ETXCTRL)
- * timer 3(TIMER_L) and 4(TIMER_H) and set clock source register to 8MHz.
- * In combinational mode, the counter register(IT83XX_ETWD_ETXCNTLR) of timer 3
- * is a fixed value = 7, and observation register(IT83XX_ETWD_ETXCNTOR)
- * of timer 4 will increase one per-us.
- *
- * For example, if
- * __hw_clock_source_set() set 0 us, the counter setting registers are
- * timer 3(TIMER_L) = 0x000007 (fixed, will not change)
- * timer 4(TIMER_H) = 0xffffffff
- *
- * Note:
- * In combinational mode, the counter observation value of
- * timer 4(TIMER_H), 6, 8 will in incrementing order.
- * For the above example, the counter observation value registers will be
- * timer 3(TIMER_L) 0x0000007
- * timer 4(TIMER_H) ~0xffffffff = 0x00000000
- *
- * The following will describe timer 3 and 4's operation in combinational mode:
- * 1. When timer 3(TIMER_L) has completed each counting (per-us),
-      timer 4(TIMER_H) observation value++.
- * 2. When timer 4(TIMER_H) observation value overflows:
- *    timer 4(TIMER_H) observation value = ~counter setting register.
- * 3. Timer 4(TIMER_H) interrupt occurs.
- *
- * IT839X only supports terminal count interrupt. We need a separate
- * 8 MHz 32-bit timer to handle events.
- */
-
-#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
-
-const struct ext_timer_ctrl_t et_ctrl_regs[] = {
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
-		IT83XX_IRQ_EXT_TIMER3},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
-		IT83XX_IRQ_EXT_TIMER4},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
-		IT83XX_IRQ_EXT_TIMER5},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
-		IT83XX_IRQ_EXT_TIMER6},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
-		IT83XX_IRQ_EXT_TIMER7},
-	{&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
-		IT83XX_IRQ_EXT_TMR8},
-};
-BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT);
-
-static void free_run_timer_overflow(void)
-{
-	/*
-	 * If timer 4 (TIMER_H) counter register != 0xffffffff.
-	 * This usually happens once after sysjump, force time, and etc.
-	 * (when __hw_clock_source_set is called and param 'ts' != 0)
-	 */
-	if (IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) != 0xffffffff) {
-		/* set timer counter register */
-		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff;
-		/* bit[1], timer reset */
-		IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
-	}
-	/* w/c interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq);
-	/* timer overflow */
-	process_timers(1);
-	update_exc_start_time();
-}
-
-static void event_timer_clear_pending_isr(void)
-{
-	/* w/c interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-}
-
-uint32_t __ram_code __hw_clock_source_read(void)
-{
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-	/*
-	 * In combinational mode, the counter observation register of
-	 * timer 4(TIMER_H) will increment.
-	 */
-	return ext_observation_reg_read(FREE_EXT_TIMER_H);
-#else
-	return IT83XX_ETWD_ETXCNTOR(FREE_EXT_TIMER_H);
-#endif
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	/* counting down timer, microseconds to timer counter register */
-	IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts;
-	/* bit[1], timer reset */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t wait;
-	/* bit0, disable event timer */
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
-	/* w/c interrupt status */
-	event_timer_clear_pending_isr();
-	/* microseconds to timer counter */
-	wait = deadline - __hw_clock_source_read();
-	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) =
-		wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ?
-		EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff;
-	/* enable and re-start timer */
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03;
-	task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	uint32_t next_event_us = __hw_clock_source_read();
-
-	/* bit0, event timer is enabled */
-	if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) {
-		/* timer counter observation value to microseconds */
-		next_event_us += EVENT_TIMER_COUNT_TO_US(
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-			ext_observation_reg_read(EVENT_EXT_TIMER));
-#else
-			IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#endif
-	}
-	return next_event_us;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* stop event timer */
-	ext_timer_stop(EVENT_EXT_TIMER, 1);
-	event_timer_clear_pending_isr();
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* bit3, timer 3 and timer 4 combinational mode */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3);
-	/* init free running timer (timer 4, TIMER_H), clock source is 8mhz */
-	ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1);
-	/* 1us counter setting (timer 3, TIMER_L) */
-	ext_timer_ms(FREE_EXT_TIMER_L, EXT_PSR_8M_HZ, 1, 0, 7, 1, 1);
-	__hw_clock_source_set(start_t);
-	/* init event timer */
-	ext_timer_ms(EVENT_EXT_TIMER, EXT_PSR_8M_HZ, 0, 0, 0xffffffff, 1, 1);
-	/* returns the IRQ number of event timer */
-	return et_ctrl_regs[EVENT_EXT_TIMER].irq;
-}
-
-static void __hw_clock_source_irq(void)
-{
-	/* Determine interrupt number. */
-	int irq = intc_get_ec_int();
-
-	/* SW/HW interrupt of event timer. */
-	if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) {
-		IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff;
-		IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1);
-		event_timer_clear_pending_isr();
-		process_timers(0);
-		return;
-	}
-
-#ifdef CONFIG_WATCHDOG
-	/*
-	 * Both the external timer for the watchdog warning and the HW timer
-	 * go through this irq. So, if this interrupt was caused by watchdog
-	 * warning timer, then call that function.
-	 */
-	if (irq == et_ctrl_regs[WDT_EXT_TIMER].irq) {
-		watchdog_warning_irq();
-		return;
-	}
-#endif
-
-#ifdef CONFIG_FANS
-	if (irq == et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq) {
-		fan_ext_timer_interrupt();
-		return;
-	}
-#endif
-
-	/* Interrupt of free running timer TIMER_H. */
-	if (irq == et_ctrl_regs[FREE_EXT_TIMER_H].irq) {
-		free_run_timer_overflow();
-		return;
-	}
-
-	/*
-	 * This interrupt is used to wakeup EC from sleep mode
-	 * to complete PLL frequency change.
-	 */
-	if (irq == et_ctrl_regs[LOW_POWER_EXT_TIMER].irq) {
-		ext_timer_stop(LOW_POWER_EXT_TIMER, 1);
-		return;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
-
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-/* Number of CPU cycles in 125 us */
-#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
-uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
-{
-	uint32_t prev_mask = read_clear_int_mask();
-	uint32_t val;
-
-	asm volatile(
-		/* read observation register for the first time */
-		"lwi %0,[%1]\n\t"
-		/*
-		 * the delay time between reading the first and second
-		 * observation registers need to be greater than 0.125us and
-		 * smaller than 0.250us.
-		 */
-		".rept %2\n\t"
-		"nop\n\t"
-		".endr\n\t"
-		/* read for the second time */
-		"lwi %0,[%1]\n\t"
-		: "=&r"(val)
-		: "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)),
-			"i"(CYCLES_125NS));
-	/* restore interrupts */
-	set_int_mask(prev_mask);
-
-	return val;
-}
-#endif
-
-void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq)
-{
-	/* enable external timer n */
-	IT83XX_ETWD_ETXCTRL(ext_timer) |= 0x03;
-
-	if (en_irq) {
-		task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
-		task_enable_irq(et_ctrl_regs[ext_timer].irq);
-	}
-}
-
-void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq)
-{
-	/* disable external timer n */
-	IT83XX_ETWD_ETXCTRL(ext_timer) &= ~0x01;
-
-	if (dis_irq)
-		task_disable_irq(et_ctrl_regs[ext_timer].irq);
-}
-
-static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t count)
-{
-	uint8_t intc_mask;
-
-	/* rising-edge-triggered */
-	intc_mask = et_ctrl_regs[ext_timer].mask;
-	*et_ctrl_regs[ext_timer].mode |= intc_mask;
-	*et_ctrl_regs[ext_timer].polarity &= ~intc_mask;
-
-	/* clear interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
-
-	/* These bits control the clock input source to the exttimer 3 - 8 */
-	IT83XX_ETWD_ETXPSR(ext_timer) = ext_timer_clock;
-
-	/* The count number of external timer n. */
-	IT83XX_ETWD_ETXCNTLR(ext_timer) = count;
-
-	ext_timer_stop(ext_timer, 0);
-	if (start)
-		ext_timer_start(ext_timer, 0);
-
-	if (with_int)
-		task_enable_irq(et_ctrl_regs[ext_timer].irq);
-	else
-		task_disable_irq(et_ctrl_regs[ext_timer].irq);
-}
-
-int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw)
-{
-	uint32_t count;
-
-	if (raw) {
-		count = ms;
-	} else {
-		if (ext_timer_clock == EXT_PSR_32P768K_HZ)
-			count = MS_TO_COUNT(32768, ms);
-		else if (ext_timer_clock == EXT_PSR_1P024K_HZ)
-			count = MS_TO_COUNT(1024, ms);
-		else if (ext_timer_clock == EXT_PSR_32_HZ)
-			count = MS_TO_COUNT(32, ms);
-		else if (ext_timer_clock == EXT_PSR_8M_HZ)
-			count = 8000 * ms;
-		else
-			return -1;
-	}
-
-	if (count == 0)
-		return -3;
-
-	if (first_time_enable) {
-		ext_timer_start(ext_timer, 0);
-		ext_timer_stop(ext_timer, 0);
-	}
-
-	ext_timer_ctrl(ext_timer, ext_timer_clock, start, with_int, count);
-
-	return 0;
-}
diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h
deleted file mode 100644
index 2ccdce1d96..0000000000
--- a/chip/it83xx/hwtimer_chip.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* External timers control module for IT83xx. */
-
-#ifndef __CROS_EC_HWTIMER_CHIP_H
-#define __CROS_EC_HWTIMER_CHIP_H
-
-#define TIMER_COUNT_1US_SHIFT      3
-
-/* Microseconds to event timer counter setting register */
-#define EVENT_TIMER_US_TO_COUNT(us)  ((us) << TIMER_COUNT_1US_SHIFT)
-/* Event timer counter observation value to microseconds */
-#define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT)
-
-#define FREE_EXT_TIMER_L     EXT_TIMER_3
-#define FREE_EXT_TIMER_H     EXT_TIMER_4
-#define FAN_CTRL_EXT_TIMER   EXT_TIMER_5
-#define EVENT_EXT_TIMER      EXT_TIMER_6
-/*
- * The low power timer is used to continue system time when EC goes into low
- * power in idle task. Timer 7 is 24bit timer and configured at 32.768khz.
- * The configuration is enough for continuing system time, because periodic
- * tick event (interval is 500ms on it8xxx2) will wake EC up.
- *
- * IMPORTANT:
- * If you change low power timer to a non-24bit timer, you also have to change
- * mask of observation register in clock_sleep_mode_wakeup_isr() or EC will get
- * wrong system time after resume.
- */
-#define LOW_POWER_EXT_TIMER  EXT_TIMER_7
-#define LOW_POWER_TIMER_MASK (BIT(24) - 1)
-#define WDT_EXT_TIMER        EXT_TIMER_8
-
-enum ext_timer_clock_source {
-	EXT_PSR_32P768K_HZ = 0,
-	EXT_PSR_1P024K_HZ  = 1,
-	EXT_PSR_32_HZ      = 2,
-	EXT_PSR_8M_HZ      = 3
-};
-
-/*
- * 24-bit timers: external timer 3, 5, and 7
- * 32-bit timers: external timer 4, 6, and 8
- */
-enum ext_timer_sel {
-	/* timer 3 and 4 combine mode for free running timer */
-	EXT_TIMER_3 = 0,
-	EXT_TIMER_4,
-	/* For fan control */
-	EXT_TIMER_5,
-	/* timer 6 for event timer */
-	EXT_TIMER_6,
-	/* For WDT capture important state information before being reset */
-	EXT_TIMER_7,
-	/* HW timer for low power mode */
-	EXT_TIMER_8,
-	EXT_TIMER_COUNT,
-};
-
-struct ext_timer_ctrl_t {
-	volatile uint8_t *mode;
-	volatile uint8_t *polarity;
-	volatile uint8_t *isr;
-	uint8_t mask;
-	uint8_t irq;
-};
-
-extern const struct ext_timer_ctrl_t et_ctrl_regs[];
-#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
-uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer);
-#endif
-void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq);
-void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq);
-void fan_ext_timer_interrupt(void);
-void update_exc_start_time(void);
-
-/**
- * Config a external timer.
- *
- * @param raw	(!=0) timer count equal to param "ms" no conversion.
- */
-int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int et_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw);
-
-#endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
deleted file mode 100644
index 5aa8f8a460..0000000000
--- a/chip/it83xx/i2c.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Default maximum time we allow for an I2C transfer */
-#define I2C_TIMEOUT_DEFAULT_US (100 * MSEC)
-
-enum enhanced_i2c_transfer_direct {
-	TX_DIRECT,
-	RX_DIRECT,
-};
-
-enum i2c_host_status {
-	/* Host busy */
-	HOSTA_HOBY = 0x01,
-	/* Finish Interrupt */
-	HOSTA_FINTR = 0x02,
-	/* Device error */
-	HOSTA_DVER = 0x04,
-	/* Bus error */
-	HOSTA_BSER = 0x08,
-	/* Fail */
-	HOSTA_FAIL = 0x10,
-	/* Not response ACK */
-	HOSTA_NACK = 0x20,
-	/* Time-out error */
-	HOSTA_TMOE = 0x40,
-	/* Byte done status */
-	HOSTA_BDS = 0x80,
-	/* Error bit is set */
-	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER |
-				HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE),
-	/* W/C for next byte */
-	HOSTA_NEXT_BYTE = HOSTA_BDS,
-	/* W/C host status register */
-	HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
-};
-
-enum enhanced_i2c_host_status {
-	/* ACK receive */
-	E_HOSTA_ACK = 0x01,
-	/* Interrupt pending */
-	E_HOSTA_INTP = 0x02,
-	/* Read/Write */
-	E_HOSTA_RW = 0x04,
-	/* Time out error */
-	E_HOSTA_TMOE = 0x08,
-	/* Arbitration lost */
-	E_HOSTA_ARB = 0x10,
-	/* Bus busy */
-	E_HOSTA_BB = 0x20,
-	/* Address match */
-	E_HOSTA_AM = 0x40,
-	/* Byte done status */
-	E_HOSTA_BDS = 0x80,
-	/* time out or lost arbitration */
-	E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
-	/* Byte transfer done and ACK receive */
-	E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
-};
-
-enum enhanced_i2c_ctl {
-	/* Hardware reset */
-	E_HW_RST = 0x01,
-	/* Stop */
-	E_STOP = 0x02,
-	/* Start & Repeat start */
-	E_START = 0x04,
-	/* Acknowledge */
-	E_ACK = 0x08,
-	/* State reset */
-	E_STS_RST = 0x10,
-	/* Mode select */
-	E_MODE_SEL = 0x20,
-	/* I2C interrupt enable */
-	E_INT_EN = 0x40,
-	/* 0 : Standard mode , 1 : Receive mode */
-	E_RX_MODE = 0x80,
-	/* State reset and hardware reset */
-	E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
-	/* Generate start condition and transmit peripheral address */
-	E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
-	/* Generate stop condition */
-	E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
-};
-
-enum i2c_reset_cause {
-	I2C_RC_NO_IDLE_FOR_START = 1,
-	I2C_RC_TIMEOUT,
-};
-
-struct i2c_ch_freq {
-	int kbps;
-	uint8_t freq_set;
-};
-
-static const struct i2c_ch_freq i2c_freq_select[] = {
-	{ 50,   1},
-	{ 100,  2},
-	{ 400,  3},
-	{ 1000, 4},
-};
-
-struct i2c_pin {
-	volatile uint8_t *pin_clk;
-	volatile uint8_t *pin_data;
-	volatile uint8_t *pin_clk_ctrl;
-	volatile uint8_t *pin_data_ctrl;
-	volatile uint8_t *mirror_clk;
-	volatile uint8_t *mirror_data;
-	uint8_t clk_mask;
-	uint8_t data_mask;
-};
-
-static const struct i2c_pin i2c_pin_regs[] = {
-	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4,
-		&IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB,
-		&IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB,
-		0x08, 0x10},
-	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC,
-		0x02, 0x04},
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF,
-		0x80, 0x80},
-#else
-	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF,
-		0x40, 0x80},
-#endif
-	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2,
-		&IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH,
-		&IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH,
-		0x02, 0x04},
-	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7,
-		&IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE,
-		&IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE,
-		0x01, 0x80},
-	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5,
-		&IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA,
-		&IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA,
-		0x10, 0x20},
-};
-
-struct i2c_ctrl_t {
-	uint8_t irq;
-	enum clock_gate_offsets clock_gate;
-	int reg_shift;
-};
-
-const struct i2c_ctrl_t i2c_ctrl_regs[] = {
-	{IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1},
-	{IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1},
-	{IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1},
-	{IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3},
-	{IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0},
-	{IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1},
-};
-
-enum i2c_ch_status {
-	I2C_CH_NORMAL = 0,
-	I2C_CH_REPEAT_START,
-	I2C_CH_WAIT_READ,
-	I2C_CH_WAIT_NEXT_XFER,
-};
-
-/* I2C port state data */
-struct i2c_port_data {
-	const uint8_t *out;  /* Output data pointer */
-	int out_size;        /* Output data to transfer, in bytes */
-	uint8_t *in;         /* Input data pointer */
-	int in_size;         /* Input data to transfer, in bytes */
-	int flags;           /* Flags (I2C_XFER_*) */
-	int widx;            /* Index into output data */
-	int ridx;            /* Index into input data */
-	int err;             /* Error code, if any */
-	uint8_t addr_8bit;   /* address of device */
-	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
-	uint8_t freq;        /* Frequency setting */
-
-	enum i2c_ch_status i2ccs;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-static int i2c_ch_reg_shift(int p)
-{
-	/*
-	 * only enhanced port needs to be changed the parameter of registers
-	 */
-	ASSERT(p >= I2C_STANDARD_PORT_COUNT && p < I2C_PORT_COUNT);
-
-	/*
-	 * The registers of i2c enhanced ports are not sequential.
-	 * This routine transfers the i2c port number to related
-	 * parameter of registers.
-	 *
-	 * IT83xx chip : i2c enhanced ports - channel D,E,F
-	 * channel D registers : 0x3680 ~ 0x36FF
-	 * channel E registers : 0x3500 ~ 0x357F
-	 * channel F registers : 0x3580 ~ 0x35FF
-	 */
-	return i2c_ctrl_regs[p].reg_shift;
-}
-
-static void i2c_reset(int p, int cause)
-{
-	int p_ch;
-
-	if (p < I2C_STANDARD_PORT_COUNT) {
-		/* bit1, kill current transaction. */
-		IT83XX_SMB_HOCTL(p) = 0x2;
-		IT83XX_SMB_HOCTL(p) = 0;
-		/* W/C host status register */
-		IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-	} else {
-		/* Shift register */
-		p_ch = i2c_ch_reg_shift(p);
-		/* State reset and hardware reset */
-		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-	}
-	CPRINTS("I2C ch%d reset cause %d", p, cause);
-}
-
-static void i2c_r_last_byte(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	/*
-	 * bit5, The firmware shall write 1 to this bit
-	 * when the next byte will be the last byte for i2c read.
-	 */
-	if ((pd->flags & I2C_XFER_STOP) && (pd->ridx == pd->in_size - 1))
-		IT83XX_SMB_HOCTL(p) |= 0x20;
-}
-
-static void i2c_w2r_change_direction(int p)
-{
-	/* I2C switch direction */
-	if (IT83XX_SMB_HOCTL2(p) & 0x08) {
-		i2c_r_last_byte(p);
-		IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-	} else {
-		/*
-		 * bit2, I2C switch direction wait.
-		 * bit3, I2C switch direction enable.
-		 */
-		IT83XX_SMB_HOCTL2(p) |= 0x0C;
-		IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-		i2c_r_last_byte(p);
-		IT83XX_SMB_HOCTL2(p) &= ~0x04;
-	}
-}
-
-static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
-			       uint8_t data, int first_byte)
-{
-	struct i2c_port_data *pd = pdata + p;
-	int p_ch;
-	int nack = 0;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (first_byte) {
-		/* First byte must be peripheral address. */
-		IT83XX_I2C_DTR(p_ch) =
-			data | (direct == RX_DIRECT ? BIT(0) : 0);
-		/* start or repeat start signal. */
-		IT83XX_I2C_CTR(p_ch) = E_START_ID;
-	} else {
-		if (direct == TX_DIRECT)
-			/* Transmit data */
-			IT83XX_I2C_DTR(p_ch) = data;
-		else {
-			/*
-			 * Receive data.
-			 * Last byte should be NACK in the end of read cycle
-			 */
-			if (((pd->ridx + 1) == pd->in_size) &&
-				(pd->flags & I2C_XFER_STOP))
-				nack = 1;
-		}
-		/* Set hardware reset to start next transmission */
-		IT83XX_I2C_CTR(p_ch) =
-			E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK);
-	}
-}
-
-static int i2c_tran_write(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* i2c enable */
-		IT83XX_SMB_HOCTL2(p) = 0x13;
-		/*
-		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted peripheral.
-		 */
-		IT83XX_SMB_TRASLA(p) = pd->addr_8bit;
-		/* Send first byte */
-		IT83XX_SMB_HOBDB(p) = *(pd->out++);
-		pd->widx++;
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		/*
-		 * bit0, Host interrupt enable.
-		 * bit[2:4}, Extend command.
-		 * bit6, start.
-		 */
-		IT83XX_SMB_HOCTL(p) = 0x5D;
-	} else {
-		/* Host has completed the transmission of a byte */
-		if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) {
-			if (pd->widx < pd->out_size) {
-				/* Send next byte */
-				IT83XX_SMB_HOBDB(p) = *(pd->out++);
-				pd->widx++;
-				/* W/C byte done for next byte */
-				IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-				if (pd->i2ccs == I2C_CH_REPEAT_START) {
-					pd->i2ccs = I2C_CH_NORMAL;
-					task_enable_irq(i2c_ctrl_regs[p].irq);
-				}
-			} else {
-				/* done */
-				pd->out_size = 0;
-				if (pd->in_size > 0) {
-					/* write to read */
-					i2c_w2r_change_direction(p);
-				} else {
-					if (pd->flags & I2C_XFER_STOP) {
-						/* set I2C_EN = 0 */
-						IT83XX_SMB_HOCTL2(p) = 0x11;
-						/* W/C byte done for finish */
-						IT83XX_SMB_HOSTA(p) =
-							HOSTA_NEXT_BYTE;
-					} else {
-						pd->i2ccs = I2C_CH_REPEAT_START;
-						return 0;
-					}
-				}
-			}
-		}
-	}
-	return 1;
-}
-
-static int i2c_tran_read(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* i2c enable */
-		IT83XX_SMB_HOCTL2(p) = 0x13;
-		/*
-		 * bit0, Direction of the host transfer.
-		 * bit[1:7}, Address of the targeted peripheral.
-		 */
-		IT83XX_SMB_TRASLA(p) = pd->addr_8bit | 0x01;
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		/*
-		 * bit0, Host interrupt enable.
-		 * bit[2:4}, Extend command.
-		 * bit5, The firmware shall write 1 to this bit
-		 *       when the next byte will be the last byte.
-		 * bit6, start.
-		 */
-		if ((1 == pd->in_size) && (pd->flags & I2C_XFER_STOP))
-			IT83XX_SMB_HOCTL(p) = 0x7D;
-		else
-			IT83XX_SMB_HOCTL(p) = 0x5D;
-	} else {
-		if ((pd->i2ccs == I2C_CH_REPEAT_START) ||
-			(pd->i2ccs == I2C_CH_WAIT_READ)) {
-			if (pd->i2ccs == I2C_CH_REPEAT_START) {
-				/* write to read */
-				i2c_w2r_change_direction(p);
-			} else {
-				/* For last byte */
-				i2c_r_last_byte(p);
-				/* W/C for next byte */
-				IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-			}
-			pd->i2ccs = I2C_CH_NORMAL;
-			task_enable_irq(i2c_ctrl_regs[p].irq);
-		} else if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) {
-			if (pd->ridx < pd->in_size) {
-				/* To get received data. */
-				*(pd->in++) = IT83XX_SMB_HOBDB(p);
-				pd->ridx++;
-				/* For last byte */
-				i2c_r_last_byte(p);
-				/* done */
-				if (pd->ridx == pd->in_size) {
-					pd->in_size = 0;
-					if (pd->flags & I2C_XFER_STOP) {
-						/* W/C for finish */
-						IT83XX_SMB_HOSTA(p) =
-							HOSTA_NEXT_BYTE;
-					} else {
-						pd->i2ccs = I2C_CH_WAIT_READ;
-						return 0;
-					}
-				} else {
-					/* W/C for next byte */
-					IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE;
-				}
-			}
-		}
-	}
-	return 1;
-}
-
-static void enhanced_i2c_start(int p)
-{
-	/* Shift register */
-	int p_ch = i2c_ch_reg_shift(p);
-
-	/* State reset and hardware reset */
-	IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-	/* Set i2c frequency */
-	IT83XX_I2C_PSR(p_ch) = pdata[p].freq;
-	IT83XX_I2C_HSPR(p_ch) = pdata[p].freq;
-	/*
-	 * Set time out register.
-	 * I2C D/E/F clock/data low timeout.
-	 */
-	IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
-	/* bit1: Enable enhanced i2c module */
-	IT83XX_I2C_CTR1(p_ch) = BIT(1);
-}
-
-static int enhanced_i2c_tran_write(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	uint8_t out_data;
-	int p_ch;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (pd->flags & I2C_XFER_START) {
-		/* Clear start bit */
-		pd->flags &= ~I2C_XFER_START;
-		enhanced_i2c_start(p);
-		/* Send ID */
-		i2c_pio_trans_data(p, TX_DIRECT, pd->addr_8bit, 1);
-	} else {
-		/* Host has completed the transmission of a byte */
-		if (pd->widx < pd->out_size) {
-			out_data = *(pd->out++);
-			pd->widx++;
-
-			/* Send Byte */
-			i2c_pio_trans_data(p, TX_DIRECT, out_data, 0);
-			if (pd->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			}
-		} else {
-			/* done */
-			pd->out_size = 0;
-			if (pd->in_size > 0) {
-				/* Write to read protocol */
-				pd->i2ccs = I2C_CH_REPEAT_START;
-				/* Repeat Start */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
-			} else {
-				if (pd->flags & I2C_XFER_STOP) {
-					IT83XX_I2C_CTR(p_ch) = E_FINISH;
-					/* wait for stop bit interrupt*/
-					return 1;
-				}
-				/* Direct write with direct read */
-				pd->i2ccs = I2C_CH_WAIT_NEXT_XFER;
-				return 0;
-			}
-		}
-	}
-	return 1;
-}
-
-static int enhanced_i2c_tran_read(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	uint8_t in_data = 0;
-	int p_ch;
-
-	/* Shift register */
-	p_ch = i2c_ch_reg_shift(p);
-
-	if (pd->flags & I2C_XFER_START) {
-		/* clear start flag */
-		pd->flags &= ~I2C_XFER_START;
-		enhanced_i2c_start(p);
-		/* Direct read  */
-		pd->i2ccs = I2C_CH_WAIT_READ;
-		/* Send ID */
-		i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit, 1);
-	} else {
-		if (pd->i2ccs) {
-			if (pd->i2ccs == I2C_CH_REPEAT_START) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				/* Receive data */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-			} else if (pd->i2ccs == I2C_CH_WAIT_READ) {
-				pd->i2ccs = I2C_CH_NORMAL;
-				/* Receive data */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-				/* Turn on irq before next direct read */
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			} else {
-				/* Write to read */
-				pd->i2ccs = I2C_CH_WAIT_READ;
-				/* Send ID */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
-				task_enable_irq(i2c_ctrl_regs[p].irq);
-			}
-		} else {
-			if (pd->ridx < pd->in_size) {
-				/* read data */
-				*(pd->in++) = IT83XX_I2C_DRR(p_ch);
-				pd->ridx++;
-
-				/* done */
-				if (pd->ridx == pd->in_size) {
-					pd->in_size = 0;
-					if (pd->flags & I2C_XFER_STOP) {
-						pd->i2ccs = I2C_CH_NORMAL;
-						IT83XX_I2C_CTR(p_ch) = E_FINISH;
-						/* wait for stop bit interrupt*/
-						return 1;
-					}
-					/* End the transaction */
-					pd->i2ccs = I2C_CH_WAIT_READ;
-					return 0;
-				}
-				/* read next byte */
-				i2c_pio_trans_data(p, RX_DIRECT, in_data, 0);
-			}
-		}
-	}
-	return 1;
-}
-
-static int enhanced_i2c_error(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	/* Shift register */
-	int p_ch = i2c_ch_reg_shift(p);
-	int i2c_str = IT83XX_I2C_STR(p_ch);
-
-	if (i2c_str & E_HOSTA_ANY_ERROR) {
-		pd->err = i2c_str & E_HOSTA_ANY_ERROR;
-	/* device does not respond ACK */
-	} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
-		if (IT83XX_I2C_CTR(p_ch) & E_ACK)
-			pd->err = E_HOSTA_ACK;
-	}
-
-	return pd->err;
-}
-
-static int i2c_transaction(int p)
-{
-	struct i2c_port_data *pd = pdata + p;
-	int p_ch;
-
-	if (p < I2C_STANDARD_PORT_COUNT) {
-		/* any error */
-		if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) {
-			pd->err = (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR);
-		} else {
-			/* i2c write */
-			if (pd->out_size)
-				return i2c_tran_write(p);
-			/* i2c read */
-			else if (pd->in_size)
-				return i2c_tran_read(p);
-			/* wait finish */
-			if (!(IT83XX_SMB_HOSTA(p) & HOSTA_FINTR))
-				return 1;
-		}
-		/* W/C */
-		IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-		/* disable the SMBus host interface */
-		IT83XX_SMB_HOCTL2(p) = 0x00;
-	} else {
-		/* no error */
-		if (!(enhanced_i2c_error(p))) {
-			/* i2c write */
-			if (pd->out_size)
-				return enhanced_i2c_tran_write(p);
-			/* i2c read */
-			else if (pd->in_size)
-				return enhanced_i2c_tran_read(p);
-		}
-		p_ch = i2c_ch_reg_shift(p);
-		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-		IT83XX_I2C_CTR1(p_ch) = 0;
-	}
-	/* done doing work */
-	return 0;
-}
-
-int i2c_is_busy(int port)
-{
-	int p_ch;
-
-	if (port < I2C_STANDARD_PORT_COUNT)
-		return (IT83XX_SMB_HOSTA(port) &
-			(HOSTA_HOBY | HOSTA_ALL_WC_BIT));
-
-	p_ch = i2c_ch_reg_shift(port);
-	return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB);
-}
-
-int chip_i2c_xfer(int port, uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t events = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	/*
-	 * Make the below i2c transaction work:
-	 * - i2c_xfer with I2C_XFER_START flag
-	 * - i2c_xfer with I2C_XFER_START flag
-	 * - xxx
-	 * - i2c_xfer with I2C_XFER_STOP flag
-	 */
-	if (pd->i2ccs)
-		flags &= ~I2C_XFER_START;
-
-	/* Copy data to port struct */
-	pd->out = out;
-	pd->out_size = out_size;
-	pd->in = in;
-	pd->in_size = in_size;
-	pd->flags = flags;
-	pd->widx = 0;
-	pd->ridx = 0;
-	pd->err = 0;
-	pd->addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
-		|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-
-		/* Attempt to unwedge the port. */
-		pd->err = i2c_unwedge(port);
-
-		/* reset i2c port */
-		i2c_reset(port, I2C_RC_NO_IDLE_FOR_START);
-
-		/* Return if port is still wedged */
-		if (pd->err)
-			return pd->err;
-	}
-
-	pd->task_waiting = task_get_current();
-	if (pd->flags & I2C_XFER_START) {
-		pd->i2ccs = I2C_CH_NORMAL;
-		/* enable i2c interrupt */
-		task_clear_pending_irq(i2c_ctrl_regs[port].irq);
-		task_enable_irq(i2c_ctrl_regs[port].irq);
-	}
-	/* Start transaction */
-	i2c_transaction(port);
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
-	/* disable i2c interrupt */
-	task_disable_irq(i2c_ctrl_regs[port].irq);
-	pd->task_waiting = TASK_ID_INVALID;
-
-	/* Handle timeout */
-	if (!(events & TASK_EVENT_I2C_IDLE)) {
-		pd->err = EC_ERROR_TIMEOUT;
-		/* reset i2c port */
-		i2c_reset(port, I2C_RC_TIMEOUT);
-	}
-
-	/* reset i2c channel status */
-	if (pd->err)
-		pd->i2ccs = I2C_CH_NORMAL;
-
-	return pd->err;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return !!(*i2c_pin_regs[port].mirror_clk &
-			i2c_pin_regs[port].clk_mask);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return !!(*i2c_pin_regs[port].mirror_data &
-			i2c_pin_regs[port].data_mask);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	int pin_sts = 0;
-
-	if (port < I2C_STANDARD_PORT_COUNT)
-		return IT83XX_SMB_SMBPCTL(port) & 0x03;
-
-	if (*i2c_pin_regs[port].mirror_clk & i2c_pin_regs[port].clk_mask)
-		pin_sts |= I2C_LINE_SCL_HIGH;
-	if (*i2c_pin_regs[port].mirror_data & i2c_pin_regs[port].data_mask)
-		pin_sts |= I2C_LINE_SDA_HIGH;
-
-	return pin_sts;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-void i2c_interrupt(int port)
-{
-	int id = pdata[port].task_waiting;
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(i2c_ctrl_regs[port].irq);
-
-	/* If no task is waiting, just return */
-	if (id == TASK_ID_INVALID)
-		return;
-
-	/* If done doing work, wake up the task waiting for the transfer */
-	if (!i2c_transaction(port)) {
-		task_disable_irq(i2c_ctrl_regs[port].irq);
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-	}
-}
-
-/*
- * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
- * (offset 0h ~ 7h).
- */
-static void i2c_standard_port_timing_regs_400khz(int port)
-{
-	/* Port clock frequency depends on setting of timing registers. */
-	IT83XX_SMB_SCLKTS(port) = 0;
-	/* Suggested setting of timing registers of 400kHz. */
-	IT83XX_SMB_4P7USL = 0x6;
-	IT83XX_SMB_4P0USL = 0;
-	IT83XX_SMB_300NS = 0x1;
-	IT83XX_SMB_250NS = 0x2;
-	IT83XX_SMB_45P3USL = 0x6a;
-	IT83XX_SMB_45P3USH = 0x1;
-	IT83XX_SMB_4P7A4P0H = 0;
-}
-
-/* Set clock frequency for i2c port A, B , or C */
-static void i2c_standard_port_set_frequency(int port, int freq_khz)
-{
-	/*
-	 * If port's clock frequency is 400kHz, we use timing registers
-	 * for setting. So we can adjust tlow to meet timing.
-	 * The others use basic 50/100/1000 KHz setting.
-	 */
-	if (freq_khz == 400) {
-		i2c_standard_port_timing_regs_400khz(port);
-	} else {
-		for (int f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) {
-			if (freq_khz >= i2c_freq_select[f].kbps) {
-				IT83XX_SMB_SCLKTS(port) =
-						i2c_freq_select[f].freq_set;
-				break;
-			}
-		}
-	}
-
-	/* This field defines the SMCLK0/1/2 clock/data low timeout. */
-	IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
-}
-
-/* Set clock frequency for i2c port D, E , or F */
-static void i2c_enhanced_port_set_frequency(int port, int freq_khz)
-{
-	int port_reg_shift, clk_div, psr;
-
-	/* Get base address of i2c enhanced port's registers. */
-	port_reg_shift = i2c_ch_reg_shift(port);
-	/*
-	 * Let psr(Prescale) = IT83XX_I2C_PSR(port_reg_shift)
-	 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
-	 * SMBus clock = PLL_CLOCK / clk_div
-	 * SMBus clock cycle = 1 / SMBus clock
-	 * 1 SCL cycle = 1 / (1000 x freq)
-	 * 1 / (1000 x freq) = 2 x (psr + 2) x (1 / (PLL_CLOCK / clk_div))
-	 * psr = ((PLL_CLOCK / clk_div) x (1 / (1000 x freq)) x (1 / 2)) - 2
-	 */
-	if (freq_khz) {
-		/* Get SMBus clock divide value */
-		clk_div = (IT83XX_ECPM_SCDCR2 & 0x0F) + 1;
-		/* Calculate PSR value */
-		psr = (PLL_CLOCK / (clk_div * (2 * 1000 * freq_khz))) - 2;
-		/* Set psr value under 0xFD */
-		if (psr > 0xFD)
-			psr = 0xFD;
-
-		/* Set I2C Speed */
-		IT83XX_I2C_PSR(port_reg_shift) = (psr & 0xFF);
-		IT83XX_I2C_HSPR(port_reg_shift) = (psr & 0xFF);
-		/* Backup */
-		pdata[port].freq = (psr & 0xFF);
-	}
-}
-
-static void i2c_freq_changed(void)
-{
-	int i, freq, port;
-
-	/* Set clock frequency for I2C ports */
-	for (i = 0; i < i2c_ports_used; i++) {
-		freq = i2c_ports[i].kbps;
-		port = i2c_ports[i].port;
-		if (port < I2C_STANDARD_PORT_COUNT)
-			i2c_standard_port_set_frequency(port, freq);
-		else
-			i2c_enhanced_port_set_frequency(port, freq);
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	int i, p, p_ch;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	/* bit7, 0: SMCLK2 is located on GPF6, 1: SMCLK2 is located on GPC7 */
-	IT83XX_GPIO_GRC7 |= 0x80;
-#endif
-
-	/* Enable I2C function. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		/* I2c port mapping. */
-		p = i2c_ports[i].port;
-
-		clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0);
-
-		if (p < I2C_STANDARD_PORT_COUNT) {
-			/*
-			 * bit0, The SMBus host interface is enabled.
-			 * bit1, Enable to communicate with I2C device
-			 *        and support I2C-compatible cycles.
-			 * bit4, This bit controls the reset mechanism
-			 *        of SMBus master to handle the SMDAT
-			 *        line low if 25ms reg timeout.
-			 */
-			IT83XX_SMB_HOCTL2(p) = 0x11;
-			/*
-			 * bit1, Kill SMBus host transaction.
-			 * bit0, Enable the interrupt for the master interface.
-			 */
-			IT83XX_SMB_HOCTL(p) = 0x03;
-			IT83XX_SMB_HOCTL(p) = 0x01;
-			/* W/C host status register */
-			IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
-			IT83XX_SMB_HOCTL2(p) = 0x00;
-		} else {
-			/* Shift register */
-			p_ch = i2c_ch_reg_shift(p);
-			switch (p) {
-			case IT83XX_I2C_CH_D:
-				#ifndef CONFIG_UART_HOST
-				/* Enable SMBus D channel */
-				IT83XX_GPIO_GRC2 |= 0x20;
-				#endif
-				break;
-			case IT83XX_I2C_CH_E:
-				/* Enable SMBus E channel */
-				IT83XX_GCTRL_PMER1 |= 0x01;
-				break;
-			case IT83XX_I2C_CH_F:
-				/* Enable SMBus F channel */
-				IT83XX_GCTRL_PMER1 |= 0x02;
-				break;
-			}
-			/* Software reset */
-			IT83XX_I2C_DHTR(p_ch) |= 0x80;
-			IT83XX_I2C_DHTR(p_ch) &= 0x7F;
-			/* State reset and hardware reset */
-			IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
-			/* bit1, Module enable */
-			IT83XX_I2C_CTR1(p_ch) = 0;
-		}
-		pdata[i].task_waiting = TASK_ID_INVALID;
-	}
-
-	i2c_freq_changed();
-
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		/* Use default timeout */
-		i2c_set_timeout(i, 0);
-	}
-}
diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c
deleted file mode 100644
index 91eb2c1dfb..0000000000
--- a/chip/it83xx/i2c_peripheral.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module for Chrome EC */
-#include "clock.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c_peripheral.h"
-#include "registers.h"
-#include <stddef.h>
-#include <string.h>
-#include "task.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* The size must be a power of 2 */
-#define I2C_MAX_BUFFER_SIZE 0x100
-#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1)
-
-#define I2C_READ_MAXFIFO_DATA 16
-#define I2C_ENHANCED_CH_INTERVAL 0x80
-
-/* Store controller to peripheral data of channel D, E, F by DMA */
-static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store peripheral to controller data of channel D, E, F by DMA */
-static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
-/* Store read and write data of channel A by FIFO mode */
-static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
-
-static uint32_t w_index;
-static uint32_t r_index;
-static int wr_done[I2C_ENHANCED_PORT_COUNT];
-
-void buffer_index_reset(void)
-{
-	/* Reset write buffer index */
-	w_index = 0;
-	/* Reset read buffer index */
-	r_index = 0;
-}
-
-/* Data structure to define I2C peripheral control configuration. */
-struct i2c_periph_ctrl_t {
-	int irq;              /* peripheral irq */
-	/* offset from base 0x00F03500 register; -1 means unused. */
-	int offset;
-	enum clock_gate_offsets clock_gate;
-	int dma_index;
-};
-
-/* I2C peripheral control */
-const struct i2c_periph_ctrl_t i2c_periph_ctrl[] = {
-	[IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1,
-		.clock_gate = CGC_OFFSET_SMBA, .dma_index = -1},
-	[IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180,
-		.clock_gate = CGC_OFFSET_SMBD, .dma_index = 0},
-	[IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0,
-		.clock_gate = CGC_OFFSET_SMBE, .dma_index = 1},
-	[IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80,
-		.clock_gate = CGC_OFFSET_SMBF, .dma_index = 2},
-};
-
-void i2c_peripheral_read_write_data(int port)
-{
-	int periph_status, i;
-
-	/* I2C peripheral channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-		int count;
-
-		periph_status = IT83XX_SMB_SLSTA;
-
-		/* bit0-4 : FIFO byte count */
-		count = IT83XX_SMB_SFFSTA & 0x1F;
-
-		/* Peripheral data register is waiting for read or write. */
-		if (periph_status & IT83XX_SMB_SDS) {
-			/* Controller to read data */
-			if (periph_status & IT83XX_SMB_RCS) {
-				for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
-					/* Return buffer data to controller */
-					IT83XX_SMB_SLDA =
-					pbuffer[(i + r_index) & I2C_SIZE_MASK];
-
-				/* Index to next 16 bytes of read buffer */
-				r_index += I2C_READ_MAXFIFO_DATA;
-			}
-			/* Controller to write data */
-			else {
-				/* FIFO Full */
-				if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
-					for (i = 0; i < count; i++)
-				/* Get data from controller to buffer */
-						pbuffer[(w_index + i) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-				}
-
-				/* Index to next byte of write buffer */
-				w_index += count;
-			}
-		}
-		/* Stop condition, indicate stop condition detected. */
-		if (periph_status & IT83XX_SMB_SPDS) {
-			/* Read data less 16 bytes status */
-			if (periph_status & IT83XX_SMB_RCS) {
-				/* Disable FIFO mode to clear left count */
-				IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE;
-
-				/* Peripheral A FIFO Enable */
-				IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-			}
-			/* Controller to write data */
-			else {
-				for (i = 0; i < count; i++)
-					/* Get data from controller to buffer */
-					pbuffer[(i + w_index) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
-			}
-
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-		/* Peripheral time status, timeout status occurs. */
-		if (periph_status & IT83XX_SMB_STS) {
-			/* Reset read and write buffer index */
-			buffer_index_reset();
-		}
-
-		/* Write clear the peripheral status */
-		IT83XX_SMB_SLSTA = periph_status;
-	}
-	/* Enhanced I2C peripheral channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_periph_ctrl[port].dma_index;
-
-		/* Interrupt pending */
-		if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
-
-			periph_status = IT83XX_I2C_IRQ_ST(ch);
-
-			/* Controller to read data */
-			if (periph_status & IT83XX_I2C_IDR_CLR) {
-			/*
-			 * TODO(b:129360157): Return buffer data by
-			 * "out_data" array.
-			 * Ex: Write data to buffer from 0x00 to 0xFF
-			 */
-				for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
-					out_data[idx][i] = i;
-			}
-			/* Controller to write data */
-			if (periph_status & IT83XX_I2C_IDW_CLR) {
-				/* Controller to write data finish flag */
-				wr_done[idx] = 1;
-			}
-			/* Peripheral finish */
-			if (periph_status & IT83XX_I2C_P_CLR) {
-				if (wr_done[idx]) {
-			/*
-			 * TODO(b:129360157): Handle controller write
-			 * data by "in_data" array.
-			 */
-					CPRINTS("WData: %ph",
-						HEX_BUF(in_data[idx],
-							I2C_MAX_BUFFER_SIZE));
-					wr_done[idx] = 0;
-				}
-			}
-
-			/* Write clear the peripheral status */
-			IT83XX_I2C_IRQ_ST(ch) = periph_status;
-		}
-
-		/* Hardware reset */
-		IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT;
-	}
-}
-
-void i2c_periph_interrupt(int port)
-{
-	/* Peripheral to read and write fifo data */
-	i2c_peripheral_read_write_data(port);
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(i2c_periph_ctrl[port].irq);
-}
-
-void i2c_peripheral_enable(int port, uint8_t periph_addr)
-{
-
-	clock_enable_peripheral(i2c_periph_ctrl[port].clock_gate, 0, 0);
-
-	/* I2C peripheral channel A FIFO mode */
-	if (port < I2C_STANDARD_PORT_COUNT) {
-
-		/* This field defines the SMCLK0/1/2 clock/data low timeout. */
-		IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
-
-		/* bit0 : Peripheral A FIFO Enable */
-		IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE;
-
-		/*
-		 * bit1 : Peripheral interrupt enable.
-		 * bit2 : SMCLK/SMDAT will be released if timeout.
-		 * bit3 : Peripheral detect STOP condition interrupt enable.
-		 */
-		IT83XX_SMB_SICR = 0x0E;
-
-		/* Peripheral address 1 */
-		IT83XX_SMB_RESLADR = periph_addr;
-
-		/* Write clear all peripheral status */
-		IT83XX_SMB_SLSTA = 0xE7;
-
-		/* bit5 : Enable the SMBus peripheral device */
-		IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN;
-	}
-	/* Enhanced I2C peripheral channel D, E, F DMA mode */
-	else {
-		int ch, idx;
-		uint32_t in_data_addr, out_data_addr;
-
-		/* Get enhanced i2c channel */
-		ch = i2c_periph_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL;
-
-		idx = i2c_periph_ctrl[port].dma_index;
-
-		switch (port) {
-		case IT83XX_I2C_CH_D:
-			/* Enable I2C D channel */
-			IT83XX_GPIO_GRC2 |= (1 << 5);
-			break;
-		case IT83XX_I2C_CH_E:
-			/* Enable I2C E channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 0);
-			break;
-		case IT83XX_I2C_CH_F:
-			/* Enable I2C F channel */
-			IT83XX_GCTRL_PMER1 |= (1 << 1);
-			break;
-		}
-
-		/* Software reset */
-		IT83XX_I2C_DHTR(ch) |= (1 << 7);
-		IT83XX_I2C_DHTR(ch) &= ~(1 << 7);
-
-		/* This field defines the SMCLK3/4/5 clock/data low timeout. */
-		IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT;
-
-		/* Bit stretching */
-		IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR;
-
-		/* Peripheral address(8-bit)*/
-		IT83XX_I2C_IDR(ch) = periph_addr << 1;
-
-		/* I2C interrupt enable and set acknowledge */
-		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT |
-			IT83XX_I2C_INTEN | IT83XX_I2C_ACK;
-
-		/*
-		 * bit3 : Peripheral ID write flag
-		 * bit2 : Peripheral ID read flag
-		 * bit1 : Peripheral received data flag
-		 * bit0 : Peripheral finish
-		 */
-		IT83XX_I2C_IRQ_ST(ch) = 0xFF;
-
-		/* Clear read and write data buffer of DMA */
-		memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-		memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE);
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			in_data_addr = (uint32_t)in_data[idx] & 0xffffff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xffffff;
-		} else {
-			in_data_addr = (uint32_t)in_data[idx] & 0xfff;
-			out_data_addr = (uint32_t)out_data[idx] & 0xfff;
-		}
-
-		/* DMA write target address register */
-		IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8;
-		IT83XX_I2C_RAMLA(ch) = in_data_addr;
-
-		if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) {
-			/*
-			 * DMA write target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16;
-			/*
-			 * DMA read target address register
-			 * for high order byte
-			 */
-			IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16;
-			IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8;
-			IT83XX_I2C_CMD_ADDL(ch) = out_data_addr;
-		} else {
-			/* DMA read target address register */
-			IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8;
-			IT83XX_I2C_RAMLA2(ch) = out_data_addr;
-		}
-
-		/* I2C module enable and command queue mode */
-		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN |
-			IT83XX_I2C_MDL_EN;
-	}
-}
-
-static void i2c_peripheral_init(void)
-{
-	int  i, p;
-
-	/* DLM 52k~56k size select enable */
-	IT83XX_GCTRL_MCCR2 |= (1 << 4);
-
-	/* Enable I2C Peripheral function */
-	for (i = 0; i < i2c_periphs_used; i++) {
-
-		/* I2c peripheral port mapping. */
-		p = i2c_periph_ports[i].port;
-
-		/* To enable peripheral ch[x] */
-		i2c_peripheral_enable(p, i2c_periph_ports[i].addr);
-
-		/* Clear the interrupt status */
-		task_clear_pending_irq(i2c_periph_ctrl[p].irq);
-
-		/* enable i2c interrupt */
-		task_enable_irq(i2c_periph_ctrl[p].irq);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, i2c_peripheral_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
deleted file mode 100644
index 80abfaad63..0000000000
--- a/chip/it83xx/intc.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "intc.h"
-#include "it83xx_pd.h"
-#include "ite_pd_intc.h"
-#include "kmsc_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-
-int __ram_code intc_get_ec_int(void)
-{
-	extern volatile int ec_int;
-	return ec_int;
-}
-
-void intc_cpu_int_group_5(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_5 = intc_get_ec_int();
-
-	switch (intc_group_5) {
-#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
-	case IT83XX_IRQ_KBC_OUT:
-		lpc_kbc_obe_interrupt();
-		break;
-
-	case IT83XX_IRQ_KBC_IN:
-		lpc_kbc_ibf_interrupt();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_5, intc_cpu_int_group_5, 2);
-
-void intc_cpu_int_group_4(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_4 = intc_get_ec_int();
-
-	switch (intc_group_4) {
-#ifdef CONFIG_HOSTCMD_X86
-	case IT83XX_IRQ_PMC_IN:
-		pm1_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC2_IN:
-		pm2_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC3_IN:
-		pm3_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC4_IN:
-		pm4_ibf_interrupt();
-		break;
-
-	case IT83XX_IRQ_PMC5_IN:
-		pm5_ibf_interrupt();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_4, intc_cpu_int_group_4, 2);
-
-void intc_cpu_int_group_12(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_12 = intc_get_ec_int();
-
-	switch (intc_group_12) {
-#ifdef CONFIG_PECI
-	case IT83XX_IRQ_PECI:
-		peci_interrupt();
-		break;
-#endif
-#ifdef CONFIG_HOSTCMD_ESPI
-	case IT83XX_IRQ_ESPI:
-		espi_interrupt();
-		break;
-
-	case IT83XX_IRQ_ESPI_VW:
-		espi_vw_interrupt();
-		break;
-#endif
-#ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-	case IT83XX_IRQ_USBPD0:
-		chip_pd_irq(USBPD_PORT_A);
-		break;
-
-	case IT83XX_IRQ_USBPD1:
-		chip_pd_irq(USBPD_PORT_B);
-		break;
-#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-	case IT83XX_IRQ_USBPD2:
-		chip_pd_irq(USBPD_PORT_C);
-		break;
-#endif
-#endif
-#ifdef CONFIG_SPI
-	case IT83XX_IRQ_SPI_PERIPHERAL:
-		spi_peripheral_int_handler();
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_12, intc_cpu_int_group_12, 2);
-
-void intc_cpu_int_group_7(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_7 = intc_get_ec_int();
-
-	switch (intc_group_7) {
-#ifdef CONFIG_ADC
-	case IT83XX_IRQ_ADC:
-		adc_interrupt();
-		break;
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-	case IT83XX_IRQ_V_COMP:
-		voltage_comparator_interrupt();
-		break;
-#endif
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_7, intc_cpu_int_group_7, 2);
-
-void intc_cpu_int_group_6(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_6 = intc_get_ec_int();
-
-	switch (intc_group_6) {
-#if defined(CONFIG_I2C_CONTROLLER) || defined(CONFIG_I2C_PERIPHERAL)
-	case IT83XX_IRQ_SMB_A:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (IT83XX_SMB_SFFCTL & IT83XX_SMB_SAFE)
-			i2c_periph_interrupt(IT83XX_I2C_CH_A);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_A);
-		break;
-
-	case IT83XX_IRQ_SMB_B:
-		i2c_interrupt(IT83XX_I2C_CH_B);
-		break;
-
-	case IT83XX_IRQ_SMB_C:
-		i2c_interrupt(IT83XX_I2C_CH_C);
-		break;
-
-	case IT83XX_IRQ_SMB_D:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(3) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_D);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_D);
-		break;
-
-	case IT83XX_IRQ_SMB_E:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(0) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_E);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_E);
-		break;
-
-	case IT83XX_IRQ_SMB_F:
-#ifdef CONFIG_I2C_PERIPHERAL
-		if (!(IT83XX_I2C_CTR(1) & IT83XX_I2C_MODE))
-			i2c_periph_interrupt(IT83XX_I2C_CH_F);
-		else
-#endif
-			i2c_interrupt(IT83XX_I2C_CH_F);
-		break;
-#endif
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_6, intc_cpu_int_group_6, 2);
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
deleted file mode 100644
index 62ceb34576..0000000000
--- a/chip/it83xx/intc.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTC control module for IT83xx. */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/*
- * The DSB instruction guarantees a modified architecture or hardware state
- * can be seen by any following dependent data operations.
- */
-static inline void data_serialization_barrier(void)
-{
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		asm volatile ("dsb");
-}
-
-int intc_get_ec_int(void);
-void pm1_ibf_interrupt(void);
-void pm2_ibf_interrupt(void);
-void pm3_ibf_interrupt(void);
-void pm4_ibf_interrupt(void);
-void pm5_ibf_interrupt(void);
-void lpcrst_interrupt(enum gpio_signal signal);
-void peci_interrupt(void);
-void adc_interrupt(void);
-#ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-void voltage_comparator_interrupt(void);
-#endif
-void i2c_interrupt(int port);
-#ifdef CONFIG_I2C_PERIPHERAL
-void i2c_periph_interrupt(int port);
-#endif
-void clock_sleep_mode_wakeup_isr(void);
-int clock_ec_wake_from_sleep(void);
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds);
-void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
-void espi_fw_reset_module(void);
-void espi_interrupt(void);
-void espi_vw_interrupt(void);
-void espi_enable_pad(int enable);
-void espi_init(void);
-void clock_cpu_standby(void);
-void spi_emmc_cmd0_isr(uint32_t *cmd0_payload);
-void spi_peripheral_int_handler(void);
-#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
-void lpc_kbc_ibf_interrupt(void);
-void lpc_kbc_obe_interrupt(void);
-#endif
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
deleted file mode 100644
index fb01309721..0000000000
--- a/chip/it83xx/irq.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IT83xx chip-specific part of the IRQ handling.
- */
-
-#include "common.h"
-#include "irq_chip.h"
-#include "registers.h"
-#include "util.h"
-
-#define IRQ_GROUP(n, cpu_ints...) \
-	{(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
-	 (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \
-	 ##cpu_ints}
-
-static const struct {
-	uint8_t isr_off;
-	uint8_t ier_off;
-	uint8_t cpu_int[8];
-} irq_groups[] = {
-	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
-	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
-	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
-	IRQ_GROUP(3,  { 5,  4,  4,  4, 11, 11,  3,  2}),
-	IRQ_GROUP(4,  {11, 11, 11, 11,  8,  9,  9,  9}),
-	IRQ_GROUP(5,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(6,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(7,  {10, 10,  3, 12,  3,  3,  3,  3}),
-	IRQ_GROUP(8,  { 4,  4,  4,  4,  4,  4, -1, 12}),
-	IRQ_GROUP(9,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(10, { 3,  6, 12, 12,  5,  2,  2,  2}),
-	IRQ_GROUP(11, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(12, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(13, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(14, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(15, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(16, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(17, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
-	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
-	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
-#if defined(IT83XX_INTC_GROUP_21_22_SUPPORT)
-	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}),
-	IRQ_GROUP(22, { 2,  2,  2,  2,  2,  2,  2,  2}),
-#else
-	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
-	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
-#endif
-	IRQ_GROUP(23, { 2,  2, -1, -1, -1, -1, -1,  2}),
-	IRQ_GROUP(24, { 2,  2,  2,  2,  2,  2, -1,  2}),
-	IRQ_GROUP(25, { 2,  2,  2,  2, -1, -1, -1, -1}),
-	IRQ_GROUP(26, { 2,  2,  2,  2,  2,  2,  2, -1}),
-	IRQ_GROUP(27, { 2,  2,  2,  2,  2,  2, -1, -1}),
-	IRQ_GROUP(28, { 2,  2,  2,  2,  2,  2, -1, -1}),
-};
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-/* Number of CPU hardware interrupts (HW0 ~ HW15) */
-int cpu_int_entry_number;
-#endif
-
-int chip_get_ec_int(void)
-{
-	extern volatile int ec_int;
-
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
-	int i;
-
-	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
-		ec_int = IT83XX_INTC_IVCT(cpu_int_entry_number);
-		/*
-		 * WORKAROUND: when the interrupt vector register isn't
-		 * latched in a load operation,
-		 * we read it again to make sure the value we got
-		 * is the correct value.
-		 */
-		if (ec_int == IT83XX_INTC_IVCT(cpu_int_entry_number))
-			break;
-	}
-	/* Determine interrupt number */
-	ec_int -= 16;
-#else /* defined(CHIP_FAMILY_IT8XXX2) RISCV core */
-	/* wait until two equal interrupt values are read */
-	do {
-		ec_int = IT83XX_INTC_AIVCT;
-	} while (ec_int != IT83XX_INTC_AIVCT);
-	ec_int -= 0x10;
-	/* Unsupported EC INT number. */
-	if (chip_get_intc_group(ec_int) >= 16)
-		return -1;
-#endif
-	return ec_int;
-}
-
-int chip_get_intc_group(int irq)
-{
-	return irq_groups[irq / 8].cpu_int[irq % 8];
-}
-
-void chip_enable_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* SOC's interrupts share CPU machine-mode external interrupt */
-	if (IS_ENABLED(CHIP_CORE_RISCV))
-		IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit);
-
-	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
-	if (IS_ENABLED(CHIP_CORE_NDS32))
-		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit);
-}
-
-void chip_disable_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* SOC's interrupts share CPU machine-mode external interrupt */
-	if (IS_ENABLED(CHIP_CORE_RISCV)) {
-		volatile uint8_t _ier __unused;
-
-		IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit);
-		/*
-		 * This load operation will guarantee the above modification of
-		 * EC's register can be seen by any following instructions.
-		 */
-		_ier = IT83XX_INTC_REG(irq_groups[group].ier_off);
-	}
-
-	/* SOC's interrupts use CPU HW interrupt 2 ~ 15 */
-	if (IS_ENABLED(CHIP_CORE_NDS32)) {
-		volatile uint8_t _ext_ier __unused;
-
-		IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit);
-		/*
-		 * This load operation will guarantee the above modification of
-		 * EC's register can be seen by any following instructions.
-		 */
-		_ext_ier = IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group));
-	}
-}
-
-void chip_clear_pending_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	/* always write 1 clear, no | */
-	IT83XX_INTC_REG(irq_groups[group].isr_off) = BIT(bit);
-}
-
-int chip_trigger_irq(int irq)
-{
-	int group = irq / 8;
-	int bit = irq % 8;
-
-	return irq_groups[group].cpu_int[bit];
-}
-
-void chip_init_irqs(void)
-{
-	int i;
-
-	/* Clear all IERx and EXT_IERx */
-	for (i = 0; i < ARRAY_SIZE(irq_groups); i++) {
-		IT83XX_INTC_REG(irq_groups[i].ier_off) = 0;
-		if (IS_ENABLED(CHIP_CORE_NDS32))
-			IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(i)) = 0;
-	}
-}
diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S
deleted file mode 100644
index 5265eb7253..0000000000
--- a/chip/it83xx/it83xx_fpu.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config_chip.h"
-
-/*
- * DLMB register = 0x80189:
- * Disable all interrupts and switching CPU's
- * ALU (Arithmetic Logic Unit) to floating point operation mode.
- * (IEEE standard 754 floating point)
- *
- * DLMB register = 0x80009:
- * Restore interrupts and ALU.
- */
-	.text
-	.align	2
-	.global	__addsf3
-	.type	__addsf3, @function
-__addsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point addition single-precision */
-	add45  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__addsf3, .-__addsf3
-
-	.text
-	.align	2
-	.global	__subsf3
-	.type	__subsf3, @function
-__subsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point subtraction single-precision */
-	sub45  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__subsf3, .-__subsf3
-
-	.text
-	.align	2
-	.global	__mulsf3
-	.type	__mulsf3, @function
-__mulsf3:
-#ifdef IT83XX_FPU_MUL_BY_DIV
-#define SIGN	$r2
-#define EXPOA	$r3
-#define MANTA	$r4
-#define VALUA	$r5
-#define EXPOB	$r6
-#define MANTB	$r7
-#define VALUB	$r8
-#define SPROD	$r15
-        /* save r6-r8 */
-	smw.adm	$r6, [$sp], $r8, #0x0
-	xor    SPROD, $r1, $r0  /* sign(A xor B) */
-	move   SIGN, #0x80000000
-	and    SPROD, SPROD, SIGN /* store sign bit */
-	slli   VALUA, $r0, 1    /* A<<1, (exponent and mantissa) */
-	slli   VALUB, $r1, 1    /* B<<1, (exponent and mantissa) */
-	srli   EXPOA, VALUA, 24 /* exponent(A) */
-	srli   EXPOB, VALUB, 24 /* exponent(B) */
-	slli   MANTA, VALUA, 7  /* A<<8, mantissa(A) with exponent's LSB */
-	slli   MANTB, VALUB, 7  /* A<<8, mantissa(B) with exponent's LSB */
-	beqz   VALUA, .LFzeroA  /* exponent(A) and mantissa (A) are zero */
-	beqc   EXPOA, 0xff, .LFinfnanA /* A is inf or NaN */
-	beqz   VALUB, .LFzeroB  /* exponent(B) and mantissa (B) are zero */
-	beqc   EXPOB, 0xff, .LFinfnanB /* B is inf or NaN */
-        /* A*B = A/(1/B) */
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	sethi  $r5, #0x3f800    /* r5 = 1.0f */
-	divsr  $r1,$r1,$r5,$r1  /* r1 = 1.0f / r1 */
-	divsr  $r0,$r0,$r0,$r1  /* r0 = r0 / r1 */
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-.LFret:
-	/* restore r6-r8  */
-	lmw.bim	$r6, [$sp], $r8, #0x0
-	ret5	$lp
-
-.LFzeroA:                       /* A is zero */
-	beqc EXPOB, 0xff, .LFnan/*zero * inf = zero * NaN = NaN */
-.LFzero:
-	move $r0, SPROD         /* return 0.0f or -0.0f */
-	b    .LFret
-.LFinfnanA:                     /* exponent(A) is 0xff */
-	bne  MANTA, SIGN, .LFnan/* A is NaN: NaN * B = NaN */
-	beqz VALUB, .LFnan      /* A is inf and B is zero: inf * zero = NaN */
-	bnec EXPOB, 0xff, .LFinf/* B is finite: inf * B = inf */
-.LFinfnanB:                     /* exponent(B) is 0xff */
-	bne  MANTB, SIGN, .LFnan/* B is NaN: A * NaN = NaN */
-.LFinf:
-	move $r0, #0x7f800000
-	or   $r0, $r0, SPROD    /* return inf or -inf */
-	b   .LFret
-.LFzeroB:                       /* B is zero and A is finit */
-	b   .LFzero	        /* B is zero */
-.LFnan:
-	move $r0, #0xffc00000   /* return NaN */
-	b    .LFret
-#else  /* !IT83XX_FPU_MUL_BY_DIV */
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point multiplication single-precision */
-	mul33  $r0, $r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-#endif /* IT83XX_FPU_MUL_BY_DIV */
-	.size	__mulsf3, .-__mulsf3
-
-	.text
-	.align	2
-	.global	__divsf3
-	.type	__divsf3, @function
-__divsf3:
-	sethi  $r2, 0x80        /* r2 = 0x80000 */
-	addi   $r3, $r2, 0x189  /* r3 = 0x80189 */
-	addi45 $r2, 0x9         /* r2 = 0x80009 */
-	mtsr   $r3, $dlmb       /* dlmb = 0x80189 */
-	dsb
-	/* Floating-point division single-precision */
-	divsr  $r0,$r0,$r0,$r1
-	mtsr   $r2, $dlmb       /* dlmb = 0x80009 */
-	dsb
-	ret5   $lp
-	.size	__divsf3, .-__divsf3
diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c
deleted file mode 100644
index 6c7a10c463..0000000000
--- a/chip/it83xx/keyboard_raw.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "irq_chip.h"
-
-#define KSOH_PIN_MASK (((1 << (KEYBOARD_COLS_MAX - 8)) - 1) & 0xff)
-
-/*
- * Initialize the raw keyboard interface.
- */
-void keyboard_raw_init(void)
-{
-	uint32_t int_mask;
-
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * bit2, Setting 1 enables the internal pull-up of the KSO[15:0] pins.
-	 * To pull up KSO[17:16], set the GPCR registers of their
-	 * corresponding GPIO ports.
-	 * bit0, Setting 1 enables the open-drain mode of the KSO[17:0] pins.
-	 */
-	IT83XX_KBS_KSOCTRL = 0x05;
-
-	/* bit2, 1 enables the internal pull-up of the KSI[7:0] pins. */
-	IT83XX_KBS_KSICTRL = 0x04;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* KSO[2] is high, others are low. */
-	IT83XX_KBS_KSOL = BIT(2);
-	/* Enable KSO2's push-pull */
-	IT83XX_KBS_KSOLGCTRL |= BIT(2);
-	IT83XX_KBS_KSOLGOEN |= BIT(2);
-#else
-	/* KSO[7:0] pins low. */
-	IT83XX_KBS_KSOL = 0x00;
-#endif
-
-	/* critical section with interrupts off */
-	int_mask = read_clear_int_mask();
-	/*
-	 * KSO[COLS_MAX:8] pins low.
-	 * NOTE: KSO[15:8] pins can part be enabled for keyboard function and
-	 *       rest be configured as GPIO output mode. In this case that we
-	 *       disable the ISR in critical section to avoid race condition.
-	 */
-	IT83XX_KBS_KSOH1 &= ~KSOH_PIN_MASK;
-	/* restore interrupts */
-	set_int_mask(int_mask);
-
-	/* KSI[0-7] falling-edge triggered is selected */
-	IT83XX_WUC_WUEMR3 = 0xFF;
-
-	/* W/C */
-	IT83XX_WUC_WUESR3 = 0xFF;
-
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-
-	/* Enable WUC for KSI[0-7] */
-	IT83XX_WUC_WUENR3 = 0xFF;
-}
-
-/*
- * Finish initialization after task scheduling has started.
- */
-void keyboard_raw_task_start(void)
-{
-	IT83XX_WUC_WUESR3 = 0xFF;
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-	task_enable_irq(IT83XX_IRQ_WKINTC);
-}
-
-/*
- * Drive the specified column low.
- */
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int mask;
-	uint32_t int_mask;
-
-	/* Tri-state all outputs */
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0xffff;
-	/* Assert all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;
-	/* Assert a single output */
-	else
-		mask = 0xffff ^ BIT(col);
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* KSO[2] is inverted. */
-	mask ^= BIT(2);
-#endif
-	IT83XX_KBS_KSOL = mask & 0xff;
-
-	/* critical section with interrupts off */
-	int_mask = read_clear_int_mask();
-	/*
-	 * Because IT83XX_KBS_KSOH1 register is shared by keyboard scan
-	 * out and GPIO output mode, so we don't drive all KSOH pins
-	 * here (this depends on how many keyboard matrix output pin
-	 * we are using).
-	 */
-	IT83XX_KBS_KSOH1 = (IT83XX_KBS_KSOH1 & ~KSOH_PIN_MASK) |
-		((mask >> 8) & KSOH_PIN_MASK);
-	/* restore interrupts */
-	set_int_mask(int_mask);
-}
-
-/*
- * Read raw row state.
- * Bits are 1 if signal is present, 0 if not present.
- */
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return IT83XX_KBS_KSI ^ 0xff;
-}
-
-/*
- * Enable or disable keyboard matrix scan interrupts.
- */
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		IT83XX_WUC_WUESR3 = 0xFF;
-		task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-		task_enable_irq(IT83XX_IRQ_WKINTC);
-	} else {
-		task_disable_irq(IT83XX_IRQ_WKINTC);
-	}
-}
-
-/*
- * Interrupt handler for keyboard matrix scan interrupt.
- */
-void keyboard_raw_interrupt(void)
-{
-	IT83XX_WUC_WUESR3 = 0xFF;
-	task_clear_pending_irq(IT83XX_IRQ_WKINTC);
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return !(IT83XX_GPIO_DATA_MIRROR(port) & BIT(id));
-}
diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h
deleted file mode 100644
index cf4169a1c4..0000000000
--- a/chip/it83xx/kmsc_chip.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard matrix scan control module for IT83xx. */
-
-#ifndef __CROS_EC_KMSC_CHIP_H
-#define __CROS_EC_KMSC_CHIP_H
-
-void keyboard_raw_interrupt(void);
-
-#endif /* __CROS_EC_KMSC_CHIP_H */
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
deleted file mode 100644
index 867d9e024f..0000000000
--- a/chip/it83xx/lpc.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "ec2i_chip.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "pwm.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-/* LPC PM channels */
-enum lpc_pm_ch {
-	LPC_PM1 = 0,
-	LPC_PM2,
-	LPC_PM3,
-	LPC_PM4,
-	LPC_PM5,
-};
-
-enum pm_ctrl_mask {
-	/* Input Buffer Full Interrupt Enable. */
-	PM_CTRL_IBFIE = 0x01,
-	/* Output Buffer Empty Interrupt Enable. */
-	PM_CTRL_OBEIE = 0x02,
-};
-
-#define LPC_ACPI_CMD      LPC_PM1   /* ACPI commands 62h/66h port */
-#define LPC_HOST_CMD      LPC_PM2   /* Host commands 200h/204h port */
-#define LPC_HOST_PORT_80H LPC_PM3   /* Host 80h port */
-
-static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE]
-			__attribute__((section(".h2ram.pool.acpiec")));
-static uint8_t host_cmd_memmap[256]
-			__attribute__((section(".h2ram.pool.hostcmd")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-static int p80l_index;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)host_cmd_memmap;
-
-static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set)
-{
-	if (set)
-		IT83XX_PMC_PMCTL(ch) |= ctrl;
-	else
-		IT83XX_PMC_PMCTL(ch) &= ~ctrl;
-}
-
-static void pm_set_status(enum lpc_pm_ch ch, uint8_t status, int set)
-{
-	if (set)
-		IT83XX_PMC_PMSTS(ch) |= status;
-	else
-		IT83XX_PMC_PMSTS(ch) &= ~status;
-}
-
-static uint8_t pm_get_status(enum lpc_pm_ch ch)
-{
-	return IT83XX_PMC_PMSTS(ch);
-}
-
-static uint8_t pm_get_data_in(enum lpc_pm_ch ch)
-{
-	return IT83XX_PMC_PMDI(ch);
-}
-
-static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out)
-{
-	IT83XX_PMC_PMDO(ch) = out;
-}
-
-static void pm_clear_ibf(enum lpc_pm_ch ch)
-{
-	/* bit7, write-1 clear IBF */
-	IT83XX_PMC_PMIE(ch) |= BIT(7);
-}
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-static void keyboard_irq_assert(void)
-{
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-}
-#endif
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_SMI_L, 0);
-	udelay(65);
-	espi_vw_set_wire(VW_SMI_L, 1);
-#else
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#endif
-}
-
-static void lpc_generate_sci(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_SCI_L, 0);
-	udelay(65);
-	espi_vw_set_wire(VW_SCI_L, 1);
-#else
-	gpio_set_level(GPIO_PCH_SCI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SCI_L, 1);
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the OBF status bit. */
-	pm_put_data_out(LPC_HOST_CMD, args->result);
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-}
-
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable PMC1 interrupt while updating status register */
-	task_disable_irq(IT83XX_IRQ_PMC_IN);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 1);
-	} else {
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 0);
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 1);
-	} else {
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 0);
-	}
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte. */
-	pm_put_data_out(LPC_HOST_CMD, pkt->driver_result);
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)acpi_ec_memmap;
-}
-
-int lpc_keyboard_has_char(void)
-{
-	/* OBE or OBF */
-	return IT83XX_KBC_KBHISR & 0x01;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	/* IBE or IBF */
-	return IT83XX_KBC_KBHISR & 0x02;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	/* Clear programming data bit 7-4 */
-	IT83XX_KBC_KBHISR &= 0x0F;
-
-	/* keyboard */
-	IT83XX_KBC_KBHISR |= 0x10;
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	/* The data output to the KBC Data Output Register. */
-	IT83XX_KBC_KBHIKDOR = chr;
-	task_enable_irq(IT83XX_IRQ_KBC_OUT);
-	if (send_irq)
-		keyboard_irq_assert();
-#else
-	/*
-	 * bit0 = 0, The IRQ1 is controlled by the IRQ1B bit in KBIRQR.
-	 * bit1 = 0, The IRQ12 is controlled by the IRQ12B bit in KBIRQR.
-	 */
-	IT83XX_KBC_KBHICR &= 0x3C;
-
-	/*
-	 * Enable the interrupt to keyboard driver in the host processor
-	 * via SERIRQ when the output buffer is full.
-	 */
-	if (send_irq)
-		IT83XX_KBC_KBHICR |= 0x01;
-
-	udelay(16);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	/* The data output to the KBC Data Output Register. */
-	IT83XX_KBC_KBHIKDOR = chr;
-	task_enable_irq(IT83XX_IRQ_KBC_OUT);
-#endif
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	/* bit6, write-1 clear OBF */
-	IT83XX_KBC_KBHICR |= BIT(6);
-	IT83XX_KBC_KBHICR &= ~BIT(6);
-	set_int_mask(int_mask);
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char()) {
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-		keyboard_irq_assert();
-#else
-		/* The IRQ1 is controlled by the IRQ1B bit in KBIRQR. */
-		IT83XX_KBC_KBHICR &= ~0x01;
-
-		/*
-		 * When the OBFKIE bit in KBC Host Interface Control Register
-		 * (KBHICR) is 0, the bit directly controls the IRQ1 signal.
-		 */
-		IT83XX_KBC_KBIRQR |= 0x01;
-#endif
-
-		task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-
-		task_enable_irq(IT83XX_IRQ_KBC_OUT);
-	}
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	pm_set_status(LPC_ACPI_CMD, mask, 1);
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	pm_set_status(LPC_ACPI_CMD, mask, 0);
-}
-
-#ifndef CONFIG_HOSTCMD_ESPI
-int lpc_get_pltrst_asserted(void)
-{
-	return !gpio_get_level(GPIO_PCH_PLTRST_L);
-}
-#endif
-
-#ifdef HAS_TASK_KEYPROTO
-/* KBC and PMC control modules */
-void lpc_kbc_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending()) {
-		keyboard_host_write(IT83XX_KBC_KBHIDIR,
-			(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
-		/* bit7, write-1 clear IBF */
-		IT83XX_KBC_KBHICR |= BIT(7);
-		IT83XX_KBC_KBHICR &= ~BIT(7);
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-
-void lpc_kbc_obe_interrupt(void)
-{
-	task_disable_irq(IT83XX_IRQ_KBC_OUT);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	if (!(IT83XX_KBC_KBHICR & 0x01)) {
-		IT83XX_KBC_KBIRQR &= ~0x01;
-
-		IT83XX_KBC_KBHICR |= 0x01;
-	}
-#endif
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-#endif /* HAS_TASK_KEYPROTO */
-
-void pm1_ibf_interrupt(void)
-{
-	int is_cmd;
-	uint8_t value, result;
-
-	if (pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_FROM_HOST) {
-		/* Set the busy bit */
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 1);
-
-		/* data from command port or data port */
-		is_cmd = pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_LAST_CMD;
-
-		/* Get command or data */
-		value = pm_get_data_in(LPC_ACPI_CMD);
-
-		/* Handle whatever this was. */
-		if (acpi_ap_to_ec(is_cmd, value, &result))
-			pm_put_data_out(LPC_ACPI_CMD, result);
-
-		pm_clear_ibf(LPC_ACPI_CMD);
-
-		/* Clear the busy bit */
-		pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0);
-
-		/*
-		 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty
-		 * Output Buffer Full condition on the kernel channel.
-		 */
-		lpc_generate_sci();
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
-}
-
-void pm2_ibf_interrupt(void)
-{
-	uint8_t value __attribute__((unused)) = 0;
-	uint8_t status;
-
-	status = pm_get_status(LPC_HOST_CMD);
-	/* IBE */
-	if (!(status & EC_LPC_STATUS_FROM_HOST)) {
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	}
-
-	/* IBF and data port */
-	if (!(status & EC_LPC_STATUS_LAST_CMD)) {
-		/* R/C IBF*/
-		value = pm_get_data_in(LPC_HOST_CMD);
-		pm_clear_ibf(LPC_HOST_CMD);
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	}
-
-	/* Set the busy bit */
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 1);
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = pm_get_data_in(LPC_HOST_CMD);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	if (host_cmd_args.command != EC_COMMAND_PROTOCOL_3)
-		host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)host_cmd_memmap;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)host_cmd_memmap;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-
-		pm_clear_ibf(LPC_HOST_CMD);
-		task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-		return;
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-
-	pm_clear_ibf(LPC_HOST_CMD);
-	task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-}
-
-void pm3_ibf_interrupt(void)
-{
-	int new_p80_idx, i;
-	enum ec2i_message ec2i_r;
-
-	/* set LDN */
-	if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) {
-		/* get P80L current index */
-		ec2i_r = ec2i_read(HOST_INDEX_DSLDC6);
-		/* clear IBF */
-		pm_clear_ibf(LPC_HOST_PORT_80H);
-		/* read OK */
-		if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS) {
-			new_p80_idx = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK;
-			for (i = 0; i < (P80L_P80LE - P80L_P80LB + 1); i++) {
-				if (++p80l_index > P80L_P80LE)
-					p80l_index = P80L_P80LB;
-				port_80_write(IT83XX_BRAM_BANK1(p80l_index));
-				if (p80l_index == new_p80_idx)
-					break;
-			}
-		}
-	} else {
-		pm_clear_ibf(LPC_HOST_PORT_80H);
-	}
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
-}
-
-void pm4_ibf_interrupt(void)
-{
-	pm_clear_ibf(LPC_PM4);
-	task_clear_pending_irq(IT83XX_IRQ_PMC4_IN);
-}
-
-void pm5_ibf_interrupt(void)
-{
-	pm_clear_ibf(LPC_PM5);
-	task_clear_pending_irq(IT83XX_IRQ_PMC5_IN);
-}
-
-static void lpc_init(void)
-{
-	enum ec2i_message ec2i_r;
-
-	/* SPI peripheral interface is disabled */
-	IT83XX_GCTRL_SSCR = 0;
-	/*
-	 * DLM 52k~56k size select enable.
-	 * For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF.
-	 */
-	IT83XX_GCTRL_MCCR2 |= 0x10;
-
-	/* The register pair to access PNPCFG is 004Eh and 004Fh */
-	IT83XX_GCTRL_BADRSEL = 0x01;
-
-	/* Disable KBC IRQ */
-	IT83XX_KBC_KBIRQR = 0x00;
-
-	/*
-	 * bit2, Output Buffer Empty CPU Interrupt Enable.
-	 * bit3, Input Buffer Full CPU Interrupt Enable.
-	 * bit5, IBF/OBF EC clear mode.
-	 *   0b: IBF cleared if EC read data register, EC reset, or host reset.
-	 *       OBF cleared if host read data register, or EC reset.
-	 *   1b: IBF cleared if EC write-1 to bit7 at related registers,
-	 *       EC reset, or host reset.
-	 *       OBF cleared if host read data register, EC write-1 to bit6 at
-	 *       related registers, or EC reset.
-	 */
-	IT83XX_KBC_KBHICR |= 0x2C;
-
-	/* PM1 Input Buffer Full Interrupt Enable for 62h/66 port */
-	pm_set_ctrl(LPC_ACPI_CMD, PM_CTRL_IBFIE, 1);
-
-	/* PM2 Input Buffer Full Interrupt Enable for 200h/204 port */
-	pm_set_ctrl(LPC_HOST_CMD, PM_CTRL_IBFIE, 1);
-
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-
-	/* Host LPC I/O cycle mapping to RAM */
-#ifdef IT83XX_H2RAM_REMAPPING
-	/*
-	 * On it8xxx2 series, host I/O cycles are mapped to the first block
-	 * (0x80080000~0x80080fff) at default, and it is adjustable.
-	 * We should set the correct offset depends on the base address of
-	 * H2RAM section, so EC will be able to receive/handle commands from
-	 * host.
-	 */
-	IT83XX_GCTRL_H2ROFSR =
-		(CONFIG_H2RAM_BASE - CONFIG_RAM_BASE) / CONFIG_H2RAM_SIZE;
-#endif
-	/*
-	 * bit[4], H2RAM through LPC IO cycle.
-	 * bit[1], H2RAM window 1 enabled.
-	 * bit[0], H2RAM window 0 enabled.
-	 */
-	IT83XX_SMFI_HRAMWC |= 0x13;
-
-	/*
-	 * bit[7:6]
-	 * Host RAM Window[x] Read Protect Enable
-	 * 00b: Disabled
-	 * 01b: Lower half of RAM window protected
-	 * 10b: Upper half of RAM window protected
-	 * 11b: All protected
-	 *
-	 * bit[5:4]
-	 * Host RAM Window[x] Write Protect Enable
-	 * 00b: Disabled
-	 * 01b: Lower half of RAM window protected
-	 * 10b: Upper half of RAM window protected
-	 * 11b: All protected
-	 *
-	 * bit[2:0]
-	 * Host RAM Window 1 Size (HRAMW1S)
-	 * 0h: 16 bytes
-	 * 1h: 32 bytes
-	 * 2h: 64 bytes
-	 * 3h: 128 bytes
-	 * 4h: 256 bytes
-	 * 5h: 512 bytes
-	 * 6h: 1024 bytes
-	 * 7h: 2048 bytes
-	 */
-
-	/* H2RAM Win 0 Base Address 800h allow r/w for host_cmd_memmap */
-	IT83XX_SMFI_HRAMW0BA = 0x80;
-	IT83XX_SMFI_HRAMW0AAS = 0x04;
-
-	/* H2RAM Win 1 Base Address 900h allow r for acpi_ec_memmap */
-	IT83XX_SMFI_HRAMW1BA = 0x90;
-	IT83XX_SMFI_HRAMW1AAS = 0x34;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/*
-	 * bit[5], Dedicated interrupt
-	 * INT3: PMC1 Output Buffer Empty Int
-	 * INT25: PMC1 Input Buffer Full Int
-	 * INT26: PMC2 Output Buffer Empty Int
-	 * INT27: PMC2 Input Buffer Full Int
-	 */
-	IT83XX_PMC_MBXCTRL |= 0x20;
-
-	/* PM3 Input Buffer Full Interrupt Enable for 80h port */
-	pm_set_ctrl(LPC_HOST_PORT_80H, PM_CTRL_IBFIE, 1);
-
-	p80l_index = P80L_P80LC;
-	if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) {
-		/* get P80L current index */
-		ec2i_r = ec2i_read(HOST_INDEX_DSLDC6);
-		/* read OK */
-		if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS)
-			p80l_index = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK;
-	}
-
-	/*
-	 * bit[7], enable P80L function.
-	 * bit[6], accept port 80h cycle.
-	 * bit[1-0], 10b: I2EC is read-only.
-	 */
-	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
-
-#ifndef CONFIG_HOSTCMD_ESPI
-	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
-#endif
-
-#ifdef HAS_TASK_KEYPROTO
-	task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
-	task_disable_irq(IT83XX_IRQ_KBC_OUT);
-
-	task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
-	task_enable_irq(IT83XX_IRQ_KBC_IN);
-#endif
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
-	pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0);
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
-	pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0);
-	task_enable_irq(IT83XX_IRQ_PMC2_IN);
-
-	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
-	task_enable_irq(IT83XX_IRQ_PMC3_IN);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_init();
-#endif
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifndef CONFIG_HOSTCMD_ESPI
-void lpcrst_interrupt(enum gpio_signal signal)
-{
-	if (lpc_get_pltrst_asserted())
-		/* Store port 80 reset event */
-		port_80_write(PORT_80_EVENT_RESET);
-
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
-}
-#endif
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(IT83XX_IRQ_PMC_IN);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(IT83XX_IRQ_PMC_IN);
-}
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c
deleted file mode 100644
index 07336eaaf6..0000000000
--- a/chip/it83xx/peci.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "clock.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "util.h"
-#include "timer.h"
-#include "task.h"
-
-enum peci_status {
-	PECI_STATUS_NO_ERR        = 0x00,
-	PECI_STATUS_HOBY          = 0x01,
-	PECI_STATUS_FINISH        = 0x02,
-	PECI_STATUS_RD_FCS_ERR    = 0x04,
-	PECI_STATUS_WR_FCS_ERR    = 0x08,
-	PECI_STATUS_EXTERR        = 0x20,
-	PECI_STATUS_BUSERR        = 0x40,
-	PECI_STATUS_RCV_ERRCODE   = 0x80,
-	PECI_STATUS_ERR_NEED_RST  = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
-	PECI_STATUS_ANY_ERR       = (PECI_STATUS_RCV_ERRCODE |
-					PECI_STATUS_BUSERR |
-					PECI_STATUS_EXTERR |
-					PECI_STATUS_WR_FCS_ERR |
-					PECI_STATUS_RD_FCS_ERR),
-	PECI_STATUS_ANY_BIT       = 0xFE,
-	PECI_STATUS_TIMEOUT       = 0xFF,
-};
-
-static task_id_t peci_current_task;
-
-static void peci_init_vtt_freq(void)
-{
-	/*
-	 * bit2, enable the PECI interrupt generated by data valid event
-	 * from PECI.
-	 *
-	 * bit[1-0], these bits are used to set PECI VTT level.
-	 * 00b: 1.10v
-	 * 01b: 1.05v
-	 * 10b: 1.00v
-	 */
-	IT83XX_PECI_PADCTLR = 0x06;
-
-	/*
-	 * bit[2-0], these bits are used to set PECI host's optimal
-	 * transfer rate.
-	 * 000b: 2.0 MHz
-	 * 001b: 1.0 MHz
-	 * 100b: 1.6 MHz
-	 */
-	IT83XX_PECI_HOCTL2R = 0x01;
-}
-
-static void peci_reset(void)
-{
-	/* Reset PECI */
-	IT83XX_GCTRL_RSTC4 |= 0x10;
-
-	/* short delay */
-	udelay(15);
-
-	peci_init_vtt_freq();
-}
-
-/**
- * Start a PECI transaction
- *
- * @param  peci transaction data
- *
- * @return zero if successful, non-zero if error
- */
-int peci_transaction(struct peci_data *peci)
-{
-	uint8_t status;
-	int index;
-
-	/* To enable PECI function pin */
-	IT83XX_GPIO_GPCRF6 = 0x00;
-
-	/*
-	 * bit5, Both write and read data FIFO pointers will be cleared.
-	 *
-	 * bit4, This bit enables the PECI host to abort the transaction
-	 *       when FCS error occurs.
-	 *
-	 * bit2, This bit enables the contention mechanism of the PECI bus.
-	 *       When this bit is set, the host will abort the transaction
-	 *       if the PECI bus is contentious.
-	 */
-	IT83XX_PECI_HOCTLR |= 0x34;
-
-	/* This register is the target address field of the PECI protocol. */
-	IT83XX_PECI_HOTRADDR = peci->addr;
-
-	/* This register is the write length field of the PECI protocol. */
-	ASSERT(peci->w_len <= PECI_WRITE_DATA_FIFO_SIZE);
-
-	if (peci->cmd_code == PECI_CMD_PING) {
-		/* write length is 0 */
-		IT83XX_PECI_HOWRLR = 0x00;
-	} else {
-		if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_IAMSR) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
-
-			/* write length include Cmd Code + AW FCS */
-			IT83XX_PECI_HOWRLR = peci->w_len + 2;
-
-			/* bit1, The bit enables the AW_FCS hardwired mechanism
-			 * based on the PECI command. This bit is functional
-			 * only when the AW_FCS supported command of
-			 * PECI 2.0/3.0/3.1 is issued.
-			 * When this bit is set, the hardware will handle the
-			 * calculation of AW_FCS.
-			 */
-			IT83XX_PECI_HOCTLR |= 0x02;
-		} else {
-			/* write length include Cmd Code */
-			IT83XX_PECI_HOWRLR = peci->w_len + 1;
-
-			IT83XX_PECI_HOCTLR &= ~0x02;
-		}
-	}
-
-	/* This register is the read length field of the PECI protocol. */
-	ASSERT(peci->r_len <= PECI_READ_DATA_FIFO_SIZE);
-	IT83XX_PECI_HORDLR = peci->r_len;
-
-	/* This register is the command field of the PECI protocol. */
-	IT83XX_PECI_HOCMDR = peci->cmd_code;
-
-	/* The write data field of the PECI protocol. */
-	for (index = 0x00; index < peci->w_len; index++)
-		IT83XX_PECI_HOWRDR = peci->w_buf[index];
-
-	peci_current_task = task_get_current();
-	task_clear_pending_irq(IT83XX_IRQ_PECI);
-	task_enable_irq(IT83XX_IRQ_PECI);
-
-	/* start */
-	IT83XX_PECI_HOCTLR |= 0x01;
-
-	/* pre-set timeout */
-	index = peci->timeout_us;
-	if (task_wait_event(peci->timeout_us) != TASK_EVENT_TIMER)
-		index = 0;
-
-	task_disable_irq(IT83XX_IRQ_PECI);
-
-	peci_current_task = TASK_ID_INVALID;
-
-	if (index < peci->timeout_us) {
-
-		status = IT83XX_PECI_HOSTAR;
-
-		/* any error */
-		if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) {
-
-			if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST)
-				peci_reset();
-
-		} else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) {
-
-			/* The read data field of the PECI protocol. */
-			for (index = 0x00; index < peci->r_len; index++)
-				peci->r_buf[index] = IT83XX_PECI_HORDDR;
-
-			/* W/C */
-			IT83XX_PECI_HOSTAR = PECI_STATUS_FINISH;
-			status = IT83XX_PECI_HOSTAR;
-		}
-	} else {
-		/* transaction timeout */
-		status = PECI_STATUS_TIMEOUT;
-	}
-
-	/* Don't disable PECI host controller if controller already enable. */
-	IT83XX_PECI_HOCTLR = 0x08;
-
-	/* W/C */
-	IT83XX_PECI_HOSTAR = PECI_STATUS_ANY_BIT;
-
-	/* Disable PECI function pin */
-	IT83XX_GPIO_GPCRF6 = 0x80;
-
-	return status;
-}
-
-void peci_interrupt(void)
-{
-	task_clear_pending_irq(IT83XX_IRQ_PECI);
-	task_disable_irq(IT83XX_IRQ_PECI);
-
-	if (peci_current_task != TASK_ID_INVALID)
-		task_wake(peci_current_task);
-}
-
-static void peci_init(void)
-{
-	clock_enable_peripheral(CGC_OFFSET_PECI, 0, 0);
-	peci_init_vtt_freq();
-
-	/* bit3,this bit enables the PECI host controller. */
-	IT83XX_PECI_HOCTLR |= 0x08;
-
-	/* bit4, PECI enable */
-	IT83XX_GPIO_GRC2 |= 0x10;
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c
deleted file mode 100644
index fda8dd23d6..0000000000
--- a/chip/it83xx/pwm.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for IT83xx. */
-
-#include "clock.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-#include "math_util.h"
-
-#define PWM_CTRX_MIN 100
-#define PWM_EC_FREQ  8000000
-
-const struct pwm_ctrl_t pwm_ctrl_regs[] = {
-	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0},
-	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1},
-	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2},
-	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3},
-	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4},
-	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5},
-	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6},
-	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7},
-};
-
-const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = {
-	{ &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS,
-		&IT83XX_PWM_PCFSR, 0x01},
-	{ &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS,
-		&IT83XX_PWM_PCFSR, 0x02},
-	{ &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS,
-		&IT83XX_PWM_PCFSR, 0x04},
-	{ &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS,
-		&IT83XX_PWM_PCFSR, 0x08},
-};
-
-static int pwm_get_cycle_time(enum pwm_channel ch)
-{
-	int pcs_shift;
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* bit shift for "Prescaler Clock Source Select Group" register. */
-	pcs_shift = (ch % 4) * 2;
-
-	/* setting of "Prescaler Clock Source Select Group" register. */
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> pcs_shift) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	return cycle_time_setting;
-}
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	/* pwm channel mapping */
-	int pwm_reg_index = pwm_channels[ch].channel;
-
-	/*
-	 * enabled : pin to PWM function.
-	 * disabled : pin to GPIO input function.
-	 */
-	if (enabled)
-		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x00;
-	else
-		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x80 |
-			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ?
-			4 : 2);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* pin is PWM function and PWMs clock counter was enabled */
-	return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 &&
-		IT83XX_PWM_ZTIER & 0x02) ? 1 : 0;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int pcs_shift;
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* bit shift for "Prescaler Clock Source Select Group" register. */
-	pcs_shift = (ch % 4) * 2;
-
-	/* setting of "Prescaler Clock Source Select Group" register.*/
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> pcs_shift) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	/* to update PWM DCRx depend on CTRx setting. */
-	if (percent == 100) {
-		*pwm_ctrl_regs[ch].pwm_duty = cycle_time_setting;
-	} else {
-		*pwm_ctrl_regs[ch].pwm_duty =
-			((cycle_time_setting + 1) * percent) / 100;
-	}
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	int pcs_mask;
-	int pcs_reg;
-	int cycle_time_setting;
-	int percent;
-	int ch_idx;
-
-	ch_idx = ch;
-
-	/* pwm channel mapping */
-	ch = pwm_channels[ch].channel;
-
-	/* setting of "Prescaler Clock Source Select Group" register.*/
-	pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source;
-
-	/* only bit0 bit1 information. */
-	pcs_mask = (pcs_reg >> ((ch % 4) * 2)) & 0x03;
-
-	/* get cycle time setting of PWM channel x. */
-	cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time;
-
-	percent = *pwm_ctrl_regs[ch].pwm_duty * 100 / cycle_time_setting;
-
-	if (pwm_channels[ch_idx].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* output signal duty cycle. */
-	return percent;
-}
-
-void pwm_duty_inc(enum pwm_channel ch)
-{
-	int cycle_time, pwm_ch;
-
-	/* pwm channel mapping */
-	pwm_ch = pwm_channels[ch].channel;
-
-	cycle_time = pwm_get_cycle_time(ch);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty -= 1;
-	} else {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty += 1;
-	}
-}
-
-void pwm_duty_reduce(enum pwm_channel ch)
-{
-	int cycle_time, pwm_ch;
-
-	/* pwm channel mapping */
-	pwm_ch = pwm_channels[ch].channel;
-
-	cycle_time = pwm_get_cycle_time(ch);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty += 1;
-	} else {
-		if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0)
-			*pwm_ctrl_regs[pwm_ch].pwm_duty -= 1;
-	}
-}
-
-static int pwm_ch_freq(enum pwm_channel ch)
-{
-	int actual_freq = -1, targe_freq, deviation;
-	int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask;
-	int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ?
-							32768 : PWM_EC_FREQ;
-
-	targe_freq = pwm_channels[ch].freq_hz;
-	deviation = (targe_freq / 100) + 1;
-
-	for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) {
-		pcfsr = (pwm_clk_src / (ctr + 1) / targe_freq) - 1;
-		if (pcfsr >= 0) {
-			actual_freq = pwm_clk_src / (ctr + 1) / (pcfsr + 1);
-			if (ABS(actual_freq - targe_freq) < deviation)
-				break;
-		}
-	}
-
-	if (ctr < PWM_CTRX_MIN) {
-		actual_freq = -1;
-	} else {
-		pcfsr_sel = pwm_channels[ch].pcfsr_sel;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cycle_time = ctr;
-
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			/*
-			 * Select 32.768KHz as PWM clock source.
-]			 *
-			 * NOTE:
-			 * For pwm_channels[], the maximum supported pwm output
-			 * signal frequency is 324 Hz (32768/(PWM_CTRX_MIN+1)).
-			 */
-			*pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg &=
-				~pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl;
-		else
-			/* ec clock 8MHz */
-			*pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg |=
-				pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl;
-
-		/* pwm channel mapping */
-		ch = pwm_channels[ch].channel;
-
-		/*
-		 * bit shift for "Prescaler Clock Source Select Group"
-		 * register.
-		 */
-		pcs_shift = (ch % 4) * 2;
-		pcs_mask = pcfsr_sel << pcs_shift;
-
-		*pwm_ctrl_regs[ch].pwm_clock_source &= ~(0x3 << pcs_shift);
-		*pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask;
-
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb =
-			(pcfsr >> 8) & 0xFF;
-	}
-
-	return actual_freq;
-}
-
-static void pwm_init(void)
-{
-	int ch;
-
-	for (ch = 0; ch < PWM_CH_COUNT; ch++)
-		pwm_ch_freq(ch);
-
-	/*
-	 * The cycle timer1 of chip 8320 later series was enhanced from
-	 * 8bits to 10bits resolution, and others are still 8bit resolution.
-	 * Because the cycle timer1 high byte default value is not zero,
-	 * we clear cycle timer1 high byte at init and use it as 8-bit
-	 * resolution like others.
-	 */
-	IT83XX_PWM_CTR1M = 0;
-	/* enable PWMs clock counter. */
-	IT83XX_PWM_ZTIER |= 0x02;
-}
-
-/* The chip PWM module initialization. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h
deleted file mode 100644
index 4e8aba1c62..0000000000
--- a/chip/it83xx/pwm_chip.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for IT83xx. */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-enum pwm_pcfsr_sel {
-	PWM_PRESCALER_C4 = 1,
-	PWM_PRESCALER_C6 = 2,
-	PWM_PRESCALER_C7 = 3,
-};
-
-enum pwm_hw_channel {
-	PWM_HW_CH_DCR0 = 0,
-	PWM_HW_CH_DCR1,
-	PWM_HW_CH_DCR2,
-	PWM_HW_CH_DCR3,
-	PWM_HW_CH_DCR4,
-	PWM_HW_CH_DCR5,
-	PWM_HW_CH_DCR6,
-	PWM_HW_CH_DCR7,
-
-	PWM_HW_CH_TOTAL,
-};
-
-enum tach_ch_sel {
-	/* Pin GPIOD.6 */
-	TACH_CH_TACH0A = 0,
-	/* Pin GPIOD.7 */
-	TACH_CH_TACH1A,
-	/* Pin GPIOJ.2 */
-	TACH_CH_TACH0B,
-	/* Pin GPIOJ.3 */
-	TACH_CH_TACH1B,
-	/* Number of TACH channels */
-	TACH_CH_COUNT,
-
-	TACH_CH_NULL = 0xFF,
-};
-
-/* Data structure to define PWM channel control registers. */
-struct pwm_ctrl_t {
-	/* PWM channel output duty register. */
-	volatile uint8_t *pwm_duty;
-	/* PWM channel clock source selection register. */
-	volatile uint8_t *pwm_clock_source;
-	/* PWM channel pin control register. */
-	volatile uint8_t *pwm_pin;
-};
-
-/* Data structure to define PWM channel control registers part 2. */
-struct pwm_ctrl_t2 {
-	/* PWM cycle time register. */
-	volatile uint8_t *pwm_cycle_time;
-	/* PWM channel clock prescaler register (LSB). */
-	volatile uint8_t *pwm_cpr_lsb;
-	/* PWM channel clock prescaler register (MSB). */
-	volatile uint8_t *pwm_cpr_msb;
-	/* PWM prescaler clock frequency select register. */
-	volatile uint8_t *pwm_pcfsr_reg;
-	/* PWM prescaler clock frequency select register setting. */
-	uint8_t pwm_pcfsr_ctrl;
-};
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	int freq_hz;
-	enum pwm_pcfsr_sel pcfsr_sel;
-};
-
-/* Tachometer channel of each physical fan */
-struct fan_tach_t {
-	enum tach_ch_sel ch_tach;
-	/* the numbers of square pulses per revolution of fan. */
-	int fan_p;
-	/* allow actual rpm ~= targe rpm +- rpm_re */
-	int rpm_re;
-	/* startup duty of fan */
-	int s_duty;
-};
-
-extern const struct pwm_t pwm_channels[];
-/* The list of tachometer channel of fans is instantiated in board.c. */
-extern const struct fan_tach_t fan_tach[];
-
-void pwm_duty_inc(enum pwm_channel ch);
-void pwm_duty_reduce(enum pwm_channel ch);
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
deleted file mode 100644
index 34a2ddd6ae..0000000000
--- a/chip/it83xx/registers.h
+++ /dev/null
@@ -1,1678 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for IT83xx processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-#define __ram_code __attribute__((section(__RAM_CODE_SECTION_NAME)))
-
-/* IRQ numbers */
-/* Group 0 */
-#define IT83XX_IRQ_WKO20           1
-#define IT83XX_IRQ_KBC_OUT         2
-#define IT83XX_IRQ_PMC_OUT         3
-#define IT83XX_IRQ_SMB_D           4
-#define IT83XX_IRQ_WKINTAD         5
-#define IT83XX_IRQ_WKO23           6
-#define IT83XX_IRQ_PWM             7
-/* Group 1 */
-#define IT83XX_IRQ_ADC             8
-#define IT83XX_IRQ_SMB_A           9
-#define IT83XX_IRQ_SMB_B          10
-#define IT83XX_IRQ_KB_MATRIX      11
-#define IT83XX_IRQ_WKO26          12
-#define IT83XX_IRQ_WKINTC         13
-#define IT83XX_IRQ_WKO25          14
-#define IT83XX_IRQ_CIR            15
-/* Group 2 */
-#define IT83XX_IRQ_SMB_C          16
-#define IT83XX_IRQ_WKO24          17
-#define IT83XX_IRQ_PS2_2          18
-#define IT83XX_IRQ_PS2_1          19
-#define IT83XX_IRQ_PS2_0          20
-#define IT83XX_IRQ_WKO22          21
-#define IT83XX_IRQ_SMFI           22
-#define IT83XX_IRQ_USB            23
-/* Group 3 */
-#define IT83XX_IRQ_KBC_IN         24
-#define IT83XX_IRQ_PMC_IN         25
-#define IT83XX_IRQ_PMC2_OUT       26
-#define IT83XX_IRQ_PMC2_IN        27
-#define IT83XX_IRQ_GINT           28
-#define IT83XX_IRQ_EGPC           29
-#define IT83XX_IRQ_EXT_TIMER1     30
-#define IT83XX_IRQ_WKO21          31
-/* Group 4 */
-#define IT83XX_IRQ_GPINT0         32
-#define IT83XX_IRQ_GPINT1         33
-#define IT83XX_IRQ_GPINT2         34
-#define IT83XX_IRQ_GPINT3         35
-#define IT83XX_IRQ_CIR_GPINT      36
-#define IT83XX_IRQ_SSPI           37
-#define IT83XX_IRQ_UART1          38
-#define IT83XX_IRQ_UART2          39
-/* Group 5 */
-#define IT83XX_IRQ_WKO50          40
-#define IT83XX_IRQ_WKO51          41
-#define IT83XX_IRQ_WKO52          42
-#define IT83XX_IRQ_WKO53          43
-#define IT83XX_IRQ_WKO54          44
-#define IT83XX_IRQ_WKO55          45
-#define IT83XX_IRQ_WKO56          46
-#define IT83XX_IRQ_WKO57          47
-/* Group 6 */
-#define IT83XX_IRQ_WKO60          48
-#define IT83XX_IRQ_WKO61          49
-#define IT83XX_IRQ_WKO62          50
-#define IT83XX_IRQ_WKO63          51
-#define IT83XX_IRQ_WKO64          52
-#define IT83XX_IRQ_WKO65          53
-#define IT83XX_IRQ_WKO66          54
-#define IT83XX_IRQ_WKO67          55
-/* Group 7 */
-#define IT83XX_IRQ_RTCT_ALARM1    56
-#define IT83XX_IRQ_RTCT_ALARM2    57
-#define IT83XX_IRQ_EXT_TIMER2     58
-#define IT83XX_IRQ_DEFERRED_SPI   59
-#define IT83XX_IRQ_TMR_A0         60
-#define IT83XX_IRQ_TMR_A1         61
-#define IT83XX_IRQ_TMR_B0         62
-#define IT83XX_IRQ_TMR_B1         63
-/* Group 8 */
-#define IT83XX_IRQ_PMC2EX_OUT     64
-#define IT83XX_IRQ_PMC2EX_IN      65
-#define IT83XX_IRQ_PMC3_OUT       66
-#define IT83XX_IRQ_PMC3_IN        67
-#define IT83XX_IRQ_PMC4_OUT       68
-#define IT83XX_IRQ_PMC4_IN        69
-#define IT83XX_IRQ_I2BRAM         71
-/* Group 9 */
-#define IT83XX_IRQ_WKO70          72
-#define IT83XX_IRQ_WKO71          73
-#define IT83XX_IRQ_WKO72          74
-#define IT83XX_IRQ_WKO73          75
-#define IT83XX_IRQ_WKO74          76
-#define IT83XX_IRQ_WKO75          77
-#define IT83XX_IRQ_WKO76          78
-#define IT83XX_IRQ_WKO77          79
-/* Group 10 */
-#define IT83XX_IRQ_EXT_TMR8       80
-#define IT83XX_IRQ_SMB_CLOCK_HELD 81
-#define IT83XX_IRQ_CEC            82
-#define IT83XX_IRQ_H2RAM_LPC      83
-#define IT83XX_IRQ_HW_KB_SCAN     84
-#define IT83XX_IRQ_WKO88          85
-#define IT83XX_IRQ_WKO89          86
-#define IT83XX_IRQ_WKO90          87
-/* Group 11 */
-#define IT83XX_IRQ_WKO80          88
-#define IT83XX_IRQ_WKO81          89
-#define IT83XX_IRQ_WKO82          90
-#define IT83XX_IRQ_WKO83          91
-#define IT83XX_IRQ_WKO84          92
-#define IT83XX_IRQ_WKO85          93
-#define IT83XX_IRQ_WKO86          94
-#define IT83XX_IRQ_WKO87          95
-/* Group 12 */
-#define IT83XX_IRQ_WKO91          96
-#define IT83XX_IRQ_WKO92          97
-#define IT83XX_IRQ_WKO93          98
-#define IT83XX_IRQ_WKO94          99
-#define IT83XX_IRQ_WKO95          100
-#define IT83XX_IRQ_WKO96          101
-#define IT83XX_IRQ_WKO97          102
-#define IT83XX_IRQ_WKO98          103
-/* Group 13 */
-#define IT83XX_IRQ_WKO99          104
-#define IT83XX_IRQ_WKO100         105
-#define IT83XX_IRQ_WKO101         106
-#define IT83XX_IRQ_WKO102         107
-#define IT83XX_IRQ_WKO103         108
-#define IT83XX_IRQ_WKO104         109
-#define IT83XX_IRQ_WKO105         110
-#define IT83XX_IRQ_WKO106         111
-/* Group 14 */
-#define IT83XX_IRQ_WKO107         112
-#define IT83XX_IRQ_WKO108         113
-#define IT83XX_IRQ_WKO109         114
-#define IT83XX_IRQ_WKO110         115
-#define IT83XX_IRQ_WKO111         116
-#define IT83XX_IRQ_WKO112         117
-#define IT83XX_IRQ_WKO113         118
-#define IT83XX_IRQ_WKO114         119
-/* Group 15 */
-#define IT83XX_IRQ_WKO115         120
-#define IT83XX_IRQ_WKO116         121
-#define IT83XX_IRQ_WKO117         122
-#define IT83XX_IRQ_WKO118         123
-#define IT83XX_IRQ_WKO119         124
-#define IT83XX_IRQ_WKO120         125
-#define IT83XX_IRQ_WKO121         126
-#define IT83XX_IRQ_WKO122         127
-/* Group 16 */
-#define IT83XX_IRQ_WKO128         128
-#define IT83XX_IRQ_WKO129         129
-#define IT83XX_IRQ_WKO130         130
-#define IT83XX_IRQ_WKO131         131
-#define IT83XX_IRQ_WKO132         132
-#define IT83XX_IRQ_WKO133         133
-#define IT83XX_IRQ_WKO134         134
-#define IT83XX_IRQ_WKO135         135
-/* Group 17 */
-#define IT83XX_IRQ_WKO136         136
-#define IT83XX_IRQ_WKO137         137
-#define IT83XX_IRQ_WKO138         138
-#define IT83XX_IRQ_WKO139         139
-#define IT83XX_IRQ_WKO140         140
-#define IT83XX_IRQ_WKO141         141
-#define IT83XX_IRQ_WKO142         142
-#define IT83XX_IRQ_WKO143         143
-/* Group 18 */
-#define IT83XX_IRQ_WKO123         144
-#define IT83XX_IRQ_WKO124         145
-#define IT83XX_IRQ_WKO125         146
-#define IT83XX_IRQ_WKO126         147
-#define IT83XX_IRQ_PMC5_OUT       149
-#define IT83XX_IRQ_PMC5_IN        150
-#define IT83XX_IRQ_V_COMP         151
-/* Group 19 */
-#define IT83XX_IRQ_SMB_E          152
-#define IT83XX_IRQ_SMB_F          153
-#define IT83XX_IRQ_OSC_DMA        154
-#define IT83XX_IRQ_EXT_TIMER3     155
-#define IT83XX_IRQ_EXT_TIMER4     156
-#define IT83XX_IRQ_EXT_TIMER5     157
-#define IT83XX_IRQ_EXT_TIMER6     158
-#define IT83XX_IRQ_EXT_TIMER7     159
-/* Group 20 */
-#define IT83XX_IRQ_PECI           160
-#define IT83XX_IRQ_SOFTWARE       161
-#define IT83XX_IRQ_ESPI           162
-#define IT83XX_IRQ_ESPI_VW        163
-#define IT83XX_IRQ_PCH_P80        164
-#define IT83XX_IRQ_USBPD0         165
-#define IT83XX_IRQ_USBPD1         166
-/* Group 21 */
-#if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_IRQ_WKO40          168
-#define IT83XX_IRQ_WKO45          169
-#define IT83XX_IRQ_WKO46          170
-#define IT83XX_IRQ_WKO144         171
-#define IT83XX_IRQ_WKO145         172
-#define IT83XX_IRQ_WKO146         173
-#define IT83XX_IRQ_WKO147         174
-#define IT83XX_IRQ_WKO148         175
-/* Group 22 */
-#define IT83XX_IRQ_WKO149         176
-#define IT83XX_IRQ_WKO150         177
-
-#define IT83XX_IRQ_COUNT          178
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-/* Group 21 */
-#define IT83XX_IRQ_AUDIO_IF       170
-#define IT83XX_IRQ_SPI_PERIPHERAL 171
-#define IT83XX_IRQ_DSP_ENGINE     172
-#define IT83XX_IRQ_NN_ENGINE      173
-#define IT83XX_IRQ_USBPD2         174
-#define IT83XX_IRQ_CRYPTO         175
-/* Group 22 */
-#define IT83XX_IRQ_WKO40          176
-#define IT83XX_IRQ_WKO45          177
-#define IT83XX_IRQ_WKO46          178
-#define IT83XX_IRQ_WKO144         179
-#define IT83XX_IRQ_WKO145         180
-#define IT83XX_IRQ_WKO146         181
-#define IT83XX_IRQ_WKO147         182
-#define IT83XX_IRQ_WKO148         183
-/* Group 23 */
-#define IT83XX_IRQ_WKO149         184
-#define IT83XX_IRQ_WKO150         185
-#define IT83XX_IRQ_SSPI1          191
-/* Group 24 */
-#define IT83XX_IRQ_XLPIN0         192
-#define IT83XX_IRQ_XLPIN1         193
-#define IT83XX_IRQ_XLPIN2         194
-#define IT83XX_IRQ_XLPIN3         195
-#define IT83XX_IRQ_XLPIN4         196
-#define IT83XX_IRQ_XLPIN5         197
-#define IT83XX_IRQ_WEEK_ALARM     199
-/* Group 25 */
-#define IT83XX_IRQ_GPO0           200
-#define IT83XX_IRQ_GPO1           201
-#define IT83XX_IRQ_GPO2           202
-#define IT83XX_IRQ_GPO3           203
-/* Group 26 */
-#define IT83XX_IRQ_GPP0           208
-#define IT83XX_IRQ_GPP1           209
-#define IT83XX_IRQ_GPP2           210
-#define IT83XX_IRQ_GPP3           211
-#define IT83XX_IRQ_GPP4           212
-#define IT83XX_IRQ_GPP5           213
-#define IT83XX_IRQ_GPP6           214
-/* Group 27 */
-#define IT83XX_IRQ_GPQ0           216
-#define IT83XX_IRQ_GPQ1           217
-#define IT83XX_IRQ_GPQ2           218
-#define IT83XX_IRQ_GPQ3           219
-#define IT83XX_IRQ_GPQ4           220
-#define IT83XX_IRQ_GPQ5           221
-/* Group 28 */
-#define IT83XX_IRQ_GPR0           224
-#define IT83XX_IRQ_GPR1           225
-#define IT83XX_IRQ_GPR2           226
-#define IT83XX_IRQ_GPR3           227
-#define IT83XX_IRQ_GPR4           228
-#define IT83XX_IRQ_GPR5           229
-
-#define IT83XX_IRQ_COUNT          230
-#endif /* !defined(CHIP_FAMILY_IT8320) */
-
-/* IRQ dispatching to CPU INT vectors */
-#define IT83XX_CPU_INT_IRQ_1       2
-#define IT83XX_CPU_INT_IRQ_2       5
-#define IT83XX_CPU_INT_IRQ_3       4
-#define IT83XX_CPU_INT_IRQ_4       6
-#define IT83XX_CPU_INT_IRQ_5       2
-#define IT83XX_CPU_INT_IRQ_6       2
-#define IT83XX_CPU_INT_IRQ_7       4
-#define IT83XX_CPU_INT_IRQ_8       7
-#define IT83XX_CPU_INT_IRQ_9       6
-#define IT83XX_CPU_INT_IRQ_10      6
-#define IT83XX_CPU_INT_IRQ_11      5
-#define IT83XX_CPU_INT_IRQ_12      2
-#define IT83XX_CPU_INT_IRQ_13      2
-#define IT83XX_CPU_INT_IRQ_14      2
-#define IT83XX_CPU_INT_IRQ_15      8
-#define IT83XX_CPU_INT_IRQ_16      6
-#define IT83XX_CPU_INT_IRQ_17      2
-#define IT83XX_CPU_INT_IRQ_18      8
-#define IT83XX_CPU_INT_IRQ_19      8
-#define IT83XX_CPU_INT_IRQ_20      8
-#define IT83XX_CPU_INT_IRQ_21      2
-#define IT83XX_CPU_INT_IRQ_22     12
-#define IT83XX_CPU_INT_IRQ_23     12
-#define IT83XX_CPU_INT_IRQ_24      5
-#define IT83XX_CPU_INT_IRQ_25      4
-#define IT83XX_CPU_INT_IRQ_26      4
-#define IT83XX_CPU_INT_IRQ_27      4
-#define IT83XX_CPU_INT_IRQ_28     11
-#define IT83XX_CPU_INT_IRQ_29     11
-#define IT83XX_CPU_INT_IRQ_30      3
-#define IT83XX_CPU_INT_IRQ_31      2
-#define IT83XX_CPU_INT_IRQ_32     11
-#define IT83XX_CPU_INT_IRQ_33     11
-#define IT83XX_CPU_INT_IRQ_34     11
-#define IT83XX_CPU_INT_IRQ_35     11
-#define IT83XX_CPU_INT_IRQ_36      8
-#define IT83XX_CPU_INT_IRQ_37      9
-#define IT83XX_CPU_INT_IRQ_38      9
-#define IT83XX_CPU_INT_IRQ_39      9
-#define IT83XX_CPU_INT_IRQ_40      2
-#define IT83XX_CPU_INT_IRQ_41      2
-#define IT83XX_CPU_INT_IRQ_42      2
-#define IT83XX_CPU_INT_IRQ_43      2
-#define IT83XX_CPU_INT_IRQ_44      2
-#define IT83XX_CPU_INT_IRQ_45      2
-#define IT83XX_CPU_INT_IRQ_46      2
-#define IT83XX_CPU_INT_IRQ_47      2
-#define IT83XX_CPU_INT_IRQ_48      2
-#define IT83XX_CPU_INT_IRQ_49      2
-#define IT83XX_CPU_INT_IRQ_50      2
-#define IT83XX_CPU_INT_IRQ_51      2
-#define IT83XX_CPU_INT_IRQ_52      2
-#define IT83XX_CPU_INT_IRQ_53      2
-#define IT83XX_CPU_INT_IRQ_54      2
-#define IT83XX_CPU_INT_IRQ_55      2
-#define IT83XX_CPU_INT_IRQ_56     10
-#define IT83XX_CPU_INT_IRQ_57     10
-#define IT83XX_CPU_INT_IRQ_58      3
-#define IT83XX_CPU_INT_IRQ_59     12
-#define IT83XX_CPU_INT_IRQ_60      3
-#define IT83XX_CPU_INT_IRQ_61      3
-#define IT83XX_CPU_INT_IRQ_62      3
-#define IT83XX_CPU_INT_IRQ_63      3
-#define IT83XX_CPU_INT_IRQ_64      4
-#define IT83XX_CPU_INT_IRQ_65      4
-#define IT83XX_CPU_INT_IRQ_66      4
-#define IT83XX_CPU_INT_IRQ_67      4
-#define IT83XX_CPU_INT_IRQ_68      4
-#define IT83XX_CPU_INT_IRQ_69      4
-#define IT83XX_CPU_INT_IRQ_71     12
-#define IT83XX_CPU_INT_IRQ_72      2
-#define IT83XX_CPU_INT_IRQ_73      2
-#define IT83XX_CPU_INT_IRQ_74      2
-#define IT83XX_CPU_INT_IRQ_75      2
-#define IT83XX_CPU_INT_IRQ_76      2
-#define IT83XX_CPU_INT_IRQ_77      2
-#define IT83XX_CPU_INT_IRQ_78      2
-#define IT83XX_CPU_INT_IRQ_79      2
-#define IT83XX_CPU_INT_IRQ_80      3
-#define IT83XX_CPU_INT_IRQ_81      6
-#define IT83XX_CPU_INT_IRQ_82     12
-#define IT83XX_CPU_INT_IRQ_83     12
-#define IT83XX_CPU_INT_IRQ_84      5
-#define IT83XX_CPU_INT_IRQ_85      2
-#define IT83XX_CPU_INT_IRQ_86      2
-#define IT83XX_CPU_INT_IRQ_87      2
-#define IT83XX_CPU_INT_IRQ_88      2
-#define IT83XX_CPU_INT_IRQ_89      2
-#define IT83XX_CPU_INT_IRQ_90      2
-#define IT83XX_CPU_INT_IRQ_91      2
-#define IT83XX_CPU_INT_IRQ_92      2
-#define IT83XX_CPU_INT_IRQ_93      2
-#define IT83XX_CPU_INT_IRQ_94      2
-#define IT83XX_CPU_INT_IRQ_95      2
-#define IT83XX_CPU_INT_IRQ_96      2
-#define IT83XX_CPU_INT_IRQ_97      2
-#define IT83XX_CPU_INT_IRQ_98      2
-#define IT83XX_CPU_INT_IRQ_99      2
-#define IT83XX_CPU_INT_IRQ_100     2
-#define IT83XX_CPU_INT_IRQ_101     2
-#define IT83XX_CPU_INT_IRQ_102     2
-#define IT83XX_CPU_INT_IRQ_103     2
-#define IT83XX_CPU_INT_IRQ_104     2
-#define IT83XX_CPU_INT_IRQ_105     2
-#define IT83XX_CPU_INT_IRQ_106     2
-#define IT83XX_CPU_INT_IRQ_107     2
-#define IT83XX_CPU_INT_IRQ_108     2
-#define IT83XX_CPU_INT_IRQ_109     2
-#define IT83XX_CPU_INT_IRQ_110     2
-#define IT83XX_CPU_INT_IRQ_111     2
-#define IT83XX_CPU_INT_IRQ_112     2
-#define IT83XX_CPU_INT_IRQ_113     2
-#define IT83XX_CPU_INT_IRQ_114     2
-#define IT83XX_CPU_INT_IRQ_115     2
-#define IT83XX_CPU_INT_IRQ_116     2
-#define IT83XX_CPU_INT_IRQ_117     2
-#define IT83XX_CPU_INT_IRQ_118     2
-#define IT83XX_CPU_INT_IRQ_119     2
-#define IT83XX_CPU_INT_IRQ_120     2
-#define IT83XX_CPU_INT_IRQ_121     2
-#define IT83XX_CPU_INT_IRQ_122     2
-#define IT83XX_CPU_INT_IRQ_123     2
-#define IT83XX_CPU_INT_IRQ_124     2
-#define IT83XX_CPU_INT_IRQ_125     2
-#define IT83XX_CPU_INT_IRQ_126     2
-#define IT83XX_CPU_INT_IRQ_127     2
-#define IT83XX_CPU_INT_IRQ_128     2
-#define IT83XX_CPU_INT_IRQ_129     2
-#define IT83XX_CPU_INT_IRQ_130     2
-#define IT83XX_CPU_INT_IRQ_131     2
-#define IT83XX_CPU_INT_IRQ_132     2
-#define IT83XX_CPU_INT_IRQ_133     2
-#define IT83XX_CPU_INT_IRQ_134     2
-#define IT83XX_CPU_INT_IRQ_135     2
-#define IT83XX_CPU_INT_IRQ_136     2
-#define IT83XX_CPU_INT_IRQ_137     2
-#define IT83XX_CPU_INT_IRQ_138     2
-#define IT83XX_CPU_INT_IRQ_139     2
-#define IT83XX_CPU_INT_IRQ_140     2
-#define IT83XX_CPU_INT_IRQ_141     2
-#define IT83XX_CPU_INT_IRQ_142     2
-#define IT83XX_CPU_INT_IRQ_143     2
-#define IT83XX_CPU_INT_IRQ_144     2
-#define IT83XX_CPU_INT_IRQ_145     2
-#define IT83XX_CPU_INT_IRQ_146     2
-#define IT83XX_CPU_INT_IRQ_147     2
-#define IT83XX_CPU_INT_IRQ_149     4
-#define IT83XX_CPU_INT_IRQ_150     4
-#define IT83XX_CPU_INT_IRQ_151     7
-#define IT83XX_CPU_INT_IRQ_152     6
-#define IT83XX_CPU_INT_IRQ_153     6
-#define IT83XX_CPU_INT_IRQ_154    12
-#define IT83XX_CPU_INT_IRQ_155     3
-#define IT83XX_CPU_INT_IRQ_156     3
-#define IT83XX_CPU_INT_IRQ_157     3
-#define IT83XX_CPU_INT_IRQ_158     3
-#define IT83XX_CPU_INT_IRQ_159     3
-#define IT83XX_CPU_INT_IRQ_160    12
-#define IT83XX_CPU_INT_IRQ_161    12
-#define IT83XX_CPU_INT_IRQ_162    12
-#define IT83XX_CPU_INT_IRQ_163    12
-#define IT83XX_CPU_INT_IRQ_164    12
-#define IT83XX_CPU_INT_IRQ_165    12
-#define IT83XX_CPU_INT_IRQ_166    12
-#define IT83XX_CPU_INT_IRQ_167    12
-#define IT83XX_CPU_INT_IRQ_168     2
-#define IT83XX_CPU_INT_IRQ_169     2
-#if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_CPU_INT_IRQ_170     2
-#define IT83XX_CPU_INT_IRQ_171     2
-#define IT83XX_CPU_INT_IRQ_172     2
-#define IT83XX_CPU_INT_IRQ_173     2
-#define IT83XX_CPU_INT_IRQ_174     2
-#define IT83XX_CPU_INT_IRQ_175     2
-#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-#define IT83XX_CPU_INT_IRQ_170    12
-#define IT83XX_CPU_INT_IRQ_171    12
-#define IT83XX_CPU_INT_IRQ_172    12
-#define IT83XX_CPU_INT_IRQ_173    12
-#define IT83XX_CPU_INT_IRQ_174    12
-#define IT83XX_CPU_INT_IRQ_175    12
-#endif
-#define IT83XX_CPU_INT_IRQ_176     2
-#define IT83XX_CPU_INT_IRQ_177     2
-#define IT83XX_CPU_INT_IRQ_178     2
-#define IT83XX_CPU_INT_IRQ_179     2
-#define IT83XX_CPU_INT_IRQ_180     2
-#define IT83XX_CPU_INT_IRQ_181     2
-#define IT83XX_CPU_INT_IRQ_182     2
-#define IT83XX_CPU_INT_IRQ_183     2
-#define IT83XX_CPU_INT_IRQ_184     2
-#define IT83XX_CPU_INT_IRQ_185     2
-#define IT83XX_CPU_INT_IRQ_191     2
-#define IT83XX_CPU_INT_IRQ_192     2
-#define IT83XX_CPU_INT_IRQ_193     2
-#define IT83XX_CPU_INT_IRQ_194     2
-#define IT83XX_CPU_INT_IRQ_195     2
-#define IT83XX_CPU_INT_IRQ_196     2
-#define IT83XX_CPU_INT_IRQ_197     2
-#define IT83XX_CPU_INT_IRQ_199     2
-#define IT83XX_CPU_INT_IRQ_200     2
-#define IT83XX_CPU_INT_IRQ_201     2
-#define IT83XX_CPU_INT_IRQ_202     2
-#define IT83XX_CPU_INT_IRQ_203     2
-#define IT83XX_CPU_INT_IRQ_208     2
-#define IT83XX_CPU_INT_IRQ_209     2
-#define IT83XX_CPU_INT_IRQ_210     2
-#define IT83XX_CPU_INT_IRQ_211     2
-#define IT83XX_CPU_INT_IRQ_212     2
-#define IT83XX_CPU_INT_IRQ_213     2
-#define IT83XX_CPU_INT_IRQ_214     2
-#define IT83XX_CPU_INT_IRQ_216     2
-#define IT83XX_CPU_INT_IRQ_217     2
-#define IT83XX_CPU_INT_IRQ_218     2
-#define IT83XX_CPU_INT_IRQ_219     2
-#define IT83XX_CPU_INT_IRQ_220     2
-#define IT83XX_CPU_INT_IRQ_221     2
-#define IT83XX_CPU_INT_IRQ_224     2
-#define IT83XX_CPU_INT_IRQ_225     2
-#define IT83XX_CPU_INT_IRQ_226     2
-#define IT83XX_CPU_INT_IRQ_227     2
-#define IT83XX_CPU_INT_IRQ_228     2
-#define IT83XX_CPU_INT_IRQ_229     2
-
-/* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
-#define CPU_INT_2_ALL_GPIOS      255
-#define IT83XX_CPU_INT_IRQ_255     2
-
-#define CPU_INT_GROUP_5          254
-#define IT83XX_CPU_INT_IRQ_254     5
-
-#define CPU_INT_GROUP_4          252
-#define IT83XX_CPU_INT_IRQ_252     4
-
-#define CPU_INT_GROUP_12         253
-#define IT83XX_CPU_INT_IRQ_253    12
-
-#define CPU_INT_GROUP_3          251
-#define IT83XX_CPU_INT_IRQ_251     3
-
-#define CPU_INT_GROUP_6          250
-#define IT83XX_CPU_INT_IRQ_250     6
-
-#define CPU_INT_GROUP_9          249
-#define IT83XX_CPU_INT_IRQ_249     9
-
-#define CPU_INT_GROUP_7          248
-#define IT83XX_CPU_INT_IRQ_248     7
-
-#define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq)
-
-/* --- INTC --- */
-#define IT83XX_INTC_BASE    CHIP_EC_INTC_BASE
-
-#define IT83XX_INTC_REG(n)  REG8(IT83XX_INTC_BASE+(n))
-
-#define IT83XX_INTC_AIVCT   REG8(IT83XX_INTC_BASE+0x10)
-
-#define IT83XX_INTC_IER0    REG8(IT83XX_INTC_BASE+0x04)
-#define IT83XX_INTC_IER1    REG8(IT83XX_INTC_BASE+0x05)
-#define IT83XX_INTC_IER2    REG8(IT83XX_INTC_BASE+0x06)
-#define IT83XX_INTC_IER3    REG8(IT83XX_INTC_BASE+0x07)
-#define IT83XX_INTC_IER4    REG8(IT83XX_INTC_BASE+0x15)
-#define IT83XX_INTC_IER5    REG8(IT83XX_INTC_BASE+0x19)
-#define IT83XX_INTC_IER6    REG8(IT83XX_INTC_BASE+0x1d)
-#define IT83XX_INTC_IER7    REG8(IT83XX_INTC_BASE+0x21)
-#define IT83XX_INTC_IER8    REG8(IT83XX_INTC_BASE+0x25)
-#define IT83XX_INTC_IER9    REG8(IT83XX_INTC_BASE+0x29)
-#define IT83XX_INTC_IER10   REG8(IT83XX_INTC_BASE+0x2d)
-#define IT83XX_INTC_IER11   REG8(IT83XX_INTC_BASE+0x31)
-#define IT83XX_INTC_IER12   REG8(IT83XX_INTC_BASE+0x35)
-#define IT83XX_INTC_IER13   REG8(IT83XX_INTC_BASE+0x39)
-#define IT83XX_INTC_IER14   REG8(IT83XX_INTC_BASE+0x3d)
-#define IT83XX_INTC_IER15   REG8(IT83XX_INTC_BASE+0x41)
-#define IT83XX_INTC_IER16   REG8(IT83XX_INTC_BASE+0x45)
-#define IT83XX_INTC_IER17   REG8(IT83XX_INTC_BASE+0x49)
-#define IT83XX_INTC_IER18   REG8(IT83XX_INTC_BASE+0x4d)
-#define IT83XX_INTC_IER19   REG8(IT83XX_INTC_BASE+0x51)
-#define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
-#define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
-#define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
-#define IT83XX_INTC_IER23   REG8(IT83XX_INTC_BASE+0x91)
-#define IT83XX_INTC_IER24   REG8(IT83XX_INTC_BASE+0x95)
-#define IT83XX_INTC_IER25   REG8(IT83XX_INTC_BASE+0x99)
-#define IT83XX_INTC_IER26   REG8(IT83XX_INTC_BASE+0x9d)
-#define IT83XX_INTC_IER27   REG8(IT83XX_INTC_BASE+0xa1)
-#define IT83XX_INTC_IER28   REG8(IT83XX_INTC_BASE+0xa5)
-
-#define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
-#define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
-#define IT83XX_INTC_ISR2    REG8(IT83XX_INTC_BASE+0x02)
-#define IT83XX_INTC_ISR3    REG8(IT83XX_INTC_BASE+0x03)
-#define IT83XX_INTC_ISR4    REG8(IT83XX_INTC_BASE+0x14)
-#define IT83XX_INTC_ISR5    REG8(IT83XX_INTC_BASE+0x18)
-#define IT83XX_INTC_ISR6    REG8(IT83XX_INTC_BASE+0x1c)
-#define IT83XX_INTC_ISR7    REG8(IT83XX_INTC_BASE+0x20)
-#define IT83XX_INTC_ISR8    REG8(IT83XX_INTC_BASE+0x24)
-#define IT83XX_INTC_ISR9    REG8(IT83XX_INTC_BASE+0x28)
-#define IT83XX_INTC_ISR10   REG8(IT83XX_INTC_BASE+0x2c)
-#define IT83XX_INTC_ISR11   REG8(IT83XX_INTC_BASE+0x30)
-#define IT83XX_INTC_ISR12   REG8(IT83XX_INTC_BASE+0x34)
-#define IT83XX_INTC_ISR13   REG8(IT83XX_INTC_BASE+0x38)
-#define IT83XX_INTC_ISR14   REG8(IT83XX_INTC_BASE+0x3c)
-#define IT83XX_INTC_ISR15   REG8(IT83XX_INTC_BASE+0x40)
-#define IT83XX_INTC_ISR16   REG8(IT83XX_INTC_BASE+0x44)
-#define IT83XX_INTC_ISR17   REG8(IT83XX_INTC_BASE+0x48)
-#define IT83XX_INTC_ISR18   REG8(IT83XX_INTC_BASE+0x4c)
-#define IT83XX_INTC_ISR19   REG8(IT83XX_INTC_BASE+0x50)
-#define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
-#define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
-#define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
-#define IT83XX_INTC_ISR23   REG8(IT83XX_INTC_BASE+0x90)
-#define IT83XX_INTC_ISR24   REG8(IT83XX_INTC_BASE+0x94)
-#define IT83XX_INTC_ISR25   REG8(IT83XX_INTC_BASE+0x98)
-#define IT83XX_INTC_ISR26   REG8(IT83XX_INTC_BASE+0x9c)
-#define IT83XX_INTC_ISR27   REG8(IT83XX_INTC_BASE+0xa0)
-#define IT83XX_INTC_ISR28   REG8(IT83XX_INTC_BASE+0xa4)
-
-#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
-#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
-#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52)
-#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53)
-
-#define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n))
-#define IT83XX_INTC_IVCT(i)     REG8(IT83XX_INTC_BASE+0x80+(i))
-
-/* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */
-#define IT83XX_EC2I_BASE  0x00F01200
-
-#define IT83XX_EC2I_IHIOA       REG8(IT83XX_EC2I_BASE+0x00)
-#define IT83XX_EC2I_IHD         REG8(IT83XX_EC2I_BASE+0x01)
-#define IT83XX_EC2I_LSIOHA      REG8(IT83XX_EC2I_BASE+0x02)
-#define IT83XX_EC2I_SIOLV       REG8(IT83XX_EC2I_BASE+0x03)
-#define IT83XX_EC2I_IBMAE       REG8(IT83XX_EC2I_BASE+0x04)
-#define IT83XX_EC2I_IBCTL       REG8(IT83XX_EC2I_BASE+0x05)
-
-/* --- System Wake-UP Control (SWUC) --- */
-#define IT83XX_SWUC_BASE  0x00F01400
-#define IT83XX_SWUC_SWCTL1      REG8(IT83XX_SWUC_BASE+0x00)
-
-/* --- Wake-Up Control (WUC) --- */
-#define IT83XX_WUC_BASE   0x00F01B00
-
-#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00)
-#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c)
-#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04)
-#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d)
-#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c)
-#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f)
-
-#define IT83XX_WUC_WUESR10    REG8(IT83XX_WUC_BASE+0x21)
-#define IT83XX_WUC_WUESR11    REG8(IT83XX_WUC_BASE+0x25)
-
-#define IT83XX_WUC_WUEMR3     REG8(IT83XX_WUC_BASE+0x02)
-#define IT83XX_WUC_WUESR3     REG8(IT83XX_WUC_BASE+0x06)
-#define IT83XX_WUC_WUENR3     REG8(IT83XX_WUC_BASE+0x0A)
-
-#define IT83XX_WUC_WUEMR4     REG8(IT83XX_WUC_BASE+0x03)
-#define IT83XX_WUC_WUESR4     REG8(IT83XX_WUC_BASE+0x07)
-#define IT83XX_WUC_WUENR4     REG8(IT83XX_WUC_BASE+0x0B)
-
-/* --- UART --- */
-#define IT83XX_UART0_BASE 0x00F02700
-#define IT83XX_UART1_BASE 0x00F02800
-
-#define IT83XX_UART_BASE(n)        CONCAT3(IT83XX_UART, n, _BASE)
-#define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset))
-
-#define IT83XX_UART_DLL(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_DLM(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_RBR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_THR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_IER(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_IIR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_FCR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_LCR(n)         IT83XX_UART_REG(n, 0x03)
-#define IT83XX_UART_MCR(n)         IT83XX_UART_REG(n, 0x04)
-#define IT83XX_UART_LSR(n)         IT83XX_UART_REG(n, 0x05)
-#define IT83XX_UART_MSR(n)         IT83XX_UART_REG(n, 0x06)
-#define IT83XX_UART_SCR(n)         IT83XX_UART_REG(n, 0x07)
-#define IT83XX_UART_ECSMPR(n)      IT83XX_UART_REG(n, 0x08)
-#define IT83XX_UART_CSSR(n)        IT83XX_UART_REG(n, 0x09)
-
-/* --- GPIO --- */
-
-#define IT83XX_GPIO_BASE  0x00F01600
-#define IT83XX_GPIO2_BASE 0x00F03E00
-
-#define IT83XX_GPIO_GCR         REG8(IT83XX_GPIO_BASE+0x00)
-#define IT83XX_GPIO_GCR_LPC_RST_B7      0x1
-#define IT83XX_GPIO_GCR_LPC_RST_D2      0x2
-#define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3
-#define IT83XX_GPIO_GCR_LPC_RST_POS     1
-
-#define IT83XX_GPIO_GPDRA       REG8(IT83XX_GPIO_BASE+0x01)
-#define IT83XX_GPIO_GPDRB       REG8(IT83XX_GPIO_BASE+0x02)
-#define IT83XX_GPIO_GPDRC       REG8(IT83XX_GPIO_BASE+0x03)
-#define IT83XX_GPIO_GPDRE       REG8(IT83XX_GPIO_BASE+0x05)
-#define IT83XX_GPIO_GPDRF       REG8(IT83XX_GPIO_BASE+0x06)
-#define IT83XX_GPIO_GPDRH       REG8(IT83XX_GPIO_BASE+0x08)
-
-#define IT83XX_GPIO_GPCRA0      REG8(IT83XX_GPIO_BASE+0x10)
-#define IT83XX_GPIO_GPCRA1      REG8(IT83XX_GPIO_BASE+0x11)
-#define IT83XX_GPIO_GPCRA2      REG8(IT83XX_GPIO_BASE+0x12)
-#define IT83XX_GPIO_GPCRA3      REG8(IT83XX_GPIO_BASE+0x13)
-#define IT83XX_GPIO_GPCRA4      REG8(IT83XX_GPIO_BASE+0x14)
-#define IT83XX_GPIO_GPCRA5      REG8(IT83XX_GPIO_BASE+0x15)
-#define IT83XX_GPIO_GPCRA6      REG8(IT83XX_GPIO_BASE+0x16)
-#define IT83XX_GPIO_GPCRA7      REG8(IT83XX_GPIO_BASE+0x17)
-
-#define IT83XX_GPIO_GPCRB0      REG8(IT83XX_GPIO_BASE+0x18)
-#define IT83XX_GPIO_GPCRB1      REG8(IT83XX_GPIO_BASE+0x19)
-#define IT83XX_GPIO_GPCRB2      REG8(IT83XX_GPIO_BASE+0x1A)
-#define IT83XX_GPIO_GPCRB3      REG8(IT83XX_GPIO_BASE+0x1B)
-#define IT83XX_GPIO_GPCRB4      REG8(IT83XX_GPIO_BASE+0x1C)
-#define IT83XX_GPIO_GPCRB5      REG8(IT83XX_GPIO_BASE+0x1D)
-#define IT83XX_GPIO_GPCRB6      REG8(IT83XX_GPIO_BASE+0x1E)
-#define IT83XX_GPIO_GPCRB7      REG8(IT83XX_GPIO_BASE+0x1F)
-
-#define IT83XX_GPIO_GPCRC0      REG8(IT83XX_GPIO_BASE+0x20)
-#define IT83XX_GPIO_GPCRC1      REG8(IT83XX_GPIO_BASE+0x21)
-#define IT83XX_GPIO_GPCRC2      REG8(IT83XX_GPIO_BASE+0x22)
-#define IT83XX_GPIO_GPCRC3      REG8(IT83XX_GPIO_BASE+0x23)
-#define IT83XX_GPIO_GPCRC4      REG8(IT83XX_GPIO_BASE+0x24)
-#define IT83XX_GPIO_GPCRC5      REG8(IT83XX_GPIO_BASE+0x25)
-#define IT83XX_GPIO_GPCRC6      REG8(IT83XX_GPIO_BASE+0x26)
-#define IT83XX_GPIO_GPCRC7      REG8(IT83XX_GPIO_BASE+0x27)
-
-#define IT83XX_GPIO_GPCRE0      REG8(IT83XX_GPIO_BASE+0x30)
-#define IT83XX_GPIO_GPCRE1      REG8(IT83XX_GPIO_BASE+0x31)
-#define IT83XX_GPIO_GPCRE2      REG8(IT83XX_GPIO_BASE+0x32)
-#define IT83XX_GPIO_GPCRE3      REG8(IT83XX_GPIO_BASE+0x33)
-#define IT83XX_GPIO_GPCRE4      REG8(IT83XX_GPIO_BASE+0x34)
-#define IT83XX_GPIO_GPCRE5      REG8(IT83XX_GPIO_BASE+0x35)
-#define IT83XX_GPIO_GPCRE6      REG8(IT83XX_GPIO_BASE+0x36)
-#define IT83XX_GPIO_GPCRE7      REG8(IT83XX_GPIO_BASE+0x37)
-
-#define IT83XX_GPIO_GPCRF0      REG8(IT83XX_GPIO_BASE+0x38)
-#define IT83XX_GPIO_GPCRF1      REG8(IT83XX_GPIO_BASE+0x39)
-#define IT83XX_GPIO_GPCRF2      REG8(IT83XX_GPIO_BASE+0x3A)
-#define IT83XX_GPIO_GPCRF3      REG8(IT83XX_GPIO_BASE+0x3B)
-#define IT83XX_GPIO_GPCRF4      REG8(IT83XX_GPIO_BASE+0x3C)
-#define IT83XX_GPIO_GPCRF5      REG8(IT83XX_GPIO_BASE+0x3D)
-#define IT83XX_GPIO_GPCRF6      REG8(IT83XX_GPIO_BASE+0x3E)
-#define IT83XX_GPIO_GPCRF7      REG8(IT83XX_GPIO_BASE+0x3F)
-
-#define IT83XX_GPIO_GPCRH0      REG8(IT83XX_GPIO_BASE+0x48)
-#define IT83XX_GPIO_GPCRH1      REG8(IT83XX_GPIO_BASE+0x49)
-#define IT83XX_GPIO_GPCRH2      REG8(IT83XX_GPIO_BASE+0x4A)
-#define IT83XX_GPIO_GPCRH3      REG8(IT83XX_GPIO_BASE+0x4B)
-#define IT83XX_GPIO_GPCRH4      REG8(IT83XX_GPIO_BASE+0x4C)
-#define IT83XX_GPIO_GPCRH5      REG8(IT83XX_GPIO_BASE+0x4D)
-#define IT83XX_GPIO_GPCRH6      REG8(IT83XX_GPIO_BASE+0x4E)
-#define IT83XX_GPIO_GPCRH7      REG8(IT83XX_GPIO_BASE+0x4F)
-
-#define IT83XX_GPIO_GPCRI0      REG8(IT83XX_GPIO_BASE+0x50)
-#define IT83XX_GPIO_GPCRI1      REG8(IT83XX_GPIO_BASE+0x51)
-#define IT83XX_GPIO_GPCRI2      REG8(IT83XX_GPIO_BASE+0x52)
-#define IT83XX_GPIO_GPCRI3      REG8(IT83XX_GPIO_BASE+0x53)
-#define IT83XX_GPIO_GPCRI4      REG8(IT83XX_GPIO_BASE+0x54)
-#define IT83XX_GPIO_GPCRI5      REG8(IT83XX_GPIO_BASE+0x55)
-#define IT83XX_GPIO_GPCRI6      REG8(IT83XX_GPIO_BASE+0x56)
-#define IT83XX_GPIO_GPCRI7      REG8(IT83XX_GPIO_BASE+0x57)
-
-#define IT83XX_GPIO_GPCRM5      REG8(IT83XX_GPIO_BASE+0xA5)
-
-#define IT83XX_GPIO_GPDMRA      REG8(IT83XX_GPIO_BASE+0x61)
-#define IT83XX_GPIO_GPDMRB      REG8(IT83XX_GPIO_BASE+0x62)
-#define IT83XX_GPIO_GPDMRC      REG8(IT83XX_GPIO_BASE+0x63)
-#define IT83XX_GPIO_GPDMRE      REG8(IT83XX_GPIO_BASE+0x65)
-#define IT83XX_GPIO_GPDMRF      REG8(IT83XX_GPIO_BASE+0x66)
-#define IT83XX_GPIO_GPDMRH      REG8(IT83XX_GPIO_BASE+0x68)
-
-#define IT83XX_GPIO_GPCRL0      REG8(IT83XX_GPIO_BASE+0x98)
-#define IT83XX_GPIO_GPCRL1      REG8(IT83XX_GPIO_BASE+0x99)
-#define IT83XX_GPIO_GPCRL2      REG8(IT83XX_GPIO_BASE+0x9A)
-#define IT83XX_GPIO_GPCRL3      REG8(IT83XX_GPIO_BASE+0x9B)
-#define IT83XX_GPIO_GPCRP0      REG8(IT83XX_GPIO2_BASE+0x18)
-#define IT83XX_GPIO_GPCRP1      REG8(IT83XX_GPIO2_BASE+0x19)
-
-#define IT83XX_GPIO_GRC1        REG8(IT83XX_GPIO_BASE+0xF0)
-#define IT83XX_GPIO_GRC2        REG8(IT83XX_GPIO_BASE+0xF1)
-#define IT83XX_GPIO_GRC3        REG8(IT83XX_GPIO_BASE+0xF2)
-#define IT83XX_GPIO_GRC4        REG8(IT83XX_GPIO_BASE+0xF3)
-#define IT83XX_GPIO_GRC5        REG8(IT83XX_GPIO_BASE+0xF4)
-#define IT83XX_GPIO_GRC6        REG8(IT83XX_GPIO_BASE+0xF5)
-#define IT83XX_GPIO_GRC7        REG8(IT83XX_GPIO_BASE+0xF6)
-#define IT83XX_GPIO_GRC8        REG8(IT83XX_GPIO_BASE+0xF7)
-#define IT83XX_GPIO_GRC19       REG8(IT83XX_GPIO_BASE+0xE4)
-#define IT83XX_GPIO_GRC20       REG8(IT83XX_GPIO_BASE+0xE5)
-#define IT83XX_GPIO_GRC21       REG8(IT83XX_GPIO_BASE+0xE6)
-#define IT83XX_GPIO_GRC22       REG8(IT83XX_GPIO_BASE+0xE7)
-#define IT83XX_GPIO_GRC23       REG8(IT83XX_GPIO_BASE+0xE8)
-#define IT83XX_GPIO_GRC24       REG8(IT83XX_GPIO_BASE+0xE9)
-#define IT83XX_GPIO_GCR25       REG8(IT83XX_GPIO_BASE+0xD1)
-#define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
-#define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
-#define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
-#define IT83XX_GPIO_GCR29       REG8(IT83XX_GPIO_BASE+0xEE)
-#define IT83XX_GPIO_GCR30       REG8(IT83XX_GPIO_BASE+0xED)
-#define IT83XX_GPIO_GCR31       REG8(IT83XX_GPIO_BASE+0xD5)
-#define IT83XX_GPIO_GCR32       REG8(IT83XX_GPIO_BASE+0xD6)
-#define IT83XX_GPIO_GCR33       REG8(IT83XX_GPIO_BASE+0xD7)
-
-#define IT83XX_VBATPC_BGPOPSCR  REG8(IT83XX_GPIO2_BASE+0xF0)
-#define IT83XX_VBATPC_XLPIER    REG8(IT83XX_GPIO2_BASE+0xF5)
-
-enum {
-	/* GPIO group index */
-	GPIO_A = 0x1,
-	GPIO_B = 0x2,
-	GPIO_C = 0x3,
-	GPIO_D = 0x4,
-	GPIO_E = 0x5,
-	GPIO_F = 0x6,
-	GPIO_G = 0x7,
-	GPIO_H = 0x8,
-	GPIO_I = 0x9,
-	GPIO_J = 0xa,
-	GPIO_K = 0xb,
-	GPIO_L = 0xc,
-	GPIO_M = 0xd,
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	GPIO_O = 0xe,
-	GPIO_P = 0xf,
-	GPIO_Q = 0x10,
-	GPIO_R = 0x11,
-#endif
-	GPIO_PORT_COUNT,
-
-	/*
-	 * NOTE: support flags when KSI/KSO are configured as GPIO
-	 * 1) it8320bx:
-	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN, GPIO_HIGH, GPIO_LOW
-	 * input: GPIO_INPUT
-	 * 2) it8320dx, it8xxx1, and it8xxx2:
-	 * output: GPIO_OUTPUT, GPIO_OPEN_DRAIN(always internal pullup),
-	 *         GPIO_HIGH, GPIO_LOW
-	 * input: GPIO_INPUT, GPIO_PULL_UP
-	 */
-	/* KSI[7-0]  GPIO data mirror register. */
-	GPIO_KSI,
-	/* KSO[15-8] GPIO data mirror register. */
-	GPIO_KSO_H,
-	/* KSO[7-0]  GPIO data mirror register. */
-	GPIO_KSO_L,
-	/* Compiler check COUNT and gpio_group_to_reg member cnt match or not */
-	COUNT,
-};
-
-struct gpio_reg_t {
-	/* GPIO and KSI/KSO port data register (bit mapping to pin) */
-	uint32_t reg_gpdr;
-	/* GPIO and KSI/KSO port data mirror register (bit mapping to pin) */
-	uint32_t reg_gpdmr;
-	/* GPIO and KSI/KSO port output type register (bit mapping to pin) */
-	uint32_t reg_gpotr;
-	/* GPIO port control register (byte mapping to pin) */
-	uint32_t reg_gpcr;
-};
-
-/* GPIO group index convert to GPIO data/output type/ctrl group address */
-static const struct gpio_reg_t gpio_group_to_reg[] = {
-	/*               GPDR(set),  GPDMR(get), GPOTR,      GPCR      */
-	[GPIO_A]     = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
-	[GPIO_B]     = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
-	[GPIO_C]     = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
-	[GPIO_D]     = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
-	[GPIO_E]     = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
-	[GPIO_F]     = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
-	[GPIO_G]     = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
-	[GPIO_H]     = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
-	[GPIO_I]     = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
-	[GPIO_J]     = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
-	[GPIO_K]     = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
-	[GPIO_L]     = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
-	[GPIO_M]     = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
-#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O]     = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
-	[GPIO_P]     = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
-	[GPIO_Q]     = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
-	[GPIO_R]     = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
-#endif
-	[GPIO_KSI]   = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF },
-	[GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, 0xFFFFFFFF },
-	[GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, 0xFFFFFFFF },
-};
-BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-#define IT83XX_GPIO_DATA(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpdr)
-#define IT83XX_GPIO_DATA_MIRROR(port)          \
-	REG8(gpio_group_to_reg[port].reg_gpdmr)
-#define IT83XX_GPIO_GPOT(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpotr)
-#define IT83XX_GPIO_CTRL(port, pin_offset)     \
-	REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset)
-#define GPCR_PORT_PIN_MODE_INPUT          BIT(7)
-#define GPCR_PORT_PIN_MODE_OUTPUT         BIT(6)
-#define GPCR_PORT_PIN_MODE_PULLUP         BIT(2)
-#define GPCR_PORT_PIN_MODE_PULLDOWN       BIT(1)
-
-/* --- Clock and Power Management (ECPM) --- */
-
-#define IT83XX_ECPM_BASE  0x00F01E00
-
-#define IT83XX_ECPM_CGCTRL1R_OFF 0x01
-#define IT83XX_ECPM_CGCTRL2R_OFF 0x02
-#define IT83XX_ECPM_CGCTRL3R_OFF 0x05
-#define IT83XX_ECPM_CGCTRL4R_OFF 0x09
-
-#define IT83XX_ECPM_PLLCTRL	REG8(IT83XX_ECPM_BASE+0x03)
-enum ec_pll_ctrl {
-	EC_PLL_DOZE = 0,
-	EC_PLL_SLEEP = 1,
-	EC_PLL_DEEP_DOZE = 3,
-};
-
-#define IT83XX_ECPM_AUTOCG	REG8(IT83XX_ECPM_BASE+0x04)
-#define IT83XX_ECPM_PLLFREQR	REG8(IT83XX_ECPM_BASE+0x06)
-#define IT83XX_ECPM_PLLCSS	REG8(IT83XX_ECPM_BASE+0x08)
-#define IT83XX_ECPM_SCDCR0	REG8(IT83XX_ECPM_BASE+0x0c)
-#define IT83XX_ECPM_SCDCR1	REG8(IT83XX_ECPM_BASE+0x0d)
-#define IT83XX_ECPM_SCDCR2	REG8(IT83XX_ECPM_BASE+0x0e)
-#define IT83XX_ECPM_SCDCR3	REG8(IT83XX_ECPM_BASE+0x0f)
-#define IT83XX_ECPM_SCDCR4	REG8(IT83XX_ECPM_BASE+0x10)
-
-/*
- * The clock gate offsets combine the register offset from ECPM_BASE and the
- * mask within that register into one value. These are used for
- * clock_enable_peripheral() and clock_disable_peripheral()
- */
-enum clock_gate_offsets {
-	CGC_OFFSET_EGPC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
-	CGC_OFFSET_CIR   = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
-	CGC_OFFSET_SWUC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
-	CGC_OFFSET_USB   = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
-	CGC_OFFSET_PECI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
-	CGC_OFFSET_UART  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
-	CGC_OFFSET_SSPI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
-	CGC_OFFSET_DBGR  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
-	CGC_OFFSET_SMBF  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
-	CGC_OFFSET_SMBE  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
-	CGC_OFFSET_SMBD  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
-	CGC_OFFSET_SMBC  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
-	CGC_OFFSET_SMBB  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
-	CGC_OFFSET_SMBA  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
-	CGC_OFFSET_SMB   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
-	CGC_OFFSET_CEC   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
-};
-
-/* --- Timer (TMR) --- */
-#define IT83XX_TMR_BASE         0x00F02900
-
-#define IT83XX_TMR_PRSC         REG8(IT83XX_TMR_BASE+0x00)
-#define IT83XX_TMR_GCSMS        REG8(IT83XX_TMR_BASE+0x01)
-#define IT83XX_TMR_CTR_A0       REG8(IT83XX_TMR_BASE+0x02)
-#define IT83XX_TMR_CTR_A1       REG8(IT83XX_TMR_BASE+0x03)
-#define IT83XX_TMR_CTR_B0       REG8(IT83XX_TMR_BASE+0x04)
-#define IT83XX_TMR_CTR_B1       REG8(IT83XX_TMR_BASE+0x05)
-#define IT83XX_TMR_DCR_A0       REG8(IT83XX_TMR_BASE+0x06)
-#define IT83XX_TMR_DCR_A1       REG8(IT83XX_TMR_BASE+0x07)
-#define IT83XX_TMR_DCR_B0       REG8(IT83XX_TMR_BASE+0x08)
-#define IT83XX_TMR_DCR_B1       REG8(IT83XX_TMR_BASE+0x09)
-#define IT83XX_TMR_CCGSR        REG8(IT83XX_TMR_BASE+0x0A)
-#define IT83XX_TMR_TMRCE        REG8(IT83XX_TMR_BASE+0x0B)
-#define IT83XX_TMR_TMRIE        REG8(IT83XX_TMR_BASE+0x0C)
-
-/* --- External Timer and Watchdog (ETWD) --- */
-#define IT83XX_ETWD_BASE  0x00F01F00
-
-#define IT83XX_ETWD_ETWCFG        REG8(IT83XX_ETWD_BASE+0x01)
-#define IT83XX_ETWD_ET1PSR        REG8(IT83XX_ETWD_BASE+0x02)
-#define IT83XX_ETWD_ET1CNTLHR     REG8(IT83XX_ETWD_BASE+0x03)
-#define IT83XX_ETWD_ET1CNTLLR     REG8(IT83XX_ETWD_BASE+0x04)
-#define IT83XX_ETWD_ETWCTRL       REG8(IT83XX_ETWD_BASE+0x05)
-#define IT83XX_ETWD_EWDCNTLLR     REG8(IT83XX_ETWD_BASE+0x06)
-#define IT83XX_ETWD_EWDKEYR       REG8(IT83XX_ETWD_BASE+0x07)
-#define IT83XX_ETWD_EWDCNTLHR     REG8(IT83XX_ETWD_BASE+0x09)
-#define IT83XX_ETWD_ETXCTRL(n)    REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
-#define IT83XX_ETWD_ETXPSR(n)     REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
-#define IT83XX_ETWD_ETXCNTLR(n)   REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
-#define IT83XX_ETWD_ETXCNTOR(n)   REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
-
-/* --- General Control (GCTRL) --- */
-#define IT83XX_GCTRL_BASE 0x00F02000
-
-#ifdef IT83XX_CHIP_ID_3BYTES
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x85)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x86)
-#define IT83XX_GCTRL_CHIPID3      REG8(IT83XX_GCTRL_BASE+0x87)
-#else
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x00)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x01)
-#endif
-#define IT83XX_GCTRL_CHIPVER      REG8(IT83XX_GCTRL_BASE+0x02)
-#define IT83XX_GCTRL_DBGROS       REG8(IT83XX_GCTRL_BASE+0x03)
-#define IT83XX_SMB_DBGR           BIT(0)
-#define IT83XX_GCTRL_WNCKR        REG8(IT83XX_GCTRL_BASE+0x0B)
-#define IT83XX_GCTRL_RSTS         REG8(IT83XX_GCTRL_BASE+0x06)
-#define IT83XX_GCTRL_BADRSEL      REG8(IT83XX_GCTRL_BASE+0x0A)
-#define IT83XX_GCTRL_SPCTRL1      REG8(IT83XX_GCTRL_BASE+0x0D)
-#define IT83XX_GCTRL_RSTDMMC      REG8(IT83XX_GCTRL_BASE+0x10)
-#define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
-#define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
-#define IT83XX_GCTRL_MCCR3        REG8(IT83XX_GCTRL_BASE+0x20)
-#define IT83XX_GCTRL_SPISLVPFE    BIT(6)
-#define IT83XX_GCTRL_RSTC5        REG8(IT83XX_GCTRL_BASE+0x21)
-#define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
-#define IT83XX_GCTRL_PMER1        REG8(IT83XX_GCTRL_BASE+0x32)
-#define IT83XX_GCTRL_PMER2        REG8(IT83XX_GCTRL_BASE+0x33)
-#define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
-#define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
-#define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
-#define IT83XX_GCTRL_PIN_MUX0     REG8(IT83XX_GCTRL_BASE+0x46)
-#define IT83XX_DLM14_ENABLE       BIT(5)
-#define IT83XX_GCTRL_SSCR         REG8(IT83XX_GCTRL_BASE+0x4A)
-#define IT83XX_GCTRL_ETWDUARTCR   REG8(IT83XX_GCTRL_BASE+0x4B)
-#define IT83XX_GCTRL_WMCR         REG8(IT83XX_GCTRL_BASE+0x4C)
-#define IT83XX_GCTRL_H2ROFSR      REG8(IT83XX_GCTRL_BASE+0x53)
-/* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */
-#define ETWD_HW_RST_EN            BIT(0)
-#define IT83XX_GCTRL_RVILMCR0     REG8(IT83XX_GCTRL_BASE+0x5D)
-#define ILMCR_ILM0_ENABLE         BIT(0)
-#define ILMCR_ILM2_ENABLE         BIT(2)
-#define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
-#define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
-#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
-
-/* --- Pulse Width Modulation (PWM) --- */
-#define IT83XX_PWM_BASE   0x00F01800
-
-#define IT83XX_PWM_C0CPRS       REG8(IT83XX_PWM_BASE+0x00)
-#define IT83XX_PWM_CTR          REG8(IT83XX_PWM_BASE+0x01)
-#define IT83XX_PWM_DCR0         REG8(IT83XX_PWM_BASE+0x02)
-#define IT83XX_PWM_DCR1         REG8(IT83XX_PWM_BASE+0x03)
-#define IT83XX_PWM_DCR2         REG8(IT83XX_PWM_BASE+0x04)
-#define IT83XX_PWM_DCR3         REG8(IT83XX_PWM_BASE+0x05)
-#define IT83XX_PWM_DCR4         REG8(IT83XX_PWM_BASE+0x06)
-#define IT83XX_PWM_DCR5         REG8(IT83XX_PWM_BASE+0x07)
-#define IT83XX_PWM_DCR6         REG8(IT83XX_PWM_BASE+0x08)
-#define IT83XX_PWM_DCR7         REG8(IT83XX_PWM_BASE+0x09)
-#define IT83XX_PWM_PWMPOL       REG8(IT83XX_PWM_BASE+0x0A)
-#define IT83XX_PWM_PCFSR        REG8(IT83XX_PWM_BASE+0x0B)
-#define IT83XX_PWM_PCSSGL       REG8(IT83XX_PWM_BASE+0x0C)
-#define IT83XX_PWM_PCSSGH       REG8(IT83XX_PWM_BASE+0x0D)
-#define IT83XX_PWM_CR256PCSSG   REG8(IT83XX_PWM_BASE+0x0E)
-#define IT83XX_PWM_PCSGR        REG8(IT83XX_PWM_BASE+0x0F)
-#define IT83XX_PWM_CTR1M        REG8(IT83XX_PWM_BASE+0x10)
-#define IT83XX_PWM_F1TLRR       REG8(IT83XX_PWM_BASE+0x1E)
-#define IT83XX_PWM_F1TMRR       REG8(IT83XX_PWM_BASE+0x1F)
-#define IT83XX_PWM_F2TLRR       REG8(IT83XX_PWM_BASE+0x20)
-#define IT83XX_PWM_F2TMRR       REG8(IT83XX_PWM_BASE+0x21)
-#define IT83XX_PWM_ZINTSCR      REG8(IT83XX_PWM_BASE+0x22)
-#define IT83XX_PWM_ZTIER        REG8(IT83XX_PWM_BASE+0x23)
-#define IT83XX_PWM_TSWCTLR      REG8(IT83XX_PWM_BASE+0x24)
-#define IT83XX_PWM_C4CPRS       REG8(IT83XX_PWM_BASE+0x27)
-#define IT83XX_PWM_C4MCPRS      REG8(IT83XX_PWM_BASE+0x28)
-#define IT83XX_PWM_C6CPRS       REG8(IT83XX_PWM_BASE+0x2B)
-#define IT83XX_PWM_C6MCPRS      REG8(IT83XX_PWM_BASE+0x2C)
-#define IT83XX_PWM_C7CPRS       REG8(IT83XX_PWM_BASE+0x2D)
-#define IT83XX_PWM_C7MCPRS      REG8(IT83XX_PWM_BASE+0x2E)
-#define IT83XX_PWM_CLK6MSEL     REG8(IT83XX_PWM_BASE+0x40)
-#define IT83XX_PWM_CTR1         REG8(IT83XX_PWM_BASE+0x41)
-#define IT83XX_PWM_CTR2         REG8(IT83XX_PWM_BASE+0x42)
-#define IT83XX_PWM_CTR3         REG8(IT83XX_PWM_BASE+0x43)
-#define IT83XX_PWM_PWM5TOCTRL   REG8(IT83XX_PWM_BASE+0x44)
-#define IT83XX_PWM_CFLRR        REG8(IT83XX_PWM_BASE+0x45)
-#define IT83XX_PWM_CFMRR        REG8(IT83XX_PWM_BASE+0x46)
-#define IT83XX_PWM_CFINTCTRL    REG8(IT83XX_PWM_BASE+0x47)
-#define IT83XX_PWM_TSWCTRL      REG8(IT83XX_PWM_BASE+0x48)
-#define IT83XX_PWM_PWMODENR     REG8(IT83XX_PWM_BASE+0x49)
-
-/* Analog to Digital Converter (ADC) */
-#define IT83XX_ADC_BASE   0x00F01900
-
-#define IT83XX_ADC_ADCSTS       REG8(IT83XX_ADC_BASE+0x00)
-#define IT83XX_ADC_ADCCFG       REG8(IT83XX_ADC_BASE+0x01)
-#define IT83XX_ADC_ADCCTL       REG8(IT83XX_ADC_BASE+0x02)
-#define IT83XX_ADC_ADCGCR       REG8(IT83XX_ADC_BASE+0x03)
-#define IT83XX_ADC_DBKEN            BIT(7) /* ADC data buffer keep enable. */
-#define IT83XX_ADC_VCH0CTL      REG8(IT83XX_ADC_BASE+0x04)
-#define IT83XX_ADC_KDCTL        REG8(IT83XX_ADC_BASE+0x05)
-#define IT83XX_ADC_AHCE             BIT(7)
-#define IT83XX_ADC_VCH1CTL      REG8(IT83XX_ADC_BASE+0x06)
-#define IT83XX_ADC_VCH1DATL     REG8(IT83XX_ADC_BASE+0x07)
-#define IT83XX_ADC_VCH1DATM     REG8(IT83XX_ADC_BASE+0x08)
-#define IT83XX_ADC_VCH2CTL      REG8(IT83XX_ADC_BASE+0x09)
-#define IT83XX_ADC_VCH2DATL     REG8(IT83XX_ADC_BASE+0x0A)
-#define IT83XX_ADC_VCH2DATM     REG8(IT83XX_ADC_BASE+0x0B)
-#define IT83XX_ADC_VCH3CTL      REG8(IT83XX_ADC_BASE+0x0C)
-#define IT83XX_ADC_VCH3DATL     REG8(IT83XX_ADC_BASE+0x0D)
-#define IT83XX_ADC_VCH3DATM     REG8(IT83XX_ADC_BASE+0x0E)
-#define IT83XX_ADC_VHSCDBL      REG8(IT83XX_ADC_BASE+0x14)
-#define IT83XX_ADC_VHSCDBM      REG8(IT83XX_ADC_BASE+0x15)
-#define IT83XX_ADC_VCH0DATL     REG8(IT83XX_ADC_BASE+0x18)
-#define IT83XX_ADC_VCH0DATM     REG8(IT83XX_ADC_BASE+0x19)
-#define IT83XX_ADC_VHSGCDBL     REG8(IT83XX_ADC_BASE+0x1C)
-#define IT83XX_ADC_VHSGCDBM     REG8(IT83XX_ADC_BASE+0x1D)
-#define IT83XX_ADC_ADCSAR       REG8(IT83XX_ADC_BASE+0x32)
-#define IT83XX_ADC_VCMPSCP      REG8(IT83XX_ADC_BASE+0x37)
-#define IT83XX_ADC_VCH4CTL      REG8(IT83XX_ADC_BASE+0x38)
-#define IT83XX_ADC_VCH4DATM     REG8(IT83XX_ADC_BASE+0x39)
-#define IT83XX_ADC_VCH4DATL     REG8(IT83XX_ADC_BASE+0x3A)
-#define IT83XX_ADC_VCH5CTL      REG8(IT83XX_ADC_BASE+0x3B)
-#define IT83XX_ADC_VCH5DATM     REG8(IT83XX_ADC_BASE+0x3C)
-#define IT83XX_ADC_VCH5DATL     REG8(IT83XX_ADC_BASE+0x3D)
-#define IT83XX_ADC_VCH6CTL      REG8(IT83XX_ADC_BASE+0x3E)
-#define IT83XX_ADC_VCH6DATM     REG8(IT83XX_ADC_BASE+0x3F)
-#define IT83XX_ADC_VCH6DATL     REG8(IT83XX_ADC_BASE+0x40)
-#define IT83XX_ADC_VCH7CTL      REG8(IT83XX_ADC_BASE+0x41)
-#define IT83XX_ADC_VCH7DATM     REG8(IT83XX_ADC_BASE+0x42)
-#define IT83XX_ADC_VCH7DATL     REG8(IT83XX_ADC_BASE+0x43)
-#define IT83XX_ADC_ADCDVSTS     REG8(IT83XX_ADC_BASE+0x44)
-#define IT83XX_ADC_VCMPSTS      REG8(IT83XX_ADC_BASE+0x45)
-#define IT83XX_ADC_VCMP0CTL     REG8(IT83XX_ADC_BASE+0x46)
-#define ADC_VCMP_CMPEN              BIT(7)
-#define ADC_VCMP_CMPINTEN           BIT(6)
-#define ADC_VCMP_GREATER_THRESHOLD  BIT(5)
-#define ADC_VCMP_EDGE_TRIGGER       BIT(4)
-#define ADC_VCMP_GPIO_ACTIVE_LOW    BIT(3)
-#define IT83XX_ADC_CMP0THRDATM  REG8(IT83XX_ADC_BASE+0x47)
-#define IT83XX_ADC_CMP0THRDATL  REG8(IT83XX_ADC_BASE+0x48)
-#define IT83XX_ADC_VCMP1CTL     REG8(IT83XX_ADC_BASE+0x49)
-#define IT83XX_ADC_CMP1THRDATM  REG8(IT83XX_ADC_BASE+0x4A)
-#define IT83XX_ADC_CMP1THRDATL  REG8(IT83XX_ADC_BASE+0x4B)
-#define IT83XX_ADC_VCMP2CTL     REG8(IT83XX_ADC_BASE+0x4C)
-#define IT83XX_ADC_CMP2THRDATM  REG8(IT83XX_ADC_BASE+0x4D)
-#define IT83XX_ADC_CMP2THRDATL  REG8(IT83XX_ADC_BASE+0x4E)
-#define IT83XX_ADC_VCH13CTL     REG8(IT83XX_ADC_BASE+0x60)
-#define IT83XX_ADC_VCH13DATM    REG8(IT83XX_ADC_BASE+0x61)
-#define IT83XX_ADC_VCH13DATL    REG8(IT83XX_ADC_BASE+0x62)
-#define IT83XX_ADC_VCH14CTL     REG8(IT83XX_ADC_BASE+0x63)
-#define IT83XX_ADC_VCH14DATM    REG8(IT83XX_ADC_BASE+0x64)
-#define IT83XX_ADC_VCH14DATL    REG8(IT83XX_ADC_BASE+0x65)
-#define IT83XX_ADC_VCH15CTL     REG8(IT83XX_ADC_BASE+0x66)
-#define IT83XX_ADC_VCH15DATM    REG8(IT83XX_ADC_BASE+0x67)
-#define IT83XX_ADC_VCH15DATL    REG8(IT83XX_ADC_BASE+0x68)
-#define IT83XX_ADC_VCH16CTL     REG8(IT83XX_ADC_BASE+0x69)
-#define IT83XX_ADC_VCH16DATM    REG8(IT83XX_ADC_BASE+0x6A)
-#define IT83XX_ADC_VCH16DATL    REG8(IT83XX_ADC_BASE+0x6B)
-#define IT83XX_ADC_ADCDVSTS2    REG8(IT83XX_ADC_BASE+0x6C)
-#define IT83XX_ADC_VCMPSTS2     REG8(IT83XX_ADC_BASE+0x6D)
-#define IT83XX_ADC_VCMP3CTL     REG8(IT83XX_ADC_BASE+0x6E)
-#define IT83XX_ADC_CMP3THRDATM  REG8(IT83XX_ADC_BASE+0x6F)
-#define IT83XX_ADC_CMP3THRDATL  REG8(IT83XX_ADC_BASE+0x70)
-#define IT83XX_ADC_VCMP4CTL     REG8(IT83XX_ADC_BASE+0x71)
-#define IT83XX_ADC_CMP4THRDATM  REG8(IT83XX_ADC_BASE+0x72)
-#define IT83XX_ADC_CMP4THRDATL  REG8(IT83XX_ADC_BASE+0x73)
-#define IT83XX_ADC_VCMP5CTL     REG8(IT83XX_ADC_BASE+0x74)
-#define IT83XX_ADC_CMP5THRDATM  REG8(IT83XX_ADC_BASE+0x75)
-#define IT83XX_ADC_CMP5THRDATL  REG8(IT83XX_ADC_BASE+0x76)
-#define IT83XX_ADC_VCMP0CSELM   REG8(IT83XX_ADC_BASE+0x77)
-#define ADC_VCMP_VCMPCSELM          BIT(0)
-#define IT83XX_ADC_VCMP1CSELM   REG8(IT83XX_ADC_BASE+0x78)
-#define IT83XX_ADC_VCMP2CSELM   REG8(IT83XX_ADC_BASE+0x79)
-#define IT83XX_ADC_VCMP3CSELM   REG8(IT83XX_ADC_BASE+0x7A)
-#define IT83XX_ADC_VCMP4CSELM   REG8(IT83XX_ADC_BASE+0x7B)
-#define IT83XX_ADC_VCMP5CSELM   REG8(IT83XX_ADC_BASE+0x7C)
-
-/* Digital to Analog Converter (DAC) */
-#define IT83XX_DAC_BASE   0x00F01A00
-
-#define IT83XX_DAC_DACPDREG     REG8(IT83XX_DAC_BASE+0x01)
-#define IT83XX_DAC_POWDN(ch)    BIT(ch)
-#define IT83XX_DAC_DACDAT(ch)   REG8(IT83XX_DAC_BASE+0x02+ch)
-
-/* Keyboard Controller (KBC) */
-#define IT83XX_KBC_BASE   0x00F01300
-
-#define IT83XX_KBC_KBHICR       REG8(IT83XX_KBC_BASE+0x00)
-#define IT83XX_KBC_KBIRQR       REG8(IT83XX_KBC_BASE+0x02)
-#define IT83XX_KBC_KBHISR       REG8(IT83XX_KBC_BASE+0x04)
-#define IT83XX_KBC_KBHIKDOR     REG8(IT83XX_KBC_BASE+0x06)
-#define IT83XX_KBC_KBHIMDOR     REG8(IT83XX_KBC_BASE+0x08)
-#define IT83XX_KBC_KBHIDIR      REG8(IT83XX_KBC_BASE+0x0A)
-
-/* Power Management Channel (PMC) */
-#define IT83XX_PMC_BASE   0x00F01500
-
-#define IT83XX_PMC_PM1STS       REG8(IT83XX_PMC_BASE+0x00)
-#define IT83XX_PMC_PM1DO        REG8(IT83XX_PMC_BASE+0x01)
-#define IT83XX_PMC_PM1DOSCI     REG8(IT83XX_PMC_BASE+0x02)
-#define IT83XX_PMC_PM1DOSMI     REG8(IT83XX_PMC_BASE+0x03)
-#define IT83XX_PMC_PM1DI        REG8(IT83XX_PMC_BASE+0x04)
-#define IT83XX_PMC_PM1DISCI     REG8(IT83XX_PMC_BASE+0x05)
-#define IT83XX_PMC_PM1CTL       REG8(IT83XX_PMC_BASE+0x06)
-#define IT83XX_PMC_PM1IC        REG8(IT83XX_PMC_BASE+0x07)
-#define IT83XX_PMC_PM1IE        REG8(IT83XX_PMC_BASE+0x08)
-#define IT83XX_PMC_PM2STS       REG8(IT83XX_PMC_BASE+0x10)
-#define IT83XX_PMC_PM2DO        REG8(IT83XX_PMC_BASE+0x11)
-#define IT83XX_PMC_PM2DOSCI     REG8(IT83XX_PMC_BASE+0x12)
-#define IT83XX_PMC_PM2DOSMI     REG8(IT83XX_PMC_BASE+0x13)
-#define IT83XX_PMC_PM2DI        REG8(IT83XX_PMC_BASE+0x14)
-#define IT83XX_PMC_PM2DISCI     REG8(IT83XX_PMC_BASE+0x15)
-#define IT83XX_PMC_PM2CTL       REG8(IT83XX_PMC_BASE+0x16)
-#define IT83XX_PMC_PM2IC        REG8(IT83XX_PMC_BASE+0x17)
-#define IT83XX_PMC_PM2IE        REG8(IT83XX_PMC_BASE+0x18)
-#define IT83XX_PMC_PM3STS       REG8(IT83XX_PMC_BASE+0x20)
-#define IT83XX_PMC_PM3DO        REG8(IT83XX_PMC_BASE+0x21)
-#define IT83XX_PMC_PM3DI        REG8(IT83XX_PMC_BASE+0x22)
-#define IT83XX_PMC_PM3CTL       REG8(IT83XX_PMC_BASE+0x23)
-#define IT83XX_PMC_PM3IC        REG8(IT83XX_PMC_BASE+0x24)
-#define IT83XX_PMC_PM3IE        REG8(IT83XX_PMC_BASE+0x25)
-#define IT83XX_PMC_PM4STS       REG8(IT83XX_PMC_BASE+0x30)
-#define IT83XX_PMC_PM4DO        REG8(IT83XX_PMC_BASE+0x31)
-#define IT83XX_PMC_PM4DI        REG8(IT83XX_PMC_BASE+0x32)
-#define IT83XX_PMC_PM4CTL       REG8(IT83XX_PMC_BASE+0x33)
-#define IT83XX_PMC_PM4IC        REG8(IT83XX_PMC_BASE+0x34)
-#define IT83XX_PMC_PM4IE        REG8(IT83XX_PMC_BASE+0x35)
-#define IT83XX_PMC_PM5STS       REG8(IT83XX_PMC_BASE+0x40)
-#define IT83XX_PMC_PM5DO        REG8(IT83XX_PMC_BASE+0x41)
-#define IT83XX_PMC_PM5DI        REG8(IT83XX_PMC_BASE+0x42)
-#define IT83XX_PMC_PM5CTL       REG8(IT83XX_PMC_BASE+0x43)
-#define IT83XX_PMC_PM5IC        REG8(IT83XX_PMC_BASE+0x44)
-#define IT83XX_PMC_PM5IE        REG8(IT83XX_PMC_BASE+0x45)
-#define IT83XX_PMC_MBXCTRL      REG8(IT83XX_PMC_BASE+0x19)
-#define IT83XX_PMC_MBXEC_00     REG8(IT83XX_PMC_BASE+0xF0)
-#define IT83XX_PMC_MBXEC_01     REG8(IT83XX_PMC_BASE+0xF1)
-#define IT83XX_PMC_MBXEC_02     REG8(IT83XX_PMC_BASE+0xF2)
-#define IT83XX_PMC_MBXEC_03     REG8(IT83XX_PMC_BASE+0xF3)
-#define IT83XX_PMC_MBXEC_04     REG8(IT83XX_PMC_BASE+0xF4)
-#define IT83XX_PMC_MBXEC_05     REG8(IT83XX_PMC_BASE+0xF5)
-#define IT83XX_PMC_MBXEC_06     REG8(IT83XX_PMC_BASE+0xF6)
-#define IT83XX_PMC_MBXEC_07     REG8(IT83XX_PMC_BASE+0xF7)
-#define IT83XX_PMC_MBXEC_08     REG8(IT83XX_PMC_BASE+0xF8)
-#define IT83XX_PMC_MBXEC_09     REG8(IT83XX_PMC_BASE+0xF9)
-#define IT83XX_PMC_MBXEC_10     REG8(IT83XX_PMC_BASE+0xFA)
-#define IT83XX_PMC_MBXEC_11     REG8(IT83XX_PMC_BASE+0xFB)
-#define IT83XX_PMC_MBXEC_12     REG8(IT83XX_PMC_BASE+0xFC)
-#define IT83XX_PMC_MBXEC_13     REG8(IT83XX_PMC_BASE+0xFD)
-#define IT83XX_PMC_MBXEC_14     REG8(IT83XX_PMC_BASE+0xFE)
-#define IT83XX_PMC_MBXEC_15     REG8(IT83XX_PMC_BASE+0xFF)
-#define IT83XX_PMC_PMSTS(ch)    REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
-#define IT83XX_PMC_PMDO(ch)     REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
-#define IT83XX_PMC_PMDI(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
-#define IT83XX_PMC_PMCTL(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
-#define IT83XX_PMC_PMIE(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
-
-/* Keyboard Matrix Scan control (KBS) */
-#define IT83XX_KBS_BASE   0x00F01D00
-
-#define IT83XX_KBS_KSOL         REG8(IT83XX_KBS_BASE+0x00)
-#define IT83XX_KBS_KSOH1        REG8(IT83XX_KBS_BASE+0x01)
-#define IT83XX_KBS_KSOCTRL      REG8(IT83XX_KBS_BASE+0x02)
-#define IT83XX_KBS_KSOH2        REG8(IT83XX_KBS_BASE+0x03)
-#define IT83XX_KBS_KSI          REG8(IT83XX_KBS_BASE+0x04)
-#define IT83XX_KBS_KSICTRL      REG8(IT83XX_KBS_BASE+0x05)
-#define IT83XX_KBS_KSIGCTRL     REG8(IT83XX_KBS_BASE+0x06)
-#define IT83XX_KBS_KSIGOEN      REG8(IT83XX_KBS_BASE+0x07)
-#define IT83XX_KBS_KSIGDAT      REG8(IT83XX_KBS_BASE+0x08)
-#define IT83XX_KBS_KSIGDMRR     REG8(IT83XX_KBS_BASE+0x09)
-#define IT83XX_KBS_KSOHGCTRL    REG8(IT83XX_KBS_BASE+0x0A)
-#define IT83XX_KBS_KSOHGOEN     REG8(IT83XX_KBS_BASE+0x0B)
-#define IT83XX_KBS_KSOHGDMRR    REG8(IT83XX_KBS_BASE+0x0C)
-#define IT83XX_KBS_KSOLGCTRL    REG8(IT83XX_KBS_BASE+0x0D)
-#define IT83XX_KBS_KSOLGOEN     REG8(IT83XX_KBS_BASE+0x0E)
-#define IT83XX_KBS_KSOLGDMRR    REG8(IT83XX_KBS_BASE+0x0F)
-#define IT83XX_KBS_KSO0LSDR     REG8(IT83XX_KBS_BASE+0x10)
-#define IT83XX_KBS_KSO1LSDR     REG8(IT83XX_KBS_BASE+0x11)
-#define IT83XX_KBS_KSO2LSDR     REG8(IT83XX_KBS_BASE+0x12)
-#define IT83XX_KBS_KSO3LSDR     REG8(IT83XX_KBS_BASE+0x13)
-#define IT83XX_KBS_KSO4LSDR     REG8(IT83XX_KBS_BASE+0x14)
-#define IT83XX_KBS_KSO5LSDR     REG8(IT83XX_KBS_BASE+0x15)
-#define IT83XX_KBS_KSO6LSDR     REG8(IT83XX_KBS_BASE+0x16)
-#define IT83XX_KBS_KSO7LSDR     REG8(IT83XX_KBS_BASE+0x17)
-#define IT83XX_KBS_KSO8LSDR     REG8(IT83XX_KBS_BASE+0x18)
-#define IT83XX_KBS_KSO9LSDR     REG8(IT83XX_KBS_BASE+0x19)
-#define IT83XX_KBS_KSO10LSDR    REG8(IT83XX_KBS_BASE+0x1A)
-#define IT83XX_KBS_KSO11LSDR    REG8(IT83XX_KBS_BASE+0x1B)
-#define IT83XX_KBS_KSO12LSDR    REG8(IT83XX_KBS_BASE+0x1C)
-#define IT83XX_KBS_KSO13LSDR    REG8(IT83XX_KBS_BASE+0x1D)
-#define IT83XX_KBS_KSO14LSDR    REG8(IT83XX_KBS_BASE+0x1E)
-#define IT83XX_KBS_KSO15LSDR    REG8(IT83XX_KBS_BASE+0x1F)
-#define IT83XX_KBS_KSO16LSDR    REG8(IT83XX_KBS_BASE+0x20)
-#define IT83XX_KBS_KSO17LSDR    REG8(IT83XX_KBS_BASE+0x21)
-#define IT83XX_KBS_SDC1R        REG8(IT83XX_KBS_BASE+0x22)
-#define IT83XX_KBS_SDC2R        REG8(IT83XX_KBS_BASE+0x23)
-#define IT83XX_KBS_SDC3R        REG8(IT83XX_KBS_BASE+0x24)
-#define IT83XX_KBS_SDSR         REG8(IT83XX_KBS_BASE+0x25)
-#define IT83XX_KBS_KSIGPODR     REG8(IT83XX_KBS_BASE+0x26)
-#define IT83XX_KBS_KSOHGPODR    REG8(IT83XX_KBS_BASE+0x27)
-#define IT83XX_KBS_KSOLGPODR    REG8(IT83XX_KBS_BASE+0x28)
-
-/* Shared Memory Flash Interface Bridge (SMFI) */
-#define IT83XX_SMFI_BASE  0x00F01000
-
-#define IT83XX_SMFI_SMECCS      REG8(IT83XX_SMFI_BASE+0x20)
-#define IT83XX_SMFI_MASK_HOSTWA 	BIT(5)
-#define IT83XX_SMFI_HRAMWC      REG8(IT83XX_SMFI_BASE+0x5A)
-#define IT83XX_SMFI_HRAMW0BA    REG8(IT83XX_SMFI_BASE+0x5B)
-#define IT83XX_SMFI_HRAMW1BA    REG8(IT83XX_SMFI_BASE+0x5C)
-#define IT83XX_SMFI_HRAMW0AAS   REG8(IT83XX_SMFI_BASE+0x5D)
-#define IT83XX_SMFI_HRAMW1AAS   REG8(IT83XX_SMFI_BASE+0x5E)
-#define IT83XX_SMFI_HRAMW2BA    REG8(IT83XX_SMFI_BASE+0x76)
-#define IT83XX_SMFI_HRAMW3BA    REG8(IT83XX_SMFI_BASE+0x77)
-#define IT83XX_SMFI_HRAMW2AAS   REG8(IT83XX_SMFI_BASE+0x78)
-#define IT83XX_SMFI_HRAMW3AAS   REG8(IT83XX_SMFI_BASE+0x79)
-#define IT83XX_SMFI_H2RAMECSIE  REG8(IT83XX_SMFI_BASE+0x7A)
-#define IT83XX_SMFI_H2RAMECSA   REG8(IT83XX_SMFI_BASE+0x7B)
-#define IT83XX_SMFI_H2RAMHSS    REG8(IT83XX_SMFI_BASE+0x7C)
-#define IT83XX_SMFI_ECINDAR0    REG8(IT83XX_SMFI_BASE+0x3B)
-#define IT83XX_SMFI_ECINDAR1    REG8(IT83XX_SMFI_BASE+0x3C)
-#define IT83XX_SMFI_ECINDAR2    REG8(IT83XX_SMFI_BASE+0x3D)
-#define IT83XX_SMFI_ECINDAR3    REG8(IT83XX_SMFI_BASE+0x3E)
-#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
-#define IT83XX_SMFI_ECINDDR     REG8(IT83XX_SMFI_BASE+0x3F)
-#define IT83XX_SMFI_SCAR0L      REG8(IT83XX_SMFI_BASE+0x40)
-#define IT83XX_SMFI_SCAR0M      REG8(IT83XX_SMFI_BASE+0x41)
-#define IT83XX_SMFI_SCAR0H      REG8(IT83XX_SMFI_BASE+0x42)
-#define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
-#define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
-#define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
-#define IT83XX_SMFI_FLHCTRL3R   REG8(IT83XX_SMFI_BASE+0x63)
-#define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
-#define IT83XX_SMFI_FLHCTRL6R   REG8(IT83XX_SMFI_BASE+0xA2)
-/* Enable EC-indirect page program command */
-#define IT83XX_SMFI_MASK_ECINDPP BIT(3)
-
-/* Serial Peripheral Interface (SSPI) */
-#define IT83XX_SSPI_BASE  0x00F02600
-
-#define IT83XX_SSPI_SPIDATA     REG8(IT83XX_SSPI_BASE+0x00)
-#define IT83XX_SSPI_SPICTRL1    REG8(IT83XX_SSPI_BASE+0x01)
-#define IT83XX_SSPI_SPICTRL2    REG8(IT83XX_SSPI_BASE+0x02)
-#define IT83XX_SSPI_SPISTS      REG8(IT83XX_SSPI_BASE+0x03)
-#define IT83XX_SSPI_SPICTRL3    REG8(IT83XX_SSPI_BASE+0x04)
-
-/* Serial Peripheral Interface (SPI) */
-#define IT83XX_SPI_BASE  0x00F03A00
-
-#define IT83XX_SPI_SPISGCR      REG8(IT83XX_SPI_BASE+0x00)
-#define IT83XX_SPI_SPISCEN         BIT(0)
-#define IT83XX_SPI_TXRXFAR      REG8(IT83XX_SPI_BASE+0x01)
-#define IT83XX_SPI_CPURXF2A        BIT(4)
-#define IT83XX_SPI_CPURXF1A        BIT(3)
-#define IT83XX_SPI_CPUTFA          BIT(1)
-#define IT83XX_SPI_TXFCR        REG8(IT83XX_SPI_BASE+0x02)
-#define IT83XX_SPI_TXFCMR          BIT(2)
-#define IT83XX_SPI_TXFR            BIT(1)
-#define IT83XX_SPI_TXFS            BIT(0)
-#define IT83XX_SPI_GCR2         REG8(IT83XX_SPI_BASE+0x03)
-#define IT83XX_SPI_RXF2OC          BIT(4)
-#define IT83XX_SPI_RXF1OC          BIT(3)
-#define IT83XX_SPI_RXFAR           BIT(0)
-#define IT83XX_SPI_IMR          REG8(IT83XX_SPI_BASE+0x04)
-#define IT83XX_SPI_RX_FIFO_FULL    BIT(7)
-#define IT83XX_SPI_RX_REACH        BIT(5)
-#define IT83XX_SPI_EDIM            BIT(2)
-#define IT83XX_SPI_ISR          REG8(IT83XX_SPI_BASE+0x05)
-#define IT83XX_SPI_TXFSR        REG8(IT83XX_SPI_BASE+0x06)
-#define IT83XX_SPI_ENDDETECTINT    BIT(2)
-#define IT83XX_SPI_RXFSR        REG8(IT83XX_SPI_BASE+0x07)
-#define IT83XX_SPI_RXFFSM          (BIT(4) | BIT(3))
-#define IT83XX_SPI_RXF2FS          BIT(2)
-#define IT83XX_SPI_RXF1FS          BIT(1)
-#ifdef CHIP_VARIANT_IT83202BX
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x08)
-#else
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x0b)
-#endif
-#define IT83XX_SPI_CPUWTFDB0    REG32(IT83XX_SPI_BASE+0x08)
-#define IT83XX_SPI_FCR          REG8(IT83XX_SPI_BASE+0x09)
-#define IT83XX_SPI_SPISRTXF        BIT(2)
-#define IT83XX_SPI_RXFR            BIT(1)
-#define IT83XX_SPI_RXFCMR          BIT(0)
-#define IT83XX_SPI_RXFRDRB0     REG32(IT83XX_SPI_BASE+0x0C)
-#define IT83XX_SPI_FTCB0R       REG8(IT83XX_SPI_BASE+0x18)
-#define IT83XX_SPI_FTCB1R       REG8(IT83XX_SPI_BASE+0x19)
-#define IT83XX_SPI_TCCB0        REG8(IT83XX_SPI_BASE+0x1A)
-#define IT83XX_SPI_TCCB1        REG8(IT83XX_SPI_BASE+0x1B)
-#define IT83XX_SPI_HPR2         REG8(IT83XX_SPI_BASE+0x1E)
-#define IT83XX_SPI_EMMCBMR      REG8(IT83XX_SPI_BASE+0x21)
-#define IT83XX_SPI_EMMCABM         BIT(1) /* eMMC Alternative Boot Mode */
-#define IT83XX_SPI_RX_VLISMR    REG8(IT83XX_SPI_BASE+0x26)
-#define IT83XX_SPI_RVLIM           BIT(0)
-#define IT83XX_SPI_RX_VLISR     REG8(IT83XX_SPI_BASE+0x27)
-#define IT83XX_SPI_RVLI            BIT(0)
-
-/* Platform Environment Control Interface (PECI) */
-#define IT83XX_PECI_BASE  0x00F02C00
-
-#define IT83XX_PECI_HOSTAR      REG8(IT83XX_PECI_BASE+0x00)
-#define IT83XX_PECI_HOCTLR      REG8(IT83XX_PECI_BASE+0x01)
-#define IT83XX_PECI_HOCMDR      REG8(IT83XX_PECI_BASE+0x02)
-#define IT83XX_PECI_HOTRADDR    REG8(IT83XX_PECI_BASE+0x03)
-#define IT83XX_PECI_HOWRLR      REG8(IT83XX_PECI_BASE+0x04)
-#define IT83XX_PECI_HORDLR      REG8(IT83XX_PECI_BASE+0x05)
-#define IT83XX_PECI_HOWRDR      REG8(IT83XX_PECI_BASE+0x06)
-#define IT83XX_PECI_HORDDR      REG8(IT83XX_PECI_BASE+0x07)
-#define IT83XX_PECI_HOCTL2R     REG8(IT83XX_PECI_BASE+0x08)
-#define IT83XX_PECI_RWFCSV      REG8(IT83XX_PECI_BASE+0x09)
-#define IT83XX_PECI_RRFCSV      REG8(IT83XX_PECI_BASE+0x0A)
-#define IT83XX_PECI_WFCSV       REG8(IT83XX_PECI_BASE+0x0B)
-#define IT83XX_PECI_RFCSV       REG8(IT83XX_PECI_BASE+0x0C)
-#define IT83XX_PECI_AWFCSV      REG8(IT83XX_PECI_BASE+0x0D)
-#define IT83XX_PECI_PADCTLR     REG8(IT83XX_PECI_BASE+0x0E)
-
-/*
- * The count number of the counter for 25 ms register.
- * The 25 ms register is calculated by (count number *1.024 kHz).
- */
-#define I2C_CLK_LOW_TIMEOUT  255 /* ~=249 ms */
-
-/* SMBus/I2C Interface (SMB/I2C) */
-#define IT83XX_SMB_BASE   0x00F01C00
-
-#define IT83XX_SMB_4P7USL       REG8(IT83XX_SMB_BASE+0x00)
-#define IT83XX_SMB_4P0USL       REG8(IT83XX_SMB_BASE+0x01)
-#define IT83XX_SMB_300NS        REG8(IT83XX_SMB_BASE+0x02)
-#define IT83XX_SMB_250NS        REG8(IT83XX_SMB_BASE+0x03)
-#define IT83XX_SMB_25MS         REG8(IT83XX_SMB_BASE+0x04)
-#define IT83XX_SMB_45P3USL      REG8(IT83XX_SMB_BASE+0x05)
-#define IT83XX_SMB_45P3USH      REG8(IT83XX_SMB_BASE+0x06)
-#define IT83XX_SMB_4P7A4P0H     REG8(IT83XX_SMB_BASE+0x07)
-#define IT83XX_SMB_SLVISELR     REG8(IT83XX_SMB_BASE+0x08)
-#define IT83XX_SMB_SCLKTS(ch)   REG8(IT83XX_SMB_BASE+0x09+ch)
-#define IT83XX_SMB_CHSEF        REG8(IT83XX_SMB_BASE+0x11)
-#define IT83XX_SMB_CHSAB        REG8(IT83XX_SMB_BASE+0x20)
-#define IT83XX_SMB_CHSCD        REG8(IT83XX_SMB_BASE+0x21)
-#define IT83XX_SMB_HOSTA(ch)    REG8(IT83XX_SMB_BASE+0x40+(ch << 6))
-#define IT83XX_SMB_HOCTL(ch)    REG8(IT83XX_SMB_BASE+0x41+(ch << 6))
-#define IT83XX_SMB_HOCMD(ch)    REG8(IT83XX_SMB_BASE+0x42+(ch << 6))
-#define IT83XX_SMB_TRASLA(ch)   REG8(IT83XX_SMB_BASE+0x43+(ch << 6))
-#define IT83XX_SMB_D0REG(ch)    REG8(IT83XX_SMB_BASE+0x44+(ch << 6))
-#define IT83XX_SMB_D1REG(ch)    REG8(IT83XX_SMB_BASE+0x45+(ch << 6))
-#define IT83XX_SMB_HOBDB(ch)    REG8(IT83XX_SMB_BASE+0x46+(ch << 6))
-#define IT83XX_SMB_PECERC(ch)   REG8(IT83XX_SMB_BASE+0x47+(ch << 6))
-#define IT83XX_SMB_SMBPCTL(ch)  REG8(IT83XX_SMB_BASE+0x4A+(ch << 6))
-#define IT83XX_SMB_HOCTL2(ch)   REG8(IT83XX_SMB_BASE+0x50+(ch << 6))
-#define IT83XX_SMB_SLVEN        (1 << 5)
-#define IT83XX_SMB_RESLADR      REG8(IT83XX_SMB_BASE+0x48)
-#define IT83XX_SMB_SLDA         REG8(IT83XX_SMB_BASE+0x49)
-#define IT83XX_SMB_SLSTA        REG8(IT83XX_SMB_BASE+0x4B)
-#define IT83XX_SMB_SPDS         (1 << 5)
-#define IT83XX_SMB_RCS          (1 << 3)
-#define IT83XX_SMB_STS          (1 << 2)
-#define IT83XX_SMB_SDS          (1 << 1)
-#define IT83XX_SMB_SICR         REG8(IT83XX_SMB_BASE+0x4C)
-#define IT83XX_SMB_RESLADR2     REG8(IT83XX_SMB_BASE+0x51)
-#define IT83XX_SMB_ENADDR2      (1 << 7)
-#define IT83XX_SMB_SFFCTL       REG8(IT83XX_SMB_BASE+0x55)
-#define IT83XX_SMB_HSAPE        BIT(1)
-#define IT83XX_SMB_SAFE         (1 << 0)
-#define IT83XX_SMB_SFFSTA       REG8(IT83XX_SMB_BASE+0x56)
-#define IT83XX_SMB_SFFFULL      (1 << 6)
-
-/* BRAM */
-#define IT83XX_BRAM_BASE  0x00F02200
-
-/* offset 0 ~ 0x7f */
-#define IT83XX_BRAM_BANK0(i)    REG8(IT83XX_BRAM_BASE + i)
-/* Battery backed RAM indices. */
-enum bram_indices {
-	/* reset flags uses 4 bytes */
-	BRAM_IDX_RESET_FLAGS0 = 0,
-	BRAM_IDX_RESET_FLAGS1 = 1,
-	BRAM_IDX_RESET_FLAGS2 = 2,
-	BRAM_IDX_RESET_FLAGS3 = 3,
-
-	/* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */
-	BRAM_IDX_PD0 =           4,
-	BRAM_IDX_PD1 =           5,
-	BRAM_IDX_PD2 =           6,
-
-	/* index 7 is reserved */
-
-	BRAM_IDX_SCRATCHPAD0  = 8,
-	BRAM_IDX_SCRATCHPAD1  = 9,
-	BRAM_IDX_SCRATCHPAD2  = 0xa,
-	BRAM_IDX_SCRATCHPAD3  = 0xb,
-
-	/* EC logs status */
-	BRAM_IDX_EC_LOG_STATUS = 0xc,
-
-	/* offset 0x0d ~ 0x1f are reserved for future use. */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * offset 0x20 ~ 0x7b are reserved for future use.
-	 * (apply to x86 platform)
-	 */
-
-	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0x7c,
-	BRAM_IDX_VALID_FLAGS1  = 0x7d,
-	BRAM_IDX_VALID_FLAGS2  = 0x7e,
-	BRAM_IDX_VALID_FLAGS3  = 0x7f
-	/* offset 0x7f is the end of BRAM bank 0. */
-#else
-
-	/* panic data uses 144 bytes (offset 0x20 ~ 0xaf) */
-	BRAM_PANIC_DATA_START  = 0x20,
-	BRAM_PANIC_DATA_END    = 0xaf,
-
-	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0xbc,
-	BRAM_IDX_VALID_FLAGS1  = 0xbd,
-	BRAM_IDX_VALID_FLAGS2  = 0xbe,
-	BRAM_IDX_VALID_FLAGS3  = 0xbf
-	/* offset 0xbf is the end of BRAM bank 1. */
-#endif
-};
-#define BRAM_RESET_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
-#define BRAM_RESET_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
-#define BRAM_RESET_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
-#define BRAM_RESET_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
-
-#define BRAM_SCRATCHPAD0        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
-#define BRAM_SCRATCHPAD1        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
-#define BRAM_SCRATCHPAD2        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
-#define BRAM_SCRATCHPAD3        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
-
-#define BRAM_EC_LOG_STATUS      IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS)
-enum bram_ec_logs_status {
-	EC_LOG_SAVED_IN_FLASH = 1,
-	EC_LOG_SAVED_IN_MEMORY
-};
-
-#define BRAM_VALID_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
-#define BRAM_VALID_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
-#define BRAM_VALID_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
-#define BRAM_VALID_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
-
-/*
- * These 128 bytes are use to latch port 80h data on x86 platform.
- * And they will be used to save panic data if the GPG1 reset mechanism
- * is enabled.
- */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
-/* offset 0x80 ~ 0xbf */
-#define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
-#else
-/* Length of bram panic data */
-#define BRAM_PANIC_LEN (BRAM_PANIC_DATA_END - BRAM_PANIC_DATA_START + 1)
-#endif
-
-/*
- * Enhanced SMBus/I2C Interface
- * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580
- * Ch_D: ch = 0x03  , Ch_E: ch = 0x00  , Ch_F: ch = 0x01
- */
-#define IT83XX_I2C_BASE   0x00F03500
-
-#define IT83XX_I2C_DRR(ch)           REG8(IT83XX_I2C_BASE+0x00+(ch << 7))
-#define IT83XX_I2C_PSR(ch)           REG8(IT83XX_I2C_BASE+0x01+(ch << 7))
-#define IT83XX_I2C_HSPR(ch)          REG8(IT83XX_I2C_BASE+0x02+(ch << 7))
-#define IT83XX_I2C_STR(ch)           REG8(IT83XX_I2C_BASE+0x03+(ch << 7))
-#define IT83XX_I2C_BB                (1 << 5)
-#define IT83XX_I2C_TIME_OUT          (1 << 3)
-#define IT83XX_I2C_RW                (1 << 2)
-#define IT83XX_I2C_INTPEND           (1 << 1)
-#define IT83XX_I2C_DHTR(ch)          REG8(IT83XX_I2C_BASE+0x04+(ch << 7))
-#define IT83XX_I2C_TOR(ch)           REG8(IT83XX_I2C_BASE+0x05+(ch << 7))
-#define IT83XX_I2C_DTR(ch)           REG8(IT83XX_I2C_BASE+0x08+(ch << 7))
-#define IT83XX_I2C_CTR(ch)           REG8(IT83XX_I2C_BASE+0x09+(ch << 7))
-#define IT83XX_I2C_INTEN             (1 << 6)
-#define IT83XX_I2C_MODE              (1 << 5)
-#define IT83XX_I2C_STARST            (1 << 4)
-#define IT83XX_I2C_ACK               (1 << 3)
-#define IT83XX_I2C_HALT              (1 << 0)
-#define IT83XX_I2C_CTR1(ch)          REG8(IT83XX_I2C_BASE+0x0A+(ch << 7))
-#define IT83XX_I2C_COMQ_EN           (1 << 7)
-#define IT83XX_I2C_MDL_EN            (1 << 1)
-#define IT83XX_I2C_BYTE_CNT_L(ch)    REG8(IT83XX_I2C_BASE+0x0C+(ch << 7))
-#define IT83XX_I2C_IRQ_ST(ch)        REG8(IT83XX_I2C_BASE+0x0D+(ch << 7))
-#define IT83XX_I2C_IDW_CLR           (1 << 3)
-#define IT83XX_I2C_IDR_CLR           (1 << 2)
-#define IT83XX_I2C_SLVDATAFLG        (1 << 1)
-#define IT83XX_I2C_P_CLR             (1 << 0)
-#define IT83XX_I2C_IDR(ch)           REG8(IT83XX_I2C_BASE+0x06+(ch << 7))
-#define IT83XX_I2C_TOS(ch)           REG8(IT83XX_I2C_BASE+0x07+(ch << 7))
-#define IT83XX_I2C_CLK_STR           (1 << 7)
-#define IT83XX_I2C_IDR2(ch)          REG8(IT83XX_I2C_BASE+0x1F+(ch << 7))
-#define IT83XX_I2C_RAMHA(ch)         REG8(IT83XX_I2C_BASE+0x23+(ch << 7))
-#define IT83XX_I2C_RAMLA(ch)         REG8(IT83XX_I2C_BASE+0x24+(ch << 7))
-#define IT83XX_I2C_RAMHA2(ch)        REG8(IT83XX_I2C_BASE+0x2B+(ch << 7))
-#define IT83XX_I2C_RAMLA2(ch)        REG8(IT83XX_I2C_BASE+0x2C+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH(ch)      REG8(IT83XX_I2C_BASE+0x25+(ch << 7))
-#define IT83XX_I2C_CMD_ADDL(ch)      REG8(IT83XX_I2C_BASE+0x26+(ch << 7))
-#define IT83XX_I2C_RAMH2A(ch)        REG8(IT83XX_I2C_BASE+0x50+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH2(ch)     REG8(IT83XX_I2C_BASE+0x52+(ch << 7))
-
-enum i2c_channels {
-	IT83XX_I2C_CH_A,  /* GPIO.B3/B4 */
-	IT83XX_I2C_CH_B,  /* GPIO.C1/C2 */
-	IT83XX_I2C_CH_C,  /* GPIO.F6/F7 or GPIO.C7/F7 */
-	IT83XX_I2C_CH_D,  /* GPIO.H1/H2 */
-	IT83XX_I2C_CH_E,  /* GPIO.E0/E7 */
-	IT83XX_I2C_CH_F,  /* GPIO.A4/A5 (for util/iteflash) */
-	IT83XX_I2C_PORT_COUNT,
-};
-
-#define USB_VID_ITE 0x048d
-
-#define IT83XX_ESPI_BASE  0x00F03100
-
-#define IT83XX_ESPI_GCAC1      REG8(IT83XX_ESPI_BASE+0x05)
-#define IT83XX_ESPI_ESPCTRL0   REG8(IT83XX_ESPI_BASE+0x90)
-#define IT83XX_ESPI_ESGCTRL0   REG8(IT83XX_ESPI_BASE+0xA0)
-#define IT83XX_ESPI_ESGCTRL1   REG8(IT83XX_ESPI_BASE+0xA1)
-#define IT83XX_ESPI_ESGCTRL2   REG8(IT83XX_ESPI_BASE+0xA2)
-
-/* eSPI VW */
-#define IT83XX_ESPI_VW_BASE  0x00F03200
-#define IT83XX_ESPI_VWIDX(i)   REG8(IT83XX_ESPI_VW_BASE+(i))
-
-#define VW_LEVEL_FIELD(f)          ((f) << 0)
-#define VW_VALID_FIELD(f)          ((f) << 4)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
-#define VW_IDX_2_SLP_S3            BIT(0)
-#define VW_IDX_2_SLP_S4            BIT(1)
-#define VW_IDX_2_SLP_S5            BIT(2)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
-#define VW_IDX_3_SUS_STAT          BIT(0)
-#define VW_IDX_3_PLTRST            BIT(1)
-#define VW_IDX_3_OOB_RST_WARN      BIT(2)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
-#define VW_IDX_4_OOB_RST_ACK       BIT(0)
-#define VW_IDX_4_WAKE              BIT(2)
-#define VW_IDX_4_PME               BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
-#define VW_IDX_5_SLAVE_BTLD_DONE   BIT(0)
-#define VW_IDX_5_FATAL             BIT(1)
-#define VW_IDX_5_NON_FATAL         BIT(2)
-#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
-#define VW_IDX_5_BTLD_STATUS_DONE  (VW_IDX_5_SLAVE_BTLD_DONE | \
-					VW_IDX_5_SLAVE_BTLD_STATUS)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
-#define VW_IDX_6_SCI               BIT(0)
-#define VW_IDX_6_SMI               BIT(1)
-#define VW_IDX_6_RCIN              BIT(2)
-#define VW_IDX_6_HOST_RST_ACK      BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
-#define VW_IDX_7_HOST_RST_WARN     BIT(0)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
-#define VW_IDX_40_SUS_ACK           BIT(0)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
-#define VW_IDX_41_SUS_WARN          BIT(0)
-#define VW_IDX_41_SUS_PWRDN_ACK     BIT(1)
-#define VW_IDX_41_SLP_A             BIT(3)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
-#define VW_IDX_42_SLP_LAN           BIT(0)
-#define VW_IDX_42_SLP_WLAN          BIT(1)
-
-#define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
-#define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
-#define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
-
-#define IT83XX_ESPI_VWCTRL0    REG8(IT83XX_ESPI_VW_BASE+0x90)
-#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
-
-#define IT83XX_ESPI_VWCTRL1    REG8(IT83XX_ESPI_VW_BASE+0x91)
-#define IT83XX_ESPI_VWCTRL2    REG8(IT83XX_ESPI_VW_BASE+0x92)
-#define IT83XX_ESPI_VWCTRL3    REG8(IT83XX_ESPI_VW_BASE+0x93)
-
-/* eSPI Queue 0 */
-#define IT83XX_ESPI_QUEUE_BASE  0x00F03300
-/* PUT_PC data byte 0 - 63 */
-#define IT83XX_ESPI_QUEUE_PUT_PC(i)  REG8(IT83XX_ESPI_QUEUE_BASE+(i))
-/* PUT_OOB data byte 0 - 79 */
-#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i))
-
-/* USB Controller */
-#define IT83XX_USB_BASE   0x00F02F00
-
-#define IT83XX_USB_P0MCR  REG8(IT83XX_USB_BASE+0xE4)
-#define USB_DP_DM_PULL_DOWN_EN BIT(4)
-
-/* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-/* --- MISC (not implemented yet) --- */
-
-#define IT83XX_PS2_BASE   0x00F01700
-#define IT83XX_EGPIO_BASE 0x00F02100
-#define IT83XX_CIR_BASE   0x00F02300
-#define IT83XX_DBGR_BASE  0x00F02500
-#define IT83XX_OW_BASE    0x00F02A00
-#define IT83XX_CEC_BASE   0x00F02E00
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
deleted file mode 100644
index 63f8e4247c..0000000000
--- a/chip/it83xx/spi.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI driver for Chrome EC.
- *
- * This uses FIFO mode to handle transmission and reception.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-#define SPI_RX_MAX_FIFO_SIZE 256
-#define SPI_TX_MAX_FIFO_SIZE 256
-
-#define EC_SPI_PREAMBLE_LENGTH 4
-#define EC_SPI_PAST_END_LENGTH 4
-
-/* Max data size for a version 3 request/response packet. */
-#define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
-
-static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	/* This is the byte which matters */
-	EC_SPI_FRAME_START,
-};
-
-/* Store read and write data buffer */
-static uint8_t in_msg[SPI_RX_MAX_FIFO_SIZE] __aligned(4);
-static uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet spi_packet;
-
-enum spi_peripheral_state_machine {
-	/* Ready to receive next request */
-	SPI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SPI_STATE_RECEIVING,
-	/* Processing request */
-	SPI_STATE_PROCESSING,
-	/* Received bad data */
-	SPI_STATE_RX_BAD,
-
-	SPI_STATE_COUNT,
-} spi_peripheral_state;
-
-static const int spi_response_state[] = {
-	[SPI_STATE_READY_TO_RECV] = EC_SPI_OLD_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
-};
-BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
-
-static void spi_set_state(int state)
-{
-	/* SPI peripheral state machine */
-	spi_peripheral_state = state;
-	/* Response spi peripheral state */
-	IT83XX_SPI_SPISRDR = spi_response_state[state];
-}
-
-static void reset_rx_fifo(void)
-{
-	/* End Rx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0x00;
-	/* Rx FIFO reset and count monitor reset */
-	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
-}
-
-/* This routine handles spi received unexcepted data */
-static void spi_bad_received_data(int count)
-{
-	int i;
-
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	spi_set_state(SPI_STATE_RX_BAD);
-	/* End CPU access Rx FIFO, so it can clock in bytes from AP again. */
-	IT83XX_SPI_TXRXFAR = 0;
-
-	CPRINTS("SPI rx bad data");
-	CPRINTF("in_msg=[");
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-}
-
-static void spi_response_host_data(uint8_t *out_msg_addr, int tx_size)
-{
-	int i;
-
-	/* Tx FIFO reset and count monitor reset */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-	/* CPU Tx FIFO1 and FIFO2 access */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
-
-	for (i = 0; i < tx_size; i += 4)
-		/* Write response data from out_msg buffer to Tx FIFO */
-		IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(out_msg_addr + i);
-
-	/*
-	 * After writing data to Tx FIFO is finished, this bit will
-	 * be to indicate the SPI peripheral.
-	 */
-	IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
-	/* End Tx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0;
-	/* SPI peripheral read Tx FIFO */
-	IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
-}
-
-/*
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response_packet(struct host_packet *pkt)
-{
-	int i, tx_size;
-
-	if (spi_peripheral_state != SPI_STATE_PROCESSING) {
-		CPRINTS("The request data is not processing.");
-		return;
-	}
-
-	/* Append our past-end byte, which we reserved space for. */
-	for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++)
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
-
-	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
-
-	/* Transmit the reply */
-	spi_response_host_data(out_msg, tx_size);
-}
-
-/* Store request data from Rx FIFO to in_msg buffer */
-static void spi_host_request_data(uint8_t *in_msg_addr, int count)
-{
-	int i;
-
-	/* CPU Rx FIFO1 access */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPURXF1A;
-	/*
-	 * In spi_parse_header, the request data will separate to
-	 * write in_msg buffer so we cannot set CPU to end accessing
-	 * Rx FIFO in this function. We will set IT83XX_SPI_TXRXFAR = 0
-	 * in reset_rx_fifo.
-	 */
-
-	for (i = 0; i < count; i += 4)
-		/* Get data from controller to buffer */
-		*(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
-}
-
-/* Parse header for version of spi-protocol */
-static void spi_parse_header(void)
-{
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-
-	/* Store request data from Rx FIFO to in_msg buffer */
-	spi_host_request_data(in_msg, sizeof(*r));
-
-	/* Protocol version 3 */
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		int pkt_size;
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			return spi_bad_received_data(pkt_size);
-
-		/* Store request data from Rx FIFO to in_msg buffer */
-		spi_host_request_data(in_msg + sizeof(*r),
-			pkt_size - sizeof(*r));
-
-		/* Set up parameters for host request */
-		spi_packet.send_response = spi_send_response_packet;
-		spi_packet.request = in_msg;
-		spi_packet.request_temp = NULL;
-		spi_packet.request_max = sizeof(in_msg);
-		spi_packet.request_size = pkt_size;
-
-		/* Response must start with the preamble */
-		memcpy(out_msg, out_preamble, EC_SPI_PREAMBLE_LENGTH);
-
-		spi_packet.response = out_msg + EC_SPI_PREAMBLE_LENGTH;
-		/* Reserve space for frame start and trailing past-end byte */
-		spi_packet.response_max = SPI_MAX_RESPONSE_SIZE;
-		spi_packet.response_size = 0;
-		spi_packet.driver_result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		spi_set_state(SPI_STATE_PROCESSING);
-
-		/* Go to common-layer to handle request */
-		host_packet_receive(&spi_packet);
-	} else {
-		/* Invalid version number */
-		CPRINTS("Invalid version number");
-		return spi_bad_received_data(1);
-	}
-}
-
-void spi_event(enum gpio_signal signal)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* EC has started receiving the request from the AP */
-		spi_set_state(SPI_STATE_RECEIVING);
-		/* Disable idle task deep sleep bit of SPI in S0. */
-		disable_sleep(SLEEP_MASK_SPI);
-	}
-}
-
-void spi_peripheral_int_handler(void)
-{
-	if (IS_ENABLED(CONFIG_BOOTBLOCK) &&
-	    (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) &&
-	    (IT83XX_SPI_EMMCBMR & IT83XX_SPI_EMMCABM)) {
-		spi_host_request_data(in_msg, 128);
-		/* End CPU access RX FIFO */
-		IT83XX_SPI_TXRXFAR = 0;
-		/* Write to clear interrupt status */
-		IT83XX_SPI_ISR = 0xff;
-		/*
-		 * Handle eMMC CMD0:
-		 * GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION
-		 */
-		spi_emmc_cmd0_isr((uint32_t *)in_msg);
-		return;
-	}
-
-	/*
-	 * The status of SPI end detection interrupt bit is set, it
-	 * means that host command parse has been completed and AP
-	 * has received the last byte which is EC_SPI_PAST_END from
-	 * EC responded data, then AP ended the transaction.
-	 */
-	if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
-		/* Ready to receive */
-		spi_set_state(SPI_STATE_READY_TO_RECV);
-		/*
-		 * Once there is no SPI active, enable idle task deep
-		 * sleep bit of SPI in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_SPI);
-		/* CS# is deasserted, so write clear all peripheral status */
-		IT83XX_SPI_ISR = 0xff;
-	}
-	/*
-	 * The status of Rx valid length interrupt bit is set that
-	 * indicates reached target count(IT83XX_SPI_FTCB1R,
-	 * IT83XX_SPI_FTCB0R) and the length field of the host
-	 * requested data.
-	 */
-	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
-		/* write clear peripheral status */
-		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-		/* Parse header for version of spi-protocol */
-		spi_parse_header();
-	}
-
-	/* Clear the interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-}
-
-static void spi_init(void)
-{
-	/* Set FIFO data target count */
-	struct ec_host_request cmd_head;
-
-	/*
-	 * Target count means the size of host request.
-	 * And plus extra 4 bytes because the CPU accesses FIFO base on
-	 * word. If host requested data length is one byte, we need to
-	 * align the data length to 4 bytes.
-	 */
-	int target_count = sizeof(cmd_head) + 4;
-	/* Offset of data_len member of host request. */
-	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
-
-	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
-	IT83XX_SPI_FTCB0R = target_count & 0xff;
-	/*
-	 * The register setting can capture the length field of host
-	 * request.
-	 */
-	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
-	IT83XX_SPI_TCCB0 = offset & 0xff;
-
-	/* Set SPI pins to alternate function */
-	gpio_config_module(MODULE_SPI, 1);
-	/*
-	 * Memory controller configuration register 3.
-	 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
-	 */
-	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
-	/* Set unused blocked byte */
-	IT83XX_SPI_HPR2 = 0x00;
-	/* Rx valid length interrupt enabled */
-	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
-	/*
-	 * General control register2
-	 * bit4 : Rx FIFO2 will not be overwrited once it's full.
-	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
-	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
-	 */
-	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-				| IT83XX_SPI_RXFAR;
-	/*
-	 * Interrupt mask register (0b:Enable, 1b:Mask)
-	 * bit5 : Rx byte reach interrupt mask
-	 * bit2 : SPI end detection interrupt mask
-	 */
-	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
-	/* Reset fifo and prepare to for next transaction */
-	reset_rx_fifo();
-	/* Ready to receive */
-	spi_set_state(SPI_STATE_READY_TO_RECV);
-	/* Interrupt status register(write one to clear) */
-	IT83XX_SPI_ISR = 0xff;
-	/* SPI peripheral enable (after settings are ready) */
-	IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
-	/* Enable SPI peripheral interrupt */
-	task_clear_pending_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-	task_enable_irq(IT83XX_IRQ_SPI_PERIPHERAL);
-	/* Enable SPI chip select pin interrupt */
-	gpio_clear_pending_interrupt(GPIO_SPI0_CS);
-	gpio_enable_interrupt(GPIO_SPI0_CS);
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/* reset peripheral SPI module */
-static void spi_reset(void)
-{
-	/*
-	 * Reset SPI module before sysjump. New FW images (RO/RW) will
-	 * re-configure it.
-	 */
-	IT83XX_GCTRL_RSTC5 |= BIT(1);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, spi_reset, HOOK_PRIO_DEFAULT);
-
-#if defined(SECTION_IS_RO) && defined(CONFIG_BOOTBLOCK)
-/* AP has booted */
-void emmc_ap_jump_to_bl(enum gpio_signal signal)
-{
-	/* Transmission completed. Set SPI pin mux to AP communication mode */
-	IT83XX_GCTRL_PIN_MUX0 &= ~BIT(7);
-	/* Reset and re-initialize SPI module to communication mode */
-	spi_reset();
-	spi_init();
-	/* Disable interrupt of detection of AP's BOOTBLOCK_EN_L */
-	gpio_disable_interrupt(GPIO_BOOTBLOCK_EN_L);
-	enable_sleep(SLEEP_MASK_EMMC);
-
-	CPRINTS("eMMC emulation disabled. AP Jumped to BL");
-}
-#endif
-
-/* Get protocol information */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		spi_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/it83xx/spi_master.c b/chip/it83xx/spi_master.c
deleted file mode 100644
index d3898deef6..0000000000
--- a/chip/it83xx/spi_master.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-enum sspi_clk_sel {
-	sspi_clk_24mhz = 0,
-	sspi_clk_12mhz,
-	sspi_clk_8mhz,
-	sspi_clk_6mhz,
-	sspi_clk_4p8mhz,
-	sspi_clk_4mhz,
-	sspi_clk_3p428mhz,
-	sspi_clk_3mhz,
-};
-
-enum sspi_ch_sel {
-	SSPI_CH_CS0 = 0,
-	SSPI_CH_CS1,
-};
-
-static void sspi_frequency(enum sspi_clk_sel freq)
-{
-	/*
-	 * bit[6:5]
-	 * Bit 6:Clock Polarity (CLPOL)
-	 * 0: SSCK is low in the idle mode.
-	 * 1: SSCK is high in the idle mode.
-	 * Bit 5:Clock Phase (CLPHS)
-	 * 0: Latch data on the first SSCK edge.
-	 * 1: Latch data on the second SSCK edge.
-	 *
-	 * bit[4:2]
-	 * 000b: 1/2 clk_sspi
-	 * 001b: 1/4 clk_sspi
-	 * 010b: 1/6 clk_sspi
-	 * 011b: 1/8 clk_sspi
-	 * 100b: 1/10 clk_sspi
-	 * 101b: 1/12 clk_sspi
-	 * 110b: 1/14 clk_sspi
-	 * 111b: 1/16 clk_sspi
-	 *
-	 * SSCK frequency is [freq] MHz and mode 3.
-	 * note, clk_sspi need equal to 48MHz above.
-	 */
-	IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2));
-}
-
-static void sspi_transmission_end(void)
-{
-	/* Write 1 to end the SPI transmission. */
-	IT83XX_SSPI_SPISTS = 0x20;
-
-	/* Short delay for "Transfer End Flag" */
-	IT83XX_GCTRL_WNCKR = 0;
-
-	/* Write 1 to clear this bit and terminate data transmission. */
-	IT83XX_SSPI_SPISTS = 0x02;
-}
-
-/* We assume only one SPI port in the chip, one SPI device */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-
-	if (enable) {
-		/*
-		 * bit[5:4]
-		 * 00b: SPI channel 0 and channel 1 are disabled.
-		 * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled.
-		 * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled.
-		 * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled.
-		 */
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 |= 0x20;
-		else
-			IT83XX_GPIO_GRC1 |= 0x10;
-
-		gpio_config_module(MODULE_SPI_CONTROLLER, 1);
-	} else {
-		if (port == SSPI_CH_CS1)
-			IT83XX_GPIO_GRC1 &= ~0x20;
-		else
-			IT83XX_GPIO_GRC1 &= ~0x10;
-
-		gpio_config_module(MODULE_SPI_CONTROLLER, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
-{
-	int idx;
-	uint8_t port = spi_device->port;
-	static struct mutex spi_mutex;
-
-	mutex_lock(&spi_mutex);
-	/* bit[0]: Write cycle */
-	IT83XX_SSPI_SPICTRL2 &= ~0x04;
-	for (idx = 0x00; idx < txlen; idx++) {
-		IT83XX_SSPI_SPIDATA = txdata[idx];
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-	}
-
-	/* bit[1]: Read cycle */
-	IT83XX_SSPI_SPICTRL2 |= 0x04;
-	for (idx = 0x00; idx < rxlen; idx++) {
-		if (port == SSPI_CH_CS1)
-			/* Write 1 to start the data transmission of CS1 */
-			IT83XX_SSPI_SPISTS |= 0x08;
-		else
-			/* Write 1 to start the data transmission of CS0 */
-			IT83XX_SSPI_SPISTS |= 0x10;
-		rxdata[idx] = IT83XX_SSPI_SPIDATA;
-	}
-
-	sspi_transmission_end();
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-static void sspi_init(void)
-{
-	int i;
-
-	clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0);
-	sspi_frequency(sspi_clk_8mhz);
-
-	/*
-	 * bit[5:3] Byte Width (BYTEWIDTH)
-	 * 000b: 8-bit transmission
-	 * 001b: 1-bit transmission
-	 * 010b: 2-bit transmission
-	 * 011b: 3-bit transmission
-	 * 100b: 4-bit transmission
-	 * 101b: 5-bit transmission
-	 * 110b: 6-bit transmission
-	 * 111b: 7-bit transmission
-	 *
-	 * bit[1] Blocking selection
-	 */
-	IT83XX_SSPI_SPICTRL2 |= 0x02;
-
-	for (i = 0; i < spi_devices_used; i++)
-		/* Disabling spi module */
-		spi_enable(&spi_devices[i], 0);
-}
-DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI);
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
deleted file mode 100644
index 16871e5826..0000000000
--- a/chip/it83xx/system.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "ec2i_chip.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "intc.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	__enter_hibernate(seconds, microseconds);
-}
-
-/* Clear reset flags if it's not cleared in check_reset_cause() */
-static int delayed_clear_reset_flags;
-static void clear_reset_flags(void)
-{
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			delayed_clear_reset_flags) {
-		chip_save_reset_flags(0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
-
-#if !defined(CONFIG_HOSTCMD_LPC) && !defined(CONFIG_HOSTCMD_ESPI)
-static void system_save_panic_data_to_bram(void)
-{
-	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
-
-	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
-		IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START) = ptr[i];
-}
-
-static void system_restore_panic_data_from_bram(void)
-{
-	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
-
-	for (int i = 0; i < CONFIG_PANIC_DATA_SIZE; i++)
-		ptr[i] = IT83XX_BRAM_BANK0(i + BRAM_PANIC_DATA_START);
-}
-BUILD_ASSERT(BRAM_PANIC_LEN >= CONFIG_PANIC_DATA_SIZE);
-#else
-static void system_save_panic_data_to_bram(void) {}
-static void system_restore_panic_data_from_bram(void) {}
-#endif
-
-static void system_reset_ec_by_gpg1(void)
-{
-	system_save_panic_data_to_bram();
-	/* Set GPG1 as output high and wait until EC reset. */
-	IT83XX_GPIO_CTRL(GPIO_G, 1) = GPCR_PORT_PIN_MODE_OUTPUT;
-	IT83XX_GPIO_DATA(GPIO_G) |= BIT(1);
-	while (1)
-		;
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags;
-	uint8_t raw_reset_cause = IT83XX_GCTRL_RSTS & 0x03;
-	uint8_t raw_reset_cause2 = IT83XX_GCTRL_SPCTRL4 & 0x07;
-
-	/* Restore saved reset flags. */
-	flags = chip_read_reset_flags();
-
-	/* Clear reset cause. */
-	IT83XX_GCTRL_RSTS |= 0x03;
-	IT83XX_GCTRL_SPCTRL4 |= 0x07;
-
-	/* Determine if watchdog reset or power on reset. */
-	if (raw_reset_cause & 0x02) {
-		flags |= EC_RESET_FLAG_WATCHDOG;
-		if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) {
-			/*
-			 * Save watchdog reset flag to BRAM so we can restore
-			 * the flag on next reboot.
-			 */
-			chip_save_reset_flags(EC_RESET_FLAG_WATCHDOG);
-			/*
-			 * Assert GPG1 to reset EC and then EC_RST_ODL will be
-			 * toggled.
-			 */
-			system_reset_ec_by_gpg1();
-		}
-	} else if (raw_reset_cause & 0x01) {
-		flags |= EC_RESET_FLAG_POWER_ON;
-	} else {
-		if ((IT83XX_GCTRL_RSTS & 0xC0) == 0x80)
-			flags |= EC_RESET_FLAG_POWER_ON;
-	}
-
-	if (raw_reset_cause2 & 0x04)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	/* watchdog module triggers these reset */
-	if (flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_SOFT))
-		flags &= ~EC_RESET_FLAG_WATCHDOG;
-
-	/*
-	 * On power-on of some boards, H1 releases the EC from reset but then
-	 * quickly asserts and releases the reset a second time. This means the
-	 * EC sees 2 resets. In order to carry over some important flags (e.g.
-	 * HIBERNATE) to the second resets, the reset flag will not be wiped if
-	 * we know this is the first reset.
-	 */
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			(flags & EC_RESET_FLAG_POWER_ON)) {
-		if (flags & EC_RESET_FLAG_INITIAL_PWR) {
-			/* Second boot, clear the flag immediately */
-			chip_save_reset_flags(0);
-		} else {
-			/*
-			 * First boot, Keep current flags and set INITIAL_PWR
-			 * flag. EC reset should happen soon.
-			 *
-			 * It's possible that H1 never trigger EC reset, or
-			 * reset happens before this line. Both cases should be
-			 * fine because we will have the correct flag anyway.
-			 */
-			chip_save_reset_flags(chip_read_reset_flags() |
-						EC_RESET_FLAG_INITIAL_PWR);
-
-			/*
-			 * Schedule chip_save_reset_flags(0) later.
-			 * Wait until end of HOOK_INIT should be long enough.
-			 */
-			delayed_clear_reset_flags = 1;
-		}
-	} else {
-		/* Clear saved reset flags. */
-		chip_save_reset_flags(0);
-	}
-
-	system_set_reset_flags(flags);
-
-	/* Clear PD contract recorded in bram if this is a power-on reset. */
-	if (IS_ENABLED(CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM) &&
-	   (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
-		for (int i = 0; i < MAX_SYSTEM_BBRAM_IDX_PD_PORTS; i++)
-			system_set_bbram((SYSTEM_BBRAM_IDX_PD0 + i), 0);
-	}
-
-	if ((IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) &&
-		(flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN)))
-		system_restore_panic_data_from_bram();
-}
-
-static void system_reset_cause_is_unknown(void)
-{
-	/* No reset cause and not sysjump. */
-	if (!system_get_reset_flags() && !system_jumped_to_this_image())
-		/*
-		 * We decrease 4 or 2 for "ec_reset_lp" here, that depend on
-		 * which jump and link instruction has executed.
-		 * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4)
-		 */
-		ccprintf("===Unknown reset! jump from %x or %x===\n",
-				ec_reset_lp - 4, ec_reset_lp - 2);
-}
-DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST);
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
-	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-	    (reset_flags & EC_RESET_FLAG_HARD) ||
-	    (reset_flags & EC_RESET_FLAG_SOFT) ||
-	    (reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-void chip_pre_init(void)
-{
-	/* bit1=0: disable pre-defined command */
-	IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_HSAPE;
-
-	/* bit0, EC received the special waveform from iteflash */
-	if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) {
-		/*
-		 * Wait ~200ms, so iteflash will have enough time to let
-		 * EC enter follow mode. And once EC goes into follow mode, EC
-		 * will be stayed here (no following sequences, eg:
-		 * enable watchdog/write protect/power-on sequence...) until
-		 * we reset it.
-		 */
-		for (int i = 0; i < (200 * MSEC / 15); i++)
-			/* delay ~15.25us */
-			IT83XX_GCTRL_WNCKR = 0;
-	}
-
-	if (IS_ENABLED(IT83XX_ETWD_HW_RESET_SUPPORT))
-		/* System triggers a soft reset by default (command: reboot). */
-		IT83XX_GCTRL_ETWDUARTCR &= ~ETWD_HW_RST_EN;
-
-	if (IS_ENABLED(IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED))
-		/*
-		 * bit7: wake up CPU if it is in low power mode and
-		 * an interrupt is pending.
-		 */
-		IT83XX_GCTRL_WMCR |= BIT(7);
-}
-
-#define BRAM_VALID_MAGIC        0x4252414D  /* "BRAM" */
-#define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff)
-#define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff)
-#define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff)
-#define BRAM_VALID_MAGIC_FIELD3 ((BRAM_VALID_MAGIC >> 24) & 0xff)
-void chip_bram_valid(void)
-{
-	int i;
-
-	if ((BRAM_VALID_FLAGS0 != BRAM_VALID_MAGIC_FIELD0) ||
-	    (BRAM_VALID_FLAGS1 != BRAM_VALID_MAGIC_FIELD1) ||
-	    (BRAM_VALID_FLAGS2 != BRAM_VALID_MAGIC_FIELD2) ||
-	    (BRAM_VALID_FLAGS3 != BRAM_VALID_MAGIC_FIELD3)) {
-		/*
-		 * Magic does not match, so BRAM must be uninitialized. Clear
-		 * entire Bank0 BRAM, and set magic value.
-		 */
-		for (i = 0; i < BRAM_IDX_VALID_FLAGS0; i++)
-			IT83XX_BRAM_BANK0(i) = 0;
-
-		BRAM_VALID_FLAGS0 = BRAM_VALID_MAGIC_FIELD0;
-		BRAM_VALID_FLAGS1 = BRAM_VALID_MAGIC_FIELD1;
-		BRAM_VALID_FLAGS2 = BRAM_VALID_MAGIC_FIELD2;
-		BRAM_VALID_FLAGS3 = BRAM_VALID_MAGIC_FIELD3;
-	}
-
-#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
-	if (BRAM_EC_LOG_STATUS == EC_LOG_SAVED_IN_FLASH) {
-		/* Restore EC logs from flash. */
-		memcpy((void *)__preserved_logs_start,
-			(const void *)CHIP_FLASH_PRESERVE_LOGS_BASE,
-			(uintptr_t)__preserved_logs_size);
-	}
-	BRAM_EC_LOG_STATUS = 0;
-#endif
-}
-
-void system_pre_init(void)
-{
-	/* No initialization required */
-
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	uint32_t flags = 0;
-	flags |= BRAM_RESET_FLAGS0 << 24;
-	flags |= BRAM_RESET_FLAGS1 << 16;
-	flags |= BRAM_RESET_FLAGS2 << 8;
-	flags |= BRAM_RESET_FLAGS3;
-	return flags;
-}
-
-void chip_save_reset_flags(uint32_t save_flags)
-{
-	BRAM_RESET_FLAGS0 = save_flags >> 24;
-	BRAM_RESET_FLAGS1 = (save_flags >> 16) & 0xff;
-	BRAM_RESET_FLAGS2 = (save_flags >> 8) & 0xff;
-	BRAM_RESET_FLAGS3 = save_flags & 0xff;
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* We never get this warning message in normal case. */
-	if (IT83XX_GCTRL_DBGROS & IT83XX_SMB_DBGR) {
-		ccprintf("!Reset will be failed due to EC is in debug mode!\n");
-		cflush();
-	}
-
-#if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
-	/* Saving EC logs into flash before reset. */
-	crec_flash_physical_erase(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		CHIP_FLASH_PRESERVE_LOGS_SIZE);
-	crec_flash_physical_write(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		(uintptr_t)__preserved_logs_size, __preserved_logs_start);
-	BRAM_EC_LOG_STATUS = EC_LOG_SAVED_IN_FLASH;
-#endif
-
-	/* Disable interrupts to avoid task swaps during reboot. */
-	interrupt_disable();
-
-	/* Handle saving common reset flags. */
-	system_encode_save_flags(flags, &save_flags);
-
-	if (clock_ec_wake_from_sleep())
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* bit0: enable watchdog hardware reset. */
-#ifdef IT83XX_ETWD_HW_RESET_SUPPORT
-	if (flags & SYSTEM_RESET_HARD)
-		IT83XX_GCTRL_ETWDUARTCR |= ETWD_HW_RST_EN;
-#endif
-	/* Set GPG1 as output high and wait until EC reset. */
-	if (IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1))
-		system_reset_ec_by_gpg1();
-
-	/*
-	 * Writing invalid key to watchdog module triggers a soft or hardware
-	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
-	 */
-	IT83XX_ETWD_ETWCFG |= 0x20;
-	IT83XX_ETWD_EWDKEYR = 0x00;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	BRAM_SCRATCHPAD3 = (value >> 24) & 0xff;
-	BRAM_SCRATCHPAD2 = (value >> 16) & 0xff;
-	BRAM_SCRATCHPAD1 = (value >> 8) & 0xff;
-	BRAM_SCRATCHPAD0 = value & 0xff;
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = (BRAM_SCRATCHPAD3 << 24) | (BRAM_SCRATCHPAD2 << 16) |
-		 (BRAM_SCRATCHPAD1 << 8) | (BRAM_SCRATCHPAD0);
-	return EC_SUCCESS;
-}
-
-static uint32_t system_get_chip_id(void)
-{
-#ifdef IT83XX_CHIP_ID_3BYTES
-	return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) |
-		IT83XX_GCTRL_CHIPID3;
-#else
-	return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2;
-#endif
-}
-
-static uint8_t system_get_chip_version(void)
-{
-	/* bit[3-0], chip version */
-	return IT83XX_GCTRL_CHIPVER & 0x0F;
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "ite";
-}
-
-const char *system_get_chip_name(void)
-{
-	static char buf[8] = {'i', 't'};
-	int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3);
-	uint32_t chip_id = system_get_chip_id();
-
-	for (int n = 2; num >= 0; n++, num--)
-		buf[n] = to_hex(chip_id >> (num * 4) & 0xF);
-
-	return buf;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = system_get_chip_version();
-
-	buf[0] = to_hex(rev + 0xa);
-	buf[1] = 'x';
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bram_idx_lookup(enum system_bbram_idx idx)
-{
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BRAM_IDX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BRAM_IDX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BRAM_IDX_PD2;
-	return -1;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int bram_idx = bram_idx_lookup(idx);
-
-	if (bram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	*value = IT83XX_BRAM_BANK0(bram_idx);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int bram_idx = bram_idx_lookup(idx);
-
-	if (bram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	IT83XX_BRAM_BANK0(bram_idx) = value;
-	return EC_SUCCESS;
-}
-
-uintptr_t system_get_fw_reset_vector(uintptr_t base)
-{
-	/*
-	 * Because our reset vector is at the beginning of image copy
-	 * (see init.S). So I just need to return 'base' here and EC will jump
-	 * to the reset vector.
-	 */
-	return base;
-}
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
deleted file mode 100644
index d0b645e68c..0000000000
--- a/chip/it83xx/uart.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "intc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Traces on UART1 */
-#define UART_PORT      0
-#define UART_PORT_HOST 1
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (IT83XX_UART_IER(UART_PORT) & 0x02)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/* Re-enable the transmit interrupt. */
-	IT83XX_UART_IER(UART_PORT) |= 0x02;
-}
-
-void uart_tx_stop(void)
-{
-	IT83XX_UART_IER(UART_PORT) &= ~0x02;
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/*
-	 * Wait for transmit FIFO empty (TEMT) and transmitter holder
-	 * register and transmitter shift registers to be empty (THRE).
-	 */
-	while ((IT83XX_UART_LSR(UART_PORT) & 0x60) != 0x60)
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/* Transmit is ready when FIFO is empty (THRE). */
-	return IT83XX_UART_LSR(UART_PORT) & 0x20;
-}
-
-int uart_tx_in_progress(void)
-{
-	/*
-	 * Transmit is in progress if transmit holding register or transmitter
-	 * shift register are not empty (TEMT).
-	 */
-	return !(IT83XX_UART_LSR(UART_PORT) & 0x40);
-}
-
-int uart_rx_available(void)
-{
-	return IT83XX_UART_LSR(UART_PORT) & 0x01;
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	IT83XX_UART_THR(UART_PORT) = c;
-}
-
-int uart_read_char(void)
-{
-	return IT83XX_UART_RBR(UART_PORT);
-}
-
-static void uart_ec_interrupt(void)
-{
-	uint8_t uart_ier;
-
-	/* clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_UART1);
-
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-
-	uart_ier = IT83XX_UART_IER(UART_PORT);
-	IT83XX_UART_IER(UART_PORT) = 0;
-	IT83XX_UART_IER(UART_PORT) = uart_ier;
-}
-
-static void intc_cpu_int_group_9(void)
-{
-	/* Determine interrupt number. */
-	int intc_group_9 = intc_get_ec_int();
-
-	switch (intc_group_9) {
-	case IT83XX_IRQ_UART1:
-		uart_ec_interrupt();
-		break;
-	default:
-		break;
-	}
-}
-DECLARE_IRQ(CPU_INT_GROUP_9, intc_cpu_int_group_9, 1);
-
-static void uart_config(void)
-{
-	/*
-	 * Specify clock source of the UART is 24MHz,
-	 * must match CLK_UART_DIV_SEL.
-	 */
-	IT83XX_UART_CSSR(UART_PORT) = 0x01;
-
-	/* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */
-	IT83XX_UART_LCR(UART_PORT) = 0x83;
-
-	/* Set divisor to set baud rate to 115200 */
-	IT83XX_UART_DLM(UART_PORT) = 0x00;
-	IT83XX_UART_DLL(UART_PORT) = 0x01;
-
-	/*
-	 * Clear DLAB bit to exclude access to DLL and DLM and give access to
-	 * RBR and THR.
-	 */
-	IT83XX_UART_LCR(UART_PORT) = 0x03;
-
-	/*
-	 * Enable TX and RX FIFOs and set RX FIFO interrupt level to the
-	 * minimum 1 byte.
-	 */
-	IT83XX_UART_FCR(UART_PORT) = 0x07;
-
-	/*
-	 * set OUT2 bit to enable interrupt logic.
-	 */
-	IT83XX_UART_MCR(UART_PORT) = 0x08;
-}
-
-#ifdef CONFIG_UART_HOST
-static void host_uart_config(void)
-{
-	/*
-	 * Specify clock source of the UART is 24MHz,
-	 * must match CLK_UART_DIV_SEL.
-	 */
-	IT83XX_UART_CSSR(UART_PORT_HOST) = 0x01;
-	/* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */
-	IT83XX_UART_LCR(UART_PORT_HOST) = 0x83;
-	/* Set divisor to set baud rate to 115200 */
-	IT83XX_UART_DLM(UART_PORT_HOST) = 0x00;
-	IT83XX_UART_DLL(UART_PORT_HOST) = 0x01;
-	/*
-	 * Clear DLAB bit to exclude access to DLL and DLM and give access to
-	 * RBR and THR.
-	 */
-	IT83XX_UART_LCR(UART_PORT_HOST) = 0x03;
-	/*
-	 * Enable TX and RX FIFOs and set RX FIFO interrupt level to the
-	 * minimum 1 byte.
-	 */
-	IT83XX_UART_FCR(UART_PORT_HOST) = 0x07;
-}
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	gpio_clear_pending_interrupt(GPIO_UART1_RX);
-	gpio_enable_interrupt(GPIO_UART1_RX);
-}
-
-void uart_exit_dsleep(void)
-{
-	gpio_disable_interrupt(GPIO_UART1_RX);
-	gpio_clear_pending_interrupt(GPIO_UART1_RX);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	clock_refresh_console_in_use();
-	/* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART1_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-void uart_init(void)
-{
-	/*
-	 * bit3: uart1 belongs to the EC side.
-	 * This is necessary for enabling eSPI module.
-	 */
-	IT83XX_GCTRL_RSTDMMC |= BIT(3);
-
-	/* reset uart before config it */
-	IT83XX_GCTRL_RSTC4 |= BIT(1);
-
-	/* Waiting for when we can use the GPIO module to set pin muxing */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* switch UART1 on without hardware flow control */
-	IT83XX_GPIO_GRC1 |= 0x01;
-	IT83XX_GPIO_GRC6 |= 0x03;
-
-	/* Enable clocks to UART 1 and 2. */
-	clock_enable_peripheral(CGC_OFFSET_UART, 0, 0);
-
-	/* Config UART 1 */
-	uart_config();
-
-#ifdef CONFIG_UART_HOST
-	/* bit2, reset UART2 */
-	IT83XX_GCTRL_RSTC4 |= BIT(2);
-	/* SIN1/SOUT1 of UART 2 is enabled. */
-	IT83XX_GPIO_GRC1 |= BIT(2);
-	/* Config UART 2 */
-	host_uart_config();
-#endif
-
-	/* clear interrupt status */
-	task_clear_pending_irq(IT83XX_IRQ_UART1);
-
-	/* Enable interrupts */
-	IT83XX_UART_IER(UART_PORT) = 0x03;
-	task_enable_irq(IT83XX_IRQ_UART1);
-
-	init_done = 1;
-}
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c
deleted file mode 100644
index f0e200c4ac..0000000000
--- a/chip/it83xx/watchdog.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer_chip.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-
-/* Enter critical period or not. */
-static int wdt_warning_fired;
-
-/*
- * We use WDT_EXT_TIMER to trigger an interrupt just before the watchdog timer
- * will fire so that we can capture important state information before
- * being reset.
- */
-
-/* Magic value to tickle the watchdog register. */
-#define ITE83XX_WATCHDOG_MAGIC_WORD  0x5C
-/* Start to print warning message. */
-#define ITE83XX_WATCHDOG_WARNING_MS  CONFIG_AUX_TIMER_PERIOD_MS
-/* The interval to print warning message at critical period. */
-#define ITE83XX_WATCHDOG_CRITICAL_MS 30
-
-/* set warning timer */
-static void watchdog_set_warning_timer(int32_t ms, int init)
-{
-	ext_timer_ms(WDT_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, ms, init, 0);
-}
-
-void watchdog_warning_irq(void)
-{
-#ifdef CONFIG_SOFTWARE_PANIC
-	struct panic_data * const pdata_ptr = get_panic_data_write();
-
-#if defined(CHIP_CORE_NDS32)
-	pdata_ptr->nds_n8.ipc = get_ipc();
-#elif defined(CHIP_CORE_RISCV)
-	pdata_ptr->riscv.mepc = get_mepc();
-#endif
-#endif
-	/* clear interrupt status */
-	task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq);
-
-	/* Reset warning timer. */
-	IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
-
-#if defined(CHIP_CORE_NDS32)
-	/*
-	 * The IPC (Interruption Program Counter) is the shadow stack register
-	 * of the PC (Program Counter). It stores the return address of program
-	 * (PC->IPC) when the ISR was called.
-	 *
-	 * The LP (Link Pointer) stores the program address of the next
-	 * sequential instruction for function call return purposes.
-	 * LP = PC+4 after a jump and link instruction (jal).
-	 */
-	panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n",
-		get_ipc(), ilp, task_get_current());
-#elif defined(CHIP_CORE_RISCV)
-	panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n",
-		get_mepc(), ira, task_get_current());
-#endif
-
-	if (!wdt_warning_fired++)
-		/*
-		 * Reduce interval of warning timer, so we can print more
-		 * warning messages during critical period.
-		 */
-		watchdog_set_warning_timer(ITE83XX_WATCHDOG_CRITICAL_MS, 0);
-}
-
-void watchdog_reload(void)
-{
-	/* Reset warning timer. */
-	IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03;
-
-	/* Restart (tickle) watchdog timer. */
-	IT83XX_ETWD_EWDKEYR = ITE83XX_WATCHDOG_MAGIC_WORD;
-
-	if (wdt_warning_fired) {
-		wdt_warning_fired = 0;
-		/* Reset warning timer to default if watchdog is touched. */
-		watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 0);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	uint16_t wdt_count = CONFIG_WATCHDOG_PERIOD_MS * 1024 / 1000;
-
-	/* Unlock access to watchdog registers. */
-	IT83XX_ETWD_ETWCFG = 0x00;
-
-	/* Set WD timer to use 1.024kHz clock. */
-	IT83XX_ETWD_ET1PSR = 0x01;
-
-	/* Set WDT key match enabled and WDT clock to use ET1PSR. */
-	IT83XX_ETWD_ETWCFG = 0x30;
-
-#ifdef CONFIG_HIBERNATE
-	/* bit4: watchdog can be stopped. */
-	IT83XX_ETWD_ETWCTRL |= BIT(4);
-#else
-	/* Specify that watchdog cannot be stopped. */
-	IT83XX_ETWD_ETWCTRL = 0x00;
-#endif
-
-	/* Start WDT_EXT_TIMER (CONFIG_AUX_TIMER_PERIOD_MS ms). */
-	watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 1);
-
-	/* Start timer 1 (must be started for watchdog timer to run). */
-	IT83XX_ETWD_ET1CNTLLR = 0x00;
-
-	/*
-	 * Set watchdog timer to CONFIG_WATCHDOG_PERIOD_MS ms.
-	 * Writing CNTLL starts timer.
-	 */
-	IT83XX_ETWD_EWDCNTLHR = (wdt_count >> 8) & 0xff;
-	IT83XX_ETWD_EWDCNTLLR = wdt_count & 0xff;
-
-	/* Lock access to watchdog registers. */
-	IT83XX_ETWD_ETWCFG = 0x3f;
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
deleted file mode 100644
index 13b5ebdebd..0000000000
--- a/chip/lm4/adc.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#include "adc.h"
-#include "atomic.h"
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US SECOND
-
-static volatile task_id_t task_waiting_on_ss[LM4_ADC_SEQ_COUNT];
-
-static void configure_gpio(void)
-{
-	int i, port, mask;
-
-	/* Use analog function for AIN */
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		if (adc_channels[i].gpio_mask) {
-			mask = adc_channels[i].gpio_mask;
-			port = adc_channels[i].gpio_port;
-			LM4_GPIO_DEN(port) &= ~mask;
-			LM4_GPIO_AMSEL(port) |= mask;
-		}
-	}
-}
-
-/**
- * Flush an ADC sequencer and initiate a read.
- *
- * @param seq		Sequencer to read
- * @return Raw ADC value.
- */
-static int flush_and_read(enum lm4_adc_sequencer seq)
-{
-	/*
-	 * This is currently simple because we can dedicate a sequencer to each
-	 * ADC channel.  If we have enough channels that's no longer possible,
-	 * this code will need to become more complex.  For example, we could:
-	 *
-	 * 1) Read them all using a timer interrupt, and then return the most
-	 * recent value?  This is lowest-latency for the caller, but won't
-	 * return accurate data if read frequently.
-	 *
-	 * 2) Reserve SS3 for reading a single value, and configure it on each
-	 * read?  Needs mutex if we could have multiple callers; doesn't matter
-	 * if just used for debugging.
-	 *
-	 * 3) Both?
-	 */
-	volatile uint32_t scratch  __attribute__((unused));
-	int event;
-
-	/* Empty the FIFO of any previous results */
-	while (!(LM4_ADC_SSFSTAT(seq) & 0x100))
-		scratch = LM4_ADC_SSFIFO(seq);
-
-	/*
-	 * This assumes we don't have multiple tasks accessing the same
-	 * sequencer. Add mutex lock if needed.
-	 */
-	task_waiting_on_ss[seq] = task_get_current();
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC |= 0x01 << seq;
-
-	/* Enable interrupt */
-	LM4_ADC_ADCIM |= 0x01 << seq;
-
-	/* Initiate sample sequence */
-	LM4_ADC_ADCPSSI |= 0x01 << seq;
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US);
-
-	/* Disable interrupt */
-	LM4_ADC_ADCIM &= ~(0x01 << seq);
-
-	task_waiting_on_ss[seq] = TASK_ID_INVALID;
-
-	if (!(event & TASK_EVENT_ADC_DONE))
-		return ADC_READ_ERROR;
-
-	/* Read the FIFO and convert to temperature */
-	return LM4_ADC_SSFIFO(seq);
-}
-
-/**
- * Configure an ADC sequencer to be dedicated for an ADC input.
- *
- * @param seq		Sequencer to configure
- * @param ain_id	ADC input to use
- * @param ssctl		Value for sampler sequencer control register
- *
- */
-static void adc_configure(const struct adc_t *adc)
-{
-	const enum lm4_adc_sequencer seq = adc->sequencer;
-
-	/* Configure sample sequencer */
-	LM4_ADC_ADCACTSS &= ~(0x01 << seq);
-
-	/* Trigger sequencer by processor request */
-	LM4_ADC_ADCEMUX = (LM4_ADC_ADCEMUX & ~(0xf << (seq * 4))) | 0x00;
-
-	/* Sample internal temp sensor */
-	if (adc->channel == LM4_AIN_NONE) {
-		LM4_ADC_SSMUX(seq) = 0x00;
-		LM4_ADC_SSEMUX(seq) = 0x00;
-	} else {
-		LM4_ADC_SSMUX(seq) = adc->channel & 0xf;
-		LM4_ADC_SSEMUX(seq) = adc->channel >> 4;
-	}
-	LM4_ADC_SSCTL(seq) = adc->flag;
-
-	/* Enable sample sequencer */
-	LM4_ADC_ADCACTSS |= 0x01 << seq;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	static uint32_t ch_busy_mask;
-	static struct mutex adc_clock;
-	int rv;
-
-	/*
-	 * TODO(crbug.com/314121): Generalize ADC reads such that any task can
-	 * trigger a read of any channel.
-	 */
-
-	/*
-	 * Enable ADC clock and set a bit in ch_busy_mask to signify that this
-	 * channel is busy. Note, this function may be called from multiple
-	 * tasks, but each channel may be read by only one task. If assert
-	 * fails, then it means multiple tasks are trying to read same channel.
-	 */
-	mutex_lock(&adc_clock);
-	ASSERT(!(ch_busy_mask & (1UL << ch)));
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	ch_busy_mask |= (1UL << ch);
-	mutex_unlock(&adc_clock);
-
-	rv = flush_and_read(adc->sequencer);
-
-	/*
-	 * If no ADC channels are busy, then disable ADC clock to conserve
-	 * power.
-	 */
-	mutex_lock(&adc_clock);
-	ch_busy_mask &= ~(1UL << ch);
-	if (!ch_busy_mask)
-		clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	mutex_unlock(&adc_clock);
-
-	if (rv == ADC_READ_ERROR)
-		return ADC_READ_ERROR;
-
-	return rv * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle an interrupt on the specified sample sequencer.
- */
-static void handle_interrupt(int ss)
-{
-	int id = task_waiting_on_ss[ss];
-
-	/* Clear the interrupt status */
-	LM4_ADC_ADCISC = (0x1 << ss);
-
-	/* Wake up the task which was waiting on the interrupt, if any */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_ADC_DONE);
-}
-
-void ss0_interrupt(void) { handle_interrupt(0); }
-void ss1_interrupt(void) { handle_interrupt(1); }
-void ss2_interrupt(void) { handle_interrupt(2); }
-void ss3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS2, ss2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_ADC0_SS3, ss3_interrupt, 2);
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_ECTEMP
-static int command_ectemp(int argc, char **argv)
-{
-	int t = adc_read_channel(ADC_CH_EC_TEMP);
-	ccprintf("EC temperature is %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ectemp, command_ectemp,
-			NULL,
-			"Print EC temperature");
-#endif
-
-/*****************************************************************************/
-/* Initialization */
-
-static void adc_init(void)
-{
-	int i;
-
-	/* Configure GPIOs */
-	configure_gpio();
-
-	/*
-	 * Temporarily enable the PLL when turning on the clock to the ADC
-	 * module, to work around chip errata (10.4).  No need to notify
-	 * other modules; the PLL isn't enabled long enough to matter.
-	 */
-	clock_enable_pll(1, 0);
-
-	/* Enable ADC0 module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/*
-	 * Use external voltage references (VREFA+, VREFA-) instead of
-	 * VDDA and GNDA.
-	 */
-	LM4_ADC_ADCCTL = 0x01;
-
-	/* Use internal oscillator */
-	LM4_ADC_ADCCC = 0x1;
-
-	/* Disable the PLL now that the ADC is using the internal oscillator */
-	clock_enable_pll(0, 0);
-
-	/* No tasks waiting yet */
-	for (i = 0; i < LM4_ADC_SEQ_COUNT; i++)
-		task_waiting_on_ss[i] = TASK_ID_INVALID;
-
-	/* Enable IRQs */
-	task_enable_irq(LM4_IRQ_ADC0_SS0);
-	task_enable_irq(LM4_IRQ_ADC0_SS1);
-	task_enable_irq(LM4_IRQ_ADC0_SS2);
-	task_enable_irq(LM4_IRQ_ADC0_SS3);
-
-	/* 2**6 = 64x oversampling */
-	LM4_ADC_ADCSAC = 6;
-
-	/* Initialize ADC sequencer */
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_configure(adc_channels + i);
-
-	/* Disable ADC0 module until it is needed to conserve power. */
-	clock_disable_peripheral(CGC_OFFSET_ADC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h
deleted file mode 100644
index a402c845a1..0000000000
--- a/chip/lm4/adc_chip.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include <stdint.h>
-
-enum lm4_adc_sequencer {
-	LM4_ADC_SEQ0 = 0,
-	LM4_ADC_SEQ1,
-	LM4_ADC_SEQ2,
-	LM4_ADC_SEQ3,
-	LM4_ADC_SEQ_COUNT
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	enum lm4_adc_sequencer sequencer;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-	int flag;
-	uint32_t gpio_port;
-	uint8_t gpio_mask;
-};
-
-/* Minimum and maximum values returned by raw ADC read. */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 4095
-
-/* Just plain id mapping for code readability */
-#define LM4_AIN(x) (x)
-
-/* Mock value for "channel" in adc_t if we don't have an external channel. */
-#define LM4_AIN_NONE (-1)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
deleted file mode 100644
index 26419d3a04..0000000000
--- a/chip/lm4/build.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# LM4 chip specific files build
-#
-
-# LM4 SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o
-
-# Optional chip modules
-chip-$(CONFIG_ADC)+=adc.o chip_temp_sensor.o
-chip-$(CONFIG_EEPROM)+=eeprom.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PECI)+=peci.o
-# pwm functions are implemented with the fan functions
-chip-$(CONFIG_PWM)+=pwm.o fan.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/lm4/chip_temp_sensor.c b/chip/lm4/chip_temp_sensor.c
deleted file mode 100644
index 93b66f5f3f..0000000000
--- a/chip/lm4/chip_temp_sensor.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for Chrome EC */
-
-#include "adc.h"
-#include "common.h"
-#include "hooks.h"
-
-/* Initialize temperature reading to a valid value (27 C) */
-static int last_val = C_TO_K(27);
-
-static void chip_temp_sensor_poll(void)
-{
-	last_val = adc_read_channel(ADC_CH_EC_TEMP);
-}
-DECLARE_HOOK(HOOK_SECOND, chip_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-int chip_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	if (last_val == ADC_READ_ERROR)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = last_val;
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c
deleted file mode 100644
index 39800c9034..0000000000
--- a/chip/lm4/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define PLL_CLOCK 66666667  /* System clock = 200MHz PLL/3 = 66.667MHz */
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-/*
- * Length of time for the processor to wake up from deep sleep. Actual
- * measurement gives anywhere up to 780us, depending on the mode it is coming
- * out of. The datasheet gives a maximum of 846us, for coming out of deep
- * sleep in our worst case deep sleep mode.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 850
-#else
-/*
- * Length of time for the processor to wake up from deep sleep. Datasheet
- * maximum is 145us, but in practice have seen as much as 336us.
- */
-#define DEEP_SLEEP_RECOVER_TIME_USEC 400
-#endif
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif
-
-static int freq;
-
-/**
- * Disable the PLL; run off internal oscillator.
- */
-static void disable_pll(void)
-{
-	/* Switch to 16MHz internal oscillator and power down the PLL */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(0) |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_PWRDN |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	LM4_SYSTEM_RCC2 &= ~LM4_SYSTEM_RCC2_USERCC2;
-
-	freq = INTERNAL_CLOCK;
-}
-
-/**
- * Enable the PLL to run at full clock speed.
- */
-static void enable_pll(void)
-{
-	/* Disable the PLL so we can reconfigure it */
-	disable_pll();
-
-	/*
-	 * Enable the PLL (PWRDN is no longer set) and set divider.  PLL is
-	 * still bypassed, since it hasn't locked yet.
-	 */
-	LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(2) |
-		LM4_SYSTEM_RCC_USESYSDIV |
-		LM4_SYSTEM_RCC_BYPASS |
-		LM4_SYSTEM_RCC_OSCSRC(1) |
-		LM4_SYSTEM_RCC_MOSCDIS;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * If using the low power idle, then set the ACG bit, which specifies
-	 * that the sleep and deep sleep modes are using their own clock gating
-	 * registers SCGC and DCGS respectively instead of using the run mode
-	 * clock gating registers RCGC.
-	 */
-	LM4_SYSTEM_RCC |= LM4_SYSTEM_RCC_ACG;
-#endif
-
-	/* Wait for the PLL to lock */
-	clock_wait_cycles(1024);
-	while (!(LM4_SYSTEM_PLLSTAT & 1))
-		;
-
-	/* Remove bypass on PLL */
-	LM4_SYSTEM_RCC &= ~LM4_SYSTEM_RCC_BYPASS;
-	freq = PLL_CLOCK;
-}
-
-void clock_enable_pll(int enable, int notify)
-{
-	if (enable)
-		enable_pll();
-	else
-		disable_pll();
-
-	/* Notify modules of frequency change */
-	if (notify)
-		hook_notify(HOOK_FREQ_CHANGE);
-}
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef BOARD_BDS
-	/*
-	 * Perform an auto calibration of the internal oscillator using the
-	 * 32.768KHz hibernate clock, unless we've already done so.  This is
-	 * only necessary on A2 silicon as on BDS; A3 silicon is all
-	 * factory-trimmed.
-	 */
-	if ((LM4_SYSTEM_PIOSCSTAT & 0x300) != 0x100) {
-		/* Start calibration */
-		LM4_SYSTEM_PIOSCCAL = 0x80000000;
-		LM4_SYSTEM_PIOSCCAL = 0x80000200;
-		/* Wait for result */
-		clock_wait_cycles(16);
-		while (!(LM4_SYSTEM_PIOSCSTAT & 0x300))
-			;
-	}
-#else
-	/*
-	 * Only BDS has an external crystal; other boards don't have one, and
-	 * can disable main oscillator control to reduce power consumption.
-	 */
-	LM4_SYSTEM_MOSCCTL = 0x04;
-#endif
-
-	/* Make sure PLL is disabled */
-	disable_pll();
-}
-
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) |= mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) |= mask;
-
-	/* Wait for clock change to take affect. */
-	clock_wait_cycles(3);
-}
-
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	if (mode & CGC_MODE_RUN)
-		*(LM4_SYSTEM_RCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_SLEEP)
-		*(LM4_SYSTEM_SCGC_BASE + offset) &= ~mask;
-
-	if (mode & CGC_MODE_DSLEEP)
-		*(LM4_SYSTEM_DCGC_BASE + offset) &= ~mask;
-}
-
-/*
- * The low power idle task does not support using the EEPROM,
- * because it is dangerous to go to deep sleep while EEPROM
- * transaction is in progress. To fix, LM4_EEPROM_EEDONE, should
- * be checked before going in to deep sleep.
- */
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_EEPROM)
-#error "Low power idle mode does not support use of EEPROM"
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-
-}
-
-/* Low power idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	timestamp_t t0, t1, rtc_t0, rtc_t1;
-	int next_delay = 0;
-	int time_for_dsleep, margin_us;
-	int use_low_speed_clock;
-
-	/* Enable the hibernate IRQ used to wake up from deep sleep */
-	system_enable_hib_interrupt();
-
-	/* Set SRAM and flash power management to 'low power' in deep sleep. */
-	LM4_SYSTEM_DSLPPWRCFG = 0x23;
-
-	/* Enable JTAG interrupt which will notify us when JTAG is in use. */
-	gpio_enable_interrupt(GPIO_JTAG_TCK);
-
-	/*
-	 * Initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot in which the low speed
-	 * clock will not be used in idle.
-	 */
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/*
-		 * Disable interrupts before going to deep sleep in order to
-		 * calculate the appropriate time to wake up. Note: the wfi
-		 * instruction waits until an interrupt is pending, so it
-		 * will still wake up even with interrupts disabled.
-		 */
-		interrupt_disable();
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		/* Do we have enough time before next event to deep sleep. */
-		time_for_dsleep = next_delay > (DEEP_SLEEP_RECOVER_TIME_USEC +
-						HIB_SET_RTC_MATCH_DELAY_USEC);
-
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			/* Deep-sleep in STOP mode. */
-			idle_dsleep_cnt++;
-
-			/* Check if the console use has expired. */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* Enable low speed deep sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if low speed
-				 * deep sleep is allowed to give time for
-				 * sleep mask to update.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disabling console in "
-						"deep sleep");
-			}
-
-			/*
-			 * Determine if we should use a lower clock speed or
-			 * keep the same (16MHz) clock in deep sleep. Use the
-			 * lower speed only if the sleep mask specifies that low
-			 * speed sleep is allowed, the console UART TX is not
-			 * busy, and the console UART buffer is empty.
-			 */
-			use_low_speed_clock = LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-				!uart_tx_in_progress() && uart_buffer_empty();
-
-#ifdef CONFIG_LOW_POWER_USE_LFIOSC
-			/* Set the deep sleep clock register. Use either the
-			 *  normal PIOSC (16MHz) or the LFIOSC (32kHz). */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x32 : 0x10;
-#else
-			/*
-			 * Set the deep sleep clock register. Use either the
-			 * PIOSC with no divider (16MHz) or the PIOSC with
-			 * a /64 divider (250kHz).
-			 */
-			LM4_SYSTEM_DSLPCLKCFG = use_low_speed_clock ?
-					0x1f800010 : 0x10;
-#endif
-
-			/*
-			 * If using low speed clock, disable console.
-			 * This will also convert the console RX pin to a GPIO
-			 * and set an edge interrupt to wake us from deep sleep
-			 * if any action occurs on console.
-			 */
-			if (use_low_speed_clock)
-				uart_enter_dsleep();
-
-			/* Set deep sleep bit. */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			/* Record real time before sleeping. */
-			rtc_t0 = system_get_rtc();
-
-			/*
-			 * Set RTC interrupt in time to wake up before
-			 * next event.
-			 */
-			system_set_rtc_alarm(0, next_delay -
-						DEEP_SLEEP_RECOVER_TIME_USEC);
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			/* Clear deep sleep bit. */
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* Disable and clear RTC interrupt. */
-			system_reset_rtc_alarm();
-
-			/* Fast forward timer according to RTC counter. */
-			rtc_t1 = system_get_rtc();
-			t1.val = t0.val + (rtc_t1.val - rtc_t0.val);
-			force_time(t1);
-
-			/* If using low speed clock, re-enable the console. */
-			if (use_low_speed_clock)
-				uart_exit_dsleep();
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += (rtc_t1.val - rtc_t0.val);
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - (int)(rtc_t1.val - rtc_t0.val);
-			if (margin_us < 0)
-				CPRINTS("overslept by %dus", -margin_us);
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped. */
-			asm("wfi");
-		}
-		interrupt_enable();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_SLEEP
-/**
- * Measure baseline for power consumption.
- *
- * Levels :
- *   0 : CPU running in tight loop
- *   1 : CPU running in tight loop but peripherals gated
- *   2 : CPU in sleep mode
- *   3 : CPU in sleep mode and peripherals gated
- *   4 : CPU in deep sleep mode
- *   5 : CPU in deep sleep mode and peripherals gated
- *
- * Clocks :
- *   0 : No change
- *   1 : 16MHz
- *   2 : 1 MHz
- *   3 : 30kHz
- *
- * SRAM Power Management:
- *   0 : Active
- *   1 : Standby
- *   3 : Low Power
- *
- * Flash Power Management:
- *   0 : Active
- *   2 : Low Power
- */
-static int command_sleep(int argc, char **argv)
-{
-	int level = 0;
-	int clock = 0;
-	int sram_pm = 0;
-	int flash_pm = 0;
-	uint32_t uartibrd = 0;
-	uint32_t uartfbrd = 0;
-
-	if (argc >= 2)
-		level = strtoi(argv[1], NULL, 10);
-	if (argc >= 3)
-		clock = strtoi(argv[2], NULL, 10);
-	if (argc >= 4)
-		sram_pm = strtoi(argv[3], NULL, 10);
-	if (argc >= 5)
-		flash_pm = strtoi(argv[4], NULL, 10);
-
-#ifdef BOARD_BDS
-	/* Remove LED current sink. */
-	gpio_set_level(GPIO_DEBUG_LED, 0);
-#endif
-
-	ccprintf("Sleep : level %d, clock %d, sram pm %d, flash_pm %d...\n",
-			level, clock, sram_pm, flash_pm);
-	cflush();
-
-	/* Set clock speed. */
-	if (clock) {
-		/* Use ROM code function to set the clock */
-		void **func_table = (void **)*(uint32_t *)0x01000044;
-		void (*rom_clock_set)(uint32_t rcc) = func_table[23];
-
-		/* Disable interrupts. */
-		asm volatile("cpsid i");
-
-		switch (clock) {
-		case 1: /* 16MHz IOSC */
-			uartibrd = 17;
-			uartfbrd = 23;
-			rom_clock_set(0x00000d51);
-			break;
-		case 2: /* 1MHz IOSC */
-			uartibrd = 1;
-			uartfbrd = 5;
-			rom_clock_set(0x07C00d51);
-			break;
-		case 3: /* 30 kHz */
-			uartibrd = 0;
-			uartfbrd = 0;
-			rom_clock_set(0x00000d71);
-			break;
-		}
-
-		/*
-		 * TODO(crosbug.com/p/23795): move this to the UART module;
-		 * ugly to have UARTisms here.  Also note this only fixes
-		 * UART0, not UART1.  Should just be able to trigger
-		 * HOOK_FREQ_CHANGE and have that take care of it.
-		 */
-		if (uartfbrd) {
-			/* Disable the port via UARTCTL and add HSE. */
-			LM4_UART_CTL(0) = 0x0320;
-			/* Set the baud rate divisor. */
-			LM4_UART_IBRD(0) = uartibrd;
-			LM4_UART_FBRD(0) = uartfbrd;
-			/* Poke UARTLCRH to make the new divisor take effect. */
-			LM4_UART_LCRH(0) = LM4_UART_LCRH(0);
-			/* Enable the port. */
-			LM4_UART_CTL(0) |= 0x0001;
-		}
-		asm volatile("cpsie i");
-	}
-
-	if (uartfbrd) {
-		ccprintf("We are still alive. RCC=%08x\n", LM4_SYSTEM_RCC);
-		cflush();
-	}
-
-	/* Enable interrupts. */
-	asm volatile("cpsid i");
-
-	/* gate peripheral clocks */
-	if (level & 1) {
-		clock_disable_peripheral(CGC_OFFSET_WD,     0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_TIMER,  0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_GPIO,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_DMA,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_HIB,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_UART,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_SSI,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_I2C,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_ADC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_LPC,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_PECI,   0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_FAN,    0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_EEPROM, 0xffffffff,
-				CGC_MODE_ALL);
-		clock_disable_peripheral(CGC_OFFSET_WTIMER, 0xffffffff,
-				CGC_MODE_ALL);
-	}
-
-	/* Set deep sleep bit. */
-	if (level >= 4)
-		CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Set SRAM and flash PM for sleep and deep sleep. */
-	LM4_SYSTEM_SLPPWRCFG = (flash_pm << 4) | sram_pm;
-	LM4_SYSTEM_DSLPPWRCFG = (flash_pm << 4) | sram_pm;
-
-	/* Go to low power mode (forever ...) */
-	if (level > 1)
-		while (1) {
-			asm("wfi");
-			watchdog_reload();
-		}
-	else
-		while (1)
-			watchdog_reload();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sleep, command_sleep,
-			"[level [clock] [sram pm] [flash pm]]",
-			"Drop into sleep");
-#endif /* CONFIG_CMD_SLEEP */
-
-#ifdef CONFIG_CMD_PLL
-
-static int command_pll(int argc, char **argv)
-{
-	int v;
-
-	/* Toggle the PLL */
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			clock_enable_pll(v, 1);
-		} else {
-			/* Disable PLL and set extra divider */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			LM4_SYSTEM_RCC = LM4_SYSTEM_RCC_SYSDIV(v - 1) |
-				LM4_SYSTEM_RCC_BYPASS |
-				LM4_SYSTEM_RCC_PWRDN |
-				LM4_SYSTEM_RCC_OSCSRC(1) |
-				LM4_SYSTEM_RCC_MOSCDIS;
-
-			freq = INTERNAL_CLOCK / v;
-
-			/* Notify modules of frequency change */
-			hook_notify(HOOK_FREQ_CHANGE);
-		}
-	}
-
-	/* Print current PLL state */
-	ccprintf("RCC:     0x%08x\n", LM4_SYSTEM_RCC);
-	ccprintf("RCC2:    0x%08x\n", LM4_SYSTEM_RCC2);
-	ccprintf("PLLSTAT: 0x%08x\n", LM4_SYSTEM_PLLSTAT);
-	ccprintf("Clock:   %d Hz\n", clock_get_freq());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pll, command_pll,
-			"[ on | off | <div> ]",
-			"Get/set PLL state");
-
-#endif /* CONFIG_CMD_PLL */
-
-#ifdef CONFIG_CMD_CLOCKGATES
-/**
- * Print all clock gating registers
- */
-static int command_clock_gating(int argc, char **argv)
-{
-	ccprintf("         Run       , Sleep     , Deep Sleep\n");
-
-	ccprintf("WD:      0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WD));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WD));
-
-	ccprintf("TIMER:   0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_TIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_TIMER));
-
-	ccprintf("GPIO:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_GPIO));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_GPIO));
-
-	ccprintf("DMA:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_DMA));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_DMA));
-
-	ccprintf("HIB:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_HIB));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_HIB));
-
-	ccprintf("UART:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_UART));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_UART));
-
-	ccprintf("SSI:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_SSI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_SSI));
-
-	ccprintf("I2C:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_I2C));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_I2C));
-
-	ccprintf("ADC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_ADC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_ADC));
-
-	ccprintf("LPC:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_LPC));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_LPC));
-
-	ccprintf("PECI:    0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_PECI));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_PECI));
-
-	ccprintf("FAN:     0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_FAN));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_FAN));
-
-	ccprintf("EEPROM:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_EEPROM));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_EEPROM));
-
-	ccprintf("WTIMER:  0x%08x, ",
-				*(LM4_SYSTEM_RCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x, ",	*(LM4_SYSTEM_SCGC_BASE + CGC_OFFSET_WTIMER));
-	ccprintf("0x%08x\n",	*(LM4_SYSTEM_DCGC_BASE + CGC_OFFSET_WTIMER));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clockgates, command_clock_gating,
-			"",
-			"Get state of the clock gating controls regs");
-#endif /* CONFIG_CMD_CLOCKGATES */
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use low speed clock or
-			 * allow it to use the low speed clock.
-			 */
-			if (v)
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-	ccprintf("DSLPCLKCFG register:      0x%08x\n", LM4_SYSTEM_DSLPCLKCFG);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep not to use low speed clock.\nUse 'off' to "
-			"allow deep sleep to auto-select using the low speed "
-			"clock.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
-
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
deleted file mode 100644
index 4e442004c9..0000000000
--- a/chip/lm4/config_chip.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* 16.000 MHz internal oscillator frequency (PIOSC) */
-#define INTERNAL_CLOCK 16000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 132
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 6
-
-/*
- * Time it takes to set the RTC match register. This value is conservatively
- * set based on measurements around 200us.
- */
-#define HIB_SET_RTC_MATCH_DELAY_USEC 300
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CONFIG_RAM_BASE             0x20000000
-#define CONFIG_RAM_SIZE             0x00008000
-
-/* System stack size */
-#define CONFIG_STACK_SIZE           4096
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE        512
-#define LARGER_TASK_STACK_SIZE      768
-#define SMALLER_TASK_STACK_SIZE     384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE             512
-
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
-
-/* Ideal flash write size fills the 32-entry flash write buffer */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
-
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* Lock the boot configuration to prevent brickage. */
-
-/*
- * No GPIO trigger for ROM bootloader.
- * Keep JTAG debugging enabled.
- * Use 0xA442 flash write key.
- * Lock it this way.
- */
-#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
-
-/****************************************************************************/
-/* Customize the build */
-
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_PECI
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-#define CONFIG_MPU
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/lm4/eeprom.c b/chip/lm4/eeprom.c
deleted file mode 100644
index 97fd3bdc24..0000000000
--- a/chip/lm4/eeprom.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EEPROM module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "eeprom.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Size of EEPROM block in bytes */
-#define EEPROM_BLOCK_SIZE 64
-
-/* Count of EEPROM blocks */
-static int block_count;
-
-/*
- * Wait for the current EEPROM operation to finish; all operations but write
- * should normally finish in 4 system clocks, but worst case is up to
- * 1800ms if the EEPROM needs to do an internal page erase/copy.  We must
- * spin-wait for this delay, because EEPROM operations will fail if the chip
- * drops to sleep mode.
- */
-static int wait_for_done(void)
-{
-	int j;
-
-	for (j = 0; j < 20; j++) {  /* 20 * 100 ms = 2000 ms */
-		uint64_t tstop = get_time().val + 100 * MSEC;
-		while (get_time().val < tstop) {
-			if (!(LM4_EEPROM_EEDONE & 0x01))
-				return EC_SUCCESS;
-		}
-		watchdog_reload();
-	}
-
-	return EC_ERROR_UNKNOWN;
-}
-
-
-int eeprom_get_block_count(void)
-{
-	return block_count;
-}
-
-
-int eeprom_get_block_size(void)
-{
-	return EEPROM_BLOCK_SIZE;
-}
-
-
-int eeprom_read(int block, int offset, int size, char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	for (; size; size -= sizeof(uint32_t))
-		*(d++) = LM4_EEPROM_EERDWRINC;
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_write(int block, int offset, int size, const char *data)
-{
-	uint32_t *d = (uint32_t *)data;
-	int rv;
-
-	if (block < 0 || block >= block_count ||
-	    offset < 0 || offset > EEPROM_BLOCK_SIZE || offset & 3 ||
-	    size < 0 || offset + size > EEPROM_BLOCK_SIZE || size & 3)
-		return EC_ERROR_UNKNOWN;
-
-	rv = wait_for_done();
-	if (rv)
-		return rv;
-
-	LM4_EEPROM_EEBLOCK = block;
-	if (LM4_EEPROM_EEBLOCK != block)
-		return EC_ERROR_UNKNOWN;  /* Error setting block */
-
-	LM4_EEPROM_EEOFFSET = offset >> 2;
-
-	/* Write 32 bits at a time; wait for each write to complete */
-	for (; size; size -= sizeof(uint32_t)) {
-		LM4_EEPROM_EERDWRINC = *(d++);
-
-		rv = wait_for_done();
-		if (rv)
-			return rv;
-
-		if (LM4_EEPROM_EEDONE & 0x10) {
-			/* Failed due to write protect */
-			return EC_ERROR_ACCESS_DENIED;
-		} else if (LM4_EEPROM_EEDONE & 0x100) {
-			/* Failed due to program voltage level */
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int eeprom_hide(int block)
-{
-	/* Block 0 can't be hidden */
-	if (block <= 0 || block >= block_count)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_EEPROM_EEHIDE |= 1 << block;
-	return EC_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_eeprom_info(int argc, char **argv)
-{
-	ccprintf("%d blocks @ %d bytes, hide=0x%08x\n",
-		 eeprom_get_block_count(), eeprom_get_block_size(),
-		 LM4_EEPROM_EEHIDE);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(eeinfo, command_eeprom_info,
-			NULL,
-			"Print EEPROM info");
-
-
-static int command_eeprom_read(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	int rv;
-	uint32_t d;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		offset = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	rv = eeprom_read(block, offset, sizeof(d), (char *)&d);
-	if (rv == EC_SUCCESS)
-		ccprintf("%d:%d = 0x%08x\n", block, offset, d);
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(eeread, command_eeprom_read,
-			"block [offset]",
-			"Read a word of EEPROM");
-
-
-static int command_eeprom_write(int argc, char **argv)
-{
-	int block = 0;
-	int offset = 0;
-	char *e;
-	uint32_t d;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-	offset = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	d = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	ccprintf("Writing 0x%08x to %d:%d...\n", d, block, offset);
-	return eeprom_write(block, offset, sizeof(d), (char *)&d);
-}
-DECLARE_CONSOLE_COMMAND(eewrite, command_eeprom_write,
-			"block offset value",
-			"Write a word of EEPROM");
-
-
-#ifdef CONSOLE_COMMAND_EEHIDE
-static int command_eeprom_hide(int argc, char **argv)
-{
-	int block = 0;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	block = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	ccprintf("Hiding block %d\n", block);
-	return eeprom_hide(block);
-}
-DECLARE_CONSOLE_COMMAND(eehide, command_eeprom_hide,
-			"block",
-			"Hide a block of EEPROM");
-#endif
-
-
-/*****************************************************************************/
-/* Initialization */
-
-
-int eeprom_init(void)
-{
-	/* Enable the EEPROM module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_EEPROM, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Wait for internal EEPROM init to finish */
-	wait_for_done();
-
-	/* Store block count */
-	block_count = LM4_EEPROM_EESIZE >> 16;
-
-	/*
-	 * Handle resetting the EEPROM module to clear state from a previous
-	 * error condition.
-	 */
-	if (LM4_EEPROM_EESUPP & 0xc0) {
-		LM4_SYSTEM_SREEPROM = 1;
-		clock_wait_cycles(200);
-		LM4_SYSTEM_SREEPROM = 0;
-
-		/* Wait again for internal init to finish */
-		clock_wait_cycles(6);
-		wait_for_done();
-
-		/* Fail if error condition didn't clear */
-		if (LM4_EEPROM_EESUPP & 0xc0)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/lm4/fan.c b/chip/lm4/fan.c
deleted file mode 100644
index b09323a37b..0000000000
--- a/chip/lm4/fan.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4 fan control module. */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum RPM for fan controller */
-#define MAX_RPM 0x1fff
-
-/* Maximum PWM for PWM controller */
-#define MAX_PWM 0x1ff
-
-/*
- * Scaling factor for requested/actual RPM for CPU fan.  We need this because
- * the fan controller on Blizzard filters tach pulses that are less than 64
- * 15625Hz ticks apart, which works out to ~7000rpm on an unscaled fan.  By
- * telling the controller we actually have twice as many edges per revolution,
- * the controller can handle fans that actually go twice as fast.  See
- * crosbug.com/p/7718.
- */
-#define RPM_SCALE 2
-
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (enabled)
-		LM4_FAN_FANCTL |= BIT(ch);
-	else
-		LM4_FAN_FANCTL &= ~BIT(ch);
-}
-
-int fan_get_enabled(int ch)
-{
-	return (LM4_FAN_FANCTL & BIT(ch)) ? 1 : 0;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	int duty;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty = (MAX_PWM * percent + 50) / 100;
-
-	/* Always enable the channel */
-	fan_set_enabled(ch, 1);
-
-	/* Set the duty cycle */
-	LM4_FAN_FANCMD(ch) = duty << 16;
-}
-
-int fan_get_duty(int ch)
-{
-	return ((LM4_FAN_FANCMD(ch) >> 16) * 100 + MAX_PWM / 2) / MAX_PWM;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return (LM4_FAN_FANCH(ch) & 0x0001) ? 0 : 1;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	int was_enabled = fan_get_enabled(ch);
-	int was_rpm = fan_get_rpm_mode(ch);
-
-	if (!was_rpm && rpm_mode) {
-		/* Enable RPM control */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) &= ~0x0001;
-		fan_set_enabled(ch, was_enabled);
-	} else if (was_rpm && !rpm_mode) {
-		/* Disable RPM mode */
-		fan_set_enabled(ch, 0);
-		LM4_FAN_FANCH(ch) |= 0x0001;
-		fan_set_enabled(ch, was_enabled);
-	}
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	return (LM4_FAN_FANCST(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return (LM4_FAN_FANCMD(ch) & MAX_RPM) * RPM_SCALE;
-}
-
-test_mockable void fan_set_rpm_target(int ch, int rpm)
-{
-	/* Apply fan scaling */
-	if (rpm > 0)
-		rpm /= RPM_SCALE;
-
-	/* Treat out-of-range requests as requests for maximum fan speed */
-	if (rpm < 0 || rpm > MAX_RPM)
-		rpm = MAX_RPM;
-
-	LM4_FAN_FANCMD(ch) = rpm;
-}
-
-/* The LM4 status is the original definition of enum fan_status */
-enum fan_status fan_get_status(int ch)
-{
-	return (LM4_FAN_FANSTS >> (2 * ch)) & 0x03;
-}
-
-/**
- * Return non-zero if fan is enabled but stalled.
- */
-int fan_is_stalled(int ch)
-{
-	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0)
-		return 0;
-
-	/* Check for stall condition */
-	return fan_get_status(ch) == FAN_STATUS_STOPPED;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	uint32_t init;
-
-	if (flags & FAN_USE_RPM_MODE)
-		/*
-		 * Configure automatic/feedback mode:
-		 * 0x8000 = bit 15     = auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0020 = bits 5:4   = average 4 edges when
-		 *                       calculating RPM
-		 * 0x000c = bits 3:2   = 8 pulses per revolution
-		 *                       (see note at top of file)
-		 * 0x0000 = bit 0      = automatic control
-		 */
-		init = 0x802c;
-	else
-		/*
-		 * Configure drive-only mode:
-		 * 0x0000 = bit 15     = no auto-restart
-		 * 0x0000 = bit 14     = slow acceleration
-		 * 0x0000 = bits 13:11 = no hysteresis
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0000 = bits 7:6   = no fast start
-		 * 0x0000 = bits 5:4   = no RPM averaging
-		 * 0x0000 = bits 3:2   = 1 pulses per revolution
-		 * 0x0001 = bit 0      = manual control
-		 */
-		init = 0x0001;
-
-	if (flags & FAN_USE_FAST_START)
-		/*
-		 * Configure fast-start mode
-		 * 0x0000 = bits 10:8  = start period (2<<0) edges
-		 * 0x0040 = bits 7:6   = fast start at 50% duty
-		 */
-		init |= 0x0040;
-
-	LM4_FAN_FANCH(ch) = init;
-}
-
-static void fan_init(void)
-{
-
-#ifdef CONFIG_FAN_DSLEEP
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1, CGC_MODE_ALL);
-#else
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#endif
-	/* Disable all fans */
-	LM4_FAN_FANCTL = 0;
-}
-/* Init before PWM */
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c
deleted file mode 100644
index 5b61874984..0000000000
--- a/chip/lm4/flash.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "flash.h"
-#include "registers.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define FLASH_FWB_WORDS 32
-#define FLASH_FWB_BYTES (FLASH_FWB_WORDS * 4)
-
-#define BANK_SHIFT 5 /* bank registers have 32bits each, 2^32 */
-#define BANK_MASK (BIT(BANK_SHIFT) - 1) /* 5 bits */
-#define F_BANK(b) ((b) >> BANK_SHIFT)
-#define F_BIT(b) (1 << ((b) & BANK_MASK))
-
-/* Flash timeouts.  These are 2x the spec sheet max. */
-#define ERASE_TIMEOUT_MS 200
-#define WRITE_TIMEOUT_US 300
-
-int stuck_locked;  /* Is physical flash stuck protected? */
-int all_protected; /* Has all-flash protection been requested? */
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void protect_banks(int start_bank, int bank_count)
-{
-	int bank;
-	for (bank = start_bank; bank < start_bank + bank_count; bank++)
-		LM4_FLASH_FMPPE[F_BANK(bank)] &= ~F_BIT(bank);
-}
-
-/**
- * Perform a write-buffer operation.  Buffer (FWB) and address (FMA) must be
- * pre-loaded.
- *
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int write_buffer(void)
-{
-	int t;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (!LM4_FLASH_FWBVAL)
-		return EC_SUCCESS;  /* Nothing to do */
-
-	/* Clear previous error status */
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;
-
-	/* Start write operation at page boundary */
-	LM4_FLASH_FMC2 = 0xa4420001;
-
-	/*
-	 * Reload the watchdog timer, so that writing a large amount of flash
-	 * doesn't cause a watchdog reset.
-	 */
-	watchdog_reload();
-
-	/* Wait for write to complete */
-	for (t = 0; LM4_FLASH_FMC2 & 0x01; t += 10) {
-		if (t > WRITE_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-		udelay(10);
-	}
-
-	/* Check for error conditions - program failed, erase needed,
-	 * voltage error. */
-	if (LM4_FLASH_FCRIS & 0x2e01)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	const uint32_t *data32 = (const uint32_t *)data;
-	int rv;
-	int i;
-
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	/* Get initial write buffer index and page */
-	LM4_FLASH_FMA = offset & ~(FLASH_FWB_BYTES - 1);
-	i = (offset >> 2) & (FLASH_FWB_WORDS - 1);
-
-	/* Copy words into buffer */
-	for (; size > 0; size -= 4) {
-		LM4_FLASH_FWB[i++] = *data32++;
-		if (i == FLASH_FWB_WORDS) {
-			rv = write_buffer();
-			if (rv != EC_SUCCESS)
-				return rv;
-
-			/* Advance to next page */
-			i = 0;
-			LM4_FLASH_FMA += FLASH_FWB_BYTES;
-		}
-	}
-
-	/* Handle final partial page, if any */
-	if (i > 0)
-		return write_buffer();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	LM4_FLASH_FCMISC = LM4_FLASH_FCRIS;  /* Clear previous error status */
-
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		     offset += CONFIG_FLASH_ERASE_SIZE) {
-		int t;
-
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased(offset, CONFIG_FLASH_ERASE_SIZE))
-			continue;
-
-		LM4_FLASH_FMA = offset;
-
-		/*
-		 * Reload the watchdog timer, so that erasing many flash pages
-		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using msleep() below.
-		 */
-		watchdog_reload();
-
-		/* Start erase */
-		LM4_FLASH_FMC = 0xa4420002;
-
-		/* Wait for erase to complete */
-		for (t = 0; LM4_FLASH_FMC & 0x02; t++) {
-			if (t > ERASE_TIMEOUT_MS)
-				return EC_ERROR_TIMEOUT;
-			msleep(1);
-		}
-
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (LM4_FLASH_FCRIS & 0x0a01)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	return (LM4_FLASH_FMPPE[F_BANK(bank)] & F_BIT(bank)) ? 0 : 1;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Protect the entire flash */
-		all_protected = 1;
-		protect_banks(0, CONFIG_FLASH_SIZE_BYTES /
-			      CONFIG_FLASH_BANK_SIZE);
-	} else
-		/* Protect the WP region (read-only section and pstate) */
-		protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT);
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-
-		/* Update all-now flag if all flash is protected */
-		if (prot_flags & EC_FLASH_PROTECT_ALL_NOW)
-			all_protected = 1;
-
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Otherwise, do a hard boot to clear the flash protection registers */
-	system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
deleted file mode 100644
index 841bfdb214..0000000000
--- a/chip/lm4/gpio.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "switch.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* 0-terminated list of GPIO base addresses */
-static const uint32_t gpio_bases[] = {
-	LM4_GPIO_A, LM4_GPIO_B, LM4_GPIO_C, LM4_GPIO_D,
-	LM4_GPIO_E, LM4_GPIO_F, LM4_GPIO_G, LM4_GPIO_H,
-	LM4_GPIO_J, LM4_GPIO_K, LM4_GPIO_L, LM4_GPIO_M,
-	LM4_GPIO_N, LM4_GPIO_P, LM4_GPIO_Q, 0
-};
-
-/**
- * Find the index of a GPIO port base address
- *
- * This is used by the clock gating registers.
- *
- * @param port_base	Base address to find (LM4_GPIO_[A-Q])
- *
- * @return The index, or -1 if no match.
- */
-static int find_gpio_port_index(uint32_t port_base)
-{
-	int i;
-	for (i = 0; gpio_bases[i]; i++) {
-		if (gpio_bases[i] == port_base)
-			return i;
-	}
-	return -1;
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int port_index = find_gpio_port_index(port);
-	int cgmask;
-
-	/* Ignore (do nothing for) invalid port values */
-	if (port_index < 0)
-		return;
-
-	/* Enable the GPIO port in run and sleep. */
-	cgmask = 1 << port_index;
-	clock_enable_peripheral(CGC_OFFSET_GPIO, cgmask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	if (func != GPIO_ALT_FUNC_NONE) {
-		int pctlmask = 0;
-		int i;
-		/* Expand mask from bits to nibbles */
-		for (i = 0; i < 8; i++) {
-			if (mask & BIT(i))
-				pctlmask |= 1 << (4 * i);
-		}
-
-		LM4_GPIO_PCTL(port) =
-			(LM4_GPIO_PCTL(port) & ~(pctlmask * 0xf)) |
-			(pctlmask * func);
-		LM4_GPIO_AFSEL(port) |= mask;
-	} else {
-		LM4_GPIO_AFSEL(port) &= ~mask;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return LM4_GPIO_DATA(gpio_list[signal].port,
-			     gpio_list[signal].mask) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	/*
-	 * Ok to write 0xff because LM4_GPIO_DATA bit-masks only the bit
-	 * we care about.
-	 */
-	LM4_GPIO_DATA(gpio_list[signal].port,
-		      gpio_list[signal].mask) = (value ? 0xff : 0);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/*
-	 * Select open drain first, so that we don't glitch the signal
-	 * when changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		LM4_GPIO_ODR(port) |= mask;
-	else
-		LM4_GPIO_ODR(port) &= ~mask;
-
-	if (flags & GPIO_OUTPUT)
-		LM4_GPIO_DIR(port) |= mask;
-	else
-		LM4_GPIO_DIR(port) &= ~mask;
-
-	/* Handle pullup / pulldown */
-	if (flags & GPIO_PULL_UP) {
-		LM4_GPIO_PUR(port) |= mask;
-	} else if (flags & GPIO_PULL_DOWN) {
-		LM4_GPIO_PDR(port) |= mask;
-	} else {
-		/* No pull up/down */
-		LM4_GPIO_PUR(port) &= ~mask;
-		LM4_GPIO_PDR(port) &= ~mask;
-	}
-
-	/* Set up interrupt type */
-	if (flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))
-		LM4_GPIO_IS(port) |= mask;
-	else
-		LM4_GPIO_IS(port) &= ~mask;
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		LM4_GPIO_IEV(port) |= mask;
-	else
-		LM4_GPIO_IEV(port) &= ~mask;
-
-	/* Handle interrupting on both edges */
-	if ((flags & GPIO_INT_F_RISING) &&
-	    (flags & GPIO_INT_F_FALLING))
-		LM4_GPIO_IBE(port) |= mask;
-	else
-		LM4_GPIO_IBE(port) &= ~mask;
-
-	if (flags & GPIO_ANALOG)
-		LM4_GPIO_DEN(port) &= ~mask;
-	else
-		LM4_GPIO_DEN(port) |= mask;
-
-	/* Set level */
-	if (flags & GPIO_HIGH)
-		LM4_GPIO_DATA(port, mask) = 0xff;
-	else if (flags & GPIO_LOW)
-		LM4_GPIO_DATA(port, mask) = 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	LM4_GPIO_IM(g->port) &= ~g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if no interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	LM4_GPIO_ICR(g->port) |= g->mask;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Convert GPIO port to a mask that can be used to set the
- * clock gate control register for GPIOs.
- */
-static int gpio_port_to_clock_gate_mask(uint32_t gpio_port)
-{
-	int index = find_gpio_port_index(gpio_port);
-
-	return index >= 0 ? BIT(index) : 0;
-}
-#endif
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (LM4_SYSTEM_RCGCGPIO == 0x7fff) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	} else {
-		/*
-		 * Enable clocks to all the GPIO blocks since we use all of
-		 * them as GPIOs in run and sleep modes.
-		 */
-		clock_enable_peripheral(CGC_OFFSET_GPIO, 0x7fff,
-				CGC_MODE_RUN | CGC_MODE_SLEEP);
-	}
-
-	/*
-	 * Disable GPIO commit control for PD7 and PF0, since we don't use the
-	 * NMI pin function.
-	 */
-	LM4_GPIO_LOCK(LM4_GPIO_D) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_D) |= 0x80;
-	LM4_GPIO_LOCK(LM4_GPIO_D) = 0;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_F) |= 0x01;
-	LM4_GPIO_LOCK(LM4_GPIO_F) = 0;
-
-	/* Clear SSI0 alternate function on PA2:5 */
-	LM4_GPIO_AFSEL(LM4_GPIO_A) &= ~0x3c;
-
-	/* Mask all GPIO interrupts */
-	for (i = 0; gpio_bases[i]; i++)
-		LM4_GPIO_IM(gpio_bases[i]) = 0;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-		/*
-		 * Enable board specific GPIO ports to interrupt deep sleep by
-		 * providing a clock to that port in deep sleep mode.
-		 */
-		if (flags & GPIO_INT_DSLEEP) {
-			clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(g->port),
-				CGC_MODE_ALL);
-		}
-#endif
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the main chipset.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Enable KB scan row to interrupt deep sleep by providing a clock
-	 * signal to that port in deep sleep mode.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_GPIO,
-				gpio_port_to_clock_gate_mask(KB_SCAN_ROW_GPIO),
-				CGC_MODE_ALL);
-#endif
-}
-
-/* List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems. */
-static const uint8_t gpio_irqs[] = {
-	LM4_IRQ_GPIOA, LM4_IRQ_GPIOB, LM4_IRQ_GPIOC, LM4_IRQ_GPIOD,
-	LM4_IRQ_GPIOE, LM4_IRQ_GPIOF, LM4_IRQ_GPIOG, LM4_IRQ_GPIOH,
-	LM4_IRQ_GPIOJ,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPIOK)
-	LM4_IRQ_GPIOK,
-#endif
-	LM4_IRQ_GPIOL, LM4_IRQ_GPIOM,
-#if defined(KB_SCAN_ROW_IRQ) && (KB_SCAN_ROW_IRQ != LM4_IRQ_GPION)
-	LM4_IRQ_GPION,
-#endif
-	LM4_IRQ_GPIOP, LM4_IRQ_GPIOQ
-};
-
-static void gpio_init(void)
-{
-	int i;
-
-	/* Enable IRQs now that pins are set up */
-	for (i = 0; i < ARRAY_SIZE(gpio_irqs); i++)
-		task_enable_irq(gpio_irqs[i]);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * @param port		GPIO port (LM4_GPIO_*)
- * @param mis		Masked interrupt status value for that port
- */
-static void gpio_interrupt(int port, uint32_t mis)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
-		if (port == g->port && (mis & g->mask)) {
-			gpio_irq_handlers[i](i);
-			mis &= ~g->mask;
-		}
-	}
-}
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the main handler above.
- */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)		\
-	void irqfunc(void)				\
-	{						\
-		uint32_t mis = LM4_GPIO_MIS(gpiobase);	\
-		LM4_GPIO_ICR(gpiobase) = mis;		\
-		gpio_interrupt(gpiobase, mis);		\
-	}
-
-GPIO_IRQ_FUNC(__gpio_a_interrupt, LM4_GPIO_A);
-GPIO_IRQ_FUNC(__gpio_b_interrupt, LM4_GPIO_B);
-GPIO_IRQ_FUNC(__gpio_c_interrupt, LM4_GPIO_C);
-GPIO_IRQ_FUNC(__gpio_d_interrupt, LM4_GPIO_D);
-GPIO_IRQ_FUNC(__gpio_e_interrupt, LM4_GPIO_E);
-GPIO_IRQ_FUNC(__gpio_f_interrupt, LM4_GPIO_F);
-GPIO_IRQ_FUNC(__gpio_g_interrupt, LM4_GPIO_G);
-GPIO_IRQ_FUNC(__gpio_h_interrupt, LM4_GPIO_H);
-GPIO_IRQ_FUNC(__gpio_j_interrupt, LM4_GPIO_J);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-GPIO_IRQ_FUNC(__gpio_k_interrupt, LM4_GPIO_K);
-#endif
-GPIO_IRQ_FUNC(__gpio_l_interrupt, LM4_GPIO_L);
-GPIO_IRQ_FUNC(__gpio_m_interrupt, LM4_GPIO_M);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-GPIO_IRQ_FUNC(__gpio_n_interrupt, LM4_GPIO_N);
-#endif
-GPIO_IRQ_FUNC(__gpio_p_interrupt, LM4_GPIO_P);
-GPIO_IRQ_FUNC(__gpio_q_interrupt, LM4_GPIO_Q);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(LM4_IRQ_GPIOA, __gpio_a_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOB, __gpio_b_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOC, __gpio_c_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOE, __gpio_e_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOF, __gpio_f_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOG, __gpio_g_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOH, __gpio_h_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOJ, __gpio_j_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_K)
-DECLARE_IRQ(LM4_IRQ_GPIOK, __gpio_k_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOL, __gpio_l_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOM, __gpio_m_interrupt, 1);
-#if defined(KB_SCAN_ROW_GPIO) && (KB_SCAN_ROW_GPIO != LM4_GPIO_N)
-DECLARE_IRQ(LM4_IRQ_GPION, __gpio_n_interrupt, 1);
-#endif
-DECLARE_IRQ(LM4_IRQ_GPIOP, __gpio_p_interrupt, 1);
-DECLARE_IRQ(LM4_IRQ_GPIOQ, __gpio_q_interrupt, 1);
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
deleted file mode 100644
index 44e1c2fb27..0000000000
--- a/chip/lm4/hwtimer.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	/* set the match on the deadline */
-	LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
-	/* Set the match interrupt */
-	LM4_TIMER_IMR(6) |= 0x10;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return 0xffffffff - LM4_TIMER_TAMATCHR(6);
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupt */
-	LM4_TIMER_IMR(6) &= ~0x10;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - LM4_TIMER_TAV(6);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	LM4_TIMER_TAV(6) = 0xffffffff - ts;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t status = LM4_TIMER_RIS(6);
-
-	/* Clear interrupt */
-	LM4_TIMER_ICR(6) = status;
-
-	/*
-	 * Find expired timers and set the new timer deadline; check the IRQ
-	 * status to determine if the free-running counter overflowed.
-	 */
-	process_timers(status & 0x01);
-}
-DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
-
-static void update_prescaler(void)
-{
-	/*
-	 * Set the prescaler to increment every microsecond.  This takes
-	 * effect immediately, because the TAILD bit in TAMR is clear.
-	 */
-	LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * Use WTIMER0 (timer 6) configured as a free running counter with 1 us
-	 * period.
-	 */
-
-	/* Enable WTIMER0 clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_WTIMER, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Ensure timer is disabled : TAEN = TBEN = 0 */
-	LM4_TIMER_CTL(6) &= ~0x101;
-	/* Set overflow interrupt */
-	LM4_TIMER_IMR(6) = 0x1;
-	/* 32-bit timer mode */
-	LM4_TIMER_CFG(6) = 4;
-
-	/* Set initial prescaler */
-	update_prescaler();
-
-	/* Periodic mode, counting down */
-	LM4_TIMER_TAMR(6) = 0x22;
-	/* Use the full 32-bits of the timer */
-	LM4_TIMER_TAILR(6) = 0xffffffff;
-	/* Starts counting in timer A */
-	LM4_TIMER_CTL(6) |= 0x1;
-
-	/*
-	 * Override the count with the start value now that counting has
-	 * started.
-	 */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(LM4_IRQ_TIMERW0A);
-
-	return LM4_IRQ_TIMERW0A;
-}
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
deleted file mode 100644
index 56084c38e6..0000000000
--- a/chip/lm4/i2c.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for Chrome EC */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Flags for writes to MCS */
-#define LM4_I2C_MCS_RUN   BIT(0)
-#define LM4_I2C_MCS_START BIT(1)
-#define LM4_I2C_MCS_STOP  BIT(2)
-#define LM4_I2C_MCS_ACK   BIT(3)
-#define LM4_I2C_MCS_HS    BIT(4)
-#define LM4_I2C_MCS_QCMD  BIT(5)
-
-/* Flags for reads from MCS */
-#define LM4_I2C_MCS_BUSY   BIT(0)
-#define LM4_I2C_MCS_ERROR  BIT(1)
-#define LM4_I2C_MCS_ADRACK BIT(2)
-#define LM4_I2C_MCS_DATACK BIT(3)
-#define LM4_I2C_MCS_ARBLST BIT(4)
-#define LM4_I2C_MCS_IDLE   BIT(5)
-#define LM4_I2C_MCS_BUSBSY BIT(6)
-#define LM4_I2C_MCS_CLKTO  BIT(7)
-
-/*
- * Minimum delay between resetting the port or sending a stop condition,
- * and when the port can be expected to be back in an idle state (and
- * the peripheral has had long enough to see the start/stop condition
- * edges).
- *
- * 500 us = 50 clocks at 100 KHz bus speed.  This has been experimentally
- * determined to be enough.
- */
-#define I2C_IDLE_US 500
-
-/* IRQ for each port */
-static const uint32_t i2c_irqs[] = {LM4_IRQ_I2C0, LM4_IRQ_I2C1, LM4_IRQ_I2C2,
-				    LM4_IRQ_I2C3, LM4_IRQ_I2C4, LM4_IRQ_I2C5};
-BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_PORT_COUNT);
-
-/* I2C port state data */
-struct i2c_port_data {
-	const uint8_t *out;	/* Output data pointer */
-	int out_size;		/* Output data to transfer, in bytes */
-	uint8_t *in;		/* Input data pointer */
-	int in_size;		/* Input data to transfer, in bytes */
-	int flags;		/* Flags (I2C_XFER_*) */
-	int idx;		/* Index into input/output data */
-	int err;		/* Error code, if any */
-	uint32_t timeout_us;	/* Transaction timeout, or 0 to use default */
-
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-int i2c_is_busy(int port)
-{
-	return LM4_I2C_MCS(port) & LM4_I2C_MCS_BUSBSY;
-}
-
-/**
- * I2C transfer engine.
- *
- * @return Zero when done with transfer (ready to wake task).
- *
- * MCS sequence on multi-byte write:
- *     0x3 0x1 0x1 ... 0x1 0x5
- * Single byte write:
- *     0x7
- *
- * MCS receive sequence on multi-byte read:
- *     0xb 0x9 0x9 ... 0x9 0x5
- * Single byte read:
- *     0x7
- */
-int i2c_do_work(int port)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS_RUN;
-
-	if (pd->flags & I2C_XFER_START) {
-		/* Set start bit on first byte */
-		reg_mcs |= LM4_I2C_MCS_START;
-		pd->flags &= ~I2C_XFER_START;
-	} else if (LM4_I2C_MCS(port) & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST |
-					LM4_I2C_MCS_ERROR)) {
-		/*
-		 * Error after starting; abort transfer.  Ignore errors at
-		 * start because arbitration and timeout errors are taken care
-		 * of in chip_i2c_xfer(), and peripheral ack failures will
-		 * automatically clear once we send a start condition.
-		 */
-		pd->err = EC_ERROR_UNKNOWN;
-		return 0;
-	}
-
-	if (pd->out_size) {
-		/* Send next byte of output */
-		LM4_I2C_MDR(port) = *(pd->out++);
-		pd->idx++;
-
-		/* Handle starting to send last byte */
-		if (pd->idx == pd->out_size) {
-
-			/* Done with output after this */
-			pd->out_size = 0;
-			pd->idx = 0;
-
-			/* Resend start bit when changing direction */
-			pd->flags |= I2C_XFER_START;
-
-			/*
-			 * Send stop bit after last byte if the stop flag is
-			 * on, and caller doesn't expect to receive data.
-			 */
-			if ((pd->flags & I2C_XFER_STOP) && pd->in_size == 0)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-		}
-
-		LM4_I2C_MCS(port) = reg_mcs;
-		return 1;
-
-	} else if (pd->in_size) {
-		if (pd->idx) {
-			/* Copy the byte we just read */
-			*(pd->in++) = LM4_I2C_MDR(port) & 0xff;
-		} else {
-			/* Starting receive; switch to receive address */
-			LM4_I2C_MSA(port) |= 0x01;
-		}
-
-		if (pd->idx < pd->in_size) {
-			/* More data to read */
-			pd->idx++;
-
-			/* ACK all bytes except the last one */
-			if ((pd->flags & I2C_XFER_STOP) &&
-			    pd->idx == pd->in_size)
-				reg_mcs |= LM4_I2C_MCS_STOP;
-			else
-				reg_mcs |= LM4_I2C_MCS_ACK;
-
-			LM4_I2C_MCS(port) = reg_mcs;
-			return 1;
-		}
-	}
-
-	/* If we're still here, done with transfer */
-	return 0;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	struct i2c_port_data *pd = pdata + port;
-	uint32_t reg_mcs = LM4_I2C_MCS(port);
-	int events = 0;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	/* Copy data to port struct */
-	pd->out = out;
-	pd->out_size = out_size;
-	pd->in = in;
-	pd->in_size = in_size;
-	pd->flags = flags;
-	pd->idx = 0;
-	pd->err = 0;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) &&
-	    ((reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST)) ||
-			    (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-		uint32_t tpr = LM4_I2C_MTPR(port);
-
-		CPRINTS("I2C%d Addr:%02X bad status 0x%02x, SCL=%d, SDA=%d",
-			port,
-			I2C_STRIP_FLAGS(addr_flags),
-			reg_mcs,
-			i2c_get_line_levels(port) & I2C_LINE_SCL_HIGH,
-			i2c_get_line_levels(port) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Clock timeout or arbitration lost.  Reset port to clear. */
-		atomic_or(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-		atomic_clear_bits(LM4_SYSTEM_SRI2C_ADDR, BIT(port));
-		clock_wait_cycles(3);
-
-		/* Restore settings */
-		LM4_I2C_MCR(port) = 0x10;
-		LM4_I2C_MTPR(port) = tpr;
-
-		/*
-		 * We don't know what edges the peripheral saw, so sleep
-		 * long enough that the peripheral will see the new
-		 * start condition below.
-		 */
-		usleep(I2C_IDLE_US);
-	}
-
-	/* Set peripheral address for transmit */
-	LM4_I2C_MSA(port) = (I2C_STRIP_FLAGS(addr_flags) << 1) & 0xff;
-
-	/* Enable interrupts */
-	pd->task_waiting = task_get_current();
-	LM4_I2C_MICR(port) = 0x03;
-	LM4_I2C_MIMR(port) = 0x03;
-
-	/* Kick the port interrupt handler to start the transfer */
-	task_trigger_irq(i2c_irqs[port]);
-
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
-
-	/* Disable interrupts */
-	LM4_I2C_MIMR(port) = 0x00;
-	pd->task_waiting = TASK_ID_INVALID;
-
-	/* Handle timeout */
-	if (events & TASK_EVENT_TIMER)
-		pd->err = EC_ERROR_TIMEOUT;
-
-	if (pd->err) {
-		/* Force port back idle */
-		LM4_I2C_MCS(port) = LM4_I2C_MCS_STOP;
-		usleep(I2C_IDLE_US);
-	}
-
-	return pd->err;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-	int ret;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	/* If we are driving the pin low, it must be low. */
-	if (gpio_get_level(g) == 0)
-		return 0;
-
-	/*
-	 * Otherwise, we need to toggle it to an input to read the true pin
-	 * state.
-	 */
-	gpio_set_flags(g, GPIO_INPUT);
-	ret = gpio_get_level(g);
-	gpio_set_flags(g, GPIO_ODR_HIGH);
-
-	return ret;
-}
-
-int i2c_get_line_levels(int port)
-{
-	/* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */
-	return LM4_I2C_MBMON(port) & 0x03;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void i2c_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		/*
-		 * From datasheet:
-		 *     SCL_PRD = 2 * (1 + TPR) * (SCL_LP + SCL_HP) * CLK_PRD
-		 *
-		 * so:
-		 *     TPR = SCL_PRD / (2 * (SCL_LP + SCL_HP) * CLK_PRD) - 1
-		 *
-		 * converting from period to frequency:
-		 *     TPR = CLK_FREQ / (SCL_FREQ * 2 * (SCL_LP + SCL_HP)) - 1
-		 */
-		const int d = 2 * (6 + 4) * (i2c_ports[i].kbps * 1000);
-
-		/* Round TPR up, so desired kbps is an upper bound */
-		const int tpr = (freq + d - 1) / d - 1;
-
-#ifdef PRINT_I2C_SPEEDS
-		const int f = freq / (2 * (1 + tpr) * (6 + 4));
-		CPRINTS("I2C%d clk=%d tpr=%d freq=%d",
-			i2c_ports[i].port, freq, tpr, f);
-#endif
-
-		LM4_I2C_MTPR(i2c_ports[i].port) = tpr;
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	uint32_t mask = 0;
-	int i;
-
-	/* Enable I2C modules in run and sleep modes. */
-	for (i = 0; i < i2c_ports_used; i++)
-		mask |= 1 << i2c_ports[i].port;
-
-	clock_enable_peripheral(CGC_OFFSET_I2C, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Initialize ports as controller, with interrupts enabled */
-	for (i = 0; i < i2c_ports_used; i++)
-		LM4_I2C_MCR(i2c_ports[i].port) = 0x10;
-
-	/* Set initial clock frequency */
-	i2c_freq_changed();
-
-	/* Enable IRQs; no tasks are waiting on ports */
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		pdata[i].task_waiting = TASK_ID_INVALID;
-		task_enable_irq(i2c_irqs[i]);
-
-		/* Use default timeout */
-		i2c_set_timeout(i, 0);
-	}
-}
-
-/**
- * Handle an interrupt on the specified port.
- *
- * @param port		I2C port generating interrupt
- */
-static void handle_interrupt(int port)
-{
-	int id = pdata[port].task_waiting;
-
-	/* Clear the interrupt status */
-	LM4_I2C_MICR(port) = LM4_I2C_MMIS(port);
-
-	/* If no task is waiting, just return */
-	if (id == TASK_ID_INVALID)
-		return;
-
-	/* If done doing work, wake up the task waiting for the transfer */
-	if (!i2c_do_work(port))
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-
-DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C2, i2c2_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C3, i2c3_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C4, i2c4_interrupt, 2);
-DECLARE_IRQ(LM4_IRQ_I2C5, i2c5_interrupt, 2);
diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c
deleted file mode 100644
index 81af0efdde..0000000000
--- a/chip/lm4/keyboard_raw.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-
-void keyboard_raw_init(void)
-{
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * Set column outputs as open-drain; we either pull them low or let
-	 * them float high.
-	 */
-	LM4_GPIO_AFSEL(LM4_GPIO_P) = 0;  /* KSO[7:0] */
-	LM4_GPIO_AFSEL(LM4_GPIO_Q) &= ~0x1f;  /* KSO[12:8] */
-	LM4_GPIO_DEN(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DEN(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_DIR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_DIR(LM4_GPIO_Q) |= 0x1f;
-	LM4_GPIO_ODR(LM4_GPIO_P) = 0xff;
-	LM4_GPIO_ODR(LM4_GPIO_Q) |= 0x1f;
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/*
-	 * When column 2 is inverted, the Silego has a pulldown instead of a
-	 * pullup.  So drive it push-pull instead of open-drain.
-	 */
-	LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2);
-#endif
-
-	/* Set row inputs with pull-up */
-	LM4_GPIO_AFSEL(KB_SCAN_ROW_GPIO) &= 0xff;
-	LM4_GPIO_DEN(KB_SCAN_ROW_GPIO) |= 0xff;
-	LM4_GPIO_DIR(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_PUR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Edge-sensitive on both edges. */
-	LM4_GPIO_IS(KB_SCAN_ROW_GPIO) = 0;
-	LM4_GPIO_IBE(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
-	 * masked off, so this won't trigger interrupts yet.
-	 */
-	LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(KB_SCAN_ROW_IRQ);
-}
-
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int mask;
-
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0x1fff;			/* Tri-state all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;			/* Assert all outputs */
-	else
-		mask = 0x1fff ^ BIT(col);	/* Assert a single output */
-
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/* Invert column 2 output */
-	mask ^= BIT(2);
-#endif
-
-	LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff;
-	LM4_GPIO_DATA(LM4_GPIO_Q, 0x1f) = (mask >> 8) & 0x1f;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return LM4_GPIO_DATA(KB_SCAN_ROW_GPIO, 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear pending interrupts before enabling them, because the
-		 * raw interrupt status may have been tripped by keyboard
-		 * scanning or, if a key is already pressed, by driving all the
-		 * outputs.
-		 *
-		 * We won't lose keyboard events because the scanning task will
-		 * explicitly check the raw row state before waiting for an
-		 * interrupt.  If a key is pressed, the task won't wait.
-		 */
-		LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0xff;
-	} else {
-		LM4_GPIO_IM(KB_SCAN_ROW_GPIO) = 0;
-	}
-}
-
-/**
- * Interrupt handler for the entire GPIO bank of keyboard rows.
- */
-void keyboard_raw_interrupt(void)
-{
-	/* Clear all pending keyboard interrupts */
-	LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(KB_SCAN_ROW_IRQ, keyboard_raw_interrupt, 3);
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
deleted file mode 100644
index 6e3c39220d..0000000000
--- a/chip/lm4/lpc.c
+++ /dev/null
@@ -1,835 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "pwm.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* LPC channels */
-#define LPC_CH_ACPI     0  /* ACPI commands */
-#define LPC_CH_PORT80   1  /* Port 80 debug output */
-#define LPC_CH_CMD_DATA 2  /* Data for host commands (args/params/response) */
-#define LPC_CH_KEYBOARD 3  /* 8042 keyboard emulation */
-#define LPC_CH_CMD      4  /* Host commands */
-#define LPC_CH_MEMMAP   5  /* Memory-mapped data */
-#define LPC_CH_COMX     7  /* UART emulation */
-/* LPC pool offsets */
-#define LPC_POOL_OFFS_ACPI       0  /* ACPI commands - 0=in, 1=out */
-#define LPC_POOL_OFFS_PORT80     4  /* Port 80 - 4=in, 5=out */
-#define LPC_POOL_OFFS_COMX       8  /* UART emulation range - 8-15 */
-#define LPC_POOL_OFFS_KEYBOARD  16  /* Keyboard - 16=in, 17=out */
-#define LPC_POOL_OFFS_CMD       20  /* Host commands - 20=in, 21=out */
-#define LPC_POOL_OFFS_CMD_DATA 512  /* Data range for host commands - 512-767 */
-#define LPC_POOL_OFFS_MEMMAP   768  /* Memory-mapped data - 768-1023 */
-/* LPC pool data pointers */
-#define LPC_POOL_ACPI     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_ACPI)
-#define LPC_POOL_PORT80   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_PORT80)
-#define LPC_POOL_COMX     (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_COMX)
-#define LPC_POOL_KEYBOARD (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KEYBOARD)
-#define LPC_POOL_CMD      (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD)
-#define LPC_POOL_CMD_DATA (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD_DATA)
-#define LPC_POOL_MEMMAP   (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_MEMMAP)
-/* LPC COMx I/O address (in x86 I/O address space) */
-#define LPC_COMX_ADDR 0x3f8  /* COM1 */
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static uint8_t * const cmd_params = (uint8_t *)LPC_POOL_CMD_DATA +
-	EC_LPC_ADDR_HOST_PARAM - EC_LPC_ADDR_HOST_ARGS;
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)LPC_POOL_CMD_DATA;
-
-static void wait_irq_sent(void)
-{
-	/*
-	 * A hard-coded delay here isn't very elegant, but it's the best we can
-	 * manage (and it's a short delay, so it's not that horrible).  We need
-	 * this because SIRQRIS isn't cleared in continuous mode, and the EC
-	 * has trouble sending more than 1 frame in quiet mode.  Waiting 4 us =
-	 * 2 SERIRQ frames ensures the IRQ has been sent out.
-	 */
-	udelay(4);
-}
-
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-static void keyboard_irq_assert(void)
-{
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	uint64_t tstop = get_time().val + MSEC;
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	/* Wait for host senses the interrupt and gets the char. */
-	do {
-		if (get_time().val > tstop)
-			break;
-	} while (lpc_keyboard_has_char());
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-}
-#else
-static void wait_send_serirq(uint32_t lpcirqctl)
-{
-	LM4_LPC_LPCIRQCTL = lpcirqctl;
-	wait_irq_sent();
-}
-
-/**
- * Manually generate an IRQ to host (edge-trigger).
- *
- * @param irq_num	IRQ number to generate.  Pass 0 to set the AH
- *			(active high) bit.
- *
- * For SERIRQ quite mode, we need to set LM4_LPC_LPCIRQCTL twice.
- * The first one is to assert IRQ (pull low), and then the second one is
- * to de-assert it. This generates a pulse (high-low-high) for an IRQ.
- */
-static void lpc_manual_irq(int irq_num)
-{
-	uint32_t common_bits =
-	    0x00000004 |  /* PULSE */
-	    0x00000002 |  /* ONCHG - for quiet mode */
-	    0x00000001;   /* SND - send immediately */
-
-	/* Send out the IRQ first. */
-	wait_send_serirq((1 << (irq_num + 16)) | common_bits);
-
-	/* Generate a all-high frame to simulate a rising edge. */
-	wait_send_serirq(common_bits);
-}
-
-static inline void keyboard_irq_assert(void)
-{
-	/* Use serirq method. */
-	lpc_manual_irq(1);  /* IRQ#1 */
-}
-#endif
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	host_event_t smi;
-
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-
-	smi = lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI);
-	if (smi)
-		HOST_EVENT_CPRINTS("smi", smi);
-}
-
-/**
- * Generate SCI pulse to the host chipset via LPC0SCI.
- */
-static void lpc_generate_sci(void)
-{
-	host_event_t sci;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	LM4_LPC_LPCCTL |= LM4_LPC_SCI_START;
-#endif
-
-	sci = lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI);
-	if (sci)
-		HOST_EVENT_CPRINTS("sci", sci);
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(uint64_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)LPC_POOL_MEMMAP;
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = args->result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	LPC_POOL_CMD[1] = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	task_disable_irq(LM4_IRQ_LPC);
-	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
-	task_enable_irq(LM4_IRQ_LPC);
-}
-
-int lpc_keyboard_has_char(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_TOH) ? 1 : 0;
-}
-
-/* Return true if the FRMH is set */
-int lpc_keyboard_input_pending(void)
-{
-	return (LM4_LPC_ST(LPC_CH_KEYBOARD) & LM4_LPC_ST_FRMH) ? 1 : 0;
-}
-
-/* Put a char to host buffer and send IRQ if specified. */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	LPC_POOL_KEYBOARD[1] = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/* Make sure the previous TOH and IRQ has been sent out. */
-	wait_irq_sent();
-
-	LM4_LPC_ST(LPC_CH_KEYBOARD) &= ~LM4_LPC_ST_TOH;
-
-	/* Ensure there is no TOH set in this period. */
-	wait_irq_sent();
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-#ifdef CONFIG_UART_HOST
-
-int lpc_comx_has_char(void)
-{
-	return LM4_LPC_ST(LPC_CH_COMX) & LM4_LPC_ST_FRMH;
-}
-
-int lpc_comx_get_char(void)
-{
-	return LPC_POOL_COMX[0];
-}
-
-void lpc_comx_put_char(int c)
-{
-	LPC_POOL_COMX[1] = c;
-
-	/*
-	 * We could in theory manually trigger an IRQ, like we do for the 8042
-	 * keyboard interface, but neither the kernel nor BIOS seems to require
-	 * this.
-	 */
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMI_L GPIO
- *   - SCI pulse via LPC0SCI
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(LM4_IRQ_LPC);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(LM4_LPC_ST(LPC_CH_ACPI) & LM4_LPC_ST_SMI))
-			need_smi = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SMI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SMI;
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SCI;
-	} else
-		LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SCI;
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(LM4_IRQ_LPC);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	uint32_t set_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		set_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) |= set_mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	uint32_t clear_mask = 0;
-	if (mask & EC_LPC_STATUS_BURST_MODE)
-		clear_mask |= LM4_LPC_ST_BURST;
-
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~clear_mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0;
-}
-
-/**
- * Handle write to ACPI I/O port
- *
- * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
- */
-static void handle_acpi_write(int is_cmd)
-{
-	uint8_t value, result;
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_BUSY;
-
-	/* Read command/data; this clears the FRMH status bit. */
-	value = LPC_POOL_ACPI[0];
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		LPC_POOL_ACPI[1] = result;
-
-	/* Clear the busy bit */
-	LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_BUSY;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-/**
- * Handle write to host command I/O ports.
- *
- * @param is_cmd	Is write command (1) or data (0)?
- */
-static void handle_host_write(int is_cmd)
-{
-	/* Ignore data writes or overlapping commands from host */
-	uint32_t is_overlapping = LM4_LPC_ST(LPC_CH_CMD) & LM4_LPC_ST_BUSY;
-	if (!is_cmd || is_overlapping) {
-		if (is_overlapping)
-			CPRINTS("LPC Ignoring overlapping HC");
-		LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_FRMH;
-		return;
-	}
-
-	/* Set the busy bit */
-	LM4_LPC_ST(LPC_CH_CMD) |= LM4_LPC_ST_BUSY;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = LPC_POOL_CMD[0];
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* See if we have an old or new style command */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)LPC_POOL_CMD_DATA;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)LPC_POOL_CMD_DATA;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-
-	} else if (host_cmd_flags & EC_HOST_ARGS_FLAG_FROM_HOST) {
-		/* Version 2 (link) style command */
-		int size = lpc_host_args->data_size;
-		int csum, i;
-
-		host_cmd_args.version = lpc_host_args->command_version;
-		host_cmd_args.params = params_copy;
-		host_cmd_args.params_size = size;
-		host_cmd_args.response = cmd_params;
-		host_cmd_args.response_max = EC_PROTO2_MAX_PARAM_SIZE;
-		host_cmd_args.response_size = 0;
-
-		/* Verify params size */
-		if (size > EC_PROTO2_MAX_PARAM_SIZE) {
-			host_cmd_args.result = EC_RES_INVALID_PARAM;
-		} else {
-			const uint8_t *src = cmd_params;
-			uint8_t *copy = params_copy;
-
-			/*
-			 * Verify checksum and copy params out of LPC space.
-			 * This ensures the data acted on by the host command
-			 * handler can't be changed by host writes after the
-			 * checksum is verified.
-			 */
-			csum = host_cmd_args.command +
-				host_cmd_flags +
-				host_cmd_args.version +
-				host_cmd_args.params_size;
-
-			for (i = 0; i < size; i++) {
-				csum += *src;
-				*(copy++) = *(src++);
-			}
-
-			if ((uint8_t)csum != lpc_host_args->checksum)
-				host_cmd_args.result = EC_RES_INVALID_CHECKSUM;
-		}
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-/**
- * LPC interrupt handler
- */
-void lpc_interrupt(void)
-{
-	uint32_t mis = LM4_LPC_LPCMIS;
-	uint32_t st;
-
-	/* Clear the interrupt bits we're handling */
-	LM4_LPC_LPCIC = mis;
-
-#ifdef HAS_TASK_HOSTCMD
-	/* Handle ACPI command and data writes */
-	st = LM4_LPC_ST(LPC_CH_ACPI);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_acpi_write(st & LM4_LPC_ST_CMD);
-
-	/* Handle user command writes */
-	st = LM4_LPC_ST(LPC_CH_CMD);
-	if (st & LM4_LPC_ST_FRMH)
-		handle_host_write(st & LM4_LPC_ST_CMD);
-#endif
-
-	/*
-	 * Handle port 80 writes (CH0MIS1).  Due to crosbug.com/p/12349 the
-	 * interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2))
-	 * apparently gets lost on back-to-back writes to port 80, so check the
-	 * FRMH bit in the channel status register to see if a write is
-	 * pending.  Loop to handle bursts of back-to-back writes.
-	 */
-	while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH)
-		port_80_write(LPC_POOL_PORT80[0]);
-
-#ifdef HAS_TASK_KEYPROTO
-	/* Handle keyboard interface writes */
-	st = LM4_LPC_ST(LPC_CH_KEYBOARD);
-	if (st & LM4_LPC_ST_FRMH)
-		keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD);
-
-	if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) {
-		/* Host read data; wake up task to send remaining bytes */
-		task_wake(TASK_ID_KEYPROTO);
-	}
-#endif
-
-#ifdef CONFIG_UART_HOST
-	/* Handle COMx */
-	if (lpc_comx_has_char()) {
-		/* Copy a character to the UART if there's space */
-		if (uart_comx_putc_ok())
-			uart_comx_putc(lpc_comx_get_char());
-	}
-#endif
-
-	/* Debugging: print changes to LPC0RESET */
-	if (mis & BIT(31)) {
-		if (LM4_LPC_LPCSTS & BIT(10)) {
-			int i;
-
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-			/*
-			 * Workaround for crosbug.com/p/12349; clear all FRMH
-			 * bits so host writes will trigger interrupts.
-			 */
-			for (i = 0; i < 8; i++)
-				LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH;
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-	}
-}
-DECLARE_IRQ(LM4_IRQ_LPC, lpc_interrupt, 2);
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	LM4_LPC_LPCIM &= ~(LM4_LPC_INT_MASK(LPC_CH_ACPI, 6));
-}
-
-static void lpc_init(void)
-{
-	/* Enable LPC clock in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_LPC, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_LPC_LPCIM = 0;
-	LM4_LPC_LPCCTL = 0;
-	LM4_LPC_LPCIRQCTL = 0;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/*
-	 * Set LPC channel 0 to I/O address 0x62 (data) / 0x66 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_ACPI) = EC_LPC_ADDR_ACPI_DATA;
-	LM4_LPC_CTL(LPC_CH_ACPI) = (LPC_POOL_OFFS_ACPI << (5 - 1));
-	LM4_LPC_ST(LPC_CH_ACPI) = 0;
-	/* Unmask interrupt for host command and data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
-
-	/*
-	 * Set LPC channel 1 to I/O address 0x80 (data), single endpoint,
-	 * pool bytes 4(data)/5(cmd).
-	 */
-	LM4_LPC_ADR(LPC_CH_PORT80) = 0x80;
-	LM4_LPC_CTL(LPC_CH_PORT80) = (LPC_POOL_OFFS_PORT80 << (5 - 1));
-	/* Unmask interrupt for host data writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_PORT80, 2);
-
-	/*
-	 * Set LPC channel 2 to I/O address 0x880, range endpoint,
-	 * arbitration disabled, pool bytes 512-639.  To access this from
-	 * x86, use the following command to set GEN_LPC2:
-	 *
-	 *   pci_write32 0 0x1f 0 0x88 0x007c0801
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD_DATA) = EC_LPC_ADDR_HOST_ARGS;
-	LM4_LPC_CTL(LPC_CH_CMD_DATA) = 0x8019 |
-		(LPC_POOL_OFFS_CMD_DATA << (5 - 1));
-
-	/*
-	 * Set LPC channel 3 to I/O address 0x60 (data) / 0x64 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60;
-	LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) |
-		(0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1));
-	LM4_LPC_ST(LPC_CH_KEYBOARD) = 0;
-	/* Unmask interrupt for host command/data writes and data reads */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 7);
-
-	/*
-	 * Set LPC channel 4 to I/O address 0x200 (data) / 0x204 (command),
-	 * single endpoint, offset 0 for host command/writes and 1 for EC
-	 * data writes, pool bytes 0(data)/1(cmd)
-	 */
-	LM4_LPC_ADR(LPC_CH_CMD) = EC_LPC_ADDR_HOST_DATA;
-	LM4_LPC_CTL(LPC_CH_CMD) = (LPC_POOL_OFFS_CMD << (5 - 1));
-	/*
-	 * Initialize status bits to 0.  We never set the ACPI burst status bit,
-	 * so this guarantees that at least one status bit will always be 0.
-	 * This is used by comm_lpc.c to detect that the EC is present on the
-	 * LPC bus.  See crosbug.com/p/10963.
-	 */
-	LM4_LPC_ST(LPC_CH_CMD) = 0;
-	/* Unmask interrupt for host command writes */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_CMD, 4);
-
-	/*
-	 * Set LPC channel 5 to I/O address 0x900, range endpoint,
-	 * arbitration enabled, pool bytes 768-1023.  To access this from
-	 * x86, use the following command to set GEN_LPC3:
-	 *
-	 *   pci_write32 0 0x1f 0 0x8c 0x007c0901
-	 */
-	LM4_LPC_ADR(LPC_CH_MEMMAP) = EC_LPC_ADDR_MEMMAP;
-	LM4_LPC_CTL(LPC_CH_MEMMAP) = 0x0019 | (LPC_POOL_OFFS_MEMMAP << (5 - 1));
-
-#ifdef CONFIG_UART_HOST
-	/*
-	 * Set LPC channel 7 to COM port I/O address.  Note that channel 7
-	 * ignores the TYPE bit and is always an 8-byte range.
-	 */
-	LM4_LPC_ADR(LPC_CH_COMX) = LPC_COMX_ADDR;
-	/*
-	 * In theory we could configure IRQSELs and set IRQEN2/CX, and then the
-	 * host could enable IRQs on its own.  So far that hasn't been
-	 * necessary, and due to the issues with IRQs (see wait_irq_sent()
-	 * above) it might not work anyway.
-	 */
-	LM4_LPC_CTL(LPC_CH_COMX) = 0x0004 | (LPC_POOL_OFFS_COMX << (5 - 1));
-	/* Enable COMx emulation for reads and writes. */
-	LM4_LPC_LPCDMACX = 0x00310000;
-	/*
-	 * Unmask interrupt for host data writes.  We don't need interrupts for
-	 * reads, because there's no flow control in that direction; LPC is
-	 * much faster than the UART, and the UART doesn't have anywhere
-	 * sensible to buffer input anyway.
-	 */
-	LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_COMX, 2);
-#endif /* CONFIG_UART_HOST */
-
-	/*
-	 * Unmask LPC bus reset interrupt.  This lets us monitor the PCH
-	 * PLTRST# signal for debugging.
-	 */
-	LM4_LPC_LPCIM |= BIT(31);
-
-	/* Enable LPC channels */
-	LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 |
-		BIT(LPC_CH_ACPI) |
-		BIT(LPC_CH_PORT80) |
-		BIT(LPC_CH_CMD_DATA) |
-		BIT(LPC_CH_KEYBOARD) |
-		BIT(LPC_CH_CMD) |
-		BIT(LPC_CH_MEMMAP);
-
-#ifdef CONFIG_UART_HOST
-	LM4_LPC_LPCCTL |= 1 << LPC_CH_COMX;
-#endif
-
-	/*
-	 * Ensure the EC (peripheral) has control of the memory-mapped
-	 * I/O space.  Once the EC has won arbitration for the
-	 * memory-mapped space, it will keep control of it until it
-	 * writes the last byte in the space.  (That never happens; we
-	 * can't use the last byte in the space because ACPI can't see
-	 * it anyway.)
-	 */
-	while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
-		/* Clear HW1ST */
-		LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
-		/* Do a peripheral write; this should cause SW1ST to be set */
-		*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
-	}
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Enable LPC interrupt */
-	task_enable_irq(LM4_IRQ_LPC);
-
-#ifdef CONFIG_UART_HOST
-	/* Enable COMx UART */
-	uart_comx_enable();
-#endif
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-static void lpc_tick(void)
-{
-	/*
-	 * Make sure pending LPC interrupts have been processed.
-	 * This works around a LM4 bug where host writes sometimes
-	 * don't trigger interrupts.  See crosbug.com/p/13965.
-	 */
-	task_trigger_irq(LM4_IRQ_LPC);
-}
-DECLARE_HOOK(HOOK_TICK, lpc_tick, HOOK_PRIO_DEFAULT);
-
-/**
- * Get protocol information
- */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(2) | BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     lpc_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c
deleted file mode 100644
index b3b54a64bc..0000000000
--- a/chip/lm4/peci.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-/* Initial PECI baud rate */
-#define PECI_BAUD_RATE 100000
-
-/* Polling interval for PECI, in ms */
-#define PECI_POLL_INTERVAL_MS 250
-
-/*
- * Internal and external path delays, in ns.  The external delay is a
- * best-guess measurement, but we're fairly tolerant of a bad guess because
- * PECI_BAUD_RATE is slow compared to PECI's actual maximum baud rate.
- */
-#define PECI_TD_FET_NS 60
-#define PECI_TD_INT_NS 80
-
-/* Number of controller retries. Should be between 0 and 7. */
-#define PECI_RETRY_COUNT 4
-
-/* Timing negotiation error bypass. 1 = on. 0 = off. */
-#define PECI_ERROR_BYPASS 1
-
-#define TEMP_AVG_LENGTH 4  /* Should be power of 2 */
-static int temp_vals[TEMP_AVG_LENGTH];
-static int temp_idx;
-
-int peci_get_cpu_temp(void)
-{
-	int v = LM4_PECI_M0D0 & 0xffff;
-
-	if (v >= 0x8000 && v <= 0x8fff)
-		return -1;
-
-	return v >> 6;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int sum = 0;
-	int success_cnt = 0;
-	int i;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i) {
-		if (temp_vals[i] >= 0) {
-			success_cnt++;
-			sum += temp_vals[i];
-		}
-	}
-
-	/*
-	 * Require at least two valid samples. When the AP transitions into S0,
-	 * it is possible, depending on the timing of the PECI sample, to read
-	 * an invalid temperature. This is very rare, but when it does happen
-	 * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
-	 * samples here assures us that one bad maximum temperature reading
-	 * when entering S0 won't cause us to trigger an over temperature.
-	 */
-	if (success_cnt < 2)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = sum / success_cnt;
-	return EC_SUCCESS;
-}
-
-static void peci_temp_sensor_poll(void)
-{
-	temp_vals[temp_idx] = peci_get_cpu_temp();
-	temp_idx = (temp_idx + 1) & (TEMP_AVG_LENGTH - 1);
-}
-DECLARE_HOOK(HOOK_TICK, peci_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static void peci_freq_changed(void)
-{
-	int freq = clock_get_freq();
-	int baud;
-
-	/* Disable polling while reconfiguring */
-	LM4_PECI_CTL = 0;
-
-	/*
-	 * Calculate baud setting from desired rate, compensating for internal
-	 * and external delays.
-	 */
-	baud = freq / (4 * PECI_BAUD_RATE) - 2;
-	baud -= (freq / 1000000) * (PECI_TD_FET_NS + PECI_TD_INT_NS) / 1000;
-
-	/* Set baud rate and polling rate */
-	LM4_PECI_DIV = (baud << 16) |
-		(PECI_POLL_INTERVAL_MS * (freq / 1000 / 4096));
-
-	/* Set up temperature monitoring to report in degrees K */
-	LM4_PECI_CTL = ((CONFIG_PECI_TJMAX + 273) << 22) | 0x0001 |
-		       (PECI_RETRY_COUNT << 12) |
-		       (PECI_ERROR_BYPASS << 11);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, peci_freq_changed, HOOK_PRIO_DEFAULT);
-
-static void peci_init(void)
-{
-	int i;
-
-	/* Enable the PECI module in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_PECI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_PECI, 1);
-
-	/* Set initial clock frequency */
-	peci_freq_changed();
-
-	/* Initialize temperature reading buffer to a valid value. */
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i)
-		temp_vals[i] = 300; /* 27 C */
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t = peci_get_cpu_temp();
-	if (t == -1) {
-		ccprintf("PECI error 0x%04x\n", LM4_PECI_M0D0 & 0xffff);
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("CPU temp = %d K = %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
-			"Print CPU temperature");
diff --git a/chip/lm4/pwm.c b/chip/lm4/pwm.c
deleted file mode 100644
index 38ce61714d..0000000000
--- a/chip/lm4/pwm.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for LM4.
- *
- * On this chip, the PWM logic is implemented by the hardware FAN modules.
- */
-
-#include "clock.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	fan_set_enabled(pwm_channels[ch].channel, enabled);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return fan_get_enabled(pwm_channels[ch].channel);
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	/* Assume the fan control is active high and invert it ourselves */
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	/* Always enable the channel */
-	pwm_enable(ch, 1);
-
-	/* Set the duty cycle */
-	fan_set_duty(pwm_channels[ch].channel, percent);
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	int percent = fan_get_duty(pwm_channels[ch].channel);
-
-	if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)
-		percent = 100 - percent;
-
-	return percent;
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i)
-		fan_channel_setup(pwm_channels[i].channel,
-				       (pwm_channels[i].flags &
-					PWM_CONFIG_HAS_RPM_MODE)
-				       ? FAN_USE_RPM_MODE : 0);
-}
-
-/* The chip-specific fan module initializes before this. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/lm4/pwm_chip.h b/chip/lm4/pwm_chip.h
deleted file mode 100644
index ada5785495..0000000000
--- a/chip/lm4/pwm_chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LM4-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
deleted file mode 100644
index 0c59da19f6..0000000000
--- a/chip/lm4/registers.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for LM4x processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-#define LM4_UART_CH0_BASE      0x4000c000
-#define LM4_UART_CH1_BASE      0x4000d000
-#define LM4_UART_CH_SEP        0x00001000
-static inline int lm4_uart_addr(int ch, int offset)
-{
-	return offset + LM4_UART_CH0_BASE + LM4_UART_CH_SEP * ch;
-}
-#define LM4UARTREG(ch, offset) REG32(lm4_uart_addr(ch, offset))
-#define LM4_UART_DR(ch)        LM4UARTREG(ch, 0x000)
-#define LM4_UART_FR(ch)        LM4UARTREG(ch, 0x018)
-#define LM4_UART_IBRD(ch)      LM4UARTREG(ch, 0x024)
-#define LM4_UART_FBRD(ch)      LM4UARTREG(ch, 0x028)
-#define LM4_UART_LCRH(ch)      LM4UARTREG(ch, 0x02c)
-#define LM4_UART_CTL(ch)       LM4UARTREG(ch, 0x030)
-#define LM4_UART_IFLS(ch)      LM4UARTREG(ch, 0x034)
-#define LM4_UART_IM(ch)        LM4UARTREG(ch, 0x038)
-#define LM4_UART_ICR(ch)       LM4UARTREG(ch, 0x044)
-#define LM4_UART_DMACTL(ch)    LM4UARTREG(ch, 0x048)
-#define LM4_UART_CC(ch)        LM4UARTREG(ch, 0xfc8)
-
-#define LM4_SSI_BASE           0x40008000
-#define LM4_SSI_CH_SEP         0x40001000
-static inline int lm4_spi_addr(int ch, int offset)
-{
-	return offset + LM4_SSI_BASE + LM4_SSI_CH_SEP * ch;
-}
-#define LM4SSIREG(ch, offset)  REG32(lm4_spi_addr(ch, offset))
-#define LM4_SSI_CR0(ch)        LM4SSIREG(ch, 0x000)
-#define LM4_SSI_CR1(ch)        LM4SSIREG(ch, 0x004)
-#define LM4_SSI_DR(ch)         LM4SSIREG(ch, 0x008)
-#define LM4_SSI_SR(ch)         LM4SSIREG(ch, 0x00c)
-#define LM4_SSI_SR_TFE         BIT(0)  /* Transmit FIFO empty */
-#define LM4_SSI_SR_TNF         BIT(1)  /* Transmit FIFO not full */
-#define LM4_SSI_SR_RNE         BIT(2)  /* Receive FIFO not empty */
-#define LM4_SSI_SR_RFF         BIT(3)  /* Receive FIFO full */
-#define LM4_SSI_SR_BSY         BIT(4)  /* Busy */
-#define LM4_SSI_CPSR(ch)       LM4SSIREG(ch, 0x010)
-#define LM4_SSI_IM(ch)         LM4SSIREG(ch, 0x014)
-#define LM4_SSI_RIS(ch)        LM4SSIREG(ch, 0x018)
-#define LM4_SSI_MIS(ch)        LM4SSIREG(ch, 0x01c)
-#define LM4_SSI_ICR(ch)        LM4SSIREG(ch, 0x020)
-#define LM4_SSI_DMACTL(ch)     LM4SSIREG(ch, 0x024)
-#define LM4_SSI_CC(ch)         LM4SSIREG(ch, 0xfc8)
-
-#define LM4_ADC_ADCACTSS       REG32(0x40038000)
-#define LM4_ADC_ADCRIS         REG32(0x40038004)
-#define LM4_ADC_ADCIM          REG32(0x40038008)
-#define LM4_ADC_ADCISC         REG32(0x4003800c)
-#define LM4_ADC_ADCOSTAT       REG32(0x40038010)
-#define LM4_ADC_ADCEMUX        REG32(0x40038014)
-#define LM4_ADC_ADCUSTAT       REG32(0x40038018)
-#define LM4_ADC_ADCSSPRI       REG32(0x40038020)
-#define LM4_ADC_ADCSPC         REG32(0x40038024)
-#define LM4_ADC_ADCPSSI        REG32(0x40038028)
-#define LM4_ADC_ADCSAC         REG32(0x40038030)
-#define LM4_ADC_ADCCTL         REG32(0x40038038)
-#define LM4_ADC_ADCCC          REG32(0x40038fc8)
-#define LM4_ADC_SS0_BASE       0x40038040
-#define LM4_ADC_SS1_BASE       0x40038060
-#define LM4_ADC_SS2_BASE       0x40038080
-#define LM4_ADC_SS3_BASE       0x400380a0
-#define LM4_ADC_SS_SEP         0x00000020
-static inline int lm4_adc_addr(int ss, int offset)
-{
-	return offset + LM4_ADC_SS0_BASE + LM4_ADC_SS_SEP * ss;
-}
-#define LM4ADCREG(ss, offset)  REG32(lm4_adc_addr(ss, offset))
-#define LM4_ADC_SSMUX(ss)      LM4ADCREG(ss, 0x000)
-#define LM4_ADC_SSCTL(ss)      LM4ADCREG(ss, 0x004)
-#define LM4_ADC_SSFIFO(ss)     LM4ADCREG(ss, 0x008)
-#define LM4_ADC_SSFSTAT(ss)    LM4ADCREG(ss, 0x00c)
-#define LM4_ADC_SSOP(ss)       LM4ADCREG(ss, 0x010)
-#define LM4_ADC_SSEMUX(ss)     LM4ADCREG(ss, 0x018)
-
-#define LM4_LPC_LPCCTL         REG32(0x40080000)
-#define LM4_LPC_SCI_START      BIT(9)  /* Start a pulse on LPC0SCI signal */
-#define LM4_LPC_SCI_CLK_1      (0 << 10) /* SCI asserted for 1 clock period */
-#define LM4_LPC_SCI_CLK_2      (1 << 10) /* SCI asserted for 2 clock periods */
-#define LM4_LPC_SCI_CLK_4      (2 << 10) /* SCI asserted for 4 clock periods */
-#define LM4_LPC_SCI_CLK_8      (3 << 10) /* SCI asserted for 8 clock periods */
-#define LM4_LPC_LPCSTS         REG32(0x40080004)
-#define LM4_LPC_LPCIRQCTL      REG32(0x40080008)
-#define LM4_LPC_LPCIRQST       REG32(0x4008000c)
-#define LM4_LPC_LPCIM          REG32(0x40080100)
-#define LM4_LPC_LPCRIS         REG32(0x40080104)
-#define LM4_LPC_LPCMIS         REG32(0x40080108)
-#define LM4_LPC_LPCIC          REG32(0x4008010c)
-#define LM4_LPC_INT_MASK(ch, bits) ((bits) << (4 * (ch)))
-#define LM4_LPC_LPCDMACX       REG32(0x40080120)
-#define LM4_LPC_CH0_BASE       0x40080010
-#define LM4_LPC_CH1_BASE       0x40080020
-#define LM4_LPC_CH2_BASE       0x40080030
-#define LM4_LPC_CH3_BASE       0x40080040
-#define LM4_LPC_CH4_BASE       0x40080050
-#define LM4_LPC_CH5_BASE       0x40080060
-#define LM4_LPC_CH6_BASE       0x40080070
-#define LM4_LPC_CH7_BASE       0x40080080
-#define LM4_LPC_CH_SEP         0x00000010
-static inline int lm4_lpc_addr(int ch, int offset)
-{
-	return offset + LM4_LPC_CH0_BASE + LM4_LPC_CH_SEP * ch;
-}
-#define LM4LPCREG(ch, offset)  REG32(lm4_lpc_addr(ch, offset))
-#define LM4_LPC_CTL(ch)        LM4LPCREG(ch, 0x000)
-#define LM4_LPC_ST(ch)         LM4LPCREG(ch, 0x004)
-#define LM4_LPC_ST_TOH         BIT(0)  /* TO Host bit */
-#define LM4_LPC_ST_FRMH        BIT(1)  /* FRoM Host bit */
-#define LM4_LPC_ST_CMD         BIT(3)  /* Last from-host byte was command */
-#define LM4_LPC_ST_BURST       BIT(8)
-#define LM4_LPC_ST_SCI         BIT(9)
-#define LM4_LPC_ST_SMI         BIT(10)
-#define LM4_LPC_ST_BUSY        BIT(12)
-#define LM4_LPC_ADR(ch)        LM4LPCREG(ch, 0x008)
-#define LM4_LPC_POOL_BYTES     1024   /* Size of LPCPOOL in bytes */
-#define LM4_LPC_LPCPOOL        ((volatile unsigned char *)0x40080400)
-
-#define LM4_FAN_FANSTS         REG32(0x40084000)
-#define LM4_FAN_FANCTL         REG32(0x40084004)
-#define LM4_FAN_CH0_BASE       0x40084010
-#define LM4_FAN_CH1_BASE       0x40084020
-#define LM4_FAN_CH2_BASE       0x40084030
-#define LM4_FAN_CH3_BASE       0x40084040
-#define LM4_FAN_CH4_BASE       0x40084050
-#define LM4_FAN_CH5_BASE       0x40084060
-#define LM4_FAN_CH_SEP         0x00000010
-static inline int lm4_fan_addr(int ch, int offset)
-{
-	return offset + LM4_FAN_CH0_BASE + LM4_FAN_CH_SEP * ch;
-}
-#define LM4FANREG(ch, offset)  REG32(lm4_fan_addr(ch, offset))
-#define LM4_FAN_FANCH(ch)      LM4FANREG(ch, 0x000)
-#define LM4_FAN_FANCMD(ch)     LM4FANREG(ch, 0x004)
-#define LM4_FAN_FANCST(ch)     LM4FANREG(ch, 0x008)
-
-#define LM4_EEPROM_EESIZE      REG32(0x400af000)
-#define LM4_EEPROM_EEBLOCK     REG32(0x400af004)
-#define LM4_EEPROM_EEOFFSET    REG32(0x400af008)
-#define LM4_EEPROM_EERDWR      REG32(0x400af010)
-#define LM4_EEPROM_EERDWRINC   REG32(0x400af014)
-#define LM4_EEPROM_EEDONE      REG32(0x400af018)
-#define LM4_EEPROM_EESUPP      REG32(0x400af01c)
-#define LM4_EEPROM_EEUNLOCK    REG32(0x400af020)
-#define LM4_EEPROM_EEPROT      REG32(0x400af030)
-#define LM4_EEPROM_EEPASS0     REG32(0x400af034)
-#define LM4_EEPROM_EEPASS1     REG32(0x400af038)
-#define LM4_EEPROM_EEPASS2     REG32(0x400af03c)
-#define LM4_EEPROM_EEINT       REG32(0x400af040)
-#define LM4_EEPROM_EEHIDE      REG32(0x400af050)
-
-#define LM4_PECI_CTL           REG32(0x400b0000)
-#define LM4_PECI_DIV           REG32(0x400b0004)
-#define LM4_PECI_CMP           REG32(0x400b0008)
-#define LM4_PECI_M0D0C         REG32(0x400b0010)
-#define LM4_PECI_M0D1C         REG32(0x400b0014)
-#define LM4_PECI_M1D0C         REG32(0x400b0018)
-#define LM4_PECI_M1D1C         REG32(0x400b001c)
-#define LM4_PECI_M0D0          REG32(0x400b0040)
-#define LM4_PECI_M0D1          REG32(0x400b0044)
-#define LM4_PECI_M1D0          REG32(0x400b0048)
-#define LM4_PECI_M1D1          REG32(0x400b004c)
-#define LM4_PECI_IM            REG32(0x400b0080)
-#define LM4_PECI_RIS           REG32(0x400b0084)
-#define LM4_PECI_MIS           REG32(0x400b0088)
-#define LM4_PECI_IC            REG32(0x400b008c)
-#define LM4_PECI_ACADDR        REG32(0x400b0100)
-#define LM4_PECI_ACARG         REG32(0x400b0104)
-#define LM4_PECI_ACRDWR0       REG32(0x400b0108)
-#define LM4_PECI_ACRDWR1       REG32(0x400b010c)
-#define LM4_PECI_ACCMD         REG32(0x400b0110)
-#define LM4_PECI_ACCODE        REG32(0x400b0114)
-
-
-#define LM4_HIBERNATE_HIBRTCC  REG32(0x400fc000)
-#define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004)
-#define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c)
-#define LM4_HIBERNATE_HIBCTL   REG32(0x400fc010)
-#define LM4_HIBCTL_WRC         BIT(31)
-#define LM4_HIBCTL_CLK32EN     BIT(6)
-#define LM4_HIBCTL_PINWEN      BIT(4)
-#define LM4_HIBCTL_RTCWEN      BIT(3)
-#define LM4_HIBCTL_HIBREQ      BIT(1)
-#define LM4_HIBCTL_RTCEN       BIT(0)
-#define LM4_HIBERNATE_HIBIM    REG32(0x400fc014)
-#define LM4_HIBERNATE_HIBRIS   REG32(0x400fc018)
-#define LM4_HIBERNATE_HIBMIS   REG32(0x400fc01c)
-#define LM4_HIBERNATE_HIBIC    REG32(0x400fc020)
-#define LM4_HIBERNATE_HIBRTCT  REG32(0x400fc024)
-#define LM4_HIBERNATE_HIBRTCSS REG32(0x400fc028)
-#define LM4_HIBERNATE_HIBDATA_ENTRIES 16  /* Number of entries in HIBDATA[] */
-#define LM4_HIBERNATE_HIBDATA  ((volatile uint32_t *)0x400fc030)
-
-#define LM4_FLASH_FMA          REG32(0x400fd000)
-#define LM4_FLASH_FMD          REG32(0x400fd004)
-#define LM4_FLASH_FMC          REG32(0x400fd008)
-#define LM4_FLASH_FCRIS        REG32(0x400fd00c)
-#define LM4_FLASH_FCMISC       REG32(0x400fd014)
-#define LM4_FLASH_FMC2         REG32(0x400fd020)
-#define LM4_FLASH_FWBVAL       REG32(0x400fd030)
-/* FWB size is 32 words = 128 bytes */
-#define LM4_FLASH_FWB          ((volatile uint32_t*)0x400fd100)
-#define LM4_FLASH_FSIZE        REG32(0x400fdfc0)
-#define LM4_FLASH_FMPRE0       REG32(0x400fe200)
-#define LM4_FLASH_FMPRE1       REG32(0x400fe204)
-#define LM4_FLASH_FMPRE2       REG32(0x400fe208)
-#define LM4_FLASH_FMPRE3       REG32(0x400fe20c)
-#define LM4_FLASH_FMPPE        ((volatile uint32_t*)0x400fe400)
-#define LM4_FLASH_FMPPE0       REG32(0x400fe400)
-#define LM4_FLASH_FMPPE1       REG32(0x400fe404)
-#define LM4_FLASH_FMPPE2       REG32(0x400fe408)
-#define LM4_FLASH_FMPPE3       REG32(0x400fe40c)
-
-#define LM4_SYSTEM_DID0        REG32(0x400fe000)
-#define LM4_SYSTEM_DID1        REG32(0x400fe004)
-#define LM4_SYSTEM_PBORCTL     REG32(0x400fe030)
-#define LM4_SYSTEM_RIS         REG32(0x400fe050)
-#define LM4_SYSTEM_MISC        REG32(0x400fe058)
-#define LM4_SYSTEM_RESC        REG32(0x400fe05c)
-#define LM4_SYSTEM_RCC         REG32(0x400fe060)
-#define LM4_SYSTEM_RCC_ACG        BIT(27)
-#define LM4_SYSTEM_RCC_SYSDIV(x)  (((x) & 0xf) << 23)
-#define LM4_SYSTEM_RCC_USESYSDIV  BIT(22)
-#define LM4_SYSTEM_RCC_PWRDN      BIT(13)
-#define LM4_SYSTEM_RCC_BYPASS     BIT(11)
-#define LM4_SYSTEM_RCC_XTAL(x)    (((x) & 0x1f) << 6)
-#define LM4_SYSTEM_RCC_OSCSRC(x)  (((x) & 0x3) << 4)
-#define LM4_SYSTEM_RCC_IOSCDIS    BIT(1)
-#define LM4_SYSTEM_RCC_MOSCDIS    BIT(0)
-#define LM4_SYSTEM_RCC2        REG32(0x400fe070)
-#define LM4_SYSTEM_RCC2_USERCC2     BIT(31)
-#define LM4_SYSTEM_RCC2_DIV400      BIT(30)
-#define LM4_SYSTEM_RCC2_SYSDIV2(x)  (((x) & 0x3f) << 23)
-#define LM4_SYSTEM_RCC2_SYSDIV2LSB  BIT(22)
-#define LM4_SYSTEM_RCC2_PWRDN2      BIT(13)
-#define LM4_SYSTEM_RCC2_BYPASS2     BIT(11)
-#define LM4_SYSTEM_RCC2_OSCSRC2(x)  (((x) & 0x7) << 4)
-#define LM4_SYSTEM_MOSCCTL     REG32(0x400fe07c)
-#define LM4_SYSTEM_DSLPCLKCFG  REG32(0x400fe144)
-#define LM4_SYSTEM_PIOSCCAL    REG32(0x400fe150)
-#define LM4_SYSTEM_PIOSCSTAT   REG32(0x400fe154)
-#define LM4_SYSTEM_PLLSTAT     REG32(0x400fe168)
-#define LM4_SYSTEM_SLPPWRCFG   REG32(0x400fe188)
-#define LM4_SYSTEM_DSLPPWRCFG  REG32(0x400fe18c)
-#define LM4_SYSTEM_LDOSPCTL    REG32(0x400fe1b4)
-#define LM4_SYSTEM_LDOSPCAL    REG32(0x400fe1b8)
-#define LM4_SYSTEM_LDODPCTL    REG32(0x400fe1bc)
-#define LM4_SYSTEM_LDODPCAL    REG32(0x400fe1c0)
-#define LM4_SYSTEM_SPDMST      REG32(0x400fe1cc)
-#define LM4_SYSTEM_BOOTCFG     REG32(0x400fe1d0)
-#define LM4_SYSTEM_BOOTCFG_MASK 0x7fff00ec /* Reserved bits of BOOTCFG reg */
-/* Note: USER_REG3 is used to hold pre-programming process data and should not
- * be modified by EC code.  See crosbug.com/p/8889. */
-#define LM4_SYSTEM_USER_REG3   REG32(0x400fe1ec)
-#define LM4_SYSTEM_SRI2C       REG32(0x400fe520)
-#define LM4_SYSTEM_SREEPROM    REG32(0x400fe558)
-
-#define LM4_SYSTEM_SRI2C_ADDR  ((uint32_t *)0x400fe520)
-
-#define LM4_SYSTEM_RCGC_BASE   ((volatile uint32_t *)0x400fe600)
-#define LM4_SYSTEM_RCGCGPIO    REG32(0x400fe608)
-#define LM4_SYSTEM_SCGC_BASE   ((volatile uint32_t *)0x400fe700)
-#define LM4_SYSTEM_DCGC_BASE   ((volatile uint32_t *)0x400fe800)
-
-/*
- * Offsets from CGC_BASE registers for each peripheral.
- * Note: these are in units of 32-bit words offset from
- * the base address.
- */
-enum clock_gate_offsets {
-	CGC_OFFSET_WD =        0,
-	CGC_OFFSET_TIMER =     1,
-	CGC_OFFSET_GPIO =      2,
-	CGC_OFFSET_DMA =       3,
-	CGC_OFFSET_HIB =       5,
-	CGC_OFFSET_UART =      6,
-	CGC_OFFSET_SSI =       7,
-	CGC_OFFSET_I2C =       8,
-	CGC_OFFSET_ADC =       14,
-	CGC_OFFSET_LPC =       18,
-	CGC_OFFSET_PECI =      20,
-	CGC_OFFSET_FAN =       21,
-	CGC_OFFSET_EEPROM =    22,
-	CGC_OFFSET_WTIMER =    23,
-};
-
-#define LM4_SYSTEM_PREEPROM    REG32(0x400fea58)
-
-#define LM4_DMA_DMACFG         REG32(0x400ff004)
-#define LM4_DMA_DMACTLBASE     REG32(0x400ff008)
-#define LM4_DMA_DMACHMAP0      REG32(0x400ff510)
-#define LM4_DMA_DMACHMAP1      REG32(0x400ff514)
-#define LM4_DMA_DMACHMAP2      REG32(0x400ff518)
-#define LM4_DMA_DMACHMAP3      REG32(0x400ff51c)
-
-/* IRQ numbers */
-#define LM4_IRQ_GPIOA            0
-#define LM4_IRQ_GPIOB            1
-#define LM4_IRQ_GPIOC            2
-#define LM4_IRQ_GPIOD            3
-#define LM4_IRQ_GPIOE            4
-#define LM4_IRQ_UART0            5
-#define LM4_IRQ_UART1            6
-#define LM4_IRQ_SSI0             7
-#define LM4_IRQ_I2C0             8
-/* 9 - 13 reserved */
-#define LM4_IRQ_ADC0_SS0        14
-#define LM4_IRQ_ADC0_SS1        15
-#define LM4_IRQ_ADC0_SS2        16
-#define LM4_IRQ_ADC0_SS3        17
-#define LM4_IRQ_WATCHDOG        18
-#define LM4_IRQ_TIMER0A         19
-#define LM4_IRQ_TIMER0B         20
-#define LM4_IRQ_TIMER1A         21
-#define LM4_IRQ_TIMER1B         22
-#define LM4_IRQ_TIMER2A         23
-#define LM4_IRQ_TIMER2B         24
-#define LM4_IRQ_ACMP0           25
-#define LM4_IRQ_ACMP1           26
-#define LM4_IRQ_ACMP2           27
-#define LM4_IRQ_SYSCTRL         28
-#define LM4_IRQ_EEPROM          29
-#define LM4_IRQ_GPIOF           30
-#define LM4_IRQ_GPIOG           31
-#define LM4_IRQ_GPIOH           32
-#define LM4_IRQ_UART2           33
-#define LM4_IRQ_SSI1            34
-#define LM4_IRQ_TIMER3A         35
-#define LM4_IRQ_TIMER3B         36
-#define LM4_IRQ_I2C1            37
-/* 38 - 42 reserved */
-#define LM4_IRQ_HIBERNATE       43
-/* 44 - 45 reserved */
-#define LM4_IRQ_UDMA_SOFTWARE   46
-#define LM4_IRQ_UDMA_ERROR      47
-#define LM4_IRQ_ADC1_SS0        48
-#define LM4_IRQ_ADC1_SS1        49
-#define LM4_IRQ_ADC1_SS2        50
-#define LM4_IRQ_ADC1_SS3        51
-/* 52 - 53 reserved */
-#define LM4_IRQ_GPIOJ           54
-#define LM4_IRQ_GPIOK           55
-#define LM4_IRQ_GPIOL           56
-#define LM4_IRQ_SSI2            57
-#define LM4_IRQ_SSI3            58
-#define LM4_IRQ_UART3           59
-#define LM4_IRQ_UART4           60
-#define LM4_IRQ_UART5           61
-#define LM4_IRQ_UART6           62
-#define LM4_IRQ_UART7           63
-/* 64 - 67 reserved */
-#define LM4_IRQ_I2C2            68
-#define LM4_IRQ_I2C3            69
-#define LM4_IRQ_TIMER4A         70
-#define LM4_IRQ_TIMER4B         71
-/* 72 - 91 reserved */
-#define LM4_IRQ_TIMER5A         92
-#define LM4_IRQ_TIMER5B         93
-#define LM4_IRQ_TIMERW0A        94
-#define LM4_IRQ_TIMERW0B        95
-#define LM4_IRQ_TIMERW1A        96
-#define LM4_IRQ_TIMERW1B        97
-#define LM4_IRQ_TIMERW2A        98
-#define LM4_IRQ_TIMERW2B        99
-#define LM4_IRQ_TIMERW3A       100
-#define LM4_IRQ_TIMERW3B       101
-#define LM4_IRQ_TIMERW4A       102
-#define LM4_IRQ_TIMERW4B       103
-#define LM4_IRQ_TIMERW5A       104
-#define LM4_IRQ_TIMERW5B       105
-#define LM4_IRQ_SYS_EXCEPTION  106
-#define LM4_IRQ_SYS_PECI       107
-#define LM4_IRQ_LPC            108
-#define LM4_IRQ_I2C4           109
-#define LM4_IRQ_I2C5           110
-#define LM4_IRQ_GPIOM          111
-#define LM4_IRQ_GPION          112
-/* 113 reserved */
-#define LM4_IRQ_FAN            114
-/* 115 reserved */
-#define LM4_IRQ_GPIOP          116
-#define LM4_IRQ_GPIOP1         117
-#define LM4_IRQ_GPIOP2         118
-#define LM4_IRQ_GPIOP3         119
-#define LM4_IRQ_GPIOP4         120
-#define LM4_IRQ_GPIOP5         121
-#define LM4_IRQ_GPIOP6         122
-#define LM4_IRQ_GPIOP7         123
-#define LM4_IRQ_GPIOQ          124
-#define LM4_IRQ_GPIOQ1         125
-#define LM4_IRQ_GPIOQ2         126
-#define LM4_IRQ_GPIOQ3         127
-#define LM4_IRQ_GPIOQ4         128
-#define LM4_IRQ_GPIOQ5         129
-#define LM4_IRQ_GPIOQ6         130
-#define LM4_IRQ_GPIOQ7         131
-/* 132 - 138 reserved */
-
-/* GPIO */
-#define LM4_GPIO_PORTA_BASE         0x40004000
-#define LM4_GPIO_PORTB_BASE         0x40005000
-#define LM4_GPIO_PORTC_BASE         0x40006000
-#define LM4_GPIO_PORTD_BASE         0x40007000
-#define LM4_GPIO_PORTE_BASE         0x40024000
-#define LM4_GPIO_PORTF_BASE         0x40025000
-#define LM4_GPIO_PORTG_BASE         0x40026000
-#define LM4_GPIO_PORTH_BASE         0x40027000
-#define LM4_GPIO_PORTJ_BASE         0x4003d000
-#define LM4_GPIO_PORTK_BASE         0x40061000
-#define LM4_GPIO_PORTL_BASE         0x40062000
-#define LM4_GPIO_PORTM_BASE         0x40063000
-#define LM4_GPIO_PORTN_BASE         0x40064000
-#define LM4_GPIO_PORTP_BASE         0x40065000
-#define LM4_GPIO_PORTQ_BASE         0x40066000
-#define LM4_GPIO_PORTA_AHB_BASE     0x40058000
-#define LM4_GPIO_PORTB_AHB_BASE     0x40059000
-#define LM4_GPIO_PORTC_AHB_BASE     0x4005a000
-#define LM4_GPIO_PORTD_AHB_BASE     0x4005b000
-#define LM4_GPIO_PORTE_AHB_BASE     0x4005c000
-#define LM4_GPIO_PORTF_AHB_BASE     0x4005d000
-#define LM4_GPIO_PORTG_AHB_BASE     0x4005e000
-#define LM4_GPIO_PORTH_AHB_BASE     0x4005f000
-#define LM4_GPIO_PORTJ_AHB_BASE     0x40060000
-/* Ports for passing to LM4GPIOREG(); abstracted from base addresses above so
- * that we can switch to/from AHB. */
-#define LM4_GPIO_A LM4_GPIO_PORTA_BASE
-#define LM4_GPIO_B LM4_GPIO_PORTB_BASE
-#define LM4_GPIO_C LM4_GPIO_PORTC_BASE
-#define LM4_GPIO_D LM4_GPIO_PORTD_BASE
-#define LM4_GPIO_E LM4_GPIO_PORTE_BASE
-#define LM4_GPIO_F LM4_GPIO_PORTF_BASE
-#define LM4_GPIO_G LM4_GPIO_PORTG_BASE
-#define LM4_GPIO_H LM4_GPIO_PORTH_BASE
-#define LM4_GPIO_J LM4_GPIO_PORTJ_BASE
-#define LM4_GPIO_K LM4_GPIO_PORTK_BASE
-#define LM4_GPIO_L LM4_GPIO_PORTL_BASE
-#define LM4_GPIO_M LM4_GPIO_PORTM_BASE
-#define LM4_GPIO_N LM4_GPIO_PORTN_BASE
-#define LM4_GPIO_P LM4_GPIO_PORTP_BASE
-#define LM4_GPIO_Q LM4_GPIO_PORTQ_BASE
-#define LM4GPIOREG(port, offset)      REG32((port) + (offset))
-#define LM4_GPIO_DATA(port, mask)     LM4GPIOREG(port, ((mask) << 2))
-#define LM4_GPIO_DIR(port)            LM4GPIOREG(port, 0x400)
-#define LM4_GPIO_IS(port)             LM4GPIOREG(port, 0x404)
-#define LM4_GPIO_IBE(port)            LM4GPIOREG(port, 0x408)
-#define LM4_GPIO_IEV(port)            LM4GPIOREG(port, 0x40c)
-#define LM4_GPIO_IM(port)             LM4GPIOREG(port, 0x410)
-#define LM4_GPIO_RIS(port)            LM4GPIOREG(port, 0x414)
-#define LM4_GPIO_MIS(port)            LM4GPIOREG(port, 0x418)
-#define LM4_GPIO_ICR(port)            LM4GPIOREG(port, 0x41c)
-#define LM4_GPIO_AFSEL(port)          LM4GPIOREG(port, 0x420)
-#define LM4_GPIO_DR2R(port)           LM4GPIOREG(port, 0x500)
-#define LM4_GPIO_DR4R(port)           LM4GPIOREG(port, 0x504)
-#define LM4_GPIO_DR8R(port)           LM4GPIOREG(port, 0x508)
-#define LM4_GPIO_ODR(port)            LM4GPIOREG(port, 0x50c)
-#define LM4_GPIO_PUR(port)            LM4GPIOREG(port, 0x510)
-#define LM4_GPIO_PDR(port)            LM4GPIOREG(port, 0x514)
-#define LM4_GPIO_SLR(port)            LM4GPIOREG(port, 0x518)
-#define LM4_GPIO_DEN(port)            LM4GPIOREG(port, 0x51c)
-#define LM4_GPIO_LOCK(port)           LM4GPIOREG(port, 0x520)
-#define LM4_GPIO_CR(port)             LM4GPIOREG(port, 0x524)
-#define LM4_GPIO_AMSEL(port)          LM4GPIOREG(port, 0x528)
-#define LM4_GPIO_PCTL(port)           LM4GPIOREG(port, 0x52c)
-
-/* Chip-independent aliases for port base addresses */
-#define GPIO_A LM4_GPIO_A
-#define GPIO_B LM4_GPIO_B
-#define GPIO_C LM4_GPIO_C
-#define GPIO_D LM4_GPIO_D
-#define GPIO_E LM4_GPIO_E
-#define GPIO_F LM4_GPIO_F
-#define GPIO_G LM4_GPIO_G
-#define GPIO_H LM4_GPIO_H
-#define GPIO_J LM4_GPIO_J
-#define GPIO_K LM4_GPIO_K
-#define GPIO_L LM4_GPIO_L
-#define GPIO_M LM4_GPIO_M
-#define GPIO_N LM4_GPIO_N
-#define GPIO_P LM4_GPIO_P
-#define GPIO_Q LM4_GPIO_Q
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-/* Value to write to LM4_GPIO_LOCK to unlock writes */
-#define LM4_GPIO_LOCK_UNLOCK          0x4c4f434b
-
-/* I2C */
-#define LM4_I2C0_BASE                 0x40020000
-#define LM4_I2C1_BASE                 0x40021000
-#define LM4_I2C2_BASE                 0x40022000
-#define LM4_I2C3_BASE                 0x40023000
-#define LM4_I2C4_BASE                 0x400c0000
-#define LM4_I2C5_BASE                 0x400c1000
-#define LM4_I2C_BASESEP               0x00001000
-/* I2C base address by port.  Compiles to a constant in gcc if port
-   and offset are constant. */
-static inline int lm4_i2c_addr(int port, int offset)
-{
-	return offset + (port < 4 ?
-			 LM4_I2C0_BASE + LM4_I2C_BASESEP * port :
-			 LM4_I2C4_BASE + LM4_I2C_BASESEP * (port - 4));
-}
-#define LM4I2CREG(port, offset)       REG32(lm4_i2c_addr(port, offset))
-#define LM4_I2C_MSA(port)             LM4I2CREG(port, 0x000)
-#define LM4_I2C_MCS(port)             LM4I2CREG(port, 0x004)
-#define LM4_I2C_MDR(port)             LM4I2CREG(port, 0x008)
-#define LM4_I2C_MTPR(port)            LM4I2CREG(port, 0x00c)
-#define LM4_I2C_MIMR(port)            LM4I2CREG(port, 0x010)
-#define LM4_I2C_MRIS(port)            LM4I2CREG(port, 0x014)
-#define LM4_I2C_MMIS(port)            LM4I2CREG(port, 0x018)
-#define LM4_I2C_MICR(port)            LM4I2CREG(port, 0x01c)
-#define LM4_I2C_MCR(port)             LM4I2CREG(port, 0x020)
-#define LM4_I2C_MCLKOCNT(port)        LM4I2CREG(port, 0x024)
-#define LM4_I2C_MBMON(port)           LM4I2CREG(port, 0x02c)
-
-
-/* Timers */
-/* Timers 0-5 are 16/32 bit */
-#define LM4_TIMER0_BASE                 0x40030000
-#define LM4_TIMER1_BASE                 0x40031000
-#define LM4_TIMER2_BASE                 0x40032000
-#define LM4_TIMER3_BASE                 0x40033000
-#define LM4_TIMER4_BASE                 0x40034000
-#define LM4_TIMER5_BASE                 0x40035000
-/* Timers 6-11 are 32/64 bit */
-#define LM4_TIMERW0_BASE                0x40036000
-#define LM4_TIMERW1_BASE                0x40037000
-#define LM4_TIMERW2_BASE                0x4004c000
-#define LM4_TIMERW3_BASE                0x4004d000
-#define LM4_TIMERW4_BASE                0x4004e000
-#define LM4_TIMERW5_BASE                0x4004f000
-#define LM4_TIMER_SEP                   0x00001000
-static inline int lm4_timer_addr(int timer, int offset)
-{
-	if (timer < 8)
-		return offset + LM4_TIMER0_BASE + LM4_TIMER_SEP * timer;
-	else
-		return offset + LM4_TIMERW2_BASE + LM4_TIMER_SEP * (timer - 8);
-}
-#define LM4TIMERREG(timer, offset)      REG32(lm4_timer_addr(timer, offset))
-#define LM4_TIMER_CFG(tmr)              LM4TIMERREG(tmr, 0x00)
-#define LM4_TIMER_TAMR(tmr)             LM4TIMERREG(tmr, 0x04)
-#define LM4_TIMER_TBMR(tmr)             LM4TIMERREG(tmr, 0x08)
-#define LM4_TIMER_CTL(tmr)              LM4TIMERREG(tmr, 0x0c)
-#define LM4_TIMER_SYNC(tmr)             LM4TIMERREG(tmr, 0x10)
-#define LM4_TIMER_IMR(tmr)              LM4TIMERREG(tmr, 0x18)
-#define LM4_TIMER_RIS(tmr)              LM4TIMERREG(tmr, 0x1c)
-#define LM4_TIMER_MIS(tmr)              LM4TIMERREG(tmr, 0x20)
-#define LM4_TIMER_ICR(tmr)              LM4TIMERREG(tmr, 0x24)
-#define LM4_TIMER_TAILR(tmr)            LM4TIMERREG(tmr, 0x28)
-#define LM4_TIMER_TBILR(tmr)            LM4TIMERREG(tmr, 0x2c)
-#define LM4_TIMER_TAMATCHR(tmr)         LM4TIMERREG(tmr, 0x30)
-#define LM4_TIMER_TBMATCHR(tmr)         LM4TIMERREG(tmr, 0x34)
-#define LM4_TIMER_TAPR(tmr)             LM4TIMERREG(tmr, 0x38)
-#define LM4_TIMER_TBPR(tmr)             LM4TIMERREG(tmr, 0x3c)
-#define LM4_TIMER_TAPMR(tmr)            LM4TIMERREG(tmr, 0x40)
-#define LM4_TIMER_TBPMR(tmr)            LM4TIMERREG(tmr, 0x44)
-#define LM4_TIMER_TAR(tmr)              LM4TIMERREG(tmr, 0x48)
-#define LM4_TIMER_TBR(tmr)              LM4TIMERREG(tmr, 0x4c)
-#define LM4_TIMER_TAV(tmr)              LM4TIMERREG(tmr, 0x50)
-#define LM4_TIMER_TBV(tmr)              LM4TIMERREG(tmr, 0x54)
-#define LM4_TIMER_RTCPD(tmr)            LM4TIMERREG(tmr, 0x58)
-#define LM4_TIMER_TAPS(tmr)             LM4TIMERREG(tmr, 0x5c)
-#define LM4_TIMER_TBPS(tmr)             LM4TIMERREG(tmr, 0x60)
-#define LM4_TIMER_TAPV(tmr)             LM4TIMERREG(tmr, 0x64)
-#define LM4_TIMER_TBPV(tmr)             LM4TIMERREG(tmr, 0x68)
-
-#define LM4_SYSTICK_CTRL                REG32(0xe000e010)
-#define LM4_SYSTICK_RELOAD              REG32(0xe000e014)
-#define LM4_SYSTICK_CURRENT             REG32(0xe000e018)
-
-/* Watchdogs */
-#define LM4_WATCHDOG0_BASE              0x40000000
-#define LM4_WATCHDOG1_BASE              0x40001000
-static inline int lm4_watchdog_addr(int num, int offset)
-{
-	return offset + (num ? LM4_WATCHDOG1_BASE : LM4_WATCHDOG0_BASE);
-}
-#define LM4WDTREG(num, offset)		REG32(lm4_watchdog_addr(num, offset))
-#define LM4_WATCHDOG_LOAD(n)            LM4WDTREG(n, 0x000)
-#define LM4_WATCHDOG_VALUE(n)           LM4WDTREG(n, 0x004)
-#define LM4_WATCHDOG_CTL(n)             LM4WDTREG(n, 0x008)
-#define LM4_WATCHDOG_ICR(n)             LM4WDTREG(n, 0x00c)
-#define LM4_WATCHDOG_RIS(n)             LM4WDTREG(n, 0x010)
-#define LM4_WATCHDOG_TEST(n)            LM4WDTREG(n, 0x418)
-#define LM4_WATCHDOG_LOCK(n)            LM4WDTREG(n, 0xc00)
-
-#define LM4_TEST_MODE_ENABLED		REG32(0x400fdff0)
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c
deleted file mode 100644
index 629e306af7..0000000000
--- a/chip/lm4/spi.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-		/*
-		 * Don't use the SSI0 frame output.
-		 * CS# is a GPIO so we can keep it low during an entire
-		 * transaction.
-		 */
-		gpio_set_flags(spi_device->gpio_cs, GPIO_OUTPUT);
-		gpio_set_level(spi_device->gpio_cs, 1);
-
-		/* Enable SSI port */
-		LM4_SSI_CR1(0) |= 0x02;
-	} else {
-		/* Disable SSI port */
-		LM4_SSI_CR1(0) &= ~0x02;
-
-		/* Make sure CS# is deselected */
-		gpio_set_level(spi_device->gpio_cs, 1);
-		gpio_set_flags(spi_device->gpio_cs[i], GPIO_ODR_HIGH);
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int totallen = txlen + rxlen;
-	int txcount = 0, rxcount = 0;
-	static struct mutex spi_mutex;
-	volatile uint32_t unused  __attribute__((unused));
-
-	mutex_lock(&spi_mutex);
-	/* Empty the receive FIFO */
-	while (LM4_SSI_SR(0) & LM4_SSI_SR_RNE)
-		unused = LM4_SSI_DR(0);
-
-	/* Start transaction.  Need to do this explicitly because the LM4
-	 * SSI controller pulses its frame select every byte, and the EEPROM
-	 * wants the chip select held low during the entire transaction. */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	while (rxcount < totallen) {
-		/* Handle received bytes if any.  We just checked rxcount <
-		 * totallen, so we don't need to worry about overflowing the
-		 * receive buffer. */
-		if (LM4_SSI_SR(0) & LM4_SSI_SR_RNE) {
-			if (rxcount < txlen) {
-				/* Throw away bytes received while we were
-				   transmitting */
-				unused = LM4_SSI_DR(0);
-			} else
-				*(rxdata++) = LM4_SSI_DR(0);
-			rxcount++;
-		}
-
-		/* Transmit another byte if needed */
-		if ((LM4_SSI_SR(0) & LM4_SSI_SR_TNF) && txcount < totallen) {
-			if (txcount < txlen)
-				LM4_SSI_DR(0) = *(txdata++);
-			else {
-				/* Clock out unused byte so we can clock in the
-				 * response byte */
-				LM4_SSI_DR(0) = 0;
-			}
-			txcount++;
-		}
-	}
-
-	/* End transaction */
-	gpio_set_level(spi_device->gpio_cs, 1);
-	mutex_unlock(&spi_mutex);
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static int spi_init(void)
-{
-	/* Enable the SPI module in run and sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_SSI, 0x1,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	LM4_SSI_CR1(0) = 0;       /* Disable SSI */
-	LM4_SSI_CR0(0) = 0x0007;  /* SCR=0, SPH=0, SPO=0, FRF=SPI, 8-bit */
-
-	/* Use PIOSC for clock.  This limits us to 8MHz (PIOSC/2), but is
-	 * simpler to configure and we don't need to worry about clock
-	 * frequency changing when the PLL is disabled.  If we really start
-	 * using this, might be worth using the system clock and handling
-	 * frequency change (like we do with PECI) so we can go faster. */
-	LM4_SSI_CC(0) = 1;
-	/* SSICLK = PIOSC / (CPSDVSR * (1 + SCR)
-	 *        = 16 MHz / (2 * (1 + 0))
-	 *        = 8 MHz */
-	LM4_SSI_CPSR(0) = 2;
-
-	/* Ensure the SPI port is disabled.  This keeps us from interfering
-	 * with the main chipset when we're not explicitly using the SPI
-	 * bus. */
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		   int rxlen)
-{
-	uint8_t rxdata[32];
-	int rv;
-	int i;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
-	if (rv)
-		return rv;
-
-	ccprintf("%-12s:", desc);
-	for (i = 0; i < rxlen; i++)
-		ccprintf(" 0x%02x", rxdata[i]);
-	ccputs("\n");
-	return EC_SUCCESS;
-}
-
-
-static int command_spirom(int argc, char **argv)
-{
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
-	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
-	printrx("Unique ID", txunique, sizeof(txunique), 8);
-	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
-	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
-
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-			NULL,
-			"Test reading SPI EEPROM");
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
deleted file mode 100644
index 56bd1a82fd..0000000000
--- a/chip/lm4/system.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : LM4 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Indices for hibernate data registers */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD,           /* General-purpose scratchpad */
-	HIBDATA_INDEX_WAKE,                 /* Wake reasons for hibernate */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS,    /* Saved reset flags */
-#ifdef CONFIG_SOFTWARE_PANIC
-	HIBDATA_INDEX_SAVED_PANIC_REASON,   /* Saved panic reason */
-	HIBDATA_INDEX_SAVED_PANIC_INFO,     /* Saved panic data */
-	HIBDATA_INDEX_SAVED_PANIC_EXCEPTION,/* Saved panic exception code */
-	HIBDATA_INDEX_SAVED_PANIC_FLAGS,    /* Saved panic flags */
-#endif
-};
-
-/* Flags for HIBDATA_INDEX_WAKE */
-#define HIBDATA_WAKE_RTC        BIT(0)  /* RTC alarm */
-#define HIBDATA_WAKE_HARD_RESET BIT(1)  /* Hard reset via short RTC alarm */
-#define HIBDATA_WAKE_PIN        BIT(2)  /* Wake pin */
-
-/*
- * Time to hibernate to trigger a power-on reset.  50 ms is sufficient for the
- * EC itself, but we need a longer delay to ensure the rest of the components
- * on the same power rail are reset and 5VALW has dropped.
- */
-#define HIB_RESET_USEC 1000000
-
-/*
- * Convert between microseconds and the hibernation module RTC subsecond
- * register which has 15-bit resolution. Divide down both numerator and
- * denominator to avoid integer overflow while keeping the math accurate.
- */
-#define HIB_RTC_USEC_TO_SUBSEC(us) ((us) * (32768/64) / (1000000/64))
-#define HIB_RTC_SUBSEC_TO_USEC(ss) ((ss) * (1000000/64) / (32768/64))
-
-/**
- * Wait for a write to commit to a hibernate register.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-static int wait_for_hibctl_wc(void)
-{
-	int i;
-
-	/* Wait for write-capable */
-	for (i = 0; i < 1000000; i++) {
-		if (LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_WRC)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-/**
- * Read hibernate register at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-static uint32_t hibdata_read(enum hibdata_index index)
-{
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return 0;
-
-	return LM4_HIBERNATE_HIBDATA[index];
-}
-
-/**
- * Write hibernate register at specified index.
- *
- * @return nonzero if error.
- */
-static int hibdata_write(enum hibdata_index index, uint32_t value)
-{
-	int rv;
-
-	if (index < 0 || index >= LM4_HIBERNATE_HIBDATA_ENTRIES)
-		return EC_ERROR_INVAL;
-
-	/* Wait for ok-to-write */
-	rv = wait_for_hibctl_wc();
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Write register */
-	LM4_HIBERNATE_HIBDATA[index] = value;
-
-	/* Wait for write-complete */
-	return wait_for_hibctl_wc();
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return hibdata_read(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	hibdata_write(HIBDATA_INDEX_SAVED_RESET_FLAGS, flags);
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t hib_status = LM4_HIBERNATE_HIBRIS;
-	uint32_t raw_reset_cause = LM4_SYSTEM_RESC;
-	uint32_t hib_wake_flags = hibdata_read(HIBDATA_INDEX_WAKE);
-	uint32_t flags = 0;
-
-	/* Clear the reset causes now that we've read them */
-	LM4_SYSTEM_RESC = 0;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = hib_status;
-	hibdata_write(HIBDATA_INDEX_WAKE, 0);
-
-	if (raw_reset_cause & 0x02) {
-		/*
-		 * Full power-on reset of chip.  This resets the flash
-		 * protection registers to their permanently-stored values.
-		 * Note that this is also triggered by hibernation, because
-		 * that de-powers the chip.
-		 */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	} else if (!flags && (raw_reset_cause & 0x01)) {
-		/*
-		 * LM4 signals the reset pin in RESC for all power-on resets,
-		 * even though the external pin wasn't asserted.  Make setting
-		 * this flag mutually-exclusive with power on flag, so we can
-		 * use it to indicate a keyboard-triggered reset.
-		 */
-		flags |= EC_RESET_FLAG_RESET_PIN;
-	}
-
-	if (raw_reset_cause & 0x04)
-		flags |= EC_RESET_FLAG_BROWNOUT;
-
-	if (raw_reset_cause & 0x10)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_reset_cause & 0x28) {
-		/* Watchdog timer 0 or 1 */
-		flags |= EC_RESET_FLAG_WATCHDOG;
-	}
-
-	/* Handle other raw reset causes */
-	if (raw_reset_cause && !flags)
-		flags |= EC_RESET_FLAG_OTHER;
-
-
-	if ((hib_status & 0x09) &&
-	    (hib_wake_flags & HIBDATA_WAKE_HARD_RESET)) {
-		/* Hibernation caused by software-triggered hard reset */
-		flags |= EC_RESET_FLAG_HARD;
-
-		/* Consume the hibernate reasons so we don't see them below */
-		hib_status &= ~0x09;
-	}
-
-	if ((hib_status & 0x01) && (hib_wake_flags & HIBDATA_WAKE_RTC))
-		flags |= EC_RESET_FLAG_RTC_ALARM;
-
-	if ((hib_status & 0x08) && (hib_wake_flags & HIBDATA_WAKE_PIN))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (hib_status & 0x04)
-		flags |= EC_RESET_FLAG_LOW_BATTERY;
-
-	/* Restore then clear saved reset flags */
-	flags |= chip_read_reset_flags();
-	chip_save_reset_flags(0);
-
-	system_set_reset_flags(flags);
-}
-
-/*
- * A3 and earlier chip stepping has a problem accessing flash during shutdown.
- * To work around that, we jump to RAM before hibernating.  This function must
- * live in RAM.  It must be called with interrupts disabled, cannot call other
- * functions, and can't be declared static (or else the compiler optimizes it
- * into the main hibernate function.
- */
-void  __attribute__((noinline)) __attribute__((section(".iram.text")))
-__enter_hibernate(int hibctl)
-{
-	LM4_HIBERNATE_HIBCTL = hibctl;
-	while (1)
-		;
-}
-
-/**
- * Read the real-time clock.
- *
- * @param ss_ptr       Destination for sub-seconds value, if not null.
- *
- * @return the real-time clock seconds value.
- */
-uint32_t system_get_rtc_sec_subsec(uint32_t *ss_ptr)
-{
-	uint32_t rtc, rtc2;
-	uint32_t rtcss, rtcss2;
-
-	/*
-	 * The hibernate module isn't synchronized, so need to read repeatedly
-	 * to guarantee a valid read.
-	 */
-	do {
-		rtc = LM4_HIBERNATE_HIBRTCC;
-		rtcss = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtcss2 = LM4_HIBERNATE_HIBRTCSS & 0x7fff;
-		rtc2 = LM4_HIBERNATE_HIBRTCC;
-	} while (rtc != rtc2 || rtcss != rtcss2);
-
-	if (ss_ptr)
-		*ss_ptr = rtcss;
-
-	return rtc;
-}
-
-timestamp_t system_get_rtc(void)
-{
-	uint32_t rtc, rtc_ss;
-	timestamp_t time;
-
-	rtc = system_get_rtc_sec_subsec(&rtc_ss);
-
-	time.val = ((uint64_t)rtc) * SECOND + HIB_RTC_SUBSEC_TO_USEC(rtc_ss);
-	return time;
-}
-
-/**
- * Set the real-time clock.
- *
- * @param seconds	New clock value.
- */
-void system_set_rtc(uint32_t seconds)
-{
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCLD = seconds;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Set the hibernate RTC match time at a given time from now
- *
- * @param seconds      Number of seconds from now for RTC match
- * @param microseconds Number of microseconds from now for RTC match
- */
-static void set_hibernate_rtc_match_time(uint32_t seconds,
-					uint32_t microseconds)
-{
-	uint32_t rtc, rtcss;
-
-	/*
-	 * Make sure that the requested delay is not less then the
-	 * amount of time it takes to set the RTC match registers,
-	 * otherwise, the match event could be missed.
-	 */
-	if (seconds == 0 && microseconds < HIB_SET_RTC_MATCH_DELAY_USEC)
-		microseconds = HIB_SET_RTC_MATCH_DELAY_USEC;
-
-	/* Calculate the wake match */
-	rtc = system_get_rtc_sec_subsec(&rtcss) + seconds;
-	rtcss += HIB_RTC_USEC_TO_SUBSEC(microseconds);
-	if (rtcss > 0x7fff) {
-		rtc += rtcss >> 15;
-		rtcss &= 0x7fff;
-	}
-
-	/* Set RTC alarm match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCM0 = rtc;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCSS = rtcss << 16;
-	wait_for_hibctl_wc();
-}
-
-/**
- * Use hibernate module to set up an RTC interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before RTC interrupt
- * @param microseconds Number of microseconds before RTC interrupt
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Set match time */
-	set_hibernate_rtc_match_time(seconds, microseconds);
-
-	/* Enable RTC interrupt on match */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 1;
-
-	/*
-	 * Wait for the write to commit.  This ensures that the RTC interrupt
-	 * actually gets enabled.  This is important if we're about to switch
-	 * the system to the 30 kHz oscillator, which might prevent the write
-	 * from committing.
-	 */
-	wait_for_hibctl_wc();
-}
-
-/**
- * Disable and clear the RTC interrupt.
- */
-void system_reset_rtc_alarm(void)
-{
-	/* Disable hibernate interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	/* Clear interrupts */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-}
-
-/**
- * Hibernate module interrupt
- */
-void __hibernate_irq(void)
-{
-	system_reset_rtc_alarm();
-}
-DECLARE_IRQ(LM4_IRQ_HIBERNATE, __hibernate_irq, 1);
-
-/**
- * Enable hibernate interrupt
- */
-void system_enable_hib_interrupt(void)
-{
-	task_enable_irq(LM4_IRQ_HIBERNATE);
-}
-
-/**
- * Internal hibernate function.
- *
- * @param seconds      Number of seconds to sleep before RTC alarm
- * @param microseconds Number of microseconds to sleep before RTC alarm
- * @param flags        Additional hibernate wake flags
- */
-static void hibernate(uint32_t seconds, uint32_t microseconds, uint32_t flags)
-{
-	uint32_t hibctl;
-
-	/* Set up wake reasons and hibernate flags */
-	hibctl = LM4_HIBERNATE_HIBCTL | LM4_HIBCTL_PINWEN;
-
-	if (flags & HIBDATA_WAKE_PIN)
-		hibctl |= LM4_HIBCTL_PINWEN;
-	else
-		hibctl &= ~LM4_HIBCTL_PINWEN;
-
-	if (seconds || microseconds) {
-		hibctl |= LM4_HIBCTL_RTCWEN;
-		flags |= HIBDATA_WAKE_RTC;
-
-		set_hibernate_rtc_match_time(seconds, microseconds);
-
-		/* Enable RTC interrupt on match */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBIM = 1;
-	} else {
-		hibctl &= ~LM4_HIBCTL_RTCWEN;
-	}
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/* Clear pending interrupt */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIC = LM4_HIBERNATE_HIBRIS;
-
-	/* Store hibernate flags */
-	hibdata_write(HIBDATA_INDEX_WAKE, flags);
-
-	__enter_hibernate(hibctl | LM4_HIBCTL_HIBREQ);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-	hibernate(seconds, microseconds, HIBDATA_WAKE_PIN);
-}
-
-void chip_pre_init(void)
-{
-	/* Enable clocks to GPIO block C in run and sleep modes. */
-	clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL);
-
-	/*
-	 * Ensure PC0:3 are set to JTAG function.  They should be set this way
-	 * on a cold boot, but on a warm reboot a previous misbehaving image
-	 * could have set them differently.
-	 */
-	if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) &&
-	    ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) &&
-	    ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f))
-		return;  /* Already properly configured */
-
-	/* Unlock commit register for JTAG pins */
-	LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK;
-	LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f;
-
-	/* Reset JTAG pins */
-	LM4_GPIO_PCTL(LM4_GPIO_C) =
-		(LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111;
-	LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f;
-	LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f;
-
-	/* Set interrupt on either edge of the JTAG signals */
-	LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f;
-
-	/* Re-lock commit register */
-	LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f;
-	LM4_GPIO_LOCK(LM4_GPIO_C) = 0;
-}
-
-void system_pre_init(void)
-{
-	uint32_t hibctl;
-#ifdef CONFIG_SOFTWARE_PANIC
-	uint32_t reason, info;
-	uint8_t exception, panic_flags;
-#endif
-
-	/*
-	 * Enable clocks to the hibernation module in run, sleep,
-	 * and deep sleep modes.
-	 */
-	clock_enable_peripheral(CGC_OFFSET_HIB, 0x1, CGC_MODE_ALL);
-
-	/*
-	 * Enable the hibernation oscillator, if it's not already enabled.
-	 * This should only need setting if the EC completely lost power (for
-	 * example, the battery was pulled).
-	 */
-	if (!(LM4_HIBERNATE_HIBCTL & LM4_HIBCTL_CLK32EN)) {
-		int i;
-
-		/* Enable clock to hibernate module */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_CLK32EN;
-
-		/* Wait for write-complete */
-		for (i = 0; i < 1000000; i++) {
-			if (LM4_HIBERNATE_HIBRIS & 0x10)
-				break;
-		}
-
-		/* Enable and reset RTC */
-		wait_for_hibctl_wc();
-		LM4_HIBERNATE_HIBCTL |= LM4_HIBCTL_RTCEN;
-		system_set_rtc(0);
-
-		/* Clear all hibernate data entries */
-		for (i = 0; i < LM4_HIBERNATE_HIBDATA_ENTRIES; i++)
-			hibdata_write(i, 0);
-	}
-
-	/*
-	 * Set wake reasons to RTC match and WAKE pin by default.
-	 * Before going in to hibernate, these may change.
-	 */
-	hibctl = LM4_HIBERNATE_HIBCTL;
-	hibctl |= LM4_HIBCTL_RTCWEN;
-	hibctl |= LM4_HIBCTL_PINWEN;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBCTL = hibctl;
-
-	/*
-	 * Initialize registers after reset to work around LM4 chip errata
-	 * (still present in A3 chip stepping).
-	 */
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBRTCT = 0x7fff;
-	wait_for_hibctl_wc();
-	LM4_HIBERNATE_HIBIM = 0;
-
-	check_reset_cause();
-
-#ifdef CONFIG_SOFTWARE_PANIC
-	/* Restore then clear saved panic reason */
-	reason = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_REASON);
-	info = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_INFO);
-	exception = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION);
-	panic_flags = hibdata_read(HIBDATA_INDEX_SAVED_PANIC_FLAGS);
-
-	if (reason || info || exception) {
-		panic_set_reason(reason, info, exception);
-		panic_get_data()->flags = panic_flags;
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_FLAGS, 0);
-	}
-#endif
-
-	/* Initialize bootcfg if needed */
-	if (LM4_SYSTEM_BOOTCFG != CONFIG_BOOTCFG_VALUE) {
-		/* read-modify-write */
-		LM4_FLASH_FMD = (LM4_SYSTEM_BOOTCFG_MASK & LM4_SYSTEM_BOOTCFG)
-			| (~LM4_SYSTEM_BOOTCFG_MASK & CONFIG_BOOTCFG_VALUE);
-		LM4_FLASH_FMA = 0x75100000;
-		LM4_FLASH_FMC = 0xa4420008;  /* WRKEY | COMT */
-		while (LM4_FLASH_FMC & 0x08)
-			;
-	}
-
-	/* Brown-outs should trigger a reset */
-	LM4_SYSTEM_PBORCTL |= 0x02;
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	chip_save_reset_flags(save_flags);
-
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception, panic_flags;
-
-		panic_flags = panic_get_data()->flags;
-
-		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_REASON, reason);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_INFO, info);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-		hibdata_write(HIBDATA_INDEX_SAVED_PANIC_FLAGS, panic_flags);
-#endif
-
-		/*
-		 * Bounce through hibernate to trigger a hard reboot.  Do
-		 * not wake on wake pin, since we need the full duration.
-		 */
-		hibernate(0, HIB_RESET_USEC, HIBDATA_WAKE_HARD_RESET);
-	} else
-		CPU_NVIC_APINT = 0x05fa0004;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	return hibdata_write(HIBDATA_INDEX_SCRATCHPAD, value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = hibdata_read(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "ti";
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_id_string(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-	uint32_t did = LM4_SYSTEM_DID1 >> 16;
-
-	if (*p)
-		return (const char *)str;
-
-	*p = to_hex(did >> 12);
-	*(p + 1) = to_hex((did >> 8) & 0xf);
-	*(p + 2) = to_hex((did >> 4) & 0xf);
-	*(p + 3) = to_hex(did & 0xf);
-	*(p + 4) = '\0';
-
-	return (const char *)str;
-}
-
-const char *system_get_raw_chip_name(void)
-{
-	switch ((LM4_SYSTEM_DID1 & 0xffff0000) >> 16) {
-	case 0x10de:
-		return "tm4e1g31h6zrb";
-	case 0x10e2:
-		return "lm4fsxhh5bb";
-	case 0x10e3:
-		return "lm4fs232h5bb";
-	case 0x10e4:
-		return "lm4fs99h5bb";
-	case 0x10e6:
-		return "lm4fs1ah5bb";
-	case 0x10ea:
-		return "lm4fs1gh5bb";
-	default:
-		return system_get_chip_id_string();
-	}
-}
-
-const char *system_get_chip_name(void)
-{
-	const char *postfix = "-tm"; /* test mode */
-	static char str[20];
-	const char *raw_chip_name = system_get_raw_chip_name();
-	char *p = str;
-
-	if (LM4_TEST_MODE_ENABLED) {
-		/* Debug mode is enabled. Postfix chip name. */
-		while (*raw_chip_name)
-			*(p++) = *(raw_chip_name++);
-		while (*postfix)
-			*(p++) = *(postfix++);
-		*p = '\0';
-		return (const char *)str;
-	} else {
-		return raw_chip_name;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char rev[3];
-
-	/* Extract the major[15:8] and minor[7:0] revisions. */
-	rev[0] = 'A' + ((LM4_SYSTEM_DID0 >> 8) & 0xff);
-	rev[1] = '0' + (LM4_SYSTEM_DID0 & 0xff);
-	rev[2] = 0;
-
-	return rev;
-}
-
-/*****************************************************************************/
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t rtc;
-	uint32_t rtcss;
-
-	rtc = system_get_rtc_sec_subsec(&rtcss);
-	cprintf(ch, "RTC: 0x%08x.%04x (%d.%06d s)\n",
-		 rtc, rtcss, rtc, HIB_RTC_SUBSEC_TO_USEC(rtcss));
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		uint32_t t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-			"[set <seconds>]",
-			"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-	system_enable_hib_interrupt();
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-	}
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec_subsec(NULL);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		     system_rtc_get_value,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		     system_rtc_set_value,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
deleted file mode 100644
index 7ccea9eb75..0000000000
--- a/chip/lm4/uart.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#ifdef CONFIG_UART_HOST
-#define IRQ_UART_HOST CONCAT2(LM4_IRQ_UART, CONFIG_UART_HOST)
-#endif
-
-static int init_done;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (LM4_UART_IM(0) & 0x20)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	LM4_UART_IM(0) |= 0x20;
-	task_trigger_irq(LM4_IRQ_UART0);
-}
-
-void uart_tx_stop(void)
-{
-	LM4_UART_IM(0) &= ~0x20;
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(LM4_UART_FR(0) & 0x80))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return !(LM4_UART_FR(0) & 0x20);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* Transmit is in progress if the TX busy bit is set. */
-	return LM4_UART_FR(0) & 0x08;
-}
-
-int uart_rx_available(void)
-{
-	return !(LM4_UART_FR(0) & 0x10);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	LM4_UART_DR(0) = c;
-}
-
-int uart_read_char(void)
-{
-	return LM4_UART_DR(0);
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	int scratch __attribute__ ((unused));
-	while (!(LM4_UART_FR(channel) & 0x10))
-		scratch = LM4_UART_DR(channel);
-}
-
-/**
- * Interrupt handler for UART0
- */
-void uart_ec_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(0) = 0x70;
-
-
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
-
-#ifdef CONFIG_UART_HOST
-
-/**
- * Interrupt handler for Host UART
- */
-void uart_host_interrupt(void)
-{
-	/* Clear transmit and receive interrupt status */
-	LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
-
-#ifdef CONFIG_HOSTCMD_LPC
-	/*
-	 * If we have space in our FIFO and a character is pending in LPC,
-	 * handle that character.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x20) && lpc_comx_has_char()) {
-		/* Copy the next byte then disable transmit interrupt */
-		LM4_UART_DR(CONFIG_UART_HOST) = lpc_comx_get_char();
-		LM4_UART_IM(CONFIG_UART_HOST) &= ~0x20;
-	}
-
-	/*
-	 * Handle received character.  There is no flow control on input;
-	 * received characters are blindly forwarded to LPC.  This is ok
-	 * because LPC is much faster than UART, and we don't have flow control
-	 * on the UART receive-side either.
-	 */
-	if (!(LM4_UART_FR(CONFIG_UART_HOST) & 0x10))
-		lpc_comx_put_char(LM4_UART_DR(CONFIG_UART_HOST));
-#endif
-}
-/* Must be same prio as LPC interrupt handler so they don't preempt */
-DECLARE_IRQ(IRQ_UART_HOST, uart_host_interrupt, 2);
-
-#endif /* CONFIG_UART_HOST */
-
-static void uart_config(int port)
-{
-	/* Disable the port */
-	LM4_UART_CTL(port) = 0x0300;
-	/* Use the internal oscillator */
-	LM4_UART_CC(port) = 0x1;
-	/* Set the baud rate divisor */
-	LM4_UART_IBRD(port) = (INTERNAL_CLOCK / 16) / CONFIG_UART_BAUD_RATE;
-	LM4_UART_FBRD(port) =
-		(((INTERNAL_CLOCK / 16) % CONFIG_UART_BAUD_RATE) * 64
-		 + CONFIG_UART_BAUD_RATE / 2) / CONFIG_UART_BAUD_RATE;
-	/*
-	 * 8-N-1, FIFO enabled.  Must be done after setting
-	 * the divisor for the new divisor to take effect.
-	 */
-	LM4_UART_LCRH(port) = 0x70;
-	/*
-	 * Interrupt when RX fifo at minimum (>= 1/8 full), and TX fifo
-	 * when <= 1/4 full
-	 */
-	LM4_UART_IFLS(port) = 0x01;
-	/*
-	 * Unmask receive-FIFO, receive-timeout.  We need
-	 * receive-timeout because the minimum RX FIFO depth is 1/8 = 2
-	 * bytes; without the receive-timeout we'd never be notified
-	 * about single received characters.
-	 */
-	LM4_UART_IM(port) = 0x50;
-	/* Enable the port */
-	LM4_UART_CTL(port) |= 0x0001;
-}
-
-void uart_init(void)
-{
-	uint32_t mask = 0;
-
-	/*
-	 * Enable UART0 in run, sleep, and deep sleep modes. Enable the Host
-	 * UART in run and sleep modes.
-	 */
-	mask |= 1;
-	clock_enable_peripheral(CGC_OFFSET_UART, mask, CGC_MODE_ALL);
-
-#ifdef CONFIG_UART_HOST
-	mask |= BIT(CONFIG_UART_HOST);
-#endif
-
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Configure UARTs (identically) */
-	uart_config(0);
-
-#ifdef CONFIG_UART_HOST
-	uart_config(CONFIG_UART_HOST);
-#endif
-
-	/*
-	 * Enable interrupts for UART0 only. Host UART will have to wait
-	 * until the LPC bus is initialized.
-	 */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/* Disable the UART0 module interrupt. */
-	task_disable_irq(LM4_IRQ_UART0);
-
-	/* Disable UART0 peripheral in deep sleep. */
-	clock_disable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-
-	/*
-	 * Set the UART0 RX pin to be a generic GPIO with the flags defined
-	 * in the board.c file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* Clear any pending GPIO interrupts on the UART0 RX pin. */
-	LM4_GPIO_ICR(g.port) = g.mask;
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-void uart_exit_dsleep(void)
-{
-	const struct gpio_info g = gpio_list[GPIO_UART0_RX];
-
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not get called.
-	 */
-	if (!(LM4_GPIO_MIS(g.port) & g.mask))
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(LM4_IRQ_UART0);
-
-	/* Enable UART0 peripheral in deep sleep */
-	clock_enable_peripheral(CGC_OFFSET_UART, 0x1, CGC_MODE_DSLEEP);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-/*****************************************************************************/
-/* COMx functions */
-
-#ifdef CONFIG_UART_HOST
-
-void uart_comx_enable(void)
-{
-	uart_clear_rx_fifo(CONFIG_UART_HOST);
-	task_enable_irq(IRQ_UART_HOST);
-}
-
-int uart_comx_putc_ok(void)
-{
-	if (LM4_UART_FR(CONFIG_UART_HOST) & 0x20) {
-		/*
-		 * FIFO is full, so enable transmit interrupt to let us know
-		 * when it empties.
-		 */
-		LM4_UART_IM(CONFIG_UART_HOST) |= 0x20;
-		return 0;
-	} else {
-		return 1;
-	}
-}
-
-void uart_comx_putc(int c)
-{
-	LM4_UART_DR(CONFIG_UART_HOST) = c;
-}
-
-#endif /* CONFIG_UART_HOST */
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_COMXTEST
-
-/**
- * Write a character to COMx, waiting for space in the output buffer if
- * necessary.
- */
-static void uart_comx_putc_wait(int c)
-{
-		while (!uart_comx_putc_ok())
-			;
-		uart_comx_putc(c);
-}
-
-static int command_comxtest(int argc, char **argv)
-{
-	/* Put characters to COMX port */
-	const char *c = argc > 1 ? argv[1] : "testing comx output!";
-
-	ccprintf("Writing \"%s\\r\\n\" to COMx UART...\n", c);
-
-	while (*c)
-		uart_comx_putc_wait(*c++);
-
-	uart_comx_putc_wait('\r');
-	uart_comx_putc_wait('\n');
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(comxtest, command_comxtest,
-			"[string]",
-			"Write test data to COMx uart");
-
-#endif /* CONFIG_CMD_COMXTEST */
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
deleted file mode 100644
index 50f122bf02..0000000000
--- a/chip/lm4/watchdog.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "clock.h"
-#include "common.h"
-#include "registers.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * We use watchdog 0 which is clocked on the system clock
- * to avoid the penalty cycles on each write access
- */
-
-/* magic value to unlock the watchdog registers */
-#define LM4_WATCHDOG_MAGIC_WORD  0x1ACCE551
-
-static uint32_t watchdog_period;     /* Watchdog counter initial value */
-
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) __attribute__((naked));
-void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_trace\n"
-		      /* Do NOT reset the watchdog interrupt here; it will
-		       * be done in watchdog_reload(), or reset will be
-		       * triggered if we don't call that by the next watchdog
-		       * period.  Instead, de-activate the interrupt in the
-		       * NVIC, so the watchdog trace will only be printed
-		       * once.
-		       */
-		     "mov r0, %[irq]\n"
-		     "bl task_disable_irq\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n"
-			: : [irq] "i" (LM4_IRQ_WATCHDOG));
-}
-const struct irq_priority __keep IRQ_PRIORITY(LM4_IRQ_WATCHDOG)
-	__attribute__((section(".rodata.irqprio")))
-		= {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest
-					    priority */
-
-void watchdog_reload(void)
-{
-	uint32_t status = LM4_WATCHDOG_RIS(0);
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* As we reboot only on the second timeout, if we have already reached
-	 * the first timeout we need to reset the interrupt bit. */
-	if (status) {
-		LM4_WATCHDOG_ICR(0) = status;
-		/* That doesn't seem to unpend the watchdog interrupt (even if
-		 * we do writes to force the write to be committed), so
-		 * explicitly unpend the interrupt before re-enabling it. */
-		task_clear_pending_irq(LM4_IRQ_WATCHDOG);
-		task_enable_irq(LM4_IRQ_WATCHDOG);
-	}
-
-	/* Reload the watchdog counter */
-	LM4_WATCHDOG_LOAD(0) = watchdog_period;
-
-	/* Re-lock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-static void watchdog_freq_changed(void)
-{
-	/* Set the timeout period */
-	watchdog_period = CONFIG_WATCHDOG_PERIOD_MS * (clock_get_freq() / 1000);
-
-	/* Reload the watchdog timer now */
-	watchdog_reload();
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, watchdog_freq_changed, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Enable watchdog 0 clock in run, sleep, and deep sleep modes */
-	clock_enable_peripheral(CGC_OFFSET_WD, 0x1, CGC_MODE_ALL);
-
-	/* Set initial timeout period */
-	watchdog_freq_changed();
-
-	/* Unlock watchdog registers */
-	LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
-
-	/* De-activate the watchdog when the JTAG stops the CPU */
-	LM4_WATCHDOG_TEST(0) |= BIT(8);
-
-	/* Reset after 2 time-out, activate the watchdog and lock the control
-	 * register. */
-	LM4_WATCHDOG_CTL(0) = 0x3;
-
-	/* Reset watchdog interrupt bits */
-	LM4_WATCHDOG_ICR(0) = LM4_WATCHDOG_RIS(0);
-
-	/* Lock watchdog registers against unintended accesses */
-	LM4_WATCHDOG_LOCK(0) = 0xdeaddead;
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(LM4_IRQ_WATCHDOG);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
deleted file mode 100644
index e0f5636b2e..0000000000
--- a/chip/max32660/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# MAX32660 chip specific files build
-#
-
-# MAX32660 SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
-chip-$(CONFIG_I2C)+=i2c_chip.o
-
-# Optional chip modules
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o
-chip-$(CONFIG_WATCHDOG)+=wdt_chip.o
-
diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c
deleted file mode 100644
index 901c5d559c..0000000000
--- a/chip/max32660/clock_chip.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Clocks and Power Management Module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-#include "pwrseq_regs.h"
-
-#define MAX32660_SYSTEMCLOCK SYS_CLOCK_HIRC
-
-/** Clock source */
-typedef enum {
-	SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring
-								 on MAX32660 */
-	SYS_CLOCK_HFXIN =
-		MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
-	SYS_CLOCK_HFXIN_DIGITAL = 0x9,	/**< External Clock Input*/
-	SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency
-							 Internal Oscillator */
-} sys_system_clock_t;
-
-/***** Functions ******/
-static void clock_wait_ready(uint32_t ready)
-{
-	// Start timeout, wait for ready
-	do {
-		if (MXC_GCR->clkcn & ready) {
-			return;
-		}
-	} while (1);
-}
-
-extern void (*const __isr_vector[])(void);
-uint32_t SystemCoreClock = HIRC96_FREQ;
-
-static void clock_update(void)
-{
-	uint32_t base_freq, divide, ovr;
-
-	// Get the clock source and frequency
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		base_freq = HIRC96_FREQ / 4;
-	} else {
-		if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-			base_freq = HIRC96_FREQ / 2;
-		} else {
-			base_freq = HIRC96_FREQ;
-		}
-	}
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	SystemCoreClock = base_freq >> divide;
-}
-
-void clock_init(void)
-{
-	/* Switch system clock to HIRC */
-	uint32_t ovr, divide;
-
-	// Set FWS higher than what the minimum for the fastest clock is
-	MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-			   (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-
-	// Enable 96MHz Clock
-	MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN;
-
-	// Wait for the 96MHz clock
-	clock_wait_ready(MXC_F_GCR_CLKCN_HIRC_RDY);
-
-	// Set 96MHz clock as System Clock
-	MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL,
-		     MXC_S_GCR_CLKCN_CLKSEL_HIRC);
-
-	// Wait for system clock to be ready
-	clock_wait_ready(MXC_F_GCR_CLKCN_CKRDY);
-
-	// Update the system core clock
-	clock_update();
-
-	// Get the clock divider
-	divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >>
-		 MXC_F_GCR_CLKCN_PSC_POS;
-
-	// get ovr setting
-	ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
-
-	// Set flash wait settings
-	if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	} else {
-		if (divide == 0) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else if (divide == 1) {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		} else {
-			MXC_GCR->memckcn =
-				(MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) |
-				(0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
-		}
-	}
-}
diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h
deleted file mode 100644
index c97c246bb7..0000000000
--- a/chip/max32660/config_chip.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* 96.000 MHz internal oscillator frequency */
-#define INTERNAL_CLOCK 96000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 132
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 8192
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * Time it takes to set the RTC match register. This value is conservatively
- * set based on measurements around 200us.
- */
-#define HIB_SET_RTC_MATCH_DELAY_USEC 300
-
-/****************************************************************************/
-/* Memory mapping */
-
-#define CONFIG_RAM_BASE 0x20000000
-#define CONFIG_RAM_SIZE 0x00018000 /* 96k MAX32660 SRAM Size*/
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 4096
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 768
-#define SMALLER_TASK_STACK_SIZE 384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_BANK_SIZE 0x00002000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
-
-/* Ideal flash write size fills the 32-entry flash write buffer */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4)
-
-/* This is the physical size of the flash on the chip. We'll reserve one bank
- * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
- * doesn't support a write-protect pin, and if we make the write-protection
- * permanent, it can't be undone easily enough to support RMA. */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256K MAX32660 FLASH Size */
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/****************************************************************************/
-/* Lock the boot configuration to prevent brickage. */
-
-/*
- * No GPIO trigger for ROM bootloader.
- * Keep JTAG debugging enabled.
- * Use 0xA442 flash write key.
- * Lock it this way.
- */
-#define CONFIG_BOOTCFG_VALUE 0x7ffffffe
-
-/****************************************************************************/
-/* Customize the build */
-
-/* Optional features present on this chip */
-#define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c
deleted file mode 100644
index 747d7dcc58..0000000000
--- a/chip/max32660/flash_chip.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Flash Memory Module for Chrome EC */
-
-#include "flash.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "registers.h"
-#include "common.h"
-#include "icc_regs.h"
-#include "flc_regs.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-/***** Definitions *****/
-
-/// Bit mask that can be used to find the starting address of a page in flash
-#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
-
-/// Calculate the address of a page in flash from the page number
-#define MXC_FLASH_PAGE_ADDR(page)                                              \
-	(MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
-
-void flash_operation(void)
-{
-	volatile uint32_t *line_addr;
-	volatile uint32_t __attribute__((unused)) line;
-
-	// Clear the cache
-	MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
-	MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
-
-	// Clear the line fill buffer
-	line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE);
-	line = *line_addr;
-
-	line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
-	line = *line_addr;
-}
-
-static int flash_busy(void)
-{
-	return (MXC_FLC->cn &
-		(MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE));
-}
-
-static int flash_init_controller(void)
-{
-	// Set flash clock divider to generate a 1MHz clock from the APB clock
-	MXC_FLC->clkdiv = SystemCoreClock / 1000000;
-
-	/* Check if the flash controller is busy */
-	if (flash_busy()) {
-		return EC_ERROR_BUSY;
-	}
-
-	/* Clear stale errors */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-	}
-
-	/* Unlock flash */
-	MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) |
-		      MXC_S_FLC_CN_UNLOCK_UNLOCKED;
-
-	return EC_SUCCESS;
-}
-
-static int flash_device_page_erase(uint32_t address)
-{
-	int err;
-
-	if ((err = flash_init_controller()) != EC_SUCCESS)
-		return err;
-
-	// Align address on page boundary
-	address = address - (address % MXC_FLASH_PAGE_SIZE);
-
-	/* Write paflash_init_controllerde */
-	MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) |
-		      MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE;
-	/* Issue page erase command */
-	MXC_FLC->addr = address;
-	MXC_FLC->cn |= MXC_F_FLC_CN_PGE;
-
-	/* Wait until flash operation is complete */
-	while (flash_busy())
-		;
-
-	/* Lock flash */
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
-
-	/* Check access violations */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-		return EC_ERROR_UNKNOWN;
-	}
-
-	flash_operation();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int err;
-	uint32_t bytes_written;
-	uint8_t current_data[4];
-
-	if ((err = flash_init_controller()) != EC_SUCCESS)
-		return err;
-
-	// write in 32-bit units until we are 128-bit aligned
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
-	MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
-
-	// Align the address and read/write if we have to
-	if (offset & 0x3) {
-
-		// Figure out how many bytes we have to write to round up the
-		// address
-		bytes_written = 4 - (offset & 0x3);
-
-		// Save the data currently in the flash
-		memcpy(current_data, (void *)(offset & (~0x3)), 4);
-
-		// Modify current_data to insert the data from buffer
-		memcpy(&current_data[4 - bytes_written], data, bytes_written);
-
-		// Write the modified data
-		MXC_FLC->addr = offset - (offset % 4);
-		memcpy((void *)&MXC_FLC->data[0], &current_data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += bytes_written;
-		size -= bytes_written;
-		data += bytes_written;
-	}
-
-	while ((size >= 4) && ((offset & 0x1F) != 0)) {
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += 4;
-		size -= 4;
-		data += 4;
-	}
-
-	if (size >= 16) {
-
-		// write in 128-bit bursts while we can
-		MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
-
-		while (size >= 16) {
-			MXC_FLC->addr = offset;
-			memcpy((void *)&MXC_FLC->data[0], data, 16);
-			MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-			/* Wait until flash operation is complete */
-			while (flash_busy())
-				;
-
-			offset += 16;
-			size -= 16;
-			data += 16;
-		}
-
-		// Return to 32-bit writes.
-		MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
-	}
-
-	while (size >= 4) {
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-
-		offset += 4;
-		size -= 4;
-		data += 4;
-	}
-
-	if (size > 0) {
-		// Save the data currently in the flash
-		memcpy(current_data, (void *)(offset), 4);
-
-		// Modify current_data to insert the data from data
-		memcpy(current_data, data, size);
-
-		MXC_FLC->addr = offset;
-		memcpy((void *)&MXC_FLC->data[0], current_data, 4);
-		MXC_FLC->cn |= MXC_F_FLC_CN_WR;
-
-		/* Wait until flash operation is complete */
-		while (flash_busy())
-			;
-	}
-
-	/* Lock flash */
-	MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
-
-	/* Check access violations */
-	if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
-		MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
-		return EC_ERROR_UNKNOWN;
-	}
-
-	flash_operation();
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int i;
-	int pages;
-	int error_status;
-
-	/*
-	 * erase 'size' number of bytes starting at address 'offset'
-	 */
-	/* calculate the number of pages */
-	pages = size / CONFIG_FLASH_ERASE_SIZE;
-	/* iterate over the number of pages */
-	for (i = 0; i < pages; i++) {
-		/* erase the page after calculating the start address */
-		error_status = flash_device_page_erase(
-			offset + (i * CONFIG_FLASH_ERASE_SIZE));
-		if (error_status != EC_SUCCESS) {
-			return error_status;
-		}
-	}
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	/* Not protected */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	/* no flags set */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	/* These are the flags we're going to pay attention to */
-	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	/* no flags writable */
-	return 0;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	/* nothing to do here */
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	/* nothing to do here */
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Test Commands */
-
-/*
- * Read, Write, and Erase a page of flash memory using chip routines
- * NOTE: This is a DESTRUCTIVE test for the range of flash pages tested
- *       make sure that PAGE_START is beyond your flash code.
- */
-static int command_flash_test1(int argc, char **argv)
-{
-	int i;
-	uint8_t *ptr;
-	const uint32_t PAGE_START = 9;
-	const uint32_t PAGE_END = 32;
-	uint32_t page;
-	int error_status;
-	uint32_t flash_address;
-	const int BUFFER_SIZE = 32;
-	uint8_t buffer[BUFFER_SIZE];
-
-	/*
-	 * As a test, write unique data to each page in this for loop, later
-	 * verify data in pages
-	 */
-	for (page = PAGE_START; page < PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-
-		/*
-		 * erase page
-		 */
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_erase\n");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/*
-		 * verify page was erased
-		 */
-		// CPRINTS("read flash page %d, address %x, ", page,
-		// flash_address);
-		ptr = (uint8_t *)flash_address;
-		for (i = 0; i < CONFIG_FLASH_ERASE_SIZE; i++) {
-			if (*ptr++ != 0xff) {
-				CPRINTS("Error with verifying page erase\n");
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-
-		/*
-		 * write pattern to page, just write BUFFER_SIZE worth of data
-		 */
-		for (i = 0; i < BUFFER_SIZE; i++) {
-			buffer[i] = i + page;
-		}
-		error_status = crec_flash_physical_write(flash_address,
-							 BUFFER_SIZE, buffer);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_write\n");
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	/*
-	 * Verify data in pages
-	 */
-	for (page = PAGE_START; page < PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-
-		/*
-		 * read a portion of flash memory
-		 */
-		ptr = (uint8_t *)flash_address;
-		for (i = 0; i < BUFFER_SIZE; i++) {
-			if (*ptr++ != (i + page)) {
-				CPRINTS("Error with verifing written test "
-					"data\n");
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		CPRINTS("Verified Erase, Write, Read page %d", page);
-	}
-
-	/*
-	 * Clean up after tests
-	 */
-	for (page = PAGE_START; page <= PAGE_END; page++) {
-		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
-		if (error_status != EC_SUCCESS) {
-			CPRINTS("Error with crec_flash_physical_erase\n");
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	CPRINTS("done command_flash_test1.");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flashtest1, command_flash_test1, "flashtest1",
-			"Flash chip routine tests");
diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h
deleted file mode 100644
index a484763c0b..0000000000
--- a/chip/max32660/flc_regs.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the FLC Peripheral Module
- */
-
-#ifndef _FLC_REGS_H_
-#define _FLC_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * Registers, Bit Masks and Bit Positions for the FLC Peripheral
- * Module.
- */
-
-/**
- * Structure type to access the FLC Registers.
- */
-typedef struct {
-	__IO uint32_t addr;   /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
-	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x08:<\tt> FLC CN Register */
-	__R uint32_t rsv_0xc_0x23[6];
-	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
-	__R uint32_t rsv_0x28_0x2f[2];
-	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
-	__O uint32_t acntl;    /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
-} mxc_flc_regs_t;
-
-/* Register offsets for module FLC */
-/**
- * FLC Peripheral Register Offsets from the FLC Base Peripheral
- * Address.
- */
-#define MXC_R_FLC_ADDR                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_FLC_CLKDIV                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_FLC_CN                                                           \
-	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_FLC_INTR                                                         \
-	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x024 */
-#define MXC_R_FLC_DATA                                                         \
-	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x030 */
-#define MXC_R_FLC_ACNTL                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt>       \
-				    0x0x040 */
-
-/**
- * Flash Write Address.
- */
-#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
-#define MXC_F_FLC_ADDR_ADDR                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
-
-/**
- * Flash Clock Divide. The clock (PLL0) is divided by this value to
- * generate a 1 MHz clock for Flash controller.
- */
-#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
-#define MXC_F_FLC_CLKDIV_CLKDIV                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
-
-/**
- * Flash Control Register.
- */
-#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
-#define MXC_F_FLC_CN_WR                                                        \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
-#define MXC_V_FLC_CN_WR_COMPLETE                                               \
-	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value                            \
-			   */
-#define MXC_S_FLC_CN_WR_COMPLETE                                               \
-	(MXC_V_FLC_CN_WR_COMPLETE                                              \
-	 << MXC_F_FLC_CN_WR_POS)		/**< CN_WR_COMPLETE Setting */
-#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
-#define MXC_S_FLC_CN_WR_START                                                  \
-	(MXC_V_FLC_CN_WR_START                                                 \
-	 << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
-
-#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
-#define MXC_F_FLC_CN_ME                                                        \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
-
-#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
-#define MXC_F_FLC_CN_PGE                                                       \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
-
-#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
-#define MXC_F_FLC_CN_WDTH                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
-#define MXC_V_FLC_CN_WDTH_SIZE128                                              \
-	((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
-#define MXC_S_FLC_CN_WDTH_SIZE128                                              \
-	(MXC_V_FLC_CN_WDTH_SIZE128                                             \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
-#define MXC_V_FLC_CN_WDTH_SIZE32                                               \
-	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value                            \
-			   */
-#define MXC_S_FLC_CN_WDTH_SIZE32                                               \
-	(MXC_V_FLC_CN_WDTH_SIZE32                                              \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
-
-#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
-#define MXC_F_FLC_CN_ERASE_CODE                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
-#define MXC_V_FLC_CN_ERASE_CODE_NOP                                            \
-	((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
-#define MXC_S_FLC_CN_ERASE_CODE_NOP                                            \
-	(MXC_V_FLC_CN_ERASE_CODE_NOP                                           \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting  \
-					  */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                      \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting   \
-					  */
-
-#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
-#define MXC_F_FLC_CN_PEND                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
-#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)     /**< CN_PEND_IDLE Value */
-#define MXC_S_FLC_CN_PEND_IDLE                                                 \
-	(MXC_V_FLC_CN_PEND_IDLE                                                \
-	 << MXC_F_FLC_CN_PEND_POS)		 /**< CN_PEND_IDLE Setting */
-#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
-#define MXC_S_FLC_CN_PEND_BUSY                                                 \
-	(MXC_V_FLC_CN_PEND_BUSY                                                \
-	 << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
-
-#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
-#define MXC_F_FLC_CN_LVE                                                       \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
-#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)      /**< CN_LVE_DIS Value */
-#define MXC_S_FLC_CN_LVE_DIS                                                   \
-	(MXC_V_FLC_CN_LVE_DIS                                                  \
-	 << MXC_F_FLC_CN_LVE_POS)	     /**< CN_LVE_DIS Setting */
-#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
-#define MXC_S_FLC_CN_LVE_EN                                                    \
-	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting   \
-						       */
-
-#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
-#define MXC_F_FLC_CN_BRST                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
-#define MXC_V_FLC_CN_BRST_DISABLE                                              \
-	((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
-#define MXC_S_FLC_CN_BRST_DISABLE                                              \
-	(MXC_V_FLC_CN_BRST_DISABLE                                             \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
-#define MXC_V_FLC_CN_BRST_ENABLE                                               \
-	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value                            \
-			   */
-#define MXC_S_FLC_CN_BRST_ENABLE                                               \
-	(MXC_V_FLC_CN_BRST_ENABLE                                              \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
-
-#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
-#define MXC_F_FLC_CN_UNLOCK                                                    \
-	((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
-#define MXC_V_FLC_CN_UNLOCK_UNLOCKED                                           \
-	((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
-#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                           \
-	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                                          \
-	 << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
-
-/**
- * Flash Interrupt Register.
- */
-#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
-#define MXC_F_FLC_INTR_DONE                                                    \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
-#define MXC_V_FLC_INTR_DONE_INACTIVE                                           \
-	((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
-#define MXC_S_FLC_INTR_DONE_INACTIVE                                           \
-	(MXC_V_FLC_INTR_DONE_INACTIVE                                          \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
-#define MXC_V_FLC_INTR_DONE_PENDING                                            \
-	((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
-#define MXC_S_FLC_INTR_DONE_PENDING                                            \
-	(MXC_V_FLC_INTR_DONE_PENDING                                           \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
-
-#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
-#define MXC_F_FLC_INTR_AF                                                      \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
-#define MXC_V_FLC_INTR_AF_NOERROR                                              \
-	((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
-#define MXC_S_FLC_INTR_AF_NOERROR                                              \
-	(MXC_V_FLC_INTR_AF_NOERROR                                             \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
-#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
-#define MXC_S_FLC_INTR_AF_ERROR                                                \
-	(MXC_V_FLC_INTR_AF_ERROR                                               \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
-
-#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
-#define MXC_F_FLC_INTR_DONEIE                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
-#define MXC_V_FLC_INTR_DONEIE_DISABLE                                          \
-	((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_DISABLE                                          \
-	(MXC_V_FLC_INTR_DONEIE_DISABLE                                         \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
-#define MXC_V_FLC_INTR_DONEIE_ENABLE                                           \
-	((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_ENABLE                                           \
-	(MXC_V_FLC_INTR_DONEIE_ENABLE                                          \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
-
-#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
-#define MXC_F_FLC_INTR_AFIE                                                    \
-	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
-
-/**
- * Flash Write Data.
- */
-#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
-#define MXC_F_FLC_DATA_DATA                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
-
-/**
- * Access Control Register. Writing the ACNTL register with the
- * following values in the order shown, allows read and write access to the
- * system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl =
- * 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will
- * disable access to system and user information block. Readback of this
- * register is always zero.
- */
-#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
-#define MXC_F_FLC_ACNTL_ACNTL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FLC_REGS_H_ */
diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h
deleted file mode 100644
index c9de13812c..0000000000
--- a/chip/max32660/gcr_regs.h
+++ /dev/null
@@ -1,1365 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the GCR Peripheral Module
- */
-
-#ifndef _GCR_REGS_H_
-#define _GCR_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * Registers, Bit Masks and Bit Positions for the GCR Peripheral
- * Module.
- */
-
-/**
- * Structure type to access the GCR Registers.
- */
-typedef struct {
-	__IO uint32_t scon;  /**< <tt>\b 0x00:<\tt> GCR SCON Register */
-	__IO uint32_t rstr0; /**< <tt>\b 0x04:<\tt> GCR RSTR0 Register */
-	__IO uint32_t clkcn; /**< <tt>\b 0x08:<\tt> GCR CLKCN Register */
-	__IO uint32_t pm;    /**< <tt>\b 0x0C:<\tt> GCR PM Register */
-	__R uint32_t rsv_0x10_0x17[2];
-	__IO uint32_t pckdiv; /**< <tt>\b 0x18:<\tt> GCR PCKDIV Register */
-	__R uint32_t rsv_0x1c_0x23[2];
-	__IO uint32_t perckcn0; /**< <tt>\b 0x24:<\tt> GCR PERCKCN0 Register */
-	__IO uint32_t memckcn;  /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
-	__IO uint32_t memzcn;   /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
-	__R uint32_t rsv_0x30;
-	__IO uint32_t scck;     /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
-	__IO uint32_t mpri0;    /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
-	__IO uint32_t mpri1;    /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
-	__IO uint32_t sysst;    /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
-	__IO uint32_t rstr1;    /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
-	__IO uint32_t perckcn1; /**< <tt>\b 0x48:<\tt> GCR PERCKCN1 Register */
-	__IO uint32_t evten;    /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
-	__I uint32_t revision;  /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
-	__IO uint32_t syssie;   /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
-} mxc_gcr_regs_t;
-
-/**
- * GCR Peripheral Register Offsets from the GCR Base Peripheral
- * Address.
- */
-#define MXC_R_GCR_SCON                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_GCR_RSTR0                                                        \
-	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_GCR_CLKCN                                                        \
-	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_GCR_PM                                                           \
-	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x00C */
-#define MXC_R_GCR_PCKDIV                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x018 */
-#define MXC_R_GCR_PERCKCN0                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x024 */
-#define MXC_R_GCR_MEMCKCN                                                      \
-	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x028 */
-#define MXC_R_GCR_MEMZCN                                                       \
-	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x02C */
-#define MXC_R_GCR_SCCK                                                         \
-	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x034 */
-#define MXC_R_GCR_MPRI0                                                        \
-	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x038 */
-#define MXC_R_GCR_MPRI1                                                        \
-	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x03C */
-#define MXC_R_GCR_SYSST                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x040 */
-#define MXC_R_GCR_RSTR1                                                        \
-	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x044 */
-#define MXC_R_GCR_PERCKCN1                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x048 */
-#define MXC_R_GCR_EVTEN                                                        \
-	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x04C */
-#define MXC_R_GCR_REVISION                                                     \
-	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x050 */
-#define MXC_R_GCR_SYSSIE                                                       \
-	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt>       \
-				    0x0x054 */
-
-/**
- * System Control.
- */
-#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
-#define MXC_F_GCR_SCON_SBUSARB                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
-#define MXC_V_GCR_SCON_SBUSARB_FIX                                             \
-	((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
-#define MXC_S_GCR_SCON_SBUSARB_FIX                                             \
-	(MXC_V_GCR_SCON_SBUSARB_FIX                                            \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
-#define MXC_V_GCR_SCON_SBUSARB_ROUND                                           \
-	((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
-#define MXC_S_GCR_SCON_SBUSARB_ROUND                                           \
-	(MXC_V_GCR_SCON_SBUSARB_ROUND                                          \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
-
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS                                     \
-	4 /**< SCON_FLASH_PAGE_FLIP Position */
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
-							   SCON_FLASH_PAGE_FLIP \
-							   Mask */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
-	((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
-#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
-	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                 \
-	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                           \
-						   SCON_FLASH_PAGE_FLIP_NORMAL \
-						   Setting */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
-	((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
-#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                  \
-	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
-	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                            \
-						   SCON_FLASH_PAGE_FLIP_SWAPPED \
-						   Setting */
-
-#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
-#define MXC_F_GCR_SCON_FPU_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
-#define MXC_V_GCR_SCON_FPU_DIS_ENABLE                                          \
-	((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_FPU_DIS_DISABLE                                         \
-	((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
-
-#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
-#define MXC_F_GCR_SCON_CCACHE_FLUSH                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH    \
-							Mask */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                    \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL     \
-						Setting */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                     \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
-#define MXC_F_GCR_SCON_SWD_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
-#define MXC_V_GCR_SCON_SWD_DIS_ENABLE                                          \
-	((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_SWD_DIS_DISABLE                                         \
-	((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
-
-/**
- * Reset Register 0.
- */
-#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
-#define MXC_F_GCR_RSTR0_DMA                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
-#define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
-#define MXC_S_GCR_RSTR0_DMA_RFU                                                \
-	(MXC_V_GCR_RSTR0_DMA_RFU                                               \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET                                              \
-	(MXC_V_GCR_RSTR0_DMA_RESET                                             \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_DMA_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_DMA_BUSY                                               \
-	(MXC_V_GCR_RSTR0_DMA_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
-#define MXC_F_GCR_RSTR0_WDT                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
-#define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
-#define MXC_S_GCR_RSTR0_WDT_RFU                                                \
-	(MXC_V_GCR_RSTR0_WDT_RFU                                               \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET                                              \
-	(MXC_V_GCR_RSTR0_WDT_RESET                                             \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_WDT_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_WDT_BUSY                                               \
-	(MXC_V_GCR_RSTR0_WDT_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
-#define MXC_F_GCR_RSTR0_GPIO0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
-#define MXC_V_GCR_RSTR0_GPIO0_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RFU                                              \
-	(MXC_V_GCR_RSTR0_GPIO0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET                                            \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
-#define MXC_S_GCR_RSTR0_GPIO0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_GPIO0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
-#define MXC_F_GCR_RSTR0_TIMER0                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
-#define MXC_V_GCR_RSTR0_TIMER0_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER0_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER0_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER0_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER0_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
-#define MXC_F_GCR_RSTR0_TIMER1                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
-#define MXC_V_GCR_RSTR0_TIMER1_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER1_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER1_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER1_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER1_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
-#define MXC_F_GCR_RSTR0_TIMER2                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
-#define MXC_V_GCR_RSTR0_TIMER2_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER2_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_TIMER2_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER2_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER2_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
-#define MXC_F_GCR_RSTR0_UART0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
-#define MXC_V_GCR_RSTR0_UART0_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
-#define MXC_S_GCR_RSTR0_UART0_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART0_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
-#define MXC_F_GCR_RSTR0_UART1                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
-#define MXC_V_GCR_RSTR0_UART1_RFU                                              \
-	((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
-#define MXC_S_GCR_RSTR0_UART1_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART1_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET                                            \
-	((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART1_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET_DONE                                       \
-	((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART1_BUSY                                             \
-	((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART1_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART1_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
-#define MXC_F_GCR_RSTR0_SPI0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SPI0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SPI0_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI0_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
-#define MXC_F_GCR_RSTR0_SPI1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SPI1_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SPI1_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI1_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI1_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI1_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI1_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI1_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
-#define MXC_F_GCR_RSTR0_I2C0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_I2C0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_I2C0_RFU                                               \
-	(MXC_V_GCR_RSTR0_I2C0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET                                             \
-	(MXC_V_GCR_RSTR0_I2C0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_I2C0_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
-#define MXC_S_GCR_RSTR0_I2C0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_I2C0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
-#define MXC_F_GCR_RSTR0_RTC                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
-#define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
-#define MXC_S_GCR_RSTR0_RTC_RFU                                                \
-	(MXC_V_GCR_RSTR0_RTC_RFU                                               \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET                                              \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET                                              \
-	(MXC_V_GCR_RSTR0_RTC_RESET                                             \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET_DONE                                         \
-	((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_RTC_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_RTC_BUSY                                               \
-	(MXC_V_GCR_RSTR0_RTC_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
-#define MXC_F_GCR_RSTR0_SRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_SRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_SRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_SRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_SRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SRST_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_SRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
-#define MXC_F_GCR_RSTR0_PRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask   \
-							 */
-#define MXC_V_GCR_RSTR0_PRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value                            \
-			   */
-#define MXC_S_GCR_RSTR0_PRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_PRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_PRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_PRST_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_PRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_PRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
-
-#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
-#define MXC_F_GCR_RSTR0_SYSTEM                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
-#define MXC_V_GCR_RSTR0_SYSTEM_RFU                                             \
-	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RFU                                             \
-	(MXC_V_GCR_RSTR0_SYSTEM_RFU                                            \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET                                           \
-	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET                                           \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET                                          \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting   \
-					 */
-#define MXC_V_GCR_RSTR0_SYSTEM_BUSY                                            \
-	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                                            \
-	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
-
-/**
- * Clock Control.
- */
-#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
-#define MXC_F_GCR_CLKCN_PSC                                                    \
-	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
-#define MXC_V_GCR_CLKCN_PSC_DIV1                                               \
-	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV1                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV1                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV2                                               \
-	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV2                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV2                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV4                                               \
-	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV4                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV4                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV8                                               \
-	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value                            \
-			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV8                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV8                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV16                                              \
-	((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV16                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV16                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV32                                              \
-	((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV32                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV32                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV64                                              \
-	((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV64                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV64                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV128                                             \
-	((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV128                                             \
-	(MXC_V_GCR_CLKCN_PSC_DIV128                                            \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
-
-#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
-#define MXC_F_GCR_CLKCN_CLKSEL                                                 \
-	((uint32_t)(0x7UL                                                      \
-		    << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
-#define MXC_V_GCR_CLKCN_CLKSEL_HIRC                                            \
-	((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                            \
-	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                                           \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_NANORING                                        \
-	((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                                        \
-	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                                       \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                          \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
-
-#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
-#define MXC_F_GCR_CLKCN_CKRDY                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
-#define MXC_V_GCR_CLKCN_CKRDY_BUSY                                             \
-	((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                             \
-	(MXC_V_GCR_CLKCN_CKRDY_BUSY                                            \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
-#define MXC_V_GCR_CLKCN_CKRDY_READY                                            \
-	((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_READY                                            \
-	(MXC_V_GCR_CLKCN_CKRDY_READY                                           \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
-#define MXC_F_GCR_CLKCN_X32K_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
-#define MXC_V_GCR_CLKCN_X32K_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_X32K_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_X32K_EN_EN                                             \
-	((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_X32K_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
-
-#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
-#define MXC_F_GCR_CLKCN_HIRC_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
-#define MXC_V_GCR_CLKCN_HIRC_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_HIRC_EN_EN                                             \
-	((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_HIRC_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
-
-#define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
-#define MXC_F_GCR_CLKCN_X32K_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
-#define MXC_V_GCR_CLKCN_X32K_RDY_NOT                                           \
-	((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_X32K_RDY_READY                                         \
-	((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_X32K_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
-#define MXC_F_GCR_CLKCN_HIRC_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_READY                                         \
-	((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
-
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY  \
-							   Mask */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting  \
-					     */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                      \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY        \
-					       Setting */
-
-/**
- * Power Management.
- */
-#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
-#define MXC_F_GCR_PM_MODE                                                      \
-	((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
-#define MXC_V_GCR_PM_MODE_ACTIVE                                               \
-	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value                            \
-			   */
-#define MXC_S_GCR_PM_MODE_ACTIVE                                               \
-	(MXC_V_GCR_PM_MODE_ACTIVE                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
-#define MXC_V_GCR_PM_MODE_SHUTDOWN                                             \
-	((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
-#define MXC_S_GCR_PM_MODE_SHUTDOWN                                             \
-	(MXC_V_GCR_PM_MODE_SHUTDOWN                                            \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
-#define MXC_V_GCR_PM_MODE_BACKUP                                               \
-	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value                            \
-			   */
-#define MXC_S_GCR_PM_MODE_BACKUP                                               \
-	(MXC_V_GCR_PM_MODE_BACKUP                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
-
-#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
-#define MXC_F_GCR_PM_GPIOWKEN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
-#define MXC_V_GCR_PM_GPIOWKEN_DIS                                              \
-	((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
-#define MXC_S_GCR_PM_GPIOWKEN_DIS                                              \
-	(MXC_V_GCR_PM_GPIOWKEN_DIS                                             \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
-#define MXC_V_GCR_PM_GPIOWKEN_EN                                               \
-	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value                            \
-			   */
-#define MXC_S_GCR_PM_GPIOWKEN_EN                                               \
-	(MXC_V_GCR_PM_GPIOWKEN_EN                                              \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
-
-#define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
-#define MXC_F_GCR_PM_RTCWKEN                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask   \
-							 */
-#define MXC_V_GCR_PM_RTCWKEN_DIS                                               \
-	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value                            \
-			   */
-#define MXC_S_GCR_PM_RTCWKEN_DIS                                               \
-	(MXC_V_GCR_PM_RTCWKEN_DIS                                              \
-	 << MXC_F_GCR_PM_RTCWKEN_POS)		  /**< PM_RTCWKEN_DIS Setting */
-#define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
-#define MXC_S_GCR_PM_RTCWKEN_EN                                                \
-	(MXC_V_GCR_PM_RTCWKEN_EN                                               \
-	 << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
-
-#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
-#define MXC_F_GCR_PM_HIRCPD                                                    \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
-#define MXC_V_GCR_PM_HIRCPD_ACTIVE                                             \
-	((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
-#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                             \
-	(MXC_V_GCR_PM_HIRCPD_ACTIVE                                            \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
-#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
-#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                         \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
-
-/**
- * Peripheral Clock Divider.
- */
-#define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
-#define MXC_F_GCR_PCKDIV_AONCD                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_4                                           \
-	((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_8                                           \
-	((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_16                                          \
-	((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_32                                          \
-	((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
-
-/**
- * Peripheral Clock Disable.
- */
-#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
-#define MXC_F_GCR_PERCKCN0_GPIO0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
-#define MXC_F_GCR_PERCKCN0_DMAD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
-#define MXC_V_GCR_PERCKCN0_DMAD_EN                                             \
-	((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_EN                                             \
-	(MXC_V_GCR_PERCKCN0_DMAD_EN                                            \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
-#define MXC_V_GCR_PERCKCN0_DMAD_DIS                                            \
-	((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_DIS                                            \
-	(MXC_V_GCR_PERCKCN0_DMAD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
-#define MXC_F_GCR_PERCKCN0_SPI0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI0D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI0D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
-#define MXC_F_GCR_PERCKCN0_SPI1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI1D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI1D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
-#define MXC_F_GCR_PERCKCN0_UART0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART0D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART0D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
-#define MXC_F_GCR_PERCKCN0_UART1D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART1D_EN                                           \
-	((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART1D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART1D_DIS                                          \
-	((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART1D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
-#define MXC_F_GCR_PERCKCN0_I2C0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C0D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C0D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
-#define MXC_F_GCR_PERCKCN0_T0D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
-#define MXC_V_GCR_PERCKCN0_T0D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T0D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T0D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T0D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T0D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T0D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
-#define MXC_F_GCR_PERCKCN0_T1D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
-#define MXC_V_GCR_PERCKCN0_T1D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T1D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T1D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T1D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T1D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T1D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
-#define MXC_F_GCR_PERCKCN0_T2D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
-#define MXC_V_GCR_PERCKCN0_T2D_EN                                              \
-	((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T2D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T2D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T2D_DIS                                             \
-	((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T2D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T2D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
-#define MXC_F_GCR_PERCKCN0_I2C1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C1D_EN                                            \
-	((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C1D_DIS                                           \
-	((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
-
-/**
- * Memory Clock Control Register.
- */
-#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
-#define MXC_F_GCR_MEMCKCN_FWS                                                  \
-	((uint32_t)(                                                           \
-		0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                              \
-						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                              \
-						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                              \
-						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE     \
-						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                              \
-						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP  \
-						Setting */
-
-#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
-#define MXC_F_GCR_MEMCKCN_ICACHELS                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS  \
-							   Mask */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                     \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE       \
-					       Setting */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP  \
-					       Setting */
-
-/**
- * Memory Zeroize Control.
- */
-#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
-#define MXC_F_GCR_MEMZCN_SRAM0Z                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                           \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_START                                          \
-	((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                          \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_START                                         \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
-
-#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
-#define MXC_F_GCR_MEMZCN_ICACHEZ                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                          \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_START                                         \
-	((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_START                                         \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_START                                        \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
-
-/**
- * System Status Register.
- */
-#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
-#define MXC_F_GCR_SYSST_ICECLOCK                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
-#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
-	((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
-	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                     \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \
-					   */
-#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                       \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting   \
-					   */
-
-#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
-#define MXC_F_GCR_SYSST_CODEINTERR                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR  \
-							   Mask */
-#define MXC_V_GCR_SYSST_CODEINTERR_NORM                                        \
-	((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
-#define MXC_S_GCR_SYSST_CODEINTERR_NORM                                        \
-	(MXC_V_GCR_SYSST_CODEINTERR_NORM                                       \
-	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \
-					     */
-#define MXC_V_GCR_SYSST_CODEINTERR_CODE                                        \
-	((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
-#define MXC_S_GCR_SYSST_CODEINTERR_CODE                                        \
-	(MXC_V_GCR_SYSST_CODEINTERR_CODE                                       \
-	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting \
-					     */
-
-#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
-#define MXC_F_GCR_SYSST_SCMEMF                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
-#define MXC_V_GCR_SYSST_SCMEMF_NORM                                            \
-	((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
-#define MXC_S_GCR_SYSST_SCMEMF_NORM                                            \
-	(MXC_V_GCR_SYSST_SCMEMF_NORM                                           \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
-#define MXC_V_GCR_SYSST_SCMEMF_MEMORY                                          \
-	((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
-#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                                          \
-	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                                         \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
-
-/**
- * Reset Register.
- */
-#define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
-#define MXC_F_GCR_RSTR1_I2C1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask   \
-							 */
-#define MXC_V_GCR_RSTR1_I2C1_RESET                                             \
-	((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET                                             \
-	(MXC_V_GCR_RSTR1_I2C1_RESET                                            \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
-#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR1_I2C1_BUSY                                              \
-	((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
-#define MXC_S_GCR_RSTR1_I2C1_BUSY                                              \
-	(MXC_V_GCR_RSTR1_I2C1_BUSY                                             \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
-
-/**
- * Peripheral Clock Disable.
- */
-#define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
-#define MXC_F_GCR_PERCKCN1_FLCD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
-#define MXC_V_GCR_PERCKCN1_FLCD_EN                                             \
-	((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_EN                                             \
-	(MXC_V_GCR_PERCKCN1_FLCD_EN                                            \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
-#define MXC_V_GCR_PERCKCN1_FLCD_DIS                                            \
-	((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_DIS                                            \
-	(MXC_V_GCR_PERCKCN1_FLCD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
-
-#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
-#define MXC_F_GCR_PERCKCN1_ICACHED                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED  \
-							   Mask */
-#define MXC_V_GCR_PERCKCN1_ICACHED_EN                                          \
-	((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                          \
-	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                         \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting   \
-					     */
-#define MXC_V_GCR_PERCKCN1_ICACHED_DIS                                         \
-	((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                         \
-	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                        \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting  \
-					     */
-
-/**
- * Event Enable Register.
- */
-#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
-#define MXC_F_GCR_EVTEN_DMAEVENT                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
-
-#define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
-#define MXC_F_GCR_EVTEN_RXEVENT                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
-
-/**
- * Revision Register.
- */
-#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
-#define MXC_F_GCR_REVISION_REVISION                                            \
-	((uint32_t)(                                                           \
-		0xFFFFUL                                                       \
-		<< MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION    \
-							Mask */
-
-/**
- * System Status Interrupt Enable Register.
- */
-#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
-#define MXC_F_GCR_SYSSIE_ICEULIE                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
-#define MXC_V_GCR_SYSSIE_ICEULIE_DIS                                           \
-	((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                                           \
-	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                                          \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_ICEULIE_EN                                            \
-	((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_EN                                            \
-	(MXC_V_GCR_SYSSIE_ICEULIE_EN                                           \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
-
-#define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
-#define MXC_F_GCR_SYSSIE_CIEIE                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
-#define MXC_V_GCR_SYSSIE_CIEIE_DIS                                             \
-	((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_DIS                                             \
-	(MXC_V_GCR_SYSSIE_CIEIE_DIS                                            \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_CIEIE_EN                                              \
-	((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_EN                                              \
-	(MXC_V_GCR_SYSSIE_CIEIE_EN                                             \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
-
-#define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
-#define MXC_F_GCR_SYSSIE_SCMFIE                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
-#define MXC_V_GCR_SYSSIE_SCMFIE_DIS                                            \
-	((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                                            \
-	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                                           \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_SCMFIE_EN                                             \
-	((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_EN                                             \
-	(MXC_V_GCR_SYSSIE_SCMFIE_EN                                            \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
-
-#endif /* _GCR_REGS_H_ */
diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c
deleted file mode 100644
index 5fe38cd657..0000000000
--- a/chip/max32660/gpio_chip.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "switch.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "registers.h"
-#include "gpio_regs.h"
-
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
-
-/* 0-terminated list of GPIO base addresses */
-static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0};
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-			enum gpio_alternate_func func)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
-
-	switch (func) {
-	case GPIO_ALT_FUNC_1:
-		gpio->en_clr = mask;
-		gpio->en1_clr = mask;
-		break;
-	case GPIO_ALT_FUNC_2:
-		gpio->en_clr = mask;
-		gpio->en1_set = mask;
-		break;
-	case GPIO_ALT_FUNC_3:
-		gpio->en_set = mask;
-		gpio->en1_set = mask;
-		break;
-	default:
-	    /* Default as input */
-		gpio->out_en_clr = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-		break;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	return (gpio->in & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	if (value) {
-		gpio->out_set = gpio_list[signal].mask;
-	} else {
-		gpio->out_clr = gpio_list[signal].mask;
-	}
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
-
-	/* Setup for either an output or input. */
-	if (flags & GPIO_OUTPUT) {
-		gpio->out_en_set = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-	} else {
-		gpio->out_en_clr = mask;
-		gpio->en_set = mask;
-		gpio->en1_clr = mask;
-	}
-
-	/* Handle pull up, pull down or neither. */
-	if (flags & GPIO_PULL_UP) {
-		gpio->pad_cfg1 |= mask;
-		gpio->pad_cfg2 &= ~mask;
-		gpio->ps |= mask;
-	} else if (flags & GPIO_PULL_DOWN) {
-		gpio->pad_cfg1 &= ~mask;
-		gpio->pad_cfg2 |= mask;
-		gpio->ps &= ~mask;
-	} else {
-		/* No pull up/down */
-		gpio->pad_cfg1 &= ~mask;
-		gpio->pad_cfg2 &= ~mask;
-		gpio->ps &= ~mask;
-	}
-
-	/* Handle setting up level interrupts. */
-	if (flags & GPIO_INT_F_HIGH) {
-		/* Level triggered mode. */
-		gpio->int_mod &= ~mask;
-		/* Level high generates interrupt. */
-		gpio->int_pol |= mask;
-	} else if (flags & GPIO_INT_F_LOW) {
-		/* Level triggered mode. */
-		gpio->int_mod &= ~mask;
-		/* Level low generates interrupt. */
-		gpio->int_pol &= ~mask;
-	}
-
-	/* Handle setting up edge interrupts. */
-	if (flags & GPIO_INT_F_RISING) {
-		/* Edge triggered mode. */
-		gpio->int_mod |= mask;
-		/* Rising edge generates interrupt. */
-		gpio->int_pol |= mask;
-	} else if (flags & GPIO_INT_F_FALLING) {
-		/* Edge triggered mode. */
-		gpio->int_mod |= mask;
-		/* Falling edge generates interrupt. */
-		gpio->int_pol &= ~mask;
-	}
-
-	/* Handle interrupting on both edges. */
-	if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) {
-		/* Dual edge triggered mode. */
-		gpio->int_dual_edge |= mask;
-	} else {
-		/* Not dual edge triggered mode. */
-		gpio->int_dual_edge &= ~mask;
-	}
-
-	/* Set the gpio pin high or low. */
-	if (flags & GPIO_HIGH) {
-		gpio->out_set = mask;
-	} else if (flags & GPIO_LOW) {
-		gpio->out_clr = mask;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_en_set = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_en_clr = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port);
-
-	gpio->int_clr = gpio_list[signal].mask;
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-
-	/* Mask all GPIO interrupts */
-	for (i = 0; gpio_bases[i]; i++)
-		gpio_bases[i]->int_en = 0;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-static void gpio_init(void)
-{
-	/*
-	 * Enable global GPIO0 Port interrupt. Note that interrupts still need to be
-	 * enabled at the per pin level.
-	 */
-	task_enable_irq(EC_GPIO0_IRQn);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * port		GPIO port
- * mis		Masked interrupt status value for that port
- */
-static void gpio_interrupt(int port, uint32_t mis)
-{
-	int i = 0;
-	const struct gpio_info *g = gpio_list;
-
-	for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) {
-		if (port == g->port && (mis & g->mask)) {
-			gpio_irq_handlers[i](i);
-			mis &= ~g->mask;
-		}
-	}
-}
-
-/**
- * Handlers for each GPIO port. Read the interrupt status, call the common GPIO
- * interrupt handler and clear the GPIO hardware interrupt status.
- */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                                       \
-	void irqfunc(void)                                                     \
-	{                                                                      \
-		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase);           \
-		uint32_t mis = gpio->int_stat;                                 \
-		gpio_interrupt(gpiobase, mis);                                 \
-		gpio->int_clr = mis;                                           \
-	}
-
-GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0);
-#undef GPIO_IRQ_FUNC
-DECLARE_IRQ(EC_GPIO0_IRQn, __gpio_0_interrupt, 1);
diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h
deleted file mode 100644
index 1c6fcf7a71..0000000000
--- a/chip/max32660/gpio_regs.h
+++ /dev/null
@@ -1,866 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the GPIO Peripheral
- * Module */
-
-#ifndef _GPIO_REGS_H_
-#define _GPIO_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * gpio
- * Individual I/O for each GPIO
- */
-
-/**
- * gpio_registers
- * Structure type to access the GPIO Registers.
- */
-typedef struct {
-	__IO uint32_t en;     /**< <tt>\b 0x00:<\tt> GPIO EN Register */
-	__IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */
-	__IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */
-	__IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */
-	__IO uint32_t
-		out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */
-	__IO uint32_t
-		out_en_clr;   /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */
-	__IO uint32_t out;    /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
-	__O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */
-	__O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */
-	__I uint32_t in;      /**< <tt>\b 0x24:<\tt> GPIO IN Register */
-	__IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */
-	__IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */
-	__R uint32_t rsv_0x30;
-	__IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */
-	__IO uint32_t
-		int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */
-	__IO uint32_t
-		int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */
-	__I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */
-	__R uint32_t rsv_0x44;
-	__IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */
-	__IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */
-	__IO uint32_t
-		wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */
-	__IO uint32_t
-		wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */
-	__R uint32_t rsv_0x58;
-	__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE
-					Register */
-	__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */
-	__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */
-	__IO uint32_t en1;      /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
-	__IO uint32_t en1_set;  /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
-	__IO uint32_t en1_clr;  /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
-	__IO uint32_t en2;      /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
-	__IO uint32_t en2_set;  /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
-	__IO uint32_t en2_clr;  /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
-	__R uint32_t rsv_0x80_0xa7[10];
-	__IO uint32_t is;  /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
-	__IO uint32_t sr;  /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
-	__IO uint32_t ds;  /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
-	__IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */
-	__IO uint32_t ps;  /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
-	__R uint32_t rsv_0xbc;
-	__IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */
-} mxc_gpio_regs_t;
-
-#define PIN_0 ((uint32_t)(1UL << 0))   /**< Pin 0 Define */
-#define PIN_1 ((uint32_t)(1UL << 1))   /**< Pin 1 Define */
-#define PIN_2 ((uint32_t)(1UL << 2))   /**< Pin 2 Define */
-#define PIN_3 ((uint32_t)(1UL << 3))   /**< Pin 3 Define */
-#define PIN_4 ((uint32_t)(1UL << 4))   /**< Pin 4 Define */
-#define PIN_5 ((uint32_t)(1UL << 5))   /**< Pin 5 Define */
-#define PIN_6 ((uint32_t)(1UL << 6))   /**< Pin 6 Define */
-#define PIN_7 ((uint32_t)(1UL << 7))   /**< Pin 7 Define */
-#define PIN_8 ((uint32_t)(1UL << 8))   /**< Pin 8 Define */
-#define PIN_9 ((uint32_t)(1UL << 9))   /**< Pin 9 Define */
-#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
-#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
-#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
-#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */
-#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */
-#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */
-#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */
-#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */
-#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */
-#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */
-#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */
-#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */
-#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */
-#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */
-#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */
-#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */
-#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */
-#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */
-#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */
-#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */
-#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */
-#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */
-
-/**
- * Enumeration type for the GPIO Function Type
- */
-typedef enum {
-	GPIO_FUNC_IN,   /**< GPIO Input */
-	GPIO_FUNC_OUT,  /**< GPIO Output */
-	GPIO_FUNC_ALT1, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT2, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT3, /**< Alternate Function Selection */
-	GPIO_FUNC_ALT4, /**< Alternate Function Selection */
-} gpio_func_t;
-
-/**
- * Enumeration type for the type of GPIO pad on a given pin.
- */
-typedef enum {
-	GPIO_PAD_NONE,      /**< No pull-up or pull-down */
-	GPIO_PAD_PULL_UP,   /**< Set pad to weak pull-up */
-	GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
-} gpio_pad_t;
-
-/**
- * Structure type for configuring a GPIO port.
- */
-typedef struct {
-	uint32_t port;    /**< Index of GPIO port */
-	uint32_t mask;    /**< Pin mask (multiple pins may be set) */
-	gpio_func_t func; /**< Function type */
-	gpio_pad_t pad;   /**< Pad type */
-} gpio_cfg_t;
-
-typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t;
-
-typedef enum {
-	GPIO_INTERRUPT_FALLING = 0, /**< Interrupt triggers on falling edge */
-	GPIO_INTERRUPT_HIGH = GPIO_INTERRUPT_FALLING, /**< Interrupt triggers
-							 when level is high */
-	GPIO_INTERRUPT_RISING, /**< Interrupt triggers on rising edge */
-	GPIO_INTERRUPT_LOW = GPIO_INTERRUPT_RISING, /**< Interrupt triggers when
-						       level is low */
-	GPIO_INTERRUPT_BOTH /**< Interrupt triggers on either edge */
-} gpio_int_pol_t;
-
-/* Register offsets for module GPIO */
-#define MXC_R_GPIO_EN                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x000 */
-#define MXC_R_GPIO_EN_SET                                                      \
-	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x004 */
-#define MXC_R_GPIO_EN_CLR                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x008 */
-#define MXC_R_GPIO_OUT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x00C */
-#define MXC_R_GPIO_OUT_EN_SET                                                  \
-	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x010 */
-#define MXC_R_GPIO_OUT_EN_CLR                                                  \
-	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x014 */
-#define MXC_R_GPIO_OUT                                                         \
-	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x018 */
-#define MXC_R_GPIO_OUT_SET                                                     \
-	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x01C */
-#define MXC_R_GPIO_OUT_CLR                                                     \
-	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x020 */
-#define MXC_R_GPIO_IN                                                          \
-	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x024 */
-#define MXC_R_GPIO_INT_MOD                                                     \
-	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x028 */
-#define MXC_R_GPIO_INT_POL                                                     \
-	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x02C */
-#define MXC_R_GPIO_INT_EN                                                      \
-	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x034 */
-#define MXC_R_GPIO_INT_EN_SET                                                  \
-	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x038 */
-#define MXC_R_GPIO_INT_EN_CLR                                                  \
-	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x03C */
-#define MXC_R_GPIO_INT_STAT                                                    \
-	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x040 */
-#define MXC_R_GPIO_INT_CLR                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x048 */
-#define MXC_R_GPIO_WAKE_EN                                                     \
-	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x04C */
-#define MXC_R_GPIO_WAKE_EN_SET                                                 \
-	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x050 */
-#define MXC_R_GPIO_WAKE_EN_CLR                                                 \
-	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x054 */
-#define MXC_R_GPIO_INT_DUAL_EDGE                                               \
-	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x05C */
-#define MXC_R_GPIO_PAD_CFG1                                                    \
-	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x060 */
-#define MXC_R_GPIO_PAD_CFG2                                                    \
-	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x064 */
-#define MXC_R_GPIO_EN1                                                         \
-	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x068 */
-#define MXC_R_GPIO_EN1_SET                                                     \
-	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x06C */
-#define MXC_R_GPIO_EN1_CLR                                                     \
-	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x070 */
-#define MXC_R_GPIO_EN2                                                         \
-	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x074 */
-#define MXC_R_GPIO_EN2_SET                                                     \
-	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x078 */
-#define MXC_R_GPIO_EN2_CLR                                                     \
-	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x07C */
-#define MXC_R_GPIO_IS                                                          \
-	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0A8 */
-#define MXC_R_GPIO_SR                                                          \
-	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0AC */
-#define MXC_R_GPIO_DS                                                          \
-	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B0 */
-#define MXC_R_GPIO_DS1                                                         \
-	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B4 */
-#define MXC_R_GPIO_PS                                                          \
-	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0B8 */
-#define MXC_R_GPIO_VSSEL                                                       \
-	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>      \
-				    0x0x0C0 */
-
-/**
- * GPIO Function Enable Register. Each bit controls the GPIO_EN
- * setting for one GPIO pin on the associated port.
- */
-#define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
-#define MXC_F_GPIO_EN_GPIO_EN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
-#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
-#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                       \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
-#define MXC_V_GPIO_EN_GPIO_EN_GPIO                                             \
-	((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
-#define MXC_S_GPIO_EN_GPIO_EN_GPIO                                             \
-	(MXC_V_GPIO_EN_GPIO_EN_GPIO                                            \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
-
-/**
- * GPIO Set Function Enable Register. Writing a 1 to one or more bits
- * in this register sets the bits in the same positions in GPIO_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
-#define MXC_F_GPIO_EN_SET_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
-
-/**
- * GPIO Clear Function Enable Register. Writing a 1 to one or more
- * bits in this register clears the bits in the same positions in GPIO_EN to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
-#define MXC_F_GPIO_EN_CLR_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
-
-/**
- * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN
- * setting for one GPIO pin in the associated port.
- */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS                                      \
-	0 /**< OUT_EN_GPIO_OUT_EN Position                                     \
-	   */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \
-							  Mask */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                     \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS     \
-						  Setting */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                      \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN      \
-						  Setting */
-
-/**
- * GPIO Output Enable Set Function Enable Register. Writing a 1 to one
- * or more bits in this register sets the bits in the same positions in
- * GPIO_OUT_EN to 1, without affecting other bits in that register.
- */
-#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
-#define MXC_F_GPIO_OUT_EN_SET_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
-
-/**
- * GPIO Output Enable Clear Function Enable Register. Writing a 1 to
- * one or more bits in this register clears the bits in the same positions in
- * GPIO_OUT_EN to 0, without affecting other bits in that register.
- */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
-
-/**
- * GPIO Output Register. Each bit controls the GPIO_OUT setting for
- * one pin in the associated port.  This register can be written either
- * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
- */
-#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
-#define MXC_F_GPIO_OUT_GPIO_OUT                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
-#define MXC_V_GPIO_OUT_GPIO_OUT_LOW                                            \
-	((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                                            \
-	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                                           \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
-#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                          \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
-
-/**
- * GPIO Output Set. Writing a 1 to one or more bits in this register
- * sets the bits in the same positions in GPIO_OUT to 1, without affecting other
- * bits in that register.
- */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS                                    \
-	0 /**< OUT_SET_GPIO_OUT_SET Position */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
-							    OUT_SET_GPIO_OUT_SET \
-							    Mask */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO  \
-						    Setting */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
-	((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                   \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET \
-						    Setting */
-/**
- * GPIO Output Clear. Writing a 1 to one or more bits in this register
- * clears the bits in the same positions in GPIO_OUT to 0, without affecting
- * other bits in that register.
- */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS                                    \
-	0 /**< OUT_CLR_GPIO_OUT_CLR Position */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
-							    OUT_CLR_GPIO_OUT_CLR \
-							    Mask */
-
-/**
- * GPIO Input Register. Read-only register to read from the logic
- * states of the GPIO pins on this port.
- */
-#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
-#define MXC_F_GPIO_IN_GPIO_IN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
-
-/**
- * GPIO Interrupt Mode Register. Each bit in this register controls
- * the interrupt mode setting for the associated GPIO pin on this port.
- */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS                                    \
-	0 /**< INT_MOD_GPIO_INT_MOD Position */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
-							    INT_MOD_GPIO_INT_MOD \
-							    Mask */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
-	((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                 \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_LEVEL \
-						    Setting */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_EDGE  \
-						    Setting */
-
-/**
- * GPIO Interrupt Polarity Register. Each bit in this register
- * controls the interrupt polarity setting for one GPIO pin in the associated
- * port.
- */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS                                    \
-	0 /**< INT_POL_GPIO_INT_POL Position */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
-							    INT_POL_GPIO_INT_POL \
-							    Mask */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                \
-	((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
-#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING                                  \
-	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                 \
-	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                            \
-						    INT_POL_GPIO_INT_POL_FALLING \
-						    Setting */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
-	((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
-#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING                                  \
-	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
-	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                           \
-						    INT_POL_GPIO_INT_POL_RISING \
-						    Setting */
-
-/**
- * GPIO Interrupt Enable Register. Each bit in this register controls
- * the GPIO interrupt enable for the associated pin on the GPIO port.
- */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS                                      \
-	0 /**< INT_EN_GPIO_INT_EN Position                                     \
-	   */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \
-							  Mask */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                     \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS     \
-						  Setting */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                      \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN      \
-						  Setting */
-
-/**
- * GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this
- * register sets the bits in the same positions in GPIO_INT_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS                              \
-	0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
-								  INT_EN_SET_GPIO_INT_EN_SET \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                               \
-	((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
-#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                        \
-	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                       \
-	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                             \
-							  INT_EN_SET_GPIO_INT_EN_SET_NO \
-							  Setting */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                              \
-	((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
-#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                        \
-	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                       \
-	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                              \
-							  INT_EN_SET_GPIO_INT_EN_SET_SET \
-							  Setting */
-/**
- * GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in
- * this register clears the bits in the same positions in GPIO_INT_EN to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS                              \
-	0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
-								  INT_EN_CLR_GPIO_INT_EN_CLR \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                               \
-	((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
-#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                        \
-	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                       \
-	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                             \
-							  INT_EN_CLR_GPIO_INT_EN_CLR_NO \
-							  Setting */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                            \
-	((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
-#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                        \
-	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                       \
-	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                                \
-							  INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \
-							  Setting */
-/**
- * GPIO Interrupt Status Register. Each bit in this register contains
- * the pending interrupt status for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS                                  \
-	0 /**< INT_STAT_GPIO_INT_STAT Position */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
-							      INT_STAT_GPIO_INT_STAT \
-							      Mask */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
-	((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
-#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO                                    \
-	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
-	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                         \
-						      INT_STAT_GPIO_INT_STAT_NO \
-						      Setting */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                              \
-	((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
-#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                    \
-	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                   \
-	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                              \
-						      INT_STAT_GPIO_INT_STAT_PENDING \
-						      Setting */
-
-/**
- * GPIO Status Clear. Writing a 1 to one or more bits in this register
- * clears the bits in the same positions in GPIO_INT_STAT to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
-#define MXC_F_GPIO_INT_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
-
-/**
- * GPIO Wake Enable Register. Each bit in this register controls the
- * PMU wakeup enable for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS                                    \
-	0 /**< WAKE_EN_GPIO_WAKE_EN Position */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
-							    WAKE_EN_GPIO_WAKE_EN \
-							    Mask */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
-	((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                   \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \
-						    Setting */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN  \
-						    Setting */
-
-/**
- * GPIO Wake Enable Set. Writing a 1 to one or more bits in this
- * register sets the bits in the same positions in GPIO_WAKE_EN to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL   \
-							   Mask */
-
-/**
- * GPIO Wake Enable Clear. Writing a 1 to one or more bits in this
- * register clears the bits in the same positions in GPIO_WAKE_EN to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL   \
-							   Mask */
-
-/**
- * GPIO Interrupt Dual Edge Mode Register. Each bit in this register
- * selects dual edge mode for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS                        \
-	0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                      \
-	((uint32_t)(                                                                                     \
-		0xFFFFFFFFUL                                                                             \
-		<< MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
-									INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
-									Mask                             \
-								      */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                         \
-	((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
-#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                              \
-	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                             \
-	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
-								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
-								Setting */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                         \
-	((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
-#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                              \
-	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                             \
-	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
-								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \
-								Setting */
-
-/**
- * GPIO Input Mode Config 1. Each bit in this register enables the
- * weak pull-up for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS                                  \
-	0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
-							      PAD_CFG1_GPIO_PAD_CFG1 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                            \
-	((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                                \
-						      PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
-	((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
-						      PAD_CFG1_GPIO_PAD_CFG1_PU \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
-	((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
-#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                    \
-	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
-	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
-						      PAD_CFG1_GPIO_PAD_CFG1_PD \
-						      Setting */
-
-/**
- * GPIO Input Mode Config 2. Each bit in this register enables the
- * weak pull-up for the associated GPIO pin in this port.
- */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS                                  \
-	0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
-							      PAD_CFG2_GPIO_PAD_CFG2 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                            \
-	((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                                \
-						      PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
-	((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
-						      PAD_CFG2_GPIO_PAD_CFG2_PU \
-						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
-	((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
-#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                    \
-	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
-	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
-						      PAD_CFG2_GPIO_PAD_CFG2_PD \
-						      Setting */
-
-/**
- * GPIO Alternate Function Enable Register. Each bit in this register
- * selects between primary/secondary functions for the associated GPIO pin in
- * this port.
- */
-#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
-#define MXC_F_GPIO_EN1_GPIO_EN1                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
-#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                       \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
-#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                     \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting   \
-					  */
-
-/**
- * GPIO Alternate Function Set. Writing a 1 to one or more bits in
- * this register sets the bits in the same positions in GPIO_EN1 to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
-#define MXC_F_GPIO_EN1_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
-
-/**
- * GPIO Alternate Function Clear. Writing a 1 to one or more bits in
- * this register clears the bits in the same positions in GPIO_EN1 to 0, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
-#define MXC_F_GPIO_EN1_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
-
-/**
- * GPIO Alternate Function Enable Register. Each bit in this register
- * selects between primary/secondary functions for the associated GPIO pin in
- * this port.
- */
-#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
-#define MXC_F_GPIO_EN2_GPIO_EN2                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
-#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                       \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
-#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                     \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting   \
-					  */
-
-/**
- * GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in
- * this register sets the bits in the same positions in GPIO_EN2 to 1, without
- * affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
-#define MXC_F_GPIO_EN2_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
-
-/**
- * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits
- * in this register clears the bits in the same positions in GPIO_EN2 to 0,
- * without affecting other bits in that register.
- */
-#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
-#define MXC_F_GPIO_EN2_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
-
-/**
- * GPIO Drive Strength  Register. Each bit in this register selects
- * the drive strength for the associated GPIO pin in this port. Refer to the
- * Datasheet for sink/source current of GPIO pins in each mode.
- */
-#define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
-#define MXC_F_GPIO_DS_DS                                                       \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
-#define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
-#define MXC_S_GPIO_DS_DS_LD                                                    \
-	(MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
-#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL)	 /**< DS_DS_HD Value */
-#define MXC_S_GPIO_DS_DS_HD                                                    \
-	(MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
-
-/**
- * GPIO Drive Strength 1 Register. Each bit in this register selects
- * the drive strength for the associated GPIO pin in this port. Refer to the
- * Datasheet for sink/source current of GPIO pins in each mode.
- */
-#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
-#define MXC_F_GPIO_DS1_ALL                                                     \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
-
-/**
- * GPIO Pull Select Mode.
- */
-#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
-#define MXC_F_GPIO_PS_ALL                                                      \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask   \
-							     */
-
-/**
- * GPIO Voltage Select.
- */
-#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
-#define MXC_F_GPIO_VSSEL_ALL                                                   \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
-
-#endif /* _GPIO_REGS_H_ */
diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c
deleted file mode 100644
index 5417e161b2..0000000000
--- a/chip/max32660/hwtimer_chip.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 HW Timer module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "task.h"
-#include "timer.h"
-#include "registers.h"
-#include "tmr_regs.h"
-#include "gcr_regs.h"
-
-/* Define the rollover timer */
-#define TMR_ROLLOVER MXC_TMR0
-#define TMR_ROLLOVER_IRQ EC_TMR0_IRQn
-
-/* Define the event timer */
-#define TMR_EVENT MXC_TMR1
-#define TMR_EVENT_IRQ EC_TMR1_IRQn
-
-#define ROLLOVER_EVENT 1
-#define NOT_ROLLOVER_EVENT 0
-
-#define TMR_PRESCALER MXC_V_TMR_CN_PRES_DIV8
-#define TMR_DIV (1 << TMR_PRESCALER)
-
-/* The frequency of timer using the prescaler */
-#define TIMER_FREQ_HZ (PeripheralClock / TMR_DIV)
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-static uint32_t last_deadline;
-
-/* brief Timer prescaler values */
-enum tmr_pres {
-	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1,     /// Divide input clock by 1
-	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2,     /// Divide input clock by 2
-	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4,     /// Divide input clock by 4
-	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8,     /// Divide input clock by 8
-	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16,   /// Divide input clock by 16
-	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32,   /// Divide input clock by 32
-	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64,   /// Divide input clock by 64
-	TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128
-	TMR_PRES_256 =
-		(0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256
-	TMR_PRES_512 =
-		(0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512
-	TMR_PRES_1024 =
-		(0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024
-	TMR_PRES_2048 =
-		(0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048
-	TMR_PRES_4096 =
-		(0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096
-};
-
-/* Timer modes */
-enum tmr_mode {
-	TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT
-	TMR_MODE_CONTINUOUS =
-		MXC_V_TMR_CN_TMODE_CONTINUOUS,	 /// Timer Mode CONTINUOUS
-	TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER
-	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM,	 /// Timer Mode PWM
-	TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE
-	TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE
-	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED,     /// Timer Mode GATED
-	TMR_MODE_CAPTURE_COMPARE =
-		MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
-};
-
-/*
- * Calculate the number of microseconds for a given timer tick
- */
-static inline uint32_t ticks_to_usecs(uint32_t ticks)
-{
-	return (uint64_t)ticks * SECOND / TIMER_FREQ_HZ;
-}
-
-/*
- * Calculate the number of timer ticks for a given microsecond value
- */
-static inline uint32_t usecs_to_ticks(uint32_t usecs)
-{
-	return ((uint64_t)(usecs)*TIMER_FREQ_HZ / SECOND);
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t event_time_us;
-	uint32_t event_time_ticks;
-	uint32_t time_now;
-
-	last_deadline = deadline;
-	time_now = __hw_clock_source_read();
-
-	/* check if the deadline has rolled over */
-	if (deadline < time_now) {
-		event_time_us = (0xFFFFFFFF - time_now) + deadline;
-	} else {
-		/* How long from the current time to the deadline? */
-		event_time_us = (deadline - __hw_clock_source_read());
-	}
-
-	/* Convert event_time to ticks rounding up */
-	event_time_ticks = usecs_to_ticks(event_time_us) + 1;
-
-	/* set the event time into the timer compare */
-	TMR_EVENT->cmp = event_time_ticks;
-	/* zero out the timer */
-	TMR_EVENT->cnt = 0;
-	TMR_EVENT->cn |= MXC_F_TMR_CN_TEN;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	TMR_EVENT->cn &= ~(MXC_F_TMR_CN_TEN);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t timer_count_ticks;
-
-	/* Read the timer value and return the results in microseconds */
-	timer_count_ticks = TMR_ROLLOVER->cnt;
-	return ticks_to_usecs(timer_count_ticks);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	uint32_t timer_count_ticks;
-	timer_count_ticks = usecs_to_ticks(ts);
-	TMR_ROLLOVER->cnt = timer_count_ticks;
-}
-
-/**
- * Interrupt handler for Timer
- */
-static void __timer_event_isr(void)
-{
-	/* Clear the event timer */
-	TMR_EVENT->intr = MXC_F_TMR_INTR_IRQ_CLR;
-	/* Process the timer, pass in that this was NOT a rollover event */
-	if (TMR_ROLLOVER->intr) {
-		TMR_ROLLOVER->intr = MXC_F_TMR_INTR_IRQ_CLR;
-		process_timers(ROLLOVER_EVENT);
-	} else {
-		process_timers(NOT_ROLLOVER_EVENT);
-	}
-}
-/*
- * Declare the EC Timer lower in priority than the I2C interrupt. This
- * allows the I2C driver to process time sensitive interrupts.
- */
-DECLARE_IRQ(EC_TMR1_IRQn, __timer_event_isr, 2);
-
-static void init_timer(mxc_tmr_regs_t *timer, enum tmr_pres prescaler,
-		       enum tmr_mode mode, uint32_t count)
-{
-	/* Disable the Timer */
-	timer->cn &= ~(MXC_F_TMR_CN_TEN);
-
-	if (timer == MXC_TMR0) {
-		/* Enable Timer 0 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T0D);
-	} else if (timer == MXC_TMR1) {
-		/* Enable Timer 1 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T1D);
-	} else if (timer == MXC_TMR2) {
-		/* Enable Timer 2 Clock */
-		MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T2D);
-	}
-
-	/* Disable timer and clear settings */
-	timer->cn = 0;
-
-	/* Clear interrupt flag */
-	timer->intr = MXC_F_TMR_INTR_IRQ_CLR;
-
-	/* Set the prescaler */
-	timer->cn = (prescaler << MXC_F_TMR_CN_PRES_POS);
-
-	/* Configure the timer */
-	timer->cn = (timer->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
-		    ((mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) |
-		    ((0 << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
-
-	timer->cnt = 0x1;
-	timer->cmp = count;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* Initialize two timers, one for the OS Rollover and one for the OS
-	 * Events */
-	init_timer(TMR_ROLLOVER, TMR_PRESCALER, TMR_MODE_CONTINUOUS,
-		   0xffffffff);
-	init_timer(TMR_EVENT, TMR_PRESCALER, TMR_MODE_COMPARE, 0x0);
-	__hw_clock_source_set(start_t);
-
-	/* Enable the timers */
-	TMR_ROLLOVER->cn |= MXC_F_TMR_CN_TEN;
-	TMR_EVENT->cn |= MXC_F_TMR_CN_TEN;
-
-	/* Enable the IRQ */
-	task_enable_irq(TMR_EVENT_IRQ);
-
-	/* Return the Event timer IRQ number (NOT the Rollover IRQ) */
-	return TMR_EVENT_IRQ;
-}
-
-static int hwtimer_display(int argc, char **argv)
-{
-	CPRINTS(" TMR_EVENT count 0x%08x", TMR_EVENT->cnt);
-	CPRINTS(" TMR_ROLLOVER count 0x%08x", TMR_ROLLOVER->cnt);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hwtimer, hwtimer_display, "hwtimer",
-			"Display hwtimer counts");
diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c
deleted file mode 100644
index f28e85f0ca..0000000000
--- a/chip/max32660/i2c_chip.c
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 I2C port module for Chrome EC. */
-
-#include <stdint.h>
-#include <stddef.h>
-#include "common.h"
-#include "config_chip.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "stdbool.h"
-#include "system.h"
-#include "task.h"
-#include "registers.h"
-#include "i2c_regs.h"
-
-/**
- * Byte to use if the EC HOST requested more data
- * than the I2C Slave is able to send.
- */
-#define EC_PADDING_BYTE 0xec
-
-/* **** Definitions **** */
-#define I2C_ERROR \
-	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \
-	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \
-	 MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
-	 MXC_F_I2C_INT_FL0_STOP_ER)
-
-#define T_LOW_MIN (160) /* tLOW minimum in nanoseconds */
-#define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */
-#define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */
-#define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */
-#define T_AF_MIN (10)	/* tAF minimun in nanoseconds */
-
-/**
- * typedef i2c_speed_t - I2C speed modes.
- * @I2C_STD_MODE: 100KHz bus speed
- * @I2C_FAST_MODE: 400KHz Bus Speed
- * @I2C_FASTPLUS_MODE: 1MHz Bus Speed
- * @I2C_HS_MODE: 3.4MHz Bus Speed
- */
-typedef enum {
-	I2C_STD_MODE = 100000,
-	I2C_FAST_MODE = 400000,
-	I2C_FASTPLUS_MODE = 1000000,
-	I2C_HS_MODE = 3400000
-} i2c_speed_t;
-
-/**
- * typedef i2c_autoflush_disable_t - Enable/Disable TXFIFO Autoflush mode.
- */
-typedef enum {
-	I2C_AUTOFLUSH_ENABLE = 0,
-	I2C_AUTOFLUSH_DISABLE = 1
-} i2c_autoflush_disable_t;
-
-/**
- * typedef i2c_master_state_t - Available transaction states for I2C Master.
- */
-typedef enum {
-	I2C_MASTER_IDLE = 1,
-	I2C_MASTER_START = 2,
-	I2C_MASTER_WRITE_COMPLETE = 3,
-	I2C_MASTER_READ_COMPLETE = 4
-} i2c_master_state_t;
-
-/**
- * typedef i2c_slave_state_t - Available transaction states for I2C Slave.
- */
-typedef enum {
-	I2C_SLAVE_WRITE_COMPLETE = 0,
-	I2C_SLAVE_ADDR_MATCH_READ = 1,
-	I2C_SLAVE_ADDR_MATCH_WRITE = 2,
-} i2c_slave_state_t;
-
-/**
- * typedef i2c_req_t - I2C Transaction request.
- */
-typedef struct i2c_req i2c_req_t;
-
-/**
- * typedef i2c_req_state_t - Saves the state of the non-blocking requests.
- * @req: Pointer to I2C transaction request information.
- */
-typedef struct {
-	i2c_req_t *req;
-} i2c_req_state_t;
-
-/**
- * struct i2c_req - I2C Transaction request.
- * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0.
- * 	  Only supports 7-bit addressing. LSb of the given
- * 	  address will be used as the read/write bit, the addr
- * 	  will not be shifted. Used for both master and slave
- * 	  transactions.
- * @addr_match_flag: Indicates which slave address was matched.
- *                   0x1 indicates first slave address matched.
- *                   0x2 indicates second slave address matched.
- *                   0x4 indicates third slave address matched.
- *                   0x8 indicates fourth slave address matched.
- * @tx_data: Data for master write/slave read.
- * @rx_data: Data for master read/slave write.
- * @received_count:  Number of rx bytes sent.
- * @tx_remain: Number of bytes to transmit to the master. This
- *             value is -1 if should clock stretch, 0 if start
- *             sending EC_PADDING_BYTE.  Any other values in this
- *             field will transmit data to the Master.
- * @state: I2C slave state that indicates address match, read and
- *         write status.
- * @restart: Restart or stop bit indicator.
- *           0 to send a stop bit at the end of the transaction
- *           Non-zero to send a restart at end of the transaction
- *           Only used for Master transactions.
- * @response_pending: Indicates that a response to the I2C master
- *           is pending.
- * @expecting_done: Indicates if an I2C done flag is expected. This
- *           is used by the driver to determine the order to process
- *           the flags.
- * @expecting_start: Indicates if an I2C start flag is expected. This
- *           is used by the driver to determine the order to process
- *           the flags.
- */
-struct i2c_req {
-	uint8_t addr;
-	uint8_t addr_match_flag;
-	const uint8_t *tx_data;
-	uint8_t *rx_data;
-	volatile unsigned received_count;
-	volatile int tx_remain;
-	volatile i2c_slave_state_t state;
-	volatile int restart;
-	volatile bool response_pending;
-	volatile bool expecting_done;
-	volatile bool expecting_start;
-};
-
-static i2c_req_state_t states[MXC_I2C_INSTANCES];
-
-/**
- * struct i2c_port_data
- * @out: Output data pointer.
- * @out_size: Output data to transfer, in bytes.
- * @in: Input data pointer.
- * @in_size: Input data to transfer, in bytes.
- * @flags: Flags (I2C_XFER_*).
- * @idx: Index into input/output data.
- * @err: Error code, if any.
- * @timeout_us:	Transaction timeout, or 0 to use default.
- * @task_waiting: Task waiting on port, or TASK_ID_INVALID if none.
- */
-struct i2c_port_data {
-	const uint8_t *out;
-	int out_size;
-	uint8_t *in;
-	int in_size;
-	int flags;
-	int idx;
-	int err;
-	uint32_t timeout_us;
-	volatile int task_waiting;
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-/* **** Function Prototypes **** */
-static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len,
-			    int restart);
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-static void init_i2cs(int port);
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c);
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/* Port address for each I2C */
-static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-static void i2c_send_board_response(int len);
-static void i2c_process_board_command(int read, int addr, int len);
-void board_i2c_process(int read, uint8_t addr, int len, char *buffer,
-		       void (*send_response)(int len));
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/**
- * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes.
- * @port: Port to access
- * @slave_addr:	Slave device address
- * @out: Data to send
- * @out_size: Number of bytes to send
- * @in: Destination buffer for received data
- * @in_size: Number of bytes to receive
- * @flags: Flags (see I2C_XFER_* above)
- *
- * Chip-level function to transmit one block of raw data, then receive one
- * block of raw data.
- *
- * This is a low-level chip-dependent function and should only be called by
- * i2c_xfer().\
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out,
-		  int out_size, uint8_t *in, int in_size, int flags)
-{
-	int xfer_start;
-	int xfer_stop;
-	int status;
-
-	xfer_start = flags & I2C_XFER_START;
-	xfer_stop = flags & I2C_XFER_STOP;
-
-	if (out_size) {
-		status = i2c_master_write(i2c_bus_ports[port], slave_addr_flags,
-					  xfer_start, xfer_stop, out, out_size,
-					  1);
-		if (status != EC_SUCCESS) {
-			return status;
-		}
-	}
-	if (in_size) {
-		status = i2c_master_read(i2c_bus_ports[port], slave_addr_flags,
-					 xfer_start, xfer_stop, in, in_size, 0);
-		if (status != EC_SUCCESS) {
-			return status;
-		}
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_get_line_levels() - Read the current digital levels on the I2C pins.
- * @port: Port number to use when reading line levels.
- *
- * Return a byte where bit 0 is the line level of SCL and
- * bit 1 is the line level of SDA.
- */
-int i2c_get_line_levels(int port)
-{
-	/* Retrieve the current levels of SCL and SDA from the control reg. */
-	return (i2c_bus_ports[port]->ctrl >> MXC_F_I2C_CTRL_SCL_POS) & 0x03;
-}
-
-/**
- * i2c_set_timeout()
- * @port: Port number to set timeout for.
- * @timeout: Timeout duration in microseconds.
- */
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/**
- * i2c_init() - Initialize the I2C ports used on device.
- */
-void i2c_init(void)
-{
-	int i;
-	int port;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Initialize all I2C ports used. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		port = i2c_ports[i].port;
-		i2c_init_peripheral(i2c_bus_ports[port],
-				    i2c_ports[i].kbps * 1000);
-		i2c_set_timeout(i, 0);
-	}
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	/* Initialize the I2C Slave */
-	init_i2cs(I2C_PORT_EC);
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-	/*
-	 * Set the secondary I2C slave address for the board.
-	 */
-	/* Index the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(i2c_bus_ports[I2C_PORT_EC]->slave_addr &
-		 ~(MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX |
-		   MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS)) |
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS);
-	/* Set the secondary slave address. */
-	i2c_bus_ports[I2C_PORT_EC]->slave_addr =
-		(1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS) |
-		CONFIG_BOARD_I2C_ADDR_FLAGS;
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-}
-
-/**
- *  I2C Peripheral Implementation
- */
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* IRQ for each I2C */
-static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
-
-/**
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t *const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static struct host_packet i2c_packet;
-
-static i2c_req_t req_slave;
-volatile int ec_pending_response = 0;
-
-/**
- * i2c_send_response_packet() - Send the response packet to get processed.
- * @pkt: Packet to send.
- */
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress. */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* Host_buffer data range. */
-	req_slave.tx_remain = size + 2;
-	req_slave.response_pending = true;
-
-	/* Call the handler to send the response packet. */
-	i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]);
-}
-
-/**
- * i2c_process_command() - Process the command in the i2c host buffer.
- */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	i2c_packet.send_response = i2c_send_response_packet;
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer. */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-
-	host_packet_receive(&i2c_packet);
-}
-
-/**
- * i2c_slave_service() - Called by the I2C slave interrupt controller.
- * @req:   Request currently being processed.
- */
-void i2c_slave_service(i2c_req_t *req)
-{
-	/* Check if there was a host command (I2C master write). */
-	if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		req->state = I2C_SLAVE_WRITE_COMPLETE;
-		/* A response to this write is pending. */
-		/* Assume that there is nothing to send back to the HOST. */
-		req->tx_remain = -1;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-		if (req->addr_match_flag != 0x1) {
-			i2c_process_board_command(
-				0, CONFIG_BOARD_I2C_ADDR_FLAGS,
-				req->received_count);
-		} else
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-		{
-			i2c_process_command();
-		}
-	}
-}
-
-/**
- * I2C0_IRQHandler() - Async Handler for I2C Slave driver.
- */
-void I2C0_IRQHandler(void)
-{
-	i2c_slave_handler(i2c_bus_ports[0]);
-}
-
-/**
- * I2C1_IRQHandler() - Async Handler for I2C Slave driver.
- */
-void I2C1_IRQHandler(void)
-{
-	i2c_slave_handler(i2c_bus_ports[1]);
-}
-
-DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1);
-DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1);
-
-/**
- * i2c_slave_service_read() - Services the Master I2C read from the slave.
- * @i2c: I2C peripheral pointer.
- * @req: Pointer to the request info.
- */
-static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/*
-	 * Clear the RX Threshold interrupt if set. Make sure and preserve
-	 * a possible done bit, address match, or multiple slave address
-	 * flags.
-	 */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
-	i2c->int_fl1 = i2c->int_fl1;
-	/*
-	 * If there is nothing to transmit to the EC HOST, then default
-	 * to clock stretching.
-	 */
-	if (req->tx_remain < 0) {
-		return;
-	}
-	/* If there is data to send to the Master then fill the TX FIFO. */
-	if (req->tx_remain != 0) {
-		/* There is no longer a response pending from the slave to the master. */
-		req->response_pending = false;
-		/* Fill the FIFO with data to transimit to the I2C Master. */
-		while ((req->tx_remain > 0) &&
-			!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = *(req->tx_data)++;
-			req->tx_remain--;
-		}
-	}
-	/*
-	 * If we have sent everything to the Master that we can,
-	 * then send padding byte.
-	 */
-	if (req->tx_remain == 0) {
-		/* Tx response is fulfilled. */
-		/* Fill the FIFO with the EC padding byte. */
-		while (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = EC_PADDING_BYTE;
-		}
-	}
-	/* Set the threshold for TX, the threshold is a four bit field. */
-	i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-			(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
-	/* Enable interrupts of interest. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-}
-
-/**
- * i2c_slave_service_write() - Services the Master I2C write to the slave.
- * @i2c: I2C peripheral pointer.
- * @req: Pointer to the request info.
- */
-static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/* Clear all flags except address matching and done. */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
-	i2c->int_fl1 = i2c->int_fl1;
-	/* Read out any data in the RX FIFO. */
-	while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-		*(req->rx_data)++ = i2c->fifo;
-		req->received_count++;
-	}
-	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 1)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-	/* Enable interrupts of interest. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-}
-
-/**
- * i2c_slave_handler() - I2C interrupt handler.
- * @i2c: Base address of the I2C module.
- *
- * This function should be called by the application from the interrupt
- * handler if I2C interrupts are enabled. Alternately, this function
- * can be periodically called by the application if I2C interrupts are
- * disabled.
- */
-static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
-{
-	i2c_req_t *req;
-
-	/* Get the request context for this interrupt. */
-	req = states[MXC_I2C_GET_IDX(i2c)].req;
-
-
-	/* Check for an address match flag. */
-	if ((req->expecting_start) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
-		req->expecting_done = true;
-		req->expecting_start = false;
-		/*
-		* Save the address match index to identify
-		* targeted slave address.
-		*/
-		req->addr_match_flag =
-			(i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >>
-			MXC_F_I2C_INT_FL0_MAMI_POS;
-
-		/* Clear all interrupt flags except a done interrupt. */
-		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_DONE);
-		i2c->int_fl1 = i2c->int_fl1;
-
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-
-		/* Check if Master is writing to the slave. */
-		if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
-			/* I2C Master is writing to the slave. */
-			req->rx_data = host_buffer;
-			req->tx_data = host_buffer;
-			req->tx_remain = -1; /* Nothing to send yet. */
-			/* Clear the RX (receive from I2C Master) byte counter. */
-			req->received_count = 0;
-			req->state = I2C_SLAVE_ADDR_MATCH_WRITE;
-			/* The Master is writing, there can not be a response pending yet. */
-			req->response_pending = false;
-			/* Set the RX threshold interrupt level. */
-			i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-					~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-					(MXC_I2C_FIFO_DEPTH - 2)
-						<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-		} else {
-			/* The Master is reading from the slave. */
-			/* Start transmitting to the Master from the start of buffer. */
-			req->tx_data = host_buffer;
-			req->state = I2C_SLAVE_ADDR_MATCH_READ;
-			/* Set the threshold for TX, the threshold is a four bit field. */
-			i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-				(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-			/*
-			* If this is a board address match and there is not
-			* already a pending response to the I2C Master then
-			* fulfill this board read request.
-			*/
-			if ((req->response_pending == 0) &&
-				(req->addr_match_flag != 0x1)) {
-				i2c_process_board_command(
-					1, CONFIG_BOARD_I2C_ADDR_FLAGS, 0);
-			}
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-		}
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-		/* Inhibit sleep mode when addressed until STOPF flag is set. */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Check for DONE interrupt. */
-	if ((req->expecting_done) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-		req->expecting_start = true;
-		req->expecting_done = false;
-		/* Clear all interrupts except a possible address match. */
-		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-			MXC_F_I2C_INT_FL0_MAMI_MASK);
-		i2c->int_fl1 = i2c->int_fl1;
-
-		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
-		i2c->int_en1 = 0;
-		/* If this was a DONE after a write then read the fifo until empty. */
-		if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-			/* Read out any data in the RX FIFO. */
-			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-				*(req->rx_data)++ = i2c->fifo;
-				req->received_count++;
-			}
-		}
-		/* Manually clear the RX FIFO. */
-		i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
-		/* Manually clear the TX FIFO. */
-		i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
-
-		/* Process the Master write that just finished. */
-		i2c_slave_service(req);
-
-		/* No longer inhibit deep sleep after done. */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Check for an I2C Master Read or Write. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		/* Clear the error interrupt. */
-		i2c->int_fl0 = I2C_ERROR;
-		i2c->int_en0 = 0;
-		/* Manually clear the TXFIFO. */
-		i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
-		/* Disable and clear interrupts. */
-		i2c->int_en0 = 0;
-		i2c->int_en1 = 0;
-		i2c->int_fl0 = i2c->int_fl0;
-		i2c->int_fl1 = i2c->int_fl1;
-		/* Cycle the I2C peripheral enable on error. */
-		i2c->ctrl = 0;
-		i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_READ) {
-		/* Service a read request from the I2C Master. */
-		i2c_slave_service_read(i2c, req);
-	} else if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) {
-		/* Service a write request from the I2C Master. */
-		i2c_slave_service_write(i2c, req);
-	}
-
-}
-
-/**
- * init_i2cs() - Async Handler for I2C Slave driver.
- * @port: I2C port number to initialize.
- */
-void init_i2cs(int port)
-{
-	int error;
-
-	error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE);
-	if (error != EC_SUCCESS) {
-		while (1)
-			;
-	}
-	/* Prepare for interrupt driven slave requests. */
-	req_slave.addr = CONFIG_HOSTCMD_I2C_ADDR_FLAGS;
-	req_slave.tx_data = host_buffer; /* Transmitted to host. */
-	req_slave.tx_remain = -1;
-	req_slave.rx_data = host_buffer; /* Received from host. */
-	req_slave.restart = 0;
-	req_slave.response_pending = false;
-	states[port].req = &req_slave;
-	error = i2c_slave_async(i2c_bus_ports[port], &req_slave);
-	if (error != EC_SUCCESS) {
-		while (1)
-			;
-	}
-	states[port].req->expecting_done = false;
-	states[port].req->expecting_start = true;
-	task_enable_irq(i2c_bus_irqs[port]);
-}
-
-/**
- * i2c_slave_async() - Slave Read and Write Asynchronous.
- * @i2c:   Pointer to I2C regs.
- * @req:   Request for an I2C transaction.
- *
- * Return EC_SUCCESS if successful, otherwise returns a common error code.
- */
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN))
-		return EC_ERROR_UNKNOWN;
-	/* Disable master mode. */
-	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
-	/* Set the Slave Address in the I2C peripheral register. */
-	i2c->slave_addr = req->addr;
-	/* Clear the receive count from the I2C Master. */
-	req->received_count = 0;
-	/* Disable and clear the interrupts. */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-
-	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 2)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
-
-	/* Only enable the I2C Address match interrupt. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-
-static void i2c_send_board_response(int len)
-{
-	/* Set the number of bytes to send to the I2C master. */
-	req_slave.tx_remain = len;
-	/* Indicate that there is a response pending from the slave. */
-	req_slave.response_pending = true;
-}
-
-
-static void i2c_process_board_command(int read, int addr, int len)
-{
-	board_i2c_process(read, addr, len, &host_buffer[0],
-			  i2c_send_board_response);
-}
-#endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
-#endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
-/**
- * i2c_set_speed() - Set the transfer speed of the selected I2C.
- * @i2c: Pointer to I2C peripheral.
- * @i2cspeed: Speed to set.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	uint32_t ticks;
-	uint32_t ticks_lo;
-	uint32_t ticks_hi;
-	uint32_t time_pclk;
-	uint32_t target_bus_freq;
-	uint32_t time_scl_min;
-	uint32_t clock_low_min;
-	uint32_t clock_high_min;
-	uint32_t clock_min;
-
-	if (i2cspeed == I2C_HS_MODE) {
-		/* Compute dividers for high speed mode. */
-		time_pclk = 1000000 / (PeripheralClock / 1000);
-
-		target_bus_freq = i2cspeed;
-		if (target_bus_freq < 1000) {
-			return EC_ERROR_INVAL;
-		}
-
-		time_scl_min = 1000000 / (target_bus_freq / 1000);
-		clock_low_min =
-			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
-			 time_pclk) - 1;
-		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
-				  T_AF_MIN) /
-				  time_pclk) - 1;
-		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
-
-		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
-				   ? (clock_low_min)
-				   : (clock_min - clock_high_min);
-		ticks_hi = clock_high_min;
-
-		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
-		    (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
-			return EC_ERROR_INVAL;
-		}
-
-		/* Write results to destination registers. */
-		i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) |
-			      (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
-
-		/* Still need to load dividers for the preamble that each
-		 * high-speed transaction starts with. Switch setting to fast
-		 * mode and fall out of if statement.
-		 */
-		i2cspeed = I2C_FAST_MODE;
-	}
-
-	/* Get the number of periph clocks needed to achieve selected speed. */
-	ticks = PeripheralClock / i2cspeed;
-
-	/* For a 50% duty cycle, half the ticks will be spent high and half will
-	 * be low.
-	 */
-	ticks_hi = (ticks >> 1) - 1;
-	ticks_lo = (ticks >> 1) - 1;
-
-	/* Account for rounding error in odd tick counts. */
-	if (ticks & 1) {
-		ticks_hi++;
-	}
-
-	/* Will results fit into 9 bit registers?  (ticks_hi will always be >=
-	 * ticks_lo.  No need to check ticks_lo.)
-	 */
-	if (ticks_hi > 0x1FF) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* 0 is an invalid value for the destination registers. (ticks_hi will
-	 * always be >= ticks_lo.  No need to check ticks_hi.)
-	 */
-	if (ticks_lo == 0) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Write results to destination registers. */
-	i2c->clk_lo = ticks_lo;
-	i2c->clk_hi = ticks_hi;
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_init_peripheral() - Initialize and enable I2C.
- * @i2c:      Pointer to I2C peripheral registers.
- * @i2cspeed: Desired speed (I2C mode).
- * @sys_cfg:  System configuration object.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	/**
-	 * Always disable the HW autoflush on data NACK and let the SW handle
-	 * the flushing.
-	 */
-	i2c->tx_ctrl0 |= 0x20;
-
-	i2c->ctrl = 0; /* Clear configuration bits. */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
-	i2c->status = 0; /* Clear status bits. */
-
-	i2c->ctrl = 0; /* Clear configuration bits. */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */
-	i2c->master_ctrl = 0; /* Clear master configuration bits. */
-	i2c->status = 0; /* Clear status bits. */
-
-	/* Check for HS mode. */
-	if (i2cspeed == I2C_HS_MODE) {
-		i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode. */
-	}
-
-	/* Disable and clear interrupts. */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-
-	i2c->timeout = 0x0; /* Set timeout. */
-	i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* Clear the RX FIFO. */
-	i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* Clear the TX FIFO. */
-
-	return i2c_set_speed(i2c, i2cspeed);
-}
-
-/**
- * i2c_master_write()
- * @i2c:  Pointer to I2C regs.
- * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
- *        Only supports 7-bit addressing. LSb of the given address
- *        will be used as the read/write bit, the \p addr <b>will
- *        not be shifted. Used for both master and
- *        slave transactions.
- * @data: Data to be written.
- * @len:  Number of bytes to Write.
- * @restart: 0 to send a stop bit at the end of the transaction,
- *	     otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return  EC_SUCCESS, or non-zero if error.
- */
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len, int restart)
-{
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	/* Clear the interrupt flag. */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode. */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	/* Load FIFO with slave address for WRITE and as much data as we can. */
-	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-	}
-
-	if (start) {
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the write bit.
-		 */
-		i2c->fifo = (addr << 1) & ~(0x1);
-	}
-
-	while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-		i2c->fifo = *data++;
-		len--;
-	}
-	/* Generate Start signal. */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-	}
-
-	/* Write remaining data to FIFO. */
-	while (len > 0) {
-		/* Check for errors. */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = *data++;
-			len--;
-		}
-	}
-	/* Check if Repeated Start requested. */
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	if (stop) {
-		/* Wait for Done. */
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop if requested and there is no restart. */
-	if (stop && !restart) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear stop interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-	}
-
-	/* Check for errors. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_master_read()
- * @i2c:        Pointer to I2C regs.
- * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
- * @data:       Data to be written.
- * @len:        Number of bytes to Write.
- * @restart:    0 to send a stop bit at the end of the transaction,
- * 	       otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return:     EC_SUCCESS if successful, otherwise returns a common error code
- */
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart)
-{
-	volatile int length = len;
-	int interactive_receive_mode;
-
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	if (len > 255) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Clear the interrupt flag. */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode. */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	if (stop) {
-		/* Set receive count. */
-		i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = len;
-		interactive_receive_mode = 0;
-	} else {
-		i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = 1;
-		interactive_receive_mode = 1;
-	}
-
-	/* Load FIFO with slave address. */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-		}
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the read bit.
-		 */
-		i2c->fifo = ((addr << 1) | 1);
-	}
-
-	/* Wait for all data to be received or error. */
-	while (length > 0) {
-		/* Check for errors */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit. */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* If in interactive receive mode then ack each received byte. */
-		if (interactive_receive_mode) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
-				;
-			if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) {
-				/* Read the data. */
-				*data++ = i2c->fifo;
-				length--;
-				/* Clear the bit. */
-				if (length != 1) {
-					i2c->int_fl0 =
-						MXC_F_I2C_INT_EN0_RX_MODE;
-				}
-			}
-		} else {
-			if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-				*data++ = i2c->fifo;
-				length--;
-			}
-		}
-	}
-
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	/* Wait for Done. */
-	if (stop) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors. */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit. */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag. */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop. */
-	if (!restart) {
-		if (stop) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-				/* Check for errors. */
-				if (i2c->int_fl0 & I2C_ERROR) {
-					/* Set the stop bit. */
-					i2c->master_ctrl &= ~(
-						MXC_F_I2C_MASTER_CTRL_RESTART);
-					i2c->master_ctrl |=
-						MXC_F_I2C_MASTER_CTRL_STOP;
-					return EC_ERROR_UNKNOWN;
-				}
-			}
-			/* Clear Stop interrupt flag. */
-			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-		}
-	}
-
-	/* Check for errors. */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h
deleted file mode 100644
index 8cd2fd8868..0000000000
--- a/chip/max32660/i2c_regs.h
+++ /dev/null
@@ -1,1627 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the I2C Peripheral */
-
-#ifndef _I2C_REGS_H_
-#define _I2C_REGS_H_
-
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
- */
-
-/**
- * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
-	__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
-	__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
-	__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
-	__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
-	__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
-	__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
-	__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
-	__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
-	__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
-	__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
-	__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
-	__IO uint32_t
-		master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
-	__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
-	__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
-	__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
-	__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
-	__IO uint32_t
-		slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
-	__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
-} mxc_i2c_regs_t;
-
-/* Register offsets for module I2C */
-/**
- * I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
- */
-#define MXC_R_I2C_CTRL \
-	((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0000</tt> */
-#define MXC_R_I2C_STATUS \
-	((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0004</tt> */
-#define MXC_R_I2C_INT_FL0 \
-	((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0008</tt> */
-#define MXC_R_I2C_INT_EN0 \
-	((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x000C</tt> */
-#define MXC_R_I2C_INT_FL1 \
-	((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0010</tt> */
-#define MXC_R_I2C_INT_EN1 \
-	((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0014</tt> */
-#define MXC_R_I2C_FIFO_LEN \
-	((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0018</tt> */
-#define MXC_R_I2C_RX_CTRL0 \
-	((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x001C</tt> */
-#define MXC_R_I2C_RX_CTRL1 \
-	((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0020</tt> */
-#define MXC_R_I2C_TX_CTRL0 \
-	((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0024</tt> */
-#define MXC_R_I2C_TX_CTRL1 \
-	((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0028</tt> */
-#define MXC_R_I2C_FIFO \
-	((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x002C</tt> */
-#define MXC_R_I2C_MASTER_CTRL \
-	((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0030</tt> */
-#define MXC_R_I2C_CLK_LO \
-	((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0034</tt> */
-#define MXC_R_I2C_CLK_HI \
-	((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0038</tt> */
-#define MXC_R_I2C_HS_CLK \
-	((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt>       \
-				    0x003C</tt> */
-#define MXC_R_I2C_TIMEOUT \
-	((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0040</tt> */
-#define MXC_R_I2C_SLAVE_ADDR \
-	((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0044</tt> */
-#define MXC_R_I2C_DMA \
-	((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt>       \
-				    0x0048</tt> */
-
-/**
- * Control Register0.
- */
-#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
-#define MXC_F_I2C_CTRL_I2C_EN \
-	((uint32_t)(0x1UL     \
-		    << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
-#define MXC_V_I2C_CTRL_I2C_EN_DIS \
-	((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
-#define MXC_S_I2C_CTRL_I2C_EN_DIS  \
-	(MXC_V_I2C_CTRL_I2C_EN_DIS \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
-#define MXC_V_I2C_CTRL_I2C_EN_EN \
-	((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value                            \
-			   */
-#define MXC_S_I2C_CTRL_I2C_EN_EN  \
-	(MXC_V_I2C_CTRL_I2C_EN_EN \
-	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
-
-#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
-#define MXC_F_I2C_CTRL_MST \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
-#define MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
-#define MXC_S_I2C_CTRL_MST_SLAVE_MODE  \
-	(MXC_V_I2C_CTRL_MST_SLAVE_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
-#define MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
-#define MXC_S_I2C_CTRL_MST_MASTER_MODE  \
-	(MXC_V_I2C_CTRL_MST_MASTER_MODE \
-	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
-
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
-#define MXC_F_I2C_CTRL_GEN_CALL_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR  \
-							 Mask */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS      \
-						 Setting */
-#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
-#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN  \
-	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
-	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN       \
-						 Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
-#define MXC_F_I2C_CTRL_RX_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_RX_MODE_DIS  \
-	(MXC_V_I2C_CTRL_RX_MODE_DIS \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
-#define MXC_S_I2C_CTRL_RX_MODE_EN  \
-	(MXC_V_I2C_CTRL_RX_MODE_EN \
-	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
-#define MXC_F_I2C_CTRL_RX_MODE_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK  \
-							   Mask */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting  \
-					     */
-#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
-#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK  \
-	(MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
-	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting \
-					     */
-
-#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
-#define MXC_F_I2C_CTRL_SCL_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
-#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW  \
-	(MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
-#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL  \
-	(MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
-	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
-#define MXC_F_I2C_CTRL_SDA_OUT \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
-#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW  \
-	(MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW        \
-					   Setting */
-#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
-#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA  \
-	(MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
-	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting  \
-					 */
-
-#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
-#define MXC_F_I2C_CTRL_SCL \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
-
-#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
-#define MXC_F_I2C_CTRL_SDA \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
-
-#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
-#define MXC_F_I2C_CTRL_SW_OUT_EN \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
-#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
-	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
-					     Setting */
-#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
-#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE  \
-	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
-	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE   \
-					     Setting */
-
-#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
-#define MXC_F_I2C_CTRL_READ \
-	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
-#define MXC_V_I2C_CTRL_READ_WRITE \
-	((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
-#define MXC_S_I2C_CTRL_READ_WRITE  \
-	(MXC_V_I2C_CTRL_READ_WRITE \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
-#define MXC_V_I2C_CTRL_READ_READ \
-	((uint32_t)0x1UL) /**< CTRL_READ_READ Value                            \
-			   */
-#define MXC_S_I2C_CTRL_READ_READ  \
-	(MXC_V_I2C_CTRL_READ_READ \
-	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
-
-#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS \
-	12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
-#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS \
-	((uint32_t)(                      \
-		0x1UL                     \
-		<< MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**<                       \
-							      CTRL_SCL_CLK_STRECH_DIS \
-							      Mask */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
-#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN  \
-	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                          \
-						      CTRL_SCL_CLK_STRECH_DIS_EN \
-						      Setting */
-#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
-#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS  \
-	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
-	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                           \
-						      CTRL_SCL_CLK_STRECH_DIS_DIS \
-						      Setting */
-
-#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
-#define MXC_F_I2C_CTRL_SCL_PP_MODE \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE  \
-							   Mask */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting  \
-					     */
-#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
-#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN  \
-	(MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
-	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting   \
-					     */
-
-#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
-#define MXC_F_I2C_CTRL_HS_MODE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
-#define MXC_V_I2C_CTRL_HS_MODE_DIS \
-	((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
-#define MXC_S_I2C_CTRL_HS_MODE_DIS  \
-	(MXC_V_I2C_CTRL_HS_MODE_DIS \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
-#define MXC_V_I2C_CTRL_HS_MODE_EN \
-	((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
-#define MXC_S_I2C_CTRL_HS_MODE_EN  \
-	(MXC_V_I2C_CTRL_HS_MODE_EN \
-	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
-
-/**
- * I2C_STATUS I2C_STATUS
- */
-#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
-#define MXC_F_I2C_STATUS_BUS \
-	((uint32_t)(0x1UL    \
-		    << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask   \
-							 */
-#define MXC_V_I2C_STATUS_BUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
-#define MXC_S_I2C_STATUS_BUS_IDLE  \
-	(MXC_V_I2C_STATUS_BUS_IDLE \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_BUS_BUSY \
-	((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
-#define MXC_S_I2C_STATUS_BUS_BUSY  \
-	(MXC_V_I2C_STATUS_BUS_BUSY \
-	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
-
-#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_I2C_STATUS_RX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
-#define MXC_F_I2C_STATUS_RX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
-#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting \
-					   */
-#define MXC_V_I2C_STATUS_RX_FULL_FULL \
-	((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
-#define MXC_S_I2C_STATUS_RX_FULL_FULL  \
-	(MXC_V_I2C_STATUS_RX_FULL_FULL \
-	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
-
-#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_I2C_STATUS_TX_EMPTY \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY  \
-							    Mask */
-#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY      \
-					      Setting */
-#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting  \
-					    */
-
-#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
-#define MXC_F_I2C_STATUS_TX_FULL \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
-#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY        \
-					     Setting */
-#define MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
-#define MXC_S_I2C_STATUS_TX_FULL_EMPTY  \
-	(MXC_V_I2C_STATUS_TX_FULL_EMPTY \
-	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
-
-#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
-#define MXC_F_I2C_STATUS_CLK_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE  \
-							    Mask */
-#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
-			     Value */
-#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
-	(MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                              \
-					      STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK      \
-			     Value */
-#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK  \
-	(MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                          \
-					      STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
-					      Setting */
-
-#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
-#define MXC_F_I2C_STATUS_STATUS \
-	((uint32_t)(            \
-		0xFUL           \
-		<< MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
-#define MXC_V_I2C_STATUS_STATUS_IDLE \
-	((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
-#define MXC_S_I2C_STATUS_STATUS_IDLE  \
-	(MXC_V_I2C_STATUS_STATUS_IDLE \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting   \
-					  */
-#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK       \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
-#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR  \
-	(MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR        \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK    \
-					    Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX \
-	((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
-#define MXC_S_I2C_STATUS_STATUS_TX  \
-	(MXC_V_I2C_STATUS_STATUS_TX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_RX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_RX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_RX \
-	((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
-#define MXC_S_I2C_STATUS_STATUS_RX  \
-	(MXC_V_I2C_STATUS_STATUS_RX \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
-#define MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
-#define MXC_S_I2C_STATUS_STATUS_TX_ACK  \
-	(MXC_V_I2C_STATUS_STATUS_TX_ACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_NACK \
-	((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
-#define MXC_S_I2C_STATUS_STATUS_NACK  \
-	(MXC_V_I2C_STATUS_STATUS_NACK \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
-#define MXC_V_I2C_STATUS_STATUS_BY_ST \
-	((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
-#define MXC_S_I2C_STATUS_STATUS_BY_ST  \
-	(MXC_V_I2C_STATUS_STATUS_BY_ST \
-	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
-
-/**
- * Interrupt Status Register.
- */
-#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
-#define MXC_F_I2C_INT_FL0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
-#define MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DONE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DONE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_DONE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DONE_PENDING  \
-	(MXC_V_I2C_INT_FL0_DONE_PENDING \
-	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
-#define MXC_F_I2C_INT_FL0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS \
-	2 /**< INT_FL0_GEN_CALL_ADDR Position */
-#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**<                     \
-							    INT_FL0_GEN_CALL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                              \
-						    INT_FL0_GEN_CALL_ADDR_INACTIVE \
-						    Setting */
-#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
-#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING  \
-	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
-	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                             \
-						    INT_FL0_GEN_CALL_ADDR_PENDING \
-						    Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_FL0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE \
-						 Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING  \
-						 Setting */
-
-#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
-#define MXC_F_I2C_INT_FL0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE   \
-						Setting */
-#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING  \
-	(MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
-	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING    \
-						Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
-#define MXC_F_I2C_INT_FL0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
-#define MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
-#define MXC_V_I2C_INT_FL0_STOP_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_FL0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
-#define MXC_F_I2C_INT_FL0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
-#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting \
-					   */
-#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting  \
-					   */
-
-#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
-#define MXC_F_I2C_INT_FL0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
-#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting   \
-					  */
-#define MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_TO_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_TO_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
-
-#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS \
-	10 /**< INT_FL0_ADDR_NACK_ER Position */
-#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**<                    \
-							   INT_FL0_ADDR_NACK_ER \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                             \
-						   INT_FL0_ADDR_NACK_ER_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                            \
-						   INT_FL0_ADDR_NACK_ER_PENDING \
-						   Setting */
-
-#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
-#define MXC_F_I2C_INT_FL0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_FL0_DO_NOT_RESP_ER Position */
-#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_FL0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                               \
-						     INT_FL0_DO_NOT_RESP_ER_INACTIVE \
-						     Setting */
-#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                              \
-						     INT_FL0_DO_NOT_RESP_ER_PENDING \
-						     Setting */
-
-#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
-#define MXC_F_I2C_INT_FL0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE     \
-					       Setting */
-#define MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_START_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_START_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING      \
-					       Setting */
-
-#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
-#define MXC_F_I2C_INT_FL0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE       \
-					      Setting */
-#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
-#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING  \
-	(MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
-	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING        \
-					      Setting */
-
-#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS \
-	15 /**< INT_FL0_TX_LOCK_OUT Position */
-#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_FL0_TX_LOCK_OUT  \
-							  Mask */
-
-#define MXC_F_I2C_INT_FL0_MAMI_POS 16 /**< INT_FL0_MAMI Position */
-/* INT_FL0_MAMI Mask */
-#define MXC_F_I2C_INT_FL0_MAMI_MASK \
-	((uint32_t)(0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 0 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 \
-	((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 1 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 \
-	((uint32_t)(0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 2 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 \
-	((uint32_t)(0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS))
-/* INT_FL0_MAMI Address Match 3 */
-#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 \
-	((uint32_t)(0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)) 
-
-/**
- * Interrupt Enable Register.
- */
-#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
-#define MXC_F_I2C_INT_EN0_DONE \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
-#define MXC_V_I2C_INT_EN0_DONE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
-#define MXC_S_I2C_INT_EN0_DONE_DIS  \
-	(MXC_V_I2C_INT_EN0_DONE_DIS \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DONE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
-#define MXC_S_I2C_INT_EN0_DONE_EN  \
-	(MXC_V_I2C_INT_EN0_DONE_EN \
-	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
-#define MXC_F_I2C_INT_EN0_RX_MODE \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
-#define MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_MODE_EN  \
-	(MXC_V_I2C_INT_EN0_RX_MODE_EN \
-	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS \
-	2 /**< INT_EN0_GEN_CTRL_ADDR Position */
-#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR \
-	((uint32_t)(                    \
-		0x1UL                   \
-		<< MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**<                     \
-							    INT_EN0_GEN_CTRL_ADDR \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
-#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS  \
-	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**<                          \
-						    INT_EN0_GEN_CTRL_ADDR_DIS  \
-						    Setting */
-#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
-#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN  \
-	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
-	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN \
-						    Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
-#define MXC_F_I2C_INT_EN0_ADDR_MATCH \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH  \
-							 Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS      \
-						 Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN       \
-						 Setting */
-
-#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_RX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_RX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_RX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
-#define MXC_F_I2C_INT_EN0_TX_THRESH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH    \
-							Mask */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS        \
-						Setting */
-#define MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_THRESH_EN  \
-	(MXC_V_I2C_INT_EN0_TX_THRESH_EN \
-	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting \
-					      */
-
-#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
-#define MXC_F_I2C_INT_EN0_STOP \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
-#define MXC_V_I2C_INT_EN0_STOP_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ACK \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
-#define MXC_F_I2C_INT_EN0_ARB_ER \
-	((uint32_t)(             \
-		0x1UL            \
-		<< MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
-#define MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ARB_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ARB_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
-#define MXC_F_I2C_INT_EN0_TO_ER \
-	((uint32_t)(            \
-		0x1UL           \
-		<< MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
-#define MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_TO_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_TO_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_TO_ER_EN  \
-	(MXC_V_I2C_INT_EN0_TO_ER_EN \
-	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
-#define MXC_F_I2C_INT_EN0_ADDR_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_ADDR_ER_EN  \
-	(MXC_V_I2C_INT_EN0_ADDR_ER_EN \
-	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
-#define MXC_F_I2C_INT_EN0_DATA_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_DATA_ER_EN  \
-	(MXC_V_I2C_INT_EN0_DATA_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS \
-	12 /**< INT_EN0_DO_NOT_RESP_ER Position */
-#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**<                      \
-							     INT_EN0_DO_NOT_RESP_ER \
-							     Mask */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                          \
-						     INT_EN0_DO_NOT_RESP_ER_DIS \
-						     Setting */
-#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN  \
-	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                         \
-						     INT_EN0_DO_NOT_RESP_ER_EN \
-						     Setting */
-
-#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
-#define MXC_F_I2C_INT_EN0_START_ER \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER  \
-							   Mask */
-#define MXC_V_I2C_INT_EN0_START_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_START_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_START_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting  \
-					     */
-#define MXC_V_I2C_INT_EN0_START_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_START_ER_EN  \
-	(MXC_V_I2C_INT_EN0_START_ER_EN \
-	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting   \
-					     */
-
-#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
-#define MXC_F_I2C_INT_EN0_STOP_ER \
-	((uint32_t)(0x1UL         \
-		    << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER  \
-							    Mask */
-#define MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_DIS  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_DIS \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
-#define MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
-#define MXC_S_I2C_INT_EN0_STOP_ER_EN  \
-	(MXC_V_I2C_INT_EN0_STOP_ER_EN \
-	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
-
-#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS \
-	15 /**< INT_EN0_TX_LOCK_OUT Position */
-#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**<                    \
-							  INT_EN0_TX_LOCK_OUT  \
-							  Mask */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
-#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN  \
-	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
-	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN     \
-						  Setting */
-
-/**
- * Interrupt Status Register 1.
- */
-#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS \
-	0 /**< INT_FL1_RX_OVERFLOW Position                                    \
-	   */
-#define MXC_F_I2C_INT_FL1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_FL1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
-#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE  \
-	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_INACTIVE \
-						  Setting */
-#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
-#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING  \
-	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
-						  INT_FL1_RX_OVERFLOW_PENDING  \
-						  Setting */
-
-#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS \
-	1 /**< INT_FL1_TX_UNDERFLOW Position */
-#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_FL1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
-#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE  \
-	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                             \
-						   INT_FL1_TX_UNDERFLOW_INACTIVE \
-						   Setting */
-#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
-#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING  \
-	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
-	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                            \
-						   INT_FL1_TX_UNDERFLOW_PENDING \
-						   Setting */
-
-/**
- * Interrupt Staus Register 1.
- */
-#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS \
-	0 /**< INT_EN1_RX_OVERFLOW Position                                    \
-	   */
-#define MXC_F_I2C_INT_EN1_RX_OVERFLOW \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**<                    \
-							  INT_EN1_RX_OVERFLOW  \
-							  Mask */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS    \
-						  Setting */
-#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
-#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN  \
-	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN     \
-						  Setting */
-
-#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS \
-	1 /**< INT_EN1_TX_UNDERFLOW Position */
-#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW \
-	((uint32_t)(                   \
-		0x1UL                  \
-		<< MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**<                    \
-							   INT_EN1_TX_UNDERFLOW \
-							   Mask */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
-#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS  \
-	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS  \
-						   Setting */
-#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
-#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN  \
-	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
-	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN   \
-						   Setting */
-
-/**
- * FIFO Configuration Register.
- */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_RX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN \
-							     Mask */
-
-#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
-#define MXC_F_I2C_FIFO_LEN_TX_LEN \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN \
-							     Mask */
-
-/**
- * Receive Control Register 0.
- */
-#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
-#define MXC_F_I2C_RX_CTRL0_DNR \
-	((uint32_t)(0x1UL      \
-		    << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
-#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
-#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND  \
-	(MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
-#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
-#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY  \
-	(MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**<                                      \
-					   RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
-					   Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
-#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
-	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**<                              \
-						RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH  \
-	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
-	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
-#define MXC_F_I2C_RX_CTRL0_RX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH  \
-							 Mask */
-
-/**
- * Receive Control Register 1.
- */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
-#define MXC_F_I2C_RX_CTRL1_RX_CNT \
-	((uint32_t)(0xFFUL        \
-		    << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT \
-							     Mask */
-
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
-#define MXC_F_I2C_RX_CTRL1_RX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO  \
-							   Mask */
-
-/**
- * Transmit Control Register 0.
- */
-#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS \
-	0 /**< TX_CTRL0_TX_PRELOAD Position                                    \
-	   */
-#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**<                    \
-							  TX_CTRL0_TX_PRELOAD  \
-							  Mask */
-
-#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS \
-	1 /**< TX_CTRL0_TX_READY_MODE Position */
-#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**<                      \
-							     TX_CTRL0_TX_READY_MODE \
-							     Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
-#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN  \
-	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                         \
-						     TX_CTRL0_TX_READY_MODE_EN \
-						     Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
-#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS  \
-	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
-	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                          \
-						     TX_CTRL0_TX_READY_MODE_DIS \
-						     Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_FLUSH \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH    \
-							Mask */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
-#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
-	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**<                              \
-						TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
-						Setting */
-#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
-#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH  \
-	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
-	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH      \
-						Setting */
-
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
-#define MXC_F_I2C_TX_CTRL0_TX_THRESH \
-	((uint32_t)(                 \
-		0xFUL                \
-		<< MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH  \
-							 Mask */
-
-/**
- * Transmit Control Register 1.
- */
-#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
-#define MXC_F_I2C_TX_CTRL1_TX_READY \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY    \
-							Mask */
-
-#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
-#define MXC_F_I2C_TX_CTRL1_TX_LAST \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST  \
-							   Mask */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
-#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW  \
-	(MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
-					       Setting */
-#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
-#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION  \
-	(MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
-	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**<                                \
-					       TX_CTRL1_TX_LAST_END_TRANSACTION \
-					       Setting */
-
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
-#define MXC_F_I2C_TX_CTRL1_TX_FIFO \
-	((uint32_t)(               \
-		0xFUL              \
-		<< MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO  \
-							   Mask */
-
-/**
- * Data Register.
- */
-#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
-#define MXC_F_I2C_FIFO_DATA \
-	((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
-
-/**
- * Master Control Register.
- */
-#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
-#define MXC_F_I2C_MASTER_CTRL_START \
-	((uint32_t)(                \
-		0x1UL               \
-		<< MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START    \
-							Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_RESTART_POS \
-	1 /**< MASTER_CTRL_RESTART Position                                    \
-	   */
-#define MXC_F_I2C_MASTER_CTRL_RESTART \
-	((uint32_t)(                  \
-		0x1UL                 \
-		<< MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**<                    \
-							  MASTER_CTRL_RESTART  \
-							  Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
-#define MXC_F_I2C_MASTER_CTRL_STOP \
-	((uint32_t)(               \
-		0x1UL              \
-		<< MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP  \
-							   Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS \
-	7 /**< MASTER_CTRL_SL_EX_ADDR Position */
-#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR \
-	((uint32_t)(                     \
-		0x1UL                    \
-		<< MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**<                      \
-							     MASTER_CTRL_SL_EX_ADDR \
-							     Mask */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                     \
-						     MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
-						     Setting */
-#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                      \
-						     MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
-						     Setting */
-
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS \
-	8 /**< MASTER_CTRL_MASTER_CODE Position */
-#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE \
-	((uint32_t)(                      \
-		0x7UL                     \
-		<< MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**<                       \
-							      MASTER_CTRL_MASTER_CODE \
-							      Mask */
-
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS \
-	11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
-#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP \
-	((uint32_t)(                       \
-		0x1UL                      \
-		<< MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**<                        \
-							       MASTER_CTRL_SCL_SPEED_UP \
-							       Mask */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                           \
-						       MASTER_CTRL_SCL_SPEED_UP_EN \
-						       Setting */
-#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
-#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS  \
-	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
-	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                            \
-						       MASTER_CTRL_SCL_SPEED_UP_DIS \
-						       Setting */
-
-/**
- * Clock Low Register.
- */
-#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
-#define MXC_F_I2C_CLK_LO_CLK_LO \
-	((uint32_t)(            \
-		0x1FFUL         \
-		<< MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
-
-/**
- * Clock high Register.
- */
-#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
-#define MXC_F_I2C_CLK_HI_CKH \
-	((uint32_t)(0x1FFUL  \
-		    << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
-
-/**
- * HS-Mode Clock Control Register
- */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_LO \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO  \
-							   Mask */
-
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
-#define MXC_F_I2C_HS_CLK_HS_CLK_HI \
-	((uint32_t)(               \
-		0xFFUL             \
-		<< MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI  \
-							   Mask */
-
-/**
- * Timeout Register
- */
-#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
-#define MXC_F_I2C_TIMEOUT_TO \
-	((uint32_t)(0xFFFFUL \
-		    << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
-
-/**
- * Slave Address Register.
- */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS \
-	0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \
-	((uint32_t)(                    \
-		0x3FFUL                 \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**<                     \
-							    SLAVE_ADDR_SLAVE_ADDR \
-							    Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS \
-	10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \
-	((uint32_t)(                        \
-		0x1UL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_DIS \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS \
-	11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
-#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \
-	((uint32_t)(                        \
-		0xFUL                       \
-		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**<                         \
-								SLAVE_ADDR_SLAVE_ADDR_IDX \
-								Mask */
-
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS \
-	15 /**< SLAVE_ADDR_EX_ADDR Position                                    \
-	    */
-#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR \
-	((uint32_t)(                 \
-		0x1UL                \
-		<< MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR  \
-							 Mask */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                 \
-						 SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
-						 Setting */
-#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
-#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS  \
-	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                  \
-						 SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
-						 Setting */
-
-/**
- * DMA Register.
- */
-#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
-#define MXC_F_I2C_DMA_TX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
-#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
-#define MXC_S_I2C_DMA_TX_EN_DIS  \
-	(MXC_V_I2C_DMA_TX_EN_DIS \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
-#define MXC_S_I2C_DMA_TX_EN_EN  \
-	(MXC_V_I2C_DMA_TX_EN_EN \
-	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
-
-#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
-#define MXC_F_I2C_DMA_RX_EN \
-	((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
-#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
-#define MXC_S_I2C_DMA_RX_EN_DIS  \
-	(MXC_V_I2C_DMA_RX_EN_DIS \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
-#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
-#define MXC_S_I2C_DMA_RX_EN_EN  \
-	(MXC_V_I2C_DMA_RX_EN_EN \
-	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
-
-#endif /* _I2C_REGS_H_ */
diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h
deleted file mode 100644
index 5f40e4203d..0000000000
--- a/chip/max32660/icc_regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the ICC */
-
-#ifndef _ICC_REGS_H_
-#define _ICC_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the ICC Registers.
- */
-typedef struct {
-	__I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */
-	__I uint32_t memcfg;   /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
-	__R uint32_t rsv_0x8_0xff[62];
-	__IO uint32_t
-		cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */
-	__R uint32_t rsv_0x104_0x6ff[383];
-	__IO uint32_t
-		invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */
-} mxc_icc_regs_t;
-
-/**
- * ICC Peripheral Register Offsets from the ICC Base Peripheral
- * Address.
- */
-#define MXC_R_ICC_CACHE_ID                                                     \
-	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_ICC_MEMCFG                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_ICC_CACHE_CTRL                                                   \
-	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x100 */
-#define MXC_R_ICC_INVALIDATE                                                   \
-	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>       \
-				    0x0x700 */
-
-/**
- * Cache ID Register.
- */
-#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
-#define MXC_F_ICC_CACHE_ID_RELNUM                                              \
-	((uint32_t)(                                                           \
-		0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
-							     Mask */
-
-#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
-#define MXC_F_ICC_CACHE_ID_PARTNUM                                             \
-	((uint32_t)(0xFUL                                                      \
-		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM  \
-							   Mask */
-
-#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
-#define MXC_F_ICC_CACHE_ID_CCHID                                               \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
-
-/**
- * Memory Configuration Register.
- */
-#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
-#define MXC_F_ICC_MEMCFG_CCHSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
-
-#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
-#define MXC_F_ICC_MEMCFG_MEMSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
-
-/**
- * Cache Control and Status Register.
- */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS                                      \
-	0 /**< CACHE_CTRL_CACHE_EN Position                                    \
-	   */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                          \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                    \
-							  CACHE_CTRL_CACHE_EN  \
-							  Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                     \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS    \
-						  Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                      \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN     \
-						  Setting */
-
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS                                     \
-	16 /**< CACHE_CTRL_CACHE_RDY Position */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
-							   CACHE_CTRL_CACHE_RDY \
-							   Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                \
-	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                  \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                 \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                             \
-						   CACHE_CTRL_CACHE_RDY_NOTREADY \
-						   Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                           \
-						   CACHE_CTRL_CACHE_RDY_READY  \
-						   Setting */
-
-#endif /* _ICC_REGS_H_ */
diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h
deleted file mode 100644
index f323b4568c..0000000000
--- a/chip/max32660/pwrseq_regs.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.

- * Use of this source code is governed by a BSD-style license that can be

- * found in the LICENSE file.

- */

-

-/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */

-

-#ifndef _PWRSEQ_REGS_H_

-#define _PWRSEQ_REGS_H_

-

-/* **** Includes **** */

-#include <stdint.h>

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-

-#if defined(__ICCARM__)

-#pragma system_include

-#endif

-

-#if defined(__CC_ARM)

-#pragma anon_unions

-#endif

-

-/*

-    If types are not defined elsewhere (CMSIS) define them here

-*/

-#ifndef __IO

-#define __IO volatile

-#endif

-#ifndef __I

-#define __I volatile const

-#endif

-#ifndef __O

-#define __O volatile

-#endif

-#ifndef __R

-#define __R volatile const

-#endif

-

-/* **** Definitions **** */

-

-/**

- * mxc_pwrseq_regs_t

- * Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral

- * Module.

- */

-

-/**

- * pwrseq_registers

- * Structure type to access the PWRSEQ Registers.

- */

-typedef struct {

-	__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */

-	__IO uint32_t

-		lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */

-	__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */

-	__R uint32_t rsv_0xc_0x3f[13];

-	__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */

-} mxc_pwrseq_regs_t;

-

-/**

- * Register offsets for module PWRSEQ

- * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base

- */

-#define MXC_R_PWRSEQ_LP_CTRL                                                   \

-	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0000</tt> */

-#define MXC_R_PWRSEQ_LP_WAKEFL                                                 \

-	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0004</tt> */

-#define MXC_R_PWRSEQ_LPWK_EN                                                   \

-	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0008</tt> */

-#define MXC_R_PWRSEQ_LPMEMSD                                                   \

-	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \  \

-				    \ \ \ 0x0040</tt> */

-

-/**

- * pwrseq_registers

- * Low Power Control Register.

- */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS                                   \

-	0 /**< LP_CTRL_RAMRET_SEL0 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL0 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS                                   \

-	1 /**< LP_CTRL_RAMRET_SEL1 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL1 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS                                   \

-	2 /**< LP_CTRL_RAMRET_SEL2 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL2 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS                                   \

-	3 /**< LP_CTRL_RAMRET_SEL3 Position */

-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                         \

-	((uint32_t)(                                                             \

-		0x1UL                                                            \

-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \                                                                               \

-							     LP_CTRL_RAMRET_SEL3 \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \

-	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \

-						     \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \

-	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN  \

-						     \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */

-#define MXC_F_PWRSEQ_LP_CTRL_OVR                                               \

-	((uint32_t)(0x3UL                                                      \

-		    << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                          \

-	((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                          \

-	((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                          \

-	((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */

-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                                          \

-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                         \

-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS                              \

-	6 /**< LP_CTRL_VCORE_DET_BYPASS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                              \

-	((uint32_t)(                                                                       \

-		0x1UL                                                                      \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \                                                                                         \

-								  LP_CTRL_VCORE_DET_BYPASS \

-								  \                        \

-								  \ \ \ \                                                                                         \

-								  Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                          \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \

-							  LP_CTRL_VCORE_DET_BYPASS_ENABLED \

-							  \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                          \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \

-							  LP_CTRL_VCORE_DET_BYPASS_DISABLE \

-							  \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS                                     \

-	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \

-	((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \

-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                    \

-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \

-						   \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \

-	((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \

-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \

-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \  \

-						   \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS                                    \

-	10 /**< LP_CTRL_FAST_WK_EN Position */

-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                        \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \                                                                             \

-							    LP_CTRL_FAST_WK_EN \

-							    \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \

-	((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \

-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                   \

-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \

-						    \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \

-	((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \

-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \

-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \  \

-						    \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */

-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                            \

-	((uint32_t)(                                                           \

-		0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \

-							      \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \

-	((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */

-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \

-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                        \

-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \

-	((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */

-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \

-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                       \

-	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \

-					      * \                              \

-					      * \ \                                                                             \

-					      * \ \ \                                                                             \

-					      */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS                                 \

-	12 /**< LP_CTRL_VCORE_POR_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VCORE_POR_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                 \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VCORE_POR_DIS_DIS \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VCORE_POR_DIS_EN \

-						       \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                                           \

-	((uint32_t)(0x1UL                                                      \

-		    << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \

-							     \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \

-	((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \

-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \

-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting  \

-					       * \                             \

-					       * \ \                                                                             \

-					       * \ \ \                                                                             \

-					       * \ \ \ \                                                                             \

-					       */

-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \

-	((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \

-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                      \

-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \

-					       * \                             \

-					       * \ \                                                                             \

-					       * \ \ \                                                                             \

-					       * \ \ \ \                                                                             \

-					       */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS                                 \

-	20 /**< LP_CTRL_VCORE_SVM_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VCORE_SVM_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \

-	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VCORE_SVM_DIS_EN \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                 \

-	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VCORE_SVM_DIS_DIS \

-						       \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS                                 \

-	25 /**< LP_CTRL_VDDIO_POR_DIS Position */

-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                           \

-	((uint32_t)(                                                                 \

-		0x1UL                                                                \

-		<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \                                                                                   \

-							       LP_CTRL_VDDIO_POR_DIS \

-							       \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \

-	((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                              \

-						       LP_CTRL_VDDIO_POR_DIS_EN \

-						       \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                 \

-	((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */

-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                   \

-	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                  \

-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                               \

-						       LP_CTRL_VDDIO_POR_DIS_DIS \

-						       \ \ \ \ Setting */

-

-/**

- * pwrseq_registers

- * Low Power Mode Wakeup Flags for GPIO0

- */

-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */

-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                                          \

-	((uint32_t)(                                                           \

-		0x3FFFUL                                                       \

-		<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \

-							  \ \ \ Mask */

-

-/**

- * pwrseq_registers

- * Low Power I/O Wakeup Enable Register 0. This register enables low

- * power wakeup functionality for GPIO0.

- */

-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */

-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                            \

-	((uint32_t)(0x3FFFUL                                                   \

-		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \

-							    \ \ \ Mask */

-

-/**

- * pwrseq_registers

- * Low Power Memory Shutdown Control.

- */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS                                     \

-	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM0_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS                                     \

-	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM1_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS                                     \

-	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM2_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS                                     \

-	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \                                                                             \

-	   */

-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                         \

-	((uint32_t)(                                                           \

-		0x1UL                                                          \

-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \

-							   \ \ \ \ Mask */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \

-	((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL  \

-						   \ \ \ \ Setting */

-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \

-	((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */

-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \

-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \

-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                                                                             \

-						   LPMEMSD_SRAM3_OFF_SHUTDOWN  \

-						   \ \ \ \ Setting */

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _PWRSEQ_REGS_H_ */

diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
deleted file mode 100644
index e444888fa0..0000000000
--- a/chip/max32660/registers.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Register map, needed for a common include file */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include <stdint.h>
-
-#define EC_PF_IRQn 0 /* 0x10  0x0040  16: Power Fail */
-#define EC_WDT0_IRQn 1 /* 0x11  0x0044  17: Watchdog 0 */
-#define EC_RSV00_IRQn 2 /* 0x12  0x0048  18: RSV00 */
-#define EC_RTC_IRQn 3 /* 0x13  0x004C  19: RTC */
-#define EC_RSV1_IRQn 4 /* 0x14  0x0050  20: RSV1 */
-#define EC_TMR0_IRQn 5 /* 0x15  0x0054  21: Timer 0 */
-#define EC_TMR1_IRQn 6 /* 0x16  0x0058  22: Timer 1 */
-#define EC_TMR2_IRQn 7 /* 0x17  0x005C  23: Timer 2 */
-#define EC_RSV02_IRQn 8 /* 0x18  0x0060  24: RSV02 */
-#define EC_RSV03_IRQn 9 /* 0x19  0x0064  25: RSV03 */
-#define EC_RSV04_IRQn 10 /* 0x1A  0x0068  26: RSV04 */
-#define EC_RSV05_IRQn 11 /* 0x1B  0x006C  27: RSV05 */
-#define EC_RSV06_IRQn 12 /* 0x1C  0x0070  28: RSV06 */
-#define EC_I2C0_IRQn 13 /* 0x1D  0x0074  29: I2C0 */
-#define EC_UART0_IRQn 14 /* 0x1E  0x0078  30: UART 0 */
-#define EC_UART1_IRQn 15 /* 0x1F  0x007C  31: UART 1 */
-#define EC_SPI17Y_IRQn 16 /* 0x20  0x0080  32: SPI17Y */
-#define EC_SPIMSS_IRQn 17 /* 0x21  0x0084  33: SPIMSS */
-#define EC_RSV07_IRQn 18 /* 0x22  0x0088  34: RSV07 */
-#define EC_RSV08_IRQn 19 /* 0x23  0x008C  35: RSV08 */
-#define EC_RSV09_IRQn 20 /* 0x24  0x0090  36: RSV09 */
-#define EC_RSV10_IRQn 21 /* 0x25  0x0094  37: RSV10 */
-#define EC_RSV11_IRQn 22 /* 0x26  0x0098  38: RSV11 */
-#define EC_FLC_IRQn 23 /* 0x27  0x009C  39: FLC */
-#define EC_GPIO0_IRQn 24 /* 0x28  0x00A0  40: GPIO0 */
-#define EC_RSV12_IRQn 25 /* 0x29  0x00A4  41: RSV12 */
-#define EC_RSV13_IRQn 26 /* 0x2A  0x00A8  42: RSV13 */
-#define EC_RSV14_IRQn 27 /* 0x2B  0x00AC  43: RSV14 */
-#define EC_DMA0_IRQn 28 /* 0x2C  0x00B0  44: DMA0 */
-#define EC_DMA1_IRQn 29 /* 0x2D  0x00B4  45: DMA1 */
-#define EC_DMA2_IRQn 30 /* 0x2E  0x00B8  46: DMA2 */
-#define EC_DMA3_IRQn 31 /* 0x2F  0x00BC  47: DMA3 */
-#define EC_RSV15_IRQn 32 /* 0x30  0x00C0  48: RSV15 */
-#define EC_RSV16_IRQn 33 /* 0x31  0x00C4  49: RSV16 */
-#define EC_RSV17_IRQn 34 /* 0x32  0x00C8  50: RSV17 */
-#define EC_RSV18_IRQn 35 /* 0x33  0x00CC  51: RSV18 */
-#define EC_I2C1_IRQn 36 /* 0x34  0x00D0  52: I2C1 */
-#define EC_RSV19_IRQn 37 /* 0x35  0x00D4  53: RSV19 */
-#define EC_RSV20_IRQn 38 /* 0x36  0x00D8  54: RSV20 */
-#define EC_RSV21_IRQn 39 /* 0x37  0x00DC  55: RSV21 */
-#define EC_RSV22_IRQn 40 /* 0x38  0x00E0  56: RSV22 */
-#define EC_RSV23_IRQn 41 /* 0x39  0x00E4  57: RSV23 */
-#define EC_RSV24_IRQn 42 /* 0x3A  0x00E8  58: RSV24 */
-#define EC_RSV25_IRQn 43 /* 0x3B  0x00EC  59: RSV25 */
-#define EC_RSV26_IRQn 44 /* 0x3C  0x00F0  60: RSV26 */
-#define EC_RSV27_IRQn 45 /* 0x3D  0x00F4  61: RSV27 */
-#define EC_RSV28_IRQn 46 /* 0x3E  0x00F8  62: RSV28 */
-#define EC_RSV29_IRQn 47 /* 0x3F  0x00FC  63: RSV29 */
-#define EC_RSV30_IRQn 48 /* 0x40  0x0100  64: RSV30 */
-#define EC_RSV31_IRQn 49 /* 0x41  0x0104  65: RSV31 */
-#define EC_RSV32_IRQn 50 /* 0x42  0x0108  66: RSV32 */
-#define EC_RSV33_IRQn 51 /* 0x43  0x010C  67: RSV33 */
-#define EC_RSV34_IRQn 52 /* 0x44  0x0110  68: RSV34 */
-#define EC_RSV35_IRQn 53 /* 0x45  0x0114  69: RSV35 */
-#define EC_GPIOWAKE_IRQn 54 /* 0x46  0x0118  70: GPIO Wakeup */
-
-#ifndef HIRC96_FREQ
-#define HIRC96_FREQ 96000000
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
-#ifndef PeripheralClock
-#define PeripheralClock    \
-	(SystemCoreClock / \
-	 2) /*!< Peripheral Clock Frequency                  \
-			       */
-#endif
-
-#define MXC_FLASH_MEM_BASE 0x00000000UL
-#define MXC_FLASH_PAGE_SIZE 0x00002000UL
-#define MXC_FLASH_MEM_SIZE 0x00040000UL
-#define MXC_INFO_MEM_BASE 0x00040000UL
-#define MXC_INFO_MEM_SIZE 0x00001000UL
-#define MXC_SRAM_MEM_BASE 0x20000000UL
-#define MXC_SRAM_MEM_SIZE 0x00018000UL
-
-/*
-   Base addresses and configuration settings for all MAX32660 peripheral
-   modules.
-*/
-
-/******************************************************************************/
-/*                                                             Global control */
-#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
-#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
-
-/******************************************************************************/
-/*                                            Non-battery backed SI Registers */
-#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
-#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
-
-/******************************************************************************/
-/*                                                                   Watchdog */
-#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
-#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
-
-/******************************************************************************/
-/*                                                            Real Time Clock */
-#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
-#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
-
-/******************************************************************************/
-/*                                                            Power Sequencer */
-#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
-#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
-
-/******************************************************************************/
-/*                                                                       GPIO */
-#define MXC_CFG_GPIO_INSTANCES (1)
-#define MXC_CFG_GPIO_PINS_PORT (14)
-
-#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
-#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
-
-#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1)
-
-#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
-
-#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
-
-#define PORT_0 ((uint32_t)(0UL)) /**< Port 0  Define*/
-#define PORT_1 ((uint32_t)(1UL)) /**< Port 1  Define*/
-#define PORT_2 ((uint32_t)(2UL)) /**< Port 2  Define*/
-#define PORT_3 ((uint32_t)(3UL)) /**< Port 3  Define*/
-#define PORT_4 ((uint32_t)(4UL)) /**< Port 4  Define*/
-
-#define GPIO_0 PORT_0 /**< Port 0  Define*/
-#define GPIO_1 PORT_1 /**< Port 1  Define*/
-#define GPIO_2 PORT_2 /**< Port 2  Define*/
-#define GPIO_3 PORT_3 /**< Port 3  Define*/
-#define GPIO_4 PORT_4 /**< Port 4  Define*/
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_0
-
-/******************************************************************************/
-/*                                                                        I2C */
-#define MXC_I2C_INSTANCES (2)
-#define MXC_I2C_FIFO_DEPTH (8)
-
-#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
-#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
-#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
-#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
-
-#define MXC_I2C_GET_IRQ(i) \
-	(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
-
-#define MXC_I2C_GET_BASE(i) \
-	((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
-
-#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
-
-#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
-
-#define MXC_CFG_TMR_INSTANCES (3)
-
-#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
-#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
-#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
-#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
-#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
-#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
-
-#define MXC_TMR_GET_IRQ(i)              \
-	(IRQn_Type)((i) == 0 ?          \
-			    TMR0_IRQn : \
-			    (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
-
-#define MXC_TMR_GET_BASE(i)         \
-	((i) == 0 ? MXC_BASE_TMR0 : \
-		    (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
-
-#define MXC_TMR_GET_TMR(i) \
-	((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
-
-#define MXC_TMR_GET_IDX(p) \
-	((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1)
-
-/******************************************************************************/
-/*                                                                        FLC */
-#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
-#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
-
-/******************************************************************************/
-/*                                                          Instruction Cache */
-#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
-#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
-
-/******************************************************************************/
-/*                                               UART / Serial Port Interface */
-
-#define MXC_UART_INSTANCES (2)
-#define MXC_UART_FIFO_DEPTH (8)
-
-#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
-#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
-#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
-#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
-
-#define MXC_UART_GET_IRQ(i) \
-	(IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0)
-
-#define MXC_UART_GET_BASE(i) \
-	((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0)
-
-#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0)
-
-#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1)
-
-#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/max32660/system_chip.c b/chip/max32660/system_chip.c
deleted file mode 100644
index 07127dc8c5..0000000000
--- a/chip/max32660/system_chip.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 System module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "registers.h"
-#include "gcr_regs.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-void chip_pre_init(void)
-{
-}
-
-void system_pre_init(void)
-{
-}
-
-void system_reset(int flags)
-{
-	MXC_GCR->rstr0 = MXC_F_GCR_RSTR0_SYSTEM;
-	while (1)
-		;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "maxim";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "max32660";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "A1";
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h
deleted file mode 100644
index 946cacbc50..0000000000
--- a/chip/max32660/tmr_regs.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the TMR Peripheral */
-
-#ifndef _TMR_REGS_H_
-#define _TMR_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * 32-bit reloadable timer that can be used for timing and event
- * counting.
- */
-
-/**
- * Structure type to access the TMR Registers.
- */
-typedef struct {
-	__IO uint32_t cnt;    /**< <tt>\b 0x00:<\tt> TMR CNT Register */
-	__IO uint32_t cmp;    /**< <tt>\b 0x04:<\tt> TMR CMP Register */
-	__IO uint32_t pwm;    /**< <tt>\b 0x08:<\tt> TMR PWM Register */
-	__IO uint32_t intr;   /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x10:<\tt> TMR CN Register */
-	__IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */
-} mxc_tmr_regs_t;
-
-/**
- * TMR Peripheral Register Offsets from the TMR Base Peripheral
- * Address.
- */
-#define MXC_R_TMR_CNT                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_TMR_CMP                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x004 */
-#define MXC_R_TMR_PWM                                                          \
-	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x008 */
-#define MXC_R_TMR_INTR                                                         \
-	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x00C */
-#define MXC_R_TMR_CN                                                           \
-	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x010 */
-#define MXC_R_TMR_NOLCMP                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt>       \
-				    0x0x014 */
-
-/**
- * Clear Interrupt. Writing a value (0 or 1) to a bit in this register
- * clears the associated interrupt.
- */
-#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
-#define MXC_F_TMR_INTR_IRQ_CLR                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
-
-/**
- * Timer Control Register.
- */
-#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
-#define MXC_F_TMR_CN_TMODE                                                     \
-	((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
-#define MXC_V_TMR_CN_TMODE_ONESHOT                                             \
-	((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
-#define MXC_S_TMR_CN_TMODE_ONESHOT                                             \
-	(MXC_V_TMR_CN_TMODE_ONESHOT                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
-#define MXC_V_TMR_CN_TMODE_CONTINUOUS                                          \
-	((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
-#define MXC_S_TMR_CN_TMODE_CONTINUOUS                                          \
-	(MXC_V_TMR_CN_TMODE_CONTINUOUS                                         \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
-#define MXC_V_TMR_CN_TMODE_COUNTER                                             \
-	((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
-#define MXC_S_TMR_CN_TMODE_COUNTER                                             \
-	(MXC_V_TMR_CN_TMODE_COUNTER                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
-#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
-#define MXC_S_TMR_CN_TMODE_PWM                                                 \
-	(MXC_V_TMR_CN_TMODE_PWM                                                \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURE                                             \
-	((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURE                                             \
-	(MXC_V_TMR_CN_TMODE_CAPTURE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
-#define MXC_V_TMR_CN_TMODE_COMPARE                                             \
-	((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
-#define MXC_S_TMR_CN_TMODE_COMPARE                                             \
-	(MXC_V_TMR_CN_TMODE_COMPARE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
-#define MXC_V_TMR_CN_TMODE_GATED                                               \
-	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value                            \
-			   */
-#define MXC_S_TMR_CN_TMODE_GATED                                               \
-	(MXC_V_TMR_CN_TMODE_GATED                                              \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                     \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
-
-#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
-#define MXC_F_TMR_CN_PRES                                                      \
-	((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
-#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL)     /**< CN_PRES_DIV1 Value */
-#define MXC_S_TMR_CN_PRES_DIV1                                                 \
-	(MXC_V_TMR_CN_PRES_DIV1                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV1 Setting */
-#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
-#define MXC_S_TMR_CN_PRES_DIV2                                                 \
-	(MXC_V_TMR_CN_PRES_DIV2                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV2 Setting */
-#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
-#define MXC_S_TMR_CN_PRES_DIV4                                                 \
-	(MXC_V_TMR_CN_PRES_DIV4                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV4 Setting */
-#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
-#define MXC_S_TMR_CN_PRES_DIV8                                                 \
-	(MXC_V_TMR_CN_PRES_DIV8                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV8 Setting */
-#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
-#define MXC_S_TMR_CN_PRES_DIV16                                                \
-	(MXC_V_TMR_CN_PRES_DIV16                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV16 Setting */
-#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
-#define MXC_S_TMR_CN_PRES_DIV32                                                \
-	(MXC_V_TMR_CN_PRES_DIV32                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV32 Setting */
-#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
-#define MXC_S_TMR_CN_PRES_DIV64                                                \
-	(MXC_V_TMR_CN_PRES_DIV64                                               \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
-#define MXC_V_TMR_CN_PRES_DIV128                                               \
-	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value                            \
-			   */
-#define MXC_S_TMR_CN_PRES_DIV128                                               \
-	(MXC_V_TMR_CN_PRES_DIV128                                              \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
-
-#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
-#define MXC_F_TMR_CN_TPOL                                                      \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
-#define MXC_V_TMR_CN_TPOL_ACTIVEHI                                             \
-	((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVEHI                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVEHI                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
-#define MXC_V_TMR_CN_TPOL_ACTIVELO                                             \
-	((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVELO                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVELO                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
-
-#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
-#define MXC_F_TMR_CN_TEN                                                       \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
-#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL)      /**< CN_TEN_DIS Value */
-#define MXC_S_TMR_CN_TEN_DIS                                                   \
-	(MXC_V_TMR_CN_TEN_DIS                                                  \
-	 << MXC_F_TMR_CN_TEN_POS)	     /**< CN_TEN_DIS Setting */
-#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
-#define MXC_S_TMR_CN_TEN_EN                                                    \
-	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting   \
-						       */
-
-#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
-#define MXC_F_TMR_CN_PRES3                                                     \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
-
-#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
-#define MXC_F_TMR_CN_PWMSYNC                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask   \
-							 */
-#define MXC_V_TMR_CN_PWMSYNC_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_PWMSYNC_DIS                                               \
-	(MXC_V_TMR_CN_PWMSYNC_DIS                                              \
-	 << MXC_F_TMR_CN_PWMSYNC_POS)		  /**< CN_PWMSYNC_DIS Setting */
-#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
-#define MXC_S_TMR_CN_PWMSYNC_EN                                                \
-	(MXC_V_TMR_CN_PWMSYNC_EN                                               \
-	 << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
-
-#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
-#define MXC_F_TMR_CN_NOLHPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask   \
-							 */
-#define MXC_V_TMR_CN_NOLHPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_NOLHPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLHPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLHPOL_POS)		  /**< CN_NOLHPOL_DIS Setting */
-#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
-#define MXC_S_TMR_CN_NOLHPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLHPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
-
-#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
-#define MXC_F_TMR_CN_NOLLPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask   \
-							 */
-#define MXC_V_TMR_CN_NOLLPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_NOLLPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLLPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLLPOL_POS)		  /**< CN_NOLLPOL_DIS Setting */
-#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
-#define MXC_S_TMR_CN_NOLLPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLLPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
-
-#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
-#define MXC_F_TMR_CN_PWMCKBD                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask   \
-							 */
-#define MXC_V_TMR_CN_PWMCKBD_DIS                                               \
-	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value                            \
-			   */
-#define MXC_S_TMR_CN_PWMCKBD_DIS                                               \
-	(MXC_V_TMR_CN_PWMCKBD_DIS                                              \
-	 << MXC_F_TMR_CN_PWMCKBD_POS)		  /**< CN_PWMCKBD_DIS Setting */
-#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
-#define MXC_S_TMR_CN_PWMCKBD_EN                                                \
-	(MXC_V_TMR_CN_PWMCKBD_EN                                               \
-	 << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
-
-/**
- * Timer Non-Overlapping Compare Register.
- */
-#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
-#define MXC_F_TMR_NOLCMP_NOLLCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
-
-#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
-#define MXC_F_TMR_NOLCMP_NOLHCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TMR_REGS_H_ */
diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c
deleted file mode 100644
index c30a6ebd45..0000000000
--- a/chip/max32660/uart_chip.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Console UART Module for Chrome EC */
-
-#include <stdint.h>
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "registers.h"
-#include "tmr_regs.h"
-#include "gpio_regs.h"
-#include "common.h"
-#include "gcr_regs.h"
-#include "uart_regs.h"
-
-static int done_uart_init_yet;
-
-#ifndef UARTN
-#define UARTN CONFIG_UART_HOST
-#endif
-
-#if (UARTN == 0)
-#define MXC_UART MXC_UART0
-#define EC_UART_IRQn EC_UART0_IRQn
-#elif (UARTN == 1)
-#define MXC_UART MXC_UART1
-#define EC_UART_IRQn EC_UART1_IRQn
-#else
-#error "MAX32660 supports only UART 0 or 1 for EC console"
-#endif
-
-#define UART_BAUD 115200
-
-#define UART_ER_IF                                                             \
-	(MXC_F_UART_INT_FL_RX_FRAME_ERROR |                                    \
-	 MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN)
-
-#define UART_ER_IE                                                             \
-	(MXC_F_UART_INT_EN_RX_FRAME_ERROR |                                    \
-	 MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN)
-
-#define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH)
-
-#define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH)
-
-#define UART_TX_IF                                                             \
-	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY |                 \
-	 MXC_F_UART_INT_FL_TX_FIFO_THRESH)
-
-#define UART_TX_IE                                                             \
-	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY |                 \
-	 MXC_F_UART_INT_EN_TX_FIFO_THRESH)
-
-#define UART_RX_THRESHOLD_LEVEL 1
-
-/**
- * Alternate clock rate. (7.3728MHz) */
-#define UART_ALTERNATE_CLOCK_HZ 7372800
-
-/* ************************************************************************* */
-static unsigned int uart_number_write_available(mxc_uart_regs_t *uart)
-{
-	return MXC_UART_FIFO_DEPTH -
-	       ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >>
-		MXC_F_UART_STATUS_TX_FIFO_CNT_POS);
-}
-
-/* ************************************************************************* */
-static unsigned int uart_number_read_available(mxc_uart_regs_t *uart)
-{
-	return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >>
-		MXC_F_UART_STATUS_RX_FIFO_CNT_POS);
-}
-
-static void uartn_enable_tx_interrupt(int uart_num)
-{
-	// Enable the interrupts
-	MXC_UART_GET_UART(uart_num)->int_en |= UART_TX_IE;
-}
-
-static void uartn_disable_tx_interrupt(int uart_num)
-{
-	// Disable the interrupts
-	MXC_UART_GET_UART(uart_num)->int_en &= ~UART_TX_IE;
-}
-
-static int uartn_tx_in_progress(int uart_num)
-{
-	return ((MXC_UART_GET_UART(uart_num)->status &
-		 (MXC_F_UART_STATUS_TX_BUSY)) != 0);
-}
-
-static void uartn_tx_flush(int uart_num)
-{
-	while (uartn_tx_in_progress(uart_num)) {
-	}
-}
-
-static int uartn_tx_ready(int uart_num)
-{
-	int avail;
-	avail = uart_number_write_available(MXC_UART_GET_UART(uart_num));
-	/* True if the TX buffer is not completely full */
-	return (avail != 0);
-}
-
-static int uartn_rx_available(int uart_num)
-{
-	int avail;
-	/* True if the RX buffer is not completely empty. */
-	avail = uart_number_read_available(MXC_UART_GET_UART(uart_num));
-	return (avail != 0);
-}
-
-static void uartn_write_char(int uart_num, char c)
-{
-	int avail;
-	mxc_uart_regs_t *uart;
-
-	uart = MXC_UART_GET_UART(uart_num);
-	/* Refill the TX FIFO */
-	avail = uart_number_write_available(uart);
-
-	/* wait until there is room in the fifo */
-	while (avail == 0) {
-		avail = uart_number_write_available(uart);
-	}
-
-	/* stuff the fifo with the character */
-	uart->fifo = c;
-}
-
-static int uartn_read_char(int uart_num)
-{
-	int c;
-	c = MXC_UART_GET_UART(uart_num)->fifo;
-	return c;
-}
-
-static void uartn_clear_interrupt_flags(int uart_num)
-{
-	uint32_t flags;
-	// Read and clear interrupts
-	//    intst = MXC_UART_GET_UART(uart_num)->int_fl;
-	//    MXC_UART_GET_UART(uart_num)->int_fl = ~intst;
-
-	flags = MXC_UART_GET_UART(uart_num)->int_fl;
-	MXC_UART_GET_UART(uart_num)->int_fl = flags;
-}
-
-static inline int uartn_is_rx_interrupt(int uart_num)
-{
-	return MXC_UART_GET_UART(uart_num)->int_fl & UART_RX_IF;
-}
-
-static inline int uartn_is_tx_interrupt(int uart_num)
-{
-	return MXC_UART_GET_UART(uart_num)->int_fl & UART_TX_IF;
-}
-
-int uart_init_done(void)
-{
-	return done_uart_init_yet;
-}
-
-void uart_tx_start(void)
-{
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.
-	 */
-	uartn_enable_tx_interrupt(UARTN);
-	task_trigger_irq(EC_UART_IRQn);
-}
-
-void uart_tx_stop(void)
-{
-	uartn_disable_tx_interrupt(UARTN);
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_in_progress(void)
-{
-	return uartn_tx_in_progress(UARTN);
-}
-
-void uart_tx_flush(void)
-{
-	uartn_tx_flush(UARTN);
-}
-
-int uart_tx_ready(void)
-{
-	/* True if the TX buffer is not completely full */
-	return uartn_tx_ready(UARTN);
-}
-
-int uart_rx_available(void)
-{
-	/* True if the RX buffer is not completely empty. */
-	return uartn_rx_available(UARTN);
-}
-
-void uart_write_char(char c)
-{
-	/* write a character to the UART */
-	uartn_write_char(UARTN, c);
-}
-
-int uart_read_char(void)
-{
-	return uartn_read_char(UARTN);
-}
-
-/**
- * Interrupt handlers for UART
- */
-void uart_rxtx_interrupt(void)
-{
-	/* Process the Console Input */
-	uart_process_input();
-	/* Process the Buffered Console Output */
-	uart_process_output();
-	uartn_clear_interrupt_flags(UARTN);
-}
-DECLARE_IRQ(EC_UART_IRQn, uart_rxtx_interrupt, 1);
-
-void uart_init(void)
-{
-	uint32_t flags;
-	uint32_t baud0 = 0, baud1 = 0, div;
-	int32_t factor = -1;
-
-	/* Init the GPIO Port Mapping */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Drain FIFOs and enable UART and set configuration */
-	MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
-
-	/* Set the baud rate */
-	div = PeripheralClock / (UART_BAUD); 	// constant part of DIV (i.e. DIV
-					     					// * (Baudrate*factor_int))
-
-	do {
-		factor += 1;
-		baud0 = div >> (7 - factor); 	// divide by 128,64,32,16 to
-					     				// extract integer part
-		baud1 = ((div << factor) -
-			 (baud0 << 7)); 			// subtract factor corrected div -
-										// integer parts
-
-	} while ((baud0 == 0) && (factor < 4));
-
-	MXC_UART->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0);
-	MXC_UART->baud1 = baud1;
-
-	MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL
-			    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
-
-	/* Clear Interrupt Flags */
-	flags = MXC_UART->int_fl;
-	MXC_UART->int_fl = flags;
-
-	/* Enable the RX interrupts */
-	MXC_UART->int_en |= UART_RX_IE;
-
-	/* Enable the IRQ */
-	task_enable_irq(EC_UART_IRQn);
-	/* Set a flag for the system that the UART has been initialized */
-	done_uart_init_yet = 1;
-}
diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h
deleted file mode 100644
index a2de0cc0a0..0000000000
--- a/chip/max32660/uart_regs.h
+++ /dev/null
@@ -1,677 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the UART Peripheral */
-
-#ifndef _UART_REGS_H_
-#define _UART_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the UART Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */
-	__IO uint32_t
-		thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */
-	__I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */
-	__IO uint32_t int_en;  /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
-	__IO uint32_t int_fl;  /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
-	__IO uint32_t baud0;   /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
-	__IO uint32_t baud1;   /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
-	__IO uint32_t fifo;    /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
-	__IO uint32_t dma;     /**< <tt>\b 0x20:<\tt> UART DMA Register */
-	__IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */
-} mxc_uart_regs_t;
-
-/**
- * UART Peripheral Register Offsets from the UART Base Peripheral
- * Address.
- */
-#define MXC_R_UART_CTRL                                                        \
-	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x000 */
-#define MXC_R_UART_THRESH_CTRL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x004 */
-#define MXC_R_UART_STATUS                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x008 */
-#define MXC_R_UART_INT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x00C */
-#define MXC_R_UART_INT_FL                                                      \
-	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x010 */
-#define MXC_R_UART_BAUD0                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x014 */
-#define MXC_R_UART_BAUD1                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x018 */
-#define MXC_R_UART_FIFO                                                        \
-	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x01C */
-#define MXC_R_UART_DMA                                                         \
-	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x020 */
-#define MXC_R_UART_TX_FIFO                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt>      \
-				    0x0x024 */
-
-/**
- * Control Register.
- */
-#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
-#define MXC_F_UART_CTRL_ENABLE                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
-#define MXC_V_UART_CTRL_ENABLE_DIS                                             \
-	((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
-#define MXC_S_UART_CTRL_ENABLE_DIS                                             \
-	(MXC_V_UART_CTRL_ENABLE_DIS                                            \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
-#define MXC_V_UART_CTRL_ENABLE_EN                                              \
-	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value                            \
-			   */
-#define MXC_S_UART_CTRL_ENABLE_EN                                              \
-	(MXC_V_UART_CTRL_ENABLE_EN                                             \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
-
-#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
-#define MXC_F_UART_CTRL_PARITY_EN                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
-#define MXC_V_UART_CTRL_PARITY_EN_DIS                                          \
-	((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
-#define MXC_S_UART_CTRL_PARITY_EN_DIS                                          \
-	(MXC_V_UART_CTRL_PARITY_EN_DIS                                         \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
-#define MXC_V_UART_CTRL_PARITY_EN_EN                                           \
-	((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
-#define MXC_S_UART_CTRL_PARITY_EN_EN                                           \
-	(MXC_V_UART_CTRL_PARITY_EN_EN                                          \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
-
-#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
-#define MXC_F_UART_CTRL_PARITY                                                 \
-	((uint32_t)(                                                           \
-		0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
-#define MXC_V_UART_CTRL_PARITY_EVEN                                            \
-	((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
-#define MXC_S_UART_CTRL_PARITY_EVEN                                            \
-	(MXC_V_UART_CTRL_PARITY_EVEN                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
-#define MXC_V_UART_CTRL_PARITY_ODD                                             \
-	((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
-#define MXC_S_UART_CTRL_PARITY_ODD                                             \
-	(MXC_V_UART_CTRL_PARITY_ODD                                            \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
-#define MXC_V_UART_CTRL_PARITY_MARK                                            \
-	((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
-#define MXC_S_UART_CTRL_PARITY_MARK                                            \
-	(MXC_V_UART_CTRL_PARITY_MARK                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
-#define MXC_V_UART_CTRL_PARITY_SPACE                                           \
-	((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
-#define MXC_S_UART_CTRL_PARITY_SPACE                                           \
-	(MXC_V_UART_CTRL_PARITY_SPACE                                          \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
-
-#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
-#define MXC_F_UART_CTRL_PARMD                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask  \
-							  */
-#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
-#define MXC_S_UART_CTRL_PARMD_1                                                \
-	(MXC_V_UART_CTRL_PARMD_1                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS)		  /**< CTRL_PARMD_1 Setting */
-#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
-#define MXC_S_UART_CTRL_PARMD_0                                                \
-	(MXC_V_UART_CTRL_PARMD_0                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
-
-#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
-#define MXC_F_UART_CTRL_TX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
-
-#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
-#define MXC_F_UART_CTRL_RX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
-
-#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
-#define MXC_F_UART_CTRL_BITACC                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
-#define MXC_V_UART_CTRL_BITACC_FRAME                                           \
-	((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
-#define MXC_S_UART_CTRL_BITACC_FRAME                                           \
-	(MXC_V_UART_CTRL_BITACC_FRAME                                          \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
-#define MXC_V_UART_CTRL_BITACC_BIT                                             \
-	((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
-#define MXC_S_UART_CTRL_BITACC_BIT                                             \
-	(MXC_V_UART_CTRL_BITACC_BIT                                            \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
-
-#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
-#define MXC_F_UART_CTRL_CHAR_SIZE                                              \
-	((uint32_t)(                                                           \
-		0x3UL                                                          \
-		<< MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
-#define MXC_V_UART_CTRL_CHAR_SIZE_5                                            \
-	((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_5                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_5                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_6                                            \
-	((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_6                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_6                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_7                                            \
-	((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_7                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_7                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_8                                            \
-	((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_8                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_8                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
-
-#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
-#define MXC_F_UART_CTRL_STOPBITS                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
-#define MXC_V_UART_CTRL_STOPBITS_1                                             \
-	((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1                                             \
-	(MXC_V_UART_CTRL_STOPBITS_1                                            \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
-#define MXC_V_UART_CTRL_STOPBITS_1_5                                           \
-	((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1_5                                           \
-	(MXC_V_UART_CTRL_STOPBITS_1_5                                          \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
-
-#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
-#define MXC_F_UART_CTRL_FLOW_CTRL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
-#define MXC_V_UART_CTRL_FLOW_CTRL_EN                                           \
-	((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_EN                                           \
-	(MXC_V_UART_CTRL_FLOW_CTRL_EN                                          \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
-#define MXC_V_UART_CTRL_FLOW_CTRL_DIS                                          \
-	((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                                          \
-	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                                         \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
-
-#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
-#define MXC_F_UART_CTRL_FLOW_POL                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
-#define MXC_V_UART_CTRL_FLOW_POL_0                                             \
-	((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_0                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_0                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
-#define MXC_V_UART_CTRL_FLOW_POL_1                                             \
-	((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_1                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_1                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
-
-#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
-#define MXC_F_UART_CTRL_NULL_MODEM                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
-							     Mask */
-#define MXC_V_UART_CTRL_NULL_MODEM_DIS                                         \
-	((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                         \
-	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                        \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting   \
-					     */
-#define MXC_V_UART_CTRL_NULL_MODEM_EN                                          \
-	((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_EN                                          \
-	(MXC_V_UART_CTRL_NULL_MODEM_EN                                         \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
-
-#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
-#define MXC_F_UART_CTRL_BREAK                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask  \
-							  */
-#define MXC_V_UART_CTRL_BREAK_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value                            \
-			   */
-#define MXC_S_UART_CTRL_BREAK_DIS                                              \
-	(MXC_V_UART_CTRL_BREAK_DIS                                             \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
-#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
-#define MXC_S_UART_CTRL_BREAK_EN                                               \
-	(MXC_V_UART_CTRL_BREAK_EN                                              \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
-
-#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
-#define MXC_F_UART_CTRL_CLKSEL                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
-#define MXC_V_UART_CTRL_CLKSEL_SYSTEM                                          \
-	((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
-#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                                          \
-	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                                         \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
-#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
-#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                      \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
-
-#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
-#define MXC_F_UART_CTRL_RX_TO                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
-
-/**
- * Threshold Control register.
- */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS                              \
-	0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_RX_FIFO_THRESH \
-								  Mask */
-
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS                              \
-	8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_TX_FIFO_THRESH \
-								  Mask */
-
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS                             \
-	16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                 \
-	((uint32_t)(                                                                           \
-		0x3FUL                                                                         \
-		<< MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
-								   THRESH_CTRL_RTS_FIFO_THRESH \
-								   Mask */
-
-/**
- * Status Register.
- */
-#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
-#define MXC_F_UART_STATUS_TX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
-
-#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
-#define MXC_F_UART_STATUS_RX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
-
-#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
-#define MXC_F_UART_STATUS_PARITY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
-
-#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
-#define MXC_F_UART_STATUS_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
-
-#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_UART_STATUS_RX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
-							     Mask */
-
-#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
-#define MXC_F_UART_STATUS_RX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
-
-#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_UART_STATUS_TX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
-							     Mask */
-
-#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
-#define MXC_F_UART_STATUS_TX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
-
-#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS                                      \
-	8 /**< STATUS_RX_FIFO_CNT Position                                     \
-	   */
-#define MXC_F_UART_STATUS_RX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS                                      \
-	16 /**< STATUS_TX_FIFO_CNT Position                                    \
-	    */
-#define MXC_F_UART_STATUS_TX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
-#define MXC_F_UART_STATUS_RX_TO                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
-
-/**
- * Interrupt Enable Register.
- */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS                                   \
-	0 /**< INT_EN_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_EN_RX_FRAME_ERROR \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS                                  \
-	1 /**< INT_EN_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_EN_RX_PARITY_ERROR \
-							      Mask */
-
-#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
-#define MXC_F_UART_INT_EN_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
-#define MXC_F_UART_INT_EN_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS                                   \
-	4 /**< INT_EN_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_RX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS                             \
-	5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_EN_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS                                   \
-	6 /**< INT_EN_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_TX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
-#define MXC_F_UART_INT_EN_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
-
-#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
-#define MXC_F_UART_INT_EN_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT   \
-							 Mask */
-
-#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
-#define MXC_F_UART_INT_EN_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK   \
-							 Mask */
-
-/**
- * Interrupt Status Flags.
- */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS                                   \
-	0 /**< INT_FL_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_FL_RX_FRAME_ERROR \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS                                  \
-	1 /**< INT_FL_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_FL_RX_PARITY_ERROR \
-							      Mask */
-
-#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
-#define MXC_F_UART_INT_FL_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
-#define MXC_F_UART_INT_FL_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS                                   \
-	4 /**< INT_FL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_RX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS                             \
-	5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_FL_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS                                   \
-	6 /**< INT_FL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_TX_FIFO_THRESH \
-							     Mask */
-
-#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
-#define MXC_F_UART_INT_FL_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
-
-#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
-#define MXC_F_UART_INT_FL_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT   \
-							 Mask */
-
-#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
-#define MXC_F_UART_INT_FL_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK   \
-							 Mask */
-
-/**
- * Baud rate register. Integer portion.
- */
-#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
-#define MXC_F_UART_BAUD0_IBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
-
-#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
-#define MXC_F_UART_BAUD0_FACTOR                                                \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
-#define MXC_V_UART_BAUD0_FACTOR_128                                            \
-	((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
-#define MXC_S_UART_BAUD0_FACTOR_128                                            \
-	(MXC_V_UART_BAUD0_FACTOR_128                                           \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_64                                             \
-	((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
-#define MXC_S_UART_BAUD0_FACTOR_64                                             \
-	(MXC_V_UART_BAUD0_FACTOR_64                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_32                                             \
-	((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
-#define MXC_S_UART_BAUD0_FACTOR_32                                             \
-	(MXC_V_UART_BAUD0_FACTOR_32                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_16                                             \
-	((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
-#define MXC_S_UART_BAUD0_FACTOR_16                                             \
-	(MXC_V_UART_BAUD0_FACTOR_16                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
-
-/**
- * Baud rate register. Decimal Setting.
- */
-#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
-#define MXC_F_UART_BAUD1_DBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
-
-/**
- * FIFO Data buffer.
- */
-#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
-#define MXC_F_UART_FIFO_FIFO                                                   \
-	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask   \
-							  */
-
-
-/**
- * DMA Configuration.
- */
-#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
-#define MXC_F_UART_DMA_TDMA_EN                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
-#define MXC_V_UART_DMA_TDMA_EN_DIS                                             \
-	((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_TDMA_EN_DIS                                             \
-	(MXC_V_UART_DMA_TDMA_EN_DIS                                            \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_TDMA_EN_EN                                              \
-	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value                            \
-			   */
-#define MXC_S_UART_DMA_TDMA_EN_EN                                              \
-	(MXC_V_UART_DMA_TDMA_EN_EN                                             \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
-
-#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
-#define MXC_F_UART_DMA_RXDMA_EN                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
-#define MXC_V_UART_DMA_RXDMA_EN_DIS                                            \
-	((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_RXDMA_EN_DIS                                            \
-	(MXC_V_UART_DMA_RXDMA_EN_DIS                                           \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_RXDMA_EN_EN                                             \
-	((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
-#define MXC_S_UART_DMA_RXDMA_EN_EN                                             \
-	(MXC_V_UART_DMA_RXDMA_EN_EN                                            \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
-
-#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_TXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL   \
-							   Mask */
-
-#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_RXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL   \
-							   Mask */
-
-/**
- * Transmit FIFO Status register.
- */
-#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
-#define MXC_F_UART_TX_FIFO_DATA                                                \
-	((uint32_t)(0x7FUL                                                     \
-		    << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
-
-#endif /* _UART_REGS_H_ */
diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c
deleted file mode 100644
index 1c99c798fc..0000000000
--- a/chip/max32660/wdt_chip.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Watchdog Module */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-#include "console.h"
-#include "registers.h"
-#include "board.h"
-#include "wdt_regs.h"
-
-#define CPUTS(outstr) cputs(CC_COMMAND, outstr)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
-
-/* For a System clock of 96MHz, 
- *     Time in seconds = 96000000 / 2 * 2^power
- * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
- *     Time in seconds = 96000000 / 2 * 2^29
- *                     = 11.1 Seconds
- */
-#define WATCHDOG_TIMER_PERIOD MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
-
-volatile int starve_dog = 0;
-
-void watchdog_reload(void)
-{
-	if (!starve_dog) {
-		/* Reset the watchdog */
-		MXC_WDT0->rst = 0x00A5;
-		MXC_WDT0->rst = 0x005A;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Set the Watchdog period */
-	MXC_SETFIELD(MXC_WDT0->ctrl, MXC_F_WDT_CTRL_RST_PERIOD,
-		     (WATCHDOG_TIMER_PERIOD << 4));
-
-	/* We want the WD to reset us if it is not fed in time. */
-	MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_RST_EN;
-	/* Enable the watchdog */
-	MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_WDT_EN;
-	/* Reset the watchdog */
-	MXC_WDT0->rst = 0x00A5;
-	MXC_WDT0->rst = 0x005A;
-	return EC_SUCCESS;
-}
-
-static int command_watchdog_test(int argc, char **argv)
-{
-	starve_dog = 1;
-
-	CPRINTS("done command_watchdog_test.");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(wdttest, command_watchdog_test, "wdttest",
-			"Force a WDT reset.");
diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h
deleted file mode 100644
index 32d6fe0925..0000000000
--- a/chip/max32660/wdt_regs.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the WDT Peripheral */
-
-#ifndef _WDT_REGS_H_
-#define _WDT_REGS_H_
-
-#include <stdint.h>
-
-/*
-    If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/**
- * Structure type to access the WDT Registers.
- */
-typedef struct {
-	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> WDT CTRL Register */
-	__O uint32_t rst;   /**< <tt>\b 0x04:<\tt> WDT RST Register */
-} mxc_wdt_regs_t;
-
-/**
- * WDT Peripheral Register Offsets from the WDT Base Peripheral
- * Address.
- */
-#define MXC_R_WDT_CTRL                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt>       \
-				    0x0x000 */
-#define MXC_R_WDT_RST                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt>       \
-				    0x0x004 */
-
-/**
- * Watchdog Timer Control Register.
- */
-#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
-#define MXC_F_WDT_CTRL_INT_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17      \
-					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16      \
-					      Setting */
-
-#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
-#define MXC_F_WDT_CTRL_RST_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17      \
-					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16      \
-					      Setting */
-
-#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
-#define MXC_F_WDT_CTRL_WDT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
-#define MXC_V_WDT_CTRL_WDT_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_WDT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_WDT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_WDT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_WDT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_WDT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
-#define MXC_F_WDT_CTRL_INT_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
-#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                      \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting   \
-					  */
-#define MXC_V_WDT_CTRL_INT_FLAG_PENDING                                        \
-	((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                                        \
-	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                                       \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
-
-#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
-#define MXC_F_WDT_CTRL_INT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
-#define MXC_V_WDT_CTRL_INT_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_INT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_INT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_INT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_INT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_INT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
-#define MXC_F_WDT_CTRL_RST_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
-#define MXC_V_WDT_CTRL_RST_EN_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
-#define MXC_S_WDT_CTRL_RST_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_RST_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_RST_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value                            \
-			   */
-#define MXC_S_WDT_CTRL_RST_EN_EN                                               \
-	(MXC_V_WDT_CTRL_RST_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
-
-#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
-#define MXC_F_WDT_CTRL_RST_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
-#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                       \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
-#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                      \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting   \
-					  */
-
-/**
- * Watchdog Timer Reset Register.
- */
-#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
-#define MXC_F_WDT_RST_WDT_RST                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
-#define MXC_V_WDT_RST_WDT_RST_SEQ0                                             \
-	((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ0                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ0                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
-#define MXC_V_WDT_RST_WDT_RST_SEQ1                                             \
-	((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ1                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ1                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
-
-#endif /* _WDT_REGS_H_ */
diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c
deleted file mode 100644
index d40a8a9d1c..0000000000
--- a/chip/mchp/adc.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/*
- * Conversion on a single channel takes less than 12 ms. Set timeout to
- * 15 ms so that we have a 3-ms margin.
- */
-#define ADC_SINGLE_READ_TIME 15000
-
-struct mutex adc_lock;
-
-/*
- * Volatile should not be needed.
- * ADC ISR only reads task_waiting.
- * Two other non-ISR routines only write task_waiting when
- * interrupt is disabled or before starting ADC.
- */
-static task_id_t task_waiting;
-
-/*
- * Start ADC single-shot conversion.
- * 1. Disable ADC interrupt.
- * 2. Clear sticky hardware status.
- * 3. Start conversion.
- * 4. Enable interrupt.
- * 5. Wait with timeout for ADC ISR to
- *    to set TASK_EVENT_TIMER.
- */
-static int start_single_and_wait(int timeout)
-{
-	int event;
-
-	MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	task_waiting = task_get_current();
-
-	/* clear all R/W1C channel status */
-	MCHP_ADC_STS = 0xffffu;
-	/* clear R/W1C single done status */
-	MCHP_ADC_CTRL |= BIT(7);
-	/* clear GIRQ single status */
-	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	/* make sure all writes are issued before starting conversion */
-	asm volatile ("dsb");
-
-	/* Start conversion */
-	MCHP_ADC_CTRL |= BIT(1);
-
-	MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	/* Wait for interrupt, ISR disables interrupt */
-	event = task_wait_event(timeout);
-	task_waiting = TASK_ID_INVALID;
-	return event != TASK_EVENT_TIMER;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-
-	mutex_lock(&adc_lock);
-
-	MCHP_ADC_SINGLE = 1 << adc->channel;
-
-	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
-		value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			adc->factor_div + adc->shift;
-	else
-		value = ADC_READ_ERROR;
-
-	mutex_unlock(&adc_lock);
-	return value;
-}
-
-int adc_read_all_channels(int *data)
-{
-	int i;
-	int ret = EC_SUCCESS;
-	const struct adc_t *adc;
-
-	mutex_lock(&adc_lock);
-
-	MCHP_ADC_SINGLE = 0;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		MCHP_ADC_SINGLE |= 1 << adc_channels[i].channel;
-
-	if (!start_single_and_wait(ADC_SINGLE_READ_TIME * ADC_CH_COUNT)) {
-		ret = EC_ERROR_TIMEOUT;
-		goto exit_all_channels;
-	}
-
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		adc = adc_channels + i;
-		data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			  adc->factor_div + adc->shift;
-	}
-
-exit_all_channels:
-	mutex_unlock(&adc_lock);
-
-	return ret;
-}
-
-/*
- * Enable GPIO pins.
- * Using MEC17xx direct mode interrupts. Do not
- * set Interrupt Aggregator Block Enable bit
- * for GIRQ containing ADC.
- */
-static void adc_init(void)
-{
-	trace0(0, ADC, 0, "adc_init");
-
-	gpio_config_module(MODULE_ADC, 1);
-
-	/* clear ADC sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC);
-
-	/* Activate ADC module */
-	MCHP_ADC_CTRL |= BIT(0);
-
-	/* Enable interrupt */
-	task_waiting = TASK_ID_INVALID;
-	MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-	task_enable_irq(MCHP_IRQ_ADC_SNGL);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
-
-void adc_interrupt(void)
-{
-	MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	/* clear individual chan conversion status */
-	MCHP_ADC_STS = 0xffffu;
-
-	/* Clear interrupt status bit */
-	MCHP_ADC_CTRL |= BIT(7);
-
-	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
-
-	if (task_waiting != TASK_ID_INVALID)
-		task_wake(task_waiting);
-}
-DECLARE_IRQ(MCHP_IRQ_ADC_SNGL, adc_interrupt, 2);
diff --git a/chip/mchp/adc_chip.h b/chip/mchp/adc_chip.h
deleted file mode 100644
index 0f14d5a459..0000000000
--- a/chip/mchp/adc_chip.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-};
-
-/* List of ADC channels */
-enum chip_adc_channel {
-	CHIP_ADC_CH0 = 0,
-	CHIP_ADC_CH1,
-	CHIP_ADC_CH2,
-	CHIP_ADC_CH3,
-	CHIP_ADC_CH4,
-	CHIP_ADC_CH5,
-	CHIP_ADC_CH6,
-	CHIP_ADC_CH7,
-	CHIP_ADC_COUNT,
-};
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#ifdef CHIP_FAMILY_MEC172X
-/* MEC172x ADC is 12BIT resolution in default */
-#define ADC_READ_MAX 4095
-#else
-#define ADC_READ_MAX 1023
-#endif
-
-/* Just plain id mapping for code readability */
-#define MCHP_ADC_CH(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
deleted file mode 100644
index 155fbf385f..0000000000
--- a/chip/mchp/build.mk
+++ /dev/null
@@ -1,119 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Microchip(MCHP) MEC chip specific files build
-#
-
-# pass verbose build setting to SPI image generation script
-SCRIPTVERBOSE=
-ifeq ($(V),1)
-SCRIPTVERBOSE=--verbose
-endif
-
-# MCHP MEC SoC's have a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# JTAG debug with Keil ARM MDK debugger
-# do not allow GCC dwarf debug extensions
-#CFLAGS_DEBUG_EXTRA=-gdwarf-3 -gstrict-dwarf
-
-LDFLAGS_EXTRA=
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_MEC_GPIO_EC_CMDS)+=gpio_cmds.o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_MCHP_GPSPI)+=gpspi.o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_SPI)+=spi.o qmspi.o
-chip-$(CONFIG_TFDP)+=tfdp.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-
-# location of the scripts and keys used to pack the SPI flash image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Allow SPI size to be overridden by board specific size, default to 512KB
-CHIP_SPI_SIZE_KB?=512
-
-TEST_SPI=
-ifeq ($(CONFIG_MCHP_LFW_DEBUG),y)
-	TEST_SPI=--test_spi
-endif
-
-# Select chip. Default is MEC170X
-PACK_EC=pack_ec.py
-ifeq ($(CHIP_FAMILY),mec152x)
-	PACK_EC=pack_ec_mec152x.py
-endif
-ifeq ($(CHIP_FAMILY),mec172x)
-	PACK_EC=pack_ec_mec172x.py
-endif
-
-# pack_ec.py creates SPI flash image for MEC
-# _rw_size is CONFIG_RW_SIZE
-# Commands to convert $^ to $@.tmp
-cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/${PACK_EC} -o $@.tmp -i $@.tmp1 \
-		--loader_file $(chip-lfw-flat) ${TEST_SPI} \
-		--spi_size ${CHIP_SPI_SIZE_KB} \
-		--image_size $(_rw_size) ${SCRIPTVERBOSE}; rm -f $@.tmp1
-
-chip-lfw = chip/${CHIP}/lfw/ec_lfw
-chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat
-
-# build these specifically for lfw with -lfw suffix
-objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util util_stdlib gpio) \
-		$(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \
-		core/$(CORE)/cpu $(chip-lfw))
-
-# reuse version.o (and its dependencies) from main board
-objs_lfw += $(out)/RW/common/version.o
-
-dirs-y+=chip/$(CHIP)/lfw
-
-# objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-Ichip/mchp/lfw -DLFW=$(EMPTY)
-# Remove the lto flag for the loader.  It actually causes it to bloat in size.
-ifeq ($(CONFIG_LTO),y)
-$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
-endif
-$(out)/RW/%-lfw.o: %.c
-	$(call quiet,c_to_o,CC     )
-
-# let lfw's elf link only with selected objects
-ifeq ($(CHIP_FAMILY),mec172x)
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %_416kb.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(chip-lfw-flat)
-else
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(chip-lfw-flat)
-endif
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
deleted file mode 100644
index 362025ee1c..0000000000
--- a/chip/mchp/clock.c
+++ /dev/null
@@ -1,780 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "tfdp_chip.h"
-#include "vboot_hash.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-#define HTIMER_DIV_1_US_MAX	(1998848)
-#define HTIMER_DIV_1_1SEC	(0x8012)
-
-/* Recovery time for HvySlp2 is 0 us */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
-
-#define SET_HTIMER_DELAY_USEC           200
-
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t total_idle_dsleep_time_us;
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-static uint32_t pcr_slp_en[MCHP_PCR_SLP_RST_REG_MAX];
-static uint32_t pcr_clk_req[MCHP_PCR_SLP_RST_REG_MAX];
-static uint32_t ecia_result[MCHP_INT_GIRQ_NUM];
-#endif
-
-/*
- * Fixed amount of time to keep the console in use flag true after
- * boot in order to give a permanent window in which the heavy sleep
- * mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq = 48000000;
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-/*
- * MEC170x and MEC152x have the same 32 KHz clock enable hardware.
- * MEC172x 32 KHz clock configuration is different and includes
- * hardware to check the crystal before switching and to monitor
- * the 32 KHz input if desired.
- */
-#ifdef CHIP_FAMILY_MEC172X
-/* 32 KHz crystal connected in parallel */
-static inline void config_32k_src_crystal(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN
-			| MCHP_VBAT_CSS_SRC_XTAL;
-}
-
-/* 32 KHz source is 32KHZ_IN pin which must be configured */
-static inline void config_32k_src_se_input(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN
-				| MCHP_VBAT_CSS_SRC_SWPS;
-}
-
-static inline void config_32k_src_sil_osc(void)
-{
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN;
-}
-
-#else
-static void config_32k_src_crystal(void)
-{
-	MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL;
-}
-
-/* 32 KHz source is 32KHZ_IN pin which must be configured */
-static inline void config_32k_src_se_input(void)
-{
-	MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT;
-}
-
-static inline void config_32k_src_sil_osc(void)
-{
-	MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL);
-}
-#endif
-
-/** clock_init
- * @note
- * MCHP MEC implements 4 control bits in the VBAT Clock Enable register.
- * It also implements an internal silicon 32KHz +/- 2% oscillator powered
- * by VBAT.
- * b[3] = XOSEL 0=parallel, 1=single-ended
- * b[2] = 32KHZ_SOURCE specifies source of always-on clock domain
- *        0=internal silicon oscillator
- *        1=crystal XOSEL pin(s)
- * b[1] = EXT_32K use always-on clock domain or external 32KHZ_IN pin
- *        0=32K source is always-on clock domain
- *        1=32K source is 32KHZ_IN pin (GPIO 0165)
- * b[0] = 32K_SUPPRESS
- *        0=32K clock domain stays enabled if VTR is off. Powered by VBAT
- *        1=32K clock domain is disabled if VTR is off.
- * Set b[3] based on CONFIG_CLOCK_CRYSTAL
- * Set b[2:0] = 100b
- *    b[0]=0 32K clock domain always on (requires VBAT if VTR is off)
- *    b[1]=0 32K source is the 32K clock domain NOT the 32KHZ_IN pin
- *    b[2]=1 If activity detected on crystal pins switch 32K input from
- *           internal silicon oscillator to XOSEL pin(s) based on b[3].
- */
-void clock_init(void)
-{
-	if (IS_ENABLED(CONFIG_CLOCK_SRC_EXTERNAL))
-		if (IS_ENABLED(CONFIG_CLOCK_CRYSTAL))
-			config_32k_src_crystal();
-		else
-			/* 32KHz 50% duty waveform on 32KHZ_IN pin */
-			config_32k_src_se_input();
-	else
-		/* Use internal silicon 32KHz OSC */
-		config_32k_src_sil_osc();
-
-	/* Wait for PLL to lock onto 32KHz source (OSC_LOCK == 1) */
-	while (!(MCHP_PCR_CHIP_OSC_ID & 0x100))
-		;
-}
-
-/**
- * Speed through boot + vboot hash calculation, dropping our processor
- * clock only after vboot hashing is completed.
- */
-static void clock_turbo_disable(void);
-DECLARE_DEFERRED(clock_turbo_disable);
-
-static void clock_turbo_disable(void)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress())
-		hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
-	else
-#endif
-		/* Use 12 MHz processor clock for power savings */
-		MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_12MHZ;
-}
-DECLARE_HOOK(HOOK_INIT,
-		clock_turbo_disable,
-		HOOK_PRIO_INIT_VBOOT_HASH + 1);
-
-/**
- * initialization of Hibernation timer 0
- * Clear PCR sleep enable.
- * GIRQ=21, aggregator bit = 1, Direct NVIC = 112
- * NVIC direct connect interrupts are used for all peripherals
- * (exception GPIO's) then the MCHP_INT_BLK_EN GIRQ bit should not be
- * set.
- */
-void htimer_init(void)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_HTMR0);
-	MCHP_HTIMER_PRELOAD(0) = 0; /* disable at beginning */
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
-
-	task_enable_irq(MCHP_IRQ_HTIMER0);
-}
-
-/**
- * Use hibernate module to set up an htimer interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before htimer interrupt
- * @param microseconds Number of microseconds before htimer interrupt
- * @note hibernation timer input clock is 32.768KHz.
- * Control register bit[0] selects the divider.
- * 0 is divide by 1 for 30.5 us per LSB for a maximum of
- *	65535 * 30.5 us = 1998817.5 us or 32.786 counts per second
- * 1 is divide by 4096 for 0.125 s per LSB for a maximum of ~2 hours.
- *	65535 * 0.125 s ~ 8192 s = 2.27 hours
- */
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds)
-{
-	uint32_t hcnt, ns;
-	uint8_t hctrl;
-
-	MCHP_HTIMER_PRELOAD(0) = 0; /* disable */
-
-	if (microseconds > 1000000ul) {
-		ns = (microseconds / 1000000ul);
-		microseconds %= 1000000ul;
-		if ((0xfffffffful - seconds) > ns)
-			seconds += ns;
-		else
-			seconds = 0xfffffffful;
-	}
-
-	if (seconds > 1) {
-		hcnt = (seconds << 3);	/* divide by 0.125 */
-		if (hcnt > 0xfffful)
-			hcnt = 0xfffful;
-		hctrl = 1;
-	} else {
-		/*
-		 * approximate(~2% error) as seconds is 0 or 1
-		 * seconds / 30.5e-6 + microseconds / 30.5
-		 */
-		hcnt = (seconds << 15) + (microseconds >> 5) +
-			(microseconds >> 10);
-		hctrl = 0;
-	}
-
-	MCHP_HTIMER_CONTROL(0) = hctrl;
-	MCHP_HTIMER_PRELOAD(0) = hcnt;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-/**
- * return time slept in micro-seconds
- */
-static timestamp_t system_get_htimer(void)
-{
-	uint16_t count;
-	timestamp_t time;
-
-	count =  MCHP_HTIMER_COUNT(0);
-
-
-	if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */
-		/* 0.125 sec per count */
-		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2) us per count */
-		time.le.lo = (uint32_t)(count * 61 / 2);
-
-	time.le.hi = 0;
-
-	return time;  /* in uSec */
-}
-
-/**
- * Disable and clear hibernation timer interrupt
- */
-static void system_reset_htimer_alarm(void)
-{
-	MCHP_HTIMER_PRELOAD(0) = 0;
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
-}
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-static void print_pcr_regs(void)
-{
-	int i;
-
-	trace0(0, MEC, 0, "Current PCR registers");
-	for (i = 0; i < 5; i++) {
-		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X",
-			i, MCHP_PCR_SLP_EN(i));
-		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X",
-			i, MCHP_PCR_CLK_REQ(i));
-	}
-}
-
-static void print_ecia_regs(void)
-{
-	int i;
-
-	trace0(0, MEC, 0, "Current GIRQn.Result registers");
-	for (i = MCHP_INT_GIRQ_FIRST;
-			i <= MCHP_INT_GIRQ_LAST; i++)
-		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X",
-			i, MCHP_INT_RESULT(i));
-}
-
-static void save_regs(void)
-{
-	int i;
-
-	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		pcr_slp_en[i] = MCHP_PCR_SLP_EN(i);
-		pcr_clk_req[i] = MCHP_PCR_CLK_REQ(i);
-	}
-
-	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		ecia_result[i] =
-			MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
-}
-
-static void print_saved_regs(void)
-{
-	int i;
-
-	trace0(0, BRD, 0, "Before sleep saved registers");
-	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X",
-			i, pcr_slp_en[i]);
-		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X",
-			i, pcr_clk_req[i]);
-	}
-
-	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X",
-			(i+MCHP_INT_GIRQ_FIRST), ecia_result[i]);
-}
-#else
-static __maybe_unused void print_pcr_regs(void) {}
-static __maybe_unused void print_ecia_regs(void) {}
-static __maybe_unused void save_regs(void) {}
-static __maybe_unused void print_saved_regs(void) {}
-#endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */
-
-/**
- * This is MCHP specific and equivalent to ARM Cortex's
- * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
- * MCHP has new SLP_ALL feature.
- * When SLP_ALL is enabled and HW sees sleep entry trigger from CPU.
- * 1. HW saves PCR.SLP_EN registers
- * 2. HW sets all PCR.SLP_EN bits to 1.
- * 3. System sleeps
- * 4. wake event wakes system
- * 5. HW restores original values of all PCR.SLP_EN registers
- * NOTE1: Current RTOS core (Cortex-M4) does not use SysTick timer.
- * We can leave code to disable it but do not re-enable on wake.
- * NOTE2: Some peripherals will not sleep until outstanding transactions
- * are complete: I2C, DMA, GPSPI, QMSPI, etc.
- * NOTE3: Security blocks do not fully implement HW sleep therefore their
- * sleep enables must be manually set/restored.
- *
- */
-static void prepare_for_deep_sleep(void)
-{
-	/* sysTick timer */
-	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
-	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
-
-	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
-
-	/* Enable assertion of DeepSleep signals
-	 * from the core when core enters sleep.
-	 */
-	CPU_SCB_SYSCTRL |= BIT(2);
-
-	/* Stop timers */
-	MCHP_TMR32_CTL(0) &= ~1;
-	MCHP_TMR32_CTL(1) &= ~1;
-#ifdef CONFIG_WATCHDOG_HELP
-	MCHP_TMR16_CTL(0) &= ~1;
-	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-#endif
-	MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-
-#ifdef CONFIG_WATCHDOG
-	/* Stop watchdog */
-	MCHP_WDG_CTL &= ~1;
-#endif
-
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-#else
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-#endif
-
-#ifdef CONFIG_ADC
-	/*
-	 * Clear ADC activate bit. If a conversion is in progress the
-	 * ADC block will not enter low power until the conversion is
-	 * complete.
-	 */
-	MCHP_ADC_CTRL &= ~1;
-#endif
-
-	/* stop Port80 capture timer */
-#ifndef CHIP_FAMILY_MEC172X
-	MCHP_P80_ACTIVATE(0) = 0;
-#endif
-
-	/*
-	 * Clear SLP_EN bit(s) for wake sources.
-	 * Currently only Hibernation timer 0.
-	 * GPIO pins can always wake.
-	 */
-	MCHP_PCR_SLP_EN3 &= ~(MCHP_PCR_SLP_EN3_HTMR0);
-
-#ifdef CONFIG_PWM
-	pwm_keep_awake(); /* clear sleep enables of active PWM's */
-#else
-	/* Disable 100 Khz clock */
-	MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
-#endif
-
-#ifdef CONFIG_CHIPSET_DEBUG
-	/* Disable JTAG and preserve mode */
-	MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE);
-#endif
-
-	/* call board level */
-#ifdef CONFIG_BOARD_DEEP_SLEEP
-	board_prepare_for_deep_sleep();
-#endif
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-	save_regs();
-#endif
-}
-
-static void resume_from_deep_sleep(void)
-{
-	MCHP_PCR_SYS_SLP_CTL = 0x00;  /* default */
-
-	/* Disable assertion of DeepSleep signal when core executes WFI */
-	CPU_SCB_SYSCTRL &= ~BIT(2);
-
-#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
-	print_saved_regs();
-	print_pcr_regs();
-	print_ecia_regs();
-#endif
-
-#ifdef CONFIG_CHIPSET_DEBUG
-	MCHP_EC_JTAG_EN |= (MCHP_JTAG_ENABLE);
-#endif
-
-	MCHP_PCR_SLOW_CLK_CTL |= 0x1e0;
-
-	/* call board level */
-#ifdef CONFIG_BOARD_DEEP_SLEEP
-	board_resume_from_deep_sleep();
-#endif
-	/*
-	 * re-enable hibernation timer 0 PCR.SLP_EN to
-	 * reduce power.
-	 */
-	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	#ifdef CONFIG_POWER_S0IX
-	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	#else
-	MCHP_ESPI_ACTIVATE |= 1;
-	#endif
-#else
-	#ifdef CONFIG_POWER_S0IX
-	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	#else
-	MCHP_LPC_ACT |= 1;
-	#endif
-#endif
-
-	/* re-enable Port 80 capture */
-#ifndef CHIP_FAMILY_MEC172X
-	MCHP_P80_ACTIVATE(0) = 1;
-#endif
-
-#ifdef CONFIG_ADC
-	MCHP_ADC_CTRL |= 1;
-#endif
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(0) |= 1;
-	MCHP_TMR32_CTL(1) |= 1;
-	MCHP_TMR16_CTL(0) |= 1;
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-
-	/* Enable watchdog */
-#ifdef CONFIG_WATCHDOG
-#ifdef CONFIG_CHIPSET_DEBUG
-	/* enable WDG stall on active JTAG and do not start */
-	MCHP_WDG_CTL = BIT(4);
-#else
-	MCHP_WDG_CTL |= 1;
-#endif
-#endif
-}
-
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-/**
- * Low power idle task. Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
-{
-	timestamp_t t0;
-	timestamp_t t1;
-	timestamp_t ht_t1;
-	uint32_t next_delay;
-	uint32_t max_sleep_time;
-	int time_for_dsleep;
-	int uart_ready_for_deepsleep;
-
-	htimer_init(); /* hibernation timer initialize */
-
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val +
-			CONSOLE_IN_USE_ON_BOOT_TIME;
-
-
-	/*
-	 * Print when the idle task starts. This is the lowest priority
-	 * task, so this only starts once all other tasks have gotten a
-	 * chance to do their task initializations and have gone to sleep.
-	 */
-	CPRINTS("MEC low power idle task started");
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-
-		t0 = get_time();  /* uSec */
-
-		/* __hw_clock_event_get() is next programmed timer event */
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		time_for_dsleep = next_delay >
-			(HEAVY_SLEEP_RECOVER_TIME_USEC +
-			SET_HTIMER_DELAY_USEC);
-
-		max_sleep_time = next_delay -
-				HEAVY_SLEEP_RECOVER_TIME_USEC;
-
-		/* check if there enough time for deep sleep */
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-			/*
-			 * Check if the console use has expired and
-			 * console sleep is masked by GPIO(UART-RX)
-			 * interrupt.
-			 */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-				t0.val > console_expire_time.val) {
-				/* allow console to sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if
-				 * heavy sleep is allowed to give time
-				 * for sleep mask to be updated.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("MEC Disable console "
-						"in deep sleep");
-			}
-
-
-			/* UART is not being used  */
-			uart_ready_for_deepsleep =
-				LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-					!uart_tx_in_progress() &&
-					uart_buffer_empty();
-
-			/*
-			 * Since MCHP's heavy sleep mode requires all
-			 * blocks to be sleep capable, UART/console
-			 * readiness is final decision factor of
-			 * heavy sleep of EC.
-			 */
-			if (uart_ready_for_deepsleep) {
-
-				idle_dsleep_cnt++;
-
-				/*
-				 * configure UART Rx as GPIO wakeup
-				 * interrupt source
-				 */
-				uart_enter_dsleep();
-
-				/* MCHP specific deep-sleep mode */
-				prepare_for_deep_sleep();
-
-				/*
-				 * 'max_sleep_time' value should be big
-				 * enough so that hibernation timer's
-				 * interrupt triggers only after 'wfi'
-				 * completes its execution.
-				 */
-				max_sleep_time -=
-					(get_time().le.lo - t0.le.lo);
-
-				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0,
-						max_sleep_time);
-
-				/* set sleep all just before WFI */
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_HEAVY;
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_ALL;
-
-			} else {
-				idle_sleep_cnt++;
-			}
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("dsb");
-			asm("wfi");
-			asm("isb");
-			asm("nop");
-
-			if (uart_ready_for_deepsleep) {
-
-				resume_from_deep_sleep();
-
-				/*
-				 * Fast forward timer according to htimer
-				 * counter:
-				 * Since all blocks including timers
-				 * will be in sleep mode, timers stops
-				 * except hibernate timer.
-				 * And system schedule timer should be
-				 * corrected after wakeup by either
-				 * hibernate timer or GPIO_UART_RX
-				 * interrupt.
-				 */
-				ht_t1 = system_get_htimer();
-
-				/* disable/clear htimer wakeup interrupt */
-				system_reset_htimer_alarm();
-
-				t1.val = t0.val +
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
-
-				force_time(t1);
-
-				/* re-enable UART */
-				uart_exit_dsleep();
-
-				/* Record time spent in deep sleep. */
-				total_idle_dsleep_time_us +=
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
-			}
-
-		} else { /* CPU 'Sleep' mode */
-
-			idle_sleep_cnt++;
-
-			asm("wfi");
-
-		}
-
-		interrupt_enable();
-	} /* while(1) */
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n",
-			idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n",
-			idle_dsleep_cnt);
-
-	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-			total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n",
-			ts.val);
-
-	if (IS_ENABLED(CONFIG_MCHP_DEEP_SLP_DEBUG))
-		print_pcr_regs();	/* debug */
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* defined(CONFIG_CMD_IDLE_STATS) */
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use heavy sleep mode or
-			 * allow it to use the heavy sleep mode.
-			 */
-			if (v)  /* 'on' */
-				disable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep NOT to enter heavy sleep mode.\nUse 'off' to "
-		"allow deep sleep to use heavy sleep whenever conditions "
-		"allow.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleep mask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h
deleted file mode 100644
index 2e7de60358..0000000000
--- a/chip/mchp/clock_chip.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Microchip MEC1701 specific module for Chrome EC */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include <stdint.h>
-
-void htimer_init(void);
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds);
-
-#endif /* __CROS_EC_I2C_CLOCK_H */
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
deleted file mode 100644
index cf7ead512a..0000000000
--- a/chip/mchp/config_chip.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* Number of IRQ vectors on the NVIC */
-#ifdef CHIP_FAMILY_MEC152X
-#define CONFIG_IRQ_COUNT 174
-#elif defined(CHIP_FAMILY_MEC170X)
-#define CONFIG_IRQ_COUNT 157
-#elif defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_IRQ_COUNT 181
-#endif
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	1024
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Enable chip_pre_init called from main
- * Used for configuring peripheral block
- * sleep enables.
- */
-#define CONFIG_CHIP_PRE_INIT
-
-/*
- * MCHP EC's have I2C controllers and multiple I2C ports. Any port may be
- * mapped to any controller at run time. Enable multi-port controller feature.
- * Board level configuration determines how many controllers/ports are used
- * and the mapping of port(s) to controller(s). NOTE: Some MCHP packages
- * may not implement all I2C ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-
-/*
- * MCHP I2C controllers also act as I2C peripherals listening for their
- * peripheral address. Each controller has two programmable peripheral
- * addresses. Define fake peripheral addresses that aren't used by
- * peripherals on the board.
- */
-#define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C1_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C2_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C3_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C4_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C5_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C6_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C7_SLAVE_ADDRS	0xE3E1
-
-/************************************************************************/
-/* Memory mapping */
-
-/*
- * MEC170x-H and MEC152x-H have a total of 256KB SRAM.
- *   CODE at 0xE0000 - 0x117FFF, DATA at 0x118000 - 0x11FFFF
- * MEC172x-N has a total of 416KB SRAM: 352KB CODE 64KB DATA
- *   CODE at 0xC0000 - 0x117FFF, DATA at 0x118000 - 0x127FFF
- *   Customer data preserved across reset is 1KB at 0x12_7400.
- *   Set top of SRAM to 0x12_7800.  We lose the top 2KB.
- * MCHP MEC can fetch code from data or data from code.
- */
-
-/************************************************************************/
-/* Define our RAM layout. */
-
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MEC_SRAM_BASE_START	0x000C0000
-#define CONFIG_MEC_SRAM_BASE_END	(0x00128000 - (2 * 1024))
-#else
-#define CONFIG_MEC_SRAM_BASE_START	0x000E0000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#endif
-
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
-/* 64k Data RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00010000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
-
-/* System stack size */
-/* was 1024, temporarily expanded to 2048 for debug */
-#define CONFIG_STACK_SIZE		2048
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
-
-#define CHARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define HOOKS_TASK_STACK_SIZE		1024	/* 640 */
-#define CONSOLE_TASK_STACK_SIZE		1024	/* 640 */
-#define HOST_CMD_TASK_STACK_SIZE	1024	/* 640 */
-
-/*
- * TODO: Large stack consumption
- * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
- */
-/* original = 800, if stack exceptions expand to 1024 for debug */
-#define PD_TASK_STACK_SIZE		2048
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			672
-
-/************************************************************************/
-/* Define our flash layout. */
-
-/*
- * MEC1521H loads firmware using QMSPI controller
- * CONFIG_SPI_FLASH_PORT is the index into
- * spi_devices[] in board.c
- */
-#define CONFIG_SPI_FLASH_PORT 0
-#define CONFIG_SPI_FLASH
-
-/*
- * MEC1727 chip has integrated SPI flash with 512KB size
- */
-#if (defined(CHIP_VARIANT_MEC1727SZ) || defined(CHIP_VARIANT_MEC1727LJ))
-/* Total size of writable flash */
-#define CONFIG_FLASH_SIZE_BYTES 524288
-#endif
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
-
-/* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
-
-/* Program memory base address */
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000C0000
-#else
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000E0000
-#endif
-
-/*
- * Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
- * by hardware, it will add several system clock cycles delay between CS
- * deassertion to CS assertion at the start of the next transaction, this
- * guarantees SPI back to back transactions, so 1ms delay can be removed
- * to optimze timing. MEC172x chip supports this hardware feature.
- */
-#if defined(CHIP_FAMILY_MEC172X)
-#undef CONFIG_SPI_FLASH_READ_WAIT_MS
-#define CONFIG_SPI_FLASH_READ_WAIT_MS 0
-#endif
-
-#include "config_flash_layout.h"
-
-/************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_DMA
-#define CONFIG_HOSTCMD_X86
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-/*
- * Enable configuration after ESPI_RESET# de-asserts
- */
-#undef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
-
-/*
- * Enable CPRINT in chip eSPI module
- * Define at board level.
- */
-#undef CONFIG_MCHP_ESPI_DEBUG
-
-/*
- * Enable EC UART commands in eSPI module useful for debugging.
- */
-#undef CONFIG_MCHP_ESPI_EC_CMD
-
-/*
- * Enable CPRINT debug messages in LPC module
- */
-#undef CONFIG_MCHP_DEBUG_LPC
-
-/*
- * Define this to use MEC1701 ROM SPI read API
- * in little firmware module instead of SPI code
- * from this module
- */
-#undef CONFIG_CHIP_LFW_USE_ROM_SPI
-
-/*
- * Use DMA when transmitting commands & data
- * with GPSPI controllers.
- */
-#if defined(CHIP_FAMILY_MEC170X) || defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MCHP_GPSPI_TX_DMA
-#endif
-
-/*
- * Use DMA when transmitting command & data of length
- * greater than QMSPI TX FIFO size.
- */
-#define CONFIG_MCHP_QMSPI_TX_DMA
-
-/*
- * Board level gpio.inc is using MCHP data sheet GPIO pin
- * numbers which are octal.
- * MCHP has 6 banks/ports each containing 32 GPIO's.
- * Each bank/port is connected to a GIRQ.
- * Port numbering:
- * GPIO_015 = 13 decimal. Port = 13/32 = 0, bit = 13 % 32 = 13
- * GPIO_0123 = 83 decimal. Port 83/32 = 2, bit = 83 % 32 = 19
- * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
- * You must use octal GPIO numbers in PIN(gpio_num) macro in
- * gpio.inc files.
- * Example: GPIO 211 in documentation 0211 = 137 = 0x89
- * GPIO(PCH_SLP_S0_L, PIN(0211), GPIO_INPUT | GPIO_PULL_DOWN)
- * OR
- * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
- */
-#define GPIO_BANK(index) ((index) >> 5)
-#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
-
-#define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#ifndef __ASSEMBLER__
-
-
-#endif /* #ifndef __ASSEMBLER__ */
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h
deleted file mode 100644
index d423ac0238..0000000000
--- a/chip/mchp/config_flash_layout.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * mec17xx flash layout:
- * - Non memory-mapped, external SPI.
- * - RW image at the beginning of writable region.
- * - Bootloader at the beginning of protected region, followed by RO image.
- * - Loader + (RO | RW) loaded into program memory.
- */
-
-/* Non-memmory mapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#define CONFIG_SPI_FLASH
-
-/*
- * MEC170x/MEC152x BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04.
- * One valid TAG must be present.
- * TAG's point to a Header which must be located on a 256 byte
- * boundary anywhere in the flash (24-bit addressing).
- * Locate BootROM load Header + LFW + EC_RO at start of second
- * 4KB sector (offset 0x1000).
- * Locate BootROM load Header + EC_RW at start of second half of
- * SPI flash.
- * LFW size is 4KB
- * EC_RO and EC_RW padded sizes from the build are 188KB each.
- * Storage size is 1/2 flash size.
- */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF	0
-/* Lower 256KB of flash is protected region */
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-/* Writable storage for EC_RW starts at 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
-/* Writeable storage is 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-
-
-/* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0x1000
-
-/* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-/*
- * Write protect LFW + EC_RO
- */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * RO / RW images follow the loader in program memory. Either RO or RW
- * image will be loaded -- both cannot be loaded at the same time.
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-/*
- * Total SRAM and the amount allocated for data are specified
- * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h
- * The little firmware (lfw) loader is resident in first 4KB of Code SRAM.
- * EC_RO/RW size = Total SRAM - Data SRAM - LFW size.
- * !!! EC_RO/RW size MUST be a multiple of flash erase block size.
- * defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h
- * and must be located on a erase block boundary. !!!
- */
-#if (CONFIG_MEC_SRAM_SIZE > CONFIG_EC_PROTECTED_STORAGE_SIZE)
-#define CONFIG_RO_SIZE			(CONFIG_EC_PROTECTED_STORAGE_SIZE - \
-					CONFIG_LOADER_SIZE - 0x2000)
-#else
-#define CONFIG_RO_SIZE			(CONFIG_MEC_SRAM_SIZE - \
-					CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
-#endif
-
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-/*
- * NOTE: CONFIG_RW_SIZE is passed to the SPI image generation script by
- * chip build.mk
- * LFW requires CONFIG_RW_SIZE is equal to CONFIG_RO_SIZE !!!
- */
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/*
- * WP region consists of first half of SPI containing TAGs at beginning
- * of SPI flash and header + binary(LFW+EC_RO) an offset aligned on
- * a 256 byte boundary.
- * NOTE: Changing CONFIG_BOOT_HEADER_STORAGE_OFF requires changing
- * parameter --payload_offset parameter in build.mk passed to the
- * python image builder.
- * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device.
- * We only use first TAG pointing to LFW + EC_RO.
- * MEC170x Header size is 128 bytes.
- * MEC152x Header size is 320 bytes.
- * Firmware binary is located immediately after the header.
- * Second half of SPI flash contains:
- * Header(128/320 bytes) + EC_RW
- * EC flash erase/write commands check alignment base on
- * CONFIG_FLASH_ERASE_SIZE defined in config_chip.h
- * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or
- * greater aligned boundaries.
- */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0x1000
-#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF	0
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0xc0
-#elif defined(CHIP_FAMILY_MEC152X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x140
-#elif defined(CHIP_FAMILY_MEC170X)
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x80
-#else
-#error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid"
-#endif
-#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE	0
-
-/* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/*
- * RW image starts at offset 0 of second half of SPI.
- * RW Header not needed.
- */
-#define CONFIG_RW_STORAGE_OFF		(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
-
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c
deleted file mode 100644
index 982dfa8122..0000000000
--- a/chip/mchp/dma.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	dma_chan_t *pd = NULL;
-
-	if (channel < MCHP_DMAC_COUNT) {
-		pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS +
-				(channel << MCHP_DMA_CH_OFS_BITPOS));
-	}
-
-	return pd;
-}
-
-void dma_disable(enum dma_channel channel)
-{
-	if (channel < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN)
-			MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN);
-
-		if (MCHP_DMA_CH_ACT(channel)	& MCHP_DMA_ACT_EN)
-			MCHP_DMA_CH_ACT(channel) = 0;
-	}
-}
-
-void dma_disable_all(void)
-{
-	uint16_t ch;
-	uint32_t unused = 0;
-
-	for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) {
-		/* Abort any current transfer. */
-		MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_ABORT;
-		/* Disable the channel. */
-		MCHP_DMA_CH_CTRL(ch) &= ~(MCHP_DMA_RUN);
-		MCHP_DMA_CH_ACT(ch) = 0;
-	}
-
-	/* Soft-reset the block. */
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST;
-	unused += MCHP_DMA_MAIN_CTRL;
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT;
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan	Channel to read
- * @param count	Number of bytes to transfer
- * @param periph Pointer to peripheral data register
- * @param memory Pointer to memory address for receive/transmit
- * @param flags	DMA flags for the control register, normally:
- *		MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV for tx
- *		MCHP_DMA_INC_MEM for rx
- *		Plus transfer unit length(1, 2, or 4) in bits[22:20]
- * @note MCHP DMA does not require address aliasing. Because count
- * is the number of bytes to transfer memory start - memory end = count.
- */
-static void prepare_channel(enum dma_channel ch, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-
-		MCHP_DMA_CH_CTRL(ch) = 0;
-		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
-
-		MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)periph;
-
-		MCHP_DMA_CH_CTRL(ch) = flags;
-		MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN;
-	}
-}
-
-void dma_go(dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the
-	 *  latest data.
-	 */
-	asm volatile("dsb;");
-
-	if (chan != NULL)
-		chan->ctrl |= MCHP_DMA_RUN;
-}
-
-void dma_go_chan(enum dma_channel ch)
-{
-	asm volatile("dsb;");
-	if (ch < MCHP_DMAC_COUNT)
-		MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	if (option != NULL)
-		/*
-		 * Cast away const for memory pointer; this is ok because
-		 * we know we're preparing the channel for transmit.
-		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			option->flags);
-}
-
-void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units)
-{
-	uint32_t nflags;
-
-	if (option != NULL) {
-		nflags = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK);
-		nflags |= MCHP_DMA_XFER_SIZE(dma_xfr_units & 0x07);
-		/*
-		 * Cast away const for memory pointer; this is ok because
-		 * we know we're preparing the channel for transmit.
-		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			nflags);
-	}
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	if (option != NULL) {
-		prepare_channel(option->channel, count, option->periph,
-				memory,
-				MCHP_DMA_INC_MEM |
-				MCHP_DMA_DEV(option->channel) |
-				option->flags);
-		dma_go_chan(option->channel);
-	}
-}
-
-/*
- * Configure and start DMA channel for read from device and write to
- * memory. Allow caller to override DMA transfer unit length.
- */
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory)
-{
-	uint32_t ch, ctrl;
-
-	if (option != NULL) {
-		ch = option->channel;
-		if (ch < MCHP_DMAC_COUNT) {
-
-			MCHP_DMA_CH_CTRL(ch) = 0;
-			MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory +
-					count;
-
-			MCHP_DMA_CH_DEV_ADDR(ch) =
-					(uint32_t)option->periph;
-
-			ctrl = option->flags &
-					~(MCHP_DMA_XFER_SIZE_MASK);
-			ctrl |= MCHP_DMA_INC_MEM;
-			ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen);
-			ctrl |= MCHP_DMA_DEV(option->channel);
-			MCHP_DMA_CH_CTRL(ch) = ctrl;
-			MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN;
-		}
-
-		dma_go_chan(option->channel);
-	}
-}
-
-/*
- * Return the number of bytes transferred.
- * The number of bytes transferred can be easily determined
- * from the difference in DMA memory start address register
- * and memory end address register. No need to look at DMA
- * transfer size field because the hardware increments memory
- * start address by unit size on each unit transferred.
- * Why is a signed integer being used for a count value?
- */
-int dma_bytes_done(dma_chan_t *chan, int orig_count)
-{
-	int bcnt;
-
-	if (chan == NULL)
-		return 0;
-
-	bcnt = (int)chan->mem_end;
-	bcnt -= (int)chan->mem_start;
-	bcnt = orig_count - bcnt;
-
-	return bcnt;
-}
-
-bool dma_is_enabled(dma_chan_t *chan)
-{
-	return (chan->ctrl & MCHP_DMA_RUN);
-}
-
-int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count)
-{
-	uint32_t cnt;
-
-	cnt = 0;
-	if (ch < MCHP_DMAC_COUNT)
-		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN)
-			cnt = (uint32_t)orig_count -
-					(MCHP_DMA_CH_MEM_END(ch) -
-					 MCHP_DMA_CH_MEM_START(ch));
-
-	return (int)cnt;
-}
-
-/*
- * Initialize DMA block.
- * Clear PCR DMA sleep enable.
- * Soft-Reset block should clear after one clock but read-back to
- * be safe.
- * Set block activate bit after reset.
- */
-void dma_init(void)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_DMA);
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST;
-	MCHP_DMA_MAIN_CTRL;
-	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT;
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	timestamp_t deadline;
-
-	if (channel < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_ACT(channel) == 0)
-			return EC_SUCCESS;
-
-		deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-
-		while (!(MCHP_DMA_CH_ISTS(channel) &
-			 MCHP_DMA_STS_DONE)) {
-
-			if (deadline.val <= get_time().val)
-				return EC_ERROR_TIMEOUT;
-
-			udelay(DMA_POLLING_INTERVAL_US);
-		}
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-/*
- * Clear all interrupt status in specified DMA channel
- */
-void dma_clear_isr(enum dma_channel channel)
-{
-	if (channel < MCHP_DMAC_COUNT)
-		MCHP_DMA_CH_ISTS(channel) = 0x0f;
-}
-
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf;
-		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)membuf + nb;
-		MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)pdev;
-	}
-}
-
-/*
- * ch = zero based DMA channel number
- * unit_len = DMA unit size 1, 2 or 4 bytes
- * flags
- *   b[0] = direction, 0=device_to_memory, 1=memory_to_device
- *   b[1] = 1 increment memory address
- *   b[2] = 1 increment device address
- *   b[3] = disable HW flow control
- */
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags)
-{
-	uint32_t ctrl;
-
-	if (ch < MCHP_DMAC_COUNT) {
-		ctrl = MCHP_DMA_XFER_SIZE(unit_len & 0x07);
-		ctrl += MCHP_DMA_DEV(dev_id & MCHP_DMA_DEV_MASK0);
-		if (flags & 0x01)
-			ctrl |= MCHP_DMA_TO_DEV;
-		if (flags & 0x02)
-			ctrl |= MCHP_DMA_INC_MEM;
-		if (flags & 0x04)
-			ctrl |= MCHP_DMA_INC_DEV;
-		if (flags & 0x08)
-			ctrl |= MCHP_DMA_DIS_HW_FLOW;
-		MCHP_DMA_CH_CTRL(ch) = ctrl;
-	}
-}
-
-void dma_clr_chan(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		MCHP_DMA_CH_ACT(ch) = 0;
-		MCHP_DMA_CH_CTRL(ch) = 0;
-		MCHP_DMA_CH_IEN(ch) = 0;
-		MCHP_DMA_CH_ISTS(ch) = 0xff;
-		MCHP_DMA_CH_FSM_RO(ch) = MCHP_DMA_CH_ISTS(ch);
-		MCHP_DMA_CH_ACT(ch) = 1;
-	}
-}
-
-void dma_run(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT) {
-		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_DIS_HW_FLOW)
-			MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_SW_GO;
-		else
-			MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN;
-	}
-}
-
-/*
- * Check if DMA channel is done or stopped on error
- * Returns 0 not done or stopped on error
- * Returns non-zero if done or stopped.
- * Caller should check bit pattern for specific bit,
- * done, flow control error, and bus error.
- */
-uint32_t dma_is_done_chan(enum dma_channel ch)
-{
-	if (ch < MCHP_DMAC_COUNT)
-		return (uint32_t)(MCHP_DMA_CH_ISTS(ch) & 0x07);
-
-	return 0;
-}
-
-/*
- * Use DMA Channel 0 CRC32 ALU to compute CRC32 of data.
- * Hardware implements IEEE 802.3 CRC32.
- * IEEE 802.3 CRC32 initial value = 0xffffffff.
- * Data must be aligned >= 4-bytes and number of bytes must
- * be a multiple of 4.
- */
-int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
-{
-	if ((mstart == NULL) || (nbytes == 0))
-		return EC_ERROR_INVAL;
-
-	if ((((uint32_t)mstart | nbytes) & 0x03) != 0)
-		return EC_ERROR_INVAL;
-
-	MCHP_DMA_CH_ACT(0) = 0;
-	MCHP_DMA_CH_CTRL(0) = 0;
-	MCHP_DMA_CH_IEN(0) = 0;
-	MCHP_DMA_CH_ISTS(0) = 0xff;
-	MCHP_DMA_CH0_CRC32_EN = 1;
-	MCHP_DMA_CH0_CRC32_DATA	= 0xfffffffful;
-	/* program device address to point to read-only register */
-	MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c);
-	MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart;
-	MCHP_DMA_CH_MEM_END(0) = (uint32_t)mstart + nbytes;
-	if (ien != 0)
-		MCHP_DMA_CH_IEN(0) = 0x07;
-	MCHP_DMA_CH_ACT(0) = 1;
-	MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM +
-		MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
-	MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO;
-	return EC_SUCCESS;
-}
diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h
deleted file mode 100644
index 4784b2c922..0000000000
--- a/chip/mchp/dma_chip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC DMA controller chip level API
- */
-/** @file dma_chip.h
- *MCHP MEC Direct Memory Access block
- */
-/** @defgroup MEC dma
- */
-
-#ifndef _DMA_CHIP_H
-#define _DMA_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory);
-
-void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units);
-
-void dma_clr_chan(enum dma_channel ch);
-
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev);
-
-/*
- * ch = zero based DMA channel number
- * unit_len = DMA unit size 1, 2 or 4 bytes
- * flags
- *   b[0] = direction, 0=device_to_memory, 1=memory_to_device
- *   b[1] = 1 increment memory address
- *   b[2] = 1 increment device address
- *   b[3] = disable HW flow control
- */
-#define DMA_FLAG_D2M		0
-#define DMA_FLAG_M2D		1
-#define DMA_FLAG_INCR_MEM	2
-#define DMA_FLAG_INCR_DEV	4
-#define DMA_FLAG_SW_FLOW	8
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags);
-
-void dma_run(enum dma_channel ch);
-
-uint32_t dma_is_done_chan(enum dma_channel ch);
-
-int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef _DMA_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
deleted file mode 100644
index 8a38a82688..0000000000
--- a/chip/mchp/espi.c
+++ /dev/null
@@ -1,1505 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "common.h"
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "port80.h"
-#include "util.h"
-#include "chipset.h"
-
-#include "registers.h"
-#include "espi.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "system.h"
-#include "task.h"
-#include "console.h"
-#include "uart.h"
-#include "util.h"
-#include "power.h"
-#include "timer.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-#ifdef CONFIG_MCHP_TFDP
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-/* Default config to use maximum frequency */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
-#if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_66M
-#else
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_50M
-#endif
-#endif
-
-/* Default config to support all modes */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MODE
-#define CONFIG_HOSTCMD_ESPI_EC_MODE		MCHP_ESPI_CAP1_ALL_MODE
-#endif
-
-/* Default config to support all channels */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	MCHP_ESPI_CAP0_ALL_CHAN_SUPP
-#endif
-/*
- * eSPI slave to master virtual wire pulse timeout.
- */
-#define ESPI_S2M_VW_PULSE_LOOP_CNT		50
-#define ESPI_S2M_VW_PULSE_LOOP_DLY_US		10
-
-/*
- * eSPI master enable virtual wire channel timeout.
- */
-#define ESPI_CHAN_READY_TIMEOUT_US (100 * MSEC)
-#define ESPI_CHAN_READY_POLL_INTERVAL_US 100
-
-static uint32_t espi_channels_ready;
-
-/*
- * eSPI Virtual Wire reset values
- * VWire name used by chip independent code.
- * Host eSPI Master VWire index containing signal
- * Reset value of VWire. Note, each Host VWire index may
- * have a different reset source:
- *	EC Power-on/chip reset
- *	ESPI_RESET# assertion by Host eSPI master
- *	eSPI Platform Reset assertion by Host eSPI master
- *		MEC1701H allows eSPI Platform reset to
- *		be a VWire or side band signal.
- *
- * NOTE MEC1701H Boot-ROM will restore VWires ... from
- * VBAT power register MCHP_VBAT_VWIRE_BACKUP.
- *	bits[3:0] = Master-to-Slave Index 02h SRC3:SRC0 values
- *		MSVW00 register
- *			SRC0 = SLP_S3#
- *			SRC1 = SLP_S4#
- *			SRC2 = SLP_S5#
- *			SRC3 = reserved
- *	bits[7:4] = Master-to-Slave Index 42h SRC3:SRC0 values
- *		MSVW04 register
- *			SRC0 = SLP_LAN#
- *			SRC1 = SLP_WLAN#
- *			SRC2 = reserved
- *			SRC3 = reserved
- *
- */
-struct vw_info_t {
-	uint16_t name;		/* signal name */
-	uint8_t  host_idx;	/* Host VWire index of signal */
-	uint8_t  reset_val;	/* reset value of VWire */
-	uint8_t  flags;		/* b[0]=0(MSVW), =1(SMVW) */
-	uint8_t  reg_idx;	/* MSVW or SMVW index */
-	uint8_t  src_num;	/* SRC number */
-	uint8_t  rsvd;
-};
-
-
-/* VW signals used in eSPI */
-/*
- * MEC1701H VWire mapping based on eSPI Spec 1.0,
- * eSPI Compatibility spec 0.96,
- * MCHP HW defaults and ec/include/espi.h
- *
- * MSVW00 index=02h PORValue=00000000_04040404_00000102 reset=RESET_SYS
- *	SRC0 = VW_SLP_S3_L, IntrDis
- *	SRC1 = VW_SLP_S4_L, IntrDis
- *	SRC2 = VW_SLP_S5_L, IntrDis
- *	SRC3 = reserved, IntrDis
- * MSVW01 index=03h PORValue=00000000_04040404_00000003 reset=RESET_ESPI
- *	SRC0 = VW_SUS_STAT_L, IntrDis
- *	SRC1 = VW_PLTRST_L, IntrDis
- *	SRC2 = VW_OOB_RST_WARN, IntrDis
- *	SRC3 = reserved, IntrDis
- * MSVW02 index=07h PORValue=00000000_04040404_00000307 reset=PLTRST
- *	SRC0 = VW_HOST_RST_WARN
- *	SRC1 = 0 reserved
- *	SRC2 = 0 reserved
- *	SRC3 = 0 reserved
- * MSVW03 index=41h PORValue=00000000_04040404_00000041 reset=RESET_ESPI
- *	SRC0 = VW_SUS_WARN_L, IntrDis
- *	SRC1 = VW_SUS_PWRDN_ACK_L, IntrDis
- *	SRC2 = 0 reserved, IntrDis
- *	SRC3 = VW_SLP_A_L, IntrDis
- * MSVW04 index=42h PORValue=00000000_04040404_00000141 reset=RESET_SYS
- *	SRC0 = VW_SLP_LAN, IntrDis
- *	SRC1 = VW_SLP_WLAN, IntrDis
- *	SRC2 = reserved, IntrDis
- *	SRC3 = reserved, IntrDis
- *
- * SMVW00 index=04h PORValue=01010000_0000C004 STOM=1100 reset=RESET_ESPI
- *	SRC0 = VW_OOB_RST_ACK
- *	SRC1 = 0 reserved
- *	SRC2 = VW_WAKE_L
- *	SRC3 = VW_PME_L
- * SMVW01 index=05h PORValue=00000000_00000005 STOM=0000 reset=RESET_ESPI
- *	SRC0 = SLAVE_BOOT_LOAD_DONE   !!! NOTE: Google combines SRC0 & SRC3
- *	SRC1 = VW_ERROR_FATAL
- *	SRC2 = VW_ERROR_NON_FATAL
- *	SRC3 = SLAVE_BOOT_LOAD_STATUS !!! into VW_PERIPHERAL_BTLD_STATUS_DONE
- * SMVW02 index=06h PORValue=00010101_00007306 STOM=0111 reset=PLTRST
- *	SRC0 = VW_SCI_L
- *	SRC1 = VW_SMI_L
- *	SRC2 = VW_RCIN_L
- *	SRC3 = VW_HOST_RST_ACK
- * SMVW03 index=40h PORValue=00000000_00000040 STOM=0000 reset=RESET_ESPI
- *	SRC0 = assign VW_SUS_ACK
- *	SRC1 = 0
- *	SRC2 = 0
- *	SRC3 = 0
- *
- * table of vwire structures
- * MSVW00 at 0x400F9C00 offset = 0x000
- * MSVW01 at 0x400F9C0C offset = 0x00C
- *
- * SMVW00 at 0x400F9E00 offset = 0x200
- * SMVW01 at 0x400F9E08 offset = 0x208
- *
- */
-
-/*
- * Virtual Wire table
- * Each entry contains:
- *	Signal name from include/espi.h
- *	Host chipset VWire index number
- *      Reset value of VWire
- *      flags where bit[0]==0 Wire is Master-to-Slave or 1 Slave-to-Master
- *	MEC1701 register index into MSVW or SMVW register banks
- *	MEC1701 source number in MSVW or SMVW bank
- *      Reserved
- *	Pointer to name string for debug
- */
-static const struct vw_info_t vw_info_tbl[] = {
-	/* name				host  reset       reg   SRC
-	 *				index value flags index num   rsvd
-	 */
-	/* MSVW00 Host index 02h (In) */
-	{VW_SLP_S3_L,			 0x02, 0x00, 0x00, 0x00, 0x00, 0x00},
-	{VW_SLP_S4_L,			 0x02, 0x00, 0x00, 0x00, 0x01, 0x00},
-	{VW_SLP_S5_L,			 0x02, 0x00, 0x10, 0x00, 0x02, 0x00},
-	/* MSVW01 Host index 03h (In) */
-	{VW_SUS_STAT_L,			 0x03, 0x00, 0x10, 0x01, 0x00, 0x00},
-	{VW_PLTRST_L,			 0x03, 0x00, 0x10, 0x01, 0x01, 0x00},
-	{VW_OOB_RST_WARN,		 0x03, 0x00, 0x10, 0x01, 0x02, 0x00},
-	/* SMVW00 Host Index 04h (Out) */
-	{VW_OOB_RST_ACK,		 0x04, 0x00, 0x01, 0x00, 0x00, 0x00},
-	{VW_WAKE_L,			 0x04, 0x01, 0x01, 0x00, 0x02, 0x00},
-	{VW_PME_L,			 0x04, 0x01, 0x01, 0x00, 0x03, 0x00},
-	/* SMVW01 Host index 05h (Out) */
-	{VW_ERROR_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x01, 0x00},
-	{VW_ERROR_NON_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x02, 0x00},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00},
-	/* SMVW02 Host index 06h (Out) */
-	{VW_SCI_L,			 0x06, 0x01, 0x01, 0x02, 0x00, 0x00},
-	{VW_SMI_L,			 0x06, 0x01, 0x01, 0x02, 0x01, 0x00},
-	{VW_RCIN_L,			 0x06, 0x01, 0x01, 0x02, 0x02, 0x00},
-	{VW_HOST_RST_ACK,		 0x06, 0x00, 0x01, 0x02, 0x03, 0x00},
-	/* MSVW02 Host index 07h (In) */
-	{VW_HOST_RST_WARN,		 0x07, 0x00, 0x10, 0x02, 0x00, 0x00},
-	/* SMVW03 Host Index 40h (Out) */
-	{VW_SUS_ACK,			 0x40, 0x00, 0x01, 0x03, 0x00, 0x00},
-	/* MSVW03 Host Index 41h (In) */
-	{VW_SUS_WARN_L,			 0x41, 0x00, 0x10, 0x03, 0x00, 0x00},
-	{VW_SUS_PWRDN_ACK_L,		 0x41, 0x00, 0x10, 0x03, 0x01, 0x00},
-	{VW_SLP_A_L,			 0x41, 0x00, 0x10, 0x03, 0x03, 0x00},
-	/* MSVW04 Host index 42h (In) */
-	{VW_SLP_LAN,			 0x42, 0x00, 0x10, 0x04, 0x00, 0x00},
-	{VW_SLP_WLAN,			 0x42, 0x00, 0x10, 0x04, 0x01, 0x00}
-};
-BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT);
-
-
-/************************************************************************/
-/* eSPI internal utilities */
-
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	int i;
-
-	/* Search table by signal name */
-	for (i = 0; i < ARRAY_SIZE(vw_info_tbl); i++) {
-		if (vw_info_tbl[i].name == event)
-			return i;
-	}
-
-	return -1;
-}
-
-
-/*
- * Initialize eSPI hardware upon ESPI_RESET# de-assertion
- */
-#ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
-static void espi_reset_deassert_init(void)
-{
-
-}
-#endif
-
-/* Call this on entry to deepest sleep state with EC turned off.
- * May not be required in future host eSPI chipsets.
- *
- * Save Master-to-Slave VWire Index 02h & 42h before
- * entering a deep sleep state where EC power is shut off.
- * PCH requires we restore these VWires on wake.
- * SLP_S3#, SLP_S4#, SLP_S5# in index 02h
- * SLP_LAN#, SLP_WLAN# in index 42h
- * Current VWire states are saved to a battery backed 8-bit
- * register in MEC1701H.
- * If a VBAT POR occurs the value of this register = 0 which
- * is the default state of the above VWires on a hardware
- * POR.
- * VBAT byte bit definitions
- * Host Index 02h -> MSVW00
- * Host Index 42h -> MSVW04
- * 0 Host Index 02h SRC0
- * 1 Host Index 02h SRC1
- * 2 Host Index 02h SRC2
- * 3 Host Index 02h SRC3
- * 4 Host Index 42h SRC0
- * 5 Host Index 42h SRC1
- * 6 Host Index 42h SRC2
- * 7 Host Index 42h SRC3
- */
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-static void espi_vw_save(void)
-{
-	uint32_t i, r;
-	uint8_t vb;
-
-	vb = 0;
-	r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42);
-	for (i = 0; i < 4; i++) {
-		if (r & (1ul << (i << 3)))
-			vb |= (1u << i);
-	}
-
-	vb <<= 4;
-	r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02);
-	for (i = 0; i < 4; i++) {
-		if (r & (1ul << (i << 3)))
-			vb |= (1u << i);
-	}
-
-	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
-	r = (r & 0xFFFFFF00) | vb;
-	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r;
-}
-
-/*
- * Update MEC1701H VBAT powered VWire backup values restored on
- * MCHP chip reset. MCHP Boot-ROM loads these values into
- * MSVW00 SRC[0:3](Index 02h) and MSVW04 SRC[0:3](Index 42h)
- * on chip reset(POR, WDT reset, chip reset, wake from EC off).
- * Always clear backup value after restore.
- */
-static void espi_vw_restore(void)
-{
-	uint32_t i, r;
-	uint8_t vb;
-
-#ifdef EVB_NO_ESPI_TEST_MODE
-	vb = 0xff; /* force SLP_Sx# signals to 1 */
-#else
-	vb = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) & 0xff;
-#endif
-	r = 0;
-	for (i = 0; i < 4; i++) {
-		if (vb & (1u << i))
-			r |= (1ul << (i << 3));
-	}
-	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02) = r;
-	CPRINTS("eSPI restore MSVW00(Index 02h) = 0x%08x", r);
-
-	vb >>= 4;
-	r = 0;
-	for (i = 0; i < 4; i++) {
-		if (vb & (1u << i))
-			r |= (1ul << (i << 3));
-	}
-	MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42) = r;
-	CPRINTS("eSPI restore MSVW00(Index 42h) = 0x%08x", r);
-
-	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
-	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00;
-
-}
-#endif
-
-static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id)
-{
-	uint8_t msvw;
-
-	msvw = 0;
-	if (msvw_id < MSVW_MAX) {
-		uint32_t r = MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id);
-
-		msvw = (r & 0x01);
-		msvw |= ((r >> 7) & 0x02);
-		msvw |= ((r >> 14) & 0x04);
-		msvw |= ((r >> 21) & 0x08);
-	}
-
-	return msvw;
-}
-
-static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id,
-						       uint8_t src_bitmap)
-{
-	if (msvw_id < MSVW_MAX) {
-		uint32_t r = (src_bitmap & 0x08) << 21;
-
-		r |= (src_bitmap & 0x04) << 14;
-		r |= (src_bitmap & 0x02) << 7;
-		r |= (src_bitmap & 0x01);
-		MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id) = r;
-	}
-}
-
-static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id)
-{
-	uint8_t smvw;
-
-	smvw = 0;
-	if (smvw_id < SMVW_MAX) {
-		uint32_t r = MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id);
-
-		smvw = (r & 0x01);
-		smvw |= ((r >> 7) & 0x02);
-		smvw |= ((r >> 14) & 0x04);
-		smvw |= ((r >> 21) & 0x08);
-	}
-
-	return smvw;
-}
-
-static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
-						       uint8_t src_bitmap)
-{
-	if (smvw_id < SMVW_MAX) {
-		uint32_t r = (src_bitmap & 0x08) << 21;
-
-		r |= (src_bitmap & 0x04) << 14;
-		r |= (src_bitmap & 0x02) << 7;
-		r |= (src_bitmap & 0x01);
-		MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id) = r;
-	}
-}
-
-
-/*
- * Called before releasing RSMRST#
- *	ESPI_RESET# is asserted
- *	PLATFORM_RESET# is asserted
- */
-static void espi_bar_pre_init(void)
-{
-	/* Configuration IO BAR set to 0x2E/0x2F */
-	MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E;
-	MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00;
-	MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1;
-}
-
-/*
- * Called before releasing RSMRST#
- *	ESPI_RESET# is asserted
- *	PLATFORM_RESET# is asserted
- * Set all MSVW to either edge interrupt
- *	IRQ_SELECT fields are reset on RESET_SYS not ESPI_RESET or PLTRST
- *
- */
-static void espi_vw_pre_init(void)
-{
-	uint32_t i;
-
-	CPRINTS("eSPI VW Pre-Init");
-
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-	espi_vw_restore();
-#endif
-
-	/* disable all */
-	for (i = 0; i < MSVW_MAX; i++)
-		MCHP_ESPI_VW_M2S_IRQSEL_ALL(i) = 0x0f0f0f0ful;
-
-	/* clear spurious status */
-	MCHP_INT_SOURCE(24) = 0xfffffffful;
-	MCHP_INT_SOURCE(25) = 0xfffffffful;
-
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H02) = 0x040f0f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H03) = 0x040f0f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H07) = 0x0404040ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H41) = 0x0f040f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H42) = 0x04040f0ful;
-	MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H47) = 0x0404040ful;
-
-	MCHP_INT_ENABLE(24) = 0xfff3b177ul;
-	MCHP_INT_ENABLE(25) = 0x01ul;
-
-	MCHP_INT_SOURCE(24) = 0xfffffffful;
-	MCHP_INT_SOURCE(25) = 0xfffffffful;
-
-	MCHP_INT_BLK_EN = (1ul << 24) + (1ul << 25);
-
-	task_enable_irq(MCHP_IRQ_GIRQ24);
-	task_enable_irq(MCHP_IRQ_GIRQ25);
-
-	CPRINTS("eSPI VW Pre-Init Done");
-}
-
-
-/*
- * If VWire, Flash, and OOB channels have been enabled
- * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1
- * SLAVE_BOOT_LOAD_STATUS = SRC3 of Slave-to-Master Index 05h
- * SLAVE_BOOT_LOAD_DONE = SRC0 of Slave-to-Master Index 05h
- * Note, if set individually then set status first then done.
- * We set both simultaneously. ESPI_ALERT# will assert only if one
- * or both bits change.
- * SRC0 is bit[32] of SMVW01
- * SRC3 is bit[56] of SMVW01
- */
-static void espi_send_boot_load_done(void)
-{
-	/* First set SLAVE_BOOT_LOAD_STATUS = 1 */
-	MCHP_ESPI_VW_S2M_SRC3(SMVW_H05) = 1;
-	/* Next set SLAVE_BOOT_LOAD_DONE = 1 */
-	MCHP_ESPI_VW_S2M_SRC0(SMVW_H05) = 1;
-
-	CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1");
-}
-
-
-/*
- * Called when eSPI PLTRST# VWire de-asserts
- * Re-initialize any hardware that was reset while PLTRST# was
- * asserted.
- * Logical Device BAR's, etc.
- *   Each BAR requires address, mask, and valid bit
- *     mask = bit map of address[7:0] to mask out
- *	0 = no masking, match exact address
- *	0x01 = mask bit[0], match two consecutive addresses
- *	0xff = mask bits[7:0], match 256 consecutive bytes
- *     eSPI has two registers for each BAR
- *       Host visible register
- *		base address in bits[31:16]
- *		valid = bit[0]
- *       EC only register
- *		mask = bits[7:0]
- *		Logical device number = bits[13:8]
- *		Virtualized = bit[16] Not Implemented
- */
-static void espi_host_init(void)
-{
-	CPRINTS("eSPI - espi_host_init");
-
-	/* BAR's */
-
-	/* Configuration IO BAR set to 0x2E/0x2F */
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x01;
-	MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E;
-	MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00;
-	MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1;
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	chip_acpi_ec_config(0, 0x62, 0x04);
-
-	/* Set up ACPI1 for 0x200-0x203, 0x204-0x207 */
-	chip_acpi_ec_config(1, 0x200, 0x07);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	chip_8042_config(0x60);
-
-	/* EMI at 0x800 for accessing shared memory */
-	chip_emi0_config(0x800);
-
-	/* Setup Port80 Debug Hardware for I/O 80h */
-	chip_port80_config(0x80);
-
-	lpc_mem_mapped_init();
-
-	MCHP_ESPI_PC_STATUS = 0xfffffffful;
-	/* PC enable & Mastering enable changes */
-	MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28);
-
-
-	/* Sufficiently initialized */
-	lpc_set_init_done(1);
-
-	/* last set eSPI Peripheral Channel Ready = 1 */
-	/* Done in ISR for PC Channel */
-	MCHP_ESPI_IO_PC_READY = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	/* NOTE: This routine may pulse SCI# and/or SMI#
-	 * For eSPI these are virtual wires. VWire channel should be
-	 * enabled before PLTRST# is de-asserted so its safe BUT has
-	 * PC Channel(I/O) Enable occurred?
-	 */
-	lpc_update_host_event_status();
-
-	CPRINTS("eSPI - espi_host_init Done");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST);
-
-
-/*
- * Called in response to VWire OOB_RST_WARN==1 from
- * espi_vw_evt_oob_rst_warn.
- * Host chipset eSPI documentation states eSPI slave should
- * if necessary flush any OOB upstream (OOB TX) data before the slave
- * sends OOB_RST_ACK=1 to the Host.
- */
-static void espi_oob_flush(void)
-{
-}
-
-
-/*
- * Called in response to VWire HOST_RST_WARN==1 from
- * espi_vw_evt_host_rst_warn.
- * Host chipset eSPI documentation states assertion of HOST_RST_WARN
- * can be used if necessary to flush any Peripheral Channel data
- * before slave sends HOST_RST_ACK to Host.
- */
-static void espi_pc_flush(void)
-{
-}
-
-/* The ISRs of VW signals which used for power sequences */
-void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
-{
-	CPRINTS("eSPI power signal interrupt for VW %d", signal);
-	power_signal_interrupt((enum gpio_signal) signal);
-}
-
-/************************************************************************/
-/* IC specific low-level driver */
-
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	int tidx;
-	uint8_t ridx, src_num;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 == (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Master-to-Slave */
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	if (level)
-		level = 1;
-
-	if (signal == VW_PERIPHERAL_BTLD_STATUS_DONE) {
-		/* SLAVE_BOOT_LOAD_STATUS */
-		MCHP_ESPI_VW_S2M_SRC3(ridx) = level;
-		/* SLAVE_BOOT_LOAD_DONE after status */
-		MCHP_ESPI_VW_S2M_SRC0(ridx) = level;
-	} else {
-		MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level;
-	}
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Set Wire %s = %d",
-		espi_vw_get_wire_name(signal), level);
-#endif
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set Slave to Master virtual wire to level and wait for hardware
- * to process virtual wire.
- * If virtual wire written to same value then hardware change bit
- * is 0 and routine returns success.
- * If virtual wire written to different value then hardware change bit
- * goes to 1 until bit is transmitted upstream to the master. This may
- * happen quickly is bus is idle. Poll for hardware clearing change bit
- * until timeout.
- */
-static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num,
-		uint8_t level)
-{
-	uint32_t i;
-
-	MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01;
-
-	for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) {
-		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) &
-		     (1u << src_num)) == 0)
-			return EC_SUCCESS;
-		udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/*
- * Create a pulse on a Slave-to-Master VWire
- * Use case is generate low pulse on SCI# virtual wire.
- * Should a timeout mechanism be added because we are
- * waiting on Host eSPI Master to respond to eSPI Alert and
- * then read the VWires. If the eSPI Master is OK the maximum
- * time will still be variable depending upon link frequency and
- * other activity on the link. Other activity is currently bounded by
- * Host chipset eSPI maximum payload length of 64 bytes + packet overhead.
- * Lowest eSPI transfer rate is 1x at 20 MHz, assume 30% packet overhead.
- * (64 * 1.3) * 8 = 666 bits is roughly 34 us. Pad to 100 us.
- */
-int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
-{
-	int rc, tidx;
-	uint8_t ridx, src_num, level;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 == (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Master-to-Slave */
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	level = 0;
-	if (pulse_level)
-		level = 1;
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Pulse Wire %s to %d",
-		espi_vw_get_wire_name(signal), level);
-#endif
-
-	/* set requested inactive state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level);
-	if (rc != EC_SUCCESS)
-		return rc;
-
-	/* drive to requested active state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, level);
-	if (rc != EC_SUCCESS)
-		return rc;
-
-	/* set to requested inactive state */
-	rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level);
-
-	return rc;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	int vw, tidx;
-	uint8_t ridx, src_num;
-
-	vw = 0;
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx >= 0 && (0 == (vw_info_tbl[tidx].flags & (1u << 0)))) {
-		ridx = vw_info_tbl[tidx].reg_idx;
-		src_num = vw_info_tbl[tidx].src_num;
-		vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01;
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-		CPRINTS("VW GetWire %s = %d",
-			espi_vw_get_wire_name(signal), vw);
-#endif
-	}
-
-	return vw;
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	int tidx;
-	uint8_t ridx, src_num, girq_num, bpos;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 != (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrEn for VW[%s]",
-		espi_vw_get_wire_name(signal));
-#endif
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	/*
-	 * Set SRCn_IRQ_SELECT field for VWire to either edge
-	 * Write enable set bit in GIRQ24 or GIRQ25
-	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
-	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
-	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
-
-	girq_num = 24;
-	if (ridx > 6) {
-		girq_num++;
-		ridx -= 7;
-	}
-	bpos = (ridx << 2) + src_num;
-
-	MCHP_INT_SOURCE(girq_num) = (1ul << bpos);
-	MCHP_INT_ENABLE(girq_num) = (1ul << bpos);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	int tidx;
-	uint8_t ridx, src_num, bpos;
-
-	tidx = espi_vw_get_signal_index(signal);
-
-	if (tidx < 0)
-		return EC_ERROR_PARAM1;
-
-	if (0 != (vw_info_tbl[tidx].flags & (1u << 0)))
-		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
-
-#ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrDis for VW[%s]",
-		espi_vw_get_wire_name(signal));
-#endif
-
-	ridx = vw_info_tbl[tidx].reg_idx;
-	src_num = vw_info_tbl[tidx].src_num;
-
-	/*
-	 * Set SRCn_IRQ_SELECT field for VWire to disabled
-	 * Write enable set bit in GIRQ24 or GIRQ25
-	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
-	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
-	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_DISABLED;
-
-	if (ridx < 7) {
-		bpos = (ridx << 2) + src_num;
-		MCHP_INT_DISABLE(24) = (1ul << bpos);
-
-	} else {
-		bpos = ((ridx - 7) << 2) + src_num;
-		MCHP_INT_DISABLE(25) = (1ul << bpos);
-	}
-
-	return EC_SUCCESS;
-}
-
-/************************************************************************/
-/* VW event handlers */
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-
-/* SLP_Sx event handler */
-void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S3: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S3_L);
-}
-
-void espi_vw_evt_slp_s4_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S4: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S4_L);
-}
-
-void espi_vw_evt_slp_s5_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_S5: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SLP_S5_L);
-}
-
-void espi_vw_evt_sus_stat_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_STAT: %d", wire_state);
-	espi_vw_power_signal_interrupt(VW_SUS_STAT_L);
-}
-
-/* PLTRST# event handler */
-void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW PLTRST#: %d", wire_state);
-
-	if (wire_state) /* Platform Reset de-assertion */
-		espi_host_init();
-	else /* assertion */
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-
-}
-
-/* OOB Reset Warn event handler */
-void espi_vw_evt_oob_rst_warn(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW OOB_RST_WARN: %d", wire_state);
-
-	espi_oob_flush();
-
-	espi_vw_set_wire(VW_OOB_RST_ACK, wire_state);
-}
-
-/* SUS_WARN# event handler */
-void espi_vw_evt_sus_warn_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_WARN#: %d", wire_state);
-
-	udelay(100);
-
-	/*
-	 *  Add any Deep Sx prep here
-	 * NOTE: we could schedule a deferred function and have
-	 * it send ACK to host after preparing for Deep Sx
-	 */
-#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-	espi_vw_save();
-#endif
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_SUS_ACK, wire_state);
-}
-
-/*
- * SUS_PWRDN_ACK
- * PCH is informing us it does not need suspend power well.
- * if SUS_PWRDN_ACK == 1 we can turn off suspend power well assuming
- * hardware design allow.
- */
-void espi_vw_evt_sus_pwrdn_ack(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SUS_PWRDN_ACK: %d", wire_state);
-}
-
-/* SLP_A#(SLP_M#) */
-void espi_vw_evt_slp_a_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_A: %d", wire_state);
-
-	/* Put handling of ASW well devices here, if any */
-}
-
-/* HOST_RST WARN event handler */
-void espi_vw_evt_host_rst_warn(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW HOST_RST_WARN: %d", wire_state);
-
-	espi_pc_flush();
-
-	/* Send HOST_RST_ACK to host */
-	espi_vw_set_wire(VW_HOST_RST_ACK, wire_state);
-}
-
-/* SLP_LAN# */
-void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_LAN: %d", wire_state);
-}
-
-/* SLP_WLAN# */
-void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW SLP_WLAN: %d", wire_state);
-
-}
-
-void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("VW HOST_C10: %d", wire_state);
-}
-
-void espi_vw_evt1_dflt(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("Unknown M2S VW: state=%d GIRQ24 bitpos=%d", wire_state, bpos);
-}
-
-void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos)
-{
-	CPRINTS("Unknown M2S VW: state=%d GIRQ25 bitpos=%d", wire_state, bpos);
-}
-
-/************************************************************************/
-/* Interrupt handlers */
-
-/* MEC1701H
- * GIRQ19 all direct connect capable, none wake capable
- *	b[0] = Peripheral Channel (PC)
- *	b[1] = Bus Master 1 (BM1)
- *	b[2] = Bus Master 2 (BM2)
- *	b[3] = LTR
- *	b[4] = OOB_UP
- *	b[5] = OOB_DN
- *	b[6] = Flash Channel (FC)
- *	b[7] = ESPI_RESET# change
- *	b[8] = VWire Channel (VW) enable assertion
- *	b[9:31] = 0 reserved
- *
- * GIRQ22 b[9]=ESPI interface wake peripheral logic only, not EC.
- *	Not direct connect capable
- *
- * GIRQ24
- *	b[0:3]   = MSVW00_SRC[0:3]
- *	b[4:7]   = MSVW01_SRC[0:3]
- *	b[8:11]  = MSVW02_SRC[0:3]
- *	b[12:15] = MSVW03_SRC[0:3]
- *	b[16:19] = MSVW04_SRC[0:3]
- *	b[20:23] = MSVW05_SRC[0:3]
- *	b[24:27] = MSVW06_SRC[0:3]
- *	b[28:31] = 0 reserved
- *
- * GIRQ25
- *	b[0:3]   = MSVW07_SRC[0:3]
- *	b[4:7]   = MSVW08_SRC[0:3]
- *	b[8:11]  = MSVW09_SRC[0:3]
- *	b[12:15] = MSVW10_SRC[0:3]
- *	b[16:31] = 0 reserved
- *
- */
-
-typedef void (*FPVW)(uint32_t, uint32_t);
-
-#define MCHP_GIRQ24_NUM_M2S	(7 * 4)
-const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
-	espi_vw_evt_slp_s3_n,	/* MSVW00, Host M2S 02h */
-	espi_vw_evt_slp_s4_n,
-	espi_vw_evt_slp_s5_n,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_stat_n,	/* MSVW01, Host M2S 03h */
-	espi_vw_evt_pltrst_n,
-	espi_vw_evt_oob_rst_warn,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_host_rst_warn, /* MSVW02, Host M2S 07h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_warn_n,	/* MSVW03, Host M2S 41h */
-	espi_vw_evt_sus_pwrdn_ack,
-	espi_vw_evt1_dflt,
-	espi_vw_evt_slp_a_n,
-	espi_vw_evt_slp_lan_n,	/* MSVW04, Host M2S 42h */
-	espi_vw_evt_slp_wlan_n,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW05, Host M2S 43h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW06, Host M2S 44h */
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt
-};
-
-#define MCHP_GIRQ25_NUM_M2S	(4 * 4)
-const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = {
-	espi_vw_evt_host_c10,	/* MSVW07, Host M2S 47h */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW08 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW09 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW10 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-};
-
-/* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */
-void espi_mswv1_interrupt(void)
-{
-	uint32_t d, girq24_result, bpos;
-
-	d = MCHP_INT_ENABLE(24);
-	girq24_result = MCHP_INT_RESULT(24);
-	MCHP_INT_SOURCE(24) = girq24_result;
-
-	bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */
-	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
-		(girq24_vw_handlers[bpos])(d, bpos);
-		girq24_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq24_result);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2);
-
-
-/* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */
-void espi_msvw2_interrupt(void)
-{
-	uint32_t d, girq25_result, bpos;
-
-	d = MCHP_INT_ENABLE(25);
-	girq25_result = MCHP_INT_RESULT(25);
-	MCHP_INT_SOURCE(25) = girq25_result;
-
-	bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */
-	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
-		(girq25_vw_handlers[bpos])(d, bpos);
-		girq25_result &= ~(1ul << bpos);
-		bpos = __builtin_ctz(girq25_result);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2);
-
-
-
-/*
- * NOTES:
- * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and
- * their registers can't be programmed. All channel Enable and Ready bits
- * are cleared. The only operational logic is the ESPI_RESET# change
- * detection logic.
- * Once ESPI_RESET# de-asserts, firmware can enable interrupts on all
- * other eSPI channels/components.
- * Implications are:
- * ESPI_RESET# assertion -
- *	All channel ready bits are cleared stopping all outstanding
- *	transactions and clearing registers and internal FIFO's.
- * ESPI_RESET# de-assertion -
- *	All channels/components can now be programmed and can detect
- *	reception of channel enable messages from the eSPI Master.
- */
-
-/*
- * eSPI Reset change handler
- * Multiple scenarios must be handled.
- * eSPI Link initialization from de-assertion of RSMRST#
- *	Upon RSMRST# de-assertion, the PCH may drive ESPI_RESET# low
- *	and then back high. If the platform has a pull-down on ESPI_RESET#
- *	then we will not see both edges. We must handle the scenario where
- *	ESPI_RESET# has only a rising edge or is pulsed low once RSMRST#
- *	has been released.
- * eSPI Link is operational and PCH asserts ESPI_RESET# due to
- * global reset event or some other system problem.
- *	eSPI link is operational and the system generates a global reset
- *	event to the PCH. EC is unaware of global reset and sees PCH
- *	activate ESPI_RESET#.
- *
- * ESPI_RESET# assertion will disable all MCHP eSPI channel ready
- * bits and place all channels is reset state. Any hardware affected by
- * ESPI_RESET# must be re-initialized after ESPI_RESET# de-asserts.
- *
- * Note ESPI_RESET# is not equivalent to LPC LRESET#. LRESET# is
- * equivalent to eSPI Platform Reset.
- *
- */
-void espi_reset_isr(void)
-{
-	uint8_t erst;
-
-	erst = MCHP_ESPI_IO_RESET_STATUS;
-	MCHP_ESPI_IO_RESET_STATUS = erst;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
-	if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = (
-				MCHP_ESPI_PC_GIRQ_BIT +
-				MCHP_ESPI_OOB_TX_GIRQ_BIT +
-				MCHP_ESPI_FC_GIRQ_BIT +
-				MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_ESPI_OOB_TX_IEN = (1ul << 1);
-		MCHP_ESPI_FC_IEN = (1ul << 1);
-		MCHP_ESPI_PC_IEN = (1ul << 25);
-		CPRINTS("eSPI Reset de-assert");
-
-	} else { /* falling edge - reset asserted */
-		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		espi_channels_ready = 0;
-
-		chipset_handle_espi_reset_assert();
-
-		CPRINTS("eSPI Reset assert");
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_RESET, espi_reset_isr, 3);
-
-/*
- * eSPI Virtual Wire channel enable handler
- * Must disable once VW Enable is set by eSPI Master
- */
-void espi_vw_en_isr(void)
-{
-	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT;
-
-	MCHP_ESPI_IO_VW_READY = 1;
-
-	espi_channels_ready |= (1ul << 0);
-
-	CPRINTS("eSPI VW Enable received, set VW Ready");
-
-	if (0x03 == (espi_channels_ready & 0x03))
-		espi_send_boot_load_done();
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2);
-
-
-/*
- * eSPI OOB TX and OOB channel enable change interrupt handler
- */
-void espi_oob_tx_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_OOB_TX_STATUS;
-	MCHP_ESPI_OOB_TX_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_TX_GIRQ_BIT;
-	if (sts & (1ul << 1)) {
-		/* Channel Enable change */
-		if (sts & (1ul << 9)) { /* enable? */
-			MCHP_ESPI_OOB_RX_LEN = 73;
-			MCHP_ESPI_IO_OOB_READY = 1;
-			espi_channels_ready |= (1ul << 2);
-			CPRINTS("eSPI OOB_UP ISR: OOB Channel Enable");
-		} else { /* no, disabled by Master */
-			espi_channels_ready &= ~(1ul << 2);
-			CPRINTS("eSPI OOB_UP ISR: OOB Channel Disable");
-		}
-	} else {
-		/* Handle OOB Up transmit status: done and/or errors, here */
-		CPRINTS("eSPI OOB_UP status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2);
-
-
-/* eSPI OOB RX interrupt handler */
-void espi_oob_rx_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_OOB_RX_STATUS;
-	MCHP_ESPI_OOB_RX_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_RX_GIRQ_BIT;
-	/* Handle OOB Up transmit status: done and/or errors, if any */
-	CPRINTS("eSPI OOB_DN status = 0x%x", sts);
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2);
-
-
-/*
- * eSPI Flash Channel enable change and data transfer
- * interrupt handler
- */
-void espi_fc_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_FC_STATUS;
-	MCHP_ESPI_FC_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_FC_GIRQ_BIT;
-	if (sts & (1ul << 1)) {
-		/* Channel Enable change */
-		if (sts & (1ul << 0)) { /* enable? */
-			MCHP_ESPI_IO_FC_READY = 1;
-			espi_channels_ready |= (1ul << 1);
-			CPRINTS("eSPI FC ISR: Enable");
-			if (0x03 == (espi_channels_ready & 0x03))
-				espi_send_boot_load_done();
-		} else { /* no, disabled by Master */
-			espi_channels_ready &= ~(1ul << 1);
-			CPRINTS("eSPI FC ISR: Disable");
-		}
-	} else {
-		/* Handle FC command status: done and/or errors */
-		CPRINTS("eSPI FC status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2);
-
-
-/* eSPI Peripheral Channel interrupt handler */
-void espi_pc_isr(void)
-{
-	uint32_t sts;
-
-	sts = MCHP_ESPI_PC_STATUS;
-	MCHP_ESPI_PC_STATUS = sts;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_PC_GIRQ_BIT;
-	if (sts & (1ul << 25)) {
-		if (sts & (1ul << 24)) {
-			MCHP_ESPI_IO_PC_READY = 1;
-			espi_channels_ready |= (1ul << 3);
-			CPRINTS("eSPI PC Channel Enable");
-		} else {
-			espi_channels_ready &= ~(1ul << 3);
-			CPRINTS("eSPI PC Channel Disable");
-		}
-
-	} else {
-		/* Handler PC channel errors here */
-		CPRINTS("eSPI PC status = 0x%x", sts);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2);
-
-
-/************************************************************************/
-
-/*
- * Enable/disable direct mode interrupt for ESPI_RESET# change.
- * Optionally clear status before enable or after disable.
- */
-static void espi_reset_ictrl(int enable, int clr_status)
-{
-	if (enable) {
-		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
-			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
-		}
-		MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN;
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
-		task_enable_irq(MCHP_IRQ_ESPI_RESET);
-	} else {
-		task_disable_irq(MCHP_IRQ_ESPI_RESET);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
-		MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN);
-		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
-			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
-		}
-	}
-}
-
-/* eSPI Initialization functions */
-
-/* MEC1701H */
-void espi_init(void)
-{
-	espi_channels_ready = 0;
-
-	CPRINTS("eSPI - espi_init");
-
-	/* Clear PCR eSPI sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ESPI);
-
-	/*
-	 * b[8]=0(eSPI PLTRST# VWire is platform reset), b[0]=0
-	 * VCC_PWRGD is asserted when PLTRST# VWire is 1(inactive)
-	 */
-	MCHP_PCR_PWR_RST_CTL = 0;
-
-	/*
-	 * There is no MODULE_ESPI in include/module_id.h
-	 * eSPI pins marked as MODULE_LPC in board/myboard/board.h
-	 * eSPI pins are on VTR3.
-	 * Make sure VTR3 chip knows VTR3 is 1.8V
-	 * This is done in system_pre_init()
-	 */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/* Set channel */
-	MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP;
-
-	/* Set eSPI frequency & mode */
-	MCHP_ESPI_IO_CAP1 = (MCHP_ESPI_IO_CAP1 &
-				(~(MCHP_ESPI_CAP1_MAX_FREQ_MASK |
-				MCHP_ESPI_CAP1_IO_MASK))) |
-				CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ |
-				(CONFIG_HOSTCMD_ESPI_EC_MODE
-				<< MCHP_ESPI_CAP1_IO_BITPOS);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
-#else
-	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
-#endif
-
-	MCHP_PCR_PWR_RST_CTL &=
-		~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
-
-	MCHP_ESPI_ACTIVATE = 1;
-
-	espi_bar_pre_init();
-
-	/*
-	 * VWires are configured to be reset by different events.
-	 * Default configuration has:
-	 * RESET_SYS (chip reset) MSVW00, MSVW04
-	 * RESET_ESPI MSVW01, MSVW03, SMVW00, SMVW01
-	 * PLTRST MSVW02, SMVW02
-	 */
-	espi_vw_pre_init();
-
-	/*
-	 * Configure MSVW00 & MSVW04
-	 * Any change to default values (SRCn bits)
-	 * Any change to interrupt enable, SRCn_IRQ_SELECT bit fields
-	 *   Should interrupt bits in MSVWyx and GIRQ24/25 be touched
-	 *   before ESPI_RESET# de-asserts?
-	 */
-
-	MCHP_ESPI_PC_STATUS = 0xfffffffful;
-	MCHP_ESPI_OOB_RX_STATUS = 0xfffffffful;
-	MCHP_ESPI_FC_STATUS = 0xfffffffful;
-	MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = 0xfffffffful;
-	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = 0xfffffffful;
-
-	task_enable_irq(MCHP_IRQ_ESPI_PC);
-	task_enable_irq(MCHP_IRQ_ESPI_OOB_UP);
-	task_enable_irq(MCHP_IRQ_ESPI_OOB_DN);
-	task_enable_irq(MCHP_IRQ_ESPI_FC);
-	task_enable_irq(MCHP_IRQ_ESPI_VW_EN);
-
-	/* Enable eSPI Master-to-Slave Virtual wire NVIC inputs
-	 * VWire block interrupts are all disabled by default
-	 * and will be controlled by espi_vw_enable/disable_wire_in
-	 */
-	CPRINTS("eSPI - enable ESPI_RESET# interrupt");
-
-	/* Enable ESPI_RESET# interrupt and clear status */
-	espi_reset_ictrl(1, 1);
-
-	CPRINTS("eSPI - espi_init - done");
-}
-
-
-#ifdef CONFIG_MCHP_ESPI_EC_CMD
-static int command_espi(int argc, char **argv)
-{
-	uint32_t chan, w0, w1, w2;
-	char *e;
-
-	if (argc == 1) {
-		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
-	} else if (argc == 2) {
-		int i;
-
-		if (strcasecmp(argv[1], "cfg") == 0) {
-			ccprintf("eSPI Reg32A [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_A);
-			ccprintf("eSPI Reg32B [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_B);
-			ccprintf("eSPI Reg32C [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_C);
-			ccprintf("eSPI Reg32D [0x%08x]\n",
-				 MCHP_ESPI_IO_REG32_D);
-		} else if (strcasecmp(argv[1], "vsm") == 0) {
-			for (i = 0; i < MSVW_MAX; i++) {
-				w0 = MSVW(i, 0);
-				w1 = MSVW(i, 1);
-				w2 = MSVW(i, 2);
-				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i,
-					w2, w1, w0);
-			}
-		} else if (strcasecmp(argv[1], "vms") == 0) {
-			for (i = 0; i < SMVW_MAX; i++) {
-				w0 = SMVW(i, 0);
-				w1 = SMVW(i, 1);
-				ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0);
-			}
-		}
-	/* Enable/Disable the channels of eSPI */
-	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (m < 0 || m > 4)
-			return EC_ERROR_PARAM2;
-		else if (m == 4)
-			chan = 0x0F;
-		else
-			chan = 0x01 << m;
-		if (strcasecmp(argv[1], "en") == 0)
-			MCHP_ESPI_IO_CAP0 |= chan;
-		else if (strcasecmp(argv[1], "dis") == 0)
-			MCHP_ESPI_IO_CAP0 &= ~chan;
-		else
-			return EC_ERROR_PARAM1;
-		ccprintf("eSPI IO Cap0 [0x%02x]\n", MCHP_ESPI_IO_CAP0);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
-			"eSPI configurations");
-#endif
diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c
deleted file mode 100644
index 17b60b703d..0000000000
--- a/chip/mchp/fan.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC fan control module. */
-
-/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
-
-#include "fan.h"
-#include "registers.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/* Maximum fan driver setting value */
-#define MAX_FAN_DRIVER_SETTING 0x3ff
-
-/* Fan driver setting data in bit[15:6] of hardware register */
-#define FAN_DRIVER_SETTING_SHIFT 6
-
-/* Maximum tach reading/target value */
-#define MAX_TACH 0x1fff
-
-/* Tach target value for disable fan */
-#define FAN_OFF_TACH 0xfff8
-
-/*
- * RPM = (n - 1) * m * f * 60 / poles / TACH
- *   n = number of edges = 5
- *   m = multiplier defined by RANGE = 2 in our case
- *   f = 32.768K
- *   poles = 2
- */
-#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
-#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
-
-static int rpm_setting;
-static int duty_setting;
-static int in_rpm_mode = 1;
-
-
-static void clear_status(void)
-{
-	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
-	MCHP_FAN_STATUS(0) = 0x23;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (in_rpm_mode) {
-		if (enabled)
-			fan_set_rpm_target(ch, rpm_setting);
-		else
-			MCHP_FAN_TARGET(0) = FAN_OFF_TACH;
-	} else {
-		if (enabled)
-			fan_set_duty(ch, duty_setting);
-		else
-			MCHP_FAN_SETTING(0) = 0;
-	}
-	clear_status();
-}
-
-int fan_get_enabled(int ch)
-{
-	if (in_rpm_mode)
-		return (MCHP_FAN_TARGET(0) & 0xff00) != 0xff00;
-	else
-		return !!MCHP_FAN_SETTING(0);
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty_setting = percent;
-	MCHP_FAN_SETTING(0) = (percent * MAX_FAN_DRIVER_SETTING / 100)
-		<< FAN_DRIVER_SETTING_SHIFT;
-	clear_status();
-}
-
-int fan_get_duty(int ch)
-{
-	duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT)
-		* 100 / MAX_FAN_DRIVER_SETTING;
-	return duty_setting;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return !!(MCHP_FAN_CFG1(0) & BIT(7));
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		MCHP_FAN_CFG1(0) |= BIT(7);
-	else
-		MCHP_FAN_CFG1(0) &= ~BIT(7);
-	clear_status();
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	if ((MCHP_FAN_READING(0) >> 8) == 0xff)
-		return 0;
-	else
-		return TACH_TO_RPM(MCHP_FAN_READING(0) >> 3);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return rpm_setting;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	rpm_setting = rpm;
-	MCHP_FAN_TARGET(0) = RPM_TO_TACH(rpm) << 3;
-	clear_status();
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	uint8_t sts = MCHP_FAN_STATUS(0);
-
-	if (sts & (BIT(5) | BIT(1)))
-		return FAN_STATUS_FRUSTRATED;
-	if (fan_get_rpm_actual(ch) == 0)
-		return FAN_STATUS_STOPPED;
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	uint8_t sts = MCHP_FAN_STATUS(0);
-
-	if (fan_get_rpm_actual(ch)) {
-		MCHP_FAN_STATUS(0) = 0x1;
-		return 0;
-	}
-	return sts & 0x1;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/* Clear PCR sleep enable for RPM2FAN0 */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_RPMPWM0);
-	/* Configure PWM Min drive */
-	MCHP_FAN_MIN_DRV(0) = 0x0A;
-	/*
-	 * Fan configuration 1 register:
-	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
-	 *   0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
-	 *   0x08 = bits 4:3 = 5 edges, 2 poles
-	 *   0x03 = bits 2:0 = 400 ms update time
-	 *
-	 * Fan configuration 2 register:
-	 *   0x00 = bit 7    = Ramp control disabled
-	 *   0x00 = bit 6    = Glitch filter enabled
-	 *   0x30 = bits 5:4 = Using both derivative options
-	 *   0x04 = bits 3:2 = error range is 50 RPM
-	 *   0x00 = bits 1   = normal polarity
-	 *   0x00 = bit 0    = Reserved
-	 */
-	if (flags & FAN_USE_RPM_MODE)
-		MCHP_FAN_CFG1(0) = 0xab;
-	else
-		MCHP_FAN_CFG1(0) = 0x2b;
-	MCHP_FAN_CFG2(0) = 0x34;
-	clear_status();
-}
diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c
deleted file mode 100644
index 1679cf92cb..0000000000
--- a/chip/mchp/flash.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "util.h"
-#include "hooks.h"
-#include "tfdp_chip.h"
-
-#define PAGE_SIZE 256
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-static int entire_flash_locked;
-
-/* The previous write protect state before sys jump */
-
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/**
- * Read from physical flash.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Destination buffer for data.
- */
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	trace13(0, FLASH, 0,
-		"flash_phys_read: offset=0x%08X size=0x%08X dataptr=0x%08X",
-		offset, size, (uint32_t)data);
-	return spi_flash_read(data, offset, size);
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int ret = EC_SUCCESS;
-	int  i, write_size;
-
-	trace13(0, FLASH, 0,
-		"flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X",
-		offset, size, (uint32_t)data);
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < size; i += write_size) {
-		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
-				      (uint8_t *)data + i);
-		if (ret != EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int crec_flash_physical_erase(int offset, int size)
-{
-	int ret;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	trace12(0, FLASH, 0,
-		"flash_phys_erase: offset=0x%08X size=0x%08X",
-		offset, size);
-	ret = spi_flash_erase(offset, size);
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
-}
-
-/**
- * Protect flash now.
- *
- * This is always successful, and only emulates "now" protection
- *
- * @param all      Protect all (=1) or just read-only
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all)
-		entire_flash_locked = 1;
-
-	/*
-	 * RO "now" protection is not currently implemented. If needed, it
-	 * can be added by splitting the entire_flash_locked variable into
-	 * and RO and RW vars, and setting + checking the appropriate var
-	 * as required.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF,
-				    CONFIG_WP_STORAGE_SIZE)) {
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-	enum spi_flash_wp wp_status = SPI_WP_NONE;
-
-	wp_status = spi_flash_check_wp();
-
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
-		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-
-	if (!entire_flash_locked)
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/**
- * Enable write protect for the specified range.
- *
- * Once write protect is enabled, it will stay enabled until HW PIN is
- * de-asserted and SRP register is unset.
- *
- * However, this implementation treats FLASH_WP_ALL as FLASH_WP_RO but
- * tries to remember if "all" region is protected.
- *
- * @param range         The range to protect.
- * @return              EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int offset, size, ret;
-	enum spi_flash_wp flashwp = SPI_WP_NONE;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection */
-		offset = size = 0;
-		flashwp = SPI_WP_NONE;
-	} else {
-		if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-			entire_flash_locked = 1;
-
-		offset = CONFIG_WP_STORAGE_OFF;
-		size = CONFIG_WP_STORAGE_SIZE;
-		flashwp = SPI_WP_HARDWARE;
-	}
-
-	ret = spi_flash_set_protect(offset, size);
-	if (ret == EC_SUCCESS)
-		ret = spi_flash_set_wp(flashwp);
-	return ret;
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	crec_flash_physical_restore_state();
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image
-	 * could have applied write protection. Nothing additional needs
-	 * to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c
deleted file mode 100644
index 611ced1019..0000000000
--- a/chip/mchp/gpio.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for MCHP MEC */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "lpc_chip.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-
-struct gpio_int_mapping {
-	int8_t girq_id;
-	int8_t port_offset;
-};
-
-/*
- * Mapping from GPIO port to GIRQ info
- * MEC17xx each bank contains 32 GPIO's.
- * Pin Id is the bit position [0:31]
- * Bank		GPIO's		GIRQ
- * 0		0000 - 0036	11
- * 1		0040 - 0076	10
- * 2		0100 - 0135	9
- * 3		0140 - 0175	8
- * 4		0200 - 0235	12
- * 5		0240 - 0276	26
- */
-static const struct gpio_int_mapping int_map[] = {
-	{ 11, 0 }, { 10, 1 }, { 9, 2 },
-	{ 8, 3 }, { 12, 4 }, { 26, 5 }
-};
-BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT);
-
-/*
- * These pins default to BGPO functionality. BGPO overrides GPIO Control
- * register programming. If the pin is in the GPIO list the user wants to
- * use the pin as GPIO and we must disable BGPIO functionality for this pin.
- */
-struct bgpo_pin {
-	uint16_t pin;
-	uint8_t bgpo_pos;
-};
-
-static const struct bgpo_pin bgpo_list[] = {
-	{ 0101, 1 }, /* GPIO 0101 */
-	{ 0102, 2 }, /* GPIO 0102 */
-#if defined(CHIP_FAMILY_MEC152X)
-	{ 0253, 0 }, /* GPIO 0253 */
-#elif defined(CHIP_FAMILY_MEC170X)
-	{ 0172, 3 }, /* GPIO 0172 */
-#endif
-};
-
-static const uint32_t bgpo_map[] = {
-#if defined(CHIP_FAMILY_MEC152X)
-	0, 0, (BIT(1) | BIT(2)), 0, 0, BIT(11)
-#elif defined(CHIP_FAMILY_MEC170X)
-	0, 0, (BIT(1) | BIT(2)), BIT(26), 0, 0
-#else
-	0, 0, 0, 0, 0, 0
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(bgpo_map) == MCHP_GPIO_MAX_PORT);
-
-/* Check for BGPO capable pins on this port and disable BGPO feature */
-static void disable_bgpo(uint32_t port, uint32_t mask)
-{
-	int i, n;
-	uint32_t gpnum;
-	uint32_t m = bgpo_map[port] & mask;
-
-	while (m) {
-		i = __builtin_ffs(m) - 1;
-		gpnum = (port * 32U) + i;
-		for (n = 0; n < ARRAY_SIZE(bgpo_list); n++)
-			if (gpnum == bgpo_list[n].pin)
-				MCHP_WKTIMER_BGPO_POWER &=
-					~BIT(bgpo_list[n].bgpo_pos);
-		m &= ~BIT(i);
-	}
-}
-
-/*
- * NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant
- * 1-bit of val or if val == 0 returns 0
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int i;
-	uint32_t val;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = __builtin_ffs(mask) - 1;
-		val = MCHP_GPIO_CTL(port, i);
-		val &= ~(BIT(12) | BIT(13));
-		/* mux_control = DEFAULT, indicates GPIO */
-		if (func > GPIO_ALT_FUNC_DEFAULT)
-			val |= (func & 0x3) << 12;
-		MCHP_GPIO_CTL(port, i) = val;
-		mask &= ~BIT(i);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-	uint32_t val;
-
-	if (mask == 0)
-		return 0;
-	i = GPIO_MASK_TO_NUM(mask);
-	val = MCHP_GPIO_CTL(gpio_list[signal].port, i);
-
-	return (val & BIT(24)) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-
-	if (mask == 0)
-		return;
-	i = GPIO_MASK_TO_NUM(mask);
-
-	if (value)
-		MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
-	else
-		MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
-}
-
-/*
- * Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN.
- * If GPIO_POWER_DOWN flag is set force GPIO Control to
- * GPIO input, interrupt detect disabled, power control field
- * in bits[3:2]=10b.
- * NOTE: if interrupt detect is enabled when pin is powered down
- * then a false edge may be detected.
- * NOTE 2: MEC152x family implements input pad disable (bit[15]=1).
- */
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	int i;
-	uint32_t val;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		val = MCHP_GPIO_CTL(port, i);
-
-#ifdef CONFIG_GPIO_POWER_DOWN
-		if (flags & GPIO_POWER_DOWN) {
-			val = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-			MCHP_GPIO_CTL(port, i) = val;
-			continue;
-		}
-#endif
-		val &= ~(MCHP_GPIO_CTRL_PWR_MASK
-			| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-		val |= MCHP_GPIO_CTRL_PWR_VTR;
-		/*
-		 * Select open drain first, so that we don't
-		 * glitch the signal when changing the line to
-		 * an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			val |= (MCHP_GPIO_OPEN_DRAIN);
-		else
-			val &= ~(MCHP_GPIO_OPEN_DRAIN);
-
-		if (flags & GPIO_OUTPUT) {
-			val |= (MCHP_GPIO_OUTPUT);
-			val &= ~(MCHP_GPIO_OUTSEL_PAR);
-		} else {
-			val &= ~(MCHP_GPIO_OUTPUT);
-			val |= (MCHP_GPIO_OUTSEL_PAR);
-		}
-
-		/* Handle pull-up / pull-down */
-		val &= ~(MCHP_GPIO_CTRL_PUD_MASK);
-		if (flags & GPIO_PULL_UP)
-			val |= MCHP_GPIO_CTRL_PUD_PU;
-		else if (flags & GPIO_PULL_DOWN)
-			val |= MCHP_GPIO_CTRL_PUD_PD;
-		else
-			val |= MCHP_GPIO_CTRL_PUD_NONE;
-
-		/* Set up interrupt */
-		val &= ~(MCHP_GPIO_INTDET_MASK);
-		switch (flags & GPIO_INT_ANY) {
-		case GPIO_INT_F_RISING:
-			val |= MCHP_GPIO_INTDET_EDGE_RIS;
-			break;
-		case GPIO_INT_F_FALLING:
-			val |= MCHP_GPIO_INTDET_EDGE_FALL;
-			break;
-		case GPIO_INT_BOTH: /* both edges */
-			val |= MCHP_GPIO_INTDET_EDGE_BOTH;
-			break;
-		case GPIO_INT_F_LOW:
-			val |= MCHP_GPIO_INTDET_LVL_LO;
-			break;
-		case GPIO_INT_F_HIGH:
-			val |= MCHP_GPIO_INTDET_LVL_HI;
-			break;
-		default:
-			val |= MCHP_GPIO_INTDET_DISABLED;
-			break;
-		}
-
-		/* Set up level */
-		if (flags & GPIO_HIGH)
-			val |= (MCHP_GPIO_CTRL_OUT_LVL);
-		else if (flags & GPIO_LOW)
-			val &= ~(MCHP_GPIO_CTRL_OUT_LVL);
-
-		MCHP_GPIO_CTL(port, i) = val;
-	}
-}
-
-void gpio_power_off_by_mask(uint32_t port, uint32_t mask)
-{
-	int i;
-
-	if (port >= MCHP_GPIO_MAX_PORT)
-		return;
-
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-					| MCHP_GPIO_INTDET_DISABLED
-					| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-	}
-}
-
-int gpio_power_off(enum gpio_signal signal)
-{
-	int i, port;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_ERROR_INVAL;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
-
-	return EC_SUCCESS;
-}
-
-/*
- * gpio_list[signal].port = [0, 6] each port contains up to 32 pins
- * gpio_list[signal].mask = bit mask in 32-bit port
- * NOTE: MCHP GPIO are always aggregated not direct connected to NVIC.
- * GPIO's are aggregated into banks of 32 pins.
- * Each bank/port are connected to a GIRQ.
- * int_map[port].girq_id is the GIRQ ID
- * The bit number in the GIRQ registers is the same as the bit number
- * in the GPIO bank.
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-	MCHP_INT_ENABLE(girq_id) = BIT(i);
-	MCHP_INT_BLK_EN |= BIT(girq_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-
-	MCHP_INT_DISABLE(girq_id) = BIT(i);
-
-	return EC_SUCCESS;
-}
-
-/*
- * MCHP Interrupt Source is R/W1C no need for read-modify-write.
- * GPIO's are aggregated meaning the NVIC Pending bit may be
- * set for another GPIO in the GIRQ. You can clear NVIC pending
- * and the hardware should re-assert it within one Cortex-M4 clock.
- * If the Cortex-M4 is clocked slower than AHB then the Cortex-M4
- * will take longer to register the interrupt. Not clearing NVIC
- * pending leave a pending status if only the GPIO this routine
- * clears is pending.
- * NVIC (system control) register space is strongly-ordered
- * Interrupt Aggregator is in Device space (system bus connected
- * to AHB) with the Cortex-M4 write buffer.
- * We need to insure the write to aggregator register in device
- * AHB space completes before NVIC pending is cleared.
- * The Cortex-M4 memory ordering rules imply Device access
- * comes before strongly ordered access. Cortex-M4 will not re-order
- * the writes. Due to the presence of the write buffer a DSB will
- * not guarantee the clearing of the device status completes. Add
- * a read back before clearing NVIC pending.
- * GIRQ 8, 9, 10, 11, 12, 26 map to NVIC inputs 0, 1, 2, 3, 4, and 18.
- */
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-
-	/* Clear interrupt source sticky status bit even if not enabled */
-	MCHP_INT_SOURCE(girq_id) = BIT(i);
-	i = MCHP_INT_SOURCE(girq_id);
-	task_clear_pending_irq(girq_id - 8);
-
-	return EC_SUCCESS;
-}
-
-/*
- * MCHP NOTE - called from main before scheduler started
- */
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		disable_bgpo(g->port, g->mask);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/* Clear any interrupt flags before enabling GPIO interrupt
- * Original code has flaws.
- * Writing result register to source only clears bits that have their
- * enable and sources bits set.
- * We must clear the NVIC pending R/W bit before setting NVIC enable.
- * NVIC Pending is only cleared by the NVIC HW on ISR entry.
- * Modifications are:
- * 1. Clear all status bits in each GPIO GIRQ. This assumes any edges
- *    will occur after gpio_init. The old code is also making this
- *    assumption for the GPIO's that have been enabled.
- * 2. Clear NVIC pending to prevent ISR firing on false edge.
- */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MCHP_INT_SOURCE(x) = 0xfffffffful; \
-		task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \
-		task_enable_irq(MCHP_IRQ_GIRQ ## x); \
-	} while (0)
-
-
-static void gpio_init(void)
-{
-	ENABLE_GPIO_GIRQ(8);
-	ENABLE_GPIO_GIRQ(9);
-	ENABLE_GPIO_GIRQ(10);
-	ENABLE_GPIO_GIRQ(11);
-	ENABLE_GPIO_GIRQ(12);
-	ENABLE_GPIO_GIRQ(26);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/************************************************************************/
-/* Interrupt handlers */
-
-
-/**
- * Handler for each GIRQ interrupt. This reads and clears the interrupt
- * bits for the GIRQ interrupt, then finds and calls the corresponding
- * GPIO interrupt handlers.
- *
- * @param girq		GIRQ index
- * @param port	zero based GPIO port number [0, 5]
- * @note __builtin_ffs(x) returns bitpos+1 of least significant 1-bit
- * in x or 0 if no bits are set.
- */
-static void gpio_interrupt(int girq, int port)
-{
-	int i, bit;
-	const struct gpio_info *g = gpio_list;
-	uint32_t sts = MCHP_INT_RESULT(girq);
-
-	/* RW1C, no need for read-modify-write */
-	MCHP_INT_SOURCE(girq) = sts;
-
-	trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts);
-	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x",
-		port, MCHP_GPIO_PARIN(port));
-
-	for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) {
-		if (g->port != port)
-			continue;
-
-		bit = __builtin_ffs(g->mask);
-		if (bit) {
-			bit--;
-			if (sts & BIT(bit)) {
-				trace12(0, GPIO, 0,
-					"Bit[%d]: handler @ 0x%08x", bit,
-					(uint32_t)gpio_irq_handlers[i]);
-				gpio_irq_handlers[i](i);
-			}
-			sts &= ~BIT(bit);
-		}
-	}
-}
-
-#define GPIO_IRQ_FUNC(irqfunc, girq, port)\
-	void irqfunc(void) \
-	{ \
-		gpio_interrupt(girq, port);\
-	}
-
-GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3);
-GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 2);
-GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 1);
-GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
-GPIO_IRQ_FUNC(__girq_12_interrupt, 12, 4);
-GPIO_IRQ_FUNC(__girq_26_interrupt, 26, 5);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(MCHP_IRQ_GIRQ8, __girq_8_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ9, __girq_9_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ10, __girq_10_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ11, __girq_11_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ12, __girq_12_interrupt, 1);
-DECLARE_IRQ(MCHP_IRQ_GIRQ26, __girq_26_interrupt, 1);
-
diff --git a/chip/mchp/gpio_chip.h b/chip/mchp/gpio_chip.h
deleted file mode 100644
index 7baaa76fa2..0000000000
--- a/chip/mchp/gpio_chip.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file gpio_chip.h
- *MEC GPIO module
- */
-/** @defgroup MEC gpio
- */
-
-#ifndef _GPIO_CHIP_H
-#define _GPIO_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "gpio.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-int gpio_power_off(enum gpio_signal signal);
-
-void gpio_power_off_by_mask(uint32_t port, uint32_t mask);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef _GPIO_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c
deleted file mode 100644
index cbf5f4c462..0000000000
--- a/chip/mchp/gpio_cmds.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP MEC GPIO module EC UART commands */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "util.h"
-#include "gpio_chip.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-
-
-static int cmd_gp_get_config(int argc, char **argv)
-{
-	char *e;
-	int i;
-	uint32_t gctrl;
-
-	/* If a signal is specified, print only that one */
-	if (argc == 2) {
-		i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		if (!gpio_is_implemented(i))
-			return EC_ERROR_PARAM1;
-
-		gctrl = MCHP_GPIO_CTRL(i);
-
-		ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-
-	} else { /* Otherwise print them all */
-		for (i = 0; i < GPIO_COUNT; i++) {
-			if (!gpio_is_implemented(i))
-				continue;  /* Skip unsupported signals */
-
-			gctrl = MCHP_GPIO_CTRL(i);
-
-			ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-		}
-	}
-
-	/* Flush console to avoid truncating output */
-	cflush();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config,
-			"[number]",
-			"Read GPIO config");
-
-static int cmd_gp_set_config(int argc, char **argv)
-{
-	char *e;
-	int i;
-	uint32_t gctrl;
-
-	/* If a signal is specified, print only that one */
-	if (argc > 2) {
-		i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		if (!gpio_is_implemented(i))
-			return EC_ERROR_PARAM1;
-
-		gctrl = (uint32_t)strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		MCHP_GPIO_CTRL(i) = gctrl;
-		gctrl = MCHP_GPIO_CTRL(i);
-		ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl);
-
-	} else {
-		ccprintf(" Requires two parameters: GPIO num and new config");
-	}
-	/* Flush console to avoid truncating output */
-	cflush();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config,
-			"gp_num val",
-			"Set GPIO config");
-
diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c
deleted file mode 100644
index 5234db8260..0000000000
--- a/chip/mchp/gpspi.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* General Purpose SPI master module for MCHP MEC */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "spi_chip.h"
-#include "gpspi_chip.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-/* One byte at 12 MHz full duplex = 0.67 us */
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
-
-/*
- * GP-SPI
- */
-
-/**
- * Return zero based GPSPI controller index given hardware port.
- * @param hw_port b[7:4]==1 (GPSPI), b[3:0]=0(GPSPI0), 1(GPSPI1)
- * @return 0(GPSPI0) or 1(GPSPI1)
- */
-static uint8_t gpspi_port_to_ctrl_id(uint8_t hw_port)
-{
-	return (hw_port & 0x01);
-}
-
-static int gpspi_wait_byte(const int ctrl)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	while ((MCHP_SPI_SR(ctrl) & 0x3) != 0x3) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-/* NOTE: auto-read must be disabled before calling this routine! */
-static void gpspi_rx_fifo_clean(const int ctrl)
-{
-	uint8_t unused = 0;
-
-	/* If ACTIVE and/or RXFF then clean it */
-	if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4)
-		unused += MCHP_SPI_RD(ctrl);
-
-	if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2)
-		unused += MCHP_SPI_RD(ctrl);
-}
-/*
- * NOTE: auto-read must be disabled before calling this routine!
- */
-#ifndef CONFIG_MCHP_GPSPI_TX_DMA
-static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
-{
-	int i;
-	int ret;
-	uint8_t unused = 0;
-
-	gpspi_rx_fifo_clean(ctrl);
-
-	ret = EC_SUCCESS;
-	for (i = 0; i < txlen; ++i) {
-		MCHP_SPI_TD(ctrl) = txdata[i];
-		ret = gpspi_wait_byte(ctrl);
-		if (ret != EC_SUCCESS)
-			break;
-		unused += MCHP_SPI_RD(ctrl);
-	}
-
-	return ret;
-}
-#endif
-
-int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	int hw_port, ctrl;
-	int ret = EC_SUCCESS;
-	int cs_asserted = 0;
-	const struct dma_option *opdma;
-#ifdef CONFIG_MCHP_GPSPI_TX_DMA
-	dma_chan_t *chan;
-#endif
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	hw_port = spi_device->port;
-
-	ctrl = gpspi_port_to_ctrl_id(hw_port);
-
-	/* Disable auto read */
-	MCHP_SPI_CR(ctrl) &= ~BIT(5);
-
-	if ((txdata != NULL) && (txdata != 0)) {
-#ifdef CONFIG_MCHP_GPSPI_TX_DMA
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-		if (opdma == NULL)
-			return EC_ERROR_INVAL;
-
-		gpspi_rx_fifo_clean(ctrl);
-
-		dma_prepare_tx(opdma, txlen, txdata);
-
-		chan = dma_get_channel(opdma->channel);
-
-		gpio_set_level(spi_device->gpio_cs, 0);
-		cs_asserted = 1;
-
-		dma_go(chan);
-		ret = dma_wait(opdma->channel);
-		if (ret == EC_SUCCESS)
-			ret = gpspi_wait_byte(ctrl);
-
-		dma_disable(opdma->channel);
-		dma_clear_isr(opdma->channel);
-
-		gpspi_rx_fifo_clean(ctrl);
-#else
-		gpio_set_level(spi_device->gpio_cs, 0);
-		cs_asserted = 1;
-
-		ret = gpspi_tx(ctrl, txdata, txlen);
-#endif
-	}
-
-	if (ret == EC_SUCCESS)
-		if ((rxlen != 0) && (rxdata != NULL)) {
-			ret = EC_ERROR_INVAL;
-			opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-			if (opdma != NULL) {
-				if (!cs_asserted)
-					gpio_set_level(spi_device->gpio_cs, 0);
-				/* Enable auto read */
-				MCHP_SPI_CR(ctrl) |= BIT(5);
-				dma_start_rx(opdma, rxlen, rxdata);
-				MCHP_SPI_TD(ctrl) = 0;
-				ret = EC_SUCCESS;
-			}
-		}
-
-	return ret;
-}
-
-int gpspi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int ctrl, hw_port;
-	int ret;
-	enum dma_channel chan;
-	const struct dma_option *opdma;
-	timestamp_t deadline;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	hw_port = spi_device->port;
-	ctrl = gpspi_port_to_ctrl_id(hw_port);
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	chan = opdma->channel;
-
-	ret = dma_wait(chan);
-
-	/* Disable auto read */
-	MCHP_SPI_CR(ctrl) &= ~BIT(5);
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	/* Wait for FIFO empty SPISR_TXBE */
-	while ((MCHP_SPI_SR(ctrl) & 0x01) != 0x1) {
-		if (timestamp_expired(deadline, NULL)) {
-			ret = EC_ERROR_TIMEOUT;
-			break;
-		}
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-
-	dma_disable(chan);
-	dma_clear_isr(chan);
-	if (MCHP_SPI_SR(ctrl) & 0x2)
-		hw_port = MCHP_SPI_RD(ctrl);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return ret;
-}
-
-int gpspi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	const struct dma_option *opdma;
-
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-
-	return dma_wait(opdma->channel);
-}
-
-/**
- * Enable GPSPI controller and MODULE_SPI_CONTROLLER pins
- *
- * @param hw_port b[7:4]=1 b[3:0]=0(GPSPI0), 1(GPSPI1)
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called from mec1701/spi.c
- *
- */
-int gpspi_enable(int hw_port, int enable)
-{
-	uint32_t ctrl;
-
-	if ((hw_port != GPSPI0_PORT) && (hw_port != GPSPI1_PORT))
-		return EC_ERROR_INVAL;
-
-	gpio_config_module(MODULE_SPI_CONTROLLER, (enable > 0));
-
-	ctrl = (uint32_t)hw_port & 0x0f;
-
-	if (enable) {
-
-		if (ctrl)
-			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1);
-		else
-			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI0);
-
-		/* Set enable bit in SPI_AR */
-		MCHP_SPI_AR(ctrl) |= 0x1;
-
-		/* Set SPDIN to 0 -> Full duplex */
-		MCHP_SPI_CR(ctrl) &= ~(0x3 << 2);
-
-		/* Set CLKPOL, TCLKPH, RCLKPH to 0 */
-		MCHP_SPI_CC(ctrl) &= ~0x7;
-
-		/* Set LSBF to 0 -> MSB first */
-		MCHP_SPI_CR(ctrl) &= ~0x1;
-	} else {
-		/* soft reset */
-		MCHP_SPI_CR(ctrl) |= (1u << 4);
-
-		/* Clear enable bit in SPI_AR */
-		MCHP_SPI_AR(ctrl) &= ~0x1;
-
-		if (ctrl)
-			MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI1);
-		else
-			MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI0);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h
deleted file mode 100644
index 529a727e36..0000000000
--- a/chip/mchp/gpspi_chip.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file gpspi_chip.h
- *MCHP MEC General Purpose SPI Master
- */
-/** @defgroup MCHP MEC gpspi
- */
-
-#ifndef _GPSPI_CHIP_H
-#define _GPSPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-int gpspi_transaction_flush(const struct spi_device_t *spi_device);
-
-int gpspi_transaction_wait(const struct spi_device_t *spi_device);
-
-int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int gpspi_enable(int port, int enable);
-
-#endif /* #ifndef _GPSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c
deleted file mode 100644
index e84f278f4a..0000000000
--- a/chip/mchp/hwtimer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "tfdp_chip.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
-	MCHP_TMR32_CTL(1) |= BIT(5);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return MCHP_TMR32_CNT(1) - MCHP_TMR32_CNT(0) + 0xffffffff;
-}
-
-void __hw_clock_event_clear(void)
-{
-	MCHP_TMR32_CTL(1) &= ~BIT(5);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - MCHP_TMR32_CNT(0);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	MCHP_TMR32_CTL(0) &= ~BIT(5);
-	MCHP_TMR32_CNT(0) = 0xffffffff - ts;
-	MCHP_TMR32_CTL(0) |= BIT(5);
-}
-
-/*
- * Always clear both timer and aggregator status
- */
-static void __hw_clock_source_irq(int timer_id)
-{
-	MCHP_TMR32_STS(timer_id & 0x01) |= 1;
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
-
-	/* If IRQ is from timer 0, 32-bit timer overflowed */
-	process_timers(timer_id == 0);
-}
-
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
-DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
-DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
-
-static void configure_timer(int timer_id)
-{
-	uint32_t val;
-
-	/* Ensure timer is not running */
-	MCHP_TMR32_CTL(timer_id) &= ~BIT(5);
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(timer_id) |= BIT(0);
-
-	val = MCHP_TMR32_CTL(timer_id);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MCHP_TMR32_CTL(timer_id) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MCHP_TMR32_PRE(timer_id) = 0xffffffff;
-
-	/* Enable interrupt */
-	MCHP_TMR32_IEN(timer_id) |= 1;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 +
-			MCHP_PCR_SLP_EN3_BTMR32_1);
-
-	/*
-	 * The timer can only fire interrupt when its value reaches zero.
-	 * Therefore we need two timers:
-	 *   - Timer 0 as free running timer
-	 *   - Timer 1 as event timer
-	 */
-	configure_timer(0);
-	configure_timer(1);
-
-	/* Override the count */
-	MCHP_TMR32_CNT(0) = 0xffffffff - start_t;
-
-	/* Auto restart */
-	MCHP_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MCHP_TMR32_CTL(0) |= BIT(5);
-
-	/* Enable interrupt */
-	task_enable_irq(MCHP_IRQ_TIMER32_0);
-	task_enable_irq(MCHP_IRQ_TIMER32_1);
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	/*
-	 * Not needed when using direct mode interrupts
-	 * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ);
-	 */
-	return MCHP_IRQ_TIMER32_1;
-}
diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
deleted file mode 100644
index 9891f4d41e..0000000000
--- a/chip/mchp/i2c.c
+++ /dev/null
@@ -1,1096 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for MCHP MEC */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "tfdp_chip.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
-
-/*
- * MCHP I2C BAUD clock source is 16 MHz.
- */
-#define I2C_CLOCK			16000000UL
-#define MCHP_I2C_SUPPORTED_BUS_CLOCKS	6
-
-/* SMBus Timing values for 1MHz Speed */
-#define SPEED_1MHZ_BUS_CLOCK		0x0509ul
-#define SPEED_1MHZ_DATA_TIMING		0x06060601ul
-#define SPEED_1MHZ_DATA_TIMING_2	0x06ul
-#define SPEED_1MHZ_IDLE_SCALING		0x01000050ul
-#define SPEED_1MHZ_TIMEOUT_SCALING	0x149CC2C7ul
-/* SMBus Timing values for 400kHz speed */
-#define SPEED_400KHZ_BUS_CLOCK		0x0F17ul
-#define SPEED_400KHZ_DATA_TIMING	0x040A0F01ul
-#define SPEED_400KHZ_DATA_TIMING_2	0x0Aul
-#define SPEED_400KHZ_IDLE_SCALING	0x01000050ul
-#define SPEED_400KHZ_TIMEOUT_SCALING	0x149CC2C7ul
-/* SMBus Timing values for 100kHz speed */
-#define SPEED_100KHZ_BUS_CLOCK		0x4F4Ful
-#define SPEED_100KHZ_DATA_TIMING	0x0C4D4306ul
-#define SPEED_100KHZ_DATA_TIMING_2	0x4Dul
-#define SPEED_100KHZ_IDLE_SCALING	0x01FC01EDul
-#define SPEED_100KHZ_TIMEOUT_SCALING	0x4B9CC2C7ul
-/* Bus clock dividers for 333, 80, and 40 kHz */
-#define SPEED_333KHZ_BUS_CLOCK		0x0F1Ful
-#define SPEED_80KHZ_BUS_CLOCK		0x6363ul
-#define SPEED_40KHZ_BUS_CLOCK		0xC7C7ul
-
-/* Status */
-#define STS_NBB			BIT(0) /* Bus busy */
-#define STS_LAB			BIT(1) /* Arbitration lost */
-#define STS_LRB			BIT(3) /* Last received bit */
-#define STS_BER			BIT(4) /* Bus error */
-#define STS_PIN			BIT(7) /* Pending interrupt */
-/* Control */
-#define CTRL_ACK		BIT(0) /* Acknowledge */
-#define CTRL_STO		BIT(1) /* STOP */
-#define CTRL_STA		BIT(2) /* START */
-#define CTRL_ENI		BIT(3) /* Enable interrupt */
-#define CTRL_ESO		BIT(6) /* Enable serial output */
-#define CTRL_PIN		BIT(7) /* Pending interrupt not */
-/* Completion */
-#define COMP_DTEN		BIT(2) /* enable device timeouts */
-#define COMP_MCEN		BIT(3) /* enable ctrl. cumulative timeouts */
-#define COMP_SCEN		BIT(4) /* enable periph. cumulative timeouts */
-#define COMP_BIDEN		BIT(5) /* enable Bus idle timeouts */
-#define COMP_IDLE		BIT(29) /* i2c bus is idle */
-#define COMP_RW_BITS_MASK	0x3C /* R/W bits mask */
-/* Configuration */
-#define CFG_PORT_MASK		(0x0F) /* port selection field */
-#define CFG_TCEN		BIT(4) /* Enable HW bus timeouts */
-#define CFG_FEN			BIT(8) /* enable input filtering */
-#define CFG_RESET		BIT(9) /* reset controller */
-#define CFG_ENABLE		BIT(10) /* enable controller */
-#define CFG_GC_DIS		BIT(14) /* disable general call address */
-#define CFG_ENIDI		BIT(29) /* Enable I2C idle interrupt */
-/* Enable network layer controller done interrupt */
-#define CFG_ENMI		BIT(30)
-/* Enable network layer peripheral done interrupt */
-#define CFG_ENSI		BIT(31)
-/* Controller Command */
-#define MCMD_MRUN		BIT(0)
-#define MCMD_MPROCEED		BIT(1)
-#define MCMD_START0		BIT(8)
-#define MCMD_STARTN		BIT(9)
-#define MCMD_STOP		BIT(10)
-#define MCMD_READM		BIT(12)
-#define MCMD_WCNT_BITPOS	(16)
-#define MCMD_WCNT_MASK0		(0xFF)
-#define MCMD_WCNT_MASK		(0xFF << 16)
-#define MCMD_RCNT_BITPOS	(24)
-#define MCMD_RCNT_MASK0		(0xFF)
-#define MCMD_RCNT_MASK		(0xFF << 24)
-
-/* Maximum transfer of a SMBUS block transfer */
-#define SMBUS_MAX_BLOCK_SIZE 32
-/*
- * Amount of time to blocking wait for i2c bus to finish. After this
- * blocking timeout, if the bus is still not finished, then allow other
- * tasks to run.
- * Note: this is just long enough for a 400kHz bus to finish transmitting
- * one byte assuming the bus isn't being held.
- */
-#define I2C_WAIT_BLOCKING_TIMEOUT_US 25
-
-enum i2c_transaction_state {
-	/* Stop condition was sent in previous transaction */
-	I2C_TRANSACTION_STOPPED,
-	/* Stop condition was not sent in previous transaction */
-	I2C_TRANSACTION_OPEN,
-};
-
-/* I2C controller state data
- * NOTE: I2C_CONTROLLER_COUNT is defined at board level.
- */
-static struct {
-	/* Transaction timeout, or 0 to use default. */
-	uint32_t timeout_us;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	/*
-	 * MCHP Remove volatile.
-	 * ISR only reads.
-	 * Non-ISR only writes when interrupt is disabled.
-	 */
-	task_id_t task_waiting;
-	enum i2c_transaction_state transaction_state;
-	/* transaction context */
-	int out_size;
-	const uint8_t *outp;
-	int in_size;
-	uint8_t *inp;
-	int xflags;
-	uint32_t i2c_complete; /* ISR write */
-	uint32_t flags;
-	uint8_t port;
-	uint8_t periph_addr_8bit;
-	uint8_t ctrl;
-	uint8_t hwsts;
-	uint8_t hwsts2;
-	uint8_t hwsts3; /* ISR write */
-	uint8_t hwsts4;
-	uint8_t lines;
-} cdata[I2C_CONTROLLER_COUNT];
-
-static const uint16_t i2c_ctrl_nvic_id[] = {
-	MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_IRQ_I2C_4
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX);
-
-static const uint16_t i2c_controller_pcr[] = {
-	MCHP_PCR_I2C0, MCHP_PCR_I2C1, MCHP_PCR_I2C2, MCHP_PCR_I2C3,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_PCR_I2C4
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX);
-
-static uintptr_t i2c_ctrl_base_addr[] = {
-	MCHP_I2C0_BASE, MCHP_I2C1_BASE, MCHP_I2C2_BASE, MCHP_I2C3_BASE,
-#if defined(CHIP_FAMILY_MEC172X)
-	MCHP_I2C4_BASE
-#elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_I2C4_BASE,
-	/* NOTE: 5-7 do not implement network layer hardware */
-	MCHP_I2C5_BASE, MCHP_I2C6_BASE, MCHP_I2C7_BASE
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX);
-
-static bool chip_i2c_is_controller_valid(int controller)
-{
-	if ((controller < 0) || (controller >= MCHP_I2C_CTRL_MAX))
-		return false;
-	return true;
-}
-
-static uintptr_t chip_i2c_ctrl_base(int controller)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-
-	return i2c_ctrl_base_addr[controller];
-}
-
-static uint32_t chip_i2c_ctrl_nvic_id(int controller)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-
-	return (uint32_t)i2c_ctrl_nvic_id[controller];
-}
-
-static void i2c_ctrl_slp_en(int controller, int sleep_en)
-{
-	if (!chip_i2c_is_controller_valid(controller))
-		return;
-	if (sleep_en)
-		MCHP_PCR_SLP_EN_DEV(i2c_controller_pcr[controller]);
-	else
-		MCHP_PCR_SLP_DIS_DEV(i2c_controller_pcr[controller]);
-}
-
-uint32_t chip_i2c_get_ctx_flags(int port)
-{
-	int controller = i2c_port_to_controller(port);
-
-	if (!chip_i2c_is_controller_valid(controller))
-		return 0;
-	return cdata[controller].flags;
-}
-
-/*
- * MCHP I2C controller tuned bus clock values.
- * MCHP I2C_SMB_Controller_3.6.pdf Table 6-3
- */
-struct i2c_bus_clk {
-	int freq_khz;
-	int bus_clk;
-};
-
-const struct i2c_bus_clk i2c_freq_tbl[] = {
-	{ 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK },
-	{ 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK },
-	{ 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK },
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_freq_tbl) == MCHP_I2C_SUPPORTED_BUS_CLOCKS);
-
-/* I2C controller assignment to a port */
-static int i2c_p2c[MCHP_I2C_PORT_COUNT];
-
-static int get_closest(int lesser, int greater, int target)
-{
-	if (target - i2c_freq_tbl[lesser].freq_khz >=
-	    i2c_freq_tbl[greater].freq_khz - target)
-		return greater;
-	else
-		return lesser;
-}
-
-/*
- * Return index in i2c_freq_tbl of supported frequencies
- * closest to requested frequency.
- */
-static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps)
-{
-	int i, limit, m, imax;
-
-	if (req_kbps <= i2c_freq_tbl[0].freq_khz)
-		return &i2c_freq_tbl[0];
-
-	imax = ARRAY_SIZE(i2c_freq_tbl);
-	if (req_kbps >= i2c_freq_tbl[imax - 1].freq_khz)
-		return &i2c_freq_tbl[imax - 1];
-
-	/* we only get here if ARRAY_SIZE(...) > 1
-	 * and req_kbps is in range.
-	 */
-	i = 0;
-	limit = imax;
-	while (i < limit) {
-		m = (i + limit) / 2;
-		if (i2c_freq_tbl[m].freq_khz == req_kbps)
-			break;
-
-		if (req_kbps < i2c_freq_tbl[m].freq_khz) {
-			if (m > 0 && req_kbps > i2c_freq_tbl[m - 1].freq_khz) {
-				m = get_closest(m - 1, m, req_kbps);
-				break;
-			}
-			limit = m;
-		} else {
-			if (m < imax - 1 &&
-			    req_kbps < i2c_freq_tbl[m + 1].freq_khz) {
-				m = get_closest(m, m + 1, req_kbps);
-				break;
-			}
-			i = m + 1;
-		}
-	}
-
-	return &i2c_freq_tbl[m];
-}
-
-/*
- * Refer to NXP UM10204 for minimum timing requirement of T_Low and T_High.
- * http://www.nxp.com/documents/user_manual/UM10204.pdf
- * I2C spec. timing value are used in recommended registers values
- * in MCHP I2C_SMB_Controller_3.6.pdf
- * Restrict frequencies to those in the above MCHP spec.
- * 40, 80, 100, 333, 400, and 1000 kHz.
- */
-static void configure_controller_speed(int controller, int kbps)
-{
-	const struct i2c_bus_clk *p;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-
-	p = get_supported_speed_idx(kbps);
-	MCHP_I2C_BUS_CLK(raddr) = p->bus_clk;
-
-	if (p->freq_khz > 400) { /* Fast mode plus */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_1MHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_1MHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_1MHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_1MHZ_TIMEOUT_SCALING;
-	} else if (p->freq_khz > 100) { /* Fast mode */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_400KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_400KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_400KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_400KHZ_TIMEOUT_SCALING;
-	} else { /* Standard mode */
-		MCHP_I2C_DATA_TIM(raddr) = SPEED_100KHZ_DATA_TIMING;
-		MCHP_I2C_DATA_TIM_2(raddr) = SPEED_100KHZ_DATA_TIMING_2;
-		MCHP_I2C_IDLE_SCALE(raddr) = SPEED_100KHZ_IDLE_SCALING;
-		MCHP_I2C_TOUT_SCALE(raddr) = SPEED_100KHZ_TIMEOUT_SCALING;
-	}
-}
-
-/*
- * NOTE: direct mode interrupts do not need GIRQn bit
- * set in aggregator block enable register.
- */
-static void enable_controller_irq(int controller)
-{
-	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
-
-	MCHP_INT_ENABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-	task_enable_irq(nvic_id);
-}
-
-static void disable_controller_irq(int controller)
-{
-	uint32_t nvic_id = chip_i2c_ctrl_nvic_id(controller);
-
-	MCHP_INT_DISABLE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-	/* read back into read-only reg. to insure disable takes effect */
-	MCHP_INT_BLK_IRQ = MCHP_INT_DISABLE(MCHP_I2C_GIRQ);
-	task_disable_irq(nvic_id);
-	task_clear_pending_irq(nvic_id);
-}
-
-/*
- * Do NOT enable controller's IDLE interrupt in the configuration
- * register. IDLE is meant for multi-controller and controller acting
- * as a peripheral.
- */
-static void configure_controller(int controller, int port, int kbps)
-{
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-
-	if (raddr == 0)
-		return;
-
-	disable_controller_irq(controller);
-	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-
-	/* set to default except for port select field b[3:0] */
-	MCHP_I2C_CONFIG(raddr) = (uint32_t)(port & 0xf);
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN;
-
-	/* Set both controller peripheral addresses to 0 the
-	 * general call address. We disable general call
-	 * below.
-	 */
-	MCHP_I2C_OWN_ADDR(raddr) = 0;
-
-	configure_controller_speed(controller, kbps);
-
-	/* Controller timings done, clear RO status, enable
-	 * output, and ACK generation.
-	 */
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ACK;
-
-	/* filter enable, disable General Call */
-	MCHP_I2C_CONFIG(raddr) |= CFG_FEN + CFG_GC_DIS;
-	/* enable controller */
-	MCHP_I2C_CONFIG(raddr) |= CFG_ENABLE;
-}
-
-static void reset_controller(int controller)
-{
-	int i;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	if (raddr == 0)
-		return;
-
-	/* Reset asserted for at least one AHB clock */
-	MCHP_I2C_CONFIG(raddr) |= BIT(9);
-	MCHP_EC_ID_RO = 0;
-	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
-
-	for (i = 0; i < i2c_ports_used; ++i)
-		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
-			configure_controller(controller, i2c_ports[i].port,
-					     i2c_ports[i].kbps);
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-			break;
-		}
-}
-
-/*
- * !!! WARNING !!!
- * We have observed task_wait_event_mask() returning 0 if the I2C
- * controller IDLE interrupt is enabled. We believe it is due to the ISR
- * post multiple events too quickly but don't have absolute proof.
- */
-static int wait_for_interrupt(int controller, int timeout)
-{
-	int event;
-
-	if (timeout <= 0)
-		return EC_ERROR_TIMEOUT;
-
-	cdata[controller].task_waiting = task_get_current();
-	enable_controller_irq(controller);
-
-	/* Wait until I2C interrupt or timeout. */
-	event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout);
-
-	disable_controller_irq(controller);
-	cdata[controller].task_waiting = TASK_ID_INVALID;
-
-	return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS;
-}
-
-static int wait_idle(int controller)
-{
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-	uint8_t sts = MCHP_I2C_STATUS(raddr);
-
-	while (!(sts & STS_NBB)) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MCHP_I2C_STATUS(raddr);
-	}
-
-	if (sts & (STS_BER | STS_LAB))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-/*
- * Return EC_SUCCESS on ACK of byte else EC_ERROR_UNKNOWN.
- * Record I2C.Status in cdata[controller] structure.
- * Byte transmit finished with no I2C bus error or lost arbitration.
- *	PIN -> 0. LRB bit contains peripheral ACK/NACK bit.
- *	Peripheral ACK:  I2C.Status == 0x00
- *	Peripheral NACK: I2C.Status == 0x08
- * Byte transmit finished with I2C bus errors or lost arbitration.
- *	PIN -> 0 and BER and/or LAB set.
- *
- * Byte receive finished with no I2C bus errors or lost arbitration.
- *	PIN -> 0. LRB=0/1 based on ACK bit in I2C.Control.
- *	Controller receiver must NACK last byte it wants to receive.
- *	How do we handle this if we don't know direction of transfer?
- *	I2C.Control is write-only so we can't see Controller's ACK control
- *	bit.
- */
-static int wait_byte_done(int controller, uint8_t mask, uint8_t expected)
-{
-	uint64_t block_timeout;
-	uint64_t task_timeout;
-	uintptr_t raddr;
-	int rv;
-	uint8_t sts;
-
-	rv = 0;
-	raddr = chip_i2c_ctrl_base(controller);
-	block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	task_timeout = block_timeout + cdata[controller].timeout_us;
-	sts = MCHP_I2C_STATUS(raddr);
-	cdata[controller].hwsts = sts;
-	while (sts & STS_PIN) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout) {
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		}
-		sts = MCHP_I2C_STATUS(raddr);
-		cdata[controller].hwsts = sts;
-	}
-
-	rv = EC_SUCCESS;
-	if ((sts & mask) != expected)
-		rv = EC_ERROR_UNKNOWN;
-	return rv;
-}
-
-/*
- * Select port on controller. If controller configured
- * for port do nothing.
- * Switch port by reset and reconfigure to handle cases where
- * the peripheral on current port is driving line(s) low.
- * NOTE: I2C hardware reset only requires one AHB clock, back to back
- * writes is OK but we added an extra write as insurance.
- */
-static void select_port(int port, int controller)
-{
-	uint32_t port_sel;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	port_sel = (uint32_t)(port & 0x0f);
-	if ((MCHP_I2C_CONFIG(raddr) & 0x0f) == port_sel)
-		return;
-
-	MCHP_I2C_CONFIG(raddr) |= BIT(9);
-	MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */
-	MCHP_I2C_CONFIG(raddr) &= ~BIT(9);
-	configure_controller(controller, port_sel, i2c_ports[port].kbps);
-}
-
-/*
- * Use safe method (reading GPIO.Control PAD input bit)
- * to obtain SCL line state in bit[0] and SDA line state in bit[1].
- * NOTE: I2C controller bit-bang register is not safe. Using
- * bit-bang requires timeouts be disabled and the controller in an
- * idle state. Switching controller to bit-bang mode when the controller
- * is not idle will cause problems.
- */
-static uint32_t get_line_level(int port)
-{
-	uint32_t lines;
-
-	lines = i2c_raw_get_scl(port) & 0x01;
-	lines |= (i2c_raw_get_sda(port) & 0x01) << 1;
-	return lines;
-}
-
-/*
- * Check if I2C port connected to controller has bus error or
- * other issues such as stuck clock/data lines.
- */
-static int i2c_check_recover(int port, int controller)
-{
-	uintptr_t raddr;
-	uint32_t lines;
-	uint8_t reg;
-
-	raddr = chip_i2c_ctrl_base(controller);
-	lines = get_line_level(port);
-	reg = MCHP_I2C_STATUS(raddr);
-
-	if ((((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-	     (lines != I2C_LINE_IDLE))) {
-		cdata[controller].flags |= (1ul << 16);
-		CPRINTS("I2C%d port%d recov status 0x%02x, SDA:SCL=0x%0x",
-			controller, port, reg, lines);
-		/* Attempt to unwedge the port. */
-		if (lines != I2C_LINE_IDLE)
-			if (i2c_unwedge(port))
-				return EC_ERROR_UNKNOWN;
-
-		/* Bus error, bus busy, or arbitration lost. Try reset. */
-		reset_controller(controller);
-		select_port(port, controller);
-		/*
-		 * We don't know what edges the peripheral saw, so sleep long
-		 * enough that the peripheral will see the new start condition
-		 * below.
-		 */
-		usleep(1000);
-		reg = MCHP_I2C_STATUS(raddr);
-		lines = get_line_level(port);
-		if ((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB) ||
-		    (lines != I2C_LINE_IDLE))
-			return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
-{
-	if (!skip) {
-		**in = val;
-		(*in)++;
-	}
-}
-
-/*
- * I2C Controller transmit
- * Caller has filled in cdata[ctrl] parameters
- */
-static int i2c_mtx(int ctrl)
-{
-	uintptr_t raddr;
-	int i, rv;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-	rv = EC_SUCCESS;
-	cdata[ctrl].flags |= (1ul << 1);
-	if (cdata[ctrl].xflags & I2C_XFER_START) {
-		cdata[ctrl].flags |= (1ul << 2);
-		MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit;
-		/* Clock out the peripheral address, sending START bit */
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-				       CTRL_ACK | CTRL_STA;
-		cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
-	}
-
-	for (i = 0; i < cdata[ctrl].out_size; ++i) {
-		rv = wait_byte_done(ctrl, 0xff, 0x00);
-		if (rv) {
-			cdata[ctrl].flags |= (1ul << 17);
-			MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-					      CTRL_STO | CTRL_ACK;
-			return rv;
-		}
-		cdata[ctrl].flags |= (1ul << 15);
-		MCHP_I2C_DATA(raddr) = cdata[ctrl].outp[i];
-	}
-
-	rv = wait_byte_done(ctrl, 0xff, 0x00);
-	if (rv) {
-		cdata[ctrl].flags |= (1ul << 18);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_ENI |
-				       CTRL_STO | CTRL_ACK;
-		return rv;
-	}
-
-	/*
-	 * Send STOP bit if the stop flag is on, and caller
-	 * doesn't expect to receive data.
-	 */
-	if ((cdata[ctrl].xflags & I2C_XFER_STOP) &&
-	    (cdata[ctrl].in_size == 0)) {
-		cdata[ctrl].flags |= (1ul << 3);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-				       CTRL_ACK;
-		cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
-	}
-	return rv;
-}
-
-/*
- * I2C Controller-Receive helper routine for sending START or
- * Repeated-START.
- * This routine should only be called if a (Repeated-)START
- * is required.
- * If I2C controller is Idle or Stopped
- *   Send START by:
- *	Write read address to I2C.Data
- *	Write PIN=ESO=STA=ACK=1, STO=0 to I2C.Ctrl. This
- *	will trigger controller to output 8-bits of data.
- * Else if I2C controller is Open (previous START sent)
- *   Send Repeated-START by:
- *	Write ESO=STA=ACK=1, PIN=STO=0 to I2C.Ctrl. Controller
- *	will generate START but not transmit data.
- *	Write read address to I2C.Data. Controller will transmit
- *	8-bits of data
- * NOTE: Controller clocks in address on SDA as its transmitting.
- * Therefore 1-byte RX-FIFO will contain address plus R/nW bit.
- * Controller will wait for peripheral to release SCL before transmitting
- * 9th clock and latching (N)ACK on SDA.
- * Spin on I2C.Status PIN -> 0. Enable I2C interrupt if spin time
- * exceeds threshold. If a timeout occurs generate STOP and return
- * an error.
- *
- * Because I2C generates clocks for next byte when reading I2C.Data
- * register we must prepare control logic.
- * If the caller requests STOP and read length is 1 then set
- * clear ACK bit in I2C.Ctrl. Set ESO=ENI=1, PIN=STA=STO=ACK=0
- * in I2C.Ctrl. Controller must NACK last byte.
- */
-static int i2c_mrx_start(int ctrl)
-{
-	uintptr_t raddr;
-	int rv;
-	uint8_t u8;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-
-	cdata[ctrl].flags |= (1ul << 4);
-	u8 = CTRL_ESO | CTRL_ENI | CTRL_STA | CTRL_ACK;
-	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_OPEN) {
-		cdata[ctrl].flags |= (1ul << 5);
-		/* Repeated-START then address */
-		MCHP_I2C_CTRL(raddr) = u8;
-	}
-	MCHP_I2C_DATA(raddr) = cdata[ctrl].periph_addr_8bit | 0x01;
-	if (cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
-		cdata[ctrl].flags |= (1ul << 6);
-		/* address then START */
-		MCHP_I2C_CTRL(raddr) = u8 | CTRL_PIN;
-	}
-	cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN;
-	/* Controller generates START, transmits data(address) capturing
-	 * 9-bits from SDA (8-bit address + (N)Ack bit).
-	 * We leave captured address in I2C.Data register.
-	 * Controller receive data read routine assumes data is pending
-	 * in I2C.Data
-	 */
-	cdata[ctrl].flags |= (1ul << 7);
-	rv = wait_byte_done(ctrl, 0xff, 0x00);
-	if (rv) {
-		cdata[ctrl].flags |= (1ul << 19);
-		MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-				       CTRL_ACK;
-		return rv;
-	}
-	/* if STOP requested and last 1 or 2 bytes prepare controller
-	 * to NACK last byte. Do this before read of extra data so
-	 * controller is setup to NACK last byte.
-	 */
-	cdata[ctrl].flags |= (1ul << 8);
-	if (cdata[ctrl].xflags & I2C_XFER_STOP && (cdata[ctrl].in_size < 2)) {
-		cdata[ctrl].flags |= (1ul << 9);
-		MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
-	}
-	/*
-	 * Read & discard peripheral address.
-	 * Generates clocks for next data
-	 */
-	cdata[ctrl].flags |= (1ul << 10);
-	u8 = MCHP_I2C_DATA(raddr);
-	return rv;
-}
-/*
- * I2C Controller-Receive data read helper.
- * Assumes I2C is in use, (Rpt-)START was previously sent.
- * Reading I2C.Data generates clocks for the next byte. If caller
- * requests STOP then we must clear I2C.Ctrl ACK before reading
- * second to last byte from RX-FIFO data register. Before reading
- * the last byte we must set I2C.Ctrl to generate a stop after
- * the read from RX-FIFO register.
- * NOTE: I2C.Status.LRB only records the (N)ACK bit in controller
- * transmit mode, not in controller receive mode.
- * NOTE2: Do not set ENI bit in I2C.Ctrl for STOP generation.
- */
-static int i2c_mrx_data(int ctrl)
-{
-	uint32_t nrx = (uint32_t)cdata[ctrl].in_size;
-	uint32_t stop = (uint32_t)cdata[ctrl].xflags & I2C_XFER_STOP;
-	uint8_t *pdest = cdata[ctrl].inp;
-	int rv;
-	uintptr_t raddr;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-
-	cdata[ctrl].flags |= (1ul << 11);
-	while (nrx) {
-		rv = wait_byte_done(ctrl, 0xff, 0x00);
-		if (rv) {
-			cdata[ctrl].flags |= (1ul << 20);
-			MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO |
-					       CTRL_ACK;
-			return rv;
-		}
-		if (stop) {
-			if (nrx == 2) {
-				cdata[ctrl].flags |= (1ul << 12);
-				MCHP_I2C_CTRL(raddr) = CTRL_ESO | CTRL_ENI;
-			} else if (nrx == 1) {
-				cdata[ctrl].flags |= (1ul << 13);
-				MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO |
-						       CTRL_STO | CTRL_ACK;
-			}
-		}
-		*pdest++ = MCHP_I2C_DATA(raddr);
-		nrx--;
-	}
-	cdata[ctrl].flags |= (1ul << 14);
-	return EC_SUCCESS;
-}
-
-/*
- * Called from common I2C
- */
-int chip_i2c_xfer(int port, uint16_t periph_addr_flags, const uint8_t *out,
-		  int out_size, uint8_t *in, int in_size, int flags)
-{
-	int ctrl;
-	int ret_done;
-	uintptr_t raddr;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	ctrl = i2c_port_to_controller(port);
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	raddr = chip_i2c_ctrl_base(ctrl);
-	if (raddr == 0)
-		return EC_ERROR_INVAL;
-
-	cdata[ctrl].flags = (1ul << 0);
-	disable_controller_irq(ctrl);
-	select_port(port, ctrl);
-
-	/* store transfer context */
-	cdata[ctrl].i2c_complete = 0;
-	cdata[ctrl].hwsts = 0;
-	cdata[ctrl].hwsts2 = 0;
-	cdata[ctrl].hwsts3 = 0;
-	cdata[ctrl].hwsts4 = 0;
-	cdata[ctrl].port = port & 0xff;
-	cdata[ctrl].periph_addr_8bit = I2C_STRIP_FLAGS(periph_addr_flags) << 1;
-	cdata[ctrl].out_size = out_size;
-	cdata[ctrl].outp = out;
-	cdata[ctrl].in_size = in_size;
-	cdata[ctrl].inp = in;
-	cdata[ctrl].xflags = flags;
-
-	if ((flags & I2C_XFER_START) &&
-	    cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) {
-		wait_idle(ctrl);
-		ret_done = i2c_check_recover(port, ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	ret_done = EC_SUCCESS;
-	if (out_size) {
-		ret_done = i2c_mtx(ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	if (in_size) {
-		if (cdata[ctrl].xflags & I2C_XFER_START) {
-			ret_done = i2c_mrx_start(ctrl);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-		}
-		ret_done = i2c_mrx_data(ctrl);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-	}
-
-	cdata[ctrl].flags |= (1ul << 15);
-	/* MCHP wait for STOP to complete */
-	if (cdata[ctrl].xflags & I2C_XFER_STOP)
-		wait_idle(ctrl);
-
-	/* Check for error conditions */
-	if (MCHP_I2C_STATUS(raddr) & (STS_LAB | STS_BER)) {
-		cdata[ctrl].flags |= (1ul << 21);
-		goto err_chip_i2c_xfer;
-	}
-	cdata[ctrl].flags |= (1ul << 14);
-	return EC_SUCCESS;
-
-err_chip_i2c_xfer:
-	cdata[ctrl].flags |= (1ul << 22);
-	cdata[ctrl].hwsts2 = MCHP_I2C_STATUS(raddr); /* record status */
-	/* NOTE: writing I2C.Ctrl.PIN=1 will clear all bits
-	 * except NBB in I2C.Status
-	 */
-	MCHP_I2C_CTRL(raddr) = CTRL_PIN | CTRL_ESO | CTRL_STO | CTRL_ACK;
-	cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED;
-	/* record status after STOP */
-	cdata[ctrl].hwsts4 = MCHP_I2C_STATUS(raddr);
-
-	/* record line levels.
-	 * Note line levels may reflect STOP condition
-	 */
-	cdata[ctrl].lines = (uint8_t)get_line_level(cdata[ctrl].port);
-	if (cdata[ctrl].hwsts2 & STS_BER) {
-		cdata[ctrl].flags |= (1ul << 23);
-		reset_controller(ctrl);
-	}
-	return EC_ERROR_UNKNOWN;
-}
-/*
- * A safe method of reading port's SCL pin level.
- */
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SCL pin defined for this port,
-	 * then return 1 to appear idle.
-	 */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-	return gpio_get_level(g);
-}
-
-/*
- * A safe method of reading port's SDA pin level.
- */
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SDA pin defined for this port,
-	 * then return 1 to appear idle.
-	 */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-	return gpio_get_level(g);
-}
-
-/*
- * Caller is responsible for locking the port.
- */
-int i2c_get_line_levels(int port)
-{
-	int rv, controller;
-
-	controller = i2c_port_to_controller(port);
-	if (controller < 0)
-		return 0x03; /* No controller, return high line levels */
-
-	select_port(port, controller);
-	rv = get_line_level(port);
-	return rv;
-}
-
-/*
- * this function returns the controller for I2C
- * return mod of MCHP_I2C_CTRL_MAX
- */
-__overridable int board_i2c_p2c(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-	return i2c_p2c[port];
-}
-
-/*
- * I2C port must be a zero based number.
- * MCHP I2C can map any port to any of the 4 controllers.
- * Call board level function as board designs may choose
- * to wire up and group ports differently.
- */
-int i2c_port_to_controller(int port)
-{
-	return board_i2c_p2c(port);
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	/* Parameter is port, but timeout is stored by-controller. */
-	cdata[i2c_port_to_controller(port)].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-/*
- * Initialize I2C controllers specified by the board configuration.
- * If multiple ports are mapped to the same controller choose the
- * lowest speed.
- */
-void i2c_init(void)
-{
-	int i, controller, kbps;
-	int controller_kbps[MCHP_I2C_CTRL_MAX];
-	const struct i2c_bus_clk *pbc;
-
-	for (i = 0; i < MCHP_I2C_CTRL_MAX; i++)
-		controller_kbps[i] = 0;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	memset(cdata, 0, sizeof(cdata));
-
-	for (i = 0; i < i2c_ports_used; ++i) {
-		/* Assign I2C controller to I2C port */
-		i2c_p2c[i2c_ports[i].port] = i % MCHP_I2C_CTRL_MAX;
-
-		controller = i2c_port_to_controller(i2c_ports[i].port);
-		kbps = i2c_ports[i].kbps;
-
-		/* Clear PCR sleep enable for controller */
-		i2c_ctrl_slp_en(controller, 0);
-
-		if (controller_kbps[controller] &&
-		    (controller_kbps[controller] != kbps)) {
-			CPRINTF("I2C[%d] init speed conflict: %d != %d\n",
-				controller, kbps, controller_kbps[controller]);
-			kbps = MIN(kbps, controller_kbps[controller]);
-		}
-
-		/* controller speed hardware limits */
-		pbc = get_supported_speed_idx(kbps);
-		if (pbc->freq_khz != kbps)
-			CPRINTF("I2C[%d] init requested speed %d"
-				" using closest supported speed %d\n",
-				controller, kbps, pbc->freq_khz);
-
-		controller_kbps[controller] = pbc->freq_khz;
-		configure_controller(controller, i2c_ports[i].port,
-				     controller_kbps[controller]);
-		cdata[controller].task_waiting = TASK_ID_INVALID;
-		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-		/* Use default timeout. */
-		i2c_set_timeout(i2c_ports[i].port, 0);
-	}
-}
-
-/*
- * Handle I2C interrupts.
- * I2C controller is configured to fire interrupts on
- * anything causing PIN 1->0 and I2C IDLE (NBB -> 1).
- * NVIC interrupt disable must clear NVIC pending bit.
- */
-static void handle_interrupt(int controller)
-{
-	uint32_t r;
-	int id = cdata[controller].task_waiting;
-	uintptr_t raddr = chip_i2c_ctrl_base(controller);
-
-	/*
-	 * Write to control register interferes with I2C transaction.
-	 * Instead, let's disable IRQ from the core until the next time
-	 * we want to wait for STS_PIN/STS_NBB.
-	 */
-	disable_controller_irq(controller);
-	cdata[controller].hwsts3 = MCHP_I2C_STATUS(raddr);
-	/* Clear all interrupt status */
-	r = MCHP_I2C_COMPLETE(raddr);
-	MCHP_I2C_COMPLETE(raddr) = r;
-	cdata[controller].i2c_complete = r;
-	MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller);
-
-	/* Wake up the task which was waiting on the I2C interrupt, if any. */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void)
-{
-	handle_interrupt(0);
-}
-void i2c1_interrupt(void)
-{
-	handle_interrupt(1);
-}
-void i2c2_interrupt(void)
-{
-	handle_interrupt(2);
-}
-void i2c3_interrupt(void)
-{
-	handle_interrupt(3);
-}
-#if defined(CHIP_FAMILY_MEC172X)
-void i2c4_interrupt(void)
-{
-	handle_interrupt(4);
-}
-#elif defined(CHIP_FAMILY_MEC152X)
-void i2c4_interrupt(void)
-{
-	handle_interrupt(4);
-}
-void i2c5_interrupt(void)
-{
-	handle_interrupt(5);
-}
-void i2c6_interrupt(void)
-{
-	handle_interrupt(6);
-}
-void i2c7_interrupt(void)
-{
-	handle_interrupt(7);
-}
-#endif
-
-DECLARE_IRQ(MCHP_IRQ_I2C_0, i2c0_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_1, i2c1_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_2, i2c2_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_3, i2c3_interrupt, 2);
-#if defined(CHIP_FAMILY_MEC172X)
-DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
-#elif defined(CHIP_FAMILY_MEC152X)
-DECLARE_IRQ(MCHP_IRQ_I2C_4, i2c4_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_5, i2c5_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_6, i2c6_interrupt, 2);
-DECLARE_IRQ(MCHP_IRQ_I2C_7, i2c7_interrupt, 2);
-#endif
diff --git a/chip/mchp/i2c_chip.h b/chip/mchp/i2c_chip.h
deleted file mode 100644
index c8ceb98d04..0000000000
--- a/chip/mchp/i2c_chip.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MCHP-specific I2C module for Chrome EC */
-
-#ifndef _I2C_CHIP_H
-#define _I2C_CHIP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Place any C interfaces here */
-
-/*
- * Function returns the controller for I2C.
- *
- * Default function assigns controller for I2C port with modulo operation. If
- * the I2C ports used are greater than MCHP_I2C_CTRL_MAX, then I2C ports will
- * share the controller. Typically Type-C chips need individual controller per
- * port because of heavy I2C transactions. Hence, define a board specific
- * controller assignment when the I2C ports used are greater than
- * MCHP_I2C_CTRL_MAX.
- */
-__override_proto int board_i2c_p2c(int port);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _I2C_CHIP_H */
diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c
deleted file mode 100644
index 946ea1ca90..0000000000
--- a/chip/mchp/keyboard_raw.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for MCHP MEC
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-/*
- * Using direct mode interrupt, do not enable
- * GIRQ bit in aggregator block enable register.
- */
-void keyboard_raw_init(void)
-{
-	/* clear key scan PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_KEYSCAN);
-
-	keyboard_raw_enable_interrupt(0);
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/* Enable keyboard scan interrupt */
-	MCHP_INT_ENABLE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-	MCHP_KS_KSI_INT_EN = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(MCHP_IRQ_KSC_INT);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	if (out == KEYBOARD_COLUMN_ALL) {
-		MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	} else if (out == KEYBOARD_COLUMN_NONE) {
-		MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	} else {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (out == 2) {
-			MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		} else {
-			MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-#else
-		MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-#endif
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	uint8_t b1, b2;
-
-	b1 = MCHP_KS_KSI_INPUT;
-	b2 = (b1 & 0xff) ^ 0xff;
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	/* return (MCHP_KS_KSI_INPUT & 0xff) ^ 0xff; */
-	return b2;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-		task_clear_pending_irq(MCHP_IRQ_KSC_INT);
-		task_enable_irq(MCHP_IRQ_KSC_INT);
-	} else {
-		task_disable_irq(MCHP_IRQ_KSC_INT);
-	}
-}
-
-void keyboard_raw_interrupt(void)
-{
-	/* Clear interrupt status bits */
-	MCHP_KS_KSI_STATUS = 0xff;
-
-	MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT;
-
-	/* Wake keyboard scan task to handle interrupt */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0;
-}
diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c
deleted file mode 100644
index 6f34a33a8d..0000000000
--- a/chip/mchp/lfw/ec_lfw.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC SoC little FW
- *
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "cros_version.h"
-#include "gpio.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
-#include "system.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
-#include "tfdp_chip.h"
-
-#ifdef CONFIG_MCHP_LFW_DEBUG
-#include "dma_chip.h"
-#endif
-
-#include "ec_lfw.h"
-
-/*
- * Check if LFW build is pulling in GPSPI which is not
- * used for EC firmware SPI flash access.
- */
-#ifdef CONFIG_MCHP_GPSPI
-#error "FORCED BUILD ERROR: CONFIG_MCHP_GPSPI is defined"
-#endif
-
-#define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC)
-#define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-__attribute__ ((section(".intvector")))
-const struct int_vector_t hdr_int_vect = {
-	/* init sp, unused. set by MEC ROM loader */
-	(void *)lfw_stack_top,  /* preserve ROM log. was (void *)0x11FA00, */
-	&lfw_main,	/* was &lfw_main, */	  /* reset vector */
-	&fault_handler,   /* NMI handler */
-	&fault_handler,   /* HardFault handler */
-	&fault_handler,   /* MPU fault handler */
-	&fault_handler    /* Bus fault handler */
-};
-
-/* SPI devices - from board.c */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 4, GPIO_QMSPI_CS0 },
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-/*
- * At POR or EC reset MCHP Boot-ROM should only load LFW and jumps
- * into LFW entry point located at offset 0x04 of LFW.
- * Entry point is programmed into SPI Header by Python SPI image
- * builder in chip/mchp/util.
- *
- * EC_RO/RW calling LFW should enter through this routine if you
- * want the vector table updated. The stack should be set to
- * LFW linker file parameter lfw_stack_top because we do not
- * know if the callers stack is OK.
- *
- * Make sure lfw_stack_top will not overwrite panic data!
- * from include/panic.h
- * Panic data goes at the end of RAM. This is safe because we don't
- * context switch away from the panic handler before rebooting,
- * and stacks and data start at the beginning of RAM.
- *
- * chip level config_chip.h
- * #define CONFIG_RAM_SIZE 0x00008000
- * #define CONFIG_RAM_BASE 0x120000 - 0x8000 = 0x118000
- *
- *  #define PANIC_DATA_PTR ((struct panic_data *)\
- *	(CONFIG_RAM_BASE + CONFIG_RAM_SIZE - sizeof(struct panic_data)))
- *
- * LFW stack located by ec_lfw.ld linker file 256 bytes below top of
- * data SRAM.
- * PROVIDE( lfw_stack_top = 0x11F000 );
- *
- * !!!WARNING!!!
- * Current MEC BootROM's zeros all memory therefore any chip reset
- * will destroy panic data.
- */
-
-/*
- * Configure 32-bit basic timer 0 for 1MHz, auto-reload and
- * no interrupt.
- */
-void timer_init(void)
-{
-	uint32_t val = 0;
-
-	/* Ensure timer is not running */
-	MCHP_TMR32_CTL(0) &= ~BIT(5);
-
-	/* Enable timer */
-	MCHP_TMR32_CTL(0) |= BIT(0);
-
-	val = MCHP_TMR32_CTL(0);
-
-	/* Prescale = 48 -> 1MHz -> Period = 1 us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MCHP_TMR32_CTL(0) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MCHP_TMR32_PRE(0) = 0xffffffff;
-
-	/* Override the count */
-	MCHP_TMR32_CNT(0) = 0xffffffff;
-
-	/* Auto restart */
-	MCHP_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MCHP_TMR32_CTL(0) |= BIT(5);
-
-}
-
-/*
- * Use copy of SPI flash read compiled for LFW (no semaphores).
- * LFW timeout code does not use interrupts so reset timer
- * before starting SPI read to minimize probability of
- * timer wrap.
- */
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
-{
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
-
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	__hw_clock_source_set(0); /* restart free run timer */
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-/*
- * Load EC_RO/RW image from local SPI flash.
- * If CONFIG_MEC_TEST_EC_RORW_CRC was define the last 4 bytes
- * of the binary is IEEE 802.3 CRC32 of the previous bytes.
- * Use DMA channel 0 CRC32 HW to check data integrity.
- */
-int spi_image_load(uint32_t offset)
-{
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
-	uint32_t i;
-#ifdef CONFIG_MCHP_LFW_DEBUG
-	uint32_t crc_calc, crc_exp;
-	int rc;
-#endif
-
-	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
-
-	/* Why fill all but last 4-bytes? */
-	memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
-
-	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
-#ifdef CONFIG_MCHP_LFW_DEBUG
-		rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-		if (rc != EC_SUCCESS) {
-			trace2(0, LFW, 0,
-				"spi_flash_readloc block %d ret = %d",
-				i, rc);
-			while (MCHP_PCR_PROC_CLK_CTL)
-				MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
-		}
-#else
-		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-#endif
-
-#ifdef CONFIG_MCHP_LFW_DEBUG
-	dma_crc32_start(buf, (CONFIG_RO_SIZE - 4), 0);
-	do {
-		MCHP_USEC_DELAY(31); /* delay(stall) CPU by 32 us */
-		i = dma_is_done_chan(0);
-	} while (i == 0);
-	crc_calc = MCHP_DMA_CH0_CRC32_DATA;
-	crc_exp = *((uint32_t *)&buf[CONFIG_RO_SIZE - 4]);
-	trace12(0, LFW, 0, "EC image CRC32 = 0x%08x  expected = 0x%08x",
-		crc_calc, crc_exp);
-#endif
-
-	return 0;
-}
-
-void udelay(unsigned int us)
-{
-	uint32_t t0 = __hw_clock_source_read();
-
-	while (__hw_clock_source_read() - t0 < us)
-		;
-}
-
-void usleep(unsigned int us)
-{
-	udelay(us);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return ((int64_t)(now->val - deadline.val) >= 0);
-}
-
-/*
- * LFW does not use interrupts so no ISR will fire to
- * increment high 32-bits of timestap_t. Force high
- * word to zero. NOTE: There is a risk of false timeout
- * errors due to timer wrap. We will reset timer before
- * each SPI transaction.
- */
-timestamp_t get_time(void)
-{
-	timestamp_t ts;
-
-	ts.le.hi = 0;	/* clksrc_high; */
-	ts.le.lo = __hw_clock_source_read();
-	return ts;
-}
-
-#ifdef CONFIG_UART_CONSOLE
-
-BUILD_ASSERT(CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES);
-
-void uart_write_c(char c)
-{
-	/* Put in carriage return prior to newline to mimic uart_vprintf() */
-	if (c == '\n')
-		uart_write_c('\r');
-
-	/* Wait for space in transmit FIFO. */
-	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(5)))
-		;
-	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
-}
-
-void uart_puts(const char *str)
-{
-	if (!str || !*str)
-		return;
-
-	do {
-		uart_write_c(*str++);
-	} while (*str);
-}
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
-	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
-
-	/* Set DLAB = 0 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
-
-	/* Activate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-}
-#else
-void uart_write_c(char c __attribute__((unused))) {}
-
-void uart_puts(const char *str __attribute__((unused))) {}
-
-void uart_init(void) {}
-#endif /* #ifdef CONFIG_UART_CONSOLE */
-
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	usleep(1000);
-	MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-
-	resetvec();
-}
-
-/*
- * If any of VTR POR, VBAT POR, chip resets, or WDT reset are active
- * force VBAT image type to none causing load of EC_RO.
- */
-void system_init(void)
-{
-	uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				MCHP_PWR_RST_STS_SYS;
-
-	trace12(0, LFW, 0,
-		"VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
-		wdt_sts, rst_sts);
-
-	if (rst_sts || wdt_sts)
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX)
-					= EC_IMAGE_UNKNOWN;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
-}
-
-
-/*
- * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly.
- * NOTE: Based on LFW from MEC1322
- * Upon chip reset, BootROM loads image = LFW+EC_RO and enters LFW.
- * LFW checks reset type:
- *   VTR POR, chip reset, WDT reset then set VBAT Load type to Unknown.
- * LFW reads VBAT Load type:
- *   EC_IMAGE_RO then read EC_RO from SPI flash and jump into it.
- *   EC_IMAGE_RO then read EC_RW from SPI flash and jump into it.
- *   Other then jump into EC image loaded by Boot-ROM.
- */
-void lfw_main(void)
-{
-
-	uintptr_t init_addr;
-
-	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
-
-	/* Use 48 MHz processor clock to power through boot */
-	MCHP_PCR_PROC_CLK_CTL = 1;
-
-#ifdef CONFIG_WATCHDOG
-	/* Reload watchdog which may be running in case of sysjump */
-	MCHP_WDG_KICK = 1;
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Stop aux timer */
-	MCHP_TMR16_CTL(0) &= ~1;
-#endif
-#endif
-	/*
-	 * TFDP functions will compile to nothing if CONFIG_MEC1701_TFDP
-	 * is not defined.
-	 */
-	tfdp_power(1);
-	tfdp_enable(1, 1);
-	trace0(0, LFW, 0, "LFW first trace");
-
-	timer_init();
-	clock_init();
-	cpu_init();
-	dma_init();
-	uart_init();
-	system_init();
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	uart_puts("littlefw ");
-	uart_puts(current_image_data.version);
-	uart_puts("\n");
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		trace0(0, LFW, 0, "LFW EC_RW Load");
-		uart_puts("lfw-RW load\n");
-
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF);
-		break;
-	case EC_IMAGE_RO:
-		trace0(0, LFW, 0, "LFW EC_RO Load");
-		uart_puts("lfw-RO load\n");
-
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF +
-			       CONFIG_RO_STORAGE_OFF);
-		break;
-	default:
-		trace0(0, LFW, 0, "LFW default: use EC_RO loaded by BootROM");
-		uart_puts("lfw-default case\n");
-
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = EC_IMAGE_RO;
-
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	trace11(0, LFW, 0, "Get EC reset handler from 0x%08x", (init_addr + 4));
-	trace11(0, LFW, 0, "Jump to EC @ 0x%08x",
-		*((uint32_t *)(init_addr + 4)));
-	jump_to_image(*(uintptr_t *)(init_addr + 4));
-
-	/* should never get here */
-	while (1)
-		;
-}
diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h
deleted file mode 100644
index c989a3bc1b..0000000000
--- a/chip/mchp/lfw/ec_lfw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC SoC little FW
- *
- */
-
-#include <stdint.h>
-#include <stdnoreturn.h>
-
-/* Why naked?  This is dangerous except for
- * function/ISR wrappers using inline assembly.
- * lfw_main() makes many calls and has one local variable.
- * Naked C functions should not use local data unless the local
- * data can fit in CPU registers.
- * Note other C functions called by lfw_main() are not marked naked and
- * do include compiler generated prolog and epilog code.
- * We also do not know how much stack space is available when
- * EC_RO calls lfw_main().
- *
-noreturn void lfw_main(void) __attribute__ ((naked));
-*/
-noreturn void lfw_main(void);
-void fault_handler(void) __attribute__((naked));
-
-/*
- * Defined in linker file ec_lfw.ld
- */
-extern uint32_t lfw_stack_top[];
-
-struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
-};
-
-#define SPI_CHUNK_SIZE			1024
diff --git a/chip/mchp/lfw/ec_lfw.ld b/chip/mchp/lfw/ec_lfw.ld
deleted file mode 100644
index 8e8601a5ee..0000000000
--- a/chip/mchp/lfw/ec_lfw.ld
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC parts with 256KB SRAM SoC little FW
- *
- */
-
-/*
- * Memory Spaces Definitions
- * LFW occupies first 4KB of CODE SRAM.
- * First 24 bytes contain a minimal Cortex-M4
- * vector table.
- */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x0E0000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x0E0018, LENGTH = 0xFE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/*
- * MEC 256KB SRAM 0xE0000 - 0x11FFFF
- * Data Top 32KB at 0x118000 - 0x11FFFF
- * Boot-ROM log is 0x11FF00 - 0x11FFFF
- * Set top of LFW stack 1KB below top of SRAM
- * because EC panic and jump data live at
- * top of SRAM.
- * !!!WARNING!!!
- * POR or any chip reset will cause MEC BootROM
- * to run. BootROM will clear all CODE & DATA SRAM.
- * Panic data will be lost.
- *
- */
-PROVIDE( lfw_stack_top = 0x11F000 );
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mchp/lfw/ec_lfw_416kb.ld b/chip/mchp/lfw/ec_lfw_416kb.ld
deleted file mode 100644
index 97be2fe06a..0000000000
--- a/chip/mchp/lfw/ec_lfw_416kb.ld
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MCHP MEC parts with 416KB SRAM SoC little FW
- *
- */
-
-/*
- * Memory Spaces Definitions
- * LFW occupies first 4KB of CODE SRAM.
- * First 24 bytes contain a minimal Cortex-M4
- * vector table.
- */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x0C0000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x0C0018, LENGTH = 0xFE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/*
- * MEC172xN has 416KB total SRAM: 352KB CODE 64KB DATA
- * CODE: 0x0C0000 - 0x117FFF
- * DATA: 0x118000 - 0x127FFF
- * Boot-ROM log is 0x11FF00 - 0x11FFFF
- * MEC172x Top 1KB is not cleared if OTP customer flag enabled.
- * !!! TODO !!! Does presence of PUF feature move customer area?
- * Boot-ROM spec states 3.5KB from top is lost.
- * 0x12_7800 - 0x12_7fff 2KB used by PUF option
- * 0x12_7400 - 0x12_77ff 1KB Customer use. Not cleared by Boot-ROM
- * 0x12_7200 - 0x12_73ff 512 byte Boot-ROM log
- * CrOS EC puts panic data at Top of RAM.
- * We must set Top of RAM to be customer region far enough to
- * hold panic data.
- * Set Top of SRAM to 0x12_7800.
- * This requires size of SRAM = 0x127800 - 0x118000 = 0xF800 (62 KB)
- */
-PROVIDE( lfw_stack_top = 0x127800 );
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mchp/lfw/gpio.inc b/chip/mchp/lfw/gpio.inc
deleted file mode 100644
index 598a6044d7..0000000000
--- a/chip/mchp/lfw/gpio.inc
+++ /dev/null
@@ -1,107 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common GPIOs needed for LFW loader and main process FW
- */
-
-/* SPI
- * External SPI chip select must be open drain and driven high or
- * internal SPI chip select must be push-pull and driven high before
- * SPI controller configuration.
- * QMSPI external Shared CS0# is GPIO_0055
- * QMSPI internal CS0# is GPIO_0116
- */
-#if defined(CHIP_VARIANT_MEC1727SZ)
-GPIO(QMSPI_CS0, PIN(0116), GPIO_PULL_UP | GPIO_HIGH)
-#else
-GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH)
-#endif
-
-/* Boot-ROM loads from external or internal SPI flash.
- * There are two external ports: shared(default) and private.
- * NOTE: QMSPI Shared SPI Port pins are on VTR2
- * SHD_CS0# = GPIO 0055 Func 2 bank 1 b[13]
- * SHD_CLK  = GPIO 0056 Func 2 bank 1 b[14]
- * SHD_IO0  = GPIO 0223 Func 1 bank 4 b[19]
- * SHD_IO1  = GPIO 0224 Func 2 bank 4 b[20]
- * Not using IO2 and IO2 as data
- * SHD_IO2  = GPIO 0227 Func 1 bank 4 b[23]
- * SHD_IO3  = GPIO 0016 Func 2 bank 0 b[14]
- * MEC1727 variants load from internal 512KB SPI flash(internal only pins)
- * INT_CS# = GPIO 0116 Func 1 bank 2 14
- * INT_SCK = GPIO 0117 Func 1 bank 2 15
- * INT_IO0 = GPIO 0074 Func 1 bank 1 28
- * INT_IO1 = GPIO 0075 Func 1 bank 1 29
- * INT_WP# = GPIO 0076 Func 0 for WP# control
- * Internal flash HOLD# connected to VTR1 rail.
- */
-#if defined(CHIP_VARIANT_MEC1727SZ)
-/* MEC1727 variants have internal SPI flash on internal only pins */
-ALTERNATE(PIN_MASK(2, 0x4000), 1, MODULE_SPI_FLASH, GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(2, 0x8000), 1, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(1, 0x30000000), 1, MODULE_SPI_FLASH, 0)
-#else
-/* external SPI flash on QMSPI SHD_xx pins */
-ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
-ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x080000), 1, MODULE_SPI_FLASH, 0)
-ALTERNATE(PIN_MASK(4, 0x100000), 2, MODULE_SPI_FLASH, 0)
-#endif
-
-/* UART
- * Per CONFIG_UART_CONSOLE and chip to configure UART pins
- */
-#if CONFIG_UART_CONSOLE == 0
-/* select UART0 */
-/* MEC170X, MEC152X and MEC172X support same UART0 pins and ALT function */
-/*
- * UART0
- * GPIO_0105 Func 1 = UART_RX
- * GPIO_0104 Func 1 = UART_TX
- * Bank 2 bits[5:4]
- */
-ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
-
-#elif CONFIG_UART_CONSOLE == 1
-/* select UART1 */
-/* MEC170X, MEC152X and MEC172X support same UART1 pins
- * but ALT function 2 on MEC170X, function 1 on others
- */
-#if defined(CHIP_FAMILY_MEC170X)
-/*
- * UART1
- * GPIO_0171 Func 2 = UART_RX
- * GPIO_0170 Func 2 = UART_TX
- * Bank 3 bits[25:24]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 2, MODULE_UART, 0)
-
-#else
-/*
- * UART1
- * GPIO_0171 Func 1 = UART_RX
- * GPIO_0170 Func 1 = UART_TX
- * Bank 3 bits[25:24]
- */
-ALTERNATE(PIN_MASK(3, 0x03000000), 1, MODULE_UART, 0)
-
-#endif /* defined(CHIP_FAMILY_MEC170X) */
-
-#else
-/* select UART2 */
-/* only MEC152X supports UART2 pins */
-#if defined(CHIP_FAMILY_MEC152X)
-/*
- * UART2
- * GPIO_0145 Func 2 = UART_RX
- * GPIO_0146 Func 2 = UART_TX
- * Bank 3 bits[6:5]
- */
-ALTERNATE(PIN_MASK(3, 0x60), 2, MODULE_UART, 0)
-
-#endif /* defined(CHIP_FAMILY_MEC152X) */
-
-#endif /* CONFIG_UART_CONSOLE == 0 */
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
deleted file mode 100644
index b5db07b88f..0000000000
--- a/chip/mchp/lpc.c
+++ /dev/null
@@ -1,1022 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for MCHP MEC family */
-
-#include "common.h"
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "espi.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "chipset.h"
-#include "tfdp_chip.h"
-
-/* Console output macros */
-#ifdef CONFIG_MCHP_DEBUG_LPC
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-static uint8_t
-mem_mapped[0x200] __attribute__((section(".bss.big_align")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)mem_mapped;
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-static uint8_t custom_acpi_cmd;
-static uint8_t custom_acpi_ec2os_cnt;
-static uint8_t custom_apci_ec2os[4];
-#endif
-
-
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be
-	 * pulled high by the external pull up resistor. This ensures the
-	 * host will see the following falling edge, regardless of the
-	 * line state before this function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length
- * is 60 ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need
- * pulse length >61us. Both are short enough and events are infrequent,
- * so just delay for 65 us.
- */
-static void lpc_generate_smi(void)
-{
-	CPUTS("LPC Pulse SMI");
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* eSPI: pulse SMI# Virtual Wire low */
-	espi_vw_pulse_wire(VW_SMI_L, 0);
-#else
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#endif
-}
-
-static void lpc_generate_sci(void)
-{
-	CPUTS("LPC Pulse SCI");
-#ifdef CONFIG_SCI_GPIO
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_pulse_wire(VW_SCI_L, 0);
-#else
-	MCHP_ACPI_PM_STS |= 1;
-	udelay(65);
-	MCHP_ACPI_PM_STS &= ~1;
-#endif
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that
-	 * through a separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	espi_vw_set_wire(VW_WAKE_L, !wake_events);
-#else
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-#endif
-}
-
-static uint8_t *lpc_get_hostcmd_data_range(void)
-{
-	return mem_mapped;
-}
-
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via PCH_SMI_L GPIO
- *   - SCI pulse via PCH_SCI_L GPIO
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	CPUTS("LPC update_host_event_status");
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(MCHP_IRQ_ACPIEC0_IBF);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(MCHP_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING;
-	} else {
-		MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING;
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING;
-	} else {
-		MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING;
-	}
-
-	/* Copy host events to mapped memory */
-	*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-			lpc_get_host_events();
-
-	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the parameter buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte. */
-	MCHP_ACPI_EC_EC2OS(1, 0) = args->result;
-
-	/*
-	 * Clear processing flag in hardware and
-	 * sticky status in interrupt aggregator.
-	 */
-	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is
-	 * synchronous anyway
-	 */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS) {
-		/* CPRINTS("LPC EC_RES_IN_PROGRESS"); */
-		return;
-	}
-
-	CPRINTS("LPC Set EC2OS(1,0)=0x%02x", pkt->driver_result);
-
-	/* Write result to the data byte. */
-	MCHP_ACPI_EC_EC2OS(1, 0) = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return mem_mapped + 0x100;
-}
-
-void lpc_mem_mapped_init(void)
-{
-	/* We support LPC arguments and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-}
-
-const int acpi_ec_pcr_slp[] = {
-	MCHP_PCR_ACPI_EC0,
-	MCHP_PCR_ACPI_EC1,
-	MCHP_PCR_ACPI_EC2,
-	MCHP_PCR_ACPI_EC3,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_PCR_ACPI_EC4,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES);
-
-const int acpi_ec_nvic_ibf[] = {
-	MCHP_IRQ_ACPIEC0_IBF,
-	MCHP_IRQ_ACPIEC1_IBF,
-	MCHP_IRQ_ACPIEC2_IBF,
-	MCHP_IRQ_ACPIEC3_IBF,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_IRQ_ACPIEC4_IBF,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-const int acpi_ec_espi_bar_id[] = {
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC2,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
-#ifndef CHIP_FAMILY_MEC152X
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC4,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(acpi_ec_espi_bar_id) == MCHP_ACPI_EC_INSTANCES);
-#endif
-
-void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
-{
-	if (instance >= MCHP_ACPI_EC_INSTANCES) {
-		CPUTS("ACPI EC CFG invalid");
-		return;
-	}
-
-	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
-			mask;
-	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) +
-		(1ul << 15) + mask;
-#endif
-	MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
-	task_enable_irq(acpi_ec_nvic_ibf[instance]);
-}
-
-/*
- * 8042EM hardware decodes with fixed mask of 0x04
- * Example: io_base == 0x60 -> decodes 0x60/0x64
- * Enable both IBF and OBE interrupts.
- */
-void chip_8042_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
-			(io_base << 16) + 0x01ul;
-#else
-	/* Set up 8042 interface at 0x60/0x64 */
-	MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15);
-#endif
-	/* Set up indication of Auxiliary status */
-	MCHP_8042_KB_CTRL |= BIT(7);
-
-	MCHP_8042_ACT |= 1;
-
-	MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT +
-			MCHP_8042_IBF_GIRQ_BIT;
-
-	task_enable_irq(MCHP_IRQ_8042EM_IBF);
-	task_enable_irq(MCHP_IRQ_8042EM_OBE);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MCHP_8042_KB_CTRL |= BIT(5);
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
-	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
-#else
-	MCHP_LPC_SIRQ(1) = 0x01;
-#endif
-#endif
-}
-
-/*
- * Access data RAM
- * MCHP EMI Base address register = physical address of buffer
- * in SRAM. EMI hardware adds 16-bit offset Host programs into
- * EC_Address_LSB/MSB registers.
- * Limit EMI read / write range. First 256 bytes are RW for host
- * commands. Second 256 bytes are RO for memory-mapped data.
- * Hardware decodes a fixed 16 byte IO range.
- */
-void chip_emi0_config(uint32_t io_base)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15);
-#endif
-
-	MCHP_EMI_MBA0(0) = (uint32_t)mem_mapped;
-
-	MCHP_EMI_MRL0(0) = 0x200;
-	MCHP_EMI_MWL0(0) = 0x100;
-
-	MCHP_INT_ENABLE(MCHP_EMI_GIRQ) = MCHP_EMI_GIRQ_BIT(0);
-	task_enable_irq(MCHP_IRQ_EMI0);
-}
-
-/* Setup Port 80 Debug Hardware ports.
- * First instance for I/O 80h only.
- * Clear FIFO's and time stamp.
- * Set FIFO interrupt threshold to maximum of 14 bytes.
- */
-#if defined(CHIP_FAMILY_MEC172X)
-void chip_port80_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BDP0);
-
-	/* reset, configure, and enable */
-	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_SRST;
-	MCHP_BDP0_CONFIG = MCHP_BDP_CFG_FIFO_THRH_28;
-	MCHP_BDP0_INTR_EN = MCHP_BDP_IEN_THRH;
-	MCHP_BDP0_ACTV = 1;
-
-	MCHP_INT_SOURCE(15) = MCHP_INT15_BDP0;
-	MCHP_INT_ENABLE(15) = MCHP_INT15_BDP0;
-	task_enable_irq(MCHP_IRQ_BDP0);
-
-	/* Last: Enable Host access via eSPI IO BAR */
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_BDP0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) =
-			(io_base << 16) + 0x01ul;
-}
-#else
-void chip_port80_config(uint32_t io_base)
-{
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
-
-	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
-			MCHP_P80_RESET_TIMESTAMP_WO;
-
-#ifdef CONFIG_HOSTCMD_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
-			(io_base << 16) + 0x01ul;
-#else
-	MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15);
-#endif
-	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 +
-			MCHP_P80_TIMEBASE_1500KHZ +
-			MCHP_P80_TIMER_ENABLE;
-
-	MCHP_P80_ACTIVATE(0) = 1;
-
-	MCHP_INT_SOURCE(15) = MCHP_P80_GIRQ_BIT(0);
-	MCHP_INT_ENABLE(15) = MCHP_P80_GIRQ_BIT(0);
-	task_enable_irq(MCHP_IRQ_PORT80DBG0);
-}
-#endif
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-static void chip_lpc_iobar_debug(void)
-{
-	CPRINTS("LPC ACPI EC0 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(0));
-	CPRINTS("LPC ACPI EC1 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(1));
-	CPRINTS("LPC 8042EM IO BAR   = 0x%08x", MCHP_LPC_8042_BAR);
-	CPRINTS("LPC EMI0 IO BAR     = 0x%08x", MCHP_LPC_EMI0_BAR);
-	CPRINTS("LPC Port80Dbg0 IO BAR = 0x%08x", MCHP_LPC_P80DBG0_BAR);
-}
-#endif
-
-/*
- * Most registers in LPC module are reset when the host is off.
- * We need to set up LPC again when the host is starting up.
- * MCHP LRESET# can be one of two pins
- *	GPIO_0052 Function 2
- *	GPIO_0064 Function 1
- * Use GPIO interrupt to detect LRESET# changes.
- * Use GPIO_0064 for LRESET#. Must update board/board_name/gpio.inc
- *
- * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
- *
- */
-#ifndef CONFIG_HOSTCMD_ESPI
-static void setup_lpc(void)
-{
-	MCHP_LPC_CFG_BAR |= (1ul << 15);
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	chip_acpi_ec_config(0, 0x62, 0x04);
-
-	/* Set up ACPI1 for 0x200 - 0x207 */
-	chip_acpi_ec_config(1, 0x200, 0x07);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	chip_8042_config(0x60);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MCHP_8042_KB_CTRL |= BIT(5);
-	MCHP_LPC_SIRQ(1) = 0x01;
-#endif
-	/* EMI0 at IO 0x800 */
-	chip_emi0_config(0x800);
-
-	chip_port80_config(0x80);
-
-	lpc_mem_mapped_init();
-
-	/* Activate LPC interface */
-	MCHP_LPC_ACT |= 1;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-	chip_lpc_iobar_debug();
-#endif
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST);
-#endif
-
-static void lpc_init(void)
-{
-	CPUTS("LPC HOOK_INIT");
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	/*
-	 * Clear PCR sleep enables for peripherals we are using for
-	 * both LPC and eSPI.
-	 * Global Configuration, ACPI EC0/1, 8042 Keyboard controller.
-	 * NOTE: EMI doesn't have a sleep enable.
-	 */
-	MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_MIF8042);
-
-#ifdef CONFIG_HOSTCMD_ESPI
-
-	espi_init();
-
-#else
-	/* Clear PCR LPC sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_LPC);
-
-	/* configure pins */
-	gpio_config_module(MODULE_LPC, 1);
-
-	/*
-	 * MCHP LRESET# interrupt is GPIO interrupt
-	 * and configured by GPIO table in board level gpio.inc
-	 * Refer to lpcrst_interrupt() in this file.
-	 */
-	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
-
-	/*
-	 * b[8]=1(LRESET# is platform reset), b[0]=0 VCC_PWRGD is
-	 * asserted when LRESET# is 1(inactive)
-	 */
-	MCHP_PCR_PWR_RST_CTL = 0x100ul;
-
-	/*
-	 * Allow LPC sleep if Host CLKRUN# signals
-	 * clock stop and there are no pending SERIRQ
-	 * or LPC DMA.
-	 */
-	MCHP_LPC_EC_CLK_CTRL =
-		(MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
-
-	setup_lpc();
-#endif
-}
-/*
- * Set priority to higher than default; this way LPC memory mapped
- * data is ready before other inits try to initialize their
- * memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-void lpc_set_init_done(int val)
-{
-	init_done = val;
-}
-
-/*
- * MCHP MCHP family allows selecting one of two GPIO pins alternate
- * functions as LRESET#.
- * LRESET# can be monitored as bit[1](read-only) of the
- * LPC Bus Monitor register. NOTE: Bus Monitor is synchronized with
- * LPC clock. We have observed APL configurations where LRESET#
- * changes while LPC clock is not running!
- * bit[1]==0 -> LRESET# is high
- * bit[1]==1 -> LRESET# is low (active)
- * LRESET# active causes the EC to activate internal signal RESET_HOST.
- * MCHP_PCR_PWR_RST_STS bit[3](read-only) = RESET_HOST_STATUS =
- * 0 = Reset active
- * 1 = Reset not active
- * MCHP is different than MEC1322 in that LRESET# is not connected
- * to a separate interrupt source.
- * If using LPC the board design must select on of the two GPIO pins
- * dedicated for LRESET# and this pin must be configured in the
- * board level gpio.inc
- */
-void lpcrst_interrupt(enum gpio_signal signal)
-{
-#ifndef CONFIG_HOSTCMD_ESPI
-	/* Initialize LPC module when LRESET# is de-asserted */
-	if (!lpc_get_pltrst_asserted()) {
-		setup_lpc();
-	} else {
-		/* Store port 80 reset event */
-		port_80_write(PORT_80_EVENT_RESET);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		/* Notify HOOK_CHIPSET_RESET */
-		hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-	}
-#ifdef CONFIG_MCHP_DEBUG_LPC
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
-#endif
-#endif
-}
-
-/*
- * TODO - Is this only for debug of EMI host communication
- * or logging of EMI host communication? We don't observe
- * this ISR so Host is not writing to MCHP_EMI_H2E_MBX(0).
- */
-void emi0_interrupt(void)
-{
-	uint8_t h2e;
-
-	h2e = MCHP_EMI_H2E_MBX(0);
-	CPRINTS("LPC Host 0x%02x -> EMI0 H2E(0)", h2e);
-	port_80_write(h2e);
-}
-DECLARE_IRQ(MCHP_IRQ_EMI0, emi0_interrupt, 1);
-
-/*
- * ISR empties BIOS Debug 0 FIFO and
- * writes data to circular buffer. How can we be
- * sure this routine can read the last Port 80h byte?
- * MEC172x BDP capture data is different. It returns a
- * 16-bit value where bits [7:0] are the data and bits [15:7]
- * are flags indicating if the data is part of a multi-byte
- * write sequence by the host and read-only FIFO status bits.
- * The capture HW in previous chips included an optional time
- * stamp in bits[31:8] of the data register.
- */
-int port_80_read(void)
-{
-	int data = PORT_80_IGNORE;
-
-#if defined(CHIP_FAMILY_MEC172X)
-	if (MCHP_BDP0_STATUS & MCHP_BDP_STATUS_NOT_EMPTY)
-		data = MCHP_BDP0_DATTR & 0xFFU;
-#else
-	if (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY)
-		data = MCHP_P80_CAP(0) & 0xFF;
-#endif
-
-	return data;
-}
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-/*
- * Handle custom ACPI EC0 commands.
- * Some chipset CoreBoot will send read board ID command expecting
- * a two byte response.
- */
-static int acpi_ec0_custom(int is_cmd, uint8_t value,
-		uint8_t *resultptr)
-{
-	int rval;
-
-	rval = 0;
-	custom_acpi_ec2os_cnt = 0;
-	*resultptr = 0x00;
-
-	if (is_cmd && (value == 0x0d)) {
-		MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-		/* Write two bytes sequence 0xC2, 0x04 to Host */
-		if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) {
-			/* Host enabled 4-byte mode */
-			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
-			MCHP_ACPI_EC_EC2OS(0, 1) = 0x04;
-			MCHP_ACPI_EC_EC2OS(0, 2) = 0x00;
-			/* Sets OBF */
-			MCHP_ACPI_EC_EC2OS(0, 3) = 0x00;
-		} else {
-			/* single byte mode */
-			*resultptr = 0x02;
-			custom_acpi_ec2os_cnt = 1;
-			custom_apci_ec2os[0] = 0x04;
-			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
-			MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-					MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-			task_enable_irq(MCHP_IRQ_ACPIEC0_OBE);
-		}
-		custom_acpi_cmd = 0;
-		rval = 1;
-	}
-
-	return rval;
-}
-#endif
-
-void acpi_0_interrupt(void)
-{
-	uint8_t value, result, is_cmd;
-
-	is_cmd = MCHP_ACPI_EC_STATUS(0);
-
-	/* Set the bust bi */
-	MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING;
-
-	result = MCHP_ACPI_EC_BYTE_CTL(0);
-
-	/* Read command/data; this clears the FRMH bit. */
-	value = MCHP_ACPI_EC_OS2EC(0, 0);
-
-	is_cmd &= EC_LPC_STATUS_LAST_CMD;
-
-	/* Handle whatever this was. */
-	result = 0;
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		MCHP_ACPI_EC_EC2OS(0, 0) = result;
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-	else
-		acpi_ec0_custom(is_cmd, value, &result);
-#endif
-	/* Clear the busy bit */
-	MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-
-	/* Clear R/W1C status bit in Aggregator */
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty /
-	 * Output Buffer Full condition on the kernel channel/
-	 */
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-
-#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
-/*
- * ACPI EC0 output buffer empty ISR.
- * Used to handle custom ACPI EC0 command requiring
- * two byte response.
- */
-void acpi_0_obe_isr(void)
-{
-	uint8_t sts, data;
-
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-
-	sts = MCHP_ACPI_EC_STATUS(0);
-	data = MCHP_ACPI_EC_BYTE_CTL(0);
-	data = sts;
-	if (custom_acpi_ec2os_cnt) {
-		custom_acpi_ec2os_cnt--;
-		data = custom_apci_ec2os[custom_acpi_ec2os_cnt];
-	}
-
-	if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */
-		MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
-	}
-
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC0_OBE, acpi_0_obe_isr, 1);
-#endif
-
-void acpi_1_interrupt(void)
-{
-	uint8_t st = MCHP_ACPI_EC_STATUS(1);
-
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
-		return;
-
-	/* Set the busy bit */
-	MCHP_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = MCHP_ACPI_EC_OS2EC(1, 0);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request =
-			(const void *)lpc_get_hostcmd_data_range();
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so
-		 * pass in the entire buffer
-		 */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response =
-			(void *)lpc_get_hostcmd_data_range();
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-
-		host_packet_receive(&lpc_packet);
-
-	} else {
-		/* Old style command unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-
-		/* Hand off to host command handler */
-		host_command_received(&host_cmd_args);
-	}
-}
-DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
-
-#ifdef HAS_TASK_KEYPROTO
-/*
- * Reading data out of input buffer clears read-only status
- * in 8042EM. Next, we must clear aggregator status.
- */
-void kb_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MCHP_8042_H2E,
-				    MCHP_8042_STS & BIT(3));
-
-	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT;
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MCHP_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
-
-/*
- * Interrupt generated when Host reads data byte from 8042EM
- * output buffer. The 8042EM STATUS.OBF bit will clear when the
- * Host reads the data and assert its OBE signal to interrupt
- * aggregator. Clear aggregator 8042EM OBE R/WC status bit before
- * invoking task.
- */
-void kb_obe_interrupt(void)
-{
-	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT;
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1);
-#endif
-
-/*
- * Bit 0 of 8042EM STATUS register is OBF meaning EC has written
- * data to EC2HOST data register. OBF is cleared when the host
- * reads the data.
- */
-int lpc_keyboard_has_char(void)
-{
-	return (MCHP_8042_STS & BIT(0)) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	return (MCHP_8042_STS & BIT(1)) ? 1 : 0;
-}
-
-/*
- * called from common/keyboard_8042.c
- */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	MCHP_8042_E2H = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-/*
- * Read 8042 register and write to read-only register
- * insuring compiler does not optimize out the read.
- */
-void lpc_keyboard_clear_buffer(void)
-{
-	MCHP_PCR_CHIP_OSC_ID = MCHP_8042_OBF_CLR;
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	MCHP_ACPI_EC_STATUS(0) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	MCHP_ACPI_EC_STATUS(0) &= ~mask;
-}
-
-/*
- * Read hardware to determine state of platform reset signal.
- * LPC issue: Observed APL chipset changing LRESET# while LPC
- * clock is not running. This violates original LPC specification.
- * Unable to find information in APL chipset documentation
- * stating APL can change LRESET# with LPC clock not running.
- * Could this be a CoreBoot issue during CB LPC configuration?
- * We work-around this issue by reading the GPIO state.
- */
-int lpc_get_pltrst_asserted(void)
-{
-#ifdef CONFIG_HOSTCMD_ESPI
-	/*
-	 * eSPI PLTRST# a VWire or side-band signal
-	 * Controlled by CONFIG_HOSTCMD_ESPI
-	 */
-	return !espi_vw_get_wire(VW_PLTRST_L);
-#else
-	/* returns 1 if LRESET# pin is asserted(low) else 0 */
-#ifdef CONFIG_CHIPSET_APL_GLK
-	/* Use GPIO */
-	return !gpio_get_level(GPIO_PCH_PLTRST_L);
-#else
-	/* assumes LPC clock is running when host changes LRESET# */
-	return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
-#endif
-#endif
-}
-
-/* Enable LPC ACPI-EC0 interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
-}
-
-/* Disable LPC ACPI-EC0 interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(MCHP_IRQ_ACPIEC0_IBF);
-}
-
-/* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
-{
-	lpc_init();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO");
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
-
-#ifdef CONFIG_MCHP_DEBUG_LPC
-static int command_lpc(int argc, char **argv)
-{
-	if (argc == 1)
-		return EC_ERROR_PARAM1;
-
-	if (!strcasecmp(argv[1], "sci"))
-		lpc_generate_sci();
-	else if (!strcasecmp(argv[1], "smi"))
-		lpc_generate_smi();
-	else if (!strcasecmp(argv[1], "wake"))
-		lpc_update_wake(-1);
-	else
-		return EC_ERROR_PARAM1;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]",
-	"Trigger SCI/SMI");
-#endif
-
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
deleted file mode 100644
index dcb5577fc1..0000000000
--- a/chip/mchp/lpc_chip.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Microchip MEC1701 specific module for Chrome EC */
-
-#ifndef __CROS_EC_LPC_CHIP_H
-#define __CROS_EC_LPC_CHIP_H
-
-#ifdef CONFIG_HOSTCMD_ESPI
-
-#include "espi.h"
-
-#define MCHP_HOST_IF_LPC  (0)
-#define MCHP_HOST_IF_ESPI (1)
-
-/* eSPI Initialization functions */
-void espi_init(void);
-
-/* eSPI ESPI_RESET# interrupt handler */
-void espi_reset_handler(void);
-
-/*
- *
- */
-int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level);
-
-void lpc_update_host_event_status(void);
-
-#endif
-
-/* LPC LRESET interrupt handler */
-void lpcrst_interrupt(enum gpio_signal signal);
-
-void lpc_set_init_done(int val);
-
-void lpc_mem_mapped_init(void);
-
-#ifndef CONFIG_HOSTCMD_ESPI
-void lpcrst_interrupt(enum gpio_signal signal);
-#endif
-
-void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask);
-void chip_8042_config(uint32_t io_base);
-void chip_emi0_config(uint32_t io_base);
-void chip_port80_config(uint32_t io_base);
-
-#endif /* __CROS_EC_LPC_CHIP_H */
diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c
deleted file mode 100644
index ecfd0b5ebb..0000000000
--- a/chip/mchp/port80.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 Timer Interrupt for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "task.h"
-#include "tfdp_chip.h"
-
-
-#if defined(CHIP_FAMILY_MEC172X)
-/*
- * MEC172x family implements a new Port 0x80 capture block.
- * The BDP HW can capture 8, 16, and 32 bit writes.
- * Interrupt fires when BDP FIFO threshold is reached.
- * Data can be read from a 16-bit register containing:
- * b[7:0] data byte
- * b[9:8] = byte lane
- * b[11:10]= flags indicating current byte is a single byte or part of
- * a multi-byte sequence.
- * b[14:12] = copy of bits[2:0] of the status register
- * b[15] = 0 reserved
- * NOTE: The overrun bit could be used to set a flag indicating EC could
- * not keep up with the host.
- */
-void port_80_interrupt(void)
-{
-	int d = MCHP_BDP0_DATTR;
-
-	while (d & MCHP_BDP_DATTR_NE) {
-		port_80_write(d & 0xffU);
-		d = MCHP_BDP0_DATTR;
-	}
-
-	MCHP_INT_SOURCE(MCHP_BDP0_GIRQ) = MCHP_BDP0_GIRQ_BIT;
-}
-DECLARE_IRQ(MCHP_IRQ_BDP0, port_80_interrupt, 3);
-#else
-/*
- * Interrupt fires when number of bytes written
- * to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level
- * Issues:
- * 1. eSPI will not break 16-bit I/O into two 8-bit writes
- *    as LPC does. This means Port 80h hardware will capture
- *    only bits[7:0] of data.
- * 2. If Host performs write of 16-bit code as consecutive
- *    byte writes the Port 80h hardware will capture both but
- *    we do not know the order it was written.
- * 3. If Host sometimes writes one byte code to I/O 80h and
- *    sometimes two byte code to I/O 80h/81h how do we determine
- *    what to do?
- *
- * An alternative is to document Host must write 16-bit codes
- * to I/O 80h and 90h.  LSB to 0x80 and MSB to 0x90.
- *
- */
-void port_80_interrupt(void)
-{
-	int d;
-
-	while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) {
-		/*
-		 * This masks off time stamp d = port_80_read();
-		 * b[7:0] = data, b[32:8] = time stamp
-		 */
-		d = MCHP_P80_CAP(0);
-		trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff));
-		port_80_write(d & 0xff);
-	}
-
-	MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0);
-}
-DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3);
-#endif
-
diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c
deleted file mode 100644
index ae22f13ca5..0000000000
--- a/chip/mchp/pwm.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_PWM, outstr)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-
-/* Bit map of PWM channels that must remain active during low power idle. */
-static uint32_t pwm_keep_awake_mask;
-
-/* Table of PWM PCR sleep enable register index and bit position. */
-static const uint16_t pwm_pcr[] = {
-	MCHP_PCR_PWM0,
-	MCHP_PCR_PWM1,
-	MCHP_PCR_PWM2,
-	MCHP_PCR_PWM3,
-	MCHP_PCR_PWM4,
-	MCHP_PCR_PWM5,
-	MCHP_PCR_PWM6,
-	MCHP_PCR_PWM7,
-	MCHP_PCR_PWM8,
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_pcr) == MCHP_PWM_ID_MAX);
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (enabled) {
-		MCHP_PWM_CFG(id) |= BIT(0);
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |= BIT(id);
-	} else {
-		MCHP_PWM_CFG(id) &= ~BIT(0);
-		pwm_keep_awake_mask &= ~BIT(id);
-	}
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return MCHP_PWM_CFG(pwm_channels[ch].channel) & 0x1;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	MCHP_PWM_ON(id) = percent;
-	MCHP_PWM_OFF(id) = 100 - percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	return MCHP_PWM_ON(pwm_channels[ch].channel);
-}
-
-void pwm_keep_awake(void)
-{
-	if (pwm_keep_awake_mask) {
-		for (uint32_t i = 0; i < MCHP_PWM_ID_MAX; i++)
-			if (pwm_keep_awake_mask & BIT(i))
-				MCHP_PCR_SLP_DIS_DEV(pwm_pcr[i]);
-	} else {
-		MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK);
-	}
-}
-
-/*
- * clock_low=0 selects the 48MHz Ring Oscillator source
- * clock_low=1 selects the 100kHz_Clk source
- */
-static void pwm_configure(int ch, int active_low, int clock_low)
-{
-	MCHP_PWM_CFG(ch) = (15 << 3) /* divider = 16 */
-		| (active_low ? BIT(2) : 0)
-		| (clock_low  ? BIT(1) : 0);
-}
-
-static void pwm_slp_en(int pwm_id, int sleep_en)
-{
-	if ((pwm_id < 0) || (pwm_id > MCHP_PWM_ID_MAX))
-		return;
-
-	if (sleep_en)
-		MCHP_PCR_SLP_EN_DEV(pwm_pcr[pwm_id]);
-	else
-		MCHP_PCR_SLP_DIS_DEV(pwm_pcr[pwm_id]);
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm_slp_en(pwm_channels[i].channel, 0);
-		pwm_configure(pwm_channels[i].channel,
-			      pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
-			      pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
-		pwm_set_duty(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h
deleted file mode 100644
index f828a234a7..0000000000
--- a/chip/mchp/pwm_chip.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1701H-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/*
- * MEC152x SZ 144-pin has 9 PWM and 4 TACH
- * MEC170x SZ 144-pin has 9 PWM and 3 TACH
- * MEC172x SZ 144-pin has 9 PWM and 4 TACH
- */
-enum pwm_hw_id {
-	PWM_HW_CH_0 = 0,
-	PWM_HW_CH_1,
-	PWM_HW_CH_2,
-	PWM_HW_CH_3,
-	PWM_HW_CH_4,
-	PWM_HW_CH_5,
-	PWM_HW_CH_6,
-	PWM_HW_CH_7,
-	PWM_HW_CH_8,
-	PWM_HW_CH_COUNT
-};
-
-enum tach_hw_id {
-	TACH_HW_CH_0 = 0,
-	TACH_HW_CH_1,
-	TACH_HW_CH_2,
-#ifndef CHIP_FAMILY_MEC170X
-	TACH_HW_CH_3,
-#endif
-	TACH_HW_CH_COUNT
-};
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM Channel ID */
-	int channel;
-
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-void pwm_keep_awake(void);
-
-#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c
deleted file mode 100644
index 72eaa91d37..0000000000
--- a/chip/mchp/qmspi.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* QMSPI master module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "dma_chip.h"
-#include "spi_chip.h"
-#include "qmspi_chip.h"
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define QMSPI_TRANSFER_TIMEOUT (100 * MSEC)
-#define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
-
-
-
-#ifndef CONFIG_MCHP_QMSPI_TX_DMA
-#ifdef LFW
-/*
- * MCHP 32-bit timer 0 configured for 1us count down mode and no
- * interrupt in the LFW environment. Don't need to sleep CPU in LFW.
- */
-static int qmspi_wait(uint32_t mask, uint32_t mval)
-{
-	uint32_t t1, t2, td;
-
-	t1 = MCHP_TMR32_CNT(0);
-
-	while ((MCHP_QMSPI0_STS & mask) != mval) {
-		t2 = MCHP_TMR32_CNT(0);
-		if (t1 >= t2)
-			td = t1 - t2;
-		else
-			td = t1 + (0xfffffffful - t2);
-		if (td > QMSPI_BYTE_TRANSFER_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-#else
-/*
- * This version uses the full EC_RO/RW timer infrastructure and it needs
- * a timer ISR to handle timer underflow. Without the ISR we observe false
- * timeouts when debugging with JTAG.
- * QMSPI_BYTE_TRANSFER_TIMEOUT_US currently 3ms
- * QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US currently 100 us
- */
-
-static int qmspi_wait(uint32_t mask, uint32_t mval)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + (QMSPI_BYTE_TRANSFER_TIMEOUT_US);
-
-	while ((MCHP_QMSPI0_STS & mask) != mval) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-
-		usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-#endif /* #ifdef LFW */
-#endif /* #ifndef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * Wait for QMSPI read using DMA to finish.
- * DMA subsystem has 100 ms timeout
- */
-int qmspi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	const struct dma_option *opdma;
-
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	if (opdma != NULL)
-		return dma_wait(opdma->channel);
-
-	return EC_ERROR_INVAL;
-}
-
-/*
- * Create QMSPI transmit data descriptor not using DMA.
- * Transmit on MOSI pin (single/full-duplex) from TX FIFO.
- * TX FIFO filled by CPU.
- * Caller will apply close and last flags if applicable.
- */
-#ifndef CONFIG_MCHP_QMSPI_TX_DMA
-static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid)
-{
-	uint32_t d;
-
-	d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_TX_DATA;
-	d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-
-	if (ntx <= MCHP_QMSPI_C_MAX_UNITS)
-		d |= MCHP_QMSPI_C_XFRU_1B;
-	else {
-		if ((ntx & 0x0f) == 0) {
-			ntx >>= 4;
-			d |= MCHP_QMSPI_C_XFRU_16B;
-		} else if ((ntx & 0x03) == 0) {
-			ntx >>= 2;
-			d |= MCHP_QMSPI_C_XFRU_4B;
-		} else
-			d |= MCHP_QMSPI_C_XFRU_1B;
-
-		if (ntx > MCHP_QMSPI_C_MAX_UNITS)
-			return 0; /* overflow unit count field */
-	}
-
-	d |= (ntx << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-
-	return d;
-}
-
-/*
- * Create QMSPI receive data descriptor using DMA.
- * Receive data on MISO pin (single/full-duplex) and store in QMSPI
- * RX FIFO. QMSPI triggers DMA channel to read from RX FIFO and write
- * to memory. Return value is an uint64_t where low 32-bit word is the
- * descriptor and upper 32-bit word is DMA channel unit length with
- * value (1, 2, or 4).
- * Caller will apply close and last flags if applicable.
- */
-static uint64_t qmspi_build_rx_descr(uint32_t raddr,
-		uint32_t nrx, uint32_t ndid)
-{
-	uint32_t d, dmau, na;
-	uint64_t u;
-
-	d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_RX_EN;
-	d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-
-	dmau = 1;
-	na = (raddr | nrx) & 0x03;
-	if (na == 0) {
-		d |= MCHP_QMSPI_C_RX_DMA_4B;
-		dmau <<= 2;
-	} else if (na == 0x02) {
-		d |= MCHP_QMSPI_C_RX_DMA_2B;
-		dmau <<= 1;
-	} else {
-		d |= MCHP_QMSPI_C_RX_DMA_1B;
-	}
-
-	if ((nrx & 0x0f) == 0) {
-		nrx >>= 4;
-		d |= MCHP_QMSPI_C_XFRU_16B;
-	} else if ((nrx & 0x03) == 0) {
-		nrx >>= 2;
-		d |= MCHP_QMSPI_C_XFRU_4B;
-	} else {
-		d |= MCHP_QMSPI_C_XFRU_1B;
-	}
-
-	u = 0;
-	if (nrx <= MCHP_QMSPI_C_MAX_UNITS) {
-		d |= (nrx << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-		u = dmau;
-		u <<= 32;
-		u |= d;
-	}
-
-	return u;
-}
-#endif
-
-#ifdef CONFIG_MCHP_QMSPI_TX_DMA
-
-#define QMSPI_ERR_ANY			0x80
-#define QMSPI_ERR_BAD_PTR		0x81
-#define QMSPI_ERR_OUT_OF_DESCR		0x85
-
-/*
- * bits[1:0] of word
- * 1 -> 0
- * 2 -> 1
- * 4 -> 2
- */
-static uint32_t qmspi_pins_encoding(uint8_t npins)
-{
-	return (uint32_t)(npins >> 1) & 0x03;
-}
-
-/*
- * Clear status, FIFO's, and all descriptors.
- * Enable descriptor mode.
- */
-static void qmspi_descr_mode_ready(void)
-{
-	int i;
-
-	MCHP_QMSPI0_CTRL = 0;
-	MCHP_QMSPI0_IEN  = 0;
-	MCHP_QMSPI0_EXE  = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS  = 0xfffffffful;
-	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
-	/* clear all descriptors */
-	for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++)
-		MCHP_QMSPI0_DESCR(i) = 0;
-}
-
-/*
- * helper
- * did = zero based index of start descriptor
- * descr = descriptor configuration
- * nb = number of bytes to transfer
- * Return index of last descriptor allocated or 0xffff
- * if out of descriptors.
- * Algorithm:
- * If requested number of bytes will fit in one descriptor then
- * configure descriptor for QMSPI byte units and return.
- * Otherwise allocate multiple descriptor using QMSPI 16-byte mode
- * and remaining < 16 bytes in byte unit descriptor until all bytes
- * exhausted or out of descriptors error.
- */
-static uint32_t qmspi_descr_alloc(uint32_t did,
-				uint32_t descr, uint32_t nb)
-{
-	uint32_t nu;
-
-	while (nb) {
-		if (did >= MCHP_QMSPI_MAX_DESCR)
-			return 0xffff;
-
-		descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK +
-			MCHP_QMSPI_C_XFRU_MASK);
-
-		if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) {
-			descr |= MCHP_QMSPI_C_XFRU_1B;
-			descr += (nb << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-			nb = 0;
-		} else {
-			descr |= MCHP_QMSPI_C_XFRU_16B;
-			nu = (nb >> 4) & MCHP_QMSPI_C_NUM_UNITS_MASK0;
-			descr += (nu << MCHP_QMSPI_C_NUM_UNITS_BITPOS);
-			nb -= (nu << 4);
-		}
-
-		descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-		MCHP_QMSPI0_DESCR(did) = descr;
-		if (nb)
-			did++;
-	}
-
-	return did;
-}
-
-/*
- * Build one or more descriptors for command/data transmit.
- * cfg b[7:0] = start descriptor index
- * cfg b[15:8] = number of pins for transmit.
- * If bytes to transmit will fit in TX FIFO then fill TX FIFO and build
- * one descriptor.
- * Otherwise build one or more descriptors to fill TX FIFO using DMA
- * channel and configure the DMA channel for memory to device transfer.
- */
-static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
-					uint32_t cfg,
-					const uint8_t *data,
-					uint32_t ndata)
-{
-	uint32_t d, d2, did, dma_cfg;
-
-	did = cfg & 0x0f;
-	d = qmspi_pins_encoding((cfg >> 8) & 0x07);
-
-	if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) {
-		d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) +
-			MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
-		d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
-		MCHP_QMSPI0_DESCR(did) = d2;
-		while (ndata--)
-			MCHP_QMSPI0_TX_FIFO8 = *data++;
-	} else { // TX DMA
-		if (((uint32_t)data | ndata) & 0x03) {
-			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_1B);
-		} else {
-			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_4B);
-		}
-		did = qmspi_descr_alloc(did, d, ndata);
-		if (did == 0xffff)
-			return QMSPI_ERR_OUT_OF_DESCR;
-
-		dma_clr_chan(opdma->channel);
-		dma_cfg_buffers(opdma->channel, data, ndata,
-			(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_TX_REQ_ID,
-			(DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
-		dma_run(opdma->channel);
-	}
-
-	return did;
-}
-
-/*
- * QMSPI0 Start
- * flags
- *  b[0] = 1 de-assert chip select when done
- *  b[1] = 1 enable QMSPI interrupts
- *  b[2] = 1 start
- */
-void qmspi_cfg_irq_start(uint8_t flags)
-{
-	MCHP_INT_DISABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	MCHP_INT_SOURCE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	MCHP_QMSPI0_IEN = 0;
-
-	if (flags & (1u << 1)) {
-		MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE +
-			MCHP_QMSPI_STS_PROG_ERR);
-		MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
-	}
-
-	if (flags & (1u << 2))
-		MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
-}
-
-/*
- * QMSPI transmit and/or receive
- * np_flags
- *  b[7:0] = flags
- *	b[0] = close(de-assert chip select when done)
- *	b[1] = enable Done and ProgError interrupt
- *	b[2] = start
- *  b[15:8] = number of tx pins
- *  b[24:16] = number of rx pins
- *
- * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
- * or error (bit[7]==1)
- */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx)
-{
-	uint32_t d, did, dma_cfg;
-	const struct dma_option *opdma;
-
-	qmspi_descr_mode_ready();
-
-	did = 0;
-	if (ntx) {
-		if (txdata == NULL)
-			return QMSPI_ERR_BAD_PTR;
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-
-		d = qmspi_pins_encoding((np_flags >> 8) & 0xff);
-		dma_cfg = (np_flags & 0xFF00) + did;
-		did = qmspi_xmit_data_descr(opdma, dma_cfg, txdata, ntx);
-		if (did & QMSPI_ERR_ANY)
-			return (uint8_t)(did & 0xff);
-
-		if (nrx)
-			did++; /* point to next descriptor */
-	}
-
-	if (nrx) {
-		if (rxdata == NULL)
-			return QMSPI_ERR_BAD_PTR;
-
-		if (did >= MCHP_QMSPI_MAX_DESCR)
-			return QMSPI_ERR_OUT_OF_DESCR;
-
-		d = qmspi_pins_encoding((np_flags >> 16) & 0xff);
-		/* compute DMA units: 1 or 4 */
-		if (((uint32_t)rxdata | nrx) & 0x03) {
-			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_1B);
-		} else {
-			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_4B);
-		}
-		did = qmspi_descr_alloc(did, d, nrx);
-		if (did & QMSPI_ERR_ANY)
-			return (uint8_t)(did & 0xff);
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-		dma_clr_chan(opdma->channel);
-		dma_cfg_buffers(opdma->channel, rxdata, nrx,
-			(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_RX_REQ_ID,
-			(DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
-		dma_run(opdma->channel);
-	}
-
-	if (ntx || nrx) {
-		d = MCHP_QMSPI0_DESCR(did);
-		d |= MCHP_QMSPI_C_DESCR_LAST;
-		if (np_flags & 0x01)
-			d |= MCHP_QMSPI_C_CLOSE;
-		MCHP_QMSPI0_DESCR(did) = d;
-		qmspi_cfg_irq_start(np_flags & 0xFF);
-	}
-
-	return (uint8_t)(did & 0xFF);
-}
-#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * QMSPI controller must control chip select therefore this routine
- * configures QMSPI to assert SPI CS# and de-assert when done.
- * Transmit using QMSPI TX FIFO only when tx data fits in TX FIFO else
- * use TX DMA.
- * Transmit and receive will allocate as many QMSPI descriptors as
- * needed for data size. This could result in an error if the maximum
- * number of descriptors is exceeded.
- * Descriptors are limited to 0x7FFF units where unit size is 1, 4, or
- * 16 bytes. Code determines unit size based upon number of bytes and
- * alignment of data buffer.
- * DMA channel will move data in units of 1 or 4 bytes also based upon
- * the number of data bytes and buffer alignment.
- * The most efficient transfers are those where TX and RX buffers are
- * aligned >= 4 bytes and the number of bytes is a multiple of 4.
- * NOTE on SPI flash commands:
- * This routine does NOT handle SPI flash commands requiring
- * extra clocks or special mode bytes. Extra clocks and special mode
- * bytes require additional descriptors. For example the flash read
- * dual command (0x3B):
- * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on
- *    one pin (IO0).
- * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When
- *    this descriptor is executed QMSPI will tri-state IO0 & IO1 and
- *    output 8 clocks (dual mode 4 clocks per byte). The SPI flash may
- *    turn on its output drivers on the first clock.
- * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit
- *    size and DMA unit size based on number of bytes to read and
- *    alignment of destination buffer.
- * The common SPI API will be required to supply more information about
- * SPI flash read commands.  A further complication is some larger SPI
- * flash devices support a 4-byte address mode. 4-byte address mode can
- * be implemented as separate command code or a configuration bit in
- * the SPI flash that changes the default 24-bit address command to
- * require a 32-bit address.
- * 0x03 is 1-1-1
- * 0x3B is 1-1-2 with 8 clocks
- * 0x6B is 1-1-4 with 8 clocks
- * 0xBB is 1-2-2 with 4 clocks
- * Number of IO pins for command
- * Number of IO pins for address
- * Number of IO pins for data
- * Number of bit/bytes for address (3 or 4)
- * Number of clocks after address phase
- */
-#ifdef CONFIG_MCHP_QMSPI_TX_DMA
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	uint32_t np_flags, ntx, nrx;
-	int ret;
-	uint8_t rc;
-
-	ntx = 0;
-	if (txlen >= 0)
-		ntx = (uint32_t)txlen;
-
-	nrx = 0;
-	if (rxlen >= 0)
-		nrx = (uint32_t)rxlen;
-
-	np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */
-	rc = qmspi_xfr(spi_device, np_flags,
-			txdata, ntx,
-			rxdata, nrx);
-
-	if (rc & QMSPI_ERR_ANY)
-		return EC_ERROR_INVAL;
-
-	ret = EC_SUCCESS;
-	return ret;
-}
-#else
-/*
- * Transmit using CPU and QMSPI TX FIFO(no DMA).
- * Receive using DMA as above.
- */
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	const struct dma_option *opdma;
-	uint32_t d, did, dmau;
-	uint64_t u;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	/* soft reset the controller */
-	MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-	d = spi_device->div;
-	d <<= MCHP_QMSPI_M_CLKDIV_BITPOS;
-	d += (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0);
-	MCHP_QMSPI0_MODE = d;
-	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
-
-	d = did = 0;
-
-	if (txlen > 0) {
-		if (txdata == NULL)
-			return EC_ERROR_PARAM2;
-
-		d = qmspi_build_tx_descr((uint32_t)txlen, 1);
-		if (d == 0) /* txlen too large */
-			return EC_ERROR_OVERFLOW;
-
-		MCHP_QMSPI0_DESCR(did) = d;
-	}
-
-	if (rxlen > 0) {
-		if (rxdata == NULL)
-			return EC_ERROR_PARAM4;
-
-		u = qmspi_build_rx_descr((uint32_t)rxdata,
-				(uint32_t)rxlen, 2);
-
-		d = (uint32_t)u;
-		dmau = u >> 32;
-
-		if (txlen > 0)
-			did++;
-		MCHP_QMSPI0_DESCR(did) = d;
-
-		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-		dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata);
-	}
-
-	MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE +
-			MCHP_QMSPI_C_DESCR_LAST);
-
-	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
-
-	while (txlen--) {
-		if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) {
-			if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY,
-					MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
-							EC_SUCCESS) {
-				MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
-				return EC_ERROR_TIMEOUT;
-			}
-		} else
-			MCHP_QMSPI0_TX_FIFO8 = *txdata++;
-	}
-
-	return EC_SUCCESS;
-}
-#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */
-
-/*
- * Wait for QMSPI descriptor mode transfer to finish.
- * QMSPI is configured to perform a complete transaction.
- * Assert CS#
- * optional transmit
- *   CPU keeps filling TX FIFO until all bytes are transmitted.
- * optional receive
- *   QMSPI is configured to read rxlen bytes and uses a DMA channel
- *   to move data from its RX FIFO to memory.
- * De-assert CS#
- * This routine can be called with QMSPI hardware in four states:
- * 1. Transmit only and QMSPI has finished (empty TX FIFO) by the time
- *    this routine is called. QMSPI.Status transfer done status will be
- *    set and QMSPI HW has de-asserted SPI CS#.
- * 2. Transmit only and QMSPI TX FIFO is still transmitting.
- *    QMSPI transfer done status is not asserted and CS# is still
- *    asserted. QMSPI HW will de-assert CS# when done or firmware
- *    manually stops QMSPI.
- * 3. Receive was enabled and DMA channel is moving data from
- *    QMSPI RX FIFO to memory. QMSPI.Status transfer done and DMA done
- *    status bits are not set. QMSPI SPI CS# will stay asserted until
- *    transaction finishes or firmware manually stops QMSPI.
- * 4. Receive was enabled and DMA channel is finished. QMSPI RX FIFO
- *    should be empty and DMA channel is done.  QMSPI.Status transfer
- *    done and DMA done status bits will be set. QMSPI HW has de-asserted
- *    SPI CS#.
- * We are using QMSPI in descriptor mode. The definition of QMSPI.Status
- * transfer complete bit in this mode is: complete will be set to 1 only
- * when the last buffer completes its transfer.
- * TX only sets complete when transfer unit count is matched and all units
- * have been clocked out of the TX FIFO.
- * RX DMA transfer complete will be set when the last transfer unit
- * is out of the RX FIFO but DMA may not be complete until it finishes
- * moving the transfer unit to memory.
- * If TX only spin on QMSPI.Status Transfer_Complete bit.
- * If RX used spin on QMsPI.Status Transfer_Complete and DMA_Complete.
- * Search descriptors looking for RX DMA enabled.
- * If RX DMA is enabled add DMA complete flag to status mask.
- * Spin while QMSPI.Status & mask != mask or timeout.
- * If timeout force QMSPI to stop and exit spin loop.
- * if DMA was enabled disable DMA channel.
- * Clear QMSPI.Status and FIFO's
- */
-int qmspi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int ret;
-	uint32_t qsts, mask;
-	const struct dma_option *opdma;
-	timestamp_t deadline;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-	mask = MCHP_QMSPI_STS_DONE;
-
-	ret = EC_SUCCESS;
-	deadline.val = get_time().val + QMSPI_TRANSFER_TIMEOUT;
-
-	qsts = MCHP_QMSPI0_STS;
-	while ((qsts & mask) != mask) {
-		if (timestamp_expired(deadline, NULL)) {
-			MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
-			ret = EC_ERROR_TIMEOUT;
-			break;
-		}
-		usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-		qsts = MCHP_QMSPI0_STS;
-	}
-
-	/* clear transmit DMA channel */
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR);
-	if (opdma == NULL)
-		return EC_ERROR_INVAL;
-
-	dma_disable(opdma->channel);
-	dma_clear_isr(opdma->channel);
-
-	/* clear receive DMA channel */
-	opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
-	if (opdma == NULL)
-		return EC_ERROR_INVAL;
-
-	dma_disable(opdma->channel);
-	dma_clear_isr(opdma->channel);
-
-	/* clear QMSPI FIFO's */
-	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS = 0xffffffff;
-
-	return ret;
-}
-
-/**
- * Enable QMSPI controller and MODULE_SPI_FLASH pins.
- *
- * @param hw_port b[3:0]=0 and b[7:4]=0
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called by spi_enable in mec1701/spi.c
- *
- */
-int qmspi_enable(int hw_port, int enable)
-{
-	uint8_t unused __attribute__((unused)) = 0;
-
-	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d",
-			hw_port, enable);
-
-	if (hw_port != QMSPI0_PORT)
-		return EC_ERROR_INVAL;
-
-	gpio_config_module(MODULE_SPI_FLASH, (enable > 0));
-
-	if (enable) {
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI);
-		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE +
-				MCHP_QMSPI_M_SPI_MODE0 +
-				MCHP_QMSPI_M_CLKDIV_12M);
-	} else {
-		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE_ACT_SRST = 0;
-		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h
deleted file mode 100644
index 1a1d764267..0000000000
--- a/chip/mchp/qmspi_chip.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC17xx processor
- */
-/** @file qmspi_chip.h
- *MEC17xx Quad SPI Master
- */
-/** @defgroup MCHP MEC qmspi
- */
-
-#ifndef _QMSPI_CHIP_H
-#define _QMSPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-
-int qmspi_transaction_flush(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_wait(const struct spi_device_t *spi_device);
-
-int qmspi_transaction_sync(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
-
-int qmspi_enable(int port, int enable);
-
-/*
- * QMSPI0 Start
- * flags
- *  b[0] = ignored
- *  b[1] = 1 enable QMSPI interrupts
- *  b[2] = 1 start
- */
-void qmspi_cfg_irq_start(uint8_t flags);
-
-/*
- * QMSPI transmit and/or receive
- * np_flags
- *  b[7:0] = flags
- *	b[0] = close(de-assert chip select when done)
- *	b[1] = enable Done and ProgError interrupt
- *	b[2] = start
- *  b[15:8] = number of tx pins
- *  b[24:16] = number of rx pins
- *
- * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
- * or error (bit[7]==1)
- */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx);
-
-#endif /* #ifndef _QMSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h
deleted file mode 100644
index 10021ede8b..0000000000
--- a/chip/mchp/registers-mec152x.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC152x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
-#define MCHP_IRQ_I2C_5		168
-#define MCHP_IRQ_I2C_6		169
-#define MCHP_IRQ_I2C_7		170
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_UART2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-#define MCHP_IRQ_LASIC		64
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_HDMI_CEC	160
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_PROCHOT	87
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PSPI		155
-#define MCHP_IRQ_SGPIO_0	161
-#define MCHP_IRQ_SGPIO_1	162
-#define MCHP_IRQ_SGPIO_2	163
-#define MCHP_IRQ_SGPIO_3	164
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-/* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_KSC_INT	135
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX		174
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_I2C5_BASE		0x40005100
-#define MCHP_I2C6_BASE		0x40005200
-#define MCHP_I2C7_BASE		0x40005300
-#define MCHP_QMSPI0_BASE	0x40070000
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_UART2_BASE		0x400f2c00
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MCHP AHB masters do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
-/* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
-/* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
-#define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
-
-/*
- * PCR Peripheral Reset Lock register
- * MEC152x PCR Peripheral reset registers do not reset on
- * peripheral sleep. The peripheral is reset immediately.
- * Firmware must write an unlock value to this new lock
- * register, write to PCR reset enable register(s), and
- * write a lock value.
- */
-#define MCHP_PCR_RST_LOCK		REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL		0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL		0xa6382d4c
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX	5
-
-/* MC152x new bit allow sleep entry when PLL is not locked */
-#define MCHP_PCR_SYS_SLP_NO_PLL		BIT(8)
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG	BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP	BIT(1)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_UART2		MCHP_PCR_ERB(2, 28)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ASIF		MCHP_PCR_ERB(2, 24)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_UART2		BIT(28)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ASIF		BIT(24)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-#define MCHP_PCR_HDMI_CEC	MCHP_PCR_ERB(3, 1)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_HDMI_CEC	BIT(1)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xfffffffd
-#define MCHP_PCR_SLP_EN3_PWM_ALL	0
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_SGPIO3		MCHP_PCR_ERB(4, 20)
-#define MCHP_PCR_SGPIO2		MCHP_PCR_ERB(4, 19)
-#define MCHP_PCR_SGPIO1		MCHP_PCR_ERB(4, 18)
-#define MCHP_PCR_SGPIO0		MCHP_PCR_ERB(4, 17)
-#define MCHP_PCR_SLV_SPI	MCHP_PCR_ERB(4, 16)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_I2C7		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_I2C6		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_I2C5		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_SGPIO3		BIT(20)
-#define MCHP_PCR_SLP_EN4_SGPIO2		BIT(19)
-#define MCHP_PCR_SLP_EN4_SGPIO1		BIT(18)
-#define MCHP_PCR_SLP_EN4_SGPIO0		BIT(17)
-#define MCHP_PCR_SLP_EN4_SLV_SPI	BIT(16)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_I2C7		BIT(12)
-#define MCHP_PCR_SLP_EN4_I2C6		BIT(11)
-#define MCHP_PCR_SLP_EN4_I2C5		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL	0
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE	(~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE	(~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE	(~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE	(~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE	(~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT		BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT		BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT			BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN		BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS			BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT			BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR			BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST			BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD		BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR				REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO				REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN			REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL			REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN			REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN				REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT				REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL		REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_VCI_FW_OVRD			REG8(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_CRYPTO_SRESET			REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR			REG8(MCHP_EC_BASE + 0x64)
-#define MCHP_EC_SLP_STS_MIRROR			REG8(MCHP_EC_BASE + 0x114)
-
-/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE	0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN	0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV	0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD	0x04
-
-/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
-
-/* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN		20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST		8
-#define MCHP_INT_GIRQ_LAST		26
-#define MCHP_INT_GIRQ_NUM		(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
-
-/* GIRQ13 I2C controllers. Direct capable */
-#define MCHP_INT13_I2C(x) (1ul << (x))
-
-/* GIRQ14 DMA channels 0 - 11. Direct capable */
-#define MCHP_INT14_DMA(x) (1ul << (x))
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_UART_2		BIT(4)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_HDMI_CEC		BIT(5)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_PROCHOT		BIT(17)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SLV_SPI		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_OPT			BIT(3)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDT			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SLV_SPI	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_I2C5	BIT(6)
-#define MCHP_INT22_WAKE_ONLY_I2C6	BIT(7)
-#define MCHP_INT22_WAKE_ONLY_I2C7	BIT(8)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_RTMR			BIT(10)
-#define MCHP_INT23_HTMR_0		BIT(16)
-#define MCHP_INT23_HTMR_1		BIT(17)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 2 */
-#define MCHP_UART_INSTANCES		3
-#define MCHP_UART_SPACING		0x400
-#define MCHP_UART_CFG_OFS		0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ			15
-#define MCHP_UART0_GIRQ_BIT		(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT		(MCHP_INT15_UART_1)
-#define MCHP_UART2_GIRQ_BIT		(MCHP_INT15_UART_2)
-#define MCHP_UART_GIRQ_BIT(x)		BIT(x)
-/* BIT defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY		BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT 6
-#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
-
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS		0
-#define MCHP_GPIO_CTRL_PUD_MASK0		0x03
-#define MCHP_GPIO_CTRL_PUD_MASK			0x03
-#define MCHP_GPIO_CTRL_PUD_NONE			0x00
-#define MCHP_GPIO_CTRL_PUD_PU			0x01
-#define MCHP_GPIO_CTRL_PUD_PD			0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER		0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS		2
-#define MCHP_GPIO_CTRL_PWR_MASK0		0x03
-#define MCHP_GPIO_CTRL_PWR_MASK			(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR			(0x00 << 2)
-#define MCHP_GPIO_CTRL_PWR_OFF			(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK			0xF0
-#define MCHP_GPIO_INTDET_LVL_LO			0x00
-#define MCHP_GPIO_INTDET_LVL_HI			0x10
-#define MCHP_GPIO_INTDET_DISABLED		0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS		0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL		0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH		0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN		BIT(7)
-#define MCHP_GPIO_PUSH_PULL			0u
-#define MCHP_GPIO_OPEN_DRAIN			BIT(8)
-#define MCHP_GPIO_INPUT				0u
-#define MCHP_GPIO_OUTPUT			BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL			0u
-#define MCHP_GPIO_OUTSEL_PAR			BIT(10)
-#define MCHP_GPIO_POLARITY_NINV			0u
-#define MCHP_GPIO_POLARITY_INV			BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS		12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0		0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK		(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO		(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1			(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2			(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3			(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL			BIT(16)
-/* MEC15xx only */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS		15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT		BIT(15)
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING		0x20
-#define MCHP_TMR16_INSTANCES		2
-#define MCHP_TMR32_INSTANCES		2
-#define MCHP_TMR16_MAX			(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX			(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	\
-	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	\
-	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ			23
-#define MCHP_TMR16_GIRQ_BIT(n)		BIT(0 + (n))
-#define MCHP_TMR32_GIRQ			23
-#define MCHP_TMR32_GIRQ_BIT(n)		BIT(4 + (n))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ			23
-#define MCHP_RTMR_GIRQ_BIT(x)		BIT(10)
-
-/* Watchdog */
-/* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
-/* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
-/* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
-/* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 16 */
-#define MCHP_VBAT_RAM_SIZE		64
-#define MCHP_VBAT_RAM(wnum)		REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		14
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch pad RAM
- */
-#define MCHP_IMAGETYPE_IDX	15
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
-
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS		2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK		BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT		0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL		BIT(2)
-
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS		1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK		BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON		0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN		BIT(1)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	3
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	2
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n)	(MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
-#define MCHP_P80_BASE(n)	\
-	(MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
-#define MCHP_P80_HOST_DATA(n)	REG8(MCHP_P80_BASE(n))
-/* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
-/*
- * Port 80 Data register bits
- * bits[7:0] = data captured on Host write
- * bits[31:8] = optional time stamp
- */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
-	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
-
-/* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
-	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
-/* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
-/* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK	\
-	((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
-
-/* PWM */
-#define MCHP_PWM_INSTANCES	9
-#define MCHP_PWM_ID_MAX		(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING	16
-#define MCHP_PWM_BASE(x)	(MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x)	\
-	(MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES	4
-#define MCHP_ACPI_EC_MAX	(ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING	0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE		\
-	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/*
- * I2C controllers 0 - 4 include SMBus network layer functionality.
- * I2C controllers 5 - 7 are I2C only and include slave mode
- * promiscuous functionality.
- */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL5		5
-#define MCHP_I2C_CTRL6		6
-#define MCHP_I2C_CTRL7		7
-#define MCHP_I2C_CTRL_MAX	8
-
-#define MCHP_I2C_SEP0		0x400
-#define MCHP_I2C_SEP1		0x100
-
-/*
- * MEC152xH 144-pin package has eight I2C controllers and sixteen ports.
- * Any port can be mapped to any I2C controller.
- *
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C mutex array, etc.
- *
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- *
- * Locking must occur by-controller (not by-port).
- * I2C00_SCL/SDA on GPIO004 F1, GPIO003 F1
- * I2C01_SCL/SDA on GPIO0131 F1, GPIO130 F1
- *	Alternate pins: GPIO073 F2, GPIO072 F2
- * I2C02_SCL/SDA on GPIO0155 F1, GPIO0154 F1
- * I2C03_SCL/SDA on GPIO010 F1, GPIO007 F1
- * I2C04_SCL/SDA on GPIO0144 F1, GPIO0143 F1
- * I2C05_SCL/SDA on GPIO0142 F1, GPIO0141 F1
- * I2C06_SCL/SDA on GPIO0140 F1, GPIO0132 F1
- * I2C07_SCL/SDA on GPIO013 F1, GPIO012 F1
- *	Alternate pins: GPIO0024 F3, GPIO0152 F3
- * I2C08_SCL/SDA on GPIO012 F1, GPIO0211 F1
- * I2C09_SCL/SDA on GPIO0146 F1, GPIO0145 F1
- * I2C10_SCL/SDA on GPIO0107 F3, GPIO030 F2
- * I2C11_SCL/SDA on GPIO062 F2, GPIO000 F3
- * I2C12_SCL/SDA on GPIO027 F3, GPIO026 F3
- * I2C13_SCL/SDA on GPIO065 F2, GPIO066 F2
- * I2C14_SCL/SDA on GPIO071 F2, GPIO070 F2
- * I2C15_SCL/SDA on GPIO0150 F1, GPIO0147 F1
- */
-
-#define MCHP_MEC1521SZ_I2C_PORT_MASK	0xFEFFul
-#define MCHP_MEC1523SZ_I2C_PORT_MASK	0xFFFFul
-
-#define MCHP_I2C_PORT_MASK	MCHP_MEC1521SZ_I2C_PORT_MASK
-
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT11,
-	MCHP_I2C_PORT12,
-	MCHP_I2C_PORT13,
-	MCHP_I2C_PORT14,
-	MCHP_I2C_PORT15,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
-
-/*
- * I2C controllers 0-4 implement network layer hardware.
- * I2C controllers 5-7 do include network layer hardware.
- * MEC152x has I2C promiscuous mode feature in the following
- * additional registers.
- */
-#define MCHP_I2C_SLAVE_ADDR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x6c))
-#define MCHP_I2C_PROM_INTR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x70))
-#define MCHP_I2C_PROM_INTR_EN(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x74))
-#define MCHP_I2C_PROM_CTRL(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x78))
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ			21
-#define MCHP_KS_GIRQ_BIT		BIT(25)
-#define MCHP_KS_DIRECT_NVIC		135
-
-/* ADC */
-#define MCHP_ADC_GIRQ				17
-#define MCHP_ADC_GIRQ_SINGLE_BIT		BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT		BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC		78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC		79
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING			0x20
-#define MCHP_HTIMER_ADDR(n)		\
-	(MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ			23
-/* HTIMER[0:1] -> GIRQ23 bits[16:17] */
-#define MCHP_HTIMER_GIRQ_BIT(n)			BIT(16 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)		(112 + (n))
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC152x implements 16 descriptors, support for two chip selects,
- * and additional SPI signal timing registers.
- */
-#define MCHP_QMSPI_MAX_DESCR	16
-/*
- * Chip select implemented in bit[13:12] of the Mode register.
- * These bits are reserved in earlier chips.
- */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	(0x03 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS0	(0x00 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS1	(0x01 << MCHP_QMSPI_M_CS_POS)
-
-/* New QMSPI chip select timing register */
-#define MCHP_QMSPI_CS_TIMING			\
-	REG32(MCHP_QMSPI0_BASE + 0x28)
-#define MCHP_QMSPI_CST_DFLT_VAL			0x06060406
-#define MCHP_QMSPI_CST_ON2CLK_MASK		0x0f
-#define MCHP_QMSPI_CST_ON2CLK_DFLT		0x06
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS		8
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0	0x0f
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK		0x0f00
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT		0x0400
-#define MCHP_QMSPI_CST_DLY_LDH_POS		16
-#define MCHP_QMSPI_CST_DLY_LDH_MASK0		0x0f
-#define MCHP_QMSPI_CST_DLY_LDH_MASK		0xf0000
-#define MCHP_QMSPI_CST_DLY_LDH_DFLT		0x60000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_POS		24
-#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT		0x06000000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0		0xff
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK		0xff000000
-
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
-
-/* eSPI */
-
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_ID_UART2	0x15
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-#define MCHP_ESPI_SIRQ_UART2		19
-
-#define MCHP_ESPI_MSVW_BASE	(MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE	((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
-
-/*
- * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
- */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v)		(24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	12
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE	(MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- * On MCHP, any DMA channel may serve any device. Since we have
- * 12 channels and 12 devices request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_I2C4_SLAVE,
-	MCHP_DMAC_I2C4_MASTER,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR	0x10000000
-#define MCHP_USEC_DELAY(x)		(REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h
deleted file mode 100644
index bfe012a0d8..0000000000
--- a/chip/mchp/registers-mec1701.h
+++ /dev/null
@@ -1,1350 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC170x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-#define MCHP_IRQ_PWRGRD0	88
-#define MCHP_IRQ_PWRGRD1	89
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_LPC		90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_BCM1_ERR	98
-#define MCHP_IRQ_BCM1_BUSY	99
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PS2_2		102
-#define MCHP_IRQ_EEPROM		155
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_VCI_IN5	127
-#define MCHP_IRQ_VCI_IN6	128
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21A_WAKE	131
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_PS2_2_WAKE	133
-#define MCHP_IRQ_ENVMON		134
-#define MCHP_IRQ_KSC_INT	135
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX 157
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000000
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_QMSPI0_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MCHP AHB masters do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 8-bit Device ID */
-#define MCHP_CHIP_DEV_ID	REG8(MCHP_CHIP_BASE + 0x20)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX 5
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_LPC		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_LPC		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_2		MCHP_PCR_ERB(3, 7)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_2		BIT(7)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_FJCL		MCHP_PCR_ERB(4, 15)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_BCM1		MCHP_PCR_ERB(4, 9)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_FJCL		BIT(15)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
-
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL \
-	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x060
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
-/* same function, old bit name */
-#define MCHP_PWR_RST_STS_VTR		BIT(6)
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR			REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO			REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN		REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL		REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN		REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN			REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT			REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL	REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_PECI_DISABLE		REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_CRYPTO_SRESET		REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR		REG8(MCHP_EC_BASE + 0x64)
-
-/* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
-
-/* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
-
-/* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
-
-/* GIRQ13 I2C controllers. Direct capable */
-#define MCHP_INT13_I2C(x) (1ul << (x))
-
-/* GIRQ14 DMA channels 0 - 13. Direct capable */
-#define MCHP_INT14_DMA(x) (1ul << (x))
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(4)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(5)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(6)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(7)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_PWRGRD0		BIT(18)
-#define MCHP_INT17_PWRGRD1		BIT(19)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_LPC_ERR		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_BCM1_BUSY		BIT(8)
-#define MCHP_INT18_BCM1_ERR		BIT(9)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_PS2_2		BIT(12)
-#define MCHP_INT18_PSPI			BIT(13)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_ISPI			BIT(8)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_RTMR			BIT(0)
-#define MCHP_INT21_HTMR_0		BIT(1)
-#define MCHP_INT21_HTMR_1		BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_VCI_IN5		BIT(16)
-#define MCHP_INT21_VCI_IN6		BIT(17)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1A_WAKE		BIT(20)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_PS2_2_WAKE		BIT(22)
-#define MCHP_INT21_ENVMON		BIT(24)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_LPC	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT23_CCT			BIT(10)
-#define MCHP_INT23_CCT_CAP0		BIT(11)
-#define MCHP_INT23_CCT_CAP1		BIT(12)
-#define MCHP_INT23_CCT_CAP2		BIT(13)
-#define MCHP_INT23_CCT_CAP3		BIT(14)
-#define MCHP_INT23_CCT_CAP4		BIT(15)
-#define MCHP_INT23_CCT_CAP6		BIT(16)
-#define MCHP_INT23_CCT_CMP0		BIT(17)
-#define MCHP_INT23_CCT_CMP1		BIT(18)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- *
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10
-#define MCHP_GPIO_INTDET_DISABLED	0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0u
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0u
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0u
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0u
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1		(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
-/* MEC170x reserved read-only 0 bit. Value set to 0 */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	0
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
-
-/* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch RAM
- */
-#define MCHP_IMAGETYPE_IDX	31
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
-
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS	2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK	BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT	0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL	BIT(2)
-
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS	1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK	BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON	0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN	BIT(1)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
-#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
-#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
-/* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
-/*
- * Port 80 Data register bits
- * bits[7:0] = data captured on Host write
- * bits[31:8] = optional time stamp
- */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
-	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
-
-/* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
-	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
-/* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
-/* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
-
-/* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	3
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL_MAX	4
-
-#define MCHP_I2C_SEP0		0x400
-
-/*
- * MEC1701H 144-pin package has four I2C controllers and eleven ports.
- * Any port can be mapped to any I2C controller.
- * NOTE: 144-pin package does not implement port 1.
- *
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C mutex array, etc.
- *
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- *
- * Locking must occur by-controller (not by-port).
- */
-#define MCHP_I2C_PORT_MASK 0x07FDul
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,	/* port 1, do not use. pins not present */
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
-
-/* ADC */
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
-/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
-
-/* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
-/* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
-/* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC1701 implements 5 descriptors and a single chip select.
- */
-#define MCHP_QMSPI_MAX_DESCR	5
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
-
-/* LPC */
-#define MCHP_LPC_RT_BASE	(MCHP_LPC_BASE + 0x100)
-#define MCHP_LPC_CFG_BASE	(MCHP_LPC_BASE + 0x300)
-#define MCHP_LPC_ACT		REG8(MCHP_LPC_CFG_BASE + 0x30)
-#define MCHP_LPC_SIRQ(x)	REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
-#define MCHP_LPC_CFG_BAR	REG32(MCHP_LPC_CFG_BASE + 0x60)
-#define MCHP_LPC_MAILBOX_BAR	REG32(MCHP_LPC_CFG_BASE + 0x64)
-#define MCHP_LPC_8042_BAR	REG32(MCHP_LPC_CFG_BASE + 0x68)
-#define MCHP_LPC_ACPI_EC0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x6C)
-#define MCHP_LPC_ACPI_EC1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x70)
-#define MCHP_LPC_ACPI_EC2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x74)
-#define MCHP_LPC_ACPI_EC3_BAR	REG32(MCHP_LPC_CFG_BASE + 0x78)
-#define MCHP_LPC_ACPI_EC4_BAR	REG32(MCHP_LPC_CFG_BASE + 0x7C)
-#define MCHP_LPC_ACPI_PM1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x80)
-#define MCHP_LPC_PORT92_BAR	REG32(MCHP_LPC_CFG_BASE + 0x84)
-#define MCHP_LPC_UART0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x88)
-#define MCHP_LPC_UART1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x8C)
-#define MCHP_LPC_EMI0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x90)
-#define MCHP_LPC_EMI1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x94)
-#define MCHP_LPC_EMI2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x98)
-#define MCHP_LPC_P80DBG0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x9C)
-#define MCHP_LPC_P80DBG1_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA0)
-#define MCHP_LPC_RTC_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA4)
-#define MCHP_LPC_ACPI_EC_BAR(x)	REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2))
-/* LPC BAR bits */
-#define MCHP_LPC_IO_BAR_ADDR_BITPOS	(16)
-#define MCHP_LPC_IO_BAR_EN		(1ul << 15)
-/* LPC Generic Memory BAR's, 64-bit registers */
-#define MCHP_LPC_SRAM0_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB0)
-#define MCHP_LPC_SRAM0_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xB4)
-#define MCHP_LPC_SRAM1_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB8)
-#define MCHP_LPC_SRAM1_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xBC)
-/*
- * LPC Logical Device Memory BAR's, 48-bit registers
- * Use 16-bit aligned access
- */
-#define MCHP_LPC_MAILBOX_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC0)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC2)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xC4)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC6)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC8)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xCA)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xCC)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xCE)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD0)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD2)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xD4)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD6)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD8)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xDA)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xDC)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xDE)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE0)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE2)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xE4)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE6)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE8)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xEA)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xEC)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xEE)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xF0)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xF2)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xF4)
-
-#define MCHP_LPC_BUS_MONITOR	REG32(MCHP_LPC_RT_BASE + 0x4)
-#define MCHP_LPC_HOST_ERROR	REG32(MCHP_LPC_RT_BASE + 0x8)
-#define MCHP_LPC_EC_SERIRQ	REG32(MCHP_LPC_RT_BASE + 0xC)
-#define MCHP_LPC_EC_CLK_CTRL	REG32(MCHP_LPC_RT_BASE + 0x10)
-#define MCHP_LPC_BAR_INHIBIT	REG32(MCHP_LPC_RT_BASE + 0x20)
-#define MCHP_LPC_BAR_INIT	REG32(MCHP_LPC_RT_BASE + 0x30)
-#define MCHP_LPC_SRAM0_BAR	REG32(MCHP_LPC_RT_BASE + 0xf8)
-#define MCHP_LPC_SRAM1_BAR	REG32(MCHP_LPC_RT_BASE + 0xfc)
-
-/* eSPI */
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-
-#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-
-/*
- * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
- */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	14
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- *
- * On MCHP, any DMA channel may serve any device. Since we have
- * 14 channels and 14 device request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_SPI0_TX,
-	MCHP_DMAC_SPI0_RX,
-	MCHP_DMAC_SPI1_TX,
-	MCHP_DMAC_SPI1_RX,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_SPI0_TX_REQ_ID		8
-#define MCHP_DMA_SPI0_RX_REQ_ID		9
-#define MCHP_DMA_SPI1_TX_REQ_ID		10
-#define MCHP_DMA_SPI1_RX_REQ_ID		11
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	12
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	13
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR 0x10000000
-#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec172x.h b/chip/mchp/registers-mec172x.h
deleted file mode 100644
index dc811ea3c7..0000000000
--- a/chip/mchp/registers-mec172x.h
+++ /dev/null
@@ -1,1503 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC172x family controllers
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/*
- * IRQ Numbers
- * NOTE: GIRQ22 aggregated output and its sources are not connected to
- * the NVIC.
- */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
-/* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
-/* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-#define MCHP_IRQ_DMA_14		38
-#define MCHP_IRQ_DMA_15		39
-/* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_BDP0		62
-/* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE		65
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AESH		68
-/* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-/* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_EEPROM		155
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
-/* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-#define MCHP_IRQ_ESPI_SAF_DONE	166
-#define MCHP_IRQ_ESPI_SAF_ERR	166
-#define MCHP_IRQ_ESPI_SAF_CACHE	169
-/* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
-#define MCHP_IRQ_CLK32K_MON	174
-/* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_KSC_INT	135
-#define MCHP_IRQ_GLUE		172
-/* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-/* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX 180
-
-/* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_CACHE_CTRL_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_SPIEP_BASE		0x40007000
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_ESPI_SAF_BASE	0x40008000
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_VCI_BASE		0x4000ae00
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_BCL_0_BASE		0x4000cd00
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_QMSPI0_BASE	0x40070000
-#define MCHP_ESPI_SAF_COMM_BASE 0x40071000
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-#define MCHP_OTP_BASE		0x40082000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_PORT92_BASE	0x400f2000
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_GLUE_BASE		0x400f3c00
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_RTC_BASE		0x400f5000
-#define MCHP_BDP0_BASE		0x400f8000
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
-
-#ifndef __ASSEMBLER__
-
-/*
- * Helper function for RAM address aliasing
- * NOTE: MEC17xx and MEC15xx AHB controllers do NOT require aliasing.
- * Cortex-M4 bit-banding does require aliasing of the
- * DATA SRAM region.
- */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-/* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
-/* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
-/* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
-/* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
-#define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
-
-/* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_96MHZ		1U
-#define MCHP_PCR_CLK_CTL_48MHZ		2U
-#define MCHP_PCR_CLK_CTL_24MHZ		4U
-#define MCHP_PCR_CLK_CTL_12MHZ		8U
-
-/* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX 5
-
-/* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
-
-/*
- * Encode register number and bit position
- * b[4:0] = bit number
- * b[10:8] = zero based register number
- */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
-
-/* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) | BIT(20) | BIT(21) |\
-	BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
-/* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
-/*
- * block not used by default
- * Do not sleep ECIA, PMC, CPU and ECS
- */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
-
-/* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_BDP0		MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 16)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
-
-/* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_BDP0		BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
-/* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
-
-/* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_CRYPTO		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_CRYPTO		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	BIT(26)
-/* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
-
-/* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(4, 22)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
-
-/* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_GPSPI1		BIT(22)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
-
-/* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL \
-	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
-
-/* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
-
-/* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
-#define MCHP_PWR_RST_STS_MASK \
-	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
-
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT		BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR		BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
-
-/* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	0
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
-
-/* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
-
-/*
- * PCR Peripheral Reset Lock register
- * MEC152x PCR Peripheral reset registers do not reset on
- * peripheral sleep. The peripheral is reset immediately.
- * Firmware must write an unlock value to this new lock
- * register, write to PCR reset enable register(s), and
- * write a lock value.
- */
-#define MCHP_PCR_RST_LOCK	REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL	0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL	0xa6382d4c
-
-/* PCR VBAT soft reset. Trigger a VBAT reset */
-#define MCHP_PCR_VBAT_SRST	REG32(MCHP_PCR_BASE + 0x88)
-#define MCHP_PCR_VBAT_SRST_EN	BIT(0)
-
-/* PCR 32KHz clock source select */
-#define MCHP_PCR_CK32_SS	REG32(MCHP_PCR_BASE + 0x8c)
-#define MCHP_PCR_CK32_SEL_MASK	GENMASK(1, 0)
-#define MCHP_PCR_CK32_SEL_SIL	0
-#define MCHP_PCR_CK32_SEL_XTAL	1
-#define MCHP_PCR_CK32_SEL_PIN	2
-#define MCHP_PCR_CK32_SEL_OFF	3
-
-/* PCR 32KHz period count (RO) */
-#define MCHP_PCR_CK32_PER_CNT		REG32(MCHP_PCR_BASE + 0xc0)
-#define MCHP_PCR_CD32_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz high pulse count (RO) */
-#define MCHP_PCR_CK32_HP_CNT		REG32(MCHP_PCR_BASE + 0xc4)
-#define MCHP_PCR_CK32_HP_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz minimum acceptable period count */
-#define MCHP_PCR_CK32_MIN_PER_CNT	REG32(MCHP_PCR_BASE + 0xc8)
-#define MCHP_PCR_CK32_MIN_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz maximum acceptable period count */
-#define MCHP_PCR_CK32_MAX_PER_CNT	REG32(MCHP_PCR_BASE + 0xcc)
-#define MCHP_PCR_CK32_MAX_PER_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz duty cycle variation count (RO) */
-#define MCHP_PCR_CK32_DC_VAR_CNT	REG32(MCHP_PCR_BASE + 0xd0)
-#define MCHP_PCR_CK32_DC_VAR_CNT_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz duty cycle variation acceptable maximum */
-#define MCHP_PCR_CK32_DC_VAR_MAX	REG32(MCHP_PCR_BASE + 0xd4)
-#define MCHP_PCR_CK32_DC_VAR_MAX_MSK	GENMASK(15, 0)
-
-/* PCR 32KHz valid count */
-#define MCHP_PCR_CK32_VAL_CNT		REG32(MCHP_PCR_BASE + 0xd8)
-#define MCHP_PCR_CK32_VAL_CNT_MSK	GENMASK(7, 0)
-
-/* PCR 32KHz valid count minimum */
-#define MCHP_PCR_CK32_MIN_VAL_CNT	REG32(MCHP_PCR_BASE + 0xdc)
-#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK	GENMASK(7, 0)
-
-/* PCR 32KHz control */
-#define MCHP_PCR_CK32_CTRL		REG32(MCHP_PCR_BASE + 0xe0)
-#define MCHP_PCR_CK32_CTRL_MSK		(GENMASK(2, 0) | BIT(4) | BIT(24))
-#define MCHP_PCR_CK32_CTRL_PER_EN	BIT(0)
-#define MCHP_PCR_CK32_CTRL_DC_EN	BIT(1)
-#define MCHP_PCR_CK32_CTRL_VAL_EN	BIT(2)
-#define MCHP_PCR_CK32_CTRL_SRC_SIL	BIT(3)
-#define MCHP_PCR_CK32_CTRL_CLR_CNT	BIT(24)
-
-/* PCR 32KHz interrupt status */
-#define MCHP_PCR_CK32_INTR_STS		REG8(MCHP_PCR_BASE + 0xe4)
-/* PCR 32KHz interrupt enable */
-#define MCHP_PCR_CK32_INTR_EN		REG8(MCHP_PCR_BASE + 0xe8)
-#define MCHP_PCR_CK32_INTR_PULSE_RDY	BIT(0)
-#define MCHP_PCR_CK32_INTR_PASS_PER	BIT(1)
-#define MCHP_PCR_CK32_INTR_PASS_DUTY	BIT(2)
-#define MCHP_PCR_CK32_INTR_FAIL		BIT(3)
-#define MCHP_PCR_CK32_INTR_STALL	BIT(4)
-#define MCHP_PCR_CK32_INTR_VALID	BIT(5)
-#define MCHP_PCR_CK32_INTR_UNWELL	BIT(6)
-
-/* EC Subsystem */
-#define MCHP_EC_AHB_ERR		REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO		REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN	REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL	REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN	REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN		REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT		REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_PECI_DISABLE	REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_VCI_FW_OVRD	REG32(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_BROM_STS	REG32(MCHP_EC_BASE + 0x54)
-#define MCHP_EC_VW_SRC_CFG	REG32(MCHP_EC_BASE + 0x90)
-#define MCHP_EC_CMP_CTRL	REG32(MCHP_EC_BASE + 0x94)
-#define MCHP_EC_CMP_SLP_CTRL	REG32(MCHP_EC_BASE + 0x98)
-
-/* AHB ERR Disable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
-
-/* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
-/* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
-/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
-/* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
-
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
-/* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
-
-/*
- * GPIO GIRQ's are not direct capable
- * GIRQ08 GPIO 0140 - 0176
- * GIRQ09 GPIO 0100 - 0136
- * GIRQ10 GPIO 040 - 076
- * GIRQ11 GPIO 000 - 036
- * GIRQ12 GPIO 0200 - 0236
- * GIRQ26 GPIO 0240 - 0276
- * Other GIRQ's not direct capable:
- * GIRQ22 wake peripheral clock only
- * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
- */
-#define MCHP_INT_AGGR_ONLY_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\
-		BIT(12) | BIT(22) | BIT(24) | BIT(25) | BIT(26))
-
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP (BIT(13) | BIT(14) | BIT(15) |\
-	BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23))
-
-/* GIRQ13 I2C controllers 0 - 4. Direct capable */
-#define MCHP_INT13_I2C(x) BIT(x)
-
-/* GIRQ14 DMA channels 0 - 15. Direct capable */
-#define MCHP_INT14_DMA(x) BIT(x)
-
-/* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_BDP0			BIT(22)
-
-/* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_DONE		BIT(0)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AESH_DONE		BIT(3)
-
-/* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(20)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(21)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(22)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(23)
-
-/* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SPIEP		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PSPI			BIT(13)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
-
-/* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
-#define MCHP_INT19_ESPI_SAF_CACHE	BIT(11)
-
-/* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_OTP			BIT(3)
-#define MCHP_INT20_ISPI			BIT(8)
-#define MCHP_INT20_CLK32K_MON		BIT(9)
-
-/* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDG			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-#define MCHP_INT21_GLUE			BIT(26)
-
-/* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SPIEP	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-#define MCHP_INT22_WAKE_ONLY_STAP	BIT(15)
-
-/* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT21_RTMR			BIT(10)
-#define MCHP_INT21_HTMR_0		BIT(16)
-#define MCHP_INT21_HTMR_1		BIT(17)
-
-/* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
-#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
-
-/* GIRQ25 sources Master-to-Slave v=[7:10], Source=[0:3] */
-#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
-
-/* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
-#define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/*
- * GPIO
- * MCHP each Port contains 32 GPIO's.
- * GPIO Control 1 registers are 32-bit registers starting at
- * MCHP_GPIO_BASE.
- * index = octal GPIO number from MCHP specification.
- * port/bank = index >> 5
- * id = index & 0x1F
- *
- * The port/bank, id pair may also be used to access GPIO's via
- * parallel I/O registers if GPIO control is configured for
- * parallel I/O.
- *
- * From ec/chip/mec1701/config_chip.h
- * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F)
- *
- * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2)
- *
- * Example: GPIO043, Control 1 register address = 0x4008108c
- * port/bank = 0x23 >> 5 = 1
- * id        = 0x23 & 0x1F = 0x03
- * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
- *
- * Example: GPIO235, Control 1 register address = 0x40081274
- * port/bank = 0x9d >> 5   = 4
- * id        = 0x9d & 0x1f = 0x1d
- * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
- *
- */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
-
-/* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
-/*
- * In MECxxxx documentation GPIO numbers are octal, each control
- * register is located on a 32-bit boundary.
- */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
-
-/*
- * GPIO control register bit fields
- */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		GENMASK(2, 1)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02U << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0U
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10U
-#define MCHP_GPIO_INTDET_DISABLED	0x40U
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0U
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0U
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0U
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0U
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0U
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0U
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0U
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x07U
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x07U << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	0
-#define MCHP_GPIO_CTRL_FUNC_1		(1U << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2U << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3U << 12)
-#define MCHP_GPIO_CTRL_FUNC_4		(4U << 12)
-#define MCHP_GPIO_CTRL_FUNC_5		(5U << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
-/* MEC172x implements input pad disable */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	BIT(15)
-
-/*
- * GPIO Parallel Input and Output registers.
- * gpio_bank in [0, 5]
- */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
-
-/* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
-
-/* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
-
-/* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
-
-/* Watchdog */
-/* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
-/* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
-/* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
-/* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
-
-/* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CSS			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-#define MCHP_VBAT_ROM_FEAT		REG32(MCHP_VBAT_BASE + 0x28)
-#define MCHP_VBAT_EMB_DEBOUNCE_EN	REG32(MCHP_VBAT_BASE + 0x34)
-/* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
-/*
- * Miscellaneous firmware control fields
- * scratch pad index cannot be more than 32 as
- * MEC152x has 64 bytes = 16 words of scratch RAM
- */
-#define MCHP_IMAGETYPE_IDX	31
-
-/* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
-
-/* Bit definitions for MCHP_VBAT_CSS */
-#define MCHP_VBAT_CSS_SIL32K_EN		BIT(0)
-#define MCHP_VBAT_CSS_XTAL_EN		BIT(8)
-#define MCHP_VBAT_CSS_XTAL_SINGLE	BIT(9)
-#define MCHP_VBAT_CSS_XTAL_HSC_DIS	BIT(10)
-#define MCHP_VBAT_CSS_XTAL_CNT_POS	11
-#define MCHP_VBAT_CSS_XTAL_CNT_MASK	(0x03U << 11)
-#define MCHP_VBAT_CSS_SRC_POS		16
-#define MCHP_VBAT_CSS_SRC_MASK		(0x03U << 16)
-#define MCHP_VBAT_CSS_SRC_SIL_OSC	0
-#define MCHP_VBAT_CSS_SRC_XTAL		(1U << 16)
-/* Switch from 32KHZ_IN input to silicon OSC when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPS		(2U << 16)
-/* Switch from 32KHZ_IN input to XTAL on VBAT when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPX		(3U << 16)
-/* Disable 32Khz silicon oscillator when VBAT goes off */
-#define MCHP_VBAT_CSS_NVB_SUPS		BIT(18)
-
-/* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
-
-/* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
-/* base of EMI registers only accessible by EC */
-#define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
-/* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
-
-/* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
-
-/* MEC172x includes one instance of the BIOS Debug Port
- * capable of capturing Host I/O port 0x80 and 0x90 writes.
- * EC Data Value register:
- * bits[7:0] oldest FIFO data from Host
- * bits[15:16] data attributes/status
- * Read with 16 or 32 access guarantees attributes/status bits
- * correspond to data in bits[7:0].
- */
-#define MCHP_BDP0_HDATA		REG32(MCHP_BDP0_BASE)
-#define MCHP_BDP0_DATTR		REG16(MCHP_BDP0_BASE + 0x100)
-#define MCHP_BDP0_CONFIG	REG32(MCHP_BDP0_BASE + 0x104)
-#define MCHP_BDP0_STATUS	REG8(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_INTR_EN	REG8(MCHP_BDP0_BASE + 0x109)
-#define MCHP_BDP0_STS_IEN	REG16(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_SNAPSHOT	REG32(MCHP_BDP0_BASE + 0x10C)
-#define MCHP_BDP0_CAPTURE	REG32(MCHP_BDP0_BASE + 0x110)
-#define MCHP_BDP0_ACTV		REG8(MCHP_BDP0_BASE + 0x330)
-#define MCHP_BDP0_ALIAS_HDATA	REG8(MCHP_BDP0_BASE + 0x400)
-#define MCHP_BDP0_ALIAS_ACTV	REG8(MCHP_BDP0_BASE + 0x730)
-#define MCHP_BDP0_ALIAS_BLN	REG8(MCHP_BDP0_BASE + 0x7F0)
-
-#define MCHP_BDP0_GIRQ		15
-#define MCHP_BDP0_GIRQ_BIT	BIT(22)
-
-/* BDP DATATR as 16-bit value bit definitions */
-#define MCHP_BDP_DATTR_POS		0
-#define MCHP_BDP_DATTR_DATA_MASK	0xff
-#define MCHP_BDP_DATTR_LANE_POS		8
-#define MCHP_BDP_DATTR_LANE_MASK	GENMASK(9, 8)
-#define MCHP_BDP_DATTR_LANE_0		0
-#define MCHP_BDP_DATTR_LANE_1		(1U << 8)
-#define MCHP_BDP_DATTR_LANE_2		(2U << 8)
-#define MCHP_BDP_DATTR_LANE_3		(3U << 8)
-#define MCHP_BDP_DATTR_LEN_POS		10
-#define MCHP_BDP_DATTR_LEN_MASK		GENMASK(11, 10)
-#define MCHP_BDP_DATTR_LEN_1		0
-#define MCHP_BDP_DATTR_LEN_2		(1U << 10)
-#define MCHP_BDP_DATTR_LEN_4		(2U << 10)
-#define MCHP_BDP_DATTR_LEN_INVAL	(3U << 10)
-#define MCHP_BDP_DATTR_NE		BIT(12)
-#define MCHP_BDP_DATTR_OVR		BIT(13)
-#define MCHP_BDP_DATTR_THRH		BIT(14)
-
-/* BDP Configuration */
-#define MCHP_BDP_CFG_FLUSH_FIFO		BIT(0)
-#define MCHP_BDP_CFG_SNAPSHOT_CLR	BIT(1)
-#define MCHP_BDP_CFG_FIFO_THRH_POS	8
-#define MCHP_BDP_CFG_FIFO_THRH_1	0
-#define MCHP_BDP_CFG_FIFO_THRH_4	(1U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_8	(2U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_16	(3U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_20	(4U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_24	(5U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_28	(6U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_30	(7U << 8)
-#define MCHP_BDP_CFG_SRST		BIT(31)
-
-/* BDP Status */
-#define MCHP_BDP_STATUS_MASK		GENMASK(2, 0)
-#define MCHP_BDP_STATUS_NOT_EMPTY	BIT(0)
-#define MCHP_BDP_STATUS_OVERRUN		BIT(1)
-#define MCHP_BDP_STATUS_THRH		BIT(2)
-
-/* BDP Interrupt enable */
-#define MCHP_BDP_IEN_THRH		BIT(0)
-
-/* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
-
-/* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
-
-/* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
-
-/* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
-
-/* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
-
-/* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
-
-/* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL_MAX	5
-
-#define MCHP_I2C_SEP0		0x400
-
-/*
- * MEC172x SZ(144-pin) package implements 15 ports. No Port 11.
- * LJ(176-pin) package implements 16 ports.
- * Any port can be mapped to any I2C controller.
- * I2C port values must be zero based consecutive whole numbers due to
- * port number used as an index for I2C the mutex list, etc.
- * Refer to chip i2c_port_to_controller function for mapping
- * of port to controller.
- * Locking must occur by-controller (not by-port).
- */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
-#define MCHP_I2C_PORT_MASK GENMASK(15, 0)
-#else
-#define MCHP_I2C_PORT_MASK (GENMASK(15, 0) & ~BIT(11))
-#endif
-enum MCHP_i2c_port {
-	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,
-	MCHP_I2C_PORT2,
-	MCHP_I2C_PORT3,
-	MCHP_I2C_PORT4,
-	MCHP_I2C_PORT5,
-	MCHP_I2C_PORT6,
-	MCHP_I2C_PORT7,
-	MCHP_I2C_PORT8,
-	MCHP_I2C_PORT9,
-	MCHP_I2C_PORT10,
-	MCHP_I2C_PORT11,
-	MCHP_I2C_PORT12,
-	MCHP_I2C_PORT13,
-	MCHP_I2C_PORT14,
-	MCHP_I2C_PORT15,
-	MCHP_I2C_PORT_COUNT,
-};
-
-/* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
-
-/* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
-/* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
-
-/* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
-
-/* ADC */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
-#define MCHP_ADC_CHAN_MASK GENMASK(15, 0)
-#else
-#define MCHP_ADC_CHAN_MASK GENMASK(7, 0)
-#endif
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
-#define MCHP_ADC_CONFIG			REG32(MCHP_ADC_BASE + 0x7c)
-#define MCHP_ADC_CONFIG_DFLT		0x0101U
-#define MCHP_ADC_CFG_CLK_LO_TM_MSK	GENMASK(7, 0)
-#define MCHP_ADC_CFG_CLK_HI_TM_MSK	GENMASK(15, 8)
-#define MCHP_ADC_VREF_CSEL		REG32(MCHP_ADC_BASE + 0x80)
-#define MCHP_ADC_VREF_CSEL_MSK(ch)	(0x03U << ((ch) * 2U))
-#define MCHP_ADC_VREF_CSEL_GPIO(ch)	BIT((ch) * 2U)
-#define MCHP_ADC_VREF_CTRL		REG32(MCHP_ADC_BASE + 0x84)
-#define MCHP_ADC_VREF_CTRL_DFLT		0U
-#define MCHP_ADC_VCTRL_CHRG_DLY_MSK	GENMASK(15, 0)
-#define MCHP_ADC_VCTRL_SW_DLY_MSK	GENMASK(28, 16)
-#define MCHP_ADC_VCTRL_DRV_UNUSED_LO	BIT(29)
-#define MCHP_ADC_VCTRL_SEL_STS_RO_POS	30
-#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK	GENMASK(31, 30)
-#define MCHP_ADC_SAR_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x88)
-#define MCHP_ADC_SAR_ADC_CTRL_DFLT	((0x202U << 7) | (0x03U << 1))
-#define MCHP_ADC_SAC_DIFF_INPUT		BIT(0)
-#define MCHP_ADC_SAC_RES_POS		1
-#define MCHP_ADC_SAC_RES_MSK		GENMASK(2, 1)
-#define MCHP_ADC_SAC_RES_10BIT		(2U << 1)
-#define MCHP_ADC_SAC_RES_12BIT		(3U << 1)
-#define MCHP_ADC_SAC_RJ_10BIT		BIT(3)
-#define MCHP_ADC_SAC_WU_DLY_POS		7
-#define MCHP_ADC_SAC_WU_DLY_MSK		GENMASK(16, 7)
-#define MCHP_ADC_SAC_WU_DLY_DLFT	(0x202U << 7)
-
-/* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
-/* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
-
-/* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
-/* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
-/* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
-
-/*
- * Quad Master SPI (QMSPI)
- * MEC172x implements 16 descriptors, support for two chip selects,
- * chip select timing and a local DMA unit with 3 RX channels and
- * 3 TX channels. It retains support of the legacy DMA block.
- */
-#define MCHP_QMSPI_MAX_DESCR	16
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC 91
-/* SAF DMA mode when QMSPI when eSPI SAF is enabled */
-#define MCHP_QMSPI_M_SAF_EN	BIT(2)
-/* Local DMA enables in Mode register */
-#define MCHP_QMSPI_M_LDRX_EN	BIT(3)
-#define MCHP_QMSPI_M_LDTX_EN	BIT(4)
-/* Chip select implemented in bit[13:12] of the Mode register. */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	GENMASK(13, 12)
-#define MCHP_QMSPI_M_CS0	0U
-#define MCHP_QMSPI_M_CS1	BIT(12)
-/* QMSPI alternate clock divider when CS1 is active. */
-#define MCHP_QMSPI0_ALTM	REG32(MCHP_QMSPI0_BASE + 0xc0)
-#define MCHP_QMSPI0_ALTM_EN	BIT(0)
-/* QMSPI taps select */
-#define MCHP_QMSPI0_TAPS		REG32(MCHP_QMSPI0_BASE + 0xd0)
-/* QMSPI Taps adjust */
-#define MCHP_QMSPI0_TAPS_ADJ		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_SCK_POS	0
-#define MCHP_QMSPI0_TAPS_SCK_MSK	GENMASK(7, 0)
-#define MCHP_QMSPI0_TAPS_CTL_POS	8
-#define MCHP_QMSPI0_TAPS_CTL_MSK	GENMASK(15, 8)
-/* QMSPI Taps control */
-#define MCHP_QMSPI0_TAPS_CTRL		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS	0
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK	GENMASK(1, 0)
-#define MCHP_QMSPI0_TAPS_CTRL_UPDATE	BIT(2)
-#define MCHP_QMSPI0_TAPS_CTRL_GO	BIT(8)
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS	16
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK	GENMASK(18, 16)
-/* QMSPI LDMA descriptor enables */
-#define MCHP_QMSPI0_LDRX_DEN	REG32(MCHP_QMSPI0_BASE + 0x100)
-#define MCHP_QMSPI0_LDTX_DEN	REG32(MCHP_QMSPI0_BASE + 0x104)
-/*
- * QMSPI LDMA channel registers.
- * Each channel implement 3 32-bit registers:
- * control, memory base address, and transfer length.
- */
-#define MCHP_QMSPI0_LDRX_CHANS 3U
-#define MCHP_QMSPI0_LDTX_CHANS 3U
-#define MCHP_QMSPI0_LDRX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x110 + ((n)*16U))
-#define MCHP_QMSPI0_LDRX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x114 + ((n)*16U))
-#define MCHP_QMSPI0_LDRX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x118 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_CTRL(n) REG32(MCHP_QMSPI0_BASE + 0x140 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x144 + ((n)*16U))
-#define MCHP_QMSPI0_LDTX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x148 + ((n)*16U))
-/* LDMA RX or TX channel control register */
-#define MCHP_QMSPI_LDC_MSK		GENMASK(6, 0)
-#define MCHP_QMSPI_LDC_EN		BIT(0)
-#define MCHP_QMSPI_LDC_RSTART_EN	BIT(1)
-#define MCHP_QMSPI_LDC_RSTART_MA_EN	BIT(2)
-#define MCHP_QMSPI_LDC_LEN_EN		BIT(3)
-#define MCHP_QMSPI_LDC_ACC_SZ_POS	4
-#define MCHP_QMSPI_LDC_ACC_SZ_MSK	GENMASK(5, 4)
-#define MCHP_QMSPI_LDC_ACC_1BYTE	0
-#define MCHP_QMSPI_LDC_ACC_2BYTES	(1U << 4)
-#define MCHP_QMSPI_LDC_ACC_4BYTES	(2U << 4)
-#define MCHP_QMSPI_LDC_INCR_ADDR	BIT(6)
-
-/* eSPI */
-/* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_BDP0		0x10
-#define MCHP_ESPI_IO_BAR_BDP0_ALT	0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_TB32		0x14
-#define MCHP_ESPI_IO_BAR_GLUE		0x16
-
-/* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
-#define MCHP_ESPI_MBAR_ID_TB32		9
-
-/* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-
-#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
-
-/*
- * eSPI RESET, channel enables and operations except Master-to-Slave
- * WWires are all on GIRQ19
- */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
-#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT	BIT(11)
-
-/* eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
-/*
- * Four source bits, SRC[0:3] per Master-to-Slave register
- * v = MSVW [0:10]
- * n = VWire SRC bit = [0:3]
- */
-#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
-
-#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
-/* DMA */
-#define MCHP_DMA_MAX_CHAN	16
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
-
-/*
- * Available DMA channels.
- *
- * On MCHP, any DMA channel may serve any device. Since we have
- * 14 channels and 14 device request signals, we make each channel
- * dedicated to the device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MCHP_DMAC_I2C0_SLAVE = 0,
-	MCHP_DMAC_I2C0_MASTER,
-	MCHP_DMAC_I2C1_SLAVE,
-	MCHP_DMAC_I2C1_MASTER,
-	MCHP_DMAC_I2C2_SLAVE,
-	MCHP_DMAC_I2C2_MASTER,
-	MCHP_DMAC_I2C3_SLAVE,
-	MCHP_DMAC_I2C3_MASTER,
-	MCHP_DMAC_I2C4_SLAVE,
-	MCHP_DMAC_I2C5_MASTER,
-	MCHP_DMAC_QMSPI0_TX,
-	MCHP_DMAC_QMSPI0_RX,
-	MCHP_DMAC_SPI0_TX,
-	MCHP_DMAC_SPI0_RX,
-	MCHP_DMAC_SPI1_TX,
-	MCHP_DMAC_SPI1_RX,
-	/* Channel count */
-	MCHP_DMAC_COUNT,
-};
-
-/*
- * Peripheral device DMA Device ID's for bits [15:9]
- * in DMA channel control register.
- */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
-#define MCHP_DMA_SPI0_TX_REQ_ID		12
-#define MCHP_DMA_SPI0_RX_REQ_ID		13
-#define MCHP_DMA_SPI1_TX_REQ_ID		14
-#define MCHP_DMA_SPI1_RX_REQ_ID		15
-
-/*
- * Hardware delay register.
- * Write of 0 <= n <= 31 will stall the Cortex-M4
- * for n+1 microseconds. Interrupts will not be
- * serviced during the delay period. Reads have
- * no effect.
- */
-#define MCHP_USEC_DELAY_REG_ADDR 0x08000000
-#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
-
-#endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h
deleted file mode 100644
index 65936caa2d..0000000000
--- a/chip/mchp/registers.h
+++ /dev/null
@@ -1,895 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for Microchip MEC family processors
- */
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-
-#if defined(CHIP_FAMILY_MEC152X)
-#include "registers-mec152x.h"
-#elif defined(CHIP_FAMILY_MEC170X)
-#include "registers-mec1701.h"
-#elif defined(CHIP_FAMILY_MEC172X)
-#include "registers-mec172x.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-/* Common registers */
-/* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_SOURCE(x)		REG32(MCHP_INTx_BASE(x) + 0x0)
-#define MCHP_INT_ENABLE(x)		REG32(MCHP_INTx_BASE(x) + 0x4)
-#define MCHP_INT_RESULT(x)		REG32(MCHP_INTx_BASE(x) + 0x8)
-#define MCHP_INT_DISABLE(x)		REG32(MCHP_INTx_BASE(x) + 0xc)
-#define MCHP_INT_BLK_EN			REG32(MCHP_INT_BASE + 0x200)
-#define MCHP_INT_BLK_DIS		REG32(MCHP_INT_BASE + 0x204)
-#define MCHP_INT_BLK_IRQ		REG32(MCHP_INT_BASE + 0x208)
-
-/* EC Chip Configuration */
-#define MCHP_CHIP_LEGACY_DEV_ID		REG8(MCHP_CHIP_BASE + 0x20)
-#define MCHP_CHIP_LEGACY_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
-
-/* Power/Clocks/Resets */
-#define MCHP_PCR_SYS_SLP_CTL		REG32(MCHP_PCR_BASE + 0x00)
-#define MCHP_PCR_PROC_CLK_CTL		REG32(MCHP_PCR_BASE + 0x04)
-#define MCHP_PCR_SLOW_CLK_CTL		REG32(MCHP_PCR_BASE + 0x08)
-#define MCHP_PCR_CHIP_OSC_ID		REG32(MCHP_PCR_BASE + 0x0C)
-#define MCHP_PCR_PWR_RST_STS		REG32(MCHP_PCR_BASE + 0x10)
-#define MCHP_PCR_PWR_RST_CTL		REG32(MCHP_PCR_BASE + 0x14)
-#define MCHP_PCR_SYS_RST		REG32(MCHP_PCR_BASE + 0x18)
-#define MCHP_PCR_SLP_EN0		REG32(MCHP_PCR_BASE + 0x30)
-#define MCHP_PCR_SLP_EN1		REG32(MCHP_PCR_BASE + 0x34)
-#define MCHP_PCR_SLP_EN2		REG32(MCHP_PCR_BASE + 0x38)
-#define MCHP_PCR_SLP_EN3		REG32(MCHP_PCR_BASE + 0x3C)
-#define MCHP_PCR_SLP_EN4		REG32(MCHP_PCR_BASE + 0x40)
-#define MCHP_PCR_CLK_REQ0		REG32(MCHP_PCR_BASE + 0x50)
-#define MCHP_PCR_CLK_REQ1		REG32(MCHP_PCR_BASE + 0x54)
-#define MCHP_PCR_CLK_REQ2		REG32(MCHP_PCR_BASE + 0x58)
-#define MCHP_PCR_CLK_REQ3		REG32(MCHP_PCR_BASE + 0x5C)
-#define MCHP_PCR_CLK_REQ4		REG32(MCHP_PCR_BASE + 0x60)
-#define MCHP_PCR_RST_EN0		REG32(MCHP_PCR_BASE + 0x70)
-#define MCHP_PCR_RST_EN1		REG32(MCHP_PCR_BASE + 0x74)
-#define MCHP_PCR_RST_EN2		REG32(MCHP_PCR_BASE + 0x78)
-#define MCHP_PCR_RST_EN3		REG32(MCHP_PCR_BASE + 0x7C)
-#define MCHP_PCR_RST_EN4		REG32(MCHP_PCR_BASE + 0x80)
-#define MCHP_PCR_SLP_EN(x)		REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2))
-#define MCHP_PCR_CLK_REQ(x)		REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2))
-#define MCHP_PCR_RST_EN(x)		REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2))
-
-/* Bit definitions for MCHP_PCR_SYS_SLP_CTL */
-#define MCHP_PCR_SYS_SLP_LIGHT		(0ul << 0)
-#define MCHP_PCR_SYS_SLP_HEAVY		(1ul << 0)
-#define MCHP_PCR_SYS_SLP_ALL		(1ul << 3)
-/*
- * Set/clear PCR sleep enable bit for single device
- * d bits[10:8] = register 0 - 4
- * d bits[4:0] = register bit position
- */
-#define MCHP_PCR_SLP_EN_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d) & 0x1f)))
-#define MCHP_PCR_SLP_DIS_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d) & 0x1f)))
-/*
- * Set/clear bit pattern specified by mask in a single PCR sleep enable
- * register.
- * id = zero based ID of sleep enable register (0-4)
- * m = bit mask of bits to change
- */
-#define MCHP_PCR_SLP_EN_DEV_MASK(id, m)		(MCHP_PCR_SLP_EN((id)) |= (m))
-#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m)	(MCHP_PCR_SLP_EN((id)) &= ~(m))
-/* Slow Clock Control Mask */
-#define MCHP_PCR_SLOW_CLK_CTL_MASK		0x03FFul
-
-/* TFDP */
-#define MCHP_TFDP_DATA		REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL		REG8(MCHP_TFDP_BASE + 0x04)
-
-/* UART */
-#define MCHP_UART_ACT(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
-#define MCHP_UART_CFG(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
-/* DLAB=0 */
-#define MCHP_UART_RB(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_TB(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_IER(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-/* DLAB=1 */
-#define MCHP_UART_PBRG0(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_PBRG1(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-#define MCHP_UART_FCR(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_IIR(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_LCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
-#define MCHP_UART_MCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
-#define MCHP_UART_LSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
-#define MCHP_UART_MSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
-#define MCHP_UART_SCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
-/* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
-
-/* Timer */
-#define MCHP_TMR16_CNT(x)	REG32(MCHP_TMR16_BASE(x) + 0x0)
-#define MCHP_TMR16_PRE(x)	REG32(MCHP_TMR16_BASE(x) + 0x4)
-#define MCHP_TMR16_STS(x)	REG32(MCHP_TMR16_BASE(x) + 0x8)
-#define MCHP_TMR16_IEN(x)	REG32(MCHP_TMR16_BASE(x) + 0xc)
-#define MCHP_TMR16_CTL(x)	REG32(MCHP_TMR16_BASE(x) + 0x10)
-#define MCHP_TMR32_CNT(x)	REG32(MCHP_TMR32_BASE(x) + 0x0)
-#define MCHP_TMR32_PRE(x)	REG32(MCHP_TMR32_BASE(x) + 0x4)
-#define MCHP_TMR32_STS(x)	REG32(MCHP_TMR32_BASE(x) + 0x8)
-#define MCHP_TMR32_IEN(x)	REG32(MCHP_TMR32_BASE(x) + 0xc)
-#define MCHP_TMR32_CTL(x)	REG32(MCHP_TMR32_BASE(x) + 0x10)
-
-/* RTimer */
-#define MCHP_RTMR_COUNTER	REG32(MCHP_RTMR_BASE + 0x00)
-#define MCHP_RTMR_PRELOAD	REG32(MCHP_RTMR_BASE + 0x04)
-#define MCHP_RTMR_CONTROL	REG8(MCHP_RTMR_BASE + 0x08)
-#define MCHP_RTMR_SOFT_INTR	REG8(MCHP_RTMR_BASE + 0x0c)
-
-/* Watch dog timer */
-#define MCHP_WDG_LOAD			REG16(MCHP_WDG_BASE + 0x0)
-#define MCHP_WDG_CTL			REG16(MCHP_WDG_BASE + 0x4)
-#define MCHP_WDG_KICK			REG8(MCHP_WDG_BASE + 0x8)
-#define MCHP_WDG_CNT			REG16(MCHP_WDG_BASE + 0xc)
-#define MCHP_WDT_CTL_ENABLE		BIT(0)
-#define MCHP_WDT_CTL_HTMR_STALL_EN	BIT(2)
-#define MCHP_WDT_CTL_WKTMR_STALL_EN	BIT(3)
-#define MCHP_WDT_CTL_JTAG_STALL_EN	BIT(4)
-
-/* Blinking-Breathing LED */
-#define MCHP_BBLED_CONFIG(x)		REG32(MCHP_BBLED_BASE(x) + 0x00)
-#define MCHP_BBLED_LIMITS(x)		REG32(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MIN(x)		REG8(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MAX(x)		REG8(MCHP_BBLED_BASE(x) + 0x06)
-#define MCHP_BBLED_DELAY(x)		REG32(MCHP_BBLED_BASE(x) + 0x08)
-#define MCHP_BBLED_UPDATE_STEP(x)	REG32(MCHP_BBLED_BASE(x) + 0x0C)
-#define MCHP_BBLED_UPDATE_INTV(x)	REG32(MCHP_BBLED_BASE(x) + 0x10)
-#define MCHP_BBLED_OUTPUT_DLY(x)	REG8(MCHP_BBLED_BASE(x) + 0x14)
-/* BBLED Configuration Register */
-#define MCHP_BBLED_ASYMMETRIC		BIT(16)
-#define MCHP_BBLED_WDT_RELOAD_BITPOS	8
-#define MCHP_BBLED_WDT_RELOAD_MASK0	0xFFul
-#define MCHP_BBLED_WDT_RELOAD_MASK	(0xFFul << 8)
-#define MCHP_BBLED_RESET		BIT(7)
-#define MCHP_BBLED_EN_UPDATE		BIT(6)
-#define MCHP_BBLED_PWM_SIZE_BITPOS	4
-#define MCHP_BBLED_PWM_SIZE_MASK0	0x03ul
-#define MCHP_BBLED_PWM_SIZE_MASK	(0x03ul << 4)
-#define MCHP_BBLED_PWM_SIZE_6BIT	(0x02ul << 4)
-#define MCHP_BBLED_PWM_SIZE_7BIT	(0x01ul << 4)
-#define MCHP_BBLED_PWM_SIZE_8BIT	(0x00ul << 4)
-#define MCHP_BBLED_SYNC			BIT(3)
-#define MCHP_BBLED_CLK_48M		BIT(2)
-#define MCHP_BBLED_CLK_32K		0
-#define MCHP_BBLED_CTRL_MASK		0x03ul
-#define MCHP_BBLED_CTRL_ALWAYS_ON	0x03ul
-#define MCHP_BBLED_CTRL_BLINK		0x02ul
-#define MCHP_BBLED_CTRL_BREATHE		0x01ul
-#define MCHP_BBLED_CTRL_OFF		0x00ul
-/* BBLED Delay Register */
-#define MCHP_BBLED_DLY_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_LO_BITPOS	0
-#define MCHP_BBLED_DLY_LO_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_HI_BITPOS	12
-#define MCHP_BBLED_DLY_HI_MASK		(0x0FFFul << 12)
-/*
- * BBLED Update Step Register
- * 8 update fields numbered 0 - 7
- */
-#define MCHP_BBLED_UPD_STEP_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_STEP_MASK(u)	(0x0Ful << (((u) & 0x07) + 4))
-/*
- * BBLED Update Interval Register
- * 8 interval fields numbered 0 - 7
- */
-#define MCHP_BBLED_UPD_INTV_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_INTV_MASK(i)	(0x0Ful << (((i) & 0x07) + 4))
-
-/* EMI */
-#define MCHP_EMI_H2E_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x0)
-#define MCHP_EMI_E2H_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x1)
-#define MCHP_EMI_MBA0(n)		REG32(MCHP_EMI_BASE(n) + 0x4)
-#define MCHP_EMI_MRL0(n)		REG16(MCHP_EMI_BASE(n) + 0x8)
-#define MCHP_EMI_MWL0(n)		REG16(MCHP_EMI_BASE(n) + 0xa)
-#define MCHP_EMI_MBA1(n)		REG32(MCHP_EMI_BASE(n) + 0xc)
-#define MCHP_EMI_MRL1(n)		REG16(MCHP_EMI_BASE(n) + 0x10)
-#define MCHP_EMI_MWL1(n)		REG16(MCHP_EMI_BASE(n) + 0x12)
-#define MCHP_EMI_ISR(n)			REG16(MCHP_EMI_BASE(n) + 0x14)
-#define MCHP_EMI_HCE(n)			REG16(MCHP_EMI_BASE(n) + 0x16)
-#define MCHP_EMI_ISR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x8)
-#define MCHP_EMI_ISR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x9)
-#define MCHP_EMI_IMR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xa)
-#define MCHP_EMI_IMR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xb)
-
-/* Mailbox */
-#define MCHP_MBX_INDEX			REG8(MCHP_MBX_RT_BASE + 0x0)
-#define MCHP_MBX_DATA			REG8(MCHP_MBX_RT_BASE + 0x1)
-#define MCHP_MBX_H2E_MBX		REG8(MCHP_MBX_BASE + 0x0)
-#define MCHP_MBX_E2H_MBX		REG8(MCHP_MBX_BASE + 0x4)
-#define MCHP_MBX_ISR			REG8(MCHP_MBX_BASE + 0x8)
-#define MCHP_MBX_IMR			REG8(MCHP_MBX_BASE + 0xc)
-#define MCHP_MBX_REG(x)			REG8(MCHP_MBX_BASE + 0x10 + (x))
-
-/* PWM */
-#define MCHP_PWM_ON(x)			REG32(MCHP_PWM_BASE(x) + 0x00)
-#define MCHP_PWM_OFF(x)			REG32(MCHP_PWM_BASE(x) + 0x04)
-#define MCHP_PWM_CFG(x)			REG32(MCHP_PWM_BASE(x) + 0x08)
-
-/* TACH */
-#define MCHP_TACH_CTRL(x)		REG32(MCHP_TACH_BASE(x))
-#define MCHP_TACH_CTRL_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x00)
-#define MCHP_TACH_CTRL_CNT(x)		REG16(MCHP_TACH_BASE(x) + 0x02)
-#define MCHP_TACH_STATUS(x)		REG8(MCHP_TACH_BASE(x) + 0x04)
-#define MCHP_TACH_LIMIT_HI(x)		REG16(MCHP_TACH_BASE(x) + 0x08)
-#define MCHP_TACH_LIMIT_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x0C)
-
-/* ACPI */
-#define MCHP_ACPI_EC_EC2OS(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MCHP_ACPI_EC_STATUS(x)		REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
-#define MCHP_ACPI_EC_BYTE_CTL(x)	REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
-#define MCHP_ACPI_EC_OS2EC(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y))
-#define MCHP_ACPI_PM1_STS1		REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
-#define MCHP_ACPI_PM1_STS2		REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
-#define MCHP_ACPI_PM1_EN1		REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
-#define MCHP_ACPI_PM1_EN2		REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
-#define MCHP_ACPI_PM1_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
-#define MCHP_ACPI_PM1_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
-#define MCHP_ACPI_PM2_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
-#define MCHP_ACPI_PM2_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
-#define MCHP_ACPI_PM_STS		REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
-
-/* 8042 */
-#define MCHP_8042_OBF_CLR		REG8(MCHP_8042_BASE + 0x0)
-#define MCHP_8042_H2E			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_E2H			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_STS			REG8(MCHP_8042_BASE + 0x104)
-#define MCHP_8042_KB_CTRL		REG8(MCHP_8042_BASE + 0x108)
-#define MCHP_8042_PCOBF			REG8(MCHP_8042_BASE + 0x114)
-#define MCHP_8042_ACT			REG8(MCHP_8042_BASE + 0x330)
-
-/* PROCHOT */
-#define MCHP_PCHOT_CUM_CNT		REG32(MCHP_PROCHOT_BASE + 0x00)
-#define MCHP_PCHOT_DTY_CYC_CNT		REG32(MCHP_PROCHOT_BASE + 0x04)
-#define MCHP_PCHOT_DTY_PRD_CNT		REG32(MCHP_PROCHOT_BASE + 0x08)
-#define MCHP_PCHOT_STS_CTRL		REG32(MCHP_PROCHOT_BASE + 0x0C)
-#define MCHP_PCHOT_ASERT_CNT		REG32(MCHP_PROCHOT_BASE + 0x10)
-#define MCHP_PCHOT_ASERT_CNT_LMT	REG32(MCHP_PROCHOT_BASE + 0x14)
-#define MCHP_PCHOT_TEST			REG32(MCHP_PROCHOT_BASE + 0x18)
-
-/* I2C registers access given controller base address */
-#define MCHP_I2C_CTRL(addr)		REG8(addr)
-#define MCHP_I2C_STATUS(addr)		REG8(addr)
-#define MCHP_I2C_OWN_ADDR(addr)		REG16(addr + 0x4)
-#define MCHP_I2C_DATA(addr)		REG8(addr + 0x8)
-#define MCHP_I2C_MASTER_CMD(addr)	REG32(addr + 0xc)
-#define MCHP_I2C_SLAVE_CMD(addr)	REG32(addr + 0x10)
-#define MCHP_I2C_PEC(addr)		REG8(addr + 0x14)
-#define MCHP_I2C_DATA_TIM_2(addr)	REG8(addr + 0x18)
-#define MCHP_I2C_COMPLETE(addr)		REG32(addr + 0x20)
-#define MCHP_I2C_IDLE_SCALE(addr)	REG32(addr + 0x24)
-#define MCHP_I2C_CONFIG(addr)		REG32(addr + 0x28)
-#define MCHP_I2C_BUS_CLK(addr)		REG16(addr + 0x2c)
-#define MCHP_I2C_BLK_ID(addr)		REG8(addr + 0x30)
-#define MCHP_I2C_REV(addr)		REG8(addr + 0x34)
-#define MCHP_I2C_BB_CTRL(addr)		REG8(addr + 0x38)
-#define MCHP_I2C_TST_DATA_TIM(addr)	REG32(addr + 0x3c)
-#define MCHP_I2C_DATA_TIM(addr)		REG32(addr + 0x40)
-#define MCHP_I2C_TOUT_SCALE(addr)	REG32(addr + 0x44)
-#define MCHP_I2C_SLAVE_TX_BUF(addr)	REG8(addr + 0x48)
-#define MCHP_I2C_SLAVE_RX_BUF(addr)	REG8(addr + 0x4c)
-#define MCHP_I2C_MASTER_TX_BUF(addr)	REG8(addr + 0x50)
-#define MCHP_I2C_MASTER_RX_BUF(addr)	REG8(addr + 0x54)
-#define MCHP_I2C_TEST_1(addr)		REG32(addr + 0x58)
-#define MCHP_I2C_TEST_2(addr)		REG32(addr + 0x5c)
-#define MCHP_I2C_WAKE_STS(addr)		REG8(addr + 0x60)
-#define MCHP_I2C_WAKE_EN(addr)		REG8(addr + 0x64)
-#define MCHP_I2C_TEST_3(addr)		REG32(addr + 0x68)
-
-/* Keyboard scan matrix */
-#define MCHP_KS_KSO_SEL			REG32(MCHP_KEYSCAN_BASE + 0x4)
-#define MCHP_KS_KSI_INPUT		REG32(MCHP_KEYSCAN_BASE + 0x8)
-#define MCHP_KS_KSI_STATUS		REG32(MCHP_KEYSCAN_BASE + 0xc)
-#define MCHP_KS_KSI_INT_EN		REG32(MCHP_KEYSCAN_BASE + 0x10)
-#define MCHP_KS_EXT_CTRL		REG32(MCHP_KEYSCAN_BASE + 0x14)
-
-/* ADC */
-#define MCHP_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x0)
-#define MCHP_ADC_DELAY		REG32(MCHP_ADC_BASE + 0x4)
-#define MCHP_ADC_STS		REG32(MCHP_ADC_BASE + 0x8)
-#define MCHP_ADC_SINGLE		REG32(MCHP_ADC_BASE + 0xc)
-#define MCHP_ADC_REPEAT		REG32(MCHP_ADC_BASE + 0x10)
-#define MCHP_ADC_READ(x)	REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4))
-
-/* Hibernation timer */
-#define MCHP_HTIMER_PRELOAD(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x0)
-#define MCHP_HTIMER_CONTROL(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x4)
-#define MCHP_HTIMER_COUNT(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x8)
-
-/* Week timer and BGPO control */
-#define MCHP_WKTIMER_CTRL		REG32(MCHP_WKTIMER_BASE + 0)
-#define MCHP_WKTIMER_ALARM_CNT		REG32(MCHP_WKTIMER_BASE + 0x04)
-#define MCHP_WKTIMER_COMPARE		REG32(MCHP_WKTIMER_BASE + 0x08)
-#define MCHP_WKTIMER_CLK_DIV		REG32(MCHP_WKTIMER_BASE + 0x0c)
-#define MCHP_WKTIMER_SUBSEC_ISEL	REG32(MCHP_WKTIMER_BASE + 0x10)
-#define MCHP_WKTIMER_SUBWK_CTRL		REG32(MCHP_WKTIMER_BASE + 0x14)
-#define MCHP_WKTIMER_SUBWK_ALARM	REG32(MCHP_WKTIMER_BASE + 0x18)
-#define MCHP_WKTIMER_BGPO_DATA		REG32(MCHP_WKTIMER_BASE + 0x1c)
-#define MCHP_WKTIMER_BGPO_POWER		REG32(MCHP_WKTIMER_BASE + 0x20)
-#define MCHP_WKTIMER_BGPO_RESET		REG32(MCHP_WKTIMER_BASE + 0x24)
-
-/* Quad Master SPI (QMSPI) */
-#define MCHP_QMSPI0_MODE		REG32(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_ACT_SRST	REG8(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_SPI_MODE	REG8(MCHP_QMSPI0_BASE + 0x01)
-#define MCHP_QMSPI0_MODE_FDIV		REG8(MCHP_QMSPI0_BASE + 0x02)
-#define MCHP_QMSPI0_CTRL		REG32(MCHP_QMSPI0_BASE + 0x04)
-#define MCHP_QMSPI0_EXE			REG8(MCHP_QMSPI0_BASE + 0x08)
-#define MCHP_QMSPI0_IFCTRL		REG8(MCHP_QMSPI0_BASE + 0x0C)
-#define MCHP_QMSPI0_STS			REG32(MCHP_QMSPI0_BASE + 0x10)
-#define MCHP_QMSPI0_BUFCNT_STS		REG32(MCHP_QMSPI0_BASE + 0x14)
-#define MCHP_QMSPI0_IEN			REG32(MCHP_QMSPI0_BASE + 0x18)
-#define MCHP_QMSPI0_BUFCNT_TRIG		REG32(MCHP_QMSPI0_BASE + 0x1C)
-#define MCHP_QMSPI0_TX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_RX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_DESCR(x)		\
-	REG32(MCHP_QMSPI0_BASE + 0x30 + ((x) * 4))
-/* Bits in MCHP_QMSPI0_MODE */
-#define MCHP_QMSPI_M_ACTIVATE		BIT(0)
-#define MCHP_QMSPI_M_SOFT_RESET		BIT(1)
-#define MCHP_QMSPI_M_SPI_MODE_MASK	(0x7ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0		(0x0ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3		(0x3ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0_48M	(0x4ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3_48M	(0x7ul << 8)
-/*
- * clock divider is 8-bit field in bits[23:16]
- * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256
- */
-#define MCHP_QMSPI_M_CLKDIV_BITPOS	16
-#define MCHP_QMSPI_M_CLKDIV_48M		(1ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_24M		(2ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_16M		(3ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_12M		(4ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_8M		(6ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_6M		(8ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_1M		(48ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_188K	(0x100ul << 16)
-/* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */
-#define MCHP_QMSPI_C_1X			(0ul << 0) /* Full Duplex */
-#define MCHP_QMSPI_C_2X			(1ul << 0) /* Dual IO */
-#define MCHP_QMSPI_C_4X			(2ul << 0) /* Quad IO */
-#define MCHP_QMSPI_C_TX_DIS		(0ul << 2)
-#define MCHP_QMSPI_C_TX_DATA		(1ul << 2)
-#define MCHP_QMSPI_C_TX_ZEROS		(2ul << 2)
-#define MCHP_QMSPI_C_TX_ONES		(3ul << 2)
-#define MCHP_QMSPI_C_TX_DMA_DIS		(0ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_1B		(1ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_2B		(2ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_4B		(3ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_MASK	(3ul << 4)
-#define MCHP_QMSPI_C_RX_DIS		0
-#define MCHP_QMSPI_C_RX_EN		BIT(6)
-#define MCHP_QMSPI_C_RX_DMA_DIS		(0ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_1B		(1ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_2B		(2ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_4B		(3ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_MASK	(3ul << 7)
-#define MCHP_QMSPI_C_NO_CLOSE		0
-#define MCHP_QMSPI_C_CLOSE		BIT(9)
-#define MCHP_QMSPI_C_XFRU_BITS		(0ul << 10)
-#define MCHP_QMSPI_C_XFRU_1B		(1ul << 10)
-#define MCHP_QMSPI_C_XFRU_4B		(2ul << 10)
-#define MCHP_QMSPI_C_XFRU_16B		(3ul << 10)
-#define MCHP_QMSPI_C_XFRU_MASK		(3ul << 10)
-/* Control */
-#define MCHP_QMSPI_C_START_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_START_DESCR_MASK	(0xFul << 12)
-#define MCHP_QMSPI_C_DESCR_MODE_EN	BIT(16)
-/* Descriptors, indicates the current descriptor is the last */
-#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK0	0xFul
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK \
-	((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
-#define MCHP_QMSPI_C_NXTD(n) ((n) << 12)
-#define MCHP_QMSPI_C_DESCR_LAST		BIT(16)
-/*
- * Total transfer length is the count in this field
- * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx
- */
-#define MCHP_QMSPI_C_NUM_UNITS_BITPOS	17
-#define MCHP_QMSPI_C_MAX_UNITS		0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK0	0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK \
-	((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
-/* Bits in MCHP_QMSPI0_EXE */
-#define MCHP_QMSPI_EXE_START		BIT(0)
-#define MCHP_QMSPI_EXE_STOP		BIT(1)
-#define MCHP_QMSPI_EXE_CLR_FIFOS	BIT(2)
-/* MCHP QMSPI FIFO Sizes */
-#define MCHP_QMSPI_TX_FIFO_LEN		8
-#define MCHP_QMSPI_RX_FIFO_LEN		8
-/* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */
-#define MCHP_QMSPI_STS_DONE		BIT(0)
-#define MCHP_QMSPI_STS_DMA_DONE		BIT(1)
-#define MCHP_QMSPI_STS_TX_BUFF_ERR	BIT(2)
-#define MCHP_QMSPI_STS_RX_BUFF_ERR	BIT(3)
-#define MCHP_QMSPI_STS_PROG_ERR		BIT(4)
-#define MCHP_QMSPI_STS_TX_BUFF_FULL	BIT(8)
-#define MCHP_QMSPI_STS_TX_BUFF_EMPTY	BIT(9)
-#define MCHP_QMSPI_STS_TX_BUFF_REQ	BIT(10)
-#define MCHP_QMSPI_STS_TX_BUFF_STALL	BIT(11) /* status only */
-#define MCHP_QMSPI_STS_RX_BUFF_FULL	BIT(12)
-#define MCHP_QMSPI_STS_RX_BUFF_EMPTY	BIT(13)
-#define MCHP_QMSPI_STS_RX_BUFF_REQ	BIT(14)
-#define MCHP_QMSPI_STS_RX_BUFF_STALL	BIT(15) /* status only */
-#define MCHP_QMSPI_STS_ACTIVE		BIT(16) /* status only */
-/* Bits in MCHP_QMSPI0_BUFCNT (read-only) */
-#define MCHP_QMSPI_BUFCNT_TX_BITPOS	0
-#define MCHP_QMSPI_BUFCNT_TX_MASK	0xFFFFul
-#define MCHP_QMSPI_BUFCNT_RX_BITPOS	16
-#define MCHP_QMSPI_BUFCNT_RX_MASK	(0xFFFFul << 16)
-#define MCHP_QMSPI0_ID			0
-
-/* eSPI */
-/* eSPI IO Component */
-/* Peripheral Channel Registers */
-#define MCHP_ESPI_PC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x114)
-#define MCHP_ESPI_PC_IEN		REG32(MCHP_ESPI_IO_BASE + 0x118)
-#define MCHP_ESPI_PC_BAR_INHIBIT_LO	REG32(MCHP_ESPI_IO_BASE + 0x120)
-#define MCHP_ESPI_PC_BAR_INHIBIT_HI	REG32(MCHP_ESPI_IO_BASE + 0x124)
-#define MCHP_ESPI_PC_BAR_INIT_LD_0C	REG16(MCHP_ESPI_IO_BASE + 0x128)
-#define MCHP_ESPI_PC_EC_IRQ		REG8(MCHP_ESPI_IO_BASE + 0x12C)
-/* LTR Registers */
-#define MCHP_ESPI_IO_LTR_STATUS		REG16(MCHP_ESPI_IO_BASE + 0x220)
-#define MCHP_ESPI_IO_LTR_IEN		REG8(MCHP_ESPI_IO_BASE + 0x224)
-#define MCHP_ESPI_IO_LTR_CTRL		REG16(MCHP_ESPI_IO_BASE + 0x228)
-#define MCHP_ESPI_IO_LTR_MSG		REG16(MCHP_ESPI_IO_BASE + 0x22C)
-/* OOB Channel Registers */
-#define MCHP_ESPI_OOB_RX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x240)
-#define MCHP_ESPI_OOB_RX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x244)
-#define MCHP_ESPI_OOB_TX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x248)
-#define MCHP_ESPI_OOB_TX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x24C)
-#define MCHP_ESPI_OOB_RX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x250)
-#define MCHP_ESPI_OOB_TX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x254)
-#define MCHP_ESPI_OOB_RX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x258)
-#define MCHP_ESPI_OOB_RX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x25C)
-#define MCHP_ESPI_OOB_RX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x260)
-#define MCHP_ESPI_OOB_TX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x264)
-#define MCHP_ESPI_OOB_TX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x268)
-#define MCHP_ESPI_OOB_TX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x26C)
-/* Flash Channel Registers */
-#define MCHP_ESPI_FC_ADDR_LO		REG32(MCHP_ESPI_IO_BASE + 0x280)
-#define MCHP_ESPI_FC_ADDR_HI		REG32(MCHP_ESPI_IO_BASE + 0x284)
-#define MCHP_ESPI_FC_BUF_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x288)
-#define MCHP_ESPI_FC_BUF_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x28C)
-#define MCHP_ESPI_FC_XFR_LEN		REG32(MCHP_ESPI_IO_BASE + 0x290)
-#define MCHP_ESPI_FC_CTL		REG32(MCHP_ESPI_IO_BASE + 0x294)
-#define MCHP_ESPI_FC_IEN		REG8(MCHP_ESPI_IO_BASE + 0x298)
-#define MCHP_ESPI_FC_CONFIG		REG32(MCHP_ESPI_IO_BASE + 0x29C)
-#define MCHP_ESPI_FC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x2A0)
-/* VWire Channel Registers */
-#define MCHP_ESPI_VW_STATUS		REG8(MCHP_ESPI_IO_BASE + 0x2B0)
-/* Global Registers */
-/* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */
-#define MCHP_ESPI_IO_REG32_A		REG32(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP_ID		REG8(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP0		REG8(MCHP_ESPI_IO_BASE + 0x2E1)
-#define MCHP_ESPI_IO_CAP1		REG8(MCHP_ESPI_IO_BASE + 0x2E2)
-#define MCHP_ESPI_IO_PC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E3)
-/* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */
-#define MCHP_ESPI_IO_REG32_B		REG32(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_VW_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_OOB_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E5)
-#define MCHP_ESPI_IO_FC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E6)
-#define MCHP_ESPI_IO_PC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E7)
-/* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */
-#define MCHP_ESPI_IO_REG32_C		REG32(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_OOB_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_FC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E9)
-#define MCHP_ESPI_IO_RESET_STATUS	REG8(MCHP_ESPI_IO_BASE + 0x2EA)
-#define MCHP_ESPI_IO_RESET_IEN		REG8(MCHP_ESPI_IO_BASE + 0x2EB)
-/* 32-bit register containing PLTRST_SRC/VW_READY */
-#define MCHP_ESPI_IO_REG32_D		REG32(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_PLTRST_SRC		REG8(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_VW_READY		REG8(MCHP_ESPI_IO_BASE + 0x2ED)
-/* Bits in MCHP_ESPI_IO_CAP0 */
-#define MCHP_ESPI_CAP0_PC_SUPP		0x01
-#define MCHP_ESPI_CAP0_VW_SUPP		0x02
-#define MCHP_ESPI_CAP0_OOB_SUPP		0x04
-#define MCHP_ESPI_CAP0_FC_SUPP		0x08
-#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP	(MCHP_ESPI_CAP0_PC_SUPP | \
-					MCHP_ESPI_CAP0_VW_SUPP | \
-					MCHP_ESPI_CAP0_OOB_SUPP | \
-					MCHP_ESPI_CAP0_FC_SUPP)
-/* Bits in MCHP_ESPI_IO_CAP1 */
-#define MCHP_ESPI_CAP1_RW_MASK		0x37
-#define MCHP_ESPI_CAP1_MAX_FREQ_MASK	0x07
-#define MCHP_ESPI_CAP1_MAX_FREQ_20M	0
-#define MCHP_ESPI_CAP1_MAX_FREQ_25M	1
-#define MCHP_ESPI_CAP1_MAX_FREQ_33M	2
-#define MCHP_ESPI_CAP1_MAX_FREQ_50M	3
-#define MCHP_ESPI_CAP1_MAX_FREQ_66M	4
-#define MCHP_ESPI_CAP1_SINGLE_MODE	0
-#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE	BIT(0)
-#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE	BIT(1)
-#define MCHP_ESPI_CAP1_ALL_MODE		(MCHP_ESPI_CAP1_SINGLE_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_QUAD_MODE)
-#define MCHP_ESPI_CAP1_IO_BITPOS	4
-#define MCHP_ESPI_CAP1_IO_MASK0		0x03
-#define MCHP_ESPI_CAP1_IO_MASK		(0x03ul << MCHP_ESPI_CAP1_IO_BITPOS)
-#define MCHP_ESPI_CAP1_IO1_VAL		0x00
-#define MCHP_ESPI_CAP1_IO12_VAL		0x01
-#define MCHP_ESPI_CAP1_IO24_VAL		0x02
-#define MCHP_ESPI_CAP1_IO124_VAL	0x03
-#define MCHP_ESPI_CAP1_IO1		(0x00 << 4)
-#define MCHP_ESPI_CAP1_IO12		(0x01 << 4)
-#define MCHP_ESPI_CAP1_IO24		(0x02 << 4)
-#define MCHP_ESPI_CAP1_IO124		(0x03 << 4)
-/* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */
-#define MCHP_ESPI_RST_PIN_MASK		BIT(1)
-#define MCHP_ESPI_RST_CHG_STS		BIT(0)
-#define MCHP_ESPI_RST_IEN		BIT(0)
-/* Bits in MCHP_ESPI_IO_PLTRST_SRC */
-#define MCHP_ESPI_PLTRST_SRC_VW		0
-#define MCHP_ESPI_PLTRST_SRC_PIN	1
-/*
- * eSPI Slave Activate Register
- * bit[0] = 0 de-active block is clock-gates
- * bit[0] = 1 block is powered and functional
- */
-#define MCHP_ESPI_ACTIVATE		REG8(MCHP_ESPI_IO_BASE + 0x330)
-/*
- * IO BAR's starting at offset 0x134
- * b[16]=virtualized R/W
- * b[15:14]=0 reserved RO
- * b[13:8]=Logical Device Number RO
- * b[7:0]=mask
- */
-#define MCHP_ESPI_IO_BAR_CTL(x)	\
-	REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
-/* access mask field of eSPI IO BAR Control register */
-#define MCHP_ESPI_IO_BAR_CTL_MASK(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
-/*
- * IO BAR's starting at offset 0x334
- * b[31:16] = I/O address
- * b[15:1]=0 reserved
- * b[0] = valid
- */
-#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_VALID(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
-#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x337)
-#define MCHP_ESPI_IO_BAR_ADDR(x) \
-	REG16(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
-/* eSPI Serial IRQ registers */
-#define MCHP_ESPI_IO_SERIRQ_REG(x)	REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x))
-/* eSPI Virtual Wire Error Register */
-#define MCHP_ESPI_IO_VW_ERROR		REG8(MCHP_ESPI_IO_BASE + 0x3f0)
-/*
- * eSPI Logical Device Memory Host BAR's to specify Host memory
- * base address and valid bit.
- * Each Logical Device implementing memory access has an 80-bit register.
- * b[0]=Valid
- * b[15:1]=0(reserved)
- * b[79:16]=eSPI bus memory address(Host address space)
- */
-#define MCHP_ESPI_MBAR_VALID(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x130)
-#define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x132)
-#define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x134)
-#define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x136)
-#define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x138)
-/*
- * eSPI SRAM BAR's
- * b[0,3,8:15] = 0 reserved
- * b[2:1] = access
- * b[7:4] = size
- * b[79:16] = Host address
- */
-#define MCHP_ESPI_SRAM_BAR_CFG(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ac)
-#define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ae)
-#define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b0)
-#define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b2)
-#define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b4)
-/* eSPI Memory Bus Master Registers */
-#define MCHP_ESPI_BM_STATUS		REG32(MCHP_ESPI_MEM_BASE + 0x200)
-#define MCHP_ESPI_BM_IEN		REG32(MCHP_ESPI_MEM_BASE + 0x204)
-#define MCHP_ESPI_BM_CONFIG		REG32(MCHP_ESPI_MEM_BASE + 0x208)
-#define MCHP_ESPI_BM1_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x210)
-#define MCHP_ESPI_BM1_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x214)
-#define MCHP_ESPI_BM1_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x218)
-#define MCHP_ESPI_BM1_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x21c)
-#define MCHP_ESPI_BM2_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x224)
-#define MCHP_ESPI_BM2_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x228)
-#define MCHP_ESPI_BM2_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x22c)
-#define MCHP_ESPI_BM2_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x230)
-/*
- * eSPI Memory BAR's for Logical Devices
- * b[0] = Valid
- * b[2:1] = access
- * b[3] = 0 reserved
- * b[7:4] = size
- * b[15:8] = 0 reserved
- * b[47:16] = EC SRAM Address where Host address is mapped
- * b[79:48] = 0 reserved
- *
- * BAR's start at offset 0x330
- */
-#define MCHP_ESPI_MBAR_EC_VSIZE(x) \
-	REG32(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x330)
-#define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x332)
-#define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x334)
-#define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x336)
-
-/* eSPI Virtual Wire registers */
-#define MCHP_ESPI_MSVW_LEN	12
-#define MCHP_ESPI_SMVW_LEN	8
-
-#define MCHP_ESPI_MSVW_ADDR(n) \
-	((MCHP_ESPI_MSVW_BASE) + ((n) * (MCHP_ESPI_MSVW_LEN)))
-
-#define MCHP_ESPI_MSVW_MTOS_BITPOS 4
-
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO		0
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI		1
-#define MCHP_ESPI_MSVW_IRQSEL_DISABLED		4
-#define MCHP_ESPI_MSVW_IRQSEL_RISING		0x0d
-#define MCHP_ESPI_MSVW_IRQSEL_FALLING		0x0e
-#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES	0x0f
-
-/*
- * Mapping of eSPI Master Host VWire group indices to
- * MCHP eSPI Master to Slave 96-bit VWire registers.
- * MSVW_xy where xy = PCH VWire number.
- * Each PCH VWire number controls 4 virtual wires.
- */
-#define MSVW_H02	0
-#define MSVW_H03	1
-#define MSVW_H07	2
-#define MSVW_H41	3
-#define MSVW_H42	4
-#define MSVW_H43	5
-#define MSVW_H44	6
-#define MSVW_H47	7
-#define MSVW_H4A	8
-#define MSVW_HSPARE0	9
-#define MSVW_HSPARE1	10
-#define MSVW_MAX	11
-
-/* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */
-#define MSVW(id, w) \
-	REG32(MCHP_ESPI_MSVW_BASE + ((id) * 12) + (((w) & 0x03) * 4))
-/* Access index value in byte 0 */
-#define MCHP_ESPI_VW_M2S_INDEX(id)	REG8(MCHP_ESPI_VW_BASE + ((id) * 12))
-/*
- * Access MTOS_SOURCE and MTOS_STATE in byte 1
- * MTOS_SOURCE = b[1:0] specifies reset source
- * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event
- */
-#define MCHP_ESPI_VW_M2S_MTOS(id) \
-	REG8(MCHP_ESPI_VW_BASE + 1 + ((id) * 12))
-/*
- * Access Index, MTOS Source, and MTOS State as 16-bit quantity.
- * Index in b[7:0]
- * MTOS Source in b[9:8]
- * MTOS State in b[15:12]
- */
-#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 12))
-/* Access SRCn IRQ Select bit fields */
-#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
-#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 5)
-#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 6)
-#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 7)
-#define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4 + ((src) & 0x03))
-#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
-/* Access individual source bits */
-#define MCHP_ESPI_VW_M2S_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 8)
-#define MCHP_ESPI_VW_M2S_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 9)
-#define MCHP_ESPI_VW_M2S_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 10)
-#define MCHP_ESPI_VW_M2S_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 11)
-/*
- * Access all four Source bits as 32-bit value, Source bits are located
- * at bits[0, 8, 16, 24] of 32-bit word.
- */
-#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + 8 + ((id) * 12))
-/*
- * Access an individual Source bit as byte where
- * bit[0] contains the source bit.
- */
-#define MCHP_ESPI_VW_M2S_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 8 + ((id) * 8) + ((src) & 0x03))
-
-/*
- * Indices of Slave to Master Virtual Wire registers.
- * Registers are 64-bit.
- * Host chipset groups VWires into groups of 4 with
- * a spec. defined index.
- * SMVW_Ixy where xy = eSPI Master defined index.
- * MCHP maps Host indices into its Slave to Master
- * 64-bit registers.
- */
-#define SMVW_H04	0
-#define SMVW_H05	1
-#define SMVW_H06	2
-#define SMVW_H40	3
-#define SMVW_H45	4
-#define SMVW_H46	5
-#define SMVW_HSPARE6	6
-#define SMVW_HSPARE7	7
-#define SMVW_HSPARE8	8
-#define SMVW_HSPARE9	9
-#define SMVW_HSPARE10	10
-#define SMVW_MAX	11
-
-/* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */
-#define SMVW(id, w) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200 + (((w) & 0x01) * 4))
-/* Access Index in b[7:0] of byte 0 */
-#define MCHP_ESPI_VW_S2M_INDEX(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
-/* Access STOM_SOURCE and STOM_STATE in byte 1
- * STOM_SOURCE = b[1:0]
- * STOM_STATE = b[7:4]
- */
-#define MCHP_ESPI_VW_S2M_STOM(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x201)
-/* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0]
- * Index = b[7:0]
- * STOM_SOURCE = b[9:8]
- * STOM_STATE = [15:12]
- */
-#define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
-/* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */
-#define MCHP_ESPI_VW_S2M_CHANGE(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x202)
-/* Access individual SRC bits
- * bit[0] = SRCn
- */
-#define MCHP_ESPI_VW_S2M_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
-#define MCHP_ESPI_VW_S2M_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x205)
-#define MCHP_ESPI_VW_S2M_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x206)
-#define MCHP_ESPI_VW_S2M_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x207)
-/*
- * Access specified source bit as byte read/write.
- * Source bit is in bit[0] of byte.
- */
-#define MCHP_ESPI_VW_S2M_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) * 8) + ((src) & 0x03))
-/* Access SRC[0:3] as 32-bit word
- * SRC0 = b[0]
- * SRC1 = b[8]
- * SRC2 = b[16]
- * SRC3 = b[24]
- */
-#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
-
-/* DMA */
-#define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00)
-#define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04)
-#define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08)
-/* DMA Channel Registers */
-#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS))
-#define MCHP_DMA_CH_MEM_START(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x04)
-#define MCHP_DMA_CH_MEM_END(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x08)
-#define MCHP_DMA_CH_DEV_ADDR(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x0c)
-#define MCHP_DMA_CH_CTRL(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x10)
-#define MCHP_DMA_CH_ISTS(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x14)
-#define MCHP_DMA_CH_IEN(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x18)
-#define MCHP_DMA_CH_FSM_RO(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x1c)
-/*
- * DMA Channel 0 implements CRC-32 feature
- */
-#define MCHP_DMA_CH0_CRC32_EN		REG8(MCHP_DMA_CH_BASE + 0x20)
-#define MCHP_DMA_CH0_CRC32_DATA		REG32(MCHP_DMA_CH_BASE + 0x24)
-#define MCHP_DMA_CH0_CRC32_POST_STS	REG8(MCHP_DMA_CH_BASE + 0x28)
-/*
- * DMA Channel 1 implements memory fill feature
- */
-#define MCHP_DMA_CH1_FILL_EN \
-	REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
-#define MCHP_DMA_CH1_FILL_DATA \
-	REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
-/* Bits for DMA Main Control */
-#define MCHP_DMA_MAIN_CTRL_ACT		BIT(0)
-#define MCHP_DMA_MAIN_CTRL_SRST		BIT(1)
-/* Bits for DMA channel regs */
-#define MCHP_DMA_ACT_EN			BIT(0)
-/* DMA Channel Control */
-#define MCHP_DMA_ABORT			BIT(25)
-#define MCHP_DMA_SW_GO			BIT(24)
-#define MCHP_DMA_XFER_SIZE_MASK		(7ul << 20)
-#define MCHP_DMA_XFER_SIZE(x)		((x) << 20)
-#define MCHP_DMA_DIS_HW_FLOW		BIT(19)
-#define MCHP_DMA_INC_DEV		BIT(17)
-#define MCHP_DMA_INC_MEM		BIT(16)
-#define MCHP_DMA_DEV(x)			((x) << 9)
-#define MCHP_DMA_DEV_MASK0		(0x7f)
-#define MCHP_DMA_DEV_MASK		(0x7f << 9)
-#define MCHP_DMA_TO_DEV			BIT(8)
-#define MCHP_DMA_DONE			BIT(2)
-#define MCHP_DMA_RUN			BIT(0)
-/* DMA Channel Status */
-#define MCHP_DMA_STS_ALU_DONE		BIT(3)
-#define MCHP_DMA_STS_DONE		BIT(2)
-#define MCHP_DMA_STS_HWFL_ERR		BIT(1)
-#define MCHP_DMA_STS_BUS_ERR		BIT(0)
-
-/*
- * Required structure typedef for common/dma.h interface
- * !!! checkpatch.pl will not like this !!!
- * structure moved to chip level dma.c
- * We can't remove dma_chan_t as its used in DMA API header.
- */
-struct MCHP_dma_chan {
-	uint32_t act;		/* Activate */
-	uint32_t mem_start;	/* Memory start address */
-	uint32_t mem_end;	/* Memory end address */
-	uint32_t dev;		/* Device address */
-	uint32_t ctrl;		/* Control */
-	uint32_t int_status;	/* Interrupt status */
-	uint32_t int_enabled;	/* Interrupt enabled */
-	uint32_t chfsm;		/* channel fsm read-only */
-	uint32_t alu_en;	/* channels 0 & 1 only */
-	uint32_t alu_data;	/* channels 0 & 1 only */
-	uint32_t alu_sts;	/* channel 0 only */
-	uint32_t alu_ro;	/* channel 0 only */
-	uint32_t rsvd[4];	/* 0x30 - 0x3F */
-};
-
-/* Common code and header file must use this */
-typedef struct MCHP_dma_chan dma_chan_t;
-
-/* Wake pin definitions, defined at board-level */
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c
deleted file mode 100644
index 48712e8b7e..0000000000
--- a/chip/mchp/spi.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* QMSPI master module for MCHP MEC family */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-#include "spi_chip.h"
-#include "qmspi_chip.h"
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#include "gpspi_chip.h"
-#endif
-#include "tfdp_chip.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-#if defined(CONFIG_MCHP_GPSPI) && defined(CHIP_FAMILY_MEC152X)
-#error "FORCED BUILD ERROR: MEC152X does not implement GPSPI!"
-#endif
-
-static const struct dma_option spi_rx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_RX,
-		(void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_RX,
-		(void *)&MCHP_SPI_RD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_RX,
-		(void *)&MCHP_SPI_RD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#endif
-};
-
-static const struct dma_option spi_tx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_TX,
-		(void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_TX,
-		(void *)&MCHP_SPI_TD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_TX,
-		(void *)&MCHP_SPI_TD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
-#endif
-#endif
-};
-
-/* only regular image needs mutex, LFW does not have scheduling */
-#ifndef LFW
-static struct mutex spi_mutex[ARRAY_SIZE(spi_rx_option)];
-
-/*
- * Acquire mutex for specified SPI controller/port.
- * Note if mutex is owned by another task this routine
- * will block until mutex is released.
- */
-static void spi_mutex_lock(uint8_t hw_port)
-{
-	uint32_t n;
-
-	n = 0;
-#ifdef CONFIG_MCHP_GPSPI
-	if (hw_port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (hw_port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-	mutex_lock(&spi_mutex[n]);
-}
-
-/*
- * Release mutex for specified SPI controller/port.
- */
-static void spi_mutex_unlock(uint8_t hw_port)
-{
-	uint32_t n;
-
-	n = 0;
-#ifdef CONFIG_MCHP_GPSPI
-	if (hw_port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (hw_port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-	mutex_unlock(&spi_mutex[n]);
-}
-#endif /* #ifndef LFW */
-
-/*
- * Public SPI interface
- */
-
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx)
-{
-	uint32_t n;
-
-	if (spi_device == NULL)
-		return NULL;
-
-	n = 0;
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	if (spi_device->port & 0xF0) {
-#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03
-		n = (spi_device->port & 0x0F) + 1;
-#else
-		n = 1;
-#endif
-	}
-#endif
-
-	if (is_tx)
-		return &spi_tx_option[n];
-	else
-		return &spi_rx_option[n];
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
-		break;
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_flush(spi_device);
-		break;
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_flush(spi_device);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-/* Wait for async response received but do not de-assert chip select */
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_INVAL;
-
-	switch (spi_device->port) {
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-#ifndef LFW
-	case GPSPI0_PORT:
-	case GPSPI1_PORT:
-		rc = gpspi_transaction_wait(spi_device);
-		break;
-#endif
-#endif
-	case QMSPI0_PORT:
-		rc = qmspi_transaction_wait(spi_device);
-		break;
-	default:
-		rc = EC_ERROR_INVAL;
-	}
-
-	return rc;
-}
-
-/*
- * called from common/spi_flash.c
- * For tranfers reading less than the size of QMSPI RX FIFO call
- * a routine where reads use FIFO only no DMA.
- * GP-SPI only has a one byte RX FIFO but small data transfers will be OK
- * without the overhead of DMA setup.
- */
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rc;
-
-	if (spi_device == NULL)
-		return EC_ERROR_PARAM1;
-
-#ifndef LFW
-	spi_mutex_lock(spi_device->port);
-#endif
-
-	rc = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	if (rc == EC_SUCCESS)
-		rc = spi_transaction_flush(spi_device);
-
-#ifndef LFW
-	spi_mutex_unlock(spi_device->port);
-#endif
-
-	return rc;
-}
-
-/**
- * Enable SPI port and associated controller
- *
- * @param spi_device SPI device
- * @param enable
- * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized
- * @note called from common/spi_flash.c
- *
- * spi_device->port is defined as
- * bits[3:0] = controller instance
- * bits[7:4] = controller family 0 = QMSPI, 1 = GPSPI
- */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int rc;
-	uint8_t hw_port = spi_device->port;
-	rc = EC_ERROR_INVAL;
-
-	if ((hw_port & 0xF0) == QMSPI_CLASS)
-		rc = qmspi_enable(hw_port, enable);
-#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
-	if ((hw_port & 0xF0) == GPSPI_CLASS)
-		rc = gpspi_enable(hw_port, enable);
-#endif
-	return rc;
-}
diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h
deleted file mode 100644
index 75973e4a78..0000000000
--- a/chip/mchp/spi_chip.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MCHP MEC processor
- */
-/** @file qmpis_chip.h
- *MCHP MEC Quad SPI Master
- */
-/** @defgroup MCHP MEC qmspi
- */
-
-#ifndef _SPI_CHIP_H
-#define _SPI_CHIP_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* struct spi_device_t */
-#include "spi.h"
-
-#define SPI_DMA_OPTION_RD	0
-#define SPI_DMA_OPTION_WR	1
-
-/*
- * bits[3:0] = controller instance
- * bits[7:4] = controller family
- * 0 = QMSPI, 1 = GPSPI
- */
-#define QMSPI0_PORT	0x00
-#define GPSPI0_PORT	0x10
-#define GPSPI1_PORT	0x11
-
-
-#define QMSPI_CLASS0	0
-#define GPSPI_CLASS0	1
-
-#define QMSPI_CLASS	(0 << 4)
-#define GPSPI_CLASS	BIT(4)
-
-#define QMSPI_CTRL0	0
-#define GPSPI_CTRL0	0
-#define GPSPI_CTRL1	1
-
-/*
- * Encode zero based controller class and instance values
- * in port value of spi_device_t.
- */
-#define SPI_CTRL_ID(c, i) (((c & 0xf) << 4) + (i & 0xf))
-
-/*
- * helper to return pointer to QMSPI or GPSPI struct dma_option
- */
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx);
-
-#endif /* #ifndef _QMSPI_CHIP_H */
-/**   @}
- */
-
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
deleted file mode 100644
index d67314d716..0000000000
--- a/chip/mchp/system.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : MCHP hardware specific implementation */
-
-#include <stdnoreturn.h>
-
-#include "common.h" /* includes config.h and board.h */
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "tfdp_chip.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-/* Index values for hibernate data registers (RAM backed by VBAT) */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratch pad */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,		/* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,		/* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,		/* USB-PD2 saved port state */
-};
-
-/*
- * Voltage rail configuration
- * MEC172x VTR1 is 3.3V only, VTR2 is auto-detected 3.3 or 1.8V, and
- * VTR3 is always 1.8V.
- * MEC170x and MEC152x require manual selection of VTR3 for 1.8 or 3.3V.
- * The eSPI pins are on VTR3 and require 1.8V
- */
-#ifdef CHIP_FAMILY_MEC172X
-static void vtr3_voltage_select(int use18v)
-{
-	(void) use18v;
-}
-#else
-static void vtr3_voltage_select(int use18v)
-{
-	if (use18v)
-		MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18;
-	else
-		MCHP_EC_GPIO_BANK_PWR &= ~(MCHP_EC_GPIO_BANK_PWR_VTR3_18);
-}
-#endif
-
-
-/*
- * The current logic will set EC_RESET_FLAG_RESET_PIN flag
- * even if the reset was caused by WDT. MEC170x/MEC152x HW RESET_SYS
- * status goes active for any of the following:
- *	RESET_VTR: power rail change
- *	WDT Event: WDT timed out
- *	FW triggered chip reset: SYSRESETREQ or PCR sys reset bit
- * The code does check WDT status in the VBAT PFR register.
- * Is it correct to report both EC_RESET_FLAG_RESET_PIN and
- * EC_RESET_FLAG_WATCHDOG on a WDT only reset?
- */
-static void check_reset_cause(void)
-{
-	uint32_t status = MCHP_VBAT_STS;
-	uint32_t flags = 0;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				(MCHP_PWR_RST_STS_SYS |
-				MCHP_PWR_RST_STS_VBAT);
-
-	/* Clear the reset causes now that we've read them */
-	MCHP_VBAT_STS |= status;
-	MCHP_PCR_PWR_RST_STS |= rst_sts;
-
-	/*
-	 * BIT[6] indicates RESET_SYS asserted.
-	 * RESET_SYS will assert on VTR reset, WDT reset, or
-	 * firmware triggering a reset using Cortex-M4 SYSRESETREQ
-	 * or MCHP PCR system reset register.
-	 */
-	if (rst_sts & MCHP_PWR_RST_STS_SYS)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-
-	flags |= chip_read_reset_flags();
-	chip_save_reset_flags(0);
-
-	if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	system_set_reset_flags(flags);
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT))
-		return 0;
-	else
-		return 1;
-}
-
-/*
- * Sleep unused blocks to reduce power.
- * Drivers/modules will clear PCR sleep enables for their blocks.
- * Keep sleep enables cleared for required blocks:
- * ECIA, PMC, CPU, ECS and optionally JTAG.
- * SLEEP_ALL feature will set these upon sleep entry.
- * Based on CONFIG_CHIPSET_DEBUG enable or disable ARM SWD
- * 2-pin JTAG mode.
- */
-static void chip_periph_sleep_control(void)
-{
-	uint32_t d;
-
-	d = MCHP_PCR_SLP_EN0_SLEEP;
-
-	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG)) {
-		d &= ~(MCHP_PCR_SLP_EN0_JTAG);
-		MCHP_EC_JTAG_EN = MCHP_JTAG_MODE_SWD | MCHP_JTAG_ENABLE;
-	} else
-		MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE);
-
-	MCHP_PCR_SLP_EN0 = d;
-	MCHP_PCR_SLP_EN1 = MCHP_PCR_SLP_EN1_UNUSED_BLOCKS;
-	MCHP_PCR_SLP_EN2 = MCHP_PCR_SLP_EN2_SLEEP;
-	MCHP_PCR_SLP_EN3 = MCHP_PCR_SLP_EN3_SLEEP;
-	MCHP_PCR_SLP_EN4 = MCHP_PCR_SLP_EN4_SLEEP;
-}
-
-#ifdef CONFIG_CHIP_PRE_INIT
-void chip_pre_init(void)
-{
-	chip_periph_sleep_control();
-
-	if (IS_ENABLED(CONFIG_MCHP_TFDP)) {
-		/* MCHP Enable TFDP for fast debug messages */
-		tfdp_power(1);
-		tfdp_enable(1, 1);
-		CPRINTS("chip_pre_init: Image type = 0x%02x",
-			MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX));
-	}
-}
-#endif
-
-void system_pre_init(void)
-{
-	/*
-	 * Make sure AHB Error capture is enabled.
-	 * Signals bus fault to Cortex-M4 core if an address presented
-	 * to AHB is not claimed by any HW block.
-	 */
-	MCHP_EC_AHB_ERR = 0;	/* write any value to clear */
-	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
-
-	/* Manual voltage selection only required for MEC170x and MEC152x */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
-		vtr3_voltage_select(1);
-	else
-		vtr3_voltage_select(0);
-
-	if (!IS_ENABLED(CONFIG_CHIP_PRE_INIT))
-		chip_periph_sleep_control();
-
-	/* Enable direct NVIC */
-	MCHP_EC_INT_CTRL |= 1;
-
-	/* Disable ARM TRACE debug port */
-	MCHP_EC_TRACE_EN &= ~1;
-
-	/*
-	 * Enable aggregated only interrupt GIRQ's
-	 * Make sure direct mode interrupt sources aggregated outputs
-	 * are not enabled.
-	 * Aggregated only GIRQ's 8,9,10,11,12,22,24,25,26
-	 * Direct GIRQ's = 13,14,15,16,17,18,19,21,23
-	 * These bits only need to be touched again on RESET_SYS.
-	 * NOTE: GIRQ22 wake for AHB peripherals not processor.
-	 */
-	MCHP_INT_BLK_DIS = 0xfffffffful;
-	MCHP_INT_BLK_EN = MCHP_INT_AGGR_ONLY_BITMAP;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
-}
-
-noreturn void _system_reset(int flags, int wake_from_hibernate)
-{
-	uint32_t save_flags = 0;
-
-	/* DEBUG */
-	CPRINTS("MEC system reset: flag = 0x%08x wake = %d", flags,
-		wake_from_hibernate);
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	if (wake_from_hibernate)
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-	else if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	else
-		save_flags |= EC_RESET_FLAG_SOFT;
-
-	chip_save_reset_flags(save_flags);
-
-	/*
-	 * Trigger chip reset
-	 */
-	if (!IS_ENABLED(CONFIG_DEBUG_BRINGUP))
-		MCHP_PCR_SYS_RST |= MCHP_PCR_SYS_SOFT_RESET;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	_system_reset(flags, 0);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mchp";
-}
-
-#ifdef CHIP_VARIANT_MEC1701
-/*
- * MEC1701H Chip ID = 0x2D
- *              Rev = 0x82
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEV_ID) {
-	case 0x2D:
-		return "mec1701";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-#ifdef CHIP_FAMILY_MEC152X
-/*
- * MEC152x family implements chip ID as a 32-bit
- * register where:
- * b[31:16] = 16-bit Device ID
- * b[15:8] = 8-bit Sub ID
- * b[7:0] = Revision
- *
- * MEC1521-128 WFBGA 0023_33_xxh
- * MEC1521-144 WFBGA 0023_34_xxh
- * MEC1523-144 WFBGA 0023_B4_xxh
- * MEC1527-144 WFBGA 0023_74_xxh
- * MEC1527-128 WFBGA 0023_73_xxh
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
-	case 0x00201400: /* 144 pin rev A? */
-		return "mec1503_revA";
-	case 0x00203400: /* 144 pin */
-		return "mec1501";
-	case 0x00207400: /* 144 pin */
-		return "mec1507";
-	case 0x00208400: /* 144 pin */
-		return "mec1503";
-	case 0x00233300: /* 128 pin */
-	case 0x00233400: /* 144 pin */
-		return "mec1521";
-	case 0x0023B400: /* 144 pin */
-		return "mec1523";
-	case 0x00237300: /* 128 pin */
-	case 0x00237400: /* 144 pin */
-		return "mec1527";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-#ifdef CHIP_FAMILY_MEC172X
-/*
- * MEC172x family implements chip ID as a 32-bit
- * register where:
- * b[31:16] = 16-bit Device ID
- * b[15:8] = 8-bit Sub ID
- * b[7:0] = Revision
- *
- * MEC1723N-B0-I/SZ 144 pin: 0x0022_34_xx
- * MEC1727N-B0-I/SZ 144 pin: 0x0022_74_xx
- * MEC1721N-B0-I/LJ 176 pin: 0x0022_27_xx
- * MEC1723N-B0-I/LJ 176 pin: 0x0022_37_xx
- * MEC1727N-B0-I/LJ 176 pin: 0x0022_77_xx
- */
-const char *system_get_chip_name(void)
-{
-	switch (MCHP_CHIP_DEVRID32 & ~(MCHP_CHIP_REV_MASK)) {
-	case 0x00223400:
-		return "MEC1723NSZ";
-	case 0x00227400:
-		return "MEC1727NSZ";
-	case 0x00222700:
-		return "MEC1721NLJ";
-	case 0x00223700:
-		return "MEC1723NLJ";
-	case 0x00227700:
-		return "MEC1727NLJ";
-	default:
-		return "unknown";
-	}
-}
-#endif
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = MCHP_CHIP_DEV_REV;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		return HIBDATA_INDEX_PD0;
-	case SYSTEM_BBRAM_IDX_PD1:
-		return HIBDATA_INDEX_PD1;
-	case SYSTEM_BBRAM_IDX_PD2:
-		return HIBDATA_INDEX_PD2;
-	default:
-		return 1;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	*value = MCHP_VBAT_RAM(hibdata);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	MCHP_VBAT_RAM(hibdata) = value;
-	return EC_SUCCESS;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-/*
- * Local function to disable clocks in the chip's host interface
- * so the chip can enter deep sleep. Only MEC170X has LPC.
- * MEC152x and MEC172x only include eSPI and SPI host interfaces.
- * NOTE: we do it this way because the LPC registers are only
- * defined for MEC170x and the IS_ENABLED() macro causes the
- * compiler to evaluate both true and false code paths.
- */
-#if defined(CONFIG_HOSTCMD_ESPI)
-static void disable_host_ifc_clocks(void)
-{
-	MCHP_ESPI_ACTIVATE &= ~0x01;
-}
-#else
-static void disable_host_ifc_clocks(void)
-{
-	#ifdef CHIP_FAMILY_MEC170X
-	MCHP_LPC_ACT &= ~0x1;
-	#endif
-}
-#endif
-
-
-/*
- * Called when hibernation timer is not used in deep sleep.
- * Switch 32 KHz clock logic from external 32KHz input to
- * internal silicon OSC.
- * NOTE: MEC172x auto-switches from external source to silicon
- * oscillator.
- */
-#ifdef CHIP_FAMILY_MEC172X
-static void switch_32k_pin2sil(void) {}
-#else
-static void switch_32k_pin2sil(void)
-{
-	MCHP_VBAT_CE &= ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN);
-}
-#endif
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	if (IS_ENABLED(CONFIG_HOSTCMD_PD)) {
-		/* Inform the PD MCU that we are going to hibernate. */
-		host_command_pd_request_hibernate();
-		/* Wait to ensure exchange with PD before hibernating. */
-		msleep(100);
-	}
-
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Disable interrupts */
-	interrupt_disable();
-	for (i = 0; i < MCHP_IRQ_MAX; ++i) {
-		task_disable_irq(i);
-		task_clear_pending_irq(i);
-	}
-
-	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) {
-		MCHP_INT_DISABLE(i) = 0xffffffff;
-		MCHP_INT_SOURCE(i)  = 0xffffffff;
-	}
-
-	/* Disable UART */
-	MCHP_UART_ACT(0) &= ~0x1;
-
-	disable_host_ifc_clocks();
-
-	/* Disable JTAG */
-	MCHP_EC_JTAG_EN &= ~1;
-
-	/* Stop watchdog */
-	MCHP_WDG_CTL &= ~(MCHP_WDT_CTL_ENABLE);
-
-	/* Stop timers */
-	MCHP_TMR32_CTL(0) &= ~1;
-	MCHP_TMR32_CTL(1) &= ~1;
-	for (i = 0; i < MCHP_TMR16_INSTANCES; i++)
-		MCHP_TMR16_CTL(i) &= ~1;
-
-	/* Power down ADC */
-	/*
-	 * If ADC is in middle of acquisition it will continue until finished
-	 */
-	MCHP_ADC_CTRL &= ~1;
-
-	/* Disable blocks */
-	MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK);
-
-	/* Setup GPIOs for hibernate */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-	if (hibernate_wake_pins_used > 0) {
-		for (i = 0; i < hibernate_wake_pins_used; ++i) {
-			const enum gpio_signal pin = hibernate_wake_pins[i];
-
-			gpio_reset(pin);
-			gpio_enable_interrupt(pin);
-		}
-
-		interrupt_enable();
-		task_enable_irq(MCHP_IRQ_GIRQ8);
-		task_enable_irq(MCHP_IRQ_GIRQ9);
-		task_enable_irq(MCHP_IRQ_GIRQ10);
-		task_enable_irq(MCHP_IRQ_GIRQ11);
-		task_enable_irq(MCHP_IRQ_GIRQ12);
-		task_enable_irq(MCHP_IRQ_GIRQ26);
-	}
-
-	if (seconds || microseconds) {
-		htimer_init();
-		system_set_htimer_alarm(seconds, microseconds);
-		interrupt_enable();
-	} else
-		switch_32k_pin2sil();
-
-	/*
-	 * Set sleep state
-	 * arm sleep state to trigger on next WFI
-	 */
-	CPU_SCB_SYSCTRL |= 0x4;
-	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_HEAVY;
-	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL;
-
-	asm("dsb");
-	asm("wfi");
-	asm("isb");
-	asm("nop");
-
-	/* Use fastest clock to speed through wake-up */
-	MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_FASTEST;
-
-	/* Reboot */
-	_system_reset(0, 1);
-
-	/* We should never get here. */
-	while (1)
-		;
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-DECLARE_IRQ(MCHP_IRQ_HTIMER0, htimer_interrupt, 1);
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
-
-	return *(lfw_vector + 1);
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
-}
-
diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c
deleted file mode 100644
index b4368b46a8..0000000000
--- a/chip/mchp/tfdp.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/** @file tfdp.c
- *MCHP Trace FIFO Data Port hardware access
- */
-/** @defgroup MCHP Peripherals TFDP
- *  @{
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "tfdp_chip.h"
-
-#ifdef CONFIG_MCHP_TFDP
-
-
-static uint32_t get_disable_intr(void)
-{
-	uint32_t m;
-
-	__asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m));
-
-	return m;
-}
-
-static void restore_intr(uint32_t m)
-{
-	if (!m)
-		__asm__ __volatile__ ("cpsie i" : : : "memory");
-}
-
-
-/**
- * tfdp_power - Gate clocks On/Off to TFDP block when idle
- *
- * @param pwr_on (0=Gate clocks when idle), (1=Do not gate
- *                 clocks when idle)
- */
-void tfdp_power(uint8_t pwr_on)
-{
-	if (pwr_on)
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_TFDP);
-	else
-		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP);
-}
-
-
-/**
- * tfdp_enable - Init Trace FIFO Data Port
- * @param uint8_t non-zero=enable TFDP, false=disable TFDP
- * @param uint8_t non-zero=change TFDP pin configuration.
- * If TFDP is enabled then GPIO170/171 set to Alt. Func. 1
- * Else GPIO170/171 set to GPIO input, internal pull-up enabled.
- * @note -
- */
-#define MCHP_TFDP_DATA	REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL	REG8(MCHP_TFDP_BASE + 0x04)
-
-void tfdp_enable(uint8_t en, uint8_t pin_cfg)
-{
-	if (en) {
-		MCHP_TFDP_CTRL = 0x01u;
-		if (pin_cfg)
-			gpio_config_module(MODULE_TFDP, 1);
-	} else {
-		MCHP_TFDP_CTRL = 0x00u;
-		if (pin_cfg)
-			gpio_config_module(MODULE_TFDP, 0);
-	}
-} /* end tfdp_enable() */
-
-
-/**
- * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
- * over TFDP.
- *
- * @param nbr 16-bit trace number
- * @param b unused
- *
- * @return uint8_t always TRUE
- * @note Function implements critical section.
- * Uses tool kit __disable_irq()/__enable_irq() pair which may use
- * priviledged Cortex-Mx instructions.
- */
-void TFDPTrace0(uint16_t nbr)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
- * and 16-bit data lsb first over TFDP.
- *
- * @param nbr 16-bit trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Function implements critical section.
- * Uses tool kit __disable_irq()/__enable_irq() pair which may use
- * priviledged Cortex-Mx instructions.
- */
-void TFDPTrace1(uint16_t nbr, uint32_t p1)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
- * and two 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
- * and three 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- * @param uint32_t p3 16-bit data3 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
- * and four 16-bit data parameters lsb first over TFDP.
- *
- * @param nbr trace number
- * @param b unused
- * @param uint32_t p1 16-bit data1 in b[15:0]
- * @param uint32_t p2 16-bit data2 in b[15:0]
- * @param uint32_t p3 16-bit data3 in b[15:0]
- * @param uint32_t p4 16-bit data4 in b[15:0]
- *
- * @return uint8_t always TRUE
- * @note Uses tool kit functions to save/disable/restore
- *       interrupts for critical section. These may use
- *       priviledged instructions.
- */
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p4;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 8);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- *  TFDPTrace11 - Transmit one 32-bit data item over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data to be transmitted
- *
- */
-void TFDPTrace11(uint16_t nbr, uint32_t p1)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-
-/**
- *  TFDPTrace12 - Transmit two 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *
- */
-void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-/**
- *  TFDPTrace13 - Transmit three 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *  @param uint32_t p3 32-bit data3 to be transmitted
- *
- */
-void TFDPTrace13(uint16_t nbr, uint32_t p1,
-		 uint32_t p2, uint32_t p3)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-/**
- *  TFDPTrace14 - Transmit four 32-bit data items over TFDP
- *
- *  @param nbr trace number
- *  @param b unused
- *  @param uint32_t p1 32-bit data1 to be transmitted
- *  @param uint32_t p2 32-bit data2 to be transmitted
- *  @param uint32_t p3 32-bit data3 to be transmitted
- *  @param uint32_t p4 32-bit data4 to be transmitted
- */
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
-{
-#ifdef MCHP_TRACE_MASK_IRQ
-	uint32_t prim;
-
-	prim = get_disable_intr();
-#endif
-
-	MCHP_TFDP_DATA = (TFDP_FRAME_START);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)nbr;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(nbr >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p1;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p1 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p2;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p2 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p3;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p3 >> 24);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)p4;
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 8);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 16);
-	TFDP_DELAY();
-	MCHP_TFDP_DATA = (uint8_t)(p4 >> 24);
-	TFDP_DELAY();
-
-#ifdef MCHP_TRACE_MASK_IRQ
-	restore_intr(prim);
-#endif
-}
-
-#endif /* #ifdef CONFIG_MCHP_TFDP */
-
-
-/* end tfdp.c */
-/**   @}
- */
diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h
deleted file mode 100644
index 64d4d0b77e..0000000000
--- a/chip/mchp/tfdp_chip.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/** @file tfdp_chip.h
- *MCHP MEC TFDP Peripheral Library API
- */
-/** @defgroup MCHP MEC Peripherals Trace
- */
-
-#ifndef _TFDP_CHIP_H
-#define _TFDP_CHIP_H
-
-#include <stdint.h>
-
-
-#ifdef CONFIG_MCHP_TFDP
-
-#undef TRACE0
-#undef TRACE1
-#undef TRACE2
-#undef TRACE3
-#undef TRACE4
-#undef TRACE11
-#undef TRACE12
-#undef TRACE13
-#undef TRACE14
-#undef trace0
-#undef trace1
-#undef trace2
-#undef trace3
-#undef trace4
-#undef trace11
-#undef trace12
-#undef trace13
-#undef trace14
-
-#define MCHP_TFDP_BASE_ADDR	(0x40008c00ul)
-
-#define TFDP_FRAME_START   (0xFD)
-
-#define TFDP_POWER_ON   (1u)
-#define TFDP_POWER_OFF  (0u)
-
-#define TFDP_ENABLE         (1u)
-#define TFDP_DISABLE        (0u)
-#define TFDP_CFG_PINS       (1u)
-#define TFDP_NO_CFG_PINS    (0u)
-
-#define  MCHP_TRACE_MASK_IRQ
-
-#define TFDP_DELAY()
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void tfdp_power(uint8_t pwr_on);
-void tfdp_enable(uint8_t en, uint8_t pin_cfg);
-void TFDPTrace0(uint16_t nbr);
-void TFDPTrace1(uint16_t nbr, uint32_t p1);
-void TFDPTrace2(uint16_t nbr, uint32_t p1,
-		uint32_t p2);
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3);
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		uint32_t p3, uint32_t p4);
-void TFDPTrace11(uint16_t nbr, uint32_t p1);
-void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2);
-void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3);
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4);
-
-#ifdef __cplusplus
-}
-#endif
-
-#define TRACE0(nbr, cat, b, str) TFDPTrace0(nbr)
-#define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1)
-#define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2)
-#define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \
-	p3, p4)
-#define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1)
-#define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2)
-#define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3)
-#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \
-	TFDPTrace14(nbr, p1, p2, p3, p4)
-
-
-#else /* #ifdef MCHP_TRACE */
-
-/* !!! To prevent compiler warnings of unused parameters,
- * when trace is disabled by TRGEN source processing,
- * you can either:
- * 1. Disable compiler's unused parameter warning
- * 2. Change these macros to write parameters to a read-only
- *    register.
- */
-#define tfdp_power(pwr_on)
-#define tfdp_enable(en, pin_cfg)
-#define TRACE0(nbr, cat, b, str)
-#define TRACE1(nbr, cat, b, str, p1)
-#define TRACE2(nbr, cat, b, str, p1, p2)
-#define TRACE3(nbr, cat, b, str, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4)
-#define TRACE11(nbr, cat, b, str, p1)
-#define TRACE12(nbr, cat, b, str, p1, p2)
-#define TRACE13(nbr, cat, b, str, p1, p2, p3)
-#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4)
-
-#endif /* #ifdef CONFIG_MCHP_TFDP */
-
-/*
- * Always define lower case traceN(...) as blank (fully removed)
- */
-#define trace0(nbr, cat, b, str)
-#define trace1(nbr, cat, b, str, p1)
-#define trace2(nbr, cat, b, str, p1, p2)
-#define trace3(nbr, cat, b, str, p1, p2, p3)
-#define trace4(nbr, cat, b, str, p1, p2, p3, p4)
-#define trace11(nbr, cat, b, str, p1)
-#define trace12(nbr, cat, b, str, p1, p2)
-#define trace13(nbr, cat, b, str, p1, p2, p3)
-#define trace14(nbr, cat, b, str, p1, p2, p3, p4)
-
-#endif /* #ifndef _TFDP_CHIP_H */
-/* end tfdp_chip.h */
-/**   @}
- */
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
deleted file mode 100644
index 56c99646a4..0000000000
--- a/chip/mchp/uart.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for MCHP MEC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "tfdp_chip.h"
-
-#define TX_FIFO_SIZE	16
-
-BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) &&
-	     (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES));
-
-#if CONFIG_UART_CONSOLE == 2
-
-#define UART_IRQ		MCHP_IRQ_UART2
-#define UART_IRQ_BIT		MCHP_UART2_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART2
-#define GPIO_UART_RX		GPIO_UART2_RX
-/* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(5)
-
-#elif CONFIG_UART_CONSOLE == 1
-
-#define UART_IRQ		MCHP_IRQ_UART1
-#define UART_IRQ_BIT		MCHP_UART1_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART1
-#define GPIO_UART_RX		GPIO_UART1_RX
-/* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(25)
-
-#else
-
-#define UART_IRQ		MCHP_IRQ_UART0
-#define UART_IRQ_BIT		MCHP_UART0_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART0
-#define GPIO_UART_RX		GPIO_UART0_RX
-/* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */
-#define UART_RX_PIN_GIRQ	9
-#define UART_RX_PIN_BIT		BIT(5)
-
-#endif /* CONFIG_UART_CONSOLE == 2 */
-
-static int init_done;
-static int tx_fifo_used;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (MCHP_UART_IER(CONFIG_UART_CONSOLE) & BIT(1))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(1);
-	task_trigger_irq(UART_IRQ);
-}
-
-void uart_tx_stop(void)
-{
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * We have no indication of free space in transmit FIFO. To work around
-	 * this, we check transmit FIFO empty bit every 16 characters written.
-	 */
-	return tx_fifo_used != 0 ||
-		(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
-}
-
-int uart_rx_available(void)
-{
-	return MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(0);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
-}
-
-int uart_read_char(void)
-{
-	return MCHP_UART_RB(CONFIG_UART_CONSOLE);
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	MCHP_UART_FCR(channel) = BIT(0) | BIT(1);
-}
-
-void uart_disable_interrupt(void)
-{
-	task_disable_irq(UART_IRQ);
-}
-
-void uart_enable_interrupt(void)
-{
-	task_enable_irq(UART_IRQ);
-}
-
-/**
- * Interrupt handler for UART.
- * Lower priority below other critical ISR's.
- */
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	/* Trace statement to provide time marker for UART output? */
-	uart_process_output();
-}
-DECLARE_IRQ(UART_IRQ, uart_ec_interrupt, 2);
-
-void uart_init(void)
-{
-	/* Clear UART PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(UART_PCR);
-
-	/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
-	MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
-
-	/* Set DLAB = 0 */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
-
-	/* Activate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/*
-	 * Enable interrupts for UART
-	 */
-	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
-	MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(0);
-	MCHP_UART_MCR(CONFIG_UART_CONSOLE) |= BIT(3);
-
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-
-	task_enable_irq(UART_IRQ);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	/* Disable the UART interrupt. */
-	task_disable_irq(UART_IRQ);  /* NVIC interrupt for UART=13 */
-
-	/*
-	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
-	 * with the flags defined in the gpio.inc file.
-	 */
-	gpio_reset(GPIO_UART_RX);
-
-	/* power-down/deactivate UART */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) &= ~BIT(0);
-
-	/* clear interrupt enable for UART */
-	MCHP_INT_DISABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-
-	/* Clear pending interrupts on UART RX pin */
-	MCHP_INT_SOURCE(UART_RX_PIN_GIRQ) = UART_RX_PIN_BIT;
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART_RX);
-}
-
-
-void uart_exit_dsleep(void)
-{
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not run at all.
-	 */
-	if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
-	MCHP_INT_SOURCE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-	MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
-	task_enable_irq(UART_IRQ);
-
-	/* power-up/activate UART0 */
-	MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py
deleted file mode 100755
index 7908b0bf37..0000000000
--- a/chip/mchp/util/pack_ec.py
+++ /dev/null
@@ -1,536 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC17xx
-# Based on MEC170x_ROM_Description.pdf DS00002225C (07-28-17).
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC1701 has 256KB SRAM from 0xE0000 - 0x120000
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF]
-# SPI flash size for board is 512KB
-# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags)
-#
-
-LFW_SIZE = 0x1000
-LOAD_ADDR = 0x0E0000
-LOAD_ADDR_RW = 0xE1000
-HEADER_SIZE = 0x40
-SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file, offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
-
-def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-def BuildHeader(args, payload_len, load_addr, rorofile):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
-
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
-
-  # byte[6]
-  b = 0
-  header.append(b)
-
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
-
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
-
-  # header signature is appended by the caller
-
-  return header
-
-
-def BuildHeader2(args, payload_len, load_addr, payload_entry):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
-
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
-
-  # byte[6]
-  b = 0
-  header.append(b)
-
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
-
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', payload_entry))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
-
-  # header signature is appended by the caller
-
-  return header
-
-#
-# Compute SHA-256 of data and return digest
-# as a bytearray
-#
-def HashByteArray(data):
-  hasher = hashlib.sha256()
-  hasher.update(data)
-  h = hasher.digest()
-  bah = bytearray(h)
-  return bah
-
-#
-# Return 64-byte signature of byte array data.
-# Signature is SHA256 of data with 32 0 bytes appended
-#
-def SignByteArray(data):
-  debug_print("Signature is SHA-256 of data")
-  sigb = HashByteArray(data)
-  sigb.extend(b'\0' * 32)
-  return sigb
-
-
-# MEC1701H supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the start of header",
-                      default=0x80)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-
-  return parser.parse_args()
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("\n")
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".payload_offset = ", hex(args.payload_offset))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", args.spi_read_cmd)
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".verbose = ", args.verbose)
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin MEC17xx pack_ec.py script")
-
-
-  # MEC17xx maximum 192KB each for RO & RW
-  # mec1701 chip Makefile sets args.spi_size = 512
-  # Tags at offset 0
-  #
-  print_args(args)
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mec1701/config_flash_layout.h
-  # defines.
-  # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at offset 0x40000 (256KB)
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  # debug
-  debug_print("EC_LFW + EC_RO length = ",hex(payload_len))
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RO except for last 4 bytes
-  # skip over 4KB LFW
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)]))
-    crc_ofs = payload_len - 4
-    debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  # Chromebooks are not using MEC BootROM ECDSA.
-  # We implemented the ECDSA disabled case where
-  # the 64-byte signature contains a SHA-256 of the binary plus
-  # 32 zeros bytes.
-  payload_signature = SignByteArray(payload)
-  # debug
-  printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
-
-  # MEC17xx Header is 0x80 bytes with an 64 byte signature
-  # (32 byte SHA256 + 32 zero bytes)
-  header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
-  # debug
-  printByteArrayAsHex(header, "Header LFW + EC_RO")
-
-  # MEC17xx payload ECDSA not used, 64 byte signature is
-  # SHA256 + 32 zero bytes
-  header_signature = SignByteArray(header)
-  # debug
-  printByteArrayAsHex(header_signature, "header_signature")
-
-  tag = BuildTag(args)
-  # MEC17xx truncate RW length to args.image_size to not overwrite LFW
-  # offset may be different due to Header size and other changes
-  # MCHP we want to append a SHA-256 to the end of the actual payload
-  # to test SPI read routines.
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  payload_rw = GetPayloadFromOffset(args.input, args.image_size)
-  debug_print("type(payload_rw) is ", type(payload_rw))
-  debug_print("len(payload_rw) is ", hex(len(payload_rw)))
-
-  # truncate to args.image_size
-  rw_len = args.image_size
-  payload_rw = payload_rw[:rw_len]
-  payload_rw_len = len(payload_rw)
-  debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
-
-  payload_entry_tuple = struct.unpack_from('<I', payload_rw, 4)
-  debug_print("payload_entry_tuple = ", payload_entry_tuple)
-
-  payload_entry = payload_entry_tuple[0]
-  debug_print("payload_entry = ", hex(payload_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(payload_rw)
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RW except for last 4 bytes
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload_rw[:(payload_rw_len - 32)]))
-    crc_ofs = payload_rw_len - 4
-    debug_print("EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload_rw[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  payload_rw_sig = SignByteArray(payload_rw)
-  # debug
-  printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC170x Boot-ROM Tags are located at SPI offset 0
-  spi_list.append((0, tag, "tag"))
-
-  spi_list.append((args.header_loc, header, "header(lwf + ro)"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature,
-    "header(lwf + ro) signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload,
-    "payload(lfw + ro)"))
-
-  offset = args.header_loc + args.payload_offset + payload_len
-
-  # No SPI Header for EC_RW as its not loaded by BootROM
-  spi_list.append((offset, payload_signature,
-                   "payload(lfw_ro) signature"))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  if rw_offset < offset + len(payload_signature):
-    print("ERROR: EC_RW overlaps EC_RO")
-
-  spi_list.append((rw_offset, payload_rw, "payload(rw)"))
-
-  # don't add to EC_RW. We don't know if Google will process
-  # EC SPI flash binary with other tools during build of
-  # coreboot and OS.
-  #offset = rw_offset + payload_rw_len
-  #spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py
deleted file mode 100755
index 34846cd6ba..0000000000
--- a/chip/mchp/util/pack_ec_mec152x.py
+++ /dev/null
@@ -1,803 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC152x
-# Based on MEC1521/MEC1523_ROM_Description.pdf
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC152xH has 256KB SRAM from 0xE0000 - 0x120000
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF]
-# SPI flash size for board is 512KB
-# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags)
-
-LFW_SIZE = 0x1000
-LOAD_ADDR = 0x0E0000
-LOAD_ADDR_RW = 0xE1000
-MEC152X_HEADER_SIZE = 0x140
-MEC152X_HEADER_VERSION = 0x02
-PAYLOAD_PAD_BYTE = b'\xff'
-SPI_ERASE_BLOCK_SIZE = 0x1000
-SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
-CHIP_MAX_CODE_SRAM_KB = 224
-
-MEC152X_DICT = {
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x02,
-                "PAYLOAD_OFFSET":0x140,
-                "PAYLOAD_GRANULARITY":128,
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
-
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
-
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
-
-  return payload
-
-def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
-
-# Return 0=Slow slew rate or 1=Fast slew rate
-def GetSpiSlewRate(args):
-    if args.spi_slew_fast == True:
-        return 1
-    return 0
-
-# Return SPI CPOL = 0 or 1
-def GetSpiCpol(args):
-    if args.spi_cpol == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MOSI
-# 0 = SPI Master drives data is stable on inactive to clock edge
-# 1 = SPI Master drives data is stable on active to inactive clock edge
-def GetSpiCphaMosi(args):
-    if args.spi_cpha_mosi == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MISO 0 or 1
-# 0 = SPI Master samples data on inactive to active clock edge
-# 1 = SPI Master samples data on active to inactive clock edge
-def GetSpiCphaMiso(args):
-    if args.spi_cpha_miso == 0:
-        return 0
-    return 1
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
-
-#
-# Build SPI image header for MEC152x
-# MEC152x image header size = 320(0x140) bytes
-#
-# Description using Python slice notation [start:start+len]
-#
-# header[0:4] = 'PHCM'
-# header[4] = header version = 0x02(MEC152x)
-# header[5] = SPI clock speed, drive strength, sampling mode
-#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
-#   bits[3:2] = SPI controller pins drive strength
-#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
-#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
-#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
-#   bit[6] = CHPHA_MOSI
-#       1:data change on first inactive to active clock edge
-#       0:data change on first active to inactive clock edge
-#   bit[7] = CHPHA_MISO:
-#       1: Data captured on first inactive to active clock edge
-#       0: Data captured on first active to inactive clock edge
-# header[6] Boot-ROM loader flags
-#   bits[2:0] = VTR0,1,2 rails. 0=3.3V, 1=1.8V. NOTE VTR1=0 always
-#   bits[5:3] = 111b
-#   bit[6]: For MEC152x controls authentication
-#           0=Authentication disabled. Signature is SHA-384 of FW payload
-#           1=Authentication enabled. Signature is ECDSA P-384
-#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
-# header[7]: SPI Flash read command
-#            0x03 1-1-1 read freq < 33MHz
-#            0x0B 1-1-1 + 8 clocks(data tri-stated)
-#            0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
-#            0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
-#            NOTE: Quad requires SPI flash device QE(quad enable) bit
-#            to be factory set. Enabling QE disables HOLD# and WP#
-#            functionality of the SPI flash device.
-# header[0x8:0xC] SRAM Load address little-endian format
-# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
-#                  this address on successful load. (little-endian)
-# header[0x10:0x12] little-endian format: FW binary size in units of
-#                   128 bytes(MEC152x)
-# header[0x12:0x14] = 0 reserved
-# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
-#                     header to FW payload.
-#                     MEC152x: Offset must be a multiple of 128
-#                     Offset must be > header size.
-#                     NOTE: If Authentication is enabled size includes
-#                     the appended signature.
-# MEC152x:
-# header[0x18] = Authentication key select. Set to 0 for no Authentication.
-# header[0x19:0x50] = 0 reserved.
-# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
-# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
-# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
-# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
-# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
-#
-def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = MEC152X_HEADER_SIZE
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = MEC152X_HEADER_VERSION
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqMHz = GetSpiClockParameter(args)
-  header[5] = (int(spiFreqMHz // 48) - 1) & 0x03
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # b[0]=0 VTR1 must be 3.3V
-  # b[1]=0(VTR2 3.3V), 1(VTR2 1.8V)
-  # b[2]=0(VTR3 3.3V), 1(VTR3 1.8V)
-  # b[5:3]=111b
-  # b[6]=0 No ECDSA
-  # b[7]=0 No encrypted FW image
-  header[6] = 0x7 << 3
-  if args.vtr2_V18 == True:
-      header[6] |= 0x02
-  if args.vtr3_V18 == True:
-      header[6] |= 0x04
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17
-  header[0x14:0x18] = chip_dict["PAYLOAD_OFFSET"].to_bytes(4, 'little')
-
-  # MEC152x: Disable ECDSA and encryption
-  header[0x18] = 0
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
-
-#
-# MEC152x 128-byte EC Info Block appended to
-# end of padded FW binary
-# bytes 0 through 103 are undefined, we set to 0xFF
-# bytes 104 through 119 are rollback permissions
-# bytes 120 through 123 are key revocation permissions
-# byte 124 = customer platform ID[7:0]
-# byte 125 = customer platform ID[15:8]
-# byte 126 = customer auto rollback flags
-# byte 127 = customer current image revision
-#
-def GenEcInfoBlock(args, chip_dict):
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
-
-#
-# Generate SPI FW image co-signature.
-# MEC152X cosignature is 96 bytes used by OEM FW
-# developer to sign their binary with ECDSA-P384-SHA384 or
-# some other signature algorithm that fits in 96 bytes.
-# At this time Cros-EC is not using this field, fill with 0xFF.
-# If this feature is implemented we need to read the OEM's
-# generated signature from a file and extract the binary
-# signature.
-#
-def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
-
-#
-# Generate SPI FW Image trailer.
-# MEC152X: Size = 160 bytes
-#   binary = payload || encryption_key_header || ec_info_block || cosignature
-#   trailer[0:48] = SHA384(binary)
-#   trailer[48:144] = 0xFF
-#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
-#       Authentication & encryption are not used therefore random data
-#       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
-    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
-    hasher = hashlib.sha384()
-    hasher.update(payload)
-    if ec_info_block != None:
-      hasher.update(ec_info_block)
-    if encryption_key_header != None:
-      hasher.update(encryption_key_header)
-    if cosignature != None:
-      hasher.update(cosignature)
-    trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
-
-    return trailer
-
-# MEC152xH supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-# FlashMap is an option for MEC152x
-# It is a 32 bit structure
-# bits[18:0] = bits[30:12] of second SPI flash base address
-# bits[23:19] = 0 reserved
-# bits[31:24] = CRC8 of bits[23:0]
-# Input:
-#   integer containing base address of second SPI flash
-#   This value is usually equal to the size of the first
-#   SPI flash and should be a multiple of 4KB
-# Output:
-#   bytearray of length 4
-def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  #TODO I commented this out. Why?
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC152X TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC152X TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase master drives data.
-                              0=Data driven on active to inactive clock edge,
-                              1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase master samples data.
-                              0=Data sampled on inactive to active clock edge,
-                              1=Data sampled on active to inactive clock edge""",
-                      default=0)
-
-  parser.add_argument("--vtr2_V18", action='store_true',
-                      help="Chip VTR2 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
-
-  parser.add_argument("--vtr3_V18", action='store_true',
-                      help="Chip VTR3 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
-
-  return parser.parse_args()
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
-  debug_print(".vtr2_V18 = ", args.vtr2_V18)
-  debug_print(".vtr3_V18 = ", args.vtr3_V18)
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-# MEC152x SPI Image Generator
-# No authentication
-# No payload encryption
-#
-# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
-# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
-# TAG Size = 4 bytes
-#  bits[23:0] = bits[31:8] of Header SPI offset
-#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
-#
-# MEC152X SPI header and payload layout for minimum size
-# header offset aligned on 256 byte boundary
-# header_spi_address:
-#   header[0:0x4F] = Header data
-#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
-#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
-#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
-#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
-#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
-# payload_spi_address = header_spi_address + len(Header)
-#       Payload had been padded such that len(padded_payload) % 128 == 0
-#   padded_payload[padded_payload_len]
-# payload_signature_address = payload_spi_address + len(padded_payload)
-#  payload_encryption_key_header[128] Not present if encryption disabled
-#  payload_cosignature[96] = 0 if Authentication is disabled
-#  payload_trailer[160] = SHA384(padded_payload ||
-#                                optional payload_encryption_key_header)
-#                       || 48 * [0]
-#                       || 48 * [0]
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin pack_ec_mec152x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC152X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-  #
-  assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, \
-      "Header location %d is not on a flash erase block boundary boundary" % args.header_loc
-
-  max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE
-  if args.test_spi:
-      max_image_size -= 32 # SHA256 digest
-
-  assert args.image_size > max_image_size, \
-      "Image size exceeds maximum" % args.image_size
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mchp/config_flash_layout.h
-  # defines.
-  # MEC152x Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash.
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        LOAD_ADDR, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
-
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC152X Add TAG's
-  spi_list.append((args.tag0_loc, tag0, "tag0"))
-  spi_list.append((args.tag1_loc, tag1, "tag1"))
-
-  # flashmap is non-zero only for systems with two external
-  # SPI flash chips.
-  flashmap = BuildFlashMap(0)
-  spi_list.append((8, flashmap, "flashmap"))
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list.append((args.header_loc + chip_dict["PAYLOAD_OFFSET"], lfw_ecro,
-                   "lfw_ecro"))
-
-  offset = args.header_loc + chip_dict["PAYLOAD_OFFSET"] + lfw_ecro_len
-
-  if ec_info_block != None:
-    spi_list.append((offset, ec_info_block, "EC Info Block"))
-    offset += len(ec_info_block)
-
-  if cosignature != None:
-    spi_list.append((offset, cosignature, "ECRO Cosignature"))
-    offset += len(cosignature)
-
-  if trailer != None:
-    spi_list.append((offset, trailer, "ECRO Trailer"))
-    offset += len(trailer)
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  assert rw_offset >= offset, \
-      print("""Offset of EC_RW at {0:08x} overlaps end
-               of EC_RO at {0:08x}""".format(rw_offset, offset))
-
-  spi_list.append((rw_offset, ecrw, "ecrw"))
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py
deleted file mode 100755
index 32747d3d9a..0000000000
--- a/chip/mchp/util/pack_ec_mec172x.py
+++ /dev/null
@@ -1,851 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC172x
-# Based on MEC172x_ROM_Description.pdf revision 6/8/2020
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-import zlib # CRC32
-
-# MEC172x has 416KB SRAM from 0xC0000 - 0x127FFF
-# SRAM is divided into contiguous CODE & DATA
-# CODE at [0xC0000, 0x117FFF] DATA at [0x118000, 0x127FFF]
-# Google EC SPI flash size for board is currently 512KB
-# split into 1/2.
-# EC_RO: 0 - 0x3FFFF
-# EC_RW: 0x40000 - 0x7FFFF
-#
-SPI_ERASE_BLOCK_SIZE = 0x1000
-SPI_CLOCK_LIST = [48, 24, 16, 12, 96]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
-# Maximum EC_RO/EC_RW code size is based upon SPI flash erase
-# sector size, MEC172x Boot-ROM TAG, Header, Footer.
-# SPI Offset      Description
-# 0x00 - 0x07     TAG0 and TAG1
-# 0x1000 - 0x113F Boot-ROM SPI Header
-# 0x1140 - 0x213F 4KB LFW
-# 0x2040 - 0x3EFFF
-# 0x3F000 - 0x3FFFF BootROM EC_INFO_BLK || COSIG || ENCR_KEY_HDR(optional) || TRAILER
-CHIP_MAX_CODE_SRAM_KB = (256 - 12)
-
-MEC172X_DICT = {
-                "LFW_SIZE": 0x1000,
-                "LOAD_ADDR": 0xC0000,
-                "TAG_SIZE": 4,
-                "KEY_BLOB_SIZE": 1584,
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x03,
-                "PAYLOAD_GRANULARITY":128,
-                "PAYLOAD_PAD_BYTE":b'\xff',
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def mock_print(*args, **kwargs):
-  pass
-
-debug_print = mock_print
-
-# Debug helper routine
-def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
-
-def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
-
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
-
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
-
-  return payload
-
-def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
-
-# Return 0=Slow slew rate or 1=Fast slew rate
-def GetSpiSlewRate(args):
-    if args.spi_slew_fast == True:
-        return 1
-    return 0
-
-# Return SPI CPOL = 0 or 1
-def GetSpiCpol(args):
-    if args.spi_cpol == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MOSI
-# 0 = SPI Master drives data is stable on inactive to clock edge
-# 1 = SPI Master drives data is stable on active to inactive clock edge
-def GetSpiCphaMosi(args):
-    if args.spi_cpha_mosi == 0:
-        return 0
-    return 1
-
-# Return SPI CPHA_MISO 0 or 1
-# 0 = SPI Master samples data on inactive to active clock edge
-# 1 = SPI Master samples data on active to inactive clock edge
-def GetSpiCphaMiso(args):
-    if args.spi_cpha_miso == 0:
-        return 0
-    return 1
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
-
-#
-# Build SPI image header for MEC172x
-# MEC172x image header size = 320(0x140) bytes
-#
-# Description using Python slice notation [start:start+len]
-#
-# header[0:4] = 'PHCM'
-# header[4] = header version = 0x03(MEC172x)
-# header[5] = SPI clock speed, drive strength, sampling mode
-#   bits[1:0] = SPI clock speed: 0=48, 1=24, 2=16, 3=12
-#   bits[3:2] = SPI controller pins drive strength
-#               00b=2mA, 01b=4mA, 10b=8mA, 11b=12mA
-#   bit[4] = SPI controller pins slew rate: 0=slow, 1=fast
-#   bit[5] = SPI CPOL: 0=SPI clock idle is low, 1=idle is high
-#   bit[6] = CHPHA_MOSI
-#       1:data change on first inactive to active clock edge
-#       0:data change on first active to inactive clock edge
-#   bit[7] = CHPHA_MISO:
-#       1: Data captured on first inactive to active clock edge
-#       0: Data captured on first active to inactive clock edge
-# header[6] Boot-ROM loader flags
-#   bits[0] = 0(use header[5] b[1:0]), 1(96 MHz)
-#   bits[2:1] = 0 reserved
-#   bits[5:3] = 111b
-#   bit[6]: For MEC172x controls authentication
-#           0=Authentication disabled. Signature is SHA-384 of FW payload
-#           1=Authentication enabled. Signature is ECDSA P-384
-#   bit[7]: 0=FW pyload not encrypted, 1=FW payload is encrypted
-# header[7]: SPI Flash read command
-#            0 -> 0x03 1-1-1 read freq < 33MHz
-#            1 -> 0x0B 1-1-1 + 8 clocks(data tri-stated)
-#            2 -> 0x3B 1-1-2 + 8 clocks(data tri-stated). Data phase is dual I/O
-#            3 -> 0x6B 1-1-4 + 8 clocks(data tri-stated). Data phase is Quad I/O
-#            NOTE: Quad requires SPI flash device QE(quad enable) bit
-#            to be factory set. Enabling QE disables HOLD# and WP#
-#            functionality of the SPI flash device.
-# header[0x8:0xC] SRAM Load address little-endian format
-# header[0xC:0x10] SRAM FW entry point. Boot-ROM jumps to
-#                  this address on successful load. (little-endian)
-# header[0x10:0x12] little-endian format: FW binary size in units of
-#                   128 bytes(MEC172x)
-# header[0x12:0x14] = 0 reserved
-# header[0x14:0x18] = Little-ending format: Unsigned offset from start of
-#                     header to FW payload.
-#                     MEC172x: Offset must be a multiple of 128
-#                     Offset must be >= header size.
-#                     NOTE: If Authentication is enabled size includes
-#                     the appended signature.
-# MEC172x:
-# header[0x18] = Authentication key select. Set to 0 for no Authentication.
-# header[0x19] = SPI flash device(s) drive strength feature flags
-#                 b[0]=1 SPI flash device 0 has drive strength feature
-#                 b[1]=SPI flash 0: DrvStr Write format(0=2 bytes, 1=1 byte)
-#                 b[2]=1 SPI flash device 1 has drive strength feature
-#                 b[3]=SPI flash 1: DrvStr Write format(0=2 bytes, 1=1 byte)
-#                 b[7:4] = 0 reserved
-# header[0x1A:0x20] = 0 reserved
-# header[0x20] = SPI opcode to read drive strength from SPI flash 0
-# header[0x21] = SPI opcode to write drive strength to SPI flash 0
-# header[0x22] = SPI flash 0: drvStr value
-# header[0x23] = SPI flash 0: drvStr mask
-# header[0x24] = SPI opcode to read drive strength from SPI flash 1
-# header[0x25] = SPI opcode to write drive strength to SPI flash 1
-# header[0x26] = SPI flash 1: drvStr value
-# header[0x27] = SPI flash 1: drvStr mask
-# header[0x28:0x48] = reserved, may be any value
-# header[0x48:0x50] = reserved for customer use
-# header[0x50:0x80] = ECDSA-384 public key x-coord. = 0 Auth. disabled
-# header[0x80:0xB0] = ECDSA-384 public key y-coord. = 0 Auth. disabled
-# header[0xB0:0xE0] = SHA-384 digest of header[0:0xB0]
-# header[0xE0:0x110] = Header ECDSA-384 signature x-coord. = 0 Auth. disabled
-# header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
-#
-def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = chip_dict["HEADER_SIZE"]
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = chip_dict["HEADER_VER"]
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqIndex = GetSpiClockParameter(args)
-  if spiFreqIndex > 3:
-    header[6] |= 0x01
-  else:
-    header[5] = spiFreqIndex
-
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # header[6]
-  # b[0] value set above
-  # b[2:1] = 00b, b[5:3]=111b
-  # b[7]=0 No encryption of FW payload
-  header[6] |= 0x7 << 3
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-  assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, \
-         print("Payload size not a multiple of {0}".format(chip_dict["PAYLOAD_GRANULARITY"]))
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be
-  # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO).
-  # LFW location provided on the command line.
-  assert (args.lfw_loc % 4096 == 0), \
-         print("LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc))
-
-  assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), \
-         print("LFW location not greater than header location + header size")
-
-  lfw_ofs = args.lfw_loc - args.header_loc
-  header[0x14:0x18] = lfw_ofs.to_bytes(4, 'little')
-
-  # MEC172x: authentication key select. Authentication not used, set to 0.
-  header[0x18] = 0
-
-  # header[0x19], header[0x20:0x28]
-  # header[0x1A:0x20] reserved 0
-  # MEC172x: supports SPI flash devices with drive strength settings
-  # TODO leave these fields at 0 for now. We must add 6 command line
-  # arguments.
-
-  # header[0x28:0x48] reserve can be any value
-  # header[0x48:0x50] Customer use. TODO
-  # authentication disabled, leave these 0.
-  # header[0x50:0x80] ECDSA P384 Authentication Public key Rx
-  # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
-
-#
-# MEC172x 128-byte EC Info Block appended to end of padded FW binary.
-# Python slice notation
-# byte[0:0x64] are undefined, we set to 0xFF
-# byte[0x64] = FW Build LSB
-# byte[0x65] = FW Build MSB
-# byte[0x66:0x68] = undefined, set to 0xFF
-# byte[0x68:0x78] = Roll back permissions bit maps
-# byte[0x78:0x7c] = key revocation bit maps
-# byte[0x7c] = platform ID LSB
-# byte[0x7d] = platform ID MSB
-# byte[0x7e] = auto-rollback protection enable
-# byte[0x7f] = current imeage revision
-#
-def GenEcInfoBlock(args, chip_dict):
-  # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"])
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
-
-#
-# Generate SPI FW image co-signature.
-# MEC172x cosignature is 96 bytes used by OEM FW
-# developer to sign their binary with ECDSA-P384-SHA384 or
-# some other signature algorithm that fits in 96 bytes.
-# At this time Cros-EC is not using this field, fill with 0xFF.
-# If this feature is implemented we need to read the OEM's
-# generated signature from a file and extract the binary
-# signature.
-#
-def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
-
-#
-# Generate SPI FW Image trailer.
-# MEC172x: Size = 160 bytes
-#   binary = payload || encryption_key_header || ec_info_block || cosignature
-#   trailer[0:48] = SHA384(binary)
-#   trailer[48:144] = 0xFF
-#   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
-#       Authentication & encryption are not used therefore random data
-#       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
-    debug_print("GenTrailer SHA384 computation")
-    trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
-    hasher = hashlib.sha384()
-    hasher.update(payload)
-    debug_print("  Update: payload len=0x{0:0x}".format(len(payload)))
-    if ec_info_block != None:
-      hasher.update(ec_info_block)
-      debug_print("  Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block)))
-    if encryption_key_header != None:
-      hasher.update(encryption_key_header)
-      debug_print("  Update: encryption_key_header len=0x{0:0x}".format(len(encryption_key_header)))
-    if cosignature != None:
-      hasher.update(cosignature)
-      debug_print("  Update: cosignature len=0x{0:0x}".format(len(cosignature)))
-    trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
-
-    return trailer
-
-# MEC172x supports two 32-bit Tags located at offsets 0x0 and 0x4
-# in the SPI flash.
-# Tag format:
-#   bits[23:0] correspond to bits[31:8] of the Header SPI address
-#       Header is always on a 256-byte boundary.
-#   bits[31:24] = CRC8-ITU of bits[23:0].
-# Notice there is no chip-select field in the Tag both Tag's point
-# to the same flash part.
-#
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
-
-def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
-    tag.append(Crc8(0, tag))
-    return tag
-
-
-# FlashMap is an option for MEC172x
-# It is a 32 bit structure
-# bits[18:0] = bits[30:12] of second SPI flash base address
-# bits[23:19] = 0 reserved
-# bits[31:24] = CRC8 of bits[23:0]
-# Input:
-#   integer containing base address of second SPI flash
-#   This value is usually equal to the size of the first
-#   SPI flash and should be a multiple of 4KB
-# Output:
-#   bytearray of length 4
-def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
-
-#
-# Creates temporary file for read/write
-# Reads binary file containing LFW image_size (loader_file)
-# Writes LFW image to temporary file
-# Reads RO image at beginning of rorw_file up to image_size
-#  (assumes RO/RW images have been padded with 0xFF
-# Returns temporary file name
-#
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
-
-#
-# Generate a test EC_RW image of same size
-# as original.
-# Preserve image_data structure and fill all
-# other bytes with 0xA5.
-# useful for testing SPI read and EC build
-# process hash generation.
-#
-def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
-
-def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("--load_addr", type=int,
-                      help="EC SRAM load address",
-                      default=0xC0000)
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash. Must be on a 256 byte boundary",
-                      default=0x0100)
-  parser.add_argument("--lfw_loc", type=int,
-                      help="Location of LFW in SPI flash. Must be on a 4KB boundary",
-                      default=0x1000)
-  parser.add_argument("--lfw_size", type=int,
-                      help="LFW size in bytes",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 244KB",
-                      default=(244 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC172x TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC172x TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase controller drives data.
-                              0=Data driven on active to inactive clock edge,
-                              1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase controller samples data.
-                              0=Data sampled on inactive to active clock edge,
-                              1=Data sampled on active to inactive clock edge""",
-                      default=0)
-
-  return parser.parse_args()
-
-def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".load_addr", hex(args.load_addr))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".lfw_loc = ", hex(args.lfw_loc))
-  debug_print(".lfw_size = ", hex(args.lfw_size))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
-
-def spi_list_append(mylist, loc, data, description):
-  """Append SPI data block tuple to list"""
-  t = (loc, data, description)
-  mylist.append(t)
-  debug_print("Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(loc, len(data), description))
-
-#
-# Handle quiet mode build from Makefile
-# Quiet mode when V is unset or V=0
-# Verbose mode when V=1
-#
-# MEC172x SPI Image Generator
-# No authentication
-# No payload encryption
-#
-# SPI Offset 0x0 = TAG0 points to Header for EC-RO FW
-# SPI Offset 0x4 = TAG1 points to Header for EC-RO FW
-# TAG Size = 4 bytes
-#  bits[23:0] = bits[31:8] of Header SPI offset
-#  bits[31:24] = CRC8-ITU checksum of bits[23:0].
-#
-# MEC172x SPI header and payload layout for minimum size
-# header offset aligned on 256 byte boundary
-# header_spi_address:
-#   header[0:0x4F] = Header data
-#   header[0x50:0x80] = ECDSA-P384 public key x for Header authentication
-#   header[0x80:0xB0] = ECDSA-P384 public key y for Header authentication
-#   header[0xB0:0xE0] = SHA384 digest of header[0:0xB0]
-#   header[0xE0:0x110] = ECDSA-P384-SHA384 Signature.R of header[0:0xB0]
-#   header[0x110:0x140] = ECDSA-P384-SHA384 Signature.S of header[0:0xB0]
-# payload_spi_address = header_spi_address + len(Header)
-#       Payload had been padded such that len(padded_payload) % 128 == 0
-#   padded_payload[padded_payload_len]
-# payload_signature_address = payload_spi_address + len(padded_payload)
-#  payload_encryption_key_header[128] Not present if encryption disabled
-#  payload_cosignature[96] = 0 if Authentication is disabled
-#  payload_trailer[160] = SHA384(padded_payload ||
-#                                optional payload_encryption_key_header)
-#                       || 48 * [0]
-#                       || 48 * [0]
-#
-def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin pack_ec_mec172x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC172X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-
-  spi_size = args.spi_size * 1024
-  spi_image_size = spi_size // 2
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-  debug_print("LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry))
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        args.load_addr, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
-
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list = []
-
-  # MEC172x Add TAG's
-  #spi_list.append((args.tag0_loc, tag0, "tag0"))
-  #spi_list.append((args.tag1_loc, tag1, "tag1"))
-  spi_list_append(spi_list, args.tag0_loc, tag0, "TAG0")
-  spi_list_append(spi_list, args.tag1_loc, tag1, "TAG1")
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  #spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list_append(spi_list, args.header_loc, header, "LFW-EC_RO Header")
-
-  spi_list_append(spi_list, args.lfw_loc, lfw_ecro, "LFW-EC_RO FW")
-
-  offset = args.lfw_loc + len(lfw_ecro)
-  debug_print("SPI offset after LFW_ECRO = 0x{0:08x}".format(offset))
-
-  if ec_info_block != None:
-    spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block")
-    offset += len(ec_info_block)
-
-  debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset))
-
-  if cosignature != None:
-    #spi_list.append((offset, co-signature, "ECRO Co-signature"))
-    spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature")
-    offset += len(cosignature)
-
-  debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset))
-
-  if trailer != None:
-    #spi_list.append((offset, trailer, "ECRO Trailer"))
-    spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer")
-    offset += len(trailer)
-
-  debug_print("SPI offset after trailer = 0x{0:08x}".format(offset))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  #spi_list.append((rw_offset, ecrw, "ecrw"))
-  spi_list_append(spi_list, rw_offset, ecrw, "EC_RW")
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  debug_print("Display spi_list:")
-  dumpsects(spi_list)
-
-  #
-  # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c
deleted file mode 100644
index b8f986f5cd..0000000000
--- a/chip/mchp/watchdog.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-#include "tfdp_chip.h"
-
-void watchdog_reload(void)
-{
-	MCHP_WDG_KICK = 1;
-
-	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
-		/* Reload the auxiliary timer */
-		MCHP_TMR16_CTL(0) &= ~BIT(5);
-		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-		MCHP_TMR16_CTL(0) |= BIT(5);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
-static void wdg_intr_enable(int enable)
-{
-	if (enable) {
-		MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
-		MCHP_WDG_IEN = MCHP_WDG_IEN_IRQ_EN;
-		MCHP_WDG_CTL |= MCHP_WDG_RESET_IRQ_EN;
-		MCHP_INT_ENABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-		task_enable_irq(MCHP_IRQ_WDG);
-	} else {
-		MCHP_WDG_IEN = 0U;
-		MCHP_WDG_CTL &= ~(MCHP_WDG_RESET_IRQ_EN);
-		MCHP_INT_DISABLE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-		task_disable_irq(MCHP_IRQ_WDG);
-	}
-}
-#else
-static void wdg_intr_enable(int enable)
-{
-	(void) enable;
-}
-#endif
-
-
-/*
- * MEC1701 WDG asserts chip reset on LOAD count expiration.
- * WDG interrupt is simulated using a 16-bit general purpose
- * timer whose period is sufficiently less that the WDG timeout
- * period allowing watchdog trace data to be saved.
- *
- * MEC152x adds interrupt capability to the WDT.
- * Enable MEC152x WDG interrupt. WDG event will assert
- * IRQ and kick itself starting another LOAD timeout.
- * After the new LOAD expires WDG will assert chip reset.
- * The WDG ISR calls watchdog trace save API, upon return we
- * enter a spin loop waiting for the LOAD period to expire.
- * WDG does not have a way to trigger an immediate reset except
- * by re-programming it.
- */
-int watchdog_init(void)
-{
-	if (IS_ENABLED(CONFIG_WATCHDOG_HELP)) {
-		/*
-		 * MEC170x Watchdog does not warn us before expiring.
-		 * Let's use a 16-bit timer as an auxiliary timer.
-		 */
-
-		/* Clear 16-bit basic timer 0 PCR sleep enable */
-		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0);
-
-		/* Stop the auxiliary timer if it's running */
-		MCHP_TMR16_CTL(0) &= ~BIT(5);
-
-		/* Enable auxiliary timer */
-		MCHP_TMR16_CTL(0) |= BIT(0);
-
-		/* Prescaler = 48000 -> 1kHz -> Period = 1 ms */
-		MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU)
-					| (47999 << 16);
-
-		/* No auto restart */
-		MCHP_TMR16_CTL(0) &= ~BIT(3);
-
-		/* Count down */
-		MCHP_TMR16_CTL(0) &= ~BIT(2);
-
-		/* Enable interrupt from auxiliary timer */
-		MCHP_TMR16_IEN(0) |= BIT(0);
-		task_enable_irq(MCHP_IRQ_TIMER16_0);
-		MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
-
-		/* Load and start the auxiliary timer */
-		MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-		MCHP_TMR16_CNT(0) |= BIT(5);
-	}
-
-	MCHP_WDG_CTL = 0;
-
-	/* Clear WDT PCR sleep enable */
-	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_WDT);
-
-	/* Set timeout. It takes 1007 us to decrement WDG_CNT by 1. */
-	MCHP_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
-
-	wdg_intr_enable(1);
-
-	/*
-	 * Start watchdog
-	 * If chipset debug build enable feature to prevent watchdog from
-	 * counting if a debug cable is attached to JTAG_RST#.
-	 */
-	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG))
-		MCHP_WDG_CTL |= (MCHP_WDT_CTL_ENABLE
-			| MCHP_WDT_CTL_JTAG_STALL_EN);
-	else
-		MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
-
-	return EC_SUCCESS;
-}
-
-/* MEC152x Watchdog can fire an interrupt to CPU before system reset */
-#if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X)
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear WDG first then aggregator */
-	MCHP_WDG_STATUS = MCHP_WDG_STS_IRQ;
-	MCHP_INT_SOURCE(MCHP_WDG_GIRQ) = MCHP_WDG_GIRQ_BIT;
-
-	/* Cause WDG to reload again. */
-	MCHP_WDG_KICK = 1;
-
-	watchdog_trace(excep_lr, excep_sp);
-
-	/* Reset system by re-programing WDT to trigger after 2 32KHz clocks */
-	MCHP_WDG_CTL = 0; /* clear enable to allow write to load register */
-	MCHP_WDG_LOAD = 2;
-	MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
-
-}
-
-/* ISR for watchdog warning naked will keep SP & LR */
-void
-IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked));
-void IRQ_HANDLER(MCHP_IRQ_WDG)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/*
-			 * Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveniently saves
-			 * R0=LR so we can pass it to task_resched_if_needed.
-			 */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
-}
-
-/* put the watchdog at the highest priority */
-const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_WDG)
-__attribute__((section(".rodata.irqprio")))
-= {MCHP_IRQ_WDG, 0};
-
-#else
-/*
- * MEC1701 watchdog only resets. Use a 16-bit timer to fire in interrupt
- * for saving watchdog trace.
- */
-#ifdef CONFIG_WATCHDOG_HELP
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear status */
-	MCHP_TMR16_STS(0) |= 1;
-	/* clear aggregator status */
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void
-IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
-void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /*
-		      * Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed.
-		      */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n");
-}
-
-/* Put the watchdog at the highest interrupt priority. */
-const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MCHP_IRQ_TIMER16_0, 0};
-
-#endif /* #ifdef CONFIG_WATCHDOG_HELP */
-#endif /* #if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X) */
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c
deleted file mode 100644
index 95fe99f891..0000000000
--- a/chip/mec1322/adc.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * Conversion on a single channel takes less than 12 ms. Set timeout to
- * 15 ms so that we have a 3-ms margin.
- */
-#define ADC_SINGLE_READ_TIME 15000
-
-struct mutex adc_lock;
-
-static volatile task_id_t task_waiting;
-
-static int start_single_and_wait(int timeout)
-{
-	int event;
-
-	task_waiting = task_get_current();
-
-	/* Start conversion */
-	MEC1322_ADC_CTRL |= BIT(1);
-
-	/* Wait for interrupt */
-	event = task_wait_event(timeout);
-	task_waiting = TASK_ID_INVALID;
-	return event != TASK_EVENT_TIMER;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-
-	mutex_lock(&adc_lock);
-
-	MEC1322_ADC_SINGLE = 1 << adc->channel;
-
-	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
-		value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul /
-			adc->factor_div + adc->shift;
-	else
-		value = ADC_READ_ERROR;
-
-	mutex_unlock(&adc_lock);
-	return value;
-}
-
-static void adc_init(void)
-{
-	/* Activate ADC module */
-	MEC1322_ADC_CTRL |= BIT(0);
-
-	/* Enable interrupt */
-	task_waiting = TASK_ID_INVALID;
-	MEC1322_INT_ENABLE(17) |= BIT(10);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	task_enable_irq(MEC1322_IRQ_ADC_SNGL);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
-
-void adc_interrupt(void)
-{
-	/* Clear interrupt status bit */
-	MEC1322_ADC_CTRL |= BIT(7);
-
-	if (task_waiting != TASK_ID_INVALID)
-		task_wake(task_waiting);
-}
-DECLARE_IRQ(MEC1322_IRQ_ADC_SNGL, adc_interrupt, 2);
diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h
deleted file mode 100644
index a6425d6872..0000000000
--- a/chip/mec1322/adc_chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-};
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-
-/* Just plain id mapping for code readability */
-#define MEC1322_ADC_CH(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
deleted file mode 100644
index 2b0c9cc229..0000000000
--- a/chip/mec1322/build.mk
+++ /dev/null
@@ -1,79 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# MEC1322 chip specific files build
-#
-
-# MEC1322 SoC has a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-ifeq ($(CONFIG_LTO),y)
-# Re-include the core's build.mk file so we can remove the lto flag.
-include core/$(CORE)/build.mk
-endif
-
-# Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_SPI)+=spi.o
-
-# location of the scripts and keys used to pack the SPI flash image
-SCRIPTDIR:=./chip/${CHIP}/util
-
-# Allow SPI size to be overridden by board specific size, default to 256KB.
-CHIP_SPI_SIZE_KB?=256
-
-# Commands to convert $^ to $@.tmp
-cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \
-		 ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \
-		--loader_file $(mec1322-lfw-flat) \
-		--payload_key ${SCRIPTDIR}/rsakey_sign_payload.pem \
-		--header_key ${SCRIPTDIR}/rsakey_sign_header.pem \
-		--spi_size ${CHIP_SPI_SIZE_KB} \
-		--image_size $(_rw_size); rm -f $@.tmp1
-
-mec1322-lfw = chip/mec1322/lfw/ec_lfw
-mec1322-lfw-flat = $(out)/RW/$(mec1322-lfw)-lfw.flat
-
-# build these specifically for lfw with -lfw suffix
-objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util gpio) \
-		$(addprefix chip/$(CHIP)/, spi dma gpio clock hwtimer) \
-		core/$(CORE)/cpu $(mec1322-lfw))
-
-# reuse version.o (and its dependencies) from main board
-objs_lfw += $(out)/RW/common/version.o
-
-dirs-y+=chip/$(CHIP)/lfw
-
-# objs with -lfw suffix are to include lfw's gpio
-$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY)
-# Remove the lto flag for the loader.  It actually causes it to bloat in size.
-ifeq ($(CONFIG_LTO),y)
-$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU))
-endif
-$(out)/RW/%-lfw.o: %.c
-	$(call quiet,c_to_o,CC     )
-
-# let lfw's elf link only with selected objects
-$(out)/RW/%-lfw.elf: private objs = $(objs_lfw)
-$(out)/RW/%-lfw.elf: override shlib :=
-$(out)/RW/%-lfw.elf: %.ld $(objs_lfw)
-	$(call quiet,elf,LD     )
-
-# final image needs lfw loader
-$(out)/$(PROJECT).bin: $(mec1322-lfw-flat)
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c
deleted file mode 100644
index ce07284891..0000000000
--- a/chip/mec1322/clock.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "vboot_hash.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Recovery time for HvySlp2 is 0 usec */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
-
-#define SET_HTIMER_DELAY_USEC           200
-
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t total_idle_dsleep_time_us;
-
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the heavy sleep mode is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 60;
-static timestamp_t console_expire_time;
-#endif /*CONFIG_LOW_POWER_IDLE */
-
-static int freq = 48000000;
-
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-void clock_init(void)
-{
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* XOSEL: 0 = Parallel resonant crystal */
-	MEC1322_VBAT_CE &= ~0x1;
-#else
-	/* XOSEL: 1 = Single ended clock source */
-	MEC1322_VBAT_CE |= 0x1;
-#endif
-
-	/* 32K clock enable */
-	MEC1322_VBAT_CE |= 0x2;
-
-#ifdef CONFIG_CLOCK_CRYSTAL
-	/* Wait for crystal to stabilize (OSC_LOCK == 1) */
-	while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100))
-		;
-#endif
-}
-
-/**
- * Speed through boot + vboot hash calculation, dropping our processor clock
- * only after vboot hashing is completed.
- */
-static void clock_turbo_disable(void);
-DECLARE_DEFERRED(clock_turbo_disable);
-
-static void clock_turbo_disable(void)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress())
-		hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC);
-	else
-#endif
-		/* Use 12 MHz processor clock for power savings */
-		MEC1322_PCR_PROC_CLK_CTL = 4;
-}
-DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * initialization of Hibernation timer
- */
-static void htimer_init(void)
-{
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_INT_ENABLE(17) |= BIT(20);  /* GIRQ=17, aggregator bit = 20 */
-	MEC1322_HTIMER_PRELOAD = 0;  /* disable at beginning */
-
-	task_enable_irq(MEC1322_IRQ_HTIMER);
-}
-
-/**
- * Use hibernate module to set up an htimer interrupt at a given
- * time from now
- *
- * @param seconds      Number of seconds before htimer interrupt
- * @param microseconds Number of microseconds before htimer interrupt
- */
-static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	if (seconds || microseconds) {
-
-		if (seconds > 2) {
-			/* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */
-			/* (number of counts to be loaded)
-			 * = seconds * ( 8 clocks per second )
-			 *   + microseconds / 125000
-			 *   ---> (0 if (microseconds < 125000)
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-
-		} else { /* count up to 2 sec. */
-
-			MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */
-
-			/* (number of counts to be loaded)
-			 * = (total microseconds) / 30.5;
-			 */
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 61;
-		}
-	}
-}
-
-/**
- * return time slept in micro-seconds
- */
-static timestamp_t system_get_htimer(void)
-{
-	uint16_t count;
-	timestamp_t time;
-
-	count =  MEC1322_HTIMER_COUNT;
-
-
-	if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */
-		/* 0.125 sec per count */
-		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
-		/* 30.5(=61/2)usec per count */
-		time.le.lo = (uint32_t)(count * 61 / 2);
-
-	time.le.hi = 0;
-
-	return time;  /* in uSec */
-}
-
-/**
- * Disable and clear hibernation timer interrupt
- */
-static void system_reset_htimer_alarm(void)
-{
-	MEC1322_HTIMER_PRELOAD = 0;
-}
-
-/**
- * This is mec1322 specific and equivalent to ARM Cortex's
- * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL
- */
-static void prepare_for_deep_sleep(void)
-{
-	uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN |
-			     MEC1322_PCR_EC_SLP_EN_SLEEP;
-
-	/* sysTick timer */
-	CPU_NVIC_ST_CTRL &= ~ST_ENABLE;
-	CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-	/* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-#ifdef CONFIG_PWM
-	if (pwm_get_keep_awake_mask())
-		ec_slp_en &= ~pwm_get_keep_awake_mask();
-	else
-#endif
-		/* Disable 100 Khz clock */
-		MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00;
-
-	MEC1322_PCR_EC_SLP_EN = ec_slp_en;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-
-#ifndef CONFIG_POWER_S0IX
-	MEC1322_LPC_ACT = 0x0;
-#endif
-
-	MEC1322_PCR_SYS_SLP_CTL = 0x2;  /* heavysleep 2 */
-
-	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
-}
-
-static void resume_from_deep_sleep(void)
-{
-	CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */
-	CPU_NVIC_ST_CTRL |= ST_ENABLE;
-
-	MEC1322_EC_JTAG_EN = 1;
-	MEC1322_EC_ADC_VREF_PD &= ~1;
-	/* ADC_VREF_PD overrides ADC_CTRL ! */
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= 1;
-	MEC1322_TMR32_CTL(1) |= 1;
-	MEC1322_TMR16_CTL(0) |= 1;
-
-	/* Enable watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0;
-	MEC1322_PCR_CHIP_SLP_EN &= ~0x3;
-	MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE;
-	MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
-	MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
-
-	MEC1322_PCR_SYS_SLP_CTL = 0xF8;  /* default */
-
-#ifndef CONFIG_POWER_S0IX
-	/* Enable LPC */
-	MEC1322_LPC_ACT |= 1;
-#endif
-}
-
-
-void clock_refresh_console_in_use(void)
-{
-	disable_sleep(SLEEP_MASK_CONSOLE);
-
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-}
-
-/**
- * Low power idle task.  Executed when no tasks are ready to be scheduled.
- */
-void __idle(void)
-{
-	timestamp_t t0;
-	timestamp_t t1;
-	timestamp_t ht_t1;
-	uint32_t next_delay;
-	uint32_t max_sleep_time;
-	int time_for_dsleep;
-	int uart_ready_for_deepsleep;
-
-	htimer_init(); /* hibernation timer initialize */
-
-	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	CPRINTS("low power idle task started");
-
-	while (1) {
-		/* Disable interrupts */
-		interrupt_disable();
-
-		t0 = get_time();  /* uSec */
-
-		/* __hw_clock_event_get() is next programmed timer event */
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
-						SET_HTIMER_DELAY_USEC);
-
-		max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
-
-		/* check if there enough time for deep sleep */
-		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-
-
-			/*
-			 * Check if the console use has expired and console
-			 * sleep is masked by GPIO(UART-RX) interrupt.
-			 */
-			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
-				/* allow console to sleep. */
-				enable_sleep(SLEEP_MASK_CONSOLE);
-
-				/*
-				 * Wait one clock before checking if heavy sleep
-				 * is allowed to give time for sleep mask
-				 * to be updated.
-				 */
-				clock_wait_cycles(1);
-
-				if (LOW_SPEED_DEEP_SLEEP_ALLOWED)
-					CPRINTS("Disable console in deepsleep");
-			}
-
-
-			/* UART is not being used  */
-			uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED
-						&& !uart_tx_in_progress()
-						&& uart_buffer_empty();
-
-			/*
-			 * Since MEC1322's heavysleep modes requires all block
-			 * to be sleepable, UART/console's readiness is final
-			 * decision factor of heavysleep of EC.
-			 */
-			if (uart_ready_for_deepsleep) {
-
-				idle_dsleep_cnt++;
-
-				/*
-				 * config UART Rx as GPIO wakeup interrupt
-				 * source
-				 */
-				uart_enter_dsleep();
-
-				/* MEC1322 specific deep-sleep mode */
-				prepare_for_deep_sleep();
-
-				/*
-				 * 'max_sleep_time' value should be big
-				 * enough so that hibernation timer's interrupt
-				 * triggers only after 'wfi' completes its
-				 * excution.
-				 */
-				max_sleep_time -= (get_time().le.lo - t0.le.lo);
-
-				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0, max_sleep_time);
-			} else {
-				idle_sleep_cnt++;
-			}
-
-			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
-
-			if (uart_ready_for_deepsleep) {
-
-				resume_from_deep_sleep();
-
-				/*
-				 * Fast forward timer according to htimer
-				 * counter:
-				 * Since all blocks including timers will be in
-				 * sleep mode, timers stops except hibernate
-				 * timer.
-				 * And system schedule timer should be corrected
-				 * after wakeup by either hibernate timer or
-				 * GPIO_UART_RX interrupt.
-				 */
-				ht_t1 = system_get_htimer();
-
-				/* disable/clear htimer wakeup interrupt */
-				system_reset_htimer_alarm();
-
-				t1.val = t0.val +
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-
-				force_time(t1);
-
-				/* re-eanble UART */
-				uart_exit_dsleep();
-
-				/* Record time spent in deep sleep. */
-				total_idle_dsleep_time_us +=
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
-			}
-
-		} else { /* CPU 'Sleep' mode */
-
-			idle_sleep_cnt++;
-
-			asm("wfi");
-
-		}
-
-		interrupt_enable();
-	} /* while(1) */
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-
-	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-						total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* defined(CONFIG_CMD_IDLE_STATS) */
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use heavy sleep mode or
-			 * allow it to use the heavy sleep mode.
-			 */
-			if (v)  /* 'on' */
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
-			"Deep sleep clock settings:\nUse 'on' to force deep "
-			"sleep NOT to enter heavysleep mode.\nUse 'off' to "
-			"allow deep sleep to use heavysleep whenever conditions"
-			"allow.\n"
-			"Give a timeout value for the console in use timeout.\n"
-			"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
deleted file mode 100644
index 414fb492bf..0000000000
--- a/chip/mec1322/config_chip.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	93
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-/****************************************************************************/
-/* Memory mapping */
-
-/*
- * The memory region for RAM is actually 0x00100000-0x00120000.
- * RAM for RO/RW = 20k
- * CODE size of the Loader is 3k
- * As per the above configuartion the upper 20k
- * is used to store data.The rest is for code.
- * the lower 107K is flash[ 3k Loader and 104k RO/RW],
- * and the higher 20K is RAM shared by loader and RO/RW.
- */
-
-/****************************************************************************/
-/* Define our RAM layout. */
-
-#define CONFIG_MEC_SRAM_BASE_START	0x00100000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
-
-/* 20k RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00005000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE		1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		512
-#define LARGER_TASK_STACK_SIZE		640
-
-#define CHARGER_TASK_STACK_SIZE		640
-#define HOOKS_TASK_STACK_SIZE		640
-#define CONSOLE_TASK_STACK_SIZE		640
-#define HOST_CMD_TASK_STACK_SIZE	640
-
-/*
- * TODO: Large stack consumption
- * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
- */
-#define PD_TASK_STACK_SIZE		800
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			512
-
-/****************************************************************************/
-/* Define our flash layout. */
-
-/* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
-/* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
-
-/* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
-
-/* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-
-#include "config_flash_layout.h"
-
-/****************************************************************************/
-/* Customize the build */
-/* Optional features present on this chip */
-#if 0
-#define CONFIG_ADC
-#define CONFIG_PECI
-#define CONFIG_MPU
-#endif
-#define CONFIG_DMA
-#define CONFIG_HOSTCMD_LPC
-#define CONFIG_SPI
-#define CONFIG_SWITCH
-
-#define GPIO_PIN(index) (index / 10), (1 << (index % 10))
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
deleted file mode 100644
index a5b064b8cc..0000000000
--- a/chip/mec1322/config_flash_layout.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * mec1322 flash layout:
- * - Non memory-mapped, external SPI.
- * - RW image at the beginning of writable region.
- * - Bootloader at the beginning of protected region, followed by RO image.
- * - Loader + (RO | RW) loaded into program memory.
- */
-
-/* Non-memmapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
-#define CONFIG_SPI_FLASH
-
-/* EC region of SPI resides at end of ROM, protected region follows writable */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE_BYTES - 0x20000)
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE_BYTES - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-
-/* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
-/* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-/*
- * Write protect 128k section of 256k physical flash which contains loader
- * and RO Images.
- */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * RO / RW images follow the loader in program memory. Either RO or RW
- * image will be loaded -- both cannot be loaded at the same time.
- */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-
-/* WP region consists of second half of SPI, and begins with the boot header */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
-
-/* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
-
-/* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
-
-/* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c
deleted file mode 100644
index a6c6fed5ad..0000000000
--- a/chip/mec1322/dma.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-
-	return &dma->chan[channel];
-}
-
-void dma_disable(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	if (chan->act == 1)
-		chan->act = 0;
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-	mec1322_dma_regs_t *dma;
-
-	for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) {
-		mec1322_dma_chan_t *chan = dma_get_channel(ch);
-		/* Abort any current transfer. */
-		chan->ctrl |= BIT(25);
-		/* Disable the channel. */
-		chan->ctrl &= ~BIT(0);
-		chan->act = 0;
-	}
-
-	/* Soft-reset the block. */
-	dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x2;
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan		Channel to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register, normally:
- *				MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV for tx
- *				MEC1322_DMA_INC_MEM for rx
- */
-static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count,
-		void *periph, void *memory, unsigned flags)
-{
-	int xfer_size = (flags >> 20) & 0x7;
-
-	if (chan->ctrl & BIT(0))
-		chan->ctrl &= ~BIT(0);
-
-	chan->act |= 0x1;
-	chan->dev = (uint32_t)periph;
-	chan->mem_start = MEC1322_RAM_ALIAS((uint32_t)memory);
-	chan->mem_end = MEC1322_RAM_ALIAS((uint32_t)memory) + xfer_size * count;
-	chan->ctrl = flags;
-}
-
-void dma_go(mec1322_dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	chan->ctrl |= MEC1322_DMA_RUN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(option->channel);
-
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the channel for transmit.
-	 */
-	prepare_channel(chan, count, option->periph, (void *)memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV |
-			MEC1322_DMA_DEV(option->channel) | option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	mec1322_dma_chan_t *chan;
-
-	chan = dma_get_channel(option->channel);
-
-	prepare_channel(chan, count, option->periph, memory,
-			MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) |
-			option->flags);
-	dma_go(chan);
-}
-
-int dma_bytes_done(mec1322_dma_chan_t *chan, int orig_count)
-{
-	int xfer_size = (chan->ctrl >> 20) & 0x7;
-
-	return orig_count - (chan->mem_end - chan->mem_start) / xfer_size;
-}
-
-bool dma_is_enabled(mec1322_dma_chan_t *chan)
-{
-	return (chan->ctrl & MEC1322_DMA_RUN);
-}
-
-void dma_init(void)
-{
-	mec1322_dma_regs_t *dma = MEC1322_DMA_REGS;
-	dma->ctrl |= 0x1;
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-	timestamp_t deadline;
-
-	if (chan->act == 0)
-		return EC_SUCCESS;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while (!(chan->int_status & 0x4)) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-void dma_clear_isr(enum dma_channel channel)
-{
-	mec1322_dma_chan_t *chan = dma_get_channel(channel);
-
-	chan->int_status |= 0x4;
-}
diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c
deleted file mode 100644
index 1f54389fc7..0000000000
--- a/chip/mec1322/fan.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322 fan control module. */
-
-/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */
-
-#include "fan.h"
-#include "registers.h"
-#include "util.h"
-
-/* Maximum tach reading/target value */
-#define MAX_TACH 0x1fff
-
-/* Tach target value for disable fan */
-#define FAN_OFF_TACH 0xfff8
-
-/*
- * RPM = (n - 1) * m * f * 60 / poles / TACH
- *   n = number of edges = 5
- *   m = multiplier defined by RANGE = 2 in our case
- *   f = 32.768K
- *   poles = 2
- */
-#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH)
-#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1))
-
-static int rpm_setting;
-static int duty_setting;
-static int in_rpm_mode = 1;
-
-
-static void clear_status(void)
-{
-	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
-	MEC1322_FAN_STATUS = 0x23;
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	if (in_rpm_mode) {
-		if (enabled)
-			fan_set_rpm_target(ch, rpm_setting);
-		else
-			MEC1322_FAN_TARGET = FAN_OFF_TACH;
-	} else {
-		if (enabled)
-			fan_set_duty(ch, duty_setting);
-		else
-			MEC1322_FAN_SETTING = 0;
-	}
-	clear_status();
-}
-
-int fan_get_enabled(int ch)
-{
-	if (in_rpm_mode)
-		return (MEC1322_FAN_TARGET & 0xff00) != 0xff00;
-	else
-		return !!MEC1322_FAN_SETTING;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	duty_setting = percent;
-	MEC1322_FAN_SETTING = percent * 255 / 100;
-	clear_status();
-}
-
-int fan_get_duty(int ch)
-{
-	return duty_setting;
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return !!(MEC1322_FAN_CFG1 & BIT(7));
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		MEC1322_FAN_CFG1 |= BIT(7);
-	else
-		MEC1322_FAN_CFG1 &= ~BIT(7);
-	clear_status();
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	if ((MEC1322_FAN_READING >> 8) == 0xff)
-		return 0;
-	else
-		return TACH_TO_RPM(MEC1322_FAN_READING >> 3);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return rpm_setting;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	rpm_setting = rpm;
-	MEC1322_FAN_TARGET = RPM_TO_TACH(rpm) << 3;
-	clear_status();
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-
-	if (sts & (BIT(5) | BIT(1)))
-		return FAN_STATUS_FRUSTRATED;
-	if (fan_get_rpm_actual(ch) == 0)
-		return FAN_STATUS_STOPPED;
-	return FAN_STATUS_LOCKED;
-}
-
-int fan_is_stalled(int ch)
-{
-	uint8_t sts = MEC1322_FAN_STATUS;
-	if (fan_get_rpm_actual(ch)) {
-		MEC1322_FAN_STATUS = 0x1;
-		return 0;
-	}
-	return sts & 0x1;
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	/*
-	 * Fan configuration 1 register:
-	 *   0x80 = bit 7    = RPM mode (0x00 if FAN_USE_RPM_MODE not set)
-	 *   0x20 = bits 6:5 = min 1000 RPM, multiplier = 2
-	 *   0x08 = bits 4:3 = 5 edges, 2 poles
-	 *   0x03 = bits 2:0 = 400 ms update time
-	 *
-	 * Fan configuration 2 register:
-	 *   0x00 = bit 6    = Ramp control disabled
-	 *   0x00 = bit 5    = Glitch filter enabled
-	 *   0x18 = bits 4:3 = Using both derivative options
-	 *   0x02 = bits 2:1 = error range is 50 RPM
-	 *   0x00 = bits 0   = normal polarity
-	 */
-	if (flags & FAN_USE_RPM_MODE)
-		MEC1322_FAN_CFG1 = 0xab;
-	else
-		MEC1322_FAN_CFG1 = 0x2b;
-	MEC1322_FAN_CFG2 = 0x1a;
-	clear_status();
-}
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
deleted file mode 100644
index fac5b08d8f..0000000000
--- a/chip/mec1322/flash.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "util.h"
-#include "hooks.h"
-
-#define PAGE_SIZE 256
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-static int entire_flash_locked;
-
-/* The previous write protect state before sys jump */
-
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/**
- * Read from physical flash.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Destination buffer for data.
- */
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	return spi_flash_read(data, offset, size);
-}
-
-/**
- * Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param offset        Flash offset to write.
- * @param size          Number of bytes to write.
- * @param data          Data to write to flash.  Must be 32-bit aligned.
- */
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int ret = EC_SUCCESS;
-	int  i, write_size;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < size; i += write_size) {
-		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
-				      (uint8_t *)data + i);
-		if (ret != EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param offset        Flash offset to erase.
- * @param size          Number of bytes to erase.
- */
-int crec_flash_physical_erase(int offset, int size)
-{
-	int ret;
-
-	if (entire_flash_locked)
-		return EC_ERROR_ACCESS_DENIED;
-
-	ret = spi_flash_erase(offset, size);
-	return ret;
-}
-
-/**
- * Read physical write protect setting for a flash bank.
- *
- * @param bank    Bank index to check.
- * @return        non-zero if bank is protected until reboot.
- */
-int crec_flash_physical_get_protect(int bank)
-{
-	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
-}
-
-/**
- * Protect flash now.
- *
- * This is always successful, and only emulates "now" protection
- *
- * @param all      Protect all (=1) or just read-only
- * @return         non-zero if error.
- */
-int crec_flash_physical_protect_now(int all)
-{
-	if (all)
-		entire_flash_locked = 1;
-
-	/*
-	 * RO "now" protection is not currently implemented. If needed, it
-	 * can be added by splitting the entire_flash_locked variable into
-	 * and RO and RW vars, and setting + checking the appropriate var
-	 * as required.
-	 */
-	return EC_SUCCESS;
-}
-
-/**
- * Return flash protect state flags from the physical layer.
- *
- * This should only be called by flash_get_protect().
- *
- * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF,
-				    CONFIG_WP_STORAGE_SIZE)) {
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-/**
- * Return the valid flash protect flags.
- *
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-/**
- * Return the writable flash protect flags.
- *
- * @param    cur_flags The current flash protect flags.
- * @return   A combination of EC_FLASH_PROTECT_* flags from ec_commands.h
- */
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-	enum spi_flash_wp wp_status = SPI_WP_NONE;
-
-	wp_status = spi_flash_check_wp();
-
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
-		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-
-	if (!entire_flash_locked)
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/**
- * Enable write protect for the specified range.
- *
- * Once write protect is enabled, it will stay enabled until HW PIN is
- * de-asserted and SRP register is unset.
- *
- * However, this implementation treats EC_FLASH_PROTECT_ALL_AT_BOOT as
- * EC_FLASH_PROTECT_RO_AT_BOOT but tries to remember if "all" region
- * is protected.
- *
- * @param new_flags to protect (only EC_FLASH_PROTECT_*_AT_BOOT are
- * taken care of)
- * @return              EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int offset, size, ret;
-	enum spi_flash_wp flashwp = SPI_WP_NONE;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection */
-		offset = size = 0;
-		flashwp = SPI_WP_NONE;
-	} else {
-		if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-			entire_flash_locked = 1;
-
-		offset = CONFIG_WP_STORAGE_OFF;
-		size = CONFIG_WP_STORAGE_SIZE;
-		flashwp = SPI_WP_HARDWARE;
-	}
-
-	ret = spi_flash_set_protect(offset, size);
-	if (ret == EC_SUCCESS)
-		ret = spi_flash_set_wp(flashwp);
-	return ret;
-}
-
-/**
- * Initialize the module.
- *
- * Applies at-boot protection settings if necessary.
- */
-int crec_flash_pre_init(void)
-{
-	crec_flash_physical_restore_state();
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c
deleted file mode 100644
index 331022c87c..0000000000
--- a/chip/mec1322/gpio.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for MEC1322 */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct gpio_int_mapping {
-	int8_t girq_id;
-	int8_t port_offset;
-};
-
-/* Mapping from GPIO port to GIRQ info */
-static const struct gpio_int_mapping int_map[22] = {
-	{11, 0}, {11, 0}, {11, 0}, {11, 0},
-	{10, 4}, {10, 4}, {10, 4}, {-1, -1},
-	{-1, -1}, {-1, -1}, {9, 10}, {9, 10},
-	{9, 10}, {9, 10}, {8, 14}, {8, 14},
-	{8, 14}, {-1, -1}, {-1, -1}, {-1, -1},
-	{20, 20}, {20, 20}
-};
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int i;
-	uint32_t val;
-
-	while (mask) {
-		i = __builtin_ffs(mask) - 1;
-		val = MEC1322_GPIO_CTL(port, i);
-		val &= ~(BIT(12) | BIT(13));
-		/* mux_control = DEFAULT, indicates GPIO */
-		if (func > GPIO_ALT_FUNC_DEFAULT)
-			val |= (func & 0x3) << 12;
-		MEC1322_GPIO_CTL(port, i) = val;
-		mask &= ~BIT(i);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-	uint32_t val;
-
-	if (mask == 0)
-		return 0;
-	i = GPIO_MASK_TO_NUM(mask);
-	val = MEC1322_GPIO_CTL(gpio_list[signal].port, i);
-
-	return (val & BIT(24)) ? 1 : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	uint32_t mask = gpio_list[signal].mask;
-	int i;
-
-	if (mask == 0)
-		return;
-	i = GPIO_MASK_TO_NUM(mask);
-
-	if (value)
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
-	else
-		MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	int i;
-	uint32_t val;
-	while (mask) {
-		i = GPIO_MASK_TO_NUM(mask);
-		mask &= ~BIT(i);
-		val = MEC1322_GPIO_CTL(port, i);
-
-		/*
-		 * Select open drain first, so that we don't glitch the signal
-		 * when changing the line to an output.
-		 */
-		if (flags & GPIO_OPEN_DRAIN)
-			val |= BIT(8);
-		else
-			val &= ~BIT(8);
-
-		if (flags & GPIO_OUTPUT) {
-			val |= BIT(9);
-			val &= ~BIT(10);
-		} else {
-			val &= ~BIT(9);
-			val |= BIT(10);
-		}
-
-		/* Handle pullup / pulldown */
-		if (flags & GPIO_PULL_UP)
-			val = (val & ~0x3) | 0x1;
-		else if (flags & GPIO_PULL_DOWN)
-			val = (val & ~0x3) | 0x2;
-		else
-			val &= ~0x3;
-
-		/* Set up interrupt */
-		if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-			val |= BIT(7);
-		else
-			val &= ~BIT(7);
-
-		val &= ~(0x7 << 4);
-
-		if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING))
-			val |= 0x7 << 4;
-		else if (flags & GPIO_INT_F_RISING)
-			val |= 0x5 << 4;
-		else if (flags & GPIO_INT_F_FALLING)
-			val |= 0x6 << 4;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= 0x1 << 4;
-		else if (!(flags & GPIO_INT_F_LOW)) /* No interrupt flag set */
-			val |= 0x4 << 4;
-
-		/* Set up level */
-		if (flags & GPIO_HIGH)
-			val |= BIT(16);
-		else if (flags & GPIO_LOW)
-			val &= ~BIT(16);
-
-		MEC1322_GPIO_CTL(port, i) = val;
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id);
-	MEC1322_INT_BLK_EN |= BIT(girq_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	MEC1322_INT_DISABLE(girq_id) = BIT(bit_id);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	int i, port, girq_id, bit_id;
-
-	if (gpio_list[signal].mask == 0)
-		return EC_SUCCESS;
-
-	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
-	port = gpio_list[signal].port;
-	girq_id = int_map[port].girq_id;
-	bit_id = (port - int_map[port].port_offset) * 8 + i;
-
-	/* Clear interrupt source sticky status bit even if not enabled */
-	MEC1322_INT_SOURCE(girq_id) |= 1 << bit_id;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	int i;
-	int flags;
-	int is_warm = system_is_reboot_warm();
-	const struct gpio_info *g = gpio_list;
-
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/* Use as GPIO, not alternate function */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/* Clear any interrupt flags before enabling GPIO interrupt */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \
-		task_enable_irq(MEC1322_IRQ_GIRQ ## x); \
-	} while (0)
-
-static void gpio_init(void)
-{
-	ENABLE_GPIO_GIRQ(8);
-	ENABLE_GPIO_GIRQ(9);
-	ENABLE_GPIO_GIRQ(10);
-	ENABLE_GPIO_GIRQ(11);
-	ENABLE_GPIO_GIRQ(20);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-
-/**
- * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for
- * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt
- * handlers.
- *
- * @param girq		GIRQ index
- * @param port_offset	GPIO port offset for the given GIRQ
- */
-static void gpio_interrupt(int girq, int port_offset)
-{
-	int i, bit;
-	const struct gpio_info *g = gpio_list;
-	uint32_t sts = MEC1322_INT_RESULT(girq);
-
-	MEC1322_INT_SOURCE(girq) |= sts;
-
-	for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) {
-		bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1;
-		if (sts & BIT(bit))
-			gpio_irq_handlers[i](i);
-		sts &= ~BIT(bit);
-	}
-}
-
-#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset)  \
-	void irqfunc(void)                         \
-	{                                          \
-		gpio_interrupt(girq, port_offset); \
-	}
-
-GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 14);
-GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 10);
-GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 4);
-GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0);
-GPIO_IRQ_FUNC(__girq_20_interrupt, 20, 20);
-
-#undef GPIO_IRQ_FUNC
-
-/*
- * Declare IRQs.  Nesting this macro inside the GPIO_IRQ_FUNC macro works
- * poorly because DECLARE_IRQ() stringizes its inputs.
- */
-DECLARE_IRQ(MEC1322_IRQ_GIRQ8, __girq_8_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ9, __girq_9_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ10, __girq_10_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ11, __girq_11_interrupt, 1);
-DECLARE_IRQ(MEC1322_IRQ_GIRQ20, __girq_20_interrupt, 1);
diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c
deleted file mode 100644
index a5c5858620..0000000000
--- a/chip/mec1322/hwtimer.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
-	MEC1322_TMR32_CTL(1) |= BIT(5);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff;
-}
-
-void __hw_clock_event_clear(void)
-{
-	MEC1322_TMR32_CTL(1) &= ~BIT(5);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return 0xffffffff - MEC1322_TMR32_CNT(0);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-	MEC1322_TMR32_CNT(0) = 0xffffffff - ts;
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-}
-
-static void __hw_clock_source_irq(int timer_id)
-{
-	if (timer_id == 1)
-		MEC1322_TMR32_STS(1) |= 1;
-	/* If IRQ is from timer 0, 32-bit timer overflowed */
-	process_timers(timer_id == 0);
-}
-
-void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
-DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
-
-static void configure_timer(int timer_id)
-{
-	uint32_t val;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(timer_id) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(timer_id) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(timer_id);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(timer_id) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(timer_id) = 0xffffffff;
-
-	/* Enable interrupt */
-	MEC1322_TMR32_IEN(timer_id) |= 1;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * The timer can only fire interrupt when its value reaches zero.
-	 * Therefore we need two timers:
-	 *   - Timer 0 as free running timer
-	 *   - Timer 1 as event timer
-	 */
-	configure_timer(0);
-	configure_timer(1);
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff - start_t;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-	/* Enable interrupt */
-	task_enable_irq(MEC1322_IRQ_TIMER32_0);
-	task_enable_irq(MEC1322_IRQ_TIMER32_1);
-	MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	return MEC1322_IRQ_TIMER32_1;
-}
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
deleted file mode 100644
index aecc8abd9b..0000000000
--- a/chip/mec1322/i2c.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_CLOCK 16000000 /* 16 MHz */
-
-/* Status */
-#define STS_NBB BIT(0) /* Bus busy */
-#define STS_LAB BIT(1) /* Arbitration lost */
-#define STS_LRB BIT(3) /* Last received bit */
-#define STS_BER BIT(4) /* Bus error */
-#define STS_PIN BIT(7) /* Pending interrupt */
-
-/* Control */
-#define CTRL_ACK BIT(0) /* Acknowledge */
-#define CTRL_STO BIT(1) /* STOP */
-#define CTRL_STA BIT(2) /* START */
-#define CTRL_ENI BIT(3) /* Enable interrupt */
-#define CTRL_ESO BIT(6) /* Enable serial output */
-#define CTRL_PIN BIT(7) /* Pending interrupt not */
-
-/* Completion */
-#define COMP_IDLE BIT(29)    /* i2c bus is idle */
-#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
-
-/* Maximum transfer of a SMBUS block transfer */
-#define SMBUS_MAX_BLOCK_SIZE 32
-
-/*
- * Amount of time to blocking wait for i2c bus to finish. After this blocking
- * timeout, if the bus is still not finished, then allow other tasks to run.
- * Note: this is just long enough for a 400kHz bus to finish transmitting one
- * byte assuming the bus isn't being held.
- */
-#define I2C_WAIT_BLOCKING_TIMEOUT_US 25
-
-enum i2c_transaction_state {
-	/* Stop condition was sent in previous transaction */
-	I2C_TRANSACTION_STOPPED,
-	/* Stop condition was not sent in previous transaction */
-	I2C_TRANSACTION_OPEN,
-};
-
-/* I2C controller state data */
-static struct {
-	/* Transaction timeout, or 0 to use default. */
-	uint32_t timeout_us;
-	/* Task waiting on port, or TASK_ID_INVALID if none. */
-	volatile task_id_t task_waiting;
-	enum i2c_transaction_state transaction_state;
-} cdata[I2C_CONTROLLER_COUNT];
-
-/* Map port number to port name in datasheet, for debug prints. */
-static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = {
-	[MEC1322_I2C0_0] = "0_0",
-	[MEC1322_I2C0_1] = "0_1",
-	[MEC1322_I2C1] = "1",
-	[MEC1322_I2C2] = "2",
-	[MEC1322_I2C3] = "3",
-};
-
-static void configure_controller_speed(int controller, int kbps)
-{
-	int t_low, t_high;
-	const int period = I2C_CLOCK / 1000 / kbps;
-
-	/*
-	 * Refer to NXP UM10204 for minimum timing requirement of T_Low and
-	 * T_High.
-	 * http://www.nxp.com/documents/user_manual/UM10204.pdf
-	 */
-	if (kbps > 400) {
-		/* Fast mode plus */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x06060601;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x06;
-	} else if (kbps > 100) {
-		/* Fast mode */
-		/* By spec, clk low period is 1.3us min */
-		t_low = MAX((int)(I2C_CLOCK * 1.3 / 1000000), period / 2 - 1);
-		t_high = period - t_low - 2;
-		MEC1322_I2C_DATA_TIM(controller) = 0x040a0a01;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x0a;
-	} else {
-		/* Standard mode */
-		t_low = t_high = period / 2 - 1;
-		MEC1322_I2C_DATA_TIM(controller) = 0x0c4d5006;
-		MEC1322_I2C_DATA_TIM_2(controller) = 0x4d;
-	}
-
-	/* Clock periods is one greater than the contents of these fields */
-	MEC1322_I2C_BUS_CLK(controller) = ((t_high & 0xff) << 8) |
-					  (t_low & 0xff);
-}
-
-static void configure_controller(int controller, int kbps)
-{
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN;
-	MEC1322_I2C_OWN_ADDR(controller) = 0x0;
-	configure_controller_speed(controller, kbps);
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_ACK | CTRL_ENI;
-	MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */
-
-	/* Enable interrupt */
-	MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */
-	MEC1322_INT_ENABLE(12) |= BIT(controller);
-	MEC1322_INT_BLK_EN |= BIT(12);
-}
-
-static void reset_controller(int controller)
-{
-	int i;
-
-	MEC1322_I2C_CONFIG(controller) |= BIT(9);
-	udelay(100);
-	MEC1322_I2C_CONFIG(controller) &= ~BIT(9);
-
-	for (i = 0; i < i2c_ports_used; ++i)
-		if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
-			configure_controller(controller, i2c_ports[i].kbps);
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-			break;
-		}
-}
-
-static int wait_for_interrupt(int controller, int timeout)
-{
-	int event;
-
-	if (timeout <= 0)
-		return EC_ERROR_TIMEOUT;
-
-	cdata[controller].task_waiting = task_get_current();
-	task_enable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wait until I2C interrupt or timeout. */
-	event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout);
-
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-	cdata[controller].task_waiting = TASK_ID_INVALID;
-
-	return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS;
-}
-
-static int wait_idle(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (!(sts & STS_NBB)) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	if (sts & (STS_BER | STS_LAB))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static int wait_byte_done(int controller)
-{
-	uint8_t sts = MEC1322_I2C_STATUS(controller);
-	uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US;
-	uint64_t task_timeout = block_timeout + cdata[controller].timeout_us;
-	int rv = 0;
-
-	while (sts & STS_PIN) {
-		if (rv)
-			return rv;
-		if (get_time().val > block_timeout)
-			rv = wait_for_interrupt(controller,
-						task_timeout - get_time().val);
-		sts = MEC1322_I2C_STATUS(controller);
-	}
-
-	return sts & STS_LRB;
-}
-
-static void select_port(int port)
-{
-	/*
-	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
-	 * use port 0.
-	 */
-	uint8_t port_sel = (port == MEC1322_I2C0_1) ? 1 : 0;
-	int controller = i2c_port_to_controller(port);
-
-	MEC1322_I2C_CONFIG(controller) &= ~0xf;
-	MEC1322_I2C_CONFIG(controller) |= port_sel;
-
-}
-
-static inline int get_line_level(int controller)
-{
-	int ret, ctrl;
-	/*
-	* We need to enable BB (Bit Bang) mode in order to read line level
-	* properly, othervise line levels return always idle (0x60).
-	*/
-	ctrl = MEC1322_I2C_BB_CTRL(controller);
-	MEC1322_I2C_BB_CTRL(controller) |= 1;
-	ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3;
-	MEC1322_I2C_BB_CTRL(controller) = ctrl;
-	return ret;
-}
-
-static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
-{
-	if (!skip) {
-		**in = val;
-		(*in)++;
-	}
-}
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	int i;
-	int controller;
-	int send_start = flags & I2C_XFER_START;
-	int send_stop = flags & I2C_XFER_STOP;
-	int skip = 0;
-	int bytes_to_read;
-	uint8_t reg;
-	int ret_done;
-
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	select_port(port);
-	controller = i2c_port_to_controller(port);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED)
-		wait_idle(controller);
-
-	reg = MEC1322_I2C_STATUS(controller);
-	if (send_start &&
-	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED &&
-	    (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-			    (get_line_level(controller)
-			    != I2C_LINE_IDLE))) {
-		CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d",
-			i2c_port_names[port], reg,
-			get_line_level(controller) & I2C_LINE_SCL_HIGH,
-			get_line_level(controller) & I2C_LINE_SDA_HIGH);
-
-		/* Attempt to unwedge the port. */
-		i2c_unwedge(port);
-
-		/* Bus error, bus busy, or arbitration lost. Try reset. */
-		reset_controller(controller);
-		select_port(port);
-
-		/*
-		 * We don't know what edges the slave saw, so sleep long enough
-		 * that the slave will see the new start condition below.
-		 */
-		usleep(1000);
-	}
-
-	if (out_size) {
-		if (send_start) {
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(slave_addr_flags)
-					  << 1);
-
-			/* Clock out the slave address, sending START bit */
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_ENI | CTRL_ACK |
-						       CTRL_STA;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-		}
-
-		for (i = 0; i < out_size; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			MEC1322_I2C_DATA(controller) = out[i];
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		/*
-		 * Send STOP bit if the stop flag is on, and caller
-		 * doesn't expect to receive data.
-		 */
-		if (send_stop && in_size == 0) {
-			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-						       CTRL_STO | CTRL_ACK;
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-		}
-	}
-
-	if (in_size) {
-		/* Resend start bit when changing direction */
-		if (out_size || send_start) {
-			/* Repeated start case */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_OPEN)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI;
-
-			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(slave_addr_flags)
-					  << 1)
-				| 0x01;
-
-			/* New transaction case, clock out slave address. */
-			if (cdata[controller].transaction_state ==
-			    I2C_TRANSACTION_STOPPED)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI |
-							       CTRL_PIN;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_OPEN;
-
-			/* Skip over the unused byte */
-			skip = 1;
-			in_size++;
-		}
-
-		/* Special flags need to be set for last two bytes */
-		bytes_to_read = send_stop ? in_size - 2 : in_size;
-
-		for (i = 0; i < bytes_to_read; ++i) {
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			skip = 0;
-		}
-		ret_done = wait_byte_done(controller);
-		if (ret_done)
-			goto err_chip_i2c_xfer;
-
-		if (send_stop) {
-			/*
-			 * De-assert ACK bit before reading the next to last
-			 * byte, so that the last byte is NACK'ed.
-			 */
-			MEC1322_I2C_CTRL(controller) = CTRL_ESO | CTRL_ENI;
-			push_in_buf(&in, MEC1322_I2C_DATA(controller), skip);
-			ret_done = wait_byte_done(controller);
-			if (ret_done)
-				goto err_chip_i2c_xfer;
-
-			/* Send STOP */
-			MEC1322_I2C_CTRL(controller) =
-				CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO;
-
-			cdata[controller].transaction_state =
-				I2C_TRANSACTION_STOPPED;
-
-			/*
-			 * We need to know our stop point two bytes in
-			 * advance. If we don't know soon enough, we need
-			 * to do an extra read (to last_addr + 1) to
-			 * issue the stop.
-			 */
-			push_in_buf(&in, MEC1322_I2C_DATA(controller),
-				    in_size == 1);
-		}
-	}
-
-	/* Check for error conditions */
-	if (MEC1322_I2C_STATUS(controller) & (STS_LAB | STS_BER))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-err_chip_i2c_xfer:
-	/* Send STOP and return error */
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_STO | CTRL_ACK;
-	cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-	if (ret_done == STS_LRB)
-		return EC_ERROR_BUSY;
-	else if (ret_done == EC_ERROR_TIMEOUT) {
-		/*
-		 * If our transaction timed out then our i2c controller
-		 * may be wedged without showing any other outward signs
-		 * of failure. Reset the controller so that future
-		 * transactions have a chance of success.
-		 */
-		reset_controller(controller);
-		return EC_ERROR_TIMEOUT;
-	}
-	else
-		return EC_ERROR_UNKNOWN;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_get_line_levels(int port)
-{
-	int rv;
-
-	i2c_lock(port, 1);
-	select_port(port);
-	rv = get_line_level(i2c_port_to_controller(port));
-	i2c_lock(port, 0);
-	return rv;
-}
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= MEC1322_I2C_PORT_COUNT)
-		return -1;
-	return (port == MEC1322_I2C0_0) ? 0 : port - 1;
-}
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	/* Param is port, but timeout is stored by-controller. */
-	cdata[i2c_port_to_controller(port)].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-void i2c_init(void)
-{
-	int i;
-	int controller;
-	int controller0_kbps = -1;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; ++i) {
-		/*
-		 * If this controller has multiple ports, check if we already
-		 * configured it. If so, ensure previously configured bitrate
-		 * matches.
-		 */
-		controller = i2c_port_to_controller(i2c_ports[i].port);
-		if (controller == 0) {
-			if (controller0_kbps != -1) {
-				ASSERT(controller0_kbps == i2c_ports[i].kbps);
-				continue;
-			}
-			controller0_kbps = i2c_ports[i].kbps;
-		}
-		configure_controller(controller, i2c_ports[i].kbps);
-		cdata[controller].task_waiting = TASK_ID_INVALID;
-		cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
-
-		/* Use default timeout. */
-		i2c_set_timeout(i2c_ports[i].port, 0);
-	}
-}
-
-static void handle_interrupt(int controller)
-{
-	int id = cdata[controller].task_waiting;
-
-	/* Clear the interrupt status */
-	MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE);
-
-	/*
-	 * Write to control register interferes with I2C transaction.
-	 * Instead, let's disable IRQ from the core until the next time
-	 * we want to wait for STS_PIN/STS_NBB.
-	 */
-	task_disable_irq(MEC1322_IRQ_I2C_0 + controller);
-
-	/* Wake up the task which was waiting on the I2C interrupt, if any. */
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_IDLE);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-
-DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_2, i2c2_interrupt, 2);
-DECLARE_IRQ(MEC1322_IRQ_I2C_3, i2c3_interrupt, 2);
diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c
deleted file mode 100644
index 2c62ada9ac..0000000000
--- a/chip/mec1322/keyboard_raw.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for MEC1322
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void keyboard_raw_init(void)
-{
-	keyboard_raw_enable_interrupt(0);
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/* Enable keyboard scan interrupt */
-	MEC1322_INT_ENABLE(17) |= BIT(21);
-	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_KS_KSI_INT_EN = 0xff;
-}
-
-void keyboard_raw_task_start(void)
-{
-	task_enable_irq(MEC1322_IRQ_KSC_INT);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	if (out == KEYBOARD_COLUMN_ALL) {
-		MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	} else if (out == KEYBOARD_COLUMN_NONE) {
-		MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	} else {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (out == 2) {
-			MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		} else {
-			MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-#else
-		MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
-#endif
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Invert it so 0=not pressed, 1=pressed */
-	return (MEC1322_KS_KSI_INPUT & 0xff) ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		task_clear_pending_irq(MEC1322_IRQ_KSC_INT);
-		task_enable_irq(MEC1322_IRQ_KSC_INT);
-	} else {
-		task_disable_irq(MEC1322_IRQ_KSC_INT);
-	}
-}
-
-void keyboard_raw_interrupt(void)
-{
-	/* Clear interrupt status bits */
-	MEC1322_KS_KSI_STATUS = 0xff;
-
-	/* Wake keyboard scan task to handle interrupt */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
deleted file mode 100644
index 1fb334e144..0000000000
--- a/chip/mec1322/lfw/ec_lfw.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "cros_version.h"
-#include "gpio.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "util.h"
-#include "timer.h"
-#include "dma.h"
-#include "registers.h"
-#include "cpu.h"
-#include "clock.h"
-#include "system.h"
-#include "hwtimer.h"
-#include "gpio_list.h"
-
-#include "ec_lfw.h"
-
-__attribute__ ((section(".intvector")))
-const struct int_vector_t hdr_int_vect = {
-			(void *)0x11FA00, /* init sp, unused,
-						set by MEC ROM loader*/
-			&lfw_main,	  /* reset vector */
-			&fault_handler,   /* NMI handler */
-			&fault_handler,   /* HardFault handler */
-			&fault_handler,   /* MPU fault handler */
-			&fault_handler    /* Bus fault handler */
-};
-
-/* SPI devices - from glados/board.c*/
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-
-void timer_init()
-{
-	uint32_t val = 0;
-
-	/* Ensure timer is not running */
-	MEC1322_TMR32_CTL(0) &= ~BIT(5);
-
-	/* Enable timer */
-	MEC1322_TMR32_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR32_CTL(0);
-
-	/* Pre-scale = 48 -> 1MHz -> Period = 1us */
-	val = (val & 0xffff) | (47 << 16);
-
-	MEC1322_TMR32_CTL(0) = val;
-
-	/* Set preload to use the full 32 bits of the timer */
-	MEC1322_TMR32_PRE(0) = 0xffffffff;
-
-	/* Override the count */
-	MEC1322_TMR32_CNT(0) = 0xffffffff;
-
-	/* Auto restart */
-	MEC1322_TMR32_CTL(0) |= BIT(3);
-
-	/* Start counting in timer 0 */
-	MEC1322_TMR32_CTL(0) |= BIT(5);
-
-}
-
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
-{
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
-
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-int spi_image_load(uint32_t offset)
-{
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
-	uint32_t i;
-
-	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
-	memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
-
-	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
-		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-
-	return 0;
-
-}
-
-void udelay(unsigned us)
-{
-	uint32_t t0 = __hw_clock_source_read();
-	while (__hw_clock_source_read() - t0 < us)
-		;
-}
-
-void usleep(unsigned us)
-{
-	udelay(us);
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return now->le.lo >= deadline.le.lo;
-}
-
-
-timestamp_t get_time(void)
-{
-	timestamp_t ts;
-
-	ts.le.hi = 0;
-	ts.le.lo = __hw_clock_source_read();
-	return ts;
-}
-
-void uart_write_c(char c)
-{
-	/* Put in carriage return prior to newline to mimic uart_vprintf() */
-	if (c == '\n')
-		uart_write_c('\r');
-
-	/* Wait for space in transmit FIFO. */
-	while (!(MEC1322_UART_LSR & BIT(5)))
-		;
-	MEC1322_UART_TB = c;
-}
-
-void uart_puts(const char *str)
-{
-	if (!str || !*str)
-		return;
-
-	do {
-		uart_write_c(*str++);
-	} while (*str);
-}
-
-void fault_handler(void)
-{
-	uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
-	/* trigger reset in 1 ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-	while (1)
-		;
-
-}
-
-void jump_to_image(uintptr_t init_addr)
-{
-	void (*resetvec)(void) = (void(*)(void))init_addr;
-	resetvec();
-}
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	gpio_config_module(MODULE_UART, 1);
-}
-
-void system_init(void)
-{
-
-	uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				MEC1322_PWR_RST_STS_VCC1;
-
-	if (rst_sts || wdt_sts)
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-void lfw_main()
-{
-
-	uintptr_t init_addr;
-
-	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
-
-	/* Use 48 MHz processor clock to power through boot */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-#ifdef CONFIG_WATCHDOG
-	/* Reload watchdog which may be running in case of sysjump */
-	MEC1322_WDG_KICK = 1;
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Stop aux timer */
-	MEC1322_TMR16_CTL(0) &= ~1;
-#endif
-#endif
-
-	timer_init();
-	clock_init();
-	cpu_init();
-	dma_init();
-	uart_init();
-	system_init();
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	uart_puts("littlefw ");
-	uart_puts(current_image_data.version);
-	uart_puts("\n");
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		uart_puts("lfw-RW load\n");
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-		spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF +
-			       CONFIG_RW_STORAGE_OFF);
-		break;
-	case EC_IMAGE_RO:
-		uart_puts("lfw-RO load\n");
-		spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF +
-			       CONFIG_RO_STORAGE_OFF);
-		/* fall through */
-	default:
-		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	jump_to_image(*(uintptr_t *)(init_addr + 4));
-
-	/* should never get here */
-	while (1)
-		;
-}
diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h
deleted file mode 100644
index dd26fbd323..0000000000
--- a/chip/mec1322/lfw/ec_lfw.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-#include <stdnoreturn.h>
-
-noreturn void lfw_main(void) __attribute__ ((naked));
-void fault_handler(void) __attribute__((naked));
-
-struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
-};
-
-#define SPI_CHUNK_SIZE			1024
diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld
deleted file mode 100644
index 65e17e4941..0000000000
--- a/chip/mec1322/lfw/ec_lfw.ld
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MEC1322 SoC little FW
- *
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    VECTOR(r )  : ORIGIN =  0x100000, LENGTH = 0x18
-    SRAM (xrw)  : ORIGIN =  0x100018, LENGTH = 0xBE8
-}
-
-/*
- * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the
- * values here.
- */
-ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.")
-ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0xC00, "Invalid VECTOR+SRAM length.")
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(lfw_main)
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
-    /*
-     * The vector table goes first
-     */
-    .intvector :
-    {
-        . = ALIGN(4);
-        KEEP(*(.intvector))
-    } > VECTOR
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to FLASH.
-     */
-
-    .text :
-    {
-        *(.text .text.*)                        /* all remaining code */
-        *(.rodata .rodata.*)            /* read-only data (constants) */
-    } >SRAM
-
-    . = ALIGN(4);
-
-    /* Padding */
-
-    .fill : {
-        FILL(0xFF);
-        . = ORIGIN(SRAM) + LENGTH(SRAM) - 1;
-        BYTE(0xFF);   /* emit at least a byte to make linker happy */
-    }
-
-    __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR);
-}
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
deleted file mode 100644
index 020cd0e23e..0000000000
--- a/chip/mec1322/lpc.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for MEC1322 */
-
-#include "acpi.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "chipset.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
-
-static struct host_packet lpc_packet;
-static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
-
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-	(struct ec_lpc_host_args *)mem_mapped;
-
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-}
-
-static void lpc_generate_sci(void)
-{
-#ifdef CONFIG_SCI_GPIO
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#else
-	MEC1322_ACPI_PM_STS |= 1;
-	udelay(65);
-	MEC1322_ACPI_PM_STS &= ~1;
-#endif
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return mem_mapped + 0x100;
-}
-
-static uint8_t *lpc_get_hostcmd_data_range(void)
-{
-	return mem_mapped;
-}
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via PCH_SMI_L GPIO
- *   - SCI pulse via PCH_SCI_L GPIO
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING;
-	}
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING;
-	} else {
-		MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING;
-	}
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte. */
-	MEC1322_ACPI_EC_EC2OS(1, 0) = pkt->driver_result;
-
-	/* Clear the busy bit, so the host knows the EC is done. */
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-}
-
-/*
- * Most registers in LPC module are reset when the host is off. We need to
- * set up LPC again when the host is starting up.
- */
-static void setup_lpc(void)
-{
-	gpio_config_module(MODULE_LPC, 1);
-
-	/* Set up interrupt on LRESET# deassert */
-	MEC1322_INT_SOURCE(19) = BIT(1);
-	MEC1322_INT_ENABLE(19) |= BIT(1);
-	MEC1322_INT_BLK_EN |= BIT(19);
-	task_enable_irq(MEC1322_IRQ_GIRQ19);
-
-	/* Set up ACPI0 for 0x62/0x66 */
-	MEC1322_LPC_ACPI_EC0_BAR = 0x00628304;
-	MEC1322_INT_ENABLE(15) |= BIT(6);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	/* Clear STATUS_PROCESSING bit in case it was set during sysjump */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-
-	/* Set up ACPI1 for 0x200/0x204 */
-	MEC1322_LPC_ACPI_EC1_BAR = 0x02008407;
-	MEC1322_INT_ENABLE(15) |= BIT(8);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF);
-
-	/* Set up 8042 interface at 0x60/0x64 */
-	MEC1322_LPC_8042_BAR = 0x00608104;
-
-	/* Set up indication of Auxiliary sts */
-	MEC1322_8042_KB_CTRL |= BIT(7);
-
-	MEC1322_8042_ACT |= 1;
-	MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14));
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_8042EM_IBF);
-	task_enable_irq(MEC1322_IRQ_8042EM_OBF);
-
-#ifndef CONFIG_KEYBOARD_IRQ_GPIO
-	/* Set up SERIRQ for keyboard */
-	MEC1322_8042_KB_CTRL |= BIT(5);
-	MEC1322_LPC_SIRQ(1) = 0x01;
-#endif
-
-	/* Set up EMI module for memory mapped region, base address 0x800 */
-	MEC1322_LPC_EMI_BAR = 0x0800800f;
-	MEC1322_INT_ENABLE(15) |= BIT(2);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_EMI);
-
-	/* Access data RAM through alias address */
-	MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000;
-
-	/*
-	 * Limit EMI read / write range. First 256 bytes are RW for host
-	 * commands. Second 256 bytes are RO for mem-mapped data.
-	 */
-	MEC1322_EMI_MRL0 = 0x200;
-	MEC1322_EMI_MWL0 = 0x100;
-
-	/* Set up Mailbox for Port80 trapping */
-	MEC1322_MBX_INDEX = 0xff;
-	MEC1322_LPC_MAILBOX_BAR = 0x00808901;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST);
-
-static void lpc_init(void)
-{
-	/* Activate LPC interface */
-	MEC1322_LPC_ACT |= 1;
-
-	/*
-	* Ring Oscillator not permitted to shut down
-	* until LPC activate bit is cleared
-	*/
-	MEC1322_LPC_CLK_CTRL |= 3;
-
-	/* Initialize host args and memory map to all zero */
-	memset(lpc_host_args, 0, sizeof(*lpc_host_args));
-	memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
-
-	setup_lpc();
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-void girq19_interrupt(void)
-{
-	/* Check interrupt result for LRESET# trigger */
-	if (MEC1322_INT_RESULT(19) & BIT(1)) {
-		/* Initialize LPC module when LRESET# is deasserted */
-		if (!lpc_get_pltrst_asserted()) {
-			setup_lpc();
-		} else {
-			/* Store port 80 reset event */
-			port_80_write(PORT_80_EVENT_RESET);
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-			/* Notify HOOK_CHIPSET_RESET */
-			hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-		}
-
-		CPRINTS("LPC RESET# %sasserted",
-			lpc_get_pltrst_asserted() ? "" : "de");
-
-		/* Clear interrupt source */
-		MEC1322_INT_SOURCE(19) = BIT(1);
-	}
-}
-DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1);
-
-void emi_interrupt(void)
-{
-	port_80_write(MEC1322_EMI_H2E_MBX);
-}
-DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1);
-
-/*
- * Port80 POST code polling limitation:
- * - POST code 0xFF is ignored.
- */
-int port_80_read(void)
-{
-	int data;
-
-	/* read MBX_INDEX for POST code */
-	data = MEC1322_MBX_INDEX;
-
-	/* clear MBX_INDEX for next POST code*/
-	MEC1322_MBX_INDEX = 0xff;
-
-	/* mark POST code 0xff as invalid */
-	if (data == 0xff)
-		data = PORT_80_IGNORE;
-
-	return data;
-}
-
-void acpi_0_interrupt(void)
-{
-	uint8_t value, result, is_cmd;
-
-	is_cmd = MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_LAST_CMD;
-
-	/* Set the bust bi */
-	MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING;
-
-	/* Read command/data; this clears the FRMH bit. */
-	value = MEC1322_ACPI_EC_OS2EC(0, 0);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		MEC1322_ACPI_EC_EC2OS(0, 0) = result;
-
-	/* Clear the busy bit */
-	MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-
-void acpi_1_interrupt(void)
-{
-	uint8_t st = MEC1322_ACPI_EC_STATUS(1);
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
-		return;
-
-	/* Set the busy bit */
-	MEC1322_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING;
-
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = MEC1322_ACPI_EC_OS2EC(1, 0);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* We only support new style command (v3) now */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)lpc_get_hostcmd_data_range();
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)lpc_get_hostcmd_data_range();
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-		host_packet_receive(&lpc_packet);
-		return;
-	} else {
-		/* Old style command unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
-
-#ifdef HAS_TASK_KEYPROTO
-void kb_ibf_interrupt(void)
-{
-	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MEC1322_8042_H2E,
-				    MEC1322_8042_STS & BIT(3));
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1);
-
-void kb_obf_interrupt(void)
-{
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1);
-#endif
-
-int lpc_keyboard_has_char(void)
-{
-	return (MEC1322_8042_STS & BIT(0)) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	return (MEC1322_8042_STS & BIT(1)) ? 1 : 0;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	MEC1322_8042_E2H = chr;
-	if (send_irq)
-		keyboard_irq_assert();
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	volatile char unused __attribute__((unused));
-
-	unused = MEC1322_8042_OBF_CLR;
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	MEC1322_ACPI_EC_STATUS(0) &= ~mask;
-}
-
-int lpc_get_pltrst_asserted(void)
-{
-	return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
-}
-
-/* Enable LPC ACPI-EC0 interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* Disable LPC ACPI-EC0 interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
-}
-
-/* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
-{
-	lpc_init();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c
deleted file mode 100644
index df4583ed8b..0000000000
--- a/chip/mec1322/port80.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 Timer Interrupt for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "port80.h"
-#include "registers.h"
-#include "task.h"
-
-/* Fire timer interrupt every 1000 usec to check for port80 data. */
-#define POLL_PERIOD_USEC 1000
-/* After 30 seconds of no port 80 data, disable the timer interrupt. */
-#define INTERRUPT_DISABLE_TIMEOUT_SEC 30
-#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \
-				      * 1000000 \
-				      / POLL_PERIOD_USEC)
-
-/* Count the number of consecutive interrupts with no port 80 data. */
-static int idle_count;
-
-static void port_80_interrupt_enable(void)
-{
-	idle_count = 0;
-
-	/* Enable the interrupt. */
-	task_enable_irq(MEC1322_IRQ_TIMER16_1);
-	/* Enable and start the timer. */
-	MEC1322_TMR16_CTL(1) |= 1 | BIT(5);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
-
-static void port_80_interrupt_disable(void)
-{
-	/* Disable the timer block. */
-	MEC1322_TMR16_CTL(1) &= ~1;
-	/* Disable the interrupt. */
-	task_disable_irq(MEC1322_IRQ_TIMER16_1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable,
-	     HOOK_PRIO_DEFAULT);
-
-/*
- * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown
- * timer.  This timer is on GIRQ23, bit 1.
- */
-static void port_80_interrupt_init(void)
-{
-	uint32_t val = 0;
-
-	/*
-	 * The timers are driven by a 48MHz oscillator.  Prescale down to
-	 * 1MHz. 48MHz/48 -> 1MHz
-	 */
-	val = MEC1322_TMR16_CTL(1);
-	val = (val & 0xFFFF) | (47 << 16);
-	/* Automatically restart the timer. */
-	val |= BIT(3);
-	/* The counter should decrement. */
-	val &= ~BIT(2);
-	MEC1322_TMR16_CTL(1) = val;
-
-	/* Set the reload value(us). */
-	MEC1322_TMR16_PRE(1) = POLL_PERIOD_USEC;
-
-	/* Clear the status if any. */
-	MEC1322_TMR16_STS(1) |= 1;
-
-	/* Clear any pending interrupt. */
-	MEC1322_INT_SOURCE(23) = BIT(1);
-	/* Enable IRQ vector 23. */
-	MEC1322_INT_BLK_EN |= BIT(23);
-	/* Enable the interrupt. */
-	MEC1322_TMR16_IEN(1) |= 1;
-	MEC1322_INT_ENABLE(23) = BIT(1);
-
-	port_80_interrupt_enable();
-}
-DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT);
-
-void port_80_interrupt(void)
-{
-	int data;
-
-	MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */
-	if (BIT(1) & MEC1322_INT_RESULT(23)) {
-		data = port_80_read();
-
-		if (data != PORT_80_IGNORE) {
-			idle_count = 0;
-			port_80_write(data);
-		}
-	}
-
-	if (++idle_count >= INTERRUPT_DISABLE_IDLE_COUNT)
-		port_80_interrupt_disable();
-}
-DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2);
diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c
deleted file mode 100644
index ce94e50e7e..0000000000
--- a/chip/mec1322/pwm.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for MEC1322 */
-
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * PWMs that must remain active in low-power idle - MEC1322_PCR_EC_SLP_EN
- * bit mask.
- */
-static uint32_t pwm_keep_awake_mask;
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (enabled) {
-		MEC1322_PWM_CFG(id) |= 0x1;
-		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |=
-				MEC1322_PCR_EC_SLP_EN_PWM(id);
-	} else {
-		MEC1322_PWM_CFG(id) &= ~0x1;
-		pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id);
-	}
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1;
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	int id = pwm_channels[ch].channel;
-
-	if (percent < 0)
-		percent = 0;
-	else if (percent > 100)
-		percent = 100;
-
-	MEC1322_PWM_ON(id) = percent;
-	MEC1322_PWM_OFF(id) = 100 - percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	return MEC1322_PWM_ON(pwm_channels[ch].channel);
-}
-
-uint32_t pwm_get_keep_awake_mask(void)
-{
-	return pwm_keep_awake_mask;
-}
-
-static void pwm_configure(int ch, int active_low, int clock_low)
-{
-	/*
-	 * clock_low=0 selects the 48MHz Ring Oscillator source
-	 * clock_low=1 selects the 100kHz_Clk source
-	 */
-	MEC1322_PWM_CFG(ch) = (15 << 3) |    /* Pre-divider = 16 */
-			      (active_low ? BIT(2) : 0) |
-			      (clock_low  ? BIT(1) : 0);
-}
-
-static void pwm_init(void)
-{
-	int i;
-
-	for (i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm_configure(pwm_channels[i].channel,
-			      pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW,
-			      pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK);
-		pwm_set_duty(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h
deleted file mode 100644
index 9c441aaecd..0000000000
--- a/chip/mec1322/pwm_chip.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MEC1322-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM Channel ID */
-	int channel;
-
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-/*
- * Returns PWMs that must remain active in low-power idle -
- * MEC1322_PCR_EC_SLP_EN bit mask.
- */
-uint32_t pwm_get_keep_awake_mask(void);
-#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
deleted file mode 100644
index 7bbd9fb068..0000000000
--- a/chip/mec1322/registers.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for MEC1322 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/* Helper function for RAM address aliasing */
-#define MEC1322_RAM_ALIAS(x)   \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
-
-/* EC Chip Configuration */
-#define MEC1322_CHIP_BASE      0x400fff00
-#define MEC1322_CHIP_DEV_ID    REG8(MEC1322_CHIP_BASE + 0x20)
-#define MEC1322_CHIP_DEV_REV   REG8(MEC1322_CHIP_BASE + 0x21)
-
-
-/* Power/Clocks/Resets */
-#define MEC1322_PCR_BASE         0x40080100
-#define MEC1322_PCR_CHIP_SLP_EN  REG32(MEC1322_PCR_BASE + 0x0)
-#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
-#define MEC1322_PCR_EC_SLP_EN    REG32(MEC1322_PCR_BASE + 0x8)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN_SLEEP	0xe0700ff7
-#define  MEC1322_PCR_EC_SLP_EN_PWM(n)	(1 << ((n) ? (19 + (n)) : 4))
-#define  MEC1322_PCR_EC_SLP_EN_PWM3	BIT(22)
-#define  MEC1322_PCR_EC_SLP_EN_PWM2	BIT(21)
-#define  MEC1322_PCR_EC_SLP_EN_PWM1	BIT(20)
-#define  MEC1322_PCR_EC_SLP_EN_PWM0	BIT(4)
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN_WAKE	(~0xe0700ff7)
-#define MEC1322_PCR_EC_CLK_REQ   REG32(MEC1322_PCR_BASE + 0xc)
-#define MEC1322_PCR_HOST_SLP_EN  REG32(MEC1322_PCR_BASE + 0x10)
-/* Command all blocks to sleep */
-#define  MEC1322_PCR_HOST_SLP_EN_SLEEP	0x5f003
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_HOST_SLP_EN_WAKE	(~0x5f003)
-#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
-#define MEC1322_PCR_SYS_SLP_CTL  REG32(MEC1322_PCR_BASE + 0x18)
-#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
-#define MEC1322_PCR_EC_SLP_EN2   REG32(MEC1322_PCR_BASE + 0x24)
-/* Mask to command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN2_SLEEP	0x1ffffff8
-/* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN2_WAKE	(~0x03fffff8)
-#define MEC1322_PCR_EC_CLK_REQ2  REG32(MEC1322_PCR_BASE + 0x28)
-#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
-#define MEC1322_PCR_CHIP_OSC_ID  REG32(MEC1322_PCR_BASE + 0x30)
-#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34)
-#define MEC1322_PCR_CHIP_RST_EN  REG32(MEC1322_PCR_BASE + 0x38)
-#define MEC1322_PCR_HOST_RST_EN  REG32(MEC1322_PCR_BASE + 0x3c)
-#define MEC1322_PCR_EC_RST_EN    REG32(MEC1322_PCR_BASE + 0x40)
-#define MEC1322_PCR_EC_RST_EN2   REG32(MEC1322_PCR_BASE + 0x44)
-#define MEC1322_PCR_PWR_RST_CTL  REG32(MEC1322_PCR_BASE + 0x48)
-
-/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */
-#define MEC1322_PWR_RST_STS_VCC1 BIT(6)
-#define MEC1322_PWR_RST_STS_VBAT BIT(5)
-
-/* EC Subsystem */
-#define MEC1322_EC_BASE        0x4000fc00
-#define MEC1322_EC_INT_CTRL    REG32(MEC1322_EC_BASE + 0x18)
-#define MEC1322_EC_TRACE_EN    REG32(MEC1322_EC_BASE + 0x1c)
-#define MEC1322_EC_JTAG_EN     REG32(MEC1322_EC_BASE + 0x20)
-#define MEC1322_EC_WDT_CNT     REG32(MEC1322_EC_BASE + 0x28)
-#define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38)
-
-/* Interrupt aggregator */
-#define MEC1322_INT_BASE       0x4000c000
-#define MEC1322_INTx_BASE(x)   (MEC1322_INT_BASE + ((x) - 8) * 0x14)
-#define MEC1322_INT_SOURCE(x)  REG32(MEC1322_INTx_BASE(x) + 0x0)
-#define MEC1322_INT_ENABLE(x)  REG32(MEC1322_INTx_BASE(x) + 0x4)
-#define MEC1322_INT_RESULT(x)  REG32(MEC1322_INTx_BASE(x) + 0x8)
-#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc)
-#define MEC1322_INT_BLK_EN     REG32(MEC1322_INT_BASE + 0x200)
-#define MEC1322_INT_BLK_DIS    REG32(MEC1322_INT_BASE + 0x204)
-#define MEC1322_INT_BLK_IRQ    REG32(MEC1322_INT_BASE + 0x208)
-
-
-/* UART */
-#define MEC1322_UART_CONFIG_BASE  0x400f1f00
-#define MEC1322_UART_RUNTIME_BASE 0x400f1c00
-
-#define MEC1322_UART_ACT       REG8(MEC1322_UART_CONFIG_BASE + 0x30)
-#define MEC1322_UART_CFG       REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
-
-/* DLAB=0 */
-#define MEC1322_UART_RB /*R*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_TB /*W*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_IER       REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-/* DLAB=1 */
-#define MEC1322_UART_PBRG0     REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_PBRG1     REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
-
-#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_LCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
-#define MEC1322_UART_MCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
-#define MEC1322_UART_LSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
-#define MEC1322_UART_MSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
-#define MEC1322_UART_SCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
-
-/* Bit defines for MEC1322_UART_LSR */
-#define MEC1322_LSR_TX_EMPTY     BIT(5)
-
-/* GPIO */
-#define MEC1322_GPIO_BASE      0x40081000
-
-static inline uintptr_t gpio_port_base(int port_id)
-{
-	int oct = (port_id / 10) * 8 + port_id % 10;
-	return MEC1322_GPIO_BASE + oct * 0x20;
-}
-#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2))
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-
-/* Timer */
-#define MEC1322_TMR16_BASE(x)  (0x40000c00 + (x) * 0x20)
-#define MEC1322_TMR32_BASE(x)  (0x40000c80 + (x) * 0x20)
-
-#define MEC1322_TMR16_CNT(x)   REG32(MEC1322_TMR16_BASE(x) + 0x0)
-#define MEC1322_TMR16_PRE(x)   REG32(MEC1322_TMR16_BASE(x) + 0x4)
-#define MEC1322_TMR16_STS(x)   REG32(MEC1322_TMR16_BASE(x) + 0x8)
-#define MEC1322_TMR16_IEN(x)   REG32(MEC1322_TMR16_BASE(x) + 0xc)
-#define MEC1322_TMR16_CTL(x)   REG32(MEC1322_TMR16_BASE(x) + 0x10)
-#define MEC1322_TMR32_CNT(x)   REG32(MEC1322_TMR32_BASE(x) + 0x0)
-#define MEC1322_TMR32_PRE(x)   REG32(MEC1322_TMR32_BASE(x) + 0x4)
-#define MEC1322_TMR32_STS(x)   REG32(MEC1322_TMR32_BASE(x) + 0x8)
-#define MEC1322_TMR32_IEN(x)   REG32(MEC1322_TMR32_BASE(x) + 0xc)
-#define MEC1322_TMR32_CTL(x)   REG32(MEC1322_TMR32_BASE(x) + 0x10)
-
-
-/* Watchdog */
-#define MEC1322_WDG_BASE       0x40000400
-#define MEC1322_WDG_LOAD       REG16(MEC1322_WDG_BASE + 0x0)
-#define MEC1322_WDG_CTL        REG8(MEC1322_WDG_BASE + 0x4)
-#define MEC1322_WDG_KICK       REG8(MEC1322_WDG_BASE + 0x8)
-#define MEC1322_WDG_CNT        REG16(MEC1322_WDG_BASE + 0xc)
-
-
-/* VBAT */
-#define MEC1322_VBAT_BASE      0x4000a400
-#define MEC1322_VBAT_STS       REG32(MEC1322_VBAT_BASE + 0x0)
-#define MEC1322_VBAT_CE        REG32(MEC1322_VBAT_BASE + 0x8)
-#define MEC1322_VBAT_RAM(x)    REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
-
-/* Bit definition for MEC1322_VBAT_STS */
-#define MEC1322_VBAT_STS_WDT	BIT(5)
-
-/* Miscellaneous firmware control fields
- * scratch pad index cannot be more than 16 as
- * mec has 64 bytes = 16 indexes of scratchpad RAM
- */
-#define MEC1322_IMAGETYPE_IDX     15
-
-/* LPC */
-#define MEC1322_LPC_CFG_BASE     0x400f3300
-#define MEC1322_LPC_ACT          REG8(MEC1322_LPC_CFG_BASE + 0x30)
-#define MEC1322_LPC_SIRQ(x)      REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
-#define MEC1322_LPC_CFG_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x60)
-#define MEC1322_LPC_EMI_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x64)
-#define MEC1322_LPC_UART_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x68)
-#define MEC1322_LPC_8042_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x78)
-#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88)
-#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c)
-#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90)
-#define MEC1322_LPC_PORT92_BAR   REG32(MEC1322_LPC_CFG_BASE + 0x94)
-#define MEC1322_LPC_MAILBOX_BAR  REG32(MEC1322_LPC_CFG_BASE + 0x98)
-#define MEC1322_LPC_RTC_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x9c)
-#define MEC1322_LPC_MEM_BAR      REG32(MEC1322_LPC_CFG_BASE + 0xa0)
-#define MEC1322_LPC_MEM_BAR_CFG  REG32(MEC1322_LPC_CFG_BASE + 0xa4)
-
-#define MEC1322_LPC_RT_BASE      0x400f3100
-#define MEC1322_LPC_BUS_MONITOR  REG32(MEC1322_LPC_RT_BASE + 0x4)
-#define MEC1322_LPC_CLK_CTRL     REG32(MEC1322_LPC_RT_BASE + 0x10)
-#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc)
-
-
-/* EMI */
-#define MEC1322_EMI_BASE       0x400f0100
-#define MEC1322_EMI_H2E_MBX    REG8(MEC1322_EMI_BASE + 0x0)
-#define MEC1322_EMI_E2H_MBX    REG8(MEC1322_EMI_BASE + 0x1)
-#define MEC1322_EMI_MBA0       REG32(MEC1322_EMI_BASE + 0x4)
-#define MEC1322_EMI_MRL0       REG16(MEC1322_EMI_BASE + 0x8)
-#define MEC1322_EMI_MWL0       REG16(MEC1322_EMI_BASE + 0xa)
-#define MEC1322_EMI_MBA1       REG32(MEC1322_EMI_BASE + 0xc)
-#define MEC1322_EMI_MRL1       REG16(MEC1322_EMI_BASE + 0x10)
-#define MEC1322_EMI_MWL1       REG16(MEC1322_EMI_BASE + 0x12)
-#define MEC1322_EMI_ISR        REG16(MEC1322_EMI_BASE + 0x14)
-#define MEC1322_EMI_HCE        REG16(MEC1322_EMI_BASE + 0x16)
-
-#define MEC1322_EMI_RT_BASE    0x400f0000
-#define MEC1322_EMI_ISR_B0     REG8(MEC1322_EMI_RT_BASE + 0x8)
-#define MEC1322_EMI_ISR_B1     REG8(MEC1322_EMI_RT_BASE + 0x9)
-#define MEC1322_EMI_IMR_B0     REG8(MEC1322_EMI_RT_BASE + 0xa)
-#define MEC1322_EMI_IMR_B1     REG8(MEC1322_EMI_RT_BASE + 0xb)
-
-
-/* Mailbox */
-#define MEC1322_MBX_RT_BASE    0x400f2400
-#define MEC1322_MBX_INDEX      REG8(MEC1322_MBX_RT_BASE + 0x0)
-#define MEC1322_MBX_DATA       REG8(MEC1322_MBX_RT_BASE + 0x1)
-
-#define MEC1322_MBX_BASE       0x400f2500
-#define MEC1322_MBX_H2E_MBX    REG8(MEC1322_MBX_BASE + 0x0)
-#define MEC1322_MBX_E2H_MBX    REG8(MEC1322_MBX_BASE + 0x4)
-#define MEC1322_MBX_ISR        REG8(MEC1322_MBX_BASE + 0x8)
-#define MEC1322_MBX_IMR        REG8(MEC1322_MBX_BASE + 0xc)
-#define MEC1322_MBX_REG(x)     REG8(MEC1322_MBX_BASE + 0x10 + (x))
-
-
-/* PWM */
-#define MEC1322_PWM_BASE(x)    (0x40005800 + (x) * 0x10)
-#define MEC1322_PWM_ON(x)      REG32(MEC1322_PWM_BASE(x) + 0x00)
-#define MEC1322_PWM_OFF(x)     REG32(MEC1322_PWM_BASE(x) + 0x04)
-#define MEC1322_PWM_CFG(x)     REG32(MEC1322_PWM_BASE(x) + 0x08)
-
-
-/* ACPI */
-#define MEC1322_ACPI_EC_BASE(x)     (0x400f0c00 + (x) * 0x400)
-#define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MEC1322_ACPI_EC_STATUS(x)   REG8(MEC1322_ACPI_EC_BASE(x) + 0x104)
-#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
-#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
-
-#define MEC1322_ACPI_PM_RT_BASE     0x400f1400
-#define MEC1322_ACPI_PM1_STS1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
-#define MEC1322_ACPI_PM1_STS2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
-#define MEC1322_ACPI_PM1_EN1        REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
-#define MEC1322_ACPI_PM1_EN2        REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
-#define MEC1322_ACPI_PM1_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
-#define MEC1322_ACPI_PM1_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
-#define MEC1322_ACPI_PM2_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
-#define MEC1322_ACPI_PM2_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
-#define MEC1322_ACPI_PM_EC_BASE     0x400f1500
-#define MEC1322_ACPI_PM_STS         REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
-
-
-/* 8042 */
-#define MEC1322_8042_BASE      0x400f0400
-#define MEC1322_8042_OBF_CLR   REG8(MEC1322_8042_BASE + 0x0)
-#define MEC1322_8042_H2E       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_E2H       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_STS       REG8(MEC1322_8042_BASE + 0x104)
-#define MEC1322_8042_KB_CTRL   REG8(MEC1322_8042_BASE + 0x108)
-#define MEC1322_8042_PCOBF     REG8(MEC1322_8042_BASE + 0x114)
-#define MEC1322_8042_ACT       REG8(MEC1322_8042_BASE + 0x330)
-
-
-/* FAN */
-#define MEC1322_FAN_BASE       0x4000a000
-#define MEC1322_FAN_SETTING    REG8(MEC1322_FAN_BASE + 0x0)
-#define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1)
-#define MEC1322_FAN_CFG1       REG8(MEC1322_FAN_BASE + 0x2)
-#define MEC1322_FAN_CFG2       REG8(MEC1322_FAN_BASE + 0x3)
-#define MEC1322_FAN_GAIN       REG8(MEC1322_FAN_BASE + 0x5)
-#define MEC1322_FAN_SPIN_UP    REG8(MEC1322_FAN_BASE + 0x6)
-#define MEC1322_FAN_STEP       REG8(MEC1322_FAN_BASE + 0x7)
-#define MEC1322_FAN_MIN_DRV    REG8(MEC1322_FAN_BASE + 0x8)
-#define MEC1322_FAN_VALID_CNT  REG8(MEC1322_FAN_BASE + 0x9)
-#define MEC1322_FAN_DRV_FAIL   REG16(MEC1322_FAN_BASE + 0xa)
-#define MEC1322_FAN_TARGET     REG16(MEC1322_FAN_BASE + 0xc)
-#define MEC1322_FAN_READING    REG16(MEC1322_FAN_BASE + 0xe)
-#define MEC1322_FAN_BASE_FREQ  REG8(MEC1322_FAN_BASE + 0x10)
-#define MEC1322_FAN_STATUS     REG8(MEC1322_FAN_BASE + 0x11)
-
-
-/* I2C */
-#define MEC1322_I2C0_BASE      0x40001800
-#define MEC1322_I2C1_BASE      0x4000ac00
-#define MEC1322_I2C2_BASE      0x4000b000
-#define MEC1322_I2C3_BASE      0x4000b400
-#define MEC1322_I2C_BASESEP    0x00000400
-#define MEC1322_I2C_ADDR(controller, offset) \
-	(offset + (controller == 0 ? MEC1322_I2C0_BASE : \
-		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
-
-/*
- * MEC1322 has five ports distributed among four controllers. Locking must
- * occur by-controller (not by-port).
- */
-enum mec1322_i2c_port {
-	MEC1322_I2C0_0 = 0,      /* Controller 0, port 0 */
-	MEC1322_I2C0_1 = 1,      /* Controller 0, port 1 */
-	MEC1322_I2C1   = 2,      /* Controller 1 */
-	MEC1322_I2C2   = 3,      /* Controller 2 */
-	MEC1322_I2C3   = 4,      /* Controller 3 */
-	MEC1322_I2C_PORT_COUNT,
-};
-
-#define MEC1322_I2C_CTRL(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_STATUS(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_OWN_ADDR(ctrl)      REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
-#define MEC1322_I2C_DATA(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
-#define MEC1322_I2C_MASTER_CMD(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
-#define MEC1322_I2C_SLAVE_CMD(ctrl)     REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
-#define MEC1322_I2C_PEC(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
-#define MEC1322_I2C_DATA_TIM_2(ctrl)    REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
-#define MEC1322_I2C_COMPLETE(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
-#define MEC1322_I2C_IDLE_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
-#define MEC1322_I2C_CONFIG(ctrl)        REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
-#define MEC1322_I2C_BUS_CLK(ctrl)       REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
-#define MEC1322_I2C_BLK_ID(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
-#define MEC1322_I2C_REV(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
-#define MEC1322_I2C_BB_CTRL(ctrl)       REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
-#define MEC1322_I2C_DATA_TIM(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
-#define MEC1322_I2C_TOUT_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
-#define MEC1322_I2C_SLAVE_TX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
-#define MEC1322_I2C_SLAVE_RX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
-#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50))
-#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54))
-
-
-/* Keyboard scan matrix */
-#define MEC1322_KS_BASE        0x40009c00
-#define MEC1322_KS_KSO_SEL     REG32(MEC1322_KS_BASE + 0x4)
-#define MEC1322_KS_KSI_INPUT   REG32(MEC1322_KS_BASE + 0x8)
-#define MEC1322_KS_KSI_STATUS  REG32(MEC1322_KS_BASE + 0xc)
-#define MEC1322_KS_KSI_INT_EN  REG32(MEC1322_KS_BASE + 0x10)
-#define MEC1322_KS_EXT_CTRL    REG32(MEC1322_KS_BASE + 0x14)
-
-
-/* ADC */
-#define MEC1322_ADC_BASE       0x40007c00
-#define MEC1322_ADC_CTRL       REG32(MEC1322_ADC_BASE + 0x0)
-#define MEC1322_ADC_DELAY      REG32(MEC1322_ADC_BASE + 0x4)
-#define MEC1322_ADC_STS        REG32(MEC1322_ADC_BASE + 0x8)
-#define MEC1322_ADC_SINGLE     REG32(MEC1322_ADC_BASE + 0xc)
-#define MEC1322_ADC_REPEAT     REG32(MEC1322_ADC_BASE + 0x10)
-#define MEC1322_ADC_READ(x)    REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4)
-
-
-/* Hibernation timer */
-#define MEC1322_HTIMER_BASE    0x40009800
-#define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0)
-#define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4)
-#define MEC1322_HTIMER_COUNT   REG16(MEC1322_HTIMER_BASE + 0x8)
-
-
-/* SPI */
-#define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port))
-#define MEC1322_SPI_AR(port)   REG8(MEC1322_SPI_BASE(port) + 0x00)
-#define MEC1322_SPI_CR(port)   REG8(MEC1322_SPI_BASE(port) + 0x04)
-#define MEC1322_SPI_SR(port)   REG8(MEC1322_SPI_BASE(port) + 0x08)
-#define MEC1322_SPI_TD(port)   REG8(MEC1322_SPI_BASE(port) + 0x0c)
-#define MEC1322_SPI_RD(port)   REG8(MEC1322_SPI_BASE(port) + 0x10)
-#define MEC1322_SPI_CC(port)   REG8(MEC1322_SPI_BASE(port) + 0x14)
-#define MEC1322_SPI_CG(port)   REG8(MEC1322_SPI_BASE(port) + 0x18)
-
-
-/* DMA */
-#define MEC1322_DMA_BASE            0x40002400
-
-/*
- * Available DMA channels.
- *
- * On MEC1322, any DMA channel may serve any device. Since we have
- * 12 channels and 12 devices, we make each channel dedicated to the
- * device of the same number.
- */
-enum dma_channel {
-	/* Channel numbers */
-	MEC1322_DMAC_I2C0_SLAVE =  0,
-	MEC1322_DMAC_I2C0_MASTER = 1,
-	MEC1322_DMAC_I2C1_SLAVE =  2,
-	MEC1322_DMAC_I2C1_MASTER = 3,
-	MEC1322_DMAC_I2C2_SLAVE =  4,
-	MEC1322_DMAC_I2C2_MASTER = 5,
-	MEC1322_DMAC_I2C3_SLAVE =  6,
-	MEC1322_DMAC_I2C3_MASTER = 7,
-	MEC1322_DMAC_SPI0_TX =     8,
-	MEC1322_DMAC_SPI0_RX =     9,
-	MEC1322_DMAC_SPI1_TX =    10,
-	MEC1322_DMAC_SPI1_RX =    11,
-
-	/* Channel count */
-	MEC1322_DMAC_COUNT =      12,
-};
-
-/* Registers for a single channel of the DMA controller */
-struct mec1322_dma_chan {
-	uint32_t act;         /* Activate */
-	uint32_t mem_start;   /* Memory start address */
-	uint32_t mem_end;     /* Memory end address */
-	uint32_t dev;         /* Device address */
-	uint32_t ctrl;        /* Control */
-	uint32_t int_status;  /* Interrupt status */
-	uint32_t int_enabled; /* Interrupt enabled */
-	uint32_t pad;
-};
-
-/* Always use mec1322_dma_chan_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_chan mec1322_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef mec1322_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct mec1322_dma_regs {
-	uint32_t ctrl;
-	uint32_t data;
-	uint32_t pad[2];
-	mec1322_dma_chan_t chan[MEC1322_DMAC_COUNT];
-};
-
-/* Always use mec1322_dma_regs_t so volatile keyword is included! */
-typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t;
-
-#define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE)
-
-/* Bits for DMA channel regs */
-#define MEC1322_DMA_ACT_EN		BIT(0)
-#define MEC1322_DMA_XFER_SIZE(x)	((x) << 20)
-#define MEC1322_DMA_INC_DEV		BIT(17)
-#define MEC1322_DMA_INC_MEM		BIT(16)
-#define MEC1322_DMA_DEV(x)		((x) << 9)
-#define MEC1322_DMA_TO_DEV		BIT(8)
-#define MEC1322_DMA_DONE		BIT(2)
-#define MEC1322_DMA_RUN			BIT(0)
-
-
-/* IRQ Numbers */
-#define MEC1322_IRQ_I2C_0        0
-#define MEC1322_IRQ_I2C_1        1
-#define MEC1322_IRQ_I2C_2        2
-#define MEC1322_IRQ_I2C_3        3
-#define MEC1322_IRQ_DMA_0        4
-#define MEC1322_IRQ_DMA_1        5
-#define MEC1322_IRQ_DMA_2        6
-#define MEC1322_IRQ_DMA_3        7
-#define MEC1322_IRQ_DMA_4        8
-#define MEC1322_IRQ_DMA_5        9
-#define MEC1322_IRQ_DMA_6        10
-#define MEC1322_IRQ_DMA_7        11
-#define MEC1322_IRQ_LPC          12
-#define MEC1322_IRQ_UART         13
-#define MEC1322_IRQ_EMI          14
-#define MEC1322_IRQ_ACPIEC0_IBF  15
-#define MEC1322_IRQ_ACPIEC0_OBF  16
-#define MEC1322_IRQ_ACPIEC1_IBF  17
-#define MEC1322_IRQ_ACPIEC1_OBF  18
-#define MEC1322_IRQ_ACPIPM1_CTL  19
-#define MEC1322_IRQ_ACPIPM1_EN   20
-#define MEC1322_IRQ_ACPIPM1_STS  21
-#define MEC1322_IRQ_8042EM_OBF   22
-#define MEC1322_IRQ_8042EM_IBF   23
-#define MEC1322_IRQ_MAILBOX      24
-#define MEC1322_IRQ_PECI_HOST    25
-#define MEC1322_IRQ_TACH_0       26
-#define MEC1322_IRQ_TACH_1       27
-#define MEC1322_IRQ_ADC_SNGL     28
-#define MEC1322_IRQ_ADC_RPT      29
-#define MEC1322_IRQ_PS2_0        32
-#define MEC1322_IRQ_PS2_1        33
-#define MEC1322_IRQ_PS2_2        34
-#define MEC1322_IRQ_PS2_3        35
-#define MEC1322_IRQ_SPI0_TX      36
-#define MEC1322_IRQ_SPI0_RX      37
-#define MEC1322_IRQ_HTIMER       38
-#define MEC1322_IRQ_KSC_INT      39
-#define MEC1322_IRQ_MAILBOX_DATA 40
-#define MEC1322_IRQ_TIMER16_0    49
-#define MEC1322_IRQ_TIMER16_1    50
-#define MEC1322_IRQ_TIMER16_2    51
-#define MEC1322_IRQ_TIMER16_3    52
-#define MEC1322_IRQ_TIMER32_0    53
-#define MEC1322_IRQ_TIMER32_1    54
-#define MEC1322_IRQ_SPI1_TX      55
-#define MEC1322_IRQ_SPI1_RX      56
-#define MEC1322_IRQ_GIRQ8        57
-#define MEC1322_IRQ_GIRQ9        58
-#define MEC1322_IRQ_GIRQ10       59
-#define MEC1322_IRQ_GIRQ11       60
-#define MEC1322_IRQ_GIRQ12       61
-#define MEC1322_IRQ_GIRQ13       62
-#define MEC1322_IRQ_GIRQ14       63
-#define MEC1322_IRQ_GIRQ15       64
-#define MEC1322_IRQ_GIRQ16       65
-#define MEC1322_IRQ_GIRQ17       66
-#define MEC1322_IRQ_GIRQ18       67
-#define MEC1322_IRQ_GIRQ19       68
-#define MEC1322_IRQ_GIRQ20       69
-#define MEC1322_IRQ_GIRQ21       70
-#define MEC1322_IRQ_GIRQ22       71
-#define MEC1322_IRQ_GIRQ23       72
-#define MEC1322_IRQ_DMA_8        81
-#define MEC1322_IRQ_DMA_9        82
-#define MEC1322_IRQ_DMA_10       83
-#define MEC1322_IRQ_DMA_11       84
-#define MEC1322_IRQ_PWM_WDT3     85
-#define MEC1322_IRQ_RTC          91
-#define MEC1322_IRQ_RTC_ALARM    92
-
-/* Wake pin definitions, defined at board-level */
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
deleted file mode 100644
index 0c4174cecd..0000000000
--- a/chip/mec1322/spi.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI master module for MEC1322 */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-#include "hooks.h"
-#include "task.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-
-#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
-#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
-
-#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2)
-
-/* only regular image needs mutex, LFW does not have scheduling */
-/* TODO: Move SPI locking to common code */
-#ifndef LFW
-static struct mutex spi_mutex;
-#endif
-
-static const struct dma_option spi_rx_option[] = {
-	{
-		SPI_DMA_CHANNEL(0),
-		(void *)&MEC1322_SPI_RD(0),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-	{
-		SPI_DMA_CHANNEL(1),
-		(void *)&MEC1322_SPI_RD(1),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-};
-
-static int wait_byte(const int port)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	while ((MEC1322_SPI_SR(port) & 0x3) != 0x3) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static int spi_tx(const int port, const uint8_t *txdata, int txlen)
-{
-	int i;
-	int ret = EC_SUCCESS;
-	uint8_t unused __attribute__((unused)) = 0;
-
-	for (i = 0; i < txlen; ++i) {
-		MEC1322_SPI_TD(port) = txdata[i];
-		ret = wait_byte(port);
-		if (ret != EC_SUCCESS)
-			return ret;
-		unused = MEC1322_SPI_RD(port);
-	}
-
-	return ret;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int port = spi_device->port;
-	int ret = EC_SUCCESS;
-
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	ret = spi_tx(port, txdata, txlen);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable auto read */
-	MEC1322_SPI_CR(port) |= BIT(5);
-
-	if (rxlen != 0) {
-		dma_start_rx(&spi_rx_option[port], rxlen, rxdata);
-		MEC1322_SPI_TD(port) = 0;
-	}
-	return ret;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-	int ret = dma_wait(SPI_DMA_CHANNEL(port));
-	uint8_t unused __attribute__((unused)) = 0;
-
-	timestamp_t deadline;
-
-	/* Disable auto read */
-	MEC1322_SPI_CR(port) &= ~BIT(5);
-
-	deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
-	/* Wait for FIFO empty SPISR_TXBE */
-	while ((MEC1322_SPI_SR(port) & 0x01) != 0x1) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US);
-	}
-
-	dma_disable(SPI_DMA_CHANNEL(port));
-	dma_clear_isr(SPI_DMA_CHANNEL(port));
-	if (MEC1322_SPI_SR(port) & 0x2)
-		unused = MEC1322_SPI_RD(port);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return ret;
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int ret;
-
-#ifndef LFW
-	mutex_lock(&spi_mutex);
-#endif
-	ret = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	if (ret)
-		return ret;
-	ret = spi_transaction_flush(spi_device);
-
-#ifndef LFW
-	mutex_unlock(&spi_mutex);
-#endif
-	return ret;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-
-	if (enable) {
-		gpio_config_module(MODULE_SPI, 1);
-
-		/* Set enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) |= 0x1;
-
-		/* Set SPDIN to 0 -> Full duplex */
-		MEC1322_SPI_CR(port) &= ~(0x3 << 2);
-
-		/* Set CLKPOL, TCLKPH, RCLKPH to 0 */
-		MEC1322_SPI_CC(port) &= ~0x7;
-
-		/* Set LSBF to 0 -> MSB first */
-		MEC1322_SPI_CR(port) &= ~0x1;
-	} else {
-		/* Clear enable bit in SPI_AR */
-		MEC1322_SPI_AR(port) &= ~0x1;
-
-		gpio_config_module(MODULE_SPI, 0);
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
deleted file mode 100644
index 6e482d3a78..0000000000
--- a/chip/mec1322/system.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : MEC1322 hardware specific implementation */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "spi.h"
-
-/* Indices for hibernate data registers (RAM backed by VBAT) */
-enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratchpad */
-	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,               /* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,               /* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,               /* USB-PD2 saved port state */
-};
-
-static void check_reset_cause(void)
-{
-	uint32_t status = MEC1322_VBAT_STS;
-	uint32_t flags = 0;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				(MEC1322_PWR_RST_STS_VCC1 |
-				MEC1322_PWR_RST_STS_VBAT);
-
-	/* Clear the reset causes now that we've read them */
-	MEC1322_VBAT_STS |= status;
-	MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
-
-	/*
-	* BIT[6] determine VCC1 reset
-	*/
-	if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-
-	flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
-
-	if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	system_set_reset_flags(flags);
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-	/*
-	* Check reset cause here,
-	* gpio_pre_init is executed faster than system_pre_init
-	*/
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT) ||
-		(reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-void system_pre_init(void)
-{
-	/* Enable direct NVIC */
-	MEC1322_EC_INT_CTRL |= 1;
-
-	/* Disable ARM TRACE debug port */
-	MEC1322_EC_TRACE_EN &= ~1;
-
-	/* Deassert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL &= ~BIT(0);
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags;
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-noreturn
-void _system_reset(int flags, int wake_from_hibernate)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	if (wake_from_hibernate)
-		save_flags |= EC_RESET_FLAG_HIBERNATE;
-	else if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-	else
-		save_flags |= EC_RESET_FLAG_SOFT;
-
-	chip_save_reset_flags(save_flags);
-
-	/* Trigger watchdog in 1ms */
-	MEC1322_WDG_LOAD = 1;
-	MEC1322_WDG_CTL |= 1;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-void system_reset(int flags)
-{
-	_system_reset(flags, 0);
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "smsc";
-}
-
-const char *system_get_chip_name(void)
-{
-	switch (MEC1322_CHIP_DEV_ID) {
-	case 0x15:
-		return "mec1322";
-	default:
-		return "unknown";
-	}
-}
-
-static char to_hex(int x)
-{
-	if (x >= 0 && x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char buf[3];
-	uint8_t rev = MEC1322_CHIP_DEV_REV;
-
-	buf[0] = to_hex(rev / 16);
-	buf[1] = to_hex(rev & 0xf);
-	buf[2] = '\0';
-	return buf;
-}
-
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		return HIBDATA_INDEX_PD0;
-	case SYSTEM_BBRAM_IDX_PD1:
-		return HIBDATA_INDEX_PD1;
-	case SYSTEM_BBRAM_IDX_PD2:
-		return HIBDATA_INDEX_PD2;
-	default:
-		return -1;
-	}
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	*value = MEC1322_VBAT_RAM(hibdata);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int hibdata = bbram_idx_lookup(idx);
-
-	if (hibdata < 0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	MEC1322_VBAT_RAM(hibdata) = value;
-	return EC_SUCCESS;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value;
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Disable interrupts */
-	interrupt_disable();
-	for (i = 0; i <= 92; ++i) {
-		task_disable_irq(i);
-		task_clear_pending_irq(i);
-	}
-
-	for (i = 8; i <= 23; ++i)
-		MEC1322_INT_DISABLE(i) = 0xffffffff;
-
-	MEC1322_INT_BLK_DIS |= 0xffff00;
-
-	/* Power down ADC VREF */
-	MEC1322_EC_ADC_VREF_PD |= 1;
-
-	/* Assert nSIO_RESET */
-	MEC1322_PCR_PWR_RST_CTL |= 1;
-
-	/* Disable UART */
-	MEC1322_UART_ACT &= ~0x1;
-	MEC1322_LPC_ACT &= ~0x1;
-
-	/* Disable JTAG */
-	MEC1322_EC_JTAG_EN &= ~1;
-
-	/* Disable 32KHz clock */
-	MEC1322_VBAT_CE &= ~0x2;
-
-	/* Stop watchdog */
-	MEC1322_WDG_CTL &= ~1;
-
-	/* Stop timers */
-	MEC1322_TMR32_CTL(0) &= ~1;
-	MEC1322_TMR32_CTL(1) &= ~1;
-	MEC1322_TMR16_CTL(0) &= ~1;
-
-	/* Power down ADC */
-	MEC1322_ADC_CTRL &= ~1;
-
-	/* Disable blocks */
-	MEC1322_PCR_CHIP_SLP_EN |= 0x3;
-	MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
-	MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
-	MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
-	MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
-
-	/* Set sleep state */
-	MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
-	CPU_SCB_SYSCTRL |= 0x4;
-
-	/* Setup GPIOs for hibernate */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-#ifdef CONFIG_USB_PD_PORT_MAX_COUNT
-	/*
-	 * Leave USB-C charging enabled in hibernate, in order to
-	 * allow wake-on-plug. 5V enable must be pulled low.
-	 */
-	switch (board_get_usb_pd_port_count()) {
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	case 2:
-		gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 1
-	case 1:
-		gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
-		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
-		/* Fall through */
-#endif
-	case 0:
-		/* Nothing to do but break */
-		break;
-	default:
-		/* More ports needs to be defined */
-		ASSERT(false);
-		break;
-	}
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */
-
-	if (hibernate_wake_pins_used > 0) {
-		for (i = 0; i < hibernate_wake_pins_used; ++i) {
-			const enum gpio_signal pin = hibernate_wake_pins[i];
-
-			gpio_reset(pin);
-			gpio_enable_interrupt(pin);
-		}
-
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_GIRQ8);
-		task_enable_irq(MEC1322_IRQ_GIRQ9);
-		task_enable_irq(MEC1322_IRQ_GIRQ10);
-		task_enable_irq(MEC1322_IRQ_GIRQ11);
-		task_enable_irq(MEC1322_IRQ_GIRQ20);
-	}
-
-	if (seconds || microseconds) {
-		MEC1322_INT_BLK_EN |= BIT(17);
-		MEC1322_INT_ENABLE(17) |= BIT(20);
-		interrupt_enable();
-		task_enable_irq(MEC1322_IRQ_HTIMER);
-		if (seconds > 2) {
-			ASSERT(seconds <= 0xffff / 8);
-			MEC1322_HTIMER_CONTROL = 1;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 8 + microseconds / 125000);
-		} else {
-			MEC1322_HTIMER_CONTROL = 0;
-			MEC1322_HTIMER_PRELOAD =
-				(seconds * 1000000 + microseconds) * 2 / 71;
-		}
-	}
-
-	asm("wfi");
-
-	/* Use 48MHz clock to speed through wake-up */
-	MEC1322_PCR_PROC_CLK_CTL = 1;
-
-	/* Reboot */
-	_system_reset(0, 1);
-
-	/* We should never get here. */
-	while (1)
-		;
-}
-
-void htimer_interrupt(void)
-{
-	/* Time to wake up */
-}
-DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1);
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX);
-}
-
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
-
-	return *(lfw_vector + 1);
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
-}
diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
deleted file mode 100644
index 2c607d0b72..0000000000
--- a/chip/mec1322/uart.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for MEC1322 */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "lpc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define TX_FIFO_SIZE 16
-
-static int init_done;
-static int tx_fifo_used;
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (MEC1322_UART_IER & BIT(1))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	MEC1322_UART_IER |= BIT(1);
-	task_trigger_irq(MEC1322_IRQ_UART);
-}
-
-void uart_tx_stop(void)
-{
-	MEC1322_UART_IER &= ~BIT(1);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	/* Wait for transmit FIFO empty */
-	while (!(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * We have no indication of free space in transmit FIFO. To work around
-	 * this, we check transmit FIFO empty bit every 16 characters written.
-	 */
-	return tx_fifo_used != 0 || (MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_tx_in_progress(void)
-{
-	/* return 0: FIFO is empty, 1: FIFO NOT Empty */
-	return !(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY);
-}
-
-int uart_rx_available(void)
-{
-	return MEC1322_UART_LSR & BIT(0);
-}
-
-void uart_write_char(char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uart_tx_ready())
-		;
-
-	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
-	MEC1322_UART_TB = c;
-}
-
-int uart_read_char(void)
-{
-	return MEC1322_UART_RB;
-}
-
-static void uart_clear_rx_fifo(int channel)
-{
-	MEC1322_UART_FCR = BIT(0) | BIT(1);
-}
-
-/**
- * Interrupt handler for UART
- */
-void uart_ec_interrupt(void)
-{
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1);
-
-void uart_init(void)
-{
-	/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
-	MEC1322_UART_CFG &= ~BIT(1);
-
-	/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
-
-	/* Set CLK_SRC = 0 */
-	MEC1322_UART_CFG &= ~BIT(0);
-
-	/* Set DLAB = 1 */
-	MEC1322_UART_LCR |= BIT(7);
-
-	/* PBRG0/PBRG1 */
-	MEC1322_UART_PBRG0 = 1;
-	MEC1322_UART_PBRG1 = 0;
-
-	/* Set DLAB = 0 */
-	MEC1322_UART_LCR &= ~BIT(7);
-
-	/* Set word length to 8-bit */
-	MEC1322_UART_LCR |= BIT(0) | BIT(1);
-
-	/* Enable FIFO */
-	MEC1322_UART_FCR = BIT(0);
-
-	/* Activate UART */
-	MEC1322_UART_ACT |= BIT(0);
-
-	/*
-	clock_enable_peripheral(CGC_OFFSET_UART, mask,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);*/
-
-	gpio_config_module(MODULE_UART, 1);
-
-	/*
-	 * Enable interrupts for UART0.
-	 */
-	uart_clear_rx_fifo(0);
-	MEC1322_UART_IER |= BIT(0);
-	MEC1322_UART_MCR |= BIT(3);
-	MEC1322_INT_ENABLE(15) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(15);
-	task_enable_irq(MEC1322_IRQ_UART);
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void uart_enter_dsleep(void)
-{
-	/* Disable the UART interrupt. */
-	task_disable_irq(MEC1322_IRQ_UART);  /* NVIC interrupt for UART=13 */
-
-	/*
-	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
-	 * with the flags defined in the gpio.inc file.
-	 */
-	gpio_reset(GPIO_UART0_RX);
-
-	/* power-down/de-activate UART0 */
-	MEC1322_UART_ACT &= ~BIT(0);
-
-	/* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */
-	MEC1322_INT_SOURCE(8) = (1<<18);
-
-	/* Enable GPIO interrupts on the UART0 RX pin. */
-	gpio_enable_interrupt(GPIO_UART0_RX);
-}
-
-
-void uart_exit_dsleep(void)
-{
-	/*
-	 * If the UART0 RX GPIO interrupt has not fired, then no edge has been
-	 * detected. Disable the GPIO interrupt so that switching the pin over
-	 * to a UART pin doesn't inadvertently cause a GPIO edge interrupt.
-	 * Note: we can't disable this interrupt if it has already fired
-	 * because then the IRQ will not run at all.
-	 */
-	if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */
-		gpio_disable_interrupt(GPIO_UART0_RX);
-
-	/* Configure UART0 pins for use in UART peripheral. */
-	gpio_config_module(MODULE_UART, 1);
-
-	/* Clear pending interrupts on UART peripheral and enable interrupts. */
-	uart_clear_rx_fifo(0);
-	task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */
-
-	/* power-up/activate UART0 */
-	MEC1322_UART_ACT |= BIT(0);
-}
-
-void uart_deepsleep_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Activity seen on UART RX pin while UART was disabled for deep sleep.
-	 * The console won't see that character because the UART is disabled,
-	 * so we need to inform the clock module of UART activity ourselves.
-	 */
-	clock_refresh_console_in_use();
-
-	/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
-	gpio_disable_interrupt(GPIO_UART0_RX);
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py
deleted file mode 100755
index 9783ffb2d5..0000000000
--- a/chip/mec1322/util/pack_ec.py
+++ /dev/null
@@ -1,248 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script to pack EC binary into SPI flash image for MEC1322
-# Based on MEC1322_ROM_Doc_Rev0.5.pdf.
-
-import argparse
-import hashlib
-import os
-import struct
-import subprocess
-import tempfile
-
-LOAD_ADDR = 0x100000
-HEADER_SIZE = 0x140
-SPI_CLOCK_LIST = [48, 24, 12, 8]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b]
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
-
-def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
-
-def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file,offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
-
-def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
-
-def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
-
-def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
-
-def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
-
-def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
-
-def BuildHeader(args, payload_len, rorofile):
-  # Identifier and header version
-  header = bytearray(b'CSMS\0')
-
-  PadZeroTo(header, 0x6)
-  header.append(GetSpiClockParameter(args))
-  header.append(GetSpiReadCmdParameter(args))
-
-  header.extend(struct.pack('<I', LOAD_ADDR))
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  header.extend(struct.pack('<I', args.payload_offset))
-
-  exp, modulus = GetPublicKey(args.payload_key)
-  PadZeroTo(header, 0x20)
-  header.extend(exp)
-  PadZeroTo(header, 0x30)
-  header.extend(modulus)
-  PadZeroTo(header, HEADER_SIZE)
-
-  return header
-
-def SignByteArray(data, pem_file):
-  hash_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  sign_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  try:
-      with open(hash_file, 'wb') as f:
-        hasher = hashlib.sha256()
-        hasher.update(data)
-        f.write(hasher.digest())
-      subprocess.run(['openssl', 'rsautl', '-sign', '-inkey', pem_file,
-                      '-keyform', 'PEM', '-in', hash_file, '-out', sign_file],
-                     check=True)
-      with open(sign_file, 'rb') as f:
-        signed = f.read()
-        return bytearray(reversed(signed))
-  finally:
-    os.remove(hash_file)
-    os.remove(sign_file)
-
-def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  if args.chip_select != 0:
-    tag[2] |= 0x80
-  tag.append(Crc8(0, tag))
-  return tag
-
-def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """TODO:Clean up to get rid of Temp file and just use memory
-  to save data"""
-  """Create a temp file with the
-  first image_size bytes from the rorw file and the
-  bytes from the loader_file appended
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1:
-    pro = fin1.read()
-  fo.write(pro)
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-  fo.write(ro)
-  fo.close()
-  return fo.name
-
-def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-                      help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-                      metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--header_key",
-                      help="PEM key file for signing header",
-                      default="rsakey_sign_header.pem")
-  parser.add_argument("--payload_key",
-                      help="PEM key file for signing payload",
-                      default="rsakey_sign_payload.pem")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in MB",
-                      default=4)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x170000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the header",
-                      default=0x240)
-  parser.add_argument("-r", "--rwpayload_loc", type=int,
-                      help="The offset of payload from the header",
-                      default=0x190000)
-  parser.add_argument("-z", "--romstart", type=int,
-                      help="The first location to output of the rom",
-                      default=0)
-  parser.add_argument("-c", "--chip_select", type=int,
-                      help="Chip select signal to use, either 0 or 1.",
-                      default=0)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image.",
-                      default=(96 * 1024))
-  return parser.parse_args()
-
-def main():
-  args = parseargs()
-
-  spi_size = args.spi_size * 1024
-  args.header_loc = spi_size - (128 * 1024)
-  args.rwpayload_loc = spi_size - (256 * 1024)
-  args.romstart = spi_size - (256 * 1024)
-
-  spi_list = []
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  payload_signature = SignByteArray(payload, args.payload_key)
-  header = BuildHeader(args, payload_len, rorofile)
-  header_signature = SignByteArray(header, args.header_key)
-  tag = BuildTag(args)
-  # truncate the RW to 128k
-  payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024]
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list.append((args.header_loc, header, "header"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload, "payload"))
-  spi_list.append((args.header_loc + args.payload_offset + payload_len,
-                   payload_signature, "payload_signature"))
-  spi_list.append((spi_size - 256, tag, "tag"))
-  spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw"))
-
-
-  spi_list = sorted(spi_list)
-
-  with open(args.output, 'wb') as f:
-    addr = args.romstart
-    for s in spi_list:
-      assert addr <= s[0]
-      if addr < s[0]:
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-      f.write(s[1])
-      addr += len(s[1])
-    if addr < spi_size:
-      f.write(b'\xff' * (spi_size - addr))
-
-if __name__ == '__main__':
-  main()
diff --git a/chip/mec1322/util/rsakey_sign_header.pem b/chip/mec1322/util/rsakey_sign_header.pem
deleted file mode 100644
index 37799ebbec..0000000000
--- a/chip/mec1322/util/rsakey_sign_header.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQCd0knJ+sVzkO40
-g7VguqpqrmwqgYPfgq3m7GHGitWgxjM/JDpKaOvq4G9O+yYUD/75V5GZJkRY0iE8
-MJCCvSkyoFHcCP0jvma9G/c13wXfLPGUunrJnV+Wzwy5+S1MXdax532gK9qeUmOB
-HpIttkFRl3qhVHu9to2dbsx1S/AIA0GIPAINkcZxfRCAcheIoqK/oMqse+EDS9Zm
-6frha9oS1+iRlqMPYKrOgWTKnkY3H/4M/HFj90hVzxun3qQj0mo3EdYoSrbCnyjG
-JNjnuCdSEODmG5+FCTVWCfl/AolYmOWjMfCnfX7/HlfhOY+fOR91FKrgOjWHHf3a
-0FhdUZDNAgMBAAECggEBAJKea6j2jXu42GP3PIk5wdrMYnb2zeHXEOJpFskR8Dem
-CrQNXw4D/bC+gwo4Lv8SgUl6PiyurW5rAS9e2tJrFBwRbxthSnNrjxz/HyJwKI9W
-vLT0reAikUyU3Hjl8lxxDWVH76DfPQI6/nBVS26mVHaNqQK6bx8nutbYuZ/7RWra
-zatdjrl29D0E/xTva0S4AUPI7DmflwS6YbfVlTsyhnwphaEwD7eCDhD9h4nGQG8z
-0WKDN2X1F7CmjrK9fy7SCHO9SKc3WNSjp2Dc0ImF2k72Mfw5jtOs81lczktztPy0
-gv4x6Tg0ws4Et9eI6Ub80tAZ+wQ5Vj+wzExMOp4K5KECgYEA0jz5IsRmie6y/WRG
-6dI98nnyLoISIQue8xOA5J/OUyYfHn9CgJvGslRVg2mmSQ9GPkaMIN0dADvB6Tsh
-XelAZZjnAo8pSyahz3OdcdgP6xksMjtKReXiLqu0ntfQS42nQDYNvRd2/clrYYRN
-SlijT53QMqI4DSMz+0rLqUwvRskCgYEAwCyEEJ1Z/CI2ONN1tIEnJSuzZRYxlwNL
-mVXx03ZSVi+L2MOMJjiCoeUZ/MVSacW+Elg6aU3U1GdOhNfQaPZJNqISACtm314Y
-Xi9bMXegyQp3uBRnEah82ejm8hloOAOKZNgbqgt9o6FDrsccw3udIgzsgPY4koUK
-1fNrDPJ5x+UCgYBwlEH8whr+hZnHYqkukGynqXFsQi6fD3AATlNZGdIMaH+FfzQH
-VmNiHxLjmfF3cfx1YKWs+3qKI3XFBOrrNPpM7UHW9v5vxbIkOo725XIwvHwUMfel
-0mH6B+ximsJpkuMa2VcmCKipYfBkecpBo5FgEuvoEUHelxlA2V6Ru8AdMQKBgQC/
-uanoiZQFIHzIJPABrfjH9Nl9uK6w4vDBgiVJu3pZ0gXLtQxV9Xse2dsbfCHEtSv0
-UWG1PZlgb9C+aDHdBhn1D6y1zpdLsizNiqGIsLkQ2gim9nP+AgLNxLbkQsTfXWjt
-Q04WUHCAl5tW+/+OZ/1Uw2ARKZU3WNR+r+PVfvRQoQKBgQCjksWLe3Zx2yxnUenz
-vaY09UTt42rawbUkm+xpNzOt7K1TudRODe444XG9fFgkNa5HPiAENoZ91Jv223x8
-Fi2SjfGA6/r/J1ash4cDcJLogTEP27YyJyhwXZFKtjfFeD3e2hvcMFMDG4EBHHXd
-Bv/r6+6E+f30Y4bN3ZgK/rN6Tg==
------END PRIVATE KEY-----
diff --git a/chip/mec1322/util/rsakey_sign_payload.pem b/chip/mec1322/util/rsakey_sign_payload.pem
deleted file mode 100644
index 6845097749..0000000000
--- a/chip/mec1322/util/rsakey_sign_payload.pem
+++ /dev/null
@@ -1,28 +0,0 @@
------BEGIN PRIVATE KEY-----
-MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDQaeNJ6+a/KXhs
-/0Xa2coG+4d+pc+4qs4O/6caxAtzr1YP155C4QxqfZw0DETreK7K/kgSgOJ6Q1gW
-Yo88Fb4foxVYJbV2Bb+mdNlaHP/o6TrvBmqdsIjP5u1FwtmjquaewL2E3T4rHCXl
-QgM7AQXAFzKt2HeaMeHvC2t+x/AganhfztOpqhGTL6lHiLC55SPNkWCb3GokotbL
-Ul7q+wLSTpKS0vNuigjGVBVuV7YrwWhehOoLuV5FDMXHlMTemYH6+V5j78ZtSrXm
-0RmKAKXoO+HbKbgALICUw5kzxXLSAoHx2rXLlou9I00olxsWir1lokxaWa1La3wA
-pr214pxXAgMBAAECggEAdsXxrz4OeaEDrXJpeAioNwR/unB6ie5lkmyl6f4R3LLu
-5AZofgrNTZ8aNxtK57sWOj9iCZGEAFOCzvcKVB68BEGnt11+Ja2vBAkRmWZvfWf1
-myTX+9gQkBM144zhBYIu/ggvuZlwhZb8DcRqHOU/RrKxwhtcRfbpoJasg0skkQO0
-bU2hwSu4kM+T2diyXp4V1PR4vrxZPNQ+B8sWxWKJs58+3NdWswwe9NcFQla0QTFz
-7MIlMJNlJgTXjSYC8TjDlBlevwE5HoikpfSSvFr4uouyfpfWBxNFd8Tm/yFSTUqY
-XO3oyU/NLK+BN7Sxj6Cs1Fx65yhMCmsqGQqCNOz2OQKBgQD4gIF6vVduyKfPV3EE
-4lhFktlFRXeR+z9LXpGth3vwNN0XpPql1jr8hYPQqpSKefZRF5r8hLjt2ZaLDbnb
-iVYwHxbXRuF5P6qsaSy1uVYG4og5LV5ddSBzf+/MhDInQk/O5tdvOrgQfcJzRJRg
-MSx5uzs66r8/AFKCVTB/ptNgzQKBgQDWs7qqaHNHGRRfegRhwkkDvhRAMQKWsgL7
-kTWw/qW+b8mRYhCC4JvbU+OeFkf5kejGpFgDuvB4eH+rsPRVU8jSWZXrMKjGdZN1
-T6fFa5vz1VsRNhiVU3F2jfXTY5t7qQ18jEoMQxGxdGJy52Py+3N34ZWNS4cifLNS
-rYjZnQmhswKBgD3rd1foGgMmyHmnpie7ZpdfcfgKyTJ80larZ80/dyhxY63ik/oC
-mYwWkLPL7Vtb7H5kTWAiihnqH9LiRq9nVyyCcqSNqt0VeiefxV46oi7w/1SP83WC
-G+XruQrS3dRed5hseL3kebzSOUOTkQ0u85AZkTarC6BdKjIDnCQSo5T5AoGAKNep
-087o1waTVJJOkRY3c4nOKmPoXShh3t9BunjGqNJ1Ir3n7C20GGX9783HRVeXU2ph
-/9uo8RHjH5Ma97xngHRgS4xHHvGw6mkLvkd5NEpK95w10vo7pFTfBaZ2JnEDSsUZ
-NPnxPLOqIreX0No6nfyAyY8rlsjoB/tRBCyWb3cCgYEAgzJCllzahDvgCbmjI9Km
-h7mUVc5U2fQR5B/WRa5iTSlQd+O4TXna7ZCxKDyYlesSBAiKanX0669Iri6cu4S6
-gMc7MJmm3VrnZGXoukSv3Zyot+hkaFrZTrXAIQiuYDK6YC5OK7kqM+DqtJOWUsfg
-itdiqPKeYtViDQkxqJ1nkSw=
------END PRIVATE KEY-----
diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c
deleted file mode 100644
index ad93fb1240..0000000000
--- a/chip/mec1322/watchdog.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	MEC1322_WDG_KICK = 1;
-
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Reload the auxiliary timer */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CTL(0) |= BIT(5);
-#endif
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#ifdef CONFIG_WATCHDOG_HELP
-	uint32_t val;
-
-	/*
-	 * Watchdog does not warn us before expiring. Let's use a 16-bit
-	 * timer as an auxiliary timer.
-	 */
-
-	/* Stop the auxiliary timer if it's running */
-	MEC1322_TMR16_CTL(0) &= ~BIT(5);
-
-	/* Enable auxiliary timer */
-	MEC1322_TMR16_CTL(0) |= BIT(0);
-
-	val = MEC1322_TMR16_CTL(0);
-
-	/* Pre-scale = 48000 -> 1kHz -> Period = 1ms */
-	val = (val & 0xffff) | (47999 << 16);
-
-	/* No auto restart */
-	val &= ~BIT(3);
-
-	/* Count down */
-	val &= ~BIT(2);
-
-	MEC1322_TMR16_CTL(0) = val;
-
-	/* Enable interrupt from auxiliary timer */
-	MEC1322_TMR16_IEN(0) |= 1;
-	task_enable_irq(MEC1322_IRQ_TIMER16_0);
-	MEC1322_INT_ENABLE(23) |= BIT(0);
-	MEC1322_INT_BLK_EN |= BIT(23);
-
-	/* Load and start the auxiliary timer */
-	MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
-	MEC1322_TMR16_CNT(0) |= BIT(5);
-#endif
-
-	/* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */
-	MEC1322_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007;
-
-	/* Start watchdog */
-	MEC1322_WDG_CTL |= 1;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* Clear status */
-	MEC1322_TMR16_STS(0) |= 1;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) __attribute__((naked));
-void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveninently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the
-						 highest priority */
-#endif
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
deleted file mode 100644
index 3e8f63b5a2..0000000000
--- a/chip/mt_scp/build.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# SCP specific files build
-#
-
-# Required chip modules
-chip-y=
-
-CPPFLAGS+=-Ichip/$(CHIP)/$(CHIP_VARIANT)
-dirs-y+=chip/$(CHIP)/$(CHIP_VARIANT)
-# Each chip variant can provide specific build.mk if any
--include chip/$(CHIP)/$(CHIP_VARIANT)/build.mk
-
-ifeq ($(CHIP_VARIANT),$(filter $(CHIP_VARIANT),mt8192 mt8195))
-CPPFLAGS+=-Ichip/$(CHIP)/rv32i_common
-dirs-y+=chip/$(CHIP)/rv32i_common
-include chip/$(CHIP)/rv32i_common/build.mk
-endif
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
deleted file mode 100644
index 112920a4c6..0000000000
--- a/chip/mt_scp/config_chip.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CHIP_VARIANT_MT8183
-#include "mt8183/config_chip.h"
-#endif
-
-#if defined(CHIP_VARIANT_MT8192) || defined(CHIP_VARIANT_MT8195)
-#include "rv32i_common/config_chip.h"
-#endif
diff --git a/chip/mt_scp/mt8183/audio_codec_wov.c b/chip/mt_scp/mt8183/audio_codec_wov.c
deleted file mode 100644
index 0a4684f909..0000000000
--- a/chip/mt_scp/mt8183/audio_codec_wov.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "hooks.h"
-#include "memmap.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* VIF FIFO irq is triggered above this level */
-#define WOV_TRIGGER_LEVEL 160
-
-int audio_codec_wov_enable_notifier(void)
-{
-	SCP_VIF_FIFO_DATA_THRE = WOV_TRIGGER_LEVEL + 1;
-	SCP_VIF_FIFO_EN |= VIF_FIFO_IRQ_EN;
-
-	task_enable_irq(SCP_IRQ_MAD_FIFO);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_disable_notifier(void)
-{
-	SCP_VIF_FIFO_EN &= ~VIF_FIFO_IRQ_EN;
-
-	task_disable_irq(SCP_IRQ_MAD_FIFO);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_enable(void)
-{
-	SCP_VIF_FIFO_EN = 0;
-
-	SCP_RXIF_CFG0 = (RXIF_CFG0_RESET_VAL & ~RXIF_RGDL2_MASK) |
-			RXIF_RGDL2_DMIC_16K;
-	SCP_RXIF_CFG1 = RXIF_CFG1_RESET_VAL;
-
-	SCP_VIF_FIFO_EN |= VIF_FIFO_RSTN;
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_wov_disable(void)
-{
-	SCP_VIF_FIFO_EN = 0;
-
-	return EC_SUCCESS;
-}
-
-static size_t wov_fifo_level(void)
-{
-	uint32_t fifo_status = SCP_VIF_FIFO_STATUS;
-
-	if (!(fifo_status & VIF_FIFO_VALID))
-		return 0;
-
-	if (fifo_status & VIF_FIFO_FULL)
-		return VIF_FIFO_MAX;
-
-	return VIF_FIFO_LEVEL(fifo_status);
-}
-
-int32_t audio_codec_wov_read(void *buf, uint32_t count)
-{
-	int16_t *out = buf;
-	uint8_t gain = 1;
-
-	if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
-		audio_codec_dmic_get_gain_idx(0, &gain);
-
-	count >>= 1;
-
-	while (count-- && wov_fifo_level()) {
-		if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
-			*out++ = audio_codec_s16_scale_and_clip(
-					SCP_VIF_FIFO_DATA, gain);
-		else
-			*out++ = SCP_VIF_FIFO_DATA;
-	}
-
-	return (void *)out - buf;
-}
-
-static void wov_fifo_interrupt_handler(void)
-{
-#ifdef HAS_TASK_WOV
-	task_wake(TASK_ID_WOV);
-#endif
-
-	audio_codec_wov_disable_notifier();
-
-	/* Read to clear */
-	SCP_VIF_FIFO_IRQ_STATUS;
-}
-DECLARE_IRQ(SCP_IRQ_MAD_FIFO, wov_fifo_interrupt_handler, 2);
-
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr)
-{
-	return memmap_ap_to_scp(ap_addr, ec_addr);
-}
diff --git a/chip/mt_scp/mt8183/build.mk b/chip/mt_scp/mt8183/build.mk
deleted file mode 100644
index 206563a7c5..0000000000
--- a/chip/mt_scp/mt8183/build.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/gpio.o
-chip-y+=$(CHIP_VARIANT)/memmap.o
-chip-y+=$(CHIP_VARIANT)/system.o
-chip-y+=$(CHIP_VARIANT)/uart.o
-
-# Optional chip modules
-chip-$(CONFIG_AUDIO_CODEC_WOV)+=$(CHIP_VARIANT)/audio_codec_wov.o
-chip-$(CONFIG_COMMON_TIMER)+=$(CHIP_VARIANT)/hrtimer.o
-chip-$(CONFIG_I2C)+=$(CHIP_VARIANT)/i2c.o
-chip-$(CONFIG_IPI)+=$(CHIP_VARIANT)/ipi.o $(CHIP_VARIANT)/ipi_table.o
-chip-$(CONFIG_SPI)+=$(CHIP_VARIANT)/spi.o
-chip-$(CONFIG_WATCHDOG)+=$(CHIP_VARIANT)/watchdog.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RO/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
-$(out)/RW/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
-
-ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
-HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
-ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
-LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
-HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
-endif
-endif
diff --git a/chip/mt_scp/mt8183/clock.c b/chip/mt_scp/mt8183/clock.c
deleted file mode 100644
index 3029a00a01..0000000000
--- a/chip/mt_scp/mt8183/clock.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
-#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
-
-void clock_init(void)
-{
-	/* Set VREQ to HW mode */
-	SCP_CPU_VREQ = CPU_VREQ_HW_MODE;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* Set DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Initialize 26MHz system clock counter reset value to 1. */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
-	/* Initialize high frequency ULPOSC counter reset value to 1. */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
-	/* Initialize sleep mode control VREQ counter. */
-	SCP_CLK_SLEEP_CTRL =
-		(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
-
-	/* Set normal wake clock */
-	SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
-
-	/* Enable fast wakeup support */
-	SCP_CLK_SLEEP = 0;
-	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
-			  HIGH_FINAL_VAL_DEFAULT;
-	SCP_FAST_WAKE_CNT_END =
-		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
-		FAST_WAKE_CNT_END_DEFAULT;
-
-	/* Set slow wake clock */
-	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
-			WAKE_CKSW_SEL_SLOW_DEFAULT;
-
-	/* Select CLK_HIGH as wakeup clock */
-	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
-			    ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
-			   CKSW_SEL_SLOW_ULPOSC2_CLK;
-
-	/*
-	 * Set legacy wakeup
-	 *   - disable SPM sleep control
-	 *   - disable SCP sleep mode
-	 */
-	SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE);
-
-	task_enable_irq(SCP_IRQ_CLOCK);
-	task_enable_irq(SCP_IRQ_CLOCK2);
-}
-
-static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali)
-{
-	uint32_t val;
-
-	/* Clear all bits */
-	val = 0;
-	/* Enable CP */
-	val |= OSC_CP_EN;
-	/* Set div */
-	val |= osc_div << 17;
-	/* F-band = 0, I-band = 4 */
-	val |= 4 << 6;
-	/* Set calibration */
-	val |= osc_cali;
-	/* Set control register 1 */
-	AP_ULPOSC_CON02(osc) = val;
-	/* Set control register 2, enable div2 */
-	AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN;
-}
-
-static inline void busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 */
-	volatile int i = usec * 28;
-
-	while (i--)
-		;
-}
-
-static unsigned int scp_measure_ulposc_freq(int osc)
-{
-	unsigned int result = 0;
-	int cnt;
-
-	/* Before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* Select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* Set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* Enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* Trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt; cnt--) {
-		busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* Disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-	return result;
-}
-
-static inline int signum(int v)
-{
-	return (v > 0) - (v < 0);
-}
-
-static inline int abs(int v)
-{
-	return (v >= 0) ? v : -v;
-}
-
-static int scp_ulposc_config_measure(int osc, int div, int cali)
-{
-	int freq;
-
-	scp_ulposc_config(osc, div, cali);
-	freq = scp_measure_ulposc_freq(osc);
-	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n",
-		osc + 1, div, cali, freq,
-		freq * 26 * 1000 / 1024);
-
-	return freq;
-}
-
-/**
- * Calibrate ULPOSC to target frequency.
- *
- * @param osc           0:ULPOSC1, 1:ULPOSC2
- * @param target_mhz    Target frequency to set
- * @return              Frequency counter output
- *
- */
-static int scp_calibrate_ulposc(int osc, int target_mhz)
-{
-	int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
-	struct ulposc {
-		int div;        /* frequency divisor/multiplier */
-		int cali;       /* variable resistor calibrator */
-		int freq;       /* frequency counter measure result */
-	} curr, prev = {0};
-	enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
-	int param, param_max;
-
-	curr.div = ULPOSC_DIV_MAX / 2;
-	curr.cali = ULPOSC_CALI_MAX / 2;
-
-	param = curr.div;
-	param_max = ULPOSC_DIV_MAX;
-
-	/*
-	 * In the loop below, linear search closest div value to get desired
-	 * frequency counter value. Then adjust cali to get a better result.
-	 * Note that this doesn't give optimal output frequency, but it's
-	 * usually close enough.
-	 * TODO(b:120176040): See if we can efficiently calibrate the clock with
-	 * more precision by exploring more of the cali/div space.
-	 *
-	 * The frequency function follows. Note that f is positively correlated
-	 * with both div and cali:
-	 * f(div, cali) = k1 * (div + k2) / R(cali) * C
-	 * Where:
-	 *   R(cali) = k3 / (1 + k4 * (cali - k4))
-	 */
-	while (1) {
-		curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali);
-
-		if (!curr.freq)
-			return 0;
-
-		/*
-		 * If previous and current are on either side of the desired
-		 * frequency, pick the closest one.
-		 */
-		if (prev.freq && signum(target_freq - curr.freq) !=
-				 signum(target_freq - prev.freq)) {
-			if (abs(target_freq - prev.freq) <
-					abs(target_freq - curr.freq))
-				curr = prev;
-
-			if (stage == STAGE_CALI)
-				break;
-
-			/* Switch to optimizing cali */
-			stage = STAGE_CALI;
-			param = curr.cali;
-			param_max = ULPOSC_CALI_MAX;
-		}
-
-		prev = curr;
-		param += signum(target_freq - curr.freq);
-
-		if (param < 0 || param >= param_max)
-			return 0;
-
-		if (stage == STAGE_DIV)
-			curr.div = param;
-		else
-			curr.cali = param;
-	}
-
-	/*
-	 * It's possible we end up using prev, so reset the configuration and
-	 * measure again.
-	 */
-	return scp_ulposc_config_measure(osc, curr.div, curr.cali);
-}
-
-static void scp_clock_high_enable(int osc)
-{
-	/* Enable high speed clock */
-	SCP_CLK_EN |= EN_CLK_HIGH;
-
-	switch (osc) {
-	case 0:
-		/* After 25ms, enable ULPOSC */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_EN |= CG_CLK_HIGH;
-		break;
-	case 1:
-		/* Turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* After 25ms, turn on ULPOSC2 high core clock gate */
-		busy_udelay(25 * MSEC);
-		SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG;
-		break;
-	default:
-		break;
-	}
-}
-
-void scp_use_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV2;
-
-	SCP_CLK_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV1;
-}
-
-void scp_enable_clock(void)
-{
-	/* Select default CPU clock */
-	scp_use_clock(SCP_CLK_26M);
-
-	/* VREQ */
-	SCP_CPU_VREQ = 0x10001;
-	SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ;
-
-	/* DDREN auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* Set settle time */
-	SCP_CLK_SYS_VAL = 1;  /* System clock */
-	SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
-	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
-
-	/* Disable slow wake */
-	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
-	/* Disable SPM sleep control, disable sleep mode */
-	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
-
-	/* Turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-	scp_ulposc_config(0, 12, 32);
-	scp_clock_high_enable(0); /* Turn on ULPOSC1 */
-	scp_ulposc_config(1, 16, 32);
-	scp_clock_high_enable(1); /* Turn on ULPOSC2 */
-
-	/* Calibrate ULPOSC */
-	scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-	scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-
-	/* Select ULPOSC2 high speed CPU clock */
-	scp_use_clock(SCP_CLK_ULPOSC2);
-
-	/* Enable default clock gate */
-	SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-			CG_I2C_M | CG_MAD_M | CG_AP2P_M;
-
-	/* Select pwrap_ulposc */
-	AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16;
-
-	/* Enable pwrap_ulposc clock gate */
-	AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG;
-}
-
-DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3);
-void clock_control_irq(void)
-{
-	/* Read ack CLK_IRQ */
-	(SCP_CLK_IRQ_ACK);
-	task_clear_pending_irq(SCP_IRQ_CLOCK);
-}
-
-DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3);
-void clock_fast_wakeup_irq(void)
-{
-	/* Ack fast wakeup */
-	SCP_SLEEP_IRQ2 = 1;
-	task_clear_pending_irq(SCP_IRQ_CLOCK2);
-}
-
-/* Console command */
-int command_ulposc(int argc, char *argv[])
-{
-	if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
-		scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
-		scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ);
-	}
-
-	/* SCP clock meter counts every (26MHz / 1024) tick */
-	ccprintf("ULPOSC1 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(0) * 26 * 1000 / 1024);
-	ccprintf("ULPOSC2 frequency: %u kHz\n",
-		 scp_measure_ulposc_freq(1) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]",
-			"Calibrate ULPOSC frequency");
diff --git a/chip/mt_scp/mt8183/clock_chip.h b/chip/mt_scp/mt8183/clock_chip.h
deleted file mode 100644
index a16bf2e54e..0000000000
--- a/chip/mt_scp/mt8183/clock_chip.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-#include "common.h"
-#include "registers.h"
-
-/* Default ULPOSC clock speed in MHz */
-#ifndef ULPOSC1_CLOCK_MHZ
-#define ULPOSC1_CLOCK_MHZ 240
-#endif
-#ifndef ULPOSC2_CLOCK_MHZ
-#define ULPOSC2_CLOCK_MHZ 330
-#endif
-
-void scp_enable_clock(void);
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SEL_SYS_26M,
-	SCP_CLK_32K = CLK_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SEL_ULPOSC_2,
-	SCP_CLK_ULPOSC1 = CLK_SEL_ULPOSC_1,
-};
-
-/* Switches to use 'src' clock */
-void scp_use_clock(enum scp_clock_source src);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/mt_scp/mt8183/config_chip.h b/chip/mt_scp/mt8183/config_chip.h
deleted file mode 100644
index e0710a908b..0000000000
--- a/chip/mt_scp/mt8183/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default to UART 2 (AP UART) for EC console */
-#define CONFIG_UART_CONSOLE 2
-
-/* Number of IRQ vectors */
-#define CONFIG_IRQ_COUNT 56
-
-/*
- * Number of EINT can be 0 ~ 160. Change this to conditional macro
- * on adding other variants.
- */
-#define MAX_NUM_EINT 8
-#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_MAPPED_STORAGE_BASE 0
-/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
-#define CONFIG_MPU
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 256
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/mt8183/gpio.c b/chip/mt_scp/mt8183/gpio.c
deleted file mode 100644
index a4896aae72..0000000000
--- a/chip/mt_scp/mt8183/gpio.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	int bit, mode_reg_index, shift;
-	uint32_t mode_bits, mode_mask;
-
-	/* Up to 8 alt functions per port */
-	if (func > GPIO_ALT_FUNC_7)
-		return;
-
-	if (func == GPIO_ALT_FUNC_NONE)
-		func = GPIO_ALT_FUNC_DEFAULT;
-
-	while (mask) {
-		/* 32 gpio per port */
-		bit = get_next_bit(&mask);
-		/* 8 gpio per mode reg */
-		mode_reg_index = (port << 2) | (bit >> 3);
-		/*
-		 * b[3]   - write enable(?)
-		 * b[2:0] - mode
-		 */
-		shift = (bit & 7) << 2;
-		mode_bits = func << shift;
-		mode_mask = ~(0xf << shift);
-		AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) &
-						mode_mask) | mode_bits;
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(AP_GPIO_DIN(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
-}
-
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
-	else
-		AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Set input/output mode */
-	if (flags & GPIO_OUTPUT) {
-		/* Set level before changing to output mode */
-		if (flags & GPIO_HIGH)
-			AP_GPIO_DOUT(port) |= mask;
-		if (flags & GPIO_LOW)
-			AP_GPIO_DOUT(port) &= ~mask;
-		AP_GPIO_DIR(port) |= mask;
-	} else {
-		AP_GPIO_DIR(port) &= ~mask;
-	}
-
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH))
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW))
-		SCP_EINT_POLARITY_CLR[port] = mask;
-	else
-		SCP_EINT_POLARITY_SET[port] = mask;
-
-	/* Set sensitivity register on edge trigger */
-	if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING))
-		SCP_EINT_SENS_SET[port] = mask;
-	else
-		SCP_EINT_SENS_CLR[port] = mask;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	/* TODO(b/120167145): implement get flags */
-	return 0;
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_CLR[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_MASK_SET[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (signal >= GPIO_IH_COUNT || !g->mask)
-		return EC_ERROR_INVAL;
-
-	SCP_EINT_ACK[g->port] = g->mask;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-	int is_warm = system_is_reboot_warm();
-
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-void gpio_init(void)
-{
-	/* Enable EINT IRQ */
-	task_enable_irq(SCP_IRQ_EINT);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/* Interrupt handler */
-void __keep gpio_interrupt(void)
-{
-	int bit, port;
-	uint32_t pending;
-	enum gpio_signal signal;
-
-	for (port = 0; port <= MAX_EINT_PORT; port++) {
-		pending = SCP_EINT_STATUS[port];
-
-		while (pending) {
-			bit = get_next_bit(&pending);
-			SCP_EINT_ACK[port] = BIT(bit);
-			/* Skip masked gpio */
-			if (SCP_EINT_MASK_GET[port] & BIT(bit))
-				continue;
-			/* Call handler */
-			signal = port * 32 + bit;
-			if (signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-}
-DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1);
diff --git a/chip/mt_scp/mt8183/hrtimer.c b/chip/mt_scp/mt8183/hrtimer.c
deleted file mode 100644
index 92887af2a7..0000000000
--- a/chip/mt_scp/mt8183/hrtimer.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-
-/* ULPOSC1 should be a multiple of 8. */
-BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0);
-#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8)
-
-/* Common timer overflows at 0x100000000 micro seconds */
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-static uint8_t sys_high;
-static uint8_t event_high;
-
-/* Convert hardware countdown timer to 64bit countup ticks */
-static inline uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_TIMER_VAL(TIMER_SYSTEM));
-}
-
-static inline uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_TIMER_VAL(TIMER_EVENT));
-}
-
-static inline void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) |
-			  clock_source;
-}
-
-static inline void timer_ack_irq(int n)
-{
-	SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR;
-}
-
-/* Set hardware countdown value */
-static inline void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	SCP_TIMER_RESET_VAL(n) = reset_value;
-}
-
-static void timer_reset(int n)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_32K);
-}
-
-/* Reload a new 32bit countdown value */
-static void timer_reload(int n, uint32_t value)
-{
-	__hw_timer_enable_clock(n, 0);
-	timer_set_reset_value(n, value);
-	__hw_timer_enable_clock(n, 1);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff)
-			__hw_timer_enable_clock(TIMER_EVENT, 1);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	/* Disable event timer clock when done. */
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	return 0;
-}
-
-void __hw_clock_event_clear(void)
-{
-	__hw_timer_enable_clock(TIMER_EVENT, 0);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	if (enable) {
-		SCP_TIMER_IRQ_CTRL(n) |= 1;
-		SCP_TIMER_EN(n) |= 1;
-	} else {
-		SCP_TIMER_EN(n) &= ~1;
-		SCP_TIMER_IRQ_CTRL(n) &= ~1;
-	}
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/*
-	 * TODO(b/120169529): check clock tree to see if we need to turn on
-	 * MCLK and BCLK gate.
-	 */
-	SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B);
-
-	/* Reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; t++)
-		timer_reset(t);
-
-	/* Enable timer IRQ wake source */
-	SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) |
-			       (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) |
-			       (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5));
-	/*
-	 * Timer configuration:
-	 *   OS TIMER    - count up @ 13MHz, 64bit value with latch.
-	 *   SYS TICK    - count down @ 26MHz
-	 *   EVENT TICK  - count down @ 26MHz
-	 */
-
-	/* Turn on OS TIMER, tick at 13MHz */
-	SCP_OSTIMER_CON |= 1;
-
-	/* System timestamp timer from BCLK (sourced from ULPOSC) */
-	SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8;
-
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK);
-	sys_high = TIMER_CLOCK_MHZ-1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	__hw_timer_enable_clock(TIMER_SYSTEM, 1);
-	task_enable_irq(IRQ_TIMER(TIMER_SYSTEM));
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK);
-	task_enable_irq(IRQ_TIMER(TIMER_EVENT));
-
-	return IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-static void __hw_clock_source_irq(int n)
-{
-	uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n);
-
-	/* Ack if we're hardware interrupt */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		timer_ack_irq(n);
-
-	switch (n) {
-	case TIMER_EVENT:
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (timer_reload_event_high())
-				return;
-		}
-		process_timers(0);
-		break;
-	case TIMER_SYSTEM:
-		/* If this is a hardware irq, check overflow */
-		if (timer_ctrl & TIMER_IRQ_STATUS) {
-			if (sys_high) {
-				sys_high--;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ-1;
-				process_timers(1);
-			}
-		} else {
-			process_timers(0);
-		}
-		break;
-	default:
-		return;
-	}
-
-}
-
-#define DECLARE_TIMER_IRQ(n) \
-	DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \
-	void __hw_clock_source_irq_##n(void) { __hw_clock_source_irq(n); }
-
-DECLARE_TIMER_IRQ(0);
-DECLARE_TIMER_IRQ(1);
-DECLARE_TIMER_IRQ(2);
-DECLARE_TIMER_IRQ(3);
-DECLARE_TIMER_IRQ(4);
-DECLARE_TIMER_IRQ(5);
diff --git a/chip/mt_scp/mt8183/ipi.c b/chip/mt_scp/mt8183/ipi.c
deleted file mode 100644
index 8e13781db3..0000000000
--- a/chip/mt_scp/mt8183/ipi.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI)
- *
- * IPC is a communication bridge between AP and SCP.  AP/SCP sends an IPC
- * interrupt to SCP/AP to inform to collect the commmunication mesesages in the
- * shared buffer.
- *
- * There are 4 IPCs in the current architecture, from IPC0 to IPC3.  The
- * priority of IPC is proportional to its IPC index. IPC3 has the highest
- * priority and IPC0 has the lowest one.
- *
- * IPC0 may contain zero or more IPIs.  Each IPI represents a task or a service,
- * e.g. host command, or video encoding.  IPIs are recognized by IPI ID, which
- * should sync across AP and SCP.  Shared buffer should designated which IPI
- * ID it talks to.
- *
- * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3.
- */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "ipi_chip.h"
-#include "mkbp_event.h"
-#include "power.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "hwtimer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
-#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
-#define HOSTCMD_TYPE_HOSTCMD 1
-#define HOSTCMD_TYPE_HOSTEVENT 2
-
-static volatile int16_t ipc0_enabled_count;
-static struct mutex ipc0_lock;
-static struct mutex ipi_lock;
-/* IPC0 shared objects, including send object and receive object. */
-static struct ipc_shared_obj *const scp_send_obj =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const scp_recv_obj =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-static char ipi_ready;
-
-#ifdef HAS_TASK_HOSTCMD
-/*
- * hostcmd and hostevent share the same IPI ID, and use first byte type to
- * indicate its type.
- */
-static struct hostcmd_data {
-	const uint8_t type;
-	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
-	uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4);
-} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
-BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-static struct host_packet ipi_packet;
-#endif
-
-/* Check if SCP to AP IPI is in use. */
-static inline int is_ipi_busy(void)
-{
-	return SCP_HOST_INT & IPC_SCP2HOST_BIT;
-}
-
-/* If IPI is declared as a wake-up source, wake AP up. */
-static inline void try_to_wakeup_ap(int32_t id)
-{
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	if (id == IPI_NS_SERVICE)
-		return;
-#endif
-
-	if (*ipi_wakeup_table[id])
-		SCP_SPM_INT = SPM_INT_A2SPM;
-}
-
-void ipi_disable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((--ipc0_enabled_count) == 0)
-		task_disable_irq(irq);
-
-	mutex_unlock(&ipc0_lock);
-}
-
-void ipi_enable_irq(int irq)
-{
-	/* Only support SCP_IRQ_IPC0 for now. */
-	if (irq != SCP_IRQ_IPC0)
-		return;
-
-	mutex_lock(&ipc0_lock);
-
-	if ((++ipc0_enabled_count) == 1) {
-		int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL;
-
-		task_enable_irq(irq);
-
-		if (ipi_ready && pending_ipc)
-			/*
-			 * IPC may be triggered while SCP_IRQ_IPC0 was disabled.
-			 * AP will still updates SCP_GIPC_IN.
-			 * Trigger the IRQ handler if it has a
-			 * pending IPC.
-			 */
-			task_trigger_irq(irq);
-	}
-
-	mutex_unlock(&ipc0_lock);
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	int i;
-	const task_id_t s3_suspend_tasks[] = {
-#ifndef S3_SUSPEND_TASK_LIST
-#define S3_SUSPEND_TASK_LIST
-#endif
-#define TASK(n, ...) TASK_ID_##n,
-		S3_SUSPEND_TASK_LIST
-	};
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		ccprints("AP suspend");
-		/*
-		 * On AP suspend, Vcore is 0.6V, and we should not use ULPOSC2,
-		 * which needs at least 0.7V.  Switch to ULPOSC1 instead.
-		 */
-		scp_use_clock(SCP_CLK_ULPOSC1);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_disable_task(s3_suspend_tasks[i]);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		ccprints("AP resume");
-		/* Vcore is raised to >=0.7V, switch back to ULPSOC2 */
-		scp_use_clock(SCP_CLK_ULPOSC2);
-
-		for (i = 0; i < ARRAY_SIZE(s3_suspend_tasks); ++i)
-			task_enable_task(s3_suspend_tasks[i]);
-	}
-}
-
-/* Send data from SCP to AP. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	if (!ipi_ready)
-		return EC_ERROR_BUSY;
-
-	/* TODO(b:117917141): Remove this check completely. */
-	if (in_interrupt_context()) {
-		CPRINTS("Err: invoke %s() in ISR CTX", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(scp_send_obj->buffer))
-		return EC_ERROR_INVAL;
-
-	ipi_disable_irq(SCP_IRQ_IPC0);
-	mutex_lock(&ipi_lock);
-
-	/* Check if there is already an IPI pending in AP. */
-	if (is_ipi_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		try_to_wakeup_ap(id);
-
-		mutex_unlock(&ipi_lock);
-		ipi_enable_irq(SCP_IRQ_IPC0);
-		CPRINTS("Err: IPI Busy, %d", id);
-
-		return EC_ERROR_BUSY;
-	}
-
-
-	scp_send_obj->id = id;
-	scp_send_obj->len = len;
-	memcpy(scp_send_obj->buffer, buf, len);
-
-	/* Send IPI to AP: interrutp AP to receive IPI messages. */
-	try_to_wakeup_ap(id);
-	SCP_HOST_INT = IPC_SCP2HOST_BIT;
-
-	while (wait && is_ipi_busy())
-		;
-
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	return EC_SUCCESS;
-}
-
-static void ipi_handler(void)
-{
-	if (scp_recv_obj->id >= IPI_COUNT) {
-		CPRINTS("#ERR IPI %d", scp_recv_obj->id);
-		return;
-	}
-
-	/*
-	 * Only print IPI that is not host command channel, which will
-	 * be printed by host command driver.
-	 */
-	if (scp_recv_obj->id != IPI_HOST_COMMAND)
-		CPRINTS("IPI %d", scp_recv_obj->id);
-
-	/*
-	 * Pass the buffer to handler. Each handler should be in charge of
-	 * the buffer copying/reading before returning from handler.
-	 */
-	ipi_handler_table[scp_recv_obj->id](
-		scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len);
-}
-
-void ipi_inform_ap(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	struct rpmsg_ns_msg ns_msg;
-#endif
-
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED;
-	scp_run.enc_capability = 0;
-
-	ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-
-	if (ret)
-		ccprintf("Failed to send initialization IPC messages.\n");
-
-#ifdef CONFIG_RPMSG_NAME_SERVICE
-	ns_msg.id = IPI_HOST_COMMAND;
-	strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
-	ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
-	if (ret)
-		ccprintf("Failed to announce host command channel.\n");
-#endif
-}
-
-#ifdef HAS_TASK_HOSTCMD
-#if defined(CONFIG_MKBP_USE_CUSTOM)
-int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp)
-{
-	static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT;
-
-	/* This should be moved into ipi_send for more accuracy */
-	if (timestamp)
-		*timestamp = __hw_clock_source_read();
-
-	if (active)
-		return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj,
-				sizeof(hc_evt_obj), 1);
-	return EC_SUCCESS;
-}
-#endif
-
-static void ipi_send_response_packet(struct host_packet *pkt)
-{
-	int ret;
-
-	ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj,
-		       pkt->response_size +
-			       offsetof(struct hostcmd_data, response),
-		       1);
-	if (ret)
-		CPRINTS("#ERR IPI HOSTCMD %d", ret);
-}
-
-static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len)
-{
-	uint8_t *in_msg = buf;
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-	int i;
-
-	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-		CPRINTF("in_msg=[");
-		for (i = 0; i < len; i++)
-			CPRINTF("%02x ", in_msg[i]);
-		CPRINTF("]\n");
-		return;
-	}
-
-	/* Protocol version 3 */
-
-	ipi_packet.send_response = ipi_send_response_packet;
-
-	/*
-	 * Just assign the buffer to request, host_packet_receive
-	 * handles the buffer copy.
-	 */
-	ipi_packet.request = (void *)r;
-	ipi_packet.request_temp = NULL;
-	ipi_packet.request_max = IPI_MAX_REQUEST_SIZE;
-	ipi_packet.request_size = host_request_expected_size(r);
-
-	ipi_packet.response = hc_cmd_obj.response;
-	/* Reserve space for the preamble and trailing byte */
-	ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE;
-	ipi_packet.response_size = 0;
-
-	ipi_packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&ipi_packet);
-}
-DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0);
-
-/*
- * Get protocol information
- */
-static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = IPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info,
-		     EC_VER_MASK(0));
-#endif
-
-static void ipi_enable_ipc0_deferred(void)
-{
-	/* Clear IPC0 IRQs. */
-	SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL;
-
-	/* All tasks are up, we can safely enable IPC0 IRQ now. */
-	SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN;
-	ipi_enable_irq(SCP_IRQ_IPC0);
-
-	ipi_ready = 1;
-
-	/* Inform AP that SCP is inited.  */
-	ipi_inform_ap();
-
-	CPRINTS("ipi init");
-}
-DECLARE_DEFERRED(ipi_enable_ipc0_deferred);
-
-/* Initialize IPI. */
-static void ipi_init(void)
-{
-	/* Clear send share buffer. */
-	memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj));
-
-	/* Enable IRQ after all tasks are up.  */
-	hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4);
-void ipc_handler(void)
-{
-	/* TODO(b/117917141): We only support IPC_ID(0) for now. */
-	if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0);
-	}
-
-	SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0));
-}
diff --git a/chip/mt_scp/mt8183/ipi_chip.h b/chip/mt_scp/mt8183/ipi_chip.h
deleted file mode 100644
index 758047951f..0000000000
--- a/chip/mt_scp/mt8183/ipi_chip.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-#include "common.h"
-#include "registers.h"
-
-#define IPC_MAX 1
-#define IPC_ID(n) (n)
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-/*
- * Video decoder supported capability:
- * BIT(4): 0 enable 4K
- *         1 disable 4K
- */
-#define VCODEC_CAPABILITY_4K_DISABLED BIT(4)
-
-#ifndef IPI_SCP_INIT
-#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for IPI_SCP_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP. This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/* Size of the rpmsg device name, should sync across kernel and EC. */
-#define RPMSG_NAME_SIZE 32
-
-/*
- * The layout of name service message.
- * This should sync across kernel and EC.
- */
-struct rpmsg_ns_msg {
-	/* Name of the corresponding rpmsg_driver. */
-	char name[RPMSG_NAME_SIZE];
-	/* IPC ID */
-	uint32_t id;
-};
-
-/*
- * IPC Handler.
- */
-void ipc_handler(void);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timeing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(int irq);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(int irq);
-
-/* IPI tables */
-extern void (*ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/mt8183/ipi_table.c b/chip/mt_scp/mt8183/ipi_table.c
deleted file mode 100644
index 8569ab24a7..0000000000
--- a/chip/mt_scp/mt8183/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type name[] __aligned(4)                                               \
-		__attribute__((section(".rodata.ipi, \"a\" @"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt_scp/mt8183/memmap.c b/chip/mt_scp/mt8183/memmap.c
deleted file mode 100644
index 6d8f2b0c87..0000000000
--- a/chip/mt_scp/mt8183/memmap.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "memmap.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP addr    :  AP addr
- * 0x20000000     0x40000000
- * 0x30000000     0x50000000
- * 0x60000000     0x60000000
- * 0x70000000     0x70000000
- * 0x80000000     0x80000000
- * 0x90000000     0x00000000
- * 0xA0000000     0x10000000
- * 0xB0000000     0x20000000
- * 0xC0000000     0x30000000
- * 0xD0000000     0x10000000
- * 0xE0000000     0xA0000000
- * 0xF0000000     0x90000000
- */
-
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,			/* 0x0: SRAM */
-	MAP_INVALID,			/* 0x1: Cached access (see below) */
-	0x4, 0x5,			/* 0x2-0x3 */
-	MAP_INVALID, MAP_INVALID,	/* 0x4-0x5 (unmapped: registers) */
-	0x6, 0x7, 0x8,			/* 0x6-0x8 */
-	0x0, 0x1, 0x2, 0x3,		/* 0x9-0xc */
-	0x1, 0xa, 0x9			/* 0xd-0xf */
-};
-
-/*
- * AP addr     :  SCP cache addr
- * 0x50000000     0x10000000
- */
-#define CACHE_TRANS_AP_ADDR 0x50000000
-#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
-/* FIXME: This should be configurable */
-#define CACHE_TRANS_AP_SIZE 0x00400000
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-static void cpu_invalidate_icache(void)
-{
-	SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_ICACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	asm volatile("dsb; isb");
-}
-
-void cpu_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read is necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache(void)
-{
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN;
-	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Read necessary to confirm the invalidation finish. */
-	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
-	asm volatile("dsb;");
-}
-
-void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
-{
-	size_t pos;
-	uintptr_t addr;
-
-	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
-		addr = base + pos;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
-		SCP_CACHE_OP(CACHE_DCACHE) |=
-			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Read necessary to confirm the invalidation finish. */
-		REG32(addr);
-	}
-	asm volatile("dsb;");
-}
-
-static void scp_cache_init(void)
-{
-	int c;
-	const int region = 0;
-
-	/* First make sure all caches are disabled, and reset stats. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		/*
-		 * Changing cache-size config may change the SRAM logical
-		 * address in the mean time.  This may break the loaded
-		 * memory layout, and thus break the system.  Cache-size
-		 * should only be be configured in kernel driver before
-		 * laoding the firmware. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK |
-				     SCP_CACHE_CON_WAYEN);
-		SCP_CACHE_REGION_EN(c) = 0;
-		SCP_CACHE_ENTRY(c, region) = 0;
-		SCP_CACHE_END_ENTRY(c, region) = 0;
-
-		/* Reset statistics. */
-		SCP_CACHE_HCNT0U(c) = 0;
-		SCP_CACHE_HCNT0L(c) = 0;
-		SCP_CACHE_CCNT0U(c) = 0;
-		SCP_CACHE_CCNT0L(c) = 0;
-	}
-
-	/* No "normal" remap. */
-	SCP_L1_REMAP_CFG0 = 0;
-	SCP_L1_REMAP_CFG1 = 0;
-	SCP_L1_REMAP_CFG2 = 0;
-	SCP_L1_REMAP_CFG3 = 0;
-	/*
-	 * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and
-	 * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7.
-	 */
-	SCP_L1_REMAP_OTHER =
-		(CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8;
-
-	/* Disable sleep protect */
-	SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
-		~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
-
-	/* Enable region 0 for both I-cache and D-cache. */
-	for (c = 0; c < CACHE_COUNT; c++) {
-		SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR;
-		SCP_CACHE_END_ENTRY(c, region) =
-			CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE;
-		SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C;
-
-		SCP_CACHE_REGION_EN(c) |= 1 << region;
-
-		/*
-		 * Enable cache. Note that cache size setting should have been
-		 * done in kernel driver. b/137920815#comment18
-		 */
-		SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0;
-	}
-
-	cpu_invalidate_icache();
-	cpu_invalidate_dcache();
-}
-
-static int command_cacheinfo(int argc, char **argv)
-{
-	const char cache_name[] = {'I', 'D'};
-	int c;
-
-	for (c = 0; c < 2; c++) {
-		uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
-			SCP_CACHE_HCNT0L(c);
-		uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
-			SCP_CACHE_CCNT0L(c);
-
-		ccprintf("%ccache hit count:    %llu\n", cache_name[c], hit);
-		ccprintf("%ccache access count: %llu\n", cache_name[c], access);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo,
-			     NULL,
-			     "Dump cache info");
-
-void scp_memmap_init(void)
-{
-	/*
-	 * Default config, LARGE DRAM not active:
-	 *   REG32(0xA0001F00) & 0x2000 != 0
-	 */
-
-	/*
-	 * SCP_REMAP_CFG1
-	 * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
-	 * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
-	 * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
-	 * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
-	 */
-	SCP_REMAP_CFG1 =
-		(uint32_t)addr_map[0x7] << 24 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x3] << 8 |
-		(uint32_t)addr_map[0x2];
-
-	/*
-	 * SCP_REMAP_CFG2
-	 * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
-	 * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
-	 * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
-	 * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
-	 */
-	SCP_REMAP_CFG2 =
-		(uint32_t)addr_map[0xb] << 24 |
-		(uint32_t)addr_map[0xa] << 16 |
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0x8];
-	/*
-	 * SCP_REMAP_CFG3
-	 * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
-	 * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
-	 * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
-	 * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
-	 */
-	SCP_REMAP_CFG3 =
-		(uint32_t)addr_map[0xd] << 28 |
-		(uint32_t)addr_map[0xf] << 16 |
-		(uint32_t)addr_map[0xe] << 8 |
-		(uint32_t)addr_map[0xc];
-
-	/* Initialize cache remapping. */
-	scp_cache_init();
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); i++) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
-			(i << SCP_REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> SCP_REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << SCP_REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_DRAM_BASE
-BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
-BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
-#endif
-
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	uintptr_t lsb;
-
-	if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb > CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb;
-	return EC_SUCCESS;
-}
-
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	uintptr_t lsb;
-
-	if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
-			CACHE_TRANS_SCP_CACHE_ADDR)
-		return EC_ERROR_INVAL;
-
-	lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
-	if (lsb >= CACHE_TRANS_AP_SIZE)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = CACHE_TRANS_AP_ADDR | lsb;
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/mt8183/memmap.h b/chip/mt_scp/mt8183/memmap.h
deleted file mode 100644
index fbecb5e8cf..0000000000
--- a/chip/mt_scp/mt8183/memmap.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SCP memory map
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-void scp_memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to tranlate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-/**
- * Translate AP addr to SCP cache addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Tranlated AP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP cache address to tranlate
- * @param ap_addr		Translated SCP cache address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/mt8183/registers.h b/chip/mt_scp/mt8183/registers.h
deleted file mode 100644
index 21270b452d..0000000000
--- a/chip/mt_scp/mt8183/registers.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for SCP
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-/* IRQ numbers */
-#define SCP_IRQ_IPC0			0
-#define SCP_IRQ_IPC1			1
-#define SCP_IRQ_IPC2			2
-#define SCP_IRQ_IPC3			3
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-#define SCP_IRQ_UART0			8
-#define SCP_IRQ_UART1			9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1			11
-#define SCP_IRQ_I2C2			12
-#define SCP_IRQ_CLOCK			13
-#define SCP_IRQ_MAD_FIFO		14
-#define SCP_IRQ_TIMER0			15
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_TIMER_STATUS		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-#define SCP_IRQ_DMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD1_F216		26
-#define SCP_IRQ_MD1			27
-#define SCP_IRQ_C2K			28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-#define SCP_IRQ_AP_EINT			32
-#define SCP_IRQ_DEBUG			33
-#define SCP_CCIF0			34
-#define SCP_CCIF1			35
-#define SCP_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-#define SCP_IRQ_TWAM			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_HWDVFS_HIGH		42
-#define SCP_IRQ_HWDVFS_LOW		43
-#define SCP_IRQ_CLOCK2			44
-/* RESERVED 45-52 */
-#define SCP_IRQ_AP_EINT2		53
-#define SCP_IRQ_AP_EINT_EVT		54
-#define SCP_IRQ_MAD_DATA		55
-
-#define SCP_CFG_BASE			0x405C0000
-
-#define SCP_AP_RESOURCE			REG32(SCP_CFG_BASE + 0x04)
-#define SCP_BUS_RESOURCE		REG32(SCP_CFG_BASE + 0x08)
-
-/* SCP to host interrupt */
-#define SCP_HOST_INT			REG32(SCP_CFG_BASE + 0x1C)
-#define   IPC_SCP2HOST_SSHUB		0xff0000
-#define   WDT_INT			0x100
-#define   IPC_SCP2HOST                  0xff
-#define   IPC_SCP2HOST_BIT		0x1
-
-/* SCP to SPM interrupt */
-#define SCP_SPM_INT			REG32(SCP_CFG_BASE + 0x20)
-#define   SPM_INT_A2SPM			BIT(0)
-#define   SPM_INT_B2SPM			BIT(1)
-#define SCP_SPM_INT2			REG32(SCP_CFG_BASE + 0x24)
-
-/*
- * AP side to SCP IPC
- * APMCU writes 1 bit to trigger ith IPC to SCP.
- * SCP writes 1 bit to ith bit to clear ith IPC.
- */
-#define SCP_GIPC_IN			REG32(SCP_CFG_BASE + 0x28)
-  #define SCP_GIPC_IN_CLEAR_IPCN(n)	(1 << (n))
-  #define SCP_GPIC_IN_CLEAR_ALL		0x7FFFF
-#define SCP_CONN_INT			REG32(SCP_CFG_BASE + 0x2C)
-
-/* 8 general purpose registers, 0 ~ 7 */
-#define SCP_GPR				REG32_ADDR(SCP_CFG_BASE + 0x50)
-/*
- * SCP_GPR[0]
- *   b15-b0   : scratchpad
- *   b31-b16  : saved flags
- * SCP_GPR[1]
- *   b15-b0   : power on state
- */
-#define SCP_PWRON_STATE			SCP_GPR[1]
-#define   PWRON_DEFAULT			0xdee80000
-#define   PWRON_WATCHDOG		BIT(0)
-#define   PWRON_RESET			BIT(1)
-/* AP defined features */
-#define SCP_EXPECTED_FREQ		SCP_GPR[3]
-#define SCP_CURRENT_FREQ		SCP_GPR[4]
-#define SCP_REBOOT			SCP_GPR[5]
-#define  READY_TO_REBOOT		0x34
-#define  REBOOT_OK			1
-
-/* Miscellaneous */
-#define SCP_SEMAPHORE			REG32(SCP_CFG_BASE + 0x90)
-#define CORE_CONTROL			REG32(SCP_CFG_BASE + 0xA0)
-#define CORE_FPU_FLAGS			REG32(SCP_CFG_BASE + 0xA4)
-#define CORE_REG_SP			REG32(SCP_CFG_BASE + 0xA8)
-#define CORE_REG_LR			REG32(SCP_CFG_BASE + 0xAC)
-#define CORE_REG_PSP			REG32(SCP_CFG_BASE + 0xB0)
-#define CORE_REG_PC			REG32(SCP_CFG_BASE + 0xB4)
-#define SCP_SLP_PROTECT_CFG		REG32(SCP_CFG_BASE + 0xC8)
-#define   P_CACHE_SLP_PROT_EN		BIT(3)
-#define   D_CACHE_SLP_PROT_EN		BIT(4)
-#define SCP_ONE_TIME_LOCK		REG32(SCP_CFG_BASE + 0xDC)
-#define SCP_SECURE_CTRL			REG32(SCP_CFG_BASE + 0xE0)
-#define   ENABLE_SPM_MASK_VREQ		BIT(28)
-#define   DISABLE_REMAP			BIT(22)
-#define   DISABLE_JTAG			BIT(21)
-#define   DISABLE_AP_TCM		BIT(20)
-#define SCP_SYS_CTRL			REG32(SCP_CFG_BASE + 0xE4)
-#define   DDREN_FIX_VALUE		BIT(28)
-#define   AUTO_DDREN			BIT(18)
-
-/* Memory remap control */
-/*
- * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7
- * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6
- * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
- * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
- */
-#define SCP_REMAP_CFG1			REG32(SCP_CFG_BASE + 0x120)
-/*
- * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
- * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
- * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
- * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
- */
-#define SCP_REMAP_CFG2			REG32(SCP_CFG_BASE + 0x124)
-/*
- * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
- * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
- * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
- * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
- */
-#define SCP_REMAP_CFG3			REG32(SCP_CFG_BASE + 0x128)
-
-#define SCP_REMAP_ADDR_SHIFT		28
-#define SCP_REMAP_ADDR_LSB_MASK		(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_REMAP_ADDR_MSB_MASK		((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Cached memory remap control */
-#define SCP_L1_REMAP_CFG0		REG32(SCP_CFG_BASE + 0x12C)
-/*
- * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401
- * L1C_EXT_ADDR0[13:0]  remap register for addr msb 31~20 equal to 0x400
- */
-#define SCP_L1_REMAP_CFG1		REG32(SCP_CFG_BASE + 0x130)
-/*
- * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403
- * L1C_EXT_ADDR2[13:0]  remap register for addr msb 31~20 equal to 0x402
- */
-#define SCP_L1_REMAP_CFG2		REG32(SCP_CFG_BASE + 0x134)
-/*
- * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405
- * L1C_EXT_ADDR4[13:0]  remap register for addr msb 31~20 equal to 0x404
- */
-#define SCP_L1_REMAP_CFG3		REG32(SCP_CFG_BASE + 0x138)
-/*
- * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1
- * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0
- * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7
- */
-#define SCP_L1_REMAP_OTHER		REG32(SCP_CFG_BASE + 0x13C)
-
-#define SCP_L1_EXT_ADDR_SHIFT		20
-#define SCP_L1_EXT_ADDR_OTHER_SHIFT	28
-#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK	(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK	((~0) << SCP_REMAP_ADDR_SHIFT)
-
-/* Audio/voice FIFO */
-#define SCP_AUDIO_BASE			(SCP_CFG_BASE + 0x1000)
-#define SCP_VIF_FIFO_EN			REG32(SCP_AUDIO_BASE)
-#define   VIF_FIFO_RSTN			(1 << 0)
-#define   VIF_FIFO_IRQ_EN		(1 << 1)
-#define   VIF_FIFO_SRAM_PWR		(1 << 2)
-#define   VIF_FIFO_RSTN_STATUS		(1 << 4)
-#define SCP_VIF_FIFO_STATUS		REG32(SCP_AUDIO_BASE + 0x04)
-#define   VIF_FIFO_VALID		(1 << 0)
-#define   VIF_FIFO_FULL			(1 << 4)
-#define   VIF_FIFO_LEVEL(status)	(((status) >> 16) & 0xff)
-#define   VIF_FIFO_MAX			256
-#define SCP_VIF_FIFO_DATA		REG32(SCP_AUDIO_BASE + 0x08)
-#define SCP_VIF_FIFO_DATA_THRE		REG32(SCP_AUDIO_BASE + 0x0C)
-/* VIF IRQ status clears on read! */
-#define SCP_VIF_FIFO_IRQ_STATUS		REG32(SCP_AUDIO_BASE + 0x10)
-/* Audio/voice serial interface */
-#define SCP_RXIF_CFG0			REG32(SCP_AUDIO_BASE + 0x14)
-#define   RXIF_CFG0_RESET_VAL		0x2A130001
-#define   RXIF_AFE_ON			(1 << 0)
-#define   RXIF_SCKINV			(1 << 1)
-#define   RXIF_RG_DL_2_IN_MODE(mode)	(((mode) & 0xf) << 8)
-#define   RXIF_RGDL2_AMIC_16K		(0x1 << 8)
-#define   RXIF_RGDL2_DMIC_16K		(0x2 << 8)
-#define   RXIF_RGDL2_DMIC_LP_16K	(0x3 << 8)
-#define   RXIF_RGDL2_AMIC_32K		(0x5 << 8)
-#define   RXIF_RGDL2_MASK		(0xf << 8)
-#define   RXIF_UP8X_RSP(p)		(((p) & 0x7) << 16)
-#define   RXIF_RG_RX_READEN		(1 << 19)
-#define   RXIF_MONO			(1 << 20)
-#define   RXIF_RG_CLK_A16P7K_EN(cnt)	(((cnt) & 0xff) << 24)
-#define SCP_RXIF_CFG1			REG32(SCP_AUDIO_BASE + 0x18)
-#define   RXIF_CFG1_RESET_VAL		0x33180014
-#define   RXIF_RG_SYNC_CNT_TBL(t)	((t) & 0x1ff)
-#define   RXIF_RG_SYNC_SEARCH_TBL(t)	(((t) & 0x1f) << 16)
-#define   RXIF_RG_SYNC_CHECK_ROUND(r)	(((r) & 0xf) << 24)
-#define   RXIF_RG_INSYNC_CHECK_ROUND(r)	(((r) & 0xf) << 28)
-#define SCP_RXIF_CFG2			REG32(SCP_AUDIO_BASE + 0x1C)
-#define   RXIF_SYNC_WORD(w)		((w) & 0xffff)
-#define SCP_RXIF_OUT			REG32(SCP_AUDIO_BASE + 0x20)
-#define SCP_RXIF_STATUS			REG32(SCP_AUDIO_BASE + 0x24)
-#define SCP_RXIF_IRQ_EN			REG32(SCP_AUDIO_BASE + 0x28)
-
-/* INTC control */
-#define SCP_INTC_BASE			(SCP_CFG_BASE + 0x2000)
-#define SCP_INTC_IRQ_STATUS		REG32(SCP_INTC_BASE)
-#define SCP_INTC_IRQ_ENABLE		REG32(SCP_INTC_BASE + 0x04)
-#define   IPC0_IRQ_EN			BIT(0)
-#define SCP_INTC_IRQ_OUTPUT		REG32(SCP_INTC_BASE + 0x08)
-#define SCP_INTC_IRQ_WAKEUP		REG32(SCP_INTC_BASE + 0x0C)
-#define SCP_INTC_NMI			REG32(SCP_INTC_BASE + 0x10)
-#define SCP_INTC_SPM_WAKEUP		REG32(SCP_INTC_BASE + 0x14)
-#define SCP_INTC_SPM_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x18)
-#define SCP_INTC_UART_RX_IRQ		REG32(SCP_INTC_BASE + 0x1C)
-#define SCP_INTC_IRQ_STATUS_MSB		REG32(SCP_INTC_BASE + 0x80)
-#define SCP_INTC_IRQ_ENABLE_MSB		REG32(SCP_INTC_BASE + 0x84)
-#define SCP_INTC_IRQ_OUTPUT_MSB		REG32(SCP_INTC_BASE + 0x88)
-#define SCP_INTC_IRQ_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x8C)
-
-/* Timer */
-#define NUM_TIMERS			6
-#define SCP_TIMER_BASE(n)		(SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
-#define SCP_TIMER_EN(n)			REG32(SCP_TIMER_BASE(n))
-#define SCP_TIMER_RESET_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x04)
-#define SCP_TIMER_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x08)
-#define SCP_TIMER_IRQ_CTRL(n)		REG32(SCP_TIMER_BASE(n) + 0x0C)
-#define   TIMER_IRQ_ENABLE		BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLEAR		BIT(5)
-#define SCP_TIMER_CLK_SEL(n)		REG32(SCP_TIMER_BASE(n) + 0x40)
-#define   TIMER_CLK_32K			(0 << 4)
-#define   TIMER_CLK_26M			BIT(4)
-#define   TIMER_CLK_BCLK		(2 << 4)
-#define   TIMER_CLK_PCLK		(3 << 4)
-#define   TIMER_CLK_MASK		(3 << 4)
-/* OS timer */
-#define SCP_OSTIMER_BASE		(SCP_CFG_BASE + 0x3080)
-#define SCP_OSTIMER_CON			REG32(SCP_OSTIMER_BASE)
-#define SCP_OSTIMER_INIT_L		REG32(SCP_OSTIMER_BASE + 0x04)
-#define SCP_OSTIMER_INIT_H		REG32(SCP_OSTIMER_BASE + 0x08)
-#define SCP_OSTIMER_VAL_L		REG32(SCP_OSTIMER_BASE + 0x0C)
-#define SCP_OSTIMER_VAL_H		REG32(SCP_OSTIMER_BASE + 0x10)
-#define SCP_OSTIMER_TVAL		REG32(SCP_OSTIMER_BASE + 0x14)
-#define SCP_OSTIMER_IRQ_ACK		REG32(SCP_OSTIMER_BASE + 0x18)
-#define   OSTIMER_LATCH0_EN		BIT(5)
-#define   OSTIMER_LATCH1_EN		BIT(13)
-#define   OSTIMER_LATCH2_EN		BIT(21)
-#define SCP_OSTIMER_LATCH_CTRL		REG32(SCP_OSTIMER_BASE + 0x20)
-#define SCP_OSTIMER_LATCH0_L		REG32(SCP_OSTIMER_BASE + 0x24)
-#define SCP_OSTIMER_LATCH0_H		REG32(SCP_OSTIMER_BASE + 0x28)
-#define SCP_OSTIMER_LATCH1_L		REG32(SCP_OSTIMER_BASE + 0x2C)
-#define SCP_OSTIMER_LATCH1_H		REG32(SCP_OSTIMER_BASE + 0x30)
-#define SCP_OSTIMER_LATCH2_L		REG32(SCP_OSTIMER_BASE + 0x34)
-#define SCP_OSTIMER_LATCH2_H		REG32(SCP_OSTIMER_BASE + 0x38)
-
-/* Clock, PMIC wrapper, etc. */
-#define SCP_CLK_BASE			(SCP_CFG_BASE + 0x4000)
-#define SCP_CLK_SEL			REG32(SCP_CLK_BASE)
-#define   CLK_SEL_SYS_26M		0
-#define   CLK_SEL_32K			1
-#define   CLK_SEL_ULPOSC_2		2
-#define   CLK_SEL_ULPOSC_1		3
-
-#define SCP_CLK_EN			REG32(SCP_CLK_BASE + 0x04)
-#define   EN_CLK_SYS			BIT(0) /* System clock */
-#define   EN_CLK_HIGH			BIT(1) /* ULPOSC */
-#define   CG_CLK_HIGH			BIT(2)
-#define   EN_SYS_IRQ			BIT(16)
-#define   EN_HIGH_IRQ			BIT(17)
-#define SCP_CLK_SAFE_ACK		REG32(SCP_CLK_BASE + 0x08)
-#define SCP_CLK_ACK			REG32(SCP_CLK_BASE + 0x0C)
-#define SCP_CLK_IRQ_ACK			REG32(SCP_CLK_BASE + 0x10)
-/*
- * System clock counter value.
- * CLK_SYS_VAL[9:0] System clock counter initial/reset value.
- */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_BASE + 0x14)
-#define   CLK_SYS_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_SYS_VAL(n)		((n) & CLK_SYS_VAL_MASK)
-/*
- * ULPOSC clock counter value.
- * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value.
- */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_BASE + 0x18)
-#define   CLK_HIGH_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_HIGH_VAL(n)		((n) & CLK_HIGH_VAL_MASK)
-#define SCP_CLK_SLOW_SEL		REG32(SCP_CLK_BASE + 0x1C)
-#define   CKSW_SEL_SLOW_MASK		0x3
-#define   CKSW_SEL_SLOW_DIV_MASK	0x30
-#define   CKSW_SEL_SLOW_SYS_CLK		0
-#define   CKSW_SEL_SLOW_32K_CLK		1
-#define   CKSW_SEL_SLOW_ULPOSC2_CLK	2
-#define   CKSW_SEL_SLOW_ULPOSC1_CLK	3
-/*
- * Sleep mode control.
- * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the
- *     voltage after returning from  sleep mode.
- */
-#define SCP_CLK_SLEEP_CTRL		REG32(SCP_CLK_BASE + 0x20)
-#define   EN_SLEEP_CTRL			BIT(0)
-#define   VREQ_COUNTER_MASK		0xfe
-#define   VREQ_COUNTER_VAL(v)		(((v) << 1) & VREQ_COUNTER_MASK)
-#define   SPM_SLEEP_MODE		BIT(8)
-#define   SPM_SLEEP_MODE_CLK_AO		BIT(9)
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_BASE + 0x24)
-#define   CLK_DIV1			0
-#define   CLK_DIV2			1
-#define   CLK_DIV4			2
-#define   CLK_DIV8			3
-#define SCP_CLK_DEBUG			REG32(SCP_CLK_BASE + 0x28)
-#define SCP_CLK_SRAM_POWERDOWN		REG32(SCP_CLK_BASE + 0x2C)
-#define SCP_CLK_GATE			REG32(SCP_CLK_BASE + 0x30)
-#define   CG_TIMER_M			BIT(0)
-#define   CG_TIMER_B			BIT(1)
-#define   CG_MAD_M			BIT(2)
-#define   CG_I2C_M			BIT(3)
-#define   CG_I2C_B			BIT(4)
-#define   CG_GPIO_M			BIT(5)
-#define   CG_AP2P_M			BIT(6)
-#define   CG_UART_M			BIT(7)
-#define   CG_UART_B			BIT(8)
-#define   CG_UART_RSTN			BIT(9)
-#define   CG_UART1_M			BIT(10)
-#define   CG_UART1_B			BIT(11)
-#define   CG_UART1_RSTN			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_TWAM			BIT(20)
-#define   CG_CACHE_I_CTRL		BIT(21)
-#define   CG_CACHE_D_CTRL		BIT(22)
-#define SCP_PMICW_CTRL			REG32(SCP_CLK_BASE + 0x34)
-#define   PMICW_SLEEP_REQ		BIT(0)
-#define   PMICW_SLEEP_ACK		BIT(4)
-#define   PMICW_CLK_MUX			BIT(8)
-#define   PMICW_DCM			BIT(9)
-#define SCP_SLEEP_WAKE_DEBUG		REG32(SCP_CLK_BASE + 0x38)
-#define SCP_DCM_EN			REG32(SCP_CLK_BASE + 0x3C)
-#define SCP_WAKE_CKSW			REG32(SCP_CLK_BASE + 0x40)
-#define   WAKE_CKSW_SEL_NORMAL_MASK	0x3
-#define   WAKE_CKSW_SEL_SLOW_MASK	0x30
-#define   WAKE_CKSW_SEL_SLOW_DEFAULT	0x10
-#define SCP_CLK_UART			REG32(SCP_CLK_BASE + 0x44)
-#define   CLK_UART_SEL_MASK		0x3
-#define   CLK_UART_SEL_26M		0x0
-#define   CLK_UART_SEL_32K		0x1
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART_SEL_ULPOSC1_DIV10	0x2
-#define   CLK_UART1_SEL_MASK		(0x3 << 16)
-#define   CLK_UART1_SEL_26M		(0x0 << 16)
-#define   CLK_UART1_SEL_32K		(0x1 << 16)
-/* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART1_SEL_ULPOSC1_DIV10	(0x2 << 16)
-#define SCP_CLK_BCLK			REG32(SCP_CLK_BASE + 0x48)
-#define   CLK_BCLK_SEL_MASK		0x3
-#define   CLK_BCLK_SEL_SYS_DIV8		0x0
-#define   CLK_BCLK_SEL_32K		0x1
-#define   CLK_BCLK_SEL_ULPOSC1_DIV8	0x2
-#define SCP_CLK_SPI_BCK			REG32(SCP_CLK_BASE + 0x4C)
-#define SCP_CLK_DIV_CNT			REG32(SCP_CLK_BASE + 0x50)
-#define SCP_CPU_VREQ			REG32(SCP_CLK_BASE + 0x54)
-#define   CPU_VREQ_HW_MODE		0x10001
-#define SCP_CLK_CLEAR			REG32(SCP_CLK_BASE + 0x58)
-#define SCP_CLK_HIGH_CORE		REG32(SCP_CLK_BASE + 0x5C)
-#define   CLK_HIGH_CORE_CG		(1 << 1)
-#define SCP_SLEEP_IRQ2			REG32(SCP_CLK_BASE + 0x64)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_BASE + 0x6C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-#define   HIGH_FINAL_VAL_MASK		0x1f00
-#define   HIGH_FINAL_VAL_DEFAULT	0x300
-#define SCP_CLK_L1_SRAM_PD		REG32(SCP_CLK_BASE + 0x80)
-#define SCP_CLK_TCM_TAIL_SRAM_PD	REG32(SCP_CLK_BASE + 0x94)
-#define SCP_CLK_SLEEP			REG32(SCP_CLK_BASE + 0xA0)
-#define   SLOW_WAKE_DISABLE		1
-#define SCP_FAST_WAKE_CNT_END		REG32(SCP_CLK_BASE + 0xA4)
-#define   FAST_WAKE_CNT_END_MASK	0xfff
-#define   FAST_WAKE_CNT_END_DEFAULT	0x18
-#define   MEM_CK_CS_ISO_CNT_END_MASK	0x7f0000
-
-/* Peripherals */
-#define SCP_I2C0_BASE			(SCP_CFG_BASE + 0x5000)
-#define SCP_I2C1_BASE			(SCP_CFG_BASE + 0x6000)
-#define SCP_I2C2_BASE			(SCP_CFG_BASE + 0x7000)
-
-#define SCP_GPIO_BASE			(SCP_CFG_BASE + 0x8000)
-#define SCP_UART0_BASE			(SCP_CFG_BASE + 0x9000)
-#define SCP_UART1_BASE			(SCP_CFG_BASE + 0xE000)
-#define SCP_UART_COUNT			2
-
-/* External GPIO interrupt */
-#define SCP_EINT_BASE			(SCP_CFG_BASE + 0xA000)
-#define SCP_EINT_STATUS			REG32_ADDR(SCP_EINT_BASE)
-#define SCP_EINT_ACK			REG32_ADDR(SCP_EINT_BASE + 0x040)
-#define SCP_EINT_MASK_GET		REG32_ADDR(SCP_EINT_BASE + 0x080)
-#define SCP_EINT_MASK_SET		REG32_ADDR(SCP_EINT_BASE + 0x0C0)
-#define SCP_EINT_MASK_CLR		REG32_ADDR(SCP_EINT_BASE + 0x100)
-#define SCP_EINT_SENS_GET		REG32_ADDR(SCP_EINT_BASE + 0x140)
-#define SCP_EINT_SENS_SET		REG32_ADDR(SCP_EINT_BASE + 0x180)
-#define SCP_EINT_SENS_CLR		REG32_ADDR(SCP_EINT_BASE + 0x1C0)
-#define SCP_EINT_SOFT_GET		REG32_ADDR(SCP_EINT_BASE + 0x200)
-#define SCP_EINT_SOFT_SET		REG32_ADDR(SCP_EINT_BASE + 0x240)
-#define SCP_EINT_SOFT_CLR		REG32_ADDR(SCP_EINT_BASE + 0x280)
-#define SCP_EINT_POLARITY_GET		REG32_ADDR(SCP_EINT_BASE + 0x300)
-#define SCP_EINT_POLARITY_SET		REG32_ADDR(SCP_EINT_BASE + 0x340)
-#define SCP_EINT_POLARITY_CLR		REG32_ADDR(SCP_EINT_BASE + 0x380)
-#define SCP_EINT_D0_EN			REG32_ADDR(SCP_EINT_BASE + 0x400)
-#define SCP_EINT_D1_EN			REG32_ADDR(SCP_EINT_BASE + 0x420)
-#define SCP_EINT_DBNC_GET		REG32_ADDR(SCP_EINT_BASE + 0x500)
-#define SCP_EINT_DBNC_SET		REG32_ADDR(SCP_EINT_BASE + 0x600)
-#define SCP_EINT_DBNC_CLR		REG32_ADDR(SCP_EINT_BASE + 0x700)
-
-#define SCP_PMICWP2P_BASE		(SCP_CFG_BASE + 0xB000)
-#define   PMICW_WACS_CMD		REG32(SCP_PMICWP2P_BASE + 0x200)
-#define   PMICW_WACS_RDATA		REG32(SCP_PMICWP2P_BASE + 0x204)
-#define   PMICW_WACS_VLDCLR		REG32(SCP_PMICWP2P_BASE + 0x208)
-#define SCP_SPMP2P_BASE			(SCP_CFG_BASE + 0xC000)
-#define SCP_DMA_BASE			(SCP_CFG_BASE + 0xD000)
-#define   DMA_ACKINT_CHX		REG32(SCP_DMA_BASE + 0x20)
-#define SCP_SPI0_BASE			(SCP_CFG_BASE + 0xF000)
-#define SCP_SPI1_BASE			(SCP_CFG_BASE + 0x10000)
-#define SCP_SPI2_BASE			(SCP_CFG_BASE + 0x11000)
-
-#define CACHE_ICACHE 0
-#define CACHE_DCACHE 1
-#define CACHE_COUNT 2
-#define SCP_CACHE_BASE			(SCP_CFG_BASE + 0x14000)
-#define SCP_CACHE_SEL(x)		(SCP_CACHE_BASE + (x)*0x3000)
-#define SCP_CACHE_CON(x)		REG32(SCP_CACHE_SEL(x))
-#define SCP_CACHE_CON_MCEN		BIT(0)
-#define SCP_CACHE_CON_CNTEN0		BIT(2)
-#define SCP_CACHE_CON_CNTEN1		BIT(3)
-#define SCP_CACHE_CON_CACHESIZE_SHIFT	8
-#define SCP_CACHE_CON_CACHESIZE_MASK	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_0KB	(0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_8KB	(0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_16KB	(0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_32KB	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_WAYEN		BIT(10)
-
-#define SCP_CACHE_OP(x)			REG32(SCP_CACHE_SEL(x) + 0x04)
-#define SCP_CACHE_OP_EN			BIT(0)
-#define SCP_CACHE_OP_OP_SHIFT		1
-#define SCP_CACHE_OP_OP_MASK		(0xf << SCP_CACHE_OP_OP_SHIFT)
-
-#define   OP_INVALIDATE_ALL_LINES		(0x1 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_ADDRESS	(0x2 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_SET_WAY	(0x4 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ALL_LINES		(0x9 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS	(0xa << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY	(0xc << SCP_CACHE_OP_OP_SHIFT)
-
-#define SCP_CACHE_OP_TADDR_SHIFT	5
-#define SCP_CACHE_OP_TADDR_MASK		(0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
-#define SCP_CACHE_LINE_SIZE		BIT(SCP_CACHE_OP_TADDR_SHIFT)
-
-/* Cache statistics */
-#define SCP_CACHE_HCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x08)
-#define SCP_CACHE_HCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x0c)
-#define SCP_CACHE_CCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x10)
-#define SCP_CACHE_CCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x14)
-#define SCP_CACHE_HCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x18)
-#define SCP_CACHE_HCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x1c)
-#define SCP_CACHE_CCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x20)
-#define SCP_CACHE_CCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x24)
-
-#define SCP_CACHE_REGION_EN(x)		REG32(SCP_CACHE_SEL(x) + 0x2c)
-
-#define SCP_CACHE_ENTRY_BASE(x)		(SCP_CACHE_SEL(x) + 0x2000)
-#define SCP_CACHE_ENTRY(x, reg)		REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
-#define SCP_CACHE_END_ENTRY_BASE(x)	(SCP_CACHE_SEL(x) + 0x2040)
-#define SCP_CACHE_END_ENTRY(x, reg)	REG32(SCP_CACHE_END_ENTRY_BASE(x) + \
-						(reg)*4)
-#define SCP_CACHE_ENTRY_C		BIT(8)
-#define SCP_CACHE_ENTRY_BASEADDR_MASK	(0xfffff << 12)
-
-/* ARMV7 regs */
-#define ARM_SCB_SCR			REG32(0xE000ED10)
-#define   SCR_DEEPSLEEP			BIT(2)
-
-/* AP regs */
-#define AP_BASE				0xA0000000
-#define TOPCK_BASE			AP_BASE /* Top clock */
-#define SCP_UART2_BASE			(AP_BASE + 0x01002000) /* AP UART0 */
-
-/* CLK_CFG_5 regs */
-#define AP_CLK_CFG_5		REG32(TOPCK_BASE + 0x0090)
-#define   PWRAP_ULPOSC_MASK	(0x3000000)
-#define   CLK26M			(0 << 24)
-#define   OSC_D16			(1 << 24)
-#define   OSC_D4			(2 << 24)
-#define   OSC_D8			(3 << 24)
-#define AP_CLK_CFG_5_CLR	REG32(TOPCK_BASE + 0x0098)
-#define   PWRAP_ULPOSC_CG	BIT(31)
-
-/* OSC meter */
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0104)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x010C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK            0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x26 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x25 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		(1 << 4)
-#define   CFG_FREQ_METER_ENABLE		(1 << 12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-
-/* GPIO */
-#define AP_GPIO_BASE			(AP_BASE + 0x00005000)
-/*
- * AP_GPIO_DIR
- * GPIO input/out direction, 1 bit per pin.
- * 0:input 1:output
- */
-#define AP_GPIO_DIR(n)			REG32(AP_GPIO_BASE + ((n) << 4))
-/*
- * AP_GPIO_DOUT, n in [0..5]
- * GPIO output level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DOUT(n)			REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
-/*
- * AP_GPIO_DIN, n in [0..5]
- * GPIO input level, 1 bit per pin
- * 0:low 1:high
- */
-#define AP_GPIO_DIN(n)			REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
-/*
- * AP_GPIO_MODE, n in [0..22]
- * Pin mode selection, 4 bit per pin
- * bit3   - write enable, set to 1 for hw to fetch bit2,1,0.
- * bit2-0 - mode 0 ~ 7
- */
-#define AP_GPIO_MODE(n)			REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
-#define AP_GPIO_TRAP			REG32(AP_GPIO_BASE + 0x6B0)
-#define AP_GPIO_UNIMPLEMENTED		REG32(AP_GPIO_BASE + 0x6C0)
-#define AP_GPIO_DBG			REG32(AP_GPIO_BASE + 0x6D0)
-#define AP_GPIO_BANK			REG32(AP_GPIO_BASE + 0x6E0)
-/* AP_GPIO_SEC, n in [0..5] */
-#define AP_GPIO_SEC(n)			REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
-
-/*
- * PLL ULPOSC
- * ULPOSC1:  AP_ULPOSC_CON[0] AP_ULPOSC_CON[1]
- * ULPOSC2:  AP_ULPOSC_CON[2] AP_ULPOSC_CON[3]
- * osc: 0 for ULPOSC1, 1 for ULPSOC2.
- */
-#define AP_ULPOSC_BASE0			(AP_BASE + 0xC700)
-#define AP_ULPOSC_BASE1			(AP_BASE + 0xC704)
-#define AP_ULPOSC_CON02(osc)		REG32(AP_ULPOSC_BASE0 + (osc) * 0x8)
-#define AP_ULPOSC_CON13(osc)		REG32(AP_ULPOSC_BASE1 + (osc) * 0x8)
-/*
- * AP_ULPOSC_CON[0,2]
- * bit0-5:   calibration
- * bit6-12:  I-band
- * bit13-16: F-band
- * bit17-22: div
- * bit23:    CP_EN
- * bit24-31: reserved
- */
-#define OSC_CALI_MSK			(0x3f << 0)
-#define OSC_CALI_BITS			6
-#define OSC_IBAND_MASK			(0x7f << 6)
-#define OSC_FBAND_MASK			(0x0f << 13)
-#define OSC_DIV_MASK			(0x1f << 17)
-#define OSC_DIV_BITS			5
-#define OSC_CP_EN			BIT(23)
-#define OSC_RESERVED_MASK		(0xff << 24)
-/* AP_ULPOSC_CON[1,3] */
-#define OSC_MOD_MASK			(0x03 << 0)
-#define OSC_DIV2_EN			BIT(2)
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#ifndef __ASSEMBLER__
-
-/*
- * Cortex-M4 mod
- * Available power saving features:
- * 1. FPU freeze - freeze FPU operand when FPU is not used
- * 2. LSU gating - gate LSU clock when not LSU operation
- * 3. Trace clk disable - gate trace clock
- * 4. DCM for CPU stall - gate CPU clock when CPU stall
- */
-#define CM4_MODIFICATION		REG32(0xE00FE000)
-#define CM4_DCM_FEATURE			REG32(0xE00FE004)
-/* UART, 16550 compatible */
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-#define UART_IRQ(n)			CONCAT2(SCP_IRQ_UART, n)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-
-/* Watchdog */
-#define SCP_WDT_BASE			(SCP_CFG_BASE + 0x84)
-#define SCP_WDT_REG(offset)		REG32(SCP_WDT_BASE + offset)
-#define SCP_WDT_CFG			SCP_WDT_REG(0)
-#define   SCP_WDT_FREQ			33825
-#define   SCP_WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   SCP_WDT_PERIOD(ms)		(SCP_WDT_FREQ * (ms) / 1000)
-#define   SCP_WDT_ENABLE		BIT(31)
-#define SCP_WDT_RELOAD			SCP_WDT_REG(4)
-#define   SCP_WDT_RELOAD_VALUE		1
-
-#endif /* !__ASSEMBLER__ */
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/mt8183/serial_reg.h b/chip/mt_scp/mt8183/serial_reg.h
deleted file mode 100644
index 5344566272..0000000000
--- a/chip/mt_scp/mt8183/serial_reg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * UART register map
- */
-
-#ifndef __CROS_EC_SERIAL_REG_H
-#define __CROS_EC_SERIAL_REG_H
-
-#include "registers.h"
-
-/* Number of hardware ports */
-#define HW_UART_PORTS 2
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* Data register
- *   (Read) Rcvr buffer register
- *   (Write) Xmit holding register
- */
-#define UART_DATA(n)			UART_REG(n, 0)
-/* (Write) Interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define UART_IER_RDI			BIT(0) /* Recv data int */
-#define UART_IER_THRI			BIT(1) /* Xmit holding register int */
-#define UART_IER_RLSI			BIT(2) /* Rcvr line status int */
-#define UART_IER_MSI			BIT(3) /* Modem status int */
-/* (Read) Interrupt ID register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define UART_IIR_NO_INT			BIT(0) /* No int pending */
-#define UART_IIR_ID_MASK		0x0e /* Interrupt ID mask */
-#define UART_IIR_MSI			0x00
-#define UART_IIR_THRI			0x02
-#define UART_IIR_RDI			0x04
-#define UART_IIR_RLSI			0x06
-#define UART_IIR_BUSY			0x07 /* DW APB busy */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define UART_FCR_ENABLE_FIFO		BIT(0) /* Enable FIFO */
-#define UART_FCR_CLEAR_RCVR		BIT(1) /* Clear rcvr FIFO */
-#define UART_FCR_CLEAR_XMIT		BIT(2) /* Clear xmit FIFO */
-#define UART_FCR_DMA_SELECT		BIT(3)
-/* FIFO trigger levels */
-#define UART_FCR_T_TRIG_00		0x00
-#define UART_FCR_T_TRIG_01		0x10
-#define UART_FCR_T_TRIG_10		0x20
-#define UART_FCR_T_TRIG_11		0x30
-#define UART_FCR_R_TRIG_00		0x00
-#define UART_FCR_R_TRIG_01		0x40
-#define UART_FCR_R_TRIG_10		0x80
-#define UART_FCR_R_TRIG_11		0x80
-/* (Write) Line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define UART_LCR_WLEN5			0 /* Word length 5 bits */
-#define UART_LCR_WLEN6			1
-#define UART_LCR_WLEN7			2
-#define UART_LCR_WLEN8			3
-#define UART_LCR_STOP			BIT(2) /* Stop bits: 1bit, 2bits */
-#define UART_LCR_PARITY			BIT(3) /* Parity enable */
-#define UART_LCR_EPAR			BIT(4) /* Even parity */
-#define UART_LCR_SPAR			BIT(5) /* Stick parity */
-#define UART_LCR_SBC			BIT(6) /* Set break control */
-#define UART_LCR_DLAB			BIT(7) /* Divisor latch access */
-/* (Write) Modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) Line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define UART_LSR_DR			BIT(0) /* Data ready */
-#define UART_LSR_OE			BIT(1) /* Overrun error */
-#define UART_LSR_PE			BIT(2) /* Parity error */
-#define UART_LSR_FE			BIT(3) /* Frame error */
-#define UART_LSR_BI			BIT(4) /* Break interrupt */
-#define UART_LSR_THRE			BIT(5) /* Xmit-hold-register empty */
-#define UART_LSR_TEMT			BIT(6) /* Xmit empty */
-#define UART_LSR_FIFOE			BIT(7) /* FIFO error */
-
-/* DLAB == 1 */
-
-/* (Write) Divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0) /* Low */
-#define UART_DLH(n)			UART_REG(n, 1) /* High */
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-#define UART_SAMPLE_COUNT(n)		UART_REG(n, 10)
-#define UART_SAMPLE_POINT(n)		UART_REG(n, 11)
-#define UART_RATE_FIX(n)		UART_REG(n, 13)
-
-#endif /* __CROS_EC_SERIAL_REG_H */
diff --git a/chip/mt_scp/mt8183/system.c b/chip/mt_scp/mt8183/system.c
deleted file mode 100644
index 03f39298c9..0000000000
--- a/chip/mt_scp/mt8183/system.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * SCP_GPR[0] b15-b0  - scratchpad
- * SCP_GPR[0] b31-b16 - saved_flags
- */
-
-int system_set_scratchpad(uint32_t value)
-{
-	/* Check if value fits in 16 bits */
-	if (value & 0xffff0000)
-		return EC_ERROR_INVAL;
-
-	SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value;
-
-	return EC_SUCCESS;
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = SCP_GPR[0] & 0xffff;
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void chip_pre_init(void)
-{
-}
-
-static void scp_cm4_mod(void)
-{
-	CM4_MODIFICATION = 3;
-	CM4_DCM_FEATURE = 3;
-}
-
-static void scp_enable_pirq(void)
-{
-	/* Enable all peripheral to SCP IRQ, except IPC0. */
-	SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE;
-	SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF;
-}
-
-void system_pre_init(void)
-{
-	/* CM4 Modification */
-	scp_cm4_mod();
-	/* Clock */
-	scp_enable_clock();
-	/* Peripheral IRQ */
-	scp_enable_pirq();
-	/* Init dram mapping (and cache) */
-	scp_memmap_init();
-	/* Disable jump (mt_scp has only RW) and enable MPU. */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	/* Remember that the software asked us to hard reboot */
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-
-	/* Reset flags are 32-bits, but save only 16 bits. */
-	ASSERT(!(save_flags >> 16));
-	SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff);
-
-	/* SCP can not hard reset itself */
-	ASSERT(!(flags & SYSTEM_RESET_HARD));
-
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* Set watchdog timer to small value, and spin wait for watchdog reset */
-	SCP_WDT_CFG = 0;
-	SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1);
-	watchdog_reload();
-	while (1)
-		;
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_reset_cause = SCP_GPR[1];
-
-	/* Set state to power-on */
-	SCP_PWRON_STATE = PWRON_DEFAULT;
-
-	if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) {
-		/* Reboot */
-		if (raw_reset_cause & PWRON_WATCHDOG)
-			flags |= EC_RESET_FLAG_WATCHDOG;
-		else if (raw_reset_cause & PWRON_RESET)
-			flags |= EC_RESET_FLAG_POWER_ON;
-		else
-			flags |= EC_RESET_FLAG_OTHER;
-	} else {
-		/* Power lost restart */
-		flags |= EC_RESET_FLAG_POWER_ON;
-	}
-	system_set_reset_flags(SCP_GPR[0] >> 16);
-	SCP_GPR[0] &= 0xffff;
-}
-
-int system_is_reboot_warm(void)
-{
-	const uint32_t cold_flags =
-		EC_RESET_FLAG_RESET_PIN |
-		EC_RESET_FLAG_POWER_ON  |
-		EC_RESET_FLAG_WATCHDOG  |
-		EC_RESET_FLAG_HARD      |
-		EC_RESET_FLAG_SOFT      |
-		EC_RESET_FLAG_HIBERNATE;
-
-	check_reset_cause();
-
-	return !(system_get_reset_flags() & cold_flags);
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
diff --git a/chip/mt_scp/mt8183/uart.c b/chip/mt_scp/mt8183/uart.c
deleted file mode 100644
index 7907f9537d..0000000000
--- a/chip/mt_scp/mt8183/uart.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "clock_chip.h"
-#include "console.h"
-#include "registers.h"
-#include "serial_reg.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console UART index */
-#define UARTN           CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-
-static uint8_t uart_done, tx_started;
-
-int uart_init_done(void)
-{
-	/*
-	 * TODO: AP UART support
-	 * When access AP UART port, wait for AP peripheral clock
-	 */
-	return uart_done;
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	tx_started = 0;
-
-	/* AP UART mode doesn't support interrupt */
-	if (UARTN >= SCP_UART_COUNT)
-		return;
-
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	/* Check xmit FIFO empty */
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	/* Check rcvr data ready */
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_DATA(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_DATA(UARTN);
-}
-
-void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2);
-void uart_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_IRQ(UARTN));
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-}
-
-DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2);
-void uart_rx_interrupt(void)
-{
-	uint8_t ier;
-
-	task_clear_pending_irq(UART_RX_IRQ(UARTN));
-	SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN);
-	uart_process();
-	ier = UART_IER(UARTN);
-	UART_IER(UARTN) = 0;
-	UART_IER(UARTN) = ier;
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-}
-#endif
-
-void uart_task(void)
-{
-#if (UARTN >= SCP_UART_COUNT)
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-#endif
-}
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	/*
-	 * UART clock source is set to ULPOSC1 / 10 below.
-	 *
-	 * TODO(b:134035444): We could get slightly more precise frequency by
-	 * using the _measured_ ULPOSC1 frequency (instead of the target).
-	 */
-	const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-	/* Init clock */
-#if UARTN == 0
-	SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
-#elif UARTN == 1
-	SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
-	SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
-#endif
-
-	/* Init and clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-	/* DLAB = 1 and update DLL DLH */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-	/* UART RX IRQ needs an extra enable */
-	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
-#endif
-	gpio_config_module(MODULE_UART, 1);
-	uart_done = 1;
-}
diff --git a/chip/mt_scp/mt8183/watchdog.c b/chip/mt_scp/mt8183/watchdog.c
deleted file mode 100644
index 74e2cad8e5..0000000000
--- a/chip/mt_scp/mt8183/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "panic.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t watchdog_timeout =
-		SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* Disable watchdog */
-	SCP_WDT_CFG = 0;
-	/* Enable watchdog */
-	SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout;
-	/* Reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8192/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c
deleted file mode 100644
index 43f570fc62..0000000000
--- a/chip/mt_scp/mt8192/clock.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
-	SCP_CLK_26M = CLK_SW_SEL_26M,
-	SCP_CLK_32K = CLK_SW_SEL_32K,
-	SCP_CLK_ULPOSC2 = CLK_SW_SEL_ULPOSC2,
-	SCP_CLK_ULPOSC1 = CLK_SW_SEL_ULPOSC1,
-};
-
-static struct opp_ulposc_cfg {
-	uint32_t osc;
-	uint32_t div;
-	uint32_t fband;
-	uint32_t mod;
-	uint32_t cali;
-	uint32_t target_mhz;
-} opp[] = {
-	{
-		.osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3,
-		.cali = 64,
-	},
-	{
-		.osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0,
-		.cali = 64,
-	},
-	{
-		.osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0,
-		.cali = 64,
-	},
-};
-
-static inline void clock_busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 *
-	 * `volatile' in order to avoid compiler to optimize the function out
-	 * (otherwise, the function will be eliminated).
-	 */
-	volatile int i = usec * 28;
-
-	while (--i)
-		;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
-	unsigned int val = 0;
-
-	/* set div */
-	val |= opp->div << OSC_DIV_SHIFT;
-	/* set F-band; I-band = 82 */
-	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
-	/* set calibration */
-	val |= opp->cali;
-	/* set control register 0 */
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	/* set mod */
-	val = opp->mod << OSC_MOD_SHIFT;
-	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
-	val |= 41 << OSC_RSV1_SHIFT;
-	/* set control register 1 */
-	AP_ULPOSC_CON1(opp->osc) = val;
-
-	/* bias = 64 */
-	AP_ULPOSC_CON2(opp->osc) = 64;
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
-				     uint32_t cali_val)
-{
-	uint32_t val;
-
-	val = AP_ULPOSC_CON0(opp->osc);
-	val &= ~OSC_CALI_MASK;
-	val |= cali_val;
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
-	uint32_t result = 0;
-	int cnt;
-
-	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* enable frequency meter, without start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* trigger frequency meter start */
-	AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN;
-
-	/*
-	 * Frequency meter counts cycles in 1 / (26 * 1024) second period.
-	 *   freq_in_hz = freq_counter * 26 * 1024
-	 *
-	 * The hardware takes 38us to count cycles. Delay up to 100us,
-	 * as clock_busy_udelay may not be accurate when sysclk is not 26Mhz
-	 * (e.g. when recalibrating/measuring after boot).
-	 */
-	for (cnt = 100; cnt > 0; --cnt) {
-		clock_busy_udelay(1);
-		if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_SCP_CFG_1);
-			break;
-		}
-	}
-
-	/* disable freq meter */
-	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
-
-	return result;
-}
-
-#define CAL_MIS_RATE	40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
-	uint32_t curr, target;
-
-	curr = clock_ulposc_measure_freq(opp->osc);
-	target = opp->target_mhz * 1024 / 26;
-
-	/* check if calibrated value is in the range of target value +- 4% */
-	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
-	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
-		return 1;
-	else
-		return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
-	uint32_t current_val = 0;
-	uint32_t target_val = opp->target_mhz * 1024 / 26;
-	uint32_t middle, min = 0, max = OSC_CALI_MASK;
-	uint32_t diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		clock_ulposc_config_cali(opp, middle);
-		current_val = clock_ulposc_measure_freq(opp->osc);
-
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	clock_ulposc_config_cali(opp, min);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_min = current_val - target_val;
-	else
-		diff_by_min = target_val - current_val;
-
-	clock_ulposc_config_cali(opp, max);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_max = current_val - target_val;
-	else
-		diff_by_max = target_val - current_val;
-
-	if (diff_by_min < diff_by_max)
-		cal_result = min;
-	else
-		cal_result = max;
-
-	clock_ulposc_config_cali(opp, cal_result);
-	if (!clock_ulposc_is_calibrated(opp))
-		assert(0);
-
-	return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
-	/* enable high speed clock */
-	SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
-	switch (osc) {
-	case 0:
-		/* after 150us, enable ULPOSC */
-		clock_busy_udelay(150);
-		SCP_CLK_ENABLE |= CLK_HIGH_CG;
-		break;
-	case 1:
-		/* turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* after 150us, turn on ULPOSC2 high core clock gate */
-		clock_busy_udelay(150);
-		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_high_disable(int osc)
-{
-	switch (osc) {
-	case 0:
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
-	/*
-	 * ULPOSC1(osc=0) is already
-	 * - calibrated
-	 * - enabled in coreboot
-	 * - used by pmic wrapper
-	 */
-	if (opp->osc != 0) {
-		clock_high_disable(opp->osc);
-		clock_ulposc_config_default(opp);
-		clock_high_enable(opp->osc);
-	}
-
-	/* Calibrate only if it is not accurate enough. */
-	if (!clock_ulposc_is_calibrated(opp))
-		opp->cali = clock_ulposc_process_cali(opp);
-
-#ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
-		opp->osc, opp->target_mhz, opp->cali);
-#endif
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
-	/*
-	 * DIV2 divider takes precedence over clock selection to prevent
-	 * over-clocking.
-	 */
-	if (src == SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL2;
-
-	SCP_CLK_SW_SEL = src;
-
-	if (src != SCP_CLK_ULPOSC1)
-		SCP_CLK_DIV_SEL = CLK_DIV_SEL1;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		CPRINTS("AP suspend");
-		clock_select_clock(SCP_CLK_ULPOSC1);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		CPRINTS("AP resume");
-		clock_select_clock(SCP_CLK_ULPOSC2);
-	}
-}
-
-void clock_init(void)
-{
-	int i;
-
-	/* select default 26M system clock */
-	clock_select_clock(SCP_CLK_26M);
-
-	/* set VREQ to HW mode */
-	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
-	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
-	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
-	/* set DDREN to auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
-	/* turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
-	/* calibrate ULPOSC */
-	for (i = 0; i < ARRAY_SIZE(opp); ++i)
-		clock_calibrate_ulposc(&opp[i]);
-
-	/* select ULPOSC2 high speed CPU clock */
-	clock_select_clock(SCP_CLK_ULPOSC2);
-
-	/* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */
-	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
-	/* enable default clock gate */
-	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-		CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
-	int i;
-
-	for (i = 0; i <= 1; ++i)
-		ccprintf("ULPOSC%u frequency: %u kHz\n",
-			 i + 1,
-			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
-			"Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h
deleted file mode 100644
index 5928ca0473..0000000000
--- a/chip/mt_scp/mt8192/clock_regs.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_26M		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x2)
-
-/* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0140)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-/* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x017C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x25 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x24 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON2_BASE		(AP_REG_BASE + 0xC2B8)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON2(osc) \
-		REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-31: reserved
- */
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
-/* AP_ULPOSC_CON1
- * bit0-7: 32K calibration
- * bit 8-15: rsv1
- * bit 16-23: rsv2
- * bit 24-25: mod
- * bit26: div2_en
- * bit27-31: reserved
- */
-#define OSC_RSV1_SHIFT			8
-#define OSC_RSV2_SHIFT			16
-#define OSC_MOD_SHIFT			24
-#define OSC_DIV2_EN			BIT(26)
-/* AP_ULPOSC_CON2
- * bit0-7: bias
- * bit8-31: reserved
- */
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
deleted file mode 100644
index 63eb1243b3..0000000000
--- a/chip/mt_scp/mt8192/intc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x0800001d
-#define SCP_INTC_IRQ_POL2		0x00000020
-#define SCP_INTC_GRP_LEN		3
-#define SCP_INTC_IRQ_COUNT		96
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_CCIF0			34
-#define SCP_IRQ_CCIF1			35
-/* 36 */
-#define SCP_IRQ_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-/* 40 */
-#define SCP_IRQ_DPMAIF			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_CPU_TICK1		54
-#define SCP_IRQ_MAD_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_I3C2_IBI_WAKE		58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-/* 72 */
-/* 76 */
-#define SCP_IRQ_I2C1_2			78
-#define SCP_IRQ_I2C2			79
-/* 80 */
-#define SCP_IRQ_AUD2AUDIODSP		80
-#define SCP_IRQ_AUD2AUDIODSP_2		81
-#define SCP_IRQ_CONN2ADSP_A2DPOL	82
-#define SCP_IRQ_CONN2ADSP_BTCVSD	83
-/* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO	84
-#define SCP_IRQ_PCIE2ADSP		85
-#define SCP_IRQ_APU2ADSP_ENGINE		86
-#define SCP_IRQ_APU2ADSP_MBOX		87
-/* 88 */
-#define SCP_IRQ_CCIF3			88
-#define SCP_IRQ_I2C_DMA0		89
-#define SCP_IRQ_I2C_DMA1		90
-#define SCP_IRQ_I2C_DMA2		91
-/* 92 */
-#define SCP_IRQ_I2C_DMA3		92
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
deleted file mode 100644
index 0ebb93cbb4..0000000000
--- a/chip/mt_scp/mt8192/uart.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8192 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
-	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO164 and GPIO165 to alt func 3 */
-	AP_GPIO_MODE20_CLR = 0x00770000;
-	AP_GPIO_MODE20_SET = 0x00330000;
-#elif UARTN == 1
-	SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
-#endif
-}
diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c
deleted file mode 100644
index 2f9b9a7808..0000000000
--- a/chip/mt_scp/mt8192/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
-	return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
-	return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 |
-		VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
-		VDEC_CAP_VP9_FRAME;
-}
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
deleted file mode 100644
index c81bd83595..0000000000
--- a/chip/mt_scp/mt8195/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Required chip modules
-chip-y+=$(CHIP_VARIANT)/uart.o
-chip-y+=$(CHIP_VARIANT)/clock.o
-chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c
deleted file mode 100644
index c6bf3cbc79..0000000000
--- a/chip/mt_scp/mt8195/clock.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks, PLL and power settings */
-
-#include <assert.h>
-#include <string.h>
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "csr.h"
-#include "ec_commands.h"
-#include "power.h"
-#include "registers.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
-
-enum scp_clock_source {
-	SCP_CLK_SYSTEM,
-	SCP_CLK_32K,
-	SCP_CLK_ULPOSC1,
-	SCP_CLK_ULPOSC2_LOW_SPEED,
-	SCP_CLK_ULPOSC2_HIGH_SPEED,
-};
-
-enum {
-	OPP_ULPOSC2_LOW_SPEED,
-	OPP_ULPOSC2_HIGH_SPEED,
-};
-
-static struct opp_ulposc_cfg {
-	uint32_t osc;
-	uint32_t div;
-	uint32_t fband;
-	uint32_t mod;
-	uint32_t cali;
-	uint32_t target_mhz;
-	uint32_t clk_div;
-} opp[] = {
-	[OPP_ULPOSC2_LOW_SPEED] = {
-		.osc = 1, .target_mhz = 326, .clk_div = CLK_DIV_SEL2, .div = 19,
-		.fband = 10, .mod = 0, .cali = 64, /* 326MHz / 2 = 163MHz */
-	},
-	[OPP_ULPOSC2_HIGH_SPEED] = {
-		.osc = 1, .target_mhz = 360, .clk_div = CLK_DIV_SEL1, .div = 21,
-		.fband = 10, .mod = 0, .cali = 64, /* 360MHz / 1 = 360MHz */
-	},
-};
-
-static inline void clock_busy_udelay(int usec)
-{
-	/*
-	 * Delaying by busy-looping, for place that can't use udelay because of
-	 * the clock not configured yet. The value 28 is chosen approximately
-	 * from experiment.
-	 *
-	 * `volatile' in order to avoid compiler to optimize the function out
-	 * (otherwise, the function will be eliminated).
-	 */
-	volatile int i = usec * 28;
-
-	while (--i)
-		;
-}
-
-static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
-{
-	uint32_t val = 0;
-
-	/* set mod, div2_en = 0, cp_en = 0 */
-	val |= opp->mod << OSC_MOD_SHIFT;
-	/* set div */
-	val |= opp->div << OSC_DIV_SHIFT;
-	/* set F-band, I-band = 82 */
-	val |= (opp->fband << OSC_FBAND_SHIFT) | (82 << OSC_IBAND_SHIFT);
-	/* set calibration */
-	val |= opp->cali;
-	/* set control register 0 */
-	AP_ULPOSC_CON0(opp->osc) = val;
-
-	clock_busy_udelay(50);
-
-	/* bias = 65 */
-	val = 65 << OSC_BIAS_SHIFT;
-	/* rsv2 = 0, rsv1 = 41, cali_32k = 0 */
-	val |= 41 << OSC_RSV1_SHIFT;
-	/* set control register 1 */
-	AP_ULPOSC_CON1(opp->osc) = val;
-
-	/* set settle time */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2);
-}
-
-static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
-				     uint32_t cali_val)
-{
-	uint32_t val;
-
-	val = AP_ULPOSC_CON0(opp->osc);
-	val &= ~OSC_CALI_MASK;
-	val |= cali_val;
-	AP_ULPOSC_CON0(opp->osc) = val;
-	opp->cali = cali_val;
-
-	clock_busy_udelay(50);
-}
-
-static uint32_t clock_ulposc_measure_freq(uint32_t osc)
-{
-	uint32_t result = 0;
-	int cnt;
-	uint32_t cali_0 = AP_CLK26CALI_0;
-	uint32_t cali_1 = AP_CLK26CALI_1;
-	uint32_t dbg_cfg = AP_CLK_DBG_CFG;
-	uint32_t misc_cfg = AP_CLK_MISC_CFG_0;
-
-	/* Set ckgen_load_cnt: CLK26CALI_1[25:16] */
-	AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT;
-
-	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
-
-	/* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
-
-	/* set meter divisor to 1, bit[31:24] = b00000000 */
-	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
-			    MISC_METER_DIV_1;
-
-	/* enable frequency meter, without start */
-	AP_CLK26CALI_0 |= CFG_FREQ_METER_ENABLE;
-
-	/* trigger frequency meter start */
-	AP_CLK26CALI_0 |= CFG_FREQ_METER_RUN;
-
-	clock_busy_udelay(45);
-
-	for (cnt = 10000; cnt > 0; --cnt) {
-		clock_busy_udelay(10);
-		if (!(AP_CLK26CALI_0 & CFG_FREQ_METER_RUN)) {
-			result = CFG_FREQ_COUNTER(AP_CLK26CALI_1);
-			break;
-		}
-	}
-
-	AP_CLK26CALI_0 = cali_0;
-	AP_CLK26CALI_1 = cali_1;
-	AP_CLK_DBG_CFG = dbg_cfg;
-	AP_CLK_MISC_CFG_0 = misc_cfg;
-
-	/* disable freq meter */
-	AP_CLK26CALI_0 &= ~CFG_FREQ_METER_ENABLE;
-
-	return result;
-}
-
-#define CAL_MIS_RATE	40
-static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
-{
-	uint32_t curr, target;
-
-	curr = clock_ulposc_measure_freq(opp->osc);
-	target = opp->target_mhz * 512 / 26;
-
-#ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n",
-		opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali);
-#endif
-
-	/* check if calibrated value is in the range of target value +- 4% */
-	if (curr > (target * (1000 - CAL_MIS_RATE) / 1000) &&
-	    curr < (target * (1000 + CAL_MIS_RATE) / 1000))
-		return 1;
-	else
-		return 0;
-}
-
-static uint32_t clock_ulposc_process_cali(struct opp_ulposc_cfg *opp)
-{
-	uint32_t current_val = 0;
-	uint32_t target_val = opp->target_mhz * 512 / 26;
-	uint32_t middle, min = 0, max = OSC_CALI_MASK;
-	uint32_t diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		clock_ulposc_config_cali(opp, middle);
-		current_val = clock_ulposc_measure_freq(opp->osc);
-
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	clock_ulposc_config_cali(opp, min);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_min = current_val - target_val;
-	else
-		diff_by_min = target_val - current_val;
-
-	clock_ulposc_config_cali(opp, max);
-	current_val = clock_ulposc_measure_freq(opp->osc);
-	if (current_val > target_val)
-		diff_by_max = current_val - target_val;
-	else
-		diff_by_max = target_val - current_val;
-
-	if (diff_by_min < diff_by_max)
-		cal_result = min;
-	else
-		cal_result = max;
-
-	clock_ulposc_config_cali(opp, cal_result);
-	if (!clock_ulposc_is_calibrated(opp))
-		assert(0);
-
-	return cal_result;
-}
-
-static void clock_high_enable(int osc)
-{
-	/* enable high speed clock */
-	SCP_CLK_ENABLE |= CLK_HIGH_EN;
-
-	switch (osc) {
-	case 0:
-		/* after 150us, enable ULPOSC */
-		clock_busy_udelay(150);
-		SCP_CLK_ENABLE |= CLK_HIGH_CG | CLK_HIGH_EN;
-
-		/* topck ulposc1 clk gating off */
-		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CK;
-		/* select topck ulposc1 as scp clk parent */
-		AP_CLK_CFG_29_CLR = ULPOSC1_CLK_SEL;
-
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		/* turn off ULPOSC2 high-core-disable switch */
-		SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB;
-		/* after 150us, scp requests ULPOSC2 high core clock */
-		clock_busy_udelay(150);
-		SCP_CLK_HIGH_CORE_CG |= HIGH_CORE_CG;
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-
-		/* topck ulposc2 clk gating off */
-		AP_CLK_CFG_29_CLR = PDN_F_ULPOSC_CORE_CK;
-		/* select topck ulposc2 as scp clk parent */
-		AP_CLK_CFG_29_CLR = ULPOSC2_CLK_SEL;
-
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_high_disable(int osc)
-{
-	switch (osc) {
-	case 0:
-		/* topck ulposc1 clk gating on */
-		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CK;
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CK_UPDATE;
-		clock_busy_udelay(50);
-
-		/* scp doesn't request ulposc1 clk */
-		SCP_CLK_ENABLE &= ~CLK_HIGH_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ENABLE &= ~CLK_HIGH_EN;
-		clock_busy_udelay(50);
-		break;
-	case 1:
-		/* topck ulposc2 clk gating on */
-		AP_CLK_CFG_29_SET = PDN_F_ULPOSC_CORE_CK;
-		AP_CLK_CFG_UPDATE3 = F_ULPOSC_CORE_CK_UPDATE;
-		clock_busy_udelay(50);
-
-		/* scp doesn't request ulposc2 clk */
-		SCP_CLK_HIGH_CORE_CG &= ~HIGH_CORE_CG;
-		clock_busy_udelay(50);
-		SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-		clock_busy_udelay(50);
-		break;
-	default:
-		break;
-	}
-}
-
-static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
-{
-	/*
-	 * ULPOSC1(osc=0) is already
-	 * - calibrated
-	 * - enabled in coreboot
-	 * - used by pmic wrapper
-	 */
-	if (opp->osc != 0) {
-		clock_high_disable(opp->osc);
-		clock_ulposc_config_default(opp);
-		clock_high_enable(opp->osc);
-	}
-
-	/* Calibrate only if it is not accurate enough. */
-	if (!clock_ulposc_is_calibrated(opp))
-		opp->cali = clock_ulposc_process_cali(opp);
-}
-
-static void clock_select_clock(enum scp_clock_source src)
-{
-	uint32_t sel;
-	uint32_t div;
-
-	switch (src) {
-	case SCP_CLK_SYSTEM:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_SYSTEM;
-		break;
-	case SCP_CLK_32K:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_32K;
-		break;
-	case SCP_CLK_ULPOSC1:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_ULPOSC1;
-		break;
-	case SCP_CLK_ULPOSC2_LOW_SPEED:
-		/* parking at scp system clk until ulposc clk is ready */
-		clock_select_clock(SCP_CLK_SYSTEM);
-
-		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_LOW_SPEED],
-					 opp[OPP_ULPOSC2_LOW_SPEED].cali);
-		div = opp[OPP_ULPOSC2_LOW_SPEED].clk_div;
-
-		sel = CLK_SW_SEL_ULPOSC2;
-		break;
-	case SCP_CLK_ULPOSC2_HIGH_SPEED:
-		/* parking at scp system clk until ulposc clk is ready */
-		clock_select_clock(SCP_CLK_SYSTEM);
-
-		clock_ulposc_config_cali(&opp[OPP_ULPOSC2_HIGH_SPEED],
-					 opp[OPP_ULPOSC2_HIGH_SPEED].cali);
-		div = opp[OPP_ULPOSC2_HIGH_SPEED].clk_div;
-
-		sel = CLK_SW_SEL_ULPOSC2;
-		break;
-	default:
-		div = CLK_DIV_SEL1;
-		sel = CLK_SW_SEL_SYSTEM;
-		break;
-	}
-
-	SCP_CLK_DIV_SEL = div;
-	SCP_CLK_SW_SEL = sel;
-}
-
-__override void
-power_chipset_handle_host_sleep_event(enum host_sleep_event state,
-				      struct host_sleep_event_context *ctx)
-{
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		CPRINTS("AP suspend");
-		clock_select_clock(SCP_CLK_32K);
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		CPRINTS("AP resume");
-		clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
-	}
-}
-
-void clock_init(void)
-{
-	uint32_t i;
-
-	/* select scp system clock (default 26MHz) */
-	clock_select_clock(SCP_CLK_SYSTEM);
-
-	/* set VREQ to HW mode */
-	SCP_CPU_VREQ_CTRL = VREQ_SEL | VREQ_DVFS_SEL;
-	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
-	SCP_SEC_CTRL &= ~VREQ_SECURE_DIS;
-
-	/* set DDREN to auto mode */
-	SCP_SYS_CTRL |= AUTO_DDREN;
-
-	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
-
-	/* turn off ULPOSC2 */
-	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
-
-	/* calibrate ULPOSC2 */
-	for (i = 0; i < ARRAY_SIZE(opp); ++i)
-		clock_calibrate_ulposc(&opp[i]);
-
-	/* select ULPOSC2 high speed SCP clock */
-	clock_select_clock(SCP_CLK_ULPOSC2_HIGH_SPEED);
-
-	/* select BCLK to use ULPOSC / 8 */
-	SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8;
-
-	/* enable default clock gate */
-	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-			  CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
-}
-
-#ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
-{
-	uint32_t osc;
-
-	for (osc = 0; osc <= OPP_ULPOSC2_HIGH_SPEED; ++osc)
-		ccprintf("ULPOSC%u frequency: %u kHz\n", osc + 1,
-			 clock_ulposc_measure_freq(osc) * 26 * 1000 / 512);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[ulposc]",
-			"Measure ULPOSC frequency");
-#endif
diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h
deleted file mode 100644
index 6e7ec6bdbb..0000000000
--- a/chip/mt_scp/mt8195/clock_regs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP clock module registers */
-
-#ifndef __CROS_EC_CLOCK_REGS_H
-#define __CROS_EC_CLOCK_REGS_H
-
-/* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_SYSTEM		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
-/* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x3)
-
-/* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_CFG_UPDATE3		REG32(TOPCK_BASE + 0x0010)
-#define   F_ULPOSC_CK_UPDATE		BIT(21)
-#define   F_ULPOSC_CORE_CK_UPDATE	BIT(22)
-#define AP_CLK_CFG_29_SET		REG32(TOPCK_BASE + 0x0180)
-#define AP_CLK_CFG_29_CLR		REG32(TOPCK_BASE + 0x0184)
-#define   ULPOSC1_CLK_SEL		(0x3 << 8)
-#define   PDN_F_ULPOSC_CK		BIT(15)
-#define   ULPOSC2_CLK_SEL		(0x3 << 16)
-#define   PDN_F_ULPOSC_CORE_CK		BIT(23)
-/* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x020C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x7f << 8)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x30 << 8)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x32 << 8)
-#define AP_CLK26CALI_0			REG32(TOPCK_BASE + 0x0218)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(7)
-#define AP_CLK26CALI_1			REG32(TOPCK_BASE + 0x021C)
-#define   CFG_CKGEN_LOAD_CNT		0x01ff0000
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x022C)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-/*
- * ULPOSC
- * osc: 0 for ULPOSC1, 1 for ULPOSC2.
- */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-/*
- * AP_ULPOSC_CON0
- * bit0-6: calibration
- * bit7-13: iband
- * bit14-17: fband
- * bit18-23: div
- * bit24: cp_en
- * bit25-26: mod
- * bit27: div2_en
- * bit28-31: reserved
- */
-#define OSC_CALI_SHIFT			0
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
-#define OSC_MOD_SHIFT			25
-#define OSC_DIV2_EN			BIT(27)
-/*
- * AP_ULPOSC_CON1
- * bit0-7: rsv1
- * bit8-15: rsv2
- * bit16-23: 32K calibration
- * bit24-31: bias
- */
-#define OSC_RSV1_SHIFT			0
-#define OSC_RSV2_SHIFT			8
-#define OSC_32KCALI_SHIFT		16
-#define OSC_BIAS_SHIFT			24
-
-#endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
deleted file mode 100644
index 87181c46ca..0000000000
--- a/chip/mt_scp/mt8195/intc.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INTC_H
-#define __CROS_EC_INTC_H
-
-/* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x044001dd
-#define SCP_INTC_IRQ_POL2		0xffffdfe0
-#define SCP_INTC_IRQ_POL3		0xfffffff3
-#define SCP_INTC_GRP_LEN		4
-#define SCP_INTC_IRQ_COUNT		127
-
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_GCE			34
-#define SCP_IRQ_MDP_GCE			35
-/* 36 */
-#define SCP_IRQ_VDEC			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_VDEC_LAT		38
-#define SCP_IRQ_VDEC1			39
-/* 40 */
-#define SCP_IRQ_VDEC1_LAT		40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_VDEC_INT_LINE_CNT	54
-#define SCP_IRQ_VOW_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_VENC			58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-#define SCP_IRQ_CAMSYS_29		70
-#define SCP_IRQ_CAMSYS_28		71
-/* 72 */
-#define SCP_IRQ_CAMSYS_5		72
-#define SCP_IRQ_CAMSYS_4		73
-#define SCP_IRQ_CAMSYS_3		74
-#define SCP_IRQ_CAMSYS_2		75
-/* 76 */
-#define SCP_IRQ_HDMIRX_PM_DVI_SQH	76
-#define SCP_IRQ_HDMIRX_RESERVED		77
-#define SCP_IRQ_NNA0_0			78
-#define SCP_IRQ_NNA0_1			79
-/* 80 */
-#define SCP_IRQ_NNA0_2			80
-#define SCP_IRQ_NNA1_0			81
-#define SCP_IRQ_NNA1_1			82
-#define SCP_IRQ_NNA1_2			83
-/* 84 */
-#define SCP_IRQ_JPEGENC			84
-#define SCP_IRQ_JPEGDEC			85
-#define SCP_IRQ_JPEGDEC_C2		86
-#define SCP_IRQ_VENC_C1			87
-/* 88 */
-#define SCP_IRQ_JPEGENC_C1		88
-#define SCP_IRQ_JPEGDEC_C1		89
-#define SCP_IRQ_HDMITX			90
-#define SCP_IRQ_HDMI2			91
-/* 92 */
-#define SCP_IRQ_EARC			92
-#define SCP_IRQ_CEC			93
-#define SCP_IRQ_HDMI_DEV_DET		94
-#define SCP_IRQ_HDMIRX_OUT_ARM_PHY	95
-/* 96 */
-#define SCP_IRQ_I2C2			96
-#define SCP_IRQ_I2C3			97
-#define SCP_IRQ_I3C2_IBI_WAKE		98
-#define SCP_IRQ_I3C3_IBI_WAKE		99
-/* 100 */
-#define SCP_IRQ_SYS_I2C_0		100
-#define SCP_IRQ_SYS_I2C_1		101
-#define SCP_IRQ_SYS_I2C_2		102
-#define SCP_IRQ_SYS_I2C_3		103
-/* 104 */
-#define SCP_IRQ_SYS_I2C_4		104
-#define SCP_IRQ_SYS_I2C_5		105
-#define SCP_IRQ_SYS_I2C_6		106
-#define SCP_IRQ_SYS_I2C_7		107
-/* 108 */
-#define SCP_IRQ_DISP2ADSP_0		108
-#define SCP_IRQ_DISP2ADSP_1		109
-#define SCP_IRQ_DISP2ADSP_2		110
-#define SCP_IRQ_DISP2ADSP_3		111
-/* 112 */
-#define SCP_IRQ_DISP2ADSP_4		112
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_0	113
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_1	114
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_2	115
-/* 116 */
-#define SCP_IRQ_GCE1_SECURE		116
-#define SCP_IRQ_GCE_SECURE		117
-
-#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
deleted file mode 100644
index 76674fa7d3..0000000000
--- a/chip/mt_scp/mt8195/uart.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module for MT8195 specific */
-
-#include "uart_regs.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-
-void uart_init_pinmux(void)
-{
-#if UARTN == 0
-	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
-	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO102 and GPIO103 to alt func 5 */
-	AP_GPIO_MODE12_CLR = 0x77000000;
-	AP_GPIO_MODE12_SET = 0x55000000;
-#endif
-}
diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c
deleted file mode 100644
index dc4b7b3397..0000000000
--- a/chip/mt_scp/mt8195/video.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "video.h"
-
-uint32_t video_get_enc_capability(void)
-{
-	return VENC_CAP_4K;
-}
-
-uint32_t video_get_dec_capability(void)
-{
-	return VDEC_CAP_MT21C | VDEC_CAP_MM21 |
-		VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
-		VDEC_CAP_VP9_FRAME;
-}
diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk
deleted file mode 100644
index ac7e13db77..0000000000
--- a/chip/mt_scp/rv32i_common/build.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# SCP specific files build
-#
-
-CORE:=riscv-rv32i
-
-# Required chip modules
-chip-y+=rv32i_common/cache.o
-chip-y+=rv32i_common/gpio.o
-chip-y+=rv32i_common/intc.o
-chip-y+=rv32i_common/memmap.o
-chip-y+=rv32i_common/system.o
-chip-y+=rv32i_common/uart.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RW/chip/$(CHIP)/rv32i_common/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
-
-# Optional chip modules
-chip-$(CONFIG_COMMON_TIMER)+=rv32i_common/hrtimer.o
-chip-$(CONFIG_IPI)+=rv32i_common/ipi.o rv32i_common/ipi_table.o
-chip-$(CONFIG_WATCHDOG)+=rv32i_common/watchdog.o
-chip-$(HAS_TASK_HOSTCMD)+=rv32i_common/hostcmd.o
diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c
deleted file mode 100644
index 62147590fe..0000000000
--- a/chip/mt_scp/rv32i_common/cache.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cache.h"
-#include "console.h"
-#include "csr.h"
-
-extern struct mpu_entry mpu_entries[];
-
-void cache_init(void)
-{
-	int i;
-	uint32_t mpu_en = 0;
-
-	/* disable mpu */
-	clear_csr(CSR_MCTREN, CSR_MCTREN_MPU);
-
-	/* enable i$, d$ */
-	set_csr(CSR_MCTREN, CSR_MCTREN_ICACHE);
-	set_csr(CSR_MCTREN, CSR_MCTREN_DCACHE);
-
-	/* invalidate icache and dcache */
-	cache_invalidate_icache();
-	cache_invalidate_dcache();
-
-	/* set mpu entries
-	 *
-	 * The pragma is for force GCC unrolls the following loop.
-	 * See b/172886808
-	 */
-#pragma GCC unroll 16
-	for (i = 0; i < NR_MPU_ENTRIES; ++i) {
-		if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) {
-			write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr |
-						mpu_entries[i].attribute);
-			write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr);
-			mpu_en |= BIT(i);
-		}
-	}
-
-	/* enable mpu entries */
-	write_csr(CSR_MPU_ENTRY_EN, mpu_en);
-
-	/* enable mpu */
-	set_csr(CSR_MCTREN, CSR_MCTREN_MPU);
-
-	/* fence */
-	asm volatile ("fence.i" ::: "memory");
-}
-
-#ifdef DEBUG
-/*
- * I for I-cache
- * D for D-cache
- * C for control transfer instructions (branch, jump, ret, interrupt, ...)
- */
-static enum {
-	PMU_SELECT_I = 0,
-	PMU_SELECT_D,
-	PMU_SELECT_C
-} pmu_select;
-
-int command_enable_pmu(int argc, char **argv)
-{
-	static const char * const selectors[] = {
-		[PMU_SELECT_I] = "I",
-		[PMU_SELECT_D] = "D",
-		[PMU_SELECT_C] = "C",
-	};
-	int i;
-
-	if (argc != 2)
-		return EC_ERROR_PARAM1;
-
-	for (i = 0; i < ARRAY_SIZE(selectors); ++i) {
-		if (strcasecmp(argv[1], selectors[i]) == 0) {
-			pmu_select = i;
-			break;
-		}
-	}
-	if (i >= ARRAY_SIZE(selectors))
-		return EC_ERROR_PARAM1;
-
-	ccprintf("select \"%s\"\n", selectors[pmu_select]);
-
-	/* disable all PMU */
-	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
-
-	/* reset cycle count */
-	write_csr(CSR_PMU_MCYCLE, 0);
-	write_csr(CSR_PMU_MCYCLEH, 0);
-	/* reset retired-instruction count */
-	write_csr(CSR_PMU_MINSTRET, 0);
-	write_csr(CSR_PMU_MINSTRETH, 0);
-	/* reset counter{3,4,5} */
-	write_csr(CSR_PMU_MHPMCOUNTER3, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER3H, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER4, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER4H, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER5, 0);
-	write_csr(CSR_PMU_MHPMCOUNTER5H, 0);
-
-	/* select different event IDs for counter{3,4,5} */
-	switch (pmu_select) {
-	case PMU_SELECT_I:
-		/* I-cache access count */
-		write_csr(CSR_PMU_MHPMEVENT3, 1);
-		/* I-cache miss count */
-		write_csr(CSR_PMU_MHPMEVENT4, 3);
-		/* noncacheable I-AXI access count */
-		write_csr(CSR_PMU_MHPMEVENT5, 5);
-		break;
-	case PMU_SELECT_D:
-		/* D-cache access count */
-		write_csr(CSR_PMU_MHPMEVENT3, 11);
-		/* D-cache miss count */
-		write_csr(CSR_PMU_MHPMEVENT4, 12);
-		/* noncacheable D-AXI access count */
-		write_csr(CSR_PMU_MHPMEVENT5, 14);
-		break;
-	case PMU_SELECT_C:
-		/* control transfer instruction count */
-		write_csr(CSR_PMU_MHPMEVENT3, 27);
-		/* control transfer miss-predict count */
-		write_csr(CSR_PMU_MHPMEVENT4, 28);
-		/* interrupt count */
-		write_csr(CSR_PMU_MHPMEVENT5, 29);
-		break;
-	}
-
-	cache_invalidate_icache();
-	cache_flush_dcache();
-
-	/* enable all PMU */
-	set_csr(CSR_PMU_MPMUCTR,
-		CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		CSR_PMU_MPMUCTR_H5);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu,
-			     "[I | D | C]", "Enable PMU");
-
-int command_disable_pmu(int argc, char **argv)
-{
-	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu,
-			     NULL, "Disable PMU");
-
-int command_show_pmu(int argc, char **argv)
-{
-	uint64_t val3, val4, val5;
-	uint32_t p;
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) |
-			read_csr(CSR_PMU_MCYCLE);
-	ccprintf("cycles: %lld\n", val3);
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) |
-			read_csr(CSR_PMU_MINSTRET);
-	ccprintf("retired instructions: %lld\n", val3);
-
-	val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER3);
-	val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER4);
-	val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER5);
-
-	if (val3)
-		p = val4 * 10000 / val3;
-	else
-		p = 0;
-
-	switch (pmu_select) {
-	case PMU_SELECT_I:
-		ccprintf("I-cache:\n");
-		ccprintf("  access: %lld\n", val3);
-		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
-		ccprintf("non-cacheable I: %lld\n", val5);
-		break;
-	case PMU_SELECT_D:
-		ccprintf("D-cache:\n");
-		ccprintf("  access: %lld\n", val3);
-		ccprintf("  miss: %lld (%d.%d%%)\n", val4, p / 100, p % 100);
-		ccprintf("non-cacheable D: %lld\n", val5);
-		break;
-	case PMU_SELECT_C:
-		ccprintf("control transfer instruction:\n");
-		ccprintf("  total: %lld\n", val3);
-		ccprintf("  miss-predict: %lld (%d.%d%%)\n",
-			 val4, p / 100, p % 100);
-		ccprintf("interrupts: %lld\n", val5);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(show_pmu, command_show_pmu, NULL, "Show PMU");
-#endif
diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h
deleted file mode 100644
index 13e5ad1a42..0000000000
--- a/chip/mt_scp/rv32i_common/cache.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CACHE_H
-#define __CROS_EC_CACHE_H
-
-#include "common.h"
-#include "csr.h"
-#include "stdint.h"
-#include "util.h"
-
-/* rs1 0~31 register X0~X31 */
-#define COP(rs1) (((rs1) << 15) | 0x400f)
-
-#define COP_OP_BARRIER_ICACHE		0x0
-#define COP_OP_INVALIDATE_ICACHE	0x8
-#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
-
-#define COP_OP_BARRIER_DCACHE		0x10
-#define COP_OP_WRITEBACK_DCACHE		0x14
-#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
-#define COP_OP_INVALIDATE_DCACHE	0x18
-#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
-/* FLUSH = WRITEBACK + INVALIDATE */
-#define COP_OP_FLUSH_DCACHE		0x1C
-#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
-
-static inline void cache_op_all(uint32_t op)
-{
-	register int t0 asm("t0") = op;
-	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-}
-
-static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
-{
-	size_t offset;
-	register int t0 asm("t0");
-
-	/* NOTE: cache operations must use 32 byte aligned address */
-	if (addr & GENMASK(3, 0))
-		return EC_ERROR_INVAL;
-
-	for (offset = 0; offset < length; offset += 4) {
-		t0 = addr + offset + op;
-		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-	}
-
-	return EC_SUCCESS;
-}
-
-/* memory barrier of I$ */
-static inline void cache_barrier_icache(void)
-{
-	cache_op_all(COP_OP_BARRIER_ICACHE);
-}
-
-/* invalidate all I$ */
-static inline void cache_invalidate_icache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_ICACHE);
-}
-
-/* invalidate a range of I$ */
-static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
-}
-
-/* memory barrier of D$ */
-static inline void cache_barrier_dcache(void)
-{
-	cache_op_all(COP_OP_BARRIER_DCACHE);
-}
-
-/* writeback all D$ */
-static inline void cache_writeback_dcache(void)
-{
-	cache_op_all(COP_OP_WRITEBACK_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback a range of D$ */
-static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-/* invalidate all D$ */
-static inline void cache_invalidate_dcache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_DCACHE);
-}
-
-/* invalidate a range of D$ */
-static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
-}
-
-/* writeback and invalidate all D$ */
-static inline void cache_flush_dcache(void)
-{
-	cache_op_all(COP_OP_FLUSH_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback and invalidate a range of D$ */
-static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-struct mpu_entry {
-	/* 1k alignment and the address is inclusive */
-	uintptr_t start_addr;
-	/* 1k alignment in 4GB boundary and non-inclusive */
-	uintptr_t end_addr;
-	/* MPU_ATTR */
-	uint32_t attribute;
-};
-
-void cache_init(void);
-
-#ifdef DEBUG
-int command_enable_pmu(int argc, char **argv);
-int command_disable_pmu(int argc, char **argv);
-int command_show_pmu(int argc, char **argv);
-#endif
-
-#endif /* #ifndef __CROS_EC_CACHE_H */
diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h
deleted file mode 100644
index ac53d51732..0000000000
--- a/chip/mt_scp/rv32i_common/config_chip.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/riscv-rv32i/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_PROGRAM_MEMORY_BASE_LOAD 0x10500000
-#define CONFIG_MAPPED_STORAGE_BASE 0
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-#undef CONFIG_LID_SWITCH
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 640
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 488
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-#define ULTRA_TASK_STACK_SIZE 1056
-#define TRENTA_TASK_STACK_SIZE 1184
-
-/* TODO: need to confirm, placeholder */
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-#undef CONFIG_TASK_PROFILING
-/* TODO: not yet supported */
-#undef CONFIG_MPU
-/* TODO: core/riscv-rv32i pollution */
-#define __ram_code
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h
deleted file mode 100644
index 7c767d0592..0000000000
--- a/chip/mt_scp/rv32i_common/csr.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Control and status register */
-
-/* TODO: move to core/riscv-rv32i? */
-
-#ifndef __CROS_EC_CSR_H
-#define __CROS_EC_CSR_H
-
-#include "common.h"
-
-static inline uint32_t read_csr(uint32_t reg)
-{
-	uint32_t val;
-
-	asm volatile("csrr %0, %1" : "=r"(val) : "i"(reg));
-	return val;
-}
-
-static inline void write_csr(uint32_t reg, uint32_t val)
-{
-	asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val));
-}
-
-static inline uint32_t set_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-static inline uint32_t clear_csr(uint32_t reg, uint32_t bit)
-{
-	uint32_t val;
-
-	asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
-	return val;
-}
-
-/* VIC */
-#define CSR_VIC_MICAUSE		(0x5c0)
-#define CSR_VIC_MIEMS		(0x5c2)
-#define CSR_VIC_MIPEND_G0	(0x5d0)
-#define CSR_VIC_MIMASK_G0	(0x5d8)
-#define CSR_VIC_MIWAKEUP_G0	(0x5e0)
-#define CSR_VIC_MILSEL_G0	(0x5e8)
-#define CSR_VIC_MIEMASK_G0	(0x5f0)
-
-/* centralized control enable */
-#define CSR_MCTREN		(0x7c0)
-/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
-#define   CSR_MCTREN_ICACHE	BIT(0)
-#define   CSR_MCTREN_DCACHE	BIT(1)
-#define   CSR_MCTREN_ITCM	BIT(2)
-#define   CSR_MCTREN_DTCM	BIT(3)
-#define   CSR_MCTREN_BTB	BIT(4)
-#define   CSR_MCTREN_RAS	BIT(5)
-#define   CSR_MCTREN_VIC	BIT(6)
-#define   CSR_MCTREN_CG		BIT(7)
-#define   CSR_MCTREN_MPU	BIT(8)
-
-/* MPU */
-#define CSR_MPU_ENTRY_EN	(0x9c0)
-#define CSR_MPU_LITCM		(0x9dc)
-#define CSR_MPU_LDTCM		(0x9dd)
-#define CSR_MPU_HITCM		(0x9de)
-#define CSR_MPU_HDTCM		(0x9df)
-#define CSR_MPU_L(n)		(0x9e0 + (n))
-#define CSR_MPU_H(n)		(0x9f0 + (n))
-/* MPU attributes: set if permitted */
-/* Privilege, machine mode in RISC-V.  We don't use the flag because
- * we don't separate user / machine mode in EC OS. */
-#define   MPU_ATTR_P		BIT(5)
-/* Readable */
-#define   MPU_ATTR_R		BIT(6)
-/* Writable */
-#define   MPU_ATTR_W		BIT(7)
-/* Cacheable */
-#define   MPU_ATTR_C		BIT(8)
-/* Bufferable */
-#define   MPU_ATTR_B		BIT(9)
-
-/* PMU */
-#define CSR_PMU_MPMUCTR		(0xbc0)
-#define   CSR_PMU_MPMUCTR_C	BIT(0)
-#define   CSR_PMU_MPMUCTR_I	BIT(1)
-#define   CSR_PMU_MPMUCTR_H3	BIT(2)
-#define   CSR_PMU_MPMUCTR_H4	BIT(3)
-#define   CSR_PMU_MPMUCTR_H5	BIT(4)
-
-#define CSR_PMU_MCYCLE		(0xb00)
-#define CSR_PMU_MINSTRET	(0xb02)
-#define CSR_PMU_MHPMCOUNTER3	(0xb03)
-#define CSR_PMU_MHPMCOUNTER4	(0xb04)
-#define CSR_PMU_MHPMCOUNTER5	(0xb05)
-
-#define CSR_PMU_MCYCLEH		(0xb80)
-#define CSR_PMU_MINSTRETH	(0xb82)
-#define CSR_PMU_MHPMCOUNTER3H	(0xb83)
-#define CSR_PMU_MHPMCOUNTER4H	(0xb84)
-#define CSR_PMU_MHPMCOUNTER5H	(0xb85)
-
-#define CSR_PMU_MHPMEVENT3	(0x323)
-#define CSR_PMU_MHPMEVENT4	(0x324)
-#define CSR_PMU_MHPMEVENT5	(0x325)
-
-#endif /* __CROS_EC_CSR_H */
diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c
deleted file mode 100644
index 0ca3e3ac25..0000000000
--- a/chip/mt_scp/rv32i_common/gpio.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module */
-
-#include "gpio.h"
-
-void gpio_pre_init(void)
-{
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-}
diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c
deleted file mode 100644
index 42a463ee56..0000000000
--- a/chip/mt_scp/rv32i_common/hostcmd.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "host_command.h"
-#include "ipi_chip.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-#define HOSTCMD_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */
-#define HOSTCMD_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4)
-#define HOSTCMD_TYPE_HOSTCMD 1
-#define HOSTCMD_TYPE_HOSTEVENT 2
-
-/*
- * hostcmd and hostevent share the same IPI ID, and use first byte type to
- * indicate its type.
- */
-static struct hostcmd_data {
-	const uint8_t type;
-	/* To be compatible with CONFIG_HOSTCMD_ALIGNED */
-	uint8_t response[HOSTCMD_MAX_RESPONSE_SIZE] __aligned(4);
-} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD };
-BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
-
-/* Size of the rpmsg device name, should sync across kernel and EC. */
-#define RPMSG_NAME_SIZE 32
-
-/*
- * The layout of name service message.
- * This should sync across kernel and EC.
- */
-struct rpmsg_ns_msg {
-	/* Name of the corresponding rpmsg_driver. */
-	char name[RPMSG_NAME_SIZE];
-	/* IPC ID */
-	uint32_t addr;
-};
-
-static void hostcmd_send_response_packet(struct host_packet *pkt)
-{
-	int ret;
-
-	ret = ipi_send(SCP_IPI_HOST_COMMAND, &hc_cmd_obj,
-		       pkt->response_size +
-			       offsetof(struct hostcmd_data, response),
-		       1);
-	if (ret)
-		CPRINTS("failed to %s(), ret=%d", __func__, ret);
-}
-
-static void hostcmd_handler(int32_t id, void *buf, uint32_t len)
-{
-	static struct host_packet packet;
-	uint8_t *in_msg = buf;
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-	int i;
-
-	if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-		CPRINTF("in_msg=[");
-		for (i = 0; i < len; i++)
-			CPRINTF("%02x ", in_msg[i]);
-		CPRINTF("]\n");
-		return;
-	}
-
-	/* Protocol version 3 */
-
-	packet.send_response = hostcmd_send_response_packet;
-
-	/*
-	 * Just assign the buffer to request, host_packet_receive
-	 * handles the buffer copy.
-	 */
-	packet.request = (void *)r;
-	packet.request_temp = NULL;
-	packet.request_max = HOSTCMD_MAX_REQUEST_SIZE;
-	packet.request_size = host_request_expected_size(r);
-
-	packet.response = hc_cmd_obj.response;
-	/* Reserve space for the preamble and trailing byte */
-	packet.response_max = HOSTCMD_MAX_RESPONSE_SIZE;
-	packet.response_size = 0;
-
-	packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&packet);
-}
-DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0);
-
-/*
- * Get protocol information
- */
-static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = HOSTCMD_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = HOSTCMD_MAX_RESPONSE_SIZE;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, hostcmd_get_protocol_info,
-		     EC_VER_MASK(0));
-
-void hostcmd_init(void)
-{
-	int ret;
-	struct rpmsg_ns_msg ns_msg;
-
-	if (IS_ENABLED(CONFIG_RPMSG_NAME_SERVICE)) {
-		ns_msg.addr = SCP_IPI_HOST_COMMAND;
-		strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE);
-		ret = ipi_send(SCP_IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1);
-		if (ret)
-			CPRINTS("Failed to announce host command channel");
-	}
-}
diff --git a/chip/mt_scp/rv32i_common/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h
deleted file mode 100644
index b93f1e725d..0000000000
--- a/chip/mt_scp/rv32i_common/hostcmd.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_HOSTCMD_H
-#define __CROS_EC_HOSTCMD_H
-
-/* Initialize hostcmd. */
-void hostcmd_init(void);
-
-#endif /* __CROS_EC_HOSTCMD_H */
diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c
deleted file mode 100644
index 89ffaa2fca..0000000000
--- a/chip/mt_scp/rv32i_common/hrtimer.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * High-res hardware timer
- *
- * SCP hardware 32bit count down timer can be configured to source clock from
- * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
- * source, countdown mode and converts to micro second value matching common
- * timer.
- */
-
-#include "common.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-
-#define TIMER_SYSTEM 5
-#define TIMER_EVENT 3
-#define TIMER_CLOCK_MHZ 32.5
-#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1)
-
-/* High 32-bit for system timer. */
-static uint8_t sys_high;
-/* High 32-bit for event timer. */
-static uint8_t event_high;
-
-static void timer_enable(int n)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_EN;
-	SCP_CORE0_TIMER_EN(n) |= TIMER_EN;
-}
-
-static void timer_disable(int n)
-{
-	SCP_CORE0_TIMER_EN(n) &= ~TIMER_EN;
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_IRQ_CTRL(n) &= ~TIMER_IRQ_EN;
-}
-
-static int timer_is_irq(int n)
-{
-	return SCP_CORE0_TIMER_IRQ_CTRL(n) & TIMER_IRQ_STATUS;
-}
-
-static void timer_ack_irq(int n)
-{
-	SCP_CORE0_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLR;
-}
-
-static void timer_set_reset_value(int n, uint32_t reset_value)
-{
-	/* cannot be changed when timer is enabled */
-	SCP_CORE0_TIMER_RST_VAL(n) = reset_value;
-}
-
-static void timer_set_clock(int n, uint32_t clock_source)
-{
-	SCP_CORE0_TIMER_EN(n) =
-		(SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source;
-}
-
-static void timer_reset(int n)
-{
-	timer_disable(n);
-	timer_ack_irq(n);
-	timer_set_reset_value(n, 0xffffffff);
-	timer_set_clock(n, TIMER_CLK_SRC_32K);
-}
-
-/* Convert hardware countdown timer to 64bit countup ticks. */
-static uint64_t timer_read_raw_system(void)
-{
-	uint32_t timer_ctrl = SCP_CORE0_TIMER_IRQ_CTRL(TIMER_SYSTEM);
-	uint32_t sys_high_adj = sys_high;
-
-	/*
-	 * If an IRQ is pending, but has not been serviced yet, adjust the
-	 * sys_high value.
-	 */
-	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1)
-					: (TIMER_CLOCK_MHZ - 1);
-
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM));
-}
-
-static uint64_t timer_read_raw_event(void)
-{
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_CORE0_TIMER_CUR_VAL(TIMER_EVENT));
-}
-
-static void timer_reload(int n, uint32_t value)
-{
-	timer_disable(n);
-	timer_set_reset_value(n, value);
-	timer_enable(n);
-}
-
-static int timer_reload_event_high(void)
-{
-	if (event_high) {
-		if (SCP_CORE0_TIMER_RST_VAL(TIMER_EVENT) == 0xffffffff)
-			timer_enable(TIMER_EVENT);
-		else
-			timer_reload(TIMER_EVENT, 0xffffffff);
-		event_high--;
-		return 1;
-	}
-
-	timer_disable(TIMER_EVENT);
-	return 0;
-}
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	int t;
-
-	/* enable clock gate */
-	SCP_SET_CLK_CG |= CG_TIMER_MCLK | CG_TIMER_BCLK;
-
-	/* reset all timer, select 32768Hz clock source */
-	for (t = 0; t < NUM_TIMERS; ++t)
-		timer_reset(t);
-
-	/* System timestamp timer */
-	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_BCLK);
-	sys_high = TIMER_CLOCK_MHZ - 1;
-	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM));
-	timer_enable(TIMER_SYSTEM);
-
-	/* Event tick timer */
-	timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_BCLK);
-	task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT));
-
-	return SCP_IRQ_TIMER(TIMER_SYSTEM);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return timer_read_raw_system() / TIMER_CLOCK_MHZ;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* c1ea4, magic number for clear state */
-	timer_disable(TIMER_EVENT);
-	timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4);
-	event_high = 0;
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ;
-	uint64_t now_raw = timer_read_raw_system();
-	uint32_t event_deadline;
-
-	if (deadline_raw > now_raw) {
-		deadline_raw -= now_raw;
-		event_deadline = (uint32_t)deadline_raw;
-		event_high = deadline_raw >> 32;
-	} else {
-		event_deadline = 1;
-		event_high = 0;
-	}
-
-	if (event_deadline)
-		timer_reload(TIMER_EVENT, event_deadline);
-	else
-		timer_reload_event_high();
-}
-
-static void irq_group6_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case SCP_IRQ_TIMER(TIMER_EVENT):
-		if (timer_is_irq(TIMER_EVENT)) {
-			timer_ack_irq(TIMER_EVENT);
-
-			if (!timer_reload_event_high())
-				process_timers(0);
-
-			task_clear_pending_irq(ec_int);
-		}
-		break;
-	case SCP_IRQ_TIMER(TIMER_SYSTEM):
-		/* If this is a hardware irq, check overflow */
-		if (!in_soft_interrupt_context()) {
-			timer_ack_irq(TIMER_SYSTEM);
-
-			if (sys_high) {
-				--sys_high;
-				process_timers(0);
-			} else {
-				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ - 1;
-				process_timers(1);
-			}
-
-			task_clear_pending_irq(ec_int);
-		} else {
-			process_timers(0);
-		}
-		break;
-	}
-}
-DECLARE_IRQ(6, irq_group6_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c
deleted file mode 100644
index 7e6b39e1f2..0000000000
--- a/chip/mt_scp/rv32i_common/intc.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* INTC control module */
-
-#include "console.h"
-#include "csr.h"
-#include "intc.h"
-#include "registers.h"
-
-/*
- * INTC_GRP_0 is reserved.  See swirq of syscall_handler() in
- * core/riscv-rv32i/task.c for more details.
- *
- * Lower group has higher priority.  Group 0 has highest priority.
- */
-enum INTC_GROUP {
-	INTC_GRP_0 = 0x0,
-	INTC_GRP_1,
-	INTC_GRP_2,
-	INTC_GRP_3,
-	INTC_GRP_4,
-	INTC_GRP_5,
-	INTC_GRP_6,
-	INTC_GRP_7,
-	INTC_GRP_8,
-	INTC_GRP_9,
-	INTC_GRP_10,
-	INTC_GRP_11,
-	INTC_GRP_12,
-	INTC_GRP_13,
-	INTC_GRP_14,
-};
-
-#ifdef BOARD_ASURADA_SCP
-static struct {
-	uint8_t group;
-} irqs[SCP_INTC_IRQ_COUNT] = {
-	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
-	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
-	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
-	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
-	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
-	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
-	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
-	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
-	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF0]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF1]			= { INTC_GRP_0 },
-	/* 36 */
-	[SCP_IRQ_CCIF2]			= { INTC_GRP_0 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB0]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB1]			= { INTC_GRP_0 },
-	/* 40 */
-	[SCP_IRQ_DPMAIF]		= { INTC_GRP_0 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
-	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
-	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
-	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_CPU_TICK1]		= { INTC_GRP_0 },
-	[SCP_IRQ_MAD_DATAIN]		= { INTC_GRP_0 },
-	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
-	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
-	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
-	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	/* 72 */
-	/* 76 */
-	[SCP_IRQ_I2C1_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	/* 80 */
-	[SCP_IRQ_AUD2AUDIODSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_AUD2AUDIODSP_2]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_A2DPOL]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_BTCVSD]	= { INTC_GRP_0 },
-	/* 84 */
-	[SCP_IRQ_CONN2ADSP_BLEISO]	= { INTC_GRP_0 },
-	[SCP_IRQ_PCIE2ADSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_ENGINE]	= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_MBOX]		= { INTC_GRP_0 },
-	/* 88 */
-	[SCP_IRQ_CCIF3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA0]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA1]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA2]		= { INTC_GRP_0 },
-	/* 92 */
-	[SCP_IRQ_I2C_DMA3]		= { INTC_GRP_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
-#endif
-
-#ifdef BOARD_CHERRY_SCP
-static struct {
-	uint8_t group;
-} irqs[SCP_INTC_IRQ_COUNT] = {
-	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
-	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
-	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
-	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
-	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
-	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
-	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
-	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
-	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_GCE]			= { INTC_GRP_0 },
-	[SCP_IRQ_MDP_GCE]		= { INTC_GRP_0 },
-	/* 36 */
-	[SCP_IRQ_VDEC]			= { INTC_GRP_8 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_VDEC1]			= { INTC_GRP_8 },
-	/* 40 */
-	[SCP_IRQ_VDEC1_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
-	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
-	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
-	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_INT_LINE_CNT]	= { INTC_GRP_0 },
-	[SCP_IRQ_VOW_DATAIN]		= { INTC_GRP_0 },
-	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC]			= { INTC_GRP_8 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
-	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
-	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
-	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_29]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_28]		= { INTC_GRP_0 },
-	/* 72 */
-	[SCP_IRQ_CAMSYS_5]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_3]		= { INTC_GRP_0 },
-	[SCP_IRQ_CAMSYS_2]		= { INTC_GRP_0 },
-	/* 76 */
-	[SCP_IRQ_HDMIRX_PM_DVI_SQH]	= { INTC_GRP_0 },
-	[SCP_IRQ_HDMIRX_RESERVED]	= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_1]		= { INTC_GRP_0 },
-	/* 80 */
-	[SCP_IRQ_NNA0_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_2]		= { INTC_GRP_0 },
-	/* 84 */
-	[SCP_IRQ_JPEGENC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C2]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC_C1]		= { INTC_GRP_8 },
-	/* 88 */
-	[SCP_IRQ_JPEGENC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMITX]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	/* 92 */
-	[SCP_IRQ_EARC]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
-	/* 96 */
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C3_IBI_WAKE]		= { INTC_GRP_0 },
-	/* 100 */
-	[SCP_IRQ_SYS_I2C_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_3]		= { INTC_GRP_0 },
-	/* 104 */
-	[SCP_IRQ_SYS_I2C_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_5]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_6]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_7]		= { INTC_GRP_0 },
-	/* 108 */
-	[SCP_IRQ_DISP2ADSP_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_3]		= { INTC_GRP_0 },
-	/* 112 */
-	[SCP_IRQ_DISP2ADSP_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_0]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_1]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_2]	= { INTC_GRP_0 },
-	/* 116 */
-	[SCP_IRQ_GCE1_SECURE]		= { INTC_GRP_0 },
-	[SCP_IRQ_GCE_SECURE]		= { INTC_GRP_0 },
-};
-BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
-#endif
-
-/*
- * Find current interrupt source.
- *
- * Lower group has higher priority.
- * Higher INT number has higher priority.
- */
-int chip_get_ec_int(void)
-{
-	extern volatile int ec_int;
-	unsigned int group, sta;
-	int word;
-
-	if (!SCP_CORE0_INTC_IRQ_OUT)
-		goto error;
-
-	group = read_csr(CSR_VIC_MICAUSE);
-
-	for (word = SCP_INTC_GRP_LEN - 1; word >= 0; --word) {
-		sta = SCP_CORE0_INTC_IRQ_GRP_STA(group, word);
-		if (sta) {
-			ec_int = __fls(sta) + word * 32;
-			return ec_int;
-		}
-	}
-
-error:
-	/* unreachable, SCP crashes and dumps registers after returning */
-	return -1;
-}
-
-int chip_get_intc_group(int irq)
-{
-	return irqs[irq].group;
-}
-
-void chip_enable_irq(int irq)
-{
-	unsigned int word, group, mask;
-
-	word = SCP_INTC_WORD(irq);
-	group = irqs[irq].group;
-	mask = BIT(SCP_INTC_BIT(irq));
-
-	/* disable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) &= ~mask;
-	/* set group */
-	SCP_CORE0_INTC_IRQ_GRP(group, word) |= mask;
-	/* set as a wakeup source */
-	SCP_CORE0_INTC_SLP_WAKE_EN(word) |= mask;
-	/* enable interrupt */
-	SCP_CORE0_INTC_IRQ_EN(word) |= mask;
-}
-
-void chip_disable_irq(int irq)
-{
-	/*
-	 * Disabling INTC IRQ in runtime is unstable in MT8192 SCP.
-	 * See b/163682416#comment17.
-	 *
-	 * Ideally, this function will be removed by LTO.
-	 */
-	ccprints("WARNING: %s is unsupported", __func__);
-}
-
-void chip_clear_pending_irq(int irq)
-{
-	unsigned int group = irqs[irq].group;
-
-	/* must clear interrupt source before writing this */
-	write_csr(CSR_VIC_MIEMS, group);
-}
-
-int chip_trigger_irq(int irq)
-{
-	extern volatile int ec_int;
-
-	ec_int = irq;
-	return irqs[irq].group;
-}
-
-void chip_init_irqs(void)
-{
-	unsigned int word, group;
-
-	/* INTC init */
-	/* clear enable and wakeup settings */
-	for (word = 0; word < SCP_INTC_GRP_LEN; ++word) {
-		SCP_CORE0_INTC_IRQ_EN(word) = 0x0;
-		SCP_CORE0_INTC_SLP_WAKE_EN(word) = 0x0;
-
-		/* clear group settings */
-		for (group = 0; group < SCP_INTC_GRP_COUNT; ++group)
-			SCP_CORE0_INTC_IRQ_GRP(group, word) = 0x0;
-	}
-	/* reset to default polarity */
-	SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0;
-	SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1;
-	SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2;
-#if SCP_INTC_GRP_LEN > 3
-	SCP_CORE0_INTC_IRQ_POL(3) = SCP_INTC_IRQ_POL3;
-#endif
-
-	/* GVIC init */
-	/* enable all groups as interrupt sources */
-	write_csr(CSR_VIC_MIMASK_G0, 0xffffffff);
-	/* use level trigger */
-	write_csr(CSR_VIC_MILSEL_G0, 0xffffffff);
-	/* enable all groups as wakeup sources */
-	write_csr(CSR_VIC_MIWAKEUP_G0, 0xffffffff);
-
-	/* enable GVIC */
-	set_csr(CSR_MCTREN, CSR_MCTREN_VIC);
-}
diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c
deleted file mode 100644
index cba5c65d0b..0000000000
--- a/chip/mt_scp/rv32i_common/ipi.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "cache.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hostcmd.h"
-#include "ipi_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "video.h"
-
-#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args)
-
-static uint8_t init_done;
-
-static struct mutex ipi_lock;
-static struct ipc_shared_obj *const ipi_send_buf =
-	(struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR;
-static struct ipc_shared_obj *const ipi_recv_buf =
-	(struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR +
-				  sizeof(struct ipc_shared_obj));
-
-static uint32_t disable_irq_count, saved_int_mask;
-
-void ipi_disable_irq(void)
-{
-	if (atomic_read_add(&disable_irq_count, 1) == 0)
-		saved_int_mask = read_clear_int_mask();
-}
-
-void ipi_enable_irq(void)
-{
-	if (atomic_read_sub(&disable_irq_count, 1) == 1)
-		set_int_mask(saved_int_mask);
-}
-
-static int ipi_is_busy(void)
-{
-	return SCP_SCP2APMCU_IPC_SET & IPC_SCP2HOST;
-}
-
-static void ipi_wake_ap(int32_t id)
-{
-	if (id >= IPI_COUNT)
-		return;
-
-	if (*ipi_wakeup_table[id])
-		SCP_SCP2SPM_IPC_SET = IPC_SCP2HOST;
-}
-
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
-{
-	int ret;
-
-	if (!init_done) {
-		CPRINTS("IPI has not initialized");
-		return EC_ERROR_BUSY;
-	}
-
-	if (in_interrupt_context()) {
-		CPRINTS("invoke %s() in ISR context", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	if (len > sizeof(ipi_send_buf->buffer)) {
-		CPRINTS("data length exceeds limitation");
-		return EC_ERROR_INVAL;
-	}
-
-	ipi_disable_irq();
-	mutex_lock(&ipi_lock);
-
-	if (ipi_is_busy()) {
-		/*
-		 * If the following conditions meet,
-		 *   1) There is an IPI pending in AP.
-		 *   2) The incoming IPI is a wakeup IPI.
-		 * then it assumes that AP is in suspend state.
-		 * Send a AP wakeup request to SPM.
-		 *
-		 * The incoming IPI will be checked if it's a wakeup source.
-		 */
-		ipi_wake_ap(id);
-
-		CPRINTS("IPI busy, id=%d", id);
-		ret = EC_ERROR_BUSY;
-		goto error;
-	}
-
-	ipi_send_buf->id = id;
-	ipi_send_buf->len = len;
-	memcpy(ipi_send_buf->buffer, buf, len);
-
-	/* flush memory cache (if any) */
-	cache_flush_dcache_range((uintptr_t)ipi_send_buf,
-				 sizeof(*ipi_send_buf));
-
-	/* interrupt AP to handle the message */
-	ipi_wake_ap(id);
-	SCP_SCP2APMCU_IPC_SET = IPC_SCP2HOST;
-
-	if (wait)
-		while (ipi_is_busy())
-			;
-
-	ret = EC_SUCCESS;
-error:
-	mutex_unlock(&ipi_lock);
-	ipi_enable_irq();
-	return ret;
-}
-
-static void ipi_enable_deferred(void)
-{
-	struct scp_run_t scp_run;
-	int ret;
-
-	init_done = 1;
-
-	/* inform AP that SCP is up */
-	scp_run.signaled = 1;
-	strncpy(scp_run.fw_ver, system_get_version(EC_IMAGE_RW),
-		SCP_FW_VERSION_LEN);
-	scp_run.dec_capability = video_get_dec_capability();
-	scp_run.enc_capability = video_get_enc_capability();
-
-	ret = ipi_send(SCP_IPI_INIT, (void *)&scp_run, sizeof(scp_run), 1);
-	if (ret) {
-		CPRINTS("failed to send initialization IPC messages");
-		init_done = 0;
-		return;
-	}
-
-#ifdef HAS_TASK_HOSTCMD
-	hostcmd_init();
-#endif
-
-	task_enable_irq(SCP_IRQ_GIPC_IN0);
-}
-DECLARE_DEFERRED(ipi_enable_deferred);
-
-static void ipi_init(void)
-{
-	memset(ipi_send_buf, 0, sizeof(struct ipc_shared_obj));
-	memset(ipi_recv_buf, 0, sizeof(struct ipc_shared_obj));
-
-	/* enable IRQ after all tasks are up */
-	hook_call_deferred(&ipi_enable_deferred_data, 0);
-}
-DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT);
-
-static void ipi_handler(void)
-{
-	if (ipi_recv_buf->id >= IPI_COUNT) {
-		CPRINTS("invalid IPI, id=%d", ipi_recv_buf->id);
-		return;
-	}
-
-	CPRINTS("IPI %d", ipi_recv_buf->id);
-
-	ipi_handler_table[ipi_recv_buf->id](
-		ipi_recv_buf->id, ipi_recv_buf->buffer, ipi_recv_buf->len);
-}
-
-static void irq_group7_handler(void)
-{
-	extern volatile int ec_int;
-
-	if (SCP_GIPC_IN_SET & GIPC_IN(0)) {
-		ipi_handler();
-		SCP_GIPC_IN_CLR = GIPC_IN(0);
-		asm volatile ("fence.i" ::: "memory");
-		task_clear_pending_irq(ec_int);
-	}
-}
-DECLARE_IRQ(7, irq_group7_handler, 0);
diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h
deleted file mode 100644
index 47a9434b09..0000000000
--- a/chip/mt_scp/rv32i_common/ipi_chip.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_IPI_CHIP_H
-#define __CROS_EC_IPI_CHIP_H
-
-#include "common.h"
-
-/*
- * Length of EC version string is at most 32 byte (NULL included), which
- * also aligns SCP fw_version length.
- */
-#define SCP_FW_VERSION_LEN 32
-
-#ifndef SCP_IPI_INIT
-#error If CONFIG_IPI is enabled, SCP_IPI_INIT must be defined.
-#endif
-
-/*
- * Share buffer layout for SCP_IPI_INIT response. This structure should sync
- * across kernel and EC.
- */
-struct scp_run_t {
-	uint32_t signaled;
-	int8_t fw_ver[SCP_FW_VERSION_LEN];
-	uint32_t dec_capability;
-	uint32_t enc_capability;
-};
-
-/*
- * The layout of the IPC0 AP/SCP shared buffer.
- * This should sync across kernel and EC.
- */
-struct ipc_shared_obj {
-	/* IPI ID */
-	int32_t id;
-	/* Length of the contents in buffer. */
-	uint32_t len;
-	/* Shared buffer contents. */
-	uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE];
-};
-
-/* Send a IPI contents to AP.  This shouldn't be used in ISR context. */
-int ipi_send(int32_t id, const void *buf, uint32_t len, int wait);
-
-/*
- * An IPC IRQ could be shared across many IPI handlers.
- * Those handlers would usually operate on disabling or enabling the IPC IRQ.
- * This may disorder the actual timing to on/off the IRQ when there are many
- * tasks try to operate on it.  As a result, any access to the SCP_IRQ_*
- * should go through ipi_{en,dis}able_irq(), which support a counter to
- * enable/disable the IRQ at correct timing.
- */
-/* Disable IPI IRQ. */
-void ipi_disable_irq(void);
-/* Enable IPI IRQ. */
-void ipi_enable_irq(void);
-
-/* IPI tables */
-extern void (*const ipi_handler_table[])(int32_t, void *, uint32_t);
-extern int *const ipi_wakeup_table[];
-
-/* Helper macros to build the IPI handler and wakeup functions. */
-#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler)
-#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup)
-
-/*
- * Macro to declare an IPI handler.
- * _id: The ID of the IPI
- * handler: The IPI handler function
- * is_wakeup_src: Declare IPI ID as a wake-up source or not
- */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
-		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
-	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
-
-#endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c
deleted file mode 100644
index 8fe3f1e598..0000000000
--- a/chip/mt_scp/rv32i_common/ipi_table.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IPI handlers declaration
- */
-
-#include "common.h"
-#include "ipi_chip.h"
-
-typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#define ipi_arguments int32_t id, void *data, uint32_t len
-
-#if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
-
-const int ipi_wakeup_undefined;
-
-#define table(type, name, x) x
-
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
-		ipi_##number##_##suffix(args);
-
-#define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
-
-#endif /* PASS == 1 */
-
-#if PASS == 2
-
-#undef table
-#undef ipi_x_func
-#undef ipi_x_var
-
-#define table(type, name, x)                                                   \
-	type const name[]                                                      \
-		__attribute__((aligned(4), used, section(".rodata.ipi"))) = {x}
-
-#define ipi_x_var(suffix, number)                                              \
-	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
-
-#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
-
-#endif /* PASS == 2 */
-
-/*
- * Include generated IPI table (by util/gen_ipi_table). The contents originate
- * from IPI_COUNT definition in board.h
- */
-#include "ipi_table_gen.inc"
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "ipi_table.c"
-BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT);
-#endif
diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c
deleted file mode 100644
index a666bb23d7..0000000000
--- a/chip/mt_scp/rv32i_common/memmap.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cache.h"
-#include "registers.h"
-#include "stdint.h"
-
-/*
- * Map SCP address (bits 31~28) to AP address
- *
- * SCP address	AP address	Note
- *
- * 0x0000_0000			SRAM
- * 0x1000_0000	0x5000_0000	CPU DRAM
- * 0x2000_0000	0x7000_0000
- * 0x3000_0000
- *
- * 0x4000_0000
- * 0x5000_0000	0x0000_0000
- * 0x6000_0000	0x1000_0000
- * 0x7000_0000	0xa000_0000
- *
- * 0x8000_0000
- * 0x9000_0000	0x8000_0000
- * 0xa000_0000	0x9000_0000
- * 0xb000_0000
- *
- * 0xc000_0000	0x8000_0000
- * 0xd000_0000	0x2000_0000
- * 0xe000_0000	0x3000_0000
- * 0xf000_0000	0x6000_0000
- */
-
-#define REMAP_ADDR_SHIFT		28
-#define REMAP_ADDR_LSB_MASK		(BIT(REMAP_ADDR_SHIFT) - 1)
-#define REMAP_ADDR_MSB_MASK		((~0) << REMAP_ADDR_SHIFT)
-#define MAP_INVALID 0xff
-
-static const uint8_t addr_map[16] = {
-	MAP_INVALID,	/* SRAM */
-	0x5,		/* ext_addr_0x1 */
-	0x7,		/* ext_addr_0x2 */
-	MAP_INVALID,	/* no ext_addr_0x3 */
-
-	MAP_INVALID,	/* no ext_addr_0x4 */
-	0x0,		/* ext_addr_0x5 */
-	0x1,		/* ext_addr_0x6 */
-	0xa,		/* ext_addr_0x7 */
-
-	MAP_INVALID,	/* no ext_addr_0x8 */
-	0x8,		/* ext_addr_0x9 */
-	0x9,		/* ext_addr_0xa */
-	MAP_INVALID,	/* no ext_addr_0xb */
-
-	0x8,		/* ext_addr_0xc */
-	0x2,		/* ext_addr_0xd */
-	0x3,		/* ext_addr_0xe */
-	0x6,		/* ext_addr_0xf */
-};
-
-void memmap_init(void)
-{
-	SCP_R_REMAP_0X0123 =
-		(uint32_t)addr_map[0x1] << 8 |
-		(uint32_t)addr_map[0x2] << 16;
-
-	SCP_R_REMAP_0X4567 =
-		(uint32_t)addr_map[0x5] << 8 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x7] << 24;
-
-	SCP_R_REMAP_0X89AB =
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0xa] << 16;
-
-	SCP_R_REMAP_0XCDEF =
-		(uint32_t)addr_map[0xc] |
-		(uint32_t)addr_map[0xd] << 8 |
-		(uint32_t)addr_map[0xe] << 16 |
-		(uint32_t)addr_map[0xf] << 24;
-
-	cache_init();
-}
-
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
-{
-	int i;
-	uint8_t msb = ap_addr >> REMAP_ADDR_SHIFT;
-
-	for (i = 0; i < ARRAY_SIZE(addr_map); ++i) {
-		if (addr_map[i] != msb)
-			continue;
-
-		*scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) |
-			(i << REMAP_ADDR_SHIFT);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
-{
-	int i = scp_addr >> REMAP_ADDR_SHIFT;
-
-	if (addr_map[i] == MAP_INVALID)
-		return EC_ERROR_INVAL;
-
-	*ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << REMAP_ADDR_SHIFT);
-	return EC_SUCCESS;
-}
diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h
deleted file mode 100644
index 0857c9a89e..0000000000
--- a/chip/mt_scp/rv32i_common/memmap.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MEMMAP_H
-#define __CROS_EC_MEMMAP_H
-
-#include "stdint.h"
-
-void memmap_init(void);
-
-/**
- * Translate AP addr to SCP addr.
- *
- * @param ap_addr		AP address to translate
- * @param scp_addr		Translated AP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr);
-
-/**
- * Translate SCP addr to AP addr.
- *
- * @param scp_addr		SCP address to translate
- * @param ap_addr		Translated SCP address
- * @return			EC_SUCCESS or EC_ERROR_INVAL
- */
-int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr);
-
-#endif /* #ifndef __CROS_EC_MEMMAP_H */
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h
deleted file mode 100644
index adbef5f98b..0000000000
--- a/chip/mt_scp/rv32i_common/registers.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Register map */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "intc.h"
-
-#define UNIMPLEMENTED_GPIO_BANK 0
-
-#define SCP_REG_BASE			0x70000000
-
-/* clock control */
-#define SCP_CLK_CTRL_BASE		(SCP_REG_BASE + 0x21000)
-/* system clock counter value */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_CTRL_BASE + 0x0014)
-#define   CLK_SYS_VAL_MASK		(0x3ff << 0)
-#define   CLK_SYS_VAL_VAL(v)		((v) & CLK_SYS_VAL_MASK)
-/* ULPOSC clock counter value */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_CTRL_BASE + 0x0018)
-#define   CLK_HIGH_VAL_MASK             (0x1f << 0)
-#define   CLK_HIGH_VAL_VAL(v)		((v) & CLK_HIGH_VAL_MASK)
-/* sleep mode control */
-#define SCP_SLEEP_CTRL                  REG32(SCP_CLK_CTRL_BASE + 0x0020)
-#define   SLP_CTRL_EN			BIT(0)
-#define   VREQ_COUNT_MASK		(0x7F << 1)
-#define   VREQ_COUNT_VAL(v)		(((v) << 1) & VREQ_COUNT_MASK)
-#define   SPM_SLP_MODE			BIT(8)
-/* clock divider select */
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0024)
-#define   CLK_DIV_SEL1			0
-#define   CLK_DIV_SEL2			1
-#define   CLK_DIV_SEL4			2
-#define   CLK_DIV_SEL3			3
-/* clock gate */
-#define SCP_SET_CLK_CG			REG32(SCP_CLK_CTRL_BASE + 0x0030)
-#define   CG_TIMER_MCLK			BIT(0)
-#define   CG_TIMER_BCLK			BIT(1)
-#define   CG_MAD_MCLK			BIT(2)
-#define   CG_I2C_MCLK			BIT(3)
-#define   CG_I2C_BCLK			BIT(4)
-#define   CG_GPIO_MCLK			BIT(5)
-#define   CG_AP2P_MCLK			BIT(6)
-#define   CG_UART0_MCLK			BIT(7)
-#define   CG_UART0_BCLK			BIT(8)
-#define   CG_UART0_RST			BIT(9)
-#define   CG_UART1_MCLK			BIT(10)
-#define   CG_UART1_BCLK			BIT(11)
-#define   CG_UART1_RST			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_I3C0			BIT(21)
-#define   CG_I3C1			BIT(22)
-#define   CG_DMA2_CH0			BIT(23)
-#define   CG_DMA2_CH1			BIT(24)
-#define   CG_DMA2_CH2			BIT(25)
-#define   CG_DMA2_CH3			BIT(26)
-/* UART clock select */
-#define SCP_UART_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0044)
-#define   UART0_CK_SEL_SHIFT		0
-#define   UART0_CK_SEL_MASK		(0x3 << UART0_CK_SEL_SHIFT)
-#define   UART0_CK_SEL_VAL(v)		((v) & UART0_CK_SEL_MASK)
-#define   UART0_CK_SW_STATUS_MASK	(0xf << 8)
-#define   UART0_CK_SW_STATUS_VAL(v)	((v) & UART0_CK_SW_STATUS_MASK)
-#define   UART1_CK_SEL_SHIFT		16
-#define   UART1_CK_SEL_MASK		(0x3 << UART1_CK_SEL_SHIFT)
-#define   UART1_CK_SEL_VAL(v)		((v) & UART1_CK_SEL_MASK)
-#define   UART1_CK_SW_STATUS_MASK	(0xf << 24)
-#define   UART1_CK_SW_STATUS_VAL(v)	((v) & UART1_CK_SW_STATUS_MASK)
-#define     UART_CK_SEL_26M		0
-#define     UART_CK_SEL_32K		1
-#define     UART_CK_SEL_ULPOSC		2
-#define     UART_CK_SW_STATUS_26M	BIT(0)
-#define     UART_CK_SW_STATUS_32K	BIT(1)
-#define     UART_CK_SW_STATUS_ULPOS	BIT(2)
-/* BCLK clock select */
-#define SCP_BCLK_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0048)
-#define   BCLK_CK_SEL_SYS_DIV8		0
-#define   BCLK_CK_SEL_32K		1
-#define   BCLK_CK_SEL_ULPOSC_DIV8	2
-/* VREQ control */
-#define SCP_CPU_VREQ_CTRL		REG32(SCP_CLK_CTRL_BASE + 0x0054)
-#define   VREQ_SEL			BIT(0)
-#define   VREQ_VALUE			BIT(4)
-#define   VREQ_EXT_SEL			BIT(8)
-#define   VREQ_DVFS_SEL			BIT(16)
-#define   VREQ_DVFS_VALUE		BIT(20)
-#define   VREQ_DVFS_EXT_SEL		BIT(24)
-#define   VREQ_SRCLKEN_SEL		BIT(27)
-#define   VREQ_SRCLKEN_VALUE		BIT(28)
-/* clock on control */
-#define SCP_CLK_HIGH_CORE_CG		REG32(SCP_CLK_CTRL_BASE + 0x005C)
-#define   HIGH_CORE_CG			BIT(1)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_CTRL_BASE + 0x006C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_DIS_SUB			BIT(1)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-
-/* system control */
-#define SCP_SYS_CTRL			REG32(SCP_REG_BASE + 0x24000)
-#define   AUTO_DDREN			BIT(9)
-
-/* IPC */
-#define SCP_SCP2APMCU_IPC_SET		REG32(SCP_REG_BASE + 0x24080)
-#define SCP_SCP2SPM_IPC_SET		REG32(SCP_REG_BASE + 0x24090)
-#define   IPC_SCP2HOST			BIT(0)
-#define SCP_GIPC_IN_SET			REG32(SCP_REG_BASE + 0x24098)
-#define SCP_GIPC_IN_CLR			REG32(SCP_REG_BASE + 0x2409C)
-#define   GIPC_IN(n)			BIT(n)
-
-/* UART */
-#define SCP_UART_COUNT			2
-#define UART_TX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _TX)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-#define SCP_UART0_BASE			(SCP_REG_BASE + 0x26000)
-#define SCP_UART1_BASE			(SCP_REG_BASE + 0x27000)
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-
-/* WDT */
-#define SCP_CORE0_WDT_IRQ		REG32(SCP_REG_BASE + 0x30030)
-#define SCP_CORE0_WDT_CFG		REG32(SCP_REG_BASE + 0x30034)
-#define   WDT_FREQ			33825 /* 0xFFFFF / 31 */
-#define   WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   WDT_PERIOD(ms)		(WDT_FREQ * (ms) / 1000)
-#define   WDT_EN			BIT(31)
-#define SCP_CORE0_WDT_KICK		REG32(SCP_REG_BASE + 0x30038)
-#define SCP_CORE0_WDT_CUR_VAL		REG32(SCP_REG_BASE + 0x3003C)
-
-/* INTC */
-#define SCP_INTC_WORD(irq)		((irq) >> 5) /* word length = 2^5 */
-#define SCP_INTC_BIT(irq)		((irq) & 0x1F) /* bit shift =LSB[0:4] */
-#define SCP_INTC_GRP_COUNT		15
-#define SCP_INTC_GRP_GAP		4
-
-#define SCP_CORE0_INTC_IRQ_BASE		(SCP_REG_BASE + 0x32000)
-#define SCP_CORE0_INTC_IRQ_STA(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
-#define SCP_CORE0_INTC_IRQ_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
-#define SCP_CORE0_INTC_IRQ_POL(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_SLP_WAKE_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
-#define SCP_CORE0_INTC_IRQ_OUT		REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
-/* UART */
-#define SCP_CORE0_INTC_UART0_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
-#define SCP_CORE0_INTC_UART1_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
-#define SCP_CORE0_INTC_UART_RX_IRQ(n)	CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
-
-/* XGPT (general purpose timer) */
-#define NUM_TIMERS			6
-#define SCP_CORE0_TIMER_BASE(n)		(SCP_REG_BASE + 0x33000 + (0x10 * (n)))
-#define SCP_CORE0_TIMER_EN(n)		REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
-#define   TIMER_EN			BIT(0)
-#define   TIMER_CLK_SRC_32K		(0 << 4)
-#define   TIMER_CLK_SRC_26M		(1 << 4)
-#define   TIMER_CLK_SRC_BCLK		(2 << 4)
-#define   TIMER_CLK_SRC_MCLK		(3 << 4)
-#define   TIMER_CLK_SRC_MASK		(3 << 4)
-#define SCP_CORE0_TIMER_RST_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
-#define SCP_CORE0_TIMER_CUR_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
-#define SCP_CORE0_TIMER_IRQ_CTRL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
-#define   TIMER_IRQ_EN			BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLR			BIT(5)
-#define SCP_IRQ_TIMER(n)		CONCAT2(SCP_IRQ_TIMER, n)
-
-/* secure control */
-#define SCP_SEC_CTRL			REG32(SCP_REG_BASE + 0xA5000)
-#define   VREQ_SECURE_DIS		BIT(4)
-/* memory remap */
-#define SCP_R_REMAP_0X0123		REG32(SCP_REG_BASE + 0xA5060)
-#define SCP_R_REMAP_0X4567		REG32(SCP_REG_BASE + 0xA5064)
-#define SCP_R_REMAP_0X89AB		REG32(SCP_REG_BASE + 0xA5068)
-#define SCP_R_REMAP_0XCDEF		REG32(SCP_REG_BASE + 0xA506C)
-
-/* external address: AP */
-#define AP_REG_BASE			0x60000000 /* 0x10000000 remap to 0x6 */
-/* AP GPIO */
-#define AP_GPIO_BASE			(AP_REG_BASE + 0x5000)
-#define AP_GPIO_MODE11_SET		REG32(AP_GPIO_BASE + 0x03B4)
-#define AP_GPIO_MODE11_CLR		REG32(AP_GPIO_BASE + 0x03B8)
-#define AP_GPIO_MODE12_SET		REG32(AP_GPIO_BASE + 0x03C4)
-#define AP_GPIO_MODE12_CLR		REG32(AP_GPIO_BASE + 0x03C8)
-#define AP_GPIO_MODE20_SET		REG32(AP_GPIO_BASE + 0x0444)
-#define AP_GPIO_MODE20_CLR		REG32(AP_GPIO_BASE + 0x0448)
-
-#include "clock_regs.h"
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c
deleted file mode 100644
index 0e12154f6d..0000000000
--- a/chip/mt_scp/rv32i_common/system.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System : hardware specific implementation */
-
-#include "csr.h"
-#include "memmap.h"
-#include "registers.h"
-#include "system.h"
-
-void system_pre_init(void)
-{
-	memmap_init();
-
-	/* enable CPU and platform low power CG */
-	/* enable CPU DCM */
-	set_csr(CSR_MCTREN, CSR_MCTREN_CG);
-
-	/* Disable jump (it has only RW) */
-	system_disable_jump();
-}
-
-void system_reset(int flags)
-{
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return EC_ERROR_INVAL;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "mtk";
-}
-
-const char *system_get_chip_name(void)
-{
-	/* Support only SCP_A for now */
-	return "scp_a";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c
deleted file mode 100644
index 35b4003c9f..0000000000
--- a/chip/mt_scp/rv32i_common/uart.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module */
-
-#include "csr.h"
-#include "system.h"
-#include "uart.h"
-#include "uart_regs.h"
-#include "util.h"
-
-/*
- * UARTN == 0, SCP UART0
- * UARTN == 1, SCP UART1
- * UARTN == 2, AP UART1
- */
-#define UARTN CONFIG_UART_CONSOLE
-#define UART_IDLE_WAIT_US 500
-#define UART_INTC_GROUP 12
-
-static uint8_t init_done, tx_started;
-
-void uart_init(void)
-{
-	const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
-	const uint32_t uart_clock = 26000000;
-	const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
-
-	uart_init_pinmux();
-
-	/* Clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
-	/* Line control: parity none, 8 bit, 1 stop bit */
-	UART_LCR(UARTN) = UART_LCR_WLEN8;
-	/* For baud rate <= 115200 */
-	UART_HIGHSPEED(UARTN) = 0;
-
-	/* DLAB start */
-	UART_LCR(UARTN) |= UART_LCR_DLAB;
-	UART_DLL(UARTN) = div & 0xff;
-	UART_DLH(UARTN) = (div >> 8) & 0xff;
-	UART_LCR(UARTN) &= ~UART_LCR_DLAB;
-	/* DLAB end */
-
-	/* Enable received data interrupt */
-	UART_IER(UARTN) |= UART_IER_RDI;
-
-#if (UARTN < SCP_UART_COUNT)
-	task_enable_irq(UART_TX_IRQ(UARTN));
-	task_enable_irq(UART_RX_IRQ(UARTN));
-#endif
-
-	init_done = 1;
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_flush(void)
-{
-	while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_THRE;
-}
-
-int uart_rx_available(void)
-{
-	return UART_LSR(UARTN) & UART_LSR_DR;
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-
-	UART_THR(UARTN) = c;
-}
-
-int uart_read_char(void)
-{
-	return UART_RBR(UARTN);
-}
-
-void uart_tx_start(void)
-{
-	tx_started = 1;
-	if (UART_IER(UARTN) & UART_IER_THRI)
-		return;
-	disable_sleep(SLEEP_MASK_UART);
-	UART_IER(UARTN) |= UART_IER_THRI;
-}
-
-void uart_tx_stop(void)
-{
-	/*
-	 * Workaround for b/157541273.
-	 * Don't unset the THRI flag unless we are in the UART ISR.
-	 *
-	 * Note:
-	 * MICAUSE denotes current INTC group number.
-	 */
-	if (in_interrupt_context() &&
-	    read_csr(CSR_VIC_MICAUSE) != UART_INTC_GROUP)
-		return;
-
-	tx_started = 0;
-	UART_IER(UARTN) &= ~UART_IER_THRI;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-static void uart_process(void)
-{
-	uart_process_input();
-	uart_process_output();
-}
-
-#if (UARTN < SCP_UART_COUNT)
-static void uart_irq_handler(void)
-{
-	extern volatile int ec_int;
-
-	switch (ec_int) {
-	case UART_TX_IRQ(UARTN):
-		uart_process();
-		task_clear_pending_irq(ec_int);
-		break;
-	case UART_RX_IRQ(UARTN):
-		uart_process();
-		SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0);
-		asm volatile ("fence.i" ::: "memory");
-		task_clear_pending_irq(ec_int);
-		break;
-	}
-}
-DECLARE_IRQ(UART_INTC_GROUP, uart_irq_handler, 0);
-#else
-
-#ifndef HAS_TASK_APUART
-#error "APUART task hasn't defined in ec.tasklist."
-#endif
-
-void uart_task(void)
-{
-	while (1) {
-		if (uart_rx_available() || tx_started)
-			uart_process();
-		else
-			task_wait_event(UART_IDLE_WAIT_US);
-	}
-}
-#endif
diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h
deleted file mode 100644
index c88b9c758b..0000000000
--- a/chip/mt_scp/rv32i_common/uart_regs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SCP UART module registers */
-
-#ifndef __CROS_EC_UART_REGS_H
-#define __CROS_EC_UART_REGS_H
-
-#include "registers.h"
-
-/* Chip specific function for setting UART pinmux. */
-void uart_init_pinmux(void);
-
-/* DLAB (Divisor Latch Access Bit) == 0 */
-
-/* (Read) receiver buffer register */
-#define UART_RBR(n)			UART_REG(n, 0)
-/* (Write) transmitter holding register */
-#define UART_THR(n)			UART_REG(n, 0)
-/* (Write) interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define   UART_IER_RDI			BIT(0) /* received data */
-#define   UART_IER_THRI			BIT(1) /* THR empty */
-#define   UART_IER_RLSI			BIT(2) /* receiver LSR change */
-#define   UART_IER_MSI			BIT(3) /* MSR change */
-/* (Read) interrupt identification register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define   UART_IIR_ID_MASK		0x0e
-#define   UART_IIR_MSI			0x00 /* modem status change */
-#define   UART_IIR_NO_INT		0x01 /* no int pending */
-#define   UART_IIR_THRI			0x02 /* THR empty */
-#define   UART_IIR_RDI			0x04 /* received data available */
-#define   UART_IIR_RLSI			0x06 /* line status change */
-/* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define   UART_FCR_ENABLE_FIFO		BIT(0) /* enable FIFO */
-#define   UART_FCR_CLEAR_RCVR		BIT(1) /* clear receive FIFO */
-#define   UART_FCR_CLEAR_XMIT		BIT(2) /* clear transmit FIFO */
-#define   UART_FCR_DMA_SELECT		BIT(3) /* select DMA mode */
-/* (Write) line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define   UART_LCR_WLEN5		0 /* word length 5 bits */
-#define   UART_LCR_WLEN6		1
-#define   UART_LCR_WLEN7		2
-#define   UART_LCR_WLEN8		3
-#define   UART_LCR_STOP			BIT(2) /* stop bits: 1bit, 2bits */
-#define   UART_LCR_PARITY		BIT(3) /* parity enable */
-#define   UART_LCR_EPAR			BIT(4) /* even parity */
-#define   UART_LCR_SPAR			BIT(5) /* stick parity */
-#define   UART_LCR_SBC			BIT(6) /* set break control */
-#define   UART_LCR_DLAB			BIT(7) /* divisor latch access */
-/* (Write) modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
-/* (Read) line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define   UART_LSR_DR			BIT(0) /* data ready */
-#define   UART_LSR_OE			BIT(1) /* overrun error */
-#define   UART_LSR_PE			BIT(2) /* parity error */
-#define   UART_LSR_FE			BIT(3) /* frame error */
-#define   UART_LSR_BI			BIT(4) /* break interrupt */
-#define   UART_LSR_THRE			BIT(5) /* THR empty */
-#define   UART_LSR_TEMT			BIT(6) /* THR empty, line idle */
-#define   UART_LSR_FIFOE		BIT(7) /* FIFO error */
-/* (Read) modem status register */
-#define UART_MSR(n)			UART_REG(n, 6)
-/* (Read/Write) scratch register */
-#define UART_SCR(n)			UART_REG(n, 7)
-
-/* DLAB == 1 */
-
-/* (Write) divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0)
-#define UART_DLH(n)			UART_REG(n, 1)
-
-/* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-
-#endif /* __CROS_EC_UART_REGS_H */
diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h
deleted file mode 100644
index e4538c4456..0000000000
--- a/chip/mt_scp/rv32i_common/video.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_VIDEO_H
-#define __CROS_EC_VIDEO_H
-
-#include "common.h"
-
-/*
- * Video decoder supported capability
- */
-#define VDEC_CAP_4K_DISABLED BIT(4)
-#define VDEC_CAP_MM21 BIT(5)
-#define VDEC_CAP_MT21C BIT(6)
-#define VDEC_CAP_H264_SLICE BIT(8)
-#define VDEC_CAP_VP8_FRAME BIT(9)
-#define VDEC_CAP_VP9_FRAME BIT(10)
-#define VDEC_CAP_IRQ_IN_SCP BIT(16)
-
-/*
- * Video encoder supported capability:
- * BIT(0): enable 4K
- */
-#define VENC_CAP_4K BIT(0)
-
-uint32_t video_get_enc_capability(void);
-uint32_t video_get_dec_capability(void);
-
-#endif /* #ifndef __CROS_EC_VIDEO_H */
diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c
deleted file mode 100644
index 72ca5edad8..0000000000
--- a/chip/mt_scp/rv32i_common/watchdog.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "hooks.h"
-#include "registers.h"
-#include "watchdog.h"
-
-void watchdog_reload(void)
-{
-	SCP_CORE0_WDT_KICK = BIT(0);
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	const uint32_t timeout = WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS);
-
-	/* disable watchdog */
-	SCP_CORE0_WDT_CFG &= ~WDT_EN;
-	/* clear watchdog irq */
-	SCP_CORE0_WDT_IRQ |= BIT(0);
-	/* enable watchdog */
-	SCP_CORE0_WDT_CFG = WDT_EN | timeout;
-	/* reload watchdog */
-	watchdog_reload();
-
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
deleted file mode 100644
index ea16589d9b..0000000000
--- a/chip/npcx/adc.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific ADC module for Chrome EC */
-
-#include "adc.h"
-#include "atomic.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US            SECOND
-#define ADC_CLK                   2000000
-#define ADC_REGULAR_DLY           0x11
-#define ADC_REGULAR_ADCCNF2       0x8B07
-#define ADC_REGULAR_GENDLY        0x0100
-#define ADC_REGULAR_MEAST         0x0001
-
-/* ADC conversion mode */
-enum npcx_adc_conversion_mode {
-	ADC_CHN_CONVERSION_MODE   = 0,
-	ADC_SCAN_CONVERSION_MODE  = 1
-};
-
-/* Global variables */
-static volatile task_id_t task_waiting;
-
-struct mutex adc_lock;
-
-/**
- * Preset ADC operation clock.
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void adc_freq_changed(void)
-{
-	uint8_t prescaler_divider    = 0;
-
-	/* Set clock prescaler divider to ADC module*/
-	prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0x3F)
-		prescaler_divider = 0x3F;
-
-	/* Set Core Clock Division Factor in order to obtain the ADC clock */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_SCLKDIV_FIELD, prescaler_divider);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT);
-
-/**
- * Flush an ADC sequencer and initiate a read.
- *
- * @param   input_ch    operation channel
- * @param   timeout		preset timeout
- * @return  TRUE/FALSE  success/fail
- * @notes   set SW-triggered interrupt conversion and one-shot mode in npcx chip
- */
-static int start_single_and_wait(enum npcx_adc_input_channel input_ch
-		, int timeout)
-{
-	int event;
-
-	task_waiting = task_get_current();
-
-	/* Stop ADC conversion first */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-	/* Set ADC conversion code to SW conversion mode */
-	SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			ADC_CHN_CONVERSION_MODE);
-
-	/* Set conversion type to one-shot type */
-	CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-
-	/* Update number of channel to be converted */
-	SET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD, input_ch);
-
-	/* Clear End-of-Conversion Event status */
-	SET_BIT(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV);
-
-	/* Enable ADC End-of-Conversion Interrupt if applicable */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN);
-
-	/* Start conversion */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_ADC_DONE, timeout);
-
-	task_waiting = TASK_ID_INVALID;
-
-	return (event == TASK_EVENT_ADC_DONE);
-
-}
-
-static uint16_t repetitive_enabled;
-void npcx_set_adc_repetitive(enum npcx_adc_input_channel input_ch, int enable)
-{
-	mutex_lock(&adc_lock);
-
-	/* Stop ADC conversion */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-	if (enable) {
-		/* Forbid EC enter deep sleep during conversion. */
-		disable_sleep(SLEEP_MASK_ADC);
-		/* Turn on ADC */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-		/* Set ADC conversion code to SW conversion mode */
-		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			  ADC_SCAN_CONVERSION_MODE);
-		/* Update number of channel to be converted */
-		SET_BIT(NPCX_ADCCS, input_ch);
-		/* Set conversion type to repetitive (runs continuously) */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-		repetitive_enabled |= BIT(input_ch);
-
-		/* Start conversion */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-	} else {
-		CLEAR_BIT(NPCX_ADCCS, input_ch);
-		repetitive_enabled &= ~BIT(input_ch);
-
-		if (!repetitive_enabled) {
-			/* Turn off ADC */
-			CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-			/* Set ADC to one-shot mode */
-			CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-			/* Allow ec enter deep sleep */
-			enable_sleep(SLEEP_MASK_ADC);
-		} else {
-			/* Start conversion again */
-			SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-		}
-	}
-
-	mutex_unlock(&adc_lock);
-}
-
-/**
- * Return the ADC value from CHNDAT register directly.
- *
- * @param   input_ch    channel number
- * @return  ADC data
- */
-int adc_read_data(enum npcx_adc_input_channel input_ch)
-{
-	const struct adc_t *adc = adc_channels + input_ch;
-	int value;
-	uint16_t chn_data;
-
-	chn_data = NPCX_CHNDAT(adc->input_ch);
-	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-		 adc->factor_mul / adc->factor_div + adc->shift;
-	return value;
-}
-
-/**
- * Start a single conversion and return the result
- *
- * @param   ch    operation channel
- * @return  ADC converted voltage or error message
- */
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	uint16_t chn_data;
-
-	mutex_lock(&adc_lock);
-
-	/* Forbid ec enter deep sleep during ADC conversion is proceeding. */
-	disable_sleep(SLEEP_MASK_ADC);
-
-	/* Turn on ADC */
-	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-
-	if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) {
-		chn_data = NPCX_CHNDAT(adc->input_ch);
-		if ((adc->input_ch ==
-			GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD))
-			&& (IS_BIT_SET(chn_data,
-					NPCX_CHNDAT_NEW))) {
-			value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-				adc->factor_mul / adc->factor_div + adc->shift;
-		} else {
-			value = ADC_READ_ERROR;
-		}
-	} else {
-		value = ADC_READ_ERROR;
-	}
-
-	if (!repetitive_enabled) {
-		/* Turn off ADC */
-		CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCEN);
-		/* Allow ec enter deep sleep */
-		enable_sleep(SLEEP_MASK_ADC);
-	} else {
-		/* Set ADC conversion code to SW conversion mode */
-		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-		  ADC_SCAN_CONVERSION_MODE);
-		/* Set conversion type to repetitive (runs continuously) */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
-		/* Start conversion */
-		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
-	}
-
-	mutex_unlock(&adc_lock);
-
-	return value;
-}
-
-/* Board should register these callbacks with npcx_adc_cfg_thresh_int(). */
-static void (*adc_thresh_irqs[NPCX_ADC_THRESH_CNT])(void);
-
-void npcx_adc_thresh_int_enable(int threshold_idx, int enable)
-{
-	uint16_t thrcts;
-
-	enable = !!enable;
-
-	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
-		return;
-	}
-	threshold_idx--; /* convert to 0-based */
-
-	/* avoid clearing other threshold status */
-	thrcts = NPCX_THRCTS & ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
-
-	if (enable) {
-		/* clear threshold status */
-		SET_BIT(thrcts, threshold_idx);
-		/* set enable threshold status */
-		SET_BIT(thrcts, NPCX_THRCTS_THR1_IEN + threshold_idx);
-	} else {
-		CLEAR_BIT(thrcts, NPCX_THRCTS_THR1_IEN + threshold_idx);
-	}
-	NPCX_THRCTS = thrcts;
-}
-
-void npcx_adc_register_thresh_irq(int threshold_idx,
-				  const struct npcx_adc_thresh_t *thresh_cfg)
-{
-	int npcx_adc_ch;
-	int raw_val;
-	int mul;
-	int div;
-	int shift;
-
-	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
-		return;
-	}
-	npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch;
-
-	if (!thresh_cfg->adc_thresh_cb) {
-		CPRINTS("No callback for ADC Threshold %d!",
-			threshold_idx);
-		return;
-	}
-
-	/* Fill in the table */
-	adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb;
-
-	/* Select the channel */
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL,
-		  npcx_adc_ch);
-
-	if (thresh_cfg->lower_or_higher)
-		SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
-	else
-		CLEAR_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
-
-	/* Set the threshold value. */
-	mul = adc_channels[thresh_cfg->adc_ch].factor_mul;
-	div = adc_channels[thresh_cfg->adc_ch].factor_div;
-	shift = adc_channels[thresh_cfg->adc_ch].shift;
-
-	raw_val = (thresh_cfg->thresh_assert - shift) * div / mul;
-	CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx,
-		raw_val, thresh_cfg->lower_or_higher);
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL,
-		  raw_val);
-
-#if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-	/* Disable deassertion threshold function */
-	CLEAR_BIT(NPCX_THR_DCTL(threshold_idx), NPCX_THR_DCTL_THRD_EN);
-#endif
-
-	/* Enable threshold detection */
-	SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THEN);
-}
-
-/**
- * ADC interrupt handler
- *
- * @param   none
- * @return  none
- * @notes   Only handle SW-triggered conversion in npcx chip
- */
-void adc_interrupt(void)
-{
-	int i;
-	uint16_t thrcts;
-
-	if (IS_BIT_SET(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN) &&
-	    IS_BIT_SET(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV)) {
-		/* Disable End-of-Conversion Interrupt */
-		CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_INTECEN);
-
-		/* Stop conversion for single-shot mode */
-		if (!repetitive_enabled)
-			SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_STOP);
-
-		/* Clear End-of-Conversion Event status */
-		SET_BIT(NPCX_ADCSTS, NPCX_ADCSTS_EOCEV);
-
-		/* Wake up the task which was waiting for the interrupt */
-		if (task_waiting != TASK_ID_INVALID)
-			task_set_event(task_waiting, TASK_EVENT_ADC_DONE);
-	}
-
-	for (i = NPCX_THRCTS_THR1_STS; i < NPCX_ADC_THRESH_CNT; i++) {
-		if (IS_BIT_SET(NPCX_THRCTS, NPCX_THRCTS_THR1_IEN + i) &&
-		    IS_BIT_SET(NPCX_THRCTS, i)) {
-			/* avoid clearing other threshold status */
-			thrcts = NPCX_THRCTS &
-					~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
-			/* Clear threshold status */
-			SET_BIT(thrcts, i);
-			NPCX_THRCTS = thrcts;
-			if (adc_thresh_irqs[i])
-				adc_thresh_irqs[i]();
-		}
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_ADC, adc_interrupt, 4);
-
-/**
- * ADC initial.
- *
- * @param none
- * @return none
- */
-static void adc_init(void)
-{
-	/* Configure pins from GPIOs to ADCs */
-	gpio_config_module(MODULE_ADC, 1);
-
-	/* Enable ADC clock (bit4 mask = 0x10) */
-	clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Set Core Clock Division Factor in order to obtain the ADC clock */
-	adc_freq_changed();
-
-	/* Set regular speed */
-	SET_FIELD(NPCX_ATCTL, NPCX_ATCTL_DLY_FIELD, (ADC_REGULAR_DLY - 1));
-
-	/* Set the other ADC settings */
-	NPCX_ADCCNF2 = ADC_REGULAR_ADCCNF2;
-	NPCX_GENDLY = ADC_REGULAR_GENDLY;
-	NPCX_MEAST = ADC_REGULAR_MEAST;
-
-	task_waiting = TASK_ID_INVALID;
-
-	/* Enable IRQs */
-	task_enable_irq(NPCX_IRQ_ADC);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h
deleted file mode 100644
index 300447df16..0000000000
--- a/chip/npcx/adc_chip.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#include "common.h"
-
-/* Minimum and maximum values returned by raw ADC read. */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 1023
-#define ADC_MAX_VOLT 2816
-
-/* ADC input channel select */
-enum npcx_adc_input_channel {
-	NPCX_ADC_CH0 = 0,
-	NPCX_ADC_CH1,
-	NPCX_ADC_CH2,
-	NPCX_ADC_CH3,
-	NPCX_ADC_CH4,
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_ADC_CH5,
-	NPCX_ADC_CH6,
-	NPCX_ADC_CH7,
-	NPCX_ADC_CH8,
-	NPCX_ADC_CH9,
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_ADC_CH10,
-	NPCX_ADC_CH11,
- #endif
-	NPCX_ADC_CH_COUNT
-};
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	enum npcx_adc_input_channel input_ch;
-	int factor_mul;
-	int factor_div;
-	int shift;
-};
-
-/*
- * Boards may configure a ADC channel for use with thershold interrupts.
- * The threshold levels may be set from 0 to ADC_MAX_VOLT inclusive.
- */
-struct npcx_adc_thresh_t {
-	/* The ADC channel to monitor to generate threshold interrupts. */
-	enum adc_channel adc_ch;
-
-	/* Called when the interrupt fires */
-	void (*adc_thresh_cb)(void);
-
-	/* If set, threshold event is asserted when <= threshold level */
-	int lower_or_higher;
-
-	/* Desired threshold level in mV to assert. */
-	int thresh_assert;
-};
-
-/**
- * Boards should call this function to register their threshold interrupt with
- * one of the threshold detectors. 'threshold_idx' is 1-based.
- *
- * @param threshold_idx - 1-based threshold detector index
- * @param thresh_cfg - Pointer to ADC threshold interrupt configuration
- */
-void npcx_adc_register_thresh_irq(int threshold_idx,
-				  const struct npcx_adc_thresh_t *thresh_cfg);
-
-/**
- * Configure an ADC channel for repetitive conversion.
- *
- * If you are using ADC threshold interrupts and the need is timing critical,
- * you will want to enable this on the ADC channels you have configured for
- * threshold interrupts.
- *
- * NOTE: Enabling this will prevent the EC from entering deep sleep and will
- * increase power consumption!
- *
- * @param input_ch - The ADC channel you wish to configure
- * @param enable   - 1 to enable, 0 to disable
- */
-void npcx_set_adc_repetitive(enum npcx_adc_input_channel input_ch, int enable);
-
-/**
- * Enable/Disable ADC threshold detector interrupt.
- *
- * @param threshold_idx - 1-based threshold detector index
- * @param enable         - 1 to enable, 0 to disable
- */
-void npcx_adc_thresh_int_enable(int threshold_idx, int enable);
-
-/**
- * Return the ADC value from CHNDAT register directly when the channel is
- * configured in the repetitive mode.
- *
- * @param   input_ch    channel number
- * @return  ADC data
- */
-int adc_read_data(enum npcx_adc_input_channel input_ch);
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c
deleted file mode 100644
index 4ab64774c1..0000000000
--- a/chip/npcx/apm.c
+++ /dev/null
@@ -1,694 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific APM module for Chrome EC */
-
-#include "apm_chip.h"
-#include "common.h"
-#include "registers.h"
-#include "util.h"
-#include "wov_chip.h"
-
-static struct apm_config apm_conf;
-static struct apm_auto_gain_config	apm_gain_conf;
-
-
-static uint32_t apm_indirect_reg[][3] = {
-	{(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)},
-	{(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)},
-	{(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)}
-};
-
-#define APM_CNTRL_REG 0
-#define APM_DATA_REG 1
-
-/**
- * Reads data indirect register.
- *
- * @param   reg_offset    - Indirect register APM_MIX_REG, APM_ADC_AGC_REG or
- *                          APM_VAD_REG.
- * @param   indirect_addr - Indirect access address.
- * @return  The read data.
- */
-static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				      uint8_t indirect_addr)
-{
-	/* Set the indirect access address. */
-	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
-
-	/* Read command. */
-	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-
-	/* Get the data. */
-	return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]);
-}
-
-/**
- * Writes data indirect register.
- *
- * @param   reg_offset    - Indirect register APM_MIX_REG, APM_ADC_AGC_REG or
- *                          APM_VAD_REG.
- * @param   indirect_addr - Indirect access address.
- * @param   value         - Written value.
- * @return  None
- */
-static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				uint8_t indirect_addr, uint8_t value)
-{
-	/* Set the data. */
-	REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value;
-
-	/* Set the indirect access address. */
-	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
-
-	/* Write command. */
-	SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
-}
-
-/**
- * Sets the ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate)
-{
-	if (rate == APM_DMIC_RATE_0_75)
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_3_0);
-	else if (rate == APM_DMIC_RATE_1_2)
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_2_4);
-	else
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			rate);
-}
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	/* Set VAD_0 register. */
-	if (rate == APM_DMIC_RATE_0_75)
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-				APM_DMIC_RATE_3_0);
-	else if (rate == APM_DMIC_RATE_1_2)
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-			  APM_DMIC_RATE_2_4);
-	else
-		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, rate);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Translates from ADC real value to frequency code
- *
- * @param   adc_freq_val   - ADC frequency.
- * @return  ADC frequency code, 0xFFFF in case of wrong value.
- */
-static enum apm_adc_frequency apm_adc_freq_val_2_code(uint32_t adc_freq_val)
-{
-	enum apm_adc_frequency freq_code;
-
-	switch (adc_freq_val) {
-	case 8000:
-		freq_code = APM_ADC_FREQ_8_000_KHZ;
-		break;
-	case 12000:
-		freq_code = APM_ADC_FREQ_12_000_KHZ;
-		break;
-	case 16000:
-		freq_code = APM_ADC_FREQ_16_000_KHZ;
-		break;
-	case 24000:
-		freq_code = APM_ADC_FREQ_24_000_KHZ;
-		break;
-	case 32000:
-		freq_code = APM_ADC_FREQ_32_000_KHZ;
-		break;
-	case 48000:
-		freq_code = APM_ADC_FREQ_48_000_KHZ;
-		break;
-	default:
-		freq_code = APM_ADC_FREQ_UNSUPPORTED;
-		break;
-	}
-
-	return freq_code;
-}
-
-/**
- * Initiate APM module local parameters..
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_init(void)
-{
-	apm_conf.adc_ram_dmic_rate = APM_DMIC_RATE_0_75;
-	apm_conf.adc_i2s_dmic_rate = APM_DMIC_RATE_3_0;
-	apm_conf.gain_coupling = APM_ADC_CHAN_GAINS_INDEPENDENT;
-	apm_conf.left_chan_gain = 0;
-	apm_conf.right_chan_gain = 0;
-
-	apm_gain_conf.stereo_enable	 = 0;
-	apm_gain_conf.agc_target	 = APM_ADC_MAX_TARGET_LEVEL_19_5;
-	apm_gain_conf.nois_gate_en	 = 0;
-	apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD;
-	apm_gain_conf.hold_time	 = APM_HOLD_TIME_128;
-	apm_gain_conf.attack_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.decay_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.gain_max	 = APM_GAIN_VALUE_42_5;
-	apm_gain_conf.gain_min	 = APM_GAIN_VALUE_0_0;
-}
-
-/**
- * Enables/Disables APM  module.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_enable(int enable)
-{
-	if (enable) {
-		CLEAR_BIT(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-
-		/* Work around that enable the AGC. */
-		SET_FIELD(NPCX_APM_CR_APM, NPCX_APM_CR_APM_AGC_DIS, 0x00);
-
-	} else
-		SET_BIT(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-}
-
-/**
- * Enables/Disables voice activity detected interrupt.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  APM interrupt mode.
- */
-void apm_enable_vad_interrupt(int enable)
-{
-	wov_interrupt_enable(WOV_VAD_INT_INDX, enable);
-	wov_interrupt_enable(WOV_VAD_WAKE_INDX, enable);
-	if (enable)
-		CLEAR_BIT(NPCX_APM_IMR, NPCX_APM_IMR_VAD_DTC_MASK);
-	else
-		SET_BIT(NPCX_APM_IMR, NPCX_APM_IMR_VAD_DTC_MASK);
-}
-
-/**
- * Enable/Disable the WoV in the ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_adc_wov_enable(int enable)
-{
-	if (enable) {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
-	} else {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
-	}
-}
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_adc_enable(int enable)
-{
-	if (enable) {
-		CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
-	} else {
-		SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
-	}
-}
-
-/**
- * sets the ADC frequency.
- *
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_set_freq(enum apm_adc_frequency adc_freq)
-{
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_FREQ, adc_freq);
-}
-
-/**
- * Configures the ADC.
- *
- * @param   hpf_enable  - High pass filter enabled flag, 1 means enable
- * @param   filter_mode - ADC wind noise filter mode.
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq)
-{
-	if (hpf_enable)
-		SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
-	else
-		CLEAR_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
-
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_WNF, filter_mode);
-
-	SET_FIELD(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_FREQ, adc_freq);
-}
-
-/**
- * Enables/Disables Digital Microphone.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_dmic_enable(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_PD_DMIC);
-	else
-		SET_BIT(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_PD_DMIC);
-}
-
-/**
- * Sets the RAM ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_ram_dmic_config(enum apm_dmic_rate rate)
-{
-	apm_conf.adc_ram_dmic_rate = rate;
-}
-
-/**
- * Gets the RAM ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_ram_dmic_rate(void)
-{
-	return apm_conf.adc_ram_dmic_rate;
-}
-
-/**
- * Sets the ADC I2S DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_i2s_dmic_config(enum apm_dmic_rate rate)
-{
-	apm_conf.adc_i2s_dmic_rate = rate;
-}
-
-/**
- * Gets the ADC I2S DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_i2s_dmic_rate(void)
-{
-	return apm_conf.adc_i2s_dmic_rate;
-}
-/**
- * Configures Digital Mixer
- *
- * @param   mix_left  - Mixer left channel output selection on ADC path.
- * @param   mix_right - Mixer right channel output selection on ADC path.
- * @return  None
- */
-void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-			      enum apm_dig_mix mix_right)
-{
-	uint8_t mix_2 = 0;
-
-	SET_FIELD(mix_2, NPCX_APM_MIX_2_AIADCL_SEL, mix_left);
-	SET_FIELD(mix_2, NPCX_APM_MIX_2_AIADCR_SEL, mix_right);
-
-	apm_write_indirect_data(APM_MIX_REG, APM_INDIRECT_MIX_2_REG, mix_2);
-}
-
-/**
- * Enables/Disables the VAD functionality.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_vad_enable(int enable)
-{
-	if (enable)
-		NPCX_APM_CR_VAD = 0x80;
-	else
-		NPCX_APM_CR_VAD = 0x00;
-}
-
-/**
- * Enables/Disables VAD ADC wakeup
- *
- * @param   enable - 1 enable, 0 disable.
- *
- * @return  None
- */
-void apm_vad_adc_wakeup_enable(int enable)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	if (enable)
-		SET_BIT(vad_data, NPCX_VAD_0_VAD_ADC_WAKEUP);
-	else
-		CLEAR_BIT(vad_data, NPCX_VAD_0_VAD_ADC_WAKEUP);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate(enum apm_dmic_rate rate)
-{
-	apm_conf.vad_dmic_rate = rate;
-}
-
-/**
- * Gets VAD DMIC rate.
- *
- * @param   None
- *
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_vad_dmic_rate(void)
-{
-	return apm_conf.vad_dmic_rate;
-}
-
-/**
- * Sets VAD Input chanel.
- *
- * @param   chan_src                - Processed digital microphone channel
- *                                    selection.
- * @return  None
- */
-void apm_set_vad_input_channel(enum apm_vad_in_channel_src chan_src)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG);
-
-	SET_FIELD(vad_data, NPCX_VAD_0_VAD_INSEL, chan_src);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_0_REG, vad_data);
-}
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-void apm_set_vad_sensitivity(uint8_t sensitivity_db)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG);
-
-	SET_FIELD(vad_data, NPCX_VAD_1_VAD_POWER_SENS, sensitivity_db);
-
-	apm_write_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG, vad_data);
-}
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-uint8_t apm_get_vad_sensitivity(void)
-{
-	uint8_t vad_data;
-
-	vad_data = apm_read_indirect_data(APM_VAD_REG, APM_INDIRECT_VAD_1_REG);
-
-	return GET_FIELD(vad_data, NPCX_VAD_1_VAD_POWER_SENS);
-}
-
-/**
- * Restarts VAD functionality.
- *
- * @param   None
- * @return  None
- */
-void apm_vad_restart(void)
-{
-	SET_BIT(NPCX_APM_CR_VAD_CMD, NPCX_APM_CR_VAD_CMD_VAD_RESTART);
-}
-
-/**
- * Restarts VAD functionality.
- *
- * @param   gain_coupling   - ADC digital gain coupling (independent or
- *                            rigth tracks left).
- * @param   left_chan_gain  - Left channel ADC digital gain programming value.
- * @param   right_chan_gain - Right channel ADC digital gain programming value.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-		uint8_t left_chan_gain, uint8_t right_chan_gain)
-{
-	/* Check parameters validity. */
-	if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B))
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Store the parameters in order to use them in case the function
-	 * was called prioe calling to wov_set_mode.
-	 */
-	apm_conf.gain_coupling = gain_coupling;
-	apm_conf.left_chan_gain = left_chan_gain;
-	apm_conf.right_chan_gain = right_chan_gain;
-
-	/* Set gain coupling.*/
-	if (gain_coupling == APM_ADC_CHAN_GAINS_INDEPENDENT)
-		CLEAR_BIT(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_LRGID);
-	else
-		SET_BIT(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_LRGID);
-
-	/* set channels gains. */
-	SET_FIELD(NPCX_APM_GCR_ADCL, NPCX_APM_GCR_ADCL_GIDL, left_chan_gain);
-	SET_FIELD(NPCX_APM_GCR_ADCR, NPCX_APM_GCR_ADCR_GIDR, right_chan_gain);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_auto_gain_cntrl_enable(int enable)
-{
-	if (enable)
-		NPCX_APM_CR_ADC_AGC = 0x80;
-	else
-		NPCX_APM_CR_ADC_AGC = 0x00;
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   gain_cfg - struct of apm auto gain config
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg)
-{
-	uint8_t gain_data = 0;
-
-	/* Check parameters validity. */
-
-	if (gain_cfg->gain_min > gain_cfg->gain_max)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Store the parameters in order to use them in case the function
-	 * was called prioe calling to wov_set_mode.
-	 */
-	apm_gain_conf.stereo_enable = gain_cfg->stereo_enable;
-	apm_gain_conf.agc_target = gain_cfg->agc_target;
-	apm_gain_conf.nois_gate_en = gain_cfg->nois_gate_en;
-	apm_gain_conf.nois_gate_thold = gain_cfg->nois_gate_thold;
-	apm_gain_conf.hold_time = gain_cfg->hold_time;
-	apm_gain_conf.attack_time = gain_cfg->attack_time;
-	apm_gain_conf.decay_time = gain_cfg->decay_time;
-	apm_gain_conf.gain_max = gain_cfg->gain_max;
-	apm_gain_conf.gain_min = gain_cfg->gain_min;
-
-	/* Set the parameters. */
-
-	if (gain_cfg->stereo_enable)
-		CLEAR_BIT(gain_data, NPCX_ADC_AGC_0_AGC_STEREO);
-	else
-		SET_BIT(gain_data, NPCX_ADC_AGC_0_AGC_STEREO);
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_0_AGC_TARGET, gain_cfg->agc_target);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_0_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	if (gain_cfg->nois_gate_en)
-		SET_BIT(gain_data, NPCX_ADC_AGC_1_NG_EN);
-	else
-		CLEAR_BIT(gain_data, NPCX_ADC_AGC_1_NG_EN);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_1_NG_THR, gain_cfg->nois_gate_thold);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_1_HOLD, gain_cfg->hold_time);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_1_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_2_ATK, gain_cfg->attack_time);
-	SET_FIELD(gain_data, NPCX_ADC_AGC_2_DCY, gain_cfg->decay_time);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_2_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_3_AGC_MAX, gain_cfg->gain_max);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_3_REG,
-				gain_data);
-
-	gain_data = 0;
-
-	SET_FIELD(gain_data, NPCX_ADC_AGC_4_AGC_MIN, gain_cfg->gain_min);
-
-	apm_write_indirect_data(APM_ADC_AGC_REG, APM_INDIRECT_ADC_AGC_4_REG,
-				gain_data);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Sets APM mode (enables & disables APN sub modules accordingly
- * to the APM mode).
- *
- * @param apm_mode - APM mode, DEFAULT, DETECTION, RECORD or INDEPENDENT modes.
- * @return  None
- */
-void apm_set_mode(enum wov_modes wov_mode)
-{
-	apm_enable(0);
-
-	switch (wov_mode) {
-	case WOV_MODE_OFF:
-		apm_enable_vad_interrupt(0);
-		apm_dmic_enable(0);
-		apm_adc_enable(0);
-		apm_vad_enable(0);
-		wov_apm_active(0);
-		break;
-
-	case WOV_MODE_VAD:
-		apm_clear_vad_detected_bit();
-		wov_apm_active(1);
-		apm_dmic_enable(1);
-		apm_adc_wov_enable(1);
-		apm_set_vad_dmic_rate_l(apm_conf.vad_dmic_rate);
-		apm_set_vad_sensitivity(wov_conf.sensitivity_db);
-		apm_enable_vad_interrupt(1);
-		apm_vad_restart();
-		apm_vad_enable(1);
-		break;
-
-	case WOV_MODE_RAM:
-	case WOV_MODE_I2S:
-	case WOV_MODE_RAM_AND_I2S:
-		wov_apm_active(1);
-		apm_vad_enable(0);
-		apm_enable_vad_interrupt(0);
-		if (wov_mode == WOV_MODE_RAM)
-			apm_set_adc_dmic_config_l(apm_conf.adc_ram_dmic_rate);
-		else
-			apm_set_adc_dmic_config_l(apm_conf.adc_i2s_dmic_rate);
-		apm_dmic_enable(1);
-		apm_adc_enable(1);
-		break;
-
-	default:
-		apm_set_vad_dmic_rate_l(APM_DMIC_RATE_1_0);
-		apm_set_adc_dmic_config_l(APM_DMIC_RATE_1_0);
-		apm_vad_enable(0);
-		apm_enable_vad_interrupt(0);
-		apm_dmic_enable(0);
-		apm_adc_enable(0);
-		wov_apm_active(0);
-		break;
-	}
-
-	apm_adc_gain_config(apm_conf.gain_coupling,
-				apm_conf.left_chan_gain,
-				apm_conf.right_chan_gain);
-
-	apm_adc_auto_gain_config(&apm_gain_conf);
-
-	apm_adc_set_freq(apm_adc_freq_val_2_code(wov_conf.sample_per_sec));
-
-	if (wov_mode != WOV_MODE_OFF)
-		apm_enable(1);
-}
-
-/**
- * Clears VAD detected bit in IFR register.
- *
- * @param   None
- * @return  None.
- */
-void apm_clear_vad_detected_bit(void)
-{
-	apm_vad_enable(0);
-
-	APM_CLEAR_VAD_INTERRUPT;
-}
diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h
deleted file mode 100644
index ad62538374..0000000000
--- a/chip/npcx/apm_chip.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_APM_CHIP_H
-#define __CROS_EC_APM_CHIP_H
-
-#include "common.h"
-
-/* MIX indirect registers. */
-#define APM_INDIRECT_MIX_2_REG      0x02
-
-/* ADC_AGC indirect registers. */
-#define APM_INDIRECT_ADC_AGC_0_REG  0x00
-#define APM_INDIRECT_ADC_AGC_1_REG  0x01
-#define APM_INDIRECT_ADC_AGC_2_REG  0x02
-#define APM_INDIRECT_ADC_AGC_3_REG  0x03
-#define APM_INDIRECT_ADC_AGC_4_REG  0x04
-
-/* APM_VAD_REG indirect registers. */
-#define APM_INDIRECT_VAD_0_REG       0x00
-#define APM_INDIRECT_VAD_1_REG       0x01
-
-/* APM macros. */
-#define APM_IS_IRQ_PENDING    IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
-#define APM_IS_VOICE_ACTIVITY_DETECTED \
-	IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-#define APM_CLEAR_VAD_INTERRUPT    SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-
-/* Indirect registers. */
-enum apm_indirect_reg_offset {
-	APM_MIX_REG = 0,
-	APM_ADC_AGC_REG,
-	APM_VAD_REG
-};
-
-/* ADC wind noise filter modes. */
-enum apm_adc_wind_noise_filter_mode {
-	APM_ADC_WIND_NOISE_FILTER_INACTIVE = 0,
-	APM_ADC_WIND_NOISE_FILTER_MODE_1_ACTIVE,
-	APM_ADC_WIND_NOISE_FILTER_MODE_2_ACTIVE,
-	APM_ADC_WIND_NOISE_FILTER_MODE_3_ACTIVE,
-};
-
-/* ADC frequency. */
-enum apm_adc_frequency {
-	APM_ADC_FREQ_8_000_KHZ = 0x00,
-	APM_ADC_FREQ_11_025_KHZ,
-	APM_ADC_FREQ_12_000_KHZ,
-	APM_ADC_FREQ_16_000_KHZ,
-	APM_ADC_FREQ_22_050_KHZ,
-	APM_ADC_FREQ_24_000_KHZ,
-	APM_ADC_FREQ_32_000_KHZ,
-	APM_ADC_FREQ_44_100_KHZ,
-	APM_ADC_FREQ_48_000_KHZ,
-	APM_ADC_FREQ_UNSUPPORTED = 0x0F
-};
-
-/* DMIC source. */
-enum apm_dmic_src {
-	APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */
-	APM_AVERAGE_DMIC_CHANNEL = 0x02  /* Average between left & right.   */
-};
-
-/* ADC digital microphone rate. */
-enum apm_dmic_rate {
-	/* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */
-	APM_DMIC_RATE_3_0 = 0,   /* 3.0 -3.25 MHz (default). */
-	APM_DMIC_RATE_2_4,       /* 2.4 -2.6 MHz.            */
-	APM_DMIC_RATE_1_0,       /* 1.0 -1.08 MHz.           */
-	APM_DMIC_RATE_1_2,       /* 1.2 MHz.                        */
-	APM_DMIC_RATE_0_75       /* 750 KHz.                 */
-};
-
-/* Digitla mixer output. */
-enum apm_dig_mix {
-	APM_OUT_MIX_NORMAL_INPUT = 0,    /* Default. */
-	APM_OUT_MIX_CROSS_INPUT,
-	APM_OUT_MIX_MIXED_INPUT,
-	APM_OUT_MIX_NO_INPUT
-};
-
-/* VAD Input Channel Selection */
-enum apm_vad_in_channel_src {
-	APM_IN_LEFT = 0,
-	APM_IN_RIGHT,
-	APM_IN_AVERAGE_LEFT_RIGHT,
-	APM_IN_RESERVED
-};
-
-/* ADC digital gain coupling. */
-enum apm_adc_gain_coupling {
-	APM_ADC_CHAN_GAINS_INDEPENDENT = 0,
-	APM_ADC_RIGHT_CHAN_GAIN_TRACKS_LEFT
-};
-
-/* ADC target output level. */
-enum apm_adc_target_out_level {
-	APM_ADC_MAX_TARGET_LEVEL = 0,
-	APM_ADC_MAX_TARGET_LEVEL_1_5,
-	APM_ADC_MAX_TARGET_LEVEL_3_0,
-	APM_ADC_MAX_TARGET_LEVEL_4_5,
-	APM_ADC_MAX_TARGET_LEVEL_6_0,
-	APM_ADC_MAX_TARGET_LEVEL_7_5,
-	APM_ADC_MAX_TARGET_LEVEL_9_0,
-	APM_ADC_MAX_TARGET_LEVEL_10_5,
-	APM_ADC_MAX_TARGET_LEVEL_12_0,
-	APM_ADC_MAX_TARGET_LEVEL_13_5,
-	APM_ADC_MAX_TARGET_LEVEL_15_0,
-	APM_ADC_MAX_TARGET_LEVEL_16_5,
-	APM_ADC_MAX_TARGET_LEVEL_18_0,
-	APM_ADC_MAX_TARGET_LEVEL_19_5, /* Default. */
-	APM_ADC_MAX_TARGET_LEVEL_21_0,
-	APM_ADC_MAX_TARGET_LEVEL_22_5
-};
-
-/* Noise gate threshold values. */
-enum apm_noise_gate_threshold {
-	APM_MIN_NOISE_GET_THRESHOLD = 0,
-	APM_MIN_NOISE_GET_THRESHOLD_6,
-	APM_MIN_NOISE_GET_THRESHOLD_12,
-	APM_MIN_NOISE_GET_THRESHOLD_18,
-	APM_MIN_NOISE_GET_THRESHOLD_24,
-	APM_MIN_NOISE_GET_THRESHOLD_30,
-	APM_MIN_NOISE_GET_THRESHOLD_36,
-	APM_MIN_NOISE_GET_THRESHOLD_42
-};
-
-/* Hold time in msec before starting AGC adjustment to the TARGET value. */
-enum apm_agc_adj_hold_time {
-	APM_HOLD_TIME_0 = 0,
-	APM_HOLD_TIME_2,
-	APM_HOLD_TIME_4,
-	APM_HOLD_TIME_8,
-	APM_HOLD_TIME_16,
-	APM_HOLD_TIME_32,
-	APM_HOLD_TIME_64,
-	APM_HOLD_TIME_128, /* Default. */
-	APM_HOLD_TIME_256,
-	APM_HOLD_TIME_512,
-	APM_HOLD_TIME_1024,
-	APM_HOLD_TIME_2048,
-	APM_HOLD_TIME_4096,
-	APM_HOLD_TIME_8192,
-	APM_HOLD_TIME_16384,
-	APM_HOLD_TIME_32768
-};
-
-/* Attack time in msec - gain ramp down. */
-enum apm_gain_ramp_time {
-	APM_GAIN_RAMP_TIME_32 = 0,
-	APM_GAIN_RAMP_TIME_64,
-	APM_GAIN_RAMP_TIME_96,
-	APM_GAIN_RAMP_TIME_128,
-	APM_GAIN_RAMP_TIME_160, /* Default. */
-	APM_GAIN_RAMP_TIME_192,
-	APM_GAIN_RAMP_TIME_224,
-	APM_GAIN_RAMP_TIME_256,
-	APM_GAIN_RAMP_TIME_288,
-	APM_GAIN_RAMP_TIME_320,
-	APM_GAIN_RAMP_TIME_352,
-	APM_GAIN_RAMP_TIME_384,
-	APM_GAIN_RAMP_TIME_416,
-	APM_GAIN_RAMP_TIME_448,
-	APM_GAIN_RAMP_TIME_480,
-	APM_GAIN_RAMP_TIME_512
-};
-
-/* Minimum and Maximum gain values. */
-enum apm_gain_values {
-	APM_GAIN_VALUE_0_0 = 0,
-	APM_GAIN_VALUE_1_5,
-	APM_GAIN_VALUE_3_0,
-	APM_GAIN_VALUE_4_5,
-	APM_GAIN_VALUE_6_0,
-	APM_GAIN_VALUE_7_5,
-	APM_GAIN_VALUE_9_0,
-	APM_GAIN_VALUE_10_5,
-	APM_GAIN_VALUE_12_0,
-	APM_GAIN_VALUE_13_5,
-	APM_GAIN_VALUE_15_0,
-	APM_GAIN_VALUE_16_5,
-	APM_GAIN_VALUE_18_0,
-	APM_GAIN_VALUE_19_5,
-	APM_GAIN_VALUE_21_0,
-	APM_GAIN_VALUE_22_5,
-	APM_GAIN_VALUE_23_0_1ST,
-	APM_GAIN_VALUE_23_0_2ND,
-	APM_GAIN_VALUE_23_0_3RD,
-	APM_GAIN_VALUE_24_5,
-	APM_GAIN_VALUE_26_0,
-	APM_GAIN_VALUE_27_5,
-	APM_GAIN_VALUE_29_0,
-	APM_GAIN_VALUE_30_5,
-	APM_GAIN_VALUE_32_0,
-	APM_GAIN_VALUE_33_5,
-	APM_GAIN_VALUE_35_0,
-	APM_GAIN_VALUE_36_5,
-	APM_GAIN_VALUE_38_0,
-	APM_GAIN_VALUE_39_5,
-	APM_GAIN_VALUE_41_0,
-	APM_GAIN_VALUE_42_5
-};
-
-/* ADC Audio Data Word Length */
-enum apm_adc_data_length {
-	APM_ADC_DATA_LEN_16_BITS = 0x00,
-	APM_ADC_DATA_LEN_18_BITS,
-	APM_ADC_DATA_LEN_20_BITS,
-	APM_ADC_DATA_LEN_24_BITS
-};
-
-struct apm_config {
-	enum apm_dmic_rate vad_dmic_rate;
-	enum apm_dmic_rate adc_ram_dmic_rate;
-	enum apm_dmic_rate adc_i2s_dmic_rate;
-	enum apm_adc_gain_coupling gain_coupling;
-	uint8_t left_chan_gain;
-	uint8_t right_chan_gain;
-};
-struct apm_auto_gain_config {
-	int stereo_enable;
-	enum apm_adc_target_out_level agc_target;
-	int nois_gate_en;
-	enum apm_noise_gate_threshold nois_gate_thold;
-	enum apm_agc_adj_hold_time hold_time;
-	enum apm_gain_ramp_time attack_time;
-	enum apm_gain_ramp_time decay_time;
-	enum apm_gain_values gain_max;
-	enum apm_gain_values gain_min;
-};
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-enum wov_modes;
-/**
- * Sets the RAM ADC DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_ram_dmic_config(enum apm_dmic_rate rate);
-
-/**
- * Gets the RAM ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_ram_dmic_rate(void);
-
-/**
- * Sets the ADC I2S DMIC rate.
- *
- * @param   rate      - ADC digital microphone rate
- * @return  None
- */
-void apm_set_adc_i2s_dmic_config(enum apm_dmic_rate rate);
-
-/**
- * Gets the ADC I2S DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_i2s_dmic_rate(void);
-
-/**
- * Sets VAD DMIC rate.
- *
- * @param   rate    - VAD DMIC rate
- *
- * @return  None
- */
-void apm_set_vad_dmic_rate(enum apm_dmic_rate rate);
-
-/**
- * Gets VAD DMIC rate.
- *
- * @param   None
- *
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_vad_dmic_rate(void);
-
-/**
- * Gets the ADC DMIC rate.
- *
- * @param   None
- * @return  ADC digital microphone rate code.
- */
-enum apm_dmic_rate apm_get_adc_dmic_rate(void);
-
-/**
- * Initiate APM module local parameters..
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void apm_init(void);
-
-/**
- * Enables/Disables APM  module.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_enable(int enable);
-
-/**
- * Enables/Disables voice activity detected interrupt.
- *
- * @param   enable - enabled flag, true means enable
- * @return  APM interrupt mode.
- */
-void apm_enable_vad_interrupt(int enable);
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_adc_enable(int enable);
-
-/**
- * sets the ADC frequency.
- *
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_set_freq(enum apm_adc_frequency adc_freq);
-
-/**
- * Configures the ADC.
- *
- * @param   hpf_enable  - High pass filter enabled flag, true means enable
- * @param   filter_mode - ADC wind noise filter mode.
- * @param   adc_freq    - ADC frequency.
- * @return  None
- */
-void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq);
-
-/**
- * Enables/Disables Digital Microphone.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_dmic_enable(int enable);
-
-/**
- * Configures Digital Microphone.
- *
- * @param   mix_left  - Mixer left channel output selection on ADC path.
- * @param   mix_right - Mixer right channel output selection on ADC path.
- * @return  None
- */
-void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-		enum apm_dig_mix mix_right);
-
-/**
- * Enables/Disables the VAD functionality.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_vad_enable(int enable);
-
-/**
- * Enables/Disables VAD ADC wakeup
- *
- * @param   enable - true enable, false disable.
- *
- * @return  None
- */
-void apm_vad_adc_wakeup_enable(int enable);
-
-/**
- * Sets VAD Input chanel.
- *
- * @param   chan_src	- Processed digital microphone channel
- *			  selection.
- * @return  None
- */
-void apm_set_vad_input_channel(enum apm_vad_in_channel_src chan_src);
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-void apm_set_vad_sensitivity(uint8_t sensitivity_db);
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-uint8_t apm_get_vad_sensitivity(void);
-
-/**
- * Restarts VAD functionality.
- *
- * @param   None
- * @return  None
- */
-void apm_vad_restart(void);
-
-/**
- * Restarts VAD functionality.
- *
- * @param   gain_coupling   - ADC digital gain coupling (independent or
- *                            rigth tracks left).
- * @param   left_chan_gain  - Left channel ADC digital gain programming value.
- * @param   right_chan_gain - Right channel ADC digital gain programming value.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-			uint8_t left_chan_gain, uint8_t right_chan_gain);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   enable - enabled flag, true means enable
- * @return  None
- */
-void apm_auto_gain_cntrl_enable(int enable);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param   gain_cfg - struct of apm auto gain config
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg);
-
-/**
- * Sets APM mode (enables & disables APN sub modules accordingly
- * to the APM mode).
- *
- * @param apm_mode - APM mode, DEFAULT, DETECTION, RECORD or INDEPENDENT modes.
- * @return  None
- */
-void apm_set_mode(enum wov_modes wov_mode);
-
-/**
- * Clears VAD detected bit in IFR register.
- *
- * @param   None
- * @return  None.
- */
-void apm_clear_vad_detected_bit(void);
-
-#endif /* __CROS_EC_APM_CHIP_H */
diff --git a/chip/npcx/audio_codec_dmic.c b/chip/npcx/audio_codec_dmic.c
deleted file mode 100644
index e242a8b2d2..0000000000
--- a/chip/npcx/audio_codec_dmic.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "ec_commands.h"
-#include "wov_chip.h"
-
-int audio_codec_dmic_get_max_gain(uint8_t *gain)
-{
-	*gain = 31;
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain)
-{
-	int left_gain, right_gain;
-
-	wov_get_gain(&left_gain, &right_gain);
-
-	switch (channel) {
-	case EC_CODEC_DMIC_CHANNEL_0:
-		left_gain = gain;
-		break;
-	case EC_CODEC_DMIC_CHANNEL_1:
-		right_gain = gain;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	wov_set_gain(left_gain, right_gain);
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain)
-{
-	int left_gain, right_gain;
-
-	wov_get_gain(&left_gain, &right_gain);
-
-	switch (channel) {
-	case EC_CODEC_DMIC_CHANNEL_0:
-		*gain = left_gain;
-		break;
-	case EC_CODEC_DMIC_CHANNEL_1:
-		*gain = right_gain;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c
deleted file mode 100644
index 12c4173048..0000000000
--- a/chip/npcx/audio_codec_i2s_rx.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "ec_commands.h"
-#include "wov_chip.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-int audio_codec_i2s_rx_enable(void)
-{
-	/*
-	 * The mic source and sample rate don't need to be set each time
-	 * an i2s stream is started, but the audio codec does not
-	 * contain a method to select these as they must be the values
-	 * set below for proper i2s operation. Since the default values
-	 * set in wov.c are different than what's required, they are set
-	 * each time an i2s stream is started.
-	 */
-	wov_set_mic_source(WOV_SRC_STEREO);
-
-	/* Mode must be WOV_MODE_OFF to change sample rate */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_sample_rate(48000);
-
-	return wov_set_mode(WOV_MODE_I2S);
-}
-
-int audio_codec_i2s_rx_disable(void)
-{
-	return wov_set_mode(WOV_MODE_OFF);
-}
-
-int audio_codec_i2s_rx_set_sample_depth(uint8_t depth)
-{
-	int bits_num;
-
-	if (depth == EC_CODEC_I2S_RX_SAMPLE_DEPTH_24)
-		bits_num = 24;
-	else
-		bits_num = 16;
-
-	/* Sample depth can only be changed when mode is WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	return wov_set_sample_depth(bits_num);
-}
-
-int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt)
-{
-	enum wov_dai_format fmt = WOV_DAI_FMT_I2S;
-
-	switch (daifmt) {
-	case EC_CODEC_I2S_RX_DAIFMT_I2S:
-		fmt = WOV_DAI_FMT_I2S;
-		break;
-	case EC_CODEC_I2S_RX_DAIFMT_RIGHT_J:
-		fmt = WOV_DAI_FMT_RIGHT_J;
-		break;
-	case EC_CODEC_I2S_RX_DAIFMT_LEFT_J:
-		fmt = WOV_DAI_FMT_LEFT_J;
-		break;
-	}
-
-	/* To change mode setting it must be set to WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_i2s_fmt(fmt);
-
-	return EC_SUCCESS;
-}
-
-int audio_codec_i2s_rx_set_bclk(uint32_t bclk)
-{
-	/* To change bclk setting it must be set to WOV_MODE_OFF */
-	wov_set_mode(WOV_MODE_OFF);
-	wov_set_i2s_bclk(bclk);
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
deleted file mode 100644
index 4be1b2994f..0000000000
--- a/chip/npcx/build.mk
+++ /dev/null
@@ -1,92 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# NPCX chip specific files build
-#
-
-# NPCX SoC has a Cortex-M4F ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
-# Assign default CHIP_FAMILY as npcx5 for old boards used npcx5 series
-ifeq ($(CHIP_FAMILY),)
-CHIP_FAMILY:=npcx5
-endif
-
-# Required chip modules
-chip-y=header.o clock.o gpio.o hwtimer.o system.o uart.o uartn.o sib.o
-chip-y+=system-$(CHIP_FAMILY).o
-chip-y+=gpio-$(CHIP_FAMILY).o
-
-# Optional chip modules
-chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_AUDIO_CODEC)+=apm.o wov.o
-chip-$(CONFIG_AUDIO_CODEC_DMIC)+=audio_codec_dmic.o
-chip-$(CONFIG_AUDIO_CODEC_I2S_RX)+=audio_codec_i2s_rx.o
-chip-$(CONFIG_FANS)+=fan.o
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
-chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
-chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
-chip-$(CONFIG_PECI)+=peci.o
-chip-$(CONFIG_HOSTCMD_SHI)+=shi.o
-chip-$(CONFIG_CEC)+=cec.o
-# pwm functions are implemented with the fan functions
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-
-chip-$(CONFIG_PS2)+=ps2.o
-# Only npcx9 or later chip family can support LCT module
-ifneq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),npcx5 npcx7))
-chip-y+=lct.o
-endif
-
-chip-$(CONFIG_SHA256_HW_ACCELERATE)+=sha256_chip.o
-
-# spi monitor program fw for openocd and UUT(UART Update Tool)
-npcx-monitor-fw=chip/npcx/spiflashfw/npcx_monitor
-npcx-monitor-fw-bin=${out}/$(npcx-monitor-fw).bin
-PROJECT_EXTRA+=${npcx-monitor-fw-bin}
-# Monitor header is only used for UUT which is not supported on npcx5.
-ifneq "$(CHIP_FAMILY)" "npcx5"
-npcx-monitor-hdr=chip/npcx/spiflashfw/monitor_hdr
-npcx-monitor-hdr-ro-bin=${out}/$(npcx-monitor-hdr)_ro.bin
-npcx-monitor-hdr-rw-bin=${out}/$(npcx-monitor-hdr)_rw.bin
-PROJECT_EXTRA+=${npcx-monitor-hdr-ro-bin} ${npcx-monitor-hdr-rw-bin}
-endif
-
-# ECST tool is for filling the header used by booter of npcx EC
-show_esct_cmd=$(if $(V),,echo '  ECST   ' $(subst $(out)/,,$@) ; )
-
-# Get the firmware length from the mapfile.  This can differ from the file
-# size when the CONFIG_CHIP_INIT_ROM_REGION is used. Note that the -fwlen
-# parameter for the ecst utility must be in hex.
-cmd_fwlen=$(shell awk '\
-  /__flash_used =/ {flash_used = strtonum($$1)} \
-  END {printf ("%x", flash_used)}' $(1))
-
-# ECST options for header
-bld_ecst=${out}/util/ecst -chip $(CHIP_VARIANT) \
-	-usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc -nofcrc -flashsize 8 \
-	-fwlen $(call cmd_fwlen, $(patsubst %.flat,%.map,$(2))) \
-	-spimaxclk 50 -spireadmode dual 1> /dev/null
-
-# Replace original one with the flat file including header
-moveflat=mv -f $(1) $(2)
-
-# Commands for ECST
-cmd_ecst=$(show_esct_cmd)$(call moveflat,$@,$@.tmp);$(call bld_ecst,$@.tmp,$@)
-
-# Commands to append npcx header in ec.RO.flat
-cmd_org_ec_elf_to_flat = $(OBJCOPY) --set-section-flags .roshared=share \
-                         -O binary $(patsubst %.flat,%.elf,$@) $@
-cmd_npcx_ro_elf_to_flat=$(cmd_org_ec_elf_to_flat);$(cmd_ecst)
-cmd_ec_elf_to_flat = $(if $(filter $(out)/RO/ec.RO.flat, $@), \
-                     $(cmd_npcx_ro_elf_to_flat), $(cmd_org_ec_elf_to_flat) )
diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
deleted file mode 100644
index ebaefa551a..0000000000
--- a/chip/npcx/cec.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "cec.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if !(DEBUG_CEC)
-#define CPRINTF(...)
-#define CPRINTS(...)
-#else
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
-#endif
-
-/* Time in us to timer clock ticks */
-#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100)
-#if DEBUG_CEC
-/* Timer clock ticks to us */
-#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k)
-#endif
-
-/* Notification from interrupt to CEC task that data has been received */
-#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0)
-
-/* CEC broadcast address. Also the highest possible CEC address */
-#define CEC_BROADCAST_ADDR 15
-
-/* Address to indicate that no logical address has been set */
-#define CEC_UNREGISTERED_ADDR 255
-
-/*
- * The CEC specification requires at least one and a maximum of
- * five resends attempts
- */
-#define CEC_MAX_RESENDS 5
-
-/*
- * Free time timing (us). Our free-time is calculated from the end of
- * the last bit (not from the start). We compensate by having one
- * free-time period less than in the spec.
- */
-#define NOMINAL_BIT_TICKS APB1_TICKS(2400)
- /* Resend */
-#define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS))
-/* New initiator */
-#define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS))
-/* Present initiator */
-#define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS))
-
-/* Start bit timing */
-#define START_BIT_LOW_TICKS		APB1_TICKS(3700)
-#define START_BIT_MIN_LOW_TICKS		APB1_TICKS(3500)
-#define START_BIT_MAX_LOW_TICKS		APB1_TICKS(3900)
-#define START_BIT_HIGH_TICKS		APB1_TICKS(800)
-#define START_BIT_MIN_DURATION_TICKS	APB1_TICKS(4300)
-#define START_BIT_MAX_DURATION_TICKS	APB1_TICKS(5700)
-
-/* Data bit timing */
-#define DATA_ZERO_LOW_TICKS		APB1_TICKS(1500)
-#define DATA_ZERO_MIN_LOW_TICKS		APB1_TICKS(1300)
-#define DATA_ZERO_MAX_LOW_TICKS		APB1_TICKS(1700)
-#define DATA_ZERO_HIGH_TICKS		APB1_TICKS(900)
-#define DATA_ZERO_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ZERO_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-#define DATA_ONE_LOW_TICKS		APB1_TICKS(600)
-#define DATA_ONE_MIN_LOW_TICKS		APB1_TICKS(400)
-#define DATA_ONE_MAX_LOW_TICKS		APB1_TICKS(800)
-#define DATA_ONE_HIGH_TICKS		APB1_TICKS(1800)
-#define DATA_ONE_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ONE_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-/* Time from low that it should be safe to sample an ACK */
-#define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050)
-
-#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \
-					(DATA_ZERO_ ## type ## _TICKS))
-#define DATA_HIGH(data) DATA_TIME(HIGH, data)
-#define DATA_LOW(data) DATA_TIME(LOW, data)
-
-/*
- * Number of short pulses seen before the debounce logic goes into ignoring
- * the bus for DEBOUNCE_WAIT_LONG instead of DEBOUNCE_WAIT_SHORT
- */
-#define DEBOUNCE_CUTOFF 3
-
-/* The limit how short a start-bit can be to trigger debounce logic */
-#define DEBOUNCE_LIMIT_TICKS APB1_TICKS(200)
-/* The time we ignore the bus for the first three debounce cases */
-#define DEBOUNCE_WAIT_SHORT_TICKS APB1_TICKS(100)
-/* The time we ignore the bus after the three initial debounce cases */
-#define DEBOUNCE_WAIT_LONG_TICKS APB1_TICKS(500)
-
-/*
- * The variance in timing we allow outside of the CEC specification for
- * incoming signals. Our measurements aren't 100% accurate either, so this
- * gives some robustness.
- */
-#define VALID_TOLERANCE_TICKS APB1_TICKS(100)
-
-/*
- * Defines used for setting capture timers to a point where we are
- * sure that if we get a timeout, something is wrong.
- */
-#define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \
-			      START_BIT_MIN_LOW_TICKS +	\
-			      VALID_TOLERANCE_TICKS)
-#define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \
-			     DATA_ONE_MIN_LOW_TICKS + \
-			     VALID_TOLERANCE_TICKS)
-
-#define VALID_TIME(type, bit, t) \
-	((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \
-	 && (t) <=  (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS))
-#define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t)
-#define VALID_HIGH(bit, low_time, high_time) \
-	(((low_time) + (high_time) <= \
-	  bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
-	 ((low_time) + (high_time) >= \
-	  bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
-#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \
-				VALID_HIGH(DATA_ONE, low_time, high_time) : \
-				VALID_HIGH(DATA_ZERO, low_time, high_time))
-
-/*
- * CEC state machine states. Each state typically takes action on entry and
- * timeouts. INITIATIOR states are used for sending, FOLLOWER states are used
- *  for receiving.
- */
-enum cec_state {
-	CEC_STATE_DISABLED = 0,
-	CEC_STATE_IDLE,
-	CEC_STATE_INITIATOR_FREE_TIME,
-	CEC_STATE_INITIATOR_START_LOW,
-	CEC_STATE_INITIATOR_START_HIGH,
-	CEC_STATE_INITIATOR_HEADER_INIT_LOW,
-	CEC_STATE_INITIATOR_HEADER_INIT_HIGH,
-	CEC_STATE_INITIATOR_HEADER_DEST_LOW,
-	CEC_STATE_INITIATOR_HEADER_DEST_HIGH,
-	CEC_STATE_INITIATOR_DATA_LOW,
-	CEC_STATE_INITIATOR_DATA_HIGH,
-	CEC_STATE_INITIATOR_EOM_LOW,
-	CEC_STATE_INITIATOR_EOM_HIGH,
-	CEC_STATE_INITIATOR_ACK_LOW,
-	CEC_STATE_INITIATOR_ACK_HIGH,
-	CEC_STATE_INITIATOR_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_START_LOW,
-	CEC_STATE_FOLLOWER_START_HIGH,
-	CEC_STATE_FOLLOWER_DEBOUNCE,
-	CEC_STATE_FOLLOWER_HEADER_INIT_LOW,
-	CEC_STATE_FOLLOWER_HEADER_INIT_HIGH,
-	CEC_STATE_FOLLOWER_HEADER_DEST_LOW,
-	CEC_STATE_FOLLOWER_HEADER_DEST_HIGH,
-	CEC_STATE_FOLLOWER_EOM_LOW,
-	CEC_STATE_FOLLOWER_EOM_HIGH,
-	CEC_STATE_FOLLOWER_ACK_LOW,
-	CEC_STATE_FOLLOWER_ACK_VERIFY,
-	CEC_STATE_FOLLOWER_ACK_FINISH,
-	CEC_STATE_FOLLOWER_DATA_LOW,
-	CEC_STATE_FOLLOWER_DATA_HIGH,
-};
-
-/* Edge to trigger capture timer interrupt on */
-enum cap_edge {
-	CAP_EDGE_FALLING,
-	CAP_EDGE_RISING
-};
-
-/* Receive buffer and states */
-struct cec_rx {
-	/*
-	 * The current incoming message being parsed. Copied to
-	 * receive queue upon completion
-	 */
-	struct cec_msg_transfer transfer;
-	/* End of Message received from source? */
-	uint8_t eom;
-	/* A follower NAK:ed a broadcast transfer */
-	uint8_t broadcast_nak;
-	/*
-	 * Keep track of pulse low time to be able to verify
-	 * pulse duration
-	 */
-	int low_ticks;
-	/* Number of too short pulses seen in a row */
-	int debounce_count;
-};
-
-/* Transfer buffer and states */
-struct cec_tx {
-	/* Outgoing message */
-	struct cec_msg_transfer transfer;
-	/* Message length */
-	uint8_t len;
-	/* Number of resends attempted in current send */
-	uint8_t resends;
-	/* Acknowledge received from sink? */
-	uint8_t ack;
-	/*
-	 * When sending multiple concurrent frames,
-	 * the free-time is slightly higher
-	 */
-	int present_initiator;
-};
-
-/* Single state for CEC. We are INITIATOR, FOLLOWER or IDLE */
-static enum cec_state cec_state;
-
-/* Parameters and buffers for follower (receiver) state */
-static struct cec_rx cec_rx;
-
-/* Queue of completed incoming CEC messages */
-static struct cec_rx_queue cec_rx_queue;
-
-/* Parameters and buffer for initiator (sender) state */
-static struct cec_tx cec_tx;
-
-/*
- * Time between interrupt triggered and the next timer was
- * set when measuring pulse width
- */
-static int cap_delay;
-
-/* Value charged into the capture timer on last capture start */
-static int cap_charge;
-
-/*
- * CEC address of ourself. We ack incoming packages on this address.
- * However, the AP is responsible for writing the initiator address
- * on writes. UINT32_MAX means means that the address hasn't been
- * set by the AP yet.
- */
-static uint8_t cec_addr = UINT8_MAX;
-
-/* Events to send to AP */
-static uint32_t cec_events;
-
-/* APB1 frequency. Store divided by 10k to avoid some runtime divisions */
-static uint32_t apb1_freq_div_10k;
-
-static void send_mkbp_event(uint32_t event)
-{
-	atomic_or(&cec_events, event);
-	mkbp_send_event(EC_MKBP_EVENT_CEC_EVENT);
-}
-
-static void tmr_cap_start(enum cap_edge edge, int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* Select edge to trigger capture on */
-	UPDATE_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG,
-		   edge == CAP_EDGE_RISING);
-
-	/*
-	 * Set capture timeout. If we don't have a timeout, we
-	 * turn the timeout interrupt off and only care about
-	 * the edge change.
-	 */
-	if (timeout > 0) {
-		/*
-		 * Store the time it takes from the interrupts starts to when we
-		 * actually get here. This part of the pulse-width needs to be
-		 * taken into account
-		 */
-		cap_delay = (0xffff - NPCX_TCNT1(mdl));
-		cap_charge = timeout - cap_delay;
-		NPCX_TCNT1(mdl) = cap_charge;
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	} else {
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-		NPCX_TCNT1(mdl) = 0;
-	}
-
-	/* Clear out old events */
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
-	SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
-	NPCX_TCRA(mdl) = 0;
-	/* Start the capture timer */
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr_cap_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TCIEN);
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 0);
-}
-
-static int tmr_cap_get(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	return (cap_charge + cap_delay - NPCX_TCRA(mdl));
-}
-
-static void tmr_oneshot_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT1(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, 1);
-}
-
-static void tmr2_start(int timeout)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	NPCX_TCNT2(mdl) = timeout;
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 1);
-}
-
-static void tmr2_stop(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C2CSEL_FIELD, 0);
-}
-
-void enter_state(enum cec_state new_state)
-{
-	int gpio = -1, timeout = -1;
-	enum cap_edge cap_edge = -1;
-	uint8_t addr;
-
-	cec_state = new_state;
-	switch (new_state) {
-	case CEC_STATE_DISABLED:
-		gpio = 1;
-		memset(&cec_rx, 0, sizeof(struct cec_rx));
-		memset(&cec_tx, 0, sizeof(struct cec_tx));
-		memset(&cec_rx_queue, 0, sizeof(struct cec_rx_queue));
-		cap_charge = 0;
-		cap_delay = 0;
-		cec_events = 0;
-		break;
-	case CEC_STATE_IDLE:
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		cec_rx.transfer.bit = 0;
-		cec_rx.transfer.byte = 0;
-		if (cec_tx.len > 0) {
-			/* Execute a postponed send */
-			enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-		} else {
-			/* Wait for incoming command */
-			gpio = 1;
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = 0;
-		}
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		if (cec_tx.resends)
-			timeout = FREE_TIME_RS_TICKS;
-		else if (cec_tx.present_initiator)
-			timeout = FREE_TIME_PI_TICKS;
-		else
-			timeout = FREE_TIME_NI_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		cec_tx.present_initiator = 1;
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		gpio = 0;
-		timeout = START_BIT_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = START_BIT_HIGH_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		gpio = 1;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_get_bit(&cec_tx.transfer));
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer,
-						       cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer,
-							cec_tx.len));
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		gpio = 0;
-		timeout = DATA_LOW(1);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		gpio = 1;
-		/* Aim for the middle of the safe sample time */
-		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 -
-							DATA_ONE_LOW_TICKS;
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT);
-		if ((cec_tx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR) {
-			/*
-			 * We are sending a broadcast. Any follower can
-			 * can NAK a broadcast message the same way they
-			 * would ACK a direct message
-			 */
-			cec_tx.ack = !cec_tx.ack;
-		}
-		/*
-		 * We are at the safe sample time. Wait
-		 * until the end of this bit
-		 */
-		timeout = NOMINAL_BIT_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		cec_tx.present_initiator = 0;
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_START_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		cec_rx.debounce_count = 0;
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_START_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-		if (cec_rx.debounce_count >= DEBOUNCE_CUTOFF) {
-			timeout = DEBOUNCE_WAIT_LONG_TICKS;
-		} else {
-			timeout = DEBOUNCE_WAIT_SHORT_TICKS;
-			cec_rx.debounce_count++;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		addr = cec_rx.transfer.buf[0] & 0x0f;
-		if (addr == cec_addr) {
-			/* Destination is our address */
-			gpio = 0;
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		} else if (addr == CEC_BROADCAST_ADDR) {
-			/* Don't ack broadcast or packets which destination
-			 * are us, but continue reading
-			 */
-			timeout = NOMINAL_SAMPLE_TIME_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		/*
-		 * We are at safe sample time. A broadcast frame is considered
-		 * lost if any follower pulls the line low
-		 */
-		if ((cec_rx.transfer.buf[0] & 0x0f) == CEC_BROADCAST_ADDR)
-			cec_rx.broadcast_nak = !gpio_get_level(CEC_GPIO_OUT);
-		else
-			cec_rx.broadcast_nak = 0;
-
-		/*
-		 * We release the ACK at the end of data zero low
-		 * period (ACK is technically a zero).
-		 */
-		timeout = DATA_ZERO_LOW_TICKS - NOMINAL_SAMPLE_TIME_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		gpio = 1;
-		if (cec_rx.eom || cec_rx.transfer.byte >= MAX_CEC_MSG_LEN) {
-			addr = cec_rx.transfer.buf[0] & 0x0f;
-			if (addr == cec_addr || addr == CEC_BROADCAST_ADDR) {
-				task_set_event(TASK_ID_CEC,
-					       TASK_EVENT_RECEIVED_DATA);
-			}
-			timeout = DATA_ZERO_HIGH_TICKS;
-		} else {
-			cap_edge = CAP_EDGE_FALLING;
-			timeout = CAP_DATA_HIGH_TICKS;
-		}
-		break;
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		cap_edge = CAP_EDGE_RISING;
-		timeout = CAP_DATA_LOW_TICKS;
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		cap_edge = CAP_EDGE_FALLING;
-		timeout = CAP_DATA_HIGH_TICKS;
-		break;
-	/* No default case, since all states must be handled explicitly */
-	}
-
-	if (gpio >= 0)
-		gpio_set_level(CEC_GPIO_OUT, gpio);
-	if (timeout >= 0) {
-		if (cap_edge >= 0)
-			tmr_cap_start(cap_edge, timeout);
-		else
-			tmr_oneshot_start(timeout);
-	}
-}
-
-static void cec_event_timeout(void)
-{
-	switch (cec_state) {
-	case CEC_STATE_DISABLED:
-	case CEC_STATE_IDLE:
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-		enter_state(CEC_STATE_INITIATOR_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_START_LOW:
-		enter_state(CEC_STATE_INITIATOR_START_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_START_HIGH:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_INIT_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 4)
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_INIT_LOW);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_LOW:
-		enter_state(CEC_STATE_INITIATOR_HEADER_DEST_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_HEADER_DEST_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.byte == 1)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_HEADER_DEST_LOW);
-		break;
-	case CEC_STATE_INITIATOR_EOM_LOW:
-		enter_state(CEC_STATE_INITIATOR_EOM_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_EOM_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_LOW);
-		break;
-	case CEC_STATE_INITIATOR_ACK_LOW:
-		enter_state(CEC_STATE_INITIATOR_ACK_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_ACK_HIGH:
-		enter_state(CEC_STATE_INITIATOR_ACK_VERIFY);
-		break;
-	case CEC_STATE_INITIATOR_ACK_VERIFY:
-		if (cec_tx.ack) {
-			if (!cec_transfer_is_eom(&cec_tx.transfer,
-						 cec_tx.len)) {
-				/* More data in this frame */
-				enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-			} else {
-				/* Transfer completed successfully */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_OK);
-			}
-		} else {
-			if (cec_tx.resends < CEC_MAX_RESENDS) {
-				/* Resend */
-				cec_tx.resends++;
-				enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-			} else {
-				/* Transfer failed */
-				cec_tx.len = 0;
-				cec_tx.resends = 0;
-				enter_state(CEC_STATE_IDLE);
-				send_mkbp_event(EC_MKBP_CEC_SEND_FAILED);
-			}
-		}
-		break;
-	case CEC_STATE_INITIATOR_DATA_LOW:
-		enter_state(CEC_STATE_INITIATOR_DATA_HIGH);
-		break;
-	case CEC_STATE_INITIATOR_DATA_HIGH:
-		cec_transfer_inc_bit(&cec_tx.transfer);
-		if (cec_tx.transfer.bit == 0)
-			enter_state(CEC_STATE_INITIATOR_EOM_LOW);
-		else
-			enter_state(CEC_STATE_INITIATOR_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_VERIFY);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_VERIFY:
-		if (cec_rx.broadcast_nak)
-			enter_state(CEC_STATE_IDLE);
-		else
-			enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-	case CEC_STATE_FOLLOWER_START_HIGH:
-	case CEC_STATE_FOLLOWER_DEBOUNCE:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		enter_state(CEC_STATE_IDLE);
-		break;
-
-	}
-}
-
-static void cec_event_cap(void)
-{
-	int t;
-	int data;
-
-	switch (cec_state) {
-	case CEC_STATE_IDLE:
-		/* A falling edge during idle, likely a start bit */
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_INITIATOR_FREE_TIME:
-	case CEC_STATE_INITIATOR_START_HIGH:
-	case CEC_STATE_INITIATOR_HEADER_INIT_HIGH:
-		/*
-		 * A falling edge during free-time, postpone
-		 * this send and listen
-		 */
-		cec_tx.transfer.bit = 0;
-		cec_tx.transfer.byte = 0;
-		enter_state(CEC_STATE_FOLLOWER_START_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_START_LOW:
-		/* Rising edge of start bit, validate low time */
-		t =  tmr_cap_get();
-		if (VALID_LOW(START_BIT, t)) {
-			cec_rx.low_ticks = t;
-			enter_state(CEC_STATE_FOLLOWER_START_HIGH);
-		} else if (t < DEBOUNCE_LIMIT_TICKS) {
-			/* Wait a bit if start-pulses are really short */
-			enter_state(CEC_STATE_FOLLOWER_DEBOUNCE);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_START_HIGH:
-		if (VALID_HIGH(START_BIT, cec_rx.low_ticks, tmr_cap_get()))
-			enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_LOW:
-	case CEC_STATE_FOLLOWER_HEADER_DEST_LOW:
-	case CEC_STATE_FOLLOWER_DATA_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 0);
-			enter_state(cec_state + 1);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_transfer_set_bit(&cec_rx.transfer, 1);
-			enter_state(cec_state + 1);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_INIT_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 4)
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_INIT_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_HEADER_DEST_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_HEADER_DEST_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_LOW:
-		t = tmr_cap_get();
-		if (VALID_LOW(DATA_ZERO, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 0;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else if (VALID_LOW(DATA_ONE, t)) {
-			cec_rx.low_ticks = t;
-			cec_rx.eom = 1;
-			enter_state(CEC_STATE_FOLLOWER_EOM_HIGH);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	case CEC_STATE_FOLLOWER_EOM_HIGH:
-		t = tmr_cap_get();
-		data = cec_rx.eom;
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t))
-			enter_state(CEC_STATE_FOLLOWER_ACK_LOW);
-		else
-			enter_state(CEC_STATE_IDLE);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_LOW:
-		enter_state(CEC_STATE_FOLLOWER_ACK_FINISH);
-		break;
-	case CEC_STATE_FOLLOWER_ACK_FINISH:
-		enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		break;
-	case CEC_STATE_FOLLOWER_DATA_HIGH:
-		t = tmr_cap_get();
-		data = cec_transfer_get_bit(&cec_rx.transfer);
-		if (VALID_DATA_HIGH(data, cec_rx.low_ticks, t)) {
-			cec_transfer_inc_bit(&cec_rx.transfer);
-			if (cec_rx.transfer.bit == 0)
-				enter_state(CEC_STATE_FOLLOWER_EOM_LOW);
-			else
-				enter_state(CEC_STATE_FOLLOWER_DATA_LOW);
-		} else {
-			enter_state(CEC_STATE_IDLE);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static void cec_event_tx(void)
-{
-	/*
-	 * If we have an ongoing receive, this transfer
-	 * will start when transitioning to IDLE
-	 */
-	if (cec_state == CEC_STATE_IDLE)
-		enter_state(CEC_STATE_INITIATOR_FREE_TIME);
-}
-
-void cec_isr(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-	uint8_t events;
-
-	/* Retrieve events NPCX_TECTRL_TAXND */
-	events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4));
-
-	if (events & BIT(NPCX_TECTRL_TAPND)) {
-		/* Capture event */
-		cec_event_cap();
-	} else {
-		/*
-		 * Capture timeout
-		 * We only care about this if the capture event is not
-		 * happening, since we will get both events in the
-		 * edge-trigger case
-		 */
-		if (events & BIT(NPCX_TECTRL_TCPND))
-			cec_event_timeout();
-	}
-	/* Oneshot timer, a transfer has been initiated from AP */
-	if (events & BIT(NPCX_TECTRL_TDPND)) {
-		tmr2_stop();
-		cec_event_tx();
-	}
-
-	/* Clear handled events */
-	SET_FIELD(NPCX_TECLR(mdl), FIELD(0, 4), events);
-}
-DECLARE_IRQ(NPCX_IRQ_MFT_1, cec_isr, 4);
-
-static int cec_send(const uint8_t *msg, uint8_t len)
-{
-	int i;
-
-	if (cec_tx.len != 0)
-		return -1;
-
-	cec_tx.len = len;
-
-	CPRINTS("Send CEC:");
-	for (i = 0; i < len && i < MAX_CEC_MSG_LEN; i++)
-		CPRINTS(" 0x%02x", msg[i]);
-
-	memcpy(cec_tx.transfer.buf, msg, len);
-
-	/* Elevate to interrupt context */
-	tmr2_start(0);
-
-	return 0;
-}
-
-static enum ec_status hc_cec_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_write *params = args->params;
-
-	if (cec_state == CEC_STATE_DISABLED)
-		return EC_RES_UNAVAILABLE;
-
-	if (args->params_size == 0 || args->params_size > MAX_CEC_MSG_LEN)
-		return EC_RES_INVALID_PARAM;
-
-	if (cec_send(params->msg, args->params_size) != 0)
-		return EC_RES_BUSY;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_WRITE_MSG, hc_cec_write, EC_VER_MASK(0));
-
-static int cec_set_enable(uint8_t enable)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	if (enable != 0 && enable != 1)
-		return EC_RES_INVALID_PARAM;
-
-	/* Enabling when already enabled? */
-	if (enable && cec_state != CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	/* Disabling when already disabled? */
-	if (!enable && cec_state == CEC_STATE_DISABLED)
-		return EC_RES_SUCCESS;
-
-	if (enable) {
-		/* Configure GPIO40/TA1 as capture timer input (TA1) */
-		CLEAR_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-		SET_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-
-		enter_state(CEC_STATE_IDLE);
-
-		/*
-		 * Capture falling edge of first start
-		 * bit to get things going
-		 */
-		tmr_cap_start(CAP_EDGE_FALLING, 0);
-
-		/* Enable timer interrupts */
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		SET_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		/* Enable multifunction timer interrupt */
-		task_enable_irq(NPCX_IRQ_MFT_1);
-
-		CPRINTF("CEC enabled\n");
-	} else {
-		/* Disable timer interrupts */
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TAIEN);
-		CLEAR_BIT(NPCX_TIEN(mdl), NPCX_TIEN_TDIEN);
-
-		tmr2_stop();
-		tmr_cap_stop();
-
-		task_disable_irq(NPCX_IRQ_MFT_1);
-
-		/* Configure GPIO40/TA1 back to GPIO */
-		CLEAR_BIT(NPCX_DEVALT(3), NPCX_DEVALT3_TA1_SL1);
-		SET_BIT(NPCX_DEVALT(0xC), NPCX_DEVALTC_TA1_SL2);
-
-		enter_state(CEC_STATE_DISABLED);
-
-		CPRINTF("CEC disabled\n");
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static int cec_set_logical_addr(uint8_t logical_addr)
-{
-	if (logical_addr >= CEC_BROADCAST_ADDR &&
-	    logical_addr != CEC_UNREGISTERED_ADDR)
-		return EC_RES_INVALID_PARAM;
-
-	cec_addr = logical_addr;
-	CPRINTF("CEC address set to: %u\n", cec_addr);
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status hc_cec_set(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_cec_set *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		return cec_set_enable(params->val);
-	case CEC_CMD_LOGICAL_ADDRESS:
-		return cec_set_logical_addr(params->val);
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0));
-
-
-static enum ec_status hc_cec_get(struct host_cmd_handler_args *args)
-{
-	struct ec_response_cec_get *response = args->response;
-	const struct ec_params_cec_get *params = args->params;
-
-	switch (params->cmd) {
-	case CEC_CMD_ENABLE:
-		response->val = cec_state == CEC_STATE_DISABLED ? 0 : 1;
-		break;
-	case CEC_CMD_LOGICAL_ADDRESS:
-		response->val = cec_addr;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	args->response_size = sizeof(*response);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CEC_GET, hc_cec_get, EC_VER_MASK(0));
-
-static int cec_get_next_event(uint8_t *out)
-{
-	uint32_t event_out = atomic_clear(&cec_events);
-
-	memcpy(out, &event_out, sizeof(event_out));
-
-	return sizeof(event_out);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_EVENT, cec_get_next_event);
-
-static int cec_get_next_msg(uint8_t *out)
-{
-	int rv;
-	uint8_t msg_len, msg[MAX_CEC_MSG_LEN];
-
-	rv = cec_rx_queue_pop(&cec_rx_queue, msg, &msg_len);
-	if (rv != 0)
-		return EC_RES_UNAVAILABLE;
-
-	memcpy(out, msg, msg_len);
-
-	return msg_len;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg);
-
-
-static void cec_init(void)
-{
-	int mdl = NPCX_MFT_MODULE_1;
-
-	/* APB1 is the clock we base the timers on */
-	apb1_freq_div_10k = clock_get_apb1_freq()/10000;
-
-	/* Ensure Multi-Function timer is powered up. */
-	CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD);
-
-	/* Mode 2 - Dual-input capture */
-	SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, NPCX_MFT_MDSEL_2);
-
-	/* Enable capture TCNT1 into TCRA and preset TCNT1. */
-	SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
-
-	/* If RO doesn't set it, RW needs to set it explicitly. */
-	gpio_set_level(CEC_GPIO_PULL_UP, 1);
-
-	/* Ensure the CEC bus is not pulled low by default on startup. */
-	gpio_set_level(CEC_GPIO_OUT, 1);
-
-	CPRINTS("CEC initialized");
-}
-DECLARE_HOOK(HOOK_INIT, cec_init, HOOK_PRIO_LAST);
-
-void cec_task(void *unused)
-{
-	int rv;
-	uint32_t events;
-
-	CPRINTF("CEC task starting\n");
-
-	while (1) {
-		events = task_wait_event(-1);
-		if (events & TASK_EVENT_RECEIVED_DATA) {
-			rv = cec_rx_queue_push(&cec_rx_queue,
-					       cec_rx.transfer.buf,
-					       cec_rx.transfer.byte);
-			if (rv == EC_ERROR_OVERFLOW) {
-				/* Queue full, prefer the most recent msg */
-				cec_rx_queue_flush(&cec_rx_queue);
-				rv = cec_rx_queue_push(&cec_rx_queue,
-						       cec_rx.transfer.buf,
-						       cec_rx.transfer.byte);
-			}
-			if (rv == EC_SUCCESS)
-				mkbp_send_event(EC_MKBP_EVENT_CEC_MESSAGE);
-		}
-	}
-}
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
deleted file mode 100644
index ad611973be..0000000000
--- a/chip/npcx/clock.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "uartn.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define WAKE_INTERVAL   61        /* Unit: 61 usec */
-#define IDLE_PARAMS     0x7       /* Support deep idle, instant wake-up */
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-/*
- * Fixed amount of time to keep the console in use flag true after boot in
- * order to give a permanent window in which the low speed clock is not used.
- */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
-static int console_in_use_timeout_sec = 15;
-static timestamp_t console_expire_time;
-#endif
-
-/**
- * Enable clock to peripheral by setting the CGC register pertaining
- * to run, sleep, and/or deep sleep modes.
- *
- * @param offset  Offset of the peripheral. See enum clock_gate_offsets.
- * @param mask    Bit mask of the bits within CGC reg to set.
- * @param mode    no used
- */
-void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	/* Don't support for different mode */
-	uint8_t reg_mask = mask & 0xff;
-
-	/* Set PD bit to 0 */
-	NPCX_PWDWN_CTL(offset) &= ~reg_mask;
-	/* Wait for clock change to take affect. */
-	clock_wait_cycles(3);
-}
-
-/**
- * Disable clock to peripheral by setting the CGC register pertaining
- * to run, sleep, and/or deep sleep modes.
- *
- * @param offset  Offset of the peripheral. See enum clock_gate_offsets.
- * @param mask    Bit mask of the bits within CGC reg to clear.
- * @param mode    no used
- */
-void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
-{
-	/* Don't support for different mode */
-	uint8_t reg_mask = mask & 0xff;
-
-	/* Set PD bit to 1 */
-	NPCX_PWDWN_CTL(offset) |= reg_mask;
-
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set the CPU clocks and PLLs.
- */
-void clock_init(void)
-{
-#if defined(CONFIG_CLOCK_SRC_EXTERNAL) && defined(NPCX_EXT32K_OSC_SUPPORT)
-	/* Select external 32kHz crystal oscillator as LFCLK source. */
-	SET_BIT(NPCX_LFCGCTL2, NPCX_LFCGCTL2_XT_OSC_SL_EN);
-#endif
-
-	/*
-	 * Resting the OSC_CLK (even to the same value) will make the clock
-	 * unstable for a little which can affect peripheral communication like
-	 * eSPI. Skip this if not needed (e.g. RW jump)
-	 */
-	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML
-				|| NPCX_HFCGMH != HFCGMH) {
-		/*
-		 * Configure frequency multiplier M/N values according to
-		 * the requested OSC_CLK (Unit:Hz).
-		 */
-		NPCX_HFCGN  = HFCGN;
-		NPCX_HFCGML = HFCGML;
-		NPCX_HFCGMH = HFCGMH;
-
-		/* Load M and N values into the frequency multiplier */
-		SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
-		/* Wait for stable */
-		while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
-			;
-	}
-
-	/* Set all clock prescalers of core and peripherals. */
-#if defined(CHIP_FAMILY_NPCX5)
-	NPCX_HFCGP  = (FPRED << 4);
-	NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_HFCGP   = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD  = (FIUDIV << 4);
-	NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4));
-#else
-	NPCX_HFCBCD2 = APB3DIV;
-#endif
-#endif
-
-	/* Notify modules of frequency change */
-	hook_notify(HOOK_FREQ_CHANGE);
-
-	/* Configure alt. clock GPIOs (eg. optional 32KHz clock) */
-	gpio_config_module(MODULE_CLOCK, 1);
-}
-
-#if defined(CHIP_FAMILY_NPCX5)
-void clock_turbo(void)
-{
-	/* Configure Frequency multiplier values to 50MHz */
-	NPCX_HFCGN  = 0x02;
-	NPCX_HFCGML = 0xEC;
-	NPCX_HFCGMH = 0x0B;
-
-	/* Load M and N values into the frequency multiplier */
-	SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
-
-	/* Wait for stable */
-	while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
-		;
-
-	/* Keep Core CLK & FMCLK are the same if Core CLK exceed 33MHz */
-	NPCX_HFCGP = 0x00;
-
-	/*
-	 * Let APB2 equals Core CLK/2 if default APB2 clock is divisible
-	 * by 1MHz
-	 */
-	NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
-}
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-void clock_turbo(void)
-{
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	/* For NPCX9:
-	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
-	 * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but
-	 * can keep AHB6DIV to 0.
-	 */
-	NPCX_HFCGP = 0x00;
-#else
-	/* For NPCX7:
-	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
-	 * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
-	 */
-	NPCX_HFCGP = 0x01;
-#endif
-	NPCX_HFCBCD = BIT(4);
-}
-
-void clock_normal(void)
-{
-	/* Set CORE_CLK (CPU), AHB6_CLK and FIU_CLK back to original values. */
-	NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD = (FIUDIV << 4);
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	/* Assume we have a single task using MODULE_FAST_CPU */
-	if (module == MODULE_FAST_CPU) {
-		if (enable)
-			clock_turbo();
-		else
-			clock_normal();
-	}
-}
-
-#endif
-
-/**
- * Return the current clock frequency in Hz.
- */
-int clock_get_freq(void)
-{
-	return CORE_CLK;
-}
-
-/**
- * Return the current FMUL clock frequency in Hz.
- */
-int clock_get_fm_freq(void)
-{
-	return FMCLK;
-}
-
-/**
- * Return the current APB1 clock frequency in Hz.
- */
-int clock_get_apb1_freq(void)
-{
-	return NPCX_APB_CLOCK(1);
-}
-
-/**
- * Return the current APB2 clock frequency in Hz.
- */
-int clock_get_apb2_freq(void)
-{
-	return NPCX_APB_CLOCK(2);
-}
-
-/**
- * Return the current APB3 clock frequency in Hz.
- */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-int clock_get_apb3_freq(void)
-{
-	return NPCX_APB_CLOCK(3);
-}
-#endif
-
-/**
- * Wait for a number of clock cycles.
- *
- * Simple busy waiting for use before clocks/timers are initialized.
- *
- * @param cycles	Number of cycles to wait.
- */
-void clock_wait_cycles(uint32_t cycles)
-{
-	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void clock_refresh_console_in_use(void)
-{
-	/* Set console in use expire time. */
-	console_expire_time = get_time();
-	console_expire_time.val += console_in_use_timeout_sec * SECOND;
-	return;
-}
-
-#if defined(CHIP_FAMILY_NPCX5)
-void clock_uart2gpio(void)
-{
-	/* Is pimux to UART? */
-	if (npcx_is_uart()) {
-		/* Flush tx before enter deep idle */
-		uart_tx_flush();
-		/* Change pinmux to GPIO and disable UART IRQ */
-		task_disable_irq(NPCX_IRQ_UART);
-		/* Set to GPIO */
-		npcx_uart2gpio();
-		/* Clear pending wakeup */
-		uart_clear_pending_wakeup();
-		/* Enable MIWU for GPIO (UARTRX) */
-		uart_enable_wakeup(1);
-	}
-}
-
-void clock_gpio2uart(void)
-{
-	/* Is Pending bit of GPIO (UARTRX) */
-	if (uart_is_wakeup_from_gpio()) {
-		/* Refresh console in-use timer */
-		clock_refresh_console_in_use();
-		/* Disable MIWU for GPIO (UARTRX) */
-		uart_enable_wakeup(0);
-		/* Go back CR_SIN */
-		npcx_gpio2uart();
-		/* Enable uart again */
-		task_enable_irq(NPCX_IRQ_UART);
-	}
-}
-#endif
-
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	timestamp_t t0, t1;
-	uint32_t next_evt;
-	uint32_t next_evt_us;
-	uint16_t evt_count;
-
-	/*
-	 * Initialize console in use to true and specify the console expire
-	 * time in order to give a fixed window on boot in which the low speed
-	 * clock will not be used in idle.
-	 */
-	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
-
-	while (1) {
-		/*
-		 * Disable interrupts before going to deep sleep in order to
-		 * calculate the appropriate time to wake up. Note: the wfi
-		 * instruction waits until an interrupt is pending, so it
-		 * will still wake up even with interrupts disabled.
-		 */
-		interrupt_disable();
-
-		/* Compute event delay */
-		t0 = get_time();
-		next_evt = __hw_clock_event_get();
-
-		/* Do we have enough time before next event to deep sleep. */
-		if (DEEP_SLEEP_ALLOWED &&
-		    /*
-		     * Our HW timer doesn't tick in deep sleep - we do manual
-		     * adjustment based on sleep duration after wake. Avoid
-		     * the tricky overflow case by waiting out the period just
-		     * before overflow.
-		     */
-		    next_evt != EVT_MAX_EXPIRED_US &&
-		    /* Ensure event hasn't already expired */
-		    next_evt > t0.le.lo &&
-		    /* Ensure we have sufficient time before expiration */
-		    next_evt - t0.le.lo > WAKE_INTERVAL &&
-		    /* Make sure it's over console expired time */
-		    t0.val > console_expire_time.val) {
-#if DEBUG_CLK
-			/* Use GPIO to indicate SLEEP mode */
-			CLEAR_BIT(NPCX_PDOUT(0), 0);
-#endif
-			idle_dsleep_cnt++;
-
-			/* Enable Host access wakeup */
-			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-
-#if defined(CHIP_FAMILY_NPCX5)
-			/* UART-rx(console) become to GPIO (NONE INT mode) */
-			clock_uart2gpio();
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-			uartn_wui_en(CONFIG_CONSOLE_UART);
-#endif
-
-			/*
-			 * Disable input buffer of all 1.8v i2c ports before
-			 * entering deep sleep for better power consumption.
-			 */
-			gpio_enable_1p8v_i2c_wake_up_input(0);
-
-			/* Set deep idle - instant wake-up mode */
-			NPCX_PMCSR = IDLE_PARAMS;
-
-			/* Get current counter value of event timer */
-			evt_count = __hw_clock_event_count();
-
-			/*
-			 * TODO (ML): We found the same symptom of idle occurs
-			 * after wake-up from deep idle. Please see task.c for
-			 * more detail.
-			 * Workaround: Apply the same bypass of idle.
-			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
-
-			/* Get time delay cause of deep idle */
-			next_evt_us = __hw_clock_get_sleep_time(evt_count);
-
-			/*
-			 * Clear PMCSR manually in case there's wake-up between
-			 * setting it and wfi.
-			 */
-			NPCX_PMCSR = 0;
-#if defined(CHIP_FAMILY_NPCX5)
-			/* GPIO back to UART-rx (console) */
-			clock_gpio2uart();
-#endif
-
-			/* Enable input buffer of all 1.8v i2c ports. */
-			gpio_enable_1p8v_i2c_wake_up_input(1);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += next_evt_us;
-
-			/* Fast forward timer according to wake-up timer. */
-			t1.val = t0.val + next_evt_us;
-			/* Leave overflow situation for ITIM32 */
-			if (t1.le.hi == t0.le.hi)
-				force_time(t1);
-		} else {
-#if DEBUG_CLK
-			/* Use GPIO to indicate NORMAL mode */
-			SET_BIT(NPCX_PDOUT(0), 0);
-#endif
-			idle_sleep_cnt++;
-
-			/*
-			 * Using host access to make sure M4 core clock will
-			 * return when the eSPI accesses the Host modules if
-			 * CSAE bit is set. Please notice this symptom only
-			 * occurs at npcx5.
-			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
-			/* Enable Host access wakeup */
-			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-#endif
-			/*
-			 * Normal idle : wait for interrupt
-			 * TODO (ML): Workaround method for wfi issue.
-			 * Please see task.c for more detail
-			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
-		}
-
-		/*
-		 * Restore interrupt
-		 * RTOS will leave idle task to handle ISR which wakes up EC
-		 */
-		interrupt_enable();
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
-
-/**
- * Configure deep sleep clock settings.
- */
-static int command_dsleep(int argc, char **argv)
-{
-	int v;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &v)) {
-			/*
-			 * Force deep sleep not to use low speed clock or
-			 * allow it to use the low speed clock.
-			 */
-			if (v)
-				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else
-				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-		} else {
-			/* Set console in use timeout. */
-			char *e;
-			v = strtoi(argv[1], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM1;
-
-			console_in_use_timeout_sec = v;
-
-			/* Refresh console in use to use new timeout. */
-			clock_refresh_console_in_use();
-		}
-	}
-
-	ccprintf("Sleep mask: %08x\n", sleep_mask);
-	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
-	ccprintf("PMCSR register:      0x%02x\n", NPCX_PMCSR);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep not to use low speed clock.\nUse 'off' to "
-		"allow deep sleep to auto-select using the low speed "
-		"clock.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleepmask'.");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
deleted file mode 100644
index 702b55c52a..0000000000
--- a/chip/npcx/clock_chip.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific clock module for Chrome EC */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-/*
- * EC clock tree plan: (Default OSC_CLK is 40MHz.)
- *
- * Target OSC_CLK for NPCX7 is 90MHz, FMCLK is 45MHz, CPU and APBs is 15MHz.
- * Target OSC_CLK for NPCX5 is 30MHz, FMCLK is 30MHz, CPU and APBs is 15MHz.
- */
-#if defined(CHIP_FAMILY_NPCX5)
-/*
- * NPCX5 clock tree: (Please refer Figure 55. for more information.)
- *
- * Suggestion:
- * - OSC_CLK >= 30MHz, FPRED should be 1, else 0.
- *   (Keep FMCLK in 30-50 MHz possibly which is tested strictly.)
- */
-/* Target OSC_CLK freq */
-#define OSC_CLK 30000000
-/* Core clock prescaler */
-#if (OSC_CLK >= 30000000)
-#define FPRED 1 /* CORE_CLK = OSC_CLK(FMCLK)/2 */
-#else
-#define FPRED 0 /* CORE_CLK = OSC_CLK(FMCLK) */
-#endif
-/* Core domain clock */
-#define CORE_CLK (OSC_CLK / (FPRED + 1))
-/* FMUL clock */
-#define FMCLK OSC_CLK
-/* APBs source clock */
-#define APBSRC_CLK CORE_CLK
-/* APB1 clock divider */
-#define APB1DIV 3 /* Default APB1 clock = CORE_CLK/4 */
-/* APB2 clock divider */
-#define APB2DIV 0 /* Let APB2 = CORE_CLK since UART baudrate tolerance */
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-/*
- * NPCX7 clock tree: (Please refer Figure 58. for more information.)
- *
- * Suggestion:
- * - OSC_CLK >= 80MHz, XF_RANGE should be 1, else 0.
- * - CORE_CLK > 66MHz, AHB6DIV should be 1, else 0.
- * - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
- */
-/* Target OSC_CLK freq */
-#define OSC_CLK 90000000
-/* Core clock prescaler */
-#define FPRED 5 /* CORE_CLK = OSC_CLK/6 */
-/* Core domain clock */
-#define CORE_CLK (OSC_CLK / (FPRED + 1))
-/* FMUL clock */
-#if (OSC_CLK >= 80000000)
-#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK >= 80MHz */
-#else
-#define FMCLK OSC_CLK /* FMUL clock = OSC_CLK */
-#endif
-/* AHB6 clock */
-#if (CORE_CLK > 66000000)
-#define AHB6DIV 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 66MHz */
-#else
-#define AHB6DIV 0 /* AHB6_CLK = CORE_CLK */
-#endif
-/* FIU clock divider */
-#if (CORE_CLK > 50000000)
-#define FIUDIV 1 /* FIU_CLK = CORE_CLK/2 */
-#else
-#define FIUDIV 0 /* FIU_CLK = CORE_CLK */
-#endif
-/* APBs source clock */
-#define APBSRC_CLK OSC_CLK
-/* APB1 clock divider */
-#define APB1DIV 5 /* APB1 clock = OSC_CLK/6 */
-/* APB2 clock divider */
-#define APB2DIV 5 /* APB2 clock = OSC_CLK/6 */
-/* APB3 clock divider */
-#define APB3DIV 5 /* APB3 clock = OSC_CLK/6 */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-/* APB4 clock divider */
-#define APB4DIV 5 /* APB4 clock = OSC_CLK/6 */
-#endif
-#endif
-
-/* Get APB clock freq */
-#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV + 1))
-
-/*
- * Frequency multiplier M/N value definitions according to the requested
- * OSC_CLK (Unit:Hz).
- */
-#if (OSC_CLK > 80000000)
-#define HFCGN    0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
-#else
-#define HFCGN    0x02
-#endif
-#if   (OSC_CLK == 100000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
-#elif (OSC_CLK == 90000000)
-#define HFCGMH   0x0A
-#define HFCGML   0xBA
-#elif (OSC_CLK == 80000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
-#elif (OSC_CLK == 66000000)
-#define HFCGMH   0x0F
-#define HFCGML   0xBC
-#elif (OSC_CLK == 50000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
-#elif (OSC_CLK == 48000000)
-#define HFCGMH   0x0B
-#define HFCGML   0x72
-#elif (OSC_CLK == 40000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
-#elif (OSC_CLK == 33000000)
-#define HFCGMH   0x07
-#define HFCGML   0xDE
-#elif (OSC_CLK == 30000000)
-#define HFCGMH   0x07
-#define HFCGML   0x27
-#elif (OSC_CLK == 26000000)
-#define HFCGMH   0x06
-#define HFCGML   0x33
-#else
-#error "Unsupported OSC_CLK Frequency"
-#endif
-
-#if defined(CHIP_FAMILY_NPCX5)
-#if (OSC_CLK > 50000000)
-#error "Unsupported OSC_CLK on NPCX5 series!"
-#endif
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-#if (OSC_CLK > 100000000)
-#error "Unsupported OSC_CLK on NPCX series!"
-#endif
-#endif
-
-/**
- * Return the current FMUL clock frequency in Hz.
- */
-int clock_get_fm_freq(void);
-
-/**
- * Return the current APB1 clock frequency in Hz.
- */
-int clock_get_apb1_freq(void);
-
-/**
- * Return the current APB2 clock frequency in Hz.
- */
-int clock_get_apb2_freq(void);
-
-/**
- * Return the current APB3 clock frequency in Hz.
- */
-int clock_get_apb3_freq(void);
-
-/**
- * Set the CPU clock to maximum freq for better performance.
- */
-void clock_turbo(void);
-
-/**
- * Set the CPU clock back to normal freq.
- */
-void clock_turbo_disable(void);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h
deleted file mode 100644
index 434caba1d8..0000000000
--- a/chip/npcx/config_chip-npcx5.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H
-#define __CROS_EC_CONFIG_CHIP_NPCX5_H
-
-/*
- * NPCX5 Series Device-Specific Information
- * Ex. NPCX5(M)(N)(G)
- * @param M: 7: 132-pins package, 8: 128-pins package
- * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size
- * @param G: Google EC.
- */
-
-/* Chip ID for all variants */
-#define NPCX585G_CHIP_ID		0x12
-#define NPCX575G_CHIP_ID		0x13
-#define NPCX586G_CHIP_ID		0x16
-#define NPCX576G_CHIP_ID		0x17
-
-/*****************************************************************************/
-/* Hardware features */
-
-/* Number of UART modules. */
-#define UART_MODULE_COUNT 1
-
-/*
- * For NPCX5, PS2_3 pins also support other alternate functions (e.g., TA2).
- * PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_3
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT	4
-/* Number of I2C ports */
-#define I2C_PORT_COUNT		5
-
-/*****************************************************************************/
-/* Memory mapping */
-#define NPCX_BTRAM_SIZE		0x800 /* 2KB data ram used by booter. */
-#define CONFIG_RAM_BASE		0x200C0000 /* memory address of data ram */
-#define CONFIG_DATA_RAM_SIZE	0x00008000 /* Size of data RAM */
-#define CONFIG_RAM_SIZE		(CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-#define CONFIG_LPRAM_BASE	0x40001600 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-
-/* Use chip variant to specify the size and start address of program memory */
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 96KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024)
-/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 224KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024)
-/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000
-#else
-#error "Unsupported chip variant"
-#endif
-
-/* Total RAM size checking for npcx ec */
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 128KB RAM in NPCX5M5G */
-#if (NPCX_RAM_SIZE != 0x20000)
-#error "Wrong memory mapping layout for NPCX5M5G"
-#endif
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 256KB RAM in NPCX5M6G */
-#if (NPCX_RAM_SIZE != 0x40000)
-#error "Wrong memory mapping layout for NPCX5M6G"
-#endif
-#endif
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
deleted file mode 100644
index 434c3a7889..0000000000
--- a/chip/npcx/config_chip-npcx7.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX7_H
-#define __CROS_EC_CONFIG_CHIP_NPCX7_H
-
-/*
- * NPCX7 Series Device-Specific Information
- * Ex. NPCX7(M)(N)(G/K/F)(B/C)
- * @param M: 8: 128-pins package, 9: 144-pins package
- * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
- * @param G/K/F/W: Google EC depends on specific features.
- * @param B/C: (Optional) Chip generation in the same series.
- */
-
-/* Chip ID for all variants */
-#define NPCX787G_CHIP_ID		0x1F
-#define NPCX796F_A_B_CHIP_ID		0x21
-#define NPCX796F_C_CHIP_ID		0x29
-#define NPCX797F_C_CHIP_ID		0x20
-#define NPCX797W_B_CHIP_ID		0x24
-#define NPCX797W_C_CHIP_ID		0x2C
-
-/*****************************************************************************/
-/* Hardware features */
-
-/* The optional hardware features depend on chip variant */
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
-#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
-#endif
-
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_UART_FIFO_SUPPORT
-/* Number of UART modules. */
-#define NPCX_SECOND_UART
-#define UART_MODULE_COUNT 2
-
-/*
- * For NPCX7, PS2_2 & PS2_3 pins also support other alternate functions
- * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_2
-#undef NPCX_PS2_MODULE_3
-
-/* 64-bit timer support */
-#define NPCX_ITIM64_SUPPORT
-#else
-#define UART_MODULE_COUNT 1
-#endif
-
-#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */
-#endif
-
-/*
- * Number of I2C controllers. Controller 4/5/6 has 2 ports, so the chip has
- * three additional ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT 8
-/* Number of I2C ports */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define I2C_PORT_COUNT 10
-#else
-#define I2C_PORT_COUNT 11
-#endif
-
-#define NPCX_I2C_FIFO_SUPPORT
-
-/* Use SHI module version 2 supported by npcx7 family */
-#define NPCX_SHI_V2
-
-/*****************************************************************************/
-/* Memory mapping */
-#define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
-
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* 62 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-	/* 256KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-#elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-	/*
-	 * Code RAM is normally assumed to be same as image size, but since
-	 * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
-	 * need to explicitly configure it. This is the actual size of code
-	 * RAM on-chip.
-	 */
-#	define CONFIG_CODE_RAM_SIZE (256 * 1024)
-	/*
-	 * In npcx797wc and npcx797fc, the code RAM size is limited by the
-	 * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
-	 * re-organize the memory to:
-	 * 1. the overall memory (RAM) layout is re-organized against the
-	 * datasheet:
-	 *     In datasheet: 320 KB code RAM + 64 KB data RAM
-	 *     After re-organization: 256 KB code RAM + 128 KB data RAM.
-	 * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
-	 * -WB). After the boot header is added, a 256K image would be
-	 * too large to fit in either RO or RW sections of Flash (each
-	 * of which is half of it). Because other code assumes that
-	 * image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-
-	/*
-	 * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
-	 * is not the actual size of code RAM.
-	 */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
-#else
-#	error "Unsupported chip variant"
-#endif
-
-#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-/* no low power ram in npcx7 series */
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
deleted file mode 100644
index 0248c40f86..0000000000
--- a/chip/npcx/config_chip-npcx9.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX9_H
-#define __CROS_EC_CONFIG_CHIP_NPCX9_H
-
-/*
- * NPCX9 Series Device-Specific Information
- * Ex. NPCX9(M)(N)(G/K/F)(B/C)
- * @param M: 9: 144-pins package
- * @param N: 3: 320KB RAM Size, 6: 256KB RAM Size.
- * @param F: Google EC.
- * @param B/C: (Optional) Chip generation in the same series.
- */
-
-/* Chip ID for all variants */
-#define NPCX996F_CHIP_ID		0x21
-#define NPCX993F_CHIP_ID		0x25
-
-/*****************************************************************************/
-/* Hardware features */
-
-#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
-#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_LCT_SUPPORT /* Long Countdown Timer support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
-
-#define NPCX_UART_FIFO_SUPPORT
-/* Number of UART modules. */
-#define NPCX_SECOND_UART
-#define UART_MODULE_COUNT 2
-
-/*
- * For NPCX9, PS2_2 & PS2_3 pins also support other alternate functions
- * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_2
-#undef NPCX_PS2_MODULE_3
-
-/*
- * Number of I2C controllers. Controller 5/6 has 2 ports, so the chip has
- * two additional ports.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT 8
-#define I2C_PORT_COUNT 10
-
-#define NPCX_I2C_FIFO_SUPPORT
-
-/* Use SHI module version 2 supported by npcx7 and latter family */
-#define NPCX_SHI_V2
-
-/* PSL_OUT optional configuration */
-/* Set PSL_OUT mode to pulse mode */
-#define NPCX_PSL_CFG_PSL_OUT_PULSE	BIT(0)
-/* set PSL_OUT to open-drain */
-#define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
-#define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
-
-
-#define CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-/*****************************************************************************/
-/* Memory mapping */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-#endif
-
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-
-#if defined(CHIP_VARIANT_NPCX9M3F)
-	/*
-	 * 256KB program RAM, but only 512K of Flash. After the boot header is
-	 * added, a 256K image would be too large to fit in either RO or RW
-	 * sections of Flash (each of which is half of it). Because other code
-	 * assumes that image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
-	/* program memory base address for Code RAM (0x100C0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-
-	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
-			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
-#elif defined(CHIP_VARIANT_NPCX9M6F)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-#else
-#	error "Unsupported chip variant"
-#endif
-
-/* Internal spi-flash setting */
-#define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
-#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
-
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
deleted file mode 100644
index cee339206c..0000000000
--- a/chip/npcx/config_chip.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-
-/*
- * Set the chip family version to 4 digits to keep the flexibility in case
- * we need the minor version for chip variants in a family.
- */
-#define NPCX_FAMILY_NPCX5        5000
-#define NPCX_FAMILY_NPCX7        7000
-#define NPCX_FAMILY_NPCX9        9000
-
-/* Features depend on chip family */
-#if defined(CHIP_FAMILY_NPCX5)
-#include "config_chip-npcx5.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX5
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "config_chip-npcx7.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX7
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "config_chip-npcx9.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX9
-#else
-#error "Unsupported chip family"
-#endif
-
-/* 32k hz internal oscillator frequency (FRCLK) */
-#define INT_32K_CLOCK 32768
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 64
-
-/* Use a bigger console output buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-/*
- * Interval between HOOK_TICK notifications
- * Notice instant wake-up from deep-idle cannot exceed 200 ms
- */
-#define HOOK_TICK_INTERVAL_MS 200
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE       1024
-
-/* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
-
-#define CHARGER_TASK_STACK_SIZE		800
-#define HOOKS_TASK_STACK_SIZE		800
-#define CONSOLE_TASK_STACK_SIZE		800
-
-/* Default task stack size */
-#define TASK_STACK_SIZE			672
-
-/* Address of RAM log used by Booter */
-#define ADDR_BOOT_RAMLOG        0x100C7FC0
-
-#include "config_flash_layout.h"
-
-/* Optional features present on this chip */
-#define CONFIG_ADC
-#define CONFIG_RTC
-#define CONFIG_SWITCH
-#define CONFIG_MPU
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-/* Default use UART1 as console */
-#define CONFIG_CONSOLE_UART    0
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
deleted file mode 100644
index 79961548c9..0000000000
--- a/chip/npcx/config_flash_layout.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
-#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
-
-/*
- * npcx flash layout:
- * - Memory-mapped external SPI.
- * - Image header at the beginning of protected region, followed by RO image.
- * - RW image starts at the second half of flash.
- */
-
-/* Memmapped, external SPI */
-#define CONFIG_EXTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-/* Storage is memory-mapped, but program runs from SRAM */
-#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#undef  CONFIG_FLASH_PSTATE
-
-#if defined(CHIP_VARIANT_NPCX5M5G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x80000
-#elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#else
-#error "Unsupported chip variant"
-#endif
-
-/* Header support which is used by booter to copy FW from flash to code ram */
-#define NPCX_RO_HEADER
-#define CONFIG_RO_HDR_MEM_OFF	0x0
-#define CONFIG_RO_HDR_SIZE	0x40
-
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* RO firmware in program memory - use all of program memory */
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		NPCX_PROGRAM_MEMORY_SIZE
-
-/*
- * ROM resident area in flash used to store data objects that are not copied
- * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
- */
-#define CONFIG_RO_ROM_RESIDENT_MEM_OFF	CONFIG_RO_SIZE
-#define CONFIG_RO_ROM_RESIDENT_SIZE \
-	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
-
-/*
- * RW firmware in program memory - Identical to RO, only one image loaded at
- * a time.
- */
-#define CONFIG_RW_MEM_OFF	CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE		CONFIG_RO_SIZE
-
-#define CONFIG_RW_ROM_RESIDENT_MEM_OFF	CONFIG_RW_SIZE
-#define CONFIG_RW_ROM_RESIDENT_SIZE \
-	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
-
-#if (CONFIG_RO_SIZE != CONFIG_RW_SIZE)
-#error "Unsupported.. FLASH_ERASE_SIZE assumes RO and RW size is same!"
-#endif
-
-#if (CONFIG_RO_MEM_OFF != 0)
-#error "Unsupported.. CONFIG_RO_MEM_OFF is assumed to be 0!"
-#endif
-
-/*
- * The common flash support requires that the CONFIG_WP_STORAGE_SIZE and
- * CONFIG_EC_WRITABLE_STORAGE_SIZE are both a multiple of
- * CONFIG_FLASH_ERASE_SIZE.
- *
- * THE NPCX supports erase sizes of 64 KiB, 32 KiB, and 4 KiB. The NPCX flash
- * driver does not currently support CONFIG_FLASH_MULTIPLE_REGION, so set
- * the erase size to the maximum (64 KiB) for the best performance.
- * Using smaller erase sizes increases boot time. If write protected and
- * writable flash regions are not a multiple of 64 KiB, then support
- * for CONFIG_FLASH_MULTIPLE_REGION must be added.
- */
-#define CONFIG_FLASH_ERASE_SIZE		0x10000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_64K_ERASE
-
-#if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE)
-#error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \
-	"CONFIG_EC_WRITABLE_STORAGE_SIZE are the same."
-#endif
-
-/*
- * If the total flash size is not a multiple of 64k, this slows the boot
- * time. CONFIG_FLASH_MULTIPLE_REGION should be enabled in this case to
- * optimize the erase block handling.
- */
-#if ((CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE) != 0)
-#error "CONFIG_WP_STORAGE_SIZE is not a multiple of 64K. Correct the flash " \
-	"size or add support for CONFIG_FLASH_MULTIPLE_REGION."
-#endif
-
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-
-/* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
-
-/* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
-/* RW image resides at start of writable region */
-#define CONFIG_RW_STORAGE_OFF	0
-
-#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
deleted file mode 100644
index c8976afed0..0000000000
--- a/chip/npcx/espi.c
+++ /dev/null
@@ -1,704 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ESPI module for Chrome EC */
-
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "chipset.h"
-#include "console.h"
-#include "uart.h"
-#include "util.h"
-#include "power.h"
-#include "espi.h"
-#include "lpc_chip.h"
-#include "hooks.h"
-#include "timer.h"
-
-/* Console output macros */
-#if !(DEBUG_ESPI)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-
-/* Default eSPI configuration for VW events */
-struct vwevms_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t espirst_en; /* Enable reset by eSPI_RST assert */
-	uint8_t int_en;     /* Interrupt/Wake-up enable */
-};
-
-struct vwevsm_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t cdrst_en;   /* Enable cold reset */
-	uint8_t valid;      /* Valid VW mask */
-};
-
-/* Default MIWU configurations for VW events */
-struct host_wui_item {
-	uint16_t table : 2; /* MIWU table 0-2 */
-	uint16_t group : 3; /* MIWU group 0-7 */
-	uint16_t num   : 3; /* MIWU bit   0-7 */
-	uint16_t edge  : 4; /* MIWU edge trigger type rising/falling/any */
-};
-
-/* Mapping item between VW signal, index and value */
-struct vw_event_t {
-	uint16_t name;     /* Name of signal */
-	uint8_t  evt_idx;  /* VW index of signal */
-	uint8_t  evt_val;  /* VW value of signal */
-};
-
-/* Default settings of VWEVMS registers (Please refer Table.43/44) */
-static const struct vwevms_config_t espi_in_list[] = {
-	/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
-#ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-	{0x02,  1,  0,  1,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
-#else
-	{0x02,  1,  0,  0,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
-#endif
-	{0x03,  1,  0,  1,  1},  /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
-	{0x07,  1,  1,  1,  1},  /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
-	{0x41,  1,  0,  1,  1},  /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
-	{0x42,  1,  0,  0,  1},  /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
-	{0x47,  1,  1,  1,  1},  /* HOST_C10,  Reserve,    Reserve,   Reserve */
-};
-
-/* Default settings of VWEVSM registers (Please refer Table.43/44) */
-static const struct vwevsm_config_t espi_out_list[] = {
-	/* IDX EN ENPL ENCDR VDMASK         VW Event Bit 0 - 3 (S->M)         */
-	{0x04,  1,  0,  0, 0x0D}, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
-	{0x05,  1,  0,  0, 0x0F}, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
-#ifdef CONFIG_SCI_GPIO
-	{0x06,  1,  1,  0, 0x0C}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
-#else
-	{0x06,  1,  1,  0, 0x0F}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
-#endif
-	{0x40,  1,  0,  0, 0x01}, /* SUS_ACK,    Reserve, Reserve, Reserve    */
-};
-
-/* eSPI interrupts used in MIWU */
-static const struct host_wui_item espi_vw_int_list[] = {
-	/* ESPI_RESET  */
-	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING},
-	/* SLP_S3 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING},
-	/* SLP_S4 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING},
-	/* SLP_S5 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING},
-	/* VW_WIRE_PLTRST */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING},
-	/* VW_WIRE_OOB_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING},
-	/* VW_WIRE_HOST_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING},
-	/* VW_WIRE_SUS_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING},
-};
-
-/* VW signals used in eSPI */
-static const struct vw_event_t vw_events_list[] = {
-	{VW_SLP_S3_L,                    0x02,   0x01},	/* index 02h (In)  */
-	{VW_SLP_S4_L,                    0x02,   0x02},
-	{VW_SLP_S5_L,                    0x02,   0x04},
-	{VW_SUS_STAT_L,                  0x03,   0x01},	/* index 03h (In)  */
-	{VW_PLTRST_L,                    0x03,   0x02},
-	{VW_OOB_RST_WARN,                0x03,   0x04},
-	{VW_OOB_RST_ACK,                 0x04,   0x01},	/* index 04h (Out) */
-	{VW_WAKE_L,                      0x04,   0x04},
-	{VW_PME_L,                       0x04,   0x08},
-	{VW_ERROR_FATAL,                 0x05,   0x02},	/* index 05h (Out) */
-	{VW_ERROR_NON_FATAL,             0x05,   0x04},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05,   0x09},
-	{VW_SCI_L,                       0x06,   0x01},	/* index 06h (Out) */
-	{VW_SMI_L,                       0x06,   0x02},
-	{VW_RCIN_L,                      0x06,   0x04},
-	{VW_HOST_RST_ACK,                0x06,   0x08},
-	{VW_HOST_RST_WARN,               0x07,   0x01},	/* index 07h (In)  */
-	{VW_SUS_ACK,                     0x40,   0x01},	/* index 40h (Out) */
-	{VW_SUS_WARN_L,                  0x41,   0x01},	/* index 41h (In)  */
-	{VW_SUS_PWRDN_ACK_L,             0x41,   0x02},
-	{VW_SLP_A_L,                     0x41,   0x08},
-	{VW_SLP_LAN,                     0x42,   0x01},	/* index 42h (In)  */
-	{VW_SLP_WLAN,                    0x42,   0x02},
-};
-
-/* Flag for boot load signals */
-static uint8_t boot_load_done;
-
-/*****************************************************************************/
-/* eSPI internal utilities */
-
-/* Recovery utility for eSPI reset */
-static void espi_reset_recovery(void)
-{
-	/* TODO: Put recovery stuff related to eSPI reset here */
-
-	/* Clear boot load flag */
-	boot_load_done = 0;
-}
-
-/* Configure Controller-to-Peripheral virtual wire inputs */
-static void espi_vw_config_in(const struct vwevms_config_t *config)
-{
-	uint32_t val;
-	uint8_t  i, index;
-
-	switch (VM_TYPE(config->idx)) {
-	case ESPI_VW_TYPE_SYS_EV:
-	case ESPI_VW_TYPE_PLT:
-		for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
-			index = VWEVMS_IDX_GET(NPCX_VWEVMS(i));
-			/* Set VW input register */
-			if (index == config->idx) {
-				/* Get Wire field */
-				val = NPCX_VWEVMS(i) & 0x0F;
-				val |= VWEVMS_FIELD(config->idx,
-						config->idx_en,
-						config->pltrst_en,
-						config->int_en,
-						config->espirst_en);
-				NPCX_VWEVMS(i) = val;
-				return;
-			}
-		}
-		CPRINTS("No match index of all VWEVMSs");
-		break;
-	default:
-		CPRINTS("No support type of VWEVMS");
-		break;
-	}
-}
-
-/* Configure Peripheral-to-Controller virtual wire outputs */
-static void espi_vw_config_out(const struct vwevsm_config_t *config)
-{
-	uint32_t val;
-	uint8_t i, index;
-
-	switch (VM_TYPE(config->idx)) {
-	case ESPI_VW_TYPE_SYS_EV:
-	case ESPI_VW_TYPE_PLT:
-		for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
-			index = VWEVSM_IDX_GET(NPCX_VWEVSM(i));
-			/* Set VW output register */
-			if (index == config->idx) {
-				/* Preserve WIRE(3-0) and HW_WIRE (27-24). */
-				val = NPCX_VWEVSM(i) & 0x0F00000F;
-				val |= VWEVSM_FIELD(config->idx,
-						config->idx_en,
-						config->valid,
-						config->pltrst_en,
-						config->cdrst_en);
-				NPCX_VWEVSM(i) = val;
-				return;
-			}
-		}
-		CPRINTS("No match index of all VWEVSMs");
-		break;
-	default:
-		CPRINTS("No support type of VWEVSM");
-		break;
-	}
-}
-
-/* Config Controller-to-Peripheral VWire interrupt edge type and enable it */
-static void espi_enable_vw_int(const struct host_wui_item *vwire_int)
-{
-	uint8_t table = vwire_int->table;
-	uint8_t group = vwire_int->group;
-	uint8_t num   = vwire_int->num;
-	uint8_t edge  = vwire_int->edge;
-
-	/* Set detection mode to edge */
-	CLEAR_BIT(NPCX_WKMOD(table, group), num);
-
-	if (edge != MIWU_EDGE_ANYING) {
-		/* Disable Any Edge */
-		CLEAR_BIT(NPCX_WKAEDG(table, group), num);
-		/* Enable Rising Edge */
-		if (edge == MIWU_EDGE_RISING)
-			CLEAR_BIT(NPCX_WKEDG(table, group), num);
-		/* Enable Falling Edge */
-		else
-			SET_BIT(NPCX_WKEDG(table, group), num);
-	} else
-		/* enable Any Edge */
-		SET_BIT(NPCX_WKAEDG(table, group), num);
-
-	/* Clear the pending bit */
-	NPCX_WKPCL(table, group) = BIT(num);
-
-	/* Enable wake-up input sources */
-	SET_BIT(NPCX_WKEN(table, group), num);
-}
-
-/* Get vw index & value information by signal */
-static int espi_vw_get_signal_index(enum espi_vw_signal event)
-{
-	int index;
-
-	/* Find the vw index by signal name first */
-	for (index = 0; index < ARRAY_SIZE(vw_events_list); index++) {
-		if (vw_events_list[index].name == event)
-			break;
-	}
-	/* Cannot find the index */
-	if (index == ARRAY_SIZE(vw_events_list))
-		return -1;
-
-	return index;
-}
-
-/* The ISRs of VW signals which used for power sequences */
-void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL))
-		/* TODO: Add VW handler in power/common.c */
-		power_signal_interrupt((enum gpio_signal) signal);
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	uint8_t offset, value;
-	int sig_idx;
-
-	/* Get index of vw signal list by signale name */
-	sig_idx = espi_vw_get_signal_index(signal);
-
-	/* Cannot find index by signal name */
-	if (sig_idx < 0)
-		return EC_ERROR_PARAM1;
-
-	/* Find the output register offset by vw index */
-	for (offset = 0; offset < ESPI_VWEVSM_NUM; offset++) {
-		uint8_t vw_idx = VWEVSM_IDX_GET(NPCX_VWEVSM(offset));
-		/* If index matches. break */
-		if (vw_idx == vw_events_list[sig_idx].evt_idx)
-			break;
-	}
-
-	/* Cannot match index */
-	if (offset == ESPI_VWEVSM_NUM)
-		return EC_ERROR_PARAM1;
-
-	value = GET_FIELD(NPCX_VWEVSM(offset), NPCX_VWEVSM_WIRE);
-	/* Set wire */
-	if (level)
-		value |= vw_events_list[sig_idx].evt_val;
-	else /* Clear wire */
-		value &= (~vw_events_list[sig_idx].evt_val);
-
-	SET_FIELD(NPCX_VWEVSM(offset), NPCX_VWEVSM_WIRE, value);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	uint8_t offset, value;
-	int sig_idx;
-
-	/* Get index of vw signal list by signale name */
-	sig_idx = espi_vw_get_signal_index(signal);
-
-	/* Cannot find index by signal name */
-	if (sig_idx < 0)
-		return -1;
-
-	/* Find the input register offset by vw index */
-	for (offset = 0; offset < ESPI_VWEVMS_NUM; offset++) {
-		uint8_t vw_idx = VWEVMS_IDX_GET(NPCX_VWEVMS(offset));
-		/* If index matches. break */
-		if (vw_idx == vw_events_list[sig_idx].evt_idx)
-			break;
-	}
-
-	/* Cannot match index */
-	if (offset == ESPI_VWEVMS_NUM)
-		return -1;
-
-	/* Get wire & check with valid bits */
-	value = GET_FIELD(NPCX_VWEVMS(offset), NPCX_VWEVMS_WIRE);
-	value &= GET_FIELD(NPCX_VWEVMS(offset), NPCX_VWEVMS_VALID);
-
-	return !!(value & vw_events_list[sig_idx].evt_val);
-}
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	if (signal == VW_SLP_S3_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 0);
-	else if (signal == VW_SLP_S4_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 1);
-	else if (signal == VW_SLP_S5_L)
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 2);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	if (signal == VW_SLP_S3_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 0);
-	else if (signal == VW_SLP_S4_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 1);
-	else if (signal == VW_SLP_S5_L)
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_1), 2);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* VW event handlers */
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-#endif
-
-/* PLTRST# event handler */
-void espi_vw_evt_pltrst(void)
-{
-	int pltrst = espi_vw_get_wire(VW_PLTRST_L);
-
-	CPRINTS("VW PLTRST: %d", pltrst);
-
-	if (pltrst) {
-		/* PLTRST# deasserted */
-#if defined(CHIP_FAMILY_NPCX5)
-		/* See errata 2.22 */
-
-		/* Disable eSPI peripheral channel support first */
-		CLEAR_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
-
-		/* Initialize host settings */
-		host_register_init();
-
-		/* Enable eSPI peripheral channel */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
-
-		/* Re-enable eSPI peripheral channel support */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCCHN_SUPP);
-#else
-		/* Initialize host settings */
-		host_register_init();
-
-		/* Enable eSPI peripheral channel */
-		SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN);
-#endif
-	} else {
-		/* PLTRST# asserted */
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		hook_call_deferred(&espi_chipset_reset_data, MSEC);
-#endif
-	}
-}
-
-/* SLP_Sx event handler */
-void espi_vw_evt_slp_s3(void)
-{
-	CPRINTS("VW SLP_S3: %d", espi_vw_get_wire(VW_SLP_S3_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S3_L);
-}
-
-void espi_vw_evt_slp_s4(void)
-{
-	CPRINTS("VW SLP_S4: %d", espi_vw_get_wire(VW_SLP_S4_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S4_L);
-}
-
-void espi_vw_evt_slp_s5(void)
-{
-	CPRINTS("VW SLP_S5: %d", espi_vw_get_wire(VW_SLP_S5_L));
-	espi_vw_power_signal_interrupt(VW_SLP_S5_L);
-}
-
-/* OOB Reset event handler */
-void espi_vw_evt_oobrst(void)
-{
-	CPRINTS("VW OOB_RST: %d", espi_vw_get_wire(VW_OOB_RST_WARN));
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_OOB_RST_ACK, espi_vw_get_wire(VW_OOB_RST_WARN));
-}
-
-/* SUS_WARN# event handler */
-void espi_vw_evt_sus_warn(void)
-{
-	CPRINTS("VW SUS_WARN#: %d", espi_vw_get_wire(VW_SUS_WARN_L));
-
-	udelay(100);
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_SUS_ACK, espi_vw_get_wire(VW_SUS_WARN_L));
-}
-
-/* HOSTRST WARN event handler */
-void espi_vw_evt_hostrst_warn(void)
-{
-	CPRINTS("VW HOST_RST_WARN#: %d", espi_vw_get_wire(VW_HOST_RST_WARN));
-
-	/* Send ACK to host by WARN#'s wire */
-	espi_vw_set_wire(VW_HOST_RST_ACK, espi_vw_get_wire(VW_HOST_RST_WARN));
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/* eSPI reset assert/de-assert interrupt */
-void espi_espirst_handler(void)
-{
-	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 5);
-
-	CPRINTS("eSPI RST issued!");
-}
-
-/* Handle eSPI virtual wire interrupt 1 */
-void __espi_wk2a_interrupt(void)
-{
-	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_1);
-
-	/* Clear pending bits of MIWU */
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_1) = pending_bits;
-
-	/* Handle events of virtual-wire */
-	if (IS_BIT_SET(pending_bits, 0))
-		espi_vw_evt_slp_s3();
-	if (IS_BIT_SET(pending_bits, 1))
-		espi_vw_evt_slp_s4();
-	if (IS_BIT_SET(pending_bits, 2))
-		espi_vw_evt_slp_s5();
-	if (IS_BIT_SET(pending_bits, 5))
-		espi_vw_evt_pltrst();
-	if (IS_BIT_SET(pending_bits, 6))
-		espi_vw_evt_oobrst();
-}
-DECLARE_IRQ(NPCX_IRQ_WKINTA_2, __espi_wk2a_interrupt, 3);
-
-/* Handle eSPI virtual wire interrupt 2 */
-void __espi_wk2b_interrupt(void)
-{
-	uint8_t pending_bits = NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_2);
-
-	/* Clear pending bits of MIWU */
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_2) = pending_bits;
-
-	/* Handle events of virtual-wire */
-	if (IS_BIT_SET(pending_bits, 4))
-		espi_vw_evt_sus_warn();
-	if (IS_BIT_SET(pending_bits, 0))
-		espi_vw_evt_hostrst_warn();
-}
-DECLARE_IRQ(NPCX_IRQ_WKINTB_2, __espi_wk2b_interrupt, 3);
-
-/* Interrupt handler for eSPI status changed */
-void espi_interrupt(void)
-{
-	int chan;
-	uint32_t mask, status;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/*
-	 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
-	 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
-	 */
-	mask = NPCX_ESPIIE | BIT(NPCX_ESPISTS_VWUPDW);
-#else
-	mask = NPCX_ESPIIE;
-#endif
-	status = NPCX_ESPISTS & mask;
-
-	while (status) {
-		/* Clear pending bits first */
-		NPCX_ESPISTS = status;
-
-		if (IS_BIT_SET(status, NPCX_ESPISTS_BERR))
-			/* Always print eSPI Bus Errors */
-			cprints(CC_LPC, "eSPI Bus Error");
-
-		/* eSPI inband reset(from VW) */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_IBRST)) {
-			CPRINTS("eSPI RST inband RST");
-			espi_reset_recovery();
-
-		} /* eSPI reset (from eSPI_rst pin) */
-		else if (IS_BIT_SET(status, NPCX_ESPISTS_ESPIRST)) {
-			CPRINTS("eSPI RST");
-			chipset_handle_espi_reset_assert();
-			espi_reset_recovery();
-		}
-
-		/* eSPI configuration is updated */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_CFGUPD)) {
-			/*
-			 * If host enable/disable channel for VW/OOB/FLASH, EC
-			 * should follow except Peripheral channel. It is
-			 * handled by PLTRST separately.
-			 */
-			for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT;
-					chan++) {
-				if (!IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						IS_HOST_CHAN_EN(chan))
-					ENABLE_ESPI_CHAN(chan);
-				else if (IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						!IS_HOST_CHAN_EN(chan))
-					DISABLE_ESPI_CHAN(chan);
-			}
-
-			/*
-			 * Send BOOTLOAD_DONE and BOOTLOAD_STATUS
-			 * events to host simultaneously. To indicate the
-			 * completion of EC firmware code loading.
-			 */
-			if (boot_load_done == 0 &&
-			    IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) {
-
-				espi_vw_set_wire(
-					VW_PERIPHERAL_BTLD_STATUS_DONE, 1);
-				boot_load_done = 1;
-			}
-		}
-
-		/* Any VW signal sent by Host - leave it, handle in MIWU ISR */
-		if (IS_BIT_SET(status, NPCX_ESPISTS_VWUPD))
-			CPRINTS("VW Updated INT");
-
-		/* Get status again */
-		status = NPCX_ESPISTS & mask;
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_ESPI, espi_interrupt, 4);
-
-/*****************************************************************************/
-/* eSPI Initialization functions */
-void espi_init(void)
-{
-	int i;
-
-	/* Support all channels */
-	NPCX_ESPICFG |= ESPI_SUPP_CH_ALL;
-
-	/* Support all I/O modes */
-	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD,
-		NPCX_ESPI_IO_MODE_ALL);
-
-	/* Set eSPI speed to max supported */
-	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD,
-		  NPCX_ESPI_MAXFREQ_MAX);
-
-	/* Configure Controller-to-Peripheral Virtual Wire indexes (Inputs) */
-	for (i = 0; i < ARRAY_SIZE(espi_in_list); i++)
-		espi_vw_config_in(&espi_in_list[i]);
-
-	/* Configure Peripheral-to-Controller Virtual Wire indexes (Outputs) */
-	for (i = 0; i < ARRAY_SIZE(espi_out_list); i++)
-		espi_vw_config_out(&espi_out_list[i]);
-
-	/* Configure MIWU for eSPI VW */
-	for (i = 0; i < ARRAY_SIZE(espi_vw_int_list); i++)
-		espi_enable_vw_int(&espi_vw_int_list[i]);
-}
-
-static int command_espi(int argc, char **argv)
-{
-	uint32_t chan;
-	char *e;
-
-	if (argc == 1) {
-		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
-	} else if (argc == 2) {
-		int i;
-
-		if (strcasecmp(argv[1], "cfg") == 0) {
-			ccprintf("ESPICFG [0x%08x]\n", NPCX_ESPICFG);
-		} else if (strcasecmp(argv[1], "vsm") == 0) {
-			for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
-				uint32_t val = NPCX_VWEVSM(i);
-				uint8_t  idx = VWEVSM_IDX_GET(val);
-
-				ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx,
-						val);
-			}
-		} else if (strcasecmp(argv[1], "vms") == 0) {
-			for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
-				uint32_t val = NPCX_VWEVMS(i);
-				uint8_t  idx = VWEVMS_IDX_GET(val);
-
-				ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx,
-						val);
-			}
-		}
-	/* Enable/Disable the channels of eSPI */
-	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		if (m > 4)
-			return EC_ERROR_PARAM2;
-		else if (m == 4)
-			chan = 0x0F;
-		else
-			chan = 0x01 << m;
-		if (strcasecmp(argv[1], "en") == 0)
-			NPCX_ESPICFG = NPCX_ESPICFG | chan;
-		else if (strcasecmp(argv[1], "dis") == 0)
-			NPCX_ESPICFG = NPCX_ESPICFG & ~chan;
-		else
-			return EC_ERROR_PARAM1;
-		ccprintf("ESPICFG [0x%08x]\n", NPCX_ESPICFG);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
-			"eSPI configurations");
diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c
deleted file mode 100644
index f0b3215ce0..0000000000
--- a/chip/npcx/fan.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX fan control module. */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "console.h"
-#include "timer.h"
-#include "task.h"
-#include "hooks.h"
-#include "system.h"
-#include "math_util.h"
-
-#if !(DEBUG_FAN)
-#define CPRINTS(...)
-#else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-#endif
-
-/* Tacho measurement state */
-enum tacho_measure_state {
-	/* Tacho normal state */
-	TACHO_NORMAL = 0,
-	/* Tacho underflow state */
-	TACHO_UNDERFLOW
-};
-
-/* Fan mode */
-enum tacho_fan_mode {
-	/* FAN rpm mode */
-	TACHO_FAN_RPM = 0,
-	/* FAN duty mode */
-	TACHO_FAN_DUTY,
-};
-
-/* Fan status data structure */
-struct fan_status_t {
-	/* Current state of the measurement */
-	enum tacho_measure_state cur_state;
-	/* Fan mode */
-	enum tacho_fan_mode fan_mode;
-	/* MFT sampling freq*/
-	uint32_t mft_freq;
-	/* Actual rpm */
-	int rpm_actual;
-	/* Target rpm */
-	int rpm_target;
-	/* Automatic fan status */
-	enum fan_status auto_status;
-};
-
-/* Global variables */
-static volatile struct fan_status_t fan_status[FAN_CH_COUNT];
-static int rpm_pre[FAN_CH_COUNT];
-
-/*
- * Fan specifications. If they (PULSES_ROUND and RPM_DEVIATION) cannot meet
- * the followings, please replace them with correct one in board-level driver.
- */
-
-/* Pulses per round */
-#ifndef PULSES_ROUND
-#define PULSES_ROUND 2 /* 4-phases pwm-type fan. (2-phases should be 1) */
-#endif
-
-/* Rpm deviation (Unit:percent) */
-#ifndef RPM_DEVIATION
-#define RPM_DEVIATION 7
-#endif
-
-/*
- * RPM = 60 * f / (n * TACH)
- *   n = Pulses per round
- *   f = Tachometer (MFT) operation freq
- *   TACH = Counts of tachometer
- */
-#define TACH_TO_RPM(ch, tach) \
-	((fan_status[ch].mft_freq * 60 / PULSES_ROUND) / MAX((tach), 1))
-
-/* MFT TCNT default count */
-#define TACHO_MAX_CNT (BIT(16) - 1)
-
-/* Margin of target rpm */
-#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100)
-
-/**
- * MFT get fan rpm value
- *
- * @param   ch      operation channel
- * @return  actual  rpm
- */
-static int mft_fan_rpm(int ch)
-{
-	volatile struct fan_status_t *p_status = fan_status + ch;
-	int mdl = mft_channels[ch].module;
-	int tacho;
-
-	/* Check whether MFT underflow flag is occurred */
-	if (IS_BIT_SET(NPCX_TECTRL(mdl), NPCX_TECTRL_TCPND)) {
-		/* Clear pending flags */
-		SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TCCLR);
-
-		/*
-		 * Flag TDPND means mft underflow happen,
-		 * but let MFT still can re-measure actual rpm
-		 * when user change pwm/fan duty during
-		 * TACHO_UNDERFLOW state.
-		 */
-		p_status->cur_state = TACHO_UNDERFLOW;
-		p_status->auto_status = FAN_STATUS_STOPPED;
-		CPRINTS("Tacho is underflow !");
-
-		return 0;
-	}
-
-	/* Check whether MFT capture flag is set, else return previous rpm */
-	if (IS_BIT_SET(NPCX_TECTRL(mdl), NPCX_TECTRL_TAPND))
-		/* Clear pending flags */
-		SET_BIT(NPCX_TECLR(mdl), NPCX_TECLR_TACLR);
-	else
-		return p_status->rpm_actual;
-
-	p_status->cur_state = TACHO_NORMAL;
-	/*
-	 * Start of the last tacho cycle is detected -
-	 * calculated tacho cycle duration
-	 */
-	tacho = TACHO_MAX_CNT - NPCX_TCRA(mdl);
-	/* Transfer tacho to actual rpm */
-	return (tacho > 0) ? (TACH_TO_RPM(ch, tacho)) : 0;
-}
-
-/**
- * Set fan prescaler based on apb1 clock
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void mft_set_apb1_prescaler(int ch)
-{
-	int mdl = mft_channels[ch].module;
-	uint16_t prescaler_divider = 0;
-
-	/* Set clock prescaler divider to MFT module*/
-	prescaler_divider = (uint16_t)(clock_get_apb1_freq()
-			/ fan_status[ch].mft_freq);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0xFF)
-		prescaler_divider = 0xFF;
-
-	NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider;
-}
-
-/**
- * Fan configuration.
- *
- * @param ch                        operation channel
- * @param enable_mft_read_rpm       FAN_USE_RPM_MODE enable flag
- * @return none
- */
-static void fan_config(int ch, int enable_mft_read_rpm)
-{
-	int mdl = mft_channels[ch].module;
-	int pwm_id = mft_channels[ch].pwm_id;
-	enum npcx_mft_clk_src clk_src = mft_channels[ch].clk_src;
-
-	volatile struct fan_status_t *p_status = fan_status + ch;
-
-	/* Setup pwm with fan spec. */
-	pwm_config(pwm_id);
-
-	/* Need to initialize MFT or not */
-	if (enable_mft_read_rpm) {
-
-		/* Initialize tacho sampling rate */
-		if (clk_src == TCKC_LFCLK)
-			p_status->mft_freq = INT_32K_CLOCK;
-		else if (clk_src == TCKC_PRESCALE_APB1_CLK)
-			p_status->mft_freq = clock_get_apb1_freq();
-		else
-			p_status->mft_freq = 0;
-
-		/* Set mode 5 to MFT module */
-		SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD,
-				NPCX_MFT_MDSEL_5);
-
-		/* Set MFT operation frequency */
-		if (clk_src == TCKC_PRESCALE_APB1_CLK)
-			mft_set_apb1_prescaler(ch);
-
-		/* Set the low power mode or not. */
-		UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR,
-				clk_src == TCKC_LFCLK);
-
-		/* Set the default count-down timer. */
-		NPCX_TCNT1(mdl) = TACHO_MAX_CNT;
-		NPCX_TCRA(mdl)  = TACHO_MAX_CNT;
-
-		/* Set the edge polarity to rising. */
-		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG);
-		/* Enable capture TCNT1 into TCRA and preset TCNT1. */
-		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEN);
-		/* Enable input debounce logic into TA. */
-		SET_BIT(NPCX_TCFG(mdl), NPCX_TCFG_TADBEN);
-
-		/* Set the clock source type and start capturing */
-		SET_FIELD(NPCX_TCKC(mdl), NPCX_TCKC_C1CSEL_FIELD, clk_src);
-	}
-
-	/* Set default fan states */
-	p_status->cur_state = TACHO_NORMAL;
-	p_status->fan_mode = TACHO_FAN_DUTY;
-	p_status->auto_status = FAN_STATUS_STOPPED;
-}
-
-/**
- * Check all fans are stopped
- *
- * @return   1: all fans are stopped. 0: else.
- */
-static int fan_all_disabled(void)
-{
-	int ch;
-
-	for (ch = 0; ch < fan_get_count(); ch++)
-		if (fan_status[ch].auto_status != FAN_STATUS_STOPPED)
-			return 0;
-	return 1;
-}
-
-/**
- * Adjust fan duty by difference between target and actual rpm
- *
- * @param   ch        operation channel
- * @param   rpm_diff  difference between target and actual rpm
- * @param   duty      current fan duty
- */
-static void fan_adjust_duty(int ch, int rpm_diff, int duty)
-{
-	int duty_step = 0;
-
-	/* Find suitable duty step */
-	if (ABS(rpm_diff) >= 2000)
-		duty_step = 20;
-	else if (ABS(rpm_diff) >= 1000)
-		duty_step = 10;
-	else if (ABS(rpm_diff) >= 500)
-		duty_step = 5;
-	else if (ABS(rpm_diff) >= 250)
-		duty_step = 3;
-	else
-		duty_step = 1;
-
-	/* Adjust fan duty step by step */
-	if (rpm_diff > 0)
-		duty = MIN(duty + duty_step, 100);
-	else
-		duty = MAX(duty - duty_step, 1);
-
-	fan_set_duty(ch, duty);
-
-	CPRINTS("fan%d: duty %d, rpm_diff %d", ch, duty, rpm_diff);
-}
-
-/**
- * Smart fan control function.
- *
- * @param   ch         operation channel
- * @param   rpm_actual actual operation rpm value
- * @param   rpm_target target operation rpm value
- * @return  current    fan control status
- */
-enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
-{
-	int duty, rpm_diff;
-
-	/* wait rpm is stable */
-	if (ABS(rpm_actual - rpm_pre[ch]) > RPM_MARGIN(rpm_actual)) {
-		rpm_pre[ch] = rpm_actual;
-		return FAN_STATUS_CHANGING;
-	}
-
-	/* Record previous rpm */
-	rpm_pre[ch] = rpm_actual;
-
-	/* Adjust PWM duty */
-	rpm_diff = rpm_target - rpm_actual;
-	duty = fan_get_duty(ch);
-	if (duty == 0 && rpm_target == 0)
-		return FAN_STATUS_STOPPED;
-
-	/* Increase PWM duty */
-	if (rpm_diff > RPM_MARGIN(rpm_target)) {
-		if (duty == 100)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-	/* Decrease PWM duty */
-	} else if (rpm_diff < -RPM_MARGIN(rpm_target)) {
-		if (duty == 1 && rpm_target != 0)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-	}
-
-	return FAN_STATUS_LOCKED;
-}
-
-/**
- * Tick function for fan control.
- *
- * @return  none
- */
-void fan_tick_func(void)
-{
-	int ch;
-
-	for (ch = 0; ch < FAN_CH_COUNT ; ch++) {
-		volatile struct fan_status_t *p_status = fan_status + ch;
-		/* Make sure rpm mode is enabled */
-		if (p_status->fan_mode != TACHO_FAN_RPM) {
-		/* Fan in duty mode still want rpm_actual being updated. */
-			p_status->rpm_actual = mft_fan_rpm(ch);
-			if (p_status->rpm_actual > 0)
-				p_status->auto_status = FAN_STATUS_LOCKED;
-			else
-				p_status->auto_status = FAN_STATUS_STOPPED;
-			continue;
-		}
-		if (!fan_get_enabled(ch))
-			continue;
-		/* Get actual rpm */
-		p_status->rpm_actual = mft_fan_rpm(ch);
-		/* Do smart fan stuff */
-		p_status->auto_status = fan_smart_control(ch,
-				p_status->rpm_actual, p_status->rpm_target);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/**
- * Set fan duty cycle.
- *
- * @param   ch      operation channel
- * @param   percent duty cycle percent
- * @return  none
- */
-void fan_set_duty(int ch, int percent)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	/* duty is zero */
-	if (!percent) {
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-		if (fan_all_disabled())
-			enable_sleep(SLEEP_MASK_FAN);
-	} else
-		disable_sleep(SLEEP_MASK_FAN);
-
-	/* Set the duty cycle of PWM */
-	pwm_set_duty(pwm_id, percent);
-}
-
-/**
- * Get fan duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle
- */
-int fan_get_duty(int ch)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	/* Return percent */
-	return pwm_get_duty(pwm_id);
-}
-/**
- * Check fan is rpm operation mode.
- *
- * @param   ch  operation channel
- * @return  rpm operation mode or not
- */
-int fan_get_rpm_mode(int ch)
-{
-	return fan_status[ch].fan_mode == TACHO_FAN_RPM ? 1 : 0;
-}
-
-/**
- * Set fan to rpm operation mode.
- *
- * @param   ch          operation channel
- * @param   rpm_mode    rpm operation mode flag
- * @return  none
- */
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode)
-		fan_status[ch].fan_mode = TACHO_FAN_RPM;
-	else
-		fan_status[ch].fan_mode = TACHO_FAN_DUTY;
-}
-
-/**
- * Get fan actual operation rpm.
- *
- * @param   ch  operation channel
- * @return  actual operation rpm value
- */
-int fan_get_rpm_actual(int ch)
-{
-	/* Check PWM is enabled first */
-	if (fan_get_duty(ch) == 0)
-		return 0;
-
-	CPRINTS("fan %d: get actual rpm = %d", ch, fan_status[ch].rpm_actual);
-	return fan_status[ch].rpm_actual;
-}
-
-/**
- * Check fan enabled.
- *
- * @param   ch  operation channel
- * @return  enabled or not
- */
-int fan_get_enabled(int ch)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	return pwm_get_enabled(pwm_id);
-}
-/**
- * Set fan enabled.
- *
- * @param   ch      operation channel
- * @param   enabled enabled flag
- * @return  none
- */
-void fan_set_enabled(int ch, int enabled)
-{
-	int pwm_id = mft_channels[ch].pwm_id;
-
-	if (!enabled)
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-	pwm_enable(pwm_id, enabled);
-}
-
-/**
- * Get fan setting rpm.
- *
- * @param   ch  operation channel
- * @return  setting rpm value
- */
-int fan_get_rpm_target(int ch)
-{
-	return fan_status[ch].rpm_target;
-}
-
-/**
- * Set fan setting rpm.
- *
- * @param   ch  operation channel
- * @param   rpm setting rpm value
- * @return  none
- */
-void fan_set_rpm_target(int ch, int rpm)
-{
-	if (rpm == 0) {
-		/* If rpm = 0, disable PWM immediately. Why?*/
-		fan_set_duty(ch, 0);
-	} else {
-		/* This is the counterpart of disabling PWM above. */
-		if (!fan_get_enabled(ch))
-			fan_set_enabled(ch, 1);
-		if (rpm > fans[ch].rpm->rpm_max)
-			rpm = fans[ch].rpm->rpm_max;
-		else if (rpm < fans[ch].rpm->rpm_min)
-			rpm = fans[ch].rpm->rpm_min;
-	}
-
-	/* Set target rpm */
-	fan_status[ch].rpm_target = rpm;
-	CPRINTS("fan %d: set target rpm = %d", ch, fan_status[ch].rpm_target);
-}
-
-/**
- * Check fan operation status.
- *
- * @param   ch          operation channel
- * @return  fan_status  fan operation status
- */
-enum fan_status fan_get_status(int ch)
-{
-	return fan_status[ch].auto_status;
-}
-
-/**
- * Check fan is stall condition.
- *
- * @param   ch          operation channel
- * @return  non-zero    if fan is enabled but stalled
- */
-int fan_is_stalled(int ch)
-{
-	return fan_get_enabled(ch) && fan_get_duty(ch) &&
-			fan_status[ch].cur_state == TACHO_UNDERFLOW;
-}
-
-/**
- * Fan channel setup.
- *
- * @param ch        operation channel
- * @param flags     input flags
- * @return none
- */
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	fan_config(ch, (flags & FAN_USE_RPM_MODE));
-}
-
-/**
- * Fan initial.
- *
- * @param none
- * @return none
- */
-static void fan_init(void)
-{
-	/* Enable the fan module and delay a few clocks */
-	clock_enable_peripheral(CGC_OFFSET_FAN, CGC_FAN_MASK, CGC_MODE_ALL);
-}
-DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h
deleted file mode 100644
index 6fc228ec84..0000000000
--- a/chip/npcx/fan_chip.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific MFT module for Chrome EC */
-
-#ifndef __CROS_EC_FAN_CHIP_H
-#define __CROS_EC_FAN_CHIP_H
-
-/* MFT mode select */
-enum npcx_mft_mdsel {
-	NPCX_MFT_MDSEL_1,
-	NPCX_MFT_MDSEL_2,
-	NPCX_MFT_MDSEL_3,
-	NPCX_MFT_MDSEL_4,
-	NPCX_MFT_MDSEL_5,
-	/* Number of MFT modes */
-	NPCX_MFT_MDSEL_COUNT
-};
-
-/* MFT module select */
-enum npcx_mft_module {
-	NPCX_MFT_MODULE_1,
-	NPCX_MFT_MODULE_2,
-	NPCX_MFT_MODULE_3,
-	/* Number of MFT modules */
-	NPCX_MFT_MODULE_COUNT
-};
-
-/* MFT clock source */
-enum npcx_mft_clk_src {
-	TCKC_NOCLK = 0,
-	TCKC_PRESCALE_APB1_CLK = 1,
-	TCKC_LFCLK = 4,
-};
-
-/* Data structure to define MFT channels. */
-struct mft_t {
-	/* MFT module ID */
-	enum npcx_mft_module module;
-	/* MFT clock source */
-	enum npcx_mft_clk_src clk_src;
-	/* PWM id */
-	int pwm_id;
-};
-
-extern const struct mft_t mft_channels[];
-
-#endif /* __CROS_EC_FAN_CHIP_H */
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
deleted file mode 100644
index 507b83714c..0000000000
--- a/chip/npcx/flash.c
+++ /dev/null
@@ -1,832 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "flash.h"
-#include "host_command.h"
-#include "registers.h"
-#include "spi_flash_reg.h"
-#include "switch.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "task.h"
-#include "watchdog.h"
-#include "console.h"
-#include "hwtimer_chip.h"
-
-static int all_protected; /* Has all-flash protection been requested? */
-static int addr_prot_start;
-static int addr_prot_length;
-static uint8_t flag_prot_inconsistent;
-
-/* SR regs aren't readable when UMA lock is on, so save a copy */
-static uint8_t saved_sr1;
-static uint8_t saved_sr2;
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-#define TRISTATE_FLASH(x)
-#else
-#define TRISTATE_FLASH(x) flash_tristate(x)
-#endif
-
-/* Ensure only one task is accessing flash at a time. */
-static struct mutex flash_lock;
-
-/*****************************************************************************/
-/* flash internal functions */
-#if !defined(NPCX_INT_FLASH_SUPPORT)
-static void flash_pinmux(int enable)
-{
-	/* Select pin-mux for FIU*/
-	UPDATE_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI, !enable);
-
-	/* CS0/1 pinmux */
-	if (enable) {
-#if (FIU_CHIP_SELECT == 1)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-#elif (FIU_CHIP_SELECT == 2)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-#endif
-	} else {
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-	}
-}
-#endif
-
-static void flash_execute_cmd(uint8_t code, uint8_t cts)
-{
-	/*
-	 * Flash mutex must be held while executing UMA commands after
-	 * task_start().
-	 */
-	ASSERT(!task_start_called() || flash_lock.lock);
-
-	/* set UMA_CODE */
-	NPCX_UMA_CODE = code;
-	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
-	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-static void flash_cs_level(int level)
-{
-	/* Set chip select to high/low level */
-	UPDATE_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1, level);
-}
-
-static int flash_wait_ready(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_BUSY;
-	const timestamp_t start = get_time();
-	const uint32_t timeout_us = 10 * SECOND;
-	const timestamp_t deadline = {
-		.val = start.val + timeout_us,
-	};
-
-	/* Chip Select down. */
-	flash_cs_level(0);
-	/* Command for Read status register */
-	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
-	do {
-		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-		/* Busy bit is clear */
-		if ((NPCX_UMA_DB0 & mask) == 0)
-			break;
-		usleep(10);
-	} while (!timestamp_expired(deadline, NULL)); /* Wait for Busy clear */
-
-	/* Chip Select high. */
-	flash_cs_level(1);
-
-	if (timestamp_expired(deadline, NULL))
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-static int flash_write_enable(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_WEL;
-	int rv;
-	/* Wait for previous operation to complete */
-	rv = flash_wait_ready();
-	if (rv)
-		return rv;
-
-	/* Write enable command */
-	flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
-
-	/* Wait for flash is not busy */
-	rv = flash_wait_ready();
-	if (rv)
-		return rv;
-
-	if (NPCX_UMA_DB0 & mask)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_BUSY;
-}
-
-static void flash_set_address(uint32_t dest_addr)
-{
-	uint8_t *addr = (uint8_t *)&dest_addr;
-	/* Write address */
-	NPCX_UMA_AB2 = addr[2];
-	NPCX_UMA_AB1 = addr[1];
-	NPCX_UMA_AB0 = addr[0];
-}
-
-static uint8_t flash_get_status1(void)
-{
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr1;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read status register1 */
-	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	ret = NPCX_UMA_DB0;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return ret;
-}
-
-static uint8_t flash_get_status2(void)
-{
-	uint8_t ret;
-
-	if (all_protected)
-		return saved_sr2;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read status register2 */
-	flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	ret = NPCX_UMA_DB0;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return ret;
-}
-
-#ifdef NPCX_INT_FLASH_SUPPORT
-static int is_int_flash_protected(void)
-{
-	return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
-}
-
-static void flash_protect_int_flash(int enable)
-{
-	/*
-	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
-	 * only rebooting EC can clear it.
-	 */
-	if (enable && !is_int_flash_protected())
-		SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
-}
-#endif
-
-#ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
-
-void flash_get_mfr_dev_id(uint8_t *dest)
-{
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read manufacturer and device ID.  Send cmd=0x90 + 24-bit address=0 */
-	flash_set_address(0);
-	flash_execute_cmd(CMD_READ_MAN_DEV_ID,
-			  MASK_CMD_RD_2BYTE | MASK(A_SIZE));
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	dest[0] = NPCX_UMA_DB0;
-	dest[1] = NPCX_UMA_DB1;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-}
-
-#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
-
-void flash_get_jedec_id(uint8_t *dest)
-{
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Read manufacturer and device ID */
-	flash_execute_cmd(CMD_READ_ID, MASK_CMD_RD_3BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	dest[0] = NPCX_UMA_DB0;
-	dest[1] = NPCX_UMA_DB1;
-	dest[2] = NPCX_UMA_DB2;
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-}
-
-static void flash_uma_lock(int enable)
-{
-	if (enable && !all_protected) {
-		/*
-		 * Store SR1 / SR2 for later use since we're about to lock
-		 * out all access (including read access) to these regs.
-		 */
-		saved_sr1 = flash_get_status1();
-		saved_sr2 = flash_get_status2();
-	}
-
-	all_protected = enable;
-	UPDATE_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK, enable);
-}
-
-static int flash_set_status_for_prot(int reg1, int reg2)
-{
-	/*
-	 * Writing SR regs will fail if our UMA lock is enabled. If WP
-	 * is deasserted then remove the lock and allow the write.
-	 */
-	if (all_protected) {
-#ifdef NPCX_INT_FLASH_SUPPORT
-		if (is_int_flash_protected())
-			return EC_ERROR_ACCESS_DENIED;
-#endif
-
-		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
-			return EC_ERROR_ACCESS_DENIED;
-		flash_uma_lock(0);
-	}
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now before setting them.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /*_CONFIG_WP_ACTIVE_HIGH_*/
-#endif
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Enable write */
-	flash_write_enable();
-
-	NPCX_UMA_DB0 = reg1;
-	NPCX_UMA_DB1 = reg2;
-
-	/* Write status register 1/2 */
-	flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	spi_flash_reg_to_protect(reg1, reg2,
-				 &addr_prot_start, &addr_prot_length);
-
-	return EC_SUCCESS;
-}
-
-static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
-{
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-	/* Check if ranges overlap */
-	if (MAX(addr_prot_start, offset) < MIN(addr_prot_start +
-		addr_prot_length, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-}
-
-static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
-{
-	unsigned int start;
-	unsigned int len;
-	uint8_t sr1, sr2;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-#endif
-
-	sr1 = flash_get_status1();
-	sr2 = flash_get_status2();
-
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute current protect range */
-	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
-	if (rv)
-		return rv;
-
-	/* Check if ranges overlap */
-	if (MAX(start, offset) < MIN(start + len, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-
-}
-
-static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
-				int hw_protect)
-{
-	int rv;
-	uint8_t sr1 = flash_get_status1();
-	uint8_t sr2 = flash_get_status2();
-
-	/* Invalid values */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute desired protect range */
-	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
-	if (rv)
-		return rv;
-
-	if (hw_protect)
-		sr1 |= SPI_FLASH_SR1_SRP0;
-
-	return flash_set_status_for_prot(sr1, sr2);
-}
-
-static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
-{
-	unsigned int i;
-	/* Chip Select down */
-	flash_cs_level(0);
-	/* Set write address */
-	flash_set_address(dest_addr);
-	/* Start programming */
-	flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
-	for (i = 0; i < bytes; i++) {
-		flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
-		data++;
-	}
-	/* Chip Select up */
-	flash_cs_level(1);
-}
-
-static int flash_program_bytes(uint32_t offset, uint32_t bytes,
-	const uint8_t *data)
-{
-	int write_size;
-	int rv;
-
-	while (bytes > 0) {
-		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE -
-		(offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
-
-		/* Enable write */
-		rv = flash_write_enable();
-		if (rv)
-			return rv;
-
-		/* Burst UMA transaction */
-		flash_burst_write(offset, write_size, data);
-
-		/* Wait write completed */
-		rv = flash_wait_ready();
-		if (rv)
-			return rv;
-
-		data   += write_size;
-		offset += write_size;
-		bytes  -= write_size;
-	}
-
-	return rv;
-}
-
-/*****************************************************************************/
-
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	int dest_addr = offset;
-	uint32_t idx;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-	/* Chip Select down. */
-	flash_cs_level(0);
-
-	/* Set read address */
-	flash_set_address(dest_addr);
-	/* Start fast read - 1110 1001 - EXEC, WR, CMD, ADDR */
-	flash_execute_cmd(CMD_FAST_READ, MASK_CMD_ADR_WR);
-
-	/* Burst read transaction */
-	for (idx = 0; idx < size; idx++) {
-		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		/* wait for UMA to complete */
-		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
-			;
-		/* Get read transaction results*/
-		data[idx] = NPCX_UMA_DB0;
-	}
-
-	/* Chip Select up */
-	flash_cs_level(1);
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int dest_addr = offset;
-	int write_len;
-	int rv;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size
-	     | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1))
-		return EC_ERROR_INVAL;
-
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-
-	while (size > 0) {
-		/* First write multiples of 256, then (size % 256) last */
-		write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
-					size : CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-		/* check protection */
-		if (flash_check_prot_range(dest_addr, write_len)) {
-			rv = EC_ERROR_ACCESS_DENIED;
-			break;
-		}
-
-		rv = flash_program_bytes(dest_addr, write_len, data);
-		if (rv)
-			break;
-
-		data      += write_len;
-		dest_addr += write_len;
-		size      -= write_len;
-	}
-
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int rv = EC_SUCCESS;
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	/* Disable tri-state */
-	TRISTATE_FLASH(0);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		offset += CONFIG_FLASH_ERASE_SIZE) {
-		/* check protection */
-		if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) {
-			rv = EC_ERROR_ACCESS_DENIED;
-			break;
-		}
-
-		/*
-		 * Reload the watchdog timer, so that erasing many flash pages
-		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using msleep() below.
-		 */
-		watchdog_reload();
-
-		/* Enable write */
-		rv = flash_write_enable();
-		if (rv)
-			break;
-
-		/* Set erase address */
-		flash_set_address(offset);
-		/* Start erase */
-		flash_execute_cmd(NPCX_ERASE_COMMAND, MASK_CMD_ADR);
-
-		/* Wait erase completed */
-		rv = flash_wait_ready();
-		if (rv)
-			break;
-	}
-
-	/* Enable tri-state */
-	TRISTATE_FLASH(1);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
-
-	return flash_check_prot_reg(addr, CONFIG_FLASH_BANK_SIZE);
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Check if WP region is protected in status register */
-	if (flash_check_prot_reg(WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
-				 WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE))
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * TODO: If status register protects a range, but SRP0 is not set,
-	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
-	 */
-	if (flag_prot_inconsistent)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/*
-		 * Set UMA_LOCK bit for locking all UMA transaction.
-		 * But we still can read directly from flash mapping address
-		 */
-		flash_uma_lock(1);
-	} else {
-		/* TODO: Implement RO "now" protection */
-	}
-
-	return EC_SUCCESS;
-}
-
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int ret;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection bits in status register */
-		return flash_set_status_for_prot(0, 0);
-	}
-
-	ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF,
-				   CONFIG_WP_STORAGE_SIZE,
-				   1);
-
-	/*
-	 * Set UMA_LOCK bit for locking all UMA transaction.
-	 * But we still can read directly from flash mapping address
-	 */
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		flash_uma_lock(1);
-
-	return ret;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-			EC_FLASH_PROTECT_RO_NOW |
-			EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-			(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	/*
-	 * Protect status registers of internal spi-flash if WP# is active
-	 * during ec initialization.
-	 */
-#ifdef NPCX_INT_FLASH_SUPPORT
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(!gpio_get_level(GPIO_WP_L));
-#endif /*CONFIG_WP_ACTIVE_HIGH */
-#endif
-
-#if !defined(NPCX_INT_FLASH_SUPPORT)
-	/* Enable FIU interface */
-	flash_pinmux(1);
-#endif
-
-#if defined(CONFIG_EXTERNAL_STORAGE) && !defined(NPCX_INT_FLASH_SUPPORT)
-	/* Disable tristate all the time */
-	CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-#endif
-
-	/* Initialize UMA to unlocked */
-	flash_uma_lock(0);
-	return EC_SUCCESS;
-}
-
-void crec_flash_lock_mapped_storage(int lock)
-{
-	if (lock)
-		mutex_lock(&flash_lock);
-	else
-		mutex_unlock(&flash_lock);
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-#if defined(CONFIG_HOSTCMD_FLASH_SPI_INFO) && !defined(BOARD_NPCX_EVB)
-/* NPCX EVB uses implementation from spi_flash.c */
-
-static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_flash_spi_info *r = args->response;
-
-	flash_get_jedec_id(r->jedec);
-	r->reserved0 = 0;
-	flash_get_mfr_dev_id(r->mfr_dev_id);
-	r->sr1 = flash_get_status1();
-	r->sr2 = flash_get_status2();
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
-		     EC_VER_MASK(0));
-
-#endif
-
-#ifdef CONFIG_CMD_FLASH_TRISTATE
-#ifdef NPCX_INT_FLASH_SUPPORT
-#error "Flash tristate is not relevant when internal flash is used."
-#endif
-static void flash_tristate(int enable)
-{
-	/* Enable/Disable FIU pins to tri-state */
-	UPDATE_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS, enable);
-}
-
-static int flash_spi_sel_lock(int enable)
-{
-	/*
-	 * F_SPI_QUAD, F_SPI_CS1_1/2, F_SPI_TRIS become read-only
-	 * if this bit is set
-	 */
-	UPDATE_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK, enable);
-	return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_flash_spi_sel_lock(int argc, char **argv)
-{
-	int ena;
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &ena))
-			return EC_ERROR_PARAM1;
-		ena = flash_spi_sel_lock(ena);
-		ccprintf("Enabled: %d\n", ena);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock,
-			"[on | off]",
-			"Lock spi flash interface selection");
-
-static int command_flash_tristate(int argc, char **argv)
-{
-	int ena;
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &ena))
-			return EC_ERROR_PARAM1;
-		flash_tristate(ena);
-		ccprintf("Enabled: %d\n", ena);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate,
-			"[on | off]",
-			"Tristate spi flash pins");
-#endif /* CONFIG_CMD_FLASH_TRISTATE */
-
-static int command_flash_chip(int argc, char **argv)
-{
-	uint8_t jedec_id[3];
-
-	ccprintf("Status 1: 0x%02x, Status 2: 0x%02x\n", flash_get_status1(),
-			flash_get_status2());
-
-	flash_get_jedec_id(jedec_id);
-	ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0],
-			jedec_id[1], jedec_id[2]);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip,
-			NULL,
-			"Print flash chip info");
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
deleted file mode 100644
index e1d13c98d1..0000000000
--- a/chip/npcx/gpio-npcx5.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "task.h"
-
-/*
- * List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems.
- */
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
-	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
-	task_enable_irq(NPCX_IRQ_WKINTC_0);
-	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
-	task_enable_irq(NPCX_IRQ_WKINTA_1);
-	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-#endif
-	task_enable_irq(NPCX_IRQ_WKINTD_1);
-	task_enable_irq(NPCX_IRQ_WKINTE_1);
-	task_enable_irq(NPCX_IRQ_WKINTF_1);
-	task_enable_irq(NPCX_IRQ_WKINTG_1);
-	task_enable_irq(NPCX_IRQ_WKINTH_1);
-#if defined(CHIP_FAMILY_NPCX7)
-	task_enable_irq(NPCX_IRQ_WKINTFG_2);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
-
-/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_wk0efgh_interrupt(void)
-{
-	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
-		/* Pending bit 7 or 6 or 5? */
-		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
-			/* Disable host wake-up */
-			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			/* Clear pending bit of WUI */
-			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			return;
-		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
-				espi_espirst_handler();
-				return;
-			}
-		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
-				lpc_lreset_pltrst_handler();
-				return;
-			}
-		}
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void __gpio_rtc_interrupt(void)
-{
-	/* Check pending bit 7 */
-#ifdef CONFIG_HOSTCMD_RTC
-	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-		return;
-	}
-#endif
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 1)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
-}
-
-void __gpio_wk1h_interrupt(void)
-{
-#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
-	(CONFIG_CONSOLE_UART == 0)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-	} else
-#endif
-		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
-}
-
-GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
-GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
-GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
-GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
-/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
-GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
-#endif
-GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
-GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
-GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-#if defined(CHIP_FAMILY_NPCX7)
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-#endif
-
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SHI
-/*
- * HACK: Make CS GPIO P2 to improve SHI reliability.
- * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P3 CS interrupt.
- */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
-#else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
-#if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
-#endif
-
-#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
deleted file mode 120000
index 39b939f44c..0000000000
--- a/chip/npcx/gpio-npcx7.c
+++ /dev/null
@@ -1 +0,0 @@
-gpio-npcx5.c
\ No newline at end of file
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
deleted file mode 100644
index 2bb4ae085c..0000000000
--- a/chip/npcx/gpio-npcx9.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lct_chip.h"
-#include "lpc_chip.h"
-#include "registers.h"
-#include "task.h"
-
-/*
- * List of GPIO IRQs to enable. Don't automatically enable interrupts for
- * the keyboard input GPIO bank - that's handled separately. Of course the
- * bank is different for different systems.
- */
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(NPCX_IRQ_CR_SIN2_WKINTA_0);
-	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
-	task_enable_irq(NPCX_IRQ_WKINTC_0);
-	task_enable_irq(NPCX_IRQ_MTC_WKINTD_0);
-	task_enable_irq(NPCX_IRQ_WKINTE_0);
-	task_enable_irq(NPCX_IRQ_WKINTF_0);
-	task_enable_irq(NPCX_IRQ_WKINTG_0);
-	task_enable_irq(NPCX_IRQ_WKINTH_0);
-	task_enable_irq(NPCX_IRQ_WKINTA_1);
-	task_enable_irq(NPCX_IRQ_WKINTB_1);
-#ifndef HAS_TASK_KEYSCAN
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-#endif
-	task_enable_irq(NPCX_IRQ_WKINTD_1);
-	task_enable_irq(NPCX_IRQ_WKINTE_1);
-	task_enable_irq(NPCX_IRQ_WKINTF_1);
-	task_enable_irq(NPCX_IRQ_WKINTG_1);
-	task_enable_irq(NPCX_IRQ_WKINTH_1);
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
- */
-
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-void _irq_func(void)					\
-{							\
-	gpio_interrupt(wui_int);			\
-}
-
-/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_host_interrupt(void)
-{
-	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
-		/* Pending bit 7 or 6 or 5? */
-		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
-			/* Disable host wake-up */
-			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			/* Clear pending bit of WUI */
-			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-			return;
-		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
-				espi_espirst_handler();
-				return;
-			}
-		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
-				lpc_lreset_pltrst_handler();
-				return;
-			}
-		}
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void __gpio_rtc_interrupt(void)
-{
-	/* Check pending bit 7 */
-#ifdef CONFIG_HOSTCMD_RTC
-	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
-}
-void __gpio_cr_sin2_interrupt(void)
-{
-#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 1)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-		return;
-	}
-#endif
-	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-
-}
-
-void __gpio_wk1h_interrupt(void)
-{
-#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 0)
-	/* Handle the interrupt from UART wakeup event */
-	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
-	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
-		/*
-		 * Disable WKEN bit to avoid the other unnecessary interrupts
-		 * from the coming data bits after the start bit. (Pending bit
-		 * of CR_SIN is set when a high-to-low transaction occurs.)
-		 */
-		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Clear pending bit for WUI */
-		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
-		/* Notify the clock module that the console is in use. */
-		clock_refresh_console_in_use();
-	} else
-#endif
-		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
-}
-
-void __gpio_lct_interrupt(void)
-{
-	if (NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_6) & LCT_WUI_MASK) {
-		NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) |= LCT_WUI_MASK;
-		npcx_lct_clear_event();
-		return;
-	}
-	gpio_interrupt(WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-}
-
-GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
-GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
-GPIO_IRQ_FUNC(__gpio_wk0f_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk0g_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
-GPIO_IRQ_FUNC(__gpio_wk0h_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
-GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
-GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
-#ifndef HAS_TASK_KEYSCAN
-/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
-GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
-#endif
-GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
-GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
-GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
-GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
-GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
-
-DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,     __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,         __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0,     __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_0,         __gpio_host_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTF_0,         __gpio_wk0f_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTG_0,         __gpio_wk0g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_0,         __gpio_wk0h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,         __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,         __gpio_wk1b_interrupt, 3);
-#ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,     __gpio_wk1c_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,         __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,         __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SHI
-/*
- * HACK: Make CS GPIO P2 to improve SHI reliability.
- * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P3 CS interrupt.
- */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 2);
-#else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 3);
-#endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,         __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,         __gpio_wk1h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2,     __gpio_lct_interrupt, 3);
-
-#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
deleted file mode 100644
index e740f0aa9f..0000000000
--- a/chip/npcx/gpio.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "common.h"
-#include "gpio.h"
-#include "gpio_chip.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "system.h"
-#include "system_chip.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "hwtimer_chip.h"
-
-#if !(DEBUG_GPIO)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_GPIO, outstr)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-#endif
-
-/* Constants for GPIO interrupt mapping */
-#define GPIO_INT(name, pin, flags, signal) NPCX_WUI_GPIO_##pin,
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Extend gpio_wui_table for the bypass of better power consumption */
-#define GPIO(name, pin, flags) NPCX_WUI_GPIO_##pin,
-#define UNIMPLEMENTED(name) WUI_NONE,
-#else
-/* Ignore GPIO and UNIMPLEMENTED definitions if not using lower power idle */
-#define GPIO(name, pin, flags)
-#define UNIMPLEMENTED(name)
-#endif
-static const struct npcx_wui gpio_wui_table[] = {
-	#include "gpio.wrap"
-};
-
-struct npcx_gpio {
-	uint8_t port  : 4;
-	uint8_t bit   : 3;
-	uint8_t valid : 1;
-};
-
-BUILD_ASSERT(sizeof(struct npcx_gpio) == 1);
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-struct npcx_alt {
-	uint8_t group;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-	uint8_t reserved  : 4;
-};
-#else
-struct npcx_alt {
-	uint8_t group     : 4;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-};
-#endif
-
-struct gpio_alt_map {
-	struct npcx_gpio gpio;
-	struct npcx_alt  alt;
-};
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-BUILD_ASSERT(sizeof(struct gpio_alt_map) == 3);
-#else
-BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2);
-#endif
-
-/* Constants for GPIO alternative mapping */
-const __const_data struct gpio_alt_map gpio_alt_table[] = NPCX_ALT_TABLE;
-
-struct gpio_lvol_item {
-	struct npcx_gpio lvol_gpio[8];
-};
-
-/* Constants for GPIO low-voltage mapping */
-const struct gpio_lvol_item gpio_lvol_table[] = NPCX_LVOL_TABLE;
-
-/*****************************************************************************/
-/* Internal functions */
-
-static int gpio_match(uint8_t port, uint8_t bit, struct npcx_gpio gpio)
-{
-	return (gpio.valid && (gpio.port == port) && (gpio.bit == bit));
-}
-
-#ifdef CONFIG_CMD_GPIO_EXTENDED
-static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit)
-{
-	struct gpio_alt_map const *map;
-	uint8_t alt_mask, devalt;
-
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
-	     map++) {
-		if (gpio_match(port, bit, map->gpio)) {
-			alt_mask = 1 << map->alt.bit;
-			devalt = NPCX_DEVALT(map->alt.group);
-			/*
-			 * alt.inverted == 0:
-			 *   !!(devalt & alt_mask) == 0 -> GPIO
-			 *   !!(devalt & alt_mask) == 1 -> Alternate
-			 * alt.inverted == 1:
-			 *   !!(devalt & alt_mask) == 0 -> Alternate
-			 *   !!(devalt & alt_mask) == 1 -> GPIO
-			 */
-			return !!(devalt & alt_mask) ^ map->alt.inverted;
-		}
-	}
-	return 0;
-}
-#endif
-
-static int gpio_alt_sel(uint8_t port, uint8_t bit,
-			enum gpio_alternate_func func)
-{
-	struct gpio_alt_map const *map;
-
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
-	     map++) {
-		if (gpio_match(port, bit, map->gpio)) {
-			uint8_t alt_mask = 1 << map->alt.bit;
-
-			/*
-			 * func < GPIO_ALT_FUNC_DEFAULT -> GPIO functionality
-			 * map->alt.inverted -> Set DEVALT bit for GPIO
-			 */
-			if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted)
-				NPCX_DEVALT(map->alt.group) &= ~alt_mask;
-			else
-				NPCX_DEVALT(map->alt.group) |=  alt_mask;
-
-			return 1;
-		}
-	}
-
-	if (func > GPIO_ALT_FUNC_DEFAULT)
-		CPRINTS("Warn! No alter func in port%d, pin%d", port, bit);
-
-	return -1;
-}
-
-/* Set interrupt type for GPIO input */
-static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags)
-{
-	uint8_t table, group, pmask;
-
-	if (signal >= GPIO_IH_COUNT)
-		return;
-
-	table = gpio_wui_table[signal].table;
-	group = gpio_wui_table[signal].group;
-	pmask = 1 << gpio_wui_table[signal].bit;
-
-	ASSERT(flags & GPIO_INT_ANY);
-
-	/* Handle interrupt for level trigger */
-	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) {
-		/* Set detection mode to level */
-		NPCX_WKMOD(table, group) |= pmask;
-		/* Handle interrupting on level high */
-		if (flags & GPIO_INT_F_HIGH)
-			NPCX_WKEDG(table, group) &= ~pmask;
-		/* Handle interrupting on level low */
-		else if (flags & GPIO_INT_F_LOW)
-			NPCX_WKEDG(table, group) |= pmask;
-	}
-	/* Handle interrupt for edge trigger */
-	else {
-		/* Set detection mode to edge */
-		NPCX_WKMOD(table, group) &= ~pmask;
-		/* Handle interrupting on both edges */
-		if ((flags & GPIO_INT_F_RISING) &&
-			(flags & GPIO_INT_F_FALLING)) {
-			/* Enable any edge */
-			NPCX_WKAEDG(table, group) |= pmask;
-		}
-		/* Handle interrupting on rising edge */
-		else if (flags & GPIO_INT_F_RISING) {
-			/* Disable any edge */
-			NPCX_WKAEDG(table, group) &= ~pmask;
-			NPCX_WKEDG(table, group) &= ~pmask;
-		}
-		/* Handle interrupting on falling edge */
-		else if (flags & GPIO_INT_F_FALLING) {
-			/* Disable any edge */
-			NPCX_WKAEDG(table, group) &= ~pmask;
-			NPCX_WKEDG(table, group) |= pmask;
-		}
-	}
-
-	/* Enable wake-up input sources */
-	NPCX_WKINEN(table, group) |= pmask;
-	/*
-	 * Clear pending bit since it might be set
-	 * if WKINEN bit is changed.
-	 */
-	NPCX_WKPCL(table, group) |= pmask;
-
-	/* No support analog mode */
-}
-
-#ifdef CONFIG_CMD_GPIO_EXTENDED
-static uint8_t gpio_is_low_voltage_level_sel(uint8_t port, uint8_t bit)
-{
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(gpio_lvol_table); i++) {
-		const struct npcx_gpio *gpio = gpio_lvol_table[i].lvol_gpio;
-
-		for (j = 0; j < ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio); j++) {
-			if (gpio_match(port, bit, gpio[j]))
-				return IS_BIT_SET(NPCX_LV_GPIO_CTL(i), j);
-		}
-	}
-	return 0;
-}
-#endif
-
-/* Select low voltage detection level */
-void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage)
-{
-	int i, j;
-
-	for (i = 0; i < ARRAY_SIZE(gpio_lvol_table); i++) {
-		const struct npcx_gpio *gpio = gpio_lvol_table[i].lvol_gpio;
-
-		for (j = 0; j < ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio); j++) {
-			if (gpio_match(port, bit, gpio[j])) {
-				if (low_voltage)
-					/* Select vol-detect level for 1.8V */
-					SET_BIT(NPCX_LV_GPIO_CTL(i), j);
-				else
-					/* Select vol-detect level for 3.3V */
-					CLEAR_BIT(NPCX_LV_GPIO_CTL(i), j);
-				return;
-			}
-		}
-	}
-
-	if (low_voltage)
-		CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d",
-								port, bit);
-}
-
-/* Set the low voltage detection level by mask */
-static void gpio_low_vol_sel_by_mask(uint8_t p, uint8_t mask, uint8_t low_vol)
-{
-	int bit;
-	uint32_t lv_mask = mask;
-
-	while (lv_mask) {
-		bit = get_next_bit(&lv_mask);
-		gpio_low_voltage_level_sel(p, bit, low_vol);
-	};
-}
-/* The bypass of low voltage IOs for better power consumption */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int gpio_is_i2c_pin(enum gpio_signal signal)
-{
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++)
-		if (i2c_ports[i].scl == signal || i2c_ports[i].sda == signal)
-			return 1;
-
-	return 0;
-}
-
-static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable)
-{
-	const struct npcx_wui *wui = gpio_wui_table + signal;
-
-	/* Is it a valid wui mapping item? */
-	if (wui->table != MIWU_TABLE_COUNT) {
-		/* Turn on/off input io buffer by WKINENx registers */
-		if (enable)
-			SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit);
-		else
-			CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group),
-						wui->bit);
-	}
-}
-
-void gpio_enable_1p8v_i2c_wake_up_input(int enable)
-{
-	int i;
-
-	/* Set input buffer of 1.8V i2c ports. */
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (gpio_list[i2c_ports[i].scl].flags & GPIO_SEL_1P8V)
-			gpio_enable_wake_up_input(i2c_ports[i].scl, enable);
-		if (gpio_list[i2c_ports[i].sda].flags & GPIO_SEL_1P8V)
-			gpio_enable_wake_up_input(i2c_ports[i].sda, enable);
-	}
-}
-#endif
-
-/*
- * Make sure the bit depth of low voltage register.
- */
-BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8);
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	/* Enable alternative pins by func */
-	int pin;
-
-	/* check each bit from mask  */
-	for (pin = 0; pin < 8; pin++)
-		if (mask & BIT(pin))
-			gpio_alt_sel(port, pin, func);
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	ASSERT(signal_is_gpio(signal));
-
-	return !!(NPCX_PDIN(gpio_list[signal].port) & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	ASSERT(signal_is_gpio(signal));
-
-	if (value)
-		NPCX_PDOUT(gpio_list[signal].port) |=  gpio_list[signal].mask;
-	else
-		NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
-}
-
-#ifdef CONFIG_GPIO_GET_EXTENDED
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	uint32_t flags = 0;
-
-	if (NPCX_PDIR(port) & mask)
-		flags |= GPIO_OUTPUT;
-	else
-		flags |= GPIO_INPUT;
-
-	if (NPCX_PDIN(port) & mask)
-		flags |= GPIO_HIGH;
-	else
-		flags |= GPIO_LOW;
-
-	if (NPCX_PTYPE(port) & mask)
-		flags |= GPIO_OPEN_DRAIN;
-
-	/* If internal pulling is enabled */
-	if (NPCX_PPULL(port) & mask) {
-		if (NPCX_PPUD(port) & mask)
-			flags |= GPIO_PULL_DOWN;
-		else
-			flags |= GPIO_PULL_UP;
-	}
-
-	if (gpio_is_alt_sel(port, GPIO_MASK_TO_NUM(mask)))
-		flags |= GPIO_ALTERNATE;
-
-	if (gpio_is_low_voltage_level_sel(port, GPIO_MASK_TO_NUM(mask)))
-		flags |= GPIO_SEL_1P8V;
-
-	if (NPCX_PLOCK_CTL(port) & mask)
-		flags |= GPIO_LOCKED;
-
-	return flags;
-}
-#endif
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* If all GPIO pins are locked, return directly */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	if ((NPCX_PLOCK_CTL(port) & mask) == mask)
-		return;
-#endif
-
-	/*
-	 * Configure pin as input, if requested. Output is configured only
-	 * after setting all other attributes, so as not to create a
-	 * temporary incorrect logic state 0:input 1:output
-	 */
-	if (!(flags & GPIO_OUTPUT))
-		NPCX_PDIR(port) &= ~mask;
-
-	/* Select open drain 0:push-pull 1:open-drain */
-	if (flags & GPIO_OPEN_DRAIN)
-		NPCX_PTYPE(port) |= mask;
-	else
-		NPCX_PTYPE(port) &= ~mask;
-
-	/* Select pull-up/down of GPIO 0:pull-up 1:pull-down */
-	if (flags & GPIO_PULL_UP) {
-		if (flags & GPIO_SEL_1P8V) {
-			CPRINTS("Warn! enable internal PU and low voltage mode"
-					" at the same time is illegal. port 0x%x, mask 0x%x",
-					port, mask);
-		} else {
-			NPCX_PPUD(port)  &= ~mask;
-			NPCX_PPULL(port) |= mask; /* enable pull down/up */
-		}
-	} else if (flags & GPIO_PULL_DOWN) {
-		NPCX_PPUD(port)  |= mask;
-		NPCX_PPULL(port) |= mask; /* enable pull down/up */
-	} else {
-		/* No pull up/down */
-		NPCX_PPULL(port) &= ~mask; /* disable pull down/up */
-	}
-
-	/* 1.8V low voltage select */
-	if (flags & GPIO_SEL_1P8V) {
-		/*
-		 * Set IO type to open-drain before selecting low-voltage level
-		 */
-		NPCX_PTYPE(port) |= mask;
-		gpio_low_vol_sel_by_mask(port, mask, 1);
-	} else
-		gpio_low_vol_sel_by_mask(port, mask, 0);
-
-	/* Set up interrupt type */
-	if (flags & GPIO_INT_ANY) {
-		const struct gpio_info *g = gpio_list;
-		enum gpio_signal gpio_int;
-
-		/* Find gpio signal in GPIO_INTs by port and mask */
-		for (gpio_int = 0; gpio_int < GPIO_IH_COUNT; gpio_int++, g++)
-			if ((g->port == port) && (g->mask & mask))
-				gpio_interrupt_type_sel(gpio_int, flags);
-	}
-
-	/* Set level 0:low 1:high*/
-	if (flags & GPIO_HIGH)
-		NPCX_PDOUT(port) |= mask;
-	else if (flags & GPIO_LOW)
-		NPCX_PDOUT(port) &= ~mask;
-
-	/* Configure pin as output, if requested 0:input 1:output */
-	if (flags & GPIO_OUTPUT)
-		NPCX_PDIR(port) |= mask;
-
-	/* Lock GPIO output and configuration if need */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	if (flags & GPIO_LOCKED)
-		NPCX_PLOCK_CTL(port) |= mask;
-#endif
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	/* Set MIWU enable bit */
-	NPCX_WKEN(wui.table, wui.group) |= 1 << wui.bit;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	NPCX_WKEN(wui.table, wui.group) &= ~(1 << wui.bit);
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	struct npcx_wui wui;
-
-	/* Fail if not an interrupt handler */
-	if (signal >= GPIO_IH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	wui = gpio_wui_table[signal];
-	NPCX_WKPCL(wui.table, wui.group) |= 1 << wui.bit;
-
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	const struct unused_pin_info *u = unused_pin_list;
-	int is_warm;
-	int flags;
-	int i, j;
-
-	system_check_bbram_on_reset();
-	is_warm = system_is_reboot_warm();
-
-	/*
-	 * On power-on of some boards, H1 releases the EC from reset but then
-	 * quickly asserts and releases the reset a second time. This means the
-	 * EC sees 2 resets: (1) power-on reset, (2) reset-pin reset. If we add
-	 * a delay between reset (1) and configuring GPIO output levels, then
-	 * reset (2) will happen before the end of the delay so we avoid extra
-	 * output toggles.
-	 *
-	 * Make sure to set up the timer before using udelay().
-	 */
-	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-	    system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR) {
-		__hw_early_init_hwtimer(0);
-		udelay(2 * SECOND);
-		/* Shouldn't get here, but proceeding anyway... */
-	}
-
-#ifdef CHIP_FAMILY_NPCX7
-	/*
-	 * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
-	 * for more information. It will be fixed in next chip.
-	 */
-	SET_BIT(NPCX_DEVCNT, 7);
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/* Lock VCC_RST# alternative bit in case switch to GPO77 unexpectedly */
-	SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_VCC1_RST_LK);
-#endif
-
-	/* Pin_Mux for FIU/SPI (set to GPIO) */
-	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-#if defined(NPCX_INT_FLASH_SUPPORT)
-	SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-#endif
-
-	/* Pin_Mux for PWRGD */
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_NO_PWRGD);
-
-	/* Pin_Mux for PECI */
-#ifndef CONFIG_PECI
-	SET_BIT(NPCX_DEVALT(0xA), NPCX_DEVALTA_NO_PECI_EN);
-#endif
-
-	/* Pin_Mux for LPC & SHI */
-#ifdef CONFIG_HOSTCMD_SHI
-	/* Switching to eSPI mode for SHI interface */
-	NPCX_DEVCNT |= 0x08;
-	/* Alternate Intel bus interface LPC/eSPI to GPIOs first */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_1), NPCX_DEVALT1_NO_LPC_ESPI);
-#endif
-
-	/* Clear all interrupt pending and enable bits of GPIOS */
-	for (i = 0; i < 2; i++) {
-		for (j = 0; j < 8; j++) {
-			NPCX_WKPCL(i, j) = 0xFF;
-			NPCX_WKEN(i, j) = 0;
-		}
-	}
-
-	/* No support enable clock for the GPIO port in run and sleep. */
-	/* Set flag for each GPIO pin in gpio_list */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-
-		/*
-		 * Ensure that any GPIO defined in gpio.inc is actually
-		 * configured as a GPIO, and not left in its default state,
-		 * which may or may not be as a GPIO.
-		 */
-		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
-	}
-
-	/* The bypass of low voltage IOs for better power consumption */
-#ifdef CONFIG_LOW_POWER_IDLE
-	/* Disable input buffer of 1.8V GPIOs without ISR */
-	g = gpio_list + GPIO_IH_COUNT;
-	for (i = GPIO_IH_COUNT; i < GPIO_COUNT; i++, g++) {
-		/*
-		 * I2c ports are both alternate mode and normal gpio pin, but
-		 * the alternate mode needs the wake up input even though the
-		 * normal gpio definition doesn't have an ISR.
-		 */
-		if ((g->flags & GPIO_SEL_1P8V) && !gpio_is_i2c_pin(i))
-			gpio_enable_wake_up_input(i, 0);
-	}
-#endif
-
-	/* Configure unused pins as GPIO INPUT with PU to save power. */
-	for (i = 0; i < unused_pin_count; i++, u++) {
-		gpio_set_flags_by_mask(u->port, u->mask,
-				       GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_alternate_function(g->port, g->mask,
-					    GPIO_ALT_FUNC_NONE);
-	}
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-
-/**
- * Handle a GPIO interrupt.
- *
- * @param wui_int wui table & group for GPIO interrupt no.
- */
-
-void gpio_interrupt(struct npcx_wui wui_int)
-{
-	int i;
-	uint8_t wui_mask;
-	uint8_t table = wui_int.table;
-	uint8_t group = wui_int.group;
-
-	/* Get pending mask */
-	wui_mask = NPCX_WKPND(table, group) & NPCX_WKEN(table, group);
-
-	/* Find GPIOs and execute interrupt service routine */
-	for (i = 0; i < GPIO_IH_COUNT && wui_mask; i++) {
-		uint8_t pin_mask = 1 << gpio_wui_table[i].bit;
-
-		if ((gpio_wui_table[i].table == table) &&
-			(gpio_wui_table[i].group == group) &&
-			(wui_mask & pin_mask)) {
-			/* Clear pending bit of GPIO */
-			NPCX_WKPCL(table, group) = pin_mask;
-			/* Execute GPIO's ISR */
-			gpio_irq_handlers[i](i);
-			/* In case declare the same GPIO in gpio_wui_table */
-			wui_mask &= ~pin_mask;
-		}
-	}
-
-	if (wui_mask)
-		/* No ISR for this interrupt, just clear it */
-		NPCX_WKPCL(table, group) = wui_mask;
-}
-
-#undef GPIO_IRQ_FUNC
-#if DEBUG_GPIO && defined(CONFIG_LOW_POWER_IDLE)
-/*
- * Command used to disable input buffer of gpios one by one to
- * investigate power consumption
- */
-static int command_gpiodisable(int argc, char **argv)
-{
-	uint8_t i;
-	uint8_t offset;
-	const uint8_t non_isr_gpio_num = GPIO_COUNT - GPIO_IH_COUNT;
-	const struct gpio_info *g_list;
-	int flags;
-	static uint8_t idx = 0;
-	int num = -1;
-	int enable;
-	char *e;
-
-	if (argc == 2) {
-		if (!strcasecmp(argv[1], "info")) {
-			offset = idx + GPIO_IH_COUNT;
-			g_list = gpio_list + offset;
-			flags = g_list->flags;
-
-			ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT);
-			ccprintf("Total Non-ISR GPIO declaration: %d\n",
-						non_isr_gpio_num);
-			ccprintf("Next GPIO Num to check by ");
-			ccprintf("\"gpiodisable next\"\n");
-			ccprintf("  offset: %d\n", offset);
-			ccprintf("  current GPIO name: %s\n", g_list->name);
-			ccprintf("  current GPIO flags: 0x%08x\n", flags);
-			return EC_SUCCESS;
-		}
-		/* List all non-ISR GPIOs in gpio.inc */
-		if (!strcasecmp(argv[1], "list")) {
-			for (i = GPIO_IH_COUNT; i < GPIO_COUNT; i++)
-				ccprintf("%d: %s\n", i, gpio_get_name(i));
-			return EC_SUCCESS;
-		}
-
-		if (!strcasecmp(argv[1], "next")) {
-			while (1) {
-				if (idx == non_isr_gpio_num)
-					break;
-
-				offset = idx + GPIO_IH_COUNT;
-				g_list = gpio_list + offset;
-				flags = g_list->flags;
-				ccprintf("current GPIO : %d %s --> ",
-							offset, g_list->name);
-				if (gpio_is_i2c_pin(offset)) {
-					ccprintf("Ignore I2C pin!\n");
-					idx++;
-					continue;
-				} else if (flags & GPIO_SEL_1P8V) {
-					ccprintf("Ignore 1v8 pin!\n");
-					idx++;
-					continue;
-				} else {
-					if ((flags & GPIO_INPUT) ||
-						    (flags & GPIO_OPEN_DRAIN)) {
-						ccprintf("Disable WKINEN!\n");
-						gpio_enable_wake_up_input(
-								offset, 0);
-						idx++;
-						break;
-					}
-					ccprintf("Not Input or OpenDrain\n");
-					idx++;
-					continue;
-				}
-			};
-			if (idx == non_isr_gpio_num) {
-				ccprintf("End of GPIO list, reset index!\n");
-				idx = 0;
-			};
-			return EC_SUCCESS;
-		}
-	}
-	if (argc == 3) {
-		num = strtoi(argv[1], &e, 0);
-		if (*e || num < GPIO_IH_COUNT || num >= GPIO_COUNT)
-			return EC_ERROR_PARAM1;
-
-		if (parse_bool(argv[2], &enable))
-			gpio_enable_wake_up_input(num, enable ? 1 : 0);
-		else
-			return EC_ERROR_PARAM2;
-
-		return EC_SUCCESS;
-	}
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable,
-		"info/list/next/<num> on|off",
-		"Disable GPIO input buffer to investigate power consumption");
-#endif
diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h
deleted file mode 100644
index 83916a421b..0000000000
--- a/chip/npcx/gpio_chip-npcx5.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX5_H
-#define __CROS_EC_GPIO_CHIP_NPCX5_H
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7)
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_1_3 WUI(1, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_6_5 WUI(1, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_B_6 WUI_NONE
-#define NPCX_WUI_GPIO_D_6 WUI_NONE
-
-/* Others GPIO without MIWU functionality on npcx5 */
-#define NPCX_WUI_GPIO_D_4 WUI_NONE
-#define NPCX_WUI_GPIO_D_5 WUI_NONE
-#define NPCX_WUI_GPIO_D_7 WUI_NONE
-#define NPCX_WUI_GPIO_E_0 WUI_NONE
-#define NPCX_WUI_GPIO_E_1 WUI_NONE
-#define NPCX_WUI_GPIO_E_2 WUI_NONE
-#define NPCX_WUI_GPIO_E_3 WUI_NONE
-#define NPCX_WUI_GPIO_E_4 WUI_NONE
-#define NPCX_WUI_GPIO_E_5 WUI_NONE
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SDA1 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C0_1_SL)) /* SMB0SCL1 */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL */
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN SEL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT SEL2 */
-
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1  */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SIN */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
-/* KSO09 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* Clock module */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
-#define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
-
-/* PS/2 module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_3  /* KSO16 */               \
-	NPCX_ALT_GPIO_0_4  /* KSO13 */               \
-	NPCX_ALT_GPIO_0_5  /* KSO12 */               \
-	NPCX_ALT_GPIO_0_6  /* KSO11 */               \
-	NPCX_ALT_GPIO_0_7  /* KSO10 */               \
-	NPCX_ALT_GPIO_1_0  /* KSO09 & CR_SOUT */     \
-	NPCX_ALT_GPIO_1_1  /* KSO08 & CR_SIN */      \
-	NPCX_ALT_GPIO_1_2  /* KSO07 */               \
-	NPCX_ALT_GPIO_1_3  /* KSO06 */               \
-	NPCX_ALT_GPIO_1_4  /* KSO05 */               \
-	NPCX_ALT_GPIO_1_5  /* KSO04 */               \
-	NPCX_ALT_GPIO_1_6  /* KSO03 */               \
-	NPCX_ALT_GPIO_1_7  /* KSO02 */               \
-	NPCX_ALT_GPIO_2_0  /* KSO01 */               \
-	NPCX_ALT_GPIO_2_1  /* KSO00 */               \
-	NPCX_ALT_GPIO_2_2  /* KSI7 */                \
-	NPCX_ALT_GPIO_2_3  /* KSI6 */                \
-	NPCX_ALT_GPIO_2_4  /* KSI5 */                \
-	NPCX_ALT_GPIO_2_5  /* KSI4 */                \
-	NPCX_ALT_GPIO_2_6  /* KSI3 */                \
-	NPCX_ALT_GPIO_2_7  /* KSI2 */                \
-	NPCX_ALT_GPIO_3_0  /* KSI1 */                \
-	NPCX_ALT_GPIO_3_1  /* KSI0 */                \
-	NPCX_ALT_GPIO_3_4  /* PS2_DAT2 */            \
-	NPCX_ALT_GPIO_3_7  /* PS2_CLK2 */            \
-	NPCX_ALT_GPIO_4_0  /* TA1_SEL1 */            \
-	NPCX_ALT_GPIO_4_1  /* ADC4 */                \
-	NPCX_ALT_GPIO_4_2  /* ADC3 */                \
-	NPCX_ALT_GPIO_4_4  /* ADC1 */                \
-	NPCX_ALT_GPIO_4_5  /* ADC0 */                \
-	NPCX_ALT_GPIO_4_3  /* ADC2 */                \
-	NPCX_ALT_GPIO_6_0  /* PWM7 */                \
-	NPCX_ALT_GPIO_6_2  /* PS2_CLK1 */            \
-	NPCX_ALT_GPIO_6_3  /* PS2_DAT1 */            \
-	NPCX_ALT_GPIO_6_4  /* CR_SIN2 */             \
-	NPCX_ALT_GPIO_6_5  /* CR_SOUT2 */            \
-	NPCX_ALT_GPIO_6_7  /* PS2_CLK0 */            \
-	NPCX_ALT_GPIO_7_0  /* PS2_DAT0 */            \
-	NPCX_ALT_GPIO_7_3  /* TA2_SEL1 */            \
-	NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */            \
-	NPCX_ALT_GPIO_8_0  /* PWM3 */                \
-	NPCX_ALT_GPIO_8_2  /* KSO14 */               \
-	NPCX_ALT_GPIO_8_3  /* KSO15 */               \
-	NPCX_ALT_GPIO_8_7  /* SMB1SDA */             \
-	NPCX_ALT_GPIO_9_0  /* SMB1SCL */             \
-	NPCX_ALT_GPIO_9_1  /* SMB2SDA */             \
-	NPCX_ALT_GPIO_9_2  /* SMB2SCL */             \
-	NPCX_ALT_GPIO_9_3  /* TA1_SEL2 */            \
-	NPCX_ALT_GPIO_9_5  /* SPIP_MISO */           \
-	NPCX_ALT_GPIO_A_1  /* SPIP_SCLK */           \
-	NPCX_ALT_GPIO_A_3  /* SPIP_MOSI */           \
-	NPCX_ALT_GPIO_A_5  /* SPIP_CS1  */           \
-	NPCX_ALT_GPIO_A_6  /* TA2_SEL2/PS2_CLK3 */   \
-	NPCX_ALT_GPIO_A_7  /* PS2_DAT3 */            \
-	NPCX_ALT_GPIO_B_1  /* KSO17 */               \
-	NPCX_ALT_GPIO_B_2  /* SMB0SDA1 */            \
-	NPCX_ALT_GPIO_B_3  /* SMB0SCL1 */            \
-	NPCX_ALT_GPIO_B_4  /* SMB0SDA0 */            \
-	NPCX_ALT_GPIO_B_5  /* SMB0SCL0 */            \
-	NPCX_ALT_GPIO_B_6  /* PWM4 */                \
-	NPCX_ALT_GPIO_B_7  /* PWM5 */                \
-	NPCX_ALT_GPIO_C_0  /* PWM6 */                \
-	NPCX_ALT_GPIO_C_2  /* PWM1 */                \
-	NPCX_ALT_GPIO_C_3  /* PWM0 */                \
-	NPCX_ALT_GPIO_C_4  /* PWM2 */                \
-	NPCX_ALT_GPIO_D_0  /* SMB3SDA */             \
-	NPCX_ALT_GPIO_D_1  /* SMB3SCL */             \
-	NPCX_ALT_GPIO_E_7  /* 32KCLKIN */            \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO(6, 5)
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* 4 Low-Voltage Control Groups on npcx5 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h
deleted file mode 100644
index 7f815e6d30..0000000000
--- a/chip/npcx/gpio_chip-npcx7.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX7_H
-#define __CROS_EC_GPIO_CHIP_NPCX7_H
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#ifndef NPCX_PSL_MODE_SUPPORT
-#define NPCX_WUI_GPIO_8_4 WUI(0, MIWU_GROUP_1, 4) /* Used as VSBY in PSL */
-#define NPCX_WUI_GPIO_8_5 WUI(0, MIWU_GROUP_1, 5) /* Used as PSL_OUT in PSL */
-#endif
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_D_7 WUI(0, MIWU_GROUP_7, 6)
-#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
-#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */
-#endif
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/
-#endif
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* MIWU2 */
-/* Group F: NPCX_IRQ_WKINTFG_2 */
-#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_B_6 WUI_NONE /* Software strap pin GP_SEL0_L */
-#define NPCX_WUI_GPIO_D_6 WUI_NONE
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */
-/* Pin-Mux for PSL/UART2/SMB4_0 */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL))  /* CR_SOUT2 */
-#define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
-#else
-#define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */
-#define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
-#endif
-#else
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SDA0 */
-#define NPCX_ALT_GPIO_8_5 ALT(8, 5, NPCX_ALT(2, I2C4_0_SL)) /* SMB4SCL0 */
-#endif
-
-#define NPCX_ALT_GPIO_F_2 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */
-#define NPCX_ALT_GPIO_F_3 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */
-#define NPCX_ALT_GPIO_3_6 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */
-#define NPCX_ALT_GPIO_3_3 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */
-#define NPCX_ALT_GPIO_F_4 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */
-#define NPCX_ALT_GPIO_F_5 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */
-/* Pin-Mux for PWM1/SMB6_0 */
-#if NPCX7_PWM1_SEL
-#define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
-#else
-#define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
-#endif
-#define NPCX_ALT_GPIO_E_3 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */
-#define NPCX_ALT_GPIO_E_4 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#else
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
-#endif
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7  */
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9  */
-
-/* PS/2 Module */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(C, UART_SL2)) /* CR_SIN SEL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(C, UART_SL2)) /* CR_SOUT SEL2 */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* Clock module (Optional) */
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_ALT_GPIO_E_7 /* No 32KCLKIN */
-#else
-#define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
-#endif
-
-/* Pin-Mux for UART2/32KHZ_OUT */
-#if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL))    /* CR_SIN2 */
-#else
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
-#endif
-
-/* PSL module (Optional) */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#else
-#define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_1 /* NO PSL in NPCX7mnG series */
-#define NPCX_ALT_GPIO_0_2 /* NO PSL in NPCX7mnG series */
-#endif
-
-/* WOV module (Optional) */
-#if defined(NPCX_WOV_SUPPORT) && \
-	(defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV))
-#define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */
-#define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */
-#define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */
-
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(E, I2S_SL)) /* I2S_SYNC */
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(E, I2S_SL)) /* I2S_SCLK */
-#define NPCX_ALT_GPIO_B_0 ALT(B, 0, NPCX_ALT(E, I2S_SL)) /* I2S_DATA */
-#define NPCX_ALT_GPIO_9_4 ALT(9, 4, NPCX_ALT(E, WOV_SL)) /* DMIC_CLK */
-#define NPCX_ALT_GPIO_9_7 ALT(9, 7, NPCX_ALT(E, WOV_SL)) /* DMIC_IN  */
-#else
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_5 ALT(A, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_CS1  */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-#define NPCX_ALT_GPIO_B_0
-#define NPCX_ALT_GPIO_9_4
-#define NPCX_ALT_GPIO_9_7
-#endif
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
-	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
-	NPCX_ALT_GPIO_0_2 /* PSL_IN4 */               \
-	NPCX_ALT_GPIO_0_3 /* KSO16 */                 \
-	NPCX_ALT_GPIO_0_4 /* KSO13 */                 \
-	NPCX_ALT_GPIO_0_5 /* KSO12 */                 \
-	NPCX_ALT_GPIO_0_6 /* KSO11 */                 \
-	NPCX_ALT_GPIO_0_7 /* KSO10 */                 \
-	NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */        \
-	NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */       \
-	NPCX_ALT_GPIO_1_2 /* KSO07 */                 \
-	NPCX_ALT_GPIO_1_3 /* KSO06 */                 \
-	NPCX_ALT_GPIO_1_4 /* KSO05 */                 \
-	NPCX_ALT_GPIO_1_5 /* KSO04 */                 \
-	NPCX_ALT_GPIO_1_6 /* KSO03 */                 \
-	NPCX_ALT_GPIO_1_7 /* KSO02 */                 \
-	NPCX_ALT_GPIO_2_0 /* KSO01 */                 \
-	NPCX_ALT_GPIO_2_1 /* KSO00 */                 \
-	NPCX_ALT_GPIO_2_2 /* KSI7 */                  \
-	NPCX_ALT_GPIO_2_3 /* KSI6 */                  \
-	NPCX_ALT_GPIO_2_4 /* KSI5 */                  \
-	NPCX_ALT_GPIO_2_5 /* KSI4 */                  \
-	NPCX_ALT_GPIO_2_6 /* KSI3 */                  \
-	NPCX_ALT_GPIO_2_7 /* KSI2 */                  \
-	NPCX_ALT_GPIO_3_0 /* KSI1 */                  \
-	NPCX_ALT_GPIO_3_1 /* KSI0 */                  \
-	NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */              \
-	NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */         \
-	NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */              \
-	NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */         \
-	NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */              \
-	NPCX_ALT_GPIO_4_1 /* ADC4  */                 \
-	NPCX_ALT_GPIO_4_2 /* ADC3  */                 \
-	NPCX_ALT_GPIO_4_3 /* ADC2  */                 \
-	NPCX_ALT_GPIO_4_4 /* ADC1  */                 \
-	NPCX_ALT_GPIO_4_5 /* ADC0  */                 \
-	NPCX_ALT_GPIO_6_0 /* PWM7 */                  \
-	NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */              \
-	NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */              \
-	NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */          \
-	NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */         \
-	NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */              \
-	NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */              \
-	NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */              \
-	NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */   \
-	NPCX_ALT_GPIO_8_0 /* PWM3 */                  \
-	NPCX_ALT_GPIO_8_2 /* KSO14 */		      \
-	NPCX_ALT_GPIO_8_3 /* KSO15 */		      \
-	NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */              \
-	NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */   \
-	NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */              \
-	NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */              \
-	NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */              \
-	NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */              \
-	NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */              \
-	NPCX_ALT_GPIO_9_4 /* DMIC_CLK */              \
-	NPCX_ALT_GPIO_9_5 /* SPIP_MISO */             \
-	NPCX_ALT_GPIO_9_7 /* DMIC_IN */               \
-	NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */             \
-	NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */             \
-	NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */   \
-	NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */     \
-	NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */     \
-	NPCX_ALT_GPIO_B_0 /* I2S_DATA */              \
-	NPCX_ALT_GPIO_B_1 /* KSO17 */		      \
-	NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */              \
-	NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */              \
-	NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */              \
-	NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */              \
-	NPCX_ALT_GPIO_B_6 /* PWM4 */                  \
-	NPCX_ALT_GPIO_B_7 /* PWM5 */                  \
-	NPCX_ALT_GPIO_C_0 /* PWM6 */                  \
-	NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */              \
-	NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */       \
-	NPCX_ALT_GPIO_C_3 /* PWM0 */                  \
-	NPCX_ALT_GPIO_C_4 /* PWM2 */                  \
-	NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */              \
-	NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */              \
-	NPCX_ALT_GPIO_D_2 /* PSL_IN1 */               \
-	NPCX_ALT_GPIO_E_1 /* ADC7  */                 \
-	NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */              \
-	NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */              \
-	NPCX_ALT_GPIO_E_7 /* 32KCLKIN */              \
-	NPCX_ALT_GPIO_F_0 /* ADC9  */                 \
-	NPCX_ALT_GPIO_F_1 /* ADC8  */                 \
-	NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */              \
-	NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */              \
-	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
-	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#else
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#endif
-
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */
-#else
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#endif
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/
-#else
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#endif
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
-
-/* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
-
-/* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h
deleted file mode 100644
index 005a03d83e..0000000000
--- a/chip/npcx/gpio_chip-npcx9.h
+++ /dev/null
@@ -1,470 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_NPCX9_H
-#define __CROS_EC_GPIO_CHIP_NPCX9_H
-
-#ifndef NPCX9_PWM1_SEL
-#define NPCX9_PWM1_SEL 0
-#endif /* NPCX9_PWM1_SEL */
-
-/*****************************************************************************/
-/* Macro functions for MIWU mapping table */
-
-/* MIWU0 */
-/* Group A: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_8_0 WUI(0, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_8_1 WUI(0, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_8_2 WUI(0, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_8_3 WUI(0, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_8_6 WUI(0, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_8_7 WUI(0, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_TWD_WKINTB_0 */
-#define NPCX_WUI_GPIO_9_0 WUI(0, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_9_1 WUI(0, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_9_2 WUI(0, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_9_3 WUI(0, MIWU_GROUP_2, 3)
-#define NPCX_WUI_GPIO_9_4 WUI(0, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_9_5 WUI(0, MIWU_GROUP_2, 5)
-
-/* Group C: NPCX_IRQ_WKINTC_0 */
-#define NPCX_WUI_GPIO_9_6 WUI(0, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_9_7 WUI(0, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_A_0 WUI(0, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_A_1 WUI(0, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_A_2 WUI(0, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_A_3 WUI(0, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_A_4 WUI(0, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_A_5 WUI(0, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_MTC_WKINTAD_0 */
-#define NPCX_WUI_GPIO_A_6 WUI(0, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_A_7 WUI(0, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_B_0 WUI(0, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_B_1 WUI(0, MIWU_GROUP_4, 5)
-#define NPCX_WUI_GPIO_B_2 WUI(0, MIWU_GROUP_4, 6)
-
-/* Group E: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_B_3 WUI(0, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_B_4 WUI(0, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_B_5 WUI(0, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_B_7 WUI(0, MIWU_GROUP_5, 4)
-
-/* Group F: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_C_0 WUI(0, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_C_1 WUI(0, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_C_2 WUI(0, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_C_3 WUI(0, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_C_4 WUI(0, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_C_5 WUI(0, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_C_6 WUI(0, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_C_7 WUI(0, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_D_0 WUI(0, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_D_1 WUI(0, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_D_2 WUI(0, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_D_3 WUI(0, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_D_4 WUI(0, MIWU_GROUP_7, 4)
-#define NPCX_WUI_GPIO_D_5 WUI(0, MIWU_GROUP_7, 5)
-#define NPCX_WUI_GPIO_E_0 WUI(0, MIWU_GROUP_7, 7)
-
-/* Group H: NPCX_IRQ_WKINTEFGH_0 */
-#define NPCX_WUI_GPIO_E_1 WUI(0, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_E_2 WUI(0, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_E_3 WUI(0, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_E_4 WUI(0, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_E_5 WUI(0, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
-
-/* MIWU1 */
-/* Group A: NPCX_IRQ_WKINTA_1 */
-#define NPCX_WUI_GPIO_0_0 WUI(1, MIWU_GROUP_1, 0)
-#define NPCX_WUI_GPIO_0_1 WUI(1, MIWU_GROUP_1, 1)
-#define NPCX_WUI_GPIO_0_2 WUI(1, MIWU_GROUP_1, 2)
-#define NPCX_WUI_GPIO_0_3 WUI(1, MIWU_GROUP_1, 3)
-#define NPCX_WUI_GPIO_0_4 WUI(1, MIWU_GROUP_1, 4)
-#define NPCX_WUI_GPIO_0_5 WUI(1, MIWU_GROUP_1, 5)
-#define NPCX_WUI_GPIO_0_6 WUI(1, MIWU_GROUP_1, 6)
-#define NPCX_WUI_GPIO_0_7 WUI(1, MIWU_GROUP_1, 7)
-
-/* Group B: NPCX_IRQ_WKINTB_1 */
-#define NPCX_WUI_GPIO_1_0 WUI(1, MIWU_GROUP_2, 0)
-#define NPCX_WUI_GPIO_1_1 WUI(1, MIWU_GROUP_2, 1)
-#define NPCX_WUI_GPIO_F_4 WUI(1, MIWU_GROUP_2, 2)
-#define NPCX_WUI_GPIO_1_4 WUI(1, MIWU_GROUP_2, 4)
-#define NPCX_WUI_GPIO_1_5 WUI(1, MIWU_GROUP_2, 5)
-#define NPCX_WUI_GPIO_1_6 WUI(1, MIWU_GROUP_2, 6)
-#define NPCX_WUI_GPIO_1_7 WUI(1, MIWU_GROUP_2, 7)
-
-/* Group C: NPCX_IRQ_KSI_WKINTC_1 */
-#define NPCX_WUI_GPIO_3_1 WUI(1, MIWU_GROUP_3, 0)
-#define NPCX_WUI_GPIO_3_0 WUI(1, MIWU_GROUP_3, 1)
-#define NPCX_WUI_GPIO_2_7 WUI(1, MIWU_GROUP_3, 2)
-#define NPCX_WUI_GPIO_2_6 WUI(1, MIWU_GROUP_3, 3)
-#define NPCX_WUI_GPIO_2_5 WUI(1, MIWU_GROUP_3, 4)
-#define NPCX_WUI_GPIO_2_4 WUI(1, MIWU_GROUP_3, 5)
-#define NPCX_WUI_GPIO_2_3 WUI(1, MIWU_GROUP_3, 6)
-#define NPCX_WUI_GPIO_2_2 WUI(1, MIWU_GROUP_3, 7)
-
-/* Group D: NPCX_IRQ_WKINTD_1 */
-#define NPCX_WUI_GPIO_2_0 WUI(1, MIWU_GROUP_4, 0)
-#define NPCX_WUI_GPIO_2_1 WUI(1, MIWU_GROUP_4, 1)
-#define NPCX_WUI_GPIO_F_5 WUI(1, MIWU_GROUP_4, 2)
-#define NPCX_WUI_GPIO_3_3 WUI(1, MIWU_GROUP_4, 3)
-#define NPCX_WUI_GPIO_3_4 WUI(1, MIWU_GROUP_4, 4)
-#define NPCX_WUI_GPIO_3_6 WUI(1, MIWU_GROUP_4, 6)
-#define NPCX_WUI_GPIO_3_7 WUI(1, MIWU_GROUP_4, 7)
-
-/* Group E: NPCX_IRQ_WKINTE_1 */
-#define NPCX_WUI_GPIO_4_0 WUI(1, MIWU_GROUP_5, 0)
-#define NPCX_WUI_GPIO_4_1 WUI(1, MIWU_GROUP_5, 1)
-#define NPCX_WUI_GPIO_4_2 WUI(1, MIWU_GROUP_5, 2)
-#define NPCX_WUI_GPIO_4_3 WUI(1, MIWU_GROUP_5, 3)
-#define NPCX_WUI_GPIO_4_4 WUI(1, MIWU_GROUP_5, 4)
-#define NPCX_WUI_GPIO_4_5 WUI(1, MIWU_GROUP_5, 5)
-#define NPCX_WUI_GPIO_4_6 WUI(1, MIWU_GROUP_5, 6)
-#define NPCX_WUI_GPIO_4_7 WUI(1, MIWU_GROUP_5, 7)
-
-/* Group F: NPCX_IRQ_WKINTF_1 */
-#define NPCX_WUI_GPIO_5_0 WUI(1, MIWU_GROUP_6, 0)
-#define NPCX_WUI_GPIO_5_1 WUI(1, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_5_2 WUI(1, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_5_3 WUI(1, MIWU_GROUP_6, 3)
-#define NPCX_WUI_GPIO_5_4 WUI(1, MIWU_GROUP_6, 4)
-#define NPCX_WUI_GPIO_5_5 WUI(1, MIWU_GROUP_6, 5)
-#define NPCX_WUI_GPIO_5_6 WUI(1, MIWU_GROUP_6, 6)
-#define NPCX_WUI_GPIO_5_7 WUI(1, MIWU_GROUP_6, 7)
-
-/* Group G: NPCX_IRQ_WKINTG_1 */
-#define NPCX_WUI_GPIO_6_0 WUI(1, MIWU_GROUP_7, 0)
-#define NPCX_WUI_GPIO_6_1 WUI(1, MIWU_GROUP_7, 1)
-#define NPCX_WUI_GPIO_6_2 WUI(1, MIWU_GROUP_7, 2)
-#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
-#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
-
-/* Group H: NPCX_IRQ_WKINTH_1 */
-#define NPCX_WUI_GPIO_7_0 WUI(1, MIWU_GROUP_8, 0)
-#define NPCX_WUI_GPIO_6_7 WUI(1, MIWU_GROUP_8, 1)
-#define NPCX_WUI_GPIO_7_2 WUI(1, MIWU_GROUP_8, 2)
-#define NPCX_WUI_GPIO_7_3 WUI(1, MIWU_GROUP_8, 3)
-#define NPCX_WUI_GPIO_7_4 WUI(1, MIWU_GROUP_8, 4)
-#define NPCX_WUI_GPIO_7_5 WUI(1, MIWU_GROUP_8, 5)
-#define NPCX_WUI_GPIO_7_6 WUI(1, MIWU_GROUP_8, 6)
-
-/* MIWU2 */
-/* Group F: NPCX_IRQ_WKINTFG_2 */
-#define NPCX_WUI_GPIO_F_1 WUI(2, MIWU_GROUP_6, 1)
-#define NPCX_WUI_GPIO_F_2 WUI(2, MIWU_GROUP_6, 2)
-#define NPCX_WUI_GPIO_B_6 WUI(2, MIWU_GROUP_6, 6)
-
-/* Others GPO without MIWU functionality */
-#define NPCX_WUI_GPIO_1_2 WUI_NONE
-#define NPCX_WUI_GPIO_1_3 WUI_NONE /* Software strap pin GP_SEL1_L */
-#define NPCX_WUI_GPIO_3_2 WUI_NONE
-#define NPCX_WUI_GPIO_3_5 WUI_NONE
-#define NPCX_WUI_GPIO_6_5 WUI_NONE /* Software strap pin FLPRG_L */
-#define NPCX_WUI_GPIO_6_6 WUI_NONE
-#define NPCX_WUI_GPIO_7_7 WUI_NONE
-#define NPCX_WUI_GPIO_8_5 WUI_NONE /* PSL_OUT/GPO85 */
-#define NPCX_WUI_GPIO_D_6 WUI_NONE /* strap pin SHDF_ESPI */
-#define NPCX_WUI_GPIO_D_7 WUI_NONE /* PSL_GPO/GPOD7 */
-
-/*****************************************************************************/
-/* Macro functions for Alternative mapping table */
-
-/* I2C Module */
-#define NPCX_ALT_GPIO_B_4 ALT(B, 4, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SDA0 */
-#define NPCX_ALT_GPIO_B_5 ALT(B, 5, NPCX_ALT(2, I2C0_0_SL)) /* SMB0SCL0 */
-#define NPCX_ALT_GPIO_B_2 ALT(B, 2, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SDA0 */
-#define NPCX_ALT_GPIO_B_3 ALT(B, 3, NPCX_ALT(2, I2C7_0_SL)) /* SMB7SCL0 */
-#define NPCX_ALT_GPIO_8_7 ALT(8, 7, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SDA0 */
-#define NPCX_ALT_GPIO_9_0 ALT(9, 0, NPCX_ALT(2, I2C1_0_SL)) /* SMB1SCL0 */
-#define NPCX_ALT_GPIO_9_1 ALT(9, 1, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SDA0 */
-#define NPCX_ALT_GPIO_9_2 ALT(9, 2, NPCX_ALT(2, I2C2_0_SL)) /* SMB2SCL0 */
-#define NPCX_ALT_GPIO_3_6 ALT(3, 6, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SDA0 */
-#define NPCX_ALT_GPIO_3_3 ALT(3, 3, NPCX_ALT(2, I2C5_0_SL)) /* SMB5SCL0 */
-#define NPCX_ALT_GPIO_D_0 ALT(D, 0, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SDA0 */
-#define NPCX_ALT_GPIO_D_1 ALT(D, 1, NPCX_ALT(2, I2C3_0_SL)) /* SMB3SCL0 */
-
-#define NPCX_ALT_GPIO_F_2 ALT(F, 2, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SDA1 */
-#define NPCX_ALT_GPIO_F_3 ALT(F, 3, NPCX_ALT(6, I2C4_1_SL)) /* SMB4SCL1 */
-#define NPCX_ALT_GPIO_F_4 ALT(F, 4, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SDA1 */
-#define NPCX_ALT_GPIO_F_5 ALT(F, 5, NPCX_ALT(6, I2C5_1_SL)) /* SMB5SCL1 */
-#define NPCX_ALT_GPIO_E_3 ALT(E, 3, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SDA1 */
-#define NPCX_ALT_GPIO_E_4 ALT(E, 4, NPCX_ALT(6, I2C6_1_SL)) /* SMB6SCL1 */
-/* Pin-Mux for PWM1/SMB6_0 */
-#if NPCX9_PWM1_SEL
-#define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
-#else
-#define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
-#endif
-
-/* ADC Module */
-#define NPCX_ALT_GPIO_4_5 ALT(4, 5, NPCX_ALT(6, ADC0_SL)) /* ADC0  */
-#define NPCX_ALT_GPIO_4_4 ALT(4, 4, NPCX_ALT(6, ADC1_SL)) /* ADC1  */
-#define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2  */
-#define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3  */
-#define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4  */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2)
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */
-#else
-#define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
-#define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
-#endif
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL))  /* ADC8  */
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL))  /* ADC7  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL))  /* ADC9  */
-#define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10  */
-#define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11  */
-
-/* PS/2 Module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL))  /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL))  /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL))  /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL))  /* PS2_DATA1 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
-#else
-#define NPCX_ALT_GPIO_A_7
-#endif
-
-/* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL))  /* CR_SIN2_SL */
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */
-#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL))  /* CR_SIN3_SL */
-#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */
-
-/* PWM Module */
-#define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
-#define NPCX_ALT_GPIO_C_4 ALT(C, 4, NPCX_ALT(4, PWM2_SL)) /* PWM2 */
-#define NPCX_ALT_GPIO_8_0 ALT(8, 0, NPCX_ALT(4, PWM3_SL)) /* PWM3 */
-#define NPCX_ALT_GPIO_B_6 ALT(B, 6, NPCX_ALT(4, PWM4_SL)) /* PWM4 */
-#define NPCX_ALT_GPIO_B_7 ALT(B, 7, NPCX_ALT(4, PWM5_SL)) /* PWM5 */
-#define NPCX_ALT_GPIO_C_0 ALT(C, 0, NPCX_ALT(4, PWM6_SL)) /* PWM6 */
-#define NPCX_ALT_GPIO_6_0 ALT(6, 0, NPCX_ALT(4, PWM7_SL)) /* PWM7 */
-
-/* MFT Module */
-#define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */
-#define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */
-#define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */
-#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */
-#else
-#define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */
-#endif
-
-/* Keyboard Scan Module */
-#define NPCX_ALT_GPIO_3_1 ALT(3, 1, NPCX_ALT_INV(7, NO_KSI0_SL)) /* KSI0 */
-#define NPCX_ALT_GPIO_3_0 ALT(3, 0, NPCX_ALT_INV(7, NO_KSI1_SL)) /* KSI1 */
-#define NPCX_ALT_GPIO_2_7 ALT(2, 7, NPCX_ALT_INV(7, NO_KSI2_SL)) /* KSI2 */
-#define NPCX_ALT_GPIO_2_6 ALT(2, 6, NPCX_ALT_INV(7, NO_KSI3_SL)) /* KSI3 */
-#define NPCX_ALT_GPIO_2_5 ALT(2, 5, NPCX_ALT_INV(7, NO_KSI4_SL)) /* KSI4 */
-#define NPCX_ALT_GPIO_2_4 ALT(2, 4, NPCX_ALT_INV(7, NO_KSI5_SL)) /* KSI5 */
-#define NPCX_ALT_GPIO_2_3 ALT(2, 3, NPCX_ALT_INV(7, NO_KSI6_SL)) /* KSI6 */
-#define NPCX_ALT_GPIO_2_2 ALT(2, 2, NPCX_ALT_INV(7, NO_KSI7_SL)) /* KSI7 */
-#define NPCX_ALT_GPIO_2_1 ALT(2, 1, NPCX_ALT_INV(8, NO_KSO00_SL)) /* KSO00 */
-#define NPCX_ALT_GPIO_2_0 ALT(2, 0, NPCX_ALT_INV(8, NO_KSO01_SL)) /* KSO01 */
-#define NPCX_ALT_GPIO_1_7 ALT(1, 7, NPCX_ALT_INV(8, NO_KSO02_SL)) /* KSO02 */
-#define NPCX_ALT_GPIO_1_6 ALT(1, 6, NPCX_ALT_INV(8, NO_KSO03_SL)) /* KSO03 */
-#define NPCX_ALT_GPIO_1_5 ALT(1, 5, NPCX_ALT_INV(8, NO_KSO04_SL)) /* KSO04 */
-#define NPCX_ALT_GPIO_1_4 ALT(1, 4, NPCX_ALT_INV(8, NO_KSO05_SL)) /* KSO05 */
-#define NPCX_ALT_GPIO_1_3 ALT(1, 3, NPCX_ALT_INV(8, NO_KSO06_SL)) /* KSO06 */
-#define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
-/* KSO08 & CR_SOUT */
-#define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
-#define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
-#define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
-#define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
-#define NPCX_ALT_GPIO_0_5 ALT(0, 5, NPCX_ALT_INV(9, NO_KSO12_SL)) /* KSO12 */
-#define NPCX_ALT_GPIO_0_4 ALT(0, 4, NPCX_ALT_INV(9, NO_KSO13_SL)) /* KSO13 */
-#define NPCX_ALT_GPIO_8_2 ALT(8, 2, NPCX_ALT_INV(9, NO_KSO14_SL)) /* KSO14 */
-#define NPCX_ALT_GPIO_8_3 ALT(8, 3, NPCX_ALT_INV(9, NO_KSO15_SL)) /* KSO15 */
-#define NPCX_ALT_GPIO_0_3 ALT(0, 3, NPCX_ALT_INV(A, NO_KSO16_SL)) /* KSO16 */
-#define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
-
-/* PSL module */
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL))      /* PSL_GPO */
-
-/* SPI Module */
-#define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
-#define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
-#define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
-
-#define NPCX_ALT_TABLE { \
-	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
-	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
-	NPCX_ALT_GPIO_0_2 /* PSL_IN4 */               \
-	NPCX_ALT_GPIO_0_3 /* KSO16 */                 \
-	NPCX_ALT_GPIO_0_4 /* KSO13 */                 \
-	NPCX_ALT_GPIO_0_5 /* KSO12 */                 \
-	NPCX_ALT_GPIO_0_6 /* KSO11 */                 \
-	NPCX_ALT_GPIO_0_7 /* KSO10 */                 \
-	NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */        \
-	NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */       \
-	NPCX_ALT_GPIO_1_2 /* KSO07 */                 \
-	NPCX_ALT_GPIO_1_3 /* KSO06 */                 \
-	NPCX_ALT_GPIO_1_4 /* KSO05 */                 \
-	NPCX_ALT_GPIO_1_5 /* KSO04 */                 \
-	NPCX_ALT_GPIO_1_6 /* KSO03 */                 \
-	NPCX_ALT_GPIO_1_7 /* KSO02 */                 \
-	NPCX_ALT_GPIO_2_0 /* KSO01 */                 \
-	NPCX_ALT_GPIO_2_1 /* KSO00 */                 \
-	NPCX_ALT_GPIO_2_2 /* KSI7 */                  \
-	NPCX_ALT_GPIO_2_3 /* KSI6 */                  \
-	NPCX_ALT_GPIO_2_4 /* KSI5 */                  \
-	NPCX_ALT_GPIO_2_5 /* KSI4 */                  \
-	NPCX_ALT_GPIO_2_6 /* KSI3 */                  \
-	NPCX_ALT_GPIO_2_7 /* KSI2 */                  \
-	NPCX_ALT_GPIO_3_0 /* KSI1 */                  \
-	NPCX_ALT_GPIO_3_1 /* KSI0 */                  \
-	NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */              \
-	NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */         \
-	NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */              \
-	NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */         \
-	NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */              \
-	NPCX_ALT_GPIO_4_1 /* ADC4  */                 \
-	NPCX_ALT_GPIO_4_2 /* ADC3  */                 \
-	NPCX_ALT_GPIO_4_3 /* ADC2  */                 \
-	NPCX_ALT_GPIO_4_4 /* ADC1  */                 \
-	NPCX_ALT_GPIO_4_5 /* ADC0  */                 \
-	NPCX_ALT_GPIO_6_0 /* PWM7 */                  \
-	NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */              \
-	NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */              \
-	NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */           \
-	NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */          \
-	NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */              \
-	NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */              \
-	NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */              \
-	NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */            \
-	NPCX_ALT_GPIO_8_0 /* PWM3 */                  \
-	NPCX_ALT_GPIO_8_2 /* KSO14 */                 \
-	NPCX_ALT_GPIO_8_3 /* KSO15 */                 \
-	NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */           \
-	NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */              \
-	NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */              \
-	NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */              \
-	NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */              \
-	NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */              \
-	NPCX_ALT_GPIO_9_5 /* SPIP_MISO */             \
-	NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */             \
-	NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */             \
-	NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */     \
-	NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */     \
-	NPCX_ALT_GPIO_B_1 /* KSO17 */                 \
-	NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */              \
-	NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */              \
-	NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */              \
-	NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */              \
-	NPCX_ALT_GPIO_B_6 /* PWM4 */                  \
-	NPCX_ALT_GPIO_B_7 /* PWM5 */                  \
-	NPCX_ALT_GPIO_C_0 /* PWM6 */                  \
-	NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */              \
-	NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */       \
-	NPCX_ALT_GPIO_C_3 /* PWM0 */                  \
-	NPCX_ALT_GPIO_C_4 /* PWM2 */                  \
-	NPCX_ALT_GPIO_C_7 /* ADC11 */                 \
-	NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */              \
-	NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */              \
-	NPCX_ALT_GPIO_D_2 /* PSL_IN1 */               \
-	NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */            \
-	NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */           \
-	NPCX_ALT_GPIO_D_7 /* PSL_GPO */               \
-	NPCX_ALT_GPIO_E_0 /* ADC10 */                 \
-	NPCX_ALT_GPIO_E_1 /* ADC7  */                 \
-	NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */              \
-	NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */              \
-	NPCX_ALT_GPIO_F_0 /* ADC9  */                 \
-	NPCX_ALT_GPIO_F_1 /* ADC8  */                 \
-	NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */              \
-	NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */              \
-	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
-	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
-}
-
-/*****************************************************************************/
-/* Macro functions for Low-Voltage mapping table */
-
-/* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
-
-/* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
-
-/* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
-
-/* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
-
-/* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
-
-/* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
-
-/* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
-
-#endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */
diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
deleted file mode 100644
index 2d0b2b4e9b..0000000000
--- a/chip/npcx/gpio_chip.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GPIO_CHIP_H
-#define __CROS_EC_GPIO_CHIP_H
-
-struct npcx_wui {
-	uint8_t table : 2;
-	uint8_t group : 3;
-	uint8_t bit   : 3;
-};
-
-/* Macros to initialize the MIWU mapping table. */
-#define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index
-#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \
-						.bit = idx })
-#define WUI_INT(tbl, grp)  WUI(tbl, grp, 0)
-#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \
-				      .bit = 0 })
-
-/* Macros to initialize the alternative and low voltage mapping table. */
-#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0})
-#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \
-							.bit = pin, .valid = 1})
-
-#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
-#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
-#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \
-			.alt = (_alt) },
-
-#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
-				     NPCX_LVOL_CTRL_##ctrl##_1, \
-				     NPCX_LVOL_CTRL_##ctrl##_2, \
-				     NPCX_LVOL_CTRL_##ctrl##_3, \
-				     NPCX_LVOL_CTRL_##ctrl##_4, \
-				     NPCX_LVOL_CTRL_##ctrl##_5, \
-				     NPCX_LVOL_CTRL_##ctrl##_6, \
-				     NPCX_LVOL_CTRL_##ctrl##_7, }
-
-/**
- * Switch NPCX UART pins back to normal GPIOs.
- */
-void npcx_uart2gpio(void);
-
-/**
- * Switch NPCX UART pins to UART mode (depending on the currently selected
- * pad, see uart.c).
- */
-void npcx_gpio2uart(void);
-
-/* Set input buffer of all 1.8v i2c ports. */
-void gpio_enable_1p8v_i2c_wake_up_input(int enable);
-
-void gpio_interrupt(struct npcx_wui wui_int);
-
-/*
- * Include the MIWU, alternative and low-Voltage macro functions for GPIOs
- * depends on Nuvoton chip series.
- */
-#if defined(CHIP_FAMILY_NPCX5)
-#include "gpio_chip-npcx5.h"
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "gpio_chip-npcx7.h"
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "gpio_chip-npcx9.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_GPIO_CHIP_H */
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
deleted file mode 100644
index 0ba3ee59d6..0000000000
--- a/chip/npcx/header.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Booter header for Chrome EC.
- *
- * This header is used by Nuvoton EC Booter.
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "registers.h"
-
-/* Signature used by fw header */
-#define SIG_FW_EC           0x2A3B4D5E
-
-/* Definition used by error detection configuration */
-#define CHECK_CRC	    0x00
-#define CHECK_CHECKSUM	    0x01
-#define ERROR_DETECTION_EN  0x02
-#define ERROR_DETECTION_DIS 0x00
-
-/* Code RAM addresses use by header */
-/* Put FW at the begin of CODE RAM */
-#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
-
-/* TODO: It will be filled automatically by ECST */
-/* The entry point of reset handler (filled by ECST tool)*/
-#define FW_ENTRY_ADDR  0x100A8169
-
-/* Error detection addresses use by header (A offset relative to flash image) */
-#define ERRCHK_START_ADDR  0x0
-#define ERRCHK_END_ADDR    0x0
-
-/* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
-#define FW_SIZE            CONFIG_RO_SIZE
-
-/* FW Header used by NPCX5M5G Booter */
-struct __packed fw_header_t {
-	uint32_t anchor;         /* A constant used to verify FW header       */
-	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
-	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
-	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
-	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
-	uint32_t fw_load_addr;   /* Firmware load start address               */
-	uint32_t fw_entry;       /* Firmware entry point                      */
-	uint32_t err_detect_start_addr; /* FW error detect start address      */
-	uint32_t err_detect_end_addr;   /* FW error detect end address        */
-	uint32_t fw_length;      /* Firmware length in bytes                  */
-	uint8_t  flash_size;     /* Indicate SPI flash size                   */
-	uint8_t  reserved[26];   /* Reserved bytes                            */
-	uint32_t sig_header;     /* The CRC signature of the firmware header  */
-	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
-} __aligned(1);
-
-__keep  __attribute__ ((section(".header")))
-const struct fw_header_t fw_header = {
-	/* 00 */ SIG_FW_EC,
-	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
-	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
-	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
-	/* 08 */ 0x00,   /* Disable CRC check functionality */
-	/* 09 */ FW_START_ADDR,
-	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
-	/* 11 */ ERRCHK_START_ADDR,
-	/* 15 */ ERRCHK_END_ADDR,
-	/* 19 */ FW_SIZE,/* Filling by ECST tool */
-	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
-	/* 1E-3F Other fields are filled by ECST tool or reserved         */
-};
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
deleted file mode 100644
index 92f9843d09..0000000000
--- a/chip/npcx/hwtimer.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "math_util.h"
-#include "registers.h"
-#include "console.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Depth of event timer */
-#define TICK_EVT_DEPTH         16 /* Depth of event timer Unit: bits */
-#define TICK_EVT_INTERVAL      BIT(TICK_EVT_DEPTH) /* Unit: us */
-#define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */
-#define TICK_EVT_MAX_CNT     (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
-
-/* Time when event will be expired unit:us */
-static volatile uint32_t evt_expired_us;
-/* 32-bits event counter */
-static volatile uint32_t evt_cnt;
-/* Debugger information */
-#if DEBUG_TMR
-static volatile uint32_t evt_cnt_us_dbg;
-static volatile uint32_t cur_cnt_us_dbg;
-#endif
-
-#if !(DEBUG_TMR)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-#endif
-
-/*****************************************************************************/
-/* Internal functions */
-void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
-{
-	/* Select which clock to use for this timer */
-	UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL,
-			source != ITIM_SOURCE_CLOCK_APB2);
-
-	/* Clear timeout status */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS);
-
-	/* ITIM timeout interrupt enable */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_IE);
-
-	/* ITIM timeout wake-up enable */
-	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_WUE);
-}
-
-/*****************************************************************************/
-/* HWTimer event handlers */
-void __hw_clock_event_set(uint32_t deadline)
-{
-	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND);
-	int32_t  evt_cnt_us;
-	/* Is deadline min value? */
-	if (evt_expired_us != 0 && evt_expired_us < deadline)
-		return;
-
-	/* mark min event value */
-	evt_expired_us = deadline;
-	evt_cnt_us = deadline - __hw_clock_source_read();
-#if DEBUG_TMR
-	evt_cnt_us_dbg = deadline - __hw_clock_source_read();
-#endif
-	/* Deadline is behind current timer */
-	if (evt_cnt_us < 0)
-		evt_cnt_us = 1;
-
-	/* Event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/*
-	 * ITIM count down : event expired : Unit: 1/32768 sec
-	 * It must exceed evt_expired_us for process_timers function
-	 */
-	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick);
-	if (evt_cnt > TICK_EVT_MAX_CNT) {
-		CPRINTS("Event overflow! 0x%08x, us is %d",
-				evt_cnt, evt_cnt_us);
-		evt_cnt = TICK_EVT_MAX_CNT;
-	}
-
-	/* Wait for module disable to take effect before updating count */
-	while (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
-		;
-
-	NPCX_ITCNT(ITIM_EVENT_NO) = MAX(evt_cnt, 1);
-
-	/* Event module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Wait for module enable */
-	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN))
-		;
-
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_EVENT_NO));
-}
-
-/* Returns the time-stamp of the next programmed event */
-uint32_t __hw_clock_event_get(void)
-{
-	if (evt_expired_us)
-		return evt_expired_us;
-	else /* No events. Give maximum deadline */
-		return EVT_MAX_EXPIRED_US;
-}
-
-/* Get current counter value of event timer */
-uint16_t __hw_clock_event_count(void)
-{
-	uint16_t cnt, cnt2;
-
-	cnt = NPCX_ITCNT(ITIM_EVENT_NO);
-	/* Wait for two consecutive equal values are read */
-	while ((cnt2 = NPCX_ITCNT(ITIM_EVENT_NO)) != cnt)
-		cnt = cnt2;
-
-	return cnt;
-}
-
-/* Returns time delay cause of deep idle */
-uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt)
-{
-	fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK);
-	uint32_t sleep_time;
-	uint16_t cnt = __hw_clock_event_count();
-
-	/* Event has been triggered but timer ISR doesn't handle it */
-	if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS))
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick);
-	/* Event hasn't been triggered */
-	else
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) *
-				       evt_tick);
-
-	return sleep_time;
-}
-
-/* Cancel the next event programmed by __hw_clock_event_set */
-void __hw_clock_event_clear(void)
-{
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Disable interrupt of Event */
-	task_disable_irq(ITIM_INT(ITIM_EVENT_NO));
-
-	/* Clear event parameters */
-	evt_expired_us = 0;
-	evt_cnt = 0;
-}
-
-/* Irq for hwtimer event */
-void __hw_clock_event_irq(void)
-{
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-
-	/* Disable interrupt of event */
-	task_disable_irq(ITIM_INT(ITIM_EVENT_NO));
-
-	/* Clear timeout status for event */
-	SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS);
-
-	/* Clear event parameters */
-	evt_expired_us = 0;
-	evt_cnt = 0;
-
-	/* handle upper driver */
-	process_timers(0);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Set event for ITIM32 after process_timers() since no events set if
-	 * event's deadline is over 32 bits but current source clock isn't.
-	 * ITIM32 is based on apb2 and ec won't wake-up in deep-idle even if it
-	 * expires.
-	 */
-	if (evt_expired_us == 0)
-		__hw_clock_event_set(EVT_MAX_EXPIRED_US);
-#endif
-
-}
-DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3);
-
-/*****************************************************************************/
-/* HWTimer tick handlers */
-
-/* Modify preload counter of source clock. */
-void hw_clock_source_set_preload(uint32_t ts, uint8_t clear)
-{
-	/* ITIM32 module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_CKSEL);
-
-	/* Set preload counter to current time */
-	NPCX_ITCNT_SYSTEM = TICK_ITIM32_MAX_CNT - ts;
-	/* Clear timeout status or not */
-	if (clear)
-		SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS);
-	/* ITIM32 module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-}
-
-/* Returns the value of the free-running counter used as clock. */
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t cnt, cnt2;
-
-	cnt = NPCX_ITCNT_SYSTEM;
-	/*
-	 * Wait for two consecutive equal values are read no matter
-	 * ITIM's source clock is APB2 or 32K since mux's delay.
-	 */
-	while ((cnt2 = NPCX_ITCNT_SYSTEM) != cnt)
-		cnt = cnt2;
-
-#if DEBUG_TMR
-	cur_cnt_us_dbg = TICK_ITIM32_MAX_CNT - cnt;
-#endif
-	return TICK_ITIM32_MAX_CNT - cnt;
-}
-
-/* Override the current value of the hardware counter */
-void __hw_clock_source_set(uint32_t ts)
-{
-#if DEBUG_TMR
-	cur_cnt_us_dbg = TICK_ITIM32_MAX_CNT - ts;
-#endif
-	hw_clock_source_set_preload(ts, 0);
-}
-
-/* Irq for hwtimer tick */
-void __hw_clock_source_irq(void)
-{
-	/* Is timeout trigger trigger? */
-	if (IS_BIT_SET(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS)) {
-		/* Restore ITIM32 preload counter value to maximum value */
-		hw_clock_source_set_preload(0, 1);
-		/* 32-bits timer count overflow */
-		process_timers(1);
-
-	} else { /* Handle soft trigger */
-		process_timers(0);
-#ifdef CONFIG_LOW_POWER_IDLE
-		/* Set event for ITIM32. Please see above for detail */
-		if (evt_expired_us == 0)
-			__hw_clock_event_set(EVT_MAX_EXPIRED_US);
-#endif
-	}
-}
-DECLARE_IRQ(ITIM_INT(ITIM_SYSTEM_NO), __hw_clock_source_irq, 3);
-
-/* Handle ITIM32 overflow if interrupt is disabled */
-void __hw_clock_handle_overflow(uint32_t clksrc_high)
-{
-	timestamp_t newtime;
-
-	/* Overflow occurred? */
-	if (!IS_BIT_SET(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS))
-		return;
-
-	/* Clear timeout status */
-	SET_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_TO_STS);
-
-	/*
-	 * Restore ITIM32 preload counter value to maximum and execute
-	 * process_timers() later in ISR by trigger software interrupt in
-	 * force_time().
-	 */
-	newtime.le.hi = clksrc_high + 1;
-	newtime.le.lo = 0;
-	force_time(newtime);
-}
-
-static void update_prescaler(void)
-{
-	/*
-	 * prescaler to time tick
-	 * Ttick_unit = (PRE_8+1) * Tapb2_clk
-	 * PRE_8 = (Ttick_unit/Tapb2_clk) -1
-	 */
-	NPCX_ITPRE(ITIM_SYSTEM_NO)  = (clock_get_apb2_freq() / SECOND) - 1;
-	/* Set event tick unit = 1/32768 sec */
-	NPCX_ITPRE(ITIM_EVENT_NO) = 0;
-
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-void __hw_early_init_hwtimer(uint32_t start_t)
-{
-	/*
-	 * 1. Use ITIM16-1 as internal time reading
-	 * 2. Use ITIM16-2 for event handling
-	 */
-
-	/* Enable clock for ITIM peripheral */
-	clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* init tick & event timer first */
-	init_hw_timer(ITIM_SYSTEM_NO,  ITIM_SOURCE_CLOCK_APB2);
-	init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K);
-
-	/* Set initial prescaler */
-	update_prescaler();
-
-	hw_clock_source_set_preload(start_t, 1);
-}
-
-/* Note that early_init_hwtimer() has already executed by this point */
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * Override the count with the start value now that counting has
-	 * started. Note that we may have already called this function from
-	 * gpio_pre_init(), but only in the case where we expected a reset, so
-	 * we should not get here in that case.
-	 */
-	__hw_early_init_hwtimer(start_t);
-
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_SYSTEM_NO));
-
-	return ITIM_INT(ITIM_SYSTEM_NO);
-}
diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h
deleted file mode 100644
index 987f3b52bd..0000000000
--- a/chip/npcx/hwtimer_chip.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific hwtimer module for Chrome EC */
-
-#ifndef __CROS_EC_HWTIMER_CHIP_H
-#define __CROS_EC_HWTIMER_CHIP_H
-
-/* Use ITIM32 as main hardware timer */
-#define TICK_ITIM32_MAX_CNT  0xFFFFFFFF
-/* Maximum deadline of event */
-#define EVT_MAX_EXPIRED_US   TICK_ITIM32_MAX_CNT
-
-/* Clock source for ITIM16 */
-enum ITIM_SOURCE_CLOCK_T {
-	ITIM_SOURCE_CLOCK_APB2 = 0,
-	ITIM_SOURCE_CLOCK_32K  = 1,
-};
-
-/**
- * Initialise a hardware timer
- *
- * Select the source clock for a timer and prepare it for use.
- *
- * @param itim_no	Timer number to init (enum ITIM_MODULE_T)
- * @param source	Source for timer clock (enum ITIM_SOURCE_CLOCK_T)
- */
-void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source);
-
-/* Returns the counter value of event timer */
-uint16_t __hw_clock_event_count(void);
-
-/* Returns time delay because of deep idle */
-uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt);
-
-/* Handle ITIM32 overflow if interrupt is disabled */
-void __hw_clock_handle_overflow(uint32_t clksrc_high);
-
-/**
- * Set up the timer for use before the task system is available
- *
- * @param start_t	Value to assign to the counter
- */
-void __hw_early_init_hwtimer(uint32_t start_t);
-
-#endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c
deleted file mode 100644
index 6b78fd53f9..0000000000
--- a/chip/npcx/i2c-npcx5.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module driver depends on chip series for Chrome EC */
-
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-
-	return (port == NPCX_I2C_PORT0_0) ? 0 : port - 1;
-}
-
-void i2c_select_port(int port)
-{
-	/*
-	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
-	 * use port 0.
-	 */
-	if (port > NPCX_I2C_PORT0_1)
-		return;
-
-	/* Select IO pins for multi-ports I2C controllers */
-	UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL,
-			(port == NPCX_I2C_PORT0_1));
-}
-
-int i2c_is_raw_mode(int port)
-{
-	int bit = (port > NPCX_I2C_PORT0_1) ? ((port - 1) * 2) : port;
-
-	if (IS_BIT_SET(NPCX_DEVALT(2), bit))
-		return 0;
-	else
-		return 1;
-}
-
diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c
deleted file mode 100644
index 3f27aff49e..0000000000
--- a/chip/npcx/i2c-npcx7.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C module driver depends on chip series for Chrome EC */
-
-#include "common.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-int i2c_port_to_controller(int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return -1;
-
-	if (port <= NPCX_I2C_PORT3_0)
-		return port;
-#ifndef NPCX_PSL_MODE_SUPPORT
-	else if (port == NPCX_I2C_PORT4_0)
-		return 4;
-#endif
-	else /* If port >= NPCX_I2C_PORT4_1 */
-		return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2);
-}
-
-void i2c_select_port(int port)
-{
-	/* Only I2C 4/5/6 have multiple ports in series npcx7 */
-	if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0)
-		return;
-	/* Select I2C ports for the same controller */
-	else if (port <= NPCX_I2C_PORT4_1) {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
-			(port == NPCX_I2C_PORT4_1));
-	} else if (port <= NPCX_I2C_PORT5_1) {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
-			(port == NPCX_I2C_PORT5_1));
-	} else {
-		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
-			(port == NPCX_I2C_PORT6_1));
-	}
-}
-
-int i2c_is_raw_mode(int port)
-{
-	int group, bit;
-
-	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
-			port == NPCX_I2C_PORT6_1) {
-		group = 6;
-		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
-	} else {
-		group = 2;
-		if (port <= NPCX_I2C_PORT3_0)
-			bit = 2 * port;
-		else
-			bit = I2C_PORT_COUNT - port;
-	}
-
-	if (IS_BIT_SET(NPCX_DEVALT(group), bit))
-		return 0;
-	else
-		return 1;
-}
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
deleted file mode 120000
index b1b16a3198..0000000000
--- a/chip/npcx/i2c-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
deleted file mode 100644
index 26935f778f..0000000000
--- a/chip/npcx/i2c.c
+++ /dev/null
@@ -1,1224 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C port module for Chrome EC */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2c_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if !(DEBUG_I2C)
-#define CPUTS(...)
-#define CPRINTS(...)
-#define CPRINTF(...)
-#else
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#endif
-
-/* Timeout for device should be available after reset (SMBus spec. unit:ms) */
-#define I2C_MAX_TIMEOUT 35
-/*
- * Timeout for SCL held to low by peripheral device. (SMBus spec. unit:ms).
- * Some I2C devices may violate this timing and clock stretch for longer.
- * TODO: Consider increasing this timeout.
- */
-#define I2C_MIN_TIMEOUT 25
-
-/*
- * I2C module that supports FIFO mode has 32 bytes Tx FIFO and
- * 32 bytes Rx FIFO.
- */
-#define NPCX_I2C_FIFO_MAX_SIZE    32
-
-/* Macro functions of I2C */
-#define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START)
-#define I2C_STOP(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
-#define I2C_NACK(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
-/* I2C module automatically stall bus after sending peripheral address */
-#define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE)
-#define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data)
-#define I2C_READ_BYTE(ctrl, data)  (data = NPCX_SMBSDA(ctrl))
-#define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F)
-#define I2C_TX_FIFO_AVAILABLE(ctrl) \
-		(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
-
-#define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F)
-#define I2C_RX_FIFO_AVAILABLE(ctrl) \
-			(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
-/* Drive the SCL signal to low */
-#define I2C_SCL_STALL(ctrl) \
-		(NPCX_SMBCTL3(ctrl) = \
-			(NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
-/*
- * Release the SCL signal to be pulled up to high level.
- * Note: The SCL might be still driven low either by I2C module or external
- * devices connected to ths bus.
- */
-#define I2C_SCL_FREE(ctrl) \
-		(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
-
-/* Error values that functions can return */
-enum smb_error {
-	SMB_OK = 0,                 /* No error                           */
-	SMB_CH_OCCUPIED,            /* Channel is already occupied        */
-	SMB_MEM_POOL_INIT_ERROR,    /* Memory pool initialization error   */
-	SMB_BUS_FREQ_ERROR,         /* SMbus freq was not valid           */
-	SMB_INVLAID_REGVALUE,       /* Invalid SMbus register value       */
-	SMB_UNEXIST_CH_ERROR,       /* Channel does not exist             */
-	SMB_NO_SUPPORT_PTL,         /* Not support SMBus Protocol         */
-	SMB_BUS_ERROR,              /* Encounter bus error                */
-	SMB_NO_ADDRESS_MATCH,       /* No peripheral address match        */
-				    /*  (Controller Mode)                 */
-	SMB_READ_DATA_ERROR,        /* Read data for SDA error            */
-	SMB_READ_OVERFLOW_ERROR,    /* Read data over than we predict     */
-	SMB_TIMEOUT_ERROR,          /* Timeout expired                    */
-	SMB_MODULE_ISBUSY,          /* Module is occupied by other device */
-	SMB_BUS_BUSY,               /* SMBus is occupied by other device  */
-};
-
-/*
- * Internal SMBus Interface driver states values, which reflect events
- * which occurred on the bus
- */
-enum smb_oper_state_t {
-	SMB_IDLE,
-	SMB_CONTROLLER_START,
-	SMB_WRITE_OPER,
-	SMB_READ_OPER,
-	SMB_FAKE_READ_OPER,
-	SMB_REPEAT_START,
-	SMB_WRITE_SUSPEND,
-	SMB_READ_SUSPEND,
-};
-
-/* I2C controller state data */
-struct i2c_status {
-	int                   flags;     /* Flags (I2C_XFER_*) */
-	const uint8_t        *tx_buf;    /* Entry pointer of transmit buffer */
-	uint8_t              *rx_buf;    /* Entry pointer of receive buffer  */
-	uint16_t              sz_txbuf;  /* Size of Tx buffer in bytes */
-	uint16_t              sz_rxbuf;  /* Size of rx buffer in bytes */
-	uint16_t              idx_buf;   /* Current index of Tx/Rx buffer */
-	uint16_t              addr_flags;/* Target address */
-	enum smb_oper_state_t oper_state;/* Smbus operation state */
-	enum smb_error        err_code;  /* Error code */
-	int                   task_waiting; /* Task waiting on controller */
-	uint32_t              timeout_us;/* Transaction timeout */
-	uint16_t              kbps;      /* Speed */
-};
-/* I2C controller state data array */
-static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
-
-/* I2C timing setting */
-struct i2c_timing {
-	uint8_t clock; /* I2C source clock. (Unit: MHz)*/
-	uint8_t HLDT;  /* I2C hold-time. (Unit: clocks) */
-	uint8_t k1;    /* k1 = SCL low-time (Unit: clocks) */
-	uint8_t k2;    /* k2 = SCL high-time (Unit: clocks) */
-};
-
-/* I2C timing setting array of 400K & 1M Hz */
-static const struct i2c_timing i2c_400k_timings[] = {
-	{20,  7, 32, 22},
-	{15,  7, 24, 18},};
-const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings);
-
-static const struct i2c_timing i2c_1m_timings[] = {
-	{20, 7, 16, 10},
-	{15, 7, 14, 10},};
-const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
-
-/* IRQ for each port */
-const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = {
-		NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-		NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT);
-
-static void i2c_init_bus(int controller)
-{
-	/* Enable FIFO mode */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		SET_BIT(NPCX_SMBFIF_CTL(controller), NPCX_SMBFIF_CTL_FIFO_EN);
-
-	/* Enable module - before configuring CTL1 */
-	SET_BIT(NPCX_SMBCTL2(controller), NPCX_SMBCTL2_ENABLE);
-
-	/* Enable SMB interrupt and New Address Match interrupt source */
-	SET_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_NMINTE);
-	SET_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_INTEN);
-}
-
-int i2c_bus_busy(int controller)
-{
-	return IS_BIT_SET(NPCX_SMBCST(controller), NPCX_SMBCST_BB) ? 1 : 0;
-}
-
-static int i2c_wait_stop_completed(int controller, int timeout)
-{
-	if (timeout <= 0)
-		return EC_ERROR_INVAL;
-
-	/* Wait till STOP condition is generated. ie. I2C bus is idle. */
-	while (timeout > 0) {
-		if (!IS_BIT_SET(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STOP))
-			break;
-		if (--timeout > 0)
-			msleep(1);
-	}
-
-	if (timeout)
-		return EC_SUCCESS;
-	else
-		return EC_ERROR_TIMEOUT;
-}
-
-static void i2c_abort_data(int controller)
-{
-	/* Clear NEGACK, STASTR and BER bits */
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR);
-	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
-
-	/* Wait till STOP condition is generated */
-	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT)
-			!= EC_SUCCESS) {
-		cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller);
-		/* Clear BB (BUS BUSY) bit */
-		SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
-		return;
-	}
-
-	/* Clear BB (BUS BUSY) bit */
-	SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
-}
-
-static int i2c_reset(int controller)
-{
-	uint16_t timeout = I2C_MAX_TIMEOUT;
-
-	/* Disable the SMB module */
-	CLEAR_BIT(NPCX_SMBCTL2(controller), NPCX_SMBCTL2_ENABLE);
-
-	while (--timeout) {
-		/* WAIT FOR SCL & SDA IS HIGH */
-		if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL)
-		  && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
-			break;
-		msleep(1);
-	}
-
-	if (timeout == 0) {
-		cprintf(CC_I2C, "Reset i2c %02x fail!\n", controller);
-		return 0;
-	}
-
-	/* Init the SMB module again */
-	i2c_init_bus(controller);
-	return 1;
-}
-
-static void i2c_select_bank(int controller, int bank)
-{
-	if (bank)
-		SET_BIT(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_BNK_SEL);
-	else
-		CLEAR_BIT(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_BNK_SEL);
-}
-
-static void i2c_stall_bus(int controller, int stall)
-{
-	i2c_select_bank(controller, 0);
-	/*
-	 * Enable the writing to SCL_LVL and SDA_LVL bit in
-	 * SMBnCTL3 register. Then, firmware can set SCL_LVL to 0 to
-	 * stall the bus when needed. Note: this register should be
-	 * accessed when bank = 0.
-	 */
-	SET_BIT(NPCX_SMBCTL4(controller), NPCX_SMBCTL4_LVL_WE);
-	if (stall)
-		I2C_SCL_STALL(controller);
-	else
-		I2C_SCL_FREE(controller);
-	/*
-	 * Disable the writing to SCL_LVL and SDA_LVL bit in
-	 * SMBnCTL3 register. It will prevent form changing the level of
-	 * SCL/SDA when touching other bits in SMBnCTL3 register.
-	 */
-	CLEAR_BIT(NPCX_SMBCTL4(controller), NPCX_SMBCTL4_LVL_WE);
-	i2c_select_bank(controller, 1);
-}
-
-static void i2c_recovery(int controller, volatile struct i2c_status *p_status)
-{
-	cprintf(CC_I2C,
-		"i2c %d recovery! error code is %d, current state is %d\n",
-		controller, p_status->err_code, p_status->oper_state);
-
-	/* Make sure the bus is not stalled before exit. */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_stall_bus(controller, 0);
-
-	/* Abort data, wait for STOP condition completed. */
-	i2c_abort_data(controller);
-
-	/* Reset i2c controller by re-enable i2c controller*/
-	if (!i2c_reset(controller))
-		return;
-
-	/* Restore to idle status */
-	p_status->oper_state = SMB_IDLE;
-}
-
-/*
- * This function can be called in either single-byte mode or FIFO mode.
- * In single-byte mode - it always write 1 byte to SMBSDA register at one time.
- * In FIFO mode - write as many as available bytes in FIFO at one time.
- */
-static void i2c_fifo_write_data(int controller)
-{
-	int len, fifo_avail, i;
-
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	len = 1;
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-		len = p_status->sz_txbuf - p_status->idx_buf;
-		fifo_avail = I2C_TX_FIFO_AVAILABLE(controller);
-		len = MIN(len, fifo_avail);
-	}
-	for (i = 0; i < len; i++) {
-		I2C_WRITE_BYTE(controller,
-				p_status->tx_buf[p_status->idx_buf++]);
-		CPRINTF("%02x ",
-				p_status->tx_buf[p_status->idx_buf - 1]);
-	}
-	CPRINTF("\n");
-}
-
-enum smb_error i2c_controller_transaction(int controller)
-{
-	/* Set i2c mode to object */
-	int events = 0;
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* Switch to bank 1 to access I2C FIO registers */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_select_bank(controller, 1);
-
-	/* Assign current SMB status of controller */
-	if (p_status->oper_state == SMB_IDLE) {
-		/* New transaction */
-		p_status->oper_state = SMB_CONTROLLER_START;
-		/* Clear FIFO and status bit */
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			NPCX_SMBFIF_CTS(controller) =
-				BIT(NPCX_SMBFIF_CTS_RXF_TXE) |
-				BIT(NPCX_SMBFIF_CTS_CLR_FIFO);
-		}
-	} else if (p_status->oper_state == SMB_WRITE_SUSPEND) {
-		if (p_status->sz_txbuf == 0) {
-			/* Read bytes from next transaction */
-			p_status->oper_state = SMB_REPEAT_START;
-			CPUTS("R");
-		} else {
-			/* Continue to write the other bytes */
-			p_status->oper_state = SMB_WRITE_OPER;
-			CPRINTS("-W");
-			/*
-			 * This function can be called in either single-byte
-			 * mode or FIFO mode.
-			 */
-			i2c_fifo_write_data(controller);
-		}
-	} else if (p_status->oper_state == SMB_READ_SUSPEND) {
-		if (!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			/*
-			 * Do extra read if read length is 1 and I2C_XFER_STOP
-			 * is set simultaneously.
-			 */
-			if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP)) {
-				/*
-				 * Since SCL is released after reading last
-				 * byte from previous transaction, adding a
-				 * extra byte for next transaction which let
-				 * ec sets NACK bit in time is necessary.
-				 * Or i2c controller cannot generate STOP
-				 * when the last byte is ACK during receiving.
-				 */
-				p_status->sz_rxbuf++;
-				p_status->oper_state = SMB_FAKE_READ_OPER;
-			} else
-				/*
-				 * Need to read the other bytes from
-				 * next transaction
-				 */
-				p_status->oper_state = SMB_READ_OPER;
-		}
-	} else
-		cprintf(CC_I2C, "Unexpected i2c state machine! %d\n",
-				p_status->oper_state);
-
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-		if (p_status->sz_rxbuf > 0) {
-			if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) {
-				/* Set RX threshold = FIFO_MAX_SIZE */
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
-			} else {
-				/*
-				 * set RX threshold = remaining data bytes
-				 * (it should be <= FIFO_MAX_SIZE)
-				 */
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						p_status->sz_rxbuf);
-				/*
-				 * Set LAST bit generate the NACK at the
-				 * last byte of the data group in FIFO
-				 */
-				if (p_status->flags & I2C_XFER_STOP) {
-					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
-				}
-			}
-
-			/* Free the stalled SCL signal */
-			if (p_status->oper_state == SMB_READ_SUSPEND) {
-				p_status->oper_state = SMB_READ_OPER;
-				i2c_stall_bus(controller, 0);
-			}
-		}
-	}
-
-	/* Generate a START condition */
-	if (p_status->oper_state == SMB_CONTROLLER_START ||
-			p_status->oper_state == SMB_REPEAT_START) {
-		I2C_START(controller);
-		CPUTS("ST");
-	}
-
-	/* Enable event and error interrupts */
-	task_enable_irq(i2c_irqs[controller]);
-
-	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE,
-			p_status->timeout_us);
-
-	/* Disable event and error interrupts */
-	task_disable_irq(i2c_irqs[controller]);
-
-	/*
-	 * Accessing FIFO register is only needed during transaction.
-	 * Switch back to bank 0 at the end of transaction
-	 */
-	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-		i2c_select_bank(controller, 0);
-
-	/*
-	 * If Stall-After-Start mode is still enabled since NACK or BUS error
-	 * occurs, disable it.
-	 */
-	if (IS_BIT_SET(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE))
-		CLEAR_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE);
-
-	/* Handle bus timeout */
-	if ((events & TASK_EVENT_I2C_IDLE) == 0) {
-		p_status->err_code = SMB_TIMEOUT_ERROR;
-		/* Recovery I2C controller */
-		i2c_recovery(controller, p_status);
-	}
-	/* Recovery bus if we encounter bus error */
-	else if (p_status->err_code == SMB_BUS_ERROR)
-		i2c_recovery(controller, p_status);
-
-	/* Wait till STOP condition is generated for normal transaction */
-	if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller,
-			I2C_MIN_TIMEOUT) != EC_SUCCESS) {
-		cprintf(CC_I2C,
-			"STOP fail! scl %02x is held by slave device!\n",
-			controller);
-		p_status->err_code = SMB_TIMEOUT_ERROR;
-	}
-
-	return p_status->err_code;
-}
-
-/* Issue stop condition if necessary and end transaction */
-void i2c_done(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* need to STOP or not */
-	if (p_status->flags & I2C_XFER_STOP) {
-		/* Issue a STOP condition on the bus */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-			NPCX_SMBFIF_CTS(controller) =
-						BIT(NPCX_SMBFIF_CTS_RXF_TXE);
-
-		/* Clear SDAST by writing mock byte */
-		I2C_WRITE_BYTE(controller, 0xFF);
-	}
-
-	/* Set error code */
-	p_status->err_code = SMB_OK;
-	/* Set SMB status if we need stall bus */
-	p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_WRITE_SUSPEND;
-	/*
-	 * Disable interrupt for i2c controller stall SCL
-	 * and forbid SDAST generate interrupt
-	 * until common layer start other transactions
-	 */
-	if (p_status->oper_state == SMB_WRITE_SUSPEND)
-		task_disable_irq(i2c_irqs[controller]);
-
-	/* Notify upper layer */
-	task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-	CPUTS("-END");
-}
-
-static void i2c_handle_receive(int controller)
-{
-	uint8_t data;
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* last byte is about to be read - end of transaction */
-	if (p_status->idx_buf == (p_status->sz_rxbuf - 1)) {
-		/* need to STOP or not */
-		if (p_status->flags & I2C_XFER_STOP) {
-			/* Stop should set before reading last byte */
-			I2C_STOP(controller);
-			CPUTS("-SP");
-		} else {
-			/*
-			 * Disable interrupt before i2c controller read SDA
-			 * reg (stall SCL) and forbid SDAST generate
-			 * interrupt until starting other transactions
-			 */
-			task_disable_irq(i2c_irqs[controller]);
-		}
-	}
-	/* Check if byte-before-last is about to be read */
-	else if (p_status->idx_buf == (p_status->sz_rxbuf - 2)) {
-		/*
-		 * Set nack before reading byte-before-last,
-		 * so that nack will be generated after receive
-		 * of last byte
-		 */
-		if (p_status->flags & I2C_XFER_STOP) {
-			I2C_NACK(controller);
-			CPUTS("-GNA");
-		}
-	}
-
-	/* Read data for SMBSDA */
-	I2C_READ_BYTE(controller, data);
-	CPRINTS("-R(%02x)", data);
-
-	/* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */
-	if (p_status->oper_state == SMB_FAKE_READ_OPER &&
-			p_status->idx_buf == (p_status->sz_rxbuf - 1))
-		p_status->idx_buf++;
-	else
-		p_status->rx_buf[p_status->idx_buf++] = data;
-
-	/* last byte is read - end of transaction */
-	if (p_status->idx_buf == p_status->sz_rxbuf) {
-		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
-		/* Set error code */
-		p_status->err_code = SMB_OK;
-		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-END");
-	}
-}
-
-static void i2c_fifo_read_data(int controller, uint8_t bytes_in_fifo)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	while (bytes_in_fifo--) {
-		uint8_t data;
-
-		data = NPCX_SMBSDA(controller);
-		p_status->rx_buf[p_status->idx_buf++] = data;
-		CPRINTF("%02x ", data);
-	}
-	CPRINTF("\n");
-}
-
-static void i2c_fifo_handle_receive(int controller)
-{
-	uint8_t bytes_in_fifo, remaining_bytes;
-
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/*
-	 * Clear RX_THST bit (RX-FIFO Threshold Status).
-	 * It is set when RX_BYTES = RX_THR after being RX_BYTES < RX_THR
-	 */
-	SET_BIT(NPCX_SMBRXF_STS(controller), NPCX_SMBRXF_STS_RX_THST);
-	SET_BIT(NPCX_SMBFIF_CTS(controller), NPCX_SMBFIF_CTS_RXF_TXE);
-
-	bytes_in_fifo = I2C_RX_FIFO_OCCUPIED(controller);
-	remaining_bytes = p_status->sz_rxbuf - p_status->idx_buf;
-	if (remaining_bytes - bytes_in_fifo <= 0) {
-		/*
-		 * Last byte is about to be read - end of transaction.
-		 * Stop should be set before reading last byte.
-		 */
-		if (p_status->flags & I2C_XFER_STOP) {
-			I2C_STOP(controller);
-			CPUTS("-FSP");
-		} else {
-			task_disable_irq(i2c_irqs[controller]);
-			/*
-			 * The I2C bus will be freed from stalled and continue
-			 * to recevie data when reading data from FIFO.
-			 * Pull SCL signal down to stall the bus manually.
-			 * SCL signal will be freed when it gets a new I2C
-			 * transaction call from common layer.
-			 */
-			i2c_stall_bus(controller, 1);
-		}
-
-		CPRINTS("-LFR");
-		i2c_fifo_read_data(controller, remaining_bytes);
-	} else {
-		CPRINTS("-FR");
-		/*
-		 * The I2C bus will be freed from stalled and continue to
-		 * recevie data when reading data from FIFO.
-		 * This may caue driver cannot set the new Rx threshold in time.
-		 * Manually stall SCL signal until the new Rx threshold is set.
-		 */
-		i2c_stall_bus(controller, 1);
-		i2c_fifo_read_data(controller, bytes_in_fifo);
-		remaining_bytes = p_status->sz_rxbuf - p_status->idx_buf;
-		if (remaining_bytes > 0) {
-			if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) {
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
-			} else {
-				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						remaining_bytes);
-				if (p_status->flags & I2C_XFER_STOP) {
-					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
-					CPRINTS("-FGNA");
-				}
-			}
-
-		}
-		i2c_stall_bus(controller, 0);
-
-	}
-	/* last byte is read - end of transaction */
-	if (p_status->idx_buf == p_status->sz_rxbuf) {
-		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
-		/* Set error code */
-		p_status->err_code = SMB_OK;
-		/* Notify upper layer of missing data */
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-END");
-	}
-
-}
-
-static void i2c_handle_sda_irq(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-	uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1;
-
-	/* 1 Issue Start is successful ie. write address byte */
-	if (p_status->oper_state == SMB_CONTROLLER_START
-			|| p_status->oper_state == SMB_REPEAT_START) {
-		/* Prepare address byte */
-		if (p_status->sz_txbuf == 0) {/* Receive mode */
-			p_status->oper_state = SMB_READ_OPER;
-			/*
-			 * Receiving one or zero bytes - stall bus after
-			 * START condition. If there's no peripheral
-			 * devices on bus, FW needn't to set ACK bit.
-			 */
-			if (p_status->sz_rxbuf < 2)
-				I2C_STALL(controller);
-
-			/* Write the address to the bus R bit*/
-			I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
-			CPRINTS("-ARR-0x%02x", addr_8bit);
-		} else {/* Transmit mode */
-			p_status->oper_state = SMB_WRITE_OPER;
-			/* Write the address to the bus W bit*/
-			I2C_WRITE_BYTE(controller, addr_8bit);
-			CPRINTS("-ARW-0x%02x", addr_8bit);
-		}
-		/* Completed handling START condition */
-		return;
-	}
-	/* 2 Handle controller write operation */
-	else if (p_status->oper_state == SMB_WRITE_OPER) {
-		/* all bytes have been written, in a pure write operation */
-		if (p_status->idx_buf == p_status->sz_txbuf) {
-			/*  no more message */
-			if (p_status->sz_rxbuf == 0)
-				i2c_done(controller);
-			/*
-			 * need to restart & send peripheral address
-			 * immediately
-			 */
-			else {
-				/*
-				 * Prepare address byte
-				 * and start to receive bytes
-				 */
-				p_status->oper_state = SMB_READ_OPER;
-				/* Reset index of buffer */
-				p_status->idx_buf = 0;
-
-				/*
-				 * Generate (Repeated) Start
-				 * upon next write to SDA
-				 */
-				I2C_START(controller);
-				CPUTS("-RST");
-				/*
-				 * Receiving one byte only - set NACK just
-				 * before writing address byte.
-				 * Set NACK (ACK bit in the SMBnCTL1 register)
-				 * only in the single-byte mode.
-				 * In FIFO mode, NACK is set via LAST bit
-				 * in the SMBnTXF_CTL register.
-				 */
-				if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP) &&
-					!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-					I2C_NACK(controller);
-					CPUTS("-GNA");
-				}
-				/* Write the address to the bus R bit*/
-				I2C_WRITE_BYTE(controller,
-					       (addr_8bit | 0x1));
-				CPUTS("-ARR");
-			}
-		}
-		/*
-		 * write next byte (not last byte and not peripheral
-		 * address)
-		 */
-		else {
-			/*
-			 * This function can be called in either single-byte
-			 * mode or FIFO mode.
-			 */
-			CPRINTS("-W");
-			i2c_fifo_write_data(controller);
-		}
-	}
-	/*
-	 * 3 Handle controller read operation (read or after a write
-	 * operation)
-	 */
-	else if (p_status->oper_state == SMB_READ_OPER ||
-			p_status->oper_state == SMB_FAKE_READ_OPER) {
-		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
-			i2c_fifo_handle_receive(controller);
-		else
-			i2c_handle_receive(controller);
-	}
-}
-
-static void i2c_controller_int_handler(int controller)
-{
-	volatile struct i2c_status *p_status = i2c_stsobjs + controller;
-
-	/* Condition 1 : A Bus Error has been identified */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_BER)) {
-		uint8_t __attribute__((unused)) data;
-		/* Generate a STOP condition */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear BER Bit */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-		/* Make sure peripheral doesn't hold bus by reading */
-		I2C_READ_BYTE(controller, data);
-
-		/* Set error code */
-		p_status->err_code = SMB_BUS_ERROR;
-		/* Notify upper layer */
-		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-BER");
-
-		/*
-		 * Disable smb's interrupts to forbid ec to enter ISR again
-		 * before executing error recovery.
-		 */
-		task_disable_irq(i2c_irqs[controller]);
-
-		/* return for executing error recovery immediately */
-		return;
-	}
-
-	/* Condition 2: A negative acknowledge has occurred */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_NEGACK)) {
-		/* Generate a STOP condition */
-		I2C_STOP(controller);
-		CPUTS("-SP");
-		/* Clear NEGACK Bit */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
-		/* Set error code */
-		p_status->err_code = SMB_NO_ADDRESS_MATCH;
-		/* Notify upper layer */
-		p_status->oper_state = SMB_IDLE;
-		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
-		CPUTS("-NA");
-	}
-
-	/* Condition 3: A Stall after START has occurred for READ-BYTE */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_STASTR)) {
-		CPUTS("-STL");
-
-		/* Disable Stall-After-Start mode first */
-		CLEAR_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE);
-
-		/*
-		 * Generate stop condition and return success status since
-		 * ACK received on zero-byte transaction.
-		 */
-		if (p_status->sz_rxbuf == 0)
-			i2c_done(controller);
-		/*
-		 * Otherwise we have a one-byte transaction, so NACK after
-		 * receiving next byte, if requested.
-		 * Set NACK (ACK bit in the SMBnCTL1 register) only in the
-		 * single-byte mode.
-		 * In FIFO mode, NACK is set via LAST bit in the SMBnTXF_CTL
-		 * register.
-		 */
-		else if ((p_status->flags & I2C_XFER_STOP) &&
-				 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
-			I2C_NACK(controller);
-		}
-
-		/* Clear STASTR to release SCL after setting NACK/STOP bits */
-		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR);
-	}
-
-	/* Condition 4: SDA status is set - transmit or receive */
-	if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST)) {
-		i2c_handle_sda_irq(controller);
-#if DEBUG_I2C
-		/* SDAST still issued with unexpected state machine */
-		if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) &&
-				p_status->oper_state != SMB_WRITE_SUSPEND) {
-			cprints(CC_I2C, "i2c %d unknown state %d, error %d\n",
-			  controller, p_status->oper_state, p_status->err_code);
-		}
-#endif
-	}
-}
-
-/**
- * Handle an interrupt on the specified controller.
- *
- * @param controller   I2C controller generating interrupt
- */
-void handle_interrupt(int controller)
-{
-	i2c_controller_int_handler(controller);
-}
-
-void i2c0_interrupt(void) { handle_interrupt(0); }
-void i2c1_interrupt(void) { handle_interrupt(1); }
-void i2c2_interrupt(void) { handle_interrupt(2); }
-void i2c3_interrupt(void) { handle_interrupt(3); }
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-void i2c4_interrupt(void) { handle_interrupt(4); }
-void i2c5_interrupt(void) { handle_interrupt(5); }
-void i2c6_interrupt(void) { handle_interrupt(6); }
-void i2c7_interrupt(void) { handle_interrupt(7); }
-#endif
-
-DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB2, i2c1_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB3, i2c2_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB4, i2c3_interrupt, 4);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-DECLARE_IRQ(NPCX_IRQ_SMB5, i2c4_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB6, i2c5_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB7, i2c6_interrupt, 4);
-DECLARE_IRQ(NPCX_IRQ_SMB8, i2c7_interrupt, 4);
-#endif
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	int ctrl = i2c_port_to_controller(port);
-
-	/* Return if i2c_port_to_controller() returned an error */
-	if (ctrl < 0)
-		return;
-
-	/* Param is port, but timeout is stored by-controller. */
-	i2c_stsobjs[ctrl].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
-}
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	volatile struct i2c_status *p_status;
-	int ctrl = i2c_port_to_controller(port);
-
-	/* Return error if i2c_port_to_controller() returned an error */
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	/* Skip unnecessary transaction */
-	if (out_size == 0 && in_size == 0)
-		return EC_SUCCESS;
-
-	p_status = i2c_stsobjs + ctrl;
-
-	/* Assign current task ID */
-	p_status->task_waiting = task_get_current();
-
-	/* Select port for multi-ports i2c controller */
-	i2c_select_port(port);
-
-	/* Copy data to controller struct */
-	p_status->flags      = flags;
-	p_status->tx_buf     = out;
-	p_status->sz_txbuf   = out_size;
-	p_status->rx_buf     = in;
-	p_status->sz_rxbuf   = in_size;
-	p_status->addr_flags = addr_flags;
-
-	/* Reset index & error */
-	p_status->idx_buf     = 0;
-	p_status->err_code    = SMB_OK;
-
-	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) &&
-	     /* Ignore busy bus for repeated start */
-	     p_status->oper_state != SMB_WRITE_SUSPEND &&
-	     (i2c_bus_busy(ctrl)
-	     || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-		int ret;
-
-		/* Attempt to unwedge the i2c port */
-		ret = i2c_unwedge(port);
-		if (ret)
-			return ret;
-		p_status->err_code = SMB_BUS_BUSY;
-		/* recover i2c controller */
-		i2c_recovery(ctrl, p_status);
-		/* Select port again for recovery */
-		i2c_select_port(port);
-	}
-
-	CPUTS("\n");
-
-	/* Start controller transaction */
-	i2c_controller_transaction(ctrl);
-
-	/* Reset task ID */
-	p_status->task_waiting = TASK_ID_INVALID;
-
-	CPRINTS("-Err:0x%02x", p_status->err_code);
-
-	return (p_status->err_code == SMB_OK) ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-/**
- * Return raw I/O line levels (I2C_LINE_*) for a port when port is in alternate
- * function mode.
- *
- * @param port  Port to check
- * @return      State of SCL/SDA bit 0/1
- */
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		   (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	/*
-	 * Check do we support this port of i2c and return gpio number of scl.
-	 * Please notice we cannot read voltage level from GPIO in M4 EC
-	 */
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) {
-		if (i2c_is_raw_mode(port))
-			return gpio_get_level(g);
-		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL);
-	}
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	/*
-	 * Check do we support this port of i2c and return gpio number of scl.
-	 * Please notice we cannot read voltage level from GPIO in M4 EC
-	 */
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) {
-		if (i2c_is_raw_mode(port))
-			return gpio_get_level(g);
-		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL);
-	}
-
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle */
-	return 1;
-}
-
-/*****************************************************************************/
-
-static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
-{
-	int freq, j;
-	int scl_freq;
-	const struct i2c_timing *pTiming;
-	int i2c_timing_used;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/*
-	 * SMB0/1/4/5/6/7 use APB3 clock
-	 * SMB2/3 use APB2 clock
-	 */
-	freq = (ctrl < 2 || ctrl > 3) ?
-		clock_get_apb3_freq() : clock_get_apb2_freq();
-#else /* CHIP_FAMILY_NPCX5 */
-	/*
-	 * SMB0/1 use core clock
-	 * SMB2/3 use APB2 clock
-	 */
-	freq = (ctrl < 2) ? clock_get_freq() : clock_get_apb2_freq();
-#endif
-
-	if (bus_freq_kbps == i2c_stsobjs[ctrl].kbps)
-		return;
-
-	/*
-	 * Set SCL frequency by formula:
-	 * tSCL = 4 * SCLFRQ * tCLK
-	 * fSCL = fCLK / (4*SCLFRQ)
-	 * SCLFRQ = ceil(fCLK/(4*fSCL))
-	 */
-	scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */
-
-	/* Normal mode if I2C freq is under 100kHz */
-	if (bus_freq_kbps <= 100) {
-		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-		/* Set divider value of SCL */
-		SET_FIELD(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_SCLFRQ7_FIELD,
-			  (scl_freq & 0x7F));
-		SET_FIELD(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_SCLFRQ2_FIELD,
-			  (scl_freq >> 7));
-		return;
-	}
-
-	/* use Fast Mode */
-	SET_BIT(NPCX_SMBCTL3(ctrl), NPCX_SMBCTL3_400K);
-	/*
-	 * Set SCLH(L)T and hold-time directly for best I2C
-	 * timing condition for all source clocks. Please refer
-	 * Section 7.5.9 "SMBus Timing - Fast Mode" for detail.
-	 */
-	if (bus_freq_kbps == 400) {
-		pTiming = i2c_400k_timings;
-		i2c_timing_used = i2c_400k_timing_used;
-	} else if (bus_freq_kbps == 1000) {
-		pTiming = i2c_1m_timings;
-		i2c_timing_used = i2c_1m_timing_used;
-	} else {
-		i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-		/* Set value from formula */
-		NPCX_SMBSCLLT(ctrl) = scl_freq;
-		NPCX_SMBSCLHT(ctrl) = scl_freq;
-		cprints(CC_I2C,
-			"Warning: I2C %d: Use 400kHz or 1MHz for better timing",
-			ctrl);
-		return;
-	}
-
-	for (j = 0; j < i2c_timing_used; j++, pTiming++) {
-		if (pTiming->clock == (freq/SECOND)) {
-			i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
-			/* Set SCLH(L)T and hold-time */
-			NPCX_SMBSCLLT(ctrl) = pTiming->k1/2;
-			NPCX_SMBSCLHT(ctrl) = pTiming->k2/2;
-			SET_FIELD(NPCX_SMBCTL4(ctrl),
-				  NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT);
-			break;
-		}
-	}
-	if (j == i2c_timing_used)
-		cprints(CC_I2C, "Error: I2C %d: src clk %d not supported",
-			ctrl, freq / SECOND);
-}
-
-/* Hooks */
-
-static void i2c_freq_changed(void)
-{
-	int i;
-
-	for (i = 0; i < I2C_CONTROLLER_COUNT; ++i) {
-		/* No bus speed configured */
-		i2c_stsobjs[i].kbps = 0;
-	}
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		const struct i2c_port_t *p;
-		int ctrl;
-
-		p = &i2c_ports[i];
-		ctrl = i2c_port_to_controller(p->port);
-		if (ctrl < 0)
-			continue;
-		i2c_port_set_freq(ctrl, p->kbps);
-	}
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT);
-
-enum i2c_freq chip_i2c_get_freq(int chip_i2c_port)
-{
-	int ctrl;
-	int kbps;
-
-	ctrl = i2c_port_to_controller(chip_i2c_port);
-	if (ctrl < 0)
-		return I2C_FREQ_COUNT;
-
-	kbps = i2c_stsobjs[ctrl].kbps;
-
-	if (kbps > 400)
-		return I2C_FREQ_1000KHZ;
-	if (kbps > 100)
-		return I2C_FREQ_400KHZ;
-
-	if (kbps == 100)
-		return I2C_FREQ_100KHZ;
-
-	return I2C_FREQ_COUNT;
-}
-
-int chip_i2c_set_freq(int chip_i2c_port, enum i2c_freq freq)
-{
-	int ctrl;
-	int bus_freq_kbps;
-
-	ctrl = i2c_port_to_controller(chip_i2c_port);
-	if (ctrl < 0)
-		return EC_ERROR_INVAL;
-
-	switch (freq) {
-	case I2C_FREQ_100KHZ:
-		bus_freq_kbps = 100;
-		break;
-	case I2C_FREQ_400KHZ:
-		bus_freq_kbps = 400;
-		break;
-	case I2C_FREQ_1000KHZ:
-		bus_freq_kbps = 1000;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	i2c_port_set_freq(ctrl, bus_freq_kbps);
-	return EC_SUCCESS;
-}
-
-void i2c_init(void)
-{
-	int i;
-
-	/* Configure pins from GPIOs to I2Cs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Enable clock for I2C peripheral */
-	clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#endif
-
-	/* Set I2C freq */
-	i2c_freq_changed();
-	/*
-	 * initialize smb status and register
-	 */
-	for (i = 0; i < i2c_ports_used; i++) {
-		volatile struct i2c_status *p_status;
-		int port = i2c_ports[i].port;
-		int ctrl = i2c_port_to_controller(port);
-
-		/* ignore the port if i2c_port_to_controller() failed */
-		if (ctrl < 0)
-			continue;
-
-		p_status = i2c_stsobjs + ctrl;
-
-		/* status init */
-		p_status->oper_state = SMB_IDLE;
-
-		/* Reset task ID */
-		p_status->task_waiting = TASK_ID_INVALID;
-
-		/* Use default timeout. */
-		i2c_set_timeout(port, 0);
-
-		/* Init the SMB module */
-		i2c_init_bus(ctrl);
-	}
-}
diff --git a/chip/npcx/i2c_chip.h b/chip/npcx/i2c_chip.h
deleted file mode 100644
index 014e6cddf2..0000000000
--- a/chip/npcx/i2c_chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific I2C module for Chrome EC */
-
-#ifndef __CROS_EC_I2C_CHIP_H
-#define __CROS_EC_I2C_CHIP_H
-
-/**
- * Select specific i2c port connected to i2c controller.
- *
- * @parm port I2C port
- */
-void i2c_select_port(int port);
-
-/*
- * Due to we couldn't support GPIO reading when IO is selected I2C, we need
- * to distingulish which mode we used currently.
- *
- * @parm port I2C port
- *
- * @return 0: i2c ports are selected to pins. 1: GPIOs are selected to pins.
- */
-int i2c_is_raw_mode(int port);
-
-#endif /* __CROS_EC_I2C_CHIP_H */
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
deleted file mode 100644
index e6b8cad7bd..0000000000
--- a/chip/npcx/keyboard_raw.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include "common.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "clock.h"
-#include "gpio.h"
-#include "registers.h"
-#include "task.h"
-
-/**
- * Initialize the raw keyboard interface.
- */
-void keyboard_raw_init(void)
-{
-	/* Enable clock for KBS peripheral */
-	clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Ensure top-level interrupt is disabled */
-	keyboard_raw_enable_interrupt(0);
-
-	/*
-	 * Select quasi-bidirectional buffers for KSO pins. It reduces the
-	 * low-to-high transition time. This feature only supports in npcx7.
-	 */
-#ifdef CONFIG_KEYBOARD_KSO_HIGH_DRIVE
-	SET_FIELD(NPCX_KBSCTL, NPCX_KBHDRV_FIELD, 0x01);
-#endif
-
-	/* pull-up KBSIN 0-7 internally */
-	NPCX_KBSINPU = 0xFF;
-
-	/* Disable automatic scan mode */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSMODE);
-
-	/* Disable automatic interrupt enable */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSIEN);
-
-	/* Disable increment enable */
-	CLEAR_BIT(NPCX_KBSCTL, NPCX_KBSINC);
-
-	/* Set KBSOUT to zero to detect key-press */
-	NPCX_KBSOUT0 = 0x00;
-	NPCX_KBSOUT1 = 0x00;
-
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-
-	/*
-	 * Enable interrupts for the inputs.  The top-level interrupt is still
-	 * masked off, so this won't trigger interrupts yet.
-	 */
-
-	/* Clear pending input sources used by scanner */
-	NPCX_WKPCL(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Enable Wake-up Button */
-	NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Select high to low transition (falling edge) */
-	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) =  0xFF;
-
-	/* Enable interrupt of WK KBS */
-	keyboard_raw_enable_interrupt(1);
-}
-
-/**
- * Finish initialization after task scheduling has started.
- */
-void keyboard_raw_task_start(void)
-{
-	/* Enable MIWU to trigger KBS interrupt */
-	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-}
-
-/**
- * Drive the specified column low.
- */
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	/*
-	 * Nuvoton Keyboard Scan IP supports 18x8 Matrix
-	 * It also support automatic scan functionality
-	 */
-	uint32_t mask, col_out;
-
-	/* Add support for CONFIG_KEYBOARD_KSO_BASE shifting */
-	col_out = col + CONFIG_KEYBOARD_KSO_BASE;
-
-	/* Drive all lines to high */
-	if (col == KEYBOARD_COLUMN_NONE) {
-		mask = ~0;
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-	}
-	/* Set KBSOUT to zero to detect key-press */
-	else if (col == KEYBOARD_COLUMN_ALL) {
-		mask = ~(BIT(keyboard_cols) - 1);
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		gpio_set_level(GPIO_KBD_KSO2, 1);
-#endif
-	}
-	/* Drive one line for detection */
-	else {
-#if defined(CONFIG_KEYBOARD_CUSTOMIZATION)
-		board_keyboard_drive_col(col);
-#elif defined(CONFIG_KEYBOARD_COL2_INVERTED)
-		if (col == 2)
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		else
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-#endif
-		mask = ~BIT(col_out);
-	}
-
-	/* Set KBSOUT */
-	NPCX_KBSOUT0 = (mask & 0xFFFF);
-	NPCX_KBSOUT1 = ((mask >> 16) & 0x03);
-}
-
-/**
- * Read raw row state.
- * Bits are 1 if signal is present, 0 if not present.
- */
-test_mockable int keyboard_raw_read_rows(void)
-{
-	/* Bits are active-low, so invert returned levels */
-	return (~NPCX_KBSIN) & KB_ROW_MASK;
-}
-
-/**
- * Enable or disable keyboard interrupts.
- */
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable)
-		task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
-	else
-		task_disable_irq(NPCX_IRQ_KSI_WKINTC_1);
-}
-
-/*
- * Interrupt handler for the entire GPIO bank of keyboard rows.
- */
-void keyboard_raw_interrupt(void)
-{
-	/* Clear pending input sources used by scanner */
-	NPCX_WKPCL(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
-
-	/* Wake the scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5);
-
-int keyboard_raw_is_input_low(int port, int id)
-{
-	return (NPCX_PDIN(port) & BIT(id)) == 0;
-}
-
diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c
deleted file mode 100644
index e23fa3bf6a..0000000000
--- a/chip/npcx/lct.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LCT (Long Countdown Timer) module for Chrome EC */
-#include "lct_chip.h"
-#include "console.h"
-#include "hooks.h"
-#include "registers.h"
-#include "rtc.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define LCT_CLK_ENABLE_DELAY_USEC    150
-
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't set power source when LCT is enabled");
-		return;
-	}
-
-	if (pwr_src == NPCX_LCT_PWR_SRC_VSBY)
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR);
-	else
-		CLEAR_BIT(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR);
-}
-
-void npcx_lct_enable_clk(uint8_t enable)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't set/unset clock when LCT is enabled");
-		return;
-	}
-
-	if (enable) {
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_CLK_EN);
-		/*
-		 * This bit must be set to 1 at least tLCTCKEN (150 us)
-		 * before the LCT is enabled.
-		 */
-		udelay(LCT_CLK_ENABLE_DELAY_USEC);
-	} else {
-		CLEAR_BIT(NPCX_LCTCONT, NPCX_LCTCONT_CLK_EN);
-	}
-}
-
-void npcx_lct_enable(uint8_t enable)
-{
-	enable = !!enable;
-	SET_FIELD(NPCX_LCTCONT, NPCX_LCTCONT_EN_FIELD, enable);
-	/* Wait until the bit value equals to what is set */
-	while (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN) != enable)
-		;
-}
-
-void npcx_lct_config(int seconds, int psl_ena, int int_ena)
-{
-	if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_EN)) {
-		CPRINTS("Don't config LCT when LCT is enabled");
-		return;
-	}
-
-	/* LCT can count max to (16 weeks - 1 second) */
-	if (seconds > NPCX_LCT_MAX) {
-		CPRINTS("LCT time is out of range");
-		return;
-	}
-
-	/* Clear pending LCT event first */
-	NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-
-	NPCX_LCTWEEK = seconds / SECS_PER_WEEK;
-	seconds %= SECS_PER_WEEK;
-	NPCX_LCTDAY = seconds / SECS_PER_DAY;
-	seconds %= SECS_PER_DAY;
-	NPCX_LCTHOUR = seconds / SECS_PER_HOUR;
-	seconds %= SECS_PER_HOUR;
-	NPCX_LCTMINUTE = seconds / SECS_PER_MINUTE;
-	NPCX_LCTSECOND = seconds % SECS_PER_MINUTE;
-
-	if (psl_ena) {
-		if (IS_BIT_SET(NPCX_LCTCONT, NPCX_LCTCONT_VSBY_PWR))
-			SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_PSL_EN);
-		else
-			CPRINTS("LCT must source VSBY to support PSL wakeup");
-	}
-
-	if (int_ena)
-		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN);
-
-}
-
-uint32_t npcx_lct_get_time(void)
-{
-	uint32_t second;
-	uint8_t week, day, hour, minute;
-
-	do {
-		week   = NPCX_LCTWEEK;
-		day    = NPCX_LCTDAY;
-		hour   = NPCX_LCTHOUR;
-		minute = NPCX_LCTMINUTE;
-		second = NPCX_LCTSECOND;
-	} while (week   != NPCX_LCTWEEK   ||
-		 day    != NPCX_LCTDAY    ||
-		 hour   != NPCX_LCTHOUR   ||
-		 minute != NPCX_LCTMINUTE ||
-		 second != NPCX_LCTSECOND);
-
-	second += minute * SECS_PER_MINUTE +
-		  hour * SECS_PER_HOUR +
-		  day * SECS_PER_DAY +
-		  week * SECS_PER_WEEK;
-
-	return second;
-}
-
-void npcx_lct_clear_event(void)
-{
-	NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-}
-
-int npcx_lct_is_event_set(void)
-{
-	return IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST);
-}
-
-static void npcx_lct_init(void)
-{
-	/* Disable LCT */
-	npcx_lct_enable(0);
-	/* Clear control and status registers */
-	NPCX_LCTCONT = 0x0;
-	npcx_lct_clear_event();
-	/* Clear all timer registers */
-	NPCX_LCTSECOND = 0x0;
-	NPCX_LCTMINUTE = 0x0;
-	NPCX_LCTHOUR = 0x0;
-	NPCX_LCTDAY = 0x0;
-	NPCX_LCTWEEK = 0x0;
-}
-DECLARE_HOOK(HOOK_INIT, npcx_lct_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CMD_RTC_ALARM
-static int command_lctalarm(int argc, char **argv)
-{
-	char *e;
-	int seconds;
-
-	seconds = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	npcx_lct_enable(0);
-	npcx_lct_sel_power_src(NPCX_LCT_PWR_SRC_VSBY);
-	npcx_lct_enable_clk(1);
-	/* Enable LCT event interrupt and MIWU */
-	npcx_lct_config(seconds, 0, 1);
-	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	npcx_lct_enable(1);
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(lctalarm, command_lctalarm, "", "");
-#endif
diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h
deleted file mode 100644
index 197c189f43..0000000000
--- a/chip/npcx/lct_chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_LCT_CHIP_H
-#define __CROS_EC_LCT_CHIP_H
-#include "registers.h"
-#include "rtc.h"
-
-#define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1)
-
-enum NPCX_LCT_PWR_SRC {
-	NPCX_LCT_PWR_SRC_VCC1,
-	NPCX_LCT_PWR_SRC_VSBY
-};
-
-void npcx_lct_config(int seconds, int psl_ena, int int_ena);
-void npcx_lct_enable(uint8_t enable);
-void npcx_lct_enable_clk(uint8_t enable);
-void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src);
-void npcx_lct_clear_event(void);
-int npcx_lct_is_event_set(void);
-
-/* return the current time of LCT in second */
-uint32_t npcx_lct_get_time(void);
-
-#endif  /* __CROS_EC_LCT_CHIP_H */
diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h
deleted file mode 100644
index 88c0a9ed83..0000000000
--- a/chip/npcx/lfw/ec_lfw.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX5M5G SoC little FW used by booter
- */
-
-#ifndef __CROS_EC_EC_LFW_H
-#define __CROS_EC_EC_LFW_H
-
-/* Begin address for the .iram section; defined in linker script */
-extern unsigned int __iram_fw_start;
-/* End address for the .iram section; defined in linker script */
-extern unsigned int __iram_fw_end;
-/* Begin address for the iram codes; defined in linker script */
-extern unsigned int __flash_fw_start;
-
-#endif /* __CROS_EC_EC_LFW_H */
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
deleted file mode 100644
index adf78b642d..0000000000
--- a/chip/npcx/lpc.c
+++ /dev/null
@@ -1,991 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LPC module for Chrome EC */
-
-#include "acpi.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i8042_protocol.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "lpc_chip.h"
-#include "port80.h"
-#include "registers.h"
-#include "system.h"
-#include "sib_chip.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "system_chip.h"
-
-/* Console output macros */
-#if !(DEBUG_LPC)
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#endif
-
-/* PM channel definitions */
-#define PMC_ACPI     PM_CHAN_1
-#define PMC_HOST_CMD PM_CHAN_2
-
-#define PORT80_MAX_BUF_SIZE    16
-static uint16_t port80_buf[PORT80_MAX_BUF_SIZE];
-
-static struct	host_packet lpc_packet;
-static struct	host_cmd_handler_args host_cmd_args;
-static uint8_t	host_cmd_flags;         /* Flags from host command */
-static uint8_t	shm_mem_host_cmd[256] __aligned(8);
-static uint8_t	shm_memmap[256] __aligned(8);
-/* Params must be 32-bit aligned */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static int init_done;
-
-static struct ec_lpc_host_args * const lpc_host_args =
-		(struct ec_lpc_host_args *)shm_mem_host_cmd;
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-static void keyboard_irq_assert(void)
-{
-#ifdef CONFIG_KEYBOARD_IRQ_GPIO
-	/*
-	 * Enforce signal-high for long enough for the signal to be pulled high
-	 * by the external pullup resistor.  This ensures the host will see the
-	 * following falling edge, regardless of the line state before this
-	 * function call.
-	 */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-	udelay(4);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0);
-	udelay(4);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
-#else
-	/*
-	 * SERIRQ is automatically sent by KBC
-	 */
-#endif
-}
-
-static void lpc_task_enable_irq(void)
-{
-#ifdef HAS_TASK_KEYPROTO
-	task_enable_irq(NPCX_IRQ_KBC_IBF);
-#endif
-	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
-	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
-	task_enable_irq(NPCX_IRQ_ESPI);
-	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
-	task_enable_irq(NPCX_IRQ_WKINTA_2);
-	/* Virtual Wire: HOST_RST_WARN, SUS_WARN, SUS_PWRDN_ACK, SLP_A */
-	task_enable_irq(NPCX_IRQ_WKINTB_2);
-	/* Enable eSPI module interrupts and wake-up functionalities */
-	NPCX_ESPIIE |= (ESPIIE_GENERIC | ESPIIE_VW);
-	NPCX_ESPIWE |= (ESPIWE_GENERIC | ESPIWE_VW);
-#endif
-}
-
-static void lpc_task_disable_irq(void)
-{
-#ifdef HAS_TASK_KEYPROTO
-	task_disable_irq(NPCX_IRQ_KBC_IBF);
-#endif
-	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
-	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
-	task_disable_irq(NPCX_IRQ_ESPI);
-	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
-	task_disable_irq(NPCX_IRQ_WKINTA_2);
-	/* Virtual Wire: HOST_RST_WARN,SUS_WARN, SUS_PWRDN_ACK, SLP_A */
-	task_disable_irq(NPCX_IRQ_WKINTB_2);
-	/* Disable eSPI module interrupts and wake-up functionalities */
-	NPCX_ESPIIE &= ~(ESPIIE_GENERIC | ESPIIE_VW);
-	NPCX_ESPIWE &= ~(ESPIWE_GENERIC | ESPIWE_VW);
-#endif
-}
-/**
- * Generate SMI pulse to the host chipset via GPIO.
- *
- * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is
- * 60ns.  If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse
- * length >61us.  Both are short enough and events are infrequent, so just
- * delay for 65us.
- */
-static void lpc_generate_smi(void)
-{
-	host_event_t smi;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
-	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
-	 * The reason is - if GPIOC6/CPIO76 are not selected as SMI/SCI, reading
-	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
-	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
-	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
-	udelay(65);
-	/* Generate a falling edge */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(0);
-	udelay(65);
-	/* Set signal high */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(1);
-#else
-	/* SET SMIB bit to pull SMI_L to high.*/
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
-	/* Generate a falling edge */
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(65);
-	/* Set signal high */
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-#endif
-	smi = lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI);
-	if (smi)
-		HOST_EVENT_CPRINTS("smi", smi);
-}
-
-/**
- * Generate SCI pulse to the host chipset via LPC0SCI.
- */
-static void lpc_generate_sci(void)
-{
-	host_event_t sci;
-
-#ifdef CONFIG_SCI_GPIO
-	/* Enforce signal-high for long enough to debounce high */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-	udelay(65);
-	/* Generate a falling edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 0);
-	udelay(65);
-	/* Set signal high, now that we've generated the edge */
-	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
-	/*
-	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
-	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
-	 * The reason is - if GPIOC6/CPIO76 are not selected as SMI/SCI, reading
-	 * from SMIB/SCIB doesn't really reflect the SMI/SCI status. SMI/SCI
-	 * status should be read from bit 1/0 in eSPI VMEVSM(2) register.
-	 */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
-	udelay(65);
-	/* Generate a falling edge */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(0);
-	udelay(65);
-	/* Set signal high */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(1);
-#else
-	/* Set SCIB bit to pull SCI_L to high.*/
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
-	/* Generate a falling edge */
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(65);
-	/* Set signal high */
-	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-#endif
-
-	sci = lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI);
-	if (sci)
-		HOST_EVENT_CPRINTS("sci", sci);
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_PCH_WAKE_L, !wake_events);
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	return (uint8_t *)shm_memmap;
-}
-
-static void lpc_send_response(struct host_cmd_handler_args *args)
-{
-	uint8_t *out;
-	int size = args->response_size;
-	int csum;
-	int i;
-
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (args->result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Handle negative size */
-	if (size < 0) {
-		args->result = EC_RES_INVALID_RESPONSE;
-		size = 0;
-	}
-
-	/* New-style response */
-	lpc_host_args->flags =
-			(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
-
-	lpc_host_args->data_size = size;
-
-	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
-
-	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
-		csum += *out;
-
-	lpc_host_args->checksum = (uint8_t)csum;
-
-	/* Fail if response doesn't fit in the param buffer */
-	if (size > EC_PROTO2_MAX_PARAM_SIZE)
-		args->result = EC_RES_INVALID_RESPONSE;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	NPCX_HIPMDO(PMC_HOST_CMD) = args->result;
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	/* Ignore in-progress on LPC since interface is synchronous anyway */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	NPCX_HIPMDO(PMC_HOST_CMD) = pkt->driver_result;
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-}
-
-int lpc_keyboard_has_char(void)
-{
-	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	return (NPCX_HIKMST&0x01) ? 1 : 0;
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	return (NPCX_HIKMST&0x02) ? 1 : 0;
-}
-
-/* Put a char to host buffer by HIKDO and send IRQ if specified. */
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	NPCX_HIKDO = chr;
-	CPRINTS("KB put %02x", chr);
-
-	/* Enable OBE interrupt to detect host read data out */
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_enable_irq(NPCX_IRQ_KBC_OBE);
-	if (send_irq) {
-		keyboard_irq_assert();
-	}
-}
-
-/* Put an aux char to host buffer by HIMDO and assert status bit 5. */
-void lpc_aux_put_char(uint8_t chr, int send_irq)
-{
-	if (send_irq)
-		SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBFMIE);
-	else
-		CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBFMIE);
-
-	NPCX_HIKMST |= I8042_AUX_DATA;
-	NPCX_HIMDO = chr;
-	CPRINTS("AUX put %02x", chr);
-
-	/* Enable OBE interrupt to detect host read data out */
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_enable_irq(NPCX_IRQ_KBC_OBE);
-}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/*
-	 * Only npcx5 series need this bypass. The bug of FW_OBF is fixed in
-	 * npcx7 series and later npcx ec.
-	 */
-#ifdef CHIP_FAMILY_NPCX5
-	/* Clear OBF flag in host STATUS and HIKMST regs */
-	if (IS_BIT_SET(NPCX_HIKMST, NPCX_HIKMST_OBF)) {
-		/*
-		 * Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF
-		 * but it does not deassert IRQ1 when it was already asserted.
-		 * Emulate a host read to clear these two flags and also
-		 * deassert IRQ1
-		 */
-		sib_read_kbc_reg(0x0);
-	}
-#else
-	/* Make sure the previous TOH and IRQ has been sent out. */
-	udelay(4);
-	/* Clear OBE flag in host STATUS  and HIKMST regs*/
-	SET_BIT(NPCX_HICTRL, NPCX_HICTRL_FW_OBF);
-	/* Ensure there is no TOH set in this period. */
-	udelay(4);
-#endif
-}
-
-void lpc_keyboard_resume_irq(void)
-{
-	if (lpc_keyboard_has_char())
-		keyboard_irq_assert();
-}
-
-/**
- * Update the host event status.
- *
- * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMI_L GPIO
- *   - SCI pulse via LPC0SCI
- */
-void lpc_update_host_event_status(void)
-{
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable LPC interrupt while updating status register */
-	lpc_task_disable_irq();
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(NPCX_HIPMST(PMC_ACPI) & NPCX_HIPMST_ST2))
-			need_smi = 1;
-		SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST2);
-	} else
-		CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST2);
-
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-		SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST1);
-	} else
-		CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_ST1);
-
-	/* Copy host events to mapped memory */
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
-
-	lpc_task_enable_irq();
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	NPCX_HIPMST(PMC_ACPI) |= mask;
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	NPCX_HIPMST(PMC_ACPI) &= ~mask;
-}
-
-/* Enable LPC ACPI-EC interrupts */
-void lpc_enable_acpi_interrupts(void)
-{
-	SET_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_IBFIE);
-}
-
-/* Disable LPC ACPI-EC interrupts */
-void lpc_disable_acpi_interrupts(void)
-{
-	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_IBFIE);
-}
-
-/**
- * Handle write to ACPI I/O port
- *
- * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
- */
-static void handle_acpi_write(int is_cmd)
-{
-	uint8_t value, result;
-
-	/* Set processing flag before reading command byte */
-	SET_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_F0);
-
-	/* Read command/data; this clears the FRMH status bit. */
-	value = NPCX_HIPMDI(PMC_ACPI);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result))
-		NPCX_HIPMDO(PMC_ACPI) = result;
-
-	/* Clear processing flag */
-	CLEAR_BIT(NPCX_HIPMST(PMC_ACPI), NPCX_HIPMST_F0);
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-/**
- * Handle write to host command I/O ports.
- *
- * @param is_cmd	Is write command (1) or data (0)?
- */
-static void handle_host_write(int is_cmd)
-{
-	/* Set processing flag before reading command byte */
-	SET_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-	/*
-	 * Read the command byte.  This clears the FRMH bit in
-	 * the status byte.
-	 */
-	host_cmd_args.command = NPCX_HIPMDI(PMC_HOST_CMD);
-
-	host_cmd_args.result = EC_RES_SUCCESS;
-	host_cmd_args.send_response = lpc_send_response;
-	host_cmd_flags = lpc_host_args->flags;
-
-	/* See if we have an old or new style command */
-	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
-		lpc_packet.send_response = lpc_send_response_packet;
-
-		lpc_packet.request = (const void *)shm_mem_host_cmd;
-		lpc_packet.request_temp = params_copy;
-		lpc_packet.request_max = sizeof(params_copy);
-		/* Don't know the request size so pass in the entire buffer */
-		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-		lpc_packet.response = (void *)shm_mem_host_cmd;
-		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-		lpc_packet.response_size = 0;
-
-		lpc_packet.driver_result = EC_RES_SUCCESS;
-
-		host_packet_receive(&lpc_packet);
-		return;
-
-	} else {
-		/* Old style command, now unsupported */
-		host_cmd_args.result = EC_RES_INVALID_COMMAND;
-	}
-
-	/* Hand off to host command handler */
-	host_command_received(&host_cmd_args);
-}
-
-/*****************************************************************************/
-/* Interrupt handlers */
-#ifdef HAS_TASK_KEYPROTO
-/* KB controller input buffer full ISR */
-void lpc_kbc_ibf_interrupt(void)
-{
-	uint8_t status;
-	uint8_t ibf;
-	/* If "command" input 0, else 1*/
-	if (lpc_keyboard_input_pending()) {
-		/*
-		 * Reading HIKMDI causes the IBF flag to deassert and allows
-		 * the host to write a new byte into the input buffer. So if we
-		 * don't capture the status before reading HIKMDI we will race
-		 * with the host and get an invalid value for HIKMST.A20.
-		 */
-		status = NPCX_HIKMST;
-		ibf = NPCX_HIKMDI;
-		keyboard_host_write(ibf, (status & 0x08) ? 1 : 0);
-		CPRINTS("ibf isr %02x", ibf);
-		task_wake(TASK_ID_KEYPROTO);
-	} else {
-		CPRINTS("ibf isr spurious");
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 4);
-
-/* KB controller output buffer empty ISR */
-void lpc_kbc_obe_interrupt(void)
-{
-	/* Disable KBC OBE interrupt */
-	CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
-	task_disable_irq(NPCX_IRQ_KBC_OBE);
-
-	CPRINTS("obe isr %02x", NPCX_HIKMST);
-
-	NPCX_HIKMST &= ~I8042_AUX_DATA;
-
-	task_wake(TASK_ID_KEYPROTO);
-}
-DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4);
-#endif
-
-/* PM channel input buffer full ISR */
-void lpc_pmc_ibf_interrupt(void)
-{
-	/* Channel-1 for ACPI usage*/
-	/* Channel-2 for Host Command usage , so the argument data had been
-	 * put on the share memory firstly*/
-	if (NPCX_HIPMST(PMC_ACPI) & 0x02)
-		handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0);
-	else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02)
-		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0);
-}
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4);
-
-/* PM channel output buffer empty ISR */
-void lpc_pmc_obe_interrupt(void)
-{
-}
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 4);
-
-void lpc_port80_interrupt(void)
-{
-	uint8_t i;
-	uint8_t count = 0;
-	uint32_t code = 0;
-
-	/* buffer Port80 data to the local buffer if FIFO is not empty */
-	while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE))
-		port80_buf[count++] = NPCX_DP80BUF;
-
-	for (i = 0; i < count; i++) {
-		uint8_t offset;
-		uint32_t buf_data;
-
-		buf_data = port80_buf[i];
-		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
-		code |= (buf_data & 0xFF) << (8 * offset);
-
-		if (i == count - 1) {
-			port_80_write(code);
-			break;
-		}
-
-		/* peek the offset of the next byte */
-		buf_data = port80_buf[i + 1];
-		offset = GET_FIELD(buf_data, NPCX_DP80BUF_OFFS_FIELD);
-		/*
-		 * If the peeked next byte's offset is 0 means it is the start
-		 * of the new code. Pass the current code to Port80
-		 * common layer.
-		 */
-		if (offset == 0) {
-			port_80_write(code);
-			code = 0;
-		}
-	}
-
-	/* If FIFO is overflow */
-	if (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FOR)) {
-		SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FOR);
-		CPRINTS("DP80 FIFO Overflow!");
-	}
-
-	/* Clear pending bit of host writing */
-	SET_BIT(NPCX_DP80STS, NPCX_DP80STS_FWR);
-}
-DECLARE_IRQ(NPCX_IRQ_PORT80, lpc_port80_interrupt, 4);
-
-/**
- * Preserve event masks across a sysjump.
- */
-static void lpc_sysjump(void)
-{
-	lpc_task_disable_irq();
-
-	/* Disable protect for Win 1 and 2. */
-	NPCX_WIN_WR_PROT(0) = 0;
-	NPCX_WIN_WR_PROT(1) = 0;
-	NPCX_WIN_RD_PROT(0) = 0;
-	NPCX_WIN_RD_PROT(1) = 0;
-
-	/* Reset base address for Win 1 and 2. */
-	NPCX_WIN_BASE(0) = 0xfffffff8;
-	NPCX_WIN_BASE(1) = 0xfffffff8;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, lpc_sysjump, HOOK_PRIO_DEFAULT);
-
-/* For LPC host register initial via SIB module */
-void host_register_init(void)
-{
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-
-	/* enable ACPI*/
-	sib_write_reg(SIO_OFFSET, 0x07, 0x11);
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* Enable kbc and mouse */
-#ifdef HAS_TASK_KEYPROTO
-	/* LDN = 0x06 : keyboard */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x06);
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* LDN = 0x05 : mouse */
-	if (IS_ENABLED(CONFIG_PS2)) {
-		sib_write_reg(SIO_OFFSET, 0x07, 0x05);
-		sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-	}
-#endif
-
-	/* Setting PMC2 */
-	/* LDN register = 0x12(PMC2) */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x12);
-	/* CMD port is 0x200 */
-	sib_write_reg(SIO_OFFSET, 0x60, 0x02);
-	sib_write_reg(SIO_OFFSET, 0x61, 0x00);
-	/* Data port is 0x204 */
-	sib_write_reg(SIO_OFFSET, 0x62, 0x02);
-	sib_write_reg(SIO_OFFSET, 0x63, 0x04);
-	/* enable PMC2 */
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	/* Setting SHM */
-	/* LDN register = 0x0F(SHM) */
-	sib_write_reg(SIO_OFFSET, 0x07, 0x0F);
-	/* WIN1&2 mapping to IO */
-	sib_write_reg(SIO_OFFSET, 0xF1,
-			sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
-	/* WIN1 as Host Command on the IO:0x0800 */
-	sib_write_reg(SIO_OFFSET, 0xF5, 0x08);
-	sib_write_reg(SIO_OFFSET, 0xF4, 0x00);
-	/* WIN2 as MEMMAP on the IO:0x900 */
-	sib_write_reg(SIO_OFFSET, 0xF9, 0x09);
-	sib_write_reg(SIO_OFFSET, 0xF8, 0x00);
-
-	/*
-	 * eSPI allows sending 4 bytes of Port80 code in a single PUT_IOWR_SHORT
-	 * transaction. When setting OFS0_SEL~OFS3_SEL in DPAR1 register to 1,
-	 * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO.
-	 * This is only supported when CHIP_FAMILY >= NPCX9.
-	 */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
-		sib_write_reg(SIO_OFFSET, 0xFD, 0x0F);
-	/* enable SHM */
-	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
-
-	CPRINTS("Host settings are done!");
-
-}
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static void lpc_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(lpc_chipset_reset);
-#endif
-
-int lpc_get_pltrst_asserted(void)
-{
-	/* Read current PLTRST status */
-	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
-}
-
-#ifndef CONFIG_HOSTCMD_ESPI
-/* Initialize host settings by interrupt */
-void lpc_lreset_pltrst_handler(void)
-{
-	int pltrst_asserted;
-
-	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
-
-	/* Ignore PLTRST# from SOC if it is not valid */
-	if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
-		return;
-
-	pltrst_asserted = lpc_get_pltrst_asserted();
-
-	CPRINTS("LPC RESET# %sasserted", pltrst_asserted ? "" : "de");
-
-	/*
-	 * Once LRESET is de-asserted (low -> high), we need to initialize lpc
-	 * settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers
-	 * won't be reset by Host domain reset but Core domain does.
-	 */
-	if (!pltrst_asserted)
-		host_register_init();
-	else {
-		/* Clear processing flag when LRESET is asserted */
-		CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-		/* Notify HOOK_CHIPSET_RESET */
-		hook_call_deferred(&lpc_chipset_reset_data, MSEC);
-#endif
-	}
-}
-#endif
-
-/*****************************************************************************/
-/* LPC/eSPI Initialization functions */
-
-static void lpc_init(void)
-{
-	/* Enable clock for LPC peripheral */
-	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/*
-	 * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT
-	 * register) is updated by booter after VCC1 Power-Up reset according to
-	 * VHIF voltage.
-	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
-	 * field should be set by firmware.
-	 */
-#ifdef CONFIG_HOSTCMD_ESPI
-	/* Initialize eSPI module */
-	NPCX_DEVCNT |= 0x08;
-	espi_init();
-#else
-	/* Switching to LPC interface */
-	NPCX_DEVCNT |= 0x04;
-#endif
-	/* Enable 4E/4F */
-	if (!IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_VHCFGA)) {
-		NPCX_HCBAL = 0x4E;
-		NPCX_HCBAH = 0x0;
-	}
-	/* Clear Host Access Hold state */
-	NPCX_SMC_CTL = 0xC0;
-
-#ifndef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
-	 * continuous or quiet mode.
-	 */
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_CLKRN_SL);
-#endif
-
-	/*
-	 * Set pin-mux from GPIOs to SCL/SMI to make sure toggling SCIB/SMIB is
-	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
-	 * automatically by toggling them, too. It's unnecessary to set pin mux.
-	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
-	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
-#endif
-
-	/* Initialize Hardware for UART Host */
-#ifdef CONFIG_UART_HOST
-	/* Init COMx LPC UART */
-	/* FMCLK have to using 50MHz */
-	NPCX_DEVALT(0xB) = 0xFF;
-	/* Make sure Host Access unlock */
-	CLEAR_BIT(NPCX_LKSIOHA, 2);
-	/* Clear Host Access Lock Violation */
-	SET_BIT(NPCX_SIOLV, 2);
-#endif
-
-	/* Don't stall SHM transactions */
-	NPCX_SHM_CTL = NPCX_SHM_CTL & ~0x40;
-	/* Disable Protect Win1&2*/
-	NPCX_WIN_WR_PROT(0) = 0;
-	NPCX_WIN_WR_PROT(1) = 0;
-	NPCX_WIN_RD_PROT(0) = 0;
-	NPCX_WIN_RD_PROT(1) = 0;
-	/* Open Win1 256 byte for Host CMD, Win2 256 for MEMMAP*/
-	NPCX_WIN_SIZE = 0x88;
-	NPCX_WIN_BASE(0) = (uint32_t)shm_mem_host_cmd;
-	NPCX_WIN_BASE(1) = (uint32_t)shm_memmap;
-	/* Write protect of Share memory */
-	NPCX_WIN_WR_PROT(1) = 0xFF;
-
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-			EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-			EC_HOST_CMD_FLAG_VERSION_3;
-
-	/*
-	 * Clear processing flag before enabling lpc's interrupts in case
-	 * it's set by the other command during sysjump.
-	 */
-	CLEAR_BIT(NPCX_HIPMST(PMC_HOST_CMD), NPCX_HIPMST_F0);
-
-	/* Turn on PMC2 for Host Command usage */
-	SET_BIT(NPCX_HIPMCTL(PMC_HOST_CMD), 0);
-
-	/*
-	 * Set required control value (avoid setting HOSTWAIT bit at this stage)
-	 */
-	NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F;
-	/* Clear status */
-	NPCX_SMC_STS = NPCX_SMC_STS;
-
-	/* Create mailbox */
-
-	/*
-	 * Init KBC
-	 * Clear OBF status flag,
-	 * IBF(K&M) INT enable,
-	 * OBF Mouse Full INT enable and OBF KB Full INT enable
-	 */
-#ifdef HAS_TASK_KEYPROTO
-	lpc_keyboard_clear_buffer();
-	NPCX_HICTRL = 0x0B;
-#endif
-
-	/*
-	 * Turn on enhance mode on PM channel-1,
-	 * enable IBF core interrupt
-	 */
-	NPCX_HIPMCTL(PMC_ACPI) |= 0x81;
-	/* Normally Polarity IRQ1,12 type (level + high) setting */
-	NPCX_HIIRQC = 0x00;
-
-	/*
-	 * Init PORT80
-	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
-	 */
-#ifdef CONFIG_HOSTCMD_ESPI
-	NPCX_DP80CTL = 0x2b;
-#else
-	NPCX_DP80CTL = 0x29;
-#endif
-	SET_BIT(NPCX_GLUE_SDP_CTS, 3);
-#if SUPPORT_P80_SEG
-	SET_BIT(NPCX_GLUE_SDP_CTS, 0);
-#endif
-
-	/*
-	 * Use SMI/SCI postive polarity as default.
-	 * Negative polarity must be enabled in the case that SMI/SCI is
-	 * generated automatically by hardware. In current design,
-	 * SMI/SCI is conntrolled by FW. Use postive polarity is more
-	 * intuitive.
-	 */
-	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL);
-	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL);
-	/* Set SMIB/SCIB to make sure SMI/SCI are high at init */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI)
-			| BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB);
-#ifndef CONFIG_SCI_GPIO
-	/*
-	 * Allow SMI/SCI generated from PM module.
-	 * Either hardware autimatically generates,
-	 * or set SCIB/SMIB bit in HIPMIC register.
-	 */
-	SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SCIE);
-	SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SMIE);
-#endif
-	lpc_task_enable_irq();
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	/* Update host events now that we can copy them to memmap */
-	lpc_update_host_event_status();
-
-	/*
-	 * TODO: For testing LPC with Chromebox, please make sure LPC_CLK is
-	 * generated before executing this function. EC needs LPC_CLK to access
-	 * LPC register through SIB module. For Chromebook platform, this
-	 * functionality should be done by BIOS or executed in hook function of
-	 * HOOK_CHIPSET_STARTUP
-	 */
-#ifdef BOARD_NPCX_EVB
-	/* initial IO port address via SIB-write modules */
-	host_register_init();
-#else
-#ifndef CONFIG_HOSTCMD_ESPI
-	/*
-	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
-	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
-	 * signal instead. WUI57 of table 0 is set when EC receives
-	 * LRESET/PLTRST from either VW or GPIO. Since WUI57 of table 0 and
-	 * WUI15 of table 2 are issued at the same time in case of eSPI, there
-	 * is no need to indicate LRESET/PLTRST via two sources. Thus, do not
-	 * initialize LRESET# interrupt in case of eSPI.
-	 */
-	/* Set detection mode to edge */
-	CLEAR_BIT(NPCX_WKMOD(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-	/* Handle interrupting on any edge */
-	SET_BIT(NPCX_WKAEDG(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-	/* Enable wake-up input sources */
-	SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7);
-#endif
-#endif
-}
-/*
- * Set prio to higher than default; this way LPC memory mapped data is ready
- * before other inits try to initialize their memmap data.
- */
-DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
-
-#if DEBUG_LPC
-static int command_lpc(int argc, char **argv)
-{
-	if (argc == 1)
-		return EC_ERROR_PARAM1;
-
-	if (!strcasecmp(argv[1], "sci"))
-		lpc_generate_sci();
-	else if (!strcasecmp(argv[1], "smi"))
-		lpc_generate_smi();
-	else if (!strcasecmp(argv[1], "wake"))
-		lpc_update_wake(-1);
-	else
-		return EC_ERROR_PARAM1;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", "Trigger SCI/SMI");
-
-#endif
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
deleted file mode 100644
index 607fdde5fa..0000000000
--- a/chip/npcx/lpc_chip.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific hwtimer module for Chrome EC */
-
-#ifndef __CROS_EC_LPC_CHIP_H
-#define __CROS_EC_LPC_CHIP_H
-
-/* For host registers initialization via SIB module */
-void host_register_init(void);
-
-/* eSPI Initialization functions */
-void espi_init(void);
-/* eSPI reset assert/de-assert interrupt */
-void espi_espirst_handler(void);
-/* LPC PLTRST assert/de-assert interrupt */
-void lpc_lreset_pltrst_handler(void);
-#endif /* __CROS_EC_LPC_CHIP_H */
diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c
deleted file mode 100644
index badfbd87d9..0000000000
--- a/chip/npcx/peci.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "peci.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-
-/* Initial PECI baud rate */
-#define PECI_BAUD_RATE        750000
-
-#define TEMP_AVG_LENGTH       4  /* Should be power of 2 */
-
-
-/* PECI Time-out */
-#define PECI_DONE_TIMEOUT_US  (10*MSEC)
-
-#define NULL_PENDING_TASK_ID  0xFFFFFFFF
-#define PECI_MAX_FIFO_SIZE    16
-#define PROC_SOCKET           0x30
-/* PECI Command Code */
-enum peci_command_t {
-	PECI_COMMAND_PING               = 0x00,
-	PECI_COMMAND_GET_DIB            = 0xF7,
-	PECI_COMMAND_GET_TEMP           = 0x01,
-	PECI_COMMAND_RD_PKG_CFG         = 0xA1,
-	PECI_COMMAND_WR_PKG_CFG         = 0xA5,
-	PECI_COMMAND_RD_IAMSR           = 0xB1,
-	PECI_COMMAND_RD_PCI_CFG         = 0x61,
-	PECI_COMMAND_RD_PCI_CFG_LOCAL   = 0xE1,
-	PECI_COMMAND_WR_PCI_CFG_LOCAL   = 0xE5,
-	PECI_COMMAND_NONE               = 0xFF
-};
-
-#define PECI_COMMAND_GET_TEMP_WR_LENS 0x00
-#define PECI_COMMAND_GET_TEMP_RD_LENS 0x02
-
-/* PECI Domain Number */
-static int temp_vals[TEMP_AVG_LENGTH];
-static int temp_idx;
-static uint8_t peci_sts;
-/* For PECI Done interrupt usage */
-static int peci_pending_task_id;
-
-/*****************************************************************************/
-/* Internal functions */
-
-/**
- * This routine initiates the parameters of a PECI transaction
- *
- * @param   wr_length How many byte of *wr_data went to be send
- * @param   rd_length How many byte went to received (not include FCS)
- * @param   cmd_code  Command code
- * @param   *wr_data  Buffer pointer of write data
- * @return  TASK_EVENT_PECI_DONE that mean slave had a response
- */
-static uint32_t peci_trans(
-		uint8_t             wr_length,
-		uint8_t             rd_length,
-		enum peci_command_t cmd_code,
-		uint8_t            *wr_data
-)
-{
-	uint32_t events;
-	/* Ensure no PECI transaction is in progress */
-	if (IS_BIT_SET(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_START_BUSY)) {
-		/*
-		 * PECI transaction is in progress -
-		 * can not initiate a new one
-		 */
-		return 0;
-	}
-	/* Set basic transaction parameters */
-	NPCX_PECI_ADDR = PROC_SOCKET;
-	NPCX_PECI_CMD = cmd_code;
-	/* Aviod over space */
-	if (rd_length > PECI_MAX_FIFO_SIZE)
-		rd_length = PECI_MAX_FIFO_SIZE;
-	/* Read-Length */
-	NPCX_PECI_RD_LENGTH = rd_length;
-	if (wr_length > PECI_MAX_FIFO_SIZE)
-		wr_length = PECI_MAX_FIFO_SIZE;
-	/* copy of data */
-	for (events = 0; events < wr_length; events++)
-		NPCX_PECI_DATA_OUT(events) = wr_data[events];
-	/* Write-Length */
-	if (cmd_code != PECI_COMMAND_PING) {
-		if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) ||
-				(cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
-			/*CMD+AWFCS*/
-			NPCX_PECI_WR_LENGTH = wr_length + 2;
-			/* Enable AWFCS */
-			SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_AWFCS_EN);
-		} else {
-			/*CMD*/
-			NPCX_PECI_WR_LENGTH = wr_length + 1;
-			/* Enable AWFCS */
-			CLEAR_BIT(NPCX_PECI_CTL_STS,
-					NPCX_PECI_CTL_STS_AWFCS_EN);
-		}
-	}
-
-	/* Start the PECI transaction */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_START_BUSY);
-
-	/* It should be using a interrupt , don't waste cpu computing power */
-	peci_pending_task_id = task_get_current();
-	return task_wait_event_mask(TASK_EVENT_PECI_DONE,
-					PECI_DONE_TIMEOUT_US);
-
-}
-
-/**
- * PECI transaction error status.
- *
- * @return  Bit3 - CRC error Bit4 - ABRT error
- */
-static uint8_t peci_check_error_state(void)
-{
-	return peci_sts;
-}
-
-/*****************************************************************************/
-/* PECI drivers */
-int peci_get_cpu_temp(void)
-{
-	uint32_t events;
-	int16_t cpu_temp = -1;
-
-	/* Start PECI trans */
-	events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS,
-				PECI_COMMAND_GET_TEMP_RD_LENS,
-				PECI_COMMAND_GET_TEMP, NULL);
-	/* if return DONE , that mean slave had a PECI response */
-	if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) {
-		/* check CRC & ABRT */
-		events = peci_check_error_state();
-		if (events) {
-			;
-		} else {
-			uint16_t *ptr;
-			ptr = (uint16_t *)&cpu_temp;
-			ptr[0] = (NPCX_PECI_DATA_IN(1) << 8) |
-				 (NPCX_PECI_DATA_IN(0) << 0);
-		}
-	}
-	return (int)cpu_temp;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int sum = 0;
-	int success_cnt = 0;
-	int i;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i) {
-		if (temp_vals[i] >= 0) {
-			success_cnt++;
-			sum += temp_vals[i];
-		}
-	}
-
-	/*
-	 * Require at least two valid samples. When the AP transitions into S0,
-	 * it is possible, depending on the timing of the PECI sample, to read
-	 * an invalid temperature. This is very rare, but when it does happen
-	 * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
-	 * samples here assures us that one bad maximum temperature reading
-	 * when entering S0 won't cause us to trigger an over temperature.
-	 */
-	if (success_cnt < 2)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = sum / success_cnt;
-	return EC_SUCCESS;
-}
-
-static void peci_temp_sensor_poll(void)
-{
-	int val;
-
-	val = peci_get_cpu_temp();
-	if (val != -1) {
-		temp_vals[temp_idx] = val;
-		temp_idx = (temp_idx + 1) & (TEMP_AVG_LENGTH - 1);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, peci_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static void peci_freq_changed(void)
-{
-	/* PECI's clock source is FMCLK */
-	int freq = clock_get_fm_freq();
-	int baud = 0xF;
-
-	/* Disable polling while reconfiguring */
-	NPCX_PECI_CTL_STS = 0;
-
-	/*
-	 * Set the maximum bit rate used by the PECI module during both
-	 * Address Timing Negotiation and Data Timing Negotiation.
-	 * The resulting maximum bit rate MAX_BIT_RATE in decimal is
-	 * according to the following formula:
-	 *
-	 * MAX_BIT_RATE [d] = (freq / (4 * baudrate)) - 1
-	 * Maximum bit rate should not extend the field's boundaries.
-	 */
-	if (freq != 0) {
-		baud = (uint8_t)(freq  / (4 * PECI_BAUD_RATE)) - 1;
-		/* Set maximum PECI baud rate (bit0 - bit4) */
-		if (baud > 0x1F)
-			baud = 0x1F;
-	}
-	/* Enhanced High-Speed */
-	if (baud >= 7) {
-		CLEAR_BIT(NPCX_PECI_RATE, 6);
-		CLEAR_BIT(NPCX_PECI_CFG, 3);
-	} else {
-		SET_BIT(NPCX_PECI_RATE, 6);
-		SET_BIT(NPCX_PECI_CFG, 3);
-	}
-	/* Setting Rate */
-	NPCX_PECI_RATE = baud;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, peci_freq_changed, HOOK_PRIO_DEFAULT);
-
-static void peci_init(void)
-{
-	int i;
-
-	/* Enable clock for PECI peripheral */
-	clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/* Set PECI freq */
-	peci_freq_changed();
-
-	/* make sure PECI_DATA function pin enable */
-	CLEAR_BIT(NPCX_DEVALT(0x0A), 6);
-	/* Set initial clock frequency */
-	peci_freq_changed();
-	/* Initialize temperature reading buffer to a valid value. */
-	for (i = 0; i < TEMP_AVG_LENGTH; ++i)
-		temp_vals[i] = 300; /* 27 C */
-
-	/* init Pending task id */
-	peci_pending_task_id = NULL_PENDING_TASK_ID;
-	/* Enable PECI Done interrupt */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_DONE_EN);
-
-	task_enable_irq(NPCX_IRQ_PECI);
-}
-DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
-
-/* If received a PECI DONE interrupt, post the event to PECI task */
-void peci_done_interrupt(void){
-	if (peci_pending_task_id != NULL_PENDING_TASK_ID)
-		task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE);
-	peci_sts = NPCX_PECI_CTL_STS & 0x18;
-	/* no matter what, clear status bit again */
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_DONE);
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_CRC_ERR);
-	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_ABRT_ERR);
-}
-DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t = peci_get_cpu_temp();
-	if (t == -1) {
-		ccprintf("PECI response timeout\n");
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-		NULL,
-		"Print CPU temperature");
diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c
deleted file mode 100644
index 7b8086cbcd..0000000000
--- a/chip/npcx/ps2.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PS/2 module for Chrome EC */
-#include "atomic.h"
-#include "clock.h"
-#include "console.h"
-#include "hooks.h"
-#include "gpio.h"
-#include "ps2_chip.h"
-#include "task.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
-
-#if !(DEBUG_PS2)
-#define DEBUG_CPRINTS(...)
-#define DEBUG_CPRINTF(...)
-#else
-#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
-#endif
-
-/*
- * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
- * reset the shift mechanism.
- */
-#define PS2_SHIFT_MECH_RESET       0x47
-
-#define PS2_TRANSACTION_TIMEOUT    (20 * MSEC)
-#define PS2_BUSY_RETRY             10
-
-enum ps2_input_debounce_cycle {
-	PS2_IDB_1_CYCLE,
-	PS2_IDB_2_CYCLE,
-	PS2_IDB_4_CYCLE,
-	PS2_IDB_8_CYCLE,
-	PS2_IDB_16_CYCLE,
-	PS2_IDB_32_CYCLE,
-};
-
-enum ps2_opr_mode {
-	PS2_TX_MODE,
-	PS2_RX_MODE,
-};
-
-struct ps2_data {
-	/* PS/2 module operation mode */
-	uint8_t opr_mode;
-	/*
-	 * The callback function to process data received from PS/2 device.
-	 * Note: this is called in the PS/2 interrupt handler
-	 */
-	void (*rx_handler_cb)(uint8_t data);
-};
-static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = {
-	 [0 ... (NPCX_PS2_CH_COUNT - 1)] =  { PS2_RX_MODE, NULL }
-};
-
-/*
- * Bitmap to record the enabled PS/2 channel by upper layer.
- * Only bit[7 and bit[5:3] are used
- * (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
- */
-static uint32_t channel_enabled_mask;
-static struct mutex ps2_lock;
-static volatile task_id_t task_waiting = TASK_ID_INVALID;
-
-static void ps2_init(void)
-{
-	/* Disable the power down bit of PS/2 */
-	clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Disable shift mechanism and configure PS/2 to received mode. */
-	NPCX_PS2_PSCON = 0x0;
-	/* Set WDAT3-0 and clear CLK3-0 before enabling shift mechanism */
-	NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-
-	/*
-	 * PS/2 interrupt enable register
-	 * [0] - : SOTIE   = 1: Start Of Transaction Interrupt Enable
-	 * [1] - : EOTIE   = 1: End Of Transaction Interrupt Enable
-	 * [4] - : WUE     = 1: Wake-Up Enable
-	 * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock
-	 */
-	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) |
-				BIT(NPCX_PS2_PSIEN_EOTIE) |
-				BIT(NPCX_PS2_PSIEN_PS2_WUE) |
-				BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
-
-	/* Enable weak internal pull-up */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED);
-	/* Enable shift mechanism */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_EN);
-
-	/* Configure pins from GPIOs to PS/2 interface */
-	gpio_config_module(MODULE_PS2, 1);
-	task_enable_irq(NPCX_IRQ_PS2);
-}
-DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT);
-
-void ps2_enable_channel(int channel, int enable,
-					void (*callback)(uint8_t data))
-{
-	if (channel >= NPCX_PS2_CH_COUNT) {
-		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
-		return;
-	}
-
-	/*
-	 * Disable the interrupt during changing the enabled channel mask to
-	 * prevent from preemption
-	 */
-	interrupt_disable();
-	if (enable) {
-		ps2_ch_data[channel].rx_handler_cb = callback;
-		channel_enabled_mask |= BIT(NPCX_PS2_PSOSIG_CLK(channel));
-		/* Enable the relevant channel clock */
-		SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-	} else {
-		channel_enabled_mask &=  ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
-		/* Disable the relevant channel clock */
-		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-		ps2_ch_data[channel].rx_handler_cb = NULL;
-	}
-	interrupt_enable();
-}
-
-/* Check if the shift mechanism is busy */
-static int ps2_is_busy(void)
-{
-	/*
-	 * The driver pulls the CLK for non-active channels to low when Start
-	 * bit is detected and pull the CLK of the active channel low after
-	 * Stop bit detected. The EOT bit is set when Stop bit is detected,
-	 * but both SOT and EOT are cleared when all CLKs are pull low
-	 * (due to Shift Mechanism is reset)
-	 */
-	return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) |
-		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0;
-}
-
-int ps2_transmit_byte(int channel, uint8_t data)
-{
-	int event;
-
-	uint8_t busy_retry = PS2_BUSY_RETRY;
-
-	if (channel >= NPCX_PS2_CH_COUNT) {
-		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!(BIT(NPCX_PS2_PSOSIG_CLK(channel)) & channel_enabled_mask)) {
-		CPRINTS("Err: PS/2 Tx w/o enabling CH");
-		return EC_ERROR_INVAL;
-	}
-
-	mutex_lock(&ps2_lock);
-	while (ps2_is_busy()) {
-		usleep(PS2_TRANSACTION_TIMEOUT);
-		if (busy_retry == 0) {
-			mutex_unlock(&ps2_lock);
-			return EC_ERROR_BUSY;
-		}
-		busy_retry--;
-	}
-
-	task_waiting = task_get_current();
-	ps2_ch_data[channel].opr_mode = PS2_TX_MODE;
-
-	/* Set PS/2 in transmit mode */
-	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-	/* Enable Start Of Transaction interrupt */
-	SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-
-	/* Reset the shift mechanism */
-	NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-	/* Inhibit communication should last at least 100 micro-seconds */
-	udelay(100);
-
-	/* Write the data to be transmitted */
-	NPCX_PS2_PSDAT = data;
-	/* Apply the Request-to-send */
-	CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_WDAT(channel));
-	SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
-
-	/* Wait for interrupt */
-	event = task_wait_event_mask(TASK_EVENT_PS2_DONE,
-					PS2_TRANSACTION_TIMEOUT);
-	task_waiting = TASK_ID_INVALID;
-
-	if (event == TASK_EVENT_TIMER) {
-		task_disable_irq(NPCX_IRQ_PS2);
-		CPRINTS("PS/2 Tx timeout");
-		/* Reset the shift mechanism */
-		NPCX_PS2_PSOSIG = PS2_SHIFT_MECH_RESET;
-		/* Change the PS/2 module to receive mode */
-		CLEAR_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-		/* Restore the channel to Receive mode */
-		ps2_ch_data[channel].opr_mode = PS2_RX_MODE;
-		/*
-		 * Restore the enabled channel according to channel_enabled_mask
-		 */
-		NPCX_PS2_PSOSIG |= channel_enabled_mask;
-		task_enable_irq(NPCX_IRQ_PS2);
-	}
-	mutex_unlock(&ps2_lock);
-
-	DEBUG_CPRINTF("Evt:0x%08x\n", event);
-	return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-
-}
-
-static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
-{
-	uint8_t mask;
-
-	mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL |
-					BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
-	NPCX_PS2_PSOSIG &= mask;
-
-}
-
-static int ps2_is_rx_error(uint8_t ch)
-{
-	uint8_t	status;
-
-	status = NPCX_PS2_PSTAT &
-				(BIT(NPCX_PS2_PSTAT_PERR) |
-				 BIT(NPCX_PS2_PSTAT_RFERR));
-	if (status) {
-
-		if (status & BIT(NPCX_PS2_PSTAT_PERR))
-			CPRINTF("PS2 CH %d RX parity error\n", ch);
-		if (status & BIT(NPCX_PS2_PSTAT_RFERR))
-			CPRINTF("PS2 CH %d RX Frame error\n", ch);
-		return 1;
-	} else
-		return 0;
-}
-
-void ps2_int_handler(void)
-{
-	uint8_t active_ch;
-
-	DEBUG_CPRINTS("PS2 INT");
-	/*
-	 * ACH = 1 : CHannel 0
-	 * ACH = 2 : CHannel 1
-	 * ACH = 4 : CHannel 2
-	 * ACH = 5 : CHannel 3
-	 */
-	active_ch = GET_FIELD(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_ACH);
-	active_ch = active_ch > 2 ? (active_ch - 2) : (active_ch - 1);
-	DEBUG_CPRINTF("ACH:%0d-", active_ch);
-
-	/*
-	 * Inhibit PS/2 transaction of the other non-active channels by
-	 * pulling down the clock signal
-	 */
-	ps2_stop_inactive_ch_clk(active_ch);
-
-	/* PS/2 Start of Transaction */
-	if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) &&
-			IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
-		DEBUG_CPRINTF("SOT-");
-		/*
-		 * Once set, SOT is not cleared until the shift mechanism
-		 * is reset. Therefore, SOTIE should be cleared on the
-		 * first occurrence of an SOT interrupt.
-		 */
-		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-	/* PS/2 End of Transaction */
-	} else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) {
-		DEBUG_CPRINTF("EOT-");
-		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
-
-		/*
-		 * Clear the CLK of active channel to reset
-		 * the shift mechanism
-		 */
-		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(active_ch));
-
-		if (ps2_ch_data[active_ch].opr_mode == PS2_TX_MODE) {
-			/* Change the PS/2 module to receive mode */
-			CLEAR_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_XMT);
-			ps2_ch_data[active_ch].opr_mode = PS2_RX_MODE;
-			task_set_event(task_waiting, TASK_EVENT_PS2_DONE);
-		} else {
-			if (!ps2_is_rx_error(active_ch)) {
-				uint8_t data_read = NPCX_PS2_PSDAT;
-				struct ps2_data *ps2_ptr =
-							&ps2_ch_data[active_ch];
-
-				DEBUG_CPRINTF("Recv:0x%02x", data_read);
-				if (ps2_ptr->rx_handler_cb)
-					ps2_ptr->rx_handler_cb(data_read);
-			}
-		}
-
-		/* Restore the enabled channel */
-		NPCX_PS2_PSOSIG |= channel_enabled_mask;
-		/*
-		 * Re-enable the Start Of Transaction interrupt when
-		 * the shift mechanism is reset
-		 */
-		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
-	}
-	DEBUG_CPRINTF("\n");
-
-}
-DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5);
-
-#ifdef CONFIG_CMD_PS2
-static int command_ps2ench(int argc, char **argv)
-{
-	uint8_t ch;
-	uint8_t enable;
-	char *e;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	enable = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	if (enable)
-		ps2_enable_channel(ch, 1, NULL);
-	else
-		ps2_enable_channel(ch, 0, NULL);
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench,
-			"ps2_ench channel 1|0",
-			"Enable/Disable PS/2 channel");
-
-static int command_ps2write(int argc, char **argv)
-{
-	uint8_t ch, data;
-	char *e;
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-	data = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	ps2_transmit_byte(ch, data);
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write,
-		"ps2_write channel data",
-		"Write data byte to PS/2 channel ");
-#endif
diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h
deleted file mode 100644
index d88e6791ad..0000000000
--- a/chip/npcx/ps2_chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PS2_CHIP_H
-#define __CROS_EC_PS2_CHIP_H
-
-#include "common.h"
-
-enum npcx_ps2_channel {
-	NPCX_PS2_CH0,
-	NPCX_PS2_CH1,
-	NPCX_PS2_CH2,
-	NPCX_PS2_CH3,
-	NPCX_PS2_CH_COUNT
-};
-
-void ps2_enable_channel(int channel, int enable,
-			void (*callback)(uint8_t data));
-int ps2_transmit_byte(int channel, uint8_t data);
-
-#endif  /* __CROS_EC_PS2_CHIP_H */
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c
deleted file mode 100644
index b2016906b3..0000000000
--- a/chip/npcx/pwm.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for NPCX.
- *
- * On this chip, the PWM logic is implemented by the hardware FAN modules.
- */
-
-#include "assert.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "util.h"
-
-#if !(DEBUG_PWM)
-#define CPRINTS(...)
-#else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
-#endif
-
-/* pwm resolution for each channel */
-static uint32_t pwm_res[PWM_CH_COUNT];
-
-/* PWM clock source */
-enum npcx_pwm_source_clock {
-	NPCX_PWM_CLOCK_APB2_LFCLK  = 0,
-	NPCX_PWM_CLOCK_FX          = 1,
-	NPCX_PWM_CLOCK_FR          = 2,
-	NPCX_PWM_CLOCK_RESERVED    = 3,
-	NPCX_PWM_CLOCK_UNDEF       = 0xFF
-};
-
-/* PWM heartbeat mode */
-enum npcx_pwm_heartbeat_mode {
-	NPCX_PWM_HBM_NORMAL    = 0,
-	NPCX_PWM_HBM_25        = 1,
-	NPCX_PWM_HBM_50        = 2,
-	NPCX_PWM_HBM_100       = 3,
-	NPCX_PWM_HBM_UNDEF     = 0xFF
-};
-
-/**
- * Set PWM operation clock.
- *
- * @param   ch      operation channel
- * @param   freq    desired PWM frequency
- * @notes   changed when initialization
- */
-static void pwm_set_freq(enum pwm_channel ch, uint32_t freq)
-{
-	int mdl = pwm_channels[ch].channel;
-	uint32_t clock;
-	uint32_t pre;
-
-	assert(freq != 0);
-
-	/* Disable PWM for module configuration */
-	pwm_enable(ch, 0);
-
-	/*
-	 * Get PWM clock frequency. Use internal 32K as PWM clock source if
-	 * the PWM must be active during low-power idle.
-	 */
-	if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-		clock = INT_32K_CLOCK;
-	else
-		clock = clock_get_apb2_freq();
-
-	/* Calculate prescaler */
-	pre = DIV_ROUND_UP(clock, (0xffff * freq));
-
-	/*
-	 * Calculate maximum resolution for the given freq. and prescaler. And
-	 * prevent it exceed the resolution of CTR/DCR registers.
-	 */
-	pwm_res[ch] = MIN((clock / pre) / freq, NPCX_PWM_MAX_RAW_DUTY);
-
-	/* Set PWM prescaler. */
-	NPCX_PRSC(mdl) = pre - 1;
-
-	/* Set PWM cycle time */
-	NPCX_CTR(mdl) = pwm_res[ch];
-
-	/* Set the duty cycle to 100% since DCR == CTR */
-	NPCX_DCR(mdl) = pwm_res[ch];
-}
-
-/**
- * Set PWM enabled.
- *
- * @param   ch      operation channel
- * @param   enabled enabled flag
- */
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Start or close PWM module */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_PWR, enabled);
-}
-
-/**
- * Check PWM enabled.
- *
- * @param   ch  operation channel
- * @return  enabled or not
- */
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-	return IS_BIT_SET(NPCX_PWMCTL(mdl), NPCX_PWMCTL_PWR);
-}
-
-/**
- * Set PWM duty cycle.
- *
- * @param   ch      operation channel
- * @param   percent duty cycle percent
- */
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	/* Convert percent on [0, 100] to 16 bit duty */
-	pwm_set_raw_duty(ch, (percent * EC_PWM_MAX_DUTY) / 100);
-}
-
-/**
- * Set PWM duty cycle.
- *
- * @param   ch      operation channel
- * @param   duty    cycle duty
- */
-void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
-{
-	int mdl = pwm_channels[ch].channel;
-	uint32_t sd;
-
-	CPRINTS("pwm%d, set duty=%d", mdl, duty);
-
-	/* Assume the fan control is active high and invert it ourselves */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP,
-			(pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
-
-	CPRINTS("initial freq=0x%x", pwm_channels[ch].freq);
-	CPRINTS("duty_cycle_cnt=%d", duty);
-
-	/* duty ranges from 0 - 0xffff, so scale down to 0 - pwm_res[ch] */
-	sd = DIV_ROUND_NEAREST(duty * pwm_res[ch], EC_PWM_MAX_DUTY);
-
-	/* Set the duty cycle. If it is zero, set DCR > CTR */
-	NPCX_DCR(mdl) = sd ? sd : NPCX_PWM_MAX_RAW_DUTY + 1;
-}
-
-/**
- * Get PWM duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle percent
- */
-int pwm_get_duty(enum pwm_channel ch)
-{
-	/* duty ranges from 0 - 0xffff, so scale to 0 - 100 */
-	return DIV_ROUND_NEAREST(pwm_get_raw_duty(ch) * 100, EC_PWM_MAX_DUTY);
-}
-
-/**
- * Get PWM duty cycle.
- *
- * @param   ch  operation channel
- * @return  duty cycle
- */
-uint16_t pwm_get_raw_duty(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Return duty */
-	if (NPCX_DCR(mdl) > NPCX_CTR(mdl))
-		return 0;
-	else
-		/*
-		 * NPCX_DCR ranges from 0 - pwm_res[ch],
-		 * so scale to 0 - 0xffff
-		 */
-		return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY,
-						pwm_res[ch]);
-}
-
-/**
- * PWM configuration.
- *
- * @param  ch    operation channel
- */
-void pwm_config(enum pwm_channel ch)
-{
-	int mdl = pwm_channels[ch].channel;
-
-	/* Disable PWM for module configuration */
-	pwm_enable(ch, 0);
-
-	/* Set PWM heartbeat mode is no heartbeat */
-	SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD,
-			NPCX_PWM_HBM_NORMAL);
-
-	/* Select default CLK or LFCLK clock input to PWM module */
-	SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD,
-			NPCX_PWM_CLOCK_APB2_LFCLK);
-
-	/* Set PWM polarity normal first */
-	CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP);
-
-	/* Select PWM clock source */
-	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL,
-			(pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
-
-	/* Select PWM IO type */
-	UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT,
-			(pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
-
-	/* Set PWM operation frequency */
-	pwm_set_freq(ch, pwm_channels[ch].freq);
-}
-
-/**
- * PWM initial.
- */
-static void pwm_init(void)
-{
-	int i;
-	uint8_t pd_mask = 0;
-
-	/* Take enabled PWMs out of power-down state */
-	for (i = 0; i < PWM_CH_COUNT; i++) {
-		pd_mask |= (1 << pwm_channels[i].channel);
-		pwm_res[i] = 0;
-	}
-
-	clock_enable_peripheral(CGC_OFFSET_PWM, pd_mask, CGC_MODE_ALL);
-
-	for (i = 0; i < PWM_CH_COUNT; i++)
-		pwm_config(i);
-}
-
-/* The chip-specific fan module initializes before this. */
-DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM);
diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h
deleted file mode 100644
index 7acfef81e5..0000000000
--- a/chip/npcx/pwm_chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/* PWM channel ID */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	/* PWM freq. */
-	uint32_t freq;
-};
-
-extern const struct pwm_t pwm_channels[];
-void pwm_config(enum pwm_channel ch);
-
-/* Npcx PWM maximum duty cycle value */
-#define NPCX_PWM_MAX_RAW_DUTY (UINT16_MAX - 1)
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h
deleted file mode 100644
index c441c1c926..0000000000
--- a/chip/npcx/registers-npcx5.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX5 family of chips.
- *
- * Support chip variant:
- * - npcx5m5g
- * - npcx5m6g
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ8_NOUSED		NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ16_NOUSED		NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ19_NOUSED		NPCX_IRQ_19
-#define NPCX_IRQ20_NOUSED		NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ32_NOUSED		NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
-
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)	(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)))
-
-enum {
-	NPCX_UART_PORT0 = 0, /* UART port 0 */
-	NPCX_UART_COUNT
-};
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C0_1_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C3_0_SL		6
-
-/* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
-
-/* pin-mux for Misc. */
-/* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB0SEL		0
-
-/* SMB enumeration: I2C port definitions. */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT0_1,	/* I2C port 0, bus 1 */
-	NPCX_I2C_PORT1,		/* I2C port 1 */
-	NPCX_I2C_PORT2,		/* I2C port 2 */
-	NPCX_I2C_PORT3,		/* I2C port 3 */
-	NPCX_I2C_COUNT,
-};
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD))
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
-
-/* ITIM registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
-/* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM16_1,
-	ITIM16_2,
-	ITIM16_3,
-	ITIM16_4,
-	ITIM16_5,
-	ITIM16_6,
-	ITIM32,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers */
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INTWK_EN			VWEVMS_INT_EN
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_66 = 4,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#elif (FMCLK <= 48000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_66
-#endif
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_WK_GROUP		6
-#define NPCX_UART_WK_BIT		4
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#else /* !NPCX_UART_MODULE2 */
-
-#define NPCX_UART_WK_GROUP		1
-#define NPCX_UART_WK_BIT		0
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* This routine checks pending bit of GPIO wake-up functionality */
-static inline int uart_is_wakeup_from_gpio(void)
-{
-	return IS_BIT_SET(NPCX_WKPND(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine checks wake-up functionality from GPIO is enabled or not */
-static inline int uart_is_enable_wakeup(void)
-{
-	return IS_BIT_SET(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine clears the pending wake-up from GPIO on UART rx pin */
-static inline void uart_clear_pending_wakeup(void)
-{
-	SET_BIT(NPCX_WKPCL(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT);
-}
-
-/* This routine enables wake-up functionality from GPIO on UART rx pin */
-static inline void uart_enable_wakeup(int enable)
-{
-	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT,
-		enable);
-}
-
-/* This routine checks functionality is UART rx or not */
-static inline int npcx_is_uart(void)
-{
-	return IS_BIT_SET(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-}
-
-/* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-
-/* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h
deleted file mode 100644
index 535abfbf0f..0000000000
--- a/chip/npcx/registers-npcx7.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX7 family of chips.
- *
- * Support chip variant:
- * - npcx7m6g
- * - npcx7m6f
- * - npcx7m6fb
- * - npcx7m6fc
- * - npcx7m7fc
- * - npcx7m7wb
- * - npcx7m7wc
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ4_NOUSED		NPCX_IRQ_4
-#else
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#endif
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ_WOV			NPCX_IRQ_22
-#else
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#endif
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#else
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#endif
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
-
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 +	((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
-
-enum {
-	NPCX_UART_PORT0 = 0, /* UART port 0 */
-#ifdef NPCX_SECOND_UART
-	NPCX_UART_PORT1 = 1, /* UART port 1 */
-#endif
-	NPCX_UART_COUNT
-};
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-/* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
-
-/* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
-#endif
-
-/* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
-
-/* GLUE registers */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#endif
-
-/* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT2_I2C4_0_SL		7
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
-
-/* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-
-/* pin-mux for PSL */
-#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
-#endif
-
-#ifdef CHIP_VARIANT_NPCX7M6G
-/* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
-#endif
-
-/* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
-#ifdef NPCX_SECOND_UART
-/* Secondary UART selection */
-#define NPCX_DEVALTA_UART2_SL		5
-#endif
-
-/* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
-
-#ifdef NPCX_WOV_SUPPORT
-/* pin-mux for WoV */
-#define NPCX_DEVALTE_WOV_SL		0
-#define NPCX_DEVALTE_I2S_SL		1
-#define NPCX_DEVALTE_DMCLK_FAST		2
-#endif
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
-
-/* SMB enumeration: I2C port definitions */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-#ifdef CHIP_VARIANT_NPCX7M6G
-	NPCX_I2C_PORT4_0,	/* I2C port 4, bus 0 */
-#endif
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
-	NPCX_I2C_COUNT,
-};
-
-/* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
-
-/* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#endif
-#ifdef NPCX_SECOND_UART
-#define NPCX_PWDWN_CTL7_UART2_PD	6
-#endif
-#ifdef NPCX_WOV_SUPPORT
-#define NPCX_PWDWN_CTL7_WOV_PD		7
-#endif
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-	CGC_OFFSET_I2C2 = 6,
-#ifdef NPCX_SECOND_UART
-	CGC_OFFSET_UART2 = 6,
-#endif
-#ifdef NPCX_WOV_SUPPORT
-	CGC_OFFSET_WOV	= 6,
-#endif
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_7 = 6,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#ifdef NPCX_SECOND_UART
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
-#endif
-#ifdef NPCX_WOV_SUPPORT
-#define CGC_WOV_MASK			BIT(NPCX_PWDWN_CTL7_WOV_PD)
-#endif
-
-/* BBRAM register fields */
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
-	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
-#else
-#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
-#endif
-
-/* ITIM16 registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
-/* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM16_1,
-	ITIM16_2,
-	ITIM16_3,
-	ITIM16_4,
-	ITIM16_5,
-	ITIM16_6,
-	ITIM32,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
-
-/* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
-
-/* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#endif
-
-/* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#ifdef NPCX_SECOND_UART
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
-#endif
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-
-/* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h
deleted file mode 100644
index 1d2a02084c..0000000000
--- a/chip/npcx/registers-npcx9.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Specific register map for NPCX9 family of chips.
- *
- * Support chip variant:
- * - npcx993f
- * - npcx996f
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ_MTC_WKINTD_0		NPCX_IRQ_5
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTD_0
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_CR_SIN2_WKINTA_0	NPCX_IRQ_7
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTE_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM32_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM32_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM32_1		NPCX_IRQ_28
-#define NPCX_I3C_MDMA5			NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ_WKINTF_0		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ_UART3			NPCX_IRQ_38
-#define NPCX_IRQ_UART4			NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ_WKINTG_0		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM32_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM32_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM32_6		NPCX_IRQ_45
-#define NPCX_IRQ_WKINTH_0		NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_WKINTG_2			NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#define NPCX_IRQ_LCT_WKINTF_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
-/* MIWU definition */
-#define LCT_WUI_GROUP			MIWU_GROUP_6
-#define LCT_WUI_MASK			MASK_PIN7
-
-/* Modules Map */
-
-/* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x009)
-
-/* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		6
-#define NPCX_FWCTRL_FW_SLOT		7
-
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400E0000 + ((mdl) * 0x2000L))
-#define NPCX_LCT_BASE_ADDR		0x400D7000
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
-
-enum {
-	NPCX_UART_PORT0 = 0,	/* UART port 0 */
-	NPCX_UART_PORT1 = 1,	/* UART port 1 */
-	NPCX_UART_PORT2 = 2,	/* UART port 2 */
-	NPCX_UART_PORT3 = 3,	/* UART port 3 */
-	NPCX_UART_COUNT
-};
-
- /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
-
-/* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
-
-/* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
-
-/* GLUE registers */
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#define NPCX_GLUE_PSL_MCTL1		REG8(NPCX_GLUE_REGS_BASE + 0x034)
-#define NPCX_GLUE_PSL_MCTL2		REG8(NPCX_GLUE_REGS_BASE + 0x038)
-
-/* PSL register fields */
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL	7
-#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL		6
-#define NPCX_GLUE_PSL_MCTL1_LCT_EV		4
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV		3
-#define NPCX_GLUE_PSL_MCTL1_PLS_EN		1
-#define NPCX_GLUE_PSL_MCTL1_OD_EN		0
-
-#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK	7
-#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN		6
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN	3
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL		FIELD(0, 1)
-
-/* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
-
-/* System Configuration (SCFG) Registers */
-
-/* SCFG enumeration */
-enum {
-	ALT_GROUP_0,
-	ALT_GROUP_1,
-	ALT_GROUP_2,
-	ALT_GROUP_3,
-	ALT_GROUP_4,
-	ALT_GROUP_5,
-	ALT_GROUP_6,
-	ALT_GROUP_7,
-	ALT_GROUP_8,
-	ALT_GROUP_9,
-	ALT_GROUP_A,
-	ALT_GROUP_B,
-	ALT_GROUP_C,
-	ALT_GROUP_D,
-	ALT_GROUP_E,
-	ALT_GROUP_F,
-	ALT_GROUP_G,
-	ALT_GROUP_H,
-	ALT_GROUP_J,
-	ALT_GROUP_COUNT
-};
-
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
-/* Device Alternate Function Lock */
-#define NPCX_DEVALT_LK(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
-
-/* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
-
-/* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-#define NPCX_DEVALTF_ADC10_SL		5
-#define NPCX_DEVALTF_ADC11_SL		6
-
-/* pin-mux for PSL */
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
-
-/* pin-mux for Misc. */
-
-/* pin-mux for UART */
-#define NPCX_DEVALTJ_CR_SIN1_SL1	0
-#define NPCX_DEVALTJ_CR_SOUT1_SL1	1
-#define NPCX_DEVALTJ_CR_SIN1_SL2	2
-#define NPCX_DEVALTJ_CR_SOUT1_SL2	3
-#define NPCX_DEVALTJ_CR_SIN2_SL		4
-#define NPCX_DEVALTJ_CR_SOUT2_SL	5
-#define NPCX_DEVALTJ_CR_SIN3_SL		6
-#define NPCX_DEVALTJ_CR_SOUT3_SL	7
-#define NPCX_DEVALTE_CR_SIN4_SL		6
-#define NPCX_DEVALTE_CR_SOUT4_SL	7
-
-/* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
-
-/* VCC_RST Pull-Up Disable */
-#define NPCX_DEVALTG_VCC1_RST_PUD	5
-#define NPCX_DEVALTG_PSL_OUT_SL		6
-#define NPCX_DEVALTG_PSL_GPO_SL		7
-
-/* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
-
-/* pin-mux for JTAG */
-#define NPCX_JEN_CTL1			REG8(NPCX_SCFG_BASE_ADDR + 0x120)
-#define NPCX_JEN_CTL1_JEN_EN_FIELD	FIELD(0, 4)
-#define NPCX_JEN_CTL1_JEN_EN_DIS	0x06
-#define NPCX_JEN_CTL1_JEN_EN_ENA	0x09
-
-/* SMB enumeration: I2C port definitions. */
-enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
-	NPCX_I2C_COUNT,
-};
-
-/* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
-
-/* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#define NPCX_PWDWN_CTL7_UART2_PD	6
-
-/*
- * PMC enumeration:
- * Offsets from CGC_BASE registers for each peripheral.
- */
-enum {
-	CGC_OFFSET_KBS = 0,
-	CGC_OFFSET_UART = 0,
-	CGC_OFFSET_FAN = 0,
-	CGC_OFFSET_FIU = 0,
-	CGC_OFFSET_PS2 = 0,
-	CGC_OFFSET_PWM = 1,
-	CGC_OFFSET_I2C = 2,
-	CGC_OFFSET_ADC = 3,
-	CGC_OFFSET_PECI = 3,
-	CGC_OFFSET_SPI = 3,
-	CGC_OFFSET_TIMER = 3,
-	CGC_OFFSET_LPC = 4,
-	CGC_OFFSET_ESPI = 5,
-	CGC_OFFSET_I2C2 = 6,
-	CGC_OFFSET_UART2 = 6,
-};
-
-enum NPCX_PMC_PWDWN_CTL_T {
-	NPCX_PMC_PWDWN_1 = 0,
-	NPCX_PMC_PWDWN_2 = 1,
-	NPCX_PMC_PWDWN_3 = 2,
-	NPCX_PMC_PWDWN_4 = 3,
-	NPCX_PMC_PWDWN_5 = 4,
-	NPCX_PMC_PWDWN_6 = 5,
-	NPCX_PMC_PWDWN_7 = 6,
-	NPCX_PMC_PWDWN_CNT,
-};
-
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
-	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
-
-/* ITIM registers */
-#define NPCX_ITCNT32(n)			REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
-
-/* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32(ITIM32_6)
-/* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT32
-
-/* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM32_1
-/* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO				ITIM32_5
-/* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32_6
-
-/* ITIM enumeration */
-enum ITIM_MODULE_T {
-	ITIM32_1,
-	ITIM32_2,
-	ITIM32_3,
-	ITIM32_4,
-	ITIM32_5,
-	ITIM32_6,
-	ITIM_MODULE_COUNT,
-};
-
-/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
-
-/* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
-
-/* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
-
-/* eSPI max supported frequency */
-enum {
-	NPCX_ESPI_MAXFREQ_20 = 0,
-	NPCX_ESPI_MAXFREQ_25 = 1,
-	NPCX_ESPI_MAXFREQ_33 = 2,
-	NPCX_ESPI_MAXFREQ_50 = 3,
-	NPCX_ESPI_MAXFREQ_66 = 4,
-	NPCX_ESPI_MAXFREQ_NONE = 0xFF
-};
-
-/* eSPI Operating Frequency */
-enum {
-	NPCX_ESPI_OPFREQ_20 = 0,
-	NPCX_ESPI_OPFREQ_25 = 1,
-	NPCX_ESPI_OPFREQ_33 = 2,
-	NPCX_ESPI_OPFREQ_50 = 3,
-	NPCX_ESPI_OPFREQ_66 = 4,
-	NPCX_ESPI_OPFREQ_NONE = 0xFF
-};
-
-/* eSPI max frequency support per FMCLK */
-#if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
-#else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
-#endif
-
-/* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
-
-/* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 0x10))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 0x10))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x02 + \
-					((n) * 0x10))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x03 + \
-					((n) * 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x04 + \
-					((n) * 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x05 + \
-					((n) * 0x10))
-#define NPCX_WKST_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x06 + \
-					((n) * 0x10))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + \
-					((n) * 0x10))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKST(port, n)		REG8(NPCX_WKST_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
-
-/* LCT register */
-#define NPCX_LCTCONT			REG8(NPCX_LCT_BASE_ADDR + 0x002)
-#define NPCX_LCTSTAT			REG8(NPCX_LCT_BASE_ADDR + 0x004)
-#define NPCX_LCTSECOND			REG8(NPCX_LCT_BASE_ADDR + 0x005)
-#define NPCX_LCTMINUTE			REG8(NPCX_LCT_BASE_ADDR + 0x006)
-#define NPCX_LCTHOUR			REG8(NPCX_LCT_BASE_ADDR + 0x008)
-#define NPCX_LCTDAY			REG8(NPCX_LCT_BASE_ADDR + 0x00A)
-#define NPCX_LCTWEEK			REG8(NPCX_LCT_BASE_ADDR + 0x00C)
-/* LCTCONT fields */
-#define NPCX_LCTCONT_EN			0
-#define NPCX_LCTCONT_EN_FIELD		FIELD(0, 1)
-#define NPCX_LCTCONT_EVEN		1
-#define NPCX_LCTCONT_PSL_EN		2
-#define NPCX_LCTCONT_CLK_EN		6
-#define NPCX_LCTCONT_VSBY_PWR		7
-/* LCTSTAT fields */
-#define NPCX_LCTSTAT_EVST		0
-
-/* UART registers and functions */
-#if NPCX_UART_MODULE2
-/*
- * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
- * always 1 == MIWU_TABLE_1.
- */
-#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#endif /* NPCX_UART_MODULE2 */
-
-/* ADC register */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
-/* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-/* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n)))
-
-/* ADC register fields */
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR6_IEN		13
-#define NPCX_THRCTS_THR5_IEN		12
-#define NPCX_THRCTS_THR4_IEN		11
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR6_STS		5
-#define NPCX_THRCTS_THR5_STS		4
-#define NPCX_THRCTS_THR4_STS		3
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH4		4
-#define NPCX_ADC_THRESH5		5
-#define NPCX_ADC_THRESH6		6
-#define NPCX_ADC_THRESH_CNT		6
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
deleted file mode 100644
index f0c241e7f9..0000000000
--- a/chip/npcx/registers.h
+++ /dev/null
@@ -1,1693 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for NPCX processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "clock_chip.h"
-
-/******************************************************************************/
-/*
- * Macro Functions
- */
-/* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
-/* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
-/* Read field functions */
-#define GET_FIELD(reg, field) \
-	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
-/* Write field functions */
-#define SET_FIELD(reg, field, value) \
-	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
-
-/******************************************************************************/
-/*
- * NPCX (Nuvoton M4 EC) Register Definitions
- */
-
-/* Global Definition */
-#define I2C_7BITS_ADDR                   0
-/* Switcher of features */
-#define SUPPORT_LCT                      1
-#define SUPPORT_WDG                      1
-#define SUPPORT_P80_SEG                  0 /* Note: it uses KSO10 & KSO11 */
-/* Switcher of debugging */
-#define DEBUG_GPIO                       0
-#define DEBUG_I2C                        0
-#define DEBUG_TMR                        0
-#define DEBUG_WDG                        0
-#define DEBUG_FAN                        0
-#define DEBUG_PWM                        0
-#define DEBUG_SPI                        0
-#define DEBUG_FLH                        0
-#define DEBUG_PECI                       0
-#define DEBUG_SHI                        0
-#define DEBUG_CLK                        0
-#define DEBUG_LPC                        0
-#define DEBUG_ESPI                       0
-#define DEBUG_CEC                        0
-#define DEBUG_SIB                        0
-#define DEBUG_PS2                        0
-
-/* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
-
-/* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
-
-/*
- * NPCX-IRQ numbers
- */
-#define NPCX_IRQ_0                       0
-#define NPCX_IRQ_1                       1
-#define NPCX_IRQ_2                       2
-#define NPCX_IRQ_3                       3
-#define NPCX_IRQ_4                       4
-#define NPCX_IRQ_5                       5
-#define NPCX_IRQ_6                       6
-#define NPCX_IRQ_7                       7
-#define NPCX_IRQ_8                       8
-#define NPCX_IRQ_9                       9
-#define NPCX_IRQ_10                      10
-#define NPCX_IRQ_11                      11
-#define NPCX_IRQ_12                      12
-#define NPCX_IRQ_13                      13
-#define NPCX_IRQ_14                      14
-#define NPCX_IRQ_15                      15
-#define NPCX_IRQ_16                      16
-#define NPCX_IRQ_17                      17
-#define NPCX_IRQ_18                      18
-#define NPCX_IRQ_19                      19
-#define NPCX_IRQ_20                      20
-#define NPCX_IRQ_21                      21
-#define NPCX_IRQ_22                      22
-#define NPCX_IRQ_23                      23
-#define NPCX_IRQ_24                      24
-#define NPCX_IRQ_25                      25
-#define NPCX_IRQ_26                      26
-#define NPCX_IRQ_27                      27
-#define NPCX_IRQ_28                      28
-#define NPCX_IRQ_29                      29
-#define NPCX_IRQ_30                      30
-#define NPCX_IRQ_31                      31
-#define NPCX_IRQ_32                      32
-#define NPCX_IRQ_33                      33
-#define NPCX_IRQ_34                      34
-#define NPCX_IRQ_35                      35
-#define NPCX_IRQ_36                      36
-#define NPCX_IRQ_37                      37
-#define NPCX_IRQ_38                      38
-#define NPCX_IRQ_39                      39
-#define NPCX_IRQ_40                      40
-#define NPCX_IRQ_41                      41
-#define NPCX_IRQ_42                      42
-#define NPCX_IRQ_43                      43
-#define NPCX_IRQ_44                      44
-#define NPCX_IRQ_45                      45
-#define NPCX_IRQ_46                      46
-#define NPCX_IRQ_47                      47
-#define NPCX_IRQ_48                      48
-#define NPCX_IRQ_49                      49
-#define NPCX_IRQ_50                      50
-#define NPCX_IRQ_51                      51
-#define NPCX_IRQ_52                      52
-#define NPCX_IRQ_53                      53
-#define NPCX_IRQ_54                      54
-#define NPCX_IRQ_55                      55
-#define NPCX_IRQ_56                      56
-#define NPCX_IRQ_57                      57
-#define NPCX_IRQ_58                      58
-#define NPCX_IRQ_59                      59
-#define NPCX_IRQ_60                      60
-#define NPCX_IRQ_61                      61
-#define NPCX_IRQ_62                      62
-#define NPCX_IRQ_63                      63
-
-#define NPCX_IRQ_COUNT                   64
-
-/******************************************************************************/
-/* High Frequency Clock Generator (HFCG) registers */
-#define NPCX_HFCGCTRL                     REG8(NPCX_HFCG_BASE_ADDR + 0x000)
-#define NPCX_HFCGML                       REG8(NPCX_HFCG_BASE_ADDR + 0x002)
-#define NPCX_HFCGMH                       REG8(NPCX_HFCG_BASE_ADDR + 0x004)
-#define NPCX_HFCGN                        REG8(NPCX_HFCG_BASE_ADDR + 0x006)
-#define NPCX_HFCGP                        REG8(NPCX_HFCG_BASE_ADDR + 0x008)
-#define NPCX_HFCBCD                       REG8(NPCX_HFCG_BASE_ADDR + 0x010)
-
-/* HFCG register fields */
-#define NPCX_HFCGCTRL_LOAD               0
-#define NPCX_HFCGCTRL_LOCK               2
-#define NPCX_HFCGCTRL_CLK_CHNG           7
-
-/******************************************************************************/
-/* Low Frequency Clock Generator (LFCG) registers */
-#define NPCX_LFCGCTL                      REG8(NPCX_LFCG_BASE_ADDR + 0x000)
-#define NPCX_HFRDI                       REG16(NPCX_LFCG_BASE_ADDR + 0x002)
-#define NPCX_HFRDF                       REG16(NPCX_LFCG_BASE_ADDR + 0x004)
-#define NPCX_FRCDIV                      REG16(NPCX_LFCG_BASE_ADDR + 0x006)
-#define NPCX_DIVCOR1                     REG16(NPCX_LFCG_BASE_ADDR + 0x008)
-#define NPCX_DIVCOR2                     REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
-#define NPCX_LFCGCTL2                     REG8(NPCX_LFCG_BASE_ADDR + 0x014)
-
-/* LFCG register fields */
-#define NPCX_LFCGCTL_XTCLK_VAL            7
-#define NPCX_LFCGCTL2_XT_OSC_SL_EN        6
-
-/******************************************************************************/
-/* CR UART Register */
-#define NPCX_UTBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
-#define NPCX_URBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
-#define NPCX_UICTRL(n)                   REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
-#define NPCX_USTAT(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
-#define NPCX_UFRS(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
-#define NPCX_UMDSL(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
-#define NPCX_UBAUD(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
-#define NPCX_UPSR(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
-
-/******************************************************************************/
-/* KBSCAN registers */
-#define NPCX_KBSIN                        REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
-#define NPCX_KBSINPU                      REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
-#define NPCX_KBSOUT0                     REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
-#define NPCX_KBSOUT1                     REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
-#define NPCX_KBS_BUF_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
-#define NPCX_KBS_BUF_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
-#define NPCX_KBSEVT                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
-#define NPCX_KBSCTL                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
-#define NPCX_KBS_CFG_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
-#define NPCX_KBS_CFG_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
-
-/* KBSCAN register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSDONE                     0
-#define NPCX_KBSERR                      1
-#define NPCX_KBSSTART                    0
-#define NPCX_KBSMODE                     1
-#define NPCX_KBSIEN                      2
-#define NPCX_KBSINC                      3
-#define NPCX_KBSCFGINDX                  0
-
-/* KBSCAN definitions */
-#define KB_ROW_NUM  8  /* Rows numbers of keyboard matrix */
-#define KB_COL_NUM  18 /* Columns numbers of keyboard matrix */
-#define KB_ROW_MASK ((1<<KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
-
-/******************************************************************************/
-/* GLUE registers */
-#define NPCX_GLUE_SDPD0                   REG8(NPCX_GLUE_REGS_BASE + 0x010)
-#define NPCX_GLUE_SDPD1                   REG8(NPCX_GLUE_REGS_BASE + 0x012)
-#define NPCX_GLUE_SDP_CTS                 REG8(NPCX_GLUE_REGS_BASE + 0x014)
-#define NPCX_GLUE_SMBSEL                  REG8(NPCX_GLUE_REGS_BASE + 0x021)
-/******************************************************************************/
-
-/* MIWU enumeration */
-enum {
-	MIWU_TABLE_0,
-	MIWU_TABLE_1,
-	MIWU_TABLE_2,
-	MIWU_TABLE_COUNT
-};
-
-enum {
-	MIWU_GROUP_1,
-	MIWU_GROUP_2,
-	MIWU_GROUP_3,
-	MIWU_GROUP_4,
-	MIWU_GROUP_5,
-	MIWU_GROUP_6,
-	MIWU_GROUP_7,
-	MIWU_GROUP_8,
-	MIWU_GROUP_COUNT
-};
-
-enum {
-	MIWU_EDGE_RISING,
-	MIWU_EDGE_FALLING,
-	MIWU_EDGE_ANYING,
-};
-
-/* MIWU utilities */
-#define MIWU_TABLE_WKKEY MIWU_TABLE_1
-#define MIWU_GROUP_WKKEY MIWU_GROUP_3
-
-/******************************************************************************/
-/* GPIO registers */
-#define NPCX_PDOUT(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
-#define NPCX_PDIN(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
-#define NPCX_PDIR(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
-#define NPCX_PPULL(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
-#define NPCX_PPUD(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
-#define NPCX_PENVDD(n)                    REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
-#define NPCX_PTYPE(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
-
-/* GPIO enumeration */
-enum {
-	GPIO_PORT_0,
-	GPIO_PORT_1,
-	GPIO_PORT_2,
-	GPIO_PORT_3,
-	GPIO_PORT_4,
-	GPIO_PORT_5,
-	GPIO_PORT_6,
-	GPIO_PORT_7,
-	GPIO_PORT_8,
-	GPIO_PORT_9,
-	GPIO_PORT_A,
-	GPIO_PORT_B,
-	GPIO_PORT_C,
-	GPIO_PORT_D,
-	GPIO_PORT_E,
-	GPIO_PORT_F,
-	GPIO_PORT_COUNT
-};
-
-enum {
-	MASK_PIN0 = BIT(0),
-	MASK_PIN1 = BIT(1),
-	MASK_PIN2 = BIT(2),
-	MASK_PIN3 = BIT(3),
-	MASK_PIN4 = BIT(4),
-	MASK_PIN5 = BIT(5),
-	MASK_PIN6 = BIT(6),
-	MASK_PIN7 = BIT(7),
-};
-
-/* Chip-independent aliases for port base group */
-#define GPIO_0 GPIO_PORT_0
-#define GPIO_1 GPIO_PORT_1
-#define GPIO_2 GPIO_PORT_2
-#define GPIO_3 GPIO_PORT_3
-#define GPIO_4 GPIO_PORT_4
-#define GPIO_5 GPIO_PORT_5
-#define GPIO_6 GPIO_PORT_6
-#define GPIO_7 GPIO_PORT_7
-#define GPIO_8 GPIO_PORT_8
-#define GPIO_9 GPIO_PORT_9
-#define GPIO_A GPIO_PORT_A
-#define GPIO_B GPIO_PORT_B
-#define GPIO_C GPIO_PORT_C
-#define GPIO_D GPIO_PORT_D
-#define GPIO_E GPIO_PORT_E
-#define GPIO_F GPIO_PORT_F
-#define UNIMPLEMENTED_GPIO_BANK GPIO_PORT_0
-
-/******************************************************************************/
-/* MSWC Registers */
-#define NPCX_MSWCTL1                      REG8(NPCX_MSWC_BASE_ADDR + 0x000)
-#define NPCX_MSWCTL2                      REG8(NPCX_MSWC_BASE_ADDR + 0x002)
-#define NPCX_HCBAL                        REG8(NPCX_MSWC_BASE_ADDR + 0x008)
-#define NPCX_HCBAH                        REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
-#define NPCX_SRID_CR                      REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
-#define NPCX_SID_CR                       REG8(NPCX_MSWC_BASE_ADDR + 0x020)
-#define NPCX_DEVICE_ID_CR                 REG8(NPCX_MSWC_BASE_ADDR + 0x022)
-
-/* MSWC register fields */
-#define NPCX_MSWCTL1_HRSTOB              0
-#define NPCS_MSWCTL1_HWPRON              1
-#define NPCX_MSWCTL1_PLTRST_ACT          2
-#define NPCX_MSWCTL1_VHCFGA              3
-#define NPCX_MSWCTL1_HCFGLK              4
-#define NPCX_MSWCTL1_PWROFFB             6
-#define NPCX_MSWCTL1_A20MB               7
-
-/******************************************************************************/
-/* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
-
-/* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
-
-/* DEVALT */
-/* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
-
-/* pin-mux for LPC/eSPI */
-#define NPCX_DEVALT1_KBRST_SL            0
-#define NPCX_DEVALT1_A20M_SL             1
-#define NPCX_DEVALT1_SMI_SL              2
-#define NPCX_DEVALT1_EC_SCI_SL           3
-#define NPCX_DEVALT1_NO_PWRGD            4
-#define NPCX_DEVALT1_RST_OUT_SL          5
-#define NPCX_DEVALT1_CLKRN_SL            6
-#define NPCX_DEVALT1_NO_LPC_ESPI         7
-
-/* pin-mux for PS2 */
-#define NPCX_DEVALT3_PS2_0_SL            0
-#define NPCX_DEVALT3_PS2_1_SL            1
-#define NPCX_DEVALT3_PS2_2_SL            2
-#define NPCX_DEVALT3_PS2_3_SL            3
-#define NPCX_DEVALTC_PS2_3_SL2           3
-
-/* pin-mux for Tacho */
-#define NPCX_DEVALT3_TA1_SL1             4
-#define NPCX_DEVALT3_TB1_SL1             5
-#define NPCX_DEVALT3_TA2_SL1             6
-#define NPCX_DEVALT3_TB2_SL1             7
-#define NPCX_DEVALTC_TA1_SL2             4
-#define NPCX_DEVALTC_TB1_SL2             5
-#define NPCX_DEVALTC_TA2_SL2             6
-#define NPCX_DEVALTC_TB2_SL2             7
-
-/* pin-mux for PWM */
-#define NPCX_DEVALT4_PWM0_SL             0
-#define NPCX_DEVALT4_PWM1_SL             1
-#define NPCX_DEVALT4_PWM2_SL             2
-#define NPCX_DEVALT4_PWM3_SL             3
-#define NPCX_DEVALT4_PWM4_SL             4
-#define NPCX_DEVALT4_PWM5_SL             5
-#define NPCX_DEVALT4_PWM6_SL             6
-#define NPCX_DEVALT4_PWM7_SL             7
-
-/* pin-mux for JTAG */
-#define NPCX_DEVALT5_TRACE_EN            0
-
-/* pin-mux for ADC */
-#define NPCX_DEVALT6_ADC0_SL             0
-#define NPCX_DEVALT6_ADC1_SL             1
-#define NPCX_DEVALT6_ADC2_SL             2
-#define NPCX_DEVALT6_ADC3_SL             3
-#define NPCX_DEVALT6_ADC4_SL             4
-
-/* pin-mux for Keyboard */
-#define NPCX_DEVALT7_NO_KSI0_SL          0
-#define NPCX_DEVALT7_NO_KSI1_SL          1
-#define NPCX_DEVALT7_NO_KSI2_SL          2
-#define NPCX_DEVALT7_NO_KSI3_SL          3
-#define NPCX_DEVALT7_NO_KSI4_SL          4
-#define NPCX_DEVALT7_NO_KSI5_SL          5
-#define NPCX_DEVALT7_NO_KSI6_SL          6
-#define NPCX_DEVALT7_NO_KSI7_SL          7
-#define NPCX_DEVALT8_NO_KSO00_SL         0
-#define NPCX_DEVALT8_NO_KSO01_SL         1
-#define NPCX_DEVALT8_NO_KSO02_SL         2
-#define NPCX_DEVALT8_NO_KSO03_SL         3
-#define NPCX_DEVALT8_NO_KSO04_SL         4
-#define NPCX_DEVALT8_NO_KSO05_SL         5
-#define NPCX_DEVALT8_NO_KSO06_SL         6
-#define NPCX_DEVALT8_NO_KSO07_SL         7
-#define NPCX_DEVALT9_NO_KSO08_SL         0
-#define NPCX_DEVALT9_NO_KSO09_SL         1
-#define NPCX_DEVALT9_NO_KSO10_SL         2
-#define NPCX_DEVALT9_NO_KSO11_SL         3
-#define NPCX_DEVALT9_NO_KSO12_SL         4
-#define NPCX_DEVALT9_NO_KSO13_SL         5
-#define NPCX_DEVALT9_NO_KSO14_SL         6
-#define NPCX_DEVALT9_NO_KSO15_SL         7
-#define NPCX_DEVALTA_NO_KSO16_SL         0
-#define NPCX_DEVALTA_NO_KSO17_SL         1
-
-/* pin-mux for Others */
-#define NPCX_DEVALTA_32K_OUT_SL          2
-#define NPCX_DEVALTA_NO_VCC1_RST         4
-#define NPCX_DEVALTA_NO_PECI_EN          6
-#define NPCX_DEVALTC_SHI_SL              1
-
-/* Others bit definitions */
-#define NPCX_LFCGCALCNT_LPREG_CTL_EN     1
-
-/******************************************************************************/
-/* Development and Debug Support (DBG) Registers */
-#define NPCX_DBGCTRL                      REG8(NPCX_SCFG_BASE_ADDR + 0x074)
-#define NPCX_DBGFRZEN1                    REG8(NPCX_SCFG_BASE_ADDR + 0x076)
-#define NPCX_DBGFRZEN2                    REG8(NPCX_SCFG_BASE_ADDR + 0x077)
-#define NPCX_DBGFRZEN3                    REG8(NPCX_SCFG_BASE_ADDR + 0x078)
-/* DBG register fields */
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
-
-/******************************************************************************/
-/* SMBus Registers */
-#define NPCX_SMBSDA(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
-#define NPCX_SMBST(n)                     REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
-#define NPCX_SMBCST(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
-#define NPCX_SMBCTL1(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
-#define NPCX_SMBADDR1(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
-#define NPCX_SMBTMR_ST(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
-#define NPCX_SMBCTL2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
-#define NPCX_SMBTMR_EN(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
-#define NPCX_SMBADDR2(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
-#define NPCX_SMBCTL3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
-/* SMB Registers in bank 0 */
-#define NPCX_SMBADDR3(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBADDR7(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
-#define NPCX_SMBADDR4(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMBADDR8(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
-#define NPCX_SMBADDR5(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-#define NPCX_SMBADDR6(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
-#define NPCX_SMBCST2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
-#define NPCX_SMBCST3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
-#define NPCX_SMBCTL4(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBSCLLT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBFIF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
-#define NPCX_SMBSCLHT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
-/* SMB Registers in bank 1 */
-#define NPCX_SMBFIF_CTS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBTXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMB_T_OUT(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-/*
- * These two registers are the same as in bank 0
- * #define NPCX_SMBCST2(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
- * #define NPCX_SMBCST3(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
- */
-#define NPCX_SMBTXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBRXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBRXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
-
-/* SMBus register fields */
-#define NPCX_SMBST_XMIT                  0
-#define NPCX_SMBST_MASTER                1
-#define NPCX_SMBST_NMATCH                2
-#define NPCX_SMBST_STASTR                3
-#define NPCX_SMBST_NEGACK                4
-#define NPCX_SMBST_BER                   5
-#define NPCX_SMBST_SDAST                 6
-#define NPCX_SMBST_SLVSTP                7
-#define NPCX_SMBCST_BUSY                 0
-#define NPCX_SMBCST_BB                   1
-#define NPCX_SMBCST_MATCH                2
-#define NPCX_SMBCST_GCMATCH              3
-#define NPCX_SMBCST_TSDA                 4
-#define NPCX_SMBCST_TGSCL                5
-#define NPCX_SMBCST_MATCHAF              6
-#define NPCX_SMBCST_ARPMATCH             7
-#define NPCX_SMBCST2_MATCHA1F            0
-#define NPCX_SMBCST2_MATCHA2F            1
-#define NPCX_SMBCST2_MATCHA3F            2
-#define NPCX_SMBCST2_MATCHA4F            3
-#define NPCX_SMBCST2_MATCHA5F            4
-#define NPCX_SMBCST2_MATCHA6F            5
-#define NPCX_SMBCST2_MATCHA7F            6
-#define NPCX_SMBCST2_INTSTS              7
-#define NPCX_SMBCST3_MATCHA8F            0
-#define NPCX_SMBCST3_MATCHA9F            1
-#define NPCX_SMBCST3_MATCHA10F           2
-#define NPCX_SMBCTL1_START               0
-#define NPCX_SMBCTL1_STOP                1
-#define NPCX_SMBCTL1_INTEN               2
-#define NPCX_SMBCTL1_ACK                 4
-#define NPCX_SMBCTL1_GCMEN               5
-#define NPCX_SMBCTL1_NMINTE              6
-#define NPCX_SMBCTL1_STASTRE             7
-#define NPCX_SMBCTL2_ENABLE              0
-#define NPCX_SMBCTL2_SCLFRQ7_FIELD       FIELD(1, 7)
-#define NPCX_SMBCTL3_ARPMEN              2
-#define NPCX_SMBCTL3_SCLFRQ2_FIELD       FIELD(0, 2)
-#define NPCX_SMBCTL3_IDL_START           3
-#define NPCX_SMBCTL3_400K                4
-#define NPCX_SMBCTL3_BNK_SEL             5
-#define NPCX_SMBCTL3_SDA_LVL             6
-#define NPCX_SMBCTL3_SCL_LVL             7
-#define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
-#define NPCX_SMBCTL4_LVL_WE              7
-#define NPCX_SMBADDR1_SAEN               7
-#define NPCX_SMBADDR2_SAEN               7
-#define NPCX_SMBADDR3_SAEN               7
-#define NPCX_SMBADDR4_SAEN               7
-#define NPCX_SMBADDR5_SAEN               7
-#define NPCX_SMBADDR6_SAEN               7
-#define NPCX_SMBADDR7_SAEN               7
-#define NPCX_SMBADDR8_SAEN               7
-#define NPCX_SMBFIF_CTS_RXF_TXE          1
-#define NPCX_SMBFIF_CTS_CLR_FIFO         6
-
-#define NPCX_SMBFIF_CTL_FIFO_EN          4
-
-#define NPCX_SMBRXF_STS_RX_THST          6
-
-/* RX FIFO threshold */
-#define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
-/*
- * In controller receiving mode, last byte in FIFO should send ACK or NACK
- */
-#define NPCX_SMBRXF_CTL_LAST             7
-
-/******************************************************************************/
-/* Power Management Controller (PMC) Registers */
-#define NPCX_PMCSR                     REG8(NPCX_PMC_BASE_ADDR + 0x000)
-#define NPCX_ENIDL_CTL                 REG8(NPCX_PMC_BASE_ADDR + 0x003)
-#define NPCX_DISIDL_CTL                REG8(NPCX_PMC_BASE_ADDR + 0x004)
-#define NPCX_DISIDL_CTL1               REG8(NPCX_PMC_BASE_ADDR + 0x005)
-#define NPCX_PWDWN_CTL_ADDR(offset)    (((offset) < 6) ? \
-			(NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
-			(NPCX_PMC_BASE_ADDR + 0x024))
-#define NPCX_PWDWN_CTL(offset)         REG8(NPCX_PWDWN_CTL_ADDR(offset))
-
-/* PMC register fields */
-#define NPCX_PMCSR_DI_INSTW              0
-#define NPCX_PMCSR_DHF                   1
-#define NPCX_PMCSR_IDLE                  2
-#define NPCX_PMCSR_NWBI                  3
-#define NPCX_PMCSR_OHFC                  6
-#define NPCX_PMCSR_OLFC                  7
-#define NPCX_DISIDL_CTL_RAM_DID          5
-#define NPCX_ENIDL_CTL_ADC_LFSL          7
-#define NPCX_ENIDL_CTL_LP_WK_CTL         6
-#define NPCX_ENIDL_CTL_PECI_ENI          2
-#define NPCX_ENIDL_CTL_ADC_ACC_DIS       1
-#define NPCX_PWDWN_CTL1_KBS_PD           0
-#define NPCX_PWDWN_CTL1_SDP_PD           1
-#define NPCX_PWDWN_CTL1_FIU_PD           2
-#define NPCX_PWDWN_CTL1_PS2_PD           3
-#define NPCX_PWDWN_CTL1_UART_PD          4
-#define NPCX_PWDWN_CTL1_MFT1_PD          5
-#define NPCX_PWDWN_CTL1_MFT2_PD          6
-#define NPCX_PWDWN_CTL1_MFT3_PD          7
-#define NPCX_PWDWN_CTL2_PWM0_PD          0
-#define NPCX_PWDWN_CTL2_PWM1_PD          1
-#define NPCX_PWDWN_CTL2_PWM2_PD          2
-#define NPCX_PWDWN_CTL2_PWM3_PD          3
-#define NPCX_PWDWN_CTL2_PWM4_PD          4
-#define NPCX_PWDWN_CTL2_PWM5_PD          5
-#define NPCX_PWDWN_CTL2_PWM6_PD          6
-#define NPCX_PWDWN_CTL2_PWM7_PD          7
-#define NPCX_PWDWN_CTL3_SMB0_PD          0
-#define NPCX_PWDWN_CTL3_SMB1_PD          1
-#define NPCX_PWDWN_CTL3_SMB2_PD          2
-#define NPCX_PWDWN_CTL3_SMB3_PD          3
-#define NPCX_PWDWN_CTL3_GMDA_PD          7
-#define NPCX_PWDWN_CTL4_ITIM1_PD         0
-#define NPCX_PWDWN_CTL4_ITIM2_PD         1
-#define NPCX_PWDWN_CTL4_ITIM3_PD         2
-#define NPCX_PWDWN_CTL4_ADC_PD           4
-#define NPCX_PWDWN_CTL4_PECI_PD          5
-#define NPCX_PWDWN_CTL4_PWM6_PD          6
-#define NPCX_PWDWN_CTL4_SPIP_PD          7
-#define NPCX_PWDWN_CTL5_SHI_PD           1
-#define NPCX_PWDWN_CTL5_MRFSH_DIS        2
-#define NPCX_PWDWN_CTL5_C2HACC_PD        3
-#define NPCX_PWDWN_CTL5_SHM_REG_PD       4
-#define NPCX_PWDWN_CTL5_SHM_PD           5
-#define NPCX_PWDWN_CTL5_DP80_PD          6
-#define NPCX_PWDWN_CTL5_MSWC_PD          7
-#define NPCX_PWDWN_CTL6_ITIM4_PD         0
-#define NPCX_PWDWN_CTL6_ITIM5_PD         1
-#define NPCX_PWDWN_CTL6_ITIM6_PD         2
-#define NPCX_PWDWN_CTL6_ESPI_PD          7
-
-/* TODO: set PD masks based upon actual peripheral usage */
-#define CGC_KBS_MASK     BIT(NPCX_PWDWN_CTL1_KBS_PD)
-#define CGC_UART_MASK    BIT(NPCX_PWDWN_CTL1_UART_PD)
-#define CGC_FAN_MASK     (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \
-			 BIT(NPCX_PWDWN_CTL1_MFT2_PD))
-#define CGC_FIU_MASK     BIT(NPCX_PWDWN_CTL1_FIU_PD)
-#define CGC_PS2_MASK     BIT(NPCX_PWDWN_CTL1_PS2_PD)
-#define CGC_ADC_MASK     BIT(NPCX_PWDWN_CTL4_ADC_PD)
-#define CGC_PECI_MASK    BIT(NPCX_PWDWN_CTL4_PECI_PD)
-#define CGC_SPI_MASK     BIT(NPCX_PWDWN_CTL4_SPIP_PD)
-#define CGC_TIMER_MASK   (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
-#define CGC_LPC_MASK     (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_DP80_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
-#define CGC_ESPI_MASK    BIT(NPCX_PWDWN_CTL6_ESPI_PD)
-
-/******************************************************************************/
-/* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
-
-/* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
-
-/******************************************************************************/
-/* Shared Memory (SHM) Registers */
-#define NPCX_SMC_STS                REG8(NPCX_SHM_BASE_ADDR + 0x000)
-#define NPCX_SMC_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x001)
-#define NPCX_SHM_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x002)
-#define NPCX_IMA_WIN_SIZE           REG8(NPCX_SHM_BASE_ADDR + 0x005)
-#define NPCX_WIN_SIZE               REG8(NPCX_SHM_BASE_ADDR + 0x007)
-#define NPCX_SHAW_SEM(win)          REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
-#define NPCX_IMA_SEM                REG8(NPCX_SHM_BASE_ADDR + 0x00B)
-#define NPCX_SHCFG                  REG8(NPCX_SHM_BASE_ADDR + 0x00E)
-#define NPCX_WIN_WR_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L))
-#define NPCX_WIN_RD_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L))
-#define NPCX_IMA_WR_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x016)
-#define NPCX_IMA_RD_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x017)
-#define NPCX_WIN_BASE(win)         REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-
-#define NPCX_PWIN_BASEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-#define NPCX_PWIN_SIZEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L))
-
-#define NPCX_IMA_BASE              REG32(NPCX_SHM_BASE_ADDR + 0x02C)
-#define NPCX_RST_CFG                REG8(NPCX_SHM_BASE_ADDR + 0x03A)
-#define NPCX_DP80BUF               REG16(NPCX_SHM_BASE_ADDR + 0x040)
-#define NPCX_DP80STS                REG8(NPCX_SHM_BASE_ADDR + 0x042)
-#define NPCX_DP80CTL                REG8(NPCX_SHM_BASE_ADDR + 0x044)
-#define NPCX_HOFS_STS               REG8(NPCX_SHM_BASE_ADDR + 0x048)
-#define NPCX_HOFS_CTL               REG8(NPCX_SHM_BASE_ADDR + 0x049)
-#define NPCX_COFS2                 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
-#define NPCX_COFS1                 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
-#define NPCX_IHOFS2                REG16(NPCX_SHM_BASE_ADDR + 0x050)
-#define NPCX_IHOFS1                REG16(NPCX_SHM_BASE_ADDR + 0x052)
-#define NPCX_SHM_VER                REG8(NPCX_SHM_BASE_ADDR + 0x07F)
-
-/* SHM register fields */
-#define NPCX_SMC_STS_HRERR               0
-#define NPCX_SMC_STS_HWERR               1
-#define NPCX_SMC_STS_HSEM1W              4
-#define NPCX_SMC_STS_HSEM2W              5
-#define NPCX_SMC_STS_SHM_ACC             6
-#define NPCX_SMC_CTL_HERR_IE             2
-#define NPCX_SMC_CTL_HSEM1_IE            3
-#define NPCX_SMC_CTL_HSEM2_IE            4
-#define NPCX_SMC_CTL_ACC_IE              5
-#define NPCX_SMC_CTL_PREF_EN             6
-#define NPCX_SMC_CTL_HOSTWAIT            7
-#define NPCX_FLASH_SIZE_STALL_HOST       6
-#define NPCX_FLASH_SIZE_RD_BURST         7
-#define NPCX_WIN_PROT_RW1L_RP            0
-#define NPCX_WIN_PROT_RW1L_WP            1
-#define NPCX_WIN_PROT_RW1H_RP            2
-#define NPCX_WIN_PROT_RW1H_WP            3
-#define NPCX_WIN_PROT_RW2L_RP            4
-#define NPCX_WIN_PROT_RW2L_WP            5
-#define NPCX_WIN_PROT_RW2H_RP            6
-#define NPCX_WIN_PROT_RW2H_WP            7
-#define NPCX_PWIN_SIZEI_RPROT            13
-#define NPCX_PWIN_SIZEI_WPROT            14
-#define NPCX_CSEM2                       6
-#define NPCX_CSEM3                       7
-#define NPCX_DP80BUF_OFFS_FIELD          FIELD(8, 3)
-#define NPCX_DP80STS_FWR                 5
-#define NPCX_DP80STS_FNE                 6
-#define NPCX_DP80STS_FOR                 7
-#define NPCX_DP80CTL_DP80EN              0
-#define NPCX_DP80CTL_SYNCEN              1
-#define NPCX_DP80CTL_RFIFO               4
-#define NPCX_DP80CTL_CIEN                5
-
-/******************************************************************************/
-/* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
-
-/* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
-
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
-/******************************************************************************/
-/* PM Channel Registers */
-#define NPCX_HIPMST(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
-#define NPCX_HIPMDO(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
-#define NPCX_HIPMDI(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
-#define NPCX_SHIPMDI(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
-#define NPCX_HIPMDOC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
-#define NPCX_HIPMDOM(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
-#define NPCX_HIPMDIC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
-#define NPCX_HIPMCTL(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
-#define NPCX_HIPMCTL2(n)                  REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
-#define NPCX_HIPMIC(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
-#define NPCX_HIPMIE(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
-
-/* PM Channel register field */
-
-/* NPCX_HIPMIE */
-#define NPCX_HIPMIE_SCIE                 1
-#define NPCX_HIPMIE_SMIE                 2
-
-/* NPCX_HIPMCTL */
-#define NPCX_HIPMCTL_IBFIE               0
-#define NPCX_HIPMCTL_SCIPOL              6
-
-/* NPCX_HIPMST */
-#define NPCX_HIPMST_F0                   2 /* EC_LPC_CMDR_BUSY */
-#define NPCX_HIPMST_ST0                  4 /* EC_LPC_CMDR_ACPI_BRST */
-#define NPCX_HIPMST_ST1                  5 /* EC_LPC_CMDR_SCI */
-#define NPCX_HIPMST_ST2                  6 /* EC_LPC_CMDR_SMI */
-
-/* NPCX_HIPMIC */
-#define NPCX_HIPMIC_SMIB                 1
-#define NPCX_HIPMIC_SCIB                 2
-#define NPCX_HIPMIC_SMIPOL               6
-
-/*
- * PM Channel enumeration
- */
-enum PM_CHANNEL_T {
-	PM_CHAN_1,
-	PM_CHAN_2,
-	PM_CHAN_3,
-	PM_CHAN_4
-};
-
-/******************************************************************************/
-/* SuperI/O Internal Bus (SIB) Registers */
-#define NPCX_IHIOA                       REG16(NPCX_SIB_BASE_ADDR + 0x000)
-#define NPCX_IHD                          REG8(NPCX_SIB_BASE_ADDR + 0x002)
-#define NPCX_LKSIOHA                     REG16(NPCX_SIB_BASE_ADDR + 0x004)
-#define NPCX_SIOLV                       REG16(NPCX_SIB_BASE_ADDR + 0x006)
-#define NPCX_CRSMAE                      REG16(NPCX_SIB_BASE_ADDR + 0x008)
-#define NPCX_SIBCTRL                      REG8(NPCX_SIB_BASE_ADDR + 0x00A)
-#define NPCX_C2H_VER                      REG8(NPCX_SIB_BASE_ADDR + 0x00E)
-/* SIB register fields  */
-#define NPCX_SIBCTRL_CSAE                0
-#define NPCX_SIBCTRL_CSRD                1
-#define NPCX_SIBCTRL_CSWR                2
-#define NPCX_LKSIOHA_LKCFG               0
-#define NPCX_LKSIOHA_LKHIKBD            11
-#define NPCX_CRSMAE_CFGAE                0
-#define NPCX_CRSMAE_HIKBDAE             11
-
-/******************************************************************************/
-/* Battery-Backed RAM (BBRAM) Registers */
-#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
-#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + offset)
-
-/* BBRAM register fields */
-#define NPCX_BKUP_STS_IBBR               7
-
-/******************************************************************************/
-/* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
-
-/* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
-
-/******************************************************************************/
-/* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
-
-/* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
-
-/******************************************************************************/
-/* PECI Registers */
-
-#define NPCX_PECI_CTL_STS                REG8(NPCX_PECI_BASE_ADDR + 0x000)
-#define NPCX_PECI_RD_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x001)
-#define NPCX_PECI_ADDR                   REG8(NPCX_PECI_BASE_ADDR + 0x002)
-#define NPCX_PECI_CMD                    REG8(NPCX_PECI_BASE_ADDR + 0x003)
-#define NPCX_PECI_CTL2                   REG8(NPCX_PECI_BASE_ADDR + 0x004)
-#define NPCX_PECI_INDEX                  REG8(NPCX_PECI_BASE_ADDR + 0x005)
-#define NPCX_PECI_IDATA                  REG8(NPCX_PECI_BASE_ADDR + 0x006)
-#define NPCX_PECI_WR_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x007)
-#define NPCX_PECI_CFG                    REG8(NPCX_PECI_BASE_ADDR + 0x009)
-#define NPCX_PECI_RATE                   REG8(NPCX_PECI_BASE_ADDR + 0x00F)
-#define NPCX_PECI_DATA_IN(i)             REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-#define NPCX_PECI_DATA_OUT(i)            REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-
-/* PECI register fields */
-#define NPCX_PECI_CTL_STS_START_BUSY     0
-#define NPCX_PECI_CTL_STS_DONE           1
-#define NPCX_PECI_CTL_STS_AVL_ERR        2
-#define NPCX_PECI_CTL_STS_CRC_ERR        3
-#define NPCX_PECI_CTL_STS_ABRT_ERR       4
-#define NPCX_PECI_CTL_STS_AWFCS_EN       5
-#define NPCX_PECI_CTL_STS_DONE_EN        6
-#define NPCX_ESTRPST_PECIST              0
-#define SFT_STRP_CFG_CK50                5
-
-/******************************************************************************/
-/* PWM Registers */
-#define NPCX_PRSC(n)                     REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
-#define NPCX_CTR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
-#define NPCX_PWMCTL(n)                    REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
-#define NPCX_DCR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
-#define NPCX_PWMCTLEX(n)                  REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
-
-/* PWM register fields */
-#define NPCX_PWMCTL_INVP                 0
-#define NPCX_PWMCTL_CKSEL                1
-#define NPCX_PWMCTL_HB_DC_CTL_FIELD      FIELD(2, 2)
-#define NPCX_PWMCTL_PWR                  7
-#define NPCX_PWMCTLEX_FCK_SEL_FIELD      FIELD(4, 2)
-#define NPCX_PWMCTLEX_OD_OUT             7
-/******************************************************************************/
-/* MFT Registers */
-#define NPCX_TCNT1(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
-#define NPCX_TCRA(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
-#define NPCX_TCRB(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
-#define NPCX_TCNT2(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
-#define NPCX_TPRSC(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
-#define NPCX_TCKC(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
-#define NPCX_TMCTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
-#define NPCX_TECTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
-#define NPCX_TECLR(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
-#define NPCX_TIEN(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
-#define NPCX_TWUEN(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
-#define NPCX_TCFG(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
-
-/* MFT register fields */
-#define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
-#define NPCX_TCKC_LOW_PWR                7
-#define NPCX_TCKC_PLS_ACC_CLK            6
-#define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
-#define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
-#define NPCX_TMCTRL_TAEN                 5
-#define NPCX_TMCTRL_TBEN                 6
-#define NPCX_TMCTRL_TAEDG                3
-#define NPCX_TMCTRL_TBEDG                4
-#define NPCX_TCFG_TADBEN                 6
-#define NPCX_TCFG_TBDBEN                 7
-#define NPCX_TECTRL_TAPND                0
-#define NPCX_TECTRL_TBPND                1
-#define NPCX_TECTRL_TCPND                2
-#define NPCX_TECTRL_TDPND                3
-#define NPCX_TECLR_TACLR                 0
-#define NPCX_TECLR_TBCLR                 1
-#define NPCX_TECLR_TCCLR                 2
-#define NPCX_TECLR_TDCLR                 3
-#define NPCX_TIEN_TAIEN                  0
-#define NPCX_TIEN_TBIEN                  1
-#define NPCX_TIEN_TCIEN                  2
-#define NPCX_TIEN_TDIEN                  3
-#define NPCX_TWUEN_TAWEN                 0
-#define NPCX_TWUEN_TBWEN                 1
-#define NPCX_TWUEN_TCWEN                 2
-#define NPCX_TWUEN_TDWEN                 3
-/******************************************************************************/
-/* ITIM16/32 Define */
-#define ITIM_INT(module)               CONCAT2(NPCX_IRQ_, module)
-
-/* ITIM16/32 register */
-#define NPCX_ITPRE(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
-#define NPCX_ITCTS(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
-
-/* ITIM16 register fields */
-#define NPCX_ITCTS_TO_STS                0
-#define NPCX_ITCTS_TO_IE                 2
-#define NPCX_ITCTS_TO_WUE                3
-#define NPCX_ITCTS_CKSEL                 4
-#define NPCX_ITCTS_ITEN                  7
-
-/******************************************************************************/
-/* Serial Host Interface (SHI) Registers */
-#define NPCX_SHICFG1                      REG8(NPCX_SHI_BASE_ADDR + 0x001)
-#define NPCX_SHICFG2                      REG8(NPCX_SHI_BASE_ADDR + 0x002)
-#define NPCX_I2CADDR1                     REG8(NPCX_SHI_BASE_ADDR + 0x003)
-#define NPCX_I2CADDR2                     REG8(NPCX_SHI_BASE_ADDR + 0x004)
-#define NPCX_EVENABLE                     REG8(NPCX_SHI_BASE_ADDR + 0x005)
-#define NPCX_EVSTAT                       REG8(NPCX_SHI_BASE_ADDR + 0x006)
-#define NPCX_SHI_CAPABILITY               REG8(NPCX_SHI_BASE_ADDR + 0x007)
-#define NPCX_STATUS                       REG8(NPCX_SHI_BASE_ADDR + 0x008)
-#define NPCX_IBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00A)
-#define NPCX_OBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00B)
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
-
-/******************************************************************************/
-/* Monotonic Counter (MTC) Registers */
-#define NPCX_TTC                         REG32(NPCX_MTC_BASE_ADDR + 0x000)
-#define NPCX_WTC                         REG32(NPCX_MTC_BASE_ADDR + 0x004)
-#define NPCX_MTCTST                       REG8(NPCX_MTC_BASE_ADDR + 0x008)
-#define NPCX_MTCVER                       REG8(NPCX_MTC_BASE_ADDR + 0x00C)
-
-/* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
-
-/******************************************************************************/
-/* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL                  REG32(0x40001044)
-
-/******************************************************************************/
-/*  eSPI Registers */
-#define NPCX_ESPIID                 REG32(NPCX_ESPI_BASE_ADDR + 0X00)
-#define NPCX_ESPICFG                REG32(NPCX_ESPI_BASE_ADDR + 0X04)
-#define NPCX_ESPISTS                REG32(NPCX_ESPI_BASE_ADDR + 0X08)
-#define NPCX_ESPIIE                 REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
-#define NPCX_ESPIWE                 REG32(NPCX_ESPI_BASE_ADDR + 0X10)
-#define NPCX_VWREGIDX               REG32(NPCX_ESPI_BASE_ADDR + 0X14)
-#define NPCX_VWREGDATA              REG32(NPCX_ESPI_BASE_ADDR + 0X18)
-#define NPCX_OOBCTL                 REG32(NPCX_ESPI_BASE_ADDR + 0X24)
-#define NPCX_FLASHRXRDHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X28)
-#define NPCX_FLASHTXWRHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
-#define NPCX_FLASHCFG               REG32(NPCX_ESPI_BASE_ADDR + 0X34)
-#define NPCX_FLASHCTL               REG32(NPCX_ESPI_BASE_ADDR + 0X38)
-#define NPCX_ESPIERR                REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
-
-/* eSPI Virtual Wire channel registers */
-#define NPCX_VWEVSM(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n)))
-#define NPCX_VWEVMS(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n)))
-#define NPCX_VWCTL                  REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
-
-/* eSPI register fields */
-#define NPCX_ESPICFG_PCHANEN             0
-#define NPCX_ESPICFG_VWCHANEN            1
-#define NPCX_ESPICFG_OOBCHANEN           2
-#define NPCX_ESPICFG_FLASHCHANEN         3
-#define NPCX_ESPICFG_HPCHANEN            4
-#define NPCX_ESPICFG_HVWCHANEN           5
-#define NPCX_ESPICFG_HOOBCHANEN          6
-#define NPCX_ESPICFG_HFLASHCHANEN        7
-#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 2)
-#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 3)
-#define NPCX_ESPICFG_OPFREQ_FIELD        FIELD(17, 3)
-#define NPCX_ESPICFG_IOMODESEL_FIELD     FIELD(20, 2)
-#define NPCX_ESPICFG_ALERT_MODE          22
-#define NPCX_ESPICFG_CRC_CHK             23
-#define NPCX_ESPICFG_PCCHN_SUPP          24
-#define NPCX_ESPICFG_VWCHN_SUPP          25
-#define NPCX_ESPICFG_OOBCHN_SUPP         26
-#define NPCX_ESPICFG_FLASHCHN_SUPP       27
-#define NPCX_ESPIERR_INVCMD              0 /* Invalid Command Type */
-#define NPCX_ESPIERR_INVCYC              1 /* Invalid Cycle Type */
-#define NPCX_ESPIERR_CRCERR              2 /* Transaction CRC Error */
-#define NPCX_ESPIERR_ABCOMP              3 /* Abnormal Completion */
-#define NPCX_ESPIERR_PROTERR             4 /* Protocol Error */
-#define NPCX_ESPIERR_BADSIZE             5 /* Bad Size */
-#define NPCX_ESPIERR_NPBADALN            6 /* NPPC Bad Address Alignment */
-#define NPCX_ESPIERR_PCBADALN            7 /* PPC Bad Address Alignment */
-#define NPCX_ESPIERR_UNCMD               9 /* Unsupported Command */
-#define NPCX_ESPIERR_EXTRACYC            10 /* Extra eSPI Clock Cycles */
-#define NPCX_ESPIERR_VWERR               11 /* Virtual Channel Access Error */
-#define NPCX_ESPIERR_UNPBM               14 /* Unsuccessful Bus Completion */
-#define NPCX_ESPIERR_UNFLASH             15 /* Unsuccessful Flash Completion */
-#define NPCX_ESPIIE_IBRSTIE              0
-#define NPCX_ESPIIE_CFGUPDIE             1
-#define NPCX_ESPIIE_BERRIE               2
-#define NPCX_ESPIIE_OOBRXIE              3
-#define NPCX_ESPIIE_FLASHRXIE            4
-#define NPCX_ESPIIE_SFLASHRDIE           5
-#define NPCX_ESPIIE_PERACCIE             6
-#define NPCX_ESPIIE_DFRDIE               7
-#define NPCX_ESPIIE_VWUPDIE              8
-#define NPCX_ESPIIE_ESPIRSTIE            9
-#define NPCX_ESPIIE_PLTRSTIE             10
-#define NPCX_ESPIIE_AMERRIE              15
-#define NPCX_ESPIIE_AMDONEIE             16
-#define NPCX_ESPIWE_IBRSTWE              0
-#define NPCX_ESPIWE_CFGUPDWE             1
-#define NPCX_ESPIWE_BERRWE               2
-#define NPCX_ESPIWE_OOBRXWE              3
-#define NPCX_ESPIWE_FLASHRXWE            4
-#define NPCX_ESPIWE_PERACCWE             6
-#define NPCX_ESPIWE_DFRDWE               7
-#define NPCX_ESPIWE_VWUPDWE              8
-#define NPCX_ESPIWE_ESPIRSTWE            9
-#define NPCX_ESPISTS_IBRST               0
-#define NPCX_ESPISTS_CFGUPD              1
-#define NPCX_ESPISTS_BERR                2
-#define NPCX_ESPISTS_OOBRX               3
-#define NPCX_ESPISTS_FLASHRX             4
-#define NPCX_ESPISTS_SFLASHRD            5
-#define NPCX_ESPISTS_PERACC              6
-#define NPCX_ESPISTS_DFRD                7
-#define NPCX_ESPISTS_VWUPD               8
-#define NPCX_ESPISTS_ESPIRST             9
-#define NPCX_ESPISTS_PLTRST              10
-#define NPCX_ESPISTS_AMERR               15
-#define NPCX_ESPISTS_AMDONE              16
-/* eSPI Virtual Wire channel register fields */
-#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVSM_VALID                FIELD(4, 4)
-#define NPCX_VWEVMS_VALID                FIELD(4, 4)
-
-/* Macro functions for eSPI CFG & IE */
-#define IS_PERIPHERAL_CHAN_ENABLE(ch)    IS_BIT_SET(NPCX_ESPICFG, ch)
-#define IS_HOST_CHAN_EN(ch)              IS_BIT_SET(NPCX_ESPICFG, (ch+4))
-#define ENABLE_ESPI_CHAN(ch)             SET_BIT(NPCX_ESPICFG, ch)
-#define DISABLE_ESPI_CHAN(ch)            CLEAR_BIT(NPCX_ESPICFG, ch)
-/* ESPI Peripheral Channel Support Definitions */
-#define ESPI_SUPP_CH_PC                  BIT(NPCX_ESPICFG_PCCHN_SUPP)
-#define ESPI_SUPP_CH_VM                  BIT(NPCX_ESPICFG_VWCHN_SUPP)
-#define ESPI_SUPP_CH_OOB                 BIT(NPCX_ESPICFG_OOBCHN_SUPP)
-#define ESPI_SUPP_CH_FLASH               BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
-#define ESPI_SUPP_CH_ALL                 (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \
-					  ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH)
-/* ESPI Interrupts Enable Definitions */
-#define ESPIIE_IBRST                     BIT(NPCX_ESPIIE_IBRSTIE)
-#define ESPIIE_CFGUPD                    BIT(NPCX_ESPIIE_CFGUPDIE)
-#define ESPIIE_BERR                      BIT(NPCX_ESPIIE_BERRIE)
-#define ESPIIE_OOBRX                     BIT(NPCX_ESPIIE_OOBRXIE)
-#define ESPIIE_FLASHRX                   BIT(NPCX_ESPIIE_FLASHRXIE)
-#define ESPIIE_SFLASHRD                  BIT(NPCX_ESPIIE_SFLASHRDIE)
-#define ESPIIE_PERACC                    BIT(NPCX_ESPIIE_PERACCIE)
-#define ESPIIE_DFRD                      BIT(NPCX_ESPIIE_DFRDIE)
-#define ESPIIE_VWUPD                     BIT(NPCX_ESPIIE_VWUPDIE)
-#define ESPIIE_ESPIRST                   BIT(NPCX_ESPIIE_ESPIRSTIE)
-#define ESPIIE_PLTRST                    BIT(NPCX_ESPIIE_PLTRSTIE)
-#define ESPIIE_AMERR                     BIT(NPCX_ESPIIE_AMERRIE)
-#define ESPIIE_AMDONE                    BIT(NPCX_ESPIIE_AMDONEIE)
-/* eSPI Interrupts for VW */
-#define ESPIIE_VW                        (ESPIIE_VWUPD | ESPIIE_PLTRST)
-/* eSPI Interrupts for Generic */
-#define ESPIIE_GENERIC                   (ESPIIE_IBRST | ESPIIE_CFGUPD | \
-					  ESPIIE_BERR | ESPIIE_ESPIRST)
-/* ESPI Wake-up Enable Definitions */
-#define ESPIWE_IBRST                     BIT(NPCX_ESPIWE_IBRSTWE)
-#define ESPIWE_CFGUPD                    BIT(NPCX_ESPIWE_CFGUPDWE)
-#define ESPIWE_BERR                      BIT(NPCX_ESPIWE_BERRWE)
-#define ESPIWE_OOBRX                     BIT(NPCX_ESPIWE_OOBRXWE)
-#define ESPIWE_FLASHRX                   BIT(NPCX_ESPIWE_FLASHRXWE)
-#define ESPIWE_PERACC                    BIT(NPCX_ESPIWE_PERACCWE)
-#define ESPIWE_DFRD                      BIT(NPCX_ESPIWE_DFRDWE)
-#define ESPIWE_VWUPD                     BIT(NPCX_ESPIWE_VWUPDWE)
-#define ESPIWE_ESPIRST                   BIT(NPCX_ESPIWE_ESPIRSTWE)
-/* eSPI  Wake-up enable for VW */
-#define ESPIWE_VW                        ESPIWE_VWUPD
-/* eSPI  Wake-up enable for Generic */
-#define ESPIWE_GENERIC                   (ESPIWE_IBRST | ESPIWE_CFGUPD | \
-					  ESPIWE_BERR)
-/* Macro functions for eSPI VW */
-#define ESPI_VWEVMS_NUM                  12
-#define ESPI_VWEVSM_NUM                  10
-#define ESPI_VW_IDX_WIRE_NUM             4
-/* Determine Virtual Wire type */
-#define VM_TYPE(i)              ((i >= 0   && i <=  1) ? ESPI_VW_TYPE_INT_EV : \
-				 (i >= 2   && i <=  7) ? ESPI_VW_TYPE_SYS_EV : \
-				 (i >= 64  && i <= 127) ? ESPI_VW_TYPE_PLT : \
-				 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \
-							ESPI_VW_TYPE_NONE)
-
-/* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVMS_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVMS_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVMS_INT_EN(e)             ((e<<18) & 0x00040000)
-#define VWEVMS_ESPIRST_EN(r)         ((r<<19) & 0x00080000)
-#define VWEVMS_FIELD(i, n, p, e, r)  (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \
-				VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \
-				VWEVMS_ESPIRST_EN(r))
-#define VWEVMS_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
-
-/* Bit field manipulation for VWEVSM Value */
-#define VWEVSM_VALID_N(v)            ((v<<4)  & 0x000000F0)
-#define VWEVSM_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVSM_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVSM_DIRTY(d)              ((d<<16) & 0x00010000)
-#define VWEVSM_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVSM_CDRST_EN(c)           ((c<<19) & 0x00080000)
-#define VWEVSM_FIELD(i, n, v, p, c)  (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \
-				VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\
-				VWEVSM_CDRST_EN(c))
-#define VWEVSM_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
-
-/* define macro to handle SMI/SCI Virtual Wire */
-/* Read SMI VWire status from VWEVSM(offset 2) register. */
-#define SMI_STATUS_MASK    ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002))
-/*
- * Read SCI VWire status from VWEVSM(offset 2) register.
- * Left shift 2 to meet the SCIB field in HIPMIC register.
- */
-#define SCI_STATUS_MASK    (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2)
-#define SCIB_MASK(v)       (v << NPCX_HIPMIC_SCIB)
-#define SMIB_MASK(v)       (v << NPCX_HIPMIC_SMIB)
-#define NPCX_VW_SCI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SMI_STATUS_MASK | SCIB_MASK(level))
-#define NPCX_VW_SMI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SCI_STATUS_MASK | SMIB_MASK(level))
-
-/* eSPI enumeration */
-/* eSPI channels */
-enum {
-	NPCX_ESPI_CH_PC = 0,
-	NPCX_ESPI_CH_VW,
-	NPCX_ESPI_CH_OOB,
-	NPCX_ESPI_CH_FLASH,
-	NPCX_ESPI_CH_COUNT,
-	NPCX_ESPI_CH_GENERIC,
-	NPCX_ESPI_CH_NONE = 0xFF
-};
-
-/* eSPI IO modes */
-enum {
-	NPCX_ESPI_IO_MODE_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_QUAD   = 2,
-	NPCX_ESPI_IO_MODE_ALL    = 3,
-	NPCX_ESPI_IO_MODE_NONE   = 0xFF
-};
-
-/* eSPI IO mode selected */
-enum {
-	NPCX_ESPI_IO_MODE_SEL_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_SEL_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_SEL_QUARD  = 2,
-	NPCX_ESPI_IO_MODE_SEL_NONE   = 0xFF
-};
-
-/* VW types */
-enum {
-	ESPI_VW_TYPE_INT_EV,            /* Interrupt event */
-	ESPI_VW_TYPE_SYS_EV,            /* System Event */
-	ESPI_VW_TYPE_PLT,               /* Platform specific */
-	ESPI_VW_TYPE_GPIO,              /* General Purpose I/O Expander */
-	ESPI_VW_TYPE_NUM,
-	ESPI_VW_TYPE_NONE = 0xFF
-};
-
-/******************************************************************************/
-/* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL                    REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB                   REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB                   REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT                   REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
-#define NPCX_GDMA_CSRC                   REG32(NPCX_GDMA_BASE_ADDR + 0x010)
-#define NPCX_GDMA_CDST                   REG32(NPCX_GDMA_BASE_ADDR + 0x014)
-#define NPCX_GDMA_CTCNT                  REG32(NPCX_GDMA_BASE_ADDR + 0x018)
-
-
-/******************************************************************************/
-/* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
-
-/******************************************************************************/
-/* Nuvoton internal used only registers */
-#define NPCX_INTERNAL_CTRL1               REG8(0x400DB000)
-#define NPCX_INTERNAL_CTRL2               REG8(0x400DD000)
-#define NPCX_INTERNAL_CTRL3               REG8(0x400DF000)
-
-/******************************************************************************/
-/* Optional M4 Registers */
-#define CPU_DHCSR                        REG32(0xE000EDF0)
-#define CPU_MPU_CTRL                     REG32(0xE000ED94)
-#define CPU_MPU_RNR                      REG32(0xE000ED98)
-#define CPU_MPU_RBAR                     REG32(0xE000ED9C)
-#define CPU_MPU_RASR                     REG32(0xE000EDA0)
-
-
-/******************************************************************************/
-/* Flash Utiltiy definition */
-/*
- *  Flash commands for the W25Q16CV SPI flash
- */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
-
-/*
- * Status registers for the W25Q16CV SPI flash
- */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
-
-/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
-/* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
-
-/******************************************************************************/
-/* APM (Audio Processing Module) Registers */
-#define NPCX_APM_SR                 REG8(NPCX_APM_BASE_ADDR + 0x000)
-#define NPCX_APM_SR2                REG8(NPCX_APM_BASE_ADDR + 0x004)
-#define NPCX_APM_ICR                REG8(NPCX_APM_BASE_ADDR + 0x008)
-#define NPCX_APM_IMR                REG8(NPCX_APM_BASE_ADDR + 0x00C)
-#define NPCX_APM_IFR                REG8(NPCX_APM_BASE_ADDR + 0x010)
-#define NPCX_APM_CR_APM             REG8(NPCX_APM_BASE_ADDR + 0x014)
-#define NPCX_APM_CR_CK              REG8(NPCX_APM_BASE_ADDR + 0x018)
-#define NPCX_APM_AICR_ADC           REG8(NPCX_APM_BASE_ADDR + 0x01C)
-#define NPCX_APM_FCR_ADC            REG8(NPCX_APM_BASE_ADDR + 0x020)
-#define NPCX_APM_CR_DMIC            REG8(NPCX_APM_BASE_ADDR + 0x02C)
-#define NPCX_APM_CR_ADC             REG8(NPCX_APM_BASE_ADDR + 0x030)
-#define NPCX_APM_CR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x034)
-#define NPCX_APM_DR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x038)
-#define NPCX_APM_GCR_ADCL           REG8(NPCX_APM_BASE_ADDR + 0x03C)
-#define NPCX_APM_GCR_ADCR           REG8(NPCX_APM_BASE_ADDR + 0x040)
-#define NPCX_APM_GCR_MIXADCL        REG8(NPCX_APM_BASE_ADDR + 0x044)
-#define NPCX_APM_GCR_MIXADCR        REG8(NPCX_APM_BASE_ADDR + 0x048)
-#define NPCX_APM_CR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x04C)
-#define NPCX_APM_DR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x050)
-#define NPCX_APM_SR_ADC_AGCDGL      REG8(NPCX_APM_BASE_ADDR + 0x054)
-#define NPCX_APM_SR_ADC_AGCDGR      REG8(NPCX_APM_BASE_ADDR + 0x058)
-#define NPCX_APM_CR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x05C)
-#define NPCX_APM_DR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x060)
-#define NPCX_APM_CR_VAD_CMD         REG8(NPCX_APM_BASE_ADDR + 0x064)
-#define NPCX_APM_CR_TR              REG8(NPCX_APM_BASE_ADDR + 0x068)
-#define NPCX_APM_DR_TR              REG8(NPCX_APM_BASE_ADDR + 0x06C)
-#define NPCX_APM_SR_TR1             REG8(NPCX_APM_BASE_ADDR + 0x070)
-#define NPCX_APM_SR_TR_SRCADC       REG8(NPCX_APM_BASE_ADDR + 0x074)
-
-/******************************************************************************/
-/* APM register fields */
-#define NPCX_APM_SR_IRQ_PEND                    6
-#define NPCX_APM_SR2_SMUTEIP                    6
-#define NPCX_APM_ICR_INTR_MODE                  FIELD(6, 2)
-#define NPCX_APM_IMR_VAD_DTC_MASK               6
-#define NPCX_APM_IFR_VAD_DTC                    6
-#define NPCX_APM_CR_APM_PD                      0
-#define NPCX_APM_CR_APM_AGC_DIS                 FIELD(1, 2)
-#define NPCX_APM_CR_CK_MCLK_FREQ                FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_ADC_AUDIOIF           FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_PD_AICR_ADC           4
-#define NPCX_APM_AICR_ADC_ADC_ADWL              FIELD(6, 2)
-#define NPCX_APM_FCR_ADC_ADC_FREQ               FIELD(0, 4)
-#define NPCX_APM_FCR_ADC_ADC_WNF                FIELD(4, 2)
-#define NPCX_APM_FCR_ADC_ADC_HPF                6
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT     FIELD(0, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT      FIELD(2, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE          FIELD(4, 3)
-#define NPCX_APM_CR_DMIC_PD_DMIC                7
-#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE           7
-#define NPCX_APM_CR_MIX_MIX_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_MIX_MIX_LOAD                6
-#define NPCX_APM_DR_MIX_MIX_DATA                FIELD(0, 8)
-#define NPCX_APM_MIX_2_AIADCR_SEL               FIELD(4, 2)
-#define NPCX_APM_MIX_2_AIADCL_SEL               FIELD(6, 2)
-#define NPCX_APM_GCR_ADCL_GIDL                  FIELD(0, 6)
-#define NPCX_APM_GCR_ADCL_LRGID                 7
-#define NPCX_APM_GCR_ADCR_GIDR                  FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCL_GIMIXL             FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCR_GIMIXR             FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD         FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD        6
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN          7
-#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA        FIELD(0, 8)
-#define NPCX_ADC_AGC_0_AGC_TARGET               FIELD(2, 4)
-#define NPCX_ADC_AGC_0_AGC_STEREO               6
-#define NPCX_ADC_AGC_1_HOLD                     FIELD(0, 4)
-#define NPCX_ADC_AGC_1_NG_THR                   FIELD(4, 3)
-#define NPCX_ADC_AGC_1_NG_EN                    7
-#define NPCX_ADC_AGC_2_DCY                      FIELD(0, 4)
-#define NPCX_ADC_AGC_2_ATK                      FIELD(4, 4)
-#define NPCX_ADC_AGC_3_AGC_MAX                  FIELD(0, 5)
-#define NPCX_ADC_AGC_4_AGC_MIN                  FIELD(0, 5)
-#define NPCX_APM_CR_VAD_VAD_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_VAD_VAD_LOAD                6
-#define NPCX_APM_CR_VAD_VAD_EN                  7
-#define NPCX_APM_DR_VAD_VAD_DATA                FIELD(0, 8)
-#define NPCX_APM_CR_VAD_CMD_VAD_RESTART         0
-#define NPCX_APM_CR_TR_FAST_ON                  7
-#define NPCX_VAD_0_VAD_INSEL                    FIELD(0, 2)
-#define NPCX_VAD_0_VAD_DMIC_FREQ                FIELD(2, 3)
-#define NPCX_VAD_0_VAD_ADC_WAKEUP               5
-#define NPCX_VAD_0_ZCD_EN                       6
-#define NPCX_VAD_1_VAD_POWER_SENS               FIELD(0, 5)
-#define NPCX_APM_CONTROL_ADD                    FIELD(0, 6)
-#define NPCX_APM_CONTROL_LOAD                   6
-
-/******************************************************************************/
-/* FMUL2 (Frequency Multiplier Module 2) Registers */
-#define NPCX_FMUL2_FM2CTRL          REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
-#define NPCX_FMUL2_FM2ML            REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
-#define NPCX_FMUL2_FM2MH            REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
-#define NPCX_FMUL2_FM2N             REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
-#define NPCX_FMUL2_FM2P             REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
-#define NPCX_FMUL2_FM2_VER          REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
-
-/******************************************************************************/
-/* FMUL2 register fields */
-#define NPCX_FMUL2_FM2CTRL_LOAD2                0
-#define NPCX_FMUL2_FM2CTRL_LOCK2                2
-#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS            5
-#define NPCX_FMUL2_FM2CTRL_TUNE_DIS             6
-#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG            7
-#define NPCX_FMUL2_FM2N_FM2N                    FIELD(0, 6)
-#define NPCX_FMUL2_FM2P_WFPRED                  FIELD(4, 4)
-
-/******************************************************************************/
-/* WOV (Wake-on-Voice) Registers */
-#define NPCX_WOV_CLOCK_CNTL         REG32(NPCX_WOV_BASE_ADDR + 0x000)
-#define NPCX_WOV_PLL_CNTL1          REG32(NPCX_WOV_BASE_ADDR + 0x004)
-#define NPCX_WOV_PLL_CNTL2          REG32(NPCX_WOV_BASE_ADDR + 0x008)
-#define NPCX_WOV_FIFO_CNT           REG32(NPCX_WOV_BASE_ADDR + 0x00C)
-#define NPCX_WOV_FIFO_OUT           REG32(NPCX_WOV_BASE_ADDR + 0x010)
-#define NPCX_WOV_STATUS             REG32(NPCX_WOV_BASE_ADDR + 0x014)
-#define NPCX_WOV_WOV_INTEN          REG32(NPCX_WOV_BASE_ADDR + 0x018)
-#define NPCX_WOV_APM_CTRL           REG32(NPCX_WOV_BASE_ADDR + 0x01C)
-#define NPCX_WOV_I2S_CNTL(n)        REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n))
-#define NPCX_WOV_VERSION            REG32(NPCX_WOV_BASE_ADDR + 0x030)
-
-/******************************************************************************/
-/* WOV register fields */
-#define NPCX_WOV_CLOCK_CNT_CLK_SEL              0
-#define NPCX_WOV_CLOCK_CNT_DMIC_EN              3
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL         7
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV             FIELD(8, 7)
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC          FIELD(16, 7)
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN        24
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL       25
-#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH           FIELD(0, 6)
-#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH           FIELD(6, 6)
-#define NPCX_WOV_FIFO_CNT_I2S_FFRST             13
-#define NPCX_WOV_FIFO_CNT_CORE_FFRST            14
-#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL            FIELD(16, 3)
-#define NPCX_WOV_STATUS_CFIFO_CNT               FIELD(0, 8)
-#define NPCX_WOV_STATUS_CFIFO_NE                8
-#define NPCX_WOV_STATUS_CFIFO_OIT               9
-#define NPCX_WOV_STATUS_CFIFO_OWT               10
-#define NPCX_WOV_STATUS_CFIFO_OVRN              11
-#define NPCX_WOV_STATUS_I2S_FIFO_OVRN           12
-#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN          13
-#define NPCX_WOV_STATUS_BITS			FIELD(9, 6)
-#define NPCX_WOV_INTEN_VAD_INTEN                0
-#define NPCX_WOV_INTEN_VAD_WKEN                 1
-#define NPCX_WOV_INTEN_CFIFO_NE_IE              8
-#define NPCX_WOV_INTEN_CFIFO_OIT_IE             9
-#define NPCX_WOV_INTEN_CFIFO_OWT_WE             10
-#define NPCX_WOV_INTEN_CFIFO_OVRN_IE            11
-#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE         12
-#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE        13
-#define NPCX_WOV_APM_CTRL_APM_RST               0
-#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN            0
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1            FIELD(4, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2            FIELD(8, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI            15
-#define NPCX_WOV_PLL_CNTL2_PLL_FBDV             FIELD(0, 12)
-#define NPCX_WOV_PLL_CNTL2_PLL_INDV             FIELD(12, 4)
-#define NPCX_WOV_I2S_CNTL_I2S_BCNT              FIELD(0, 5)
-#define NPCX_WOV_I2S_CNTL_I2S_TRIG              5
-#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ             6
-#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL            FIELD(7, 9)
-#define NPCX_WOV_I2S_CNTL_I2S_CHAN              FIELD(0, 16)
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZD             16
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZ              17
-#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV         18
-#define NPCX_WOV_I2S_CNTL0_I2S_OPS              19
-#define NPCX_WOV_I2S_CNTL0_I2S_OPE              20
-#define NPCX_WOV_I2S_CNTL0_I2S_IPS              21
-#define NPCX_WOV_I2S_CNTL0_I2S_IPE              22
-#define NPCX_WOV_I2S_CNTL0_I2S_TST              23
-#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS         24
-
-/******************************************************************************/
-/* PS/2 registers */
-#define NPCX_PS2_PSDAT                   REG8(NPCX_PS2_BASE_ADDR + 0x000)
-#define NPCX_PS2_PSTAT                   REG8(NPCX_PS2_BASE_ADDR + 0x002)
-#define NPCX_PS2_PSCON                   REG8(NPCX_PS2_BASE_ADDR + 0x004)
-#define NPCX_PS2_PSOSIG                  REG8(NPCX_PS2_BASE_ADDR + 0x006)
-#define NPCX_PS2_PSISIG                  REG8(NPCX_PS2_BASE_ADDR + 0x008)
-#define NPCX_PS2_PSIEN                   REG8(NPCX_PS2_BASE_ADDR + 0x00A)
-
-/* PS/2 register field */
-#define NPCX_PS2_PSTAT_SOT               0
-#define NPCX_PS2_PSTAT_EOT               1
-#define NPCX_PS2_PSTAT_PERR              2
-#define NPCX_PS2_PSTAT_ACH               FIELD(3, 3)
-#define NPCX_PS2_PSTAT_RFERR             6
-
-#define NPCX_PS2_PSCON_EN                0
-#define NPCX_PS2_PSCON_XMT               1
-#define NPCX_PS2_PSCON_HDRV              FIELD(2, 2)
-#define NPCX_PS2_PSCON_IDB               FIELD(4, 3)
-#define NPCX_PS2_PSCON_WPUED             7
-
-#define NPCX_PS2_PSOSIG_WDAT0            0
-#define NPCX_PS2_PSOSIG_WDAT1            1
-#define NPCX_PS2_PSOSIG_WDAT2            2
-#define NPCX_PS2_PSOSIG_CLK0             3
-#define NPCX_PS2_PSOSIG_CLK1             4
-#define NPCX_PS2_PSOSIG_CLK2             5
-#define NPCX_PS2_PSOSIG_WDAT3            6
-#define NPCX_PS2_PSOSIG_CLK3             7
-#define NPCX_PS2_PSOSIG_CLK(n)      (((n) < NPCX_PS2_CH3) ? \
-					((n) + 3) : 7)
-#define NPCX_PS2_PSOSIG_WDAT(n)     (((n) < NPCX_PS2_CH3) ? \
-					((n) + 0) : 6)
-#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \
-					(BIT(NPCX_PS2_PSOSIG_CLK0) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK1) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK2) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK3))
-
-#define NPCX_PS2_PSISIG_RDAT0            0
-#define NPCX_PS2_PSISIG_RDAT1            1
-#define NPCX_PS2_PSISIG_RDAT2            2
-#define NPCX_PS2_PSISIG_RCLK0            3
-#define NPCX_PS2_PSISIG_RCLK1            4
-#define NPCX_PS2_PSISIG_RCLK2            5
-#define NPCX_PS2_PSISIG_RDAT3            6
-#define NPCX_PS2_PSISIG_RCLK3            7
-#define NPCX_PS2_PSIEN_SOTIE             0
-#define NPCX_PS2_PSIEN_EOTIE             1
-#define NPCX_PS2_PSIEN_PS2_WUE           4
-#define NPCX_PS2_PSIEN_PS2_CLK_SEL	     7
-
-#ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-extern const enum gpio_signal hibernate_wake_pins[];
-extern const int hibernate_wake_pins_used;
-#else
-extern enum gpio_signal hibernate_wake_pins[];
-extern int hibernate_wake_pins_used;
-#endif
-
-#ifndef NPCX_UART_MODULE2
-#define NPCX_UART_MODULE2 0
-#endif /* NPCX_UART_MODULE2 */
-
-#if defined(CHIP_FAMILY_NPCX5)
-#include "registers-npcx5.h"
-#elif defined(CHIP_FAMILY_NPCX7)
-#include "registers-npcx7.h"
-#elif defined(CHIP_FAMILY_NPCX9)
-#include "registers-npcx9.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h
deleted file mode 100644
index bb66f95e88..0000000000
--- a/chip/npcx/rom_chip.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ROM_CHIP_H_
-#define __CROS_EC_ROM_CHIP_H_
-
-/******************************************************************************/
-/*
- * Enumerations of ROM api functions
- */
-enum API_SIGN_OPTIONS_T {
-	SIGN_NO_CHECK = 0,
-	SIGN_CRC_CHECK = 1,
-};
-
-enum API_RETURN_STATUS_T {
-	/* Successful download */
-	API_RET_STATUS_OK = 0,
-	/* Address is outside of flash or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SRC_ADDR = 1,
-	/* Address is outside of RAM or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_DST_ADDR = 2,
-	/* Size is 0 or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SIZE = 3,
-	/* Flash Address + Size is out of flash. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4,
-	/* RAM Address + Size is out of RAM. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5,
-	/* Wrong sign option. */
-	API_RET_STATUS_INVALID_SIGN = 6,
-	/* Error during Code copy. */
-	API_RET_STATUS_COPY_FAILED = 7,
-	/* Execution Address is outside of RAM */
-	API_RET_STATUS_INVALID_EXE_ADDR = 8,
-	/* Bad CRC value */
-	API_RET_STATUS_INVALID_SIGNATURE = 9,
-};
-
-/******************************************************************************/
-/*
- * Macro functions of ROM api functions
- */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
-#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
-
-/******************************************************************************/
-/*
- * Declarations of ROM api functions
- */
-typedef void (*download_from_flash_ptr) (
-	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
-	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
-	uint32_t exe_addr, /* jump to this address after download if not zero */
-	enum API_RETURN_STATUS_T *status /* Status fo download */
-);
-
-
-
-#endif /* __CROS_EC_ROM_CHIP_H_ */
diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c
deleted file mode 100644
index 6d2d938895..0000000000
--- a/chip/npcx/sha256_chip.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SHA256 module for Chrome EC */
-#include "common.h"
-#include "sha256.h"
-#include "util.h"
-
-enum ncl_status {
-	NCL_STATUS_OK,
-	NCL_STATUS_FAIL,
-	NCL_STATUS_INVALID_PARAM,
-	NCL_STATUS_PARAM_NOT_SUPPORTED,
-	NCL_STATUS_SYSTEM_BUSY,
-	NCL_STATUS_AUTHENTICATION_FAIL,
-	NCL_STATUS_NO_RESPONSE,
-	NCL_STATUS_HARDWARE_ERROR,
-};
-
-enum ncl_sha_type {
-	NCL_SHA_TYPE_2_256 = 0,
-	NCL_SHA_TYPE_2_384 = 1,
-	NCL_SHA_TYPE_2_512 = 2,
-	NCL_SHA_TYPE_NUM
-};
-
-/*
- * The base address of the table that holds the function pointer for each
- * SHA256 API in ROM.
- */
-#define NCL_SHA_BASE_ADDR          0x00000100UL
-struct ncl_sha {
-	/* Get the SHA context size required by SHA APIs. */
-	uint32_t (*get_context_size)(void);
-	/* Initial SHA context. */
-	enum ncl_status (*init_context)(void *ctx);
-	/* Finalize SHA context. */
-	enum ncl_status (*finalize_context)(void *ctx);
-	/* Initiate the SHA hardware module and setups needed parameters. */
-	enum ncl_status (*init)(void *ctx);
-	/*
-	 * Prepare the context buffer for a SHA calculation -  by loading the
-	 * initial SHA-256/384/512 parameters.
-	 */
-	enum ncl_status (*start)(void *ctx, enum ncl_sha_type type);
-	/*
-	 * Updates the SHA calculation with the additional data. When the
-	 * function returns, the hardware and memory buffer shall be ready to
-	 * accept new data * buffers for SHA calculation and changes to the data
-	 * in data buffer should no longer effect the SHA calculation.
-	 */
-	enum ncl_status (*update)(void *ctx, const uint8_t *data, uint32_t Len);
-	/* Return the SHA result (digest.) */
-	enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest);
-	/* Perform a complete SHA calculation */
-	enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type,
-			const uint8_t *data, uint32_t Len, uint8_t *hashDigest);
-	/* Power on/off the SHA module. */
-	enum ncl_status (*power)(void *ctx, uint8_t enable);
-	/* Reset the SHA hardware and terminate any in-progress operations. */
-	enum ncl_status (*reset)(void *ctx);
-};
-
-#define NCL_SHA ((const struct ncl_sha *)NCL_SHA_BASE_ADDR)
-
-void SHA256_init(struct sha256_ctx *ctx)
-{
-	NCL_SHA->init_context(ctx->handle);
-	NCL_SHA->power(ctx->handle, 1);
-	NCL_SHA->init(ctx->handle);
-	NCL_SHA->reset(ctx->handle);
-	NCL_SHA->start(ctx->handle, NCL_SHA_TYPE_2_256);
-}
-
-void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
-{
-	NCL_SHA->update(ctx->handle, data, len);
-}
-
-void SHA256_abort(struct sha256_ctx *ctx)
-{
-	NCL_SHA->reset(ctx->handle);
-	NCL_SHA->power(ctx->handle, 0);
-	NCL_SHA->finalize_context(ctx->handle);
-}
-
-uint8_t *SHA256_final(struct sha256_ctx *ctx)
-{
-	NCL_SHA->finish(ctx->handle, ctx->buf);
-	NCL_SHA->power(ctx->handle, 0);
-	NCL_SHA->finalize_context(ctx->handle);
-	return ctx->buf;
-}
-
-static void hmac_SHA256_step(uint8_t *output, uint8_t mask,
-			const uint8_t *key, const int key_len,
-			const uint8_t *data, const int data_len)
-{
-	struct sha256_ctx hmac_ctx;
-	uint8_t *key_pad = hmac_ctx.buf;
-	uint8_t *tmp;
-	int i;
-
-	memset(key_pad, mask, SHA256_BLOCK_SIZE);
-	for (i = 0; i < key_len; i++)
-		key_pad[i] ^= key[i];
-
-	SHA256_init(&hmac_ctx);
-	SHA256_update(&hmac_ctx, key_pad, SHA256_BLOCK_SIZE);
-	SHA256_update(&hmac_ctx, data, data_len);
-	tmp = SHA256_final(&hmac_ctx);
-	memcpy(output, tmp, SHA256_DIGEST_SIZE);
-}
-/*
- * Note: When the API is called, it will consume about half of TASK_STACK_SIZE
- * because a variable of structure sha256_ctx is declared in the function
- * hmac_SHA256_step.
- */
-void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
-		const uint8_t *message, const int message_len)
-{
-	/* This code does not support key_len > block_size. */
-	ASSERT(key_len <= SHA256_BLOCK_SIZE);
-
-	/*
-	 * i_key_pad = key (zero-padded) ^ 0x36
-	 * output = hash(i_key_pad || message)
-	 * (Use output as temporary buffer)
-	 */
-	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
-
-	/*
-	 * o_key_pad = key (zero-padded) ^ 0x5c
-	 * output = hash(o_key_pad || output)
-	 */
-	hmac_SHA256_step(output, 0x5c, key, key_len, output,
-				SHA256_DIGEST_SIZE);
-}
diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h
deleted file mode 100644
index 3b9586d962..0000000000
--- a/chip/npcx/sha256_chip.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SHA256_CHIP_H
-#define __CROS_EC_SHA256_CHIP_H
-
-#include "common.h"
-
-#define NPCX_SHA256_HANDLE_SIZE    212
-struct sha256_ctx {
-	/* the context handle required for SHA256 API */
-	uint8_t handle[NPCX_SHA256_HANDLE_SIZE];
-	/*
-	 * This is used to buffer:
-	 *   1. the result (digest) of the SHA256 computation.
-	 *   2. the 1st block input data (the key padding) for hmac_SHA256_step.
-	 */
-	uint8_t buf[SHA256_BLOCK_SIZE];
-} __aligned(4);
-
-void SHA256_abort(struct sha256_ctx *ctx);
-
-#endif  /* __CROS_EC_SHA256_CHIP_H */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
deleted file mode 100644
index 503a52807e..0000000000
--- a/chip/npcx/shi.c
+++ /dev/null
@@ -1,1082 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SHI driver for Chrome EC.
- *
- * This uses Input/Output buffer to handle SPI transmission and reception.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "task.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "spi.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-#if !(DEBUG_SHI)
-#define DEBUG_CPUTS(...)
-#define DEBUG_CPRINTS(...)
-#define DEBUG_CPRINTF(...)
-#else
-#define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr)
-#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-#endif
-
-/* SHI Bus definition */
-#ifdef NPCX_SHI_V2
-#define SHI_OBUF_FULL_SIZE  128                    /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  128                    /* Full input buffer size  */
-/* Configure the IBUFLVL2 = the size of V3 protocol header */
-#define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
-#else
-#define SHI_OBUF_FULL_SIZE  64                     /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  64                     /* Full input buffer size  */
-#endif
-#define SHI_OBUF_HALF_SIZE  (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */
-#define SHI_IBUF_HALF_SIZE  (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size  */
-
-/* Start address of SHI output buffer */
-#define SHI_OBUF_START_ADDR  (volatile uint8_t  *)(NPCX_SHI_BASE_ADDR + 0x020)
-/* Middle address of SHI output buffer */
-#define SHI_OBUF_HALF_ADDR   (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
-/* Top address of SHI output buffer */
-#define SHI_OBUF_FULL_ADDR   (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
-/*
- * Valid offset of SHI output buffer to write.
- * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
- */
-#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \
-			SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE)
-/* Start address of SHI input buffer */
-#define SHI_IBUF_START_ADDR  (&NPCX_IBUF(0))
-/* Current address of SHI input buffer */
-#define SHI_IBUF_CUR_ADDR    (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
-
-/*
- * Timeout to wait for SHI request packet
- *
- * This affects the slowest SPI clock we can support.  A delay of 8192
- * us permits a 512-byte request at 500 KHz, assuming the controller
- * starts sending bytes as soon as it asserts chip select.  That's as
- * slow as we would practically want to run the SHI interface, since
- * running it slower significantly impacts firmware update times.
- */
-#define SHI_CMD_RX_TIMEOUT_US 8192
-
-/* Timeout for glitch case. Make sure it will exceed 8 SPI clocks */
-#define SHI_GLITCH_TIMEOUT_US 10000
-
-/*
- * The AP blindly clocks back bytes over the SPI interface looking for a
- * framing byte.  So this preamble must always precede the actual response
- * packet.
- */
-
-#define SHI_OUT_PREAMBLE_LENGTH 2
-/*
- * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
- * buffer.
- */
-#define EC_SPI_PAST_END_LENGTH 1
-/*
- * Space allocation of the frame status byte (EC_SPI_FRAME_START) in the out_msg
- * buffer.
- */
-#define EC_SPI_FRAME_START_LENGTH 1
-
-/*
- * Offset of output parameters needs to account for pad and framing bytes and
- * one last past-end byte at the end so any additional bytes clocked out by
- * the AP will have a known and identifiable value.
- */
-#define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
-
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-/* The boundary which SHI will output invalid data on MISO. */
-#define SHI_BYPASS_BOUNDARY 256
-/* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */
-#undef  EC_SPI_FRAME_START_LENGTH
-#define EC_SPI_FRAME_START_LENGTH 2
-#endif
-
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size, and 512 bytes
- * of flash data:
- *  sizeof(ec_host_request):          8
- *  sizoef(ec_params_flash_write):    8
- *  payload                         512
- *
- */
-#define SHI_MAX_REQUEST_SIZE 0x220
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-/* Make sure SHI_MAX_RESPONSE_SIZE won't exceed 256 bytes */
-#define SHI_MAX_RESPONSE_SIZE (160 + sizeof(struct ec_host_response))
-BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY);
-#else
-#define SHI_MAX_RESPONSE_SIZE 0x220
-#endif
-
-/*
- * Our input and output msg buffers. These must be large enough for our largest
- * message, including protocol overhead.  The pointers after the protocol
- * overhead, as passed to the host command handler, must be 32-bit aligned.
- */
-#define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
-#define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
-static uint8_t out_msg_padded[SHI_OUT_START_PAD +
-			      SHI_MAX_RESPONSE_SIZE +
-			      SHI_OUT_END_PAD] __aligned(4);
-static uint8_t * const out_msg =
-	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
-static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet shi_packet;
-
-enum shi_state {
-	/* SHI not enabled (initial state, and when chipset is off) */
-	SHI_STATE_DISABLED = 0,
-	/* Ready to receive next request */
-	SHI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SHI_STATE_RECEIVING,
-	/* Processing request */
-	SHI_STATE_PROCESSING,
-	/* Canceling response since CS deasserted and output NOT_READY byte */
-	SHI_STATE_CNL_RESP_NOT_RDY,
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/* Keep output buffer as PROCESSING byte until reaching 256B boundary */
-	SHI_STATE_WAIT_ALIGNMENT,
-#endif
-	/* Sending response */
-	SHI_STATE_SENDING,
-	/* Received data is valid. */
-	SHI_STATE_BAD_RECEIVED_DATA,
-};
-
-volatile enum shi_state state;
-
-/* SHI bus parameters */
-struct shi_bus_parameters {
-	uint8_t *rx_msg;          /* Entry pointer of msg rx buffer   */
-	uint8_t *tx_msg;          /* Entry pointer of msg tx buffer   */
-	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
-	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
-	uint16_t sz_received;     /* Size of received data in bytes   */
-	uint16_t sz_sending;      /* Size of sending data in bytes    */
-	uint16_t sz_request;      /* request bytes need to receive    */
-	uint16_t sz_response;     /* response bytes need to receive   */
-	timestamp_t rx_deadline;  /* deadline of receiving            */
-	uint8_t  pre_ibufstat;    /* Previous IBUFSTAT value          */
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	uint16_t bytes_in_256b;   /* Sent bytes in 256 bytes boundary */
-#endif
-} shi_params;
-
-/* Forward declaration */
-static void shi_reset_prepare(void);
-static void shi_bad_received_data(void);
-static void shi_fill_out_status(uint8_t status);
-static void shi_write_half_outbuf(void);
-static void shi_write_first_pkg_outbuf(uint16_t szbytes);
-static int shi_read_inbuf_wait(uint16_t szbytes);
-static uint8_t shi_read_buf_pointer(void);
-
-/*****************************************************************************/
-/* V3 protocol layer functions */
-
-/**
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void shi_send_response_packet(struct host_packet *pkt)
-{
-	/*
-	 * Disable interrupts. This routine is not called from interrupt
-	 * context and buffer underrun will likely occur if it is
-	 * preempted after writing its initial reply byte. Also, we must be
-	 * sure our state doesn't unexpectedly change, in case we're expected
-	 * to take RESP_NOT_RDY actions.
-	 */
-	interrupt_disable();
-	if (state == SHI_STATE_PROCESSING) {
-		/* Append our past-end byte, which we reserved space for. */
-		((uint8_t *) pkt->response)[pkt->response_size + 0] =
-			EC_SPI_PAST_END;
-
-		/* Computing sending bytes of response */
-		shi_params.sz_response =
-			pkt->response_size + SHI_PROTO3_OVERHEAD;
-
-		/* Start to fill output buffer with msg buffer */
-		shi_write_first_pkg_outbuf(shi_params.sz_response);
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		/*
-		 * If response package is over 256B boundary,
-		 * keep sending PROCESSING byte
-		 */
-		if (state != SHI_STATE_WAIT_ALIGNMENT) {
-#endif
-			/* Transmit the reply */
-			state = SHI_STATE_SENDING;
-			DEBUG_CPRINTF("SND-");
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		}
-#endif
-	}
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 * Reset state machine for next transaction.
-	 */
-	else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-	} else
-		DEBUG_CPRINTS("Unexpected state %d in response handler", state);
-	interrupt_enable();
-}
-
-void shi_handle_host_package(void)
-{
-	uint16_t sz_inbuf_int = shi_params.sz_request / SHI_IBUF_HALF_SIZE;
-	uint16_t cnt_inbuf_int = shi_params.sz_received / SHI_IBUF_HALF_SIZE;
-	if (sz_inbuf_int - cnt_inbuf_int)
-		/* Need to receive data from buffer */
-		return;
-	else {
-		uint16_t remain_bytes = shi_params.sz_request
-					- shi_params.sz_received;
-
-		/* Read remaining bytes from input buffer directly */
-		if (!shi_read_inbuf_wait(remain_bytes))
-			return shi_bad_received_data();
-		/* Move to processing state immediately */
-		state = SHI_STATE_PROCESSING;
-		DEBUG_CPRINTF("PRC-");
-	}
-	/* Fill output buffer to indicate we`re processing request */
-	shi_fill_out_status(EC_SPI_PROCESSING);
-
-	/* Set up parameters for host request */
-	shi_packet.send_response = shi_send_response_packet;
-
-	shi_packet.request = in_msg;
-	shi_packet.request_temp = NULL;
-	shi_packet.request_max = sizeof(in_msg);
-	shi_packet.request_size = shi_params.sz_request;
-
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/* Move FRAME_START to second byte */
-	out_msg[0] = EC_SPI_PROCESSING;
-	out_msg[1] = EC_SPI_FRAME_START;
-#else
-	/* Put FRAME_START in first byte */
-	out_msg[0] = EC_SPI_FRAME_START;
-#endif
-	shi_packet.response = out_msg + EC_SPI_FRAME_START_LENGTH;
-
-	/* Reserve space for frame start and trailing past-end byte */
-	shi_packet.response_max = SHI_MAX_RESPONSE_SIZE;
-	shi_packet.response_size = 0;
-	shi_packet.driver_result = EC_RES_SUCCESS;
-
-	/* Go to common-layer to handle request */
-	host_packet_receive(&shi_packet);
-}
-
-/* Parse header for version of spi-protocol */
-static void shi_parse_header(void)
-{
-	/* We're now inside a transaction */
-	state = SHI_STATE_RECEIVING;
-	DEBUG_CPRINTF("RV-");
-
-	/* Setup deadline time for receiving */
-	shi_params.rx_deadline = get_time();
-	shi_params.rx_deadline.val += SHI_CMD_RX_TIMEOUT_US;
-
-	/* Wait for version, command, length bytes */
-	if (!shi_read_inbuf_wait(3))
-		return shi_bad_received_data();
-
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *) in_msg;
-		int pkt_size;
-		/*
-		 * If request is over 32 bytes,
-		 * we need to modified the algorithm again.
-		 */
-		ASSERT(sizeof(*r) < SHI_IBUF_HALF_SIZE);
-
-		/* Wait for the rest of the command header */
-		if (!shi_read_inbuf_wait(sizeof(*r) - 3))
-			return shi_bad_received_data();
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			return shi_bad_received_data();
-
-		/* Computing total bytes need to receive */
-		shi_params.sz_request = pkt_size;
-
-		shi_handle_host_package();
-	} else {
-		/* Invalid version number */
-		return shi_bad_received_data();
-	}
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/* This routine fills out all SHI output buffer with status byte */
-static void shi_fill_out_status(uint8_t status)
-{
-	uint8_t start, end;
-	uint8_t *fill_ptr;
-	uint8_t *fill_end;
-	uint8_t *obuf_end;
-
-	/* Disable interrupts in case the interfere by the other interrupts */
-	interrupt_disable();
-
-	/*
-	 * Fill out output buffer with status byte and leave a gap for PREAMBLE.
-	 * The gap guarantees the synchronization. The critical section should
-	 * be done within this gap. No racing happens.
-	 */
-	start = SHI_OBUF_VALID_OFFSET;
-	end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH)
-	       % SHI_OBUF_FULL_SIZE);
-
-	fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start;
-	fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end;
-	obuf_end = (uint8_t *)SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE;
-	while (fill_ptr != fill_end) {
-		*(fill_ptr++) = status;
-		if (fill_ptr == obuf_end)
-			fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
-	}
-
-	/* End of critical section */
-	interrupt_enable();
-}
-
-#ifdef NPCX_SHI_V2
- /*
-  * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
-  * event triggers an interrupt to core.
-  */
-static void shi_sec_ibf_int_enable(int enable)
-{
-	if (enable) {
-		/* Setup IBUFLVL2 threshold and enable it */
-		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2,
-				SHI_IBUFLVL2_THRESHOLD);
-		CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		/* Enable IBHF2 event */
-		SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
-	} else {
-		/* Disable IBHF2 event first */
-		CLEAR_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
-		/* Disable IBUFLVL2 and set threshold back to zero */
-		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2, 0);
-	}
-}
-#else
-/*
- * This routine makes sure it's valid transaction or glitch on CS bus.
- */
-static int shi_is_cs_glitch(void)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + SHI_GLITCH_TIMEOUT_US;
-	/*
-	 * If input buffer pointer is no changed after timeout, it will
-	 * return true
-	 */
-	while (shi_params.pre_ibufstat == shi_read_buf_pointer())
-		if (timestamp_expired(deadline, NULL))
-			return 1;
-	/* valid package */
-	return 0;
-}
-#endif
-
-/*
- * This routine write SHI next half output buffer from msg buffer
- */
-static void shi_write_half_outbuf(void)
-{
-	const uint8_t size = MIN(SHI_OBUF_HALF_SIZE,
-				 shi_params.sz_response -
-				 shi_params.sz_sending);
-	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
-	const uint8_t *obuf_end = obuf_ptr + size;
-	uint8_t *msg_ptr = shi_params.tx_msg;
-
-	/* Fill half output buffer */
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/*
- * This routine write SHI output buffer from msg buffer over halt of it.
- * It make sure we have enought time to handle next operations.
- */
-static void shi_write_first_pkg_outbuf(uint16_t szbytes)
-{
-	uint8_t size, offset;
-	uint8_t *obuf_ptr;
-	uint8_t *obuf_end;
-	uint8_t *msg_ptr;
-
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	/*
-	 * If response package is across 256 bytes boundary,
-	 * bypass needs to extend PROCESSING bytes after reaching the boundary.
-	 */
-	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes
-	    > SHI_BYPASS_BOUNDARY) {
-		state = SHI_STATE_WAIT_ALIGNMENT;
-		/* Set pointer of output buffer to the start address */
-		shi_params.tx_buf = SHI_OBUF_START_ADDR;
-		DEBUG_CPRINTF("WAT-");
-		return;
-	}
-#endif
-
-	/* Start writing at our current OBUF position */
-	offset = SHI_OBUF_VALID_OFFSET;
-	obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR + offset;
-	msg_ptr = shi_params.tx_msg;
-
-	/* Fill up to OBUF mid point, or OBUF end */
-	size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE),
-					szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	/* Track bytes sent for later accounting */
-	shi_params.sz_sending += size;
-
-	/* Write data to beginning of OBUF if we've reached the end */
-	if (obuf_ptr == SHI_OBUF_FULL_ADDR)
-		obuf_ptr = (uint8_t *)SHI_OBUF_START_ADDR;
-
-	/* Fill next half output buffer */
-	size = MIN(SHI_OBUF_HALF_SIZE, szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*(obuf_ptr++) = *(msg_ptr++);
-
-	/* Track bytes sent / last OBUF position written for later accounting */
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/* This routine copies SHI half input buffer data to msg buffer */
-static void shi_read_half_inbuf(void)
-{
-	/*
-	 * Copy to read buffer until reaching middle/top address of
-	 * input buffer or completing receiving data
-	 */
-	do {
-		/* Restore data to msg buffer */
-		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
-		shi_params.sz_received++;
-	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE
-		&& shi_params.sz_received != shi_params.sz_request);
-}
-
-/*
- * This routine read SHI input buffer to msg buffer until
- * we have received a certain number of bytes
- */
-static int shi_read_inbuf_wait(uint16_t szbytes)
-{
-	uint16_t i;
-
-	/* Copy data to msg buffer from input buffer */
-	for (i = 0; i < szbytes; i++, shi_params.sz_received++) {
-		/*
-		 * If input buffer pointer equals pointer which wants to read,
-		 * it means data is not ready.
-		 */
-		while (shi_params.rx_buf == SHI_IBUF_CUR_ADDR)
-			if (timestamp_expired(shi_params.rx_deadline, NULL))
-				return 0;
-		/* Restore data to msg buffer */
-		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
-	}
-	return 1;
-}
-
-/* Read pointer of input or output buffer by consecutive reading */
-static uint8_t shi_read_buf_pointer(void)
-{
-	uint8_t stat;
-	/* Wait for two consecutive equal values are read */
-	do {
-		stat = NPCX_IBUFSTAT;
-	} while (stat != NPCX_IBUFSTAT);
-
-	return stat;
-}
-
-/* This routine handles shi recevied unexcepted data */
-static void shi_bad_received_data(void)
-{
-	uint16_t i;
-
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	shi_fill_out_status(EC_SPI_RX_BAD_DATA);
-	state = SHI_STATE_BAD_RECEIVED_DATA;
-
-	CPRINTF("BAD-");
-	CPRINTF("in_msg=[");
-	for (i = 0; i < shi_params.sz_received; i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-
-	/* Reset shi's state machine for error recovery */
-	shi_reset_prepare();
-
-	DEBUG_CPRINTF("END\n");
-}
-
-/*
- * Avoid spamming the console with prints every IBF / IBHF interrupt, if
- * we find ourselves in an unexpected state.
- */
-static int last_error_state = -1;
-
-static void log_unexpected_state(char *isr_name)
-{
-#if !(DEBUG_SHI)
-	if (state != last_error_state)
-		CPRINTS("Unexpected state %d in %s ISR", state, isr_name);
-#endif
-	last_error_state = state;
-}
-
-static void shi_handle_cs_assert(void)
-{
-	/* If not enabled, ignore glitches on SHI_CS_L */
-	if (state == SHI_STATE_DISABLED)
-		return;
-
-	/* SHI V2 module filters cs glitch by hardware automatically */
-#ifndef NPCX_SHI_V2
-	/*
-	 * IBUFSTAT resets on the 7th clock cycle after CS assertion, which
-	 * may not have happened yet. We use NPCX_IBUFSTAT for calculating
-	 * buffer fill depth, so make sure it's valid before proceeding.
-	 */
-	if (shi_is_cs_glitch()) {
-		CPRINTS("ERR-GTH");
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-		return;
-	}
-#endif
-
-	/* NOT_READY should be sent and there're no spi transaction now. */
-	if (state == SHI_STATE_CNL_RESP_NOT_RDY)
-		return;
-
-	/* Chip select is low = asserted */
-	if (state != SHI_STATE_READY_TO_RECV) {
-		/* State machine should be reset in EVSTAT_EOR ISR */
-		CPRINTS("Unexpected state %d in CS ISR", state);
-		return;
-	}
-
-	DEBUG_CPRINTF("CSL-");
-
-	/*
-	 * Clear possible EOR event from previous transaction since it's
-	 * irrelevant now that CS is re-asserted.
-	 */
-	NPCX_EVSTAT = 1 << NPCX_EVSTAT_EOR;
-
-	/* Do not deep sleep during SHI transaction */
-	disable_sleep(SLEEP_MASK_SPI);
-
-#ifndef NPCX_SHI_V2
-	/*
-	 * Enable SHI interrupt - we will either succeed to parse our host
-	 * command or reset on failure from here.
-	 */
-	task_enable_irq(NPCX_IRQ_SHI);
-
-	/* Read first three bytes to parse which protocol is receiving */
-	shi_parse_header();
-#endif
-}
-
-/* This routine handles all interrupts of this module */
-void shi_int_handler(void)
-{
-	uint8_t stat_reg;
-#ifdef NPCX_SHI_V2
-	uint8_t stat2_reg;
-#endif
-
-	/* Read status register and clear interrupt status early */
-	stat_reg = NPCX_EVSTAT;
-	NPCX_EVSTAT = stat_reg;
-#ifdef NPCX_SHI_V2
-	stat2_reg = NPCX_EVSTAT2;
-
-	/* SHI CS pin is asserted in EVSTAT2 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNFE)) {
-		/* clear CSNFE bit */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE);
-		DEBUG_CPRINTF("CSNFE-");
-		/*
-		 * BUSY bit is set when SHI_CS is asserted. If not, leave it for
-		 * SHI_CS de-asserted event.
-		 */
-		if (!IS_BIT_SET(NPCX_SHICFG2, NPCX_SHICFG2_BUSY)) {
-			DEBUG_CPRINTF("CSNB-");
-			return;
-		}
-		shi_handle_cs_assert();
-	}
-#endif
-
-	/*
-	 * End of data for read/write transaction. ie SHI_CS is deasserted.
-	 * Host completed or aborted transaction
-	 */
-#ifdef NPCX_SHI_V2
-	/*
-	 * EOR has the limitation that it will not be set even if the SHI_CS is
-	 * deasserted without SPI clocks. The new SHI module introduce the
-	 * CSNRE bit which will be set when SHI_CS is deasserted regardless of
-	 * SPI clocks.
-	 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNRE)) {
-		/* Clear pending bit of CSNRE */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE);
-#else
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_EOR)) {
-#endif
-		/*
-		 * We're not in proper state.
-		 * Mark not ready to abort next transaction
-		 */
-		DEBUG_CPRINTF("CSH-");
-		/*
-		 * If the buffer is still used by the host command.
-		 * Change state machine for response handler.
-		 */
-		if (state == SHI_STATE_PROCESSING) {
-			/*
-			 * Mark not ready to prevent the other
-			 * transaction immediately
-			 */
-			shi_fill_out_status(EC_SPI_NOT_READY);
-
-			state = SHI_STATE_CNL_RESP_NOT_RDY;
-
-			/*
-			 * Disable SHI interrupt, it will remain disabled
-			 * until shi_send_response_packet() is called and
-			 * CS is asserted for a new transaction.
-			 */
-			task_disable_irq(NPCX_IRQ_SHI);
-
-			DEBUG_CPRINTF("CNL-");
-			return;
-		/* Next transaction but we're not ready */
-		} else if (state == SHI_STATE_CNL_RESP_NOT_RDY)
-			return;
-
-		/* Error state for checking*/
-		if (state != SHI_STATE_SENDING)
-#ifdef NPCX_SHI_V2
-			log_unexpected_state("CSNRE");
-#else
-			log_unexpected_state("IBEOR");
-#endif
-
-		/* reset SHI and prepare to next transaction again */
-		shi_reset_prepare();
-		DEBUG_CPRINTF("END\n");
-		return;
-	}
-
-	/*
-	 * Indicate input/output buffer pointer reaches the half buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBHF)) {
-		if (state == SHI_STATE_RECEIVING) {
-			/* Read data from input to msg buffer */
-			shi_read_half_inbuf();
-			return shi_handle_host_package();
-		} else if (state == SHI_STATE_SENDING) {
-			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_FULL_SIZE) {
-				/* Write data from bottom address again */
-				shi_params.tx_buf = SHI_OBUF_START_ADDR;
-				return shi_write_half_outbuf();
-			} else /* ignore it */
-				return;
-		} else if (state == SHI_STATE_PROCESSING) {
-			/* Wait for host to handle request */
-		}
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		else if (state == SHI_STATE_WAIT_ALIGNMENT) {
-			/*
-			 * If pointer of output buffer will reach 256 bytes
-			 * boundary soon, start to fill response data.
-			 */
-			if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY -
-					SHI_OBUF_FULL_SIZE) {
-				state = SHI_STATE_SENDING;
-				DEBUG_CPRINTF("SND-");
-				return shi_write_half_outbuf();
-			}
-		}
-#endif
-		else
-			/* Unexpected status */
-			log_unexpected_state("IBHF");
-	}
-
-#ifdef NPCX_SHI_V2
-	/*
-	 * The size of input buffer reaches the size of
-	 * protocol V3 header(=8) after CS asserted.
-	 */
-	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_IBHF2)) {
-		/* Clear IBHF2 */
-		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2);
-		DEBUG_CPRINTF("HDR-");
-		/* Disable second IBF interrupt and start to parse header */
-		shi_sec_ibf_int_enable(0);
-		shi_parse_header();
-	}
-#endif
-
-	/*
-	 * Indicate input/output buffer pointer reaches the full buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) {
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-		/* Record the sent bytes within 256B boundary */
-		shi_params.bytes_in_256b = (shi_params.bytes_in_256b +
-				SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY;
-#endif
-		if (state == SHI_STATE_RECEIVING) {
-			/* read data from input to msg buffer */
-			shi_read_half_inbuf();
-			/* Read to bottom address again */
-			shi_params.rx_buf = SHI_IBUF_START_ADDR;
-			return shi_handle_host_package();
-		} else if (state == SHI_STATE_SENDING)
-			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_HALF_SIZE)
-				return shi_write_half_outbuf();
-			else /* ignore it */
-				return;
-		else if (state == SHI_STATE_PROCESSING
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-				|| state == SHI_STATE_WAIT_ALIGNMENT
-#endif
-				)
-			/* Wait for host handles request */
-			return;
-		else
-			/* Unexpected status */
-			log_unexpected_state("IBF");
-	}
-}
-DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 2);
-
-/* Handle an CS assert event on the SHI_CS_L pin */
-void shi_cs_event(enum gpio_signal signal)
-{
-#ifdef NPCX_SHI_V2
-	/*
-	 * New SHI module handles the CS low event in the SHI module interrupt
-	 * handler (checking CSNFE bit) instead of in GPIO(MIWU) interrupt
-	 * handler. But there is still a need to configure the MIWU to generate
-	 * event to wake up EC from deep sleep. Immediately return to bypass
-	 * the CS low interrupt event from MIWU module.
-	 */
-	return;
-#else
-	shi_handle_cs_assert();
-#endif
-
-}
-
-/*****************************************************************************/
-/* Hook functions for chipset and initialization */
-
-/*
- * Reset SHI bus and prepare next transaction
- * Please make sure it is executed when there're no spi transactions
- */
-static void shi_reset_prepare(void)
-{
-	uint16_t i;
-
-	/* We no longer care about SHI interrupts, so disable them. */
-	task_disable_irq(NPCX_IRQ_SHI);
-
-	/* Disable SHI unit to clear all status bits */
-	CLEAR_BIT(NPCX_SHICFG1, NPCX_SHICFG1_EN);
-
-	/* Initialize parameters of next transaction */
-	shi_params.rx_msg = in_msg;
-	shi_params.tx_msg = out_msg;
-	shi_params.rx_buf = SHI_IBUF_START_ADDR;
-	shi_params.tx_buf = SHI_OBUF_HALF_ADDR;
-	shi_params.sz_received = 0;
-	shi_params.sz_sending = 0;
-	shi_params.sz_request = 0;
-	shi_params.sz_response = 0;
-#ifdef NPCX_SHI_BYPASS_OVER_256B
-	shi_params.bytes_in_256b = 0;
-#endif
-	/* Record last IBUFSTAT for glitch case */
-	shi_params.pre_ibufstat = shi_read_buf_pointer();
-
-	/*
-	 * Fill output buffer to indicate we`re
-	 * ready to receive next transaction.
-	 */
-	for (i = 1; i < SHI_OBUF_FULL_SIZE; i++)
-		NPCX_OBUF(i) = EC_SPI_RECEIVING;
-	NPCX_OBUF(0) = EC_SPI_OLD_READY;
-
-	/* Enable SHI & WEN functionality */
-	NPCX_SHICFG1 = 0x85;
-
-	/* Ready to receive */
-	state = SHI_STATE_READY_TO_RECV;
-	last_error_state = -1;
-
-	/* Setup second IBF interrupt and enable SHI's interrupt */
-#ifdef NPCX_SHI_V2
-	shi_sec_ibf_int_enable(1);
-	task_enable_irq(NPCX_IRQ_SHI);
-#endif
-
-	/* Allow deep sleep at the end of SHI transaction */
-	enable_sleep(SLEEP_MASK_SPI);
-
-	DEBUG_CPRINTF("RDY-");
-}
-
-static void shi_enable(void)
-{
-	int gpio_flags;
-
-	shi_reset_prepare();
-
-	/* Ensure SHI_CS_L interrupt is disabled */
-	gpio_disable_interrupt(GPIO_SHI_CS_L);
-
-	/* Enable PU, if requested */
-	gpio_flags = GPIO_INPUT | GPIO_INT_F_FALLING;
-#ifdef NPCX_SHI_CS_PU
-	gpio_flags |= GPIO_PULL_UP;
-#endif
-	gpio_set_flags(GPIO_SHI_CS_L, gpio_flags);
-
-	/*
-	 * Mux SHI related pins
-	 * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to device pins
-	 */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL);
-
-	task_clear_pending_irq(NPCX_IRQ_SHI);
-
-	/* Enable SHI_CS_L interrupt */
-	gpio_enable_interrupt(GPIO_SHI_CS_L);
-
-	/*
-	 * If CS is already asserted prior to enabling our GPIO interrupt then
-	 * we have missed the falling edge and we need to handle the
-	 * deassertion interrupt.
-	 */
-	task_enable_irq(NPCX_IRQ_SHI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, shi_enable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT);
-#endif
-
-static void shi_reenable_on_sysjump(void)
-{
-#if !(DEBUG_SHI)
-	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
-#endif
-		shi_enable();
-}
-/* Call hook after chipset sets initial power state */
-DECLARE_HOOK(HOOK_INIT,
-	     shi_reenable_on_sysjump,
-	     HOOK_PRIO_INIT_CHIPSET + 1);
-
-/* Disable SHI bus */
-static void shi_disable(void)
-{
-	state = SHI_STATE_DISABLED;
-
-	task_disable_irq(NPCX_IRQ_SHI);
-
-	/* Disable SHI_CS_L interrupt */
-	gpio_disable_interrupt(GPIO_SHI_CS_L);
-
-	/* Restore SHI_CS_L back to default state */
-	gpio_reset(GPIO_SHI_CS_L);
-
-	/*
-	 * Mux SHI related pins
-	 * SHI_SDI SHI_SDO SHI_CS# SHI_SCLK are selected to GPIO
-	 */
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_C), NPCX_DEVALTC_SHI_SL);
-
-	/*
-	 * Allow deep sleep again in case CS dropped before ec was
-	 * informed in hook function and turn off SHI's interrupt in time.
-	 */
-	enable_sleep(SLEEP_MASK_SPI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, shi_disable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT);
-#endif
-DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT);
-
-static void shi_init(void)
-{
-	/* Power on SHI module first */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_SHI_PD);
-
-#ifdef NPCX_SHI_V2
-	/* Enable SHI module Version 2 */
-	SET_BIT(NPCX_DEVALT(ALT_GROUP_F), NPCX_DEVALTF_SHI_NEW);
-#endif
-
-	/*
-	 * SHICFG1 (SHI Configuration 1) setting
-	 * [7] - IWRAP	= 1: Wrap input buffer to the first address
-	 * [6] - CPOL	= 0: Sampling on rising edge and output on falling edge
-	 * [5] - DAS	= 0: return STATUS reg data after Status command
-	 * [4] - AUTOBE	= 0: Automatically update the OBES bit in STATUS reg
-	 * [3] - AUTIBF	= 0: Automatically update the IBFS bit in STATUS reg
-	 * [2] - WEN    = 0: Enable host write to input buffer
-	 * [1] - Reserved 0
-	 * [0] - ENABLE	= 0: Disable SHI at the beginning
-	 */
-	NPCX_SHICFG1 = 0x80;
-
-	/*
-	 * SHICFG2 (SHI Configuration 2) setting
-	 * [7] - Reserved 0
-	 * [6] - REEVEN = 0: Restart events are not used
-	 * [5] - Reserved 0
-	 * [4] - REEN   = 0: Restart transactions are not used
-	 * [3] - SLWU   = 0: Seem-less wake-up is enabled by default
-	 * [2] - ONESHOT= 0: WEN is cleared at the end of a write transaction
-	 * [1] - BUSY   = 0: SHI bus is busy 0: idle.
-	 * [0] - SIMUL	= 1: Turn on simultaneous Read/Write
-	 */
-	NPCX_SHICFG2 = 0x01;
-
-	/*
-	 * EVENABLE (Event Enable) setting
-	 * [7] - IBOREN = 0: Input buffer overrun interrupt enable
-	 * [6] - STSREN = 0: status read interrupt disable
-	 * [5] - EOWEN  = 0: End-of-Data for Write Transaction Interrupt Enable
-	 * [4] - EOREN  = 1: End-of-Data for Read Transaction Interrupt Enable
-	 * [3] - IBHFEN = 1: Input Buffer Half Full Interrupt Enable
-	 * [2] - IBFEN  = 1: Input Buffer Full Interrupt Enable
-	 * [1] - OBHEEN = 0: Output Buffer Half Empty Interrupt Enable
-	 * [0] - OBEEN  = 0: Output Buffer Empty Interrupt Enable
-	 */
-	NPCX_EVENABLE = 0x1C;
-
-#ifdef NPCX_SHI_V2
-	/*
-	 * EVENABLE2 (Event Enable 2) setting
-	 * [2] - CSNFEEN = 1: SHI_CS Falling Edge Interrupt Enable
-	 * [1] - CSNREEN = 1: SHI_CS Rising Edge Interrupt Enable
-	 * [0] - IBHF2EN = 0: Input Buffer Half Full 2 Interrupt Enable
-	 */
-	NPCX_EVENABLE2 = 0x06;
-#endif
-
-	/* Clear SHI events status register */
-	NPCX_EVSTAT = 0XFF;
-}
-/* Call hook before chipset sets initial power state and calls resume hooks */
-DECLARE_HOOK(HOOK_INIT, shi_init, HOOK_PRIO_INIT_CHIPSET - 1);
-
-/**
- * Get protocol information
- */
-static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = SHI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SHI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
-EC_VER_MASK(0));
diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h
deleted file mode 100644
index c14aec196e..0000000000
--- a/chip/npcx/shi_chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SHI module for Chrome EC */
-
-#ifndef SHI_CHIP_H_
-#define SHI_CHIP_H_
-
-#ifdef CONFIG_HOSTCMD_SHI
-/**
- * Called when the NSS level changes, signalling the start of a SHI
- * transaction.
- *
- * @param signal	GPIO signal that changed
- */
-void shi_cs_event(enum gpio_signal signal);
-#ifdef NPCX_SHI_V2
-void shi_cs_gpio_int(enum gpio_signal signal);
-#endif
-#endif
-
-#endif /* SHI_CHIP_H_ */
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
deleted file mode 100644
index b8e2e17955..0000000000
--- a/chip/npcx/sib.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-#include "console.h"
-#include "hwtimer_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * Timeout to wait for host transaction to be completed.
- *
- * For eSPI - it is 200 us.
- * For LPC - it is 5 us.
- */
-#ifdef CONFIG_HOSTCMD_ESPI
-#define HOST_TRANSACTION_TIMEOUT_US 200
-#else
-#define HOST_TRANSACTION_TIMEOUT_US 5
-#endif
-
-/* Console output macros */
-#ifdef DEBUG_SIB
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#else
-#define CPUTS(...)
-#define CPRINTS(...)
-#endif
-
-/*
- * Check host read is not in-progress and no timeout
- */
-static void sib_wait_host_read_done(void)
-{
-	timestamp_t deadline, start;
-
-	start = get_time();
-	deadline.val = start.val + HOST_TRANSACTION_TIMEOUT_US;
-	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD)) {
-		if (timestamp_expired(deadline, NULL)) {
-			CPRINTS("Unexpected time of host read transaction");
-			break;
-		}
-		/* Handle ITIM32 overflow condition */
-		__hw_clock_handle_overflow(start.le.hi);
-	}
-}
-
-/*
- * Check host write is not in-progress and no timeout
- */
-static void sib_wait_host_write_done(void)
-{
-	timestamp_t deadline, start;
-
-	start = get_time();
-	deadline.val = start.val + HOST_TRANSACTION_TIMEOUT_US;
-	while (IS_BIT_SET(NPCX_SIBCTRL, NPCX_SIBCTRL_CSWR)) {
-		if (timestamp_expired(deadline, NULL)) {
-			CPRINTS("Unexpected time of host write transaction");
-			break;
-		}
-		/* Handle ITIM32 overflow condition */
-		__hw_clock_handle_overflow(start.le.hi);
-	}
-}
-
-/* Emulate host to read Keyboard I/O */
-uint8_t sib_read_kbc_reg(uint8_t io_offset)
-{
-	uint8_t data_value;
-
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host keyboard module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-	/* Enable Core access to keyboard module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-
-	/* Start a Core read from host module */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
-	/* Wait while Core read operation is in progress */
-	sib_wait_host_read_done();
-	/* Read the data */
-	data_value = NPCX_IHD;
-
-	/* Disable Core access to keyboard module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
-	/* unlock host keyboard module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
-
-	/* Enable interrupts */
-	interrupt_enable();
-
-	return data_value;
-}
-
-/* Super-IO read/write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data)
-{
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host CFG module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core access to CFG module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = index_value;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = io_data;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Disable Core access to CFG module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* unlock host CFG  module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-
-	/* Enable interrupts */
-	interrupt_enable();
-}
-
-uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value)
-{
-	uint8_t data_value;
-
-	/* Disable interrupts */
-	interrupt_disable();
-
-	/* Lock host CFG module */
-	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-	/* Enable Core access to CFG module */
-	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* Verify Core read/write to host modules is not in progress */
-	sib_wait_host_read_done();
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 0. the index register is accessed */
-	NPCX_IHIOA = io_offset;
-	/* Write the data. This starts the write access to the host module */
-	NPCX_IHD = index_value;
-	/* Wait while Core write operation is in progress */
-	sib_wait_host_write_done();
-
-	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
-	/* Start a Core read from host module */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
-	/* Wait while Core read operation is in progress */
-	sib_wait_host_read_done();
-	/* Read the data */
-	data_value = NPCX_IHD;
-
-	/* Disable Core access to CFG module */
-	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
-	/* unlock host CFG  module */
-	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
-
-	/* Enable interrupts */
-	interrupt_enable();
-
-	return data_value;
-}
-
diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h
deleted file mode 100644
index 2341f219b4..0000000000
--- a/chip/npcx/sib_chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-/* Super-IO index and register definitions */
-#define INDEX_SID       0x20
-#define INDEX_CHPREV    0x24
-#define INDEX_SRID      0x27
-
-#define SIO_OFFSET      0x4E
-
-/* Super-IO register write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data);
-/* Super-IO register read function */
-uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value);
-/* Emulate host to read Keyboard I/O */
-uint8_t sib_read_kbc_reg(uint8_t io_offset);
-
diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c
deleted file mode 100644
index 55fa8f85ab..0000000000
--- a/chip/npcx/spi.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI module for Chrome EC */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "clock.h"
-#include "clock_chip.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#if !DEBUG_SPI
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#endif
-
-/* SPI IP as SPI controller */
-#define SPI_CLK         8000000
-/**
- * Clear SPI data buffer.
- *
- * @param none
- * @return none.
- */
-static void clear_databuf(void)
-{
-	volatile uint8_t unused __attribute__((unused));
-	while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-		unused = NPCX_SPI_DATA;
-}
-
-/**
- * Preset SPI operation clock.
- *
- * @param   none
- * @return  none
- * @notes   changed when initial or HOOK_FREQ_CHANGE command
- */
-void spi_freq_changed(void)
-{
-	uint8_t prescaler_divider    = 0;
-
-	/* Set clock prescaler divider to SPI module*/
-	prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq()
-			/ 2 / SPI_CLK);
-	if (prescaler_divider >= 1)
-		prescaler_divider = prescaler_divider - 1;
-	if (prescaler_divider > 0x7F)
-		prescaler_divider = 0x7F;
-
-	/* Set core clock division factor in order to obtain the SPI clock */
-	NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV)))
-			|(prescaler_divider<<NPCX_SPI_CTL1_SCDV);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST);
-
-/**
- * Set SPI enabled.
- *
- * @spi_device SPI device to act on.
- * @param   enable enabled flag
- * @return  success
- */
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	enum gpio_signal gpio;
-
-	if (enable) {
-		/* Enabling spi module for gpio configuration */
-		gpio_config_module(MODULE_SPI, 1);
-		/* GPIO No SPI Select */
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-
-		gpio = spi_device->gpio_cs;
-		/* Make sure CS# is in GPIO output mode. */
-		gpio_set_flags(gpio, GPIO_OUTPUT);
-		/* Make sure CS# is deselected */
-		gpio_set_level(gpio, 1);
-
-		/* Enabling spi module */
-		SET_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
-	} else {
-		/* Disabling spi module */
-		CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
-		gpio = spi_device->gpio_cs;
-		/* Make sure CS# is deselected */
-		gpio_set_level(gpio, 1);
-		gpio_set_flags(gpio, GPIO_ODR_HIGH);
-		/* Disabling spi module for gpio configuration */
-		gpio_config_module(MODULE_SPI, 0);
-		/* GPIO No SPI Select */
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
-	}
-	return EC_SUCCESS;
-}
-
-
-/**
- * Flush an SPI transaction and receive data from peripheral.
- *
- * @param   spi_device  device to talk to
- * @param   txdata  transfer data
- * @param   txlen   transfer length
- * @param   rxdata  receive data
- * @param   rxlen   receive length
- * @return  success
- * @notes   set controller transaction mode in npcx chip
- */
-int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
-{
-	int i = 0;
-	enum gpio_signal gpio = spi_device->gpio_cs;
-	static struct mutex spi_lock;
-
-	mutex_lock(&spi_lock);
-	/* Make sure CS# is a GPIO output mode. */
-	gpio_set_flags(gpio, GPIO_OUTPUT);
-	/* Make sure CS# is deselected */
-	gpio_set_level(gpio, 1);
-	/* Cleaning junk data in the buffer */
-	clear_databuf();
-	/* Assert CS# to start transaction */
-	gpio_set_level(gpio, 0);
-	CPRINTS("NPCX_SPI_DATA=%x", NPCX_SPI_DATA);
-	CPRINTS("NPCX_SPI_CTL1=%x", NPCX_SPI_CTL1);
-	CPRINTS("NPCX_SPI_STAT=%x", NPCX_SPI_STAT);
-	/* Writing the data */
-	for (i = 0; i < txlen; ++i) {
-		/* Making sure we can write */
-		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
-			;
-		/* Write the data */
-		NPCX_SPI_DATA =  txdata[i];
-		CPRINTS("txdata[i]=%x", txdata[i]);
-		/* Waiting till reading is finished */
-		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-			;
-		/* Reading the (unused) data */
-		clear_databuf();
-	}
-	CPRINTS("write end");
-	/* Reading the data */
-	for (i = 0; i < rxlen; ++i) {
-		/* Making sure we can write */
-		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
-			;
-		/* Write the (unused) data */
-		NPCX_SPI_DATA =  0;
-		/* Wait till reading is finished */
-		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-			;
-		/* Reading the data */
-		rxdata[i] = (uint8_t)NPCX_SPI_DATA;
-		CPRINTS("rxdata[i]=%x", rxdata[i]);
-	}
-	/* Deassert CS# (high) to end transaction */
-	gpio_set_level(gpio, 1);
-	mutex_unlock(&spi_lock);
-
-	return EC_SUCCESS;
-}
-
-/**
- * SPI initial.
- *
- * @param none
- * @return none
- */
-static void spi_init(void)
-{
-	int i;
-	/* Enable clock for SPI peripheral */
-	clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
-
-	/* Disabling spi module */
-	for (i = 0; i < spi_devices_used; i++)
-		spi_enable(&spi_devices[i], 0);
-
-	/* Disabling spi irq */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIR);
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_EIW);
-
-	/* Setting clocking mode to normal mode */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCM);
-	/* Setting 8bit mode transfer */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_MOD);
-	/* Set core clock division factor in order to obtain the spi clock */
-	spi_freq_changed();
-
-	/* We emit zeros in idle (default behaivor) */
-	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);
-
-	CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
-	CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
-			NPCX_DEV_CTL4_SPI_SP_SEL));
-	/* Cleaning junk data in the buffer */
-	clear_databuf();
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_SPI_FLASH
-static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		int rxlen)
-{
-	uint8_t rxdata[32];
-	int rv;
-	int i;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
-	if (rv)
-		return rv;
-
-	CPRINTS("%-12s:", desc);
-	for (i = 0; i < rxlen; i++)
-		CPRINTS(" 0x%02x", rxdata[i]);
-	CPUTS("\n");
-	return EC_SUCCESS;
-}
-
-static int command_spirom(int argc, char **argv)
-{
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
-	printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
-	printrx("Unique ID", txunique, sizeof(txunique), 8);
-	printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
-	printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
-
-	spi_enable(SPI_FLASH_DEVICE, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-		NULL,
-		"Test reading SPI EEPROM");
-#endif
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
deleted file mode 100644
index 219a037d27..0000000000
--- a/chip/npcx/spiflashfw/monitor_hdr.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool -  monitor firmware header
- */
-
-#include "config.h"
-#include "npcx_monitor.h"
-
-const struct monitor_header_tag monitor_hdr = {
-	/* 0x00: TAG = 0xA5075001 */
-	NPCX_MONITOR_UUT_TAG,
-	/* 0x04: Size·of·the·EC image·be·programmed.
-	 * Default = code RAM size
-	 */
-	NPCX_PROGRAM_MEMORY_SIZE,
-	/*
-	 * 0x08: The start of RAM address to store the EC image, which will be
-	 * programed into the SPI flash.
-	 */
-	CONFIG_PROGRAM_MEMORY_BASE,
-	/* 0x0C:The Flash start address to be programmed*/
-#ifdef SECTION_IS_RO
-	/* Default: RO image is programed from the start of SPI flash */
-	CONFIG_EC_PROTECTED_STORAGE_OFF,
-#else
-	/* Default: RW image is programed from the half of SPI flash */
-	CONFIG_EC_WRITABLE_STORAGE_OFF,
-#endif
-	/* 0x10: Maximum allowable flash clock frequency */
-	0,
-	/* 0x11: SPI Flash read mode */
-	0,
-	/* 0x12: Reserved */
-	0,
-};
diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c
deleted file mode 100644
index cd52e7a80f..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool - monitor firmware
- */
-
-#include <stdint.h>
-#include "config.h"
-#include "npcx_monitor.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* spi flash internal functions */
-void sspi_flash_pinmux(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-
-	/* CS0/1 pinmux */
-	if (enable) {
-#if (FIU_CHIP_SELECT == 1)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-#elif (FIU_CHIP_SELECT == 2)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-#endif
-	} else {
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-	}
-}
-
-void sspi_flash_tristate(int enable)
-{
-	if (enable) {
-		/* Enable FIU pins to tri-state */
-		SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	} else {
-		/* Disable FIU pins to tri-state */
-		CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	}
-}
-
-void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
-{
-	/* set UMA_CODE */
-	NPCX_UMA_CODE = code;
-	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
-	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-void sspi_flash_cs_level(int level)
-{
-	/* level is high */
-	if (level) {
-		/* Set chip select to high */
-		SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	} else { /* level is low */
-		/* Set chip select to low */
-		CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	}
-}
-
-void sspi_flash_wait_ready(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_BUSY;
-
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Command for Read status register */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
-	do {
-		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
-	/* Chip Select high. */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_write_enable(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_WEL;
-	/* Write enable command */
-	sspi_flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
-	/* Wait for flash is not busy */
-	sspi_flash_wait_ready();
-
-	if (NPCX_UMA_DB0 & mask)
-		return 1;
-	else
-		return 0;
-}
-
-void sspi_flash_set_address(uint32_t dest_addr)
-{
-	uint8_t *addr = (uint8_t *)&dest_addr;
-	/* Write address */
-	NPCX_UMA_AB2 = addr[2];
-	NPCX_UMA_AB1 = addr[1];
-	NPCX_UMA_AB0 = addr[0];
-}
-
-void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
-{
-	unsigned int i;
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Set erase address */
-	sspi_flash_set_address(dest_addr);
-	/* Start write */
-	sspi_flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
-	for (i = 0; i < bytes; i++) {
-		sspi_flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
-		data++;
-	}
-	/* Chip Select up */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_physical_clear_stsreg(void)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-	/* Enable write */
-	sspi_flash_write_enable();
-
-	NPCX_UMA_DB0 = 0x0;
-	NPCX_UMA_DB1 = 0x0;
-
-	/* Write status register 1/2 */
-	sspi_flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-
-	/* Wait writing completed */
-	sspi_flash_wait_ready();
-
-	/* Read status register 1/2 for checking */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-
-	return 1;
-}
-
-void sspi_flash_physical_write(int offset, int size, const char *data)
-{
-	int dest_addr = offset;
-	const int sz_page = CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Write the data per CONFIG_FLASH_WRITE_IDEAL_SIZE bytes */
-	for (; size >= sz_page; size -= sz_page) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, sz_page, data);
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-
-		data += sz_page;
-		dest_addr += sz_page;
-	}
-
-	/* Handle final partial page, if any */
-	if (size != 0) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, size, data);
-
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-void sspi_flash_physical_erase(int offset, int size)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Set erase address */
-		sspi_flash_set_address(offset);
-		/* Start erase */
-		sspi_flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
-
-		/* Wait erase completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-int sspi_flash_verify(int offset, int size, const char *data)
-{
-	int i, result;
-	uint8_t *ptr_flash;
-	uint8_t *ptr_mram;
-	uint8_t cmp_data;
-
-	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
-	result = 1;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Start to verify */
-	for (i = 0; i < size; i++) {
-		cmp_data = ptr_mram ? ptr_mram[i] : 0xFF;
-		if (ptr_flash[i] != cmp_data) {
-			result = 0;
-			break;
-		}
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-	return result;
-}
-
-int sspi_flash_get_image_used(const char *fw_base)
-{
-	const uint8_t *image;
-	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
-
-	image = (const uint8_t *)fw_base;
-	/*
-	 * Scan backwards looking for 0xea byte, which is by definition the
-	 * last byte of the image.  See ec.lds.S for how this is inserted at
-	 * the end of the image.
-	 */
-	for (size--; size > 0 && image[size] != 0xea; size--)
-		;
-
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
-}
-
-/* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
-sspi_flash_upload(int spi_offset, int spi_size)
-{
-	/*
-	 * Flash image has been uploaded to Code RAM
-	 */
-	uint32_t sz_image;
-	uint32_t uut_tag;
-	const char *image_base;
-	uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG;
-	struct monitor_header_tag *monitor_header =
-		(struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR;
-
-	*flag_upload = 0;
-
-	uut_tag = monitor_header->tag;
-	/* If it is UUT tag, read required parameters from header */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG) {
-		sz_image = monitor_header->size;
-		spi_offset = monitor_header->dest_addr;
-		image_base = (const char *)(monitor_header->src_addr);
-	} else {
-		sz_image = spi_size;
-		image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	/* Unlock & stop watchdog */
-	NPCX_WDSDM = 0x87;
-	NPCX_WDSDM = 0x61;
-	NPCX_WDSDM = 0x63;
-
-	/* UMA Unlock */
-	CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
-
-	/*
-	 * If UUT is used, assuming the target is the internal flash.
-	 * Don't switch the pinmux and make sure bit 7 of DEVALT0 is set.
-	 */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		/* Set pinmux first */
-		sspi_flash_pinmux(1);
-
-	/* Get size of image automatically */
-	if (sz_image == 0)
-		sz_image = sspi_flash_get_image_used(image_base);
-
-	/* Clear status reg of spi flash for protection */
-	if (sspi_flash_physical_clear_stsreg()) {
-		/* Start to erase */
-		sspi_flash_physical_erase(spi_offset, sz_image);
-		/* Start to write */
-		if (image_base != NULL)
-			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
-		/* Verify data */
-		if (sspi_flash_verify(spi_offset, sz_image, image_base))
-			*flag_upload |= 0x02;
-	}
-	if (uut_tag != NPCX_MONITOR_UUT_TAG)
-		/* Disable pinmux */
-		sspi_flash_pinmux(0);
-
-	/* Mark we have finished upload work */
-	*flag_upload |= 0x01;
-
-	/* Return the status back to ROM code is required for UUT */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		return *flag_upload;
-
-	/* Infinite loop */
-	for (;;)
-		;
-}
-
diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h
deleted file mode 100644
index f4f30454d2..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_NPCX_MONITOR_H
-#define __CROS_EC_NPCX_MONITOR_H
-
-#include <stdint.h>
-
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
-
-/* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
-
-struct monitor_header_tag {
-	/* offset 0x00: TAG NPCX_MONITOR_TAG */
-	uint32_t tag;
-	/* offset 0x04: Size of the binary being programmed (in bytes) */
-	uint32_t size;
-	/* offset 0x08: The RAM address of the binary to program into the SPI */
-	uint32_t src_addr;
-	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
-	uint32_t dest_addr;
-	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
-	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
-	/* offset 0x12: Reserved */
-	uint16_t reserved;
-} __packed;
-
-#endif /* __CROS_EC_NPCX_MONITOR_H */
diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld
deleted file mode 100644
index 03e38b0609..0000000000
--- a/chip/npcx/spiflashfw/npcx_monitor.ld
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0
-}
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(sspi_flash_upload)
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    .startup_text :
-    {
-        . = ALIGN(4);
-        *(.startup_text )	/* Startup code */
-        . = ALIGN(4);
-    } >CODERAM
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to CODERAM.
-     */
-    .text :
-    {
-        . = ALIGN(4);
-        *(.text .text.*)			/* all remaining code */
-        *(.rodata .rodata.*)		/* read-only data (constants) */
-    } >CODERAM
-
-    . = ALIGN(4);
-    _etext = .;
-
-    /*
-     * This address is used by the startup code to
-     * initialise the .data section.
-     */
-    _sidata = _etext;
-
-}
diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c
deleted file mode 100644
index 4dd12fbae2..0000000000
--- a/chip/npcx/system-npcx5.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdnoreturn.h>
-
-/* System module driver depends on chip series for Chrome EC */
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hwtimer_chip.h"
-#include "mpu.h"
-#include "registers.h"
-#include "rom_chip.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "util.h"
-
-/* Begin address of Suspend RAM for hibernate utility */
-uintptr_t __lpram_fw_start = CONFIG_LPRAM_BASE;
-/* Offset of little FW in Suspend Ram for GDMA bypass */
-#define LFW_OFFSET 0x160
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-/**
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
-void system_mpu_config(void)
-{
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-}
-
-/**
- * hibernate function in low power ram for npcx5 series.
- */
-noreturn void __keep __attribute__ ((section(".lowpower_ram")))
-__enter_hibernate_in_lpram(void)
-{
-	/*
-	 * TODO (ML): Set stack pointer to upper 512B of Suspend RAM.
-	 * Our bypass needs stack instructions but FW will turn off main ram
-	 * later for better power consumption.
-	 */
-	asm (
-		"ldr r0, =0x40001800\n"
-		"mov sp, r0\n"
-	);
-
-	/* Disable Code RAM first */
-	SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS);
-	SET_BIT(NPCX_DISIDL_CTL, NPCX_DISIDL_CTL_RAM_DID);
-
-	/* Set deep idle mode*/
-	NPCX_PMCSR = 0x6;
-
-	/* Enter deep idle, wake-up by GPIOs or RTC */
-	/*
-	 * TODO (ML): Although the probability is small, it still has chance
-	 * to meet the same symptom that CPU's behavior is abnormal after
-	 * wake-up from deep idle.
-	 * Workaround: Apply the same bypass of idle but don't enable interrupt.
-	 */
-	asm (
-		"push {r0-r5}\n"        /* Save needed registers */
-		"ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
-		"wfi\n"                 /* Wait for int to enter idle */
-		"ldm r0, {r0-r5}\n"     /* Add a delay after WFI */
-		"pop {r0-r5}\n"         /* Restore regs before enabling ints */
-		"isb\n"                 /* Flush the cpu pipeline */
-	);
-
-	/* RTC wake-up */
-	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
-		/*
-		 * Mark wake-up reason for hibernate
-		 * Do not call bbram_data_write directly cause of
-		 * executing in low-power ram
-		 */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
-	else
-		/* Otherwise, we treat it as GPIOs wake-up */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
-
-	/* Start a watchdog reset */
-	NPCX_WDCNT = 0x01;
-	/* Reload and restart Timer 0 */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-/**
- * Hibernate function for different Nuvoton chip series.
- */
-void __hibernate_npcx_series(void)
-{
-	int i;
-	void (*__hibernate_in_lpram)(void) =
-			(void(*)(void))(__lpram_fw_start | 0x01);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/* Copy the __enter_hibernate_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++)
-		*((uint32_t *)__lpram_fw_start + i) =
-				*(&__flash_lpfw_start + i);
-
-	/* execute hibernate func in LPRAM */
-	__hibernate_in_lpram();
-}
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-/* Sysjump utilities in low power ram for npcx5 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	ASSERT(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
-#endif /* CONFIG_EXTERNAL_STORAGE */
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c
deleted file mode 100644
index 89b3e25e9b..0000000000
--- a/chip/npcx/system-npcx7.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdnoreturn.h>
-
-/* System module driver depends on chip series for Chrome EC */
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "lct_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "gpio.h"
-#include "hwtimer_chip.h"
-#include "mpu.h"
-#include "system_chip.h"
-#include "rom_chip.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-/* Macros for last 32K ram block */
-#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
-/* Higher bits are reserved and need to be masked */
-#define RAM_PD_MASK  (~BIT(LAST_RAM_BLK))
-
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#define LFW_OFFSET 0x160
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-#endif
-/*****************************************************************************/
-/* IC specific low-level driver depends on chip series */
-
-/*
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
-void system_mpu_config(void)
-{
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-	/*
-	 * npcx9 Rev.1 has the problem for download_from_flash API.
-	 * Workwaroud it by by the system_download_from_flash function
-	 * in the suspend RAM like npcx5.
-	 * TODO: Remove this when A2 chip is available
-	 */
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-#endif
-}
-
-#ifdef CONFIG_HIBERNATE_PSL
-#ifndef NPCX_PSL_MODE_SUPPORT
-#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!"
-#endif
-
-static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal)
-{
-	enum psl_pin_t psl_no;
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
-		psl_no = PSL_IN1;
-	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
-		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
-	else
-		psl_no = PSL_NONE;
-
-	return psl_no;
-}
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-void system_set_psl_gpo(int level)
-{
-	if (level)
-		SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
-	else
-		CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
-}
-#endif
-
-void system_enter_psl_mode(void)
-{
-	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
-	gpio_config_module(MODULE_PMU, 1);
-
-	/*
-	 * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and
-	 * reboot ec.
-	 * In npcx9, LCT timeout event can also pull PSL_OUT.
-	 * We won't decide the wake cause now but only mark we are entering
-	 * hibernation via PSL.
-	 * The actual wakeup cause will be checked by the PSL input event bits
-	 * when ec reboots.
-	 */
-	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	 /*
-	  * If pulse mode is enabled, the VCC power is turned off by the
-	  * external component (Ex: PMIC) but PSL_OUT. So we can just return
-	  * here.
-	  */
-	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
-		return;
-#endif
-
-	/*
-	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
-	 * setting bit 5 of PDOUT(8).
-	 */
-	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
-}
-
-/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
-noreturn void __keep __enter_hibernate_in_psl(void)
-{
-	system_enter_psl_mode();
-	/* Spin and wait for PSL cuts power; should never return */
-	while (1)
-		;
-}
-
-static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
-{
-	/* Set PSL input events' type as level or edge trigger */
-	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
-		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-	else if ((flags & GPIO_INT_F_RISING) ||
-		 (flags & GPIO_INT_F_FALLING))
-		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-
-	/*
-	 * Set PSL input events' polarity is low (high-to-low) active or
-	 * high (low-to-high) active
-	 */
-	if (flags & GPIO_HIB_WAKE_HIGH)
-		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
-	else
-		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
-}
-
-int system_config_psl_mode(enum gpio_signal signal)
-{
-	enum psl_pin_t psl_no;
-	const struct gpio_info *g = gpio_list + signal;
-
-	psl_no = system_gpio_to_psl(signal);
-	if (psl_no == PSL_NONE)
-		return 0;
-
-	system_psl_type_sel(psl_no, g->flags);
-	return 1;
-}
-
-#else
-/**
- * Hibernate function in last 32K ram block for npcx7 series.
- * Do not use global variable since we also turn off data ram.
- */
-noreturn void __keep __attribute__ ((section(".after_init")))
-__enter_hibernate_in_last_block(void)
-{
-	/*
-	 * The hibernate utility is located in the last block of RAM. The size
-	 * of each RAM block is 32KB. We turn off all blocks except last one
-	 * for better power consumption.
-	 */
-	NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF;
-#if defined(CHIP_FAMILY_NPCX7)
-	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F;
-#elif defined(CHIP_FAMILY_NPCX9)
-	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F;
-#endif
-
-	/* Set deep idle mode */
-	NPCX_PMCSR = 0x6;
-
-	/* Enter deep idle, wake-up by GPIOs or RTC */
-	asm volatile ("wfi");
-
-	/* RTC wake-up */
-	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
-		/*
-		 * Mark wake-up reason for hibernate
-		 * Do not call bbram_data_write directly cause of
-		 * no stack.
-		 */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
-#ifdef NPCX_LCT_SUPPORT
-	else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) {
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT;
-		/* Clear LCT event */
-		NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
-	}
-#endif
-	else
-		/* Otherwise, we treat it as GPIOs wake-up */
-		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
-
-	/* Start a watchdog reset */
-	NPCX_WDCNT = 0x01;
-	/* Reload and restart Timer 0 */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-#endif
-
-/**
- * Hibernate function for different Nuvoton chip series.
- */
-void __hibernate_npcx_series(void)
-{
-#ifdef CONFIG_HIBERNATE_PSL
-	__enter_hibernate_in_psl();
-#else
-	/* Make sure this is located in the last 32K code RAM block */
-	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE
-								< (32*1024));
-
-	/* Execute hibernate func in last 32K block */
-	__enter_hibernate_in_last_block();
-#endif
-}
-
-#if defined(CONFIG_HIBERNATE_PSL)
-static void report_psl_wake_source(void)
-{
-	if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE))
-		return;
-
-	CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf);
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT);
-#endif
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-#ifdef CONFIG_WORKAROUND_FLASH_DOWNLOAD_API
-#ifdef CONFIG_EXTERNAL_STORAGE
-/* Sysjump utilities in low power ram for npcx9 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	ASSERT(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
-#endif /* CONFIG_EXTERNAL_STORAGE */
-#endif
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
deleted file mode 120000
index 48088614a0..0000000000
--- a/chip/npcx/system-npcx9.c
+++ /dev/null
@@ -1 +0,0 @@
-system-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
deleted file mode 100644
index ac7056330f..0000000000
--- a/chip/npcx/system.c
+++ /dev/null
@@ -1,1437 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : NPCX hardware specific implementation */
-
-#include "clock.h"
-#include "clock_chip.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer_chip.h"
-#include "lct_chip.h"
-#include "registers.h"
-#include "rom_chip.h"
-#include "sib_chip.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Delay after writing TTC for value to latch */
-#define MTC_TTC_LOAD_DELAY_US 250
-#define MTC_ALARM_MASK     (BIT(25) - 1)
-#define MTC_WUI_GROUP      MIWU_GROUP_4
-#define MTC_WUI_MASK       MASK_PIN7
-
-/* ROM address of chip revision */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-#define CHIP_REV_ADDR        0x0000FFFC
-#define CHIP_REV_STR_SIZE    12
-#else
-#define CHIP_REV_ADDR        0x00007FFC
-#define CHIP_REV_STR_SIZE    6
-#endif
-
-/*  Legacy SuperI/O Configuration D register offset */
-#define SIOCFD_REG_OFFSET    0x2D
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#if defined(NPCX_LCT_SUPPORT)
-/* A flag for waking up from hibernate mode by RTC overflow event */
-static int is_rtc_overflow_event;
-#endif
-
-/*****************************************************************************/
-/* Internal functions */
-
-void system_watchdog_reset(void)
-{
-	/* Unlock & stop watchdog registers */
-	watchdog_stop_and_unlock();
-
-	/* Reset TWCFG */
-	NPCX_TWCFG = 0;
-	/* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-
-	/* Clear watchdog reset status initially*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-
-	/* Keep prescaler ratio timer0 clock to 1:1 */
-	NPCX_TWCP = 0x00;
-
-	/* Set internal counter and prescaler */
-	NPCX_TWDT0 = 0x00;
-	NPCX_WDCNT = 0x01;
-
-	/* Disable interrupt */
-	interrupt_disable();
-	/* Reload and restart Timer 0*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-	/* Enable interrupt */
-	interrupt_enable();
-}
-
-/* Return true if index is stored as a single byte in bbram */
-static int bbram_is_byte_access(enum bbram_data_index index)
-{
-	return index == BBRM_DATA_INDEX_PD0 ||
-	       index == BBRM_DATA_INDEX_PD1 ||
-	       index == BBRM_DATA_INDEX_PD2 ||
-	       index == BBRM_DATA_INDEX_PANIC_FLAGS;
-}
-
-/* Check and clear BBRAM status on any reset */
-void system_check_bbram_on_reset(void)
-{
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
-		/*
-		 * If the reset cause is not power-on reset and VBAT has ever
-		 * dropped, print a warning message.
-		 */
-		if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) ||
-			IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
-			CPRINTF("VBAT drop!\n");
-
-		/*
-		 * npcx5/npcx7m6g/npcx7m6f:
-		 *   Clear IBBR bit
-		 * npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc:
-		 *   Clear IBBR/VSBY_STS/VCC1_STS bit
-		 */
-		NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK;
-	}
-}
-
-/* Check index is within valid BBRAM range and IBBR is not set */
-static int bbram_valid(enum bbram_data_index index, int bytes)
-{
-	/* Check index */
-	if (index < 0 || index + bytes > NPCX_BBRAM_SIZE)
-		return 0;
-
-	/* Check BBRAM is valid */
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
-		NPCX_BKUP_STS = BIT(NPCX_BKUP_STS_IBBR);
-		panic_printf("IBBR set: BBRAM corrupted!\n");
-		return 0;
-	}
-	return 1;
-}
-
-/**
- * Read battery-backed ram (BBRAM) at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-static uint32_t bbram_data_read(enum bbram_data_index index)
-{
-	uint32_t value = 0;
-	int bytes = bbram_is_byte_access(index) ? 1 : 4;
-
-	if (!bbram_valid(index, bytes))
-		return 0;
-
-	/* Read BBRAM */
-	if (bytes == 4) {
-		value += NPCX_BBRAM(index + 3);
-		value = value << 8;
-		value += NPCX_BBRAM(index + 2);
-		value = value << 8;
-		value += NPCX_BBRAM(index + 1);
-		value = value << 8;
-	}
-	value += NPCX_BBRAM(index);
-
-	return value;
-}
-
-/**
- * Write battery-backed ram (BBRAM) at specified index.
- *
- * @return nonzero if error.
- */
-static int bbram_data_write(enum bbram_data_index index, uint32_t value)
-{
-	int bytes = bbram_is_byte_access(index) ? 1 : 4;
-
-	if (!bbram_valid(index, bytes))
-		return EC_ERROR_INVAL;
-
-	/* Write BBRAM */
-	NPCX_BBRAM(index) = value & 0xFF;
-	if (bytes == 4) {
-		NPCX_BBRAM(index + 1) = (value >> 8)  & 0xFF;
-		NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF;
-		NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF;
-	}
-
-	/* Wait for write-complete */
-	return EC_SUCCESS;
-}
-
-/* Map idx to a returned BBRM_DATA_INDEX_*, or return -1 on invalid idx */
-static int bbram_idx_lookup(enum system_bbram_idx idx)
-{
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BBRM_DATA_INDEX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BBRM_DATA_INDEX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BBRM_DATA_INDEX_PD2;
-	if (idx == SYSTEM_BBRAM_IDX_TRY_SLOT)
-		return BBRM_DATA_INDEX_TRY_SLOT;
-	return -1;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int bbram_idx = bbram_idx_lookup(idx);
-
-	if (bbram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	*value = bbram_data_read(bbram_idx);
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	int bbram_idx = bbram_idx_lookup(idx);
-
-	if (bbram_idx < 0)
-		return EC_ERROR_INVAL;
-
-	return bbram_data_write(bbram_idx, value);
-}
-
-/* MTC functions */
-uint32_t system_get_rtc_sec(void)
-{
-	/* Get MTC counter unit:seconds */
-	uint32_t sec = NPCX_TTC;
-	return sec;
-}
-
-void system_set_rtc(uint32_t seconds)
-{
-	/*
-	 * Set MTC counter unit:seconds, write twice to ensure values
-	 * latch to NVMem.
-	 */
-	NPCX_TTC = seconds;
-	udelay(MTC_TTC_LOAD_DELAY_US);
-	NPCX_TTC = seconds;
-	udelay(MTC_TTC_LOAD_DELAY_US);
-}
-
-#ifdef CONFIG_CHIP_PANIC_BACKUP
-/*
- * Following information from panic data is stored in BBRAM:
- *
- * index     |       data
- * ==========|=============
- *   36      |       CFSR
- *   40      |       HFSR
- *   44      |       BFAR
- *   48      |      LREG1
- *   52      |      LREG3
- *   56      |      LREG4
- *   60      |     reserved
- *
- * Above registers are chosen to be saved in case of panic because:
- * 1. CFSR, HFSR and BFAR seem to provide more information about the fault.
- * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of
- * software panic.
- */
-#define BKUP_CFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
-#define BKUP_HFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 4)
-#define BKUP_BFAR		(BBRM_DATA_INDEX_PANIC_BKUP + 8)
-#define BKUP_LREG1		(BBRM_DATA_INDEX_PANIC_BKUP + 12)
-#define BKUP_LREG3		(BBRM_DATA_INDEX_PANIC_BKUP + 16)
-#define BKUP_LREG4		(BBRM_DATA_INDEX_PANIC_BKUP + 20)
-
-#define BKUP_PANIC_DATA_VALID	BIT(0)
-
-void chip_panic_data_backup(void)
-{
-	struct panic_data *d = panic_get_data();
-
-	if (!d)
-		return;
-
-	bbram_data_write(BKUP_CFSR, d->cm.cfsr);
-	bbram_data_write(BKUP_HFSR, d->cm.hfsr);
-	bbram_data_write(BKUP_BFAR, d->cm.dfsr);
-	bbram_data_write(BKUP_LREG1, d->cm.regs[1]);
-	bbram_data_write(BKUP_LREG3, d->cm.regs[3]);
-	bbram_data_write(BKUP_LREG4, d->cm.regs[4]);
-	bbram_data_write(BBRM_DATA_INDEX_PANIC_FLAGS, BKUP_PANIC_DATA_VALID);
-}
-
-static void chip_panic_data_restore(void)
-{
-	struct panic_data *d;
-
-	/* Ensure BBRAM is valid. */
-	if (!bbram_valid(BKUP_CFSR, 4))
-		return;
-
-	/* Ensure Panic data in BBRAM is valid. */
-	if (!(bbram_data_read(BBRM_DATA_INDEX_PANIC_FLAGS) &
-	      BKUP_PANIC_DATA_VALID))
-		return;
-
-	d = get_panic_data_write();
-
-	memset(d, 0, CONFIG_PANIC_DATA_SIZE);
-	d->magic = PANIC_DATA_MAGIC;
-	d->struct_size = CONFIG_PANIC_DATA_SIZE;
-	d->struct_version = 2;
-	d->arch = PANIC_ARCH_CORTEX_M;
-
-	d->cm.cfsr = bbram_data_read(BKUP_CFSR);
-	d->cm.hfsr = bbram_data_read(BKUP_HFSR);
-	d->cm.dfsr = bbram_data_read(BKUP_BFAR);
-
-	d->cm.regs[1] = bbram_data_read(BKUP_LREG1);
-	d->cm.regs[3] = bbram_data_read(BKUP_LREG3);
-	d->cm.regs[4] = bbram_data_read(BKUP_LREG4);
-
-	/* Reset panic data in BBRAM. */
-	bbram_data_write(BBRM_DATA_INDEX_PANIC_FLAGS, 0);
-}
-#endif /* CONFIG_CHIP_PANIC_BACKUP */
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	bbram_data_write(BBRM_DATA_INDEX_SAVED_RESET_FLAGS, flags);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return bbram_data_read(BBRM_DATA_INDEX_SAVED_RESET_FLAGS);
-}
-
-static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags)
-{
-	/* Hibernate via PSL */
-	if (hib_wake_flags & HIBERNATE_WAKE_PSL) {
-#ifdef NPCX_LCT_SUPPORT
-		if (npcx_lct_is_event_set()) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-			/* Is RTC overflow event? */
-			if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) ==
-				NPCX_LCT_MAX) {
-				/*
-				 * Mark it as RTC overflow event and handle it
-				 * in hook init function later for logging info.
-				 */
-				is_rtc_overflow_event = 1;
-			}
-			npcx_lct_clear_event();
-			return;
-		}
-#endif
-		*flags |= EC_RESET_FLAG_WAKE_PIN |
-				  EC_RESET_FLAG_HIBERNATE;
-	} else { /* Hibernate via non-PSL */
-#ifdef NPCX_LCT_SUPPORT
-		if (hib_wake_flags & HIBERNATE_WAKE_LCT) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-			return;
-		}
-#endif
-		if (hib_wake_flags & HIBERNATE_WAKE_PIN) {
-			*flags |= EC_RESET_FLAG_WAKE_PIN |
-					  EC_RESET_FLAG_HIBERNATE;
-		} else if (hib_wake_flags & HIBERNATE_WAKE_MTC) {
-			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
-		}
-	}
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t hib_wake_flags = bbram_data_read(BBRM_DATA_INDEX_WAKE);
-	uint32_t chip_flags = chip_read_reset_flags();
-	uint32_t flags = chip_flags;
-
-	/* Clear saved reset flags in bbram */
-#ifdef CONFIG_POWER_BUTTON_INIT_IDLE
-	/*
-	 * We're not sure whether we're booting or not. AP_IDLE will be cleared
-	 * on S5->S3 transition.
-	 */
-	chip_flags &= EC_RESET_FLAG_AP_IDLE;
-#else
-	chip_flags = 0;
-#endif
-	/* Clear saved hibernate wake flag in bbram , too */
-	bbram_data_write(BBRM_DATA_INDEX_WAKE, 0);
-
-	chip_set_hib_flag(&flags, hib_wake_flags);
-
-	/* Use scratch bit to check power on reset or VCC1_RST reset */
-	if (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) {
-#ifdef CONFIG_BOARD_FORCE_RESET_PIN
-		/* Treat all resets as RESET_PIN */
-		flags |= EC_RESET_FLAG_RESET_PIN;
-#else
-		/* Check for VCC1 reset */
-		int reset = IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS);
-
-		/*
-		 * If configured, check the saved flags to see whether
-		 * the previous restart was a power-on, in which case
-		 * treat this restart as a power-on as well.
-		 * This is to workaround the fact that the H1 will
-		 * reset the EC at power up.
-		 */
-		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON)) {
-			/*
-			 * Reset pin restart rather than power-on, so check
-			 * for any flag set from a previous power-on.
-			 */
-			if (reset) {
-				if (flags & EC_RESET_FLAG_INITIAL_PWR)
-					/*
-					 * The previous restart was a power-on
-					 * so treat this restart as that, and
-					 * clear the flag so later code will
-					 * not wait for the second reset.
-					 */
-					flags =
-					  (flags & ~EC_RESET_FLAG_INITIAL_PWR)
-					   | EC_RESET_FLAG_POWER_ON;
-				else
-					/*
-					 * No previous power-on flag,
-					 * so this is a subsequent restart
-					 * i.e any restarts after the
-					 * second restart caused by the H1.
-					 */
-					flags |= EC_RESET_FLAG_RESET_PIN;
-			} else {
-				flags |= EC_RESET_FLAG_POWER_ON;
-
-				/*
-				 * Power-on restart, so set a flag and save it
-				 * for the next imminent reset. Later code
-				 * will check for this flag and wait for the
-				 * second reset. Waking from PSL hibernate is
-				 * power-on for EC but not for H1, so do not
-				 * wait for the second reset.
-				 */
-				if (!(flags & EC_RESET_FLAG_HIBERNATE)) {
-					flags |= EC_RESET_FLAG_INITIAL_PWR;
-					chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
-				}
-			}
-		} else
-			/*
-			 * No second reset after power-on, so
-			 * set the flags according to the restart reason.
-			 */
-			flags |= reset ? EC_RESET_FLAG_RESET_PIN
-				       : EC_RESET_FLAG_POWER_ON;
-#endif
-	}
-	chip_save_reset_flags(chip_flags);
-
-	/*
-	 * Set scratch bit to distinguish VCC1RST# is asserted again
-	 * or not. This bit will be clear automatically when VCC1RST#
-	 * is asserted or power-on reset occurs
-	 */
-	SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH);
-
-	/* Software debugger reset */
-	if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS)) {
-		flags |= EC_RESET_FLAG_SOFT;
-		/* Clear debugger reset status initially*/
-		SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS);
-	}
-
-	/* Watchdog Reset */
-	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS)) {
-		/*
-		 * Don't set EC_RESET_FLAG_WATCHDOG flag if watchdog is issued
-		 * by system_reset or hibernate in order to distinguish reset
-		 * cause is panic reason or not.
-		 */
-		if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
-				EC_RESET_FLAG_HIBERNATE)))
-			flags |= EC_RESET_FLAG_WATCHDOG;
-
-		/* Clear watchdog reset status initially*/
-		SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-	}
-
-	system_set_reset_flags(flags);
-}
-
-/**
- * Chip-level function to set GPIOs and wake-up inputs for hibernate.
- */
-#ifdef CONFIG_SUPPORT_CHIP_HIBERNATION
-static void system_set_gpios_and_wakeup_inputs_hibernate(void)
-{
-	int table, i;
-
-	/* Disable all MIWU inputs before entering hibernate */
-	for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) {
-		for (i = 0 ; i < 8 ; i++) {
-			/* Disable all wake-ups */
-			NPCX_WKEN(table, i)  = 0x00;
-			/* Clear all pending bits of wake-ups */
-			NPCX_WKPCL(table, i) = 0xFF;
-			/*
-			 * Disable all inputs of wake-ups to prevent leakage
-			 * caused by input floating.
-			 */
-			NPCX_WKINEN(table, i) = 0x00;
-		}
-	}
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	/* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */
-	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6)  = 0x00;
-	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF;
-	NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
-#endif
-
-	/* Enable wake-up inputs of hibernate_wake_pins array */
-	for (i = 0; i < hibernate_wake_pins_used; i++) {
-		gpio_reset(hibernate_wake_pins[i]);
-		/* Re-enable interrupt for wake-up inputs */
-		gpio_enable_interrupt(hibernate_wake_pins[i]);
-#if defined(CONFIG_HIBERNATE_PSL)
-		/* Config PSL pins setting for wake-up inputs */
-		if (!system_config_psl_mode(hibernate_wake_pins[i]))
-			ccprintf("Invalid PSL setting in wake-up pin %d\n", i);
-#endif
-	}
-}
-
-#ifdef NPCX_LCT_SUPPORT
-static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	/* The min resolution of LCT is 1 seconds */
-	if ((seconds == 0) && (microseconds != 0))
-		seconds = 1;
-
-	npcx_lct_enable(0);
-	npcx_lct_sel_power_src(NPCX_LCT_PWR_SRC_VSBY);
-#ifdef CONFIG_HIBERNATE_PSL
-	/* Enable LCT event to PSL */
-	npcx_lct_config(seconds, 1, 0);
-	/* save the start time of LCT */
-	if (IS_ENABLED(CONFIG_HOSTCMD_RTC) || IS_ENABLED(CONFIG_CMD_RTC))
-		bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, seconds);
-#else
-	/* Enable LCT event interrupt and MIWU */
-	npcx_lct_config(seconds, 0, 1);
-	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
-	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
-#endif
-	npcx_lct_enable(1);
-}
-#endif
-
-/**
- * hibernate function for npcx ec.
- *
- * @param seconds      Number of seconds to sleep before LCT alarm
- * @param microseconds Number of microseconds to sleep before LCT alarm
- */
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-
-	/* Disable ADC */
-	NPCX_ADCCNF = 0;
-	usleep(1000);
-
-#ifdef NPCX_LCT_SUPPORT
-	/*
-	 * This function must be called before the ITIM (system tick)
-	 * is disabled because it calls udelay inside this function
-	 */
-	npcx_lct_enable_clk(1);
-#endif
-
-	/* Set SPI pins to be in Tri-State */
-	SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-
-	/* Disable instant wake up mode for better power consumption */
-	CLEAR_BIT(NPCX_ENIDL_CTL, NPCX_ENIDL_CTL_LP_WK_CTL);
-
-	/* Disable interrupt */
-	interrupt_disable();
-
-	/* Unlock & stop watchdog */
-	watchdog_stop_and_unlock();
-
-	/* ITIM event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
-	/* ITIM time module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_SYSTEM_NO), NPCX_ITCTS_ITEN);
-	/* ITIM watchdog warn module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-
-	/* Initialize watchdog */
-	NPCX_TWCFG = 0; /* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-	NPCX_TWCP = 0x00; /* Keep prescaler ratio timer0 clock to 1:1 */
-	NPCX_TWDT0 = 0x00; /* Set internal counter and prescaler */
-
-	/* Disable interrupt */
-	interrupt_disable();
-
-	/*
-	 * Set gpios and wake-up input for better power consumption before
-	 * entering hibernate.
-	 */
-	system_set_gpios_and_wakeup_inputs_hibernate();
-
-	/*
-	 * Give the board a chance to do any late stage hibernation work.  This
-	 * is likely going to configure GPIOs for hibernation.  On some boards,
-	 * it's possible that this may not return at all.  On those boards,
-	 * power to the EC is likely being turn off entirely.
-	 */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
-		task_clear_pending_irq(i);
-
-	/* Set the timer interrupt for wake up.  */
-#ifdef NPCX_LCT_SUPPORT
-	if (seconds || microseconds) {
-		system_set_lct_alarm(seconds, microseconds);
-	} else if (IS_ENABLED(CONFIG_HIBERNATE_PSL_COMPENSATE_RTC)) {
-		system_set_lct_alarm(NPCX_LCT_MAX, 0);
-	}
-#else
-	if (seconds || microseconds)
-		system_set_rtc_alarm(seconds, microseconds);
-#endif
-
-	/* execute hibernate func depend on chip series */
-	__hibernate_npcx_series();
-}
-
-#ifdef CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
-#ifndef NPCX_LCT_SUPPORT
-#error "Do not enable CONFIG_HIBERNATE_PSL_COMPENSATE_RTC if npcx ec doesn't \
-support LCT!"
-#endif
-/*
- * The function uses the LCT counter value to compensate for RTC after hibernate
- * wake-up. Because system_set_rtc() will invoke udelay(), the function should
- * execute after timer_init(). The function also should execute before
- * npcx_lct_init() which will clear all LCT register.
- */
-void system_compensate_rtc(void)
-{
-	uint32_t rtc_time, ltc_start_time;
-
-	ltc_start_time = bbram_data_read(BBRM_DATA_INDEX_LCT_TIME);
-	if (ltc_start_time == 0)
-		return;
-
-	rtc_time = system_get_rtc_sec();
-	rtc_time += ltc_start_time - npcx_lct_get_time();
-	system_set_rtc(rtc_time);
-	/* Clear BBRAM data to avoid compensating again. */
-	bbram_data_write(BBRM_DATA_INDEX_LCT_TIME, 0);
-}
-#endif
-#endif /* CONFIG_SUPPORT_CHIP_HIBERNATION */
-
-static char system_to_hex(uint8_t val)
-{
-	uint8_t x = val & 0x0F;
-
-	if (x <= 9)
-		return '0' + x;
-	return 'a' + x - 10;
-}
-
-/*****************************************************************************/
-/* IC specific low-level driver */
-
-/*
- * Microseconds will be ignored.  The WTC register only
- * stores wakeup time in seconds.
- * Set seconds = 0 to disable the alarm
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	uint32_t cur_secs, alarm_secs;
-
-	if (seconds == EC_RTC_ALARM_CLEAR && !microseconds) {
-		CLEAR_BIT(NPCX_WTC, NPCX_WTC_WIE);
-		SET_BIT(NPCX_WTC, NPCX_WTC_PTO);
-
-		return;
-	}
-
-	/* Get current clock */
-	cur_secs = NPCX_TTC;
-
-	/* If alarm clock is not sequential or not in range */
-	alarm_secs = cur_secs + seconds;
-	alarm_secs = alarm_secs & MTC_ALARM_MASK;
-
-	/*
-	 * We should set new alarm (first 25 bits of clock value) first before
-	 * clearing PTO in case issue rtc interrupt immediately.
-	 */
-	NPCX_WTC = alarm_secs;
-
-	/* Reset alarm first */
-	system_reset_rtc_alarm();
-
-	/* Enable interrupt mode alarm */
-	SET_BIT(NPCX_WTC, NPCX_WTC_WIE);
-
-	/* Enable MTC interrupt */
-	task_enable_irq(NPCX_IRQ_MTC);
-
-	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP)  |= MTC_WUI_MASK;
-	NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP)   |= MTC_WUI_MASK;
-}
-
-void system_reset_rtc_alarm(void)
-{
-	/*
-	 * Clear interrupt & Disable alarm interrupt
-	 * Update alarm value to zero
-	 */
-	CLEAR_BIT(NPCX_WTC, NPCX_WTC_WIE);
-	SET_BIT(NPCX_WTC, NPCX_WTC_PTO);
-
-	/* Disable MTC interrupt */
-	task_disable_irq(NPCX_IRQ_MTC);
-}
-
-/*
- * Return the seconds remaining before the RTC alarm goes off.
- * Returns 0 if alarm is not set.
- */
-uint32_t system_get_rtc_alarm(void)
-{
-	/*
-	 * Return 0:
-	 * 1. If alarm is not set to go off, OR
-	 * 2. If alarm is set and has already gone off
-	 */
-	if (!IS_BIT_SET(NPCX_WTC, NPCX_WTC_WIE) ||
-	    IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) {
-		return 0;
-	}
-	/* Get seconds before alarm goes off */
-	return (NPCX_WTC - NPCX_TTC) & MTC_ALARM_MASK;
-}
-
-/**
- * Enable hibernate interrupt
- */
-void system_enable_hib_interrupt(void)
-{
-	task_enable_irq(NPCX_IRQ_MTC);
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-#ifdef CONFIG_SUPPORT_CHIP_HIBERNATION
-	/* Add additional hibernate operations here */
-	__enter_hibernate(seconds, microseconds);
-#endif
-}
-
-#ifndef CONFIG_ENABLE_JTAG_SELECTION
-static void system_disable_host_sel_jtag(void)
-{
-	int data;
-
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-	/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
-	data = sib_read_reg(SIO_OFFSET, SIOCFD_REG_OFFSET);
-	data &= ~0x80;
-	sib_write_reg(SIO_OFFSET, SIOCFD_REG_OFFSET, data);
-	/* Disable Core-to-Host Modules Access */
-	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-}
-#endif
-
-void chip_pre_init(void)
-{
-	/* Setting for fixing JTAG issue */
-	NPCX_DBGCTRL = 0x04;
-	/* Enable automatic freeze mode */
-	CLEAR_BIT(NPCX_DBGFRZEN3, NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
-
-	/*
-	 * Enable JTAG functionality by SW without pulling down strap-pin
-	 * nJEN0 or nJEN1 during ec POWERON or VCCRST reset occurs.
-	 * Please notice it will change pinmux to JTAG directly.
-	 */
-#ifdef NPCX_ENABLE_JTAG
-#if NPCX_JTAG_MODULE2
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN1_EN);
-#else
-	CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN0_EN);
-#endif
-#endif
-
-#ifndef CONFIG_ENABLE_JTAG_SELECTION
-	/*
-	 * (b/129908668)
-	 * This is the workaround to disable the JTAG0 which is enabled
-	 * accidentally by a special key combination.
-	 */
-#if NPCX_FAMILY_VERSION < NPCX_FAMILY_NPCX9
-	if (!IS_BIT_SET(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN)) {
-		/* Set DEVALT5.nJEN0_EN to disable JTAG0 */
-		SET_BIT(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN);
-		system_disable_host_sel_jtag();
-	}
-#else
-	if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) ==
-		      NPCX_JEN_CTL1_JEN_EN_ENA) {
-		SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD,
-			  NPCX_JEN_CTL1_JEN_EN_DIS);
-		system_disable_host_sel_jtag();
-	}
-#endif
-#endif
-}
-
-void system_pre_init(void)
-{
-	uint8_t pwdwn6;
-
-	/*
-	 * Add additional initialization here
-	 * EC should be initialized in Booter
-	 */
-
-	/* Power-down the modules we don't need */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xF9; /* Skip SDP_PD FIU_PD */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_2) = 0xFF;
-#if defined(CHIP_FAMILY_NPCX5)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; /* Skip GDMA */
-#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; /* Skip GDMA */
-#endif
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8;
-
-	pwdwn6 = 0x70 |
-#if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-		/*
-		 * Don't set PD of ITIM6 for NPCX9 and later chips because
-		 * they use it as the system timer.
-		 */
-		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
-#endif
-		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_HOSTCMD_ESPI)
-	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
-#endif
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
-
-#if defined(CHIP_FAMILY_NPCX7)
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7;
-#else
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
-#endif
-#endif
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xFF;
-#endif
-
-	/* Following modules can be powered down automatically in npcx7 */
-#if defined(CHIP_FAMILY_NPCX5)
-	/* Power down the modules of npcx5 used internally */
-	NPCX_INTERNAL_CTRL1 = 0x03;
-	NPCX_INTERNAL_CTRL2 = 0x03;
-	NPCX_INTERNAL_CTRL3 = 0x03;
-
-	/* Enable low-power regulator */
-	CLEAR_BIT(NPCX_LFCGCALCNT, NPCX_LFCGCALCNT_LPREG_CTL_EN);
-	SET_BIT(NPCX_LFCGCALCNT, NPCX_LFCGCALCNT_LPREG_CTL_EN);
-#endif
-
-	/*
-	 * Configure LPRAM in the MPU as a regular memory
-	 * and DATA RAM to prevent code execution
-	 */
-	system_mpu_config();
-
-	/*
-	 * Change FMUL_WIN_DLY from 0x8A to 0x81 for better WoV
-	 * audio quality.
-	 */
-#ifdef CHIP_FAMILY_NPCX7
-	NPCX_FMUL_WIN_DLY = 0x81;
-#endif
-
-#ifdef CONFIG_CHIP_PANIC_BACKUP
-	chip_panic_data_restore();
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	if (IS_ENABLED(CONFIG_HIBERNATE_PSL)) {
-		uint8_t opt_flag = CONFIG_HIBERNATE_PSL_OUT_FLAGS;
-
-		/* PSL Glitch Protection */
-		SET_BIT(NPCX_GLUE_PSL_MCTL2, NPCX_GLUE_PSL_MCTL2_PSL_GP_EN);
-
-		/*
-		 * TODO: Remove this when NPCX9 A2 chip is available because A2
-		 * chip will enable VCC1_RST to PSL wakeup source and lock it in
-		 * the booter.
-		 */
-		if (IS_ENABLED(CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP)) {
-			/*
-			 * Enable VCC1_RST as the wake-up source from
-			 * hibernation.
-			 */
-			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
-			/* Disable VCC_RST Pull-Up */
-			SET_BIT(NPCX_DEVALT(ALT_GROUP_G),
-					NPCX_DEVALTG_VCC1_RST_PUD);
-			/*
-			 * Lock this bit itself and VCC1_RST_PSL in the
-			 * PSL_MCTL1 register to read-only.
-			 */
-			SET_BIT(NPCX_GLUE_PSL_MCTL2,
-					NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
-		}
-
-		/* Don't set PSL_OUT to open-drain if it is the level mode */
-		ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) ||
-			 !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
-
-		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)
-			SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN);
-		else
-			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_OD_EN);
-
-		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE)
-			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
-		else
-			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
-	}
-#endif
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/*  Get flags to be saved in BBRAM */
-	system_encode_save_flags(flags, &save_flags);
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	/* Ask the watchdog to trigger a hard reboot */
-	system_watchdog_reset();
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-/**
- * Return the chip vendor/name/revision string.
- */
-const char *system_get_chip_vendor(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-
-	/* Read Vendor ID in core register */
-	uint8_t fam_id = NPCX_SID_CR;
-	switch (fam_id) {
-	case 0x20:
-		return "Nuvoton";
-	default:
-		*p       = system_to_hex(fam_id >> 4);
-		*(p + 1) = system_to_hex(fam_id);
-		*(p + 2) = '\0';
-		return str;
-	}
-}
-
-const char *system_get_chip_name(void)
-{
-	static char str[15] = "Unknown-";
-	char *p = str + 8;
-
-	/* Read Chip ID in core register */
-	uint8_t chip_id = NPCX_DEVICE_ID_CR;
-
-	switch (chip_id) {
-#if defined(CHIP_FAMILY_NPCX5)
-	case NPCX585G_CHIP_ID:
-		return "NPCX585G";
-	case NPCX575G_CHIP_ID:
-		return "NPCX575G";
-	case NPCX586G_CHIP_ID:
-		return "NPCX586G";
-	case NPCX576G_CHIP_ID:
-		return "NPCX576G";
-#elif defined(CHIP_FAMILY_NPCX7)
-	case NPCX787G_CHIP_ID:
-		return "NPCX787G";
-	case NPCX797F_C_CHIP_ID:
-		return "NPCX797F";
-	case NPCX796F_A_B_CHIP_ID:
-	case NPCX796F_C_CHIP_ID:
-		return "NPCX796F";
-	case NPCX797W_B_CHIP_ID:
-	case NPCX797W_C_CHIP_ID:
-		return "NPCX797W";
-#elif defined(CHIP_FAMILY_NPCX9)
-	case NPCX996F_CHIP_ID:
-		return "NPCX996F";
-	case NPCX993F_CHIP_ID:
-		return "NPCX993F";
-#endif
-	default:
-		*p       = system_to_hex(chip_id >> 4);
-		*(p + 1) = system_to_hex(chip_id);
-		*(p + 2) = '\0';
-		return str;
-	}
-}
-
-const char *system_get_chip_revision(void)
-{
-	static char rev[CHIP_REV_STR_SIZE];
-	char *p = rev;
-	/* Read chip generation from SRID_CR */
-	uint8_t chip_gen = NPCX_SRID_CR;
-	/* Read ROM data for chip revision directly */
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	uint32_t rev_num = *((uint32_t *)CHIP_REV_ADDR);
-#else
-	uint8_t rev_num = *((uint8_t *)CHIP_REV_ADDR);
-#endif
-
-#ifdef CHIP_FAMILY_NPCX7
-	uint8_t chip_id = NPCX_DEVICE_ID_CR;
-#endif
-	int s;
-
-	switch (chip_gen) {
-#if defined(CHIP_FAMILY_NPCX5)
-	case 0x05:
-		*p++ = 'A';
-		break;
-#elif defined(CHIP_FAMILY_NPCX7)
-	case 0x06:
-		*p++ = 'A';
-		break;
-	case 0x07:
-		if (chip_id == NPCX796F_A_B_CHIP_ID ||
-			chip_id == NPCX797W_B_CHIP_ID)
-			*p++ = 'B';
-		else
-			*p++ = 'C';
-		break;
-#elif defined(CHIP_FAMILY_NPCX9)
-	case 0x09:
-		*p++ = 'A';
-		break;
-#endif
-	default:
-		*p++ = system_to_hex(chip_gen >> 4);
-		*p++ = system_to_hex(chip_gen);
-		break;
-	}
-
-	*p++ = '.';
-	/*
-	 * For npcx5/npcx7, the revision number is 1 byte.
-	 * For NPCX9 and later chips, the revision number is 4 bytes.
-	 */
-	for (s = sizeof(rev_num) - 1; s >= 0; s--) {
-		uint8_t r = rev_num >> (s * 8);
-
-		*p++ = system_to_hex(r >> 4);
-		*p++ = system_to_hex(r);
-	}
-	*p++ = '\0';
-
-	return rev;
-}
-
-/**
- * Set a scratchpad register to the specified value.
- *
- * The scratchpad register must maintain its contents across a
- * software-requested warm reset.
- *
- * @param value		Value to store.
- * @return EC_SUCCESS, or non-zero if error.
- */
-int system_set_scratchpad(uint32_t value)
-{
-	return bbram_data_write(BBRM_DATA_INDEX_SCRATCHPAD, value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = bbram_data_read(BBRM_DATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-int system_is_reboot_warm(void)
-{
-	uint32_t reset_flags;
-
-	/*
-	 * Check reset cause here,
-	 * gpio_pre_init is executed faster than system_pre_init
-	 */
-	check_reset_cause();
-	reset_flags = system_get_reset_flags();
-
-	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
-	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-	    (reset_flags & EC_RESET_FLAG_HARD) ||
-	    (reset_flags & EC_RESET_FLAG_SOFT) ||
-	    (reset_flags & EC_RESET_FLAG_HIBERNATE))
-		return 0;
-	else
-		return 1;
-}
-
-#if defined(CONFIG_HIBERNATE_PSL) && defined(NPCX_LCT_SUPPORT)
-static void system_init_check_rtc_wakeup_event(void)
-{
-	/*
-	 * If platform uses PSL (Power Switch Logic) for hibernating and RTC is
-	 * also supported, determine whether ec is woken up by RTC with overflow
-	 * event (16 weeks). If so, let it go to hibernate mode immediately.
-	 */
-	if (is_rtc_overflow_event){
-		CPRINTS("Hibernate due to RTC overflow event");
-		system_hibernate(0, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, system_init_check_rtc_wakeup_event,
-	     HOOK_PRIO_DEFAULT - 1);
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec = system_get_rtc_sec();
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		uint32_t t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-	system_enable_hib_interrupt();
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-	}
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-		"[seconds [microseconds]]",
-		"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc_alarm(p->time, 0);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_alarm();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
-
-#endif /* CONFIG_HOSTCMD_RTC */
-#ifdef CONFIG_EXTERNAL_STORAGE
-void system_jump_to_booter(void)
-{
-	enum API_RETURN_STATUS_T status __attribute__((unused));
-	static uint32_t flash_offset;
-	static uint32_t flash_used;
-	static uint32_t addr_entry;
-
-	/*
-	 * Get memory offset and size for RO/RW regions.
-	 * Both of them need 16-bytes alignment since GDMA burst mode.
-	 */
-	switch (system_get_shrspi_image_copy()) {
-	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#endif
-	case EC_IMAGE_RO:
-	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
-		flash_used = CONFIG_RO_SIZE;
-		break;
-	}
-
-	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
-
-	/*
-	 * Speed up FW download time by increasing clock freq of EC. It will
-	 * restore to default in clock_init() later.
-	 */
-	clock_turbo();
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-	/* Bypass for GMDA issue of ROM api utilities */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
-	);
-#else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
-	);
-#endif
-}
-
-uint32_t system_get_lfw_address()
-{
-	/*
-	 * In A3 version, we don't use little FW anymore
-	 * We provide the alternative function in ROM
-	 */
-	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
-	return jump_addr;
-}
-
-/*
- * Set and clear image copy flags in MDC register.
- *
- * NPCX_FWCTRL_RO_REGION: 1 - RO, 0 - RW
- * NPCX_FWCTRL_FW_SLOT: 1 - SLOT_A, 0 - SLOT_B
- */
-void system_set_image_copy(enum ec_image copy)
-{
-	switch (copy) {
-	case EC_IMAGE_RW:
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-#endif
-	default:
-		CPRINTS("Invalid copy (%d) is requested as a jump destination. "
-			"Change it to %d.", copy, EC_IMAGE_RO);
-		/* Fall through to EC_IMAGE_RO */
-	case EC_IMAGE_RO:
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT);
-		break;
-	}
-}
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION)) {
-		/* RO image */
-#ifdef CHIP_HAS_RO_B
-		if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT))
-			return EC_IMAGE_RO_B;
-#endif
-		return EC_IMAGE_RO;
-	} else {
-#ifdef CONFIG_RW_B
-		/* RW image */
-		if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT))
-			/* Slot A */
-			return EC_IMAGE_RW_B;
-#endif
-		return EC_IMAGE_RW;
-	}
-}
-
-#endif
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
deleted file mode 100644
index e3cc2a8865..0000000000
--- a/chip/npcx/system_chip.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-#ifndef __CROS_EC_SYSTEM_CHIP_H
-#define __CROS_EC_SYSTEM_CHIP_H
-
-/* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC        BIT(0)  /* MTC alarm */
-#define HIBERNATE_WAKE_PIN        BIT(1)  /* Wake pin */
-#define HIBERNATE_WAKE_LCT        BIT(2)  /* LCT alarm */
-/*
- * Indicate that EC enters hibernation via PSL. When EC wakes up from
- * hibernation and this flag is set, it will check the related status bit to
- * know the actual wake up source. (From LCT or physical wakeup pins)
- */
-#define HIBERNATE_WAKE_PSL        BIT(3)
-
-/* Indices for battery-backed ram (BBRAM) data position */
-enum bbram_data_index {
-	BBRM_DATA_INDEX_SCRATCHPAD = 0,        /* General-purpose scratchpad */
-	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
-	BBRM_DATA_INDEX_WAKE = 8,	       /* Wake reasons for hibernate */
-	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
-	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
-	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
-	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
-	/* Index 16-31 available for future use */
-	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
-	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of
-						* panic data starting at index
-						* 36.
-						*/
-	BBRM_DATA_INDEX_PANIC_BKUP = 36,       /* Panic data (index 35-63)*/
-	BBRM_DATA_INDEX_LCT_TIME = 64,         /* The start time of LCT(4 bytes)
-						*/
-};
-
-enum psl_pin_t {
-	PSL_IN1,
-	PSL_IN2,
-	PSL_IN3,
-	PSL_IN4,
-	PSL_NONE,
-};
-
-/* Issue a watchdog reset */
-void system_watchdog_reset(void);
-
-/* Stops the watchdog timer and unlocks configuration. */
-void watchdog_stop_and_unlock(void);
-
-/*
- * Configure the specific memory addresses in the the MPU
- * (Memory Protection Unit) for Nuvoton different chip series.
- */
-void system_mpu_config(void);
-
-/* Hibernate function for different Nuvoton chip series. */
-void __hibernate_npcx_series(void);
-
-/* Check and clear BBRAM status on power-on reset */
-void system_check_bbram_on_reset(void);
-
-/* The utilities and variables depend on npcx chip family */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr);
-
-/* Begin address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_start;
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_end;
-
-/* Begin address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_start;
-
-/* End address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_end;
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-/* Configure PSL mode setting for the wake-up pins. */
-int system_config_psl_mode(enum gpio_signal signal);
-
-/* Configure PSL pins and enter PSL mode. */
-void system_enter_psl_mode(void);
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __after_init_end;
-
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-void system_set_psl_gpo(int level);
-#endif
-
-#endif /* __CROS_EC_SYSTEM_CHIP_H */
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
deleted file mode 100644
index efe991ec0b..0000000000
--- a/chip/npcx/uart.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hwtimer_chip.h"
-#include "lpc.h"
-#include "registers.h"
-#include "clock_chip.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "uartn.h"
-#include "util.h"
-
-#define CONSOLE_UART            CONFIG_CONSOLE_UART
-
-#if CONSOLE_UART
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART2
-#else
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART
-#endif
-
-static int init_done;
-
-#ifdef CONFIG_UART_PAD_SWITCH
-
-/* Current pad: 0 for default pad, 1 for alternate. */
-static volatile enum uart_pad pad;
-
-/*
- * When switched to alternate pad, read/write data according to the parameters
- * below.
- */
-static uint8_t *altpad_rx_buf;
-static volatile int altpad_rx_pos;
-static int altpad_rx_len;
-static uint8_t *altpad_tx_buf;
-static volatile int altpad_tx_pos;
-static int altpad_tx_len;
-
-/*
- * Time we last received a byte on default UART, we do not allow use of
- * alternate pad for block_alt_timeout_us after that, to make sure input
- * characters are not lost (either interactively, or though servod/FAFT).
- */
-static timestamp_t last_default_pad_rx_time;
-
-static const uint32_t block_alt_timeout_us = 500*MSEC;
-
-#else
-
-/* Default pad is always selected. */
-static const enum uart_pad pad = UART_DEFAULT_PAD;
-
-#endif /* CONFIG_UART_PAD_SWITCH */
-
-#if defined(CHIP_FAMILY_NPCX5)
-/* This routine switches the functionality from UART rx to GPIO */
-void npcx_uart2gpio(void)
-{
-	/* Switch both pads back to GPIO mode. */
-	CLEAR_BIT(NPCX_DEVALT(0x0C), NPCX_DEVALTC_UART_SL2);
-	CLEAR_BIT(NPCX_DEVALT(0x0A), NPCX_DEVALTA_UART_SL1);
-}
-#endif /* CHIP_FAMILY_NPCX5 */
-
-/*
- * This routine switches the functionality from GPIO to UART rx, depending
- * on the global variable "pad". It also deactivates the previous pad.
- *
- * Note that, when switching pad, we first configure the new pad, then switch
- * off the old one, to avoid having no pad selected at a given time, see
- * b/65526215#c26.
- */
-void npcx_gpio2uart(void)
-{
-#ifdef CONFIG_UART_PAD_SWITCH
-	if (pad == UART_ALTERNATE_PAD) {
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN__SL);
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
-#else
-		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
-		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-#endif
-		return;
-	}
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
-#else
-	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
-	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
-#endif
-
-#if !NPCX_UART_MODULE2 && (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7)
-	/*
-	 * UART module 1 belongs to KSO since wake-up functionality in npcx7
-	 * and later chips.
-	 */
-	CLEAR_BIT(NPCX_DEVALT(0x09), NPCX_DEVALT9_NO_KSO09_SL);
-#endif
-}
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-#if defined(CHIP_FAMILY_NPCX5)
-	if (uart_is_enable_wakeup() && pad == UART_DEFAULT_PAD) {
-		/* disable MIWU */
-		uart_enable_wakeup(0);
-		/* Set pin-mask for UART */
-		npcx_gpio2uart();
-		/* enable uart again from MIWU mode */
-		task_enable_irq(NPCX_IRQ_UART);
-	}
-#endif
-
-	uartn_tx_start(CONSOLE_UART);
-}
-
-void uart_tx_stop(void)
-{
-#ifdef NPCX_UART_FIFO_SUPPORT
-	uartn_tx_stop(CONSOLE_UART, 0);
-#else
-	uint8_t sleep_ena;
-
-	sleep_ena = (pad == UART_DEFAULT_PAD) ? 1 : 0;
-	uartn_tx_stop(CONSOLE_UART, sleep_ena);
-#endif
-}
-
-void uart_tx_flush(void)
-{
-	uartn_tx_flush(CONSOLE_UART);
-}
-
-int uart_tx_ready(void)
-{
-	return uartn_tx_ready(CONSOLE_UART);
-}
-
-int uart_tx_in_progress(void)
-{
-	return uartn_tx_in_progress(CONSOLE_UART);
-}
-
-int uart_rx_available(void)
-{
-	int rx_available = uartn_rx_available(CONSOLE_UART);
-
-	if (rx_available && pad == UART_DEFAULT_PAD) {
-#ifdef CONFIG_LOW_POWER_IDLE
-		/*
-		 * Activity seen on UART RX pin while UART was disabled for deep
-		 * sleep. The console won't see that character because the UART
-		 * is disabled, so we need to inform the clock module of UART
-		 * activity ourselves.
-		 */
-		clock_refresh_console_in_use();
-#endif
-#ifdef CONFIG_UART_PAD_SWITCH
-		last_default_pad_rx_time = get_time();
-#endif
-	}
-	return rx_available; /* If RX FIFO is empty return '0'. */
-}
-
-void uart_write_char(char c)
-{
-	uartn_write_char(CONSOLE_UART, c);
-}
-
-int uart_read_char(void)
-{
-	return uartn_read_char(CONSOLE_UART);
-}
-
-/* Interrupt handler for Console UART */
-void uart_ec_interrupt(void)
-{
-#ifdef CONFIG_UART_PAD_SWITCH
-	if (pad == UART_ALTERNATE_PAD) {
-		if (uartn_rx_available(NPCX_UART_PORT0)) {
-			uint8_t c = uartn_read_char(NPCX_UART_PORT0);
-
-			if (altpad_rx_pos < altpad_rx_len)
-				altpad_rx_buf[altpad_rx_pos++] = c;
-		}
-		if (uartn_tx_ready(NPCX_UART_PORT0)) {
-			if (altpad_tx_pos < altpad_tx_len)
-				uartn_write_char(NPCX_UART_PORT0,
-					altpad_tx_buf[altpad_tx_pos++]);
-			else
-				uart_tx_stop();
-		}
-		return;
-	}
-#endif
-#ifdef NPCX_UART_FIFO_SUPPORT
-	if (!uartn_tx_in_progress(CONSOLE_UART)) {
-		if (uart_buffer_empty()) {
-			uartn_enable_tx_complete_int(CONSOLE_UART, 0);
-			enable_sleep(SLEEP_MASK_UART);
-		}
-	}
-#endif
-
-	/* Default pad. */
-	/* Read input FIFO until empty, then fill output FIFO */
-	uart_process_input();
-	uart_process_output();
-}
-#ifdef NPCX_UART_FIFO_SUPPORT
-DECLARE_IRQ(CONSOLE_UART_IRQ, uart_ec_interrupt, 4);
-#else
-DECLARE_IRQ(CONSOLE_UART_IRQ, uart_ec_interrupt, 1);
-#endif
-
-#ifdef CONFIG_UART_PAD_SWITCH
-/*
- * Switch back to default UART pad, without flushing RX/TX buffers: If we are
- * about to panic, we just want to switch immmediately, and we don't care if we
- * output a bit of garbage.
- */
-void uart_reset_default_pad_panic(void)
-{
-	pad = UART_DEFAULT_PAD;
-
-	/* Configure new pad. */
-	npcx_gpio2uart();
-
-	/* Wait for ~2 bytes, to help the receiver resync. */
-	udelay(200);
-}
-
-static void uart_set_pad(enum uart_pad newpad)
-{
-#ifdef NPCX_UART_FIFO_SUPPORT
-	NPCX_UFTCTL(NPCX_UART_PORT0) &= ~0xE0;
-	NPCX_UFRCTL(NPCX_UART_PORT0) &= ~0xE0;
-#else
-	NPCX_UICTRL(NPCX_UART_PORT0) = 0x00;
-#endif
-	task_disable_irq(NPCX_IRQ_UART);
-
-	/* Flush the last byte */
-	uartn_tx_flush(NPCX_UART_PORT0);
-	uart_tx_stop();
-
-	/*
-	 * Allow deep sleep when default pad is selected (sleep is inhibited
-	 * during TX). Disallow deep sleep when alternate pad is selected.
-	 */
-	if (newpad == UART_DEFAULT_PAD)
-		enable_sleep(SLEEP_MASK_UART);
-	else
-		disable_sleep(SLEEP_MASK_UART);
-
-	pad = newpad;
-
-	/* Configure new pad. */
-	npcx_gpio2uart();
-
-	/* Re-enable receive interrupt. */
-	uartn_rx_int_en(NPCX_UART_PORT0);
-
-	/*
-	 * If pad is switched while a byte is being received, the last byte may
-	 * be corrupted, let's wait for ~1 byte (9/115200 = 78 us + margin),
-	 * then flush the FIFO. See b/65526215.
-	 */
-	udelay(100);
-	uartn_clear_rx_fifo(NPCX_UART_PORT0);
-
-	task_enable_irq(NPCX_IRQ_UART);
-}
-
-/* TODO(b:67026316): Remove this and replace with software flow control. */
-void uart_default_pad_rx_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * We received an interrupt on the primary pad, give up on the
-	 * transaction and switch back.
-	 */
-	gpio_disable_interrupt(GPIO_UART_MAIN_RX);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	clock_refresh_console_in_use();
-#endif
-	last_default_pad_rx_time = get_time();
-
-	uart_set_pad(UART_DEFAULT_PAD);
-}
-
-int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
-			    int timeout_us)
-{
-	uint32_t start = __hw_clock_source_read();
-	int ret = 0;
-
-	if ((get_time().val - last_default_pad_rx_time.val)
-			< block_alt_timeout_us)
-		return -EC_ERROR_BUSY;
-
-	cflush();
-
-	altpad_rx_buf = rx;
-	altpad_rx_pos = 0;
-	altpad_rx_len = rx_len;
-	altpad_tx_buf = tx;
-	altpad_tx_pos = 0;
-	altpad_tx_len = tx_len;
-
-	/*
-	 * Turn on additional pull-up during transaction: that prevents the line
-	 * from going low in case the base gets disconnected during the
-	 * transaction. See b/68954760.
-	 */
-	gpio_set_flags(GPIO_EC_COMM_PU, GPIO_OUTPUT | GPIO_HIGH);
-
-	uart_set_pad(UART_ALTERNATE_PAD);
-	gpio_clear_pending_interrupt(GPIO_UART_MAIN_RX);
-	gpio_enable_interrupt(GPIO_UART_MAIN_RX);
-	uartn_tx_start(NPCX_UART_PORT0);
-
-	do {
-		usleep(100);
-
-		/* Pad switched during transaction. */
-		if (pad != UART_ALTERNATE_PAD) {
-			ret = -EC_ERROR_BUSY;
-			goto out;
-		}
-
-		if (altpad_rx_pos == altpad_rx_len &&
-		    altpad_tx_pos == altpad_tx_len)
-			break;
-	} while ((__hw_clock_source_read() - start) < timeout_us);
-
-	gpio_disable_interrupt(GPIO_UART_MAIN_RX);
-	uart_set_pad(UART_DEFAULT_PAD);
-
-	if (altpad_tx_pos == altpad_tx_len)
-		ret = altpad_rx_pos;
-	else
-		ret = -EC_ERROR_TIMEOUT;
-
-out:
-	gpio_set_flags(GPIO_EC_COMM_PU, GPIO_INPUT);
-
-	altpad_rx_len = 0;
-	altpad_rx_pos = 0;
-	altpad_rx_buf = NULL;
-	altpad_tx_len = 0;
-	altpad_tx_pos = 0;
-	altpad_tx_buf = NULL;
-
-	return ret;
-}
-#endif
-void uart_init(void)
-{
-
-	uartn_init(CONSOLE_UART);
-	init_done = 1;
-}
diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c
deleted file mode 100644
index 2269e11e7c..0000000000
--- a/chip/npcx/uartn.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* UART module for Chrome EC */
-
-#include <clock.h>
-#include "common.h"
-#include <gpio.h>
-#include <gpio_chip.h>
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-/* Enable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* True if UART Tx FIFO empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   \
-		(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* Disable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
-/* True if the Tx FIFO is not completely full */
-#define NPCX_UART_TX_IS_READY(n)          \
-		(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
-
-/* Enable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
-/* Disable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_DIS(n)      \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
-/*
- * True if Tx is in progress
- * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register)
- * is not sent)
- */
-#define NPCX_UART_TX_IN_XMIT(n)           \
-		(!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
-
-/*
- * Enable to generate interrupt when there is at least one byte
- * in the receive FIFO
- */
-#define NPCX_UART_RX_INT_EN(n)            \
-		(SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
-/* True if at least one byte is in the receive FIFO */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      \
-		(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
-#else
-/* Enable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      (NPCX_UICTRL(n) |= 0x20)
-/* True if UART Tx buffer empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   (NPCX_UICTRL(n) & 0x20)
-/* Disable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     (NPCX_UICTRL(n) &= ~0x20)
-/* True if 1-byte Tx buffer is empty */
-#define NPCX_UART_TX_IS_READY(n)          (NPCX_UICTRL(n) & 0x01)
-/*
- * True if Tx is in progress
- * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register)
- * is not sent)
- */
-#define NPCX_UART_TX_IN_XMIT(n)           (NPCX_USTAT(n) & 0x40)
- /* Enable to generate interrupt when there is data in the receive buffer */
-#define NPCX_UART_RX_INT_EN(n)            (NPCX_UICTRL(n) = 0x40)
-/* True if there is data in the 1-byte Receive buffer */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      (NPCX_UICTRL(n) & 0x02)
-#endif
-
-struct uart_configs {
-	uint32_t irq;
-	uint32_t clk_en_offset;
-	uint32_t clk_en_msk;
-};
-static const struct uart_configs uart_cfg[] = {
-	{NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK},
-#ifdef NPCX_SECOND_UART
-	{NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK},
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-static const struct npcx_wui uart_wui[] = {
-	WUI(1, NPCX_UART_WK_GROUP, NPCX_UART_WK_BIT),
-#ifdef NPCX_SECOND_UART
-	WUI(0, NPCX_UART2_WK_GROUP, NPCX_UART2_WK_BIT),
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(uart_wui) == UART_MODULE_COUNT);
-
-void uartn_wui_en(uint8_t uart_num)
-{
-	struct npcx_wui wui;
-
-	wui = uart_wui[uart_num];
-	/* Clear pending bit before enable uart wake-up */
-	SET_BIT(NPCX_WKPCL(wui.table, wui.group), wui.bit);
-	/* Enable UART1 wake-up and interrupt request */
-	SET_BIT(NPCX_WKEN(wui.table, wui.group), wui.bit);
-}
-#endif
-
-void uartn_rx_int_en(uint8_t uart_num)
-{
-	NPCX_UART_RX_INT_EN(uart_num);
-}
-
-void uartn_tx_start(uint8_t uart_num)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (NPCX_UART_TX_EMPTY_INT_IS_EN(uart_num))
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-	/*
-	 * For FIFO mode, enable the NXMIP interrupt. This generates an
-	 * interrupt when Tx (both FIFO and shift register) is empty
-	 */
-	NPCX_UART_TX_NXMIP_INT_EN(uart_num);
-#else
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	NPCX_UART_TX_EMPTY_INT_EN(uart_num);
-#endif
-
-	task_trigger_irq(uart_cfg[uart_num].irq);
-}
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable)
-{
-	enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) :
-		NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
-}
-#endif
-
-void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena)
-{
-	/* Disable TX interrupt */
-	NPCX_UART_TX_EMPTY_INT_DIS(uart_num);
-	/*
-	 * Re-allow deep sleep when transmiting on the default pad (deep sleep
-	 * is always disabled when alternate pad is selected).
-	 */
-	if (sleep_ena == 1)
-		enable_sleep(SLEEP_MASK_UART);
-}
-
-void uartn_tx_flush(uint8_t uart_num)
-{
-	/* Wait for transmit FIFO empty and last byte is sent */
-	while (NPCX_UART_TX_IN_XMIT(uart_num))
-		;
-}
-
-int uartn_tx_ready(uint8_t uart_num)
-{
-	return NPCX_UART_TX_IS_READY(uart_num);
-}
-
-int uartn_tx_in_progress(uint8_t uart_num)
-{
-	return NPCX_UART_TX_IN_XMIT(uart_num);
-}
-
-int uartn_rx_available(uint8_t uart_num)
-{
-	return NPCX_UART_RX_IS_AVAILABLE(uart_num);
-}
-
-void uartn_write_char(uint8_t uart_num, char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uartn_tx_ready(uart_num))
-		;
-
-	NPCX_UTBUF(uart_num) = c;
-}
-
-int uartn_read_char(uint8_t uart_num)
-{
-	return NPCX_URBUF(uart_num);
-}
-
-void uartn_clear_rx_fifo(int channel)
-{
-	int scratch __attribute__ ((unused));
-
-	/* If '1',  that means there is RX data on the FIFO register */
-	while (NPCX_UART_RX_IS_AVAILABLE(channel))
-		scratch = NPCX_URBUF(channel);
-}
-
-#ifdef NPCX_UART_FIFO_SUPPORT
-static void uartn_set_fifo_mode(uint8_t uart_num)
-{
-	/* Enable the UART FIFO mode */
-	SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD);
-	/* Disable all Tx interrupts */
-	NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
-					BIT(NPCX_UFTCTL_TEMPTY_EN) |
-					BIT(NPCX_UFTCTL_NXMIPEN));
-}
-
-#endif
-
-static void uartn_config(uint8_t uart_num)
-{
-#ifdef CONFIG_LOW_POWER_IDLE
-	struct npcx_wui wui;
-#endif
-
-	/* Configure pins from GPIOs to CR_UART */
-	gpio_config_module(MODULE_UART, 1);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	/*
-	 * Configure the UART wake-up event triggered from a falling edge
-	 * on CR_SIN pin.
-	 */
-	wui = uart_wui[uart_num];
-	SET_BIT(NPCX_WKEDG(wui.table, wui.group), wui.bit);
-#endif
-	/*
-	 * If apb2's clock is not 15MHz, we need to find the other optimized
-	 * values of UPSR and UBAUD for baud rate 115200.
-	 */
-#if (NPCX_APB_CLOCK(2) != 15000000)
-#error "Unsupported apb2 clock for UART!"
-#endif
-
-	/*
-	 * Fix baud rate to 115200. If this value is modified, please also
-	 * modify the delay in uart_set_pad and uart_reset_default_pad_panic.
-	 */
-	NPCX_UPSR(uart_num) = 0x38;
-	NPCX_UBAUD(uart_num) = 0x01;
-
-	/*
-	 * 8-N-1, FIFO enabled.  Must be done after setting
-	 * the divisor for the new divisor to take effect.
-	 */
-	NPCX_UFRS(uart_num) = 0x00;
-#ifdef NPCX_UART_FIFO_SUPPORT
-	uartn_set_fifo_mode(uart_num);
-#endif
-	NPCX_UART_RX_INT_EN(uart_num);
-}
-
-void uartn_init(uint8_t uart_num)
-{
-	uint32_t offset, mask;
-
-	offset = uart_cfg[uart_num].clk_en_offset;
-	mask = uart_cfg[uart_num].clk_en_msk;
-	clock_enable_peripheral(offset, mask, CGC_MODE_ALL);
-
-	if (uart_num == NPCX_UART_PORT0)
-		npcx_gpio2uart();
-
-	/* Configure UARTs (identically) */
-	uartn_config(uart_num);
-
-	/*
-	 * Enable interrupts for UART0 only. Host UART will have to wait
-	 * until the LPC bus is initialized.
-	 */
-	uartn_clear_rx_fifo(uart_num);
-	task_enable_irq(uart_cfg[uart_num].irq);
-}
diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h
deleted file mode 100644
index e5326f72b8..0000000000
--- a/chip/npcx/uartn.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_UARTN_H
-#define __CROS_EC_UARTN_H
-
-#include "common.h"
-
-/*
- * Initialize the UART module.
- */
-void uartn_init(uint8_t uart_num);
-
-/*
- * Re-enable the UART transmit interrupt.
- *
- * This also forces triggering a UART interrupt, if the transmit interrupt was
- * disabled.
- */
-void uartn_tx_start(uint8_t uart_num);
-
- /* Disable the UART transmit interrupt. */
-void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena);
-
-/* Flush the transmit FIFO. */
-void uartn_tx_flush(uint8_t uart_num);
-
-/* Return non-zero if there is room to transmit a character immediately. */
-int uartn_tx_ready(uint8_t uart_num);
-
-/* Return non-zero if a transmit is in progress. */
-int uartn_tx_in_progress(uint8_t uart_num);
-
-/* Return non-zero if the UART has a character available to read. */
-int uartn_rx_available(uint8_t uart_num);
-
-/*
- * Send a character to the UART data register.
- *
- * If the transmit FIFO is full, blocks until there is space.
- *
- * @param c    Character to send.
- */
-void uartn_write_char(uint8_t uart_num, char c);
-
-/*
- * Read one char from the UART data register.
- *
- * @return		The character read.
- */
-int uartn_read_char(uint8_t uart_num);
-
-/* Clear all data in the UART Rx FIFO */
-void uartn_clear_rx_fifo(int channel);
-
-/* Enable the UART Rx interrupt */
-void uartn_rx_int_en(uint8_t uart_num);
-/* Enable the UART Wake-up */
-void uartn_wui_en(uint8_t uart_num);
-/* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */
-void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable);
-#endif  /* __CROS_EC_UARTN_H */
diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c
deleted file mode 100644
index 55b8df8c1c..0000000000
--- a/chip/npcx/watchdog.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "hwtimer_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "timer.h"
-#include "task.h"
-#include "util.h"
-#include "system_chip.h"
-#include "watchdog.h"
-
-/* WDCNT value for watchdog period */
-#define WDCNT_VALUE \
-	((CONFIG_WATCHDOG_PERIOD_MS * INT_32K_CLOCK) / (1024 * 1000))
-
-void watchdog_init_warning_timer(void)
-{
-	/* init watchdog timer first */
-	init_hw_timer(ITIM_WDG_NO, ITIM_SOURCE_CLOCK_32K);
-
-	/*
-	 * prescaler to TIMER_TICK
-	 * Ttick_unit = (PRE_8+1) * T32k
-	 * PRE_8 = (Ttick_unit/T32K) - 1
-	 * Unit: 1 msec
-	 */
-	NPCX_ITPRE(ITIM_WDG_NO) =
-		DIV_ROUND_NEAREST(1000 * INT_32K_CLOCK, SECOND) - 1;
-
-	/* Event module disable */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* ITIM count down : event expired */
-	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
-	/* Event module enable */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Enable interrupt of ITIM */
-	task_enable_irq(ITIM_INT(ITIM_WDG_NO));
-}
-
-static timestamp_t last_watchdog_touch;
-void watchdog_stop_and_unlock(void)
-{
-	/*
-	 * Ensure we have waited at least 3 watchdog ticks since touching WD
-	 * timer. 3 / (32768 / 1024) HZ = 93.75ms
-	 */
-	while (time_since32(last_watchdog_touch) < (100 * MSEC))
-		continue;
-
-	NPCX_WDSDM = 0x87;
-	NPCX_WDSDM = 0x61;
-	NPCX_WDSDM = 0x63;
-}
-
-static void touch_watchdog_count(void)
-{
-	NPCX_WDSDM = 0x5C;
-	last_watchdog_touch = get_time();
-}
-
-static void watchdog_reload_warning_timer(void)
-{
-	/* Disable warning timer module  */
-	CLEAR_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Wait for module disable to take effect before updating count */
-	while (IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
-		;
-
-	/* Reload the warning timer count */
-	NPCX_ITCNT(ITIM_WDG_NO) = CONFIG_AUX_TIMER_PERIOD_MS;
-
-	/* enable warning timer module  */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN);
-	/* Wait for module enable */
-	while (!IS_BIT_SET(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_ITEN))
-		;
-}
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-#ifdef CONFIG_TASK_PROFILING
-	/*
-	 * Perform IRQ profiling accounting. This is normally done by
-	 * DECLARE_IRQ(), but we are not using that for ITIM_WDG_NO.
-	 */
-	task_start_irq_handler((void *)excep_lr);
-#endif
-
-	/* Clear timeout status for event */
-	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITCTS_TO_STS);
-
-	/* Print panic info */
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-/* ISR for watchdog warning naked will keep SP & LR */
-void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void) __attribute__((naked));
-void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/* Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveninently saves
-			 * R0=LR so we can pass it to task_resched_if_needed. */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO))
-__attribute__((section(".rodata.irqprio")))
-= {ITIM_INT(ITIM_WDG_NO), 0};
-/* put the watchdog at the highest priority */
-
-void watchdog_reload(void)
-{
-	/* Disable watchdog interrupt */
-	task_disable_irq(ITIM_INT(ITIM_WDG_NO));
-
-	watchdog_reload_warning_timer();
-
-#if 1 /* mark this for testing watchdog */
-	/* Touch watchdog & reset software counter */
-	touch_watchdog_count();
-#endif
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(ITIM_INT(ITIM_WDG_NO));
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#if SUPPORT_WDG
-	/* Touch watchdog before init if it is already running */
-	if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WD_RUN))
-		touch_watchdog_count();
-
-	/* Keep prescaler ratio timer0 clock to 1:1024 */
-	NPCX_TWCP = 0x0A;
-	/* Keep prescaler ratio watchdog clock to 1:1 */
-	NPCX_WDCP = 0;
-
-	/* Clear watchdog reset status initially*/
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
-
-	/* Reset TWCFG */
-	NPCX_TWCFG = 0;
-	/* Watchdog touch by writing 5Ch to WDSDM */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDSDME);
-	/* Select T0IN clock as watchdog prescaler clock */
-	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
-	/* Disable early touch functionality */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_TESDIS);
-
-	/*
-	 * Set WDCNT initial reload value and T0OUT timeout period
-	 * WDCNT = 0 will generate watchdog reset
-	 */
-	NPCX_WDCNT = WDCNT_VALUE;
-
-	/* Disable interrupt */
-	interrupt_disable();
-	/* Reload TWDT0/WDCNT */
-	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
-	/* Wait for timer is loaded and restart */
-	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
-		;
-	/* Enable interrupt */
-	interrupt_enable();
-
-	/* Init watchdog warning timer */
-	watchdog_init_warning_timer();
-#endif
-	return EC_SUCCESS;
-}
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
deleted file mode 100644
index c4f68f5369..0000000000
--- a/chip/npcx/wov.c
+++ /dev/null
@@ -1,2071 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific WOV module for Chrome EC */
-
-#include "apm_chip.h"
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "wov_chip.h"
-
-#ifndef NPCX_WOV_SUPPORT
-#error "Do not enable CONFIG_AUDIO_CODEC_* if npcx ec doesn't support WOV !"
-#endif
-
-/* Console output macros */
-#ifndef DEBUG_AUDIO_CODEC
-#define CPUTS(...)
-#define CPRINTS(...)
-#else
-#define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr)
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-#endif
-
-/* WOV FIFO status. */
-#define WOV_STATUS_OFFSET NPCX_WOV_STATUS_CFIFO_OIT
-#define WOV_IS_CFIFO_INT_THRESHOLD(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OIT - WOV_STATUS_OFFSET))
-#define WOV_IS_CFIFO_WAKE_THRESHOLD(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OWT - WOV_STATUS_OFFSET))
-#define WOV_IS_CFIFO_OVERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_CFIFO_OVRN - WOV_STATUS_OFFSET))
-#define WOV_IS_I2S_FIFO_OVERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_I2S_FIFO_OVRN - WOV_STATUS_OFFSET))
-#define WOV_IS_I2S_FIFO_UNDERRUN(sts) \
-	IS_BIT_SET(sts, (NPCX_WOV_STATUS_I2S_FIFO_UNDRN - WOV_STATUS_OFFSET))
-
-/* Core FIFO threshold. */
-#define WOV_SET_FIFO_WAKE_THRESHOLD(n) \
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_WTHRSH, n)
-
-#define WOV_SET_FIFO_INT_THRESHOLD(n) \
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_ITHRSH, n)
-#define WOV_GET_FIFO_INT_THRESHOLD \
-	GET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_ITHRSH)
-
-#define WOV_PLL_IS_NOT_LOCK \
-	(!IS_BIT_SET(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_LOCKI))
-
-/* mask definitions that clear reserved fields for WOV registers.*/
-#define WOV_CLK_CTRL_REG_RESERVED_MASK 0x037F7FFF
-
-#define WOV_GET_FIFO_WAKE_THRESHOLD \
-	GET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_FIFO_WTHRSH)
-
-/* Wait time 4ms for FMUL2 enabled and for configuration tuning sequence. */
-#define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000)
-
-/* The size of RAM buffer to store the voice data */
-#define VOICE_BUF_SIZE    16000
-
-/* PLL setting options. */
-struct wov_pll_set_options_val {
-	uint8_t pll_indv;     /* Input Divider */
-	uint16_t pll_fbdv;    /* Feedback Divider */
-	uint8_t pll_otdv1;    /* Output devide 1. */
-	uint8_t pll_otdv2;    /* Output devide 2. */
-	uint32_t pll_ext_div; /* Index for the table pll_ext_div */
-};
-
-/* PLL External Divider Load Values. */
-struct wov_pll_ext_div_val {
-	uint8_t pll_ediv;    /* Required PLL external divider */
-	uint8_t pll_ediv_dc; /* Required PLL external divider DC */
-};
-
-static const struct wov_pll_ext_div_val pll_ext_div[] = {
-	{0x2F, 0x78}, /* 12 */
-	{0x57, 0x7C}, /* 13 */
-	{0x2B, 0x7C}, /* 14 */
-	{0x55, 0x7E}, /* 15 */
-	{0x2A, 0x7E}, /* 16 */
-	{0x15, 0x7F}, /* 17 */
-	{0x4A, 0x7F}, /* 18 */
-	{0x65, 0x3F}, /* 19 */
-	{0x32, 0x3F}, /* 20 */
-	{0x19, 0x5F}, /* 21 */
-	{0x4C, 0x5F}, /* 22 */
-	{0x66, 0x2F}, /* 23 */
-	{0x73, 0x2F}, /* 24 */
-	{0x39, 0x57}, /* 25 */
-	{0x5C, 0x57}, /* 26 */
-	{0x6E, 0x2B}, /* 27 */
-	{0x77, 0x2B}, /* 28 */
-	{0x3B, 0x55}, /* 29 */
-	{0x5D, 0x55}, /* 30 */
-	{0x2E, 0x2A}, /* 31 */
-	{0x17, 0x2A}, /* 32 */
-	{0x4B, 0x15}, /* 33 */
-	{0x25, 0x15}, /* 34 */
-	{0x52, 0x4A}, /* 35 */
-	{0x69, 0x4A}, /* 36 */
-	{0x34, 0x65}, /* 37 */
-	{0x1A, 0x65}, /* 38 */
-	{0x0D, 0x32}, /* 39 */
-	{0x46, 0x32}, /* 40 */
-	{0x63, 0x19}, /* 41 */
-	{0x31, 0x19}, /* 42 */
-	{0x58, 0x4C}, /* 43 */
-	{0x6C, 0x4C}, /* 44 */
-	{0x76, 0x66}, /* 45 */
-	{0x7B, 0x66}, /* 46 */
-	{0x3D, 0x73}, /* 47 */
-	{0x5E, 0x73}, /* 48 */
-	{0x6F, 0x39}, /* 49 */
-	{0x37, 0x39}, /* 50 */
-	{0x5B, 0x5C}, /* 51 */
-	{0x2D, 0x5C}, /* 52 */
-	{0x56, 0x6E}, /* 53 */
-	{0x6B, 0x6E}, /* 54 */
-	{0x35, 0x77}, /* 55 */
-	{0x5A, 0x77}, /* 56 */
-	{0x6D, 0x3B}, /* 57 */
-	{0x36, 0x3B}, /* 58 */
-	{0x1B, 0x5D}, /* 59 */
-	{0x4D, 0x5D}, /* 60 */
-	{0x26, 0x2E}, /* 61 */
-	{0x13, 0x2E}, /* 62 */
-	{0x49, 0x17}, /* 63 */
-	{0x24, 0x17}, /* 64 */
-	{0x12, 0x4B}, /* 65 */
-	{0x09, 0x4B}, /* 66 */
-	{0x44, 0x25}  /* 67 */
-};
-
-/* WOV interrupts */
-static const uint8_t wov_interupts[] = {
-	0,  /* VAD_INTEN */
-	1,  /* VAD_WKEN */
-	8,  /* CFIFO_NE_IE */
-	9,  /* CFIFO_OIT_IE */
-	10, /* CFIFO_OWT_WE */
-	11, /* CFIFO_OVRN_IE */
-	12, /* I2S_FIFO_OVRN_IE */
-	13  /* I2S_FIFO_UNDRN_IE */
-};
-
-struct wov_ppl_divider {
-	uint16_t pll_frame_len; /* PLL frame length. */
-	uint16_t pll_fbdv;      /* PLL feedback divider. */
-	uint8_t pll_indv;       /* PLL Input Divider. */
-	uint8_t pll_otdv1;      /* PLL Output Divider 1. */
-	uint8_t pll_otdv2;      /* PLL Output Divider 2. */
-	uint8_t pll_ediv;       /* PLL External Divide Factor. */
-};
-
-struct wov_cfifo_buf {
-	uint32_t *buf; /* Pointer to a buffer. */
-	int size;      /* Buffer size in words. */
-};
-
-struct wov_config wov_conf;
-
-static struct wov_cfifo_buf cfifo_buf;
-static wov_call_back_t callback_fun;
-
-#define WOV_RATE_ERROR_THRESH_MSEC 10
-#define WOV_RATE_ERROR_THRESH 5
-
-static int irq_underrun_count;
-static int irq_overrun_count;
-static uint32_t wov_i2s_underrun_tstamp;
-static uint32_t wov_i2s_overrun_tstamp;
-
-#define WOV_CALLBACK(event)                  \
-	{                                    \
-		if (callback_fun != NULL)    \
-			callback_fun(event); \
-	}
-
-#define CONFIG_WOV_FIFO_THRESH_WORDS WOV_FIFO_THRESHOLD_80_DATA_WORDS
-
-/**
- * Reads data from the core fifo.
- *
- * @param   num_elements - Number of elements (Dword) to read.
- *
- * @return  None
- */
-void wov_cfifo_read_handler_l(uint32_t num_elements)
-{
-	uint32_t index;
-
-	for (index = 0; index < num_elements; index++)
-		cfifo_buf.buf[index] = NPCX_WOV_FIFO_OUT;
-
-	cfifo_buf.buf = &cfifo_buf.buf[index];
-	cfifo_buf.size -= num_elements;
-}
-
-static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
-					int32_t total_div, int32_t vco_freq,
-					struct wov_ppl_divider *pll_div)
-{
-	int32_t	 d_1, d_2, d_e;
-
-	/*
-	 * Please see comments in wov_calc_pll_div_l function below.
-	 */
-	for (d_e = 4; d_e < 75; d_e++) {
-		for (d_2 = 1; d_2 < 7; d_2++) {
-			for (d_1 = 1; d_1 < 7; d_1++) {
-				if ((vco_freq / (d_1 * d_2)) > 900)
-					continue;
-
-				if (total_div == (d_in * d_e * d_1 * d_2)) {
-					pll_div->pll_indv  = d_in;
-					pll_div->pll_otdv1 = d_1;
-					pll_div->pll_otdv2 = d_2;
-					pll_div->pll_ediv  = d_e;
-					return EC_SUCCESS;
-				}
-			}
-		}
-	}
-	return EC_ERROR_INVAL;
-}
-
-/**
- * Gets the PLL divider value accordingly to the i2S clock frequency.
- *
- * @param   i2s_clk_freq - i2S clock frequency
- * @param   sample_rate  - Sample rate in KHz (16KHz or 48KHz)
- * @param   pll_div      - PLL dividers.
- *
- * @return  None
- */
-static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
-			uint32_t sample_rate, struct wov_ppl_divider *pll_div)
-{
-	int32_t d_f;
-	int32_t total_div;
-	int32_t d_in;
-	int32_t n;
-	int32_t vco_freq;
-	int32_t i2s_clk_freq_khz;
-
-	n = i2s_clk_freq / sample_rate;
-	if (i2s_clk_freq != (sample_rate * n))
-		return EC_ERROR_INVAL;
-
-	if ((n < 32) || (n >= 257))
-		return EC_ERROR_INVAL;
-
-	pll_div->pll_frame_len = n;
-
-	i2s_clk_freq_khz = i2s_clk_freq / 1000;
-
-	/*
-	 * The code below implemented the “PLL setting option� table as
-	 * describe in the NPCX7m7wb specification document.
-	 * - Total_div is VCO frequency in MHz / 12 MHz
-	 * - d_f is the Feedback Divider
-	 * - d_in is the Input Divider (PLL_INDV)
-	 * - d_e is the PLL Ext Divider
-	 * - d_2 is the Output Divide 2 (PLL_OTDV2)
-	 * - d_1 is the Output Divide 1 (PLL_OTDV1)
-	 * It is preferred that d_f will be as smaller as possible, after that
-	 * the d_in will be as smaller as possible and so on, this is the
-	 * reason that d_f (calculated from total_div) is in the external loop
-	 * and d-1 is in the internal loop (as it may contain the bigger value).
-	 * The “PLL setting option� code divided to 2 function in order to
-	 * fulfil the coding style indentation rule.
-	 */
-
-	/* total div is min_vco/12 400/12=33. */
-	for (total_div = 33; total_div < 1500; total_div++) {
-		d_f = (total_div * 12000) / i2s_clk_freq_khz;
-		if ((total_div * 12000) == (d_f * i2s_clk_freq_khz)) {
-			for (d_in = 1; d_in < 10; d_in++) {
-				if (((i2s_clk_freq / 1000) / d_in) <= 500)
-					continue;
-
-				vco_freq = total_div * 12 / d_in;
-				if ((vco_freq < 500) || (vco_freq > 1600))
-					continue;
-				if (wov_calc_pll_div_s(d_in, total_div,
-						vco_freq, pll_div) ==
-						EC_SUCCESS) {
-					pll_div->pll_fbdv  = d_f;
-					return EC_SUCCESS;
-				}
-
-			}
-		}
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-/**
- * Check if PLL is locked.
- *
- * @param   None
- *
- * @return  EC_SUCCESS if PLL is locked, EC_ERROR_UNKNOWN otherwise .
- */
-enum ec_error_list wov_wait_for_pll_lock_l(void)
-{
-	volatile uint32_t index;
-
-	for (index = 0; WOV_PLL_IS_NOT_LOCK; index++) {
-		/* PLL doesn't reach to lock state. */
-		if (index > 0xFFFF)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Configure I2S bus. (Parameters determined via common config functions.)
- *
- * @param   None.
- *
- * @return  none.
- */
-static enum ec_error_list wov_set_i2s_config_l(void)
-{
-	struct wov_ppl_divider pll_div;
-	enum ec_error_list ret_code;
-	enum wov_i2s_chan_trigger trigger_0, trigger_1;
-	int32_t start_delay_0, start_delay_1;
-
-	ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock,
-				wov_conf.sample_per_sec, &pll_div);
-	if (ret_code == EC_SUCCESS) {
-		/* Configure the PLL. */
-		ret_code = wov_pll_clk_div_config(
-			pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv,
-			pll_div.pll_indv);
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-
-		ret_code = wov_pll_clk_ext_div_config(
-			(enum wov_pll_ext_div_sel)(pll_div.pll_ediv > 15),
-			pll_div.pll_ediv);
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-
-		wov_i2s_global_config(
-			(enum wov_floating_mode)(wov_conf.dai_format ==
-						 WOV_DAI_FMT_PCM_TDM),
-			WOV_FLOATING_DRIVEN, WOV_CLK_NORMAL, 0, WOV_PULL_DOWN,
-			0, WOV_PULL_DOWN, WOV_NORMAL_MODE);
-
-		/* Configure DAI format. */
-		switch (wov_conf.dai_format) {
-		case WOV_DAI_FMT_I2S:
-			trigger_0 = WOV_I2S_SAMPLED_0_AFTER_1;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 1;
-			start_delay_1 = 1;
-			break;
-
-		case WOV_DAI_FMT_RIGHT_J:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_0_AFTER_1;
-			start_delay_0 = (pll_div.pll_frame_len / 2) -
-					wov_conf.bit_depth;
-			start_delay_1 = (pll_div.pll_frame_len / 2) -
-					wov_conf.bit_depth;
-			break;
-
-		case WOV_DAI_FMT_LEFT_J:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_0_AFTER_1;
-			start_delay_0 = 0;
-			start_delay_1 = 0;
-			break;
-
-		case WOV_DAI_FMT_PCM_A:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 1;
-			start_delay_1 = wov_conf.bit_depth + 1;
-			break;
-
-		case WOV_DAI_FMT_PCM_B:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = 0;
-			start_delay_1 = wov_conf.bit_depth;
-			break;
-
-		case WOV_DAI_FMT_PCM_TDM:
-			trigger_0 = WOV_I2S_SAMPLED_1_AFTER_0;
-			trigger_1 = WOV_I2S_SAMPLED_1_AFTER_0;
-			start_delay_0 = wov_conf.i2s_start_delay_0;
-			start_delay_1 = wov_conf.i2s_start_delay_1;
-			break;
-
-		default:
-			return EC_ERROR_INVALID_CONFIG;
-		}
-
-		udelay(100);
-
-		ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth,
-					trigger_0, start_delay_0);
-
-		ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth,
-					trigger_1, start_delay_1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * wov_i2s_channel1_disable
- *
- * @param  disable - disabled flag, 1 means disable
- *
- * @return  None
- */
-static void wov_i2s_channel1_disable(int disable)
-{
-	if (disable)
-		SET_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(1),
-			  NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS);
-}
-
-/**
- * Sets microphone source.
- *
- *		    |	Left	|  Right	|  Mono		|  Stereo
- *------------------|-----------|---------------|---------------|--------------
- *FIFO_CNT.	    |0x0 or 0x2	| 0x0 or 0x2	| 0x1 or 0x3	|0x1 or 0x3
- *CFIFI_ISEL	    |	(left)	|(left)		|(left & Right)	|(left & right)
- *------------------|-----------|---------------|---------------|--------------
- *CR_DMIC.	    |   0x1	|     0x1	|      0x2	|     0x1
- *ADC_DMIC_SEL_LEFT |  (left)	|    (left)	|   (average)	|   (left)
- *------------------|-----------|---------------|---------------|--------------
- *CR_DMIC.	    |   0x1	|     0x1	|      0x2	|     0x1
- *ADC_DMIC_SEL_RIGHT|  (right)	|    (right)	|   (average)	|   (right)
- *------------------|-----------|---------------|---------------|--------------
- *MIX_2.	    |   0x0	|     0x1	|      0x0	|     0x0
- *AIADCL_SEL	    |  (normal)	|(cross inputs)	|    (normal)	|   (normal)
- *------------------|-----------|---------------|---------------|--------------
- *MIX_2.	    |   0x3	|     0x3	|      0x0	|     0x0
- *AIADCR_SEL	    |(no input)	|  (no input)	|    (normal)	|   (normal)
- *------------------|-----------|---------------|---------------|--------------
- *VAD_0.	    |   0x0	|     0x1	|      0x2	|    Not
- *VAD_INSEL	    |  (left)	|    (right)	|    (average)	|  applicable
- *
- * @param   None.
- * @return  return EC_SUCCESS if mic source valid othewise return error code.
- */
-static enum ec_error_list wov_set_mic_source_l(void)
-{
-	switch (wov_conf.mic_src) {
-	case WOV_SRC_LEFT:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					 APM_OUT_MIX_NO_INPUT);
-		apm_set_vad_input_channel(APM_IN_LEFT);
-		wov_i2s_channel1_disable(1);
-		break;
-
-	case WOV_SRC_RIGHT:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT,
-					APM_OUT_MIX_NO_INPUT);
-		apm_set_vad_input_channel(APM_IN_RIGHT);
-		wov_i2s_channel1_disable(1);
-		break;
-
-	case WOV_SRC_MONO:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x02);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x02);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					APM_OUT_MIX_NORMAL_INPUT);
-		apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT);
-		wov_i2s_channel1_disable(0);
-		break;
-
-	case WOV_SRC_STEREO:
-		if (wov_conf.bit_depth == 16)
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
-		else
-			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
-		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
-		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					 APM_OUT_MIX_NORMAL_INPUT);
-		wov_i2s_channel1_disable(0);
-		break;
-
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void wov_over_under_deferred(void)
-{
-	CPRINTS("wov: Under/Over run error: under = %d, over = %d",
-		irq_underrun_count, irq_overrun_count);
-}
-DECLARE_DEFERRED(wov_over_under_deferred);
-
-static void wov_under_over_error_handler(int *count, uint32_t *last_time)
-{
-	uint32_t time_delta_msec;
-	uint32_t current_time = get_time().le.lo;
-
-	if (!(*count)) {
-		*last_time = current_time;
-		(*count)++;
-	} else {
-		time_delta_msec = (current_time - *last_time) / MSEC;
-		*last_time = current_time;
-		if (time_delta_msec < WOV_RATE_ERROR_THRESH_MSEC)
-			(*count)++;
-		else
-			*count = 0;
-
-		if (*count >= WOV_RATE_ERROR_THRESH) {
-			wov_stop_i2s_capture();
-			hook_call_deferred(&wov_over_under_deferred_data, 0);
-		}
-	}
-}
-
-/**
- * WoV interrupt handler.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_interrupt_handler(void)
-{
-	uint32_t wov_status;
-	uint32_t wov_inten;
-
-	wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS);
-	wov_status = wov_inten &
-			GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
-
-	/*
-	 * Voice activity detected.
-	 */
-	if (APM_IS_VOICE_ACTIVITY_DETECTED) {
-		apm_enable_vad_interrupt(0);
-		APM_CLEAR_VAD_INTERRUPT;
-		WOV_CALLBACK(WOV_EVENT_VAD);
-	}
-
-	/* Core FIFO is overrun. Reset the Core FIFO and inform the FW */
-	if (WOV_IS_CFIFO_OVERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN);
-		wov_core_fifo_reset();
-	} else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) &&
-				(cfifo_buf.buf != NULL)) {
-		/*
-		 * Core FIFO threshold or FIFO not empty event occurred.
-		 * - Read data from core FIFO to the buffer.
-		 * - In case data ready or no space for data, inform the FW.
-		 */
-
-		/* Copy data from CFIFO to RAM. */
-		wov_cfifo_read_handler_l((WOV_GET_CORE_FIFO_THRESHOLD * 2));
-
-		if (cfifo_buf.size < (WOV_GET_CORE_FIFO_THRESHOLD * 2)) {
-			cfifo_buf.buf = NULL;
-			cfifo_buf.size = 0;
-			WOV_CALLBACK(WOV_EVENT_DATA_READY);
-		}
-	}
-
-	/* I2S FIFO is overrun. Reset the I2S FIFO and inform the FW. */
-	if (WOV_IS_I2S_FIFO_OVERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_I2S_FIFO_OVERRUN);
-		wov_under_over_error_handler(&irq_overrun_count,
-					     &wov_i2s_overrun_tstamp);
-		wov_i2s_fifo_reset();
-	}
-
-	/* I2S FIFO is underrun. Reset the I2S FIFO and inform the FW. */
-	if (WOV_IS_I2S_FIFO_UNDERRUN(wov_status)) {
-		WOV_CALLBACK(WOV_EVENT_ERROR_I2S_FIFO_UNDERRUN);
-		wov_under_over_error_handler(&irq_underrun_count,
-					     &wov_i2s_underrun_tstamp);
-		wov_i2s_fifo_reset();
-	}
-
-
-	/* Clear the WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status);
-}
-
-DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4);
-
-/**
- * Enable FMUL2.
- *
- * @param   enable - enabled flag, true for enable
- * @return  None
- */
-static void wov_fmul2_enable(int enable)
-{
-	if (enable) {
-
-		/* If clock disabled, then enable it. */
-		if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
-			/* Enable clock tuning. */
-			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-			/* Enable clock. */
-			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
-
-			udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
-		}
-	} else
-		SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
-}
-
-#define WOV_FMUL2_MAX_RETRIES 0x000FFFFF
-
-/* FMUL2 clock multipliers values. */
-struct wov_fmul2_multiplier_setting_val {
-	uint8_t fm2mh;
-	uint8_t fm2ml;
-	uint8_t fm2n;
-};
-
-/**
- * Configure FMUL2 clock tunning.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_conf_tuning(void)
-{
-	/* Check if FMUL2 is enabled, then do nothing. */
-	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) ==
-			0x00)
-		return;
-
-	/* Enable clock tuning. */
-	CLEAR_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-
-	udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
-	/* Disable clock tuning. */
-	SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-}
-
-static int wov_get_cfifo_threshold_l(void)
-{
-	int fifo_threshold;
-
-	fifo_threshold = WOV_GET_FIFO_INT_THRESHOLD;
-
-	if (fifo_threshold == 0)
-		return 1;
-	else
-		return (fifo_threshold * 2);
-}
-
-/**
- * Gets clock source FMUL2 or PLL.
- *
- * @param   None.
- *
- *  NOTE:
- *
- * @return  The clock source FMUL2 (WOV_FMUL2_CLK_SRC) and
- *                    PLL (WOV_PLL_CLK_SRC)
- */
-static enum wov_clk_src_sel wov_get_clk_selection(void)
-{
-	if (IS_BIT_SET(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL))
-		return WOV_PLL_CLK_SRC;
-	else
-		return WOV_FMUL2_CLK_SRC;
-}
-
-/***************************************************************************
- *
- * Exported function.
- *
- **************************************************************************/
-
-/**
- * Set FMUL2 clock divider.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_set_clk_divider(enum fmul2_clk_divider clk_div)
-{
-	SET_FIELD(NPCX_FMUL2_FM2P, NPCX_FMUL2_FM2P_WFPRED, clk_div);
-}
-
-/**
- * Configure DMIC clock.
- *
- * @param   enable          - DMIC enabled , 1 means enable
- * @param   clk_div         - DMIC clock division factor (disable, divide by 2
- *			      divide by 4)
- * @return  None
- */
-void wov_dmic_clk_config(int enable, enum wov_dmic_clk_div_sel clk_div)
-{
-	/* If DMIC enabled then configured its clock.*/
-	if (enable) {
-		if (clk_div != WOV_DMIC_DIV_DISABLE) {
-			SET_BIT(NPCX_WOV_CLOCK_CNTL,
-				NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN);
-			if (clk_div == WOV_DMIC_DIV_BY_2)
-				CLEAR_BIT(NPCX_WOV_CLOCK_CNTL,
-					  NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL);
-			else
-				SET_BIT(NPCX_WOV_CLOCK_CNTL,
-					NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL);
-		} else
-			CLEAR_BIT(NPCX_WOV_CLOCK_CNTL,
-				  NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN);
-
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_DMIC_EN);
-	} else
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_DMIC_EN);
-}
-
-/**
- * Sets WoV mode
- *
- * @param   wov_mode - WoV mode
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_mode(enum wov_modes wov_mode)
-{
-	enum ec_error_list ret_code;
-	enum wov_clk_src_sel prev_clock;
-
-	/* If mode is OFF, then power down and exit. */
-	if (wov_mode == WOV_MODE_OFF) {
-		wov_stop_i2s_capture();
-		wov_stop_ram_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		wov_dmic_clk_config(0, WOV_DMIC_DIV_DISABLE);
-		wov_mute(1);
-		apm_set_mode(WOV_MODE_OFF);
-		wov_fmul2_enable(0);
-		wov_conf.mode = WOV_MODE_OFF;
-		return EC_SUCCESS;
-	}
-
-	switch (wov_mode) {
-	case WOV_MODE_VAD:
-		if (apm_get_vad_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_vad_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		wov_stop_i2s_capture();
-		wov_stop_ram_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		break;
-	case WOV_MODE_RAM:
-		if ((wov_conf.bit_depth != 16) && (wov_conf.bit_depth != 24))
-			return EC_ERROR_INVAL;
-
-		if (apm_get_adc_ram_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_adc_ram_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		wov_stop_i2s_capture();
-		wov_set_clk_selection(WOV_FMUL2_CLK_SRC);
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		wov_start_ram_capture();
-		break;
-	case WOV_MODE_RAM_AND_I2S:
-		if ((wov_conf.bit_depth != 16) && (wov_conf.bit_depth != 24))
-			return EC_ERROR_INVAL;
-	case WOV_MODE_I2S:
-		if (apm_get_adc_i2s_dmic_rate() == APM_DMIC_RATE_0_75)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_4);
-		else if (apm_get_adc_i2s_dmic_rate() == APM_DMIC_RATE_1_2)
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_BY_2);
-		else
-			wov_dmic_clk_config(1, WOV_DMIC_DIV_DISABLE);
-		prev_clock = wov_get_clk_selection();
-		if (prev_clock != WOV_PLL_CLK_SRC) {
-			wov_set_i2s_config_l();
-			wov_set_clk_selection(WOV_PLL_CLK_SRC);
-		}
-		apm_set_mode(wov_mode);
-		ret_code = wov_set_mic_source_l();
-		if (ret_code != EC_SUCCESS)
-			return ret_code;
-		wov_start_i2s_capture();
-		if (wov_mode == WOV_MODE_RAM_AND_I2S)
-			wov_start_ram_capture();
-		else
-			wov_stop_ram_capture();
-		break;
-	default:
-		wov_dmic_clk_config(0, WOV_DMIC_DIV_DISABLE);
-		wov_fmul2_enable(0);
-		wov_mute(1);
-		return EC_ERROR_INVAL;
-	}
-
-	wov_mute(0);
-
-	wov_conf.mode = wov_mode;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets WoV mode
- *
- * @param   None
- * @return  WoV mode
- */
-enum wov_modes wov_get_mode(void)
-{
-	return wov_conf.mode;
-}
-
-/**
- * Initiates WoV.
- *
- * @param	callback	 - Pointer to callback function.
- *
- * @return	None
- */
-void wov_init(void)
-{
-	apm_init();
-
-	wov_apm_active(1);
-	wov_mute(1);
-
-	wov_conf.mode = WOV_MODE_OFF;
-	wov_conf.sample_per_sec = 16000;
-	wov_conf.bit_depth = 16;
-	wov_conf.mic_src = WOV_SRC_LEFT;
-	wov_conf.left_chan_gain = 0;
-	wov_conf.right_chan_gain = 0;
-	wov_conf.i2s_start_delay_0 = 0;
-	wov_conf.i2s_start_delay_1 = 0;
-	wov_conf.i2s_clock = 0;
-	wov_conf.dai_format = WOV_DAI_FMT_I2S;
-	wov_conf.sensitivity_db = 5;
-
-	/* Set DMIC clock signal output to use fast transitions. */
-	SET_BIT(NPCX_DEVALT(0xE), NPCX_DEVALTE_DMCLK_FAST);
-
-	callback_fun = wov_handle_event;
-
-	wov_cfifo_config(WOV_CFIFO_IN_LEFT_CHAN_2_CONS_16_BITS,
-			 WOV_FIFO_THRESHOLD_80_DATA_WORDS);
-
-	apm_set_vad_dmic_rate(APM_DMIC_RATE_0_75);
-	apm_set_adc_ram_dmic_config(APM_DMIC_RATE_0_75);
-	apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_3_0);
-}
-
-/**
- * Select clock source FMUL2 or PLL.
- *
- * @param   clk_src - select between FMUL2 (WOV_FMUL2_CLK_SRC) and
- *                    PLL (WOV_PLL_CLK_SRC)
- *
- *  NOTE: THIS FUNCTION RESETS THE APM and RETURN ITS REGISSTERS TO THEIR
- *        DEFAULT VALUES !!!!!!!
- *
- * @return  None
- */
-void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
-{
-	int is_apm_disable;
-
-	/*
-	 * Be sure that both clocks are active, as both of them need to
-	 * be active when modify the CLK_SEL bit.
-	 */
-	if (IS_BIT_SET(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN))
-		wov_pll_enable(1);
-
-	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS))
-		wov_fmul2_enable(1);
-
-	is_apm_disable = IS_BIT_SET(NPCX_APM_CR_APM, NPCX_APM_CR_APM_PD);
-
-	apm_enable(0);
-
-	if (clk_src == WOV_FMUL2_CLK_SRC)
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL);
-	else if (wov_wait_for_pll_lock_l() == EC_SUCCESS)
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_CLK_SEL);
-
-	udelay(100);
-
-	if (!is_apm_disable)
-		apm_enable(1);
-
-	/* Disable the unneeded clock. */
-	if (clk_src == WOV_PLL_CLK_SRC)
-		wov_fmul2_enable(0);
-	else
-		wov_pll_enable(0);
-
-}
-
-/**
- * Configure PLL clock.
- *
- * @param   ext_div_sel         - PLL external divider selector.
- * @param   div_factor          - When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT
- *                                then it is the 4 LSBits of this field,
- *                                otherwise this field is an index to
- *                                PLL External Divider Load Values table.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel,
-	uint32_t div_factor)
-{
-	/* Sets the clock division factor for the PLL external divider.
-	 * The divide factor should be in the range of 2 to 67.
-	 * When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT, then the 4 least
-	 * significant bits of div_factor  are used to set the divide
-	 * ratio.
-	 * In this case the divide ration legal values are from 2 to 15
-	 * For WOV_PLL_EXT_DIV_LFSR, this parameter is used as index for
-	 * pll_ext_div table.
-	 */
-	if (ext_div_sel == WOV_PLL_EXT_DIV_BIN_CNT)
-		CLEAR_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL);
-	else
-		SET_BIT(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL);
-
-	if (ext_div_sel == WOV_PLL_EXT_DIV_BIN_CNT) {
-		if ((div_factor > 15) || (div_factor < 2))
-			return EC_ERROR_INVAL;
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV,
-			  (div_factor));
-	} else {
-		if ((div_factor > 67) || (div_factor < 12))
-			return EC_ERROR_INVAL;
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV,
-			  pll_ext_div[div_factor - 12].pll_ediv);
-
-		SET_FIELD(NPCX_WOV_CLOCK_CNTL, NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC,
-			  pll_ext_div[div_factor - 12].pll_ediv_dc);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * PLL power down.
- *
- * @param   enable - 1 enable the PLL or 0 PLL disable
- * @return  None
- */
-void wov_pll_enable(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-	else
-		SET_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	udelay(100);
-}
-
-/**
- * Configures PLL clock dividers..
- *
- * @param   out_div_1    - PLL output divider #1, valid values 1-7
- * @param   out_div_2    - PLL output divider #2, valid values 1-7
- * @param   feedback_div - PLL feadback divider (Default is 375 decimal)
- * @param   in_div       - PLL input divider
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-					uint32_t out_div_2,
-					uint32_t feedback_div,
-					uint32_t in_div)
-{
-	/* Parameter check. */
-	if ((out_div_1 < 1) || (out_div_1 > 7) ||
-		(out_div_2 < 1) || (out_div_2 > 7))
-		return EC_ERROR_INVAL;
-
-	/*
-	 * PLL configuration sequence:
-	 * 1. Set PLL_PWDEN bit to 1.
-	 * 2. Set PLL divider values.
-	 * 3. Wait 1usec.
-	 * 4. Clear PLL_PWDEN bit to 0 while not changing other PLL parameters.
-	 */
-	SET_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_OTDV1, out_div_1);
-	SET_FIELD(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_OTDV2, out_div_2);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL2, NPCX_WOV_PLL_CNTL2_PLL_FBDV,
-		  feedback_div);
-
-	SET_FIELD(NPCX_WOV_PLL_CNTL2, NPCX_WOV_PLL_CNTL2_PLL_INDV, in_div);
-
-	udelay(100);
-
-	CLEAR_BIT(NPCX_WOV_PLL_CNTL1, NPCX_WOV_PLL_CNTL1_PLL_PWDEN);
-
-	udelay(100);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Enables/Disables WoV interrupt.
- *
- * @param   int_index - Interrupt ID.
- * @param   enable    - enabled flag, 1 means enable
- *
- * @return  None.
- */
-void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable)
-{
-	if (enable)
-		SET_BIT(NPCX_WOV_WOV_INTEN, wov_interupts[int_index]);
-	else
-		CLEAR_BIT(NPCX_WOV_WOV_INTEN, wov_interupts[int_index]);
-}
-
-/**
- * Sets core FIFO threshold.
- *
- * @param   in_sel    - Core FIFO input select
- * @param   threshold - Core FIFO threshold
- *
- * @return  None
- */
-void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-		      enum wov_fifo_threshold threshold)
-{
-	/* Set core FIFO input selection. */
-	SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CFIFO_ISEL, in_sel);
-
-	/* Set wake & interrupt core FIFO threshold. */
-	WOV_SET_FIFO_WAKE_THRESHOLD(threshold);
-	WOV_SET_FIFO_INT_THRESHOLD(threshold);
-}
-
-/**
- * Start the actual capturing of the Voice data to the RAM.
- * Note that the pointer to the RAM buffer must be precisely
- * set by calling wov_set_buffer();
- *
- * @param   None
- *
- * @return  None
- */
-void wov_start_ram_capture(void)
-{
-	/* Clear the CFIFO status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x27);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	wov_interrupt_enable(WOV_CFIFO_OVERRUN_INT_INDX, 1);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_INT_INDX, 1);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_WAKE_INDX, 1);
-}
-
-/**
- * Stop the capturing of the Voice data to the RAM.
- *
- * @param   none
- *
- * @return  None
- */
-void wov_stop_ram_capture(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	wov_interrupt_enable(WOV_CFIFO_OVERRUN_INT_INDX, 0);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_INT_INDX, 0);
-	wov_interrupt_enable(WOV_CFIFO_THRESHOLD_WAKE_INDX, 0);
-
-	udelay(100);
-}
-
-/**
- * Rests the Core FIFO.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_core_fifo_reset(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-
-	udelay(1000);
-
-	/* Clear the CFIFO status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x27);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CORE_FFRST);
-}
-
-/**
- * Rests the I2S FIFO.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_i2s_fifo_reset(void)
-{
-	int disable;
-
-	disable = IS_BIT_SET(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	udelay(1000);
-
-	/* Clear the I2S status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x18);
-
-	if (!disable)
-		CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-}
-
-/**
- * Start the capturing of the Voice data via I2S.
- *
- * @param   None
- *
- * @return  None
- */
-void wov_start_i2s_capture(void)
-{
-	/* Clear counters used to track for underrun/overrun errors */
-	irq_underrun_count = 0;
-	irq_overrun_count = 0;
-
-	/* Clear the I2S status bits in WoV status register. */
-	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, 0x18);
-
-	CLEAR_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	wov_interrupt_enable(WOV_I2SFIFO_OVERRUN_INT_INDX, 1);
-	wov_interrupt_enable(WOV_I2SFIFO_UNDERRUN_INT_INDX, 1);
-}
-
-/**
- * Stop the capturing of the Voice data via I2S.
- *
- * @param   none
- *
- * @return  None
- */
-void wov_stop_i2s_capture(void)
-{
-	SET_BIT(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_I2S_FFRST);
-
-	wov_interrupt_enable(WOV_I2SFIFO_OVERRUN_INT_INDX, 0);
-	wov_interrupt_enable(WOV_I2SFIFO_UNDERRUN_INT_INDX, 0);
-
-	udelay(100);
-}
-
-/**
- * Sets data buffer for reading from core FIFO
- *
- * @param  buff          - Pointer to the read buffer, buffer must be 32 bits
- *                         aligned.
- * @param  size_in_words - Size must be a multiple of CONFIG_WOV_THRESHOLD_WORDS
- *                         (defaulte = 80 words)
- *
- * @return  None
- *
- *  Note - When the data buffer will be full the FW will be notifyed
- *         about it, and the FW will need to recall to this function.
- */
-int wov_set_buffer(uint32_t *buf, int size_in_words)
-{
-	int cfifo_threshold;
-
-	cfifo_threshold = wov_get_cfifo_threshold_l();
-	if (size_in_words !=
-		((size_in_words / cfifo_threshold) * cfifo_threshold))
-		return EC_ERROR_INVAL;
-
-	cfifo_buf.buf = buf;
-	cfifo_buf.size = size_in_words;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Resets the APM.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void wov_apm_active(int enable)
-{
-	/* For APM it is negativ logic. */
-	if (enable)
-		CLEAR_BIT(NPCX_WOV_APM_CTRL, NPCX_WOV_APM_CTRL_APM_RST);
-	else
-		SET_BIT(NPCX_WOV_APM_CTRL, NPCX_WOV_APM_CTRL_APM_RST);
-}
-
-/**
- * I2S golobal configuration
- *
- * @param   i2s_hiz_data  - Defines when the I2S data output is floating.
- * @param   i2s_hiz       - Defines if the I2S data output is always floating.
- * @param   clk_invert    - Defines the I2S bit clock edge sensitivity
- * @param   out_pull_en   - Enable a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   out_pull_mode - Select a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   in_pull_en    - Enable a pull-up or a pull-down resistor on
- *                          I2S input
- * @param   in_pull_mode  - Select a pull-up or a pull-down resistor on
- *                          I2S intput
- * @param   test_mode     - Selects I2S test mode
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en,
-	enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode)
-{
-	/* Check the parameters correctness. */
-	if ((i2s_hiz_data == WOV_FLOATING) &&
-		((GET_FIELD(NPCX_WOV_I2S_CNTL(0),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) ||
-		(GET_FIELD(NPCX_WOV_I2S_CNTL(1),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0)))
-		return EC_ERROR_INVAL;
-
-	/* Set the parameters. */
-	if (i2s_hiz_data == WOV_FLOATING_DRIVEN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZD);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZD);
-
-	if (i2s_hiz == WOV_FLOATING_DRIVEN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZ);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_HIZ);
-
-	if (clk_invert == WOV_CLK_NORMAL)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0),
-			  NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV);
-
-	if (out_pull_en)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPE);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPE);
-
-	if (out_pull_mode == WOV_PULL_DOWN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPS);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_OPS);
-
-	if (in_pull_en)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPE);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPE);
-
-	if (in_pull_mode == WOV_PULL_DOWN)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPS);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_IPS);
-
-	if (test_mode == WOV_NORMAL_MODE)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_TST);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL0_I2S_TST);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-/**
- * I2S channel configuration
- *
- * @param  channel_num     - I2S channel number, 0 or 1.
- * @param  bit_count       - I2S channel bit count.
- * @param  trigger         - Define the I2S chanel trigger 1->0 or 0->1
- * @param  start_delay     - Defines the delay from the trigger defined for
- *                           the channel till the first bit (MSB) of the data.
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-					uint32_t bit_count,
-					enum wov_i2s_chan_trigger trigger,
-					int32_t start_delay)
-{
-	/* Check the parameters correctnes. */
-	if ((channel_num != 0) && (channel_num != 1))
-		return EC_ERROR_INVAL;
-
-	if ((start_delay < 0) || (start_delay > 496))
-		return EC_ERROR_INVAL;
-
-	if ((bit_count != 16) && (bit_count != 18) && (bit_count != 20) &&
-	    (bit_count != 24))
-		return EC_ERROR_INVAL;
-
-	/* Set the parameters. */
-	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT,
-			(bit_count - 1));
-
-	if (trigger == WOV_I2S_SAMPLED_1_AFTER_0)
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num),
-			  NPCX_WOV_I2S_CNTL_I2S_TRIG);
-	else
-		SET_BIT(NPCX_WOV_I2S_CNTL(channel_num),
-			NPCX_WOV_I2S_CNTL_I2S_TRIG);
-
-	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-		  start_delay);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Sets sampling rate.
- *
- * @param   samples_per_second - Valid sample rate.
- * @return  In case sample rate is valid return EC_SUCCESS othewise return
- *          error code.
- */
-int wov_set_sample_rate(uint32_t samples_per_second)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	switch (samples_per_second) {
-	case 8000:
-	case 12000:
-	case 16000:
-	case 24000:
-	case 32000:
-	case 48000:
-		wov_conf.sample_per_sec = samples_per_second;
-		return EC_SUCCESS;
-	default:
-		return EC_ERROR_INVAL;
-	}
-}
-
-/**
- * Gets sampling rate.
- *
- * @param   None
- * @return  the current sampling rate.
- */
-uint32_t wov_get_sample_rate(void)
-{
-	return wov_conf.sample_per_sec;
-}
-
-/**
- * Sets sampling depth.
- *
- * @param   bits_num - Valid sample depth in bits.
- * @return  In case sample depth is valid return EC_SUCCESS othewise return
- *          error code.
- */
-int wov_set_sample_depth(int bits_num)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	if ((bits_num != 16) && (bits_num != 18) &&
-		(bits_num != 20) && (bits_num != 24))
-		return EC_ERROR_INVAL;
-
-	wov_conf.bit_depth = bits_num;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets sampling depth.
- *
- * @param   None.
- * @return  sample depth in bits.
- */
-int wov_get_sample_depth(void)
-{
-	return wov_conf.bit_depth;
-}
-
-/**
- * Sets microphone source.
- *
- * @param   mic_src - Valid microphone source
- * @return  return EC_SUCCESS if mic source valid othewise return error code.
- */
-int wov_set_mic_source(enum wov_mic_source mic_src)
-{
-	wov_conf.mic_src = mic_src;
-
-	return wov_set_mic_source_l();
-}
-
-/**
- * Gets microphone source.
- *
- * @param   None.
- * @return  sample depth in bits.
- */
-enum wov_mic_source wov_get_mic_source(void)
-{
-	return wov_conf.mic_src;
-}
-
-/**
- * Mutes the WoV.
- *
- * @param   enable  - enabled flag, 1 means enable
- * @return  None
- */
-void wov_mute(int enable)
-{
-	if (enable)
-		SET_BIT(NPCX_APM_CR_ADC, NPCX_APM_CR_ADC_ADC_SOFT_MUTE);
-	else
-		CLEAR_BIT(NPCX_APM_CR_ADC, NPCX_APM_CR_ADC_ADC_SOFT_MUTE);
-}
-
-/**
- * Sets gain
- *
- * @param   left_chan_gain  - Left channel gain.
- * @param   right_chan_gain - Right channel gain
- * @return  None
- */
-void wov_set_gain(int left_chan_gain, int right_chan_gain)
-{
-	wov_conf.left_chan_gain = left_chan_gain;
-	wov_conf.right_chan_gain = right_chan_gain;
-
-	(void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
-				left_chan_gain, right_chan_gain);
-}
-
-/**
- * Gets gain values
- *
- * @param   left_chan_gain  - address of left channel gain response.
- * @param   right_chan_gain - address of right channel gain response.
- * @return  None
- */
-void wov_get_gain(int *left_chan_gain, int *right_chan_gain)
-{
-	*left_chan_gain = wov_conf.left_chan_gain;
-	*right_chan_gain = wov_conf.right_chan_gain;
-}
-
-/**
- * Enables/Disables ADC.
- *
- * @param   enable - enabled flag, 1 means enable
- * @return  None
- */
-void wov_enable_agc(int enable)
-{
-	apm_auto_gain_cntrl_enable(enable);
-}
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param stereo                - Stereo enabled flag, 1 means enable.
- * @param target                - Target output level of the ADC.
- * @param noise_gate_threshold  - Noise Gate system select. 1 means enable.
- * @param hold_time             - Hold time before starting AGC adjustment to
- *                                the TARGET value.
- * @param attack_time           - Attack time - gain ramp down.
- * @param decay_time            - Decay time - gain ramp up.
- * @param max_applied_gain      - Maximum Gain Value to apply to the ADC path.
- * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-				int noise_gate_threshold, uint8_t hold_time,
-				uint16_t attack_time, uint16_t decay_time,
-				float max_applied_gain, float min_applied_gain)
-{
-	int target_code;
-	int ngth_code;
-	int attack_time_code;
-	int decay_time_code;
-	int max_applied_gain_code;
-	int min_applied_gain_code;
-	enum ec_error_list ret_code;
-	struct apm_auto_gain_config gain_cfg;
-
-	for (target_code = 0; target_code < 16; target_code++) {
-		if (((float)target_code * (-1.5)) == target)
-			break;
-	}
-	if (target_code == 16)
-		return EC_ERROR_INVAL;
-
-	if (noise_gate_threshold == 0)
-		ngth_code = 0;
-	else {
-		for (ngth_code = 0; ngth_code <= 0x07; ngth_code++) {
-			if ((-68 + ngth_code * 6) == noise_gate_threshold)
-				break;
-		}
-		if (ngth_code * 6 > 42)
-			return EC_ERROR_INVAL;
-	}
-
-	if (hold_time > 15)
-		return EC_ERROR_INVAL;
-
-	for (attack_time_code = 0; attack_time_code <= 0x0F;
-			attack_time_code++) {
-		if (((attack_time_code + 1) * 32) == attack_time)
-			break;
-	}
-	if (attack_time_code > 0x0F)
-		return EC_ERROR_INVAL;
-
-	for (decay_time_code = 0; decay_time_code <= 0x0F; decay_time_code++) {
-		if (((decay_time_code + 1) * 32) == decay_time)
-			break;
-	}
-	if (decay_time_code > 0x0F)
-		return EC_ERROR_INVAL;
-
-	for (max_applied_gain_code = 0; max_applied_gain_code < 16;
-			max_applied_gain_code++) {
-		if ((max_applied_gain_code * 1.5) == max_applied_gain)
-			break;
-	}
-	if (max_applied_gain_code == 16) {
-		for (max_applied_gain_code = 18; max_applied_gain_code < 32;
-				max_applied_gain_code++) {
-			if (((max_applied_gain_code * 1.5) - 4) ==
-					max_applied_gain)
-				break;
-		}
-	}
-	if (max_applied_gain_code >= 32)
-		return EC_ERROR_INVAL;
-
-	for (min_applied_gain_code = 0; min_applied_gain_code < 16;
-			min_applied_gain_code++) {
-		if ((min_applied_gain_code * 1.5) == min_applied_gain)
-			break;
-	}
-	if (min_applied_gain_code == 16) {
-		for (min_applied_gain_code = 18; min_applied_gain_code < 32;
-				min_applied_gain_code++) {
-			if (((min_applied_gain_code * 1.5) - 4) ==
-					min_applied_gain)
-				break;
-		}
-	}
-	if (min_applied_gain_code > 32)
-		return EC_ERROR_INVAL;
-
-	gain_cfg.stereo_enable = stereo,
-	gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code;
-	gain_cfg.nois_gate_en = (noise_gate_threshold != 0);
-	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code;
-	gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time;
-	gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code;
-	gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code;
-	gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code;
-	gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code;
-
-	ret_code = apm_adc_auto_gain_config(&gain_cfg);
-
-	return ret_code;
-}
-
-/**
- * Sets VAD sensitivity.
- *
- * @param   sensitivity_db - VAD sensitivity in db.
- * @return  None
- */
-int wov_set_vad_sensitivity(int sensitivity_db)
-{
-
-	if ((sensitivity_db < 0) || (sensitivity_db > 31))
-		return EC_ERROR_INVAL;
-
-	wov_conf.sensitivity_db = sensitivity_db;
-
-	apm_set_vad_sensitivity(sensitivity_db);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Gets VAD sensitivity.
- *
- * @param   None.
- * @return  VAD sensitivity in db
- */
-int wov_get_vad_sensitivity(void)
-{
-	return wov_conf.sensitivity_db;
-}
-
-/**
- * Configure I2S bus format. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   format    - one of the following: I2S mode, Right Justified mode,
- *                      Left Justified mode, PCM A Audio, PCM B Audio and
- *                      Time Division Multiplexing
- * @return  EC error code.
- */
-void wov_set_i2s_fmt(enum wov_dai_format format)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return;
-
-	wov_conf.dai_format = format;
-}
-
-/**
- * Configure I2S bus clock. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   i2s_clock - I2S clock frequency in Hz (needed in order to
- *                      configure the internal PLL for 12MHz)
- * @return  EC error code.
- */
-void wov_set_i2s_bclk(uint32_t i2s_clock)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return;
-
-	wov_conf.i2s_clock = i2s_clock;
-}
-
-/**
- * Configure I2S bus. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   ch0_delay - 0 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 0 (left channel)
- * @param   ch1_delay - -1 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 1 (right channel).
- *                      If channel 1 is not used set this field to -1.
- *
- * @param   flags     -  WOV_TDM_ADJACENT_TO_CH0 = BIT(0).  There is a
- *                       channel adjacent to channel 0, so float SDAT when
- *                       driving the last bit (LSB) of the channel during the
- *                       second half of the clock cycle to avoid bus contention.
- *
- *                       WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
- *                       adjacent to channel 1.
- *
- * @return  EC error code.
- */
-enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags)
-{
-	if (wov_conf.mode != WOV_MODE_OFF)
-		return EC_ERROR_INVALID_CONFIG;
-
-	if ((ch0_delay < 0) || (ch0_delay > 496) ||
-		(ch1_delay < -1) || (ch1_delay > 496))
-		return EC_ERROR_INVAL;
-
-	wov_conf.i2s_start_delay_0 = ch0_delay;
-	wov_conf.i2s_start_delay_1 = ch1_delay;
-
-	SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch0_delay);
-
-	if (ch1_delay == -1)
-		wov_i2s_channel1_disable(1);
-	else {
-		wov_i2s_channel1_disable(0);
-		SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch1_delay);
-	}
-
-	if (flags & 0x0001)
-		SET_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-
-	if (flags & 0x0002)
-		SET_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-	else
-		CLEAR_BIT(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_LBHIZ);
-
-	/* I2S should be reset in order I2S interface to function correctly. */
-	wov_i2s_fifo_reset();
-
-	return EC_SUCCESS;
-}
-
-static void wov_system_init(void)
-{
-	/* Set WoV module to be operational. */
-	clock_enable_peripheral(CGC_OFFSET_WOV, CGC_WOV_MASK,
-				CGC_MODE_RUN | CGC_MODE_SLEEP);
-	/* Configure pins from GPIOs to WOV */
-	gpio_config_module(MODULE_WOV, 1);
-	wov_init();
-
-	task_enable_irq(NPCX_IRQ_WOV);
-
-	CPRINTS("WoV init done");
-}
-DECLARE_HOOK(HOOK_INIT, wov_system_init, HOOK_PRIO_DEFAULT);
-
-void wov_handle_event(enum wov_events event)
-{
-	if (event == WOV_EVENT_DATA_READY) {
-		CPRINTS("ram data ready and stop ram capture");
-		/* just capture one times on RAM*/
-		wov_stop_ram_capture();
-	}
-	if (event == WOV_EVENT_VAD)
-		CPRINTS("got vad");
-	if (event == WOV_EVENT_ERROR_CORE_FIFO_OVERRUN)
-		CPRINTS("error: cfifo overrun");
-}
-
-#ifdef DEBUG_AUDIO_CODEC
-static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
-
-/* voice data 16Khz 2ch 16bit 1s */
-static int command_wov(int argc, char **argv)
-{
-	static int bit_clk;
-	static enum wov_dai_format i2s_fmt;
-
-	if (argc == 2) {
-		if (strcasecmp(argv[1], "init") == 0) {
-			wov_system_init();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgget") == 0) {
-			CPRINTS("mode:%d", wov_get_mode());
-			CPRINTS("sample rate:%d", wov_get_sample_rate());
-			CPRINTS("sample bits:%d", wov_get_sample_depth());
-			CPRINTS("mic source:%d", wov_get_mic_source());
-			CPRINTS("vad sensitivity :%d",
-				wov_get_vad_sensitivity());
-			return EC_SUCCESS;
-		}
-		/* Start to capature voice data and store in RAM buffer */
-		if (strcasecmp(argv[1], "capram") == 0) {
-			if (wov_set_buffer((uint32_t *)voice_buffer,
-				sizeof(voice_buffer) / sizeof(uint32_t))
-					== EC_SUCCESS) {
-				CPRINTS("Start RAM Catpure...");
-				wov_start_ram_capture();
-				return EC_SUCCESS;
-			}
-			CPRINTS("Init fail: voice buffer size");
-			return EC_ERROR_INVAL;
-		}
-	} else if (argc == 3) {
-		if (strcasecmp(argv[1], "cfgsrc") == 0) {
-			if (strcasecmp(argv[2], "mono") == 0)
-				wov_set_mic_source(WOV_SRC_MONO);
-			else if (strcasecmp(argv[2], "stereo") == 0)
-				wov_set_mic_source(WOV_SRC_STEREO);
-			else if (strcasecmp(argv[2], "left") == 0)
-				wov_set_mic_source(WOV_SRC_LEFT);
-			else if (strcasecmp(argv[2], "right") == 0)
-				wov_set_mic_source(WOV_SRC_RIGHT);
-			else
-				return EC_ERROR_INVAL;
-
-			wov_i2s_fifo_reset();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgbit") == 0) {
-			int bits;
-
-			bits = atoi(argv[2]);
-			if ((bits == 16) || (bits == 18) || (bits == 20) ||
-			    (bits == 24)) {
-				return wov_set_sample_depth(bits);
-			}
-		}
-		if (strcasecmp(argv[1], "cfgsfs") == 0) {
-			int fs;
-
-			fs = atoi(argv[2]);
-			return wov_set_sample_rate(fs);
-		}
-		if (strcasecmp(argv[1], "cfgbck") == 0) {
-			int fs;
-
-			fs = wov_get_sample_rate();
-			if (strcasecmp(argv[2], "32fs") == 0)
-				bit_clk = fs * 32;
-			else if (strcasecmp(argv[2], "48fs") == 0)
-				bit_clk = fs * 48;
-			else if (strcasecmp(argv[2], "64fs") == 0)
-				bit_clk = fs * 64;
-			else if (strcasecmp(argv[2], "128fs") == 0)
-				bit_clk = fs * 128;
-			else if (strcasecmp(argv[2], "256fs") == 0)
-				bit_clk = fs * 256;
-			else
-				return EC_ERROR_INVAL;
-
-			wov_set_i2s_fmt(i2s_fmt);
-			wov_set_i2s_bclk(bit_clk);
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgfmt") == 0) {
-			if (strcasecmp(argv[2], "i2s") == 0)
-				i2s_fmt = WOV_DAI_FMT_I2S;
-			else if (strcasecmp(argv[2], "right") == 0)
-				i2s_fmt = WOV_DAI_FMT_RIGHT_J;
-			else if (strcasecmp(argv[2], "left") == 0)
-				i2s_fmt = WOV_DAI_FMT_LEFT_J;
-			else if (strcasecmp(argv[2], "pcma") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_A;
-			else if (strcasecmp(argv[2], "pcmb") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_B;
-			else if (strcasecmp(argv[2], "tdm") == 0)
-				i2s_fmt = WOV_DAI_FMT_PCM_TDM;
-			else
-				return EC_ERROR_INVAL;
-
-			wov_set_i2s_fmt(i2s_fmt);
-			wov_set_i2s_bclk(bit_clk);
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckV") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_vad_dmic_rate(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckR") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_adc_ram_dmic_config(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "cfgdckI") == 0) {
-			if (strcasecmp(argv[2], "1.0") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_1_0);
-			else if (strcasecmp(argv[2], "1.2") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_1_2);
-			else if (strcasecmp(argv[2], "2.4") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_2_4);
-			else if (strcasecmp(argv[2], "3.0") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_3_0);
-			else if (strcasecmp(argv[2], "0.75") == 0)
-				apm_set_adc_i2s_dmic_config(APM_DMIC_RATE_0_75);
-			else
-				return EC_ERROR_INVAL;
-			return EC_SUCCESS;
-		}
-
-		if (strcasecmp(argv[1], "cfgmod") == 0) {
-			if (strcasecmp(argv[2], "off") == 0) {
-				wov_set_mode(WOV_MODE_OFF);
-				wov_stop_ram_capture();
-			} else if (strcasecmp(argv[2], "vad") == 0) {
-				wov_set_mode(WOV_MODE_VAD);
-			} else if (strcasecmp(argv[2], "ram") == 0) {
-				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
-					wov_set_mode(WOV_MODE_RAM);
-				else
-					return EC_ERROR_INVAL;
-			} else if (strcasecmp(argv[2], "i2s") == 0) {
-				wov_set_mode(WOV_MODE_I2S);
-			} else if (strcasecmp(argv[2], "rami2s") == 0) {
-				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
-					wov_set_mode(WOV_MODE_RAM_AND_I2S);
-				else
-					return EC_ERROR_INVAL;
-			} else {
-				return EC_ERROR_INVAL;
-			}
-			wov_i2s_fifo_reset();
-			return EC_SUCCESS;
-		}
-		if (strcasecmp(argv[1], "mute") == 0) {
-			if (strcasecmp(argv[2], "enable") == 0) {
-				wov_mute(1);
-				return EC_SUCCESS;
-			}
-			if (strcasecmp(argv[2], "disable") == 0) {
-				wov_mute(0);
-				return EC_SUCCESS;
-			}
-		}
-		if (strcasecmp(argv[1], "fmul2") == 0) {
-			if (strcasecmp(argv[2], "enable") == 0) {
-				CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-				return EC_SUCCESS;
-			}
-			if (strcasecmp(argv[2], "disable") == 0) {
-				SET_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
-				return EC_SUCCESS;
-			}
-		}
-		if (strcasecmp(argv[1], "vadsens") == 0)
-			return wov_set_vad_sensitivity(atoi(argv[2]));
-
-		if (strcasecmp(argv[1], "gain") == 0) {
-			wov_set_gain(atoi(argv[2]), atoi(argv[2]));
-			return EC_SUCCESS;
-		}
-	} else if (argc == 5) {
-		if (strcasecmp(argv[1], "cfgtdm") == 0) {
-			int delay0, delay1;
-			uint32_t flags;
-
-			delay0 = atoi(argv[2]);
-			delay1 = atoi(argv[3]);
-			flags = atoi(argv[4]);
-			if ((delay0 > 496) || (delay1 > 496) || (flags > 3) ||
-			    (delay0 < 0) || (delay1 < 0)) {
-				return EC_ERROR_INVAL;
-			}
-			wov_set_i2s_tdm_config(delay0, delay1, flags);
-			return EC_SUCCESS;
-		}
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-DECLARE_CONSOLE_COMMAND(wov, command_wov,
-		"init\n"
-		"mute <enable|disable>\n"
-		"capram\n"
-		"cfgsrc <mono|stereo|left|right>\n"
-		"cfgbit <16|18|20|24>\n"
-		"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
-		"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
-		"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
-		"cfgmod <off|vad|ram|i2s|rami2s>\n"
-		"cfgtdm [0~496 0~496 0~3]>\n"
-		"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgget\n"
-		"fmul2 <enable|disable>\n"
-		"vadsens <0~31>\n"
-		"gain <0~31>",
-		"wov configuration");
-#endif
diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h
deleted file mode 100644
index dce534c501..0000000000
--- a/chip/npcx/wov_chip.h
+++ /dev/null
@@ -1,658 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_WOV_CHIP_H
-#define __CROS_EC_WOV_CHIP_H
-
-#include "common.h"
-
-/* FMUL2 clock Frequency. */
-enum fmul2_clk_freq {
-	FMUL2_48_MHZ = 0, /* Default */
-	FMUL2_24_MHZ
-};
-
-enum fmul2_clk_divider {
-	FMUL2_CLK_NO_DIVIDER = 0x00,
-	FMUL2_CLK_DIVIDER_BY_2 = 0x01,
-	FMUL2_CLK_DIVIDER_BY_4 = 0x03, /* Default */
-	FMUL2_CLK_DIVIDER_BY_8 = 0x07
-};
-
-/* Microphone source. */
-enum wov_mic_source {
-	/* Only data from left mic. */
-	WOV_SRC_LEFT = 0,
-	/* Only data from right mic. */
-	WOV_SRC_RIGHT,
-	/* Both channels have the same data (average of left & right */
-	WOV_SRC_MONO,
-	/* Each channel has its own data. */
-	WOV_SRC_STEREO
-};
-
-/* Clock source for APM. */
-enum wov_clk_src_sel {
-	WOV_FMUL2_CLK_SRC = 0,
-	WOV_PLL_CLK_SRC = 1
-};
-
-/* FMUL clock division factore. */
-enum wov_fmul_div {
-	WOV_NODIV = 0,
-	WOV_DIV_BY_2,
-	WOV_DIV_BY_4, /* Default value */
-	WOV_DIV_BY_8
-};
-
-/* Lock state. */
-enum wov_lock_state {
-	WOV_UNLOCK = 0,
-	WOV_LOCK = 1
-};
-
-/* Reference clock source select. */
-enum wov_ref_clk_src_sel {
-	WOV_FREE_RUN_OSCILLATOR = 0,
-	WOV_CRYSTAL_OSCILLATOR = 1
-};
-
-/* PLL external divider select. */
-enum wov_ext_div_sel {
-	WOV_EXT_DIV_BINARY_CNT = 0,
-	WOV_EXT_DIV_LFSR_DIV = 1
-};
-
-/* FMUL output frequency. */
-enum wov_fmul_out_freq {
-	WOV_FMUL_OUT_FREQ_48_MHZ = 0,
-	WOV_FMUL_OUT_FREQ_49_MHZ = 1
-};
-
-/* Digital microphone clock divider select. */
-enum wov_dmic_clk_div_sel {
-	WOV_DMIC_DIV_DISABLE = 1,
-	WOV_DMIC_DIV_BY_2 = 2,
-	WOV_DMIC_DIV_BY_4 = 4
-};
-
-/* FIFO threshold. */
-enum wov_fifo_threshold {
-	WOV_FIFO_THRESHOLD_1_DATA_WORD = 0,
-	WOV_FIFO_THRESHOLD_2_DATA_WORDS = 1,
-	WOV_FIFO_THRESHOLD_4_DATA_WORDS = 2,
-	WOV_FIFO_THRESHOLD_8_DATA_WORDS = 4,
-	WOV_FIFO_THRESHOLD_16_DATA_WORDS = 8,
-	WOV_FIFO_THRESHOLD_32_DATA_WORDS = 16,
-	WOV_FIFO_THRESHOLD_40_DATA_WORDS = 20,
-	WOV_FIFO_THRESHOLD_64_DATA_WORDS = 32,
-	WOV_FIFO_THRESHOLD_80_DATA_WORDS = 40,
-	WOV_FIFO_THRESHOLD_96_DATA_WORDS = 48
-};
-
-/* FIFO DMA request select. */
-enum wov_fifo_dma_req_sel {
-	WOV_FIFO_DMA_DFLT_DMA_REQ_CONN = 0,
-	WOV_FIFO_DMA_DMA_REQ_CON_FIFO
-};
-
-/* FIFO operational state. */
-enum wov_fifo_oper_state {
-	WOV_FIFO_OPERATIONAL = 0,
-	WOV_FIFO_RESET, /* Default */
-};
-
-/* WoV interrupt index. */
-enum wov_interrupt_index {
-	WOV_VAD_INT_INDX,
-	WOV_VAD_WAKE_INDX,
-	WOV_CFIFO_NOT_EMPTY_INDX,
-	WOV_CFIFO_THRESHOLD_INT_INDX,
-	WOV_CFIFO_THRESHOLD_WAKE_INDX,
-	WOV_CFIFO_OVERRUN_INT_INDX,
-	WOV_I2SFIFO_OVERRUN_INT_INDX,
-	WOV_I2SFIFO_UNDERRUN_INT_INDX
-};
-
-/* FIFO DMA request selection. */
-enum wov_dma_req_sel {
-	WOV_DFLT_ESPI_DMA_REQ = 0,
-	WOV_FROM_FIFO_DMA_REQUEST
-};
-
-/* Core FIFO input select. */
-enum wov_core_fifo_in_sel {
-	WOV_CFIFO_IN_LEFT_CHAN_2_CONS_16_BITS = 0, /* Default */
-	WOV_CFIFO_IN_LEFT_RIGHT_CHAN_16_BITS,
-	WOV_CFIFO_IN_LEFT_CHAN_24_BITS,
-	WOV_CFIFO_IN_LEFT_RIGHT_CHAN_24_BITS
-};
-
-/* PLL external divider selector. */
-enum wov_pll_ext_div_sel {
-	WOV_PLL_EXT_DIV_BIN_CNT = 0,
-	WOV_PLL_EXT_DIV_LFSR
-};
-
-/* Code for events for call back function. */
-enum wov_events {
-	WOV_NO_EVENT = 0,
-	/*
-	 * Data is ready.
-	 * need to call to wov_set_buffer to update the buffer * pointer
-	 */
-	WOV_EVENT_DATA_READY = 1,
-	WOV_EVENT_VAD,		  /* Voice activity detected */
-
-	WOV_EVENT_ERROR_FIRST = 128,
-	WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128,
-	WOV_EVENT_ERROR_I2S_FIFO_UNDERRUN = 129,
-	WOV_EVENT_ERROR_I2S_FIFO_OVERRUN = 130,
-	WOV_EVENT_ERROR_LAST = 255,
-
-};
-
-/* WoV FIFO errors. */
-enum wov_fifo_errors {
-	WOV_FIFO_NO_ERROR = 0,
-	WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */
-	WOV_I2S_FIFO_OVERRUN = 2,  /* 3 : I2S FIFO is overrun.  */
-	WOV_I2S_FIFO_UNDERRUN = 3  /* 4 : I2S FIFO is underrun. */
-
-};
-
-/* Selects I2S test mode. */
-enum wov_test_mode { WOV_NORMAL_MODE = 0, WOV_TEST_MODE };
-
-/* PULL_UP/PULL_DOWN selection. */
-enum wov_pull_upd_down_sel { WOV_PULL_DOWN = 0, WOV_PULL_UP };
-
-/* I2S output data floating mode. */
-enum wov_floating_mode { WOV_FLOATING_DRIVEN = 0, WOV_FLOATING };
-
-/* Clock inverted mode. */
-enum wov_clk_inverted_mode { WOV_CLK_NORMAL = 0, WOV_CLK_INVERTED };
-
-enum wov_i2s_chan_trigger {
-	WOV_I2S_SAMPLED_1_AFTER_0 = 0,
-	WOV_I2S_SAMPLED_0_AFTER_1 = 1
-};
-
-/* APM modes. */
-enum wov_modes {
-	WOV_MODE_OFF = 1,
-	WOV_MODE_VAD,
-	WOV_MODE_RAM,
-	WOV_MODE_I2S,
-	WOV_MODE_RAM_AND_I2S
-};
-
-/* DAI format. */
-enum wov_dai_format {
-	WOV_DAI_FMT_I2S,     /* I2S mode			*/
-	WOV_DAI_FMT_RIGHT_J, /* Right Justified mode		*/
-	WOV_DAI_FMT_LEFT_J,  /* Left Justified mode		*/
-	WOV_DAI_FMT_PCM_A,   /* PCM A Audio			*/
-	WOV_DAI_FMT_PCM_B,   /* PCM B Audio			*/
-	WOV_DAI_FMT_PCM_TDM  /* Time Division Multiplexing	*/
-};
-
-struct wov_config {
-	enum wov_modes mode;
-	uint32_t sample_per_sec;
-	int bit_depth;
-	enum wov_mic_source mic_src;
-	int left_chan_gain;
-	int right_chan_gain;
-	uint16_t i2s_start_delay_0;
-	uint16_t i2s_start_delay_1;
-	uint32_t i2s_clock;
-	enum wov_dai_format dai_format;
-	int sensitivity_db;
-};
-
-extern struct wov_config wov_conf;
-
-/**
- * Set FMUL2 clock divider.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_set_clk_divider(enum fmul2_clk_divider clk_div);
-
-/**
- * WoV Call back function decleration.
- *
- * @param   event - the event that cause the call to the callback
- *		    function.
- *
- * @return  None
- */
-typedef void (*wov_call_back_t)(enum wov_events);
-
-/*
- * WoV macros.
- */
-
-/* MACROs that set fields of the Clock Control Register structure. */
-#define WOV_APM_CLK_SRC_FMUL2(reg_val) reg_val.clk_sel = 0
-#define WOV_APM_CLK_SRC_PLL(reg_val) reg_val.clk_sel = 1
-#define WOV_APM_GET_CLK_SRC(reg_val) (reg_val.clk_sel)
-
-/* Core FIFO threshold. */
-#define WOV_GET_CORE_FIFO_THRESHOLD WOV_GET_FIFO_INT_THRESHOLD
-
-/******************************************************************************
- *
- * WoV APIs
- *
- ******************************************************************************/
-
-/**
- * Initiates WoV.
- *
- * @param	callback	 - Pointer to callback function.
- *
- * @return	None
- */
-void wov_init(void);
-
-/**
- * Sets WoV stage
- *
- * @param	wov_mode - WoV stage (Table 38)
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_mode(enum wov_modes wov_mode);
-
-/**
- * Gets WoV mode
- *
- * @param	None
- * @return	WoV mode
- */
-enum wov_modes wov_get_mode(void);
-
-/**
- * Configure WoV.
- *
- * @param	samples_per_second - Valid sample rate.
- * @return	In case sample rate is valid return EC_SUCCESS othewise return
- * error code.
- */
-int wov_set_sample_rate(uint32_t samples_per_second);
-
-/**
- * Gets sampling rate.
- *
- * @param	None
- * @return	the current sampling rate.
- */
-uint32_t wov_get_sample_rate(void);
-
-/**
- * Sets sampling depth.
- *
- * @param	bits_num - Valid sample depth in bits.
- * @return	In case sample depth is valid return EC_SUCCESS othewise return
- * error code.
- */
-int wov_set_sample_depth(int bits_num);
-
-/**
- * Gets sampling depth.
- *
- * @param	None.
- * @return	sample depth in bits.
- */
-int wov_get_sample_depth(void);
-
-/**
- * Sets microphone source.
- *
- * @param	mic_src - Valid microphone source
- * @return	return EC_SUCCESS if mic source valid othewise
- * return error code.
- */
-int wov_set_mic_source(enum wov_mic_source mic_src);
-
-/**
- * Gets microphone source.
- *
- * @param	None.
- * @return	sample depth in bits.
- */
-enum wov_mic_source wov_get_mic_source(void);
-
-/**
- * Mutes the WoV.
- *
- * @param	enable	- enabled flag, true means enable
- * @return	None
- */
-void wov_mute(int enable);
-
-/**
- * Gets gain values
- *
- * @param   left_chan_gain  - address of left channel gain response.
- * @param   right_chan_gain - address of right channel gain response.
- * @return  None
- */
-void wov_get_gain(int *left_chan_gain, int *right_chan_gain);
-
-/**
- * Sets gain
- *
- * @param		left_chan_gain	- Left channel gain.
- * @param		right_chan_gain - Right channel gain
- * @return	None
- */
-void wov_set_gain(int left_chan_gain, int right_chan_gain);
-
-/**
- * Enables/Disables ADC.
- *
- * @param	enable - enabled flag, true means enable
- * @return	None
- */
-void wov_enable_agc(int enable);
-
-/**
- * Enables/Disables the automatic gain.
- *
- * @param stereo                - Stereo enabled flag, 1 means enable.
- * @param target                - Target output level of the ADC.
- * @param noise_gate_threshold  - Noise Gate system select. 1 means enable.
- * @param hold_time             - Hold time before starting AGC adjustment to
- *                                the TARGET value.
- * @param attack_time           - Attack time - gain ramp down.
- * @param decay_time            - Decay time - gain ramp up.
- * @param max_applied_gain      - Maximum Gain Value to apply to the ADC path.
- * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-		int noise_gate_threshold, uint8_t hold_time,
-		uint16_t attack_time, uint16_t decay_time,
-		float max_applied_gain, float min_applied_gain);
-
-/**
- * Sets VAD sensitivity.
- *
- * @param	sensitivity_db - VAD sensitivity in db.
- * @return	None
- */
-int wov_set_vad_sensitivity(int sensitivity_db);
-
-/**
- * Gets VAD sensitivity.
- *
- * @param	None.
- * @return	VAD sensitivity in db
- */
-int wov_get_vad_sensitivity(void);
-
-/**
- * Configure I2S bus format. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   format    - one of the following: I2S mode, Right Justified mode,
- *                      Left Justified mode, PCM A Audio, PCM B Audio and
- *                      Time Division Multiplexing
- * @return  EC error code.
- */
-void wov_set_i2s_fmt(enum wov_dai_format format);
-
-/**
- * Configure I2S bus clock. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   i2s_clock - I2S clock frequency in Hz (needed in order to
- *                      configure the internal PLL for 12MHz)
- * @return  EC error code.
- */
-void wov_set_i2s_bclk(uint32_t i2s_clock);
-
-/**
- * Configure I2S bus. (Sample rate and size are determined via common
- * config functions.)
- *
- * @param   ch0_delay - 0 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 0 (left channel)
- * @param   ch1_delay - -1 to 496.  Defines the delay from the SYNC till the
- *                      first bit (MSB) of channel 1 (right channel).
- *                      If channel 1 is not used set this field to -1.
- *
- * @param   flags     -  WOV_TDM_ADJACENT_TO_CH0 = BIT(0).  There is a
- *                       channel adjacent to channel 0, so float SDAT when
- *                       driving the last bit (LSB) of the channel during the
- *                       second half of the clock cycle to avoid bus contention.
- *
- *                       WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
- *                       adjacent to channel 1.
- *
- * @return  EC error code.
- */
-enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags);
-
-/**
- * Configure FMUL2 clock tunning.
- *
- * @param   None
- * @return  None
- */
-void wov_fmul2_conf_tuning(void);
-
-/**
- * Configure DMIC clock.
- *
- * @param   enable          - DMIC enabled , true means enable
- * @param   clk_div         - DMIC clock division factor (disable, divide by 2
- *			      divide by 4)
- * @return  None
- */
-void wov_dmic_clk_config(int enable, enum wov_dmic_clk_div_sel clk_div);
-
-/**
- * FMUL2 clock control configuration.
- *
- * @param clk_src - select between FMUL2 (WOV_FMUL2_CLK_SRC) and
- *		    PLL (WOV_PLL_CLK_SRC)
- * @return	None
- */
-extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src);
-
-/**
- * Configure PLL clock.
- *
- * @param   ext_div_sel         - PLL external divider selector.
- * @param   div_factor          - When ext_div_sel is WOV_PLL_EXT_DIV_BIN_CNT
- *                                then it is the 4 LSBits of this field,
- *                                otherwise this field is an index to
- *                                PLL External Divider Load Values table.
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor);
-
-/**
- * PLL power down.
- *
- * @param enable - true power down the PLL or false PLL operating
- * @return	None
- */
-void wov_pll_enable(int enable);
-
-/**
- * Configures PLL clock dividers..
- *
- * @param   out_div_1    - PLL output divider #1, valid values 1-7
- * @param   out_div_2    - PLL output divider #2, valid values 1-7
- * @param   feedback_div - PLL feadback divider (Default is 375 decimal)
- * @param   in_div       - PLL input divider
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-			uint32_t out_div_2,
-			uint32_t feedback_div,
-			uint32_t in_div);
-
-/**
- * Enables/Disables WoV interrupt.
- *
- * @param   int_index - Interrupt ID.
- * @param   enable    - enabled flag, 1 means enable
- *
- * @return  None.
- */
-void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable);
-
-/**
- * Sets core FIFO threshold.
- *
- * @param   in_sel    - Core FIFO input select
- * @param   threshold - Core FIFO threshold
- *
- * @return  None
- */
-void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-			enum wov_fifo_threshold threshold);
-
-/**
- * Start the actual capturing of the Voice data to the RAM.
- * Note that the pointer to the RAM buffer must be precisely
- * set by calling wov_set_buffer();
- *
- * @param	None
- *
- * @return	None
- */
-void wov_start_ram_capture(void);
-
-/**
- * Stop the capturing of the Voice data to the RAM.
- *
- * @param	none
- *
- * @return  None
- */
-void wov_stop_ram_capture(void);
-
-/**
- * Rests the Core FIFO.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_core_fifo_reset(void);
-
-/**
- * Rests the I2S FIFO.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_i2s_fifo_reset(void);
-
-/**
- * Start the capturing of the Voice data via I2S.
- *
- * @param	None
- *
- * @return	None
- */
-void wov_start_i2s_capture(void);
-
-/**
- * Stop the capturing of the Voice data via I2S.
- *
- * @param	none
- *
- * @return  None
- */
-void wov_stop_i2s_capture(void);
-
-/**
- * Reads data from the core fifo.
- *
- * @param	num_elements - Number of elements (Dword) to read.
- *
- * @return	None
- */
-void wov_cfifo_read_handler(uint32_t num_elements);
-
-/**
- * Sets data buffer for reading from core FIFO
- *
- * @param  buff          - Pointer to the read buffer, buffer must be 32 bits
- *                         aligned.
- * @param  size_in_words - Size must be a multiple of CONFIG_WOV_THRESHOLD_WORDS
- *                         (defaulte = 80 words)
- *
- * @return  None
- *
- *  Note - When the data buffer will be full the FW will be notifyed
- *         about it, and the FW will need to recall to this function.
- */
-int wov_set_buffer(uint32_t *buff, int size_in_words);
-
-/**
- * Resets the APM.
- *
- * @param enable - enabled flag, true or false
- * @return	None
- */
-void wov_apm_active(int enable);
-
-void wov_handle_event(enum wov_events event);
-
-/**
- * I2S golobal configuration
- *
- * @param   i2s_hiz_data  - Defines when the I2S data output is floating.
- * @param   i2s_hiz       - Defines if the I2S data output is always floating.
- * @param   clk_invert    - Defines the I2S bit clock edge sensitivity
- * @param   out_pull_en   - Enable a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   out_pull_mode - Select a pull-up or a pull-down resistor on
- *                          I2S output
- * @param   in_pull_en    - Enable a pull-up or a pull-down resistor on
- *                          I2S input
- * @param   in_pull_mode  - Select a pull-up or a pull-down resistor on
- *                          I2S intput
- * @param   test_mode     - Selects I2S test mode
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode);
-
-/**
- * I2S channel configuration
- *
- * @param  channel_num     - I2S channel number, 0 or 1.
- * @param  bit_count       - I2S channel bit count.
- * @param  trigger         - Define the I2S chanel trigger 1->0 or 0->1
- * @param  start_delay     - Defines the delay from the trigger defined for
- *                           the channel till the first bit (MSB) of the data.
- *
- * @return  EC_ERROR_INVAL or EC_SUCCESS
- */
-enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-			uint32_t bit_count, enum wov_i2s_chan_trigger trigger,
-			int32_t start_delay);
-
-#endif /* __CROS_EC_WOV_CHIP_H */
diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c
deleted file mode 100644
index 89eb117efd..0000000000
--- a/chip/nrf51/bluetooth_le.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h"
-#include "include/bluetooth_le.h"
-#include "console.h"
-#include "ppi.h"
-#include "radio.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_LE, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
-
-static void ble2nrf_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p)
-{
-	if (ble_p->header_type_adv) {
-		radio_p->s0 = ble_p->header.adv.type & 0xf;
-		radio_p->s0 |= (ble_p->header.adv.txaddr ?
-			1 << BLE_ADV_HEADER_TXADD_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.adv.rxaddr ?
-			1 << BLE_ADV_HEADER_RXADD_SHIFT : 0);
-		radio_p->length = ble_p->header.adv.length & 0x3f; /* 6 bits */
-	} else {
-		radio_p->s0 = ble_p->header.data.llid & 0x3;
-		radio_p->s0 |= (ble_p->header.data.nesn ?
-			1 << BLE_DATA_HEADER_NESN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.sn ?
-			1 << BLE_DATA_HEADER_SN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.md ?
-			1 << BLE_DATA_HEADER_MD_SHIFT : 0);
-		radio_p->length = ble_p->header.data.length & 0x1f; /* 5 bits */
-	}
-
-	if (radio_p->length > 0)
-		memcpy(radio_p->payload, ble_p->payload, radio_p->length);
-}
-
-static void nrf2ble_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p, int type_adv)
-{
-	if (type_adv) {
-		ble_p->header_type_adv = 1;
-		ble_p->header.adv.type = radio_p->s0 & 0xf;
-		ble_p->header.adv.txaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0;
-		ble_p->header.adv.rxaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0;
-		/* Length check? 6-37 Bytes */
-		ble_p->header.adv.length = radio_p->length;
-	} else {
-		ble_p->header_type_adv = 0;
-		ble_p->header.data.llid = radio_p->s0 & 0x3;
-		ble_p->header.data.nesn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0;
-		ble_p->header.data.sn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0;
-		ble_p->header.data.md = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0;
-		/* Length check? 0-31 Bytes */
-		ble_p->header.data.length = radio_p->length;
-	}
-
-	if (radio_p->length > 0)
-		memcpy(ble_p->payload, radio_p->payload, radio_p->length);
-}
-
-struct ble_pdu adv_packet;
-struct nrf51_ble_packet_t on_air_packet;
-
-struct ble_pdu rcv_packet;
-
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return rv;
-	NRF51_RADIO_CRCCNF = 3 | NRF51_RADIO_CRCCNF_SKIP_ADDR; /* 3-byte CRC */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-
-	NRF51_RADIO_CRCINIT = crc_init_val;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	NRF51_RADIO_BASE0 = access_address << 8;
-	NRF51_RADIO_PREFIX0 = access_address >> 24;
-
-	if (access_address != BLE_ADV_ACCESS_ADDRESS)
-		CPRINTF("Initializing radio for data packet.\n");
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_ADV_DATA;
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_ADV_DATA;
-
-	return rv;
-
-}
-
-static struct nrf51_ble_packet_t tx_packet;
-
-static uint32_t tx_end, rsp_end;
-
-void ble_tx(struct ble_pdu *pdu)
-{
-	uint32_t timeout_time;
-
-	ble2nrf_packet(pdu, &tx_packet);
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	NRF51_RADIO_RXEN = 0;
-	NRF51_RADIO_TXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("ERROR DURING RADIO TX SETUP. TRY AGAIN.\n");
-			return;
-		}
-	}
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_END) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO DID NOT SHUT DOWN AFTER TX. "
-				"RECOMMEND REBOOT.\n");
-			return;
-		}
-	}
-	NRF51_RADIO_DISABLE = 1;
-}
-
-static struct nrf51_ble_packet_t rx_packet;
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv)
-{
-	uint32_t done;
-	uint32_t timeout_time;
-	int ppi_channel_requested;
-
-	/* Prevent illegal wait times */
-	if (timeout <= 0) {
-		NRF51_RADIO_DISABLE = 1;
-		return EC_ERROR_TIMEOUT;
-	}
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	/*
-	 * These shortcuts cause packet transmission 150 microseconds after
-	 * packet receive, as is the BTLE standard. See NRF51 manual:
-	 * section 17.1.12
-	 */
-	NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-			NRF51_RADIO_SHORTS_DISABLED_TXEN |
-			NRF51_RADIO_SHORTS_END_DISABLE;
-
-	/*
-	 * This creates a shortcut that marks the time
-	 * that the payload was received by the radio
-	 * in NRF51_TIMER_CC(0,1)
-	 */
-	ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1;
-	if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) {
-		NRF51_PPI_CHEN |= BIT(ppi_channel_requested);
-		NRF51_PPI_CHENSET |= BIT(ppi_channel_requested);
-	}
-
-
-	NRF51_RADIO_RXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO NOT SET UP IN TIME. TIMING OUT.\n");
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	timeout_time = get_time().val + timeout;
-	do {
-		if (get_time().val >= timeout_time) {
-			NRF51_RADIO_DISABLE = 1;
-			return EC_ERROR_TIMEOUT;
-		}
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	rsp_end = get_time().le.lo;
-
-	if (NRF51_RADIO_CRCSTATUS == 0) {
-		CPRINTF("INVALID CRC\n");
-		return EC_ERROR_CRC;
-	}
-
-	nrf2ble_packet(pdu, &rx_packet, adv);
-
-	/*
-	 * Throw error if radio not yet disabled. Something has
-	 * gone wrong. May be in an unexpected state.
-	 */
-	if (NRF51_RADIO_DISABLED != 1)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Allow list handling */
-int ble_radio_clear_allow_list(void)
-{
-	NRF51_RADIO_DACNF = 0;
-	return EC_SUCCESS;
-}
-
-int ble_radio_read_allow_list_size(uint8_t *ret_size)
-{
-	int i, size = 0;
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-
-	/* Count the bits that are set */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++)
-		if (dacnf & NRF51_RADIO_DACNF_ENA(i))
-			size++;
-
-	*ret_size = size;
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t rand)
-{
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-	int i;
-	uint32_t aligned;
-
-	/* Check for duplicates using ble_radio_remove_device? */
-
-	/* Find a free entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX &&
-		(dacnf & NRF51_RADIO_DACNF_ENA(i)); i++)
-		;
-
-	if (i == NRF51_RADIO_DACNF_MAX)
-		return EC_ERROR_OVERFLOW;
-
-	memcpy(&aligned, addr_ptr, 4);
-	NRF51_RADIO_DAB(i) = aligned;
-	memcpy(&aligned, addr_ptr + 4, 2);
-	NRF51_RADIO_DAP(i) = aligned;
-
-	NRF51_RADIO_DACNF = dacnf | NRF51_RADIO_DACNF_ENA(i) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0);
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t rand)
-{
-	int i, dacnf = NRF51_RADIO_DACNF;
-
-	/* Find a matching entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) {
-		uint32_t dab = NRF51_RADIO_DAB(i), dap = NRF51_RADIO_DAP(i);
-
-		if ((dacnf & NRF51_RADIO_DACNF_ENA(i)) && /* Enabled */
-		    /* Rand flag matches */
-		    (rand == ((dacnf & NRF51_RADIO_DACNF_TXADD(i)) != 0)) &&
-		    /* Address matches */
-		    (!memcmp(addr_ptr, &dab, 4)) &&
-		    (!memcmp(addr_ptr + 4, &dap, 2)))
-			break;
-	}
-
-	if (i == NRF51_RADIO_DACNF_MAX) /* Not found is successfully removed */
-		return EC_SUCCESS;
-
-	NRF51_RADIO_DACNF = dacnf & ~((NRF51_RADIO_DACNF_ENA(i)) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0));
-
-	return EC_SUCCESS;
-}
-
-
-int ble_adv_packet(struct ble_pdu *adv_packet, int chan)
-{
-	int done;
-	int rv;
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	ble_tx(adv_packet);
-
-	do {
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	tx_end = get_time().le.lo;
-
-	if (adv_packet->header.adv.type ==
-	    BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND)
-		return EC_SUCCESS;
-
-	rv = ble_rx(&rcv_packet, 16000, 1);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check for valid responses */
-	switch (rcv_packet.header.adv.type) {
-	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
-		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
-		/* Connections are only allowed for two types of advertising */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-		/* The InitAddr needs to match for Directed advertising */
-		if (adv_packet->header.adv.type ==
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-		    memcmp(&adv_packet->payload[BLUETOOTH_ADDR_OCTETS],
-			   &rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	default: /* Unhandled response packet */
-		return rv;
-	break;
-	}
-
-	dump_ble_packet(&rcv_packet);
-	CPRINTF("tx_end %u Response %u\n", tx_end, rsp_end);
-
-	return rv;
-}
-
-int ble_adv_event(struct ble_pdu *adv_packet)
-{
-	int chan;
-	int rv;
-
-	for (chan = 37; chan < 40; chan++) {
-		rv = ble_adv_packet(adv_packet, chan);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return rv;
-}
-
-static void fill_header(struct ble_pdu *adv, int type, int txaddr, int rxaddr)
-{
-	adv->header_type_adv = 1;
-	adv->header.adv.type = type;
-	adv->header.adv.txaddr = txaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.rxaddr = rxaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.length = 0;
-}
-
-static int fill_payload(uint8_t *payload, uint64_t addr, int name_length)
-{
-	uint8_t *curr;
-
-	curr = pack_adv_addr(payload, addr);
-	curr = pack_adv(curr, name_length, GAP_COMPLETE_NAME,
-		"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrs");
-	curr = pack_adv_int(curr, 2, GAP_APPEARANCE,
-			    GAP_APPEARANCE_HID_KEYBOARD);
-	curr = pack_adv_int(curr, 1, GAP_FLAGS,
-		GAP_FLAGS_LE_LIM_DISC | GAP_FLAGS_LE_NO_BR_EDR);
-	curr = pack_adv_int(curr, 2, GAP_COMP_16_BIT_UUID,
-			    GATT_SERVICE_HID_UUID);
-
-	return curr - payload;
-}
-
-static void fill_packet(struct ble_pdu *adv, uint64_t addr, int type,
-			int name_length)
-{
-	fill_header(adv, type, BLE_ADV_HEADER_RANDOM_ADDR,
-		    BLE_ADV_HEADER_PUBLIC_ADDR);
-
-	adv->header.adv.length = fill_payload(adv->payload, addr, name_length);
-}
-
-static int command_ble_adv(int argc, char **argv)
-{
-	int type, length, reps, interval;
-	uint64_t addr;
-	char *e;
-	int i;
-	int rv;
-
-	if (argc < 3 || argc > 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	type = strtoi(argv[1], &e, 0);
-	if (*e || type < 0 || (type > 2 && type != 6))
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 4) {
-		reps = strtoi(argv[3], &e, 0);
-		if (*e || reps < 0)
-			return EC_ERROR_PARAM3;
-	} else {
-		reps = 1;
-	}
-
-	if (argc >= 5) {
-		interval = strtoi(argv[4], &e, 0);
-		if (*e || interval < 0)
-			return EC_ERROR_PARAM4;
-	} else {
-		interval = 100000;
-	}
-
-	if (type == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && length != 12) {
-		length = 12;
-		CPRINTS("type DIRECT needs to have a length of 12");
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-
-		CPRINTS("ADV @%pP", &adv_packet);
-
-	((uint32_t *)&addr)[0] = 0xA3A2A1A0 | type;
-	((uint32_t *)&addr)[1] = BLE_RANDOM_ADDR_MSBS_STATIC << 8 | 0x5A4;
-
-		fill_packet(&adv_packet, addr, type, length);
-
-	for (i = 0; i < reps; i++) {
-		ble_adv_event(&adv_packet);
-		usleep(interval);
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_adv, command_ble_adv,
-			"type len [reps] [interval = 100000 (100ms)]",
-			"Send a BLE packet of type type of length len");
-
-static int command_ble_adv_scan(int argc, char **argv)
-{
-	int chan, packets, i;
-	int addr_lsbyte;
-	char *e;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	if (argc >= 3) {
-		packets = strtoi(argv[2], &e, 0);
-		if (*e || packets < 0)
-			return EC_ERROR_PARAM2;
-	} else {
-		packets = 1;
-	}
-
-	if (argc >= 4) {
-		addr_lsbyte = strtoi(argv[3], &e, 0);
-		if (*e || addr_lsbyte > 255)
-			return EC_ERROR_PARAM3;
-	} else {
-		addr_lsbyte = -1;
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	CPRINTS("ADV Listen");
-	if (addr_lsbyte != -1)
-		CPRINTS("filtered (%x)", addr_lsbyte);
-
-	for (i = 0; i < packets; i++) {
-		rv = ble_rx(&rcv_packet, 1000000, 1);
-
-		if (rv == EC_ERROR_TIMEOUT)
-			continue;
-
-		if (addr_lsbyte == -1 || rcv_packet.payload[0] == addr_lsbyte)
-			dump_ble_packet(&rcv_packet);
-	}
-
-	rv = radio_disable();
-
-	CPRINTS("on_air payload rcvd %pP", &rx_packet);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_scan, command_ble_adv_scan,
-			"chan [num] [addr0]",
-			"Scan for [num] BLE packets on channel chan");
-
diff --git a/chip/nrf51/bluetooth_le.h b/chip/nrf51/bluetooth_le.h
deleted file mode 100644
index dbb3bccd6e..0000000000
--- a/chip/nrf51/bluetooth_le.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __NRF51_BLUETOOTH_LE_H
-#define __NRF51_BLUETOOTH_LE_H
-
-#include "common.h"
-#include "include/bluetooth_le.h"
-
-#define NRF51_BLE_LENGTH_BITS 8
-#define NRF51_BLE_S0_BYTES    1
-#define NRF51_BLE_S1_BITS     0 /* no s1 field */
-
-#define BLE_ACCESS_ADDRESS_BYTES 4
-#define EXTRA_RECEIVE_BYTES      0
-#define BLE_ADV_WHITEN           1
-
-#define RADIO_SETUP_TIMEOUT 1000
-
-/* Data and Advertisements have the same PCNF values */
-#define NRF51_RADIO_PCNF0_ADV_DATA \
-			NRF51_RADIO_PCNF0_VAL(NRF51_BLE_LENGTH_BITS, \
-			NRF51_BLE_S0_BYTES, \
-			NRF51_BLE_S1_BITS)
-
-#define NRF51_RADIO_PCNF1_ADV_DATA \
-			NRF51_RADIO_PCNF1_VAL(BLE_MAX_ADV_PAYLOAD_OCTETS, \
-		    EXTRA_RECEIVE_BYTES, \
-		    BLE_ACCESS_ADDRESS_BYTES - 1, \
-		    BLE_ADV_WHITEN)
-
-struct nrf51_ble_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t payload[BLE_MAX_DATA_PAYLOAD_OCTETS];
-} __packed;
-
-struct nrf51_ble_config_t {
-	uint8_t channel;
-	uint8_t address;
-	uint32_t crc_init;
-};
-
-/* Initialize the nRF51 radio for BLE */
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val);
-
-/* Transmit pdu on the radio */
-void ble_tx(struct ble_pdu *pdu);
-
-/* Receive a packet into pdu if one comes before the timeout */
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv);
-
-/* Allow list handling */
-
-/* Clear the allow list */
-int ble_radio_clear_allow_list(void);
-
-/* Read the size of the allow list and assign it to ret_size */
-int ble_radio_read_allow_list_size(uint8_t *ret_size);
-
-/* Add the device with the address specified by addr_ptr and type */
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t type);
-
-/* Remove the device with the address specified by addr_ptr and type */
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t type);
-
-#endif  /* __NRF51_BLUETOOTH_LE_H */
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk
deleted file mode 100644
index 7a7a33d402..0000000000
--- a/chip/nrf51/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nRF51822 chip specific files build
-#
-
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-
-chip-y+=gpio.o system.o uart.o
-chip-y+=watchdog.o ppi.o
-
-chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o
-chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer.o clock.o
-chip-$(CONFIG_I2C)+=i2c.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/nrf51/clock.c b/chip/nrf51/clock.c
deleted file mode 100644
index fe56140175..0000000000
--- a/chip/nrf51/clock.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-void clock_init(void)
-{
-}
-
-int clock_get_freq(void)
-{
-	/* constant 16 MHz clock */
-	return 16000000;
-}
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
deleted file mode 100644
index f63fff0fe3..0000000000
--- a/chip/nrf51/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m0/config_core.h"
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 1024
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * --- chip variant settings ---
- */
-
-/* RAM mapping */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Flash mapping */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Not that much RAM, set to smaller */
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
-
diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c
deleted file mode 100644
index 53694b5a74..0000000000
--- a/chip/nrf51/gpio.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it.
- */
-
-static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT];
-static const struct gpio_info *gpio_int_port;
-
-volatile uint32_t * const nrf51_alt_funcs[] = {
-	/* UART */
-	&NRF51_UART_PSELRTS,
-	&NRF51_UART_PSELTXD,
-	&NRF51_UART_PSELCTS,
-	&NRF51_UART_PSELRXD,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI0_PSELSCK,
-	&NRF51_SPI0_PSELMOSI,
-	&NRF51_SPI0_PSELMISO,
-	/* TWI0 (I2C) */
-	&NRF51_TWI0_PSELSCL,
-	&NRF51_TWI0_PSELSDA,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI1_PSELSCK,
-	&NRF51_SPI1_PSELMOSI,
-	&NRF51_SPI1_PSELMISO,
-	/* TWI1 (I2C) */
-	&NRF51_TWI1_PSELSCL,
-	&NRF51_TWI1_PSELSDA,
-	/* SPIS1 (SPI SLAVE) */
-	&NRF51_SPIS1_PSELSCK,
-	&NRF51_SPIS1_PSELMISO,
-	&NRF51_SPIS1_PSELMOSI,
-	&NRF51_SPIS1_PSELCSN,
-	/* QDEC (ROTARY DECODER) */
-	&NRF51_QDEC_PSELLED,
-	&NRF51_QDEC_PSELA,
-	&NRF51_QDEC_PSELB,
-	/* LPCOMP (Low Power Comparator) */
-	&NRF51_LPCOMP_PSEL,
-};
-
-const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs);
-
-/* Make sure the function table and defines stay in sync */
-BUILD_ASSERT(ARRAY_SIZE(nrf51_alt_funcs) == NRF51_MAX_ALT_FUNCS &&
-	NRF51_MAX_ALT_FUNCS <= GPIO_ALT_FUNC_MAX);
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t val = 0;
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	if (flags & GPIO_OUTPUT)
-		val |= NRF51_PIN_CNF_DIR_OUTPUT;
-	else if (flags & GPIO_INPUT)
-		val |= NRF51_PIN_CNF_DIR_INPUT;
-
-	if (flags & GPIO_PULL_DOWN)
-		val |= NRF51_PIN_CNF_PULLDOWN;
-	else if (flags & GPIO_PULL_UP)
-		val |= NRF51_PIN_CNF_PULLUP;
-
-	/* TODO: Drive strength? H0D1? */
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= NRF51_PIN_CNF_DRIVE_S0D1;
-
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			NRF51_GPIO0_OUTSET = mask;
-		else if (flags & GPIO_LOW)
-			NRF51_GPIO0_OUTCLR = mask;
-	}
-
-	/* Interrupt levels */
-	if (flags & GPIO_INT_SHARED) {
-		/*
-		 * There are no shared edge-triggered interrupts;
-		 * they're either high or low.
-		 */
-		ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0);
-		ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL);
-		if (flags & GPIO_INT_F_LOW)
-			val |= NRF51_PIN_CNF_SENSE_LOW;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= NRF51_PIN_CNF_SENSE_HIGH;
-	}
-
-	NRF51_PIN_CNF(bit) = val;
-}
-
-
-static void gpio_init(void)
-{
-	task_enable_irq(NRF51_PERID_GPIOTE);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(NRF51_GPIO0_IN & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		NRF51_GPIO0_OUTSET = gpio_list[signal].mask;
-	else
-		NRF51_GPIO0_OUTCLR = gpio_list[signal].mask;
-}
-
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (NRF51_POWER_RESETREAS &
-			(NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */
-			 NRF51_POWER_RESETREAS_LPCOMP)) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	}
-
-	/* Initialize Interrupt configuration */
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++)
-		gpio_ints[i] = NULL;
-	gpio_int_port = NULL;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels again.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/*
- * NRF51 doesn't have an alternate function table.
- * Use the pin select registers in place of the function number.
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */
-	ASSERT(port == GPIO_0);
-	ASSERT((func >= GPIO_ALT_FUNC_DEFAULT && func < nrf51_alt_func_count) ||
-		func == GPIO_ALT_FUNC_NONE);
-
-	/* Remove the previous setting(s) */
-	if (func == GPIO_ALT_FUNC_NONE) {
-		int i;
-		for (i = 0; i < nrf51_alt_func_count; i++) {
-			if (*(nrf51_alt_funcs[i]) == bit)
-				*(nrf51_alt_funcs[i]) = 0xffffffff;
-		}
-	} else {
-		*(nrf51_alt_funcs[func]) = bit;
-	}
-}
-
-
-/*
- *  Enable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- *
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int pin;
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		int int_num, free_slot = -1;
-		uint32_t event_config = 0;
-
-		for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) {
-			if (gpio_ints[int_num] == g)
-				return EC_SUCCESS; /* This is already set up. */
-
-			if (gpio_ints[int_num] == NULL && free_slot == -1)
-				free_slot = int_num;
-		}
-
-		ASSERT(free_slot != -1);
-
-		gpio_ints[free_slot] = g;
-		pin = GPIO_MASK_TO_NUM(g->mask);
-		event_config = (pin << NRF51_GPIOTE_PSEL_POS) |
-			NRF51_GPIOTE_MODE_EVENT;
-
-		ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING));
-
-		/* RISING | FALLING = TOGGLE */
-		if (g->flags & GPIO_INT_F_RISING)
-			event_config |= NRF51_GPIOTE_POLARITY_LOTOHI;
-		if (g->flags & GPIO_INT_F_FALLING)
-			event_config |= NRF51_GPIOTE_POLARITY_HITOLO;
-
-		NRF51_GPIOTE_CONFIG(free_slot) = event_config;
-
-		/* Enable the IN[] interrupt. */
-		NRF51_GPIOTE_INTENSET = 1 << free_slot;
-
-	} else {
-		/* The first handler for the shared interrupt wins. */
-		if (gpio_int_port == NULL) {
-			gpio_int_port = g;
-
-			/* Enable the PORT interrupt. */
-			NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- *  Disable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- */
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	int i;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-			/* Remove matching handler. */
-			if (gpio_ints[i] == g) {
-				/* Disable the interrupt */
-				NRF51_GPIOTE_INTENCLR =
-					1 << NRF51_GPIOTE_IN_BIT(i);
-				/* Zero the handler */
-				gpio_ints[i] = NULL;
-			}
-		}
-	} else {
-		/* Disable the interrupt */
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-		/* Zero the shared handler */
-		gpio_int_port = NULL;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Clear interrupt and run handler.
- */
-void gpio_interrupt(void)
-{
-	const struct gpio_info *g;
-	int i;
-	int signal;
-
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-		if (NRF51_GPIOTE_IN(i)) {
-			NRF51_GPIOTE_IN(i) = 0;
-			g = gpio_ints[i];
-			signal = g - gpio_list;
-			if (g && signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-
-	if (NRF51_GPIOTE_PORT) {
-		NRF51_GPIOTE_PORT = 0;
-		g = gpio_int_port;
-		signal = g - gpio_list;
-		if (g && signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1);
diff --git a/chip/nrf51/hwtimer.c b/chip/nrf51/hwtimer.c
deleted file mode 100644
index 980a889657..0000000000
--- a/chip/nrf51/hwtimer.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Hardware timers driver.
- *
- * nRF51x has one fully functional hardware counter, but 4 stand-alone
- * capture/compare (CC) registers.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/*
- * capture/compare (CC) registers:
- *   CC_INTERRUPT -- used to interrupt next clock event.
- *   CC_CURRENT -- used to capture the current value.
- *   CC_OVERFLOW -- used to detect overflow on virtual timer (not hardware).
- */
-
-#define CC_INTERRUPT  0
-#define CC_CURRENT    1
-#define CC_OVERFLOW   2
-
-/* The nRF51 has 3 timers, use HWTIMER to specify which one is used here. */
-#define HWTIMER       0
-
-static uint32_t last_deadline;  /* cache of event set */
-
-/*
- * The nRF51x timer cannot be set to a specified value (reset to zero only).
- * Thus, we have to use a variable "shift" to maintain the offset between the
- * hardware value and virtual clock value.
- *
- * Once __hw_clock_source_set(ts) is called, the shift will be like:
- *
- *   virtual time  ------------------------------------------------
- *                  <----------> ^
- *                      shift    | ts
- *               0 |             |
- *   hardware      v
- *   counter time  ------------------------------------------------
- *
- *
- * Below diagram shows what it is when overflow happens.
- *
- *                       | now                                | prev_read
- *                       v                                    v
- *   virtual time  ------------------------------------------------
- *                 ---->                                    <------
- *                 shift                                      shift
- *                                                         |
- *   hardware                                              v
- *   counter time  ------------------------------------------------
- *
- */
-static uint32_t shift;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = deadline - shift;
-
-	/* enable interrupt */
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* disable interrupt */
-	NRF51_TIMER_INTENCLR(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	/* to capture the current value */
-	NRF51_TIMER_CAPTURE(HWTIMER, CC_CURRENT) = 1;
-	return NRF51_TIMER_CC(HWTIMER, CC_CURRENT) + shift;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	shift = ts;
-
-	/* reset counter to zero */
-	NRF51_TIMER_STOP(HWTIMER) = 1;
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* So that no interrupt until next __hw_clock_event_set() */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = ts - 1;
-
-	/* Update the overflow point */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0 - shift;
-
-	/* Start the timer again */
-	NRF51_TIMER_START(HWTIMER) = 1;
-}
-
-
-/* Interrupt handler for timer */
-void timer_irq(void)
-{
-	int overflow = 0;
-
-	/* clear status */
-	NRF51_TIMER_COMPARE(HWTIMER, CC_INTERRUPT) = 0;
-
-	if (NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW)) {
-		NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW) = 0;
-		overflow = 1;
-	}
-
-	process_timers(overflow);
-}
-
-/* DECLARE_IRQ doesn't like the NRF51_PERID_TIMER(n) macro */
-BUILD_ASSERT(NRF51_PERID_TIMER(HWTIMER) == NRF51_PERID_TIMER0);
-DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-
-	/* Start the high freq crystal oscillator */
-	NRF51_CLOCK_HFCLKSTART = 1;
-	/* TODO: check if the crystal oscillator is running (HFCLKSTAT) */
-
-	/* 32-bit timer mode */
-	NRF51_TIMER_MODE(HWTIMER) = NRF51_TIMER_MODE_TIMER;
-	NRF51_TIMER_BITMODE(HWTIMER) = NRF51_TIMER_BITMODE_32;
-
-	/*
-	 * The external crystal oscillator is 16MHz (HFCLK).
-	 * Set the prescaler to 16 so that the timer counter is increasing
-	 * every micro-second (us).
-	 */
-	NRF51_TIMER_PRESCALER(HWTIMER) = 4;  /* actual value is 2**4 = 16 */
-
-	/* Not to trigger interrupt until __hw_clock_event_set() is called. */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = 0xffffffff;
-
-	/* Set to 0 so that the next overflow can trigger timer_irq(). */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0;
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_OVERFLOW);
-
-	/* Clear the timer counter */
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(NRF51_PERID_TIMER(HWTIMER));
-
-	/* Start the timer */
-	NRF51_TIMER_START(HWTIMER) = 1;
-
-	return NRF51_PERID_TIMER(HWTIMER);
-}
-
diff --git a/chip/nrf51/i2c.c b/chip/nrf51/i2c.c
deleted file mode 100644
index ff23152c89..0000000000
--- a/chip/nrf51/i2c.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ppi.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_TIMEOUT 20000
-
-/* Keep track of the PPI channel used for each port */
-static int i2c_ppi_chan[] = {-1, -1};
-
-static void i2c_init_port(unsigned int port);
-
-/* board-specific setup for post-I2C module init */
-void __board_i2c_post_init(int port)
-{
-}
-
-void board_i2c_post_init(int port)
-		__attribute__((weak, alias("__board_i2c_post_init")));
-
-static void i2c_init_port(unsigned int port)
-{
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	NRF51_TWI_PSELSCL(port) = NRF51_TWI_SCL_PIN(port);
-	NRF51_TWI_PSELSDA(port) = NRF51_TWI_SDA_PIN(port);
-	NRF51_TWI_FREQUENCY(port) = NRF51_TWI_FREQ(port);
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	NRF51_PPI_EEP(i2c_ppi_chan[port]) = (uint32_t)&NRF51_TWI_BB(port);
-	NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-		(uint32_t)&NRF51_TWI_SUSPEND(port);
-
-	/* Master enable */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_ENABLE_VAL;
-
-	if (!(i2c_raw_get_scl(port) && (i2c_raw_get_sda(port))))
-		CPRINTF("port %d could be wedged\n", port);
-}
-
-void i2c_init(void)
-{
-	int i, rv;
-
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (i2c_ppi_chan[i] == -1) {
-			rv = ppi_request_channel(&i2c_ppi_chan[i]);
-			ASSERT(rv == EC_SUCCESS);
-
-			i2c_init_port(i);
-		}
-	}
-}
-
-static void dump_i2c_reg(int port)
-{
-#ifdef CONFIG_I2C_DEBUG
-	CPRINTF("port      : %01d\n", port);
-	CPRINTF("Regs :\n");
-	CPRINTF(" 1: INTEN     : %08x\n", NRF51_TWI_INTEN(port));
-	CPRINTF(" 2: ERRORSRC  : %08x\n", NRF51_TWI_ERRORSRC(port));
-	CPRINTF(" 3: ENABLE    : %08x\n", NRF51_TWI_ENABLE(port));
-	CPRINTF(" 4: PSELSCL   : %08x\n", NRF51_TWI_PSELSCL(port));
-	CPRINTF(" 5: PSELSDA   : %08x\n", NRF51_TWI_PSELSDA(port));
-	CPRINTF(" 6: RXD       : %08x\n", NRF51_TWI_RXD(port));
-	CPRINTF(" 7: TXD       : %08x\n", NRF51_TWI_TXD(port));
-	CPRINTF(" 8: FREQUENCY : %08x\n", NRF51_TWI_FREQUENCY(port));
-	CPRINTF(" 9: ADDRESS   : %08x\n", NRF51_TWI_ADDRESS(port));
-	CPRINTF("Events :\n");
-	CPRINTF(" STOPPED   : %08x\n", NRF51_TWI_STOPPED(port));
-	CPRINTF(" RXDRDY    : %08x\n", NRF51_TWI_RXDRDY(port));
-	CPRINTF(" TXDSENT   : %08x\n", NRF51_TWI_TXDSENT(port));
-	CPRINTF(" ERROR     : %08x\n", NRF51_TWI_ERROR(port));
-	CPRINTF(" BB        : %08x\n", NRF51_TWI_BB(port));
-#endif /* CONFIG_I2C_DEBUG */
-}
-
-static void i2c_recover(int port)
-{
-	/*
-	 * Recovery of the TWI peripheral:
-	 * To recover a TWI peripheral that has been locked up you must use
-	 * the following code.
-	 * After the recover function it is important to reconfigure all
-	 * relevant TWI registers explicitly to ensure that it operates
-	 * correctly.
-	 *    TWI0:
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 0;
-	 *      nrf_delay_us(5);
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 1;
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
-	 */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_DISABLE_VAL;
-	NRF51_TWI_POWER(port) = 0;
-	udelay(5);
-	NRF51_TWI_POWER(port) = 1;
-
-	i2c_init_port(port);
-}
-
-static void handle_i2c_error(int port, int rv)
-{
-	if (rv == EC_SUCCESS)
-		return;
-
-#ifdef CONFIG_I2C_DEBUG
-	if (rv != EC_ERROR_TIMEOUT)
-		CPRINTF("handle_i2c_error %d\n", rv);
-	else
-		CPRINTF("handle_i2c_error: Timeout\n");
-
-	dump_i2c_reg(port);
-#endif
-
-	/* This may be a little too heavy handed. */
-	i2c_recover(port);
-}
-
-static int i2c_master_write(const int port, const uint16_t slave_addr_flags,
-			    const uint8_t *data, int size, int stop)
-{
-	int bytes_sent;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	/* Clear the sent bit */
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	for (bytes_sent = 0; bytes_sent < size; bytes_sent++) {
-		/*Send a byte */
-		NRF51_TWI_TXD(port) = data[bytes_sent];
-
-		/* Only send a start for the first byte */
-		if (bytes_sent == 0)
-			NRF51_TWI_STARTTX(port) = 1;
-
-		/* Wait for ACK/NACK */
-		timeout = I2C_TIMEOUT;
-		while (timeout > 0 && NRF51_TWI_TXDSENT(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		/* Clear the sent bit */
-		NRF51_TWI_TXDSENT(port) = 0;
-	}
-
-	if (stop) {
-		NRF51_TWI_STOPPED(port) = 0;
-		NRF51_TWI_STOP(port) = 1;
-		timeout = 10;
-		while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-			timeout--;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int i2c_master_read(const int port, const uint16_t slave_addr_flags,
-			   uint8_t *data, int size)
-{
-	int curr_byte;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	if (size == 1) /* Last byte: stop after this one. */
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_STOP(port);
-	else
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_SUSPEND(port);
-	NRF51_PPI_CHENSET = 1 << i2c_ppi_chan[port];
-
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_STARTRX(port) = 1;
-
-	for (curr_byte = 0; curr_byte < size; curr_byte++) {
-
-		/* Wait for data */
-		while (timeout > 0 && NRF51_TWI_RXDRDY(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		data[curr_byte] = NRF51_TWI_RXD(port);
-		NRF51_TWI_RXDRDY(port) = 0;
-
-		/* Second to the last byte: stop next time. */
-		if (curr_byte == size-2)
-			NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-				(uint32_t)&NRF51_TWI_STOP(port);
-
-		/*
-		 * According to nRF51822-PAN v2.4 (Product Anomaly Notice),
-		 * the I2C locks up when RESUME is triggered too soon.
-		 * "the firmware should ensure that the time between receiving
-		 * the RXDRDY event and trigging the RESUME task is at least
-		 * two times the TWI clock period (i.e. 20 μs at 100 kbps).
-		 * Provided the TWI slave doesn’t do clock stretching during
-		 * the ACK bit, this will be enough to avoid the RESUME task
-		 * hit the end of the ACK bit. If this fails, a recovery of
-		 * the peripheral will be necessary, see i2c_recover.
-		 */
-		udelay(20);
-		NRF51_TWI_RESUME(port) = 1;
-	}
-
-	timeout = I2C_TIMEOUT;
-	while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-		timeout--;
-
-	NRF51_TWI_STOP(port) = 0;
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	return EC_SUCCESS;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int rv = EC_SUCCESS;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	if (out_bytes)
-		rv = i2c_master_write(port, slave_addr_flags,
-				      out, out_bytes,
-				      in_bytes ? 0 : 1);
-	if (rv == EC_SUCCESS && in_bytes)
-		rv = i2c_master_read(port, slave_addr_flags,
-				     in, in_bytes);
-
-	handle_i2c_error(port, rv);
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
diff --git a/chip/nrf51/keyboard_raw.c b/chip/nrf51/keyboard_raw.c
deleted file mode 100644
index 779c68454c..0000000000
--- a/chip/nrf51/keyboard_raw.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for nRF51
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of output pins for driving. */
-static unsigned int col_mask;
-
-void keyboard_raw_init(void)
-{
-	int i;
-
-	/* Initialize col_mask */
-	col_mask = 0;
-	for (i = 0; i < keyboard_cols; i++)
-		col_mask |= gpio_list[GPIO_KB_OUT00 + i].mask;
-
-	/* Ensure interrupts are disabled */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/*
-	 * Enable the interrupt for keyboard matrix inputs.
-	 * One is enough, since they are shared.
-	 */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* tri-state all first */
-	NRF51_GPIO0_OUTSET = col_mask;
-
-	/* drive low for specified pin(s) */
-	if (out == KEYBOARD_COLUMN_ALL)
-		NRF51_GPIO0_OUTCLR = col_mask;
-	else if (out != KEYBOARD_COLUMN_NONE)
-		NRF51_GPIO0_OUTCLR = gpio_list[GPIO_KB_OUT00 + out].mask;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	int state = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		if (NRF51_GPIO0_IN & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear the PORT event before enabling the interrupt.
-		 */
-		NRF51_GPIOTE_PORT = 0;
-		NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-	} else {
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c
deleted file mode 100644
index 016cbf3008..0000000000
--- a/chip/nrf51/ppi.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ppi.h"
-#include "registers.h"
-#include "util.h"
-
-#define NRF51_PPI_FIRST_PP_CH NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_LAST_PP_CH  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-static uint32_t channels_in_use;
-static uint32_t channel_groups_in_use;
-
-int ppi_request_pre_programmed_channel(int ppi_chan)
-{
-	ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH &&
-		ppi_chan <= NRF51_PPI_LAST_PP_CH);
-
-	if (channels_in_use & BIT(ppi_chan))
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(ppi_chan);
-
-	return EC_SUCCESS;
-}
-
-int ppi_request_channel(int *ppi_chan)
-{
-	int chan;
-
-	for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++)
-		if ((channels_in_use & BIT(chan)) == 0)
-			break;
-
-	if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS)
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(chan);
-	*ppi_chan = chan;
-	return EC_SUCCESS;
-}
-
-void ppi_release_channel(int ppi_chan)
-{
-	channels_in_use &= ~BIT(ppi_chan);
-}
-
-void ppi_release_group(int ppi_group)
-{
-	channel_groups_in_use &= ~BIT(ppi_group);
-}
-
-int ppi_request_group(int *ppi_group)
-{
-	int group;
-
-	for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++)
-		if ((channel_groups_in_use & BIT(group)) == 0)
-			break;
-
-	if (group == NRF51_PPI_NUM_GROUPS)
-		return EC_ERROR_BUSY;
-
-	channel_groups_in_use |= BIT(group);
-	*ppi_group = group;
-	return EC_SUCCESS;
-}
diff --git a/chip/nrf51/ppi.h b/chip/nrf51/ppi.h
deleted file mode 100644
index bbb74a2cf0..0000000000
--- a/chip/nrf51/ppi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * PPI channels are a way to connect NRF51 EVENTs to TASKs without software
- * involvement. They are like SHORTs, except between peripherals.
- *
- * PPI groups are user-defined sets of channels that can be enabled and disabled
- * together.
- */
-
-/*
- * Reserve a pre-programmed PPI channel.
- *
- * Return EC_SUCCESS if ppi_chan is a pre-programmed channel that was not in
- * use, otherwise returns EC_ERROR_BUSY.
- */
-int ppi_request_pre_programmed_channel(int ppi_chan);
-
-/*
- * Reserve an available PPI channel.
- *
- * Return EC_SUCCESS and set the value of ppi_chan to an available PPI
- * channel.  If no channel is available, return EC_ERROR_BUSY.
- */
-int ppi_request_channel(int *ppi_chan);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_channel(int ppi_chan);
-
-/*
- * Reserve a PPI group.
- *
- * Return EC_SUCCESS and set the value of ppi_group to an available PPI
- * group.  If no group is available, return EC_ERROR_BUSY.
- */
-int ppi_request_group(int *ppi_group);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_group(int ppi_group);
diff --git a/chip/nrf51/radio.c b/chip/nrf51/radio.c
deleted file mode 100644
index af9d029a0d..0000000000
--- a/chip/nrf51/radio.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "radio.h"
-
-int radio_disable(void)
-{
-	int timeout = 10000;
-
-	NRF51_RADIO_DISABLED = 0;
-	NRF51_RADIO_DISABLE = 1;
-
-	while (!NRF51_RADIO_DISABLED && timeout > 0)
-		timeout--;
-
-	if (timeout == 0)
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-int radio_init(enum nrf51_radio_mode_t mode)
-{
-	int err_code = radio_disable();
-
-	if (mode == BLE_1MBIT) {
-		NRF51_RADIO_MODE = NRF51_RADIO_MODE_BLE_1MBIT;
-
-		NRF51_RADIO_TIFS = 150;	/* Bluetooth 4.1 Vol 6 pg 58 4.1 */
-
-		/*
-		 * BLE never sends or receives two packets in a row.
-		 * Enabling the radio means we want to transmit or receive.
-		 * After transmission, disable as quickly as possible.
-		 */
-		NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-				NRF51_RADIO_SHORTS_END_DISABLE;
-
-		/* Use factory parameters if available */
-		if (!(NRF51_FICR_OVERRIDEEN & NRF51_FICR_OVERRIDEEN_BLE_BIT_N)
-		    ) {
-			int i;
-
-			for (i = 0; i < 4; i++) {
-				NRF51_RADIO_OVERRIDE(i) =
-					NRF51_FICR_BLE_1MBIT(i);
-			}
-			NRF51_RADIO_OVERRIDE(4) = NRF51_FICR_BLE_1MBIT(4) |
-				NRF51_RADIO_OVERRIDE_EN;
-		}
-	} else {
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return err_code;
-}
-
diff --git a/chip/nrf51/radio.h b/chip/nrf51/radio.h
deleted file mode 100644
index 5b7e764fb9..0000000000
--- a/chip/nrf51/radio.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Radio interface for Chrome EC */
-
-#ifndef __NRF51_RADIO_H
-#define __NRF51_RADIO_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "registers.h"
-
-#ifndef NRF51_RADIO_MAX_PAYLOAD
-	#define NRF51_RADIO_MAX_PAYLOAD 253
-#endif
-
-#define RADIO_DONE (NRF51_RADIO_END == 1)
-
-enum nrf51_radio_mode_t {
-	BLE_1MBIT = NRF51_RADIO_MODE_BLE_1MBIT,
-};
-
-struct nrf51_radio_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t s1; /* Bits after length */
-	uint8_t payload[NRF51_RADIO_MAX_PAYLOAD];
-} __packed;
-
-int radio_init(enum nrf51_radio_mode_t mode);
-
-int radio_disable(void);
-
-#endif  /* __NRF51_RADIO_H */
diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c
deleted file mode 100644
index 6c20874f4e..0000000000
--- a/chip/nrf51/radio_test.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h" /* chan2freq */
-#include "btle_hci_int.h"
-#include "console.h"
-#include "radio.h"
-#include "radio_test.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define BLE_TEST_TYPE_PRBS9   0
-#define BLE_TEST_TYPE_F0      1
-#define BLE_TEST_TYPE_AA      2
-#define BLE_TEST_TYPE_PRBS15  3
-#define BLE_TEST_TYPE_FF      4
-#define BLE_TEST_TYPE_00      5
-#define BLE_TEST_TYPE_0F      6
-#define BLE_TEST_TYPE_55      7
-
-#define BLE_TEST_TYPES_IMPLEMENTED 0xf6 /* No PRBS yet */
-
-static struct nrf51_ble_packet_t rx_packet;
-static struct nrf51_ble_packet_t tx_packet;
-static uint32_t rx_end;
-
-static int test_in_progress;
-
-void ble_test_stop(void)
-{
-	test_in_progress = 0;
-}
-
-static uint32_t prbs_lfsr;
-static uint32_t prbs_poly;
-
-/*
- * This is a Galois LFSR, the polynomial is the counterpart of the Fibonacci
- * LFSR in the doc.  It requires fewer XORs to implement in software.
- * This also means that the initial value is different.
- */
-static uint8_t prbs_next_byte(void)
-{
-	int i;
-	int lsb;
-	uint8_t rv = 0;
-
-	for (i = 0; i < 8; i++) {
-		lsb = prbs_lfsr & 1;
-		rv |= lsb << i;
-		prbs_lfsr = prbs_lfsr >> 1;
-		if (lsb)
-			prbs_lfsr ^= prbs_poly;
-	}
-	return rv;
-}
-
-void ble_test_fill_tx_packet(int type, int len)
-{
-	int i;
-
-	tx_packet.s0 = type & 0xf;
-	tx_packet.length = len;
-
-	switch (type) {
-	case BLE_TEST_TYPE_PRBS9:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x108;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_PRBS15:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x6000;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_F0:
-		memset(tx_packet.payload, 0xF0, len);
-		break;
-	case BLE_TEST_TYPE_AA:
-		memset(tx_packet.payload, 0xAA, len);
-		break;
-	case BLE_TEST_TYPE_FF:
-		memset(tx_packet.payload, 0xFF, len);
-		break;
-	case BLE_TEST_TYPE_00:
-		memset(tx_packet.payload, 0x00, len);
-		break;
-	case BLE_TEST_TYPE_0F:
-		memset(tx_packet.payload, 0x0F, len);
-		break;
-	case BLE_TEST_TYPE_55:
-		memset(tx_packet.payload, 0x55, len);
-		break;
-	default:
-		break;
-	}
-}
-
-static int ble_test_init(int chan)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return HCI_ERR_Hardware_Failure;
-
-	if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-	NRF51_RADIO_CRCINIT = 0x555555;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	/* The testing address is the inverse of the advertising address. */
-	NRF51_RADIO_BASE0 = (~BLE_ADV_ACCESS_ADDRESS) << 8;
-
-	NRF51_RADIO_PREFIX0 = (~BLE_ADV_ACCESS_ADDRESS) >> 24;
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_TEST;
-
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_TEST;
-
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(2*chan + 2402);
-
-	test_in_progress = 1;
-	return rv;
-}
-
-int ble_test_rx_init(int chan)
-{
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	return ble_test_init(chan);
-}
-
-int ble_test_tx_init(int chan, int len, int type)
-{
-	if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 ||
-			(len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS))
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	ble_test_fill_tx_packet(type, len);
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-
-	return ble_test_init(chan);
-}
-
-void ble_test_tx(void)
-{
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_TXEN = 1;
-}
-
-int ble_test_rx(void)
-{
-	int retries = 100;
-
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_RXEN = 1;
-
-	do {
-		retries--;
-		if (retries <= 0) {
-			radio_disable();
-			return EC_ERROR_TIMEOUT;
-		}
-		usleep(100);
-	} while (!NRF51_RADIO_END);
-
-	rx_end = get_time().le.lo;
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/nrf51/radio_test.h b/chip/nrf51/radio_test.h
deleted file mode 100644
index 591b78a78c..0000000000
--- a/chip/nrf51/radio_test.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Radio test interface for NRF51
- *
- * These functions implement parts of the Direct Test Mode functionality in
- * the Bluetooth Spec.
- */
-
-#ifndef __NRF51_RADIO_TEST_H
-#define __NRF51_RADIO_TEST_H
-
-#define BLE_MAX_TEST_PAYLOAD_OCTETS       37
-#define BLE_MAX_TEST_CHANNEL              39
-#define BLE_MIN_TEST_CHANNEL              0
-
-#define NRF51_RADIO_PCNF0_TEST NRF51_RADIO_PCNF0_ADV_DATA
-
-#define BLE_TEST_WHITEN           0
-
-#define NRF51_RADIO_PCNF1_TEST \
-	NRF51_RADIO_PCNF1_VAL(BLE_MAX_TEST_PAYLOAD_OCTETS, \
-			      EXTRA_RECEIVE_BYTES, \
-			      BLE_ACCESS_ADDRESS_BYTES - 1, \
-			      BLE_TEST_WHITEN)
-
-/*
- * Prepare the radio for transmitting packets.  The value of chan must be
- * between 0 and 39 inclusive.  The maximum length is 37.
- */
-
-int ble_test_tx_init(int chan, int type, int len);
-int ble_test_rx_init(int chan);
-void ble_test_tx(void);
-int ble_test_rx(void);
-void ble_test_stop(void);
-
-#endif /* __NRF51_RADIO_TEST_H */
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h
deleted file mode 100644
index daf014df72..0000000000
--- a/chip/nrf51/registers.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/*
- *  Peripheral IDs
- *
- *  nRF51 has very good design that the peripheral IDs is actually the IRQ#.
- *  Thus, the following numbers are used in DECLARE_IRQ(), task_enable_irq()
- *  and task_disable_irq().
- */
-#define NRF51_PERID_POWER   0
-#define NRF51_PERID_CLOCK   0
-#define NRF51_PERID_RADIO   1
-#define NRF51_PERID_USART   2
-#define NRF51_PERID_SPI0    3
-#define NRF51_PERID_TWI0    3
-#define NRF51_PERID_SPI1    4
-#define NRF51_PERID_TWI1    4
-#define NRF51_PERID_SPIS    4
-#define NRF51_PERID_GPIOTE  6
-#define NRF51_PERID_ADC     7
-#define NRF51_PERID_TIMER0  8
-#define NRF51_PERID_TIMER1  9
-#define NRF51_PERID_TIMER2  10
-#define NRF51_PERID_RTC     11
-#define NRF51_PERID_TEMP    12
-#define NRF51_PERID_RNG     13
-#define NRF51_PERID_ECB     14
-#define NRF51_PERID_CCM     15
-#define NRF51_PERID_AAR     16
-#define NRF51_PERID_WDT     17
-#define NRF51_PERID_QDEC    18
-#define NRF51_PERID_LPCOMP  19
-#define NRF51_PERID_NVMC    30
-#define NRF51_PERID_PPI     31
-
-/*
- * The nRF51 allows any pin to be mapped to any function.  This
- * doesn't fit well with the notion of the alternate function table.
- * Implement an alternate function table.  See ./gpio.c.
- */
-
-	/* UART */
-#define NRF51_UART_ALT_FUNC_RTS        0
-#define NRF51_UART_ALT_FUNC_TXD        1
-#define NRF51_UART_ALT_FUNC_CTS        2
-#define NRF51_UART_ALT_FUNC_RXD        3
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI0_ALT_FUNC_SCK        4
-#define NRF51_SPI0_ALT_FUNC_MOSI       5
-#define NRF51_SPI0_ALT_FUNC_MISO       6
-	/* TWI0 (I2C) */
-#define NRF51_TWI0_ALT_FUNC_SCL        7
-#define NRF51_TWI0_ALT_FUNC_SDA        8
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI1_ALT_FUNC_SCK        9
-#define NRF51_SPI1_ALT_FUNC_MOSI       10
-#define NRF51_SPI1_ALT_FUNC_MISO       11
-	/* TWI1 (I2C) */
-#define NRF51_TWI1_ALT_FUNC_SCL        12
-#define NRF51_TWI1_ALT_FUNC_SDA        13
-	/* SPIS1 (SPI SLAVE) */
-#define NRF51_SPIS1_ALT_FUNC_SCK       14
-#define NRF51_SPIS1_ALT_FUNC_MISO      15
-#define NRF51_SPIS1_ALT_FUNC_MOSI      16
-#define NRF51_SPIS1_ALT_FUNC_CSN       17
-	/* QDEC (ROTARY DECODER) */
-#define NRF51_QDEC_ALT_FUNC_LED        18
-#define NRF51_QDEC_ALT_FUNC_A          19
-#define NRF51_QDEC_ALT_FUNC_B          20
-	/* LPCOMP (Low Power Comparator) */
-#define NRF51_LPCOMP_ALT_FUNC          21
-#define NRF51_MAX_ALT_FUNCS            22
-
-/*
- * Configuration Registers
- */
-
-/*
- * FICR
- */
-#define NRF51_FICR_BASE                0x10000000
-#define NRF51_FICR_CODEPAGESIZE        REG32(NRF51_FICR_BASE + 0x010)
-#define NRF51_FICR_CLENR0              REG32(NRF51_FICR_BASE + 0x014)
-#define NRF51_FICR_PPFC                REG32(NRF51_FICR_BASE + 0x028)
-#define NRF51_FICR_NUMRAMBLOCK         REG32(NRF51_FICR_BASE + 0x02C)
-#define NRF51_FICR_SIZERAMBLOCK(n)     REG32(NRF51_FICR_BASE + 0x034 + ((n)*4))
-#define NRF51_FICR_CONFIGID            REG32(NRF51_FICR_BASE + 0x05C)
-#define NRF51_FICR_DEVICEID(n)         REG32(NRF51_FICR_BASE + 0x060 + ((n)*4))
-#define NRF51_FICR_ER(n)               REG32(NRF51_FICR_BASE + 0x080 + ((n)*4))
-#define NRF51_FICR_IR(n)               REG32(NRF51_FICR_BASE + 0x090 + ((n)*4))
-#define NRF51_FICR_DEVICEADDRTYPE      REG32(NRF51_FICR_BASE + 0x0A0)
-#define NRF51_FICR_DEVICEADDR(n)       REG32(NRF51_FICR_BASE + 0x0A4 + ((n)*4))
-#define NRF51_FICR_OVERRIDEEN          REG32(NRF51_FICR_BASE + 0x0AC)
-#define NRF51_FICR_BLE_1MBIT(n)        REG32(NRF51_FICR_BASE + 0x0EC + ((n)*4))
-
-/* DEVICEADDRTYPE */
-#define NRF51_FICR_DEVICEADDRTYPE_RANDOM      1
-
-/* OVERRIDEEN */
-#define NRF51_FICR_OVERRIDEEN_NRF_BIT_N       1
-#define NRF51_FICR_OVERRIDEEN_BLE_BIT_N       8
-
-/*
- * UICR
- */
-#define NRF51_UICR_BASE                0x10001000
-#define NRF51_UICR_CLENR0              REG32(NRF51_UICR_BASE + 0x000)
-#define NRF51_UICR_RBPCONF             REG32(NRF51_UICR_BASE + 0x004)
-#define NRF51_UICR_XTALFREQ            REG32(NRF51_UICR_BASE + 0x008)
-#define NRF51_UICR_FWID                REG32(NRF51_UICR_BASE + 0x010)
-#define NRF51_UICR_FWID_CUSTOMER(n)    REG32(NRF51_UICR_BASE + 0x080 + ((n)*4))
-
-#define NRF51_UICR_XTALFREQ_16MHZ      0xFF
-#define NRF51_UICR_XTALFREQ_32MHZ      0x00
-
-/*
- * Devices
- */
-
-/*
- *  Power
- */
-#define NRF51_POWER_BASE    0x40000000
-/* Tasks */
-#define NRF51_POWER_CONSTLAT  REG32(NRF51_POWER_BASE + 0x078)
-#define NRF51_POWER_LOWPWR    REG32(NRF51_POWER_BASE + 0x07C)
-/* Events */
-#define NRF51_POWER_POFWARN   REG32(NRF51_POWER_BASE + 0x108)
-/* Registers */
-#define NRF51_POWER_INTENSET  REG32(NRF51_POWER_BASE + 0x304)
-#define NRF51_POWER_INTENCLR  REG32(NRF51_POWER_BASE + 0x308)
-#define NRF51_POWER_RESETREAS REG32(NRF51_POWER_BASE + 0x400)
-#define NRF51_POWER_SYSTEMOFF REG32(NRF51_POWER_BASE + 0x500)
-#define NRF51_POWER_POFCON    REG32(NRF51_POWER_BASE + 0x510)
-#define NRF51_POWER_GPREGRET  REG32(NRF51_POWER_BASE + 0x51C)
-#define NRF51_POWER_RAMON     REG32(NRF51_POWER_BASE + 0x524)
-#define NRF51_POWER_RESET     REG32(NRF51_POWER_BASE + 0x544)
-#define NRF51_POWER_DCDCEN    REG32(NRF51_POWER_BASE + 0x578)
-
-#define NRF51_POWER_RESETREAS_RESETPIN          0x00001
-#define NRF51_POWER_RESETREAS_DOG               0x00002
-#define NRF51_POWER_RESETREAS_SREQ              0x00004
-#define NRF51_POWER_RESETREAS_LOCKUP            0x00008
-#define NRF51_POWER_RESETREAS_OFF               0x10000
-#define NRF51_POWER_RESETREAS_LPCOMP            0x20000
-#define NRF51_POWER_RESETREAS_DIF               0x40000
-
-
-/*
- *  Clock
- */
-#define NRF51_CLOCK_BASE    0x40000000
-/* Tasks */
-#define NRF51_CLOCK_HFCLKSTART REG32(NRF51_CLOCK_BASE + 0x000)
-#define NRF51_CLOCK_HFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x004)
-#define NRF51_CLOCK_LFCLKSTART REG32(NRF51_CLOCK_BASE + 0x008)
-#define NRF51_CLOCK_LFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x00C)
-#define NRF51_CLOCK_CAL     REG32(NRF51_CLOCK_BASE + 0x010)
-#define NRF51_CLOCK_CTSTART REG32(NRF51_CLOCK_BASE + 0x014)
-#define NRF51_CLOCK_CTSTOP  REG32(NRF51_CLOCK_BASE + 0x018)
-/* Events */
-#define NRF51_CLOCK_HFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x100)
-#define NRF51_CLOCK_LFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x104)
-#define NRF51_CLOCK_DONE    REG32(NRF51_CLOCK_BASE + 0x10C)
-#define NRF51_CLOCK_CCTO    REG32(NRF51_CLOCK_BASE + 0x110)
-/* Registers */
-#define NRF51_CLOCK_INTENSET  REG32(NRF51_CLOCK_BASE + 0x304)
-#define NRF51_CLOCK_INTENCLR  REG32(NRF51_CLOCK_BASE + 0x308)
-#define NRF51_CLOCK_HFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x40C)
-#define NRF51_CLOCK_LFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x418)
-#define NRF51_CLOCK_LFCLKSRC  REG32(NRF51_CLOCK_BASE + 0x518)
-#define NRF51_CLOCK_CTIV      REG32(NRF51_CLOCK_BASE + 0x538)
-#define NRF51_CLOCK_XTALFREQ  REG32(NRF51_CLOCK_BASE + 0x550)
-
-/*
- *  Radio
- */
-#define NRF51_RADIO_BASE    0x40001000
-/* Tasks */
-#define NRF51_RADIO_TXEN      REG32(NRF51_RADIO_BASE + 0x000)
-#define NRF51_RADIO_RXEN      REG32(NRF51_RADIO_BASE + 0x004)
-#define NRF51_RADIO_START     REG32(NRF51_RADIO_BASE + 0x008)
-#define NRF51_RADIO_STOP      REG32(NRF51_RADIO_BASE + 0x00C)
-#define NRF51_RADIO_DISABLE   REG32(NRF51_RADIO_BASE + 0x010)
-#define NRF51_RADIO_RSSISTART REG32(NRF51_RADIO_BASE + 0x014)
-#define NRF51_RADIO_RSSISTOP  REG32(NRF51_RADIO_BASE + 0x018)
-#define NRF51_RADIO_BCSTART   REG32(NRF51_RADIO_BASE + 0x01C)
-#define NRF51_RADIO_BCSTOP    REG32(NRF51_RADIO_BASE + 0x020)
-/* Events */
-#define NRF51_RADIO_READY     REG32(NRF51_RADIO_BASE + 0x100)
-#define NRF51_RADIO_ADDRESS   REG32(NRF51_RADIO_BASE + 0x104)
-#define NRF51_RADIO_PAYLOAD   REG32(NRF51_RADIO_BASE + 0x108)
-#define NRF51_RADIO_END       REG32(NRF51_RADIO_BASE + 0x10C)
-#define NRF51_RADIO_DISABLED  REG32(NRF51_RADIO_BASE + 0x110)
-#define NRF51_RADIO_DEVMATCH  REG32(NRF51_RADIO_BASE + 0x114)
-#define NRF51_RADIO_DEVMISS   REG32(NRF51_RADIO_BASE + 0x118)
-#define NRF51_RADIO_RSSIEND   REG32(NRF51_RADIO_BASE + 0x11C)
-#define NRF51_RADIO_BCMATCH   REG32(NRF51_RADIO_BASE + 0x128)
-/* Registers */
-#define NRF51_RADIO_SHORTS      REG32(NRF51_RADIO_BASE + 0x200)
-#define NRF51_RADIO_INTENSET    REG32(NRF51_RADIO_BASE + 0x304)
-#define NRF51_RADIO_INTENCLR    REG32(NRF51_RADIO_BASE + 0x308)
-#define NRF51_RADIO_CRCSTATUS   REG32(NRF51_RADIO_BASE + 0x400)
-#define NRF51_RADIO_RXMATCH     REG32(NRF51_RADIO_BASE + 0x408)
-#define NRF51_RADIO_RXCRC       REG32(NRF51_RADIO_BASE + 0x40C)
-#define NRF51_RADIO_DAI         REG32(NRF51_RADIO_BASE + 0x410)
-#define NRF51_RADIO_PACKETPTR   REG32(NRF51_RADIO_BASE + 0x504)
-#define NRF51_RADIO_FREQUENCY   REG32(NRF51_RADIO_BASE + 0x508)
-#define NRF51_RADIO_TXPOWER     REG32(NRF51_RADIO_BASE + 0x50C)
-#define NRF51_RADIO_MODE        REG32(NRF51_RADIO_BASE + 0x510)
-#define NRF51_RADIO_PCNF0       REG32(NRF51_RADIO_BASE + 0x514)
-#define NRF51_RADIO_PCNF1       REG32(NRF51_RADIO_BASE + 0x518)
-#define NRF51_RADIO_BASE0       REG32(NRF51_RADIO_BASE + 0x51C)
-#define NRF51_RADIO_BASE1       REG32(NRF51_RADIO_BASE + 0x520)
-#define NRF51_RADIO_PREFIX0     REG32(NRF51_RADIO_BASE + 0x524)
-#define NRF51_RADIO_PREFIX1     REG32(NRF51_RADIO_BASE + 0x528)
-#define NRF51_RADIO_TXADDRESS   REG32(NRF51_RADIO_BASE + 0x52C)
-#define NRF51_RADIO_RXADDRESSES REG32(NRF51_RADIO_BASE + 0x530)
-#define NRF51_RADIO_CRCCNF      REG32(NRF51_RADIO_BASE + 0x534)
-#define NRF51_RADIO_CRCPOLY     REG32(NRF51_RADIO_BASE + 0x538)
-#define NRF51_RADIO_CRCINIT     REG32(NRF51_RADIO_BASE + 0x53C)
-#define NRF51_RADIO_TEST        REG32(NRF51_RADIO_BASE + 0x540)
-#define NRF51_RADIO_TIFS        REG32(NRF51_RADIO_BASE + 0x544)
-#define NRF51_RADIO_RSSISAMPLE  REG32(NRF51_RADIO_BASE + 0x548)
-/* NRF51_RADIO_STATE (0x550) is Broken (PAN 2.4) */
-#define NRF51_RADIO_DATAWHITEIV REG32(NRF51_RADIO_BASE + 0x554)
-#define NRF51_RADIO_BCC         REG32(NRF51_RADIO_BASE + 0x560)
-#define NRF51_RADIO_DAB(n)      REG32(NRF51_RADIO_BASE + 0x600 + ((n) * 4))
-#define NRF51_RADIO_DAP(n)      REG32(NRF51_RADIO_BASE + 0x620 + ((n) * 4))
-#define NRF51_RADIO_DACNF       REG32(NRF51_RADIO_BASE + 0x640)
-#define NRF51_RADIO_OVERRIDE(n) REG32(NRF51_RADIO_BASE + 0x724 + ((n) * 4))
-#define NRF51_RADIO_POWER       REG32(NRF51_RADIO_BASE + 0xFFC)
-
-/* Shorts */
-#define NRF51_RADIO_SHORTS_READY_START                0x001
-#define NRF51_RADIO_SHORTS_END_DISABLE                0x002
-#define NRF51_RADIO_SHORTS_DISABLED_TXEN              0x004
-#define NRF51_RADIO_SHORTS_DISABLED_RXEN              0x008
-#define NRF51_RADIO_SHORTS_ADDRESS_RSSISTART          0x010
-/* NRF51_RADIO_SHORTS_END_START (0x20) is Broken (PAN 2.4) */
-#define NRF51_RADIO_SHORTS_ADDRESS_BCSTART            0x040
-#define NRF51_RADIO_SHORTS_DISABLED_RSSISTOP          0x100
-
-/* For RADIO.INTEN bits */
-#define NRF51_RADIO_READY_BIT                         0
-#define NRF51_RADIO_ADDRESS_BIT                       1
-#define NRF51_RADIO_PAYLOAD_BIT                       2
-#define NRF51_RADIO_END_BIT                           3
-#define NRF51_RADIO_DISABLED_BIT                      4
-#define NRF51_RADIO_DEVMATCH_BIT                      5
-#define NRF51_RADIO_DEVMISS_BIT                       6
-#define NRF51_RADIO_RSSIEND_BIT                       7
-#define NRF51_RADIO_BCMATCH_BIT                       10
-
-/* CRC Status */
-#define NRF51_RADIO_CRCSTATUS_OK                      0x1
-
-/* Frequency (in MHz) */
-#define NRF51_RADIO_FREQUENCY_VAL(x)                  ((x) - 2400)
-
-/* TX Power */
-#define NRF51_RADIO_TXPOWER_POS_4_DBM                 0x04
-#define NRF51_RADIO_TXPOWER_0_DBM                     0x00
-#define NRF51_RADIO_TXPOWER_NEG_8_DBM                 0xFC
-#define NRF51_RADIO_TXPOWER_NEG_12_DBM                0xF8
-#define NRF51_RADIO_TXPOWER_NEG_16_DBM                0xF4
-#define NRF51_RADIO_TXPOWER_NEG_20_DBM                0xEC
-#define NRF51_RADIO_TXPOWER_NEG_30_DBM                0xD8
-
-/* TX Mode */
-#define NRF51_RADIO_MODE_BLE_1MBIT                    0x03
-
-/*
- * PCNF0 and PCNF1 Packet Configuration
- *
- * The radio unpacks the packet for you according to these settings.
- *
- * The on-air format is:
- *
- * |_Preamble_|___Base___|_Prefix_|___S0____|_Length_,_S1_|__Payload__|___|
- * 0           <ba_bytes> <1 byte><s0_bytes>   <1 byte>    <max_bytes> <extra>
- *
- * The in-memory format is
- *
- * uint8_t s0[s0_bytes];
- * uint8_t length;
- * uint8_t s1;
- * uint8_t payload[max_bytes];
- *
- * lf_bits is how many bits to store in length
- * s1_bits is how many bits to store in s1
- *
- * If any one of these lengths are set to zero, the field is omitted in memory.
- */
-
-#define NRF51_RADIO_PCNF0_LFLEN_SHIFT                 0
-#define NRF51_RADIO_PCNF0_S0LEN_SHIFT                 8
-#define NRF51_RADIO_PCNF0_S1LEN_SHIFT                 16
-
-#define NRF51_RADIO_PCNF0_VAL(lf_bits, s0_bytes, s1_bits) \
-	((lf_bits) << NRF51_RADIO_PCNF0_LFLEN_SHIFT | \
-	 (s0_bytes) << NRF51_RADIO_PCNF0_S0LEN_SHIFT | \
-	 (s1_bits) << NRF51_RADIO_PCNF0_S1LEN_SHIFT)
-
-#define NRF51_RADIO_PCNF1_MAXLEN_SHIFT                0
-#define NRF51_RADIO_PCNF1_STATLEN_SHIFT               8
-#define NRF51_RADIO_PCNF1_BALEN_SHIFT                 16
-#define NRF51_RADIO_PCNF1_ENDIAN_BIG                  0x1000000
-#define NRF51_RADIO_PCNF1_WHITEEN                     0x2000000
-
-#define NRF51_RADIO_PCNF1_VAL(max_bytes, extra_bytes, ba_bytes, whiten) \
-	((max_bytes) << NRF51_RADIO_PCNF1_MAXLEN_SHIFT | \
-	 (extra_bytes) << NRF51_RADIO_PCNF1_STATLEN_SHIFT | \
-	 (ba_bytes) << NRF51_RADIO_PCNF1_BALEN_SHIFT | \
-	 ((whiten) ? NRF51_RADIO_PCNF1_WHITEEN : 0))
-
-/* PREFIX0 */
-#define NRF51_RADIO_PREFIX0_AP0_SHIFT                 0
-#define NRF51_RADIO_PREFIX0_AP1_SHIFT                 8
-#define NRF51_RADIO_PREFIX0_AP2_SHIFT                 16
-#define NRF51_RADIO_PREFIX0_AP3_SHIFT                 24
-
-/* PREFIX1 */
-#define NRF51_RADIO_PREFIX1_AP4_SHIFT                 0
-#define NRF51_RADIO_PREFIX1_AP5_SHIFT                 8
-#define NRF51_RADIO_PREFIX1_AP6_SHIFT                 16
-#define NRF51_RADIO_PREFIX1_AP7_SHIFT                 24
-
-/* CRCCNF */
-#define NRF51_RADIO_CRCCNF_SKIP_ADDR                  0x100
-
-/* TEST */
-#define NRF51_RADIO_TEST_CONST_CARRIER_EN             0x01
-#define NRF51_RADIO_TEST_PLL_LOCK_EN                  0x02
-
-/* STATE */
-#define NRF51_RADIO_STATE_DISABLED                    0
-#define NRF51_RADIO_STATE_RXRU                        1
-#define NRF51_RADIO_STATE_RXIDLE                      2
-#define NRF51_RADIO_STATE_RX                          3
-#define NRF51_RADIO_STATE_RXDISABLE                   4
-#define NRF51_RADIO_STATE_TXRU                        9
-#define NRF51_RADIO_STATE_TXIDLE                      10
-#define NRF51_RADIO_STATE_TX                          11
-#define NRF51_RADIO_STATE_TXDISABLE                   12
-
-/* DACNF */
-#define NRF51_RADIO_DACNF_ENA(n)                      (1 << (n))
-#define NRF51_RADIO_DACNF_MAX                         8
-#define NRF51_RADIO_DACNF_TXADD(n)                    (1 << ((n)+8))
-#define NRF51_RADIO_TXADD_MAX                         8
-
-/* OVERRIDE4 */
-#define NRF51_RADIO_OVERRIDE_EN                       BIT(31)
-
-
-/*
- *  UART
- */
-#define NRF51_UART_BASE     0x40002000
-/* Tasks */
-#define NRF51_UART_STARTRX  REG32(NRF51_UART_BASE + 0x000)
-#define NRF51_UART_STOPRX   REG32(NRF51_UART_BASE + 0x004)
-#define NRF51_UART_STARTTX  REG32(NRF51_UART_BASE + 0x008)
-#define NRF51_UART_STOPTX   REG32(NRF51_UART_BASE + 0x00C)
-/* Events */
-#define NRF51_UART_RXDRDY   REG32(NRF51_UART_BASE + 0x108)
-#define NRF51_UART_TXDRDY   REG32(NRF51_UART_BASE + 0x11C)
-#define NRF51_UART_ERROR    REG32(NRF51_UART_BASE + 0x124)
-#define NRF51_UART_RXTO     REG32(NRF51_UART_BASE + 0x144)
-/* Registers */
-#define NRF51_UART_INTENSET REG32(NRF51_UART_BASE + 0x304)
-#define NRF51_UART_INTENCLR REG32(NRF51_UART_BASE + 0x308)
-#define NRF51_UART_ERRORSRC REG32(NRF51_UART_BASE + 0x480)
-#define NRF51_UART_ENABLE   REG32(NRF51_UART_BASE + 0x500)
-#define NRF51_UART_PSELRTS  REG32(NRF51_UART_BASE + 0x508)
-#define NRF51_UART_PSELTXD  REG32(NRF51_UART_BASE + 0x50C)
-#define NRF51_UART_PSELCTS  REG32(NRF51_UART_BASE + 0x510)
-#define NRF51_UART_PSELRXD  REG32(NRF51_UART_BASE + 0x514)
-#define NRF51_UART_RXD      REG32(NRF51_UART_BASE + 0x518)
-#define NRF51_UART_TXD      REG32(NRF51_UART_BASE + 0x51C)
-#define NRF51_UART_BAUDRATE REG32(NRF51_UART_BASE + 0x524)
-#define NRF51_UART_CONFIG   REG32(NRF51_UART_BASE + 0x56C)
-/* For UART.INTEN bits */
-#define NRF55_UART_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_UART_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instances
- */
-#define NRF51_TWI_BASE(port)     (0x40003000 + ((port == 0) ? 0 : 0x1000))
-/* Tasks */
-#define NRF51_TWI_STARTRX(port)   REG32(NRF51_TWI_BASE(port) + 0x000)
-#define NRF51_TWI_STARTTX(port)   REG32(NRF51_TWI_BASE(port) + 0x008)
-#define NRF51_TWI_STOP(port)      REG32(NRF51_TWI_BASE(port) + 0x014)
-#define NRF51_TWI_SUSPEND(port)   REG32(NRF51_TWI_BASE(port) + 0x01C)
-#define NRF51_TWI_RESUME(port)    REG32(NRF51_TWI_BASE(port) + 0x020)
-/* Events */
-#define NRF51_TWI_STOPPED(port)   REG32(NRF51_TWI_BASE(port) + 0x104)
-#define NRF51_TWI_RXDRDY(port)    REG32(NRF51_TWI_BASE(port) + 0x108)
-#define NRF51_TWI_TXDSENT(port)   REG32(NRF51_TWI_BASE(port) + 0x11C)
-#define NRF51_TWI_ERROR(port)     REG32(NRF51_TWI_BASE(port) + 0x124)
-#define NRF51_TWI_BB(port)        REG32(NRF51_TWI_BASE(port) + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI_INTEN(port)     REG32(NRF51_TWI_BASE(port) + 0x300)
-#define NRF51_TWI_INTENSET(port)  REG32(NRF51_TWI_BASE(port) + 0x304)
-#define NRF51_TWI_INTENCLR(port)  REG32(NRF51_TWI_BASE(port) + 0x308)
-#define NRF51_TWI_ERRORSRC(port)  REG32(NRF51_TWI_BASE(port) + 0x4C4)
-#define NRF51_TWI_ENABLE(port)    REG32(NRF51_TWI_BASE(port) + 0x500)
-#define NRF51_TWI_PSELSCL(port)   REG32(NRF51_TWI_BASE(port) + 0x508)
-#define NRF51_TWI_PSELSDA(port)   REG32(NRF51_TWI_BASE(port) + 0x50C)
-#define NRF51_TWI_RXD(port)       REG32(NRF51_TWI_BASE(port) + 0x518)
-#define NRF51_TWI_TXD(port)       REG32(NRF51_TWI_BASE(port) + 0x51C)
-#define NRF51_TWI_FREQUENCY(port) REG32(NRF51_TWI_BASE(port) + 0x524)
-#define NRF51_TWI_ADDRESS(port)   REG32(NRF51_TWI_BASE(port) + 0x588)
-#define NRF51_TWI_POWER(port)     REG32(NRF51_TWI_BASE(port) + 0xFFC)
-
-#define NRF51_TWI_100KBPS         0x01980000
-#define NRF51_TWI_250KBPS         0x40000000
-#define NRF51_TWI_400KBPS         0x06680000
-
-#define NRF51_TWI_ENABLE_VAL      0x5
-#define NRF51_TWI_DISABLE_VAL     0x0
-
-#define NRF51_TWI_ERRORSRC_ANACK  BIT(1) /* Address NACK */
-#define NRF51_TWI_ERRORSRC_DNACK  BIT(2) /* Data NACK */
-
-/*
- *  TWI (I2C) Instance 0
- */
-#define NRF51_TWI0_BASE     0x40003000
-/* Tasks */
-#define NRF51_TWI0_STARTRX   REG32(NRF51_TWI0_BASE + 0x000)
-#define NRF51_TWI0_STARTTX   REG32(NRF51_TWI0_BASE + 0x008)
-#define NRF51_TWI0_STOP      REG32(NRF51_TWI0_BASE + 0x014)
-#define NRF51_TWI0_SUSPEND   REG32(NRF51_TWI0_BASE + 0x01C)
-#define NRF51_TWI0_RESUME    REG32(NRF51_TWI0_BASE + 0x020)
-/* Events */
-#define NRF51_TWI0_STOPPED   REG32(NRF51_TWI0_BASE + 0x104)
-#define NRF51_TWI0_RXDRDY    REG32(NRF51_TWI0_BASE + 0x108)
-#define NRF51_TWI0_TXDSENT   REG32(NRF51_TWI0_BASE + 0x11C)
-#define NRF51_TWI0_ERROR     REG32(NRF51_TWI0_BASE + 0x124)
-#define NRF51_TWI0_BB        REG32(NRF51_TWI0_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI0_INTENSET  REG32(NRF51_TWI0_BASE + 0x304)
-#define NRF51_TWI0_INTENCLR  REG32(NRF51_TWI0_BASE + 0x308)
-#define NRF51_TWI0_ERRORSRC  REG32(NRF51_TWI0_BASE + 0x4C4)
-#define NRF51_TWI0_ENABLE    REG32(NRF51_TWI0_BASE + 0x500)
-#define NRF51_TWI0_PSELSCL   REG32(NRF51_TWI0_BASE + 0x508)
-#define NRF51_TWI0_PSELSDA   REG32(NRF51_TWI0_BASE + 0x50C)
-#define NRF51_TWI0_RXD       REG32(NRF51_TWI0_BASE + 0x518)
-#define NRF51_TWI0_TXD       REG32(NRF51_TWI0_BASE + 0x51C)
-#define NRF51_TWI0_FREQUENCY REG32(NRF51_TWI0_BASE + 0x524)
-#define NRF51_TWI0_ADDRESS   REG32(NRF51_TWI0_BASE + 0x588)
-
-/* For TWI0.INTEN bits */
-#define NRF55_TWI0_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI0_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instance 1
- */
-#define NRF51_TWI1_BASE     0x40004000
-/* Tasks */
-#define NRF51_TWI1_STARTRX   REG32(NRF51_TWI1_BASE + 0x000)
-#define NRF51_TWI1_STARTTX   REG32(NRF51_TWI1_BASE + 0x008)
-#define NRF51_TWI1_STOP      REG32(NRF51_TWI1_BASE + 0x014)
-#define NRF51_TWI1_SUSPEND   REG32(NRF51_TWI1_BASE + 0x01C)
-#define NRF51_TWI1_RESUME    REG32(NRF51_TWI1_BASE + 0x020)
-/* Events */
-#define NRF51_TWI1_STOPPED   REG32(NRF51_TWI1_BASE + 0x104)
-#define NRF51_TWI1_RXDRDY    REG32(NRF51_TWI1_BASE + 0x108)
-#define NRF51_TWI1_TXDSENT   REG32(NRF51_TWI1_BASE + 0x11C)
-#define NRF51_TWI1_ERROR     REG32(NRF51_TWI1_BASE + 0x124)
-#define NRF51_TWI1_BB        REG32(NRF51_TWI1_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI1_INTENSET  REG32(NRF51_TWI1_BASE + 0x304)
-#define NRF51_TWI1_INTENCLR  REG32(NRF51_TWI1_BASE + 0x308)
-#define NRF51_TWI1_ERRORSRC  REG32(NRF51_TWI1_BASE + 0x4C4)
-#define NRF51_TWI1_ENABLE    REG32(NRF51_TWI1_BASE + 0x500)
-#define NRF51_TWI1_PSELSCL   REG32(NRF51_TWI1_BASE + 0x508)
-#define NRF51_TWI1_PSELSDA   REG32(NRF51_TWI1_BASE + 0x50C)
-#define NRF51_TWI1_RXD       REG32(NRF51_TWI1_BASE + 0x518)
-#define NRF51_TWI1_TXD       REG32(NRF51_TWI1_BASE + 0x51C)
-#define NRF51_TWI1_FREQUENCY REG32(NRF51_TWI1_BASE + 0x524)
-#define NRF51_TWI1_ADDRESS   REG32(NRF51_TWI1_BASE + 0x588)
-
-/* For TWI1.INTEN bits */
-#define NRF55_TWI1_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI1_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  GPIOTE - GPIO Tasks and Events
- */
-#define NRF51_GPIOTE_BASE   0x40006000
-/* Tasks */
-#define NRF51_GPIOTE_OUT(n)    REG32(NRF51_GPIOTE_BASE + ((n) * 4))
-/* Events */
-#define NRF51_GPIOTE_IN(n)     REG32(NRF51_GPIOTE_BASE + 0x100 + ((n) * 4))
-#define NRF51_GPIOTE_PORT      REG32(NRF51_GPIOTE_BASE + 0x17C)
-/* Registers */
-#define NRF51_GPIOTE_INTENSET  REG32(NRF51_GPIOTE_BASE + 0x304)
-#define NRF51_GPIOTE_INTENCLR  REG32(NRF51_GPIOTE_BASE + 0x308)
-#define NRF51_GPIOTE_CONFIG(n) REG32(NRF51_GPIOTE_BASE + 0x510 + ((n) * 4))
-#define NRF51_GPIOTE_POWER     REG32(NRF51_GPIOTE_BASE + 0xFFC)
-
-/* Number of IN events */
-#define NRF51_GPIOTE_IN_COUNT  4
-
-/* Bits */
-/* For GPIOTE.INTEN */
-#define NRF51_GPIOTE_IN_BIT(n) (n)
-#define NRF51_GPIOTE_PORT_BIT  31
-/* For GPIOTE.CONFIG */
-#define NRF51_GPIOTE_MODE_DISABLED     (0<<0)
-#define NRF51_GPIOTE_MODE_EVENT        BIT(0)
-#define NRF51_GPIOTE_MODE_TASK         (3<<0)
-#define NRF51_GPIOTE_PSEL_POS          (8)
-#define NRF51_GPIOTE_POLARITY_LOTOHI   BIT(16)
-#define NRF51_GPIOTE_POLARITY_HITOLO   (2<<16)
-#define NRF51_GPIOTE_POLARITY_TOGGLE   (3<<16)
-#define NRF51_GPIOTE_OUTINIT_LOW       (0<<20)
-#define NRF51_GPIOTE_OUTINIT_HIGH      BIT(20)
-
-/*
- *  Timer / Counter
- */
-#define NRF51_TIMER0_BASE   0x40008000
-#define NRF51_TIMER_BASE(n)   (NRF51_TIMER0_BASE + (n) * 0x1000)
-#define NRF51_PERID_TIMER(n)  (NRF51_PERID_TIMER0 + (n))
-/* Tasks */
-#define NRF51_TIMER_START(n)  REG32(NRF51_TIMER_BASE(n) + 0x000)
-#define NRF51_TIMER_STOP(n)   REG32(NRF51_TIMER_BASE(n) + 0x004)
-#define NRF51_TIMER_COUNT(n)  REG32(NRF51_TIMER_BASE(n) + 0x008)
-#define NRF51_TIMER_CLEAR(n)  REG32(NRF51_TIMER_BASE(n) + 0x00C)
-#define NRF51_TIMER_CAPTURE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x040 + 4 * (c))
-/* Events */
-#define NRF51_TIMER_COMPARE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x140 + 4 * (c))
-/* Registers */
-#define NRF51_TIMER_SHORTCUT(n)  REG32(NRF51_TIMER_BASE(n) + 0x200)
-#define NRF51_TIMER_INTENSET(n)  REG32(NRF51_TIMER_BASE(n) + 0x304)
-#define NRF51_TIMER_INTENCLR(n)  REG32(NRF51_TIMER_BASE(n) + 0x308)
-#define NRF51_TIMER_MODE(n)      REG32(NRF51_TIMER_BASE(n) + 0x504)
-#define NRF51_TIMER_BITMODE(n)   REG32(NRF51_TIMER_BASE(n) + 0x508)
-#define NRF51_TIMER_PRESCALER(n) REG32(NRF51_TIMER_BASE(n) + 0x510)
-#define NRF51_TIMER_CC(n, c)     REG32(NRF51_TIMER_BASE(n) + 0x540 + 4 * (c))
-/* For Timer.INTEN bits */
-#define NRF51_TIMER_COMPARE_BIT(n)  (((0x140 - 0x100) / 4) + (n))
-/* For Timer Shortcuts */
-#define NRF51_TIMER_COMPARE_CLEAR(n)  (1 << (n))
-#define NRF51_TIMER_COMPARE_STOP(n)   (1 << (8 + (n)))
-/* Timer Mode (NRF51_TIMER_MODE) */
-#define NRF51_TIMER_MODE_TIMER   0  /* reset default */
-#define NRF51_TIMER_MODE_COUNTER 1
-/* Prescaler */
-#define NRF51_TIMER_PRESCALER_MASK (0xf)  /* range: 0-9, reset default: 4 */
-/* Bit length (NRF51_TIMER_BITMODE) */
-#define NRF51_TIMER_BITMODE_16  0  /* reset default */
-#define NRF51_TIMER_BITMODE_8   1
-#define NRF51_TIMER_BITMODE_24  2
-#define NRF51_TIMER_BITMODE_32  3
-
-
-/*
- *  Random Number Generator (RNG)
- */
-#define NRF51_RNG_BASE               0x4000D000
-/* Tasks */
-#define NRF51_RNG_START              REG32(NRF51_RNG_BASE + 0x000)
-#define NRF51_RNG_STOP               REG32(NRF51_RNG_BASE + 0x004)
-/* Events */
-#define NRF51_RNG_VALRDY             REG32(NRF51_RNG_BASE + 0x100)
-/* Registers */
-#define NRF51_RNG_SHORTS             REG32(NRF51_RNG_BASE + 0x200)
-#define NRF51_RNG_INTENSET           REG32(NRF51_RNG_BASE + 0x304)
-#define NRF51_RNG_INTENCLR           REG32(NRF51_RNG_BASE + 0x308)
-#define NRF51_RNG_CONFIG             REG32(NRF51_RNG_BASE + 0x504)
-#define NRF51_RNG_VALUE              REG32(NRF51_RNG_BASE + 0x508)
-/* For RNG Shortcuts */
-#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0)
-/* For RNG Config */
-#define NRF51_RNG_DERCEN             BIT(0)
-
-
-/*
- *  Watchdog Timer (WDT)
- */
-#define NRF51_WDT_BASE        0x40010000
-/* Tasks */
-#define NRF51_WDT_START       REG32(NRF51_WDT_BASE + 0x000)
-/* Events */
-#define NRF51_WDT_TIMEOUT     REG32(NRF51_WDT_BASE + 0x100)
-/* Registers */
-#define NRF51_WDT_INTENSET    REG32(NRF51_WDT_BASE + 0x304)
-#define NRF51_WDT_INTENCLR    REG32(NRF51_WDT_BASE + 0x308)
-#define NRF51_WDT_RUNSTATUS   REG32(NRF51_WDT_BASE + 0x400)
-#define NRF51_WDT_REQSTATUS   REG32(NRF51_WDT_BASE + 0x404)
-#define NRF51_WDT_CRV         REG32(NRF51_WDT_BASE + 0x504)
-#define NRF51_WDT_RREN        REG32(NRF51_WDT_BASE + 0x508)
-#define NRF51_WDT_CONFIG      REG32(NRF51_WDT_BASE + 0x50C)
-#define NRF51_WDT_RR(n)       REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4))
-#define NRF51_WDT_POWER       REG32(NRF51_WDT_BASE + 0xFFC)
-/* Bitfields */
-#define NRF51_WDT_RUNSTATUS_RUNNING        1
-#define NRF51_WDT_REQSTATUS_BIT(n)        (1<<(n))
-#define NRF51_WDT_RREN_BIT(n)             (1<<(n))
-#define NRF51_WDT_CONFIG_SLEEP_PAUSE       0
-#define NRF51_WDT_CONFIG_SLEEP_RUN         1
-#define NRF51_WDT_CONFIG_HALT_PAUSE       (0<<4)
-#define NRF51_WDT_CONFIG_HALT_RUN         BIT(4)
-
-#define NRF51_WDT_RELOAD_VAL             0x6E524635
-
-
-/*
- *  GPIO
- */
-#define NRF51_GPIO_BASE     0x50000000
-#define NRF51_GPIO0_BASE    (NRF51_GPIO_BASE + 0x500)
-#define NRF51_GPIO0_OUT     REG32(NRF51_GPIO0_BASE + 0x004)
-#define NRF51_GPIO0_OUTSET  REG32(NRF51_GPIO0_BASE + 0x008)
-#define NRF51_GPIO0_OUTCLR  REG32(NRF51_GPIO0_BASE + 0x00C)
-#define NRF51_GPIO0_IN      REG32(NRF51_GPIO0_BASE + 0x010)
-#define NRF51_GPIO0_DIR     REG32(NRF51_GPIO0_BASE + 0x014)  /* 1 for output */
-#define NRF51_GPIO0_DIRSET  REG32(NRF51_GPIO0_BASE + 0x018)
-#define NRF51_GPIO0_DIRCLR  REG32(NRF51_GPIO0_BASE + 0x01C)
-#define NRF51_PIN_BASE      (NRF51_GPIO_BASE + 0x700)
-#define NRF51_PIN_CNF(n)    REG32(NRF51_PIN_BASE + ((n) * 4))
-#define GPIO_0              NRF51_GPIO0_BASE
-
-#define NRF51_PIN_CNF_DIR_INPUT        (0)
-#define NRF51_PIN_CNF_DIR_OUTPUT       (1)
-#define NRF51_PIN_CNF_INPUT_CONNECT    (0<<1)
-#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1)
-#define NRF51_PIN_CNF_PULL_DISABLED    (0<<2)
-#define NRF51_PIN_CNF_PULLDOWN         BIT(2)
-#define NRF51_PIN_CNF_PULLUP           (3<<2)
-/*
- * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect
- * for example, S0D1 = Standard drive 0, disconnect on 1
- */
-#define NRF51_PIN_CNF_DRIVE_S0S1       (0<<8)
-#define NRF51_PIN_CNF_DRIVE_H0S1       BIT(8)
-#define NRF51_PIN_CNF_DRIVE_S0H1       (2<<8)
-#define NRF51_PIN_CNF_DRIVE_H0H1       (3<<8)
-#define NRF51_PIN_CNF_DRIVE_D0S1       (4<<8)
-#define NRF51_PIN_CNF_DRIVE_D0H1       (5<<8)
-#define NRF51_PIN_CNF_DRIVE_S0D1       (6<<8)
-#define NRF51_PIN_CNF_DRIVE_H0D1       (7<<8)
-
-#define NRF51_PIN_CNF_SENSE_DISABLED   (0<<16)
-#define NRF51_PIN_CNF_SENSE_HIGH       (2<<16)
-#define NRF51_PIN_CNF_SENSE_LOW        (3<<16)
-
-#define UNIMPLEMENTED_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
-
-#define NRF51_PPI_BASE                 0x4001F000
-#define NRF51_PPI_CHEN                 REG32(NRF51_PPI_BASE + 0x500)
-#define NRF51_PPI_CHENSET              REG32(NRF51_PPI_BASE + 0x504)
-#define NRF51_PPI_CHENCLR              REG32(NRF51_PPI_BASE + 0x508)
-#define NRF51_PPI_EEP(channel)         REG32(NRF51_PPI_BASE + 0x510 + channel*8)
-#define NRF51_PPI_TEP(channel)         REG32(NRF51_PPI_BASE + 0x514 + channel*8)
-#define NRF51_PPI_CHG(group)           REG32(NRF51_PPI_BASE + 0x800 + group*4)
-
-#define NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS        16
-#define NRF51_PPI_NUM_GROUPS                       4
-
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN        20
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_RXEN        21
-#define NRF51_PPI_CH_TIMER0_CC1__RADIO_DISABLE     22
-#define NRF51_PPI_CH_RADIO_BCMATCH__AAR_START      23
-#define NRF51_PPI_CH_RADIO_READY__CCM_KSGEN        24
-#define NRF51_PPI_CH_RADIO_ADDR__CCM_CRYPT         25
-#define NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1         26
-#define NRF51_PPI_CH_RADIO_END_TIMER0CC2           27
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_TXEN     28
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_RXEN     29
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_CLEAR   30
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START   31
-
-#define NRF51_PPI_CH_FIRST NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_CH_LAST  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-
-/* These will be defined in their respective functions if/when they are used. */
-#define NRF51_SPI0_BASE       0x40003000
-#define NRF51_SPI0_PSELSCK    REG32(NRF51_SPI0_BASE + 0x508)
-#define NRF51_SPI0_PSELMOSI   REG32(NRF51_SPI0_BASE + 0x50C)
-#define NRF51_SPI0_PSELMISO   REG32(NRF51_SPI0_BASE + 0x510)
-#define NRF51_SPI1_BASE       0x40004000
-#define NRF51_SPI1_PSELSCK    REG32(NRF51_SPI1_BASE + 0x508)
-#define NRF51_SPI1_PSELMOSI   REG32(NRF51_SPI1_BASE + 0x50C)
-#define NRF51_SPI1_PSELMISO   REG32(NRF51_SPI1_BASE + 0x510)
-#define NRF51_SPIS1_BASE      0x40004000
-#define NRF51_SPIS1_PSELSCK   REG32(NRF51_SPIS1_BASE + 0x508)
-#define NRF51_SPIS1_PSELMISO  REG32(NRF51_SPIS1_BASE + 0x50C)
-#define NRF51_SPIS1_PSELMOSI  REG32(NRF51_SPIS1_BASE + 0x510)
-#define NRF51_SPIS1_PSELCSN   REG32(NRF51_SPIS1_BASE + 0x514)
-#define NRF51_QDEC_BASE       0x40012000
-#define NRF51_QDEC_PSELLED    REG32(NRF51_QDEC_BASE + 0x51C)
-#define NRF51_QDEC_PSELA      REG32(NRF51_QDEC_BASE + 0x520)
-#define NRF51_QDEC_PSELB      REG32(NRF51_QDEC_BASE + 0x524)
-#define NRF51_LPCOMP_BASE     0x40013000
-#define NRF51_LPCOMP_PSEL     REG32(NRF51_LPCOMP_BASE + 0x504)
-
-#endif /* __CROS_EC_REGISTERS_H */
-
diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c
deleted file mode 100644
index dc7bff2059..0000000000
--- a/chip/nrf51/system.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "cpu.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-const char *system_get_chip_vendor(void)
-{
-	return "nrf";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "nrf51822";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_cause = NRF51_POWER_RESETREAS;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_DOG)
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	/* Note that the programmer uses a soft reset in debug mode. */
-	if (raw_cause & NRF51_POWER_RESETREAS_SREQ)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_OFF |
-			NRF51_POWER_RESETREAS_LPCOMP))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP |
-			NRF51_POWER_RESETREAS_DIF))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	system_set_reset_flags(flags);
-
-	/* clear it by writing 1's */
-	NRF51_POWER_RESETREAS = raw_cause;
-}
-
-static void system_watchdog_reset(void)
-{
-	if (NRF51_WDT_TIMEOUT != 0) {
-		/* Hard reset the WDT */
-		NRF51_WDT_POWER = 0;
-		NRF51_WDT_POWER = 1;
-	}
-
-	/* NRF51_WDT_CONFIG_HALT_RUN breaks this */
-	NRF51_WDT_CONFIG = NRF51_WDT_CONFIG_SLEEP_RUN;
-
-	NRF51_WDT_RREN = NRF51_WDT_RREN_BIT(0);
-	NRF51_WDT_CRV = 3; /* @32KHz */
-	NRF51_WDT_START = 1;
-}
-
-void system_reset(int flags)
-{
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	if (flags & SYSTEM_RESET_HARD)
-		/* Ask the watchdog to trigger a hard reboot */
-		system_watchdog_reset();
-	else {
-		/* Use SYSRESETREQ to trigger a soft reboot */
-		CPU_NVIC_APINT = 0x05fa0004;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void system_pre_init(void)
-{
-	check_reset_cause();
-}
diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c
deleted file mode 100644
index 1f546a2b79..0000000000
--- a/chip/nrf51/uart.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-static int ever_sent;    /* if we ever sent byte to TXD? */
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-	task_trigger_irq(NRF51_PERID_USART);
-}
-
-void uart_tx_stop(void)
-{
-	NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT);
-	should_stop = 1;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * nRF51 design is NOT tx-empty style. Instead, it is if a byte is
-	 * ever transmitted from TxD. This means NRF51_UART_TXDRDY is always
-	 * 0 after reset. So, we use 'ever_sent' to send the first byte.
-	 */
-	return NRF51_UART_TXDRDY || (!ever_sent);
-}
-
-int uart_rx_available(void)
-{
-	return NRF51_UART_RXDRDY;
-}
-
-void uart_tx_flush(void)
-{
-	while (!uart_tx_ready())
-		;
-}
-
-void uart_write_char(char c)
-{
-	ever_sent = 1;
-	NRF51_UART_TXDRDY = 0;
-	NRF51_UART_TXD = c;
-	NRF51_UART_STARTTX = 1;
-}
-
-int uart_read_char(void)
-{
-	NRF51_UART_RXDRDY = 0;
-	return NRF51_UART_RXD;
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	if (!should_stop)
-		NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-#endif  /* CONFIG_UART_TX_DMA */
-
-}
-DECLARE_IRQ(NRF51_PERID_USART, uart_interrupt, 2);
-
-
-void uart_init(void)
-{
-	NRF51_UART_PSELTXD = NRF51_UART_TX_PIN;   /* GPIO Port for Tx */
-	NRF51_UART_PSELRXD = NRF51_UART_RX_PIN;   /* GPIO Port for Rx */
-	NRF51_UART_CONFIG = 0;    /* disable HW flow control, no parity bit */
-	NRF51_UART_BAUDRATE = 0x01d7e000;  /* 115200 */
-	NRF51_UART_ENABLE = 0x4;  /* Enable UART */
-
-	task_enable_irq(NRF51_PERID_USART);
-
-	NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT);
-	NRF51_UART_STARTRX = 1;
-
-	init_done = 1;
-}
diff --git a/chip/nrf51/watchdog.c b/chip/nrf51/watchdog.c
deleted file mode 100644
index da947df48e..0000000000
--- a/chip/nrf51/watchdog.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "console.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-int watchdog_init(void)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c
deleted file mode 100644
index b0654132cd..0000000000
--- a/chip/stm32/adc-stm32f0.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct mutex adc_lock;
-
-struct adc_profile_t {
-	/* Register values. */
-	uint32_t cfgr1_reg;
-	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
-	uint32_t ier_reg;
-	/* DMA config. */
-	const struct dma_option *dma_option;
-	/* Size of DMA buffer, in units of ADC_CH_COUNT. */
-	int dma_buffer_size;
-};
-
-#ifdef CONFIG_ADC_PROFILE_SINGLE
-static const struct dma_option dma_single = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT,
-};
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_13_5_CY
-#endif
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels once using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	.ier_reg = 0,
-	.dma_option = &dma_single,
-	.dma_buffer_size = 1,
-};
-#endif
-
-#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY
-#endif
-
-static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
-};
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
-		     STM32_ADC_CFGR1_DMACFG,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	/* Fire interrupt at end of sequence. */
-	.ier_reg = STM32_ADC_IER_EOSEQIE,
-	.dma_option = &dma_continuous,
-	/* Double-buffer our samples. */
-	.dma_buffer_size = 2,
-};
-#endif
-
-static void adc_init(const struct adc_t *adc)
-{
-	/*
-	 * If clock is already enabled, and ADC module is enabled
-	 * then this is a warm reboot and ADC is already initialized.
-	 */
-	if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN))
-		return;
-
-	/* Enable ADC clock */
-	clock_enable_module(MODULE_ADC, 1);
-	/* check HSI14 in RCC ? ON by default */
-
-	/* ADC calibration (done with ADEN = 0) */
-	STM32_ADC_CR = STM32_ADC_CR_ADCAL; /* set ADCAL = 1, ADC off */
-	/* wait for the end of calibration */
-	while (STM32_ADC_CR & STM32_ADC_CR_ADCAL)
-		;
-
-	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = profile.cfgr1_reg;
-	/* clock is ADCCLK (ADEN must be off when writing this reg) */
-	STM32_ADC_CFGR2 = profile.cfgr2_reg;
-
-	/*
-	 * ADC enable (note: takes 4 ADC clocks between end of calibration
-	 * and setting ADEN).
-	 */
-	STM32_ADC_CR = STM32_ADC_CR_ADEN;
-	while (!(STM32_ADC_ISR & STM32_ADC_ISR_ADRDY))
-		STM32_ADC_CR = STM32_ADC_CR_ADEN;
-}
-
-static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate)
-{
-	/* Sampling time */
-	if (sample_rate == STM32_ADC_SMPR_DEFAULT ||
-			sample_rate >= STM32_ADC_SMPR_COUNT)
-		STM32_ADC_SMPR = profile.smpr_reg;
-	else
-		STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate);
-
-	/* Select channel to convert */
-	STM32_ADC_CHSELR = BIT(ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN;
-}
-
-#ifdef CONFIG_ADC_WATCHDOG
-
-static int watchdog_ain_id;
-static int watchdog_delay_ms;
-
-static void adc_continuous_read(int ain_id)
-{
-	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* CONT=1 -> continuous mode on */
-	STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT;
-
-	/* Start continuous conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-}
-
-static void adc_continuous_stop(void)
-{
-	/* Stop on-going conversion */
-	STM32_ADC_CR |= BIT(4); /* ADSTP */
-
-	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & BIT(4))
-		;
-
-	/* CONT=0 -> continuous mode off */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_CONT;
-}
-
-static void adc_interval_read(int ain_id, int interval_ms)
-{
-	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* EXTEN=01 -> hardware trigger detection on rising edge */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK)
-		| STM32_ADC_CFGR1_EXTEN_RISE;
-
-	/* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) |
-		STM32_ADC_CFGR1_TRG3;
-
-	__hw_timer_enable_clock(TIM_ADC, 1);
-
-	/* Upcounter, counter disabled, update event only on underflow */
-	STM32_TIM_CR1(TIM_ADC) = 0x0004;
-
-	/* TRGO on update event */
-	STM32_TIM_CR2(TIM_ADC) = 0x0020;
-	STM32_TIM_SMCR(TIM_ADC) = 0x0000;
-
-	/* Auto-reload value */
-	STM32_TIM_ARR(TIM_ADC) = interval_ms & 0xffff;
-
-	/* Set prescaler to tick per millisecond */
-	STM32_TIM_PSC(TIM_ADC) = (clock_get_freq() / MSEC) - 1;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_ADC) |= 1;
-
-	/* Start ADC conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-}
-
-static void adc_interval_stop(void)
-{
-	/* EXTEN=00 -> hardware trigger detection disabled */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK;
-
-	/* Set ADSTP to clear ADSTART */
-	STM32_ADC_CR |= BIT(4); /* ADSTP */
-
-	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & BIT(4))
-		;
-
-	/* Stop the timer */
-	STM32_TIM_CR1(TIM_ADC) &= ~0x1;
-}
-
-static int adc_watchdog_enabled(void)
-{
-	return STM32_ADC_CFGR1 & STM32_ADC_CFGR1_AWDEN;
-}
-
-static int adc_enable_watchdog_no_lock(void)
-{
-	/* Select channel */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_AWDCH_MASK) |
-			  (watchdog_ain_id << 26);
-	adc_configure(watchdog_ain_id, STM32_ADC_SMPR_DEFAULT);
-
-	/* Clear AWD interrupt flag */
-	STM32_ADC_ISR = 0x80;
-	/* Set Watchdog enable bit on a single channel */
-	STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_AWDEN | STM32_ADC_CFGR1_AWDSGL;
-	/* Enable interrupt */
-	STM32_ADC_IER |= STM32_ADC_IER_AWDIE;
-
-	if (watchdog_delay_ms)
-		adc_interval_read(watchdog_ain_id, watchdog_delay_ms);
-	else
-		adc_continuous_read(watchdog_ain_id);
-
-	return EC_SUCCESS;
-}
-
-int adc_enable_watchdog(int ain_id, int high, int low)
-{
-	int ret;
-
-	mutex_lock(&adc_lock);
-
-	watchdog_ain_id = ain_id;
-
-	/* Set thresholds */
-	STM32_ADC_TR = ((high & 0xfff) << 16) | (low & 0xfff);
-
-	ret = adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-static int adc_disable_watchdog_no_lock(void)
-{
-	if (watchdog_delay_ms)
-		adc_interval_stop();
-	else
-		adc_continuous_stop();
-
-	/* Clear Watchdog enable bit */
-	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_AWDEN;
-
-	return EC_SUCCESS;
-}
-
-int adc_disable_watchdog(void)
-{
-	int ret;
-
-	mutex_lock(&adc_lock);
-	ret = adc_disable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return ret;
-}
-
-int adc_set_watchdog_delay(int delay_ms)
-{
-	int resume_watchdog = 0;
-
-	mutex_lock(&adc_lock);
-	if (adc_watchdog_enabled()) {
-		resume_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	watchdog_delay_ms = delay_ms;
-
-	if (resume_watchdog)
-		adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return EC_SUCCESS;
-}
-
-#else /* CONFIG_ADC_WATCHDOG */
-
-static int adc_watchdog_enabled(void) { return 0; }
-static int adc_enable_watchdog_no_lock(void) { return 0; }
-static int adc_disable_watchdog_no_lock(void) { return 0; }
-
-#endif /* CONFIG_ADC_WATCHDOG */
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	int restore_watchdog = 0;
-
-	mutex_lock(&adc_lock);
-
-	adc_init(adc);
-
-	if (adc_watchdog_enabled()) {
-		restore_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	adc_configure(adc->channel, adc->sample_rate);
-
-	/* Clear flags */
-	STM32_ADC_ISR = 0xe;
-
-	/* Start conversion */
-	STM32_ADC_CR |= BIT(2); /* ADSTART */
-
-	/* Wait for end of conversion */
-	while (!(STM32_ADC_ISR & BIT(2)))
-		;
-	/* read converted value */
-	value = STM32_ADC_DR;
-
-	if (restore_watchdog)
-		adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-
-	return value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-void adc_disable(void)
-{
-	STM32_ADC_CR |= STM32_ADC_CR_ADDIS;
-	/*
-	 * Note that the ADC is not in OFF state immediately.
-	 * Once the ADC is effectively put into OFF state,
-	 * STM32_ADC_CR_ADDIS bit will be cleared by hardware.
-	 */
-}
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
deleted file mode 100644
index 543a44ab1a..0000000000
--- a/chip/stm32/adc-stm32f3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
-
-#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \
-			 ((v) << 12) | ((v) << 15) | ((v) << 18) | \
-			 ((v) << 21))
-#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
-
-/* Default ADC sample time = 13.5 cycles */
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME 2
-#endif
-
-struct mutex adc_lock;
-
-static int watchdog_ain_id;
-
-static inline void adc_set_channel(int sample_id, int channel)
-{
-	uint32_t mask, val;
-	volatile uint32_t *sqr_reg;
-
-	if (sample_id < 6) {
-		mask = 0x1f << (sample_id * 5);
-		val = channel << (sample_id * 5);
-		sqr_reg = &STM32_ADC_SQR3;
-	} else if (sample_id < 12) {
-		mask = 0x1f << ((sample_id - 6) * 5);
-		val = channel << ((sample_id - 6) * 5);
-		sqr_reg = &STM32_ADC_SQR2;
-	} else {
-		mask = 0x1f << ((sample_id - 12) * 5);
-		val = channel << ((sample_id - 12) * 5);
-		sqr_reg = &STM32_ADC_SQR1;
-	}
-
-	*sqr_reg = (*sqr_reg & ~mask) | val;
-}
-
-static void adc_configure(int ain_id)
-{
-	/* Set ADC channel */
-	adc_set_channel(0, ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~BIT(8);
-}
-
-static void __attribute__((unused)) adc_configure_all(void)
-{
-	int i;
-
-	/* Set ADC channels */
-	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_set_channel(i, adc_channels[i].channel);
-
-	/* Enable DMA */
-	STM32_ADC_CR2 |= BIT(8);
-
-	/* Enable scan mode */
-	STM32_ADC_CR1 |= BIT(8);
-}
-
-static inline int adc_powered(void)
-{
-	return STM32_ADC_CR2 & BIT(0);
-}
-
-static inline int adc_conversion_ended(void)
-{
-	return STM32_ADC_SR & BIT(1);
-}
-
-static int adc_watchdog_enabled(void)
-{
-	return STM32_ADC_CR1 & BIT(23);
-}
-
-static int adc_enable_watchdog_no_lock(void)
-{
-	/* Fail if watchdog already enabled */
-	if (adc_watchdog_enabled())
-		return EC_ERROR_UNKNOWN;
-
-	/* Set channel */
-	STM32_ADC_SQR3 = watchdog_ain_id;
-	STM32_ADC_SQR1 = 0;
-	STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id;
-
-	/* Clear interrupt bit */
-	STM32_ADC_SR &= ~0x1;
-
-	/* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */
-	STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* CONT=1 */
-	STM32_ADC_CR2 |= BIT(1);
-
-	/* Start conversion */
-	STM32_ADC_CR2 |= BIT(0);
-
-	return EC_SUCCESS;
-}
-
-int adc_enable_watchdog(int ain_id, int high, int low)
-{
-	int ret;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-
-	watchdog_ain_id = ain_id;
-
-	/* Set thresholds */
-	STM32_ADC_HTR = high & 0xfff;
-	STM32_ADC_LTR = low & 0xfff;
-
-	ret = adc_enable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-static int adc_disable_watchdog_no_lock(void)
-{
-	/* Fail if watchdog not running */
-	if (!adc_watchdog_enabled())
-		return EC_ERROR_UNKNOWN;
-
-	/* AWDEN=0, AWDIE=0 */
-	STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6);
-
-	/* CONT=0 */
-	STM32_ADC_CR2 &= ~BIT(1);
-
-	return EC_SUCCESS;
-}
-
-int adc_disable_watchdog(void)
-{
-	int ret;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-	ret = adc_disable_watchdog_no_lock();
-	mutex_unlock(&adc_lock);
-	return ret;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	int restore_watchdog = 0;
-	timestamp_t deadline;
-
-	if (!adc_powered())
-		return EC_ERROR_UNKNOWN;
-
-	mutex_lock(&adc_lock);
-
-	if (adc_watchdog_enabled()) {
-		restore_watchdog = 1;
-		adc_disable_watchdog_no_lock();
-	}
-
-	adc_configure(adc->channel);
-
-	/* Clear EOC bit */
-	STM32_ADC_SR &= ~BIT(1);
-
-	/* Start conversion (Note: For now only confirmed on F4) */
-#if defined(CHIP_FAMILY_STM32F4)
-	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART;
-#else
-	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
-#endif
-
-	/* Wait for EOC bit set */
-	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
-	value = ADC_READ_ERROR;
-	do {
-		if (adc_conversion_ended()) {
-			value = STM32_ADC_DR & ADC_READ_MAX;
-			break;
-		}
-	} while (!timestamp_expired(deadline, NULL));
-
-	if (restore_watchdog)
-		adc_enable_watchdog_no_lock();
-
-	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-static void adc_init(void)
-{
-	/*
-	 * Enable ADC clock.
-	 * APB2 clock is 16MHz. ADC clock prescaler is /2.
-	 * So the ADC clock is 8MHz.
-	 */
-	clock_enable_module(MODULE_ADC, 1);
-
-	/*
-	 * ADC clock is divided with respect to AHB, so no delay needed
-	 * here. If ADC clock is the same as AHB, a read on ADC
-	 * register is needed here.
-	 */
-
-	if (!adc_powered()) {
-		/* Power on ADC module */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
-
-		/* Reset calibration */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL;
-		while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL)
-			;
-
-		/* A/D Calibrate */
-		STM32_ADC_CR2 |= STM32_ADC_CR2_CAL;
-		while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL)
-			;
-	}
-
-	/* Set right alignment */
-	STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN;
-
-	/* Set sample time of all channels */
-	STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME);
-	STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME);
-}
-DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c
deleted file mode 120000
index 5e375b9dbf..0000000000
--- a/chip/stm32/adc-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-adc-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
deleted file mode 100644
index c1f1cfae4a..0000000000
--- a/chip/stm32/adc-stm32l.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "clock.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
-
-struct mutex adc_lock;
-
-static int restore_clock;
-
-static inline void adc_set_channel(int sample_id, int channel)
-{
-	uint32_t mask, val;
-	volatile uint32_t *sqr_reg;
-	int reg_id;
-
-	reg_id = 5 - sample_id / 6;
-
-	mask = 0x1f << ((sample_id % 6) * 5);
-	val = channel << ((sample_id % 6) * 5);
-	sqr_reg = &STM32_ADC_SQR(reg_id);
-
-	*sqr_reg = (*sqr_reg & ~mask) | val;
-}
-
-static void adc_configure(int ain_id)
-{
-	/* Set ADC channel */
-	adc_set_channel(0, ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~BIT(8);
-}
-
-static void adc_configure_all(void)
-{
-	int i;
-
-	/* Set ADC channels */
-	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_set_channel(i, adc_channels[i].channel);
-
-	/* Enable DMA */
-	STM32_ADC_CR2 |= BIT(8);
-
-	/* Enable scan mode */
-	STM32_ADC_CR1 |= BIT(8);
-}
-
-static inline int adc_powered(void)
-{
-	return STM32_ADC_SR & BIT(6); /* ADONS */
-}
-
-static void adc_enable_clock(void)
-{
-	STM32_RCC_APB2ENR |= BIT(9);
-	/* ADCCLK = HSI / 2 = 8MHz*/
-	STM32_ADC_CCR |= BIT(16);
-}
-
-static void adc_init(void)
-{
-	/*
-	 * For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled
-	 * for ADC.
-	 *
-	 * Note that we are not powering on ADC on EC initialization because
-	 * STM32L ADC module requires HSI clock. Instead, ADC module is powered
-	 * on/off in adc_prepare()/adc_release().
-	 */
-
-	/* Enable ADC clock. */
-	adc_enable_clock();
-
-	if (!adc_powered())
-		/* Power on ADC module */
-		STM32_ADC_CR2 |= BIT(0);  /* ADON */
-
-	/* Set right alignment */
-	STM32_ADC_CR2 &= ~BIT(11);
-
-	/*
-	 * Set sample time of all channels to 16 cycles.
-	 * Conversion takes (12+16)/8M = 3.34 us.
-	 */
-	STM32_ADC_SMPR1 = 0x24924892;
-	STM32_ADC_SMPR2 = 0x24924892;
-	STM32_ADC_SMPR3 = 0x24924892;
-}
-
-static void adc_prepare(void)
-{
-	if (!adc_powered()) {
-		clock_enable_module(MODULE_ADC, 1);
-		adc_init();
-		restore_clock = 1;
-	}
-}
-
-static void adc_release(void)
-{
-	if (restore_clock) {
-		clock_enable_module(MODULE_ADC, 0);
-		restore_clock = 0;
-	}
-
-	/*
-	 * Power down the ADC.  The ADC consumes a non-trivial amount of power,
-	 * so it's wasteful to leave it on.
-	 */
-	if (adc_powered())
-		STM32_ADC_CR2 = 0;
-}
-
-static inline int adc_conversion_ended(void)
-{
-	return STM32_ADC_SR & BIT(1);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	timestamp_t deadline;
-
-	mutex_lock(&adc_lock);
-
-	adc_prepare();
-
-	adc_configure(adc->channel);
-
-	/* Clear EOC bit */
-	STM32_ADC_SR &= ~BIT(1);
-
-	/* Start conversion */
-	STM32_ADC_CR2 |= BIT(30); /* SWSTART */
-
-	/* Wait for EOC bit set */
-	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
-	value = ADC_READ_ERROR;
-	do {
-		if (adc_conversion_ended()) {
-			value = STM32_ADC_DR & ADC_READ_MAX;
-			break;
-		}
-	} while (!timestamp_expired(deadline, NULL));
-
-	adc_release();
-
-	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
-}
diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c
deleted file mode 100644
index 8609d44f5d..0000000000
--- a/chip/stm32/adc-stm32l4.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-struct mutex adc_lock;
-
-struct adc_profile_t {
-	/* Register values. */
-	uint32_t cfgr1_reg;
-	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
-	uint32_t ier_reg;
-	/* DMA config. */
-	const struct dma_option *dma_option;
-	/* Size of DMA buffer, in units of ADC_CH_COUNT. */
-	int dma_buffer_size;
-};
-
-#ifdef CONFIG_ADC_PROFILE_SINGLE
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_12_5_CY
-#endif
-#endif
-
-#if defined(CHIP_FAMILY_STM32L4)
-#define ADC_CALIBRATION_TIMEOUT_US	100000U
-#define ADC_ENABLE_TIMEOUT_US		200000U
-#define ADC_CONVERSION_TIMEOUT_US	200000U
-
-#define NUMBER_OF_ADC_CHANNEL   2
-uint8_t adc1_initialized;
-#endif
-
-#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-
-#ifndef CONFIG_ADC_SAMPLE_TIME
-#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY
-#endif
-
-static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
-	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
-};
-
-static const struct adc_profile_t profile = {
-	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
-		     STM32_ADC_CFGR1_DMACFG,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	/* Fire interrupt at end of sequence. */
-	.ier_reg = STM32_ADC_IER_EOSEQIE,
-	.dma_option = &dma_continuous,
-	/* Double-buffer our samples. */
-	.dma_buffer_size = 2,
-};
-#endif
-
-static void adc_init(const struct adc_t *adc)
-{
-	/*
-	 * If clock is already enabled, and ADC module is enabled
-	 * then this is a warm reboot and ADC is already initialized.
-	 */
-
-	if (STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADCEN &&
-	    (STM32_ADC1_CR & STM32_ADC1_CR_ADEN))
-		return;
-
-	/* Enable ADC clock */
-	clock_enable_module(MODULE_ADC, 1);
-
-	/* set ADC clock to 20MHz */
-	STM32_ADC1_CCR &= ~0x003C0000;
-	STM32_ADC1_CCR |=  0x00080000;
-
-	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA;
-	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB;
-
-	/* Set ADC data resolution */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_CONT;
-	/* Set ADC conversion data alignment */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_ALIGN;
-	/* Set ADC delayed conversion mode */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_AUTDLY;
-}
-
-static void adc_configure(int ain_id, int ain_rank,
-		enum stm32_adc_smpr sample_rate)
-{
-	/* Select Sampling time and channel to convert */
-	if (ain_id <= 10)	{
-		STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3));
-		STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3));
-	} else	{
-		STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3));
-		STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3));
-	}
-
-	/* Setup Rank */
-	STM32_ADC1_JSQR &= ~(0x03);
-	STM32_ADC1_JSQR |= NUMBER_OF_ADC_CHANNEL - 1;
-
-	STM32_ADC1_JSQR &= ~(0x1F << (((ain_rank - 1) * 6) + 8));
-	STM32_ADC1_JSQR |= (ain_id << (((ain_rank - 1) * 6) + 8));
-
-	/* Disable DMA */
-	STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_DMAEN;
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-
-	int value = 0;
-	uint32_t wait_loop_index;
-
-	mutex_lock(&adc_lock);
-
-	if (adc1_initialized == 0) {
-		adc_init(adc);
-
-		/* Configure Injected Channel N */
-		for (uint8_t i = 0; i < NUMBER_OF_ADC_CHANNEL; i++) {
-			const struct adc_t *adc = adc_channels + i;
-
-			adc_configure(adc->channel, adc->rank,
-				      adc->sample_rate);
-		}
-
-		if ((STM32_ADC1_CR & STM32_ADC1_CR_ADEN) !=
-		    STM32_ADC1_CR_ADEN) {
-			/* Disable ADC deep power down (enabled by default after
-			 * reset state)
-			 */
-			STM32_ADC1_CR &= ~STM32_ADC1_CR_DEEPPWD;
-			/* Enable ADC internal voltage regulator */
-			STM32_ADC1_CR |= STM32_ADC1_CR_ADVREGEN;
-		}
-
-		/*
-		 * Delay for ADC internal voltage regulator stabilization.
-		 * Compute number of CPU cycles to wait for, from delay in us.
-		 *
-		 * Note: Variable divided by 2 to compensate partially
-		 * CPU processing cycles (depends on compilation optimization).
-		 *
-		 * Note: If system core clock frequency is below 200kHz, wait
-		 * time is only a few CPU processing cycles.
-		 */
-		wait_loop_index = ((20 * (80000000 / (100000 * 2))) / 10);
-		while (wait_loop_index-- != 0)
-			;
-
-		/* Run ADC self calibration */
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADCAL;
-
-		/* wait for the end of calibration */
-		wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
-		while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) {
-			if (wait_loop_index-- == 0)
-				break;
-		}
-
-		/* Enable ADC */
-		STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY;
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADEN;
-		wait_loop_index = ((ADC_ENABLE_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
-		while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) {
-			wait_loop_index--;
-			if (wait_loop_index == 0)
-				break;
-		}
-
-		adc1_initialized = 1;
-	}
-
-	/* Start injected conversion */
-	STM32_ADC1_CR |= BIT(3); /* JADSTART */
-
-	/* Wait for end of injected conversion */
-	wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US *
-			(CPU_CLOCK / (100000 * 2))) / 10);
-	while (!(STM32_ADC1_ISR & BIT(6))) {
-		if (wait_loop_index-- == 0)
-			break;
-	}
-
-	/* Clear JEOS bit */
-	STM32_ADC1_ISR |= BIT(6);
-
-	/* read converted value */
-	if (adc->rank == 1)
-		value = STM32_ADC1_JDR1;
-	if (adc->rank == 2)
-		value = STM32_ADC1_JDR2;
-
-	mutex_unlock(&adc_lock);
-
-	return value * adc->factor_mul / adc->factor_div + adc->shift;
-}
-
-void adc_disable(void)
-{
-	/* Disable ADC */
-	/* Do not Set ADDIS when ADC is disabled */
-	adc1_initialized = 0;
-
-	if (STM32_ADC1_CR & STM32_ADC1_CR_ADEN)
-		STM32_ADC1_CR |= STM32_ADC1_CR_ADDIS;
-
-	/*
-	 * Note that the ADC is not in OFF state immediately.
-	 * Once the ADC is effectively put into OFF state,
-	 * STM32_ADC_CR_ADDIS bit will be cleared by hardware.
-	 */
-}
diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h
deleted file mode 100644
index 7e3c688c14..0000000000
--- a/chip/stm32/adc_chip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32-specific ADC module for Chrome EC */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#ifdef CHIP_FAMILY_STM32L4
-enum stm32_adc_smpr {
-	STM32_ADC_SMPR_DEFAULT = 0,
-	STM32_ADC_SMPR_2_5_CY,
-	STM32_ADC_SMPR_6_5_CY,
-	STM32_ADC_SMPR_12_5_CY,
-	STM32_ADC_SMPR_24_5_CY,
-	STM32_ADC_SMPR_47_5_CY,
-	STM32_ADC_SMPR_92_5_CY,
-	STM32_ADC_SMPR_247_5_CY,
-	STM32_ADC_SMPR_640_5_CY,
-	STM32_ADC_SMPR_COUNT,
-};
-#else
-enum stm32_adc_smpr {
-	STM32_ADC_SMPR_DEFAULT = 0,
-	STM32_ADC_SMPR_1_5_CY,
-	STM32_ADC_SMPR_7_5_CY,
-	STM32_ADC_SMPR_13_5_CY,
-	STM32_ADC_SMPR_28_5_CY,
-	STM32_ADC_SMPR_41_5_CY,
-	STM32_ADC_SMPR_55_5_CY,
-	STM32_ADC_SMPR_71_5_CY,
-	STM32_ADC_SMPR_239_5_CY,
-	STM32_ADC_SMPR_COUNT,
-};
-#endif
-
-/* Data structure to define ADC channels. */
-struct adc_t {
-	const char *name;
-	int factor_mul;
-	int factor_div;
-	int shift;
-	int channel;
-#ifdef CHIP_FAMILY_STM32L4
-	int rank;
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	enum stm32_adc_smpr sample_rate;  /* Sampling Rate of the channel */
-#endif
-};
-
-/* Disable ADC module when we don't need it anymore. */
-void adc_disable(void);
-
-/* Minimum and maximum values returned by adc_read_channel(). */
-#define ADC_READ_MIN 0
-#define ADC_READ_MAX 4095
-
-/* Just plain id mapping for code readability */
-#define STM32_AIN(x) (x)
-
-/* Add for ADCs with RANK */
-#define STM32_RANK(x) (x)
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c
deleted file mode 100644
index 8c85366857..0000000000
--- a/chip/stm32/bkpdata.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <assert.h>
-
-#include "bkpdata.h"
-#include "registers.h"
-#include "system.h" /* enum system_bbram_idx */
-#include "task.h"
-
-uint16_t bkpdata_read(enum bkpdata_index index)
-{
-	if (index < 0 || index >= STM32_BKP_ENTRIES)
-		return 0;
-
-	if (index & 1)
-		return STM32_BKP_DATA(index >> 1) >> 16;
-	else
-		return STM32_BKP_DATA(index >> 1) & 0xFFFF;
-}
-
-int bkpdata_write(enum bkpdata_index index, uint16_t value)
-{
-	static struct mutex bkpdata_write_mutex;
-	int use_mutex = !in_interrupt_context();
-
-	if (index < 0 || index >= STM32_BKP_ENTRIES)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * Two entries share a single 32-bit register, lock mutex to prevent
-	 * read/mask/write races.
-	 */
-	if (use_mutex)
-		mutex_lock(&bkpdata_write_mutex);
-	if (index & 1) {
-		uint32_t val = STM32_BKP_DATA(index >> 1);
-		val = (val & 0x0000FFFF) | (value << 16);
-		STM32_BKP_DATA(index >> 1) = val;
-	} else {
-		uint32_t val = STM32_BKP_DATA(index >> 1);
-		val = (val & 0xFFFF0000) | value;
-		STM32_BKP_DATA(index >> 1) = val;
-	}
-	if (use_mutex)
-		mutex_unlock(&bkpdata_write_mutex);
-
-	return EC_SUCCESS;
-}
-
-int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb)
-{
-	*msb = 0;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	if (idx == SYSTEM_BBRAM_IDX_PD0)
-		return BKPDATA_INDEX_PD0;
-	if (idx == SYSTEM_BBRAM_IDX_PD1)
-		return BKPDATA_INDEX_PD1;
-	if (idx == SYSTEM_BBRAM_IDX_PD2)
-		return BKPDATA_INDEX_PD2;
-#endif
-	return -1;
-}
-
-uint32_t bkpdata_read_reset_flags()
-{
-	uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS);
-
-	flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16;
-
-	return flags;
-}
-
-__overridable
-void bkpdata_write_reset_flags(uint32_t save_flags)
-{
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
-	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16);
-}
diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h
deleted file mode 100644
index 14bd3517cc..0000000000
--- a/chip/stm32/bkpdata.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Backup data functionality */
-
-#ifndef __CROS_EC_BKPDATA_H
-#define __CROS_EC_BKPDATA_H
-
-#include "common.h"
-#include "registers.h"
-#include "system.h" /* enum system_bbram_idx */
-
-/* We use 16-bit BKP / BBRAM entries. */
-#define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2)
-
-enum bkpdata_index {
-	BKPDATA_INDEX_SCRATCHPAD,	     /* General-purpose scratchpad */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS,     /* Saved reset flags */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS_2,   /* Saved reset flags (cont) */
-#ifdef CONFIG_SOFTWARE_PANIC
-	BKPDATA_INDEX_SAVED_PANIC_REASON,    /* Saved panic reason */
-	BKPDATA_INDEX_SAVED_PANIC_INFO,      /* Saved panic data */
-	BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	BKPDATA_INDEX_PD0,		     /* USB-PD saved port0 state */
-	BKPDATA_INDEX_PD1,		     /* USB-PD saved port1 state */
-	BKPDATA_INDEX_PD2,		     /* USB-PD saved port2 state */
-#endif
-#ifdef CONFIG_SOFTWARE_PANIC
-	/**
-	 * Saving the panic flags in case that AP thinks the panic is new
-	 * after a hard reset.
-	 */
-	BKPDATA_INDEX_SAVED_PANIC_FLAGS,     /* Saved panic flags */
-#endif
-	BKPDATA_COUNT
-};
-BUILD_ASSERT(STM32_BKP_ENTRIES >= BKPDATA_COUNT);
-
-/**
- * Read backup register at specified index.
- *
- * @return The value of the register or 0 if invalid index.
- */
-uint16_t bkpdata_read(enum bkpdata_index index);
-
-/**
- * Write hibernate register at specified index.
- *
- * @return nonzero if error.
- */
-int bkpdata_write(enum bkpdata_index index, uint16_t value);
-
-int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb);
-uint32_t bkpdata_read_reset_flags(void);
-void bkpdata_write_reset_flags(uint32_t save_flags);
-
-#endif /* __CROS_EC_BKPDATA_H */
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
deleted file mode 100644
index 6817a3647d..0000000000
--- a/chip/stm32/build.mk
+++ /dev/null
@@ -1,106 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# STM32 chip specific files build
-#
-
-ifeq ($(CHIP_FAMILY),stm32f0)
-# STM32F0xx sub-family has a Cortex-M0 ARM core
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
-stm32g4))
-# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
-# STM32FH7xx family has a Cortex-M7 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
-# STM32FL5xx family has a Cortex-M33 ARM core
-CORE:=cortex-m
-# Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
-else
-# other STM32 SoCs have a Cortex-M3 ARM core
-CORE:=cortex-m
-# Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
-endif
-
-# Select between 16-bit and 32-bit timer for clock source
-TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,)
-DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4)$(CHIP_FAMILY_STM32H7),-stm32f4,)
-SPI_TYPE=$(if $(CHIP_FAMILY_STM32H7),-stm32h7,)
-
-chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o
-chip-$(CONFIG_COMMON_RUNTIME)+=bkpdata.o system.o
-chip-y+=clock-$(CHIP_FAMILY).o
-ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4))
-chip-y+=clock-f.o
-endif
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_SPI_CONTROLLER)+=spi_master$(SPI_TYPE).o
-chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o
-chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o
-chip-$(CONFIG_ITE_FLASH_SUPPORT)+=i2c_ite_flash_support.o
-chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o
-chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o
-chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o
-chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o
-chip-$(CONFIG_USART_HOST_COMMAND)+=usart_host_command.o
-chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o
-chip-$(HAS_TASK_CONSOLE)+=host_command_common.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-chip-$(HAS_TASK_CONSOLE)+=uart.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
-chip-$(HAS_TASK_POWERLED)+=power_led.o
-ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32g4 stm32l4 stm32l5))
-# STM32G4, STM32L4 and STM32L5 use the same flash IP block
-chip-y+=flash-stm32g4-l4.o
-else
-chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o
-endif
-ifdef CONFIG_FLASH_PHYSICAL
-chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o
-chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o
-chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o
-endif
-chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
-chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o
-chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o
-chip-$(CONFIG_OTP)+=otp-$(CHIP_FAMILY).o
-chip-$(CONFIG_PWM)+=pwm.o
-chip-$(CONFIG_RNG)+=trng.o
-
-ifeq ($(CHIP_FAMILY),stm32f4)
-chip-$(CONFIG_USB)+=usb_dwc.o usb_endpoints.o
-chip-$(CONFIG_USB_CONSOLE)+=usb_dwc_console.o
-chip-$(CONFIG_USB_POWER)+=usb_power.o
-chip-$(CONFIG_STREAM_USB)+=usb_dwc_stream.o
-else
-chip-$(CONFIG_STREAM_USB)+=usb-stream.o
-chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o
-chip-$(CONFIG_USB_CONSOLE)+=usb_console.o
-chip-$(CONFIG_USB_GPIO)+=usb_gpio.o
-chip-$(CONFIG_USB_HID)+=usb_hid.o
-chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o
-chip-$(CONFIG_USB_HID_TOUCHPAD)+=usb_hid_touchpad.o
-chip-$(CONFIG_USB_ISOCHRONOUS)+=usb_isochronous.o
-chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
-chip-$(CONFIG_USB_SPI)+=usb_spi.o
-endif
-chip-$(CONFIG_USB_PD_TCPM_STM32GX)+=ucpd-stm32gx.o
diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c
deleted file mode 100644
index b32b9f3ac0..0000000000
--- a/chip/stm32/charger_detect.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Detect what adapter is connected */
-
-#include "charge_manager.h"
-#include "hooks.h"
-#include "registers.h"
-#include "timer.h"
-
-static void enable_usb(void)
-{
-	/* Enable USB device clock. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-}
-DECLARE_HOOK(HOOK_INIT, enable_usb, HOOK_PRIO_DEFAULT);
-
-static void disable_usb(void)
-{
-	/* Disable USB device clock. */
-	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, disable_usb, HOOK_PRIO_DEFAULT);
-
-static uint16_t detect_type(uint16_t det_type)
-{
-	STM32_USB_BCDR &= 0;
-	usleep(1);
-	STM32_USB_BCDR |= (STM32_USB_BCDR_BCDEN | det_type);
-	usleep(1);
-	STM32_USB_BCDR &= ~(STM32_USB_BCDR_BCDEN | det_type);
-	return STM32_USB_BCDR;
-}
-
-
-int charger_detect_get_device_type(void)
-{
-	uint16_t pdet_result;
-
-	if (!(detect_type(STM32_USB_BCDR_DCDEN) & STM32_USB_BCDR_DCDET))
-		return CHARGE_SUPPLIER_PD;
-
-	pdet_result = detect_type(STM32_USB_BCDR_PDEN);
-	/* TODO: add support for detecting proprietary chargers. */
-	if (pdet_result & STM32_USB_BCDR_PDET) {
-		if (detect_type(STM32_USB_BCDR_SDEN) & STM32_USB_BCDR_SDET)
-			return CHARGE_SUPPLIER_BC12_DCP;
-		else
-			return CHARGE_SUPPLIER_BC12_CDP;
-	} else if (pdet_result & STM32_USB_BCDR_PS2DET)
-		return CHARGE_SUPPLIER_PROPRIETARY;
-	else
-		return CHARGE_SUPPLIER_BC12_SDP;
-}
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c
deleted file mode 100644
index 1a77d8ad60..0000000000
--- a/chip/stm32/clock-f.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "rtc.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* Convert decimal to BCD */
-static uint8_t u8_to_bcd(uint8_t val)
-{
-	/* Fast division by 10 (when lacking HW div) */
-	uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19;
-	uint32_t rem = val - quot * 10;
-
-	return rem | (quot << 4);
-}
-
-/* Convert between RTC regs in BCD and seconds */
-static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
-{
-	uint32_t sec;
-
-	/* convert the hours field */
-	sec = (((rtc_tr & 0x300000) >> 20) * 10 +
-	       ((rtc_tr & 0xf0000) >> 16)) * 3600;
-	/* convert the minutes field */
-	sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60;
-	/* convert the seconds field */
-	sec += ((rtc_tr & 0x70) >> 4) * 10 + (rtc_tr & 0xf);
-	return sec;
-}
-
-static uint32_t sec_to_rtc_tr(uint32_t sec)
-{
-	uint32_t rtc_tr;
-	uint8_t hour;
-	uint8_t min;
-
-	sec %= SECS_PER_DAY;
-	/* convert the hours field */
-	hour = sec / 3600;
-	rtc_tr = u8_to_bcd(hour) << 16;
-	/* convert the minutes field */
-	sec -= hour * 3600;
-	min = sec / 60;
-	rtc_tr |= u8_to_bcd(min) << 8;
-	/* convert the seconds field */
-	sec -= min * 60;
-	rtc_tr |= u8_to_bcd(sec);
-
-	return rtc_tr;
-}
-
-/* Register setup before RTC alarm is allowed for update */
-static void pre_work_set_rtc_alarm(void)
-{
-	rtc_unlock_regs();
-
-	/* Make sure alarm is disabled */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF))
-		;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-}
-
-/* Register setup after RTC alarm is updated */
-static void post_work_set_rtc_alarm(void)
-{
-	STM32_EXTI_PR = EXTI_RTC_ALR_EVENT;
-
-	/* Enable alarm and alarm interrupt */
-	STM32_EXTI_IMR |= EXTI_RTC_ALR_EVENT;
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAE;
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static struct wake_time host_wake_time;
-
-int is_host_wake_alarm_expired(timestamp_t ts)
-{
-	return host_wake_time.ts.val &&
-	       timestamp_expired(host_wake_time.ts, &ts);
-}
-
-void restore_host_wake_alarm(void)
-{
-	if (!host_wake_time.ts.val)
-		return;
-
-	pre_work_set_rtc_alarm();
-
-	/* Set alarm time */
-	STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar;
-
-	post_work_set_rtc_alarm();
-}
-
-static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
-{
-	struct calendar_date time;
-	uint32_t sec;
-
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
-	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
-
-	sec = date_to_sec(time);
-
-	return sec;
-}
-
-static uint32_t sec_to_rtc_dr(uint32_t sec)
-{
-	struct calendar_date time;
-	uint32_t rtc_dr;
-
-	time = sec_to_date(sec);
-
-	rtc_dr = u8_to_bcd(time.year) << 16;
-	rtc_dr |= u8_to_bcd(time.month) << 8;
-	rtc_dr |= u8_to_bcd(time.day);
-
-	return rtc_dr;
-}
-#endif
-
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc)
-{
-	uint32_t sec = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	sec = rtc_dr_to_sec(rtc->rtc_dr);
-#endif
-	return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) +
-	       rtc_tr_to_sec(rtc->rtc_tr);
-}
-
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc)
-{
-	rtc->rtc_dr = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	rtc->rtc_dr = sec_to_rtc_dr(sec);
-#endif
-	rtc->rtc_tr = sec_to_rtc_tr(sec);
-	rtc->rtc_ssr = 0;
-}
-
-/* Return sub-10-sec time diff between two rtc readings
- *
- * Note: this function assumes rtc0 was sampled before rtc1.
- * Additionally, this function only looks at the difference mod 10
- * seconds.
- */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1)
-{
-	uint32_t rtc0_val, rtc1_val, diff;
-
-	rtc0_val = (rtc0->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc0->rtc_ssr);
-	rtc1_val = (rtc1->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc1->rtc_ssr);
-	diff = rtc1_val;
-	if (rtc1_val < rtc0_val) {
-		/* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add
-		 * 10 seconds to get the correct value
-		 */
-		diff += 10 * SECOND;
-	}
-	diff -= rtc0_val;
-	return diff;
-}
-
-void rtc_read(struct rtc_time_reg *rtc)
-{
-	/*
-	 * Read current time synchronously. Each register must be read
-	 * twice with identical values because glitches may occur for reads
-	 * close to the RTCCLK edge.
-	 */
-	do {
-		rtc->rtc_dr = STM32_RTC_DR;
-
-		do {
-			rtc->rtc_tr = STM32_RTC_TR;
-
-			do {
-				rtc->rtc_ssr = STM32_RTC_SSR;
-			} while (rtc->rtc_ssr != STM32_RTC_SSR);
-
-		} while (rtc->rtc_tr != STM32_RTC_TR);
-
-	} while (rtc->rtc_dr != STM32_RTC_DR);
-}
-
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm)
-{
-	uint32_t alarm_sec = 0;
-	uint32_t alarm_us = 0;
-
-	if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) {
-		reset_rtc_alarm(rtc);
-		return;
-	}
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY);
-
-	pre_work_set_rtc_alarm();
-	rtc_read(rtc);
-
-	/* Calculate alarm time */
-	alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s;
-
-	if (delay_us) {
-		alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us;
-		alarm_sec = alarm_sec + alarm_us / SECOND;
-		alarm_us = alarm_us % SECOND;
-	}
-
-	/*
-	 * If seconds is greater than 1 day, subtract by 1 day to deal with
-	 * 24-hour rollover.
-	 */
-	if (alarm_sec >= SECS_PER_DAY)
-		alarm_sec -= SECS_PER_DAY;
-
-	/*
-	 * Set alarm time in seconds and check for match on
-	 * hours, minutes, and seconds.
-	 */
-	STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000;
-
-	/*
-	 * Set alarm time in subseconds and check for match on subseconds.
-	 * If the caller doesn't specify subsecond delay (e.g. host command),
-	 * just align the alarm time to second.
-	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/*
-	 * If alarm is set by the host, preserve the wake time timestamp
-	 * and alarm registers.
-	 */
-	if (save_alarm) {
-		host_wake_time.ts.val = delay_s * SECOND + get_time().val;
-		host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR;
-	}
-#endif
-	post_work_set_rtc_alarm();
-}
-
-uint32_t get_rtc_alarm(void)
-{
-	struct rtc_time_reg now;
-	uint32_t now_sec;
-	uint32_t alarm_sec;
-
-	if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE))
-		return 0;
-
-	rtc_read(&now);
-
-	now_sec = rtc_tr_to_sec(now.rtc_tr);
-	alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff);
-
-	return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) +
-	       (alarm_sec - now_sec);
-}
-
-void reset_rtc_alarm(struct rtc_time_reg *rtc)
-{
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-
-	/* Disable RTC alarm interrupt */
-	STM32_EXTI_IMR &= ~EXTI_RTC_ALR_EVENT;
-	STM32_EXTI_PR = EXTI_RTC_ALR_EVENT;
-
-	/* Clear the pending RTC alarm IRQ in NVIC */
-	task_clear_pending_irq(STM32_IRQ_RTC_ALARM);
-
-	/* Read current time */
-	rtc_read(rtc);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-test_mockable
-void __rtc_alarm_irq(void)
-{
-	struct rtc_time_reg rtc;
-	reset_rtc_alarm(&rtc);
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/* Wake up the host if there is a saved rtc wake alarm. */
-	if (host_wake_time.ts.val) {
-		host_wake_time.ts.val = 0;
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-	}
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
-
-__attribute__((weak))
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_init(void)
-{
-	/*
-	 * The initial state :
-	 *  SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/*
-	 * put 1 Wait-State for flash access to ensure proper reads at 48Mhz
-	 * and enable prefetch buffer.
-	 */
-	STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN;
-
-#ifdef CHIP_FAMILY_STM32F4
-	/* Enable data and instruction cache. */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN;
-#endif
-
-	config_hispeed_clock();
-
-	rtc_init();
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-void reset_flash_cache(void)
-{
-	/* Disable data and instruction cache. */
-	STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN);
-
-	/* Reset data and instruction cache */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST;
-}
-DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	sec = rtc_to_sec(&rtc);
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-#ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	char *e;
-	uint32_t t;
-
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		t = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		rtc_set(t);
-	} else if (argc > 1)
-		return EC_ERROR_INVAL;
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
-
-#ifdef CONFIG_CMD_RTC_ALARM
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	struct rtc_time_reg rtc;
-	char *e;
-
-	ccprintf("Setting RTC alarm\n");
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	set_rtc_alarm(s, us, &rtc, 0);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
-#endif /* CONFIG_CMD_RTC_ALARM */
-#endif /* CONFIG_CMD_RTC */
-
-/*****************************************************************************/
-/* Host commands */
-
-#ifdef CONFIG_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	r->time = rtc_to_sec(&rtc);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	rtc_set(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
-{
-	struct rtc_time_reg rtc;
-	const struct ec_params_rtc *p = args->params;
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	if (p->time >= SECS_PER_DAY)
-		return EC_RES_INVALID_PARAM;
-
-	set_rtc_alarm(p->time, 0, &rtc, 1);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
-
-static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = get_rtc_alarm();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
-
-#endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h
deleted file mode 100644
index 4662b043cb..0000000000
--- a/chip/stm32/clock-f.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#ifndef __CROS_EC_CLOCK_F_H
-#define __CROS_EC_CLOCK_F_H
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Lock and unlock RTC write access */
-static inline void rtc_lock_regs(void)
-{
-	STM32_RTC_WPR = 0xff;
-}
-static inline void rtc_unlock_regs(void)
-{
-	STM32_RTC_WPR = 0xca;
-	STM32_RTC_WPR = 0x53;
-}
-
-struct rtc_time_reg {
-	uint32_t rtc_ssr; /* subseconds */
-	uint32_t rtc_tr; /* hours, minutes, seconds */
-	uint32_t rtc_dr; /* years, months, dates, week days */
-};
-
-/* Save the RTC alarm wake time */
-struct wake_time {
-	timestamp_t ts;
-	uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */
-};
-
-/* Convert between RTC regs in BCD and seconds */
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc);
-
-/* Convert between seconds and RTC regs */
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc);
-
-/* Calculate microseconds from rtc sub-second register. */
-int32_t rtcss_to_us(uint32_t rtcss);
-
-/* Calculate rtc sub-second register value from microseconds. */
-uint32_t us_to_rtcss(int32_t us);
-
-/* Return sub-10-sec time diff between two rtc readings */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1);
-
-/* Read RTC values */
-void rtc_read(struct rtc_time_reg *rtc);
-
-/* Set RTC value */
-void rtc_set(uint32_t sec);
-
-/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm);
-
-/* Clear RTC wakeup */
-void reset_rtc_alarm(struct rtc_time_reg *rtc);
-
-/*
- * Return the remaining seconds before the RTC alarm goes off.
- * Sub-seconds are ignored. Returns 0 if alarm is not set.
- */
-uint32_t get_rtc_alarm(void);
-
-/* RTC init */
-void rtc_init(void);
-
-/* Init clock blocks and functionality */
-void clock_init(void);
-
-/* Init high speed clock config */
-void config_hispeed_clock(void);
-
-/* Get timer clock frequency (for STM32 only) */
-int clock_get_timer_freq(void);
-
-/*
- * Return 1 if host_wake_time is nonzero and the saved host_wake_time
- * is expired at a given time, ts.
- */
-int is_host_wake_alarm_expired(timestamp_t ts);
-
-/* Set RTC wakeup based on the value saved in host_wake_time */
-void restore_host_wake_alarm(void);
-
-#endif  /* __CROS_EC_CLOCK_F_H */
diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h
deleted file mode 100644
index d237b84580..0000000000
--- a/chip/stm32/clock-l4.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#ifndef __CROS_EC_CLOCK_L4_H
-#define __CROS_EC_CLOCK_L4_H
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define STM32L4_RTC_REQ 1000000
-#define STM32L4_LSI_CLOCK 32000
-
-/* Lock and unlock RTC write access */
-static inline void rtc_lock_regs(void)
-{
-	STM32_RTC_WPR = 0xff;
-}
-static inline void rtc_unlock_regs(void)
-{
-	STM32_RTC_WPR = 0xca;
-	STM32_RTC_WPR = 0x53;
-}
-
-struct rtc_time_reg {
-	uint32_t rtc_ssr; /* subseconds */
-	uint32_t rtc_tr; /* hours, minutes, seconds */
-	uint32_t rtc_dr; /* years, months, dates, week days */
-};
-
-/* Save the RTC alarm wake time */
-struct wake_time {
-	timestamp_t ts;
-	uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */
-};
-
-/* Convert between RTC regs in BCD and seconds */
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc);
-
-/* Convert between seconds and RTC regs */
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc);
-
-/* Calculate microseconds from rtc sub-second register. */
-uint32_t rtcss_to_us(uint32_t rtcss);
-
-/* Calculate rtc sub-second register value from microseconds. */
-uint32_t us_to_rtcss(uint32_t us);
-
-/* Return sub-10-sec time diff between two rtc readings */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1);
-
-/* Read RTC values */
-void rtc_read(struct rtc_time_reg *rtc);
-
-/* Set RTC value */
-void rtc_set(uint32_t sec);
-
-/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm);
-
-/* Clear RTC wakeup */
-void reset_rtc_alarm(struct rtc_time_reg *rtc);
-
-/*
- * Return the remaining seconds before the RTC alarm goes off.
- * Sub-seconds are ignored. Returns 0 if alarm is not set.
- */
-uint32_t get_rtc_alarm(void);
-
-/* RTC init */
-void rtc_init(void);
-
-/* Init clock blocks and functionality */
-void clock_init(void);
-
-/* Init high speed clock config */
-void config_hispeed_clock(void);
-
-/* Get timer clock frequency (for STM32 only) */
-int clock_get_timer_freq(void);
-
-/*
- * Return 1 if host_wake_time is nonzero and the saved host_wake_time
- * is expired at a given time, ts.
- */
-bool is_host_wake_alarm_expired(timestamp_t ts);
-
-/* Set RTC wakeup based on the value saved in host_wake_time */
-void restore_host_wake_alarm(void);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-void low_power_init(void);
-#endif
-
-#endif  /* __CROS_EC_CLOCK_L4_H */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
deleted file mode 100644
index 0f63bdd394..0000000000
--- a/chip/stm32/clock-stm32f0.c
+++ /dev/null
@@ -1,503 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* use 48Mhz USB-synchronized High-speed oscillator */
-#define HSI48_CLOCK 48000000
-
-/* use PLL at 38.4MHz as system clock. */
-#define PLL_CLOCK 38400000
-
-/* Low power idle statistics */
-#ifdef CONFIG_LOW_POWER_IDLE
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/*
- * minimum delay to enter stop mode
- *
- * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low
- * power mode is 5 us + PLL locking time is 200us.
- *
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- * For STM32F3, we are using HSE, which requires additional time to start up.
- * Therefore, the latency for STM32F3 is set longer.
- *
- * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is
- * called and the host alarm is actually restored. In practice, the max latency
- * is measured as ~600us. 1000us should be conservative enough to guarantee
- * we won't miss the host alarm.
- */
-#ifdef CHIP_VARIANT_STM32F373
-#define STOP_MODE_LATENCY 500  /* us */
-#elif defined(CHIP_VARIANT_STM32F05X)
-#define STOP_MODE_LATENCY 300  /* us */
-#elif (CPU_CLOCK == PLL_CLOCK)
-#define STOP_MODE_LATENCY 300   /* us */
-#else
-#define STOP_MODE_LATENCY 50    /* us */
-#endif
-#define SET_RTC_MATCH_DELAY 200 /* us */
-
-#ifdef CONFIG_HOSTCMD_RTC
-#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */
-#endif
-
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-/*
- * RTC clock frequency (By default connected to LSI clock)
- *
- * The LSI on any given chip can be between 30 kHz to 60 kHz.
- * Without calibration, LSI frequency may be off by as much as 50%.
- *
- * Set synchronous clock freq to (RTC clock source / 2) to maximize
- * subsecond resolution. Set asynchronous clock to 1 Hz.
- */
-
-#define RTC_PREDIV_A 1
-#ifdef CONFIG_STM32_CLOCK_LSE
-#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */
-/* GCD(RTC_FREQ, 1000000) */
-#define RTC_GCD 64
-#else /* LSI clock, 40kHz-ish */
-#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */
-/* GCD(RTC_FREQ, 1000000) */
-#define RTC_GCD 20000
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-
-/*
- * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms
- * for conversion calculations to fit in 32 bits.
- */
-#define US_GCD (1000000 / RTC_GCD)
-#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD)
-
-int32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD;
-}
-
-uint32_t us_to_rtcss(int32_t us)
-{
-	return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD;
-}
-
-void config_hispeed_clock(void)
-{
-#ifdef CHIP_FAMILY_STM32F3
-	/* Ensure that HSE is ON */
-	wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17));
-
-	/*
-	 * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
-	 * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz
-	 * ADCCLK = PCLK / 6 = 4MHz
-	 * USB uses SYSCLK = 48MHz
-	 */
-	STM32_RCC_CFGR = 0x0041a400;
-
-	/* Enable the PLL */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until the PLL is ready */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* Wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-/* F03X and F05X and F070 don't have HSI48 */
-#elif defined(CHIP_VARIANT_STM32F03X) || \
-defined(CHIP_VARIANT_STM32F05X) || \
-defined(CHIP_VARIANT_STM32F070)
-	/* If PLL is the clock source, PLL has already been set up. */
-	if ((STM32_RCC_CFGR & 0xc) == 0x8)
-		return;
-
-	/* Ensure that HSI is ON */
-	wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1));
-
-	/*
-	 * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
-	 * therefore PCLK = FCLK = SYSCLK = 48MHz
-	 */
-	/* Switch the PLL source to HSI/2 */
-	STM32_RCC_CFGR &= ~(0x00018000);
-
-	/*
-	 * Specify HSI/2 clock as input clock to PLL and set PLL (*12).
-	 */
-	STM32_RCC_CFGR |= 0x00280000;
-
-	/* Enable the PLL. */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until PLL is ready. */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL. */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-#else
-	/* Ensure that HSI48 is ON */
-	wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17));
-
-#if (CPU_CLOCK == HSI48_CLOCK)
-	/*
-	 * HSI48 = 48MHz, no prescaler, no MCO, no PLL
-	 * therefore PCLK = FCLK = SYSCLK = 48MHz
-	 * USB uses HSI48 = 48MHz
-	 */
-
-#ifdef CONFIG_USB
-	/*
-	 * Configure and enable Clock Recovery System
-	 *
-	 * Since we are running from the internal RC HSI48 clock, the CSR
-	 * is needed to guarantee an accurate 48MHz clock for USB.
-	 *
-	 * The default values configure the CRS to use the periodic USB SOF
-	 * as the SYNC signal for calibrating the HSI48.
-	 *
-	 */
-
-	/* Enable Clock Recovery System */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS;
-
-	/* Enable automatic trimming */
-	STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN;
-
-	/* Enable oscillator clock for the frequency error counter */
-	STM32_CRS_CR |= STM32_CRS_CR_CEN;
-#endif
-
-	/* switch SYSCLK to HSI48 */
-	STM32_RCC_CFGR = 0x00000003;
-
-	/* wait until the HSI48 is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0xc)
-		;
-
-#elif (CPU_CLOCK == PLL_CLOCK)
-	/*
-	 * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK
-	 * therefore PCLK = FCLK = SYSCLK = 38.4MHz
-	 * USB uses HSI48 = 48MHz
-	 */
-
-	/* If PLL is the clock source, PLL has already been set up. */
-	if ((STM32_RCC_CFGR & 0xc) == 0x8)
-		return;
-
-	/*
-	 * Specify HSI48 clock as input clock to PLL and set PLL multiplier
-	 * and divider.
-	 */
-	STM32_RCC_CFGR = 0x00098000;
-	STM32_RCC_CFGR2 = 0x4;
-
-	/* Enable the PLL. */
-	STM32_RCC_CR |= 0x01000000;
-
-	/* Wait until PLL is ready. */
-	while (!(STM32_RCC_CR & 0x02000000))
-		;
-
-	/* Switch SYSCLK to PLL. */
-	STM32_RCC_CFGR |= 0x2;
-
-	/* wait until the PLL is the clock source */
-	while ((STM32_RCC_CFGR & 0xc) != 0x8)
-		;
-
-#else
-#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
-#endif
-#endif
-}
-
-#ifdef CONFIG_HIBERNATE
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	struct rtc_time_reg rtc;
-
-	if (seconds || microseconds)
-		set_rtc_alarm(seconds, microseconds, &rtc, 0);
-
-	/* interrupts off now */
-	asm volatile("cpsid i");
-
-#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
-	/* enable the wake up pins */
-	STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
-#endif
-	STM32_PWR_CR |= 0xe;
-	CPU_SCB_SYSCTRL |= 0x4;
-	/* go to Standby mode */
-	asm("wfi");
-
-	/* we should never reach that point */
-	while (1)
-		;
-}
-#endif
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void restore_host_wake_alarm_deferred(void)
-{
-	restore_host_wake_alarm();
-}
-DECLARE_DEFERRED(restore_host_wake_alarm_deferred);
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-		if (idle_is_disabled())
-			goto en_int;
-#endif
-
-		if (DEEP_SLEEP_ALLOWED &&
-#ifdef CONFIG_HOSTCMD_RTC
-		    /*
-		     * Don't go to deep sleep mode if we might miss the
-		     * wake alarm that the host requested. Note that the
-		     * host alarm always aligns to second. Considering the
-		     * worst case, we have to ensure alarm won't go off
-		     * within RESTORE_HOST_ALARM_LATENCY + 1 second after
-		     * EC exits deep sleep mode.
-		     */
-		    !is_host_wake_alarm_expired(
-			(timestamp_t)(next_delay + t0.val + SECOND +
-				      RESTORE_HOST_ALARM_LATENCY)) &&
-#endif
-		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY,
-				      &rtc0, 0);
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			uart_enable_wakeup(0);
-
-			/*
-			 * By default only HSI 8MHz is enabled here. Re-enable
-			 * high-speed clock if in use.
-			 */
-			config_hispeed_clock();
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-#ifdef CONFIG_HOSTCMD_RTC
-			hook_call_deferred(
-				&restore_host_wake_alarm_deferred_data, 0);
-#endif
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-en_int:
-#endif
-		asm volatile("cpsie i");
-	}
-}
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-int clock_get_freq(void)
-{
-	return CPU_CLOCK;
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_ADC) {
-		if (enable)
-			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN;
-		else
-			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN;
-		return;
-	} else if (module == MODULE_USB) {
-		if (enable)
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-		else
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-	}
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	if (module == MODULE_ADC)
-		return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN);
-	else if (module == MODULE_USB)
-		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
-	return 0;
-}
-
-void rtc_init(void)
-{
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME)
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif
diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c
deleted file mode 120000
index be91154e52..0000000000
--- a/chip/stm32/clock-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-clock-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
deleted file mode 100644
index a50f5f51dd..0000000000
--- a/chip/stm32/clock-stm32f4.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_HSE,	/* High-speed external oscillator */
-	OSC_PLL,	/* PLL */
-};
-
-/*
- * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz
- * MCO outputs are selected here but are not changeable later.
- * A CONFIG may be needed if other boards have different MCO
- * requirements.
- */
-#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE  */ \
-			     (0 << 27) | /* MCO2 div / 4 */ \
-			     (6 << 24) | /* MCO1 div / 4 */ \
-			     (3 << 21))  /* MCO1 <- PLL  */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-/* RTC clock must 1 Mhz when derived from HSE */
-#define RTC_DIV DIV_ROUND_NEAREST(CONFIG_STM32_CLOCK_HSE_HZ, STM32F4_RTC_REQ)
-#else /* !CONFIG_STM32_CLOCK_HSE_HZ */
-/* RTC clock not derived from HSE, turn it off */
-#define RTC_DIV 0
-#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
-
-
-/* Bus clocks dividers depending on the configuration */
-/*
- * max speed configuration with the PLL ON
- * as defined in the registers file.
- * For STM32F446: max 45 MHz
- * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz
- */
-#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG  | \
-				    CFGR_RTCPRE(RTC_DIV) | \
-				    CFGR_PPRE2(STM32F4_APB2_PRE) | \
-				    CFGR_PPRE1(STM32F4_APB1_PRE) | \
-				    CFGR_HPRE(STM32F4_AHB_PRE))
-/*
- * lower power configuration without the PLL
- * the frequency will be low (8-24Mhz), we don't want dividers to the
- * peripheral clocks, put /1 everywhere.
- */
-#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \
-				  CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0))
-
-/* PLL output frequency */
-#define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV)
-
-/* current clock settings (PLL is initialized at startup) */
-static int current_osc = OSC_PLL;
-static int current_io_freq = STM32F4_IO_CLOCK;
-static int current_timer_freq = STM32F4_TIMER_CLOCK;
-
-/* the EC code expects to get the USART/I2C clock frequency here (APB clock) */
-int clock_get_freq(void)
-{
-	return current_io_freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return current_timer_freq;
-}
-
-static void clock_enable_osc(enum clock_osc osc, bool enabled)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_HSE:
-		ready = STM32_RCC_CR_HSERDY;
-		on = STM32_RCC_CR_HSEON;
-		break;
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLLRDY;
-		on = STM32_RCC_CR_PLLON;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/* Turn off the oscillator, but don't wait for shutdown */
-	if (!enabled) {
-		STM32_RCC_CR &= ~on;
-		return;
-	}
-
-	/* Turn on the oscillator if not already on */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI | RCC_CFGR_DIVIDERS_NO_PLL;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_HSE:
-		sw = STM32_RCC_CFGR_SW_HSE | RCC_CFGR_DIVIDERS_NO_PLL;
-		sws = STM32_RCC_CFGR_SWS_HSE;
-		break;
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL | RCC_CFGR_DIVIDERS_WITH_PLL;
-		sws = STM32_RCC_CFGR_SWS_PLL;
-		break;
-	default:
-		return;
-	}
-
-	STM32_RCC_CFGR = sw;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
-		;
-}
-
-void clock_set_osc(enum clock_osc osc)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (osc == current_osc)
-		return;
-
-	hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	default:
-	case OSC_HSI:
-		/* new clock settings: no dividers */
-		current_io_freq = STM32F4_HSI_CLOCK;
-		current_timer_freq = STM32F4_HSI_CLOCK;
-		/* Switch to HSI */
-		clock_switch_osc(OSC_HSI);
-		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		break;
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	case OSC_HSE:
-		/* new clock settings: no dividers */
-		current_io_freq = CONFIG_STM32_CLOCK_HSE_HZ;
-		current_timer_freq = CONFIG_STM32_CLOCK_HSE_HZ;
-		/* Switch to HSE */
-		clock_switch_osc(OSC_HSE);
-		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		break;
-#endif /* CONFIG_STM32_CLOCK_HSE_HZ */
-
-	case OSC_PLL:
-		/* new clock settings */
-		current_io_freq = STM32F4_IO_CLOCK;
-		current_timer_freq = STM32F4_TIMER_CLOCK;
-		/* turn on PLL and wait until it's ready */
-		clock_enable_osc(OSC_PLL, true);
-		/*
-		 * Increase flash latency before transition the clock
-		 * Use the minimum Wait States value optimized for the platform.
-		 */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY;
-		/* read-back the latency as advised by the Reference Manual */
-		unused = STM32_FLASH_ACR;
-		/* Switch to PLL */
-		clock_switch_osc(OSC_PLL);
-
-		break;
-	}
-
-	current_osc = osc;
-	hook_notify(HOOK_FREQ_CHANGE);
-}
-
-static void clock_pll_configure(void)
-{
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	int srcclock = CONFIG_STM32_CLOCK_HSE_HZ;
-#else
-	int srcclock = STM32F4_HSI_CLOCK;
-#endif
-	int plldiv, pllinputclock;
-	int pllmult, vcoclock;
-	int systemclock;
-	int usbdiv;
-	int i2sdiv;
-
-	/* PLL input must be between 1-2MHz, near 2 */
-	/* Valid values 2-63 */
-	plldiv = (srcclock + STM32F4_PLL_REQ - 1) / STM32F4_PLL_REQ;
-	pllinputclock = srcclock / plldiv;
-
-	/* PLL output clock: Must be 100-432MHz */
-	pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock;
-	vcoclock = pllinputclock * pllmult;
-
-	/* CPU/System clock */
-	systemclock = vcoclock / STM32F4_PLLP_DIV;
-	/* USB clock = 48MHz exactly */
-	usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ;
-	assert(vcoclock / usbdiv == STM32F4_USB_REQ);
-
-	/* SYSTEM/I2S: same system clock */
-	i2sdiv = (vcoclock + (systemclock / 2)) / systemclock;
-
-	/* Set up PLL */
-	STM32_RCC_PLLCFGR =
-		PLLCFGR_PLLM(plldiv) |
-		PLLCFGR_PLLN(pllmult) |
-		PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
-#if defined(CONFIG_STM32_CLOCK_HSE_HZ)
-		PLLCFGR_PLLSRC_HSE |
-#else
-		PLLCFGR_PLLSRC_HSI |
-#endif
-		PLLCFGR_PLLQ(usbdiv) |
-		PLLCFGR_PLLR(i2sdiv);
-}
-
-void low_power_init(void);
-
-void config_hispeed_clock(void)
-{
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	/* Ensure that HSE is ON */
-	clock_enable_osc(OSC_HSE, true);
-#endif
-
-	/* Put the PLL settings, they are never changing */
-	clock_pll_configure();
-	clock_enable_osc(OSC_PLL, true);
-
-	/* Switch SYSCLK to PLL, setup bus prescalers. */
-	clock_switch_osc(OSC_PLL);
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-#endif
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA_GET_ISR(0);
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_USB) {
-		if (enable) {
-			STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN;
-			STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN |
-				STM32_RCC_AHB1ENR_OTGHSULPIEN;
-		} else {
-			STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN;
-			STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN &
-				     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
-		}
-		return;
-	} else if (module == MODULE_I2C) {
-		if (enable) {
-			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR |=
-				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN
-				| STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
-			STM32_RCC_DCKCFGR2 =
-				(STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK)
-				| DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
-		} else {
-			STM32_RCC_APB1ENR &=
-				~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
-				  STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN);
-		}
-		return;
-	} else if (module == MODULE_ADC) {
-		if (enable)
-			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADC1EN;
-		else
-			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADC1EN;
-		return;
-	}
-}
-
-/* Real Time Clock (RTC) */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-#define RTC_PREDIV_A 39
-#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
-#else /* from LSI clock */
-#define RTC_PREDIV_A 1
-#define RTC_FREQ (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-/*
- * Scaling factor to ensure that the intermediate values computed from/to the
- * RTC frequency are fitting in a 32-bit integer.
- */
-#define SCALING 1000
-
-int32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING));
-}
-
-uint32_t us_to_rtcss(int32_t us)
-{
-	return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING)));
-}
-
-void rtc_init(void)
-{
-	/* Setup RTC Clock input */
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-	/* RTC clocked from the HSE */
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE);
-#else
-	/* RTC clocked from the LSI, ensure first it is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
-
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
-#endif
-
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars: Needs two separate writes. */
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S;
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK)
-		| (RTC_PREDIV_A << 16);
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
-#define STOP_MODE_LATENCY 50 /* us */
-/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
-#define PLL_LOCK_LATENCY 150 /* us */
-/*
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- */
-#define SET_RTC_MATCH_DELAY 120 /* us */
-
-
-void low_power_init(void)
-{
-	/* Turn off the main regulator during stop mode */
-	STM32_PWR_CR |= STM32_PWR_CR_LPSDSR /* aka LPDS */;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
-				   SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			/*
-			 * TODO(b/174337385) no support for wake-up on USART
-			 * uart_enable_wakeup(1);
-			 */
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
-				      &rtc0, 0);
-
-			/* Switch to HSI */
-			clock_switch_osc(OSC_HSI);
-			/* Turn off the PLL1 to save power */
-			clock_enable_osc(OSC_PLL, false);
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* turn on PLL and wait until it's ready */
-			clock_enable_osc(OSC_PLL, true);
-			/* Switch to PLL */
-			clock_switch_osc(OSC_PLL);
-
-			/*uart_enable_wakeup(0);*/
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-/* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
deleted file mode 100644
index 42a00a0f6a..0000000000
--- a/chip/stm32/clock-stm32g4.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks configuration routines */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-#define MHZ(x) ((x) * 1000000)
-#define WAIT_STATE_FREQ_STEP_HZ	MHZ(20)
-/* PLL configuration constants */
-#define STM32G4_SYSCLK_MAX_HZ		MHZ(170)
-#define STM32G4_HSI_CLK_HZ		MHZ(16)
-#define STM32G4_PLL_IN_FREQ_HZ		MHZ(4)
-#define STM32G4_PLL_R 2
-#define STM32G4_AHB_PRE 1
-#define STM32G4_APB1_PRE 1
-#define STM32G4_APB2_PRE 1
-
-enum rcc_clksrc {
-	sysclk_rsvd,
-	sysclk_hsi,
-	sysclk_hse,
-	sysclk_pll,
-};
-
-static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
-			      uint32_t pll_clk_in_hz)
-{
-	/*
-	 * The pll output frequency (Fhclkc) is determined by:
-	 *     Fvco = Fosc_in * (PLL_N / PLL_M)
-	 *     Fsysclk = Fvco / PLL_R
-	 *     Fhclk = Fsysclk / AHBpre = (Fosc * N) /(M * R * AHBpre)
-	 *
-	 * PLL_N: 8 <= N <= 127
-	 * PLL_M: 1 <= M <= 16
-	 * PLL_R: 2, 4, 6, or 8
-	 *
-	 * PLL_input freq (4 - 16 MHz)
-	 * Fvco: 2.66 MHz <= Fvco_in <= 8 MHz
-	 *       64 MHz <= Fvco_out <= 344 MHz
-	 * Fhclk <= 170 MHz
-	 *
-	 * PLL config parameters are selected given the following assumptions:
-	 *     - PLL input freq = 4 MHz
-	 *     - PLL_R divider = 2
-	 * With these assumptions the value N can be calculated by:
-	 *     N = (Fhclk * M * R * AHBpre) / Fosc
-	 *     where M = Fosc / F_pllin
-	 *     Replacing M gives:
-	 *     N = (Fhclk * R * AHBpre) / Fpll_in
-	 */
-	uint32_t pll_n;
-	uint32_t pll_m;
-	uint32_t hclk_freq;
-
-	/* Pll input divider = input freq / desired_input_freq */
-	pll_m = pll_clk_in_hz / STM32G4_PLL_IN_FREQ_HZ;
-	pll_n = (hclk_hz * STM32G4_PLL_R * STM32G4_AHB_PRE) /
-		STM32G4_PLL_IN_FREQ_HZ;
-
-	/* validity checks */
-	ASSERT(pll_m && (pll_m <= 16));
-	ASSERT((pll_n >= 8) && (pll_n <= 127));
-
-	hclk_freq = pll_clk_in_hz * pll_n / (pll_m *
-					      STM32G4_PLL_R * STM32G4_AHB_PRE);
-	/* Ensure that there aren't any integer rounding errors */
-	ASSERT(hclk_freq == hclk_hz);
-
-	/* Program PLL config register */
-	STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) |
-		PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
-		PLLCFGR_PLLR_EN |
-		PLLCFGR_PLLQ(0) |
-		PLLCFGR_PLLQ_EN |
-		PLLCFGR_PLLN(pll_n) |
-		PLLCFGR_PLLM(pll_m - 1) |
-		pll_src;
-
-	/* Wait until PLL is locked */
-	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON,
-		       STM32_RCC_CR_PLLRDY);
-
-	/*
-	 * Program prescalers and set system clock source as PLL
-	 * Assuming AHB, APB1, and APB2 prescalers are 1, and no clock output
-	 * desired so MCO fields are left at reset value.
-	 */
-	STM32_RCC_CFGR = STM32_RCC_CFGR_SW_PLL;
-
-	/* Wait until the PLL is the system clock source */
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-	       STM32_RCC_CFGR_SWS_PLL)
-		;
-}
-
-static void stm32g4_config_low_speed_clock(void)
-{
-	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
-
-	/* Setup RTC Clock input */
-	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
-	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
-}
-
-static void stm32g4_config_high_speed_clock(uint32_t hclk_hz,
-					    enum rcc_clksrc sysclk_src,
-					    uint32_t pll_clksrc)
-{
-	/* TODO(b/161502871): PLL is currently only supported clock source */
-	ASSERT(sysclk_src == sysclk_pll);
-
-	/* Ensure that HSI is ON */
-	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_HSION,
-		       STM32_RCC_CR_HSIRDY);
-
-	if (sysclk_src == sysclk_pll) {
-		/*
-		 * If PLL_R is the desired clock source, then need to calculate
-		 * PLL multilier/diviber parameters. Once the PLL output is
-		 * stable, then the PLL must be selected as the clock
-		 * source. Note, that if the current clock source selection is
-		 * the PLL and sysclk frequency == hclk_hz, there is nothing
-		 * that needs to be done here.
-		 */
-		/* If PLL is the clock source, PLL has already been set up. */
-		if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) ==
-		    STM32_RCC_CFGR_SWS_PLL)
-			return;
-		stm32g4_config_pll(hclk_hz, pll_clksrc, STM32G4_HSI_CLK_HZ);
-	}
-}
-
-void stm32g4_set_flash_ws(uint32_t freq_hz)
-{
-	int ws;
-
-	ASSERT(freq_hz <= STM32G4_SYSCLK_MAX_HZ);
-	/*
-	 * Need to calculate and then set number of wait states (in CPU cycles)
-	 * required for access to internal flash. The required values can be
-	 * found in Table 9 of RM0440 - STM32G4 technical reference manual. A
-	 * table lookup is not required though as WS = HCLK (MHz) / 20
-	 */
-	ws = freq_hz /  WAIT_STATE_FREQ_STEP_HZ;
-	/* Enable data and instruction cache */
-	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN |
-		STM32_FLASH_ACR_PRFTEN | ws;
-}
-
-void clock_init(void)
-{
-	/*
-	 * The STM32G4 has 3 potential sysclk sources:
-	 *   1. HSE -> external cyrstal oscillator circuit
-	 *   2. HSI -> Internal RC oscillator (16 MHz output)
-	 *   3. PLL -> input from either HSI or HSI
-	 *
-	 * SYSCLK is routed to AHB via the AHB prescaler. The AHB clock is fed
-	 * directly to AHB bus, core, memory, DMA, and cortex FCLK. The AHB bus
-	 * clock is then fed to both APB1 and APB2 buses via the APB1 and APB2
-	 * prescalers.
-	 *
-	 * CrosEC doesn't support having multiple clocks of different
-	 * frequencies and therefore f(AHB) = f(APB1) = f(APB2) must be
-	 * enforced. The max frequency of all these clocks is 170 MHz. Max input
-	 * frequency to the PLL is 48 MHz. The M divider can be used to lower
-	 * the PLL input frequency if necessary. The PLL has 3 different output
-	 * clocks, PLL_P, PLL_Q, and PLL_R. PLL_R is the clock which can be used
-	 * as SYSCLK.
-	 *
-	 * The STM32G4 has an additional 48 MHz internal oscillator that is fed
-	 * directly to the USB and RNG blocks.
-	 *
-	 * The STM32G4 also has a low speed clock which feeds the RTC and IWDG
-	 * blocks and as a low power clock source that can be kept running
-	 * during stop and standby modes. The low speed clock is generated from:
-	 *   1. LSE -> external crystal oscillator (max = 1 MHz)
-	 *   2. LSI -> internal fixed 32 kHz
-	 *
-	 * The initial state following system reset:
-	 *  SYSCLK from HSI, AHB, APB1, and APB2 presecaler = 1
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/* Configure flash wait state and enable I/D cache */
-	stm32g4_set_flash_ws(CPU_CLOCK);
-	/* Set up high speed clock and enable PLL */
-	stm32g4_config_high_speed_clock(CPU_CLOCK, sysclk_pll,
-					PLLCFGR_PLLSRC_HSI);
-	/* Set up low speed clock */
-	stm32g4_config_low_speed_clock();
-}
-
-int clock_get_timer_freq(void)
-{
-	/*
-	 * STM32G4 timer clocks (TCLK) are either at the same frequency as
-	 * PCLK_N when the APB prescaler is 1, and TLCK = 2 * PCLK if
-	 * APBn_pre > 1. It's expected that PCLK1 == PCLK2, so only have to
-	 * check either of the apb prescalar settings.
-	 */
-	return (STM32G4_APB1_PRE > 1 ? CPU_CLOCK * 2 : CPU_CLOCK);
-}
-
-int clock_get_freq(void)
-{
-	return CPU_CLOCK;
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	if (module == MODULE_USB) {
-		if (enable) {
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-			STM32_RCC_CRRCR |= RCC_CRRCR_HSI48O;
-		} else {
-			STM32_RCC_CRRCR &= ~RCC_CRRCR_HSI48O;
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-		}
-	} else if (module == MODULE_I2C) {
-		if (enable) {
-			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR1 |=
-				STM32_RCC_APB1ENR1_I2C1EN |
-				STM32_RCC_APB1ENR1_I2C2EN |
-				STM32_RCC_APB1ENR1_I2C3EN;
-			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
-		} else {
-			STM32_RCC_APB1ENR1 &=
-				~(STM32_RCC_APB1ENR1_I2C1EN |
-				  STM32_RCC_APB1ENR1_I2C2EN |
-				  STM32_RCC_APB1ENR1_I2C3EN);
-			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN;
-		}
-	} else if (module == MODULE_ADC) {
-		/* TODO does clock select need to be set here too? */
-		if (enable)
-			STM32_RCC_AHB2ENR |= (STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
-		else
-			STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
-	} else {
-		CPRINTS("stm32g4: enable clock module %d not supported",
-			module);
-	}
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	if (module == MODULE_USB)
-		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
-	else if (module == MODULE_I2C)
-		return !!(STM32_RCC_APB1ENR1 & STM32_RCC_APB1ENR1_I2C1EN);
-	else if (module == MODULE_ADC)
-		return !!(STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADC12EN);
-	return 0;
-}
-
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
deleted file mode 100644
index ba233dbd76..0000000000
--- a/chip/stm32/clock-stm32h7.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Clocks and power management settings
- *
- * Error Handling and Unimplemented Features:
- * Since we are dealing with code critical to the runtime of the CPU,
- * our strategy for unimplemented functionality is to ASSERT, but fallback
- * to doing nothing if ASSERT is not enabled. This is not a perfect solution,
- * but at least yields predictable behavior.
- */
-
-
-#include <stdbool.h>
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-/* Check chip family and variant for compatibility */
-#ifndef CHIP_FAMILY_STM32H7
-#error  Source clock-stm32h7.c does not support this chip family.
-#endif
-#ifndef CHIP_VARIANT_STM32H7X3
-#error Unsupported chip variant.
-#endif
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-
-enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_CSI,	/* Multi-speed internal oscillator: NOT IMPLEMENTED */
-	OSC_HSE,	/* High-speed external oscillator: NOT IMPLEMENTED */
-	OSC_PLL,	/* PLL */
-};
-
-enum voltage_scale {
-	VOLTAGE_SCALE0 = 0,
-	VOLTAGE_SCALE1,
-	VOLTAGE_SCALE2,
-	VOLTAGE_SCALE3,
-	VOLTAGE_SCALE_COUNT,
-};
-
-enum freq {
-	FREQ_1KHZ   = 1000,
-	FREQ_32KHZ  = 32  * FREQ_1KHZ,
-	FREQ_1MHZ   = 1000000,
-	FREQ_2MHZ   = 2   * FREQ_1MHZ,
-	FREQ_16MHZ  = 16  * FREQ_1MHZ,
-	FREQ_64MHZ  = 64  * FREQ_1MHZ,
-	FREQ_140MHZ = 140 * FREQ_1MHZ,
-	FREQ_200MHZ = 200 * FREQ_1MHZ,
-	FREQ_280MHZ = 280 * FREQ_1MHZ,
-	FREQ_400MHZ = 400 * FREQ_1MHZ,
-	FREQ_480MHZ = 480 * FREQ_1MHZ,
-};
-
-/* High-speed oscillator default is 64 MHz */
-#define STM32_HSI_CLOCK FREQ_64MHZ
-/* Low-speed oscillator is 32-Khz */
-#define STM32_LSI_CLOCK FREQ_32KHZ
-
-/*
- * LPTIM is a 16-bit counter clocked by LSI
- * with /4 prescaler (2^2): period 125 us, full range ~8s
- */
-#define LPTIM_PRESCALER_LOG2 2
-/*
- * LPTIM_PRESCALER and LPTIM_PERIOD_US have to be signed, because they
- * determine the signedness of the comparison with |next_delay| in
- * __idle(), where |next_delay| is negative if no next event.
- */
-#define LPTIM_PRESCALER ((int)BIT(LPTIM_PRESCALER_LOG2))
-#define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER))
-
-/* This is not the core frequency */
-static enum freq current_bus_freq = STM32_HSI_CLOCK;
-static int current_osc = OSC_HSI;
-
-int clock_get_freq(void)
-{
-	return current_bus_freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_GPIO_IDR(GPIO_A);
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-/* Flash latency values are dependent on peripheral speed and voltage scale */
-static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos)
-{
-	uint32_t target_acr;
-
-	if (axi_freq == FREQ_64MHZ && vos == VOLTAGE_SCALE3) {
-		target_acr = STM32_FLASH_ACR_WRHIGHFREQ_85MHZ |
-			     (0 << STM32_FLASH_ACR_LATENCY_SHIFT);
-	} else if (axi_freq == FREQ_200MHZ && vos == VOLTAGE_SCALE1) {
-		target_acr = STM32_FLASH_ACR_WRHIGHFREQ_285MHZ |
-			     (2 << STM32_FLASH_ACR_LATENCY_SHIFT);
-	} else {
-		ASSERT(0);
-		return;
-	}
-
-	STM32_FLASH_ACR(0) = target_acr;
-	while (STM32_FLASH_ACR(0) != target_acr)
-		;
-}
-
-/**
- * @brief Configure PLL1 to output the specified frequency.
- *
- * The input frequency to PLL1 is assumed to be the HSI, which
- * is 64MHz.
- *
- * @param output_freq The target output frequency.
- */
-static void clock_pll1_configure(enum freq output_freq) {
-	uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16)
-	uint32_t divn;     // Pll multiplier
-	uint32_t divp;     // Output 1 prescaler
-
-	switch (output_freq)
-	{
-	case FREQ_400MHZ:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64MHz/4 * 50 / 2
-		 *          = 16MHz * 50 / 2
-		 *          = 400 Mhz
-		 */
-		divn = 50;
-		divp = 2;
-		break;
-	case FREQ_200MHZ:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64 / 4 * 25 / 2
-		 *          = 16MHz * 25 / 2
-		 *          = 200 Mhz
-		 */
-		divn = 25;
-		divp = 2;
-		break;
-	case FREQ_280MHZ:
-		divn = 35;
-		divp = 2;
-		break;
-	case FREQ_480MHZ:
-		divn = 60;
-		divp = 2;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/*
-	 * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE,
-	 * requires input frequency to be between 2MHz and 16MHz.
-	 */
-	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm));
-	ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ);
-
-	/*
-	 * Ensure that we actually reach the target frequency.
-	 */
-	ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq);
-
-	/* Configure PLL1 using 64 Mhz HSI as input */
-	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI
-			    | STM32_RCC_PLLCKSEL_DIVM1(divm);
-	/* in integer mode, wide range VCO with 16Mhz input, use divP */
-	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE
-			  | STM32_RCC_PLLCFG_PLL1RGE_8M_16M
-			  | STM32_RCC_PLLCFG_DIVP1EN;
-	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp)
-			   | STM32_RCC_PLLDIV_DIVN(divn);
-}
-
-/**
- * Configure peripheral domain prescalers to allow a given sysclk frequency.
- *
- * @param sysclk The input system clock, after the system clock prescaler.
- * @return The bus clock speed selected and configured
- */
-static enum freq clock_peripheral_configure(enum freq sysclk) {
-	switch (sysclk)
-	{
-	case FREQ_64MHZ:
-		/* Restore /1 HPRE (AHB prescaler) */
-		/* Disable downstream prescalers */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
-		/* TODO(b/149512910): Adjust more peripheral prescalers */
-		return FREQ_64MHZ;
-	case FREQ_400MHZ:
-		/* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
-		/* TODO(b/149512910): Adjust more peripheral prescalers */
-		return FREQ_200MHZ;
-	default:
-		ASSERT(0);
-		return 0;
-	}
-}
-
-static void clock_enable_osc(enum clock_osc osc, bool enabled)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLL1RDY;
-		on = STM32_RCC_CR_PLL1ON;
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	/* Turn off the oscillator, but don't wait for shutdown */
-	if (!enabled) {
-		STM32_RCC_CR &= ~on;
-		return;
-	}
-
-	/* Turn on the oscillator if not already on */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL1;
-		sws = STM32_RCC_CFGR_SWS_PLL1;
-		break;
-	default:
-		return;
-	}
-
-	STM32_RCC_CFGR = sw;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws)
-		;
-}
-
-static void switch_voltage_scale(enum voltage_scale vos)
-{
-	volatile uint32_t *const vos_reg   = &STM32_PWR_D3CR;
-	const uint32_t           vos_ready = STM32_PWR_D3CR_VOSRDY;
-	const uint32_t           vos_mask  = STM32_PWR_D3CR_VOSMASK;
-	const uint32_t           vos_values[] = {
-						/* See note below about VOS0. */
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS2,
-						STM32_PWR_D3CR_VOS3,
-						};
-	BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT);
-
-	/*
-	 * Real VOS0 on the H743 requires entering VOS1 and setting an extra
-	 * SYS boost register. We currently do not implement this functionality.
-	 */
-	if (vos == VOLTAGE_SCALE0) {
-		ASSERT(0);
-		return;
-	}
-
-	*vos_reg &= ~vos_mask;
-	*vos_reg |= vos_values[vos];
-	while (!(*vos_reg & vos_ready))
-		;
-}
-
-static void clock_set_osc(enum clock_osc osc)
-{
-	enum freq target_sysclk_freq = FREQ_64MHZ;
-	enum voltage_scale target_voltage_scale = VOLTAGE_SCALE3;
-
-	if (osc == current_osc)
-		return;
-
-	switch (osc) {
-	case OSC_HSI:
-	case OSC_PLL:
-		break;
-	default:
-		ASSERT(0);
-		return;
-	}
-
-	hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	default:
-	case OSC_HSI:
-		/* Switch to HSI */
-		clock_switch_osc(osc);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
-		/* Use more optimized flash latency settings for 64-MHz ACLK */
-		clock_flash_latency(current_bus_freq, target_voltage_scale);
-		/* Turn off the PLL1 to save power */
-		clock_enable_osc(OSC_PLL, false);
-		switch_voltage_scale(target_voltage_scale);
-		break;
-
-	case OSC_PLL:
-		/*
-		 * PLL1 configuration:
-		 * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP
-		 *          = 64 / 4 * 50 / 2
-		 *          = 400 Mhz
-		 * System clock = 400 Mhz
-		 *  HPRE = /2  => AHB/Timer clock = 200 Mhz
-		 */
-		target_sysclk_freq = FREQ_400MHZ;
-		target_voltage_scale = VOLTAGE_SCALE1;
-
-		switch_voltage_scale(target_voltage_scale);
-		clock_pll1_configure(target_sysclk_freq);
-		/* turn on PLL1 and wait until it's ready */
-		clock_enable_osc(OSC_PLL, true);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
-		/* Increase flash latency before transition the clock */
-		clock_flash_latency(current_bus_freq, target_voltage_scale);
-
-		/* Switch to PLL */
-		clock_switch_osc(OSC_PLL);
-		break;
-	}
-
-	current_osc = osc;
-	hook_notify(HOOK_FREQ_CHANGE);
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	/* Assume we have a single task using MODULE_FAST_CPU */
-	if (module == MODULE_FAST_CPU) {
-		/* the PLL would be off in low power mode, disable it */
-		if (enable)
-			disable_sleep(SLEEP_MASK_PLL);
-		else
-			enable_sleep(SLEEP_MASK_PLL);
-		clock_set_osc(enable ? OSC_PLL : OSC_HSI);
-	}
-}
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */
-#define STOP_MODE_LATENCY 50 /* us */
-
-static void low_power_init(void)
-{
-	/* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */
-	STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R &
-		~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK)
-		| STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
-
-	/* configure LPTIM1 as our 1-Khz low power timer in STOP mode */
-	STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1;
-	STM32_LPTIM_CR(1) = 0; /* ensure it's disabled before configuring */
-	STM32_LPTIM_CFGR(1) = LPTIM_PRESCALER_LOG2 << 9; /* Prescaler /4 */
-	STM32_LPTIM_IER(1) = STM32_LPTIM_INT_CMPM; /* Compare int for wake-up */
-	/* Start the 16-bit free-running counter */
-	STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE;
-	STM32_LPTIM_ARR(1) = 0xFFFF;
-	STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE | STM32_LPTIM_CR_CNTSTRT;
-	task_enable_irq(STM32_IRQ_LPTIM1);
-
-	/* Wake-up interrupts from EXTI for USART and LPTIM */
-	STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */
-	STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
-
-	/* optimize power vs latency in STOP mode */
-	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
-		     | STM32_PWR_CR_SVOS5
-		     | STM32_PWR_CR_FLPS;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void lptim_interrupt(void)
-{
-	STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
-}
-DECLARE_IRQ(STM32_IRQ_LPTIM1, lptim_interrupt, 2);
-
-static uint16_t lptim_read(void)
-{
-	uint16_t cnt;
-
-	do {
-		cnt = STM32_LPTIM_CNT(1);
-	} while (cnt != STM32_LPTIM_CNT(1));
-
-	return cnt;
-}
-
-static void set_lptim_event(int delay_us, uint16_t *lptim_cnt)
-{
-	uint16_t cnt = lptim_read();
-
-	STM32_LPTIM_CMP(1) = cnt + MIN(delay_us / LPTIM_PERIOD_US - 1, 0xffff);
-	/* clean-up previous event */
-	STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM;
-	*lptim_cnt = cnt;
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	int next_delay;
-	int margin_us, t_diff;
-	uint16_t lptim0;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) {
-			/* deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_lptim_event(next_delay - STOP_MODE_LATENCY,
-					&lptim0);
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* fast forward timer according to low power counter */
-			if (STM32_PWR_CPUCR & STM32_PWR_CPUCR_STOPF) {
-				uint16_t lptim_dt = lptim_read() - lptim0;
-
-				t_diff = (int)lptim_dt * LPTIM_PERIOD_US;
-				t0.val = t0.val + t_diff;
-				force_time(t0);
-				/* clear STOPF flag */
-				STM32_PWR_CPUCR |= STM32_PWR_CPUCR_CSSF;
-			} else { /* STOP entry was aborted, no fixup */
-				t_diff = 0;
-			}
-
-			uart_enable_wakeup(0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += t_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - t_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-#ifdef CONFIG_CMD_IDLE_STATS
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_CMD_IDLE_STATS */
-#endif /* CONFIG_LOW_POWER_IDLE */
-
-void clock_init(void)
-{
-	/*
-	 * STM32H743 Errata 2.2.15:
-	 * 'Reading from AXI SRAM might lead to data read corruption'
-	 *
-	 * limit concurrent read access on AXI master to 1.
-	 */
-	STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
-
-	/*
-	 * Lock (SCUEN=0) power configuration with the LDO enabled.
-	 *
-	 * The STM32H7 Reference Manual says:
-	 * The lower byte of this register is written once after POR and shall
-	 * be written before changing VOS level or ck_sys clock frequency.
-	 *
-	 * The interesting side-effect of this that while the LDO is enabled by
-	 * default at startup, if we enter STOP mode without locking it the MCU
-	 * seems to freeze forever.
-	 */
-	STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN;
-	/*
-	 * Ensure the SPI is always clocked at the same frequency
-	 * by putting it on the fixed 64-Mhz HSI clock.
-	 * per_ck is clocked directly by the HSI (as per the default settings).
-	 */
-	STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R &
-		~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
-		  STM32_RCC_D2CCIP1R_SPI45SEL_MASK))
-		| STM32_RCC_D2CCIP1R_SPI123SEL_PERCK
-		| STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
-
-	/* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */
-	clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3);
-
-	/* Ensure that LSI is ON to clock LPTIM1 and IWDG */
-	STM32_RCC_CSR |= STM32_RCC_CSR_LSION;
-	while (!(STM32_RCC_CSR & STM32_RCC_CSR_LSIRDY))
-		;
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-#endif
-}
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI);
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL);
-		else
-			return EC_ERROR_PARAM1;
-	}
-	ccprintf("Clock frequency is now %d Hz\n", clock_get_freq());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | pll", "Set clock frequency");
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
deleted file mode 100644
index bb0da42d14..0000000000
--- a/chip/stm32/clock-stm32l.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "registers.h"
-#include "util.h"
-
-#ifdef CONFIG_STM32L_FAKE_HIBERNATE
-#include "extpower.h"
-#include "keyboard_config.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-
-static int fake_hibernate;
-#endif
-
-/* High-speed oscillator is 16 MHz */
-#define HSI_CLOCK 16000000
-/*
- * MSI is 2 MHz (default) 1 MHz, depending on ICSCR setting.  We use 1 MHz
- * because it's the lowest clock rate we can still run 115200 baud serial
- * for the debug console.
- */
-#define MSI_2MHZ_CLOCK BIT(21)
-#define MSI_1MHZ_CLOCK BIT(20)
-
-enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed oscillator */
-	OSC_MSI,	/* Med-speed oscillator @ 1 MHz */
-};
-
-static int freq;
-static int current_osc;
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-/**
- * Set which oscillator is used for the clock
- *
- * @param osc		Oscillator to use
- */
-static void clock_set_osc(enum clock_osc osc)
-{
-	uint32_t tmp_acr;
-
-	if (osc == current_osc)
-		return;
-
-	if (current_osc != OSC_INIT)
-		hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	case OSC_HSI:
-		/* Ensure that HSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
-
-		/* Disable LPSDSR */
-		STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
-
-		/*
-		 * Set the recommended flash settings for 16MHz clock.
-		 *
-		 * The 3 bits must be programmed strictly sequentially.
-		 * Also, follow the RM to check 64-bit access and latency bit
-		 * after writing those bits to the FLASH_ACR register.
-		 */
-		tmp_acr = STM32_FLASH_ACR;
-		/* Enable 64-bit access */
-		tmp_acr |= STM32_FLASH_ACR_ACC64;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check ACC64 bit == 1 */
-		while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64))
-			;
-
-		/* Enable Prefetch Buffer */
-		tmp_acr |= STM32_FLASH_ACR_PRFTEN;
-		STM32_FLASH_ACR = tmp_acr;
-
-		/* Flash 1 wait state */
-		tmp_acr |= STM32_FLASH_ACR_LATENCY;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check LATENCY bit == 1 */
-		while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY))
-			;
-
-		/* Switch to HSI */
-		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI;
-		/* RM says to check SWS bits to make sure HSI is the sysclock */
-		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_HSI)
-			;
-
-		/* Disable MSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_MSION;
-
-		freq = HSI_CLOCK;
-		break;
-
-	case OSC_MSI:
-		/* Switch to MSI @ 1MHz */
-		STM32_RCC_ICSCR =
-			(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
-		/* Ensure that MSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
-
-		/* Switch to MSI */
-		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;
-		/* RM says to check SWS bits to make sure MSI is the sysclock */
-		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_MSI)
-			;
-
-		/*
-		 * Set the recommended flash settings for <= 2MHz clock.
-		 *
-		 * The 3 bits must be programmed strictly sequentially.
-		 * Also, follow the RM to check 64-bit access and latency bit
-		 * after writing those bits to the FLASH_ACR register.
-		 */
-		tmp_acr = STM32_FLASH_ACR;
-		/* Flash 0 wait state */
-		tmp_acr &= ~STM32_FLASH_ACR_LATENCY;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check LATENCY bit == 0 */
-		while (STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY)
-			;
-
-		/* Disable prefetch Buffer */
-		tmp_acr &= ~STM32_FLASH_ACR_PRFTEN;
-		STM32_FLASH_ACR = tmp_acr;
-
-		/* Disable 64-bit access */
-		tmp_acr &= ~STM32_FLASH_ACR_ACC64;
-		STM32_FLASH_ACR = tmp_acr;
-		/* Check ACC64 bit == 0 */
-		while (STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64)
-			;
-
-		/* Disable HSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_HSION;
-
-		/* Enable LPSDSR */
-		STM32_PWR_CR |= STM32_PWR_CR_LPSDSR;
-
-		freq = MSI_1MHZ_CLOCK;
-		break;
-
-	default:
-		break;
-	}
-
-	/* Notify modules of frequency change unless we're initializing */
-	if (current_osc != OSC_INIT) {
-		current_osc = osc;
-		hook_notify(HOOK_FREQ_CHANGE);
-	} else {
-		current_osc = osc;
-	}
-}
-
-static uint64_t clock_mask;
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	uint64_t new_mask;
-
-	if (enable)
-		new_mask = clock_mask | BIT_ULL(module);
-	else
-		new_mask = clock_mask & ~BIT_ULL(module);
-
-	/* Only change clock if needed */
-	if ((!!new_mask) != (!!clock_mask)) {
-
-		/* Flush UART before switching clock speed */
-		cflush();
-
-		clock_set_osc(new_mask ? OSC_HSI : OSC_MSI);
-	}
-
-	if (module == MODULE_USB) {
-		if (enable)
-			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
-		else
-			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
-	}
-
-	clock_mask = new_mask;
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	return !!(clock_mask & BIT_ULL(module));
-}
-
-#ifdef CONFIG_STM32L_FAKE_HIBERNATE
-/*
- *  This is for NOT having enough hibernate (more precisely, the stand-by mode)
- *  wake-up source pin. STM32L100 supports 3 wake-up source pins:
- *
- *     WKUP1 (PA0)  -- used for ACOK_PMU
- *     WKUP2 (PC13) -- used for LID_OPEN
- *     WKUP3 (PE6)  -- cannot be used due to IC package.
- *
- *  However, we need the power button as a wake-up source as well and there is
- *  no available pin for us (we don't want to move the ACOK_PMU pin).
- *
- *  Fortunately, the STM32L is low-power enough so that we don't need the
- *  super-low-power mode. So, we fake this hibernate mode and accept the
- *  following wake-up source.
- *
- *     RTC alarm  (faked as well).
- *     Power button
- *     Lid open
- *     AC detected
- *
- *  The original issue is here: crosbug.com/p/25435.
- */
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	int i;
-	fake_hibernate = 1;
-
-#ifdef CONFIG_POWER_COMMON
-	/*
-	 * A quick hack to stop annoying messages from charger task.
-	 *
-	 * When the battery is under 3%, the power task would call
-	 * power_off() to shutdown AP. However, the power_off() would
-	 * notify the HOOK_CHIPSET_SHUTDOWN, where the last hook is
-	 * charge_shutdown() and it hibernates the power task (infinite
-	 * loop -- not real CPU hibernate mode). Unfortunately, the
-	 * charger task is still running. It keeps generating annoying
-	 * log message.
-	 *
-	 * Thus, the hack is to set the power state machine (before we
-	 * enter infinite loop) so that the charger task thinks the AP
-	 * is off and stops generating messages.
-	 */
-	power_set_state(POWER_G3);
-#endif
-
-	/*
-	 * Change keyboard outputs to high-Z to reduce power draw.
-	 * We don't need corresponding code to change them back,
-	 * because fake hibernate is always exited with a reboot.
-	 *
-	 * A little hacky to do this here.
-	 */
-	for (i = GPIO_KB_OUT00; i < GPIO_KB_OUT00 + KEYBOARD_COLS_MAX; i++)
-		gpio_set_flags(i, GPIO_INPUT);
-
-	ccprints("fake hibernate. waits for power button/lid/RTC/AC");
-	cflush();
-
-	if (seconds || microseconds) {
-		if (seconds)
-			sleep(seconds);
-		if (microseconds)
-			usleep(microseconds);
-	} else {
-		while (1)
-			task_wait_event(-1);
-	}
-
-	ccprints("fake RTC alarm fires. resets EC");
-	cflush();
-	system_reset(SYSTEM_RESET_HARD);
-}
-
-static void fake_hibernate_power_button_hook(void)
-{
-	if (fake_hibernate && lid_is_open() && !power_button_is_pressed()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook,
-	HOOK_PRIO_DEFAULT);
-
-static void fake_hibernate_lid_hook(void)
-{
-	if (fake_hibernate && lid_is_open()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, fake_hibernate_lid_hook, HOOK_PRIO_DEFAULT);
-
-static void fake_hibernate_ac_hook(void)
-{
-	if (fake_hibernate && extpower_is_present()) {
-		ccprints("%s() resets EC", __func__);
-		cflush();
-		system_reset(SYSTEM_RESET_HARD);
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, fake_hibernate_ac_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-void clock_init(void)
-{
-	/*
-	 * The initial state :
-	 *  SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2
-	 *  PLL unlocked, RTC enabled on LSE
-	 */
-
-	/* Switch to high-speed oscillator */
-	clock_set_osc(1);
-}
-
-static void clock_chipset_startup(void)
-{
-	/* Return to full speed */
-	clock_enable_module(MODULE_CHIPSET, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void clock_chipset_shutdown(void)
-{
-	/* Drop to lower clock speed if no other module requires full speed */
-	clock_enable_module(MODULE_CHIPSET, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI);
-		else if (!strcasecmp(argv[1], "msi"))
-			clock_set_osc(OSC_MSI);
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Clock frequency is now %d Hz\n", freq);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi",
-			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
deleted file mode 100644
index 2094751aab..0000000000
--- a/chip/stm32/clock-stm32l4.c
+++ /dev/null
@@ -1,1110 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */
-
-#include "chipset.h"
-#include "clock.h"
-#include "clock-l4.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "rtc.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/* High-speed oscillator is 16 MHz */
-#define STM32_HSI_CLOCK 16000000
-/* Multi-speed oscillator is 4 MHz by default */
-#define STM32_MSI_CLOCK 4000000
-
-/* Real Time Clock (RTC) */
-
-#ifdef CONFIG_STM32_CLOCK_HSE_HZ
-#define RTC_PREDIV_A 39
-#define RTC_FREQ ((STM32L4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */
-#else /* from LSI clock */
-#define RTC_PREDIV_A 1
-#define RTC_FREQ (STM32L4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */
-#endif
-#define RTC_PREDIV_S (RTC_FREQ - 1)
-/*
- * Scaling factor to ensure that the intermediate values computed from/to the
- * RTC frequency are fitting in a 32-bit integer.
- */
-#define SCALING 1000
-
-enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed internal oscillator */
-	OSC_MSI,	/* Multi-speed internal oscillator */
-#ifdef STM32_HSE_CLOCK	/* Allows us to catch absence of HSE at comiple time */
-	OSC_HSE,	/* High-speed external oscillator */
-#endif
-	OSC_PLL,	/* PLL */
-};
-
-static int freq = STM32_MSI_CLOCK;
-static int current_osc;
-
-int clock_get_freq(void)
-{
-	return freq;
-}
-
-int clock_get_timer_freq(void)
-{
-	return clock_get_freq();
-}
-
-void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
-{
-	volatile uint32_t unused __attribute__((unused));
-
-	if (bus == BUS_AHB) {
-		while (cycles--)
-			unused = STM32_DMA1_REGS->isr;
-	} else { /* APB */
-		while (cycles--)
-			unused = STM32_USART_BRR(STM32_USART1_BASE);
-	}
-}
-
-static void clock_enable_osc(enum clock_osc osc)
-{
-	uint32_t ready;
-	uint32_t on;
-
-	switch (osc) {
-	case OSC_HSI:
-		ready = STM32_RCC_CR_HSIRDY;
-		on = STM32_RCC_CR_HSION;
-		break;
-	case OSC_MSI:
-		ready = STM32_RCC_CR_MSIRDY;
-		on = STM32_RCC_CR_MSION;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-#ifdef STM32_HSE_BYP
-		STM32_RCC_CR |= STM32_RCC_CR_HSEBYP;
-#endif
-		ready = STM32_RCC_CR_HSERDY;
-		on = STM32_RCC_CR_HSEON;
-		break;
-#endif
-	case OSC_PLL:
-		ready = STM32_RCC_CR_PLLRDY;
-		on = STM32_RCC_CR_PLLON;
-		break;
-	default:
-		return;
-	}
-
-	/* Enable HSI and wait for HSI to be ready */
-	wait_for_ready(&STM32_RCC_CR, on, ready);
-}
-
-/* Switch system clock oscillator */
-static void clock_switch_osc(enum clock_osc osc)
-{
-	uint32_t sw;
-	uint32_t sws;
-	uint32_t val;
-
-	switch (osc) {
-	case OSC_HSI:
-		sw = STM32_RCC_CFGR_SW_HSI;
-		sws = STM32_RCC_CFGR_SWS_HSI;
-		break;
-	case OSC_MSI:
-		sw = STM32_RCC_CFGR_SW_MSI;
-		sws = STM32_RCC_CFGR_SWS_MSI;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		sw = STM32_RCC_CFGR_SW_HSE;
-		sws = STM32_RCC_CFGR_SWS_HSE;
-		break;
-#endif
-	case OSC_PLL:
-		sw = STM32_RCC_CFGR_SW_PLL;
-		sws = STM32_RCC_CFGR_SWS_PLL;
-		break;
-	default:
-		return;
-	}
-	val = STM32_RCC_CFGR;
-	val &= ~STM32_RCC_CFGR_SW;
-	val |= sw;
-	STM32_RCC_CFGR = val;
-	while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != sws)
-		;
-}
-
-/*
- * Configure PLL for HSE
- *
- * 1. Disable the PLL by setting PLLON to 0 in RCC_CR.
- * 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
- * 3. Change the desired parameter.
- * 4. Enable the PLL again by setting PLLON to 1.
- * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN
- *    in RCC_PLLCFGR.
- */
-static int stm32_configure_pll(enum clock_osc osc,
-			       uint8_t m, uint8_t n, uint8_t r)
-{
-	uint32_t val;
-	bool pll_unchanged;
-	int f;
-
-	val = STM32_RCC_PLLCFGR;
-	pll_unchanged = true;
-
-	if (osc == OSC_HSI)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_HSI)
-			pll_unchanged = false;
-
-	if (osc == OSC_MSI)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_MSI)
-			pll_unchanged = false;
-
-#ifdef STM32_HSE_CLOCK
-	if (osc == OSC_HSE)
-		if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) !=
-		    STM32_RCC_PLLCFGR_PLLSRC_HSE)
-			pll_unchanged = false;
-#endif
-
-	if ((val & STM32_RCC_PLLCFGR_PLLM_MSK) !=
-	    ((m - 1) << STM32_RCC_PLLCFGR_PLLM_POS))
-		pll_unchanged = false;
-
-	if ((val & STM32_RCC_PLLCFGR_PLLN_MSK) !=
-	    (n << STM32_RCC_PLLCFGR_PLLN_POS))
-		pll_unchanged = false;
-
-	if ((val & STM32_RCC_PLLCFGR_PLLR_MSK) !=
-	    (((r >> 1) - 1) << STM32_RCC_PLLCFGR_PLLR_POS))
-		pll_unchanged = false;
-
-	if (pll_unchanged == true) {
-		if (osc == OSC_HSI)
-			f = STM32_HSI_CLOCK;
-		else
-			f = STM32_MSI_CLOCK;
-
-		if (!(STM32_RCC_CR & STM32_RCC_CR_PLLRDY)) {
-			STM32_RCC_CR |= STM32_RCC_CR_PLLON;
-			STM32_RCC_PLLCFGR |= STM32_RCC_PLLCFGR_PLLREN;
-
-			while ((STM32_RCC_CR & STM32_RCC_CR_PLLRDY) == 0)
-				;
-		}
-		/* (f * n) shouldn't overflow based on their max values */
-		return (f * n / m / r);
-	}
-	/* 1 */
-	STM32_RCC_CR &= ~STM32_RCC_CR_PLLON;
-
-	/* 2 */
-	while (STM32_RCC_CR & STM32_RCC_CR_PLLRDY)
-		;
-
-	/* 3 */
-	val = STM32_RCC_PLLCFGR;
-
-	val &= ~STM32_RCC_PLLCFGR_PLLSRC_MSK;
-	switch (osc) {
-	case OSC_HSI:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_HSI;
-		f = STM32_HSI_CLOCK;
-		break;
-	case OSC_MSI:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_MSI;
-		f = STM32_MSI_CLOCK;
-		break;
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		val |= STM32_RCC_PLLCFGR_PLLSRC_HSE;
-		f = STM32_HSE_CLOCK;
-		break;
-#endif
-	default:
-		return -1;
-	}
-
-	ASSERT(m > 0 && m < 9);
-	val &= ~STM32_RCC_PLLCFGR_PLLM_MSK;
-	val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_POS;
-
-	/* Max and min values are from TRM */
-	ASSERT(n > 7 && n < 87);
-	val &= ~STM32_RCC_PLLCFGR_PLLN_MSK;
-	val |= n << STM32_RCC_PLLCFGR_PLLN_POS;
-
-	val &= ~STM32_RCC_PLLCFGR_PLLR_MSK;
-	switch (r) {
-	case 2:
-		val |= 0 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 4:
-		val |= 1 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 6:
-		val |= 2 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	case 8:
-		val |= 3 << STM32_RCC_PLLCFGR_PLLR_POS;
-		break;
-	default:
-		return -1;
-	}
-
-	STM32_RCC_PLLCFGR = val;
-
-	/* 4 */
-	clock_enable_osc(OSC_PLL);
-
-	/* 5 */
-	val = STM32_RCC_PLLCFGR;
-	val |= 1 << STM32_RCC_PLLCFGR_PLLREN_POS;
-	STM32_RCC_PLLCFGR = val;
-
-	/* (f * n) shouldn't overflow based on their max values */
-	return (f * n / m / r);
-}
-
-/**
- * Set system clock oscillator
- *
- * @param osc		Oscillator to use
- * @param pll_osc	Source oscillator for PLL. Ignored if osc is not PLL.
- */
-static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
-{
-	uint32_t val;
-
-	if (osc == current_osc)
-		return;
-
-	if (current_osc != OSC_INIT)
-		hook_notify(HOOK_PRE_FREQ_CHANGE);
-
-	switch (osc) {
-	case OSC_HSI:
-		/* Ensure that HSI is ON */
-		clock_enable_osc(osc);
-
-		/* Set HSI as system clock after exiting stop mode */
-		STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
-
-		/* Switch to HSI */
-		clock_switch_osc(osc);
-
-		/* Disable MSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_MSION;
-
-		freq = STM32_HSI_CLOCK;
-		break;
-
-	case OSC_MSI:
-		/* Switch to MSI @ 1MHz */
-		STM32_RCC_CR =
-			(STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
-		/* Ensure that MSI is ON */
-		clock_enable_osc(osc);
-
-		/*
-		 * Set MSI as system clock after exiting stop mode
-		 */
-		STM32_RCC_CFGR &= ~STM32_RCC_CFGR_STOPWUCK;
-
-		/* Switch to MSI */
-		clock_switch_osc(osc);
-
-		/* Disable HSI */
-		STM32_RCC_CR &= ~STM32_RCC_CR_HSION;
-
-		freq = STM32_MSI_CLOCK;
-		break;
-
-#ifdef STM32_HSE_CLOCK
-	case OSC_HSE:
-		/* Ensure that HSE is stable */
-		clock_enable_osc(osc);
-
-		/* Switch to HSE */
-		clock_switch_osc(osc);
-
-		/* Disable other clock sources */
-		STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION |
-				STM32_RCC_CR_PLLON);
-
-		freq = STM32_HSE_CLOCK;
-
-		break;
-#endif
-	case OSC_PLL:
-		/* Ensure that source clock is stable */
-		if (pll_osc == OSC_INIT) {
-			if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) !=
-			    STM32_RCC_CFGR_SWS_PLL) {
-				STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK;
-				clock_enable_osc(OSC_HSI);
-				freq = stm32_configure_pll(OSC_HSI, STM32_PLLM,
-							   STM32_PLLN,
-							   STM32_PLLR);
-			} else {
-				/* already set PLL, skip */
-				freq = STM32_HSI_CLOCK * STM32_PLLN /
-				       STM32_PLLM / STM32_PLLR;
-				break;
-			}
-		} else {
-			clock_enable_osc(pll_osc);
-			/* Configure PLLCFGR */
-			freq = stm32_configure_pll(pll_osc, STM32_PLLM,
-						   STM32_PLLN, STM32_PLLR);
-		}
-		ASSERT(freq > 0);
-
-		/* Change to Range 1 if Freq > 26MHz */
-		if (freq > 26000000U) {
-			/* Set VCO range 1 */
-			val = STM32_RCC_CR;
-			val &= ~PWR_CR1_VOS_MSK;
-			val |= PWR_CR1_VOS_0;
-			STM32_RCC_CR = val;
-
-			/*
-			 * Set Flash latency according to frequency
-			 */
-			val = STM32_FLASH_ACR;
-			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-			if (freq <= 16000000U)	{
-				val = val;
-			} else if (freq <= 32000000U)	{
-				val |= 1;
-			} else if (freq <= 48000000U)	{
-				val |= 2;
-			} else if (freq <= 64000000U)	{
-				val |= 3;
-			} else if (freq <= 80000000U)	{
-				val |= 4;
-			} else	{
-				val |= 4;
-				CPUTS("Incorrect Frequency setting in VOS1!\n");
-			}
-			STM32_FLASH_ACR = val;
-		} else	{
-			val = STM32_FLASH_ACR;
-			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-
-			if (freq <= 6000000U) {
-				val = val;
-			} else if (freq <= 12000000U) {
-				val |= 1;
-			} else if (freq <= 18000000U) {
-				val |= 2;
-			} else if (freq <= 26000000U) {
-				val |= 3;
-			} else	{
-				val |= 4;
-				CPUTS("Incorrect Frequency setting in VOS2!\n");
-			}
-			STM32_FLASH_ACR = val;
-		}
-
-		while (val != STM32_FLASH_ACR)
-			;
-
-		/* Switch to PLL */
-		clock_switch_osc(osc);
-
-		/* TODO: Disable other sources */
-		break;
-	default:
-		break;
-	}
-
-	/* Notify modules of frequency change unless we're initializing */
-	if (current_osc != OSC_INIT) {
-		current_osc = osc;
-		hook_notify(HOOK_FREQ_CHANGE);
-	} else {
-		current_osc = osc;
-	}
-}
-
-static uint64_t clock_mask;
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	uint64_t new_mask;
-
-	if (enable)
-		new_mask = clock_mask | BIT_ULL(module);
-	else
-		new_mask = clock_mask & ~BIT_ULL(module);
-
-	/* Only change clock if needed */
-	if (new_mask != clock_mask) {
-		if (module == MODULE_ADC) {
-			STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN;
-			STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN;
-
-			/* ADC select bit 28/29 */
-			STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK;
-			STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 |
-					    STM32_RCC_CCIPR_ADCSEL_1);
-			/* ADC clock enable */
-			if (enable)
-				STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1;
-			else
-				STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1;
-		} else if (module == MODULE_SPI_FLASH) {
-			if (enable)
-				STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
-			else
-				STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
-		} else if (module == MODULE_SPI ||
-			   module == MODULE_SPI_CONTROLLER) {
-			if (enable)
-				STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN;
-			else if ((new_mask & (BIT(MODULE_SPI) |
-					      BIT(MODULE_SPI_CONTROLLER))) == 0)
-				STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN;
-		} else if (module == MODULE_USB) {
-#if defined(STM32_RCC_APB1ENR2_USBFSEN)
-			if (enable)
-				STM32_RCC_APB1ENR2 |=
-					STM32_RCC_APB1ENR2_USBFSEN;
-			else
-				STM32_RCC_APB1ENR2 &=
-					~STM32_RCC_APB1ENR2_USBFSEN;
-#endif
-		}
-	}
-
-	clock_mask = new_mask;
-}
-
-int clock_is_module_enabled(enum module_id module)
-{
-	return !!(clock_mask & BIT_ULL(module));
-}
-
-void rtc_init(void)
-{
-	/* Enable RTC Alarm in EXTI */
-	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
-	task_enable_irq(STM32_IRQ_RTC_ALARM);
-
-	/* RTC was initilized, avoid initialization again */
-	if (STM32_RTC_ISR & STM32_RTC_ISR_INITS)
-		return;
-
-	rtc_unlock_regs();
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
-		;
-
-	/* Enable RTC alarm interrupt */
-	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
-
-	rtc_lock_regs();
-}
-
-#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
-void rtc_set(uint32_t sec)
-{
-	struct rtc_time_reg rtc;
-
-	sec_to_rtc(sec, &rtc);
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-
-	/* Enter RTC initialize mode */
-	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
-		;
-
-	/* Set clock prescalars */
-	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
-
-	STM32_RTC_TR = rtc.rtc_tr;
-	STM32_RTC_DR = rtc.rtc_dr;
-	/* Start RTC timer */
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
-
-	rtc_lock_regs();
-}
-#endif
-
-
-void clock_init(void)
-{
-#ifdef STM32_HSE_CLOCK
-	clock_set_osc(OSC_PLL, OSC_HSE);
-#else
-#ifdef STM32_USE_PLL
-	clock_set_osc(OSC_PLL, OSC_INIT);
-#else
-	clock_set_osc(OSC_HSI, OSC_INIT);
-#endif
-#endif
-
-#ifdef CONFIG_LOW_POWER_IDLE
-	low_power_init();
-	rtc_init();
-#endif
-}
-
-static void clock_chipset_startup(void)
-{
-	/* Return to full speed */
-	clock_enable_module(MODULE_CHIPSET, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void clock_chipset_shutdown(void)
-{
-	/* Drop to lower clock speed if no other module requires full speed */
-	clock_enable_module(MODULE_CHIPSET, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-static int command_clock(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "hsi"))
-			clock_set_osc(OSC_HSI, OSC_INIT);
-		else if (!strcasecmp(argv[1], "msi"))
-			clock_set_osc(OSC_MSI, OSC_INIT);
-#ifdef STM32_HSE_CLOCK
-		else if (!strcasecmp(argv[1], "hse"))
-			clock_set_osc(OSC_HSE, OSC_INIT);
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL, OSC_HSE);
-#else
-		else if (!strcasecmp(argv[1], "pll"))
-			clock_set_osc(OSC_PLL, OSC_HSI);
-#endif
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Clock frequency is now %d Hz\n", freq);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi"
-#ifdef STM32_HSE_CLOCK
-			" | hse | pll"
-#endif
-			,
-			"Set clock frequency");
-
-uint32_t rtcss_to_us(uint32_t rtcss)
-{
-	return ((RTC_PREDIV_S - (rtcss & 0x7FFF)) * (SECOND / SCALING) /
-		(RTC_FREQ / SCALING));
-}
-
-uint32_t us_to_rtcss(uint32_t us)
-{
-	return (RTC_PREDIV_S -
-		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
-}
-
-
-/* Convert decimal to BCD */
-static uint8_t u8_to_bcd(uint8_t val)
-{
-	/* Fast division by 10 (when lacking HW div) */
-	uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19;
-	uint32_t rem = val - quot * 10;
-
-	return rem | (quot << 4);
-}
-
-/* Convert between RTC regs in BCD and seconds */
-static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
-{
-	uint32_t sec;
-
-	/* convert the hours field */
-	sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 +
-	       ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600;
-	/* convert the minutes field */
-	sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 +
-		((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60;
-	/* convert the seconds field */
-	sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) *  10 +
-	       (rtc_tr & RTC_TR_SU);
-	return sec;
-}
-
-static uint32_t sec_to_rtc_tr(uint32_t sec)
-{
-	uint32_t rtc_tr;
-	uint8_t hour;
-	uint8_t min;
-
-	sec %= SECS_PER_DAY;
-	/* convert the hours field */
-	hour = sec / 3600;
-	rtc_tr = u8_to_bcd(hour) << 16;
-	/* convert the minutes field */
-	sec -= hour * 3600;
-	min = sec / 60;
-	rtc_tr |= u8_to_bcd(min) << 8;
-	/* convert the seconds field */
-	sec -= min * 60;
-	rtc_tr |= u8_to_bcd(sec);
-
-	return rtc_tr;
-}
-
-/* Register setup before RTC alarm is allowed for update */
-static void pre_work_set_rtc_alarm(void)
-{
-	rtc_unlock_regs();
-
-	/* Make sure alarm is disabled */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF))
-		;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-	STM32_EXTI_PR = BIT(18);
-}
-
-/* Register setup after RTC alarm is updated */
-static void post_work_set_rtc_alarm(void)
-{
-	/* Enable alarm and alarm interrupt */
-	STM32_EXTI_IMR |= BIT(18);
-	STM32_EXTI_RTSR |= BIT(18);
-	STM32_RTC_CR |= (STM32_RTC_CR_ALRAE);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static struct wake_time host_wake_time;
-
-bool is_host_wake_alarm_expired(timestamp_t ts)
-{
-	return host_wake_time.ts.val &&
-	       timestamp_expired(host_wake_time.ts, &ts);
-}
-
-void restore_host_wake_alarm(void)
-{
-	if (!host_wake_time.ts.val)
-		return;
-
-	pre_work_set_rtc_alarm();
-
-	/* Set alarm time */
-	STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar;
-
-	post_work_set_rtc_alarm();
-}
-
-static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
-{
-	struct calendar_date time;
-	uint32_t sec;
-
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
-	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
-
-	sec = date_to_sec(time);
-
-	return sec;
-}
-
-static uint32_t sec_to_rtc_dr(uint32_t sec)
-{
-	struct calendar_date time;
-	uint32_t rtc_dr;
-
-	time = sec_to_date(sec);
-
-	rtc_dr = u8_to_bcd(time.year) << 16;
-	rtc_dr |= u8_to_bcd(time.month) << 8;
-	rtc_dr |= u8_to_bcd(time.day);
-
-	return rtc_dr;
-}
-#endif
-
-uint32_t rtc_to_sec(const struct rtc_time_reg *rtc)
-{
-	uint32_t sec = 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	sec = rtc_dr_to_sec(rtc->rtc_dr);
-#endif
-	return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) +
-	       rtc_tr_to_sec(rtc->rtc_tr);
-}
-
-void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc)
-{
-	rtc->rtc_dr = 0;
-#ifdef CONFIG_HOSTCMD_RTC
-	rtc->rtc_dr = sec_to_rtc_dr(sec);
-#endif
-	rtc->rtc_tr = sec_to_rtc_tr(sec);
-	rtc->rtc_ssr = 0;
-}
-
-/* Return sub-10-sec time diff between two rtc readings
- *
- * Note: this function assumes rtc0 was sampled before rtc1.
- * Additionally, this function only looks at the difference mod 10
- * seconds.
- */
-uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0,
-		      const struct rtc_time_reg *rtc1)
-{
-	uint32_t rtc0_val, rtc1_val, diff;
-
-	rtc0_val = (rtc0->rtc_tr & RTC_TR_SU) * SECOND +
-		   rtcss_to_us(rtc0->rtc_ssr);
-	rtc1_val = (rtc1->rtc_tr & RTC_TR_SU) * SECOND +
-		   rtcss_to_us(rtc1->rtc_ssr);
-	diff = rtc1_val;
-	if (rtc1_val < rtc0_val) {
-		/* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add
-		 * 10 seconds to get the correct value
-		 */
-		diff += 10 * SECOND;
-	}
-	diff -= rtc0_val;
-	return diff;
-}
-
-void rtc_read(struct rtc_time_reg *rtc)
-{
-	/*
-	 * Read current time synchronously. Each register must be read
-	 * twice with identical values because glitches may occur for reads
-	 * close to the RTCCLK edge.
-	 */
-	do {
-		rtc->rtc_dr = STM32_RTC_DR;
-
-		do {
-			rtc->rtc_tr = STM32_RTC_TR;
-
-			do {
-				rtc->rtc_ssr = STM32_RTC_SSR;
-			} while (rtc->rtc_ssr != STM32_RTC_SSR);
-
-		} while (rtc->rtc_tr != STM32_RTC_TR);
-
-	} while (rtc->rtc_dr != STM32_RTC_DR);
-}
-
-void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
-		   struct rtc_time_reg *rtc, uint8_t save_alarm)
-{
-	uint32_t alarm_sec = 0;
-	uint32_t alarm_us = 0;
-
-	if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) {
-		reset_rtc_alarm(rtc);
-		return;
-	}
-
-	/* Alarm timeout must be within 1 day (86400 seconds) */
-	ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY);
-
-	pre_work_set_rtc_alarm();
-	rtc_read(rtc);
-
-	/* Calculate alarm time */
-	alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s;
-
-	if (delay_us) {
-		alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us;
-		alarm_sec = alarm_sec + alarm_us / SECOND;
-		alarm_us = alarm_us % SECOND;
-	}
-
-	/*
-	 * If seconds is greater than 1 day, subtract by 1 day to deal with
-	 * 24-hour rollover.
-	 */
-	if (alarm_sec >= SECS_PER_DAY)
-		alarm_sec -= SECS_PER_DAY;
-
-	/*
-	 * Set alarm time in seconds and check for match on
-	 * hours, minutes, and seconds.
-	 */
-	STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000;
-
-	/*
-	 * Set alarm time in subseconds and check for match on subseconds.
-	 * If the caller doesn't specify subsecond delay (e.g. host command),
-	 * just align the alarm time to second.
-	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/*
-	 * If alarm is set by the host, preserve the wake time timestamp
-	 * and alarm registers.
-	 */
-	if (save_alarm) {
-		host_wake_time.ts.val = delay_s * SECOND + get_time().val;
-		host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR;
-	}
-#endif
-	post_work_set_rtc_alarm();
-}
-
-uint32_t get_rtc_alarm(void)
-{
-	struct rtc_time_reg now;
-	uint32_t now_sec;
-	uint32_t alarm_sec;
-
-	if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE))
-		return 0;
-
-	rtc_read(&now);
-
-	now_sec = rtc_tr_to_sec(now.rtc_tr);
-	alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff);
-
-	return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) +
-	       (alarm_sec - now_sec);
-}
-
-void reset_rtc_alarm(struct rtc_time_reg *rtc)
-{
-	rtc_unlock_regs();
-
-	/* Disable alarm */
-	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
-	STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF;
-
-	/* Disable RTC alarm interrupt */
-	STM32_EXTI_IMR &= ~BIT(18);
-	STM32_EXTI_PR = BIT(18);
-
-	/* Clear the pending RTC alarm IRQ in NVIC */
-	task_clear_pending_irq(STM32_IRQ_RTC_ALARM);
-
-	/* Read current time */
-	rtc_read(rtc);
-
-	rtc_lock_regs();
-}
-
-#ifdef CONFIG_HOSTCMD_RTC
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-test_mockable
-void __rtc_alarm_irq(void)
-{
-	struct rtc_time_reg rtc;
-
-	reset_rtc_alarm(&rtc);
-
-#ifdef CONFIG_HOSTCMD_RTC
-	/* Wake up the host if there is a saved rtc wake alarm. */
-	if (host_wake_time.ts.val) {
-		host_wake_time.ts.val = 0;
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-	}
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
-
-
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec;
-	struct rtc_time_reg rtc;
-
-	rtc_read(&rtc);
-	sec = rtc_to_sec(&rtc);
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-
-#ifdef CONFIG_LOW_POWER_IDLE
-/* Low power idle statistics */
-static int idle_sleep_cnt;
-static int idle_dsleep_cnt;
-static uint64_t idle_dsleep_time_us;
-static int dsleep_recovery_margin_us = 1000000;
-
-/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */
-#define STOP_MODE_LATENCY 50 /* us */
-/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */
-#define PLL_LOCK_LATENCY 150 /* us */
-/*
- * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
- * in the past, it will never wake up and cause a watchdog.
- */
-#define SET_RTC_MATCH_DELAY 120 /* us */
-
-
-void low_power_init(void)
-{
-	/* Enter stop1 mode */
-	uint32_t val;
-
-	val = STM32_PWR_CR1;
-	val &= ~PWR_CR1_LPMS_MSK;
-	val |= PWR_CR1_LPMS_STOP1;
-	STM32_PWR_CR1 = val;
-}
-
-void clock_refresh_console_in_use(void)
-{
-}
-
-void __idle(void)
-{
-	timestamp_t t0;
-	uint32_t rtc_diff;
-	int next_delay, margin_us;
-	struct rtc_time_reg rtc0, rtc1;
-
-	while (1) {
-		asm volatile("cpsid i");
-
-		t0 = get_time();
-		next_delay = __hw_clock_event_get() - t0.le.lo;
-
-		if (DEEP_SLEEP_ALLOWED &&
-		    (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY +
-				   SET_RTC_MATCH_DELAY))) {
-			/* Deep-sleep in STOP mode */
-			idle_dsleep_cnt++;
-
-			uart_enable_wakeup(1);
-
-			/* Set deep sleep bit */
-			CPU_SCB_SYSCTRL |= 0x4;
-
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
-				      &rtc0, 0);
-
-
-			/* ensure outstanding memory transactions complete */
-			asm volatile("dsb");
-
-			asm("wfi");
-
-			CPU_SCB_SYSCTRL &= ~0x4;
-
-			/* turn on PLL and wait until it's ready */
-			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
-			clock_wait_bus_cycles(BUS_APB, 2);
-
-			stm32_configure_pll(OSC_HSI, STM32_PLLM,
-						   STM32_PLLN, STM32_PLLR);
-
-			/* Switch to PLL */
-			clock_switch_osc(OSC_PLL);
-
-			uart_enable_wakeup(0);
-
-			/* Fast forward timer according to RTC counter */
-			reset_rtc_alarm(&rtc1);
-			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
-			t0.val = t0.val + rtc_diff;
-			force_time(t0);
-
-			/* Record time spent in deep sleep. */
-			idle_dsleep_time_us += rtc_diff;
-
-			/* Calculate how close we were to missing deadline */
-			margin_us = next_delay - rtc_diff;
-			if (margin_us < 0)
-				/* Use CPUTS to save stack space */
-				CPUTS("Idle overslept!\n");
-
-			/* Record the closest to missing a deadline. */
-			if (margin_us < dsleep_recovery_margin_us)
-				dsleep_recovery_margin_us = margin_us;
-		} else {
-			idle_sleep_cnt++;
-
-			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
-		}
-		asm volatile("cpsie i");
-	}
-}
-
-/*****************************************************************************/
-/* Console commands */
-/* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
-{
-	timestamp_t ts = get_time();
-
-	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
-	ccprintf("Time spent in deep-sleep:            %.6llus\n",
-			idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llus\n", ts.val);
-	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
-			"Print last idle stats");
-#endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c
deleted file mode 100644
index 63f5b874bc..0000000000
--- a/chip/stm32/clock-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock-stm32l4.c"
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
deleted file mode 100644
index 3c51086c26..0000000000
--- a/chip/stm32/config-stm32f03x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CHIP_VARIANT_STM32F03X8
-#define CONFIG_FLASH_SIZE_BYTES 0x00010000
-#define CONFIG_RAM_SIZE   0x00002000
-#else
-#define CONFIG_FLASH_SIZE_BYTES 0x00008000
-#define CONFIG_RAM_SIZE   0x00001000
-#endif
-
-/* Memory mapping */
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
deleted file mode 100644
index 00bf45fde5..0000000000
--- a/chip/stm32/config-stm32f05x.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES (64 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
deleted file mode 100644
index 918a117a22..0000000000
--- a/chip/stm32/config-stm32f07x.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Reduced history because of limited RAM */
-#undef CONFIG_CONSOLE_HISTORY
-#define CONFIG_CONSOLE_HISTORY 3
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
deleted file mode 100644
index 9dc27a1fb2..0000000000
--- a/chip/stm32/config-stm32f09x.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-/*
- * Flash physical size: 256KB
- * Write protect sectors: 31 4KB sectors, one 132KB sector
- */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/*
- * STM32F09x flash layout:
- * - RO image starts at the beginning of flash: sector 0 ~ 29
- * - PSTATE immediately follows the RO image: sector 30
- * - RW image starts at 0x1f00: sector 31
- * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30
- * - Unprotected region consists of second half of RW image
- *
- *                            PSTATE(4KB)
- *                              |
- *          (124KB)             v            (132KB)
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| |<----------RW image----------->|
- * 0        (120KB)            ^ ^
- *                             | |
- *                             | 31(132KB sector)
- *                             |
- *                             30
- *
- */
-
-#define _SECTOR_4KB             (4 * 1024)
-#define _SECTOR_132KB           (132 * 1024)
-
-/* The EC uses one sector to emulate persistent state */
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   _SECTOR_4KB
-#define CONFIG_FW_PSTATE_OFF    (30 * _SECTOR_4KB)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (30 * _SECTOR_4KB)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          _SECTOR_132KB
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          32
-#define WP_BANK_COUNT           31
-#define PSTATE_BANK             30
-#define PSTATE_BANK_COUNT       1
-
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
deleted file mode 100644
index 3df5bfce67..0000000000
--- a/chip/stm32/config-stm32f373.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x2000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 81
-
-/* STM32F3 uses the older 4 byte aligned access mechanism */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h
deleted file mode 100644
index 73c9a3694f..0000000000
--- a/chip/stm32/config-stm32f4.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024)
-#else
-#	define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-#endif
-
-/* 3 regions type: 16K, 64K and 128K */
-#define SIZE_16KB (16 * 1024)
-#define SIZE_64KB (64 * 1024)
-#define SIZE_128KB (128 * 1024)
-#define CONFIG_FLASH_REGION_TYPE_COUNT 3
-#define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB)
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* minimum write size for 3.3V. 1 for 1.8V */
-#define STM32_FLASH_WRITE_SIZE_1800 1
-#define STM32_FLASH_WS_DIV_1800 16000000
-#define STM32_FLASH_WRITE_SIZE_3300 4
-#define STM32_FLASH_WS_DIV_3300 30000000
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-#ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00040000 /* 256 KB */
-#else
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00020000 /* 128 KB */
-#endif
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(256 * 1024)
-#define CONFIG_RW_MEM_OFF	(256 * 1024)
-#define CONFIG_RW_SIZE		(256 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Use OTP regions */
-#define CONFIG_OTP
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	97
-
-#undef CONFIG_CMD_CHARGEN
diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h
deleted file mode 100644
index d027ad62fb..0000000000
--- a/chip/stm32/config-stm32f76x.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
-
-/* 3 regions type: 32K, 128K and 256K */
-#define SIZE_32KB (32 * 1024)
-#define SIZE_128KB (128 * 1024)
-#define SIZE_256KB (256 * 1024)
-#define CONFIG_FLASH_REGION_TYPE_COUNT 3
-#define CONFIG_FLASH_MULTIPLE_REGION \
-	(5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB)
-
-/* Erasing 256K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* minimum write size for 3.3V. 1 for 1.8V */
-#define STM32_FLASH_WRITE_SIZE_1800 1
-#define STM32_FLASH_WS_DIV_1800 16000000
-#define STM32_FLASH_WRITE_SIZE_3300 4
-#define STM32_FLASH_WS_DIV_3300 30000000
-
-/* No page mode on STM32F, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
-/* SRAM1:    368kB 0x20020000 - 0x2007BFFF */
-/* SRAM2:     16kB 0x2007C000 - 0x2007FFFF */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00080000
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(1024 * 1024)
-#define CONFIG_RW_MEM_OFF	(1024 * 1024)
-#define CONFIG_RW_SIZE		(1024 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	109
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
deleted file mode 100644
index 4f1ed96871..0000000000
--- a/chip/stm32/config-stm32g41xb.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Memory mapping for STM32G431xb. The STM32G431xb is a category 2 device within
- * the STM32G4 chip family. Category 2 devices have either 32, 64, or 128 kB of
- * internal flash. The 'xB' indicates 128 kB of internal flash.
- *
- * STM32G431x is a single bank only device consisting of 64 pages of 2 kB
- * each. It supports both a mass erase or page erase feature. Note that
- * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
- * for the STM32G4 chip family. The minimum erase size is 1 page.
- *
- * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
- * PSTATE in single bank memories with a write size > 4 bytes.
- */
-
-#define CONFIG_FLASH_SIZE_BYTES       (128 * 1024)
-#define CONFIG_FLASH_WRITE_SIZE 0x0004
-#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
-
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* No page mode on STM32G4, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/*
- * STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM
- * is split into three blocks:
- * • 16 Kbytes mapped at address 0x2000 0000 (SRAM1).
- * •  6 Kbytes mapped at address 0x2000 4000 (SRAM2).
- * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
- *   at 0x2000 5800 address to be accessed by all bus controllers.
- */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00008000
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	3
-
-/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 12
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h
deleted file mode 100644
index 1cb5133121..0000000000
--- a/chip/stm32/config-stm32g473xc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Memory mapping for STM32G473xc. The STM32G473xc is a category 1 device within
- * the STM32G4 chip family. Category 1 devices have either 128, 256, or 512 kB
- * of internal flash. 'xc' indicates 256 kB of internal flash.
- *
- * STM32G473xc can be configured via option bytes as either a single bank or
- * dual bank device. Dual bank is the default selection.
- * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
- * for the STM32G4 chip family. In dual bank mode, the flash is organized in 2
- * kB pages, with 64 pages per bank for this variant.
- *
- * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
- * PSTATE in single bank memories with a write size > 4 bytes.
- *
- * TODO(b/181874494): Verify that dual bank mode should be used, or add support
- * for enabling single bank mode on STM32G473xc.
- */
-#define CONFIG_FLASH_SIZE_BYTES (256 * 1024)
-#define CONFIG_FLASH_WRITE_SIZE 0x0004
-#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
-
-/* Dual-bank (DBANK) mode is enabled by default for this chip */
-#define STM32_FLASH_DBANK_MODE
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/* No page mode on STM32G4, so no benefit to larger write sizes */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
-
-/*
- * STM32G473xc is a category 3 SRAM device featuring 128 Kbytes of embedded
- * SRAM. This SRAM is split into three blocks:
- * • 80 Kbytes mapped at address 0x2000 0000 (SRAM1).
- * • 16 Kbytes mapped at address 0x2001 4000 (SRAM2).
- * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
- *   at 0x2001 8000 address to be accessed by all bus controllers.
- */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00020000
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 12
-
-/* Use PSTATE embedded in the RO image, not in its own erase block */
-#define CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h
deleted file mode 100644
index da94b09069..0000000000
--- a/chip/stm32/config-stm32h7x3.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE (128 * 1024)  /* erase bank size */
-/* always use 256-bit writes due to ECC */
-#define CONFIG_FLASH_WRITE_SIZE          32   /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE    32
-
-/*
- * What the code is calling 'bank' is really the size of the block used for
- * write-protected, here it's 128KB sector (same as erase size).
- */
-#define CONFIG_FLASH_BANK_SIZE  (128 * 1024)
-
-/* Erasing 128K can take up to 2s, need to defer erase. */
-#define CONFIG_FLASH_DEFERRED_ERASE
-
-/*       ITCM-RAM:  64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */
-/*       DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */
-/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */
-/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */
-/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */
-/* (D2) AHB-SRAM3:  32kB 0x30040000 - 0x30047FFF */
-/* (D3) AHB-SRAM4:  64kB 0x38000000 - 0x3800FFFF */
-/* (D3) backup RAM:  4kB 0x38800000 - 0x38800FFF */
-#define CONFIG_RAM_BASE		0x24000000
-#define CONFIG_RAM_SIZE		0x00080000
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(128 * 1024)
-#define CONFIG_RW_MEM_OFF	(CONFIG_FLASH_SIZE_BYTES / 2)
-#define CONFIG_RW_SIZE		(512 * 1024)
-
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/*
- * Cannot use PSTATE:
- * 128kB blocks are too large and ECC prevents re-writing PSTATE word.
- */
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_PSTATE_BANK
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	150
-
-/* the Cortex-M7 core has 'standard' ARMv7-M caches */
-#define CONFIG_ARMV7M_CACHE
-/* Use the MPU to configure cacheability */
-#define CONFIG_MPU
-/* Store in uncached buffers for DMA transfers in ahb4 region */
-#define CONFIG_CHIP_UNCACHED_REGION ahb4
-/* Override MPU attribute settings to match the chip requirements */
-/* Code is Normal memory type / non-shareable / write-through */
-#define MPU_ATTR_FLASH_MEMORY  0x02
-/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */
-#define MPU_ATTR_INTERNAL_SRAM 0x0B
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
deleted file mode 100644
index 2c4efcc6df..0000000000
--- a/chip/stm32/config-stm32l100.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
-
-/*
- * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
- * a time), but that's really slow, and older host interfaces which can't ask
- * about the ideal size would then end up writing in that mode instead of the
- * faster page mode.  So lie about the write size for now.  Once all software
- * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1
- * of EC_CMD_GET_FLASH_INFO, we can remove this workaround.
- */
-#define CONFIG_FLASH_WRITE_SIZE 0x0080
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002800
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 45
-
-/* Flash erases to 0, not 1 */
-#define CONFIG_FLASH_ERASED_VALUE32 0
-
-/* Use DMA for UART receive */
-#define CONFIG_UART_RX_DMA
-
-/* Fake hibernate mode */
-#define CONFIG_STM32L_FAKE_HIBERNATE
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
deleted file mode 100644
index 0b32f95572..0000000000
--- a/chip/stm32/config-stm32l15x.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
-
-/*
- * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
- * a time), but that's really slow, and older host interfaces which can't ask
- * about the ideal size would then end up writing in that mode instead of the
- * faster page mode.  So lie about the write size for now.  Once all software
- * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1
- * of EC_CMD_GET_FLASH_INFO, we can remove this workaround.
- */
-#define CONFIG_FLASH_WRITE_SIZE 0x0080
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
-
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 45
-
-/* Lots of RAM, so use bigger UART buffer */
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 2048
-
-/* Use DMA for UART receive */
-#define CONFIG_UART_RX_DMA
-
-/* Flash erases to 0, not 1 */
-#define CONFIG_FLASH_ERASED_VALUE32 0
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h
deleted file mode 100644
index 7021bc2ce8..0000000000
--- a/chip/stm32/config-stm32l431.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE \
-	0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
-
-/*
- * STM32L431 flash layout:
- * - RO image starts at the beginning of flash: sector 0 ~ 61
- * - PSTATE immediately follows the RO image: sector 62
- * - RW image starts at 0x1f800: sector 63
- * - Protected region consists of the RO image + PSTATE: sector 0 ~ 62
- * - Unprotected region consists of second half of RW image
- *
- *                            PSTATE(2KB)
- *                              |
- *          (126KB)             v            (130KB)
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| |<----------RW image----------->|
- * 0        (124KB)            ^ ^
- *                             | |
- *                             | 63(2KB sector)
- *                             |
- *                             62
- *
- */
-
-
-
-/* The EC uses one sector to emulate persistent state */
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (62 * CONFIG_FLASH_BANK_SIZE)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (62 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \
-                                 CONFIG_RW_STORAGE_OFF)
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          128
-#define WP_BANK_COUNT           63
-#define PSTATE_BANK             62
-#define PSTATE_BANK_COUNT       1
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h
deleted file mode 100644
index 54ba9bac8d..0000000000
--- a/chip/stm32/config-stm32l442.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h
deleted file mode 100644
index 2e0084fd94..0000000000
--- a/chip/stm32/config-stm32l476.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00100000	/* 1 MB */
-#define CONFIG_FLASH_BANK_SIZE  0x800	/* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800	/* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8	/* 64 bits (without 8 bits ECC) */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100	/* 256 (32 double words) */
-
-#define CONFIG_RAM_BASE         0x20000000
-/* Only using SRAM1. SRAM2 (32 KB) is ignored. */
-#define CONFIG_RAM_SIZE         0x00018000	/* 96 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 82
diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h
deleted file mode 100644
index 6953df3950..0000000000
--- a/chip/stm32/config-stm32l552xe.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000   /* 512 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
-
-/* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
-
-/*
- * SRAM1 (48kB) at 0x20000000
- * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
- * so they are contiguous.
- */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 109
-
-/* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x4000D800
-#define CONFIG_USB_RAM_SIZE        1024
-#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
-#define CONFIG_USB_RAM_ACCESS_SIZE 4
-
-#undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
-
-/* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */
-#define DMAC_COUNT 16
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
deleted file mode 100644
index 4d630909e1..0000000000
--- a/chip/stm32/config_chip.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#ifdef CHIP_FAMILY_STM32F0
-/* CPU core BFD configuration */
-#include "core/cortex-m0/config_core.h"
-/* IRQ priorities */
-#define STM32_IRQ_EXT0_1_PRIORITY	1
-#define STM32_IRQ_EXT2_3_PRIORITY	1
-#define STM32_IRQ_EXTI4_15_PRIORITY	1
-#else
-/* CPU core BFD configuration */
-#include "core/cortex-m/config_core.h"
-#define STM32_IRQ_EXTI0_PRIORITY	1
-#define STM32_IRQ_EXTI1_PRIORITY	1
-#define STM32_IRQ_EXTI2_PRIORITY	1
-#define STM32_IRQ_EXTI3_PRIORITY	1
-#define STM32_IRQ_EXTI4_PRIORITY	1
-#define STM32_IRQ_EXTI9_5_PRIORITY	1
-#define STM32_IRQ_EXTI15_10_PRIORITY	1
-#endif
-
-/* Default to UART 1 for EC console */
-#define CONFIG_UART_CONSOLE 1
-
-/* Use variant specific configuration for flash / UART / IRQ */
-/* STM32F03X8 it itself a variant of STM32F03X with non-default flash sizes */
-#ifdef CHIP_VARIANT_STM32F03X8
-#define CHIP_VARIANT_STM32F03X
-#endif
-
-/* Number of I2C ports, can be overridden in variant */
-#define I2C_PORT_COUNT 2
-
-#if defined(CHIP_VARIANT_STM32L476)
-#include "config-stm32l476.h"
-#elif defined(CHIP_VARIANT_STM32L15X)
-#include "config-stm32l15x.h"
-#elif defined(CHIP_VARIANT_STM32L100)
-#include "config-stm32l100.h"
-#elif defined(CHIP_VARIANT_STM32L442)
-#include "config-stm32l442.h"
-#elif defined(CHIP_VARIANT_STM32L552XE)
-#include "config-stm32l552xe.h"
-#elif defined(CHIP_VARIANT_STM32F76X)
-#include "config-stm32f76x.h"
-#elif defined(CHIP_FAMILY_STM32F4)
-/* STM32F4 family */
-#include "config-stm32f4.h"
-#elif defined(CHIP_VARIANT_STM32F373)
-#include "config-stm32f373.h"
-#elif defined(CHIP_VARIANT_STM32F09X)
-/* STM32F09xx */
-#include "config-stm32f09x.h"
-#elif defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F070)
-/* STM32F07xx */
-#include "config-stm32f07x.h"
-#elif defined(CHIP_VARIANT_STM32F05X)
-/* STM32F05xx */
-#include "config-stm32f05x.h"
-#elif defined(CHIP_VARIANT_STM32F03X)
-/* STM32F03x */
-#include "config-stm32f03x.h"
-#elif defined(CHIP_VARIANT_STM32H7X3)
-#include "config-stm32h7x3.h"
-#elif defined(CHIP_VARIANT_STM32G431XB)
-#include "config-stm32g41xb.h"
-#elif defined(CHIP_VARIANT_STM32G473XC)
-#include "config-stm32g473xc.h"
-#elif defined(CHIP_VARIANT_STM32L431X)
-#include "config-stm32l431.h"
-#else
-#error "Unsupported chip variant"
-#endif
-
-#define CONFIG_PROGRAM_MEMORY_BASE 0x08000000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-#if !defined(CHIP_FAMILY_STM32F4) && \
-	!defined(CHIP_FAMILY_STM32F7) && \
-	!defined(CHIP_FAMILY_STM32H7) && \
-	!defined(CHIP_VARIANT_STM32F09X) && \
-	!defined(CHIP_VARIANT_STM32L431X)
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-#endif
-
-/* Additional special purpose regions (USB RAM and other special SRAMs) */
-#define CONFIG_CHIP_MEMORY_REGIONS
-
-/* System stack size */
-#if defined(CHIP_VARIANT_STM32F05X)
-#define CONFIG_STACK_SIZE 768
-#else
-#define CONFIG_STACK_SIZE 1024
-#endif
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Smaller task stack size */
-#define SMALLER_TASK_STACK_SIZE 384
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Even bigger */
-#define VENTI_TASK_STACK_SIZE 768
-#define ULTRA_TASK_STACK_SIZE 1056
-#define TRENTA_TASK_STACK_SIZE 1184
-
-/*
- * Console stack size. For test builds, the console is used to interact with
- * the test, and insufficient stack size causes console stack overflow after
- * running the on-device tests.
- */
-#define CONSOLE_TASK_STACK_SIZE 4096
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/*
- * Use a timer to print a watchdog warning event before the actual watchdog
- * timer fires.  This is needed on STM32, where the independent watchdog has no
- * early warning feature and the windowed watchdog has a very short period.
- */
-#define CONFIG_WATCHDOG_HELP
-
-/* Use DMA */
-#define CONFIG_DMA
-
-/* STM32 features RTC (optional feature) */
-#define CONFIG_RTC
-
-/* Number of peripheral request signals per DMA channel */
-#define STM32_DMA_PERIPHERALS_PER_CHANNEL	4
-
-/*
- * Use DMA for UART transmit for all platforms.  DMA for UART receive is
- * enabled on a per-chip basis because it doesn't seem to work reliably on
- * STM32F (see crosbug.com/p/24141).
- */
-#define CONFIG_UART_TX_DMA
-
-#ifndef CHIP_FAMILY_STM32H7
-/* Flash protection applies to the next boot, not the current one */
-#define CONFIG_FLASH_PROTECT_NEXT_BOOT
-#endif /* !CHIP_FAMILY_STM32H7 */
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_NAME_BY_PIN(port, index) #port#index
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-/* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */
-#define STM32_PLLM	1
-#define STM32_PLLN	1
-#define STM32_PLLR	1
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
deleted file mode 100644
index 2a50d5760e..0000000000
--- a/chip/stm32/crc_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CRC_HW_H
-#define __CROS_EC_CRC_HW_H
-/* CRC-32 hardware implementation with USB constants */
-
-#include "clock.h"
-#include "registers.h"
-
-static inline void crc32_init(void)
-{
-	/* switch on CRC controller */
-	STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-	/* reset CRC state */
-	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT
-		     | STM32_CRC_CR_REV_IN_WORD;
-	while (STM32_CRC_CR & 1)
-		;
-}
-
-static inline void crc32_hash32(uint32_t val)
-{
-	STM32_CRC_DR = val;
-}
-
-static inline void crc32_hash16(uint16_t val)
-{
-	STM32_CRC_DR16 = val;
-}
-
-static inline uint32_t crc32_result(void)
-{
-	return STM32_CRC_DR ^ 0xFFFFFFFF;
-}
-
-#endif /* __CROS_EC_CRC_HW_H */
diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c
deleted file mode 100644
index c4e151692c..0000000000
--- a/chip/stm32/debug_printf.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Synchronous UART debug printf */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "printf.h"
-#include "registers.h"
-#include "util.h"
-
-static int debug_txchar(void *context, int c)
-{
-	if (c == '\n') {
-		while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-			;
-		STM32_USART_TDR(UARTN_BASE) = '\r';
-	}
-
-	/* Wait for space to transmit */
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-		;
-	STM32_USART_TDR(UARTN_BASE) = c;
-
-	return 0;
-}
-
-
-
-void debug_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-void cflush(void)
-{
-	/* Wait for transmit complete */
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC))
-		;
-}
-
-int cputs(enum console_channel channel, const char *outstr)
-{
-	debug_printf(outstr);
-
-	return 0;
-}
-
-void panic_puts(const char *outstr)
-{
-	debug_printf(outstr);
-	cflush();
-}
-
-int cprintf(enum console_channel channel, const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	return 0;
-}
-
-void panic_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	cflush();
-}
-
-int cprints(enum console_channel channel, const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(debug_txchar, NULL, format, args);
-	va_end(args);
-
-	debug_printf("\n");
-
-	return 0;
-}
-
-void uart_init(void)
-{
-	/* Enable USART1 clock */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
-	/* set baudrate */
-	STM32_USART_BRR(UARTN_BASE) =
-		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
-	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN_BASE) = 0x0000;
-	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN_BASE) = 0x0000;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_UART, 1);
-}
-#endif
diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h
deleted file mode 100644
index 6091cfc7fc..0000000000
--- a/chip/stm32/debug_printf.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Synchronous UART debug printf */
-
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
-
-#ifdef CONFIG_DEBUG_PRINTF
-__attribute__((__format__(__printf__, 1, 2)))
-void debug_printf(const char *format, ...);
-#else
-#define debug_printf(...)
-#endif
-
-#endif /* __CROS_EC_DEBUG_H */
diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c
deleted file mode 100644
index 860874de8c..0000000000
--- a/chip/stm32/dma-stm32f4.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
-
-stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS };
-
-/* Callback data to use when IRQ fires */
-static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
-} dma_irq[STM32_DMAS_TOTAL_COUNT];
-
-/**
- * Return the IRQ for the DMA stream
- *
- * @param stream	stream number
- * @return IRQ for the stream
- */
-static int dma_get_irq(enum dma_channel stream)
-{
-	if (stream < STM32_DMA1_STREAM6)
-		return STM32_IRQ_DMA1_STREAM0 + stream;
-	if (stream == STM32_DMA1_STREAM7)
-		return STM32_IRQ_DMA1_STREAM7;
-	if (stream < STM32_DMA2_STREAM5)
-		return STM32_IRQ_DMA2_STREAM0 + stream - STM32_DMA2_STREAM0;
-	else
-		return STM32_IRQ_DMA2_STREAM5 + stream - STM32_DMA2_STREAM5;
-}
-
-stm32_dma_regs_t *dma_get_ctrl(enum dma_channel stream)
-{
-	return STM32_DMA_REGS[stream / STM32_DMAS_COUNT];
-}
-
-stm32_dma_stream_t *dma_get_channel(enum dma_channel stream)
-{
-	stm32_dma_regs_t *dma = dma_get_ctrl(stream);
-
-	return &dma->stream[stream % STM32_DMAS_COUNT];
-}
-
-#ifdef CHIP_FAMILY_STM32H7
-void dma_select_channel(enum dma_channel channel, uint8_t req)
-{
-	STM2_DMAMUX_CxCR(DMAMUX1, channel) = req;
-}
-#endif
-
-void dma_disable(enum dma_channel ch)
-{
-	stm32_dma_stream_t *stream = dma_get_channel(ch);
-
-	if (stream->scr & STM32_DMA_CCR_EN) {
-		stream->scr &= ~STM32_DMA_CCR_EN;
-		while (stream->scr & STM32_DMA_CCR_EN)
-			;
-	}
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-
-	for (ch = 0; ch < STM32_DMAS_TOTAL_COUNT; ch++)
-		dma_disable(ch);
-}
-
-/**
- * Prepare a stream for use and start it
- *
- * @param stream	stream to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register.
- */
-static void prepare_stream(enum dma_channel stream, unsigned count,
-		void *periph, void *memory, unsigned flags)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
-
-	dma_disable(stream);
-	dma_clear_isr(stream);
-
-	/* Following the order in DocID026448 Rev 1 (RM0383) p181 */
-	dma_stream->spar = (uint32_t)periph;
-	dma_stream->sm0ar = (uint32_t)memory;
-	dma_stream->sndtr = count;
-	dma_stream->scr = ccr;
-	ccr |= flags & STM32_DMA_CCR_CHANNEL_MASK;
-	dma_stream->scr = ccr;
-	dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
-	ccr |= flags;
-	dma_stream->scr = ccr;
-}
-
-void dma_go(stm32_dma_stream_t *stream)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	stream->scr |= STM32_DMA_CCR_EN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned count,
-		    const void *memory)
-{
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the stream for transmit.
-	 */
-	prepare_stream(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
-			option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
-{
-	stm32_dma_stream_t *stream = dma_get_channel(option->channel);
-
-	prepare_stream(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
-			option->flags);
-	dma_go(stream);
-}
-
-int dma_bytes_done(stm32_dma_stream_t *stream, int orig_count)
-{
-	/*
-	 * Note that we're intentionally not checking that DMA is enabled here
-	 * because there is a race when the hardware stops the transfer:
-	 *
-	 * From Section 9.3.14 DMA transfer completion in RM0402 Rev 5
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf:
-	 * If the stream is configured in non-circular mode, after the end of
-	 * the transfer (that is when the number of data to be transferred
-	 * reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is
-	 * cleared by Hardware) and no DMA request is served unless the software
-	 * reprograms the stream and re-enables it (by setting the EN bit in the
-	 * DMA_SxCR register).
-	 *
-	 * See http://b/132444384 for full details.
-	 */
-	return orig_count - stream->sndtr;
-}
-
-bool dma_is_enabled(stm32_dma_stream_t *stream)
-{
-	return (stream->scr & STM32_DMA_CCR_EN);
-}
-
-#ifdef CONFIG_DMA_HELP
-void dma_dump(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n",
-		dma_stream->scr, dma_stream->sndtr, dma_stream->spar,
-		dma_stream->sm0ar, dma_stream->sfcr);
-	CPRINTF("stream %d, isr=%x, ifcr=%x\n",
-		stream,
-		STM32_DMA_GET_ISR(stream),
-		STM32_DMA_GET_IFCR(stream));
-}
-
-void dma_check(enum dma_channel stream, char *buf)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	int count;
-	int i;
-
-	count = dma_stream->sndtr;
-	CPRINTF("c=%d\n", count);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", dma_stream->sndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", dma_stream->sndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-}
-
-/* Run a check of memory-to-memory DMA */
-void dma_test(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-	uint32_t ctrl;
-	char periph[32], memory[32];
-	unsigned count = sizeof(periph);
-	int i;
-
-	memset(memory, '\0', sizeof(memory));
-	for (i = 0; i < count; i++)
-		periph[i] = 10 + i;
-
-	dma_clear_isr(stream);
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	dma_stream->spar = (uint32_t)periph;
-	dma_stream->sm0ar = (uint32_t)memory;
-	dma_stream->sndtr = count;
-	dma_stream->sfcr  &= ~STM32_DMA_SFCR_DMDIS;
-	ctrl = STM32_DMA_CCR_PL_MEDIUM;
-	dma_stream->scr = ctrl;
-
-	ctrl |= STM32_DMA_CCR_MINC;
-	ctrl |= STM32_DMA_CCR_DIR_M2M;
-	ctrl |= STM32_DMA_CCR_PINC;
-
-	dma_stream->scr = ctrl;
-	dma_dump(stream);
-	dma_stream->scr = ctrl | STM32_DMA_CCR_EN;
-
-	for (i = 0; i < count; i++)
-		CPRINTF("%d/%d ", periph[i], memory[i]);
-	CPRINTF("\ncount=%d\n", dma_stream->sndtr);
-	dma_dump(stream);
-}
-#endif /* CONFIG_DMA_HELP */
-
-void dma_init(void)
-{
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1 | STM32_RCC_HB1_DMA2;
-}
-
-int dma_wait(enum dma_channel stream)
-{
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while ((STM32_DMA_GET_ISR(stream) & STM32_DMA_TCIF) == 0) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static inline void _dma_wake_callback(void *cb_data)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC);
-}
-
-void dma_enable_tc_interrupt(enum dma_channel stream)
-{
-	dma_enable_tc_interrupt_callback(stream, _dma_wake_callback,
-					 (void *)(int)task_get_current());
-}
-
-void dma_enable_tc_interrupt_callback(enum dma_channel stream,
-				      void (*callback)(void *),
-				      void *callback_data)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	dma_irq[stream].cb = callback;
-	dma_irq[stream].cb_data = callback_data;
-
-	dma_stream->scr |= STM32_DMA_CCR_TCIE;
-	task_enable_irq(dma_get_irq(stream));
-}
-
-void dma_disable_tc_interrupt(enum dma_channel stream)
-{
-	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
-
-	dma_stream->scr &= ~STM32_DMA_CCR_TCIE;
-	task_disable_irq(dma_get_irq(stream));
-
-	dma_irq[stream].cb = NULL;
-	dma_irq[stream].cb_data = NULL;
-}
-
-void dma_clear_isr(enum dma_channel stream)
-{
-	STM32_DMA_SET_IFCR(stream, STM32_DMA_ALL);
-}
-
-#ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#define STM32_DMA_IDX(dma, x)   CONCAT4(STM32_DMA, dma, _STREAM, x)
-#define STM32_DMA_FCT(dma, x)   CONCAT4(dma_, dma, _event_interrupt_stream_, x)
-#define DECLARE_DMA_IRQ(dma, x) \
-	void STM32_DMA_FCT(dma, x)(void) \
-	{ \
-		dma_clear_isr(STM32_DMA_IDX(dma, x)); \
-		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \
-			(*dma_irq[STM32_DMA_IDX(dma, x)].cb) \
-				(dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \
-		    STM32_DMA_FCT(dma, x), 1);
-
-DECLARE_DMA_IRQ(1, 0);
-DECLARE_DMA_IRQ(1, 1);
-DECLARE_DMA_IRQ(1, 2);
-DECLARE_DMA_IRQ(1, 3);
-DECLARE_DMA_IRQ(1, 4);
-DECLARE_DMA_IRQ(1, 5);
-DECLARE_DMA_IRQ(1, 6);
-DECLARE_DMA_IRQ(1, 7);
-DECLARE_DMA_IRQ(2, 0);
-DECLARE_DMA_IRQ(2, 1);
-DECLARE_DMA_IRQ(2, 2);
-DECLARE_DMA_IRQ(2, 3);
-DECLARE_DMA_IRQ(2, 4);
-DECLARE_DMA_IRQ(2, 5);
-DECLARE_DMA_IRQ(2, 6);
-DECLARE_DMA_IRQ(2, 7);
-
-#endif /* CONFIG_DMA_DEFAULT_HANDLERS */
-
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
deleted file mode 100644
index 55317ba003..0000000000
--- a/chip/stm32/dma.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-
-/* Callback data to use when IRQ fires */
-static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
-} dma_irq[STM32_DMAC_COUNT];
-
-
-/**
- * Return the IRQ for the DMA channel
- *
- * @param channel	Channel number
- * @return IRQ for the channel
- */
-static int dma_get_irq(enum dma_channel channel)
-{
-#ifdef CHIP_FAMILY_STM32F0
-	if (channel == STM32_DMAC_CH1)
-		return STM32_IRQ_DMA_CHANNEL_1;
-
-	return channel > STM32_DMAC_CH3 ?
-		STM32_IRQ_DMA_CHANNEL_4_7 :
-		STM32_IRQ_DMA_CHANNEL_2_3;
-#elif defined(CHIP_FAMILY_STM32L4)
-	if (channel < STM32_DMAC_PER_CTLR)
-		return STM32_IRQ_DMA_CHANNEL_1 + channel;
-	else {
-		if (channel <= STM32_DMAC_CH13)
-			return STM32_IRQ_DMA2_CHANNEL1 +
-			       (channel - STM32_DMAC_PER_CTLR);
-		else
-			return STM32_IRQ_DMA2_CHANNEL6 +
-			       (channel - STM32_DMAC_PER_CTLR - 5);
-	}
-#else
-	if (channel < STM32_DMAC_PER_CTLR)
-		return STM32_IRQ_DMA_CHANNEL_1 + channel;
-	else
-		return STM32_IRQ_DMA2_CHANNEL1 +
-			(channel - STM32_DMAC_PER_CTLR);
-#endif
-}
-
-/*
- * Note, you must decrement the channel value by 1 from what is specified
- * in the datasheets, as they index from 1 and this indexes from 0!
- */
-stm32_dma_chan_t *dma_get_channel(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-
-	return &dma->chan[channel % STM32_DMAC_PER_CTLR];
-}
-
-#ifdef STM32_DMAMUX_CxCR
-void dma_select_channel(enum dma_channel channel, uint8_t req)
-{
-	/*
-	 * STM32G4 includes a DMAMUX block which is used to handle dma requests
-	 * by peripherals. The correct 'req' number for a given peripheral is
-	 * given in ST doc RM0440.
-	 */
-	STM32_DMAMUX_CxCR(channel) = req;
-}
-#elif defined(STM32_DMA_CSELR)
-void dma_select_channel(enum dma_channel channel, unsigned char stream)
-{
-	/* Local channel # starting from 0 on each DMA controller */
-	const unsigned char ch = channel % STM32_DMAC_PER_CTLR;
-	const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL;
-	const unsigned char mask = BIT(shift) - 1;
-	uint32_t val;
-
-	ASSERT(ch < STM32_DMAC_PER_CTLR);
-	ASSERT(stream <= mask);
-	val = STM32_DMA_CSELR(channel) & ~(mask << ch * shift);
-	STM32_DMA_CSELR(channel) = val | (stream << ch * shift);
-}
-#endif /* STM32_DMAMUX_CxCR/STM32_DMA_CSELR */
-
-void dma_disable(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	if (chan->ccr & STM32_DMA_CCR_EN)
-		chan->ccr &= ~STM32_DMA_CCR_EN;
-}
-
-void dma_disable_all(void)
-{
-	int ch;
-
-	for (ch = 0; ch < STM32_DMAC_COUNT; ch++) {
-		stm32_dma_chan_t *chan = dma_get_channel(ch);
-
-		chan->ccr &= ~STM32_DMA_CCR_EN;
-	}
-}
-
-/**
- * Prepare a channel for use and start it
- *
- * @param chan		Channel to read
- * @param count		Number of bytes to transfer
- * @param periph	Pointer to peripheral data register
- * @param memory	Pointer to memory address for receive/transmit
- * @param flags		DMA flags for the control register, normally:
- *				STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx
- *				0 for rx
- */
-static void prepare_channel(enum dma_channel channel, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
-
-	dma_disable(channel);
-	dma_clear_isr(channel);
-
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	chan->cpar = (uint32_t)periph;
-	chan->cmar = (uint32_t)memory;
-	chan->cndtr = count;
-	chan->ccr = ccr;
-	ccr |= flags;
-	chan->ccr = ccr;
-}
-
-void dma_go(stm32_dma_chan_t *chan)
-{
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dsb;");
-
-	/* Fire it up */
-	chan->ccr |= STM32_DMA_CCR_EN;
-}
-
-void dma_prepare_tx(const struct dma_option *option, unsigned int count,
-		    const void *memory)
-{
-	/*
-	 * Cast away const for memory pointer; this is ok because we know
-	 * we're preparing the channel for transmit.
-	 */
-	prepare_channel(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
-			option->flags);
-}
-
-void dma_start_rx(const struct dma_option *option, unsigned int count,
-		  void *memory)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(option->channel);
-
-	prepare_channel(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | option->flags);
-	dma_go(chan);
-}
-
-int dma_bytes_done(stm32_dma_chan_t *chan, int orig_count)
-{
-	return orig_count - chan->cndtr;
-}
-
-bool dma_is_enabled(stm32_dma_chan_t *chan)
-{
-	return (chan->ccr & STM32_DMA_CCR_EN);
-}
-
-#ifdef CONFIG_DMA_HELP
-void dma_dump(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
-		chan->cndtr, chan->cpar, chan->cmar);
-	CPRINTF("chan %d, isr=%x, ifcr=%x\n",
-		channel,
-		(dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf,
-		(dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf);
-}
-
-void dma_check(enum dma_channel channel, char *buf)
-{
-	stm32_dma_chan_t *chan;
-	int count;
-	int i;
-
-	chan = dma_get_channel(channel);
-	count = chan->cndtr;
-	CPRINTF("c=%d\n", count);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", chan->cndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-	udelay(100 * MSEC);
-	CPRINTF("c=%d\n", chan->cndtr);
-	for (i = 0; i < count; i++)
-		CPRINTF("%02x ", buf[i]);
-}
-
-/* Run a check of memory-to-memory DMA */
-void dma_test(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-	uint32_t ctrl;
-	char periph[16], memory[16];
-	unsigned int count = sizeof(periph);
-	int i;
-
-	memset(memory, '\0', sizeof(memory));
-	for (i = 0; i < count; i++)
-		periph[i] = 10 + i;
-
-	/* Following the order in Doc ID 15965 Rev 5 p194 */
-	chan->cpar = (uint32_t)periph;
-	chan->cmar = (uint32_t)memory;
-	chan->cndtr = count;
-	ctrl = STM32_DMA_CCR_PL_MEDIUM;
-	chan->ccr = ctrl;
-
-	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
-	ctrl |= STM32_DMA_CCR_MEM2MEM;
-	ctrl |= STM32_DMA_CCR_PINC;
-/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
-/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
-	chan->ccr = ctrl;
-	chan->ccr = ctrl | STM32_DMA_CCR_EN;
-
-	for (i = 0; i < count; i++)
-		CPRINTF("%d/%d ", periph[i], memory[i]);
-	CPRINTF("\ncount=%d\n", chan->cndtr);
-}
-#endif /* CONFIG_DMA_HELP */
-
-void dma_init(void)
-{
-#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN;
-#elif defined(CHIP_FAMILY_STM32G4)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN |
-		STM32_RCC_AHB1ENR_DMAMUXEN;
-#else
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
-#endif
-#ifdef CHIP_FAMILY_STM32F3
-	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA2;
-#endif
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-int dma_wait(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-	const uint32_t mask = STM32_DMA_ISR_TCIF(channel);
-	timestamp_t deadline;
-
-	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
-	while ((dma->isr & mask) != mask) {
-		if (deadline.val <= get_time().val)
-			return EC_ERROR_TIMEOUT;
-
-		udelay(DMA_POLLING_INTERVAL_US);
-	}
-	return EC_SUCCESS;
-}
-
-static inline void _dma_wake_callback(void *cb_data)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_DMA_TC);
-}
-
-void dma_enable_tc_interrupt(enum dma_channel channel)
-{
-	dma_enable_tc_interrupt_callback(channel, _dma_wake_callback,
-					 (void *)(int)task_get_current());
-}
-
-void dma_enable_tc_interrupt_callback(enum dma_channel channel,
-				      void (*callback)(void *),
-				      void *callback_data)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	dma_irq[channel].cb = callback;
-	dma_irq[channel].cb_data = callback_data;
-
-	chan->ccr |= STM32_DMA_CCR_TCIE;
-	task_enable_irq(dma_get_irq(channel));
-}
-
-void dma_disable_tc_interrupt(enum dma_channel channel)
-{
-	stm32_dma_chan_t *chan = dma_get_channel(channel);
-
-	chan->ccr &= ~STM32_DMA_CCR_TCIE;
-	task_disable_irq(dma_get_irq(channel));
-
-	dma_irq[channel].cb = NULL;
-	dma_irq[channel].cb_data = NULL;
-}
-
-void dma_clear_isr(enum dma_channel channel)
-{
-	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
-
-	dma->ifcr |= STM32_DMA_ISR_ALL(channel);
-}
-
-#ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#ifdef CHIP_FAMILY_STM32F0
-void dma_event_interrupt_channel_1(void)
-{
-	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) {
-		dma_clear_isr(STM32_DMAC_CH1);
-		if (dma_irq[STM32_DMAC_CH1].cb != NULL)
-			(*dma_irq[STM32_DMAC_CH1].cb)
-				(dma_irq[STM32_DMAC_CH1].cb_data);
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1);
-
-void dma_event_interrupt_channel_2_3(void)
-{
-	int i;
-
-	for (i = STM32_DMAC_CH2; i <= STM32_DMAC_CH3; i++) {
-		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
-			dma_clear_isr(i);
-			if (dma_irq[i].cb != NULL)
-				(*dma_irq[i].cb)(dma_irq[i].cb_data);
-		}
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1);
-
-void dma_event_interrupt_channel_4_7(void)
-{
-	int i;
-	const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT);
-
-	for (i = STM32_DMAC_CH4; i <= max_chan; i++) {
-		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
-			dma_clear_isr(i);
-			if (dma_irq[i].cb != NULL)
-				(*dma_irq[i].cb)(dma_irq[i].cb_data);
-		}
-	}
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1);
-
-#else /* !CHIP_FAMILY_STM32F0 */
-
-#define DECLARE_DMA_IRQ(x) \
-	void CONCAT2(dma_event_interrupt_channel_, x)(void) \
-	{ \
-		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
-		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
-			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \
-				(dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
-		    CONCAT2(dma_event_interrupt_channel_, x), 1)
-
-DECLARE_DMA_IRQ(1);
-DECLARE_DMA_IRQ(2);
-DECLARE_DMA_IRQ(3);
-DECLARE_DMA_IRQ(4);
-DECLARE_DMA_IRQ(5);
-DECLARE_DMA_IRQ(6);
-DECLARE_DMA_IRQ(7);
-#ifdef CHIP_FAMILY_STM32F3
-DECLARE_DMA_IRQ(9);
-DECLARE_DMA_IRQ(10);
-#endif
-#ifdef CHIP_FAMILY_STM32L4
-DECLARE_DMA_IRQ(9);
-DECLARE_DMA_IRQ(10);
-DECLARE_DMA_IRQ(11);
-DECLARE_DMA_IRQ(12);
-DECLARE_DMA_IRQ(13);
-DECLARE_DMA_IRQ(14);
-DECLARE_DMA_IRQ(15);
-#endif
-
-#endif /* CHIP_FAMILY_STM32F0 */
-#endif /* CONFIG_DMA_DEFAULT_HANDLERS */
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
deleted file mode 100644
index 9e35a2c689..0000000000
--- a/chip/stm32/flash-f.c
+++ /dev/null
@@ -1,833 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common flash memory module for STM32F and STM32F0 */
-
-#include <stdbool.h>
-#include "battery.h"
-#include "console.h"
-#include "clock.h"
-#include "flash.h"
-#include "flash-f.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/*
- * While flash write / erase is in progress, the stm32 CPU core is mostly
- * non-functional, due to the inability to fetch instructions from flash.
- * This may greatly increase interrupt latency.
- */
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_WRITE_TIMEOUT_US 16000
-/* 20ms < tERASE < 40ms on F0/F3, for 1K / 2K sector size. */
-#define FLASH_ERASE_TIMEOUT_US 40000
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-#if !defined(CHIP_FAMILY_STM32F4)
-#error "CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE should work with all STM32F "
-"series chips, but has not been tested"
-#endif /* !CHIP_FAMILY_STM32F4 */
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/* Forward declarations */
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-static enum flash_rdp_level flash_physical_get_rdp_level(void);
-static int flash_physical_set_rdp_level(enum flash_rdp_level level);
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_WRITE_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int wait_busy(void)
-{
-	int timeout = calculate_flash_timeout();
-	while ((STM32_FLASH_SR & FLASH_SR_BUSY) && timeout-- > 0)
-		udelay(CYCLE_PER_FLASH_LOOP);
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-
-void unlock_flash_control_register(void)
-{
-	STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-	STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-}
-
-void unlock_flash_option_bytes(void)
-{
-	STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-	STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-}
-
-void disable_flash_option_bytes(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to the option key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_OPTKEYR = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void disable_flash_control_register(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to the key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_KEYR = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void lock_flash_control_register(void)
-{
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	/* FLASH_CR_OPTWRE was set by writing the keys in unlock(). */
-	STM32_FLASH_CR &= ~FLASH_CR_OPTWRE;
-#endif
-	STM32_FLASH_CR |= FLASH_CR_LOCK;
-}
-
-void lock_flash_option_bytes(void)
-{
-#if !(defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3))
-	STM32_FLASH_OPTCR |= FLASH_OPTLOCK;
-#endif
-}
-
-bool flash_option_bytes_locked(void)
-{
-	return !!STM32_FLASH_OPT_LOCKED;
-}
-
-bool flash_control_register_locked(void)
-{
-	return !!(STM32_FLASH_CR & FLASH_CR_LOCK);
-}
-
-/*
- * We at least unlock the control register lock.
- * We may also unlock other locks.
- */
-enum extra_lock_type  {
-	NO_EXTRA_LOCK = 0,
-	OPT_LOCK = 1,
-};
-
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* Always unlock CR if needed */
-	if (flash_control_register_locked())
-		unlock_flash_control_register();
-
-	/* unlock option memory if required */
-	if ((locks & OPT_LOCK) && flash_option_bytes_locked())
-		unlock_flash_option_bytes();
-
-	/* Re-enable bus fault handler */
-	ignore_bus_fault(0);
-
-	if ((locks & OPT_LOCK) && flash_option_bytes_locked())
-		return EC_ERROR_UNKNOWN;
-	if (STM32_FLASH_CR & FLASH_CR_LOCK)
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static void lock(void)
-{
-	lock_flash_control_register();
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-static int write_optb(uint32_t mask, uint32_t value)
-{
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	/* The target byte is the value we want to write. */
-	if ((STM32_FLASH_OPTCR & mask) == value)
-		return EC_SUCCESS;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	STM32_FLASH_OPTCR = (STM32_FLASH_OPTCR & ~mask) | value;
-	STM32_FLASH_OPTCR |= FLASH_OPTSTRT;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-#else
-static int write_optb(int byte, uint8_t value);
-/*
- * Option byte organization
- *
- *                 [31:24]    [23:16]    [15:8]   [7:0]
- *
- *   0x1FFF_F800    nUSER      USER       nRDP     RDP
- *
- *   0x1FFF_F804    nData1     Data1     nData0    Data0
- *
- *   0x1FFF_F808    nWRP1      WRP1      nWRP0     WRP0
- *
- *   0x1FFF_F80C    nWRP3      WRP2      nWRP2     WRP2
- *
- * Note that the variable with n prefix means the complement.
- */
-static uint8_t read_optb(int byte)
-{
-	return *(uint8_t *)(STM32_OPTB_BASE + byte);
-}
-
-static int erase_optb(void)
-{
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* Must be set in 2 separate lines. */
-	STM32_FLASH_CR |= FLASH_CR_OPTER;
-	STM32_FLASH_CR |= FLASH_CR_STRT;
-
-	rv = wait_busy();
-
-	STM32_FLASH_CR &= ~FLASH_CR_OPTER;
-
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-
-static int write_optb(int byte, uint8_t value);
-/*
- * Since the option byte erase is WHOLE erase, this function is to keep
- * rest of bytes, but make this byte 0xff.
- * Note that this could make a recursive call to write_optb().
- */
-static int preserve_optb(int byte)
-{
-	int i, rv;
-	uint8_t optb[8];
-
-	/* The byte has been reset, no need to run preserve. */
-	if (*(uint16_t *)(STM32_OPTB_BASE + byte) == 0xffff)
-		return EC_SUCCESS;
-
-	for (i = 0; i < ARRAY_SIZE(optb); ++i)
-		optb[i] = read_optb(i * 2);
-
-	optb[byte / 2] = 0xff;
-
-	rv = erase_optb();
-	if (rv)
-		return rv;
-	for (i = 0; i < ARRAY_SIZE(optb); ++i) {
-		rv = write_optb(i * 2, optb[i]);
-		if (rv)
-			return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int write_optb(int byte, uint8_t value)
-{
-	volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
-	int rv;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-
-	/* The target byte is the value we want to write. */
-	if (*(uint8_t *)hword == value)
-		return EC_SUCCESS;
-
-	/* Try to erase that byte back to 0xff. */
-	rv = preserve_optb(byte);
-	if (rv)
-		return rv;
-
-	/* The value is 0xff after erase. No need to write 0xff again. */
-	if (value == 0xff)
-		return EC_SUCCESS;
-
-	rv = unlock(OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* set OPTPG bit */
-	STM32_FLASH_CR |= FLASH_CR_OPTPG;
-
-	*hword = ((~value) << STM32_OPTB_COMPL_SHIFT) | value;
-
-	/* reset OPTPG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_OPTPG;
-
-	rv = wait_busy();
-	if (rv)
-		return rv;
-	lock();
-
-	return EC_SUCCESS;
-}
-#endif
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-/**
- * @return true if RDP (read protection) Level 1 or 2 enabled, false otherwise
- */
-bool is_flash_rdp_enabled(void)
-{
-	enum flash_rdp_level level = flash_physical_get_rdp_level();
-
-	if (level == FLASH_RDP_LEVEL_INVALID) {
-		CPRINTS("ERROR: unable to read RDP level");
-		return false;
-	}
-
-	return level != FLASH_RDP_LEVEL_0;
-}
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-#if CONFIG_FLASH_WRITE_SIZE == 1
-	uint8_t *address = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint8_t quantum = 0;
-#elif CONFIG_FLASH_WRITE_SIZE == 2
-	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint16_t quantum = 0;
-#elif CONFIG_FLASH_WRITE_SIZE == 4
-	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	uint32_t quantum = 0;
-#else
-#error "CONFIG_FLASH_WRITE_SIZE not supported."
-#endif
-	int res = EC_SUCCESS;
-	int timeout = calculate_flash_timeout();
-
-	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) {
-		res = EC_ERROR_UNKNOWN;
-		goto exit_wr;
-	}
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP;
-
-	/* set PG bit */
-	STM32_FLASH_CR |= FLASH_CR_PG;
-
-	for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) {
-		int i;
-
-		for (i = CONFIG_FLASH_WRITE_SIZE - 1, quantum = 0; i >= 0; i--)
-			quantum = (quantum << 8) + data[i];
-		data += CONFIG_FLASH_WRITE_SIZE;
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing with interrupt disabled.
-		 */
-		watchdog_reload();
-
-		/* wait to be ready  */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
-		     i++)
-			;
-
-		/* write the data */
-		*address++ = quantum;
-
-		/* Wait for writes to complete */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
-		     i++)
-			;
-
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/* Check for error conditions - erase failed, voltage error,
-		 * protection error */
-		if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PG;
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int sector_size;
-	int timeout_us;
-#ifdef CHIP_FAMILY_STM32F4
-	int sector = crec_flash_bank_index(offset);
-	/* we take advantage of sector_size == erase_size */
-	if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0))
-		return EC_ERROR_INVAL;  /* Invalid range */
-#endif
-
-	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP;
-
-	/* set SER/PER bit */
-	STM32_FLASH_CR |= FLASH_CR_PER;
-
-	while (size > 0) {
-		timestamp_t deadline;
-#ifdef CHIP_FAMILY_STM32F4
-		sector_size = crec_flash_bank_size(sector);
-		/* Timeout: from spec, proportional to the size
-		 * inversely proportional to the write size.
-		 */
-		timeout_us = sector_size * 4 / CONFIG_FLASH_WRITE_SIZE;
-#else
-		sector_size = CONFIG_FLASH_ERASE_SIZE;
-		timeout_us = FLASH_ERASE_TIMEOUT_US;
-#endif
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased(offset, sector_size))
-			goto next_sector;
-#ifdef CHIP_FAMILY_STM32F4
-		/* select page to erase */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) |
-			(sector << STM32_FLASH_CR_SNB_OFFSET);
-#else
-		/* select page to erase */
-		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
-#endif
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR |= FLASH_CR_STRT;
-
-		deadline.val = get_time().val + timeout_us;
-		/* Wait for erase to complete */
-		watchdog_reload();
-		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			usleep(timeout_us/100);
-		}
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-next_sector:
-		size -= sector_size;
-		offset += sector_size;
-#ifdef CHIP_FAMILY_STM32F4
-		sector++;
-#endif
-	}
-
-exit_er:
-	/* reset SER/PER bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PER;
-
-	lock();
-
-	return res;
-}
-
-#ifdef CHIP_FAMILY_STM32F4
-static int flash_physical_get_protect_at_boot(int block)
-{
-	/* 0: Write protection active on sector i. */
-	return !(STM32_OPTB_WP & STM32_OPTB_nWRP(block));
-}
-
-static int flash_physical_protect_at_boot_update_rdp_pstate(uint32_t new_flags)
-{
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-	int rv = EC_SUCCESS;
-
-	bool rdp_enable = (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) != 0;
-
-	/*
-	 * This is intentionally a one-way latch. Once we have enabled RDP
-	 * Level 1, we will only allow going back to Level 0 using the
-	 * bootloader (e.g., "stm32mon -U") since transitioning from Level 1 to
-	 * Level 0 triggers a mass erase.
-	 */
-	if (rdp_enable)
-		rv = flash_physical_set_rdp_level(FLASH_RDP_LEVEL_1);
-
-	return rv;
-#else
-	return EC_SUCCESS;
-#endif
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int block;
-	int original_val, val;
-
-	original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL;
-
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
-	     block++) {
-		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-		if (block >= WP_BANK_OFFSET &&
-		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-#ifdef CONFIG_FLASH_PROTECT_RW
-		else
-			protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-		if (protect)
-			val &= ~BIT(block);
-		else
-			val |= 1 << block;
-	}
-	if (original_val != val) {
-		int rv = write_optb(STM32_FLASH_nWRP_ALL,
-				    val << STM32_FLASH_nWRP_OFFSET);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return flash_physical_protect_at_boot_update_rdp_pstate(new_flags);
-}
-
-static void unprotect_all_blocks(void)
-{
-	write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL);
-}
-
-#else   /* CHIP_FAMILY_STM32F4 */
-static int flash_physical_get_protect_at_boot(int block)
-{
-	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8));
-	return (!(val & (1 << (block % 8)))) ? 1 : 0;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int block;
-	int i;
-	int original_val[4], val[4];
-
-	for (i = 0; i < 4; ++i)
-		original_val[i] = val[i] = read_optb(i * 2 + 8);
-
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
-	     block++) {
-		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-		int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
-
-		if (block >= WP_BANK_OFFSET &&
-		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-#ifdef CONFIG_ROLLBACK
-		else if (block >= ROLLBACK_BANK_OFFSET &&
-			 block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-#ifdef CONFIG_FLASH_PROTECT_RW
-		else
-			protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-		if (protect)
-			val[byte_off] = val[byte_off] & (~(1 << (block % 8)));
-		else
-			val[byte_off] = val[byte_off] | (1 << (block % 8));
-	}
-
-	for (i = 0; i < 4; ++i)
-		if (original_val[i] != val[i])
-			write_optb(i * 2 + 8, val[i]);
-
-#ifdef CONFIG_FLASH_READOUT_PROTECTION
-	/*
-	 * Set a permanent protection by increasing RDP to level 1,
-	 * trying to unprotected the flash will trigger a full erase.
-	 */
-	write_optb(0, 0x11);
-#endif
-
-	return EC_SUCCESS;
-}
-
-static void unprotect_all_blocks(void)
-{
-	int i;
-
-	for (i = 4; i < 8; ++i)
-		write_optb(i * 2, 0xff);
-}
-#endif
-
-/**
- * Check if write protect register state is inconsistent with RO_AT_BOOT and
- * ALL_AT_BOOT state.
- *
- * @return zero if consistent, non-zero if inconsistent.
- */
-static int registers_need_reset(void)
-{
-	uint32_t flags = crec_flash_get_protect();
-	int i;
-	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
-	int ro_wp_region_start = WP_BANK_OFFSET;
-	int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT;
-
-	for (i = ro_wp_region_start; i < ro_wp_region_end; i++)
-		if (flash_physical_get_protect_at_boot(i) != ro_at_boot)
-			return 1;
-	return 0;
-}
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-/**
- * Set Flash RDP (read protection) level.
- *
- * @note Does not take effect until reset.
- *
- * @param level new RDP (read protection) level to set
- * @return EC_SUCCESS on success, other on failure
- */
-int flash_physical_set_rdp_level(enum flash_rdp_level level)
-{
-	uint32_t reg_level;
-
-	switch (level) {
-	case FLASH_RDP_LEVEL_0:
-		/*
-		 * Asserting by default since we don't want to inadvertently
-		 * go from Level 1 to Level 0, which triggers a mass erase.
-		 * Remove assert if you want to use it.
-		 */
-		ASSERT(false);
-		reg_level = FLASH_OPTCR_RDP_LEVEL_0;
-		break;
-	case FLASH_RDP_LEVEL_1:
-		reg_level = FLASH_OPTCR_RDP_LEVEL_1;
-		break;
-	case FLASH_RDP_LEVEL_2:
-		/*
-		 * Asserting by default since it's permanent (there is no
-		 * way to reverse). Remove assert if you want to use it.
-		 */
-		ASSERT(false);
-		reg_level = FLASH_OPTCR_RDP_LEVEL_2;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return write_optb(FLASH_OPTCR_RDP_MASK, reg_level);
-}
-
-/**
- * @return On success, current flash read protection level.
- *         On failure, FLASH_RDP_LEVEL_INVALID
- */
-enum flash_rdp_level flash_physical_get_rdp_level(void)
-{
-	uint32_t level = (STM32_FLASH_OPTCR & FLASH_OPTCR_RDP_MASK);
-
-	switch (level) {
-	case FLASH_OPTCR_RDP_LEVEL_0:
-		return FLASH_RDP_LEVEL_0;
-	case FLASH_OPTCR_RDP_LEVEL_1:
-		return FLASH_RDP_LEVEL_1;
-	case FLASH_OPTCR_RDP_LEVEL_2:
-		return FLASH_RDP_LEVEL_2;
-	default:
-		return FLASH_RDP_LEVEL_INVALID;
-	}
-}
-#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
-
-/*****************************************************************************/
-/* High-level APIs */
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-
-#ifdef CHIP_FAMILY_STM32F4
-	unlock(NO_EXTRA_LOCK);
-	/* Set the proper write size */
-	STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) |
-		 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) <<
-		 STM32_FLASH_CR_PSIZE_OFFSET;
-	lock();
-#endif
-	if (crec_flash_physical_restore_state())
-		return EC_SUCCESS;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/* Enable physical protection for RO (0 means RO). */
-			crec_flash_physical_protect_now(0);
-		}
-
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_physical_protect_at_boot(
-				EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (registers_need_reset()) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 *
-			 * TODO(crosbug.com/p/23798): this seems really similar
-			 * to the check above.  One of them should be able to
-			 * go away.
-			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/*
-			 * Write protect pin unasserted but some section is
-			 * protected. Drop it and reboot.
-			 */
-			unprotect_all_blocks();
-			need_reset = 1;
-		}
-	}
-
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
-		/*
-		 * ALL_AT_BOOT and ALL_NOW should be both set or both unset
-		 * at boot. If they are not, it must be that the chip requires
-		 * OBL_LAUNCH to be set to reload option bytes. Let's reset
-		 * the system with OBL_LAUNCH set.
-		 * This assumes OBL_LAUNCH is used for hard reset in
-		 * chip/stm32/system.c.
-		 */
-		need_reset = 1;
-	}
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
-		/* RW_AT_BOOT and RW_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
-		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h
deleted file mode 100644
index cbbe6ec86f..0000000000
--- a/chip/stm32/flash-f.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_STM32_FLASH_F_H
-#define __CROS_EC_STM32_FLASH_F_H
-
-#include <stdbool.h>
-
-enum flash_rdp_level {
-	FLASH_RDP_LEVEL_INVALID = -1,	/**< Error occurred. */
-	FLASH_RDP_LEVEL_0,		/**< No read protection. */
-	FLASH_RDP_LEVEL_1,		/**< Reading flash is disabled while in
-					 *   bootloader mode or JTAG attached.
-					 *   Changing to Level 0 from this level
-					 *   triggers mass erase.
-					 */
-	FLASH_RDP_LEVEL_2,		/**< Same as Level 1, but is permanent
-					 *   and can never be disabled.
-					 */
-};
-
-bool is_flash_rdp_enabled(void);
-
-#endif /* __CROS_EC_STM32_FLASH_F_H */
diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h
deleted file mode 100644
index b0a46667a1..0000000000
--- a/chip/stm32/flash-regs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_STM32_FLASH_REGS_H
-#define __CROS_EC_STM32_FLASH_REGS_H
-
-#include <stdbool.h>
-
-/**
- * Unlock the flash control register using the unlock sequence.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.2  FLASH key register for bank 1" in RM0433.
- */
-void unlock_flash_control_register(void);
-
-/**
- * Unlock the flash option bytes register using the unlock sequence.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.3 FLASH option key register" in RM0433.
- */
-void unlock_flash_option_bytes(void);
-
-/**
- * Lock the flash control register.
- *
- * If the flash control register has been disabled since the last reset when
- * this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- */
-void lock_flash_control_register(void);
-
-/**
- * Lock the flash option bytes register.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- */
-void lock_flash_option_bytes(void);
-
-/**
- * Disable the flash option bytes register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash option
- * bytes register will generate a bus fault until the next reset.
- *
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- */
-void disable_flash_option_bytes(void);
-
-/**
- * Disable the flash control register.
- *
- * This function expects that bus faults have not already been ignored when
- * called.
- *
- * Once this function is called any attempt at accessing the flash control
- * register will generate a bus fault until the next reset.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- */
-void disable_flash_control_register(void);
-
-/**
- * Check if the flash option bytes are locked.
- *
- * If the flash option bytes register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
-
- * See "3.6.2 Programming user option bytes" in RM0402.
- * See "4.9.7 FLASH option control register" in RM0433.
- *
- * @return true if option bytes are locked, false otherwise
- */
-bool flash_option_bytes_locked(void);
-
-/**
- * Check if the flash control register is locked.
- *
- * If the flash control register has been disabled since the last reset
- * when this function is called, a bus fault will be generated.
- *
- * See "3.5.1 Unlocking the Flash control register" in RM0402.
- * See "4.9.4 Flash control register for bank 1" in RM0433.
- *
- * @return true if register is locked, false otherwise
- */
-bool flash_control_register_locked(void);
-
-#endif /* __CROS_EC_STM32_FLASH_REGS_H */
diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c
deleted file mode 100644
index f790a657c8..0000000000
--- a/chip/stm32/flash-stm32f0.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "common.h"
-#include "flash.h"
-#include "registers.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_get_protect(int block)
-{
-	return !(STM32_FLASH_WRPR & BIT(block));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as get_protect_flags
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-	uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01);
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-	uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23);
-#endif
-
-	/*
-	 * We only need to return detailed flags if we want to protect RW or
-	 * ROLLBACK independently (EC_FLASH_PROTECT_RO_AT_BOOT should be set
-	 * by pstate logic).
-	 */
-#if defined(CONFIG_FLASH_PROTECT_RW) || defined(CONFIG_ROLLBACK)
-	/* Flags that must be set for each region. */
-	const int mask_flags[] = {
-		[FLASH_REGION_RW] = EC_FLASH_PROTECT_RW_AT_BOOT,
-		[FLASH_REGION_RO] = EC_FLASH_PROTECT_RO_AT_BOOT,
-#ifdef CONFIG_ROLLBACK
-		[FLASH_REGION_ROLLBACK] = EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
-#endif
-	};
-
-	/*
-	 * Sets up required mask for wrp01/23 registers: for protection to be
-	 * set, values set in the mask must be zeros, values in the mask << 8
-	 * must be ones.
-	 *
-	 * Note that these masks are actually static, and could be precomputed
-	 * at build time to save flash space.
-	 */
-	uint32_t wrp_mask[FLASH_REGION_COUNT][2];
-	int i;
-	int shift = 0;
-	int reg = 0;
-
-	memset(wrp_mask, 0, sizeof(wrp_mask));
-
-	/* Scan flash protection */
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
-		/* Default: RW. */
-		int region = FLASH_REGION_RW;
-
-		if (i >= WP_BANK_OFFSET &&
-		    i < WP_BANK_OFFSET + WP_BANK_COUNT)
-			region = FLASH_REGION_RO;
-#ifdef CONFIG_ROLLBACK
-		if (i >= ROLLBACK_BANK_OFFSET &&
-		    i < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			region = FLASH_REGION_ROLLBACK;
-#endif
-
-		switch (i) {
-		case 8:
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		case 24:
-#endif
-			shift += 8;
-			break;
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		case 16:
-			reg = 1;
-			shift = 0;
-			break;
-#endif
-		}
-
-		wrp_mask[region][reg] |= 1 << shift;
-		shift++;
-	}
-
-	for (i = 0; i < FLASH_REGION_COUNT; i++) {
-		if (!(wrp01 & wrp_mask[i][0]) &&
-			(wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-			if (!(wrp23 & wrp_mask[i][1]) &&
-			     (wrp23 & wrp_mask[i][1] << 8) ==
-							 (wrp_mask[i][1] << 8))
-#endif
-				flags |= mask_flags[i];
-	}
-#endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */
-
-	if (wrp01 == 0xff00ff00)
-#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
-		if (wrp23 == 0xff00ff00)
-#endif
-			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	return EC_ERROR_INVAL;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	/* Nothing to restore */
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-#ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
-#endif
-#ifdef CONFIG_ROLLBACK
-	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-	       EC_FLASH_PROTECT_ROLLBACK_NOW |
-#endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
-	 * be cleared.
-	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-
-	return ret;
-}
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c
deleted file mode 100644
index 138e690fcc..0000000000
--- a/chip/stm32/flash-stm32f3.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for stm32f3 and stm32f4 */
-
-#include <stdbool.h>
-#include "common.h"
-#include "flash.h"
-#include "flash-f.h"
-#include "flash-regs.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "panic.h"
-
-/*****************************************************************************/
-/* Physical layer APIs */
-#ifdef CHIP_VARIANT_STM32F76X
-/*
- * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB
- */
-struct ec_flash_bank const flash_bank_array[] = {
-	{
-		.count = 4,
-		.size_exp = __fls(SIZE_32KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_32KB),
-		.protect_size_exp = __fls(SIZE_32KB),
-	},
-	{
-		.count = 1,
-		.size_exp = __fls(SIZE_128KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_128KB),
-		.protect_size_exp = __fls(SIZE_128KB),
-	},
-	{
-		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB,
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.size_exp = __fls(SIZE_256KB),
-		.erase_size_exp = __fls(SIZE_256KB),
-		.protect_size_exp = __fls(SIZE_256KB),
-	},
-};
-#elif defined(CHIP_FAMILY_STM32F4)
-/*
- * STM32F412xE has 512 KB flash
- *   8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB
- *
- * STM32F412xG has 1 MB flash
- *   12 "erase" sectors (1024 KB) :
- *           16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB
- *
- * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
- */
-struct ec_flash_bank const flash_bank_array[] = {
-	{
-		.count = 4,
-		.size_exp = __fls(SIZE_16KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_16KB),
-		.protect_size_exp = __fls(SIZE_16KB),
-	},
-	{
-		.count = 1,
-		.size_exp = __fls(SIZE_64KB),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(SIZE_64KB),
-		.protect_size_exp = __fls(SIZE_64KB),
-	},
-	{
-		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB,
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.size_exp = __fls(SIZE_128KB),
-		.erase_size_exp = __fls(SIZE_128KB),
-		.protect_size_exp = __fls(SIZE_128KB),
-	},
-};
-#endif
-
-/* Flag indicating whether we have locked down entire flash */
-static int entire_flash_locked;
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-/* The previous write protect state before sys jump */
-struct flash_wp_state {
-	int entire_flash_locked;
-};
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_get_protect(int block)
-{
-	return (entire_flash_locked ||
-#if defined(CHIP_FAMILY_STM32F3)
-		!(STM32_FLASH_WRPR & BIT(block))
-#elif defined(CHIP_FAMILY_STM32F4)
-		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
-#endif
-	       );
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/* Read all-protected state from our shadow copy */
-	if (entire_flash_locked)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-	if (is_flash_rdp_enabled())
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-#endif
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		disable_flash_control_register();
-		entire_flash_locked = 1;
-
-		return EC_SUCCESS;
-	}
-
-	disable_flash_option_bytes();
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev))
-			entire_flash_locked = prev->entire_flash_locked;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	struct flash_wp_state state;
-
-	state.entire_flash_locked = entire_flash_locked;
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
deleted file mode 120000
index 6ff8130e17..0000000000
--- a/chip/stm32/flash-stm32f4.c
+++ /dev/null
@@ -1 +0,0 @@
-flash-stm32f3.c
\ No newline at end of file
diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c
deleted file mode 100644
index f792da6e3c..0000000000
--- a/chip/stm32/flash-stm32g4-l4.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Flash memory module for STM32L4 family */
-
-#include "common.h"
-#include "clock.h"
-#include "flash.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_TIMEOUT_US 48000
-
-/*
- * Cros-Ec common flash APIs use the term 'bank' equivalent to how 'page' is
- * used in the STM32 TRMs. Redifining macros here in terms of pages in order to
- * match STM32 documentation for write protect computations in this file.
- *
- * These macros are from the common flash API and mean the following:
- * WP_BANK_OFFSET         -> index of first RO page
- * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes
- */
-#define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE
-#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE)
-#define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET
-#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \
-				 + FLASH_RO_FIRST_PAGE_IDX - 1)
-#define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1)
-#define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1)
-
-
-#define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT
-#define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET
-#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\
-					FLASH_PAGE_ROLLBACK_COUNT -1)
-
-#ifdef STM32_FLASH_DBANK_MODE
-#define FLASH_WRP_MASK              (FLASH_PAGE_MAX_COUNT - 1)
-#else
-#ifdef CHIP_FAMILY_STM32L4
-#define FLASH_WRP_MASK              0xFF
-#else
-#define FLASH_WRP_MASK              ((FLASH_PAGE_MAX_COUNT) / 2 - 1)
-#endif
-#endif /* CONFIG_FLASH_DBANK_MODE */
-#define FLASH_WRP_START(val)        ((val) & FLASH_WRP_MASK)
-#define FLASH_WRP_END(val)          (((val) >> 16) & FLASH_WRP_MASK)
-#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \
-				       (((end) & FLASH_WRP_MASK) << 16))
-#define FLASH_WRP_RANGE_DISABLED    FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
-#define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK)
-
-enum wrp_region {
-	WRP_RO,
-	WRP_RW,
-};
-
-struct wrp_info {
-	int enable;
-	int start;
-	int end;
-};
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int wait_while_busy(void)
-{
-	int timeout = calculate_flash_timeout();
-
-	while (STM32_FLASH_SR & FLASH_SR_BUSY && timeout-- > 0)
-		;
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* unlock CR if needed */
-	if (STM32_FLASH_CR & FLASH_CR_LOCK) {
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-	}
-	/* unlock option memory if required */
-	if ((locks & FLASH_CR_OPTLOCK) &&
-	    (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-	}
-
-	/* Re-enable bus fault handler */
-	ignore_bus_fault(0);
-
-	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN
-							  : EC_SUCCESS;
-}
-
-static void lock(void)
-{
-	STM32_FLASH_CR |= FLASH_CR_LOCK;
-}
-
-static void ob_lock(void)
-{
-	STM32_FLASH_CR |= FLASH_CR_OPTLOCK;
-}
-
-/*
- * Option byte organization
- *
- *                [63:56][55:48][47:40][39:32]   [31:24][23:16][15: 8][ 7: 0]
- * +--------------+-------------------+------+   +-------------------+------+
- * | 0x1FFF7800   |         nUSER     | nRDP |   |       USER        |  RDP |
- * +--------------+------------+------+------+   +------------+------+------+
- * | 0x1FFF7808   |            | nPCROP1_STRT|   |            | PCROP1_STRT |
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7810   |            | nPCROP1_END |   |            | PCROP1_END  |
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7818   |     |nWRP1A|      |nWRP1A|   |     | WRP1A|      | WRP1A|
- * |              |     |_END  |      |_STRT |   |     | _END |      | _STRT|
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7820   |     |nWRP1B|      |nWRP1B|   |     | WRP1B|      | WRP1B|
- * |              |     |_END  |      |_STRT |   |     | _END |      | _STRT|
- * +--------------+------------+-------------+   +------------+-------------+
- * | 0x1FFF7828   |     |nBOOT |      |nSEC_ |   |     | BOOT |      | SEC_ |
- * |              |     |LOCK  |      |SIZE1 |   |     | _LOCK|      | SIZE1|
- * +--------------+------------+-------------+   +------------+-------------+
- *
- * Note that the variable with n prefix means the complement.
- */
-static int unlock_optb(void)
-{
-	int rv;
-
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	rv = unlock(FLASH_CR_OPTLOCK);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-static int commit_optb(void)
-{
-	int rv;
-
-	/*
-	 * Wait for last operation.
-	 */
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	STM32_FLASH_CR |= FLASH_CR_OPTSTRT;
-
-	rv = wait_while_busy();
-	if (rv)
-		return rv;
-
-	ob_lock();
-	lock();
-
-	return EC_SUCCESS;
-}
-
-/*
- * There are a minimum of 2 WRP regions that can be set. The STM32G4
- * family has both category 2, and category 3 devices. Category 2
- * devices have only 2 WRP regions, but category 3 devices have 4 WRP
- * regions that can be configured. Category 3 devices also support dual
- * flash banks, and this mode is the default setting. When DB mode is enabled,
- * then each WRP register can only protect up to 64 2kB pages. This means that
- * one WRP register is needed per bank.
- *
- *   1. WRP1A -> used always for RO
- *   2. WRP1B -> used always for RW
- *   3. WRP2A -> may be used for RW if dual-bank (DB) mode is enabled
- *   4. WRP2B -> currently never used
- *
- * WRP areas are specified in terms of page indices with a start index
- * and an end index. start == end means a single page is protected.
- *
- *   WRPnx_start = WRPnx_end  --> WRPnx_start page is protected
- *   WRPnx_start > WRPnx_end  --> No WRP area is specified
- *   WRPnx_start < WRPnx_end  --> Pages WRPnx_start to WRPnx_end
- */
-static void optb_get_wrp(enum wrp_region region, struct wrp_info *wrp)
-{
-#ifdef STM32_FLASH_DBANK_MODE
-	int start;
-	int end;
-#endif
-	/* Assume WRP regions are not configured */
-	wrp->start = FLASH_WRP_MASK;
-	wrp->end = 0;
-	wrp->enable = 0;
-
-	if (region == WRP_RO) {
-		/*
-		 * RO write protect is fully described by WRP1AR. Get the
-		 * start/end indices. If end >= start, then RO write protect is
-		 * enabled.
-		 */
-		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1AR);
-		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1AR);
-		wrp->enable = wrp->end >= wrp->start;
-	} else if (region == WRP_RW) {
-		/*
-		 * RW write always uses WRP1BR. If dual-bank mode is being used,
-		 * then WRP2AR must also be check to determine the full range of
-		 * flash page indices being protected.
-		 */
-		wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1BR);
-		wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1BR);
-		wrp->enable = wrp->end >= wrp->start;
-#ifdef STM32_FLASH_DBANK_MODE
-		start = FLASH_WRP_START(STM32_FLASH_WRP2AR);
-		end = FLASH_WRP_END(STM32_FLASH_WRP2AR);
-		/*
-		 * If WRP2AR protection is enabled, then need to adjust either
-		 * the start, end, or both indices.
-		 */
-		if (end >= start) {
-			if (wrp->enable) {
-				/* WRP1BR is active, only need to adjust end */
-				wrp->end += end;
-			} else {
-				/*
-				 * WRP1BR is not active, so RW protection, if
-				 * enabled, is fully controlled by WRP2AR.
-				 */
-				wrp->start = start;
-				wrp->end = end;
-				wrp->enable = 1;
-			}
-		}
-#endif
-	}
-}
-
-static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp)
-{
-	int start = wrp->start;
-	int end = wrp->end;
-
-	if (!wrp->enable) {
-		/*
-		 * If enable is not set, then ignore the passed in start/end
-		 * values and set start/end to the default not protected range
-		 * which satisfies start > end
-		 */
-		start = FLASH_WRP_MASK;
-		end = 0;
-	}
-
-	if (region == WRP_RO) {
-		/* For RO can always use start/end directly */
-		STM32_FLASH_WRP1AR = FLASH_WRP_RANGE(start, end);
-	} else if (region == WRP_RW) {
-#ifdef STM32_FLASH_DBANK_MODE
-		/*
-		 * In the dual-bank flash case (STM32G4 Category 3 devices with
-		 * DB bit set), RW write protect can use both WRP1BR and WRP2AR
-		 * registers in order to span the full flash memory range.
-		 */
-		if (wrp->enable) {
-			int rw_end;
-
-			/*
-			 * If the 1st RW flash page is in the 1st half of
-			 * memory, then at least one block will be protected by
-			 * WRP1BR. If the end flash page is in the 2nd half of
-			 * memory, then cap the end for WRP1BR to its max
-			 * value. Otherwise, can use end passed in directly.
-			 */
-			if (start <= FLASH_WRP_MASK) {
-				rw_end = end > FLASH_WRP_MASK ?
-					FLASH_WRP_MASK : end;
-				STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start,
-								     rw_end);
-			}
-			/*
-			 * If the last RW flash page is in the 2nd half of
-			 * memory, then at least one block will be protected by
-			 * WRP2AR. If the start flash page is in the 2nd half of
-			 * memory, can use start directly. Otherwise, start
-			 * needs to be set to 0 here.
-			 */
-			if (end > FLASH_WRP_MASK) {
-				rw_end = end & FLASH_WRP_MASK;
-				STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(0, rw_end);
-			}
-		} else {
-			/*
-			 * RW write protect is being disabled. Set both WRP1BR
-			 * and WRP2AR to default start > end not protected
-			 * state.
-			 */
-			STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
-			STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(start, end);
-		}
-#else
-		/* Single bank case, WRP1BR can cover the full memory range */
-		STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end);
-#endif
-	}
-}
-
-static void unprotect_all_blocks(void)
-{
-	struct wrp_info wrp;
-
-	/* Set info values to unprotected */
-	wrp.start = FLASH_WRP_MASK;
-	wrp.end = 0;
-	wrp.enable = 0;
-
-	unlock_optb();
-	/* Disable RO WRP */
-	optb_set_wrp(WRP_RO, &wrp);
-	/* Disable RW WRP */
-	optb_set_wrp(WRP_RW, &wrp);
-	commit_optb();
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	wrp_ro.start = FLASH_WRP_MASK;
-	wrp_ro.end = 0;
-	wrp_ro.enable = 0;
-
-	wrp_rw.start = FLASH_WRP_MASK;
-	wrp_rw.end = 0;
-	wrp_rw.enable = 0;
-
-	/*
-	 * Default operation for this function is to disable both RO and RW
-	 * write protection in the option bytes. Based on new_flags either RO or
-	 * RW or both regions write protect may be set.
-	 */
-	if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_RO_AT_BOOT)) {
-		wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX;
-		wrp_ro.end = FLASH_RO_LAST_PAGE_IDX;
-		wrp_ro.enable = 1;
-	}
-
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
-		wrp_rw.start = FLASH_RW_FIRST_PAGE_IDX;
-		wrp_rw.end = FLASH_RW_LAST_PAGE_IDX;
-		wrp_rw.enable = 1;
-	} else {
-		/*
-		 * Start index will be 1st index following RO region index. The
-		 * end index is initialized as 'no protect' value. Only if end
-		 * gets changed based on either rollback or RW protection will
-		 * the 2nd memory protection area get written in option bytes.
-		 */
-		int start = FLASH_RW_FIRST_PAGE_IDX;
-		int end = 0;
-#ifdef CONFIG_ROLLBACK
-		if (new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) {
-			start = FLASH_PAGE_ROLLBACK_FIRST_IDX;
-			end = FLASH_PAGE_ROLLBACK_LAST_IDX;
-		} else {
-			start = FLASH_PAGE_ROLLBACK_LAST_IDX;
-		}
-#endif /* !CONFIG_ROLLBACK */
-#ifdef CONFIG_FLASH_PROTECT_RW
-		if (new_flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-			end = FLASH_RW_LAST_PAGE_IDX;
-#endif /* CONFIG_FLASH_PROTECT_RW */
-
-		if (end) {
-			wrp_rw.start = start;
-			wrp_rw.end = end;
-			wrp_rw.enable = 1;
-		}
-	}
-
-	unlock_optb();
-#ifdef CONFIG_FLASH_READOUT_PROTECTION
-	/*
-	 * Set a permanent protection by increasing RDP to level 1,
-	 * trying to unprotected the flash will trigger a full erase.
-	 */
-	STM32_FLASH_OPTR = (STM32_FLASH_OPTR & ~0xff) | 0x11;
-#endif
-	optb_set_wrp(WRP_RO, &wrp_ro);
-	optb_set_wrp(WRP_RW, &wrp_rw);
-	commit_optb();
-
-	return EC_SUCCESS;
-}
-
-/**
- * Check if write protect register state is inconsistent with RO_AT_BOOT and
- * ALL_AT_BOOT state.
- *
- * @return zero if consistent, non-zero if inconsistent.
- */
-static int registers_need_reset(void)
-{
-	uint32_t flags = crec_flash_get_protect();
-	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
-	/* The RO region is write-protected by the WRP1AR range. */
-	uint32_t wrp1ar = STM32_OPTB_WRP1AR;
-	uint32_t ro_range = ro_at_boot ?
-		FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-				  FLASH_RO_LAST_PAGE_IDX)
-		: FLASH_WRP_RANGE_DISABLED;
-
-	return ro_range != (wrp1ar & FLASH_WRP1X_MASK);
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int res = EC_SUCCESS;
-	int timeout = calculate_flash_timeout();
-	int i;
-	int unaligned = (uint32_t)data & (STM32_FLASH_MIN_WRITE_SIZE - 1);
-	uint32_t *data32 = (void *)data;
-
-	/* Check Flash offset */
-	if (offset % STM32_FLASH_MIN_WRITE_SIZE)
-		return EC_ERROR_MEMORY_ALLOCATION;
-
-	if (unlock(FLASH_CR_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ERR_MASK;
-
-	/* set PG bit */
-	STM32_FLASH_CR |= FLASH_CR_PG;
-
-	for (; size > 0; size -= STM32_FLASH_MIN_WRITE_SIZE) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing.
-		 */
-		watchdog_reload();
-
-		/* wait to be ready  */
-		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
-		     i++)
-			;
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/* write the 2 words */
-		if (unaligned) {
-			*address++ = (uint32_t)data[0] | (data[1] << 8)
-				   | (data[2] << 16) | (data[3] << 24);
-			*address++ = (uint32_t)data[4] | (data[5] << 8)
-				   | (data[6] << 16) | (data[7] << 24);
-			data += STM32_FLASH_MIN_WRITE_SIZE;
-		} else {
-			*address++ = *data32++;
-			*address++ = *data32++;
-		}
-
-		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
-		     i++)
-			;
-
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error.
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR &= ~FLASH_CR_PG;
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int pg;
-	int last;
-
-	if (unlock(FLASH_CR_LOCK) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = FLASH_SR_ERR_MASK;
-
-	last = (offset + size) / CONFIG_FLASH_ERASE_SIZE;
-	for (pg = offset / CONFIG_FLASH_ERASE_SIZE; pg < last; pg++) {
-		timestamp_t deadline;
-
-		/* select page to erase and PER bit */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK)
-				| FLASH_CR_PER | FLASH_CR_PNB(pg);
-
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR |= FLASH_CR_STRT;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during a
-		 * long erase operation.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_TIMEOUT_US;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			usleep(300);
-		}
-		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* reset PER bit */
-	STM32_FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PNB_MASK);
-
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	optb_get_wrp(WRP_RO, &wrp_ro);
-	optb_get_wrp(WRP_RW, &wrp_rw);
-
-	return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) ||
-		((block >= wrp_rw.start) && (block <= wrp_rw.end));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as get_protect_flags
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-	struct wrp_info wrp_ro;
-	struct wrp_info wrp_rw;
-
-	optb_get_wrp(WRP_RO, &wrp_ro);
-	optb_get_wrp(WRP_RW, &wrp_rw);
-
-	/* Check if RO is fully protected */
-	if (wrp_ro.start == FLASH_RO_FIRST_PAGE_IDX &&
-	    wrp_ro.end == FLASH_RO_LAST_PAGE_IDX)
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	if (wrp_rw.enable) {
-
-#ifdef CONFIG_ROLLBACK
-		if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX &&
-		    wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX)
-			flags |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif /* CONFIG_ROLLBACK */
-#ifdef CONFIG_FLASH_PROTECT_RW
-		if (wrp_rw.end == PHYSICAL_BANKS)
-			flags |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif /* CONFIG_FLASH_PROTECT_RW */
-		if (wrp_rw.end == PHYSICAL_BANKS &&
-		    wrp_rw.start == WP_BANK_OFFSET + WP_BANK_COUNT &&
-		    flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-			flags |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-	}
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	return EC_ERROR_INVAL;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-#ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
-#endif
-#ifdef CONFIG_ROLLBACK
-	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-	       EC_FLASH_PROTECT_ROLLBACK_NOW |
-#endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
-	 * be cleared.
-	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-
-	return ret;
-}
-
-int crec_flash_physical_force_reload(void)
-{
-	int rv = unlock(FLASH_CR_OPTLOCK);
-
-	if (rv)
-		return rv;
-
-	/* Force a reboot; this should never return. */
-	STM32_FLASH_CR = FLASH_CR_OBL_LAUNCH;
-	while (1)
-		;
-
-	return EC_ERROR_UNKNOWN;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_physical_protect_at_boot(
-				EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (registers_need_reset()) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 *
-			 * TODO(crosbug.com/p/23798): this seems really similar
-			 * to the check above.  One of them should be able to
-			 * go away.
-			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else {
-		if (prot_flags & EC_FLASH_PROTECT_RO_NOW) {
-			/*
-			 * Write protect pin unasserted but some section is
-			 * protected. Drop it and reboot.
-			 */
-			unprotect_all_blocks();
-			need_reset = 1;
-		}
-	}
-
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
-		/*
-		 * ALL_AT_BOOT and ALL_NOW should be both set or both unset
-		 * at boot. If they are not, it must be that the chip requires
-		 * OBL_LAUNCH to be set to reload option bytes. Let's reset
-		 * the system with OBL_LAUNCH set.
-		 * This assumes OBL_LAUNCH is used for hard reset in
-		 * chip/stm32/system.c.
-		 */
-		need_reset = 1;
-	}
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
-		/* RW_AT_BOOT and RW_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if ((crec_flash_physical_get_valid_flags() &
-	     EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
-	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
-	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
-		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
-		need_reset = 1;
-	}
-#endif
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c
deleted file mode 100644
index 087ddbf062..0000000000
--- a/chip/stm32/flash-stm32h7.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Flash memory module for STM32H7 family */
-
-#include "common.h"
-#include "clock.h"
-#include "cpu.h"
-#include "flash.h"
-#include "flash-regs.h"
-#include "hooks.h"
-#include "registers.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status
- */
-#define CYCLE_PER_FLASH_LOOP 2
-
-/* Flash 256-bit word programming timeout. */
-#define FLASH_TIMEOUT_US 600
-
-/*
- * Flash 128-KB block erase timeout.
- * Datasheet says maximum is about 4 seconds in x8.
- * Real delay seems to be: < 1 second in x64, < 2 seconds in x8.
- */
-#define FLASH_ERASE_TIMEOUT_US (4200 * MSEC)
-
-/*
- * Option bytes programming timeout.
- * No specification, real delay seems to be around 300ms.
- */
-#define FLASH_OPT_PRG_TIMEOUT_US (1000 * MSEC)
-
-/*
- * All variants have 2 banks (as in parallel hardware / controllers)
- * not what is called 'bank' in the common code (ie Write-Protect sectors)
- * both have the same number of 128KB blocks.
- */
-#define HWBANK_SIZE  (CONFIG_FLASH_SIZE_BYTES / 2)
-#define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE)
-#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1)
-
-/*
- * We can tune the power consumption vs erase/write speed
- * by default, go fast (and consume current)
- */
-#define DEFAULT_PSIZE FLASH_CR_PSIZE_DWORD
-
-/* Can no longer write/erase flash until next reboot */
-static int access_disabled;
-/* Can no longer modify write-protection in option bytes until next reboot */
-static int option_disabled;
-/* Is physical flash stuck protected? (avoid reboot loop) */
-static int stuck_locked;
-
-#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
-#define FLASH_HOOK_VERSION 1
-
-/* The previous write protect state before sys jump */
-struct flash_wp_state {
-	int access_disabled;
-	int option_disabled;
-	int stuck_locked;
-};
-
-static inline int calculate_flash_timeout(void)
-{
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-}
-
-static int unlock(int bank)
-{
-	/* unlock CR only if needed */
-	if (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) {
-		/*
-		 * We may have already locked the flash module and get a bus
-		 * fault in the attempt to unlock. Need to disable bus fault
-		 * handler now.
-		 */
-		ignore_bus_fault(1);
-
-		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY2;
-		ignore_bus_fault(0);
-	}
-
-	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN
-						      : EC_SUCCESS;
-}
-
-static void lock(int bank)
-{
-	STM32_FLASH_CR(bank) |= FLASH_CR_LOCK;
-}
-
-static int unlock_optb(void)
-{
-	if (option_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (unlock(0))
-		return EC_ERROR_UNKNOWN;
-
-	if (flash_option_bytes_locked()) {
-		/*
-		 * We may have already locked the flash module and get a bus
-		 * fault in the attempt to unlock. Need to disable bus fault
-		 * handler now.
-		 */
-		ignore_bus_fault(1);
-
-		unlock_flash_option_bytes();
-		ignore_bus_fault(0);
-	}
-
-	return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN
-					   : EC_SUCCESS;
-}
-
-static int commit_optb(void)
-{
-	/* might use this before timer_init, cannot use get_time/usleep */
-	int timeout = (FLASH_OPT_PRG_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
-
-	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART;
-
-	while (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_BUSY && timeout-- > 0)
-		;
-
-	lock_flash_option_bytes();
-	lock(0);
-
-	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-}
-
-static void protect_blocks(uint32_t blocks)
-{
-	if (unlock_optb())
-		return;
-	STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK);
-	STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK)
-				& BLOCKS_HWBANK_MASK);
-	commit_optb();
-}
-
-
-/*
- * Helper function definitions for consistency with F4 to enable flash
- * physical unitesting
- */
-void unlock_flash_control_register(void)
-{
-	unlock(0);
-	unlock(1);
-}
-
-void unlock_flash_option_bytes(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 *
-	 * Consecutively program values. Ref: RM0433:4.9.2
-	 */
-	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1;
-	STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2;
-}
-
-void disable_flash_option_bytes(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 *
-	 * Writing anything other than the pre-defined keys to the option key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_OPTKEYR(0) = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void disable_flash_control_register(void)
-{
-	ignore_bus_fault(1);
-	/*
-	 * Writing anything other than the pre-defined keys to a key
-	 * register results in a bus fault and the register being locked until
-	 * reboot (even with a further correct key write).
-	 */
-	STM32_FLASH_KEYR(0) = 0xffffffff;
-	STM32_FLASH_KEYR(1) = 0xffffffff;
-	ignore_bus_fault(0);
-}
-
-void lock_flash_control_register(void)
-{
-	lock(0);
-	lock(1);
-}
-
-void lock_flash_option_bytes(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 */
-	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK;
-}
-
-bool flash_option_bytes_locked(void)
-{
-	/*
-	 * Always use bank 0 flash controller as there is only one option bytes
-	 * set for both banks. See http://b/181130245
-	 */
-	return  !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK);
-}
-
-bool flash_control_register_locked(void)
-{
-	return !!(STM32_FLASH_CR(0) & FLASH_CR_LOCK) &&
-	       !!(STM32_FLASH_CR(1) & FLASH_CR_LOCK);
-}
-
-/*
- * If RDP as PSTATE option is defined, use that as 'Write Protect enabled' flag:
- * it makes no sense to be able to unlock RO, as that'd allow flashing
- * arbitrary RO that could read back all flash.
- *
- * crbug.com/888109: Do not copy this code over to other STM32 chips without
- * understanding the full implications.
- *
- * If RDP is not defined, use the option bytes RSS1 bit.
- * TODO(crbug.com/888104): Validate that using RSS1 for this purpose is safe.
- */
-#ifndef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-#error "crbug.com/888104: Using RSS1 for write protect PSTATE may not be safe."
-#endif
-static int is_wp_enabled(void)
-{
-#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK)
-		!= FLASH_OPTSR_RDP_LEVEL_0;
-#else
-	return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1);
-#endif
-}
-
-static int set_wp(int enabled)
-{
-	int rv;
-
-	rv = unlock_optb();
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	if (enabled) {
-		/* Enable RDP level 1. */
-		STM32_FLASH_OPTSR_PRG(0) =
-			(STM32_FLASH_OPTSR_PRG(0) & ~FLASH_OPTSR_RDP_MASK) |
-			FLASH_OPTSR_RDP_LEVEL_1;
-	}
-#else
-	if (enabled)
-		STM32_FLASH_OPTSR_PRG(0) |= FLASH_OPTSR_RSS1;
-	else
-		STM32_FLASH_OPTSR_PRG(0) &= ~FLASH_OPTSR_RSS1;
-#endif
-
-	return commit_optb();
-}
-
-/*****************************************************************************/
-/* Physical layer APIs */
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int res = EC_SUCCESS;
-	int bank = offset / HWBANK_SIZE;
-	uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int timeout = calculate_flash_timeout();
-	int i;
-	int unaligned = (uint32_t)data & (CONFIG_FLASH_WRITE_SIZE - 1);
-	uint32_t *data32 = (void *)data;
-
-	if (access_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* work on a single hardware bank at a time */
-	if ((offset + size - 1) / HWBANK_SIZE != bank)
-		return EC_ERROR_INVAL;
-
-	if (unlock(bank) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
-
-	/* select write parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
-
-	/* set PG bit */
-	STM32_FLASH_CR(bank) |= FLASH_CR_PG;
-
-	for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing.
-		 */
-		watchdog_reload();
-
-		/* write a 256-bit flash word */
-		if (unaligned) {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++,
-								     data += 4)
-				*address++ = (uint32_t)data[0] | (data[1] << 8)
-					   | (data[2] << 16) | (data[3] << 24);
-		} else {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++)
-				*address++ = *data32++;
-		}
-
-		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR(bank) &
-		     (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++)
-			;
-
-		if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Disable PG bit */
-	STM32_FLASH_CR(bank) &= ~FLASH_CR_PG;
-
-	lock(bank);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/* Invalidate D-cache, to make sure we do not read back stale data. */
-	cpu_clean_invalidate_dcache();
-#endif
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int res = EC_SUCCESS;
-	int bank = offset / HWBANK_SIZE;
-	int last = (offset + size) / CONFIG_FLASH_ERASE_SIZE;
-	int sect;
-
-	if (access_disabled)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* work on a single hardware bank at a time */
-	if ((offset + size - 1) / HWBANK_SIZE != bank)
-		return EC_ERROR_INVAL;
-
-	if (unlock(bank) != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear previous error status */
-	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
-
-	/* select erase parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
-
-	for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) {
-		timestamp_t deadline;
-
-		/* select page to erase and PER bit */
-		STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank)
-					& ~FLASH_CR_SNB_MASK)
-				| FLASH_CR_SER | FLASH_CR_SNB(sect);
-
-		/* set STRT bit : start erase */
-		STM32_FLASH_CR(bank) |= FLASH_CR_STRT;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during a
-		 * long erase operation.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_ERASE_TIMEOUT_US;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR(bank) & FLASH_SR_BUSY) &&
-		       (get_time().val < deadline.val)) {
-			/*
-			 * Interrupts may not be enabled, so we are using
-			 * udelay() instead of usleep() which can trigger
-			 * Forced Hard Fault (see b/180761547).
-			 */
-			udelay(5000);
-		}
-		if (STM32_FLASH_SR(bank) & FLASH_SR_BUSY) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions - erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* reset SER bit */
-	STM32_FLASH_CR(bank) &= ~(FLASH_CR_SER | FLASH_CR_SNB_MASK);
-
-	lock(bank);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/* Invalidate D-cache, to make sure we do not read back stale data. */
-	cpu_clean_invalidate_dcache();
-#endif
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	int bank = block / BLOCKS_PER_HWBANK;
-	int index = block % BLOCKS_PER_HWBANK;
-
-	return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index));
-}
-
-/*
- * Note: This does not need to update _NOW flags, as flash_get_protect
- * in common code already does so.
- */
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (access_disabled)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	if (is_wp_enabled())
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	return flags;
-}
-
-#define WP_RANGE(start, count) (((1 << (count)) - 1) << (start))
-#define RO_WP_RANGE WP_RANGE(WP_BANK_OFFSET, WP_BANK_COUNT)
-
-int crec_flash_physical_protect_now(int all)
-{
-	protect_blocks(RO_WP_RANGE);
-
-	/*
-	 * Lock the option bytes or the full access by writing a wrong
-	 * key to FLASH_*KEYR. This triggers a bus fault, so we need to
-	 * disable bus fault handler while doing this.
-	 *
-	 * This incorrect key fault causes the flash to become
-	 * permanently locked until reset, a correct keyring write
-	 * will not unlock it.
-	 */
-
-	if (all) {
-		/* cannot do any write/erase access until next reboot */
-		disable_flash_control_register();
-		access_disabled = 1;
-	}
-	/* cannot modify the WP bits in the option bytes until reboot */
-	disable_flash_option_bytes();
-	option_disabled = 1;
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	int new_wp_enable = !!(new_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	if (is_wp_enabled() != new_wp_enable)
-		return set_wp(new_wp_enable);
-
-	return EC_SUCCESS;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_physical_restore_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	int version, size;
-	const struct flash_wp_state *prev;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. We simply need to represent these
-         * irreversible flags to other components.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
-		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
-		if (prev && version == FLASH_HOOK_VERSION &&
-		    size == sizeof(*prev)) {
-			access_disabled = prev->access_disabled;
-			option_disabled = prev->option_disabled;
-			stuck_locked = prev->stuck_locked;
-		}
-		return 1;
-	}
-
-	return 0;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	if (crec_flash_physical_restore_state())
-		return EC_SUCCESS;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv;
-
-			rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						    EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Otherwise, do a hard boot to clear the flash protection registers */
-	system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void flash_preserve_state(void)
-{
-	const struct flash_wp_state state = {
-		.access_disabled = access_disabled,
-		.option_disabled = option_disabled,
-		.stuck_locked = stuck_locked,
-	};
-
-	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
deleted file mode 100644
index f34200219a..0000000000
--- a/chip/stm32/flash-stm32l.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "flash.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Approximate number of CPU cycles per iteration of the loop when polling
- * the flash status.
- */
-#define CYCLE_PER_FLASH_LOOP 10
-
-/* Flash page programming timeout.  This is 2x the datasheet max. */
-#define FLASH_TIMEOUT_MS 16
-
-static int flash_timeout_loop;
-
-/**
- * Lock all the locks.
- */
-static void lock(void)
-{
-	ignore_bus_fault(1);
-
-	STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK |
-		STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK;
-
-	ignore_bus_fault(0);
-}
-
-/**
- * Unlock the specified locks.
- */
-static int unlock(int locks)
-{
-	/*
-	 * We may have already locked the flash module and get a bus fault
-	 * in the attempt to unlock. Need to disable bus fault handler now.
-	 */
-	ignore_bus_fault(1);
-
-	/* Unlock PECR if needed */
-	if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) {
-		STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY1;
-		STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY2;
-	}
-
-	/* Fail if it didn't unlock */
-	if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) {
-		ignore_bus_fault(0);
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* Unlock program memory if required */
-	if ((locks & STM32_FLASH_PECR_PRG_LOCK) &&
-	    (STM32_FLASH_PECR & STM32_FLASH_PECR_PRG_LOCK)) {
-		STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY1;
-		STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY2;
-	}
-
-	/* Unlock option memory if required */
-	if ((locks & STM32_FLASH_PECR_OPT_LOCK) &&
-	    (STM32_FLASH_PECR & STM32_FLASH_PECR_OPT_LOCK)) {
-		STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY2;
-	}
-
-	ignore_bus_fault(0);
-
-	/* Successful if we unlocked everything we wanted */
-	if (!(STM32_FLASH_PECR & (locks | STM32_FLASH_PECR_PE_LOCK)))
-		return EC_SUCCESS;
-
-	/* Otherwise relock everything and return error */
-	lock();
-	return EC_ERROR_ACCESS_DENIED;
-}
-
-/**
- * Read an option byte word.
- *
- * Option bytes are stored in pairs in 32-bit registers; the upper 16 bits is
- * the 1's compliment of the lower 16 bits.
- */
-static uint16_t read_optb(int offset)
-{
-	return REG16(STM32_OPTB_BASE + offset);
-}
-
-/**
- * Write an option byte word.
- *
- * Requires OPT_LOCK unlocked.
- */
-static void write_optb(int offset, uint16_t value)
-{
-	REG32(STM32_OPTB_BASE + offset) =
-		(uint32_t)value | ((uint32_t)(~value) << 16);
-}
-
-/**
- * Read the at-boot protection option bits.
- */
-static uint32_t read_optb_wrp(void)
-{
-	return read_optb(STM32_OPTB_WRP1L) |
-		((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
-}
-
-/**
- * Write the at-boot protection option bits.
- */
-static void write_optb_wrp(uint32_t value)
-{
-	write_optb(STM32_OPTB_WRP1L, (uint16_t)value);
-	write_optb(STM32_OPTB_WRP1H, value >> 16);
-}
-
-/**
- * Write data to flash.
- *
- * This function lives in internal RAM, as we cannot read flash during writing.
- * You must not call other functions from this one or declare it static.
- */
-void  __attribute__((section(".iram.text")))
-	iram_flash_write(uint32_t *addr, uint32_t *data)
-{
-	int i;
-
-	/* Wait for ready  */
-	for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop); i++)
-		;
-
-	/* Set PROG and FPRG bits */
-	STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG;
-
-	/* Send words for the half page */
-	for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); i++)
-		*addr++ = *data++;
-
-	/* Wait for writes to complete */
-	for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop);
-	     i++)
-		;
-
-	/* Disable PROG and FPRG bits */
-	STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG);
-}
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	uint32_t *data32 = (uint32_t *)data;
-	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	int res = EC_SUCCESS;
-	int word_mode = 0;
-	int i;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) & 3)
-		return EC_ERROR_INVAL;
-
-	/* Unlock program area */
-	res = unlock(STM32_FLASH_PECR_PRG_LOCK);
-	if (res)
-		goto exit_wr;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0xf00;
-
-	/*
-	 * If offset and size aren't on word boundaries, do word writes.  This
-	 * is slower, but since we claim to the outside world that writes must
-	 * be half-page size, the only code which hits this path is writing
-	 * pstate (which is just writing one word).
-	 */
-	if ((offset | size) & (CONFIG_FLASH_WRITE_SIZE - 1))
-		word_mode = 1;
-
-	/* Update flash timeout based on current clock speed */
-	flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) /
-		CYCLE_PER_FLASH_LOOP;
-
-	while (size > 0) {
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset when doing
-		 * long writing with interrupt disabled.
-		 */
-		watchdog_reload();
-
-		if (word_mode) {
-			/* Word write */
-			*address++ = *data32++;
-
-			/* Wait for writes to complete */
-			for (i = 0; ((STM32_FLASH_SR & 9) != 8) &&
-				     (i < flash_timeout_loop); i++)
-				;
-
-			size -= sizeof(uint32_t);
-		} else {
-			/* Half page write */
-			interrupt_disable();
-			iram_flash_write(address, data32);
-			interrupt_enable();
-			address += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t);
-			data32 += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t);
-			size -= CONFIG_FLASH_WRITE_SIZE;
-		}
-
-		if (STM32_FLASH_SR & 1) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_wr;
-		}
-
-		/*
-		 * Check for error conditions: erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & 0xf00) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_wr;
-		}
-	}
-
-exit_wr:
-	/* Relock program lock */
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	uint32_t *address;
-	int res = EC_SUCCESS;
-
-	res = unlock(STM32_FLASH_PECR_PRG_LOCK);
-	if (res)
-		return res;
-
-	/* Clear previous error status */
-	STM32_FLASH_SR = 0xf00;
-
-	/* Set PROG and ERASE bits */
-	STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE;
-
-	for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-	     size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
-		timestamp_t deadline;
-
-		/* Do nothing if already erased */
-		if (crec_flash_is_erased((uint32_t)address -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    CONFIG_FLASH_ERASE_SIZE))
-			continue;
-
-		/* Start erase */
-		*address = 0x00000000;
-
-		/*
-		 * Reload the watchdog timer to avoid watchdog reset during
-		 * multi-page erase operations.
-		 */
-		watchdog_reload();
-
-		deadline.val = get_time().val + FLASH_TIMEOUT_MS * MSEC;
-		/* Wait for erase to complete */
-		while ((STM32_FLASH_SR & 1) &&
-		       (get_time().val < deadline.val)) {
-			usleep(300);
-		}
-		if (STM32_FLASH_SR & 1) {
-			res = EC_ERROR_TIMEOUT;
-			goto exit_er;
-		}
-
-		/*
-		 * Check for error conditions: erase failed, voltage error,
-		 * protection error
-		 */
-		if (STM32_FLASH_SR & 0xF00) {
-			res = EC_ERROR_UNKNOWN;
-			goto exit_er;
-		}
-	}
-
-exit_er:
-	/* Disable program and erase, and relock PECR */
-	STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE);
-	lock();
-
-	return res;
-}
-
-int crec_flash_physical_get_protect(int block)
-{
-	/*
-	 * If the entire flash interface is locked, then all blocks are
-	 * protected until reboot.
-	 */
-	if (crec_flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW)
-		return 1;
-
-	/* Check the active write protect status */
-	return STM32_FLASH_WRPR & BIT(block);
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	uint32_t prot;
-	uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET;
-	int rv;
-
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* Read the current protection status */
-	prot = read_optb_wrp();
-
-	/* Set/clear bits */
-	if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		prot |= mask;
-	else
-		prot &= ~mask;
-
-	if (prot == read_optb_wrp())
-		return EC_SUCCESS;  /* No bits changed */
-
-	/* Unlock option bytes */
-	rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
-	if (rv)
-		return rv;
-
-	/* Update them */
-	write_optb_wrp(prot);
-
-	/* Relock */
-	lock();
-
-	return EC_SUCCESS;
-}
-
-int crec_flash_physical_force_reload(void)
-{
-	int rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
-
-	if (rv)
-		return rv;
-
-	/* Force a reboot; this should never return. */
-	STM32_FLASH_PECR = STM32_FLASH_PECR_OBL_LAUNCH;
-	while (1)
-		;
-
-	return EC_ERROR_UNKNOWN;
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	uint32_t flags = 0;
-
-	/*
-	 * Try to unlock PECR; if that fails, then all flash is protected for
-	 * the current boot.
-	 */
-	if (unlock(STM32_FLASH_PECR_PE_LOCK))
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-	lock();
-
-	return flags;
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	if (all) {
-		/* Re-lock the registers if they're unlocked */
-		lock();
-
-		/* Prevent unlocking until reboot */
-		ignore_bus_fault(1);
-		STM32_FLASH_PEKEYR = 0;
-		ignore_bus_fault(0);
-
-		return EC_SUCCESS;
-	} else {
-		/* No way to protect just the RO flash until next boot */
-		return EC_ERROR_INVAL;
-	}
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-int crec_flash_pre_init(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-	uint32_t prot_flags = crec_flash_get_protect();
-	int need_reset = 0;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection. Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			/*
-			 * Pstate wants RO protected at boot, but the write
-			 * protect register wasn't set to protect it.  Force an
-			 * update to the write protect register and reboot so
-			 * it takes effect.
-			 */
-			crec_flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-
-		if (prot_flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT) {
-			/*
-			 * Write protect register was in an inconsistent state.
-			 * Set it back to a good state and reboot.
-			 */
-			crec_flash_protect_at_boot(prot_flags &
-					EC_FLASH_PROTECT_RO_AT_BOOT);
-			need_reset = 1;
-		}
-	} else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW |
-				 EC_FLASH_PROTECT_ERROR_INCONSISTENT)) {
-		/*
-		 * Write protect pin unasserted but some section is
-		 * protected. Drop it and reboot.
-		 */
-		unlock(STM32_FLASH_PECR_OPT_LOCK);
-		write_optb_wrp(0);
-		lock();
-		need_reset = 1;
-	}
-
-	if (need_reset)
-		system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS);
-
-	return EC_SUCCESS;
-}
diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c
deleted file mode 100644
index 55628cb6d4..0000000000
--- a/chip/stm32/gpio-f0-l.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * GPIO module for Chrome EC
- *
- * These functions are shared by the STM32F0 and STM32L variants.
- */
-
-#include "common.h"
-#include "gpio_chip.h"
-#include "registers.h"
-#include "util.h"
-
-static uint32_t expand_to_2bit_mask(uint32_t mask)
-{
-	uint32_t mask_out = 0;
-	while (mask) {
-		int bit = get_next_bit(&mask);
-		mask_out |= 3 << (bit * 2);
-	}
-	return mask_out;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	uint32_t flags = 0;
-	uint32_t val = 0;
-	const uint32_t mask2 = expand_to_2bit_mask(mask);
-
-	/* Only one bit must be set. */
-	if ((mask != (mask & -mask)) || (mask == 0))
-		return 0;
-
-	/* Check output type. */
-	val = STM32_GPIO_PUPDR(port) & mask2;
-	if (val == (0x55555555 & mask2))
-		flags |= GPIO_PULL_UP;
-	if (val == (0xaaaaaaaa & mask2))
-		flags |= GPIO_PULL_DOWN;
-
-	if (STM32_GPIO_OTYPER(port) & mask)
-		flags |= GPIO_OPEN_DRAIN;
-
-	/* Check mode. */
-	val = STM32_GPIO_MODER(port) & mask2;
-	if (val == (0x55555555 & mask2))
-		flags |= GPIO_OUTPUT;
-	if (val == (0xFFFFFFFF & mask2))
-		flags |= GPIO_ANALOG;
-	if (val == (0x0 & mask2))
-		flags |= GPIO_INPUT;
-	if (val == (0xaaaaaaaa & mask2))
-		flags |= GPIO_ALTERNATE;
-
-	if (flags & GPIO_OUTPUT) {
-		if (STM32_GPIO_ODR(port) & mask)
-			flags |= GPIO_HIGH;
-		else
-			flags |= GPIO_LOW;
-	}
-
-
-	if (STM32_EXTI_RTSR & mask)
-		flags |= GPIO_INT_F_RISING;
-	if (STM32_EXTI_RTSR & mask)
-		flags |= GPIO_INT_F_RISING;
-
-	return flags;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Bitmask for registers with 2 bits per GPIO pin */
-	const uint32_t mask2 = expand_to_2bit_mask(mask);
-	uint32_t val;
-
-	/* Set up pullup / pulldown */
-	val = STM32_GPIO_PUPDR(port) & ~mask2;
-	if (flags & GPIO_PULL_UP)
-		val |= 0x55555555 & mask2;	/* Pull Up = 01 */
-	else if (flags & GPIO_PULL_DOWN)
-		val |= 0xaaaaaaaa & mask2;	/* Pull Down = 10 */
-	STM32_GPIO_PUPDR(port) = val;
-
-	/*
-	 * Select open drain first, so that we don't glitch the signal when
-	 * changing the line to an output.
-	 */
-	if (flags & GPIO_OPEN_DRAIN)
-		STM32_GPIO_OTYPER(port) |= mask;
-	else
-		STM32_GPIO_OTYPER(port) &= ~mask;
-
-	val = STM32_GPIO_MODER(port) & ~mask2;
-	if (flags & GPIO_OUTPUT) {
-		/*
-		 * Set pin level first to avoid glitching.  This is harmless on
-		 * STM32L because the set/reset register isn't connected to the
-		 * output drivers until the pin is made an output.
-		 */
-		if (flags & GPIO_HIGH)
-			STM32_GPIO_BSRR(port) = mask;
-		else if (flags & GPIO_LOW)
-			STM32_GPIO_BSRR(port) = mask << 16;
-
-		/* General purpose, MODE = 01 */
-		val |= 0x55555555 & mask2;
-		STM32_GPIO_MODER(port) = val;
-
-	} else if (flags & GPIO_ANALOG) {
-		/* Analog, MODE=11 */
-		val |= 0xFFFFFFFF & mask2;
-		STM32_GPIO_MODER(port) = val;
-	} else if (flags & GPIO_INPUT) {
-		/* Input, MODE=00 */
-		STM32_GPIO_MODER(port) = val;
-	} else if (flags & GPIO_ALTERNATE) {
-		/* Alternate, MODE=10 */
-		val |= 0xaaaaaaaa & mask2;
-		STM32_GPIO_MODER(port) = val;
-	}
-
-	/* Set up interrupts if necessary */
-	ASSERT(!(flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH)));
-	if (flags & GPIO_INT_F_RISING)
-		STM32_EXTI_RTSR |= mask;
-	if (flags & GPIO_INT_F_FALLING)
-		STM32_EXTI_FTSR |= mask;
-	/* Interrupt is enabled by gpio_enable_interrupt() */
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	/* Ensure that the func parameter isn't overflowed */
-	BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX);
-
-	int bit;
-	uint32_t half;
-	uint32_t afr;
-	uint32_t moder = STM32_GPIO_MODER(port);
-
-	if (func == GPIO_ALT_FUNC_NONE) {
-		/* Return to normal GPIO function, defaulting to input. */
-		while (mask) {
-			bit = get_next_bit(&mask);
-			moder &= ~(0x3 << (bit * 2));
-		}
-		STM32_GPIO_MODER(port) = moder;
-		return;
-	}
-
-	/* Low half of the GPIO bank */
-	half = mask & 0xff;
-	afr = STM32_GPIO_AFRL(port);
-	while (half) {
-		bit = get_next_bit(&half);
-		afr &= ~(0xf << (bit * 4));
-		afr |= func << (bit * 4);
-		moder &= ~(0x3 << (bit * 2 + 0));
-		moder |= 0x2 << (bit * 2 + 0);
-	}
-	STM32_GPIO_AFRL(port) = afr;
-
-	/* High half of the GPIO bank */
-	half = (mask >> 8) & 0xff;
-	afr = STM32_GPIO_AFRH(port);
-	while (half) {
-		bit = get_next_bit(&half);
-		afr &= ~(0xf << (bit * 4));
-		afr |= func << (bit * 4);
-		moder &= ~(0x3 << (bit * 2 + 16));
-		moder |= 0x2 << (bit * 2 + 16);
-	}
-	STM32_GPIO_AFRH(port) = afr;
-	STM32_GPIO_MODER(port) = moder;
-}
diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c
deleted file mode 100644
index d7e7aa4391..0000000000
--- a/chip/stm32/gpio-stm32f0.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x7e0000;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0_1);
-	task_enable_irq(STM32_IRQ_EXTI2_3);
-	task_enable_irq(STM32_IRQ_EXTI4_15);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c
deleted file mode 100644
index bfc2631de8..0000000000
--- a/chip/stm32/gpio-stm32f3.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x7e0000;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c
deleted file mode 100644
index 4a4e095a71..0000000000
--- a/chip/stm32/gpio-stm32f4.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-int gpio_required_clocks(void)
-{
-	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
-	);
-
-	/*
-	 * If no ports are in use, then system_is_reboot_warm
-	 * may not be valid.
-	 */
-	ASSERT(gpio_ports_used);
-
-	return gpio_ports_used;
-}
-
-void gpio_enable_clocks(void)
-{
-	/* Enable only ports that are referenced in the gpio.inc */
-	STM32_RCC_AHB1ENR |= gpio_required_clocks();
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c
deleted file mode 100644
index 55b2c11e7b..0000000000
--- a/chip/stm32/gpio-stm32g4.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-int gpio_required_clocks(void)
-{
-	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
-	);
-
-	/*
-	 * If no ports are in use, then system_is_reboot_warm
-	 * may not be valid.
-	 */
-	ASSERT(gpio_ports_used);
-
-	return gpio_ports_used;
-}
-
-void gpio_enable_clocks(void)
-{
-	/* Enable only ports that are referenced in the gpio.inc */
-	STM32_RCC_AHB2ENR |= gpio_required_clocks();
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c
deleted file mode 100644
index a2fb97225d..0000000000
--- a/chip/stm32/gpio-stm32h7.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/* Enable all GPIOs clocks */
-	STM32_RCC_AHB4ENR |= STM32_RCC_AHB4ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c
deleted file mode 100644
index 52c424eea0..0000000000
--- a/chip/stm32/gpio-stm32l.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHBENR |= 0x3f;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c
deleted file mode 100644
index b5c4940454..0000000000
--- a/chip/stm32/gpio-stm32l4.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI9_5);
-	task_enable_irq(STM32_IRQ_EXTI15_10);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c
deleted file mode 100644
index 43a7db05da..0000000000
--- a/chip/stm32/gpio-stm32l5.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-void gpio_enable_clocks(void)
-{
-	/*
-	 * Enable all GPIOs clocks
-	 *
-	 * TODO(crosbug.com/p/23770): only enable the banks we need to,
-	 * and support disabling some of them in low-power idle.
-	 */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK;
-
-	/* Delay 1 AHB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_AHB, 1);
-}
-
-static void gpio_init(void)
-{
-	/* Enable IRQs now that pins are set up */
-	task_enable_irq(STM32_IRQ_EXTI0);
-	task_enable_irq(STM32_IRQ_EXTI1);
-	task_enable_irq(STM32_IRQ_EXTI2);
-	task_enable_irq(STM32_IRQ_EXTI3);
-	task_enable_irq(STM32_IRQ_EXTI4);
-	task_enable_irq(STM32_IRQ_EXTI5);
-	task_enable_irq(STM32_IRQ_EXTI6);
-	task_enable_irq(STM32_IRQ_EXTI7);
-	task_enable_irq(STM32_IRQ_EXTI8);
-	task_enable_irq(STM32_IRQ_EXTI9);
-	task_enable_irq(STM32_IRQ_EXTI10);
-	task_enable_irq(STM32_IRQ_EXTI11);
-	task_enable_irq(STM32_IRQ_EXTI12);
-	task_enable_irq(STM32_IRQ_EXTI13);
-	task_enable_irq(STM32_IRQ_EXTI14);
-	task_enable_irq(STM32_IRQ_EXTI15);
-
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI5, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI6, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI7, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI8, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI9, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI10, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI11, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI12, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI13, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI14, gpio_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_EXTI15, gpio_interrupt, 1);
-
-#include "gpio-f0-l.c"
diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c
deleted file mode 100644
index ccfd3399e2..0000000000
--- a/chip/stm32/gpio.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-/* For each EXTI bit, record which GPIO entry is using it */
-static uint8_t exti_events[16];
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	const struct unused_pin_info *u = unused_pin_list;
-	int is_warm = system_is_reboot_warm();
-	int i;
-
-	/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
-#ifdef CHIP_FAMILY_STM32H7
-	STM32_RCC_APB4ENR |= STM32_RCC_SYSCFGEN;
-#else
-	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
-#endif
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/* Disable all GPIO EXTINTs (EXTINT0..15) left enabled after sysjump. */
-	STM32_EXTI_IMR &= ~0xFFFF;
-
-	if (!is_warm)
-		gpio_enable_clocks();
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels or
-		 * we'll shut off the AP.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-
-	/* Configure optional unused pins for low power optimization. */
-	for (i = 0; i < unused_pin_count; i++, u++) {
-		/*
-		 * Configure unused pins as ANALOG INPUT to save power.
-		 * For more info, please see
-		 * "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY"
-		 * ("AN4365") section 1.2.6 and section 7.3.12 of the STM32F412
-		 * reference manual.
-		 */
-		if (IS_ENABLED(CHIP_FAMILY_STM32F4))
-			gpio_set_flags_by_mask(u->port, u->mask, GPIO_ANALOG);
-	}
-}
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(STM32_GPIO_IDR(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	STM32_GPIO_BSRR(gpio_list[signal].port) =
-			gpio_list[signal].mask << (value ? 0 : 16);
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	const struct gpio_info *g_old = gpio_list;
-
-	uint32_t bit, group, shift, bank;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	bit = GPIO_MASK_TO_NUM(g->mask);
-
-	g_old += exti_events[bit];
-
-	if ((exti_events[bit]) && (exti_events[bit] != signal)) {
-		CPRINTS("Overriding %s with %s on EXTI%d",
-			g_old->name, g->name, bit);
-	}
-	exti_events[bit] = signal;
-
-	group = bit / 4;
-	shift = (bit % 4) * 4;
-	bank = (g->port - STM32_GPIOA_BASE) / 0x400;
-
-	STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
-				      ~(0xF << shift)) | (bank << shift);
-	STM32_EXTI_IMR |= g->mask;
-
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	uint32_t bit;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	STM32_EXTI_IMR &= ~g->mask;
-
-	bit = GPIO_MASK_TO_NUM(g->mask);
-
-	exti_events[bit] = 0;
-
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Write 1 to clear interrupt */
-	STM32_EXTI_PR = g->mask;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Interrupt handler */
-
-void __keep gpio_interrupt(void)
-{
-	int bit;
-	/* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */
-	uint32_t pending = STM32_EXTI_PR & 0xFFFF;
-	uint8_t signal;
-
-	/* Write 1 to clear interrupt */
-	STM32_EXTI_PR = pending;
-
-	while (pending) {
-		bit = get_next_bit(&pending);
-		signal = exti_events[bit];
-		if (signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-#ifdef CHIP_FAMILY_STM32F0
-DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY);
-DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY);
-#endif
diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h
deleted file mode 100644
index a5b642fb05..0000000000
--- a/chip/stm32/gpio_chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CHIP_STM32_GPIO_CHIP_H
-#define __CROS_EC_CHIP_STM32_GPIO_CHIP_H
-
-#include "include/gpio.h"
-
-/**
- * Enable GPIO peripheral clocks.
- */
-void gpio_enable_clocks(void);
-
-/**
- * Return gpio port clocks that are necessary to support
- * the pins in gpio.inc.
- */
-int gpio_required_clocks(void);
-
-#endif  /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c
deleted file mode 100644
index b39a298c64..0000000000
--- a/chip/stm32/host_command_common.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "fpsensor_detect.h"
-#include "host_command.h"
-#include "spi.h"
-#include "usart_host_command.h"
-
-#ifndef CONFIG_I2C_PERIPHERAL
-
-/* Store current transport type */
-static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN;
-
-/*
- * Get protocol information
- */
-static enum ec_status host_command_protocol_info(struct host_cmd_handler_args
-						 *args)
-{
-	enum ec_status ret_status = EC_RES_INVALID_COMMAND;
-
-	/*
-	 * Read transport type from TRANSPORT_SEL bootstrap pin the first
-	 * time this function is called.
-	 */
-	if (IS_ENABLED(CONFIG_FINGERPRINT_MCU) &&
-	    (curr_transport_type == FP_TRANSPORT_TYPE_UNKNOWN))
-		curr_transport_type = get_fp_transport_type();
-
-	if (IS_ENABLED(CONFIG_USART_HOST_COMMAND) &&
-	    curr_transport_type == FP_TRANSPORT_TYPE_UART)
-		ret_status = usart_get_protocol_info(args);
-	else if (IS_ENABLED(CONFIG_SPI) &&
-		 curr_transport_type == FP_TRANSPORT_TYPE_SPI)
-		ret_status = spi_get_protocol_info(args);
-
-	return ret_status;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     host_command_protocol_info,
-		     EC_VER_MASK(0));
-
-#endif /* CONFIG_I2C_PERIPHERAL */
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
deleted file mode 100644
index 953110017f..0000000000
--- a/chip/stm32/hwtimer.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware timers driver */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * Trigger select mapping for slave timer from master timer.  This is
- * unfortunately not very straightforward; there's no tidy way to do this
- * algorithmically.  To avoid burning memory for a lookup table, use macros to
- * compute the offset.  This also has the benefit that compilation will fail if
- * an unsupported master/slave pairing is used.
- */
-#ifdef CHIP_FAMILY_STM32F0
-/*
- * Slave        Master
- *     1    15  2  3 17
- *     2     1 15  3 14
- *     3     1  2 15 14
- *    15     2  3 16 17
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15  0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_1_MASTER_17  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_1   0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_15  2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_15_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_15_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_15_MASTER_16 2
-#define STM32_TIM_TS_SLAVE_15_MASTER_17 3
-#elif defined(CHIP_FAMILY_STM32F3)
-/*
- * Slave        Master
- *     2    19 15  3 14
- *     3    19  2  5 14
- *     4    19  2  3 15
- *     5     2  3  4 15
- *    12     4  5 13 14
- *    19     2  3 15 16
- *    ---------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_2_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_15  1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_2_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_3_MASTER_5   2
-#define STM32_TIM_TS_SLAVE_3_MASTER_14  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_19  0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2   1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3   2
-#define STM32_TIM_TS_SLAVE_4_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_5_MASTER_2   0
-#define STM32_TIM_TS_SLAVE_5_MASTER_3   1
-#define STM32_TIM_TS_SLAVE_5_MASTER_4   2
-#define STM32_TIM_TS_SLAVE_5_MASTER_15  3
-#define STM32_TIM_TS_SLAVE_12_MASTER_4  0
-#define STM32_TIM_TS_SLAVE_12_MASTER_5  1
-#define STM32_TIM_TS_SLAVE_12_MASTER_13 2
-#define STM32_TIM_TS_SLAVE_12_MASTER_14 3
-#define STM32_TIM_TS_SLAVE_19_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_19_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_19_MASTER_15 2
-#define STM32_TIM_TS_SLAVE_19_MASTER_16 3
-#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */
-/*
- * Slave        Master
- *     1    15  2  3  4  (STM32F100 only)
- *     2     9 10  3  4
- *     3     9  2 11  4
- *     4    10  2  3  9
- *     9     2  3 10 11  (STM32L15x only)
- *     --------------------
- *     ts =  0  1  2  3
- */
-#define STM32_TIM_TS_SLAVE_1_MASTER_15 0
-#define STM32_TIM_TS_SLAVE_1_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_1_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_1_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_2_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_2_MASTER_10 1
-#define STM32_TIM_TS_SLAVE_2_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_2_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_3_MASTER_9  0
-#define STM32_TIM_TS_SLAVE_3_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_3_MASTER_11 2
-#define STM32_TIM_TS_SLAVE_3_MASTER_4  3
-#define STM32_TIM_TS_SLAVE_4_MASTER_10 0
-#define STM32_TIM_TS_SLAVE_4_MASTER_2  1
-#define STM32_TIM_TS_SLAVE_4_MASTER_3  2
-#define STM32_TIM_TS_SLAVE_4_MASTER_9  3
-#define STM32_TIM_TS_SLAVE_9_MASTER_2  0
-#define STM32_TIM_TS_SLAVE_9_MASTER_3  1
-#define STM32_TIM_TS_SLAVE_9_MASTER_10 2
-#define STM32_TIM_TS_SLAVE_9_MASTER_11 3
-#endif /* !CHIP_FAMILY_STM32F0 */
-#define TSMAP(slave, master) \
-	CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master)
-
-/*
- * Timers are defined per board.  This gives us flexibility to work around
- * timers which are dedicated to board-specific PWM sources.
- */
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB)
-#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB)
-#define IRQ_WD  IRQ_TIM(TIM_WATCHDOG)
-
-/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */
-#if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1)
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_BRK_UP_TRG
-#else /* !(TIM_WATCHDOG == 1) */
-#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_CC
-#endif /* !(TIM_WATCHDOG == 1) */
-
-#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE)
-#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG)
-
-static uint32_t last_deadline;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-
-	if ((deadline >> 16) > STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* first set a match on the MSB */
-		STM32_TIM_CCR1(TIM_CLOCK_MSB) = deadline >> 16;
-		/* disable LSB match */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) |= 2;
-	}
-	/*
-	 * In the unlikely case where the MSB has increased and matched
-	 * the deadline MSB before we set the match interrupt, as the STM
-	 * hardware timer won't trigger an interrupt, we fall back to the
-	 * following LSB event code to set another interrupt.
-	 */
-	if ((deadline >> 16) == STM32_TIM_CNT(TIM_CLOCK_MSB)) {
-		/* we can set a match on the LSB only */
-		STM32_TIM_CCR1(TIM_CLOCK_LSB) = deadline & 0xffff;
-		/* disable MSB match */
-		STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-		/* Clear the match flags */
-		STM32_TIM_SR(TIM_CLOCK_MSB) = ~2;
-		STM32_TIM_SR(TIM_CLOCK_LSB) = ~2;
-		/* Set the match interrupt */
-		STM32_TIM_DIER(TIM_CLOCK_LSB) |= 2;
-	}
-	/*
-	 * If the LSB deadline is already in the past and won't trigger an
-	 * interrupt, the common code in process_timers will deal with the
-	 * expired timer and automatically set the next deadline, we don't need
-	 * to do anything here.
-	 */
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupts */
-	STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2;
-	STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	uint32_t hi;
-	uint32_t lo;
-
-	/* Ensure the two half-words are coherent */
-	do {
-		hi = STM32_TIM_CNT(TIM_CLOCK_MSB);
-		lo = STM32_TIM_CNT(TIM_CLOCK_LSB);
-	} while (hi != STM32_TIM_CNT(TIM_CLOCK_MSB));
-
-	return (hi << 16) | lo;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	STM32_TIM_CNT(TIM_CLOCK_MSB) = ts >> 16;
-	STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB);
-
-	/* Clear status */
-	STM32_TIM_SR(TIM_CLOCK_LSB) = 0;
-	STM32_TIM_SR(TIM_CLOCK_MSB) = 0;
-
-	/*
-	 * Find expired timers and set the new timer deadline
-	 * signal overflow if the 16-bit MSB counter has overflowed.
-	 */
-	process_timers(stat_tim_msb & 0x01);
-}
-DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1);
-DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1);
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	volatile uint32_t *reg;
-	uint32_t mask = 0;
-
-	/*
-	 * Mapping of timers to reg/mask is split into a few different ranges,
-	 * some specific to individual chips.
-	 */
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n == 1) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM1;
-	}
-#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	if (n >= 9 && n <= 11) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM9 << (n - 9);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0)
-	if (n >= 15 && n <= 17) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM15 << (n - 15);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	if (n == 14) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM14;
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F3)
-	if (n == 12 || n == 13) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM12 << (n - 12);
-	}
-	if (n == 18) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM18;
-	}
-	if (n == 19) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM19;
-	}
-#endif
-
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	}
-
-	if (!mask)
-		return;
-
-	if (enable)
-		*reg |= mask;
-	else
-		*reg &= ~mask;
-}
-
-static void update_prescaler(void)
-{
-	/*
-	 * Pre-scaler value :
-	 * TIM_CLOCK_LSB is counting microseconds;
-	 * TIM_CLOCK_MSB is counting every TIM_CLOCK_LSB overflow.
-	 *
-	 * This will take effect at the next update event (when the current
-	 * prescaler counter ticks down, or if forced via EGR).
-	 */
-	STM32_TIM_PSC(TIM_CLOCK_MSB) = 0;
-	STM32_TIM_PSC(TIM_CLOCK_LSB) = (clock_get_timer_freq() / SECOND) - 1;
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/*
-	 * we use 2 chained 16-bit counters to emulate a 32-bit one :
-	 * TIM_CLOCK_MSB is the MSB (Slave)
-	 * TIM_CLOCK_LSB is the LSB (Master)
-	 */
-
-	/* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */
-	__hw_timer_enable_clock(TIM_CLOCK_MSB, 1);
-	__hw_timer_enable_clock(TIM_CLOCK_LSB, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Upcounter, counter disabled, update event only
-	 * on overflow.
-	 */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) = 0x0004;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) = 0x0004;
-	/*
-	 * TIM_CLOCK_LSB (master mode) generates a periodic trigger signal on
-	 * each UEV
-	 */
-	STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000;
-	STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020;
-
-	STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 |
-		(TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
-	STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Auto-reload value : 16-bit free-running counters */
-	STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff;
-	STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff;
-
-	/* Update prescaler */
-	update_prescaler();
-
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_EGR(TIM_CLOCK_LSB) = 0x0001;
-
-	/* Set up the overflow interrupt on TIM_CLOCK_MSB */
-	STM32_TIM_DIER(TIM_CLOCK_MSB) = 0x0001;
-	STM32_TIM_DIER(TIM_CLOCK_LSB) = 0x0000;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_CLOCK_MSB) |= 1;
-	STM32_TIM_CR1(TIM_CLOCK_LSB) |= 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_MSB);
-	task_enable_irq(IRQ_LSB);
-
-	return IRQ_LSB;
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* clear status */
-	timer->sr = 0;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
-void IRQ_HANDLER(IRQ_WD)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0,pc}\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
-
-void hwtimer_setup_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	/* Enable clock */
-	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Down counter, counter disabled, update
-	 * event only on overflow.
-	 */
-	timer->cr1 = 0x0014 | BIT(7);
-
-	/* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */
-	timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4);
-
-	/*
-	 * The auto-reload value is based on the period between rollovers for
-	 * TIM_CLOCK_LSB. Since TIM_CLOCK_LSB runs at 1MHz, it will overflow
-	 * in 65.536ms. We divide our required watchdog period by this amount
-	 * to obtain the number of times TIM_CLOCK_LSB can overflow before we
-	 * generate an interrupt.
-	 */
-	timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16);
-
-	/* count on every TIM_CLOCK_LSB overflow */
-	timer->psc = 0;
-
-	/* Reload the pre-scaler from arr when it goes below zero */
-	timer->egr = 0x0000;
-
-	/* setup the overflow interrupt */
-	timer->dier = 0x0001;
-
-	/* Start counting */
-	timer->cr1 |= 1;
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_WD);
-}
-
-void hwtimer_reset_watchdog(void)
-{
-	struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
-
-	timer->cnt = timer->arr;
-}
-
-#endif  /* defined(CONFIG_WATCHDOG_HELP) */
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c
deleted file mode 100644
index 963fa44e51..0000000000
--- a/chip/stm32/hwtimer32.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware 32-bit timer driver */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "panic.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	/* set the match on the deadline */
-	STM32_TIM32_CCR1(TIM_CLOCK32) = deadline;
-	/* Clear the match flags */
-	STM32_TIM_SR(TIM_CLOCK32) = ~2;
-	/* Set the match interrupt */
-	STM32_TIM_DIER(TIM_CLOCK32) |= 2;
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return STM32_TIM32_CCR1(TIM_CLOCK32);
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* Disable the match interrupts */
-	STM32_TIM_DIER(TIM_CLOCK32) &= ~2;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return STM32_TIM32_CNT(TIM_CLOCK32);
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	STM32_TIM32_CNT(TIM_CLOCK32) = ts;
-}
-
-void __hw_clock_source_irq(void)
-{
-	uint32_t stat_tim = STM32_TIM_SR(TIM_CLOCK32);
-
-	/* Clear status */
-	STM32_TIM_SR(TIM_CLOCK32) = 0;
-
-	/*
-	 * Find expired timers and set the new timer deadline
-	 * signal overflow if the update interrupt flag is set.
-	 */
-	process_timers(stat_tim & 0x01);
-}
-DECLARE_IRQ(IRQ_TIM(TIM_CLOCK32), __hw_clock_source_irq, 1);
-
-void __hw_timer_enable_clock(int n, int enable)
-{
-	volatile uint32_t *reg;
-	uint32_t mask = 0;
-
-	/*
-	 * Mapping of timers to reg/mask is split into a few different ranges,
-	 * some specific to individual chips.
-	 */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7)
-	if (n == 1) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM1;
-	}
-#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	if (n >= 9 && n <= 11) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM9 << (n - 9);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7)
-	if (n >= 15 && n <= 17) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM15 << (n - 15);
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-defined(CHIP_FAMILY_STM32H7)
-	if (n == 14) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM14;
-	}
-#endif
-
-#if defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32H7)
-	if (n == 12 || n == 13) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM12 << (n - 12);
-	}
-#endif
-#if defined(CHIP_FAMILY_STM32F3)
-	if (n == 18) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM18;
-	}
-	if (n == 19) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = STM32_RCC_PB2_TIM19;
-	}
-#endif
-#if defined(CHIP_FAMILY_STM32G4)
-	reg = &STM32_RCC_APB2ENR;
-	if (n == 1)
-		mask = STM32_RCC_APB2ENR_TIM1;
-	else if (n == 8)
-		mask = STM32_RCC_APB2ENR_TIM8;
-	else if (n == 20)
-		mask = STM32_RCC_APB2ENR_TIM20;
-	else if (n >= 15 && n <= 17)
-		mask = STM32_RCC_APB2ENR_TIM15 << (n - 15);
-#endif
-#if defined(CHIP_FAMILY_STM32L4)
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR1;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	} else if (n == 1 || n == 15 || n == 16) {
-		reg = &STM32_RCC_APB2ENR;
-		mask = (n == 1)	 ? STM32_RCC_APB2ENR_TIM1EN :
-		       (n == 15) ? STM32_RCC_APB2ENR_TIM15EN :
-					 STM32_RCC_APB2ENR_TIM16EN;
-	}
-#else
-	if (n >= 2 && n <= 7) {
-		reg = &STM32_RCC_APB1ENR;
-		mask = STM32_RCC_PB1_TIM2 << (n - 2);
-	}
-#endif
-
-	if (!mask)
-		return;
-
-	if (enable)
-		*reg |= mask;
-	else
-		*reg &= ~mask;
-}
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7)
-/* for families using a variable clock feeding the timer */
-static void update_prescaler(void)
-{
-	uint32_t t;
-	/*
-	 * Pre-scaler value :
-	 * the timer is incrementing every microsecond
-	 */
-	STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1;
-	/*
-	 * Forcing reloading the pre-scaler,
-	 * but try to maintain a sensible time-keeping while triggering
-	 * the update event.
-	 */
-	interrupt_disable();
-	/* Ignore the next update */
-	STM32_TIM_DIER(TIM_CLOCK32) &= ~0x0001;
-	/*
-	 * prepare to reload the counter with the current value
-	 * to avoid rolling backward the microsecond counter.
-	 */
-	t = STM32_TIM32_CNT(TIM_CLOCK32) + 1;
-	/* issue an update event, reloads the pre-scaler and the counter */
-	STM32_TIM_EGR(TIM_CLOCK32) = 0x0001;
-	/* clear the 'spurious' update unless we were going to roll-over */
-	if (t)
-		STM32_TIM_SR(TIM_CLOCK32) = ~1;
-	/* restore a sensible time value */
-	STM32_TIM32_CNT(TIM_CLOCK32) = t;
-	/* restore roll-over events */
-	STM32_TIM_DIER(TIM_CLOCK32) |= 0x0001;
-	interrupt_enable();
-
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Watchdog timer runs at 1KHz */
-	STM32_TIM_PSC(TIM_WATCHDOG) =
-		(clock_get_timer_freq()  / SECOND * MSEC)- 1;
-#endif  /* CONFIG_WATCHDOG_HELP */
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
-#endif /* CHIP_FAMILY_STM32L  || CHIP_FAMILY_STM32L4 || */
-	/*  CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-	/* Enable TIM peripheral block clocks */
-	__hw_timer_enable_clock(TIM_CLOCK32, 1);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Upcounter, counter disabled, update event only
-	 * on overflow.
-	 */
-	STM32_TIM_CR1(TIM_CLOCK32) = 0x0004;
-	/* No special configuration */
-	STM32_TIM_CR2(TIM_CLOCK32) = 0x0000;
-	STM32_TIM_SMCR(TIM_CLOCK32) = 0x0000;
-
-	/* Auto-reload value : 32-bit free-running counter */
-	STM32_TIM32_ARR(TIM_CLOCK32) = 0xffffffff;
-
-	/* Update prescaler to increment every microsecond */
-	STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1;
-
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_CLOCK32) = 0x0001;
-
-	/* Set up the overflow interrupt */
-	STM32_TIM_DIER(TIM_CLOCK32) = 0x0001;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_CLOCK32) |= 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_TIM(TIM_CLOCK32));
-
-	return IRQ_TIM(TIM_CLOCK32);
-}
-
-#ifdef CONFIG_WATCHDOG_HELP
-
-#define IRQ_WD IRQ_TIM(TIM_WATCHDOG)
-
-void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
-{
-	/* clear status */
-	STM32_TIM_SR(TIM_WATCHDOG) = 0;
-
-	watchdog_trace(excep_lr, excep_sp);
-}
-
-void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
-void IRQ_HANDLER(IRQ_WD)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI. */
-		     "push {r0, lr}\n"
-		     "bl watchdog_check\n"
-		     "pop {r0,pc}\n");
-}
-const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
-
-void hwtimer_setup_watchdog(void)
-{
-	int freq;
-
-	/* Enable clock */
-	__hw_timer_enable_clock(TIM_WATCHDOG, 1);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Timer configuration : Up counter, counter disabled, update
-	 * event only on overflow.
-	 */
-	STM32_TIM_CR1(TIM_WATCHDOG) = 0x0004;
-	/* No special configuration */
-	STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000;
-	STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000;
-
-	/*
-	 * all timers has 16-bit prescale.
-	 * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz.
-	 * set prescale as 10KHz and 10 times arr value instead.
-	 * For clock freq < 64MHz, timer runs at 1KHz.
-	 */
-	freq = clock_get_timer_freq();
-
-	if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) {
-		/* AUto-reload value */
-		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS;
-
-		/* Update prescaler: watchdog timer runs at 1KHz */
-		STM32_TIM_PSC(TIM_WATCHDOG) =
-			(freq / SECOND * MSEC) - 1;
-	}
-#ifdef CHIP_FAMILY_STM32L4
-	else {
-		/* 10 times ARR value with 10KHz timer */
-		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10;
-
-		/* Update prescaler: watchdog timer runs at 10KHz */
-		STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1;
-	}
-#endif
-	/* Reload the pre-scaler */
-	STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001;
-
-	/* setup the overflow interrupt */
-	STM32_TIM_DIER(TIM_WATCHDOG) = 0x0001;
-	STM32_TIM_SR(TIM_WATCHDOG) = 0;
-
-	/* Start counting */
-	STM32_TIM_CR1(TIM_WATCHDOG) |= 1;
-
-	/* Enable timer interrupts */
-	task_enable_irq(IRQ_WD);
-}
-
-void hwtimer_reset_watchdog(void)
-{
-	STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000;
-}
-
-#endif  /* CONFIG_WATCHDOG_HELP */
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
deleted file mode 100644
index cdf5421efc..0000000000
--- a/chip/stm32/i2c-stm32f0.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "i2c_private.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER	(10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_PERIPHERAL STM32_IRQ_I2C1
-#else
-#define IRQ_PERIPHERAL STM32_IRQ_I2C2
-#endif
-#endif
-
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER;
-}
-
-/* timingr register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta = 0;
-
-	do {
-		int isr = STM32_I2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Supported i2c input clocks */
-enum stm32_i2c_clk_src {
-	I2C_CLK_SRC_48MHZ = 0,
-	I2C_CLK_SRC_8MHZ = 1,
-	I2C_CLK_SRC_COUNT,
-};
-
-/* timingr register values for supported input clks / i2c clk rates */
-static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
-	[I2C_CLK_SRC_48MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x50100103,
-		[I2C_FREQ_400KHZ] = 0x50330609,
-		[I2C_FREQ_100KHZ] = 0xB0421214,
-	},
-	[I2C_CLK_SRC_8MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x00100306,
-		[I2C_FREQ_400KHZ] = 0x00310309,
-		[I2C_FREQ_100KHZ] = 0x10420f13,
-	},
-};
-
-int chip_i2c_set_freq(int port, enum i2c_freq freq)
-{
-	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
-
-#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
-	if (port == STM32_I2C1_PORT) {
-		/*
-		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
-		 * from STOP mode since HSI is only clock running immediately
-		 * upon exit from STOP mode.
-		 */
-		src = I2C_CLK_SRC_8MHZ;
-	}
-#endif
-
-	/* Disable port */
-	STM32_I2C_CR1(port) = 0;
-	STM32_I2C_CR2(port) = 0;
-	/* Set clock frequency */
-	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
-	/* Enable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
-
-	pdata[port].freq = freq;
-
-	return EC_SUCCESS;
-}
-
-enum i2c_freq chip_i2c_get_freq(int port)
-{
-	return pdata[port].freq;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static int i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int ret = EC_SUCCESS;
-	enum i2c_freq freq;
-
-	/* Enable clocks to I2C modules if necessary */
-	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
-		STM32_RCC_APB1ENR |= 1 << (21 + port);
-
-	if (port == STM32_I2C1_PORT) {
-#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
-		/*
-		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
-		 * from STOP mode since HSI is only clock running immediately
-		 * upon exit from STOP mode.
-		 */
-		STM32_RCC_CFGR3 &= ~0x10;
-#else
-		/* Use SYSCLK for i2c clock. */
-		STM32_RCC_CFGR3 |= 0x10;
-#endif
-	}
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set clock frequency */
-	switch (p->kbps) {
-	case 1000:
-		freq = I2C_FREQ_1000KHZ;
-		break;
-	case 400:
-		freq = I2C_FREQ_400KHZ;
-		break;
-	case 100:
-		freq = I2C_FREQ_100KHZ;
-		break;
-	default: /* unknown speed, defaults to 100kBps */
-		CPRINTS("I2C bad speed %d kBps", p->kbps);
-		freq = I2C_FREQ_100KHZ;
-		ret = EC_ERROR_INVAL;
-	}
-
-	/* Set up initial bus frequencies */
-	chip_i2c_set_freq(p->port, freq);
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-
-	return ret;
-}
-
-/*****************************************************************************/
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* Host command peripheral */
-/*
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static int host_i2c_resp_port;
-static int tx_pending;
-static int tx_index, tx_end;
-static struct host_packet i2c_packet;
-
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* host_buffer data range */
-	tx_index = 0;
-	tx_end = size + 2;
-
-	/*
-	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the controller i2c
-	 * doesn't need to snoop the response stream to abort transaction.
-	 */
-	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
-}
-
-/* Process the command in the i2c host buffer */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	/*
-	 * TODO(crosbug.com/p/29241): Combine this functionality with the
-	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
-	 * host command i2c process function which handles all protocol
-	 * versions.
-	 */
-	i2c_packet.send_response = i2c_send_response_packet;
-
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-	host_packet_receive(&i2c_packet);
-}
-
-#ifdef TCPCI_I2C_PERIPHERAL
-static void i2c_send_tcpc_response(int len)
-{
-	/* host_buffer data range, beyond this length, will return 0xec */
-	tx_index = 0;
-	tx_end = len;
-
-	/* enable transmit interrupt and use irq to send data back */
-	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
-}
-
-static void i2c_process_tcpc_command(int read, int addr, int len)
-{
-	tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0],
-			 i2c_send_tcpc_response);
-}
-#endif
-
-static void i2c_event_handler(int port)
-{
-	int i2c_isr;
-	static int rx_pending, buf_idx;
-#ifdef TCPCI_I2C_PERIPHERAL
-	int addr;
-#endif
-
-	i2c_isr = STM32_I2C_ISR(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a peripheral allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
-				STM32_I2C_ICR_ARLOCF;
-	}
-
-	/* Transfer matched our peripheral address */
-	if (i2c_isr & STM32_I2C_ISR_ADDR) {
-		if (i2c_isr & STM32_I2C_ISR_DIR) {
-			/* Transmitter peripheral */
-			/* Clear transmit buffer */
-			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
-
-			/* Enable txis interrupt to start response */
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
-		} else {
-			/* Receiver peripheral */
-			buf_idx = 0;
-			rx_pending = 1;
-		}
-
-		/* Clear ADDR bit by writing to ADDRCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
-		/* Inhibit sleep mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Receiver full event */
-	if (i2c_isr & STM32_I2C_ISR_RXNE)
-		host_buffer[buf_idx++] = STM32_I2C_RXDR(port);
-
-	/* Stop condition on bus */
-	if (i2c_isr & STM32_I2C_ISR_STOP) {
-#ifdef TCPCI_I2C_PERIPHERAL
-		/*
-		 * if tcpc is being addressed, and we received a stop
-		 * while rx is pending, then this is a write only to
-		 * the tcpc.
-		 */
-		addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port));
-		if (rx_pending && ADDR_IS_TCPC(addr))
-			i2c_process_tcpc_command(0, addr, buf_idx);
-#endif
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear STOPF bit by writing to STOPCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Controller requested STOP or RESTART */
-	if (i2c_isr & STM32_I2C_ISR_NACK) {
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-		/* Clear NACK */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
-		/* Resend last byte on RESTART */
-		if (port == I2C_PORT_EC && tx_index)
-			tx_index--;
-	}
-
-	/* Transmitter empty event */
-	if (i2c_isr & STM32_I2C_ISR_TXIS) {
-		if (port == I2C_PORT_EC) { /* host is waiting for PD response */
-			if (tx_pending) {
-				if (tx_index < tx_end) {
-					STM32_I2C_TXDR(port) =
-						host_buffer[tx_index++];
-				} else {
-					STM32_I2C_TXDR(port) = 0xec;
-					/*
-					 * Set tx_index = 0 to prevent NACK
-					 * handler resending last buffer byte.
-					 */
-					tx_index = 0;
-					tx_end = 0;
-					/* No pending data */
-					tx_pending = 0;
-				}
-			} else if (rx_pending) {
-				host_i2c_resp_port = port;
-				/*
-				 * Disable TXIS interrupt, transmission will
-				 * be prepared by host command task.
-				 */
-				STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-#ifdef TCPCI_I2C_PERIPHERAL
-				addr = STM32_I2C_ISR_ADDCODE(
-					STM32_I2C_ISR(port));
-				if (ADDR_IS_TCPC(addr))
-					i2c_process_tcpc_command(1, addr,
-								 buf_idx);
-				else
-#endif
-					i2c_process_command();
-
-				/* Reset host buffer after end of transfer */
-				rx_pending = 0;
-				tx_pending = 1;
-			} else {
-				STM32_I2C_TXDR(port) = 0xec;
-			}
-		}
-	}
-}
-void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
-#endif
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-
-#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT)
-	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
-		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1);
-#endif
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		uint32_t cr2 = STM32_I2C_CR2(port);
-
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(port) = 0;
-		if (cr2 & STM32_I2C_CR2_RELOAD) {
-			/*
-			 * If I2C_XFER_START flag is on and we've set RELOAD=1
-			 * in previous chip_i2c_xfer() call. Then we are
-			 * probably in the middle of an i2c transaction.
-			 *
-			 * In this case, we need to clear the RELOAD bit and
-			 * wait for Transfer Complete (TC) flag, to make sure
-			 * the chip is not expecting another NBYTES data, And
-			 * send repeated-start correctly.
-			 */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(port) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[i] = STM32_I2C_RXDR(port);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(port) = 0;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-
-#ifdef CONFIG_I2C_SCL_GATE_ADDR
-	if (port == CONFIG_I2C_SCL_GATE_PORT &&
-	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
-		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0);
-#endif
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
-	/*
-	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
-	 * from STOP mode on address match. Note, this only works on I2C1 and
-	 * only if the clock to I2C1 is HSI 8MHz.
-	 */
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
-#endif
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-#ifdef TCPCI_I2C_PERIPHERAL
-	/*
-	 * Configure TCPC address with OA2[1] masked so that we respond
-	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
-	 */
-	STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100
-		| (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
-#endif
-	task_enable_irq(IRQ_PERIPHERAL);
-#endif
-}
-
diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c
deleted file mode 120000
index ce8523ea90..0000000000
--- a/chip/stm32/i2c-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-i2c-stm32f0.c
\ No newline at end of file
diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c
deleted file mode 100644
index c1f19704b5..0000000000
--- a/chip/stm32/i2c-stm32f4.c
+++ /dev/null
@@ -1,1010 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER   (10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C1_EV
-#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C1_ER
-#else
-#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C2_EV
-#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C2_ER
-#endif
-#endif
-
-/* Define I2C blocks available in stm32f4:
- * We have standard ST I2C blocks and a "fast mode plus" I2C block,
- * which do not share the same registers or functionality. So we'll need
- * two sets of functions to handle this for stm32f4. In stm32f446, we
- * only have one FMP block so we'll hardcode its port number.
- */
-#define STM32F4_FMPI2C_PORT	3
-
-static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)},
-	{STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)},
-	{STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)},
-};
-
-static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)},
-	{STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)},
-	{STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)},
-};
-
-/* Callback for ISR to wake task on DMA complete. */
-static inline void _i2c_dma_wake_callback(void *cb_data, int port)
-{
-	task_id_t id = (task_id_t)(int)cb_data;
-
-	if (id != TASK_ID_INVALID)
-		task_set_event(id, TASK_EVENT_I2C_COMPLETION(port));
-}
-
-/* Each callback is hardcoded to an I2C channel. */
-static void _i2c_dma_wake_callback_0(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 0);
-}
-
-static void _i2c_dma_wake_callback_1(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 1);
-}
-
-static void _i2c_dma_wake_callback_2(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 2);
-}
-
-static void _i2c_dma_wake_callback_3(void *cb_data)
-{
-	_i2c_dma_wake_callback(cb_data, 3);
-}
-
-/* void (*callback)(void *) */
-static void (*i2c_callbacks[I2C_PORT_COUNT])(void *) = {
-	_i2c_dma_wake_callback_0,
-	_i2c_dma_wake_callback_1,
-	_i2c_dma_wake_callback_2,
-	_i2c_dma_wake_callback_3,
-};
-
-/* Enable the I2C interrupt callback for this port. */
-void i2c_dma_enable_tc_interrupt(enum dma_channel stream, int port)
-{
-	dma_enable_tc_interrupt_callback(stream, i2c_callbacks[port],
-					 (void *)(int)task_get_current());
-}
-
-/**
- * Wait for SR1 register to contain the specified mask of 0 or 1.
- *
- * @param port		I2C port
- * @param mask		mask of bits of interest
- * @param val		desired value of bits of interest
- * @param poll		uS poll frequency
- *
- * @return		EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-#define SET 0xffffffff
-#define UNSET 0
-static int wait_sr1_poll(int port, int mask, int val, int poll)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
-
-	while (get_time().val < timeout) {
-		int sr1 = STM32_I2C_SR1(port);
-
-		/* Check for errors */
-		if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR |
-			   STM32_I2C_SR1_AF)) {
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((sr1 & mask) == (val & mask))
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(poll);
-	}
-
-	CPRINTS("I2C timeout: p:%d m:%x", port, mask);
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Wait for SR1 register to contain the specified mask of ones */
-static int wait_sr1(int port, int mask)
-{
-	return wait_sr1_poll(port, mask, SET, 100);
-}
-
-
-/**
- * Send a start condition and peripheral address on the specified port.
- *
- * @param port		I2C port
- * @param addr_8bit	I2C address, with LSB set for receive-mode
- *
- * @return Non-zero if error.
- */
-static int send_start(const int port, const uint16_t addr_8bit)
-{
-	int rv;
-
-	/* Send start bit */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_START;
-	rv = wait_sr1_poll(port, STM32_I2C_SR1_SB, SET, 1);
-	if (rv)
-		return I2C_ERROR_FAILED_START;
-
-	/* Write peripheral address */
-	STM32_I2C_DR(port) = addr_8bit;
-	rv = wait_sr1_poll(port, STM32_I2C_SR1_ADDR, SET, 1);
-	if (rv)
-		return rv;
-
-	/* Read SR2 to clear ADDR bit */
-	rv = STM32_I2C_SR2(port);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Find the i2c port structure associated with the port.
- *
- * @return i2c_port_t * associated with this port number.
- */
-static const struct i2c_port_t *find_port(int port)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++) {
-		if (p->port == port)
-			return p;
-	}
-	CPRINTS("I2C port %d invalid! Crashing now.", port);
-	return NULL;
-}
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * @param port		I2C port
- * @param mask		mask of bits of interest
- * @param val		desired value of bits of interest
- * @param poll		uS poll frequency
- *
- * @return		EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER;
-
-	while (get_time().val < timeout) {
-		int isr = STM32_FMPI2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR |
-			   FMPI2C_ISR_NACKF)) {
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((isr & mask) == (val & mask))
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(poll);
-	}
-
-	CPRINTS("FMPI2C timeout p:%d, m:0x%08x", port, mask);
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Wait for ISR register to contain the specified mask of ones */
-static int wait_fmpi2c_isr(int port, int mask)
-{
-	return wait_fmpi2c_isr_poll(port, mask, SET, 100);
-}
-
-/**
- * Send a start condition and peripheral address on the specified port.
- *
- * @param port		I2C port
- * @param addr_8bit	I2C address
- * @param size		bytes to transfer
- * @param is_read	read, or write?
- *
- * @return Non-zero if error.
- */
-static int send_fmpi2c_start(const int port, const uint16_t addr_8bit,
-			     int size, int is_read)
-{
-	uint32_t reg;
-
-	/* Send start bit */
-	reg = STM32_FMPI2C_CR2(port);
-	reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK |
-		FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND |
-		FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP);
-	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND |
-		addr_8bit | FMPI2C_CR2_SIZE(size) |
-		(is_read ? FMPI2C_CR2_RD_WRN : 0);
-	STM32_FMPI2C_CR2(port) = reg;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set i2c clock rate..
- *
- * @param p		I2C port struct
- */
-static void i2c_set_freq_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int freq = clock_get_freq();
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		int prescalar;
-		int actual;
-		uint32_t reg;
-
-		/* FMP I2C clock set. */
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		prescalar = (freq / (p->kbps * 1000 *
-			     (0x12 + 1 + 0xe + 1 + 1))) - 1;
-		actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1));
-
-		reg = FMPI2C_TIMINGR_SCLL(0x12) |
-			FMPI2C_TIMINGR_SCLH(0xe) |
-			FMPI2C_TIMINGR_PRESC(prescalar);
-		STM32_FMPI2C_TIMINGR(port) = reg;
-
-		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x",
-			port, p->kbps, prescalar, actual, reg);
-
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-		udelay(10);
-	} else {
-		/* Force peripheral reset and disable port */
-		STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST;
-		STM32_I2C_CR1(port) = 0;
-
-		/* Set clock frequency */
-		if (p->kbps > 100) {
-			STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
-		} else {
-			STM32_I2C_CCR(port) = STM32_I2C_CCR_FM
-				| STM32_I2C_CCR_DUTY
-				| (freq / (16 + 9 * MSEC * p->kbps));
-		}
-		STM32_I2C_CR2(port) = freq / SECOND;
-		STM32_I2C_TRISE(port) = freq / SECOND + 1;
-
-		/* Enable port */
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-
-	/* Configure GPIOs, clocks */
-	gpio_config_module(MODULE_I2C, 1);
-	clock_enable_module(MODULE_I2C, 1);
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		/* FMP I2C block */
-		/* Set timing (?) */
-		STM32_FMPI2C_TIMINGR(port) = TIMINGR_THE_RIGHT_VALUE;
-		udelay(10);
-		/* Device enable */
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-		/* Need to wait 3 APB cycles */
-		udelay(10);
-		/* Device only. */
-		STM32_FMPI2C_OAR1(port) = 0;
-		STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_AUTOEND;
-	} else {
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_SWRST;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_SWRST;
-		udelay(10);
-	}
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p);
-}
-
-/*****************************************************************************/
-/* Interface */
-
-/**
- * Clear status regs on the specified I2C port.
- *
- * @param port		the I2c port
- */
-static void fmpi2c_clear_regs(int port)
-{
-	/* Clear status */
-	STM32_FMPI2C_ICR(port) = 0xffffffff;
-
-	/* Clear start, stop, NACK, etc. bits to get us in a known state */
-	STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP |
-				FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK |
-				FMPI2C_CR2_AUTOEND |
-				FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK);
-}
-
-/**
- * Perform an i2c transaction
- *
- * @param port		i2c port to use
- * @param addr_8bit	the i2c address
- * @param out		source buffer for data
- * @param out_bytes	bytes of data to write
- * @param in		destination buffer for data
- * @param in_bytes	bytes of data to read
- * @param flags		user cached I2C state
- *
- * @return		EC_SUCCESS on success.
- */
-static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
-			    const uint8_t *out, int out_bytes,
-			    uint8_t *in, int in_bytes, int flags)
-{
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-	ASSERT(!started);
-
-	if (STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY) {
-		CPRINTS("fmpi2c port %d busy", port);
-		return EC_ERROR_BUSY;
-	}
-
-	fmpi2c_clear_regs(port);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		rv = send_fmpi2c_start(
-			port, addr_8bit, out_bytes, FMPI2C_WRITE);
-		if (rv)
-			goto xfer_exit;
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_fmpi2c_isr(port, FMPI2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-
-			/* Write next data byte */
-			STM32_FMPI2C_TXDR(port) = out[i];
-		}
-
-		/* Wait for transaction STOP. */
-		wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF);
-	}
-
-	if (in_bytes) {
-		int rv_start;
-		const struct dma_option *dma = dma_rx_option + port;
-
-		dma_start_rx(dma, in_bytes, in);
-		i2c_dma_enable_tc_interrupt(dma->channel, port);
-
-		rv_start = send_fmpi2c_start(
-				port, addr_8bit, in_bytes, FMPI2C_READ);
-		if (rv_start)
-			goto xfer_exit;
-
-		rv = wait_fmpi2c_isr(port, FMPI2C_ISR_RXNE);
-		if (rv)
-			goto xfer_exit;
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN;
-
-		rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
-		if (rv & TASK_EVENT_I2C_COMPLETION(port))
-			rv = EC_SUCCESS;
-		else
-			rv = EC_ERROR_TIMEOUT;
-
-		dma_disable(dma->channel);
-		dma_disable_tc_interrupt(dma->channel);
-
-		/* Validate i2c is STOPped */
-		if (!rv)
-			rv = wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF);
-
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN;
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_STOP;
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p;
-
-			CPRINTS("chip_fmpi2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			p = find_port(port);
-			i2c_unwedge(port);
-			i2c_init_port(p);
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY))
-				break;
-			usleep(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		usleep(10);
-		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-
-/**
- * Clear status regs on the specified I2C port.
- *
- * @param port		the I2c port
- */
-static void i2c_clear_regs(int port)
-{
-	/*
-	 * Clear status
-	 *
-	 * TODO(crosbug.com/p/29314): should check for any leftover error
-	 * status, and reset the port if present.
-	 */
-	STM32_I2C_SR1(port) = 0;
-
-	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
-}
-
-/*****************************************************************************
- * Exported functions declared in i2c.h
- */
-
-/* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-	const struct i2c_port_t *p = find_port(port);
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-	ASSERT(!started);
-
-	if (p->port == STM32F4_FMPI2C_PORT) {
-		return chip_fmpi2c_xfer(port, addr_8bit,
-					out, out_bytes,
-					in, in_bytes, flags);
-	}
-
-	i2c_clear_regs(port);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		rv = send_start(port, addr_8bit);
-		if (rv)
-			goto xfer_exit;
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			/* Write next data byte */
-			STM32_I2C_DR(port) = out[i];
-
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* If no input bytes, queue stop condition */
-		if (!in_bytes && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-	}
-
-	if (in_bytes) {
-		int rv_start;
-
-		const struct dma_option *dma = dma_rx_option + port;
-
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_POS;
-		dma_start_rx(dma, in_bytes, in);
-		i2c_dma_enable_tc_interrupt(dma->channel, port);
-
-		/* Setup ACK/POS before sending start as per user manual */
-		if (in_bytes == 2)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS;
-		else if (in_bytes != 1)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK;
-
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_STOP;
-
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_LAST;
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_DMAEN;
-
-		rv_start = send_start(port, addr_8bit | 0x01);
-
-		if ((in_bytes == 1) && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-		if (!rv_start) {
-			rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
-			if (rv & TASK_EVENT_I2C_COMPLETION(port))
-				rv = EC_SUCCESS;
-			else
-				rv = EC_ERROR_TIMEOUT;
-		}
-
-		dma_disable(dma->channel);
-		dma_disable_tc_interrupt(dma->channel);
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
-		/* Disable ack */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-
-		if (rv_start)
-			rv = rv_start;
-
-		/* Send stop. */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_LAST;
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p;
-
-			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			p = find_port(port);
-			i2c_unwedge(port);
-			i2c_init_port(p);
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY))
-				break;
-			usleep(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows peripherals on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		usleep(10);
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-#ifdef CONFIG_I2C_CONTROLLER
-/* Handle CPU clock changing frequency */
-static void i2c_freq_change(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_set_freq_port(p);
-}
-
-/* Handle an upcoming frequency change. */
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-/* Handle a frequency change */
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	i2c_freq_change();
-
-	/* Unlock I2C ports we locked in pre-freq change hook */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 0);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Peripheral */
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-/* Host command peripheral */
-/*
- * Buffer for received host command packets (including prefix byte on request,
- * and result/size on response).  After any protocol-specific headers, the
- * buffers must be 32-bit aligned.
- */
-static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
-				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
-static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
-static int host_i2c_resp_port;
-static int tx_pending;
-static int tx_index, tx_end;
-static struct host_packet i2c_packet;
-
-static void i2c_send_response_packet(struct host_packet *pkt)
-{
-	int size = pkt->response_size;
-	uint8_t *out = host_buffer;
-
-	/* Ignore host command in-progress */
-	if (pkt->driver_result == EC_RES_IN_PROGRESS)
-		return;
-
-	/* Write result and size to first two bytes. */
-	*out++ = pkt->driver_result;
-	*out++ = size;
-
-	/* host_buffer data range */
-	tx_index = 0;
-	tx_end = size + 2;
-
-	/*
-	 * Set the transmitter to be in 'not full' state to keep sending
-	 * '0xec' in the event loop. Because of this, the controller i2c
-	 * doesn't need to snoop the response stream to abort transaction.
-	 */
-	STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN;
-}
-
-/* Process the command in the i2c host buffer */
-static void i2c_process_command(void)
-{
-	char *buff = host_buffer;
-
-	/*
-	 * TODO(crosbug.com/p/29241): Combine this functionality with the
-	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
-	 * host command i2c process function which handles all protocol
-	 * versions.
-	 */
-	i2c_packet.send_response = i2c_send_response_packet;
-
-	i2c_packet.request = (const void *)(&buff[1]);
-	i2c_packet.request_temp = params_copy;
-	i2c_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer */
-	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
-
-	/*
-	 * Stuff response at buff[2] to leave the first two bytes of
-	 * buffer available for the result and size to send over i2c.  Note
-	 * that this 2-byte offset and the 2-byte offset from host_buffer
-	 * add up to make the response buffer 32-bit aligned.
-	 */
-	i2c_packet.response = (void *)(&buff[2]);
-	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
-	i2c_packet.response_size = 0;
-
-	if (*buff >= EC_COMMAND_PROTOCOL_3) {
-		i2c_packet.driver_result = EC_RES_SUCCESS;
-	} else {
-		/* Only host command protocol 3 is supported. */
-		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
-	}
-	host_packet_receive(&i2c_packet);
-}
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-static void i2c_send_board_response(int len)
-{
-	/* host_buffer data range, beyond this length, will return 0xec */
-	tx_index = 0;
-	tx_end = len;
-
-	/* enable transmit interrupt and use irq to send data back */
-	STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN;
-}
-
-static void i2c_process_board_command(int read, int addr, int len)
-{
-	board_i2c_process(read, addr, len, &host_buffer[0],
-			  i2c_send_board_response);
-}
-#endif
-
-static void i2c_event_handler(int port)
-{
-	volatile uint32_t i2c_cr1;
-	volatile uint32_t i2c_sr2;
-	volatile uint32_t i2c_sr1;
-	static int rx_pending, buf_idx;
-	static uint16_t addr_8bit;
-
-	volatile uint32_t unused __attribute__((unused));
-
-	i2c_cr1 = STM32_I2C_CR1(port);
-	i2c_sr2 = STM32_I2C_SR2(port);
-	i2c_sr1 = STM32_I2C_SR1(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a peripheral allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (i2c_sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-		/* Disable buffer interrupt */
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-		/* Clear error status bits */
-		STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO |
-					 STM32_I2C_SR1_BERR);
-	}
-
-	/* Transfer matched our peripheral address */
-	if (i2c_sr1 & STM32_I2C_SR1_ADDR) {
-		addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ?
-			STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe;
-		if (i2c_sr2 & STM32_I2C_SR2_TRA) {
-			/* Transmitter peripheral */
-			i2c_sr1 |= STM32_I2C_SR1_TXE;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-			if (!rx_pending && !tx_pending) {
-				tx_pending = 1;
-				i2c_process_board_command(1, addr_8bit, 0);
-			}
-#endif
-		} else {
-			/* Receiver peripheral */
-			buf_idx = 0;
-			rx_pending = 1;
-		}
-
-		/* Enable buffer interrupt to start receive/response */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN;
-		/* Clear ADDR bit */
-		unused = STM32_I2C_SR1(port);
-		unused = STM32_I2C_SR2(port);
-		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* I2C in peripheral transmitter */
-	if (i2c_sr2 & STM32_I2C_SR2_TRA) {
-		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_TXE)) {
-			if (tx_pending) {
-				if (tx_index < tx_end) {
-					STM32_I2C_DR(port) =
-						host_buffer[tx_index++];
-				} else {
-					STM32_I2C_DR(port) = 0xec;
-					tx_index = 0;
-					tx_end = 0;
-					tx_pending = 0;
-				}
-			} else if (rx_pending) {
-				host_i2c_resp_port = port;
-				/* Disable buffer interrupt */
-				STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-				if ((addr_8bit >> 1) ==
-				    I2C_STRIP_FLAGS(
-					    CONFIG_BOARD_I2C_ADDR_FLAGS))
-					i2c_process_board_command(1, addr_8bit,
-								  buf_idx);
-				else
-#endif
-					i2c_process_command();
-				/* Reset host buffer */
-				rx_pending = 0;
-				tx_pending = 1;
-			} else {
-				STM32_I2C_DR(port) = 0xec;
-			}
-		}
-	} else { /* I2C in peripheral receiver */
-		if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_RXNE))
-			host_buffer[buf_idx++] = STM32_I2C_DR(port);
-	}
-
-	/* STOPF or AF */
-	if (i2c_sr1 & (STM32_I2C_SR1_STOPF | STM32_I2C_SR1_AF)) {
-		/* Disable buffer interrupt */
-		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
-
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-		if (rx_pending &&
-		    (addr_8b >> 1) ==
-		    I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS))
-			i2c_process_board_command(0, addr_8bit, buf_idx);
-#endif
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Clear AF */
-		STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF;
-		/* Clear STOPF: read SR1 and write CR1 */
-		unused = STM32_I2C_SR1(port);
-		STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/* Enable again */
-	if (!(i2c_cr1 & STM32_I2C_CR1_PE))
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-}
-void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2);
-DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2);
-#endif
-
-
-/* Init all available i2c ports */
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	/* Enable ACK */
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK;
-	/* Enable interrupts */
-	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN
-			| STM32_I2C_CR2_ITERREN;
-	/* Setup host command peripheral */
-	STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14
-		| (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-	STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL
-		| (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1);
-#endif
-	task_enable_irq(IRQ_PERIPHERAL_EV);
-	task_enable_irq(IRQ_PERIPHERAL_ER);
-#endif
-}
diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c
deleted file mode 100644
index eb1c7f1560..0000000000
--- a/chip/stm32/i2c-stm32g4.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER   (10 * MSEC)
-
-enum i2c_freq_khz {
-	freq_100 = 100,
-	freq_400 = 400,
-	freq_1000 = 1000,
-};
-
-struct i2c_timing {
-	uint8_t scll;
-	uint8_t sclh;
-	uint8_t sdadel;
-	uint8_t scldel;
-	uint8_t presc;
-};
-
-/* timing register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/*
- * The following timing config values are given in Table 371 of TM0440 which
- * assumes an I2CCLK freq of 16 MHZ. I2CCLK is connected to HSI, with is @
- * 16MHz. The TRM recommends using the STM32CubeMX tool to get more accurate
- * values. Note that the actual clock period is (scll + 1) + (schl + 1) +
- * internal detection delays for SCL being low/high.
- */
-const struct i2c_timing i2c_timingr[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = {
-		.scll = 4,
-		.sclh = 2,
-		.sdadel = 0,
-		.scldel = 2,
-		.presc = 0,
-	},
-		[I2C_FREQ_400KHZ] = {
-		.scll = 9,
-		.sclh = 4,
-		.sdadel = 2,
-		.scldel = 3,
-		.presc = 1,
-	},
-		[I2C_FREQ_100KHZ] = {
-		.scll = 19,
-		.sclh = 15,
-		.sdadel = 2,
-		.scldel = 4,
-		.presc = 3,
-	},
-};
-
-/*
- * For G4, I2C1 and I2C2 are contiguous in address space, but I2C3 and I2C4 are
- * at different offsets. In order to make the driver code easier, the base
- * address for each port's register block is defined here and can be used in i2c
- * register read/write accesses.
- */
-static const uint32_t i2c_regs_base[] = {
-	STM32_I2C1_BASE,
-	STM32_I2C2_BASE,
-	STM32_I2C3_BASE,
-	STM32_I2C4_BASE,
-};
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
-}
-
-/**
- * Set i2c clock rate..
- *
- * @param p		I2C port struct
- */
-static void i2c_set_timingr_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t base;
-	int index;
-	uint32_t timingr;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	/*
-	 * To configure an I2C port frequency requires 5 values. scll, sclh,
-	 * sdadel, scldel, and presc. With these settings, the actual SCL period
-	 * (Tscl) is given by:
-	 *     Tscl = Tsync1 + Tsync2 + [(scll+1) + (sclh+1)] * presc * Ti2clck
-	 *
-	 * Using HSI for i2cclk, so this is fixed @ 16MHz. The recommended
-	 * values for the 5 parameters are from the TRM for i2clck @ 16 MHZ.
-	 * Note that Tsyncx is a function of SCL rise/fall times and filtering
-	 * selected for the given I2C port. sdadel and scldel affect when data
-	 * is written or read relative to SCL edges.
-	 */
-
-	if (p->kbps == freq_100) {
-		index = I2C_FREQ_100KHZ;
-	} else if (p->kbps == freq_400) {
-		index = I2C_FREQ_400KHZ;
-	} else if (p->kbps == freq_400) {
-		index = I2C_FREQ_1000KHZ;
-	} else {
-		index = I2C_FREQ_100KHZ;
-		CPRINTS("stm32 i2c[p%d]: Invalid freq, setting 100Khz instead!",
-			port);
-	}
-	/* Assemble write value for timingr register */
-	timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) |
-		(i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
-		(i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
-		(i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
-		(i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
-
-	/* Write timingr value */
-	STM32_I2C_TIMINGR(base) = timingr;
-
-	/* Save freq lookup index for polling loop delay */
-	pdata[port].freq = index;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	/*
-	 * The I2C module clock can be derived from sysclk, hsi16, or pclk1.
-	 * CrosEC will typically have sysclk = pclk = cpuclk. hsi16 is fixed at
-	 * 16 Mhz and given that it's a known freq, the timing register values
-	 * can be obtained via table lookup. The I2C clock source is selected
-	 * via the I2CnSEL field for a given I2C port.
-	 *
-	 * I2CnSEL is a 2 bit field in same register for ports 0-2 (1-3 in
-	 * STM32 notation), but is in a different register for port 3.
-	 */
-	if (port < 3) {
-		int clksel;
-		int mask;
-		int shift;
-
-		shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + 2 * port;
-		mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift;
-		clksel = STM32_RCC_CCIPR;
-		clksel &= ~mask;
-		STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI
-					    << shift);
-	} else if (port == 3) {
-		/* i2c4sel is bits 1:0, no shift required */
-		STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK;
-		STM32_RCC_CCIPR2 |= STM32_RCC_CCIPR_I2CNSEL_HSI;
-	}
-
-	/*
-	 * Software reset for an I2C port is performed by clearing the PE bit in
-	 * that port's CR1 register. When this happens, SCL and SDA are
-	 * released, internal stame machines are reset, control/status bits are
-	 * also reset. The I2C block reset requires 3 APB cycles before setting
-	 * PE back to 1. This wait is ensured by the call fo i2c_set_freq_port.
-	 */
-	STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE;
-	/* Set up initial bus frequencies */
-	i2c_set_timingr_port(p);
-	/* Enable the I2C port */
-	STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE;
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-}
-
-/*****************************************************************************/
-/* Interface */
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	do {
-		int isr = STM32_I2C_ISR(base);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			   STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/*****************************************************************************
- * Exported functions declared in i2c.h
- */
-/* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-	uint32_t base;
-
-	ASSERT(port < I2C_PORT_COUNT);
-	base = i2c_regs_base[port];
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(base) = 0;
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(base) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-			in[i] = STM32_I2C_RXDR(base);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(base) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(base) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(base) = 0;
-		STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-#ifdef CONFIG_I2C_CONTROLLER
-/* Handle an upcoming frequency change. */
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-/* Handle a frequency change */
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/*
-	 * Handle CPU clock changing frequency and unlock I2C ports we locked
-	 * in pre-freq change hook
-	 */
-	for (i = 0; i < i2c_ports_used; i++, p++) {
-		i2c_set_timingr_port(p);
-		i2c_lock(p->port, 0);
-	}
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-
-/* Init all available i2c ports */
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Configure GPIO alt-func for all I2C ports */
-	gpio_config_module(MODULE_I2C, 1);
-	/* Enable the I2C clock for all I2C ports */
-	clock_enable_module(MODULE_I2C, 1);
-	/* Per port configuration */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-}
diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c
deleted file mode 100644
index 2edcb1c0b6..0000000000
--- a/chip/stm32/i2c-stm32l.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
-
-/*
- * Transmit timeout in microseconds
- *
- * In theory we shouldn't have a timeout here (at least when we're in slave
- * mode).  The slave is supposed to wait forever for the master to read bytes.
- * ...but we're going to keep the timeout to make sure we're robust.  It may in
- * fact be needed if the host resets itself mid-read.
- *
- * NOTE: One case where this timeout is useful is when the battery
- * flips out.  The battery may flip out and hold lines low for up to
- * 25ms.  If we just wait it will eventually let them go.
- */
-#define I2C_TX_TIMEOUT_MASTER	(30 * MSEC)
-
-/*
- * Delay 5us in bitbang mode.  That gives us roughly 5us low and 5us high or
- * a frequency of 100kHz.
- */
-#define I2C_BITBANG_HALF_CYCLE_US    5
-
-#ifdef CONFIG_I2C_DEBUG
-static void dump_i2c_reg(int port, const char *what)
-{
-	CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s",
-		STM32_I2C_CR1(port),
-		STM32_I2C_CR2(port),
-		STM32_I2C_SR1(port),
-		STM32_I2C_SR2(port),
-		what);
-}
-#else
-static inline void dump_i2c_reg(int port, const char *what)
-{
-}
-#endif
-
-/**
- * Wait for SR1 register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_sr1(int port, int mask)
-{
-	uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
-
-	while (get_time().val < timeout) {
-		int sr1 = STM32_I2C_SR1(port);
-
-		/* Check for errors */
-		if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR |
-			   STM32_I2C_SR1_AF)) {
-			dump_i2c_reg(port, "wait_sr1 failed");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Check for desired mask */
-		if ((sr1 & mask) == mask)
-			return EC_SUCCESS;
-
-		/* I2C is slow, so let other things run while we wait */
-		usleep(100);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/**
- * Send a start condition and slave address on the specified port.
- *
- * @param port		I2C port
- * @param slave_addr	Slave address, with LSB set for receive-mode
- *
- * @return Non-zero if error.
- */
-static int send_start(int port, uint16_t slave_addr_8bit)
-{
-	int rv;
-
-	/* Send start bit */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_START;
-	dump_i2c_reg(port, "sent start");
-	rv = wait_sr1(port, STM32_I2C_SR1_SB);
-	if (rv)
-		return I2C_ERROR_FAILED_START;
-
-	/* Write slave address */
-	STM32_I2C_DR(port) = slave_addr_8bit & 0xff;
-	rv = wait_sr1(port, STM32_I2C_SR1_ADDR);
-	if (rv)
-		return rv;
-
-	/* Read SR2 to clear ADDR bit */
-	rv = STM32_I2C_SR2(port);
-
-	dump_i2c_reg(port, "wrote addr");
-
-	return EC_SUCCESS;
-}
-
-static void i2c_set_freq_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	int freq = clock_get_freq();
-
-	/* Force peripheral reset and disable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST;
-	STM32_I2C_CR1(port) = 0;
-
-	/* Set clock frequency */
-	STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
-	STM32_I2C_CR2(port) = freq / SECOND;
-	STM32_I2C_TRISE(port) = freq / SECOND + 1;
-
-	/* Enable port */
-	STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-
-	/* Enable clocks to I2C modules if necessary */
-	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
-		STM32_RCC_APB1ENR |= 1 << (21 + port);
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p);
-}
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port,
-		  const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int started = (flags & I2C_XFER_START) ? 0 : 1;
-	int rv = EC_SUCCESS;
-	int i;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	dump_i2c_reg(port, "xfer start");
-
-	/*
-	 * Clear status
-	 *
-	 * TODO(crosbug.com/p/29314): should check for any leftover error
-	 * status, and reset the port if present.
-	 */
-	STM32_I2C_SR1(port) = 0;
-
-	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
-
-	/* No out bytes and no in bytes means just check for active */
-	if (out_bytes || !in_bytes) {
-		if (!started) {
-			rv = send_start(port, addr_8bit);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* Write data, if any */
-		for (i = 0; i < out_bytes; i++) {
-			/* Write next data byte */
-			STM32_I2C_DR(port) = out[i];
-			dump_i2c_reg(port, "wrote data");
-
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		/* Need repeated start condition before reading */
-		started = 0;
-
-		/* If no input bytes, queue stop condition */
-		if (!in_bytes && (flags & I2C_XFER_STOP))
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-	}
-
-	if (in_bytes) {
-		/* Setup ACK/POS before sending start as per user manual */
-		if (in_bytes == 2)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS;
-		else if (in_bytes != 1)
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK;
-
-		if (!started) {
-			rv = send_start(port, addr_8bit | 0x01);
-			if (rv)
-				goto xfer_exit;
-		}
-
-		if (in_bytes == 1) {
-			/* Set stop immediately after ADDR cleared */
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[0] = STM32_I2C_DR(port);
-		} else if (in_bytes == 2) {
-			/* Wait till the shift register is full */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			in[0] = STM32_I2C_DR(port);
-			in[1] = STM32_I2C_DR(port);
-		} else {
-			/* Read all but last three */
-			for (i = 0; i < in_bytes - 3; i++) {
-				/* Wait for receive buffer not empty */
-				rv = wait_sr1(port, STM32_I2C_SR1_RXNE);
-				if (rv)
-					goto xfer_exit;
-
-				dump_i2c_reg(port, "read data");
-				in[i] = STM32_I2C_DR(port);
-				dump_i2c_reg(port, "post read data");
-			}
-
-			/* Wait for BTF (data N-2 in DR, N-1 in shift) */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			/* No more acking */
-			STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK;
-			in[i++] = STM32_I2C_DR(port);
-
-			/* Wait for BTF (data N-1 in DR, N in shift) */
-			rv = wait_sr1(port, STM32_I2C_SR1_BTF);
-			if (rv)
-				goto xfer_exit;
-
-			/* If this is the last byte, queue stop condition */
-			if (flags & I2C_XFER_STOP)
-				STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-
-			/* Read the last two bytes */
-			in[i++] = STM32_I2C_DR(port);
-			in[i++] = STM32_I2C_DR(port);
-		}
-	}
-
- xfer_exit:
-	/* On error, queue a stop condition */
-	if (rv) {
-		flags |= I2C_XFER_STOP;
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP;
-		dump_i2c_reg(port, "stop after error");
-
-		/*
-		 * If failed at sending start, try resetting the port
-		 * to unwedge the bus.
-		 */
-		if (rv == I2C_ERROR_FAILED_START) {
-			const struct i2c_port_t *p = i2c_ports;
-			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
-
-			i2c_unwedge(port);
-
-			for (i = 0; i < i2c_ports_used; i++, p++) {
-				if (p->port == port) {
-					i2c_init_port(p);
-					break;
-				}
-			}
-		}
-	}
-
-	/* If a stop condition is queued, wait for it to take effect */
-	if (flags & I2C_XFER_STOP) {
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-/* Handle CPU clock changing frequency */
-static void i2c_freq_change(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_set_freq_port(p);
-}
-
-static void i2c_pre_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	/* Lock I2C ports so freq change can't interrupt an I2C transaction */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 1);
-}
-DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT);
-static void i2c_freq_change_hook(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	i2c_freq_change();
-
-	/* Unlock I2C ports we locked in pre-freq change hook */
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_lock(p->port, 0);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_i2cdump(int argc, char **argv)
-{
-	dump_i2c_reg(I2C_PORT_MASTER, "dump");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump,
-			NULL,
-			"Dump I2C regs");
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
deleted file mode 100644
index 5997ed5b70..0000000000
--- a/chip/stm32/i2c-stm32l4.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "printf.h"
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "registers.h"
-
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#define I2C_SLAVE_ERROR_CODE	0xec
-#if (I2C_PORT_EC == STM32_I2C1_PORT)
-#define IRQ_SLAVE STM32_IRQ_I2C1
-#else
-#define IRQ_SLAVE STM32_IRQ_I2C2
-#endif
-#endif
-
-/* I2C port state data */
-struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
-};
-static struct i2c_port_data pdata[I2C_PORT_COUNT];
-
-void i2c_set_timeout(int port, uint32_t timeout)
-{
-	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
-}
-
-/* timing register values for supported input clks / i2c clk rates */
-static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
-	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
-};
-
-/**
- * Wait for ISR register to contain the specified mask.
- *
- * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
- * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
- */
-static int wait_isr(int port, int mask)
-{
-	uint32_t start = __hw_clock_source_read();
-	uint32_t delta = 0;
-
-	do {
-		int isr = STM32_I2C_ISR(port);
-
-		/* Check for errors */
-		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
-			return EC_ERROR_UNKNOWN;
-
-		/* Check for desired mask */
-		if ((isr & mask) == mask)
-			return EC_SUCCESS;
-
-		delta = __hw_clock_source_read() - start;
-
-		/**
-		 * Depending on the bus speed, busy loop for a while before
-		 * sleeping and letting other things run.
-		 */
-		if (delta >= busyloop_us[pdata[port].freq])
-			usleep(100);
-	} while (delta < pdata[port].timeout_us);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Supported i2c input clocks */
-enum stm32_i2c_clk_src {
-	I2C_CLK_SRC_48MHZ = 0,
-	I2C_CLK_SRC_16MHZ = 1,
-	I2C_CLK_SRC_COUNT,
-};
-
-/* timing register values for supported input clks / i2c clk rates
- *
- * These values are calculated using ST's STM32cubeMX tool
- */
-static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
-	[I2C_CLK_SRC_48MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x20000209,
-		[I2C_FREQ_400KHZ] = 0x2010091A,
-		[I2C_FREQ_100KHZ] = 0x20303E5D,
-	},
-	[I2C_CLK_SRC_16MHZ] = {
-		[I2C_FREQ_1000KHZ] = 0x00000107,
-		[I2C_FREQ_400KHZ] = 0x00100B15,
-		[I2C_FREQ_100KHZ] = 0x00303D5B,
-	},
-};
-
-static void i2c_set_freq_port(const struct i2c_port_t *p,
-			      enum stm32_i2c_clk_src src,
-			      enum i2c_freq freq)
-{
-	int port = p->port;
-
-	/* Disable port */
-	STM32_I2C_CR1(port) = 0;
-	STM32_I2C_CR2(port) = 0;
-	/* Set clock frequency */
-	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
-	/* Enable port */
-	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
-
-	pdata[port].freq = freq;
-}
-
-/**
- * Initialize on the specified I2C port.
- *
- * @param p		the I2c port
- */
-static void i2c_init_port(const struct i2c_port_t *p)
-{
-	int port = p->port;
-	uint32_t val;
-	enum i2c_freq freq;
-	enum stm32_i2c_clk_src src = I2C_CLK_SRC_16MHZ;
-
-	/* Enable I2C clock */
-	if (!(STM32_RCC_APB1ENR1 & (1 << (21 + port))))
-		STM32_RCC_APB1ENR1 |= 1 << (21 + port);
-
-	/*	Select HSI 16MHz as I2C clock source	*/
-	val = STM32_RCC_CCIPR;
-	val &= ~(STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2));
-	val |= STM32_RCC_CCIPR_I2C_HSI16
-	       << (STM32_RCC_CCIPR_I2C1SEL_SHIFT + port * 2);
-	STM32_RCC_CCIPR = val;
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_I2C, 1);
-
-	/* Set clock frequency */
-	switch (p->kbps) {
-	case 1000:
-		STM32_SYSCFG_CFGR1 |= STM32_SYSCFG_I2CFMP(port);
-		freq = I2C_FREQ_1000KHZ;
-		break;
-	case 400:
-		freq = I2C_FREQ_400KHZ;
-		break;
-	case 100:
-		freq = I2C_FREQ_100KHZ;
-		break;
-	default: /* unknown speed, defaults to 100kBps */
-		CPRINTS("I2C bad speed %d kBps", p->kbps);
-		freq = I2C_FREQ_100KHZ;
-	}
-
-	/* Set up initial bus frequencies */
-	i2c_set_freq_port(p, src, freq);
-
-	/* Set up default timeout */
-	i2c_set_timeout(port, 0);
-}
-
-/*****************************************************************************/
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-
-static void i2c_event_handler(int port)
-{
-	/* Variables tracking the handler state.
-	 * TODO: Should have as many sets of these variables as the number
-	 * of slave ports.
-	 */
-	static int rx_pending, rx_idx;
-	static int tx_pending, tx_idx, tx_end;
-	static uint8_t slave_buffer[I2C_MAX_HOST_PACKET_SIZE + 2];
-	int isr = STM32_I2C_ISR(port);
-
-	/*
-	 * Check for error conditions. Note, arbitration loss and bus error
-	 * are the only two errors we can get as a slave allowing clock
-	 * stretching and in non-SMBus mode.
-	 */
-	if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
-		rx_pending = 0;
-		tx_pending = 0;
-
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
-				| STM32_I2C_ICR_ARLOCF;
-	}
-
-	/* Transfer matched our slave address */
-	if (isr & STM32_I2C_ISR_ADDR) {
-		if (isr & STM32_I2C_ISR_DIR) {
-			/* Transmitter slave */
-			/* Clear transmit buffer */
-			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
-
-			if (rx_pending)
-				/* RESTART */
-				i2c_data_received(port, slave_buffer, rx_idx);
-			tx_end = i2c_set_response(port, slave_buffer, rx_idx);
-			tx_idx = 0;
-			rx_pending = 0;
-			tx_pending = 1;
-
-			/* Enable txis interrupt to start response */
-			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
-		} else {
-			/* Receiver slave */
-			rx_idx = 0;
-			rx_pending = 1;
-			tx_pending = 0;
-		}
-
-		/* Clear ADDR bit by writing to ADDRCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
-		/* Inhibit stop mode when addressed until STOPF flag is set */
-		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	/*
-	 * Receive buffer not empty
-	 *
-	 * When a master finishes sending data, it'll set STOP bit. It causes
-	 * the slave to receive RXNE and STOP interrupt at the same time. So,
-	 * we need to process RXNE first, then handle STOP.
-	 */
-	if (isr & STM32_I2C_ISR_RXNE)
-		slave_buffer[rx_idx++] = STM32_I2C_RXDR(port);
-
-	/* Stop condition on bus */
-	if (isr & STM32_I2C_ISR_STOP) {
-		if (rx_pending)
-			i2c_data_received(port, slave_buffer, rx_idx);
-		tx_idx = 0;
-		tx_end = 0;
-		rx_pending = 0;
-		tx_pending = 0;
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-
-		/* Clear STOPF bit by writing to STOPCF bit */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
-
-		/* No longer inhibit deep sleep after stop condition */
-		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
-	}
-
-	if (isr & STM32_I2C_ISR_NACK) {
-		/* Make sure TXIS interrupt is disabled */
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
-		/* Clear NACK */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
-	}
-
-	/* Transmitter empty event */
-	if (isr & STM32_I2C_ISR_TXIS) {
-		if (port == I2C_PORT_EC) {
-			if (tx_pending) {
-				if (tx_idx < tx_end) {
-					STM32_I2C_TXDR(port) =
-						slave_buffer[tx_idx++];
-				} else {
-					STM32_I2C_TXDR(port)
-						= I2C_SLAVE_ERROR_CODE;
-					tx_idx = 0;
-					tx_end = 0;
-					tx_pending = 0;
-				}
-			} else {
-				STM32_I2C_TXDR(port) = I2C_SLAVE_ERROR_CODE;
-			}
-		}
-	}
-}
-
-void i2c_event_interrupt(void)
-{
-	i2c_event_handler(I2C_PORT_EC);
-}
-DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
-#endif
-
-/*****************************************************************************/
-/* Interface */
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1;
-	int rv = EC_SUCCESS;
-	int i;
-	int xfer_start = flags & I2C_XFER_START;
-	int xfer_stop = flags & I2C_XFER_STOP;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	/* Clear status */
-	if (xfer_start) {
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-		STM32_I2C_CR2(port) = 0;
-	}
-
-	if (out_bytes || !in_bytes) {
-		/*
-		 * Configure the write transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we are starting, then set START bit.
-		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < out_bytes; i++) {
-			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
-			if (rv)
-				goto xfer_exit;
-			/* Write next data byte */
-			STM32_I2C_TXDR(port) = out[i];
-		}
-	}
-	if (in_bytes) {
-		if (out_bytes) { /* wait for completion of the write */
-			rv = wait_isr(port, STM32_I2C_ISR_TC);
-			if (rv)
-				goto xfer_exit;
-		}
-		/*
-		 * Configure the read transfer: if we are stopping then set
-		 * AUTOEND bit to automatically set STOP bit after NBYTES.
-		 * if we are not stopping, set RELOAD bit so that we can load
-		 * NBYTES again. if we were just transmitting, we need to
-		 * set START bit to send (re)start and begin read transaction.
-		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
-
-		for (i = 0; i < in_bytes; i++) {
-			/* Wait for receive buffer not empty */
-			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
-			if (rv)
-				goto xfer_exit;
-
-			in[i] = STM32_I2C_RXDR(port);
-		}
-	}
-
-	/*
-	 * If we are stopping, then we already set AUTOEND and we should
-	 * wait for the stop bit to be transmitted. Otherwise, we set
-	 * the RELOAD bit and we should wait for transfer complete
-	 * reload (TCR).
-	 */
-	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
-	if (rv)
-		goto xfer_exit;
-
-xfer_exit:
-	/* clear status */
-	if (xfer_stop)
-		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
-
-	/* On error, queue a stop condition */
-	if (rv) {
-		/* queue a STOP condition */
-		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
-		/* wait for it to take effect */
-		/* Wait up to 100 us for bus idle */
-		for (i = 0; i < 10; i++) {
-			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
-				break;
-			udelay(10);
-		}
-
-		/*
-		 * Allow bus to idle for at least one 100KHz clock = 10 us.
-		 * This allows slaves on the bus to detect bus-idle before
-		 * the next start condition.
-		 */
-		udelay(10);
-		/* re-initialize the controller */
-		STM32_I2C_CR2(port) = 0;
-		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
-		udelay(10);
-		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
-	}
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g))
-		/* If no SCL pin is defined, return 1 to appear idle. */
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g))
-		/* If no SDA pin is defined, return 1 to appear idle. */
-		return 1;
-
-	return gpio_get_level(g);
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
-void i2c_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2c_init_port(p);
-
-#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
-	task_enable_irq(IRQ_SLAVE);
-#endif
-}
diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c
deleted file mode 100644
index 86cc1c6df2..0000000000
--- a/chip/stm32/i2c-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c-stm32l4.c"
diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c
deleted file mode 100644
index 916a8c364c..0000000000
--- a/chip/stm32/i2c_ite_flash_support.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* STM implementation for flashing ITE-based ECs over i2c */
-
-#include "i2c_ite_flash_support.h"
-#include "i2c.h"
-#include "registers.h"
-#include "time.h"
-
-/*
- * As of 2018-11-27 the default for both is 60 bytes.  These larger values allow
- * for reflashing of ITE EC chips over I2C
- * (https://issuetracker.google.com/79684405) in reasonably speedy fashion.  If
- * the EC firmware defaults are ever raised significantly, consider removing
- * these overrides.
- *
- * As of 2018-11-27 the actual maximum write size supported by the I2C-over-USB
- * protocol is (1<<12)-1, and the maximum read size supported is
- * (1<<15)-1.  However compile time assertions require that these values be
- * powers of 2 after overheads are included.  Thus, the write limit set here
- * /should/ be (1<<12)-4 and the read limit should be (1<<15)-6, however those
- * ideal limits are not actually possible because stm32 lacks sufficient
- * spare memory for them.  With symmetrical limits, the maximum that currently
- * fits is (1<<11)-4 write limit and (1<<11)-6 read limit, leaving 1404 bytes of
- * RAM available.
- *
- * However even with a sufficiently large write value here, the maximum that
- * actually works as of 2018-12-03 is 255 bytes.  Additionally, ITE EC firmware
- * image verification requires exactly 256 byte reads.  Thus the only useful
- * powers-of-2-minus-overhead limits to set here are (1<<9)-4 writes and
- * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of
- * RAM available with the default 60 byte limits.
- */
-#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4)
-#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4)
-#endif
-#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6)
-#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6)
-#endif
-
-/*
- * iteflash requires 256 byte reads for verifying ITE EC firmware.  Without this
- * the limit is CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE which is 255 for STM32F0 due
- * to an 8 bit field, per src/platform/ec/include/config.h comment.
- */
-#ifndef CONFIG_I2C_XFER_LARGE_TRANSFER
-#error Must define CONFIG_I2C_XFER_LARGE_TRANSFER
-#endif
-
-#define KHz 1000
-#define MHz (1000 * KHz)
-
-/*
- * These constants are values that one might want to try changing if
- * enable_ite_dfu stops working, or does not work on a new ITE EC chip revision.
- */
-
-#define ITE_DFU_I2C_CMD_ADDR_FLAGS 0x5A
-#define ITE_DFU_I2C_DATA_ADDR_FLAGS 0x35
-
-#define SMCLK_WAVEFORM_PERIOD_HZ (100 * KHz)
-#define SMDAT_WAVEFORM_PERIOD_HZ (200 * KHz)
-
-#define START_DELAY_MS 5
-#define SPECIAL_WAVEFORM_MS 50
-#define PLL_STABLE_MS 10
-
-/*
- * Digital line levels to hold before (PRE_) or after (POST_) sending the
- * special waveforms.  0 for low, 1 for high.
- */
-#define SMCLK_PRE_LEVEL 0
-#define SMDAT_PRE_LEVEL 0
-#define SMCLK_POST_LEVEL 0
-#define SMDAT_POST_LEVEL 0
-
-/* The caller should hold the i2c_lock() for ite_dfu_config.i2c_port. */
-static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output)
-{
-	/*
-	 * Ideally the write and read would be done in one I2C transaction, as
-	 * is normally done when reading from the same I2C address that the
-	 * write was sent to.  The ITE EC is abnormal in that regard, with its
-	 * different 7-bit addresses for writes vs reads.
-	 *
-	 * i2c_xfer() does not support that.  Its I2C_XFER_START and
-	 * I2C_XFER_STOP flag bits do not cleanly support that scenario, they
-	 * are for continuing transfers without either of STOP or START
-	 * in-between.
-	 *
-	 * For what it's worth, the iteflash.c FTDI-based implementation of this
-	 * does the same thing, issuing a STOP between the write and read.  This
-	 * works, even if perhaps it should not.
-	 */
-	int ret;
-	/* Tell the ITE EC which register we want to read. */
-	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_CMD_ADDR_FLAGS,
-				&register_offset, sizeof(register_offset),
-				NULL, 0, I2C_XFER_SINGLE);
-	if (ret != EC_SUCCESS)
-		return ret;
-	/* Read in the 1 byte register value. */
-	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_DATA_ADDR_FLAGS,
-				NULL, 0,
-				output, sizeof(*output), I2C_XFER_SINGLE);
-	return ret;
-}
-
-/* Helper function to read ITE chip ID, for verifying ITE DFU mode. */
-static int cprint_ite_chip_id(void)
-{
-	/*
-	 * Per i2c_read8() implementation, use an array even for single byte
-	 * reads to ensure alignment for DMA on STM32.
-	 */
-	uint8_t chipid1[1];
-	uint8_t chipid2[1];
-	uint8_t chipver[1];
-
-	int ret;
-	int chip_version;
-	int flash_kb;
-
-	i2c_lock(ite_dfu_config.i2c_port, 1);
-
-	/* Read the CHIPID1 register. */
-	ret = ite_i2c_read_register(0x00, chipid1);
-	if (ret != EC_SUCCESS)
-		goto unlock;
-
-	/* Read the CHIPID2 register. */
-	ret = ite_i2c_read_register(0x01, chipid2);
-	if (ret != EC_SUCCESS)
-		goto unlock;
-
-	/* Read the CHIPVER register. */
-	ret = ite_i2c_read_register(0x02, chipver);
-
-unlock:
-	i2c_lock(ite_dfu_config.i2c_port, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Compute chip version and embedded flash size from the CHIPVER value.
-	 *
-	 * Chip version is mapping from bit 3-0
-	 * Flash size is mapping from bit 7-4
-	 *
-	 * Chip Version (bits 3-0)
-	 * 0: AX
-	 * 1: BX
-	 * 2: CX
-	 * 3: DX
-	 *
-	 * CX or prior flash size (bits 7-4)
-	 * 0:128KB
-	 * 4:192KB
-	 * 8:256KB
-	 *
-	 * DX flash size (bits 7-4)
-	 * 0:128KB
-	 * 2:192KB
-	 * 4:256KB
-	 * 6:384KB
-	 * 8:512KB
-	 */
-	chip_version = chipver[0] & 0x07;
-	if (chip_version < 0x3) {
-		/* Chip version is CX or earlier. */
-		switch (chipver[0] >> 4) {
-		case 0:
-			flash_kb = 128;
-			break;
-		case 4:
-			flash_kb = 192;
-			break;
-		case 8:
-			flash_kb = 256;
-			break;
-		default:
-			flash_kb = -2;
-		}
-	} else if (chip_version == 0x3) {
-		/* Chip version is DX. */
-		switch (chipver[0] >> 4) {
-		case 0:
-			flash_kb = 128;
-			break;
-		case 2:
-			flash_kb = 192;
-			break;
-		case 4:
-			flash_kb = 256;
-			break;
-		case 6:
-			flash_kb = 384;
-			break;
-		case 8:
-			flash_kb = 512;
-			break;
-		default:
-			flash_kb = -3;
-		}
-	} else {
-		/* Unrecognized chip version. */
-		flash_kb = -1;
-	}
-
-	ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ",
-		chipid1[0], chipid2[0], chipver[0]);
-	ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10);
-
-	/*
-	 * IT8320_eflash_SMBus_Programming_Guide.pdf says it is an error if
-	 * CHIPID1 != 0x83.
-	 */
-	if (chipid1[0] != 0x83)
-		ret = EC_ERROR_HW_INTERNAL;
-
-	return ret;
-}
-
-/* Enable ITE direct firmware update (DFU) mode. */
-static int command_enable_ite_dfu(int argc, char **argv)
-{
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Ensure we can perform the dfu operation */
-	if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow())
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Enable peripheral clocks. */
-	STM32_RCC_APB2ENR |=
-		STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN;
-
-	/* Reset timer registers which are not otherwise set below. */
-	STM32_TIM_CR2(16) = 0x0000;
-	STM32_TIM_CR2(17) = 0x0000;
-	STM32_TIM_DIER(16) = 0x0000;
-	STM32_TIM_DIER(17) = 0x0000;
-	STM32_TIM_SR(16) = 0x0000;
-	STM32_TIM_SR(17) = 0x0000;
-	STM32_TIM_CNT(16) = 0x0000;
-	STM32_TIM_CNT(17) = 0x0000;
-	STM32_TIM_RCR(16) = 0x0000;
-	STM32_TIM_RCR(17) = 0x0000;
-	STM32_TIM_DCR(16) = 0x0000;
-	STM32_TIM_DCR(17) = 0x0000;
-	STM32_TIM_DMAR(16) = 0x0000;
-	STM32_TIM_DMAR(17) = 0x0000;
-
-	/* Prescale to 1 MHz and use ARR to achieve NNN KHz periods. */
-	/* This approach is seen in STM's documentation. */
-	STM32_TIM_PSC(16) = (CPU_CLOCK / MHz) - 1;
-	STM32_TIM_PSC(17) = (CPU_CLOCK / MHz) - 1;
-
-	/* Set the waveform periods based on 1 MHz prescale. */
-	STM32_TIM_ARR(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) - 1;
-	STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1;
-
-	/* Set output compare 1 mode to PWM mode 1 and enable preload. */
-	STM32_TIM_CCMR1(16) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-	STM32_TIM_CCMR1(17) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-
-	/*
-	 * Enable output compare 1 (or its N counterpart). Note that if only
-	 * OC1N is enabled, then it is not complemented. From datasheet:
-	 * "When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented"
-	 *
-	 * Note: we want the rising edge of SDA to be in the middle of SCL, so
-	 * invert the SDA (faster) signal.
-	 */
-	if (ite_dfu_config.use_complement_timer_channel) {
-		STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1NE;
-		STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1NE |
-				     STM32_TIM_CCER_CC1NP;
-	} else {
-		STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1E;
-		STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P;
-	}
-
-	/* Enable main output. */
-	STM32_TIM_BDTR(16) = STM32_TIM_BDTR_MOE;
-	STM32_TIM_BDTR(17) = STM32_TIM_BDTR_MOE;
-
-	/* Update generation (reinitialize counters). */
-	STM32_TIM_EGR(16) = STM32_TIM_EGR_UG;
-	STM32_TIM_EGR(17) = STM32_TIM_EGR_UG;
-
-	/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
-	STM32_TIM_CCR1(16) = SMCLK_PRE_LEVEL ? 0xFFFF : 0x0000;
-	STM32_TIM_CCR1(17) = SMDAT_PRE_LEVEL ? 0xFFFF : 0x0000;
-
-	/* Enable timer counters. */
-	STM32_TIM_CR1(16) = STM32_TIM_CR1_CEN;
-	STM32_TIM_CR1(17) = STM32_TIM_CR1_CEN;
-
-	/* Set GPIO to alternate mode TIM(16|17)_CH1(N)? */
-	gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.scl, 1);
-	gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.sda, 1);
-
-	msleep(START_DELAY_MS);
-
-	/* Set pulse width to half of waveform period. */
-	STM32_TIM_CCR1(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) / 2;
-	STM32_TIM_CCR1(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) / 2;
-
-	msleep(SPECIAL_WAVEFORM_MS);
-
-	/* Set duty cycle to 0% or 100%, pinning each channel low or high. */
-	STM32_TIM_CCR1(16) = SMCLK_POST_LEVEL ? 0xFFFF : 0x0000;
-	STM32_TIM_CCR1(17) = SMDAT_POST_LEVEL ? 0xFFFF : 0x0000;
-
-	msleep(PLL_STABLE_MS);
-
-	/* Set GPIO back to alternate mode I2C. */
-	gpio_config_pin(MODULE_I2C, ite_dfu_config.scl, 1);
-	gpio_config_pin(MODULE_I2C, ite_dfu_config.sda, 1);
-
-	/* Disable timer counters. */
-	STM32_TIM_CR1(16) = 0x0000;
-	STM32_TIM_CR1(17) = 0x0000;
-
-	/* Disable peripheral clocks. */
-	STM32_RCC_APB2ENR &=
-		~(STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN);
-
-	return cprint_ite_chip_id();
-}
-DECLARE_CONSOLE_COMMAND(
-	enable_ite_dfu, command_enable_ite_dfu, "",
-	"Enable ITE Direct Firmware Update (DFU) mode");
-
-/* Read ITE chip ID.  Can be used to verify ITE DFU mode. */
-static int command_get_ite_chipid(int argc, char **argv)
-{
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Ensure we can perform the dfu operation */
-	if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow())
-		return EC_ERROR_ACCESS_DENIED;
-
-	return cprint_ite_chip_id();
-}
-DECLARE_CONSOLE_COMMAND(
-	get_ite_chipid, command_get_ite_chipid, "",
-	"Read ITE EC chip ID, version, flash size (must be in DFU mode)");
diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c
deleted file mode 100644
index 219676968a..0000000000
--- a/chip/stm32/keyboard_raw.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for STM32
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of external interrupts on input lines */
-static unsigned int irq_mask;
-
-static const uint32_t kb_out_ports[] = { KB_OUT_PORT_LIST };
-
-static void set_irq_mask(void)
-{
-	int i;
-
-	for (i = GPIO_KB_IN00; i < GPIO_KB_IN00 + KEYBOARD_ROWS; i++)
-		irq_mask |= gpio_list[i].mask;
-}
-
-void keyboard_raw_init(void)
-{
-	/* Determine EXTI_PR mask to use for the board */
-	set_irq_mask();
-
-	/* Ensure interrupts are disabled in EXTI_PR */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/* Enable interrupts for keyboard matrix inputs */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-	gpio_enable_interrupt(GPIO_KB_IN01);
-	gpio_enable_interrupt(GPIO_KB_IN02);
-	gpio_enable_interrupt(GPIO_KB_IN03);
-	gpio_enable_interrupt(GPIO_KB_IN04);
-	gpio_enable_interrupt(GPIO_KB_IN05);
-	gpio_enable_interrupt(GPIO_KB_IN06);
-	gpio_enable_interrupt(GPIO_KB_IN07);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	int i, done = 0;
-
-	for (i = 0; i < ARRAY_SIZE(kb_out_ports); i++) {
-		uint32_t bsrr = 0;
-		int j;
-
-		for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) {
-			if (gpio_list[j].port != kb_out_ports[i])
-				continue;
-
-			if (out == KEYBOARD_COLUMN_ALL) {
-				/* drive low (clear bit) */
-				bsrr |= gpio_list[j].mask << 16;
-			} else if (out == KEYBOARD_COLUMN_NONE) {
-				/* put output in hi-Z state (set bit) */
-				bsrr |= gpio_list[j].mask;
-			} else if (j - GPIO_KB_OUT00 == out) {
-				/*
-				 * Drive specified output low, others => hi-Z.
-				 *
-				 * To avoid conflict, tri-state all outputs
-				 * first, then assert specified output.
-				 */
-				keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-				bsrr |= gpio_list[j].mask << 16;
-				done = 1;
-				break;
-			}
-		}
-
-	#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-		if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask))
-			bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask);
-	#endif
-
-		if (bsrr)
-			STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr;
-
-		if (done)
-			break;
-	}
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	unsigned int port, prev_port = 0;
-	int state = 0;
-	uint16_t port_val = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		port = gpio_list[GPIO_KB_IN00 + i].port;
-		if (port != prev_port) {
-			port_val = STM32_GPIO_IDR(port);
-			prev_port = port;
-		}
-
-		if (port_val & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Assert all outputs would trigger un-wanted interrupts.
-		 * Clear them before enable interrupt.
-		 */
-		STM32_EXTI_PR |= irq_mask;
-		STM32_EXTI_IMR |= irq_mask;	/* 1: unmask interrupt */
-	} else {
-		STM32_EXTI_IMR &= ~irq_mask;	/* 0: mask interrupts */
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc
deleted file mode 100644
index 2381c511f2..0000000000
--- a/chip/stm32/memory_regions.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef CONFIG_USB_RAM_SIZE
-REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \
-       CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2)
-#endif /* CONFIG_USB_RAM_SIZE */
-#ifdef CHIP_VARIANT_STM32H7X3
-REGION(itcm,   wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */
-REGION(dtcm,   rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */
-REGION(ahb,    rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */
-REGION(ahb4,   rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */
-REGION(backup, rw, 0x38800000, 0x01000) /* Backup RAM: 4kB */
-#endif /* CHIP_VARIANT_STM32H7X3 */
diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c
deleted file mode 100644
index 45ce38d159..0000000000
--- a/chip/stm32/otp-stm32f4.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* OTP implementation for STM32F411 */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "otp.h"
-#include "registers.h"
-#include "util.h"
-
-/*
- * OTP is only used for saving the USB serial number.
- */
-#ifdef CONFIG_SERIALNO_LEN
-/* Which block to use */
-#define OTP_SERIAL_BLOCK 0
-#define OTP_SERIAL_ADDR \
-	REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
-
-/* Number of word used in the block */
-#define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t))
-BUILD_ASSERT(CONFIG_SERIALNO_LEN % sizeof(uint32_t) == 0);
-BUILD_ASSERT(OTP_SERIAL_BLOCK_SIZE < STM32_OTP_BLOCK_SIZE);
-
-/*
- * Write an OTP block
- *
- * @param block         block to write.
- * @param size          Number of words to write.
- * @param data          Destination buffer for data.
- */
-static int otp_write(uint8_t block, int size, const char *data)
-{
-	if (block >= STM32_OTP_BLOCK_NB)
-		return EC_ERROR_PARAM1;
-	if (size >= STM32_OTP_BLOCK_SIZE)
-		return EC_ERROR_PARAM2;
-	return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) -
-					 CONFIG_PROGRAM_MEMORY_BASE,
-					 size * sizeof(uint32_t), data);
-}
-
-/*
- * Check if an OTP block is protected.
- *
- * @param block        protected block.
- * @return non-zero if that block is read only.
- */
-static int otp_get_protect(uint8_t block)
-{
-	uint32_t lock;
-
-	lock = REG32(STM32_OTP_LOCK(block));
-	return ((lock & STM32_OPT_LOCK_MASK(block)) == 0);
-}
-
-/*
- * Set a particular OTP block as read only.
- *
- * @param block        block to protect.
- */
-static int otp_set_protect(uint8_t block)
-{
-	int rv;
-	uint32_t lock;
-
-	if (otp_get_protect(block))
-		return EC_SUCCESS;
-
-	lock = REG32(STM32_OTP_LOCK(block));
-	lock &= ~STM32_OPT_LOCK_MASK(block);
-	rv = crec_flash_physical_write(STM32_OTP_LOCK(block) -
-				       CONFIG_PROGRAM_MEMORY_BASE,
-				       sizeof(uint32_t), (char *)&lock);
-	if (rv)
-		return rv;
-	else
-		return EC_SUCCESS;
-}
-
-const char *otp_read_serial(void)
-{
-	int i;
-
-	for (i = 0; i < OTP_SERIAL_BLOCK_SIZE; i++) {
-		if (OTP_SERIAL_ADDR[i] != -1)
-			return (char *)OTP_SERIAL_ADDR;
-	}
-	return NULL;
-}
-
-int otp_write_serial(const char *serialno)
-{
-	int i, ret;
-	char otp_serial[CONFIG_SERIALNO_LEN];
-
-	if (otp_get_protect(OTP_SERIAL_BLOCK))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Copy in serialno. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN - 1; i++) {
-		otp_serial[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	for (; i < CONFIG_SERIALNO_LEN; i++)
-		otp_serial[i] = 0;
-
-	ret = otp_write(OTP_SERIAL_BLOCK, OTP_SERIAL_BLOCK_SIZE, otp_serial);
-	if (ret == EC_SUCCESS)
-		return otp_set_protect(OTP_SERIAL_BLOCK);
-	else
-		return ret;
-}
-#endif
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
deleted file mode 100644
index 508745199f..0000000000
--- a/chip/stm32/power_led.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Keyboard power button LED state machine.
- *
- * This sets up TIM_POWER_LED to drive the power button LED so that the duty
- * cycle can range from 0-100%. When the lid is closed or turned off, then the
- * PWM is disabled and the GPIO is reconfigured to minimize leakage voltage.
- *
- * In suspend mode, duty cycle transitions progressively slower from 0%
- * to 100%, and progressively faster from 100% back down to 0%. This
- * results in a breathing effect. It takes about 2sec for a full cycle.
- */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "power_led.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define LED_STATE_TIMEOUT_MIN	(15 * MSEC)  /* Minimum of 15ms per step */
-#define LED_HOLD_TIME		(330 * MSEC) /* Hold for 330ms at min/max */
-#define LED_STEP_PERCENT	4	/* Incremental value of each step */
-
-static enum powerled_state led_state = POWERLED_STATE_ON;
-static int power_led_percent = 100;
-
-void powerled_set_state(enum powerled_state new_state)
-{
-	led_state = new_state;
-	/* Wake up the task */
-	task_wake(TASK_ID_POWERLED);
-}
-
-static void power_led_set_duty(int percent)
-{
-	ASSERT((percent >= 0) && (percent <= 100));
-	power_led_percent = percent;
-	pwm_set_duty(PWM_CH_POWER_LED, percent);
-}
-
-static void power_led_use_pwm(void)
-{
-	pwm_enable(PWM_CH_POWER_LED, 1);
-	power_led_set_duty(100);
-}
-
-static void power_led_manual_off(void)
-{
-	pwm_enable(PWM_CH_POWER_LED, 0);
-
-	/*
-	 * Reconfigure GPIO as a floating input. Alternatively we could
-	 * configure it as an open-drain output and set it to high impedance,
-	 * but reconfiguring as an input had better results in testing.
-	 */
-	gpio_config_module(MODULE_POWER_LED, 0);
-}
-
-/**
- * Return the timeout period (in us) for the current step.
- */
-static int power_led_step(void)
-{
-	int state_timeout = 0;
-	static enum { DOWN = -1, UP = 1 } dir = UP;
-
-	if (0 == power_led_percent) {
-		dir = UP;
-		state_timeout = LED_HOLD_TIME;
-	} else if (100 == power_led_percent) {
-		dir = DOWN;
-		state_timeout = LED_HOLD_TIME;
-	} else {
-		/*
-		 * Decreases timeout as duty cycle percentage approaches
-		 * 0%, increase as it approaches 100%.
-		 */
-		state_timeout = LED_STATE_TIMEOUT_MIN +
-			LED_STATE_TIMEOUT_MIN * (power_led_percent / 33);
-	}
-
-	/*
-	 * The next duty cycle will take effect after the timeout has
-	 * elapsed for this duty cycle and the power LED task calls this
-	 * function again.
-	 */
-	power_led_set_duty(power_led_percent);
-	power_led_percent += dir * LED_STEP_PERCENT;
-
-	return state_timeout;
-}
-
-void power_led_task(void)
-{
-	while (1) {
-		int state_timeout = -1;
-
-		switch (led_state) {
-		case POWERLED_STATE_ON:
-			/*
-			 * "ON" implies driving the LED using the PWM with a
-			 * duty duty cycle of 100%. This produces a softer
-			 * brightness than setting the GPIO to solid ON.
-			 */
-			power_led_use_pwm();
-			power_led_set_duty(100);
-			state_timeout = -1;
-			break;
-		case POWERLED_STATE_OFF:
-			/* Reconfigure GPIO to disable the LED */
-			power_led_manual_off();
-			state_timeout = -1;
-			break;
-		case POWERLED_STATE_SUSPEND:
-			/* Drive using PWM with variable duty cycle */
-			power_led_use_pwm();
-			state_timeout = power_led_step();
-			break;
-		default:
-			break;
-		}
-
-		task_wait_event(state_timeout);
-	}
-}
-
-#define CONFIG_CMD_POWERLED
-#ifdef CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
-{
-	enum powerled_state state;
-
-	if (argc != 2)
-		return EC_ERROR_INVAL;
-
-	if (!strcasecmp(argv[1], "off"))
-		state = POWERLED_STATE_OFF;
-	else if (!strcasecmp(argv[1], "on"))
-		state = POWERLED_STATE_ON;
-	else if (!strcasecmp(argv[1], "suspend"))
-		state = POWERLED_STATE_SUSPEND;
-	else
-		return EC_ERROR_INVAL;
-
-	powerled_set_state(state);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-		"[off | on | suspend]",
-		"Change power LED state");
-#endif
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c
deleted file mode 100644
index 0b339399c9..0000000000
--- a/chip/stm32/pwm.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for STM32 */
-
-#include "clock.h"
-#include "clock-f.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-#include "registers.h"
-#include "system.h"
-#include "util.h"
-
-/* Bitmap of currently active PWM channels. 1 bit per channel. */
-static uint32_t using_pwm;
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-
-	ASSERT((percent >= 0) && (percent <= 100));
-	tim->ccr[pwm->channel] = percent;
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-	return tim->ccr[pwm->channel];
-}
-
-static void pwm_configure(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-	volatile unsigned *ccmr = NULL;
-	/* Default frequency = 100 Hz */
-	int frequency = pwm->frequency ? pwm->frequency : 100;
-	uint16_t ccer;
-
-	if (using_pwm & BIT(ch))
-		return;
-
-	/* Enable timer */
-	__hw_timer_enable_clock(pwm->tim.id, 1);
-
-	/* Disable counter during setup */
-	tim->cr1 = 0x0000;
-
-	/*
-	 * Timer clock / PSC determines how fast the counter operates.
-	 * ARR determines the wave period, CCRn determines duty cycle.
-	 * Thus, frequency = timer_freq / PSC / ARR. so:
-	 *
-	 * frequency = timer_freq / (timer_freq/10000 + 1) / (99 + 1) = 100 Hz.
-	 */
-	tim->psc = clock_get_timer_freq() / (frequency * 100) - 1;
-	tim->arr = 99;
-
-	if (pwm->channel <= 2) /* Channel ID starts from 1 */
-		ccmr = &tim->ccmr1;
-	else
-		ccmr = &tim->ccmr2;
-
-	/* Output, PWM mode 1, preload enable */
-	if (pwm->channel & 0x1)
-		*ccmr = (6 << 4) | BIT(3);
-	else
-		*ccmr = (6 << 12) | BIT(11);
-
-	/* Output enable. Set active high/low. */
-	if (pwm->flags & PWM_CONFIG_ACTIVE_LOW)
-		ccer = 3 << (pwm->channel * 4 - 4);
-	else
-		ccer = 1 << (pwm->channel * 4 - 4);
-
-	/* Enable complementary output, if present. */
-	if (pwm->flags & PWM_CONFIG_COMPLEMENTARY_OUTPUT)
-		ccer |= (ccer << 2);
-
-	tim->ccer = ccer;
-
-	/*
-	 * Main output enable.
-	 * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't
-	 * harmful on STM32L.
-	 */
-	tim->bdtr |= BIT(15);
-
-	/* Generate update event to force loading of shadow registers */
-	tim->egr |= 1;
-
-	/* Enable auto-reload preload, start counting */
-	tim->cr1 |= BIT(7) | BIT(0);
-
-	atomic_or(&using_pwm, 1 << ch);
-
-	/* Prevent sleep */
-	disable_sleep(SLEEP_MASK_PWM);
-}
-
-static void pwm_disable(enum pwm_channel ch)
-{
-	const struct pwm_t *pwm = pwm_channels + ch;
-	timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
-
-	if ((using_pwm & BIT(ch)) == 0)
-		return;
-
-	/* Main output disable */
-	tim->bdtr &= ~BIT(15);
-
-	/* Disable counter */
-	tim->cr1 &= ~0x1;
-
-	/* Disable timer clock */
-	__hw_timer_enable_clock(pwm->tim.id, 0);
-
-	/* Allow sleep */
-	enable_sleep(SLEEP_MASK_PWM);
-
-	atomic_clear_bits(&using_pwm, 1 << ch);
-
-	/* Unless another PWM is active... Then prevent sleep */
-	if (using_pwm)
-		disable_sleep(SLEEP_MASK_PWM);
-}
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	if (enabled)
-		pwm_configure(ch);
-	else
-		pwm_disable(ch);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	return using_pwm & BIT(ch);
-}
-
-static void pwm_reconfigure(enum pwm_channel ch)
-{
-	atomic_clear_bits(&using_pwm, 1 << ch);
-	pwm_configure(ch);
-}
-
-/**
- * Handle clock frequency change
- */
-static void pwm_freq_change(void)
-{
-	int i;
-	for (i = 0; i < PWM_CH_COUNT; ++i)
-		if (pwm_get_enabled(i))
-			pwm_reconfigure(i);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, pwm_freq_change, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h
deleted file mode 100644
index baa793090a..0000000000
--- a/chip/stm32/pwm_chip.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32-specific PWM module for Chrome EC */
-
-#ifndef __CROS_EC_PWM_CHIP_H
-#define __CROS_EC_PWM_CHIP_H
-
-/* Data structure to define PWM channels. */
-struct pwm_t {
-	/*
-	 * Timer powering the PWM channel. Must use STM32_TIM(x) to
-	 * initialize
-	 */
-	struct {
-		int id;
-		uintptr_t base;
-	} tim;
-	/* Channel ID within the timer */
-	int channel;
-	/* PWM channel flags. See include/pwm.h */
-	uint32_t flags;
-	/* PWM frequency (Hz) */
-	int frequency;
-};
-
-extern const struct pwm_t pwm_channels[];
-
-/* Macro to fill in both timer ID and register base */
-#define STM32_TIM(x) {x, STM32_TIM_BASE(x)}
-
-/* Plain ID mapping for readability */
-#define STM32_TIM_CH(x) (x)
-
-#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h
deleted file mode 100644
index ee4963777b..0000000000
--- a/chip/stm32/registers-stm32f0.h
+++ /dev/null
@@ -1,890 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F0 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F03X
- * - STM32F05X
- * - STM32F070
- * - STM32F07X
- * - STM32F09X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_WAKEUP       2
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            3
-#define STM32_IRQ_RCC              4
-#define STM32_IRQ_EXTI0_1          5
-#define STM32_IRQ_EXTI2_3          6
-#define STM32_IRQ_EXTI4_15         7
-#define STM32_IRQ_TSC              8
-#define STM32_IRQ_DMA_CHANNEL_1    9
-#define STM32_IRQ_DMA_CHANNEL_2_3 10
-#define STM32_IRQ_DMA_CHANNEL_4_7 11
-#define STM32_IRQ_ADC_COMP        12
-#define STM32_IRQ_TIM1_BRK_UP_TRG 13
-#define STM32_IRQ_TIM1_CC         14
-#define STM32_IRQ_TIM2            15
-#define STM32_IRQ_TIM3            16
-#define STM32_IRQ_TIM6_DAC        17
-#define STM32_IRQ_TIM7            18
-#define STM32_IRQ_TIM14           19
-#define STM32_IRQ_TIM15           20
-#define STM32_IRQ_TIM16           21
-#define STM32_IRQ_TIM17           22
-#define STM32_IRQ_I2C1            23
-#define STM32_IRQ_I2C2            24
-#define STM32_IRQ_SPI1            25
-#define STM32_IRQ_SPI2            26
-#define STM32_IRQ_USART1          27
-#define STM32_IRQ_USART2          28
-#define STM32_IRQ_USART3_4        29
-#define STM32_IRQ_CEC_CAN         30
-#define STM32_IRQ_USB             31
-/* aliases for easier code sharing */
-#define STM32_IRQ_COMP STM32_IRQ_ADC_COMP
-#define STM32_IRQ_USB_LP STM32_IRQ_USB
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40010000
-
-#define STM32_DBGMCU_BASE           0x40015800
-
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40022000
-
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFF800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40021000
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWD_PVD_LS_MASK       (0x07 << 5)
-#define STM32_PWD_PVD_LS(n)         ((n & 0x07) << 5)
-#define STM32_PWR_PVDE              BIT(4)
-
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_DACEN                 BIT(29)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
-/* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
-/* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
-
-#define STM32_RCC_HB_DMA1		BIT(0)
-/* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE           STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR       STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             20
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_PVD_EVENT              BIT(16)
-#define EXTI_RTC_ALR_EVENT          BIT(17)
-#define EXTI_COMP2_EVENT            BIT(22)
-
-/* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_ISR_ADRDY        BIT(0)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_IER_AWDIE        BIT(7)
-#define STM32_ADC_IER_OVRIE        BIT(4)
-#define STM32_ADC_IER_EOSEQIE      BIT(3)
-#define STM32_ADC_IER_EOCIE        BIT(2)
-#define STM32_ADC_IER_EOSMPIE      BIT(1)
-#define STM32_ADC_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADDIS         BIT(1)
-#define STM32_ADC_CR_ADCAL         BIT(31)
-#define STM32_ADC_CFGR1            REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26)
-#define STM32_ADC_CFGR1_AWDEN      BIT(23)
-#define STM32_ADC_CFGR1_AWDSGL     BIT(22)
-/* Selects single vs continuous */
-#define STM32_ADC_CFGR1_CONT       BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC_CFGR1_OVRMOD     BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC_CFGR1_EXTEN_DIS  (0 << 10)
-#define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10)
-#define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10)
-#define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10)
-#define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10)
-/* External trigger selection */
-#define STM32_ADC_CFGR1_TRG0	   (0 << 6)
-#define STM32_ADC_CFGR1_TRG1	   (1 << 6)
-#define STM32_ADC_CFGR1_TRG2	   (2 << 6)
-#define STM32_ADC_CFGR1_TRG3	   (3 << 6)
-#define STM32_ADC_CFGR1_TRG4	   (4 << 6)
-#define STM32_ADC_CFGR1_TRG5	   (5 << 6)
-#define STM32_ADC_CFGR1_TRG6	   (6 << 6)
-#define STM32_ADC_CFGR1_TRG7	   (7 << 6)
-#define STM32_ADC_CFGR1_TRG_MASK   (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC_CFGR1_DMACFG     BIT(1)
-#define STM32_ADC_CFGR1_DMAEN      BIT(0)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC_SMPR             REG32(STM32_ADC1_BASE + 0x14)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
-
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
-
-#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
-
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-#if !defined(CHIP_VARIANT_STM32F03X) && !defined(CHIP_VARIANT_STM32F05X)
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-
-#else /* stm32f03x and stm32f05x have only 5 channels */
-	STM32_DMAC_COUNT = 5,
-#endif
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#ifdef CHIP_VARIANT_STM32F09X
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-#else
-#define STM32_DMA_REGS(channel) STM32_DMA1_REGS
-#endif
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h
deleted file mode 100644
index b7e3cfc8af..0000000000
--- a/chip/stm32/registers-stm32f3.h
+++ /dev/null
@@ -1,1013 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F3 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F373
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_USB_HP          74
-#define STM32_IRQ_USB_LP          75
-#else
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#endif
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_COMP            64
-#else
-#define STM32_IRQ_COMP            22
-#endif
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40010000
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40022000
-
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFF800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40021000
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
-/* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
-/* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
-
-#define STM32_RCC_HB_DMA1		BIT(0)
-/* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             64
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-#endif
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
-
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
-
-#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24)
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_COMP_CMP2OUTSEL_TIM4_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM4_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM16_BRK (1 << 24)
-#else
-#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
-#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#endif
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
-
-#ifdef CHIP_VARIANT_STM32F373
-#define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM5_IC4 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM15_BRK (1 << 8)
-#else
-#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
-#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#endif
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-#ifdef CHIP_VARIANT_STM32F373
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-
-	STM32_DMAC_COUNT = 10,
-#else
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-#endif
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h
deleted file mode 100644
index 503a60cc64..0000000000
--- a/chip/stm32/registers-stm32f4.h
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F411
- * - STM32F412
- * - STM32F41X
- * - STM32F446
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#if defined(CHIP_VARIANT_STM32F412)
-#define STM32_IRQ_TIM9            24 /* STM32F412 only */
-#else
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#endif
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F412)
-#define CHIP_VARIANT_STM32F41X
-#endif
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
-/* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-#if defined(CHIP_VARIANT_STM32F446)
-/* Required or recommended clocks for stm32f446 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  42000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 336000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x8
-#define STM32F4_APB1_PRE 0x0
-#define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#elif defined(CHIP_VARIANT_STM32F412)
-/* Required or recommended clocks for stm32f412 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 384000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x0
-#define STM32F4_APB1_PRE 0x4
-#define STM32F4_APB2_PRE 0x4
-#define STM32_FLASH_ACR_LATENCY     (3 << 0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#elif defined(CHIP_VARIANT_STM32F411)
-/* Required or recommended clocks for stm32f411 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
-#define STM32F4_USB_REQ 48000000
-#define STM32F4_VCO_CLOCK 384000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
-#define STM32F4_PLLP_DIV 4
-#define STM32F4_AHB_PRE 0x8
-#define STM32F4_APB1_PRE 0x0
-#define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW    0
-
-#elif defined(CHIP_VARIANT_STM32F76X)
-/* Required or recommended clocks for stm32f767/769 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
-#define STM32F4_VCO_CLOCK 360000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
-#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
-#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
-/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
-
-#else
-#error "No valid clocks defined"
-#endif
-
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
-/* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
-
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
-/* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
-/* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB1ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB1ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB1ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB1ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB1ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB1ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB1ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
-
-/* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM1		BIT(0)
-#define STM32_RCC_PB2_TIM8		BIT(1)
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-
-/* Peripheral bits for RCC_APB/AHB regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                (BIT(30)|BIT(29))
-#define  RESET_CAUSE_SFT                BIT(28)
-#define  RESET_CAUSE_POR                BIT(27)
-#define  RESET_CAUSE_PIN                BIT(26)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25))
-#define  RESET_CAUSE_RMVF                BIT(24)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define  RESET_CAUSE_SBF                BIT(1)
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF_CLR            BIT(3)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-
-/* --- Debug --- */
-
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_TIM12                  BIT(6)
-#define  STM32_DBGMCU_APB1FZ_TIM13                  BIT(7)
-#define  STM32_DBGMCU_APB1FZ_TIM14                  BIT(8)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(23)
-#define  STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT   BIT(24)
-#define  STM32_DBGMCU_APB1FZ_CAN1                   BIT(25)
-#define  STM32_DBGMCU_APB1FZ_CAN2                   BIT(26)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(0)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(1)
-#define  STM32_DBGMCU_APB2FZ_TIM9                   BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM10                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM11                  BIT(18)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
-	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define  FLASH_OPTCR_RDP_SHIFT		(8)
-#define  FLASH_OPTCR_RDP_MASK		(0xFF << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_0		(0xAA << FLASH_OPTCR_RDP_SHIFT)
-/* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTCR_RDP_LEVEL_1		(0x00 << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_2		(0xCC << FLASH_OPTCR_RDP_SHIFT)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
-#define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-#ifdef CHIP_VARIANT_STM32F41X
-	STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6,
-	STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX,
-	STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX,
-#endif
-
-#ifdef CHIP_VARIANT_STM32F41X
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2,
-#else
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1,
-#endif
-
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h
deleted file mode 100644
index 2245d6775f..0000000000
--- a/chip/stm32/registers-stm32f7.h
+++ /dev/null
@@ -1,1082 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32F7 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32F76X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-#ifdef CHIP_VARIANT_STM32F76X
-/* Required or recommended clocks for stm32f767/769 */
-#define STM32F4_PLL_REQ 2000000
-#define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
-#define STM32F4_VCO_CLOCK 360000000
-#define STM32F4_HSI_CLOCK 16000000
-#define STM32F4_LSI_CLOCK 32000
-#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
-#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
-#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
-#else
-#error "No valid clocks defined"
-#endif
-
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
-/* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
-
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
-/* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
-/* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
-/* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
-	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define STM32_FLASH_RDP_MASK            (0xFF << 8)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
-#define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-	STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6,
-	STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX,
-	STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX,
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2,
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h
deleted file mode 100644
index e3a73a0fe9..0000000000
--- a/chip/stm32/registers-stm32g4.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32G4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32G431
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_ADC1            18
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#define STM32_IRQ_FDCAN_IT0       21
-#define STM32_IRQ_FDCAN_IT1       22
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM15           24
-#define STM32_IRQ_TIM16           25
-#define STM32_IRQ_TIM17           26
-#define STM32_IRQ_TIM1_CC         27
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42
-#define STM32_IRQ_TIM8_BREAK      43
-#define STM32_IRQ_TIM8_UP         44
-#define STM32_IRQ_TIM8_TRG_COM    45
-#define STM32_IRQ_TIM8_CC         46
-#define STM32_IRQ_LPTIM1          49
-#define STM32_IRQ_SPI3            51
-#define STM32_IRQ_USART4          52
-#define STM32_IRQ_TIM6_DAC        54
-#define STM32_IRQ_TIM7            55
-#define STM32_IRQ_DMA2_CHANNEL1   56
-#define STM32_IRQ_DMA2_CHANNEL2   57
-#define STM32_IRQ_DMA2_CHANNEL3   58
-#define STM32_IRQ_DMA2_CHANNEL4   59
-#define STM32_IRQ_DMA2_CHANNEL5   60
-#define STM32_IRQ_UCPD1           63
-#define STM32_IRQ_COMP_1_2_3      64
-#define STM32_IRQ_COMP_4          65
-#define STM32_IRQ_CRS             75
-#define STM32_IRQ_SAI1            76
-#define STM32_IRQ_FPU             81
-#define STM32_IRQ_RNG             90
-#define STM32_IRQ_LPUART          91
-#define STM32_IRQ_I2C3_EV         92
-#define STM32_IRQ_I2C3_ER         93
-#define STM32_IRQ_DMAMUX_OVR      94
-#define STM32_IRQ_DMA1_CHANNEL8   96
-#define STM32_IRQ_DMA2_CHANNEL6   97
-#define STM32_IRQ_DMA2_CHANNEL7   98
-#define STM32_IRQ_DMA2_CHANNEL8   99
-#define STM32_IRQ_CORDIC          100
-#define STM32_IRQ_FMAC            101
-
-/* LPUART gets accessed as UART9 in STM32 uart driver */
-#define STM32_IRQ_USART9 STM32_IRQ_LPUART
-
-/* To simplify code generation, define DMA channel 13 - 14 */
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-#ifdef CHIP_VARIANT_STM32G431
-#define CHIP_VARIANT_STM32G431X
-#endif
-
-/* Embedded flash option bytes base address */
-#define STM32_OPTB_BANK1_BASE       0x1FFF7800UL
-#define STM32_OPTB_BANK2_BASE       0x1FFF8000UL
-
-/* Peripheral base addresses */
-#define STM32_PERIPH_BASE           (0x40000000UL)
-/* Peripheral memory map */
-#define STM32_APB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00000000UL)
-#define STM32_APB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x00010000UL)
-#define STM32_AHB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00020000UL)
-#define STM32_AHB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x08000000UL)
-
-/* APB1 peripherals */
-#define STM32_APB1PERIPH(offset)    (STM32_APB1PERIPH_BASE + offset)
-#define STM32_TIM2_BASE             STM32_APB1PERIPH(0x0000UL)
-#define STM32_TIM3_BASE             STM32_APB1PERIPH(0x0400UL)
-#define STM32_TIM4_BASE             STM32_APB1PERIPH(0x0800UL)
-#define STM32_TIM6_BASE             STM32_APB1PERIPH(0x1000UL)
-#define STM32_TIM7_BASE             STM32_APB1PERIPH(0x1400UL)
-#define STM32_CRS_BASE              STM32_APB1PERIPH(0x2000UL)
-#define STM32_TAMP_BASE             STM32_APB1PERIPH(0x2400UL)
-#define STM32_RTC_BASE              STM32_APB1PERIPH(0x2800UL)
-#define STM32_WWDG_BASE             STM32_APB1PERIPH(0x2C00UL)
-#define STM32_IWDG_BASE             STM32_APB1PERIPH(0x3000UL)
-#define STM32_SPI2_BASE             STM32_APB1PERIPH(0x3800UL)
-#define STM32_SPI3_BASE             STM32_APB1PERIPH(0x3C00UL)
-#define STM32_USART2_BASE           STM32_APB1PERIPH(0x4400UL)
-#define STM32_USART3_BASE           STM32_APB1PERIPH(0x4800UL)
-#define STM32_UART4_BASE            STM32_APB1PERIPH(0x4C00UL)
-#define STM32_I2C1_BASE             STM32_APB1PERIPH(0x5400UL)
-#define STM32_I2C2_BASE             STM32_APB1PERIPH(0x5800UL)
-/* USB_IP Peripheral Registers base address */
-#define STM32_USB_FS_BASE           STM32_APB1PERIPH(0x5C00UL)
-/* USB_IP Packet Memory Area base address */
-#define STM32_USB_PMAADDR           STM32_APB1PERIPH(0x6000UL)
-#define STM32_FDCAN1_BASE           STM32_APB1PERIPH(0x6400UL)
-/* FDCAN configuration registers base address */
-#define STM32_FDCAN_CONFIG_BASE     STM32_APB1PERIPH(0x6500UL)
-#define STM32_PWR_BASE              STM32_APB1PERIPH(0x7000UL)
-#define STM32_I2C3_BASE             STM32_APB1PERIPH(0x7800UL)
-#define STM32_LPTIM1_BASE           STM32_APB1PERIPH(0x7C00UL)
-#define STM32_LPUART1_BASE          STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
-/* UART9 is used as link to LPUART in STM32 uart.c implementation */
-#define STM32_USART9_BASE           STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
-#define STM32_UCPD1_BASE            STM32_APB1PERIPH(0xA000UL)
-#define STM32_SRAMCAN_BASE          STM32_APB1PERIPH(0xA400UL)
-
-/* APB2 peripherals */
-#define STM32_APB2PERIPH(offset)    (STM32_APB2PERIPH_BASE + offset)
-#define STM32_SYSCFG_BASE           STM32_APB2PERIPH(0x0000UL)
-#define STM32_VREFBUF_BASE          STM32_APB2PERIPH(0x0030UL)
-#define STM32_COMP1_BASE            STM32_APB2PERIPH(0x0200UL)
-#define STM32_COMP2_BASE            STM32_APB2PERIPH(0x0204UL)
-#define STM32_COMP3_BASE            STM32_APB2PERIPH(0x0208UL)
-#define STM32_COMP4_BASE            STM32_APB2PERIPH(0x020CUL)
-#define STM32_OPAMP_BASE            STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP1_BASE           STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP2_BASE           STM32_APB2PERIPH(0x0304UL)
-#define STM32_OPAMP3_BASE           STM32_APB2PERIPH(0x0308UL)
-#define STM32_EXTI_BASE             STM32_APB2PERIPH(0x0400UL)
-#define STM32_TIM1_BASE             STM32_APB2PERIPH(0x2C00UL)
-#define STM32_SPI1_BASE             STM32_APB2PERIPH(0x3000UL)
-#define STM32_TIM8_BASE             STM32_APB2PERIPH(0x3400UL)
-#define STM32_USART1_BASE           STM32_APB2PERIPH(0x3800UL)
-#define STM32_TIM15_BASE            STM32_APB2PERIPH(0x4000UL)
-#define STM32_TIM16_BASE            STM32_APB2PERIPH(0x4400UL)
-#define STM32_TIM17_BASE            STM32_APB2PERIPH(0x4800UL)
-#define STM32_SAI1_BASE             STM32_APB2PERIPH(0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
-
-/* AHB1 peripherals */
-#define STM32_AHB1PERIPH(offset)    (STM32_AHB1PERIPH_BASE + offset)
-#define STM32_DMA1_BASE             STM32_AHB1PERIPH(0x0000UL)
-#define STM32_DMA2_BASE             STM32_AHB1PERIPH(0x0400UL)
-#define STM32_DMAMUX_BASE           STM32_AHB1PERIPH(0x0800UL)
-#define STM32_CORDIC_BASE           STM32_AHB1PERIPH(0x0C00UL)
-#define STM32_RCC_BASE              STM32_AHB1PERIPH(0x1000UL)
-#define STM32_FMAC_BASE             STM32_AHB1PERIPH(0x1400UL)
-#define STM32_FLASH_REGS_BASE       STM32_AHB1PERIPH(0x2000UL)
-#define STM32_CRC_BASE              STM32_AHB1PERIPH(0x3000UL)
-
-#define STM32_DMA1_CHAN(offset)     (STM32_DMA1_BASE + offset)
-#define STM32_DMA1_Channel1_BASE    STM32_DMA1_CHAN(0x0008UL)
-#define STM32_DMA1_Channel2_BASE    STM32_DMA1_CHAN(0x001CUL)
-#define STM32_DMA1_Channel3_BASE    STM32_DMA1_CHAN(0x0030UL)
-#define STM32_DMA1_Channel4_BASE    STM32_DMA1_CHAN(0x0044UL)
-#define STM32_DMA1_Channel5_BASE    STM32_DMA1_CHAN(0x0058UL)
-#define STM32_DMA1_Channel6_BASE    STM32_DMA1_CHAN(0x006CUL)
-
-#define STM32_DMA2_CHAN(offset)     (STM32_DMA2_BASE + offset)
-#define STM32_DMA2_Channel1_BASE    STM32_DMA2_CHAN(0x0008UL)
-#define STM32_DMA2_Channel2_BASE    STM32_DMA2_CHAN(0x001CUL)
-#define STM32_DMA2_Channel3_BASE    STM32_DMA2_CHAN(0x0030UL)
-#define STM32_DMA2_Channel4_BASE    STM32_DMA2_CHAN(0x0044UL)
-#define STM32_DMA2_Channel5_BASE    STM32_DMA2_CHAN(0x0058UL)
-#define STM32_DMA2_Channel6_BASE    STM32_DMA2_CHAN(0x006CUL)
-
-#define STM32_DMAMUX(offset)          (STM32_DMAMUX_BASE + offset)
-#define STM32_DMAMUX_Channel0_BASE    STM32_DMAMUX(0x0000UL)
-#define STM32_DMAMUX_Channel1_BASE    STM32_DMAMUX(0x0004UL)
-#define STM32_DMAMUX_Channel2_BASE    STM32_DMAMUX(0x0008UL)
-#define STM32_DMAMUX_Channel3_BASE    STM32_DMAMUX(0x000CUL)
-#define STM32_DMAMUX_Channel4_BASE    STM32_DMAMUX(0x0010UL)
-#define STM32_DMAMUX_Channel5_BASE    STM32_DMAMUX(0x0014UL)
-#define STM32_DMAMUX_Channel6_BASE    STM32_DMAMUX(0x0020UL)
-#define STM32_DMAMUX_Channel7_BASE    STM32_DMAMUX(0x0024UL)
-#define STM32_DMAMUX_Channel8_BASE    STM32_DMAMUX(0x0028UL)
-#define STM32_DMAMUX_Channel9_BASE    STM32_DMAMUX(0x002CUL)
-#define STM32_DMAMUX_Channel10_BASE   STM32_DMAMUX(0x0030UL)
-#define STM32_DMAMUX_Channel11_BASE   STM32_DMAMUX(0x0034UL)
-#define STM32_DMAMUX_RequestGenerator0_BASE  STM32_DMAMUX(0x0100UL)
-#define STM32_DMAMUX_RequestGenerator1_BASE  STM32_DMAMUX(0x0104UL)
-#define STM32_DMAMUX_RequestGenerator2_BASE  STM32_DMAMUX(0x0108UL)
-#define STM32_DMAMUX_RequestGenerator3_BASE  STM32_DMAMUX(0x010CUL)
-#define STM32_DMAMUX_ChannelStatus_BASE      STM32_DMAMUX(0x0080UL)
-#define STM32_DMAMUX_RequestGenStatus_BASE   STM32_DMAMUX(0x0140UL)
-
-/* AHB2 peripherals */
-#define STM32_AHB2PERIPH(offset)    (STM32_AHB2PERIPH_BASE + offset)
-#define STM32_GPIOA_BASE            STM32_AHB2PERIPH(0x0000UL)
-#define STM32_GPIOB_BASE            STM32_AHB2PERIPH(0x0400UL)
-#define STM32_GPIOC_BASE            STM32_AHB2PERIPH(0x0800UL)
-#define STM32_GPIOD_BASE            STM32_AHB2PERIPH(0x0C00UL)
-#define STM32_GPIOE_BASE            STM32_AHB2PERIPH(0x1000UL)
-#define STM32_GPIOF_BASE            STM32_AHB2PERIPH(0x1400UL)
-#define STM32_GPIOG_BASE            STM32_AHB2PERIPH(0x1800UL)
-#define STM32_ADC1_BASE             STM32_AHB2PERIPH(0x08000000UL)
-#define STM32_ADC2_BASE             STM32_AHB2PERIPH(0x08000100UL)
-#define STM32_ADC12_COMMON_BASE     STM32_AHB2PERIPH(0x08000300UL)
-#define STM32_DAC_BASE              STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC1_BASE             STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC3_BASE             STM32_AHB2PERIPH(0x08001000UL)
-#define STM32_RNG_BASE              STM32_AHB2PERIPH(0x08060800UL)
-
-#define STM32_UNIQUE_ID_BASE        0x1FFF7590
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- UCPD --- */
-#define STM32_UCPD_REG(port, offset) \
-	REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset)))
-
-#define STM32_UCPD_CFGR1(port)              STM32_UCPD_REG(port, 0x00)
-#define STM32_UCPD_CFGR2(port)              STM32_UCPD_REG(port, 0x04)
-#define STM32_UCPD_CR(port)                 STM32_UCPD_REG(port, 0x0c)
-#define STM32_UCPD_IMR(port)                STM32_UCPD_REG(port, 0x10)
-#define STM32_UCPD_SR(port)                 STM32_UCPD_REG(port, 0x14)
-#define STM32_UCPD_ICR(port)                STM32_UCPD_REG(port, 0x18)
-#define STM32_UCPD_TX_ORDSETR(port)         STM32_UCPD_REG(port, 0x1c)
-#define STM32_UCPD_TX_PAYSZR(port)          STM32_UCPD_REG(port, 0x20)
-#define STM32_UCPD_TXDR(port)               STM32_UCPD_REG(port, 0x24)
-#define STM32_UCPD_RX_ORDSETR(port)         STM32_UCPD_REG(port, 0x28)
-#define STM32_UCPD_RX_PAYSZR(port)          STM32_UCPD_REG(port, 0x2c)
-#define STM32_UCPD_RXDR(port)               STM32_UCPD_REG(port, 0x30)
-#define STM32_UCPD_RX_ORDEXTR1(port)        STM32_UCPD_REG(port, 0x34)
-#define STM32_UCPD_RX_ORDEXTR2(port)        STM32_UCPD_REG(port, 0x38)
-
-/* --- UCPD CFGR1 Bit Definitions --- */
-#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT     0
-#define STM32_UCPD_CFGR1_HBITCLKD_MASK      ((0x3f) << \
-					     (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
-#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
-#define STM32_UCPD_CFGR1_IFRGAP_SHIFT       6
-#define STM32_UCPD_CFGR1_IFRGAP_MASK        ((0x1f) << \
-					     (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
-#define STM32_UCPD_CFGR1_IFRGAP_VAL(x)      ((x) << \
-					     STM32_UCPD_CFGR1_IFRGAP_SHIFT)
-#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT     11
-#define STM32_UCPD_CFGR1_TRANSWIN_MASK      ((0x1f) << \
-					     (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
-#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT      17
-#define STM32_UCPD_CFGR1_PSC_CLK_MASK       ((0x7) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x)     ((x) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT   20
-#define STM32_UCPD_CFGR1_RXORDSETEN_MASK    ((0x1ff) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x)  ((x) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_TXDMAEN            BIT(29)
-#define STM32_UCPD_CFGR1_RXDMAEN            BIT(30)
-#define STM32_UCPD_CFGR1_UCPDEN             BIT(31)
-
-/* --- UCPD CFGR2 Bit Definitions --- */
-#define STM32_UCPD_CFGR2_RXFILTDIS          BIT(0)
-#define STM32_UCPD_CFGR2_RXFILT2N3          BIT(1)
-#define STM32_UCPD_CFGR2_FORCECLK           BIT(2)
-#define STM32_UCPD_CFGR2_WUPEN              BIT(3)
-
-/* --- UCPD CR Bit Definitions --- */
-#define STM32_UCPD_CR_TXMODE_SHIFT          0
-#define STM32_UCPD_CR_TXMODE_MASK           ((0x3) << \
-					     (STM32_UCPD_CR_TXMODE_SHIFT))
-#define STM32_UCPD_CR_TXMODE_VAL(x)         ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
-#define STM32_UCPD_CR_TXSEND                BIT(2)
-#define STM32_UCPD_CR_TXHRST                BIT(3)
-#define STM32_UCPD_CR_RXMODE                BIT(4)
-#define STM32_UCPD_CR_PHYRXEN               BIT(5)
-#define STM32_UCPD_CR_PHYCCSEL              BIT(6)
-#define STM32_UCPD_CR_ANASUBMODE_SHIFT      7
-#define STM32_UCPD_CR_ANASUBMODE_MASK       ((0x3) << \
-					     (STM32_UCPD_CR_ANASUBMODE_SHIFT))
-#define STM32_UCPD_CR_ANASUBMODE_VAL(x)     ((x) << \
-					     STM32_UCPD_CR_ANASUBMODE_SHIFT)
-#define STM32_UCPD_CR_ANAMODE               BIT(9)
-#define STM32_UCPD_CR_CCENABLE_SHIFT        10
-#define STM32_UCPD_CR_CCENABLE_MASK         ((0x3) << \
-					     (STM32_UCPD_CR_CCENABLE_SHIFT))
-#define STM32_UCPD_CR_CCENABLE_VAL(x)       ((x) << \
-					     STM32_UCPD_CR_CCENABLE_SHIFT)
-#define STM32_UCPD_CR_FRSRXEN               BIT(16)
-#define STM32_UCPD_CR_FRSTX                 BIT(17)
-#define STM32_UCPD_CR_RDCH                  BIT(18)
-#define STM32_UCPD_CR_CC1TCDIS              BIT(20)
-#define STM32_UCPD_CR_CC2TCDIS              BIT(21)
-
-/* TX mode message types */
-#define STM32_UCPD_CR_TXMODE_DEF            0
-#define STM32_UCPD_CR_TXMODE_CBL_RST        1
-#define STM32_UCPD_CR_TXMODE_BIST           2
-
-/* --- UCPD IMR Bit Definitions --- */
-#define STM32_UCPD_IMR_TXISIE               BIT(0)
-#define STM32_UCPD_IMR_TXMSGDISCIE          BIT(1)
-#define STM32_UCPD_IMR_TXMSGSENTIE          BIT(2)
-#define STM32_UCPD_IMR_TXMSGABTIE           BIT(3)
-#define STM32_UCPD_IMR_HRSTDISCIE           BIT(4)
-#define STM32_UCPD_IMR_HRSTSENTIE           BIT(5)
-#define STM32_UCPD_IMR_TXUNDIE              BIT(6)
-#define STM32_UCPD_IMR_RXNEIE               BIT(8)
-#define STM32_UCPD_IMR_RXORDDETIE           BIT(9)
-#define STM32_UCPD_IMR_RXHRSTDETIE          BIT(10)
-#define STM32_UCPD_IMR_RXOVRIE              BIT(11)
-#define STM32_UCPD_IMR_RXMSGENDIE           BIT(12)
-#define STM32_UCPD_IMR_TYPECEVT1IE          BIT(14)
-#define STM32_UCPD_IMR_TYPECEVT2IE          BIT(15)
-#define STM32_UCPD_IMR_FRSEVTIE             BIT(20)
-
-/* --- UCPD SR Bit Definitions --- */
-#define STM32_UCPD_SR_TXIS                  BIT(0)
-#define STM32_UCPD_SR_TXMSGDISC             BIT(1)
-#define STM32_UCPD_SR_TXMSGSENT             BIT(2)
-#define STM32_UCPD_SR_TXMSGABT              BIT(3)
-#define STM32_UCPD_SR_HRSTDISC              BIT(4)
-#define STM32_UCPD_SR_HRSTSENT              BIT(5)
-#define STM32_UCPD_SR_TXUND                 BIT(6)
-#define STM32_UCPD_SR_RXNE                  BIT(8)
-#define STM32_UCPD_SR_RXORDDET              BIT(9)
-#define STM32_UCPD_SR_RXHRSTDET             BIT(10)
-#define STM32_UCPD_SR_RXOVR                 BIT(11)
-#define STM32_UCPD_SR_RXMSGEND              BIT(12)
-#define STM32_UCPD_SR_RXERR                 BIT(13)
-#define STM32_UCPD_SR_TYPECEVT1             BIT(14)
-#define STM32_UCPD_SR_TYPECEVT2             BIT(15)
-#define STM32_UCPD_SR_VSTATE_CC1_SHIFT      16
-#define STM32_UCPD_SR_VSTATE_CC1_MASK       ((0x3) << \
-					       (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC1_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC1_SHIFT)
-#define STM32_UCPD_SR_VSTATE_CC2_SHIFT      18
-#define STM32_UCPD_SR_VSTATE_CC2_MASK       ((0x3) << \
-					     (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC2_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC2_SHIFT)
-#define STM32_UCPD_SR_FRSEVT                BIT(20)
-
-#define STM32_UCPD_SR_VSTATE_OPEN           3
-#define STM32_UCPD_SR_VSTATE_RA             0
-
-/* --- UCPD ICR Bit Definitions --- */
-#define STM32_UCPD_ICR_TXMSGDISCCF          BIT(1)
-#define STM32_UCPD_ICR_TXMSGSENTCF          BIT(2)
-#define STM32_UCPD_ICR_TXMSGABTCF           BIT(3)
-#define STM32_UCPD_ICR_HRSTDISCCF           BIT(4)
-#define STM32_UCPD_ICR_HRSTSENTCF           BIT(5)
-#define STM32_UCPD_ICR_TXUNDCF              BIT(6)
-#define STM32_UCPD_ICR_RXORDDETCF           BIT(9)
-#define STM32_UCPD_ICR_RXHRSTDETCF          BIT(10)
-#define STM32_UCPD_ICR_RXOVRCF              BIT(11)
-#define STM32_UCPD_ICR_RXMSGENDCF           BIT(12)
-#define STM32_UCPD_ICR_TYPECEVT1CF          BIT(14)
-#define STM32_UCPD_ICR_TYPECEVT2CF          BIT(15)
-#define STM32_UCPD_ICR_FRSEVTCF             BIT(20)
-
-
-/* --- UCPD TX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_TX_ORDSETR_SHIFT        0
-#define STM32_UCPD_TX_ORDSETR_MASK         ((0xfffff) << \
-					    (STM32_UCPD_TX_ORDSETR_SHIFT))
-#define STM32_UCPD_TX_ORDSETR_VAL(x)       ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
-
-/* --- UCPD TX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_TX_PAYSZR_SHIFT        0
-#define STM32_UCPD_TX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_TX_PAYSZR_SHIFT))
-#define STM32_UCPD_TX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
-
-/* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_TXDR_SHIFT             0
-#define STM32_UCPD_TXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_TXDR_SHIFT))
-#define STM32_UCPD_TXDR_VAL(x)            ((x) << STM32_UCPD_TXDR_SHIFT)
-
-/* --- UCPD RX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_RXORDSETR_SHIFT        0
-#define STM32_UCPD_RXORDSETR_MASK         ((0x7) << \
-					   (STM32_UCPD_RXORDSETR_SHIFT))
-#define STM32_UCPD_RXORDSETR_VAL(x)       ((x) << STM32_UCPD_RXORDSETR_SHIFT)
-#define STM32_UCPD_RXSOP3OF4              BIT(3)
-#define STM32_UCPD_RXSOPKINVALID_SHIFT    4
-#define STM32_UCPD_RXSOPKINVALID_MASK     ((0x7) << \
-					   (STM32_UCPD_RXSOPKINVALID_SHIFT))
-#define STM32_UCPD_RXSOPKINVALID_VAL(x)   ((x) << \
-					   STM32_UCPD_RXSOPKINVALID_SHIFT)
-
-/* --- UCPD RX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_RX_PAYSZR_SHIFT        0
-#define STM32_UCPD_RX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_RX_PAYSZR_SHIFT))
-#define STM32_UCPD_RX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
-
-/* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_RXDR_SHIFT             0
-#define STM32_UCPD_RXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_RXDR_SHIFT))
-#define STM32_UCPD_RXDR_VAL(x)            ((x) << STM32_UCPD_RXDR_SHIFT)
-
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-
-/* --- USART bit definitions -- */
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_I2C3                0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_LPUART              0xC
-#define GPIO_ALT_SAI1                0xD
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset)))
-
-#define STM32_I2C_CR1(base)            REG32(stm32g4_i2c_reg(base, 0x00))
-#define STM32_I2C_CR2(base)            REG32(stm32g4_i2c_reg(base, 0x04))
-#define STM32_I2C_OAR1(base)           REG16(stm32g4_i2c_reg(base, 0x08))
-#define STM32_I2C_OAR2(base)           REG16(stm32g4_i2c_reg(base, 0x0C))
-#define STM32_I2C_TIMINGR(base)        REG32(stm32g4_i2c_reg(base, 0x10))
-#define STM32_I2C_TIMEOUTR(base)       REG32(stm32g4_i2c_reg(base, 0x14))
-#define STM32_I2C_ISR(base)            REG32(stm32g4_i2c_reg(base, 0x18))
-#define STM32_I2C_ICR(base)            REG32(stm32g4_i2c_reg(base, 0x1C))
-#define STM32_I2C_PECR(base)           REG32(stm32g4_i2c_reg(base, 0x20))
-#define STM32_I2C_RXDR(base)           REG32(stm32g4_i2c_reg(base, 0x24))
-#define STM32_I2C_TXDR(base)           REG32(stm32g4_i2c_reg(base, 0x28))
-
-/* --- I2C CR1 Bit Definitions --- */
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-
-/* --- I2C CR2 Bit Definitions --- */
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-
-/* --- I2C ISR Bit Definitions --- */
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-
-/* --- I2C ICR Bit Definitions --- */
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-
-/* --- I2C TIMINGR bit Definitions --- */
-#define STM32_I2C_TIMINGR_SCLL_OFF 0
-#define STM32_I2C_TIMINGR_SCLH_OFF 8
-#define STM32_I2C_TIMINGR_SDADEL_OFF 16
-#define STM32_I2C_TIMINGR_SCLDEL_OFF 20
-#define STM32_I2C_TIMINGR_PRESC_OFF 28
-
-/* --- Power / Reset / Clocks --- */
-
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR                 REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_CIER                  REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR                  REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR                  REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_APB1ENR1              REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2              REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_AHB1SMENR             REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR             REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR             REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_APB1SMENR1            REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2            REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR             REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_CCIPR                 REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR                 REG32(STM32_RCC_BASE + 0x98)
-#define STM32_RCC_CCIPR2                REG32(STM32_RCC_BASE + 0x9C)
-
-#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
-#define STM32_RCC_AHBENR STM32_RCC_APB1ENR
-
-/* --- RCC CR Bit Definitions --- */
-#define STM32_RCC_CR_HSION		BIT(8)
-#define STM32_RCC_CR_HSIRDY		BIT(10)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-
-/* --- RCC PLLCFGR Bit Definitions --- */
-#define  PLLCFGR_PLLSRC_OFF		0
-#define  PLLCFGR_PLLSRC(val)		(((val) & 0x3) << PLLCFGR_PLLSRC_OFF)
-#define  PLLCFGR_PLLSRC_HSI		2
-#define  PLLCFGR_PLLSRC_HSE		3
-/* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		4
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
-/* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		8
-#define  PLLCFGR_PLLN(val)		(((val) & 0x7f) << PLLCFGR_PLLN_OFF)
-#define  PLLCFGR_PLLQ_EN		BIT(20)
-#define  PLLCFGR_PLLQ_OFF		21
-#define  PLLCFGR_PLLQ(val)		(((val) & 0x3) << PLLCFGR_PLLQ_OFF)
-/* System and main CPU clock */
-#define  PLLCFGR_PLLR_EN		BIT(24)
-#define  PLLCFGR_PLLR_OFF		25
-#define  PLLCFGR_PLLR(val)		(((val) & 0x3) << PLLCFGR_PLLR_OFF)
-#define  PLLCFGR_PLLP_OFF		27
-#define  PLLCFGR_PLLP(val)		(((val) & 0x1f) << PLLCFGR_PLLP_OFF)
-
-/* --- RCC CFGR Bit Definitions --- */
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-/* AHB Prescalar: */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
-/* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			8
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
-/* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			11
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
-/* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-/* --- RCC AHB1ENR Bit Definitions --- */
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(0)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(1)
-#define STM32_RCC_AHB1ENR_DMAMUXEN	BIT(2)
-
-/* --- RCC AHB2ENR Bit Definitions --- */
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB2ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB2ENR_GPIOMASK	(0x7f << 0)
-#define STM32_RCC_AHB2ENR_ADC12EN	BIT(13)
-#define STM32_RCC_APB2ENR_ADC345EN	BIT(14)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(26)
-
-/* --- RCC APB1ENR1 Bit Definitions --- */
-#define STM32_RCC_APB1ENR1_TIM2EN                BIT(0)
-#define STM32_RCC_APB1ENR1_TIM3EN                BIT(1)
-#define STM32_RCC_APB1ENR1_TIM4EN                BIT(2)
-#define STM32_RCC_APB1ENR1_TIM5EN                BIT(3)
-#define STM32_RCC_APB1ENR1_TIM6EN                BIT(4)
-#define STM32_RCC_APB1ENR1_TIM7EN                BIT(5)
-#define STM32_RCC_APB1ENR1_WWDGEN                BIT(11)
-#define STM32_RCC_APB1ENR1_USART2                BIT(17)
-#define STM32_RCC_APB1ENR1_USART3                BIT(18)
-#define STM32_RCC_APB1ENR1_UART4                 BIT(19)
-#define STM32_RCC_APB1ENR1_UART5                 BIT(20)
-#define STM32_RCC_APB1ENR1_I2C1EN                BIT(21)
-#define STM32_RCC_APB1ENR1_I2C2EN                BIT(22)
-#define STM32_RCC_APB1ENR1_USBEN                 BIT(23)
-#define STM32_RCC_APB1ENR1_PWREN                 BIT(28)
-#define STM32_RCC_APB1ENR1_I2C3EN                BIT(30)
-
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-/* --- RCC APB1ENR2 Bit Definitions --- */
-#define STM32_RCC_APB1ENR2_LPUART1EN             BIT(0)
-#define STM32_RCC_APB1ENR2_I2C4EN                BIT(1)
-#define STM32_RCC_APB1ENR2_UPCD1EN               BIT(8)
-
-/* --- RCC APB2ENR Bit Definitions --- */
-#define STM32_RCC_APB2ENR_SYSCFGEN	BIT(0)
-#define STM32_RCC_APB2ENR_TIM1		BIT(11)
-#define STM32_RCC_APB2ENR_SPI1EN	BIT(12)
-#define STM32_RCC_APB2ENR_TIM8		BIT(13)
-#define STM32_RCC_APB2ENR_USART1        BIT(14)
-#define STM32_RCC_APB2ENR_SPI4EN	BIT(15)
-#define STM32_RCC_APB2ENR_TIM15	BIT(16)
-#define STM32_RCC_APB2ENR_TIM16	BIT(17)
-#define STM32_RCC_APB2ENR_TIM17	BIT(18)
-#define STM32_RCC_APB2ENR_TIM20	BIT(20)
-
-#define STM32_RCC_PB2_USART1		STM32_RCC_APB2ENR_USART1
-
-/* gpio.c needs STM32_RCC_SYSCFGEN */
-#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
-
-/* --- RCC APB1RSTR1 Bit Definitions --- */
-#define STM32_RCC_APB1RSTR1_USB_RST     BIT(23)
-#define STM32_RCC_APB1RSTR              STM32_RCC_APB1RSTR1
-#define STM32_RCC_PB1_USB               STM32_RCC_APB1RSTR1_USB_RST
-
-/* --- RCC CSR Bit Definitions --- */
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-/* --- RCC CCIPR Bit Definitions --- */
-#define STM32_RCC_CCIPR_UART_SYSCLK      0x1
-#define STM32_RCC_CCIPR_USART1SEL_MASK   0x3
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT  0
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  0x3
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10
-#define STM32_RCC_CCIPR_I2C1SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT    12
-#define STM32_RCC_CCIPR_I2C2SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT    14
-#define STM32_RCC_CCIPR_I2C3SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT    16
-
-#define STM32_RCC_CCIPR2_I2C4SEL_MASK    0x3
-
-#define STM32_RCC_CCIPR_I2CNSEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2)
-#define STM32_RCC_CCIPR_I2CNSEL_HSI      0x2
-/* --- RCC CRRCR Bit Definitions */
-#define RCC_CRRCR_HSI48O               BIT(0)
-#define RCC_CRRCR_HSIRDY               BIT(1)
-
-/* Reset causes definitions */
-/*
- * Reset causes in RCC CSR register. The generic names are required
- */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define STM32_RCC_CSR_RMVF              BIT(24)
-#define STM32_RCC_CSR_BORRS             BIT(25)
-#define STM32_RCC_CSR_PIN               BIT(26)
-#define STM32_RCC_CSR_POR               BIT(27)
-#define STM32_RCC_CSR_SFT               BIT(28)
-#define STM32_RCC_CSR_IWDG              BIT(29)
-#define STM32_RCC_CSR_WWDG              BIT(30)
-#define STM32_RCC_CSR_LPWR              BIT(31)
-
-
-#define  RESET_CAUSE_WDG                (STM32_RCC_CSR_WWDG | \
-					 STM32_RCC_CSR_IWDG)
-#define  RESET_CAUSE_SFT                STM32_RCC_CSR_SFT
-#define  RESET_CAUSE_POR                STM32_RCC_CSR_POR
-#define  RESET_CAUSE_PIN                STM32_RCC_CSR_PIN
-#define  RESET_CAUSE_RMVF               STM32_RCC_CSR_RMVF
-#define  RESET_CAUSE_OTHER              (STM32_RCC_CSR_LPWR | \
-					 STM32_RCC_CSR_BORRS)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_CR1                   REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2                   REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR3                   REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR4                   REG32(STM32_PWR_BASE + 0x0C)
-#define STM32_PWR_SR1                   REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SR2                   REG32(STM32_PWR_BASE + 0x14)
-#define STM32_PWR_SCR                   REG32(STM32_PWR_BASE + 0x18)
-#define STM32_PWR_SCR_CSBF              BIT(8)
-#define STM32_PWR_SR1_SBF               BIT(8)
-
-#define STM32_PWR_RESET_CAUSE STM32_PWR_SR1
-#define  RESET_CAUSE_SBF                STM32_PWR_SR1_SBF
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
-#define  RESET_CAUSE_SBF_CLR            STM32_PWR_SCR_CSBF
-
-#define STM32_PWR_CR1_DBP               BIT(8)
-
-#define STM32_PWR_CR3_UCPD1_STDBY       BIT(13)
-#define STM32_PWR_CR3_UCPD1_DBDIS       BIT(14)
-
-/* --- System Config Registers --- */
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x18)
-
-
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_CALR              REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_SHIFTR            REG32(STM32_RTC_BASE + 0x2C)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TSSSR             REG32(STM32_RTC_BASE + 0x38)
-
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x48)
-#define STM32_RTC_ALRMBSSR          REG32(STM32_RTC_BASE + 0x44)
-
-/* --- RTC CR Bit Definitions --- */
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-/* --- RTC ICSR Bit Definitions --- */
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-/* --- RTC PRER Bit Definitions --- */
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-
-
-/* --- Tamper and Backup --- */
-#define STM32_TAMP_BKPxR(n)         REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
-#define STM32_BKP_DATA(n)           STM32_TAMP_BKPxR(n)
-#define STM32_BKP_BYTES             64
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;
-	unsigned int i2spr;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-
-/* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- DBGMCU CR Bit Definitions --- */
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-/* --- DBGMCU APB1FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(30)
-/* --- DBGMCU  APB2FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(11)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(13)
-#define  STM32_DBGMCU_APB2FZ_TIM15                  BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM16                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM17                  BIT(18)
-#define  STM32_DBGMCU_APB2FZ_TIM20                  BIT(20)
-
-/* --- Flash --- */
-#define STM32_FLASH_REG(off)        REG32(STM32_FLASH_REGS_BASE + (off))
-#define STM32_FLASH_ACR             STM32_FLASH_REG(0x00)
-#define STM32_FLASH_PDKEYR          STM32_FLASH_REG(0x04)
-#define STM32_FLASH_KEYR            STM32_FLASH_REG(0x08)
-#define STM32_FLASH_OPTKEYR         STM32_FLASH_REG(0x0c)
-#define STM32_FLASH_SR              STM32_FLASH_REG(0x10)
-#define STM32_FLASH_CR              STM32_FLASH_REG(0x14)
-#define STM32_FLASH_ECCR            STM32_FLASH_REG(0x18)
-/*
- * Bank 1 Option Byte Copy Registers. These registers are loaded from the option
- * bytes location in flash at reset, assuming that option byte loading has not
- * been disabled.
- */
-#define STM32_FLASH_OPTR            STM32_FLASH_REG(0x20)
-#define STM32_FLASH_PCROP1SR        STM32_FLASH_REG(0x24)
-#define STM32_FLASH_PCROP1ER        STM32_FLASH_REG(0x28)
-#define STM32_FLASH_WRP1AR          STM32_FLASH_REG(0x2C)
-#define STM32_FLASH_WRP1BR          STM32_FLASH_REG(0x30)
-/*
- * Bank 2 Option Byte Copy Registers. These will only exist for category 3
- * devices.
- */
-#define STM32_FLASH_PCROP2SR        STM32_FLASH_REG(0x44)
-#define STM32_FLASH_PCROP2ER        STM32_FLASH_REG(0x48)
-#define STM32_FLASH_WRP2AR          STM32_FLASH_REG(0x4C)
-#define STM32_FLASH_WRP2BR          STM32_FLASH_REG(0x50)
-
-#define STM32_FLASH_SEC_SIZE1       STM32_FLASH_REG(0x70)
-#define STM32_FLASH_SEC_SIZE2       STM32_FLASH_REG(0x74)
-
-/* --- FLASH CR Bit Definitions --- */
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-
-/* --- FLASH KEYR Bit Definitions --- */
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-
-/* --- FLASH OPTKEYR Bit Definitions --- */
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-
-/* --- FLASH SR Bit Definitions --- */
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_OPTVERR           BIT(15)
-#define  FLASH_SR_RDERR             BIT(14)
-#define  FLASH_SR_FASTERR           BIT(9)
-#define  FLASH_SR_MISERR            BIT(8)
-#define  FLASH_SR_PGSERR            BIT(7)
-#define  FLASH_SR_SIZERR            BIT(6)
-#define  FLASH_SR_PGAERR            BIT(5)
-#define  FLASH_SR_WRPERR            BIT(4)
-#define  FLASH_SR_PROGERR           BIT(3)
-#define  FLASH_SR_OPERR             BIT(1)
-#define  FLASH_SR_ERR_MASK          (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \
-				     FLASH_SR_FASTERR | FLASH_SR_PGSERR | \
-				     FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
-				     FLASH_SR_WRPERR |  FLASH_SR_PROGERR | \
-				     FLASH_SR_OPERR)
-
-/* --- FLASH CR Bit Definitions --- */
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0x7f) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0x7f)
-
-#define STM32_FLASH_MIN_WRITE_SIZE  (CONFIG_FLASH_WRITE_SIZE * 2)
-
-/* --- FLASH Option bytes --- */
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BANK1_BASE + 0x00)
-#define STM32_OPTB_PCROP1_START     REG32(STM32_OPTB_BANK1_BASE + 0x08)
-#define STM32_OPTB_PCROP1_END       REG32(STM32_OPTB_BANK1_BASE + 0x10)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BANK1_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BANK1_BASE + 0x20)
-#define STM32_OPTB_SECURE1_MEM      REG32(STM32_OPTB_BANK1_BASE + 0x28)
-
-#define STM32_OPTB_UNUSED           REG32(STM32_OPTB_BANK2_BASE + 0x00)
-#define STM32_OPTB_PCROP2_START     REG32(STM32_OPTB_BANK2_BASE + 0x08)
-#define STM32_OPTB_PCROP2_END       REG32(STM32_OPTB_BANK2_BASE + 0x10)
-#define STM32_OPTB_WRP2AR           REG32(STM32_OPTB_BANK2_BASE + 0x18)
-#define STM32_OPTB_WRP2BR           REG32(STM32_OPTB_BANK2_BASE + 0x20)
-#define STM32_OPTB_SECURE2_MEM      REG32(STM32_OPTB_BANK2_BASE + 0x28)
-
-/* Read option bytes from flash memory for Bank 1 */
-#define STM32_OPTB_BANK1_READ(n)      REG32(STM32_OPTB_BANK1_BASE + ((n) * 8))
-#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4)
-#define STM32_OPTB_BANK2_READ(n)      REG32(STM32_OPTB_BANK2_BASE + ((n) * 8))
-#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4)
-
-#define STM32_OPTB_USER_DBANK       BIT(22)
-#define STM32_OPTB_USER_nBOOT1      BIT(23)
-#define STM32_OPTB_USER_nSWBOOT0    BIT(26)
-#define STM32_OPTB_USER_nBOOT0      BIT(27)
-#define STM32_OPTB_ENTRY_NUM 6
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT BIT(17)
-
-/* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_TR1              REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_TR2              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_TR3              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
-
-
-/* --- ADC CR Bit Definitions --- */
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADSTART       BIT(2)
-#define STM32_ADC_CR_ADVREGEN      BIT(28)
-#define STM32_ADC_CR_CAL           BIT(31)
-
-#define STM32_ADC_CFGR_CONT        BIT(13)
-#define STM32_ADC_CR2_ALIGN        BIT(15)
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- *
- * Channels 0 - 5 are managed by controller DMA1, 6 - 11 by DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH10,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH11,
-	STM32_DMAC_USART3_RX = STM32_DMAC_CH12,
-	STM32_DMAC_USART3_TX = STM32_DMAC_CH13,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH5,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_LPUART_RX = STM32_DMAC_CH9,
-	STM32_DMAC_LPUART_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 14,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
-/* DMAMUX registers */
-#define STM32_DMAMUX_CxCR(x)      REG32(STM32_DMAMUX_BASE + 4 * (x))
-#define STM32_DMAMUX_CSR          REG32(STM32_DMAMUX_BASE + 0x80)
-#define STM32_DMAMUX_CFR          REG32(STM32_DMAMUX_BASE + 0x84)
-#define STM32_DMAMUX_RGxCR(x)     REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
-#define STM32_DMAMUX_RGSR         REG32(STM32_DMAMUX_BASE + 0x140)
-#define STM32_DMAMUX_RGCFR        REG32(STM32_DMAMUX_BASE + 0x144)
-
-enum dmamux1_request {
-	DMAMUX_REQ_ADC1 = 5,
-	DMAMUX_REQ_DAC1_CH1 = 6,
-	DMAMUX_REQ_DAC1_CH2 = 7,
-	DMAMUX_REQ_TIM6_UP = 8,
-	DMAMUX_REQ_TIM7_UP = 9,
-	DMAMUX_REQ_SPI1_RX = 10,
-	DMAMUX_REQ_SPI1_TX = 11,
-	DMAMUX_REQ_SPI2_RX = 12,
-	DMAMUX_REQ_SPI2_TX = 13,
-	DMAMUX_REQ_SPI3_RX = 14,
-	DMAMUX_REQ_SPI3_TX = 15,
-	DMAMUX_REQ_I2C1_RX = 16,
-	DMAMUX_REQ_I2C1_TX = 17,
-	DMAMUX_REQ_I2C2_RX = 18,
-	DMAMUX_REQ_I2C2_TX = 19,
-	DMAMUX_REQ_I2C3_RX = 20,
-	DMAMUX_REQ_I2C3_TX = 21,
-	DMAMUX_REQ_I2C4_RX = 22,
-	DMAMUX_REQ_I2C4_TX = 23,
-	DMAMUX_REQ_USART1_RX = 24,
-	DMAMUX_REQ_USART1_TX = 25,
-	DMAMUX_REQ_USART2_RX = 26,
-	DMAMUX_REQ_USART2_TX = 27,
-	DMAMUX_REQ_USART3_RX = 28,
-	DMAMUX_REQ_USART3_TX = 29,
-	DMAMUX_REQ_UART4_RX = 30,
-	DMAMUX_REQ_UART4_TX = 31,
-	DMAMUX_REQ_USART5_RX = 32,
-	DMAMUX_REQ_UART5_TX = 33,
-	DMAMUX_REQ_LPUART1_RX = 34,
-	DMAMUX_REQ_LPUART1_TX = 35,
-	DMAMUX_REQ_ADC2 = 36,
-	DMAMUX_REQ_ADC3 = 37,
-	DMAMUX_REQ_ADC4 = 38,
-	DMAMUX_REQ_ADC5 = 39,
-	DMAMUX_REQ_QUADSPI = 40,
-	DMAMUX_REQ_DAC2_CH1 = 41,
-	DMAMUX_REQ_TIM1_CH1 = 42,
-	DMAMUX_REQ_TIM1_CH2 = 43,
-	DMAMUX_REQ_TIM1_CH3 = 44,
-	DMAMUX_REQ_TIM1_CH4 = 45,
-	DMAMUX_REQ_TIM1_UP = 46,
-	DMAMUX_REQ_TIM1_TRIG = 47,
-	DMAMUX_REQ_TIM1_COM = 48,
-	DMAMUX_REQ_TIM8_CH1 = 49,
-	DMAMUX_REQ_TIM8_CH2 = 50,
-	DMAMUX_REQ_TIM8_CH3 = 51,
-	DMAMUX_REQ_TIM8_CH4 = 52,
-	DMAMUX_REQ_TIM8_UP = 53,
-	DMAMUX_REQ_TIM8_TRIG = 54,
-	DMAMUX_REQ_TIM8_COM = 55,
-	DMAMUX_REQ_TIM2_CH1 = 56,
-	DMAMUX_REQ_TIM2_CH2 = 57,
-	DMAMUX_REQ_TIM2_CH3 = 58,
-	DMAMUX_REQ_TIM2_CH4 = 59,
-	DMAMUX_REQ_TIM2_UP = 60,
-	DMAMUX_REQ_TIM3_CH1 = 61,
-	DMAMUX_REQ_TIM3_CH2 = 62,
-	DMAMUX_REQ_TIM3_CH3 = 63,
-	DMAMUX_REQ_TIM3_CH4 = 64,
-	DMAMUX_REQ_TIM3_UP = 65,
-	DMAMUX_REQ_TIM3_TRIG = 66,
-	DMAMUX_REQ_TIM4_CH1 = 67,
-	DMAMUX_REQ_TIM4_CH2 = 68,
-	DMAMUX_REQ_TIM4_CH3 = 69,
-	DMAMUX_REQ_TIM4_CH4 = 70,
-	DMAMUX_REQ_TIM4_UP = 71,
-	DMAMUX_REQ_TIM5_CH1 = 72,
-	DMAMUX_REQ_TIM5_CH2 = 73,
-	DMAMUX_REQ_TIM5_CH3 = 74,
-	DMAMUX_REQ_TIM5_CH4 = 75,
-	DMAMUX_REQ_TIM5_UP = 76,
-	DMAMUX_REQ_TIM5_TRIG = 77,
-	DMAMUX_REQ_TIM15_CH1 = 78,
-	DMAMUX_REQ_TIM15_UP = 79,
-	DMAMUX_REQ_TIM15_TRIG = 80,
-	DMAMUX_REQ_TIM15_COM = 81,
-	DMAMUX_REQ_TIM16_CH1 = 82,
-	DMAMUX_REQ_TIM16_UP = 83,
-	DMAMUX_REQ_TIM17_CH1 = 84,
-	DMAMUX_REQ_TIM17_UP = 85,
-	DMAMUX_REQ_TIM20_CH1 = 86,
-	DMAMUX_REQ_TIM20_CH2 = 87,
-	DMAMUX_REQ_TIM20_CH3 = 88,
-	DMAMUX_REQ_TIM20_CH4 = 89,
-	DMAMUX_REQ_TIM20_UP = 90,
-	DMAMUX_REQ_AES_IN = 91,
-	DMAMUX_REQ_AES_OUT = 92,
-	DMAMUX_REQ_TIM20_TRIG = 93,
-	DMAMUX_REQ_TIM20_COM = 94,
-	DMAMUX_REQ_DAC3_CH1 = 102,
-	DMAMUX_REQ_DAC3_CH2 = 103,
-	DMAMUX_REQ_DAC4_CH1 = 104,
-	DMAMUX_REQ_DAC4_CH2 = 105,
-	DMAMUX_REQ_SPI4_RX = 106,
-	DMAMUX_REQ_SPI4_TX = 107,
-	DMAMUX_REQ_SAI1_A = 108,
-	DMAMUX_REQ_SAI1_B = 109,
-};
-/* LPUART gets accessed as UART9 in STM32 uart module */
-#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX
-#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
-
-/* --- USB Endpoint bit definitions  --- */
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- RNG CR Bit Definitions --- */
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-/* --- RNG SR_DRDY Bit Definitions --- */
-#define STM32_RNG_SR_DRDY           BIT(0)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h
deleted file mode 100644
index d02aaf1249..0000000000
--- a/chip/stm32/registers-stm32h7.h
+++ /dev/null
@@ -1,1228 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32H7 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32H7X3
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-#define STM32_IRQ_LPTIM1         93
-#define STM32_IRQ_TIM15         116
-#define STM32_IRQ_TIM16         117
-#define STM32_IRQ_TIM17         118
-#define STM32_IRQ_LPTIM2        138
-#define STM32_IRQ_LPTIM3        139
-#define STM32_IRQ_LPTIM4        140
-#define STM32_IRQ_LPTIM5        141
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-/*
- * STM32F4 introduces a concept of DMA stream to allow
- * fine allocation of a stream to a channel.
- */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
-
-/* Peripheral base addresses */
-
-#define STM32_GPV_BASE              0x51000000
-
-#define STM32_DBGMCU_BASE           0x5C001000
-
-#define STM32_BDMA_BASE             0x58025400
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-#define STM32_DMA2D_BASE            0x52001000
-#define STM32_DMAMUX1_BASE          0x40020800
-#define STM32_DMAMUX2_BASE          0x58025800
-#define STM32_MDMA_BASE             0x52000000
-
-#define STM32_EXTI_BASE             0x58000000
-
-#define STM32_FLASH_REGS_BASE       0x52002000
-
-#define STM32_GPIOA_BASE            0x58020000
-#define STM32_GPIOB_BASE            0x58020400
-#define STM32_GPIOC_BASE            0x58020800
-#define STM32_GPIOD_BASE            0x58020C00
-#define STM32_GPIOE_BASE            0x58021000
-#define STM32_GPIOF_BASE            0x58021400
-#define STM32_GPIOG_BASE            0x58021800
-#define STM32_GPIOH_BASE            0x58021C00
-#define STM32_GPIOI_BASE            0x58022000
-#define STM32_GPIOJ_BASE            0x58022400
-#define STM32_GPIOK_BASE            0x58022800
-
-#define STM32_IWDG_BASE             0x58004800
-
-#define STM32_LPTIM1_BASE           0x40002400
-#define STM32_LPTIM2_BASE           0x58002400
-#define STM32_LPTIM3_BASE           0x58002800
-#define STM32_LPTIM4_BASE           0x58002C00
-#define STM32_LPTIM5_BASE           0x58003000
-
-#define STM32_PWR_BASE              0x58024800
-#define STM32_RCC_BASE              0x58024400
-#define STM32_RNG_BASE              0x48021800
-#define STM32_RTC_BASE              0x58004000
-
-#define STM32_SYSCFG_BASE           0x58000400
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00
-#define STM32_SPI4_BASE             0x40013400
-#define STM32_SPI5_BASE             0x40015000
-
-#define STM32_TIM1_BASE             0x40010000
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM8_BASE             0x40010400
-#define STM32_TIM12_BASE            0x40001800
-#define STM32_TIM13_BASE            0x40001c00
-#define STM32_TIM14_BASE            0x40002000
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-
-#define STM32_UNIQUE_ID_BASE        0x1ff1e800
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-#define STM32_USART7_BASE           0x40007800
-#define STM32_USART8_BASE           0x40007C00
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)         STM32_USART_REG(base, 0x00)
-#define  STM32_USART_CR1_UE            BIT(0)
-#define  STM32_USART_CR1_UESM          BIT(1)
-#define  STM32_USART_CR1_RE            BIT(2)
-#define  STM32_USART_CR1_TE            BIT(3)
-#define  STM32_USART_CR1_RXNEIE        BIT(5)
-#define  STM32_USART_CR1_TCIE          BIT(6)
-#define  STM32_USART_CR1_TXEIE         BIT(7)
-#define  STM32_USART_CR1_PS            BIT(9)
-#define  STM32_USART_CR1_PCE           BIT(10)
-#define  STM32_USART_CR1_M             BIT(12)
-#define  STM32_USART_CR1_OVER8         BIT(15)
-#define STM32_USART_CR2(base)         STM32_USART_REG(base, 0x04)
-#define  STM32_USART_CR2_SWAP          BIT(15)
-#define STM32_USART_CR3(base)         STM32_USART_REG(base, 0x08)
-#define  STM32_USART_CR3_EIE           BIT(0)
-#define  STM32_USART_CR3_DMAR          BIT(6)
-#define  STM32_USART_CR3_DMAT          BIT(7)
-#define  STM32_USART_CR3_ONEBIT        BIT(11)
-#define  STM32_USART_CR3_OVRDIS        BIT(12)
-#define  STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define  STM32_USART_CR3_WUFIE         BIT(22)
-#define STM32_USART_BRR(base)         STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)        STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)        STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)         STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)         STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)         STM32_USART_REG(base, 0x20)
-#define  STM32_USART_ICR_ORECF         BIT(3)
-#define  STM32_USART_ICR_TCCF          BIT(6)
-#define STM32_USART_RDR(base)         STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)         STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)       STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)          STM32_USART_ISR(base)
-#define  STM32_USART_SR_ORE            BIT(3)
-#define  STM32_USART_SR_RXNE           BIT(5)
-#define  STM32_USART_SR_TC             BIT(6)
-#define  STM32_USART_SR_TXE            BIT(7)
-
-/* --- GPIO --- */
-
-
-#define STM32_GPIO_MODER(b)           REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)          REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)         REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)           REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)             REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)             REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)            REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)            REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)            REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)            REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)              REG16(stm32_i2c_reg(n, 0x00))
-#define  STM32_I2C_CR1_PE              BIT(0)
-#define  STM32_I2C_CR1_START           BIT(8)
-#define  STM32_I2C_CR1_STOP            BIT(9)
-#define  STM32_I2C_CR1_ACK             BIT(10)
-#define  STM32_I2C_CR1_POS             BIT(11)
-#define  STM32_I2C_CR1_SWRST           BIT(15)
-#define STM32_I2C_CR2(n)              REG16(stm32_i2c_reg(n, 0x04))
-#define  STM32_I2C_CR2_ITERREN         BIT(8)
-#define  STM32_I2C_CR2_ITEVTEN         BIT(9)
-#define  STM32_I2C_CR2_ITBUFEN         BIT(10)
-#define  STM32_I2C_CR2_DMAEN           BIT(11)
-#define  STM32_I2C_CR2_LAST            BIT(12)
-#define STM32_I2C_OAR1(n)             REG16(stm32_i2c_reg(n, 0x08))
-#define  STM32_I2C_OAR1_B14            BIT(14)
-#define STM32_I2C_OAR2(n)             REG16(stm32_i2c_reg(n, 0x0C))
-#define  STM32_I2C_OAR2_ENDUAL         BIT(0)
-#define STM32_I2C_DR(n)               REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)              REG16(stm32_i2c_reg(n, 0x14))
-#define  STM32_I2C_SR1_SB              BIT(0)
-#define  STM32_I2C_SR1_ADDR            BIT(1)
-#define  STM32_I2C_SR1_BTF             BIT(2)
-#define  STM32_I2C_SR1_STOPF           BIT(4)
-#define  STM32_I2C_SR1_RXNE            BIT(6)
-#define  STM32_I2C_SR1_TXE             BIT(7)
-#define  STM32_I2C_SR1_BERR            BIT(8)
-#define  STM32_I2C_SR1_ARLO            BIT(9)
-#define  STM32_I2C_SR1_AF              BIT(10)
-
-#define STM32_I2C_SR2(n)              REG16(stm32_i2c_reg(n, 0x18))
-#define  STM32_I2C_SR2_BUSY            BIT(1)
-#define  STM32_I2C_SR2_TRA             BIT(2)
-#define  STM32_I2C_SR2_DUALF           BIT(7)
-
-#define STM32_I2C_CCR(n)              REG16(stm32_i2c_reg(n, 0x1C))
-#define  STM32_I2C_CCR_DUTY            BIT(14)
-#define  STM32_I2C_CCR_FM              BIT(15)
-#define STM32_I2C_TRISE(n)            REG16(stm32_i2c_reg(n, 0x20))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR3               REG32(STM32_PWR_BASE + 0x0C)
-#define  STM32_PWR_CR3_BYPASS        BIT(0)
-#define  STM32_PWR_CR3_LDOEN         BIT(1)
-#define  STM32_PWR_CR3_SCUEN         BIT(2)
-#define  STM32_PWR_CR3_VBE           BIT(8)
-#define  STM32_PWR_CR3_VBRS          BIT(9)
-#define  STM32_PWR_CR3_USB33DEN      BIT(24)
-#define  STM32_PWR_CR3_USBREGEN      BIT(25)
-#define  STM32_PWR_CR3_USB33RDY      BIT(26)
-#define STM32_PWR_CPUCR             REG32(STM32_PWR_BASE + 0x10)
-#define  STM32_PWR_CPUCR_PDDS_D1     BIT(0)
-#define  STM32_PWR_CPUCR_PDDS_D2     BIT(1)
-#define  STM32_PWR_CPUCR_PDDS_D3     BIT(2)
-#define  STM32_PWR_CPUCR_STOPF       BIT(5)
-#define  STM32_PWR_CPUCR_SBF         BIT(6)
-#define  STM32_PWR_CPUCR_SBF_D1      BIT(7)
-#define  STM32_PWR_CPUCR_SBF_D2      BIT(8)
-#define  STM32_PWR_CPUCR_CSSF        BIT(9)
-#define  STM32_PWR_CPUCR_RUN_D3      BIT(11)
-#define STM32_PWR_D3CR              REG32(STM32_PWR_BASE + 0x18)
-#define  STM32_PWR_D3CR_VOS1         (3 << 14)
-#define  STM32_PWR_D3CR_VOS2         (2 << 14)
-#define  STM32_PWR_D3CR_VOS3         (1 << 14)
-#define  STM32_PWR_D3CR_VOSMASK      (3 << 14)
-#define  STM32_PWR_D3CR_VOSRDY       (1 << 13)
-#define STM32_PWR_WKUPCR            REG32(STM32_PWR_BASE + 0x20)
-#define STM32_PWR_WKUPFR            REG32(STM32_PWR_BASE + 0x24)
-#define STM32_PWR_WKUPEPR           REG32(STM32_PWR_BASE + 0x28)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x000)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x004)
-#define STM32_RCC_CRRCR             REG32(STM32_RCC_BASE + 0x008)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x010)
-#define STM32_RCC_D1CFGR            REG32(STM32_RCC_BASE + 0x018)
-#define STM32_RCC_D2CFGR            REG32(STM32_RCC_BASE + 0x01C)
-#define STM32_RCC_D3CFGR            REG32(STM32_RCC_BASE + 0x020)
-#define STM32_RCC_PLLCKSELR         REG32(STM32_RCC_BASE + 0x028)
-#define STM32_RCC_PLLCFGR           REG32(STM32_RCC_BASE + 0x02C)
-#define STM32_RCC_PLL1DIVR          REG32(STM32_RCC_BASE + 0x030)
-#define STM32_RCC_PLL1FRACR         REG32(STM32_RCC_BASE + 0x034)
-#define STM32_RCC_PLL2DIVR          REG32(STM32_RCC_BASE + 0x038)
-#define STM32_RCC_PLL2FRACR         REG32(STM32_RCC_BASE + 0x03C)
-#define STM32_RCC_PLL3DIVR          REG32(STM32_RCC_BASE + 0x040)
-#define STM32_RCC_PLL3FRACR         REG32(STM32_RCC_BASE + 0x044)
-#define STM32_RCC_D1CCIPR           REG32(STM32_RCC_BASE + 0x04C)
-#define STM32_RCC_D2CCIP1R          REG32(STM32_RCC_BASE + 0x050)
-#define STM32_RCC_D2CCIP2R          REG32(STM32_RCC_BASE + 0x054)
-#define STM32_RCC_D3CCIPR           REG32(STM32_RCC_BASE + 0x058)
-#define STM32_RCC_CIER              REG32(STM32_RCC_BASE + 0x060)
-#define STM32_RCC_CIFR              REG32(STM32_RCC_BASE + 0x064)
-#define STM32_RCC_CICR              REG32(STM32_RCC_BASE + 0x068)
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x070)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x074)
-
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x098)
-
-#define STM32_RCC_RSR               REG32(STM32_RCC_BASE + 0x0D0)
-#define STM32_RCC_AHB3ENR           REG32(STM32_RCC_BASE + 0x0D4)
-#define STM32_RCC_AHB1ENR           REG32(STM32_RCC_BASE + 0x0D8)
-#define STM32_RCC_AHB2ENR           REG32(STM32_RCC_BASE + 0x0DC)
-#define STM32_RCC_AHB2ENR_RNGEN     BIT(6)
-#define STM32_RCC_AHB2ENR_HASHEN    BIT(5)
-#define STM32_RCC_AHB2ENR_CRYPTEN   BIT(4)
-#define STM32_RCC_AHB4ENR           REG32(STM32_RCC_BASE + 0x0E0)
-#define STM32_RCC_AHB4ENR_GPIOMASK  0x3ff
-#define STM32_RCC_APB3ENR           REG32(STM32_RCC_BASE + 0x0E4)
-#define STM32_RCC_APB1LENR          REG32(STM32_RCC_BASE + 0x0E8)
-#define STM32_RCC_APB1HENR          REG32(STM32_RCC_BASE + 0x0EC)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x0F0)
-#define STM32_RCC_APB4ENR           REG32(STM32_RCC_BASE + 0x0F4)
-#define STM32_RCC_SYSCFGEN          BIT(1)
-#define STM32_RCC_AHB3LPENR         REG32(STM32_RCC_BASE + 0x0FC)
-#define STM32_RCC_AHB1LPENR         REG32(STM32_RCC_BASE + 0x100)
-#define STM32_RCC_AHB2LPENR         REG32(STM32_RCC_BASE + 0x104)
-#define STM32_RCC_AHB4LPENR         REG32(STM32_RCC_BASE + 0x108)
-#define STM32_RCC_APB3LPENR         REG32(STM32_RCC_BASE + 0x10C)
-#define STM32_RCC_APB1LLPENR        REG32(STM32_RCC_BASE + 0x110)
-#define STM32_RCC_APB1HLPENR        REG32(STM32_RCC_BASE + 0x114)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x118)
-#define STM32_RCC_APB4LPENR         REG32(STM32_RCC_BASE + 0x11C)
-/* Aliases */
-#define STM32_RCC_APB1ENR           STM32_RCC_APB1LENR
-
-#define STM32_RCC_CR_HSION                     BIT(0)
-#define STM32_RCC_CR_HSIRDY                    BIT(2)
-#define STM32_RCC_CR_CSION                     BIT(7)
-#define STM32_RCC_CR_CSIRDY                    BIT(8)
-#define STM32_RCC_CR_HSI48ON                   BIT(12)
-#define STM32_RCC_CR_HSI48RDY                  BIT(13)
-#define STM32_RCC_CR_PLL1ON                    BIT(24)
-#define STM32_RCC_CR_PLL1RDY                   BIT(25)
-#define STM32_RCC_CR_PLL2ON                    BIT(26)
-#define STM32_RCC_CR_PLL2RDY                   BIT(27)
-#define STM32_RCC_CR_PLL3ON                    BIT(28)
-#define STM32_RCC_CR_PLL3RDY                   BIT(29)
-#define STM32_RCC_CFGR_SW_HSI                  (0 << 0)
-#define STM32_RCC_CFGR_SW_CSI                  (1 << 0)
-#define STM32_RCC_CFGR_SW_HSE                  (2 << 0)
-#define STM32_RCC_CFGR_SW_PLL1                 (3 << 0)
-#define STM32_RCC_CFGR_SW_MASK                 (3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI                 (0 << 3)
-#define STM32_RCC_CFGR_SWS_CSI                 (1 << 3)
-#define STM32_RCC_CFGR_SWS_HSE                 (2 << 3)
-#define STM32_RCC_CFGR_SWS_PLL1                (3 << 3)
-#define STM32_RCC_CFGR_SWS_MASK                (3 << 3)
-#define STM32_RCC_D1CFGR_HPRE_DIV1             (0 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV2             (8 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV4             (9 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV8            (10 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV16           (11 << 0)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV1           (0 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV2           (4 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV4           (5 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV8           (6 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV16          (7 << 4)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV1           (0 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV2           (8 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV4           (9 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV8          (10 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV16         (1BIT(8))
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSI          (0 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_CSI          (1 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSE          (2 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_NONE         (3 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_MASK         (3 << 0)
-#define STM32_RCC_PLLCKSEL_DIVM1(m)            ((m) << 4)
-#define STM32_RCC_PLLCKSEL_DIVM2(m)            ((m) << 12)
-#define STM32_RCC_PLLCKSEL_DIVM3(m)            ((m) << 20)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN     BIT(0)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE       (0 << 1)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM     BIT(1)
-#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M         (0 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M         (1 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M         (2 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M        (3 << 2)
-#define STM32_RCC_PLLCFG_DIVP1EN               BIT(16)
-#define STM32_RCC_PLLCFG_DIVQ1EN               BIT(17)
-#define STM32_RCC_PLLCFG_DIVR1EN               BIT(18)
-#define STM32_RCC_PLLDIV_DIVN(n)               (((n) - 1) << 0)
-#define STM32_RCC_PLLDIV_DIVP(p)               (((p) - 1) << 9)
-#define STM32_RCC_PLLDIV_DIVQ(q)               (((q) - 1) << 16)
-#define STM32_RCC_PLLDIV_DIVR(r)               (((r) - 1) << 24)
-#define STM32_RCC_PLLFRAC(n)                   ((n) << 3)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q     (0 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P     (1 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P     (2 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN   (3 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK     (4 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK      (7 << 12)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_APB        (0 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q      (1 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q      (2 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI        (3 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI        (4 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE        (5 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK       (7 << 16)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK  (0 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_HSI   (3 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_CSI   (4 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_LSE   (5 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_MASK  (7 << 0)
-#define STM32_RCC_D2CCIP2_USART16SEL_PCLK      (0 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q     (1 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q     (2 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_HSI       (3 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_CSI       (4 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_LSE       (5 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_MASK      (7 << 3)
-#define STM32_RCC_D2CCIP2_RNGSEL_HSI48         (0 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q         (1 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSE           (2 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSI           (3 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_MASK          (3 << 8)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK       (0 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2       (1 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3       (2 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE        (3 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI        (4 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER        (5 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK       (7 << 28)
-#define STM32_RCC_CSR_LSION                    BIT(0)
-#define STM32_RCC_CSR_LSIRDY                   BIT(1)
-
-#define STM32_SYSCFG_PMCR           REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
-/* Peripheral bits for APB1ENR regs */
-#define STM32_RCC_PB1_LPTIM1            BIT(9)
-
-/* Peripheral bits for APB2ENR regs */
-#define STM32_RCC_PB2_TIM1              BIT(0)
-#define STM32_RCC_PB2_TIM2              BIT(1)
-#define STM32_RCC_PB2_USART1            BIT(4)
-#define STM32_RCC_PB2_SPI1              BIT(12)
-#define STM32_RCC_PB2_SPI4              BIT(13)
-#define STM32_RCC_PB2_TIM15             BIT(16)
-#define STM32_RCC_PB2_TIM16             BIT(17)
-#define STM32_RCC_PB2_TIM17             BIT(18)
-
-/* Peripheral bits for AHB1/2/3/4ENR regs */
-#define STM32_RCC_HB1_DMA1              BIT(0)
-#define STM32_RCC_HB1_DMA2              BIT(1)
-#define STM32_RCC_HB3_MDMA              BIT(0)
-#define STM32_RCC_HB4_BDMA              BIT(21)
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1           BIT(4)
-
-/* Reset causes definitions */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_RSR
-#define  RESET_CAUSE_WDG                (BIT(28)|BIT(26))
-#define  RESET_CAUSE_SFT                BIT(24)
-#define  RESET_CAUSE_POR                BIT(23)
-#define  RESET_CAUSE_PIN                BIT(22)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25)|BIT(24)| \
-					 BIT(23)|BIT(22)|BIT(21)|BIT(20)| \
-					 BIT(19)|BIT(18)|BIT(17))
-#define  RESET_CAUSE_RMVF               BIT(16)
-
-/* Power cause in PWR CPUCR register (Standby&Stop modes) */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR
-#define  RESET_CAUSE_SBF                BIT(6)
-#define  RESET_CAUSE_SBF_CLR            BIT(9)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define  STM32_RTC_CR_BYPSHAD        BIT(5)
-#define  STM32_RTC_CR_ALRAE          BIT(8)
-#define  STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define  STM32_RTC_ISR_ALRAWF        BIT(0)
-#define  STM32_RTC_ISR_RSF           BIT(5)
-#define  STM32_RTC_ISR_INITF         BIT(6)
-#define  STM32_RTC_ISR_INIT          BIT(7)
-#define  STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define  STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define  STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint32_t cr1;
-	uint32_t cr2;
-	uint32_t cfg1;
-	uint32_t cfg2;
-	uint32_t ier;
-	uint32_t sr;
-	uint32_t ifcr;
-	uint32_t _pad0;
-	uint32_t txdr;
-	uint32_t _pad1[3];
-	uint32_t rxdr;
-	uint32_t _pad2[3];
-	uint32_t crcpoly;
-	uint32_t rxcrcr;
-	uint32_t txcrcr;
-	uint32_t udrdr;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_SPE                      BIT(0)
-#define STM32_SPI_CR1_CSTART                   BIT(9)
-#define STM32_SPI_CR1_SSI                      BIT(12)
-#define STM32_SPI_CR1_DIV(div)                 ((div) << 28)
-#define STM32_SPI_CFG1_DATASIZE(n)             (((n) - 1) << 0)
-#define STM32_SPI_CFG1_FTHLV(n)                (((n) - 1) << 5)
-#define STM32_SPI_CFG1_UDRCFG_CONST            (0 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_RX          (1 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_TX          (2 << 9)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM        (0 << 11)
-#define STM32_SPI_CFG1_UDRDET_END_FRM          (1 << 11)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_SS         (2 << 11)
-#define STM32_SPI_CFG1_RXDMAEN                 BIT(14)
-#define STM32_SPI_CFG1_TXDMAEN                 BIT(15)
-#define STM32_SPI_CFG1_CRCSIZE(n)              (((n) - 1) << 16)
-#define  STM32_SPI_CFG2_MSTR                   BIT(22)
-#define  STM32_SPI_CFG2_SSM                    BIT(26)
-#define  STM32_SPI_CFG2_AFCNTR                 BIT(31)
-
-#define STM32_SPI_SR_RXNE                      BIT(0)
-#define STM32_SPI_SR_UDR                       BIT(5)
-#define STM32_SPI_SR_FRLVL                     (3 << 13)
-#define STM32_SPI_SR_TXC                       BIT(12)
-
-/* --- Debug --- */
-#define STM32_DBGMCU_APB3FZ         REG32(STM32_DBGMCU_BASE + 0x34)
-#define STM32_DBGMCU_APB1LFZ        REG32(STM32_DBGMCU_BASE + 0x3C)
-#define STM32_DBGMCU_APB1HFZ        REG32(STM32_DBGMCU_BASE + 0x44)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x4C)
-#define STM32_DBGMCU_APB4FZ         REG32(STM32_DBGMCU_BASE + 0x54)
-/* Alias */
-#define STM32_DBGMCU_APB1FZ         STM32_DBGMCU_APB1LFZ
-
-/* --- Flash --- */
-#define STM32_FLASH_REG(bank, offset)     REG32(((bank) ? 0x100 : 0) + \
-					  STM32_FLASH_REGS_BASE + (offset))
-
-#define STM32_FLASH_ACR(bank)             STM32_FLASH_REG(bank, 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ  (0 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4)
-#define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4)
-
-#define STM32_FLASH_KEYR(bank)            STM32_FLASH_REG(bank, 0x04)
-#define  FLASH_KEYR_KEY1                   0x45670123
-#define  FLASH_KEYR_KEY2                   0xCDEF89AB
-#define STM32_FLASH_OPTKEYR(bank)         STM32_FLASH_REG(bank, 0x08)
-#define  FLASH_OPTKEYR_KEY1                0x08192A3B
-#define  FLASH_OPTKEYR_KEY2                0x4C5D6E7F
-#define STM32_FLASH_CR(bank)              STM32_FLASH_REG(bank, 0x0C)
-#define  FLASH_CR_LOCK                     BIT(0)
-#define  FLASH_CR_PG                       BIT(1)
-#define  FLASH_CR_SER                      BIT(2)
-#define  FLASH_CR_BER                      BIT(3)
-#define  FLASH_CR_PSIZE_BYTE               (0 << 4)
-#define  FLASH_CR_PSIZE_HWORD              (1 << 4)
-#define  FLASH_CR_PSIZE_WORD               (2 << 4)
-#define  FLASH_CR_PSIZE_DWORD              (3 << 4)
-#define  FLASH_CR_PSIZE_MASK               (3 << 4)
-#define  FLASH_CR_FW                       BIT(6)
-#define  FLASH_CR_STRT                     BIT(7)
-#define  FLASH_CR_SNB(sec)                 (((sec) & 0x7) << 8)
-#define  FLASH_CR_SNB_MASK                FLASH_CR_SNB(0x7)
-#define STM32_FLASH_SR(bank)              STM32_FLASH_REG(bank, 0x10)
-#define  FLASH_SR_BUSY                     BIT(0)
-#define  FLASH_SR_WBNE                     BIT(1)
-#define  FLASH_SR_QW                       BIT(2)
-#define  FLASH_SR_CRC_BUSY                 BIT(3)
-#define  FLASH_SR_EOP                      BIT(16)
-#define  FLASH_SR_WRPERR                   BIT(17)
-#define  FLASH_SR_PGSERR                   BIT(18)
-#define  FLASH_SR_STRBERR                  BIT(19)
-#define  FLASH_SR_INCERR                   BIT(21)
-#define  FLASH_SR_OPERR                    BIT(22)
-#define  FLASH_SR_RDPERR                   BIT(23)
-#define  FLASH_SR_RDSERR                   BIT(24)
-#define  FLASH_SR_SNECCERR                 BIT(25)
-#define  FLASH_SR_DBECCERR                 BIT(26)
-#define  FLASH_SR_CRCEND                   BIT(27)
-#define STM32_FLASH_CCR(bank)             STM32_FLASH_REG(bank, 0x14)
-#define  FLASH_CCR_ERR_MASK              (FLASH_SR_WRPERR | FLASH_SR_PGSERR \
-					| FLASH_SR_STRBERR | FLASH_SR_INCERR \
-					| FLASH_SR_OPERR | FLASH_SR_RDPERR \
-					| FLASH_SR_RDSERR | FLASH_SR_SNECCERR \
-					| FLASH_SR_DBECCERR)
-#define STM32_FLASH_OPTCR(bank)           STM32_FLASH_REG(bank, 0x18)
-#define  FLASH_OPTCR_OPTLOCK              BIT(0)
-#define  FLASH_OPTCR_OPTSTART             BIT(1)
-#define STM32_FLASH_OPTSR_CUR(bank)       STM32_FLASH_REG(bank, 0x1C)
-#define STM32_FLASH_OPTSR_PRG(bank)       STM32_FLASH_REG(bank, 0x20)
-#define  FLASH_OPTSR_BUSY                 BIT(0)   /* only in OPTSR_CUR */
-#define  FLASH_OPTSR_RDP_MASK             (0xFF << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_0          (0xAA << 8)
-/* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTSR_RDP_LEVEL_1          (0x00 << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_2          (0xCC << 8)
-#define  FLASH_OPTSR_RSS1                 BIT(26)
-#define  FLASH_OPTSR_RSS2                 BIT(27)
-#define STM32_FLASH_OPTCCR(bank)          STM32_FLASH_REG(bank, 0x24)
-#define STM32_FLASH_PRAR_CUR(bank)        STM32_FLASH_REG(bank, 0x28)
-#define STM32_FLASH_PRAR_PRG(bank)        STM32_FLASH_REG(bank, 0x2C)
-#define STM32_FLASH_SCAR_CUR(bank)        STM32_FLASH_REG(bank, 0x30)
-#define STM32_FLASH_SCAR_PRG(bank)        STM32_FLASH_REG(bank, 0x34)
-#define STM32_FLASH_WPSN_CUR(bank)        STM32_FLASH_REG(bank, 0x38)
-#define STM32_FLASH_WPSN_PRG(bank)        STM32_FLASH_REG(bank, 0x3C)
-#define STM32_FLASH_BOOT_CUR(bank)        STM32_FLASH_REG(bank, 0x40)
-#define STM32_FLASH_BOOT_PRG(bank)        STM32_FLASH_REG(bank, 0x44)
-#define STM32_FLASH_CRC_CR(bank)          STM32_FLASH_REG(bank, 0x50)
-#define STM32_FLASH_CRC_SADDR(bank)       STM32_FLASH_REG(bank, 0x54)
-#define STM32_FLASH_CRC_EADDR(bank)       STM32_FLASH_REG(bank, 0x58)
-#define STM32_FLASH_CRC_DATA(bank)        STM32_FLASH_REG(bank, 0x5C)
-#define STM32_FLASH_ECC_FA(bank)          STM32_FLASH_REG(bank, 0x60)
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_RTSR1            REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_FTSR1            REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_SWIER1           REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_D3PMR1           REG32(STM32_EXTI_BASE + 0x0C)
-#define STM32_EXTI_D3PCR1L          REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_D3PCR1H          REG32(STM32_EXTI_BASE + 0x14)
-#define STM32_EXTI_RTSR2            REG32(STM32_EXTI_BASE + 0x20)
-#define STM32_EXTI_FTSR2            REG32(STM32_EXTI_BASE + 0x24)
-#define STM32_EXTI_SWIER2           REG32(STM32_EXTI_BASE + 0x28)
-#define STM32_EXTI_D3PMR2           REG32(STM32_EXTI_BASE + 0x2C)
-#define STM32_EXTI_D3PCR2L          REG32(STM32_EXTI_BASE + 0x30)
-#define STM32_EXTI_D3PCR2H          REG32(STM32_EXTI_BASE + 0x34)
-#define STM32_EXTI_RTSR3            REG32(STM32_EXTI_BASE + 0x40)
-#define STM32_EXTI_FTSR3            REG32(STM32_EXTI_BASE + 0x44)
-#define STM32_EXTI_SWIER3           REG32(STM32_EXTI_BASE + 0x48)
-#define STM32_EXTI_D3PMR3           REG32(STM32_EXTI_BASE + 0x4C)
-#define STM32_EXTI_D3PCR3L          REG32(STM32_EXTI_BASE + 0x50)
-#define STM32_EXTI_D3PCR3H          REG32(STM32_EXTI_BASE + 0x54)
-#define STM32_EXTI_CPUIMR1          REG32(STM32_EXTI_BASE + 0x80)
-#define STM32_EXTI_CPUIER1          REG32(STM32_EXTI_BASE + 0x84)
-#define STM32_EXTI_CPUPR1           REG32(STM32_EXTI_BASE + 0x88)
-#define STM32_EXTI_CPUIMR2          REG32(STM32_EXTI_BASE + 0x90)
-#define STM32_EXTI_CPUIER2          REG32(STM32_EXTI_BASE + 0x94)
-#define STM32_EXTI_CPUPR2           REG32(STM32_EXTI_BASE + 0x98)
-#define STM32_EXTI_CPUIMR3          REG32(STM32_EXTI_BASE + 0xA0)
-#define STM32_EXTI_CPUIER3          REG32(STM32_EXTI_BASE + 0xA4)
-#define STM32_EXTI_CPUPR3           REG32(STM32_EXTI_BASE + 0xA8)
-/* Aliases */
-#define STM32_EXTI_IMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_EMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_RTSR             STM32_EXTI_RTSR1
-#define STM32_EXTI_FTSR             STM32_EXTI_FTSR1
-#define STM32_EXTI_SWIER            STM32_EXTI_SWIER1
-#define STM32_EXTI_PR               STM32_EXTI_CPUPR1
-
-
-/* --- ADC --- */
-
-/* --- Comparators --- */
-
-
-/* --- DMA --- */
-/*
- * Available DMA streams, numbered from 0.
- *
- * Named channel to respect older interface, but a stream can serve
- * any channels, as long as they are in the same DMA controller.
- *
- * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMA1_STREAM0 = 0,
-	STM32_DMA1_STREAM1 = 1,
-	STM32_DMA1_STREAM2 = 2,
-	STM32_DMA1_STREAM3 = 3,
-	STM32_DMA1_STREAM4 = 4,
-	STM32_DMA1_STREAM5 = 5,
-	STM32_DMA1_STREAM6 = 6,
-	STM32_DMA1_STREAM7 = 7,
-	STM32_DMAS_COUNT = 8,
-	STM32_DMA2_STREAM0 = 8,
-	STM32_DMA2_STREAM1 = 9,
-	STM32_DMA2_STREAM2 = 10,
-	STM32_DMA2_STREAM3 = 11,
-	STM32_DMA2_STREAM4 = 12,
-	STM32_DMA2_STREAM5 = 13,
-	STM32_DMA2_STREAM6 = 14,
-	STM32_DMA2_STREAM7 = 15,
-
-	STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7,
-	STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5,
-
-	/* Legacy naming for uart.c */
-	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
-	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-
-	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6,
-	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
-
-	STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7,
-	STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3,
-
-	STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4,
-	STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1,
-
-	STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5,
-	STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2,
-
-	/* Legacy naming for spi_master.c */
-	STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */
-	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
-	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
-	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
-	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
-	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
-	STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */
-	STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */
-};
-
-#define STM32_REQ_USART1_TX 4
-#define STM32_REQ_USART1_RX 4
-
-#define STM32_REQ_USART2_TX 4
-#define STM32_REQ_USART2_RX 4
-
-#define STM32_I2C1_TX_REQ_CH 1
-#define STM32_I2C1_RX_REQ_CH 1
-
-#define STM32_I2C2_TX_REQ_CH 7
-#define STM32_I2C2_RX_REQ_CH 7
-
-#define STM32_I2C3_TX_REQ_CH 3
-#define STM32_I2C3_RX_REQ_CH 1
-
-#define STM32_FMPI2C4_TX_REQ_CH 2
-#define STM32_FMPI2C4_RX_REQ_CH 2
-
-#define STM32_SPI1_TX_REQ_CH 3
-#define STM32_SPI1_RX_REQ_CH 3
-#define STM32_SPI2_TX_REQ_CH 0
-#define STM32_SPI2_RX_REQ_CH 0
-#define STM32_SPI3_TX_REQ_CH 0
-#define STM32_SPI3_RX_REQ_CH 0
-
-#define STM32_DMAS_TOTAL_COUNT 16
-
-/* Registers for a single stream of a DMA controller */
-struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
-};
-
-/* Always use stm32_dma_stream_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_stream_t dma_chan_t;
-struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
-	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
-};
-
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M           (0 << 6)
-#define STM32_DMA_CCR_DIR_M2P           (1 << 6)
-#define STM32_DMA_CCR_DIR_M2M           (2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK      (0 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)  (0)
-#define STM32_DMA_CCR_RSVD_MASK         (0xF0100000)
-#define STM32_DMA_SFCR_DMDIS            BIT(2)
-#define STM32_DMA_SFCR_FTH(level)       (((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
-#define STM32_DMA_CH_GETBITS(channel, val) \
-	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
-/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */
-/* DMAMUX1/2 registers */
-#define DMAMUX1 0
-#define DMAMUX2 1
-#define STM32_DMAMUX_BASE(n)        ((n) ? STM32_DMAMUX2_BASE \
-					 : STM32_DMAMUX1_BASE)
-#define STM32_DMAMUX_REG32(n, off)  REG32(STM32_DMAMUX_BASE(n) + (off))
-#define STM2_DMAMUX_CxCR(n, x)      STM32_DMAMUX_REG32(n, 4 * (x))
-#define STM2_DMAMUX_CSR(n)          STM32_DMAMUX_REG32(n, 0x80)
-#define STM2_DMAMUX_CFR(n)          STM32_DMAMUX_REG32(n, 0x84)
-#define STM2_DMAMUX_RGxCR(n, x)     STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
-#define STM2_DMAMUX_RGSR(n)         STM32_DMAMUX_REG32(n, 0x140)
-#define STM2_DMAMUX_RGCFR(n)        STM32_DMAMUX_REG32(n, 0x144)
-
-enum dmamux1_request {
-	DMAMUX1_REQ_ADC1 = 9,
-	DMAMUX1_REQ_ADC2 = 10,
-	DMAMUX1_REQ_TIM1_CH1 = 11,
-	DMAMUX1_REQ_TIM1_CH2 = 12,
-	DMAMUX1_REQ_TIM1_CH3 = 13,
-	DMAMUX1_REQ_TIM1_CH4 = 14,
-	DMAMUX1_REQ_TIM1_UP = 15,
-	DMAMUX1_REQ_TIM1_TRIG = 16,
-	DMAMUX1_REQ_TIM1_COM = 17,
-	DMAMUX1_REQ_TIM2_CH1 = 18,
-	DMAMUX1_REQ_TIM2_CH2 = 19,
-	DMAMUX1_REQ_TIM2_CH3 = 20,
-	DMAMUX1_REQ_TIM2_CH4 = 21,
-	DMAMUX1_REQ_TIM2_UP = 22,
-	DMAMUX1_REQ_TIM3_CH1 = 23,
-	DMAMUX1_REQ_TIM3_CH2 = 24,
-	DMAMUX1_REQ_TIM3_CH3 = 25,
-	DMAMUX1_REQ_TIM3_CH4 = 26,
-	DMAMUX1_REQ_TIM3_UP = 27,
-	DMAMUX1_REQ_TIM3_TRIG = 28,
-	DMAMUX1_REQ_TIM4_CH1 = 29,
-	DMAMUX1_REQ_TIM4_CH2 = 30,
-	DMAMUX1_REQ_TIM4_CH3 = 31,
-	DMAMUX1_REQ_TIM4_UP = 32,
-	DMAMUX1_REQ_I2C1_RX = 33,
-	DMAMUX1_REQ_I2C1_TX = 34,
-	DMAMUX1_REQ_I2C2_RX = 35,
-	DMAMUX1_REQ_I2C2_TX = 36,
-	DMAMUX1_REQ_SPI1_RX = 37,
-	DMAMUX1_REQ_SPI1_TX = 38,
-	DMAMUX1_REQ_SPI2_RX = 39,
-	DMAMUX1_REQ_SPI2_TX = 40,
-	DMAMUX1_REQ_USART1_RX = 41,
-	DMAMUX1_REQ_USART1_TX = 42,
-	DMAMUX1_REQ_USART2_RX = 43,
-	DMAMUX1_REQ_USART2_TX = 44,
-	DMAMUX1_REQ_USART3_RX = 45,
-	DMAMUX1_REQ_USART3_TX = 46,
-	DMAMUX1_REQ_TIM8_CH1 = 47,
-	DMAMUX1_REQ_TIM8_CH2 = 48,
-	DMAMUX1_REQ_TIM8_CH3 = 49,
-	DMAMUX1_REQ_TIM8_CH4 = 50,
-	DMAMUX1_REQ_TIM8_UP = 51,
-	DMAMUX1_REQ_TIM8_TRIG = 52,
-	DMAMUX1_REQ_TIM8_COM = 53,
-	DMAMUX1_REQ_TIM5_CH1 = 55,
-	DMAMUX1_REQ_TIM5_CH2 = 56,
-	DMAMUX1_REQ_TIM5_CH3 = 57,
-	DMAMUX1_REQ_TIM5_CH4 = 58,
-	DMAMUX1_REQ_TIM5_UP = 59,
-	DMAMUX1_REQ_TIM5_TRIG = 60,
-	DMAMUX1_REQ_SPI3_RX = 61,
-	DMAMUX1_REQ_SPI3_TX = 62,
-	DMAMUX1_REQ_UART4_RX = 63,
-	DMAMUX1_REQ_UART4_TX = 64,
-	DMAMUX1_REQ_USART5_RX = 65,
-	DMAMUX1_REQ_UART5_TX = 66,
-	DMAMUX1_REQ_DAC1 = 67,
-	DMAMUX1_REQ_DAC2 = 68,
-	DMAMUX1_REQ_TIM6_UP = 69,
-	DMAMUX1_REQ_TIM7_UP = 70,
-	DMAMUX1_REQ_USART6_RX = 71,
-	DMAMUX1_REQ_USART6_TX = 72,
-	DMAMUX1_REQ_I2C3_RX = 73,
-	DMAMUX1_REQ_I2C3_TX = 74,
-	DMAMUX1_REQ_DCMI = 75,
-	DMAMUX1_REQ_CRYP_IN = 76,
-	DMAMUX1_REQ_CRYP_OUT = 77,
-	DMAMUX1_REQ_HASH_IN = 78,
-	DMAMUX1_REQ_UART7_RX = 79,
-	DMAMUX1_REQ_UART7_TX = 80,
-	DMAMUX1_REQ_UART8_RX = 81,
-	DMAMUX1_REQ_UART8_TX = 82,
-	DMAMUX1_REQ_SPI4_RX = 83,
-	DMAMUX1_REQ_SPI4_TX = 84,
-	DMAMUX1_REQ_SPI5_RX = 85,
-	DMAMUX1_REQ_SPI5_TX = 86,
-	DMAMUX1_REQ_SAI1_A = 87,
-	DMAMUX1_REQ_SAI1_B = 88,
-	DMAMUX1_REQ_SAI2_A = 89,
-	DMAMUX1_REQ_SAI2_B = 90,
-	DMAMUX1_REQ_SWPMI_RX = 91,
-	DMAMUX1_REQ_SWPMI_TX = 92,
-	DMAMUX1_REQ_SPDIFRX_DT = 93,
-	DMAMUX1_REQ_SPDIFRX_CS = 94,
-	DMAMUX1_REQ_TIM15_CH1 = 105,
-	DMAMUX1_REQ_TIM15_UP = 106,
-	DMAMUX1_REQ_TIM15_TRIG = 107,
-	DMAMUX1_REQ_TIM15_COM = 108,
-	DMAMUX1_REQ_TIM16_CH1 = 109,
-	DMAMUX1_REQ_TIM16_UP = 110,
-	DMAMUX1_REQ_TIM17_CH1 = 111,
-	DMAMUX1_REQ_TIM17_UP = 112,
-	DMAMUX1_REQ_SAI3_A = 113,
-	DMAMUX1_REQ_SAI3_B = 114,
-	DMAMUX1_REQ_ADC3 = 115,
-};
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define  STM32_CRC_CR_RESET          BIT(0)
-#define  STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define  STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define  STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define  STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define  STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define  STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define  STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define  STM32_CRC_CR_REV_OUT        BIT(7)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-#define  STM32_USB_CNTR_FRES        BIT(0)
-#define  STM32_USB_CNTR_PDWN        BIT(1)
-#define  STM32_USB_CNTR_LP_MODE     BIT(2)
-#define  STM32_USB_CNTR_FSUSP       BIT(3)
-#define  STM32_USB_CNTR_RESUME      BIT(4)
-#define  STM32_USB_CNTR_L1RESUME    BIT(5)
-#define  STM32_USB_CNTR_L1REQM      BIT(7)
-#define  STM32_USB_CNTR_ESOFM       BIT(8)
-#define  STM32_USB_CNTR_SOFM        BIT(9)
-#define  STM32_USB_CNTR_RESETM      BIT(10)
-#define  STM32_USB_CNTR_SUSPM       BIT(11)
-#define  STM32_USB_CNTR_WKUPM       BIT(12)
-#define  STM32_USB_CNTR_ERRM        BIT(13)
-#define  STM32_USB_CNTR_PMAOVRM     BIT(14)
-#define  STM32_USB_CNTR_CTRM        BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-#define  STM32_USB_ISTR_EP_ID_MASK  (0x000f)
-#define  STM32_USB_ISTR_DIR         BIT(4)
-#define  STM32_USB_ISTR_L1REQ       BIT(7)
-#define  STM32_USB_ISTR_ESOF        BIT(8)
-#define  STM32_USB_ISTR_SOF         BIT(9)
-#define  STM32_USB_ISTR_RESET       BIT(10)
-#define  STM32_USB_ISTR_SUSP        BIT(11)
-#define  STM32_USB_ISTR_WKUP        BIT(12)
-#define  STM32_USB_ISTR_ERR         BIT(13)
-#define  STM32_USB_ISTR_PMAOVR      BIT(14)
-#define  STM32_USB_ISTR_CTR         BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-#define  STM32_USB_BCDR_BCDEN       BIT(0)
-#define  STM32_USB_BCDR_DCDEN       BIT(1)
-#define  STM32_USB_BCDR_PDEN        BIT(2)
-#define  STM32_USB_BCDR_SDEN        BIT(3)
-#define  STM32_USB_BCDR_DCDET       BIT(4)
-#define  STM32_USB_BCDR_PDET        BIT(5)
-#define  STM32_USB_BCDR_SDET        BIT(6)
-#define  STM32_USB_BCDR_PS2DET      BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define  STM32_RNG_CR_RNGEN          BIT(2)
-#define  STM32_RNG_CR_IE             BIT(3)
-#define  STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define  STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE          BIT(1)
-#define  READ_ISS_OVERRIDE           BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h
deleted file mode 100644
index 37b31ac302..0000000000
--- a/chip/stm32/registers-stm32l.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L100
- * - STM32L15X
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
-/* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-
-
-
-/* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-#define STM32_COMP_BASE             0x40007C00
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-
-#define STM32_EXTI_BASE             0x40010400
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021800 /* see RM0038 table 5 */
-#define STM32_GPIOG_BASE            0x40021C00
-#define STM32_GPIOH_BASE            0x40021400
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1ff80000
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40010000
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40010800 /* STM32L15X only */
-#define STM32_TIM10_BASE            0x40010C00 /* STM32L15X only */
-#define STM32_TIM11_BASE            0x40011000 /* STM32L15X only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
-
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
-/* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
-
-/* --- GPIO --- */
-
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_MSION		BIT(8)
-#define STM32_RCC_CR_MSIRDY		BIT(9)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_ICSCR_MSIRANGE(n)	((n) << 13)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ	STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ	STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK	STM32_RCC_ICSCR_MSIRANGE(7)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_MSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_MSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHBRSTR           REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_SYSCFGEN		BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_AHBLPENR          REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_APB1LPENR         REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x34)
-
-#define STM32_RCC_HB_DMA1		BIT(24)
-#define STM32_RCC_PB2_TIM9		BIT(2)
-#define STM32_RCC_PB2_TIM10		BIT(3)
-#define STM32_RCC_PB2_TIM11		BIT(4)
-#define STM32_RCC_PB1_USB		BIT(23)
-
-#define STM32_SYSCFG_MEMRMP         REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC            REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
-
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned crcpr;
-	unsigned rxcrcr;
-	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY		BIT(0)
-#define STM32_FLASH_ACR_PRFTEN		BIT(1)
-#define STM32_FLASH_ACR_ACC64		BIT(2)
-#define STM32_FLASH_PECR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_PECR_PE_LOCK	BIT(0)
-#define STM32_FLASH_PECR_PRG_LOCK	BIT(1)
-#define STM32_FLASH_PECR_OPT_LOCK	BIT(2)
-#define STM32_FLASH_PECR_PROG		BIT(3)
-#define STM32_FLASH_PECR_ERASE		BIT(9)
-#define STM32_FLASH_PECR_FPRG		BIT(10)
-#define STM32_FLASH_PECR_OBL_LAUNCH	BIT(18)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define STM32_FLASH_PEKEYR          REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define STM32_FLASH_PEKEYR_KEY1		0x89ABCDEF
-#define STM32_FLASH_PEKEYR_KEY2		0x02030405
-#define STM32_FLASH_PRGKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define STM32_FLASH_PRGKEYR_KEY1	0x8C9DAEBF
-#define STM32_FLASH_PRGKEYR_KEY2	0x13141516
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OPTKEYR_KEY1	0xFBEAD9C8
-#define STM32_FLASH_OPTKEYR_KEY2	0x24252627
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP                  0x00
-#define STM32_OPTB_USER                 0x04
-#define STM32_OPTB_WRP1L                0x08
-#define STM32_OPTB_WRP1H                0x0c
-#define STM32_OPTB_WRP2L                0x10
-#define STM32_OPTB_WRP2H                0x14
-#define STM32_OPTB_WRP3L                0x18
-#define STM32_OPTB_WRP3H                0x1c
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-
-/* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR3            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_JOFR1            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_JOFR2            REG32(STM32_ADC1_BASE + 0x1C)
-#define STM32_ADC_JOFR3            REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_JOFR4            REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x2C + (n) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_SQR5             REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x44)
-#define STM32_ADC_JDR1             REG32(STM32_ADC1_BASE + 0x48)
-#define STM32_ADC_JDR2             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR4             REG32(STM32_ADC1_BASE + 0x54)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x58)
-#define STM32_ADC_SMPR0            REG32(STM32_ADC1_BASE + 0x5C)
-
-#define STM32_ADC_CCR              REG32(STM32_ADC_BASE + 0x04)
-
-/* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x00)
-
-#define STM32_COMP_OUTSEL_TIM2_IC4  (0 << 21)
-#define STM32_COMP_OUTSEL_TIM2_OCR  (1 << 21)
-#define STM32_COMP_OUTSEL_TIM3_IC4  (2 << 21)
-#define STM32_COMP_OUTSEL_TIM3_OCR  (3 << 21)
-#define STM32_COMP_OUTSEL_TIM4_IC4  (4 << 21)
-#define STM32_COMP_OUTSEL_TIM4_OCR  (5 << 21)
-#define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21)
-#define STM32_COMP_OUTSEL_NONE      (7 << 21)
-
-#define STM32_COMP_INSEL_NONE       (0 << 18)
-#define STM32_COMP_INSEL_PB3        (1 << 18)
-#define STM32_COMP_INSEL_VREF       (2 << 18)
-#define STM32_COMP_INSEL_VREF34     (3 << 18)
-#define STM32_COMP_INSEL_VREF12     (4 << 18)
-#define STM32_COMP_INSEL_VREF14     (5 << 18)
-#define STM32_COMP_INSEL_DAC_OUT1   (6 << 18)
-#define STM32_COMP_INSEL_DAC_OUT2   (7 << 18)
-
-#define STM32_COMP_WNDWE            BIT(17)
-#define STM32_COMP_VREFOUTEN        BIT(16)
-#define STM32_COMP_CMP2OUT          BIT(13)
-#define STM32_COMP_SPEED_FAST       BIT(12)
-
-#define STM32_COMP_CMP1OUT          BIT(7)
-#define STM32_COMP_CMP1EN           BIT(4)
-
-#define STM32_COMP_400KPD           BIT(3)
-#define STM32_COMP_10KPD            BIT(2)
-#define STM32_COMP_400KPU           BIT(1)
-#define STM32_COMP_10KPU            BIT(0)
-
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-
-	/* Channel functions */
-	STM32_DMAC_ADC = STM32_DMAC_CH1,
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2,
-	STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3,
-	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
-	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
-	STM32_DMAC_USART2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_USART2_TX = STM32_DMAC_CH7,
-	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
-	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
-	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
-	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH6,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH7,
-	/* Only DMA1 (with 7 channels) is present on STM32L151x */
-	STM32_DMAC_COUNT = 7,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-
-#define STM32_DMA_REGS(channel) STM32_DMA1_REGS
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h
deleted file mode 100644
index 29965fe2ee..0000000000
--- a/chip/stm32/registers-stm32l4.h
+++ /dev/null
@@ -1,2114 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L4 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L442
- * - STM32L476
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/******  STM32 specific Interrupt Numbers ********/
-#define   STM32_IRQ_WWDG                    0
-#define   STM32_IRQ_PVD_PVM                 1
-#define   STM32_IRQ_TAMP_STAMP              2
-#define   STM32_IRQ_RTC_WKUP                3
-#define   STM32_IRQ_FLASH                   4
-#define   STM32_IRQ_RCC                     5
-#define   STM32_IRQ_EXTI0                   6
-#define   STM32_IRQ_EXTI1                   7
-#define   STM32_IRQ_EXTI2                   8
-#define   STM32_IRQ_EXTI3                   9
-#define   STM32_IRQ_EXTI4                   10
-#define   STM32_IRQ_DMA_CHANNEL_1           11
-#define   STM32_IRQ_DMA_CHANNEL_2           12
-#define   STM32_IRQ_DMA_CHANNEL_3           13
-#define   STM32_IRQ_DMA_CHANNEL_4           14
-#define   STM32_IRQ_DMA_CHANNEL_5           15
-#define   STM32_IRQ_DMA_CHANNEL_6           16
-#define   STM32_IRQ_DMA_CHANNEL_7           17
-#define   STM32_IRQ_ADC1                    18
-#define   STM32_IRQ_CAN1_TX                 19
-#define   STM32_IRQ_CAN1_RX0                20
-#define   STM32_IRQ_CAN1_RX1                21
-#define   STM32_IRQ_CAN1_SCE                22
-#define   STM32_IRQ_EXTI9_5                 23
-#define   STM32_IRQ_TIM1_BRK_TIM15          24
-#define   STM32_IRQ_TIM1_UP_TIM16           25
-#define   STM32_IRQ_TIM1_TRG_COM            26
-#define   STM32_IRQ_TIM1_CC                 27
-#define   STM32_IRQ_TIM2                    28
-#define   STM32_IRQ_I2C1_EV                 31
-#define   STM32_IRQ_I2C1_ER                 32
-#define   STM32_IRQ_I2C2_EV                 33
-#define   STM32_IRQ_I2C2_ER                 34
-#define   STM32_IRQ_SPI1                    35
-#define   STM32_IRQ_SPI2                    36
-#define   STM32_IRQ_USART1                  37
-#define   STM32_IRQ_USART2                  38
-#define   STM32_IRQ_USART3                  39
-#define   STM32_IRQ_EXTI15_10               40
-#define   STM32_IRQ_RTC_ALARM               41
-#define   STM32_IRQ_SDMMC1                  49
-#define   STM32_IRQ_TIM5                    50
-#define   STM32_IRQ_SPI3                    51
-#define   STM32_IRQ_TIM6_DAC                54
-#define   STM32_IRQ_TIM7                    55
-#define   STM32_IRQ_DMA2_CHANNEL1           56
-#define   STM32_IRQ_DMA2_CHANNEL2           57
-#define   STM32_IRQ_DMA2_CHANNEL3           58
-#define   STM32_IRQ_DMA2_CHANNEL4           59
-#define   STM32_IRQ_DMA2_CHANNEL5           60
-#define   STM32_IRQ_COMP                    64
-#define   LSTM32_IRQ_PTIM1                  65
-#define   STM32_IRQ_LPTIM2                  66
-#define   STM32_IRQ_DMA2_CHANNEL6           68
-#define   STM32_IRQ_DMA2_CHANNEL7           69
-#define   STM32_IRQ_LPUART1                 70
-#define   STM32_IRQ_QUADSPI                 71
-#define   STM32_IRQ_I2C3_EV                 72
-#define   STM32_IRQ_I2C3_ER                 73
-#define   STM32_IRQ_SAI1                    74
-#define   STM32_IRQ_SWPMI1                  76
-#define   STM32_IRQ_TSC                     77
-#define   STM32_IRQ_RNG                     80
-#define   STM32_IRQ_FPU                     81
-#define   STM32_IRQ_CRS                     82
-
-/* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_USART9           STM32_IRQ_LPUART1
-
-
-/* Peripheral base addresses */
-#define FLASH_BASE            0x08000000UL
-#define FLASH_END             0x0803FFFFUL
-#define FLASH_BANK1_END       0x0803FFFFUL
-#define SRAM1_BASE            0x20000000UL
-#define SRAM2_BASE            0x10000000UL
-#define PERIPH_BASE           0x40000000UL
-#define QSPI_BASE             0x90000000UL
-#define QSPI_R_BASE           0xA0001000UL
-#define SRAM1_BB_BASE         0x22000000UL
-#define PERIPH_BB_BASE        0x42000000UL
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-#define SRAM1_SIZE_MAX        0x0000C000UL
-#define SRAM2_SIZE            0x00004000UL
-#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
-#define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \
-			& (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
-			(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \
-			(0x0000FFFFU)) << 10U))
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
-
-/*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
-#define STM32_CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
-#define STM32_LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
-#define STM32_SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)
-#define STM32_LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
-
-#define STM32_USART9_BASE           STM32_LPUART1_BASE
-
-/*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
-#define STM32_OMP1_BASE             (APB2PERIPH_BASE + 0x0200UL)
-#define STM32_COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
-#define STM32_EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
-#define STM32_FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
-#define STM32_SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
-
-/*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
-
-/*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
-#define STM32_ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
-#define STM32_ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
-
-/* Debug MCU registers base address */
-#define STM32_DBGMCU_BASE           0xE0042000UL
-#define STM32_PACKAGE_BASE          0x1FFF7500UL
-#define STM32_UID_BASE              0x1FFF7590UL
-#define STM32_FLASHSIZE_BASE        0x1FFF75E0UL
-
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
-#define STM32_OPTB_BASE             0x1FFF7800
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
-
-/* --- Macro usage in ec code --- */
-#define STM32_RCC_AHB2ENR_GPIOMASK                               \
-	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
-	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
-	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN)
-#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
-
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
-#ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
-#endif
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
-#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
-#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
-#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
-/* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR       REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
-
-#define STM32_RCC_PLLSAI1_SUPPORT
-#define STM32_RCC_PLLP_SUPPORT
-#define STM32_RCC_HSI48_SUPPORT
-#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
-#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
-
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
-
-/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
-
-/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
-
-/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
-/*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
-
-/*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
-
-/*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
-
-/*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
-/*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
-
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
-
-/*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
-
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
-
-/*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
-
-/*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
-
-/*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
-
-/*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
-
-/* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
-
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
-	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
-	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
-	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
-	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
-	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
-#define STM32_RCC_CIER_LSIRDYIE_POS 0U
-#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
-#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
-#define STM32_RCC_CIER_LSERDYIE_POS 1U
-#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
-#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
-#define STM32_RCC_CIER_MSIRDYIE_POS 2U
-#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
-#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
-#define STM32_RCC_CIER_HSIRDYIE_POS 3U
-#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
-#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
-#define STM32_RCC_CIER_HSERDYIE_POS 4U
-#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
-#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
-#define STM32_RCC_CIER_PLLRDYIE_POS 5U
-#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
-#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
-#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
-#define STM32_RCC_CIER_LSECSSIE_POS 9U
-#define STM32_RCC_CIER_LSECSSIE_MSK (0x1UL << STM32_RCC_CIER_LSECSSIE_POS)
-#define STM32_RCC_CIER_LSECSSIE STM32_RCC_CIER_LSECSSIE_MSK
-#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
-#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
-#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
-#define STM32_RCC_CIFR_LSIRDYF_POS 0U
-#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
-#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
-#define STM32_RCC_CIFR_LSERDYF_POS 1U
-#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
-#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
-#define STM32_RCC_CIFR_MSIRDYF_POS 2U
-#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
-#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
-#define STM32_RCC_CIFR_HSIRDYF_POS 3U
-#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
-#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
-#define STM32_RCC_CIFR_HSERDYF_POS 4U
-#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
-#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
-#define STM32_RCC_CIFR_PLLRDYF_POS 5U
-#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
-#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
-#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
-#define STM32_RCC_CIFR_CSSF_POS 8U
-#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
-#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
-#define STM32_RCC_CIFR_LSECSSF_POS 9U
-#define STM32_RCC_CIFR_LSECSSF_MSK (0x1UL << STM32_RCC_CIFR_LSECSSF_POS)
-#define STM32_RCC_CIFR_LSECSSF STM32_RCC_CIFR_LSECSSF_MSK
-#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
-#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
-#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
-#define STM32_RCC_CICR_LSIRDYC_POS 0U
-#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
-#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
-#define STM32_RCC_CICR_LSERDYC_POS 1U
-#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
-#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
-#define STM32_RCC_CICR_MSIRDYC_POS 2U
-#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
-#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
-#define STM32_RCC_CICR_HSIRDYC_POS 3U
-#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
-#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
-#define STM32_RCC_CICR_HSERDYC_POS 4U
-#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
-#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
-#define STM32_RCC_CICR_PLLRDYC_POS 5U
-#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
-#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
-#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
-#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
-#define STM32_RCC_CICR_CSSC_POS 8U
-#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
-#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
-#define STM32_RCC_CICR_LSECSSC_POS 9U
-#define STM32_RCC_CICR_LSECSSC_MSK (0x1UL << STM32_RCC_CICR_LSECSSC_POS)
-#define STM32_RCC_CICR_LSECSSC STM32_RCC_CICR_LSECSSC_MSK
-#define STM32_RCC_CICR_HSI48RDYC_POS 10U
-#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
-#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
-#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
-#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
-#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
-#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
-#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
-#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
-#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
-#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
-#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
-#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
-#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
-#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
-#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
-#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
-#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
-#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
-#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
-#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
-#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
-#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
-#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
-#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
-#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
-#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
-#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
-#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
-#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
-#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
-#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
-#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
-#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
-#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
-#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
-#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
-#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
-#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
-#define STM32_RCC_APB1RSTR1_LCDRST_POS 9U
-#define STM32_RCC_APB1RSTR1_LCDRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_LCDRST_POS)
-#define STM32_RCC_APB1RSTR1_LCDRST STM32_RCC_APB1RSTR1_LCDRST_MSK
-#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
-#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
-#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
-#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
-#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
-#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
-#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
-#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
-#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
-#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
-#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
-#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
-#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
-#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
-#define STM32_RCC_APB1RSTR1_CAN1RST_POS 25U
-#define STM32_RCC_APB1RSTR1_CAN1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_CAN1RST_POS)
-#define STM32_RCC_APB1RSTR1_CAN1RST STM32_RCC_APB1RSTR1_CAN1RST_MSK
-#define STM32_RCC_APB1RSTR1_USBFSRST_POS 26U
-#define STM32_RCC_APB1RSTR1_USBFSRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USBFSRST_POS)
-#define STM32_RCC_APB1RSTR1_USBFSRST STM32_RCC_APB1RSTR1_USBFSRST_MSK
-#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
-#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
-#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
-#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
-#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
-#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
-#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
-#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
-#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
-#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
-#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
-#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
-#define STM32_RCC_APB1RSTR2_SWPMI1RST_POS 2U
-#define STM32_RCC_APB1RSTR2_SWPMI1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_SWPMI1RST_POS)
-#define STM32_RCC_APB1RSTR2_SWPMI1RST STM32_RCC_APB1RSTR2_SWPMI1RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
-#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
-#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
-#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
-#define STM32_RCC_APB2RSTR_SDMMC1RST_POS 10U
-#define STM32_RCC_APB2RSTR_SDMMC1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SDMMC1RST_POS)
-#define STM32_RCC_APB2RSTR_SDMMC1RST STM32_RCC_APB2RSTR_SDMMC1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
-#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
-#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
-#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
-#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
-#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
-#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
-#define STM32_RCC_APB2RSTR_USART1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
-#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
-#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
-#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
-#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
-#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
-#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
-#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
-#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
-#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
-#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
-#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
-#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
-#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
-#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
-#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
-#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
-#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
-#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
-#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
-#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
-#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
-#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
-#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
-#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
-
-/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
-#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
-#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
-#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
-#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
-#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
-#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
-#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
-#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
-#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
-#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
-#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
-#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
-#define STM32_RCC_AHB2ENR_AESEN_POS 16U
-#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
-#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
-#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
-#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
-#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
-#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
-#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
-#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
-#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
-#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
-#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
-#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
-#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
-#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
-#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
-#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
-#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
-#define STM32_RCC_APB1ENR1_LCDEN_POS 9U
-#define STM32_RCC_APB1ENR1_LCDEN_MSK (0x1UL << STM32_RCC_APB1ENR1_LCDEN_POS)
-#define STM32_RCC_APB1ENR1_LCDEN STM32_RCC_APB1ENR1_LCDEN_MSK
-#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
-#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
-#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
-#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
-#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
-#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
-#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
-#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
-#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
-#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
-#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
-#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
-#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
-#define STM32_RCC_APB1ENR1_USART2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
-#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
-#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
-#define STM32_RCC_APB1ENR1_USART3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
-#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
-#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
-#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
-#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
-#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
-#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
-#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
-#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
-#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
-#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
-#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
-#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
-#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
-#define STM32_RCC_APB1ENR1_CAN1EN_POS 25U
-#define STM32_RCC_APB1ENR1_CAN1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_CAN1EN_POS)
-#define STM32_RCC_APB1ENR1_CAN1EN STM32_RCC_APB1ENR1_CAN1EN_MSK
-#define STM32_RCC_APB1ENR1_USBFSEN_POS 26U
-#define STM32_RCC_APB1ENR1_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_USBFSEN_POS)
-#define STM32_RCC_APB1ENR1_USBFSEN STM32_RCC_APB1ENR1_USBFSEN_MSK
-#define STM32_RCC_APB1ENR1_PWREN_POS 28U
-#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
-#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
-#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
-#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
-#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
-#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
-#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
-#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
-#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
-#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
-#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
-#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
-#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
-#define STM32_RCC_APB1ENR2_SWPMI1EN_POS 2U
-#define STM32_RCC_APB1ENR2_SWPMI1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_SWPMI1EN_POS)
-#define STM32_RCC_APB1ENR2_SWPMI1EN STM32_RCC_APB1ENR2_SWPMI1EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
-#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
-#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
-#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
-#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
-#define STM32_RCC_APB2ENR_FWEN_POS 7U
-#define STM32_RCC_APB2ENR_FWEN_MSK (0x1UL << STM32_RCC_APB2ENR_FWEN_POS)
-#define STM32_RCC_APB2ENR_FWEN STM32_RCC_APB2ENR_FWEN_MSK
-#define STM32_RCC_APB2ENR_SDMMC1EN_POS 10U
-#define STM32_RCC_APB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SDMMC1EN_POS)
-#define STM32_RCC_APB2ENR_SDMMC1EN STM32_RCC_APB2ENR_SDMMC1EN_MSK
-#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
-#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
-#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
-#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
-#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
-#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
-#define STM32_RCC_APB2ENR_USART1EN_POS 14U
-#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
-#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
-#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
-#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
-#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
-#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
-#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
-#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
-#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
-#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
-#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
-#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
-#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
-#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
-#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
-#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
-#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
-#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
-#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
-#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
-#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
-#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
-#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
-#define STM32_RCC_APB1SMENR1_LCDSMEN_POS 9U
-#define STM32_RCC_APB1SMENR1_LCDSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LCDSMEN_POS)
-#define STM32_RCC_APB1SMENR1_LCDSMEN STM32_RCC_APB1SMENR1_LCDSMEN_MSK
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
-#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
-#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
-#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
-#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_CAN1SMEN_POS 25U
-#define STM32_RCC_APB1SMENR1_CAN1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CAN1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_CAN1SMEN STM32_RCC_APB1SMENR1_CAN1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USBFSSMEN_POS 26U
-#define STM32_RCC_APB1SMENR1_USBFSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USBFSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_USBFSSMEN STM32_RCC_APB1SMENR1_USBFSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
-#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
-#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS 2U
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_SWPMI1SMEN STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN_POS 10U
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SDMMC1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SDMMC1SMEN STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
-#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
-#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
-#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
-#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
-#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
-#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
-#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER  ******************/
-#define STM32_RCC_CCIPR_USART1SEL_POS 0U
-#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
-#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
-
-#define STM32_RCC_CCIPR_USART2SEL_POS 2U
-#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
-#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
-
-#define STM32_RCC_CCIPR_USART3SEL_POS 4U
-#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
-#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U
-#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
-#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C1SEL_POS 12U
-#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
-#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C2SEL_POS 14U
-#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
-#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C3SEL_POS 16U
-#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
-#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U
-#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U
-#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-
-#define STM32_RCC_CCIPR_SAI1SEL_POS 22U
-#define STM32_RCC_CCIPR_SAI1SEL_MSK (0x3UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-#define STM32_RCC_CCIPR_SAI1SEL STM32_RCC_CCIPR_SAI1SEL_MSK
-#define STM32_RCC_CCIPR_SAI1SEL_0 (0x1UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-#define STM32_RCC_CCIPR_SAI1SEL_1 (0x2UL << STM32_RCC_CCIPR_SAI1SEL_POS)
-
-#define STM32_RCC_CCIPR_CLK48SEL_POS 26U
-#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
-#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-
-#define STM32_RCC_CCIPR_ADCSEL_POS 28U
-#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
-#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
-
-#define STM32_RCC_CCIPR_SWPMI1SEL_POS 30U
-#define STM32_RCC_CCIPR_SWPMI1SEL_MSK (0x1UL << STM32_RCC_CCIPR_SWPMI1SEL_POS)
-#define STM32_RCC_CCIPR_SWPMI1SEL STM32_RCC_CCIPR_SWPMI1SEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
-#define STM32_RCC_BDCR_LSEBYP_POS 2U
-#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
-#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
-
-#define STM32_RCC_BDCR_LSEDRV_POS 3U
-#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
-#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
-
-#define STM32_RCC_BDCR_LSECSSON_POS 5U
-#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
-#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
-#define STM32_RCC_BDCR_LSECSSD_POS 6U
-#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
-#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
-
-#define STM32_RCC_BDCR_RTCSEL_POS 8U
-#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
-#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
-
-#define STM32_RCC_BDCR_LSCOEN_POS 24U
-#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
-#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
-#define STM32_RCC_BDCR_LSCOSEL_POS 25U
-#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
-#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
-#define STM32_RCC_CSR_LSION_POS 0U
-#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
-#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
-#define STM32_RCC_CSR_LSIRDY_POS 1U
-#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
-#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
-
-#define STM32_RCC_CSR_MSISRANGE_POS 8U
-#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
-#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
-
-#define STM32_RCC_CSR_RMVF_POS 23U
-#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
-#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
-#define STM32_RCC_CSR_FWRSTF_POS 24U
-#define STM32_RCC_CSR_FWRSTF_MSK (0x1UL << STM32_RCC_CSR_FWRSTF_POS)
-#define STM32_RCC_CSR_FWRSTF STM32_RCC_CSR_FWRSTF_MSK
-#define STM32_RCC_CSR_OBLRSTF_POS 25U
-#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
-#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
-#define STM32_RCC_CSR_PINRSTF_POS 26U
-#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
-#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
-#define STM32_RCC_CSR_BORRSTF_POS 27U
-#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
-#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
-#define STM32_RCC_CSR_SFTRSTF_POS 28U
-#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
-#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
-#define STM32_RCC_CSR_IWDGRSTF_POS 29U
-#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
-#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
-#define STM32_RCC_CSR_WWDGRSTF_POS 30U
-#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
-#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
-#define STM32_RCC_CSR_LPWRRSTF_POS 31U
-#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
-#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
-#define STM32_RCC_CRRCR_HSI48ON_POS 0U
-#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
-#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
-#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
-#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
-#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
-
-/*!< HSI48CAL configuration */
-#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
-#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
-#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-
-#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
-
-/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
-
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
-
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned int sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define STM32_FLASH_PCROP1SR        REG32(STM32_FLASH_REGS_BASE + 0x24)
-#define STM32_FLASH_PCROP1ER        REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x2C)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x30)
-/* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
-
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BASE + 0x20)
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT          BIT(18)
-
-/* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
-/* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
-/* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-	STM32_DMAC_CH15 = 14,
-
-	/* Channel functions */
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 15,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h
deleted file mode 100644
index d418362fce..0000000000
--- a/chip/stm32/registers-stm32l5.h
+++ /dev/null
@@ -1,2388 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32L5 family of chips
- *
- * This header file should not be included directly.
- * Please include registers.h instead.
- *
- * Known Chip Variants
- * - STM32L552
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#error "This header file should not be included directly."
-#endif
-
-/******  STM32 specific Interrupt Numbers ********/
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            6
-#define STM32_IRQ_FLASH_S          7
-#define STM32_IRQ_RCC              9
-#define STM32_IRQ_RCC_S           10
-#define STM32_IRQ_EXTI0           11
-#define STM32_IRQ_EXTI1           12
-#define STM32_IRQ_EXTI2           13
-#define STM32_IRQ_EXTI3           14
-#define STM32_IRQ_EXTI4           15
-#define STM32_IRQ_EXTI5           16
-#define STM32_IRQ_EXTI6           17
-#define STM32_IRQ_EXTI7           18
-#define STM32_IRQ_EXTI8           19
-#define STM32_IRQ_EXTI9           20
-#define STM32_IRQ_EXTI10          21
-#define STM32_IRQ_EXTI11          22
-#define STM32_IRQ_EXTI12          23
-#define STM32_IRQ_EXTI13          24
-#define STM32_IRQ_EXTI14          25
-#define STM32_IRQ_EXTI15          26
-#define STM32_IRQ_DMAMUX_OVR      27
-#define STM32_IRQ_DMAMUX_OVR_S    28
-#define STM32_IRQ_DMA_CHANNEL_1   29
-#define STM32_IRQ_DMA_CHANNEL_2   30
-#define STM32_IRQ_DMA_CHANNEL_3   31
-#define STM32_IRQ_DMA_CHANNEL_4   32
-#define STM32_IRQ_DMA_CHANNEL_5   33
-#define STM32_IRQ_DMA_CHANNEL_6   34
-#define STM32_IRQ_DMA_CHANNEL_7   35
-#define STM32_IRQ_DMA_CHANNEL_8   36
-#define STM32_IRQ_ADC1            37
-#define STM32_IRQ_TIM1_BRK        41
-#define STM32_IRQ_TIM1_UP         42
-#define STM32_IRQ_TIM1_TRG_COM    43
-#define STM32_IRQ_TIM1_CC         44
-#define STM32_IRQ_TIM2            45
-#define STM32_IRQ_TIM3            46
-#define STM32_IRQ_TIM4            47
-#define STM32_IRQ_TIM5            48
-#define STM32_IRQ_TIM6            49
-#define STM32_IRQ_TIM7            50
-#define STM32_IRQ_TIM8_BRK        51
-#define STM32_IRQ_TIM8_UP         52
-#define STM32_IRQ_TIM8_TRG_COM    53
-#define STM32_IRQ_TIM8_CC         54
-#define STM32_IRQ_I2C1_EV         55
-#define STM32_IRQ_I2C1_ER         56
-#define STM32_IRQ_I2C2_EV         57
-#define STM32_IRQ_I2C2_ER         58
-#define STM32_IRQ_SPI1            59
-#define STM32_IRQ_SPI2            60
-#define STM32_IRQ_USART1          61
-#define STM32_IRQ_USART2          62
-#define STM32_IRQ_USART3          63
-#define STM32_IRQ_USART4          64
-#define STM32_IRQ_USART5          65
-#define STM32_IRQ_LPUART          66
-#define STM32_IRQ_LPTIM1          67
-#define STM32_IRQ_LPTIM2          68
-#define STM32_IRQ_TIM15           69
-#define STM32_IRQ_TIM16           70
-#define STM32_IRQ_TIM17           71
-#define STM32_IRQ_COMP            72
-#define STM32_IRQ_USB_FS          73
-#define STM32_IRQ_CRS             74
-#define STM32_IRQ_FMC             75
-#define STM32_IRQ_DMA2_CHANNEL1   80
-#define STM32_IRQ_DMA2_CHANNEL2   81
-#define STM32_IRQ_DMA2_CHANNEL3   82
-#define STM32_IRQ_DMA2_CHANNEL4   83
-#define STM32_IRQ_DMA2_CHANNEL5   84
-#define STM32_IRQ_DMA2_CHANNEL6   85
-#define STM32_IRQ_DMA2_CHANNEL7   86
-#define STM32_IRQ_DMA2_CHANNEL8   87
-
-/* To simplify code generation, define DMA channel 9..16 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_DMA_CHANNEL_16   STM32_IRQ_DMA2_CHANNEL8
-
-/* aliases for easier code sharing */
-#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
-#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
-#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
-#define STM32_IRQ_USB_LP STM32_IRQ_USB_FS
-
-
-#define PERIPH_BASE           0x40000000UL
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x02000000UL)
-
-/*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
-#define STM32_TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_USART4_BASE           (APB1PERIPH_BASE + 0x4c00UL)
-#define STM32_USART5_BASE           (APB1PERIPH_BASE + 0x5000UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_USB_FS_BASE           (APB1PERIPH_BASE + 0xD400UL)
-#define STM32_USB_CAN_SRAM_BASE     (APB1PERIPH_BASE + 0xD800UL)
-
-/*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_EXTI_BASE             (AHB1PERIPH_BASE + 0xf400UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
-
-/*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE + 0x0000UL)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
-
-/*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x20000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x20400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x20800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x20C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x21000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x21400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x21800UL)
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x21C00UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0xC4000UL)
-
-/* Debug MCU registers base address */
-#define STM32_PACKAGE_BASE          0x0BFA0500UL
-#define STM32_UID_BASE              0x0BFA0590UL
-#define STM32_FLASHSIZE_BASE        0x0BFA05E0UL
-
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
-/* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
-
-/* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
-
-/* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
-
-/* --- Macro usage in ec code --- */
-#define STM32_RCC_AHB2ENR_GPIOMASK                               \
-	(STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \
-	 STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \
-	 STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN)
-#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
-
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
-#ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
-#endif
-#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
-
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
-#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
-#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
-#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
-#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
-#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
-#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
-#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
-/* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR       REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
-
-#define STM32_RCC_PLLSAI1_SUPPORT
-#define STM32_RCC_PLLP_SUPPORT
-#define STM32_RCC_HSI48_SUPPORT
-#define STM32_RCC_PLLP_DIV_2_31_SUPPORT
-#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
-
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
-
-/********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
-
-/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
-
-/********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
-/*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
-
-/*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
-
-/*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
-
-/*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
-/*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
-
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
-
-/*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
-
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
-
-/*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
-
-/*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
-
-/*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
-
-/*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
-
-/* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
-
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \
-	(0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
-	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-
-/****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \
-	(0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \
-	(0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
-	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \
-	(0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \
-	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \
-	(0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS)
-
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \
-	(0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \
-	(0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \
-	(0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \
-	(0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \
-	(0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \
-	(0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIER REGISTER  ******************/
-#define STM32_RCC_CIER_LSIRDYIE_POS 0U
-#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS)
-#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK
-#define STM32_RCC_CIER_LSERDYIE_POS 1U
-#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS)
-#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK
-#define STM32_RCC_CIER_MSIRDYIE_POS 2U
-#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS)
-#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK
-#define STM32_RCC_CIER_HSIRDYIE_POS 3U
-#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS)
-#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK
-#define STM32_RCC_CIER_HSERDYIE_POS 4U
-#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS)
-#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK
-#define STM32_RCC_CIER_PLLRDYIE_POS 5U
-#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS)
-#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U
-#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK
-#define STM32_RCC_CIER_PLLSAI2RDYIE_POS 7U
-#define STM32_RCC_CIER_PLLSAI2RDYIE_MSK \
-	(0x1UL << STM32_RCC_CIER_PLLSAI2RDYIE_POS)
-#define STM32_RCC_CIER_PLLSAI2RDYIE STM32_RCC_CIER_PLLSAI2RDYIE_MSK
-#define STM32_RCC_CIER_HSI48RDYIE_POS 10U
-#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS)
-#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CIFR REGISTER  ******************/
-#define STM32_RCC_CIFR_LSIRDYF_POS 0U
-#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS)
-#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK
-#define STM32_RCC_CIFR_LSERDYF_POS 1U
-#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS)
-#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK
-#define STM32_RCC_CIFR_MSIRDYF_POS 2U
-#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS)
-#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK
-#define STM32_RCC_CIFR_HSIRDYF_POS 3U
-#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS)
-#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK
-#define STM32_RCC_CIFR_HSERDYF_POS 4U
-#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS)
-#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK
-#define STM32_RCC_CIFR_PLLRDYF_POS 5U
-#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS)
-#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U
-#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK
-#define STM32_RCC_CIFR_PLLSAI2RDYF_POS 7U
-#define STM32_RCC_CIFR_PLLSAI2RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI2RDYF_POS)
-#define STM32_RCC_CIFR_PLLSAI2RDYF STM32_RCC_CIFR_PLLSAI2RDYF_MSK
-#define STM32_RCC_CIFR_CSSF_POS 8U
-#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS)
-#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK
-#define STM32_RCC_CIFR_HSI48RDYF_POS 10U
-#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS)
-#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CICR REGISTER  ******************/
-#define STM32_RCC_CICR_LSIRDYC_POS 0U
-#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS)
-#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK
-#define STM32_RCC_CICR_LSERDYC_POS 1U
-#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS)
-#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK
-#define STM32_RCC_CICR_MSIRDYC_POS 2U
-#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS)
-#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK
-#define STM32_RCC_CICR_HSIRDYC_POS 3U
-#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS)
-#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK
-#define STM32_RCC_CICR_HSERDYC_POS 4U
-#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS)
-#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK
-#define STM32_RCC_CICR_PLLRDYC_POS 5U
-#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS)
-#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK
-#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U
-#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK
-#define STM32_RCC_CICR_PLLSAI2RDYC_POS 7U
-#define STM32_RCC_CICR_PLLSAI2RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI2RDYC_POS)
-#define STM32_RCC_CICR_PLLSAI2RDYC STM32_RCC_CICR_PLLSAI2RDYC_MSK
-#define STM32_RCC_CICR_CSSC_POS 8U
-#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS)
-#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK
-#define STM32_RCC_CICR_HSI48RDYC_POS 10U
-#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS)
-#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER  **************/
-#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U
-#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK
-#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U
-#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS)
-#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST_POS 2U
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_DMAMUX1RST_POS)
-#define STM32_RCC_AHB1RSTR_DMAMUX1RST STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK
-#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U
-#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \
-	(0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS)
-#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK
-#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U
-#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS)
-#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK
-#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U
-#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS)
-#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER  **************/
-#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U
-#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U
-#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U
-#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U
-#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U
-#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOFRST_POS 5U
-#define STM32_RCC_AHB2RSTR_GPIOFRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOFRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOFRST STM32_RCC_AHB2RSTR_GPIOFRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOGRST_POS 6U
-#define STM32_RCC_AHB2RSTR_GPIOGRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOGRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOGRST STM32_RCC_AHB2RSTR_GPIOGRST_MSK
-#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U
-#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \
-	(0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS)
-#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK
-#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U
-#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS)
-#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK
-#define STM32_RCC_AHB2RSTR_AESRST_POS 16U
-#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS)
-#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK
-#define STM32_RCC_AHB2RSTR_HASHRST_POS 17U
-#define STM32_RCC_AHB2RSTR_HASHRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_HASHRST_POS)
-#define STM32_RCC_AHB2RSTR_HASHRST STM32_RCC_AHB2RSTR_HASHRST_MSK
-#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U
-#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS)
-#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER  **************/
-#define STM32_RCC_AHB3RSTR_FMCRST_POS 0U
-#define STM32_RCC_AHB3RSTR_FMCRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_FMCRST_POS)
-#define STM32_RCC_AHB3RSTR_FMCRST STM32_RCC_AHB3RSTR_FMCRST_MSK
-#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U
-#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS)
-#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER  **************/
-#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U
-#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM3RST_POS 1U
-#define STM32_RCC_APB1RSTR1_TIM3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM3RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM3RST STM32_RCC_APB1RSTR1_TIM3RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM4RST_POS 2U
-#define STM32_RCC_APB1RSTR1_TIM4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM4RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM4RST STM32_RCC_APB1RSTR1_TIM4RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM5RST_POS 3U
-#define STM32_RCC_APB1RSTR1_TIM5RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM5RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM5RST STM32_RCC_APB1RSTR1_TIM5RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U
-#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK
-#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U
-#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS)
-#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U
-#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK
-#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U
-#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS)
-#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U
-#define STM32_RCC_APB1RSTR1_USART2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS)
-#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK
-#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U
-#define STM32_RCC_APB1RSTR1_USART3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS)
-#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK
-#define STM32_RCC_APB1RSTR1_USART4RST_POS 19U
-#define STM32_RCC_APB1RSTR1_USART4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART4RST_POS)
-#define STM32_RCC_APB1RSTR1_USART4RST STM32_RCC_APB1RSTR1_USART4RST_MSK
-#define STM32_RCC_APB1RSTR1_USART5RST_POS 20U
-#define STM32_RCC_APB1RSTR1_USART5RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_USART5RST_POS)
-#define STM32_RCC_APB1RSTR1_USART5RST STM32_RCC_APB1RSTR1_USART5RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U
-#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U
-#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK
-#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U
-#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS)
-#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK
-#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U
-#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS)
-#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK
-#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U
-#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS)
-#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK
-#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U
-#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS)
-#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK
-#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U
-#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS)
-#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U
-#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS)
-#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U
-#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS)
-#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK
-#define STM32_RCC_APB1RSTR2_I2C4RST_POS 1U
-#define STM32_RCC_APB1RSTR2_I2C4RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_I2C4RST_POS)
-#define STM32_RCC_APB1RSTR2_I2C4RST STM32_RCC_APB1RSTR2_I2C4RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U
-#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK
-#define STM32_RCC_APB1RSTR2_LPTIM3RST_POS 6U
-#define STM32_RCC_APB1RSTR2_LPTIM3RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_LPTIM3RST_POS)
-#define STM32_RCC_APB1RSTR2_LPTIM3RST STM32_RCC_APB1RSTR2_LPTIM3RST_MSK
-#define STM32_RCC_APB1RSTR2_FDCAN1RST_POS 9U
-#define STM32_RCC_APB1RSTR2_FDCAN1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_FDCAN1RST_POS)
-#define STM32_RCC_APB1RSTR2_FDCAN1RST STM32_RCC_APB1RSTR2_FDCAN1RST_MSK
-#define STM32_RCC_APB1RSTR2_USBFSRST_POS 21U
-#define STM32_RCC_APB1RSTR2_USBFSRST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_USBFSRST_POS)
-#define STM32_RCC_APB1RSTR2_USBFSRST STM32_RCC_APB1RSTR2_USBFSRST_MSK
-#define STM32_RCC_APB1RSTR2_UCPD1RST_POS 23U
-#define STM32_RCC_APB1RSTR2_UCPD1RST_MSK \
-	(0x1UL << STM32_RCC_APB1RSTR2_UCPD1RST_POS)
-#define STM32_RCC_APB1RSTR2_UCPD1RST STM32_RCC_APB1RSTR2_UCPD1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER  **************/
-#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U
-#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS)
-#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK
-#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U
-#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS)
-#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK
-#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U
-#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS)
-#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM8RST_POS 13U
-#define STM32_RCC_APB2RSTR_TIM8RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM8RST_POS)
-#define STM32_RCC_APB2RSTR_TIM8RST STM32_RCC_APB2RSTR_TIM8RST_MSK
-#define STM32_RCC_APB2RSTR_USART1RST_POS 14U
-#define STM32_RCC_APB2RSTR_USART1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS)
-#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK
-#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U
-#define STM32_RCC_APB2RSTR_TIM15RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS)
-#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK
-#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U
-#define STM32_RCC_APB2RSTR_TIM16RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS)
-#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK
-#define STM32_RCC_APB2RSTR_TIM17RST_POS 18U
-#define STM32_RCC_APB2RSTR_TIM17RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_TIM17RST_POS)
-#define STM32_RCC_APB2RSTR_TIM17RST STM32_RCC_APB2RSTR_TIM17RST_MSK
-#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U
-#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS)
-#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK
-#define STM32_RCC_APB2RSTR_SAI2RST_POS 22U
-#define STM32_RCC_APB2RSTR_SAI2RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI2RST_POS)
-#define STM32_RCC_APB2RSTR_SAI2RST STM32_RCC_APB2RSTR_SAI2RST_MSK
-#define STM32_RCC_APB2RSTR_DFSDM1RST_POS 24U
-#define STM32_RCC_APB2RSTR_DFSDM1RST_MSK \
-	(0x1UL << STM32_RCC_APB2RSTR_DFSDM1RST_POS)
-#define STM32_RCC_APB2RSTR_DFSDM1RST STM32_RCC_APB2RSTR_DFSDM1RST_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER  ***************/
-#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U
-#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS)
-#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK
-#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U
-#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
-#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
-#define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U
-#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS)
-#define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
-#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
-#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
-#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
-#define STM32_RCC_AHB1ENR_CRCEN_POS 12U
-#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS)
-#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK
-#define STM32_RCC_AHB1ENR_TSCEN_POS 16U
-#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS)
-#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK
-#define STM32_RCC_AHB1ENR_GTZCEN_POS 22U
-#define STM32_RCC_AHB1ENR_GTZCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_GTZCEN_POS)
-#define STM32_RCC_AHB1ENR_GTZCEN STM32_RCC_AHB1ENR_GTZCEN_MSK
-
-/***************  BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER  *********/
-#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U
-#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U
-#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U
-#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK
-#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U
-#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS)
-#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U
-#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOFEN_POS 5U
-#define STM32_RCC_AHB2ENR_GPIOFEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOFEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOFEN STM32_RCC_AHB2ENR_GPIOFEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOGEN_POS 6U
-#define STM32_RCC_AHB2ENR_GPIOGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOGEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOGEN STM32_RCC_AHB2ENR_GPIOGEN_MSK
-#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U
-#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS)
-#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK
-#define STM32_RCC_AHB2ENR_ADCEN_POS 13U
-#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS)
-#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK
-#define STM32_RCC_AHB2ENR_AESEN_POS 16U
-#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS)
-#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK
-#define STM32_RCC_AHB2ENR_HASHEN_POS 17U
-#define STM32_RCC_AHB2ENR_HASHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_HASHEN_POS)
-#define STM32_RCC_AHB2ENR_HASHEN STM32_RCC_AHB2ENR_HASHEN_MSK
-#define STM32_RCC_AHB2ENR_RNGEN_POS 18U
-#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS)
-#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK
-#define STM32_RCC_AHB2ENR_PKAEN_POS 19U
-#define STM32_RCC_AHB2ENR_PKAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_PKAEN_POS)
-#define STM32_RCC_AHB2ENR_PKAEN STM32_RCC_AHB2ENR_PKAEN_MSK
-#define STM32_RCC_AHB2ENR_OTFDEC1EN_POS 21U
-#define STM32_RCC_AHB2ENR_OTFDEC1EN_MSK \
-	(0x1UL << STM32_RCC_AHB2ENR_OTFDEC1EN_POS)
-#define STM32_RCC_AHB2ENR_OTFDEC1EN STM32_RCC_AHB2ENR_OTFDEC1EN_MSK
-#define STM32_RCC_AHB2ENR_SDMMC1EN_POS 22U
-#define STM32_RCC_AHB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_AHB2ENR_SDMMC1EN_POS)
-#define STM32_RCC_AHB2ENR_SDMMC1EN STM32_RCC_AHB2ENR_SDMMC1EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER  ***************/
-#define STM32_RCC_AHB3ENR_FMCEN_POS 0U
-#define STM32_RCC_AHB3ENR_FMCEN_MSK (0x1UL << STM32_RCC_AHB3ENR_FMCEN_POS)
-#define STM32_RCC_AHB3ENR_FMCEN STM32_RCC_AHB3ENR_FMCEN_MSK
-#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U
-#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS)
-#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER  **************/
-#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U
-#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS)
-#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK
-#define STM32_RCC_APB1ENR1_TIM3EN_POS 1U
-#define STM32_RCC_APB1ENR1_TIM3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM3EN_POS)
-#define STM32_RCC_APB1ENR1_TIM3EN STM32_RCC_APB1ENR1_TIM3EN_MSK
-#define STM32_RCC_APB1ENR1_TIM4EN_POS 2U
-#define STM32_RCC_APB1ENR1_TIM4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM4EN_POS)
-#define STM32_RCC_APB1ENR1_TIM4EN STM32_RCC_APB1ENR1_TIM4EN_MSK
-#define STM32_RCC_APB1ENR1_TIM5EN_POS 3U
-#define STM32_RCC_APB1ENR1_TIM5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM5EN_POS)
-#define STM32_RCC_APB1ENR1_TIM5EN STM32_RCC_APB1ENR1_TIM5EN_MSK
-#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U
-#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS)
-#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK
-#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U
-#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS)
-#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK
-#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U
-#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS)
-#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK
-#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U
-#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS)
-#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK
-#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U
-#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS)
-#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK
-#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U
-#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS)
-#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK
-#define STM32_RCC_APB1ENR1_USART2EN_POS 17U
-#define STM32_RCC_APB1ENR1_USART2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS)
-#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK
-#define STM32_RCC_APB1ENR1_USART3EN_POS 18U
-#define STM32_RCC_APB1ENR1_USART3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
-#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
-#define STM32_RCC_APB1ENR1_UART4EN_POS 19U
-#define STM32_RCC_APB1ENR1_UART4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS)
-#define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK
-#define STM32_RCC_APB1ENR1_UART5EN_POS 20U
-#define STM32_RCC_APB1ENR1_UART5EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS)
-#define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK
-#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
-#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
-#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK
-#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U
-#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS)
-#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK
-#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U
-#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS)
-#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK
-#define STM32_RCC_APB1ENR1_CRSEN_POS 24U
-#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS)
-#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK
-#define STM32_RCC_APB1ENR1_PWREN_POS 28U
-#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS)
-#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK
-#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U
-#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS)
-#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK
-#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U
-#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS)
-#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK
-#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U
-#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS)
-#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER  **************/
-#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U
-#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
-#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
-#define STM32_RCC_APB1ENR2_I2C4EN_POS 1U
-#define STM32_RCC_APB1ENR2_I2C4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
-#define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
-#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK
-#define STM32_RCC_APB1ENR2_LPTIM3EN_POS 6U
-#define STM32_RCC_APB1ENR2_LPTIM3EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_LPTIM3EN_POS)
-#define STM32_RCC_APB1ENR2_LPTIM3EN STM32_RCC_APB1ENR2_LPTIM3EN_MSK
-#define STM32_RCC_APB1ENR2_FDCAN1EN_POS 9U
-#define STM32_RCC_APB1ENR2_FDCAN1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS)
-#define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK
-#define STM32_RCC_APB1ENR2_USBFSEN_POS 21U
-#define STM32_RCC_APB1ENR2_USBFSEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS)
-#define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK
-#define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U
-#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS)
-#define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
-#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U
-#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS)
-#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK
-#define STM32_RCC_APB2ENR_TIM1EN_POS 11U
-#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS)
-#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK
-#define STM32_RCC_APB2ENR_SPI1EN_POS 12U
-#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS)
-#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK
-#define STM32_RCC_APB2ENR_TIM8EN_POS 13U
-#define STM32_RCC_APB2ENR_TIM8EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM8EN_POS)
-#define STM32_RCC_APB2ENR_TIM8EN STM32_RCC_APB2ENR_TIM8EN_MSK
-#define STM32_RCC_APB2ENR_USART1EN_POS 14U
-#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS)
-#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK
-#define STM32_RCC_APB2ENR_TIM15EN_POS 16U
-#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS)
-#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK
-#define STM32_RCC_APB2ENR_TIM16EN_POS 17U
-#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS)
-#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK
-#define STM32_RCC_APB2ENR_TIM17EN_POS 18U
-#define STM32_RCC_APB2ENR_TIM17EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM17EN_POS)
-#define STM32_RCC_APB2ENR_TIM17EN STM32_RCC_APB2ENR_TIM17EN_MSK
-#define STM32_RCC_APB2ENR_SAI1EN_POS 21U
-#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS)
-#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK
-#define STM32_RCC_APB2ENR_SAI2EN_POS 22U
-#define STM32_RCC_APB2ENR_SAI2EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI2EN_POS)
-#define STM32_RCC_APB2ENR_SAI2EN STM32_RCC_APB2ENR_SAI2EN_MSK
-#define STM32_RCC_APB2ENR_DFSDM1EN_POS 24U
-#define STM32_RCC_APB2ENR_DFSDM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_DFSDM1EN_POS)
-#define STM32_RCC_APB2ENR_DFSDM1EN STM32_RCC_APB2ENR_DFSDM1EN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER  ***************/
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U
-#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U
-#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS 2U
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U
-#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS)
-#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS)
-#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK
-#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U
-#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U
-#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_GTZCSMEN_POS 22U
-#define STM32_RCC_AHB1SMENR_GTZCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_GTZCSMEN_POS)
-#define STM32_RCC_AHB1SMENR_GTZCSMEN STM32_RCC_AHB1SMENR_GTZCSMEN_MSK
-#define STM32_RCC_AHB1SMENR_ICACHESMEN_POS 23U
-#define STM32_RCC_AHB1SMENR_ICACHESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB1SMENR_ICACHESMEN_POS)
-#define STM32_RCC_AHB1SMENR_ICACHESMEN STM32_RCC_AHB1SMENR_ICACHESMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER  *************/
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U
-#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U
-#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U
-#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN_POS 5U
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOFSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOFSMEN STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN_POS 6U
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOGSMEN STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK
-#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U
-#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS)
-#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK
-#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U
-#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS)
-#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK
-#define STM32_RCC_AHB2SMENR_HASHSMEN_POS 17U
-#define STM32_RCC_AHB2SMENR_HASHSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_HASHSMEN_POS)
-#define STM32_RCC_AHB2SMENR_HASHSMEN STM32_RCC_AHB2SMENR_HASHSMEN_MSK
-#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U
-#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS)
-#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK
-#define STM32_RCC_AHB2SMENR_PKASMEN_POS 19U
-#define STM32_RCC_AHB2SMENR_PKASMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_PKASMEN_POS)
-#define STM32_RCC_AHB2SMENR_PKASMEN STM32_RCC_AHB2SMENR_PKASMEN_MSK
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS 21U
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS)
-#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS 22U
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK \
-	(0x1UL << STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS)
-#define STM32_RCC_AHB2SMENR_SDMMC1SMEN STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER  *************/
-#define STM32_RCC_AHB3SMENR_FMCSMEN_POS 0U
-#define STM32_RCC_AHB3SMENR_FMCSMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_FMCSMEN_POS)
-#define STM32_RCC_AHB3SMENR_FMCSMEN STM32_RCC_AHB3SMENR_FMCSMEN_MSK
-#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U
-#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \
-	(0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS)
-#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER  *************/
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U
-#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM3SMEN_POS 1U
-#define STM32_RCC_APB1SMENR1_TIM3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM3SMEN STM32_RCC_APB1SMENR1_TIM3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM4SMEN_POS 2U
-#define STM32_RCC_APB1SMENR1_TIM4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM4SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM4SMEN STM32_RCC_APB1SMENR1_TIM4SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM5SMEN_POS 3U
-#define STM32_RCC_APB1SMENR1_TIM5SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM5SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM5SMEN STM32_RCC_APB1SMENR1_TIM5SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U
-#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U
-#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS)
-#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS)
-#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U
-#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS)
-#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U
-#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U
-#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U
-#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U
-#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART4SMEN_POS 19U
-#define STM32_RCC_APB1SMENR1_USART4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART4SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART4SMEN STM32_RCC_APB1SMENR1_USART4SMEN_MSK
-#define STM32_RCC_APB1SMENR1_USART5SMEN_POS 20U
-#define STM32_RCC_APB1SMENR1_USART5SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_USART5SMEN_POS)
-#define STM32_RCC_APB1SMENR1_USART5SMEN STM32_RCC_APB1SMENR1_USART5SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U
-#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U
-#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U
-#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS)
-#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK
-#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U
-#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS)
-#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK
-#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U
-#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS)
-#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U
-#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS)
-#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS)
-#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER  *************/
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_I2C4SMEN_POS 1U
-#define STM32_RCC_APB1SMENR2_I2C4SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_I2C4SMEN_POS)
-#define STM32_RCC_APB1SMENR2_I2C4SMEN STM32_RCC_APB1SMENR2_I2C4SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS 6U
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS)
-#define STM32_RCC_APB1SMENR2_LPTIM3SMEN STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS 9U
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_FDCAN1SMEN STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK
-#define STM32_RCC_APB1SMENR2_USBFSSMEN_POS 21U
-#define STM32_RCC_APB1SMENR2_USBFSSMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_USBFSSMEN_POS)
-#define STM32_RCC_APB1SMENR2_USBFSSMEN STM32_RCC_APB1SMENR2_USBFSSMEN_MSK
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN_POS 23U
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB1SMENR2_UCPD1SMEN_POS)
-#define STM32_RCC_APB1SMENR2_UCPD1SMEN STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK
-
-/************  BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER  *************/
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS)
-#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U
-#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U
-#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM8SMEN_POS 13U
-#define STM32_RCC_APB2SMENR_TIM8SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM8SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM8SMEN STM32_RCC_APB2SMENR_TIM8SMEN_MSK
-#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U
-#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS)
-#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U
-#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U
-#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK
-#define STM32_RCC_APB2SMENR_TIM17SMEN_POS 18U
-#define STM32_RCC_APB2SMENR_TIM17SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_TIM17SMEN_POS)
-#define STM32_RCC_APB2SMENR_TIM17SMEN STM32_RCC_APB2SMENR_TIM17SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U
-#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK
-#define STM32_RCC_APB2SMENR_SAI2SMEN_POS 22U
-#define STM32_RCC_APB2SMENR_SAI2SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_SAI2SMEN_POS)
-#define STM32_RCC_APB2SMENR_SAI2SMEN STM32_RCC_APB2SMENR_SAI2SMEN_MSK
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN_POS 24U
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK \
-	(0x1UL << STM32_RCC_APB2SMENR_DFSDM1SMEN_POS)
-#define STM32_RCC_APB2SMENR_DFSDM1SMEN STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK
-
-/*************  BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER  ******************/
-#define STM32_RCC_CCIPR_USART1SEL_POS 0U
-#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK
-#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS)
-#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS)
-
-#define STM32_RCC_CCIPR_USART2SEL_POS 2U
-#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK
-#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS)
-#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS)
-
-#define STM32_RCC_CCIPR_USART3SEL_POS 4U
-#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK
-#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS)
-#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS)
-
-#define STM32_RCC_CCIPR_USART4SEL_POS 6U
-#define STM32_RCC_CCIPR_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS)
-#define STM32_RCC_CCIPR_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK
-#define STM32_RCC_CCIPR_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS)
-#define STM32_RCC_CCIPR_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS)
-
-#define STM32_RCC_CCIPR_USART5SEL_POS 8U
-#define STM32_RCC_CCIPR_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS)
-#define STM32_RCC_CCIPR_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK
-#define STM32_RCC_CCIPR_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS)
-#define STM32_RCC_CCIPR_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS)
-
-#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U
-#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK
-#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C1SEL_POS 12U
-#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK
-#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C2SEL_POS 14U
-#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK
-#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS)
-
-#define STM32_RCC_CCIPR_I2C3SEL_POS 16U
-#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK
-#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U
-#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U
-#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS)
-
-#define STM32_RCC_CCIPR_LPTIM3SEL_POS 22U
-#define STM32_RCC_CCIPR_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK
-#define STM32_RCC_CCIPR_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-#define STM32_RCC_CCIPR_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS)
-
-#define STM32_RCC_CCIPR_FDCANSEL_POS 24U
-#define STM32_RCC_CCIPR_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-#define STM32_RCC_CCIPR_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK
-#define STM32_RCC_CCIPR_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-#define STM32_RCC_CCIPR_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS)
-
-#define STM32_RCC_CCIPR_CLK48SEL_POS 26U
-#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK
-#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS)
-
-#define STM32_RCC_CCIPR_ADCSEL_POS 28U
-#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK
-#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS)
-#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS)
-
-/**************  BIT DEFINITION FOR STM32_RCC_BDCR REGISTER  ******************/
-#define STM32_RCC_BDCR_LSEBYP_POS 2U
-#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS)
-#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK
-
-#define STM32_RCC_BDCR_LSEDRV_POS 3U
-#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK
-#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS)
-#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS)
-
-#define STM32_RCC_BDCR_LSECSSON_POS 5U
-#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS)
-#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK
-#define STM32_RCC_BDCR_LSECSSD_POS 6U
-#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS)
-#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK
-#define STM32_RCC_BDCR_LSESYSEN_POS 7U
-#define STM32_RCC_BDCR_LSESYSEN_MSK (0x1UL << STM32_RCC_BDCR_LSESYSEN_POS)
-#define STM32_RCC_BDCR_LSESYSEN STM32_RCC_BDCR_LSESYSEN_MSK
-
-#define STM32_RCC_BDCR_RTCSEL_POS 8U
-#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK
-#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS)
-#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS)
-
-#define STM32_RCC_BDCR_LSESYSRDY_POS 11U
-#define STM32_RCC_BDCR_LSESYSRDY_MSK (0x1UL << STM32_RCC_BDCR_LSESYSRDY_POS)
-#define STM32_RCC_BDCR_LSESYSRDY STM32_RCC_BDCR_LSESYSRDY_MSK
-#define STM32_RCC_BDCR_LSCOEN_POS 24U
-#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS)
-#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK
-#define STM32_RCC_BDCR_LSCOSEL_POS 25U
-#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS)
-#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK
-
-/**************  BIT DEFINITION FOR STM32_RCC_CSR REGISTER  *******************/
-#define STM32_RCC_CSR_LSION_POS 0U
-#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS)
-#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK
-#define STM32_RCC_CSR_LSIRDY_POS 1U
-#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS)
-#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK
-#define STM32_RCC_CSR_LSIPRE_POS 4U
-#define STM32_RCC_CSR_LSIPRE_MSK (0x1UL << STM32_RCC_CSR_LSIPRE_POS)
-#define STM32_RCC_CSR_LSIPRE STM32_RCC_CSR_LSIPRE_MSK
-
-#define STM32_RCC_CSR_MSISRANGE_POS 8U
-#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK
-#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS)
-#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS)
-
-#define STM32_RCC_CSR_RMVF_POS 23U
-#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS)
-#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK
-#define STM32_RCC_CSR_OBLRSTF_POS 25U
-#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS)
-#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK
-#define STM32_RCC_CSR_PINRSTF_POS 26U
-#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS)
-#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK
-#define STM32_RCC_CSR_BORRSTF_POS 27U
-#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS)
-#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK
-#define STM32_RCC_CSR_SFTRSTF_POS 28U
-#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS)
-#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK
-#define STM32_RCC_CSR_IWDGRSTF_POS 29U
-#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS)
-#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK
-#define STM32_RCC_CSR_WWDGRSTF_POS 30U
-#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS)
-#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK
-#define STM32_RCC_CSR_LPWRRSTF_POS 31U
-#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS)
-#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR register  *****************/
-#define STM32_RCC_CRRCR_HSI48ON_POS 0U
-#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS)
-#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK
-#define STM32_RCC_CRRCR_HSI48RDY_POS 1U
-#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS)
-#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK
-
-/**************  Bit definition for STM32_RCC_CRRCR2 register  ****************/
-/* TODO */
-
-/**************  Bit definition for STM32_RCC_DLYCFGR register  ***************/
-/* TODO */
-
-/**************  Bit definition for STM32_RCC_CCIPR2 register  ****************/
-/* TODO */
-
-
-/*!< HSI48CAL configuration */
-#define STM32_RCC_CRRCR_HSI48CAL_POS 7U
-#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK
-#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS)
-
-#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
-
-/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
-
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
-
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
-
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
-
-/* Reset causes definitions */
-/* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
-/* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
-
-/* --- Watchdogs --- */
-
-/* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
-
-/* --- SPI --- */
-
-/* The SPI controller registers */
-struct stm32_spi_regs {
-	uint16_t cr1;
-	uint16_t _pad0;
-	uint16_t cr2;
-	uint16_t _pad1;
-	unsigned int sr;
-	uint8_t dr;
-	uint8_t _pad2;
-	uint16_t _pad3;
-	unsigned int crcpr;
-	unsigned int rxcrcr;
-	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
-
-#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
-#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
-#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
-#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
-
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
-/* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-
-/* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x30)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x40)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x58)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x5C)
-/* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
-
-#define STM32_OPTB_WRP1AR           STM32_FLASH_WRP1AR
-#define STM32_OPTB_WRP1BR           STM32_FLASH_WRP1BR
-
-/* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
-#define EXTI_RTC_ALR_EVENT          BIT(18)
-
-/* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-/* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
-/* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
-/* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
-/* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
-/* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
-/* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- DMA --- */
-
-/*
- * Available DMA channels, numbered from 0.
- *
- * Note: The STM datasheet tends to number things from 1. We should ask
- * the European elevator engineers to talk to MCU engineer counterparts
- * about this.  This means that if the datasheet refers to channel n,
- * you need to use STM32_DMAC_CHn (=n-1) in the code.
- *
- * Also note that channels are overloaded; obviously you can only use one
- * function on each channel at a time.
- */
-enum dma_channel {
-	/* Channel numbers */
-	STM32_DMAC_CH1 = 0,
-	STM32_DMAC_CH2 = 1,
-	STM32_DMAC_CH3 = 2,
-	STM32_DMAC_CH4 = 3,
-	STM32_DMAC_CH5 = 4,
-	STM32_DMAC_CH6 = 5,
-	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
-	STM32_DMAC_CH9 = 8,
-	STM32_DMAC_CH10 = 9,
-	STM32_DMAC_CH11 = 10,
-	STM32_DMAC_CH12 = 11,
-	STM32_DMAC_CH13 = 12,
-	STM32_DMAC_CH14 = 13,
-	STM32_DMAC_CH15 = 14,
-
-	/* Channel functions */
-	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
-	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
-	STM32_DMAC_USART1_TX = STM32_DMAC_CH14,
-	STM32_DMAC_USART1_RX = STM32_DMAC_CH15,
-	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
-	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
-	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
-	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
-	STM32_DMAC_COUNT = 15,
-};
-
-#define STM32_DMAC_PER_CTLR 8
-
-/* Registers for a single channel of the DMA controller */
-struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
-};
-
-/* Always use stm32_dma_chan_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
-
-/* Common code and header file must use this */
-typedef stm32_dma_chan_t dma_chan_t;
-
-/* Registers for the DMA controller */
-struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
-};
-
-/* Always use stm32_dma_regs_t so volatile keyword is included! */
-typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
-
-#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
-
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
-#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
-#define STM32_DMA_REGS(channel) \
-	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
-
-/* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
-#define STM32_DMA_ISR_MASK(channel, mask) \
-	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
-
-/* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
-#endif /* !__ASSEMBLER__ */
-
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
deleted file mode 100644
index 74a195a54e..0000000000
--- a/chip/stm32/registers.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Register map for the STM32 family of chips
- *
- * This header file should only contain register definitions and
- * functionality that are common to all STM32 chips.
- * Any chip/family specific macros must be placed in their family
- * specific registers file, which is conditionally included at the
- * end of this file.
- * Include this file directly for all STM32 register definitions.
- *
- * ### History and Reasoning ###
- * In a time before chip family register file separation,
- * long long ago, there lived a single file called `registers.h`,
- * which housed register definitions for all STM32 chip family and variants.
- * This poor file was 3000 lines of register macros and C definitions,
- * swiss-cheesed by nested preprocessor conditional logic.
- * Adding a single new chip variant required splitting multiple,
- * already nested, conditional sections throughout the file.
- * Readability was on the difficult side and refactoring was dangerous.
- *
- * The number of STM32 variants had outgrown the single registers file model.
- * The minor gains of sharing a set of registers between a subset of chip
- * variants no longer outweighed the complexity of the following operations:
- * - Adding a new chip variant or variant feature
- * - Determining if a register was properly setup for a variant or if it
- *   was simply not unset
- *
- * To strike a balance between shared registers and chip specific registers,
- * the registers.h file remains a place for common definitions, but family
- * specific definitions were moved to their own files.
- * These family specific files contain a much reduced level of preprocessor
- * logic for variant specific registers.
- *
- * See https://crrev.com/c/1674679 to witness the separation steps.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-
-
-#ifndef __ASSEMBLER__
-
-/* Register definitions */
-
-/* --- USART --- */
-#define STM32_USART_BASE(n)           CONCAT3(STM32_USART, n, _BASE)
-#define STM32_USART_REG(base, offset) REG32((base) + (offset))
-
-#define STM32_IRQ_USART(n)         CONCAT2(STM32_IRQ_USART, n)
-
-/* --- TIMERS --- */
-#define STM32_TIM_BASE(n)          CONCAT3(STM32_TIM, n, _BASE)
-
-#define STM32_TIM_REG(n, offset) \
-		REG16(STM32_TIM_BASE(n) + (offset))
-#define STM32_TIM_REG32(n, offset) \
-		REG32(STM32_TIM_BASE(n) + (offset))
-
-#define STM32_TIM_CR1(n)           STM32_TIM_REG(n, 0x00)
-#define STM32_TIM_CR1_CEN		BIT(0)
-#define STM32_TIM_CR2(n)           STM32_TIM_REG(n, 0x04)
-#define STM32_TIM_SMCR(n)          STM32_TIM_REG(n, 0x08)
-#define STM32_TIM_DIER(n)          STM32_TIM_REG(n, 0x0C)
-#define STM32_TIM_SR(n)            STM32_TIM_REG(n, 0x10)
-#define STM32_TIM_EGR(n)           STM32_TIM_REG(n, 0x14)
-#define STM32_TIM_EGR_UG		BIT(0)
-#define STM32_TIM_CCMR1(n)         STM32_TIM_REG(n, 0x18)
-#define STM32_TIM_CCMR1_OC1PE		BIT(2)
-/* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */
-#define STM32_TIM_CCMR1_OC1M(n)    (((n) & 0x7) << 4)
-#define STM32_TIM_CCMR1_OC1M_MASK              STM32_TIM_CCMR1_OC1M(~0)
-#define STM32_TIM_CCMR1_OC1M_FROZEN            STM32_TIM_CCMR1_OC1M(0x0)
-#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH   STM32_TIM_CCMR1_OC1M(0x1)
-#define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2)
-#define STM32_TIM_CCMR1_OC1M_TOGGLE            STM32_TIM_CCMR1_OC1M(0x3)
-#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE    STM32_TIM_CCMR1_OC1M(0x4)
-#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE      STM32_TIM_CCMR1_OC1M(0x5)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1        STM32_TIM_CCMR1_OC1M(0x6)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2        STM32_TIM_CCMR1_OC1M(0x7)
-#define STM32_TIM_CCMR2(n)         STM32_TIM_REG(n, 0x1C)
-#define STM32_TIM_CCER(n)          STM32_TIM_REG(n, 0x20)
-#define STM32_TIM_CCER_CC1E		BIT(0)
-#define STM32_TIM_CCER_CC1P		BIT(1)
-#define STM32_TIM_CCER_CC1NE		BIT(2)
-#define STM32_TIM_CCER_CC1NP		BIT(3)
-#define STM32_TIM_CNT(n)           STM32_TIM_REG(n, 0x24)
-#define STM32_TIM_PSC(n)           STM32_TIM_REG(n, 0x28)
-#define STM32_TIM_ARR(n)           STM32_TIM_REG(n, 0x2C)
-#define STM32_TIM_RCR(n)           STM32_TIM_REG(n, 0x30)
-#define STM32_TIM_CCR1(n)          STM32_TIM_REG(n, 0x34)
-#define STM32_TIM_CCR2(n)          STM32_TIM_REG(n, 0x38)
-#define STM32_TIM_CCR3(n)          STM32_TIM_REG(n, 0x3C)
-#define STM32_TIM_CCR4(n)          STM32_TIM_REG(n, 0x40)
-#define STM32_TIM_BDTR(n)          STM32_TIM_REG(n, 0x44)
-#define STM32_TIM_BDTR_MOE		BIT(15)
-#define STM32_TIM_DCR(n)           STM32_TIM_REG(n, 0x48)
-#define STM32_TIM_DMAR(n)          STM32_TIM_REG(n, 0x4C)
-#define STM32_TIM_OR(n)            STM32_TIM_REG(n, 0x50)
-
-#define STM32_TIM_CCRx(n, x)       STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4)
-
-#define STM32_TIM32_CNT(n)         STM32_TIM_REG32(n, 0x24)
-#define STM32_TIM32_ARR(n)         STM32_TIM_REG32(n, 0x2C)
-#define STM32_TIM32_CCR1(n)        STM32_TIM_REG32(n, 0x34)
-#define STM32_TIM32_CCR2(n)        STM32_TIM_REG32(n, 0x38)
-#define STM32_TIM32_CCR3(n)        STM32_TIM_REG32(n, 0x3C)
-#define STM32_TIM32_CCR4(n)        STM32_TIM_REG32(n, 0x40)
-/* Timer registers as struct */
-struct timer_ctlr {
-	unsigned cr1;
-	unsigned cr2;
-	unsigned smcr;
-	unsigned dier;
-
-	unsigned sr;
-	unsigned egr;
-	unsigned ccmr1;
-	unsigned ccmr2;
-
-	unsigned ccer;
-	unsigned cnt;
-	unsigned psc;
-	unsigned arr;
-
-	unsigned ccr[5]; /* ccr[0] = reserved30 */
-
-	unsigned bdtr;
-	unsigned dcr;
-	unsigned dmar;
-
-	unsigned option_register;
-};
-/* Must be volatile, or compiler optimizes out repeated accesses */
-typedef volatile struct timer_ctlr timer_ctlr_t;
-
-/* --- Low power timers --- */
-#define STM32_LPTIM_BASE(n)          CONCAT3(STM32_LPTIM, n, _BASE)
-
-#define STM32_LPTIM_REG(n, offset)   REG32(STM32_LPTIM_BASE(n) + (offset))
-
-#define STM32_LPTIM_ISR(n)           STM32_LPTIM_REG(n, 0x00)
-#define STM32_LPTIM_ICR(n)           STM32_LPTIM_REG(n, 0x04)
-#define STM32_LPTIM_IER(n)           STM32_LPTIM_REG(n, 0x08)
-#define STM32_LPTIM_INT_DOWN		BIT(6)
-#define STM32_LPTIM_INT_UP		BIT(5)
-#define STM32_LPTIM_INT_ARROK		BIT(4)
-#define STM32_LPTIM_INT_CMPOK		BIT(3)
-#define STM32_LPTIM_INT_EXTTRIG		BIT(2)
-#define STM32_LPTIM_INT_ARRM		BIT(1)
-#define STM32_LPTIM_INT_CMPM		BIT(0)
-#define STM32_LPTIM_CFGR(n)          STM32_LPTIM_REG(n, 0x0C)
-#define STM32_LPTIM_CR(n)            STM32_LPTIM_REG(n, 0x10)
-#define STM32_LPTIM_CR_RSTARE		BIT(4)
-#define STM32_LPTIM_CR_COUNTRST		BIT(3)
-#define STM32_LPTIM_CR_CNTSTRT		BIT(2)
-#define STM32_LPTIM_CR_SNGSTRT		BIT(1)
-#define STM32_LPTIM_CR_ENABLE		BIT(0)
-#define STM32_LPTIM_CMP(n)           STM32_LPTIM_REG(n, 0x14)
-#define STM32_LPTIM_ARR(n)           STM32_LPTIM_REG(n, 0x18)
-#define STM32_LPTIM_CNT(n)           STM32_LPTIM_REG(n, 0x1C)
-#define STM32_LPTIM_CFGR2(n)         STM32_LPTIM_REG(n, 0x24)
-
-/* --- GPIO --- */
-
-#define GPIO_A                       STM32_GPIOA_BASE
-#define GPIO_B                       STM32_GPIOB_BASE
-#define GPIO_C                       STM32_GPIOC_BASE
-#define GPIO_D                       STM32_GPIOD_BASE
-#define GPIO_E                       STM32_GPIOE_BASE
-#define GPIO_F                       STM32_GPIOF_BASE
-#define GPIO_G                       STM32_GPIOG_BASE
-#define GPIO_H                       STM32_GPIOH_BASE
-#define GPIO_I                       STM32_GPIOI_BASE
-#define GPIO_J                       STM32_GPIOJ_BASE
-#define GPIO_K                       STM32_GPIOK_BASE
-
-#define UNIMPLEMENTED_GPIO_BANK GPIO_A
-
-
-/* --- I2C --- */
-#define STM32_I2C1_PORT             0
-#define STM32_I2C2_PORT             1
-#define STM32_I2C3_PORT             2
-#define STM32_FMPI2C4_PORT          3
-
-#define stm32_i2c_reg(port, offset) \
-	((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset)))
-/* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR_LPSDSR		(1 << 0)
-#define STM32_PWR_CR_FLPS		(1 << 9)
-#define STM32_PWR_CR_SVOS5		(1 << 14)
-#define STM32_PWR_CR_SVOS4		(2 << 14)
-#define STM32_PWR_CR_SVOS3		(3 << 14)
-#define STM32_PWR_CR_SVOS_MASK		(3 << 14)
-
-/* RTC domain control register */
-#define STM32_RCC_BDCR_BDRST		BIT(16)
-#define STM32_RCC_BDCR_RTCEN		BIT(15)
-#define STM32_RCC_BDCR_LSERDY		BIT(1)
-#define STM32_RCC_BDCR_LSEON		BIT(0)
-#define  BDCR_RTCSEL_MASK		((0x3) << 8)
-#define  BDCR_RTCSEL(source)		(((source) << 8) & BDCR_RTCSEL_MASK)
-#define  BDCR_SRC_LSE			0x1
-#define  BDCR_SRC_LSI			0x2
-#define  BDCR_SRC_HSE			0x3
-/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_TIM2		BIT(0)
-#define STM32_RCC_PB1_TIM3		BIT(1)
-#define STM32_RCC_PB1_TIM4		BIT(2)
-#define STM32_RCC_PB1_TIM5		BIT(3)
-#define STM32_RCC_PB1_TIM6		BIT(4)
-#define STM32_RCC_PB1_TIM7		BIT(5)
-#define STM32_RCC_PB1_TIM12             BIT(6) /* STM32H7 */
-#define STM32_RCC_PB1_TIM13             BIT(7) /* STM32H7 */
-#define STM32_RCC_PB1_TIM14             BIT(8) /* STM32H7 */
-#define STM32_RCC_PB1_RTC		BIT(10) /* DBGMCU only */
-#define STM32_RCC_PB1_WWDG		BIT(11)
-#define STM32_RCC_PB1_IWDG		BIT(12) /* DBGMCU only */
-#define STM32_RCC_PB1_SPI2		BIT(14)
-#define STM32_RCC_PB1_SPI3		BIT(15)
-#define STM32_RCC_PB1_USART2		BIT(17)
-#define STM32_RCC_PB1_USART3		BIT(18)
-#define STM32_RCC_PB1_USART4		BIT(19)
-#define STM32_RCC_PB1_USART5		BIT(20)
-#define STM32_RCC_PB1_PWREN		BIT(28)
-#define STM32_RCC_PB2_SPI1		BIT(12)
-/* Reset causes definitions */
-
-/* --- Watchdogs --- */
-
-#define STM32_WWDG_CR               REG32(STM32_WWDG_BASE + 0x00)
-#define STM32_WWDG_CFR              REG32(STM32_WWDG_BASE + 0x04)
-#define STM32_WWDG_SR               REG32(STM32_WWDG_BASE + 0x08)
-
-#define STM32_WWDG_TB_8             (3 << 7)
-#define STM32_WWDG_EWI              BIT(9)
-
-#define STM32_IWDG_KR               REG32(STM32_IWDG_BASE + 0x00)
-#define STM32_IWDG_KR_UNLOCK		0x5555
-#define STM32_IWDG_KR_RELOAD		0xaaaa
-#define STM32_IWDG_KR_START		0xcccc
-#define STM32_IWDG_PR               REG32(STM32_IWDG_BASE + 0x04)
-#define STM32_IWDG_RLR              REG32(STM32_IWDG_BASE + 0x08)
-#define STM32_IWDG_RLR_MAX		0x0fff
-#define STM32_IWDG_SR               REG32(STM32_IWDG_BASE + 0x0C)
-#define STM32_IWDG_SR_WVU		BIT(2)
-#define STM32_IWDG_SR_RVU		BIT(1)
-#define STM32_IWDG_SR_PVU		BIT(0)
-#define STM32_IWDG_WINR             REG32(STM32_IWDG_BASE + 0x10)
-
-/* --- Real-Time Clock --- */
-/* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-/* --- Routing interface --- */
-/* STM32L1xx only */
-#define STM32_RI_ICR                REG32(STM32_COMP_BASE + 0x04)
-#define STM32_RI_ASCR1              REG32(STM32_COMP_BASE + 0x08)
-#define STM32_RI_ASCR2              REG32(STM32_COMP_BASE + 0x0C)
-#define STM32_RI_HYSCR1             REG32(STM32_COMP_BASE + 0x10)
-#define STM32_RI_HYSCR2             REG32(STM32_COMP_BASE + 0x14)
-#define STM32_RI_HYSCR3             REG32(STM32_COMP_BASE + 0x18)
-#define STM32_RI_AMSR1              REG32(STM32_COMP_BASE + 0x1C)
-#define STM32_RI_CMR1               REG32(STM32_COMP_BASE + 0x20)
-#define STM32_RI_CICR1              REG32(STM32_COMP_BASE + 0x24)
-#define STM32_RI_AMSR2              REG32(STM32_COMP_BASE + 0x28)
-#define STM32_RI_CMR2               REG32(STM32_COMP_BASE + 0x30)
-#define STM32_RI_CICR2              REG32(STM32_COMP_BASE + 0x34)
-#define STM32_RI_AMSR3              REG32(STM32_COMP_BASE + 0x38)
-#define STM32_RI_CMR3               REG32(STM32_COMP_BASE + 0x3C)
-#define STM32_RI_CICR3              REG32(STM32_COMP_BASE + 0x40)
-#define STM32_RI_AMSR4              REG32(STM32_COMP_BASE + 0x44)
-#define STM32_RI_CMR4               REG32(STM32_COMP_BASE + 0x48)
-#define STM32_RI_CICR4              REG32(STM32_COMP_BASE + 0x4C)
-#define STM32_RI_AMSR5              REG32(STM32_COMP_BASE + 0x50)
-#define STM32_RI_CMR5               REG32(STM32_COMP_BASE + 0x54)
-#define STM32_RI_CICR5              REG32(STM32_COMP_BASE + 0x58)
-
-/* --- DAC --- */
-#define STM32_DAC_CR               REG32(STM32_DAC_BASE + 0x00)
-#define STM32_DAC_SWTRIGR          REG32(STM32_DAC_BASE + 0x04)
-#define STM32_DAC_DHR12R1          REG32(STM32_DAC_BASE + 0x08)
-#define STM32_DAC_DHR12L1          REG32(STM32_DAC_BASE + 0x0C)
-#define STM32_DAC_DHR8R1           REG32(STM32_DAC_BASE + 0x10)
-#define STM32_DAC_DHR12R2          REG32(STM32_DAC_BASE + 0x14)
-#define STM32_DAC_DHR12L2          REG32(STM32_DAC_BASE + 0x18)
-#define STM32_DAC_DHR8R2           REG32(STM32_DAC_BASE + 0x1C)
-#define STM32_DAC_DHR12RD          REG32(STM32_DAC_BASE + 0x20)
-#define STM32_DAC_DHR12LD          REG32(STM32_DAC_BASE + 0x24)
-#define STM32_DAC_DHR8RD           REG32(STM32_DAC_BASE + 0x28)
-#define STM32_DAC_DOR1             REG32(STM32_DAC_BASE + 0x2C)
-#define STM32_DAC_DOR2             REG32(STM32_DAC_BASE + 0x30)
-#define STM32_DAC_SR               REG32(STM32_DAC_BASE + 0x34)
-
-#define STM32_DAC_CR_DMAEN2        BIT(28)
-#define STM32_DAC_CR_TSEL2_SWTRG   (7 << 19)
-#define STM32_DAC_CR_TSEL2_TMR4    (5 << 19)
-#define STM32_DAC_CR_TSEL2_TMR2    (4 << 19)
-#define STM32_DAC_CR_TSEL2_TMR9    (3 << 19)
-#define STM32_DAC_CR_TSEL2_TMR7    (2 << 19)
-#define STM32_DAC_CR_TSEL2_TMR6    (0 << 19)
-#define STM32_DAC_CR_TSEL2_MASK    (7 << 19)
-#define STM32_DAC_CR_TEN2          BIT(18)
-#define STM32_DAC_CR_BOFF2         BIT(17)
-#define STM32_DAC_CR_EN2           BIT(16)
-#define STM32_DAC_CR_DMAEN1        BIT(12)
-#define STM32_DAC_CR_TSEL1_SWTRG   (7 << 3)
-#define STM32_DAC_CR_TSEL1_TMR4    (5 << 3)
-#define STM32_DAC_CR_TSEL1_TMR2    (4 << 3)
-#define STM32_DAC_CR_TSEL1_TMR9    (3 << 3)
-#define STM32_DAC_CR_TSEL1_TMR7    (2 << 3)
-#define STM32_DAC_CR_TSEL1_TMR6    (0 << 3)
-#define STM32_DAC_CR_TSEL1_MASK    (7 << 3)
-#define STM32_DAC_CR_TEN1          BIT(2)
-#define STM32_DAC_CR_BOFF1         BIT(1)
-#define STM32_DAC_CR_EN1           BIT(0)
-/* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-/* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK  (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-#define EP_TX_RX_NAK   (EP_TX_NAK | EP_RX_NAK)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
-
-/* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN		BIT(2)
-#define STM32_RNG_CR_IE			BIT(3)
-#define STM32_RNG_CR_CED		BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY		BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
-
-/* --- AXI interconnect --- */
-
-/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
-
-/* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
-
-#endif /* !__ASSEMBLER__ */
-
-#if defined(CHIP_FAMILY_STM32F0)
-#include "registers-stm32f0.h"
-#elif defined(CHIP_FAMILY_STM32F3)
-#include "registers-stm32f3.h"
-#elif defined(CHIP_FAMILY_STM32F4)
-#include "registers-stm32f4.h"
-#elif defined(CHIP_FAMILY_STM32F7)
-#include "registers-stm32f7.h"
-#elif defined(CHIP_FAMILY_STM32G4)
-#include "registers-stm32g4.h"
-#elif defined(CHIP_FAMILY_STM32H7)
-#include "registers-stm32h7.h"
-#elif defined(CHIP_FAMILY_STM32L)
-#include "registers-stm32l.h"
-#elif defined(CHIP_FAMILY_STM32L4)
-#include "registers-stm32l4.h"
-#elif defined(CHIP_FAMILY_STM32L5)
-#include "registers-stm32l5.h"
-#else
-#error "Unsupported chip family"
-#endif
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
deleted file mode 100644
index 3dbbbc4fa9..0000000000
--- a/chip/stm32/spi.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI driver for Chrome EC.
- *
- * This uses DMA to handle transmission and reception.
- */
-
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-/* SPI FIFO registers */
-#ifdef CHIP_FAMILY_STM32H7
-#define SPI_TXDR REG8(&STM32_SPI1_REGS->txdr)
-#define SPI_RXDR REG8(&STM32_SPI1_REGS->rxdr)
-#else
-#define SPI_TXDR STM32_SPI1_REGS->dr
-#define SPI_RXDR STM32_SPI1_REGS->dr
-#endif
-
-/* DMA channel option */
-static const struct dma_option dma_tx_option = {
-	STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
-#endif
-};
-
-static const struct dma_option dma_rx_option = {
-	STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR,
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
-#endif
-};
-
-/*
- * Timeout to wait for SPI request packet
- *
- * This affects the slowest SPI clock we can support.  A delay of 8192 us
- * permits a 512-byte request at 500 KHz, assuming the master starts sending
- * bytes as soon as it asserts chip select.  That's as slow as we would
- * practically want to run the SPI interface, since running it slower
- * significantly impacts firmware update times.
- */
-#define SPI_CMD_RX_TIMEOUT_US 8192
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/*
- * Offset of output parameters needs to account for pad and framing bytes and
- * one last past-end byte at the end so any additional bytes clocked out by
- * the AP will have a known and identifiable value.
- */
-#define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2)
-#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET +		\
-			     EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size, and 512 bytes
- * of flash data.
- */
-#define SPI_MAX_REQUEST_SIZE 0x220
-#define SPI_MAX_RESPONSE_SIZE 0x220
-
-/*
- * The AP blindly clocks back bytes over the SPI interface looking for a
- * framing byte.  So this preamble must always precede the actual response
- * packet.  Search for "spi-frame-header" in U-boot to see how that's
- * implemented.
- *
- * The preamble must be 32-bit aligned so that the response buffer is also
- * 32-bit aligned.
- */
-static const uint8_t out_preamble[4] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_FRAME_START,  /* This is the byte which matters */
-};
-
-/*
- * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
- * buffer. This seems to be dynamic because the F0 family needs to send it 4
- * times in order to make sure it actually stays at the repeating byte after DMA
- * ends.
- *
- * See crosbug.com/p/31390
- */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-#define EC_SPI_PAST_END_LENGTH 4
-#else
-#define EC_SPI_PAST_END_LENGTH 1
-#endif
-
-/*
- * Our input and output buffers. These must be large enough for our largest
- * message, including protocol overhead, and must be 32-bit aligned.
- */
-static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) +
-	EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
-static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached;
-static uint8_t enabled;
-#ifdef CONFIG_SPI_PROTOCOL_V2
-static struct host_cmd_handler_args args;
-#endif
-static struct host_packet spi_packet;
-
-/*
- * This is set if SPI NSS raises to high while EC is still processing a
- * command.
- */
-static int setup_transaction_later;
-
-enum spi_state {
-	/* SPI not enabled (initial state, and when chipset is off) */
-	SPI_STATE_DISABLED = 0,
-
-	/* Setting up receive DMA */
-	SPI_STATE_PREPARE_RX,
-
-	/* Ready to receive next request */
-	SPI_STATE_READY_TO_RX,
-
-	/* Receiving request */
-	SPI_STATE_RECEIVING,
-
-	/* Processing request */
-	SPI_STATE_PROCESSING,
-
-	/* Sending response */
-	SPI_STATE_SENDING,
-
-	/*
-	 * Received bad data - transaction started before we were ready, or
-	 * packet header from host didn't parse properly.  Ignoring received
-	 * data.
-	 */
-	SPI_STATE_RX_BAD,
-} state;
-
-/**
- * Wait until we have received a certain number of bytes
- *
- * Watch the DMA receive channel until it has the required number of bytes,
- * or a timeout occurs
- *
- * We keep an eye on the NSS line - if this goes high then the transaction is
- * over so there is no point in trying to receive the bytes.
- *
- * @param rxdma		RX DMA channel to watch
- * @param needed	Number of bytes that are needed
- * @param nss		GPIO signal for NSS control line
- * @return 0 if bytes received, -1 if we hit a timeout or NSS went high
- */
-static int wait_for_bytes(dma_chan_t *rxdma, int needed,
-			  enum gpio_signal nss)
-{
-	timestamp_t deadline;
-
-	ASSERT(needed <= sizeof(in_msg));
-	deadline.val = 0;
-	while (1) {
-		if (dma_bytes_done(rxdma, sizeof(in_msg)) >= needed)
-			return 0;
-		if (gpio_get_level(nss))
-			return -1;
-		if (!deadline.val) {
-			deadline = get_time();
-			deadline.val += SPI_CMD_RX_TIMEOUT_US;
-		}
-		if (timestamp_expired(deadline, NULL))
-			return -1;
-	}
-}
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/**
- * Send a reply on a given port.
- *
- * The format of a reply is as per the command interface, with a number of
- * preamble bytes before it.
- *
- * The format of a reply is a sequence of bytes:
- *
- * <hdr> <status> <len> <msg bytes> <sum> [<preamble byte>...]
- *
- * The hdr byte is just a tag to indicate that the real message follows. It
- * signals the end of any preamble required by the interface.
- *
- * The length is the entire packet size, including the header, length bytes,
- * message payload, checksum, and postamble byte.
- *
- * The preamble is at least 2 bytes, but can be longer if the STM takes ages
- * to react to the incoming message. Since we send our first byte as the AP
- * sends us the command, we clearly can't send anything sensible for that
- * byte. The second byte must be written to the output register just when the
- * command byte is ready (I think), so we can't do anything there either.
- * Any processing we do may increase this delay. That's the reason for the
- * preamble.
- *
- * It is interesting to note that it seems to be possible to run the SPI
- * interface faster than the CPU clock with this approach.
- *
- * We keep an eye on the NSS line - if this goes high then the transaction is
- * over so there is no point in trying to send the reply.
- *
- * @param txdma		TX DMA channel to send on
- * @param status	Status result to send
- * @param msg_ptr	Message payload to send, which normally starts
- *			SPI_PROTO2_OFFSET bytes into out_msg
- * @param msg_len	Number of message bytes to send
- */
-static void reply(dma_chan_t *txdma,
-		  enum ec_status status, char *msg_ptr, int msg_len)
-{
-	char *msg = out_msg;
-	int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET;
-	int sum, i;
-
-	ASSERT(msg_len + SPI_PROTO2_OVERHEAD <= sizeof(out_msg));
-
-	/* Add our header bytes - the first one might not actually be sent */
-	msg[0] = EC_SPI_PROCESSING;
-	msg[1] = EC_SPI_FRAME_START;
-	msg[2] = status;
-	msg[3] = msg_len & 0xff;
-
-	/*
-	 * Calculate the checksum; includes the status and message length bytes
-	 * but not the pad and framing bytes since those are stripped by the AP
-	 * driver.
-	 */
-	sum = status + msg_len;
-	for (i = 0; i < msg_len; i++) {
-		int ch = msg_ptr[i];
-		sum += ch;
-		if (need_copy)
-			msg[i + SPI_PROTO2_OFFSET] = ch;
-	}
-
-	/* Add the checksum and get ready to send */
-	msg[SPI_PROTO2_OFFSET + msg_len] = sum & 0xff;
-	msg[SPI_PROTO2_OFFSET + msg_len + 1] = EC_SPI_PAST_END;
-	dma_prepare_tx(&dma_tx_option, msg_len + SPI_PROTO2_OVERHEAD, msg);
-
-	/* Kick off the DMA to send the data */
-	dma_go(txdma);
-}
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-
-/**
- * Sends a byte over SPI without DMA
- *
- * This is mostly used when we want to relay status bytes to the AP while we're
- * receiving the message and we're thinking about it.
- *
- * @note It may be sent 0, 1, or >1 times, depending on whether the host clocks
- * the bus or not. Basically, the EC is saying "if you ask me what my status is,
- * you'll get this value.  But you're not required to ask, or you can ask
- * multiple times."
- *
- * @param byte	status byte to send, one of the EC_SPI_* #defines from
- *		ec_commands.h
- */
-static void tx_status(uint8_t byte)
-{
-	stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS;
-
-	SPI_TXDR = byte;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* It sends the byte 4 times in order to be sure it bypassed the FIFO
-	 * from the STM32F0 line.
-	 */
-	spi->dr = byte;
-	spi->dr = byte;
-	spi->dr = byte;
-#elif defined(CHIP_FAMILY_STM32H7)
-	spi->udrdr = byte;
-#endif
-}
-
-/**
- * Get ready to receive a message from the master.
- *
- * Set up our RX DMA and disable our TX DMA. Set up the data output so that
- * we will send preamble bytes.
- */
-static void setup_for_transaction(void)
-{
-	stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS;
-	volatile uint8_t unused __attribute__((unused));
-
-	/* clear this as soon as possible */
-	setup_transaction_later = 0;
-
-#ifndef CHIP_FAMILY_STM32H7 /* H7 is not ready to set status here */
-	/* Not ready to receive yet */
-	tx_status(EC_SPI_NOT_READY);
-#endif
-
-	/* We are no longer actively processing a transaction */
-	state = SPI_STATE_PREPARE_RX;
-
-	/* Stop sending response, if any */
-	dma_disable(STM32_DMAC_SPI1_TX);
-
-	/*
-	 * Read unused bytes in case there are some pending; this prevents the
-	 * receive DMA from getting that byte right when we start it.
-	 */
-	unused = SPI_RXDR;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */
-	unused = spi->dr;
-	unused = spi->dr;
-	unused = spi->dr;
-#endif
-
-	/* Start DMA */
-	dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);
-
-	/* Ready to receive */
-	state = SPI_STATE_READY_TO_RX;
-	tx_status(EC_SPI_OLD_READY);
-
-#ifdef CHIP_FAMILY_STM32H7
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-#endif
-}
-
-/* Forward declaration */
-static void spi_init(void);
-
-/*
- * If a setup_for_transaction() was postponed, call it now.
- * Note that setup_for_transaction() cancels Tx DMA.
- */
-static void check_setup_transaction_later(void)
-{
-	if (setup_transaction_later) {
-		spi_init(); /* Fix for bug chrome-os-partner:31390 */
-		/*
-		 * 'state' is set to SPI_STATE_READY_TO_RX. Somehow AP
-		 * de-asserted the SPI NSS during the handler was running.
-		 * Thus, the pending result will be dropped anyway.
-		 */
-	}
-}
-
-#ifdef CONFIG_SPI_PROTOCOL_V2
-/**
- * Called for V2 protocol to indicate that a command has completed
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response(struct host_cmd_handler_args *args)
-{
-	enum ec_status result = args->result;
-	dma_chan_t *txdma;
-
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 */
-	if (state != SPI_STATE_PROCESSING)
-		return;
-
-	/* state == SPI_STATE_PROCESSING */
-
-	if (args->response_size > args->response_max)
-		result = EC_RES_INVALID_RESPONSE;
-
-	/* Transmit the reply */
-	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	reply(txdma, result, args->response, args->response_size);
-
-	/*
-	 * Before the state is set to SENDING, any CS de-assertion would
-	 * set setup_transaction_later to 1.
-	 */
-	state = SPI_STATE_SENDING;
-	check_setup_transaction_later();
-}
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-
-/**
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response_packet(struct host_packet *pkt)
-{
-	dma_chan_t *txdma;
-
-	/*
-	 * If we're not processing, then the AP has already terminated the
-	 * transaction, and won't be listening for a response.
-	 */
-	if (state != SPI_STATE_PROCESSING)
-		return;
-
-	/* state == SPI_STATE_PROCESSING */
-
-	/* Append our past-end byte, which we reserved space for. */
-	((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	/* Make sure we are going to be outputting it properly when the DMA
-	 * ends due to the TX FIFO bug on the F0. See crosbug.com/p/31390
-	 */
-	((uint8_t *)pkt->response)[pkt->response_size + 1] = EC_SPI_PAST_END;
-	((uint8_t *)pkt->response)[pkt->response_size + 2] = EC_SPI_PAST_END;
-	((uint8_t *)pkt->response)[pkt->response_size + 3] = EC_SPI_PAST_END;
-#endif
-
-	/* Transmit the reply */
-	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size
-		+ EC_SPI_PAST_END_LENGTH, out_msg);
-	dma_go(txdma);
-#ifdef CHIP_FAMILY_STM32H7
-	/* clear any previous underrun */
-	STM32_SPI1_REGS->ifcr = STM32_SPI_SR_UDR;
-#endif /* CHIP_FAMILY_STM32H7 */
-
-	/*
-	 * Before the state is set to SENDING, any CS de-assertion would
-	 * set setup_transaction_later to 1.
-	 */
-	state = SPI_STATE_SENDING;
-	check_setup_transaction_later();
-}
-
-/**
- * Handle an event on the NSS pin
- *
- * A falling edge of NSS indicates that the master is starting a new
- * transaction. A rising edge indicates that we have finished.
- *
- * @param signal	GPIO signal for the NSS pin
- */
-void spi_event(enum gpio_signal signal)
-{
-	dma_chan_t *rxdma;
-	uint16_t i;
-
-	/* If not enabled, ignore glitches on NSS */
-	if (!enabled)
-		return;
-
-	/* Check chip select.  If it's high, the AP ended a transaction. */
-	if (gpio_get_level(GPIO_SPI1_NSS)) {
-		enable_sleep(SLEEP_MASK_SPI);
-
-		/*
-		 * If the buffer is still used by the host command, postpone
-		 * the DMA rx setup.
-		 */
-		if (state == SPI_STATE_PROCESSING) {
-			setup_transaction_later = 1;
-			return;
-		}
-
-		/* Set up for the next transaction */
-		spi_init(); /* Fix for bug chrome-os-partner:31390 */
-		return;
-	}
-	disable_sleep(SLEEP_MASK_SPI);
-
-	/* Chip select is low = asserted */
-	if (state != SPI_STATE_READY_TO_RX) {
-		/*
-		 * AP started a transaction but we weren't ready for it.
-		 * Tell AP we weren't ready, and ignore the received data.
-		 */
-		CPRINTS("SPI not ready");
-		tx_status(EC_SPI_NOT_READY);
-		state = SPI_STATE_RX_BAD;
-		return;
-	}
-
-	/* We're now inside a transaction */
-	state = SPI_STATE_RECEIVING;
-	tx_status(EC_SPI_RECEIVING);
-	rxdma = dma_get_channel(STM32_DMAC_SPI1_RX);
-
-	/* Wait for version, command, length bytes */
-	if (wait_for_bytes(rxdma, 3, GPIO_SPI1_NSS))
-		goto spi_event_error;
-
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *)in_msg;
-		int pkt_size;
-
-		/* Wait for the rest of the command header */
-		if (wait_for_bytes(rxdma, sizeof(*r), GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		/*
-		 * Check how big the packet should be.  We can't just wait to
-		 * see how much data the host sends, because it will keep
-		 * sending extra data until we respond.
-		 */
-		pkt_size = host_request_expected_size(r);
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			goto spi_event_error;
-
-		/* Wait for the packet data */
-		if (wait_for_bytes(rxdma, pkt_size, GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		spi_packet.send_response = spi_send_response_packet;
-
-		spi_packet.request = in_msg;
-		spi_packet.request_temp = NULL;
-		spi_packet.request_max = sizeof(in_msg);
-		spi_packet.request_size = pkt_size;
-
-		/* Response must start with the preamble */
-		memcpy(out_msg, out_preamble, sizeof(out_preamble));
-		spi_packet.response = out_msg + sizeof(out_preamble);
-		/* Reserve space for the preamble and trailing past-end byte */
-		spi_packet.response_max = sizeof(out_msg)
-			- sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH;
-		spi_packet.response_size = 0;
-
-		spi_packet.driver_result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		state = SPI_STATE_PROCESSING;
-		tx_status(EC_SPI_PROCESSING);
-
-		host_packet_receive(&spi_packet);
-		return;
-
-	} else if (in_msg[0] >= EC_CMD_VERSION0) {
-#ifdef CONFIG_SPI_PROTOCOL_V2
-		/*
-		 * Protocol version 2
-		 *
-		 * TODO(crosbug.com/p/20257): Remove once kernel supports
-		 * version 3.
-		 */
-
-#ifdef CHIP_FAMILY_STM32F0
-		CPRINTS("WARNING: Protocol version 2 is not supported on the F0"
-			" line due to crosbug.com/p/31390");
-#endif
-
-		args.version = in_msg[0] - EC_CMD_VERSION0;
-		args.command = in_msg[1];
-		args.params_size = in_msg[2];
-
-		/* Wait for parameters */
-		if (wait_for_bytes(rxdma, 3 + args.params_size, GPIO_SPI1_NSS))
-			goto spi_event_error;
-
-		/*
-		 * Params are not 32-bit aligned in protocol version 2.  As a
-		 * workaround, move them to the beginning of the input buffer
-		 * so they are aligned.
-		 */
-		if (args.params_size)
-			memmove(in_msg, in_msg + 3, args.params_size);
-
-		args.params = in_msg;
-		args.send_response = spi_send_response;
-
-		/* Allow room for the header bytes */
-		args.response = out_msg + SPI_PROTO2_OFFSET;
-		args.response_max = sizeof(out_msg) - SPI_PROTO2_OVERHEAD;
-		args.response_size = 0;
-		args.result = EC_RES_SUCCESS;
-
-		/* Move to processing state */
-		state = SPI_STATE_PROCESSING;
-		tx_status(EC_SPI_PROCESSING);
-
-		host_command_received(&args);
-		return;
-#else /* !defined(CONFIG_SPI_PROTOCOL_V2) */
-		/* Protocol version 2 is deprecated. */
-		CPRINTS("ERROR: Protocol V2 is not supported!");
-#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
-	}
-
- spi_event_error:
-	/* Error, timeout, or protocol we can't handle.  Ignore data. */
-	tx_status(EC_SPI_RX_BAD_DATA);
-	state = SPI_STATE_RX_BAD;
-	CPRINTS("SPI rx bad data");
-
-	CPRINTF("in_msg=[");
-	for (i = 0; i < dma_bytes_done(rxdma, sizeof(in_msg)); i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-}
-
-static void spi_chipset_startup(void)
-{
-	/* Enable pullup and interrupts on NSS */
-	gpio_set_flags(GPIO_SPI1_NSS, GPIO_INT_BOTH | GPIO_PULL_UP);
-
-	/* Set SPI pins to alternate function */
-	gpio_config_module(MODULE_SPI, 1);
-
-	/* Set up for next transaction */
-	setup_for_transaction();
-
-	enabled = 1;
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, spi_chipset_startup, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, spi_chipset_startup, HOOK_PRIO_DEFAULT);
-#endif
-
-static void spi_chipset_shutdown(void)
-{
-	enabled = 0;
-	state = SPI_STATE_DISABLED;
-
-	/* Disable pullup and interrupts on NSS */
-	gpio_set_flags(GPIO_SPI1_NSS, GPIO_INPUT);
-
-	/* Set SPI pins to inputs so we don't leak power when AP is off */
-	gpio_config_module(MODULE_SPI, 0);
-
-	/* Allow deep sleep when AP off */
-	enable_sleep(SLEEP_MASK_SPI);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, spi_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, spi_chipset_shutdown, HOOK_PRIO_DEFAULT);
-#endif
-
-static void spi_init(void)
-{
-	stm32_spi_regs_t *spi = STM32_SPI1_REGS;
-	uint8_t was_enabled = enabled;
-
-	/* Reset the SPI Peripheral to clear any existing weird states. */
-	/* Fix for bug chrome-os-partner:31390 */
-	enabled = 0;
-	state = SPI_STATE_DISABLED;
-	STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1;
-	STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1;
-
-	/* 40 MHz pin speed */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
-
-	/* Enable clocks to SPI1 module */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-
-	/*
-	 * Select the right DMA request for the variants using it.
-	 * This is not required for STM32F4 since the channel (aka request) is
-	 * set directly in the respective dma_option. In fact, it would be
-	 * overridden in dma-stm32f4::prepare_stream().
-	 */
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(STM32_DMAC_SPI1_TX, 1);
-	dma_select_channel(STM32_DMAC_SPI1_RX, 1);
-#elif defined(CHIP_FAMILY_STM32H7)
-	dma_select_channel(STM32_DMAC_SPI1_TX, DMAMUX1_REQ_SPI1_TX);
-	dma_select_channel(STM32_DMAC_SPI1_RX, DMAMUX1_REQ_SPI1_RX);
-#endif
-	/*
-	 * Enable rx/tx DMA and get ready to receive our first transaction and
-	 * "disable" FIFO by setting event to happen after only 1 byte
-	 */
-#ifdef CHIP_FAMILY_STM32H7
-	spi->cfg2 = 0;
-	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-			STM32_SPI_CFG1_CRCSIZE(8) |
-			STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN |
-			STM32_SPI_CFG1_UDRCFG_CONST |
-			STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
-	spi->cr1 = 0;
-#else /* !CHIP_FAMILY_STM32H7 */
-	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
-		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
-
-	/* Enable the SPI peripheral */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-#endif /* !CHIP_FAMILY_STM32H7 */
-
-	gpio_enable_interrupt(GPIO_SPI1_NSS);
-
-	/*
-	 * If we were already enabled or chipset is already on,
-	 * prepare for transaction
-	 */
-	if (was_enabled || chipset_in_state(CHIPSET_STATE_ON))
-		spi_chipset_startup();
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
-
-/**
- * Get protocol information
- */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-#ifdef CONFIG_SPI_PROTOCOL_V2
-	r->protocol_versions |= BIT(2);
-#endif
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c
deleted file mode 100644
index 4195dc595a..0000000000
--- a/chip/stm32/spi_master-stm32h7.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* SPI ports are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-	STM32_SPI3_REGS,
-	STM32_SPI4_REGS,
-};
-
-/* DMA request mapping on channels */
-static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	DMAMUX1_REQ_SPI1_TX,
-#endif
-	DMAMUX1_REQ_SPI2_TX,
-	DMAMUX1_REQ_SPI3_TX,
-	DMAMUX1_REQ_SPI4_TX,
-};
-static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	DMAMUX1_REQ_SPI1_RX,
-#endif
-	DMAMUX1_REQ_SPI2_RX,
-	DMAMUX1_REQ_SPI3_RX,
-	DMAMUX1_REQ_SPI4_RX,
-};
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-/**
- * Initialize SPI module, registers, and clocks
- * @param spi_device  device to initialize.
- */
-static void spi_master_config(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 */
-	spi->cr1 = STM32_SPI_CR1_SSI;
-	spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM |
-		    STM32_SPI_CFG2_AFCNTR;
-	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-		    STM32_SPI_CFG1_CRCSIZE(8) |
-		    STM32_SPI_CR1_DIV(spi_device->div);
-
-	dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]);
-}
-
-static int spi_master_initialize(const struct spi_device_t *spi_device)
-{
-	spi_master_config(spi_device);
-
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	/* Set flag */
-	spi_enabled[spi_device->port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(const struct spi_device_t *spi_device)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	/* Disable DMA buffers */
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	int port = spi_device->port;
-	if (enable == spi_enabled[port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(spi_device);
-	else
-		return spi_master_shutdown(spi_device);
-}
-
-static int spi_dma_start(const struct spi_device_t *spi_device,
-			 const uint8_t *txdata, uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Workaround for STM32H7 errata: without resetting the SPI controller,
-	 * the RX DMA requests will happen too early on the 2nd transfer.
-	 */
-	STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4;
-	STM32_RCC_APB2RSTR = 0;
-	dma_clear_isr(dma_tx_option[port].channel);
-	dma_clear_isr(dma_rx_option[port].channel);
-	/* restore proper SPI configuration registers. */
-	spi_master_config(spi_device);
-
-	spi->cr2 = len;
-	spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN;
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN;
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-	spi->cr1 |= STM32_SPI_CR1_CSTART;
-
-	return EC_SUCCESS;
-}
-
-static inline bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	timestamp_t timeout;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FIFO empty and BSY bit clear */
-		while (!(spi->sr & (STM32_SPI_SR_TXC)))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-
-		timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-		/* Wait for FRLVL[1:0] to indicate FIFO empty */
-		while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE))
-			if (get_time().val > timeout.val)
-				return EC_ERROR_TIMEOUT;
-
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-	spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN);
-
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	char *buf = NULL;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	rv = spi_dma_start(spi_device, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	if (rxlen) {
-		rv = spi_dma_wait(port);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-
-		rv = spi_dma_start(spi_device, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-	}
-
-err_free:
-	if (!full_readback)
-		shared_mem_release(buf);
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
deleted file mode 100644
index 8943c0c682..0000000000
--- a/chip/stm32/spi_master.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI master driver.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "stm32-dma.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#if defined(CHIP_VARIANT_STM32F373)  || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_VARIANT_STM32F76X)
-#define HAS_SPI3
-#else
-#undef  HAS_SPI3
-#endif
-
-/* The second (and third if available) SPI port are used as master */
-static stm32_spi_regs_t *SPI_REGS[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	STM32_SPI1_REGS,
-#endif
-	STM32_SPI2_REGS,
-#ifdef HAS_SPI3
-	STM32_SPI3_REGS,
-#endif
-};
-
-#ifdef CHIP_FAMILY_STM32L4
-/* DMA request mapping on channels */
-static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	/* SPI1 */ 1,
-#endif
-	/* SPI2 */ 1,
-	/* SPI3 */ 3,
-};
-#endif
-
-static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
-
-#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
-
-/* Default DMA channel options */
-#ifdef CHIP_FAMILY_STM32F4
-#define F4_CHANNEL(ch)	STM32_DMA_CCR_CHANNEL(ch)
-#else
-#define F4_CHANNEL(ch)	0
-#endif
-
-static const struct dma_option dma_tx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_TX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_TX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_TX_REQ_CH)
-	},
-#endif
-};
-
-static const struct dma_option dma_rx_option[] = {
-#ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_RX_REQ_CH)
-	},
-#endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_RX_REQ_CH)
-	},
-#ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_RX_REQ_CH)
-	},
-#endif
-};
-
-static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
-
-static int spi_tx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY));
-}
-
-static int spi_rx_done(stm32_spi_regs_t *spi)
-{
-	return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE));
-}
-
-/* Read until RX FIFO is empty (i.e. RX done) */
-static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
-{
-	uint8_t unused __attribute__((unused));
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_rx_done(spi)) {
-		unused = spi->dr;  /* Read one byte from FIFO */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/* Wait until TX FIFO is empty (i.e. TX done) */
-static int spi_clear_tx_fifo(stm32_spi_regs_t *spi)
-{
-	uint32_t start = __hw_clock_source_read(), delta;
-
-	while (!spi_tx_done(spi)) {
-		/* wait for TX complete */
-		delta = __hw_clock_source_read() - start;
-		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
-			return EC_ERROR_TIMEOUT;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Initialize SPI module, registers, and clocks
- *
- * - port: which port to initialize.
- */
-static int spi_master_initialize(const struct spi_device_t *spi_device)
-{
-	int port = spi_device->port;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/*
-	 * Set SPI master, baud rate, and software slave control.
-	 * */
-
-	/*
-	 * STM32F412
-	 * Section 26.3.5 Slave select (NSS) pin management and Figure 276
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817
-	 *
-	 * The documentation in this section is a bit confusing, so here's a
-	 * summary based on discussion with ST:
-	 *
-	 * Software NSS management (SSM = 1):
-	 *   - In master mode, the NSS output is deactivated. You need to use a
-	 *     GPIO in output mode for slave select. This is generally used for
-	 *     multi-slave operation, but you can also use it for single slave
-	 *     operation. In this case, you should make sure to configure a GPIO
-	 *     for NSS, but *not* activate the SPI alternate function on that
-	 *     same pin since that will enable hardware NSS management (see
-	 *     below).
-	 *   - In slave mode, the NSS input level is equal to the SSI bit value.
-	 *
-	 * Hardware NSS management (SSM = 0):
-	 *   - In slave mode, when NSS pin is detected low the slave (MCU) is
-	 *     selected.
-	 *   - In master mode, there are two configurations, depending on the
-	 *     SSOE bit in register SPIx_CR1.
-	 *       - NSS output enable (SSM=0, SSOE=1):
-	 *         The MCU (master) drives NSS low as soon as SPI is enabled
-	 *         (SPE=1) and releases it when SPI is disabled (SPE=0).
-	 *
-	 *       - NSS output disable (SSM=0, SSOE=0):
-	 *         Allows multimaster capability. The MCU (master) drives NSS
-	 *         low.  If another master tries to takes control of the bus and
-	 *         NSS is pulled low, a mode fault is generated and the MCU
-	 *         changes to slave mode.
-	 *
-	 *   - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as
-	 *     master on the bus, this config allows multimaster capability. If
-	 *     the NSS pin is pulled low in this mode, the SPI enters master
-	 *     mode fault state and the device is automatically reconfigured in
-	 *     slave mode.  In slave mode, the NSS pin works as a standard "chip
-	 *     select" input and the slave is selected while NSS lin is at low
-	 *     level.
-	 */
-	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
-		   (spi_device->div << 3);
-
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(dma_tx_option[port].channel, dma_req[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req[port]);
-#endif
-	/*
-	 * Configure 8-bit datasize, set FRXTH, enable DMA,
-	 * and set data size (applies to STM32F0 only).
-	 *
-	 * STM32F412:
-	 * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852
-	 *
-	 *
-	 * STM32F0:
-	 * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803
-	 */
-	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN |
-			STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE;
-#endif
-
-	/* Drive Chip Select high before turning on SPI module */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	/* Enable SPI hardware module. This will actively drive the CLK pin */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-
-	/* Set flag */
-	spi_enabled[port] = 1;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Shutdown SPI module
- */
-static int spi_master_shutdown(const struct spi_device_t *spi_device)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-
-	/* Set flag */
-	spi_enabled[port] = 0;
-
-	/* Disable DMA streams */
-	dma_disable(dma_tx_option[port].channel);
-	dma_disable(dma_rx_option[port].channel);
-
-	/* Disable SPI. Let the CLK pin float. */
-	spi->cr1 &= ~STM32_SPI_CR1_SPE;
-
-	spi_clear_rx_fifo(spi);
-
-	/* Disable DMA buffers */
-	spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN);
-
-	return rv;
-}
-
-int spi_enable(const struct spi_device_t *spi_device, int enable)
-{
-	if (enable == spi_enabled[spi_device->port])
-		return EC_SUCCESS;
-	if (enable)
-		return spi_master_initialize(spi_device);
-	else
-		return spi_master_shutdown(spi_device);
-}
-
-static int spi_dma_start(int port, const uint8_t *txdata,
-			 uint8_t *rxdata, int len)
-{
-	dma_chan_t *txdma;
-
-	/* Set up RX DMA */
-	if (rxdata)
-		dma_start_rx(&dma_rx_option[port], len, rxdata);
-
-	/* Set up TX DMA */
-	if (txdata) {
-		txdma = dma_get_channel(dma_tx_option[port].channel);
-		dma_prepare_tx(&dma_tx_option[port], len, txdata);
-		dma_go(txdma);
-	}
-
-	return EC_SUCCESS;
-}
-
-static bool dma_is_enabled_(const struct dma_option *option)
-{
-	return dma_is_enabled(dma_get_channel(option->channel));
-}
-
-static int spi_dma_wait(int port)
-{
-	int rv = EC_SUCCESS;
-
-	/* Wait for DMA transmission to complete */
-	if (dma_is_enabled_(&dma_tx_option[port])) {
-		/*
-		 * In TX mode, SPI only generates clock when we write to FIFO.
-		 * Therefore, even though `dma_wait` polls with interval 0.1ms,
-		 * we won't send extra bytes.
-		 */
-		rv = dma_wait(dma_tx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable TX DMA */
-		dma_disable(dma_tx_option[port].channel);
-	}
-
-	/* Wait for DMA reception to complete */
-	if (dma_is_enabled_(&dma_rx_option[port])) {
-		/*
-		 * Because `dma_wait` polls with interval 0.1ms, we will read at
-		 * least ~100 bytes (with 8MHz clock).  If you don't want this
-		 * overhead, you can use interrupt handler
-		 * (`dma_enable_tc_interrupt_callback`) and disable SPI
-		 * interface in callback function.
-		 */
-		rv = dma_wait(dma_rx_option[port].channel);
-		if (rv)
-			return rv;
-		/* Disable RX DMA */
-		dma_disable(dma_rx_option[port].channel);
-	}
-	return rv;
-}
-
-int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_SUCCESS;
-	int port = spi_device->port;
-	int full_readback = 0;
-
-	stm32_spi_regs_t *spi = SPI_REGS[port];
-	char *buf = NULL;
-
-	/* We should not ever be called when disabled, but fail early if so. */
-	if (!spi_enabled[port])
-		return EC_ERROR_BUSY;
-
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (rxlen == SPI_READBACK_ALL) {
-		buf = rxdata;
-		full_readback = 1;
-	} else {
-		rv = shared_mem_acquire(MAX(txlen, rxlen), &buf);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-#endif
-
-	/* Drive SS low */
-	gpio_set_level(spi_device->gpio_cs, 0);
-
-	spi_clear_rx_fifo(spi);
-
-	rv = spi_dma_start(port, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-#ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIOE;
-#endif
-
-	if (full_readback)
-		return EC_SUCCESS;
-
-	rv = spi_dma_wait(port);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
-	spi_clear_tx_fifo(spi);
-
-	if (rxlen) {
-		rv = spi_dma_start(port, buf, rxdata, rxlen);
-		if (rv != EC_SUCCESS)
-			goto err_free;
-#ifdef CONFIG_SPI_HALFDUPLEX
-		spi->cr1 &= ~STM32_SPI_CR1_BIDIOE;
-#endif
-	}
-
-err_free:
-#ifndef CONFIG_SPI_HALFDUPLEX
-	if (!full_readback)
-		shared_mem_release(buf);
-#endif
-	return rv;
-}
-
-int spi_transaction_flush(const struct spi_device_t *spi_device)
-{
-	int rv = spi_dma_wait(spi_device->port);
-
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
-
-	return rv;
-}
-
-int spi_transaction_wait(const struct spi_device_t *spi_device)
-{
-	return spi_dma_wait(spi_device->port);
-}
-
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int rv;
-	int port = spi_device->port;
-
-	mutex_lock(spi_mutex + port);
-	rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen);
-	rv |= spi_transaction_flush(spi_device);
-	mutex_unlock(spi_mutex + port);
-
-	return rv;
-}
diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h
deleted file mode 100644
index 06233b9c93..0000000000
--- a/chip/stm32/stm32-dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * Select DMA stream-channel mapping
- *
- * This selects which stream (peripheral) to be used on a specific channel.
- * Some STM32 chips simply logically OR requests, thus do not require this
- * selection.
- *
- * @param channel: (Global) channel # base 0 (Note some STM32s use base 1)
- * @param peripheral: Refer to the TRM for 'peripheral request signals'
- */
-void dma_select_channel(enum dma_channel channel, unsigned char stream);
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
deleted file mode 100644
index 03e9a74ac4..0000000000
--- a/chip/stm32/system.c
+++ /dev/null
@@ -1,631 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "bkpdata.h"
-#include "clock.h"
-#include "console.h"
-#include "cpu.h"
-#include "cros_version.h"
-#include "flash.h"
-#include "gpio_chip.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "watchdog.h"
-
-#ifdef CONFIG_STM32_CLOCK_LSE
-#define BDCR_SRC BDCR_SRC_LSE
-#define BDCR_RDY STM32_RCC_BDCR_LSERDY
-#else
-#define BDCR_SRC BDCR_SRC_LSI
-#define BDCR_RDY 0
-#endif
-#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \
-			BDCR_RDY)
-#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \
-			STM32_RCC_BDCR_BDRST)
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3);
-#endif
-
-void __no_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_COMMON_RUNTIME
-	/*
-	 * Hibernate not implemented on this platform.
-	 *
-	 * Until then, treat this as a request to hard-reboot.
-	 */
-	cprints(CC_SYSTEM, "hibernate not supported, so rebooting");
-	cflush();
-	system_reset(SYSTEM_RESET_HARD);
-#endif
-}
-
-void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
-	__attribute__((weak, alias("__no_hibernate")));
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-#ifdef CONFIG_HOSTCMD_PD
-	/* Inform the PD MCU that we are going to hibernate. */
-	host_command_pd_request_hibernate();
-	/* Wait to ensure exchange with PD before hibernating. */
-	msleep(100);
-#endif
-
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	__enter_hibernate(seconds, microseconds);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	return bkpdata_read_reset_flags();
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	bkpdata_write_reset_flags(flags);
-}
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = chip_read_reset_flags();
-	uint32_t raw_cause = STM32_RCC_RESET_CAUSE;
-#ifdef STM32_PWR_RESET_CAUSE
-	uint32_t pwr_status = STM32_PWR_RESET_CAUSE;
-#endif
-
-	/* Clear the hardware reset cause by setting the RMVF bit */
-	STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF;
-#ifdef STM32_PWR_RESET_CAUSE
-	/* Clear SBF in PWR_CSR */
-	STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR;
-#endif
-	/* Clear saved reset flags */
-	chip_save_reset_flags(0);
-
-	if (raw_cause & RESET_CAUSE_WDG) {
-		/*
-		 * IWDG or WWDG, if the watchdog was not used as an hard reset
-		 * mechanism
-		 */
-		if (!(flags & EC_RESET_FLAG_HARD))
-			flags |= EC_RESET_FLAG_WATCHDOG;
-	}
-
-	if (raw_cause & RESET_CAUSE_SFT)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & RESET_CAUSE_POR)
-		flags |= EC_RESET_FLAG_POWER_ON;
-
-	if (raw_cause & RESET_CAUSE_PIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-#ifdef STM32_PWR_RESET_CAUSE
-	if (pwr_status & RESET_CAUSE_SBF)
-		/* Hibernated and subsequently awakened */
-		flags |= EC_RESET_FLAG_HIBERNATE;
-#endif
-
-	if (!flags && (raw_cause & RESET_CAUSE_OTHER))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	/*
-	 * WORKAROUND: as we cannot de-activate the watchdog during
-	 * long hibernation, we are woken-up once by the watchdog and
-	 * go back to hibernate if we detect that condition, without
-	 * watchdog initialized this time.
-	 * The RTC deadline (if any) is already set.
-	 */
-	if ((flags & EC_RESET_FLAG_HIBERNATE) &&
-	    (flags & EC_RESET_FLAG_WATCHDOG)) {
-		__enter_hibernate(0, 0);
-	}
-
-	system_set_reset_flags(flags);
-}
-
-/* Stop all timers and WDGs we might use when JTAG stops the CPU. */
-void chip_pre_init(void)
-{
-	uint32_t apb1fz_reg = 0;
-	uint32_t apb2fz_reg = 0;
-
-#if defined(CHIP_FAMILY_STM32F0)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
-		STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
-
-	/* enable clock to debug module before writing */
-	STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN;
-#elif defined(CHIP_FAMILY_STM32F3)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17;
-#elif defined(CHIP_FAMILY_STM32F4)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2  | STM32_RCC_PB1_TIM3  | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5  | STM32_RCC_PB1_TIM6  | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14|
-		STM32_RCC_PB1_RTC   | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1  | STM32_RCC_PB2_TIM8  | STM32_RCC_PB2_TIM9 |
-		STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11;
-#elif defined(CHIP_FAMILY_STM32L4)
-
-#ifdef	CHIP_VARIANT_STM32L431X
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16;
-#else
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8;
-#endif
-#elif defined(CHIP_FAMILY_STM32L)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
-		STM32_RCC_PB2_TIM11;
-#elif defined(CHIP_FAMILY_STM32G4)
-	apb1fz_reg =
-		STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
-		STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
-		STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
-		STM32_DBGMCU_APB1FZ_RTC  | STM32_DBGMCU_APB1FZ_WWDG |
-		STM32_DBGMCU_APB1FZ_IWDG;
-	apb2fz_reg =
-		STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
-		STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
-		STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* TODO(b/67081508) */
-#endif
-#if defined(CHIP_FAMILY_STM32L5)
-	(void)apb1fz_reg;
-	(void)apb2fz_reg;
-#else
-	if (apb1fz_reg)
-		STM32_DBGMCU_APB1FZ |= apb1fz_reg;
-	if (apb2fz_reg)
-		STM32_DBGMCU_APB2FZ |= apb2fz_reg;
-#endif
-}
-
-#ifdef CONFIG_PVD
-/******************************************************************************
- * Detects sagging Vdd voltage and resets the system via the programmable
- * voltage detector interrupt.
- */
-static void configure_pvd(void)
-{
-	/* Clear Interrupt Enable Mask Register. */
-	STM32_EXTI_IMR &= ~EXTI_PVD_EVENT;
-
-	/* Clear Rising and Falling Trigger Selection Registers. */
-	STM32_EXTI_RTSR &= ~EXTI_PVD_EVENT;
-	STM32_EXTI_FTSR &= ~EXTI_PVD_EVENT;
-
-	/* Clear the value of the PVD Level Selection. */
-	STM32_PWR_CR &= ~STM32_PWD_PVD_LS_MASK;
-
-	/* Set the new value of the PVD Level Selection. */
-	STM32_PWR_CR |= STM32_PWD_PVD_LS(PVD_THRESHOLD);
-
-	/* Enable Power Clock. */
-	STM32_RCC_APB1ENR |= STM32_RCC_PB1_PWREN;
-
-	/* Configure the NVIC for PVD. */
-	task_enable_irq(STM32_IRQ_PVD);
-
-	/* Configure interrupt mode. */
-	STM32_EXTI_IMR |= EXTI_PVD_EVENT;
-	STM32_EXTI_RTSR |= EXTI_PVD_EVENT;
-
-	/* Enable the PVD Output. */
-	STM32_PWR_CR |= STM32_PWR_PVDE;
-}
-
-void pvd_interrupt(void)
-{
-	/* Clear Pending Register */
-	STM32_EXTI_PR = EXTI_PVD_EVENT;
-	/* Handle recovery by rebooting the system */
-	system_reset(0);
-}
-DECLARE_IRQ(STM32_IRQ_PVD, pvd_interrupt, HOOK_PRIO_FIRST);
-
-#endif /* CONFIG_PVD */
-
-void system_pre_init(void)
-{
-#ifdef CONFIG_SOFTWARE_PANIC
-	uint16_t reason, info;
-	uint8_t exception, panic_flags;
-#endif
-
-	/* enable clock on Power module */
-#ifndef CHIP_FAMILY_STM32H7
-#ifdef	CHIP_FAMILY_STM32L4
-	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
-#else
-	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
-#endif
-#endif
-#if defined(CHIP_FAMILY_STM32F4)
-	/* enable backup registers */
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN;
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* enable backup registers */
-	STM32_RCC_AHB4ENR |= BIT(28);
-#elif defined(CHIP_FAMILY_STM32L4)
-	/* enable RTC APB clock */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN;
-#else
-	/* enable backup registers */
-	STM32_RCC_APB1ENR |= BIT(27);
-#endif
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* Enable access to RCC CSR register and RTC backup registers */
-	STM32_PWR_CR |= BIT(8);
-#ifdef CHIP_VARIANT_STM32L476
-	/* Enable Vddio2 */
-	STM32_PWR_CR2 |= BIT(9);
-#endif
-
-	/* switch on LSI */
-	STM32_RCC_CSR |= BIT(0);
-	/* Wait for LSI to be ready */
-	while (!(STM32_RCC_CSR & BIT(1)))
-		;
-
-#if defined(CHIP_FAMILY_STM32G4)
-	/* Make sure PWR clock is enabled */
-	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
-	/* Enable access to backup domain registers */
-	STM32_PWR_CR1 |= STM32_PWR_CR1_DBP;
-#endif
-	/* re-configure RTC if needed */
-#ifdef CHIP_FAMILY_STM32L
-	if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
-		/* The RTC settings are bad, we need to reset it */
-		STM32_RCC_CSR |= 0x00800000;
-		/* Enable RTC and use LSI as clock source */
-		STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
-	}
-#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) ||	\
-	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4)
-	if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) {
-		/* The RTC settings are bad, we need to reset it */
-		STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
-		STM32_RCC_BDCR = STM32_RCC_BDCR & ~BDCR_ENABLE_MASK;
-#ifdef CONFIG_STM32_CLOCK_LSE
-		/* Turn on LSE */
-		STM32_RCC_BDCR |= STM32_RCC_BDCR_LSEON;
-		/* Wait for LSE to be ready */
-		while (!(STM32_RCC_BDCR & STM32_RCC_BDCR_LSERDY))
-			;
-#endif
-		/* Select clock source and enable RTC */
-		STM32_RCC_BDCR |= BDCR_RTCSEL(BDCR_SRC) | STM32_RCC_BDCR_RTCEN;
-	}
-#else
-#error "Unsupported chip family"
-#endif
-
-	check_reset_cause();
-
-#ifdef CONFIG_SOFTWARE_PANIC
-	/* Restore then clear saved panic reason */
-	reason = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_REASON);
-	info = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_INFO);
-	exception = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION);
-	panic_flags = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_FLAGS);
-	if (reason || info || exception || panic_flags) {
-		panic_set_reason(reason, info, exception);
-		panic_get_data()->flags = panic_flags;
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, 0);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, 0);
-	}
-#endif
-
-#ifdef CONFIG_PVD
-	configure_pvd();
-#endif
-}
-
-void system_reset(int flags)
-{
-	uint32_t save_flags = 0;
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	/*
-	 * TODO(crbug.com/1045283): Change this part of code to use
-	 * system_encode_save_flags, like all other system_reset functions.
-	 *
-	 * system_encode_save_flags(flags, &save_flags);
-	 */
-
-	/* Save current reset reasons if necessary */
-	if (flags & SYSTEM_RESET_PRESERVE_FLAGS)
-		save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED;
-
-	if (flags & SYSTEM_RESET_LEAVE_AP_OFF)
-		save_flags |= EC_RESET_FLAG_AP_OFF;
-
-	/* Remember that the software asked us to hard reboot */
-	if (flags & SYSTEM_RESET_HARD)
-		save_flags |= EC_RESET_FLAG_HARD;
-
-	/* Add in stay in RO flag into saved flags. */
-	if (flags & SYSTEM_RESET_STAY_IN_RO)
-		save_flags |= EC_RESET_FLAG_STAY_IN_RO;
-
-	if (flags & SYSTEM_RESET_AP_WATCHDOG)
-		save_flags |= EC_RESET_FLAG_AP_WATCHDOG;
-
-	chip_save_reset_flags(save_flags);
-
-#ifdef CONFIG_ARMV7M_CACHE
-	/*
-	 * Disable caches (D-cache is also flushed and invalidated)
-	 * so changes that lives in cache are saved in memory now.
-	 * Any subsequent writes will be done immediately.
-	 */
-	cpu_disable_caches();
-#endif
-
-	if (flags & SYSTEM_RESET_HARD) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		uint32_t reason, info;
-		uint8_t exception;
-		uint8_t panic_flags = panic_get_data()->flags;
-
-		/* Panic data will be wiped by hard reset, so save it */
-		panic_get_reason(&reason, &info, &exception);
-		/* 16 bits stored - upper 16 bits of reason / info are lost */
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, exception);
-		bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, panic_flags);
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4)
-		/*
-		 * Ask the flash module to reboot, so that we reload the
-		 * option bytes.
-		 */
-		crec_flash_physical_force_reload();
-
-		/* Fall through to watchdog if that fails */
-#endif
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-		/*
-		 * On some chips, a reboot doesn't always reload the option
-		 * bytes, and we need to explicitly request for a reload.
-		 * The reload request triggers a chip reset, so let's just
-		 * use this for hard reset.
-		 */
-		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#elif defined(CHIP_FAMILY_STM32G4)
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
-		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
-		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
-		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#else
-		/*
-		 * RM0433 Rev 6
-		 * Section 44.3.3
-		 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf#page=1898
-		 *
-		 * When the window option is not used, the IWDG can be
-		 * configured as follows:
-		 *
-		 * 1. Enable the IWDG by writing 0x0000 CCCC in the Key
-		 *    register (IWDG_KR).
-		 * 2. Enable register access by writing 0x0000 5555 in the Key
-		 *    register (IWDG_KR).
-		 * 3. Write the prescaler by programming the Prescaler register
-		 *    (IWDG_PR) from 0 to 7.
-		 * 4. Write the Reload register (IWDG_RLR).
-		 * 5. Wait for the registers to be updated
-		 *    (IWDG_SR = 0x0000 0000).
-		 * 6. Refresh the counter value with IWDG_RLR
-		 *    (IWDG_KR = 0x0000 AAAA)
-		 */
-
-		/*
-		 * RM0433 Rev 7
-		 * Section 45.4.4 Page 1920
-		 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-		 * If several reload, prescaler, or window values are used by
-		 * the application, it is mandatory to wait until RVU bit is
-		 * reset before changing the reload value, to wait until PVU bit
-		 * is reset before changing the prescaler value, and to wait
-		 * until WVU bit is reset before changing the window value.
-		 *
-		 * Here we should wait to finish previous IWDG_RLR register
-		 * update (see watchdog_init()) before starting next update,
-		 * otherwise new IWDG_RLR value will be lost.
-		 */
-		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
-			;
-
-		/*
-		 * Enable IWDG, which shouldn't be necessary since the IWDG
-		 * only needs to be started once, but STM32F412 hangs unless
-		 * this is added.
-		 *
-		 * See http://b/137045370.
-		 */
-		STM32_IWDG_KR = STM32_IWDG_KR_START;
-
-		/* Ask the watchdog to trigger a hard reboot */
-		STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
-		STM32_IWDG_RLR = 0x1;
-		/* Wait for value to be updated. */
-		while (STM32_IWDG_SR & STM32_IWDG_SR_RVU)
-			;
-
-		/* Reload IWDG counter, it also locks registers */
-		STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-#endif
-		/* wait for the chip to reboot */
-		while (1)
-			;
-	} else {
-		if (flags & SYSTEM_RESET_WAIT_EXT) {
-			int i;
-
-			/* Wait 10 seconds for external reset */
-			for (i = 0; i < 1000; i++) {
-				watchdog_reload();
-				udelay(10000);
-			}
-		}
-
-		/* Request a soft system reset from the core. */
-		CPU_NVIC_APINT = CPU_NVIC_APINT_KEY_WR | CPU_NVIC_APINT_SYSRST;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	/* Check if value fits in 16 bits */
-	if (value & 0xffff0000)
-		return EC_ERROR_INVAL;
-	return bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, (uint16_t)value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	*value = (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD);
-	return EC_SUCCESS;
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "stm";
-}
-
-const char *system_get_chip_name(void)
-{
-	return STRINGIFY(CHIP_VARIANT);
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-int system_get_chip_unique_id(uint8_t **id)
-{
-	*id = (uint8_t *)STM32_UNIQUE_ID_ADDRESS;
-	return STM32_UNIQUE_ID_LENGTH;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int msb = 0;
-	int bkpdata_index = bkpdata_index_lookup(idx, &msb);
-
-	if (bkpdata_index < 0)
-		return EC_ERROR_INVAL;
-
-	*value = (bkpdata_read(bkpdata_index) >> (8 * msb)) & 0xff;
-	return EC_SUCCESS;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	uint16_t read;
-	int msb = 0;
-	int bkpdata_index = bkpdata_index_lookup(idx, &msb);
-
-	if (bkpdata_index < 0)
-		return EC_ERROR_INVAL;
-
-	read = bkpdata_read(bkpdata_index);
-	if (msb)
-		read = (read & 0xff) | (value << 8);
-	else
-		read = (read & 0xff00) | value;
-
-	bkpdata_write(bkpdata_index, read);
-	return EC_SUCCESS;
-}
-
-int system_is_reboot_warm(void)
-{
-	/*
-	 * Detecting if the system is warm is relevant for a
-	 * few reasons.
-	 * One such reason is that some firmwares transition from
-	 * RO to RW images. When this happens, we may not need to
-	 * restart certain clocks. On the flip side, we may need
-	 * to restart the clocks if the RW requires a different
-	 * set of clocks. Thus, the clock configurations need to
-	 * be checked for a perfect match.
-	 */
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	return ((STM32_RCC_AHBENR & 0x7e0000) == 0x7e0000);
-#elif defined(CHIP_FAMILY_STM32L)
-	return ((STM32_RCC_AHBENR & 0x3f) == 0x3f);
-#elif defined(CHIP_FAMILY_STM32L4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
-#elif defined(CHIP_FAMILY_STM32L5)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
-#elif defined(CHIP_FAMILY_STM32F4)
-	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK)
-			== gpio_required_clocks());
-#elif defined(CHIP_FAMILY_STM32G4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== gpio_required_clocks());
-#elif defined(CHIP_FAMILY_STM32H7)
-	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK)
-			== STM32_RCC_AHB4ENR_GPIOMASK);
-#endif
-}
diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c
deleted file mode 100644
index 48d5335c53..0000000000
--- a/chip/stm32/trng.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Hardware Random Number Generator */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "panic.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "trng.h"
-#include "util.h"
-
-uint32_t rand(void)
-{
-	int tries = 300;
-	/* Wait for a valid random number */
-	while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries)
-		;
-	/* we cannot afford to feed the caller with an arbitrary number */
-	if (!tries)
-		software_panic(PANIC_SW_BAD_RNG, task_get_current());
-	/* Finally the 32-bit of entropy */
-	return STM32_RNG_DR;
-}
-
-test_mockable void rand_bytes(void *buffer, size_t len)
-{
-	while (len) {
-		uint32_t number = rand();
-		size_t cnt = 4;
-		/* deal with the lack of alignment guarantee in the API */
-		uintptr_t align = (uintptr_t)buffer & 3;
-
-		if (len < 4 || align) {
-			cnt = MIN(4 - align, len);
-			memcpy(buffer, &number, cnt);
-		} else {
-			*(uint32_t *)buffer = number;
-		}
-		len -= cnt;
-		buffer += cnt;
-	}
-}
-
-test_mockable void init_trng(void)
-{
-#ifdef CHIP_FAMILY_STM32L4
-	/* Enable the 48Mhz internal RC oscillator */
-	STM32_RCC_CRRCR |= STM32_RCC_CRRCR_HSI48ON;
-	/* no timeout: we watchdog if the oscillator doesn't start */
-	while (!(STM32_RCC_CRRCR & STM32_RCC_CRRCR_HSI48RDY))
-		;
-
-	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK)
-			| (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
-#elif defined(CHIP_FAMILY_STM32H7)
-	/* Enable the 48Mhz internal RC oscillator */
-	STM32_RCC_CR |= STM32_RCC_CR_HSI48ON;
-	/* no timeout: we watchdog if the oscillator doesn't start */
-	while (!(STM32_RCC_CR & STM32_RCC_CR_HSI48RDY))
-		;
-
-	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_D2CCIP2R =
-		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK)
-			| STM32_RCC_D2CCIP2_RNGSEL_HSI48;
-#elif defined(CHIP_FAMILY_STM32F4)
-	/*
-	 * The RNG clock is the same as the SDIO/USB OTG clock, already set at
-	 * 48 MHz during clock initialisation. Nothing to do.
-	 */
-#else
-#error "Please add support for CONFIG_RNG on this chip family."
-#endif
-	/* Enable the RNG logic */
-	STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_RNGEN;
-	/* Start the random number generation */
-	STM32_RNG_CR |= STM32_RNG_CR_RNGEN;
-}
-
-test_mockable void exit_trng(void)
-{
-	STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN;
-	STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN;
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON;
-#elif defined(CHIP_FAMILY_STM32H7)
-	STM32_RCC_CR &= ~STM32_RCC_CR_HSI48ON;
-#elif defined(CHIP_FAMILY_STM32F4)
-	/* Nothing to do */
-#endif
-}
-
-#if defined(CONFIG_CMD_RAND)
-/*
- * We want to avoid accidentally exposing debug commands in RO since we can't
- * update RO once in production.
- */
-#if defined(SECTION_IS_RW)
-static int command_rand(int argc, char **argv)
-{
-	uint8_t data[32];
-
-	init_trng();
-	rand_bytes(data, sizeof(data));
-	exit_trng();
-
-	ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data)));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rand, command_rand,
-			NULL, "Output random bytes to console.");
-
-static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rand_num *p = args->params;
-	struct ec_response_rand_num *r = args->response;
-	uint16_t num_rand_bytes = p->num_rand_bytes;
-
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (num_rand_bytes > args->response_max)
-		return EC_RES_OVERFLOW;
-
-	init_trng();
-	rand_bytes(r->rand, num_rand_bytes);
-	exit_trng();
-
-	args->response_size = num_rand_bytes;
-
-	return EC_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand,
-		     EC_VER_MASK(EC_VER_RAND_NUM));
-#endif /* SECTION_IS_RW */
-#endif /* CONFIG_CMD_RAND */
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
deleted file mode 100644
index 0632fc6687..0000000000
--- a/chip/stm32/uart.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "common.h"
-#include "clock.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-#include "stm32-dma.h"
-
-/* Console USART index */
-#define UARTN      CONFIG_UART_CONSOLE
-#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
-
-#ifdef CONFIG_UART_TX_DMA
-#define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE
-
-#ifndef CONFIG_UART_TX_DMA_CH
-#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
-#endif
-
-/* DMA channel options; assumes UART1 */
-static const struct dma_option dma_tx_option = {
-	CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-#ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
-#endif
-};
-
-#else
-#define UART_TX_INT_ENABLE STM32_USART_CR1_TXEIE
-#endif
-
-#ifdef CONFIG_UART_RX_DMA
-
-#ifndef CONFIG_UART_RX_DMA_CH
-#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART1_RX
-#endif
-/* DMA channel options; assumes UART1 */
-static const struct dma_option dma_rx_option = {
-	CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE),
-	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-#ifdef CHIP_FAMILY_STM32F4
-	STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
-#endif
-	STM32_DMA_CCR_CIRC
-};
-
-static int dma_rx_len;   /* Size of receive DMA circular buffer */
-#endif
-
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	/* If interrupt is already enabled, nothing to do */
-	if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE)
-		return;
-
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE |
-				       STM32_USART_CR1_TCIE;
-	task_trigger_irq(STM32_IRQ_USART(UARTN));
-}
-
-void uart_tx_stop(void)
-{
-	STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE;
-	should_stop = 1;
-#ifdef CONFIG_UART_TX_DMA
-	enable_sleep(SLEEP_MASK_UART);
-#endif
-}
-
-void uart_tx_flush(void)
-{
-	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
-		;
-}
-
-int uart_tx_ready(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE;
-}
-
-#ifdef CONFIG_UART_TX_DMA
-
-int uart_tx_dma_ready(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC;
-}
-
-void uart_tx_dma_start(const char *src, int len)
-{
-	/* Prepare DMA */
-	dma_prepare_tx(&dma_tx_option, len, src);
-
-	/* Force clear TC so we don't re-interrupt */
-	STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
-
-	/* Enable TCIE (chrome-os-partner:28837) */
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE;
-
-	/* Start DMA */
-	dma_go(dma_get_channel(dma_tx_option.channel));
-}
-
-#endif /* CONFIG_UART_TX_DMA */
-
-int uart_rx_available(void)
-{
-	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE;
-}
-
-#ifdef CONFIG_UART_RX_DMA
-
-void uart_rx_dma_start(char *dest, int len)
-{
-	/* Start receiving */
-	dma_rx_len = len;
-	dma_start_rx(&dma_rx_option, len, dest);
-}
-
-int uart_rx_dma_head(void)
-{
-	return dma_bytes_done(dma_get_channel(CONFIG_UART_RX_DMA_CH),
-			      dma_rx_len);
-}
-
-#endif
-
-void uart_write_char(char c)
-{
-	/* Wait for space */
-	while (!uart_tx_ready())
-		;
-
-	STM32_USART_TDR(UARTN_BASE) = c;
-}
-
-int uart_read_char(void)
-{
-	return STM32_USART_RDR(UARTN_BASE);
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_TX_DMA
-	/*
-	 * When transmission completes, enable sleep if we are done with Tx.
-	 * After that, proceed if there is other interrupt to handle.
-	 */
-	if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) {
-		if (should_stop) {
-			STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
-			enable_sleep(SLEEP_MASK_UART);
-		}
-#if defined(CHIP_FAMILY_STM32F4)
-		STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
-#else
-		STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC;
-#endif
-		if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC))
-			return;
-	}
-#endif
-
-#ifdef CONFIG_UART_TX_DMA
-	/* Disable transmission complete interrupt if DMA done */
-	if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
-#else
-	/*
-	 * Disable the TX empty interrupt before filling the TX buffer since it
-	 * needs an actual write to DR to be cleared.
-	 */
-	STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE;
-#endif
-
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	/*
-	 * Re-enable TX empty interrupt only if it was not disabled by
-	 * uart_process_output().
-	 */
-	if (!should_stop)
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE;
-#endif
-}
-DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2);
-
-/**
- * Handle clock frequency changes
- */
-static void uart_freq_change(void)
-{
-	int freq;
-	int div;
-
-#if (defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) && \
-	(UARTN <= 2)
-	/*
-	 * UART is clocked from HSI (8MHz) to allow it to work when waking
-	 * up from sleep
-	 */
-	freq = 8000000;
-#elif defined(CHIP_FAMILY_STM32H7)
-	freq = 64000000; /* from 64 Mhz HSI */
-#elif defined(CHIP_FAMILY_STM32L4)
-	/* UART clocked from HSI 16 */
-	freq = 16000000;
-#else
-	/* UART clocked from the main clock */
-	freq = clock_get_freq();
-#endif
-
-#if (UARTN == 9)	/* LPUART */
-	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256;
-#else
-	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE);
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \
-	defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4)
-	if (div / 16 > 0) {
-		/*
-		 * CPU clock is high enough to support x16 oversampling.
-		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
-		 */
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(UARTN_BASE) = div;
-	} else {
-		/*
-		 * CPU clock is low; use x8 oversampling.
-		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
-		 */
-		STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8;
-	}
-#else
-	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(UARTN_BASE) = div;
-#endif
-
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT);
-
-void uart_init(void)
-{
-	/* Select clock source */
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-#if (UARTN == 1)
-	STM32_RCC_CFGR3 |= 0x0003;   /* USART1 clock source from HSI(8MHz) */
-#elif (UARTN == 2)
-	STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */
-#endif /* UARTN */
-#elif defined(CHIP_FAMILY_STM32H7) /* Clocked from 64 Mhz HSI */
-#if ((UARTN == 1) || (UARTN == 6))
-	STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART16SEL_HSI;
-#else
-	STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART234578SEL_HSI;
-#endif /* UARTN */
-#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4)
-	/* USART1 clock source from SYSCLK */
-	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK;
-#ifdef CHIP_FAMILY_STM32L4
-	/* For STM32L4, use HSI for UART, to wake up from low power mode */
-	STM32_RCC_CCIPR |=
-		(STM32_RCC_CCIPR_UART_HSI16 << STM32_RCC_CCIPR_USART1SEL_SHIFT);
-#else
-	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
-			    << STM32_RCC_CCIPR_USART1SEL_SHIFT);
-#endif
-	/* LPUART1 clock source from SYSCLK */
-	STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK;
-	STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK
-			    << STM32_RCC_CCIPR_LPUART1SEL_SHIFT);
-#endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */
-
-	/* Enable USART clock */
-#if (UARTN == 1)
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
-#ifdef CHIP_FAMILY_STM32L4
-#if defined(CONFIG_UART_RX_DMA) || defined(CONFIG_UART_TX_DMA)
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1;
-	STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA2;
-#endif
-#endif
-#elif (UARTN == 6)
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART6;
-#elif (UARTN == 9)
-	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_LPUART1EN;
-#else
-	STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN);
-#endif
-
-	/*
-	 * For STM32F3, A delay of 1 APB clock cycles is needed before we
-	 * can access any USART register. Fortunately, we have
-	 * gpio_config_module() below and thus don't need to add the delay.
-	 */
-
-	/* Configure GPIOs */
-	gpio_config_module(MODULE_UART, 1);
-
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \
-|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4)
-	/*
-	 * Wake up on start bit detection. WUS can only be written when UE=0,
-	 * so clear UE first.
-	 */
-	STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE;
-
-	/*
-	 * Also disable the RX overrun interrupt, since we don't care about it
-	 * and we don't want to clear an extra flag in the interrupt
-	 */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
-	                               STM32_USART_CR3_OVRDIS;
-#endif
-
-	/*
-	 * UART enabled, 8 Data bits, oversampling x16, no parity,
-	 * TX and RX enabled.
-	 */
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-#else
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
-#endif
-
-	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN_BASE) = 0x0000;
-
-#ifdef CONFIG_UART_TX_DMA
-	/* Enable DMA transmitter */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT;
-#ifdef CONFIG_UART_TX_DMA_PH
-	dma_select_channel(CONFIG_UART_TX_DMA_CH, CONFIG_UART_TX_DMA_PH);
-#endif
-#else
-	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR &
-				       ~STM32_USART_CR3_DMAT &
-				       ~STM32_USART_CR3_EIE;
-#endif
-
-#ifdef CONFIG_UART_RX_DMA
-	/* Enable DMA receiver */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR;
-#else
-	/* Enable receive-not-empty interrupt */
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE;
-#endif
-
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4)
-	/* Use single-bit sampling */
-	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT;
-#endif
-
-	/* Set initial baud rate */
-	uart_freq_change();
-
-	/* Enable interrupts */
-	task_enable_irq(STM32_IRQ_USART(UARTN));
-
-#ifdef CHIP_FAMILY_STM32L4
-	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UE;
-#endif
-
-	init_done = 1;
-}
-
-#ifdef CONFIG_FORCE_CONSOLE_RESUME
-void uart_enable_wakeup(int enable)
-{
-	if (enable) {
-		/*
-		 * Allow UART wake up from STOP mode. Note, UART clock must
-		 * be HSI(8MHz) for wakeup to work.
-		 */
-		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM;
-		STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE;
-	} else {
-		/* Disable wake up from STOP mode. */
-		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM;
-	}
-}
-#endif
diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
deleted file mode 100644
index ef6ec92a89..0000000000
--- a/chip/stm32/ucpd-stm32gx.c
+++ /dev/null
@@ -1,1615 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* STM32GX UCPD module for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "driver/tcpm/tcpm.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "ucpd-stm32gx.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define USB_VID_STM32 0x0483
-
-/*
- * USB PD message buffer length. Absent extended messages, the longest PD
- * message will be 7 objects (4 bytes each) plus a 2 byte header. TCPMv2
- * suports extended messages via chunking so the data buffer length is
- * set assumign that extended messages are chunked.
- */
-#define UCPD_BUF_LEN 30
-
-#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \
-			      STM32_UCPD_IMR_RXORDDETIE | \
-			      STM32_UCPD_IMR_RXHRSTDETIE |	\
-			      STM32_UCPD_IMR_RXOVRIE |		\
-			      STM32_UCPD_IMR_RXMSGENDIE)
-
-#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \
-			      STM32_UCPD_IMR_TXMSGDISCIE |     \
-			      STM32_UCPD_IMR_TXMSGSENTIE |     \
-			      STM32_UCPD_IMR_TXMSGABTIE |      \
-			      STM32_UCPD_IMR_TXUNDIE)
-
-#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \
-			      STM32_UCPD_ICR_TXMSGSENTCF |     \
-			      STM32_UCPD_ICR_TXMSGABTCF |     \
-			      STM32_UCPD_ICR_TXUNDCF)
-
-#define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
-#define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3)
-
-struct msg_header_info {
-	enum pd_power_role pr;
-	enum pd_data_role dr;
-};
-static struct msg_header_info msg_header;
-
-/* States for managing tx messages in ucpd task */
-enum ucpd_state {
-	STATE_IDLE,
-	STATE_ACTIVE_TCPM,
-	STATE_ACTIVE_CRC,
-	STATE_HARD_RESET,
-	STATE_WAIT_CRC_ACK,
-};
-
-/* Events for pd_interrupt_handler_task */
-#define UCPD_EVT_GOOD_CRC_REQ   BIT(0)
-#define UCPD_EVT_TCPM_MSG_REQ   BIT(1)
-#define UCPD_EVT_HR_REQ         BIT(2)
-#define UCPD_EVT_TX_MSG_FAIL    BIT(3)
-#define UCPD_EVT_TX_MSG_DISC    BIT(4)
-#define UCPD_EVT_TX_MSG_SUCCESS BIT(5)
-#define UCPD_EVT_HR_DONE        BIT(6)
-#define UCPD_EVT_HR_FAIL        BIT(7)
-#define UCPD_EVT_RX_GOOD_CRC    BIT(8)
-#define UCPD_EVT_RX_MSG         BIT(9)
-
-#define UCPD_T_RECEIVE_US (1 * MSEC)
-
-#define UCPD_N_RETRY_COUNT_REV20 3
-#define UCPD_N_RETRY_COUNT_REV30 2
-
-/*
- * Tx messages are iniated either by TCPM/PRL layer or from ucpd when a GoodCRC
- * ack message needs to be sent.
- */
-enum ucpd_tx_msg {
-	TX_MSG_NONE = -1,
-	TX_MSG_TCPM = 0,
-	TX_MSG_GOOD_CRC = 1,
-	TX_MSG_TOTAL = 2,
-};
-
-#define MSG_TCPM_MASK BIT(TX_MSG_TCPM)
-#define MSG_GOOD_CRC_MASK BIT(TX_MSG_GOOD_CRC)
-
-union buffer {
-	uint16_t header;
-	uint8_t msg[UCPD_BUF_LEN];
-};
-
-struct ucpd_tx_desc {
-	enum tcpci_msg_type type;
-	int msg_len;
-	int msg_index;
-	union buffer data;
-};
-
-/* Track VCONN on/off state */
-static int ucpd_vconn_enable;
-
-/* Tx message variables */
-struct ucpd_tx_desc ucpd_tx_buffers[TX_MSG_TOTAL];
-struct ucpd_tx_desc *ucpd_tx_active_buffer;
-static int ucpd_tx_request;
-static int ucpd_timeout_us;
-static enum ucpd_state ucpd_tx_state;
-static int msg_id_match;
-static int tx_retry_count;
-static int tx_retry_max;
-
-static int ucpd_txorderset[] = {
-	TX_ORDERSET_SOP,
-	TX_ORDERSET_SOP_PRIME,
-	TX_ORDERSET_SOP_PRIME_PRIME,
-	TX_ORDERSET_SOP_PRIME_DEBUG,
-	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG,
-	TX_ORDERSET_HARD_RESET,
-	TX_ORDERSET_CABLE_RESET,
-};
-
-/* PD Rx variables */
-static int ucpd_rx_byte_count;
-static uint8_t ucpd_rx_buffer[UCPD_BUF_LEN];
-static int ucpd_crc_id;
-static bool ucpd_rx_sop_prime_enabled;
-static int ucpd_rx_msg_active;
-static bool ucpd_rx_bist_mode;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-/* Defines and macros for ucpd state logging */
-#define TX_STATE_LOG_LEN BIT(5)
-#define TX_STATE_LOG_MASK (TX_STATE_LOG_LEN - 1)
-
-struct ucpd_tx_state {
-	uint32_t ts;
-	int tx_request;
-	int timeout_us;
-	enum ucpd_state enter_state;
-	enum ucpd_state exit_state;
-	uint32_t evt;
-};
-
-struct ucpd_tx_state ucpd_tx_statelog[TX_STATE_LOG_LEN];
-int ucpd_tx_state_log_idx;
-int ucpd_tx_state_log_freeze;
-
-static char ucpd_names[][12] = {
-	"TX_IDLE",
-	"ACT_TCPM",
-	"ACT_CRC",
-	"HARD_RST",
-	"WAIT_CRC",
-};
-/* Defines and macros used for ucpd pd message logging */
-#define MSG_LOG_LEN 64
-#define MSG_BUF_LEN 10
-
-struct msg_info {
-	uint8_t dir;
-	uint8_t comp;
-	uint8_t crc;
-	uint16_t header;
-	uint32_t ts;
-	uint8_t buf[MSG_BUF_LEN];
-};
-static int msg_log_cnt;
-static int msg_log_idx;
-static struct msg_info msg_log[MSG_LOG_LEN];
-
-#define UCPD_CC_STRING_LEN 5
-
-static char ccx[4][UCPD_CC_STRING_LEN] = {
-	"Ra",
-	"Rp",
-	"Rd",
-	"Open",
-};
-static char rp_string[][8] = {
-	"Rp_usb",
-	"Rp_1.5",
-	"Rp_3.0",
-	"Open",
-};
-static int ucpd_sr_cc_event;
-static int ucpd_cc_set_save;
-static int ucpd_cc_change_log;
-
-static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line);
-
-static void ucpd_log_add_msg(uint16_t header, int dir)
-{
-	uint32_t ts = __hw_clock_source_read();
-	int idx = msg_log_idx;
-	uint8_t *buf = dir ? ucpd_rx_buffer : ucpd_tx_active_buffer->data.msg;
-
-	/*
-	 * Add a msg entry in the history log. The log is currently designed to
-	 * be from reset until MSG_LOG_LEN messages have been added.
-	 * ts -> lower 32 bits of 1 uSec running clock
-	 * dir -> 0 = tx message, 1 = rx message
-	 * comp -> ucpd transmit success
-	 * crc -> GoodCrc received following tx message
-	 */
-	if (msg_log_cnt++ < MSG_LOG_LEN) {
-		int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2,
-				    MSG_BUF_LEN);
-
-		msg_log[idx].header = header;
-		msg_log[idx].ts = ts;
-		msg_log[idx].dir = dir;
-		msg_log[idx].comp = 0;
-		msg_log[idx].crc = 0;
-		msg_log_idx++;
-		memcpy(msg_log[idx].buf, buf, msg_bytes);
-	}
-}
-
-static void ucpd_log_mark_tx_comp(void)
-{
-	/*
-	 * This msg logging utility function is used to mark when a message was
-	 * successfully transmitted when transmit interrupt occurs and the tx
-	 * message sent status was set. Because the transmit message is added
-	 * before it's sent by ucpd, the index has to back up one to mark the
-	 * correct log entry.
-	 */
-	if (msg_log_cnt < MSG_LOG_LEN) {
-		if (msg_log_idx > 0)
-			msg_log[msg_log_idx - 1].comp = 1;
-	}
-}
-
-static void ucpd_log_mark_crc(void)
-{
-	/*
-	 * This msg logging utility function is used to mark when a GoodCRC
-	 * message is received following a tx message. This status is displayed
-	 * in column s2. Because this indication follows both transmit message
-	 * and GoodCRC rx, the index must be back up 2 rows to mark the correct
-	 * tx message entry.
-	 */
-	if (msg_log_cnt < MSG_LOG_LEN) {
-		if (msg_log_idx >= 2)
-			msg_log[msg_log_idx - 2].crc = 1;
-	}
-}
-
-static void ucpd_cc_status(int port)
-{
-	int rc = stm32gx_ucpd_get_role_control(port);
-	int cc1_pull, cc2_pull;
-	enum tcpc_cc_voltage_status v_cc1, v_cc2;
-	int rv;
-	char *rp_name;
-
-	cc1_pull = rc & 0x3;
-	cc2_pull = (rc >> 2) & 0x3;
-
-	/*
-	 * This function is used to display CC settings, including pull type,
-	 * and if Rp, what the Rp value is set to. In addition, the current
-	 * values of CC voltage detector, polarity, and PD enable status are
-	 * displayed.
-	 */
-	rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2);
-	rp_name = rp_string[(rc >> 4) % 0x3];
-	ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n",
-		 ccx[cc1_pull], ccx[cc2_pull], rp_name);
-	if (!rv)
-		ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2);
-}
-
-void ucpd_cc_detect_notify_enable(int enable)
-{
-	/*
-	 * This variable is used to control when a CC detach detector is
-	 * active.
-	 */
-	ucpd_cc_change_log = enable;
-}
-
-static void ucpd_log_invalidate_entry(void)
-{
-	/*
-	 * This is a msg log utility function which is triggered when an
-	 * unexpected detach event is detected.
-	 */
-	if (msg_log_idx < (MSG_LOG_LEN - 1)) {
-		int idx = msg_log_idx;
-
-		msg_log[idx].header = 0xabcd;
-		msg_log[idx].ts = __hw_clock_source_read();
-		msg_log[idx].dir = 0;
-		msg_log[idx].comp = 0;
-		msg_log[idx].crc = 0;
-		msg_log_cnt++;
-		msg_log_idx++;
-	}
-}
-
-/*
- * This function will mark in the msg log when a detach event occurs. It will
- * only be active if ucpd_cc_change_log is set which can be controlled via the
- * ucpd console command.
- */
-static void ucpd_cc_change_notify(void)
-{
-	if (ucpd_cc_change_log) {
-		uint32_t sr = ucpd_sr_cc_event;
-
-		ucpd_log_invalidate_entry();
-
-		ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n",
-			 (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3,
-			 (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3,
-			 (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT)
-			 & 0x3);
-		/* Display CC status on EC console */
-		ucpd_cc_status(0);
-	}
-}
-DECLARE_DEFERRED(ucpd_cc_change_notify);
-#endif /* CONFIG_STM32G4_UCPD_DEBUG */
-
-static int ucpd_msg_is_good_crc(uint16_t header)
-{
-	/*
-	 * Good CRC is a control message (no data objects) with GOOD_CRC message
-	 * type in the header.
-	 */
-	return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) &&
-		(PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0;
-}
-
-static void ucpd_hard_reset_rx_log(void)
-{
-	CPRINTS("ucpd: hard reset recieved");
-}
-DECLARE_DEFERRED(ucpd_hard_reset_rx_log);
-
-static void ucpd_port_enable(int port, int enable)
-{
-	if (enable)
-		STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN;
-	else
-		STM32_UCPD_CFGR1(port) &= ~STM32_UCPD_CFGR1_UCPDEN;
-}
-
-static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line)
-{
-	int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >>
-					       STM32_UCPD_CR_CCENABLE_SHIFT;
-
-	return ((cc_enable >> cc_line) & 0x1);
-}
-
-static void ucpd_tx_data_byte(int port)
-{
-	int index = ucpd_tx_active_buffer->msg_index++;
-
-	STM32_UCPD_TXDR(port) = ucpd_tx_active_buffer->data.msg[index];
-}
-
-static void ucpd_rx_data_byte(int port)
-{
-	if (ucpd_rx_byte_count < UCPD_BUF_LEN)
-		ucpd_rx_buffer[ucpd_rx_byte_count++] = STM32_UCPD_RXDR(port);
-}
-
-static void ucpd_tx_interrupts_enable(int port, int enable)
-{
-	if (enable) {
-		STM32_UCPD_ICR(port) = UCPD_ICR_TX_INT_MASK;
-		STM32_UCPD_IMR(port) |= UCPD_IMR_TX_INT_MASK;
-	} else {
-		STM32_UCPD_IMR(port) &= ~UCPD_IMR_TX_INT_MASK;
-	}
-}
-
-static void ucpd_rx_enque_error(void)
-{
-	CPRINTS("ucpd: TCPM Enque Error!!");
-}
-DECLARE_DEFERRED(ucpd_rx_enque_error);
-
-static void stm32gx_ucpd_state_init(int port)
-{
-	/* Init variables used to manage tx process */
-	ucpd_tx_request = 0;
-	tx_retry_count = 0;
-	ucpd_tx_state = STATE_IDLE;
-	ucpd_timeout_us = -1;
-
-	/* Init variables used to manage rx */
-	ucpd_rx_sop_prime_enabled = 0;
-	ucpd_rx_msg_active = 0;
-	ucpd_rx_bist_mode = 0;
-
-	/* Vconn tracking variable */
-	ucpd_vconn_enable = 0;
-}
-
-int stm32gx_ucpd_init(int port)
-{
-	uint32_t cfgr1_reg;
-	uint32_t moder_reg;
-
-	/* Disable UCPD interrupts */
-	task_disable_irq(STM32_IRQ_UCPD1);
-
-	/*
-	* After exiting reset, stm32gx will have dead battery mode enabled by
-	* default which connects Rd to CC1/CC2. This should be disabled when EC
-	* is powered up.
-	*/
-	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
-
-	/* Ensure that clock to UCPD is enabled */
-	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
-
-	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
-	moder_reg = STM32_GPIO_MODER(GPIO_B);
-	moder_reg |= 0x3300;
-	STM32_GPIO_MODER(GPIO_B) = moder_reg;
-	/*
-	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
-	 * disabling ucpd causes the peripheral to quit any ongoing activity and
-	 * sets all ucpd registers back their default values.
-	 */
-	ucpd_port_enable(port, 0);
-
-	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
-	STM32_UCPD_CFGR1(port) = cfgr1_reg;
-
-	/*
-	 * Set RXORDSETEN field to control which types of ordered sets the PD
-	 * receiver must receive.
-	 * SOP, SOP', Hard Reset Det, Cable Reset Det enabled
-	 */
-	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_RXORDSETEN_VAL(0x1B);
-
-	/* Enable ucpd  */
-	ucpd_port_enable(port, 1);
-
-	/* Configure CC change interrupts */
-	STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE |
-		STM32_UCPD_IMR_TYPECEVT2IE;
-	STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF |
-		STM32_UCPD_ICR_TYPECEVT2CF;
-
-	/* SOP'/SOP'' must be enabled via TCPCI call */
-	ucpd_rx_sop_prime_enabled = false;
-
-	stm32gx_ucpd_state_init(port);
-
-	/* Enable UCPD interrupts */
-	task_enable_irq(STM32_IRQ_UCPD1);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_release(int port)
-{
-	ucpd_port_enable(port, 0);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int vstate_cc1;
-	int vstate_cc2;
-	int anamode;
-	uint32_t sr;
-
-	/*
-	 * cc_voltage_status is determined from vstate_cc bit field in the
-	 * status register. The meaning of the value vstate_cc depends on
-	 * current value of ANAMODE (src/snk).
-	 *
-	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
-	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
-	 * If presenting Rp (source), then need to to a circular shift of
-	 * vstate_ccx value:
-	 *     vstate_cc | cc_state
-	 *     ------------------
-	 *        0     ->    1
-	 *        1     ->    2
-	 *        2     ->    0
-	 */
-
-	/* Get vstate_ccx values and power role */
-	sr = STM32_UCPD_SR(port);
-	/* Get Rp or Rd active */
-	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
-	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
-
-	/* Do circular shift if port == source */
-	if (anamode) {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc1 += 4;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA)
-			vstate_cc2 += 4;
-	} else {
-		if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc1 = (vstate_cc1 + 1) % 3;
-		if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN)
-			vstate_cc2 = (vstate_cc2 + 1) % 3;
-	}
-
-	*cc1 = vstate_cc1;
-	*cc2 = vstate_cc2;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_role_control(int port)
-{
-	int role_control;
-	int cc1;
-	int cc2;
-	int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK)
-		>> STM32_UCPD_CR_ANASUBMODE_SHIFT;
-
-	/*
-	 * Role control register is defined as:
-	 *     R_cc1 -> b 1:0
-	 *     R_cc2 -> b 3:2
-	 *     Rp    -> b 5:4
-	 *
-	 * In TCPCI, CCx is defined as:
-	 *    00b -> Ra
-	 *    01b -> Rp
-	 *    10b -> Rd
-	 *    11b -> Open (don't care)
-	 *
-	 * For ucpd, this information is encoded in ANAMODE and ANASUBMODE
-	 * fields as follows:
-	 *   ANAMODE            CCx
-	 *     0   ->    Rp   -> 1
-	 *     1   ->    Rd   -> 2
-	 *
-	 *   ANASUBMODE:
-	 *     00b -> TYPEC_RP_RESERVED (open)
-	 *     01b -> TYPEC_RP_USB
-	 *     10b -> TYPEC_RP_1A5
-	 *     11b -> TYPEC_RP_3A0
-	 *
-	 *   CCx = ANAMODE + 1, if CCx is enabled
-	 *   Rp  = (ANASUBMODE - 1) & 0x3
-	 */
-	cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 :
-		TYPEC_CC_OPEN;
-	cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 :
-		TYPEC_CC_OPEN;
-	role_control = cc1 | (cc2 << 2);
-	/* Circular shift anasubmode to convert to Rp range */
-	role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4);
-
-	return role_control;
-}
-
-static uint32_t ucpd_get_cc_enable_mask(int port)
-{
-	uint32_t mask = STM32_UCPD_CR_CCENABLE_MASK;
-
-	if (ucpd_vconn_enable) {
-		uint32_t cr = STM32_UCPD_CR(port);
-		int pol = !!(cr & STM32_UCPD_CR_PHYCCSEL);
-
-		mask &= ~(1 << (STM32_UCPD_CR_CCENABLE_SHIFT + !pol));
-	}
-
-	return mask;
-}
-
-int stm32gx_ucpd_vconn_disc_rp(int port, int enable)
-{
-	int cr;
-
-	/* Update VCONN on/off status. Do this before getting cc enable mask */
-	ucpd_vconn_enable = enable;
-
-	cr = STM32_UCPD_CR(port);
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	cr |= ucpd_get_cc_enable_mask(port);
-
-	/* Apply cc pull resistor change */
-	STM32_UCPD_CR(port) = cr;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
-{
-	uint32_t cr = STM32_UCPD_CR(port);
-
-	/*
-	 * Always set ANASUBMODE to match desired Rp. TCPM layer has a valid
-	 * range of 0, 1, or 2. This range maps to 1, 2, or 3 in ucpd for
-	 * ANASUBMODE.
-	 */
-	cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
-	cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
-
-	/* Disconnect both pull from both CC lines for R_open case */
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	/* Set ANAMODE if cc_pull is Rd */
-	if (cc_pull == TYPEC_CC_RD) {
-		cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
-	/* Clear ANAMODE if cc_pull is Rp */
-	} else if (cc_pull == TYPEC_CC_RP) {
-		cr &= ~(STM32_UCPD_CR_ANAMODE);
-		cr |= ucpd_get_cc_enable_mask(port);
-	}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	if (ucpd_cc_change_log) {
-		CPRINTS("ucpd: set_cc: pull = %d, rp = %d", cc_pull, rp);
-	}
-#endif
-	/* Update pull values */
-	STM32_UCPD_CR(port) = cr;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) {
-	/*
-	 * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This
-	 * function is called when polarity is updated at TCPM layer. STM32Gx
-	 * only supports POLARITY_CC1 or POLARITY_CC2 and this is stored in the
-	 * PHYCCSEL bit in the CR register.
-	 */
-	if (polarity > POLARITY_CC2)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (polarity == POLARITY_CC1)
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYCCSEL;
-	else if (polarity == POLARITY_CC2)
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYCCSEL;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	ucpd_cc_set_save = STM32_UCPD_CR(port);
-#endif
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_rx_enable(int port, int enable)
-{
-	/*
-	 * USB PD receiver enable is controlled by the bit PHYRXEN in
-	 * UCPD_CR. Enable Rx interrupts when RX PD decoder is active.
-	 */
-	if (enable) {
-		STM32_UCPD_ICR(port) = UCPD_IMR_RX_INT_MASK;
-		STM32_UCPD_IMR(port) |= UCPD_IMR_RX_INT_MASK;
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYRXEN;
-	} else {
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYRXEN;
-		STM32_UCPD_IMR(port) &= ~UCPD_IMR_RX_INT_MASK;
-	}
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role)
-{
-	msg_header.pr = power_role;
-	msg_header.dr = data_role;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_sop_prime_enable(int port, bool enable)
-{
-	/* Update static varialbe used to filter SOP//SOP'' messages */
-	ucpd_rx_sop_prime_enabled = enable;
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	chip_info->vendor_id = USB_VID_STM32;
-	chip_info->product_id = 0;
-	chip_info->device_id = STM32_DBGMCU_IDCODE & 0xfff;
-	chip_info->fw_version_number = 0xEC;
-
-	return EC_SUCCESS;
-}
-
-static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
-{
-	enum tcpci_msg_type type;
-
-	/* Select the correct tx desciptor */
-	ucpd_tx_active_buffer = &ucpd_tx_buffers[msg_type];
-	type = ucpd_tx_active_buffer->type;
-
-	if (type == TCPCI_MSG_TX_HARD_RESET) {
-				/*
-		 * From RM0440 45.4.4:
-		 * In order to facilitate generation of a Hard Reset, a special
-		 * code of TXMODE field is used. No other fields need to be
-		 * written. On writing the correct code, the hardware forces
-		 * Hard Reset Tx under the correct (optimal) timings with
-		 * respect to an on-going Tx message, which (if still in
-		 * progress) is cleanly terminated by truncating the current
-		 * sequence and directly appending an EOP K-code sequence. No
-		 * specific interrupt is generated relating to this truncation
-		 * event.
-		 *
-		 * Because Hard Reset can interrupt ongoing Tx operations, it is
-		 * started differently than all other tx messages. Only need to
-		 * enable hard reset interrupts, and then set a bit in the CR
-		 * register to initiate.
-		 */
-		/* Enable interrupt for Hard Reset sent/discarded */
-		STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF |
-			STM32_UCPD_ICR_HRSTSENTCF;
-		STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE |
-			STM32_UCPD_IMR_HRSTSENTIE;
-		/* Initiate Hard Reset */
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST;
-	} else if (type != TCPCI_MSG_INVALID) {
-		int msg_len = 0;
-		int mode;
-
-		/*
-		 * These types are normal transmission, TXMODE = 0. To transmit
-		 * regular message, control or data, requires the following:
-		 *     1. Set TXMODE:
-		 *          Normal -> 0
-		 *          Cable Reset -> 1
-		 *          Bist -> 2
-		 *     2. Set TX_ORDSETR based on message type
-		 *     3. Set TX_PAYSZR which must account for 2 bytes of header
-		 *     4. Configure DMA (optional if DMA is desired)
-		 *     5. Enable transmit interrupts
-		 *     6. Start TX by setting TXSEND in CR
-		 *
-		 */
-
-		/*
-		 * Set tx length parameter (in bytes). Note the count field in
-		 * the header is number of 32 bit objects. Also, the length
-		 * field must account for the 2 header bytes.
-		 */
-		if (type == TCPCI_MSG_TX_BIST_MODE_2) {
-			mode = STM32_UCPD_CR_TXMODE_BIST;
-		} else if (type == TCPCI_MSG_CABLE_RESET) {
-			mode = STM32_UCPD_CR_TXMODE_CBL_RST;
-		} else {
-			mode = STM32_UCPD_CR_TXMODE_DEF;
-			msg_len = ucpd_tx_active_buffer->msg_len;
-		}
-
-		STM32_UCPD_TX_PAYSZR(port) = msg_len;
-
-		/* Set tx mode */
-		STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_TXMODE_MASK;
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXMODE_VAL(mode);
-
-		/* Index into ordset enum for start of packet */
-		if (type <= TCPCI_MSG_CABLE_RESET)
-			STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type];
-		else
-			STM32_UCPD_TX_ORDSETR(port) =
-				ucpd_txorderset[TX_ORDERSET_SOP];
-
-		/* Reset msg byte index */
-		ucpd_tx_active_buffer-> msg_index = 0;
-
-		/* Enable interrupts */
-		ucpd_tx_interrupts_enable(port, 1);
-
-		/* Trigger ucpd peripheral to start pd message transmit */
-		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXSEND;
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-		ucpd_log_add_msg(ucpd_tx_active_buffer->data.header, 0);
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-static void ucpd_set_tx_state(enum ucpd_state state)
-{
-	ucpd_tx_state = state;
-}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-static void ucpd_task_log(int timeout, enum ucpd_state enter,
-			  enum ucpd_state exit, int req, uint32_t evt)
-{
-	static int same_count = 0;
-	int idx = ucpd_tx_state_log_idx;
-
-	if (ucpd_tx_state_log_freeze)
-		return;
-
-	ucpd_tx_statelog[idx].ts = get_time().le.lo;
-	ucpd_tx_statelog[idx].tx_request = req;
-	ucpd_tx_statelog[idx].timeout_us = timeout;
-	ucpd_tx_statelog[idx].enter_state = enter;
-	ucpd_tx_statelog[idx].exit_state = exit;
-	ucpd_tx_statelog[idx].evt = evt;
-
-	ucpd_tx_state_log_idx = (idx + 1) & TX_STATE_LOG_MASK;
-
-	if (enter == exit) {
-		same_count++;
-	} else {
-		same_count = 0;
-	}
-
-	/*
-	 * Should not have same enter/exit states. If this happens, then freeze
-	 * state log to help in debugging.
-	 */
-	if (same_count > 5)
-		ucpd_tx_state_log_freeze = 1;
-}
-
-static void ucpd_task_log_dump(void)
-{
-	int n;
-	int idx;
-
-	ucpd_tx_state_log_freeze = 1;
-
-	/* current index will be oldest entry in the log */
-	idx = ucpd_tx_state_log_idx;
-
-	ccprintf("\n\t UCDP Task Log\n");
-	for (n = 0; n < TX_STATE_LOG_LEN; n++) {
-		ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n",
-			 n,
-			 ucpd_names[ucpd_tx_statelog[idx].enter_state],
-			 ucpd_names[ucpd_tx_statelog[idx].exit_state],
-			 ucpd_tx_statelog[idx].tx_request,
-			 ucpd_tx_statelog[idx].evt,
-			 ucpd_tx_statelog[idx].ts,
-			 ucpd_tx_statelog[idx].timeout_us);
-
-		idx = (idx + 1) & TX_STATE_LOG_MASK;
-		msleep(5);
-	}
-
-	ucpd_tx_state_log_freeze = 0;
-}
-#endif
-
-static void ucpd_manage_tx(int port, int evt)
-{
-	enum ucpd_tx_msg msg_src = TX_MSG_NONE;
-	uint16_t hdr;
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	enum ucpd_state enter = ucpd_tx_state;
-	int req = ucpd_tx_request;
-#endif
-
-	if (evt & UCPD_EVT_HR_REQ) {
-		/*
-		 * Hard reset control messages are treated as a priority. The
-		 * control message will already be set up as it comes from the
-		 * PRL layer like any other PD ctrl/data message. So just need
-		 * to indicate the correct message source and set the state to
-		 * hard reset here.
-		 */
-		ucpd_set_tx_state(STATE_HARD_RESET);
-		msg_src = TX_MSG_TCPM;
-		ucpd_tx_request &= ~(1 << msg_src);
-	}
-
-	switch (ucpd_tx_state) {
-	case STATE_IDLE:
-		if (ucpd_tx_request & MSG_GOOD_CRC_MASK) {
-			ucpd_set_tx_state(STATE_ACTIVE_CRC);
-			msg_src = TX_MSG_GOOD_CRC;
-		} else if (ucpd_tx_request & MSG_TCPM_MASK) {
-			if (evt & UCPD_EVT_RX_MSG) {
-				/*
-				 * USB-PD Specification rev 3.0, section 6.10
-				 * On receiving a received message, the protocol
-				 * layer shall discard any pending message.
-				 *
-				 * Since the pending message from the PRL has
-				 * not been sent yet, it needs to be discarded
-				 * based on the received message event.
-				 */
-				pd_transmit_complete(port,
-						     TCPC_TX_COMPLETE_DISCARDED);
-				ucpd_tx_request &= ~MSG_TCPM_MASK;
-			} else if (!ucpd_rx_msg_active) {
-				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
-				msg_src = TX_MSG_TCPM;
-				/* Save msgID required for GoodCRC check */
-				hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header;
-				msg_id_match = PD_HEADER_ID(hdr);
-				tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ?
-					UCPD_N_RETRY_COUNT_REV30 :
-					UCPD_N_RETRY_COUNT_REV20;
-			}
-		}
-
-		/* If state is not idle, then start tx message */
-		if (ucpd_tx_state != STATE_IDLE) {
-			ucpd_tx_request &= ~(1 << msg_src);
-			tx_retry_count = 0;
-		}
-		break;
-
-	case STATE_ACTIVE_TCPM:
-		/*
-		 * Check if tx msg has finsihed. For TCPM messages
-		 * transmit is not complete until a GoodCRC message
-		 * matching the msgID just sent is received. But, a tx
-		 * message can fail due to collision or underrun,
-		 * etc. If that failure occurs, dont' wait for GoodCrc
-		 * and just go to failure path.
-		 */
-		if (evt & UCPD_EVT_TX_MSG_SUCCESS) {
-			ucpd_set_tx_state(STATE_WAIT_CRC_ACK);
-			ucpd_timeout_us = UCPD_T_RECEIVE_US;
-		} else if (evt & UCPD_EVT_TX_MSG_DISC ||
-			   evt & UCPD_EVT_TX_MSG_FAIL) {
-			if (tx_retry_count < tx_retry_max) {
-				if (evt & UCPD_EVT_RX_MSG) {
-					/*
-					 * A message was received so there is no
-					 * need to retry this tx message which
-					 * had failed to send previously.
-					 * Likely, due to the wire
-					 * being active from the message that
-					 * was just received.
-					 */
-					ucpd_set_tx_state(STATE_IDLE);
-					pd_transmit_complete(port,
-							     TCPC_TX_COMPLETE_DISCARDED);
-					ucpd_set_tx_state(STATE_IDLE);
-				} else {
-					/*
-					 * Tx attempt failed. Remain in this
-					 * state, but trigger new tx attempt.
-					 */
-					msg_src = TX_MSG_TCPM;
-					tx_retry_count++;
-				}
-			} else {
-				enum tcpc_transmit_complete status;
-
-				status = (evt & UCPD_EVT_TX_MSG_FAIL) ?
-					TCPC_TX_COMPLETE_FAILED :
-					TCPC_TX_COMPLETE_DISCARDED;
-				ucpd_set_tx_state(STATE_IDLE);
-				pd_transmit_complete(port, status);
-			}
-		}
-		break;
-
-	case STATE_ACTIVE_CRC:
-		if (evt & (UCPD_EVT_TX_MSG_SUCCESS | UCPD_EVT_TX_MSG_FAIL |
-			   UCPD_EVT_TX_MSG_DISC)) {
-			ucpd_set_tx_state(STATE_IDLE);
-			if (evt & UCPD_EVT_TX_MSG_FAIL)
-				CPRINTS("ucpd: Failed to send GoodCRC!");
-			else if (evt & UCPD_EVT_TX_MSG_DISC)
-				CPRINTS("ucpd: GoodCRC message discarded!");
-		}
-		break;
-
-	case STATE_WAIT_CRC_ACK:
-		if (evt & UCPD_EVT_RX_GOOD_CRC &&
-		    ucpd_crc_id == msg_id_match) {
-			/* GoodCRC with matching ID was received */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_SUCCESS);
-			ucpd_set_tx_state(STATE_IDLE);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_crc();
-#endif
-		} else if ((evt & UCPD_EVT_RX_GOOD_CRC) ||
-			   (evt & TASK_EVENT_TIMER)) {
-			/* GoodCRC w/out match or timeout waiting */
-			if (tx_retry_count < tx_retry_max) {
-				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
-				msg_src = TX_MSG_TCPM;
-				tx_retry_count++;
-			} else {
-				ucpd_set_tx_state(STATE_IDLE);
-				pd_transmit_complete(port,
-						     TCPC_TX_COMPLETE_FAILED);
-			}
-		} else if (evt & UCPD_EVT_RX_MSG) {
-			/*
-			 * In the case of a collsion, it's possible the port
-			 * partner may not send a GoodCRC and instead send the
-			 * message that was colliding. If a message is received
-			 * in this state, then treat it as a discard from an
-			 * incoming message.
-			 */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_DISCARDED);
-			ucpd_set_tx_state(STATE_IDLE);
-		}
-		break;
-
-	case STATE_HARD_RESET:
-		if (evt & UCPD_EVT_HR_DONE) {
-			/* HR complete, reset tx state values */
-			ucpd_set_tx_state(STATE_IDLE);
-			ucpd_tx_request = 0;
-			tx_retry_count = 0;
-		} else if (evt & UCPD_EVT_HR_FAIL) {
-			ucpd_set_tx_state(STATE_IDLE);
-			ucpd_tx_request = 0;
-			tx_retry_count = 0;
-		}
-		break;
-	}
-
-	/* If msg_src is valid, then start transmit */
-	if (msg_src > TX_MSG_NONE) {
-		stm32gx_ucpd_start_transmit(port, msg_src);
-	}
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-	ucpd_task_log(ucpd_timeout_us, enter, ucpd_tx_state, req, evt);
-#endif
-}
-
-/*
- * Main task entry point for UCPD task
- *
- * @param p The PD port number for which to handle interrupts (pointer is
- * reinterpreted as an integer directly).
- */
-void ucpd_task(void *p)
-{
-	const int port = (int) ((intptr_t) p);
-
-	/* Init variables used to manage tx process */
-	stm32gx_ucpd_state_init(port);
-
-	while (1) {
-		/*
-		 * Note that ucpd_timeout_us is file scope and may be modified
-		 * in the tx state machine when entering the STATE_WAIT_CRC_ACK
-		 * state. Otherwise, the expectation is that the task is woken
-		 * only upon non-timer events.
-		 */
-		int evt = task_wait_event(ucpd_timeout_us);
-
-		/*
-		 * USB-PD messages are intiated in TCPM stack (PRL
-		 * layer). However, GoodCRC messages are initiated within the
-		 * UCPD driver based on USB-PD rx messages. These 2 types of
-		 * transmit paths are managed via task events.
-		 *
-		 * UCPD generated GoodCRC messages, are the priority path as
-		 * they must be sent immediately following a successful USB-PD
-		 * rx message. As long as a transmit operation is not underway,
-		 * then a transmit message will be started upon request. The ISR
-		 * routine sets the event to indicate that the transmit
-		 * operation is complete.
-		 *
-		 * Hard reset requests are sent as a TCPM message, but in terms
-		 * of the ucpd transmitter, they are treated as a 3rd tx msg
-		 * source since they can interrupt an ongoing tx msg, and there
-		 * is no requirement to wait for a GoodCRC reply message.
-		 */
-
-		/* Assume there is no timer for next task wake */
-		ucpd_timeout_us = -1;
-
-		if (evt & UCPD_EVT_GOOD_CRC_REQ)
-			ucpd_tx_request |= MSG_GOOD_CRC_MASK;
-
-		if (evt & UCPD_EVT_TCPM_MSG_REQ)
-			ucpd_tx_request |= MSG_TCPM_MASK;
-
-		/*
-		 * Manage PD tx messages. The state machine may need to be
-		 * called more than once when the task wakes. For instance, if
-		 * the task is woken at the completion of sending a GoodCRC,
-		 * there may be a TCPM message request pending and just changing
-		 * the state back to idle would not trigger start of transmit.
-		 */
-		do {
-			ucpd_manage_tx(port, evt);
-			/* Look at task events only once. */
-			evt = 0;
-		} while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE
-			 && !ucpd_rx_msg_active);
-	}
-}
-
-static void ucpd_send_good_crc(int port, uint16_t rx_header)
-{
-	int msg_id;
-	int rev_id;
-	uint16_t tx_header;
-	enum tcpci_msg_type tx_type;
-	enum pd_power_role pr = 0;
-	enum pd_data_role dr = 0;
-
-	/*
-	 * A GoodCRC message shall be sent by receiver to ack that the previous
-	 * message was correctly received. The GoodCRC message shall return the
-	 * rx message's msg_id field. The one exception is for GoodCRC messages,
-	 * which do not generate a GoodCRC response
-	 */
-	if (ucpd_msg_is_good_crc(rx_header)) {
-		return;
-	}
-
-	/*
-	 * Get the rx ordered set code just detected. SOP -> SOP''_Debug are in
-	 * the same order as enum tcpci_msg_type and so can be used
-	 * directly.
-	 */
-	tx_type = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
-
-	/*
-	 * PD Header(SOP):
-	 *   Extended   b15    -> set to 0 for control messages
-	 *   Count      b14:12 -> number of 32 bit data objects = 0 for ctrl msg
-	 *   MsgID      b11:9  -> running byte counter (extracted from rx msg)
-	 *   Power Role b8     -> stored in static, from set_msg_header()
-	 *   Spec Rev   b7:b6  -> PD spec revision (extracted from rx msg)
-	 *   Data Role  b5     -> stored in static, from set_msg_header
-	 *   Msg Type   b4:b0  -> data or ctrl type = PD_CTRL_GOOD_CRC
-	 */
-	/* construct header message */
-	msg_id = PD_HEADER_ID(rx_header);
-	rev_id = PD_HEADER_REV(rx_header);
-	if (tx_type == TCPCI_MSG_SOP) {
-		pr = msg_header.pr;
-		dr = msg_header.dr;
-	}
-	tx_header = PD_HEADER(PD_CTRL_GOOD_CRC, pr, dr, msg_id, 0, rev_id, 0);
-
-	/* Good CRC is header with no other objects */
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].msg_len = 2;
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].data.header = tx_header;
-	ucpd_tx_buffers[TX_MSG_GOOD_CRC].type = tx_type;
-
-	/* Notify ucpd task that a GoodCRC message tx request is pending */
-	task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ);
-}
-
-int stm32gx_ucpd_transmit(int port,
-			  enum tcpci_msg_type type,
-			  uint16_t header,
-			  const uint32_t *data)
-{
-	/* Length in bytes = (4 * object len) + 2 header byes */
-	int len = (PD_HEADER_CNT(header) << 2) + 2;
-
-	if (len > UCPD_BUF_LEN)
-		return EC_ERROR_OVERFLOW;
-
-	/* Store tx msg info in TCPM msg descriptor */
-	ucpd_tx_buffers[TX_MSG_TCPM].msg_len = len;
-	ucpd_tx_buffers[TX_MSG_TCPM].type = type;
-	ucpd_tx_buffers[TX_MSG_TCPM].data.header = header;
-	/* Copy msg objects to ucpd data buffer, after 2 header bytes */
-	memcpy(ucpd_tx_buffers[TX_MSG_TCPM].data.msg + 2, (uint8_t *)data,
-	       len - 2);
-
-	/*
-	 * Check for hard reset message here. A different event is used for hard
-	 * resets as they are able to interrupt ongoing transmit, and should
-	 * have priority over any pending message.
-	 */
-	if (type == TCPCI_MSG_TX_HARD_RESET)
-		task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_REQ);
-	else
-		task_set_event(TASK_ID_UCPD, UCPD_EVT_TCPM_MSG_REQ);
-
-	return EC_SUCCESS;
-}
-
-int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
-	int rxpaysz;
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	int sop;
-#endif
-
-	/* First 2 bytes of data buffer are the header */
-	*head = *rx_header;
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-/*
- * The message header is a 16-bit value that's stored in a 32-bit data type.
- * SOP* is encoded in bits 31 to 28 of the 32-bit data type.
- * NOTE: The 4 byte header is not part of the PD spec.
- */
-	/* Get SOP value */
-	sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
-	/* Put SOP in bits 31:28 of 32 bit header */
-	*head |= PD_HEADER_SOP(sop);
-#endif
-	rxpaysz = STM32_UCPD_RX_PAYSZR(port) & STM32_UCPD_RX_PAYSZR_MASK;
-	/* This size includes 2 bytes for message header */
-	rxpaysz -= 2;
-	/* Copy payload (src/dst are both 32 bit aligned) */
-	memcpy(payload, ucpd_rx_buffer + 2, rxpaysz);
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
-						   const bool enable)
-{
-	ucpd_rx_bist_mode = enable;
-	CPRINTS("ucpd: Bist test mode = %d", enable);
-
-	return EC_SUCCESS;
-}
-
-void stm32gx_ucpd1_irq(void)
-{
-	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
-	int port = 0;
-	uint32_t sr = STM32_UCPD_SR(port);
-	uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT
-		| STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT |
-		STM32_UCPD_SR_HRSTDISC;
-
-	/* Check for CC events, set event to wake PD task */
-	if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) {
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-		ucpd_sr_cc_event = sr;
-		hook_call_deferred(&ucpd_cc_change_notify_data, 0);
-#endif
-	}
-
-	/*
-	 * Check for Tx events. tx_mask includes all status bits related to the
-	 * end of a USB-PD tx message. If any of these bits are set, the
-	 * transmit attempt is completed. Set an event to notify ucpd tx state
-	 * machine that transmit operation is complete.
-	 */
-	if (sr & tx_done_mask) {
-		/* Check for tx message complete */
-		if (sr & STM32_UCPD_SR_TXMSGSENT) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_SUCCESS);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_tx_comp();
-#endif
-		} else if (sr & (STM32_UCPD_SR_TXMSGABT |
-				 STM32_UCPD_SR_TXUND)) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL);
-		} else if (sr & STM32_UCPD_SR_TXMSGDISC) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC);
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_mark_tx_comp();
-#endif
-		} else if (sr & STM32_UCPD_SR_HRSTSENT) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_DONE);
-		} else if (sr & STM32_UCPD_SR_HRSTDISC) {
-			task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_FAIL);
-		}
-		/* Disable Tx interrupts */
-		ucpd_tx_interrupts_enable(port, 0);
-	}
-
-	/* Check for data register empty */
-	if (sr & STM32_UCPD_SR_TXIS)
-		ucpd_tx_data_byte(port);
-
-	/* Check for Rx Events */
-	/* Check first for start of new message */
-	if (sr & STM32_UCPD_SR_RXORDDET) {
-		ucpd_rx_byte_count = 0;
-		ucpd_rx_msg_active = 1;
-	}
-	/* Check for byte received */
-	if (sr & STM32_UCPD_SR_RXNE)
-		ucpd_rx_data_byte(port);
-
-	/* Check for end of message */
-	if (sr & STM32_UCPD_SR_RXMSGEND) {
-		ucpd_rx_msg_active = 0;
-		/* Check for errors */
-		if (!(sr & STM32_UCPD_SR_RXERR)) {
-			uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
-			enum tcpci_msg_type type;
-			int good_crc = 0;
-
-			type = STM32_UCPD_RX_ORDSETR(port) &
-				STM32_UCPD_RXORDSETR_MASK;
-
-			good_crc = ucpd_msg_is_good_crc(*rx_header);
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-			ucpd_log_add_msg(*rx_header, 1);
-#endif
-			/*
-			 * Don't pass GoodCRC control messages to the TCPM
-			 * layer. In addition, need to filter for SOP'/SOP''
-			 * packets if those are not enabled. SOP'/SOP''
-			 * reception is controlled by a static variable. The
-			 * hardware orderset detection pattern can't be changed
-			 * without disabling the ucpd peripheral.
-			 */
-			if (!good_crc && (ucpd_rx_sop_prime_enabled ||
-					  type == TCPCI_MSG_SOP)) {
-
-				/*
-				 * If BIST test mode is active, then still need
-				 * to send GoodCRC reply, but there is no need
-				 * to send the message up to the tcpm layer.
-				 */
-				if(!ucpd_rx_bist_mode) {
-					if (tcpm_enqueue_message(port))
-						hook_call_deferred(&ucpd_rx_enque_error_data,
-							   0);
-				}
-
-				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_MSG);
-
-				/* Send GoodCRC message (if required) */
-				ucpd_send_good_crc(port, *rx_header);
-			} else if (good_crc) {
-				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_GOOD_CRC);
-				ucpd_crc_id = PD_HEADER_ID(*rx_header);
-			}
-		} else {
-			/* Rx message is complete, but there were bit errors */
-			CPRINTS("ucpd: rx message error");
-		}
-	}
-	/* Check for fault conditions */
-	if (sr & STM32_UCPD_SR_RXHRSTDET) {
-		/* hard reset received */
-		pd_execute_hard_reset(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-		hook_call_deferred(&ucpd_hard_reset_rx_log_data, 0);
-	}
-
-	/* Clear interrupts now that PD events have been set */
-	STM32_UCPD_ICR(port) = sr;
-}
-DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1);
-
-#ifdef CONFIG_STM32G4_UCPD_DEBUG
-static char ctrl_names[][12] = {
-	"rsvd",
-	"GoodCRC",
-	"Goto Min",
-	"Accept",
-	"Reject",
-	"Ping",
-	"PS_Rdy",
-	"Get_SRC",
-	"Get_SNK",
-	"DR_Swap",
-	"PR_Swap",
-	"VCONN_Swp",
-	"Wait",
-	"Soft_Rst",
-	"RSVD",
-	"RSVD",
-	"Not_Sup",
-	"Get_SRC_Ext",
-	"Get_Status",
-};
-
-static char data_names[][10] = {
-	"RSVD",
-	"SRC_CAP",
-	"REQUEST",
-	"BIST",
-	"SINK_CAP",
-	"BATTERY",
-        "ALERT",
-	"GET_INFO",
-	"ENTER_USB",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"VDM",
-};
-
-static void ucpd_dump_msg_log(void)
-{
-	int i;
-	int type;
-	int len;
-	int dir;
-	uint16_t header;
-	char *name;
-
-
-	ccprintf("ucpd: msg_total = %d\n", msg_log_cnt);
-	ccprintf("Idx\t  Delta(us)\tDir\t   Type\t\tLen\t s1  s2   PR\t DR\n");
-	ccprintf("-----------------------------------------------------------"
-		 "-----------------\n");
-
-	for (i = 0; i < msg_log_idx; i++) {
-		uint32_t delta_ts = 0;
-		int j;
-
-		header = msg_log[i].header;
-
-		if (header != 0xabcd) {
-			type = PD_HEADER_TYPE(header);
-			len = PD_HEADER_CNT(header);
-			name = len ? data_names[type] : ctrl_names[type];
-			dir = msg_log[i].dir;
-			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
-			}
-
-			ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d  %d\t"
-				 "%s\t %s",
-				 i,
-				 delta_ts,
-				 dir ? "Rx" : "Tx",
-				 name,
-				 len,
-				 msg_log[i].comp,
-				 msg_log[i].crc,
-				 PD_HEADER_PROLE(header) ? "SRC" : "SNK",
-				 PD_HEADER_DROLE(header) ? "DFP" : "UFP");
-			len = MIN((len * 4) + 2, MSG_BUF_LEN);
-			for (j = 0; j < len; j++)
-				ccprintf(" %02x", msg_log[i].buf[j]);
-		} else {
-			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
-			}
-			ccprintf("msg[%02d]: %08d\t CC Voltage Change!",
-				 i, delta_ts);
-		}
-		ccprintf("\n");
-		msleep(5);
-	}
-}
-
-static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp)
-{
-	int cc_enable;
-	uint32_t cr = STM32_UCPD_CR(port);
-
-	/*
-	 * Only update ANASUBMODE if specified pull type is Rp.
-	 */
-	if (pull == TYPEC_CC_RP) {
-		cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK;
-		cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp));
-	}
-
-	/*
-	 * Can't independently set pull value for CC1 from CC2. But, can
-	 * independently connect or disconnect pull for CC1 and CC2. Enable here
-	 * the CC lines specified by cc_mask. If desired pull is TYPEC_CC_OPEN,
-	 * then the CC lines specified in cc_mask will be disabled.
-	 */
-	/* Get existing cc enable value */
-	cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >>
-		STM32_UCPD_CR_CCENABLE_SHIFT;
-	/* Apply cc_mask (enable CC line specified) */
-	cc_enable |= cc_mask;
-
-	/* Set ANAMODE if cc_pull is Rd */
-	if (pull == TYPEC_CC_RD)
-		cr |= STM32_UCPD_CR_ANAMODE;
-	/* Clear ANAMODE if cc_pull is Rp */
-	else if (pull == TYPEC_CC_RP)
-		cr &= ~(STM32_UCPD_CR_ANAMODE);
-	else if (pull == TYPEC_CC_OPEN)
-		cc_enable &= ~cc_mask;
-
-	/* The value for this field needs to be OR'd in */
-	cr &= ~STM32_UCPD_CR_CCENABLE_MASK;
-	cr |= STM32_UCPD_CR_CCENABLE_VAL(cc_enable);
-	/* Update pull values */
-	STM32_UCPD_CR(port) = cr;
-	/* Display updated settings */
-	ucpd_cc_status(port);
-}
-
-void ucpd_info(int port)
-{
-	ucpd_cc_status(port);
-	ccprintf("\trx_en\t = %d\n\tpol\t = %d\n",
-		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYRXEN),
-		 !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYCCSEL));
-
-	/* Dump ucpd task state info */
-	ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n",
-		ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us);
-
-	ucpd_task_log_dump();
-}
-
-static int command_ucpd(int argc, char **argv)
-{
-	uint32_t tx_data = 0;
-	char *e;
-	int val;
-	int port = 0;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "rst")) {
-		/* Force reset of ucpd peripheral */
-		stm32gx_ucpd_init(port);
-		pd_execute_hard_reset(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-	} else if (!strcasecmp(argv[1], "info")) {
-		ucpd_info(port);
-	} else if (!strcasecmp(argv[1], "bist")) {
-		/* Need to initiate via DPM to have a timer */
-		/* TODO(b/182861002): uncomment when Gingerbread has
-		 * full PD support landed.
-		 * pd_dpm_request(port, DPM_REQUEST_BIST_TX);
-		 */
-	} else if (!strcasecmp(argv[1], "hard")) {
-		stm32gx_ucpd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0,
-				      &tx_data);
-	} else if (!strcasecmp(argv[1], "pol")) {
-		if (argc < 3)
-			return EC_ERROR_PARAM_COUNT;
-		val = strtoi(argv[2], &e, 10);
-		if (val > 1)
-			val = 0;
-		stm32gx_ucpd_set_polarity(port, val);
-		stm32gx_ucpd_set_rx_enable(port, 1);
-		ccprintf("ucpd: set pol = %d, PHYRXEN = 1\n", val);
-	} else if (!strcasecmp(argv[1], "cc")) {
-		int cc_mask;
-		int pull;
-		int rp = 0; /* needs to be initialized */
-
-		if (argc < 3) {
-			ucpd_cc_status(port);
-			return EC_SUCCESS;
-		}
-		cc_mask = strtoi(argv[2], &e, 10);
-		if (cc_mask < 1 || cc_mask > 3)
-			return EC_ERROR_PARAM2;
-		/* cc_mask has determines which cc setting to apply */
-		if (!strcasecmp(argv[3], "rd")) {
-			pull = TYPEC_CC_RD;
-		} else if (!strcasecmp(argv[3], "rp")) {
-			pull = TYPEC_CC_RP;
-			rp = strtoi(argv[4], &e, 10);
-			if (rp < 0 || rp > 2)
-				return EC_ERROR_PARAM4;
-		} else if (!strcasecmp(argv[3], "open")) {
-			pull = TYPEC_CC_OPEN;
-		} else {
-			return EC_ERROR_PARAM3;
-		}
-		stm32gx_ucpd_set_cc_debug(port, cc_mask, pull, rp);
-
-	} else if (!strcasecmp(argv[1], "log")) {
-		if (argc < 3) {
-			ucpd_dump_msg_log();
-		} else if (!strcasecmp(argv[2], "clr")) {
-			msg_log_cnt = 0;
-			msg_log_idx = 0;
-		}
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ucpd, command_ucpd,
-			"[rst|info|bist|hard|pol <0|1>|cc xx <rd|rp|open>|log",
-			"ucpd peripheral debug and control options");
-#endif
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
deleted file mode 100644
index d3af41e5bc..0000000000
--- a/chip/stm32/ucpd-stm32gx.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_UCPD_STM32GX_H
-#define __CROS_EC_UCPD_STM32GX_H
-
-/* STM32 UCPD driver for Chrome EC */
-
-#include "usb_pd_tcpm.h"
-
-/*
- * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
- * a prescaler who's output feeds the 'half-bit' divider which is used
- * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
- * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
- * range is 9 <--> 18 MHz.
- *
- *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
- * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
- *          -------          ---------    |           -------------
- *                                        |           -------------
- *                                        |---------->| ifrgap_cnt|
- *                                                    -------------
- * Requirements:
- *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
- *   2. tTransitionWindow - 12 to 20 uSec
- *   3. tInterframGap - uSec
- *
- * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
- * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
- * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
- */
-
-#define UCPD_PSC_DIV 1
-#define UCPD_HBIT_DIV 27
-#define UCPD_TRANSWIN_CNT 8
-#define UCPD_IFRGAP_CNT 17
-
-
-/*
- * K-codes and ordered set defines. These codes and sets are used to encode
- * which type of USB-PD message is being sent. This information can be found in
- * the USB-PD spec section 5.4 - 5.6. This info is also included in the STM32G4
- * TRM (RM0440) 45.4.3
- */
-#define UCPD_SYNC1 0x18u
-#define UCPD_SYNC2 0x11u
-#define UCPD_SYNC3 0x06u
-#define UCPD_RST1  0x07u
-#define UCPD_RST2  0x19u
-#define UCPD_EOP   0x0Du
-
-/* This order of this enum matches tcpm_sop_type */
-enum ucpd_tx_ordset {
-	TX_ORDERSET_SOP =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_SOP_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC3<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC3<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_RST2<<10u) |
-					(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_SYNC3<<10u) |
-					(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_HARD_RESET =	(UCPD_RST1  |
-					(UCPD_RST1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_RST2<<15u)),
-
-	TX_ORDERSET_CABLE_RESET =	(UCPD_RST1 |
-					(UCPD_SYNC1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_SYNC3<<15u)),
-};
-
-
-/**
- * STM32Gx UCPD implementation of tcpci .init method
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_init(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .release method
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_release(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .get_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param *cc1 -> pointer to cc1 result
- * @param *cc2 -> pointer to cc2 result
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_cc(int usbc_port, enum tcpc_cc_voltage_status *cc1,
-			enum tcpc_cc_voltage_status *cc2);
-
-/**
- * STM32Gx equivalent for TCPCI role_control register
- *
- * @param usbc_port -> USB-C Port number
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_role_control(int usbc_port);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param cc_pull -> Rp or Rd selection
- * @param rp -> value of Rp (if cc_pull == Rp)
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_cc(int usbc_port, int cc_pull, int rp);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_cc method
- *
- * @param usbc_port -> USB-C Port number
- * @param polarity -> CC1 or CC2 selection
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_polarity(int usbc_port, enum tcpc_cc_polarity polarity);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_rx_enable method
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> on/off for USB-PD messages
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_rx_enable(int port, int enable);
-
-/**
- * STM32Gx UCPD implementation of tcpci .set_msg_header method
- *
- * @param usbc_port -> USB-C Port number
- * @param power_role -> port's current power role
- * @param data_role -> port's current data role
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role);
-
-/**
- * STM32Gx UCPD implementation of tcpci .transmit method
- *
- * @param usbc_port -> USB-C Port number
- * @param type -> SOP/SOP'/SOP'' etc
- * @param header -> usb pd message header
- * @param *data -> pointer to message contents
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			  const uint32_t *data);
-
-/**
- * STM32Gx UCPD implementation of tcpci .get_message_raw method
- *
- * @param usbc_port -> USB-C Port number
- * @param *payload -> pointer to where message should be written
- * @param *head -> pointer to message header
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head);
-
-/**
- * STM32Gx method to remove Rp when VCONN is being supplied
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> connect/disc Rp
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_vconn_disc_rp(int port, int enable);
-
-/**
- * STM32Gx UCPD implementation of tcpci .sop_prime_enable method
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> control of SOP'/SOP'' messages
- * @return EC_SUCCESS
- */
-int stm32gx_ucpd_sop_prime_enable(int port, bool enable);
-
-int stm32gx_ucpd_get_chip_info(int port, int live,
-			       struct ec_response_pd_chip_info_v1 *chip_info);
-
-/**
- * This function is used to enable/disable a ucpd debug feature that is used to
- * mark the ucpd message log when there is a usbc detach event.
- *
- * @param enable -> on/off control for debug feature
- */
-void ucpd_cc_detect_notify_enable(int enable);
-
-/**
- * This function is used to enable/disable rx bist test mode in the ucpd
- * driver. This mode is controlled at the PE layer. When this mode is enabled,
- * the ucpd receiver will not pass BIST data messages to the protocol layer and
- * only send GoodCRC replies.
- *
- * @param usbc_port -> USB-C Port number
- * @param enable -> on/off control for rx bist mode
- */
-enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
-						   const bool enable);
-
-#endif /* __CROS_EC_UCPD_STM32GX_H */
diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c
deleted file mode 100644
index 908542146f..0000000000
--- a/chip/stm32/usart-stm32f0.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32f0.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 4
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud(config, config->baud);
-
-	task_enable_irq(config->hw->irq);
-}
-
-void usart_set_baud(struct usart_config const *config, int baud)
-{
-	usart_set_baud_f0_l(config, baud, clock_get_freq());
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	int index = config->hw->index;
-
-	/*
-	 * Only disable the shared interrupt for USART3/4 if both USARTs are
-	 * now disabled.
-	 */
-	if ((index == 0) ||
-	    (index == 1) ||
-	    (index == 2 && configs[3] == NULL) ||
-	    (index == 3 && configs[2] == NULL))
-		task_disable_irq(config->hw->irq);
-
-	configs[index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3_4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART4)
-struct usart_hw_config const usart4_hw = {
-	.index          = 3,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART3_4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3) || defined(CONFIG_STREAM_USART4)
-void usart3_4_interrupt(void)
-{
-	/*
-	 * This interrupt handler could be called with one of these configs
-	 * not initialized, so we need to check here and only call the generic
-	 * USART interrupt handler for initialized configs.
-	 */
-	if (configs[2])
-		usart_interrupt(configs[2]);
-
-	if (configs[3])
-		usart_interrupt(configs[3]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3_4, usart3_4_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h
deleted file mode 100644
index 1b7eee95a7..0000000000
--- a/chip/stm32/usart-stm32f0.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F0_H
-#define __CROS_EC_USART_STM32F0_H
-
-#include "usart.h"
-
-/*
- * The STM32F0 series can have as many as four UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-extern struct usart_hw_config const usart4_hw;
-
-#endif /* __CROS_EC_USART_STM32F0_H */
diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c
deleted file mode 100644
index 42a0cf310e..0000000000
--- a/chip/stm32/usart-stm32f3.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32f3.h"
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	configs[config->hw->index] = config;
-
-	/*
-	 * All three USARTS are clocked from the HSI(8MHz) source.  This is
-	 * done because the clock sources elsewhere are setup so that the result
-	 * of clock_get_freq() is not the input clock frequency to the USARTs
-	 * baud rate divisors.
-	 */
-	STM32_RCC_CFGR3 |= 0x000f0003;
-
-	usart_set_baud_f0_l(config, config->baud, 8000000);
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h
deleted file mode 100644
index 09f1ba608c..0000000000
--- a/chip/stm32/usart-stm32f3.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F3_H
-#define __CROS_EC_USART_STM32F3_H
-
-#include "usart.h"
-
-/*
- * The STM32F3 series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32F3_H */
diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c
deleted file mode 100644
index a554da147a..0000000000
--- a/chip/stm32/usart-stm32f4.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart-stm32f4.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	configs[config->hw->index] = config;
-
-
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h
deleted file mode 100644
index 49af2af405..0000000000
--- a/chip/stm32/usart-stm32f4.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32F4_H
-#define __CROS_EC_USART_STM32F4_H
-
-#include "usart.h"
-
-/*
- * The STM32F4 series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- * CONFIG_STREAM_USART<X> enables the corresponding hardware instance.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32F4_H */
diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c
deleted file mode 100644
index 2b7406a0a4..0000000000
--- a/chip/stm32/usart-stm32l.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32l.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 3
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h
deleted file mode 100644
index eb1ae9db1d..0000000000
--- a/chip/stm32/usart-stm32l.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32L_H
-#define __CROS_EC_USART_STM32L_H
-
-#include "usart.h"
-
-/*
- * The STM32L series can have as many as three UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-
-#endif /* __CROS_EC_USART_STM32L_H */
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c
deleted file mode 100644
index 0245718e21..0000000000
--- a/chip/stm32/usart-stm32l5.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart-stm32l.h"
-
-#include "clock.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * This configs array stores the currently active usart_config structure for
- * each USART, an entry will be NULL if no USART driver is initialized for the
- * corresponding hardware instance.
- */
-#define STM32_USARTS_MAX 4
-
-static struct usart_config const *configs[STM32_USARTS_MAX];
-
-struct usart_configs usart_get_configs(void)
-{
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
-}
-
-static void usart_variant_enable(struct usart_config const *config)
-{
-	/* Use single-bit sampling */
-	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
-
-	/*
-	 * Make sure we register this config before enabling the HW.
-	 * If we did it the other way around the FREQ_CHANGE hook could be
-	 * called before we update the configs array and we would miss the
-	 * clock frequency change event, leaving our baud rate divisor wrong.
-	 */
-	configs[config->hw->index] = config;
-
-	usart_set_baud_f0_l(config, config->baud, clock_get_freq());
-
-	task_enable_irq(config->hw->irq);
-}
-
-static void usart_variant_disable(struct usart_config const *config)
-{
-	task_disable_irq(config->hw->irq);
-
-	configs[config->hw->index] = NULL;
-}
-
-static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
-	.disable = usart_variant_disable,
-};
-
-static void freq_change(void)
-{
-	size_t	i;
-
-	for (i = 0; i < ARRAY_SIZE(configs); ++i)
-		if (configs[i])
-			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
-}
-
-DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
-
-void usart_clear_tc(struct usart_config const *config)
-{
-	STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC;
-}
-
-/*
- * USART interrupt bindings.  These functions can not be defined as static or
- * they will be removed by the linker because of the way that DECLARE_IRQ works.
- */
-#if defined(CONFIG_STREAM_USART1)
-struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
-	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart1_interrupt(void)
-{
-	usart_interrupt(configs[0]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART2)
-struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart2_interrupt(void)
-{
-	usart_interrupt(configs[1]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART3)
-struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart3_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
-#endif
-
-#if defined(CONFIG_STREAM_USART4)
-struct usart_hw_config const usart4_hw = {
-	.index          = 2,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART4,
-	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
-};
-
-void usart4_interrupt(void)
-{
-	usart_interrupt(configs[2]);
-}
-
-DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
-#endif
diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h
deleted file mode 100644
index 564ffbc580..0000000000
--- a/chip/stm32/usart-stm32l5.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_STM32L5_H
-#define __CROS_EC_USART_STM32L5_H
-
-#include "usart.h"
-
-/*
- * The STM32L5 series can have as many as four UARTS.  These are the HW configs
- * for those UARTS.  They can be used to initialize STM32 generic UART configs.
- */
-extern struct usart_hw_config const usart1_hw;
-extern struct usart_hw_config const usart2_hw;
-extern struct usart_hw_config const usart3_hw;
-extern struct usart_hw_config const usart4_hw;
-
-#endif /* __CROS_EC_USART_STM32L5_H */
diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
deleted file mode 100644
index 7f8c55aaa6..0000000000
--- a/chip/stm32/usart.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "atomic.h"
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart.h"
-#include "util.h"
-
-void usart_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-	uint32_t cr2, cr3;
-
-	/*
-	 * Enable clock to USART, this must be done first, before attempting
-	 * to configure the USART.
-	 */
-	*(config->hw->clock_register) |= config->hw->clock_enable;
-
-	/*
-	 * For STM32F3, A delay of 1 APB clock cycles is needed before we
-	 * can access any USART register. Fortunately, we have
-	 * gpio_config_module() below and thus don't need to add the delay.
-	 */
-
-	/*
-	 * Switch all GPIOs assigned to the USART module over to their USART
-	 * alternate functions.
-	 */
-	gpio_config_module(MODULE_USART, 1);
-
-	/*
-	 * 8N1, 16 samples per bit. error interrupts, and special modes
-	 * disabled.
-	 */
-
-	cr2 = 0x0000;
-	cr3 = 0x0000;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-    defined(CHIP_FAMILY_STM32L4)
-	if (config->flags & USART_CONFIG_FLAG_RX_INV)
-		cr2 |= BIT(16);
-	if (config->flags & USART_CONFIG_FLAG_TX_INV)
-		cr2 |= BIT(17);
-#endif
-	if (config->flags & USART_CONFIG_FLAG_HDSEL)
-		cr3 |= BIT(3);
-
-	STM32_USART_CR1(base) = 0x0000;
-	STM32_USART_CR2(base) = cr2;
-	STM32_USART_CR3(base) = cr3;
-
-	/*
-	 * Enable the RX, TX, and variant specific HW.
-	 */
-	config->rx->init(config);
-	config->tx->init(config);
-	config->hw->ops->enable(config);
-
-	/*
-	 * Clear error counts.
-	 */
-	config->state->rx_overrun = 0;
-	config->state->rx_dropped = 0;
-
-	/*
-	 * Enable the USART, this must be done last since most of the
-	 * configuration bits require that the USART be disabled for writes to
-	 * succeed.
-	 */
-	STM32_USART_CR1(base) |= STM32_USART_CR1_UE;
-}
-
-void usart_shutdown(struct usart_config const *config)
-{
-	STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE;
-
-	config->hw->ops->disable(config);
-}
-
-void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz)
-{
-	int      div  = DIV_ROUND_NEAREST(frequency_hz, baud);
-	intptr_t base = config->hw->base;
-
-	if (div / 16 > 0) {
-		/*
-		 * CPU clock is high enough to support x16 oversampling.
-		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
-		 */
-		STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(base) = div;
-	} else {
-		/*
-		 * CPU clock is low; use x8 oversampling.
-		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
-		 */
-		STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8;
-	}
-}
-
-void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz)
-{
-	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
-
-	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(config->hw->base) = div;
-}
-
-int usart_get_parity(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	if (!(STM32_USART_CR1(base) & STM32_USART_CR1_PCE))
-		return 0;
-	if (STM32_USART_CR1(base) & STM32_USART_CR1_PS)
-		return 1;
-	return 2;
-}
-
-/*
- * We only allow 8 bit word. CR1_PCE modifies parity enable,
- * CR1_PS modifies even/odd, CR1_M modifies total word length
- * to make room for parity.
- */
-void usart_set_parity(struct usart_config const *config, int parity)
-{
-	uint32_t ue;
-	intptr_t base = config->hw->base;
-
-	if ((parity < 0) || (parity > 2))
-		return;
-
-	/* Record active state and disable the UART. */
-	ue = STM32_USART_CR1(base) & STM32_USART_CR1_UE;
-	STM32_USART_CR1(base) &= ~STM32_USART_CR1_UE;
-
-	if (parity) {
-		/* Set parity control enable. */
-		STM32_USART_CR1(base) |=
-			(STM32_USART_CR1_PCE | STM32_USART_CR1_M);
-		/* Set parity select even/odd bit. */
-		if (parity == 2)
-			STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS;
-		else
-			STM32_USART_CR1(base) |= STM32_USART_CR1_PS;
-	} else {
-		STM32_USART_CR1(base) &=
-			~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS |
-			  STM32_USART_CR1_M);
-	}
-
-	/* Restore active state. */
-	STM32_USART_CR1(base) |= ue;
-}
-
-void usart_interrupt(struct usart_config const *config)
-{
-	config->tx->interrupt(config);
-	config->rx->interrupt(config);
-}
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
deleted file mode 100644
index 491bd66a04..0000000000
--- a/chip/stm32/usart.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USART_H
-#define __CROS_EC_USART_H
-
-/* STM32 USART driver for Chrome EC */
-
-#include "common.h"
-#include "consumer.h"
-#include "producer.h"
-#include "queue.h"
-
-#include <stdint.h>
-
-/*
- * Per-USART state stored in RAM.  This structure will be zero initialized by
- * BSS init.
- */
-struct usart_state {
-	/*
-	 * Counter of bytes received and then dropped because of lack of space
-	 * in the RX queue.
-	 */
-	uint32_t rx_dropped;
-
-	/*
-	 * Counter of the number of times an receive overrun condition is
-	 * detected.  This will not usually be a count of the number of bytes
-	 * that were lost due to overrun conditions.
-	 */
-	uint32_t rx_overrun;
-};
-
-struct usart_config;
-
-struct usart_hw_ops {
-	/*
-	 * The generic USART initialization code calls this function to allow
-	 * the variant HW specific code to perform any initialization.  This
-	 * function is called before the USART is enabled, and should among
-	 * other things enable the USARTs interrupt.
-	 */
-	void (*enable)(struct usart_config const *config);
-
-	/*
-	 * The generic USART shutdown code calls this function, allowing the
-	 * variant specific code an opportunity to do any variant specific
-	 * shutdown tasks.
-	 */
-	void (*disable)(struct usart_config const *config);
-};
-
-/*
- * The usart_rx/usart_tx structures contain functions pointers for the
- * interrupt handler and producer/consumer operations required to implement a
- * particular RX/TX strategy.
- *
- * These structures are defined by the various RX/TX implementations, and are
- * used to initialize the usart_config structure to configure the USART driver
- * for interrupt or DMA based transfer.
- */
-struct usart_rx {
-	void (*init)(struct usart_config const *config);
-	void (*interrupt)(struct usart_config const *config);
-
-	/*
-	 * Print to the console any per-strategy diagnostic information, this
-	 * is used by the usart_info command.  This can be NULL if there is
-	 * nothing interesting to display.
-	 */
-	void (*info)(struct usart_config const *config);
-
-	struct producer_ops producer_ops;
-};
-
-struct usart_tx {
-	void (*init)(struct usart_config const *config);
-	void (*interrupt)(struct usart_config const *config);
-
-	/*
-	 * Print to the console any per-strategy diagnostic information, this
-	 * is used by the usart_info command.  This can be NULL if there is
-	 * nothing interesting to display.
-	 */
-	void (*info)(struct usart_config const *config);
-
-	struct consumer_ops consumer_ops;
-};
-
-extern struct usart_rx const usart_rx_interrupt;
-extern struct usart_tx const usart_tx_interrupt;
-
-/*
- * Per-USART hardware configuration stored in flash.  Instances of this
- * structure are provided by each variants driver, one per physical USART.
- */
-struct usart_hw_config {
-	int      index;
-	intptr_t base;
-	int      irq;
-
-	uint32_t volatile *clock_register;
-	uint32_t           clock_enable;
-
-	struct usart_hw_ops const *ops;
-};
-
-/*
- * Compile time Per-USART configuration stored in flash.  Instances of this
- * structure are provided by the user of the USART.  This structure binds
- * together all information required to operate a USART.
- */
-struct usart_config {
-	/*
-	 * Pointer to USART HW configuration.  There is one HW configuration
-	 * per physical USART.
-	 */
-	struct usart_hw_config const *hw;
-
-	struct usart_rx const *rx;
-	struct usart_tx const *tx;
-
-	/*
-	 * Pointer to USART state structure.  The state structure maintains per
-	 * USART information.
-	 */
-	struct usart_state volatile *state;
-
-	/*
-	 * Baud rate for USART.
-	 */
-	int baud;
-
-	/* Other flags (rx/tx inversion, half-duplex). */
-#define USART_CONFIG_FLAG_RX_INV BIT(0)
-#define USART_CONFIG_FLAG_TX_INV BIT(1)
-#define USART_CONFIG_FLAG_HDSEL BIT(2)
-	unsigned int flags;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * Convenience macro for defining USARTs and their associated state and buffers.
- * NAME is used to construct the names of the usart_state struct, and
- * usart_config struct, the latter is just called NAME.
- *
- * HW is the name of the usart_hw_config provided by the variant specific code.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this USART
- * should write to and read from respectively.
- */
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE)	\
-	((struct usart_config const) {					\
-		.hw       = &HW,					\
-		.rx       = &RX,					\
-		.tx       = &TX,					\
-		.state    = &((struct usart_state){}),			\
-		.baud     = BAUD,					\
-		.flags    = FLAGS,					\
-		.consumer = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &TX.consumer_ops,			\
-		},							\
-		.producer = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &RX.producer_ops,			\
-		},							\
-	})
-
-/*
- * Initialize the given USART.  Once init is finished the USART streams are
- * available for operating on.
- */
-void usart_init(struct usart_config const *config);
-
-/*
- * Shutdown the given USART.
- */
-void usart_shutdown(struct usart_config const *config);
-
-/*
- * Handle a USART interrupt.  The per-variant USART code creates bindings
- * for the variants interrupts to call this generic USART interrupt handler
- * with the appropriate usart_config.
- */
-void usart_interrupt(struct usart_config const *config);
-
-/*
- * Trigger tx interrupt to process tx data. Calling this function will set
- * TXIEIE of USART HW instance and trigger associated IRQ.
- */
-void usart_tx_start(struct usart_config const *config);
-
-/*
- * These are HW specific baud rate calculation and setting functions that the
- * peripheral variant code uses during initialization and clock frequency
- * change.  The baud rate divisor input frequency is passed in Hertz.
- */
-void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz);
-void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz);
-
-/*
- * Allow specification of parity for this usart.
- * parity is 0: none, 1: odd, 2: even.
- */
-void usart_set_parity(struct usart_config const *config, int parity);
-
-/*
- * Check parity for this usart.
- * parity is 0: none, 1: odd, 2: even.
- */
-int usart_get_parity(struct usart_config const *config);
-
-/*
- * Set baud rate for this usart. Note that baud rate will get reset on
- * core frequency change, so this only makes sense if the board never
- * goes to deep idle.
- */
-void usart_set_baud(struct usart_config const *config, int baud);
-
-/*
- * Different families provide different ways of clearing the transmit complete
- * flag.  This function will be provided by the family specific implementation.
- */
-void usart_clear_tc(struct usart_config const *config);
-
-/*
- * Each family implementation provides the usart_get_configs function to access
- * a read only list of the configs that are currently enabled.
- */
-struct usart_configs {
-	/*
-	 * The family's usart_config array, entries in the array for disabled
-	 * configs will be NULL, enabled configs will point to the usart_config
-	 * that was enabled.  And the following will be true:
-	 *
-	 * configs[i]->hw->index == i;
-	 */
-	struct usart_config const * const *configs;
-
-	/*
-	 * The total possible number of configs that this family supports.
-	 * This will be the same as the number of usart_hw structs that the
-	 * family provides in its family specific usart header.
-	 */
-	size_t count;
-};
-
-struct usart_configs usart_get_configs(void);
-
-/*
- * This usart_tx structure contains function pointer to interrupt
- * handler implemented to send host response. Generic queue based
- * interrupt handler is not used for usart host transport.
- */
-extern struct usart_tx const usart_host_command_tx_interrupt;
-
-#endif /* __CROS_EC_USART_H */
diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c
deleted file mode 100644
index f4d6a65fc4..0000000000
--- a/chip/stm32/usart_host_command.c
+++ /dev/null
@@ -1,616 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "clock.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "queue_policies.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart_rx_dma.h"
-#include "usart_host_command.h"
-#include "usart-stm32f4.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-
-/*
- * Timeout to wait for complete request packet
- *
- * This value determines how long we should wait for entire packet to arrive.
- * USART host command handler should wait for at least 75% of
- * EC_MSG_DEADLINE_MS, before declaring timeout and dropping the packet.
- *
- * This timeout should be less than host's driver timeout to make sure that
- * last packet can be successfully discarded before AP attempts to resend
- * request. AP driver waits for EC_MSG_DEADLINE_MS = 200 before attempting a
- * retry.
- */
-#define USART_REQ_RX_TIMEOUT (150 * MSEC)
-
-/*
- * Timeout to wait for overrun bytes on USART
- *
- * This values determines how long call to process_request should be deferred
- * in case host is sending extra bytes. This value is based on DMA buffer size.
- *
- * There is no guarantee that AP will send continuous bytes on usart. Wait
- * for USART_DEFERRED_PROCESS_REQ_TIMEOUT_US to check if host is sending
- * extra bytes.
- * Note: This value affects the response latency.
- */
-#define USART_DEFERRED_PROCESS_REQ_TIMEOUT 300
-
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size and 512 bytes 
- * of request payload or 224 bytes of response payload.
- */
-#define USART_MAX_REQUEST_SIZE 0x220
-#define USART_MAX_RESPONSE_SIZE 0x100
-
-/*
- * FIFO size for USART DMA. Should be big enough to handle worst case
- * data processing
- */
-#define USART_DMA_FIFO_SIZE 0x110
-
-/* Local definitions */
-
-/*
- * Raw USART RX/TX byte buffers.
- */
-static uint8_t usart_in_buffer[USART_MAX_REQUEST_SIZE] __aligned(4);
-static uint8_t usart_out_buffer[USART_MAX_RESPONSE_SIZE] __aligned(4);
-
-/*
- * Maintain head position of in buffer
- * Head always starts with zero and goes up to max bytes.
- * Once the buffer contents are read, it should go back to zero.
- */
-static uint16_t usart_in_head;
-
-/*
- * Maintain head position of out buffer
- * Head always starts from zero and goes up to max bytes.
- * Head is moved by tx interrupt handler to response size sent by host command
- * task. Once all the bytes are sent (head == tail) both should go back to 0.
- */
-static uint16_t usart_out_head;
-
-/*
- * Once the response is ready, get the datalen
- */
-static uint16_t usart_out_datalen;
-
-/*
- * Enumeration to maintain different states of incoming request from
- * host
- */
-static enum uart_host_command_state {
-	/*
-	 * USART host command handler not enabled.
-	 */
-	USART_HOST_CMD_STATE_DISABLED,
-
-	/*
-	 * Ready to receive next request
-	 * This state represents USART layer is initialized and ready to
-	 * receive host request. Once the response is sent, current_state is
-	 * reset to this state to accept next packet.
-	 */
-	USART_HOST_CMD_READY_TO_RX,
-
-	/*
-	 * Receiving request
-	 * After first byte is received current_state is moved to receiving
-	 * state until all the header bytes + datalen bytes are received.
-	 * If host_request_timeout was called in this state, it would be
-	 * because of an underrun situation.
-	 */
-	USART_HOST_CMD_RECEIVING,
-
-	/*
-	 * Receiving complete
-	 * Once all the header bytes + datalen bytes are received, current_state
-	 * is moved to complete. Ideally, host should wait for response or retry
-	 * timeout before sending anymore bytes, otherwise current_state will
-	 * be moved to overrun to represent extra bytes sent by host.
-	 */
-	USART_HOST_CMD_COMPLETE,
-
-	/*
-	 * Processing request
-	 * Once the process_request starts processing usart_in_buffer,
-	 * current_state is moved to processing state. Host should not send
-	 * any bytes in this state as it would be considered contiguous
-	 * request.
-	 */
-	USART_HOST_CMD_PROCESSING,
-
-	/*
-	 * Sending response
-	 * Once host task is ready with the response bytes, current_state is
-	 * moved to sending state.
-	 */
-	USART_HOST_CMD_SENDING,
-
-	/*
-	 * Received bad data
-	 * If bad packet header is received, current_state is moved to rx_bad
-	 * state and after rx_timeout all the bytes are dropped.
-	 */
-	USART_HOST_CMD_RX_BAD,
-
-	/*
-	 * Receiving data overrun bytes
-	 * If extra bytes are received after current_state is in complete,
-	 * host is sending extra bytes which indicates data overrun.
-	 */
-	USART_HOST_CMD_RX_OVERRUN,
-
-} current_state __aligned(4);
-
-/*
- * This diagram is the state machine representation of USART host
- * command layer.
- *
- * This layer is responsible for checking packet integrity of incoming bytes
- * on usart transceiver. It will only process packet header to check version,
- * data_len. This layer will not process payload bytes.
- *
- * STATE = USART_HOST_CMD_STATE_DISABLED
- *
- * Initialize USART and local variables
- *
- * STATE = USART_HOST_CMD_READY_TO_RX
- *
- *     |<---------- HOST RETRY TIMEOUT = 200 ms ---------->|
- *     |
- *     |--------------USART_REQ_RX_TIMEOUT------>|
- *     |     Underrun if request not complete -->|
- *     |                                         |<-- USART ready to rx
- *     |____REQUEST____                                      ____REQUEST____
- *     |     |         |                                    |     |         |
- *     | HDR | DATA    |                                    | HDR | DATA    |
- *     |_____|_________|                                    |_____|_________|
- *     |
- *     |<-- Request packet start
- *           |
- * STATE = USART_HOST_CMD_RECEIVING
- *           |
- *           |<-- HDR received, now we will wait for data len bytes
- *                     |
- * If bad packet is received, move state to rx_bad
- * STATE = USART_HOST_CMD_RX_BAD
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- *                     |<-- Request packet end (data rx complete)            |
- *                     |                                                     |
- * If request_timeout is called, it represents packet underrun               |
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- * STATE = USART_HOST_CMD_COMPLETE                                           |
- *                     |                                                     |
- *                     |<-- Deferred call to process request                 |
- *                     |                                                     |
- * If extra byte is received, move state to overrun                          |
- * STATE = USART_HOST_CMD_RX_OVERRUN                                         |
- * Ignore data processing, print status on console and reset layer -----------
- *                     |                                                     |
- *                  -->|  |<-- USART_DEFERRED_PROCESS_REQ_TIMEOUT            |
- *                        |    Start process request                         |
- *                        |                                                  |
- * STATE = USART_HOST_CMD_PROCESSING                                         |
- *                        |                                                  |
- * Send ec_host_request to host command task                                 |
- *                        |<-- Packet sent to host command task              |
- *                       >|  |<-- host command task process time             |
- *                           |<-- host command task ready for response       |
- *                           |                                               |
- * STATE = USART_HOST_CMD_SENDING                                            |
- *                           |                                               |
- *                           |____RESPONSE____                               |
- *                           |     |          |                              |
- *                           | HDR | DATA     |                              |
- *                           |_____|__________|                              |
- *                                            |                              |
- *                                            |<-- Response send complete    |
- *                                                                           |
- * STATE = USART_HOST_CMD_READY_TO_RX          <------------------------------
- */
-
-/*
- * Local function definition
- */
-static void usart_host_command_reset(void);
-static void usart_host_command_request_timeout(void);
-static void usart_host_command_process_request(void);
-static void usart_host_command_process_response(struct host_packet *pkt);
-/*
- * Local variable declaration
- */
-
-/*
- * Configure dma instance for rx
- *
- * STM32_DMAS_USART1_RX is the DMA channel to be used for reception. This DMA
- * channel is for the USART peripheral.
- *
- * A unnamed, valid, empty usart_rx_dma_state structure is required to manage
- * DMA based transmission.
- *
- * USART_DMA_FIFO_SIZE is size of the valid, unnamed  DMA circular buffer.
- * This buffer is large enough to process worst case interrupt latency this
- * layer can encounter.
- */
-static struct usart_rx_dma const usart_host_command_rx_dma = {
-	.usart_rx = {
-		.producer_ops = {
-				.read = NULL,
-			},
-		.init      = usart_rx_dma_init,
-		.interrupt = usart_host_command_rx_dma_interrupt,
-		.info      = USART_RX_DMA_INFO,
-	},
-	.state       = &((struct usart_rx_dma_state) {}),
-	.fifo_buffer = ((uint8_t[USART_DMA_FIFO_SIZE]) {}),
-	.fifo_size   = USART_DMA_FIFO_SIZE,
-	.channel     = STM32_DMAS_USART1_RX,
-};
-
-/*
- * Configure USART structure with hardware, interrupt handlers, baudrate.
- */
-static struct usart_config const tl_usart = {
-	.hw	= &CONFIG_UART_HOST_COMMAND_HW,
-	.rx	= &usart_host_command_rx_dma.usart_rx,
-	.tx	= &usart_host_command_tx_interrupt,
-	.state	= &((struct usart_state){}),
-	.baud	= CONFIG_UART_HOST_COMMAND_BAUD_RATE,
-	.flags	= 0,
-};
-
-/*
- * Local function declaration
- */
-
-/*
- * This function will be called only if request rx timed out.
- * Drop the packet and put tl state into RX_READY
- */
-static void usart_host_command_request_timeout(void)
-{
-	switch (current_state) {
-	case USART_HOST_CMD_RECEIVING:
-		/* If state is receiving then timeout was hit due to underrun */
-		CPRINTS("USART HOST CMD ERROR: Request underrun detected.");
-		break;
-
-	case USART_HOST_CMD_RX_OVERRUN:
-		/* If state is rx_overrun then timeout was hit because
-		 * process request was cancelled and extra rx bytes were
-		 * dropped
-		 */
-		CPRINTS("USART HOST CMD ERROR: Request overrun detected.");
-		break;
-
-	case USART_HOST_CMD_RX_BAD:
-		/* If state is rx_bad then packet header was bad and process
-		 * request was cancelled to drop all incoming bytes.
-		 */
-		CPRINTS("USART HOST CMD ERROR: Bad packet header detected.");
-		break;
-
-	default:
-		CPRINTS("USART HOST CMD ERROR: Request timeout mishandled");
-	}
-
-	/* Reset host command layer to accept new request */
-	usart_host_command_reset();
-}
-DECLARE_DEFERRED(usart_host_command_request_timeout);
-
-/*
- * This function is called from interrupt handler after entire packet is
- * received.
- */
-static void usart_host_command_process_request(void)
-{
-	/* Handle usart_in_buffer as ec_host_request */
-	struct ec_host_request *ec_request =
-			(struct ec_host_request *)usart_in_buffer;
-
-	/* Prepare host_packet for host command task */
-	static struct host_packet uart_packet;
-
-	/*
-	 * Disable interrupts before processing request to be sent
-	 * to host command task.
-	 */
-	interrupt_disable();
-
-	/*
-	 * In case rx interrupt handler was called in this function's prologue,
-	 * host was trying to send extra byte(s) exactly when
-	 * USART_DEFERRED_PROCESS_REQ_TIMEOUT expired. If state is
-	 * not USART_HOST_CMD_COMPLETE, overrun condition is already
-	 * handled.
-	 */
-	if (current_state != USART_HOST_CMD_COMPLETE) {
-		/* Enable interrupts before exiting this function. */
-		interrupt_enable();
-
-		return;
-	}
-
-	/* Move current_state to USART_HOST_CMD_PROCESSING */
-	current_state = USART_HOST_CMD_PROCESSING;
-
-	/* Enable interrupts as current_state is safely handled. */
-	interrupt_enable();
-
-	/*
-	 * Cancel deferred call to timeout handler as request
-	 * received was good.
-	 */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
-
-	uart_packet.send_response = usart_host_command_process_response;
-	uart_packet.request = usart_in_buffer;
-	uart_packet.request_temp = NULL;
-	uart_packet.request_max = sizeof(usart_in_buffer);
-	uart_packet.request_size =
-			host_request_expected_size(ec_request);
-	uart_packet.response = usart_out_buffer;
-	uart_packet.response_max = sizeof(usart_out_buffer);
-	uart_packet.response_size = 0;
-	uart_packet.driver_result = EC_RES_SUCCESS;
-
-	/* Process usart_packet */
-	host_packet_receive(&uart_packet);
-}
-DECLARE_DEFERRED(usart_host_command_process_request);
-
-/*
- * This function is called from host command task after it is ready with a
- * response.
- */
-static void usart_host_command_process_response(struct host_packet *pkt)
-{
-	/* Disable interrupts before entering critical section. */
-	interrupt_disable();
-
-	/*
-	 * Send host command response in usart_out_buffer via
-	 * tx_interrupt_handler.
-	 *
-	 * Send response if current state is USART_HOST_CMD_PROCESSING
-	 * state. If this layer is in any other state drop response and
-	 * let request timeout handler handle state transitions.
-	 */
-	if (current_state != USART_HOST_CMD_PROCESSING) {
-		/* Enable interrupts before exiting critical section. */
-		interrupt_enable();
-
-		return;
-	}
-
-	/* Move to sending state. */
-	current_state = USART_HOST_CMD_SENDING;
-
-	/* Enable interrupts before exiting critical section. */
-	interrupt_enable();
-
-	usart_out_datalen = pkt->response_size;
-	usart_out_head = 0;
-
-	/* Start sending response to host via usart tx by
-	 * triggering tx interrupt.
-	 */
-	usart_tx_start(&tl_usart);
-}
-
-/*
- * This function will drop current request, clear buffers.
- */
-static void usart_host_command_reset(void)
-{
-	/* Cancel deferred call to process_request. */
-	hook_call_deferred(
-		&usart_host_command_process_request_data,
-		-1);
-
-	/* Cancel deferred call to timeout handler. */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
-
-	/*
-	 * Disable interrupts before entering critical region
-	 * Operations in this section should be minimum to avoid
-	 * harming the real-time characteristics of the runtime.
-	 */
-	interrupt_disable();
-
-	/* Clear in buffer, head and datalen */
-	usart_in_head = 0;
-
-	/* Clear out buffer, head and datalen */
-	usart_out_datalen = 0;
-	usart_out_head = 0;
-
-	/* Move to ready state*/
-	current_state = USART_HOST_CMD_READY_TO_RX;
-
-	/* Enable interrupts before exiting critical region
-	 */
-	interrupt_enable();
-}
-
-/*
- * Exported functions
- */
-
-/*
- * Initialize USART host command layer.
- */
-void usart_host_command_init(void)
-{
-	/* USART host command layer starts in DISABLED state */
-	current_state = USART_HOST_CMD_STATE_DISABLED;
-
-	/* Initialize transport uart */
-	usart_init(&tl_usart);
-
-	/* Initialize local variables */
-	usart_in_head = 0;
-	usart_out_head = 0;
-	usart_out_datalen = 0;
-
-	/* Move to ready state */
-	current_state = USART_HOST_CMD_READY_TO_RX;
-}
-
-/*
- * Function to handle incoming bytes from DMA interrupt handler
- *
- */
-size_t usart_host_command_rx_append_data(struct usart_config const *config,
-					 const uint8_t *src, size_t count)
-{
-	/* Define ec_host_request pointer to process in bytes later*/
-	struct ec_host_request *ec_request =
-			(struct ec_host_request *) usart_in_buffer;
-
-	/* Once the header is received, store the datalen */
-	static int usart_in_datalen;
-
-	/*
-	 * Host can send extra bytes than in header data_len
-	 * Only copy valid bytes in buffer
-	 */
-	if (current_state == USART_HOST_CMD_READY_TO_RX ||
-	    current_state == USART_HOST_CMD_RECEIVING ||
-	    (usart_in_head + count) < USART_MAX_REQUEST_SIZE) {
-		/* Copy all the bytes from DMA FIFO */
-		memcpy(usart_in_buffer + usart_in_head,
-			src, count);
-	}
-
-	/*
-	 * Add incoming byte count to usart_in_head.
-	 * Even if overflow bytes are not copied in buffer, maintain
-	 * the overflow count so that packet can be dropped later in this
-	 * function.
-	 */
-	usart_in_head += count;
-
-	if (current_state == USART_HOST_CMD_READY_TO_RX) {
-		/* Kick deferred call to request timeout handler */
-		hook_call_deferred(&usart_host_command_request_timeout_data,
-			USART_REQ_RX_TIMEOUT);
-
-		/* Move current state to receiving */
-		current_state = USART_HOST_CMD_RECEIVING;
-	}
-
-	if (usart_in_head >= sizeof(struct ec_host_request)) {
-		/* Buffer has request header. Check header and get data_len */
-		usart_in_datalen = host_request_expected_size(ec_request);
-
-		if (usart_in_datalen == 0 ||
-		    usart_in_datalen > USART_MAX_REQUEST_SIZE) {
-			/* EC host request version not compatible or
-			 * reserved byte is not zero.
-			 */
-			current_state = USART_HOST_CMD_RX_BAD;
-		} else if (usart_in_head == usart_in_datalen) {
-			/*
-			 * Once all the datalen bytes are received, wait for
-			 * USART_DEFERRED_PROCESS_REQ_TIMEOUT to call
-			 * process_request function. This is to catch overrun
-			 * bytes before processing the packet.
-			 */
-			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				USART_DEFERRED_PROCESS_REQ_TIMEOUT);
-
-			/* If no data in request, packet is complete */
-			current_state = USART_HOST_CMD_COMPLETE;
-		} else if (usart_in_head > usart_in_datalen) {
-			/* Cancel deferred call to process_request */
-			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				-1);
-
-			/* Move state to overrun*/
-			current_state = USART_HOST_CMD_RX_OVERRUN;
-		}
-	}
-
-	if (current_state == USART_HOST_CMD_PROCESSING)
-		/* Host should not send data before receiving a response.
-		 * Since the request was already sent to host command task,
-		 * just notify console about this. After response is sent
-		 * dma will be cleared to handle next packet
-		 */
-		CPRINTS("USART HOST CMD ERROR: Contiguous packets detected.");
-
-	/* Return count to show all incoming bytes were processed */
-	return count;
-}
-
-/*
- * This function processes the outgoing bytes from tl usart.
- */
-size_t usart_host_command_tx_remove_data(struct usart_config const *config,
-					 uint8_t *dest)
-{
-	size_t bytes_remaining = 0;
-
-	if (current_state == USART_HOST_CMD_SENDING &&
-	    usart_out_datalen != 0) {
-		/* Calculate byte_remaining in out_buffer */
-		bytes_remaining = usart_out_datalen - usart_out_head;
-
-		/* Get char on the head */
-		*((uint8_t *) dest) = usart_out_buffer[usart_out_head++];
-
-		/* If no bytes remaining, reset layer to accept next
-		 * request.
-		 */
-		if (bytes_remaining == 0)
-			usart_host_command_reset();
-	}
-
-	/* Return count of bytes remaining in out buffer */
-	return bytes_remaining;
-}
-
-/*
- * Get protocol information
- */
-enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions |= BIT(3);
-	r->max_request_packet_size = USART_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = USART_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h
deleted file mode 100644
index ee41d8a59b..0000000000
--- a/chip/stm32/usart_host_command.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USART_HOST_COMMAND_H
-#define __CROS_EC_USART_HOST_COMMAND_H
-
-#include <stdarg.h>  /* For va_list */
-#include "common.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "usart.h"
-
-/*
- * Add data to host command layer buffer.
- */
-size_t usart_host_command_rx_append_data(struct usart_config const *config,
-					 const uint8_t *src, size_t count);
-
-/*
- * Remove data from the host command layer buffer.
- */
-size_t usart_host_command_tx_remove_data(struct usart_config const *config,
-					 uint8_t *dest);
-
-/*
- * Get USART protocol information. This function is called in runtime if
- * board's host command transport is USART.
- */
-enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args);
-
-/*
- * Initialize USART host command layer.
- */
-void usart_host_command_init(void);
-
-#endif /* __CROS_EC_USART_HOST_COMMAND_H */
diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c
deleted file mode 100644
index 2649a97351..0000000000
--- a/chip/stm32/usart_info_command.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Console command to query USART state
- */
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "usart.h"
-
-static int command_usart_info(int argc, char **argv)
-{
-	struct usart_configs configs = usart_get_configs();
-	size_t i;
-
-	for (i = 0; i < configs.count; i++) {
-		struct usart_config const *config = configs.configs[i];
-
-		if (config == NULL)
-			continue;
-
-		ccprintf(
-			"USART%d\n"
-			"    dropped %d bytes\n"
-			"    overran %d times\n",
-			config->hw->index + 1,
-			atomic_clear((uint32_t *)&(config->state->rx_dropped)),
-			atomic_clear((uint32_t *)&(config->state->rx_overrun)));
-
-		if (config->rx->info)
-			config->rx->info(config);
-
-		if (config->tx->info)
-			config->tx->info(config);
-	}
-
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(usart_info,
-			command_usart_info,
-			NULL,
-			"Display USART info");
diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c
deleted file mode 100644
index a185878261..0000000000
--- a/chip/stm32/usart_rx_dma.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart_rx_dma.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "registers.h"
-#include "system.h"
-#include "usart_host_command.h"
-#include "util.h"
-
-typedef size_t (*add_data_t)(struct usart_config const *config,
-	const uint8_t *src, size_t count);
-
-void usart_rx_dma_init(struct usart_config const *config)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	intptr_t base = config->hw->base;
-
-	struct dma_option options = {
-		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_RDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT |
-			    STM32_DMA_CCR_CIRC),
-	};
-
-	if (IS_ENABLED(CHIP_FAMILY_STM32F4))
-		options.flags |= STM32_DMA_CCR_CHANNEL(STM32_REQ_USART1_RX);
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR;
-
-	dma_config->state->index     = 0;
-	dma_config->state->max_bytes = 0;
-
-	dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer);
-}
-
-static void usart_rx_dma_interrupt_common(
-		struct usart_config const *config,
-		add_data_t add_data)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	dma_chan_t *channel  = dma_get_channel(dma_config->channel);
-	size_t     new_index = dma_bytes_done(channel, dma_config->fifo_size);
-	size_t     old_index = dma_config->state->index;
-	size_t     new_bytes = 0;
-	size_t     added     = 0;
-
-	if (new_index > old_index) {
-		new_bytes = new_index - old_index;
-
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				new_bytes);
-	} else if (new_index < old_index) {
-		/*
-		 * Handle the case where the received bytes are not contiguous
-		 * in the circular DMA buffer.  This is done with two queue
-		 * adds.
-		 */
-		new_bytes = dma_config->fifo_size - (old_index - new_index);
-
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				dma_config->fifo_size - old_index) +
-			add_data(config,
-				dma_config->fifo_buffer,
-				new_index);
-	} else {
-		/* (new_index == old_index): nothing to add to the queue. */
-	}
-
-	atomic_add((uint32_t *)&(config->state->rx_dropped), new_bytes - added);
-
-	if (dma_config->state->max_bytes < new_bytes)
-		dma_config->state->max_bytes = new_bytes;
-
-	dma_config->state->index = new_index;
-}
-
-static size_t queue_add(struct usart_config const *config,
-			const uint8_t *src, size_t count)
-{
-	return queue_add_units(config->producer.queue, (void *)src, count);
-}
-
-void usart_rx_dma_interrupt(struct usart_config const *config)
-{
-	usart_rx_dma_interrupt_common(config, &queue_add);
-}
-
-
-#if defined(CONFIG_USART_HOST_COMMAND)
-void usart_host_command_rx_dma_interrupt(struct usart_config const *config)
-{
-	usart_rx_dma_interrupt_common(config,
-				      &usart_host_command_rx_append_data);
-}
-#endif /* CONFIG_USART_HOST_COMMAND */
-
-void usart_rx_dma_info(struct usart_config const *config)
-{
-	struct usart_rx_dma const *dma_config =
-		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
-
-	ccprintf("    DMA RX max_bytes %d\n",
-		 atomic_clear((uint32_t *)&dma_config->state->max_bytes));
-}
diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h
deleted file mode 100644
index 064ab8046c..0000000000
--- a/chip/stm32/usart_rx_dma.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Hybrid DMA/Interrupt based USART RX driver for STM32
- */
-#ifndef __CROS_EC_USART_RX_DMA_H
-#define __CROS_EC_USART_RX_DMA_H
-
-#include "producer.h"
-#include "dma.h"
-#include "queue.h"
-#include "usart.h"
-
-/*
- * Only reference the usart_rx_dma_info function if CONFIG_CMD_USART_INFO
- * is defined.  This allows the compiler to remove this function as dead code
- * when CONFIG_CMD_USART_INFO is not defined.
- */
-#ifdef CONFIG_CMD_USART_INFO
-#define USART_RX_DMA_INFO usart_rx_dma_info
-#else
-#define USART_RX_DMA_INFO NULL
-#endif
-
-/*
- * Construct a USART RX instance for DMA using the given DMA channel.
- *
- * This macro creates a new usart_rx_dma struct, complete with in RAM state,
- * the contained usart_rx struct can be used in initializing a usart_config
- * struct.
- *
- * CHANNEL is the DMA channel to be used for reception.  This must be a valid
- * DMA channel for the USART peripheral and any alternate channel mappings must
- * be handled by the board specific code.
- *
- * FIFO_SIZE is the number of bytes (which does not need to be a power of two)
- * to use for the DMA circular buffer.  This buffer must be large enough to
- * hide the worst case interrupt latency the system will encounter.  The DMA
- * RX driver adds to the output of the usart_info command a high water mark
- * of how many bytes were transferred out of this FIFO on any one interrupt.
- * This value can be used to correctly size the FIFO by setting the FIFO_SIZE
- * to something large, stress test the USART, and run usart_info.  After a
- * reasonable stress test the "DMA RX max_bytes" value will be a reasonable
- * size for the FIFO (perhaps +10% for safety).
- */
-#define USART_RX_DMA(CHANNEL, FIFO_SIZE)				\
-	((struct usart_rx_dma const) {					\
-		.usart_rx = {						\
-			.producer_ops = {				\
-				.read = NULL,				\
-			},						\
-									\
-			.init      = usart_rx_dma_init,			\
-			.interrupt = usart_rx_dma_interrupt,		\
-			.info      = USART_RX_DMA_INFO,			\
-		},							\
-									\
-		.state       = &((struct usart_rx_dma_state) {}),	\
-		 .fifo_buffer = ((uint8_t[FIFO_SIZE]) {}),		\
-		 .fifo_size   = FIFO_SIZE,				\
-		 .channel     = CHANNEL,				\
-	})
-
-/*
- * In RAM state required to manage DMA based transmission.
- */
-struct usart_rx_dma_state {
-	/*
-	 * Previous value of dma_bytes_done.  This will wrap when the DMA fills
-	 * the queue.
-	 */
-	size_t index;
-
-	/*
-	 * Maximum number of bytes transferred in any one RX interrupt.
-	 */
-	uint32_t max_bytes;
-};
-
-/*
- * Extension of the usart_rx struct to include required configuration for
- * DMA based transmission.
- */
-struct usart_rx_dma {
-	struct usart_rx usart_rx;
-
-	struct usart_rx_dma_state volatile *state;
-
-	uint8_t *fifo_buffer;
-	size_t  fifo_size;
-
-	enum dma_channel channel;
-};
-
-/*
- * Function pointers needed to initialize a usart_rx struct.  These shouldn't
- * be called in any other context as they assume that the producer or config
- * that they are passed was initialized with a complete usart_rx_dma struct.
- */
-void usart_rx_dma_init(struct usart_config const *config);
-void usart_rx_dma_interrupt(struct usart_config const *config);
-
-/*
- * Function pointers needed to initialize host command rx dma interrupt.
- * This should be only called from usart host command layer.
- */
-void usart_host_command_rx_dma_interrupt(struct usart_config const *config);
-
-/*
- * Debug function, used to print DMA RX statistics to the console.
- */
-void usart_rx_dma_info(struct usart_config const *config);
-
-#endif /* __CROS_EC_USART_RX_DMA_H */
diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f0.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c
deleted file mode 120000
index a756455f9b..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f3.c
+++ /dev/null
@@ -1 +0,0 @@
-usart_rx_interrupt.c
\ No newline at end of file
diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c
deleted file mode 100644
index 198c6dd180..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32f4.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32F0 and STM32F4 */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4)
-	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
-#endif
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c
deleted file mode 100644
index 24ca7a0487..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32l.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32L */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	/*
-	 * We have to check and clear the overrun error flag on STM32L because
-	 * we can't disable it.
-	 */
-	if (status & STM32_USART_SR_ORE) {
-		/*
-		 * In the unlikely event that the overrun error bit was set but
-		 * the RXNE bit was not (possibly because a read was done from
-		 * RDR without first reading the status register) we do a read
-		 * here to clear the overrun error bit.
-		 */
-		if (!(status & STM32_USART_SR_RXNE))
-			(void)STM32_USART_RDR(config->hw->base);
-
-		atomic_add((uint32_t *)&(config->state->rx_overrun), 1);
-	}
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c
deleted file mode 100644
index fa644b6baf..0000000000
--- a/chip/stm32/usart_rx_interrupt-stm32l5.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usart_rx_interrupt-stm32l.c"
diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c
deleted file mode 100644
index 3bc30d4aaf..0000000000
--- a/chip/stm32/usart_rx_interrupt.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
-
-#include "usart.h"
-
-#include "atomic.h"
-#include "common.h"
-#include "queue.h"
-#include "registers.h"
-
-static void usart_rx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
-	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
-}
-
-static void usart_rx_interrupt_handler(struct usart_config const *config)
-{
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
-
-	if (status & STM32_USART_SR_RXNE) {
-		uint8_t byte = STM32_USART_RDR(base);
-
-		if (!queue_add_unit(config->producer.queue, &byte))
-			atomic_add((uint32_t *)&(config->state->rx_dropped), 1);
-	}
-}
-
-struct usart_rx const usart_rx_interrupt = {
-	.producer_ops = {
-		/*
-		 * Nothing to do here, we either had enough space in the queue
-		 * when a character came in or we dropped it already.
-		 */
-		.read = NULL,
-	},
-
-	.init      = usart_rx_init,
-	.interrupt = usart_rx_interrupt_handler,
-	.info      = NULL,
-};
diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c
deleted file mode 100644
index 0c8e2c73d6..0000000000
--- a/chip/stm32/usart_tx_dma.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usart_tx_dma.h"
-
-#include "usart.h"
-#include "common.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-void usart_tx_dma_written(struct consumer const *consumer, size_t count)
-{
-	struct usart_config const *config =
-		DOWNCAST(consumer, struct usart_config, consumer);
-
-	task_trigger_irq(config->hw->irq);
-}
-
-void usart_tx_dma_init(struct usart_config const *config)
-{
-	struct usart_tx_dma const *dma_config =
-		DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx);
-
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TE;
-	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAT;
-
-	dma_config->state->dma_active = 0;
-}
-
-static void usart_tx_dma_start(struct usart_config const *config,
-			       struct usart_tx_dma const *dma_config)
-{
-	struct usart_tx_dma_state volatile *state = dma_config->state;
-	intptr_t                           base   = config->hw->base;
-
-	struct dma_option options = {
-		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_TDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT),
-	};
-
-	/*
-	 * Limit our DMA transfer.  If we didn't do this then it would be
-	 * possible to start a large DMA transfer of an entirely full buffer
-	 * that would hold up any additional writes to the TX queue
-	 * unnecessarily.
-	 */
-	state->chunk.count = MIN(state->chunk.count, dma_config->max_bytes);
-
-	dma_prepare_tx(&options, state->chunk.count, state->chunk.buffer);
-
-	state->dma_active = 1;
-
-	usart_clear_tc(config);
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TCIE;
-
-	dma_go(dma_get_channel(options.channel));
-}
-
-static void usart_tx_dma_stop(struct usart_config const *config,
-			      struct usart_tx_dma const *dma_config)
-{
-	dma_config->state->dma_active = 0;
-
-	STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_TCIE;
-}
-
-void usart_tx_dma_interrupt(struct usart_config const *config)
-{
-	struct usart_tx_dma const *dma_config =
-		DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx);
-	struct usart_tx_dma_state volatile *state = dma_config->state;
-
-	/*
-	 * If we have completed a DMA transaction, or if we haven't yet started
-	 * one then we clean up and start one now.
-	 */
-	if ((STM32_USART_SR(config->hw->base) & STM32_USART_SR_TC) ||
-	    !state->dma_active) {
-		struct queue const *queue = config->consumer.queue;
-
-		/*
-		 * Only advance the queue head (indicating that we have read
-		 * units from the queue if we had an active DMA transfer.
-		 */
-		if (state->dma_active)
-			queue_advance_head(queue, state->chunk.count);
-
-		state->chunk = queue_get_read_chunk(queue);
-
-		if (state->chunk.count)
-			usart_tx_dma_start(config, dma_config);
-		else
-			usart_tx_dma_stop(config, dma_config);
-	}
-}
diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h
deleted file mode 100644
index c17164e04a..0000000000
--- a/chip/stm32/usart_tx_dma.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * DMA based USART TX driver for STM32
- */
-#ifndef __CROS_EC_USART_TX_DMA_H
-#define __CROS_EC_USART_TX_DMA_H
-
-#include "consumer.h"
-#include "dma.h"
-#include "queue.h"
-#include "usart.h"
-
-/*
- * Construct a USART TX instance for DMA using the given DMA channel.
- *
- * This macro creates a new usart_tx_dma struct, complete with in RAM state,
- * the contained usart_tx struct can be used in initializing a usart_config
- * struct.
- *
- * CHANNEL is the DMA channel to be used for transmission.  This must be a
- * valid DMA channel for the USART peripheral and any alternate channel
- * mappings must be handled by the board specific code.
- *
- * MAX_BYTES is the maximum size in bytes of a single DMA transfer.  This
- * allows the board to tune how often the TX engine updates the queue state.
- * A larger number here could cause the queue to appear full for longer than
- * required because the queue isn't notified that it has been read from until
- * after the DMA transfer completes.
- */
-#define USART_TX_DMA(CHANNEL, MAX_BYTES)			\
-	((struct usart_tx_dma const) {				\
-		.usart_tx = {					\
-			.consumer_ops = {			\
-				.written = usart_tx_dma_written,\
-			},					\
-								\
-			.init      = usart_tx_dma_init,		\
-			.interrupt = usart_tx_dma_interrupt,	\
-			.info      = NULL,			\
-		},						\
-								\
-		.state     = &((struct usart_tx_dma_state){}),	\
-		.channel   = CHANNEL,				\
-		.max_bytes = MAX_BYTES,				\
-	})
-
-/*
- * In RAM state required to manage DMA based transmission.
- */
-struct usart_tx_dma_state {
-	/*
-	 * The current chunk of queue buffer being used for transmission.  Once
-	 * the transfer is complete, this is used to update the TX queue head
-	 * pointer as well.
-	 */
-	struct queue_chunk chunk;
-
-	/*
-	 * Flag indicating whether a DMA transfer is currently active.
-	 */
-	int dma_active;
-};
-
-/*
- * Extension of the usart_tx struct to include required configuration for
- * DMA based transmission.
- */
-struct usart_tx_dma {
-	struct usart_tx usart_tx;
-
-	struct usart_tx_dma_state volatile *state;
-
-	enum dma_channel channel;
-
-	size_t max_bytes;
-};
-
-/*
- * Function pointers needed to initialize a usart_tx struct.  These shouldn't
- * be called in any other context as they assume that the consumer or config
- * that they are passed was initialized with a complete usart_tx_dma struct.
- */
-void usart_tx_dma_written(struct consumer const *consumer, size_t count);
-void usart_tx_dma_flush(struct consumer const *consumer);
-void usart_tx_dma_init(struct usart_config const *config);
-void usart_tx_dma_interrupt(struct usart_config const *config);
-
-#endif /* __CROS_EC_USART_TX_DMA_H */
diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c
deleted file mode 100644
index d8d441ba1b..0000000000
--- a/chip/stm32/usart_tx_interrupt.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Interrupt based USART TX driver for STM32 */
-
-#include "usart.h"
-
-#include "common.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart_host_command.h"
-#include "util.h"
-
-typedef size_t (*remove_data_t)(struct usart_config const *config,
-				uint8_t *dest);
-
-static void usart_tx_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	STM32_USART_CR1(base) |= STM32_USART_CR1_TE;
-}
-
-static void usart_written(struct consumer const *consumer, size_t count)
-{
-	struct usart_config const *config =
-		DOWNCAST(consumer, struct usart_config, consumer);
-
-	/*
-	 * Enable USART interrupt.  This causes the USART interrupt handler to
-	 * start fetching from the TX queue if it wasn't already.
-	 */
-	if (count)
-		STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE;
-}
-
-static void usart_tx_interrupt_handler_common(
-		struct usart_config const *config,
-		remove_data_t remove_data)
-{
-	intptr_t base = config->hw->base;
-	uint8_t  byte;
-
-	if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE))
-		return;
-
-	if (remove_data(config, &byte)) {
-		STM32_USART_TDR(base) = byte;
-
-		/*
-		 * Make sure the TXE interrupt is enabled and that we won't go
-		 * into deep sleep.  This invocation of the USART interrupt
-		 * handler may have been manually triggered to start
-		 * transmission.
-		 */
-		disable_sleep(SLEEP_MASK_UART);
-
-		STM32_USART_CR1(base) |= STM32_USART_CR1_TXEIE;
-	} else {
-		/*
-		 * The TX queue is empty, disable the TXE interrupt and enable
-		 * deep sleep mode. The TXE interrupt will remain disabled
-		 * until a write call happens.
-		 */
-		enable_sleep(SLEEP_MASK_UART);
-
-		STM32_USART_CR1(base) &= ~STM32_USART_CR1_TXEIE;
-	}
-}
-
-static size_t queue_remove(struct usart_config const *config, uint8_t *dest)
-{
-	return queue_remove_unit(config->consumer.queue, (void *) dest);
-}
-
-static void usart_tx_interrupt_handler(struct usart_config const *config)
-{
-	usart_tx_interrupt_handler_common(config, &queue_remove);
-}
-
-void usart_tx_start(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	/* If interrupt is already enabled, nothing to do */
-	if (STM32_USART_CR1(base) & STM32_USART_CR1_TXEIE)
-		return;
-
-	disable_sleep(SLEEP_MASK_UART);
-	STM32_USART_CR1(base) |= (STM32_USART_CR1_TXEIE);
-
-	task_trigger_irq(config->hw->irq);
-}
-
-struct usart_tx const usart_tx_interrupt = {
-	.consumer_ops = {
-		.written = usart_written,
-	},
-
-	.init      = usart_tx_init,
-	.interrupt = usart_tx_interrupt_handler,
-	.info      = NULL,
-};
-
-#if defined(CONFIG_USART_HOST_COMMAND)
-
-static void usart_host_command_tx_interrupt_handler(
-		struct usart_config const *config)
-{
-	usart_tx_interrupt_handler_common(config,
-		&usart_host_command_tx_remove_data);
-}
-
-struct usart_tx const usart_host_command_tx_interrupt = {
-	.consumer_ops = {
-		.written = usart_written,
-	},
-
-	.init      = usart_tx_init,
-	.interrupt = usart_host_command_tx_interrupt_handler,
-	.info      = NULL,
-};
-#endif /* CONFIG_USART_HOST_COMMAND */
diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c
deleted file mode 100644
index 08c0a17455..0000000000
--- a/chip/stm32/usb-stm32f0.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F0 Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= BIT(15) /* DPPU */;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~BIT(15) /* DPPU */;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c
deleted file mode 100644
index 2376d00b41..0000000000
--- a/chip/stm32/usb-stm32f3.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F3 Family specific USB functionality
- */
-
-#include "usb-stm32f3.h"
-
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	usb_board_connect();
-}
-
-void usb_disconnect(void)
-{
-	usb_board_disconnect();
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h
deleted file mode 100644
index 196c43a53a..0000000000
--- a/chip/stm32/usb-stm32f3.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32F3 Family specific USB functionality
- */
-
-/*
- * A device that uses an STM32F3 part will need to define these two functions
- * which are used to connect and disconnect the device from the USB bus.  This
- * is usually accomplished by enabling a pullup on the DP USB line.  The pullup
- * should be enabled by default so that the STM32 will enumerate correctly in
- * DFU mode (which doesn't know how to enable the DP pullup, so it assumes that
- * the pullup is always there).
- */
-void usb_board_connect(void);
-void usb_board_disconnect(void);
diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c
deleted file mode 100644
index b4402f670d..0000000000
--- a/chip/stm32/usb-stm32g4.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32G4 Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c
deleted file mode 100644
index bb9838531b..0000000000
--- a/chip/stm32/usb-stm32l.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32L Family specific USB functionality
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_SYSCFG_PMC |= 1;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_SYSCFG_PMC &= ~1;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c
deleted file mode 100644
index 9eaa622815..0000000000
--- a/chip/stm32/usb-stm32l5.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "system.h"
-#include "usb_api.h"
-
-void usb_connect(void)
-{
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
-}
-
-void usb_disconnect(void)
-{
-	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c
deleted file mode 100644
index 7429832f10..0000000000
--- a/chip/stm32/usb-stream.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "config.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usart.h"
-#include "usb_hw.h"
-#include "usb-stream.h"
-
-static size_t rx_read(struct usb_stream_config const *config)
-{
-	uintptr_t address = btable_ep[config->endpoint].rx_addr;
-	size_t count = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
-
-	/*
-	 * Only read the received USB packet if there is enough space in the
-	 * receive queue.
-	 */
-	if (count > queue_space(config->producer.queue))
-		return 0;
-
-	return queue_add_memcpy(config->producer.queue,
-				(void *) address,
-				count,
-				memcpy_from_usbram);
-}
-
-static size_t tx_write(struct usb_stream_config const *config)
-{
-	uintptr_t address = btable_ep[config->endpoint].tx_addr;
-	size_t    count   = queue_remove_memcpy(config->consumer.queue,
-						(void *) address,
-						config->tx_size,
-						memcpy_to_usbram);
-
-	btable_ep[config->endpoint].tx_count = count;
-
-	return count;
-}
-
-static int tx_valid(struct usb_stream_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) == EP_TX_VALID;
-}
-
-static int rx_valid(struct usb_stream_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID;
-}
-
-static int rx_disabled(struct usb_stream_config const *config)
-{
-	return config->state->rx_disabled;
-}
-
-static void usb_read(struct producer const *producer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(producer, struct usb_stream_config, producer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-static void usb_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(consumer, struct usb_stream_config, consumer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-struct producer_ops const usb_stream_producer_ops = {
-	.read = usb_read,
-};
-
-struct consumer_ops const usb_stream_consumer_ops = {
-	.written = usb_written,
-};
-
-void usb_stream_deferred(struct usb_stream_config const *config)
-{
-	if (!tx_valid(config) && tx_write(config))
-		STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-
-	if (!rx_valid(config) && !rx_disabled(config) && rx_read(config))
-		STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-void usb_stream_tx(struct usb_stream_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-void usb_stream_rx(struct usb_stream_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-static usb_uint usb_ep_rx_size(size_t bytes)
-{
-	if (bytes < 64)
-		return bytes << 9;
-	else
-		return 0x8000 | ((bytes - 32) << 5);
-}
-
-void usb_stream_event(struct usb_stream_config const *config,
-		      enum usb_ep_event evt)
-{
-	int i;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	i = config->endpoint;
-
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
-	btable_ep[i].tx_count = 0;
-
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
-	btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size);
-
-	config->state->rx_waiting = 0;
-
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (2 <<  4) | /* TX NAK */
-			   (0 <<  9) | /* Bulk EP */
-			   (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID));
-}
-
-int usb_usart_interface(struct usb_stream_config const *config,
-			struct usart_config const *usart,
-			int interface,
-			usb_uint *rx_buf, usb_uint *tx_buf)
-{
-	struct usb_setup_packet req;
-
-	usb_read_setup_packet(rx_buf, &req);
-
-	if (req.bmRequestType != (USB_DIR_OUT |
-				  USB_TYPE_VENDOR |
-				  USB_RECIP_INTERFACE))
-		return -1;
-
-	if (req.wIndex  != interface ||
-	    req.wLength != 0)
-		return -1;
-
-	switch (req.bRequest) {
-	/* Set parity. */
-	case USB_USART_SET_PARITY:
-		usart_set_parity(usart, req.wValue);
-		break;
-	case USB_USART_SET_BAUD:
-		usart_set_baud(usart, req.wValue * 100);
-		break;
-
-	/* TODO(nsanders): support reading parity. */
-	/* TODO(nsanders): support reading baud. */
-	default:
-		return -1;
-	}
-
-	btable_ep[0].tx_count = 0;
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT);
-	return 0;
-}
diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h
deleted file mode 100644
index 915d8905cd..0000000000
--- a/chip/stm32/usb-stream.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_STREAM_H
-#define __CROS_EC_USB_STREAM_H
-
-#if defined(CHIP_FAMILY_STM32F4)
-#include "usb_dwc_stream.h"
-#else
-
-/* STM32 USB STREAM driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "consumer.h"
-#include "hooks.h"
-#include "producer.h"
-#include "queue.h"
-#include "usart.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-#include <stdint.h>
-
-/*
- * Per-USB stream state stored in RAM.  Zero initialization of this structure
- * by the BSS initialization leaves it in a valid and correctly initialized
- * state, so there is no need currently for a usb_stream_init style function.
- */
-struct usb_stream_state {
-	/*
-	 * Flag indicating that there is a full RX buffer in the USB packet RAM
-	 * that we were not able to move into the RX queue because there was
-	 * not enough room when the packet was initially received.  The
-	 * producer read operation checks this flag so that once there is
-	 * room in the queue it can copy the RX buffer into the queue and
-	 * restart USB reception by marking the RX buffer as VALID.
-	 */
-	int rx_waiting;
-	/*
-	 * Flag indicating that the incoming data on the USB link are discarded.
-	 */
-	int rx_disabled;
-};
-
-/*
- * Compile time Per-USB stream configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB stream.  This structure binds
- * together all information required to operate a USB stream.
- */
-struct usb_stream_config {
-	/*
-	 * Pointer to usb_stream_state structure.  The state structure
-	 * maintains per USB stream information.
-	 */
-	struct usb_stream_state volatile *state;
-
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-
-	/*
-	 * Deferred function to call to handle USB and Queue request.
-	 */
-	const struct deferred_data *deferred;
-
-	size_t rx_size;
-	size_t tx_size;
-
-	usb_uint *rx_ram;
-	usb_uint *tx_ram;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * These function tables are defined by the USB Stream driver and are used to
- * initialize the consumer and producer in the usb_stream_config.
- */
-extern struct consumer_ops const usb_stream_consumer_ops;
-extern struct producer_ops const usb_stream_producer_ops;
-
-/*
- * Convenience macro for defining USB streams and their associated state and
- * buffers.
- *
- * NAME is used to construct the names of the packet RAM buffers, trampoline
- * functions, usb_stream_state struct, and usb_stream_config struct, the
- * latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * stream.
- *
- * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the
- * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields
- * respectively in the USB interface descriptor.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate
- * for the RX and TX packets respectively.  The valid values for these
- * parameters are dictated by the USB peripheral.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver
- * should write to and read from respectively.
- */
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE);
- * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE);
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(RX_SIZE > 0);					\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((RX_SIZE <   64 && (RX_SIZE & 0x01) == 0) ||	\
-		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));	\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-									\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \
-	static struct usb_stream_state CONCAT2(NAME, _state);		\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_stream_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state),			\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.rx_size   = RX_SIZE,					\
-		.tx_size   = TX_SIZE,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &usb_stream_consumer_ops,		\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &usb_stream_producer_ops,		\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_stream_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_stream_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_stream_deferred(&NAME); }
-
-/* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
-
-/* Declare a utility interface for setting parity/baud. */
-#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)			\
-	static int CONCAT2(NAME,  _interface_)(usb_uint *rx_buf,	\
-					      usb_uint *tx_buf)		\
-	{ return usb_usart_interface(&NAME, &USART_CFG, INTERFACE,	\
-					rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_))
-
-/* This is a medium version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG_USART_IFACE(NAME,				\
-				      INTERFACE,			\
-				      INTERFACE_NAME,			\
-				      ENDPOINT,				\
-				      RX_SIZE,				\
-				      TX_SIZE,				\
-				      RX_QUEUE,				\
-				      TX_QUEUE,				\
-				      USART_CFG)			\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE);				\
-	USB_USART_IFACE(NAME, INTERFACE, USART_CFG)
-
-/*
- * Handle USB and Queue request in a deferred callback.
- */
-void usb_stream_deferred(struct usb_stream_config const *config);
-
-/*
- * Handle control interface requests.
- */
-enum usb_usart {
-	USB_USART_REQ_PARITY = 0,
-	USB_USART_SET_PARITY = 1,
-	USB_USART_REQ_BAUD = 2,
-	USB_USART_SET_BAUD = 3,
-};
-
-/*
- * baud rate is req/set in multiples of 100, to avoid overflowing
- * 16-bit integer.
- */
-#define USB_USART_BAUD_MULTIPLIER 100
-
-int usb_usart_interface(struct usb_stream_config const *config,
-		    struct usart_config const *usart,
-		    int interface, usb_uint *rx_buf, usb_uint *tx_buf);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB stream driver.
- */
-void usb_stream_tx(struct usb_stream_config const *config);
-void usb_stream_rx(struct usb_stream_config const *config);
-void usb_stream_event(struct usb_stream_config const *config,
-		      enum usb_ep_event evt);
-
-#endif /* defined(CHIP_FAMILY_STM32F4) */
-#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
deleted file mode 100644
index 0077815a27..0000000000
--- a/chip/stm32/usb.c
+++ /dev/null
@@ -1,957 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#ifdef CONFIG_USB_BOS
-/* v2.10 (vs 2.00) BOS Descriptor provided */
-#define USB_DEV_BCDUSB 0x0210
-#else
-#define USB_DEV_BCDUSB 0x0200
-#endif
-
-#ifndef USB_DEV_CLASS
-#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE
-#endif
-
-#ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */
-#endif
-
-#ifndef CONFIG_USB_SERIALNO
-#define USB_STR_SERIALNO 0
-#else
-static int usb_load_serial(void);
-#endif
-
-#define USB_RESUME_TIMEOUT_MS 3000
-
-/* USB Standard Device Descriptor */
-static const struct usb_device_descriptor dev_desc = {
-	.bLength = USB_DT_DEVICE_SIZE,
-	.bDescriptorType = USB_DT_DEVICE,
-	.bcdUSB = USB_DEV_BCDUSB,
-	.bDeviceClass = USB_DEV_CLASS,
-	.bDeviceSubClass = 0x00,
-	.bDeviceProtocol = 0x00,
-	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = CONFIG_USB_VID,
-	.idProduct = CONFIG_USB_PID,
-	.bcdDevice = CONFIG_USB_BCD_DEV,
-	.iManufacturer = USB_STR_VENDOR,
-	.iProduct = USB_STR_PRODUCT,
-	.iSerialNumber = USB_STR_SERIALNO,
-	.bNumConfigurations = 1
-};
-
-/* USB Configuration Descriptor */
-const struct usb_config_descriptor USB_CONF_DESC(conf) = {
-	.bLength = USB_DT_CONFIG_SIZE,
-	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD, /* no of returned bytes, set at runtime */
-	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,
-	.iConfiguration = USB_STR_VERSION,
-	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
-#endif
-	,
-	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
-};
-
-const uint8_t usb_string_desc[] = {
-	4, /* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04 /* LangID = 0x0409: U.S. English */
-};
-
-/* Endpoint table in USB controller RAM */
-struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable;
-/* Control endpoint (EP0) buffers */
-static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-
-#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx))
-
-static int set_addr;
-/* remaining size of descriptor data to transfer */
-static int desc_left;
-/* pointer to descriptor data if any */
-static const uint8_t *desc_ptr;
-/* interface that should handle the next tx transaction */
-static uint8_t iface_next = USB_IFACE_COUNT;
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-/* remote wake up feature enabled */
-static int remote_wakeup_enabled;
-#endif
-
-void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet)
-{
-	packet->bmRequestType = buffer[0] & 0xff;
-	packet->bRequest      = buffer[0] >> 8;
-	packet->wValue        = buffer[1];
-	packet->wIndex        = buffer[2];
-	packet->wLength       = buffer[3];
-}
-
-struct usb_descriptor_patch {
-	const void *address;
-	uint16_t data;
-};
-
-static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT];
-
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data)
-{
-	desc_patches[type].address = address;
-	desc_patches[type].data = data;
-}
-
-void *memcpy_to_usbram_ep0_patch(const void *src, size_t n)
-{
-	int i;
-	void *ret;
-
-	ret = memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), src, n);
-
-	for (i = 0; i < USB_DESC_PATCH_COUNT; i++) {
-		unsigned int offset = desc_patches[i].address - src;
-
-		if (offset >= n)
-			continue;
-
-		memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset),
-			&desc_patches[i].data, sizeof(desc_patches[i].data));
-	}
-
-	return ret;
-}
-
-static void ep0_send_descriptor(const uint8_t *desc, int len,
-				uint16_t fixup_size)
-{
-	/* do not send more than what the host asked for */
-	len = MIN(ep0_buf_rx[3], len);
-	/*
-	 * if we cannot transmit everything at once,
-	 * keep the remainder for the next IN packet
-	 */
-	if (len >= USB_MAX_PACKET_SIZE) {
-		desc_left = len - USB_MAX_PACKET_SIZE;
-		desc_ptr = desc + USB_MAX_PACKET_SIZE;
-		len = USB_MAX_PACKET_SIZE;
-	}
-	memcpy_to_usbram_ep0_patch(desc, len);
-	if (fixup_size) /* set the real descriptor size */
-		ep0_buf_tx[1] = fixup_size;
-	btable_ep[0].tx_count = len;
-	/* send the null OUT transaction if the transfer is complete */
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			desc_left ? 0 : EP_STATUS_OUT);
-}
-
-/* Requests on the control endpoint (aka EP0) */
-static void ep0_rx(void)
-{
-	uint16_t req = ep0_buf_rx[0]; /* bRequestType | bRequest */
-
-	/* reset any incomplete descriptor transfer */
-	desc_ptr = NULL;
-	iface_next = USB_IFACE_COUNT;
-
-	/* interface specific requests */
-	if ((req & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
-		uint8_t iface = ep0_buf_rx[2] & 0xff;
-		if (iface < USB_IFACE_COUNT) {
-			int ret;
-
-			ret = usb_iface_request[iface](ep0_buf_rx, ep0_buf_tx);
-			if (ret < 0)
-				goto unknown_req;
-			if (ret == 1)
-				iface_next = iface;
-			return;
-		}
-	}
-	/* vendor specific request */
-	if ((req & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
-#ifdef CONFIG_WEBUSB_URL
-		uint8_t b_req = req >> 8; /* bRequest in the transfer */
-		uint16_t idx = ep0_buf_rx[2]; /* wIndex in the transfer */
-
-		if (b_req == 0x01 && idx == WEBUSB_REQ_GET_URL) {
-			int len = *(uint8_t *)webusb_url;
-
-			ep0_send_descriptor(webusb_url, len, 0);
-			return;
-		}
-#endif
-		goto unknown_req;
-	}
-
-	/* TODO check setup bit ? */
-	if (req == (USB_DIR_IN | (USB_REQ_GET_DESCRIPTOR << 8))) {
-		uint8_t type = ep0_buf_rx[1] >> 8;
-		uint8_t idx = ep0_buf_rx[1] & 0xff;
-		const uint8_t *desc;
-		int len;
-
-		switch (type) {
-		case USB_DT_DEVICE: /* Setup : Get device descriptor */
-			desc = (void *)&dev_desc;
-			len = sizeof(dev_desc);
-			break;
-		case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */
-			desc = __usb_desc;
-			len = USB_DESC_SIZE;
-			break;
-#ifdef CONFIG_USB_BOS
-		case USB_DT_BOS: /* Setup : Get BOS descriptor */
-			desc = bos_ctx.descp;
-			len = bos_ctx.size;
-			break;
-#endif
-		case USB_DT_STRING: /* Setup : Get string descriptor */
-			if (idx >= USB_STR_COUNT)
-				/* The string does not exist : STALL */
-				goto unknown_req;
-#ifdef CONFIG_USB_SERIALNO
-			if (idx == USB_STR_SERIALNO)
-				desc = (uint8_t *)usb_serialno_desc;
-			else
-#endif
-				desc = usb_strings[idx];
-			len = desc[0];
-			break;
-		case USB_DT_DEVICE_QUALIFIER: /* Get device qualifier desc */
-			/* Not high speed : STALL next IN used as handshake */
-			goto unknown_req;
-		default: /* unhandled descriptor */
-			goto unknown_req;
-		}
-		ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ?
-						USB_DESC_SIZE : 0);
-	} else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) {
-		uint16_t data = 0;
-		/* Get status */
-#ifdef CONFIG_USB_SELF_POWERED
-		data |= USB_REQ_GET_STATUS_SELF_POWERED;
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		if (remote_wakeup_enabled)
-			data |= USB_REQ_GET_STATUS_REMOTE_WAKEUP;
-#endif
-		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2);
-		btable_ep[0].tx_count = 2;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			  EP_STATUS_OUT /*null OUT transaction */);
-	} else if ((req & 0xff) == USB_DIR_OUT) {
-		switch (req >> 8) {
-		case USB_REQ_SET_FEATURE:
-		case USB_REQ_CLEAR_FEATURE:
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-			if (ep0_buf_rx[1] ==
-					USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
-				remote_wakeup_enabled =
-					((req >> 8) == USB_REQ_SET_FEATURE);
-				btable_ep[0].tx_count = 0;
-				STM32_TOGGLE_EP(0, EP_TX_RX_MASK,
-						EP_TX_RX_VALID, 0);
-				break;
-			}
-#endif
-			goto unknown_req;
-		case USB_REQ_SET_ADDRESS:
-			/* set the address after we got IN packet handshake */
-			set_addr = ep0_buf_rx[1] & 0xff;
-			/* need null IN transaction -> TX Valid */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-			break;
-		case USB_REQ_SET_CONFIGURATION:
-			/* uint8_t cfg = ep0_buf_rx[1] & 0xff; */
-			/* null IN for handshake */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-			break;
-		default: /* unhandled request */
-			goto unknown_req;
-		}
-
-	} else {
-		goto unknown_req;
-	}
-
-	return;
-unknown_req:
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_RX_VALID | EP_TX_STALL, 0);
-}
-
-static void ep0_tx(void)
-{
-	if (set_addr) {
-		STM32_USB_DADDR = set_addr | 0x80;
-		set_addr = 0;
-		CPRINTF("SETAD %02x\n", STM32_USB_DADDR);
-	}
-	if (desc_ptr) {
-		/* we have an on-going descriptor transfer */
-		int len = MIN(desc_left, USB_MAX_PACKET_SIZE);
-		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, desc_ptr, len);
-		btable_ep[0].tx_count = len;
-		desc_left -= len;
-		desc_ptr += len;
-		STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID,
-				desc_left ? 0 : EP_STATUS_OUT);
-		/* send the null OUT transaction if the transfer is complete */
-		return;
-	}
-	if (iface_next < USB_IFACE_COUNT) {
-		int ret;
-
-		ret = usb_iface_request[iface_next](NULL, ep0_buf_tx);
-		if (ret < 0)
-			goto error;
-		if (ret == 0)
-			iface_next = USB_IFACE_COUNT;
-		return;
-	}
-
-error:
-	STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-static void ep0_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	STM32_USB_EP(0) = BIT(9) /* control EP */ |
-			  (2 << 4) /* TX NAK */ |
-			  (3 << 12) /* RX VALID */;
-
-	btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx);
-	btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx);
-	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10);
-	btable_ep[0].tx_count = 0;
-}
-USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event);
-
-static void usb_reset(void)
-{
-	int ep;
-
-	for (ep = 0; ep < USB_EP_COUNT; ep++)
-		usb_ep_event[ep](USB_EVENT_RESET);
-
-	/*
-	 * set the default address : 0
-	 * as we are not configured yet
-	 */
-	STM32_USB_DADDR = 0 | 0x80;
-	CPRINTF("RST EP0 %04x\n", STM32_USB_EP(0));
-}
-
-#ifdef CONFIG_USB_SUSPEND
-static void usb_pm_change_notify_hooks(void)
-{
-	hook_notify(HOOK_USB_PM_CHANGE);
-}
-DECLARE_DEFERRED(usb_pm_change_notify_hooks);
-
-/* See RM0091 Reference Manual 30.5.5 Suspend/Resume events */
-static void usb_suspend(void)
-{
-	CPRINTF("SUS%d\n", remote_wakeup_enabled);
-
-	/*
-	 * usb_suspend can be called from hook task, make sure no interrupt is
-	 * modifying CNTR at the same time.
-	 */
-	interrupt_disable();
-	/* Set FSUSP bit to activate suspend mode */
-	STM32_USB_CNTR |= STM32_USB_CNTR_FSUSP;
-
-	/* Set USB low power mode */
-	STM32_USB_CNTR |= STM32_USB_CNTR_LP_MODE;
-	interrupt_enable();
-
-	clock_enable_module(MODULE_USB, 0);
-
-	/* USB is not in use anymore, we can (hopefully) sleep now. */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-}
-
-/*
- * SOF was received (set in interrupt), reset in usb_resume in the
- * unexpected state case.
- */
-static volatile int sof_received;
-
-static void usb_resume_deferred(void)
-{
-	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received);
-	if (sof_received == 0 && (state == 2 || state == 3))
-		usb_suspend();
-	else
-		hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-}
-DECLARE_DEFERRED(usb_resume_deferred);
-
-static void usb_resume(void)
-{
-	uint32_t state;
-
-	clock_enable_module(MODULE_USB, 1);
-
-	/* Clear FSUSP bit to exit suspend mode */
-	STM32_USB_CNTR &= ~STM32_USB_CNTR_FSUSP;
-
-	/* USB is in use again */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR);
-
-	/*
-	 * Reference manual tells we should go back to sleep if state is 10 or
-	 * 11. However, setting FSUSP and LP_MODE in this interrupt routine
-	 * seems to lock the USB controller (see b/35775088 and b/71688150).
-	 * Instead, we do it in a deferred routine. The host must assert the
-	 * reset condition for 20ms, so reading D+/D- after ~3ms should be safe
-	 * (there is no chance we end up sampling during a bus transaction).
-	 */
-	if (state == 2 || state == 3) {
-		/*
-		 * This function is already called from interrupt context so
-		 * there is no risk of race here.
-		 */
-		sof_received = 0;
-		STM32_USB_CNTR |= STM32_USB_CNTR_SOFM;
-		hook_call_deferred(&usb_resume_deferred_data, 3 * MSEC);
-	} else {
-		hook_call_deferred(&usb_pm_change_notify_hooks_data, 0);
-	}
-}
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-/*
- * Makes sure usb_wake is only run once. When 0, wake is in progress.
- */
-static volatile int usb_wake_done = 1;
-
-/*
- * ESOF counter (incremented in interrupt), RESUME bit is cleared when
- * this reaches 0. Also used to detect resume timeout.
- */
-static volatile int esof_count;
-
-__attribute__((weak))
-void board_usb_wake(void)
-{
-	/* Side-band USB wake, do nothing by default. */
-}
-
-/* Called 10ms after usb_wake started. */
-static void usb_wake_deferred(void)
-{
-	if (esof_count == 3) {
-		/*
-		 * If we reach here, it means that we are not counting ESOF/SOF
-		 * properly (either of these interrupts should occur every 1ms).
-		 * This should never happen if we implemented the resume logic
-		 * correctly.
-		 *
-		 * We reset the controller in that case, which recovers the
-		 * interface.
-		 */
-		CPRINTF("USB stuck\n");
-#if defined(STM32_RCC_APB1RSTR2_USBFSRST)
-		STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST;
-		STM32_RCC_APB1RSTR2 &= STM32_RCC_APB1RSTR2_USBFSRST;
-#else
-		STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB;
-		STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB;
-#endif
-		usb_init();
-	}
-}
-DECLARE_DEFERRED(usb_wake_deferred);
-
-void usb_wake(void)
-{
-	if (!remote_wakeup_enabled ||
-	    !(STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)) {
-		/*
-		 * USB wake not enabled, or already woken up, or already waking
-		 * up, nothing to do.
-		 */
-		return;
-	}
-
-	/* Only allow one caller at a time. */
-	if (!atomic_clear((int *)&usb_wake_done))
-		return;
-
-	CPRINTF("WAKE\n");
-
-	/*
-	 * Sometimes the USB controller gets stuck, and does not count SOF/ESOF
-	 * frames anymore, detect that.
-	 */
-	hook_call_deferred(&usb_wake_deferred_data, 10 * MSEC);
-
-	/*
-	 * Set RESUME bit for 1 to 15 ms, then clear it. We ask the interrupt
-	 * routine to count 3 ESOF interrupts, which should take between
-	 * 2 and 3 ms.
-	 */
-	esof_count = 3;
-
-	/* STM32_USB_CNTR can also be updated from interrupt context. */
-	interrupt_disable();
-	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME |
-		STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM;
-	interrupt_enable();
-
-	/* Try side-band wake as well. */
-	board_usb_wake();
-}
-#endif
-
-int usb_is_suspended(void)
-{
-	/* Either hardware block is suspended... */
-	if (STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)
-		return 1;
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	/* ... or we are currently waking up. */
-	if (!usb_wake_done)
-		return 1;
-#endif
-
-	return 0;
-}
-
-int usb_is_remote_wakeup_enabled(void)
-{
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	return remote_wakeup_enabled;
-#else
-	return 0;
-#endif
-}
-#endif /* CONFIG_USB_SUSPEND */
-
-#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_USB_REMOTE_WAKEUP)
-/*
- * Called by usb_interrupt when usb_wake is asking us to count esof_count ESOF
- * interrupts (one per millisecond), then disable RESUME, then wait for resume
- * to complete.
- */
-static void usb_interrupt_handle_wake(uint16_t status)
-{
-	int state;
-	int good;
-
-	esof_count--;
-
-	/* Keep counting. */
-	if (esof_count > 0)
-		return;
-
-	/* Clear RESUME bit. */
-	if (esof_count == 0)
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME;
-
-	/* Then count down until state is resumed. */
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-				>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
-
-	/*
-	 * state 2, or receiving an SOF, means resume
-	 * completed successfully.
-	 */
-	good = (status & STM32_USB_ISTR_SOF) || (state == 2);
-
-	/* Either: state is ready, or we timed out. */
-	if (good || state == 3 || esof_count <= -USB_RESUME_TIMEOUT_MS) {
-		int ep;
-
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM;
-		usb_wake_done = 1;
-		if (!good) {
-			CPRINTF("wake error: cnt=%d state=%d\n",
-				esof_count, state);
-			usb_suspend();
-			return;
-		}
-
-		CPRINTF("RSMOK%d %d\n",	-esof_count, state);
-
-		for (ep = 1; ep < USB_EP_COUNT; ep++)
-			usb_ep_event[ep](USB_EVENT_DEVICE_RESUME);
-	}
-}
-#endif /* CONFIG_USB_SUSPEND && CONFIG_USB_REMOTE_WAKEUP */
-
-void usb_interrupt(void)
-{
-	uint16_t status = STM32_USB_ISTR;
-
-	if (status & STM32_USB_ISTR_RESET)
-		usb_reset();
-
-#ifdef CONFIG_USB_SUSPEND
-	if (status & STM32_USB_ISTR_SOF) {
-		sof_received = 1;
-		/*
-		 * The wake handler also only cares about the _first_ SOF that
-		 * is received, so we can disable that interrupt.
-		 */
-		STM32_USB_CNTR &= ~STM32_USB_CNTR_SOFM;
-	}
-
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-	if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) &&
-			!usb_wake_done)
-		usb_interrupt_handle_wake(status);
-#endif
-
-	if (status & STM32_USB_ISTR_SUSP)
-		usb_suspend();
-
-	if (status & STM32_USB_ISTR_WKUP)
-		usb_resume();
-#endif
-
-	if (status & STM32_USB_ISTR_CTR) {
-		int ep = status & STM32_USB_ISTR_EP_ID_MASK;
-		if (ep < USB_EP_COUNT) {
-			if (status & STM32_USB_ISTR_DIR)
-				usb_ep_rx[ep]();
-			else
-				usb_ep_tx[ep]();
-		}
-		/* TODO: do it in a USB task */
-		/* task_set_event(, 1 << ep_task); */
-	}
-
-	/* ack only interrupts that we handled */
-	STM32_USB_ISTR = ~status;
-}
-DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1);
-
-void usb_init(void)
-{
-	/* Enable USB device clock, possibly increasing system clock to 48MHz */
-	clock_enable_module(MODULE_USB, 1);
-
-	/* configure the pinmux */
-	gpio_config_module(MODULE_USB, 1);
-
-	/* power on sequence */
-
-	/* keep FRES (USB reset) and remove PDWN (power down) */
-	STM32_USB_CNTR = STM32_USB_CNTR_FRES;
-	udelay(1); /* startup time */
-	/* reset FRES and keep interrupts masked */
-	STM32_USB_CNTR = 0x00;
-	/* clear pending interrupts */
-	STM32_USB_ISTR = 0;
-
-	/* set descriptors table offset in dedicated SRAM */
-	STM32_USB_BTABLE = 0;
-
-	/* EXTI18 is USB wake up interrupt */
-	/* STM32_EXTI_RTSR |= BIT(18); */
-	/* STM32_EXTI_IMR |= BIT(18); */
-
-	/* Enable interrupt handlers */
-	task_enable_irq(STM32_IRQ_USB_LP);
-	/* set interrupts mask : reset/correct transfer/errors */
-	STM32_USB_CNTR = STM32_USB_CNTR_CTRM |
-			 STM32_USB_CNTR_PMAOVRM |
-			 STM32_USB_CNTR_ERRM |
-#ifdef CONFIG_USB_SUSPEND
-			 STM32_USB_CNTR_WKUPM |
-			 STM32_USB_CNTR_SUSPM |
-#endif
-			 STM32_USB_CNTR_RESETM;
-
-#ifdef CONFIG_USB_SERIALNO
-	usb_load_serial();
-#endif
-#ifndef CONFIG_USB_INHIBIT_CONNECT
-	usb_connect();
-#endif
-
-	CPRINTF("USB init done\n");
-}
-
-#ifndef CONFIG_USB_INHIBIT_INIT
-DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT);
-#endif
-
-void usb_release(void)
-{
-	/* signal disconnect to host */
-	usb_disconnect();
-
-	/* power down USB */
-	STM32_USB_CNTR = 0;
-
-	/* disable interrupt handlers */
-	task_disable_irq(STM32_IRQ_USB_LP);
-
-	/* unset pinmux */
-	gpio_config_module(MODULE_USB, 0);
-
-	/* disable USB device clock, possibly slowing down system clock */
-	clock_enable_module(MODULE_USB, 0);
-}
-/* ensure the host disconnects and reconnects over a sysjump */
-DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT);
-
-int usb_is_enabled(void)
-{
-	return clock_is_module_enabled(MODULE_USB);
-}
-
-void *memcpy_to_usbram(void *dest, const void *src, size_t n)
-{
-	int       unaligned =                 (((uintptr_t) dest) & 1);
-	usb_uint *d         = &__usb_ram_start[((uintptr_t) dest) / 2];
-	uint8_t  *s         = (uint8_t *) src;
-	int       i;
-
-	/*
-	 * Handle unaligned leading byte via read/modify/write.
-	 */
-	if (unaligned && n) {
-		*d = (*d & ~0xff00) | (*s << 8);
-		n--;
-		s++;
-		d++;
-	}
-
-	for (i = 0; i < n / 2; i++, s += 2)
-		*d++ = (s[1] << 8) | s[0];
-
-	/*
-	 * There is a trailing byte to write into a final USB packet memory
-	 * location, use a read/modify/write to be safe.
-	 */
-	if (n & 1)
-		*d = (*d & ~0x00ff) | *s;
-
-	return dest;
-}
-
-void *memcpy_from_usbram(void *dest, const void *src, size_t n)
-{
-	int             unaligned =                 (((uintptr_t) src) & 1);
-	usb_uint const *s         = &__usb_ram_start[((uintptr_t) src) / 2];
-	uint8_t        *d         = (uint8_t *) dest;
-	int             i;
-
-	if (unaligned && n) {
-		*d = *s >> 8;
-		n--;
-		s++;
-		d++;
-	}
-
-	for (i = 0; i < n / 2; i++) {
-		usb_uint value = *s++;
-
-		*d++ = (value >> 0) & 0xff;
-		*d++ = (value >> 8) & 0xff;
-	}
-
-	if (n & 1)
-		*d = *s;
-
-	return dest;
-}
-
-#ifdef CONFIG_USB_SERIALNO
-/* This will be subbed into USB_STR_SERIALNO. */
-struct usb_string_desc *usb_serialno_desc =
-	USB_WR_STRING_DESC(DEFAULT_SERIALNO);
-
-/* Update serial number */
-static int usb_set_serial(const char *serialno)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	int i;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Convert into unicode usb string desc. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++) {
-		sd->_data[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	/* Count wchars (w/o null terminator) plus size & type bytes. */
-	sd->_len = (i * 2) + 2;
-	sd->_type = USB_DT_STRING;
-
-	return EC_SUCCESS;
-}
-
-/* Retrieve serial number from pstate flash. */
-static int usb_load_serial(void)
-{
-	const char *serialno;
-	int rv;
-
-	serialno = board_read_serial();
-	if (!serialno)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = usb_set_serial(serialno);
-	return rv;
-}
-
-/* Save serial number into pstate region. */
-static int usb_save_serial(const char *serialno)
-{
-	int rv;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Save this new serial number to flash. */
-	rv = board_write_serial(serialno);
-	if (rv)
-		return rv;
-
-	/* Load this new serial number to memory. */
-	rv = usb_load_serial();
-	return rv;
-}
-
-static int command_serialno(int argc, char **argv)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	char buf[CONFIG_SERIALNO_LEN];
-	int rv = EC_SUCCESS;
-	int i;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving serial number\n");
-			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading serial number\n");
-			rv = usb_load_serial();
-		} else
-			return EC_ERROR_INVAL;
-	}
-
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++)
-		buf[i] = sd->_data[i];
-	ccprintf("Serial number: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-
-#endif  /* CONFIG_USB_SERIALNO */
-
-#ifdef CONFIG_MAC_ADDR
-
-/* Save MAC address into pstate region. */
-static int usb_save_mac_addr(const char *mac_addr)
-{
-	int rv;
-
-	if (!mac_addr) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Save this new MAC address to flash. */
-	rv = board_write_mac_addr(mac_addr);
-	if (rv) {
-		return rv;
-	}
-
-	/* Load this new MAC address to memory. */
-	if (board_read_mac_addr() != NULL) {
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static int command_macaddr(int argc, char **argv)
-{
-	const char* buf;
-	int rv = EC_SUCCESS;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving MAC address\n");
-			rv = usb_save_mac_addr(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading MAC address\n");
-		} else {
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	buf = board_read_mac_addr();
-	if (buf == NULL) {
-		buf = DEFAULT_MAC_ADDR;
-	}
-	ccprintf("MAC address: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr,
-	"load/set [value]",
-	"Read and write MAC address");
-
-#endif  /* CONFIG_MAC_ADDR */
diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c
deleted file mode 100644
index b5666c8fbf..0000000000
--- a/chip/stm32/usb_console.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE,
-					    uint8_t);
-static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
-
-static int last_tx_ok = 1;
-
-static int is_reset;
-static int is_enabled = 1;
-static int is_readonly;
-
-/* USB-Serial descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_CONSOLE,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 2,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface         = USB_STR_CONSOLE_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = 0x80 | USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk IN */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 10
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 0
-};
-
-static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-static usb_uint ep_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
-
-/* Forward declaration */
-static void handle_output(void);
-
-static void con_ep_tx(void)
-{
-	/* clear IT */
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, 0, 0, 0);
-
-	/* Check bytes in the FIFO needed to transmitted */
-	handle_output();
-}
-
-static void con_ep_rx(void)
-{
-	int i;
-
-	for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK);
-	     i++) {
-		int val = ((i & 1) ?
-			   (ep_buf_rx[i >> 1] >> 8) :
-			   (ep_buf_rx[i >> 1] & 0xff));
-
-		QUEUE_ADD_UNITS(&rx_q, &val, 1);
-	}
-
-	/* clear IT */
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_RX_MASK, EP_RX_VALID, 0);
-
-	/* wake-up the console task */
-	console_has_input();
-}
-
-static void ep_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	btable_ep[USB_EP_CONSOLE].tx_addr  = usb_sram_addr(ep_buf_tx);
-	btable_ep[USB_EP_CONSOLE].tx_count = 0;
-
-	btable_ep[USB_EP_CONSOLE].rx_addr  = usb_sram_addr(ep_buf_rx);
-	btable_ep[USB_EP_CONSOLE].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
-
-	STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */
-					(2 << 4)       | /* TX NAK        */
-					(0 << 9)       | /* Bulk EP       */
-					(is_readonly ? EP_RX_NAK
-						     : EP_RX_VALID));
-
-	is_reset = 1;
-}
-
-USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
-
-static int __tx_char(void *context, int c)
-{
-	/* Do newline to CRLF translation */
-	if (c == '\n' && __tx_char(context, '\r'))
-		return 1;
-
-	/* Return 0 on success */
-	return !QUEUE_ADD_UNITS(&tx_q, &c, 1);
-}
-
-static void usb_enable_tx(int len)
-{
-	if (!is_enabled)
-		return;
-
-	btable_ep[USB_EP_CONSOLE].tx_count = len;
-	STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-static inline int usb_console_tx_valid(void)
-{
-	return (STM32_USB_EP(USB_EP_CONSOLE) & EP_TX_MASK) == EP_TX_VALID;
-}
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !usb_is_enabled())
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (usb_console_tx_valid() || !is_reset) {
-			if (timestamp_expired(deadline, NULL)) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-
-		return EC_SUCCESS;
-	} else {
-		last_tx_ok = !usb_console_tx_valid();
-		return EC_SUCCESS;
-	}
-}
-
-/* Try to send some bytes from the Tx FIFO to the host */
-static void tx_fifo_handler(void)
-{
-	int ret;
-	size_t count;
-	usb_uint *buf = (usb_uint *)ep_buf_tx;
-
-	if (!is_reset)
-		return;
-
-	ret = usb_wait_console();
-	if (ret)
-		return;
-
-	count = 0;
-	while (count < USB_MAX_PACKET_SIZE) {
-		int val = 0;
-
-		if (!QUEUE_REMOVE_UNITS(&tx_q, &val, 1))
-			break;
-
-		if (!(count & 1))
-			buf[count/2] = val;
-		else
-			buf[count/2] |= val << 8;
-		count++;
-	}
-
-	if (count)
-		usb_enable_tx(count);
-}
-DECLARE_DEFERRED(tx_fifo_handler);
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c = 0;
-
-	if (!is_enabled)
-		return -1;
-
-	if (!QUEUE_REMOVE_UNITS(&rx_q, &c, 1))
-		return -1;
-
-	return c;
-}
-
-int usb_putc(int c)
-{
-	int ret;
-
-	ret = __tx_char(NULL, c);
-	handle_output();
-
-	return ret;
-}
-
-int usb_puts(const char *outstr)
-{
-	/* Put all characters in the output buffer */
-	while (*outstr) {
-		if (__tx_char(NULL, *outstr++) != 0)
-			break;
-	}
-	handle_output();
-
-	/* Successful if we consumed all output */
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-
-	ret = vfnprintf(__tx_char, NULL, format, args);
-	handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
-
-int usb_console_tx_blocked(void)
-{
-	return is_enabled && usb_console_tx_valid();
-}
diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c
deleted file mode 100644
index f4ee89f1f0..0000000000
--- a/chip/stm32/usb_dwc.c
+++ /dev/null
@@ -1,1423 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "usb_hw.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "watchdog.h"
-
-
-/****************************************************************************/
-/* Debug output */
-
-/* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* TODO: Something unexpected happened. Figure out how to report & fix it. */
-#define report_error(val)						\
-	CPRINTS("Unhandled USB event at %s line %d: 0x%x",		\
-		__FILE__, __LINE__, val)
-
-
-/****************************************************************************/
-/* Standard USB stuff */
-
-#ifdef CONFIG_USB_BOS
-/* v2.10 (vs 2.00) BOS Descriptor provided */
-#define USB_DEV_BCDUSB 0x0210
-#else
-#define USB_DEV_BCDUSB 0x0200
-#endif
-
-#ifndef USB_DEV_CLASS
-#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE
-#endif
-
-#ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100		/* 1.00 */
-#endif
-
-#ifndef CONFIG_USB_SERIALNO
-#define USB_STR_SERIALNO 0
-#else
-static int usb_load_serial(void);
-#endif
-
-
-/* USB Standard Device Descriptor */
-static const struct usb_device_descriptor dev_desc = {
-	.bLength = USB_DT_DEVICE_SIZE,
-	.bDescriptorType = USB_DT_DEVICE,
-	.bcdUSB = USB_DEV_BCDUSB,
-	.bDeviceClass = USB_DEV_CLASS,
-	.bDeviceSubClass = 0x00,
-	.bDeviceProtocol = 0x00,
-	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = USB_VID_GOOGLE,
-	.idProduct = CONFIG_USB_PID,
-	.bcdDevice = CONFIG_USB_BCD_DEV,
-	.iManufacturer = USB_STR_VENDOR,
-	.iProduct = USB_STR_PRODUCT,
-	.iSerialNumber = USB_STR_SERIALNO,
-	.bNumConfigurations = 1
-};
-
-/* USB Configuration Descriptor */
-const struct usb_config_descriptor USB_CONF_DESC(conf) = {
-	.bLength = USB_DT_CONFIG_SIZE,
-	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD,	 /* number of returned bytes, set at runtime */
-	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,		/* Caution: hard-coded value */
-	.iConfiguration = USB_STR_VERSION,
-	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
-#endif
-	,
-	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
-};
-
-const uint8_t usb_string_desc[] = {
-	4,					/* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04			    /* LangID = 0x0409: U.S. English */
-};
-
-/****************************************************************************/
-/* Packet-handling stuff, specific to this SoC */
-
-/* Some internal state to keep track of what's going on */
-static enum {
-	WAITING_FOR_SETUP_PACKET,
-	DATA_STAGE_IN,
-	NO_DATA_STAGE,
-} what_am_i_doing;
-
-#ifdef DEBUG_ME
-static const char * const wat[3] = {
-	[WAITING_FOR_SETUP_PACKET] = "wait_for_setup",
-	[DATA_STAGE_IN] = "data_in",
-	[NO_DATA_STAGE] = "no_data",
-};
-#endif
-
-/* Programmer's Guide, Table 10-7 */
-enum table_case {
-	BAD_0,
-	TABLE_CASE_COMPLETE,
-	TABLE_CASE_SETUP,
-	TABLE_CASE_WTF,
-	TABLE_CASE_D,
-	TABLE_CASE_E,
-	BAD_6,
-	BAD_7,
-};
-
-static enum table_case decode_table_10_7(uint32_t doepint)
-{
-	enum table_case val = BAD_0;
-
-	/* Bits: SI, SPD, IOC */
-	if (doepint & DOEPINT_XFERCOMPL)
-		val += 1;
-	if (doepint & DOEPINT_SETUP)
-		val += 2;
-	return val;
-}
-
-/* For STATUS/OUT: Use two DMA descriptors, each with one-packet buffers */
-#define NUM_OUT_BUFFERS 2
-static uint8_t __aligned(4) ep0_setup_buf[USB_MAX_PACKET_SIZE];
-
-/* For IN: Several DMA descriptors, all pointing into one large buffer, so that
- * we can return the configuration descriptor as one big blob.
- */
-#define NUM_IN_PACKETS_AT_ONCE 4
-#define IN_BUF_SIZE (NUM_IN_PACKETS_AT_ONCE * USB_MAX_PACKET_SIZE)
-static uint8_t __aligned(4) ep0_in_buf[IN_BUF_SIZE];
-
-struct dwc_usb_ep ep0_ctl = {
-	.max_packet = USB_MAX_PACKET_SIZE,
-	.tx_fifo = 0,
-	.out_pending = 0,
-	.out_expected = 0,
-	.out_data = 0,
-	.out_databuffer = ep0_setup_buf,
-	.out_databuffer_max = sizeof(ep0_setup_buf),
-	.rx_deferred = 0,
-	.in_packets = 0,
-	.in_pending = 0,
-	.in_data = 0,
-	.in_databuffer = ep0_in_buf,
-	.in_databuffer_max = sizeof(ep0_in_buf),
-	.tx_deferred = 0,
-};
-
-/* Overall device state (USB 2.0 spec, section 9.1.1).
- * We only need a few, though.
- */
-static enum {
-	DS_DEFAULT,
-	DS_ADDRESS,
-	DS_CONFIGURED,
-} device_state;
-static uint8_t configuration_value;
-
-
-/* True if the HW Rx/OUT FIFO is currently listening. */
-int rx_ep_is_active(uint32_t ep_num)
-{
-	return (GR_USB_DOEPCTL(ep_num) & DXEPCTL_EPENA) ? 1 : 0;
-}
-
-/* Number of bytes the HW Rx/OUT FIFO has for us.
- *
- * @param ep_num	USB endpoint
- *
- * @returns		number of bytes ready, zero if none.
- */
-int rx_ep_pending(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	return ep->out_pending;
-}
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-int tx_ep_is_ready(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	int ready;
-
-	/* Is the tx hw idle? */
-	ready = !(GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA);
-
-	/* Is there no pending data? */
-	ready &= (ep->in_pending == 0);
-	return ready;
-}
-
-/* Write packets of data IN to the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the write completion event.
- *
- * @param ep_num	USB endpoint to write
- * @param len		number of bytes to write
- * @param data		pointer of data to write
- *
- * @return		bytes written
- */
-int usb_write_ep(uint32_t ep_num, int len, void *data)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) {
-		CPRINTS("usb_write_ep ep%d: FAIL: tx already in progress!",
-			ep_num);
-		return 0;
-	}
-
-	/* We will send as many packets as necessary, including a final
-	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
-	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE;
-	ep->in_pending = len;
-	ep->in_data = data;
-
-	GR_USB_DIEPTSIZ(ep_num) = 0;
-
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(ep->in_packets);
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(ep_num) = (uint32_t)(ep->in_data);
-
-	/* We could support longer multi-dma transfers here. */
-	ep->in_pending -= len;
-	ep->in_packets -= ep->in_packets;
-	ep->in_data += len;
-
-	/* We are ready to enable this endpoint to start transferring data. */
-	GR_USB_DIEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	return len;
-}
-
-/* Tx/IN interrupt handler */
-void usb_epN_tx(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	uint32_t dieptsiz = GR_USB_DIEPTSIZ(ep_num);
-
-	if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) {
-		CPRINTS("usb_epN_tx ep%d: tx still active.", ep_num);
-		return;
-	}
-
-	/* clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(ep_num) = 0xffffffff;
-
-	/*
-	 * Let's assume this is actually true.
-	 * We could support multi-dma transfers here.
-	 */
-	ep->in_packets = 0;
-	ep->in_pending = dieptsiz & GC_USB_DIEPTSIZ1_XFERSIZE_MASK;
-
-	if (ep->tx_deferred)
-		hook_call_deferred(ep->tx_deferred, 0);
-}
-
-/* Read a packet of data OUT from the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the read completion event.
- *
- * @param ep_num	USB endpoint to read
- * @param len		number of bytes to read
- * @param data		pointer of data to read
- *
- * @return		EC_SUCCESS on success
- */
-int usb_read_ep(uint32_t ep_num, int len, void *data)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-	int packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE;
-
-	ep->out_data = data;
-	ep->out_pending = 0;
-	ep->out_expected = len;
-
-	GR_USB_DOEPTSIZ(ep_num) = 0;
-	GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(packets);
-	GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DOEPDMA(ep_num) = (uint32_t)ep->out_data;
-
-	GR_USB_DOEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	return EC_SUCCESS;
-}
-
-/* Rx/OUT endpoint interrupt handler */
-void usb_epN_rx(uint32_t ep_num)
-{
-	struct dwc_usb_ep *ep = usb_ctl.ep[ep_num];
-
-	/* Still receiving data. Let's wait. */
-	if (rx_ep_is_active(ep_num))
-		return;
-
-	/* Bytes received decrement DOEPTSIZ XFERSIZE */
-	if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) {
-		if (ep->out_expected > 0) {
-			ep->out_pending =
-				ep->out_expected -
-				(GR_USB_DOEPTSIZ(ep_num) &
-				 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
-		} else {
-			CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n",
-				ep_num, GR_USB_DOEPTSIZ(ep_num));
-			ep->out_pending = 0;
-		}
-		ep->out_expected = 0;
-		GR_USB_DOEPTSIZ(ep_num) = 0;
-	}
-
-	/* clear the RX/OUT interrupts */
-	GR_USB_DOEPINT(ep_num) = 0xffffffff;
-
-	if (ep->rx_deferred)
-		hook_call_deferred(ep->rx_deferred, 0);
-}
-
-/* Reset endpoint HW block. */
-void epN_reset(uint32_t ep_num)
-{
-	GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
-	GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
-		DXEPCTL_TXFNUM(ep_num);
-	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) |
-			   DAINT_OUTEP(ep_num);
-}
-
-
-/******************************************************************************
- * Internal and EP0 functions.
- */
-
-
-static void flush_all_fifos(void)
-{
-	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
-	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;
-}
-
-int send_in_packet(uint32_t ep_num)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[ep_num];
-	int len = MIN(USB_MAX_PACKET_SIZE, ep->in_pending);
-
-	if (ep->in_packets == 0) {
-		report_error(ep_num);
-		return -1;
-	}
-
-	GR_USB_DIEPTSIZ(ep_num) = 0;
-
-	GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data;
-
-
-	/* We're sending this much. */
-	ep->in_pending -= len;
-	ep->in_packets -= 1;
-	ep->in_data += len;
-
-	/* We are ready to enable this endpoint to start transferring data. */
-	return len;
-}
-
-
-/* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns
- * len, or negative on error.
- */
-int initialize_in_transfer(const void *source, uint32_t len)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-#ifdef CONFIG_USB_DWC_FS
-	/* FS OTG port does not support DMA or external phy */
-	ASSERT(!(usb->dma_en));
-	ASSERT(usb->phy_type == USB_PHY_INTERNAL);
-	ASSERT(usb->speed == USB_SPEED_FS);
-	ASSERT(usb->irq == STM32_IRQ_OTG_FS);
-#else
-	/* HS OTG port requires an external phy to support HS */
-	ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) &&
-		(usb->speed == USB_SPEED_HS)));
-	ASSERT(usb->irq == STM32_IRQ_OTG_HS);
-#endif
-
-	/* Copy the data into our FIFO buffer */
-	if (len >= IN_BUF_SIZE) {
-		report_error(len);
-		return -1;
-	}
-
-	/* Stage data in DMA buffer. */
-	memcpy(ep->in_databuffer, source, len);
-	ep->in_data = ep->in_databuffer;
-
-	/* We will send as many packets as necessary, including a final
-	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
-	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE;
-	ep->in_pending = len;
-
-	send_in_packet(0);
-	return len;
-}
-
-/* Prepare the EP0 OUT FIFO buffer to accept some data. Returns len, or
- * negative on error.
- */
-int accept_out_fifo(uint32_t len)
-{
-	/* TODO: This is not yet implemented */
-	report_error(len);
-	return -1;
-}
-
-/* The next packet from the host should be a Setup packet. Get ready for it. */
-static void expect_setup_packet(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-	ep->out_data = ep->out_databuffer;
-
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	GR_USB_DOEPTSIZ(0) = 0;
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(0x18);
-	GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_SUPCNT(1);
-	GR_USB_DOEPCTL(0) = DXEPCTL_USBACTEP | DXEPCTL_EPENA;
-	GR_USB_DOEPDMA(0) = (uint32_t)ep->out_data;
-}
-
-/* We're complaining about something by stalling both IN and OUT packets,
- * but a SETUP packet will get through anyway, so prepare for it.
- */
-static void stall_both_fifos(void)
-{
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	GR_USB_DOEPCTL(0) |= DXEPCTL_STALL;
-	GR_USB_DIEPCTL(0) |= DXEPCTL_STALL;
-	expect_setup_packet();
-}
-
-/* The TX FIFO buffer is loaded. Start the Data phase. */
-static void expect_data_phase_in(enum table_case tc)
-{
-	what_am_i_doing = DATA_STAGE_IN;
-
-	/* Send the reply (data phase in) */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP |
-					DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* We'll receive an empty packet back as a ack, I guess. */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DOEPCTL(0) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DOEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-
-}
-
-static void expect_data_phase_out(enum table_case tc)
-{
-	/* TODO: This is not yet supported */
-	report_error(tc);
-	expect_setup_packet();
-}
-
-/* No Data phase, just Status phase (which is IN, since Setup is OUT) */
-static void expect_status_phase_in(enum table_case tc)
-{
-	what_am_i_doing = NO_DATA_STAGE;
-
-	/* Expect a zero-length IN for the Status phase */
-	(void) initialize_in_transfer(0, 0);
-
-	/* Blindly following instructions here, too. */
-	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP
-			| DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-}
-
-/* Handle a Setup packet that expects us to send back data in reply. Return the
- * length of the data we're returning, or negative to indicate an error.
- */
-static int handle_setup_with_in_stage(enum table_case tc,
-				      struct usb_setup_packet *req)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-
-	const void *data = 0;
-	uint32_t len = 0;
-	int ugly_hack = 0;
-	static const uint16_t zero;		/* == 0 */
-
-	switch (req->bRequest) {
-	case USB_REQ_GET_DESCRIPTOR: {
-		uint8_t type = req->wValue >> 8;
-		uint8_t idx = req->wValue & 0xff;
-
-		switch (type) {
-		case USB_DT_DEVICE:
-			data = &dev_desc;
-			len = sizeof(dev_desc);
-			break;
-		case USB_DT_CONFIGURATION:
-			data = __usb_desc;
-			len = USB_DESC_SIZE;
-			ugly_hack = 1;		/* see below */
-			break;
-#ifdef CONFIG_USB_BOS
-		case USB_DT_BOS:
-			data = bos_ctx.descp;
-			len = bos_ctx.size;
-			break;
-#endif
-		case USB_DT_STRING:
-			if (idx >= USB_STR_COUNT)
-				return -1;
-#ifdef CONFIG_USB_SERIALNO
-			if (idx == USB_STR_SERIALNO)
-				data = (uint8_t *)usb_serialno_desc;
-			else
-#endif
-				data = usb_strings[idx];
-			len = *(uint8_t *)data;
-			break;
-		case USB_DT_DEVICE_QUALIFIER:
-			/* We're not high speed */
-			return -1;
-		case USB_DT_DEBUG:
-			/* Not supported */
-			return -1;
-		default:
-			report_error(type);
-			return -1;
-		}
-		break;
-	}
-	case USB_REQ_GET_STATUS: {
-		/* TODO: Device Status: Remote Wakeup? Self Powered? */
-		data = &zero;
-		len = sizeof(zero);
-		break;
-	}
-	case USB_REQ_GET_CONFIGURATION:
-		data = &configuration_value;
-		len = sizeof(configuration_value);
-		break;
-
-	case USB_REQ_SYNCH_FRAME:
-		/* Unimplemented */
-		return -1;
-
-	default:
-		report_error(req->bRequest);
-		return -1;
-	}
-
-	/* Don't send back more than we were asked for. */
-	len = MIN(req->wLength, len);
-
-	/* Prepare the TX FIFO. If we haven't preallocated enough room in the
-	 * TX FIFO for the largest reply, we'll have to stall. This is a bug in
-	 * our code, but detecting it easily at compile time is related to the
-	 * ugly_hack directly below.
-	 */
-	if (initialize_in_transfer(data, len) < 0)
-		return -1;
-
-	if (ugly_hack) {
-		/*
-		 * TODO: Somebody figure out how to fix this, please.
-		 *
-		 * The USB configuration descriptor request is unique in that
-		 * it not only returns the configuration descriptor, but also
-		 * all the interface descriptors and all their endpoint
-		 * descriptors as one enormous blob. We've set up some macros
-		 * so we can declare and implement separate interfaces in
-		 * separate files just by compiling them, and all the relevant
-		 * descriptors are sorted and bundled up by the linker. But the
-		 * total length of the entire blob needs to appear in the first
-		 * configuration descriptor struct and because we don't know
-		 * that value until after linking, it can't be initialized as a
-		 * constant. So we have to compute it at run-time and shove it
-		 * in here, which also means that we have to copy the whole
-		 * blob into our TX FIFO buffer so that it's mutable. Otherwise
-		 * we could just point at it (or pretty much any other constant
-		 * struct that we wanted to send to the host). Bah.
-		 */
-		struct usb_config_descriptor *cfg =
-			(struct usb_config_descriptor *)ep->in_databuffer;
-		/* set the real descriptor size */
-		cfg->wTotalLength = USB_DESC_SIZE;
-	}
-
-	return len;
-}
-
-/* Handle a Setup that comes with additional data for us. */
-static int handle_setup_with_out_stage(enum table_case tc,
-					struct usb_setup_packet *req)
-{
-	/* TODO: We don't support any of these. We should. */
-	report_error(-1);
-	return -1;
-}
-
-/* Some Setup packets don't have a data stage at all. */
-static int handle_setup_with_no_data_stage(enum table_case tc,
-					   struct usb_setup_packet *req)
-{
-	uint8_t set_addr;
-
-	switch (req->bRequest) {
-	case USB_REQ_SET_ADDRESS:
-		/*
-		 * Set the address after the IN packet handshake.
-		 *
-		 * From the USB 2.0 spec, section 9.4.6:
-		 *
-		 * As noted elsewhere, requests actually may result in
-		 * up to three stages. In the first stage, the Setup
-		 * packet is sent to the device. In the optional second
-		 * stage, data is transferred between the host and the
-		 * device. In the final stage, status is transferred
-		 * between the host and the device. The direction of
-		 * data and status transfer depends on whether the host
-		 * is sending data to the device or the device is
-		 * sending data to the host. The Status stage transfer
-		 * is always in the opposite direction of the Data
-		 * stage. If there is no Data stage, the Status stage
-		 * is from the device to the host.
-		 *
-		 * Stages after the initial Setup packet assume the
-		 * same device address as the Setup packet. The USB
-		 * device does not change its device address until
-		 * after the Status stage of this request is completed
-		 * successfully. Note that this is a difference between
-		 * this request and all other requests. For all other
-		 * requests, the operation indicated must be completed
-		 * before the Status stage
-		 */
-		set_addr = req->wValue & 0xff;
-		/*
-		 * NOTE: Now that we've said that, we don't do it. The
-		 * hardware for this SoC knows that an IN packet will
-		 * be following the SET ADDRESS, so it waits until it
-		 * sees that happen before the address change takes
-		 * effect. If we wait until after the IN packet to
-		 * change the register, the hardware gets confused and
-		 * doesn't respond to anything.
-		 */
-		GWRITE_FIELD(USB, DCFG, DEVADDR, set_addr);
-		CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr);
-		device_state = DS_ADDRESS;
-		break;
-
-	case USB_REQ_SET_CONFIGURATION:
-		switch (req->wValue) {
-		case 0:
-			configuration_value = req->wValue;
-			device_state = DS_ADDRESS;
-			break;
-		case 1:	    /* Caution: Only one config descriptor TODAY */
-			/* TODO: All endpoints set to DATA0 toggle state */
-			configuration_value = req->wValue;
-			device_state = DS_CONFIGURED;
-			break;
-		default:
-			/* Nope. That's a paddlin. */
-			report_error(-1);
-			return -1;
-		}
-		break;
-
-	case USB_REQ_CLEAR_FEATURE:
-	case USB_REQ_SET_FEATURE:
-		/* TODO: Handle DEVICE_REMOTE_WAKEUP, ENDPOINT_HALT? */
-		break;
-
-	default:
-		/* Anything else is unsupported */
-		report_error(-1);
-		return -1;
-	}
-
-	/* No data to transfer, go straight to the Status phase. */
-	return 0;
-}
-
-/* Dispatch an incoming Setup packet according to its type */
-static void handle_setup(enum table_case tc)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-	struct usb_setup_packet *req =
-		(struct usb_setup_packet *)ep->out_databuffer;
-	int data_phase_in = req->bmRequestType & USB_DIR_IN;
-	int data_phase_out = !data_phase_in && req->wLength;
-	int bytes = -1;				/* default is to stall */
-
-	if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) {
-		/* Standard Device requests */
-		if (data_phase_in)
-			bytes = handle_setup_with_in_stage(tc, req);
-		else if (data_phase_out)
-			bytes = handle_setup_with_out_stage(tc, req);
-		else
-			bytes = handle_setup_with_no_data_stage(tc, req);
-	} else if (USB_RECIP_INTERFACE ==
-		   (req->bmRequestType & USB_RECIP_MASK)) {
-		/* Interface-specific requests */
-		uint8_t iface = req->wIndex & 0xff;
-
-		if (iface < USB_IFACE_COUNT)
-			bytes = usb_iface_request[iface](req);
-	} else {
-		/* Something we need to add support for? */
-		report_error(-1);
-	}
-
-	/* We say "no" to unsupported and intentionally unhandled requests by
-	 * stalling the Data and/or Status stage.
-	 */
-	if (bytes < 0) {
-		/* Stall both IN and OUT. SETUP will come through anyway. */
-		stall_both_fifos();
-	} else {
-		if (data_phase_in)
-			expect_data_phase_in(tc);
-		else if (data_phase_out)
-			expect_data_phase_out(tc);
-		else
-			expect_status_phase_in(tc);
-	}
-}
-
-/* This handles both IN and OUT interrupts for EP0 */
-static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	struct dwc_usb_ep *ep = usb->ep[0];
-	uint32_t doepint, diepint;
-	enum table_case tc;
-	int out_complete, out_setup, in_complete;
-
-	/* Determine the interrupt cause and clear the bits quickly, but only
-	 * if they really apply. I don't think they're trustworthy if we didn't
-	 * actually get an interrupt.
-	 */
-	doepint = GR_USB_DOEPINT(0) & GR_USB_DOEPMSK;
-	if (intr_on_out)
-		GR_USB_DOEPINT(0) = doepint;
-	diepint = GR_USB_DIEPINT(0) & GR_USB_DIEPMSK;
-	if (intr_on_in)
-		GR_USB_DIEPINT(0) = diepint;
-
-	out_complete = doepint & DOEPINT_XFERCOMPL;
-	out_setup = doepint & DOEPINT_SETUP;
-	in_complete = diepint & DIEPINT_XFERCOMPL;
-
-	/* Decode the situation according to Table 10-7 */
-	tc = decode_table_10_7(doepint);
-
-	switch (what_am_i_doing) {
-	case WAITING_FOR_SETUP_PACKET:
-		if (out_setup)
-			handle_setup(tc);
-		else
-			report_error(-1);
-		break;
-
-	case DATA_STAGE_IN:
-		if (intr_on_in && in_complete) {
-			/* A packet is sent. Should we send another? */
-			if (ep->in_packets > 0) {
-				/* Send another packet. */
-				send_in_packet(0);
-				expect_data_phase_in(tc);
-			}
-		}
-
-		/* But we should ignore the OUT endpoint if we didn't actually
-		 * get an OUT interrupt.
-		 */
-		if (!intr_on_out)
-			break;
-
-		if (out_setup) {
-			/* The first IN packet has been seen. Keep going. */
-			break;
-		}
-		if (out_complete) {
-			/* We've handled the Status phase. All done. */
-			expect_setup_packet();
-			break;
-		}
-
-		/* Anything else should be ignorable. Right? */
-		break;
-
-	case NO_DATA_STAGE:
-		if (intr_on_in && in_complete) {
-			/* We are not expecting an empty packet in
-			 * return for our empty packet.
-			 */
-			expect_setup_packet();
-		}
-
-		/* Done unless we got an OUT interrupt */
-		if (!intr_on_out)
-			break;
-
-		if (out_setup) {
-			report_error(-1);
-			break;
-		}
-
-		/* Anything else means get ready for a Setup packet */
-		report_error(-1);
-		expect_setup_packet();
-		break;
-	}
-}
-
-/****************************************************************************/
-/* USB device initialization and shutdown routines */
-
-/*
- * DATA FIFO Setup. There is an internal SPRAM used to buffer the IN/OUT
- * packets and track related state without hammering the AHB and system RAM
- * during USB transactions. We have to specify where and how much of that SPRAM
- * to use for what.
- *
- * See Programmer's Guide chapter 2, "Calculating FIFO Size".
- * We're using Dedicated TxFIFO Operation, without enabling thresholding.
- *
- * Section 2.1.1.2, page 30: RXFIFO size is the same as for Shared FIFO, which
- * is Section 2.1.1.1, page 28. This is also the same as Method 2 on page 45.
- *
- * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max
- * data packet size is 64 bytes. Total SPRAM available is 1024 slots.
- */
-#define MAX_CONTROL_EPS   3
-#define MAX_NORMAL_EPS    16
-#define FIFO_RAM_DEPTH    1024
-/*
- * Device RX FIFO size is thus:
- *   (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85
- */
-#define RXFIFO_SIZE  ((4 * MAX_CONTROL_EPS + 6) + \
-		      2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
-		      (2 * MAX_NORMAL_EPS) + 1)
-/*
- * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46).
- */
-#define TXFIFO_SIZE  (2 * (USB_MAX_PACKET_SIZE / 4))
-/*
- * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1,
- * unconfigurable).
- */
-#define EP_STATUS_SIZE (4 * MAX_NORMAL_EPS * 2)
-/*
- * Make sure all that fits.
- */
-BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE <
-	     FIFO_RAM_DEPTH);
-
-
-/* Now put those constants into the correct registers */
-static void setup_data_fifos(void)
-{
-	int i;
-
-	/* Programmer's Guide, p31 */
-	GR_USB_GRXFSIZ = RXFIFO_SIZE;			      /* RXFIFO */
-	GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
-
-	/* TXFIFO 1..15 */
-	for (i = 1; i < MAX_NORMAL_EPS; i++)
-		GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
-				     (RXFIFO_SIZE + i * TXFIFO_SIZE));
-
-	/*
-	 * TODO: The Programmer's Guide is confusing about when or whether to
-	 * flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section
-	 * 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section
-	 * 7.5.4 (p162) says that flushing the RXFIFO at reset is not
-	 * recommended at all.
-	 *
-	 * I'm also unclear on whether or not the individual EPs are expected
-	 * to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so,
-	 * whether by firmware or hardware.
-	 */
-
-	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
-	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;				/* TODO: timeout 100ms */
-}
-
-static void usb_init_endpoints(void)
-{
-	int ep;
-
-	/* Prepare to receive packets on EP0 */
-	expect_setup_packet();
-
-	/* Reset the other endpoints */
-	for (ep = 1; ep < USB_EP_COUNT; ep++)
-		usb_ep_event[ep](USB_EVENT_RESET);
-}
-
-static void usb_reset(void)
-{
-	/* Clear our internal state */
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-
-	/* Clear the device address */
-	GWRITE_FIELD(USB, DCFG, DEVADDR, 0);
-
-	/* Reinitialize all the endpoints */
-	usb_init_endpoints();
-}
-
-static void usb_resetdet(void)
-{
-	/* TODO: Same as normal reset, right? I think we only get this if we're
-	 * suspended (sleeping) and the host resets us. Try it and see.
-	 */
-	usb_reset();
-}
-
-static void usb_enumdone(void)
-{
-	/* We can change to HS here. We will not go to HS today */
-	GR_USB_DCTL |= DCTL_CGOUTNAK;
-}
-
-
-void usb_interrupt(void)
-{
-	uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK;
-	uint32_t oepint = status & GINTSTS(OEPINT);
-	uint32_t iepint = status & GINTSTS(IEPINT);
-	int ep;
-
-	if (status & GINTSTS(ENUMDONE))
-		usb_enumdone();
-
-	if (status & GINTSTS(RESETDET))
-		usb_resetdet();
-
-	if (status & GINTSTS(USBRST))
-		usb_reset();
-
-	/* Endpoint interrupts */
-	if (oepint || iepint) {
-		/* Note: It seems that the DAINT bits are only trustworthy for
-		 * identifying interrupts when selected by the corresponding
-		 * OEPINT and IEPINT bits from GINTSTS.
-		 */
-		uint32_t daint = GR_USB_DAINT;
-
-		/* EP0 has a combined IN/OUT handler. Only call it once, but
-		 * let it know which direction(s) had an interrupt.
-		 */
-		if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
-			uint32_t intr_on_out = (oepint &&
-						(daint & DAINT_OUTEP(0)));
-			uint32_t intr_on_in = (iepint &&
-						(daint & DAINT_INEP(0)));
-			ep0_interrupt(intr_on_out, intr_on_in);
-		}
-
-		/* Invoke the unidirectional IN and OUT functions for the other
-		 * endpoints. Each handler must clear their own bits in
-		 * DIEPINTn/DOEPINTn.
-		 */
-		for (ep = 1; ep < USB_EP_COUNT; ep++) {
-			if (oepint && (daint & DAINT_OUTEP(ep)))
-				usb_ep_rx[ep]();
-			if (iepint && (daint & DAINT_INEP(ep)))
-				usb_ep_tx[ep]();
-		}
-	}
-
-	GR_USB_GINTSTS = status;
-}
-DECLARE_IRQ(STM32_IRQ_OTG_FS, usb_interrupt, 1);
-DECLARE_IRQ(STM32_IRQ_OTG_HS, usb_interrupt, 1);
-
-static void usb_softreset(void)
-{
-	int timeout;
-
-	CPRINTS("%s", __func__);
-
-	/* Wait for bus idle */
-	timeout = 10000;
-	while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0)
-		;
-
-	/* Reset and wait for clear */
-	GR_USB_GRSTCTL = GRSTCTL_CSFTRST;
-	timeout = 10000;
-	while ((GR_USB_GRSTCTL & GRSTCTL_CSFTRST) && timeout-- > 0)
-		;
-	if (GR_USB_GRSTCTL & GRSTCTL_CSFTRST) {
-		CPRINTF("USB: reset failed\n");
-		return;
-	}
-
-	/* Some more idle? */
-	timeout = 10000;
-	while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0)
-		;
-
-	if (!timeout) {
-		CPRINTF("USB: reset timeout\n");
-		return;
-	}
-	/* TODO: Wait 3 PHY clocks before returning */
-}
-
-void usb_connect(void)
-{
-	GR_USB_DCTL &= ~DCTL_SFTDISCON;
-}
-
-void usb_disconnect(void)
-{
-	GR_USB_DCTL |= DCTL_SFTDISCON;
-
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-}
-
-void usb_reset_init_phy(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-
-	if (usb->phy_type == USB_PHY_ULPI) {
-		GR_USB_GCCFG &= ~GCCFG_PWRDWN;
-		GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS |
-			GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
-		GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-		/* No suspend */
-		GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR;
-
-		usb_softreset();
-	} else {
-		GR_USB_GUSBCFG |= GUSBCFG_PHYSEL;
-		usb_softreset();
-		GR_USB_GCCFG |= GCCFG_PWRDWN;
-	}
-}
-
-void usb_init(void)
-{
-	int i;
-	struct dwc_usb *usb = &usb_ctl;
-
-	CPRINTS("%s", __func__);
-
-#ifdef CONFIG_USB_SERIALNO
-	usb_load_serial();
-#endif
-
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	/* Enable clocks */
-	clock_enable_module(MODULE_USB, 0);
-	clock_enable_module(MODULE_USB, 1);
-
-	/* TODO(crbug.com/496888): set up pinmux */
-	gpio_config_module(MODULE_USB, 1);
-
-	/* Make sure interrupts are disabled */
-	GR_USB_GINTMSK = 0;
-	GR_USB_DAINTMSK = 0;
-	GR_USB_DIEPMSK = 0;
-	GR_USB_DOEPMSK = 0;
-
-	/* Full-Speed Serial PHY */
-	usb_reset_init_phy();
-
-	/* Global + DMA configuration */
-	GR_USB_GAHBCFG = GAHBCFG_GLB_INTR_EN;
-	GR_USB_GAHBCFG |= GAHBCFG_HBSTLEN_INCR4;
-	if (usb->dma_en)
-		GR_USB_GAHBCFG |= GAHBCFG_DMA_EN;
-
-	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD;
-	GR_USB_GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP;
-
-	GR_USB_GCCFG &= ~GCCFG_VBDEN;
-	GR_USB_GOTGCTL |= GOTGCTL_BVALOEN;
-	GR_USB_GOTGCTL |= GOTGCTL_BVALOVAL;
-
-	GR_USB_PCGCCTL = 0;
-
-	if (usb->phy_type == USB_PHY_ULPI) {
-		/* TODO(nsanders): add HS support like so.
-		 * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-		 * | DCFG_DEVSPD_HSULPI;
-		 */
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FSULPI;
-	} else {
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FS48;
-	}
-
-	GR_USB_DCFG |= DCFG_NZLSOHSK;
-
-	flush_all_fifos();
-
-	/* Clear pending interrupts again */
-	GR_USB_GINTMSK = 0;
-	GR_USB_DIEPMSK = 0;
-	GR_USB_DOEPMSK = 0;
-	GR_USB_DAINT = 0xffffffff;
-	GR_USB_DAINTMSK = 0;
-
-	/* TODO: What about the AHB Burst Length Field? It's 0 now. */
-	GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL;
-
-	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
-
-	/* Be in disconnected state until we are ready */
-	usb_disconnect();
-
-	/* If we've restored a nonzero device address, update our state. */
-	if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) {
-		/* Caution: We only have one config TODAY, so there's no real
-		 * difference between DS_CONFIGURED and DS_ADDRESS.
-		 */
-		device_state = DS_CONFIGURED;
-		configuration_value = 1;
-	} else {
-		device_state = DS_DEFAULT;
-		configuration_value = 0;
-	}
-
-	/* Now that DCFG.DesDMA is accurate, prepare the FIFOs */
-	setup_data_fifos();
-
-	usb_init_endpoints();
-
-	/* Clear any pending interrupts */
-	for (i = 0; i < 16; i++) {
-		GR_USB_DIEPINT(i) = 0xffffffff;
-		GR_USB_DIEPTSIZ(i) = 0;
-		GR_USB_DOEPINT(i) = 0xffffffff;
-		GR_USB_DOEPTSIZ(i) = 0;
-	}
-
-	if (usb->dma_en) {
-		GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6;
-		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN
-			| DTHRCTL_NONISOTHREN;
-		i = GR_USB_DTHRCTL;
-	}
-
-	GR_USB_GINTSTS = 0xFFFFFFFF;
-
-	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL
-		| GAHBCFG_PTXFELVL;
-
-	if (!(usb->dma_en))
-		GR_USB_GINTMSK |= GINTMSK(RXFLVL);
-
-	/* Unmask some endpoint interrupt causes */
-	GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
-	GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
-		DOEPMSK_SETUPMSK;
-
-	/* Enable interrupt handlers */
-	task_enable_irq(usb->irq);
-
-	/* Allow USB interrupts to come in */
-	GR_USB_GINTMSK |=
-		/* NAK bits that must be cleared by the DCTL register */
-		GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) |
-		/* Initialization events */
-		GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
-		/* Reset detected while suspended. Need to wake up. */
-		GINTMSK(RESETDET) |		/* TODO: Do we need this? */
-		/* Idle, Suspend detected. Should go to sleep. */
-		GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP);
-
-	GR_USB_GINTMSK |=
-		/* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */
-		GINTMSK(OEPINT) | GINTMSK(IEPINT);
-
-	/* Device registers have been setup */
-	GR_USB_DCTL |= DCTL_PWRONPRGDONE;
-	udelay(10);
-	GR_USB_DCTL &= ~DCTL_PWRONPRGDONE;
-
-	/* Clear global NAKs */
-	GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK;
-
-#ifndef CONFIG_USB_INHIBIT_CONNECT
-	/* Indicate our presence to the USB host */
-	usb_connect();
-#endif
-}
-#ifndef CONFIG_USB_INHIBIT_INIT
-DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT);
-#endif
-
-void usb_release(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-
-	/* signal disconnect to host */
-	usb_disconnect();
-
-	/* disable interrupt handlers */
-	task_disable_irq(usb->irq);
-
-	/* disable clocks */
-	clock_enable_module(MODULE_USB, 0);
-	/* TODO: pin-mux */
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
-
-/* Print USB info and stats */
-static void usb_info(void)
-{
-	struct dwc_usb *usb = &usb_ctl;
-	int i;
-
-	CPRINTF("USB settings: %s%s%s\n",
-		usb->speed == USB_SPEED_FS ? "FS " : "HS ",
-		usb->phy_type == USB_PHY_INTERNAL ? "Internal Phy " : "ULPI ",
-		usb->dma_en ? "DMA " : "");
-
-	for (i = 0; i < USB_EP_COUNT; i++) {
-		CPRINTF("Endpoint %d activity: %s%s\n", i,
-			rx_ep_is_active(i) ? "RX " : "",
-			tx_ep_is_ready(i) ? "" : "TX ");
-	}
-}
-
-static int command_usb(int argc, char **argv)
-{
-	if (argc > 1) {
-		if (!strcasecmp("on", argv[1]))
-			usb_init();
-		else if (!strcasecmp("off", argv[1]))
-			usb_release();
-		else if (!strcasecmp("info", argv[1]))
-			usb_info();
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(usb, command_usb,
-			"[on|off|info]",
-			"Get/set the USB connection state and PHY selection");
-
-#ifdef CONFIG_USB_SERIALNO
-/* This will be subbed into USB_STR_SERIALNO. */
-struct usb_string_desc *usb_serialno_desc =
-	USB_WR_STRING_DESC(DEFAULT_SERIALNO);
-
-/* Update serial number */
-static int usb_set_serial(const char *serialno)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	int i;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Convert into unicode usb string desc. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++) {
-		sd->_data[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	/* Count wchars (w/o null terminator) plus size & type bytes. */
-	sd->_len = (i * 2) + 2;
-	sd->_type = USB_DT_STRING;
-
-	return EC_SUCCESS;
-}
-
-/* Retrieve serial number from pstate flash. */
-static int usb_load_serial(void)
-{
-	const char *serialno;
-	int rv;
-
-	serialno = board_read_serial();
-	if (!serialno)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = usb_set_serial(serialno);
-	return rv;
-}
-
-/* Save serial number into pstate region. */
-static int usb_save_serial(const char *serialno)
-{
-	int rv;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Save this new serial number to flash. */
-	rv = board_write_serial(serialno);
-	if (rv)
-		return rv;
-
-	/* Load this new serial number to memory. */
-	rv = usb_load_serial();
-	return rv;
-}
-
-static int command_serialno(int argc, char **argv)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	char buf[CONFIG_SERIALNO_LEN];
-	int rv = EC_SUCCESS;
-	int i;
-
-	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
-			ccprintf("Saving serial number\n");
-			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
-			ccprintf("Loading serial number\n");
-			rv = usb_load_serial();
-		} else
-			return EC_ERROR_INVAL;
-	}
-
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++)
-		buf[i] = sd->_data[i];
-	ccprintf("Serial number: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-#endif  /* CONFIG_USB_SERIALNO */
diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c
deleted file mode 100644
index 0d1340fb83..0000000000
--- a/chip/stm32/usb_dwc_console.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-static int last_tx_ok = 1;
-
-static int is_reset;
-static int is_enabled = 1;
-static int is_readonly;
-
-/* USB-Serial descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength		= USB_DT_INTERFACE_SIZE,
-	.bDescriptorType	= USB_DT_INTERFACE,
-	.bInterfaceNumber	= USB_IFACE_CONSOLE,
-	.bAlternateSetting	= 0,
-	.bNumEndpoints		= 2,
-	.bInterfaceClass	= USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass	= USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol	= USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface		= USB_STR_CONSOLE_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength		= USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType	= USB_DT_ENDPOINT,
-	.bEndpointAddress	= 0x80 | USB_EP_CONSOLE,
-	.bmAttributes		= 0x02 /* Bulk IN */,
-	.wMaxPacketSize		= USB_MAX_PACKET_SIZE,
-	.bInterval		 = 10,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength	    = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval	  = 0
-};
-
-static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE];
-static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE];
-
-static struct queue const tx_q = QUEUE_NULL(256, uint8_t);
-static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
-
-
-struct dwc_usb_ep ep_console_ctl = {
-	.max_packet = USB_MAX_PACKET_SIZE,
-	.tx_fifo = USB_EP_CONSOLE,
-	.out_pending = 0,
-	.out_data = 0,
-	.out_databuffer = ep_buf_tx,
-	.out_databuffer_max = sizeof(ep_buf_tx),
-	.in_packets = 0,
-	.in_pending = 0,
-	.in_data = 0,
-	.in_databuffer = ep_buf_rx,
-	.in_databuffer_max = sizeof(ep_buf_rx),
-};
-
-
-
-/* Let the USB HW IN-to-host FIFO transmit some bytes */
-static void usb_enable_tx(int len)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	ep->in_data = ep->in_databuffer;
-	ep->in_packets = 1;
-	ep->in_pending = len;
-
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) = 0;
-
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DIEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->in_data;
-
-	GR_USB_DIEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* Let the USB HW OUT-from-host FIFO receive some bytes */
-static void usb_enable_rx(int len)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	ep->out_data = ep->out_databuffer;
-	ep->out_pending = 0;
-
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) = 0;
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1);
-	GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len);
-	GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->out_data;
-
-	GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* True if the HW Rx/OUT FIFO has bytes for us. */
-static inline int rx_fifo_is_ready(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	return ep->out_pending;
-}
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-char buffer[65];
-static void rx_fifo_handler(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	int rx_in_fifo;
-	size_t added;
-
-	if (!rx_fifo_is_ready())
-		return;
-
-	rx_in_fifo = ep->out_pending;
-	added = QUEUE_ADD_UNITS(&rx_q, ep->out_databuffer, rx_in_fifo);
-
-	if (added != rx_in_fifo)
-		CPRINTF("DROP CONSOLE: %d/%d process\n", added, rx_in_fifo);
-
-	/* wake-up the console task */
-	console_has_input();
-
-	usb_enable_rx(USB_MAX_PACKET_SIZE);
-}
-DECLARE_DEFERRED(rx_fifo_handler);
-
-/* Rx/OUT interrupt handler */
-static void con_ep_rx(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-
-	if (GR_USB_DOEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA)
-		return;
-
-	/* Bytes received decrement DOEPTSIZ XFERSIZE */
-	if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) {
-		ep->out_pending =
-			ep->max_packet -
-			(GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
-			 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
-	}
-
-	/* Wake up the Rx FIFO handler */
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-
-	/* clear the RX/OUT interrupts */
-	GR_USB_DOEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-static inline int tx_fifo_is_ready(void)
-{
-	return !(GR_USB_DIEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA);
-}
-
-/* Try to send some bytes to the host */
-static void tx_fifo_handler(void)
-{
-	struct dwc_usb_ep *ep = &ep_console_ctl;
-	size_t count;
-
-	if (!is_reset)
-		return;
-
-	/* If the HW FIFO isn't ready, then we can't do anything right now. */
-	if (!tx_fifo_is_ready())
-		return;
-
-	count = QUEUE_REMOVE_UNITS(&tx_q,
-		ep->in_databuffer, USB_MAX_PACKET_SIZE);
-	if (count)
-		usb_enable_tx(count);
-}
-DECLARE_DEFERRED(tx_fifo_handler);
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-}
-
-/* Tx/IN interrupt handler */
-static void con_ep_tx(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-
-	/* clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-
-static void ep_event(enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	epN_reset(USB_EP_CONSOLE);
-
-	is_reset = 1;
-
-	/* Flush any queued data */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-
-	usb_enable_rx(USB_MAX_PACKET_SIZE);
-}
-
-
-USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !tx_fifo_is_ready())
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE || !is_reset) {
-			if (timestamp_expired(deadline, NULL) ||
-			    in_interrupt_context()) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-
-		return EC_SUCCESS;
-	}
-
-	last_tx_ok = queue_space(&tx_q);
-	return EC_SUCCESS;
-}
-static int __tx_char(void *context, int c)
-{
-	struct queue *state =
-			(struct queue *) context;
-
-	if (c == '\n' && __tx_char(state, '\r'))
-		return 1;
-
-	QUEUE_ADD_UNITS(state, &c, 1);
-	return 0;
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c;
-
-	if (!is_enabled)
-		return -1;
-
-	if (QUEUE_REMOVE_UNITS(&rx_q, &c, 1))
-		return c;
-
-	return -1;
-}
-
-int usb_puts(const char *outstr)
-{
-	int ret;
-	struct queue state;
-
-	if (is_readonly)
-		return EC_SUCCESS;
-
-	ret  = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	while (*outstr)
-		if (__tx_char(&state, *outstr++))
-			break;
-
-	if (queue_count(&state))
-		handle_output();
-
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int usb_putc(int c)
-{
-	char string[2];
-
-	string[0] = c;
-	string[1] = '\0';
-	return usb_puts(string);
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-	struct queue state;
-
-	if (is_readonly)
-		return EC_SUCCESS;
-
-	ret = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	ret = vfnprintf(__tx_char, &state, format, args);
-
-	if (queue_count(&state))
-		handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h
deleted file mode 100644
index ab2206d359..0000000000
--- a/chip/stm32/usb_dwc_console.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CHIP_STM32_USB_DWC_CONSOLE_H
-#define __CHIP_STM32_USB_DWC_CONSOLE_H
-
-#include "usb_hw.h"
-
-extern struct dwc_usb_ep ep_console_ctl;
-
-#endif  /* __CHIP_STM32_USB_DWC_CONSOLE_H */
diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h
deleted file mode 100644
index d1fe07cb87..0000000000
--- a/chip/stm32/usb_dwc_hw.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_DWC_HW_H
-#define __CROS_EC_USB_DWC_HW_H
-
-#include "usb_dwc_registers.h"
-
-/* Helpers for endpoint declaration */
-#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix)
-#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx)
-#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx)
-#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt)
-/* Used to check function types are correct (attribute alias does not do it) */
-#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck)
-#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
-#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
-
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)	  \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
-
-/* Endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
-struct usb_setup_packet;
-/* EP0 Interface handler callbacks */
-extern int (*usb_iface_request[]) (struct usb_setup_packet *req);
-
-
-/* True if the HW Rx/OUT FIFO is currently listening. */
-int rx_ep_is_active(uint32_t ep_num);
-
-/* Number of bytes the HW Rx/OUT FIFO has for us.
- *
- * @param ep_num        USB endpoint
- *
- * @returns             number of bytes ready, zero if none.
- */
-int rx_ep_pending(uint32_t ep_num);
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-int tx_ep_is_ready(uint32_t ep_num);
-
-/* Write packets of data IN to the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the write completion event.
- *
- * @param ep_num        USB endpoint to write
- * @param len           number of bytes to write
- * @param data          pointer of data to write
- *
- * @return              bytes written
- */
-int usb_write_ep(uint32_t ep_num, int len, void *data);
-
-/* Read a packet of data OUT from the host.
- *
- * This function uses DMA, so the *data write buffer
- * must persist until the read completion event.
- *
- * @param ep_num        USB endpoint to read
- * @param len           number of bytes to read
- * @param data          pointer of data to read
- *
- * @return              EC_SUCCESS on success
- */
-int usb_read_ep(uint32_t ep_num, int len, void *data);
-
-/* Tx/IN interrupt handler */
-void usb_epN_tx(uint32_t ep_num);
-
-/* Rx/OUT endpoint interrupt handler */
-void usb_epN_rx(uint32_t ep_num);
-
-/* Reset endpoint HW block. */
-void epN_reset(uint32_t ep_num);
-
-/*
- * Declare any interface-specific control request handlers. These Setup packets
- * arrive on the control endpoint (EP0), but are handled by the interface code.
- * The callback must prepare the EP0 IN or OUT FIFOs and return the number of
- * bytes placed in the IN FIFO. A negative return value will STALL the response
- * (and thus indicate error to the host).
- */
-#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)				\
-	int _IFACE_HANDLER(num)(struct usb_setup_packet *req)	\
-		__attribute__ ((alias(STRINGIFY(handler))))
-
-#endif	/* __CROS_EC_USB_DWC_HW_H */
diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h
deleted file mode 100644
index e44002268a..0000000000
--- a/chip/stm32/usb_dwc_i2c.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_DWC_I2C_H
-#define __CROS_EC_USB_DWC_I2C_H
-#include "usb_i2c.h"
-
-/* I2C over USB interface. This gets declared in usb_i2c.c */
-extern struct dwc_usb_ep i2c_usb__ep_ctl;
-
-#endif /* __CROS_EC_USB_DWC_I2C_H */
diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h
deleted file mode 100644
index faac9ca775..0000000000
--- a/chip/stm32/usb_dwc_registers.h
+++ /dev/null
@@ -1,7533 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32F446 USB
- */
-
-#ifndef __CHIP_STM32_USB_DWC_REGISTERS_H
-#define __CHIP_STM32_USB_DWC_REGISTERS_H
-
-/* Endpoint state */
-struct dwc_usb_ep {
-	int max_packet;
-	int tx_fifo;
-
-	int out_pending;
-	int out_expected;
-	uint8_t *out_data;
-	uint8_t *out_databuffer;
-	int out_databuffer_max;
-	const struct deferred_data *rx_deferred;
-
-	int in_packets;
-	int in_pending;
-	uint8_t *in_data;
-	uint8_t *in_databuffer;
-	int in_databuffer_max;
-	const struct deferred_data *tx_deferred;
-};
-
-/* USB state */
-enum dwc_usb_speed {
-	USB_SPEED_FS = 0,
-	USB_SPEED_HS,
-};
-
-enum dwc_usb_phy {
-	USB_PHY_INTERNAL = 0,
-	USB_PHY_ULPI,
-};
-
-struct dwc_usb {
-	struct dwc_usb_ep *ep[USB_EP_COUNT];
-	enum dwc_usb_speed speed;
-	enum dwc_usb_phy phy_type;
-	int dma_en;
-	/* IRQ must be STM32_IRQ_OTG_FS / STM32_IRQ_OTG_HS */
-	int irq;
-};
-
-extern struct dwc_usb_ep ep0_ctl;
-extern struct dwc_usb usb_ctl;
-
-/*
- * Added Alias Module Family Base Address to 0-instance Module Base Address
- * Simplify GBASE(mname) macro
- */
-#define GC_MODULE_OFFSET         0x10000
-
-#define GBASE(mname)      \
-	GC_ ## mname ## _BASE_ADDR
-#define GOFFSET(mname, rname)  \
-	GC_ ## mname ## _ ## rname ## _OFFSET
-
-#define GREG8(mname, rname) \
-	REG8(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32(mname, rname) \
-	REG32(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32_ADDR(mname, rname) \
-	REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname))
-#define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value))
-#define GREAD(mname, rname)	    GREG32(mname, rname)
-
-#define GFIELD_MASK(mname, rname, fname) \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK
-
-#define GFIELD_LSB(mname, rname, fname)  \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB
-
-#define GREAD_FIELD(mname, rname, fname) \
-	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD(mname, rname, fname, fval) \
-	(GREG32(mname, rname) = \
-	((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-
-#define GBASE_I(mname, i)     (GBASE(mname) + i*GC_MODULE_OFFSET)
-
-#define GREG32_I(mname, i, rname) \
-		REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GREG32_ADDR_I(mname, i, rname) \
-		REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value))
-#define GREAD_I(mname, i, rname)	        GREG32_I(mname, i, rname)
-
-#define GREAD_FIELD_I(mname, i, rname, fname) \
-	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \
-	(GREG32_I(mname, i, rname) = \
-	((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-/* Replace masked bits with val << lsb */
-#define REG_WRITE_MLV(reg, mask, lsb, val) \
-		(reg = ((reg & ~mask) | ((val << lsb) & mask)))
-
-
-/* USB device controller */
-#define GR_USB_REG(off)               REG32(GC_USB_BASE_ADDR + (off))
-#define GR_USB_GOTGCTL                GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
-#define GR_USB_GOTGINT                GR_USB_REG(GC_USB_GOTGINT_OFFSET)
-#define GR_USB_GAHBCFG                GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
-#define GR_USB_GUSBCFG                GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
-#define GR_USB_GRSTCTL                GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
-#define GR_USB_GINTSTS                GR_USB_REG(GC_USB_GINTSTS_OFFSET)
-#define   GINTSTS(bit)                (1 << GC_USB_GINTSTS_ ## bit ## _LSB)
-#define GR_USB_GINTMSK                GR_USB_REG(GC_USB_GINTMSK_OFFSET)
-#define   GINTMSK(bit)                (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB)
-#define GR_USB_GRXSTSR                GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
-#define GR_USB_GRXSTSP                GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
-#define GR_USB_GRXFSIZ                GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
-#define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
-/*#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)*/
-#define GR_USB_GCCFG                  GR_USB_REG(GC_USB_GCCFG_OFFSET)
-#define  GCCFG_VBDEN            BIT(21)
-#define  GCCFG_PWRDWN           BIT(16)
-#define GR_USB_PCGCCTL                GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
-
-#define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
-#define GR_USB_GHWCFG1                GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
-#define GR_USB_GHWCFG2                GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
-#define GR_USB_GHWCFG3                GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
-#define GR_USB_GHWCFG4                GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
-#define GR_USB_GDFIFOCFG              GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
-#define GR_USB_DIEPTXF(n)	\
-	GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
-#define GR_USB_DCFG                   GR_USB_REG(GC_USB_DCFG_OFFSET)
-#define GR_USB_DCTL                   GR_USB_REG(GC_USB_DCTL_OFFSET)
-#define GR_USB_DSTS                   GR_USB_REG(GC_USB_DSTS_OFFSET)
-#define GR_USB_DIEPMSK                GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
-#define GR_USB_DOEPMSK                GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
-#define GR_USB_DAINT                  GR_USB_REG(GC_USB_DAINT_OFFSET)
-#define GR_USB_DAINTMSK               GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
-#define  DAINT_INEP(ep)               (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
-#define  DAINT_OUTEP(ep)	\
-	(1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
-#define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
-#define  DTHRCTL_TXTHRLEN_6           (0x40 << 2)
-#define  DTHRCTL_RXTHRLEN_6           (0x40 << 17)
-#define  DTHRCTL_RXTHREN              BIT(16)
-#define  DTHRCTL_ISOTHREN             BIT(1)
-#define  DTHRCTL_NONISOTHREN          BIT(0)
-#define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
-
-#define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
-#define GR_USB_EPOREG(off, n)         GR_USB_REG(0xb00 + (n) * 0x20 + (off))
-#define GR_USB_DIEPCTL(n)             GR_USB_EPIREG(0x00, n)
-#define GR_USB_DIEPINT(n)             GR_USB_EPIREG(0x08, n)
-#define GR_USB_DIEPTSIZ(n)            GR_USB_EPIREG(0x10, n)
-#define GR_USB_DIEPDMA(n)             GR_USB_EPIREG(0x14, n)
-#define GR_USB_DTXFSTS(n)             GR_USB_EPIREG(0x18, n)
-#define GR_USB_DIEPDMAB(n)            GR_USB_EPIREG(0x1c, n)
-#define GR_USB_DOEPCTL(n)             GR_USB_EPOREG(0x00, n)
-#define GR_USB_DOEPINT(n)             GR_USB_EPOREG(0x08, n)
-#define GR_USB_DOEPTSIZ(n)            GR_USB_EPOREG(0x10, n)
-#define GR_USB_DOEPDMA(n)             GR_USB_EPOREG(0x14, n)
-#define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
-
-#define GOTGCTL_BVALOEN               BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
-#define GOTGCTL_BVALOVAL              BIT(7)
-
-/* Bit 5 */
-#define GAHBCFG_DMA_EN                BIT(GC_USB_GAHBCFG_DMAEN_LSB)
-/* Bit 1 */
-#define GAHBCFG_GLB_INTR_EN           BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
-/* HS Burst Len */
-#define GAHBCFG_HBSTLEN_INCR4         (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
-/* Bit 7 */
-#define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
-#define GAHBCFG_TXFELVL               GAHBCFG_NP_TXF_EMP_LVL
-#define GAHBCFG_PTXFELVL              BIT(8)
-
-#define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
-				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
-#define GUSBCFG_USBTRDTIM(n)          (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \
-				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
-/* Force device mode */
-#define GUSBCFG_FDMOD                 BIT(GC_USB_GUSBCFG_FDMOD_LSB)
-#define GUSBCFG_PHYSEL                BIT(6)
-#define GUSBCFG_SRPCAP                BIT(8)
-#define GUSBCFG_HNPCAP                BIT(9)
-#define GUSBCFG_ULPIFSLS              BIT(17)
-#define GUSBCFG_ULPIAR                BIT(18)
-#define GUSBCFG_ULPICSM               BIT(19)
-#define GUSBCFG_ULPIEVBUSD            BIT(20)
-#define GUSBCFG_ULPIEVBUSI            BIT(21)
-#define GUSBCFG_TSDPS                 BIT(22)
-#define GUSBCFG_PCCI                  BIT(23)
-#define GUSBCFG_PTCI                  BIT(24)
-#define GUSBCFG_ULPIIPD               BIT(25)
-#define GUSBCFG_TSDPS                 BIT(22)
-
-
-#define GRSTCTL_CSFTRST               BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
-#define GRSTCTL_AHBIDLE               BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
-#define GRSTCTL_TXFFLSH               BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
-#define GRSTCTL_RXFFLSH               BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
-#define GRSTCTL_TXFNUM(n)	\
-	(((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK)
-
-#define DCFG_DEVSPD_HSULPI            (0 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FSULPI            BIT(GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FS48              (3 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVADDR(a)	\
-	(((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK)
-#define DCFG_NZLSOHSK                 BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
-
-#define DCTL_SFTDISCON                BIT(GC_USB_DCTL_SFTDISCON_LSB)
-#define DCTL_CGOUTNAK                 BIT(GC_USB_DCTL_CGOUTNAK_LSB)
-#define DCTL_CGNPINNAK                BIT(GC_USB_DCTL_CGNPINNAK_LSB)
-#define DCTL_PWRONPRGDONE             BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
-
-/* Device Endpoint Common IN Interrupt Mask bits */
-#define DIEPMSK_AHBERRMSK             BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
-#define DIEPMSK_BNAININTRMSK          BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
-#define DIEPMSK_EPDISBLDMSK           BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
-#define DIEPMSK_INEPNAKEFFMSK         BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
-#define DIEPMSK_INTKNEPMISMSK         BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
-#define DIEPMSK_INTKNTXFEMPMSK        BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
-#define DIEPMSK_NAKMSK                BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
-#define DIEPMSK_TIMEOUTMSK            BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
-#define DIEPMSK_TXFIFOUNDRNMSK        BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
-#define DIEPMSK_XFERCOMPLMSK          BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint Common OUT Interrupt Mask bits */
-#define DOEPMSK_AHBERRMSK             BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
-#define DOEPMSK_BBLEERRMSK            BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
-#define DOEPMSK_BNAOUTINTRMSK         BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
-#define DOEPMSK_EPDISBLDMSK           BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
-#define DOEPMSK_NAKMSK                BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
-#define DOEPMSK_NYETMSK               BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
-#define DOEPMSK_OUTPKTERRMSK          BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
-#define DOEPMSK_OUTTKNEPDISMSK        BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
-#define DOEPMSK_SETUPMSK              BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
-#define DOEPMSK_STSPHSERCVDMSK        BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
-#define DOEPMSK_XFERCOMPLMSK          BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint-n IN Interrupt Register bits */
-#define DIEPINT_AHBERR             BIT(GC_USB_DIEPINT0_AHBERR_LSB)
-#define DIEPINT_BBLEERR            BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
-#define DIEPINT_BNAINTR            BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
-#define DIEPINT_EPDISBLD           BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
-#define DIEPINT_INEPNAKEFF         BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
-#define DIEPINT_INTKNEPMIS         BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
-#define DIEPINT_INTKNTXFEMP        BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
-#define DIEPINT_NAKINTRPT          BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
-#define DIEPINT_NYETINTRPT         BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
-#define DIEPINT_PKTDRPSTS          BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
-#define DIEPINT_TIMEOUT            BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
-#define DIEPINT_TXFEMP             BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
-#define DIEPINT_TXFIFOUNDRN        BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
-#define DIEPINT_XFERCOMPL          BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
-
-/* Device Endpoint-n OUT Interrupt Register bits */
-#define DOEPINT_AHBERR             BIT(GC_USB_DOEPINT0_AHBERR_LSB)
-#define DOEPINT_BACK2BACKSETUP     BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
-#define DOEPINT_BBLEERR            BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
-#define DOEPINT_BNAINTR            BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
-#define DOEPINT_EPDISBLD           BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
-#define DOEPINT_NAKINTRPT          BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
-#define DOEPINT_NYETINTRPT         BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
-#define DOEPINT_OUTPKTERR          BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
-#define DOEPINT_OUTTKNEPDIS        BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
-#define DOEPINT_PKTDRPSTS          BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
-#define DOEPINT_SETUP              BIT(GC_USB_DOEPINT0_SETUP_LSB)
-#define DOEPINT_STSPHSERCVD        BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
-#define DOEPINT_STUPPKTRCVD        BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
-#define DOEPINT_XFERCOMPL          BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
-
-#define DXEPCTL_EPTYPE_CTRL           (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_ISO            (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_BULK           (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_INT            (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_MASK           GC_USB_DIEPCTL0_EPTYPE_MASK
-#define DXEPCTL_TXFNUM(n)             ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
-#define DXEPCTL_STALL                 BIT(GC_USB_DIEPCTL0_STALL_LSB)
-#define DXEPCTL_CNAK                  BIT(GC_USB_DIEPCTL0_CNAK_LSB)
-#define DXEPCTL_DPID                  BIT(GC_USB_DIEPCTL0_DPID_LSB)
-#define DXEPCTL_SNAK                  BIT(GC_USB_DIEPCTL0_SNAK_LSB)
-#define DXEPCTL_NAKSTS                BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
-#define DXEPCTL_EPENA                 BIT(GC_USB_DIEPCTL0_EPENA_LSB)
-#define DXEPCTL_EPDIS                 BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
-#define DXEPCTL_USBACTEP              BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
-#define DXEPCTL_MPS64                 (0 << GC_USB_DIEPCTL0_MPS_LSB)
-#define DXEPCTL_MPS(cnt)              ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
-
-#define DXEPTSIZ_SUPCNT(n)            ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
-#define DXEPTSIZ_PKTCNT(n)            ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
-#define DXEPTSIZ_XFERSIZE(n)          ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
-
-#define DOEPDMA_BS_HOST_RDY           (0 << 30)
-#define DOEPDMA_BS_DMA_BSY            (1 << 30)
-#define DOEPDMA_BS_DMA_DONE           (2 << 30)
-#define DOEPDMA_BS_HOST_BSY           (3 << 30)
-#define DOEPDMA_BS_MASK               (3 << 30)
-#define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  BIT(27)
-#define DOEPDMA_SP                    BIT(26)
-#define DOEPDMA_IOC                   BIT(25)
-#define DOEPDMA_SR                    BIT(24)
-#define DOEPDMA_MTRF                  BIT(23)
-#define DOEPDMA_NAK                   BIT(16)
-#define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
-
-#define DIEPDMA_BS_HOST_RDY           (0 << 30)
-#define DIEPDMA_BS_DMA_BSY            (1 << 30)
-#define DIEPDMA_BS_DMA_DONE           (2 << 30)
-#define DIEPDMA_BS_HOST_BSY           (3 << 30)
-#define DIEPDMA_BS_MASK               (3 << 30)
-#define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  BIT(27)
-#define DIEPDMA_SP                    BIT(26)
-#define DIEPDMA_IOC                   BIT(25)
-#define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
-
-
-
-/* Register defs referenced from DWC block in CR50. This is not a native
- * ST block, so we'll use this modified regdefs list.
- */
-
-#define GC_USB_FS_BASE_ADDR                        0x50000000
-#define GC_USB_HS_BASE_ADDR                        0x40040000
-#ifdef CONFIG_USB_DWC_FS
-#define GC_USB_BASE_ADDR                         GC_USB_FS_BASE_ADDR
-#else
-#define GC_USB_BASE_ADDR                         GC_USB_HS_BASE_ADDR
-#endif
-
-#define GC_USB_GOTGCTL_OFFSET                    0x0
-#define GC_USB_GOTGCTL_DEFAULT                   0x0
-#define GC_USB_GOTGINT_OFFSET                    0x4
-#define GC_USB_GOTGINT_DEFAULT                   0x0
-#define GC_USB_GAHBCFG_OFFSET                    0x8
-#define GC_USB_GAHBCFG_DEFAULT                   0x0
-#define GC_USB_GUSBCFG_OFFSET                    0xc
-#define GC_USB_GUSBCFG_DEFAULT                   0x0
-#define GC_USB_GRSTCTL_OFFSET                    0x10
-#define GC_USB_GRSTCTL_DEFAULT                   0x0
-#define GC_USB_GINTSTS_OFFSET                    0x14
-#define GC_USB_GINTSTS_DEFAULT                   0x0
-#define GC_USB_GINTMSK_OFFSET                    0x18
-#define GC_USB_GINTMSK_DEFAULT                   0x0
-#define GC_USB_GRXSTSR_OFFSET                    0x1c
-#define GC_USB_GRXSTSR_DEFAULT                   0x0
-#define GC_USB_GRXSTSP_OFFSET                    0x20
-#define GC_USB_GRXSTSP_DEFAULT                   0x0
-#define GC_USB_GRXFSIZ_OFFSET                    0x24
-#define GC_USB_GRXFSIZ_DEFAULT                   0x0
-#define GC_USB_GNPTXFSIZ_OFFSET                  0x28
-#define GC_USB_GNPTXFSIZ_DEFAULT                 0x0
-
-#define GC_USB_GCCFG_OFFSET                      0x38
-#define GC_USB_GCCFG_DEFAULT                     0x0
-#define GC_USB_GUID_OFFSET                       0x3c
-#define GC_USB_GUID_DEFAULT                      0x0
-#define GC_USB_GSNPSID_OFFSET                    0x40
-#define GC_USB_GSNPSID_DEFAULT                   0x0
-#define GC_USB_GHWCFG1_OFFSET                    0x44
-#define GC_USB_GHWCFG1_DEFAULT                   0x0
-#define GC_USB_GHWCFG2_OFFSET                    0x48
-#define GC_USB_GHWCFG2_DEFAULT                   0x0
-#define GC_USB_GHWCFG3_OFFSET                    0x4c
-#define GC_USB_GHWCFG3_DEFAULT                   0x0
-#define GC_USB_GHWCFG4_OFFSET                    0x50
-#define GC_USB_GHWCFG4_DEFAULT                   0x0
-#define GC_USB_GDFIFOCFG_OFFSET                  0x5c
-#define GC_USB_GDFIFOCFG_DEFAULT                 0x0
-#define GC_USB_DIEPTXF1_OFFSET                   0x104
-#define GC_USB_DIEPTXF1_DEFAULT                  0x1000
-#define GC_USB_DIEPTXF2_OFFSET                   0x108
-#define GC_USB_DIEPTXF2_DEFAULT                  0x0
-#define GC_USB_DIEPTXF3_OFFSET                   0x10c
-#define GC_USB_DIEPTXF3_DEFAULT                  0x0
-#define GC_USB_DIEPTXF4_OFFSET                   0x110
-#define GC_USB_DIEPTXF4_DEFAULT                  0x0
-#define GC_USB_DIEPTXF5_OFFSET                   0x114
-#define GC_USB_DIEPTXF5_DEFAULT                  0x0
-#define GC_USB_DIEPTXF6_OFFSET                   0x118
-#define GC_USB_DIEPTXF6_DEFAULT                  0x0
-#define GC_USB_DIEPTXF7_OFFSET                   0x11c
-#define GC_USB_DIEPTXF7_DEFAULT                  0x0
-#define GC_USB_DIEPTXF8_OFFSET                   0x120
-#define GC_USB_DIEPTXF8_DEFAULT                  0x0
-#define GC_USB_DIEPTXF9_OFFSET                   0x124
-#define GC_USB_DIEPTXF9_DEFAULT                  0x0
-#define GC_USB_DIEPTXF10_OFFSET                  0x128
-#define GC_USB_DIEPTXF10_DEFAULT                 0x0
-#define GC_USB_DIEPTXF11_OFFSET                  0x12c
-#define GC_USB_DIEPTXF11_DEFAULT                 0x0
-#define GC_USB_DIEPTXF12_OFFSET                  0x130
-#define GC_USB_DIEPTXF12_DEFAULT                 0x0
-#define GC_USB_DIEPTXF13_OFFSET                  0x134
-#define GC_USB_DIEPTXF13_DEFAULT                 0x0
-#define GC_USB_DIEPTXF14_OFFSET                  0x138
-#define GC_USB_DIEPTXF14_DEFAULT                 0x0
-#define GC_USB_DIEPTXF15_OFFSET                  0x13c
-#define GC_USB_DIEPTXF15_DEFAULT                 0x0
-#define GC_USB_DCFG_OFFSET                       0x800
-#define GC_USB_DCFG_DEFAULT                      0x8000000
-#define GC_USB_DCTL_OFFSET                       0x804
-#define GC_USB_DCTL_DEFAULT                      0x0
-#define GC_USB_DSTS_OFFSET                       0x808
-#define GC_USB_DSTS_DEFAULT                      0x0
-#define GC_USB_DIEPMSK_OFFSET                    0x810
-#define GC_USB_DIEPMSK_DEFAULT                   0x80
-#define GC_USB_DOEPMSK_OFFSET                    0x814
-#define GC_USB_DOEPMSK_DEFAULT                   0x0
-#define GC_USB_DAINT_OFFSET                      0x818
-#define GC_USB_DAINT_DEFAULT                     0x0
-#define GC_USB_DAINTMSK_OFFSET                   0x81c
-#define GC_USB_DAINTMSK_DEFAULT                  0x0
-#define GC_USB_DVBUSDIS_OFFSET                   0x828
-#define GC_USB_DVBUSDIS_DEFAULT                  0x0
-#define GC_USB_DVBUSPULSE_OFFSET                 0x82c
-#define GC_USB_DVBUSPULSE_DEFAULT                0x0
-#define GC_USB_DTHRCTL_OFFSET                    0x830
-#define GC_USB_DTHRCTL_DEFAULT                   0x0
-#define GC_USB_DIEPEMPMSK_OFFSET                 0x834
-#define GC_USB_DIEPEMPMSK_DEFAULT                0x0
-#define GC_USB_DIEPCTL0_OFFSET                   0x900
-#define GC_USB_DIEPCTL0_DEFAULT                  0x0
-#define GC_USB_DIEPINT0_OFFSET                   0x908
-#define GC_USB_DIEPINT0_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ0_OFFSET                  0x910
-#define GC_USB_DIEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DIEPDMA0_OFFSET                   0x914
-#define GC_USB_DIEPDMA0_DEFAULT                  0x0
-#define GC_USB_DTXFSTS0_OFFSET                   0x918
-#define GC_USB_DTXFSTS0_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB0_OFFSET                  0x91c
-#define GC_USB_DIEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DIEPCTL1_OFFSET                   0x920
-#define GC_USB_DIEPCTL1_DEFAULT                  0x0
-#define GC_USB_DIEPINT1_OFFSET                   0x928
-#define GC_USB_DIEPINT1_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ1_OFFSET                  0x930
-#define GC_USB_DIEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DIEPDMA1_OFFSET                   0x934
-#define GC_USB_DIEPDMA1_DEFAULT                  0x0
-#define GC_USB_DTXFSTS1_OFFSET                   0x938
-#define GC_USB_DTXFSTS1_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB1_OFFSET                  0x93c
-#define GC_USB_DIEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DIEPCTL2_OFFSET                   0x940
-#define GC_USB_DIEPCTL2_DEFAULT                  0x0
-#define GC_USB_DIEPINT2_OFFSET                   0x948
-#define GC_USB_DIEPINT2_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ2_OFFSET                  0x950
-#define GC_USB_DIEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DIEPDMA2_OFFSET                   0x954
-#define GC_USB_DIEPDMA2_DEFAULT                  0x0
-#define GC_USB_DTXFSTS2_OFFSET                   0x958
-#define GC_USB_DTXFSTS2_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB2_OFFSET                  0x95c
-#define GC_USB_DIEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DIEPCTL3_OFFSET                   0x960
-#define GC_USB_DIEPCTL3_DEFAULT                  0x0
-#define GC_USB_DIEPINT3_OFFSET                   0x968
-#define GC_USB_DIEPINT3_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ3_OFFSET                  0x970
-#define GC_USB_DIEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DIEPDMA3_OFFSET                   0x974
-#define GC_USB_DIEPDMA3_DEFAULT                  0x0
-#define GC_USB_DTXFSTS3_OFFSET                   0x978
-#define GC_USB_DTXFSTS3_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB3_OFFSET                  0x97c
-#define GC_USB_DIEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DIEPCTL4_OFFSET                   0x980
-#define GC_USB_DIEPCTL4_DEFAULT                  0x0
-#define GC_USB_DIEPINT4_OFFSET                   0x988
-#define GC_USB_DIEPINT4_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ4_OFFSET                  0x990
-#define GC_USB_DIEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DIEPDMA4_OFFSET                   0x994
-#define GC_USB_DIEPDMA4_DEFAULT                  0x0
-#define GC_USB_DTXFSTS4_OFFSET                   0x998
-#define GC_USB_DTXFSTS4_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB4_OFFSET                  0x99c
-#define GC_USB_DIEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DIEPCTL5_OFFSET                   0x9a0
-#define GC_USB_DIEPCTL5_DEFAULT                  0x0
-#define GC_USB_DIEPINT5_OFFSET                   0x9a8
-#define GC_USB_DIEPINT5_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ5_OFFSET                  0x9b0
-#define GC_USB_DIEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DIEPDMA5_OFFSET                   0x9b4
-#define GC_USB_DIEPDMA5_DEFAULT                  0x0
-#define GC_USB_DTXFSTS5_OFFSET                   0x9b8
-#define GC_USB_DTXFSTS5_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB5_OFFSET                  0x9bc
-#define GC_USB_DIEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DIEPCTL6_OFFSET                   0x9c0
-#define GC_USB_DIEPCTL6_DEFAULT                  0x0
-#define GC_USB_DIEPINT6_OFFSET                   0x9c8
-#define GC_USB_DIEPINT6_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ6_OFFSET                  0x9d0
-#define GC_USB_DIEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DIEPDMA6_OFFSET                   0x9d4
-#define GC_USB_DIEPDMA6_DEFAULT                  0x0
-#define GC_USB_DTXFSTS6_OFFSET                   0x9d8
-#define GC_USB_DTXFSTS6_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB6_OFFSET                  0x9dc
-#define GC_USB_DIEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DIEPCTL7_OFFSET                   0x9e0
-#define GC_USB_DIEPCTL7_DEFAULT                  0x0
-#define GC_USB_DIEPINT7_OFFSET                   0x9e8
-#define GC_USB_DIEPINT7_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ7_OFFSET                  0x9f0
-#define GC_USB_DIEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DIEPDMA7_OFFSET                   0x9f4
-#define GC_USB_DIEPDMA7_DEFAULT                  0x0
-#define GC_USB_DTXFSTS7_OFFSET                   0x9f8
-#define GC_USB_DTXFSTS7_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB7_OFFSET                  0x9fc
-#define GC_USB_DIEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DIEPCTL8_OFFSET                   0xa00
-#define GC_USB_DIEPCTL8_DEFAULT                  0x0
-#define GC_USB_DIEPINT8_OFFSET                   0xa08
-#define GC_USB_DIEPINT8_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ8_OFFSET                  0xa10
-#define GC_USB_DIEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DIEPDMA8_OFFSET                   0xa14
-#define GC_USB_DIEPDMA8_DEFAULT                  0x0
-#define GC_USB_DTXFSTS8_OFFSET                   0xa18
-#define GC_USB_DTXFSTS8_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB8_OFFSET                  0xa1c
-#define GC_USB_DIEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DIEPCTL9_OFFSET                   0xa20
-#define GC_USB_DIEPCTL9_DEFAULT                  0x0
-#define GC_USB_DIEPINT9_OFFSET                   0xa28
-#define GC_USB_DIEPINT9_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ9_OFFSET                  0xa30
-#define GC_USB_DIEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DIEPDMA9_OFFSET                   0xa34
-#define GC_USB_DIEPDMA9_DEFAULT                  0x0
-#define GC_USB_DTXFSTS9_OFFSET                   0xa38
-#define GC_USB_DTXFSTS9_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB9_OFFSET                  0xa3c
-#define GC_USB_DIEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DIEPCTL10_OFFSET                  0xa40
-#define GC_USB_DIEPCTL10_DEFAULT                 0x0
-#define GC_USB_DIEPINT10_OFFSET                  0xa48
-#define GC_USB_DIEPINT10_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ10_OFFSET                 0xa50
-#define GC_USB_DIEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DIEPDMA10_OFFSET                  0xa54
-#define GC_USB_DIEPDMA10_DEFAULT                 0x0
-#define GC_USB_DTXFSTS10_OFFSET                  0xa58
-#define GC_USB_DTXFSTS10_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB10_OFFSET                 0xa5c
-#define GC_USB_DIEPDMAB10_DEFAULT                0x0
-#define GC_USB_DIEPCTL11_OFFSET                  0xa60
-#define GC_USB_DIEPCTL11_DEFAULT                 0x0
-#define GC_USB_DIEPINT11_OFFSET                  0xa68
-#define GC_USB_DIEPINT11_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ11_OFFSET                 0xa70
-#define GC_USB_DIEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DIEPDMA11_OFFSET                  0xa74
-#define GC_USB_DIEPDMA11_DEFAULT                 0x0
-#define GC_USB_DTXFSTS11_OFFSET                  0xa78
-#define GC_USB_DTXFSTS11_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB11_OFFSET                 0xa7c
-#define GC_USB_DIEPDMAB11_DEFAULT                0x0
-#define GC_USB_DIEPCTL12_OFFSET                  0xa80
-#define GC_USB_DIEPCTL12_DEFAULT                 0x0
-#define GC_USB_DIEPINT12_OFFSET                  0xa88
-#define GC_USB_DIEPINT12_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ12_OFFSET                 0xa90
-#define GC_USB_DIEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DIEPDMA12_OFFSET                  0xa94
-#define GC_USB_DIEPDMA12_DEFAULT                 0x0
-#define GC_USB_DTXFSTS12_OFFSET                  0xa98
-#define GC_USB_DTXFSTS12_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB12_OFFSET                 0xa9c
-#define GC_USB_DIEPDMAB12_DEFAULT                0x0
-#define GC_USB_DIEPCTL13_OFFSET                  0xaa0
-#define GC_USB_DIEPCTL13_DEFAULT                 0x0
-#define GC_USB_DIEPINT13_OFFSET                  0xaa8
-#define GC_USB_DIEPINT13_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ13_OFFSET                 0xab0
-#define GC_USB_DIEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DIEPDMA13_OFFSET                  0xab4
-#define GC_USB_DIEPDMA13_DEFAULT                 0x0
-#define GC_USB_DTXFSTS13_OFFSET                  0xab8
-#define GC_USB_DTXFSTS13_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB13_OFFSET                 0xabc
-#define GC_USB_DIEPDMAB13_DEFAULT                0x0
-#define GC_USB_DIEPCTL14_OFFSET                  0xac0
-#define GC_USB_DIEPCTL14_DEFAULT                 0x0
-#define GC_USB_DIEPINT14_OFFSET                  0xac8
-#define GC_USB_DIEPINT14_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ14_OFFSET                 0xad0
-#define GC_USB_DIEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DIEPDMA14_OFFSET                  0xad4
-#define GC_USB_DIEPDMA14_DEFAULT                 0x0
-#define GC_USB_DTXFSTS14_OFFSET                  0xad8
-#define GC_USB_DTXFSTS14_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB14_OFFSET                 0xadc
-#define GC_USB_DIEPDMAB14_DEFAULT                0x0
-#define GC_USB_DIEPCTL15_OFFSET                  0xae0
-#define GC_USB_DIEPCTL15_DEFAULT                 0x0
-#define GC_USB_DIEPINT15_OFFSET                  0xae8
-#define GC_USB_DIEPINT15_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ15_OFFSET                 0xaf0
-#define GC_USB_DIEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DIEPDMA15_OFFSET                  0xaf4
-#define GC_USB_DIEPDMA15_DEFAULT                 0x0
-#define GC_USB_DTXFSTS15_OFFSET                  0xaf8
-#define GC_USB_DTXFSTS15_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB15_OFFSET                 0xafc
-#define GC_USB_DIEPDMAB15_DEFAULT                0x0
-#define GC_USB_DOEPCTL0_OFFSET                   0xb00
-#define GC_USB_DOEPCTL0_DEFAULT                  0x0
-#define GC_USB_DOEPINT0_OFFSET                   0xb08
-#define GC_USB_DOEPINT0_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ0_OFFSET                  0xb10
-#define GC_USB_DOEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DOEPDMA0_OFFSET                   0xb14
-#define GC_USB_DOEPDMA0_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB0_OFFSET                  0xb1c
-#define GC_USB_DOEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DOEPCTL1_OFFSET                   0xb20
-#define GC_USB_DOEPCTL1_DEFAULT                  0x0
-#define GC_USB_DOEPINT1_OFFSET                   0xb28
-#define GC_USB_DOEPINT1_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ1_OFFSET                  0xb30
-#define GC_USB_DOEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DOEPDMA1_OFFSET                   0xb34
-#define GC_USB_DOEPDMA1_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB1_OFFSET                  0xb3c
-#define GC_USB_DOEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DOEPCTL2_OFFSET                   0xb40
-#define GC_USB_DOEPCTL2_DEFAULT                  0x0
-#define GC_USB_DOEPINT2_OFFSET                   0xb48
-#define GC_USB_DOEPINT2_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ2_OFFSET                  0xb50
-#define GC_USB_DOEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DOEPDMA2_OFFSET                   0xb54
-#define GC_USB_DOEPDMA2_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB2_OFFSET                  0xb5c
-#define GC_USB_DOEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DOEPCTL3_OFFSET                   0xb60
-#define GC_USB_DOEPCTL3_DEFAULT                  0x0
-#define GC_USB_DOEPINT3_OFFSET                   0xb68
-#define GC_USB_DOEPINT3_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ3_OFFSET                  0xb70
-#define GC_USB_DOEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DOEPDMA3_OFFSET                   0xb74
-#define GC_USB_DOEPDMA3_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB3_OFFSET                  0xb7c
-#define GC_USB_DOEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DOEPCTL4_OFFSET                   0xb80
-#define GC_USB_DOEPCTL4_DEFAULT                  0x0
-#define GC_USB_DOEPINT4_OFFSET                   0xb88
-#define GC_USB_DOEPINT4_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ4_OFFSET                  0xb90
-#define GC_USB_DOEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DOEPDMA4_OFFSET                   0xb94
-#define GC_USB_DOEPDMA4_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB4_OFFSET                  0xb9c
-#define GC_USB_DOEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DOEPCTL5_OFFSET                   0xba0
-#define GC_USB_DOEPCTL5_DEFAULT                  0x0
-#define GC_USB_DOEPINT5_OFFSET                   0xba8
-#define GC_USB_DOEPINT5_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ5_OFFSET                  0xbb0
-#define GC_USB_DOEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DOEPDMA5_OFFSET                   0xbb4
-#define GC_USB_DOEPDMA5_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB5_OFFSET                  0xbbc
-#define GC_USB_DOEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DOEPCTL6_OFFSET                   0xbc0
-#define GC_USB_DOEPCTL6_DEFAULT                  0x0
-#define GC_USB_DOEPINT6_OFFSET                   0xbc8
-#define GC_USB_DOEPINT6_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ6_OFFSET                  0xbd0
-#define GC_USB_DOEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DOEPDMA6_OFFSET                   0xbd4
-#define GC_USB_DOEPDMA6_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB6_OFFSET                  0xbdc
-#define GC_USB_DOEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DOEPCTL7_OFFSET                   0xbe0
-#define GC_USB_DOEPCTL7_DEFAULT                  0x0
-#define GC_USB_DOEPINT7_OFFSET                   0xbe8
-#define GC_USB_DOEPINT7_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ7_OFFSET                  0xbf0
-#define GC_USB_DOEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DOEPDMA7_OFFSET                   0xbf4
-#define GC_USB_DOEPDMA7_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB7_OFFSET                  0xbfc
-#define GC_USB_DOEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DOEPCTL8_OFFSET                   0xc00
-#define GC_USB_DOEPCTL8_DEFAULT                  0x0
-#define GC_USB_DOEPINT8_OFFSET                   0xc08
-#define GC_USB_DOEPINT8_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ8_OFFSET                  0xc10
-#define GC_USB_DOEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DOEPDMA8_OFFSET                   0xc14
-#define GC_USB_DOEPDMA8_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB8_OFFSET                  0xc1c
-#define GC_USB_DOEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DOEPCTL9_OFFSET                   0xc20
-#define GC_USB_DOEPCTL9_DEFAULT                  0x0
-#define GC_USB_DOEPINT9_OFFSET                   0xc28
-#define GC_USB_DOEPINT9_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ9_OFFSET                  0xc30
-#define GC_USB_DOEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DOEPDMA9_OFFSET                   0xc34
-#define GC_USB_DOEPDMA9_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB9_OFFSET                  0xc3c
-#define GC_USB_DOEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DOEPCTL10_OFFSET                  0xc40
-#define GC_USB_DOEPCTL10_DEFAULT                 0x0
-#define GC_USB_DOEPINT10_OFFSET                  0xc48
-#define GC_USB_DOEPINT10_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ10_OFFSET                 0xc50
-#define GC_USB_DOEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DOEPDMA10_OFFSET                  0xc54
-#define GC_USB_DOEPDMA10_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB10_OFFSET                 0xc5c
-#define GC_USB_DOEPDMAB10_DEFAULT                0x0
-#define GC_USB_DOEPCTL11_OFFSET                  0xc60
-#define GC_USB_DOEPCTL11_DEFAULT                 0x0
-#define GC_USB_DOEPINT11_OFFSET                  0xc68
-#define GC_USB_DOEPINT11_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ11_OFFSET                 0xc70
-#define GC_USB_DOEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DOEPDMA11_OFFSET                  0xc74
-#define GC_USB_DOEPDMA11_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB11_OFFSET                 0xc7c
-#define GC_USB_DOEPDMAB11_DEFAULT                0x0
-#define GC_USB_DOEPCTL12_OFFSET                  0xc80
-#define GC_USB_DOEPCTL12_DEFAULT                 0x0
-#define GC_USB_DOEPINT12_OFFSET                  0xc88
-#define GC_USB_DOEPINT12_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ12_OFFSET                 0xc90
-#define GC_USB_DOEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DOEPDMA12_OFFSET                  0xc94
-#define GC_USB_DOEPDMA12_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB12_OFFSET                 0xc9c
-#define GC_USB_DOEPDMAB12_DEFAULT                0x0
-#define GC_USB_DOEPCTL13_OFFSET                  0xca0
-#define GC_USB_DOEPCTL13_DEFAULT                 0x0
-#define GC_USB_DOEPINT13_OFFSET                  0xca8
-#define GC_USB_DOEPINT13_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ13_OFFSET                 0xcb0
-#define GC_USB_DOEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DOEPDMA13_OFFSET                  0xcb4
-#define GC_USB_DOEPDMA13_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB13_OFFSET                 0xcbc
-#define GC_USB_DOEPDMAB13_DEFAULT                0x0
-#define GC_USB_DOEPCTL14_OFFSET                  0xcc0
-#define GC_USB_DOEPCTL14_DEFAULT                 0x0
-#define GC_USB_DOEPINT14_OFFSET                  0xcc8
-#define GC_USB_DOEPINT14_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ14_OFFSET                 0xcd0
-#define GC_USB_DOEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DOEPDMA14_OFFSET                  0xcd4
-#define GC_USB_DOEPDMA14_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB14_OFFSET                 0xcdc
-#define GC_USB_DOEPDMAB14_DEFAULT                0x0
-#define GC_USB_DOEPCTL15_OFFSET                  0xce0
-#define GC_USB_DOEPCTL15_DEFAULT                 0x0
-#define GC_USB_DOEPINT15_OFFSET                  0xce8
-#define GC_USB_DOEPINT15_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ15_OFFSET                 0xcf0
-#define GC_USB_DOEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DOEPDMA15_OFFSET                  0xcf4
-#define GC_USB_DOEPDMA15_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB15_OFFSET                 0xcfc
-#define GC_USB_DOEPDMAB15_DEFAULT                0x0
-#define GC_USB_PCGCCTL_OFFSET                    0xe00
-#define GC_USB_PCGCCTL_DEFAULT                   0x0
-#define GC_USB_DFIFO_OFFSET                      0x20000
-#define GC_USB_GOTGCTL_BVALIDOVEN_LSB            0x6
-#define GC_USB_GOTGCTL_BVALIDOVEN_MASK           0x40
-#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE           0x1
-#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT        0x0
-#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET         0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB           0x7
-#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK          0x80
-#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE          0x1
-#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT       0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET        0x0
-#define GC_USB_GOTGCTL_CONIDSTS_LSB              0x10
-#define GC_USB_GOTGCTL_CONIDSTS_MASK             0x10000
-#define GC_USB_GOTGCTL_CONIDSTS_SIZE             0x1
-#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT          0x0
-#define GC_USB_GOTGCTL_CONIDSTS_OFFSET           0x0
-#define GC_USB_GOTGCTL_BSESVLD_LSB               0x13
-#define GC_USB_GOTGCTL_BSESVLD_MASK              0x80000
-#define GC_USB_GOTGCTL_BSESVLD_SIZE              0x1
-#define GC_USB_GOTGCTL_BSESVLD_DEFAULT           0x0
-#define GC_USB_GOTGCTL_BSESVLD_OFFSET            0x0
-#define GC_USB_GOTGCTL_OTGVER_LSB                0x14
-#define GC_USB_GOTGCTL_OTGVER_MASK               0x100000
-#define GC_USB_GOTGCTL_OTGVER_SIZE               0x1
-#define GC_USB_GOTGCTL_OTGVER_DEFAULT            0x0
-#define GC_USB_GOTGCTL_OTGVER_OFFSET             0x0
-#define GC_USB_GOTGCTL_CURMOD_LSB                0x15
-#define GC_USB_GOTGCTL_CURMOD_MASK               0x200000
-#define GC_USB_GOTGCTL_CURMOD_SIZE               0x1
-#define GC_USB_GOTGCTL_CURMOD_DEFAULT            0x0
-#define GC_USB_GOTGCTL_CURMOD_OFFSET             0x0
-#define GC_USB_GOTGINT_SESENDDET_LSB             0x2
-#define GC_USB_GOTGINT_SESENDDET_MASK            0x4
-#define GC_USB_GOTGINT_SESENDDET_SIZE            0x1
-#define GC_USB_GOTGINT_SESENDDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_SESENDDET_OFFSET          0x4
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB      0x8
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK     0x100
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB      0x9
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK     0x200
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGDET_LSB             0x11
-#define GC_USB_GOTGINT_HSTNEGDET_MASK            0x20000
-#define GC_USB_GOTGINT_HSTNEGDET_SIZE            0x1
-#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_HSTNEGDET_OFFSET          0x4
-#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB           0x12
-#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK          0x40000
-#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE          0x1
-#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT       0x0
-#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET        0x4
-#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB           0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT       0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET        0x8
-#define GC_USB_GAHBCFG_HBSTLEN_LSB               0x1
-#define GC_USB_GAHBCFG_HBSTLEN_MASK              0x1e
-#define GC_USB_GAHBCFG_HBSTLEN_SIZE              0x4
-#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT           0x0
-#define GC_USB_GAHBCFG_HBSTLEN_OFFSET            0x8
-#define GC_USB_GAHBCFG_DMAEN_LSB                 0x5
-#define GC_USB_GAHBCFG_DMAEN_MASK                0x20
-#define GC_USB_GAHBCFG_DMAEN_SIZE                0x1
-#define GC_USB_GAHBCFG_DMAEN_DEFAULT             0x0
-#define GC_USB_GAHBCFG_DMAEN_OFFSET              0x8
-
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB           0x7
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK          0x80
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE          0x1
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT       0x0
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET        0x8
-
-#define GC_USB_GAHBCFG_REMMEMSUPP_LSB            0x15
-#define GC_USB_GAHBCFG_REMMEMSUPP_MASK           0x200000
-#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE           0x1
-#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT        0x0
-#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET         0x8
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB        0x16
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK       0x400000
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE       0x1
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT    0x0
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET     0x8
-#define GC_USB_GAHBCFG_AHBSINGLE_LSB             0x17
-#define GC_USB_GAHBCFG_AHBSINGLE_MASK            0x800000
-#define GC_USB_GAHBCFG_AHBSINGLE_SIZE            0x1
-#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT         0x0
-#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET          0x8
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB      0x18
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK     0x1000000
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE     0x1
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT  0x0
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET   0x8
-#define GC_USB_GUSBCFG_TOUTCAL_LSB               0x0
-#define GC_USB_GUSBCFG_TOUTCAL_MASK              0x7
-#define GC_USB_GUSBCFG_TOUTCAL_SIZE              0x3
-#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT           0x0
-#define GC_USB_GUSBCFG_TOUTCAL_OFFSET            0xc
-
-#define GC_USB_GUSBCFG_USBTRDTIM_LSB             0xa
-#define GC_USB_GUSBCFG_USBTRDTIM_MASK            0x3c00
-#define GC_USB_GUSBCFG_USBTRDTIM_SIZE            0x4
-#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT         0x0
-#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET          0xc
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB         15
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK        0x8000
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE        0x1
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_ULPIFSLS_LSB              17
-#define GC_USB_GUSBCFG_ULPIFSLS_MASK             0x20000
-#define GC_USB_GUSBCFG_ULPIFSLS_SIZE             0x1
-#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT          0x0
-#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET           0xc
-#define GC_USB_GUSBCFG_ULPIAUTORES_LSB           18
-#define GC_USB_GUSBCFG_ULPIAUTORES_MASK          0x40000
-#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET        0xc
-#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB           19
-#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK          0x80000
-#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET        0xc
-
-#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB            20
-#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK           0x100000
-#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET         0xc
-
-#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB            21
-#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK           0x200000
-#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET         0xc
-
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB        22
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK       0x400000
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE       0x1
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT    0x0
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
-
-#define GC_USB_GUSBCFG_PCCI_LSB                  23
-#define GC_USB_GUSBCFG_PCCI_MASK                 BIT(23)
-#define GC_USB_GUSBCFG_PCCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PCCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PCCI_OFFSET               0xc
-
-#define GC_USB_GUSBCFG_PTCI_LSB                  24
-#define GC_USB_GUSBCFG_PTCI_MASK                 BIT(24)
-#define GC_USB_GUSBCFG_PTCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PTCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PTCI_OFFSET               0xc
-
-#define GC_USB_GUSBCFG_ULPIIPD_LSB               25
-#define GC_USB_GUSBCFG_ULPIIPD_MASK              BIT(25)
-#define GC_USB_GUSBCFG_ULPIIPD_SIZE              0x1
-#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT           0x0
-#define GC_USB_GUSBCFG_ULPIIPD_OFFSET            0xc
-
-#define GC_USB_GUSBCFG_FHMOD_LSB                 29
-#define GC_USB_GUSBCFG_FHMOD_MASK                BIT(29)
-#define GC_USB_GUSBCFG_FHMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FHMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FHMOD_OFFSET              0xc
-
-#define GC_USB_GUSBCFG_FDMOD_LSB                 30
-#define GC_USB_GUSBCFG_FDMOD_MASK                BIT(30)
-#define GC_USB_GUSBCFG_FDMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FDMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FDMOD_OFFSET              0xc
-
-#define GC_USB_GRSTCTL_CSFTRST_LSB               0x0
-#define GC_USB_GRSTCTL_CSFTRST_MASK              0x1
-#define GC_USB_GRSTCTL_CSFTRST_SIZE              0x1
-#define GC_USB_GRSTCTL_CSFTRST_DEFAULT           0x0
-#define GC_USB_GRSTCTL_CSFTRST_OFFSET            0x10
-#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB           0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK          0x2
-#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE          0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT       0x0
-#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET        0x10
-#define GC_USB_GRSTCTL_RXFFLSH_LSB               0x4
-#define GC_USB_GRSTCTL_RXFFLSH_MASK              0x10
-#define GC_USB_GRSTCTL_RXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_RXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFFLSH_LSB               0x5
-#define GC_USB_GRSTCTL_TXFFLSH_MASK              0x20
-#define GC_USB_GRSTCTL_TXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_TXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFNUM_LSB                0x6
-#define GC_USB_GRSTCTL_TXFNUM_MASK               0x7c0
-#define GC_USB_GRSTCTL_TXFNUM_SIZE               0x5
-#define GC_USB_GRSTCTL_TXFNUM_DEFAULT            0x0
-#define GC_USB_GRSTCTL_TXFNUM_OFFSET             0x10
-#define GC_USB_GRSTCTL_DMAREQ_LSB                0x1e
-#define GC_USB_GRSTCTL_DMAREQ_MASK               0x40000000
-#define GC_USB_GRSTCTL_DMAREQ_SIZE               0x1
-#define GC_USB_GRSTCTL_DMAREQ_DEFAULT            0x0
-#define GC_USB_GRSTCTL_DMAREQ_OFFSET             0x10
-#define GC_USB_GRSTCTL_AHBIDLE_LSB               0x1f
-#define GC_USB_GRSTCTL_AHBIDLE_MASK              0x80000000
-#define GC_USB_GRSTCTL_AHBIDLE_SIZE              0x1
-#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT           0x0
-#define GC_USB_GRSTCTL_AHBIDLE_OFFSET            0x10
-#define GC_USB_GINTSTS_CURMOD_LSB                0x0
-#define GC_USB_GINTSTS_CURMOD_MASK               0x1
-#define GC_USB_GINTSTS_CURMOD_SIZE               0x1
-#define GC_USB_GINTSTS_CURMOD_DEFAULT            0x0
-#define GC_USB_GINTSTS_CURMOD_OFFSET             0x14
-#define GC_USB_GINTSTS_MODEMIS_LSB               0x1
-#define GC_USB_GINTSTS_MODEMIS_MASK              0x2
-#define GC_USB_GINTSTS_MODEMIS_SIZE              0x1
-#define GC_USB_GINTSTS_MODEMIS_DEFAULT           0x0
-#define GC_USB_GINTSTS_MODEMIS_OFFSET            0x14
-#define GC_USB_GINTSTS_OTGINT_LSB                0x2
-#define GC_USB_GINTSTS_OTGINT_MASK               0x4
-#define GC_USB_GINTSTS_OTGINT_SIZE               0x1
-#define GC_USB_GINTSTS_OTGINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OTGINT_OFFSET             0x14
-#define GC_USB_GINTSTS_SOF_LSB                   0x3
-#define GC_USB_GINTSTS_SOF_MASK                  0x8
-#define GC_USB_GINTSTS_SOF_SIZE                  0x1
-#define GC_USB_GINTSTS_SOF_DEFAULT               0x0
-#define GC_USB_GINTSTS_SOF_OFFSET                0x14
-#define GC_USB_GINTSTS_RXFLVL_LSB                0x4
-#define GC_USB_GINTSTS_RXFLVL_MASK               0x10
-#define GC_USB_GINTSTS_RXFLVL_SIZE               0x1
-#define GC_USB_GINTSTS_RXFLVL_DEFAULT            0x0
-#define GC_USB_GINTSTS_RXFLVL_OFFSET             0x14
-#define GC_USB_GINTSTS_GINNAKEFF_LSB             0x6
-#define GC_USB_GINTSTS_GINNAKEFF_MASK            0x40
-#define GC_USB_GINTSTS_GINNAKEFF_SIZE            0x1
-#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT         0x0
-#define GC_USB_GINTSTS_GINNAKEFF_OFFSET          0x14
-#define GC_USB_GINTSTS_GOUTNAKEFF_LSB            0x7
-#define GC_USB_GINTSTS_GOUTNAKEFF_MASK           0x80
-#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE           0x1
-#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT        0x0
-#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET         0x14
-#define GC_USB_GINTSTS_ERLYSUSP_LSB              0xa
-#define GC_USB_GINTSTS_ERLYSUSP_MASK             0x400
-#define GC_USB_GINTSTS_ERLYSUSP_SIZE             0x1
-#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT          0x0
-#define GC_USB_GINTSTS_ERLYSUSP_OFFSET           0x14
-#define GC_USB_GINTSTS_USBSUSP_LSB               0xb
-#define GC_USB_GINTSTS_USBSUSP_MASK              0x800
-#define GC_USB_GINTSTS_USBSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_USBSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_USBSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_USBRST_LSB                0xc
-#define GC_USB_GINTSTS_USBRST_MASK               0x1000
-#define GC_USB_GINTSTS_USBRST_SIZE               0x1
-#define GC_USB_GINTSTS_USBRST_DEFAULT            0x0
-#define GC_USB_GINTSTS_USBRST_OFFSET             0x14
-#define GC_USB_GINTSTS_ENUMDONE_LSB              0xd
-#define GC_USB_GINTSTS_ENUMDONE_MASK             0x2000
-#define GC_USB_GINTSTS_ENUMDONE_SIZE             0x1
-#define GC_USB_GINTSTS_ENUMDONE_DEFAULT          0x0
-#define GC_USB_GINTSTS_ENUMDONE_OFFSET           0x14
-#define GC_USB_GINTSTS_ISOOUTDROP_LSB            0xe
-#define GC_USB_GINTSTS_ISOOUTDROP_MASK           0x4000
-#define GC_USB_GINTSTS_ISOOUTDROP_SIZE           0x1
-#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT        0x0
-#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET         0x14
-#define GC_USB_GINTSTS_EOPF_LSB                  0xf
-#define GC_USB_GINTSTS_EOPF_MASK                 0x8000
-#define GC_USB_GINTSTS_EOPF_SIZE                 0x1
-#define GC_USB_GINTSTS_EOPF_DEFAULT              0x0
-#define GC_USB_GINTSTS_EOPF_OFFSET               0x14
-#define GC_USB_GINTSTS_EPMIS_LSB                 0x11
-#define GC_USB_GINTSTS_EPMIS_MASK                0x20000
-#define GC_USB_GINTSTS_EPMIS_SIZE                0x1
-#define GC_USB_GINTSTS_EPMIS_DEFAULT             0x0
-#define GC_USB_GINTSTS_EPMIS_OFFSET              0x14
-#define GC_USB_GINTSTS_IEPINT_LSB                0x12
-#define GC_USB_GINTSTS_IEPINT_MASK               0x40000
-#define GC_USB_GINTSTS_IEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_IEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_IEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_OEPINT_LSB                0x13
-#define GC_USB_GINTSTS_OEPINT_MASK               0x80000
-#define GC_USB_GINTSTS_OEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_OEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_LSB           0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_MASK          0x100000
-#define GC_USB_GINTSTS_INCOMPISOIN_SIZE          0x1
-#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT       0x0
-#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET        0x14
-#define GC_USB_GINTSTS_INCOMPLP_LSB              0x15
-#define GC_USB_GINTSTS_INCOMPLP_MASK             0x200000
-#define GC_USB_GINTSTS_INCOMPLP_SIZE             0x1
-#define GC_USB_GINTSTS_INCOMPLP_DEFAULT          0x0
-#define GC_USB_GINTSTS_INCOMPLP_OFFSET           0x14
-#define GC_USB_GINTSTS_FETSUSP_LSB               0x16
-#define GC_USB_GINTSTS_FETSUSP_MASK              0x400000
-#define GC_USB_GINTSTS_FETSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_FETSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_FETSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_RESETDET_LSB              0x17
-#define GC_USB_GINTSTS_RESETDET_MASK             0x800000
-#define GC_USB_GINTSTS_RESETDET_SIZE             0x1
-#define GC_USB_GINTSTS_RESETDET_DEFAULT          0x0
-#define GC_USB_GINTSTS_RESETDET_OFFSET           0x14
-#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB          0x1c
-#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK         0x10000000
-#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE         0x1
-#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT      0x0
-#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET       0x14
-#define GC_USB_GINTSTS_SESSREQINT_LSB            0x1e
-#define GC_USB_GINTSTS_SESSREQINT_MASK           0x40000000
-#define GC_USB_GINTSTS_SESSREQINT_SIZE           0x1
-#define GC_USB_GINTSTS_SESSREQINT_DEFAULT        0x0
-#define GC_USB_GINTSTS_SESSREQINT_OFFSET         0x14
-#define GC_USB_GINTSTS_WKUPINT_LSB               0x1f
-#define GC_USB_GINTSTS_WKUPINT_MASK              0x80000000
-#define GC_USB_GINTSTS_WKUPINT_SIZE              0x1
-#define GC_USB_GINTSTS_WKUPINT_DEFAULT           0x0
-#define GC_USB_GINTSTS_WKUPINT_OFFSET            0x14
-#define GC_USB_GINTMSK_MODEMISMSK_LSB            0x1
-#define GC_USB_GINTMSK_MODEMISMSK_MASK           0x2
-#define GC_USB_GINTMSK_MODEMISMSK_SIZE           0x1
-#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_MODEMISMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_OTGINTMSK_LSB             0x2
-#define GC_USB_GINTMSK_OTGINTMSK_MASK            0x4
-#define GC_USB_GINTMSK_OTGINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OTGINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_SOFMSK_LSB                0x3
-#define GC_USB_GINTMSK_SOFMSK_MASK               0x8
-#define GC_USB_GINTMSK_SOFMSK_SIZE               0x1
-#define GC_USB_GINTMSK_SOFMSK_DEFAULT            0x0
-#define GC_USB_GINTMSK_SOFMSK_OFFSET             0x18
-#define GC_USB_GINTMSK_RXFLVLMSK_LSB             0x4
-#define GC_USB_GINTMSK_RXFLVLMSK_MASK            0x10
-#define GC_USB_GINTMSK_RXFLVLMSK_SIZE            0x1
-#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_UNKNOWN5_LSB              0x5
-#define GC_USB_GINTMSK_UNKNOWN5_MASK             0x20
-#define GC_USB_GINTMSK_UNKNOWN5_SIZE             0x1
-#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT          0x0
-#define GC_USB_GINTMSK_UNKNOWN5_OFFSET           0x18
-#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB          0x6
-#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK         0x40
-#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE         0x1
-#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT      0x0
-#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET       0x18
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB         0x7
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK        0x80
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE        0x1
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB           0xa
-#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK          0x400
-#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_USBSUSPMSK_LSB            0xb
-#define GC_USB_GINTMSK_USBSUSPMSK_MASK           0x800
-#define GC_USB_GINTMSK_USBSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_USBRSTMSK_LSB             0xc
-#define GC_USB_GINTMSK_USBRSTMSK_MASK            0x1000
-#define GC_USB_GINTMSK_USBRSTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_USBRSTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_ENUMDONEMSK_LSB           0xd
-#define GC_USB_GINTMSK_ENUMDONEMSK_MASK          0x2000
-#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB         0xe
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK        0x4000
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE        0x1
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_EOPFMSK_LSB               0xf
-#define GC_USB_GINTMSK_EOPFMSK_MASK              0x8000
-#define GC_USB_GINTMSK_EOPFMSK_SIZE              0x1
-#define GC_USB_GINTMSK_EOPFMSK_DEFAULT           0x0
-#define GC_USB_GINTMSK_EOPFMSK_OFFSET            0x18
-#define GC_USB_GINTMSK_UNKNOWN16_LSB             0x10
-#define GC_USB_GINTMSK_UNKNOWN16_MASK            0x10000
-#define GC_USB_GINTMSK_UNKNOWN16_SIZE            0x1
-#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT         0x0
-#define GC_USB_GINTMSK_UNKNOWN16_OFFSET          0x18
-#define GC_USB_GINTMSK_EPMISMSK_LSB              0x11
-#define GC_USB_GINTMSK_EPMISMSK_MASK             0x20000
-#define GC_USB_GINTMSK_EPMISMSK_SIZE             0x1
-#define GC_USB_GINTMSK_EPMISMSK_DEFAULT          0x0
-#define GC_USB_GINTMSK_EPMISMSK_OFFSET           0x18
-#define GC_USB_GINTMSK_IEPINTMSK_LSB             0x12
-#define GC_USB_GINTMSK_IEPINTMSK_MASK            0x40000
-#define GC_USB_GINTMSK_IEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_IEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_OEPINTMSK_LSB             0x13
-#define GC_USB_GINTMSK_OEPINTMSK_MASK            0x80000
-#define GC_USB_GINTMSK_OEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB        0x14
-#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK       0x100000
-#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE       0x1
-#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT    0x0
-#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET     0x18
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB      0x15
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK     0x200000
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE     0x1
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT  0x0
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET   0x18
-#define GC_USB_GINTMSK_FETSUSPMSK_LSB            0x16
-#define GC_USB_GINTMSK_FETSUSPMSK_MASK           0x400000
-#define GC_USB_GINTMSK_FETSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_RESETDETMSK_LSB           0x17
-#define GC_USB_GINTMSK_RESETDETMSK_MASK          0x800000
-#define GC_USB_GINTMSK_RESETDETMSK_SIZE          0x1
-#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_RESETDETMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB       0x1c
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK      0x10000000
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE      0x1
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT   0x0
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET    0x18
-#define GC_USB_GINTMSK_DISCONNINTMSK_LSB         0x1d
-#define GC_USB_GINTMSK_DISCONNINTMSK_MASK        0x20000000
-#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_SESSREQINTMSK_LSB         0x1e
-#define GC_USB_GINTMSK_SESSREQINTMSK_MASK        0x40000000
-#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_WKUPINTMSK_LSB            0x1f
-#define GC_USB_GINTMSK_WKUPINTMSK_MASK           0x80000000
-#define GC_USB_GINTMSK_WKUPINTMSK_SIZE           0x1
-#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET         0x18
-#define GC_USB_GRXSTSR_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSR_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSR_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSR_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSR_CHNUM_OFFSET              0x1c
-#define GC_USB_GRXSTSR_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSR_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSR_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSR_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSR_BCNT_OFFSET               0x1c
-#define GC_USB_GRXSTSR_DPID_LSB                  0xf
-#define GC_USB_GRXSTSR_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSR_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSR_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSR_DPID_OFFSET               0x1c
-#define GC_USB_GRXSTSR_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSR_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSR_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSR_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSR_PKTSTS_OFFSET             0x1c
-#define GC_USB_GRXSTSR_FN_LSB                    0x15
-#define GC_USB_GRXSTSR_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSR_FN_SIZE                   0x4
-#define GC_USB_GRXSTSR_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSR_FN_OFFSET                 0x1c
-#define GC_USB_GRXSTSP_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSP_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSP_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSP_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSP_CHNUM_OFFSET              0x20
-#define GC_USB_GRXSTSP_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSP_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSP_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSP_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSP_BCNT_OFFSET               0x20
-#define GC_USB_GRXSTSP_DPID_LSB                  0xf
-#define GC_USB_GRXSTSP_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSP_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSP_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSP_DPID_OFFSET               0x20
-#define GC_USB_GRXSTSP_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSP_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSP_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSP_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSP_PKTSTS_OFFSET             0x20
-#define GC_USB_GRXSTSP_FN_LSB                    0x15
-#define GC_USB_GRXSTSP_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSP_FN_SIZE                   0x4
-#define GC_USB_GRXSTSP_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSP_FN_OFFSET                 0x20
-#define GC_USB_GRXFSIZ_RXFDEP_LSB                0x0
-#define GC_USB_GRXFSIZ_RXFDEP_MASK               0x7ff
-#define GC_USB_GRXFSIZ_RXFDEP_SIZE               0xb
-#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT            0x0
-#define GC_USB_GRXFSIZ_RXFDEP_OFFSET             0x24
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB      0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK     0xffff
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE     0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT  0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET   0x28
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB         0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK        0xffff0000
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE        0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT     0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET      0x28
-
-#define GC_USB_GUID_GUID_LSB                     0x0
-#define GC_USB_GUID_GUID_MASK                    0xffffffff
-#define GC_USB_GUID_GUID_SIZE                    0x20
-#define GC_USB_GUID_GUID_DEFAULT                 0x0
-#define GC_USB_GUID_GUID_OFFSET                  0x3c
-#define GC_USB_GSNPSID_SYNOPSYSID_LSB            0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_MASK           0xffffffff
-#define GC_USB_GSNPSID_SYNOPSYSID_SIZE           0x20
-#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT        0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET         0x40
-#define GC_USB_GHWCFG1_EPDIR_LSB                 0x0
-#define GC_USB_GHWCFG1_EPDIR_MASK                0xffffffff
-#define GC_USB_GHWCFG1_EPDIR_SIZE                0x20
-#define GC_USB_GHWCFG1_EPDIR_DEFAULT             0x0
-#define GC_USB_GHWCFG1_EPDIR_OFFSET              0x44
-#define GC_USB_GHWCFG2_OTGMODE_LSB               0x0
-#define GC_USB_GHWCFG2_OTGMODE_MASK              0x7
-#define GC_USB_GHWCFG2_OTGMODE_SIZE              0x3
-#define GC_USB_GHWCFG2_OTGMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGMODE_OFFSET            0x48
-#define GC_USB_GHWCFG2_OTGARCH_LSB               0x3
-#define GC_USB_GHWCFG2_OTGARCH_MASK              0x18
-#define GC_USB_GHWCFG2_OTGARCH_SIZE              0x2
-#define GC_USB_GHWCFG2_OTGARCH_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGARCH_OFFSET            0x48
-#define GC_USB_GHWCFG2_SINGPNT_LSB               0x5
-#define GC_USB_GHWCFG2_SINGPNT_MASK              0x20
-#define GC_USB_GHWCFG2_SINGPNT_SIZE              0x1
-#define GC_USB_GHWCFG2_SINGPNT_DEFAULT           0x0
-#define GC_USB_GHWCFG2_SINGPNT_OFFSET            0x48
-#define GC_USB_GHWCFG2_HSPHYTYPE_LSB             0x6
-#define GC_USB_GHWCFG2_HSPHYTYPE_MASK            0xc0
-#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_FSPHYTYPE_LSB             0x8
-#define GC_USB_GHWCFG2_FSPHYTYPE_MASK            0x300
-#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMDEVEPS_LSB             0xa
-#define GC_USB_GHWCFG2_NUMDEVEPS_MASK            0x3c00
-#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE            0x4
-#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB            0xe
-#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK           0x3c000
-#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE           0x4
-#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET         0x48
-#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB          0x12
-#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK         0x40000
-#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE         0x1
-#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT      0x0
-#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET       0x48
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB         0x13
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK        0x80000
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE        0x1
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT     0x0
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET      0x48
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB       0x14
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK      0x100000
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE      0x1
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT   0x0
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET    0x48
-#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB            0x16
-#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK           0xc00000
-#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE           0x2
-#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET         0x48
-#define GC_USB_GHWCFG2_PTXQDEPTH_LSB             0x18
-#define GC_USB_GHWCFG2_PTXQDEPTH_MASK            0x3000000
-#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE            0x2
-#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG2_TKNQDEPTH_LSB             0x1a
-#define GC_USB_GHWCFG2_TKNQDEPTH_MASK            0x7c000000
-#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE            0x5
-#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB         0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK        0xf
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE        0x4
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT     0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET      0x4c
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB          0x4
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK         0x70
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE         0x3
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET       0x4c
-#define GC_USB_GHWCFG3_OTGEN_LSB                 0x7
-#define GC_USB_GHWCFG3_OTGEN_MASK                0x80
-#define GC_USB_GHWCFG3_OTGEN_SIZE                0x1
-#define GC_USB_GHWCFG3_OTGEN_DEFAULT             0x0
-#define GC_USB_GHWCFG3_OTGEN_OFFSET              0x4c
-#define GC_USB_GHWCFG3_I2CINTSEL_LSB             0x8
-#define GC_USB_GHWCFG3_I2CINTSEL_MASK            0x100
-#define GC_USB_GHWCFG3_I2CINTSEL_SIZE            0x1
-#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT         0x0
-#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET          0x4c
-#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB            0x9
-#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK           0x200
-#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE           0x1
-#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_OPTFEATURE_LSB            0xa
-#define GC_USB_GHWCFG3_OPTFEATURE_MASK           0x400
-#define GC_USB_GHWCFG3_OPTFEATURE_SIZE           0x1
-#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT        0x0
-#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET         0x4c
-#define GC_USB_GHWCFG3_RSTTYPE_LSB               0xb
-#define GC_USB_GHWCFG3_RSTTYPE_MASK              0x800
-#define GC_USB_GHWCFG3_RSTTYPE_SIZE              0x1
-#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_RSTTYPE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_ADPSUPPORT_LSB            0xc
-#define GC_USB_GHWCFG3_ADPSUPPORT_MASK           0x1000
-#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE           0x1
-#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_HSICMODE_LSB              0xd
-#define GC_USB_GHWCFG3_HSICMODE_MASK             0x2000
-#define GC_USB_GHWCFG3_HSICMODE_SIZE             0x1
-#define GC_USB_GHWCFG3_HSICMODE_DEFAULT          0x0
-#define GC_USB_GHWCFG3_HSICMODE_OFFSET           0x4c
-#define GC_USB_GHWCFG3_BCSUPPORT_LSB             0xe
-#define GC_USB_GHWCFG3_BCSUPPORT_MASK            0x4000
-#define GC_USB_GHWCFG3_BCSUPPORT_SIZE            0x1
-#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT         0x0
-#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET          0x4c
-#define GC_USB_GHWCFG3_LPMMODE_LSB               0xf
-#define GC_USB_GHWCFG3_LPMMODE_MASK              0x8000
-#define GC_USB_GHWCFG3_LPMMODE_SIZE              0x1
-#define GC_USB_GHWCFG3_LPMMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_LPMMODE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_DFIFODEPTH_LSB            0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_MASK           0xffff0000
-#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE           0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET         0x4c
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB        0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK       0xf
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE       0x4
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT    0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET     0x50
-#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB          0x4
-#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK         0x10
-#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE         0x1
-#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET       0x50
-#define GC_USB_GHWCFG4_AHBFREQ_LSB               0x5
-#define GC_USB_GHWCFG4_AHBFREQ_MASK              0x20
-#define GC_USB_GHWCFG4_AHBFREQ_SIZE              0x1
-#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT           0x0
-#define GC_USB_GHWCFG4_AHBFREQ_OFFSET            0x50
-#define GC_USB_GHWCFG4_HIBERNATION_LSB           0x6
-#define GC_USB_GHWCFG4_HIBERNATION_MASK          0x40
-#define GC_USB_GHWCFG4_HIBERNATION_SIZE          0x1
-#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT       0x0
-#define GC_USB_GHWCFG4_HIBERNATION_OFFSET        0x50
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB   0x7
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK  0x80
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE  0x1
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB          0xe
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK         0xc000
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE         0x2
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET       0x50
-#define GC_USB_GHWCFG4_NUMCTLEPS_LSB             0x10
-#define GC_USB_GHWCFG4_NUMCTLEPS_MASK            0xf0000
-#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE            0x4
-#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET          0x50
-#define GC_USB_GHWCFG4_IDDGFLTR_LSB              0x14
-#define GC_USB_GHWCFG4_IDDGFLTR_MASK             0x100000
-#define GC_USB_GHWCFG4_IDDGFLTR_SIZE             0x1
-#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT          0x0
-#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET           0x50
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB         0x15
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK        0x200000
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE        0x1
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT     0x0
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET      0x50
-#define GC_USB_GHWCFG4_AVALIDFLTR_LSB            0x16
-#define GC_USB_GHWCFG4_AVALIDFLTR_MASK           0x400000
-#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_BVALIDFLTR_LSB            0x17
-#define GC_USB_GHWCFG4_BVALIDFLTR_MASK           0x800000
-#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_SESSENDFLTR_LSB           0x18
-#define GC_USB_GHWCFG4_SESSENDFLTR_MASK          0x1000000
-#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE          0x1
-#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT       0x0
-#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET        0x50
-#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB           0x19
-#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK          0x2000000
-#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE          0x1
-#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT       0x0
-#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET        0x50
-#define GC_USB_GHWCFG4_INEPS_LSB                 0x1a
-#define GC_USB_GHWCFG4_INEPS_MASK                0x3c000000
-#define GC_USB_GHWCFG4_INEPS_SIZE                0x4
-#define GC_USB_GHWCFG4_INEPS_DEFAULT             0x0
-#define GC_USB_GHWCFG4_INEPS_OFFSET              0x50
-#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB        0x1e
-#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK       0x40000000
-#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE       0x1
-#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT    0x0
-#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET     0x50
-#define GC_USB_GHWCFG4_DESCDMA_LSB               0x1f
-#define GC_USB_GHWCFG4_DESCDMA_MASK              0x80000000
-#define GC_USB_GHWCFG4_DESCDMA_SIZE              0x1
-#define GC_USB_GHWCFG4_DESCDMA_DEFAULT           0x0
-#define GC_USB_GHWCFG4_DESCDMA_OFFSET            0x50
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB           0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK          0xffff
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE          0x10
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT       0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET        0x5c
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB      0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK     0xffff0000
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE     0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT  0x0
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET   0x5c
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET    0x104
-#define GC_USB_DIEPTXF1_RESERVED11_LSB           0xc
-#define GC_USB_DIEPTXF1_RESERVED11_MASK          0x1000
-#define GC_USB_DIEPTXF1_RESERVED11_SIZE          0x1
-#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT       0x1
-#define GC_USB_DIEPTXF1_RESERVED11_OFFSET        0x104
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET       0x104
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET    0x108
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET       0x108
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET    0x10c
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET       0x10c
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET    0x110
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET       0x110
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET    0x114
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET       0x114
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET    0x118
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET       0x118
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET    0x11c
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET       0x11c
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET    0x120
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET       0x120
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET    0x124
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET       0x124
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET   0x128
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET      0x128
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET   0x12c
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET      0x12c
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET   0x130
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET      0x130
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET   0x134
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET      0x134
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET   0x138
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET      0x138
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET   0x13c
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET      0x13c
-#define GC_USB_DCFG_DEVSPD_LSB                   0x0
-#define GC_USB_DCFG_DEVSPD_MASK                  0x3
-#define GC_USB_DCFG_DEVSPD_SIZE                  0x2
-#define GC_USB_DCFG_DEVSPD_DEFAULT               0x0
-#define GC_USB_DCFG_DEVSPD_OFFSET                0x800
-#define GC_USB_DCFG_NZSTSOUTHSHK_LSB             0x2
-#define GC_USB_DCFG_NZSTSOUTHSHK_MASK            0x4
-#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE            0x1
-#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT         0x0
-#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET          0x800
-#define GC_USB_DCFG_ENA32KHZSUSP_LSB             0x3
-#define GC_USB_DCFG_ENA32KHZSUSP_MASK            0x8
-#define GC_USB_DCFG_ENA32KHZSUSP_SIZE            0x1
-#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT         0x0
-#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET          0x800
-#define GC_USB_DCFG_DEVADDR_LSB                  0x4
-#define GC_USB_DCFG_DEVADDR_MASK                 0x7f0
-#define GC_USB_DCFG_DEVADDR_SIZE                 0x7
-#define GC_USB_DCFG_DEVADDR_DEFAULT              0x0
-#define GC_USB_DCFG_DEVADDR_OFFSET               0x800
-#define GC_USB_DCFG_PERFRINT_LSB                 0xb
-#define GC_USB_DCFG_PERFRINT_MASK                0x1800
-#define GC_USB_DCFG_PERFRINT_SIZE                0x2
-#define GC_USB_DCFG_PERFRINT_DEFAULT             0x0
-#define GC_USB_DCFG_PERFRINT_OFFSET              0x800
-#define GC_USB_DCFG_ENDEVOUTNAK_LSB              0xd
-#define GC_USB_DCFG_ENDEVOUTNAK_MASK             0x2000
-#define GC_USB_DCFG_ENDEVOUTNAK_SIZE             0x1
-#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT          0x0
-#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET           0x800
-#define GC_USB_DCFG_XCVRDLY_LSB                  0xe
-#define GC_USB_DCFG_XCVRDLY_MASK                 0x4000
-#define GC_USB_DCFG_XCVRDLY_SIZE                 0x1
-#define GC_USB_DCFG_XCVRDLY_DEFAULT              0x0
-#define GC_USB_DCFG_XCVRDLY_OFFSET               0x800
-#define GC_USB_DCFG_ERRATICINTMSK_LSB            0xf
-#define GC_USB_DCFG_ERRATICINTMSK_MASK           0x8000
-#define GC_USB_DCFG_ERRATICINTMSK_SIZE           0x1
-#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT        0x0
-#define GC_USB_DCFG_ERRATICINTMSK_OFFSET         0x800
-#define GC_USB_DCFG_DESCDMA_LSB                  0x17
-#define GC_USB_DCFG_DESCDMA_MASK                 0x800000
-#define GC_USB_DCFG_DESCDMA_SIZE                 0x1
-#define GC_USB_DCFG_DESCDMA_DEFAULT              0x0
-#define GC_USB_DCFG_DESCDMA_OFFSET               0x800
-#define GC_USB_DCFG_PERSCHINTVL_LSB              0x18
-#define GC_USB_DCFG_PERSCHINTVL_MASK             0x3000000
-#define GC_USB_DCFG_PERSCHINTVL_SIZE             0x2
-#define GC_USB_DCFG_PERSCHINTVL_DEFAULT          0x0
-#define GC_USB_DCFG_PERSCHINTVL_OFFSET           0x800
-#define GC_USB_DCFG_RESVALID_LSB                 0x1a
-#define GC_USB_DCFG_RESVALID_MASK                0xfc000000
-#define GC_USB_DCFG_RESVALID_SIZE                0x6
-#define GC_USB_DCFG_RESVALID_DEFAULT             0x2
-#define GC_USB_DCFG_RESVALID_OFFSET              0x800
-#define GC_USB_DCTL_RMTWKUPSIG_LSB               0x0
-#define GC_USB_DCTL_RMTWKUPSIG_MASK              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_SIZE              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT           0x0
-#define GC_USB_DCTL_RMTWKUPSIG_OFFSET            0x804
-#define GC_USB_DCTL_SFTDISCON_LSB                0x1
-#define GC_USB_DCTL_SFTDISCON_MASK               0x2
-#define GC_USB_DCTL_SFTDISCON_SIZE               0x1
-#define GC_USB_DCTL_SFTDISCON_DEFAULT            0x0
-#define GC_USB_DCTL_SFTDISCON_OFFSET             0x804
-#define GC_USB_DCTL_GNPINNAKSTS_LSB              0x2
-#define GC_USB_DCTL_GNPINNAKSTS_MASK             0x4
-#define GC_USB_DCTL_GNPINNAKSTS_SIZE             0x1
-#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT          0x0
-#define GC_USB_DCTL_GNPINNAKSTS_OFFSET           0x804
-#define GC_USB_DCTL_GOUTNAKSTS_LSB               0x3
-#define GC_USB_DCTL_GOUTNAKSTS_MASK              0x8
-#define GC_USB_DCTL_GOUTNAKSTS_SIZE              0x1
-#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT           0x0
-#define GC_USB_DCTL_GOUTNAKSTS_OFFSET            0x804
-#define GC_USB_DCTL_TSTCTL_LSB                   0x4
-#define GC_USB_DCTL_TSTCTL_MASK                  0x70
-#define GC_USB_DCTL_TSTCTL_SIZE                  0x3
-#define GC_USB_DCTL_TSTCTL_DEFAULT               0x0
-#define GC_USB_DCTL_TSTCTL_OFFSET                0x804
-#define GC_USB_DCTL_SGNPINNAK_LSB                0x7
-#define GC_USB_DCTL_SGNPINNAK_MASK               0x80
-#define GC_USB_DCTL_SGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_SGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_SGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_CGNPINNAK_LSB                0x8
-#define GC_USB_DCTL_CGNPINNAK_MASK               0x100
-#define GC_USB_DCTL_CGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_CGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_CGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_SGOUTNAK_LSB                 0x9
-#define GC_USB_DCTL_SGOUTNAK_MASK                0x200
-#define GC_USB_DCTL_SGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_SGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_SGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_CGOUTNAK_LSB                 0xa
-#define GC_USB_DCTL_CGOUTNAK_MASK                0x400
-#define GC_USB_DCTL_CGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_CGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_CGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_PWRONPRGDONE_LSB             0xb
-#define GC_USB_DCTL_PWRONPRGDONE_MASK            0x800
-#define GC_USB_DCTL_PWRONPRGDONE_SIZE            0x1
-#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT         0x0
-#define GC_USB_DCTL_PWRONPRGDONE_OFFSET          0x804
-#define GC_USB_DCTL_GMC_LSB                      0xd
-#define GC_USB_DCTL_GMC_MASK                     0x6000
-#define GC_USB_DCTL_GMC_SIZE                     0x2
-#define GC_USB_DCTL_GMC_DEFAULT                  0x0
-#define GC_USB_DCTL_GMC_OFFSET                   0x804
-#define GC_USB_DCTL_IGNRFRMNUM_LSB               0xf
-#define GC_USB_DCTL_IGNRFRMNUM_MASK              0x8000
-#define GC_USB_DCTL_IGNRFRMNUM_SIZE              0x1
-#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT           0x0
-#define GC_USB_DCTL_IGNRFRMNUM_OFFSET            0x804
-#define GC_USB_DCTL_NAKONBBLE_LSB                0x10
-#define GC_USB_DCTL_NAKONBBLE_MASK               0x10000
-#define GC_USB_DCTL_NAKONBBLE_SIZE               0x1
-#define GC_USB_DCTL_NAKONBBLE_DEFAULT            0x0
-#define GC_USB_DCTL_NAKONBBLE_OFFSET             0x804
-#define GC_USB_DCTL_ENCONTONBNA_LSB              0x11
-#define GC_USB_DCTL_ENCONTONBNA_MASK             0x20000
-#define GC_USB_DCTL_ENCONTONBNA_SIZE             0x1
-#define GC_USB_DCTL_ENCONTONBNA_DEFAULT          0x0
-#define GC_USB_DCTL_ENCONTONBNA_OFFSET           0x804
-#define GC_USB_DSTS_SUSPSTS_LSB                  0x0
-#define GC_USB_DSTS_SUSPSTS_MASK                 0x1
-#define GC_USB_DSTS_SUSPSTS_SIZE                 0x1
-#define GC_USB_DSTS_SUSPSTS_DEFAULT              0x0
-#define GC_USB_DSTS_SUSPSTS_OFFSET               0x808
-#define GC_USB_DSTS_ENUMSPD_LSB                  0x1
-#define GC_USB_DSTS_ENUMSPD_MASK                 0x6
-#define GC_USB_DSTS_ENUMSPD_SIZE                 0x2
-#define GC_USB_DSTS_ENUMSPD_DEFAULT              0x0
-#define GC_USB_DSTS_ENUMSPD_OFFSET               0x808
-#define GC_USB_DSTS_ERRTICERR_LSB                0x3
-#define GC_USB_DSTS_ERRTICERR_MASK               0x8
-#define GC_USB_DSTS_ERRTICERR_SIZE               0x1
-#define GC_USB_DSTS_ERRTICERR_DEFAULT            0x0
-#define GC_USB_DSTS_ERRTICERR_OFFSET             0x808
-#define GC_USB_DSTS_SOFFN_LSB                    0x8
-#define GC_USB_DSTS_SOFFN_MASK                   0x3fff00
-#define GC_USB_DSTS_SOFFN_SIZE                   0xe
-#define GC_USB_DSTS_SOFFN_DEFAULT                0x0
-#define GC_USB_DSTS_SOFFN_OFFSET                 0x808
-#define GC_USB_DSTS_DEVLNSTS_LSB                 0x16
-#define GC_USB_DSTS_DEVLNSTS_MASK                0xc00000
-#define GC_USB_DSTS_DEVLNSTS_SIZE                0x2
-#define GC_USB_DSTS_DEVLNSTS_DEFAULT             0x0
-#define GC_USB_DSTS_DEVLNSTS_OFFSET              0x808
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET        0x810
-#define GC_USB_DIEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DIEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DIEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET          0x810
-#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB            0x3
-#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK           0x8
-#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE           0x1
-#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT        0x0
-#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET         0x810
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB        0x4
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK       0x10
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB         0x5
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK        0x20
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB         0x6
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK        0x40
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_RESERVED7_LSB             0x7
-#define GC_USB_DIEPMSK_RESERVED7_MASK            0x80
-#define GC_USB_DIEPMSK_RESERVED7_SIZE            0x1
-#define GC_USB_DIEPMSK_RESERVED7_DEFAULT         0x1
-#define GC_USB_DIEPMSK_RESERVED7_OFFSET          0x810
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB        0x8
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK       0x100
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_BNAININTRMSK_LSB          0x9
-#define GC_USB_DIEPMSK_BNAININTRMSK_MASK         0x200
-#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DIEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DIEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DIEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DIEPMSK_NAKMSK_OFFSET             0x810
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET        0x814
-#define GC_USB_DOEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DOEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DOEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET          0x814
-#define GC_USB_DOEPMSK_SETUPMSK_LSB              0x3
-#define GC_USB_DOEPMSK_SETUPMSK_MASK             0x8
-#define GC_USB_DOEPMSK_SETUPMSK_SIZE             0x1
-#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT          0x0
-#define GC_USB_DOEPMSK_SETUPMSK_OFFSET           0x814
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB        0x4
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK       0x10
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB        0x5
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK       0x20
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB        0x6
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK       0x40
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE       0x1
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT    0x0
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET     0x814
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB          0x8
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK         0x100
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB         0x9
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK        0x200
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE        0x1
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT     0x0
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET      0x814
-#define GC_USB_DOEPMSK_BBLEERRMSK_LSB            0xc
-#define GC_USB_DOEPMSK_BBLEERRMSK_MASK           0x1000
-#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE           0x1
-#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT        0x0
-#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET         0x814
-#define GC_USB_DOEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DOEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DOEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DOEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DOEPMSK_NAKMSK_OFFSET             0x814
-#define GC_USB_DOEPMSK_NYETMSK_LSB               0xe
-#define GC_USB_DOEPMSK_NYETMSK_MASK              0x4000
-#define GC_USB_DOEPMSK_NYETMSK_SIZE              0x1
-#define GC_USB_DOEPMSK_NYETMSK_DEFAULT           0x0
-#define GC_USB_DOEPMSK_NYETMSK_OFFSET            0x814
-#define GC_USB_DAINT_INEPINT0_LSB                0x0
-#define GC_USB_DAINT_INEPINT0_MASK               0x1
-#define GC_USB_DAINT_INEPINT0_SIZE               0x1
-#define GC_USB_DAINT_INEPINT0_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT0_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT1_LSB                0x1
-#define GC_USB_DAINT_INEPINT1_MASK               0x2
-#define GC_USB_DAINT_INEPINT1_SIZE               0x1
-#define GC_USB_DAINT_INEPINT1_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT1_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT2_LSB                0x2
-#define GC_USB_DAINT_INEPINT2_MASK               0x4
-#define GC_USB_DAINT_INEPINT2_SIZE               0x1
-#define GC_USB_DAINT_INEPINT2_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT2_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT3_LSB                0x3
-#define GC_USB_DAINT_INEPINT3_MASK               0x8
-#define GC_USB_DAINT_INEPINT3_SIZE               0x1
-#define GC_USB_DAINT_INEPINT3_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT3_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT4_LSB                0x4
-#define GC_USB_DAINT_INEPINT4_MASK               0x10
-#define GC_USB_DAINT_INEPINT4_SIZE               0x1
-#define GC_USB_DAINT_INEPINT4_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT4_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT5_LSB                0x5
-#define GC_USB_DAINT_INEPINT5_MASK               0x20
-#define GC_USB_DAINT_INEPINT5_SIZE               0x1
-#define GC_USB_DAINT_INEPINT5_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT5_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT6_LSB                0x6
-#define GC_USB_DAINT_INEPINT6_MASK               0x40
-#define GC_USB_DAINT_INEPINT6_SIZE               0x1
-#define GC_USB_DAINT_INEPINT6_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT6_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT7_LSB                0x7
-#define GC_USB_DAINT_INEPINT7_MASK               0x80
-#define GC_USB_DAINT_INEPINT7_SIZE               0x1
-#define GC_USB_DAINT_INEPINT7_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT7_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT8_LSB                0x8
-#define GC_USB_DAINT_INEPINT8_MASK               0x100
-#define GC_USB_DAINT_INEPINT8_SIZE               0x1
-#define GC_USB_DAINT_INEPINT8_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT8_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT9_LSB                0x9
-#define GC_USB_DAINT_INEPINT9_MASK               0x200
-#define GC_USB_DAINT_INEPINT9_SIZE               0x1
-#define GC_USB_DAINT_INEPINT9_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT9_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT10_LSB               0xa
-#define GC_USB_DAINT_INEPINT10_MASK              0x400
-#define GC_USB_DAINT_INEPINT10_SIZE              0x1
-#define GC_USB_DAINT_INEPINT10_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT10_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT11_LSB               0xb
-#define GC_USB_DAINT_INEPINT11_MASK              0x800
-#define GC_USB_DAINT_INEPINT11_SIZE              0x1
-#define GC_USB_DAINT_INEPINT11_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT11_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT12_LSB               0xc
-#define GC_USB_DAINT_INEPINT12_MASK              0x1000
-#define GC_USB_DAINT_INEPINT12_SIZE              0x1
-#define GC_USB_DAINT_INEPINT12_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT12_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT13_LSB               0xd
-#define GC_USB_DAINT_INEPINT13_MASK              0x2000
-#define GC_USB_DAINT_INEPINT13_SIZE              0x1
-#define GC_USB_DAINT_INEPINT13_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT13_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT14_LSB               0xe
-#define GC_USB_DAINT_INEPINT14_MASK              0x4000
-#define GC_USB_DAINT_INEPINT14_SIZE              0x1
-#define GC_USB_DAINT_INEPINT14_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT14_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT15_LSB               0xf
-#define GC_USB_DAINT_INEPINT15_MASK              0x8000
-#define GC_USB_DAINT_INEPINT15_SIZE              0x1
-#define GC_USB_DAINT_INEPINT15_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT15_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT0_LSB               0x10
-#define GC_USB_DAINT_OUTEPINT0_MASK              0x10000
-#define GC_USB_DAINT_OUTEPINT0_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT0_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT0_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT1_LSB               0x11
-#define GC_USB_DAINT_OUTEPINT1_MASK              0x20000
-#define GC_USB_DAINT_OUTEPINT1_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT1_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT1_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT2_LSB               0x12
-#define GC_USB_DAINT_OUTEPINT2_MASK              0x40000
-#define GC_USB_DAINT_OUTEPINT2_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT2_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT2_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT3_LSB               0x13
-#define GC_USB_DAINT_OUTEPINT3_MASK              0x80000
-#define GC_USB_DAINT_OUTEPINT3_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT3_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT3_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT4_LSB               0x14
-#define GC_USB_DAINT_OUTEPINT4_MASK              0x100000
-#define GC_USB_DAINT_OUTEPINT4_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT4_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT4_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT5_LSB               0x15
-#define GC_USB_DAINT_OUTEPINT5_MASK              0x200000
-#define GC_USB_DAINT_OUTEPINT5_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT5_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT5_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT6_LSB               0x16
-#define GC_USB_DAINT_OUTEPINT6_MASK              0x400000
-#define GC_USB_DAINT_OUTEPINT6_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT6_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT6_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT7_LSB               0x17
-#define GC_USB_DAINT_OUTEPINT7_MASK              0x800000
-#define GC_USB_DAINT_OUTEPINT7_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT7_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT7_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT8_LSB               0x18
-#define GC_USB_DAINT_OUTEPINT8_MASK              0x1000000
-#define GC_USB_DAINT_OUTEPINT8_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT8_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT8_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT9_LSB               0x19
-#define GC_USB_DAINT_OUTEPINT9_MASK              0x2000000
-#define GC_USB_DAINT_OUTEPINT9_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT9_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT9_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT10_LSB              0x1a
-#define GC_USB_DAINT_OUTEPINT10_MASK             0x4000000
-#define GC_USB_DAINT_OUTEPINT10_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT10_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT10_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT11_LSB              0x1b
-#define GC_USB_DAINT_OUTEPINT11_MASK             0x8000000
-#define GC_USB_DAINT_OUTEPINT11_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT11_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT11_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT12_LSB              0x1c
-#define GC_USB_DAINT_OUTEPINT12_MASK             0x10000000
-#define GC_USB_DAINT_OUTEPINT12_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT12_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT12_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT13_LSB              0x1d
-#define GC_USB_DAINT_OUTEPINT13_MASK             0x20000000
-#define GC_USB_DAINT_OUTEPINT13_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT13_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT13_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT14_LSB              0x1e
-#define GC_USB_DAINT_OUTEPINT14_MASK             0x40000000
-#define GC_USB_DAINT_OUTEPINT14_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT14_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT14_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT15_LSB              0x1f
-#define GC_USB_DAINT_OUTEPINT15_MASK             0x80000000
-#define GC_USB_DAINT_OUTEPINT15_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT15_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT15_OFFSET           0x818
-#define GC_USB_DAINTMSK_INEPMSK0_LSB             0x0
-#define GC_USB_DAINTMSK_INEPMSK0_MASK            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK0_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK1_LSB             0x1
-#define GC_USB_DAINTMSK_INEPMSK1_MASK            0x2
-#define GC_USB_DAINTMSK_INEPMSK1_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK1_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK2_LSB             0x2
-#define GC_USB_DAINTMSK_INEPMSK2_MASK            0x4
-#define GC_USB_DAINTMSK_INEPMSK2_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK2_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK3_LSB             0x3
-#define GC_USB_DAINTMSK_INEPMSK3_MASK            0x8
-#define GC_USB_DAINTMSK_INEPMSK3_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK3_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK4_LSB             0x4
-#define GC_USB_DAINTMSK_INEPMSK4_MASK            0x10
-#define GC_USB_DAINTMSK_INEPMSK4_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK4_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK5_LSB             0x5
-#define GC_USB_DAINTMSK_INEPMSK5_MASK            0x20
-#define GC_USB_DAINTMSK_INEPMSK5_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK5_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK6_LSB             0x6
-#define GC_USB_DAINTMSK_INEPMSK6_MASK            0x40
-#define GC_USB_DAINTMSK_INEPMSK6_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK6_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK7_LSB             0x7
-#define GC_USB_DAINTMSK_INEPMSK7_MASK            0x80
-#define GC_USB_DAINTMSK_INEPMSK7_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK7_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK8_LSB             0x8
-#define GC_USB_DAINTMSK_INEPMSK8_MASK            0x100
-#define GC_USB_DAINTMSK_INEPMSK8_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK8_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK9_LSB             0x9
-#define GC_USB_DAINTMSK_INEPMSK9_MASK            0x200
-#define GC_USB_DAINTMSK_INEPMSK9_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK9_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK10_LSB            0xa
-#define GC_USB_DAINTMSK_INEPMSK10_MASK           0x400
-#define GC_USB_DAINTMSK_INEPMSK10_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK10_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK11_LSB            0xb
-#define GC_USB_DAINTMSK_INEPMSK11_MASK           0x800
-#define GC_USB_DAINTMSK_INEPMSK11_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK11_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK12_LSB            0xc
-#define GC_USB_DAINTMSK_INEPMSK12_MASK           0x1000
-#define GC_USB_DAINTMSK_INEPMSK12_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK12_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK13_LSB            0xd
-#define GC_USB_DAINTMSK_INEPMSK13_MASK           0x2000
-#define GC_USB_DAINTMSK_INEPMSK13_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK13_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK14_LSB            0xe
-#define GC_USB_DAINTMSK_INEPMSK14_MASK           0x4000
-#define GC_USB_DAINTMSK_INEPMSK14_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK14_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK15_LSB            0xf
-#define GC_USB_DAINTMSK_INEPMSK15_MASK           0x8000
-#define GC_USB_DAINTMSK_INEPMSK15_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK15_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK0_LSB            0x10
-#define GC_USB_DAINTMSK_OUTEPMSK0_MASK           0x10000
-#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK1_LSB            0x11
-#define GC_USB_DAINTMSK_OUTEPMSK1_MASK           0x20000
-#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK2_LSB            0x12
-#define GC_USB_DAINTMSK_OUTEPMSK2_MASK           0x40000
-#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK3_LSB            0x13
-#define GC_USB_DAINTMSK_OUTEPMSK3_MASK           0x80000
-#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK4_LSB            0x14
-#define GC_USB_DAINTMSK_OUTEPMSK4_MASK           0x100000
-#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK5_LSB            0x15
-#define GC_USB_DAINTMSK_OUTEPMSK5_MASK           0x200000
-#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK6_LSB            0x16
-#define GC_USB_DAINTMSK_OUTEPMSK6_MASK           0x400000
-#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK7_LSB            0x17
-#define GC_USB_DAINTMSK_OUTEPMSK7_MASK           0x800000
-#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK8_LSB            0x18
-#define GC_USB_DAINTMSK_OUTEPMSK8_MASK           0x1000000
-#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK9_LSB            0x19
-#define GC_USB_DAINTMSK_OUTEPMSK9_MASK           0x2000000
-#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK10_LSB           0x1a
-#define GC_USB_DAINTMSK_OUTEPMSK10_MASK          0x4000000
-#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK11_LSB           0x1b
-#define GC_USB_DAINTMSK_OUTEPMSK11_MASK          0x8000000
-#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK12_LSB           0x1c
-#define GC_USB_DAINTMSK_OUTEPMSK12_MASK          0x10000000
-#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK13_LSB           0x1d
-#define GC_USB_DAINTMSK_OUTEPMSK13_MASK          0x20000000
-#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK14_LSB           0x1e
-#define GC_USB_DAINTMSK_OUTEPMSK14_MASK          0x40000000
-#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK15_LSB           0x1f
-#define GC_USB_DAINTMSK_OUTEPMSK15_MASK          0x80000000
-#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET        0x81c
-#define GC_USB_DVBUSDIS_DVBUSDIS_LSB             0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_MASK            0xffff
-#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE            0x10
-#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT         0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET          0x828
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB         0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK        0xfff
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE        0xc
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT     0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET      0x82c
-#define GC_USB_DTHRCTL_NONISOTHREN_LSB           0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_MASK          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_SIZE          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT       0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET        0x830
-#define GC_USB_DTHRCTL_ISOTHREN_LSB              0x1
-#define GC_USB_DTHRCTL_ISOTHREN_MASK             0x2
-#define GC_USB_DTHRCTL_ISOTHREN_SIZE             0x1
-#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ISOTHREN_OFFSET           0x830
-#define GC_USB_DTHRCTL_TXTHRLEN_LSB              0x2
-#define GC_USB_DTHRCTL_TXTHRLEN_MASK             0x7fc
-#define GC_USB_DTHRCTL_TXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB           0xb
-#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK          0x1800
-#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE          0x2
-#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT       0x0
-#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET        0x830
-#define GC_USB_DTHRCTL_RXTHREN_LSB               0x10
-#define GC_USB_DTHRCTL_RXTHREN_MASK              0x10000
-#define GC_USB_DTHRCTL_RXTHREN_SIZE              0x1
-#define GC_USB_DTHRCTL_RXTHREN_DEFAULT           0x0
-#define GC_USB_DTHRCTL_RXTHREN_OFFSET            0x830
-#define GC_USB_DTHRCTL_RXTHRLEN_LSB              0x11
-#define GC_USB_DTHRCTL_RXTHRLEN_MASK             0x3fe0000
-#define GC_USB_DTHRCTL_RXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_ARBPRKEN_LSB              0x1b
-#define GC_USB_DTHRCTL_ARBPRKEN_MASK             0x8000000
-#define GC_USB_DTHRCTL_ARBPRKEN_SIZE             0x1
-#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET           0x830
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB      0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK     0xffff
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE     0x10
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT  0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET   0x834
-#define GC_USB_DIEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DIEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DIEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL0_MPS_OFFSET               0x900
-#define GC_USB_DIEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL0_USBACTEP_OFFSET          0x900
-#define GC_USB_DIEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_NAKSTS_OFFSET            0x900
-#define GC_USB_DIEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_EPTYPE_OFFSET            0x900
-#define GC_USB_DIEPCTL0_STALL_LSB                0x15
-#define GC_USB_DIEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_STALL_OFFSET             0x900
-#define GC_USB_DIEPCTL0_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL0_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL0_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_TXFNUM_OFFSET            0x900
-#define GC_USB_DIEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_CNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_SNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPDIS_OFFSET             0x900
-#define GC_USB_DIEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPENA_OFFSET             0x900
-#define GC_USB_DIEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET         0x908
-#define GC_USB_DIEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT0_EPDISBLD_OFFSET          0x908
-#define GC_USB_DIEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT0_AHBERR_OFFSET            0x908
-#define GC_USB_DIEPINT0_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT0_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT0_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT0_TIMEOUT_OFFSET           0x908
-#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET       0x908
-#define GC_USB_DIEPINT0_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT0_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET        0x908
-#define GC_USB_DIEPINT0_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT0_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET        0x908
-#define GC_USB_DIEPINT0_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT0_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT0_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT0_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT0_TXFEMP_OFFSET            0x908
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET       0x908
-#define GC_USB_DIEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BNAINTR_OFFSET           0x908
-#define GC_USB_DIEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET         0x908
-#define GC_USB_DIEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BBLEERR_OFFSET           0x908
-#define GC_USB_DIEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET         0x908
-#define GC_USB_DIEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET        0x908
-#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET         0x910
-#define GC_USB_DIEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ0_PKTCNT_MASK             0x180000
-#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE             0x2
-#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET           0x910
-#define GC_USB_DIEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA0_DMAADDR_OFFSET           0x914
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET   0x918
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET    0x91c
-#define GC_USB_DIEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL1_MPS_OFFSET               0x920
-#define GC_USB_DIEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_USBACTEP_OFFSET          0x920
-#define GC_USB_DIEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_DPID_OFFSET              0x920
-#define GC_USB_DIEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_NAKSTS_OFFSET            0x920
-#define GC_USB_DIEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_EPTYPE_OFFSET            0x920
-#define GC_USB_DIEPCTL1_STALL_LSB                0x15
-#define GC_USB_DIEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_STALL_OFFSET             0x920
-#define GC_USB_DIEPCTL1_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL1_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL1_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_TXFNUM_OFFSET            0x920
-#define GC_USB_DIEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_CNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_SNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD0PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD1PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPDIS_OFFSET             0x920
-#define GC_USB_DIEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPENA_OFFSET             0x920
-#define GC_USB_DIEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET         0x928
-#define GC_USB_DIEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT1_EPDISBLD_OFFSET          0x928
-#define GC_USB_DIEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT1_AHBERR_OFFSET            0x928
-#define GC_USB_DIEPINT1_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT1_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT1_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT1_TIMEOUT_OFFSET           0x928
-#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET       0x928
-#define GC_USB_DIEPINT1_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT1_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET        0x928
-#define GC_USB_DIEPINT1_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT1_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET        0x928
-#define GC_USB_DIEPINT1_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT1_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT1_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT1_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT1_TXFEMP_OFFSET            0x928
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET       0x928
-#define GC_USB_DIEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BNAINTR_OFFSET           0x928
-#define GC_USB_DIEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET         0x928
-#define GC_USB_DIEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BBLEERR_OFFSET           0x928
-#define GC_USB_DIEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET         0x928
-#define GC_USB_DIEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET        0x928
-#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET         0x930
-#define GC_USB_DIEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET           0x930
-#define GC_USB_DIEPTSIZ1_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ1_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ1_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ1_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ1_MC_OFFSET               0x930
-#define GC_USB_DIEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA1_DMAADDR_OFFSET           0x934
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET   0x938
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET    0x93c
-#define GC_USB_DIEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL2_MPS_OFFSET               0x940
-#define GC_USB_DIEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_USBACTEP_OFFSET          0x940
-#define GC_USB_DIEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_DPID_OFFSET              0x940
-#define GC_USB_DIEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_NAKSTS_OFFSET            0x940
-#define GC_USB_DIEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_EPTYPE_OFFSET            0x940
-#define GC_USB_DIEPCTL2_STALL_LSB                0x15
-#define GC_USB_DIEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_STALL_OFFSET             0x940
-#define GC_USB_DIEPCTL2_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL2_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL2_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_TXFNUM_OFFSET            0x940
-#define GC_USB_DIEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_CNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_SNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD0PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD1PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPDIS_OFFSET             0x940
-#define GC_USB_DIEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPENA_OFFSET             0x940
-#define GC_USB_DIEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET         0x948
-#define GC_USB_DIEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT2_EPDISBLD_OFFSET          0x948
-#define GC_USB_DIEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT2_AHBERR_OFFSET            0x948
-#define GC_USB_DIEPINT2_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT2_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT2_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT2_TIMEOUT_OFFSET           0x948
-#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET       0x948
-#define GC_USB_DIEPINT2_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT2_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET        0x948
-#define GC_USB_DIEPINT2_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT2_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET        0x948
-#define GC_USB_DIEPINT2_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT2_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT2_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT2_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT2_TXFEMP_OFFSET            0x948
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET       0x948
-#define GC_USB_DIEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BNAINTR_OFFSET           0x948
-#define GC_USB_DIEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET         0x948
-#define GC_USB_DIEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BBLEERR_OFFSET           0x948
-#define GC_USB_DIEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET         0x948
-#define GC_USB_DIEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET        0x948
-#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET         0x950
-#define GC_USB_DIEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET           0x950
-#define GC_USB_DIEPTSIZ2_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ2_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ2_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ2_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ2_MC_OFFSET               0x950
-#define GC_USB_DIEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA2_DMAADDR_OFFSET           0x954
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET   0x958
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET    0x95c
-#define GC_USB_DIEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL3_MPS_OFFSET               0x960
-#define GC_USB_DIEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_USBACTEP_OFFSET          0x960
-#define GC_USB_DIEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_DPID_OFFSET              0x960
-#define GC_USB_DIEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_NAKSTS_OFFSET            0x960
-#define GC_USB_DIEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_EPTYPE_OFFSET            0x960
-#define GC_USB_DIEPCTL3_STALL_LSB                0x15
-#define GC_USB_DIEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_STALL_OFFSET             0x960
-#define GC_USB_DIEPCTL3_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL3_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL3_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_TXFNUM_OFFSET            0x960
-#define GC_USB_DIEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_CNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_SNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD0PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD1PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPDIS_OFFSET             0x960
-#define GC_USB_DIEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPENA_OFFSET             0x960
-#define GC_USB_DIEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET         0x968
-#define GC_USB_DIEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT3_EPDISBLD_OFFSET          0x968
-#define GC_USB_DIEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT3_AHBERR_OFFSET            0x968
-#define GC_USB_DIEPINT3_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT3_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT3_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT3_TIMEOUT_OFFSET           0x968
-#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET       0x968
-#define GC_USB_DIEPINT3_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT3_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET        0x968
-#define GC_USB_DIEPINT3_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT3_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET        0x968
-#define GC_USB_DIEPINT3_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT3_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT3_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT3_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT3_TXFEMP_OFFSET            0x968
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET       0x968
-#define GC_USB_DIEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BNAINTR_OFFSET           0x968
-#define GC_USB_DIEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET         0x968
-#define GC_USB_DIEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BBLEERR_OFFSET           0x968
-#define GC_USB_DIEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET         0x968
-#define GC_USB_DIEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET        0x968
-#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET         0x970
-#define GC_USB_DIEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET           0x970
-#define GC_USB_DIEPTSIZ3_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ3_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ3_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ3_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ3_MC_OFFSET               0x970
-#define GC_USB_DIEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA3_DMAADDR_OFFSET           0x974
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET   0x978
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET    0x97c
-#define GC_USB_DIEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL4_MPS_OFFSET               0x980
-#define GC_USB_DIEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_USBACTEP_OFFSET          0x980
-#define GC_USB_DIEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_DPID_OFFSET              0x980
-#define GC_USB_DIEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_NAKSTS_OFFSET            0x980
-#define GC_USB_DIEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_EPTYPE_OFFSET            0x980
-#define GC_USB_DIEPCTL4_STALL_LSB                0x15
-#define GC_USB_DIEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_STALL_OFFSET             0x980
-#define GC_USB_DIEPCTL4_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL4_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL4_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_TXFNUM_OFFSET            0x980
-#define GC_USB_DIEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_CNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_SNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD0PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD1PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPDIS_OFFSET             0x980
-#define GC_USB_DIEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPENA_OFFSET             0x980
-#define GC_USB_DIEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET         0x988
-#define GC_USB_DIEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT4_EPDISBLD_OFFSET          0x988
-#define GC_USB_DIEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT4_AHBERR_OFFSET            0x988
-#define GC_USB_DIEPINT4_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT4_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT4_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT4_TIMEOUT_OFFSET           0x988
-#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET       0x988
-#define GC_USB_DIEPINT4_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT4_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET        0x988
-#define GC_USB_DIEPINT4_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT4_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET        0x988
-#define GC_USB_DIEPINT4_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT4_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT4_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT4_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT4_TXFEMP_OFFSET            0x988
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET       0x988
-#define GC_USB_DIEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BNAINTR_OFFSET           0x988
-#define GC_USB_DIEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET         0x988
-#define GC_USB_DIEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BBLEERR_OFFSET           0x988
-#define GC_USB_DIEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET         0x988
-#define GC_USB_DIEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET        0x988
-#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET         0x990
-#define GC_USB_DIEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET           0x990
-#define GC_USB_DIEPTSIZ4_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ4_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ4_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ4_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ4_MC_OFFSET               0x990
-#define GC_USB_DIEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA4_DMAADDR_OFFSET           0x994
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET   0x998
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET    0x99c
-#define GC_USB_DIEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL5_MPS_OFFSET               0x9a0
-#define GC_USB_DIEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_USBACTEP_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_DPID_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_NAKSTS_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_EPTYPE_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_STALL_LSB                0x15
-#define GC_USB_DIEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_STALL_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL5_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL5_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_TXFNUM_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_CNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_SNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD0PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD1PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPDIS_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPENA_OFFSET             0x9a0
-#define GC_USB_DIEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT5_EPDISBLD_OFFSET          0x9a8
-#define GC_USB_DIEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT5_AHBERR_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT5_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT5_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT5_TIMEOUT_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT5_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT5_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT5_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT5_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT5_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT5_TXFEMP_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BNAINTR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BBLEERR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET        0x9a8
-#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET         0x9b0
-#define GC_USB_DIEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET           0x9b0
-#define GC_USB_DIEPTSIZ5_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ5_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ5_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ5_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ5_MC_OFFSET               0x9b0
-#define GC_USB_DIEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA5_DMAADDR_OFFSET           0x9b4
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET   0x9b8
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET    0x9bc
-#define GC_USB_DIEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL6_MPS_OFFSET               0x9c0
-#define GC_USB_DIEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_USBACTEP_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_DPID_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_NAKSTS_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_EPTYPE_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_STALL_LSB                0x15
-#define GC_USB_DIEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_STALL_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL6_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL6_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_TXFNUM_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_CNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_SNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD0PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD1PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPDIS_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPENA_OFFSET             0x9c0
-#define GC_USB_DIEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT6_EPDISBLD_OFFSET          0x9c8
-#define GC_USB_DIEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT6_AHBERR_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT6_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT6_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT6_TIMEOUT_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT6_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT6_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT6_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT6_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT6_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT6_TXFEMP_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BNAINTR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BBLEERR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET        0x9c8
-#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET         0x9d0
-#define GC_USB_DIEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET           0x9d0
-#define GC_USB_DIEPTSIZ6_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ6_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ6_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ6_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ6_MC_OFFSET               0x9d0
-#define GC_USB_DIEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA6_DMAADDR_OFFSET           0x9d4
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET   0x9d8
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET    0x9dc
-#define GC_USB_DIEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL7_MPS_OFFSET               0x9e0
-#define GC_USB_DIEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_USBACTEP_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_DPID_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_NAKSTS_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_EPTYPE_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_STALL_LSB                0x15
-#define GC_USB_DIEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_STALL_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL7_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL7_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_TXFNUM_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_CNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_SNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD0PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD1PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPDIS_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPENA_OFFSET             0x9e0
-#define GC_USB_DIEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT7_EPDISBLD_OFFSET          0x9e8
-#define GC_USB_DIEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT7_AHBERR_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT7_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT7_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT7_TIMEOUT_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT7_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT7_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT7_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT7_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT7_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT7_TXFEMP_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BNAINTR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BBLEERR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET        0x9e8
-#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET         0x9f0
-#define GC_USB_DIEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET           0x9f0
-#define GC_USB_DIEPTSIZ7_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ7_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ7_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ7_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ7_MC_OFFSET               0x9f0
-#define GC_USB_DIEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA7_DMAADDR_OFFSET           0x9f4
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET   0x9f8
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET    0x9fc
-#define GC_USB_DIEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL8_MPS_OFFSET               0xa00
-#define GC_USB_DIEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_USBACTEP_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_DPID_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_NAKSTS_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_EPTYPE_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_STALL_LSB                0x15
-#define GC_USB_DIEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_STALL_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL8_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL8_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_TXFNUM_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_CNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_SNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD0PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD1PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPDIS_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPENA_OFFSET             0xa00
-#define GC_USB_DIEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET         0xa08
-#define GC_USB_DIEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT8_EPDISBLD_OFFSET          0xa08
-#define GC_USB_DIEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT8_AHBERR_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT8_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT8_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT8_TIMEOUT_OFFSET           0xa08
-#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET       0xa08
-#define GC_USB_DIEPINT8_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT8_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET        0xa08
-#define GC_USB_DIEPINT8_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT8_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET        0xa08
-#define GC_USB_DIEPINT8_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT8_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT8_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT8_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT8_TXFEMP_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET       0xa08
-#define GC_USB_DIEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BNAINTR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET         0xa08
-#define GC_USB_DIEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BBLEERR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET         0xa08
-#define GC_USB_DIEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET        0xa08
-#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET         0xa10
-#define GC_USB_DIEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET           0xa10
-#define GC_USB_DIEPTSIZ8_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ8_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ8_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ8_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ8_MC_OFFSET               0xa10
-#define GC_USB_DIEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA8_DMAADDR_OFFSET           0xa14
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET   0xa18
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET    0xa1c
-#define GC_USB_DIEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL9_MPS_OFFSET               0xa20
-#define GC_USB_DIEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_USBACTEP_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_DPID_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_NAKSTS_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_EPTYPE_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_STALL_LSB                0x15
-#define GC_USB_DIEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_STALL_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL9_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL9_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_TXFNUM_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_CNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_SNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD0PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD1PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPDIS_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPENA_OFFSET             0xa20
-#define GC_USB_DIEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET         0xa28
-#define GC_USB_DIEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT9_EPDISBLD_OFFSET          0xa28
-#define GC_USB_DIEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT9_AHBERR_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT9_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT9_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT9_TIMEOUT_OFFSET           0xa28
-#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET       0xa28
-#define GC_USB_DIEPINT9_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT9_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET        0xa28
-#define GC_USB_DIEPINT9_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT9_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET        0xa28
-#define GC_USB_DIEPINT9_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT9_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT9_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT9_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT9_TXFEMP_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET       0xa28
-#define GC_USB_DIEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BNAINTR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET         0xa28
-#define GC_USB_DIEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BBLEERR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET         0xa28
-#define GC_USB_DIEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET        0xa28
-#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET         0xa30
-#define GC_USB_DIEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET           0xa30
-#define GC_USB_DIEPTSIZ9_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ9_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ9_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ9_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ9_MC_OFFSET               0xa30
-#define GC_USB_DIEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA9_DMAADDR_OFFSET           0xa34
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET   0xa38
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET    0xa3c
-#define GC_USB_DIEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL10_MPS_OFFSET              0xa40
-#define GC_USB_DIEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_USBACTEP_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_DPID_LSB                0x10
-#define GC_USB_DIEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_DPID_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_NAKSTS_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_EPTYPE_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_STALL_LSB               0x15
-#define GC_USB_DIEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_STALL_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL10_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL10_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_TXFNUM_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_CNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_SNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD0PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD1PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPDIS_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPENA_OFFSET            0xa40
-#define GC_USB_DIEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET        0xa48
-#define GC_USB_DIEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT10_EPDISBLD_OFFSET         0xa48
-#define GC_USB_DIEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT10_AHBERR_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT10_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT10_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT10_TIMEOUT_OFFSET          0xa48
-#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET      0xa48
-#define GC_USB_DIEPINT10_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT10_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET       0xa48
-#define GC_USB_DIEPINT10_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT10_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET       0xa48
-#define GC_USB_DIEPINT10_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT10_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT10_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT10_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT10_TXFEMP_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET      0xa48
-#define GC_USB_DIEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BNAINTR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET        0xa48
-#define GC_USB_DIEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BBLEERR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET        0xa48
-#define GC_USB_DIEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET       0xa48
-#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET        0xa50
-#define GC_USB_DIEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET          0xa50
-#define GC_USB_DIEPTSIZ10_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ10_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ10_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ10_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ10_MC_OFFSET              0xa50
-#define GC_USB_DIEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA10_DMAADDR_OFFSET          0xa54
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET  0xa58
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET   0xa5c
-#define GC_USB_DIEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL11_MPS_OFFSET              0xa60
-#define GC_USB_DIEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_USBACTEP_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_DPID_LSB                0x10
-#define GC_USB_DIEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_DPID_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_NAKSTS_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_EPTYPE_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_STALL_LSB               0x15
-#define GC_USB_DIEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_STALL_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL11_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL11_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_TXFNUM_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_CNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_SNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD0PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD1PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPDIS_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPENA_OFFSET            0xa60
-#define GC_USB_DIEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET        0xa68
-#define GC_USB_DIEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT11_EPDISBLD_OFFSET         0xa68
-#define GC_USB_DIEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT11_AHBERR_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT11_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT11_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT11_TIMEOUT_OFFSET          0xa68
-#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET      0xa68
-#define GC_USB_DIEPINT11_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT11_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET       0xa68
-#define GC_USB_DIEPINT11_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT11_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET       0xa68
-#define GC_USB_DIEPINT11_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT11_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT11_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT11_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT11_TXFEMP_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET      0xa68
-#define GC_USB_DIEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BNAINTR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET        0xa68
-#define GC_USB_DIEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BBLEERR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET        0xa68
-#define GC_USB_DIEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET       0xa68
-#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET        0xa70
-#define GC_USB_DIEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET          0xa70
-#define GC_USB_DIEPTSIZ11_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ11_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ11_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ11_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ11_MC_OFFSET              0xa70
-#define GC_USB_DIEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA11_DMAADDR_OFFSET          0xa74
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET  0xa78
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET   0xa7c
-#define GC_USB_DIEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL12_MPS_OFFSET              0xa80
-#define GC_USB_DIEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_USBACTEP_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_DPID_LSB                0x10
-#define GC_USB_DIEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_DPID_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_NAKSTS_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_EPTYPE_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_STALL_LSB               0x15
-#define GC_USB_DIEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_STALL_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL12_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL12_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_TXFNUM_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_CNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_SNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD0PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD1PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPDIS_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPENA_OFFSET            0xa80
-#define GC_USB_DIEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET        0xa88
-#define GC_USB_DIEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT12_EPDISBLD_OFFSET         0xa88
-#define GC_USB_DIEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT12_AHBERR_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT12_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT12_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT12_TIMEOUT_OFFSET          0xa88
-#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET      0xa88
-#define GC_USB_DIEPINT12_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT12_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET       0xa88
-#define GC_USB_DIEPINT12_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT12_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET       0xa88
-#define GC_USB_DIEPINT12_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT12_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT12_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT12_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT12_TXFEMP_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET      0xa88
-#define GC_USB_DIEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BNAINTR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET        0xa88
-#define GC_USB_DIEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BBLEERR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET        0xa88
-#define GC_USB_DIEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET       0xa88
-#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET        0xa90
-#define GC_USB_DIEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET          0xa90
-#define GC_USB_DIEPTSIZ12_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ12_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ12_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ12_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ12_MC_OFFSET              0xa90
-#define GC_USB_DIEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA12_DMAADDR_OFFSET          0xa94
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET  0xa98
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET   0xa9c
-#define GC_USB_DIEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL13_MPS_OFFSET              0xaa0
-#define GC_USB_DIEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_USBACTEP_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_DPID_LSB                0x10
-#define GC_USB_DIEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_DPID_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_NAKSTS_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_EPTYPE_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_STALL_LSB               0x15
-#define GC_USB_DIEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_STALL_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL13_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL13_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_TXFNUM_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_CNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_SNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD0PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD1PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPDIS_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPENA_OFFSET            0xaa0
-#define GC_USB_DIEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT13_EPDISBLD_OFFSET         0xaa8
-#define GC_USB_DIEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT13_AHBERR_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT13_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT13_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT13_TIMEOUT_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT13_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT13_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT13_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT13_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT13_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT13_TXFEMP_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BNAINTR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BBLEERR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET       0xaa8
-#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET        0xab0
-#define GC_USB_DIEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET          0xab0
-#define GC_USB_DIEPTSIZ13_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ13_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ13_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ13_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ13_MC_OFFSET              0xab0
-#define GC_USB_DIEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA13_DMAADDR_OFFSET          0xab4
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET  0xab8
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET   0xabc
-#define GC_USB_DIEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL14_MPS_OFFSET              0xac0
-#define GC_USB_DIEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_USBACTEP_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_DPID_LSB                0x10
-#define GC_USB_DIEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_DPID_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_NAKSTS_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_EPTYPE_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_STALL_LSB               0x15
-#define GC_USB_DIEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_STALL_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL14_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL14_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_TXFNUM_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_CNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_SNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD0PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD1PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPDIS_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPENA_OFFSET            0xac0
-#define GC_USB_DIEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET        0xac8
-#define GC_USB_DIEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT14_EPDISBLD_OFFSET         0xac8
-#define GC_USB_DIEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT14_AHBERR_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT14_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT14_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT14_TIMEOUT_OFFSET          0xac8
-#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET      0xac8
-#define GC_USB_DIEPINT14_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT14_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET       0xac8
-#define GC_USB_DIEPINT14_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT14_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET       0xac8
-#define GC_USB_DIEPINT14_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT14_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT14_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT14_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT14_TXFEMP_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET      0xac8
-#define GC_USB_DIEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BNAINTR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET        0xac8
-#define GC_USB_DIEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BBLEERR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET        0xac8
-#define GC_USB_DIEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET       0xac8
-#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET        0xad0
-#define GC_USB_DIEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET          0xad0
-#define GC_USB_DIEPTSIZ14_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ14_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ14_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ14_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ14_MC_OFFSET              0xad0
-#define GC_USB_DIEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA14_DMAADDR_OFFSET          0xad4
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET  0xad8
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET   0xadc
-#define GC_USB_DIEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL15_MPS_OFFSET              0xae0
-#define GC_USB_DIEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_USBACTEP_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_DPID_LSB                0x10
-#define GC_USB_DIEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_DPID_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_NAKSTS_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_EPTYPE_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_STALL_LSB               0x15
-#define GC_USB_DIEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_STALL_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL15_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL15_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_TXFNUM_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_CNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_SNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD0PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD1PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPDIS_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPENA_OFFSET            0xae0
-#define GC_USB_DIEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET        0xae8
-#define GC_USB_DIEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT15_EPDISBLD_OFFSET         0xae8
-#define GC_USB_DIEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT15_AHBERR_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT15_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT15_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT15_TIMEOUT_OFFSET          0xae8
-#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET      0xae8
-#define GC_USB_DIEPINT15_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT15_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET       0xae8
-#define GC_USB_DIEPINT15_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT15_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET       0xae8
-#define GC_USB_DIEPINT15_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT15_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT15_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT15_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT15_TXFEMP_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET      0xae8
-#define GC_USB_DIEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BNAINTR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET        0xae8
-#define GC_USB_DIEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BBLEERR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET        0xae8
-#define GC_USB_DIEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET       0xae8
-#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET        0xaf0
-#define GC_USB_DIEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET          0xaf0
-#define GC_USB_DIEPTSIZ15_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ15_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ15_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ15_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ15_MC_OFFSET              0xaf0
-#define GC_USB_DIEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA15_DMAADDR_OFFSET          0xaf4
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET  0xaf8
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET   0xafc
-#define GC_USB_DOEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DOEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DOEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_MPS_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL0_USBACTEP_OFFSET          0xb00
-#define GC_USB_DOEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_NAKSTS_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_EPTYPE_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL0_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL0_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL0_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_SNP_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_STALL_LSB                0x15
-#define GC_USB_DOEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_STALL_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_CNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_SNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPDIS_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPENA_OFFSET             0xb00
-#define GC_USB_DOEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET         0xb08
-#define GC_USB_DOEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT0_EPDISBLD_OFFSET          0xb08
-#define GC_USB_DOEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT0_AHBERR_OFFSET            0xb08
-#define GC_USB_DOEPINT0_SETUP_LSB                0x3
-#define GC_USB_DOEPINT0_SETUP_MASK               0x8
-#define GC_USB_DOEPINT0_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT0_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT0_SETUP_OFFSET             0xb08
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET       0xb08
-#define GC_USB_DOEPINT0_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT0_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET       0xb08
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET    0xb08
-#define GC_USB_DOEPINT0_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT0_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT0_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BNAINTR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BBLEERR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET         0xb08
-#define GC_USB_DOEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET        0xb08
-#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET       0xb08
-#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET         0xb10
-#define GC_USB_DOEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ0_PKTCNT_MASK             0x80000
-#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE             0x1
-#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET           0xb10
-#define GC_USB_DOEPTSIZ0_SUPCNT_LSB              0x1d
-#define GC_USB_DOEPTSIZ0_SUPCNT_MASK             0x60000000
-#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE             0x2
-#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET           0xb10
-#define GC_USB_DOEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA0_DMAADDR_OFFSET           0xb14
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET    0xb1c
-#define GC_USB_DOEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_MPS_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_USBACTEP_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_DPID_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_NAKSTS_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_EPTYPE_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL1_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL1_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL1_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_SNP_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_STALL_LSB                0x15
-#define GC_USB_DOEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_STALL_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_CNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_SNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD0PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD1PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPDIS_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPENA_OFFSET             0xb20
-#define GC_USB_DOEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET         0xb28
-#define GC_USB_DOEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT1_EPDISBLD_OFFSET          0xb28
-#define GC_USB_DOEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT1_AHBERR_OFFSET            0xb28
-#define GC_USB_DOEPINT1_SETUP_LSB                0x3
-#define GC_USB_DOEPINT1_SETUP_MASK               0x8
-#define GC_USB_DOEPINT1_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT1_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT1_SETUP_OFFSET             0xb28
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET       0xb28
-#define GC_USB_DOEPINT1_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT1_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET       0xb28
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET    0xb28
-#define GC_USB_DOEPINT1_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT1_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT1_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BNAINTR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BBLEERR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET         0xb28
-#define GC_USB_DOEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET        0xb28
-#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET       0xb28
-#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET         0xb30
-#define GC_USB_DOEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET           0xb30
-#define GC_USB_DOEPTSIZ1_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ1_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ1_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET           0xb30
-#define GC_USB_DOEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA1_DMAADDR_OFFSET           0xb34
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET    0xb3c
-#define GC_USB_DOEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_MPS_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_USBACTEP_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_DPID_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_NAKSTS_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_EPTYPE_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL2_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL2_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL2_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_SNP_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_STALL_LSB                0x15
-#define GC_USB_DOEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_STALL_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_CNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_SNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD0PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD1PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPDIS_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPENA_OFFSET             0xb40
-#define GC_USB_DOEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET         0xb48
-#define GC_USB_DOEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT2_EPDISBLD_OFFSET          0xb48
-#define GC_USB_DOEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT2_AHBERR_OFFSET            0xb48
-#define GC_USB_DOEPINT2_SETUP_LSB                0x3
-#define GC_USB_DOEPINT2_SETUP_MASK               0x8
-#define GC_USB_DOEPINT2_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT2_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT2_SETUP_OFFSET             0xb48
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET       0xb48
-#define GC_USB_DOEPINT2_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT2_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET       0xb48
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET    0xb48
-#define GC_USB_DOEPINT2_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT2_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT2_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BNAINTR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BBLEERR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET         0xb48
-#define GC_USB_DOEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET        0xb48
-#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET       0xb48
-#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET         0xb50
-#define GC_USB_DOEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET           0xb50
-#define GC_USB_DOEPTSIZ2_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ2_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ2_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET           0xb50
-#define GC_USB_DOEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA2_DMAADDR_OFFSET           0xb54
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET    0xb5c
-#define GC_USB_DOEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_MPS_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_USBACTEP_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_DPID_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_NAKSTS_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_EPTYPE_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL3_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL3_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL3_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_SNP_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_STALL_LSB                0x15
-#define GC_USB_DOEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_STALL_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_CNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_SNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD0PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD1PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPDIS_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPENA_OFFSET             0xb60
-#define GC_USB_DOEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET         0xb68
-#define GC_USB_DOEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT3_EPDISBLD_OFFSET          0xb68
-#define GC_USB_DOEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT3_AHBERR_OFFSET            0xb68
-#define GC_USB_DOEPINT3_SETUP_LSB                0x3
-#define GC_USB_DOEPINT3_SETUP_MASK               0x8
-#define GC_USB_DOEPINT3_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT3_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT3_SETUP_OFFSET             0xb68
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET       0xb68
-#define GC_USB_DOEPINT3_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT3_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET       0xb68
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET    0xb68
-#define GC_USB_DOEPINT3_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT3_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT3_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BNAINTR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BBLEERR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET         0xb68
-#define GC_USB_DOEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET        0xb68
-#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET       0xb68
-#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET         0xb70
-#define GC_USB_DOEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET           0xb70
-#define GC_USB_DOEPTSIZ3_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ3_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ3_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET           0xb70
-#define GC_USB_DOEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA3_DMAADDR_OFFSET           0xb74
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET    0xb7c
-#define GC_USB_DOEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_MPS_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_USBACTEP_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_DPID_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_NAKSTS_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_EPTYPE_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL4_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL4_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL4_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_SNP_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_STALL_LSB                0x15
-#define GC_USB_DOEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_STALL_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_CNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_SNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD0PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD1PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPDIS_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPENA_OFFSET             0xb80
-#define GC_USB_DOEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET         0xb88
-#define GC_USB_DOEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT4_EPDISBLD_OFFSET          0xb88
-#define GC_USB_DOEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT4_AHBERR_OFFSET            0xb88
-#define GC_USB_DOEPINT4_SETUP_LSB                0x3
-#define GC_USB_DOEPINT4_SETUP_MASK               0x8
-#define GC_USB_DOEPINT4_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT4_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT4_SETUP_OFFSET             0xb88
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET       0xb88
-#define GC_USB_DOEPINT4_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT4_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET       0xb88
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET    0xb88
-#define GC_USB_DOEPINT4_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT4_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT4_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BNAINTR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BBLEERR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET         0xb88
-#define GC_USB_DOEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET        0xb88
-#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET       0xb88
-#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET         0xb90
-#define GC_USB_DOEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET           0xb90
-#define GC_USB_DOEPTSIZ4_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ4_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ4_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET           0xb90
-#define GC_USB_DOEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA4_DMAADDR_OFFSET           0xb94
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET    0xb9c
-#define GC_USB_DOEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_MPS_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_USBACTEP_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_DPID_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_NAKSTS_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_EPTYPE_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL5_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL5_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL5_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_SNP_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_STALL_LSB                0x15
-#define GC_USB_DOEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_STALL_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_CNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_SNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD0PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD1PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPDIS_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPENA_OFFSET             0xba0
-#define GC_USB_DOEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET         0xba8
-#define GC_USB_DOEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT5_EPDISBLD_OFFSET          0xba8
-#define GC_USB_DOEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT5_AHBERR_OFFSET            0xba8
-#define GC_USB_DOEPINT5_SETUP_LSB                0x3
-#define GC_USB_DOEPINT5_SETUP_MASK               0x8
-#define GC_USB_DOEPINT5_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT5_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT5_SETUP_OFFSET             0xba8
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET       0xba8
-#define GC_USB_DOEPINT5_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT5_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET       0xba8
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET    0xba8
-#define GC_USB_DOEPINT5_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT5_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT5_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BNAINTR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BBLEERR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET         0xba8
-#define GC_USB_DOEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET        0xba8
-#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET       0xba8
-#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET         0xbb0
-#define GC_USB_DOEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET           0xbb0
-#define GC_USB_DOEPTSIZ5_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ5_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ5_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET           0xbb0
-#define GC_USB_DOEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA5_DMAADDR_OFFSET           0xbb4
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET    0xbbc
-#define GC_USB_DOEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_MPS_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_USBACTEP_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_DPID_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_NAKSTS_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_EPTYPE_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL6_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL6_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL6_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_SNP_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_STALL_LSB                0x15
-#define GC_USB_DOEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_STALL_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_CNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_SNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD0PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD1PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPDIS_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPENA_OFFSET             0xbc0
-#define GC_USB_DOEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT6_EPDISBLD_OFFSET          0xbc8
-#define GC_USB_DOEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT6_AHBERR_OFFSET            0xbc8
-#define GC_USB_DOEPINT6_SETUP_LSB                0x3
-#define GC_USB_DOEPINT6_SETUP_MASK               0x8
-#define GC_USB_DOEPINT6_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT6_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT6_SETUP_OFFSET             0xbc8
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT6_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET    0xbc8
-#define GC_USB_DOEPINT6_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT6_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT6_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BNAINTR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BBLEERR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET        0xbc8
-#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET       0xbc8
-#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET         0xbd0
-#define GC_USB_DOEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET           0xbd0
-#define GC_USB_DOEPTSIZ6_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ6_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ6_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET           0xbd0
-#define GC_USB_DOEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA6_DMAADDR_OFFSET           0xbd4
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET    0xbdc
-#define GC_USB_DOEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_MPS_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_USBACTEP_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_DPID_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_NAKSTS_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_EPTYPE_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL7_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL7_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL7_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_SNP_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_STALL_LSB                0x15
-#define GC_USB_DOEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_STALL_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_CNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_SNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD0PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD1PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPDIS_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPENA_OFFSET             0xbe0
-#define GC_USB_DOEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT7_EPDISBLD_OFFSET          0xbe8
-#define GC_USB_DOEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT7_AHBERR_OFFSET            0xbe8
-#define GC_USB_DOEPINT7_SETUP_LSB                0x3
-#define GC_USB_DOEPINT7_SETUP_MASK               0x8
-#define GC_USB_DOEPINT7_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT7_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT7_SETUP_OFFSET             0xbe8
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT7_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET    0xbe8
-#define GC_USB_DOEPINT7_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT7_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT7_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BNAINTR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BBLEERR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET        0xbe8
-#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET       0xbe8
-#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET         0xbf0
-#define GC_USB_DOEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET           0xbf0
-#define GC_USB_DOEPTSIZ7_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ7_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ7_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET           0xbf0
-#define GC_USB_DOEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA7_DMAADDR_OFFSET           0xbf4
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET    0xbfc
-#define GC_USB_DOEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_MPS_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_USBACTEP_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_DPID_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_NAKSTS_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_EPTYPE_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL8_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL8_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL8_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_SNP_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_STALL_LSB                0x15
-#define GC_USB_DOEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_STALL_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_CNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_SNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD0PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD1PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPDIS_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPENA_OFFSET             0xc00
-#define GC_USB_DOEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET         0xc08
-#define GC_USB_DOEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT8_EPDISBLD_OFFSET          0xc08
-#define GC_USB_DOEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT8_AHBERR_OFFSET            0xc08
-#define GC_USB_DOEPINT8_SETUP_LSB                0x3
-#define GC_USB_DOEPINT8_SETUP_MASK               0x8
-#define GC_USB_DOEPINT8_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT8_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT8_SETUP_OFFSET             0xc08
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET       0xc08
-#define GC_USB_DOEPINT8_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT8_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET       0xc08
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET    0xc08
-#define GC_USB_DOEPINT8_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT8_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT8_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BNAINTR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BBLEERR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET         0xc08
-#define GC_USB_DOEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET        0xc08
-#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET       0xc08
-#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET         0xc10
-#define GC_USB_DOEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET           0xc10
-#define GC_USB_DOEPTSIZ8_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ8_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ8_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET           0xc10
-#define GC_USB_DOEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA8_DMAADDR_OFFSET           0xc14
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET    0xc1c
-#define GC_USB_DOEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_MPS_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_USBACTEP_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_DPID_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_NAKSTS_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_EPTYPE_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL9_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL9_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL9_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_SNP_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_STALL_LSB                0x15
-#define GC_USB_DOEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_STALL_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_CNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_SNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD0PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD1PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPDIS_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPENA_OFFSET             0xc20
-#define GC_USB_DOEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET         0xc28
-#define GC_USB_DOEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT9_EPDISBLD_OFFSET          0xc28
-#define GC_USB_DOEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT9_AHBERR_OFFSET            0xc28
-#define GC_USB_DOEPINT9_SETUP_LSB                0x3
-#define GC_USB_DOEPINT9_SETUP_MASK               0x8
-#define GC_USB_DOEPINT9_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT9_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT9_SETUP_OFFSET             0xc28
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET       0xc28
-#define GC_USB_DOEPINT9_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT9_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET       0xc28
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET    0xc28
-#define GC_USB_DOEPINT9_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT9_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT9_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BNAINTR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BBLEERR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET         0xc28
-#define GC_USB_DOEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET        0xc28
-#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET       0xc28
-#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET         0xc30
-#define GC_USB_DOEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET           0xc30
-#define GC_USB_DOEPTSIZ9_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ9_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ9_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET           0xc30
-#define GC_USB_DOEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA9_DMAADDR_OFFSET           0xc34
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET    0xc3c
-#define GC_USB_DOEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_MPS_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_USBACTEP_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_DPID_LSB                0x10
-#define GC_USB_DOEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_DPID_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_NAKSTS_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_EPTYPE_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL10_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL10_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL10_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_SNP_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_STALL_LSB               0x15
-#define GC_USB_DOEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_STALL_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_CNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_SNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD0PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD1PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPDIS_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPENA_OFFSET            0xc40
-#define GC_USB_DOEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET        0xc48
-#define GC_USB_DOEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT10_EPDISBLD_OFFSET         0xc48
-#define GC_USB_DOEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT10_AHBERR_OFFSET           0xc48
-#define GC_USB_DOEPINT10_SETUP_LSB               0x3
-#define GC_USB_DOEPINT10_SETUP_MASK              0x8
-#define GC_USB_DOEPINT10_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT10_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT10_SETUP_OFFSET            0xc48
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET      0xc48
-#define GC_USB_DOEPINT10_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT10_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET      0xc48
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET   0xc48
-#define GC_USB_DOEPINT10_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT10_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT10_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BNAINTR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BBLEERR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET        0xc48
-#define GC_USB_DOEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET       0xc48
-#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET      0xc48
-#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET        0xc50
-#define GC_USB_DOEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET          0xc50
-#define GC_USB_DOEPTSIZ10_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ10_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ10_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET          0xc50
-#define GC_USB_DOEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA10_DMAADDR_OFFSET          0xc54
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET   0xc5c
-#define GC_USB_DOEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_MPS_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_USBACTEP_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_DPID_LSB                0x10
-#define GC_USB_DOEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_DPID_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_NAKSTS_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_EPTYPE_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL11_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL11_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL11_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_SNP_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_STALL_LSB               0x15
-#define GC_USB_DOEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_STALL_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_CNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_SNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD0PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD1PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPDIS_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPENA_OFFSET            0xc60
-#define GC_USB_DOEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET        0xc68
-#define GC_USB_DOEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT11_EPDISBLD_OFFSET         0xc68
-#define GC_USB_DOEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT11_AHBERR_OFFSET           0xc68
-#define GC_USB_DOEPINT11_SETUP_LSB               0x3
-#define GC_USB_DOEPINT11_SETUP_MASK              0x8
-#define GC_USB_DOEPINT11_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT11_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT11_SETUP_OFFSET            0xc68
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET      0xc68
-#define GC_USB_DOEPINT11_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT11_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET      0xc68
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET   0xc68
-#define GC_USB_DOEPINT11_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT11_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT11_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BNAINTR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BBLEERR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET        0xc68
-#define GC_USB_DOEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET       0xc68
-#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET      0xc68
-#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET        0xc70
-#define GC_USB_DOEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET          0xc70
-#define GC_USB_DOEPTSIZ11_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ11_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ11_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET          0xc70
-#define GC_USB_DOEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA11_DMAADDR_OFFSET          0xc74
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET   0xc7c
-#define GC_USB_DOEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_MPS_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_USBACTEP_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_DPID_LSB                0x10
-#define GC_USB_DOEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_DPID_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_NAKSTS_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_EPTYPE_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL12_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL12_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL12_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_SNP_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_STALL_LSB               0x15
-#define GC_USB_DOEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_STALL_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_CNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_SNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD0PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD1PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPDIS_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPENA_OFFSET            0xc80
-#define GC_USB_DOEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET        0xc88
-#define GC_USB_DOEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT12_EPDISBLD_OFFSET         0xc88
-#define GC_USB_DOEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT12_AHBERR_OFFSET           0xc88
-#define GC_USB_DOEPINT12_SETUP_LSB               0x3
-#define GC_USB_DOEPINT12_SETUP_MASK              0x8
-#define GC_USB_DOEPINT12_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT12_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT12_SETUP_OFFSET            0xc88
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET      0xc88
-#define GC_USB_DOEPINT12_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT12_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET      0xc88
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET   0xc88
-#define GC_USB_DOEPINT12_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT12_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT12_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BNAINTR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BBLEERR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET        0xc88
-#define GC_USB_DOEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET       0xc88
-#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET      0xc88
-#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET        0xc90
-#define GC_USB_DOEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET          0xc90
-#define GC_USB_DOEPTSIZ12_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ12_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ12_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET          0xc90
-#define GC_USB_DOEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA12_DMAADDR_OFFSET          0xc94
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET   0xc9c
-#define GC_USB_DOEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_MPS_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_USBACTEP_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_DPID_LSB                0x10
-#define GC_USB_DOEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_DPID_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_NAKSTS_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_EPTYPE_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL13_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL13_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL13_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_SNP_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_STALL_LSB               0x15
-#define GC_USB_DOEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_STALL_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_CNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_SNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD0PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD1PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPDIS_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPENA_OFFSET            0xca0
-#define GC_USB_DOEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET        0xca8
-#define GC_USB_DOEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT13_EPDISBLD_OFFSET         0xca8
-#define GC_USB_DOEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT13_AHBERR_OFFSET           0xca8
-#define GC_USB_DOEPINT13_SETUP_LSB               0x3
-#define GC_USB_DOEPINT13_SETUP_MASK              0x8
-#define GC_USB_DOEPINT13_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT13_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT13_SETUP_OFFSET            0xca8
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET      0xca8
-#define GC_USB_DOEPINT13_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT13_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET      0xca8
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET   0xca8
-#define GC_USB_DOEPINT13_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT13_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT13_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BNAINTR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BBLEERR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET        0xca8
-#define GC_USB_DOEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET       0xca8
-#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET      0xca8
-#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET        0xcb0
-#define GC_USB_DOEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET          0xcb0
-#define GC_USB_DOEPTSIZ13_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ13_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ13_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET          0xcb0
-#define GC_USB_DOEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA13_DMAADDR_OFFSET          0xcb4
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET   0xcbc
-#define GC_USB_DOEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_MPS_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_USBACTEP_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_DPID_LSB                0x10
-#define GC_USB_DOEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_DPID_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_NAKSTS_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_EPTYPE_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL14_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL14_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL14_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_SNP_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_STALL_LSB               0x15
-#define GC_USB_DOEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_STALL_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_CNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_SNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD0PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD1PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPDIS_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPENA_OFFSET            0xcc0
-#define GC_USB_DOEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT14_EPDISBLD_OFFSET         0xcc8
-#define GC_USB_DOEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT14_AHBERR_OFFSET           0xcc8
-#define GC_USB_DOEPINT14_SETUP_LSB               0x3
-#define GC_USB_DOEPINT14_SETUP_MASK              0x8
-#define GC_USB_DOEPINT14_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT14_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT14_SETUP_OFFSET            0xcc8
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT14_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET   0xcc8
-#define GC_USB_DOEPINT14_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT14_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT14_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BNAINTR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BBLEERR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET       0xcc8
-#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET      0xcc8
-#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET        0xcd0
-#define GC_USB_DOEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET          0xcd0
-#define GC_USB_DOEPTSIZ14_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ14_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ14_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET          0xcd0
-#define GC_USB_DOEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA14_DMAADDR_OFFSET          0xcd4
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET   0xcdc
-#define GC_USB_DOEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_MPS_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_USBACTEP_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_DPID_LSB                0x10
-#define GC_USB_DOEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_DPID_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_NAKSTS_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_EPTYPE_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL15_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL15_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL15_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_SNP_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_STALL_LSB               0x15
-#define GC_USB_DOEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_STALL_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_CNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_SNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD0PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD1PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPDIS_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPENA_OFFSET            0xce0
-#define GC_USB_DOEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET        0xce8
-#define GC_USB_DOEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT15_EPDISBLD_OFFSET         0xce8
-#define GC_USB_DOEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT15_AHBERR_OFFSET           0xce8
-#define GC_USB_DOEPINT15_SETUP_LSB               0x3
-#define GC_USB_DOEPINT15_SETUP_MASK              0x8
-#define GC_USB_DOEPINT15_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT15_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT15_SETUP_OFFSET            0xce8
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET      0xce8
-#define GC_USB_DOEPINT15_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT15_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET      0xce8
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET   0xce8
-#define GC_USB_DOEPINT15_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT15_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT15_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BNAINTR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BBLEERR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET        0xce8
-#define GC_USB_DOEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET       0xce8
-#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET      0xce8
-#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET        0xcf0
-#define GC_USB_DOEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET          0xcf0
-#define GC_USB_DOEPTSIZ15_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ15_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ15_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET          0xcf0
-#define GC_USB_DOEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA15_DMAADDR_OFFSET          0xcf4
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET   0xcfc
-#define GC_USB_PCGCCTL_STOPPCLK_LSB              0x0
-#define GC_USB_PCGCCTL_STOPPCLK_MASK             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_STOPPCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_GATEHCLK_LSB              0x1
-#define GC_USB_PCGCCTL_GATEHCLK_MASK             0x2
-#define GC_USB_PCGCCTL_GATEHCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_GATEHCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_PWRCLMP_LSB               0x2
-#define GC_USB_PCGCCTL_PWRCLMP_MASK              0x4
-#define GC_USB_PCGCCTL_PWRCLMP_SIZE              0x1
-#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT           0x0
-#define GC_USB_PCGCCTL_PWRCLMP_OFFSET            0xe00
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB         0x3
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK        0x8
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE        0x1
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT     0x0
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET      0xe00
-#define GC_USB_PCGCCTL_PHYSLEEP_LSB              0x6
-#define GC_USB_PCGCCTL_PHYSLEEP_MASK             0x40
-#define GC_USB_PCGCCTL_PHYSLEEP_SIZE             0x1
-#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT          0x0
-#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET           0xe00
-#define GC_USB_PCGCCTL_L1SUSPENDED_LSB           0x7
-#define GC_USB_PCGCCTL_L1SUSPENDED_MASK          0x80
-#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE          0x1
-#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT       0x0
-#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET        0xe00
-#define GC_USB_DFIFO_SIZE                        0x1000
-
-
-#endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */
diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c
deleted file mode 100644
index 2f20d88dda..0000000000
--- a/chip/stm32/usb_dwc_stream.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "timer.h"
-#include "usb_dwc_stream.h"
-#include "util.h"
-
-#include "console.h"
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-int rx_stream_handler(struct usb_stream_config const *config)
-{
-	int rx_count = rx_ep_pending(config->endpoint);
-
-	/* If we have some, try to shove them into the queue */
-	if (rx_count) {
-		size_t added = QUEUE_ADD_UNITS(
-			config->producer.queue, config->rx_ram,
-			rx_count);
-		if (added != rx_count) {
-			CPRINTF("rx_stream_handler: failed ep%d "
-				"queue %d bytes, accepted %d\n",
-				config->endpoint, rx_count, added);
-		}
-	}
-
-	if (!rx_ep_is_active(config->endpoint))
-		usb_read_ep(config->endpoint, config->rx_size, config->rx_ram);
-
-	return rx_count;
-}
-
-/* Try to send some bytes to the host */
-int tx_stream_handler(struct usb_stream_config const *config)
-{
-	size_t count;
-
-	if (!*(config->is_reset))
-		return 0;
-	if (!tx_ep_is_ready(config->endpoint))
-		return 0;
-
-	count = QUEUE_REMOVE_UNITS(config->consumer.queue, config->tx_ram,
-				   config->tx_size);
-	if (count)
-		usb_write_ep(config->endpoint, count, config->tx_ram);
-
-	return count;
-}
-
-/* Reset stream */
-void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	epN_reset(config->endpoint);
-
-	*(config->is_reset) = 1;
-
-	/* Flush any queued data */
-	hook_call_deferred(config->deferred_tx, 0);
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-static void usb_read(struct producer const *producer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(producer, struct usb_stream_config, producer);
-
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-static void usb_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(consumer, struct usb_stream_config, consumer);
-
-	hook_call_deferred(config->deferred_tx, 0);
-}
-
-struct producer_ops const usb_stream_producer_ops = {
-	.read = usb_read,
-};
-
-struct consumer_ops const usb_stream_consumer_ops = {
-	.written = usb_written,
-};
diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h
deleted file mode 100644
index e46e7a929c..0000000000
--- a/chip/stm32/usb_dwc_stream.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_DWC_STREAM_H
-#define __CROS_EC_USB_DWC_STREAM_H
-
-/* USB STREAM driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "consumer.h"
-#include "hooks.h"
-#include "registers.h"
-#include "producer.h"
-#include "queue.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * Compile time Per-USB stream configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB stream.  This structure binds
- * together all information required to operate a USB stream.
- */
-struct usb_stream_config {
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-	struct dwc_usb_ep *ep;
-
-	int *is_reset;
-	int *overflow;
-
-	/*
-	 * Deferred function to call to handle USB and Queue request.
-	 */
-	const struct deferred_data *deferred_tx;
-	const struct deferred_data *deferred_rx;
-
-	int tx_size;
-	int rx_size;
-
-	uint8_t *tx_ram;
-	uint8_t *rx_ram;
-
-	struct consumer consumer;
-	struct producer producer;
-};
-
-/*
- * These function tables are defined by the USB Stream driver and are used to
- * initialize the consumer and producer in the usb_stream_config.
- */
-extern struct consumer_ops const usb_stream_consumer_ops;
-extern struct producer_ops const usb_stream_producer_ops;
-
-
-/*
- * Convenience macro for defining USB streams and their associated state and
- * buffers.
- *
- * NAME is used to construct the names of the packet RAM buffers, trampoline
- * functions, usb_stream_state struct, and usb_stream_config struct, the
- * latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * stream.
- *
- * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the
- * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields
- * respectively in the USB interface descriptor.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate
- * for the RX and TX packets respectively.  The valid values for these
- * parameters are dictated by the USB peripheral.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver
- * should write to and read from respectively.
- */
-
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE);
- * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE);
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];		\
-	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];		\
-	static int CONCAT2(NAME, _is_reset_);				\
-	static int CONCAT2(NAME, _overflow_);				\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	struct usb_stream_config const NAME = {				\
-		.endpoint     = ENDPOINT,				\
-		.is_reset     = &CONCAT2(NAME, _is_reset_),		\
-		.overflow     = &CONCAT2(NAME, _overflow_),		\
-		.deferred_tx  = &CONCAT2(NAME, _deferred_tx__data),	\
-		.deferred_rx  = &CONCAT2(NAME, _deferred_rx__data),	\
-		.tx_size      = TX_SIZE,				\
-		.rx_size      = RX_SIZE,				\
-		.tx_ram       = CONCAT2(NAME, _buf_tx_),		\
-		.rx_ram       = CONCAT2(NAME, _buf_rx_),		\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &usb_stream_consumer_ops,		\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &usb_stream_producer_ops,		\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ tx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ rx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_epN_tx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_epN_rx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {			\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_expected = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = CONCAT2(NAME, _buf_rx_),		\
-		.out_databuffer_max = RX_SIZE,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = CONCAT2(NAME, _buf_tx_),		\
-		.in_databuffer_max = TX_SIZE,				\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));
-
-/* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
-
-/*
- * Handle USB and Queue request in a deferred callback.
- */
-int rx_stream_handler(struct usb_stream_config const *config);
-int tx_stream_handler(struct usb_stream_config const *config);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB stream driver.
- */
-void usb_stream_tx(struct usb_stream_config const *config);
-void usb_stream_rx(struct usb_stream_config const *config);
-void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt);
-
-#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h
deleted file mode 100644
index 6d79f3aca9..0000000000
--- a/chip/stm32/usb_dwc_update.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_STM32_USB_DWC_UPDATE_H
-#define __CROS_EC_STM32_USB_DWC_UPDATE_H
-
-extern struct dwc_usb_ep usb_update_ep_ctl;
-
-#endif /* __CROS_EC_STM32_USB_DWC_UPDATE_H */
diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c
deleted file mode 100644
index 85952a1387..0000000000
--- a/chip/stm32/usb_endpoints.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB endpoints/interfaces callbacks declaration
- */
-
-#include <stdint.h>
-#include <stddef.h>
-#include "config.h"
-#include "common.h"
-#include "usb_hw.h"
-
-typedef void (*xfer_func)(void);
-typedef void (*evt_func) (enum usb_ep_event evt);
-
-#if defined(CHIP_FAMILY_STM32F4)
-#define iface_arguments struct usb_setup_packet *req
-#else
-#define iface_arguments usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx
-#endif
-typedef int (*iface_func)(iface_arguments);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#if PASS == 1
-void ep_undefined(void)
-{
-	return;
-}
-
-void ep_evt_undefined(enum usb_ep_event evt)
-{
-	return;
-}
-
-/* Undefined interface callbacks fail by returning non-zero*/
-int iface_undefined(iface_arguments)
-{
-	return 1;
-}
-
-#define table(type, name, x) x
-
-#define endpoint_tx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _tx(void);
-#define endpoint_rx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _rx(void);
-#define endpoint_evt(number) \
-	extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \
-		ep_ ## number ## _evt(enum usb_ep_event evt);
-#define interface(number) \
-	extern int __attribute__((used, weak, alias("iface_undefined"))) \
-		iface_ ## number ## _request(iface_arguments);
-
-#define null
-
-#endif /* PASS 1 */
-
-#if PASS == 2
-#undef table
-#undef endpoint_tx
-#undef endpoint_rx
-#undef endpoint_evt
-#undef interface
-#undef null
-
-/* align function pointers on a 32-bit boundary */
-#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x };
-#define null (void*)0
-
-#define ep_(num, suf) CONCAT3(ep_, num, suf)
-#define ep(num, suf) ep_(num, suf)
-
-#define endpoint_tx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx,
-#define endpoint_rx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx,
-#define endpoint_evt(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt,
-#define interface(number) \
-	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request,
-#endif /* PASS 2 */
-
-/*
- * The initializers are listed backwards, but that's so that the items beyond
- * the chip's limit are first assigned to the last field, then overwritten by
- * its actual value due to the designated initializers in the macros above.
- * It all sorts out nicely
- */
-table(xfer_func, usb_ep_tx,
-	endpoint_tx(15)
-	endpoint_tx(14)
-	endpoint_tx(13)
-	endpoint_tx(12)
-	endpoint_tx(11)
-	endpoint_tx(10)
-	endpoint_tx(9)
-	endpoint_tx(8)
-	endpoint_tx(7)
-	endpoint_tx(6)
-	endpoint_tx(5)
-	endpoint_tx(4)
-	endpoint_tx(3)
-	endpoint_tx(2)
-	endpoint_tx(1)
-	endpoint_tx(0)
-)
-
-table(xfer_func, usb_ep_rx,
-	endpoint_rx(15)
-	endpoint_rx(14)
-	endpoint_rx(13)
-	endpoint_rx(12)
-	endpoint_rx(11)
-	endpoint_rx(10)
-	endpoint_rx(9)
-	endpoint_rx(8)
-	endpoint_rx(7)
-	endpoint_rx(6)
-	endpoint_rx(5)
-	endpoint_rx(4)
-	endpoint_rx(3)
-	endpoint_rx(2)
-	endpoint_rx(1)
-	endpoint_rx(0)
-)
-
-table(evt_func, usb_ep_event,
-	endpoint_evt(15)
-	endpoint_evt(14)
-	endpoint_evt(13)
-	endpoint_evt(12)
-	endpoint_evt(11)
-	endpoint_evt(10)
-	endpoint_evt(9)
-	endpoint_evt(8)
-	endpoint_evt(7)
-	endpoint_evt(6)
-	endpoint_evt(5)
-	endpoint_evt(4)
-	endpoint_evt(3)
-	endpoint_evt(2)
-	endpoint_evt(1)
-	endpoint_evt(0)
-)
-
-#if USB_IFACE_COUNT > 0
-table(iface_func, usb_iface_request,
-	interface(7)
-	interface(6)
-	interface(5)
-	interface(4)
-	interface(3)
-	interface(2)
-	interface(1)
-	interface(0)
-)
-#endif
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "usb_endpoints.c"
-#endif
diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c
deleted file mode 100644
index 64d46875b5..0000000000
--- a/chip/stm32/usb_gpio.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "usb_gpio.h"
-
-void usb_gpio_tx(struct usb_gpio_config const *config)
-{
-	size_t   i;
-	uint32_t mask  = 1;
-	uint32_t value = 0;
-
-	for (i = 0; i < config->num_gpios; ++i, mask <<= 1)
-		value |= (gpio_get_level(config->gpios[i])) ? mask : 0;
-
-	config->tx_ram[0] = value;
-	config->tx_ram[1] = value >> 16;
-
-	btable_ep[config->endpoint].tx_count = USB_GPIO_TX_PACKET_SIZE;
-
-	/*
-	 * TX packet updated, mark the packet as VALID.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-void usb_gpio_rx(struct usb_gpio_config const *config)
-{
-	size_t   i;
-	uint32_t mask        = 1;
-	uint32_t set_mask    = ((uint32_t)(config->rx_ram[0]) |
-			        (uint32_t)(config->rx_ram[1]) << 16);
-	uint32_t clear_mask  = ((uint32_t)(config->rx_ram[2]) |
-			        (uint32_t)(config->rx_ram[3]) << 16);
-	uint32_t ignore_mask = set_mask & clear_mask;
-
-	config->state->set_mask = set_mask;
-	config->state->clear_mask = clear_mask;
-
-	if ((btable_ep[config->endpoint].rx_count & RX_COUNT_MASK) ==
-	    USB_GPIO_RX_PACKET_SIZE) {
-		for (i = 0; i < config->num_gpios; ++i, mask <<= 1) {
-			if (ignore_mask & mask)
-				;
-			else if (set_mask & mask)
-				gpio_set_level(config->gpios[i], 1);
-			else if (clear_mask & mask)
-				gpio_set_level(config->gpios[i], 0);
-		}
-	}
-
-	/*
-	 * RX packet consumed, mark the packet as VALID.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
-{
-	int i;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	i = config->endpoint;
-
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
-	btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE;
-
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
-	btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10);
-
-	/*
-	 * Initialize TX buffer with zero, the first IN transaction will fill
-	 * this in with a valid value.
-	 */
-	config->tx_ram[0] = 0;
-	config->tx_ram[1] = 0;
-
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (3 <<  4) | /* TX Valid */
-			   (0 <<  9) | /* Bulk EP */
-			   (3 << 12)); /* RX Valid */
-}
diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h
deleted file mode 100644
index b27c7f9485..0000000000
--- a/chip/stm32/usb_gpio.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_GPIO_H
-#define __CROS_EC_USB_GPIO_H
-
-/* STM32 USB GPIO driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-struct usb_gpio_state {
-	uint32_t set_mask;
-	uint32_t clear_mask;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_gpio_config {
-	struct usb_gpio_state *state;
-
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	int endpoint;
-
-	usb_uint *rx_ram;
-	usb_uint *tx_ram;
-
-	/*
-	 * GPIO list
-	 */
-	enum gpio_signal const *gpios;
-	size_t num_gpios;
-};
-
-#define USB_GPIO_RX_PACKET_SIZE 8
-#define USB_GPIO_TX_PACKET_SIZE 4
-
-/*
- * Convenience macro for defining a USB GPIO driver and its associated state.
- *
- * NAME is used to construct the names of the trampoline functions,
- * usb_gpio_state struct, and usb_gpio_config struct, the latter is just
- * called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * GPIO driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- */
-#define USB_GPIO_CONFIG(NAME,						\
-			GPIO_LIST,					\
-			INTERFACE,					\
-			ENDPOINT)					\
-	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);			\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;	\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;	\
-	struct usb_gpio_config const NAME = {				\
-		.state     = &((struct usb_gpio_state){}),		\
-		.endpoint  = ENDPOINT,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.gpios     = GPIO_LIST,					\
-		.num_gpios = ARRAY_SIZE(GPIO_LIST),			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = 0,				\
-		.bInterfaceProtocol = 0,				\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_GPIO_TX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_GPIO_RX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_gpio_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_gpio_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_gpio_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event))
-
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_gpio_tx(struct usb_gpio_config const *config);
-void usb_gpio_rx(struct usb_gpio_config const *config);
-void usb_gpio_event(struct usb_gpio_config const *config,
-		    enum usb_ep_event evt);
-
-#endif /* __CROS_EC_USB_GPIO_H */
diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c
deleted file mode 100644
index b8336fa0a0..0000000000
--- a/chip/stm32/usb_hid.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-void hid_tx(int ep)
-{
-	/* clear IT */
-	STM32_USB_EP(ep) = (STM32_USB_EP(ep) & EP_MASK);
-}
-
-void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
-	       usb_uint *hid_ep_rx_buf, int rx_len)
-{
-	int i;
-	uint16_t ep_reg;
-
-	btable_ep[ep].tx_addr = usb_sram_addr(hid_ep_tx_buf);
-	btable_ep[ep].tx_count = tx_len;
-
-	/* STM32 USB SRAM needs to be accessed one U16 at a time */
-	for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++)
-		hid_ep_tx_buf[i] = 0;
-
-	ep_reg = (ep << 0) /* Endpoint Address */ |
-		EP_TX_VALID |
-		(3 << 9) /* interrupt EP */ |
-		EP_RX_DISAB;
-
-	/* Enable RX for output reports */
-	if (hid_ep_rx_buf && rx_len > 0) {
-		btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf);
-		btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10;
-
-		ep_reg |= EP_RX_VALID;  /* RX Valid */
-	}
-
-	STM32_USB_EP(ep) = ep_reg;
-}
-
-/*
- * Keep track of state in case we need to be called multiple times,
- * if the report length is bigger than 64 bytes.
- */
-static int report_left;
-static const uint8_t *report_ptr;
-
-/*
- * Send report through ep0_buf_tx.
- *
- * If report size is greater than USB packet size (64 bytes), rest of the
- * reports will be saved in `report_ptr` and `report_left`, so we can call this
- * function again to send the remain parts.
- *
- * @return 0 if entire report is sent, 1 if there are remaining data.
- */
-static int send_report(usb_uint *ep0_buf_tx,
-		       const uint8_t *report,
-		       int report_size)
-{
-	int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE);
-
-	memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-			 report, packet_size);
-	btable_ep[0].tx_count = packet_size;
-	/* report_left != 0 if report doesn't fit in 1 packet. */
-	report_left = report_size - packet_size;
-	report_ptr = report + packet_size;
-
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			report_left ? 0 : EP_STATUS_OUT);
-
-	return report_left ? 1 : 0;
-}
-
-int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
-		      const struct usb_hid_config_t *config)
-{
-	const uint8_t *report_desc = config->report_desc;
-	int report_size = config->report_size;
-	const struct usb_hid_descriptor *hid_desc = config->hid_desc;
-
-	if (!ep0_buf_rx) {
-		/*
-		 * Continue previous transfer. We ignore report_desc/size here,
-		 * which is fine as only one GET_DESCRIPTOR command comes at a
-		 * time.
-		 */
-		if (report_left == 0)
-			return -1;
-		report_size = MIN(USB_MAX_PACKET_SIZE, report_left);
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 report_ptr, report_size);
-		btable_ep[0].tx_count = report_size;
-		report_left -= report_size;
-		report_ptr += report_size;
-		STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID,
-				report_left ? 0 : EP_STATUS_OUT);
-		return report_left ? 1 : 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE |
-					(USB_REQ_GET_DESCRIPTOR << 8))) {
-		if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) {
-			/* Setup : HID specific : Get Report descriptor */
-			return send_report(ep0_buf_tx, report_desc,
-					   MIN(ep0_buf_rx[3], report_size));
-		} else if (ep0_buf_rx[1] == (USB_HID_DT_HID << 8)) {
-			/* Setup : HID specific : Get HID descriptor */
-			memcpy_to_usbram_ep0_patch(hid_desc, sizeof(*hid_desc));
-			btable_ep[0].tx_count = sizeof(*hid_desc);
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-					EP_STATUS_OUT);
-			return 0;
-		}
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN |
-				     USB_RECIP_INTERFACE |
-				     USB_TYPE_CLASS |
-				     (USB_HID_REQ_GET_REPORT << 8))) {
-		const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF;
-		const uint8_t report_id = ep0_buf_rx[1] & 0xFF;
-		int retval;
-
-		report_left = ep0_buf_rx[3];
-		if (!config->get_report) /* not supported */
-			return -1;
-
-		retval = config->get_report(report_id,
-					    report_type,
-					    &report_ptr,
-					    &report_left);
-		if (retval)
-			return retval;
-
-		return send_report(ep0_buf_tx, report_ptr, report_left);
-	}
-
-	return -1;
-}
diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h
deleted file mode 100644
index a36a66567e..0000000000
--- a/chip/stm32/usb_hid_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB HID HW definitions, to be used by class drivers.
- */
-
-#ifndef __CROS_EC_USB_HID_HW_H
-#define __CROS_EC_USB_HID_HW_H
-
-#include <common.h>
-
-struct usb_hid_config_t {
-	const uint8_t *report_desc;
-	int report_size;
-	const struct usb_hid_descriptor *hid_desc;
-
-	/*
-	 * Handle USB HID Get_Report request, can be NULL if not supported.
-	 *
-	 * @param report_id: ID of the report being requested
-	 * @param report_type: 0x1 (INPUT) / 0x2 (OUTPUT) / 0x3 (FEATURE)
-	 * @param buffer_ptr: handler should set it to the pointer of buffer to
-	 *     return.
-	 * @param buffer_size: handler should set it to the size of returned
-	 *     buffer.
-	 */
-	int (*get_report)(uint8_t report_id,
-			  uint8_t report_type,
-			  const uint8_t **buffer_ptr,
-			  int *buffer_size);
-};
-
-/* internal callbacks for HID class drivers */
-void hid_tx(int ep);
-void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
-	       usb_uint *hid_ep_rx_buf, int rx_len);
-int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
-		      const struct usb_hid_config_t *hid_config);
-
-#endif
diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c
deleted file mode 100644
index e2a8d675e9..0000000000
--- a/chip/stm32/usb_hid_keyboard.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "link_defs.h"
-#include "pwm.h"
-#include "queue.h"
-#include "registers.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-static const int keyboard_debug;
-
-struct key_event {
-	uint32_t time;
-	uint8_t keycode;
-	uint8_t pressed;
-};
-
-static struct queue const key_queue = QUEUE_NULL(16, struct key_event);
-static struct mutex key_queue_mutex;
-
-enum hid_protocol {
-	HID_BOOT_PROTOCOL = 0,
-	HID_REPORT_PROTOCOL = 1,
-	HID_PROTOCOL_COUNT = 2,
-};
-
-/* Current protocol, behaviour is identical in both modes. */
-static enum hid_protocol protocol = HID_REPORT_PROTOCOL;
-
-#if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \
-    defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
-#define HID_KEYBOARD_EXTRA_FIELD
-#endif
-
-/*
- * Note: This first 8 bytes of this report format cannot be changed, as that
- * would break HID Boot protocol compatibility (see HID 1.11 "Appendix B: Boot
- * Interface Descriptors").
- */
-struct usb_hid_keyboard_report {
-	uint8_t modifiers; /* bitmap of modifiers 224-231 */
-	uint8_t reserved; /* 0x0 */
-	uint8_t keys[6];
-	/* Non-boot protocol fields below */
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-	/* Assistant/tablet mode switch bitmask */
-	uint8_t extra;
-#endif
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	uint32_t top_row; /* bitmap of top row action keys */
-#endif
-} __packed;
-
-struct usb_hid_keyboard_output_report {
-	uint8_t brightness;
-} __packed;
-
-#define HID_KEYBOARD_BOOT_SIZE 8
-
-#define HID_KEYBOARD_REPORT_SIZE sizeof(struct usb_hid_keyboard_report)
-#define HID_KEYBOARD_OUTPUT_REPORT_SIZE \
-	sizeof(struct usb_hid_keyboard_output_report)
-
-#define HID_KEYBOARD_EP_INTERVAL_MS 16 /* ms */
-
-/*
- * Coalesce events happening within some interval. The value must be greater
- * than EP interval to ensure we cannot have a backlog of keys.
- * It must also be short enough to ensure that the intended order of key presses
- * is passed to AP, and that we do not coalesce press and release events (which
- * would result in lost keys).
- */
-#define COALESCE_INTERVAL (18 * MSEC)
-
-/*
- * Discard key events in the FIFO buffer that are older than this amount of
- * time. Note that we do not fully drop them, we still update the report,
- * but we do not send the events individually anymore (so an old key press
- * and release will be dropped altogether, but a single press/release will
- * still be reported correctly).
- */
-#define KEY_DISCARD_MAX_TIME (1 * SECOND)
-
-/* Modifiers keycode range */
-#define HID_KEYBOARD_MODIFIER_LOW 0xe0
-#define HID_KEYBOARD_MODIFIER_HIGH 0xe7
-
-/* Supported function key range */
-#define HID_F1 0x3a
-#define HID_F12 0x45
-#define HID_F13 0x68
-#define HID_F15 0x6a
-
-/* Special keys/switches */
-#define HID_KEYBOARD_EXTRA_LOW 0xf0
-#define HID_KEYBOARD_ASSISTANT_KEY 0xf0
-#define HID_KEYBOARD_TABLET_MODE_SWITCH 0xf1
-#define HID_KEYBOARD_EXTRA_HIGH 0xf1
-
-/* The standard Chrome OS keyboard matrix table. See HUT 1.12v2 Table 12 and
- * https://www.w3.org/TR/DOM-Level-3-Events-code .
- *
- * Assistant key is mapped as 0xf0, but this key code is never actually send.
- */
-const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00},
-	{0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14},
-	{0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08},
-	{0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15},
-	{0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a},
-	{0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c},
-	{0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18},
-	{0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5},
-	{0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13},
-	{0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12},
-	{0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00},
-	{0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52},
-	{0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50},
-};
-
-/* HID descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_KEYBOARD) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_HID_KEYBOARD,
-	.bAlternateSetting = 0,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	.bNumEndpoints = 2,
-#else
-	.bNumEndpoints = 1,
-#endif
-	.bInterfaceClass = USB_CLASS_HID,
-	.bInterfaceSubClass = USB_HID_SUBCLASS_BOOT,
-	.bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD,
-	.iInterface = 0,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_KEYBOARD_REPORT_SIZE,
-	.bInterval = HID_KEYBOARD_EP_INTERVAL_MS /* ms polling interval */
-};
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = USB_EP_HID_KEYBOARD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_KEYBOARD_OUTPUT_REPORT_SIZE,
-	.bInterval = HID_KEYBOARD_EP_INTERVAL_MS
-};
-#endif
-
-#define KEYBOARD_BASE_DESC						\
-	0x05, 0x01, /* Usage Page (Generic Desktop) */			\
-	0x09, 0x06, /* Usage (Keyboard) */				\
-	0xA1, 0x01, /* Collection (Application) */			\
-									\
-	/* Modifiers */							\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */		\
-	0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */		\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x08, /* Report Count (8) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x81, 0x01, /* Input (Constant), ;Reserved byte */		\
-									\
-	/* Normal keys */						\
-	0x95, 0x06, /* Report Count (6) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0xa4, /* Logical Maximum (164) */				\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, 0x00, /* Usage Minimum (0) */				\
-	0x29, 0xa4, /* Usage Maximum (164) */				\
-	0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
-
-#define KEYBOARD_TOP_ROW_DESC						\
-	/* Modifiers */							\
-	0x05, 0x0C, /* Consumer Page */					\
-	0x0A, 0x24, 0x02, /* AC Back (0x224) */				\
-	0x0A, 0x25, 0x02, /* AC Forward (0x225) */			\
-	0x0A, 0x27, 0x02, /* AC Refresh (0x227) */			\
-	0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */			\
-	0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */	\
-	0x09, 0x70,       /* Display Brightness Decrement (0x70) */	\
-	0x09, 0x6F,       /* Display Brightness Increment (0x6F) */	\
-	0x09, 0xE2,       /* Mute (0xE2) */				\
-	0x09, 0xEA,       /* Volume Decrement (0xEA) */			\
-	0x09, 0xE9,       /* Volume Increment (0xE9) */			\
-	0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \
-	0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */		\
-	0x09, 0x7A,       /* Keyboard Brightness Decrement (0x7A) */	\
-	0x09, 0x79,       /* Keyboard Brightness Increment (0x79)*/	\
-	0x09, 0xCD,       /* Play / Pause (0xCD) */			\
-	0x09, 0xB5,       /* Scan Next Track (0xB5) */			\
-	0x09, 0xB6,       /* Scan Previous Track (0xB6) */		\
-	0x09, 0x7C,       /* Keyboard Backlight OOC (0x7C) */ \
-	0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \
-	0x09, 0x32,       /* Sleep (0x32) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x14, /* Report Count (20) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	/* 12-bit padding */						\
-	0x95, 0x0C, /* Report Count (12) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-
-#define KEYBOARD_TOP_ROW_FEATURE_DESC					\
-	0x06, 0xd1, 0xff, /* Usage Page (Google) */			\
-	0x09, 0x01,       /* Usage (Top Row List) */			\
-	0xa1, 0x02,       /* Collection (Logical) */			\
-	0x05, 0x0a,       /*   Usage Page (Ordinal) */			\
-	0x19, 0x01,       /*   Usage Minimum (1) */			\
-	0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */	\
-	0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */	\
-	0x75, 0x20,       /*   Report Size (32) */			\
-	0xb1, 0x03,       /*   Feature (Cnst,Var,Abs) */		\
-	0xc0,             /* End Collection */
-
-/*
- * Vendor-defined Usage Page 0xffd1:
- *  - 0x18: Assistant key
- *  - 0x19: Tablet mode switch
- */
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-#ifdef CONFIG_KEYBOARD_ASSISTANT_KEY
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x19, 0x18, /* Usage Minimum */					\
-	0x29, 0x18, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
-#else
-/* No assistant key: just pad 1 bit. */
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-#endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */
-
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x19, 0x19, /* Usage Minimum */					\
-	0x29, 0x19, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
-#else
-/* No tablet mode swtch: just pad 1 bit. */
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-#endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */
-
-#define KEYBOARD_VENDOR_DESC						\
-	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */	\
-									\
-	KEYBOARD_ASSISTANT_KEY_DESC					\
-	KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x06, /* Report Size (6) */				\
-	0x81, 0x01, /* Input (Constant), ;6-bit padding */
-#endif /* HID_KEYBOARD_EXTRA_FIELD */
-
-#define KEYBOARD_BACKLIGHT_DESC \
-	0xA1, 0x02, /* Collection (Logical) */				\
-	0x05, 0x14, /*   Usage Page (Alphanumeric Display) */		\
-	0x09, 0x46, /*   Usage (Display Brightness) */			\
-	0x95, 0x01, /*   Report Count (1) */				\
-	0x75, 0x08, /*   Report Size (8) */				\
-	0x15, 0x00, /*   Logical Minimum (0) */				\
-	0x25, 0x64, /*   Logical Maximum (100) */			\
-	0x91, 0x02, /*   Output (Data, Variable, Absolute) */		\
-	0xC0,       /* End Collection */
-
-/*
- * To allow dynamic detection of keyboard backlights, we define two descriptors.
- * One has keyboard backlight, and the other one does not.
- */
-
-/* HID : Report Descriptor */
-static const uint8_t report_desc[] = {
-
-	KEYBOARD_BASE_DESC
-
-#ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
-#endif
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
-#endif
-	0xC0        /* End Collection */
-};
-
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-
-/* HID : Report Descriptor with keyboard backlight */
-static const uint8_t report_desc_with_backlight[] = {
-
-	KEYBOARD_BASE_DESC
-
-#ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
-#endif
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
-#endif
-	KEYBOARD_BACKLIGHT_DESC
-
-	0xC0        /* End Collection */
-};
-
-#endif
-
-/* HID: HID Descriptor */
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD,
-						hid, hid_desc_kb) = {
-	.bLength = 9,
-	.bDescriptorType = USB_HID_DT_HID,
-	.bcdHID = 0x0100,
-	.bCountryCode = 0x00, /* Hardware target country */
-	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
-};
-
-#define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2)
-
-static usb_uint hid_ep_tx_buf[EP_TX_BUF_SIZE] __usb_ram;
-static volatile int hid_current_buf;
-
-static volatile int hid_ep_data_ready;
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-#define EP_RX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_OUTPUT_REPORT_SIZE, 2)
-static usb_uint hid_ep_rx_buf[EP_RX_BUF_SIZE] __usb_ram;
-#endif
-
-static struct usb_hid_keyboard_report report;
-
-static void keyboard_process_queue(void);
-DECLARE_DEFERRED(keyboard_process_queue);
-
-static void write_keyboard_report(void)
-{
-	/* Tell the interrupt handler to send the next buffer. */
-	hid_ep_data_ready = 1;
-	if ((STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == EP_TX_VALID) {
-		/* Endpoint is busy */
-		return;
-	}
-
-	if (atomic_clear((int *)&hid_ep_data_ready)) {
-		/*
-		 * Endpoint is not busy, and interrupt handler did not just
-		 * send the buffer: enable TX.
-		 */
-
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-	}
-
-	/*
-	 * Wake the host. This is required to prevent a race between EP getting
-	 * reloaded and host suspending the device, as, ideally, we never want
-	 * to have EP loaded during suspend, to avoid reporting stale data.
-	 */
-	usb_wake();
-}
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-
-static void hid_keyboard_rx(void)
-{
-	struct usb_hid_keyboard_output_report report;
-	memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf),
-			   HID_KEYBOARD_OUTPUT_REPORT_SIZE);
-
-	CPRINTF("Keyboard backlight set to %d%%\n", report.brightness);
-
-	pwm_enable(PWM_CH_KBLIGHT, report.brightness > 0);
-	pwm_set_duty(PWM_CH_KBLIGHT, report.brightness);
-
-	STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-}
-
-#endif
-
-static void hid_keyboard_tx(void)
-{
-	hid_tx(USB_EP_HID_KEYBOARD);
-	if (hid_ep_data_ready) {
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-		hid_ep_data_ready = 0;
-	}
-
-	if (queue_count(&key_queue) > 0)
-		hook_call_deferred(&keyboard_process_queue_data, 0);
-}
-
-static void hid_keyboard_event(enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET) {
-		protocol = HID_REPORT_PROTOCOL;
-
-		hid_reset(USB_EP_HID_KEYBOARD,
-			  hid_ep_tx_buf,
-			  HID_KEYBOARD_REPORT_SIZE,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-			  hid_ep_rx_buf,
-			  HID_KEYBOARD_OUTPUT_REPORT_SIZE
-#else
-			  NULL, 0
-#endif
-			  );
-
-		/*
-		 * Reload endpoint on reset, to make sure we report accurate
-		 * state to host (this is especially important for tablet mode
-		 * switch).
-		 */
-		write_keyboard_report();
-		return;
-	}
-
-	if (evt == USB_EVENT_DEVICE_RESUME && queue_count(&key_queue) > 0)
-		hook_call_deferred(&keyboard_process_queue_data, 0);
-}
-
-USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_keyboard_tx,
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	       hid_keyboard_rx,
-#else
-	       hid_keyboard_tx,
-#endif
-	       hid_keyboard_event);
-
-struct action_key_config {
-	uint32_t mask; /* bit position of usb_hid_keyboard_report.top_row */
-	uint32_t usage; /*usage ID */
-};
-
-static const struct action_key_config action_key[] = {
-	[TK_BACK] = { .mask = BIT(0), .usage = 0x000C0224 },
-	[TK_FORWARD] = { .mask = BIT(1), .usage = 0x000C0225 },
-	[TK_REFRESH] = { .mask = BIT(2), .usage = 0x000C0227 },
-	[TK_FULLSCREEN] = { .mask = BIT(3), .usage = 0x000C0232 },
-	[TK_OVERVIEW] = { .mask = BIT(4), .usage = 0x000C029F },
-	[TK_BRIGHTNESS_DOWN] = { .mask = BIT(5), .usage = 0x000C0070 },
-	[TK_BRIGHTNESS_UP] = { .mask = BIT(6), .usage = 0x000C006F },
-	[TK_VOL_MUTE] = { .mask = BIT(7), .usage = 0x000C00E2 },
-	[TK_VOL_DOWN] = { .mask = BIT(8), .usage = 0x000C00EA },
-	[TK_VOL_UP] = { .mask = BIT(9), .usage = 0x000C00E9 },
-	[TK_SNAPSHOT] = { .mask = BIT(10), .usage = 0x00070046 },
-	[TK_PRIVACY_SCRN_TOGGLE] = { .mask = BIT(11), .usage = 0x000C02D0 },
-	[TK_KBD_BKLIGHT_DOWN] = { .mask = BIT(12), .usage = 0x000C007A },
-	[TK_KBD_BKLIGHT_UP] = { .mask = BIT(13), .usage = 0x000C0079 },
-	[TK_PLAY_PAUSE] = { .mask = BIT(14), .usage = 0x000C00CD },
-	[TK_NEXT_TRACK] = { .mask = BIT(15), .usage = 0x000C00B5 },
-	[TK_PREV_TRACK] = { .mask = BIT(16), .usage = 0x000C00B6 },
-	[TK_KBD_BKLIGHT_TOGGLE] = { .mask = BIT(17), .usage = 0x000C007C },
-	[TK_MICMUTE] = { .mask = BIT(18), .usage = 0x000B002F },
-};
-
-/* TK_* is 1-indexed, so the next bit is at ARRAY_SIZE(action_key) - 1 */
-static const int SLEEP_KEY_MASK = BIT(ARRAY_SIZE(action_key) - 1);
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-static uint32_t feature_report[CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS];
-
-static void hid_keyboard_feature_init(void)
-{
-	const struct ec_response_keybd_config *config =
-		board_vivaldi_keybd_config();
-
-	for (int i = 0; i < CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS; i++) {
-		int key = config->action_keys[i];
-
-		if (IN_RANGE(key, 0, ARRAY_SIZE(action_key)))
-			feature_report[i] = action_key[key].usage;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, hid_keyboard_feature_init, HOOK_PRIO_DEFAULT - 1);
-#endif
-
-static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type,
-				   const uint8_t **buffer_ptr, int *buffer_size)
-{
-	if (report_type == REPORT_TYPE_INPUT) {
-		*buffer_ptr = (uint8_t *)&report;
-		*buffer_size = sizeof(report);
-		return 0;
-	}
-
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	if (report_type == REPORT_TYPE_FEATURE) {
-		*buffer_ptr = (uint8_t *)feature_report;
-		*buffer_size = (sizeof(uint32_t) *
-				CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS);
-		return 0;
-	}
-#endif
-
-	return -1;
-}
-
-static struct usb_hid_config_t hid_config_kb = {
-	.report_desc = report_desc,
-	.report_size = sizeof(report_desc),
-	.hid_desc = &hid_desc_kb,
-	.get_report = &hid_keyboard_get_report,
-};
-
-static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
-				      usb_uint *ep0_buf_tx)
-{
-	int ret;
-
-	ret = hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_kb);
-	if (ret >= 0)
-		return ret;
-
-	if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) {
-		uint16_t value = ep0_buf_rx[1];
-
-		if (value >= HID_PROTOCOL_COUNT)
-			return -1;
-
-		protocol = value;
-
-		/* Reload endpoint with appropriate tx_count. */
-		btable_ep[USB_EP_HID_KEYBOARD].tx_count =
-			(protocol == HID_BOOT_PROTOCOL) ?
-			HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE;
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
-
-		btable_ep[0].tx_count = 0;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		return 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) {
-		uint8_t value = protocol;
-
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 &value, sizeof(value));
-		btable_ep[0].tx_count = 1;
-		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		return 0;
-	}
-
-	return -1;
-}
-USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_keyboard_iface_request)
-
-void keyboard_clear_buffer(void)
-{
-	mutex_lock(&key_queue_mutex);
-	queue_init(&key_queue);
-	mutex_unlock(&key_queue_mutex);
-
-	memset(&report, 0, sizeof(report));
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-	if (tablet_get_mode())
-		report.extra |= 0x01 <<	(HID_KEYBOARD_TABLET_MODE_SWITCH -
-					 HID_KEYBOARD_EXTRA_LOW);
-#endif
-	write_keyboard_report();
-}
-
-/*
- * Convert a function key to the bit mask of corresponding action key.
- *
- * Return 0 if no need to map (not a function key or vivaldi not enabled)
- */
-static uint32_t maybe_convert_function_key(int keycode)
-{
-	const struct ec_response_keybd_config *config =
-		board_vivaldi_keybd_config();
-	/* zero-based function key index (e.g. F1 -> 0) */
-	int index;
-
-	if (!IS_ENABLED(CONFIG_USB_HID_KEYBOARD_VIVALDI) || !config)
-		return 0;
-
-	if (IN_RANGE(keycode, HID_F1, HID_F12 + 1))
-		index = keycode - HID_F1;
-	else if (IN_RANGE(keycode, HID_F13, HID_F15 + 1))
-		index = keycode - HID_F13 + 12;
-	else
-		return 0; /* not a function key */
-
-	/* convert F13 to Sleep */
-	if (index == 12 && (config->capabilities & KEYBD_CAP_SCRNLOCK_KEY))
-		return SLEEP_KEY_MASK;
-
-	if (index >= config->num_top_row_keys ||
-			config->action_keys[index] == TK_ABSENT)
-		return 0; /* not mapped */
-	return action_key[config->action_keys[index]].mask;
-}
-
-static void keyboard_process_queue(void)
-{
-	int i;
-	uint8_t mask;
-	struct key_event ev;
-	int valid = 0;
-	int trimming = 0;
-	uint32_t now = __hw_clock_source_read();
-	uint32_t first_key_time;
-
-	if (keyboard_debug)
-		CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue),
-			usb_is_suspended(), hid_ep_data_ready,
-			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK)
-			== EP_TX_VALID);
-	mutex_lock(&key_queue_mutex);
-
-	if (queue_count(&key_queue) == 0) {
-		mutex_unlock(&key_queue_mutex);
-		return;
-	}
-
-	if (usb_is_suspended() || hid_ep_data_ready) {
-		usb_wake();
-
-		if (!queue_is_full(&key_queue)) {
-			/* Queue still has space, let's keep gathering keys. */
-			mutex_unlock(&key_queue_mutex);
-			return;
-		}
-
-		/*
-		 * Queue is full, so we continue, as the code below is
-		 * guaranteed to pop at least one key from the queue, but we do
-		 * not write the report at the end.
-		 */
-		CPRINTF("Trimming queue (%d %d %d)\n", queue_count(&key_queue),
-			usb_is_suspended(), hid_ep_data_ready);
-
-		trimming = 1;
-	}
-
-	/* There is at least one element in the queue. */
-	queue_peek_units(&key_queue, &ev, 0, 1);
-	first_key_time = ev.time;
-
-	/*
-	 * Pick key events from the queue, coalescing events older than events
-	 * within EP interval time to make sure the queue cannot grow, and
-	 * dropping keys that are too old.
-	 */
-	while (queue_count(&key_queue) > 0) {
-		uint32_t action_key_mask;
-
-		queue_peek_units(&key_queue, &ev, 0, 1);
-		if (keyboard_debug)
-			CPRINTF(" =%02x/%d %d %d\n", ev.keycode, ev.keycode,
-				ev.pressed, ev.time - now);
-
-		if ((now - ev.time) <= KEY_DISCARD_MAX_TIME &&
-		    (ev.time - first_key_time) >= COALESCE_INTERVAL)
-			break;
-
-		queue_advance_head(&key_queue, 1);
-
-		action_key_mask = maybe_convert_function_key(ev.keycode);
-		if (action_key_mask) {
-#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-			if (ev.pressed)
-				report.top_row |= action_key_mask;
-			else
-				report.top_row &= ~action_key_mask;
-			valid = 1;
-#endif
-		} else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW &&
-		    ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
-#ifdef HID_KEYBOARD_EXTRA_FIELD
-			mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW);
-			if (ev.pressed)
-				report.extra |= mask;
-			else
-				report.extra &= ~mask;
-			valid = 1;
-#endif
-		} else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW &&
-		    ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
-			mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW);
-			if (ev.pressed)
-				report.modifiers |= mask;
-			else
-				report.modifiers &= ~mask;
-			valid = 1;
-		} else if (ev.pressed) {
-			/*
-			 * Add keycode to the list of keys (does nothing if the
-			 * array is already full).
-			 */
-			for (i = 0; i < ARRAY_SIZE(report.keys); i++) {
-				/* Is key already pressed? */
-				if (report.keys[i] == ev.keycode)
-					break;
-				if (report.keys[i] == 0) {
-					report.keys[i] = ev.keycode;
-					valid = 1;
-					break;
-				}
-			}
-		} else {
-			/*
-			 * Remove keycode from the list of keys (does nothing
-			 * if the key is not in the array).
-			 */
-			for (i = 0; i < ARRAY_SIZE(report.keys); i++) {
-				if (report.keys[i] == ev.keycode) {
-					report.keys[i] = 0;
-					valid = 1;
-					break;
-				}
-			}
-		}
-	}
-
-	mutex_unlock(&key_queue_mutex);
-
-	if (valid && !trimming)
-		write_keyboard_report();
-}
-
-static void queue_keycode_event(uint8_t keycode, int is_pressed)
-{
-	struct key_event ev = {
-		.time = __hw_clock_source_read(),
-		.keycode = keycode,
-		.pressed = is_pressed,
-	};
-
-	mutex_lock(&key_queue_mutex);
-	queue_add_unit(&key_queue, &ev);
-	mutex_unlock(&key_queue_mutex);
-
-	keyboard_process_queue();
-}
-
-#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#include "console.h"
-
-static void tablet_mode_change(void)
-{
-	queue_keycode_event(HID_KEYBOARD_TABLET_MODE_SWITCH, tablet_get_mode());
-}
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT);
-/* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1);
-#endif
-
-void keyboard_state_changed(int row, int col, int is_pressed)
-{
-	uint8_t keycode = keycodes[col][row];
-
-	if (!keycode) {
-		CPRINTF("Unknown key at %d/%d\n", row, col);
-		return;
-	}
-
-	queue_keycode_event(keycode, is_pressed);
-}
-
-void clear_typematic_key(void)
-{ }
-
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-void usb_hid_keyboard_init(void)
-{
-	if (board_has_keyboard_backlight()) {
-		hid_config_kb.report_desc = report_desc_with_backlight;
-		hid_config_kb.report_size = sizeof(report_desc_with_backlight);
-
-		set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT,
-			&hid_desc_kb.desc[0].wDescriptorLength,
-			sizeof(report_desc_with_backlight));
-	}
-}
-/* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */
-DECLARE_HOOK(HOOK_INIT, usb_hid_keyboard_init, HOOK_PRIO_DEFAULT - 1);
-#endif
diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c
deleted file mode 100644
index 0ead660432..0000000000
--- a/chip/stm32/usb_hid_touchpad.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "link_defs.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_hid.h"
-#include "usb_hid_hw.h"
-#include "usb_hid_touchpad.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-static const int touchpad_debug;
-
-static struct queue const report_queue = QUEUE_NULL(8,
-						struct usb_hid_touchpad_report);
-static struct mutex report_queue_mutex;
-
-#define HID_TOUCHPAD_REPORT_SIZE  sizeof(struct usb_hid_touchpad_report)
-
-/*
- * Touchpad EP interval: Make sure this value is smaller than the typical
- * interrupt interval from the trackpad.
- */
-#define HID_TOUCHPAD_EP_INTERVAL_MS 2 /* ms */
-
-/* Discard TP events older than this time */
-#define EVENT_DISCARD_MAX_TIME (1 * SECOND)
-
-/* HID descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_TOUCHPAD) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_HID_TOUCHPAD,
-	.bAlternateSetting = 0,
-	.bNumEndpoints = 1,
-	.bInterfaceClass = USB_CLASS_HID,
-	.bInterfaceSubClass = 0,
-	.bInterfaceProtocol = 0,
-	.iInterface = 0,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_HID_TOUCHPAD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_TOUCHPAD_REPORT_SIZE,
-	.bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */
-};
-
-#define FINGER_USAGE \
-	0x05, 0x0D,        /*   Usage Page (Digitizer) */ \
-	0x09, 0x22,        /*   Usage (Finger) */ \
-	0xA1, 0x02,        /*   Collection (Logical) */ \
-	0x09, 0x47,        /*     Usage (Confidence) */ \
-	0x09, 0x42,        /*     Usage (Tip Switch) */ \
-	0x09, 0x32,        /*     Usage (In Range) */ \
-	0x15, 0x00,        /*     Logical Minimum (0) */ \
-	0x25, 0x01,        /*     Logical Maximum (1) */ \
-	0x75, 0x01,        /*     Report Size (1) */ \
-	0x95, 0x03,        /*     Report Count (3) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x51,        /*     Usage (0x51) Contact identifier */ \
-	0x75, 0x04,        /*     Report Size (4) */ \
-	0x95, 0x01,        /*     Report Count (1) */ \
-	0x25, 0x0F,        /*     Logical Maximum (15) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x0D,        /*     Usage Page (Digitizer) */ \
-			   /*     Logical Maximum of Pressure */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \
-	0x75, 0x09,        /*     Report Size (9) */ \
-	0x09, 0x30,        /*     Usage (Tip pressure) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, 0xFF, 0x0F,  /*     Logical Maximum (4095) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x09, 0x48,        /*     Usage (WIDTH) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x49,        /*     Usage (HEIGHT) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x01,        /*     Usage Page (Generic Desktop Ctrls) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x55, 0x0E,        /*     Unit Exponent (-2) */ \
-	0x65, 0x11,        /*     Unit (System: SI Linear, Length: cm) */ \
-	0x09, 0x30,        /*     Usage (X) */ \
-	0x35, 0x00,        /*     Physical Minimum (0) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x09, 0x31,        /*     Usage (Y) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0xC0               /*   End Collection */
-
-/*
- * HID: Report Descriptor
- * TODO(b/35582031): There are ways to reduce flash usage, as the
- * Finger Usage is repeated 5 times.
- */
-static const uint8_t report_desc[] = {
-	/* Touchpad Collection */
-	0x05, 0x0D,                    /* Usage Page (Digitizer) */
-	0x09, 0x05,                    /* Usage (Touch Pad) */
-	0xA1, 0x01,                    /* Collection (Application) */
-	0x85, REPORT_ID_TOUCHPAD,      /*   Report ID (1, Touch) */
-	/* Finger 0 */
-	FINGER_USAGE,
-	/* Finger 1 */
-	FINGER_USAGE,
-	/* Finger 2 */
-	FINGER_USAGE,
-	/* Finger 3 */
-	FINGER_USAGE,
-	/* Finger 4 */
-	FINGER_USAGE,
-	/* Contact count */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x09, 0x54,                    /*   Usage (Contact count) */
-	0x25, MAX_FINGERS,             /*   Logical Maximum (MAX_FINGERS) */
-	0x75, 0x07,                    /*   Report Size (7) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-	/* Button */
-	0x05, 0x01,                    /*   Usage Page(Generic Desktop Ctrls) */
-	0x05, 0x09,                    /*   Usage (Button) */
-	0x19, 0x01,                    /*   Usage Minimum (0x01) */
-	0x29, 0x01,                    /*   Usage Maximum (0x01) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x25, 0x01,                    /*   Logical Maximum (1) */
-	0x75, 0x01,                    /*   Report Size (1) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-	/* Timestamp */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x55, 0x0C,                    /*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,              /*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,  /*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,  /*   Logical Maximum (65535) */
-	0x75, 0x10,                    /*   Report Size (16) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x09, 0x56,                    /*   Usage (0x56, Relative Scan Time) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-
-	0x85, REPORT_ID_DEVICE_CAPS,   /*   Report ID (Device Capabilities) */
-	0x09, 0x55,                    /*   Usage (Contact Count Maximum) */
-	0x09, 0x59,                    /*   Usage (Pad Type) */
-	0x25, 0x0F,                    /*   Logical Maximum (15) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x95, 0x02,                    /*   Report Count (2) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	/* Page 0xFF, usage 0xC5 is device certificate. */
-	0x06, 0x00, 0xFF,              /*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,   /*   Report ID (Device Certification) */
-	0x09, 0xC5,                    /*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,              /*   Logical Maximum (255) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x96, 0x00, 0x01,              /*   Report Count (256) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	0xC0,                          /* End Collection */
-};
-
-/* A 256-byte default blob for the 'device certification status' feature report.
- *
- * TODO(b/113248108): do we need a real certification?
- */
-static const uint8_t device_cert_response[] = {
-	REPORT_ID_DEVICE_CERT,
-
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
-};
-
-/* Device capabilities feature report. */
-static const uint8_t device_caps_response[] = {
-	REPORT_ID_DEVICE_CAPS,
-
-	MAX_FINGERS,            /* Contact Count Maximum */
-	0x00,                   /* Pad Type: Depressible click-pad */
-};
-
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD,
-						hid, hid_desc_tp) = {
-	.bLength = 9,
-	.bDescriptorType = USB_HID_DT_HID,
-	.bcdHID = 0x0100,
-	.bCountryCode = 0x00, /* Hardware target country */
-	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
-};
-
-static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
-
-/*
- * Write a report to EP, must be called with queue mutex held, and caller
- * must first check that EP is not busy.
- */
-static void write_touchpad_report(struct usb_hid_touchpad_report *report)
-{
-	memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf),
-			 report, sizeof(*report));
-	/* enable TX */
-	STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0);
-
-	/*
-	 * Wake the host. This is required to prevent a race between EP getting
-	 * reloaded and host suspending the device, as, ideally, we never want
-	 * to have EP loaded during suspend, to avoid reporting stale data.
-	 */
-	usb_wake();
-}
-
-static void hid_touchpad_process_queue(void);
-DECLARE_DEFERRED(hid_touchpad_process_queue);
-
-static void hid_touchpad_process_queue(void)
-{
-	struct usb_hid_touchpad_report report;
-	uint16_t now;
-	int trimming = 0;
-
-	mutex_lock(&report_queue_mutex);
-
-	/* EP is busy, or nothing in queue: do nothing. */
-	if (queue_count(&report_queue) == 0)
-		goto unlock;
-
-	now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-	if (usb_is_suspended() ||
-			(STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK)
-				== EP_TX_VALID) {
-		usb_wake();
-
-		/* Let's trim old events from the queue, if any. */
-		trimming = 1;
-	} else {
-		hook_call_deferred(&hid_touchpad_process_queue_data, -1);
-	}
-
-	if (touchpad_debug)
-		CPRINTS("TPQ t=%d (%d)", trimming, queue_count(&report_queue));
-
-	while (queue_count(&report_queue) > 0) {
-		int delta;
-
-		queue_peek_units(&report_queue, &report, 0, 1);
-
-		delta = (int)((uint16_t)(now - report.timestamp))
-				* USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-		if (touchpad_debug)
-			CPRINTS("evt t=%d d=%d", report.timestamp, delta);
-
-		/* Drop old events */
-		if (delta > EVENT_DISCARD_MAX_TIME) {
-			queue_advance_head(&report_queue, 1);
-			continue;
-		}
-
-		if (trimming) {
-			/*
-			 * If we stil fail to resume, this will discard the
-			 * event after the timeout expires.
-			 */
-			hook_call_deferred(&hid_touchpad_process_queue_data,
-					   EVENT_DISCARD_MAX_TIME - delta);
-		} else {
-			queue_advance_head(&report_queue, 1);
-			write_touchpad_report(&report);
-		}
-		break;
-	}
-
-unlock:
-	mutex_unlock(&report_queue_mutex);
-}
-
-void set_touchpad_report(struct usb_hid_touchpad_report *report)
-{
-	static int print_full = 1;
-
-	mutex_lock(&report_queue_mutex);
-
-	/* USB/EP ready and nothing in queue, just write the report. */
-	if (!usb_is_suspended() &&
-	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID
-	    && queue_count(&report_queue) == 0) {
-		write_touchpad_report(report);
-		mutex_unlock(&report_queue_mutex);
-		return;
-	}
-
-	/* Else add to queue, dropping oldest event if needed. */
-	if (touchpad_debug)
-		CPRINTS("sTP t=%d", report->timestamp);
-	if (queue_is_full(&report_queue)) {
-		if (print_full)
-			CPRINTF("TP queue full\n");
-		print_full = 0;
-
-		queue_advance_head(&report_queue, 1);
-	} else {
-		print_full = 1;
-	}
-	queue_add_unit(&report_queue, report);
-
-	mutex_unlock(&report_queue_mutex);
-
-	hid_touchpad_process_queue();
-}
-
-static void hid_touchpad_tx(void)
-{
-	hid_tx(USB_EP_HID_TOUCHPAD);
-
-	if (queue_count(&report_queue) > 0)
-		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
-}
-
-static void hid_touchpad_event(enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET)
-		hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf,
-			  HID_TOUCHPAD_REPORT_SIZE, NULL, 0);
-	else if (evt == USB_EVENT_DEVICE_RESUME &&
-			queue_count(&report_queue) > 0)
-		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
-}
-
-USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx,
-	       hid_touchpad_event);
-
-static int get_report(uint8_t report_id, uint8_t report_type,
-		      const uint8_t **buffer_ptr,
-		      int *buffer_size)
-{
-	switch (report_id) {
-	case REPORT_ID_DEVICE_CAPS:
-		*buffer_ptr = device_caps_response;
-		*buffer_size = MIN(sizeof(device_caps_response), *buffer_size);
-		return 0;
-	case REPORT_ID_DEVICE_CERT:
-		*buffer_ptr = device_cert_response;
-		*buffer_size = MIN(sizeof(device_cert_response), *buffer_size);
-		return 0;
-	}
-	return -1;
-}
-
-static const struct usb_hid_config_t hid_config_tp = {
-	.report_desc = report_desc,
-	.report_size = sizeof(report_desc),
-	.hid_desc = &hid_desc_tp,
-	.get_report = get_report,
-};
-
-static int hid_touchpad_iface_request(usb_uint *ep0_buf_rx,
-				      usb_uint *ep0_buf_tx)
-{
-	return hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_tp);
-}
-USB_DECLARE_IFACE(USB_IFACE_HID_TOUCHPAD, hid_touchpad_iface_request)
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
deleted file mode 100644
index 0c75322a7d..0000000000
--- a/chip/stm32/usb_hw.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_HW_H
-#define __CROS_EC_USB_HW_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* Event types for the endpoint event handler. */
-enum usb_ep_event {
-	USB_EVENT_RESET,
-	USB_EVENT_DEVICE_RESUME, /* Device-initiated wake completed. */
-};
-
-#if defined(CHIP_FAMILY_STM32F4)
-#include "usb_dwc_hw.h"
-#else
-
-
-/*
- * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads &
- * writes are 16-bits wide). The endpoint tables and the data buffers live in
- * this RAM.
-*/
-
-/* Primitive to access the words in USB RAM */
-typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
-/* Linker symbol for start of USB RAM */
-extern usb_uint __usb_ram_start[];
-
-/* Attribute to define a buffer variable in USB RAM */
-#define __usb_ram __attribute__((section(".usb_ram.99_data")))
-
-/* Mask for the rx_count to identify the number of bytes in the buffer. */
-#define RX_COUNT_MASK (0x3ff)
-
-struct stm32_endpoint {
-	volatile usb_uint tx_addr;
-	volatile usb_uint tx_count;
-	volatile usb_uint rx_addr;
-	volatile usb_uint rx_count;
-};
-
-extern struct stm32_endpoint btable_ep[];
-
-/* Attribute to put the endpoint table in USB RAM */
-#define __usb_btable __attribute__((section(".usb_ram.00_btable")))
-
-/* Read from USB RAM into a usb_setup_packet struct */
-struct usb_setup_packet;
-void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet);
-
-/*
- * Copy data to and from the USB dedicated RAM and take care of the weird
- * addressing.  These functions correctly handle unaligned accesses to the USB
- * memory.  They have the same prototype as memcpy, allowing them to be used
- * in places that expect memcpy.  The void pointer used to represent a location
- * in the USB dedicated RAM should be the offset in that address space, not the
- * AHB address space.
- *
- * The USB packet RAM is attached to the processor via the AHB2APB bridge.  This
- * bridge performs manipulations of read and write accesses as per the note in
- * section 2.1 of RM0091.  The upshot is that custom memcpy-like routines need
- * to be employed.
- */
-void *memcpy_to_usbram(void *dest, const void *src, size_t n);
-void *memcpy_from_usbram(void *dest, const void *src, size_t n);
-
-/*
- * Descriptor patching support, useful to change a few values in the descriptor
- * (typically, length or bitfields) without having to move descriptors to RAM.
- */
-
-enum usb_desc_patch_type {
-#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-	USB_DESC_KEYBOARD_BACKLIGHT,
-#endif
-	USB_DESC_PATCH_COUNT,
-};
-
-/*
- * Set patch in table: replace uint16_t at address (STM32 flash) with data.
- *
- * The patches need to be setup before _before_ usb_init is executed (or, at
- * least, before the first call to memcpy_to_usbram_ep0_patch).
- */
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data);
-
-/* Copy to USB ram, applying patches to src as required. */
-void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
-
-/* Compute the address inside dedicate SRAM for the USB controller */
-#define usb_sram_addr(x) ((x - __usb_ram_start) * sizeof(uint16_t))
-
-/* Helpers for endpoint declaration */
-#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix)
-#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx)
-#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx)
-#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt)
-/* Used to check function types are correct (attribute alias does not do it) */
-#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck)
-#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
-#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
-
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)        \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
-
-/* arrays with all endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
-/* array with interface-specific control request callbacks */
-extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
-
-/*
- * Interface handler returns -1 on error, 0 if it wrote the last chunk of data,
- * or 1 if more data needs to be transferred on the next control request.
- */
-#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)					\
-	int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx,			\
-			       usb_uint *epo_buf_tx)			\
-	__attribute__ ((alias(STRINGIFY(handler))));
-
-#endif
-#endif	/* __CROS_EC_USB_HW_H */
diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c
deleted file mode 100644
index 792507aa75..0000000000
--- a/chip/stm32/usb_isochronous.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "stddef.h"
-#include "common.h"
-#include "config.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_hw.h"
-#include "usb_isochronous.h"
-
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/*
- * Currently, we only support TX direction for USB isochronous transfer.
- *
- * According to RM0091, isochronous transfer is always double buffered.
- * Addresses of buffers are pointed by `btable_ep[<endpoint>].tx_addr` and
- * `btable_ep[<endpoint>].rx_addr`.
- *
- * DTOG | USB Buffer | App Buffer
- * -----+------------+-----------
- *   0  | tx_addr    | rx_addr
- *   1  | rx_addr    | tx_addr
- *
- * That is, when DTOG bit is 0 (see `get_tx_dtog()`), USB hardware will read
- * from `tx_addr`, and our application can write new data to `rx_addr` at the
- * same time.
- *
- * Number of bytes in each buffer shall be tracked by `tx_count` and `rx_count`
- * respectively.
- *
- * `get_app_addr()`, `set_app_count()` help you to to select the correct
- * variable to use by given DTOG value, which is available by `get_tx_dtog()`.
- */
-
-/*
- * Gets current DTOG value of given `config`.
- */
-static int get_tx_dtog(struct usb_isochronous_config const *config)
-{
-	return !!(STM32_USB_EP(config->endpoint) & EP_TX_DTOG);
-}
-
-/*
- * Gets buffer address that can be used by software (application).
- *
- * The mapping between application buffer address and current TX DTOG value is
- * shown in table above.
- */
-static usb_uint *get_app_addr(struct usb_isochronous_config const *config,
-			      int dtog_value)
-{
-	return config->tx_ram[dtog_value];
-}
-
-/*
- * Sets number of bytes written to application buffer.
- */
-static void set_app_count(struct usb_isochronous_config const *config,
-			  int dtog_value,
-			  usb_uint count)
-{
-	if (dtog_value)
-		btable_ep[config->endpoint].tx_count = count;
-	else
-		btable_ep[config->endpoint].rx_count = count;
-}
-
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit)
-{
-	int dtog_value = get_tx_dtog(config);
-	usb_uint *buffer = get_app_addr(config, dtog_value);
-	uintptr_t ptr = usb_sram_addr(buffer);
-
-	if (*buffer_id == -1)
-		*buffer_id = dtog_value;
-	else if (dtog_value != *buffer_id)
-		return -EC_ERROR_TIMEOUT;
-
-	if (dst_offset > config->tx_size)
-		return -EC_ERROR_INVAL;
-
-	n = MIN(n, config->tx_size - dst_offset);
-	memcpy_to_usbram((void *)(ptr + dst_offset), src, n);
-
-	if (commit)
-		set_app_count(config, dtog_value, dst_offset + n);
-
-	return n;
-}
-
-void usb_isochronous_init(struct usb_isochronous_config const *config)
-{
-	int ep = config->endpoint;
-
-	btable_ep[ep].tx_addr = usb_sram_addr(get_app_addr(config, 1));
-	btable_ep[ep].rx_addr = usb_sram_addr(get_app_addr(config, 0));
-	set_app_count(config, 0, 0);
-	set_app_count(config, 1, 0);
-
-	STM32_USB_EP(ep) = ((ep << 0) | /* Endpoint Addr */
-			    EP_TX_VALID | /* start transmit */
-			    (2 << 9) | /* ISO EP */
-			    EP_RX_DISAB);
-}
-
-void usb_isochronous_event(struct usb_isochronous_config const *config,
-			   enum usb_ep_event evt)
-{
-	if (evt == USB_EVENT_RESET)
-		usb_isochronous_init(config);
-}
-
-void usb_isochronous_tx(struct usb_isochronous_config const *config)
-{
-	/*
-	 * Clear CTR_TX, note that EP_TX_VALID will *NOT* be cleared by
-	 * hardware, so we don't need to toggle it.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, 0, 0, 0);
-	/*
-	 * Clear buffer count for buffer we just transmitted, so we do not
-	 * transmit the data twice.
-	 */
-	set_app_count(config, get_tx_dtog(config), 0);
-
-	config->tx_callback(config);
-}
-
-int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx)
-{
-	int ret = -1;
-
-	if (ep0_buf_rx[0] == (USB_DIR_OUT |
-			      USB_TYPE_STANDARD |
-			      USB_RECIP_INTERFACE |
-			      USB_REQ_SET_INTERFACE << 8)) {
-		ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]);
-
-		if (ret == 0) {
-			/* ACK */
-			btable_ep[0].tx_count = 0;
-			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
-		}
-	}
-	return ret;
-}
diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h
deleted file mode 100644
index efa4d94ab4..0000000000
--- a/chip/stm32/usb_isochronous.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_ISOCHRONOUS_H
-#define __CROS_EC_USB_ISOCHRONOUS_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-struct usb_isochronous_config;
-
-/*
- * Currently, we only support TX direction for USB isochronous transfer.
- */
-
-/*
- * Copy `n` bytes from `src` to USB buffer.
- *
- * We are using double buffering, therefore, we need to write to the buffer that
- * hardware is not currently using.  This function will handle this for you.
- *
- * Sample usage:
- *
- *	int buffer_id = -1;  // initialize to unknown
- *	int ret;
- *	size_t dst_offset = 0, src_offset = 0;
- *	const uint8_t* buf;
- *	size_t buf_size;
- *
- *	while (1) {
- *		buf = ...;
- *		buf_size = ...;
- *		if (no more data) {
- *			buf = NULL;
- *			break;
- *		} else {
- *			ret = usb_isochronous_write_buffer(
- *				config, buf, buf_size, dst_offset,
- *				&buffer_id,
- *				0);
- *			if (ret < 0)
- *				goto FAILED;
- *			dst_offset += ret;
- *			if (ret != buf_size) {
- *				// no more space in TX buffer
- *				src_offset = ret;
- *				break;
- *			}
- *		}
- *	}
- *	// commit
- *	ret = usb_isochronous_write_buffer(
- *		config, NULL, 0, dst_offset,
- *		&buffer_id, 1);
- *	if (ret < 0)
- *		goto FAILED;
- *	if (buf)
- *		// buf[src_offset ... buf_size] haven't been sent yet, send them
- *		// later.
- *
- * On the first invocation, on success, `ret` will be number of bytes that have
- * been written, and `buffer_id` will be 0 or 1, depending on which buffer we
- * are writing.  And commit=0 means there are pending data, so buffer count
- * won't be set yet.
- *
- * On the second invocation, since buffer_id is not -1, we will return an error
- * if hardware has switched to this buffer (it means we spent too much time
- * filling buffer).  And commit=1 means we are done, and buffer count will be
- * set to `dst_offset + num_bytes_written` on success.
- *
- * @return  -EC_ERROR_CODE on failure, or number of bytes written on success.
- */
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit);
-
-struct usb_isochronous_config {
-	int endpoint;
-
-	/*
-	 * On TX complete, this function will be called in **interrupt
-	 * context**.
-	 *
-	 * @param config	the usb_isochronous_config of the USB interface.
-	 */
-	void (*tx_callback)(struct usb_isochronous_config const *config);
-
-	/*
-	 * Received SET_INTERFACE request.
-	 *
-	 * @param  alternate_setting	new bAlternateSetting value.
-	 * @param  interface		interface number.
-	 * @return int			0 for success, -1 for unknown setting.
-	 */
-	int (*set_interface)(usb_uint alternate_setting, usb_uint interface);
-
-	/* USB packet RAM buffer size. */
-	size_t tx_size;
-	/* USB packet RAM buffers. */
-	usb_uint *tx_ram[2];
-};
-
-/* Define an USB isochronous interface */
-#define USB_ISOCHRONOUS_CONFIG_FULL(NAME,				\
-				    INTERFACE,				\
-				    INTERFACE_CLASS,			\
-				    INTERFACE_SUBCLASS,			\
-				    INTERFACE_PROTOCOL,			\
-				    INTERFACE_NAME,			\
-				    ENDPOINT,				\
-				    TX_SIZE,				\
-				    TX_CALLBACK,			\
-				    SET_INTERFACE,			\
-				    NUM_EXTRA_ENDPOINTS)		\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-	/* Declare buffer */						\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \
-	struct usb_isochronous_config const NAME = {			\
-		.endpoint  = ENDPOINT,					\
-		.tx_callback = TX_CALLBACK,				\
-		.set_interface = SET_INTERFACE,				\
-		.tx_size   = TX_SIZE,					\
-		.tx_ram    = {						\
-			CONCAT2(NAME, _ep_tx_buffer_0),			\
-			CONCAT2(NAME, _ep_tx_buffer_1),			\
-		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 0,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = {		\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 1,				\
-		.bNumEndpoints      = 1 + NUM_EXTRA_ENDPOINTS,		\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x01 /* Isochronous IN */,		\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 1,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_isochronous_tx(&NAME);				\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_isochronous_event(&NAME, evt);			\
-	}								\
-	static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx)	\
-	{								\
-		return usb_isochronous_iface_handler(&NAME, rx, tx);	\
-	}								\
-	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));		\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_event));			\
-
-void usb_isochronous_tx(struct usb_isochronous_config const *config);
-void usb_isochronous_event(struct usb_isochronous_config const *config,
-			   enum usb_ep_event event);
-int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx);
-#endif /* __CROS_EC_USB_ISOCHRONOUS_H */
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
deleted file mode 100644
index 90506d8975..0000000000
--- a/chip/stm32/usb_pd_phy.c
+++ /dev/null
@@ -1,680 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "dma.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-#define PD_DATARATE 300000 /* Hz */
-
-/*
- * Maximum size of a Power Delivery packet (in bits on the wire) :
- *    16-bit header + 0..7 32-bit data objects  (+ 4b5b encoding)
- * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b)
- * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5
- */
-#define PD_BIT_LEN 429
-
-#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2)
-
-/* maximum number of consecutive similar bits with Biphase Mark Coding */
-#define MAX_BITS 2
-
-/* alternating bit sequence used for packet preamble : 00 10 11 01 00 ..  */
-#define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */
-
-#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE)))
-
-/* threshold for 1 300-khz period */
-#define PERIOD 4
-#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD)
-#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2)
-
-static struct pd_physical {
-	/* samples for the PD messages */
-	uint32_t raw_samples[DIV_ROUND_UP(PD_MAX_RAW_SIZE, sizeof(uint32_t))];
-
-	/* state of the bit decoder */
-	int d_toggle;
-	int d_lastlen;
-	uint32_t d_last;
-	int b_toggle;
-
-	/* DMA structures for each PD port */
-	struct dma_option dma_tx_option;
-	struct dma_option dma_tim_option;
-
-	/* Pointers to timer register for each port */
-	timer_ctlr_t *tim_tx;
-	timer_ctlr_t *tim_rx;
-} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* keep track of RX edge timing in order to trigger receive */
-static timestamp_t
-	rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT];
-static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* keep track of transmit polarity for DMA interrupt */
-static int tx_dma_polarities[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void pd_init_dequeue(int port)
-{
-	/* preamble ends with 1 */
-	pd_phy[port].d_toggle = 0;
-	pd_phy[port].d_last = 0;
-	pd_phy[port].d_lastlen = 0;
-}
-
-static int wait_bits(int port, int nb)
-{
-	int avail;
-	stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port));
-
-	avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE);
-	if (avail < nb) { /* no received yet ... */
-		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb)
-			&& !(pd_phy[port].tim_rx->sr & 4))
-			; /* optimized for latency, not CPU usage ... */
-		if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) {
-			CPRINTS("PD TMOUT RX %d/%d",
-				dma_bytes_done(rx, PD_MAX_RAW_SIZE), nb);
-			return -1;
-		}
-	}
-	return nb;
-}
-
-int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
-{
-	int w;
-	uint8_t cnt = 0xff;
-	uint8_t *samples = (uint8_t *)pd_phy[port].raw_samples;
-
-	while ((pd_phy[port].d_lastlen < len) && (off < PD_MAX_RAW_SIZE - 1)) {
-		w = wait_bits(port, off + 2);
-		if (w < 0)
-			goto stream_err;
-		cnt = samples[off] - samples[off-1];
-		if (!cnt || (cnt > 3*PERIOD))
-			goto stream_err;
-		off++;
-		if (cnt <= PERIOD_THRESHOLD) {
-			/*
-			w = wait_bits(port, off + 1);
-			if (w < 0)
-				goto stream_err;
-			*/
-			cnt = samples[off] - samples[off-1];
-			if (cnt >  PERIOD_THRESHOLD)
-				goto stream_err;
-			off++;
-		}
-
-		/* enqueue the bit of the last period */
-		pd_phy[port].d_last = (pd_phy[port].d_last >> 1)
-		       | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
-		pd_phy[port].d_lastlen++;
-	}
-	if (off < PD_MAX_RAW_SIZE) {
-		*val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len))
-				>> (32 - len);
-		pd_phy[port].d_lastlen -= len;
-		return off;
-	} else {
-		return -1;
-	}
-stream_err:
-	/* CPRINTS("PD Invalid %d @%d", cnt, off); */
-	return -1;
-}
-
-int pd_find_preamble(int port)
-{
-	int bit;
-	uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples;
-
-	/*
-	 * Detect preamble
-	 * Alternate 1-period 1-period & 2-period.
-	 */
-	uint32_t all = 0;
-	stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port));
-
-	for (bit = 1; bit < PD_MAX_RAW_SIZE - 1; bit++) {
-		uint8_t cnt;
-		/* wait if the bit is not received yet ... */
-		if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) {
-			while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) &&
-				!(pd_phy[port].tim_rx->sr & 4))
-				;
-			if (pd_phy[port].tim_rx->sr & 4) {
-				CPRINTS("PD TMOUT RX %d/%d",
-					PD_MAX_RAW_SIZE - rx->cndtr, bit);
-				return -1;
-			}
-		}
-		cnt = vals[bit] - vals[bit-1];
-		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0);
-		if (all == 0x36db6db6)
-			return bit - 1; /* should be SYNC-1 */
-		if (all == 0xF33F3F3F)
-			return PD_RX_ERR_HARD_RESET; /* got HARD-RESET */
-		if (all == 0x3c7fe0ff)
-			return PD_RX_ERR_CABLE_RESET; /* got CABLE-RESET */
-	}
-	return -1;
-}
-
-int pd_write_preamble(int port)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-
-	/* 64-bit x2 preamble */
-	msg[0] = PD_PREAMBLE;
-	msg[1] = PD_PREAMBLE;
-	msg[2] = PD_PREAMBLE;
-	msg[3] = PD_PREAMBLE;
-	pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */
-	return 2*64;
-}
-
-int pd_write_sym(int port, int bit_off, uint32_t val10)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-	int word_idx = bit_off / 32;
-	int bit_idx = bit_off % 32;
-	uint32_t val = pd_phy[port].b_toggle ^ val10;
-	pd_phy[port].b_toggle = val & 0x200 ? 0x3FF : 0;
-	if (bit_idx <= 22) {
-		if (bit_idx == 0)
-			msg[word_idx] = 0;
-		msg[word_idx] |= val << bit_idx;
-	} else {
-		msg[word_idx] |= val << bit_idx;
-		msg[word_idx+1] = val >> (32 - bit_idx);
-		/* side effect: clear the new word when starting it */
-	}
-	return bit_off + 5*2;
-}
-
-int pd_write_last_edge(int port, int bit_off)
-{
-	uint32_t *msg = pd_phy[port].raw_samples;
-	int word_idx = bit_off / 32;
-	int bit_idx = bit_off % 32;
-
-	if (bit_idx == 0)
-		msg[word_idx] = 0;
-
-	if (!pd_phy[port].b_toggle /* last bit was 0 */) {
-		/* transition to 1, another 1, then 0 */
-		if (bit_idx == 31) {
-			msg[word_idx++] |= 1 << bit_idx;
-			msg[word_idx] = 1;
-		} else {
-			msg[word_idx] |= 3 << bit_idx;
-		}
-	}
-	/* ensure that the trailer is 0 */
-	msg[word_idx+1] = 0;
-
-	return bit_off + 3;
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-void pd_dump_packet(int port, const char *msg)
-{
-	uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples;
-	int bit;
-
-	CPRINTF("ERR %s:\n000:- ", msg);
-	/* Packet debug output */
-	for (bit = 1; bit <  PD_MAX_RAW_SIZE; bit++) {
-		int cnt = NB_PERIOD(vals[bit-1], vals[bit]);
-		if ((bit & 31) == 0)
-			CPRINTF("\n%03d:", bit);
-		CPRINTF("%1d ", cnt);
-	}
-	CPRINTF("><\n");
-	cflush();
-	for (bit = 0; bit <  PD_MAX_RAW_SIZE; bit++) {
-		if ((bit & 31) == 0)
-			CPRINTF("\n%03d:", bit);
-		CPRINTF("%02x ", vals[bit]);
-	}
-	CPRINTF("||\n");
-	cflush();
-}
-#endif /* CONFIG_COMMON_RUNTIME */
-
-/* --- SPI TX operation --- */
-
-void pd_tx_spi_init(int port)
-{
-	stm32_spi_regs_t *spi = SPI_REGS(port);
-
-	/* Enable Tx DMA for our first transaction */
-	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8);
-
-	/* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */
-	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST
-		 | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE
-		 | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
-}
-
-static void tx_dma_done(void *data)
-{
-	int port = (int)data;
-	int polarity = tx_dma_polarities[port];
-	stm32_spi_regs_t *spi = SPI_REGS(port);
-
-	while (spi->sr & STM32_SPI_SR_FTLVL)
-		; /* wait for TX FIFO empty */
-	while (spi->sr & STM32_SPI_SR_BSY)
-		; /* wait for BSY == 0 */
-
-	/* Stop counting */
-	pd_phy[port].tim_tx->cr1 &= ~1;
-
-	/* put TX pins and reference in Hi-Z */
-	pd_tx_disable(port, polarity);
-
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC);
-#endif
-}
-
-int pd_start_tx(int port, int polarity, int bit_len)
-{
-	stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX(port));
-
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* disable RX detection interrupt */
-	pd_rx_disable_monitoring(port);
-
-	/* Check that we are not receiving a frame to avoid collisions */
-	if (pd_rx_started(port))
-		return -5;
-#endif /* !CONFIG_USB_PD_TX_PHY_ONLY */
-
-	/* Initialize spi peripheral to prepare for transmission. */
-	pd_tx_spi_init(port);
-
-	/*
-	 * Set timer to one tick before reset so that the first tick causes
-	 * a rising edge on the output.
-	 */
-	pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1;
-
-	/* update DMA configuration */
-	dma_prepare_tx(&(pd_phy[port].dma_tx_option),
-			DIV_ROUND_UP(bit_len, 8),
-			pd_phy[port].raw_samples);
-	/* Flush data in write buffer so that DMA can get the latest data */
-	asm volatile("dmb;");
-
-	/* Kick off the DMA to send the data */
-	dma_clear_isr(DMAC_SPI_TX(port));
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	tx_dma_polarities[port] = polarity;
-	if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) {
-		/* Only enable interrupt if not in circular mode */
-		dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port),
-						 &tx_dma_done,
-						 (void *)port);
-	}
-#endif
-	dma_go(tx);
-
-	/*
-	 * Drive the CC line from the TX block :
-	 * - put SPI function on TX pin.
-	 * - set the low level reference.
-	 * Call this last before enabling timer in order to meet spec on
-	 * timing between enabling TX and clocking out bits.
-	 */
-	pd_tx_enable(port, polarity);
-
-	/* Start counting at 300Khz*/
-	pd_phy[port].tim_tx->cr1 |= 1;
-
-	return bit_len;
-}
-
-void pd_tx_done(int port, int polarity)
-{
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	/* wait for DMA, DMA interrupt will stop the SPI clock */
-	task_wait_event_mask(TASK_EVENT_DMA_TC, DMA_TRANSFER_TIMEOUT_US);
-	dma_disable_tc_interrupt(DMAC_SPI_TX(port));
-#else
-	tx_dma_polarities[port] = polarity;
-	tx_dma_done((void *)port);
-#endif
-
-	/* Reset SPI to clear remaining data in buffer */
-	pd_tx_spi_reset(port);
-}
-
-void pd_tx_set_circular_mode(int port)
-{
-	pd_phy[port].dma_tx_option.flags |= STM32_DMA_CCR_CIRC;
-}
-
-void pd_tx_clear_circular_mode(int port)
-{
-	/* clear the circular mode bit in flag variable */
-	pd_phy[port].dma_tx_option.flags &= ~STM32_DMA_CCR_CIRC;
-	/* disable dma transaction underway */
-	dma_disable(DMAC_SPI_TX(port));
-#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS)
-	tx_dma_done((void *)port);
-#endif
-}
-
-/* --- RX operation using comparator linked to timer --- */
-
-void pd_rx_start(int port)
-{
-	/* start sampling the edges on the CC line using the RX timer */
-	dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE,
-			pd_phy[port].raw_samples);
-	/* enable TIM2 DMA requests */
-	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */;
-	pd_phy[port].tim_rx->sr = 0; /* clear overflows */
-	pd_phy[port].tim_rx->cr1 |= 1;
-}
-
-void pd_rx_complete(int port)
-{
-	/* stop stampling TIM2 */
-	pd_phy[port].tim_rx->cr1 &= ~1;
-	/* stop DMA */
-	dma_disable(DMAC_TIM_RX(port));
-}
-
-int pd_rx_started(int port)
-{
-	/* is the sampling timer running ? */
-	return pd_phy[port].tim_rx->cr1 & 1;
-}
-
-void pd_rx_enable_monitoring(int port)
-{
-	/* clear comparator external interrupt */
-	STM32_EXTI_PR = EXTI_COMP_MASK(port);
-	/* enable comparator external interrupt */
-	STM32_EXTI_IMR |= EXTI_COMP_MASK(port);
-}
-
-void pd_rx_disable_monitoring(int port)
-{
-	/* disable comparator external interrupt */
-	STM32_EXTI_IMR &= ~EXTI_COMP_MASK(port);
-	/* clear comparator external interrupt */
-	STM32_EXTI_PR = EXTI_COMP_MASK(port);
-}
-
-uint64_t get_time_since_last_edge(int port)
-{
-	int prev_idx = (rx_edge_ts_idx[port] == 0) ?
-			PD_RX_TRANSITION_COUNT - 1 :
-			rx_edge_ts_idx[port] - 1;
-	return get_time().val - rx_edge_ts[port][prev_idx].val;
-}
-
-/* detect an edge on the PD RX pin */
-void pd_rx_handler(void)
-{
-	int pending, i;
-	int next_idx;
-	pending = STM32_EXTI_PR;
-
-#ifdef CONFIG_USB_CTVPD
-	/* Charge-Through Side detach event */
-	if (pending & EXTI_COMP2_MASK) {
-		task_wake(PD_PORT_TO_TASK_ID(0));
-		/* Clear interrupt */
-		STM32_EXTI_PR = EXTI_COMP2_MASK;
-		pending &= ~EXTI_COMP2_MASK;
-	}
-#endif
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (pending & EXTI_COMP_MASK(i)) {
-			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
-			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
-
-#if defined(CONFIG_LOW_POWER_IDLE) &&                        \
-defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
-			/*
-			 * Do not deep sleep while waiting for more edges. For
-			 * most boards, sleep is already disabled due to being
-			 * in PD connected state, but boards which define
-			 * CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED can
-			 * sleep while connected.
-			 */
-			disable_sleep(SLEEP_MASK_USB_PD);
-#endif
-
-			/*
-			 * If we have seen enough edges in a certain amount of
-			 * time, then trigger RX start.
-			 */
-			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
-				/* start sampling */
-				pd_rx_start(i);
-				/*
-				 * ignore the comparator IRQ until we are done
-				 * with current message
-				 */
-				pd_rx_disable_monitoring(i);
-				/* trigger the analysis in the task */
-				pd_rx_event(i);
-			} else {
-				/* do not trigger RX start, just clear int */
-				STM32_EXTI_PR = EXTI_COMP_MASK(i);
-			}
-			rx_edge_ts_idx[i] = next_idx;
-		}
-	}
-}
-#ifdef CONFIG_USB_PD_RX_COMP_IRQ
-DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1);
-#endif
-
-/* --- release hardware --- */
-void pd_hw_release(int port)
-{
-	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 0);
-	__hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 0);
-	dma_disable(DMAC_SPI_TX(port));
-}
-
-/* --- Startup initialization --- */
-
-void pd_hw_init_rx(int port)
-{
-	struct pd_physical *phy = &pd_phy[port];
-
-	/* configure registers used for timers */
-	phy->tim_rx = (void *)TIM_REG_RX(port);
-
-	/* configure RX DMA */
-	phy->dma_tim_option.channel = DMAC_TIM_RX(port);
-	phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port));
-	phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				     STM32_DMA_CCR_PSIZE_16_BIT;
-
-	/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
-	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1);
-	/* Timer configuration */
-	phy->tim_rx->cr1 = 0x0000;
-	phy->tim_rx->cr2 = 0x0000;
-	phy->tim_rx->dier = 0x0000;
-	/* Auto-reload value : 16-bit free running counter */
-	phy->tim_rx->arr = 0xFFFF;
-
-	/* Timeout for message receive */
-	phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000;
-	/* Timer ICx input configuration */
-	if (TIM_RX_CCR_IDX(port) == 1)
-		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0;
-	else if (TIM_RX_CCR_IDX(port) == 2)
-		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 8;
-	else if (TIM_RX_CCR_IDX(port) == 4)
-		phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8;
-	else
-		/*  Unsupported RX timer capture input */
-		ASSERT(0);
-
-	phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4);
-	/* configure DMA request on CCRx update */
-	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */;
-	/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
-	phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1;
-	/* Reload the pre-scaler and reset the counter (clear CCRx) */
-	phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port));
-	/* clear update event from reloading */
-	phy->tim_rx->sr = 0;
-
-	/* --- DAC configuration for comparator at 850mV --- */
-#ifdef CONFIG_PD_USE_DAC_AS_REF
-	/* Enable DAC interface clock. */
-	STM32_RCC_APB1ENR |= BIT(29);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* set voltage Vout=0.850V (Vref = 3.0V) */
-	STM32_DAC_DHR12RD = 850 * 4096 / 3000;
-	/* Start DAC channel 1 */
-	STM32_DAC_CR = STM32_DAC_CR_EN1;
-#endif
-
-	/* --- COMP2 as comparator for RX vs Vmid = 850mV --- */
-#ifdef CONFIG_USB_PD_INTERNAL_COMP
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
-	/* turn on COMP/SYSCFG */
-	STM32_RCC_APB2ENR |= BIT(0);
-	/* Delay 1 APB clock cycle after the clock is enabled */
-	clock_wait_bus_cycles(BUS_APB, 1);
-	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
-	STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED |
-			 STM32_COMP_CMP1INSEL_INM6 |
-			 CMP1OUTSEL |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2INSEL_INM6 |
-			 CMP2OUTSEL |
-			 STM32_COMP_CMP2HYST_HI;
-#elif defined(CHIP_FAMILY_STM32L)
-	STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */
-
-	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
-			| STM32_COMP_SPEED_FAST;
-	/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
-	STM32_RI_ASCR2 |= BIT(4);
-#else
-#error Unsupported chip family
-#endif
-#endif /* CONFIG_USB_PD_INTERNAL_COMP */
-
-	/* comparator interrupt setup */
-	EXTI_XTSR |= EXTI_COMP_MASK(port);
-	STM32_EXTI_IMR |= EXTI_COMP_MASK(port);
-	task_enable_irq(IRQ_COMP);
-}
-
-void pd_hw_init(int port, enum pd_power_role role)
-{
-	struct pd_physical *phy = &pd_phy[port];
-	uint32_t val;
-
-	/* Initialize all PD pins to default state based on desired role */
-	pd_config_init(port, role);
-
-	/* set 40 MHz pin speed on communication pins */
-	pd_set_pins_speed(port);
-
-	/* --- SPI init --- */
-
-	/* Enable clocks to SPI module */
-	spi_enable_clock(port);
-
-	/* Initialize SPI peripheral registers */
-	pd_tx_spi_init(port);
-
-	/* configure TX DMA */
-	phy->dma_tx_option.channel = DMAC_SPI_TX(port);
-	phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr;
-	phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				    STM32_DMA_CCR_PSIZE_8_BIT;
-	dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE,
-			phy->raw_samples);
-
-	/* configure registers used for timers */
-	phy->tim_tx = (void *)TIM_REG_TX(port);
-
-	/* --- set the TX timer with updates at 600KHz (BMC frequency) --- */
-	__hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 1);
-	/* Timer configuration */
-	phy->tim_tx->cr1 = 0x0000;
-	phy->tim_tx->cr2 = 0x0000;
-	phy->tim_tx->dier = 0x0000;
-	/* Auto-reload value : 600000 Khz overflow */
-	phy->tim_tx->arr = TX_CLOCK_DIV;
-	/* 50% duty cycle on the output */
-	phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2;
-	/* Timer channel output configuration */
-	val = (6 << 4) | BIT(3);
-	if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */
-		val <<= 8;
-	if (TIM_TX_CCR_IDX(port) <= 2)
-		phy->tim_tx->ccmr1 = val;
-	else
-		phy->tim_tx->ccmr2 = val;
-
-	phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4);
-	phy->tim_tx->bdtr = 0x8000;
-	/* set prescaler to /1 */
-	phy->tim_tx->psc = 0;
-	/* Reload the pre-scaler and reset the counter */
-	phy->tim_tx->egr = 0x0001;
-#ifndef CONFIG_USB_PD_TX_PHY_ONLY
-	/* Configure the reception side : comparators + edge timer + DMA */
-	pd_hw_init_rx(port);
-#endif /* CONFIG_USB_PD_TX_PHY_ONLY */
-
-	CPRINTS("USB PD initialized");
-}
-
-void pd_set_clock(int port, int freq)
-{
-	pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq);
-}
diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c
deleted file mode 100644
index 24dbff06cd..0000000000
--- a/chip/stm32/usb_power.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "timer.h"
-#include "usb_descriptor.h"
-#include "usb_power.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-static int usb_power_init_inas(struct usb_power_config const *config);
-static int usb_power_read(struct usb_power_config const *config);
-static int usb_power_write_line(struct usb_power_config const *config);
-
-void usb_power_deferred_rx(struct usb_power_config const *config)
-{
-	int rx_count = rx_ep_pending(config->endpoint);
-
-	/* Handle an incoming command if available */
-	if (rx_count)
-		usb_power_read(config);
-}
-
-void usb_power_deferred_tx(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	if (!tx_ep_is_ready(config->endpoint))
-		return;
-
-	/* We've replied, set up the next read. */
-	if (!rx_ep_is_active(config->endpoint)) {
-		/* Remove any active dma region from output buffer */
-		state->reports_xmit_active = state->reports_tail;
-
-		/* Wait for the next command */
-		usb_read_ep(config->endpoint,
-			config->ep->out_databuffer_max,
-			config->ep->out_databuffer);
-		return;
-	}
-}
-
-/* Reset stream */
-void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt)
-{
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	config->ep->out_databuffer = config->state->rx_buf;
-	config->ep->out_databuffer_max = sizeof(config->state->rx_buf);
-	config->ep->in_databuffer = config->state->tx_buf;
-	config->ep->in_databuffer_max = sizeof(config->state->tx_buf);
-
-	epN_reset(config->endpoint);
-
-	/* Flush any queued data */
-	hook_call_deferred(config->ep->rx_deferred, 0);
-	hook_call_deferred(config->ep->tx_deferred, 0);
-}
-
-
-/* Write one or more power records to USB */
-static int usb_power_write_line(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_tail));
-	/* status + size + timestamps + power list */
-	size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count);
-
-	/* Check if queue has active data. */
-	if (config->state->reports_head != config->state->reports_tail) {
-		int recordcount = 1;
-
-		/* We'll concatenate all the upcoming recrds. */
-		if (config->state->reports_tail < config->state->reports_head)
-			recordcount = config->state->reports_head -
-				      config->state->reports_tail;
-		else
-			recordcount = state->max_cached -
-				      config->state->reports_tail;
-
-		state->reports_xmit_active = state->reports_tail;
-		state->reports_tail = (state->reports_tail + recordcount) %
-			state->max_cached;
-
-		usb_write_ep(config->endpoint, bytes * recordcount, r);
-		return bytes;
-	}
-
-	return 0;
-}
-
-
-static int usb_power_state_reset(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	state->state = USB_POWER_STATE_OFF;
-	state->reports_head = 0;
-	state->reports_tail = 0;
-	state->reports_xmit_active = 0;
-
-	CPRINTS("[RESET] STATE -> OFF");
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_stop(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-
-	/* Only a valid transition from CAPTURING */
-	if (state->state != USB_POWER_STATE_CAPTURING) {
-		CPRINTS("[STOP] Error not capturing.");
-		return USB_POWER_ERROR_NOT_CAPTURING;
-	}
-
-	state->state = USB_POWER_STATE_OFF;
-	state->reports_head = 0;
-	state->reports_tail = 0;
-	state->reports_xmit_active = 0;
-	state->stride_bytes = 0;
-	CPRINTS("[STOP] STATE: CAPTURING -> OFF");
-	return USB_POWER_SUCCESS;
-}
-
-
-
-static int usb_power_state_start(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	struct usb_power_state *state = config->state;
-	int integration_us = cmd->start.integration_us;
-	int ret;
-
-	if (state->state != USB_POWER_STATE_SETUP) {
-		CPRINTS("[START] Error not setup.");
-		return USB_POWER_ERROR_NOT_SETUP;
-	}
-
-	if (count != sizeof(struct usb_power_command_start)) {
-		CPRINTS("[START] Error count %d is not %d", (int)count,
-			sizeof(struct usb_power_command_start));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	if (integration_us == 0) {
-		CPRINTS("[START] integration_us cannot be 0");
-		return USB_POWER_ERROR_UNKNOWN;
-	}
-
-	/* Calculate the reports array */
-	state->stride_bytes = USB_POWER_RECORD_SIZE(state->ina_count);
-	state->max_cached = USB_POWER_MAX_CACHED(state->ina_count);
-
-	state->integration_us = integration_us;
-	ret = usb_power_init_inas(config);
-
-	if (ret)
-		return USB_POWER_ERROR_INVAL;
-
-	state->state = USB_POWER_STATE_CAPTURING;
-	CPRINTS("[START] STATE: SETUP -> CAPTURING %dus", integration_us);
-
-	/* Find our starting time. */
-	config->state->base_time = get_time().val;
-
-	hook_call_deferred(config->deferred_cap, state->integration_us);
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_settime(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	if (count != sizeof(struct usb_power_command_settime)) {
-		CPRINTS("[SETTIME] Error: count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_settime));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	/* Find the offset between microcontroller clock and host clock. */
-	if (cmd->settime.time)
-		config->state->wall_offset = cmd->settime.time - get_time().val;
-	else
-		config->state->wall_offset = 0;
-
-	return USB_POWER_SUCCESS;
-}
-
-
-static int usb_power_state_addina(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
-{
-	struct usb_power_state *state = config->state;
-	struct usb_power_ina_cfg *ina;
-	int i;
-
-	/* Only valid from OFF or SETUP */
-	if ((state->state != USB_POWER_STATE_OFF) &&
-	    (state->state != USB_POWER_STATE_SETUP)) {
-		CPRINTS("[ADDINA] Error incorrect state.");
-		return USB_POWER_ERROR_NOT_SETUP;
-	}
-
-	if (count != sizeof(struct usb_power_command_addina)) {
-		CPRINTS("[ADDINA] Error count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_addina));
-		return USB_POWER_ERROR_READ_SIZE;
-	}
-
-	if (state->ina_count >= USB_POWER_MAX_READ_COUNT) {
-		CPRINTS("[ADDINA] Error INA list full");
-		return USB_POWER_ERROR_FULL;
-	}
-
-	/* Transition to SETUP state if necessary and clear INA data */
-	if (state->state == USB_POWER_STATE_OFF) {
-		state->state = USB_POWER_STATE_SETUP;
-		state->ina_count = 0;
-	}
-
-	if ((cmd->addina.type < USBP_INA231_POWER) ||
-	    (cmd->addina.type > USBP_INA231_SHUNTV)) {
-		CPRINTS("[ADDINA] Error INA type 0x%x invalid",
-			(int)(cmd->addina.type));
-		return USB_POWER_ERROR_INVAL;
-	}
-
-	if (cmd->addina.rs == 0) {
-		CPRINTS("[ADDINA] Error INA resistance cannot be zero!");
-		return USB_POWER_ERROR_INVAL;
-	}
-
-	/* Select INA to configure */
-	ina = state->ina_cfg + state->ina_count;
-
-	ina->port = cmd->addina.port;
-	ina->addr_flags = cmd->addina.addr_flags;
-	ina->rs = cmd->addina.rs;
-	ina->type = cmd->addina.type;
-
-	/*
-	 * INAs can be shared, in that they will have various values
-	 * (and therefore registers) read from them each cycle, including
-	 * power, voltage, current. If only a single value is read,
-	 * we an use i2c_readagain for faster transactions as we don't
-	 * have to respecify the address.
-	 */
-	ina->shared = 0;
-#ifdef USB_POWER_VERBOSE
-	ina->shared = 1;
-#endif
-
-	/* Check if shared with previously configured INAs. */
-	for (i = 0; i < state->ina_count; i++) {
-		struct usb_power_ina_cfg *tmp = state->ina_cfg + i;
-
-		if ((tmp->port == ina->port) &&
-		    (tmp->addr_flags == ina->addr_flags)) {
-			ina->shared = 1;
-			tmp->shared = 1;
-		}
-	}
-
-	state->ina_count += 1;
-	return USB_POWER_SUCCESS;
-}
-
-static int usb_power_read(struct usb_power_config const *config)
-{
-	/*
-	 * If there is a USB packet waiting we process it and generate a
-	 * response.
-	 */
-	uint8_t count		= rx_ep_pending(config->endpoint);
-	uint8_t result		= USB_POWER_SUCCESS;
-	union usb_power_command_data *cmd =
-		(union usb_power_command_data *)config->ep->out_databuffer;
-
-	struct usb_power_state *state = config->state;
-	struct dwc_usb_ep *ep = config->ep;
-
-	/* Bytes to return */
-	int in_msgsize = 1;
-
-	if (count < 2)
-		return EC_ERROR_INVAL;
-
-	/* State machine. */
-	switch (cmd->command) {
-	case USB_POWER_CMD_RESET:
-		result = usb_power_state_reset(config);
-		break;
-
-	case USB_POWER_CMD_STOP:
-		result = usb_power_state_stop(config);
-		break;
-
-	case USB_POWER_CMD_START:
-		result = usb_power_state_start(config, cmd, count);
-		if (result == USB_POWER_SUCCESS) {
-			/* Send back actual integration time. */
-			ep->in_databuffer[1] =
-				(state->integration_us >> 0) & 0xff;
-			ep->in_databuffer[2] =
-				(state->integration_us >> 8) & 0xff;
-			ep->in_databuffer[3] =
-				(state->integration_us >> 16) & 0xff;
-			ep->in_databuffer[4] =
-				(state->integration_us >> 24) & 0xff;
-			in_msgsize += 4;
-		}
-		break;
-
-	case USB_POWER_CMD_ADDINA:
-		result = usb_power_state_addina(config, cmd, count);
-		break;
-
-	case USB_POWER_CMD_SETTIME:
-		result = usb_power_state_settime(config, cmd, count);
-		break;
-
-	case USB_POWER_CMD_NEXT:
-		if (state->state == USB_POWER_STATE_CAPTURING) {
-			int ret;
-
-			ret = usb_power_write_line(config);
-			if (ret)
-				return EC_SUCCESS;
-
-			result = USB_POWER_ERROR_BUSY;
-		} else {
-			CPRINTS("[STOP] Error not capturing.");
-			result = USB_POWER_ERROR_NOT_CAPTURING;
-		}
-		break;
-
-	default:
-		CPRINTS("[ERROR] Unknown command 0x%04x", (int)cmd->command);
-		result = USB_POWER_ERROR_UNKNOWN;
-		break;
-	}
-
-	/* Return result code if applicable. */
-	ep->in_databuffer[0] = result;
-
-	usb_write_ep(config->endpoint, in_msgsize, ep->in_databuffer);
-
-	return EC_SUCCESS;
-}
-
-
-
-/******************************************************************************
- * INA231 interface.
- * List the registers and fields here.
- * TODO(nsanders): combine with the currently incompatible common INA drivers.
- */
-
-#define INA231_REG_CONF 0
-#define INA231_REG_RSHV 1
-#define INA231_REG_BUSV 2
-#define INA231_REG_PWR  3
-#define INA231_REG_CURR 4
-#define INA231_REG_CAL  5
-#define INA231_REG_EN   6
-
-
-#define INA231_CONF_AVG(val)		(((int)(val & 0x7)) << 9)
-#define INA231_CONF_BUS_TIME(val)	(((int)(val & 0x7)) << 6)
-#define INA231_CONF_SHUNT_TIME(val)	(((int)(val & 0x7)) << 3)
-#define INA231_CONF_MODE(val)		(((int)(val & 0x7)) << 0)
-#define INA231_MODE_OFF			0x0
-#define INA231_MODE_SHUNT		0x5
-#define INA231_MODE_BUS			0x6
-#define INA231_MODE_BOTH		0x7
-
-int reg_type_mapping(enum usb_power_ina_type ina_type)
-{
-	switch (ina_type) {
-	case USBP_INA231_POWER:
-		return INA231_REG_PWR;
-	case USBP_INA231_BUSV:
-		return INA231_REG_BUSV;
-	case USBP_INA231_CURRENT:
-		return INA231_REG_CURR;
-	case USBP_INA231_SHUNTV:
-		return INA231_REG_RSHV;
-
-	default:
-		return INA231_REG_CONF;
-	}
-}
-
-uint16_t ina2xx_readagain(uint8_t port, uint16_t slave_addr_flags)
-{
-	int res;
-	uint16_t val;
-
-	res = i2c_xfer(port, slave_addr_flags,
-		       NULL, 0, (uint8_t *)&val, sizeof(uint16_t));
-
-	if (res) {
-		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags));
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-
-uint16_t ina2xx_read(uint8_t port, uint16_t slave_addr_flags,
-		     uint8_t reg)
-{
-	int res;
-	int val;
-
-	res = i2c_read16(port, slave_addr_flags, reg, &val);
-	if (res) {
-		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags),
-			(int)reg);
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-int ina2xx_write(uint8_t port, uint16_t slave_addr_flags,
-		 uint8_t reg, uint16_t val)
-{
-	int res;
-	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
-
-	res = i2c_write16(port, slave_addr_flags, reg, be_val);
-	if (res)
-		CPRINTS("INA2XX I2C write failed");
-	return res;
-}
-
-
-
-/******************************************************************************
- * Background tasks
- *
- * Here we setup the INAs and read them at the specified interval.
- * INA samples are stored in a ringbuffer that can be fetched using the
- * USB commands.
- */
-
-/* INA231 integration and averaging time presets, indexed by register value */
-#define NELEMS(x)  (sizeof(x) / sizeof((x)[0]))
-static const int average_settings[] = {
-	1, 4, 16, 64, 128, 256, 512, 1024};
-static const int conversion_time_us[] =	{
-	140, 204, 332, 588, 1100, 2116, 4156, 8244};
-
-static int usb_power_init_inas(struct usb_power_config const *config)
-{
-	struct usb_power_state *state = config->state;
-	int i;
-	int shunt_time = 0;
-	int avg = 0;
-	int target_us = state->integration_us;
-
-	if (state->state != USB_POWER_STATE_SETUP) {
-		CPRINTS("[ERROR] usb_power_init_inas while not SETUP");
-		return -1;
-	}
-
-	/* Find an INA preset integration time less than specified */
-	while (shunt_time < (NELEMS(conversion_time_us) - 1)) {
-		if (conversion_time_us[shunt_time + 1] > target_us)
-			break;
-		shunt_time++;
-	}
-
-	/* Find an averaging setting from the INA presets that fits. */
-	while (avg < (NELEMS(average_settings) - 1)) {
-		if ((conversion_time_us[shunt_time] *
-		     average_settings[avg + 1])
-		    > target_us)
-			break;
-		avg++;
-	}
-
-	state->integration_us =
-		conversion_time_us[shunt_time] * average_settings[avg];
-
-	for (i = 0; i < state->ina_count; i++) {
-		int value;
-		int ret;
-		struct usb_power_ina_cfg *ina = state->ina_cfg + i;
-
-#ifdef USB_POWER_VERBOSE
-		{
-		int conf, cal;
-
-		conf = ina2xx_read(ina->port, ina->addr_flags,
-				   INA231_REG_CONF);
-		cal = ina2xx_read(ina->port, ina->addr_flags,
-				  INA231_REG_CAL);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			conf, cal);
-		}
-#endif
-		/*
-		 * Calculate INA231 Calibration register
-		 * CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
-		 * CurrentLSB 100x uA = 100x 80000000nV / (Rsh mOhm * 0x8000)
-		 */
-		/* TODO: allow voltage readings if no sense resistor. */
-		if (ina->rs == 0)
-			return -1;
-
-		ina->scale = (100 * (80000000 / 0x8000)) / ina->rs;
-
-		/*
-		 * CAL = .00512 / (CurrentLSB * Rsh)
-		 * CAL = 5120000 / (uA * mOhm)
-		 */
-		if (ina->scale == 0)
-			return -1;
-		value = (5120000 * 100) / (ina->scale * ina->rs);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CAL, value);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret);
-			return ret;
-		}
-#ifdef USB_POWER_VERBOSE
-		{
-		int actual;
-
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CAL);
-		CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
-			ina->scale / 100, ina->scale*25/100, value, actual);
-		}
-#endif
-		/* Conversion time, shunt + bus, set average. */
-		value = INA231_CONF_MODE(INA231_MODE_BOTH) |
-			INA231_CONF_SHUNT_TIME(shunt_time) |
-			INA231_CONF_BUS_TIME(shunt_time) |
-			INA231_CONF_AVG(avg);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CONF, value);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret);
-			return ret;
-		}
-#ifdef USB_POWER_VERBOSE
-		{
-		int actual;
-
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CONF);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			value, actual);
-		}
-#endif
-#ifdef USB_POWER_VERBOSE
-		{
-		int busv_mv =
-			(ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_BUSV)
-			 * 125) / 100;
-
-		CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			busv_mv);
-		}
-#endif
-		/* Initialize read from power register. This register address
-		 * will be cached and all ina2xx_readagain() calls will read
-		 * from the same address.
-		 */
-		ina2xx_read(ina->port, ina->addr_flags,
-			    reg_type_mapping(ina->type));
-#ifdef USB_POWER_VERBOSE
-		CPRINTS("[CAP] %d (%d,0x%02x): type:%d", (int)(ina->type));
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-
-/*
- * Read each INA's power integration measurement.
- *
- * INAs recall the most recent address, so no register access write is
- * necessary, simply read 16 bits from each INA and fill the result into
- * the power record.
- *
- * If the power record ringbuffer is full, fail with USB_POWER_ERROR_OVERFLOW.
- */
-static int usb_power_get_samples(struct usb_power_config const *config)
-{
-	uint64_t time = get_time().val;
-	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_head));
-	struct usb_power_ina_cfg *inas = state->ina_cfg;
-	int i;
-
-	/* TODO(nsanders): Would we prefer to evict oldest? */
-	if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count))
-	    == state->reports_xmit_active) {
-		CPRINTS("Overflow! h:%d a:%d t:%d (%d)",
-			state->reports_head, state->reports_xmit_active,
-			state->reports_tail,
-			USB_POWER_MAX_CACHED(state->ina_count));
-		return USB_POWER_ERROR_OVERFLOW;
-	}
-
-	r->status = USB_POWER_SUCCESS;
-	r->size = state->ina_count;
-	if (config->state->wall_offset)
-		time = time + config->state->wall_offset;
-	else
-		time -= config->state->base_time;
-	r->timestamp = time;
-
-	for (i = 0; i < state->ina_count; i++) {
-		int regval;
-		struct usb_power_ina_cfg *ina = inas + i;
-
-		/* Read INA231.
-		 * ina2xx_read(ina->port, ina->addr, INA231_REG_PWR);
-		 * Readagain cached this address so we'll save an I2C
-		 * transaction.
-		 */
-		if (ina->shared)
-			regval = ina2xx_read(ina->port, ina->addr_flags,
-					reg_type_mapping(ina->type));
-		else
-			regval = ina2xx_readagain(ina->port,
-						  ina->addr_flags);
-		r->power[i] = regval;
-#ifdef USB_POWER_VERBOSE
-		{
-		int current;
-		int power;
-		int voltage;
-		int bvoltage;
-
-		voltage = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_RSHV);
-		bvoltage = ina2xx_read(ina->port, ina->addr_flags,
-				       INA231_REG_BUSV);
-		current = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_CURR);
-		power = ina2xx_read(ina->port, ina->addr_flags,
-				    INA231_REG_PWR);
-		{
-		int uV = ((int)voltage * 25) / 10;
-		int mV = ((int)bvoltage * 125) / 100;
-		int uA = (uV * 1000) / ina->rs;
-		int CuA = (((int)current * ina->scale) / 100);
-		int uW = (((int)power * ina->scale*25)/100);
-
-		CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			uV/1000, ina->rs, uA/1000);
-		CPRINTS("[CAP] %duV %dmV %duA %dCuA "
-			"%duW v:%04x, b:%04x, p:%04x",
-			uV, mV, uA, CuA, uW, voltage, bvoltage, power);
-		}
-		}
-#endif
-	}
-
-	/* Mark this slot as used. */
-	state->reports_head = (state->reports_head + 1) %
-		USB_POWER_MAX_CACHED(state->ina_count);
-
-	return EC_SUCCESS;
-}
-
-/*
- * This function is called every [interval] uS, and reads the accumulated
- * values of the INAs, and reschedules itself for the next interval.
- *
- * It will stop collecting frames if a ringbuffer overflow is
- * detected, or a stop request is seen..
- */
-void usb_power_deferred_cap(struct usb_power_config const *config)
-{
-	int ret;
-	uint64_t timeout = get_time().val + config->state->integration_us;
-	uint64_t timein;
-
-	/* Exit if we have stopped capturing in the meantime. */
-	if (config->state->state != USB_POWER_STATE_CAPTURING)
-		return;
-
-	/* Get samples for this timeslice */
-	ret = usb_power_get_samples(config);
-	if (ret == USB_POWER_ERROR_OVERFLOW) {
-		CPRINTS("[CAP] usb_power_deferred_cap: OVERFLOW");
-		return;
-	}
-
-	/* Calculate time remaining until next slice. */
-	timein = get_time().val;
-	if (timeout > timein)
-		timeout = timeout - timein;
-	else
-		timeout = 0;
-
-	/* Double check if we are still capturing. */
-	if (config->state->state == USB_POWER_STATE_CAPTURING)
-		hook_call_deferred(config->deferred_cap, timeout);
-}
-
diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h
deleted file mode 100644
index 68b7f75ca2..0000000000
--- a/chip/stm32/usb_power.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_POWER_H
-#define __CROS_EC_USB_POWER_H
-
-/* Power monitoring USB interface for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * Command:
- *
- *     Commands are a 16 bit value, with optional command dependent data.
- *     +--------------+-----------------------------------+
- *     | command : 2B |					  |
- *     +--------------+-----------------------------------+
- *
- *     Responses are an 8 bit status value, with optional data.
- *     +----------+-----------------------------------+
- *     | res : 1B |				      |
- *     +----------+-----------------------------------+
- *
- *     reset:	0x0000
- *     +--------+
- *     | 0x0000 |
- *     +--------+
- *
- *     stop:	0x0001
- *     +--------+
- *     | 0x0001 |
- *     +--------+
- *
- *     addina:	0x0002
- *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs |
- *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *
- *     start:	0x0003
- *     +--------+----------------------+
- *     | 0x0003 | 4B: integration time |
- *     +--------+----------------------+
- *
- *     start response:
- *     +-------------+-----------------------------+
- *     | status : 1B | Actual integration time: 4B |
- *     +-------------+-----------------------------+
- *
- *     next:	0x0004
- *     +--------+
- *     | 0x0004 |
- *     +--------+
- *
- *     next response:
- *     +-------------+----------+----------------+----------------------------+
- *     | status : 1B | size: 1B | timestamp : 8B | payload : may span packets |
- *     +-------------+----------+----------------+----------------------------+
- *
- *     settime:	0x0005
- *     +--------+---------------------+
- *     | 0x0005 | 8B: Wall clock time |
- *     +--------+---------------------+
- *
- *
- *     Status: 1 byte status
- *
- *	 0x00: Success
- *	 0x01: I2C Error
- *	 0x02: Overflow
- *	     This can happen if data acquisition is faster than USB reads.
- *	 0x03: No configuration set.
- *	 0x04: No active capture.
- *	 0x05: Timeout.
- *	 0x06: Busy, outgoing queue is empty.
- *	 0x07: Size, command length is incorrect for command type..
- *	 0x08: More INAs specified than board limit.
- *	 0x09: Invalid input, eg. invalid INA type.
- *	 0x80: Unknown error
- *
- *     size: 1 byte incoming INA reads count
- *
- *     timestamp: 4 byte timestamp associated with these samples
- *
- */
-
-/* 8b status field. */
-enum usb_power_error {
-	USB_POWER_SUCCESS		= 0x00,
-	USB_POWER_ERROR_I2C		= 0x01,
-	USB_POWER_ERROR_OVERFLOW	= 0x02,
-	USB_POWER_ERROR_NOT_SETUP	= 0x03,
-	USB_POWER_ERROR_NOT_CAPTURING	= 0x04,
-	USB_POWER_ERROR_TIMEOUT		= 0x05,
-	USB_POWER_ERROR_BUSY		= 0x06,
-	USB_POWER_ERROR_READ_SIZE	= 0x07,
-	USB_POWER_ERROR_FULL		= 0x08,
-	USB_POWER_ERROR_INVAL		= 0x09,
-	USB_POWER_ERROR_UNKNOWN		= 0x80,
-};
-
-/* 16b command field. */
-enum usb_power_command {
-	USB_POWER_CMD_RESET	= 0x0000,
-	USB_POWER_CMD_STOP	= 0x0001,
-	USB_POWER_CMD_ADDINA	= 0x0002,
-	USB_POWER_CMD_START	= 0x0003,
-	USB_POWER_CMD_NEXT	= 0x0004,
-	USB_POWER_CMD_SETTIME	= 0x0005,
-};
-
-/* Addina "INA Type" field. */
-enum usb_power_ina_type {
-	USBP_INA231_POWER	= 0x01,
-	USBP_INA231_BUSV	= 0x02,
-	USBP_INA231_CURRENT	= 0x03,
-	USBP_INA231_SHUNTV	= 0x04,
-};
-
-/* Internal state machine values */
-enum usb_power_states {
-	USB_POWER_STATE_OFF	= 0,
-	USB_POWER_STATE_SETUP,
-	USB_POWER_STATE_CAPTURING,
-};
-
-#define USB_POWER_MAX_READ_COUNT 64
-#define USB_POWER_MIN_CACHED 10
-
-struct usb_power_ina_cfg {
-	/*
-	 * Relevant config for INA usage.
-	 */
-	/* i2c bus. TODO(nsanders): specify what kind of index. */
-	int port;
-	/* 7-bit i2c addr */
-	uint16_t addr_flags;
-
-	/* Base voltage. mV */
-	int mv;
-
-	/* Shunt resistor. mOhm */
-	int rs;
-	/* uA per div as reported from INA */
-	int scale;
-
-	/* Is this power, shunt voltage, bus voltage, or current? */
-	int type;
-	/* Is this INA returning the one value only and can use readagain? */
-	int shared;
-};
-
-
-struct __attribute__ ((__packed__)) usb_power_report {
-	uint8_t status;
-	uint8_t size;
-	uint64_t timestamp;
-	uint16_t power[USB_POWER_MAX_READ_COUNT];
-};
-
-/* Must be 4 byte aligned */
-#define USB_POWER_RECORD_SIZE(ina_count)				\
-	((((sizeof(struct usb_power_report)				\
-	- (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT)			\
-	+ (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4)
-
-#define USB_POWER_DATA_SIZE						\
-	(sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1))
-#define USB_POWER_MAX_CACHED(ina_count)					\
-	(USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count))
-
-
-struct usb_power_state {
-	/*
-	 * The power data acquisition must be setup, then started, in order to
-	 * return data.
-	 * States are OFF, SETUP, and CAPTURING.
-	 */
-	int state;
-
-	struct usb_power_ina_cfg ina_cfg[USB_POWER_MAX_READ_COUNT];
-	int ina_count;
-	int integration_us;
-	/* Start of sampling. */
-	uint64_t base_time;
-	/* Offset between microcontroller timestamp and host wall clock. */
-	uint64_t wall_offset;
-
-	/* Cached power reports for sending on USB. */
-	/* Actual backing data for variable sized record queue. */
-	uint8_t reports_data_area[USB_POWER_DATA_SIZE];
-	/* Size of power report struct for this config. */
-	int stride_bytes;
-	/* Max power records storeable in this config */
-	int max_cached;
-	struct usb_power_report *reports;
-
-	/* Head and tail pointers for output ringbuffer */
-	/* Head adds newly probed power data. */
-	int reports_head;
-	/* Tail contains oldest records not yet sent to USB */
-	int reports_tail;
-	/* Xmit_active -> tail is active usb DMA */
-	int reports_xmit_active;
-
-	/* Pointers to RAM. */
-	uint8_t rx_buf[USB_MAX_PACKET_SIZE];
-	uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4];
-};
-
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_power_config {
-	/* In RAM state of the USB power interface. */
-	struct usb_power_state *state;
-
-	/* USB endpoint state.*/
-	struct dwc_usb_ep *ep;
-
-	/* Interface and endpoint indicies. */
-	int interface;
-	int endpoint;
-
-	/* Deferred function to call to handle power request. */
-	const struct deferred_data *deferred;
-	const struct deferred_data *deferred_cap;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_start {
-	uint16_t command;
-	uint32_t integration_us;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_addina {
-	uint16_t command;
-	uint8_t port;
-	uint8_t type;
-	uint8_t addr_flags;
-	uint8_t extra;
-	uint32_t rs;
-};
-
-struct __attribute__ ((__packed__)) usb_power_command_settime {
-	uint16_t command;
-	uint64_t time;
-};
-
-union usb_power_command_data {
-	uint16_t command;
-	struct usb_power_command_start start;
-	struct usb_power_command_addina addina;
-	struct usb_power_command_settime settime;
-};
-
-
-/*
- * Convenience macro for defining a USB INA Power driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_power_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- */
-#define USB_POWER_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT)					\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	static void CONCAT2(NAME, _deferred_cap_)(void);		\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));		\
-	struct usb_power_state CONCAT2(NAME, _state_) = {		\
-		.state = USB_POWER_STATE_OFF,				\
-		.ina_count = 0,						\
-		.integration_us = 0,					\
-		.reports_head = 0,					\
-		.reports_tail = 0,					\
-		.wall_offset = 0,					\
-	};								\
-	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {		\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = 0,					\
-		.out_databuffer_max = 0,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = 0,					\
-		.in_databuffer_max = 0,					\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	struct usb_power_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.ep	= &CONCAT2(NAME, _ep_ctl),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred_cap  = &CONCAT2(NAME, _deferred_cap__data),	\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength	    = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,	\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,	\
-		.iInterface	 = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 1,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_epN_tx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_epN_rx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-			usb_power_event(&NAME, evt);			\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ usb_power_deferred_tx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ usb_power_deferred_rx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_cap_)(void)			\
-	{ usb_power_deferred_cap(&NAME); }
-
-
-/*
- * Handle power request in a deferred callback.
- */
-void usb_power_deferred_rx(struct usb_power_config const *config);
-void usb_power_deferred_tx(struct usb_power_config const *config);
-void usb_power_deferred_cap(struct usb_power_config const *config);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_power_tx(struct usb_power_config const *config);
-void usb_power_rx(struct usb_power_config const *config);
-void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt);
-
-
-
-
-#endif /* __CROS_EC_USB_DWC_POWER_H */
-
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
deleted file mode 100644
index 54caae015e..0000000000
--- a/chip/stm32/usb_spi.c
+++ /dev/null
@@ -1,627 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "spi.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "usb_spi.h"
-#include "util.h"
-
-/* Forward declare platform specific functions. */
-static bool usb_spi_received_packet(struct usb_spi_config const *config);
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config);
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
-
-/*
- * Map EC error codes to USB_SPI error codes.
- *
- * @param error     EC error code
- *
- * @returns         USB SPI error code based on the mapping.
- */
-static int16_t usb_spi_map_error(int error)
-{
-	switch (error) {
-	case EC_SUCCESS:       return USB_SPI_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_SPI_BUSY;
-	default:               return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
-	}
-}
-
-/*
- * Read data into the receive buffer.
- *
- * @param dst       Destination receive context we are writing data to.
- * @param src       Source packet context we are reading data from.
- *
- * @returns         USB_SPI_RX_DATA_OVERFLOW if the source packet is too large
- */
-static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
-				const struct usb_spi_packet_ctx *src)
-{
-	size_t max_read_length = dst->transfer_size - dst->transfer_index;
-	size_t bytes_in_buffer = src->packet_size - src->header_size;
-	const uint8_t *packet_buffer = src->bytes + src->header_size;
-
-	if (bytes_in_buffer > max_read_length) {
-		/*
-		 * An error occurred, we should not receive more data than
-		 * the buffer can support.
-		 */
-		return USB_SPI_RX_DATA_OVERFLOW;
-	}
-	memcpy(dst->buffer + dst->transfer_index, packet_buffer,
-		bytes_in_buffer);
-
-	dst->transfer_index += bytes_in_buffer;
-	return USB_SPI_SUCCESS;
-}
-
-/*
- * Fill the USB packet with data from the transmit buffer.
- *
- * @param dst       Destination packet context we are writing data to.
- * @param src       Source transmit context we are reading data from.
- */
-static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
-				struct usb_spi_transfer_ctx *src)
-{
-	size_t transfer_size = src->transfer_size - src->transfer_index;
-	size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size;
-	uint8_t *packet_buffer = dst->bytes + dst->header_size;
-
-	if (transfer_size > max_buffer_size)
-		transfer_size = max_buffer_size;
-
-	memcpy(packet_buffer, src->buffer + src->transfer_index, transfer_size);
-
-	dst->packet_size = dst->header_size + transfer_size;
-	src->transfer_index += transfer_size;
-}
-
-/*
- * Setup the USB SPI state to start a new SPI transfer.
- *
- * @param config        USB SPI config
- * @param write_count   Number of bytes to write in the SPI transfer
- * @param read_count    Number of bytes to read in the SPI transfer
- */
-static void usb_spi_setup_transfer(struct usb_spi_config const *config,
-				size_t write_count, size_t read_count)
-{
-	/* Reset any status code. */
-	config->state->status_code = USB_SPI_SUCCESS;
-
-	/* Reset the write and read counts. */
-	config->state->spi_write_ctx.transfer_size = write_count;
-	config->state->spi_write_ctx.transfer_index = 0;
-	config->state->spi_read_ctx.transfer_size = read_count;
-	config->state->spi_read_ctx.transfer_index = 0;
-}
-
-/*
- * Handle USB events that will reset the USB SPI state.
- *
- * @param config        USB SPI config
- */
-static void usb_spi_reset_interface(struct usb_spi_config const *config)
-{
-	/* Setup a 0 byte transfer to clear the contexts. */
-	usb_spi_setup_transfer(config, 0, 0);
-}
-
-/*
- * Returns if the response transfer is in progress.
- *
- * @param config        USB SPI config
- *
- * @returns         	True if a response transfer is in progress.
- */
-static bool usb_spi_response_in_progress(struct usb_spi_config const *config)
-{
-	if ((config->state->mode == USB_SPI_MODE_START_RESPONSE) ||
-	    (config->state->mode == USB_SPI_MODE_CONTINUE_RESPONSE)) {
-		return true;
-	}
-	return false;
-}
-
-/*
- * Prep the state to construct a new response. This sets the transfer
- * contexts, the mode, and status code. If a non-zero status code is
- * returned, then no payload will be transmitted.
- *
- * @param config        USB SPI config
- * @param status_code	status code to set for the response.
- */
-static void setup_transfer_response(struct usb_spi_config const *config,
-				uint16_t status_code)
-{
-	config->state->status_code = status_code;
-	config->state->spi_read_ctx.transfer_index = 0;
-	config->state->mode = USB_SPI_MODE_START_RESPONSE;
-
-	/* If an error occurred, transmit an empty start packet. */
-	if (status_code != USB_SPI_SUCCESS)
-		config->state->spi_read_ctx.transfer_size = 0;
-}
-
-/*
- * Constructs the response packet containing the SPI configuration.
- *
- * @param config        USB SPI config
- * @param packet        Packet buffer we will be transmitting.
- */
-static void create_spi_config_response(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	/* Construct the response packet. */
-	packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG;
-	packet->rsp_config.max_write_count = USB_SPI_MAX_WRITE_COUNT;
-	packet->rsp_config.max_read_count = USB_SPI_MAX_READ_COUNT;
-	/* Set the feature flags. */
-	packet->rsp_config.feature_bitmap = 0;
-#ifndef CONFIG_SPI_HALFDUPLEX
-	packet->rsp_config.feature_bitmap |=
-		USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED;
-#endif
-	packet->packet_size =
-		sizeof(struct usb_spi_response_configuration_v2);
-}
-
-/*
- * If we have a transfer response in progress, this will construct the
- * next entry. If no transfer is in progress or if we are unable to
- * create the next packet, it will not modify tx_packet.
- *
- * @param config        USB SPI config
- * @param packet        Packet buffer we will be transmitting.
- */
-static void usb_spi_create_spi_transfer_response(
-				struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *transmit_packet)
-{
-
-	if (!usb_spi_response_in_progress(config))
-		return;
-
-	if (config->state->spi_read_ctx.transfer_index == 0) {
-
-		/* Transmit the first packet with the status code. */
-		transmit_packet->header_size =
-			offsetof(struct usb_spi_response_v2, data);
-		transmit_packet->rsp_start.packet_id =
-			USB_SPI_PKT_ID_RSP_TRANSFER_START;
-		transmit_packet->rsp_start.status_code =
-			config->state->status_code;
-
-		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
-	} else if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-
-		/* Transmit the continue packets. */
-		transmit_packet->header_size =
-			offsetof(struct usb_spi_continue_v2, data);
-		transmit_packet->rsp_continue.packet_id =
-			USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE;
-		transmit_packet->rsp_continue.data_index =
-			config->state->spi_read_ctx.transfer_index;
-
-		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
-	}
-	if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-		config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE;
-	} else {
-		config->state->mode = USB_SPI_MODE_IDLE;
-	}
-}
-
-/*
- * Process the rx packet.
- *
- * @param config        USB SPI config
- * @param packet        Received packet to process.
- */
-static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) {
-		/* No valid packet exists smaller than the packet id. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
-		return;
-	}
-	/* Reset the mode until we've processed the packet. */
-	config->state->mode = USB_SPI_MODE_IDLE;
-
-	switch (packet->packet_id) {
-	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG:
-	{
-		/* The host requires the SPI configuration. */
-		config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION;
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE:
-	{
-		/*
-		 * The host has requested the device restart the last response.
-		 * This is used to recover from lost USB packets without
-		 * duplicating SPI transfers.
-		 */
-		setup_transfer_response(config, config->state->status_code);
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_START:
-	{
-		/* The host started a new USB SPI transfer */
-		size_t write_count = packet->cmd_start.write_count;
-		size_t read_count = packet->cmd_start.read_count;
-
-		if (!config->state->enabled) {
-			setup_transfer_response(config, USB_SPI_DISABLED);
-		} else if (write_count > USB_SPI_MAX_WRITE_COUNT) {
-			setup_transfer_response(config,
-				USB_SPI_WRITE_COUNT_INVALID);
-		} else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-#ifndef CONFIG_SPI_HALFDUPLEX
-			/* Full duplex mode is not supported on this device. */
-			setup_transfer_response(config,
-				USB_SPI_UNSUPPORTED_FULL_DUPLEX);
-#endif
-		} else if (read_count > USB_SPI_MAX_READ_COUNT &&
-				read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
-			setup_transfer_response(config,
-				USB_SPI_READ_COUNT_INVALID);
-		} else {
-		        usb_spi_setup_transfer(config, write_count, read_count);
-		        packet->header_size =
-		        	offsetof(struct usb_spi_command_v2, data);
-		        config->state->status_code = usb_spi_read_usb_packet(
-		        	&config->state->spi_write_ctx, packet);
-		}
-
-		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
-			break;
-		}
-
-		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
-		}
-
-		break;
-	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE:
-	{
-		/*
-		 * The host has sent a continue packet for the SPI transfer
-		 * which contains additional data payload.
-		 */
-		packet->header_size =
-			offsetof(struct usb_spi_continue_v2, data);
-		if (config->state->status_code == USB_SPI_SUCCESS) {
-			config->state->status_code = usb_spi_read_usb_packet(
-					&config->state->spi_write_ctx, packet);
-		}
-
-		/* Send responses if we encountered an error. */
-		if (config->state->status_code != USB_SPI_SUCCESS) {
-			setup_transfer_response(config,
-				config->state->status_code);
-			break;
-		}
-
-		/* Start the SPI transfer when we've read all data. */
-		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
-			config->state->mode = USB_SPI_MODE_START_SPI;
-		}
-
-		break;
-	}
-	default:
-	{
-		/* An unknown USB packet was delivered. */
-		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
-		break;
-	}
-	}
-}
-
-/* Deferred function to handle state changes, process USB SPI packets,
- * and construct responses.
- *
- * @param config        USB SPI config
- */
-void usb_spi_deferred(struct usb_spi_config const *config)
-{
-	int enabled;
-	struct usb_spi_packet_ctx *receive_packet =
-		&config->state->receive_packet;
-	struct usb_spi_packet_ctx *transmit_packet =
-		&config->state->transmit_packet;
-	transmit_packet->packet_size = 0;
-
-	if (config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE)
-		enabled = config->state->enabled_device;
-	else
-		enabled = config->state->enabled_device &&
-			  config->state->enabled_host;
-
-	/*
-	 * If our overall enabled state has changed we call the board specific
-	 * enable or disable routines and save our new state.
-	 */
-	if (enabled != config->state->enabled) {
-		if (enabled) usb_spi_board_enable(config);
-		else         usb_spi_board_disable(config);
-
-		config->state->enabled = enabled;
-	}
-
-	/* Read any packets from the endpoint. */
-
-	usb_spi_read_packet(config, receive_packet);
-	if (receive_packet->packet_size) {
-		usb_spi_process_rx_packet(config, receive_packet);
-	}
-
-	/* Need to send the USB SPI configuration */
-	if (config->state->mode == USB_SPI_MODE_SEND_CONFIGURATION) {
-		create_spi_config_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
-		config->state->mode = USB_SPI_MODE_IDLE;
-		return;
-	}
-
-	/* Start a new SPI transfer. */
-	if (config->state->mode == USB_SPI_MODE_START_SPI) {
-		uint16_t status_code;
-		int read_count = config->state->spi_read_ctx.transfer_size;
-#ifndef CONFIG_SPI_HALFDUPLEX
-		/*
-		 * Handle the full duplex mode on supported platforms.
-		 * The read count is equal to the write count.
-		 */
-		if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
-			config->state->spi_read_ctx.transfer_size =
-				config->state->spi_write_ctx.transfer_size;
-			read_count = SPI_READBACK_ALL;
-		}
-#endif
-		status_code = spi_transaction(SPI_FLASH_DEVICE,
-			config->state->spi_write_ctx.buffer,
-			config->state->spi_write_ctx.transfer_size,
-			config->state->spi_read_ctx.buffer,
-			read_count);
-
-		/* Cast the EC status code to USB SPI and start the response. */
-		status_code = usb_spi_map_error(status_code);
-		setup_transfer_response(config, status_code);
-	}
-
-	if (usb_spi_response_in_progress(config) &&
-			usb_spi_transmitted_packet(config)) {
-		usb_spi_create_spi_transfer_response(config, transmit_packet);
-		usb_spi_write_packet(config, transmit_packet);
-	}
-}
-
-/*
- * Sets which SPI modes will be enabled
- *
- * @param config        USB SPI config
- * @param enabled       usb_spi_request indicating which SPI mode is enabled.
- */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled)
-{
-	config->state->enabled_device = enabled;
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Receive the data from the endpoint into the packet and
- *  mark the endpoint as ready to accept more data.
- *
- * @param config        USB SPI config
- * @param packet        Destination packet used to store the endpoint data.
- */
-static void usb_spi_read_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	size_t packet_size;
-
-	if (!usb_spi_received_packet(config)) {
-		/* No data is present on the endpoint. */
-		packet->packet_size = 0;
-		return;
-	}
-
-	/* Copy bytes from endpoint memory. */
-	packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
-	memcpy_from_usbram(packet->bytes,
-		(void *)usb_sram_addr(config->ep_rx_ram), packet_size);
-	packet->packet_size = packet_size;
-	/* Set endpoint as valid for accepting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
-}
-
-/*
- * STM32 Platform: Transmit data from the packet to the endpoint buffer.
- *  If a packet is written, the endpoint will be marked valid for transmitting.
- *
- * @param config        USB SPI config
- * @param packet        Source packet we will write to the endpoint data.
- */
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
-{
-	if (packet->packet_size == 0)
-		return;
-
-	/* Copy bytes to endpoint memory. */
-	memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram),
-		packet->bytes, packet->packet_size);
-	btable_ep[config->endpoint].tx_count = packet->packet_size;
-
-	/* Mark the packet as having no data. */
-	packet->packet_size = 0;
-
-	/* Set endpoint as valid for transmitting new packet. */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
-}
-
-/*
- * STM32 Platform: Returns the RX endpoint status
- *
- * @param config        USB SPI config
- *
- * @returns             Returns true when the RX endpoint has a packet.
- */
-static bool usb_spi_received_packet(struct usb_spi_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) != EP_RX_VALID;
-}
-
-/* STM32 Platform: Returns the TX endpoint status
- *
- * @param config        USB SPI config
- *
- * @returns             Returns true when the TX endpoint transmitted
- *                      the packet written.
- */
-static bool usb_spi_transmitted_packet(struct usb_spi_config const *config)
-{
-	return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) != EP_TX_VALID;
-}
-
-/* STM32 Platform: Handle interrupt for USB data received.
- *
- * @param config        USB SPI config
- */
-void usb_spi_rx(struct usb_spi_config const *config)
-{
-	/*
-	 * We need to set both the TX and RX endpoints to NAK to prevent
-	 * transfers. The protocol requires responses to follow a command, but
-	 * the USB host will request the next packet from the TX endpoint
-	 * before the USB SPI has updated the memory in the buffer. By setting
-	 * it to NAK in the ISR, it will not perform a transfer until the
-	 * next packet is ready.
-	 *
-	 * This has a side effect of disabling the endpoint interrupts until
-	 * they are set to valid or a USB reset events occurs.
-	 */
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_RX_MASK, EP_TX_RX_NAK, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Handle interrupt for USB data transmitted.
- *
- * @param config        USB SPI config
- */
-void usb_spi_tx(struct usb_spi_config const *config)
-{
-	STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_NAK, 0);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-/*
- * STM32 Platform: Handle interrupt for USB events
- *
- * @param config        USB SPI config
- * @param evt           USB event
- */
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
-{
-	int endpoint;
-
-	if (evt != USB_EVENT_RESET)
-		return;
-
-	endpoint = config->endpoint;
-
-	usb_spi_reset_interface(config);
-
-	btable_ep[endpoint].tx_addr  = usb_sram_addr(config->ep_tx_ram);
-	btable_ep[endpoint].tx_count = 0;
-
-	btable_ep[endpoint].rx_addr  = usb_sram_addr(config->ep_rx_ram);
-	btable_ep[endpoint].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
-
-	STM32_USB_EP(endpoint) = ((endpoint <<  0) | /* Endpoint Addr*/
-				  (2        <<  4) | /* TX NAK */
-				  (0        <<  9) | /* Bulk EP */
-				  (3        << 12)); /* RX Valid */
-}
-
-/*
- * STM32 Platform: Handle control transfers.
- *
- * @param config        USB SPI config
- * @param rx_buf        Contains setup packet
- * @param tx_buf        unused
- */
-int usb_spi_interface(struct usb_spi_config const *config,
-		      usb_uint *rx_buf,
-		      usb_uint *tx_buf)
-{
-	struct usb_setup_packet setup;
-
-	usb_read_setup_packet(rx_buf, &setup);
-
-	if (setup.bmRequestType != (USB_DIR_OUT |
-				    USB_TYPE_VENDOR |
-				    USB_RECIP_INTERFACE))
-		return 1;
-
-	if (setup.wValue  != 0 ||
-	    setup.wIndex  != config->interface ||
-	    setup.wLength != 0)
-		return 1;
-
-	switch (setup.bRequest) {
-	case USB_SPI_REQ_ENABLE:
-		config->state->enabled_host = 1;
-		break;
-
-	case USB_SPI_REQ_DISABLE:
-		config->state->enabled_host = 0;
-		break;
-
-	default: return 1;
-	}
-
-	/*
-	 * Our state has changed, call the deferred function to handle the
-	 * state change.
-	 */
-	if (!(config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE))
-		hook_call_deferred(config->deferred, 0);
-
-	usb_spi_reset_interface(config);
-
-	btable_ep[0].tx_count = 0;
-	STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT);
-	return 0;
-}
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
deleted file mode 100644
index 591975234d..0000000000
--- a/chip/stm32/usb_spi.h
+++ /dev/null
@@ -1,594 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_SPI_H
-#define __CROS_EC_USB_SPI_H
-
-/* STM32 USB SPI driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/*
- * This SPI flash programming interface is designed to talk to a Chromium OS
- * device over a Raiden USB connection.
- *
- * USB SPI Version 2:
- *
- *     USB SPI version 2 adds support for larger SPI transfers and reduces the
- *     number of USB packets transferred. This improves performance when
- *     writing or reading large chunks of memory from a device. A packet ID
- *     field is used to distinguish the different packet types. Additional
- *     packets have been included to query the device for its configuration
- *     allowing the interface to be used on platforms with different SPI
- *     limitations. It includes validation and a packet to recover from the
- *     situations where USB packets are lost.
- *
- *     The USB SPI hosts which support packet version 2 are backwards compatible
- *     and use the bInterfaceProtocol field to identify which type of target
- *     they are connected to.
- *
- *
- * Example: USB SPI request with 128 byte write and 0 byte read.
- *
- *      Packet #1 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *           write count = 128
- *           read count  = 0
- *           payload     = First 58 bytes from the write buffer,
- *                            starting at byte 0 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #2 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *           data index  = 58
- *           payload     = Next 60 bytes from the write buffer,
- *                           starting at byte 58 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #3 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *           data index  = 118
- *           payload     = Next 10 bytes from the write buffer,
- *                           starting at byte 118 in the buffer
- *           packet size = 14 bytes
- *
- *      Packet #4 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *           status code = status code from device
- *           payload     = 0 bytes
- *           packet size = 4 bytes
- *
- * Example: USB SPI request with 2 byte write and 100 byte read.
- *
- *      Packet #1 Host to Device:
- *           packet id   = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *           write count = 2
- *           read count  = 100
- *           payload     = The 2 byte write buffer
- *           packet size = 8 bytes
- *
- *      Packet #2 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *           status code = status code from device
- *           payload     = First 60 bytes from the read buffer,
- *                            starting at byte 0 in the buffer
- *           packet size = 64 bytes
- *
- *      Packet #3 Device to Host:
- *           packet id   = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *           data index  = 60
- *           payload     = Next 40 bytes from the read buffer,
- *                           starting at byte 60 in the buffer
- *           packet size = 44 bytes
- *
- *
- * Message Packets:
- *
- * Command Start Packet (Host to Device):
- *
- *      Start of the USB SPI command, contains the number of bytes to write
- *      and read on SPI and up to the first 58 bytes of write payload.
- *      Longer writes will use the continue packets with packet id
- *      USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE to transmit the remaining data.
- *
- *     +----------------+------------------+-----------------+---------------+
- *     | packet id : 2B | write count : 2B | read count : 2B | w.p. : <= 58B |
- *     +----------------+------------------+-----------------+---------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    Valid values packet id = USB_SPI_PKT_ID_CMD_TRANSFER_START
- *
- *     write count:   2 byte, zero based count of bytes to write
- *
- *     read count:    2 byte, zero based count of bytes to read
- *                    UINT16_MAX indicates full duplex mode with a read count
- *                    equal to the write count.
- *
- *     write payload: Up to 58 bytes of data to write to SPI, the total
- *                    length of all TX packets must match write count.
- *                    Due to data alignment constraints, this must be an
- *                    even number of bytes unless this is the final packet.
- *
- *
- * Response Start Packet (Device to Host):
- *
- *      Start of the USB SPI response, contains the status code and up to
- *      the first 60 bytes of read payload. Longer reads will use the
- *      continue packets with packet id USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *      to transmit the remaining data.
- *
- *     +----------------+------------------+-----------------------+
- *     | packet id : 2B | status code : 2B | read payload : <= 60B |
- *     +----------------+------------------+-----------------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    Valid values packet id = USB_SPI_PKT_ID_RSP_TRANSFER_START
- *
- *     status code: 2 byte status code
- *         0x0000: Success
- *         0x0001: SPI timeout
- *         0x0002: Busy, try again
- *             This can happen if someone else has acquired the shared memory
- *             buffer that the SPI driver uses as /dev/null
- *         0x0003: Write count invalid. The byte limit is platform specific
- *             and is set during the configure USB SPI response.
- *         0x0004: Read count invalid. The byte limit is platform specific
- *             and is set during the configure USB SPI response.
- *         0x0005: The SPI bridge is disabled.
- *         0x0006: The RX continue packet's data index is invalid. This
- *             can indicate a USB transfer failure to the device.
- *         0x0007: The RX endpoint has received more data than write count.
- *             This can indicate a USB transfer failure to the device.
- *         0x0008: An unexpected packet arrived that the device could not
- *             process.
- *         0x0009: The device does not support full duplex mode.
- *         0x8000: Unknown error mask
- *             The bottom 15 bits will contain the bottom 15 bits from the EC
- *             error code.
- *
- *     read payload: Up to 60 bytes of data read from SPI, the total
- *                   length of all RX packets must match read count
- *                   unless an error status was returned. Due to data
- *                   alignment constraints, this must be a even number
- *                   of bytes unless this is the final packet.
- *
- *
- * Continue Packet (Bidirectional):
- *
- *      Continuation packet for the writes and read buffers. Both packets
- *      follow the same format, a data index counts the number of bytes
- *      previously transferred in the USB SPI transfer and a payload of bytes.
- *
- *     +----------------+-----------------+-------------------------------+
- *     | packet id : 2B | data index : 2B | write / read payload : <= 60B |
- *     +----------------+-----------------+-------------------------------+
- *
- *     packet id:     2 byte enum defined by packet_id_type
- *                    The packet id has 2 values depending on direction:
- *                    packet id = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE
- *                    indicates the packet is being transmitted from the host
- *                    to the device and contains SPI write payload.
- *                    packet id = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE
- *                    indicates the packet is being transmitted from the device
- *                    to the host and contains SPI read payload.
- *
- *     data index:    The data index indicates the number of bytes in the
- *                    read or write buffers that have already been transmitted.
- *                    It is used to validate that no packets have been dropped
- *                    and that the prior packets have been correctly decoded.
- *                    This value corresponds to the offset bytes in the buffer
- *                    to start copying the payload into.
- *
- *     read and write payload:
- *                    Contains up to 60 bytes of payload data to transfer to
- *                    the SPI write buffer or from the SPI read buffer.
- *
- *
- * Command Get Configuration Packet (Host to Device):
- *
- *      Query the device to request it's USB SPI configuration indicating
- *      the number of bytes it can write and read.
- *
- *     +----------------+
- *     | packet id : 2B |
- *     +----------------+
- *
- *     packet id:     2 byte enum USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG
- *
- * Response Configuration Packet (Device to Host):
- *
- *      Response packet form the device to report the maximum write and
- *      read size supported by the device.
- *
- *     +----------------+----------------+---------------+----------------+
- *     | packet id : 2B | max write : 2B | max read : 2B | feature bitmap |
- *     +----------------+----------------+---------------+----------------+
- *
- *     packet id:         2 byte enum USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG
- *
- *     max write count:   2 byte count of the maximum number of bytes
- *                        the device can write to SPI in one transaction.
- *
- *     max read count:    2 byte count of the maximum number of bytes
- *                        the device can read from SPI in one transaction.
- *
- *     feature bitmap:    Bitmap of supported features.
- *                        BIT(0): Full duplex SPI mode is supported
- *                        BIT(1:15): Reserved for future use
- *
- * Command Restart Response Packet (Host to Device):
- *
- *      Command to restart the response transfer from the device. This enables
- *      the host to recover from a lost packet when reading the response
- *      without restarting the SPI transfer.
- *
- *     +----------------+
- *     | packet id : 2B |
- *     +----------------+
- *
- *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE
- *
- * USB Error Codes:
- *
- * send_command return codes have the following format:
- *
- *     0x00000:         Status code success.
- *     0x00001-0x0FFFF: Error code returned by the USB SPI device.
- *     0x10001-0x1FFFF: USB SPI Host error codes
- *     0x20001-0x20063  Lower bits store the positive value representation
- *                      of the libusb_error enum. See the libusb documentation:
- *                      http://libusb.sourceforge.net/api-1.0/group__misc.html
- */
-
-#define USB_SPI_FULL_DUPLEX_ENABLED         (UINT16_MAX)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_START       (58)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE    (60)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE    (60)
-
-#define USB_SPI_PAYLOAD_SIZE_V2_ERROR       (60)
-
-#define USB_SPI_MIN_PACKET_SIZE             (2)
-
-enum packet_id_type {
-	/* Request USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0,
-	/* USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG     = 1,
-	/*
-	 * Start a USB SPI transfer specifying number of bytes to write,
-	 * read and deliver first packet of data to write.
-	 */
-	USB_SPI_PKT_ID_CMD_TRANSFER_START     = 2,
-	/* Additional packets containing write payload. */
-	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE  = 3,
-	/*
-	 * Request the device restart the response enabling us to recover
-	 * from packet loss without another SPI transfer.
-	 */
-	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE   = 4,
-	/*
-	 * First packet of USB SPI response with the status code
-	 * and read payload if it was successful.
-	 */
-	USB_SPI_PKT_ID_RSP_TRANSFER_START     = 5,
-	/* Additional packets containing read payload. */
-	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE  = 6,
-};
-
-enum feature_bitmap {
-	/* Indicates the platform supports full duplex mode. */
-	USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED = BIT(0)
-};
-
-struct usb_spi_response_configuration_v2 {
-	uint16_t packet_id;
-	uint16_t max_write_count;
-	uint16_t max_read_count;
-	uint16_t feature_bitmap;
-} __packed;
-
-struct usb_spi_command_v2 {
-	uint16_t packet_id;
-	uint16_t write_count;
-	/* UINT16_MAX Indicates readback all on halfduplex compliant devices. */
-	uint16_t read_count;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_START];
-} __packed;
-
-struct usb_spi_response_v2 {
-	uint16_t packet_id;
-	uint16_t status_code;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_RESPONSE];
-} __packed;
-
-struct usb_spi_continue_v2 {
-	uint16_t packet_id;
-	uint16_t data_index;
-	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE];
-} __packed;
-
-struct usb_spi_packet_ctx {
-	union {
-		uint8_t bytes[USB_MAX_PACKET_SIZE];
-		uint16_t packet_id;
-		struct usb_spi_command_v2 cmd_start;
-		struct usb_spi_continue_v2 cmd_continue;
-		struct usb_spi_response_configuration_v2 rsp_config;
-		struct usb_spi_response_v2 rsp_start;
-		struct usb_spi_continue_v2 rsp_continue;
-	} __packed;
-	/*
-	 * By storing the number of bytes in the header and knowing that the
-	 * USB data packets are all 64B long, we are able to use the header
-	 * size to store the offset of the buffer and it's size without
-	 * duplicating variables that can go out of sync.
-	 */
-	size_t header_size;
-	/* Number of bytes in the packet. */
-	size_t packet_size;
-};
-
-enum usb_spi_error {
-	USB_SPI_SUCCESS                 = 0x0000,
-	USB_SPI_TIMEOUT                 = 0x0001,
-	USB_SPI_BUSY                    = 0x0002,
-	USB_SPI_WRITE_COUNT_INVALID     = 0x0003,
-	USB_SPI_READ_COUNT_INVALID      = 0x0004,
-	USB_SPI_DISABLED                = 0x0005,
-	/* The RX continue packet's data index is invalid. */
-	USB_SPI_RX_BAD_DATA_INDEX       = 0x0006,
-	/* The RX endpoint has received more data than write count. */
-	USB_SPI_RX_DATA_OVERFLOW        = 0x0007,
-	/* An unexpected packet arrived on the device. */
-	USB_SPI_RX_UNEXPECTED_PACKET    = 0x0008,
-	/* The device does not support full duplex mode. */
-	USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009,
-	USB_SPI_UNKNOWN_ERROR           = 0x8000,
-};
-
-enum usb_spi_request {
-	USB_SPI_REQ_ENABLE  = 0x0000,
-	USB_SPI_REQ_DISABLE = 0x0001,
-};
-
-/*
- * To optimize for speed, we want to fill whole packets for each transfer
- * This is done by setting the read and write counts to the payload sizes
- * of the smaller start packet + N * continue packets.
- *
- * If a platform has a small maximum SPI transfer size, it can be optimized
- * by setting these limits to the maximum transfer size.
- */
-#define USB_SPI_BUFFER_SIZE	(USB_SPI_PAYLOAD_SIZE_V2_START + \
-				(4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
-#define USB_SPI_MAX_WRITE_COUNT	USB_SPI_BUFFER_SIZE
-#define USB_SPI_MAX_READ_COUNT	USB_SPI_BUFFER_SIZE
-
-struct usb_spi_transfer_ctx {
-	/* Address of transfer buffer. */
-	uint8_t *buffer;
-	/* Number of bytes in the transfer. */
-	size_t transfer_size;
-	/* Number of bytes transferred. */
-	size_t transfer_index;
-};
-
-enum usb_spi_mode {
-	/* No tasks are required. */
-	USB_SPI_MODE_IDLE = 0,
-	/* Indicates the device needs to send it's USB SPI configuration.*/
-	USB_SPI_MODE_SEND_CONFIGURATION,
-	/* Indicates we device needs start the SPI transfer. */
-	USB_SPI_MODE_START_SPI,
-	/* Indicates we should start a transfer response. */
-	USB_SPI_MODE_START_RESPONSE,
-	/* Indicates we need to continue a transfer response. */
-	USB_SPI_MODE_CONTINUE_RESPONSE,
-};
-
-struct usb_spi_state {
-	/*
-	 * The SPI bridge must be enabled both locally and by the host to allow
-	 * access to the SPI device.  The enabled_host flag is set and cleared
-	 * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device
-	 * control endpoint.  The enabled_device flag is set by calling
-	 * usb_spi_enable.
-	 */
-	int enabled_host;
-	int enabled_device;
-
-	/*
-	 * The current enabled state.  This is only updated in the deferred
-	 * callback.  Whenever either of the host or device specific enable
-	 * flags is changed the deferred callback is queued, and it will check
-	 * their combined state against this flag.  If the combined state is
-	 * different, then one of usb_spi_board_enable or usb_spi_board_disable
-	 * is called and this flag is updated.  This ensures that the board
-	 * specific state update routines are only called from the deferred
-	 * callback.
-	 */
-	int enabled;
-
-	/* Mark the current operating mode. */
-	enum usb_spi_mode mode;
-
-	/*
-	 * Stores the status code response for the transfer, delivered in the
-	 * header for the first response packet. Error code is cleared during
-	 * first RX packet and set if a failure occurs.
-	 */
-	uint16_t status_code;
-
-	/* Stores the content from the USB packets */
-	struct usb_spi_packet_ctx receive_packet;
-	struct usb_spi_packet_ctx transmit_packet;
-
-	/*
-	 * Context structures representing the progress receiving the SPI
-	 * write data and transmitting the SPI read data.
-	 */
-	struct usb_spi_transfer_ctx spi_write_ctx;
-	struct usb_spi_transfer_ctx spi_read_ctx;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_spi_config {
-	/* In RAM state of the USB SPI bridge. */
-	struct usb_spi_state *state;
-
-	/* Interface and endpoint indices. */
-	int interface;
-	int endpoint;
-
-	/* Deferred function to call to handle SPI request. */
-	const struct deferred_data *deferred;
-
-	/* Pointers to USB endpoint buffers. */
-	usb_uint *ep_rx_ram;
-	usb_uint *ep_tx_ram;
-
-	/* Flags. See USB_SPI_CONFIG_FLAGS_* for definitions */
-	uint32_t flags;
-};
-
-/*
- * Use when you want the SPI subsystem to be enabled even when the USB SPI
- * endpoint is not enabled by the host. This means that when this firmware
- * enables SPI, then the HW SPI module is enabled (i.e. SPE bit is set) until
- * this firmware disables the SPI module; it ignores the host's enables state.
- */
-#define USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE BIT(0)
-
-/*
- * Convenience macro for defining a USB SPI bridge driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_spi_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * SPI driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * FLAGS encodes different run-time control parameters. See
- * USB_SPI_CONFIG_FLAGS_* for definitions.
- */
-#define USB_SPI_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT,					\
-		       FLAGS)						\
-	static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_spi_state CONCAT2(NAME, _state_) = {			\
-		.enabled_host   = 0,					\
-		.enabled_device = 0,					\
-		.enabled        = 0,					\
-		.spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-		.spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-	};								\
-	struct usb_spi_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_),		\
-		.ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_),		\
-		.flags     = FLAGS,		\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,		\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,		\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_spi_tx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_spi_rx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-		usb_spi_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf,		\
-					      usb_uint *tx_buf)		\
-	{ return usb_spi_interface(&NAME, rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_spi_deferred(&NAME); }
-
-/*
- * Handle SPI request in a deferred callback.
- */
-void usb_spi_deferred(struct usb_spi_config const *config);
-
-/*
- * Set the enable state for the USB-SPI bridge.
- *
- * The bridge must be enabled from both the host and device side
- * before the SPI bus is usable.  This allows the bridge to be
- * available for host tools to use without forcing the device to
- * disconnect or disable whatever else might be using the SPI bus.
- */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB GPIO driver.
- */
-void usb_spi_tx(struct usb_spi_config const *config);
-void usb_spi_rx(struct usb_spi_config const *config);
-void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt);
-int  usb_spi_interface(struct usb_spi_config const *config,
-		       usb_uint *rx_buf,
-		       usb_uint *tx_buf);
-
-/*
- * These functions should be implemented by the board to provide any board
- * specific operations required to enable or disable access to the SPI device.
- */
-void usb_spi_board_enable(struct usb_spi_config const *config);
-void usb_spi_board_disable(struct usb_spi_config const *config);
-
-#endif /* __CROS_EC_USB_SPI_H */
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c
deleted file mode 100644
index 40dfc72059..0000000000
--- a/chip/stm32/watchdog.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * LSI oscillator frequency is typically 38 kHz, but it may be between 28-56
- * kHz and we don't calibrate it to know.  Use 56 kHz so that we pick a counter
- * value large enough that we reload before the worst-case watchdog delay
- * (fastest LSI clock).
- */
-#ifdef CHIP_FAMILY_STM32L4
-#define LSI_CLOCK 34000
-#else
-#define LSI_CLOCK 56000
-#endif
-
-/* The timeout value is multiplied by 1000 to be converted into ms */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_CLOCK)
-
-/*
- * Use largest prescaler divider = /256.  This gives a worst-case watchdog
- * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) =
- * 18.7 sec.
- *
- * For STM32L4, Max LSI is 34000. Watchdog clock is 34000 / 256 = 132Hz,
- * Max timeout = 4095 / 132 = 31 sec.
- */
-#define IWDG_PRESCALER 6
-#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER)
-
-void watchdog_reload(void)
-{
-	/* Reload the watchdog */
-	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-
-#ifdef CONFIG_WATCHDOG_HELP
-	hwtimer_reset_watchdog();
-#endif
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-#ifdef CHIP_FAMILY_STM32L4
-	timestamp_t tickstart, ticknow;
-
-	/* Enable watchdog registers */
-	STM32_IWDG_KR = STM32_IWDG_KR_START;
-#endif
-	/* Unlock watchdog registers */
-	STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
-
-	/* Set the prescaler between the LSI clock and the watchdog counter */
-	STM32_IWDG_PR = IWDG_PRESCALER & 7;
-
-	/* Set the reload value of the watchdog counter */
-	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
-			     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
-#ifdef CHIP_FAMILY_STM32L4
-	tickstart = get_time();
-	/* Wait for SR */
-	while (STM32_IWDG_SR != 0x00u) {
-		ticknow = get_time();
-		if ((ticknow.val - tickstart.val) >
-		    HAL_IWDG_DEFAULT_TIMEOUT * 1000) {
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	/* Reload the watchdog */
-	STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
-#else
-	/* Start the watchdog (and re-lock registers) */
-	STM32_IWDG_KR = STM32_IWDG_KR_START;
-
-	/*
-	 * We should really wait for IWDG_PR and IWDG_RLR value to be updated
-	 * but updating those registers can take about 48ms (found
-	 * empirically, it's 6 LSI cycles at 32kHz). Such a big delay is not
-	 * desired during system init.
-	 *
-	 * However documentation allows us to continue code execution, but
-	 * we should wait for RVU bit to be clear before updating IWDG_RLR
-	 * once again (hard reboot for STM32H7 and STM32F4).
-	 *
-	 * RM0433 Rev 7
-	 * Section 45.4.4 Page 1920
-	 * https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-	 * If several reload, prescaler, or window values are used by the
-	 * application, it is mandatory to wait until RVU bit is reset before
-	 * changing the reload value, to wait until PVU bit is reset before
-	 * changing the prescaler value, and to wait until WVU bit is reset
-	 * before changing the window value. However, after updating the
-	 * prescaler and/or the reload/window value it is not necessary to wait
-	 * until RVU or PVU or WVU is reset before continuing code execution
-	 * except in case of low-power mode entry.
-	 */
-
-#endif
-#ifdef CONFIG_WATCHDOG_HELP
-	/* Use a harder timer to warn about an impending watchdog reset */
-	hwtimer_setup_watchdog();
-#endif
-
-	return EC_SUCCESS;
-}
diff --git a/common/accel_cal.c b/common/accel_cal.c
deleted file mode 100644
index 533a14fbc4..0000000000
--- a/common/accel_cal.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "accel_cal.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
-
-#define TEMP_RANGE (CONFIG_ACCEL_CAL_MAX_TEMP - CONFIG_ACCEL_CAL_MIN_TEMP)
-
-void accel_cal_reset(struct accel_cal *cal)
-{
-	int i;
-
-	for (i = 0; i < cal->num_temp_windows; ++i) {
-		kasa_reset(&(cal->algos[i].kasa_fit));
-		newton_fit_reset(&(cal->algos[i].newton_fit));
-	}
-}
-
-static inline int compute_temp_gate(const struct accel_cal *cal, fp_t temp)
-{
-	int gate = (int) fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP,
-				       INT_TO_FP(cal->num_temp_windows)),
-				TEMP_RANGE);
-
-	return gate < cal->num_temp_windows
-		? gate : (cal->num_temp_windows - 1);
-}
-
-test_mockable bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t timestamp, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
-{
-	struct accel_cal_algo *algo;
-
-	/* Test that we're within the temperature range. */
-	if (temp >= CONFIG_ACCEL_CAL_MAX_TEMP ||
-	    temp <= CONFIG_ACCEL_CAL_MIN_TEMP)
-		return false;
-
-	/* Test that we have a still sample. */
-	if (!still_det_update(&cal->still_det, timestamp, x, y, z))
-		return false;
-
-	/* We have a still sample, update x, y, and z to the mean. */
-	x = cal->still_det.mean_x;
-	y = cal->still_det.mean_y;
-	z = cal->still_det.mean_z;
-
-	/* Compute the temp gate. */
-	algo = &cal->algos[compute_temp_gate(cal, temp)];
-
-	kasa_accumulate(&algo->kasa_fit, x, y, z);
-	if (newton_fit_accumulate(&algo->newton_fit, x, y, z)) {
-		fp_t radius;
-
-		kasa_compute(&algo->kasa_fit, cal->bias, &radius);
-		if (ABS(radius - FLOAT_TO_FP(1.0f)) <
-		    CONFIG_ACCEL_CAL_KASA_RADIUS_THRES)
-			goto accel_cal_accumulate_success;
-
-		newton_fit_compute(&algo->newton_fit, cal->bias, &radius);
-		if (ABS(radius - FLOAT_TO_FP(1.0f)) <
-		    CONFIG_ACCEL_CAL_NEWTON_RADIUS_THRES)
-			goto accel_cal_accumulate_success;
-	}
-
-	return false;
-
-accel_cal_accumulate_success:
-	accel_cal_reset(cal);
-
-	return true;
-}
diff --git a/common/acpi.c b/common/acpi.c
deleted file mode 100644
index 941a8b2e56..0000000000
--- a/common/acpi.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "acpi.h"
-#include "battery.h"
-#include "common.h"
-#include "console.h"
-#include "dptf.h"
-#include "ec_commands.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_backlight.h"
-#include "lpc.h"
-#include "pwm.h"
-#include "timer.h"
-#include "tablet_mode.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
-/* Last received ACPI command */
-static uint8_t __bss_slow acpi_cmd;
-/* First byte of data after ACPI command */
-static uint8_t __bss_slow acpi_addr;
-/* Number of data writes after command */
-static int __bss_slow acpi_data_count;
-/* Test byte in ACPI memory space */
-static uint8_t __bss_slow acpi_mem_test;
-
-#ifdef CONFIG_DPTF
-static int __bss_slow dptf_temp_sensor_id;	/* last sensor ID written */
-static int __bss_slow dptf_temp_threshold;	/* last threshold written */
-
-/*
- * Current DPTF profile number.
- * This is by default initialized to 1 if multi-profile DPTF is not supported.
- * If multi-profile DPTF is supported, this is by default initialized to 2 under
- * the assumption that profile #2 corresponds to lower thresholds and is a safer
- * profile to use until board or some EC driver sets the appropriate profile for
- * device mode.
- */
-static int current_dptf_profile = DPTF_PROFILE_DEFAULT;
-
-#endif
-
-/*
- * Keep a read cache of four bytes when burst mode is enabled, which is the
- * size of the largest non-string memmap data type.
- */
-#define ACPI_READ_CACHE_SIZE 4
-
-/* Start address that indicates read cache is flushed. */
-#define ACPI_READ_CACHE_FLUSHED (EC_ACPI_MEM_MAPPED_BEGIN - 1)
-
-/* Calculate size of valid cache based upon end of memmap data. */
-#define ACPI_VALID_CACHE_SIZE(addr) (MIN( \
-	EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \
-	ACPI_READ_CACHE_SIZE))
-
-/*
- * In burst mode, read the requested memmap data and the data immediately
- * following it into a cache. For future reads in burst mode, try to grab
- * data from the cache. This ensures the continuity of multi-byte reads,
- * which is important when dealing with data types > 8 bits.
- */
-static struct {
-	int enabled;
-	uint8_t start_addr;
-	uint8_t data[ACPI_READ_CACHE_SIZE];
-} acpi_read_cache;
-
-/*
- * Deferred function to ensure that ACPI burst mode doesn't remain enabled
- * indefinitely.
- */
-static void acpi_disable_burst_deferred(void)
-{
-	acpi_read_cache.enabled = 0;
-	lpc_clear_acpi_status_mask(EC_LPC_STATUS_BURST_MODE);
-	CPUTS("ACPI missed burst disable?");
-}
-DECLARE_DEFERRED(acpi_disable_burst_deferred);
-
-#ifdef CONFIG_DPTF
-
-static int acpi_dptf_is_profile_valid(int n)
-{
-#ifdef CONFIG_DPTF_MULTI_PROFILE
-	if ((n < DPTF_PROFILE_VALID_FIRST) || (n > DPTF_PROFILE_VALID_LAST))
-		return EC_ERROR_INVAL;
-#else
-	if (n != DPTF_PROFILE_DEFAULT)
-		return EC_ERROR_INVAL;
-#endif
-
-	return EC_SUCCESS;
-}
-
-int acpi_dptf_set_profile_num(int n)
-{
-	int ret = acpi_dptf_is_profile_valid(n);
-
-	if (ret == EC_SUCCESS) {
-		current_dptf_profile = n;
-		if (IS_ENABLED(CONFIG_DPTF_MULTI_PROFILE) &&
-		    IS_ENABLED(CONFIG_HOSTCMD_EVENTS)) {
-			/* Notify kernel to update DPTF profile */
-			host_set_single_event(EC_HOST_EVENT_MODE_CHANGE);
-		}
-	}
-	return ret;
-}
-
-int acpi_dptf_get_profile_num(void)
-{
-	return current_dptf_profile;
-}
-
-#endif
-
-/* Read memmapped data, returns read data or 0xff on error. */
-static int acpi_read(uint8_t addr)
-{
-	uint8_t *memmap_addr = (uint8_t *)(lpc_get_memmap_range() + addr -
-					   EC_ACPI_MEM_MAPPED_BEGIN);
-
-	/* Check for out-of-range read. */
-	if (addr < EC_ACPI_MEM_MAPPED_BEGIN ||
-	    addr >= EC_ACPI_MEM_MAPPED_BEGIN + EC_ACPI_MEM_MAPPED_SIZE) {
-		CPRINTS("ACPI read 0x%02x (ignored)",
-			acpi_addr);
-		return 0xff;
-	}
-
-	/* Read from cache if enabled (burst mode). */
-	if (acpi_read_cache.enabled) {
-		/* Fetch to cache on miss. */
-		if (acpi_read_cache.start_addr == ACPI_READ_CACHE_FLUSHED ||
-		    acpi_read_cache.start_addr > addr ||
-		    addr - acpi_read_cache.start_addr >=
-		    ACPI_READ_CACHE_SIZE) {
-			memcpy(acpi_read_cache.data,
-			       memmap_addr,
-			       ACPI_VALID_CACHE_SIZE(addr));
-			acpi_read_cache.start_addr = addr;
-		}
-		/* Return data from cache. */
-		return acpi_read_cache.data[addr - acpi_read_cache.start_addr];
-	} else {
-		/* Read directly from memmap data. */
-		return *memmap_addr;
-	}
-}
-
-/*
- * This handles AP writes to the EC via the ACPI I/O port. There are only a few
- * ACPI commands (EC_CMD_ACPI_*), but they are all handled here.
- */
-int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
-{
-	int data = 0;
-	int retval = 0;
-	int result = 0xff;			/* value for bogus read */
-
-	/* Read command/data; this clears the FRMH status bit. */
-	if (is_cmd) {
-		acpi_cmd = value;
-		acpi_data_count = 0;
-	} else {
-		data = value;
-		/*
-		 * The first data byte is the ACPI memory address for
-		 * read/write commands.
-		 */
-		if (!acpi_data_count++)
-			acpi_addr = data;
-	}
-
-	/* Process complete commands */
-	if (acpi_cmd == EC_CMD_ACPI_READ && acpi_data_count == 1) {
-		/* ACPI read cmd + addr */
-		switch (acpi_addr) {
-		case EC_ACPI_MEM_VERSION:
-			result = EC_ACPI_MEM_VERSION_CURRENT;
-			break;
-		case EC_ACPI_MEM_TEST:
-			result = acpi_mem_test;
-			break;
-		case EC_ACPI_MEM_TEST_COMPLIMENT:
-			result = 0xff - acpi_mem_test;
-			break;
-#ifdef CONFIG_KEYBOARD_BACKLIGHT
-		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT:
-			result = kblight_get();
-			break;
-#endif
-#ifdef CONFIG_FANS
-		case EC_ACPI_MEM_FAN_DUTY:
-			result = dptf_get_fan_duty_target();
-			break;
-#endif
-#ifdef CONFIG_DPTF
-		case EC_ACPI_MEM_TEMP_ID:
-			result = dptf_query_next_sensor_event();
-			break;
-#endif
-#ifdef CONFIG_CHARGER
-		case EC_ACPI_MEM_CHARGING_LIMIT:
-			result = dptf_get_charging_current_limit();
-			if (result >= 0)
-				result /= EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA;
-			else
-				result = EC_ACPI_MEM_CHARGING_LIMIT_DISABLED;
-			break;
-#endif
-
-		case EC_ACPI_MEM_DEVICE_ORIENTATION:
-			result = 0;
-
-#ifdef CONFIG_TABLET_MODE
-			result = tablet_get_mode() << EC_ACPI_MEM_TBMD_SHIFT;
-#endif
-
-#ifdef CONFIG_DPTF
-			result |= (acpi_dptf_get_profile_num() &
-				   EC_ACPI_MEM_DDPN_MASK)
-				<< EC_ACPI_MEM_DDPN_SHIFT;
-#endif
-			break;
-
-		case EC_ACPI_MEM_DEVICE_FEATURES0:
-		case EC_ACPI_MEM_DEVICE_FEATURES1:
-		case EC_ACPI_MEM_DEVICE_FEATURES2:
-		case EC_ACPI_MEM_DEVICE_FEATURES3: {
-			int off = acpi_addr - EC_ACPI_MEM_DEVICE_FEATURES0;
-			uint32_t val = get_feature_flags0();
-
-			/* Flush EC_FEATURE_LIMITED bit. Having it reset to 0
-			 * means that FEATURES[0-3] are supported in the first
-			 * place, and the other bits are valid.
-			 */
-			val &= ~1;
-
-			result = val >> (8 * off);
-			break;
-			}
-		case EC_ACPI_MEM_DEVICE_FEATURES4:
-		case EC_ACPI_MEM_DEVICE_FEATURES5:
-		case EC_ACPI_MEM_DEVICE_FEATURES6:
-		case EC_ACPI_MEM_DEVICE_FEATURES7: {
-			int off = acpi_addr - EC_ACPI_MEM_DEVICE_FEATURES4;
-			uint32_t val = get_feature_flags1();
-
-			result = val >> (8 * off);
-			break;
-			}
-
-#ifdef CONFIG_USB_PORT_POWER_DUMB
-		case EC_ACPI_MEM_USB_PORT_POWER: {
-			int i;
-			const int port_count = MIN(8, USB_PORT_COUNT);
-
-			/*
-			 * Convert each USB port power GPIO signal to a bit
-			 * field with max size 8 bits. USB port ID (index) 0 is
-			 * the least significant bit.
-			 */
-			result = 0;
-			for (i = 0; i < port_count; ++i) {
-				if (gpio_get_level(usb_port_enable[i]) != 0)
-					result |= 1 << i;
-			}
-			break;
-			}
-#endif
-#ifdef CONFIG_USBC_RETIMER_FW_UPDATE
-		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
-			result = usb_retimer_fw_update_get_result();
-			break;
-#endif
-		default:
-			result = acpi_read(acpi_addr);
-			break;
-		}
-
-		/* Send the result byte */
-		*resultptr = result;
-		retval = 1;
-
-	} else if (acpi_cmd == EC_CMD_ACPI_WRITE && acpi_data_count == 2) {
-		/* ACPI write cmd + addr + data */
-		switch (acpi_addr) {
-		case EC_ACPI_MEM_TEST:
-			acpi_mem_test = data;
-			break;
-#ifdef CONFIG_BATTERY_V2
-		case EC_ACPI_MEM_BATTERY_INDEX:
-			CPRINTS("ACPI battery %d", data);
-			battery_memmap_set_index(data);
-			break;
-#endif
-#ifdef CONFIG_KEYBOARD_BACKLIGHT
-		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT:
-			/*
-			 * Debug output with CR not newline, because the host
-			 * does a lot of keyboard backlights and it scrolls the
-			 * debug console.
-			 */
-			CPRINTF("\r[%pT ACPI kblight %d]",
-				PRINTF_TIMESTAMP_NOW, data);
-			kblight_set(data);
-			kblight_enable(data > 0);
-			break;
-#endif
-#ifdef CONFIG_FANS
-		case EC_ACPI_MEM_FAN_DUTY:
-			dptf_set_fan_duty_target(data);
-			break;
-#endif
-#ifdef CONFIG_DPTF
-		case EC_ACPI_MEM_TEMP_ID:
-			dptf_temp_sensor_id = data;
-			break;
-		case EC_ACPI_MEM_TEMP_THRESHOLD:
-			dptf_temp_threshold = data + EC_TEMP_SENSOR_OFFSET;
-			break;
-		case EC_ACPI_MEM_TEMP_COMMIT:
-		{
-			int idx = data & EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK;
-			int enable = data & EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK;
-			dptf_set_temp_threshold(dptf_temp_sensor_id,
-						dptf_temp_threshold,
-						idx, enable);
-			break;
-		}
-#endif
-#ifdef CONFIG_CHARGER
-		case EC_ACPI_MEM_CHARGING_LIMIT:
-			if (data == EC_ACPI_MEM_CHARGING_LIMIT_DISABLED) {
-				dptf_set_charging_current_limit(-1);
-			} else {
-				data *= EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA;
-				dptf_set_charging_current_limit(data);
-			}
-			break;
-#endif
-
-#ifdef CONFIG_USB_PORT_POWER_DUMB
-		case EC_ACPI_MEM_USB_PORT_POWER: {
-			int i;
-			int mode_field = data;
-			const int port_count = MIN(8, USB_PORT_COUNT);
-
-			/*
-			 * Read the port power bit field (with max size 8 bits)
-			 * and set the charge mode of each USB port accordingly.
-			 * USB port ID 0 is the least significant bit.
-			 */
-			for (i = 0; i < port_count; ++i) {
-				int mode = USB_CHARGE_MODE_DISABLED;
-
-				if (mode_field & 1)
-					mode = USB_CHARGE_MODE_ENABLED;
-
-				if (usb_charge_set_mode(i, mode,
-				    USB_ALLOW_SUSPEND_CHARGE)) {
-					CPRINTS("ERROR: could not set charge "
-						"mode of USB port p%d to %d",
-						i, mode);
-				}
-				mode_field >>= 1;
-			}
-			break;
-			}
-#endif
-#ifdef CONFIG_USBC_RETIMER_FW_UPDATE
-		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
-			usb_retimer_fw_update_process_op(
-				EC_ACPI_MEM_USB_RETIMER_PORT(data),
-				EC_ACPI_MEM_USB_RETIMER_OP(data));
-			break;
-#endif
-		default:
-			CPRINTS("ACPI write 0x%02x = 0x%02x (ignored)",
-				acpi_addr, data);
-			break;
-		}
-	} else if (acpi_cmd == EC_CMD_ACPI_QUERY_EVENT && !acpi_data_count) {
-		/* Clear and return the lowest host event */
-		int evt_index = lpc_get_next_host_event();
-		CPRINTS("ACPI query = %d", evt_index);
-		*resultptr = evt_index;
-		retval = 1;
-	} else if (acpi_cmd == EC_CMD_ACPI_BURST_ENABLE && !acpi_data_count) {
-		/*
-		 * TODO: The kernel only enables BURST when doing multi-byte
-		 * value reads over the ACPI port. We don't do such reads
-		 * when our memmap data can be accessed directly over LPC,
-		 * so on LM4, for example, this is dead code. We might want
-		 * to add a config to skip this code for certain chips.
-		 */
-		acpi_read_cache.enabled = 1;
-		acpi_read_cache.start_addr = ACPI_READ_CACHE_FLUSHED;
-
-		/* Enter burst mode */
-		lpc_set_acpi_status_mask(EC_LPC_STATUS_BURST_MODE);
-
-		/*
-		 * Disable from deferred function in case burst mode is enabled
-		 * for an extremely long time  (ex. kernel bug / crash).
-		 */
-		hook_call_deferred(&acpi_disable_burst_deferred_data, 1*SECOND);
-
-		/* ACPI 5.0-12.3.3: Burst ACK */
-		*resultptr = 0x90;
-		retval = 1;
-	} else if (acpi_cmd == EC_CMD_ACPI_BURST_DISABLE && !acpi_data_count) {
-		acpi_read_cache.enabled = 0;
-
-		/* Leave burst mode */
-		hook_call_deferred(&acpi_disable_burst_deferred_data, -1);
-		lpc_clear_acpi_status_mask(EC_LPC_STATUS_BURST_MODE);
-	}
-
-	return retval;
-}
diff --git a/common/adc.c b/common/adc.c
deleted file mode 100644
index c9e3a36e57..0000000000
--- a/common/adc.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ADC module for Chrome EC */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "util.h"
-
-/* 'adc' console command is not supported in continuous mode */
-#ifndef CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-static enum adc_channel find_adc_channel_by_name(const char *name)
-{
-	const struct adc_t *ch = adc_channels;
-	int i;
-
-	if (!name || !*name)
-		return ADC_CH_COUNT;
-
-	for (i = 0; i < ADC_CH_COUNT; i++, ch++) {
-		if (!strcasecmp(name, ch->name))
-			return i;
-	}
-
-	return ADC_CH_COUNT;
-}
-
-static int print_one_adc(int channel)
-{
-	int v;
-
-	v = adc_read_channel(channel);
-	if (v == ADC_READ_ERROR)
-		return EC_ERROR_UNKNOWN;
-	ccprintf("  %s = %d mV\n", adc_channels[channel].name, v);
-	return EC_SUCCESS;
-}
-
-static int command_adc(int argc, char **argv)
-{
-	int i, ret;
-
-	/* If a channel is specified, read only that one */
-	if (argc == 2) {
-		i = find_adc_channel_by_name(argv[1]);
-		if (i == ADC_CH_COUNT)
-			return EC_ERROR_PARAM1;
-		return print_one_adc(i);
-	} else {
-		/* Otherwise print them all */
-		for (i = 0; i < ADC_CH_COUNT; ++i) {
-			ret = print_one_adc(i);
-			if (ret)
-				return ret;
-		}
-		return EC_SUCCESS;
-	}
-}
-DECLARE_CONSOLE_COMMAND(adc, command_adc,
-			"[name]",
-			"Print ADC channel(s)");
-
-static enum ec_status hc_adc_read(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_adc_read *params = args->params;
-	struct ec_response_adc_read *resp = args->response;
-	enum adc_channel ch = (enum adc_channel)params->adc_channel;
-	int32_t adc_value;
-
-	if (ch >= ADC_CH_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	adc_value = adc_read_channel(ch);
-	if (adc_value == ADC_READ_ERROR)
-		return EC_RES_ERROR;
-
-	resp->adc_value = adc_value;
-	args->response_size = sizeof(*resp);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_ADC_READ, hc_adc_read, EC_VER_MASK(0));
-#endif /* CONFIG_ADC_PROFILE_FAST_CONTINUOUS */
diff --git a/common/aes-gcm.c b/common/aes-gcm.c
deleted file mode 120000
index 3176d85ff8..0000000000
--- a/common/aes-gcm.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/aes-gcm.c
\ No newline at end of file
diff --git a/common/aes.c b/common/aes.c
deleted file mode 120000
index ed10836943..0000000000
--- a/common/aes.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/aes.c
\ No newline at end of file
diff --git a/common/als.c b/common/als.c
deleted file mode 100644
index 2e9c7ba96c..0000000000
--- a/common/als.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This provides the interface for any Ambient Light Sensors that are connected
- * to the EC instead of the AP.
- */
-
-#include "als.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ALS, outstr)
-#define CPRINTS(format, args...) cprints(CC_ALS, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ALS, format, ## args)
-
-
-#define ALS_POLL_PERIOD SECOND
-
-static int task_timeout = -1;
-
-int als_read(enum als_id id, int *lux)
-{
-	int af = als[id].attenuation_factor;
-	return als[id].read(lux, af);
-}
-
-void als_task(void *u)
-{
-	int i, val;
-	uint16_t *mapped = (uint16_t *)host_get_memmap(EC_MEMMAP_ALS);
-	uint16_t als_data;
-
-	while (1) {
-		task_wait_event(task_timeout);
-
-		/* If task was disabled while waiting do not read from ALS */
-		if (task_timeout < 0)
-			continue;
-
-		for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++) {
-			als_data = als_read(i, &val) == EC_SUCCESS ? val : 0;
-			mapped[i] = als_data;
-		}
-	}
-}
-
-static void als_task_enable(void)
-{
-	int fail_count = 0;
-	int err;
-	int i;
-
-	for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++) {
-		err = als[i].init();
-		if (err) {
-			fail_count++;
-			CPRINTF("%s ALS sensor failed to initialize, err=%d\n",
-				als[i].name, err);
-		}
-	}
-
-	/*
-	 * If all the ALS filed to initialize, disable the ALS task.
-	 */
-	if (fail_count == ALS_COUNT)
-		task_timeout = -1;
-	else
-		task_timeout = ALS_POLL_PERIOD;
-
-	task_wake(TASK_ID_ALS);
-}
-
-static void als_task_disable(void)
-{
-	task_timeout = -1;
-}
-
-static void als_task_init(void)
-{
-	/*
-	 * Enable ALS task in S0 only and may need to re-enable
-	 * when sysjumped.
-	 */
-	if (system_jumped_late() &&
-		chipset_in_state(CHIPSET_STATE_ON))
-		als_task_enable();
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, als_task_enable, HOOK_PRIO_ALS_INIT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, als_task_disable, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, als_task_init, HOOK_PRIO_ALS_INIT);
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_ALS
-static int command_als(int argc, char **argv)
-{
-	int i, rv, val;
-
-	for (i = 0; i < ALS_COUNT; i++) {
-		ccprintf("%s: ", als[i].name);
-		rv = als_read(i, &val);
-		switch (rv) {
-		case EC_SUCCESS:
-			ccprintf("%d lux\n", val);
-			break;
-		default:
-			ccprintf("Error %d\n", rv);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(als, command_als,
-			NULL,
-			"Print ALS values");
-#endif
diff --git a/common/ap_hang_detect.c b/common/ap_hang_detect.c
deleted file mode 100644
index 0c9e7a186d..0000000000
--- a/common/ap_hang_detect.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AP hang detect logic */
-
-#include "ap_hang_detect.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static struct ec_params_hang_detect hdparams;
-
-static int active;  /* Is hang detect timer active / counting? */
-static int timeout_will_reboot;  /* Will the deferred call reboot the AP? */
-
-/**
- * Handle the hang detect timer expiring.
- */
-static void hang_detect_deferred(void);
-DECLARE_DEFERRED(hang_detect_deferred);
-
-static void hang_detect_deferred(void)
-{
-	/* If we're no longer active, nothing to do */
-	if (!active)
-		return;
-
-	/* If we're rebooting the AP, stop hang detection */
-	if (timeout_will_reboot) {
-		CPRINTS("hang detect triggering warm reboot");
-		host_set_single_event(EC_HOST_EVENT_HANG_REBOOT);
-		chipset_reset(CHIPSET_RESET_HANG_REBOOT);
-		active = 0;
-		return;
-	}
-
-	/* Otherwise, we're starting with the host event */
-	CPRINTS("hang detect sending host event");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-
-	/* If we're also rebooting, defer for the remaining delay */
-	if (hdparams.warm_reboot_timeout_msec) {
-		CPRINTS("hang detect continuing (for reboot)");
-		timeout_will_reboot = 1;
-		hook_call_deferred(&hang_detect_deferred_data,
-				   (hdparams.warm_reboot_timeout_msec -
-				    hdparams.host_event_timeout_msec) * MSEC);
-	} else {
-		/* Not rebooting, so go back to idle */
-		active = 0;
-	}
-}
-
-/**
- * Start the hang detect timers.
- */
-static void hang_detect_start(const char *why)
-{
-	/* If already active, don't restart timer */
-	if (active)
-		return;
-
-	if (hdparams.host_event_timeout_msec) {
-		CPRINTS("hang detect started on %s (for event)", why);
-		timeout_will_reboot = 0;
-		active = 1;
-		hook_call_deferred(&hang_detect_deferred_data,
-				   hdparams.host_event_timeout_msec * MSEC);
-	} else if (hdparams.warm_reboot_timeout_msec) {
-		CPRINTS("hang detect started on %s (for reboot)", why);
-		timeout_will_reboot = 1;
-		active = 1;
-		hook_call_deferred(&hang_detect_deferred_data,
-				   hdparams.warm_reboot_timeout_msec * MSEC);
-	}
-}
-
-/**
- * Stop the hang detect timers.
- */
-static void hang_detect_stop(const char *why)
-{
-	if (active)
-		CPRINTS("hang detect stopped on %s", why);
-
-	active = 0;
-}
-
-void hang_detect_stop_on_host_command(void)
-{
-	if (hdparams.flags & EC_HANG_STOP_ON_HOST_COMMAND)
-		hang_detect_stop("host cmd");
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void hang_detect_power_button(void)
-{
-	if (power_button_is_pressed()) {
-		if (hdparams.flags & EC_HANG_START_ON_POWER_PRESS)
-			hang_detect_start("power button");
-	} else {
-		if (hdparams.flags & EC_HANG_STOP_ON_POWER_RELEASE)
-			hang_detect_stop("power button");
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, hang_detect_power_button,
-	     HOOK_PRIO_DEFAULT);
-
-static void hang_detect_lid(void)
-{
-	if (lid_is_open()) {
-		if (hdparams.flags & EC_HANG_START_ON_LID_OPEN)
-			hang_detect_start("lid open");
-	} else {
-		if (hdparams.flags & EC_HANG_START_ON_LID_CLOSE)
-			hang_detect_start("lid close");
-	}
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, hang_detect_lid, HOOK_PRIO_DEFAULT);
-
-static void hang_detect_resume(void)
-{
-	if (hdparams.flags & EC_HANG_START_ON_RESUME)
-		hang_detect_start("resume");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, hang_detect_resume, HOOK_PRIO_DEFAULT);
-
-static void hang_detect_suspend(void)
-{
-	if (hdparams.flags & EC_HANG_STOP_ON_SUSPEND)
-		hang_detect_stop("suspend");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, hang_detect_suspend, HOOK_PRIO_DEFAULT);
-
-static void hang_detect_shutdown(void)
-{
-	/* Stop the timers */
-	hang_detect_stop("shutdown");
-
-	/* Disable hang detection; it must be enabled every boot */
-	memset(&hdparams, 0, sizeof(hdparams));
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hang_detect_shutdown, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Host command */
-
-static enum ec_status
-hang_detect_host_command(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_hang_detect *p = args->params;
-
-	/* Handle stopping hang timer on request */
-	if (p->flags & EC_HANG_STOP_NOW) {
-		hang_detect_stop("ap request");
-
-		/* Ignore the other params */
-		return EC_RES_SUCCESS;
-	}
-
-	/* Handle starting hang timer on request */
-	if (p->flags & EC_HANG_START_NOW) {
-		hang_detect_start("ap request");
-
-		/* Ignore the other params */
-		return EC_RES_SUCCESS;
-	}
-
-	/* If hang detect transitioning to disabled, stop timers */
-	if (hdparams.flags && !p->flags)
-		hang_detect_stop("ap flags=0");
-
-	/* Save new params */
-	hdparams = *p;
-	CPRINTS("hang detect flags=0x%x, event=%d ms, reboot=%d ms",
-		hdparams.flags, hdparams.host_event_timeout_msec,
-		hdparams.warm_reboot_timeout_msec);
-
-	/*
-	 * If warm reboot timeout is shorter than host event timeout, ignore
-	 * the host event timeout because a warm reboot will win.
-	 */
-	if (hdparams.warm_reboot_timeout_msec &&
-	    hdparams.warm_reboot_timeout_msec <=
-	    hdparams.host_event_timeout_msec)
-		hdparams.host_event_timeout_msec = 0;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT,
-		     hang_detect_host_command,
-		     EC_VER_MASK(0));
-
-/*****************************************************************************/
-/* Console command */
-
-static int command_hang_detect(int argc, char **argv)
-{
-	ccprintf("flags:  0x%x\n", hdparams.flags);
-
-	ccputs("event:  ");
-	if (hdparams.host_event_timeout_msec)
-		ccprintf("%d ms\n", hdparams.host_event_timeout_msec);
-	else
-		ccputs("disabled\n");
-
-	ccputs("reboot: ");
-	if (hdparams.warm_reboot_timeout_msec)
-		ccprintf("%d ms\n", hdparams.warm_reboot_timeout_msec);
-	else
-		ccputs("disabled\n");
-
-	ccputs("status: ");
-	if (active)
-		ccprintf("active for %s\n",
-			 timeout_will_reboot ? "reboot" : "event");
-	else
-		ccputs("inactive\n");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect,
-			NULL,
-			"Print hang detect state");
diff --git a/common/audio_codec.c b/common/audio_codec.c
deleted file mode 100644
index 3f7203ad15..0000000000
--- a/common/audio_codec.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "console.h"
-#include "host_command.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-static const uint32_t capabilities =
-	0
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-	| BIT(EC_CODEC_CAP_WOV_AUDIO_SHM)
-#endif
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-	| BIT(EC_CODEC_CAP_WOV_LANG_SHM)
-#endif
-	;
-
-static struct {
-	uint8_t cap;
-	uint8_t type;
-	uintptr_t *addr;
-	uint32_t len;
-} shms[EC_CODEC_SHM_ID_LAST];
-
-static enum ec_status get_capabilities(struct host_cmd_handler_args *args)
-{
-	struct ec_response_ec_codec_get_capabilities *r = args->response;
-
-	r->capabilities = capabilities;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status get_shm_addr(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec *p = args->params;
-	struct ec_response_ec_codec_get_shm_addr *r = args->response;
-	const uint8_t shm_id = p->get_shm_addr_param.shm_id;
-
-	if (shm_id >= EC_CODEC_SHM_ID_LAST)
-		return EC_RES_INVALID_PARAM;
-	if (!shms[shm_id].addr || !audio_codec_capable(shms[shm_id].cap))
-		return EC_RES_INVALID_PARAM;
-	if (!*shms[shm_id].addr &&
-	    shms[shm_id].type == EC_CODEC_SHM_TYPE_EC_RAM)
-		return EC_RES_ERROR;
-
-	r->len = shms[shm_id].len;
-	r->type = shms[shm_id].type;
-	r->phys_addr = *shms[shm_id].addr;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status set_shm_addr(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec *p = args->params;
-	const uint8_t shm_id = p->set_shm_addr_param.shm_id;
-	uintptr_t ap_addr, ec_addr;
-
-	if (shm_id >= EC_CODEC_SHM_ID_LAST)
-		return EC_RES_INVALID_PARAM;
-	if (!shms[shm_id].addr || !audio_codec_capable(shms[shm_id].cap))
-		return EC_RES_INVALID_PARAM;
-	if (p->set_shm_addr_param.len < shms[shm_id].len)
-		return EC_RES_INVALID_PARAM;
-	if (*shms[shm_id].addr)
-		return EC_RES_BUSY;
-
-	ap_addr = (uintptr_t)p->set_shm_addr_param.phys_addr;
-	if (audio_codec_memmap_ap_to_ec(ap_addr, &ec_addr) != EC_SUCCESS)
-		return EC_RES_ERROR;
-	*shms[shm_id].addr = ec_addr;
-
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status (*sub_cmds[])(struct host_cmd_handler_args *) = {
-	[EC_CODEC_GET_CAPABILITIES] = get_capabilities,
-	[EC_CODEC_GET_SHM_ADDR] = get_shm_addr,
-	[EC_CODEC_SET_SHM_ADDR] = set_shm_addr,
-};
-
-#ifdef DEBUG_AUDIO_CODEC
-static char *strcmd[] = {
-	[EC_CODEC_GET_CAPABILITIES] = "EC_CODEC_GET_CAPABILITIES",
-	[EC_CODEC_GET_SHM_ADDR] = "EC_CODEC_GET_SHM_ADDR",
-	[EC_CODEC_SET_SHM_ADDR] = "EC_CODEC_SET_SHM_ADDR",
-};
-BUILD_ASSERT(ARRAY_SIZE(sub_cmds) == ARRAY_SIZE(strcmd));
-#endif
-
-static enum ec_status host_command(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec *p = args->params;
-
-#ifdef DEBUG_AUDIO_CODEC
-	CPRINTS("subcommand: %s", strcmd[p->cmd]);
-#endif
-
-	if (p->cmd < EC_CODEC_SUBCMD_COUNT)
-		return sub_cmds[p->cmd](args);
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC, host_command, EC_VER_MASK(0));
-
-/*
- * Exported interfaces.
- */
-int audio_codec_capable(uint8_t cap)
-{
-	return capabilities & BIT(cap);
-}
-
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type)
-{
-	if (shm_id >= EC_CODEC_SHM_ID_LAST)
-		return EC_ERROR_INVAL;
-	if (cap >= EC_CODEC_CAP_LAST)
-		return EC_ERROR_INVAL;
-	if (shms[shm_id].addr || shms[shm_id].len)
-		return EC_ERROR_BUSY;
-
-	shms[shm_id].cap = cap;
-	shms[shm_id].addr = addr;
-	shms[shm_id].len = len;
-	shms[shm_id].type = type;
-
-	return EC_SUCCESS;
-}
-
-__attribute__((weak))
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar)
-{
-	int32_t val;
-
-	val = (int32_t)orig * (int32_t)scalar;
-	val = MIN(val, (int32_t)INT16_MAX);
-	val = MAX(val, (int32_t)INT16_MIN);
-	return val;
-}
diff --git a/common/audio_codec_dmic.c b/common/audio_codec_dmic.c
deleted file mode 100644
index c4f0b07a46..0000000000
--- a/common/audio_codec_dmic.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "console.h"
-#include "host_command.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-static enum ec_status dmic_get_max_gain(struct host_cmd_handler_args *args)
-{
-	struct ec_response_ec_codec_dmic_get_max_gain *r = args->response;
-
-	if (audio_codec_dmic_get_max_gain(&r->max_gain) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status dmic_set_gain_idx(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_dmic *p = args->params;
-
-	if (audio_codec_dmic_set_gain_idx(
-			p->set_gain_idx_param.channel,
-			p->set_gain_idx_param.gain) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status dmic_get_gain_idx(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_dmic *p = args->params;
-	struct ec_response_ec_codec_dmic_get_gain_idx *r = args->response;
-
-	if (audio_codec_dmic_get_gain_idx(
-			p->get_gain_idx_param.channel, &r->gain) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status (*sub_cmds[])(struct host_cmd_handler_args *) = {
-	[EC_CODEC_DMIC_GET_MAX_GAIN] = dmic_get_max_gain,
-	[EC_CODEC_DMIC_SET_GAIN_IDX] = dmic_set_gain_idx,
-	[EC_CODEC_DMIC_GET_GAIN_IDX] = dmic_get_gain_idx,
-};
-
-#ifdef DEBUG_AUDIO_CODEC
-static char *strcmd[] = {
-	[EC_CODEC_DMIC_GET_MAX_GAIN] = "EC_CODEC_DMIC_GET_MAX_GAIN",
-	[EC_CODEC_DMIC_SET_GAIN_IDX] = "EC_CODEC_DMIC_SET_GAIN_IDX",
-	[EC_CODEC_DMIC_GET_GAIN_IDX] = "EC_CODEC_DMIC_GET_GAIN_IDX",
-};
-BUILD_ASSERT(ARRAY_SIZE(sub_cmds) == ARRAY_SIZE(strcmd));
-#endif
-
-static enum ec_status dmic_host_command(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_dmic *p = args->params;
-
-#ifdef DEBUG_AUDIO_CODEC
-	CPRINTS("DMIC subcommand: %s", strcmd[p->cmd]);
-#endif
-
-	if (p->cmd < EC_CODEC_DMIC_SUBCMD_COUNT)
-		return sub_cmds[p->cmd](args);
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_DMIC, dmic_host_command, EC_VER_MASK(0));
-
-#ifdef CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN
-static uint8_t channel_gains[EC_CODEC_DMIC_CHANNEL_COUNT];
-
-int audio_codec_dmic_get_max_gain(uint8_t *gain)
-{
-	*gain = CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN;
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain)
-{
-	if (channel >= ARRAY_SIZE(channel_gains))
-		return EC_ERROR_INVAL;
-	if (gain > CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN)
-		return EC_ERROR_INVAL;
-
-	channel_gains[channel] = gain;
-	return EC_SUCCESS;
-}
-
-int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain)
-{
-	if (channel >= ARRAY_SIZE(channel_gains))
-		return EC_ERROR_INVAL;
-
-	*gain = channel_gains[channel];
-	return EC_SUCCESS;
-}
-#endif
diff --git a/common/audio_codec_i2s_rx.c b/common/audio_codec_i2s_rx.c
deleted file mode 100644
index aeae19bdca..0000000000
--- a/common/audio_codec_i2s_rx.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "console.h"
-#include "host_command.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-static uint8_t i2s_rx_enabled;
-
-static enum ec_status i2s_rx_enable(struct host_cmd_handler_args *args)
-{
-	if (i2s_rx_enabled)
-		return EC_RES_BUSY;
-
-	if (audio_codec_i2s_rx_enable() != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	i2s_rx_enabled = 1;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status i2s_rx_disable(struct host_cmd_handler_args *args)
-{
-	if (!i2s_rx_enabled)
-		return EC_RES_BUSY;
-
-	if (audio_codec_i2s_rx_disable() != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	i2s_rx_enabled = 0;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status
-i2s_rx_set_sample_depth(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_i2s_rx *p = args->params;
-	const uint8_t depth = p->set_sample_depth_param.depth;
-
-	if (i2s_rx_enabled)
-		return EC_RES_BUSY;
-	if (depth >= EC_CODEC_I2S_RX_SAMPLE_DEPTH_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	if (audio_codec_i2s_rx_set_sample_depth(depth) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status i2s_rx_set_daifmt(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_i2s_rx *p = args->params;
-	const uint8_t daifmt = p->set_daifmt_param.daifmt;
-
-	if (i2s_rx_enabled)
-		return EC_RES_BUSY;
-	if (daifmt >= EC_CODEC_I2S_RX_DAIFMT_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	if (audio_codec_i2s_rx_set_daifmt(daifmt) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status i2s_rx_set_bclk(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_i2s_rx *p = args->params;
-
-	if (i2s_rx_enabled)
-		return EC_RES_BUSY;
-
-	if (audio_codec_i2s_rx_set_bclk(p->set_bclk_param.bclk) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status i2s_rx_reset(struct host_cmd_handler_args *args)
-{
-	if (audio_codec_i2s_rx_disable() != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	i2s_rx_enabled = 0;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status (*sub_cmds[])(struct host_cmd_handler_args *) = {
-	[EC_CODEC_I2S_RX_ENABLE] = i2s_rx_enable,
-	[EC_CODEC_I2S_RX_DISABLE] = i2s_rx_disable,
-	[EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH] = i2s_rx_set_sample_depth,
-	[EC_CODEC_I2S_RX_SET_DAIFMT] = i2s_rx_set_daifmt,
-	[EC_CODEC_I2S_RX_SET_BCLK] = i2s_rx_set_bclk,
-	[EC_CODEC_I2S_RX_RESET] = i2s_rx_reset,
-};
-
-#ifdef DEBUG_AUDIO_CODEC
-static char *strcmd[] = {
-	[EC_CODEC_I2S_RX_ENABLE] = "EC_CODEC_I2S_RX_ENABLE",
-	[EC_CODEC_I2S_RX_DISABLE] = "EC_CODEC_I2S_RX_DISABLE",
-	[EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH] = "EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH",
-	[EC_CODEC_I2S_RX_SET_DAIFMT] = "EC_CODEC_I2S_RX_SET_DAIFMT",
-	[EC_CODEC_I2S_RX_SET_BCLK] = "EC_CODEC_I2S_RX_SET_BCLK",
-	[EC_CODEC_I2S_RX_RESET] = "EC_CODEC_I2S_RESET",
-};
-BUILD_ASSERT(ARRAY_SIZE(sub_cmds) == ARRAY_SIZE(strcmd));
-#endif
-
-static enum ec_status i2s_rx_host_command(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_i2s_rx *p = args->params;
-
-#ifdef DEBUG_AUDIO_CODEC
-	CPRINTS("I2S RX subcommand: %s", strcmd[p->cmd]);
-#endif
-
-	if (p->cmd < EC_CODEC_I2S_RX_SUBCMD_COUNT)
-		return sub_cmds[p->cmd](args);
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX,
-	i2s_rx_host_command, EC_VER_MASK(0));
diff --git a/common/audio_codec_wov.c b/common/audio_codec_wov.c
deleted file mode 100644
index f84e45f342..0000000000
--- a/common/audio_codec_wov.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "console.h"
-#include "host_command.h"
-#include "hotword_dsp_api.h"
-#include "sha256.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
-
-/*
- * To shorten the variable names, or the following code is likely to greater
- * than 80 columns.
- */
-#define AUDIO_BUF_LEN CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_LEN
-#define LANG_BUF_LEN CONFIG_AUDIO_CODEC_WOV_LANG_BUF_LEN
-
-static uint8_t lang_hash[SHA256_DIGEST_SIZE];
-static uint32_t lang_len;
-
-/*
- * The variables below are shared between host command and WoV task.  This lock
- * is designed to protect them.
- */
-static struct mutex lock;
-
-/*
- * wov_enabled is shared.
- *
- * host command task:
- *   - is the only writer
- *   - no need to lock if read
- */
-static uint8_t wov_enabled;
-
-/*
- * hotword_detected is shared.
- */
-static uint8_t hotword_detected;
-
-/*
- * audio_buf_rp and audio_buf_wp are shared.
- *
- * Note that: sample width is 16-bit.
- *
- * Typical ring-buffer implementation:
- *   If audio_buf_rp == audio_buf_wp, empty.
- *   If (audio_buf_wp + 2) % buf_len == audio_buf_rp, full.
- */
-static uint32_t audio_buf_rp, audio_buf_wp;
-
-static int is_buf_full(void)
-{
-	return ((audio_buf_wp + 2) % AUDIO_BUF_LEN) == audio_buf_rp;
-}
-
-/* only used by host command */
-static uint8_t speech_lib_loaded;
-
-static int check_lang_buf(uint8_t *data, uint32_t len, const uint8_t *hash)
-{
-	/*
-	 * Note: sizeof(struct sha256_ctx) = 200 bytes
-	 * should put into .bss, or stack is likely to overflow (~640 bytes)
-	 */
-	static struct sha256_ctx ctx;
-	uint8_t *digest;
-	int i;
-	uint8_t *p = (uint8_t *)audio_codec_wov_lang_buf_addr;
-
-	SHA256_init(&ctx);
-	SHA256_update(&ctx, data, len);
-	digest = SHA256_final(&ctx);
-
-#ifdef DEBUG_AUDIO_CODEC
-	CPRINTS("data=%08x len=%d", data, len);
-	hexdump(digest, SHA256_DIGEST_SIZE);
-#endif
-
-	if (memcmp(digest, hash, SHA256_DIGEST_SIZE) != 0)
-		return EC_ERROR_UNKNOWN;
-
-	for (i = len; i < LANG_BUF_LEN; ++i)
-		if (p[i])
-			return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-static enum ec_status wov_set_lang_shm(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_wov *p = args->params;
-	const struct ec_param_ec_codec_wov_set_lang_shm *pp =
-			&p->set_lang_shm_param;
-
-	if (pp->total_len > LANG_BUF_LEN)
-		return EC_RES_INVALID_PARAM;
-	if (wov_enabled)
-		return EC_RES_BUSY;
-
-	if (check_lang_buf((uint8_t *)audio_codec_wov_lang_buf_addr,
-			   pp->total_len, pp->hash) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	memcpy(lang_hash, pp->hash, sizeof(lang_hash));
-	lang_len = pp->total_len;
-	speech_lib_loaded = 0;
-
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-#else
-static enum ec_status wov_set_lang(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_wov *p = args->params;
-	const struct ec_param_ec_codec_wov_set_lang *pp = &p->set_lang_param;
-
-	if (pp->total_len > LANG_BUF_LEN)
-		return EC_RES_INVALID_PARAM;
-	if (pp->offset >= LANG_BUF_LEN)
-		return EC_RES_INVALID_PARAM;
-	if (pp->len > ARRAY_SIZE(pp->buf))
-		return EC_RES_INVALID_PARAM;
-	if (pp->offset + pp->len > pp->total_len)
-		return EC_RES_INVALID_PARAM;
-	if (wov_enabled)
-		return EC_RES_BUSY;
-
-	if (!pp->offset)
-		memset((uint8_t *)audio_codec_wov_lang_buf_addr,
-		       0, LANG_BUF_LEN);
-
-	memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset,
-		pp->buf, pp->len);
-
-	if (pp->offset + pp->len == pp->total_len) {
-		if (check_lang_buf((uint8_t *)audio_codec_wov_lang_buf_addr,
-				   pp->total_len, pp->hash) != EC_SUCCESS)
-			return EC_RES_ERROR;
-
-		memcpy(lang_hash, pp->hash, sizeof(lang_hash));
-		lang_len = pp->total_len;
-		speech_lib_loaded = 0;
-	}
-
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-#endif /* CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM */
-
-static enum ec_status wov_get_lang(struct host_cmd_handler_args *args)
-{
-	struct ec_response_ec_codec_wov_get_lang *r = args->response;
-
-	memcpy(r->hash, lang_hash, sizeof(r->hash));
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status wov_enable(struct host_cmd_handler_args *args)
-{
-	if (wov_enabled)
-		return EC_RES_BUSY;
-
-	if (audio_codec_wov_enable() != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	if (!speech_lib_loaded) {
-		if (!GoogleHotwordDspInit(
-				(void *)audio_codec_wov_lang_buf_addr))
-			return EC_RES_ERROR;
-		speech_lib_loaded = 1;
-	} else {
-		GoogleHotwordDspReset();
-	}
-
-	mutex_lock(&lock);
-	wov_enabled = 1;
-	hotword_detected = 0;
-	audio_buf_rp = audio_buf_wp = 0;
-	mutex_unlock(&lock);
-
-#ifdef HAS_TASK_WOV
-	task_wake(TASK_ID_WOV);
-#endif
-
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status wov_disable(struct host_cmd_handler_args *args)
-{
-	if (!wov_enabled)
-		return EC_RES_BUSY;
-
-	if (audio_codec_wov_disable() != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	mutex_lock(&lock);
-	wov_enabled = 0;
-	hotword_detected = 0;
-	audio_buf_rp = audio_buf_wp = 0;
-	mutex_unlock(&lock);
-
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-static enum ec_status wov_read_audio_shm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_ec_codec_wov_read_audio_shm *r = args->response;
-
-	if (!wov_enabled)
-		return EC_RES_ACCESS_DENIED;
-
-	mutex_lock(&lock);
-	if (!hotword_detected) {
-		mutex_unlock(&lock);
-		return EC_RES_ACCESS_DENIED;
-	}
-
-	r->offset = audio_buf_rp;
-	if (audio_buf_rp <= audio_buf_wp)
-		r->len = audio_buf_wp - audio_buf_rp;
-	else
-		r->len = AUDIO_BUF_LEN - audio_buf_rp;
-
-	audio_buf_rp += r->len;
-	if (audio_buf_rp == AUDIO_BUF_LEN)
-		audio_buf_rp = 0;
-	mutex_unlock(&lock);
-
-#ifdef DEBUG_AUDIO_CODEC
-	if (!r->len)
-		CPRINTS("underrun detected");
-#endif
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-#else
-static enum ec_status wov_read_audio(struct host_cmd_handler_args *args)
-{
-	struct ec_response_ec_codec_wov_read_audio *r = args->response;
-	uint8_t *p;
-
-	if (!wov_enabled)
-		return EC_RES_ACCESS_DENIED;
-
-	mutex_lock(&lock);
-	if (!hotword_detected) {
-		mutex_unlock(&lock);
-		return EC_RES_ACCESS_DENIED;
-	}
-
-	if (audio_buf_rp <= audio_buf_wp)
-		r->len = audio_buf_wp - audio_buf_rp;
-	else
-		r->len = AUDIO_BUF_LEN - audio_buf_rp;
-	r->len = MIN(sizeof(r->buf), r->len);
-
-	p = (uint8_t *)audio_codec_wov_audio_buf_addr + audio_buf_rp;
-
-	audio_buf_rp += r->len;
-	if (audio_buf_rp == AUDIO_BUF_LEN)
-		audio_buf_rp = 0;
-	mutex_unlock(&lock);
-
-#ifdef DEBUG_AUDIO_CODEC
-	if (!r->len)
-		CPRINTS("underrun detected");
-#endif
-	/*
-	 * Note: it is possible to copy corrupted audio data if overrun
-	 * happened at the point.  To keep it simple and align to SHM mode,
-	 * we ignore the case if overrun happened.
-	 */
-	memcpy(r->buf, p, r->len);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-#endif /* CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM */
-
-static enum ec_status (*sub_cmds[])(struct host_cmd_handler_args *) = {
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-	[EC_CODEC_WOV_SET_LANG_SHM] = wov_set_lang_shm,
-#else
-	[EC_CODEC_WOV_SET_LANG] = wov_set_lang,
-#endif
-	[EC_CODEC_WOV_GET_LANG] = wov_get_lang,
-	[EC_CODEC_WOV_ENABLE] = wov_enable,
-	[EC_CODEC_WOV_DISABLE] = wov_disable,
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-	[EC_CODEC_WOV_READ_AUDIO_SHM] = wov_read_audio_shm,
-#else
-	[EC_CODEC_WOV_READ_AUDIO] = wov_read_audio,
-#endif
-};
-
-#ifdef DEBUG_AUDIO_CODEC
-static char *strcmd[] = {
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-	[EC_CODEC_WOV_SET_LANG_SHM] = "EC_CODEC_WOV_SET_LANG_SHM",
-#else
-	[EC_CODEC_WOV_SET_LANG] = "EC_CODEC_WOV_SET_LANG",
-#endif
-	[EC_CODEC_WOV_GET_LANG] = "EC_CODEC_WOV_GET_LANG",
-	[EC_CODEC_WOV_ENABLE] = "EC_CODEC_WOV_ENABLE",
-	[EC_CODEC_WOV_DISABLE] = "EC_CODEC_WOV_DISABLE",
-#ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-	[EC_CODEC_WOV_READ_AUDIO_SHM] = "EC_CODEC_WOV_READ_AUDIO_SHM",
-#else
-	[EC_CODEC_WOV_READ_AUDIO] = "EC_CODEC_WOV_READ_AUDIO",
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(sub_cmds) == ARRAY_SIZE(strcmd));
-#endif
-
-static enum ec_status wov_host_command(struct host_cmd_handler_args *args)
-{
-	const struct ec_param_ec_codec_wov *p = args->params;
-
-#ifdef DEBUG_AUDIO_CODEC
-	CPRINTS("WoV subcommand: %s", strcmd[p->cmd]);
-#endif
-
-	if (p->cmd < EC_CODEC_WOV_SUBCMD_COUNT && sub_cmds[p->cmd])
-		return sub_cmds[p->cmd](args);
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_WOV, wov_host_command, EC_VER_MASK(0));
-
-/*
- * Exported interfaces.
- */
-void audio_codec_wov_task(void *arg)
-{
-	uint32_t n, req;
-	uint8_t *p;
-	int r;
-
-	while (1) {
-		mutex_lock(&lock);
-		if (!wov_enabled) {
-			mutex_unlock(&lock);
-			task_wait_event(-1);
-			continue;
-		}
-
-
-		/* Clear the buffer if full. */
-		if (is_buf_full()) {
-			audio_buf_wp = audio_buf_rp;
-
-#ifdef DEBUG_AUDIO_CODEC
-			if (hotword_detected)
-				CPRINTS("overrun detected");
-#endif
-		}
-
-		/*
-		 * Note: sample width is 16-bit.
-		 *
-		 * The linear ring buffer wastes one sample bytes to
-		 * detect buffer full.
-		 *
-		 * If buffer is empty, maximum req is BUF_LEN - 2.
-		 * If wp > rp, wp can fill to the end of linear buffer.
-		 * If wp < rp, wp can fill up to rp - 2.
-		 */
-		if (audio_buf_wp == audio_buf_rp)
-			req = AUDIO_BUF_LEN - MAX(audio_buf_wp, 2);
-		else if (audio_buf_wp > audio_buf_rp)
-			req = AUDIO_BUF_LEN - audio_buf_wp;
-		else
-			req = audio_buf_rp - audio_buf_wp - 2;
-
-		p = (uint8_t *)audio_codec_wov_audio_buf_addr + audio_buf_wp;
-		mutex_unlock(&lock);
-
-		n = audio_codec_wov_read(p, req);
-		if (n < 0) {
-			CPRINTS("failed to read: %d", n);
-			break;
-		} else if (n == 0) {
-			if (audio_codec_wov_enable_notifier() != EC_SUCCESS) {
-				CPRINTS("failed to enable_notifier");
-				break;
-			}
-
-			task_wait_event(-1);
-			continue;
-		}
-
-		mutex_lock(&lock);
-		audio_buf_wp += n;
-		if (audio_buf_wp == AUDIO_BUF_LEN)
-			audio_buf_wp = 0;
-		mutex_unlock(&lock);
-
-		/*
-		 * GoogleHotwordDspProcess() needs number of samples.  In the
-		 * case, sample is S16_LE.  Thus, n / 2.
-		 */
-		if (!hotword_detected &&
-				GoogleHotwordDspProcess(p, n / 2, &r)) {
-			CPRINTS("hotword detected");
-
-			mutex_lock(&lock);
-			/*
-			 * Note: preserve 40% of buf size for AP to read
-			 * (see go/cros-ec-codec#heading=h.582ga6pgfl2g)
-			 */
-			audio_buf_rp = audio_buf_wp + (AUDIO_BUF_LEN * 2 / 5);
-			if (audio_buf_rp >= AUDIO_BUF_LEN)
-				audio_buf_rp -= AUDIO_BUF_LEN;
-
-			hotword_detected = 1;
-			mutex_unlock(&lock);
-
-			host_set_single_event(EC_HOST_EVENT_WOV);
-		}
-
-		/*
-		 * Reasons to sleep here:
-		 * 1. read the audio data in a fixed pace (10ms)
-		 * 2. yield the processor in case of watchdog thought EC crashed
-		 */
-		task_wait_event(10 * MSEC);
-	}
-}
diff --git a/common/backlight_lid.c b/common/backlight_lid.c
deleted file mode 100644
index 3b857df592..0000000000
--- a/common/backlight_lid.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Backlight control based on lid and optional request signal from AP */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-
-
-/**
- * Activate/Deactivate the backlight GPIO pin considering active high or low.
- */
-void enable_backlight(int enabled)
-{
-#ifdef CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, !enabled);
-#else
-	gpio_set_level(GPIO_ENABLE_BACKLIGHT, enabled);
-#endif
-}
-
-/**
- * Update backlight state.
- */
-static void update_backlight(void)
-{
-#ifdef CONFIG_BACKLIGHT_REQ_GPIO
-	/* Enable the backlight if lid is open AND requested by AP */
-	enable_backlight(lid_is_open() &&
-		gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO));
-#else
-	/*
-	 * Enable backlight if lid is open; this is AND'd with the request from
-	 * the AP in hardware.
-	 */
-	enable_backlight(lid_is_open());
-#endif
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, update_backlight, HOOK_PRIO_DEFAULT);
-
-/**
- * Initialize backlight module.
- */
-static void backlight_init(void)
-{
-	update_backlight();
-
-#ifdef CONFIG_BACKLIGHT_REQ_GPIO
-	gpio_enable_interrupt(CONFIG_BACKLIGHT_REQ_GPIO);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, backlight_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_BACKLIGHT_REQ_GPIO
-void backlight_interrupt(enum gpio_signal signal)
-{
-	update_backlight();
-}
-#endif
-
-/**
- * Host command to toggle backlight.
- *
- * The requested state will persist until the next lid-switch or request-gpio
- * transition.
- */
-static enum ec_status
-switch_command_enable_backlight(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_switch_enable_backlight *p = args->params;
-
-	enable_backlight(p->enabled);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT,
-		     switch_command_enable_backlight,
-		     EC_VER_MASK(0));
-
-
diff --git a/common/base32.c b/common/base32.c
deleted file mode 100644
index a6be8409b1..0000000000
--- a/common/base32.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Base-32 encoding/decoding */
-
-#include "common.h"
-#include "base32.h"
-#include "util.h"
-
-static const unsigned char crc5_table1[] = {
-	0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F, 0x0D, 0x03,
-	0x0B, 0x05, 0x17, 0x19, 0x1A, 0x14, 0x06, 0x08
-};
-
-static const unsigned char crc5_table0[] = {
-	0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C, 0x0F, 0x19,
-	0x14, 0x02, 0x11, 0x07, 0x1E, 0x08, 0x1B, 0x0D
-};
-
-uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc)
-{
-	uint8_t tmp = sym ^ previous_crc;
-	return crc5_table1[tmp & 0x0F] ^ crc5_table0[(tmp >> 4) & 0x0F];
-}
-
-/* A-Z0-9 with I,O,0,1 removed */
-const char base32_map[33] = "ABCDEFGHJKLMNPQRSTUVWXYZ23456789";
-
-/**
- * Decode a base32 symbol.
- *
- * @param sym Input symbol
- * @return The symbol value or -1 if error.
- */
-static int decode_sym(int sym)
-{
-	int i = 0;
-
-	for (i = 0; i < 32; i++) {
-		if (sym == base32_map[i])
-			return i;
-	}
-
-	return -1;
-}
-
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every)
-{
-	const uint8_t *src = srcbits;
-	int destlen_needed;
-	int crc = 0, crc_count = 0;
-	int didx = 0;
-	int i;
-
-	*dest = 0;
-
-	/* Make sure destination is big enough */
-	destlen_needed = (srclen_bits + 4) / 5;  /* Symbols before adding CRC */
-	if (add_crc_every) {
-		/* Must be an exact number of groups to add CRC */
-		if (destlen_needed % add_crc_every)
-			return EC_ERROR_INVAL;
-		destlen_needed += destlen_needed / add_crc_every;
-	}
-	destlen_needed++;  /* For terminating null */
-	if (destlen_chars < destlen_needed)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < srclen_bits; i += 5) {
-		int sym;
-		int sidx = i / 8;
-		int bit_offs = i % 8;
-
-		if (bit_offs <= 3) {
-			/* Entire symbol fits in that byte */
-			sym = src[sidx] >> (3 - bit_offs);
-		} else {
-			/* Use the bits we have left */
-			sym = src[sidx] << (bit_offs - 3);
-
-			/* Use the bits from the next byte, if any */
-			if (i + 1 < srclen_bits)
-				sym |= src[sidx + 1] >> (11 - bit_offs);
-		}
-
-		sym &= 0x1f;
-
-		/* Pad incomplete symbol with 0 bits */
-		if (srclen_bits - i < 5)
-			sym &= 0x1f << (5 + i - srclen_bits);
-
-		dest[didx++] = base32_map[sym];
-
-		/* Add CRC if needed */
-		if (add_crc_every) {
-			crc = crc5_sym(sym, crc);
-			if (++crc_count == add_crc_every) {
-				dest[didx++] = base32_map[crc];
-				crc_count = crc = 0;
-			}
-		}
-	}
-
-	/* Terminate string and return */
-	dest[didx] = 0;
-	return EC_SUCCESS;
-}
-
-int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
-		  int crc_after_every)
-{
-	int crc = 0, crc_count = 0;
-	int out_bits = 0;
-
-	for (; *src; src++) {
-		int sym, sbits, dbits, b;
-
-		if (isspace((unsigned char)*src) || *src == '-')
-			continue;
-
-		sym = decode_sym(*src);
-		if (sym < 0)
-			return -1;  /* Bad input symbol */
-
-		/* Check CRC if needed */
-		if (crc_after_every) {
-			if (crc_count == crc_after_every) {
-				if (crc != sym)
-					return -1;
-				crc_count = crc = 0;
-				continue;
-			} else {
-				crc = crc5_sym(sym, crc);
-				crc_count++;
-			}
-		}
-
-		/*
-		 * Stop if we're out of space.  Have to do this after checking
-		 * the CRC, or we might not check the last CRC.
-		 */
-		if (out_bits >= destlen_bits)
-			break;
-
-		/* See how many bits we get to use from this symbol */
-		sbits = MIN(5, destlen_bits - out_bits);
-		if (sbits < 5)
-			sym >>= (5 - sbits);
-
-		/* Fill up the rest of the current byte */
-		dbits = 8 - (out_bits & 7);
-		b = MIN(dbits, sbits);
-		if (dbits == 8)
-			dest[out_bits / 8] = 0;  /* Starting a new byte */
-		dest[out_bits / 8] |= (sym << (dbits - b)) >> (sbits - b);
-		out_bits += b;
-		sbits -= b;
-
-		/* Start the next byte if there's space */
-		if (sbits > 0) {
-			dest[out_bits / 8] = sym << (8 - sbits);
-			out_bits += sbits;
-		}
-	}
-
-	/* If we have CRCs, should have a full group */
-	if (crc_after_every && crc_count)
-		return -1;
-
-	return out_bits;
-}
diff --git a/common/base_state.c b/common/base_state.c
deleted file mode 100644
index 43e201cab9..0000000000
--- a/common/base_state.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "base_state.h"
-#include "console.h"
-#include "host_command.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
-
-#ifdef CONFIG_BASE_ATTACHED_SWITCH
-/* 1: base attached, 0: otherwise */
-static int base_state;
-
-int base_get_state(void)
-{
-	return base_state;
-}
-
-void base_set_state(int state)
-{
-	if (base_state == !!state)
-		return;
-
-	base_state = !!state;
-	CPRINTS("base state: %stached", state ? "at" : "de");
-	hook_notify(HOOK_BASE_ATTACHED_CHANGE);
-
-	/* Notify host of mode change. This likely will wake it up. */
-	host_set_single_event(EC_HOST_EVENT_MODE_CHANGE);
-}
-#endif
-
-static int command_setbasestate(int argc, char **argv)
-{
-	if (argc != 2)
-		return EC_ERROR_PARAM_COUNT;
-	if (argv[1][0] == 'a')
-		base_force_state(EC_SET_BASE_STATE_ATTACH);
-	else if (argv[1][0] == 'd')
-		base_force_state(EC_SET_BASE_STATE_DETACH);
-	else if (argv[1][0] == 'r')
-		base_force_state(EC_SET_BASE_STATE_RESET);
-	else
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-
-}
-DECLARE_CONSOLE_COMMAND(basestate, command_setbasestate,
-	"[attach | detach | reset]",
-	"Manually force base state to attached, detached or reset.");
-
-static enum ec_status hostcmd_setbasestate(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_set_base_state *params = args->params;
-
-	if (params->cmd > EC_SET_BASE_STATE_RESET)
-		return EC_RES_INVALID_PARAM;
-
-	base_force_state(params->cmd);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SET_BASE_STATE, hostcmd_setbasestate,
-		     EC_VER_MASK(0));
diff --git a/common/battery.c b/common/battery.c
deleted file mode 100644
index 6791e4d3a2..0000000000
--- a/common/battery.c
+++ /dev/null
@@ -1,812 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common battery command.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "ec_ec_comm_client.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "math_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CUTOFFPRINTS(info) CPRINTS("%s %s", "Battery cut off", info)
-
-/* See config.h for details */
-const static int batt_host_full_factor = CONFIG_BATT_HOST_FULL_FACTOR;
-const static int batt_host_shutdown_pct = CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE;
-
-#ifdef CONFIG_BATTERY_V2
-/*
- * Store battery information in these 2 structures. Main (lid) battery is always
- * at index 0, and secondary (base) battery at index 1.
- */
-struct ec_response_battery_static_info_v1 battery_static[CONFIG_BATTERY_COUNT];
-struct ec_response_battery_dynamic_info battery_dynamic[CONFIG_BATTERY_COUNT];
-#endif
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-
-#ifndef CONFIG_BATTERY_CUTOFF_DELAY_US
-#define CONFIG_BATTERY_CUTOFF_DELAY_US (1 * SECOND)
-#endif
-
-static enum battery_cutoff_states battery_cutoff_state =
-	BATTERY_CUTOFF_STATE_NORMAL;
-
-#endif
-
-#ifdef CONFIG_BATTERY_PRESENT_GPIO
-#ifdef CONFIG_BATTERY_PRESENT_CUSTOM
-#error "Don't define both CONFIG_BATTERY_PRESENT_CUSTOM and" \
-	"CONFIG_BATTERY_PRESENT_GPIO"
-#endif
-/**
- * Physical detection of battery.
- */
-enum battery_present battery_is_present(void)
-{
-	/* The GPIO is low when the battery is present */
-	return gpio_get_level(CONFIG_BATTERY_PRESENT_GPIO) ? BP_NO : BP_YES;
-}
-#endif
-
-static const char *get_error_text(int rv)
-{
-	if (rv == EC_ERROR_UNIMPLEMENTED)
-		return "(unsupported)";
-	else
-		return "(error)";
-}
-
-static void print_item_name(const char *name)
-{
-	ccprintf("  %-11s", name);
-}
-
-static int check_print_error(int rv)
-{
-	if (rv != EC_SUCCESS)
-		ccprintf("%s\n", get_error_text(rv));
-	return rv == EC_SUCCESS;
-}
-
-static void print_battery_status(void)
-{
-	static const char * const st[] = {"EMPTY", "FULL", "DCHG", "INIT",};
-	static const char * const al[] = {"RT", "RC", "--", "TD",
-					  "OT", "--", "TC", "OC"};
-
-	int value, i;
-
-	print_item_name("Status:");
-	if (check_print_error(battery_status(&value))) {
-		ccprintf("0x%04x", value);
-
-		/* bits 0-3 are only valid when the previous transaction
-		 * failed, so ignore them */
-
-		/* bits 4-7 are status */
-		for (i = 0; i < 4; i++)
-			if (value & (1 << (i+4)))
-				ccprintf(" %s", st[i]);
-
-		/* bits 15-8 are alarms */
-		for (i = 0; i < 8; i++)
-			if (value & (1 << (i+8)))
-				ccprintf(" %s", al[i]);
-
-		ccprintf("\n");
-	}
-}
-
-static void print_battery_strings(void)
-{
-	char text[32];
-
-	print_item_name("Manuf:");
-	if (check_print_error(battery_manufacturer_name(text, sizeof(text))))
-		ccprintf("%s\n", text);
-
-	print_item_name("Device:");
-	if (check_print_error(battery_device_name(text, sizeof(text))))
-		ccprintf("%s\n", text);
-
-	print_item_name("Chem:");
-	if (check_print_error(battery_device_chemistry(text, sizeof(text))))
-		ccprintf("%s\n", text);
-}
-
-static void print_battery_params(void)
-{
-#if defined(HAS_TASK_CHARGER)
-	/* Ask charger so that we don't need to ask battery again. */
-	const struct batt_params *batt = charger_current_battery_params();
-#else
-	/* This is for test code, where doesn't have charger task. */
-	struct batt_params _batt;
-	const struct batt_params *batt = &_batt;
-
-	battery_get_params(&_batt);
-#endif
-
-	print_item_name("Param flags:");
-	ccprintf("%08x\n", batt->flags);
-
-	print_item_name("Temp:");
-	ccprintf("0x%04x = %.1d K (%.1d C)\n",
-		 batt->temperature,
-		 batt->temperature,
-		 batt->temperature - 2731);
-
-	print_item_name("V:");
-	ccprintf("0x%04x = %d mV\n", batt->voltage, batt->voltage);
-
-	print_item_name("V-desired:");
-	ccprintf("0x%04x = %d mV\n", batt->desired_voltage,
-		 batt->desired_voltage);
-
-	print_item_name("I:");
-	ccprintf("0x%04x = %d mA", batt->current & 0xffff, batt->current);
-	if (batt->current > 0)
-		ccputs("(CHG)");
-	else if (batt->current < 0)
-		ccputs("(DISCHG)");
-	ccputs("\n");
-
-	print_item_name("I-desired:");
-	ccprintf("0x%04x = %d mA\n", batt->desired_current,
-		 batt->desired_current);
-
-	print_item_name("Charging:");
-	ccprintf("%sAllowed\n",
-		 batt->flags & BATT_FLAG_WANT_CHARGE ? "" : "Not ");
-
-	print_item_name("Charge:");
-		ccprintf("%d %%\n", batt->state_of_charge);
-
-	if (IS_ENABLED(CONFIG_CHARGER)) {
-		int value;
-
-		print_item_name("  Display:");
-		value = charge_get_display_charge();
-		ccprintf("%d.%d %%\n", value / 10, value % 10);
-	}
-}
-
-static void print_battery_info(void)
-{
-	int value;
-	int hour, minute;
-
-	print_item_name("Serial:");
-	if (check_print_error(battery_serial_number(&value)))
-		ccprintf("0x%04x\n", value);
-
-	print_item_name("V-design:");
-	if (check_print_error(battery_design_voltage(&value)))
-		ccprintf("0x%04x = %d mV\n", value, value);
-
-	print_item_name("Mode:");
-	if (check_print_error(battery_get_mode(&value)))
-		ccprintf("0x%04x\n", value);
-
-	print_item_name("Abs charge:");
-	if (check_print_error(battery_state_of_charge_abs(&value)))
-		ccprintf("%d %%\n", value);
-
-	print_item_name("Remaining:");
-	if (check_print_error(battery_remaining_capacity(&value)))
-		ccprintf("%d mAh\n", value);
-
-	print_item_name("Cap-full:");
-	if (check_print_error(battery_full_charge_capacity(&value)))
-		ccprintf("%d mAh\n", value);
-
-	print_item_name("  Design:");
-	if (check_print_error(battery_design_capacity(&value)))
-		ccprintf("%d mAh\n", value);
-
-	print_item_name("Time-full:");
-	if (check_print_error(battery_time_to_full(&value))) {
-		if (value == 65535) {
-			hour   = 0;
-			minute = 0;
-		} else {
-			hour   = value / 60;
-			minute = value % 60;
-		}
-		ccprintf("%dh:%d\n", hour, minute);
-	}
-
-	print_item_name("  Empty:");
-	if (check_print_error(battery_time_to_empty(&value))) {
-		if (value == 65535) {
-			hour   = 0;
-			minute = 0;
-		} else {
-			hour   = value / 60;
-			minute = value % 60;
-		}
-		ccprintf("%dh:%d\n", hour, minute);
-	}
-
-	print_item_name("full_factor:");
-	ccprintf("0.%d\n", batt_host_full_factor);
-
-	print_item_name("shutdown_soc:");
-	ccprintf("%d %%\n", batt_host_shutdown_pct);
-}
-
-void print_battery_debug(void)
-{
-	print_battery_status();
-	print_battery_params();
-	print_battery_strings();
-	print_battery_info();
-}
-
-static int command_battery(int argc, char **argv)
-{
-	int repeat = 1;
-	int loop;
-	int sleep_ms = 0;
-	char *e;
-
-	if (argc > 1) {
-		repeat = strtoi(argv[1], &e, 0);
-		if (*e) {
-			ccputs("Invalid repeat count\n");
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	if (argc > 2) {
-		sleep_ms = strtoi(argv[2], &e, 0);
-		if (*e) {
-			ccputs("Invalid sleep ms\n");
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	for (loop = 0; loop < repeat; loop++) {
-		print_battery_debug();
-
-		/*
-		 * Running with a high repeat count will take so long the
-		 * watchdog timer fires.  So reset the watchdog timer each
-		 * iteration.
-		 */
-		watchdog_reload();
-
-		if (sleep_ms)
-			msleep(sleep_ms);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(battery, command_battery,
-			"<repeat_count> <sleep_ms>",
-			"Print battery info");
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-int battery_is_cut_off(void)
-{
-	return (battery_cutoff_state == BATTERY_CUTOFF_STATE_CUT_OFF);
-}
-
-static void pending_cutoff_deferred(void)
-{
-	int rv;
-
-	rv = board_cut_off_battery();
-
-	if (rv == EC_RES_SUCCESS) {
-		CUTOFFPRINTS("succeeded.");
-		battery_cutoff_state = BATTERY_CUTOFF_STATE_CUT_OFF;
-	} else {
-		CUTOFFPRINTS("failed!");
-		battery_cutoff_state = BATTERY_CUTOFF_STATE_NORMAL;
-	}
-}
-DECLARE_DEFERRED(pending_cutoff_deferred);
-
-static void clear_pending_cutoff(void)
-{
-	if (extpower_is_present()) {
-		battery_cutoff_state = BATTERY_CUTOFF_STATE_NORMAL;
-		hook_call_deferred(&pending_cutoff_deferred_data, -1);
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, clear_pending_cutoff, HOOK_PRIO_DEFAULT);
-
-static enum ec_status battery_command_cutoff(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_battery_cutoff *p;
-	int rv;
-
-	if (args->version == 1) {
-		p = args->params;
-		if (p->flags & EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN) {
-			battery_cutoff_state = BATTERY_CUTOFF_STATE_PENDING;
-			CUTOFFPRINTS("at-shutdown is scheduled");
-			return EC_RES_SUCCESS;
-		}
-	}
-
-	rv = board_cut_off_battery();
-	if (rv == EC_RES_SUCCESS) {
-		CUTOFFPRINTS("is successful.");
-		battery_cutoff_state = BATTERY_CUTOFF_STATE_CUT_OFF;
-	} else {
-		CUTOFFPRINTS("has failed.");
-	}
-
-	return rv;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_CUT_OFF, battery_command_cutoff,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static void check_pending_cutoff(void)
-{
-	if (battery_cutoff_state == BATTERY_CUTOFF_STATE_PENDING) {
-		CPRINTS("Cutting off battery in %d second(s)",
-			CONFIG_BATTERY_CUTOFF_DELAY_US / SECOND);
-		hook_call_deferred(&pending_cutoff_deferred_data,
-				   CONFIG_BATTERY_CUTOFF_DELAY_US);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, check_pending_cutoff, HOOK_PRIO_LAST);
-
-static int command_cutoff(int argc, char **argv)
-{
-	int rv;
-
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "at-shutdown")) {
-			battery_cutoff_state = BATTERY_CUTOFF_STATE_PENDING;
-			return EC_SUCCESS;
-		} else {
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	rv = board_cut_off_battery();
-	if (rv == EC_RES_SUCCESS) {
-		ccprints("Battery cut off");
-		battery_cutoff_state = BATTERY_CUTOFF_STATE_CUT_OFF;
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_UNKNOWN;
-}
-DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff,
-		"[at-shutdown]",
-		"Cut off the battery output");
-#else
-int battery_is_cut_off(void)
-{
-	return 0;  /* Always return NOT cut off */
-}
-#endif  /* CONFIG_BATTERY_CUT_OFF */
-
-#ifdef CONFIG_BATTERY_VENDOR_PARAM
-static int console_command_battery_vendor_param(int argc, char **argv)
-{
-	uint32_t param;
-	uint32_t value;
-	char *e;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_INVAL;
-
-	param = strtoi(argv[1], &e, 0);
-	if (*e) {
-		ccputs("Invalid param\n");
-		return EC_ERROR_INVAL;
-	}
-
-	if (argc > 2) {
-		value = strtoi(argv[2], &e, 0);
-		if (*e) {
-			ccputs("Invalid value\n");
-			return EC_ERROR_INVAL;
-		}
-		rv = battery_set_vendor_param(param, value);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	rv = battery_get_vendor_param(param, &value);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	ccprintf("0x%08x\n", value);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(battparam, console_command_battery_vendor_param,
-			"<param> [value]",
-			"Get or set battery vendor parameters");
-
-static enum ec_status
-host_command_battery_vendor_param(struct host_cmd_handler_args *args)
-{
-	int rv;
-	const struct ec_params_battery_vendor_param *p = args->params;
-	struct ec_response_battery_vendor_param *r = args->response;
-
-	args->response_size = sizeof(*r);
-
-	if (p->mode != BATTERY_VENDOR_PARAM_MODE_GET &&
-	    p->mode != BATTERY_VENDOR_PARAM_MODE_SET)
-		return EC_RES_INVALID_PARAM;
-
-	if (p->mode == BATTERY_VENDOR_PARAM_MODE_SET) {
-		rv = battery_set_vendor_param(p->param, p->value);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	rv = battery_get_vendor_param(p->param, &r->value);
-	return rv;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_VENDOR_PARAM,
-		     host_command_battery_vendor_param,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_BATTERY_VENDOR_PARAM */
-
-#ifdef CONFIG_BATTERY_V2
-#ifdef CONFIG_HOSTCMD_BATTERY_V2
-static void battery_update(enum battery_index i);
-static enum ec_status
-host_command_battery_get_static(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_battery_static_info *p = args->params;
-	struct ec_response_battery_static_info_v1 *bat;
-
-	if (p->index < 0 || p->index >= CONFIG_BATTERY_COUNT)
-		return EC_RES_INVALID_PARAM;
-	bat = &battery_static[p->index];
-
-	battery_update(p->index);
-	if (args->version == 0) {
-		struct ec_response_battery_static_info *r = args->response;
-
-		args->response_size = sizeof(*r);
-		r->design_capacity = bat->design_capacity;
-		r->design_voltage = bat->design_voltage;
-		r->cycle_count = bat->cycle_count;
-
-		/* Truncate strings to reduced v0 size */
-		memcpy(&r->manufacturer, &bat->manufacturer_ext,
-		       sizeof(r->manufacturer));
-		r->manufacturer[sizeof(r->manufacturer) - 1] = 0;
-		memcpy(&r->model, &bat->model_ext, sizeof(r->model));
-		r->model[sizeof(r->model) - 1] = 0;
-		memcpy(&r->serial, &bat->serial_ext, sizeof(r->serial));
-		r->serial[sizeof(r->serial) - 1] = 0;
-		memcpy(&r->type, &bat->type_ext, sizeof(r->type));
-		r->type[sizeof(r->type) - 1] = 0;
-	} else {
-		/* v1 command stores the same data internally */
-		struct ec_response_battery_static_info_v1 *r = args->response;
-
-		args->response_size = sizeof(*r);
-		memcpy(r, bat, sizeof(*r));
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC,
-		     host_command_battery_get_static,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static enum ec_status
-host_command_battery_get_dynamic(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_battery_dynamic_info *p = args->params;
-	struct ec_response_battery_dynamic_info *r = args->response;
-
-	if (p->index < 0 || p->index >= CONFIG_BATTERY_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	args->response_size = sizeof(*r);
-	memcpy(r, &battery_dynamic[p->index], sizeof(*r));
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_DYNAMIC,
-		     host_command_battery_get_dynamic,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_BATTERY_V2 */
-
-#ifdef HAS_TASK_HOSTCMD
-static void battery_update(enum battery_index i)
-{
-	char *batt_str;
-	int *memmap_dcap = (int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
-	int *memmap_dvlt = (int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
-	int *memmap_ccnt = (int *)host_get_memmap(EC_MEMMAP_BATT_CCNT);
-	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
-	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
-	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
-	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-
-	/* Smart battery serial number is 16 bits */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
-	memcpy(batt_str, battery_static[i].serial_ext, EC_MEMMAP_TEXT_MAX);
-	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
-
-	/* Design Capacity of Full */
-	*memmap_dcap = battery_static[i].design_capacity;
-
-	/* Design Voltage */
-	*memmap_dvlt = battery_static[i].design_voltage;
-
-	/* Cycle Count */
-	*memmap_ccnt = battery_static[i].cycle_count;
-
-	/* Battery Manufacturer string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
-	memcpy(batt_str, battery_static[i].manufacturer_ext,
-	       EC_MEMMAP_TEXT_MAX);
-	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
-
-	/* Battery Model string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
-	memcpy(batt_str, battery_static[i].model_ext, EC_MEMMAP_TEXT_MAX);
-	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
-
-	/* Battery Type string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
-	memcpy(batt_str, battery_static[i].type_ext, EC_MEMMAP_TEXT_MAX);
-	batt_str[EC_MEMMAP_TEXT_MAX - 1] = 0;
-
-	*memmap_volt = battery_dynamic[i].actual_voltage;
-	*memmap_rate = battery_dynamic[i].actual_current;
-	*memmap_cap = battery_dynamic[i].remaining_capacity;
-	*memmap_lfcc = battery_dynamic[i].full_capacity;
-	*memmap_flags = battery_dynamic[i].flags;
-}
-
-void battery_memmap_refresh(enum battery_index index)
-{
-	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
-		battery_update(index);
-}
-
-void battery_memmap_set_index(enum battery_index index)
-{
-	if (*host_get_memmap(EC_MEMMAP_BATT_INDEX) == index)
-		return;
-
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
-	if (index < 0 || index >= CONFIG_BATTERY_COUNT)
-		return;
-
-	battery_update(index);
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = index;
-}
-
-static void battery_init(void)
-{
-	*host_get_memmap(EC_MEMMAP_BATT_INDEX) = BATT_IDX_INVALID;
-	*host_get_memmap(EC_MEMMAP_BATT_COUNT) = CONFIG_BATTERY_COUNT;
-	*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 2;
-
-	battery_memmap_set_index(BATT_IDX_MAIN);
-}
-DECLARE_HOOK(HOOK_INIT, battery_init, HOOK_PRIO_DEFAULT);
-#endif /* HAS_TASK_HOSTCMD */
-#endif /* CONFIG_BATTERY_V2 */
-
-void battery_compensate_params(struct batt_params *batt)
-{
-	int numer, denom;
-	int *remain = &(batt->remaining_capacity);
-	int full = batt->full_capacity;
-
-	if ((batt->flags & BATT_FLAG_BAD_FULL_CAPACITY) ||
-			(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY))
-		return;
-
-	if (*remain <= 0 || full <= 0)
-		return;
-
-	/* Some batteries don't update full capacity as often. */
-	if (*remain > full)
-		*remain = full;
-
-	/*
-	 * EC calculates the display SoC like how Powerd used to do. Powerd
-	 * reads the display SoC from the EC. This design allows the system to
-	 * behave consistently on a single SoC value across all power states.
-	 *
-	 * Display SoC is computed as follows:
-	 *
-	 *   actual_soc = 100 * remain / full
-	 *
-	 *		   actual_soc - shutdown_pct
-	 *   display_soc = --------------------------- x 1000
-	 *		   full_factor - shutdown_pct
-	 *
-	 *		   (100 * remain / full) - shutdown_pct
-	 *		 = ------------------------------------ x 1000
-	 *		        full_factor - shutdown_pct
-	 *
-	 *		   100 x remain - full x shutdown_pct
-	 *		 = ----------------------------------- x 1000
-	 *		   full x (full_factor - shutdown_pct)
-	 */
-	numer = 1000 * ((100 * *remain) - (full * batt_host_shutdown_pct));
-	denom = full * (batt_host_full_factor - batt_host_shutdown_pct);
-	/* Rounding (instead of truncating) */
-	batt->display_charge = (numer + denom / 2) / denom;
-	if (batt->display_charge < 0)
-		batt->display_charge = 0;
-	if (batt->display_charge > 1000)
-		batt->display_charge = 1000;
-}
-
-#ifdef CONFIG_CHARGER
-static enum ec_status battery_display_soc(struct host_cmd_handler_args *args)
-{
-	struct ec_response_display_soc *r = args->response;
-
-	r->display_soc = charge_get_display_charge();
-	r->full_factor = batt_host_full_factor * 10;
-	r->shutdown_soc = batt_host_shutdown_pct * 10;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_DISPLAY_SOC, battery_display_soc, EC_VER_MASK(0));
-#endif
-
-__overridable void board_battery_compensate_params(struct batt_params *batt)
-{
-}
-
-__attribute__((weak)) int get_battery_manufacturer_name(char *dest, int size)
-{
-	strzcpy(dest, "<unkn>", size);
-	return EC_SUCCESS;
-}
-
-__overridable int battery_get_avg_voltage(void)
-{
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-
-__overridable int battery_get_avg_current(void)
-{
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_manufacturer_name(char *dest, int size)
-{
-	return get_battery_manufacturer_name(dest, size);
-}
-
-__overridable enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-#ifdef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
-
-#if CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV < 5000 || \
-    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV
-	#error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV"
-#endif
-
-#if !((defined(CONFIG_USB_PD_TCPMV1) && defined(CONFIG_USB_PD_DUAL_ROLE)) || \
-    (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)))
-	#error "Voltage reducing requires TCPM with Policy Engine"
-#endif
-
-/*
- * Returns true if input voltage should be reduced (chipset is in S5/G3) and
- * battery is full, otherwise returns false
- */
-static bool board_wants_reduced_input_voltage(void) {
-	struct batt_params batt;
-
-	/* Chipset not in S5/G3, so we don't want to reduce voltage */
-	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return false;
-
-	battery_get_params(&batt);
-
-	/* Battery needs charge, so we don't want to reduce voltage */
-	if (batt.flags & BATT_FLAG_WANT_CHARGE)
-		return false;
-
-	return true;
-}
-
-static void reduce_input_voltage_when_full(void)
-{
-	static int saved_input_voltage = -1;
-	int max_pd_voltage_mv = pd_get_max_voltage();
-	int port;
-
-	port = charge_manager_get_active_charge_port();
-	if (port < 0 || port >= board_get_usb_pd_port_count())
-		return;
-
-	if (board_wants_reduced_input_voltage()) {
-		/*
-		 * Board wants voltage to be reduced. Apply limit if current
-		 * voltage is different. Save current voltage, it will be
-		 * restored when board wants to stop reducing input voltage.
-		 */
-		if (max_pd_voltage_mv !=
-		    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) {
-			saved_input_voltage = max_pd_voltage_mv;
-			max_pd_voltage_mv =
-			    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV;
-		}
-	} else if (saved_input_voltage != -1) {
-		/*
-		 * Board doesn't want to reduce input voltage. If current
-		 * voltage is reduced we will restore previously saved voltage.
-		 * If current voltage is different we will respect newer value.
-		 */
-		if (max_pd_voltage_mv ==
-		    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV)
-			max_pd_voltage_mv = saved_input_voltage;
-
-		saved_input_voltage = -1;
-	}
-
-	if (pd_get_max_voltage() != max_pd_voltage_mv)
-		pd_set_external_voltage_limit(port, max_pd_voltage_mv);
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-#endif
-
-void battery_validate_params(struct batt_params *batt)
-{
-	/*
-	 * TODO(crosbug.com/p/27527). Sometimes the battery thinks its
-	 * temperature is 6280C, which seems a bit high. Let's ignore
-	 * anything above the boiling point of tungsten until this bug
-	 * is fixed. If the battery is really that warm, we probably
-	 * have more urgent problems.
-	 */
-	if (batt->temperature > CELSIUS_TO_DECI_KELVIN(5660)) {
-		CPRINTS("ignoring ridiculous batt.temp of %dC",
-			 DECI_KELVIN_TO_CELSIUS(batt->temperature));
-		batt->flags |= BATT_FLAG_BAD_TEMPERATURE;
-	}
-
-	/* If the battery thinks it's above 100%, don't believe it */
-	if (batt->state_of_charge > 100) {
-		CPRINTS("ignoring ridiculous batt.soc of %d%%",
-			batt->state_of_charge);
-		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-	}
-}
diff --git a/common/battery_fuel_gauge.c b/common/battery_fuel_gauge.c
deleted file mode 100644
index 528713d68f..0000000000
--- a/common/battery_fuel_gauge.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery fuel gauge parameters
- */
-
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-
-/* Get type of the battery connected on the board */
-static int get_battery_type(void)
-{
-	char manuf_name[32], device_name[32];
-	int i;
-	static enum battery_type battery_type = BATTERY_TYPE_COUNT;
-
-	/*
-	 * If battery_type is not the default value, then can return here
-	 * as there is no need to query the fuel gauge.
-	 */
-	if (battery_type != BATTERY_TYPE_COUNT)
-		return battery_type;
-
-	/* Get the manufacturer name. If can't read then just exit */
-	if (battery_manufacturer_name(manuf_name, sizeof(manuf_name)))
-		return battery_type;
-
-	/*
-	 * Compare the manufacturer name read from the fuel gauge to the
-	 * manufacturer names defined in the board_battery_info table. If
-	 * a device name has been specified in the board_battery_info table,
-	 * then both the manufacturer and device name must match.
-	 */
-	for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
-		const struct fuel_gauge_info * const fuel_gauge =
-			&board_battery_info[i].fuel_gauge;
-		int len = 0;
-
-		if (strcasecmp(manuf_name, fuel_gauge->manuf_name))
-			continue;
-
-		if (fuel_gauge->device_name != NULL) {
-
-			if (battery_device_name(device_name,
-						sizeof(device_name)))
-				continue;
-
-			len = strlen(fuel_gauge->device_name);
-			if (strncasecmp(device_name, fuel_gauge->device_name,
-						len))
-				continue;
-		}
-
-		CPRINTS("found batt:%s", fuel_gauge->manuf_name);
-		battery_type = i;
-		break;
-	}
-
-	return battery_type;
-}
-
-__overridable int board_get_default_battery_type(void)
-{
-	return DEFAULT_BATTERY_TYPE;
-}
-
-/*
- * Initialize the battery type for the board.
- *
- * The first call to battery_get_info() is when the charger task starts, so
- * initialize the battery type as soon as I2C is initialized.
- */
-static void init_battery_type(void)
-{
-	if (get_battery_type() == BATTERY_TYPE_COUNT)
-		CPRINTS("battery not found");
-}
-DECLARE_HOOK(HOOK_INIT, init_battery_type, HOOK_PRIO_INIT_I2C + 1);
-
-static inline const struct board_batt_params *get_batt_params(void)
-{
-	int type = get_battery_type();
-
-	return &board_battery_info[type == BATTERY_TYPE_COUNT ?
-		board_get_default_battery_type() : type];
-}
-
-const struct battery_info *battery_get_info(void)
-{
-	return &get_batt_params()->batt_info;
-}
-
-int cut_off_battery_block_write(const struct ship_mode_info *ship_mode)
-{
-	int rv;
-
-	uint8_t cutdata[3] = {
-		0x02,
-		ship_mode->reg_data[0] & 0xFF,
-		ship_mode->reg_data[0] >> 8,
-	};
-
-	/* SMBus protocols are block write, which include byte count
-	 * byte. Byte count segments are required to communicate
-	 * required action and the number of data bytes.
-	 * Due to ship mode command requires writing data values twice
-	 * to cutoff the battery, so byte count is 0x02.
-	 */
-	rv = sb_write_block(ship_mode->reg_addr, cutdata, sizeof(cutdata));
-	if (rv)
-		return rv;
-
-	/* Use the next set of values */
-	cutdata[1] = ship_mode->reg_data[1] & 0xFF;
-	cutdata[2] = ship_mode->reg_data[1] >> 8;
-
-	return sb_write_block(ship_mode->reg_addr, cutdata, sizeof(cutdata));
-}
-
-int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode)
-{
-	int rv;
-
-	/* Ship mode command requires writing 2 data values */
-	rv = sb_write(ship_mode->reg_addr, ship_mode->reg_data[0]);
-	if (rv)
-		return rv;
-
-	return sb_write(ship_mode->reg_addr, ship_mode->reg_data[1]);
-}
-
-int board_cut_off_battery(void)
-{
-	int rv;
-	int type = get_battery_type();
-
-	/* If battery type is unknown can't send ship mode command */
-	if (type == BATTERY_TYPE_COUNT)
-		return EC_RES_ERROR;
-
-	if (board_battery_info[type].fuel_gauge.ship_mode.wb_support)
-		rv = cut_off_battery_block_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
-	else
-		rv = cut_off_battery_sb_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
-
-	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-
-enum ec_error_list battery_sleep_fuel_gauge(void)
-{
-	const struct sleep_mode_info *sleep_command;
-	int type = get_battery_type();
-
-	/* Sleep entry command must be supplied as it will vary by gauge */
-	if (type == BATTERY_TYPE_COUNT)
-		return EC_ERROR_UNKNOWN;
-
-	sleep_command = &board_battery_info[type].fuel_gauge.sleep_mode;
-
-	if (!sleep_command->sleep_supported)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return sb_write(sleep_command->reg_addr, sleep_command->reg_data);
-}
-
-static enum ec_error_list battery_get_fet_status_regval(int *regval)
-{
-	int rv;
-	uint8_t data[6];
-	int type = get_battery_type();
-
-	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
-		/* Still don't know, so return here */
-		return EC_ERROR_BUSY;
-	}
-
-	/* Read the status of charge/discharge FETs */
-	if (board_battery_info[type].fuel_gauge.fet.mfgacc_support == 1) {
-		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				    SB_ALT_MANUFACTURER_ACCESS, data,
-				    sizeof(data));
-		/* Get the lowest 16bits of the OperationStatus() data */
-		*regval = data[2] | data[3] << 8;
-	} else
-		rv = sb_read(board_battery_info[type].fuel_gauge.fet.reg_addr,
-			     regval);
-
-	return rv;
-}
-
-int battery_is_charge_fet_disabled(void)
-{
-	int rv;
-	int reg;
-	int type = get_battery_type();
-
-	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
-		/* Still don't know, so return here */
-		return -1;
-	}
-
-	/*
-	 * If the CFET mask hasn't been defined, assume that it's not disabled.
-	 */
-	if (!board_battery_info[type].fuel_gauge.fet.cfet_mask)
-		return 0;
-
-	rv = battery_get_fet_status_regval(&reg);
-	if (rv)
-		return -1;
-
-	return (reg & board_battery_info[type].fuel_gauge.fet.cfet_mask) ==
-	       board_battery_info[type].fuel_gauge.fet.cfet_off_val;
-}
-
-/*
- * This function checks the charge/discharge FET status bits. Each battery type
- * supported provides the register address, mask, and disconnect value for these
- * 2 FET status bits. If the FET status matches the disconnected value, then
- * BATTERY_DISCONNECTED is returned. This function is required to handle the
- * cases when the fuel gauge is awake and will return a non-zero state of
- * charge, but is not able yet to provide power (i.e. discharge FET is not
- * active). By returning BATTERY_DISCONNECTED the AP will not be powered up
- * until either the external charger is able to provided enough power, or
- * the battery is able to provide power and thus prevent a brownout when the
- * AP is powered on by the EC.
- */
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	int reg;
-	int type = get_battery_type();
-
-	/* If battery type is not known, can't check CHG/DCHG FETs */
-	if (type == BATTERY_TYPE_COUNT) {
-		/* Still don't know, so return here */
-		return BATTERY_DISCONNECT_ERROR;
-	}
-
-	if (battery_get_fet_status_regval(&reg))
-		return BATTERY_DISCONNECT_ERROR;
-
-	if ((reg & board_battery_info[type].fuel_gauge.fet.reg_mask) ==
-	    board_battery_info[type].fuel_gauge.fet.disconnect_val) {
-		CPRINTS("Batt disconnected: reg 0x%04x mask 0x%04x disc 0x%04x",
-			reg,
-			board_battery_info[type].fuel_gauge.fet.reg_mask,
-			board_battery_info[type].fuel_gauge.fet.disconnect_val);
-		return BATTERY_DISCONNECTED;
-	}
-
-	return BATTERY_NOT_DISCONNECTED;
-}
-
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-int battery_imbalance_mv(void)
-{
-	int type = get_battery_type();
-
-	/*
-	 * If battery type is unknown, we cannot safely access non-standard
-	 * registers.
-	 */
-	return (type == BATTERY_TYPE_COUNT) ? 0 :
-		board_battery_info[type].fuel_gauge.imbalance_mv();
-}
-
-int battery_default_imbalance_mv(void)
-{
-	return 0;
-}
-#endif /* CONFIG_BATTERY_MEASURE_IMBALANCE */
diff --git a/common/blink.c b/common/blink.c
deleted file mode 100644
index ed16146f5a..0000000000
--- a/common/blink.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This is a confidence check program for boards that have LEDs. */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-
-#ifndef CONFIG_BLINK_LEDS
-	#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK.
-#endif
-
-static const enum gpio_signal leds[] = { CONFIG_BLINK_LEDS };
-
-BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int)*8, "Too many LEDs to drive.");
-BUILD_ASSERT(ARRAY_SIZE(leds) > 0, "Must have at least one LED to blink.");
-
-static void blink(void)
-{
-	static int led_values;
-
-	int i;
-	for (i = 0; i < ARRAY_SIZE(leds); i++)
-		gpio_set_level(leds[i], BIT(i) & led_values);
-	led_values++;
-}
-DECLARE_HOOK(HOOK_TICK, blink, HOOK_PRIO_DEFAULT);
diff --git a/common/bluetooth_le.c b/common/bluetooth_le.c
deleted file mode 100644
index 2e68893223..0000000000
--- a/common/bluetooth_le.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h"
-#include "util.h"
-#include "console.h"
-
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
-
-/*
- * Convert from BLE Channel to frequency
- *
- * Bluetooth 4.1 Vol 6 pg 36 4.1 Table 1.1
- */
-
-#define CHAN_0_MHZ      2404
-#define CHAN_11_MHZ     2428
-#define CHAN_37_MHZ     2402
-#define CHAN_38_MHZ     2426
-#define CHAN_39_MHZ     2480
-
-int chan2freq(int channel)
-{
-	int freq;
-
-	ASSERT(channel < 40 && channel >= 0);
-
-	switch (channel) {
-	case 37: /* Advertising */
-		freq = CHAN_37_MHZ;
-		break;
-	case 38: /* Advertising */
-		freq = CHAN_38_MHZ;
-		break;
-	case 39: /* Advertising */
-		freq = CHAN_39_MHZ;
-		break;
-	default:
-		/* Data Channels */
-		if (channel < 11)
-			freq = channel * 2 + CHAN_0_MHZ;
-		else
-			freq = (channel - 11) * 2 + CHAN_11_MHZ;
-	}
-	return freq;
-}
-
-/* BLE 4.1 Vol 6 2.3.3.1 */
-
-void fill_remapping_table(struct remapping_table *rt, uint8_t map[5],
-			  int hop_increment)
-{
-	int i;
-
-	rt->num_used_channels = 0;
-	rt->last_unmapped_channel = 0;
-	rt->hop_increment = hop_increment;
-
-	for (i = 0; i < 37; i++)
-		if (map[i / 8] & (1 << (i % 8)))
-			rt->remapping_index[rt->num_used_channels++] = i;
-	memcpy(rt->map, map, sizeof(rt->map));
-}
-
-/* BLE 4.1 Vol 6 4.5.8 */
-uint8_t get_next_data_channel(struct remapping_table *rt)
-{
-	rt->last_unmapped_channel =
-		(rt->last_unmapped_channel + rt->hop_increment) % 37;
-
-	/* Check if the channel is mapped */
-	if (rt->map[rt->last_unmapped_channel / 8] &
-			(1 << (rt->last_unmapped_channel % 8)))
-		return rt->last_unmapped_channel;
-	else
-		return rt->remapping_index
-			[rt->last_unmapped_channel % rt->num_used_channels];
-}
-
-/* BLE 4.1 Vol 3 Part C 11 */
-
-/* Pack advertising structures for sending */
-uint8_t *pack_adv(uint8_t *dest, int length, int type, const uint8_t *data)
-{
-	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
-	/* Add the structure type */
-	dest[1] = (uint8_t)type;
-	/* Add the data */
-	memcpy(&dest[2], data, length);
-
-	/* Return a pointer to the next structure */
-	return &dest[2+length];
-}
-
-uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data)
-{
-	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
-	/* Add the structure type */
-	dest[1] = (uint8_t)type;
-	/* Add the data */
-	memcpy(&dest[2], &data, length);
-
-	/* Return a pointer to the next structure */
-	return &dest[2+length];
-}
-
-uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr)
-{
-	memcpy(&dest[0], &addr, BLUETOOTH_ADDR_OCTETS);
-
-	/* Return a pointer to the next structure */
-	return &dest[BLUETOOTH_ADDR_OCTETS];
-}
-
-/* Parse advertising structures that have been received */
-const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type,
-			  const uint8_t **data)
-{
-	/* Get the structure length */
-	*length = *(src++);
-	/* Get the structure type */
-	*type = *(src++);
-	/* Get the data */
-	*data = src;
-
-	/* Return a pointer to the next structure */
-	return src + *length;
-}
-
-static void mem_dump(uint8_t *mem, int len)
-{
-	int i;
-	uint8_t value;
-
-	for (i = 0; i < len; i++) {
-		value = mem[i];
-		if (i % 8 == 0)
-			CPRINTF("\n%pP: %02x", &mem[i], value);
-		else
-			CPRINTF(" %02x", value);
-	}
-	CPRINTF("\n");
-}
-
-void dump_ble_addr(uint8_t *mem, char *name)
-{
-	int i;
-
-	for (i = 5; i > 0; i--)
-		CPRINTF("%02x.", mem[i]);
-	CPRINTF("%02x %s\n", mem[0], name);
-}
-
-void dump_ble_packet(struct ble_pdu *ble_p)
-{
-	int curr_offs;
-
-	if (ble_p->header_type_adv) {
-		CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n",
-			ble_p, ble_p->header.adv.type, ble_p->header.adv.length,
-			(ble_p->header.adv.txaddr ? " TXADDR" : ""),
-			(ble_p->header.adv.rxaddr ? " RXADDR" : ""));
-
-		curr_offs = 0;
-
-		if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) {
-			dump_ble_addr(ble_p->payload, "ScanA");
-			curr_offs += BLUETOOTH_ADDR_OCTETS;
-		} else if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) {
-			dump_ble_addr(ble_p->payload, "InitA");
-			curr_offs += BLUETOOTH_ADDR_OCTETS;
-		}
-		/* All packets have AdvA */
-		dump_ble_addr(ble_p->payload + curr_offs, "AdvA");
-		curr_offs += BLUETOOTH_ADDR_OCTETS;
-
-		if (ble_p->header.adv.type ==
-		    BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			dump_ble_addr(ble_p->payload + curr_offs, "InitA");
-		else
-			mem_dump(ble_p->payload + curr_offs,
-				 ble_p->header.adv.length - curr_offs);
-	} else { /* Data PDUs */
-		CPRINTF("BLE data packet @%pP: LLID %d,"
-			" nesn %d, sn %d, md %d, length %d\n",
-			ble_p, ble_p->header.data.llid, ble_p->header.data.nesn,
-			ble_p->header.data.sn, ble_p->header.data.md,
-			ble_p->header.data.length);
-		mem_dump(ble_p->payload, ble_p->header.data.length);
-	}
-}
-
diff --git a/common/body_detection.c b/common/body_detection.c
deleted file mode 100644
index 4fbc88e852..0000000000
--- a/common/body_detection.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accelgyro.h"
-#include "body_detection.h"
-#include "console.h"
-#include "hwtimer.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-static struct motion_sensor_t *body_sensor =
-	&motion_sensors[CONFIG_BODY_DETECTION_SENSOR];
-
-static int window_size = CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE;
-static uint64_t var_threshold_scaled, confidence_delta_scaled;
-static int stationary_timeframe;
-
-static int history_idx;
-static enum body_detect_states motion_state = BODY_DETECTION_OFF_BODY;
-
-static bool history_initialized;
-static bool body_detect_enable;
-STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) bool spoof_enable;
-
-static struct body_detect_motion_data
-{
-	int history[CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE]; /* acceleration */
-	int sum;              /* sum(history) */
-	uint64_t n2_variance; /* n^2 * var(history) */
-} data[2]; /* motion data for X-axis and Y-axis */
-
-/*
- * This function will update new variance and new sum according to incoming
- * value, previous value, previous sum and previous variance.
- * In order to prevent inaccuracy, we use integer to calculate instead of float
- *
- * n: window size
- * x: data in the old window
- * x': data in the new window
- * x_0: oldest value in the window, will be replaced by x_n
- * x_n: new coming value
- *
- * n^2 * var(x') = n^2 * var(x) + (x_n - x_0) *
- *                 (n * (x_n + x_0) - sum(x') - sum(x))
- */
-static void update_motion_data(struct body_detect_motion_data *x, int x_n)
-{
-	const int n = window_size;
-	const int x_0 = x->history[history_idx];
-	const int sum_diff = x_n - x_0;
-	const int new_sum = x->sum + sum_diff;
-
-	x->n2_variance += sum_diff *
-			  ((int64_t)n * (x_n + x_0) - new_sum - x->sum);
-	x->sum = new_sum;
-	x->history[history_idx] = x_n;
-}
-
-/* Update motion data of X, Y with new sensor data. */
-static void update_motion_variance(void)
-{
-	update_motion_data(&data[X], body_sensor->xyz[X]);
-	update_motion_data(&data[Y], body_sensor->xyz[Y]);
-	history_idx = (history_idx + 1 >= window_size) ? 0 : history_idx + 1;
-}
-
-/* return Var(X) + Var(Y) */
-static uint64_t get_motion_variance(void)
-{
-	return (data[X].n2_variance + data[Y].n2_variance)
-		/ window_size / window_size;
-}
-
-static int calculate_motion_confidence(uint64_t var)
-{
-	if (var < var_threshold_scaled - confidence_delta_scaled)
-		return 0;
-	if (var > var_threshold_scaled + confidence_delta_scaled)
-		return 100;
-	return 100 * (var - var_threshold_scaled + confidence_delta_scaled) /
-		(2 * confidence_delta_scaled);
-}
-
-/* Change the motion state and commit the change to AP. */
-void body_detect_change_state(enum body_detect_states state, bool spoof)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) && spoof_enable && !spoof)
-		return;
-	if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
-		struct ec_response_motion_sensor_data vector = {
-			.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO,
-			.activity_data = {
-				.activity = MOTIONSENSE_ACTIVITY_BODY_DETECTION,
-				.state = state,
-			},
-			.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
-		};
-		motion_sense_fifo_stage_data(&vector, NULL, 0,
-				__hw_clock_source_read());
-		motion_sense_fifo_commit_data();
-	}
-	/* change the motion state */
-	motion_state = state;
-	if (state == BODY_DETECTION_ON_BODY) {
-		/* reset time counting of stationary */
-		stationary_timeframe = 0;
-	}
-	/* state changing log */
-	CPRINTS("body_detect changed state to: %s body",
-		motion_state ? "on" : "off");
-}
-
-enum body_detect_states body_detect_get_state(void)
-{
-	return motion_state;
-}
-
-/* Determine window size for 1 second by sensor data rate. */
-static void determine_window_size(int odr)
-{
-	window_size = odr / 1000;
-	/* Normally, window_size should not exceed MAX_WINDOW_SIZE. */
-	if (window_size > CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE) {
-		/* This will cause window size not enough for 1 second */
-		CPRINTS("ODR exceeds CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE");
-		window_size = CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE;
-	}
-}
-
-/* Determine variance threshold scale by range and resolution. */
-static void determine_threshold_scale(int range, int resolution, int rms_noise)
-{
-	/*
-	 * range:              g
-	 * resolution:         bits
-	 * data_1g:            LSB/g
-	 * data_1g / 9800:     LSB/(mm/s^2)
-	 * (data_1g / 9800)^2: (LSB^2)/(mm^2/s^4), which number of
-	 *                     var(sensor data) will represents 1 (mm^2/s^4)
-	 * rms_noise:          ug
-	 * var_noise:          mm^2/s^4
-	 */
-	const int data_1g = BIT(resolution - 1) / range;
-	const int multiplier = POW2(data_1g);
-	const int divisor = POW2(9800);
-	/*
-	 * We are measuring the var(X) + var(Y), so theoretically, the
-	 * var(noise) should be 2 * rms_noise^2. However, in most case, on a
-	 * very stationary plane, the average of var(noise) are less than 2 *
-	 * rms_noise^2. We can multiply the rms_noise^2 with the
-	 * CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR / 100.
-	 */
-	const int var_noise = POW2((uint64_t)rms_noise) *
-			      CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR * POW2(98)
-			      / 100 / POW2(10000);
-
-	var_threshold_scaled = (uint64_t)
-		(CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) *
-		multiplier / divisor;
-	confidence_delta_scaled = (uint64_t)
-		CONFIG_BODY_DETECTION_CONFIDENCE_DELTA *
-		multiplier / divisor;
-}
-
-void body_detect_reset(void)
-{
-	int odr = body_sensor->drv->get_data_rate(body_sensor);
-	int resolution = body_sensor->drv->get_resolution(body_sensor);
-	int rms_noise = body_sensor->drv->get_rms_noise(body_sensor);
-
-	body_detect_change_state(BODY_DETECTION_ON_BODY, false);
-	/*
-	 * The sensor is suspended since its ODR is 0,
-	 * there is no need to reset until sensor is up again
-	 */
-	if (odr == 0)
-		return;
-	determine_window_size(odr);
-	determine_threshold_scale(body_sensor->current_range,
-				  resolution, rms_noise);
-	/* initialize motion data and state */
-	memset(data, 0, sizeof(data));
-	history_idx = 0;
-	history_initialized = 0;
-}
-
-void body_detect(void)
-{
-	uint64_t motion_var;
-	int motion_confidence;
-
-	if (!body_detect_enable)
-		return;
-
-	update_motion_variance();
-	if (!history_initialized) {
-		if (history_idx == window_size - 1)
-			history_initialized = 1;
-		return;
-	}
-
-	motion_var = get_motion_variance();
-	motion_confidence = calculate_motion_confidence(motion_var);
-	switch (motion_state) {
-	case BODY_DETECTION_OFF_BODY:
-		if (motion_confidence > CONFIG_BODY_DETECTION_ON_BODY_CON)
-			body_detect_change_state(BODY_DETECTION_ON_BODY, false);
-		break;
-	case BODY_DETECTION_ON_BODY:
-		stationary_timeframe += 1;
-		/* confidence exceeds the limit, reset time counting */
-		if (motion_confidence >= CONFIG_BODY_DETECTION_OFF_BODY_CON)
-			stationary_timeframe = 0;
-		/* if no motion for enough time, change state to off_body */
-		if (stationary_timeframe >=
-		    CONFIG_BODY_DETECTION_STATIONARY_DURATION * window_size)
-			body_detect_change_state(BODY_DETECTION_OFF_BODY,
-						 false);
-		break;
-	}
-}
-
-void body_detect_set_enable(int enable)
-{
-	body_detect_enable = enable;
-	body_detect_change_state(BODY_DETECTION_ON_BODY, false);
-}
-
-int body_detect_get_enable(void)
-{
-	return body_detect_enable;
-}
-
-#ifdef CONFIG_ACCEL_SPOOF_MODE
-void body_detect_set_spoof(int enable)
-{
-	spoof_enable = enable;
-	/* After disabling spoof mode, commit current state. */
-	if (!enable)
-		body_detect_change_state(motion_state, false);
-}
-
-bool body_detect_get_spoof(void)
-{
-	return spoof_enable;
-}
-#endif
diff --git a/common/btle_hci_controller.c b/common/btle_hci_controller.c
deleted file mode 100644
index cc5b872b19..0000000000
--- a/common/btle_hci_controller.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "btle_hci_int.h"
-#include "btle_hci2.h"
-#include "bluetooth_le_ll.h"
-#include "console.h"
-
-#ifdef CONFIG_BLUETOOTH_HCI_DEBUG
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_HCI, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ## args)
-
-#else /* CONFIG_BLUETOOTH_HCI_DEBUG */
-
-#define CPUTS(outstr)
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-
-#endif /* CONFIG_BLUETOOTH_HCI_DEBUG */
-
-static uint64_t hci_event_mask;
-static uint64_t hci_le_event_mask;
-
-#define MAX_MESSAGE 24
-
-#define STATUS  (return_params[0])
-#define RPARAMS (&(return_params[1]))
-
-void hci_cmd(uint8_t *hciCmdbuf)
-{
-	static struct hciCmdHdr *hdr;
-	static uint8_t *params;
-	static uint8_t return_params[32];
-
-	uint8_t rparam_count = 1; /* Just status */
-	uint16_t event = HCI_EVT_Command_Complete; /* default */
-
-	STATUS = 0xff;
-
-	hdr = (struct hciCmdHdr *)hciCmdbuf;
-	params = hciCmdbuf + sizeof(struct hciCmdHdr);
-
-	CPRINTF("opcode %x OGF %d OCF %d\n", hdr->opcode,
-		CMD_GET_OGF(hdr->opcode), CMD_GET_OCF(hdr->opcode));
-	if (hdr->paramLen) {
-		int i;
-
-		CPRINTF("paramLen %d\n", hdr->paramLen);
-		for (i = 0; i < hdr->paramLen; i++)
-			CPRINTF("%x ", params[i]);
-		CPRINTF("\n");
-	}
-
-	switch (hdr->opcode) {
-	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Reset):
-		STATUS = ll_reset();
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Set_Event_Mask):
-		if (hdr->paramLen != sizeof(hci_event_mask))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = HCI_SUCCESS;
-		memcpy(&hci_event_mask, params, sizeof(hci_event_mask));
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Read_Transmit_Power_Level):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Features):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Commands):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Version_Information):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_BD_ADDR):
-	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Read_Remote_Version_Information):
-	case CMD_MAKE_OPCODE(HCI_OGF_Status,
-				HCI_CMD_Read_RSSI):
-		event = 0;
-	break;
-
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Event_Mask):
-		if (hdr->paramLen != sizeof(hci_le_event_mask))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = HCI_SUCCESS;
-		memcpy(&hci_le_event_mask, params, sizeof(hci_le_event_mask));
-	break;
-
-	/* LE Information */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Buffer_Size):
-		if (hdr->paramLen != 0)
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_read_buffer_size(RPARAMS);
-		rparam_count = sizeof(struct hciCmplLeReadBufferSize);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Local_Supported_Features):
-		if (hdr->paramLen != 0)
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_read_local_supported_features(RPARAMS);
-		rparam_count =
-			sizeof(struct hciCmplLeReadLocalSupportedFeatures);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Supported_States):
-		if (hdr->paramLen != 0)
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_read_supported_states(RPARAMS);
-		rparam_count = sizeof(struct hciCmplLeReadSupportedStates);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Host_Channel_Classification):
-		if (hdr->paramLen !=
-		    sizeof(struct hciLeSetHostChannelClassification))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_set_host_channel_classification(params);
-	break;
-
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Random_Address):
-		if (hdr->paramLen != sizeof(struct hciLeSetRandomAddress))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_set_random_address(params);
-	break;
-
-	/* Advertising */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertise_Enable):
-		STATUS = ll_set_advertising_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertising_Data):
-		STATUS = ll_set_adv_data(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Adv_Params):
-		if (hdr->paramLen != sizeof(struct hciLeSetAdvParams))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_set_advertising_params(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Adv_Channel_TX_Power):
-		STATUS = ll_read_tx_power();
-		rparam_count = sizeof(struct hciCmplLeReadAdvChannelTxPower);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Response_Data):
-		STATUS = ll_set_scan_response_data(params);
-	break;
-
-	/* Connections */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Remote_Used_Features):
-		if (hdr->paramLen != sizeof(struct hciLeReadRemoteUsedFeatures))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_read_remote_used_features(params);
-		event = HCI_EVT_Command_Status;
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Disconnect):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Connection_Update):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection_Cancel):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Channel_Map):
-		event = 0;
-	break;
-
-	/* Encryption */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Encrypt):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Negative_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Rand):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Start_Encryption):
-		event = 0;
-	break;
-
-	/* Scanning */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Enable):
-		if (hdr->paramLen != sizeof(struct hciLeSetScanEnable))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_set_scan_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Parameters):
-		if (hdr->paramLen != sizeof(struct hciLeSetScanParams))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_set_scan_params(params);
-	break;
-
-	/* Allow List */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Clear_Allow_List):
-		if (hdr->paramLen != 0)
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_clear_allow_list();
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Allow_List_Size):
-		if (hdr->paramLen != 0)
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_read_allow_list_size(RPARAMS);
-		rparam_count = sizeof(struct hciCmplLeReadAllowListSize);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Add_Device_To_Allow_List):
-		if (hdr->paramLen != sizeof(struct hciLeAddDeviceToAllowList))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_add_device_to_allow_list(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Remove_Device_From_Allow_List):
-		if (hdr->paramLen !=
-				sizeof(struct hciLeRemoveDeviceFromAllowList))
-			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
-		else
-			STATUS = ll_remove_device_from_allow_list(params);
-	break;
-
-	/* RFPHY Testing Support */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Receiver_Test):
-		STATUS = ll_receiver_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Transmitter_Test):
-		STATUS = ll_transmitter_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Test_End):
-		STATUS = ll_test_end(RPARAMS);
-		rparam_count = sizeof(struct hciCmplLeTestEnd);
-	break;
-
-	default:
-		STATUS = HCI_ERR_Unknown_HCI_Command;
-	break;
-	}
-
-	hci_event(event, rparam_count, return_params);
-}
-
-void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len)
-{
-	int i;
-
-	/* Enqueue hdr, len, len bytes of data */
-	CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n",
-		len, hdr & ACL_HDR_MASK_CONN_ID,
-		hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
-}
-
-void hci_acl_from_host(uint8_t *hciAclbuf)
-{
-	struct hciAclHdr *hdr = (struct hciAclHdr *)hciAclbuf;
-	uint8_t *data = hciAclbuf + sizeof(struct hciAclHdr);
-	int i;
-
-	/* Send the data to the link layer */
-	CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n",
-		hdr->len, hdr->hdr & ACL_HDR_MASK_CONN_ID,
-		hdr->hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < hdr->len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
-}
-
-/*
- * Required Events
- *
- * HCI_EVT_Command_Complete
- * HCI_EVT_Command_Status
- * HCI_EVTLE_Advertising_Report
- * HCI_EVT_Disconnection_Complete
- * HCI_EVTLE_Connection_Complete
- * HCI_EVTLE_Connection_Update_Complete
- * HCI_EVTLE_Read_Remote_Used_Features_Complete
- * HCI_EVT_Number_Of_Completed_Packets
- * HCI_EVT_Read_Remote_Version_Complete
- * HCI_EVT_Encryption_Change
- * HCI_EVT_Encryption_Key_Refresh_Complete
- * HCI_EVTLE_Long_Term_Key_Request
- */
-void hci_event(uint8_t event_code, uint8_t len, uint8_t *params)
-{
-	int i;
-
-	/* Copy it to the queue. */
-	CPRINTF("Event 0x%x len %d\n", event_code, len);
-	for (i = 0; i < len; i++)
-		CPRINTF("%x ", params[i]);
-	CPRINTF("\n");
-}
-
-#ifdef CONFIG_BLUETOOTH_HCI_DEBUG
-
-/*
- * LE_Set_Advertising_Data
- * hcitool lcmd 0x2008 19 0x42410907 0x46454443 0x3c11903 0x3050102 0x181203
- * hcitool cmd 8 8 7 9 41 42 43 44 45 46 3 19 c1 3 2 1 5 3 3 12 18
- *
- * hcitool lcmd 0x2008 18 0x42410906 0x03454443 0x203c119 0x3030501 0x1812
- * hcitool cmd 8 8 6 9 41 42 43 44 45 3 19 c1 3 2 1 5 3 3 12 18
- */
-uint8_t adv0[19] = {0x07, 0x09, 'A', 'B', 'C', 'D', 'E', 'F', /* Name */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
-
-uint8_t adv1[18] = {0x06, 0x09, 'A', 'B', 'C', 'D', 'E',      /* Name */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
-
-uint8_t *adverts[] = {adv0, adv1};
-uint8_t adv_lengths[] = {sizeof(adv0), sizeof(adv1)};
-
-uint8_t scan0[4] = {0x03, 0x08, 'A', 'B'}; /* Short Name */
-
-uint8_t scan1[] = {};                         /* Empty */
-
-uint8_t *scans[] = {scan0, scan1};
-uint8_t scan_lengths[] = {sizeof(scan0), sizeof(scan1)};
-
-/*
- * LE_Set_Adv_Params
- * hcitool lcmd 0x2006 15 0x010000f0 0xb0010100 0xb4b3b2b1 0x0007c5
- * hcitool cmd 8 6 f0 0 0 1 0 1 1 b0 b1 b2 b3 b4 c5 7 0
- */
-uint8_t adv_param0[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x00,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t adv_param1[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x02,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t *adv_params[] = {adv_param0, adv_param1};
-
-/*
- * LE Information
- *
- * LE Read Buffer Size
- * hcitool cmd 8 2
- *
- * LE_Read_Local_Supported_Features
- * hcitool cmd 8 3
- *
- * LE_Read_Supported_States
- * hcitool cmd 8 1c
- *
- * LE_Set_Host_Channel_Classification
- * hcitool cmd 8 14 0 1 2 3 4
- * hcitool cmd 8 14 ff ff 02 ff 1f
- */
-
-/*
- * Scan commands:
- *
- * Set Scan Parameters:
- * hcitool cmd 8 B 0 10 0 10 0 0 0 (passive 10 10 public all)
- * hcitool lcmd 0x200B 7 0x10001000 0x0000 (passive 10 10 public all)
- *
- * hcitool cmd 8 B 1 30 0 20 0 1 1 (active 30 20 rand white)
- * hcitool lcmd 0x200B 7 0x20003001 0x0101 (active 30 20 rand white)
- *
- * Set Scan Enable:
- * hcitool cmd 8 C 0 0 (disabled)
- * hcitool cmd 8 C 1 0 (enabled no_filtering)
- * hcitool cmd 8 C 1 1 (enabled filter_duplicates)
- *
- */
-
-/* Allow list commands:
- *
- * Read allow list size
- * hcitool cmd 8 F
- *
- * Clear allow list
- * hcitool cmd 8 10
- *
- * Add device to allow list (Public C5A4A3A2A1A0)
- * hcitool cmd 8 11 0 a0 a1 a2 a3 a4 c5
- * hcitool lcmd 0x2011 7 0xA2A1A000 0xC5A4A3
- *
- * Add device to allow list (Random C5B4B3B2B1B0)
- * hcitool cmd 8 11 1 b0 b1 b2 b4 b5 c5
- * hcitool lcmd 0x2011 7 0xB2B1B001 0xC5B4B3
- *
- * Remove device from allow list (Public C5A4A3A2A1A0)
- * hcitool cmd 8 12 0 a0 a1 a2 a3 a4 c5
- * hcitool lcmd 0x2012 7 0xA2A1A000 0xC5A4A3
- *
- * Remove device from allow list (Random C5B4B3B2B1B0)
- * hcitool cmd 8 12 1 b0 b1 b2 b4 b5 c5
- * hcitool lcmd 0x2012 7 0xB2B1B001 0xC5B4B3
- *
- * Tested by checking dumping the allow list and checking its size when:
- * - adding devices
- * - removing devices
- * - removing non-existent devices
- * - adding more than 8 devices
- *
- */
-
-/*
- * Test commands:
- *
- * Rx Test channel 37
- * hcitool cmd 8 1D 25
- *
- * Tx Test channel 37 20 bytes type 2
- * hcitool cmd 8 1e 25 14 2
- *
- * Test end
- * hcitool cmd 8 1f
- */
-
-static uint8_t hci_buf[200];
-
-#define MAX_BLE_HCI_PARAMS 8
-static uint32_t param[MAX_BLE_HCI_PARAMS];
-
-static int command_ble_hci_cmd(int argc, char **argv)
-{
-	static struct hciCmdHdr header;
-	int length, opcode, i;
-	char *e;
-
-	if (argc < 3 || argc > MAX_BLE_HCI_PARAMS + 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	opcode = strtoi(argv[1], &e, 0);
-	if (*e || opcode < 0 || opcode > 0xffff)
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length < 0 || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if ((length + 3) / 4 != argc - 3) {
-		CPRINTF("Remember to pass HCI params in 32-bit chunks.\n");
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3 + i;
-	}
-
-	header.opcode = opcode;
-	header.paramLen = length;
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
-
-	hci_cmd(hci_buf);
-
-	CPRINTS("hci cmd @%pP", hci_buf);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ble_hci_cmd, command_ble_hci_cmd,
-			"opcode len uint32 uint32 uint32... (little endian)",
-			"Send an hci command of length len");
-
-static int command_hcitool(int argc, char **argv)
-{
-	static struct hciCmdHdr header;
-	int i, ogf, ocf;
-	char *e;
-
-	if (argc < 4 || argc > MAX_BLE_HCI_PARAMS + 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (argv[1][0] == 'l') /* strcmp lcmd */
-		return command_ble_hci_cmd(argc-1, &argv[1]);
-
-	ogf = strtoi(argv[2], &e, 16);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	ocf = strtoi(argv[3], &e, 16);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	header.opcode = CMD_MAKE_OPCODE(ogf, ocf);
-	header.paramLen = argc-4;
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-
-	for (i = 4; i < argc; i++) {
-		hci_buf[i - 4 + 3] = strtoi(argv[i], &e, 16);
-		if (*e)
-			return EC_ERROR_PARAM4 + i;
-	}
-
-	hci_cmd(hci_buf);
-
-	CPRINTS("hci cmd @%pP", hci_buf);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hcitool, command_hcitool,
-			"cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)",
-			"Send an hci command of length len");
-
-static int command_ble_hci_acl(int argc, char **argv)
-{
-	static struct hciAclHdr header;
-	int length, hdr, i;
-	char *e;
-
-	if (argc < 3 || argc > MAX_BLE_HCI_PARAMS + 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	hdr = strtoi(argv[1], &e, 0);
-	if (*e || hdr < 0 || hdr > 0xffff)
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length < 0 || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if ((length + 3) / 4 != argc - 3) {
-		CPRINTF("Remember to pass HCI params in 32-bit chunks.\n");
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3 + i;
-	}
-
-	header.hdr = hdr;
-	header.len = length;
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
-
-	hci_cmd(hci_buf);
-
-	CPRINTS("hci acl @%pP", hci_buf);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ble_hci_acl, command_ble_hci_acl,
-			"hdr len uint32 uint32 uint32... (little endian)",
-			"Send hci acl data of length len");
-
-static int command_ble_hci_adv(int argc, char **argv)
-{
-	static struct hciCmdHdr header;
-	int adv, p = 0, scan_rsp = 0;
-	char *e;
-
-	if (argc < 2 || argc > 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	adv = strtoi(argv[1], &e, 0);
-	if (*e || adv < 0 || adv > sizeof(adverts))
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		p = strtoi(argv[2], &e, 0);
-		if (*e || p < 0 || p > sizeof(adv_params))
-			return EC_ERROR_PARAM2;
-	}
-
-	if (argc > 3) {
-		scan_rsp = strtoi(argv[3], &e, 0);
-		if (*e || scan_rsp < 0 || scan_rsp > sizeof(scans))
-			return EC_ERROR_PARAM3;
-	}
-
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Adv_Params);
-	header.paramLen = sizeof(struct hciLeSetAdvParams);
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adv_params[p], header.paramLen);
-
-	hci_cmd(hci_buf);
-
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertising_Data);
-	header.paramLen = adv_lengths[adv];
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adverts[adv], header.paramLen);
-
-	hci_cmd(hci_buf);
-
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Scan_Response_Data);
-	header.paramLen = scan_lengths[scan_rsp];
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			scans[scan_rsp], header.paramLen);
-
-	hci_cmd(hci_buf);
-
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertise_Enable);
-	header.paramLen = sizeof(struct hciLeSetAdvEnable);
-
-	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	hci_buf[sizeof(struct hciCmdHdr)] = 1;
-
-	hci_cmd(hci_buf);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ble_hci_adv, command_ble_hci_adv,
-			"adv [params=0] [scan_rsp=0]",
-			"Use pre-defined parameters to start advertising");
-
-#endif /* CONFIG_BLUETOOTH_HCI_DEBUG */
diff --git a/common/btle_ll.c b/common/btle_ll.c
deleted file mode 100644
index 20ede4d4a0..0000000000
--- a/common/btle_ll.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le_ll.h"
-#include "bluetooth_le.h"
-#include "btle_hci_int.h"
-#include "util.h"
-#include "console.h"
-#include "radio.h"
-#include "radio_test.h"
-#include "task.h"
-#include "timer.h"
-
-#ifdef CONFIG_BLUETOOTH_LL_DEBUG
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_LL, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ## args)
-
-#else /* CONFIG_BLUETOOTH_LL_DEBUG */
-
-#define CPUTS(outstr)
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-
-#endif /* CONFIG_BLUETOOTH_LL_DEBUG */
-
-/* Link Layer */
-
-enum ll_state_t ll_state = UNINITIALIZED;
-
-static struct hciLeSetAdvParams ll_adv_params;
-static struct hciLeSetScanParams ll_scan_params;
-static int ll_adv_interval_us;
-static int ll_adv_timeout_us;
-
-static struct ble_pdu ll_adv_pdu;
-static struct ble_pdu ll_scan_rsp_pdu;
-static struct ble_pdu tx_packet_1;
-static struct ble_pdu *packet_tb_sent;
-static struct ble_connection_params conn_params;
-static int connection_initialized;
-static struct remapping_table remap_table;
-
-static uint64_t receive_time, last_receive_time;
-static uint8_t num_consecutive_failures;
-
-static uint32_t tx_end, tx_rsp_end, time_of_connect_req;
-struct ble_pdu ll_rcv_packet;
-static uint32_t ll_conn_events;
-static uint32_t errors_recovered;
-
-int ll_power;
-uint8_t is_first_data_packet;
-
-static uint64_t ll_random_address = 0xC5BADBADBAD1; /* Uninitialized */
-static uint64_t ll_public_address = 0xC5BADBADBADF; /* Uninitialized */
-static uint8_t ll_channel_map[5] = {0xff, 0xff, 0xff, 0xff, 0x1f};
-
-static uint8_t ll_filter_duplicates;
-
-int ll_pseudo_rand(int max_plus_one)
-{
-	static uint32_t lfsr = 0x55555;
-	int lsb = lfsr & 1;
-
-	lfsr = lfsr >> 1;
-	if (lsb)
-		lfsr ^= 0x80020003; /* Bits 32, 22, 2, 1 */
-	return lfsr % max_plus_one;
-}
-
-uint8_t ll_set_tx_power(uint8_t *params)
-{
-	/* Add checking */
-	ll_power = params[0];
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_read_tx_power(void)
-{
-	return ll_power;
-}
-
-/* LE Information */
-uint8_t ll_read_buffer_size(uint8_t *return_params)
-{
-	return_params[0] = LL_MAX_DATA_PACKET_LENGTH & 0xff;
-	return_params[1] = (LL_MAX_DATA_PACKET_LENGTH >> 8) & 0xff;
-	return_params[2] = LL_MAX_DATA_PACKETS;
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_read_local_supported_features(uint8_t *return_params)
-{
-	uint64_t supported_features = LL_SUPPORTED_FEATURES;
-
-	memcpy(return_params, &supported_features, sizeof(supported_features));
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_read_supported_states(uint8_t *return_params)
-{
-	uint64_t supported_states = LL_SUPPORTED_STATES;
-
-	memcpy(return_params, &supported_states, sizeof(supported_states));
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_set_host_channel_classification(uint8_t *params)
-{
-	memcpy(ll_channel_map, params, sizeof(ll_channel_map));
-	return HCI_SUCCESS;
-}
-
-/* Advertising */
-uint8_t ll_set_scan_response_data(uint8_t *params)
-{
-	if (params[0] > BLE_MAX_ADV_PAYLOAD_OCTETS)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	if (ll_state == ADVERTISING)
-		return HCI_ERR_Controller_Busy;
-
-	memcpy(&ll_scan_rsp_pdu.payload[BLUETOOTH_ADDR_OCTETS], &params[1],
-	       params[0]);
-	ll_scan_rsp_pdu.header.adv.length = params[0] + BLUETOOTH_ADDR_OCTETS;
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_set_adv_data(uint8_t *params)
-{
-	if (params[0] > BLE_MAX_ADV_PAYLOAD_OCTETS)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	if (ll_state == ADVERTISING)
-		return HCI_ERR_Controller_Busy;
-
-	/* Skip the address */
-	memcpy(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS], &params[1],
-	       params[0]);
-	ll_adv_pdu.header.adv.length = params[0] + BLUETOOTH_ADDR_OCTETS;
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_reset(void)
-{
-	ll_state = UNINITIALIZED;
-	radio_disable();
-
-	ble_radio_clear_allow_list();
-
-	return HCI_SUCCESS;
-}
-
-static uint8_t ll_state_change_request(enum ll_state_t next_state)
-{
-	/* Initialize the radio if it hasn't been initialized */
-	if (ll_state == UNINITIALIZED) {
-		if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT)
-				!= EC_SUCCESS)
-			return HCI_ERR_Hardware_Failure;
-		ll_state = STANDBY;
-	}
-
-	/* Only change states when the link layer is in STANDBY */
-	if (next_state != STANDBY && ll_state != STANDBY)
-		return HCI_ERR_Controller_Busy;
-
-	ll_state = next_state;
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_set_advertising_enable(uint8_t *params)
-{
-	uint8_t rv;
-
-	if (params[0]) {
-		rv = ll_state_change_request(ADVERTISING);
-		if (rv == HCI_SUCCESS)
-			task_wake(TASK_ID_BLE_LL);
-	} else {
-		rv = ll_state_change_request(STANDBY);
-	}
-
-	return rv;
-}
-
-uint8_t ll_set_scan_enable(uint8_t *params)
-{
-	uint8_t rv;
-
-	if (params[0]) {
-		ll_filter_duplicates = params[1];
-		rv = ll_state_change_request(SCANNING);
-		if (rv == HCI_SUCCESS)
-			task_wake(TASK_ID_BLE_LL);
-	} else {
-		rv = ll_state_change_request(STANDBY);
-	}
-
-	return HCI_SUCCESS;
-}
-
-void set_empty_data_packet(struct ble_pdu *pdu)
-{
-	/* LLID == 1 means incomplete or empty data packet */
-	pdu->header.data.llid = 1;
-	pdu->header.data.nesn = 1;
-	pdu->header.data.sn = 0;
-	pdu->header.data.md = 0;
-	pdu->header.data.length = 0;
-	pdu->header_type_adv = 0;
-}
-
-/* Connection state */
-
-/**
- * This function serves to take data from a CONNECT_REQ packet and copy it
- * into a struct, conn_params, which defines the parameter of the connection.
- * It also fills a remapping table, another essential element of the link
- * layer connection.
- */
-uint8_t initialize_connection(void)
-{
-	int cur_offset = 0, i = 0;
-	uint8_t final_octet = 0;
-	uint8_t remap_arr[5];
-	uint8_t *payload_start = (uint8_t *)(ll_rcv_packet.payload);
-
-	num_consecutive_failures = 0;
-
-	/* Copy data into the appropriate portions of memory */
-	memcpy((uint8_t *)&(conn_params.init_a),
-			payload_start, CONNECT_REQ_INITA_LEN);
-	cur_offset += CONNECT_REQ_INITA_LEN;
-
-	memcpy((uint8_t *)&(conn_params.adv_a),
-			payload_start+cur_offset, CONNECT_REQ_ADVA_LEN);
-	cur_offset += CONNECT_REQ_ADVA_LEN;
-
-	memcpy(&(conn_params.access_addr),
-			payload_start+cur_offset, CONNECT_REQ_ACCESS_ADDR_LEN);
-	cur_offset += CONNECT_REQ_ACCESS_ADDR_LEN;
-
-	conn_params.crc_init_val = 0;
-	memcpy(&(conn_params.crc_init_val),
-			payload_start+cur_offset, CONNECT_REQ_CRC_INIT_VAL_LEN);
-	cur_offset += CONNECT_REQ_CRC_INIT_VAL_LEN;
-
-	memcpy(&(conn_params.win_size),
-			payload_start+cur_offset, CONNECT_REQ_WIN_SIZE_LEN);
-	cur_offset += CONNECT_REQ_WIN_SIZE_LEN;
-
-	memcpy(&(conn_params.win_offset),
-			payload_start+cur_offset, CONNECT_REQ_WIN_OFFSET_LEN);
-	cur_offset += CONNECT_REQ_WIN_OFFSET_LEN;
-
-	memcpy(&(conn_params.interval),
-			payload_start+cur_offset, CONNECT_REQ_INTERVAL_LEN);
-	cur_offset += CONNECT_REQ_INTERVAL_LEN;
-
-	memcpy(&(conn_params.latency),
-			payload_start+cur_offset, CONNECT_REQ_LATENCY_LEN);
-	cur_offset += CONNECT_REQ_LATENCY_LEN;
-
-	memcpy(&(conn_params.timeout),
-			payload_start+cur_offset, CONNECT_REQ_TIMEOUT_LEN);
-	cur_offset += CONNECT_REQ_TIMEOUT_LEN;
-
-	conn_params.channel_map = 0;
-	memcpy(&(conn_params.channel_map),
-			payload_start+cur_offset, CONNECT_REQ_CHANNEL_MAP_LEN);
-	cur_offset += CONNECT_REQ_CHANNEL_MAP_LEN;
-
-	memcpy(&final_octet, payload_start+cur_offset,
-			CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN);
-
-	/* last  5 bits of final_octet: */
-	conn_params.hop_increment = final_octet & 0x1f;
-	/* first 3 bits of final_octet: */
-	conn_params.sleep_clock_accuracy = (final_octet & 0xe0) >> 5;
-
-	/* Set up channel mapping table */
-	for (i = 0; i < 5; ++i)
-		remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map))+i);
-	fill_remapping_table(&remap_table, remap_arr,
-		conn_params.hop_increment);
-
-	/* Calculate transmission window parameters */
-	conn_params.transmitWindowSize = conn_params.win_size * 1250;
-	conn_params.transmitWindowOffset = conn_params.win_offset * 1250;
-	conn_params.connInterval = conn_params.interval * 1250;
-	/* The following two lines convert ms -> microseconds */
-	conn_params.connLatency = 1000 * conn_params.latency;
-	conn_params.connSupervisionTimeout = 10000 * conn_params.timeout;
-	/* All these times are in microseconds! */
-
-	/* Check for common transmission errors */
-	if (conn_params.hop_increment < 5 || conn_params.hop_increment > 16) {
-		for (i = 0; i < 5; ++i)
-			CPRINTF("ERROR!! ILLEGAL HOP_INCREMENT!!\n");
-		return HCI_ERR_Invalid_LMP_Parameters;
-	}
-
-	is_first_data_packet = 1;
-	return HCI_SUCCESS;
-}
-
-/* Allow List */
-uint8_t ll_clear_allow_list(void)
-{
-	if (ble_radio_clear_allow_list() == EC_SUCCESS)
-		return HCI_SUCCESS;
-	else
-		return HCI_ERR_Hardware_Failure;
-}
-
-uint8_t ll_read_allow_list_size(uint8_t *return_params)
-{
-	if (ble_radio_read_allow_list_size(return_params) == EC_SUCCESS)
-		return HCI_SUCCESS;
-	else
-		return HCI_ERR_Hardware_Failure;
-}
-
-uint8_t ll_add_device_to_allow_list(uint8_t *params)
-{
-	if (ble_radio_add_device_to_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
-		return HCI_SUCCESS;
-	else
-		return HCI_ERR_Host_Rejected_Due_To_Limited_Resources;
-}
-
-uint8_t ll_remove_device_from_allow_list(uint8_t *params)
-{
-	if (ble_radio_remove_device_from_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
-		return HCI_SUCCESS;
-	else
-		return HCI_ERR_Hardware_Failure;
-}
-
-/* Connections */
-uint8_t ll_read_remote_used_features(uint8_t *params)
-{
-	uint16_t handle = params[0] | (((uint16_t)params[1]) << 8);
-
-	CPRINTS("Read remote used features for handle %d", handle);
-	/* Check handle */
-	return HCI_SUCCESS;
-}
-
-/* RF PHY Testing */
-static int ll_test_packets;
-
-uint8_t ll_receiver_test(uint8_t *params)
-{
-	int rv;
-
-	ll_test_packets = 0;
-
-	/* See if the link layer is busy */
-	rv = ll_state_change_request(TEST_RX);
-	if (rv)
-		return rv;
-
-	rv = ble_test_rx_init(params[0]);
-	if (rv)
-		return rv;
-
-	CPRINTS("Start Rx test");
-	task_wake(TASK_ID_BLE_LL);
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_transmitter_test(uint8_t *params)
-{
-	int rv;
-
-	ll_test_packets = 0;
-
-	/* See if the link layer is busy */
-	rv = ll_state_change_request(TEST_TX);
-	if (rv)
-		return rv;
-
-	rv = ble_test_tx_init(params[0], params[1], params[2]);
-	if (rv)
-		return rv;
-
-	CPRINTS("Start Tx test");
-	task_wake(TASK_ID_BLE_LL);
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_test_end(uint8_t *return_params)
-{
-	CPRINTS("End (%d packets)", ll_test_packets);
-
-	ble_test_stop();
-
-	if (ll_state == TEST_RX) {
-		return_params[0] = ll_test_packets & 0xff;
-		return_params[1] = (ll_test_packets >> 8);
-		ll_test_packets = 0;
-	} else {
-		return_params[0] = 0;
-		return_params[1] = 0;
-		ll_test_packets = 0;
-	}
-	return ll_reset();
-}
-
-uint8_t ll_set_random_address(uint8_t *params)
-{
-	/* No checking.  The host should know the rules. */
-	memcpy(&ll_random_address, params,
-	       sizeof(struct hciLeSetRandomAddress));
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_set_scan_params(uint8_t *params)
-{
-	if (ll_state == SCANNING)
-		return HCI_ERR_Controller_Busy;
-
-	memcpy(&ll_scan_params, params, sizeof(struct hciLeSetScanParams));
-
-	return HCI_SUCCESS;
-}
-
-uint8_t ll_set_advertising_params(uint8_t *params)
-{
-	if (ll_state == ADVERTISING)
-		return HCI_ERR_Controller_Busy;
-
-	memcpy(&ll_adv_params, params, sizeof(struct hciLeSetAdvParams));
-
-	switch (ll_adv_params.advType) {
-	case BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND:
-	case BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND:
-		if (ll_adv_params.advIntervalMin <
-		    (100000 / LL_ADV_INTERVAL_UNIT_US))    /* 100ms */
-			return HCI_ERR_Invalid_HCI_Command_Parameters;
-	/* Fall through */
-	case BLE_ADV_HEADER_PDU_TYPE_ADV_IND:
-		if (ll_adv_params.advIntervalMin > ll_adv_params.advIntervalMax)
-			return HCI_ERR_Invalid_HCI_Command_Parameters;
-		if (ll_adv_params.advIntervalMin <
-		    (20000 / LL_ADV_INTERVAL_UNIT_US) ||   /* 20ms */
-		    ll_adv_params.advIntervalMax >
-		    (10240000 / LL_ADV_INTERVAL_UNIT_US))  /* 10.24s */
-			return HCI_ERR_Invalid_HCI_Command_Parameters;
-		ll_adv_interval_us = (((ll_adv_params.advIntervalMin +
-					ll_adv_params.advIntervalMax) / 2) *
-					LL_ADV_INTERVAL_UNIT_US);
-		/* Don't time out */
-		ll_adv_timeout_us = -1;
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND:
-		ll_adv_interval_us = LL_ADV_DIRECT_INTERVAL_US;
-		ll_adv_timeout_us = LL_ADV_DIRECT_TIMEOUT_US;
-	break;
-	default:
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-	}
-
-	/* Initialize the ADV PDU */
-	ll_adv_pdu.header_type_adv = 1;
-	ll_adv_pdu.header.adv.type = ll_adv_params.advType;
-	ll_adv_pdu.header.adv.txaddr = ll_adv_params.useRandomAddress;
-
-	if (ll_adv_params.useRandomAddress)
-		memcpy(ll_adv_pdu.payload, &ll_random_address,
-		       BLUETOOTH_ADDR_OCTETS);
-	else
-		memcpy(ll_adv_pdu.payload, &ll_public_address,
-		       BLUETOOTH_ADDR_OCTETS);
-
-	if (ll_adv_params.advType == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND) {
-		ll_adv_pdu.header.adv.rxaddr =
-			ll_adv_params.directRandomAddress;
-		memcpy(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
-		       ll_adv_params.directAddr,
-		       sizeof(ll_adv_params.directAddr));
-		ll_adv_pdu.header.adv.length = 12;
-	} else {
-		ll_adv_pdu.header.adv.rxaddr = 0;
-	}
-
-	/* All other types get data from SetAdvertisingData */
-
-	/* Initialize the Scan Rsp PDU */
-	ll_scan_rsp_pdu.header_type_adv = 1;
-	ll_scan_rsp_pdu.header.adv.type = BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP;
-	ll_scan_rsp_pdu.header.adv.txaddr = ll_adv_params.useRandomAddress;
-
-	if (ll_adv_params.useRandomAddress)
-		memcpy(ll_scan_rsp_pdu.payload, &ll_random_address,
-		       BLUETOOTH_ADDR_OCTETS);
-	else
-		memcpy(ll_scan_rsp_pdu.payload, &ll_public_address,
-		       BLUETOOTH_ADDR_OCTETS);
-
-	ll_scan_rsp_pdu.header.adv.rxaddr = 0;
-
-	return HCI_SUCCESS;
-}
-
-static uint32_t tx_end, rsp_end, tx_rsp_end;
-struct ble_pdu ll_rcv_packet;
-
-/**
- * Advertises packet that has already been generated on given channel.
- *
- * This function also processes any incoming scan requests.
- *
- * @param    chan The channel on which to advertise.
- * @returns  EC_SUCCESS on packet reception, otherwise error.
- */
-int ble_ll_adv(int chan)
-{
-	int rv;
-
-	ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	ble_tx(&ll_adv_pdu);
-
-	while (!RADIO_DONE)
-		;
-
-	tx_end = get_time().le.lo;
-
-	if (ll_adv_pdu.header.adv.type ==
-	    BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND)
-		return EC_SUCCESS;
-
-	rv = ble_rx(&ll_rcv_packet, 16000, 1);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	while (!RADIO_DONE)
-		;
-
-	tx_rsp_end = get_time().le.lo;
-
-	/* Check for valid responses */
-	switch (ll_rcv_packet.header.adv.type) {
-	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
-		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
-		if ((ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		     ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) ||
-			/* The advertising address needs to match */
-		    (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-			    &ll_adv_pdu.payload[0], BLUETOOTH_ADDR_OCTETS))) {
-			/* Don't send the scan response */
-			radio_disable();
-			return rv;
-		}
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
-		/* Don't send a scan response */
-		radio_disable();
-		/* Connecting is only allowed for ADV_IND and ADV_DIRECT_IND */
-		if (ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-			   &ll_adv_pdu.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-		/* The InitAddr address needs to match for ADV_DIRECT_IND */
-		if (ll_adv_pdu.header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-			memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
-			&ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-
-		/* Mark time that connect was received */
-		time_of_connect_req = NRF51_TIMER_CC(0, 1);
-
-		/*
-		 * Enter connection state upon receiving
-		 * a connect request packet
-		 */
-		ll_state = CONNECTION;
-
-		return rv;
-	break;
-	default: /* Unhandled response packet */
-		radio_disable();
-		return rv;
-	break;
-	}
-
-	CPRINTF("ADV %u Response %u %u\n", tx_end, rsp_end, tx_rsp_end);
-
-	return rv;
-}
-
-int ble_ll_adv_event(void)
-{
-	int chan_idx;
-	int rv = EC_SUCCESS;
-
-	for (chan_idx = 0; chan_idx < 3; chan_idx++) {
-		if (ll_adv_params.advChannelMap & BIT(chan_idx)) {
-			rv = ble_ll_adv(chan_idx + 37);
-			if (rv != EC_SUCCESS)
-				return rv;
-		}
-	}
-
-	return rv;
-}
-
-
-void print_connection_state(void)
-{
-	CPRINTF("vvvvvvvvvvvvvvvvvvvCONNECTION STATEvvvvvvvvvvvvvvvvvvv\n");
-	CPRINTF("Number of connections events processed: %d\n", ll_conn_events);
-	CPRINTF("Recovered from %d bad receives.\n", errors_recovered);
-	CPRINTF("Access addr(hex): %x\n", conn_params.access_addr);
-	CPRINTF("win_size(hex): %x\n", conn_params.win_size);
-	CPRINTF("win_offset(hex): %x\n", conn_params.win_offset);
-	CPRINTF("interval(hex): %x\n", conn_params.interval);
-	CPRINTF("latency(hex): %x\n", conn_params.latency);
-	CPRINTF("timeout(hex): %x\n", conn_params.timeout);
-	CPRINTF("channel_map(hex): %llx\n", conn_params.channel_map);
-	CPRINTF("hop(hex): %x\n", conn_params.hop_increment);
-	CPRINTF("SCA(hex): %x\n", conn_params.sleep_clock_accuracy);
-	CPRINTF("transmitWindowOffset: %d\n", conn_params.transmitWindowOffset);
-	CPRINTF("connInterval: %d\n", conn_params.connInterval);
-	CPRINTF("transmitWindowSize: %d\n", conn_params.transmitWindowSize);
-	CPRINTF("^^^^^^^^^^^^^^^^^^^CONNECTION STATE^^^^^^^^^^^^^^^^^^^\n");
-}
-
-int connected_communicate(void)
-{
-	int rv;
-	long sleep_time;
-	int offset = 0;
-	uint64_t listen_time;
-	uint8_t comm_channel = get_next_data_channel(&remap_table);
-
-	if (num_consecutive_failures > 0) {
-		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
-		NRF51_RADIO_FREQUENCY =
-			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
-		NRF51_RADIO_DATAWHITEIV = comm_channel;
-		listen_time = last_receive_time + conn_params.connInterval
-			- get_time().val + conn_params.transmitWindowSize;
-
-		/*
-		 * This listens for 1.25 times the expected amount
-		 * of time. This is a margin of error. This line is
-		 * only called when a connection has failed (a missed
-		 * packet). The peripheral and the controller could have
-		 * missed this packet due to a disagreement on when
-		 * the packet should have arrived. We listen for
-		 * slightly longer than expected in the case that
-		 * there was a timing disagreement.
-		 */
-		rv = ble_rx(&ll_rcv_packet,
-			listen_time + (listen_time >> 2), 0);
-	} else {
-		if (!is_first_data_packet) {
-			sleep_time = receive_time +
-				conn_params.connInterval - get_time().val;
-			/*
-			 * The time slept is 31/32 (96.875%) of the calculated
-			 * required sleep time because the code to receive
-			 * packets requires time to set up.
-			 */
-			usleep(sleep_time - (sleep_time >> 5));
-		} else {
-			last_receive_time = time_of_connect_req;
-			sleep_time = TRANSMIT_WINDOW_OFFSET_CONSTANT +
-					conn_params.transmitWindowOffset +
-					time_of_connect_req - get_time().val;
-			if (sleep_time >= 0) {
-				/*
-				 * Radio is on for longer than needed for first
-				 * packet to make sure that it is received.
-				 */
-				usleep(sleep_time - (sleep_time >> 2));
-			} else {
-				return EC_ERROR_TIMEOUT;
-			}
-		}
-
-		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
-		NRF51_RADIO_FREQUENCY =
-			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
-		NRF51_RADIO_DATAWHITEIV = comm_channel;
-
-		/*
-		 * Timing the transmit window is very hard to do when the code
-		 * executing has actual effect on the timing. To combat this,
-		 * the radio starts a little early, and terminates when the
-		 * window normally should. The variable 'offset' represents
-		 * how early the window opens in microseconds.
-		 */
-		if (!is_first_data_packet)
-			offset = last_receive_time + conn_params.connInterval
-				- get_time().val;
-		else
-			offset = 0;
-
-		rv = ble_rx(&ll_rcv_packet,
-			    offset + conn_params.transmitWindowSize,
-			    0);
-	}
-
-	/*
-	 * The radio shortcuts have been set up so that transmission
-	 * occurs automatically after receiving. The radio just needs
-	 * to know where to find the packet to be sent.
-	 */
-	NRF51_RADIO_PACKETPTR = (uint32_t)packet_tb_sent;
-
-	receive_time = NRF51_TIMER_CC(0, 1);
-	if (rv != EC_SUCCESS)
-		receive_time = last_receive_time + conn_params.connInterval;
-
-	while (!RADIO_DONE)
-		;
-
-	last_receive_time = receive_time;
-	is_first_data_packet = 0;
-
-	return rv;
-}
-
-static uint32_t ll_adv_events;
-static timestamp_t deadline;
-static uint32_t start, end;
-
-void bluetooth_ll_task(void)
-{
-	uint64_t last_rx_time = 0;
-	CPRINTS("LL task init");
-
-	while (1) {
-		switch (ll_state) {
-		case ADVERTISING:
-
-			if (deadline.val == 0) {
-				CPRINTS("ADV @%pP", &ll_adv_pdu);
-				deadline.val = get_time().val +
-					(uint32_t)ll_adv_timeout_us;
-				ll_adv_events = 0;
-			}
-
-			ble_ll_adv_event();
-			ll_adv_events++;
-
-			if (ll_state == CONNECTION) {
-				receive_time = 0;
-				break;
-			}
-			/* sleep for 0-10ms */
-			usleep(ll_adv_interval_us + ll_pseudo_rand(10000));
-
-			if (get_time().val > deadline.val) {
-				ll_state = STANDBY;
-				break;
-			}
-		break;
-		case STANDBY:
-			deadline.val = 0;
-			CPRINTS("Standby %d events", ll_adv_events);
-			ll_adv_events = 0;
-			ll_conn_events = 0;
-			task_wait_event(-1);
-			connection_initialized = 0;
-			errors_recovered = 0;
-		break;
-		case TEST_RX:
-			if (ble_test_rx() == HCI_SUCCESS)
-				ll_test_packets++;
-			/* Packets come every 625us, sleep to save power */
-			usleep(300);
-		break;
-		case TEST_TX:
-			start = get_time().le.lo;
-			ble_test_tx();
-			ll_test_packets++;
-			end = get_time().le.lo;
-			usleep(625 - 82 - (end-start)); /* 625us */
-		break;
-		case UNINITIALIZED:
-			ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-			ll_adv_events = 0;
-			task_wait_event(-1);
-			connection_initialized = 0;
-			packet_tb_sent = &tx_packet_1;
-			set_empty_data_packet(&tx_packet_1);
-		break;
-		case CONNECTION:
-			if (!connection_initialized) {
-				if (initialize_connection() != HCI_SUCCESS) {
-					ll_state = STANDBY;
-					break;
-				}
-				connection_initialized = 1;
-				last_rx_time = NRF51_TIMER_CC(0, 1);
-			}
-
-			if (connected_communicate() == EC_SUCCESS) {
-				if (num_consecutive_failures > 0)
-					++errors_recovered;
-				num_consecutive_failures = 0;
-				last_rx_time = get_time().val;
-			} else {
-				num_consecutive_failures++;
-				if ((get_time().val - last_rx_time) >
-					conn_params.connSupervisionTimeout) {
-
-					ll_state = STANDBY;
-					CPRINTF("EXITING CONNECTION STATE "
-						"DUE TO TIMEOUT.\n");
-				}
-			}
-			++ll_conn_events;
-
-			if (ll_state == STANDBY) {
-				CPRINTF("Exiting connection state/Entering "
-					"Standby state after %d connections "
-					"events\n", ll_conn_events);
-				print_connection_state();
-			}
-		break;
-		default:
-			CPRINTS("Unhandled State ll_state = %d", ll_state);
-			ll_state = UNINITIALIZED;
-			task_wait_event(-1);
-		}
-	}
-}
-
diff --git a/common/build.mk b/common/build.mk
index a1a956f9ab..cfc023be5a 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -306,9 +306,3 @@ $(out)/rma_key_from_blob.h: board/$(BOARD)/$(BLOB_FILE) util/bin2h.sh
 	$(Q)util/bin2h.sh RMA_KEY_BLOB $< $@
 
 endif
-
-include $(_common_dir)fpsensor/build.mk
-include $(_common_dir)usbc/build.mk
-
-include $(_common_dir)mock/build.mk
-common-y+=$(foreach m,$(mock-y),mock/$(m))
diff --git a/common/button.c b/common/button.c
deleted file mode 100644
index 03bdb1234f..0000000000
--- a/common/button.c
+++ /dev/null
@@ -1,892 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Button module for Chrome EC */
-
-#include "atomic.h"
-#include "button.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "hooks.h"
-#include "keyboard_protocol.h"
-#include "led_common.h"
-#include "mkbp_input_devices.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
-
-struct button_state_t {
-	uint64_t debounce_time;
-	int debounced_pressed;
-};
-
-static struct button_state_t __bss_slow state[BUTTON_COUNT];
-
-static uint64_t __bss_slow next_deferred_time;
-
-#if defined(CONFIG_CMD_BUTTON) || defined(CONFIG_HOSTCMD_BUTTON)
-#define CONFIG_SIMULATED_BUTTON
-#endif
-
-#ifdef CONFIG_SIMULATED_BUTTON
-/* Bitmask to keep track of simulated state of each button.
- * Bit numbers are aligned to enum button.
- */
-static int sim_button_state;
-
-/*
- * Flip state of associated button type in sim_button_state bitmask.
- * In bitmask, if bit is 1, button is pressed.  If bit is 0, button is
- * released.
- *
- * Returns the appropriate GPIO value based on table below:
- * +----------+--------+--------+
- * |  state   | active | return |
- * +----------+--------+--------+
- * | pressed  |  high  |   1    |
- * | pressed  |  low   |   0    |
- * | released |  high  |   0    |
- * | released |  low   |   1    |
- * +----------+--------+--------+
- */
-static int simulated_button_pressed(const struct button_config *button)
-{
-	return !!(sim_button_state & BIT(button->type));
-}
-#endif
-
-/*
- * Whether a button is currently pressed.
- */
-static int raw_button_pressed(const struct button_config *button)
-{
-	int physical_value = 0;
-	int simulated_value = 0;
-	if (!(button->flags & BUTTON_FLAG_DISABLED)) {
-		if (IS_ENABLED(CONFIG_ADC_BUTTONS) &&
-			button_is_adc_detected(button->gpio)) {
-			physical_value =
-				adc_to_physical_value(button->gpio);
-		} else {
-			physical_value = (!!gpio_get_level(button->gpio) ==
-				!!(button->flags & BUTTON_FLAG_ACTIVE_HIGH));
-		}
-#ifdef CONFIG_SIMULATED_BUTTON
-		simulated_value = simulated_button_pressed(button);
-#endif
-	}
-
-	return (simulated_value || physical_value);
-}
-
-#ifdef CONFIG_BUTTON_TRIGGERED_RECOVERY
-
-#ifdef CONFIG_LED_COMMON
-static void button_blink_hw_reinit_led(void)
-{
-	int led_state = LED_STATE_ON;
-	timestamp_t deadline;
-	timestamp_t now = get_time();
-
-	/* Blink LED for 3 seconds. */
-	deadline.val = now.val + (3 * SECOND);
-
-	while (!timestamp_expired(deadline, &now)) {
-		led_control(EC_LED_ID_RECOVERY_HW_REINIT_LED, led_state);
-		led_state = !led_state;
-		watchdog_reload();
-		msleep(100);
-		now = get_time();
-	}
-
-	/* Reset LED to default state. */
-	led_control(EC_LED_ID_RECOVERY_HW_REINIT_LED, LED_STATE_RESET);
-}
-#endif
-
-/*
- * Whether recovery button (or combination of equivalent buttons) is pressed
- * If a dedicated recovery button is used, any of the buttons can be pressed,
- * otherwise, all the buttons must be pressed.
- */
-static int is_recovery_button_pressed(void)
-{
-	int i, pressed;
-	for (i = 0; i < recovery_buttons_count; i++) {
-		pressed = raw_button_pressed(recovery_buttons[i]);
-		if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON)) {
-			if (pressed)
-				return 1;
-		} else {
-			if (!pressed)
-				return 0;
-		}
-	}
-	return IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON) ? 0 : 1;
-}
-
-/*
- * If the EC is reset and recovery is requested, then check if HW_REINIT is
- * requested as well. Since the EC reset occurs after volup+voldn+power buttons
- * are held down for 10 seconds, check the state of these buttons for 20 more
- * seconds. If they are still held down all this time, then set host event to
- * indicate HW_REINIT is requested. Also, make sure watchdog is reloaded in
- * order to prevent watchdog from resetting the EC.
- */
-static void button_check_hw_reinit_required(void)
-{
-	timestamp_t deadline;
-	timestamp_t now = get_time();
-#ifdef CONFIG_LED_COMMON
-	uint8_t led_on = 0;
-#endif
-
-	deadline.val = now.val + (20 * SECOND);
-
-	CPRINTS("Checking for HW_REINIT request");
-
-	while (!timestamp_expired(deadline, &now)) {
-		if (!is_recovery_button_pressed() ||
-		    !power_button_signal_asserted()) {
-			CPRINTS("No HW_REINIT request");
-#ifdef CONFIG_LED_COMMON
-			if (led_on)
-				led_control(EC_LED_ID_RECOVERY_HW_REINIT_LED,
-					    LED_STATE_RESET);
-#endif
-			return;
-		}
-
-#ifdef CONFIG_LED_COMMON
-		if (!led_on) {
-			led_control(EC_LED_ID_RECOVERY_HW_REINIT_LED,
-				    LED_STATE_ON);
-			led_on = 1;
-		}
-#endif
-
-		now = get_time();
-		watchdog_reload();
-	}
-
-	CPRINTS("HW_REINIT requested");
-	host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT);
-
-#ifdef CONFIG_LED_COMMON
-	button_blink_hw_reinit_led();
-#endif
-}
-
-static int is_recovery_boot(void)
-{
-	if (system_jumped_to_this_image())
-		return 0;
-	if (!(system_get_reset_flags() &
-	    (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON)))
-		return 0;
-	if (!is_recovery_button_pressed())
-		return 0;
-	return 1;
-}
-#endif /* CONFIG_BUTTON_TRIGGERED_RECOVERY */
-
-static void button_reset(enum button button_type,
-	const struct button_config *button)
-{
-	state[button_type].debounced_pressed = raw_button_pressed(button);
-	state[button_type].debounce_time = 0;
-	gpio_enable_interrupt(button->gpio);
-}
-
-/*
- * Button initialization.
- */
-void button_init(void)
-{
-	int i;
-
-	CPRINTS("init buttons");
-	next_deferred_time = 0;
-	for (i = 0; i < BUTTON_COUNT; i++)
-		button_reset(i, &buttons[i]);
-
-#ifdef CONFIG_BUTTON_TRIGGERED_RECOVERY
-	if (is_recovery_boot()) {
-		system_clear_reset_flags(EC_RESET_FLAG_AP_OFF);
-		host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
-		button_check_hw_reinit_required();
-	}
-#endif /* defined(CONFIG_BUTTON_TRIGGERED_RECOVERY) */
-}
-
-#ifdef CONFIG_BUTTONS_RUNTIME_CONFIG
-int button_reassign_gpio(enum button button_type, enum gpio_signal gpio)
-{
-	if (button_type >= BUTTON_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable currently assigned interrupt */
-	gpio_disable_interrupt(buttons[button_type].gpio);
-
-	/* Reconfigure GPIO and enable the new interrupt */
-	buttons[button_type].gpio = gpio;
-	button_reset(button_type, &buttons[button_type]);
-
-	return EC_SUCCESS;
-}
-
-int button_disable_gpio(enum button button_type)
-{
-	if (button_type >= BUTTON_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* Disable GPIO interrupt */
-	gpio_disable_interrupt(buttons[button_type].gpio);
-	/* Mark button as disabled */
-	buttons[button_type].flags |= BUTTON_FLAG_DISABLED;
-
-	return EC_SUCCESS;
-}
-#endif
-
-
-/*
- * Handle debounced button changing state.
- */
-
-static void button_change_deferred(void);
-DECLARE_DEFERRED(button_change_deferred);
-
-#ifdef CONFIG_EMULATED_SYSRQ
-static void debug_mode_handle(void);
-DECLARE_DEFERRED(debug_mode_handle);
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, debug_mode_handle, HOOK_PRIO_LAST);
-#endif
-
-static void button_change_deferred(void)
-{
-	int i;
-	int new_pressed;
-	uint64_t soonest_debounce_time = 0;
-	uint64_t time_now = get_time().val;
-
-	for (i = 0; i < BUTTON_COUNT; i++) {
-		/* Skip this button if we are not waiting to debounce */
-		if (state[i].debounce_time == 0)
-			continue;
-
-		if (state[i].debounce_time <= time_now) {
-			/* Check if the state has changed */
-			new_pressed = raw_button_pressed(&buttons[i]);
-			if (state[i].debounced_pressed != new_pressed) {
-				state[i].debounced_pressed = new_pressed;
-#ifdef CONFIG_EMULATED_SYSRQ
-				/*
-				 * Calling deferred function for handling debug
-				 * mode so that button change processing is not
-				 * delayed.
-				 */
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
-				/*
-				 * Only the direct signal is used for sysrq.
-				 * H1_EC_RECOVERY_BTN_ODL doesn't reflect the
-				 * true state of the recovery button.
-				 */
-				if (i == BUTTON_RECOVERY)
-#endif
-					hook_call_deferred(
-						&debug_mode_handle_data, 0);
-#endif
-				CPRINTS("Button '%s' was %s",
-					buttons[i].name, new_pressed ?
-					"pressed" : "released");
-				if (IS_ENABLED(CONFIG_MKBP_INPUT_DEVICES)) {
-					mkbp_button_update(buttons[i].type,
-								new_pressed);
-				} else if (IS_ENABLED(HAS_TASK_KEYPROTO)) {
-					keyboard_update_button(buttons[i].type,
-								new_pressed);
-				}
-			}
-
-			/* Clear the debounce time to stop checking it */
-			state[i].debounce_time = 0;
-		} else {
-			/*
-			 * Make sure the next deferred call happens on or before
-			 * each button needs it.
-			 */
-			soonest_debounce_time = (soonest_debounce_time == 0) ?
-				state[i].debounce_time :
-				MIN(soonest_debounce_time,
-				    state[i].debounce_time);
-		}
-	}
-
-	if (soonest_debounce_time != 0) {
-		next_deferred_time = soonest_debounce_time;
-		hook_call_deferred(&button_change_deferred_data,
-				   next_deferred_time - time_now);
-	}
-}
-
-/*
- * Handle a button interrupt.
- */
-void button_interrupt(enum gpio_signal signal)
-{
-	int i;
-	uint64_t time_now = get_time().val;
-
-	for (i = 0; i < BUTTON_COUNT; i++) {
-		if (buttons[i].gpio != signal ||
-		    (buttons[i].flags & BUTTON_FLAG_DISABLED))
-			continue;
-
-		state[i].debounce_time = time_now + buttons[i].debounce_us;
-		if (next_deferred_time <= time_now ||
-		    next_deferred_time > state[i].debounce_time) {
-			next_deferred_time = state[i].debounce_time;
-			hook_call_deferred(&button_change_deferred_data,
-					   next_deferred_time - time_now);
-		}
-		break;
-	}
-}
-
-#ifdef CONFIG_SIMULATED_BUTTON
-static int button_present(enum keyboard_button_type type)
-{
-	int i;
-
-	for (i = 0; i < BUTTON_COUNT; i++)
-		if (buttons[i].type == type)
-			break;
-
-	return i;
-}
-
-static void button_interrupt_simulate(int button)
-{
-	button_interrupt(buttons[button].gpio);
-}
-
-static void simulate_button_release_deferred(void)
-{
-	int button_idx;
-
-	/* Release the button */
-	for (button_idx = 0; button_idx < BUTTON_COUNT; button_idx++) {
-		/* Check state for button pressed */
-		if (sim_button_state & BIT(buttons[button_idx].type)) {
-			/* Set state of the button as released */
-			atomic_clear_bits(&sim_button_state,
-					  BIT(buttons[button_idx].type));
-
-			button_interrupt_simulate(button_idx);
-		}
-	}
-}
-DECLARE_DEFERRED(simulate_button_release_deferred);
-
-static void simulate_button(uint32_t button_mask, int press_ms)
-{
-	int button_idx;
-
-	/* Press the button */
-	for (button_idx = 0; button_idx < BUTTON_COUNT; button_idx++) {
-		if (button_mask & BIT(button_idx)) {
-			/* Set state of the button as pressed */
-			atomic_or(&sim_button_state,
-				  BIT(buttons[button_idx].type));
-
-			button_interrupt_simulate(button_idx);
-		}
-	}
-
-	/* Defer the button release for specified duration */
-	hook_call_deferred(&simulate_button_release_deferred_data,
-				press_ms * MSEC);
-}
-#endif /* #ifdef CONFIG_SIMULATED_BUTTON */
-
-#ifdef CONFIG_CMD_BUTTON
-static int console_command_button(int argc, char **argv)
-{
-	int press_ms = 50;
-	char *e;
-	int argv_idx;
-	int button = BUTTON_COUNT;
-	uint32_t button_mask = 0;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	for (argv_idx = 1; argv_idx < argc; argv_idx++) {
-		if (!strcasecmp(argv[argv_idx], "vup"))
-			button = button_present(KEYBOARD_BUTTON_VOLUME_UP);
-		else if (!strcasecmp(argv[argv_idx], "vdown"))
-			button = button_present(KEYBOARD_BUTTON_VOLUME_DOWN);
-		else if (!strcasecmp(argv[argv_idx], "rec"))
-			button = button_present(KEYBOARD_BUTTON_RECOVERY);
-		else {
-			/* If last parameter check if it is an integer. */
-			if (argv_idx == argc - 1) {
-				press_ms = strtoi(argv[argv_idx], &e, 0);
-				/* If integer, break out of the loop. */
-				if (!*e)
-					break;
-			}
-			button = BUTTON_COUNT;
-		}
-
-		if (button == BUTTON_COUNT)
-			return EC_ERROR_PARAM1 + argv_idx - 1;
-
-		button_mask |= BIT(button);
-	}
-
-	if (!button_mask)
-		return EC_SUCCESS;
-
-	simulate_button(button_mask, press_ms);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(button, console_command_button,
-			"vup|vdown|rec msec",
-			"Simulate button press");
-#endif /* CONFIG_CMD_BUTTON */
-
-#ifdef CONFIG_HOSTCMD_BUTTON
-static enum ec_status host_command_button(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_button *p = args->params;
-	int idx;
-	uint32_t button_mask = 0;
-
-	/* Only available on unlocked systems */
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	for (idx = 0; idx < KEYBOARD_BUTTON_COUNT; idx++) {
-		if (p->btn_mask & BIT(idx))
-			button_mask |= BIT(button_present(idx));
-	}
-
-	simulate_button(button_mask, p->press_ms);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BUTTON, host_command_button, EC_VER_MASK(0));
-
-#endif /* CONFIG_HOSTCMD_BUTTON */
-
-
-#ifdef CONFIG_EMULATED_SYSRQ
-
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
-
-/*
- * Simplified sysrq handler
- *
- * In simplified sysrq, user can
- * - press and release recovery button to send one sysrq event to the host
- * - press and hold recovery button for 4 seconds to reset the AP (warm reset)
- */
-static void debug_mode_handle(void)
-{
-	static int recovery_button_pressed = 0;
-
-	if (!recovery_button_pressed) {
-		if (is_recovery_button_pressed()) {
-			/* User pressed recovery button. Wait for 4 seconds
-			 * to see if warm reset is requested. */
-			recovery_button_pressed = 1;
-			hook_call_deferred(&debug_mode_handle_data, 4 * SECOND);
-		}
-	} else {
-		/* We come here when recovery button is released or when
-		 * 4 sec elapsed with recovery button still pressed. */
-		if (!is_recovery_button_pressed()) {
-			/* Cancel pending timer */
-			hook_call_deferred(&debug_mode_handle_data, -1);
-			host_send_sysrq('x');
-			CPRINTS("DEBUG MODE: sysrq-x sent");
-		} else {
-			chipset_reset(CHIPSET_RESET_DBG_WARM_REBOOT);
-			CPRINTS("DEBUG MODE: Warm reset triggered");
-		}
-		recovery_button_pressed = 0;
-	}
-}
-
-#else /* CONFIG_DEDICATED_RECOVERY_BUTTON */
-
-enum debug_state {
-	STATE_DEBUG_NONE,
-	STATE_DEBUG_CHECK,
-	STATE_STAGING,
-	STATE_DEBUG_MODE_ACTIVE,
-	STATE_SYSRQ_PATH,
-	STATE_WARM_RESET_PATH,
-	STATE_SYSRQ_EXEC,
-	STATE_WARM_RESET_EXEC,
-};
-
-#define DEBUG_BTN_POWER         BIT(0)
-#define DEBUG_BTN_VOL_UP        BIT(1)
-#define DEBUG_BTN_VOL_DN        BIT(2)
-#define DEBUG_TIMEOUT           (10 * SECOND)
-
-static enum debug_state curr_debug_state = STATE_DEBUG_NONE;
-static enum debug_state next_debug_state = STATE_DEBUG_NONE;
-static timestamp_t debug_state_deadline;
-static int debug_button_hit_count;
-
-static int debug_button_mask(void)
-{
-	int mask = 0;
-
-	/* Get power button state */
-	if (power_button_is_pressed())
-		mask |= DEBUG_BTN_POWER;
-
-	/* Get volume up state */
-	if (state[BUTTON_VOLUME_UP].debounced_pressed)
-		mask |= DEBUG_BTN_VOL_UP;
-
-	/* Get volume down state */
-	if (state[BUTTON_VOLUME_DOWN].debounced_pressed)
-		mask |= DEBUG_BTN_VOL_DN;
-
-	return mask;
-}
-
-static int debug_button_pressed(int mask)
-{
-	return debug_button_mask() == mask;
-}
-
-#ifdef CONFIG_LED_COMMON
-static int debug_mode_blink_led(void)
-{
-	return ((curr_debug_state != STATE_DEBUG_NONE) &&
-		(curr_debug_state != STATE_DEBUG_CHECK));
-}
-#endif
-
-static void debug_mode_transition(enum debug_state next_state)
-{
-	timestamp_t now = get_time();
-#ifdef CONFIG_LED_COMMON
-	int curr_blink_state = debug_mode_blink_led();
-#endif
-
-	/* Cancel any deferred calls. */
-	hook_call_deferred(&debug_mode_handle_data, -1);
-
-	/* Update current debug mode state. */
-	curr_debug_state = next_state;
-
-	/* Set deadline to 10seconds from current time. */
-	debug_state_deadline.val = now.val + DEBUG_TIMEOUT;
-
-	switch (curr_debug_state) {
-	case STATE_DEBUG_NONE:
-		/*
-		 * Nothing is done here since some states can transition to
-		 * STATE_DEBUG_NONE in this function. Wait until all other
-		 * states are evaluated to take the action for STATE_NONE.
-		 */
-		break;
-	case STATE_DEBUG_CHECK:
-	case STATE_STAGING:
-		break;
-	case STATE_DEBUG_MODE_ACTIVE:
-		debug_button_hit_count = 0;
-		break;
-	case STATE_SYSRQ_PATH:
-		/*
-		 * Increment debug_button_hit_count and ensure it does not go
-		 * past 3. If it exceeds the limit transition to STATE_NONE.
-		 */
-		debug_button_hit_count++;
-		if (debug_button_hit_count == 4)
-			curr_debug_state = STATE_DEBUG_NONE;
-		break;
-	case STATE_WARM_RESET_PATH:
-		break;
-	case STATE_SYSRQ_EXEC:
-		/*
-		 * Depending upon debug_button_hit_count, send appropriate
-		 * number of sysrq events to host and transition to STATE_NONE.
-		 */
-		while (debug_button_hit_count) {
-			host_send_sysrq('x');
-			CPRINTS("DEBUG MODE: sysrq-x sent");
-			debug_button_hit_count--;
-		}
-		curr_debug_state = STATE_DEBUG_NONE;
-		break;
-	case STATE_WARM_RESET_EXEC:
-		/* Warm reset the host and transition to STATE_NONE. */
-		chipset_reset(CHIPSET_RESET_DBG_WARM_REBOOT);
-		CPRINTS("DEBUG MODE: Warm reset triggered");
-		curr_debug_state = STATE_DEBUG_NONE;
-		break;
-	default:
-		curr_debug_state = STATE_DEBUG_NONE;
-	}
-
-	if (curr_debug_state != STATE_DEBUG_NONE) {
-		/*
-		 * Schedule a deferred call after DEBUG_TIMEOUT to check for
-		 * button state if it does not change during the timeout
-		 * duration.
-		 */
-		hook_call_deferred(&debug_mode_handle_data, DEBUG_TIMEOUT);
-		return;
-	}
-
-	/* If state machine reached initial state, reset all variables. */
-	CPRINTS("DEBUG MODE: Exit!");
-	next_debug_state = STATE_DEBUG_NONE;
-	debug_state_deadline.val = 0;
-	debug_button_hit_count = 0;
-#ifdef CONFIG_LED_COMMON
-	if (curr_blink_state)
-		led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_RESET);
-#endif
-}
-
-static void debug_mode_handle(void)
-{
-	int mask;
-
-	switch (curr_debug_state) {
-	case STATE_DEBUG_NONE:
-		/*
-		 * If user pressed Vup+Vdn, check for next 10 seconds to see if
-		 * user keeps holding the keys.
-		 */
-		if (debug_button_pressed(DEBUG_BTN_VOL_UP | DEBUG_BTN_VOL_DN))
-			debug_mode_transition(STATE_DEBUG_CHECK);
-		break;
-	case STATE_DEBUG_CHECK:
-		/*
-		 * If no key is pressed or any key combo other than Vup+Vdn is
-		 * held, then quit debug check mode.
-		 */
-		if (!debug_button_pressed(DEBUG_BTN_VOL_UP | DEBUG_BTN_VOL_DN))
-			debug_mode_transition(STATE_DEBUG_NONE);
-		else if (timestamp_expired(debug_state_deadline, NULL)) {
-			/*
-			 * If Vup+Vdn are held down for 10 seconds, then its
-			 * time to enter debug mode.
-			 */
-			CPRINTS("DEBUG MODE: Active!");
-			next_debug_state = STATE_DEBUG_MODE_ACTIVE;
-			debug_mode_transition(STATE_STAGING);
-		}
-		break;
-	case STATE_STAGING:
-		mask = debug_button_mask();
-
-		/* If no button is pressed, transition to next state. */
-		if (!mask) {
-			debug_mode_transition(next_debug_state);
-			return;
-		}
-
-		/* Exit debug mode if keys are stuck for > 10 seconds. */
-		if (timestamp_expired(debug_state_deadline, NULL))
-			debug_mode_transition(STATE_DEBUG_NONE);
-		else {
-			timestamp_t now = get_time();
-
-			/*
-			 * Schedule a deferred call in case timeout hasn't
-			 * occurred yet.
-			 */
-			hook_call_deferred(&debug_mode_handle_data,
-					(debug_state_deadline.val - now.val));
-		}
-
-		break;
-	case STATE_DEBUG_MODE_ACTIVE:
-		mask = debug_button_mask();
-
-		/*
-		 * Continue in this state if button is not pressed and timeout
-		 * has not occurred.
-		 */
-		if (!mask && !timestamp_expired(debug_state_deadline, NULL))
-			return;
-
-		/* Exit debug mode if valid buttons are not pressed. */
-		if ((mask != DEBUG_BTN_VOL_UP) && (mask != DEBUG_BTN_VOL_DN)) {
-			debug_mode_transition(STATE_DEBUG_NONE);
-			return;
-		}
-
-		/*
-		 * Transition to STAGING state with next state set to:
-		 * 1. SYSRQ_PATH     : If Vup was pressed.
-		 * 2. WARM_RESET_PATH: If Vdn was pressed.
-		 */
-		if (mask == DEBUG_BTN_VOL_UP)
-			next_debug_state = STATE_SYSRQ_PATH;
-		else
-			next_debug_state = STATE_WARM_RESET_PATH;
-
-		debug_mode_transition(STATE_STAGING);
-		break;
-	case STATE_SYSRQ_PATH:
-		mask = debug_button_mask();
-
-		/*
-		 * Continue in this state if button is not pressed and timeout
-		 * has not occurred.
-		 */
-		if (!mask && !timestamp_expired(debug_state_deadline, NULL))
-			return;
-
-		/* Exit debug mode if valid buttons are not pressed. */
-		if ((mask != DEBUG_BTN_VOL_UP) && (mask != DEBUG_BTN_VOL_DN)) {
-			debug_mode_transition(STATE_DEBUG_NONE);
-			return;
-		}
-
-		if (mask == DEBUG_BTN_VOL_UP) {
-			/*
-			 * Else transition to STAGING state with next state set
-			 * to SYSRQ_PATH.
-			 */
-			next_debug_state = STATE_SYSRQ_PATH;
-		} else {
-			/*
-			 * Else if Vdn is pressed, transition to STAGING with
-			 * next state set to SYSRQ_EXEC.
-			 */
-			next_debug_state = STATE_SYSRQ_EXEC;
-		}
-		debug_mode_transition(STATE_STAGING);
-		break;
-	case STATE_WARM_RESET_PATH:
-		mask = debug_button_mask();
-
-		/*
-		 * Continue in this state if button is not pressed and timeout
-		 * has not occurred.
-		 */
-		if (!mask && !timestamp_expired(debug_state_deadline, NULL))
-			return;
-
-		/* Exit debug mode if valid buttons are not pressed. */
-		if (mask != DEBUG_BTN_VOL_UP) {
-			debug_mode_transition(STATE_DEBUG_NONE);
-			return;
-		}
-
-		next_debug_state = STATE_WARM_RESET_EXEC;
-		debug_mode_transition(STATE_STAGING);
-		break;
-	case STATE_SYSRQ_EXEC:
-	case STATE_WARM_RESET_EXEC:
-	default:
-		debug_mode_transition(STATE_DEBUG_NONE);
-		break;
-	}
-}
-
-#ifdef CONFIG_LED_COMMON
-static void debug_led_tick(void)
-{
-	static int led_state = LED_STATE_OFF;
-
-	if (debug_mode_blink_led()) {
-		led_state = !led_state;
-		led_control(EC_LED_ID_SYSRQ_DEBUG_LED, led_state);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, debug_led_tick, HOOK_PRIO_DEFAULT);
-#endif /* CONFIG_LED_COMMON */
-
-#endif /* !CONFIG_DEDICATED_RECOVERY_BUTTON */
-#endif /* CONFIG_EMULATED_SYSRQ */
-
-#ifndef CONFIG_BUTTONS_RUNTIME_CONFIG
-const struct button_config buttons[BUTTON_COUNT] = {
-#else
-struct button_config buttons[BUTTON_COUNT] = {
-#endif
-#ifdef CONFIG_VOLUME_BUTTONS
-	[BUTTON_VOLUME_UP] = {
-		.name = "Volume Up",
-		.type = KEYBOARD_BUTTON_VOLUME_UP,
-		.gpio = GPIO_VOLUME_UP_L,
-		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
-	},
-
-	[BUTTON_VOLUME_DOWN] = {
-		.name = "Volume Down",
-		.type = KEYBOARD_BUTTON_VOLUME_DOWN,
-		.gpio = GPIO_VOLUME_DOWN_L,
-		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
-	},
-
-#endif
-#if defined(CONFIG_DEDICATED_RECOVERY_BUTTON)
-	[BUTTON_RECOVERY] = {
-		.name = "Recovery",
-		.type = KEYBOARD_BUTTON_RECOVERY,
-		.gpio = GPIO_RECOVERY_L,
-		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
-	},
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON_2
-	[BUTTON_RECOVERY_2] = {
-		.name = "Recovery2",
-		.type = KEYBOARD_BUTTON_RECOVERY,
-		.gpio = GPIO_RECOVERY_L_2,
-		.debounce_us = BUTTON_DEBOUNCE_US,
-		.flags = 0,
-	}
-#endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON_2) */
-#endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
-};
-
-#ifdef CONFIG_BUTTON_TRIGGERED_RECOVERY
-/*
- * Prefer the dedicated recovery button over the volume buttons if
- * both are present.
- */
-const struct button_config *recovery_buttons[] = {
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
-	&buttons[BUTTON_RECOVERY],
-
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON_2
-	&buttons[BUTTON_RECOVERY_2],
-#endif /* defined(CONFIG_BUTTON_TRIGGERED_RECOVERY_2) */
-
-#elif defined(CONFIG_VOLUME_BUTTONS)
-	&buttons[BUTTON_VOLUME_DOWN],
-	&buttons[BUTTON_VOLUME_UP],
-#endif /* defined(CONFIG_VOLUME_BUTTONS) */
-};
-const int recovery_buttons_count = ARRAY_SIZE(recovery_buttons);
-#endif /* defined(CONFIG_BUTTON_TRIGGERED_RECOVERY) */
diff --git a/common/capsense.c b/common/capsense.c
deleted file mode 100644
index b2413ac61f..0000000000
--- a/common/capsense.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_protocol.h"
-#include "timer.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-#define CAPSENSE_I2C_ADDR 0x08
-#define CAPSENSE_MASK_BITS 8
-#define CAPSENSE_POLL_INTERVAL (20 * MSEC)
-
-static int capsense_read_bitmask(void)
-{
-	int rv;
-	uint8_t val = 0;
-
-	rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR,
-		      0, 0, &val, 1);
-
-	if (rv)
-		CPRINTS("%s failed: error %d", __func__, rv);
-
-	return val;
-}
-
-static void capsense_init(void)
-{
-	gpio_enable_interrupt(GPIO_CAPSENSE_INT_L);
-}
-DECLARE_HOOK(HOOK_INIT, capsense_init, HOOK_PRIO_DEFAULT);
-
-/*
- * Keep checking polling the capsense until all the buttons are released.
- * We're not worrying about debouncing, since the capsense module should do
- * that for us.
- */
-static void capsense_change_deferred(void)
-{
-	static uint8_t cur_val;
-	uint8_t new_val;
-	int i, n, c;
-
-	new_val = capsense_read_bitmask();
-	if (new_val != cur_val) {
-		CPRINTF("[%pT capsense 0x%02x: ",
-			PRINTF_TIMESTAMP_NOW, new_val);
-		for (i = 0; i < CAPSENSE_MASK_BITS; i++) {
-			/* See what changed */
-			n = (new_val >> i) & 0x01;
-			c = (cur_val >> i) & 0x01;
-			CPRINTF("%s", n ? " X " : " _ ");
-			if (n == c)
-				continue;
-#ifdef HAS_TASK_KEYPROTO
-			/* Treat it as a keyboard event. */
-			keyboard_update_button(i + KEYBOARD_BUTTON_CAPSENSE_1,
-					       n);
-#endif
-		}
-		CPRINTF("]\n");
-		cur_val = new_val;
-	}
-
-	if (cur_val)
-		hook_call_deferred(&capsense_change_deferred_data,
-				   CAPSENSE_POLL_INTERVAL);
-}
-DECLARE_DEFERRED(capsense_change_deferred);
-
-/*
- * Somebody's poking at us.
- */
-void capsense_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&capsense_change_deferred_data, 0);
-}
diff --git a/common/cbi.c b/common/cbi.c
deleted file mode 100644
index 345e313c54..0000000000
--- a/common/cbi.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cros Board Info
- */
-
-#include "common.h"
-#include "console.h"
-#include "crc8.h"
-#include "cros_board_info.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "timer.h"
-
-#ifdef HOST_TOOLS_BUILD
-#include <string.h>
-#else
-#include "util.h"
-#endif
-
-/*
- * Functions and variables defined here shared with host tools (e.g. cbi-util).
- * TODO: Move these to common/cbi/cbi.c and common/cbi/utils.c if they grow.
- */
-uint8_t cbi_crc8(const struct cbi_header *h)
-{
-	return cros_crc8((uint8_t *)&h->crc + 1,
-			 h->total_size - sizeof(h->magic) - sizeof(h->crc));
-}
-
-uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag,
-		      const void *buf, int size)
-{
-	struct cbi_data *d = (struct cbi_data *)p;
-
-	/*
-	 * If size of the data to be added is zero, then no need to add the tag
-	 * as well.
-	 */
-	if (size == 0)
-		return p;
-
-	d->tag = tag;
-	d->size = size;
-	memcpy(d->value, buf, size);
-	p += sizeof(*d) + size;
-	return p;
-}
-
-uint8_t *cbi_set_string(uint8_t *p, enum cbi_data_tag tag, const char *str)
-{
-	if (str == NULL)
-		return p;
-
-	return cbi_set_data(p, tag, str, strlen(str) + 1);
-}
-
-struct cbi_data *cbi_find_tag(const void *buf, enum cbi_data_tag tag)
-{
-	struct cbi_data *d;
-	const struct cbi_header *h = buf;
-	const uint8_t *p;
-	for (p = h->data; p + sizeof(*d) < (uint8_t *)buf + h->total_size;) {
-		d = (struct cbi_data *)p;
-		if (d->tag == tag)
-			return d;
-		p += sizeof(*d) + d->size;
-	}
-	return NULL;
-}
-
-/*
- * Functions and variables specific to EC firmware
- */
-#ifndef HOST_TOOLS_BUILD
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
-
-static int cache_status = CBI_CACHE_STATUS_INVALID;
-static uint8_t cbi[CBI_IMAGE_SIZE];
-static struct cbi_header * const head = (struct cbi_header *)cbi;
-
-int cbi_create(void)
-{
-	memset(cbi, 0, sizeof(cbi));
-	memcpy(head->magic, cbi_magic, sizeof(cbi_magic));
-	head->total_size = sizeof(*head);
-	head->major_version = CBI_VERSION_MAJOR;
-	head->minor_version = CBI_VERSION_MINOR;
-	head->crc = cbi_crc8(head);
-	cache_status = CBI_CACHE_STATUS_SYNCED;
-
-	return EC_SUCCESS;
-}
-
-void cbi_invalidate_cache(void)
-{
-	cache_status = CBI_CACHE_STATUS_INVALID;
-}
-
-int cbi_get_cache_status(void)
-{
-	return cache_status;
-}
-
-static int do_cbi_read(void)
-{
-	CPRINTS("Reading board info");
-
-	/* Read header */
-	if (cbi_config.drv->load(0, cbi, sizeof(*head))) {
-		CPRINTS("Failed to read header");
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check magic */
-	if (memcmp(head->magic, cbi_magic, sizeof(head->magic))) {
-		CPRINTS("Bad magic");
-		return EC_ERROR_INVAL;
-	}
-
-	/* check version */
-	if (head->major_version > CBI_VERSION_MAJOR) {
-		CPRINTS("Version mismatch");
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Check the data size. It's expected to support up to 64k but our
-	 * buffer has practical limitation.
-	 */
-	if (head->total_size < sizeof(*head) ||
-			head->total_size > CBI_IMAGE_SIZE) {
-		CPRINTS("Bad size: %d", head->total_size);
-		return EC_ERROR_OVERFLOW;
-	}
-
-	/* Read the data */
-	if (cbi_config.drv->load(sizeof(*head), head->data,
-			head->total_size - sizeof(*head))) {
-		CPRINTS("Failed to read body");
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check CRC. This supports new fields unknown to this parser. */
-	if (cbi_config.storage_type != CBI_STORAGE_TYPE_GPIO &&
-			cbi_crc8(head) != head->crc) {
-		CPRINTS("Bad CRC");
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int cbi_read(void)
-{
-	int i;
-	int rv;
-
-	if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
-		return EC_SUCCESS;
-
-	for (i = 0; i < 2; i++) {
-		rv = do_cbi_read();
-		if (rv == EC_SUCCESS) {
-			cache_status = CBI_CACHE_STATUS_SYNCED;
-			return EC_SUCCESS;
-		}
-		/* On error (I2C or bad contents), retry a read */
-	}
-
-	return rv;
-}
-
-__attribute__((weak))
-int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
-{
-	return EC_SUCCESS;
-}
-
-int cbi_get_board_info(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
-{
-	const struct cbi_data *d;
-
-	if (cbi_read())
-		return EC_ERROR_UNKNOWN;
-
-	d = cbi_find_tag(cbi, tag);
-	if (!d)
-		/* Not found */
-		return EC_ERROR_UNKNOWN;
-	if (*size < d->size)
-		/* Insufficient buffer size */
-		return EC_ERROR_INVAL;
-
-	/* Clear the buffer in case len < *size */
-	memset(buf, 0, *size);
-	/* Copy the value */
-	memcpy(buf, d->value, d->size);
-	*size = d->size;
-
-	return cbi_board_override(tag, buf, size);
-}
-
-static void cbi_remove_tag(void *const cbi, struct cbi_data *const d)
-{
-	struct cbi_header *const h = cbi;
-	const size_t size = sizeof(*d) + d->size;
-	const uint8_t *next = (uint8_t *)d + size;
-	const size_t bytes_after = ((uint8_t *)cbi + h->total_size) - next;
-
-	memmove(d, next, bytes_after);
-	h->total_size -= size;
-}
-
-int cbi_set_board_info(enum cbi_data_tag tag, const uint8_t *buf, uint8_t size)
-{
-	struct cbi_data *d;
-
-	d = cbi_find_tag(cbi, tag);
-
-	/* If we found the entry, but the size doesn't match, delete it */
-	if (d && d->size != size) {
-		cbi_remove_tag(cbi, d);
-		d = NULL;
-	}
-
-	if (!d) {
-		uint8_t *p;
-		/* Not found. Check if new item would fit */
-		if (sizeof(cbi) < head->total_size + sizeof(*d) + size)
-			return EC_ERROR_OVERFLOW;
-		/* Append new item */
-		p = cbi_set_data(&cbi[head->total_size], tag, buf, size);
-		head->total_size = p - cbi;
-	} else {
-		/* Overwrite existing item */
-		memcpy(d->value, buf, d->size);
-	}
-
-	return EC_SUCCESS;
-}
-
-int cbi_write(void)
-{
-	if (cbi_config.drv->is_protected()) {
-		CPRINTS("Failed to write due to WP");
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	return cbi_config.drv->store(cbi);
-}
-
-int cbi_get_board_version(uint32_t *ver)
-{
-	uint8_t size = sizeof(*ver);
-
-	return cbi_get_board_info(CBI_TAG_BOARD_VERSION, (uint8_t *)ver, &size);
-}
-
-int cbi_get_sku_id(uint32_t *id)
-{
-	uint8_t size = sizeof(*id);
-
-	return cbi_get_board_info(CBI_TAG_SKU_ID, (uint8_t *)id, &size);
-}
-
-int cbi_get_oem_id(uint32_t *id)
-{
-	uint8_t size = sizeof(*id);
-
-	return cbi_get_board_info(CBI_TAG_OEM_ID, (uint8_t *)id, &size);
-}
-
-int cbi_get_model_id(uint32_t *id)
-{
-	uint8_t size = sizeof(*id);
-
-	return cbi_get_board_info(CBI_TAG_MODEL_ID, (uint8_t *)id, &size);
-}
-
-int cbi_get_fw_config(uint32_t *fw_config)
-{
-	uint8_t size = sizeof(*fw_config);
-
-	return cbi_get_board_info(CBI_TAG_FW_CONFIG, (uint8_t *)fw_config,
-				  &size);
-}
-
-int cbi_get_ssfc(uint32_t *ssfc)
-{
-	uint8_t size = sizeof(*ssfc);
-
-	return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc,
-				  &size);
-}
-
-int cbi_get_pcb_supplier(uint32_t *pcb_supplier)
-{
-	uint8_t size = sizeof(*pcb_supplier);
-
-	return cbi_get_board_info(CBI_TAG_PCB_SUPPLIER, (uint8_t *)pcb_supplier,
-			&size);
-}
-
-int cbi_get_rework_id(uint64_t *id)
-{
-	uint8_t size = sizeof(*id);
-	return cbi_get_board_info(CBI_TAG_REWORK_ID, (uint8_t *)id, &size);
-}
-
-static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
-{
-	const struct __ec_align4 ec_params_get_cbi *p = args->params;
-	uint8_t size = MIN(args->response_max, UINT8_MAX);
-
-	if (p->flag & CBI_GET_RELOAD)
-		cbi_invalidate_cache();
-
-	if (cbi_get_board_info(p->tag, args->response, &size))
-		return EC_RES_INVALID_PARAM;
-
-	args->response_size = size;
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO,
-		     hc_cbi_get,
-		     EC_VER_MASK(0));
-
-static enum ec_status common_cbi_set(const struct __ec_align4
-							ec_params_set_cbi * p)
-{
-	/*
-	 * If we ultimately cannot write to the flash, then fail early unless
-	 * we are explicitly trying to write to the in-memory CBI only
-	 */
-	if (cbi_config.drv->is_protected() &&
-	    !(p->flag & CBI_SET_NO_SYNC)) {
-		CPRINTS("Failed to write due to WP");
-		return EC_RES_ACCESS_DENIED;
-	}
-
-#ifndef CONFIG_SYSTEM_UNLOCKED
-	/*
-	 * These fields are not allowed to be reprogrammed regardless the
-	 * hardware WP state. They're considered as a part of the hardware.
-	 */
-	if (p->tag == CBI_TAG_BOARD_VERSION || p->tag == CBI_TAG_OEM_ID)
-		return EC_RES_ACCESS_DENIED;
-#endif
-
-	if (p->flag & CBI_SET_INIT) {
-		memset(cbi, 0, sizeof(cbi));
-		memcpy(head->magic, cbi_magic, sizeof(cbi_magic));
-		head->total_size = sizeof(*head);
-	} else {
-		if (cbi_read())
-			return EC_RES_ERROR;
-	}
-
-	if (cbi_set_board_info(p->tag, p->data, p->size))
-		return EC_RES_INVALID_PARAM;
-
-	/*
-	 * Whether we're modifying existing data or creating new one,
-	 * we take over the format.
-	 */
-	head->major_version = CBI_VERSION_MAJOR;
-	head->minor_version = CBI_VERSION_MINOR;
-	head->crc = cbi_crc8(head);
-	cache_status = CBI_CACHE_STATUS_SYNCED;
-
-	/* Skip write if client asks so. */
-	if (p->flag & CBI_SET_NO_SYNC)
-		return EC_RES_SUCCESS;
-
-	/* We already checked write protect failure case. */
-	if (cbi_write())
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
-{
-	const struct __ec_align4 ec_params_set_cbi * p = args->params;
-
-	/* Given data size exceeds the packet size. */
-	if (args->params_size < sizeof(*p) + p->size)
-		return EC_RES_INVALID_PARAM;
-
-	return common_cbi_set(p);
-}
-DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO,
-		     hc_cbi_set,
-		     EC_VER_MASK(0));
-
-#ifdef CONFIG_CMD_CBI
-static void print_tag(const char * const tag, int rv, const uint32_t *val)
-{
-	ccprintf("%s", tag);
-	if (rv == EC_SUCCESS && val)
-		ccprintf(": %u (0x%x)\n", *val, *val);
-	else
-		ccprintf(": (Error %d)\n", rv);
-}
-
-static void print_uint64_tag(const char * const tag, int rv,
-			     const uint64_t *lval)
-{
-	ccprintf("%s", tag);
-	if (rv == EC_SUCCESS && lval)
-		ccprintf(": %llu (0x%llx)\n", *(unsigned long long *)lval,
-			 *(unsigned long long *)lval);
-	else
-		ccprintf(": (Error %d)\n", rv);
-}
-
-static void dump_cbi(void)
-{
-	uint32_t val;
-	uint64_t lval;
-
-	/* Ensure we read the latest data from flash. */
-	cbi_invalidate_cache();
-	cbi_read();
-
-	if (cbi_get_cache_status() != CBI_CACHE_STATUS_SYNCED) {
-		ccprintf("Cannot Read CBI (Error %d)\n", cbi_get_cache_status());
-		return;
-	}
-
-	ccprintf("CBI_VERSION: 0x%04x\n", head->version);
-	ccprintf("TOTAL_SIZE: %u\n", head->total_size);
-
-	print_tag("BOARD_VERSION", cbi_get_board_version(&val), &val);
-	print_tag("OEM_ID", cbi_get_oem_id(&val), &val);
-	print_tag("MODEL_ID", cbi_get_model_id(&val), &val);
-	print_tag("SKU_ID", cbi_get_sku_id(&val), &val);
-	print_tag("FW_CONFIG", cbi_get_fw_config(&val), &val);
-	print_tag("PCB_SUPPLIER", cbi_get_pcb_supplier(&val), &val);
-	print_tag("SSFC", cbi_get_ssfc(&val), &val);
-	print_uint64_tag("REWORK_ID", cbi_get_rework_id(&lval), &lval);
-}
-
-/*
- * Space for the set command (does not include data space) plus maximum
- * possible console input
- */
-static uint8_t buf[sizeof(struct ec_params_set_cbi) + \
-		       CONFIG_CONSOLE_INPUT_LINE_SIZE];
-
-static int cc_cbi(int argc, char **argv)
-{
-	struct __ec_align4 ec_params_set_cbi * setter =
-		(struct __ec_align4 ec_params_set_cbi *)buf;
-	int last_arg;
-	char *e;
-
-	if (argc == 1) {
-		dump_cbi();
-		if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
-			hexdump(cbi, CBI_IMAGE_SIZE);
-		return EC_SUCCESS;
-	}
-
-	if (strcasecmp(argv[1], "set") == 0) {
-		if (argc < 5) {
-			ccprintf("Set requires: <tag> <value> <size>\n");
-			return EC_ERROR_PARAM_COUNT;
-		}
-
-		setter->tag = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		if (setter->tag == CBI_TAG_DRAM_PART_NUM ||
-		    setter->tag == CBI_TAG_OEM_NAME) {
-			setter->size = strlen(argv[3]) + 1;
-			memcpy(setter->data, argv[3], setter->size);
-		} else {
-			uint64_t val = strtoull(argv[3], &e, 0);
-
-			if (*e)
-				return EC_ERROR_PARAM3;
-
-			setter->size = strtoi(argv[4], &e, 0);
-			if (*e)
-				return EC_ERROR_PARAM4;
-
-			if (setter->size < 1) {
-				ccprintf("Set size too small\n");
-				return EC_ERROR_PARAM4;
-			} else if (setter->tag == CBI_TAG_REWORK_ID &&
-				   setter->size > 8) {
-				ccprintf("Set size too large\n");
-				return EC_ERROR_PARAM4;
-			} else if (setter->size > 4) {
-				ccprintf("Set size too large\n");
-				return EC_ERROR_PARAM4;
-			}
-
-			memcpy(setter->data, &val, setter->size);
-		}
-
-		last_arg = 5;
-	} else if (strcasecmp(argv[1], "remove") == 0) {
-		if (argc < 3) {
-			ccprintf("Remove requires: <tag>\n");
-			return EC_ERROR_PARAM_COUNT;
-		}
-
-		setter->tag = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		setter->size = 0;
-		last_arg = 3;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	setter->flag = 0;
-
-	if (argc > last_arg) {
-		int i;
-
-		for (i = last_arg; i < argc; i++) {
-			if (strcasecmp(argv[i], "init") == 0) {
-				setter->flag |= CBI_SET_INIT;
-			} else if (strcasecmp(argv[i], "skip_write") == 0) {
-				setter->flag |= CBI_SET_NO_SYNC;
-			} else {
-				ccprintf("Invalid additional option\n");
-				return EC_ERROR_PARAM1 + i - 1;
-			}
-		}
-	}
-
-	if (common_cbi_set(setter) == EC_RES_SUCCESS)
-		return EC_SUCCESS;
-
-	return EC_ERROR_UNKNOWN;
-}
-DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, "[set <tag> <value> <size> | "
-			"remove <tag>] [init | skip_write]",
-			"Print or change Cros Board Info from flash");
-#endif /* CONFIG_CMD_CBI */
-
-#ifndef HAS_TASK_CHIPSET
-int cbi_set_fw_config(uint32_t fw_config)
-{
-	/* Check write protect status */
-	if (cbi_config.drv->is_protected())
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Ensure that CBI has been configured */
-	if (cbi_read())
-		cbi_create();
-
-	/* Update the FW_CONFIG field */
-	cbi_set_board_info(CBI_TAG_FW_CONFIG, (uint8_t *)&fw_config,
-			   sizeof(int));
-
-	/* Update CRC calculation and write to the storage */
-	head->crc = cbi_crc8(head);
-	if (cbi_write())
-		return EC_ERROR_UNKNOWN;
-
-	dump_cbi();
-
-	return EC_SUCCESS;
-}
-#endif
-
-#endif /* !HOST_TOOLS_BUILD */
diff --git a/common/cbi_eeprom.c b/common/cbi_eeprom.c
deleted file mode 100644
index 2761f0b977..0000000000
--- a/common/cbi_eeprom.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Support Cros Board Info EEPROM */
-
-#include "console.h"
-#include "cros_board_info.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
-
-/*
- * We allow EEPROMs with page size of 8 or 16. Use 8 to be the most compatible.
- * This causes a little more overhead for writes, but we are not writing to the
- * EEPROM outside of the factory process.
- */
-#define EEPROM_PAGE_WRITE_SIZE	8
-#define EEPROM_PAGE_WRITE_MS	5
-
-static int eeprom_read(uint8_t offset, uint8_t *data, int len)
-{
-	return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-			      offset, data, len);
-}
-
-static int eeprom_is_write_protected(void)
-{
-	if (IS_ENABLED(CONFIG_BYPASS_CBI_EEPROM_WP_CHECK))
-		return 0;
-#if defined(CONFIG_WP_ACTIVE_HIGH)
-	return gpio_get_level(GPIO_WP);
-#else
-	return !gpio_get_level(GPIO_WP_L);
-#endif
-}
-
-static int eeprom_write(uint8_t *cbi)
-{
-	uint8_t *p = cbi;
-	int rest = ((struct cbi_header *)p)->total_size;
-
-	while (rest > 0) {
-		int size = MIN(EEPROM_PAGE_WRITE_SIZE, rest);
-		int rv;
-
-		rv = i2c_write_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-				     p - cbi, p, size);
-		if (rv) {
-			CPRINTS("Failed to write for %d", rv);
-			return rv;
-		}
-		/* Wait for internal write cycle completion */
-		msleep(EEPROM_PAGE_WRITE_MS);
-		p += size;
-		rest -= size;
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_EEPROM_CBI_WP
-void cbi_latch_eeprom_wp(void)
-{
-	CPRINTS("WP latched");
-	gpio_set_level(GPIO_EC_CBI_WP, 1);
-}
-#endif /* CONFIG_EEPROM_CBI_WP */
-
-const struct cbi_storage_driver eeprom_drv = {
-	.store = eeprom_write,
-	.load = eeprom_read,
-	.is_protected = eeprom_is_write_protected,
-};
-
-const struct cbi_storage_config_t cbi_config = {
-	.storage_type = CBI_STORAGE_TYPE_EEPROM,
-	.drv = &eeprom_drv,
-};
diff --git a/common/cbi_gpio.c b/common/cbi_gpio.c
deleted file mode 100644
index 7b9fb25ebb..0000000000
--- a/common/cbi_gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Support Cros Board Info GPIO */
-
-#include "console.h"
-#include "cros_board_info.h"
-#include "gpio.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
-
-static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len)
-{
-	int board_id;
-	int sku_id;
-	int rv;
-	int err = 0;
-
-	if (cbi_get_cache_status() == CBI_CACHE_STATUS_SYNCED)
-		return EC_SUCCESS;
-
-	cbi_create();
-
-	board_id = system_get_board_version();
-	if (board_id < 0) {
-		CPRINTS("Failed (%d) to get a valid board id", -board_id);
-		err++;
-	} else {
-		rv = cbi_set_board_info(CBI_TAG_BOARD_VERSION,
-					(uint8_t *)&board_id, sizeof(int));
-		if (rv) {
-			CPRINTS("Failed (%d) to set BOARD_VERSION tag", rv);
-			err++;
-		}
-	}
-
-	sku_id = system_get_sku_id();
-	rv = cbi_set_board_info(CBI_TAG_SKU_ID,
-				(uint8_t *)&sku_id, sizeof(int));
-	if (rv) {
-		CPRINTS("Failed (%d) to set SKU_ID tag", rv);
-		err++;
-	}
-
-	if (err > 0)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static int cbi_gpio_is_write_protected(void)
-{
-	/*
-	 * When CBI comes from strapping pins, any attempts for updating CBI
-	 * storage should be rejected.
-	 */
-	return 1;
-}
-
-const struct cbi_storage_driver gpio_drv = {
-	.load = cbi_gpio_read,
-	.is_protected = cbi_gpio_is_write_protected,
-};
-
-const struct cbi_storage_config_t cbi_config = {
-	.storage_type = CBI_STORAGE_TYPE_GPIO,
-	.drv = &gpio_drv,
-};
diff --git a/common/cec.c b/common/cec.c
deleted file mode 100644
index 1bc3273c1d..0000000000
--- a/common/cec.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cec.h"
-#include "console.h"
-#include "task.h"
-
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
-
-/*
- * Mutex for the read-offset of the rx queue. Needed since the
- * queue is read and flushed from different contexts
- */
-static struct mutex rx_queue_readoffset_mutex;
-
-int cec_transfer_get_bit(const struct cec_msg_transfer *transfer)
-{
-	if (transfer->byte >= MAX_CEC_MSG_LEN)
-		return 0;
-
-	return transfer->buf[transfer->byte] & (0x80 >> transfer->bit);
-}
-
-void cec_transfer_set_bit(struct cec_msg_transfer *transfer, int val)
-{
-	uint8_t bit_flag;
-
-	if (transfer->byte >= MAX_CEC_MSG_LEN)
-		return;
-	bit_flag = 0x80 >> transfer->bit;
-	transfer->buf[transfer->byte] &= ~bit_flag;
-	if (val)
-		transfer->buf[transfer->byte] |= bit_flag;
-}
-
-void cec_transfer_inc_bit(struct cec_msg_transfer *transfer)
-{
-	if (++(transfer->bit) == 8) {
-		if (transfer->byte >= MAX_CEC_MSG_LEN)
-			return;
-		transfer->bit = 0;
-		transfer->byte++;
-	}
-}
-
-int cec_transfer_is_eom(const struct cec_msg_transfer *transfer, int len)
-{
-	if (transfer->bit)
-		return 0;
-	return (transfer->byte == len);
-}
-
-void cec_rx_queue_flush(struct cec_rx_queue *queue)
-{
-	mutex_lock(&rx_queue_readoffset_mutex);
-	queue->read_offset = 0;
-	mutex_unlock(&rx_queue_readoffset_mutex);
-	queue->write_offset = 0;
-}
-
-int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
-		      uint8_t msg_len)
-{
-	int i;
-	uint32_t offset;
-
-	if (msg_len > MAX_CEC_MSG_LEN || msg_len == 0)
-		return EC_ERROR_INVAL;
-
-	offset = queue->write_offset;
-	/* Fill in message length last, if successful. Set to zero for now */
-	queue->buf[offset] = 0;
-	offset = (offset + 1) % CEC_RX_BUFFER_SIZE;
-
-	for (i = 0 ; i < msg_len; i++) {
-		if (offset == queue->read_offset) {
-			/* Buffer full */
-			return EC_ERROR_OVERFLOW;
-		}
-
-		queue->buf[offset] = msg[i];
-		offset = (offset + 1) % CEC_RX_BUFFER_SIZE;
-	}
-
-	/*
-	 * Don't commit if we caught up with read-offset
-	 * since that would indicate an empty buffer
-	 */
-	if (offset == queue->read_offset) {
-		/* Buffer full */
-		return EC_ERROR_OVERFLOW;
-	}
-
-	/* Commit the push */
-	queue->buf[queue->write_offset] = msg_len;
-	queue->write_offset = offset;
-
-	return EC_SUCCESS;
-}
-
-int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
-		     uint8_t *msg_len)
-{
-	int i;
-
-	mutex_lock(&rx_queue_readoffset_mutex);
-	if (queue->read_offset == queue->write_offset) {
-		/* Queue empty */
-		mutex_unlock(&rx_queue_readoffset_mutex);
-		*msg_len = 0;
-		return -1;
-	}
-
-	/* The first byte in the buffer is the message length */
-	*msg_len = queue->buf[queue->read_offset];
-	if (*msg_len == 0 || *msg_len > MAX_CEC_MSG_LEN) {
-		mutex_unlock(&rx_queue_readoffset_mutex);
-		*msg_len = 0;
-		CPRINTF("Invalid CEC msg size: %u\n", *msg_len);
-		return -1;
-	}
-
-	queue->read_offset = (queue->read_offset + 1) % CEC_RX_BUFFER_SIZE;
-	for (i = 0; i < *msg_len; i++) {
-		msg[i] = queue->buf[queue->read_offset];
-		queue->read_offset = (queue->read_offset + 1) %
-							CEC_RX_BUFFER_SIZE;
-
-	}
-
-	mutex_unlock(&rx_queue_readoffset_mutex);
-
-	return 0;
-}
diff --git a/common/charge_manager.c b/common/charge_manager.c
deleted file mode 100644
index 862bb28725..0000000000
--- a/common/charge_manager.c
+++ /dev/null
@@ -1,1625 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "atomic.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "console.h"
-#include "dps.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#ifdef HAS_MOCK_CHARGE_MANAGER
-#error Mock defined HAS_MOCK_CHARGE_MANAGER
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#define POWER(charge_port) ((charge_port.current) * (charge_port.voltage))
-
-/* Timeout for delayed override power swap, allow for 500ms extra */
-#define POWER_SWAP_TIMEOUT (PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + \
-			    PD_T_SAFE_0V + 500 * MSEC)
-
-/*
- * Default charge supplier priority
- *
- * - Always pick dedicated charge if present since that is the best product
- *   decision.
- * - Pick PD negotiated chargers over everything else since they have the most
- *   power potential and they may not currently be negotiated at a high power.
- *   (and they can at least provide 15W)
- * - Pick Type-C which supplier current >= 1.5A, which has higher prioirty
- *   than the BC1.2 and Type-C with current under 1.5A. (USB-C spec 1.3
- *   Table 4-17: TYPEC 3.0A, 1.5A > BC1.2 > TYPEC under 1.5A)
- * - Then pick among the propreitary and BC1.2 chargers which ever has the
- *   highest available power.
- * - Last, pick one from the rest suppliers.  Also note that some boards assume
- *   wireless suppliers as low priority.
- */
-__overridable const int supplier_priority[] = {
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	[CHARGE_SUPPLIER_DEDICATED] = 0,
-#endif
-	[CHARGE_SUPPLIER_PD] = 1,
-	[CHARGE_SUPPLIER_TYPEC] = 2,
-	[CHARGE_SUPPLIER_TYPEC_DTS] = 2,
-#ifdef CHARGE_MANAGER_BC12
-	[CHARGE_SUPPLIER_PROPRIETARY] = 3,
-	[CHARGE_SUPPLIER_BC12_DCP] = 3,
-	[CHARGE_SUPPLIER_BC12_CDP] = 3,
-	[CHARGE_SUPPLIER_BC12_SDP] = 3,
-	[CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = 4,
-	[CHARGE_SUPPLIER_OTHER] = 4,
-	[CHARGE_SUPPLIER_VBUS] = 4,
-#endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	[CHARGE_SUPPLIER_WPC_BPP] = 5,
-	[CHARGE_SUPPLIER_WPC_EPP] = 5,
-	[CHARGE_SUPPLIER_WPC_GPP] = 5,
-#endif
-
-};
-BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
-
-/* Keep track of available charge for each charge port. */
-static struct charge_port_info available_charge[CHARGE_SUPPLIER_COUNT]
-					       [CHARGE_PORT_COUNT];
-
-/* Keep track of when the supplier on each port is registered. */
-static timestamp_t registration_time[CHARGE_PORT_COUNT];
-
-/*
- * Charge current ceiling (mA) for ports. This can be set to temporarily limit
- * the charge pulled from a port, without influencing the port selection logic.
- * The ceiling can be set independently from several requestors, with the
- * minimum ceiling taking effect.
- */
-static int charge_ceil[CHARGE_PORT_COUNT][CEIL_REQUESTOR_COUNT];
-
-/* Dual-role capability of attached partner port */
-static enum dualrole_capabilities dualrole_capability[CHARGE_PORT_COUNT];
-
-#ifdef CONFIG_USB_PD_LOGGING
-/* Mark port as dirty when making changes, for later logging */
-static int save_log[CHARGE_PORT_COUNT];
-#endif
-
-/* Store current state of port enable / charge current. */
-static int charge_port = CHARGE_PORT_NONE;
-static int charge_current = CHARGE_CURRENT_UNINITIALIZED;
-static int charge_current_uncapped = CHARGE_CURRENT_UNINITIALIZED;
-static int charge_voltage;
-static int charge_supplier = CHARGE_SUPPLIER_NONE;
-static int override_port = OVERRIDE_OFF;
-
-static int delayed_override_port = OVERRIDE_OFF;
-static timestamp_t delayed_override_deadline;
-
-/* Source-out Rp values for TCPMv1 */
-__maybe_unused static uint8_t source_port_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#ifdef CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT
-/* 3A on one port and 1.5A on the rest */
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT * 1500 + 1500 <=
-	     CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT);
-#endif
-
-/*
- * charge_manager initially operates in safe mode until asked to leave (through
- * charge_manager_leave_safe_mode()). While in safe mode, the following
- * behavior is altered:
- *
- * 1) All chargers are considered dedicated (and thus are valid charge source
- *    candidates) for the purpose of port selection.
- * 2) Charge ceilings are ignored. Most significantly, ILIM won't drop on PD
- *    voltage transition. If current load is high during transition, some
- *    chargers may brown-out.
- * 3) CHARGE_PORT_NONE will not be selected (POR default charge port will
- *    remain selected rather than CHARGE_PORT_NONE).
- *
- * After leaving safe mode, charge_manager reverts to its normal behavior and
- * immediately selects charge port and current using standard rules.
- */
-#ifdef CONFIG_CHARGE_MANAGER_SAFE_MODE
-static int left_safe_mode;
-#else
-static const int left_safe_mode = 1;
-#endif
-
-enum charge_manager_change_type {
-	CHANGE_CHARGE,
-	CHANGE_DUALROLE,
-};
-
-static int is_pd_port(int port)
-{
-	return port >= 0 && port < board_get_usb_pd_port_count();
-}
-
-static int is_sink(int port)
-{
-	if (!is_pd_port(port))
-		return board_charge_port_is_sink(port);
-
-	return pd_get_power_role(port) == PD_ROLE_SINK;
-}
-
-/**
- * Some of the SKUs in certain boards have less number of USB PD ports than
- * defined in CONFIG_USB_PD_PORT_MAX_COUNT. With the charge port configuration
- * for DEDICATED_PORT towards the end, this will lead to holes in the static
- * configuration. The ports that fall in that hole are invalid and this function
- * is used to check the validity of the ports.
- */
-static int is_valid_port(int port)
-{
-	if (port < 0 || port >= CHARGE_PORT_COUNT)
-		return 0;
-
-	/* Check if the port falls in the hole */
-	if (port >= board_get_usb_pd_port_count() &&
-	    port < CONFIG_USB_PD_PORT_MAX_COUNT)
-		return 0;
-	return 1;
-}
-
-#ifndef TEST_BUILD
-static int is_connected(int port)
-{
-	if (!is_pd_port(port))
-		return board_charge_port_is_connected(port);
-
-	return pd_is_connected(port);
-}
-#endif /* !TEST_BUILD */
-
-#ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-/**
- * In certain cases we need to override the default behavior of not charging
- * from non-dedicated chargers. If the system is in RO and locked, we have no
- * way of determining the actual dualrole capability of the charger because
- * PD communication is not allowed, so we must assume that it is dedicated.
- * Also, if no battery is present, the charger may be our only source of power,
- * so again we must assume that the charger is dedicated.
- *
- * @return	1 when we need to override the a non-dedicated charger
- *		to be a dedicated one, 0 otherwise.
- */
-static int charge_manager_spoof_dualrole_capability(void)
-{
-	return (system_get_image_copy() == EC_IMAGE_RO &&
-		system_is_locked()) || !left_safe_mode;
-
-}
-#endif /* !CONFIG_CHARGE_MANAGER_DRP_CHARGING */
-
-/**
- * Initialize available charge. Run before board init, so board init can
- * initialize data, if needed.
- */
-static void charge_manager_init(void)
-{
-	int i, j;
-
-	for (i = 0; i < CHARGE_PORT_COUNT; ++i) {
-		if (!is_valid_port(i))
-			continue;
-		for (j = 0; j < CHARGE_SUPPLIER_COUNT; ++j) {
-			available_charge[j][i].current =
-				CHARGE_CURRENT_UNINITIALIZED;
-			available_charge[j][i].voltage =
-				CHARGE_VOLTAGE_UNINITIALIZED;
-		}
-		for (j = 0; j < CEIL_REQUESTOR_COUNT; ++j)
-			charge_ceil[i][j] = CHARGE_CEIL_NONE;
-		if (!is_pd_port(i))
-			dualrole_capability[i] = CAP_DEDICATED;
-		if (is_pd_port(i) && !IS_ENABLED(CONFIG_USB_PD_TCPMV2))
-			source_port_rp[i] = CONFIG_USB_PD_PULLUP;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, charge_manager_init, HOOK_PRIO_CHARGE_MANAGER_INIT);
-
-/**
- * Check if the charge manager is seeded.
- *
- * @return	1 if all ports/suppliers have reported
- *		with some initial charge, 0 otherwise.
- */
-static int charge_manager_is_seeded(void)
-{
-	/* Once we're seeded, we don't need to check again. */
-	static int is_seeded;
-	int i, j;
-
-	if (is_seeded)
-		return 1;
-
-	for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i) {
-		for (j = 0; j < CHARGE_PORT_COUNT; ++j) {
-			if (!is_valid_port(j))
-				continue;
-			if (available_charge[i][j].current ==
-			    CHARGE_CURRENT_UNINITIALIZED ||
-			    available_charge[i][j].voltage ==
-			    CHARGE_VOLTAGE_UNINITIALIZED)
-				return 0;
-		}
-	}
-	is_seeded = 1;
-	return 1;
-}
-
-#ifndef TEST_BUILD
-/**
- * Get the maximum charge current for a port.
- *
- * @param port	Charge port.
- * @return	Charge current (mA).
- */
-__maybe_unused static int charge_manager_get_source_current(int port)
-{
-	if (!is_pd_port(port))
-		return 0;
-
-	switch (source_port_rp[port]) {
-	case TYPEC_RP_3A0:
-		return 3000;
-	case TYPEC_RP_1A5:
-		return 1500;
-	case TYPEC_RP_USB:
-	default:
-		return 500;
-	}
-}
-
-/*
- * Find a supplier considering available current, voltage, power, and priority.
- */
-static enum charge_supplier find_supplier(int port, enum charge_supplier sup,
-					  int min_cur)
-{
-	int i;
-	for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i) {
-		if (available_charge[i][port].current <= min_cur ||
-		    available_charge[i][port].voltage <= 0)
-			/* Doesn't meet volt or current requirement. Skip it. */
-			continue;
-		if (sup == CHARGE_SUPPLIER_NONE)
-			/* Haven't found any yet. Take it unconditionally. */
-			sup = i;
-		else if (supplier_priority[sup] < supplier_priority[i])
-			/* There is already a higher priority supplier. */
-			continue;
-		else if (supplier_priority[i] < supplier_priority[sup])
-			/* This has a higher priority. Take it. */
-			sup = i;
-		else if (POWER(available_charge[i][port]) >
-			 POWER(available_charge[sup][port]))
-			/* Priority is tie. Take it if power is higher. */
-			sup = i;
-	}
-	return sup;
-}
-
-static enum charge_supplier get_current_supplier(int port)
-{
-	enum charge_supplier supplier = CHARGE_SUPPLIER_NONE;
-
-	/* Determine supplier information to show. */
-	if (port == charge_port) {
-		supplier = charge_supplier;
-	} else {
-		/* Consider available current */
-		supplier = find_supplier(port, supplier, 0);
-		if (supplier == CHARGE_SUPPLIER_NONE)
-			/* Ignore available current */
-			supplier = find_supplier(port, supplier, -1);
-	}
-
-	return supplier;
-}
-static enum usb_power_roles get_current_power_role(int port,
-		enum charge_supplier supplier)
-{
-	enum usb_power_roles role;
-	if (charge_port == port)
-		role = USB_PD_PORT_POWER_SINK;
-	else if (is_connected(port) && !is_sink(port))
-		role = USB_PD_PORT_POWER_SOURCE;
-	else if (supplier != CHARGE_SUPPLIER_NONE)
-		role = USB_PD_PORT_POWER_SINK_NOT_CHARGING;
-	else
-		role = USB_PD_PORT_POWER_DISCONNECTED;
-	return role;
-}
-
-__overridable int board_get_vbus_voltage(int port)
-{
-	return 0;
-}
-
-static int get_vbus_voltage(int port, enum usb_power_roles current_role)
-{
-	int voltage_mv;
-
-	/*
-	 * If we are sourcing power or sinking but not charging, then VBUS must
-	 * be 5V. If we are charging, then read VBUS ADC.
-	 */
-	if (current_role == USB_PD_PORT_POWER_SINK_NOT_CHARGING) {
-		voltage_mv = 5000;
-	} else {
-#if defined(CONFIG_USB_PD_VBUS_MEASURE_CHARGER)
-		/*
-		 * Try to get VBUS from the charger. If that fails, default to 0
-		 * mV.
-		 */
-		if (charger_get_vbus_voltage(port, &voltage_mv))
-			voltage_mv = 0;
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_TCPC)
-		voltage_mv = tcpc_get_vbus_voltage(port);
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT)
-		voltage_mv = adc_read_channel(board_get_vbus_adc(port));
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT)
-		/* No VBUS ADC channel - voltage is unknown */
-		voltage_mv = 0;
-#elif defined(CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD)
-		voltage_mv = board_get_vbus_voltage(port);
-#else
-		/* There is a single ADC that measures joint Vbus */
-		voltage_mv = adc_read_channel(ADC_VBUS);
-#endif
-	}
-	return voltage_mv;
-}
-
-int charge_manager_get_vbus_voltage(int port)
-{
-	return get_vbus_voltage(port, get_current_power_role(port,
-				get_current_supplier(port)));
-}
-
-/**
- * Fills passed power_info structure with current info about the passed port.
- *
- * @param port	Charge port.
- * @param r	USB PD power info to be updated.
- */
-static void charge_manager_fill_power_info(int port,
-	struct ec_response_usb_pd_power_info *r)
-{
-	enum charge_supplier sup = get_current_supplier(port);
-
-	/* Fill in power role */
-	r->role = get_current_power_role(port, sup);
-
-	/* Is port partner dual-role capable */
-	r->dualrole = (dualrole_capability[port] == CAP_DUALROLE);
-
-	if (sup == CHARGE_SUPPLIER_NONE ||
-	    r->role == USB_PD_PORT_POWER_SOURCE) {
-		if (is_pd_port(port)) {
-			r->type = USB_CHG_TYPE_NONE;
-			r->meas.voltage_max = 0;
-			r->meas.voltage_now =
-				r->role == USB_PD_PORT_POWER_SOURCE ? 5000 : 0;
-			/* TCPMv2 tracks source-out current in the DPM */
-			if (IS_ENABLED(CONFIG_USB_PD_TCPMV2))
-				r->meas.current_max =
-					dpm_get_source_current(port);
-			else
-				r->meas.current_max =
-					charge_manager_get_source_current(port);
-			r->max_power = 0;
-		} else {
-			r->type = USB_CHG_TYPE_NONE;
-			board_fill_source_power_info(port, r);
-		}
-	} else {
-		int use_ramp_current;
-		switch (sup) {
-		case CHARGE_SUPPLIER_PD:
-			r->type = USB_CHG_TYPE_PD;
-			break;
-		case CHARGE_SUPPLIER_TYPEC:
-		case CHARGE_SUPPLIER_TYPEC_DTS:
-			r->type = USB_CHG_TYPE_C;
-			break;
-#ifdef CHARGE_MANAGER_BC12
-		case CHARGE_SUPPLIER_PROPRIETARY:
-			r->type = USB_CHG_TYPE_PROPRIETARY;
-			break;
-		case CHARGE_SUPPLIER_BC12_DCP:
-			r->type = USB_CHG_TYPE_BC12_DCP;
-			break;
-		case CHARGE_SUPPLIER_BC12_CDP:
-			r->type = USB_CHG_TYPE_BC12_CDP;
-			break;
-		case CHARGE_SUPPLIER_BC12_SDP:
-			r->type = USB_CHG_TYPE_BC12_SDP;
-			break;
-		case CHARGE_SUPPLIER_VBUS:
-			r->type = USB_CHG_TYPE_VBUS;
-			break;
-#endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-		/*
-		 * Todo:need kernel add wpc device node in power_supply
-		 * before that use USB_CHG_TYPE_PROPRIETARY to present WPC.
-		 */
-		case CHARGE_SUPPLIER_WPC_BPP:
-		case CHARGE_SUPPLIER_WPC_EPP:
-		case CHARGE_SUPPLIER_WPC_GPP:
-			r->type = USB_CHG_TYPE_PROPRIETARY;
-			break;
-#endif
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-		case CHARGE_SUPPLIER_DEDICATED:
-			r->type = USB_CHG_TYPE_DEDICATED;
-			break;
-#endif
-		default:
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			r->type = USB_CHG_TYPE_VBUS;
-#else
-			r->type = USB_CHG_TYPE_OTHER;
-#endif
-		}
-		r->meas.voltage_max = available_charge[sup][port].voltage;
-
-		/*
-		 * Report unknown charger CHARGE_DETECT_DELAY after supplier
-		 * change since PD negotiation may take time.
-		 *
-		 * Do not debounce on batteryless systems because
-		 * USB_CHG_TYPE_UNKNOWN implies the system is still on battery
-		 * while some kind of negotiation happens, but by the time the
-		 * host might request this in a battery-free configuration we
-		 * must be stable (if not, the system is either up or about to
-		 * lose power again).
-		 */
-#ifdef CONFIG_BATTERY
-		if (get_time().val < registration_time[port].val +
-				     CHARGE_DETECT_DELAY)
-			r->type = USB_CHG_TYPE_UNKNOWN;
-#endif
-
-#if defined(HAS_TASK_CHG_RAMP) || defined(CONFIG_CHARGE_RAMP_HW)
-		/* Read ramped current if active charging port */
-		use_ramp_current =
-			(charge_port == port) && chg_ramp_allowed(port, sup);
-#else
-		use_ramp_current = 0;
-#endif
-		if (use_ramp_current) {
-			/* Current limit is output of ramp module */
-			r->meas.current_lim = chg_ramp_get_current_limit();
-
-			/*
-			 * If ramp is allowed, then the max current depends
-			 * on if ramp is stable. If ramp is stable, then
-			 * max current is same as input current limit. If
-			 * ramp is not stable, then we report the maximum
-			 * current we could ramp up to for this supplier.
-			 * If ramp is not allowed, max current is just the
-			 * available charge current.
-			 */
-			r->meas.current_max = chg_ramp_is_stable() ?
-				r->meas.current_lim : chg_ramp_max(port, sup,
-					available_charge[sup][port].current);
-
-			r->max_power =
-				r->meas.current_max * r->meas.voltage_max;
-		} else {
-			r->meas.current_max = r->meas.current_lim =
-				available_charge[sup][port].current;
-			r->max_power = POWER(available_charge[sup][port]);
-		}
-
-		r->meas.voltage_now = get_vbus_voltage(port, r->role);
-	}
-}
-#endif /* TEST_BUILD */
-
-#ifdef CONFIG_USB_PD_LOGGING
-/**
- * Saves a power state log entry with the current info about the passed port.
- */
-void charge_manager_save_log(int port)
-{
-	uint16_t flags = 0;
-	struct ec_response_usb_pd_power_info pinfo;
-
-	if (!is_pd_port(port))
-		return;
-
-	save_log[port] = 0;
-	charge_manager_fill_power_info(port, &pinfo);
-
-	/* Flags are stored in the data field */
-	if (port == override_port)
-		flags |= CHARGE_FLAGS_OVERRIDE;
-	if (port == delayed_override_port)
-		flags |= CHARGE_FLAGS_DELAYED_OVERRIDE;
-	flags |= pinfo.role | (pinfo.type << CHARGE_FLAGS_TYPE_SHIFT) |
-		 (pinfo.dualrole ? CHARGE_FLAGS_DUAL_ROLE : 0);
-
-	pd_log_event(PD_EVENT_MCU_CHARGE,
-		     PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)),
-		     flags, &pinfo.meas);
-}
-#endif /* CONFIG_USB_PD_LOGGING */
-
-/**
- * Attempt to switch to power source on port if applicable.
- *
- * @param port	USB-C port to be swapped.
- */
-static void charge_manager_switch_to_source(int port)
-{
-	if (!is_pd_port(port))
-		return;
-
-	/* If connected to dual-role device, then ask for a swap */
-	if (dualrole_capability[port] == CAP_DUALROLE && is_sink(port))
-		pd_request_power_swap(port);
-}
-
-/**
- * Return the computed charge ceiling for a port, which represents the
- * minimum ceiling among all valid requestors.
- *
- * @param port	Charge port.
- * @return	Charge ceiling (mA) or CHARGE_CEIL_NONE.
- */
-static int charge_manager_get_ceil(int port)
-{
-	int ceil = CHARGE_CEIL_NONE;
-	int val, i;
-
-	if (!is_valid_port(port))
-		return ceil;
-
-	for (i = 0; i < CEIL_REQUESTOR_COUNT; ++i) {
-		val = charge_ceil[port][i];
-		if (val != CHARGE_CEIL_NONE &&
-		    (ceil == CHARGE_CEIL_NONE || val < ceil))
-			ceil = val;
-	}
-
-	return ceil;
-}
-
-/**
- * Select the 'best' charge port, as defined by the supplier heirarchy and the
- * ability of the port to provide power.
- *
- * @param new_port	Pointer to the best charge port by definition.
- * @param new_supplier	Pointer to the best charge supplier by definition.
- */
-static void charge_manager_get_best_charge_port(int *new_port,
-						int *new_supplier)
-{
-	int supplier = CHARGE_SUPPLIER_NONE;
-	int port = CHARGE_PORT_NONE;
-	int best_port_power = -1, candidate_port_power;
-	int i, j;
-
-	/* Skip port selection on OVERRIDE_DONT_CHARGE. */
-	if (override_port != OVERRIDE_DONT_CHARGE) {
-
-		/*
-		 * Charge supplier selection logic:
-		 * 1. Prefer DPS charge port.
-		 * 2. Prefer higher priority supply.
-		 * 3. Prefer higher power over lower in case priority is tied.
-		 * 4. Prefer current charge port over new port in case (1)
-		 *    and (2) are tied.
-		 * available_charge can be changed at any time by other tasks,
-		 * so make no assumptions about its consistency.
-		 */
-		for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i)
-			for (j = 0; j < CHARGE_PORT_COUNT; ++j) {
-				/* Skip this port if it is not valid. */
-				if (!is_valid_port(j))
-					continue;
-
-				/*
-				 * Skip this supplier if there is no
-				 * available charge.
-				 */
-				if (available_charge[i][j].current == 0 ||
-				    available_charge[i][j].voltage == 0)
-					continue;
-
-				/*
-				 * Don't select this port if we have a
-				 * charge on another override port.
-				 */
-				if (override_port != OVERRIDE_OFF &&
-				    override_port == port &&
-				    override_port != j)
-					continue;
-
-#ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-				/*
-				 * Don't charge from a dual-role port unless
-				 * it is our override port.
-				 */
-				if (dualrole_capability[j] != CAP_DEDICATED &&
-				    override_port != j &&
-				    !charge_manager_spoof_dualrole_capability())
-					continue;
-#endif
-
-				candidate_port_power =
-					POWER(available_charge[i][j]);
-
-				/* Select DPS port if provided. */
-				if (IS_ENABLED(CONFIG_USB_PD_DPS) &&
-				    override_port == OVERRIDE_OFF &&
-				    i == CHARGE_SUPPLIER_PD &&
-				    j == dps_get_charge_port()) {
-					supplier = i;
-					port = j;
-					break;
-				/* Select if no supplier chosen yet. */
-				} else if (supplier == CHARGE_SUPPLIER_NONE ||
-				/* ..or if supplier priority is higher. */
-				    supplier_priority[i] <
-				    supplier_priority[supplier] ||
-				/* ..or if this is our override port. */
-				   (j == override_port &&
-				    port != override_port) ||
-				/* ..or if priority is tied and.. */
-				   (supplier_priority[i] ==
-				    supplier_priority[supplier] &&
-				/* candidate port can supply more power or.. */
-				   (candidate_port_power > best_port_power ||
-				/*
-				 * candidate port is the active port and can
-				 * supply the same amount of power.
-				 */
-				   (candidate_port_power == best_port_power &&
-				    charge_port == j)))) {
-					supplier = i;
-					port = j;
-					best_port_power = candidate_port_power;
-				}
-			}
-
-	}
-
-#ifdef CONFIG_BATTERY
-	/*
-	 * if no battery present then retain same charge port
-	 * and charge supplier to avoid the port switching
-	 */
-	if (charge_port != CHARGE_SUPPLIER_NONE &&
-	    charge_port != port &&
-	    (battery_is_present() == BP_NO ||
-	     (battery_is_present() == BP_YES &&
-	      battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL))) {
-		port = charge_port;
-		supplier = charge_supplier;
-	}
-#endif
-
-	*new_port = port;
-	*new_supplier = supplier;
-}
-
-/**
- * Charge manager refresh -- responsible for selecting the active charge port
- * and charge power. Called as a deferred task.
- */
-static void charge_manager_refresh(void)
-{
-	/* Always initialize charge port on first pass */
-	static int active_charge_port_initialized;
-	int new_supplier, new_port;
-	int new_charge_current, new_charge_current_uncapped;
-	int new_charge_voltage, i;
-	int updated_new_port = CHARGE_PORT_NONE;
-	int updated_old_port = CHARGE_PORT_NONE;
-	int ceil;
-	int power_changed = 0;
-
-	/* Hunt for an acceptable charge port */
-	while (1) {
-		charge_manager_get_best_charge_port(&new_port, &new_supplier);
-
-		if (!left_safe_mode && new_port == CHARGE_PORT_NONE)
-			return;
-
-		/*
-		 * If the port or supplier changed, make an attempt to switch to
-		 * the port. We will re-set the active port on a supplier change
-		 * to give the board-level function another chance to reject
-		 * the port, for example, if the port has become a charge
-		 * source.
-		 */
-		if (active_charge_port_initialized &&
-		     new_port == charge_port &&
-		     new_supplier == charge_supplier)
-			break;
-
-		/*
-		 * For OCPC systems, reset the OCPC state to prevent current
-		 * spikes.
-		 */
-		if (IS_ENABLED(CONFIG_OCPC)) {
-			charge_set_active_chg_chip(new_port);
-			trigger_ocpc_reset();
-		}
-
-		if (board_set_active_charge_port(new_port) == EC_SUCCESS) {
-			if (IS_ENABLED(CONFIG_EXTPOWER))
-				board_check_extpower();
-			break;
-		}
-
-		/* 'Dont charge' request must be accepted. */
-		ASSERT(new_port != CHARGE_PORT_NONE);
-
-		/*
-		 * Zero the available charge on the rejected port so that
-		 * it is no longer chosen.
-		 */
-		for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i) {
-			available_charge[i][new_port].current = 0;
-			available_charge[i][new_port].voltage = 0;
-		}
-	}
-
-	active_charge_port_initialized = 1;
-
-	/*
-	 * Clear override if it wasn't selected as the 'best' port -- it means
-	 * that no charge is available on the port, or the port was rejected.
-	 */
-	if (override_port >= 0 && override_port != new_port)
-		override_port = OVERRIDE_OFF;
-
-	if (new_supplier == CHARGE_SUPPLIER_NONE) {
-		new_charge_current = 0;
-		new_charge_current_uncapped = 0;
-		new_charge_voltage = 0;
-	} else {
-		new_charge_current_uncapped =
-			available_charge[new_supplier][new_port].current;
-#ifdef CONFIG_CHARGE_RAMP_HW
-		/*
-		 * Allow to set the maximum current value, so the hardware can
-		 * know the range of acceptable current values for its ramping.
-		 */
-		if (chg_ramp_allowed(new_port, new_supplier))
-			new_charge_current_uncapped =
-				chg_ramp_max(new_port, new_supplier,
-					     new_charge_current_uncapped);
-#endif /* CONFIG_CHARGE_RAMP_HW */
-		/* Enforce port charge ceiling. */
-		ceil = charge_manager_get_ceil(new_port);
-		if (left_safe_mode && ceil != CHARGE_CEIL_NONE)
-			new_charge_current = MIN(ceil,
-						 new_charge_current_uncapped);
-		else
-			new_charge_current = new_charge_current_uncapped;
-
-		new_charge_voltage =
-			available_charge[new_supplier][new_port].voltage;
-	}
-
-	/* Change the charge limit + charge port/supplier if modified. */
-	if (new_port != charge_port || new_charge_current != charge_current ||
-	    new_supplier != charge_supplier) {
-#ifdef HAS_TASK_CHG_RAMP
-		chg_ramp_charge_supplier_change(
-				new_port, new_supplier, new_charge_current,
-				registration_time[new_port],
-				new_charge_voltage);
-#else
-#ifdef CONFIG_CHARGE_RAMP_HW
-		/* Enable or disable charge ramp */
-		charger_set_hw_ramp(chg_ramp_allowed(new_port, new_supplier));
-#endif
-		board_set_charge_limit(new_port, new_supplier,
-					new_charge_current,
-					new_charge_current_uncapped,
-					new_charge_voltage);
-#endif /* HAS_TASK_CHG_RAMP */
-
-		power_changed = 1;
-
-		CPRINTS("CL: p%d s%d i%d v%d", new_port, new_supplier,
-			new_charge_current, new_charge_voltage);
-
-		/*
-		 * (b:192638664) We try to check AC OK again to avoid
-		 * unsuccessful detection in the initial detection.
-		 */
-		if (IS_ENABLED(CONFIG_EXTPOWER))
-			board_check_extpower();
-	}
-
-	/*
-	 * Signal new power request only if the port changed, the voltage
-	 * on the same port changed, or the actual uncapped current
-	 * on the same port changed (don't consider ceil).
-	 */
-	if (new_port != CHARGE_PORT_NONE &&
-	    (new_port != charge_port ||
-	     new_charge_current_uncapped != charge_current_uncapped ||
-	     new_charge_voltage != charge_voltage))
-		updated_new_port = new_port;
-
-	/* If charge port changed, cleanup old port */
-	if (charge_port != new_port && charge_port != CHARGE_PORT_NONE) {
-		/* Check if need power swap */
-		charge_manager_switch_to_source(charge_port);
-		/* Signal new power request on old port */
-		updated_old_port = charge_port;
-	}
-
-	/* Update globals to reflect current state. */
-	charge_current = new_charge_current;
-	charge_current_uncapped = new_charge_current_uncapped;
-	charge_voltage = new_charge_voltage;
-	charge_supplier = new_supplier;
-	charge_port = new_port;
-
-#ifdef CONFIG_USB_PD_LOGGING
-	/*
-	 * Write a log under the following conditions:
-	 *  1. A port becomes active or
-	 *  2. A port becomes inactive or
-	 *  3. The active charge port power limit changes or
-	 *  4. Any supplier change on an inactive port
-	 */
-	if (updated_new_port != CHARGE_PORT_NONE)
-		save_log[updated_new_port] = 1;
-	/* Don't log non-meaningful changes on charge port */
-	else if (charge_port != CHARGE_PORT_NONE)
-		save_log[charge_port] = 0;
-
-	if (updated_old_port != CHARGE_PORT_NONE)
-		save_log[updated_old_port] = 1;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i)
-		if (save_log[i])
-			charge_manager_save_log(i);
-#endif
-
-	/* New power requests must be set only after updating the globals. */
-	if (is_pd_port(updated_new_port)) {
-		/* Check if we can get requested voltage/current */
-		if ((IS_ENABLED(CONFIG_USB_PD_TCPMV1) &&
-		    IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ||
-		    (IS_ENABLED(CONFIG_USB_PD_TCPMV2) &&
-		    IS_ENABLED(CONFIG_USB_PE_SM))) {
-			uint32_t pdo;
-			uint32_t max_voltage;
-			uint32_t max_current;
-			uint32_t unused;
-			/*
-			 * Check if new voltage/current is different
-			 * than requested. If yes, send new power request
-			 */
-			if (pd_get_requested_voltage(updated_new_port) !=
-			    charge_voltage ||
-			    pd_get_requested_current(updated_new_port) !=
-			    charge_current_uncapped)
-				pd_set_new_power_request(updated_new_port);
-
-			/*
-			 * Check if we can get more power from this port.
-			 * If yes, send new power request
-			 */
-			pd_find_pdo_index(pd_get_src_cap_cnt(updated_new_port),
-					  pd_get_src_caps(updated_new_port),
-					  pd_get_max_voltage(), &pdo);
-			pd_extract_pdo_power(pdo, &max_current, &max_voltage,
-					     &unused);
-			if (charge_voltage != max_voltage ||
-			    charge_current_uncapped != max_current)
-				pd_set_new_power_request(updated_new_port);
-		} else {
-			/*
-			 * Functions for getting requested voltage/current
-			 * are not available. Send new power request.
-			 */
-			pd_set_new_power_request(updated_new_port);
-		}
-	}
-	if (is_pd_port(updated_old_port))
-		pd_set_new_power_request(updated_old_port);
-
-	if (power_changed)
-		/* notify host of power info change */
-		pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-DECLARE_DEFERRED(charge_manager_refresh);
-
-/**
- * Called when charge override times out waiting for power swap.
- */
-static void charge_override_timeout(void)
-{
-	delayed_override_port = OVERRIDE_OFF;
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-DECLARE_DEFERRED(charge_override_timeout);
-
-/**
- * Called CHARGE_DETECT_DELAY after the most recent charge change on a port.
- */
-static void charger_detect_debounced(void)
-{
-	/* Inform host that charger detection is debounced. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-DECLARE_DEFERRED(charger_detect_debounced);
-
-/**
- * Update charge parameters for a given port / supplier.
- *
- * @param change		Type of change.
- * @param supplier		Charge supplier to be updated.
- * @param port			Charge port to be updated.
- * @param charge		Charge port current / voltage.
- */
-static void charge_manager_make_change(enum charge_manager_change_type change,
-				       int supplier,
-				       int port,
-				       const struct charge_port_info *charge)
-{
-	int i;
-	int clear_override = 0;
-
-	if (!is_valid_port(port)) {
-		CPRINTS("%s: p%d invalid", __func__, port);
-		return;
-	}
-
-	/* Determine if this is a change which can affect charge status */
-	switch (change) {
-	case CHANGE_CHARGE:
-		/* Ignore changes where charge is identical */
-		if (available_charge[supplier][port].current ==
-		    charge->current &&
-		    available_charge[supplier][port].voltage ==
-		    charge->voltage)
-			return;
-		if (charge->current > 0 &&
-		    available_charge[supplier][port].current == 0)
-			clear_override = 1;
-#ifdef CONFIG_USB_PD_LOGGING
-		save_log[port] = 1;
-#endif
-		break;
-	case CHANGE_DUALROLE:
-		/*
-		 * Ignore all except for transition to non-dualrole,
-		 * which may occur some time after we see a charge
-		 */
-#ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-		if (dualrole_capability[port] != CAP_DEDICATED)
-#endif
-			return;
-		/* Clear override only if a charge is present on the port */
-		for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i)
-			if (available_charge[i][port].current > 0) {
-				clear_override = 1;
-				break;
-			}
-		/*
-		 * If there is no charge present on the port, the dualrole
-		 * change is meaningless to charge_manager.
-		 */
-		if (!clear_override)
-			return;
-		break;
-	}
-
-	/* Remove override when a charger is plugged */
-	if (clear_override && override_port != port
-#ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	    /* only remove override when it's a dedicated charger */
-	    && dualrole_capability[port] == CAP_DEDICATED
-#endif
-	    ) {
-		override_port = OVERRIDE_OFF;
-		if (delayed_override_port != OVERRIDE_OFF) {
-			delayed_override_port = OVERRIDE_OFF;
-			hook_call_deferred(&charge_override_timeout_data, -1);
-		}
-	}
-
-	if (change == CHANGE_CHARGE) {
-		available_charge[supplier][port].current = charge->current;
-		available_charge[supplier][port].voltage = charge->voltage;
-		registration_time[port] = get_time();
-
-		/*
-		 * After CHARGE_DETECT_DELAY, inform the host that charger
-		 * detection has been debounced. Since only one deferred
-		 * routine exists for all ports, the deferred call for a given
-		 * port may potentially be cancelled. This is mostly harmless
-		 * since cancellation implies that PD_EVENT_POWER_CHANGE was
-		 * just sent due to the power change on another port.
-		 */
-		if (charge->current > 0)
-			hook_call_deferred(&charger_detect_debounced_data,
-					   CHARGE_DETECT_DELAY);
-
-		/*
-		 * If we have a charge on our delayed override port within
-		 * the deadline, make it our override port.
-		*/
-		if (port == delayed_override_port && charge->current > 0 &&
-		    is_sink(delayed_override_port) &&
-		    get_time().val < delayed_override_deadline.val) {
-			delayed_override_port = OVERRIDE_OFF;
-			hook_call_deferred(&charge_override_timeout_data, -1);
-			charge_manager_set_override(port);
-		}
-	}
-
-	/*
-	 * Don't call charge_manager_refresh unless all ports +
-	 * suppliers have reported in. We don't want to make changes
-	 * to our charge port until we are certain we know what is
-	 * attached.
-	 */
-	if (charge_manager_is_seeded())
-		hook_call_deferred(&charge_manager_refresh_data, 0);
-}
-
-void pd_set_input_current_limit(int port, uint32_t max_ma,
-				uint32_t supply_voltage)
-{
-	struct charge_port_info charge;
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV))
-		charge_reset_stable_current();
-
-	charge.current = max_ma;
-	charge.voltage = supply_voltage;
-	charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
-}
-
-void typec_set_input_current_limit(int port, typec_current_t max_ma,
-				   uint32_t supply_voltage)
-{
-	struct charge_port_info charge;
-	int i;
-	int supplier;
-	int dts = !!(max_ma & TYPEC_CURRENT_DTS_MASK);
-	static const enum charge_supplier typec_suppliers[] = {
-		CHARGE_SUPPLIER_TYPEC,
-		CHARGE_SUPPLIER_TYPEC_DTS,
-#ifdef CHARGE_MANAGER_BC12
-		CHARGE_SUPPLIER_TYPEC_UNDER_1_5A,
-#endif /* CHARGE_MANAGER_BC12 */
-	};
-
-	charge.current = max_ma & TYPEC_CURRENT_ILIM_MASK;
-	charge.voltage = supply_voltage;
-#if !defined(HAS_TASK_CHG_RAMP) && !defined(CONFIG_CHARGE_RAMP_HW)
-	/*
-	 * DTS sources such as suzy-q may not be able to actually deliver
-	 * their advertised current, so limit it to reduce chance of OC,
-	 * if we can't ramp.
-	 */
-	if (dts)
-		charge.current = MIN(charge.current, 500);
-#endif
-
-	supplier = dts ? CHARGE_SUPPLIER_TYPEC_DTS : CHARGE_SUPPLIER_TYPEC;
-
-#ifdef CHARGE_MANAGER_BC12
-	/*
-	 * According to USB-C spec 1.3 Table 4-17 "Precedence of power source
-	 * usage", the priority should be: USB-C 3.0A, 1.5A > BC1.2 > USB-C
-	 * under 1.5A.  Choosed the corresponding supplier type, according to
-	 * charge current, to update.
-	 */
-	if (charge.current < 1500)
-		supplier = CHARGE_SUPPLIER_TYPEC_UNDER_1_5A;
-#endif /* CHARGE_MANAGER_BC12 */
-
-	charge_manager_update_charge(supplier, port, &charge);
-
-	/*
-	 * TYPEC / TYPEC-DTS / TYPEC-UNDER_1_5A should be mutually exclusive.
-	 * Zero'ing all the other suppliers.
-	 */
-	for (i = 0; i < ARRAY_SIZE(typec_suppliers); ++i)
-		if (supplier != typec_suppliers[i])
-			charge_manager_update_charge(typec_suppliers[i], port,
-						     NULL);
-}
-
-void charge_manager_update_charge(int supplier,
-				  int port,
-				  const struct charge_port_info *charge)
-{
-	struct charge_port_info zero = {0};
-	if (!charge)
-		charge = &zero;
-	charge_manager_make_change(CHANGE_CHARGE, supplier, port, charge);
-}
-
-void charge_manager_update_dualrole(int port, enum dualrole_capabilities cap)
-{
-	if (!is_pd_port(port))
-		return;
-
-	/* Ignore when capability is unchanged */
-	if (cap != dualrole_capability[port]) {
-		dualrole_capability[port] = cap;
-		charge_manager_make_change(CHANGE_DUALROLE, 0, port, NULL);
-	}
-}
-
-#ifdef CONFIG_CHARGE_MANAGER_SAFE_MODE
-void charge_manager_leave_safe_mode(void)
-{
-	if (left_safe_mode)
-		return;
-
-	CPRINTS("%s()", __func__);
-	cflush();
-	left_safe_mode = 1;
-	if (charge_manager_is_seeded())
-		hook_call_deferred(&charge_manager_refresh_data, 0);
-}
-#endif
-
-void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
-{
-	if (!is_valid_port(port))
-		return;
-
-	if (charge_ceil[port][requestor] != ceil) {
-		charge_ceil[port][requestor] = ceil;
-		if (port == charge_port && charge_manager_is_seeded())
-			hook_call_deferred(&charge_manager_refresh_data, 0);
-	}
-}
-
-void charge_manager_force_ceil(int port, int ceil)
-{
-	/*
-	 * Force our input current to ceil if we're exceeding it, without
-	 * waiting for our deferred task to run.
-	 */
-	if (left_safe_mode && port == charge_port && ceil < charge_current)
-		board_set_charge_limit(port, CHARGE_SUPPLIER_PD, ceil,
-				       charge_current_uncapped, charge_voltage);
-
-	/*
-	 * Now inform charge_manager so it stays in sync with the state of
-	 * the world.
-	 */
-	charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, ceil);
-}
-
-int charge_manager_set_override(int port)
-{
-	int retval = EC_SUCCESS;
-
-	CPRINTS("Charge Override: %d", port);
-
-	/*
-	 * If attempting to change the override port, then return
-	 * error. Since we may be in the middle of a power swap on
-	 * the original override port, it's too complicated to
-	 * guarantee that the original override port is switched back
-	 * to source.
-	 */
-	if (delayed_override_port != OVERRIDE_OFF)
-		return EC_ERROR_BUSY;
-
-	/* Set the override port if it's a sink. */
-	if (port < 0 || is_sink(port)) {
-		if (override_port != port) {
-			override_port = port;
-			if (charge_manager_is_seeded())
-				hook_call_deferred(
-					&charge_manager_refresh_data, 0);
-		}
-	}
-	/*
-	 * If the attached device is capable of being a sink, request a
-	 * power swap and set the delayed override for swap completion.
-	 */
-	else if (!is_sink(port) && dualrole_capability[port] == CAP_DUALROLE) {
-		delayed_override_deadline.val = get_time().val +
-						POWER_SWAP_TIMEOUT;
-		delayed_override_port = port;
-		hook_call_deferred(&charge_override_timeout_data,
-				   POWER_SWAP_TIMEOUT);
-		pd_request_power_swap(port);
-	/* Can't charge from requested port -- return error. */
-	} else
-		retval = EC_ERROR_INVAL;
-
-	return retval;
-}
-
-int charge_manager_get_override(void)
-{
-	return override_port;
-}
-
-int charge_manager_get_active_charge_port(void)
-{
-	return charge_port;
-}
-
-int charge_manager_get_selected_charge_port(void)
-{
-	int port, supplier;
-
-	charge_manager_get_best_charge_port(&port, &supplier);
-	return port;
-}
-
-int charge_manager_get_charger_current(void)
-{
-	return charge_current;
-}
-
-int charge_manager_get_charger_voltage(void)
-{
-	return charge_voltage;
-}
-
-enum charge_supplier charge_manager_get_supplier(void)
-{
-	return charge_supplier;
-}
-
-int charge_manager_get_power_limit_uw(void)
-{
-	int current_ma = charge_current;
-	int voltage_mv = charge_voltage;
-
-	if (current_ma == CHARGE_CURRENT_UNINITIALIZED ||
-	    voltage_mv == CHARGE_VOLTAGE_UNINITIALIZED)
-		return 0;
-	else
-		return current_ma * voltage_mv;
-}
-
-#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) && \
-	!defined(CONFIG_USB_PD_TCPMV2)
-/* Note: this functionality is a part of the TCPMv2 Device Poicy Manager */
-
-/* Bitmap of ports used as power source */
-static volatile uint32_t source_port_bitmap;
-BUILD_ASSERT(sizeof(source_port_bitmap)*8 >= CONFIG_USB_PD_PORT_MAX_COUNT);
-
-static inline int has_other_active_source(int port)
-{
-	return source_port_bitmap & ~BIT(port);
-}
-
-static inline int is_active_source(int port)
-{
-	return source_port_bitmap & BIT(port);
-}
-
-static int can_supply_max_current(int port)
-{
-#ifdef CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT
-	/*
-	 * This guarantees active 3A source continues to supply 3A.
-	 *
-	 * Since redistribution occurs sequentially, younger ports get
-	 * priority. Priority surfaces only when 3A source is released.
-	 * That is, when 3A source is released, the youngest active
-	 * port gets 3A.
-	 */
-	int p;
-	if (!is_active_source(port))
-		/* Non-active ports don't get 3A */
-		return 0;
-	for (p = 0; p < board_get_usb_pd_port_count(); p++) {
-		if (p == port)
-			continue;
-		if (source_port_rp[p] ==
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
-			return 0;
-	}
-	return 1;
-#else
-	return is_active_source(port) && !has_other_active_source(port);
-#endif /* CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT */
-}
-
-void charge_manager_source_port(int port, int enable)
-{
-	uint32_t prev_bitmap = source_port_bitmap;
-	int p, rp;
-
-	if (enable)
-		atomic_or((uint32_t *)&source_port_bitmap, 1 << port);
-	else
-		atomic_clear_bits((uint32_t *)&source_port_bitmap, 1 << port);
-
-	/* No change, exit early. */
-	if (prev_bitmap == source_port_bitmap)
-		return;
-
-	/* Set port limit according to policy */
-	for (p = 0; p < board_get_usb_pd_port_count(); p++) {
-		rp = can_supply_max_current(p) ?
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT :
-				CONFIG_USB_PD_PULLUP;
-		source_port_rp[p] = rp;
-
-#ifdef CONFIG_USB_PD_LOGGING
-		if (is_connected(p) && !is_sink(p))
-			charge_manager_save_log(p);
-#endif
-
-		typec_set_source_current_limit(p, rp);
-		if (IS_ENABLED(CONFIG_USB_PD_TCPMV2))
-			typec_select_src_current_limit_rp(p, rp);
-		else
-			tcpm_select_rp_value(p, rp);
-		pd_update_contract(p);
-	}
-}
-
-int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	if (can_supply_max_current(port)) {
-		*src_pdo = pd_src_pdo_max;
-		return pd_src_pdo_max_cnt;
-	}
-
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnt;
-}
-#endif /* CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT && !CONFIG_USB_PD_TCPMV2 */
-
-#ifndef TEST_BUILD
-static enum ec_status hc_pd_power_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_power_info *p = args->params;
-	struct ec_response_usb_pd_power_info *r = args->response;
-	int port = p->port;
-
-	/* If host is asking for the charging port, set port appropriately */
-	if (port == PD_POWER_CHARGING_PORT)
-		port = charge_port;
-
-	/*
-	 * Not checking for invalid port here, because it might break existing
-	 * contract with ectool users. The invalid ports will have the response
-	 * voltage, current and power parameters set to 0.
-	 */
-	if (port >= CHARGE_PORT_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	charge_manager_fill_power_info(port, r);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO,
-		     hc_pd_power_info,
-		     EC_VER_MASK(0));
-#endif /* TEST_BUILD */
-
-static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args)
-{
-	struct ec_response_charge_port_count *resp = args->response;
-
-	args->response_size = sizeof(*resp);
-	resp->port_count = CHARGE_PORT_COUNT;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT,
-		     hc_charge_port_count,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_charge_port_override(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_charge_port_override *p = args->params;
-	const int16_t override_port = p->override_port;
-
-	if (override_port < OVERRIDE_DONT_CHARGE ||
-	    override_port >= CHARGE_PORT_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	return charge_manager_set_override(override_port) == EC_SUCCESS ?
-		EC_RES_SUCCESS : EC_RES_ERROR;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE,
-		     hc_charge_port_override,
-		     EC_VER_MASK(0));
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-static enum ec_status hc_override_dedicated_charger_limit(
-		struct host_cmd_handler_args *args)
-{
-	const struct ec_params_dedicated_charger_limit *p = args->params;
-	struct charge_port_info ci = {
-		.current = p->current_lim,
-		.voltage = p->voltage_lim,
-	};
-
-	/*
-	 * Allow a change only if the dedicated charge port is used. Host needs
-	 * to apply a change every time a dedicated charger is plugged.
-	 */
-	if (charge_port != DEDICATED_CHARGE_PORT)
-		return EC_RES_UNAVAILABLE;
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, &ci);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT,
-		     hc_override_dedicated_charger_limit,
-		     EC_VER_MASK(0));
-#endif
-
-static int command_charge_port_override(int argc, char **argv)
-{
-	int port = OVERRIDE_OFF;
-	int ret = EC_SUCCESS;
-	char *e;
-
-	if (argc >= 2) {
-		port = strtoi(argv[1], &e, 0);
-		if (*e || port < OVERRIDE_DONT_CHARGE ||
-		    port >= CHARGE_PORT_COUNT)
-			return EC_ERROR_PARAM1;
-		ret = charge_manager_set_override(port);
-	}
-
-	ccprintf("Override: %d\n", (argc >= 2 && ret == EC_SUCCESS) ?
-					port : override_port);
-	return ret;
-}
-DECLARE_CONSOLE_COMMAND(chgoverride, command_charge_port_override,
-	"[port | -1 | -2]",
-	"Force charging from a given port (-1 = off, -2 = disable charging)");
-
-#ifdef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-static void charge_manager_set_external_power_limit(int current_lim,
-						    int voltage_lim)
-{
-	int port;
-
-	if (current_lim == EC_POWER_LIMIT_NONE)
-		current_lim = CHARGE_CEIL_NONE;
-	if (voltage_lim == EC_POWER_LIMIT_NONE)
-		voltage_lim = PD_MAX_VOLTAGE_MV;
-
-	for (port = 0; port < board_get_usb_pd_port_count(); ++port) {
-		charge_manager_set_ceil(port, CEIL_REQUESTOR_HOST, current_lim);
-		pd_set_external_voltage_limit(port, voltage_lim);
-	}
-}
-
-/*
- * On transition out of S0, disable all external power limits, in case AP
- * failed to clear them.
- */
-static void charge_manager_external_power_limit_off(void)
-{
-	charge_manager_set_external_power_limit(EC_POWER_LIMIT_NONE,
-						EC_POWER_LIMIT_NONE);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, charge_manager_external_power_limit_off,
-	     HOOK_PRIO_DEFAULT);
-
-static enum ec_status
-hc_external_power_limit(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_external_power_limit_v1 *p = args->params;
-
-	charge_manager_set_external_power_limit(p->current_lim,
-						p->voltage_lim);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT,
-		     hc_external_power_limit,
-		     EC_VER_MASK(1));
-
-static int command_external_power_limit(int argc, char **argv)
-{
-	int max_current;
-	int max_voltage;
-	char *e;
-
-	if (argc >= 2) {
-		max_current = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	} else
-		max_current = EC_POWER_LIMIT_NONE;
-
-	if (argc >= 3) {
-		max_voltage = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	} else
-		max_voltage = EC_POWER_LIMIT_NONE;
-
-	charge_manager_set_external_power_limit(max_current, max_voltage);
-	ccprintf("max req: %dmA %dmV\n", max_current, max_voltage);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chglim, command_external_power_limit,
-	"[max_current (mA)] [max_voltage (mV)]",
-	"Set max charger current / voltage");
-#endif /* CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT */
-
-#ifdef CONFIG_CMD_CHARGE_SUPPLIER_INFO
-static int charge_supplier_info(int argc, char **argv)
-{
-	ccprintf("port=%d, type=%d, cur=%dmA, vtg=%dmV, lsm=%d\n",
-			charge_manager_get_active_charge_port(),
-			charge_supplier,
-			charge_current,
-			charge_voltage,
-			left_safe_mode);
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info,
-			NULL, "print chg supplier info");
-#endif
-
-__overridable
-int board_charge_port_is_sink(int port)
-{
-	return 1;
-}
-
-__overridable
-int board_charge_port_is_connected(int port)
-{
-	return 1;
-}
-
-__overridable
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
-{
-	r->meas.voltage_now = 0;
-	r->meas.voltage_max = 0;
-	r->meas.current_max = 0;
-	r->meas.current_lim = 0;
-	r->max_power = 0;
-}
diff --git a/common/charge_ramp.c b/common/charge_ramp.c
deleted file mode 100644
index a408771f40..0000000000
--- a/common/charge_ramp.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Charge input current limit ramp module for Chrome EC */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "system.h"
-#include "usb_charge.h"
-#include "util.h"
-
-test_mockable int chg_ramp_allowed(int port, int supplier)
-{
-	/* Don't allow ramping in RO when write protected. */
-	if (!system_is_in_rw() && system_is_locked())
-		return 0;
-
-	switch (supplier) {
-	/* Use ramping for USB-C DTS suppliers (debug accessory eg suzy-q). */
-	case CHARGE_SUPPLIER_TYPEC_DTS:
-		return 1;
-	/*
-	 * Use HW ramping for USB-C chargers. Don't use SW ramping since the
-	 * slow ramp causes issues with auto power on (b/169634979).
-	 */
-	case CHARGE_SUPPLIER_PD:
-	case CHARGE_SUPPLIER_TYPEC:
-		return IS_ENABLED(CONFIG_CHARGE_RAMP_HW);
-	/* default: fall through */
-	}
-
-	/* Otherwise ask the BC1.2 detect module */
-	return usb_charger_ramp_allowed(port, supplier);
-}
-
-test_mockable int chg_ramp_max(int port, int supplier, int sup_curr)
-{
-	switch (supplier) {
-	case CHARGE_SUPPLIER_PD:
-	case CHARGE_SUPPLIER_TYPEC:
-	case CHARGE_SUPPLIER_TYPEC_DTS:
-		/*
-		 * We should not ramp DTS beyond what they advertise, otherwise
-		 * we may brownout the systems they are connected to.
-		 */
-		return sup_curr;
-	/* default: fall through */
-	}
-
-	/* Otherwise ask the BC1.2 detect module */
-	return usb_charger_ramp_max(port, supplier, sup_curr);
-}
diff --git a/common/charge_ramp_sw.c b/common/charge_ramp_sw.c
deleted file mode 100644
index bfd6db057b..0000000000
--- a/common/charge_ramp_sw.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Charge input current limit ramp module for Chrome EC */
-
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* Number of times to ramp current searching for limit before stable charging */
-#define RAMP_COUNT          3
-
-/* Maximum allowable time charger can be unplugged to be considered an OCP */
-#define OC_RECOVER_MAX_TIME (SECOND)
-
-/* Delay for running state machine when board is not consuming full current */
-#define CURRENT_DRAW_DELAY  (5*SECOND)
-
-/* Current ramp increment */
-#define RAMP_CURR_INCR_MA   64
-#define RAMP_CURR_DELAY     (500*MSEC)
-#define RAMP_CURR_START_MA  500
-
-/* How much to backoff the input current limit when limit has been found */
-#define RAMP_ICL_BACKOFF    (2*RAMP_CURR_INCR_MA)
-
-/* Interval at which VBUS voltage is monitored in stable state */
-#define STABLE_VBUS_MONITOR_INTERVAL (SECOND)
-
-/* Time to delay for stablizing the charging current */
-#define STABLIZE_DELAY (5*SECOND)
-
-enum chg_ramp_state {
-	CHG_RAMP_DISCONNECTED,
-	CHG_RAMP_CHARGE_DETECT_DELAY,
-	CHG_RAMP_OVERCURRENT_DETECT,
-	CHG_RAMP_RAMP,
-	CHG_RAMP_STABILIZE,
-	CHG_RAMP_STABLE,
-};
-static enum chg_ramp_state ramp_st;
-
-struct oc_info {
-	timestamp_t ts;
-	int oc_detected;
-	int sup;
-	int icl;
-};
-
-/* OCP info for each over-current */
-static struct oc_info oc_info[CONFIG_USB_PD_PORT_MAX_COUNT][RAMP_COUNT];
-static int oc_info_idx[CONFIG_USB_PD_PORT_MAX_COUNT];
-#define ACTIVE_OC_INFO (oc_info[active_port][oc_info_idx[active_port]])
-
-/* Active charging information */
-static int active_port = CHARGE_PORT_NONE;
-static int active_sup;
-static int active_icl;
-static int active_vtg;
-static timestamp_t reg_time;
-
-static int stablize_port;
-static int stablize_sup;
-
-/* Maximum/minimum input current limit for active charger */
-static int max_icl;
-static int min_icl;
-
-void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-				timestamp_t registration_time, int voltage)
-{
-	/*
-	 * If the last active port was a valid port and the port
-	 * has changed, then this may have been an over-current.
-	 */
-	if (active_port != CHARGE_PORT_NONE &&
-	    port != active_port) {
-		if (oc_info_idx[active_port] == RAMP_COUNT - 1)
-			oc_info_idx[active_port] = 0;
-		else
-			oc_info_idx[active_port]++;
-		ACTIVE_OC_INFO.ts = get_time();
-		ACTIVE_OC_INFO.sup = active_sup;
-		ACTIVE_OC_INFO.icl = active_icl;
-	}
-
-	/* Set new active port, set ramp state, and wake ramp task */
-	active_port = port;
-	active_sup = supplier;
-	active_vtg = voltage;
-
-	/* Set min and max input current limit based on if ramp is allowed */
-	if (chg_ramp_allowed(active_port, active_sup)) {
-		min_icl = RAMP_CURR_START_MA;
-		max_icl = chg_ramp_max(active_port, active_sup, current);
-	} else {
-		min_icl = max_icl = current;
-	}
-
-	reg_time = registration_time;
-	if (ramp_st != CHG_RAMP_STABILIZE) {
-		ramp_st = (active_port == CHARGE_PORT_NONE) ?
-			  CHG_RAMP_DISCONNECTED : CHG_RAMP_CHARGE_DETECT_DELAY;
-		CPRINTS("Ramp reset: st%d", ramp_st);
-		task_wake(TASK_ID_CHG_RAMP);
-	}
-}
-
-int chg_ramp_get_current_limit(void)
-{
-	/*
-	 * If we are ramping or stable, then use the active input
-	 * current limit. Otherwise, use the minimum input current
-	 * limit.
-	 */
-	switch (ramp_st) {
-	case CHG_RAMP_RAMP:
-	case CHG_RAMP_STABILIZE:
-	case CHG_RAMP_STABLE:
-		return active_icl;
-	default:
-		return min_icl;
-	}
-}
-
-int chg_ramp_is_detected(void)
-{
-	/* Charger detected (charge detect delay has passed) */
-	return ramp_st > CHG_RAMP_CHARGE_DETECT_DELAY;
-}
-
-int chg_ramp_is_stable(void)
-{
-	return ramp_st == CHG_RAMP_STABLE;
-}
-
-void chg_ramp_task(void *u)
-{
-	int task_wait_time = -1;
-	int i, lim;
-	uint64_t detect_end_time_us = 0, time_us;
-	int last_active_port = CHARGE_PORT_NONE;
-
-	enum chg_ramp_state ramp_st_prev = CHG_RAMP_DISCONNECTED,
-				   ramp_st_new = CHG_RAMP_DISCONNECTED;
-	int active_icl_new;
-
-	/* Clear last OCP supplier to guarantee we ramp on first connect */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		oc_info[i][0].sup = CHARGE_SUPPLIER_NONE;
-
-	/*
-	 * Sleep until chg_ramp_charge_supplier_change is called to avoid
-	 * setting input current limit to zero. chg_ramp_charge_supplier_change
-	 * won't be called until charge_manager is ready to call
-	 * board_set_charge_limit by itself (if there is no chg_ramp_task).
-	 */
-	if (!IS_ENABLED(TEST_BUILD))
-		task_wait_event(-1);
-
-	while (1) {
-		ramp_st_new = ramp_st;
-		active_icl_new = active_icl;
-		switch (ramp_st) {
-		case CHG_RAMP_DISCONNECTED:
-			/* Do nothing */
-			task_wait_time = -1;
-			break;
-		case CHG_RAMP_CHARGE_DETECT_DELAY:
-			/* Delay for charge_manager to determine supplier */
-			/*
-			 * On entry to state, or if port changes, check
-			 * timestamps to determine if this was likely an
-			 * OC event (check if we lost VBUS and it came back
-			 * within OC_RECOVER_MAX_TIME).
-			 */
-			if (ramp_st_prev != ramp_st ||
-			    active_port != last_active_port) {
-				last_active_port = active_port;
-				if (reg_time.val <
-				    ACTIVE_OC_INFO.ts.val +
-				    OC_RECOVER_MAX_TIME) {
-					ACTIVE_OC_INFO.oc_detected = 1;
-				} else {
-					for (i = 0; i < RAMP_COUNT; ++i)
-						oc_info[active_port][i].
-							oc_detected = 0;
-				}
-				detect_end_time_us = get_time().val +
-						     CHARGE_DETECT_DELAY;
-				task_wait_time = CHARGE_DETECT_DELAY;
-				break;
-			}
-
-			/* If detect delay has not passed, set wait time */
-			time_us = get_time().val;
-			if (time_us < detect_end_time_us) {
-				task_wait_time = detect_end_time_us - time_us;
-				break;
-			}
-
-			/* Detect delay is over, fall through to next state */
-			ramp_st_new = CHG_RAMP_OVERCURRENT_DETECT;
-			/* notify host of power info change */
-			pd_send_host_event(PD_EVENT_POWER_CHANGE);
-		case CHG_RAMP_OVERCURRENT_DETECT:
-			/* Check if we should ramp or go straight to stable */
-			task_wait_time = SECOND;
-
-			/* Skip ramp for specific suppliers */
-			if (!chg_ramp_allowed(active_port, active_sup)) {
-				active_icl_new = min_icl;
-				ramp_st_new = CHG_RAMP_STABLE;
-				break;
-			}
-
-			/*
-			 * If we are not drawing full charge, then don't ramp,
-			 * just wait in this state, until we are.
-			 */
-			if (!charge_is_consuming_full_input_current()) {
-				task_wait_time = CURRENT_DRAW_DELAY;
-				break;
-			}
-
-			/*
-			 * Compare recent OCP events, if all info matches,
-			 * then we don't need to ramp anymore.
-			 */
-			for (i = 0; i < RAMP_COUNT; i++) {
-				if (oc_info[active_port][i].sup != active_sup ||
-				    !oc_info[active_port][i].oc_detected)
-					break;
-			}
-
-			if (i == RAMP_COUNT) {
-				/* Found OC threshold! */
-				active_icl_new = ACTIVE_OC_INFO.icl -
-						 RAMP_ICL_BACKOFF;
-				ramp_st_new = CHG_RAMP_STABLE;
-			} else {
-				/*
-				 * Need to ramp to find OC threshold, start
-				 * at the minimum input current limit.
-				 */
-				active_icl_new = min_icl;
-				ramp_st_new = CHG_RAMP_RAMP;
-			}
-			break;
-		case CHG_RAMP_RAMP:
-			/* Keep ramping until we find the limit */
-			task_wait_time = RAMP_CURR_DELAY;
-
-			/* Pause ramping if we are not drawing full current */
-			if (!charge_is_consuming_full_input_current()) {
-				task_wait_time = CURRENT_DRAW_DELAY;
-				break;
-			}
-
-			/* If VBUS is sagging a lot, then stop ramping */
-			if (board_is_vbus_too_low(active_port,
-						  CHG_RAMP_VBUS_RAMPING)) {
-				CPRINTS("VBUS low");
-				active_icl_new = MAX(min_icl, active_icl -
-							      RAMP_ICL_BACKOFF);
-				ramp_st_new = CHG_RAMP_STABILIZE;
-				task_wait_time = STABLIZE_DELAY;
-				stablize_port = active_port;
-				stablize_sup = active_sup;
-				break;
-			}
-
-			/* Ramp the current limit if we haven't reached max */
-			if (active_icl == max_icl)
-				ramp_st_new = CHG_RAMP_STABLE;
-			else if (active_icl + RAMP_CURR_INCR_MA > max_icl)
-				active_icl_new = max_icl;
-			else
-				active_icl_new = active_icl + RAMP_CURR_INCR_MA;
-			break;
-		case CHG_RAMP_STABILIZE:
-			/* Wait for current to stabilize after ramp is done */
-			/* Use default delay for exiting this state */
-			task_wait_time = SECOND;
-			if (active_port == stablize_port &&
-			    active_sup == stablize_sup) {
-				ramp_st_new = CHG_RAMP_STABLE;
-				break;
-			}
-
-			ramp_st_new = active_port == CHARGE_PORT_NONE ?
-				      CHG_RAMP_DISCONNECTED :
-				      CHG_RAMP_CHARGE_DETECT_DELAY;
-			break;
-		case CHG_RAMP_STABLE:
-			/* Maintain input current limit */
-			/* On entry log charging stats */
-			if (ramp_st_prev != ramp_st) {
-#ifdef CONFIG_USB_PD_LOGGING
-				charge_manager_save_log(active_port);
-#endif
-				/* notify host of power info change */
-				pd_send_host_event(PD_EVENT_POWER_CHANGE);
-			}
-
-			/* Keep an eye on VBUS and restart ramping if it dips */
-			if (chg_ramp_allowed(active_port, active_sup) &&
-			    board_is_vbus_too_low(active_port,
-						  CHG_RAMP_VBUS_STABLE)) {
-				CPRINTS("VBUS low; Re-ramp");
-				max_icl = MAX(min_icl,
-						max_icl - RAMP_ICL_BACKOFF);
-				active_icl_new = min_icl;
-				ramp_st_new = CHG_RAMP_RAMP;
-			}
-			task_wait_time = STABLE_VBUS_MONITOR_INTERVAL;
-			break;
-		}
-
-		ramp_st_prev = ramp_st;
-		ramp_st = ramp_st_new;
-		active_icl = active_icl_new;
-
-		/* Skip setting limit if status is stable twice in a row */
-		if (ramp_st_prev != CHG_RAMP_STABLE ||
-				ramp_st != CHG_RAMP_STABLE) {
-			CPRINTS("Ramp p%d st%d %dmA %dmA",
-				active_port, ramp_st, min_icl, active_icl);
-			/* Set the input current limit */
-			lim = chg_ramp_get_current_limit();
-			board_set_charge_limit(active_port, active_sup, lim,
-					       lim, active_vtg);
-		}
-
-		if (ramp_st == CHG_RAMP_STABILIZE)
-			/*
-			 * When in stabilize state, supplier/port may change
-			 * and we don't want to wake up task until we have
-			 * slept this amount of time.
-			 */
-			usleep(task_wait_time);
-		else
-			task_wait_event(task_wait_time);
-	}
-}
-
-#ifdef CONFIG_CMD_CHGRAMP
-static int command_chgramp(int argc, char **argv)
-{
-	int i;
-	int port;
-
-	ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n",
-		 ramp_st, min_icl, active_icl);
-
-	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		ccprintf("Port %d:\n", port);
-		ccprintf("  OC idx:%d\n", oc_info_idx[port]);
-		for (i = 0; i < RAMP_COUNT; i++) {
-			ccprintf("  OC %d: s%d oc_det%d icl%d\n", i,
-				 oc_info[port][i].sup,
-				 oc_info[port][i].oc_detected,
-				 oc_info[port][i].icl);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp,
-	"",
-	"Dump charge ramp state info");
-#endif
diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c
deleted file mode 100644
index 110d63c7bf..0000000000
--- a/common/charge_state_v2.c
+++ /dev/null
@@ -1,3108 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery charging task and state machine.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charger_profile_override.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "ec_ec_comm_client.h"
-#include "ec_ec_comm_server.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "power.h"
-#include "printf.h"
-#include "system.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-/* Extra debugging prints when allocating power between lid and base. */
-#undef CHARGE_ALLOCATE_EXTRA_DEBUG
-
-#define CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US \
-	(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT * SECOND)
-#define PRECHARGE_TIMEOUT_US (PRECHARGE_TIMEOUT * SECOND)
-#define LFCC_EVENT_THRESH 5 /* Full-capacity change reqd for host event */
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-#ifndef CONFIG_HOSTCMD_EVENTS
-#error "CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT needs CONFIG_HOSTCMD_EVENTS"
-#endif /* CONFIG_HOSTCMD_EVENTS */
-#define BAT_OCP_TIMEOUT_US (60 * SECOND)
-/* BAT_OCP_HYSTERESIS_PCT can be optionally overridden in board.h. */
-#ifndef BAT_OCP_HYSTERESIS_PCT
-#define BAT_OCP_HYSTERESIS_PCT 10
-#endif /* BAT_OCP_HYSTERESIS_PCT */
-#define BAT_OCP_HYSTERESIS \
-	(BAT_MAX_DISCHG_CURRENT * BAT_OCP_HYSTERESIS_PCT / 100) /* mA */
-#endif /* CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT */
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-#ifndef CONFIG_HOSTCMD_EVENTS
-#error "CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE needs CONFIG_HOSTCMD_EVENTS"
-#endif /* CONFIG_HOSTCMD_EVENTS */
-#define BAT_UVP_TIMEOUT_US (60 * SECOND)
-/* BAT_UVP_HYSTERESIS_PCT can be optionally overridden in board.h. */
-#ifndef BAT_UVP_HYSTERESIS_PCT
-#define BAT_UVP_HYSTERESIS_PCT 3
-#endif /* BAT_UVP_HYSTERESIS_PCT */
-#define BAT_UVP_HYSTERESIS \
-	(BAT_LOW_VOLTAGE_THRESH * BAT_UVP_HYSTERESIS_PCT / 100) /* mV */
-static timestamp_t uvp_throttle_start_time;
-#endif /* CONFIG_THROTTLE_AP_ON_BAT_OLTAGE */
-
-static int charge_request(int voltage, int current);
-
-static uint8_t battery_level_shutdown;
-
-/*
- * State for charger_task(). Here so we can reset it on a HOOK_INIT, and
- * because stack space is more limited than .bss
- */
-static const struct battery_info *batt_info;
-static struct charge_state_data curr;
-static enum charge_state_v2 prev_state;
-static int prev_ac, prev_charge, prev_full, prev_disp_charge;
-static enum battery_present prev_bp;
-static int is_full; /* battery not accepting current */
-static enum ec_charge_control_mode chg_ctl_mode;
-static int manual_voltage;  /* Manual voltage override (-1 = no override) */
-static int manual_current;  /* Manual current override (-1 = no override) */
-static unsigned int user_current_limit = -1U;
-test_export_static timestamp_t shutdown_target_time;
-static timestamp_t precharge_start_time;
-static struct sustain_soc sustain_soc;
-
-/*
- * The timestamp when the battery charging current becomes stable.
- * When a new charging status happens, charger needs several seconds to
- * stabilize the battery charging current.
- * stable_current should be evaluated when stable_ts expired.
- * stable_ts should be reset if the charger input voltage/current changes,
- * or a new battery charging voltage/request happened.
- * By evaluating stable_current, we can evaluate the battery's desired charging
- * power desired_mw. This allow us to have a better charging efficiency by
- * negotiating the most fit PDO, i.e. the PDO provides the power just enough for
- * the system and battery, or the PDO with preferred voltage.
- */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) timestamp_t stable_ts;
-/* battery charging current evaluated after stable_ts expired */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) int stable_current;
-/* battery desired power in mW. This is used to negotiate the suitable PDO */
-STATIC_IF(CONFIG_USB_PD_PREFER_MV) int desired_mw;
-STATIC_IF_NOT(CONFIG_USB_PD_PREFER_MV) struct pd_pref_config_t pd_pref_config;
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-static int base_connected;
-/* Base has responded to one of our commands already. */
-static int base_responsive;
-static int charge_base;
-static int prev_charge_base;
-static int prev_current_base;
-static int prev_allow_charge_base;
-static int prev_current_lid;
-
-/*
- * In debugging mode, with AC, input current to allocate to base. Negative
- * value disables manual mode.
- */
-static int manual_ac_current_base = -1;
-/*
- * In debugging mode, when discharging, current to transfer from lid to base
- * (negative to transfer from base to lid). Only valid when enabled is true.
- */
-static int manual_noac_enabled;
-static int manual_noac_current_base;
-#else
-static const int base_connected;
-#endif
-
-/* Is battery connected but unresponsive after precharge? */
-static int battery_seems_dead;
-
-static int battery_seems_disconnected;
-
-/*
- * Was battery removed?  Set when we see BP_NO, cleared after the battery is
- * reattached and becomes responsive.  Used to indicate an error state after
- * removal and trigger re-reading the battery static info when battery is
- * reattached and responsive.
- */
-static int battery_was_removed;
-
-static int problems_exist;
-static int debugging;
-
-
-/* Track problems in communicating with the battery or charger */
-enum problem_type {
-	PR_STATIC_UPDATE,
-	PR_SET_VOLTAGE,
-	PR_SET_CURRENT,
-	PR_SET_MODE,
-	PR_SET_INPUT_CURR,
-	PR_POST_INIT,
-	PR_CHG_FLAGS,
-	PR_BATT_FLAGS,
-	PR_CUSTOM,
-	PR_CFG_SEC_CHG,
-
-	NUM_PROBLEM_TYPES
-};
-static const char * const prob_text[] = {
-	"static update",
-	"set voltage",
-	"set current",
-	"set mode",
-	"set input current",
-	"post init",
-	"chg params",
-	"batt params",
-	"custom profile",
-	"cfg secondary chg"
-};
-BUILD_ASSERT(ARRAY_SIZE(prob_text) == NUM_PROBLEM_TYPES);
-
-/*
- * TODO(crosbug.com/p/27639): When do we decide a problem is real and not
- * just intermittent? And what do we do about it?
- */
-static void problem(enum problem_type p, int v)
-{
-	static int __bss_slow last_prob_val[NUM_PROBLEM_TYPES];
-	static timestamp_t __bss_slow last_prob_time[NUM_PROBLEM_TYPES];
-	timestamp_t t_now, t_diff;
-
-	if (last_prob_val[p] != v) {
-		t_now = get_time();
-		t_diff.val = t_now.val - last_prob_time[p].val;
-		CPRINTS("charge problem: %s, 0x%x -> 0x%x after %.6" PRId64 "s",
-			 prob_text[p], last_prob_val[p], v, t_diff.val);
-		last_prob_val[p] = v;
-		last_prob_time[p] = t_now;
-	}
-	problems_exist = 1;
-}
-
-test_export_static enum ec_charge_control_mode get_chg_ctrl_mode(void)
-{
-	return chg_ctl_mode;
-}
-
-static int battery_sustainer_set(int8_t lower, int8_t upper)
-{
-	if (lower == -1 || upper == -1) {
-		CPRINTS("Sustain mode disabled");
-		sustain_soc.lower = -1;
-		sustain_soc.upper = -1;
-		return EC_SUCCESS;
-	}
-
-	if (lower <= upper && 0 <= lower && upper <= 100) {
-		/* Currently sustainer requires discharge_on_ac. */
-		if (!IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC))
-			return EC_RES_UNAVAILABLE;
-		sustain_soc.lower = lower;
-		sustain_soc.upper = upper;
-		return EC_SUCCESS;
-	}
-
-	CPRINTS("Invalid param: %s(%d, %d)", __func__, lower, upper);
-	return EC_ERROR_INVAL;
-}
-
-static void battery_sustainer_disable(void)
-{
-	battery_sustainer_set(-1, -1);
-}
-
-static bool battery_sustainer_enabled(void)
-{
-	return sustain_soc.lower != -1 && sustain_soc.upper != -1;
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-/*
- * Parameters for dual-battery policy.
- * TODO(b:71881017): This should be made configurable by AP in the future.
- */
-struct dual_battery_policy {
-	/*** Policies when AC is not connected. ***/
-	/* Voltage to use when using OTG mode between lid and base (mV) */
-	uint16_t otg_voltage;
-	/* Maximum current to apply from base to lid (mA) */
-	uint16_t max_base_to_lid_current;
-	/*
-	 * Margin to apply between provided OTG output current and input current
-	 * limit, to make sure that input charger does not overcurrent output
-	 * charger. input_current = (1-margin) * output_current. (/128)
-	 */
-	uint8_t margin_otg_current;
-
-	/* Only do base to lid OTG when base battery above this value (%) */
-	uint8_t min_charge_base_otg;
-
-	/*
-	 * When base/lid battery percentage is below this value, do
-	 * battery-to-battery charging. (%)
-	 */
-	uint8_t max_charge_base_batt_to_batt;
-	uint8_t max_charge_lid_batt_to_batt;
-
-	/*** Policies when AC is connected. ***/
-	/* Minimum power to allocate to base (mW), includes some margin to allow
-	 * base to charge when critically low.
-	 */
-	uint16_t min_base_system_power;
-
-	/* Smoothing factor for lid power (/128) */
-	uint8_t lid_system_power_smooth;
-	/*
-	 * Smoothing factor for base/lid battery power, when the battery power
-	 * is decreasing only: we try to estimate the maximum power that the
-	 * battery is willing to take and always reset it when it draws more
-	 * than the estimate. (/128)
-	 */
-	uint8_t battery_power_smooth;
-
-	/*
-	 * Margin to add to requested base/lid battery power, to figure out how
-	 * much current to allocate. allocation = (1+margin) * request. (/128)
-	 */
-	uint8_t margin_base_battery_power;
-	uint8_t margin_lid_battery_power;
-
-	/* Maximum current to apply from lid to base (mA) */
-	uint16_t max_lid_to_base_current;
-};
-
-static const struct dual_battery_policy db_policy = {
-	.otg_voltage = 12000, /* mV */
-	.max_base_to_lid_current = 1800, /* mA, about 2000mA with margin. */
-	.margin_otg_current = 13, /* /128 = 10.1% */
-	.min_charge_base_otg = 5, /* % */
-	.max_charge_base_batt_to_batt = 4, /* % */
-	.max_charge_lid_batt_to_batt = 10, /* % */
-	.min_base_system_power = 1300, /* mW */
-	.lid_system_power_smooth = 32, /* 32/128 = 0.25 */
-	.battery_power_smooth = 1, /* 1/128 = 0.008 */
-	.margin_base_battery_power = 32, /* 32/128 = 0.25 */
-	.margin_lid_battery_power = 32, /* 32/128 = 0.25 */
-	.max_lid_to_base_current = 2000, /* mA */
-};
-
-/* Add at most "value" to power_var, subtracting from total_power budget. */
-#define CHG_ALLOCATE(power_var, total_power, value) do {	\
-	int val_capped = MIN(value, total_power);		\
-	(power_var) += val_capped;				\
-	(total_power) -= val_capped;				\
-} while (0)
-
-/* Update base battery information */
-static void update_base_battery_info(void)
-{
-	struct ec_response_battery_dynamic_info *const bd =
-		&battery_dynamic[BATT_IDX_BASE];
-
-	base_connected = board_is_base_connected();
-
-	if (!base_connected) {
-		const int invalid_flags = EC_BATT_FLAG_INVALID_DATA;
-		/* Invalidate static/dynamic information */
-		if (bd->flags != invalid_flags) {
-			bd->flags = invalid_flags;
-
-			host_set_single_event(EC_HOST_EVENT_BATTERY);
-			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-		}
-		charge_base = -1;
-		base_responsive = 0;
-		prev_current_base = 0;
-		prev_allow_charge_base = 0;
-	} else if (base_responsive) {
-		int old_flags = bd->flags;
-		int flags_changed;
-		int old_full_capacity = bd->full_capacity;
-
-		ec_ec_client_base_get_dynamic_info();
-		flags_changed = (old_flags != bd->flags);
-		/* Fetch static information when flags change. */
-		if (flags_changed)
-			ec_ec_client_base_get_static_info();
-
-		battery_memmap_refresh(BATT_IDX_BASE);
-
-		/* Newly connected battery, or change in capacity. */
-		if (old_flags & EC_BATT_FLAG_INVALID_DATA ||
-				((old_flags & EC_BATT_FLAG_BATT_PRESENT) !=
-				 (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) ||
-				old_full_capacity != bd->full_capacity)
-			host_set_single_event(EC_HOST_EVENT_BATTERY);
-
-		if (flags_changed)
-			host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-
-		/* Update charge_base */
-		if (bd->flags & (BATT_FLAG_BAD_FULL_CAPACITY |
-				 BATT_FLAG_BAD_REMAINING_CAPACITY))
-			charge_base = -1;
-		else if (bd->full_capacity > 0)
-			charge_base = 100 * bd->remaining_capacity
-						/ bd->full_capacity;
-		else
-			charge_base = 0;
-	}
-}
-
-/**
- * Setup current settings for base, and record previous values, if the base
- * is responsive.
- *
- * @param current_base Current to be drawn by base (negative to provide power)
- * @param allow_charge_base Whether base battery should be charged (only makes
- *                          sense with positive current)
- */
-static int set_base_current(int current_base, int allow_charge_base)
-{
-	/* "OTG" voltage from base to lid. */
-	const int otg_voltage = db_policy.otg_voltage;
-	int ret;
-
-	ret = ec_ec_client_base_charge_control(current_base,
-					otg_voltage, allow_charge_base);
-	if (ret) {
-		/* Ignore errors until the base is responsive. */
-		if (base_responsive)
-			return ret;
-	} else {
-		base_responsive = 1;
-		prev_current_base = current_base;
-		prev_allow_charge_base = allow_charge_base;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-/**
- * Setup current settings for lid and base, in a safe way.
- *
- * @param current_base Current to be drawn by base (negative to provide power)
- * @param allow_charge_base Whether base battery should be charged (only makes
- *                          sense with positive current)
- * @param current_lid Current to be drawn by lid (negative to provide power)
- * @param allow_charge_lid Whether lid battery should be charged
- */
-static void set_base_lid_current(int current_base, int allow_charge_base,
-				 int current_lid, int allow_charge_lid)
-{
-	/* "OTG" voltage from lid to base. */
-	const int otg_voltage = db_policy.otg_voltage;
-
-	int lid_first;
-	int ret;
-	int chgnum = 0;
-
-	/* TODO(b:71881017): This is still quite verbose during charging. */
-	if (prev_current_base != current_base ||
-	    prev_allow_charge_base != allow_charge_base ||
-	    prev_current_lid != current_lid) {
-		CPRINTS("Base/Lid: %d%s/%d%s mA",
-			current_base, allow_charge_base ? "+" : "",
-			current_lid, allow_charge_lid ? "+" : "");
-	}
-
-	/*
-	 * To decide whether to first control the lid or the base, we first
-	 * control the side that _reduces_ current that would be drawn, then
-	 * setup one that would start providing power, then increase current.
-	 */
-	if (current_lid >= 0 && current_lid < prev_current_lid)
-		lid_first = 1; /* Lid decreases current */
-	else if (current_base >= 0 && current_base < prev_current_base)
-		lid_first = 0; /* Base decreases current */
-	else if (current_lid < 0)
-		lid_first = 1; /* Lid provide power */
-	else
-		lid_first = 0; /* All other cases: control the base first */
-
-	if (!lid_first && base_connected) {
-		ret = set_base_current(current_base, allow_charge_base);
-		if (ret)
-			return;
-	}
-
-	if (current_lid >= 0) {
-		ret = charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
-		if (ret)
-			return;
-		ret = charger_set_input_current_limit(chgnum, current_lid);
-		if (ret)
-			return;
-		if (allow_charge_lid)
-			ret = charge_request(curr.requested_voltage,
-				curr.requested_current);
-		else
-			ret = charge_request(0, 0);
-	} else {
-		ret = charge_set_output_current_limit(CHARGER_SOLO,
-						-current_lid, otg_voltage);
-	}
-
-	if (ret)
-		return;
-
-	prev_current_lid = current_lid;
-
-	if (lid_first && base_connected) {
-		ret = set_base_current(current_base, allow_charge_base);
-		if (ret)
-			return;
-	}
-
-	/*
-	 * Make sure cross-power is enabled (it might not be enabled right after
-	 * plugging the base, or when an adapter just got connected).
-	 */
-	if (base_connected && current_base != 0)
-		board_enable_base_power(1);
-}
-
-/**
- * Smooth power value, covering some edge cases.
- * Compute s*curr+(1-s)*prev, where s is in 1/128 unit.
- */
-static int smooth_value(int prev, int curr, int s)
-{
-	if (curr < 0)
-		curr = 0;
-	if (prev < 0)
-		return curr;
-
-	return prev + s * (curr - prev) / 128;
-}
-
-/**
- * Add margin m to value. Compute (1+m)*value, where m is in 1/128 unit.
- */
-static int add_margin(int value, int m)
-{
-	return value + m * value / 128;
-}
-
-static void charge_allocate_input_current_limit(void)
-{
-	/*
-	 * All the power numbers are in mW.
-	 *
-	 * Since we work with current and voltage in mA and mV, multiplying them
-	 * gives numbers in uW, which are dangerously close to overflowing when
-	 * doing intermediate computations (60W * 100 overflows a 32-bit int,
-	 * for example). We therefore divide the product by 1000 and re-multiply
-	 * the power numbers by 1000 when converting them back to current.
-	 */
-	int total_power = 0;
-
-	static int prev_base_battery_power = -1;
-	int base_battery_power = 0;
-	int base_battery_power_max = 0;
-
-	static int prev_lid_system_power = -1;
-	int lid_system_power;
-
-	static int prev_lid_battery_power = -1;
-	int lid_battery_power = 0;
-	int lid_battery_power_max = 0;
-
-	int power_base = 0;
-	int power_lid = 0;
-
-	int current_base = 0;
-	int current_lid = 0;
-
-	int charge_lid = charge_get_percent();
-
-	const struct ec_response_battery_dynamic_info *const base_bd =
-		&battery_dynamic[BATT_IDX_BASE];
-
-
-	if (!base_connected) {
-		set_base_lid_current(0, 0, curr.desired_input_current, 1);
-		prev_base_battery_power = -1;
-		return;
-	}
-
-	/* Charging */
-	if (curr.desired_input_current > 0 && curr.input_voltage > 0)
-		total_power =
-			curr.desired_input_current * curr.input_voltage / 1000;
-
-	/*
-	 * TODO(b:71723024): We should be able to replace this test by curr.ac,
-	 * but the value is currently wrong, especially during transitions.
-	 */
-	if (total_power <= 0) {
-		int base_critical = charge_base >= 0 &&
-			charge_base < db_policy.max_charge_base_batt_to_batt;
-
-		/* Discharging */
-		prev_base_battery_power = -1;
-		prev_lid_system_power = -1;
-		prev_lid_battery_power = -1;
-
-		/* Manual control */
-		if (manual_noac_enabled) {
-			int lid_current, base_current;
-
-			if (manual_noac_current_base > 0) {
-				base_current = -manual_noac_current_base;
-				lid_current =
-					add_margin(manual_noac_current_base,
-						db_policy.margin_otg_current);
-			} else {
-				lid_current = manual_noac_current_base;
-				base_current =
-					add_margin(-manual_noac_current_base,
-						db_policy.margin_otg_current);
-			}
-
-			set_base_lid_current(base_current, 0, lid_current, 0);
-			return;
-		}
-
-		/*
-		 * System is off, cut power to the base. We'll reset the base
-		 * when system restarts, or when AC is plugged.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			set_base_lid_current(0, 0, 0, 0);
-			if (base_responsive) {
-				/* Base still responsive, put it to sleep. */
-				CPRINTF("Hibernating base\n");
-				ec_ec_client_hibernate();
-				base_responsive = 0;
-				board_enable_base_power(0);
-			}
-			return;
-		}
-
-		/*
-		 * System is suspended, let the lid and base run on their
-		 * own power. However, if the base battery is critically low, we
-		 * still want to provide power to the base, to make sure it
-		 * stays alive to be able to wake the system on keyboard or
-		 * touchpad events.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-					!base_critical) {
-			set_base_lid_current(0, 0, 0, 0);
-			return;
-		}
-
-		if (charge_base > db_policy.min_charge_base_otg) {
-			int lid_current = db_policy.max_base_to_lid_current;
-			int base_current = add_margin(lid_current,
-						db_policy.margin_otg_current);
-			/* Draw current from base to lid */
-			set_base_lid_current(-base_current, 0, lid_current,
-			    charge_lid < db_policy.max_charge_lid_batt_to_batt);
-		} else {
-			/*
-			 * Base battery is too low, apply power to it, and allow
-			 * it to charge if it is critically low.
-			 *
-			 * TODO(b:71881017): When suspended, this will make the
-			 * battery charge oscillate between 3 and 4 percent,
-			 * which might not be great for battery life. We need
-			 * some hysteresis.
-			 */
-			/*
-			 * TODO(b:71881017): Precompute (ideally, at build time)
-			 * the base_current, so we do not need to do a division
-			 * here.
-			 */
-			int base_current =
-				(db_policy.min_base_system_power * 1000) /
-				db_policy.otg_voltage;
-			int lid_current = add_margin(base_current,
-						db_policy.margin_otg_current);
-
-			set_base_lid_current(base_current, base_critical,
-					     -lid_current, 0);
-		}
-
-		return;
-	}
-
-	/* Manual control */
-	if (manual_ac_current_base >= 0) {
-		int current_base = manual_ac_current_base;
-		int current_lid =
-			curr.desired_input_current - manual_ac_current_base;
-
-		if (current_lid < 0) {
-			current_base = curr.desired_input_current;
-			current_lid = 0;
-		}
-
-		set_base_lid_current(current_base, 1, current_lid, 1);
-		return;
-	}
-
-	/* Estimate system power. */
-	lid_system_power = charger_get_system_power() / 1000;
-
-	/* Smooth system power, as it is very spiky */
-	lid_system_power = smooth_value(prev_lid_system_power,
-			lid_system_power, db_policy.lid_system_power_smooth);
-	prev_lid_system_power = lid_system_power;
-
-	/*
-	 * TODO(b:71881017): Smoothing the battery power isn't necessarily a
-	 * good idea: if the system takes up too much power, we may reduce the
-	 * estimate power too quickly, leading to oscillations when the system
-	 * power goes down. Instead, we should probably estimate the current
-	 * based on remaining capacity.
-	 */
-	/* Estimate lid battery power. */
-	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)))
-		lid_battery_power = curr.batt.current *
-				    curr.batt.voltage / 1000;
-	if (lid_battery_power < prev_lid_battery_power)
-		lid_battery_power = smooth_value(prev_lid_battery_power,
-			     lid_battery_power, db_policy.battery_power_smooth);
-	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT)))
-		lid_battery_power_max = curr.batt.desired_current *
-					curr.batt.desired_voltage / 1000;
-
-	lid_battery_power = MIN(lid_battery_power, lid_battery_power_max);
-
-	/* Estimate base battery power. */
-	if (!(base_bd->flags & EC_BATT_FLAG_INVALID_DATA)) {
-		base_battery_power = base_bd->actual_current *
-				     base_bd->actual_voltage / 1000;
-		base_battery_power_max = base_bd->desired_current *
-					 base_bd->desired_voltage / 1000;
-	}
-	if (base_battery_power < prev_base_battery_power)
-		base_battery_power = smooth_value(prev_base_battery_power,
-			    base_battery_power, db_policy.battery_power_smooth);
-	base_battery_power = MIN(base_battery_power, base_battery_power_max);
-
-	if (debugging) {
-		CPRINTF("%s:\n", __func__);
-		CPRINTF("total power: %d\n", total_power);
-		CPRINTF("base battery power: %d (%d)\n",
-			base_battery_power, base_battery_power_max);
-		CPRINTF("lid system power: %d\n", lid_system_power);
-		CPRINTF("lid battery power: %d\n", lid_battery_power);
-		CPRINTF("percent base/lid: %d%% %d%%\n",
-			charge_base, charge_lid);
-	}
-
-	prev_lid_battery_power = lid_battery_power;
-	prev_base_battery_power = base_battery_power;
-
-	if (total_power > 0) { /* Charging */
-		/* Allocate system power */
-		CHG_ALLOCATE(power_base, total_power,
-			db_policy.min_base_system_power);
-		CHG_ALLOCATE(power_lid, total_power, lid_system_power);
-
-		/* Allocate lid, then base battery power */
-		lid_battery_power = add_margin(lid_battery_power,
-					db_policy.margin_lid_battery_power);
-		CHG_ALLOCATE(power_lid, total_power, lid_battery_power);
-
-		base_battery_power = add_margin(base_battery_power,
-					db_policy.margin_base_battery_power);
-		CHG_ALLOCATE(power_base, total_power, base_battery_power);
-
-		/* Give everything else to the lid. */
-		CHG_ALLOCATE(power_lid, total_power, total_power);
-		if (debugging)
-			CPRINTF("power: base %d mW / lid %d mW\n",
-				power_base, power_lid);
-
-		current_base = 1000 * power_base / curr.input_voltage;
-		current_lid = 1000 * power_lid / curr.input_voltage;
-
-		if (current_base > db_policy.max_lid_to_base_current) {
-			current_lid += (current_base
-					- db_policy.max_lid_to_base_current);
-			current_base = db_policy.max_lid_to_base_current;
-		}
-
-		if (debugging)
-			CPRINTF("current: base %d mA / lid %d mA\n",
-				current_base, current_lid);
-
-		set_base_lid_current(current_base, 1, current_lid, 1);
-	} else { /* Discharging */
-	}
-
-	if (debugging)
-		CPRINTF("====\n");
-}
-#endif /* CONFIG_EC_EC_COMM_BATTERY_CLIENT */
-
-#ifndef CONFIG_BATTERY_V2
-/* Returns zero if every item was updated. */
-static int update_static_battery_info(void)
-{
-	char *batt_str;
-	int batt_serial;
-	uint8_t batt_flags = 0;
-	/*
-	 * The return values have type enum ec_error_list, but EC_SUCCESS is
-	 * zero. We'll just look for any failures so we can try them all again.
-	 */
-	int rv;
-
-	/* Smart battery serial number is 16 bits */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv = battery_serial_number(&batt_serial);
-	if (!rv)
-		snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X", batt_serial);
-
-	/* Design Capacity of Full */
-	rv |= battery_design_capacity(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP));
-
-	/* Design Voltage */
-	rv |= battery_design_voltage(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT));
-
-	/* Last Full Charge Capacity (this is only mostly static) */
-	rv |= battery_full_charge_capacity(
-		(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC));
-
-	/* Cycle Count */
-	rv |= battery_cycle_count((int *)host_get_memmap(EC_MEMMAP_BATT_CCNT));
-
-	/* Battery Manufacturer string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MFGR);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv |= battery_manufacturer_name(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Battery Model string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_MODEL);
-	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
-	rv |= battery_device_name(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Battery Type string */
-	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_TYPE);
-	rv |= battery_device_chemistry(batt_str, EC_MEMMAP_TEXT_MAX);
-
-	/* Zero the dynamic entries. They'll come next. */
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_VOLT) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_RATE) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_CAP) = 0;
-	*(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC) = 0;
-	if (extpower_is_present())
-		batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	*host_get_memmap(EC_MEMMAP_BATT_FLAG) = batt_flags;
-
-	if (rv)
-		problem(PR_STATIC_UPDATE, rv);
-	else
-		/* No errors seen. Battery data is now present */
-		*host_get_memmap(EC_MEMMAP_BATTERY_VERSION) = 1;
-
-	return rv;
-}
-
-static void update_dynamic_battery_info(void)
-{
-	/* The memmap address is constant. We should fix these calls somehow. */
-	int *memmap_volt = (int *)host_get_memmap(EC_MEMMAP_BATT_VOLT);
-	int *memmap_rate = (int *)host_get_memmap(EC_MEMMAP_BATT_RATE);
-	int *memmap_cap = (int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
-	int *memmap_lfcc = (int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	uint8_t *memmap_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-	uint8_t tmp;
-	int send_batt_status_event = 0;
-	int send_batt_info_event = 0;
-	static int __bss_slow batt_present;
-
-	tmp = 0;
-	if (curr.ac)
-		tmp |= EC_BATT_FLAG_AC_PRESENT;
-
-	if (curr.batt.is_present == BP_YES) {
-		tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		batt_present = 1;
-		/* Tell the AP to read battery info if it is newly present. */
-		if (!(*memmap_flags & EC_BATT_FLAG_BATT_PRESENT))
-			send_batt_info_event++;
-	} else {
-		/*
-		 * Require two consecutive updates with BP_NOT_SURE
-		 * before reporting it gone to the host.
-		 */
-		if (batt_present)
-			tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		else if (*memmap_flags & EC_BATT_FLAG_BATT_PRESENT)
-			send_batt_info_event++;
-		batt_present = 0;
-	}
-
-	if (curr.batt.flags & EC_BATT_FLAG_INVALID_DATA)
-		tmp |= EC_BATT_FLAG_INVALID_DATA;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE))
-		*memmap_volt = curr.batt.voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_CURRENT))
-		*memmap_rate = ABS(curr.batt.current);
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
-		/*
-		 * If we're running off the battery, it must have some charge.
-		 * Don't report zero charge, as that has special meaning
-		 * to Chrome OS powerd.
-		 */
-		if (curr.batt.remaining_capacity == 0 && !curr.batt_is_charging)
-			*memmap_cap = 1;
-		else
-			*memmap_cap = curr.batt.remaining_capacity;
-	}
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
-	    (curr.batt.full_capacity <= (*memmap_lfcc - LFCC_EVENT_THRESH) ||
-	     curr.batt.full_capacity >= (*memmap_lfcc + LFCC_EVENT_THRESH))) {
-		*memmap_lfcc = curr.batt.full_capacity;
-		/* Poke the AP if the full_capacity changes. */
-		send_batt_info_event++;
-	}
-
-	if (curr.batt.is_present == BP_YES &&
-	    !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
-		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
-
-	tmp |= curr.batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
-
-	/* Tell the AP to re-read battery status if charge state changes */
-	if (*memmap_flags != tmp)
-		send_batt_status_event++;
-
-	/* Update flags before sending host events. */
-	*memmap_flags = tmp;
-
-	if (send_batt_info_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY);
-	if (send_batt_status_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-}
-#else /* CONFIG_BATTERY_V2 */
-
-static int is_battery_string_reliable(const char *buf)
-{
-	/*
-	 * From is_string_printable rule, 0xFF is not printable.
-	 * So, EC should think battery string is unreliable if string
-	 * include 0xFF.
-	 */
-	while (*buf) {
-		if ((*buf) == 0xFF)
-			return 0;
-		buf++;
-	}
-
-	return 1;
-}
-
-static int update_static_battery_info(void)
-{
-	int batt_serial;
-	int val;
-	/*
-	 * The return values have type enum ec_error_list, but EC_SUCCESS is
-	 * zero. We'll just look for any failures so we can try them all again.
-	 */
-	int rv, ret;
-
-	struct ec_response_battery_static_info_v1 *const bs =
-		&battery_static[BATT_IDX_MAIN];
-
-	/* Clear all static information. */
-	memset(bs, 0, sizeof(*bs));
-
-	/* Smart battery serial number is 16 bits */
-	rv = battery_serial_number(&batt_serial);
-	if (!rv)
-		snprintf(bs->serial_ext, sizeof(bs->serial_ext),
-			 "%04X", batt_serial);
-
-	/* Design Capacity of Full */
-	ret = battery_design_capacity(&val);
-	if (!ret)
-		bs->design_capacity = val;
-	rv |= ret;
-
-	/* Design Voltage */
-	ret = battery_design_voltage(&val);
-	if (!ret)
-		bs->design_voltage = val;
-	rv |= ret;
-
-	/* Cycle Count */
-	ret = battery_cycle_count(&val);
-	if (!ret)
-		bs->cycle_count = val;
-	rv |= ret;
-
-	/* Battery Manufacturer string */
-	rv |= battery_manufacturer_name(bs->manufacturer_ext,
-					sizeof(bs->manufacturer_ext));
-
-	/* Battery Model string */
-	rv |= battery_device_name(bs->model_ext, sizeof(bs->model_ext));
-
-	/* Battery Type string */
-	rv |= battery_device_chemistry(bs->type_ext, sizeof(bs->type_ext));
-
-	/*
-	 * b/181639264: Battery gauge follow SMBus SPEC and SMBus define
-	 * cumulative clock low extend time for both controller (master) and
-	 * peripheral (slave). However, I2C doesn't.
-	 * Regarding this issue, we observe EC sometimes pull I2C CLK low
-	 * a while after EC start running. Actually, we are not sure the
-	 * reason until now.
-	 * If EC pull I2C CLK low too long, and it may cause battery fw timeout
-	 * because battery count cumulative clock extend time over 25ms.
-	 * When it happened, battery will release both its CLK and DATA and
-	 * reset itself. So, EC may get 0xFF when EC keep reading data from
-	 * battery. Battery static information will be unreliable and need to
-	 * be updated.
-	 * This change is improvement that EC should retry if battery string is
-	 * unreliable.
-	 */
-	if (!is_battery_string_reliable(bs->serial_ext) ||
-	    !is_battery_string_reliable(bs->manufacturer_ext) ||
-	    !is_battery_string_reliable(bs->model_ext) ||
-	    !is_battery_string_reliable(bs->type_ext))
-		rv |= EC_ERROR_UNKNOWN;
-
-	/* Zero the dynamic entries. They'll come next. */
-	memset(&battery_dynamic[BATT_IDX_MAIN], 0,
-	       sizeof(battery_dynamic[BATT_IDX_MAIN]));
-
-	if (rv)
-		problem(PR_STATIC_UPDATE, rv);
-
-#ifdef HAS_TASK_HOSTCMD
-	battery_memmap_refresh(BATT_IDX_MAIN);
-#endif
-
-	return rv;
-}
-
-static void update_dynamic_battery_info(void)
-{
-	static int __bss_slow batt_present;
-	uint8_t tmp;
-	int send_batt_status_event = 0;
-	int send_batt_info_event = 0;
-
-	struct ec_response_battery_dynamic_info *const bd =
-		&battery_dynamic[BATT_IDX_MAIN];
-
-	tmp = 0;
-	if (curr.ac)
-		tmp |= EC_BATT_FLAG_AC_PRESENT;
-
-	if (curr.batt.is_present == BP_YES) {
-		tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		batt_present = 1;
-		/* Tell the AP to read battery info if it is newly present. */
-		if (!(bd->flags & EC_BATT_FLAG_BATT_PRESENT))
-			send_batt_info_event++;
-	} else {
-		/*
-		 * Require two consecutive updates with BP_NOT_SURE
-		 * before reporting it gone to the host.
-		 */
-		if (batt_present)
-			tmp |= EC_BATT_FLAG_BATT_PRESENT;
-		else if (bd->flags & EC_BATT_FLAG_BATT_PRESENT)
-			send_batt_info_event++;
-		batt_present = 0;
-	}
-
-	if (curr.batt.flags & EC_BATT_FLAG_INVALID_DATA)
-		tmp |= EC_BATT_FLAG_INVALID_DATA;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE))
-		bd->actual_voltage = curr.batt.voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_CURRENT))
-		bd->actual_current = curr.batt.current;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_DESIRED_VOLTAGE))
-		bd->desired_voltage = curr.batt.desired_voltage;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_DESIRED_CURRENT))
-		bd->desired_current = curr.batt.desired_current;
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) {
-		/*
-		 * If we're running off the battery, it must have some charge.
-		 * Don't report zero charge, as that has special meaning
-		 * to Chrome OS powerd.
-		 */
-		if (curr.batt.remaining_capacity == 0 && !curr.batt_is_charging)
-			bd->remaining_capacity = 1;
-		else
-			bd->remaining_capacity = curr.batt.remaining_capacity;
-	}
-
-	if (!(curr.batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
-		(curr.batt.full_capacity <=
-			(bd->full_capacity - LFCC_EVENT_THRESH) ||
-		 curr.batt.full_capacity >=
-			(bd->full_capacity + LFCC_EVENT_THRESH))) {
-		bd->full_capacity = curr.batt.full_capacity;
-		/* Poke the AP if the full_capacity changes. */
-		send_batt_info_event++;
-	}
-
-	if (curr.batt.is_present == BP_YES &&
-	    !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
-		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
-
-	tmp |= curr.batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
-
-	/* Tell the AP to re-read battery status if charge state changes */
-	if (bd->flags != tmp)
-		send_batt_status_event++;
-
-	bd->flags = tmp;
-
-#ifdef HAS_TASK_HOSTCMD
-	battery_memmap_refresh(BATT_IDX_MAIN);
-#endif
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-	if (send_batt_info_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY);
-	if (send_batt_status_event)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_STATUS);
-#endif
-}
-#endif /* CONFIG_BATTERY_V2 */
-
-static const char * const state_list[] = {
-	"idle", "discharge", "charge", "precharge"
-};
-BUILD_ASSERT(ARRAY_SIZE(state_list) == NUM_STATES_V2);
-static const char * const batt_pres[] = {
-	"NO", "YES", "NOT_SURE",
-};
-
-const char *mode_text[] = EC_CHARGE_MODE_TEXT;
-BUILD_ASSERT(ARRAY_SIZE(mode_text) == CHARGE_CONTROL_COUNT);
-
-static void dump_charge_state(void)
-{
-#define DUMP(FLD, FMT) ccprintf(#FLD " = " FMT "\n", curr.FLD)
-#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg. FLD)
-#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt. FLD)
-#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc. FLD)
-
-	enum ec_charge_control_mode cmode = get_chg_ctrl_mode();
-
-	ccprintf("state = %s\n", state_list[curr.state]);
-	DUMP(ac, "%d");
-	DUMP(batt_is_charging, "%d");
-	ccprintf("chg.*:\n");
-	DUMP_CHG(voltage, "%dmV");
-	DUMP_CHG(current, "%dmA");
-	DUMP_CHG(input_current, "%dmA");
-	DUMP_CHG(status, "0x%x");
-	DUMP_CHG(option, "0x%x");
-	DUMP_CHG(flags, "0x%x");
-	cflush();
-	ccprintf("batt.*:\n");
-	ccprintf("\ttemperature = %dC\n",
-		 DECI_KELVIN_TO_CELSIUS(curr.batt.temperature));
-	DUMP_BATT(state_of_charge, "%d%%");
-	DUMP_BATT(voltage, "%dmV");
-	DUMP_BATT(current, "%dmA");
-	DUMP_BATT(desired_voltage, "%dmV");
-	DUMP_BATT(desired_current, "%dmA");
-	DUMP_BATT(flags, "0x%x");
-	DUMP_BATT(remaining_capacity, "%dmAh");
-	DUMP_BATT(full_capacity, "%dmAh");
-	ccprintf("\tis_present = %s\n", batt_pres[curr.batt.is_present]);
-	cflush();
-#ifdef CONFIG_OCPC
-	ccprintf("ocpc.*:\n");
-	DUMP_OCPC(active_chg_chip, "%d");
-	DUMP_OCPC(combined_rsys_rbatt_mo, "%dmOhm");
-	if ((curr.ocpc.active_chg_chip != -1) &&
-	    !(curr.ocpc.chg_flags[curr.ocpc.active_chg_chip] &
-	      OCPC_NO_ISYS_MEAS_CAP)) {
-		DUMP_OCPC(rbatt_mo, "%dmOhm");
-		DUMP_OCPC(rsys_mo, "%dmOhm");
-		DUMP_OCPC(isys_ma, "%dmA");
-	}
-	DUMP_OCPC(vsys_aux_mv, "%dmV");
-	DUMP_OCPC(vsys_mv, "%dmV");
-	DUMP_OCPC(primary_vbus_mv, "%dmV");
-	DUMP_OCPC(primary_ibus_ma, "%dmA");
-	DUMP_OCPC(secondary_vbus_mv, "%dmV");
-	DUMP_OCPC(secondary_ibus_ma, "%dmA");
-	DUMP_OCPC(last_error, "%d");
-	DUMP_OCPC(integral, "%d");
-	DUMP_OCPC(last_vsys, "%dmV");
-	cflush();
-#endif /* CONFIG_OCPC */
-	DUMP(requested_voltage, "%dmV");
-	DUMP(requested_current, "%dmA");
-#ifdef CONFIG_CHARGER_OTG
-	DUMP(output_current, "%dmA");
-#endif
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	DUMP(input_voltage, "%dmV");
-#endif
-	ccprintf("chg_ctl_mode = %s (%d)\n",
-		 cmode < CHARGE_CONTROL_COUNT ? mode_text[cmode] : "UNDEF",
-		 cmode);
-	ccprintf("manual_voltage = %d\n", manual_voltage);
-	ccprintf("manual_current = %d\n", manual_current);
-	ccprintf("user_current_limit = %dmA\n", user_current_limit);
-	ccprintf("battery_seems_dead = %d\n", battery_seems_dead);
-	ccprintf("battery_seems_disconnected = %d\n",
-		 battery_seems_disconnected);
-	ccprintf("battery_was_removed = %d\n", battery_was_removed);
-	ccprintf("debug output = %s\n", debugging ? "on" : "off");
-	ccprintf("Battery sustainer = %s (%d%% ~ %d%%)\n",
-		 battery_sustainer_enabled() ? "on" : "off",
-		 sustain_soc.lower, sustain_soc.upper);
-#undef DUMP
-}
-
-static void show_charging_progress(void)
-{
-	int rv = 0, minutes, to_full, chgnum = 0;
-	int dsoc;
-
-#ifdef CONFIG_BATTERY_SMART
-	/*
-	 * Predicted remaining battery capacity based on AverageCurrent().
-	 * 65535 = Battery is not being discharged.
-	 */
-	if (!battery_time_to_empty(&minutes) && minutes != 65535)
-		to_full = 0;
-	/*
-	 * Predicted time-to-full charge based on AverageCurrent().
-	 * 65535 = Battery is not being discharged.
-	 */
-	else if (!battery_time_to_full(&minutes) && minutes != 65535)
-		to_full = 1;
-	/*
-	 * If both time to empty and time to full have invalid data, consider
-	 * measured current from the coulomb counter and ac present status to
-	 * decide whether battery is about to full or empty.
-	 */
-	else {
-		to_full = curr.batt_is_charging;
-		rv = EC_ERROR_UNKNOWN;
-	}
-#else
-	if (!curr.batt_is_charging) {
-		rv = battery_time_to_empty(&minutes);
-		to_full = 0;
-	} else {
-		rv = battery_time_to_full(&minutes);
-		to_full = 1;
-	}
-#endif
-
-	dsoc = charge_get_display_charge();
-	if (rv)
-		CPRINTS("Battery %d%% (Display %d.%d %%) / ??h:?? %s%s",
-			curr.batt.state_of_charge,
-			dsoc / 10, dsoc % 10,
-			to_full ? "to full" : "to empty",
-			is_full ? ", not accepting current" : "");
-	else
-		CPRINTS("Battery %d%% (Display %d.%d %%) / %dh:%d %s%s",
-			curr.batt.state_of_charge,
-			dsoc / 10, dsoc % 10, minutes / 60, minutes % 60,
-			to_full ? "to full" : "to empty",
-			is_full ? ", not accepting current" : "");
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	CPRINTS("Base battery %d%%", charge_base);
-#endif
-
-	if (debugging) {
-		ccprintf("battery:\n");
-		print_battery_debug();
-		ccprintf("charger:\n");
-		if (IS_ENABLED(CONFIG_OCPC))
-			chgnum = charge_get_active_chg_chip();
-		print_charger_debug(chgnum);
-		ccprintf("chg:\n");
-		dump_charge_state();
-	}
-}
-
-/* Calculate if battery is full based on whether it is accepting charge */
-test_mockable int calc_is_full(void)
-{
-	static int __bss_slow ret;
-
-	/* If bad state of charge reading, return last value */
-	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE ||
-	    curr.batt.state_of_charge > 100)
-		return ret;
-	/*
-	 * Battery is full when SoC is above 90% and battery desired current
-	 * is 0. This is necessary because some batteries stop charging when
-	 * the SoC still reports <100%, so we need to check desired current
-	 * to know if it is actually full.
-	 */
-	ret = (curr.batt.state_of_charge >= 90 &&
-	       curr.batt.desired_current == 0);
-	return ret;
-}
-
-/*
- * Ask the charger for some voltage and current. If either value is 0,
- * charging is disabled; otherwise it's enabled. Negative values are ignored.
- */
-static int charge_request(int voltage, int current)
-{
-	int r1 = EC_SUCCESS, r2 = EC_SUCCESS, r3 = EC_SUCCESS, r4 = EC_SUCCESS;
-	static int __bss_slow prev_volt, prev_curr;
-
-	if (!voltage || !current) {
-#ifdef CONFIG_CHARGER_NARROW_VDC
-		current = 0;
-		/*
-		 * With NVDC charger, keep VSYS voltage higher than battery,
-		 * otherwise the BGATE FET body diode would conduct and
-		 * discharge the battery.
-		 */
-		voltage = charger_closest_voltage(
-			curr.batt.voltage + charger_get_info()->voltage_step);
-		/* If the battery is full, request the max voltage. */
-		if (is_full)
-			voltage = battery_get_info()->voltage_max;
-		/* And handle dead battery case */
-		voltage = MAX(voltage, battery_get_info()->voltage_normal);
-#else
-		voltage = current = 0;
-#endif
-	}
-
-	if (curr.ac) {
-		if (prev_volt != voltage || prev_curr != current)
-			CPRINTS("%s(%dmV, %dmA)", __func__, voltage, current);
-	}
-
-	/*
-	 * Set current before voltage so that if we are just starting
-	 * to charge, we allow some time (i2c delay) for charging circuit to
-	 * start at a voltage just above battery voltage before jumping
-	 * up. This helps avoid large current spikes when connecting
-	 * battery.
-	 */
-	if (current >= 0) {
-#ifdef CONFIG_OCPC
-		/*
-		 * For OCPC systems, don't unconditionally modify the primary
-		 * charger IC's charge current.  It may be handled by the
-		 * charger drivers directly.
-		 */
-		if (curr.ocpc.active_chg_chip == CHARGER_PRIMARY)
-#endif
-			r2 = charger_set_current(0, current);
-	}
-	if (r2 != EC_SUCCESS)
-		problem(PR_SET_CURRENT, r2);
-
-	if (voltage >= 0)
-		r1 = charger_set_voltage(0, voltage);
-	if (r1 != EC_SUCCESS)
-		problem(PR_SET_VOLTAGE, r1);
-
-#ifdef CONFIG_OCPC
-	/*
-	 * For OCPC systems, if the secondary charger is active, we need to
-	 * configure that charge IC as well.  Note that if OCPC ever supports
-	 * more than 2 charger ICs, we'll need to refactor things a bit.  The
-	 * following check should be comparing against CHARGER_PRIMARY and
-	 * config_secondary_charger should probably be config_auxiliary_charger
-	 * and take the active chgnum as a parameter.
-	 */
-	if (curr.ocpc.active_chg_chip == CHARGER_SECONDARY) {
-		if ((current >= 0) || (voltage >= 0))
-			r3 = ocpc_config_secondary_charger(&curr.desired_input_current,
-							   &curr.ocpc,
-							   voltage, current);
-		if (r3 != EC_SUCCESS)
-			problem(PR_CFG_SEC_CHG, r3);
-	}
-#endif /* CONFIG_OCPC */
-
-	/*
-	 * Set the charge inhibit bit when possible as it appears to save
-	 * power in some cases (e.g. Nyan with BQ24735).
-	 */
-	if (voltage > 0 || current > 0)
-		r4 = charger_set_mode(0);
-	else
-		r4 = charger_set_mode(CHARGE_FLAG_INHIBIT_CHARGE);
-	if (r4 != EC_SUCCESS)
-		problem(PR_SET_MODE, r4);
-
-	/*
-	 * Only update if the request worked, so we'll keep trying on failures.
-	 */
-	if (r1 || r2)
-		return r1 ? r1 : r2;
-	if (IS_ENABLED(CONFIG_OCPC) && r3)
-		return r3;
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
-	    (prev_volt != voltage || prev_curr != current))
-		charge_reset_stable_current();
-
-	prev_volt = voltage;
-	prev_curr = current;
-
-	return EC_SUCCESS;
-}
-
-void chgstate_set_manual_current(int curr_ma)
-{
-	if (curr_ma < 0)
-		manual_current = -1;
-	else
-		manual_current = charger_closest_current(curr_ma);
-}
-
-void chgstate_set_manual_voltage(int volt_mv)
-{
-	manual_voltage = charger_closest_voltage(volt_mv);
-}
-
-/* Force charging off before the battery is full. */
-static int set_chg_ctrl_mode(enum ec_charge_control_mode mode)
-{
-	bool discharge_on_ac = false;
-	int current, voltage;
-	int rv;
-
-	current = manual_current;
-	voltage = manual_voltage;
-
-	if (mode >= CHARGE_CONTROL_COUNT)
-		return EC_ERROR_INVAL;
-
-	if (mode == CHARGE_CONTROL_NORMAL) {
-		current = -1;
-		voltage = -1;
-	} else {
-		/* Changing mode is only meaningful if AC is present. */
-		if (!curr.ac)
-			return EC_ERROR_NOT_POWERED;
-
-		if (mode == CHARGE_CONTROL_DISCHARGE) {
-			if (!IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC))
-				return EC_ERROR_UNIMPLEMENTED;
-			discharge_on_ac = true;
-		} else if (mode == CHARGE_CONTROL_IDLE) {
-			current = 0;
-			voltage = 0;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC)) {
-		rv = charger_discharge_on_ac(discharge_on_ac);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	/* Commit all atomically */
-	chg_ctl_mode = mode;
-	manual_current = current;
-	manual_voltage = voltage;
-
-	return EC_SUCCESS;
-}
-
-static inline int battery_too_hot(int batt_temp_c)
-{
-	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
-		(batt_temp_c > batt_info->discharging_max_c));
-}
-
-static inline int battery_too_cold_for_discharge(int batt_temp_c)
-{
-	return (!(curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) &&
-		(batt_temp_c < batt_info->discharging_min_c));
-}
-
-__attribute__((weak)) uint8_t board_set_battery_level_shutdown(void)
-{
-	return BATTERY_LEVEL_SHUTDOWN;
-}
-
-/* True if we know the charge is too low, or we know the voltage is too low. */
-static inline int battery_too_low(void)
-{
-	return ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		 curr.batt.state_of_charge < battery_level_shutdown) ||
-		(!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) &&
-		 curr.batt.voltage <= batt_info->voltage_min));
-}
-
-__attribute__((weak))
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
-{
-#ifdef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-	return CRITICAL_SHUTDOWN_CUTOFF;
-#elif defined(CONFIG_HIBERNATE)
-	return CRITICAL_SHUTDOWN_HIBERNATE;
-#else
-	return CRITICAL_SHUTDOWN_IGNORE;
-#endif
-}
-
-static int is_battery_critical(void)
-{
-	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
-
-	/*
-	 * TODO(crosbug.com/p/27642): The thermal loop should watch the battery
-	 * temp, so it can turn fans on.
-	 */
-	if (battery_too_hot(batt_temp_c)) {
-		CPRINTS("Batt too hot: %dC", batt_temp_c);
-		return 1;
-	}
-
-	/* Note: the battery may run on AC without discharging when too cold */
-	if (!curr.ac && battery_too_cold_for_discharge(batt_temp_c)) {
-		CPRINTS("Batt too cold: %dC", batt_temp_c);
-		return 1;
-	}
-
-	if (battery_too_low() && !curr.batt_is_charging) {
-		CPRINTS("Low battery: %d%%, %dmV",
-			curr.batt.state_of_charge, curr.batt.voltage);
-		return 1;
-	}
-
-	return 0;
-}
-
- /*
-  * If the battery is at extremely low charge (and discharging) or extremely
-  * high temperature, the EC will notify the AP and start a timer. If the
-  * critical condition is not corrected before the timeout expires, the EC
-  * will shut down the AP (if the AP is not already off) and then optionally
-  * hibernate or cut off battery.
-  */
-static int shutdown_on_critical_battery(void)
-{
-	if (!is_battery_critical()) {
-		/* Reset shutdown warning time */
-		shutdown_target_time.val = 0;
-		return 0;
-	}
-
-	if (!shutdown_target_time.val) {
-		/* Start count down timer */
-		CPRINTS("Start shutdown due to critical battery");
-		shutdown_target_time.val = get_time().val
-				+ CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
-#ifdef CONFIG_HOSTCMD_EVENTS
-		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			host_set_single_event(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-#endif
-		return 1;
-	}
-
-	if (!timestamp_expired(shutdown_target_time, 0))
-		return 1;
-
-	/* Timer has expired */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
-		switch (board_critical_shutdown_check(&curr)) {
-		case CRITICAL_SHUTDOWN_HIBERNATE:
-			if (IS_ENABLED(CONFIG_HIBERNATE)) {
-				if (power_get_state() == POWER_S3S5)
-					sleep(1);
-				CPRINTS("Hibernate due to critical battery");
-				cflush();
-				system_hibernate(0, 0);
-			}
-			break;
-		case CRITICAL_SHUTDOWN_CUTOFF:
-			if (power_get_state() == POWER_S3S5)
-				sleep(1);
-			CPRINTS("Cutoff due to critical battery");
-			cflush();
-			board_cut_off_battery();
-			break;
-		case CRITICAL_SHUTDOWN_IGNORE:
-		default:
-			break;
-		}
-	} else {
-		/* Timeout waiting for AP to shut down, so kill it */
-		CPRINTS(
-		  "charge force shutdown due to critical battery");
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_BATTERY_CRIT);
-	}
-
-	return 1;
-}
-
-/*
- * Send host events as the battery charge drops below certain thresholds.
- * We handle forced shutdown and other actions elsewhere; this is just for the
- * host events. We send these even if the AP is off, since the AP will read and
- * discard any events it doesn't care about the next time it wakes up.
- */
-static void notify_host_of_low_battery_charge(void)
-{
-	/* We can't tell what the current charge is. Assume it's okay. */
-	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
-		return;
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_LOW &&
-	    prev_charge > BATTERY_LEVEL_LOW)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_LOW);
-
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL &&
-	    prev_charge > BATTERY_LEVEL_CRITICAL)
-		host_set_single_event(EC_HOST_EVENT_BATTERY_CRITICAL);
-#endif
-}
-
-static void set_charge_state(enum charge_state_v2 state)
-{
-	prev_state = curr.state;
-	curr.state = state;
-}
-
-static void notify_host_of_low_battery_voltage(void)
-{
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-	if ((curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
-	    chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	if (!uvp_throttle_start_time.val &&
-	    (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH)) {
-		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_VOLTAGE);
-		uvp_throttle_start_time = get_time();
-	} else if (uvp_throttle_start_time.val &&
-		   (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH +
-		    BAT_UVP_HYSTERESIS)) {
-		/*
-		 * Reset the timer when we are not sure if VBAT can stay
-		 * above BAT_LOW_VOLTAGE_THRESH after we stop throttling.
-		 */
-		uvp_throttle_start_time = get_time();
-	} else if (uvp_throttle_start_time.val &&
-		   (get_time().val > uvp_throttle_start_time.val +
-		     BAT_UVP_TIMEOUT_US)) {
-		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_VOLTAGE);
-		uvp_throttle_start_time.val = 0;
-	}
-#endif
-}
-
-static void notify_host_of_over_current(struct batt_params *batt)
-{
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-	static timestamp_t ocp_throttle_start_time;
-
-	if (batt->flags & BATT_FLAG_BAD_CURRENT)
-		return;
-
-	if ((!ocp_throttle_start_time.val &&
-	     (batt->current < -BAT_MAX_DISCHG_CURRENT)) ||
-	    (ocp_throttle_start_time.val &&
-	     (batt->current < -BAT_MAX_DISCHG_CURRENT + BAT_OCP_HYSTERESIS))) {
-		ocp_throttle_start_time = get_time();
-		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
-	} else if (ocp_throttle_start_time.val &&
-		   (get_time().val > ocp_throttle_start_time.val +
-		    BAT_OCP_TIMEOUT_US)) {
-		/*
-		 * Clear the timer and notify AP to stop throttling if
-		 * we haven't seen over current for BAT_OCP_TIMEOUT_US.
-		 */
-		ocp_throttle_start_time.val = 0;
-		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
-			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
-	}
-#endif
-}
-
-const struct batt_params *charger_current_battery_params(void)
-{
-	return &curr.batt;
-}
-
-/* Determine if the battery is outside of allowable temperature range */
-static int battery_outside_charging_temperature(void)
-{
-	const struct battery_info *batt_info = battery_get_info();
-	int batt_temp_c = DECI_KELVIN_TO_CELSIUS(curr.batt.temperature);
-	int max_c, min_c;
-
-	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
-		return 0;
-
-	if((curr.batt.desired_voltage == 0) &&
-		(curr.batt.desired_current == 0)){
-		max_c = batt_info->start_charging_max_c;
-		min_c = batt_info->start_charging_min_c;
-	} else {
-		max_c = batt_info->charging_max_c;
-		min_c = batt_info->charging_min_c;
-	}
-
-
-	if ((batt_temp_c >= max_c) ||
-		 (batt_temp_c <= min_c)) {
-		return 1;
-	}
-	return 0;
-}
-
-static void sustain_battery_soc(void)
-{
-	enum ec_charge_control_mode mode = get_chg_ctrl_mode();
-	int soc;
-	int rv;
-
-	/* If either AC or battery is not present, nothing to do. */
-	if (!curr.ac || curr.batt.is_present != BP_YES
-			|| !battery_sustainer_enabled())
-		return;
-
-	soc = charge_get_display_charge() / 10;
-
-	/*
-	 * When lower < upper, the sustainer discharges using DISCHARGE. When
-	 * lower == upper, the sustainer discharges using IDLE. The following
-	 * switch statement handle both cases but in reality either DISCHARGE
-	 * or IDLE is used but not both.
-	 */
-	switch (mode) {
-	case CHARGE_CONTROL_NORMAL:
-		/* Going up */
-		if (sustain_soc.upper < soc)
-			mode = sustain_soc.upper == sustain_soc.lower ?
-				CHARGE_CONTROL_IDLE : CHARGE_CONTROL_DISCHARGE;
-		break;
-	case CHARGE_CONTROL_IDLE:
-		/* Discharging naturally */
-		if (soc < sustain_soc.lower)
-			mode = CHARGE_CONTROL_NORMAL;
-		break;
-	case CHARGE_CONTROL_DISCHARGE:
-		/* Discharging actively. */
-		if (soc < sustain_soc.lower)
-			mode = CHARGE_CONTROL_NORMAL;
-		break;
-	default:
-		return;
-	}
-
-	if (mode == get_chg_ctrl_mode())
-		return;
-
-	rv = set_chg_ctrl_mode(mode);
-	CPRINTS("%s: %s control mode to %s",
-		__func__, rv == EC_SUCCESS ? "Switched" : "Failed to switch",
-		mode_text[mode]);
-}
-
-/*****************************************************************************/
-/* Hooks */
-void charger_init(void)
-{
-	/* Initialize current state */
-	memset(&curr, 0, sizeof(curr));
-	curr.batt.is_present = BP_NOT_SURE;
-	/* Manual voltage/current set to off */
-	manual_voltage = -1;
-	manual_current = -1;
-	/*
-	 * Other tasks read the params like state_of_charge at the beginning of
-	 * their tasks. Make them ready first.
-	 */
-	battery_get_params(&curr.batt);
-
-	battery_sustainer_disable();
-}
-DECLARE_HOOK(HOOK_INIT, charger_init, HOOK_PRIO_DEFAULT);
-
-/* Wake up the task when something important happens */
-static void charge_wakeup(void)
-{
-	task_wake(TASK_ID_CHARGER);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, charge_wakeup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_AC_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-/* Reset the base on S5->S0 transition. */
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_base_reset, HOOK_PRIO_DEFAULT);
-#endif
-
-#ifdef CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-static void bat_low_voltage_throttle_reset(void)
-{
-	uvp_throttle_start_time.val = 0;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     bat_low_voltage_throttle_reset,
-	     HOOK_PRIO_DEFAULT);
-#endif
-
-static int get_desired_input_current(enum battery_present batt_present,
-				     const struct charger_info * const info)
-{
-	if (batt_present == BP_YES || system_is_locked() || base_connected) {
-#ifdef CONFIG_CHARGE_MANAGER
-		int ilim = charge_manager_get_charger_current();
-		return ilim == CHARGE_CURRENT_UNINITIALIZED ?
-			CHARGE_CURRENT_UNINITIALIZED :
-			MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim);
-#else
-		return CONFIG_CHARGER_INPUT_CURRENT;
-#endif
-	} else {
-#ifdef CONFIG_USB_POWER_DELIVERY
-		return MIN(PD_MAX_CURRENT_MA, info->input_current_max);
-#else
-		return info->input_current_max;
-#endif
-	}
-}
-
-static void wakeup_battery(int *need_static)
-{
-	if (battery_seems_dead || battery_is_cut_off()) {
-		/* It's dead, do nothing */
-		set_charge_state(ST_IDLE);
-		curr.requested_voltage = 0;
-		curr.requested_current = 0;
-	} else if (curr.state == ST_PRECHARGE
-			&& (get_time().val > precharge_start_time.val +
-			PRECHARGE_TIMEOUT_US)) {
-		/* We've tried long enough, give up */
-		CPRINTS("battery seems to be dead");
-		battery_seems_dead = 1;
-		set_charge_state(ST_IDLE);
-		curr.requested_voltage = 0;
-		curr.requested_current = 0;
-	} else {
-		/* See if we can wake it up */
-		if (curr.state != ST_PRECHARGE) {
-			CPRINTS("try to wake battery");
-			precharge_start_time = get_time();
-			*need_static = 1;
-		}
-		set_charge_state(ST_PRECHARGE);
-		curr.requested_voltage = batt_info->voltage_max;
-		curr.requested_current = batt_info->precharge_current;
-	}
-}
-
-static void revive_battery(int *need_static)
-{
-	if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD)
-			&& curr.requested_voltage == 0
-			&& curr.requested_current == 0
-			&& curr.batt.state_of_charge == 0) {
-		/*
-		 * Battery is dead, give precharge current
-		 * TODO (crosbug.com/p/29467): remove this workaround
-		 * for dead battery that requests no voltage/current
-		 */
-		curr.requested_voltage = batt_info->voltage_max;
-		curr.requested_current = batt_info->precharge_current;
-	} else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT)
-			&& curr.requested_voltage == 0
-			&& curr.requested_current == 0
-			&& battery_seems_disconnected) {
-		/*
-		 * Battery is in disconnect state. Apply a
-		 * current to kick it out of this state.
-		 */
-		CPRINTS("found battery in disconnect state");
-		curr.requested_voltage = batt_info->voltage_max;
-		curr.requested_current = batt_info->precharge_current;
-	} else if (curr.state == ST_PRECHARGE
-			|| battery_seems_dead || battery_was_removed) {
-		CPRINTS("battery woke up");
-		/* Update the battery-specific values */
-		batt_info = battery_get_info();
-		*need_static = 1;
-	}
-
-	battery_seems_dead = battery_was_removed = 0;
-}
-
-/* Main loop */
-void charger_task(void *u)
-{
-	int sleep_usec;
-	int battery_critical;
-	int need_static = 1;
-	const struct charger_info * const info = charger_get_info();
-	int prev_plt_and_desired_mw;
-	int chgnum = 0;
-
-	/* Get the battery-specific values */
-	batt_info = battery_get_info();
-
-	prev_ac = prev_charge = prev_disp_charge = -1;
-	chg_ctl_mode = CHARGE_CONTROL_NORMAL;
-	shutdown_target_time.val = 0UL;
-	battery_seems_dead = 0;
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	base_responsive = 0;
-	curr.input_voltage = CHARGE_VOLTAGE_UNINITIALIZED;
-	battery_dynamic[BATT_IDX_BASE].flags = EC_BATT_FLAG_INVALID_DATA;
-	charge_base = -1;
-#endif
-#ifdef CONFIG_OCPC
-	ocpc_init(&curr.ocpc);
-	charge_set_active_chg_chip(CHARGE_PORT_NONE);
-#endif /* CONFIG_OCPC */
-
-	/*
-	 * If system is not locked and we don't have a battery to live on,
-	 * then use max input current limit so that we can pull as much power
-	 * as needed.
-	 */
-	prev_bp = BP_NOT_INIT;
-	curr.desired_input_current = get_desired_input_current(
-			curr.batt.is_present, info);
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
-		/* init battery desired power */
-		desired_mw =
-			curr.batt.desired_current * curr.batt.desired_voltage;
-		/*
-		 * Battery charging current needs time to be stable when a
-		 * new charge happens. Start the timer so we can evaluate the
-		 * stable current when timeout.
-		 */
-		charge_reset_stable_current();
-	}
-
-	battery_level_shutdown = board_set_battery_level_shutdown();
-
-	while (1) {
-
-		/* Let's see what's going on... */
-		curr.ts = get_time();
-		sleep_usec = 0;
-		problems_exist = 0;
-		battery_critical = 0;
-		curr.ac = extpower_is_present();
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-		/*
-		 * When base is powering the system, make sure curr.ac stays 0.
-		 * TODO(b:71723024): Fix extpower_is_present() in hardware
-		 * instead.
-		 */
-		if (base_responsive && prev_current_base < 0)
-			curr.ac = 0;
-
-		/* System is off: if AC gets connected, reset the base. */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-				!prev_ac && curr.ac)
-			board_base_reset();
-#endif
-		if (curr.ac != prev_ac) {
-			/*
-			 * We've noticed a change in AC presence, let the board
-			 * know.
-			 */
-			board_check_extpower();
-			if (curr.ac) {
-				/*
-				 * Some chargers are unpowered when the AC is
-				 * off, so we'll reinitialize it when AC
-				 * comes back and set the input current limit.
-				 * Try again if it fails.
-				 */
-				int rv = charger_post_init();
-
-				if (rv != EC_SUCCESS) {
-					problem(PR_POST_INIT, rv);
-				} else if (curr.desired_input_current !=
-					    CHARGE_CURRENT_UNINITIALIZED) {
-					rv = charger_set_input_current_limit(
-						chgnum,
-						curr.desired_input_current);
-					if (rv != EC_SUCCESS)
-						problem(PR_SET_INPUT_CURR, rv);
-				}
-
-				if (rv == EC_SUCCESS)
-					prev_ac = curr.ac;
-			} else {
-				/* Some things are only meaningful on AC */
-				set_chg_ctrl_mode(CHARGE_CONTROL_NORMAL);
-				battery_seems_dead = 0;
-				prev_ac = curr.ac;
-
-				/*
-				 * b/187967523, we should clear charge current,
-				 * otherwise it will effect typeC output.this
-				 * should be ok for all chargers.
-				 */
-				charger_set_current(chgnum, 0);
-			}
-		}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-		update_base_battery_info();
-#endif
-
-		charger_get_params(&curr.chg);
-		battery_get_params(&curr.batt);
-#ifdef CONFIG_OCPC
-		if (curr.ac)
-			ocpc_get_adcs(&curr.ocpc);
-#endif /* CONFIG_OCPC */
-
-		if (prev_bp != curr.batt.is_present) {
-			prev_bp = curr.batt.is_present;
-
-			/* Update battery info due to change of battery */
-			batt_info = battery_get_info();
-			need_static = 1;
-
-			curr.desired_input_current =
-				get_desired_input_current(prev_bp, info);
-			if (curr.desired_input_current !=
-			    CHARGE_CURRENT_UNINITIALIZED)
-				charger_set_input_current_limit(chgnum,
-					curr.desired_input_current);
-			hook_notify(HOOK_BATTERY_SOC_CHANGE);
-		}
-
-		battery_validate_params(&curr.batt);
-
-		notify_host_of_over_current(&curr.batt);
-
-		/* battery current stable now, saves the current. */
-		if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV) &&
-		    get_time().val > stable_ts.val && curr.batt.current >= 0)
-			stable_current = curr.batt.current;
-
-		/*
-		 * Now decide what we want to do about it. We'll normally just
-		 * pass along whatever the battery wants to the charger. Note
-		 * that if battery_get_params() can't get valid values from the
-		 * battery it uses (0, 0), which is probably safer than blindly
-		 * applying power to a battery we can't talk to.
-		 */
-		if (curr.batt.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-					BATT_FLAG_BAD_DESIRED_CURRENT)) {
-			curr.requested_voltage = 0;
-			curr.requested_current = 0;
-		} else {
-			curr.requested_voltage = curr.batt.desired_voltage;
-			curr.requested_current = curr.batt.desired_current;
-		}
-
-		/* If we *know* there's no battery, wait for one to appear. */
-		if (curr.batt.is_present == BP_NO) {
-			if (!curr.ac)
-				CPRINTS("running with no battery and no AC");
-			set_charge_state(ST_IDLE);
-			curr.batt_is_charging = 0;
-			battery_was_removed = 1;
-			goto wait_for_it;
-		}
-
-		/*
-		 * If we had trouble talking to the battery or the charger, we
-		 * should probably do nothing for a bit, and if it doesn't get
-		 * better then flag it as an error.
-		 */
-		if (curr.chg.flags & CHG_FLAG_BAD_ANY)
-			problem(PR_CHG_FLAGS, curr.chg.flags);
-		if (curr.batt.flags & BATT_FLAG_BAD_ANY)
-			problem(PR_BATT_FLAGS, curr.batt.flags);
-
-		/*
-		 * If AC is present, check if input current is sufficient to
-		 * actually charge battery.
-		 */
-		curr.batt_is_charging = curr.ac && (curr.batt.current >= 0);
-
-		/* Don't let the battery hurt itself. */
-		battery_critical = shutdown_on_critical_battery();
-
-		if (!curr.ac) {
-			set_charge_state(ST_DISCHARGE);
-			goto wait_for_it;
-		}
-
-		/* Okay, we're on AC and we should have a battery. */
-
-		/* Used for factory tests. */
-		if (get_chg_ctrl_mode() != CHARGE_CONTROL_NORMAL) {
-			set_charge_state(ST_IDLE);
-			goto wait_for_it;
-		}
-
-		/* If the battery is not responsive, try to wake it up. */
-		if (!(curr.batt.flags & BATT_FLAG_RESPONSIVE)) {
-			wakeup_battery(&need_static);
-			goto wait_for_it;
-		}
-
-		/* The battery is responding. Yay. Try to use it. */
-
-		/*
-		 * Always check the disconnect state.  This is because
-		 * the battery disconnect state is one of the items used
-		 * to decide whether or not to leave safe mode.
-		 */
-		battery_seems_disconnected =
-			battery_get_disconnect_state() == BATTERY_DISCONNECTED;
-
-		revive_battery(&need_static);
-
-		set_charge_state(ST_CHARGE);
-
-wait_for_it:
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) {
-			sleep_usec = charger_profile_override(&curr);
-			if (sleep_usec < 0)
-				problem(PR_CUSTOM, sleep_usec);
-		}
-
-		if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS)
-				&& battery_outside_charging_temperature()) {
-			curr.requested_current = 0;
-			curr.requested_voltage = 0;
-			curr.batt.flags &= ~BATT_FLAG_WANT_CHARGE;
-			if (curr.state != ST_DISCHARGE)
-				curr.state = ST_IDLE;
-		}
-
-#ifdef CONFIG_CHARGE_MANAGER
-		if (curr.batt.state_of_charge >=
-		    CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT &&
-		    !battery_seems_disconnected) {
-			/*
-			 * Sometimes the fuel gauge will report that it has
-			 * sufficient state of charge and remaining capacity,
-			 * but in actuality it doesn't.  When the EC sees that
-			 * information, it trusts it and leaves charge manager
-			 * safe mode.  Doing so will allow CHARGE_PORT_NONE to
-			 * be selected, thereby cutting off the input FETs.
-			 * When the battery cannot provide the charge it claims,
-			 * the system loses power, shuts down, and the battery
-			 * is not charged even though the charger is plugged in.
-			 * By waiting 500ms, we can avoid the selection of
-			 * CHARGE_PORT_NONE around init time and not cut off the
-			 * input FETs.
-			 */
-			msleep(500);
-			charge_manager_leave_safe_mode();
-		}
-#endif
-
-		/* Keep the AP informed */
-		if (need_static)
-			need_static = update_static_battery_info();
-		/* Wait on the dynamic info until the static info is good. */
-		if (!need_static)
-			update_dynamic_battery_info();
-		notify_host_of_low_battery_charge();
-		notify_host_of_low_battery_voltage();
-
-		/* And the EC console */
-		is_full = calc_is_full();
-
-		/* Run battery sustainer (no-op if not applicable). */
-		sustain_battery_soc();
-
-		if ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		    curr.batt.state_of_charge != prev_charge) ||
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-		    (charge_base != prev_charge_base) ||
-#endif
-		    (is_full != prev_full) ||
-		    (curr.state != prev_state) ||
-		    (charge_get_display_charge() != prev_disp_charge)) {
-			show_charging_progress();
-			prev_charge = curr.batt.state_of_charge;
-			prev_disp_charge = charge_get_display_charge();
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-			prev_charge_base = charge_base;
-#endif
-			hook_notify(HOOK_BATTERY_SOC_CHANGE);
-		}
-		prev_full = is_full;
-
-#ifndef CONFIG_CHARGER_MAINTAIN_VBAT
-		/* Turn charger off if it's not needed */
-		if (curr.state == ST_IDLE || curr.state == ST_DISCHARGE) {
-			curr.requested_voltage = 0;
-			curr.requested_current = 0;
-		}
-#endif
-
-		/* Apply external limits */
-		if (curr.requested_current > user_current_limit)
-			curr.requested_current = user_current_limit;
-
-		/* Round to valid values */
-		curr.requested_voltage =
-			charger_closest_voltage(curr.requested_voltage);
-		curr.requested_current =
-			charger_closest_current(curr.requested_current);
-
-		/* Charger only accpets request when AC is on. */
-		if (curr.ac) {
-			/*
-			 * Some batteries would wake up after cut-off if we keep
-			 * charging it. Thus, we only charge when AC is on and
-			 * battery is not cut off yet.
-			 */
-			if (battery_is_cut_off()) {
-				curr.requested_voltage = 0;
-				curr.requested_current = 0;
-			}
-			/*
-			 * As a safety feature, some chargers will stop
-			 * charging if we don't communicate with it frequently
-			 * enough. In manual mode, we'll just tell it what it
-			 * knows.
-			 */
-			else {
-				if (manual_voltage != -1)
-					curr.requested_voltage = manual_voltage;
-				if (manual_current != -1)
-					curr.requested_current = manual_current;
-			}
-		} else {
-#ifndef CONFIG_CHARGER_MAINTAIN_VBAT
-			curr.requested_voltage = charger_closest_voltage(
-				curr.batt.voltage + info->voltage_step);
-			curr.requested_current = -1;
-#endif
-#ifdef CONFIG_EC_EC_COMM_BATTERY_SERVER
-			/*
-			 * On EC-EC server, do not charge if curr.ac is 0: there
-			 * might still be some external power available but we
-			 * do not want to use it for charging.
-			 */
-			curr.requested_current = 0;
-#endif
-		}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-		charge_allocate_input_current_limit();
-#else
-		charge_request(curr.requested_voltage, curr.requested_current);
-#endif
-
-		/* How long to sleep? */
-		if (problems_exist)
-			/* If there are errors, don't wait very long. */
-			sleep_usec = CHARGE_POLL_PERIOD_SHORT;
-		else if (sleep_usec <= 0) {
-			/* default values depend on the state */
-			if (!curr.ac &&
-			    (curr.state == ST_IDLE ||
-			    curr.state == ST_DISCHARGE)) {
-#ifdef CONFIG_CHARGER_OTG
-				int output_current = curr.output_current;
-#else
-				int output_current = 0;
-#endif
-				/*
-				 * If AP is off and we do not provide power, we
-				 * can sleep a long time.
-				 */
-				if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-						     CHIPSET_STATE_ANY_SUSPEND)
-						&& output_current == 0)
-					sleep_usec =
-						CHARGE_POLL_PERIOD_VERY_LONG;
-				else
-					/* Discharging, not too urgent */
-					sleep_usec = CHARGE_POLL_PERIOD_LONG;
-			} else {
-				/* AC present, so pay closer attention */
-				sleep_usec = CHARGE_POLL_PERIOD_CHARGE;
-			}
-		}
-
-		if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
-			int is_pd_supply = charge_manager_get_supplier() ==
-					   CHARGE_SUPPLIER_PD;
-			int port = charge_manager_get_active_charge_port();
-			int bat_spec_desired_mw = curr.batt.desired_current *
-						  curr.batt.desired_voltage /
-						  1000;
-
-			/*
-			 * save the previous plt_and_desired_mw, since it
-			 * will be updated below
-			 */
-			prev_plt_and_desired_mw =
-				charge_get_plt_plus_bat_desired_mw();
-
-			/*
-			 * Update desired power by the following rules:
-			 * 1. If the battery is not charging with PD, we reset
-			 * the desired_mw to the battery spec. The actual
-			 * desired_mw will be evaluated when it starts charging
-			 * with PD again.
-			 * 2. If the battery SoC under battery's constant
-			 * voltage percent (this is a rough value that can be
-			 * applied to most batteries), the battery can fully
-			 * sink the power, the desired power should be the
-			 * same as the battery spec, and we don't need to use
-			 * evaluated value stable_current.
-			 * 3. If the battery SoC is above battery's constant
-			 * voltage percent, the real battery desired charging
-			 * power will decrease slowly and so does the charging
-			 * current. We can evaluate the battery desired power
-			 * by the product of stable_current and battery voltage.
-			 */
-			if (!is_pd_supply)
-				desired_mw = bat_spec_desired_mw;
-			else if (curr.batt.state_of_charge < pd_pref_config.cv)
-				desired_mw = bat_spec_desired_mw;
-			else if (stable_current != CHARGE_CURRENT_UNINITIALIZED)
-				desired_mw = curr.batt.voltage *
-					     stable_current / 1000;
-
-			/* if the plt_and_desired_mw changes, re-evaluate PDO */
-			if (is_pd_supply &&
-			    prev_plt_and_desired_mw !=
-				    charge_get_plt_plus_bat_desired_mw())
-				pd_set_new_power_request(port);
-		}
-
-		/* Adjust for time spent in this loop */
-		sleep_usec -= (int)(get_time().val - curr.ts.val);
-		if (sleep_usec < CHARGE_MIN_SLEEP_USEC)
-			sleep_usec = CHARGE_MIN_SLEEP_USEC;
-		else if (sleep_usec > CHARGE_MAX_SLEEP_USEC)
-			sleep_usec = CHARGE_MAX_SLEEP_USEC;
-
-		/*
-		 * If battery is critical, ensure that the sleep time is not
-		 * very long since we might want to hibernate or cut-off
-		 * battery sooner.
-		 */
-		if (battery_critical &&
-		    (sleep_usec > CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US))
-			sleep_usec = CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
-
-		task_wait_event(sleep_usec);
-	}
-}
-
-
-/*****************************************************************************/
-/* Exported functions */
-
-int charge_want_shutdown(void)
-{
-	return (curr.state == ST_DISCHARGE) &&
-		!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		(curr.batt.state_of_charge < battery_level_shutdown);
-}
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	int prevent_power_on = 0;
-	struct batt_params params;
-	struct batt_params *current_batt_params = &curr.batt;
-#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-	static int automatic_power_on = 1;
-#endif
-
-	/* If battery params seem uninitialized then retrieve them */
-	if (current_batt_params->is_present == BP_NOT_SURE) {
-		battery_get_params(&params);
-		current_batt_params = &params;
-	}
-
-#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-
-	/*
-	 * Remember that a power button was pressed, and assume subsequent
-	 * power-ups are user-requested and non-automatic.
-	 */
-	if (power_button_pressed)
-		automatic_power_on = 0;
-	/*
-	 * Require a minimum battery level to power on and ensure that the
-	 * battery can provide power to the system.
-	 */
-	if (current_batt_params->is_present != BP_YES ||
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-	    (current_batt_params->flags & BATT_FLAG_IMBALANCED_CELL &&
-		current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) ||
-#endif
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED ||
-#endif
-	    current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
-		prevent_power_on = 1;
-
-#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) && \
-	defined(CONFIG_CHARGE_MANAGER)
-	/* However, we can power on if a sufficient charger is present. */
-	if (prevent_power_on) {
-		if (charge_manager_get_power_limit_uw() >=
-		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000)
-			prevent_power_on = 0;
-#if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT) && \
-	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)
-		else if (charge_manager_get_power_limit_uw() >=
-		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT * 1000
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-		    && battery_get_disconnect_state() ==
-							BATTERY_NOT_DISCONNECTED
-#endif
-		    && (current_batt_params->state_of_charge >=
-			CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC))
-			prevent_power_on = 0;
-#endif
-	}
-#endif /* CONFIG_CHARGE_MANAGER && CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
-
-	/*
-	 * Factory override: Always allow power on if WP is disabled,
-	 * except when auto-power-on at EC startup and the battery
-	 * is physically present.
-	 */
-	prevent_power_on &= (system_is_locked() || (automatic_power_on
-#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-				    && battery_hw_present() == BP_YES
-#endif
-				     ));
-#endif /* CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON */
-
-#ifdef CONFIG_CHARGE_MANAGER
-	/* Always prevent power on until charge current is initialized */
-	if (extpower_is_present() &&
-	    (charge_manager_get_charger_current() ==
-	     CHARGE_CURRENT_UNINITIALIZED))
-		prevent_power_on = 1;
-#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-	/*
-	 * If battery is NOT physically present then prevent power on until
-	 * a sufficient charger is present.
-	 */
-	if (extpower_is_present() && battery_hw_present() == BP_NO
-#ifdef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-	    && charge_manager_get_power_limit_uw() <
-		CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000
-#endif /* CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
-	    )
-		prevent_power_on = 1;
-#endif /* CONFIG_BATTERY_HW_PRESENT_CUSTOM */
-#endif /* CONFIG_CHARGE_MANAGER */
-
-	/*
-	 * Prevent power on if there is no battery nor ac power. This
-	 * happens when the servo is powering the EC to flash it. Only include
-	 * this logic for boards in initial bring up phase since this won't
-	 * happen for released boards.
-	 */
-#ifdef CONFIG_SYSTEM_UNLOCKED
-	if (!current_batt_params->is_present && !curr.ac)
-		prevent_power_on = 1;
-#endif /* CONFIG_SYSTEM_UNLOCKED */
-
-	return prevent_power_on;
-}
-
-static int battery_near_full(void)
-{
-	if (charge_get_percent() < BATTERY_LEVEL_NEAR_FULL)
-		return 0;
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	if (charge_base > -1 && charge_base < BATTERY_LEVEL_NEAR_FULL)
-		return 0;
-#endif
-
-	return 1;
-}
-
-enum charge_state charge_get_state(void)
-{
-	switch (curr.state) {
-	case ST_IDLE:
-		if (battery_seems_dead || curr.batt.is_present == BP_NO)
-			return PWR_STATE_ERROR;
-		return PWR_STATE_IDLE;
-	case ST_DISCHARGE:
-#ifdef CONFIG_PWR_STATE_DISCHARGE_FULL
-		if (battery_near_full())
-			return PWR_STATE_DISCHARGE_FULL;
-		else
-#endif
-			return PWR_STATE_DISCHARGE;
-	case ST_CHARGE:
-		/* The only difference here is what the LEDs display. */
-		if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
-		    charge_manager_get_active_charge_port() == CHARGE_PORT_NONE)
-			return PWR_STATE_DISCHARGE;
-		else if (battery_near_full())
-			return PWR_STATE_CHARGE_NEAR_FULL;
-		else
-			return PWR_STATE_CHARGE;
-	case ST_PRECHARGE:
-		/* we're in battery discovery mode */
-		return PWR_STATE_IDLE;
-	default:
-		/* Anything else can be considered an error for LED purposes */
-		return PWR_STATE_ERROR;
-	}
-}
-
-uint32_t charge_get_flags(void)
-{
-	uint32_t flags = 0;
-
-	if (get_chg_ctrl_mode() != CHARGE_CONTROL_NORMAL)
-		flags |= CHARGE_FLAG_FORCE_IDLE;
-	if (curr.ac)
-		flags |= CHARGE_FLAG_EXTERNAL_POWER;
-	if (curr.batt.flags & BATT_FLAG_RESPONSIVE)
-		flags |= CHARGE_FLAG_BATT_RESPONSIVE;
-
-	return flags;
-}
-
-int charge_get_percent(void)
-{
-	/*
-	 * Since there's no way to indicate an error to the caller, we'll just
-	 * return the last known value. Even if we've never been able to talk
-	 * to the battery, that'll be zero, which is probably as good as
-	 * anything.
-	 */
-	return is_full ? 100 : curr.batt.state_of_charge;
-}
-
-test_mockable int charge_get_display_charge(void)
-{
-	return curr.batt.display_charge;
-}
-
-int charge_get_battery_temp(int idx, int *temp_ptr)
-{
-	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
-		return EC_ERROR_UNKNOWN;
-
-	/* Battery temp is 10ths of degrees K, temp wants degrees K */
-	*temp_ptr = curr.batt.temperature / 10;
-	return EC_SUCCESS;
-}
-
-__overridable int charge_is_consuming_full_input_current(void)
-{
-	int chg_pct = charge_get_percent();
-
-	return chg_pct > 2 && chg_pct < 95;
-}
-
-#ifdef CONFIG_CHARGER_OTG
-int charge_set_output_current_limit(int chgnum, int ma, int mv)
-{
-	int ret;
-	int enable = ma > 0;
-
-	if (enable) {
-		ret = charger_set_otg_current_voltage(chgnum, ma, mv);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	ret = charger_enable_otg_power(chgnum, enable);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* If we start/stop providing power, wake the charger task. */
-	if ((curr.output_current == 0 && enable) ||
-	    (curr.output_current > 0 && !enable))
-		task_wake(TASK_ID_CHARGER);
-
-	curr.output_current = ma;
-
-	return EC_SUCCESS;
-}
-#endif
-
-int charge_set_input_current_limit(int ma, int mv)
-{
-	__maybe_unused int chgnum = 0;
-
-	if (IS_ENABLED(CONFIG_OCPC))
-		chgnum = charge_get_active_chg_chip();
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	curr.input_voltage = mv;
-#endif
-	/*
-	 * If battery is not present, we are not locked, and base is not
-	 * connected then allow system to pull as much input current as needed.
-	 * Yes, we might overcurrent the charger but this is no worse than
-	 * browning out due to insufficient input current.
-	 */
-	if (curr.batt.is_present != BP_YES && !system_is_locked() &&
-		!base_connected) {
-
-		int prev_input = 0;
-
-		charger_get_input_current_limit(chgnum, &prev_input);
-
-#ifdef CONFIG_USB_POWER_DELIVERY
-#if ((PD_MAX_POWER_MW * 1000) / PD_MAX_VOLTAGE_MV != PD_MAX_CURRENT_MA)
-		/*
-		 * If battery is not present, input current is set to
-		 * PD_MAX_CURRENT_MA. If the input power set is greater than
-		 * the maximum allowed system power, system might get damaged.
-		 * Hence, limit the input current to meet maximum allowed
-		 * input system power.
-		 */
-
-		if (mv > 0 && mv * curr.desired_input_current >
-			PD_MAX_POWER_MW * 1000)
-			ma = (PD_MAX_POWER_MW * 1000) / mv;
-		/*
-		 * If the active charger has already been initialized to at
-		 * least this current level, nothing left to do.
-		 */
-		else if (prev_input >= ma)
-			return EC_SUCCESS;
-#else
-		if (prev_input >= ma)
-			return EC_SUCCESS;
-#endif
-		/*
-		 * If the current needs lowered due to PD max power
-		 * considerations, or needs raised for the selected active
-		 * charger chip, fall through to set.
-		 */
-#endif /* CONFIG_USB_POWER_DELIVERY */
-	}
-
-#ifdef CONFIG_CHARGER_MAX_INPUT_CURRENT
-	/* Limit input current limit to max limit for this board */
-	ma = MIN(ma, CONFIG_CHARGER_MAX_INPUT_CURRENT);
-#endif
-	curr.desired_input_current = ma;
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-	/* Wake up charger task to allocate current between lid and base. */
-	charge_wakeup();
-	return EC_SUCCESS;
-#else
-	return charger_set_input_current_limit(chgnum, ma);
-#endif
-}
-
-#ifdef CONFIG_OCPC
-void charge_set_active_chg_chip(int idx)
-{
-	ASSERT(idx < (int)board_get_charger_chip_count());
-
-	if (idx == curr.ocpc.active_chg_chip)
-		return;
-
-	CPRINTS("Act Chg: %d", idx);
-	curr.ocpc.active_chg_chip = idx;
-}
-#endif /* CONFIG_OCPC */
-
-int charge_get_active_chg_chip(void)
-{
-#ifdef CONFIG_OCPC
-	return curr.ocpc.active_chg_chip;
-#else
-	return 0;
-#endif
-}
-
-#ifdef CONFIG_USB_PD_PREFER_MV
-bool charge_is_current_stable(void)
-{
-	return get_time().val >= stable_ts.val;
-}
-
-int charge_get_plt_plus_bat_desired_mw(void)
-{
-	/*
-	 * Ideally, the system consuming power could be evaluated by
-	 * "IBus * VBus - battery charging power". But in practice,
-	 * most charger drivers don't implement IBUS ADC reading,
-	 * so we use system PLT instead as an alterntaive approach.
-	 */
-	return pd_pref_config.plt_mw + desired_mw;
-}
-
-int charge_get_stable_current(void)
-{
-	return stable_current;
-}
-
-void charge_set_stable_current(int ma)
-{
-	stable_current = ma;
-}
-
-void charge_reset_stable_current_us(uint64_t us)
-{
-	timestamp_t now = get_time();
-
-	if (stable_ts.val < now.val + us)
-		stable_ts.val = now.val + us;
-
-	stable_current = CHARGE_CURRENT_UNINITIALIZED;
-}
-
-void charge_reset_stable_current(void)
-{
-	/* it takes 8 to 10 seconds to stabilize battery current in practice */
-	charge_reset_stable_current_us(10 * SECOND);
-}
-#endif
-
-#ifdef CONFIG_OCPC
-void trigger_ocpc_reset(void)
-{
-	ocpc_reset(&curr.ocpc);
-}
-#endif
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-charge_command_charge_control(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_charge_control *p = args->params;
-	struct ec_response_charge_control *r = args->response;
-	int rv;
-
-	if (args->version >= 2) {
-		if (p->cmd == EC_CHARGE_CONTROL_CMD_SET) {
-			if (p->mode == CHARGE_CONTROL_NORMAL) {
-				rv = battery_sustainer_set(
-						p->sustain_soc.lower,
-						p->sustain_soc.upper);
-				if (rv == EC_RES_UNAVAILABLE)
-					return EC_RES_UNAVAILABLE;
-				if (rv)
-					return EC_RES_INVALID_PARAM;
-			} else {
-				battery_sustainer_disable();
-			}
-		} else if (p->cmd == EC_CHARGE_CONTROL_CMD_GET) {
-			r->mode = get_chg_ctrl_mode();
-			r->sustain_soc.lower = sustain_soc.lower;
-			r->sustain_soc.upper = sustain_soc.upper;
-			args->response_size = sizeof(*r);
-			return EC_RES_SUCCESS;
-		} else {
-			return EC_RES_INVALID_PARAM;
-		}
-	}
-
-	rv = set_chg_ctrl_mode(p->mode);
-	if (rv != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CONTROL, charge_command_charge_control,
-		     EC_VER_MASK(1) | EC_VER_MASK(2));
-
-static void reset_current_limit(void)
-{
-	user_current_limit = -1U;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, reset_current_limit, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, reset_current_limit, HOOK_PRIO_DEFAULT);
-
-static enum ec_status
-charge_command_current_limit(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_current_limit *p = args->params;
-
-	user_current_limit = p->limit;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_CURRENT_LIMIT, charge_command_current_limit,
-		     EC_VER_MASK(0));
-
-/*
- * Expose charge/battery related state
- *
- * @param param command to get corresponding data
- * @param value the corresponding data
- * @return EC_SUCCESS or error
- */
-static int charge_get_charge_state_debug(int param, uint32_t *value)
-{
-	switch (param) {
-	case CS_PARAM_DEBUG_CTL_MODE:
-		*value = get_chg_ctrl_mode();
-		break;
-	case CS_PARAM_DEBUG_MANUAL_CURRENT:
-		*value = manual_current;
-		break;
-	case CS_PARAM_DEBUG_MANUAL_VOLTAGE:
-		*value = manual_voltage;
-		break;
-	case CS_PARAM_DEBUG_SEEMS_DEAD:
-		*value = battery_seems_dead;
-		break;
-	case CS_PARAM_DEBUG_SEEMS_DISCONNECTED:
-		*value = battery_seems_disconnected;
-		break;
-	case CS_PARAM_DEBUG_BATT_REMOVED:
-		*value = battery_was_removed;
-		break;
-	default:
-		*value = 0;
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static enum ec_status
-charge_command_charge_state(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_charge_state *in = args->params;
-	struct ec_response_charge_state *out = args->response;
-	uint32_t val;
-	int rv = EC_RES_SUCCESS;
-	int chgnum = 0;
-
-	if (args->version > 0)
-		chgnum = in->chgnum;
-
-	switch (in->cmd) {
-
-	case CHARGE_STATE_CMD_GET_STATE:
-		out->get_state.ac = curr.ac;
-		out->get_state.chg_voltage = curr.chg.voltage;
-		out->get_state.chg_current = curr.chg.current;
-		out->get_state.chg_input_current = curr.chg.input_current;
-		out->get_state.batt_state_of_charge = curr.batt.state_of_charge;
-		args->response_size = sizeof(out->get_state);
-		break;
-
-	case CHARGE_STATE_CMD_GET_PARAM:
-		val = 0;
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN
-			&& in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
-			/* custom profile params */
-			rv  = charger_profile_override_get_param(
-				in->get_param.param, &val);
-		} else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG)
-			&& in->get_param.param >= CS_PARAM_DEBUG_MIN
-			&& in->get_param.param <= CS_PARAM_DEBUG_MAX) {
-			/* debug params */
-			rv = charge_get_charge_state_debug(
-				in->get_param.param, &val);
-		} else {
-			/* standard params */
-			switch (in->get_param.param) {
-			case CS_PARAM_CHG_VOLTAGE:
-				val = curr.chg.voltage;
-				break;
-			case CS_PARAM_CHG_CURRENT:
-				val = curr.chg.current;
-				break;
-			case CS_PARAM_CHG_INPUT_CURRENT:
-				val = curr.chg.input_current;
-				break;
-			case CS_PARAM_CHG_STATUS:
-				val = curr.chg.status;
-				break;
-			case CS_PARAM_CHG_OPTION:
-				val = curr.chg.option;
-				break;
-			case CS_PARAM_LIMIT_POWER:
-#ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-				/*
-				 * LIMIT_POWER status is based on battery level
-				 * and external charger power.
-				 */
-				if ((curr.batt.is_present != BP_YES ||
-				     curr.batt.state_of_charge <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT)
-				     && charge_manager_get_power_limit_uw() <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-				     * 1000 && system_is_locked())
-					val = 1;
-				else
-#endif
-					val = 0;
-				break;
-			default:
-				rv = EC_RES_INVALID_PARAM;
-			}
-		}
-
-		/* got something */
-		out->get_param.value = val;
-		args->response_size = sizeof(out->get_param);
-		break;
-
-	case CHARGE_STATE_CMD_SET_PARAM:
-		if (system_is_locked())
-			return EC_RES_ACCESS_DENIED;
-
-		val = in->set_param.value;
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN
-			&& in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
-			/* custom profile params */
-			rv  = charger_profile_override_set_param(
-				in->set_param.param, val);
-		} else {
-			switch (in->set_param.param) {
-			case CS_PARAM_CHG_VOLTAGE:
-				chgstate_set_manual_voltage(val);
-				break;
-			case CS_PARAM_CHG_CURRENT:
-				chgstate_set_manual_current(val);
-				break;
-			case CS_PARAM_CHG_INPUT_CURRENT:
-				if (charger_set_input_current_limit(chgnum,
-								    val))
-					rv = EC_RES_ERROR;
-				break;
-			case CS_PARAM_CHG_STATUS:
-			case CS_PARAM_LIMIT_POWER:
-				/* Can't set this */
-				rv = EC_RES_ACCESS_DENIED;
-				break;
-			case CS_PARAM_CHG_OPTION:
-				if (charger_set_option(val))
-					rv = EC_RES_ERROR;
-				break;
-			default:
-				rv = EC_RES_INVALID_PARAM;
-
-			}
-		}
-		break;
-
-	default:
-		CPRINTS("EC_CMD_CHARGE_STATE: bad cmd 0x%x", in->cmd);
-		rv = EC_RES_INVALID_PARAM;
-	}
-
-	return rv;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_STATE, charge_command_charge_state,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_PWR_AVG
-
-static int command_pwr_avg(int argc, char **argv)
-{
-	int avg_mv;
-	int avg_ma;
-	int avg_mw;
-
-	if (argc != 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	avg_mv = battery_get_avg_voltage();
-	if (avg_mv < 0)
-		return EC_ERROR_UNKNOWN;
-	avg_ma = battery_get_avg_current();
-	avg_mw = avg_mv * avg_ma / 1000;
-
-	ccprintf("mv = %d\nma = %d\nmw = %d\n",
-		avg_mv, avg_ma, avg_mw);
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg,
-			NULL,
-			"Get 1 min power average");
-
-#endif /* CONFIG_CMD_PWR_AVG */
-
-static int command_chgstate(int argc, char **argv)
-{
-	int rv;
-	int val;
-	char *e;
-
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "idle")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &val))
-				return EC_ERROR_PARAM2;
-			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_IDLE :
-						CHARGE_CONTROL_NORMAL);
-			if (rv)
-				return rv;
-		} else if (!strcasecmp(argv[1], "discharge")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &val))
-				return EC_ERROR_PARAM2;
-			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_DISCHARGE :
-						CHARGE_CONTROL_NORMAL);
-			if (rv)
-				return rv;
-		} else if (!strcasecmp(argv[1], "debug")) {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-			if (!parse_bool(argv[2], &debugging))
-				return EC_ERROR_PARAM2;
-		} else if (!strcasecmp(argv[1], "sustain")) {
-			int lower, upper;
-
-			if (argc <= 3)
-				return EC_ERROR_PARAM_COUNT;
-			lower = strtoi(argv[2], &e, 0);
-			if (*e)
-				return EC_ERROR_PARAM2;
-			upper = strtoi(argv[3], &e, 0);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			rv = battery_sustainer_set(lower, upper);
-			if (rv)
-				return EC_ERROR_INVAL;
-		} else {
-			return EC_ERROR_PARAM1;
-		}
-	}
-
-	dump_charge_state();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chgstate, command_chgstate,
-			"[idle|discharge|debug on|off]"
-			"\n[sustain <lower> <upper>]",
-			"Get/set charge state machine status");
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-static int command_chgdualdebug(int argc, char **argv)
-{
-	int val;
-	char *e;
-
-	if (argc > 1) {
-		if (argv[1][0] == 'c') {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-
-			if (!strcasecmp(argv[2], "auto")) {
-				val = -1;
-			} else {
-				val = strtoi(argv[2], &e, 0);
-				if (*e || val < 0)
-					return EC_ERROR_PARAM2;
-			}
-
-			manual_ac_current_base = val;
-			charge_wakeup();
-		} else if (argv[1][0] == 'd') {
-			if (argc <= 2)
-				return EC_ERROR_PARAM_COUNT;
-
-			if (!strcasecmp(argv[2], "auto")) {
-				manual_noac_enabled = 0;
-			} else {
-				val = strtoi(argv[2], &e, 0);
-				if (*e)
-					return EC_ERROR_PARAM2;
-				manual_noac_current_base = val;
-				manual_noac_enabled = 1;
-			}
-			charge_wakeup();
-		} else {
-			return EC_ERROR_PARAM1;
-		}
-	} else {
-		ccprintf("Base/Lid: %d%s/%d mA\n",
-			 prev_current_base, prev_allow_charge_base ? "+" : "",
-			 prev_current_lid);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(chgdualdebug, command_chgdualdebug,
-			"[charge (auto|<current>)|discharge (auto|<current>)]",
-			"Manually control dual-battery charging algorithm.");
-#endif
diff --git a/common/charger.c b/common/charger.c
deleted file mode 100644
index 764f8b7ba7..0000000000
--- a/common/charger.c
+++ /dev/null
@@ -1,712 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for battery charging.
- */
-
-#include "battery_smart.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "dptf.h"
-#include "host_command.h"
-#include "printf.h"
-#include "util.h"
-#include "hooks.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* DPTF current limit, -1 = none */
-static int dptf_limit_ma = -1;
-
-void dptf_set_charging_current_limit(int ma)
-{
-	dptf_limit_ma = ma >= 0 ? ma : -1;
-}
-
-int dptf_get_charging_current_limit(void)
-{
-	return dptf_limit_ma;
-}
-
-static void dptf_disable_hook(void)
-{
-	/* Before get to Sx, EC should take control of charger from DPTF */
-	dptf_limit_ma = -1;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, dptf_disable_hook, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, dptf_disable_hook, HOOK_PRIO_DEFAULT);
-
-/*
- * Boards should override this function if their count may vary during run-time
- * due to different DB options.
- */
-__overridable uint8_t board_get_charger_chip_count(void)
-{
-	return CHARGER_NUM;
-}
-
-int charger_closest_voltage(int voltage)
-{
-	const struct charger_info *info = charger_get_info();
-
-	/*
-	 * If the requested voltage is non-zero but below our minimum,
-	 * return the minimum.  See crosbug.com/p/8662.
-	 */
-	if (voltage > 0 && voltage < info->voltage_min)
-		return info->voltage_min;
-
-	/* Clip to max */
-	if (voltage > info->voltage_max)
-		return info->voltage_max;
-
-	/* Otherwise round down to nearest voltage step */
-	return voltage - (voltage % info->voltage_step);
-}
-
-int charger_closest_current(int current)
-{
-	const struct charger_info * const info = charger_get_info();
-
-	/* Apply DPTF limit if necessary */
-	if (dptf_limit_ma >= 0 && current > dptf_limit_ma)
-		current = dptf_limit_ma;
-
-	/*
-	 * If the requested current is non-zero but below our minimum,
-	 * return the minimum.  See crosbug.com/p/8662.
-	 */
-	if (current > 0 && current < info->current_min)
-		return info->current_min;
-
-	/* Clip to max */
-	if (current > info->current_max)
-		return info->current_max;
-
-	/* Otherwise round down to nearest current step */
-	return current - (current % info->current_step);
-}
-
-void charger_get_params(struct charger_params *chg)
-{
-	int chgnum = 0;
-
-	if (IS_ENABLED(CONFIG_OCPC))
-		chgnum = charge_get_active_chg_chip();
-
-	memset(chg, 0, sizeof(*chg));
-
-	/*
-	 * Only the primary charger(0) can tightly regulate the current,
-	 * therefore always query the primary charger.
-	 */
-	if (charger_get_current(0, &chg->current))
-		chg->flags |= CHG_FLAG_BAD_CURRENT;
-
-	if (charger_get_voltage(chgnum, &chg->voltage))
-		chg->flags |= CHG_FLAG_BAD_VOLTAGE;
-
-	if (charger_get_input_current_limit(chgnum, &chg->input_current))
-		chg->flags |= CHG_FLAG_BAD_INPUT_CURRENT;
-
-	if (charger_get_status(&chg->status))
-		chg->flags |= CHG_FLAG_BAD_STATUS;
-
-	if (charger_get_option(&chg->option))
-		chg->flags |= CHG_FLAG_BAD_OPTION;
-}
-
-static void print_item_name(const char *name)
-{
-	ccprintf("  %-8s", name);
-}
-
-static int check_print_error(int rv)
-{
-	if (rv == EC_SUCCESS)
-		return 1;
-	ccputs(rv == EC_ERROR_UNIMPLEMENTED ? "(unsupported)\n" : "(error)\n");
-	return 0;
-}
-
-void print_charger_debug(int chgnum)
-{
-	int d;
-	const struct charger_info *info = charger_get_info();
-
-	/* info */
-	print_item_name("Name:");
-	ccprintf("%s\n", info->name);
-
-	/* option */
-	print_item_name("Option:");
-	if (check_print_error(charger_get_option(&d)))
-		ccprintf("%pb (0x%04x)\n", BINARY_VALUE(d, 16), d);
-
-	/* manufacturer id */
-	print_item_name("Man id:");
-	if (check_print_error(charger_manufacturer_id(&d)))
-		ccprintf("0x%04x\n", d);
-
-	/* device id */
-	print_item_name("Dev id:");
-	if (check_print_error(charger_device_id(&d)))
-		ccprintf("0x%04x\n", d);
-
-	/* charge voltage limit */
-	print_item_name("V_batt:");
-	if (check_print_error(charger_get_voltage(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->voltage_min,
-			 info->voltage_max, info->voltage_step);
-
-	/* charge current limit */
-	print_item_name("I_batt:");
-	if (check_print_error(charger_get_current(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->current_min,
-			 info->current_max, info->current_step);
-
-	/* input current limit */
-	print_item_name("I_in:");
-	if (check_print_error(charger_get_input_current_limit(chgnum, &d)))
-		ccprintf("%5d (%4d - %5d, %3d)\n", d, info->input_current_min,
-			 info->input_current_max, info->input_current_step);
-
-	/* dptf current limit */
-	print_item_name("I_dptf:");
-	if (dptf_limit_ma >= 0)
-		ccprintf("%5d\n", dptf_limit_ma);
-	else
-		ccputs("disabled\n");
-}
-
-static int command_charger(int argc, char **argv)
-{
-	int d;
-	char *e;
-	int idx_provided = 0;
-	int chgnum;
-
-	if (argc == 1) {
-		print_charger_debug(0);
-		return EC_SUCCESS;
-	}
-
-	idx_provided = isdigit((unsigned char)argv[1][0]);
-	if (idx_provided)
-		chgnum = atoi(argv[1]);
-	else
-		chgnum = 0;
-
-	if ((argc == 2) && idx_provided) {
-		print_charger_debug(chgnum);
-		return EC_SUCCESS;
-	}
-
-	if (strcasecmp(argv[1+idx_provided], "input") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
-		return charger_set_input_current_limit(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "current") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
-		chgstate_set_manual_current(d);
-		return charger_set_current(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "voltage") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
-		chgstate_set_manual_voltage(d);
-		return charger_set_voltage(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "dptf") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
-		dptf_limit_ma = d;
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_PARAM1+idx_provided;
-	}
-}
-
-DECLARE_CONSOLE_COMMAND(charger, command_charger,
-			"[chgnum] [input | current | voltage | dptf] [newval]",
-			"Get or set charger param(s)");
-
-/* Driver wrapper functions */
-
-static void charger_chips_init(void)
-{
-	int chip;
-
-	for (chip = 0; chip < board_get_charger_chip_count(); chip++) {
-		if (chg_chips[chip].drv->init)
-			chg_chips[chip].drv->init(chip);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, charger_chips_init, HOOK_PRIO_INIT_I2C + 1);
-
-enum ec_error_list charger_post_init(void)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->post_init)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->post_init(chgnum);
-}
-
-const struct charger_info *charger_get_info(void)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return NULL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_info)
-		return NULL;
-
-	return chg_chips[chgnum].drv->get_info(chgnum);
-}
-
-enum ec_error_list charger_get_status(int *status)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_status)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_status(chgnum, status);
-}
-
-enum ec_error_list charger_set_mode(int mode)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_mode)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_mode(chgnum, mode);
-}
-
-enum ec_error_list charger_enable_otg_power(int chgnum, int enabled)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->enable_otg_power)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->enable_otg_power(chgnum, enabled);
-}
-
-enum ec_error_list charger_set_otg_current_voltage(int chgnum,
-						   int output_current,
-						   int output_voltage)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_otg_current_voltage)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_otg_current_voltage(
-		chgnum, output_current, output_voltage);
-}
-
-int charger_is_sourcing_otg_power(int port)
-{
-	int chgnum = 0;
-
-	if (IS_ENABLED(CONFIG_OCPC))
-		chgnum = port;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
-	}
-
-	if (!chg_chips[chgnum].drv->is_sourcing_otg_power)
-		return 0;
-
-	return chg_chips[chgnum].drv->is_sourcing_otg_power(chgnum, port);
-}
-
-enum ec_error_list charger_get_actual_current(int chgnum, int *current)
-{
-	/* Note: chgnum may be -1 if no active port is selected */
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_actual_current)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_actual_current(chgnum, current);
-}
-
-enum ec_error_list charger_get_current(int chgnum, int *current)
-{
-	/* Note: chgnum may be -1 if no active port is selected */
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_current)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_current(chgnum, current);
-}
-
-enum ec_error_list charger_set_current(int chgnum, int current)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_current)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_current(chgnum, current);
-}
-
-enum ec_error_list charger_get_actual_voltage(int chgnum, int *voltage)
-{
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_actual_voltage)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_actual_voltage(chgnum, voltage);
-}
-
-enum ec_error_list charger_get_voltage(int chgnum, int *voltage)
-{
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_voltage)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_voltage(chgnum, voltage);
-}
-
-enum ec_error_list charger_set_voltage(int chgnum, int voltage)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_voltage)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_voltage(chgnum, voltage);
-}
-
-enum ec_error_list charger_discharge_on_ac(int enable)
-{
-	int chgnum;
-	int rv = EC_ERROR_UNIMPLEMENTED;
-
-	if (IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM))
-		return board_discharge_on_ac(enable);
-
-	/*
-	 * When discharge on AC is selected, cycle through all chargers to
-	 * enable or disable this feature.
-	 */
-	for (chgnum = 0; chgnum < board_get_charger_chip_count(); chgnum++) {
-		if (chg_chips[chgnum].drv->discharge_on_ac)
-			rv = chg_chips[chgnum].drv->discharge_on_ac(chgnum,
-								    enable);
-	}
-
-	return rv;
-}
-
-enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
-{
-	int chgnum = 0;
-
-	/* Note: Assumes USBPD port == chgnum on multi-charger systems */
-	if (!IS_ENABLED(CONFIG_CHARGER_SINGLE_CHIP))
-		chgnum = port;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
-	}
-
-	if (!chg_chips[chgnum].drv->get_vbus_voltage)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_vbus_voltage(chgnum, port, voltage);
-}
-
-enum ec_error_list charger_set_input_current_limit(int chgnum,
-						   int input_current)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_input_current_limit)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_input_current_limit(chgnum,
-							      input_current);
-}
-
-enum ec_error_list charger_get_input_current_limit(int chgnum,
-						   int *input_current)
-{
-	/* Note: may be called with CHARGE_PORT_NONE regularly */
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_input_current_limit)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_input_current_limit(chgnum,
-							      input_current);
-}
-
-enum ec_error_list charger_get_input_current(int chgnum, int *input_current)
-{
-	if (chgnum < 0)
-		return EC_ERROR_INVAL;
-
-	if (chgnum >= board_get_charger_chip_count()) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_input_current)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_input_current(chgnum, input_current);
-}
-
-enum ec_error_list charger_manufacturer_id(int *id)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->manufacturer_id)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->manufacturer_id(chgnum, id);
-}
-
-enum ec_error_list charger_device_id(int *id)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->device_id)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->device_id(chgnum, id);
-}
-
-enum ec_error_list charger_get_option(int *option)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->get_option)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->get_option(chgnum, option);
-}
-
-enum ec_error_list charger_set_option(int option)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_option)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_option(chgnum, option);
-}
-
-enum ec_error_list charger_set_hw_ramp(int enable)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (!chg_chips[chgnum].drv->set_hw_ramp)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_hw_ramp(chgnum, enable);
-}
-
-#ifdef CONFIG_CHARGE_RAMP_HW
-int chg_ramp_is_stable(void)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
-	}
-
-	if (!chg_chips[chgnum].drv->ramp_is_stable)
-		return 0;
-
-	return chg_chips[chgnum].drv->ramp_is_stable(chgnum);
-}
-
-int chg_ramp_is_detected(void)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
-	}
-
-	if (!chg_chips[chgnum].drv->ramp_is_detected)
-		return 0;
-
-	return chg_chips[chgnum].drv->ramp_is_detected(chgnum);
-}
-
-int chg_ramp_get_current_limit(void)
-{
-	int chgnum = 0;
-
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
-	}
-
-	if (!chg_chips[chgnum].drv->ramp_get_current_limit)
-		return 0;
-
-	return chg_chips[chgnum].drv->ramp_get_current_limit(chgnum);
-}
-#endif
-
-enum ec_error_list charger_set_vsys_compensation(int chgnum,
-						 struct ocpc_data *ocpc,
-						 int current_ma,
-						 int voltage_mv)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * This shouldn't happen as this should only be called on chargers
-	 * that support this.
-	 */
-	if (!chg_chips[chgnum].drv->set_vsys_compensation)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return chg_chips[chgnum].drv->set_vsys_compensation(
-		chgnum, ocpc, current_ma, voltage_mv);
-}
-
-enum ec_error_list charger_is_icl_reached(int chgnum, bool *reached)
-{
-		if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (chg_chips[chgnum].drv->is_icl_reached)
-		return chg_chips[chgnum].drv->is_icl_reached(chgnum, reached);
-
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable)
-{
-	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
-		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	if (chg_chips[chgnum].drv->enable_linear_charge)
-		return chg_chips[chgnum].drv->enable_linear_charge(chgnum,
-								   enable);
-
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/common/charger_profile_override.c b/common/charger_profile_override.c
deleted file mode 100644
index 2b691b9a5a..0000000000
--- a/common/charger_profile_override.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Charger profile override for fast charging
- */
-
-#include "charger_profile_override.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "util.h"
-
-#ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-static int fast_charge_test_on;
-static int test_flag_temp;
-static int test_flag_vtg;
-static int test_temp_c;
-static int test_vtg_mV = -1;
-#endif
-
-static int fast_charging_allowed = 1;
-
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max)
-{
-	int i, voltage_range;
-	/* temp in 0.1 deg C */
-	int temp_c = curr->batt.temperature - 2731;
-	int temp_ranges = fast_chg_params->total_temp_ranges;
-	const struct fast_charge_profile *chg_profile_info =
-				fast_chg_params->chg_profile_info;
-
-#ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-	if (fast_charge_test_on && test_vtg_mV != -1) {
-		temp_c = TEMPC_TENTHS_OF_DEG(test_temp_c);
-		curr->batt.voltage = test_vtg_mV;
-
-		if (test_flag_temp)
-			curr->batt.flags |= BATT_FLAG_BAD_TEMPERATURE;
-		else
-			curr->batt.flags &= BATT_FLAG_BAD_TEMPERATURE;
-
-		if (test_flag_vtg)
-			curr->batt.flags |= BATT_FLAG_BAD_VOLTAGE;
-		else
-			curr->batt.flags &= BATT_FLAG_BAD_VOLTAGE;
-	}
-#endif
-
-	/*
-	 * Determine temperature range.
-	 * If temp reading was bad, use last range.
-	 */
-	if (!(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) {
-		while (chg_profile_info && temp_ranges) {
-			if (temp_c <= chg_profile_info->temp_c) {
-				*prev_chg_prof_info = chg_profile_info;
-				break;
-			}
-			chg_profile_info++;
-			temp_ranges--;
-		}
-
-		/* Invalid charge profile selected */
-		if (!chg_profile_info || !temp_ranges)
-			return -1;
-	}
-
-	/*
-	 * If the battery voltage reading is bad or the battery voltage is
-	 * greater than or equal to the lower limit or the battery voltage is
-	 * not in the charger profile voltage range, consider battery has high
-	 * voltage range so that we charge at lower current limit.
-	 */
-	voltage_range = CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES - 1;
-
-	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) {
-		for (i = 0; i < CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES - 1;
-			i++) {
-			if (curr->batt.voltage <
-					fast_chg_params->voltage_mV[i]) {
-				voltage_range = i;
-				break;
-			}
-		}
-	}
-
-	/*
-	 * If we are not charging or we aren't using fast charging profiles,
-	 * then do not override desired current and voltage.
-	 */
-	if (curr->state != ST_CHARGE || !fast_charging_allowed)
-		return 0;
-
-	/*
-	 * Okay, impose our custom will:
-	 */
-	curr->requested_current =
-			(*prev_chg_prof_info)->current_mA[voltage_range];
-	curr->requested_voltage = curr->requested_current ? batt_vtg_max : 0;
-
-#ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-	if (fast_charge_test_on)
-		ccprintf("Fast charge profile i=%dmA, v=%dmV\n",
-			curr->requested_current, curr->requested_voltage);
-#endif
-
-	return 0;
-}
-
-/* Customs options controllable by host command. */
-#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		*value = fast_charging_allowed;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	if (param == PARAM_FASTCHARGE) {
-		fast_charging_allowed = value;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-#ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-static int command_fastcharge(int argc, char **argv)
-{
-	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
-		return EC_ERROR_PARAM1;
-
-	ccprintf("fastcharge %s\n", fast_charging_allowed ? "on" : "off");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
-			"Get or set fast charging profile");
-#endif
-
-/*
- * Manipulate the temperature and voltage values and check if the correct
- * fast charging profile is selected.
- */
-#ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-static int command_fastcharge_test(int argc, char **argv)
-{
-	char *e;
-	int test_on;
-
-	if (argc > 1 && !parse_bool(argv[1], &test_on))
-		return EC_ERROR_PARAM2;
-
-	/* Check if only tuurn printf message on / off */
-	if (argc == 2) {
-		fast_charge_test_on = test_on;
-		test_vtg_mV = -1;
-
-		return EC_SUCCESS;
-	}
-
-	/* Validate the input parameters */
-	if ((test_on && argc != 6) || !test_on)
-		return EC_ERROR_PARAM_COUNT;
-
-	test_flag_temp = strtoi(argv[2], &e, 0);
-	if (*e || test_flag_temp > 1 || test_flag_temp < 0)
-		return EC_ERROR_PARAM3;
-
-	test_flag_vtg = strtoi(argv[3], &e, 0);
-	if (*e || test_flag_vtg > 1 || test_flag_vtg < 0)
-		return EC_ERROR_PARAM4;
-
-	test_temp_c = strtoi(argv[4], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM5;
-
-	test_vtg_mV = strtoi(argv[5], &e, 0);
-	if (*e || test_vtg_mV < 0) {
-		test_vtg_mV = -1;
-		return EC_ERROR_PARAM6;
-	}
-
-	fast_charge_test_on = 1;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fastchgtest, command_fastcharge_test,
-			"off | on tempflag[1|0] vtgflag[1|0] temp_c vtg_mV",
-			"Check if fastcharge profile works");
-#endif
diff --git a/common/clz.c b/common/clz.c
deleted file mode 100644
index b0b58e76a0..0000000000
--- a/common/clz.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Software emulation for CLZ instruction
- */
-
-#include "common.h"
-
-/**
- * Count leading zeros
- *
- * @param x non null integer.
- * @return the number of leading 0-bits in x,
- * starting at the most significant bit position.
- */
-int __keep __clzsi2(int x)
-{
-	int r = 0;
-
-	if (!x)
-		return 32;
-	if (!(x & 0xffff0000u)) {
-		x <<= 16;
-		r += 16;
-	}
-	if (!(x & 0xff000000u)) {
-		x <<= 8;
-		r += 8;
-	}
-	if (!(x & 0xf0000000u)) {
-		x <<= 4;
-		r += 4;
-	}
-	if (!(x & 0xc0000000u)) {
-		x <<= 2;
-		r += 2;
-	}
-	if (!(x & 0x80000000u)) {
-		x <<= 1;
-		r += 1;
-	}
-	return r;
-}
diff --git a/common/crc.c b/common/crc.c
deleted file mode 100644
index 8b45150b67..0000000000
--- a/common/crc.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* CRC-32 implementation with USB constants */
-
-#include "common.h"
-
-/* Constants matching USB3 and USB PD definitions */
-#define CRC32_INITIAL 0xFFFFFFFF
-
-/* Pre-computed values for polynom 0x04C11DB7 */
-static const uint32_t crc32_tab[] = {
-	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
-	0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
-	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
-	0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
-	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
-	0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
-	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
-	0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
-	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
-	0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
-	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
-	0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
-	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
-	0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
-	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
-	0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
-	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
-	0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
-	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
-	0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
-	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
-	0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
-	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
-	0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
-	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
-	0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
-	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
-	0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
-	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
-	0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
-	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
-	0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
-	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
-	0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
-	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
-	0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
-	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
-	0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
-	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
-	0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
-	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
-	0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
-	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
-};
-
-static uint32_t _crc32_hash(uint32_t crc, const void *buf, int size)
-{
-	const uint8_t *p;
-
-	p = (const uint8_t *)buf;
-
-	while (size--) {
-		crc ^= *p++;
-		crc = crc32_tab[crc & 0xFF] ^ (crc >> 8);
-	}
-
-	return crc;
-}
-
-void crc32_ctx_init(uint32_t *crc)
-{
-	*crc = CRC32_INITIAL;
-}
-
-void crc32_ctx_hash(uint32_t *crc, const void *buf, int size)
-{
-	*crc = _crc32_hash(*crc, buf, size);
-}
-
-void crc32_ctx_hash32(uint32_t *crc, uint32_t val)
-{
-	*crc = _crc32_hash(*crc, &val, sizeof(val));
-}
-
-void crc32_ctx_hash16(uint32_t *crc, uint16_t val)
-{
-	*crc = _crc32_hash(*crc, &val, sizeof(val));
-}
-
-void crc32_ctx_hash8(uint32_t *crc, uint8_t val)
-{
-	*crc = _crc32_hash(*crc, &val, sizeof(val));
-}
-
-uint32_t crc32_ctx_result(uint32_t *crc)
-{
-	return *crc ^ 0xFFFFFFFF;
-}
-
-/* Accumulator for the CRC */
-static uint32_t crc_;
-
-void crc32_init(void)
-{
-	crc32_ctx_init(&crc_);
-}
-
-void crc32_hash(const void *buf, int size)
-{
-	crc32_ctx_hash(&crc_, buf, size);
-}
-
-void crc32_hash32(uint32_t val)
-{
-	crc32_ctx_hash32(&crc_, val);
-}
-
-void crc32_hash16(uint16_t val)
-{
-	crc32_ctx_hash16(&crc_, val);
-}
-
-uint32_t crc32_result(void)
-{
-	return crc32_ctx_result(&crc_);
-}
diff --git a/common/crc8.c b/common/crc8.c
deleted file mode 100644
index 8098fa74eb..0000000000
--- a/common/crc8.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "common.h"
-#include "crc8.h"
-
-inline uint8_t cros_crc8(const uint8_t *data, int len)
-{
-	return cros_crc8_arg(data, len, 0);
-}
-
-uint8_t cros_crc8_arg(const uint8_t *data, int len, uint8_t previous_crc)
-{
-	unsigned crc = previous_crc << 8;
-	int i, j;
-
-	for (j = len; j; j--, data++) {
-		crc ^= (*data << 8);
-		for (i = 8; i; i--) {
-			if (crc & 0x8000)
-				crc ^= (0x1070 << 3);
-			crc <<= 1;
-		}
-	}
-
-	return (uint8_t)(crc >> 8);
-}
diff --git a/common/ctz.c b/common/ctz.c
deleted file mode 100644
index bb6f69624e..0000000000
--- a/common/ctz.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Software emulation for CTZ instruction
- */
-
-#include "common.h"
-
-/**
- * Count trailing zeros
- *
- * @param x non null integer.
- * @return the number of trailing 0-bits in x,
- * starting at the least significant bit position.
- *
- * Using a de Brujin sequence, as documented here:
- * http://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightMultLookup
- */
-int __keep __ctzsi2(int x)
-{
-	static const uint8_t MulDeBruijnBitPos[32] = {
-		0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
-		31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
-	};
-	return MulDeBruijnBitPos[((uint32_t)((x & -x) * 0x077CB531U)) >> 27];
-}
diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c
deleted file mode 120000
index 3218a877a2..0000000000
--- a/common/curve25519-generic.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/curve25519-generic.c
\ No newline at end of file
diff --git a/common/curve25519.c b/common/curve25519.c
deleted file mode 120000
index aa9bebe86e..0000000000
--- a/common/curve25519.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/common/curve25519.c
\ No newline at end of file
diff --git a/common/device_event.c b/common/device_event.c
deleted file mode 100644
index f7944ae930..0000000000
--- a/common/device_event.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Device event commands for Chrome EC */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "lpc.h"
-#include "mkbp_event.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_EVENTS, outstr)
-#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args)
-
-static uint32_t device_current_events;
-static uint32_t device_enabled_events;
-
-uint32_t device_get_current_events(void)
-{
-	return device_current_events;
-}
-
-static uint32_t device_get_and_clear_events(void)
-{
-	return atomic_clear(&device_current_events);
-}
-
-static uint32_t device_get_enabled_events(void)
-{
-	return device_enabled_events;
-}
-
-void device_set_events(uint32_t mask)
-{
-	/* Ignore events that are not enabled */
-	mask &= device_enabled_events;
-
-	if ((device_current_events & mask) != mask) {
-		CPRINTS("device event set 0x%08x", mask);
-	} else {
-		/*
-		 * We are here because there is no flag change (1->1, 0->0).
-		 * For 0->0, we shouldn't notify the host because the flag is
-		 * disabled. For 1->1, it's most likely redundant but we still
-		 * need to notify the host in case the host didn't have a
-		 * chance to read the flags. Otherwise, the flag would never be
-		 * consumed because the host would never be notified.
-		 */
-		if (!mask)
-			return;
-	}
-
-	atomic_or(&device_current_events, mask);
-
-	/* Signal host that a device event is pending */
-	host_set_single_event(EC_HOST_EVENT_DEVICE);
-}
-
-void device_clear_events(uint32_t mask)
-{
-	/* Only print if something's about to change */
-	if (device_current_events & mask)
-		CPRINTS("device event clear 0x%08x", mask);
-
-	atomic_clear_bits(&device_current_events, mask);
-}
-
-static void device_set_enabled_events(uint32_t mask)
-{
-	if ((device_enabled_events & mask) != mask)
-		CPRINTS("device enabled events set 0x%08x", mask);
-
-	device_enabled_events = mask;
-}
-
-void device_enable_event(enum ec_device_event event)
-{
-	atomic_or(&device_enabled_events, EC_DEVICE_EVENT_MASK(event));
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_DEVICE_EVENT
-static int command_device_event(int argc, char **argv)
-{
-	/* Handle sub-commands */
-	if (argc == 3) {
-		char *e;
-		int i = strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-		else if (!strcasecmp(argv[1], "set"))
-			device_set_events(i);
-		else if (!strcasecmp(argv[1], "clear"))
-			device_clear_events(i);
-		else if (!strcasecmp(argv[1], "enable"))
-			device_set_enabled_events(i);
-		else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Enabled Events:  0x%08x\n", device_get_enabled_events());
-	ccprintf("Current Events:  0x%08x\n", device_get_current_events());
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(deviceevent, command_device_event,
-			"[set | clear | enable] [mask]",
-			"Print / set device event state");
-#endif
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status device_event_cmd(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_device_event *p = args->params;
-	struct ec_response_device_event *r = args->response;
-
-	switch (p->param) {
-	case EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS:
-		r->event_mask = device_get_and_clear_events();
-		break;
-	case EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS:
-		r->event_mask = device_get_enabled_events();
-		break;
-	case EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS:
-		device_set_enabled_events(p->event_mask);
-		r->event_mask = device_get_enabled_events();
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_DEVICE_EVENT, device_event_cmd, EC_VER_MASK(0));
diff --git a/common/device_state.c b/common/device_state.c
deleted file mode 100644
index 0ba94d6115..0000000000
--- a/common/device_state.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "device_state.h"
-#include "hooks.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/**
- * Return text description for a state
- *
- * @param state		State
- * @return String describing that state
- */
-static const char *state_desc(enum device_state state)
-{
-	return state == DEVICE_STATE_ON ? "on" :
-			state == DEVICE_STATE_OFF ? "off" : "unknown";
-}
-
-enum device_state device_get_state(enum device_type device)
-{
-	return device_states[device].state;
-}
-
-int device_set_state(enum device_type device, enum device_state state)
-{
-	struct device_config *dc = device_states + device;
-
-	/*
-	 * It'd be handy for debugging if we could print to the console when
-	 * device_set_state() is called.  But unfortunately, it'll be called a
-	 * LOT when debouncing UART activity on DETECT_EC or DETECT_AP.  So
-	 * only print when the last known state changes below.
-	 */
-
-	dc->state = state;
-
-	if (state != DEVICE_STATE_UNKNOWN && dc->last_known_state != state) {
-		dc->last_known_state = state;
-		CPRINTS("DEV %s -> %s", dc->name, state_desc(state));
-		return 1;
-	}
-
-	return 0;
-}
-
-/**
- * Periodic check of device states.
- *
- * The board does all the work.
- *
- * Note that device states can change outside of this context as well, for
- * example, from a GPIO interrupt handler.
- */
-static void check_device_state(void)
-{
-	int i;
-
-	for (i = 0; i < DEVICE_COUNT; i++)
-		board_update_device_state(i);
-}
-DECLARE_HOOK(HOOK_SECOND, check_device_state, HOOK_PRIO_DEFAULT);
-
-static int command_devices(int argc, char **argv)
-{
-	const struct device_config *dc = device_states;
-	int i;
-
-	ccprintf("Device    State   LastKnown\n");
-
-	for (i = 0; i < DEVICE_COUNT; i++, dc++)
-		ccprintf("%-9s %-7s %s\n", dc->name, state_desc(dc->state),
-			 state_desc(dc->last_known_state));
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices,
-			     "",
-			     "Get the device states");
diff --git a/common/dps.c b/common/dps.c
deleted file mode 100644
index 235f4d4e08..0000000000
--- a/common/dps.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Dynamic PDO Selection.
- */
-
-#include <stdint.h>
-
-#include "adc.h"
-#include "dps.h"
-#include "atomic.h"
-#include "battery.h"
-#include "console.h"
-#include "charger.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charge_state_v2.h"
-#include "math_util.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "usb_pe_sm.h"
-
-
-#define K_MORE_PWR 96
-#define K_LESS_PWR 93
-#define K_SAMPLE 1
-#define K_WINDOW 3
-#define T_REQUEST_STABLE_TIME (10 * SECOND)
-#define T_NEXT_CHECK_TIME (5 * SECOND)
-
-#define DPS_FLAG_DISABLED		BIT(0)
-#define DPS_FLAG_NO_SRCCAP		BIT(1)
-#define DPS_FLAG_WAITING		BIT(2)
-#define DPS_FLAG_SAMPLED		BIT(3)
-#define DPS_FLAG_NEED_MORE_PWR		BIT(4)
-
-#define DPS_FLAG_STOP_EVENTS		(DPS_FLAG_DISABLED | \
-					 DPS_FLAG_NO_SRCCAP)
-#define DPS_FLAG_ALL			GENMASK(31, 0)
-
-#define MAX_MOVING_AVG_WINDOW		5
-
-BUILD_ASSERT(K_MORE_PWR > K_LESS_PWR && 100 >= K_MORE_PWR && 100 >= K_LESS_PWR);
-
-/* lock for updating timeout value */
-static mutex_t dps_lock;
-static timestamp_t timeout;
-static bool is_enabled = true;
-static int debug_level;
-static bool fake_enabled;
-static int fake_mv, fake_ma;
-static int dynamic_mv;
-static int dps_port = CHARGE_PORT_NONE;
-static uint32_t flag;
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, "DPS " format, ##args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, "DPS " format, ##args)
-
-__overridable struct dps_config_t dps_config = {
-	.k_less_pwr = K_LESS_PWR,
-	.k_more_pwr = K_MORE_PWR,
-	.k_sample = K_SAMPLE,
-	.k_window = K_WINDOW,
-	.t_stable = T_REQUEST_STABLE_TIME,
-	.t_check = T_NEXT_CHECK_TIME,
-	.is_more_efficient = NULL,
-};
-
-int dps_get_dynamic_voltage(void)
-{
-	return dynamic_mv;
-}
-
-int dps_get_charge_port(void)
-{
-	return dps_port;
-}
-
-bool dps_is_enabled(void)
-{
-	return is_enabled;
-}
-
-static void dps_enable(bool en)
-{
-	bool prev_en = is_enabled;
-
-	is_enabled = en;
-
-	if (is_enabled && !prev_en)
-		task_wake(TASK_ID_DPS);
-}
-
-static void update_timeout(int us)
-{
-	timestamp_t new_timeout;
-
-	new_timeout.val = get_time().val + us;
-
-	mutex_lock(&dps_lock);
-	if (new_timeout.val > timeout.val)
-		timeout = new_timeout;
-	mutex_unlock(&dps_lock);
-}
-
-/*
- * DPS reset.
- */
-static void dps_reset(void)
-{
-	dynamic_mv = PD_MAX_VOLTAGE_MV;
-	dps_port = CHARGE_PORT_NONE;
-}
-
-/*
- * DPS initialization.
- */
-static void dps_init(void)
-{
-	dps_reset();
-
-	if (dps_config.k_window > MAX_MOVING_AVG_WINDOW) {
-		dps_config.k_window = MAX_MOVING_AVG_WINDOW;
-		CPRINTS("ERR:WIN");
-	}
-
-	if (dps_config.k_less_pwr > 100 ||
-	    dps_config.k_more_pwr > 100 ||
-	    dps_config.k_more_pwr <= dps_config.k_less_pwr) {
-		dps_config.k_less_pwr = K_LESS_PWR;
-		dps_config.k_more_pwr = K_MORE_PWR;
-		CPRINTS("ERR:COEF");
-	}
-}
-
-static bool is_near_limit(int val, int limit)
-{
-	return val >= (limit * dps_config.k_more_pwr / 100);
-}
-
-bool is_more_efficient(int curr_mv, int prev_mv, int batt_mv, int batt_mw,
-		       int input_mw)
-{
-	if (dps_config.is_more_efficient)
-		return dps_config.is_more_efficient(curr_mv, prev_mv, batt_mv,
-						    batt_mw, input_mw);
-
-	return ABS(curr_mv - batt_mv) < ABS(prev_mv - batt_mv);
-}
-
-/*
- * Get the input power of the active port.
- *
- * input_power = vbus * input_current
- *
- * @param vbus: VBUS in mV
- * @param input_curr: input current in mA
- *
- * @return input_power of the result of vbus * input_curr in mW
- */
-static int get_desired_input_power(int *vbus, int *input_current)
-{
-	int active_port;
-	int charger_id;
-	enum ec_error_list rv;
-
-	active_port = charge_manager_get_active_charge_port();
-
-	if (active_port == CHARGE_PORT_NONE)
-		return 0;
-
-	charger_id = charge_get_active_chg_chip();
-
-	if (fake_enabled) {
-		*vbus = fake_mv;
-		*input_current = fake_ma;
-		return fake_mv * fake_ma / 1000;
-	}
-
-	rv = charger_get_input_current(charger_id, input_current);
-	if (rv)
-		return 0;
-
-	*vbus = charge_manager_get_vbus_voltage(active_port);
-
-	return (*vbus) * (*input_current) / 1000;
-}
-
-/*
- * Get the most efficient PDO voltage for the battery of the charging port
- *
- * | W\Batt | 1S(3.7V) | 2S(7.4V) | 3S(11.1V) | 4S(14.8V) |
- * --------------------------------------------------------
- * | 0-15W  | 5V       | 9V       | 12V       | 15V       |
- * | 15-27W | 9V       | 9V       | 12V       | 15V       |
- * | 27-36W | 12V      | 12V      | 12V       | 15V       |
- * | 36-45W | 15V      | 15V      | 15V       | 15V       |
- * | 45-60W | 20V      | 20V      | 20V       | 20V       |
- *
- *
- * @return 0 if error occurs, else battery efficient voltage in mV
- */
-int get_efficient_voltage(void)
-{
-	int eff_mv = 0;
-	int batt_mv;
-	int batt_pwr;
-	int input_pwr, vbus, input_curr;
-	const struct batt_params *batt = charger_current_battery_params();
-
-	input_pwr = get_desired_input_power(&vbus, &input_curr);
-
-	if (!input_pwr)
-		return 0;
-
-	if (battery_design_voltage(&batt_mv))
-		return 0;
-
-	batt_pwr = batt->current * batt->voltage / 1000;
-
-	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		const int cnt = pd_get_src_cap_cnt(i);
-		const uint32_t *src_caps = pd_get_src_caps(i);
-
-		for (int j = 0; j < cnt; ++j) {
-			int ma, mv, unused;
-
-			pd_extract_pdo_power(src_caps[j], &ma, &mv, &unused);
-			/*
-			 * If the eff_mv is not picked, or we have more
-			 * efficient voltage (less voltage diff)
-			 */
-			if (eff_mv == 0 ||
-			    is_more_efficient(mv, eff_mv, batt_mv, batt_pwr,
-					      input_pwr))
-				eff_mv = mv;
-		}
-	}
-
-	return eff_mv;
-}
-
-struct pdo_candidate {
-	int port;
-	int mv;
-	int mw;
-};
-
-#define UPDATE_CANDIDATE(new_port, new_mv, new_mw) \
-	do { \
-		cand->port = new_port; \
-		cand->mv = new_mv; \
-		cand->mw = new_mw; \
-	} while (0)
-
-#define CLEAR_AND_RETURN() \
-	do { \
-		moving_avg_count = 0; \
-		return false; \
-	} while (0)
-
-/*
- * Evaluate the system power if a new PD power request is needed.
- *
- * @param struct pdo_candidate: The candidate PDO. (Return value)
- * @return true if a new power request, or false otherwise.
- */
-static bool has_new_power_request(struct pdo_candidate *cand)
-{
-	int vbus, input_curr, input_pwr;
-	int input_pwr_avg = 0, input_curr_avg = 0;
-	int batt_pwr, batt_mv;
-	int max_mv = pd_get_max_voltage();
-	int req_pwr, req_ma, req_mv;
-	int input_curr_limit;
-	int active_port = charge_manager_get_active_charge_port();
-	int charger_id;
-	static int input_pwrs[MAX_MOVING_AVG_WINDOW];
-	static int input_currs[MAX_MOVING_AVG_WINDOW];
-	static int prev_active_port = CHARGE_PORT_NONE;
-	static int prev_req_mv;
-	static int moving_avg_count;
-	const struct batt_params *batt = charger_current_battery_params();
-
-	/* set a default value in case it early returns. */
-	UPDATE_CANDIDATE(CHARGE_PORT_NONE, INT32_MAX, 0);
-
-	if (active_port == CHARGE_PORT_NONE)
-		CLEAR_AND_RETURN();
-
-	req_mv = pd_get_requested_voltage(active_port);
-	req_ma = pd_get_requested_current(active_port);
-
-	if (!req_mv)
-		CLEAR_AND_RETURN();
-
-	if (battery_design_voltage(&batt_mv))
-		CLEAR_AND_RETURN();
-
-	/* if last sample is not the same as the current one, reset counting. */
-	if (prev_req_mv != req_mv || prev_active_port != active_port)
-		moving_avg_count = 0;
-	prev_active_port = active_port;
-	prev_req_mv = req_mv;
-
-	req_pwr = req_mv * req_ma / 1000;
-	batt_pwr = batt->current * batt->voltage / 1000;
-	input_pwr = get_desired_input_power(&vbus, &input_curr);
-
-	if (!input_pwr)
-		CLEAR_AND_RETURN();
-
-	/* record moving average */
-	input_pwrs[moving_avg_count % dps_config.k_window] = input_pwr;
-	input_currs[moving_avg_count % dps_config.k_window] = input_curr;
-	if (++moving_avg_count < dps_config.k_window)
-		return false;
-
-	for (int i = 0; i < dps_config.k_window; i++) {
-		input_curr_avg += input_currs[i];
-		input_pwr_avg += input_pwrs[i];
-	}
-	input_curr_avg /= dps_config.k_window;
-	input_pwr_avg /= dps_config.k_window;
-
-	charger_id = charge_get_active_chg_chip();
-
-	if (!charger_get_input_current_limit(charger_id, &input_curr_limit))
-		/* set as last requested mA if we're unable to get the limit. */
-		input_curr_limit = req_ma;
-
-	/*
-	 * input power might be insufficient, force it to negotiate a more
-	 * powerful PDO.
-	 */
-	if (is_near_limit(input_pwr_avg, req_pwr) ||
-	    is_near_limit(input_curr_avg, MIN(req_ma, input_curr_limit))) {
-		flag |= DPS_FLAG_NEED_MORE_PWR;
-		if (!fake_enabled)
-			input_pwr_avg = req_pwr + 1;
-	} else {
-		flag &= ~DPS_FLAG_NEED_MORE_PWR;
-	}
-
-	if (debug_level)
-		CPRINTS("C%d 0x%x last (%dmW %dmV) input (%dmW %dmV %dmA) "
-			"avg (%dmW, %dmA)",
-			active_port, flag, req_pwr, req_mv, input_pwr, vbus,
-			input_curr, input_pwr_avg, input_curr_avg);
-
-	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		const uint32_t * const src_caps = pd_get_src_caps(i);
-
-		for (int j = 0; j < pd_get_src_cap_cnt(i); ++j) {
-			int ma, mv, unused;
-			int mw;
-			bool efficient;
-
-			/* TODO(b:169532537): support augmented PDO. */
-			if ((src_caps[j] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-				continue;
-
-			pd_extract_pdo_power(src_caps[j], &ma, &mv, &unused);
-
-			if (mv > max_mv)
-				continue;
-
-			mw = ma * mv / 1000;
-			efficient = is_more_efficient(mv, cand->mv, batt_mv,
-						      batt_pwr, input_pwr_avg);
-
-			if (flag & DPS_FLAG_NEED_MORE_PWR) {
-				/* the insufficient case.*/
-				if (input_pwr_avg > cand->mw &&
-				    (mw > cand->mw ||
-				     (mw == cand->mw && efficient))) {
-					UPDATE_CANDIDATE(i, mv, mw);
-				} else if (input_pwr_avg <= mw && efficient) {
-					UPDATE_CANDIDATE(i, mv, mw);
-				}
-			} else {
-				int adjust_pwr =
-					mw * dps_config.k_less_pwr / 100;
-				int adjust_cand_mw =
-					cand->mw * dps_config.k_less_pwr / 100;
-
-				/* Pick if we don't have a candidate yet. */
-				if (!cand->mw) {
-					UPDATE_CANDIDATE(i, mv, mw);
-					/*
-					 * if the candidate is insufficient, and
-					 * we get one provides more.
-					 */
-				} else if ((adjust_cand_mw < input_pwr_avg &&
-					    cand->mw < mw) ||
-					   /*
-					    * if the candidate is sufficient,
-					    * and we pick a more efficient one.
-					    */
-					   (adjust_cand_mw >= input_pwr_avg &&
-					    adjust_pwr >= input_pwr_avg &&
-					    efficient)) {
-					UPDATE_CANDIDATE(i, mv, mw);
-				}
-			}
-
-
-			/*
-			 * if the candidate is the same as the current one, pick
-			 * the one at active charge port.
-			 */
-			if (mw == cand->mw && mv == cand->mv &&
-			    i == active_port)
-				UPDATE_CANDIDATE(i, mv, mw);
-		}
-	}
-
-	if (!cand->mv)
-		CPRINTS("ERR:CNDMV");
-
-	return (cand->mv != req_mv);
-}
-
-static bool has_srccap(void)
-{
-	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		if (pd_is_connected(i) &&
-		    pd_get_power_role(i) == PD_ROLE_SINK &&
-		    pd_get_src_cap_cnt(i) > 0)
-			return true;
-	}
-	return false;
-}
-
-void dps_update_stabilized_time(int port)
-{
-	update_timeout(dps_config.t_stable);
-}
-
-void dps_task(void *u)
-{
-	struct pdo_candidate last_cand = {CHARGE_PORT_NONE, 0, 0};
-	int sample_count = 0;
-
-	dps_init();
-	update_timeout(dps_config.t_check);
-
-	while (1) {
-		struct pdo_candidate curr_cand = {CHARGE_PORT_NONE, 0, 0};
-		timestamp_t now;
-
-		now = get_time();
-		if (flag & DPS_FLAG_STOP_EVENTS) {
-			dps_reset();
-			task_wait_event(-1);
-			/* clear flags after wake up. */
-			flag = 0;
-			update_timeout(dps_config.t_check);
-			continue;
-		} else if (now.val < timeout.val) {
-			flag |= DPS_FLAG_WAITING;
-			task_wait_event(timeout.val - now.val);
-			flag &= ~DPS_FLAG_WAITING;
-		}
-
-		if (!is_enabled) {
-			flag |= DPS_FLAG_DISABLED;
-			continue;
-		}
-
-		if (!has_srccap()) {
-			flag |= DPS_FLAG_NO_SRCCAP;
-			continue;
-		}
-
-		if (!has_new_power_request(&curr_cand)) {
-			sample_count = 0;
-			flag &= ~DPS_FLAG_SAMPLED;
-		} else {
-			if (last_cand.port == curr_cand.port &&
-			    last_cand.mv == curr_cand.mv &&
-			    last_cand.mw == curr_cand.mw)
-				sample_count++;
-			else
-				sample_count = 1;
-			flag |= DPS_FLAG_SAMPLED;
-		}
-
-		if (sample_count == dps_config.k_sample) {
-			dynamic_mv = curr_cand.mv;
-			dps_port = curr_cand.port;
-			pd_dpm_request(dps_port,
-				       DPM_REQUEST_NEW_POWER_LEVEL);
-			sample_count = 0;
-			flag &= ~(DPS_FLAG_SAMPLED | DPS_FLAG_NEED_MORE_PWR);
-		}
-
-		last_cand.port = curr_cand.port;
-		last_cand.mv = curr_cand.mv;
-		last_cand.mw = curr_cand.mw;
-
-		update_timeout(dps_config.t_check);
-	}
-}
-
-static int command_dps(int argc, char **argv)
-{
-	int port = charge_manager_get_active_charge_port();
-	int input_pwr, vbus, input_curr;
-	int holder;
-
-	if (argc == 1) {
-		uint32_t last_ma = 0, last_mv = 0;
-		int batt_mv;
-
-		ccprintf("flag=0x%x k_more=%d k_less=%d k_sample=%d k_win=%d\n",
-			 flag, dps_config.k_more_pwr, dps_config.k_less_pwr,
-			 dps_config.k_sample, dps_config.k_window);
-		ccprintf("t_stable=%d t_check=%d\n",
-			 dps_config.t_stable / SECOND,
-			 dps_config.t_check / SECOND);
-		if (!is_enabled) {
-			ccprintf("DPS Disabled\n");
-			return EC_SUCCESS;
-		}
-
-		if (port == CHARGE_PORT_NONE) {
-			ccprintf("No charger attached\n");
-			return EC_SUCCESS;
-		}
-
-		battery_design_voltage(&batt_mv);
-		input_pwr = get_desired_input_power(&vbus, &input_curr);
-		if (!(flag & DPS_FLAG_NO_SRCCAP)) {
-			last_mv = pd_get_requested_voltage(port);
-			last_ma = pd_get_requested_current(port);
-		}
-		ccprintf("C%d DPS Enabled\n"
-			 "Requested: %dmV/%dmA\n"
-			 "Measured:  %dmV/%dmA/%dmW\n"
-			 "Efficient: %dmV\n"
-			 "Batt:      %dmv\n"
-			 "PDMaxMV:   %dmV\n",
-			 port, last_mv, last_ma,
-			 vbus, input_curr, input_pwr,
-			 get_efficient_voltage(),
-			 batt_mv,
-			 pd_get_max_voltage());
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "en")) {
-		dps_enable(true);
-		return EC_SUCCESS;
-	} else if (!strcasecmp(argv[1], "dis")) {
-		dps_enable(false);
-		return EC_SUCCESS;
-	} else if (!strcasecmp(argv[1], "fakepwr")) {
-		if (argc == 2) {
-			ccprintf("%sabled %dmV/%dmA\n",
-				 fake_enabled ? "en" : "dis", fake_mv, fake_ma);
-			return EC_SUCCESS;
-		}
-
-		if (!strcasecmp(argv[2], "dis")) {
-			fake_enabled = false;
-			return EC_SUCCESS;
-		}
-
-		if (argc < 4)
-			return EC_ERROR_PARAM_COUNT;
-
-		holder = atoi(argv[2]);
-		if (holder <= 0)
-			return EC_ERROR_PARAM2;
-		fake_mv = holder;
-
-		holder = atoi(argv[3]);
-		if (holder <= 0)
-			return EC_ERROR_PARAM3;
-		fake_ma = holder;
-
-		fake_enabled = true;
-		return EC_SUCCESS;
-	}
-
-	if (argc != 3)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(argv[1], "debug")) {
-		debug_level = atoi(argv[2]);
-	} else if (!strcasecmp(argv[1], "setkmore")) {
-		holder = atoi(argv[2]);
-		if (holder > 100 || holder <= 0 ||
-		    holder < dps_config.k_less_pwr)
-			return EC_ERROR_PARAM2;
-		dps_config.k_more_pwr = holder;
-	} else if (!strcasecmp(argv[1], "setkless")) {
-		holder = atoi(argv[2]);
-		if (holder > 100 || holder <= 0 ||
-		    holder > dps_config.k_more_pwr)
-			return EC_ERROR_PARAM2;
-		dps_config.k_less_pwr = holder;
-	} else if (!strcasecmp(argv[1], "setksample")) {
-		holder = atoi(argv[2]);
-		if (holder <= 0)
-			return EC_ERROR_PARAM2;
-		dps_config.k_sample = holder;
-	} else if (!strcasecmp(argv[1], "setkwin")) {
-		holder = atoi(argv[2]);
-		if (holder <= 0 || holder > MAX_MOVING_AVG_WINDOW)
-			return EC_ERROR_PARAM2;
-		dps_config.k_window = holder;
-	} else if (!strcasecmp(argv[1], "settcheck")) {
-		holder = atoi(argv[2]);
-		if (holder <= 0)
-			return EC_ERROR_PARAM2;
-		dps_config.t_check = holder * SECOND;
-	} else if (!strcasecmp(argv[1], "settstable")) {
-		holder = atoi(argv[2]);
-		if (holder <= 0)
-			return EC_ERROR_PARAM2;
-		dps_config.t_stable = holder * SECOND;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dps, command_dps,
-			"en|dis|debug <int>\n"
-			"\t\t set(kmore|kless|ksample|kwindow) <int>\n"
-			"\t\t set(tstable|tcheck) <int>\n"
-			"\t\t fakepwr [dis|<mV> <mA>]",
-			"Print/set Dynamic PDO Selection state.");
diff --git a/common/dptf.c b/common/dptf.c
deleted file mode 100644
index 33a42ba5af..0000000000
--- a/common/dptf.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "dptf.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-#ifdef CONFIG_ZEPHYR
-#include "temp_sensor/temp_sensor.h"
-#endif
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_DPTF, outstr)
-#define CPRINTS(format, args...) cprints(CC_DPTF, format, ## args)
-
-/*****************************************************************************/
-/* DPTF temperature thresholds */
-
-static struct {
-	int temp;     /* degrees K, negative for disabled */
-	cond_t over;      /* watch for crossings */
-} dptf_threshold[TEMP_SENSOR_COUNT][DPTF_THRESHOLDS_PER_SENSOR];
-
-static void dptf_init(void)
-{
-	int id, t;
-
-	for (id = 0; id < TEMP_SENSOR_COUNT; id++)
-		for (t = 0; t < DPTF_THRESHOLDS_PER_SENSOR; t++) {
-			dptf_threshold[id][t].temp = -1;
-			cond_init(&dptf_threshold[id][t].over, 0);
-		}
-
-}
-DECLARE_HOOK(HOOK_INIT, dptf_init, HOOK_PRIO_DEFAULT);
-
-/* Keep track of which triggered sensor thresholds the AP has seen */
-static uint32_t dptf_seen;
-
-int dptf_query_next_sensor_event(void)
-{
-	int id;
-
-	for (id = 0; id < TEMP_SENSOR_COUNT; id++)
-		if (dptf_seen & BIT(id)) {  /* atomic? */
-			atomic_clear_bits(&dptf_seen, BIT(id));
-			return id;
-		}
-
-	return -1;
-}
-
-/* Return true if any threshold transition occurs. */
-static int dptf_check_temp_threshold(int sensor_id, int temp)
-{
-	int tripped = 0;
-	int max, i;
-
-	if (sensor_id >= TEMP_SENSOR_COUNT) {
-		CPRINTS("DPTF: Invalid sensor ID");
-		return 0;
-	}
-
-	for (i = 0; i < DPTF_THRESHOLDS_PER_SENSOR; i++) {
-
-		max = dptf_threshold[sensor_id][i].temp;
-		if (max < 0)      /* disabled? */
-			continue;
-
-		if (temp >= max)
-			cond_set_true(&dptf_threshold[sensor_id][i].over);
-		else if (temp <= max - DPTF_THRESHOLD_HYSTERESIS)
-			cond_set_false(&dptf_threshold[sensor_id][i].over);
-
-		if (cond_went_true(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF over threshold [%d][%d",
-				sensor_id, i);
-			atomic_or(&dptf_seen, BIT(sensor_id));
-			tripped = 1;
-		}
-		if (cond_went_false(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF under threshold [%d][%d",
-				sensor_id, i);
-			atomic_or(&dptf_seen, BIT(sensor_id));
-			tripped = 1;
-		}
-	}
-
-	return tripped;
-}
-
-void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable)
-{
-	CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled",
-		sensor_id, K_TO_C(temp), idx, enable ? "en" : "dis");
-
-	if ((sensor_id >= TEMP_SENSOR_COUNT) ||
-	    (idx >= DPTF_THRESHOLDS_PER_SENSOR)) {
-		CPRINTS("DPTF: Invalid sensor ID");
-		return;
-	}
-
-	if (enable) {
-		/* Don't update threshold condition if already enabled */
-		if (dptf_threshold[sensor_id][idx].temp == -1)
-			cond_init(&dptf_threshold[sensor_id][idx].over, 0);
-		dptf_threshold[sensor_id][idx].temp = temp;
-		atomic_clear_bits(&dptf_seen, BIT(sensor_id));
-	} else {
-		dptf_threshold[sensor_id][idx].temp = -1;
-	}
-}
-
-/*****************************************************************************/
-/* EC-specific thermal controls */
-
-test_mockable_static void smi_sensor_failure_warning(void)
-{
-	CPRINTS("can't read any temp sensors!");
-	host_set_single_event(EC_HOST_EVENT_THERMAL);
-}
-
-static void thermal_control_dptf(void)
-{
-	int i, t, rv;
-	int dptf_tripped;
-	int num_sensors_read;
-
-	dptf_tripped = 0;
-	num_sensors_read = 0;
-
-	/* go through all the sensors */
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		rv = temp_sensor_read(i, &t);
-		if (rv != EC_SUCCESS)
-			continue;
-		else
-			num_sensors_read++;
-		/* and check the dptf thresholds */
-		dptf_tripped |= dptf_check_temp_threshold(i, t);
-	}
-
-	if (!num_sensors_read) {
-		/*
-		 * Trigger a SMI event if we can't read any sensors.
-		 *
-		 * In theory we could do something more elaborate like forcing
-		 * the system to shut down if no sensors are available after
-		 * several retries.  This is a very unlikely scenario -
-		 * particularly on LM4-based boards, since the LM4 has its own
-		 * internal temp sensor.  It's most likely to occur during
-		 * bringup of a new board, where we haven't debugged the I2C
-		 * bus to the sensors; forcing a shutdown in that case would
-		 * merely hamper board bringup.
-		 */
-		if (!chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			smi_sensor_failure_warning();
-	}
-
-	/* Don't forget to signal any DPTF thresholds */
-	if (dptf_tripped)
-		host_set_single_event(EC_HOST_EVENT_THERMAL_THRESHOLD);
-}
-
-/* Wait until after the sensors have been read */
-DECLARE_HOOK(HOOK_SECOND, thermal_control_dptf, HOOK_PRIO_TEMP_SENSOR_DONE);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_dptftemp(int argc, char **argv)
-{
-	int id, t;
-	int temp, trig;
-
-	ccprintf("sensor   thresh0   thresh1\n");
-	for (id = 0; id < TEMP_SENSOR_COUNT; id++) {
-		ccprintf(" %2d", id);
-		for (t = 0; t < DPTF_THRESHOLDS_PER_SENSOR; t++) {
-			temp = dptf_threshold[id][t].temp;
-			trig = cond_is_true(&dptf_threshold[id][t].over);
-			if (temp < 0)
-				ccprintf("       --- ");
-			else
-				ccprintf("       %3d%c", temp,
-					 trig ? '*' : ' ');
-		}
-		ccprintf("    %s\n", temp_sensors[id].name);
-	}
-
-	ccprintf("AP seen mask: 0x%08x\n", dptf_seen);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp,
-			NULL,
-			"Print DPTF thermal parameters (degrees Kelvin)");
diff --git a/common/ec.libsharedobjs.ld b/common/ec.libsharedobjs.ld
deleted file mode 100644
index adf5081640..0000000000
--- a/common/ec.libsharedobjs.ld
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-SECTIONS
-{
-	.roshared : { KEEP(*(.roshared*)) }
-	/*
-	* Save the .ARM.atrributes section to make the linker not complain
-	* about conflicting CPU architectures when linking with the RW objs.
-	* This section will be discarded by the main EC linker script.
-	*/
-	.ARM.attributes : { KEEP(*(.ARM.*)) }
-}
diff --git a/common/ec_ec_comm_client.c b/common/ec_ec_comm_client.c
deleted file mode 100644
index c92433af8c..0000000000
--- a/common/ec_ec_comm_client.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, functions and definitions for client.
- */
-
-#include "battery.h"
-#include "common.h"
-#include "console.h"
-#include "crc8.h"
-#include "ec_commands.h"
-#include "ec_ec_comm_client.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-/*
- * TODO(b:65697962): The packed structures below do not play well if we force EC
- * host commands structures to be aligned on 32-bit boundary. There are ways to
- * fix that, possibly requiring copying data around, or modifying
- * uart_alt_pad_write_read API to write the actual server response to a separate
- * buffer.
- */
-#ifdef CONFIG_HOSTCMD_ALIGNED
-#error "Cannot define CONFIG_HOSTCMD_ALIGNED with EC-EC communication client."
-#endif
-
-#define EC_EC_HOSTCMD_VERSION 4
-
-/* Print extra debugging information */
-#undef EXTRA_DEBUG
-
-/*
- * During early debugging, we would like to check that the error rate does
- * grow out of control.
- */
-#define DEBUG_EC_COMM_STATS
-#ifdef DEBUG_EC_COMM_STATS
-struct {
-	int total;
-	int errtimeout;
-	int errbusy;
-	int errunknown;
-	int errdatacrc;
-	int errcrc;
-	int errinval;
-} comm_stats;
-
-#define INCR_COMM_STATS(var) (comm_stats.var++)
-#else
-#define INCR_COMM_STATS(var)
-#endif
-
-/**
- * Write a command on the EC-EC communication UART channel.
- *
- * @param command	One of EC_CMD_*.
- * @param data		Packed structure with this layout:
- * struct {
- *	struct {
- *		struct ec_host_request4 head;
- *		struct ec_params_* param;
- *		uint8_t crc8;
- *	} req;
- *	struct {
- *		struct ec_host_response4 head;
- *		struct ec_response_* info;
- *		uint8_t crc8;
- *	} resp;
- * } __packed data;
- *
- * Where req is the request to be transmitted (head and crc8 are computed by
- * this function), and resp is the response to be received (head integrity and
- * crc8 are verified by this function).
- *
- * This format is required as the EC-EC UART is half-duplex, and all the
- * transmitted data is received back, i.e. the client writes req, then reads
- * req, followed by resp.
- *
- * When a command does not take parameters, param/crc8 must be omitted in
- * tx structure. The same applies to rx structure if the response does not
- * include a payload: info/crc8 must be omitted.
- *
- * @param req_len	size of req.param (0 if no parameter is passed).
- * @param resp_len	size of resp.info (0 if no information is returned).
- * @param timeout_us	timeout in microseconds for the transaction to complete.
- *
- * @return
- *  - EC_SUCCESS on success.
- *  - EC_ERROR_TIMEOUT when remote end times out replying.
- *  - EC_ERROR_BUSY when UART is busy and cannot transmit currently.
- *  - EC_ERROR_CRC when the header or data CRC is invalid.
- *  - EC_ERROR_INVAL when the received header is invalid.
- *  - EC_ERROR_UNKNOWN on other error.
- */
-static int write_command(uint16_t command,
-			 uint8_t *data, int req_len, int resp_len,
-			 int timeout_us)
-{
-	/* Sequence number. */
-	static uint8_t cur_seq;
-	int ret;
-	int hascrc, response_seq;
-
-	struct ec_host_request4 *request_header = (void *)data;
-	/* Request (TX) length is header + (data + crc8), response follows. */
-	int tx_length =
-		sizeof(*request_header) + ((req_len > 0) ? (req_len + 1) : 0);
-
-	struct ec_host_response4 *response_header =
-		(void *)&data[tx_length];
-	/* RX length is TX length + response from server. */
-	int rx_length = tx_length +
-		sizeof(*request_header) + ((resp_len > 0) ? (resp_len + 1) : 0);
-
-	/*
-	 * Make sure there is a gap between each command, so that the server
-	 * can recover its state machine after each command.
-	 *
-	 * TODO(b:65697962): We can be much smarter than this, and record the
-	 * last transaction time instead of just sleeping blindly.
-	 */
-	usleep(10*MSEC);
-
-#ifdef DEBUG_EC_COMM_STATS
-	if ((comm_stats.total % 128) == 0) {
-		CPRINTF("UART %d (T%dB%d,U%dC%dD%dI%d)\n", comm_stats.total,
-			comm_stats.errtimeout, comm_stats.errbusy,
-			comm_stats.errunknown, comm_stats.errcrc,
-			comm_stats.errdatacrc, comm_stats.errinval);
-	}
-#endif
-
-	cur_seq = (cur_seq + 1) &
-		(EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT);
-
-	memset(request_header, 0, sizeof(*request_header));
-	/* fields0: leave seq_dup and is_response as 0. */
-	request_header->fields0 =
-		EC_EC_HOSTCMD_VERSION | /* version */
-		(cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
-	/* fields1: leave command_version as 0. */
-	if (req_len > 0)
-		request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-	request_header->command = command;
-	request_header->data_len = req_len;
-	request_header->header_crc =
-		cros_crc8((uint8_t *)request_header, sizeof(*request_header)-1);
-	if (req_len > 0)
-		data[sizeof(*request_header) + req_len] =
-			cros_crc8(&data[sizeof(*request_header)], req_len);
-
-	ret = uart_alt_pad_write_read((void *)data, tx_length,
-				      (void *)data, rx_length, timeout_us);
-
-	INCR_COMM_STATS(total);
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("EC-EC ret=%d/%d\n", ret, rx_length);
-#endif
-
-	if (ret != rx_length) {
-		if (ret == -EC_ERROR_TIMEOUT) {
-			INCR_COMM_STATS(errtimeout);
-			return EC_ERROR_TIMEOUT;
-		}
-
-		if (ret == -EC_ERROR_BUSY) {
-			INCR_COMM_STATS(errbusy);
-			return EC_ERROR_BUSY;
-		}
-
-		INCR_COMM_STATS(errunknown);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (response_header->header_crc !=
-	    cros_crc8((uint8_t *)response_header,
-		      sizeof(*response_header) - 1)) {
-		INCR_COMM_STATS(errcrc);
-		return EC_ERROR_CRC;
-	}
-
-	hascrc = response_header->fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-	response_seq = (response_header->fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-		EC_PACKET4_0_SEQ_NUM_SHIFT;
-
-	/*
-	 * Validate received header.
-	 * Note that we _require_ data crc to be present if there is data to be
-	 * read back, else we would not know how many bytes to read exactly.
-	 */
-	if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK)
-				!= EC_EC_HOSTCMD_VERSION ||
-			!(response_header->fields0 &
-				EC_PACKET4_0_IS_RESPONSE_MASK) ||
-			response_seq != cur_seq ||
-			(response_header->data_len > 0 && !hascrc) ||
-			response_header->data_len != resp_len) {
-		INCR_COMM_STATS(errinval);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check data CRC. */
-	if (hascrc &&
-	    data[rx_length - 1] !=
-		    cros_crc8(&data[tx_length + sizeof(*request_header)],
-			      resp_len)) {
-		INCR_COMM_STATS(errdatacrc);
-		return EC_ERROR_CRC;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * handle error from write_command
- *
- * @param ret is return value from write_command
- * @param request_result is data.resp.head.result (response result value)
- *
- * @return EC_RES_ERROR if ret is not EC_SUCCESS, else request_result.
- */
-static int handle_error(const char *func, int ret, int request_result)
-{
-	if (ret != EC_SUCCESS) {
-		/* Do not print busy errors as they just spam the console. */
-		if (ret != EC_ERROR_BUSY)
-			CPRINTF("%s: tx error %d\n", func, ret);
-		return EC_RES_ERROR;
-	}
-
-	if (request_result != EC_RES_SUCCESS)
-		CPRINTF("%s: cmd error %d\n", func, ret);
-
-	return request_result;
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-int ec_ec_client_base_get_dynamic_info(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_battery_dynamic_info param;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-			struct ec_response_battery_dynamic_info info;
-			uint8_t crc8;
-		} resp;
-	} __packed data;
-
-	data.req.param.index = 0;
-
-	ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
-	ret = handle_error(__func__, ret, data.resp.head.result);
-	if (ret != EC_RES_SUCCESS)
-		return ret;
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("V:          %d mV\n", data.resp.info.actual_voltage);
-	CPRINTF("I:          %d mA\n", data.resp.info.actual_current);
-	CPRINTF("Remaining:  %d mAh\n", data.resp.info.remaining_capacity);
-	CPRINTF("Cap-full:   %d mAh\n", data.resp.info.full_capacity);
-	CPRINTF("Flags:      %04x\n", data.resp.info.flags);
-	CPRINTF("V-desired:  %d mV\n", data.resp.info.desired_voltage);
-	CPRINTF("I-desired:  %d mA\n", data.resp.info.desired_current);
-#endif
-
-	memcpy(&battery_dynamic[BATT_IDX_BASE], &data.resp.info,
-				sizeof(battery_dynamic[BATT_IDX_BASE]));
-	return EC_RES_SUCCESS;
-}
-
-int ec_ec_client_base_get_static_info(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_battery_static_info param;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-			struct ec_response_battery_static_info info;
-			uint8_t crc8;
-		} resp;
-	} __packed data;
-
-	data.req.param.index = 0;
-
-	ret = write_command(EC_CMD_BATTERY_GET_STATIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
-	ret = handle_error(__func__, ret, data.resp.head.result);
-	if (ret != EC_RES_SUCCESS)
-		return ret;
-
-#ifdef EXTRA_DEBUG
-	CPRINTF("Cap-design: %d mAh\n", data.resp.info.design_capacity);
-	CPRINTF("V-design:   %d mV\n", data.resp.info.design_voltage);
-	CPRINTF("Manuf:      %s\n", data.resp.info.manufacturer);
-	CPRINTF("Model:      %s\n", data.resp.info.model);
-	CPRINTF("Serial:     %s\n", data.resp.info.serial);
-	CPRINTF("Type:       %s\n", data.resp.info.type);
-	CPRINTF("C-count:    %d\n", data.resp.info.cycle_count);
-#endif
-
-	memcpy(&battery_static[BATT_IDX_BASE], &data.resp.info,
-				sizeof(battery_static[BATT_IDX_BASE]));
-	return EC_RES_SUCCESS;
-}
-
-int ec_ec_client_base_charge_control(int max_current,
-				     int otg_voltage,
-				     int allow_charging)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_charger_control ctrl;
-			uint8_t crc8;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-		} resp;
-	} __packed data;
-
-	data.req.ctrl.allow_charging = allow_charging;
-	data.req.ctrl.max_current = max_current;
-	data.req.ctrl.otg_voltage = otg_voltage;
-
-	ret = write_command(EC_CMD_CHARGER_CONTROL,
-		(void *)&data, sizeof(data.req.ctrl), 0, 30 * MSEC);
-
-	return handle_error(__func__, ret, data.resp.head.result);
-}
-
-int ec_ec_client_hibernate(void)
-{
-	int ret;
-	struct {
-		struct {
-			struct ec_host_request4 head;
-			struct ec_params_reboot_ec param;
-		} req;
-		struct {
-			struct ec_host_response4 head;
-		} resp;
-	} __packed data;
-
-	data.req.param.cmd = EC_REBOOT_HIBERNATE;
-	data.req.param.flags = 0;
-
-	ret = write_command(EC_CMD_REBOOT_EC,
-		(void *)&data, sizeof(data.req.param), 0, 30 * MSEC);
-
-	return handle_error(__func__, ret, data.resp.head.result);
-}
-#endif /* CONFIG_EC_EC_COMM_BATTERY */
diff --git a/common/ec_ec_comm_server.c b/common/ec_ec_comm_server.c
deleted file mode 100644
index 23b5fee139..0000000000
--- a/common/ec_ec_comm_server.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, task and functions for server.
- */
-
-#include "common.h"
-#include "battery.h"
-#include "charge_state_v2.h"
-#include "console.h"
-#include "crc8.h"
-#include "ec_commands.h"
-#include "ec_ec_comm_server.h"
-#include "extpower.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* Print extra debugging information */
-#undef EXTRA_DEBUG
-
-/* Set if the client allows the server to charge the battery. */
-static int charging_allowed;
-
-/*
- * Our command parameter buffer must be big enough to fit any command
- * parameter, and crc byte.
- */
-#define LARGEST_PARAMS_SIZE 8
-
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_static_info));
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_dynamic_info));
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_charger_control));
-
-#define COMMAND_BUFFER_PARAMS_SIZE (LARGEST_PARAMS_SIZE + 1)
-
-/*
- * Maximum time needed to read a full command, commands are at most 17 bytes, so
- * should not take more than 2ms to be sent at 115200 bps.
- */
-#define COMMAND_TIMEOUT_US (5 * MSEC)
-
-
-void ec_ec_comm_server_written(struct consumer const *consumer, size_t count)
-{
-	task_wake(TASK_ID_ECCOMM);
-}
-
-/*
- * Discard all data from the input queue.
- *
- * Note that we always sleep for 1ms after clearing the queue, to make sure
- * that we give enough time for the next byte to arrive.
- */
-static void discard_queue(void)
-{
-	do {
-		queue_advance_head(&ec_ec_comm_server_input,
-				queue_count(&ec_ec_comm_server_input));
-		usleep(1 * MSEC);
-	} while (queue_count(&ec_ec_comm_server_input) > 0);
-}
-
-/* Write response to client. */
-static void write_response(uint16_t res, int seq, const void *data, int len)
-{
-	struct ec_host_response4 header;
-	uint8_t crc;
-
-	header.fields0 =
-		4 | /* version */
-		EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */
-		(seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
-	/* Set data_crc_present if there is data */
-	header.fields1 = (len > 0) ? EC_PACKET4_1_DATA_CRC_PRESENT_MASK : 0;
-	header.result = res;
-	header.data_len = len;
-	header.reserved = 0;
-	header.header_crc =
-		cros_crc8((uint8_t *)&header, sizeof(header)-1);
-	QUEUE_ADD_UNITS(&ec_ec_comm_server_output,
-			(uint8_t *)&header, sizeof(header));
-
-	if (len > 0) {
-		QUEUE_ADD_UNITS(&ec_ec_comm_server_output, data, len);
-		crc = cros_crc8(data, len);
-		QUEUE_ADD_UNITS(&ec_ec_comm_server_output, &crc, sizeof(crc));
-	}
-}
-
-/*
- * Read len bytes into buffer. Waiting up to COMMAND_TIMEOUT_US after start.
- *
- * Returns EC_SUCCESS or EC_ERROR_TIMEOUT.
- */
-static int read_data(void *buffer, size_t len, uint32_t start)
-{
-	uint32_t delta;
-
-	while (queue_count(&ec_ec_comm_server_input) < len) {
-		delta = __hw_clock_source_read() - start;
-		if (delta >= COMMAND_TIMEOUT_US)
-			return EC_ERROR_TIMEOUT;
-
-		/* Every incoming byte wakes the task. */
-		task_wait_event(COMMAND_TIMEOUT_US - delta);
-	}
-
-	/* Fetch header */
-	QUEUE_REMOVE_UNITS(&ec_ec_comm_server_input, buffer, len);
-
-	return EC_SUCCESS;
-}
-
-static void handle_cmd_reboot_ec(
-	const struct ec_params_reboot_ec *params,
-	int data_len, int seq)
-{
-	int ret = EC_RES_SUCCESS;
-
-	if (data_len != sizeof(*params)) {
-		ret = EC_RES_INVALID_COMMAND;
-		goto out;
-	}
-
-	/* Only handle hibernate */
-	if (params->cmd != EC_REBOOT_HIBERNATE) {
-		ret = EC_RES_INVALID_PARAM;
-		goto out;
-	}
-
-	CPRINTS("Hibernating...");
-
-	system_hibernate(0, 0);
-	/* We should not be able to write back the response. */
-
-out:
-	write_response(ret, seq, NULL, 0);
-}
-
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-static void handle_cmd_charger_control(
-	const struct ec_params_charger_control *params,
-	int data_len, int seq)
-{
-	int ret = EC_RES_SUCCESS;
-	int prev_charging_allowed = charging_allowed;
-
-	if (data_len != sizeof(*params)) {
-		ret = EC_RES_INVALID_COMMAND;
-		goto out;
-	}
-
-	if (params->max_current >= 0) {
-		charge_set_output_current_limit(CHARGER_SOLO, 0, 0);
-		charge_set_input_current_limit(
-			MIN(MAX_CURRENT_MA, params->max_current), 0);
-		charging_allowed = params->allow_charging;
-	} else {
-		if (-params->max_current > MAX_OTG_CURRENT_MA ||
-				params->otg_voltage > MAX_OTG_VOLTAGE_MV) {
-			ret = EC_RES_INVALID_PARAM;
-			goto out;
-		}
-
-		/* Reset input current to minimum. */
-		charge_set_input_current_limit(CONFIG_CHARGER_INPUT_CURRENT, 0);
-		/* Setup and enable "OTG". */
-		charge_set_output_current_limit(CHARGER_SOLO,
-						-params->max_current,
-						params->otg_voltage);
-		charging_allowed = 0;
-	}
-
-	if (prev_charging_allowed != charging_allowed)
-		hook_notify(HOOK_AC_CHANGE);
-
-out:
-	write_response(ret, seq, NULL, 0);
-}
-
-/*
- * On dual-battery server, we use the charging allowed signal from client to
- * indicate whether external power is present.
- *
- * In most cases, this actually matches the external power status of the client
- * (server battery charging when AC is connected, or discharging when server
- * battery still has enough capacity), with one exception: when we do client to
- * server battery charging (in this case the "external" power is the client).
- */
-int extpower_is_present(void)
-{
-	return charging_allowed;
-}
-#endif
-
-void ec_ec_comm_server_task(void *u)
-{
-	struct ec_host_request4 header;
-	/*
-	 * If CONFIG_HOSTCMD_ALIGNED is set, it is important that params is
-	 * aligned on a 32-bit boundary.
-	 */
-	uint8_t __aligned(4) params[COMMAND_BUFFER_PARAMS_SIZE];
-	unsigned int len, seq = 0, hascrc, cmdver;
-	uint32_t start;
-
-	while (1) {
-		task_wait_event(-1);
-
-		if (queue_count(&ec_ec_comm_server_input) == 0)
-			continue;
-
-		/* We got some data, start timeout counter. */
-		start = __hw_clock_source_read();
-
-		/* Wait for whole header to be available and read it. */
-		if (read_data(&header, sizeof(header), start)) {
-			CPRINTS("%s timeout (header)", __func__);
-			goto discard;
-		}
-
-#ifdef EXTRA_DEBUG
-		CPRINTS("%s f0=%02x f1=%02x cmd=%02x, length=%d", __func__,
-			header.fields0, header.fields1,
-			header.command, header.data_len);
-#endif
-
-		/* Ignore response (we wrote that ourselves) */
-		if (header.fields0 & EC_PACKET4_0_IS_RESPONSE_MASK)
-			goto discard;
-
-		/* Validate version and crc. */
-		if ((header.fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) != 4 ||
-		    header.header_crc !=
-			    cros_crc8((uint8_t *)&header, sizeof(header) - 1)) {
-			CPRINTS("%s header/crc error", __func__);
-			goto discard;
-		}
-
-		len = header.data_len;
-		hascrc = header.fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
-		if (hascrc)
-			len += 1;
-
-		/*
-		 * Ignore commands that are too long to fit in our buffer.
-		 */
-		if (len > sizeof(params)) {
-			CPRINTS("%s len error (%d)", __func__, len);
-			/* Discard the data first, then write error back. */
-			discard_queue();
-			write_response(EC_RES_OVERFLOW, seq, NULL, 0);
-			goto discard;
-		}
-
-		seq = (header.fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-			EC_PACKET4_0_SEQ_NUM_SHIFT;
-
-		cmdver = header.fields1 & EC_PACKET4_1_COMMAND_VERSION_MASK;
-
-		/* Wait for the rest of the data to be available and read it. */
-		if (read_data(params, len, start)) {
-			CPRINTS("%s timeout (data)", __func__);
-			goto discard;
-		}
-
-		/* Check data CRC */
-		if (hascrc && params[len-1] != cros_crc8(params, len-1)) {
-			CPRINTS("%s data crc error", __func__);
-			write_response(EC_RES_INVALID_CHECKSUM, seq, NULL, 0);
-			goto discard;
-		}
-
-		/* For now, all commands have version 0. */
-		if (cmdver != 0) {
-			CPRINTS("%s bad command version", __func__);
-			write_response(EC_RES_INVALID_VERSION, seq, NULL, 0);
-			continue;
-		}
-
-		switch (header.command) {
-#ifdef CONFIG_EC_EC_COMM_BATTERY
-		case EC_CMD_BATTERY_GET_STATIC:
-			/* Note that we ignore the battery index parameter. */
-			write_response(EC_RES_SUCCESS, seq,
-				&battery_static[BATT_IDX_MAIN],
-				sizeof(battery_static[BATT_IDX_MAIN]));
-			break;
-		case EC_CMD_BATTERY_GET_DYNAMIC:
-			/* Note that we ignore the battery index parameter. */
-			write_response(EC_RES_SUCCESS, seq,
-				&battery_dynamic[BATT_IDX_MAIN],
-				sizeof(battery_dynamic[BATT_IDX_MAIN]));
-			break;
-		case EC_CMD_CHARGER_CONTROL:
-			handle_cmd_charger_control((void *)params,
-						header.data_len, seq);
-			break;
-#endif
-		case EC_CMD_REBOOT_EC:
-			handle_cmd_reboot_ec((void *)params,
-						header.data_len, seq);
-			break;
-		default:
-			write_response(EC_RES_INVALID_COMMAND, seq,
-				NULL, 0);
-		}
-
-		continue;
-discard:
-		/*
-		 * Some error occurred: discard all data in the queue.
-		 */
-		discard_queue();
-	}
-}
diff --git a/common/espi.c b/common/espi.c
deleted file mode 100644
index 0a747d3bda..0000000000
--- a/common/espi.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* eSPI common functionality for Chrome EC */
-
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "espi.h"
-#include "timer.h"
-#include "util.h"
-
-
-const char *espi_vw_names[] = {
-	"VW_SLP_S3_L",
-	"VW_SLP_S4_L",
-	"VW_SLP_S5_L",
-	"VW_SUS_STAT_L",
-	"VW_PLTRST_L",
-	"VW_OOB_RST_WARN",
-	"VW_OOB_RST_ACK",
-	"VW_WAKE_L",
-	"VW_PME_L",
-	"VW_ERROR_FATAL",
-	"VW_ERROR_NON_FATAL",
-	/* Merge bit 3/0 into one signal. Need to set them simultaneously */
-	"VW_PERIPHERAL_BTLD_STATUS_DONE",
-	"VW_SCI_L",
-	"VW_SMI_L",
-	"VW_RCIN_L",
-	"VW_HOST_RST_ACK",
-	"VW_HOST_RST_WARN",
-	"VW_SUS_ACK",
-	"VW_SUS_WARN_L",
-	"VW_SUS_PWRDN_ACK_L",
-	"VW_SLP_A_L",
-	"VW_SLP_LAN",
-	"VW_SLP_WLAN",
-};
-BUILD_ASSERT(ARRAY_SIZE(espi_vw_names) == VW_SIGNAL_COUNT);
-
-
-const char *espi_vw_get_wire_name(enum espi_vw_signal signal)
-{
-	if (espi_signal_is_vw(signal))
-		return espi_vw_names[signal - VW_SIGNAL_START];
-
-	return NULL;
-}
-
-
-int espi_signal_is_vw(int signal)
-{
-	return ((signal >= VW_SIGNAL_START) && (signal < VW_SIGNAL_END));
-}
diff --git a/common/event_log.c b/common/event_log.c
deleted file mode 100644
index 95e44413bc..0000000000
--- a/common/event_log.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "event_log.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Event log FIFO */
-#define UNIT_SIZE sizeof(struct event_log_entry)
-#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE/UNIT_SIZE)
-#define UNIT_COUNT_MASK		(UNIT_COUNT - 1)
-static struct event_log_entry __bss_slow log_events[UNIT_COUNT];
-BUILD_ASSERT(POWER_OF_TWO(UNIT_COUNT));
-
-/*
- * The FIFO pointers are defined as following :
- * "log_head" is the next available event to dequeue.
- * "log_tail" is marking the end of the FIFO content (after last committed
- *  event)
- * "log_tail_next" is the next available spot to enqueue events.
- * The pointers are not wrapped until they are used, so we don't need an extra
- * entry to disambiguate between full and empty FIFO.
- *
- * For concurrency, several tasks might try to enqueue events in parallel with
- * log_add_event(). Only one task is dequeuing events (host commands, VDM,
- * TPM command handler). When the FIFO is full, log_add_event() will discard
- * the oldest events, so "log_head" is incremented/decremented in a critical
- * section since it is accessed from both log_add_event() and
- * log_dequeue_event(). log_tail_next is also protected as several writers can
- * race to add an event to the queue.
- * When a writer is done adding its event, it is updating log_tail,
- * so the event can be consumed by log_dequeue_event().
- */
-static size_t log_head;
-static size_t log_tail;
-static size_t log_tail_next;
-
-/* Size of one FIFO entry */
-#define ENTRY_SIZE(payload_sz) (1+DIV_ROUND_UP((payload_sz), UNIT_SIZE))
-
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-			  void *payload, uint32_t timestamp)
-{
-	struct event_log_entry *r;
-	size_t payload_size = EVENT_LOG_SIZE(size);
-	size_t total_size = ENTRY_SIZE(payload_size);
-	size_t current_tail, first;
-	uint32_t lock_key;
-
-	/* --- critical section : reserve queue space --- */
-	lock_key = irq_lock();
-	current_tail = log_tail_next;
-	log_tail_next = current_tail + total_size;
-	irq_unlock(lock_key);
-	/* --- end of critical section --- */
-
-	/* Out of space : discard the oldest entry */
-	while ((UNIT_COUNT - (current_tail - log_head)) < total_size) {
-		struct event_log_entry *oldest;
-		/* --- critical section : atomically free-up space --- */
-		lock_key = irq_lock();
-		oldest = log_events + (log_head & UNIT_COUNT_MASK);
-		log_head += ENTRY_SIZE(EVENT_LOG_SIZE(oldest->size));
-		irq_unlock(lock_key);
-		/* --- end of critical section --- */
-	}
-
-	r = log_events + (current_tail & UNIT_COUNT_MASK);
-
-	r->timestamp = timestamp;
-	r->type = type;
-	r->size = size;
-	r->data = data;
-	/* copy the payload into the FIFO */
-	first = MIN(total_size - 1, (UNIT_COUNT -
-		    (current_tail & UNIT_COUNT_MASK)) - 1);
-	if (first)
-		memcpy(r->payload, payload, first * UNIT_SIZE);
-	if (first < total_size - 1)
-		memcpy(log_events, ((uint8_t *)payload) + first * UNIT_SIZE,
-			(total_size - first) * UNIT_SIZE);
-	/* mark the entry available in the queue if nobody is behind us */
-	if (current_tail == log_tail)
-		log_tail = log_tail_next;
-}
-
-int log_dequeue_event(struct event_log_entry *r)
-{
-	uint32_t now = get_time().val >> EVENT_LOG_TIMESTAMP_SHIFT;
-	unsigned int total_size, first;
-	struct event_log_entry *entry;
-	size_t current_head;
-	uint32_t lock_key;
-
-retry:
-	current_head = log_head;
-	/* The log FIFO is empty */
-	if (log_tail == current_head) {
-		memset(r, 0, UNIT_SIZE);
-		r->type = EVENT_LOG_NO_ENTRY;
-		return UNIT_SIZE;
-	}
-
-	entry = log_events + (current_head & UNIT_COUNT_MASK);
-	total_size = ENTRY_SIZE(EVENT_LOG_SIZE(entry->size));
-	first = MIN(total_size, UNIT_COUNT - (current_head & UNIT_COUNT_MASK));
-	memcpy(r, entry, first * UNIT_SIZE);
-	if (first < total_size)
-		memcpy(r + first, log_events, (total_size-first) * UNIT_SIZE);
-
-	/* --- critical section : remove the entry from the queue --- */
-	lock_key = irq_lock();
-	if (log_head != current_head) { /* our entry was thrown away */
-		irq_unlock(lock_key);
-		goto retry;
-	}
-	log_head += total_size;
-	irq_unlock(lock_key);
-	/* --- end of critical section --- */
-
-	/* fixup the timestamp : number of milliseconds in the past */
-	r->timestamp = now - r->timestamp;
-
-	return total_size * UNIT_SIZE;
-}
-
-#ifdef CONFIG_CMD_DLOG
-/*
- * Display TPM event logs.
- */
-static int command_dlog(int argc, char **argv)
-{
-	size_t log_cur;
-	const uint8_t * const log_events_end =
-		(uint8_t *)&log_events[UNIT_COUNT];
-
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "clear")) {
-			interrupt_disable();
-			log_head = log_tail = log_tail_next = 0;
-			interrupt_enable();
-
-			return EC_SUCCESS;
-		}
-		/* Too many parameters */
-		return EC_ERROR_PARAM1;
-	}
-
-	ccprintf(" TIMESTAMP | TYPE |  DATA | SIZE | PAYLOAD\n");
-	log_cur = log_head;
-	while (log_cur != log_tail) {
-		struct event_log_entry *r;
-		uint8_t *payload;
-		uint32_t payload_bytes;
-
-		r = &log_events[log_cur & UNIT_COUNT_MASK];
-		payload_bytes = EVENT_LOG_SIZE(r->size);
-		log_cur += ENTRY_SIZE(payload_bytes);
-
-		ccprintf("%10d   %4d  0x%04X   %4d   ", r->timestamp, r->type,
-			r->data, payload_bytes);
-
-		/* display payload if exists */
-		payload = r->payload;
-		while (payload_bytes--) {
-			if (payload >= log_events_end)
-				payload = (uint8_t *)&log_events[0];
-
-			ccprintf("%02X", *payload);
-			payload++;
-		}
-		ccprintf("\n");
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(dlog,
-			command_dlog,
-			"[clear]",
-			"Display/clear TPM event logs");
-#endif
diff --git a/common/extpower_common.c b/common/extpower_common.c
deleted file mode 100644
index 9021b77626..0000000000
--- a/common/extpower_common.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "extpower.h"
-#include "hooks.h"
-#include "host_command.h"
-
-__overridable void board_check_extpower(void)
-{
-}
-
-void extpower_handle_update(int is_present)
-{
-	uint8_t *memmap_batt_flags;
-
-	hook_notify(HOOK_AC_CHANGE);
-	memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-
-	/* Forward notification to host */
-	if (is_present) {
-		*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-		host_set_single_event(EC_HOST_EVENT_AC_CONNECTED);
-	} else {
-		*memmap_batt_flags &= ~EC_BATT_FLAG_AC_PRESENT;
-		host_set_single_event(EC_HOST_EVENT_AC_DISCONNECTED);
-	}
-}
diff --git a/common/extpower_gpio.c b/common/extpower_gpio.c
deleted file mode 100644
index 4cdcb834f8..0000000000
--- a/common/extpower_gpio.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Pure GPIO-based external power detection */
-
-#include "common.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "timer.h"
-
-static int debounced_extpower_presence;
-
-int extpower_is_present(void)
-{
-	return debounced_extpower_presence;
-}
-
-/**
- * Deferred function to handle external power change
- */
-static void extpower_deferred(void)
-{
-	int extpower_presence = gpio_get_level(GPIO_AC_PRESENT);
-
-	if (extpower_presence == debounced_extpower_presence)
-		return;
-
-	debounced_extpower_presence = extpower_presence;
-	extpower_handle_update(extpower_presence);
-
-}
-DECLARE_DEFERRED(extpower_deferred);
-
-void extpower_interrupt(enum gpio_signal signal)
-{
-	/* Trigger deferred notification of external power change */
-	hook_call_deferred(&extpower_deferred_data,
-			CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC);
-}
-
-static void extpower_init(void)
-{
-	uint8_t *memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
-
-	debounced_extpower_presence = gpio_get_level(GPIO_AC_PRESENT);
-
-	/* Initialize the memory-mapped AC_PRESENT flag */
-	if (debounced_extpower_presence)
-		*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
-	else
-		*memmap_batt_flags &= ~EC_BATT_FLAG_AC_PRESENT;
-
-	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_AC_PRESENT);
-}
-DECLARE_HOOK(HOOK_INIT, extpower_init, HOOK_PRIO_INIT_EXTPOWER);
diff --git a/common/fan.c b/common/fan.c
deleted file mode 100644
index 636bec04f9..0000000000
--- a/common/fan.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Basic Chrome OS fan control */
-
-#include "assert.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "printf.h"
-#include "system.h"
-#include "util.h"
-
-/* True if we're listening to the thermal control task. False if we're setting
- * things manually. */
-static int thermal_control_enabled[CONFIG_FANS];
-
-int is_thermal_control_enabled(int idx)
-{
-	return thermal_control_enabled[idx];
-}
-
-#ifdef CONFIG_FAN_UPDATE_PERIOD
-/* Should we ignore the fans for a while? */
-static int fan_update_counter[CONFIG_FANS];
-#endif
-
-/*
- * Number of fans.
- *
- * Use fan_get_count and fan_set_count to access it. It should be set only
- * before HOOK_INIT/HOOK_PRIO_DEFAULT.
- */
-static int fan_count = CONFIG_FANS;
-
-int fan_get_count(void)
-{
-	return fan_count;
-}
-
-void fan_set_count(int count)
-{
-	/* You can only decrease the count. */
-	assert(count <= CONFIG_FANS);
-	fan_count = count;
-}
-
-#ifndef CONFIG_FAN_RPM_CUSTOM
-/* This is the default implementation. It's only called over [0,100].
- * Convert the percentage to a target RPM. We can't simply scale all
- * the way down to zero because most fans won't turn that slowly, so
- * we'll map [1,100] => [FAN_MIN,FAN_MAX], and [0] => "off".
-*/
-int fan_percent_to_rpm(int fan, int pct)
-{
-	int rpm, max, min;
-
-	if (!pct) {
-		rpm = 0;
-	} else {
-		min = fans[fan].rpm->rpm_min;
-		max = fans[fan].rpm->rpm_max;
-		rpm = ((pct - 1) * max + (100 - pct) * min) / 99;
-	}
-
-	return rpm;
-}
-#endif	/* CONFIG_FAN_RPM_CUSTOM */
-
-/* The thermal task will only call this function with pct in [0,100]. */
-test_mockable void fan_set_percent_needed(int fan, int pct)
-{
-	int actual_rpm, new_rpm;
-
-	if (!is_thermal_control_enabled(fan))
-		return;
-
-#ifdef CONFIG_FAN_UPDATE_PERIOD
-	/* Only set each fan every so often, to avoid rapid changes. */
-	fan_update_counter[fan] %= CONFIG_FAN_UPDATE_PERIOD;
-	if (fan_update_counter[fan]++)
-		return;
-#endif
-
-	new_rpm = fan_percent_to_rpm(fan, pct);
-	actual_rpm = fan_get_rpm_actual(FAN_CH(fan));
-
-	/* If we want to turn and the fans are currently significantly below
-	 * the minimum turning speed, we should turn at least as fast as the
-	 * necessary start speed instead. */
-	if (new_rpm &&
-	    actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
-	    new_rpm < fans[fan].rpm->rpm_start)
-		new_rpm = fans[fan].rpm->rpm_start;
-
-	fan_set_rpm_target(FAN_CH(fan), new_rpm);
-}
-
-static void set_enabled(int fan, int enable)
-{
-	fan_set_enabled(FAN_CH(fan), enable);
-
-	if (fans[fan].conf->enable_gpio >= 0)
-		gpio_set_level(fans[fan].conf->enable_gpio, enable);
-}
-
-test_export_static void set_thermal_control_enabled(int fan, int enable)
-{
-	thermal_control_enabled[fan] = enable;
-
-	/* If controlling the fan, need it in RPM-control mode */
-	if (enable)
-		fan_set_rpm_mode(FAN_CH(fan), 1);
-}
-
-static void set_duty_cycle(int fan, int percent)
-{
-	/* Move the fan to manual control */
-	fan_set_rpm_mode(FAN_CH(fan), 0);
-
-	/* enable the fan when non-zero duty */
-	set_enabled(fan, (percent > 0) ? 1 : 0);
-
-	/* Disable thermal engine automatic fan control. */
-	set_thermal_control_enabled(fan, 0);
-
-	/* Set the duty cycle */
-	fan_set_duty(FAN_CH(fan), percent);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int cc_fanauto(int argc, char **argv)
-{
-	char *e;
-	int fan = 0;
-
-	if (fan_count > 1) {
-		if (argc < 2) {
-			ccprintf("fan number is required as the first arg\n");
-			return EC_ERROR_PARAM_COUNT;
-		}
-		fan = strtoi(argv[1], &e, 0);
-		if (*e || fan >= fan_count)
-			return EC_ERROR_PARAM1;
-		argc--;
-		argv++;
-	}
-
-	set_thermal_control_enabled(fan, 1);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto,
-			"{fan}",
-			"Enable thermal fan control");
-
-/* Return 0 for off, 1 for on, -1 for unknown */
-static int is_powered(int fan)
-{
-	int is_pgood = -1;
-
-	/* If we have an enable output, see if it's on or off. */
-	if (fans[fan].conf->enable_gpio >= 0)
-		is_pgood = gpio_get_level(fans[fan].conf->enable_gpio);
-	/* If we have a pgood input, it overrides any enable output. */
-	if (fans[fan].conf->pgood_gpio >= 0)
-		is_pgood = gpio_get_level(fans[fan].conf->pgood_gpio);
-
-	return is_pgood;
-}
-
-static int cc_faninfo(int argc, char **argv)
-{
-	static const char * const human_status[] = {
-		"not spinning", "changing", "locked", "frustrated"
-	};
-	int tmp, is_pgood;
-	int fan;
-	char leader[20] = "";
-	for (fan = 0; fan < fan_count; fan++) {
-		if (fan_count > 1)
-			snprintf(leader, sizeof(leader), "Fan %d ", fan);
-		if (fan)
-			ccprintf("\n");
-		ccprintf("%sActual: %4d rpm\n", leader,
-			 fan_get_rpm_actual(FAN_CH(fan)));
-		ccprintf("%sTarget: %4d rpm\n", leader,
-			 fan_get_rpm_target(FAN_CH(fan)));
-		ccprintf("%sDuty:   %d%%\n", leader,
-			 fan_get_duty(FAN_CH(fan)));
-		tmp = fan_get_status(FAN_CH(fan));
-		ccprintf("%sStatus: %d (%s)\n", leader,
-			 tmp, human_status[tmp]);
-		ccprintf("%sMode:   %s\n", leader,
-			 fan_get_rpm_mode(FAN_CH(fan)) ? "rpm" : "duty");
-		ccprintf("%sAuto:   %s\n", leader,
-			 is_thermal_control_enabled(fan) ? "yes" : "no");
-		ccprintf("%sEnable: %s\n", leader,
-			 fan_get_enabled(FAN_CH(fan)) ? "yes" : "no");
-		is_pgood = is_powered(fan);
-		if (is_pgood >= 0)
-			ccprintf("%sPower:  %s\n", leader,
-				 is_pgood ? "yes" : "no");
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo,
-			NULL,
-			"Print fan info");
-
-static int cc_fanset(int argc, char **argv)
-{
-	const char *rpm_str;
-	int rpm;
-	char *e;
-	int fan = 0;
-
-	if (fan_count == 0) {
-		ccprintf("Fan count is zero\n");
-		return EC_ERROR_INVAL;
-	}
-
-	if (fan_count > 1) {
-		if (argc < 3) {
-			ccprintf("fan number is required as the first arg\n");
-			return EC_ERROR_PARAM_COUNT;
-		}
-	}
-
-	if (argc == 3) {
-		fan = strtoi(argv[1], &e, 0);
-		if (*e || fan >= fan_count)
-			return EC_ERROR_PARAM1;
-		rpm_str = argv[2];
-	} else if (argc == 2) {
-		rpm_str = argv[1];
-	} else {
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	rpm = strtoi(rpm_str, &e, 0);
-	if (*e == '%') {		/* Wait, that's a percentage */
-		ccprintf("Fan rpm given as %d%%\n", rpm);
-		if (rpm < 0)
-			rpm = 0;
-		else if (rpm > 100)
-			rpm = 100;
-		rpm = fan_percent_to_rpm(fan, rpm);
-	} else if (*e) {
-		return EC_ERROR_PARAM1;
-	}
-
-	/* Move the fan to automatic control */
-	fan_set_rpm_mode(FAN_CH(fan), 1);
-
-	/* enable the fan when non-zero rpm */
-	set_enabled(fan, (rpm > 0) ? 1 : 0);
-
-	/* Disable thermal engine automatic fan control. */
-	set_thermal_control_enabled(fan, 0);
-
-	fan_set_rpm_target(FAN_CH(fan), rpm);
-
-	ccprintf("Setting fan %d rpm target to %d\n", fan, rpm);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fanset, cc_fanset,
-			"[fan] (rpm | pct%)",
-			"Set fan speed");
-
-static int cc_fanduty(int argc, char **argv)
-{
-	const char *percent_str;
-	int percent = 0;
-	char *e;
-	int fan = 0;
-
-	if (fan_count == 0) {
-		ccprintf("Fan count is zero\n");
-		return EC_ERROR_INVAL;
-	}
-
-	if (fan_count > 1) {
-		if (argc < 3) {
-			ccprintf("fan number is required as the first arg\n");
-			return EC_ERROR_PARAM_COUNT;
-		}
-	}
-
-	if (argc == 3) {
-		fan = strtoi(argv[1], &e, 0);
-		if (*e || fan >= fan_count)
-			return EC_ERROR_PARAM1;
-		percent_str = argv[2];
-	} else if (argc == 2) {
-		percent_str = argv[1];
-	} else {
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	percent = strtoi(percent_str, &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	ccprintf("Setting fan %d duty cycle to %d%%\n", fan, percent);
-	set_duty_cycle(fan, percent);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty,
-			"[fan] percent",
-			"Set fan duty cycle");
-
-/*****************************************************************************/
-/* DPTF interface functions */
-
-/* 0-100% if in duty mode. -1 if not */
-int dptf_get_fan_duty_target(void)
-{
-	int fan = 0;				/* TODO(crosbug.com/p/23803) */
-
-	if (fan_count == 0)
-		return -1;
-
-	if (is_thermal_control_enabled(fan) || fan_get_rpm_mode(FAN_CH(fan)))
-		return -1;
-
-	return fan_get_duty(FAN_CH(fan));
-}
-
-/* 0-100% sets duty, out of range means let the EC drive */
-void dptf_set_fan_duty_target(int pct)
-{
-	int fan;
-
-	if (pct < 0 || pct > 100) {
-		/* TODO(crosbug.com/p/23803) */
-		for (fan = 0; fan < fan_count; fan++)
-			set_thermal_control_enabled(fan, 1);
-	} else {
-		/* TODO(crosbug.com/p/23803) */
-		for (fan = 0; fan < fan_count; fan++)
-			set_duty_cycle(fan, pct);
-	}
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-hc_pwm_get_fan_target_rpm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_pwm_get_fan_rpm *r = args->response;
-
-	if (fan_count == 0)
-		return EC_RES_ERROR;
-
-	/* TODO(crosbug.com/p/23803) */
-	r->rpm = fan_get_rpm_target(FAN_CH(0));
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM,
-		     hc_pwm_get_fan_target_rpm,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_fan_target_rpm_v1 *p_v1 = args->params;
-	const struct ec_params_pwm_set_fan_target_rpm_v0 *p_v0 = args->params;
-	int fan;
-
-	if (args->version == 0) {
-		for (fan = 0; fan < fan_count; fan++) {
-			/* enable the fan if rpm is non-zero */
-			set_enabled(fan, (p_v0->rpm > 0) ? 1 : 0);
-
-			set_thermal_control_enabled(fan, 0);
-			fan_set_rpm_mode(FAN_CH(fan), 1);
-			fan_set_rpm_target(FAN_CH(fan), p_v0->rpm);
-		}
-
-		return EC_RES_SUCCESS;
-	}
-
-	fan = p_v1->fan_idx;
-	if (fan >= fan_count)
-		return EC_RES_ERROR;
-
-	/* enable the fan if rpm is non-zero */
-	set_enabled(fan, (p_v1->rpm > 0) ? 1 :0);
-
-	set_thermal_control_enabled(fan, 0);
-	fan_set_rpm_mode(FAN_CH(fan), 1);
-	fan_set_rpm_target(FAN_CH(fan), p_v1->rpm);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM,
-		     hc_pwm_set_fan_target_rpm,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_fan_duty_v1 *p_v1 = args->params;
-	const struct ec_params_pwm_set_fan_duty_v0 *p_v0 = args->params;
-	int fan;
-
-	if (args->version == 0) {
-		for (fan = 0; fan < fan_count; fan++)
-			set_duty_cycle(fan, p_v0->percent);
-
-		return EC_RES_SUCCESS;
-	}
-
-	fan = p_v1->fan_idx;
-	if (fan >= fan_count)
-		return EC_RES_ERROR;
-
-	set_duty_cycle(fan, p_v1->percent);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY,
-		     hc_pwm_set_fan_duty,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static enum ec_status
-hc_thermal_auto_fan_ctrl(struct host_cmd_handler_args *args)
-{
-	int fan;
-	const struct ec_params_auto_fan_ctrl_v1 *p_v1 = args->params;
-
-	if (args->version == 0) {
-		for (fan = 0; fan < fan_count; fan++)
-			set_thermal_control_enabled(fan, 1);
-
-		return EC_RES_SUCCESS;
-	}
-
-	fan = p_v1->fan_idx;
-	if (fan >= fan_count)
-		return EC_RES_ERROR;
-
-	set_thermal_control_enabled(fan, 1);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL,
-		     hc_thermal_auto_fan_ctrl,
-		     EC_VER_MASK(0)|EC_VER_MASK(1));
-
-
-/*****************************************************************************/
-/* Hooks */
-
-/* We only have a limited number of memory-mapped slots to report fan speed to
- * the AP. If we have more fans than that, some will be inaccessible. But
- * if we're using that many fans, we probably have bigger problems.
- */
-BUILD_ASSERT(CONFIG_FANS <= EC_FAN_SPEED_ENTRIES);
-
-#define PWMFAN_SYSJUMP_TAG 0x5046  /* "PF" */
-#define PWM_HOOK_VERSION 1
-/* Saved PWM state across sysjumps */
-struct pwm_fan_state {
-	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
-	uint16_t rpm;
-	uint8_t flag;	/* FAN_STATE_FLAG_* */
-};
-
-/* For struct pwm_fan_state.flag */
-#define FAN_STATE_FLAG_ENABLED	BIT(0)
-#define FAN_STATE_FLAG_THERMAL	BIT(1)
-
-static void pwm_fan_init(void)
-{
-	const struct pwm_fan_state *prev;
-	struct pwm_fan_state state;
-	uint16_t *mapped;
-	int version, size;
-	int i;
-	int fan;
-
-	if (fan_count == 0)
-		return;
-
-	for (fan = 0; fan < fan_count; fan++)
-		fan_channel_setup(FAN_CH(fan), fans[fan].conf->flags);
-
-	/* Restore previous state. */
-	prev = (const struct pwm_fan_state *)
-		system_get_jump_tag(PWMFAN_SYSJUMP_TAG, &version, &size);
-	if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev)) {
-		memcpy(&state, prev, sizeof(state));
-	} else {
-		memset(&state, 0, sizeof(state));
-	}
-
-	for (fan = 0; fan < fan_count; fan++) {
-		fan_set_enabled(FAN_CH(fan),
-				state.flag & FAN_STATE_FLAG_ENABLED);
-		fan_set_rpm_target(FAN_CH(fan), state.rpm);
-		set_thermal_control_enabled(
-				fan, state.flag & FAN_STATE_FLAG_THERMAL);
-	}
-
-	/* Initialize memory-mapped data */
-	mapped = (uint16_t *)host_get_memmap(EC_MEMMAP_FAN);
-	for (i = 0; i < EC_FAN_SPEED_ENTRIES; i++)
-		mapped[i] = EC_FAN_SPEED_NOT_PRESENT;
-}
-DECLARE_HOOK(HOOK_INIT, pwm_fan_init, HOOK_PRIO_DEFAULT);
-
-static void pwm_fan_second(void)
-{
-	uint16_t *mapped = (uint16_t *)host_get_memmap(EC_MEMMAP_FAN);
-	uint16_t rpm;
-	int stalled = 0;
-	int fan;
-
-	for (fan = 0; fan < fan_count; fan++) {
-		if (fan_is_stalled(FAN_CH(fan))) {
-			rpm = EC_FAN_SPEED_STALLED;
-			stalled = 1;
-			cprints(CC_PWM, "Fan %d stalled!", fan);
-		} else {
-			rpm = fan_get_rpm_actual(FAN_CH(fan));
-		}
-
-		mapped[fan] = rpm;
-	}
-
-	/*
-	 * Issue warning.  As we have thermal shutdown
-	 * protection, issuing warning here should be enough.
-	 */
-	if (stalled)
-		host_set_single_event(EC_HOST_EVENT_THERMAL);
-}
-DECLARE_HOOK(HOOK_SECOND, pwm_fan_second, HOOK_PRIO_DEFAULT);
-
-static void pwm_fan_preserve_state(void)
-{
-	struct pwm_fan_state state = {0};
-	int fan = 0;
-
-	if (fan_count == 0)
-		return;
-
-	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
-	if (fan_get_enabled(FAN_CH(fan)))
-		state.flag |= FAN_STATE_FLAG_ENABLED;
-	if (is_thermal_control_enabled(fan))
-		state.flag |= FAN_STATE_FLAG_THERMAL;
-	state.rpm = fan_get_rpm_target(FAN_CH(fan));
-
-	system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, pwm_fan_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void pwm_fan_control(int enable)
-{
-	int fan;
-
-	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
-	for (fan = 0; fan < fan_count; fan++) {
-		set_thermal_control_enabled(fan, enable);
-		fan_set_rpm_target(FAN_CH(fan), enable ?
-			fan_percent_to_rpm(FAN_CH(fan), CONFIG_FAN_INIT_SPEED) :
-			0);
-		set_enabled(fan, enable);
-	}
-}
-
-static void pwm_fan_stop(void)
-{
-	/*
-	 * There is no need to cool CPU in S3 or S5. We currently don't
-	 * have fans for battery or charger chip. Battery systems will
-	 * control charge current based on its own temperature readings.
-	 * Thus, we do not need to keep fans running in S3 or S5.
-	 *
-	 * Even with a fan on charging system, it's questionable to run
-	 * a fan in S3/S5. Under an extreme heat condition, spinning a
-	 * fan would create more heat as it draws current from a
-	 * battery and heat would come from ambient air instead of CPU.
-	 *
-	 * Thermal control may be already disabled if DPTF is used.
-	 */
-	pwm_fan_control(0); /* crosbug.com/p/8097 */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, pwm_fan_stop, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pwm_fan_stop, HOOK_PRIO_DEFAULT);
-
-static void pwm_fan_start(void)
-{
-	/*
-	 * Even if the DPTF is enabled, enable thermal control here.
-	 * Upon booting to S0, if needed AP will disable/throttle it using
-	 * host commands.
-	 */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON))
-		pwm_fan_control(1);
-}
-/* On Fizz, CHIPSET_RESUME isn't triggered when AP warm resets.
- * So we hook CHIPSET_RESET instead.
- */
-DECLARE_HOOK(HOOK_CHIPSET_RESET, pwm_fan_start, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pwm_fan_start, HOOK_PRIO_DEFAULT);
diff --git a/common/flash.c b/common/flash.c
deleted file mode 100644
index c8f58a82af..0000000000
--- a/common/flash.c
+++ /dev/null
@@ -1,1562 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Flash memory module for Chrome EC - common functions */
-
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "otp.h"
-#include "rwsig.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "util.h"
-#include "vboot_hash.h"
-
-/*
- * Contents of erased flash, as a 32-bit value.  Most platforms erase flash
- * bits to 1.
- */
-#ifndef CONFIG_FLASH_ERASED_VALUE32
-#define CONFIG_FLASH_ERASED_VALUE32 (-1U)
-#endif
-
-#ifdef CONFIG_FLASH_PSTATE
-
-/*
- * If flash isn't mapped to the EC's address space, it's probably SPI, and
- * should be using SPI write protect, not PSTATE.
- */
-#if !defined(CONFIG_INTERNAL_STORAGE) || !defined(CONFIG_MAPPED_STORAGE)
-#error "PSTATE should only be used with internal mem-mapped flash."
-#endif
-
-#ifdef CONFIG_FLASH_PSTATE_BANK
-/* Persistent protection state - emulates a SPI status register for flashrom */
-/* NOTE: It's not expected that RO and RW will support
- * differing PSTATE versions. */
-#define PERSIST_STATE_VERSION 3  /* Expected persist_state.version */
-
-/* Flags for persist_state.flags */
-/* Protect persist state and RO firmware at boot */
-#define PERSIST_FLAG_PROTECT_RO 0x02
-#define PSTATE_VALID_FLAGS      BIT(0)
-#define PSTATE_VALID_SERIALNO   BIT(1)
-#define PSTATE_VALID_MAC_ADDR   BIT(2)
-
-struct persist_state {
-	uint8_t version;            /* Version of this struct */
-	uint8_t flags;              /* Lock flags (PERSIST_FLAG_*) */
-	uint8_t valid_fields;       /* Flags for valid data. */
-	uint8_t reserved;           /* Reserved; set 0 */
-#ifdef CONFIG_SERIALNO_LEN
-	uint8_t serialno[CONFIG_SERIALNO_LEN]; /* Serial number. */
-#endif /* CONFIG_SERIALNO_LEN */
-#ifdef CONFIG_MAC_ADDR_LEN
-	uint8_t mac_addr[CONFIG_MAC_ADDR_LEN];
-#endif /* CONFIG_MAC_ADDR_LEN */
-#if !defined(CONFIG_SERIALNO_LEN) && !defined(CONFIG_MAC_ADDR_LEN)
-	uint8_t padding[4 % CONFIG_FLASH_WRITE_SIZE];
-#endif
-};
-
-/* written with flash_physical_write, need to respect alignment constraints */
-#ifndef CHIP_FAMILY_STM32L /* STM32L1xx is somewhat lying to us */
-BUILD_ASSERT(sizeof(struct persist_state) % CONFIG_FLASH_WRITE_SIZE == 0);
-#endif
-
-BUILD_ASSERT(sizeof(struct persist_state) <= CONFIG_FW_PSTATE_SIZE);
-
-#else /* !CONFIG_FLASH_PSTATE_BANK */
-
-/*
- * Flags for write protect state depend on the erased value of flash.  The
- * locked value must be the same as the unlocked value with one or more bits
- * transitioned away from the erased state.  That way, it is possible to
- * rewrite the data in-place to set the lock.
- *
- * STM32F0x can only write 0x0000 to a non-erased half-word, which means
- * PSTATE_MAGIC_LOCKED isn't quite as pretty.  That's ok; the only thing
- * we actually need to detect is PSTATE_MAGIC_UNLOCKED, since that's the
- * only value we'll ever alter, and the only value which causes us not to
- * lock the flash at boot.
- */
-#if (CONFIG_FLASH_ERASED_VALUE32 == -1U)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x00000000  /* ""     */
-#elif (CONFIG_FLASH_ERASED_VALUE32 == 0)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x5f5f5057  /* "WP__" */
-#else
-/* What kind of wacky flash doesn't erase all bits to 1 or 0? */
-#error "PSTATE needs magic values for this flash architecture."
-#endif
-
-/*
- * Rewriting the write protect flag in place currently requires a minimum write
- * size <= the size of the flag value.
- *
- * We could work around this on chips with larger minimum write size by reading
- * the write block containing the flag into RAM, changing it to the locked
- * value, and then rewriting that block.  But we should only pay for that
- * complexity when we run across another chip which needs it.
- */
-#if (CONFIG_FLASH_WRITE_SIZE > 4)
-#error "Non-bank-based PSTATE requires flash write size <= 32 bits."
-#endif
-
-const uint32_t pstate_data __attribute__((section(".rodata.pstate"))) =
-#ifdef CONFIG_FLASH_PSTATE_LOCKED
-	PSTATE_MAGIC_LOCKED;
-#else
-	PSTATE_MAGIC_UNLOCKED;
-#endif
-
-#endif /* !CONFIG_FLASH_PSTATE_BANK */
-#endif /* CONFIG_FLASH_PSTATE */
-
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-const struct ec_flash_bank *flash_bank_info(int bank)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		if (bank < flash_bank_array[i].count)
-			return &flash_bank_array[i];
-		bank -= flash_bank_array[i].count;
-	}
-
-	return NULL;
-}
-
-int crec_flash_bank_size(int bank)
-{
-	int rv;
-	const struct ec_flash_bank *info = flash_bank_info(bank);
-
-	if (!info)
-		return -1;
-
-	rv = BIT(info->size_exp);
-	ASSERT(rv > 0);
-	return rv;
-}
-
-int crec_flash_bank_erase_size(int bank)
-{
-	int rv;
-	const struct ec_flash_bank *info = flash_bank_info(bank);
-
-	if (!info)
-		return -1;
-
-	rv = BIT(info->erase_size_exp);
-	ASSERT(rv > 0);
-	return rv;
-}
-
-int crec_flash_bank_index(int offset)
-{
-	int bank_offset = 0, i;
-
-	if (offset == 0)
-		return bank_offset;
-
-	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		int all_sector_size = flash_bank_array[i].count <<
-			flash_bank_array[i].size_exp;
-		if (offset >= all_sector_size) {
-			offset -= all_sector_size;
-			bank_offset += flash_bank_array[i].count;
-			continue;
-		}
-		if (offset & ((1 << flash_bank_array[i].size_exp) - 1))
-			return -1;
-		return bank_offset + (offset >> flash_bank_array[i].size_exp);
-	}
-	if (offset != 0)
-		return -1;
-	return bank_offset;
-}
-
-int crec_flash_bank_count(int offset, int size)
-{
-	int begin = crec_flash_bank_index(offset);
-	int end = crec_flash_bank_index(offset + size);
-
-	if (begin == -1 || end == -1)
-		return -1;
-	return end - begin;
-}
-
-int crec_flash_bank_start_offset(int bank)
-{
-	int i;
-	int offset;
-	int bank_size;
-
-	if (bank < 0)
-		return -1;
-
-	offset = 0;
-	for (i = 0; i < bank; i++) {
-		bank_size = crec_flash_bank_size(i);
-		if (bank_size < 0)
-			return -1;
-		offset += bank_size;
-	}
-
-	return offset;
-}
-
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
-
-static int flash_range_ok(int offset, int size_req, int align)
-{
-	if (offset < 0 || size_req < 0 ||
-	    offset > CONFIG_FLASH_SIZE_BYTES ||
-	    size_req > CONFIG_FLASH_SIZE_BYTES ||
-	    offset + size_req > CONFIG_FLASH_SIZE_BYTES ||
-	    (offset | size_req) & (align - 1))
-		return 0;  /* Invalid range */
-
-	return 1;
-}
-
-#ifdef CONFIG_MAPPED_STORAGE
-/**
- * Get the physical memory address of a flash offset
- *
- * This is used for direct flash access. We assume that the flash is
- * contiguous from this start address through to the end of the usable
- * flash.
- *
- * @param offset	Flash offset to get address of
- * @param dataptrp	Returns pointer to memory address of flash offset
- * @return pointer to flash memory offset, if ok, else NULL
- */
-static const char *flash_physical_dataptr(int offset)
-{
-	return (char *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE + offset);
-}
-
-int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp)
-{
-	if (!flash_range_ok(offset, size_req, align))
-		return -1;  /* Invalid range */
-	if (ptrp)
-		*ptrp = flash_physical_dataptr(offset);
-
-	return CONFIG_FLASH_SIZE_BYTES - offset;
-}
-#endif
-
-#ifdef CONFIG_FLASH_PSTATE
-#ifdef CONFIG_FLASH_PSTATE_BANK
-
-/**
- * Read and return persistent state flags (EC_FLASH_PROTECT_*)
- */
-static uint32_t flash_read_pstate(void)
-{
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	if ((pstate->version == PERSIST_STATE_VERSION) &&
-	    (pstate->valid_fields & PSTATE_VALID_FLAGS) &&
-	    (pstate->flags & PERSIST_FLAG_PROTECT_RO)) {
-		/* Lock flag is known to be set */
-		return EC_FLASH_PROTECT_RO_AT_BOOT;
-	} else {
-#ifdef CONFIG_WP_ALWAYS
-		return PERSIST_FLAG_PROTECT_RO;
-#else
-		return 0;
-#endif
-	}
-}
-
-/**
- * Write persistent state after erasing.
- *
- * @param pstate	New data to set in pstate. NOT memory mapped
- *                      old pstate as it will be erased.
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int flash_write_pstate_data(struct persist_state *newpstate)
-{
-	int rv;
-
-	/* Erase pstate */
-	rv = crec_flash_physical_erase(CONFIG_FW_PSTATE_OFF,
-				       CONFIG_FW_PSTATE_SIZE);
-	if (rv)
-		return rv;
-
-	/*
-	 * Note that if we lose power in here, we'll lose the pstate contents.
-	 * That's ok, because it's only possible to write the pstate before
-	 * it's protected.
-	 */
-
-	/* Write the updated pstate */
-	return crec_flash_physical_write(CONFIG_FW_PSTATE_OFF,
-					 sizeof(*newpstate),
-					 (const char *)newpstate);
-}
-
-
-
-/**
- * Validate and Init persistent state datastructure.
- *
- * @param pstate	A pstate data structure. Will be valid at complete.
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int validate_pstate_struct(struct persist_state *pstate)
-{
-	if (pstate->version != PERSIST_STATE_VERSION) {
-		memset(pstate, 0, sizeof(*pstate));
-		pstate->version = PERSIST_STATE_VERSION;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Write persistent state from pstate, erasing if necessary.
- *
- * @param flags		New flash write protect flags to set in pstate.
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int flash_write_pstate(uint32_t flags)
-{
-	struct persist_state newpstate;
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	/* Only check the flags we write to pstate */
-	flags &= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* Check if pstate has actually changed */
-	if (flags == flash_read_pstate())
-		return EC_SUCCESS;
-
-	/* Cache the old copy for read/modify/write. */
-	memcpy(&newpstate, pstate, sizeof(newpstate));
-	validate_pstate_struct(&newpstate);
-
-	if (flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		newpstate.flags |= PERSIST_FLAG_PROTECT_RO;
-	else
-		newpstate.flags &= ~PERSIST_FLAG_PROTECT_RO;
-	newpstate.valid_fields |= PSTATE_VALID_FLAGS;
-
-	return flash_write_pstate_data(&newpstate);
-}
-
-#ifdef CONFIG_SERIALNO_LEN
-/**
- * Read and return persistent serial number.
- */
-const char *crec_flash_read_pstate_serial(void)
-{
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	if ((pstate->version == PERSIST_STATE_VERSION) &&
-	    (pstate->valid_fields & PSTATE_VALID_SERIALNO)) {
-		return (const char *)(pstate->serialno);
-	}
-
-	return NULL;
-}
-
-/**
- * Write persistent serial number to pstate, erasing if necessary.
- *
- * @param serialno		New ascii serial number to set in pstate.
- * @return EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_write_pstate_serial(const char *serialno)
-{
-	int length;
-	struct persist_state newpstate;
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	/* Check that this is OK */
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	length = strnlen(serialno, sizeof(newpstate.serialno));
-	if (length >= sizeof(newpstate.serialno)) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Cache the old copy for read/modify/write. */
-	memcpy(&newpstate, pstate, sizeof(newpstate));
-	validate_pstate_struct(&newpstate);
-
-	/*
-	 * Erase any prior data and copy the string. The length was verified to
-	 * be shorter than the buffer so a null terminator always remains.
-	 */
-	memset(newpstate.serialno, '\0', sizeof(newpstate.serialno));
-	memcpy(newpstate.serialno, serialno, length);
-
-	newpstate.valid_fields |= PSTATE_VALID_SERIALNO;
-
-	return flash_write_pstate_data(&newpstate);
-}
-
-#endif /* CONFIG_SERIALNO_LEN */
-
-#ifdef CONFIG_MAC_ADDR_LEN
-
-/**
- * Read and return persistent MAC address.
- */
-const char *crec_flash_read_pstate_mac_addr(void)
-{
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	if ((pstate->version == PERSIST_STATE_VERSION) &&
-	    (pstate->valid_fields & PSTATE_VALID_MAC_ADDR)) {
-		return (const char *)(pstate->mac_addr);
-	}
-
-	return NULL;
-}
-
-/**
- * Write persistent MAC Addr to pstate, erasing if necessary.
- *
- * @param mac_addr		New ascii MAC address to set in pstate.
- * @return EC_SUCCESS, or nonzero if error.
- */
-int crec_flash_write_pstate_mac_addr(const char *mac_addr)
-{
-	int length;
-	struct persist_state newpstate;
-	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
-
-	/* Check that this is OK, data is valid and fits in the region. */
-	if (!mac_addr) {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * This will perform validation of the mac address before storing it.
-	 * The MAC address format is '12:34:56:78:90:AB', a 17 character long
-	 * string containing pairs of hex digits, each pair delimited by a ':'.
-	 */
-	length = strnlen(mac_addr, sizeof(newpstate.mac_addr));
-	if (length != 17) {
-		return EC_ERROR_INVAL;
-	}
-	for (int i = 0; i < 17; i++) {
-		if (i % 3 != 2) {
-			/* Verify the remaining characters are hex digits. */
-			if ((mac_addr[i] < '0' || '9' < mac_addr[i]) &&
-			    (mac_addr[i] < 'A' || 'F' < mac_addr[i]) &&
-			    (mac_addr[i] < 'a' || 'f' < mac_addr[i])) {
-				return EC_ERROR_INVAL;
-			}
-		} else {
-			/* Every 3rd character is a ':' */
-			if (mac_addr[i] != ':') {
-				return EC_ERROR_INVAL;
-			}
-		}
-	}
-
-	/* Cache the old copy for read/modify/write. */
-	memcpy(&newpstate, pstate, sizeof(newpstate));
-	validate_pstate_struct(&newpstate);
-
-	/*
-	 * Erase any prior data and copy the string. The length was verified to
-	 * be shorter than the buffer so a null terminator always remains.
-	 */
-	memset(newpstate.mac_addr, '\0', sizeof(newpstate.mac_addr));
-	memcpy(newpstate.mac_addr, mac_addr, length);
-
-	newpstate.valid_fields |= PSTATE_VALID_MAC_ADDR;
-
-	return flash_write_pstate_data(&newpstate);
-}
-
-#endif /* CONFIG_MAC_ADDR_LEN */
-
-#else /* !CONFIG_FLASH_PSTATE_BANK */
-
-/**
- * Return the address of the pstate data in EC-RO.
- */
-static const uintptr_t get_pstate_addr(void)
-{
-	uintptr_t addr = (uintptr_t)&pstate_data;
-
-	/* Always use the pstate data in RO, even if we're RW */
-	if (system_is_in_rw())
-		addr += CONFIG_RO_MEM_OFF - CONFIG_RW_MEM_OFF;
-
-	return addr;
-}
-
-/**
- * Read and return persistent state flags (EC_FLASH_PROTECT_*)
- */
-static uint32_t flash_read_pstate(void)
-{
-	/* Check for the unlocked magic value */
-	if (*(const uint32_t *)get_pstate_addr() == PSTATE_MAGIC_UNLOCKED)
-		return 0;
-
-	/* Anything else is locked */
-	return EC_FLASH_PROTECT_RO_AT_BOOT;
-}
-
-/**
- * Write persistent state from pstate, erasing if necessary.
- *
- * @param flags		New flash write protect flags to set in pstate.
- * @return EC_SUCCESS, or nonzero if error.
- */
-static int flash_write_pstate(uint32_t flags)
-{
-	const uint32_t new_pstate = PSTATE_MAGIC_LOCKED;
-
-	/* Only check the flags we write to pstate */
-	flags &= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* Check if pstate has actually changed */
-	if (flags == flash_read_pstate())
-		return EC_SUCCESS;
-
-	/* We can only set the protect flag, not clear it */
-	if (!(flags & EC_FLASH_PROTECT_RO_AT_BOOT))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * Write a new pstate.  We can overwrite the existing value, because
-	 * we're only moving bits from the erased state to the unerased state.
-	 */
-	return crec_flash_physical_write(get_pstate_addr() -
-					 CONFIG_PROGRAM_MEMORY_BASE,
-					 sizeof(new_pstate),
-					 (const char *)&new_pstate);
-}
-
-#endif /* !CONFIG_FLASH_PSTATE_BANK */
-#endif /* CONFIG_FLASH_PSTATE */
-
-int crec_flash_is_erased(uint32_t offset, int size)
-{
-	const uint32_t *ptr;
-
-#ifdef CONFIG_MAPPED_STORAGE
-	/* Use pointer directly to flash */
-	if (crec_flash_dataptr(offset, size, sizeof(uint32_t),
-			  (const char **)&ptr) < 0)
-		return 0;
-
-	crec_flash_lock_mapped_storage(1);
-	for (size /= sizeof(uint32_t); size > 0; size--, ptr++)
-		if (*ptr != CONFIG_FLASH_ERASED_VALUE32) {
-			crec_flash_lock_mapped_storage(0);
-			return 0;
-	}
-
-	crec_flash_lock_mapped_storage(0);
-#else
-	/* Read flash a chunk at a time */
-	uint32_t buf[8];
-	int bsize;
-
-	while (size) {
-		bsize = MIN(size, sizeof(buf));
-
-		if (crec_flash_read(offset, bsize, (char *)buf))
-			return 0;
-
-		size -= bsize;
-		offset += bsize;
-
-		ptr = buf;
-		for (bsize /= sizeof(uint32_t); bsize > 0; bsize--, ptr++)
-			if (*ptr != CONFIG_FLASH_ERASED_VALUE32)
-				return 0;
-
-	}
-#endif
-
-	return 1;
-}
-
-int crec_flash_read(int offset, int size, char *data)
-{
-#ifdef CONFIG_MAPPED_STORAGE
-	const char *src;
-
-	if (crec_flash_dataptr(offset, size, 1, &src) < 0)
-		return EC_ERROR_INVAL;
-
-	crec_flash_lock_mapped_storage(1);
-	memcpy(data, src, size);
-	crec_flash_lock_mapped_storage(0);
-	return EC_SUCCESS;
-#else
-	return crec_flash_physical_read(offset, size, data);
-#endif
-}
-
-static void flash_abort_or_invalidate_hash(int offset, int size)
-{
-#ifdef CONFIG_VBOOT_HASH
-	if (vboot_hash_in_progress()) {
-		/* Abort hash calculation when flash update is in progress. */
-		vboot_hash_abort();
-		return;
-	}
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-	/*
-	 * If EC executes in RAM and is currently in RW, we keep the current
-	 * hash. On the next hash check, AP will catch hash mismatch between the
-	 * flash copy and the RAM copy, then take necessary actions.
-	 */
-	if (system_is_in_rw())
-		return;
-#endif
-
-	/* If EC executes in place, we need to invalidate the cached hash. */
-	vboot_hash_invalidate(offset, size);
-#endif
-
-#ifdef HAS_TASK_RWSIG
-	/*
-	 * If RW flash has been written to, make sure we do not automatically
-	 * jump to RW after the timeout.
-	 */
-	if ((offset >= CONFIG_RW_MEM_OFF &&
-		    offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
-	    ((offset + size) > CONFIG_RW_MEM_OFF &&
-		    (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
-	    (offset < CONFIG_RW_MEM_OFF &&
-		    (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)))
-		rwsig_abort();
-#endif
-}
-
-int crec_flash_write(int offset, int size, const char *data)
-{
-	if (!flash_range_ok(offset, size, CONFIG_FLASH_WRITE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
-
-	flash_abort_or_invalidate_hash(offset, size);
-
-	return crec_flash_physical_write(offset, size, data);
-}
-
-int crec_flash_erase(int offset, int size)
-{
-#ifndef CONFIG_FLASH_MULTIPLE_REGION
-	if (!flash_range_ok(offset, size, CONFIG_FLASH_ERASE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
-#endif
-
-	flash_abort_or_invalidate_hash(offset, size);
-
-	return crec_flash_physical_erase(offset, size);
-}
-
-int crec_flash_protect_at_boot(uint32_t new_flags)
-{
-#ifdef CONFIG_FLASH_PSTATE
-	uint32_t new_pstate_flags = new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* Read the current persist state from flash */
-	if (flash_read_pstate() != new_pstate_flags) {
-		/* Need to update pstate */
-		int rv;
-
-#ifdef CONFIG_FLASH_PSTATE_BANK
-		/* Fail if write protect block is already locked */
-		if (crec_flash_physical_get_protect(PSTATE_BANK))
-			return EC_ERROR_ACCESS_DENIED;
-#endif
-
-		/* Write the desired flags */
-		rv = flash_write_pstate(new_pstate_flags);
-		if (rv)
-			return rv;
-	}
-
-#ifdef CONFIG_FLASH_PROTECT_NEXT_BOOT
-	/*
-	 * Try updating at-boot protection state, if on a platform where write
-	 * protection only changes after a reboot.  Otherwise we wouldn't
-	 * update it until after the next reboot, and we'd need to reboot
-	 * again.  Ignore errors, because the protection registers might
-	 * already be locked this boot, and we'll still apply the correct state
-	 * again on the next boot.
-	 *
-	 * This assumes PSTATE immediately follows RO, which it does on
-	 * all STM32 platforms (which are the only ones with this config).
-	 */
-	crec_flash_physical_protect_at_boot(new_flags);
-#endif
-
-	return EC_SUCCESS;
-#else
-	return crec_flash_physical_protect_at_boot(new_flags);
-#endif
-}
-
-uint32_t crec_flash_get_protect(void)
-{
-	uint32_t flags = 0;
-	int i;
-	/* Region protection status */
-	int not_protected[FLASH_REGION_COUNT] = {0};
-#ifdef CONFIG_ROLLBACK
-	/* Flags that must be set to set ALL_NOW flag. */
-	const uint32_t all_flags = EC_FLASH_PROTECT_RO_NOW |
-				   EC_FLASH_PROTECT_RW_NOW |
-				   EC_FLASH_PROTECT_ROLLBACK_NOW;
-#else
-	const uint32_t all_flags = EC_FLASH_PROTECT_RO_NOW |
-				   EC_FLASH_PROTECT_RW_NOW;
-#endif
-
-	/* Read write protect GPIO */
-#ifdef CONFIG_WP_ALWAYS
-	flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#elif defined(CONFIG_WP_ACTIVE_HIGH)
-	if (gpio_get_level(GPIO_WP))
-		flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#else
-	if (!gpio_get_level(GPIO_WP_L))
-		flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
-#endif
-
-#ifdef CONFIG_FLASH_PSTATE
-	/* Read persistent state of RO-at-boot flag */
-	flags |= flash_read_pstate();
-#endif
-
-	/* Scan flash protection */
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
-		int is_ro = (i >= WP_BANK_OFFSET &&
-			i < WP_BANK_OFFSET + WP_BANK_COUNT);
-		enum flash_region region = is_ro ? FLASH_REGION_RO :
-			FLASH_REGION_RW;
-		int bank_flag = is_ro ? EC_FLASH_PROTECT_RO_NOW :
-			EC_FLASH_PROTECT_RW_NOW;
-
-#ifdef CONFIG_ROLLBACK
-		if (i >= ROLLBACK_BANK_OFFSET &&
-		    i < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) {
-			region = FLASH_REGION_ROLLBACK;
-			bank_flag = EC_FLASH_PROTECT_ROLLBACK_NOW;
-		}
-#endif
-
-		if (crec_flash_physical_get_protect(i)) {
-			/* At least one bank in the region is protected */
-			flags |= bank_flag;
-			if (not_protected[region])
-				flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-		} else {
-			/* At least one bank in the region is NOT protected */
-			not_protected[region] = 1;
-			if (flags & bank_flag)
-				flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-		}
-	}
-
-	if ((flags & all_flags) == all_flags)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/*
-	 * If the RW or ROLLBACK banks are protected but the RO banks aren't,
-	 * that's inconsistent.
-	 *
-	 * Note that we check this before adding in the physical flags below,
-	 * since some chips can also protect ALL_NOW for the current boot by
-	 * locking up the flash program-erase registers.
-	 */
-	if ((flags & all_flags) && !(flags & EC_FLASH_PROTECT_RO_NOW))
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-#ifndef CONFIG_FLASH_PROTECT_RW
-	/* RW flag was used for intermediate computations, clear it now. */
-	flags &= ~EC_FLASH_PROTECT_RW_NOW;
-#endif
-
-	/* Add in flags from physical layer */
-	return flags | crec_flash_physical_get_protect_flags();
-}
-
-/*
- * Request a flash protection flags change for |mask| flash protect flags
- * to |flags| state.
- *
- * Order of flag processing:
- * 1. Clear/Set RO_AT_BOOT + Clear *_AT_BOOT flags + Commit *_AT_BOOT flags.
- * 2. Return if RO_AT_BOOT and HW-WP are not asserted.
- * 3. Set remaining *_AT_BOOT flags + Commit *_AT_BOOT flags.
- * 4. Commit RO_NOW.
- * 5. Commit ALL_NOW.
- */
-int crec_flash_set_protect(uint32_t mask, uint32_t flags)
-{
-	int retval = EC_SUCCESS;
-	int rv;
-	int old_flags_at_boot = crec_flash_get_protect() &
-		(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RW_AT_BOOT |
-			EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			EC_FLASH_PROTECT_ALL_AT_BOOT);
-	int new_flags_at_boot = old_flags_at_boot;
-
-	/* Sanitize input flags */
-	flags = flags & mask;
-
-	/*
-	 * Process flags we can set.  Track the most recent error, but process
-	 * all flags before returning.
-	 */
-
-	/*
-	 * AT_BOOT flags are trickier than NOW flags, as they can be set
-	 * when HW write protection is disabled and can be unset without
-	 * a reboot.
-	 *
-	 * If we are only setting/clearing RO_AT_BOOT, things are simple.
-	 * Setting ALL_AT_BOOT is processed only if HW write protection is
-	 * enabled and RO_AT_BOOT is set, so it's also simple.
-	 *
-	 * The most tricky one is when we want to clear ALL_AT_BOOT. We need
-	 * to determine whether to clear protection for the entire flash or
-	 * leave RO protected. There are two cases that we want to keep RO
-	 * protected:
-	 *   A. RO_AT_BOOT was already set before flash_set_protect() is
-	 *      called.
-	 *   B. RO_AT_BOOT was not set, but it's requested to be set by
-	 *      the caller of flash_set_protect().
-	 */
-
-	/* 1.a - Clear RO_AT_BOOT. */
-	new_flags_at_boot &= ~(mask & EC_FLASH_PROTECT_RO_AT_BOOT);
-	/* 1.b - Set RO_AT_BOOT. */
-	new_flags_at_boot |= flags & EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/* 1.c - Clear ALL_AT_BOOT. */
-	if ((mask & EC_FLASH_PROTECT_ALL_AT_BOOT) &&
-	    !(flags & EC_FLASH_PROTECT_ALL_AT_BOOT)) {
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_ALL_AT_BOOT;
-		/* Must also clear RW/ROLLBACK. */
-#ifdef CONFIG_FLASH_PROTECT_RW
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-#ifdef CONFIG_ROLLBACK
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-	}
-
-	/* 1.d - Clear RW_AT_BOOT. */
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if ((mask & EC_FLASH_PROTECT_RW_AT_BOOT) &&
-	    !(flags & EC_FLASH_PROTECT_RW_AT_BOOT)) {
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_RW_AT_BOOT;
-		/* Must also clear ALL (otherwise nothing will happen). */
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_ALL_AT_BOOT;
-	}
-#endif
-
-	/* 1.e - Clear ROLLBACK_AT_BOOT. */
-#ifdef CONFIG_ROLLBACK
-	if ((mask & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
-	    !(flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)) {
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-		/* Must also remove ALL (otherwise nothing will happen). */
-		new_flags_at_boot &= ~EC_FLASH_PROTECT_ALL_AT_BOOT;
-	}
-#endif
-
-	/* 1.f - Commit *_AT_BOOT "clears" (and RO "set" 1.b). */
-	if (new_flags_at_boot != old_flags_at_boot) {
-		rv = crec_flash_protect_at_boot(new_flags_at_boot);
-		if (rv)
-			retval = rv;
-		old_flags_at_boot = new_flags_at_boot;
-	}
-
-	/* 2 - Return if RO_AT_BOOT and HW-WP are not asserted.
-	 *
-	 * All subsequent flags only work if write protect is enabled (that is,
-	 * hardware WP flag) *and* RO is protected at boot (software WP flag).
-	 */
-	if ((~crec_flash_get_protect()) & (EC_FLASH_PROTECT_GPIO_ASSERTED |
-				      EC_FLASH_PROTECT_RO_AT_BOOT))
-		return retval;
-
-	/*
-	 * 3.a - Set ALL_AT_BOOT.
-	 *
-	 * The case where ALL/RW/ROLLBACK_AT_BOOT is cleared is already covered
-	 * above, so we do not need to mask it out.
-	 */
-	new_flags_at_boot |= flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-
-	/* 3.b - Set RW_AT_BOOT. */
-#ifdef CONFIG_FLASH_PROTECT_RW
-	new_flags_at_boot |= flags & EC_FLASH_PROTECT_RW_AT_BOOT;
-#endif
-
-	/* 3.c - Set ROLLBACK_AT_BOOT. */
-#ifdef CONFIG_ROLLBACK
-	new_flags_at_boot |= flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
-#endif
-
-	/* 3.d - Commit *_AT_BOOT "sets". */
-	if (new_flags_at_boot != old_flags_at_boot) {
-		rv = crec_flash_protect_at_boot(new_flags_at_boot);
-		if (rv)
-			retval = rv;
-	}
-
-	/* 4 - Commit RO_NOW. */
-	if (flags & EC_FLASH_PROTECT_RO_NOW) {
-		rv = crec_flash_physical_protect_now(0);
-		if (rv)
-			retval = rv;
-
-		/*
-		 * Latch the CBI EEPROM WP immediately if HW WP is asserted and
-		 * we're now protecting the RO region with SW WP.
-		 */
-		if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) &&
-		    (EC_FLASH_PROTECT_GPIO_ASSERTED &
-		     crec_flash_get_protect()))
-			cbi_latch_eeprom_wp();
-	}
-
-	/* 5 - Commit ALL_NOW. */
-	if (flags & EC_FLASH_PROTECT_ALL_NOW) {
-		rv = crec_flash_physical_protect_now(1);
-		if (rv)
-			retval = rv;
-	}
-
-	return retval;
-}
-
-#ifdef CONFIG_FLASH_DEFERRED_ERASE
-static volatile enum ec_status erase_rc = EC_RES_SUCCESS;
-static struct ec_params_flash_erase_v1 erase_info;
-
-static void flash_erase_deferred(void)
-{
-	erase_rc = EC_RES_BUSY;
-	if (crec_flash_erase(erase_info.params.offset, erase_info.params.size))
-		erase_rc = EC_RES_ERROR;
-	else
-		erase_rc = EC_RES_SUCCESS;
-}
-DECLARE_DEFERRED(flash_erase_deferred);
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_FLASHINFO
-static int command_flash_info(int argc, char **argv)
-{
-	int i, flags;
-
-	ccprintf("Usable:  %4d KB\n", CONFIG_FLASH_SIZE_BYTES / 1024);
-	ccprintf("Write:   %4d B (ideal %d B)\n", CONFIG_FLASH_WRITE_SIZE,
-		 CONFIG_FLASH_WRITE_IDEAL_SIZE);
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-	ccprintf("Regions:\n");
-	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		ccprintf(" %d region%s:\n",
-			 flash_bank_array[i].count,
-			 (flash_bank_array[i].count == 1 ? "" : "s"));
-		ccprintf("  Erase:   %4d B (to %d-bits)\n",
-			 1 << flash_bank_array[i].erase_size_exp,
-			 CONFIG_FLASH_ERASED_VALUE32 ? 1 : 0);
-		ccprintf("  Size/Protect: %4d B\n",
-			 1 << flash_bank_array[i].size_exp);
-	}
-#else
-	ccprintf("Erase:   %4d B (to %d-bits)\n", CONFIG_FLASH_ERASE_SIZE,
-		 CONFIG_FLASH_ERASED_VALUE32 ? 1 : 0);
-	ccprintf("Protect: %4d B\n", CONFIG_FLASH_BANK_SIZE);
-#endif
-	flags = crec_flash_get_protect();
-	ccprintf("Flags:  ");
-	if (flags & EC_FLASH_PROTECT_GPIO_ASSERTED)
-		ccputs(" wp_gpio_asserted");
-	if (flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		ccputs(" ro_at_boot");
-	if (flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		ccputs(" all_at_boot");
-	if (flags & EC_FLASH_PROTECT_RO_NOW)
-		ccputs(" ro_now");
-	if (flags & EC_FLASH_PROTECT_ALL_NOW)
-		ccputs(" all_now");
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-		ccputs(" rw_at_boot");
-	if (flags & EC_FLASH_PROTECT_RW_NOW)
-		ccputs(" rw_now");
-#endif
-	if (flags & EC_FLASH_PROTECT_ERROR_STUCK)
-		ccputs(" STUCK");
-	if (flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT)
-		ccputs(" INCONSISTENT");
-#ifdef CONFIG_ROLLBACK
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)
-		ccputs(" rollback_at_boot");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_NOW)
-		ccputs(" rollback_now");
-#endif
-	ccputs("\n");
-
-	ccputs("Protected now:");
-	for (i = 0; i < PHYSICAL_BANKS; i++) {
-		if (!(i & 31))
-			ccputs("\n    ");
-		else if (!(i & 7))
-			ccputs(" ");
-		ccputs(crec_flash_physical_get_protect(i) ? "Y" : ".");
-	}
-	ccputs("\n");
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info,
-			     NULL,
-			     "Print flash info");
-#endif /* CONFIG_CMD_FLASHINFO */
-
-#ifdef CONFIG_CMD_FLASH
-static int command_flash_erase(int argc, char **argv)
-{
-	int offset = -1;
-	int size = -1;
-	int rv;
-
-	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = parse_offset_size(argc, argv, 1, &offset, &size);
-	if (rv)
-		return rv;
-
-	ccprintf("Erasing %d bytes at 0x%x...\n", size, offset);
-	return crec_flash_erase(offset, size);
-}
-DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase,
-			"offset size",
-			"Erase flash");
-
-static int command_flash_write(int argc, char **argv)
-{
-	int offset = -1;
-	int size = -1;
-	int rv;
-	char *data;
-	int i;
-
-	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
-		return EC_ERROR_ACCESS_DENIED;
-
-	rv = parse_offset_size(argc, argv, 1, &offset, &size);
-	if (rv)
-		return rv;
-
-	if (size > shared_mem_size())
-		size = shared_mem_size();
-
-	/* Acquire the shared memory buffer */
-	rv = shared_mem_acquire(size, &data);
-	if (rv) {
-		ccputs("Can't get shared mem\n");
-		return rv;
-	}
-
-	/* Fill the data buffer with a pattern */
-	for (i = 0; i < size; i++)
-		data[i] = i;
-
-	ccprintf("Writing %d bytes to 0x%x...\n", size, offset);
-	rv = crec_flash_write(offset, size, data);
-
-	/* Free the buffer */
-	shared_mem_release(data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write,
-			"offset size",
-			"Write pattern to flash");
-
-static int command_flash_read(int argc, char **argv)
-{
-	int offset = -1;
-	int size = 256;
-	int rv;
-	char *data;
-	int i;
-
-	rv = parse_offset_size(argc, argv, 1, &offset, &size);
-	if (rv)
-		return rv;
-
-	if (size > shared_mem_size())
-		size = shared_mem_size();
-
-	/* Acquire the shared memory buffer */
-	rv = shared_mem_acquire(size, &data);
-	if (rv) {
-		ccputs("Can't get shared mem\n");
-		return rv;
-	}
-
-	/* Read the data */
-	if (crec_flash_read(offset, size, data)) {
-		shared_mem_release(data);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Dump it */
-	for (i = 0; i < size; i++) {
-		if ((offset + i) % 16) {
-			ccprintf(" %02x", data[i]);
-		} else {
-			ccprintf("\n%08x: %02x", offset + i, data[i]);
-			cflush();
-		}
-	}
-	ccprintf("\n");
-
-	/* Free the buffer */
-	shared_mem_release(data);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(flashread, command_flash_read,
-			"offset [size]",
-			"Read flash");
-#endif
-
-#ifdef CONFIG_CMD_FLASH_WP
-static int command_flash_wp(int argc, char **argv)
-{
-	int val;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "now"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
-
-	if (!strcasecmp(argv[1], "all"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
-
-	if (!strcasecmp(argv[1], "noall"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, 0);
-
-#ifdef CONFIG_FLASH_PROTECT_RW
-	if (!strcasecmp(argv[1], "rw"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, -1);
-
-	if (!strcasecmp(argv[1], "norw"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
-#endif
-
-#ifdef CONFIG_ROLLBACK
-	if (!strcasecmp(argv[1], "rb"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
-					      -1);
-
-	if (!strcasecmp(argv[1], "norb"))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT,
-					      0);
-#endif
-
-	/* Do this last, since anything starting with 'n' means "no" */
-	if (parse_bool(argv[1], &val))
-		return crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-					 val ? -1 : 0);
-
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp,
-			"<BOOLEAN> | now | all | noall"
-#ifdef CONFIG_FLASH_PROTECT_RW
-			" | rw | norw"
-#endif
-#ifdef CONFIG_ROLLBACK
-			" | rb | norb"
-#endif
-			, "Modify flash write protect");
-#endif /* CONFIG_CMD_FLASH_WP */
-
-/*****************************************************************************/
-/* Host commands */
-
-/*
- * All internal EC code assumes that offsets are provided relative to
- * physical address zero of storage. In some cases, the region of storage
- * belonging to the EC is not physical address zero - a non-zero fmap_base
- * indicates so. Since fmap_base is not yet handled correctly by external
- * code, we must perform the adjustment in our host command handlers -
- * adjust all offsets so they are relative to the beginning of the storage
- * region belonging to the EC. TODO(crbug.com/529365): Handle fmap_base
- * correctly in flashrom, dump_fmap, etc. and remove EC_FLASH_REGION_START.
- */
-#define EC_FLASH_REGION_START MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, \
-				  CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_info_2 *p_2 = args->params;
-	struct ec_response_flash_info_2 *r_2 = args->response;
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-	int banks_size = ARRAY_SIZE(flash_bank_array);
-	const struct ec_flash_bank *banks = flash_bank_array;
-#else
-	struct ec_response_flash_info_1 *r_1 = args->response;
-#if CONFIG_FLASH_BANK_SIZE < CONFIG_FLASH_ERASE_SIZE
-#error "Flash: Bank size expected bigger or equal to erase size."
-#endif
-	struct ec_flash_bank single_bank = {
-		.count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-		.size_exp = __fls(CONFIG_FLASH_BANK_SIZE),
-		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
-		.erase_size_exp = __fls(CONFIG_FLASH_ERASE_SIZE),
-		.protect_size_exp = __fls(CONFIG_FLASH_BANK_SIZE),
-	};
-	int banks_size = 1;
-	const struct ec_flash_bank *banks = &single_bank;
-#endif
-	int banks_len;
-	int ideal_size;
-
-	/*
-	 * Compute the ideal amount of data for the host to send us,
-	 * based on the maximum response size and the ideal write size.
-	 */
-	ideal_size = (args->response_max -
-		 sizeof(struct ec_params_flash_write)) &
-		~(CONFIG_FLASH_WRITE_IDEAL_SIZE - 1);
-	/*
-	 * If we can't get at least one ideal block, then just want
-	 * as high a multiple of the minimum write size as possible.
-	 */
-	if (!ideal_size)
-		ideal_size = (args->response_max -
-				sizeof(struct ec_params_flash_write)) &
-				~(CONFIG_FLASH_WRITE_SIZE - 1);
-
-
-	if (args->version >= 2) {
-		args->response_size = sizeof(struct ec_response_flash_info_2);
-		r_2->flash_size =
-			CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START;
-#if (CONFIG_FLASH_ERASED_VALUE32 == 0)
-		r_2->flags = EC_FLASH_INFO_ERASE_TO_0;
-#else
-		r_2->flags = 0;
-#endif
-#ifdef CONFIG_FLASH_SELECT_REQUIRED
-		r_2->flags |= EC_FLASH_INFO_SELECT_REQUIRED;
-#endif
-		r_2->write_ideal_size = ideal_size;
-		r_2->num_banks_total = banks_size;
-		r_2->num_banks_desc = MIN(banks_size, p_2->num_banks_desc);
-		banks_len = r_2->num_banks_desc * sizeof(struct ec_flash_bank);
-		memcpy(r_2->banks, banks, banks_len);
-		args->response_size += banks_len;
-		return EC_RES_SUCCESS;
-	}
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-	return EC_RES_INVALID_PARAM;
-#else
-	r_1->flash_size = CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START;
-	r_1->flags = 0;
-	r_1->write_block_size = CONFIG_FLASH_WRITE_SIZE;
-	r_1->erase_block_size = CONFIG_FLASH_ERASE_SIZE;
-	r_1->protect_block_size = CONFIG_FLASH_BANK_SIZE;
-	if (args->version == 0) {
-		/* Only version 0 fields returned */
-		args->response_size = sizeof(struct ec_response_flash_info);
-	} else {
-		args->response_size = sizeof(struct ec_response_flash_info_1);
-		/* Fill in full version 1 struct */
-		r_1->write_ideal_size = ideal_size;
-#if (CONFIG_FLASH_ERASED_VALUE32 == 0)
-		r_1->flags |= EC_FLASH_INFO_ERASE_TO_0;
-#endif
-#ifdef CONFIG_FLASH_SELECT_REQUIRED
-		r_1->flags |= EC_FLASH_INFO_SELECT_REQUIRED;
-#endif
-	}
-	return EC_RES_SUCCESS;
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
-}
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-#define FLASH_INFO_VER EC_VER_MASK(2)
-#else
-#define FLASH_INFO_VER (EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2))
-#endif
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO,
-		     flash_command_get_info, FLASH_INFO_VER);
-
-
-static enum ec_status flash_command_read(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_read *p = args->params;
-	uint32_t offset = p->offset + EC_FLASH_REGION_START;
-
-	if (p->size > args->response_max)
-		return EC_RES_OVERFLOW;
-
-	if (crec_flash_read(offset, p->size, args->response))
-		return EC_RES_ERROR;
-
-	args->response_size = p->size;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ,
-		     flash_command_read,
-		     EC_VER_MASK(0));
-
-/**
- * Flash write command
- *
- * Version 0 and 1 are equivalent from the EC-side; the only difference is
- * that the host can only send 64 bytes of data at a time in version 0.
- */
-static enum ec_status flash_command_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_write *p = args->params;
-	uint32_t offset = p->offset + EC_FLASH_REGION_START;
-
-	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
-		return EC_RES_ACCESS_DENIED;
-
-	if (p->size + sizeof(*p) > args->params_size)
-		return EC_RES_INVALID_PARAM;
-
-#ifdef CONFIG_INTERNAL_STORAGE
-	if (system_unsafe_to_overwrite(offset, p->size))
-		return EC_RES_ACCESS_DENIED;
-#endif
-
-	if (crec_flash_write(offset, p->size, (const uint8_t *)(p + 1)))
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE,
-		     flash_command_write,
-		     EC_VER_MASK(0) | EC_VER_MASK(EC_VER_FLASH_WRITE));
-
-#ifndef CONFIG_FLASH_MULTIPLE_REGION
-/*
- * Make sure our image sizes are a multiple of flash block erase size so that
- * the host can erase the entire image.
- * Note that host (flashrom/depthcharge) does not erase/program the
- * EC_FLASH_REGION_RO region, it only queries this region.
- */
-BUILD_ASSERT(CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
-BUILD_ASSERT(CONFIG_EC_WRITABLE_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE == 0);
-
-#endif
-
-static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_erase *p = args->params;
-	int rc = EC_RES_SUCCESS, cmd = FLASH_ERASE_SECTOR;
-	uint32_t offset;
-#ifdef CONFIG_FLASH_DEFERRED_ERASE
-	const struct ec_params_flash_erase_v1 *p_1 = args->params;
-
-	if (args->version > 0) {
-		cmd = p_1->cmd;
-		p = &p_1->params;
-	}
-#endif
-	offset = p->offset + EC_FLASH_REGION_START;
-
-	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
-		return EC_RES_ACCESS_DENIED;
-
-#ifdef CONFIG_INTERNAL_STORAGE
-	if (system_unsafe_to_overwrite(offset, p->size))
-		return EC_RES_ACCESS_DENIED;
-#endif
-
-	switch (cmd) {
-	case FLASH_ERASE_SECTOR:
-#if defined(HAS_TASK_HOSTCMD) && defined(CONFIG_HOST_COMMAND_STATUS)
-		args->result = EC_RES_IN_PROGRESS;
-		host_send_response(args);
-#endif
-		if (crec_flash_erase(offset, p->size))
-			return EC_RES_ERROR;
-
-		break;
-#ifdef CONFIG_FLASH_DEFERRED_ERASE
-	case FLASH_ERASE_SECTOR_ASYNC:
-		rc = erase_rc;
-		if (rc == EC_RES_SUCCESS) {
-			memcpy(&erase_info, p_1, sizeof(*p_1));
-			hook_call_deferred(&flash_erase_deferred_data,
-					   100 * MSEC);
-		} else {
-			/*
-			 * Not our job to return the result of
-			 * the previous command.
-			 */
-			rc = EC_RES_BUSY;
-		}
-		break;
-	case FLASH_ERASE_GET_RESULT:
-		rc = erase_rc;
-		if (rc != EC_RES_BUSY)
-			/* Ready for another command */
-			erase_rc = EC_RES_SUCCESS;
-		break;
-#endif
-	default:
-		rc = EC_RES_INVALID_PARAM;
-	}
-	return rc;
-}
-
-
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_ERASE, flash_command_erase,
-		EC_VER_MASK(0)
-#ifdef CONFIG_FLASH_DEFERRED_ERASE
-		| EC_VER_MASK(1)
-#endif
-		);
-
-static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_protect *p = args->params;
-	struct ec_response_flash_protect *r = args->response;
-
-	/*
-	 * Handle requesting new flags.  Note that we ignore the return code
-	 * from flash_set_protect(), since errors will be visible to the caller
-	 * via the flags in the response.  (If we returned error, the caller
-	 * wouldn't get the response.)
-	 */
-	if (p->mask)
-		crec_flash_set_protect(p->mask, p->flags);
-
-	/*
-	 * Retrieve the current flags.  The caller can use this to determine
-	 * which of the requested flags could be set.  This is cleaner than
-	 * simply returning error, because it provides information to the
-	 * caller about the actual result.
-	 */
-	r->flags = crec_flash_get_protect();
-
-	/* Indicate which flags are valid on this platform */
-	r->valid_flags =
-		EC_FLASH_PROTECT_GPIO_ASSERTED |
-		EC_FLASH_PROTECT_ERROR_STUCK |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT |
-		crec_flash_physical_get_valid_flags();
-	r->writable_flags = crec_flash_physical_get_writable_flags(r->flags);
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-
-/*
- * TODO(crbug.com/239197) : Adding both versions to the version mask is a
- * temporary workaround for a problem in the cros_ec driver. Drop
- * EC_VER_MASK(0) once cros_ec driver can send the correct version.
- */
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT,
-		     flash_command_protect,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static enum ec_status
-flash_command_region_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_region_info *p = args->params;
-	struct ec_response_flash_region_info *r = args->response;
-
-	switch (p->region) {
-	case EC_FLASH_REGION_RO:
-		r->offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-			    CONFIG_RO_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
-		r->size = EC_FLASH_REGION_RO_SIZE;
-		break;
-	case EC_FLASH_REGION_ACTIVE:
-		r->offset = flash_get_rw_offset(system_get_active_copy()) -
-				EC_FLASH_REGION_START;
-		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-		break;
-	case EC_FLASH_REGION_WP_RO:
-		r->offset = CONFIG_WP_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
-		r->size = CONFIG_WP_STORAGE_SIZE;
-		break;
-	case EC_FLASH_REGION_UPDATE:
-		r->offset = flash_get_rw_offset(system_get_update_copy()) -
-				EC_FLASH_REGION_START;
-		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO,
-		     flash_command_region_info,
-		     EC_VER_MASK(EC_VER_FLASH_REGION_INFO));
-
-
-#ifdef CONFIG_FLASH_SELECT_REQUIRED
-
-static enum ec_status flash_command_select(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_flash_select *p = args->params;
-
-	return crec_board_flash_select(p->select);
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT,
-		     flash_command_select,
-		     EC_VER_MASK(0));
-
-#endif /* CONFIG_FLASH_SELECT_REQUIRED */
diff --git a/common/fmap.c b/common/fmap.c
deleted file mode 100644
index 47fa75f0e9..0000000000
--- a/common/fmap.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-
-#include "common.h"
-#include "cros_version.h"
-#include "rwsig.h"
-#include "util.h"
-
-/*
- * FMAP structs.
- * See https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/master/lib/fmap.h
- */
-#define FMAP_NAMELEN 32
-#define FMAP_SIGNATURE "__FMAP__"
-#define FMAP_SIGNATURE_SIZE 8
-#define FMAP_VER_MAJOR 1
-#define FMAP_VER_MINOR 0
-
-/*
- * For address containing CONFIG_PROGRAM_MEMORY_BASE (symbols in *.RO.lds.S and
- * variable), this computes the offset to the start of the image on flash.
- */
-#define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \
-			   CONFIG_RO_MEM_OFF)
-
-/*
- * All internal EC code assumes that offsets are provided relative to
- * physical address zero of storage. In some cases, the region of storage
- * belonging to the EC is not physical address zero - a non-zero fmap_base
- * indicates so. Since fmap_base is not yet handled correctly by external
- * code, we must perform the adjustment in our host command handlers -
- * adjust all offsets so they are relative to the beginning of the storage
- * region belonging to the EC. TODO(crbug.com/529365): Handle fmap_base
- * correctly in flashrom, dump_fmap, etc. and remove EC_FLASH_REGION_START.
- */
-#if CONFIG_EC_WRITABLE_STORAGE_OFF < CONFIG_EC_PROTECTED_STORAGE_OFF
-#define FMAP_REGION_START CONFIG_EC_WRITABLE_STORAGE_OFF
-#else
-#define FMAP_REGION_START CONFIG_EC_PROTECTED_STORAGE_OFF
-#endif
-
-struct fmap_header {
-	char        fmap_signature[FMAP_SIGNATURE_SIZE];
-	uint8_t     fmap_ver_major;
-	uint8_t     fmap_ver_minor;
-	uint64_t    fmap_base;
-	uint32_t    fmap_size;
-	char        fmap_name[FMAP_NAMELEN];
-	uint16_t    fmap_nareas;
-} __packed;
-
-#define FMAP_AREA_STATIC      BIT(0)	/* can be checksummed */
-#define FMAP_AREA_COMPRESSED  BIT(1)  /* may be compressed */
-#define FMAP_AREA_RO          BIT(2)  /* writes may fail */
-
-struct fmap_area_header {
-	uint32_t area_offset;
-	uint32_t area_size;
-	char     area_name[FMAP_NAMELEN];
-	uint16_t area_flags;
-} __packed;
-
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-#define NUM_EC_FMAP_AREAS_RWSIG 2
-#else
-#define NUM_EC_FMAP_AREAS_RWSIG 0
-#endif
-
-#ifdef CONFIG_ROLLBACK
-#define NUM_EC_FMAP_AREAS_ROLLBACK 1
-#else
-#define NUM_EC_FMAP_AREAS_ROLLBACK 0
-#endif
-#ifdef CONFIG_RW_B
-#  ifdef CONFIG_RWSIG_TYPE_RWSIG
-#    define NUM_EC_FMAP_AREAS_RW_B     2
-#  else
-#    define NUM_EC_FMAP_AREAS_RW_B     1
-#  endif
-#else
-#define NUM_EC_FMAP_AREAS_RW_B     0
-#endif
-
-#define NUM_EC_FMAP_AREAS (7 + \
-			NUM_EC_FMAP_AREAS_RWSIG + \
-			NUM_EC_FMAP_AREAS_ROLLBACK + \
-			NUM_EC_FMAP_AREAS_RW_B)
-
-const struct _ec_fmap {
-	struct fmap_header header;
-	struct fmap_area_header area[NUM_EC_FMAP_AREAS];
-} ec_fmap __keep __attribute__((section(".google"))) = {
-	/* Header */
-	{
-		.fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'},
-		.fmap_ver_major = FMAP_VER_MAJOR,
-		.fmap_ver_minor = FMAP_VER_MINOR,
-		.fmap_base = CONFIG_PROGRAM_MEMORY_BASE,
-		.fmap_size = CONFIG_FLASH_SIZE_BYTES,
-		/* Used to distinguish the EC FMAP from other FMAPs */
-		.fmap_name = "EC_FMAP",
-		.fmap_nareas = NUM_EC_FMAP_AREAS,
-	},
-
-	{
-	/* RO Firmware */
-		{
-			/*
-			 * Range of RO firmware to be updated. EC_RO
-			 * section includes the bootloader section
-			 * because it may need to be updated/paired
-			 * with a different RO.  Verified in factory
-			 * finalization by hash. Should not have
-			 * volatile data (ex, calibration results).
-			 */
-			.area_name = "EC_RO",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START,
-			.area_size = CONFIG_RO_SIZE + CONFIG_RO_STORAGE_OFF,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-		{
-			/* (Optional) RO firmware code. */
-			.area_name = "FR_MAIN",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF,
-			.area_size = CONFIG_RO_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-		{
-			/*
-			 * RO firmware version ID. Must be NULL terminated
-			 * ASCII, and padded with \0.
-			 */
-			.area_name = "RO_FRID",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
-			.area_size = sizeof(current_image_data.version),
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-
-		/* Other RO stuff: FMAP, WP, KEYS, etc. */
-		{
-			.area_name = "FMAP",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)&ec_fmap),
-			.area_size = sizeof(ec_fmap),
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-		{
-			/*
-			 * The range for write protection, for factory
-			 * finalization.  Should include (may be identical to)
-			 * EC_RO and aligned to hardware specification.
-			 */
-			.area_name = "WP_RO",
-			.area_offset = CONFIG_WP_STORAGE_OFF -
-				       FMAP_REGION_START,
-			.area_size = CONFIG_WP_STORAGE_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-		{
-			/* RO public key address, for RW verification */
-			.area_name = "KEY_RO",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_PUBKEY_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
-			.area_size = CONFIG_RO_PUBKEY_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-#endif
-
-		/* RW Firmware */
-		{
-			 /* The range of RW firmware to be auto-updated. */
-			.area_name = "EC_RW",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF,
-			.area_size = CONFIG_RW_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-		{
-			/*
-			 * RW firmware version ID. Must be NULL terminated
-			 * ASCII, and padded with \0.
-			 * TODO: Get the relative offset of
-			 * __image_data_offset within our RW image to
-			 * accommodate image asymmetry.
-			 */
-			.area_name = "RW_FWID",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
-			.area_size = sizeof(current_image_data.version),
-			.area_flags = FMAP_AREA_STATIC,
-		},
-#ifdef CONFIG_ROLLBACK
-		{
-			/*
-			 * RW rollback version, 32-bit unsigned integer.
-			 * TODO: Get the relative offset of
-			 * __image_data_offset within our RW image to
-			 * accommodate image asymmetry.
-			 */
-			.area_name = "RW_RBVER",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data, rollback_version),
-			.area_size = sizeof(
-				current_image_data.rollback_version),
-			.area_flags = FMAP_AREA_STATIC,
-		},
-#endif
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-		{
-			 /* RW image signature */
-			.area_name = "SIG_RW",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
-			.area_size = CONFIG_RW_SIG_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-#endif
-#ifdef CONFIG_RW_B
-		/* RW Firmware */
-		{
-			 /* The range of RW firmware to be auto-updated. */
-			.area_name = "EC_RW_B",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
-				CONFIG_RW_SIZE,
-			.area_size = CONFIG_RW_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-		{
-			 /* RW_B image signature */
-			.area_name = "SIG_RW_B",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_B_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
-			.area_size = CONFIG_RW_SIG_SIZE,
-			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
-		},
-#endif
-#endif
-	}
-};
diff --git a/common/fpsensor/OWNERS b/common/fpsensor/OWNERS
deleted file mode 100644
index 395f722670..0000000000
--- a/common/fpsensor/OWNERS
+++ /dev/null
@@ -1,10 +0,0 @@
-# Fingerprint Sensor
-
-# Don't inherit owners from elsewhere in the manifest
-set noparent
-
-hesling@chromium.org
-jora@google.com
-josienordrum@google.com
-tomhughes@chromium.org
-yichengli@chromium.org
diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c
deleted file mode 100644
index 25010c7db8..0000000000
--- a/common/fpsensor/fpsensor.c
+++ /dev/null
@@ -1,887 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "cryptoc/util.h"
-#include "ec_commands.h"
-#include "fpsensor.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_detect.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "link_defs.h"
-#include "mkbp_event.h"
-#include "overflow.h"
-#include "spi.h"
-#include "system.h"
-#include "task.h"
-#include "trng.h"
-#include "util.h"
-#include "watchdog.h"
-
-#if !defined(CONFIG_RNG)
-#error "fpsensor requires RNG"
-#endif
-
-#if defined(SECTION_IS_RO)
-#error "fpsensor code should not be in RO image."
-#endif
-
-/* Ready to encrypt a template. */
-static timestamp_t encryption_deadline;
-
-/* raw image offset inside the acquired frame */
-#ifndef FP_SENSOR_IMAGE_OFFSET
-#define FP_SENSOR_IMAGE_OFFSET 0
-#endif
-
-#define FP_MODE_ANY_CAPTURE (FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | \
-			     FP_MODE_MATCH)
-#define FP_MODE_ANY_DETECT_FINGER (FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \
-				   FP_MODE_ANY_CAPTURE)
-#define FP_MODE_ANY_WAIT_IRQ      (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE)
-
-/* Delay between 2 s of the sensor to detect finger removal */
-#define FINGER_POLLING_DELAY (100*MSEC)
-
-/* Timing statistics. */
-static uint32_t capture_time_us;
-static uint32_t matching_time_us;
-static uint32_t overall_time_us;
-static timestamp_t overall_t0;
-static uint8_t timestamps_invalid;
-
-BUILD_ASSERT(sizeof(struct ec_fp_template_encryption_metadata) % 4 == 0);
-
-/* Interrupt line from the fingerprint sensor */
-void fps_event(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_SENSOR_IRQ);
-}
-
-static void send_mkbp_event(uint32_t event)
-{
-	atomic_or(&fp_events, event);
-	mkbp_send_event(EC_MKBP_EVENT_FINGERPRINT);
-}
-
-static inline int is_raw_capture(uint32_t mode)
-{
-	int capture_type = FP_CAPTURE_TYPE(mode);
-
-	return (capture_type == FP_CAPTURE_VENDOR_FORMAT
-	     || capture_type == FP_CAPTURE_QUALITY_TEST);
-}
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-static inline int is_test_capture(uint32_t mode)
-{
-	int capture_type = FP_CAPTURE_TYPE(mode);
-
-	return (mode & FP_MODE_CAPTURE)
-		&& (capture_type == FP_CAPTURE_PATTERN0
-		    || capture_type == FP_CAPTURE_PATTERN1
-		    || capture_type == FP_CAPTURE_RESET_TEST);
-}
-
-/*
- * contains the bit FP_MODE_ENROLL_SESSION if a finger enrollment is on-going.
- * It is used to detect the ENROLL_SESSION transition when sensor_mode is
- * updated by the host.
- */
-static uint32_t enroll_session;
-
-static uint32_t fp_process_enroll(void)
-{
-	int percent = 0;
-	int res;
-
-	if (template_newly_enrolled != FP_NO_SUCH_TEMPLATE)
-		CPRINTS("Warning: previously enrolled template has not been "
-			"read yet.");
-
-	/* begin/continue enrollment */
-	CPRINTS("[%d]Enrolling ...", templ_valid);
-	res = fp_finger_enroll(fp_buffer, &percent);
-	CPRINTS("[%d]Enroll =>%d (%d%%)", templ_valid, res, percent);
-	if (res < 0)
-		return EC_MKBP_FP_ENROLL
-		     | EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL);
-	templ_dirty |= BIT(templ_valid);
-	if (percent == 100) {
-		res = fp_enrollment_finish(fp_template[templ_valid]);
-		if (res) {
-			res = EC_MKBP_FP_ERR_ENROLL_INTERNAL;
-		} else {
-			template_newly_enrolled = templ_valid;
-			fp_enable_positive_match_secret(templ_valid,
-				&positive_match_secret_state);
-			templ_valid++;
-		}
-		sensor_mode &= ~FP_MODE_ENROLL_SESSION;
-		enroll_session &= ~FP_MODE_ENROLL_SESSION;
-	}
-	return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res)
-	     | (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET);
-}
-
-static bool fp_match_success(int match_result)
-{
-	if (match_result == EC_MKBP_FP_ERR_MATCH_YES ||
-	    match_result == EC_MKBP_FP_ERR_MATCH_YES_UPDATED ||
-	    match_result == EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED) {
-		return true;
-	}
-
-	return false;
-}
-
-static uint32_t fp_process_match(void)
-{
-	timestamp_t t0 = get_time();
-	int res = -1;
-	uint32_t updated = 0;
-	int32_t fgr = FP_NO_SUCH_TEMPLATE;
-
-	/* match finger against current templates */
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-	CPRINTS("Matching/%d ...", templ_valid);
-	if (templ_valid) {
-		res = fp_finger_match(fp_template[0], templ_valid, fp_buffer,
-				      &fgr, &updated);
-		CPRINTS("Match =>%d (finger %d)", res, fgr);
-
-		if (fp_match_success(res)) {
-			/*
-			 * Match succeded! Let's check if template number
-			 * is valid. If it is not valid, overwrite result
-			 * with EC_MKBP_FP_ERR_MATCH_NO_INTERNAL.
-			 */
-			if (fgr >= 0 && fgr < FP_MAX_FINGER_COUNT) {
-				fp_enable_positive_match_secret(fgr,
-					&positive_match_secret_state);
-			} else {
-				res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
-			}
-		} else if (res < 0) {
-			/*
-			 * Negative result means that there is a problem with
-			 * code responsible for matching. Overwrite it with
-			 * MATCH_NO_INTERNAL to let upper layers know what
-			 * happened.
-			 */
-			res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
-		}
-
-		if (res == EC_MKBP_FP_ERR_MATCH_YES_UPDATED)
-			templ_dirty |= updated;
-	} else {
-		CPRINTS("No enrolled templates");
-		res = EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES;
-	}
-
-	if (!fp_match_success(res))
-		timestamps_invalid |= FPSTATS_MATCHING_INV;
-
-	matching_time_us = time_since32(t0);
-	return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res)
-	| ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) & EC_MKBP_FP_MATCH_IDX_MASK);
-}
-
-static void fp_process_finger(void)
-{
-	timestamp_t t0 = get_time();
-	int res = fp_sensor_acquire_image_with_mode(fp_buffer,
-			FP_CAPTURE_TYPE(sensor_mode));
-	capture_time_us = time_since32(t0);
-	if (!res) {
-		uint32_t evt = EC_MKBP_FP_IMAGE_READY;
-
-		/* Clean up SPI before clocking up to avoid hang on the dsb
-		 * in dma_go. Ignore the return value to let the WDT reboot
-		 * the MCU (and avoid getting trapped in the loop).
-		 * b/112781659 */
-		res = spi_transaction_flush(&spi_devices[0]);
-		if (res)
-			CPRINTS("Failed to flush SPI: 0x%x", res);
-		/* we need CPU power to do the computations */
-		clock_enable_module(MODULE_FAST_CPU, 1);
-
-		if (sensor_mode & FP_MODE_ENROLL_IMAGE)
-			evt = fp_process_enroll();
-		else if (sensor_mode & FP_MODE_MATCH)
-			evt = fp_process_match();
-
-		sensor_mode &= ~FP_MODE_ANY_CAPTURE;
-		overall_time_us = time_since32(overall_t0);
-		send_mkbp_event(evt);
-
-		/* go back to lower power mode */
-		clock_enable_module(MODULE_FAST_CPU, 0);
-	} else {
-		timestamps_invalid |= FPSTATS_CAPTURE_INV;
-	}
-}
-#endif /* HAVE_FP_PRIVATE_DRIVER */
-
-void fp_task(void)
-{
-	int timeout_us = -1;
-
-	CPRINTS("FP_SENSOR_SEL: %s",
-		fp_sensor_type_to_str(get_fp_sensor_type()));
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	/* Reset and initialize the sensor IC */
-	fp_sensor_init();
-
-	while (1) {
-		uint32_t evt;
-		enum finger_state st = FINGER_NONE;
-
-		/* Wait for a sensor IRQ or a new mode configuration */
-		evt = task_wait_event(timeout_us);
-
-		if (evt & TASK_EVENT_UPDATE_CONFIG) {
-			uint32_t mode = sensor_mode;
-
-			gpio_disable_interrupt(GPIO_FPS_INT);
-			if ((mode ^ enroll_session) & FP_MODE_ENROLL_SESSION) {
-				if (mode & FP_MODE_ENROLL_SESSION) {
-					if (fp_enrollment_begin())
-						sensor_mode &=
-							~FP_MODE_ENROLL_SESSION;
-				} else {
-					fp_enrollment_finish(NULL);
-				}
-				enroll_session =
-					sensor_mode & FP_MODE_ENROLL_SESSION;
-			}
-			if (is_test_capture(mode)) {
-				fp_sensor_acquire_image_with_mode(fp_buffer,
-					FP_CAPTURE_TYPE(mode));
-				sensor_mode &= ~FP_MODE_CAPTURE;
-				send_mkbp_event(EC_MKBP_FP_IMAGE_READY);
-				continue;
-			} else if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
-				/* wait for a finger on the sensor */
-				fp_sensor_configure_detect();
-			}
-			if (sensor_mode & FP_MODE_DEEPSLEEP)
-				/* Shutdown the sensor */
-				fp_sensor_low_power();
-			if (sensor_mode & FP_MODE_FINGER_UP)
-				/* Poll the sensor to detect finger removal */
-				timeout_us = FINGER_POLLING_DELAY;
-			else
-				timeout_us = -1;
-			if (mode & FP_MODE_ANY_WAIT_IRQ) {
-				gpio_enable_interrupt(GPIO_FPS_INT);
-			} else if (mode & FP_MODE_RESET_SENSOR) {
-				fp_reset_and_clear_context();
-				sensor_mode &= ~FP_MODE_RESET_SENSOR;
-			} else if (mode & FP_MODE_SENSOR_MAINTENANCE) {
-				fp_maintenance();
-				sensor_mode &= ~FP_MODE_SENSOR_MAINTENANCE;
-			} else {
-				fp_sensor_low_power();
-			}
-		} else if (evt & (TASK_EVENT_SENSOR_IRQ | TASK_EVENT_TIMER)) {
-			overall_t0 = get_time();
-			timestamps_invalid = 0;
-			gpio_disable_interrupt(GPIO_FPS_INT);
-			if (sensor_mode & FP_MODE_ANY_DETECT_FINGER) {
-				st = fp_sensor_finger_status();
-				if (st == FINGER_PRESENT &&
-				    sensor_mode & FP_MODE_FINGER_DOWN) {
-					CPRINTS("Finger!");
-					sensor_mode &= ~FP_MODE_FINGER_DOWN;
-					send_mkbp_event(EC_MKBP_FP_FINGER_DOWN);
-				}
-				if (st == FINGER_NONE &&
-				    sensor_mode & FP_MODE_FINGER_UP) {
-					sensor_mode &= ~FP_MODE_FINGER_UP;
-					timeout_us = -1;
-					send_mkbp_event(EC_MKBP_FP_FINGER_UP);
-				}
-			}
-
-			if (st == FINGER_PRESENT &&
-			    sensor_mode & FP_MODE_ANY_CAPTURE)
-				fp_process_finger();
-
-			if (sensor_mode & FP_MODE_ANY_WAIT_IRQ) {
-				fp_sensor_configure_detect();
-				gpio_enable_interrupt(GPIO_FPS_INT);
-			} else {
-				fp_sensor_low_power();
-			}
-		}
-	}
-#else /* !HAVE_FP_PRIVATE_DRIVER */
-	while (1) {
-		uint32_t evt = task_wait_event(timeout_us);
-
-		send_mkbp_event(evt);
-	}
-#endif /* !HAVE_FP_PRIVATE_DRIVER */
-}
-
-static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_passthru *params = args->params;
-	void *out = args->response;
-	int rc;
-	int ret = EC_RES_SUCCESS;
-
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (params->len > args->params_size +
-	    offsetof(struct ec_params_fp_passthru, data) ||
-	    params->len > args->response_max)
-		return EC_RES_INVALID_PARAM;
-
-	rc = spi_transaction_async(&spi_devices[0], params->data,
-				   params->len, out, SPI_READBACK_ALL);
-	if (params->flags & EC_FP_FLAG_NOT_COMPLETE)
-		rc |= spi_transaction_wait(&spi_devices[0]);
-	else
-		rc |= spi_transaction_flush(&spi_devices[0]);
-
-	if (rc == EC_ERROR_TIMEOUT)
-		ret = EC_RES_TIMEOUT;
-	else if (rc)
-		ret = EC_RES_ERROR;
-
-	args->response_size = params->len;
-	return ret;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_PASSTHRU, fp_command_passthru, EC_VER_MASK(0));
-
-static enum ec_status fp_command_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_info *r = args->response;
-
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	if (fp_sensor_get_info(r) < 0)
-#endif
-		return EC_RES_UNAVAILABLE;
-
-	r->template_size = FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE;
-	r->template_max = FP_MAX_FINGER_COUNT;
-	r->template_valid = templ_valid;
-	r->template_dirty = templ_dirty;
-	r->template_version = FP_TEMPLATE_FORMAT_VERSION;
-
-	/* V1 is identical to V0 with more information appended */
-	args->response_size = args->version ? sizeof(*r) :
-			sizeof(struct ec_response_fp_info_v0);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_INFO, fp_command_info,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-BUILD_ASSERT(FP_CONTEXT_NONCE_BYTES == 12);
-
-int validate_fp_buffer_offset(const uint32_t buffer_size, const uint32_t offset,
-			      const uint32_t size)
-{
-	uint32_t bytes_requested;
-
-	if (check_add_overflow(size, offset, &bytes_requested))
-		return EC_ERROR_OVERFLOW;
-
-	if (bytes_requested > buffer_size)
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_status fp_command_frame(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_frame *params = args->params;
-	void *out = args->response;
-	uint32_t idx = FP_FRAME_GET_BUFFER_INDEX(params->offset);
-	uint32_t offset = params->offset & FP_FRAME_OFFSET_MASK;
-	uint32_t size = params->size;
-	uint32_t fgr;
-	uint8_t key[SBP_ENC_KEY_LEN];
-	struct ec_fp_template_encryption_metadata *enc_info;
-	int ret;
-
-	if (size > args->response_max)
-		return EC_RES_INVALID_PARAM;
-
-	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
-		/* The host requested a frame. */
-		if (system_is_locked())
-			return EC_RES_ACCESS_DENIED;
-		if (!is_raw_capture(sensor_mode))
-			offset += FP_SENSOR_IMAGE_OFFSET;
-
-		ret = validate_fp_buffer_offset(sizeof(fp_buffer), offset,
-						size);
-		if (ret != EC_SUCCESS)
-			return EC_RES_INVALID_PARAM;
-
-		memcpy(out, fp_buffer + offset, size);
-		args->response_size = size;
-		return EC_RES_SUCCESS;
-	}
-
-	/* The host requested a template. */
-
-	/* Templates are numbered from 1 in this host request. */
-	fgr = idx - FP_FRAME_INDEX_TEMPLATE;
-
-	if (fgr >= FP_MAX_FINGER_COUNT)
-		return EC_RES_INVALID_PARAM;
-	if (fgr >= templ_valid)
-		return EC_RES_UNAVAILABLE;
-	ret = validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
-	if (ret != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	if (!offset) {
-		/* Host has requested the first chunk, do the encryption. */
-		timestamp_t now = get_time();
-		/* Encrypted template is after the metadata. */
-		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
-		/* Positive match salt is after the template. */
-		uint8_t *positive_match_salt =
-			encrypted_template + sizeof(fp_template[0]);
-		size_t encrypted_blob_size = sizeof(fp_template[0]) +
-					     sizeof(fp_positive_match_salt[0]);
-
-		/* b/114160734: Not more than 1 encrypted message per second. */
-		if (!timestamp_expired(encryption_deadline, &now))
-			return EC_RES_BUSY;
-		encryption_deadline.val = now.val + (1 * SECOND);
-
-		memset(fp_enc_buffer, 0, sizeof(fp_enc_buffer));
-		/*
-		 * The beginning of the buffer contains nonce, encryption_salt
-		 * and tag.
-		 */
-		enc_info = (void *)fp_enc_buffer;
-		enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION;
-		init_trng();
-		rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES);
-		rand_bytes(enc_info->encryption_salt,
-			   FP_CONTEXT_ENCRYPTION_SALT_BYTES);
-		exit_trng();
-
-		if (fgr == template_newly_enrolled) {
-			/*
-			 * Newly enrolled templates need new positive match
-			 * salt, new positive match secret and new validation
-			 * value.
-			 */
-			template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
-			init_trng();
-			rand_bytes(fp_positive_match_salt[fgr],
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
-		}
-
-		ret = derive_encryption_key(key, enc_info->encryption_salt);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to derive key", fgr);
-			return EC_RES_UNAVAILABLE;
-		}
-
-		/*
-		 * Copy the payload to |fp_enc_buffer| where it will be
-		 * encrypted in-place.
-		 */
-		memcpy(encrypted_template, fp_template[fgr],
-		       sizeof(fp_template[0]));
-		memcpy(positive_match_salt, fp_positive_match_salt[fgr],
-		       sizeof(fp_positive_match_salt[0]));
-
-		/* Encrypt the secret blob in-place. */
-		ret = aes_gcm_encrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
-				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
-				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
-		always_memset(key, 0, sizeof(key));
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to encrypt template", fgr);
-			return EC_RES_UNAVAILABLE;
-		}
-		templ_dirty &= ~BIT(fgr);
-	}
-	memcpy(out, fp_enc_buffer + offset, size);
-	args->response_size = size;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_FRAME, fp_command_frame, EC_VER_MASK(0));
-
-static enum ec_status fp_command_stats(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_stats *r = args->response;
-
-	r->capture_time_us = capture_time_us;
-	r->matching_time_us = matching_time_us;
-	r->overall_time_us = overall_time_us;
-	r->overall_t0.lo = overall_t0.le.lo;
-	r->overall_t0.hi = overall_t0.le.hi;
-	r->timestamps_invalid = timestamps_invalid;
-	/*
-	 * Note that this is set to FP_NO_SUCH_TEMPLATE when positive match
-	 * secret is read/disabled, and we are not using this field in biod.
-	 */
-	r->template_matched = positive_match_secret_state.template_matched;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_STATS, fp_command_stats, EC_VER_MASK(0));
-
-static bool template_needs_validation_value(
-	struct ec_fp_template_encryption_metadata *enc_info)
-{
-	return enc_info->struct_version == 3
-		&& FP_TEMPLATE_FORMAT_VERSION == 4;
-}
-
-static int validate_template_format(
-	struct ec_fp_template_encryption_metadata *enc_info)
-{
-	if (template_needs_validation_value(enc_info))
-		/* The host requested migration to v4. */
-		return EC_RES_SUCCESS;
-
-	if (enc_info->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
-		CPRINTS("Invalid template format %d", enc_info->struct_version);
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_template *params = args->params;
-	uint32_t size = params->size & ~FP_TEMPLATE_COMMIT;
-	int xfer_complete = params->size & FP_TEMPLATE_COMMIT;
-	uint32_t offset = params->offset;
-	uint32_t idx = templ_valid;
-	uint8_t key[SBP_ENC_KEY_LEN];
-	struct ec_fp_template_encryption_metadata *enc_info;
-	int ret;
-
-	/* Can we store one more template ? */
-	if (idx >= FP_MAX_FINGER_COUNT)
-		return EC_RES_OVERFLOW;
-
-	if (args->params_size !=
-	    size + offsetof(struct ec_params_fp_template, data))
-		return EC_RES_INVALID_PARAM;
-	ret = validate_fp_buffer_offset(sizeof(fp_enc_buffer), offset, size);
-	if (ret != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	memcpy(&fp_enc_buffer[offset], params->data, size);
-
-	if (xfer_complete) {
-		/* Encrypted template is after the metadata. */
-		uint8_t *encrypted_template = fp_enc_buffer + sizeof(*enc_info);
-		/* Positive match salt is after the template. */
-		uint8_t *positive_match_salt =
-			encrypted_template + sizeof(fp_template[0]);
-		size_t encrypted_blob_size;
-
-		/*
-		 * The complete encrypted template has been received, start
-		 * decryption.
-		 */
-		fp_clear_finger_context(idx);
-		/*
-		 * The beginning of the buffer contains nonce, encryption_salt
-		 * and tag.
-		 */
-		enc_info = (void *)fp_enc_buffer;
-		ret = validate_template_format(enc_info);
-		if (ret != EC_RES_SUCCESS) {
-			CPRINTS("fgr%d: Template format not supported", idx);
-			return EC_RES_INVALID_PARAM;
-		}
-
-		if (enc_info->struct_version <= 3) {
-			encrypted_blob_size = sizeof(fp_template[0]);
-		} else {
-			encrypted_blob_size =
-				sizeof(fp_template[0]) +
-				sizeof(fp_positive_match_salt[0]);
-		}
-
-		ret = derive_encryption_key(key, enc_info->encryption_salt);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to derive key", idx);
-			return EC_RES_UNAVAILABLE;
-		}
-
-		/* Decrypt the secret blob in-place. */
-		ret = aes_gcm_decrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
-				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
-				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
-		always_memset(key, 0, sizeof(key));
-		if (ret != EC_SUCCESS) {
-			CPRINTS("fgr%d: Failed to decipher template", idx);
-			/* Don't leave bad data in the template buffer */
-			fp_clear_finger_context(idx);
-			return EC_RES_UNAVAILABLE;
-		}
-		memcpy(fp_template[idx], encrypted_template,
-		       sizeof(fp_template[0]));
-		if (template_needs_validation_value(enc_info)) {
-			CPRINTS("fgr%d: Generating positive match salt.", idx);
-			init_trng();
-			rand_bytes(positive_match_salt,
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
-		}
-		if (bytes_are_trivial(positive_match_salt,
-				      sizeof(fp_positive_match_salt[0]))) {
-			CPRINTS("fgr%d: Trivial positive match salt.", idx);
-			always_memset(fp_template[idx], 0,
-				      sizeof(fp_template[0]));
-			return EC_RES_INVALID_PARAM;
-		}
-		memcpy(fp_positive_match_salt[idx], positive_match_salt,
-		       sizeof(fp_positive_match_salt[0]));
-
-		templ_valid++;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_TEMPLATE, fp_command_template, EC_VER_MASK(0));
-
-#ifdef CONFIG_CMD_FPSENSOR_DEBUG
-/* --- Debug console commands --- */
-
-/*
- * Send the current Fingerprint buffer to the host
- * it is formatted as an 8-bpp PGM ASCII file.
- *
- * In addition, it prepends a short Z-Modem download signature,
- * which triggers automatically your preferred viewer if you configure it
- * properly in "File transfer protocols" in the Minicom options menu.
- * (as triggered by Ctrl-A O)
- * +--------------------------------------------------------------------------+
- * |     Name             Program             Name U/D FullScr IO-Red. Multi  |
- * | A  zmodem     /usr/bin/sz -vv -b          Y    U    N       Y       Y    |
- *  [...]
- * | L  pgm        /usr/bin/display_pgm        N    D    N       Y       N    |
- * | M  Zmodem download string activates... L                                 |
- *
- * My /usr/bin/display_pgm looks like this:
- * #!/bin/sh
- * TMPF=$(mktemp)
- * ascii-xfr -rdv ${TMPF}
- * display ${TMPF}
- *
- * Alternative (if you're using screen as your terminal):
- *
- * From *outside* the chroot:
- *
- * Install ascii-xfr: sudo apt-get install minicom
- * Install imagemagick: sudo apt-get install imagemagick
- *
- * Add the following to your ${HOME}/.screenrc:
- *
- * zmodem catch
- * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display /tmp/finger.pgm"'
- *
- * From *outside the chroot*, use screen to connect to UART console:
- *
- * sudo screen -c ${HOME}/.screenrc /dev/pts/NN 115200
- *
- */
-static void upload_pgm_image(uint8_t *frame)
-{
-	int x, y;
-	uint8_t *ptr = frame;
-
-	/* fake Z-modem ZRQINIT signature */
-	CPRINTF("#IGNORE for ZModem\r**\030B00");
-	msleep(2000); /* let the download program start */
-	/* Print 8-bpp PGM ASCII header */
-	CPRINTF("P2\n%d %d\n255\n", FP_SENSOR_RES_X, FP_SENSOR_RES_Y);
-
-	for (y = 0; y < FP_SENSOR_RES_Y; y++) {
-		watchdog_reload();
-		for (x = 0; x < FP_SENSOR_RES_X; x++, ptr++)
-			CPRINTF("%d ", *ptr);
-		CPRINTF("\n");
-		cflush();
-	}
-
-	CPRINTF("\x04"); /* End Of Transmission */
-}
-
-static enum ec_error_list fp_console_action(uint32_t mode)
-{
-	int tries = 200;
-	uint32_t mode_output = 0;
-	int rc = 0;
-
-	if (!(sensor_mode & FP_MODE_RESET_SENSOR))
-		CPRINTS("Waiting for finger ...");
-
-	rc = fp_set_sensor_mode(mode, &mode_output);
-
-	if (rc != EC_RES_SUCCESS) {
-		/*
-		 * EC host command errors do not directly map to console command
-		 * errors.
-		 */
-		return EC_ERROR_UNKNOWN;
-	}
-
-	while (tries--) {
-		if (!(sensor_mode & FP_MODE_ANY_CAPTURE)) {
-			CPRINTS("done (events:%x)", fp_events);
-			return 0;
-		}
-		usleep(100 * MSEC);
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-int command_fpcapture(int argc, char **argv)
-{
-	int capture_type = FP_CAPTURE_SIMPLE_IMAGE;
-	uint32_t mode;
-	enum ec_error_list rc;
-
-	/*
-	 * TODO(b/142944002): Remove this redundant check for system_is_locked
-	 * once we have unit-tests/integration-tests in place.
-	 */
-	if (system_is_locked())
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (argc >= 2) {
-		char *e;
-
-		capture_type = strtoi(argv[1], &e, 0);
-		if (*e || capture_type < 0)
-			return EC_ERROR_PARAM1;
-	}
-	mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT)
-				  & FP_MODE_CAPTURE_TYPE_MASK);
-
-	rc = fp_console_action(mode);
-	if (rc == EC_SUCCESS)
-		upload_pgm_image(fp_buffer + FP_SENSOR_IMAGE_OFFSET);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND_FLAGS(fpcapture, command_fpcapture, NULL,
-			      "Capture fingerprint in PGM format",
-			      CMD_FLAG_RESTRICTED);
-
-int command_fpenroll(int argc, char **argv)
-{
-	enum ec_error_list rc;
-	int percent = 0;
-	uint32_t event;
-	static const char * const enroll_str[] = {"OK", "Low Quality",
-						  "Immobile", "Low Coverage"};
-
-	/*
-	 * TODO(b/142944002): Remove this redundant check for system_is_locked
-	 * once we have unit-tests/integration-tests in place.
-	 */
-	if (system_is_locked())
-		return EC_ERROR_ACCESS_DENIED;
-
-	do {
-		int tries = 1000;
-
-		rc = fp_console_action(FP_MODE_ENROLL_SESSION |
-				       FP_MODE_ENROLL_IMAGE);
-		if (rc != EC_SUCCESS)
-			break;
-		event = atomic_clear(&fp_events);
-		percent = EC_MKBP_FP_ENROLL_PROGRESS(event);
-		CPRINTS("Enroll capture: %s (%d%%)",
-			enroll_str[EC_MKBP_FP_ERRCODE(event) & 3], percent);
-		/* wait for finger release between captures */
-		sensor_mode = FP_MODE_ENROLL_SESSION | FP_MODE_FINGER_UP;
-		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
-		while (tries-- && sensor_mode & FP_MODE_FINGER_UP)
-			usleep(20 * MSEC);
-	} while (percent < 100);
-	sensor_mode = 0; /* reset FP_MODE_ENROLL_SESSION */
-	task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND_FLAGS(fpenroll, command_fpenroll, NULL,
-			      "Enroll a new fingerprint",
-			      CMD_FLAG_RESTRICTED);
-
-
-int command_fpmatch(int argc, char **argv)
-{
-	enum ec_error_list rc = fp_console_action(FP_MODE_MATCH);
-	uint32_t event = atomic_clear(&fp_events);
-
-	if (rc == EC_SUCCESS && event & EC_MKBP_FP_MATCH) {
-		uint32_t errcode = EC_MKBP_FP_ERRCODE(event);
-
-		CPRINTS("Match: %s (%d)",
-			errcode & EC_MKBP_FP_ERR_MATCH_YES ? "YES" : "NO",
-			errcode);
-	}
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND(fpmatch, command_fpmatch, NULL,
-			"Run match algorithm against finger");
-
-int command_fpclear(int argc, char **argv)
-{
-	/*
-	 * We intentionally run this on the fp_task so that we use the
-	 * same code path as host commands.
-	 */
-	enum ec_error_list rc = fp_console_action(FP_MODE_RESET_SENSOR);
-
-	if (rc < 0)
-		CPRINTS("Failed to clear fingerprint context: %d", rc);
-
-	atomic_clear(&fp_events);
-
-	return rc;
-}
-DECLARE_CONSOLE_COMMAND(fpclear, command_fpclear, NULL,
-			"Clear fingerprint sensor context");
-
-int command_fpmaintenance(int argc, char **argv)
-{
-#ifdef HAVE_FP_PRIVATE_DRIVER
-	return fp_maintenance();
-#else
-	return EC_SUCCESS;
-#endif /* #ifdef HAVE_FP_PRIVATE_DRIVER */
-}
-DECLARE_CONSOLE_COMMAND(fpmaintenance, command_fpmaintenance, NULL,
-			"Run fingerprint sensor maintenance");
-
-#endif /* CONFIG_CMD_FPSENSOR_DEBUG */
diff --git a/common/fpsensor/fpsensor_crypto.c b/common/fpsensor/fpsensor_crypto.c
deleted file mode 100644
index 73d7aca681..0000000000
--- a/common/fpsensor/fpsensor_crypto.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <stdbool.h>
-
-#include "aes.h"
-#include "aes-gcm.h"
-#include "cryptoc/util.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "rollback.h"
-
-#if !defined(CONFIG_AES) || !defined(CONFIG_AES_GCM) || \
-	!defined(CONFIG_ROLLBACK_SECRET_SIZE)
-#error "fpsensor requires AES, AES_GCM and ROLLBACK_SECRET_SIZE"
-#endif
-
-static int get_ikm(uint8_t *ikm)
-{
-	int ret;
-
-	if (!fp_tpm_seed_is_set()) {
-		CPRINTS("Seed hasn't been set.");
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/*
-	 * The first CONFIG_ROLLBACK_SECRET_SIZE bytes of IKM are read from the
-	 * anti-rollback blocks.
-	 */
-	ret = rollback_get_secret(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to read rollback secret: %d", ret);
-		return EC_ERROR_HW_INTERNAL;
-	}
-	/*
-	 * IKM is the concatenation of the rollback secret and the seed from
-	 * the TPM.
-	 */
-	memcpy(ikm + CONFIG_ROLLBACK_SECRET_SIZE, tpm_seed, sizeof(tpm_seed));
-
-	return EC_SUCCESS;
-}
-
-static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size,
-			 const uint8_t *ikm, size_t ikm_size)
-{
-	/*
-	 * Derive a key with the "extract" step of HKDF
-	 * https://tools.ietf.org/html/rfc5869#section-2.2
-	 */
-	hmac_SHA256(prk, salt, salt_size, ikm, ikm_size);
-}
-
-static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size,
-				uint8_t *prk, size_t prk_size,
-				uint8_t *info, size_t info_size)
-{
-	uint8_t key_buf[SHA256_DIGEST_SIZE];
-	uint8_t message_buf[SHA256_DIGEST_SIZE + 1];
-
-	if (out_key_size > SHA256_DIGEST_SIZE) {
-		CPRINTS("Deriving key material longer than SHA256_DIGEST_SIZE "
-			"requires more steps of HKDF expand.");
-		return EC_ERROR_INVAL;
-	}
-
-	if (info_size > SHA256_DIGEST_SIZE) {
-		CPRINTS("Info size too big for HKDF.");
-		return EC_ERROR_INVAL;
-	}
-
-	memcpy(message_buf, info, info_size);
-	/* 1 step, set the counter byte to 1. */
-	message_buf[info_size] = 0x01;
-	hmac_SHA256(key_buf, prk, prk_size, message_buf, info_size + 1);
-
-	memcpy(out_key, key_buf, out_key_size);
-	always_memset(key_buf, 0, sizeof(key_buf));
-
-	return EC_SUCCESS;
-}
-
-int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk,
-		size_t prk_size, const uint8_t *info, size_t info_size)
-{
-	/*
-	 * "Expand" step of HKDF.
-	 * https://tools.ietf.org/html/rfc5869#section-2.3
-	 */
-#define HASH_LEN SHA256_DIGEST_SIZE
-	uint8_t count = 1;
-	const uint8_t *T = out_key;
-	size_t T_len = 0;
-	uint8_t T_buffer[HASH_LEN];
-	/* Number of blocks. */
-	const uint32_t N = DIV_ROUND_UP(L, HASH_LEN);
-	uint8_t info_buffer[HASH_LEN + HKDF_MAX_INFO_SIZE + sizeof(count)];
-	bool arguments_valid = false;
-
-	if (out_key == NULL || L == 0)
-		CPRINTS("HKDF expand: output buffer not valid.");
-	else if (prk == NULL)
-		CPRINTS("HKDF expand: prk is NULL.");
-	else if (info == NULL && info_size > 0)
-		CPRINTS("HKDF expand: info is NULL but info size is not zero.");
-	else if (info_size > HKDF_MAX_INFO_SIZE)
-		CPRINTF("HKDF expand: info size larger than %d bytes.\n",
-			HKDF_MAX_INFO_SIZE);
-	else if (N > HKDF_SHA256_MAX_BLOCK_COUNT)
-		CPRINTS("HKDF expand: output key size too large.");
-	else
-		arguments_valid = true;
-
-	if (!arguments_valid)
-		return EC_ERROR_INVAL;
-
-	while (L > 0) {
-		const size_t block_size = L < HASH_LEN ? L : HASH_LEN;
-
-		memcpy(info_buffer, T, T_len);
-		memcpy(info_buffer + T_len, info, info_size);
-		info_buffer[T_len + info_size] = count;
-		hmac_SHA256(T_buffer, prk, prk_size, info_buffer,
-			    T_len + info_size + sizeof(count));
-		memcpy(out_key, T_buffer, block_size);
-
-		T += T_len;
-		T_len = HASH_LEN;
-		count++;
-		out_key += block_size;
-		L -= block_size;
-	}
-	always_memset(T_buffer, 0, sizeof(T_buffer));
-	always_memset(info_buffer, 0, sizeof(info_buffer));
-	return EC_SUCCESS;
-#undef HASH_LEN
-}
-
-int derive_positive_match_secret(uint8_t *output,
-				 const uint8_t *input_positive_match_salt)
-{
-	int ret;
-	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
-	uint8_t prk[SHA256_DIGEST_SIZE];
-	static const char info_prefix[] = "positive_match_secret for user ";
-	uint8_t info[sizeof(info_prefix) - 1 + sizeof(user_id)];
-
-	if (bytes_are_trivial(input_positive_match_salt,
-			      FP_POSITIVE_MATCH_SALT_BYTES)) {
-		CPRINTS("Failed to derive positive match secret: "
-			"salt bytes are trivial.");
-		return EC_ERROR_INVAL;
-	}
-
-	ret = get_ikm(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to get IKM: %d", ret);
-		return ret;
-	}
-
-	/* "Extract" step of HKDF. */
-	hkdf_extract(prk, input_positive_match_salt,
-		     FP_POSITIVE_MATCH_SALT_BYTES, ikm, sizeof(ikm));
-	always_memset(ikm, 0, sizeof(ikm));
-
-	memcpy(info, info_prefix, strlen(info_prefix));
-	memcpy(info + strlen(info_prefix), user_id, sizeof(user_id));
-
-	/* "Expand" step of HKDF. */
-	ret = hkdf_expand(output, FP_POSITIVE_MATCH_SECRET_BYTES, prk,
-			  sizeof(prk), info, sizeof(info));
-	always_memset(prk, 0, sizeof(prk));
-
-	/* Check that secret is not full of 0x00 or 0xff. */
-	if (bytes_are_trivial(output, FP_POSITIVE_MATCH_SECRET_BYTES)) {
-		CPRINTS("Failed to derive positive match secret: "
-			"derived secret bytes are trivial.");
-		ret = EC_ERROR_HW_INTERNAL;
-	}
-	return ret;
-}
-
-int derive_encryption_key(uint8_t *out_key, const uint8_t *salt)
-{
-	int ret;
-	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + sizeof(tpm_seed)];
-	uint8_t prk[SHA256_DIGEST_SIZE];
-
-	BUILD_ASSERT(SBP_ENC_KEY_LEN <= SHA256_DIGEST_SIZE);
-	BUILD_ASSERT(SBP_ENC_KEY_LEN <= CONFIG_ROLLBACK_SECRET_SIZE);
-	BUILD_ASSERT(sizeof(user_id) == SHA256_DIGEST_SIZE);
-
-	ret = get_ikm(ikm);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to get IKM: %d", ret);
-		return ret;
-	}
-
-	/* "Extract step of HKDF. */
-	hkdf_extract(prk, salt, FP_CONTEXT_ENCRYPTION_SALT_BYTES, ikm,
-		     sizeof(ikm));
-	always_memset(ikm, 0, sizeof(ikm));
-
-	/*
-	 * Only 1 "expand" step of HKDF since the size of the "info" context
-	 * (user_id in our case) is exactly SHA256_DIGEST_SIZE.
-	 * https://tools.ietf.org/html/rfc5869#section-2.3
-	 */
-	ret = hkdf_expand_one_step(out_key, SBP_ENC_KEY_LEN, prk, sizeof(prk),
-				   (uint8_t *)user_id, sizeof(user_id));
-	always_memset(prk, 0, sizeof(prk));
-
-	return ret;
-}
-
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size)
-{
-	int res;
-	AES_KEY aes_key;
-	GCM128_CONTEXT ctx;
-
-	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
-		CPRINTS("Invalid nonce size %d bytes", nonce_size);
-		return EC_ERROR_INVAL;
-	}
-
-	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	if (res) {
-		CPRINTS("Failed to set encryption key: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	/* CRYPTO functions return 1 on success, 0 on error. */
-	res = CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, ciphertext,
-				    text_size);
-	if (!res) {
-		CPRINTS("Failed to encrypt: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_tag(&ctx, tag, tag_size);
-	return EC_SUCCESS;
-}
-
-int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
-		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size)
-{
-	int res;
-	AES_KEY aes_key;
-	GCM128_CONTEXT ctx;
-
-	if (nonce_size != FP_CONTEXT_NONCE_BYTES) {
-		CPRINTS("Invalid nonce size %d bytes", nonce_size);
-		return EC_ERROR_INVAL;
-	}
-
-	res = AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	if (res) {
-		CPRINTS("Failed to set decryption key: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	/* CRYPTO functions return 1 on success, 0 on error. */
-	res = CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, plaintext,
-				    text_size);
-	if (!res) {
-		CPRINTS("Failed to decrypt: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	res = CRYPTO_gcm128_finish(&ctx, tag, tag_size);
-	if (!res) {
-		CPRINTS("Found incorrect tag: %d", res);
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
diff --git a/common/fpsensor/fpsensor_private.h b/common/fpsensor/fpsensor_private.h
deleted file mode 100644
index a42049dece..0000000000
--- a/common/fpsensor/fpsensor_private.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Internal header file for common/fpsensor directory */
-
-#ifndef __CROS_EC_FPSENSOR_PRIVATE_H
-#define __CROS_EC_FPSENSOR_PRIVATE_H
-
-#include <stdint.h>
-
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
-int validate_fp_buffer_offset(uint32_t buffer_size, uint32_t offset,
-			      uint32_t size);
-
-#endif /* __CROS_EC_FPSENSOR_PRIVATE_H */
diff --git a/common/fpsensor/fpsensor_state.c b/common/fpsensor/fpsensor_state.c
deleted file mode 100644
index db64110b56..0000000000
--- a/common/fpsensor/fpsensor_state.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cryptoc/util.h"
-#include "ec_commands.h"
-#include "fpsensor.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_private.h"
-#include "fpsensor_state.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Last acquired frame (aligned as it is used by arbitrary binary libraries) */
-uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE] FP_FRAME_SECTION __aligned(4);
-/* Fingers templates for the current user */
-uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
-/* Encryption/decryption buffer */
-/* TODO: On-the-fly encryption/decryption without a dedicated buffer */
-/*
- * Store the encryption metadata at the beginning of the buffer containing the
- * ciphered data.
- */
-uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
-/* Salt used in derivation of positive match secret. */
-uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
-
-struct positive_match_secret_state positive_match_secret_state = {
-	.template_matched = FP_NO_SUCH_TEMPLATE,
-	.readable = false,
-	.deadline.val = 0,
-};
-
-/* Index of the last enrolled but not retrieved template. */
-int8_t template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
-/* Number of used templates */
-uint32_t templ_valid;
-/* Bitmap of the templates with local modifications */
-uint32_t templ_dirty;
-/* Current user ID */
-uint32_t user_id[FP_CONTEXT_USERID_WORDS];
-/* Part of the IKM used to derive encryption keys received from the TPM. */
-uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
-/* Status of the FP encryption engine. */
-static uint32_t fp_encryption_status;
-
-uint32_t fp_events;
-
-uint32_t sensor_mode;
-
-void fp_task_simulate(void)
-{
-	int timeout_us = -1;
-
-	while (1)
-		task_wait_event(timeout_us);
-}
-
-void fp_clear_finger_context(int idx)
-{
-	always_memset(fp_template[idx], 0, sizeof(fp_template[0]));
-	always_memset(fp_positive_match_salt[idx], 0,
-		      sizeof(fp_positive_match_salt[0]));
-}
-
-/**
- * @warning |fp_buffer| contains data used by the matching algorithm that must
- * be released by calling fp_sensor_deinit() first. Call
- * fp_reset_and_clear_context instead of calling this directly.
- */
-static void _fp_clear_context(void)
-{
-	int idx;
-
-	templ_valid = 0;
-	templ_dirty = 0;
-	always_memset(fp_buffer, 0, sizeof(fp_buffer));
-	always_memset(fp_enc_buffer, 0, sizeof(fp_enc_buffer));
-	always_memset(user_id, 0, sizeof(user_id));
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-	for (idx = 0; idx < FP_MAX_FINGER_COUNT; idx++)
-		fp_clear_finger_context(idx);
-}
-
-void fp_reset_and_clear_context(void)
-{
-	if (fp_sensor_deinit() != EC_SUCCESS)
-		CPRINTS("Failed to deinit sensor");
-	_fp_clear_context();
-	if (fp_sensor_init() != EC_SUCCESS)
-		CPRINTS("Failed to init sensor");
-}
-
-int fp_get_next_event(uint8_t *out)
-{
-	uint32_t event_out = atomic_clear(&fp_events);
-
-	memcpy(out, &event_out, sizeof(event_out));
-
-	return sizeof(event_out);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_FINGERPRINT, fp_get_next_event);
-
-static enum ec_status fp_command_tpm_seed(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_seed *params = args->params;
-
-	if (params->struct_version != FP_TEMPLATE_FORMAT_VERSION) {
-		CPRINTS("Invalid seed format %d", params->struct_version);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (fp_encryption_status & FP_ENC_STATUS_SEED_SET) {
-		CPRINTS("Seed has already been set.");
-		return EC_RES_ACCESS_DENIED;
-	}
-	memcpy(tpm_seed, params->seed, sizeof(tpm_seed));
-	fp_encryption_status |= FP_ENC_STATUS_SEED_SET;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_SEED, fp_command_tpm_seed, EC_VER_MASK(0));
-
-int fp_tpm_seed_is_set(void)
-{
-	return fp_encryption_status & FP_ENC_STATUS_SEED_SET;
-}
-
-static enum ec_status
-fp_command_encryption_status(struct host_cmd_handler_args *args)
-{
-	struct ec_response_fp_encryption_status *r = args->response;
-
-	r->valid_flags = FP_ENC_STATUS_SEED_SET;
-	r->status = fp_encryption_status;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_ENC_STATUS, fp_command_encryption_status,
-		     EC_VER_MASK(0));
-
-static int validate_fp_mode(const uint32_t mode)
-{
-	uint32_t capture_type = FP_CAPTURE_TYPE(mode);
-	uint32_t algo_mode = mode & ~FP_MODE_CAPTURE_TYPE_MASK;
-	uint32_t cur_mode = sensor_mode;
-
-	if (capture_type >= FP_CAPTURE_TYPE_MAX)
-		return EC_ERROR_INVAL;
-
-	if (algo_mode & ~FP_VALID_MODES)
-		return EC_ERROR_INVAL;
-
-	if ((mode & FP_MODE_ENROLL_SESSION) &&
-	    templ_valid >= FP_MAX_FINGER_COUNT) {
-		CPRINTS("Maximum number of fingers already enrolled: %d",
-			FP_MAX_FINGER_COUNT);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Don't allow sensor reset if any other mode is
-	 * set (including FP_MODE_RESET_SENSOR itself).
-	 */
-	if (mode & FP_MODE_RESET_SENSOR) {
-		if (cur_mode & FP_VALID_MODES)
-			return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output)
-{
-	int ret;
-
-	if (mode_output == NULL)
-		return EC_RES_INVALID_PARAM;
-
-	ret = validate_fp_mode(mode);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Invalid FP mode 0x%x", mode);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (!(mode & FP_MODE_DONT_CHANGE)) {
-		sensor_mode = mode;
-		task_set_event(TASK_ID_FPSENSOR, TASK_EVENT_UPDATE_CONFIG);
-	}
-
-	*mode_output = sensor_mode;
-	return EC_RES_SUCCESS;
-}
-
-static enum ec_status fp_command_mode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_mode *p = args->params;
-	struct ec_response_fp_mode *r = args->response;
-
-	int ret = fp_set_sensor_mode(p->mode, &r->mode);
-
-	if (ret == EC_RES_SUCCESS)
-		args->response_size = sizeof(*r);
-
-	return ret;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_MODE, fp_command_mode, EC_VER_MASK(0));
-
-static enum ec_status fp_command_context(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_context_v1 *p = args->params;
-	uint32_t mode_output;
-
-	switch (p->action) {
-	case FP_CONTEXT_ASYNC:
-		if (sensor_mode & FP_MODE_RESET_SENSOR)
-			return EC_RES_BUSY;
-
-		/**
-		 * Trigger a call to fp_reset_and_clear_context() by
-		 * requesting a reset. Since that function triggers a call to
-		 * fp_sensor_open(), this must be asynchronous because
-		 * fp_sensor_open() can take ~175 ms. See http://b/137288498.
-		 */
-		return fp_set_sensor_mode(FP_MODE_RESET_SENSOR, &mode_output);
-
-	case FP_CONTEXT_GET_RESULT:
-		if (sensor_mode & FP_MODE_RESET_SENSOR)
-			return EC_RES_BUSY;
-
-		memcpy(user_id, p->userid, sizeof(user_id));
-		return EC_RES_SUCCESS;
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_CONTEXT, fp_command_context, EC_VER_MASK(1));
-
-int fp_enable_positive_match_secret(uint32_t fgr,
-				    struct positive_match_secret_state *state)
-{
-	timestamp_t now;
-
-	if (state->readable) {
-		CPRINTS("Error: positive match secret already readable.");
-		fp_disable_positive_match_secret(state);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	now = get_time();
-	state->template_matched = fgr;
-	state->readable = true;
-	state->deadline.val = now.val + (5 * SECOND);
-	return EC_SUCCESS;
-}
-
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state)
-{
-	state->template_matched = FP_NO_SUCH_TEMPLATE;
-	state->readable = false;
-	state->deadline.val = 0;
-}
-
-static enum ec_status fp_command_read_match_secret(
-	struct host_cmd_handler_args *args)
-{
-	const struct ec_params_fp_read_match_secret *params = args->params;
-	struct ec_response_fp_read_match_secret *response = args->response;
-	int8_t fgr = params->fgr;
-	timestamp_t now = get_time();
-	struct positive_match_secret_state state_copy
-		= positive_match_secret_state;
-
-	fp_disable_positive_match_secret(&positive_match_secret_state);
-
-	if (fgr < 0 || fgr >= FP_MAX_FINGER_COUNT) {
-		CPRINTS("Invalid finger number %d", fgr);
-		return EC_RES_INVALID_PARAM;
-	}
-	if (timestamp_expired(state_copy.deadline, &now)) {
-		CPRINTS("Reading positive match secret disallowed: "
-			"deadline has passed.");
-		return EC_RES_TIMEOUT;
-	}
-	if (fgr != state_copy.template_matched || !state_copy.readable) {
-		CPRINTS("Positive match secret for finger %d is not meant to "
-			"be read now.", fgr);
-		return EC_RES_ACCESS_DENIED;
-	}
-
-	if (derive_positive_match_secret(response->positive_match_secret,
-					 fp_positive_match_salt[fgr])
-		!= EC_SUCCESS) {
-		CPRINTS("Failed to derive positive match secret for finger %d",
-			fgr);
-		/* Keep the template and encryption salt. */
-		return EC_RES_ERROR;
-	}
-	CPRINTS("Derived positive match secret for finger %d", fgr);
-	args->response_size = sizeof(*response);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FP_READ_MATCH_SECRET, fp_command_read_match_secret,
-		     EC_VER_MASK(0));
diff --git a/common/gesture.c b/common/gesture.c
deleted file mode 100644
index 88d79448a5..0000000000
--- a/common/gesture.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Board specific gesture recognition */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "gesture.h"
-#include "lid_switch.h"
-#include "lightbar.h"
-#include "motion_sense.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_GESTURE, outstr)
-#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ## args)
-
-
-/*
- * Double tap detection parameters
- * Double tap works by looking for two isolated Z-axis accelerometer impulses
- * preceded and followed by relatively calm periods of accelerometer motion.
- *
- * Define an outer and inner window. The inner window specifies how
- * long the tap impulse is expected to last. The outer window specifies the
- * period before the initial tap impluse and after the final tap impulse for
- * which to check for relatively calm periods. In between the two impulses
- * there is a minimum and maximum interstice time allowed.
- */
-#define OUTER_WINDOW \
-	(CONFIG_GESTURE_TAP_OUTER_WINDOW_T / \
-	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define INNER_WINDOW \
-	(CONFIG_GESTURE_TAP_INNER_WINDOW_T / \
-	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MIN_INTERSTICE \
-	(CONFIG_GESTURE_TAP_MIN_INTERSTICE_T / \
-	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MAX_INTERSTICE \
-	(CONFIG_GESTURE_TAP_MAX_INTERSTICE_T / \
-	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MAX_WINDOW OUTER_WINDOW
-
-/* State machine states for detecting double tap */
-enum tap_states {
-	/* Look for calm before the storm */
-	TAP_IDLE,
-	/* Record first Z impulse */
-	TAP_IMPULSE_1,
-
-	/* Eye of the storm, expect Z motion to drop and then suddenly spike */
-	TAP_INTERSTICE_DROP,
-	TAP_INTERSTICE_RISE,
-
-	/* Record second Z impulse */
-	TAP_IMPULSE_2,
-	/* Should be quiet after the storm */
-	TAP_AFTER_EVENT
-};
-
-/* Tap sensor to use */
-static struct motion_sensor_t *sensor =
-&motion_sensors[CONFIG_GESTURE_TAP_SENSOR];
-
-/* Tap state information */
-static int history_z[MAX_WINDOW];  /* Changes in Z */
-static int history_xy[MAX_WINDOW]; /* Changes in X and Y */
-static int state, history_idx;
-static int history_initialized, history_init_index;
-static int tap_debug;
-
-/* Tap detection flag */
-static int tap_detection;
-
-/*
- * TODO(crosbug.com/p/33102): Cleanup this function: break into multiple
- * functions and generalize so it can be used for other boards.
- */
-static int gesture_tap_for_battery(void)
-{
-	/* Current and previous accel x,y,z */
-	int x, y, z;
-	static int x_p, y_p, z_p;
-
-	/* Number of iterations in this state */
-	static int state_cnt;
-
-	/*
-	 * Running sums of data diffs for inner and outer windows.
-	 * Z data kept separate from X and Y data
-	 */
-	static int sum_z_inner, sum_z_outer, sum_xy_inner, sum_xy_outer;
-
-	/* Total variation in each signal, normalized for window size */
-	int delta_z_outer, delta_z_inner, delta_xy_outer, delta_xy_inner;
-
-	/* Max variation seen during tap event and state cnts since max */
-	static int delta_z_inner_max;
-	static int cnts_since_max;
-
-	/* Interstice Z motion thresholds */
-	static int z_drop_thresh, z_rise_thresh;
-
-	int history_idx_inner, state_p;
-	int ret = 0;
-
-	/* Get data */
-	x = sensor->xyz[0];
-	y = sensor->xyz[1];
-	z = sensor->xyz[2];
-
-	/*
-	 * Calculate history of change in Z sensor and keeping
-	 * running sums for the past.
-	 */
-	history_idx_inner = history_idx - INNER_WINDOW;
-	if (history_idx_inner < 0)
-		history_idx_inner += MAX_WINDOW;
-	sum_z_inner -= history_z[history_idx_inner];
-	sum_z_outer -= history_z[history_idx];
-	history_z[history_idx] = ABS(z - z_p);
-	sum_z_inner += history_z[history_idx];
-	sum_z_outer += history_z[history_idx];
-
-	/*
-	 * Calculate history of change in X and Y sensors combined
-	 * and keep a running sum of the change over the past.
-	 */
-	sum_xy_inner -= history_xy[history_idx_inner];
-	sum_xy_outer -= history_xy[history_idx];
-	history_xy[history_idx] = ABS(x - x_p) + ABS(y - y_p);
-	sum_xy_inner += history_xy[history_idx];
-	sum_xy_outer += history_xy[history_idx];
-
-	/* Increment history index */
-	history_idx = (history_idx == MAX_WINDOW - 1) ? 0 : (history_idx + 1);
-
-	/* Store previous X, Y, Z data */
-	x_p = x;
-	y_p = y;
-	z_p = z;
-
-	/*
-	 * Ignore data until we fill history buffer and wrap around. If
-	 * detection is paused, history_init_index will store the index
-	 * when paused, so that when re-started, we will wait until we
-	 * wrap around again.
-	 */
-	if (history_idx == history_init_index)
-		history_initialized = 1;
-	if (!history_initialized)
-		return 0;
-
-	/*
-	 * Normalize data based on window size and isolate outer and inner
-	 * window data.
-	 */
-	delta_z_outer = (sum_z_outer - sum_z_inner) * 1000 /
-			(OUTER_WINDOW - INNER_WINDOW);
-	delta_z_inner = sum_z_inner * 1000 / INNER_WINDOW;
-	delta_xy_outer = (sum_xy_outer - sum_xy_inner) * 1000 /
-			(OUTER_WINDOW - INNER_WINDOW);
-	delta_xy_inner = sum_xy_inner * 1000 / INNER_WINDOW;
-
-	state_cnt++;
-	state_p = state;
-
-	switch (state) {
-	case TAP_IDLE:
-		/* Look for a sudden increase in Z movement */
-		if (delta_z_inner > 30000 &&
-		    delta_z_inner > 13 * delta_z_outer &&
-		    delta_z_inner > 1 * delta_xy_inner) {
-			delta_z_inner_max = delta_z_inner;
-			state_cnt = 0;
-			state = TAP_IMPULSE_1;
-		}
-		break;
-
-	case TAP_IMPULSE_1:
-		/* Find the peak inner window of Z movement */
-		if (delta_z_inner > delta_z_inner_max) {
-			delta_z_inner_max = delta_z_inner;
-			cnts_since_max = state_cnt;
-		}
-
-		/* After inner window has passed, move to next state */
-		if (state_cnt >= INNER_WINDOW) {
-			state = TAP_INTERSTICE_DROP;
-			z_drop_thresh = delta_z_inner_max / 12;
-			z_rise_thresh = delta_z_inner_max / 3;
-			state_cnt += INNER_WINDOW - cnts_since_max;
-		}
-		break;
-
-	case TAP_INTERSTICE_DROP:
-		/* Check for z motion to go back down first */
-		if (delta_z_inner < z_drop_thresh)
-			state = TAP_INTERSTICE_RISE;
-
-		if (state_cnt > MAX_INTERSTICE)
-			state = TAP_IDLE;
-
-		break;
-
-	case TAP_INTERSTICE_RISE:
-		/* Then, check for z motion to go back up */
-		if (delta_z_inner > z_rise_thresh) {
-			if (state_cnt < MIN_INTERSTICE) {
-				state = TAP_IDLE;
-			} else {
-				delta_z_inner_max = delta_z_inner;
-				state_cnt = 0;
-				state = TAP_IMPULSE_2;
-			}
-		}
-
-		if (state_cnt > MAX_INTERSTICE)
-			state = TAP_IDLE;
-		break;
-
-	case TAP_IMPULSE_2:
-		/* Find the peak inner window of Z movement */
-		if (delta_z_inner > delta_z_inner_max) {
-			delta_z_inner_max = delta_z_inner;
-			cnts_since_max = state_cnt;
-		}
-
-		/* After inner window has passed, move to next state */
-		if (state_cnt >= INNER_WINDOW) {
-			state = TAP_AFTER_EVENT;
-			state_cnt += INNER_WINDOW - cnts_since_max;
-		}
-
-	case TAP_AFTER_EVENT:
-		/* Check for small Z movement after the event */
-		if (state_cnt < OUTER_WINDOW)
-			break;
-
-		if (2 * delta_z_inner_max > 3 * delta_z_outer &&
-		    delta_z_outer > 1 * delta_xy_outer)
-			ret = 1;
-
-		state = TAP_IDLE;
-		break;
-	}
-
-	/* On state transitions, print debug info */
-	if (tap_debug &&
-	    (state != state_p ||
-	     (state_cnt % 10000 == 9999))) {
-		/* make sure we don't divide by 0 */
-		if (delta_z_outer == 0 || delta_xy_inner == 0)
-			CPRINTS("tap st %d->%d, error div by 0",
-				state_p, state);
-		else
-			CPRINTS("tap st %d->%d, st_cnt %-3d "
-				"Z_in:Z_out %-3d, Z_in:XY_in %-3d "
-				"dZ_in %-8.3d, dZ_in_max %-8.3d, "
-				"dZ_out %-8.3d",
-				state_p, state, state_cnt,
-				delta_z_inner / delta_z_outer,
-				delta_z_inner / delta_xy_inner,
-				delta_z_inner,
-				delta_z_inner_max,
-				delta_z_outer);
-	}
-
-	return ret;
-}
-
-static void gesture_chipset_resume(void)
-{
-	/* disable tap detection */
-	tap_detection = 0;
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume,
-	     GESTURE_HOOK_PRIO);
-
-static void gesture_chipset_suspend(void)
-{
-	/*
-	 * Clear tap init and history initialized so that we have to
-	 * record a whole new set of data, and enable tap detection
-	 */
-	history_initialized = 0;
-	history_init_index = history_idx;
-	state = TAP_IDLE;
-	tap_detection = 1;
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend,
-	     GESTURE_HOOK_PRIO);
-
-void gesture_calc(uint32_t *event)
-{
-	/* Only check for gesture if lid is closed and tap detection is on */
-	if (!tap_detection || lid_is_open())
-		return;
-
-	if (gesture_tap_for_battery())
-		*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-}
-
-/*****************************************************************************/
-/* Console commands */
-static int command_tap_info(int argc, char **argv)
-{
-	int val;
-
-	ccprintf("tap:   %s\n", (tap_detection && !lid_is_open()) ?
-					"on" : "off");
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &val))
-			return EC_ERROR_PARAM1;
-		tap_debug = val;
-	}
-
-	ccprintf("debug: %s\n", tap_debug ? "on" : "off");
-	ccprintf("odr:   %d\n", sensor->drv->get_data_rate(sensor));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info,
-			"debug on/off",
-			"Print tap information");
-
diff --git a/common/gyro_cal.c b/common/gyro_cal.c
deleted file mode 100644
index 572e401b18..0000000000
--- a/common/gyro_cal.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gyro_cal.h"
-#include "string.h"
-#include <stdbool.h>
-
-/*
- * Maximum gyro bias correction (should be set based on expected max bias
- * of the given sensor). [rad/sec]
- */
-#define MAX_GYRO_BIAS FLOAT_TO_FP(0.2f)
-
-static void device_stillness_check(struct gyro_cal *gyro_cal,
-				   uint32_t sample_time_us);
-
-static void compute_gyro_cal(struct gyro_cal *gyro_cal,
-			     uint32_t calibration_time_us);
-
-static void check_window(struct gyro_cal *gyro_cal, uint32_t sample_time_us);
-
-/** Data tracker command enumeration. */
-enum gyro_cal_tracker_command {
-	/** Resets the local data used for data tracking. */
-	DO_RESET = 0,
-	/** Updates the local tracking data. */
-	DO_UPDATE_DATA,
-	/** Stores intermediate results for later recall. */
-	DO_STORE_DATA,
-	/** Computes and provides the results of the gate function. */
-	DO_EVALUATE
-};
-
-/**
- * Reset the gyro_cal's temperature statistics.
- *
- * @param gyro_cal Pointer to the gyro_cal data structure.
- */
-static void gyro_temperature_stats_tracker_reset(struct gyro_cal *gyro_cal);
-
-/**
- * Updates the temperature min/max and mean during the stillness period.
- *
- * @param gyro_cal		Pointer to the gyro_cal data structure.
- * @param temperature_kelvin	New temperature sample to include.
- */
-static void gyro_temperature_stats_tracker_update(struct gyro_cal *gyro_cal,
-						  int temperature_kelvin);
-
-/**
- * Store the tracker data to be used for calculation.
- *
- * @param gyro_cal Pointer to the gyro_cal data structure.
- */
-static void gyro_temperature_stats_tracker_store(struct gyro_cal *gyro_cal);
-
-/**
- * Compute whether or not the temperature values are in range.
- *
- * @param gyro_cal	Pointer to the gyro_cal data structure.
- * @return		'true' if the min and max temperature values exceed the
- *			range set by 'temperature_delta_limit_kelvin'.
- */
-static bool gyro_temperature_stats_tracker_eval(struct gyro_cal *gyro_cal);
-
-/**
- * Tracks the minimum and maximum gyroscope stillness window means.
- * Returns
- *
- * @param gyro_cal Pointer to the gyro_cal data structure.
- * @param do_this  Command enumerator that controls function behavior.
- */
-static void gyro_still_mean_tracker_reset(struct gyro_cal *gyro_cal);
-
-/**
- * Compute the min/max window mean values according to 'window_mean_tracker'.
- *
- * @param gyro_cal Pointer to the gyro_cal data structure.
- */
-static void gyro_still_mean_tracker_update(struct gyro_cal *gyro_cal);
-
-/**
- * Store the most recent "stillness" mean data to the gyro_cal data structure.
- *
- * @param gyro_cal Pointer to the gyro_cal data structure.
- */
-static void gyro_still_mean_tracker_store(struct gyro_cal *gyro_cal);
-
-/**
- * Compute whether or not the gyroscope window range is within the valid range.
- *
- * @param gyro_cal	Pointer to the gyro_cal data structure.
- * @return		'true' when the difference between gyroscope min and max
- *			window means are outside the range set by
- *			'stillness_mean_delta_limit'.
- */
-static bool gyro_still_mean_tracker_eval(struct gyro_cal *gyro_cal);
-
-void init_gyro_cal(struct gyro_cal *gyro_cal)
-{
-	gyro_still_mean_tracker_reset(gyro_cal);
-	gyro_temperature_stats_tracker_reset(gyro_cal);
-}
-
-void gyro_cal_get_bias(struct gyro_cal *gyro_cal, fpv3_t bias,
-		       int *temperature_kelvin, uint32_t *calibration_time_us)
-{
-	bias[X] = gyro_cal->bias_x;
-	bias[Y] = gyro_cal->bias_y;
-	bias[Z] = gyro_cal->bias_z;
-	*calibration_time_us = gyro_cal->calibration_time_us;
-	*temperature_kelvin = gyro_cal->bias_temperature_kelvin;
-}
-
-void gyro_cal_set_bias(struct gyro_cal *gyro_cal, fpv3_t bias,
-		       int temperature_kelvin, uint32_t calibration_time_us)
-{
-	gyro_cal->bias_x = bias[X];
-	gyro_cal->bias_y = bias[Y];
-	gyro_cal->bias_z = bias[Z];
-	gyro_cal->calibration_time_us = calibration_time_us;
-	gyro_cal->bias_temperature_kelvin = temperature_kelvin;
-}
-
-void gyro_cal_remove_bias(struct gyro_cal *gyro_cal, fpv3_t in, fpv3_t out)
-{
-	if (gyro_cal->gyro_calibration_enable) {
-		out[X] = in[X] - gyro_cal->bias_x;
-		out[Y] = in[Y] - gyro_cal->bias_y;
-		out[Z] = in[Z] - gyro_cal->bias_z;
-	}
-}
-
-bool gyro_cal_new_bias_available(struct gyro_cal *gyro_cal)
-{
-	bool new_gyro_cal_available = (gyro_cal->gyro_calibration_enable &&
-				       gyro_cal->new_gyro_cal_available);
-
-	/* Clear the flag. */
-	gyro_cal->new_gyro_cal_available = false;
-
-	return new_gyro_cal_available;
-}
-
-void gyro_cal_update_gyro(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			  fp_t x, fp_t y, fp_t z, int temperature_kelvin)
-{
-	/*
-	 * Make sure that a valid window end-time is set, and start the window
-	 * timer.
-	 */
-	if (gyro_cal->stillness_win_endtime_us <= 0) {
-		gyro_cal->stillness_win_endtime_us =
-			sample_time_us + gyro_cal->window_time_duration_us;
-
-		/* Start the window timer. */
-		gyro_cal->gyro_window_start_us = sample_time_us;
-	}
-
-	/* Update the temperature statistics. */
-	gyro_temperature_stats_tracker_update(gyro_cal, temperature_kelvin);
-
-	/* Pass gyro data to stillness detector */
-	gyro_still_det_update(&gyro_cal->gyro_stillness_detect,
-			      gyro_cal->stillness_win_endtime_us,
-			      sample_time_us, x, y, z);
-
-	/*
-	 * Perform a device stillness check, set next window end-time, and
-	 * possibly do a gyro bias calibration and stillness detector reset.
-	 */
-	device_stillness_check(gyro_cal, sample_time_us);
-}
-
-void gyro_cal_update_mag(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			 fp_t x, fp_t y, fp_t z)
-{
-	/* Pass magnetometer data to stillness detector. */
-	gyro_still_det_update(&gyro_cal->mag_stillness_detect,
-			      gyro_cal->stillness_win_endtime_us,
-			      sample_time_us, x, y, z);
-
-	/* Received a magnetometer sample; incorporate it into detection. */
-	gyro_cal->using_mag_sensor = true;
-
-	/*
-	 * Perform a device stillness check, set next window end-time, and
-	 * possibly do a gyro bias calibration and stillness detector reset.
-	 */
-	device_stillness_check(gyro_cal, sample_time_us);
-}
-
-void gyro_cal_update_accel(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			   fp_t x, fp_t y, fp_t z)
-{
-	/* Pass accelerometer data to stillnesss detector. */
-	gyro_still_det_update(&gyro_cal->accel_stillness_detect,
-			      gyro_cal->stillness_win_endtime_us,
-			      sample_time_us, x, y, z);
-
-	/*
-	 * Perform a device stillness check, set next window end-time, and
-	 * possibly do a gyro bias calibration and stillness detector reset.
-	 */
-	device_stillness_check(gyro_cal, sample_time_us);
-}
-
-/**
- * Handle the case where the device is found to be still. This function should
- * be called from device_stillness_check.
- *
- * @param gyro_cal Pointer to the gyroscope calibration struct.
- */
-static void handle_device_is_still(struct gyro_cal *gyro_cal)
-{
-	/*
-	 * Device is "still" logic:
-	 * If not previously still, then record the start time.
-	 * If stillness period is too long, then do a calibration.
-	 * Otherwise, continue collecting stillness data.
-	 */
-	bool stillness_duration_exceeded = false;
-
-	/*
-	 * If device was not previously still, set new start timestamp.
-	 */
-	if (!gyro_cal->prev_still) {
-		/*
-		 * Record the starting timestamp of the current stillness
-		 * window. This enables the calculation of total duration of
-		 * the stillness period.
-		 */
-		gyro_cal->start_still_time_us =
-			gyro_cal->gyro_stillness_detect.window_start_time;
-	}
-
-	/*
-	 * Check to see if current stillness period exceeds the desired limit.
-	 */
-	stillness_duration_exceeded =
-		gyro_cal->gyro_stillness_detect.last_sample_time >=
-		(gyro_cal->start_still_time_us +
-		 gyro_cal->max_still_duration_us);
-
-	/* Track the new stillness mean and temperature data. */
-	gyro_still_mean_tracker_store(gyro_cal);
-	gyro_temperature_stats_tracker_store(gyro_cal);
-
-	if (stillness_duration_exceeded) {
-		/*
-		 * The current stillness has gone too long. Do a calibration
-		 * with the current data and reset.
-		 */
-
-		/*
-		 * Updates the gyro bias estimate with the current window data
-		 * and resets the stats.
-		 */
-		gyro_still_det_reset(&gyro_cal->accel_stillness_detect,
-				     /*reset_stats=*/true);
-		gyro_still_det_reset(&gyro_cal->gyro_stillness_detect,
-				     /*reset_stats=*/true);
-		gyro_still_det_reset(&gyro_cal->mag_stillness_detect,
-				     /*reset_stats=*/true);
-
-		/*
-		 * Resets the local calculations because the stillness
-		 * period is over.
-		 */
-		gyro_still_mean_tracker_reset(gyro_cal);
-		gyro_temperature_stats_tracker_reset(gyro_cal);
-
-		/* Computes a new gyro offset estimate. */
-		compute_gyro_cal(
-			gyro_cal,
-			gyro_cal->gyro_stillness_detect.last_sample_time);
-
-		/*
-		 * Update stillness flag. Force the start of a new
-		 * stillness period.
-		 */
-		gyro_cal->prev_still = false;
-	} else {
-		/* Continue collecting stillness data. */
-
-		/* Extend the stillness period. */
-		gyro_still_det_reset(&gyro_cal->accel_stillness_detect,
-				     /*reset_stats=*/false);
-		gyro_still_det_reset(&gyro_cal->gyro_stillness_detect,
-				     /*reset_stats=*/false);
-		gyro_still_det_reset(&gyro_cal->mag_stillness_detect,
-				     /*reset_stats=*/false);
-
-		/* Update the stillness flag. */
-		gyro_cal->prev_still = true;
-	}
-}
-
-static void handle_device_not_still(struct gyro_cal *gyro_cal)
-{
-	/* Device is NOT still; motion detected. */
-
-	/*
-	 * If device was previously still and the total stillness
-	 * duration is not "too short", then do a calibration with the
-	 * data accumulated thus far.
-	 */
-	bool stillness_duration_too_short =
-		gyro_cal->gyro_stillness_detect.window_start_time <
-		(gyro_cal->start_still_time_us +
-		 gyro_cal->min_still_duration_us);
-
-	if (gyro_cal->prev_still && !stillness_duration_too_short)
-		compute_gyro_cal(
-			gyro_cal,
-			gyro_cal->gyro_stillness_detect.window_start_time);
-
-	/* Reset the stillness detectors and the stats. */
-	gyro_still_det_reset(&gyro_cal->accel_stillness_detect,
-			     /*reset_stats=*/true);
-	gyro_still_det_reset(&gyro_cal->gyro_stillness_detect,
-			     /*reset_stats=*/true);
-	gyro_still_det_reset(&gyro_cal->mag_stillness_detect,
-			     /*reset_stats=*/true);
-
-	/* Resets the temperature and sensor mean data. */
-	gyro_temperature_stats_tracker_reset(gyro_cal);
-	gyro_still_mean_tracker_reset(gyro_cal);
-
-	/* Update stillness flag. */
-	gyro_cal->prev_still = false;
-}
-
-void device_stillness_check(struct gyro_cal *gyro_cal, uint32_t sample_time_us)
-{
-	bool min_max_temp_exceeded = false;
-	bool mean_not_stable = false;
-	bool device_is_still = false;
-	fp_t conf_not_rot = INT_TO_FP(0);
-	fp_t conf_not_accel = INT_TO_FP(0);
-	fp_t conf_still = INT_TO_FP(0);
-
-	/* Check the window timer. */
-	check_window(gyro_cal, sample_time_us);
-
-	/* Is there enough data to do a stillness calculation? */
-	if ((!gyro_cal->mag_stillness_detect.stillness_window_ready &&
-	     gyro_cal->using_mag_sensor) ||
-	    !gyro_cal->accel_stillness_detect.stillness_window_ready ||
-	    !gyro_cal->gyro_stillness_detect.stillness_window_ready)
-		return; /* Not yet, wait for more data. */
-
-	/* Set the next window end-time for the stillness detectors. */
-	gyro_cal->stillness_win_endtime_us =
-		sample_time_us + gyro_cal->window_time_duration_us;
-
-	/* Update the confidence scores for all sensors. */
-	gyro_still_det_compute(&gyro_cal->accel_stillness_detect);
-	gyro_still_det_compute(&gyro_cal->gyro_stillness_detect);
-	if (gyro_cal->using_mag_sensor) {
-		gyro_still_det_compute(&gyro_cal->mag_stillness_detect);
-	} else {
-		/*
-		 * Not using magnetometer, force stillness confidence to 100%.
-		 */
-		gyro_cal->mag_stillness_detect.stillness_confidence =
-			INT_TO_FP(1);
-	}
-
-	/* Updates the mean tracker data. */
-	gyro_still_mean_tracker_update(gyro_cal);
-
-	/*
-	 * Determine motion confidence scores (rotation, accelerating, and
-	 * stillness).
-	 */
-	conf_not_rot =
-		fp_mul(gyro_cal->gyro_stillness_detect.stillness_confidence,
-		       gyro_cal->mag_stillness_detect.stillness_confidence);
-	conf_not_accel = gyro_cal->accel_stillness_detect.stillness_confidence;
-	conf_still = fp_mul(conf_not_rot, conf_not_accel);
-
-	/* Evaluate the mean and temperature gate functions. */
-	mean_not_stable = gyro_still_mean_tracker_eval(gyro_cal);
-	min_max_temp_exceeded = gyro_temperature_stats_tracker_eval(gyro_cal);
-
-	/* Determines if the device is currently still. */
-	device_is_still = (conf_still > gyro_cal->stillness_threshold) &&
-			  !mean_not_stable && !min_max_temp_exceeded;
-
-	if (device_is_still)
-		handle_device_is_still(gyro_cal);
-	else
-		handle_device_not_still(gyro_cal);
-
-	/* Reset the window timer after we have processed data. */
-	gyro_cal->gyro_window_start_us = sample_time_us;
-}
-
-void compute_gyro_cal(struct gyro_cal *gyro_cal, uint32_t calibration_time_us)
-{
-	/* Check to see if new calibration values is within acceptable range. */
-	if (!(gyro_cal->gyro_stillness_detect.prev_mean[X] < MAX_GYRO_BIAS &&
-	      gyro_cal->gyro_stillness_detect.prev_mean[X] > -MAX_GYRO_BIAS &&
-	      gyro_cal->gyro_stillness_detect.prev_mean[Y] < MAX_GYRO_BIAS &&
-	      gyro_cal->gyro_stillness_detect.prev_mean[Y] > -MAX_GYRO_BIAS &&
-	      gyro_cal->gyro_stillness_detect.prev_mean[Z] < MAX_GYRO_BIAS &&
-	      gyro_cal->gyro_stillness_detect.prev_mean[Z] > -MAX_GYRO_BIAS))
-		/* Outside of range. Ignore, reset, and continue. */
-		return;
-
-	/* Record the new gyro bias offset calibration. */
-	gyro_cal->bias_x = gyro_cal->gyro_stillness_detect.prev_mean[X];
-	gyro_cal->bias_y = gyro_cal->gyro_stillness_detect.prev_mean[Y];
-	gyro_cal->bias_z = gyro_cal->gyro_stillness_detect.prev_mean[Z];
-
-	/*
-	 * Store the calibration temperature (using the mean temperature over
-	 * the "stillness" period).
-	 */
-	gyro_cal->bias_temperature_kelvin = gyro_cal->temperature_mean_kelvin;
-
-	/* Store the calibration time stamp. */
-	gyro_cal->calibration_time_us = calibration_time_us;
-
-	/* Record the final stillness confidence. */
-	gyro_cal->stillness_confidence = fp_mul(
-		gyro_cal->gyro_stillness_detect.prev_stillness_confidence,
-		gyro_cal->accel_stillness_detect.prev_stillness_confidence);
-	gyro_cal->stillness_confidence = fp_mul(
-		gyro_cal->stillness_confidence,
-		gyro_cal->mag_stillness_detect.prev_stillness_confidence);
-
-	/* Set flag to indicate a new gyro calibration value is available. */
-	gyro_cal->new_gyro_cal_available = true;
-}
-
-void check_window(struct gyro_cal *gyro_cal, uint32_t sample_time_us)
-{
-	bool window_timeout;
-
-	/* Check for initialization of the window time (=0). */
-	if (gyro_cal->gyro_window_start_us <= 0)
-		return;
-
-	/*
-	 * Checks for the following window timeout conditions:
-	 * i.  The current timestamp has exceeded the allowed window duration.
-	 * ii. A timestamp was received that has jumped backwards by more than
-	 *     the allowed window duration (e.g., timestamp clock roll-over).
-	 */
-	window_timeout =
-		(sample_time_us > gyro_cal->gyro_window_timeout_duration_us +
-					  gyro_cal->gyro_window_start_us) ||
-		(sample_time_us + gyro_cal->gyro_window_timeout_duration_us <
-		 gyro_cal->gyro_window_start_us);
-
-	/* If a timeout occurred then reset to known good state. */
-	if (window_timeout) {
-		/* Reset stillness detectors and restart data capture. */
-		gyro_still_det_reset(&gyro_cal->accel_stillness_detect,
-				     /*reset_stats=*/true);
-		gyro_still_det_reset(&gyro_cal->gyro_stillness_detect,
-				     /*reset_stats=*/true);
-		gyro_still_det_reset(&gyro_cal->mag_stillness_detect,
-				     /*reset_stats=*/true);
-
-		/* Resets the temperature and sensor mean data. */
-		gyro_temperature_stats_tracker_reset(gyro_cal);
-		gyro_still_mean_tracker_reset(gyro_cal);
-
-		/* Resets the stillness window end-time. */
-		gyro_cal->stillness_win_endtime_us = 0;
-
-		/* Force stillness confidence to zero. */
-		gyro_cal->accel_stillness_detect.prev_stillness_confidence = 0;
-		gyro_cal->gyro_stillness_detect.prev_stillness_confidence = 0;
-		gyro_cal->mag_stillness_detect.prev_stillness_confidence = 0;
-		gyro_cal->stillness_confidence = 0;
-		gyro_cal->prev_still = false;
-
-		/*
-		 * If there are no magnetometer samples being received then
-		 * operate the calibration algorithm without this sensor.
-		 */
-		if (!gyro_cal->mag_stillness_detect.stillness_window_ready &&
-		    gyro_cal->using_mag_sensor) {
-			gyro_cal->using_mag_sensor = false;
-		}
-
-		/* Assert window timeout flags. */
-		gyro_cal->gyro_window_start_us = 0;
-	}
-}
-
-void gyro_temperature_stats_tracker_reset(struct gyro_cal *gyro_cal)
-{
-	/* Resets the mean accumulator. */
-	gyro_cal->temperature_mean_tracker.num_points = 0;
-	gyro_cal->temperature_mean_tracker.mean_accumulator = INT_TO_FP(0);
-
-	/* Initializes the min/max temperatures values. */
-	gyro_cal->temperature_mean_tracker.temperature_min_kelvin = 0x7fff;
-	gyro_cal->temperature_mean_tracker.temperature_max_kelvin = 0xffff;
-}
-
-void gyro_temperature_stats_tracker_update(struct gyro_cal *gyro_cal,
-					   int temperature_kelvin)
-{
-	/* Does the mean accumulation. */
-	gyro_cal->temperature_mean_tracker.mean_accumulator +=
-		temperature_kelvin;
-	gyro_cal->temperature_mean_tracker.num_points++;
-
-	/* Tracks the min, max, and latest temperature values. */
-	gyro_cal->temperature_mean_tracker.latest_temperature_kelvin =
-		temperature_kelvin;
-	if (gyro_cal->temperature_mean_tracker.temperature_min_kelvin >
-	    temperature_kelvin) {
-		gyro_cal->temperature_mean_tracker.temperature_min_kelvin =
-			temperature_kelvin;
-	}
-	if (gyro_cal->temperature_mean_tracker.temperature_max_kelvin <
-	    temperature_kelvin) {
-		gyro_cal->temperature_mean_tracker.temperature_max_kelvin =
-			temperature_kelvin;
-	}
-}
-
-void gyro_temperature_stats_tracker_store(struct gyro_cal *gyro_cal)
-{
-	/*
-	 * Store the most recent temperature statistics data to the
-	 * gyro_cal data structure. This functionality allows previous
-	 * results to be recalled when the device suddenly becomes "not
-	 * still".
-	 */
-	if (gyro_cal->temperature_mean_tracker.num_points > 0)
-		gyro_cal->temperature_mean_kelvin =
-			gyro_cal->temperature_mean_tracker.mean_accumulator /
-			gyro_cal->temperature_mean_tracker.num_points;
-	else
-		gyro_cal->temperature_mean_kelvin =
-			gyro_cal->temperature_mean_tracker
-				.latest_temperature_kelvin;
-}
-
-bool gyro_temperature_stats_tracker_eval(struct gyro_cal *gyro_cal)
-{
-	bool min_max_temp_exceeded = false;
-
-	/* Determines if the min/max delta exceeded the set limit. */
-	if (gyro_cal->temperature_mean_tracker.num_points > 0) {
-		min_max_temp_exceeded =
-			(gyro_cal->temperature_mean_tracker
-				 .temperature_max_kelvin -
-			 gyro_cal->temperature_mean_tracker
-				 .temperature_min_kelvin) >
-			gyro_cal->temperature_delta_limit_kelvin;
-	}
-
-	return min_max_temp_exceeded;
-}
-
-void gyro_still_mean_tracker_reset(struct gyro_cal *gyro_cal)
-{
-	size_t i;
-
-	/* Resets the min/max window mean values to a default value. */
-	for (i = 0; i < 3; i++) {
-		gyro_cal->window_mean_tracker.gyro_winmean_min[i] = FLT_MAX;
-		gyro_cal->window_mean_tracker.gyro_winmean_max[i] = -FLT_MAX;
-	}
-}
-
-void gyro_still_mean_tracker_update(struct gyro_cal *gyro_cal)
-{
-	int i;
-
-	/* Computes the min/max window mean values. */
-	for (i = 0; i < 3; ++i) {
-		if (gyro_cal->window_mean_tracker.gyro_winmean_min[i] >
-		    gyro_cal->gyro_stillness_detect.win_mean[i]) {
-			gyro_cal->window_mean_tracker.gyro_winmean_min[i] =
-				gyro_cal->gyro_stillness_detect.win_mean[i];
-		}
-		if (gyro_cal->window_mean_tracker.gyro_winmean_max[i] <
-		    gyro_cal->gyro_stillness_detect.win_mean[i]) {
-			gyro_cal->window_mean_tracker.gyro_winmean_max[i] =
-				gyro_cal->gyro_stillness_detect.win_mean[i];
-		}
-	}
-}
-
-void gyro_still_mean_tracker_store(struct gyro_cal *gyro_cal)
-{
-	/*
-	 * Store the most recent "stillness" mean data to the gyro_cal
-	 * data structure. This functionality allows previous results to
-	 * be recalled when the device suddenly becomes "not still".
-	 */
-	memcpy(gyro_cal->gyro_winmean_min,
-	       gyro_cal->window_mean_tracker.gyro_winmean_min,
-	       sizeof(gyro_cal->window_mean_tracker.gyro_winmean_min));
-	memcpy(gyro_cal->gyro_winmean_max,
-	       gyro_cal->window_mean_tracker.gyro_winmean_max,
-	       sizeof(gyro_cal->window_mean_tracker.gyro_winmean_max));
-}
-
-bool gyro_still_mean_tracker_eval(struct gyro_cal *gyro_cal)
-{
-	bool mean_not_stable = false;
-	size_t i;
-
-	/*
-	 * Performs the stability check and returns the 'true' if the
-	 * difference between min/max window mean value is outside the
-	 * stable range.
-	 */
-	for (i = 0; i < 3 && !mean_not_stable; i++) {
-		mean_not_stable |=
-			(gyro_cal->window_mean_tracker.gyro_winmean_max[i] -
-			 gyro_cal->window_mean_tracker.gyro_winmean_min[i]) >
-			gyro_cal->stillness_mean_delta_limit;
-	}
-
-	return mean_not_stable;
-}
diff --git a/common/gyro_still_det.c b/common/gyro_still_det.c
deleted file mode 100644
index 4574e22e5f..0000000000
--- a/common/gyro_still_det.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gyro_still_det.h"
-#include "vec3.h"
-
-/* Enforces the limits of an input value [0,1]. */
-static fp_t gyro_still_det_limit(fp_t value);
-
-void gyro_still_det_update(struct gyro_still_det *gyro_still_det,
-			   uint32_t stillness_win_endtime, uint32_t sample_time,
-			   fp_t x, fp_t y, fp_t z)
-{
-	fp_t delta = INT_TO_FP(0);
-
-	/*
-	 * Using the method of the assumed mean to preserve some numerical
-	 * stability while avoiding per-sample divisions that the more
-	 * numerically stable Welford method would afford.
-	 *
-	 * Reference for the numerical method used below to compute the
-	 * online mean and variance statistics:
-	 *   1). en.wikipedia.org/wiki/assumed_mean
-	 */
-
-	/* Increment the number of samples. */
-	gyro_still_det->num_acc_samples++;
-
-	/* Online computation of mean for the running stillness period. */
-	gyro_still_det->mean[X] += x;
-	gyro_still_det->mean[Y] += y;
-	gyro_still_det->mean[Z] += z;
-
-	/* Is this the first sample of a new window? */
-	if (gyro_still_det->start_new_window) {
-		/* Record the window start time. */
-		gyro_still_det->window_start_time = sample_time;
-		gyro_still_det->start_new_window = false;
-
-		/* Update assumed mean values. */
-		gyro_still_det->assumed_mean[X] = x;
-		gyro_still_det->assumed_mean[Y] = y;
-		gyro_still_det->assumed_mean[Z] = z;
-
-		/* Reset current window mean and variance. */
-		gyro_still_det->num_acc_win_samples = 0;
-		gyro_still_det->win_mean[X] = INT_TO_FP(0);
-		gyro_still_det->win_mean[Y] = INT_TO_FP(0);
-		gyro_still_det->win_mean[Z] = INT_TO_FP(0);
-		gyro_still_det->acc_var[X] = INT_TO_FP(0);
-		gyro_still_det->acc_var[Y] = INT_TO_FP(0);
-		gyro_still_det->acc_var[Z] = INT_TO_FP(0);
-	} else {
-		/*
-		 * Check to see if we have enough samples to compute a stillness
-		 * confidence score.
-		 */
-		gyro_still_det->stillness_window_ready =
-			(sample_time >= stillness_win_endtime) &&
-			(gyro_still_det->num_acc_samples > 1);
-	}
-
-	/* Record the most recent sample time stamp. */
-	gyro_still_det->last_sample_time = sample_time;
-
-	/* Online window mean and variance ("one-pass" accumulation). */
-	gyro_still_det->num_acc_win_samples++;
-
-	delta = (x - gyro_still_det->assumed_mean[X]);
-	gyro_still_det->win_mean[X] += delta;
-	gyro_still_det->acc_var[X] += fp_sq(delta);
-
-	delta = (y - gyro_still_det->assumed_mean[Y]);
-	gyro_still_det->win_mean[Y] += delta;
-	gyro_still_det->acc_var[Y] += fp_sq(delta);
-
-	delta = (z - gyro_still_det->assumed_mean[Z]);
-	gyro_still_det->win_mean[Z] += delta;
-	gyro_still_det->acc_var[Z] += fp_sq(delta);
-}
-
-fp_t gyro_still_det_compute(struct gyro_still_det *gyro_still_det)
-{
-	fp_t tmp_denom = INT_TO_FP(1);
-	fp_t tmp_denom_mean = INT_TO_FP(1);
-	fp_t tmp;
-	fp_t upper_var_thresh, lower_var_thresh;
-
-	/* Don't divide by zero (not likely, but a precaution). */
-	if (gyro_still_det->num_acc_win_samples > 1) {
-		tmp_denom = fp_div(
-			tmp_denom,
-			INT_TO_FP(gyro_still_det->num_acc_win_samples - 1));
-		tmp_denom_mean =
-			fp_div(tmp_denom_mean,
-			       INT_TO_FP(gyro_still_det->num_acc_win_samples));
-	} else {
-		/* Return zero stillness confidence. */
-		gyro_still_det->stillness_confidence = 0;
-		return gyro_still_det->stillness_confidence;
-	}
-
-	/* Update the final calculation of window mean and variance. */
-	tmp = gyro_still_det->win_mean[X];
-	gyro_still_det->win_mean[X] =
-		fp_mul(gyro_still_det->win_mean[X], tmp_denom_mean);
-	gyro_still_det->win_var[X] =
-		fp_mul((gyro_still_det->acc_var[X] -
-			fp_mul(gyro_still_det->win_mean[X], tmp)),
-		       tmp_denom);
-
-	tmp = gyro_still_det->win_mean[Y];
-	gyro_still_det->win_mean[Y] =
-		fp_mul(gyro_still_det->win_mean[Y], tmp_denom_mean);
-	gyro_still_det->win_var[Y] =
-		fp_mul((gyro_still_det->acc_var[Y] -
-			fp_mul(gyro_still_det->win_mean[Y], tmp)),
-		       tmp_denom);
-
-	tmp = gyro_still_det->win_mean[Z];
-	gyro_still_det->win_mean[Z] =
-		fp_mul(gyro_still_det->win_mean[Z], tmp_denom_mean);
-	gyro_still_det->win_var[Z] =
-		fp_mul((gyro_still_det->acc_var[Z] -
-			fp_mul(gyro_still_det->win_mean[Z], tmp)),
-		       tmp_denom);
-
-	/* Adds the assumed mean value back to the total mean calculation. */
-	gyro_still_det->win_mean[X] += gyro_still_det->assumed_mean[X];
-	gyro_still_det->win_mean[Y] += gyro_still_det->assumed_mean[Y];
-	gyro_still_det->win_mean[Z] += gyro_still_det->assumed_mean[Z];
-
-	/* Define the variance thresholds. */
-	upper_var_thresh = gyro_still_det->var_threshold +
-			   gyro_still_det->confidence_delta;
-
-	lower_var_thresh = gyro_still_det->var_threshold -
-			   gyro_still_det->confidence_delta;
-
-	/* Compute the stillness confidence score. */
-	if ((gyro_still_det->win_var[X] > upper_var_thresh) ||
-	    (gyro_still_det->win_var[Y] > upper_var_thresh) ||
-	    (gyro_still_det->win_var[Z] > upper_var_thresh)) {
-		/*
-		 * Sensor variance exceeds the upper threshold (i.e., motion
-		 * detected). Set stillness confidence equal to 0.
-		 */
-		gyro_still_det->stillness_confidence = 0;
-	} else if ((gyro_still_det->win_var[X] <= lower_var_thresh) &&
-		   (gyro_still_det->win_var[Y] <= lower_var_thresh) &&
-		   (gyro_still_det->win_var[Z] <= lower_var_thresh)) {
-		/*
-		 * Sensor variance is below the lower threshold (i.e.
-		 * stillness detected).
-		 * Set stillness confidence equal to 1.
-		 */
-		gyro_still_det->stillness_confidence = INT_TO_FP(1);
-	} else {
-		/*
-		 * Motion detection thresholds not exceeded. Compute the
-		 * stillness confidence score.
-		 */
-		fp_t var_thresh = gyro_still_det->var_threshold;
-		fpv3_t limit;
-
-		/*
-		 * Compute the stillness confidence score.
-		 * Each axis score is limited [0,1].
-		 */
-		tmp_denom = fp_div(INT_TO_FP(1),
-				   (upper_var_thresh - lower_var_thresh));
-		limit[X] = gyro_still_det_limit(
-			FLOAT_TO_FP(0.5f) -
-			fp_mul(gyro_still_det->win_var[X] - var_thresh,
-			       tmp_denom));
-		limit[Y] = gyro_still_det_limit(
-			FLOAT_TO_FP(0.5f) -
-			fp_mul(gyro_still_det->win_var[Y] - var_thresh,
-			       tmp_denom));
-		limit[Z] = gyro_still_det_limit(
-			FLOAT_TO_FP(0.5f) -
-			fp_mul(gyro_still_det->win_var[Z] - var_thresh,
-			       tmp_denom));
-
-		gyro_still_det->stillness_confidence =
-			fp_mul(limit[X], fp_mul(limit[Y], limit[Z]));
-	}
-
-	/* Return the stillness confidence. */
-	return gyro_still_det->stillness_confidence;
-}
-
-void gyro_still_det_reset(struct gyro_still_det *gyro_still_det,
-			  bool reset_stats)
-{
-	fp_t tmp_denom = INT_TO_FP(1);
-
-	/* Reset the stillness data ready flag. */
-	gyro_still_det->stillness_window_ready = false;
-
-	/* Signal to start capture of next stillness data window. */
-	gyro_still_det->start_new_window = true;
-
-	/* Track the stillness confidence (current->previous). */
-	gyro_still_det->prev_stillness_confidence =
-		gyro_still_det->stillness_confidence;
-
-	/* Track changes in the mean estimate. */
-	if (gyro_still_det->num_acc_samples > INT_TO_FP(1))
-		tmp_denom =
-			fp_div(INT_TO_FP(1), gyro_still_det->num_acc_samples);
-
-	gyro_still_det->prev_mean[X] =
-		fp_mul(gyro_still_det->mean[X], tmp_denom);
-	gyro_still_det->prev_mean[Y] =
-		fp_mul(gyro_still_det->mean[Y], tmp_denom);
-	gyro_still_det->prev_mean[Z] =
-		fp_mul(gyro_still_det->mean[Z], tmp_denom);
-
-	/* Reset the current statistics to zero. */
-	if (reset_stats) {
-		gyro_still_det->num_acc_samples = 0;
-		gyro_still_det->mean[X] = INT_TO_FP(0);
-		gyro_still_det->mean[Y] = INT_TO_FP(0);
-		gyro_still_det->mean[Z] = INT_TO_FP(0);
-		gyro_still_det->acc_var[X] = INT_TO_FP(0);
-		gyro_still_det->acc_var[Y] = INT_TO_FP(0);
-		gyro_still_det->acc_var[Z] = INT_TO_FP(0);
-	}
-}
-
-fp_t gyro_still_det_limit(fp_t value)
-{
-	if (value < INT_TO_FP(0))
-		value = INT_TO_FP(0);
-	else if (value > INT_TO_FP(1))
-		value = INT_TO_FP(1);
-
-	return value;
-}
diff --git a/common/host_command_controller.c b/common/host_command_controller.c
deleted file mode 100644
index 0d221e44e3..0000000000
--- a/common/host_command_controller.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Host command controller module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-
-/* Number of attempts for each PD host command */
-#define PD_HOST_COMMAND_ATTEMPTS 3
-
-static struct mutex pd_mutex;
-
-/**
- * Non-task-safe internal version of pd_host_command().
- *
- * Do not call this version directly!  Use pd_host_command().
- */
-static int pd_host_command_internal(int command, int version,
-				    const void *outdata, int outsize,
-				    void *indata, int insize)
-{
-	int ret, i;
-	int resp_len;
-	struct ec_host_request rq;
-	struct ec_host_response rs;
-	static uint8_t req_buf[EC_LPC_HOST_PACKET_SIZE];
-	static uint8_t resp_buf[EC_LPC_HOST_PACKET_SIZE];
-	uint8_t sum = 0;
-	const uint8_t *c;
-	uint8_t *d;
-
-	/* Fail if output size is too big */
-	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
-		return -EC_RES_REQUEST_TRUNCATED;
-
-	/* Fill in request packet */
-	rq.struct_version = EC_HOST_REQUEST_VERSION;
-	rq.checksum = 0;
-	rq.command = command;
-	rq.command_version = version;
-	rq.reserved = 0;
-	rq.data_len = outsize;
-
-	/* Copy data and start checksum */
-	for (i = 0, c = (const uint8_t *)outdata; i < outsize; i++, c++) {
-		req_buf[sizeof(rq) + 1 + i] = *c;
-		sum += *c;
-	}
-
-	/* Finish checksum */
-	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
-		sum += *c;
-
-	/* Write checksum field so the entire packet sums to 0 */
-	rq.checksum = (uint8_t)(-sum);
-
-	/* Copy header */
-	for (i = 0, c = (const uint8_t *)&rq; i < sizeof(rq); i++, c++)
-		req_buf[1 + i] = *c;
-
-	/* Set command to use protocol v3 */
-	req_buf[0] = EC_COMMAND_PROTOCOL_3;
-
-	/*
-	 * Transmit all data and receive 2 bytes for return value and response
-	 * length.
-	 */
-	i2c_lock(I2C_PORT_PD_MCU, 1);
-	i2c_set_timeout(I2C_PORT_PD_MCU, PD_HOST_COMMAND_TIMEOUT_US);
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_ADDR_FLAGS,
-				&req_buf[0], outsize + sizeof(rq) + 1,
-				&resp_buf[0], 2, I2C_XFER_START);
-	i2c_set_timeout(I2C_PORT_PD_MCU, 0);
-	if (ret) {
-		i2c_lock(I2C_PORT_PD_MCU, 0);
-		CPRINTS("i2c transaction 1 failed: %d", ret);
-		return -EC_RES_BUS_ERROR;
-	}
-
-	resp_len = resp_buf[1];
-
-	if (resp_len > (insize + sizeof(rs))) {
-		/* Do a read to generate stop condition */
-		i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				  CONFIG_USB_PD_I2C_ADDR_FLAGS,
-				  0, 0, &resp_buf[2], 1, I2C_XFER_STOP);
-		i2c_lock(I2C_PORT_PD_MCU, 0);
-		CPRINTS("response size is too large %d > %d",
-			resp_len, insize + sizeof(rs));
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Receive remaining data */
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_ADDR_FLAGS,
-				0, 0,
-				&resp_buf[2], resp_len, I2C_XFER_STOP);
-	i2c_lock(I2C_PORT_PD_MCU, 0);
-	if (ret) {
-		CPRINTS("i2c transaction 2 failed: %d", ret);
-		return -EC_RES_BUS_ERROR;
-	}
-
-	/* Check for host command error code */
-	ret = resp_buf[0];
-	if (ret) {
-		CPRINTS("command 0x%02x returned error %d", command, ret);
-		return -ret;
-	}
-
-	/* Read back response header and start checksum */
-	sum = 0;
-	for (i = 0, d = (uint8_t *)&rs; i < sizeof(rs); i++, d++) {
-		*d = resp_buf[i + 2];
-		sum += *d;
-	}
-
-	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
-		CPRINTS("PD response version mismatch");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.reserved) {
-		CPRINTS("PD response reserved != 0");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.data_len > insize) {
-		CPRINTS("PD returned too much data");
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Read back data and update checksum */
-	resp_len -= sizeof(rs);
-	for (i = 0, d = (uint8_t *)indata; i < resp_len; i++, d++) {
-		*d = resp_buf[sizeof(rs) + i + 2];
-		sum += *d;
-	}
-
-
-	if ((uint8_t)sum) {
-		CPRINTS("command 0x%02x bad checksum returned: %d",
-			command, sum);
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return output buffer size */
-	return resp_len;
-}
-
-int pd_host_command(int command, int version,
-		    const void *outdata, int outsize,
-		    void *indata, int insize)
-{
-	int rv;
-	int tries = 0;
-
-	/* Try multiple times to send host command. */
-	for (tries = 0; tries < PD_HOST_COMMAND_ATTEMPTS; tries++) {
-		/* Acquire mutex */
-		mutex_lock(&pd_mutex);
-		/* Call internal version of host command */
-		rv = pd_host_command_internal(command, version, outdata,
-					      outsize, indata, insize);
-		/* Release mutex */
-		mutex_unlock(&pd_mutex);
-
-		/* If host command error due to i2c bus error, try again. */
-		if (rv != -EC_RES_BUS_ERROR)
-			break;
-		task_wait_event(50*MSEC);
-	}
-
-	return rv;
-}
-
-static int command_pd_mcu(int argc, char **argv)
-{
-	char *e;
-	static char __bss_slow outbuf[128];
-	static char __bss_slow inbuf[128];
-	int command, version;
-	int i, ret, tmp;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	version = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	for (i = 3; i < argc; i++) {
-		tmp = strtoi(argv[i], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-		outbuf[i-3] = tmp;
-	}
-
-	ret = pd_host_command(command, version, &outbuf, argc - 3, &inbuf,
-			sizeof(inbuf));
-
-	ccprintf("Host command 0x%02x, returned %d\n", command, ret);
-	for (i = 0; i < ret; i++)
-		ccprintf("0x%02x\n", inbuf[i]);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu,
-			"cmd ver [params]",
-			"Send PD host command");
-
diff --git a/common/host_command_pd.c b/common/host_command_pd.c
deleted file mode 100644
index f9b67c8b8d..0000000000
--- a/common/host_command_pd.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Host command module for PD MCU */
-
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "lightbar.h"
-#include "panic.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ## args)
-
-#define TASK_EVENT_EXCHANGE_PD_STATUS  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_HIBERNATING         TASK_EVENT_CUSTOM_BIT(1)
-
-/* Define local option for if we are a TCPM with an off chip TCPC */
-#if defined(CONFIG_USB_POWER_DELIVERY) && !defined(CONFIG_USB_PD_TCPM_STUB)
-#define USB_TCPM_WITH_OFF_CHIP_TCPC
-#endif
-
-#ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-/* By default allow 5V charging only for the dead battery case */
-static enum pd_charge_state charge_state = PD_CHARGE_5V;
-
-#define CHARGE_PORT_UNINITIALIZED -2
-static int charge_port = CHARGE_PORT_UNINITIALIZED;
-
-int pd_get_active_charge_port(void)
-{
-	return charge_port;
-}
-#endif /* CONFIG_HOSTCMD_PD_CHG_CTRL */
-
-void host_command_pd_send_status(enum pd_charge_state new_chg_state)
-{
-#ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-	/* Update PD MCU charge state if necessary */
-	if (new_chg_state != PD_CHARGE_NO_CHANGE)
-		charge_state = new_chg_state;
-#endif
-	/* Wake PD HC task to send status */
-	task_set_event(TASK_ID_PDCMD, TASK_EVENT_EXCHANGE_PD_STATUS);
-}
-
-void host_command_pd_request_hibernate(void)
-{
-	task_set_event(TASK_ID_PDCMD, TASK_EVENT_HIBERNATING);
-}
-
-#ifdef CONFIG_HOSTCMD_PD
-static int pd_send_host_command(struct ec_params_pd_status *ec_status,
-	struct ec_response_pd_status *pd_status)
-{
-	return pd_host_command(EC_CMD_PD_EXCHANGE_STATUS,
-			       EC_VER_PD_EXCHANGE_STATUS, ec_status,
-			       sizeof(struct ec_params_pd_status), pd_status,
-			       sizeof(struct ec_response_pd_status));
-}
-
-static void pd_exchange_update_ec_status(struct ec_params_pd_status *ec_status,
-					 uint32_t ec_state)
-{
-	/* Send PD charge state and battery state of charge */
-#ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-	ec_status->charge_state = charge_state;
-#endif
-	if (charge_get_flags() & CHARGE_FLAG_BATT_RESPONSIVE)
-		ec_status->batt_soc = charge_get_percent();
-	else
-		ec_status->batt_soc = -1;
-	ec_status->status = ec_state;
-}
-
-#ifdef CONFIG_HOSTCMD_PD_PANIC
-static void pd_check_panic(struct ec_response_pd_status *pd_status)
-{
-	static int pd_in_rw;
-
-	/*
-	 * Check if PD MCU is in RW. If PD MCU was in RW, is now in RO,
-	 * AND it did not sysjump to RO, then it must have crashed, and
-	 * therefore we should panic as well.
-	 */
-	if (pd_status->status & PD_STATUS_IN_RW) {
-		pd_in_rw = 1;
-	} else if (pd_in_rw &&
-		   !(pd_status->status & PD_STATUS_JUMPED_TO_IMAGE)) {
-		panic_printf("PD crash");
-		software_panic(PANIC_SW_PD_CRASH, 0);
-	}
-}
-#endif /* CONFIG_HOSTCMD_PD_PANIC */
-
-#ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-static void pd_check_chg_status(struct ec_response_pd_status *pd_status)
-{
-	int rv;
-#ifdef HAS_TASK_LIGHTBAR
-	/*
-	 * If charge port has changed, and it was initialized, then show
-	 * battery status on lightbar.
-	 */
-	if (pd_status->active_charge_port != charge_port) {
-		if (charge_port != CHARGE_PORT_UNINITIALIZED) {
-			charge_port = pd_status->active_charge_port;
-			lightbar_sequence(LIGHTBAR_TAP);
-		} else {
-			charge_port = pd_status->active_charge_port;
-		}
-	}
-#else
-	/* Store the active charge port */
-	charge_port = pd_status->active_charge_port;
-#endif
-
-	/* Set input current limit */
-	rv = charge_set_input_current_limit(MAX(pd_status->curr_lim_ma,
-					CONFIG_CHARGER_INPUT_CURRENT), 0);
-	if (rv < 0)
-		CPRINTS("Failed to set input curr limit from PD MCU");
-}
-#endif /* CONFIG_HOSTCMD_PD_CHG_CTRL */
-#endif /* CONFIG_HOSTCMD_PD */
-
-#ifdef USB_TCPM_WITH_OFF_CHIP_TCPC
-static void pd_service_tcpc_ports(uint16_t port_status)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if ((port_status & (PD_STATUS_TCPC_ALERT_0 << i)) &&
-		    pd_is_port_enabled(i))
-			tcpc_alert(i);
-	}
-}
-
-static int pd_get_alert(void)
-{
-#ifdef CONFIG_HOSTCMD_PD
-	return !gpio_get_level(GPIO_PD_MCU_INT);
-#else
-	return !!tcpc_get_alert_status();
-#endif
-}
-
-#endif /* USB_TCPM_WITH_OFF_CHIP_TCPC */
-
-static void pd_exchange_status(uint32_t ec_state)
-{
-#ifdef USB_TCPM_WITH_OFF_CHIP_TCPC
-	int first_exchange = 1;
-#endif
-
-#ifdef CONFIG_HOSTCMD_PD
-	struct ec_params_pd_status ec_status;
-	struct ec_response_pd_status pd_status;
-	int rv;
-
-	pd_exchange_update_ec_status(&ec_status, ec_state);
-#endif
-
-#ifdef USB_TCPM_WITH_OFF_CHIP_TCPC
-	/* Loop until the alert gpio is not active */
-	do {
-#endif
-
-#ifdef CONFIG_HOSTCMD_PD
-		rv = pd_send_host_command(&ec_status, &pd_status);
-		if (rv < 0) {
-			CPRINTS("Host command to PD MCU failed: %d", rv);
-			return;
-		}
-
-#ifdef CONFIG_HOSTCMD_PD_PANIC
-		pd_check_panic(&pd_status);
-#endif
-
-#ifdef CONFIG_HOSTCMD_PD_CHG_CTRL
-		pd_check_chg_status(&pd_status);
-#endif
-#endif /* CONFIG_HOSTCMD_PD */
-
-#ifdef USB_TCPM_WITH_OFF_CHIP_TCPC
-#ifdef CONFIG_HOSTCMD_PD
-		pd_service_tcpc_ports(pd_status.status);
-#else
-		pd_service_tcpc_ports(tcpc_get_alert_status());
-#endif
-
-		if (!first_exchange)
-			/* Delay to prevent task starvation */
-			usleep(5*MSEC);
-		first_exchange = 0;
-	} while (pd_get_alert());
-#endif /* USB_TCPM_WITH_OFF_CHIP_TCPC */
-}
-
-void pd_command_task(void *u)
-{
-	/* On startup exchange status with the PD */
-	pd_exchange_status(0);
-
-	while (1) {
-		/* Wait for the next command event */
-		int evt = task_wait_event(-1);
-		uint32_t ec_state = 0;
-
-		if (evt & TASK_EVENT_HIBERNATING)
-			ec_state = EC_STATUS_HIBERNATING;
-
-		/* Process event to send status to PD */
-		if ((evt & TASK_EVENT_EXCHANGE_PD_STATUS) ||
-		    (evt & TASK_EVENT_HIBERNATING))
-			pd_exchange_status(ec_state);
-	}
-}
-
diff --git a/common/hotword_dsp_api.c b/common/hotword_dsp_api.c
deleted file mode 100644
index dc53cd0055..0000000000
--- a/common/hotword_dsp_api.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "audio_codec.h"
-#include "hotword_dsp_api.h"
-
-const int kGoogleHotwordRequiredDataAlignment = 4;
-
-int GoogleHotwordDspInit(void *hotword_memmap)
-{
-	return 1;
-}
-
-int GoogleHotwordDspProcess(const void *samples, int num_samples,
-			    int *preamble_length_ms)
-{
-	return 0;
-}
-
-void GoogleHotwordDspReset(void)
-{
-}
-
-int GoogleHotwordDspGetMaximumAudioPreambleMs(void)
-{
-	return 0;
-}
-
-int GoogleHotwordVersion(void)
-{
-	return 0;
-}
diff --git a/common/i2c_bitbang.c b/common/i2c_bitbang.c
deleted file mode 100644
index 86d76a8b47..0000000000
--- a/common/i2c_bitbang.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "gpio.h"
-#include "i2c_bitbang.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(str) cputs(CC_I2C, str)
-
-static int started;
-
-/* TODO: respect i2c_port->kbps setting */
-static void i2c_delay(void)
-{
-	udelay(5);
-}
-
-/* Number of attempts to unwedge each pin. */
-#define UNWEDGE_SCL_ATTEMPTS  10
-#define UNWEDGE_SDA_ATTEMPTS  3
-
-static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
-{
-	int i, j;
-
-	gpio_set_level(i2c_port->scl, 1);
-	/*
-	 * If clock is low, wait for a while in case of clock stretched
-	 * by a peripheral.
-	 */
-	if (!gpio_get_level(i2c_port->scl)) {
-		for (i = 0;; i++) {
-			if (i >= UNWEDGE_SCL_ATTEMPTS) {
-				/*
-				 * If we get here, a peripheral is holding the
-				 * clock low and there is nothing we can do.
-				 */
-				CPUTS("I2C unwedge failed, SCL is held low\n");
-				return;
-			}
-			i2c_delay();
-			if (gpio_get_level(i2c_port->scl))
-				break;
-		}
-	}
-
-	if (gpio_get_level(i2c_port->sda))
-		return;
-
-	CPUTS("I2C unwedge called with SDA held low\n");
-
-	/* Keep trying to unwedge the SDA line until we run out of attempts. */
-	for (i = 0; i < UNWEDGE_SDA_ATTEMPTS; i++) {
-		/* Drive the clock high. */
-		gpio_set_level(i2c_port->scl, 0);
-		i2c_delay();
-
-		/*
-		 * Clock through the problem by clocking out 9 bits. If
-		 * peripheral releases the SDA line, then we can stop clocking
-		 * bits and send a STOP.
-		 */
-		for (j = 0; j < 9; j++) {
-			if (gpio_get_level(i2c_port->sda))
-				break;
-
-			gpio_set_level(i2c_port->scl, 0);
-			i2c_delay();
-			gpio_set_level(i2c_port->scl, 1);
-			i2c_delay();
-		}
-
-		/* Take control of SDA line and issue a STOP command. */
-		gpio_set_level(i2c_port->sda, 0);
-		i2c_delay();
-		gpio_set_level(i2c_port->sda, 1);
-		i2c_delay();
-
-		/* Check if the bus is unwedged. */
-		if (gpio_get_level(i2c_port->sda) &&
-				gpio_get_level(i2c_port->scl))
-			break;
-	}
-
-	if (!gpio_get_level(i2c_port->sda))
-		CPUTS("I2C unwedge failed, SDA still low\n");
-	if (!gpio_get_level(i2c_port->scl))
-		CPUTS("I2C unwedge failed, SCL still low\n");
-}
-
-static void i2c_stop_cond(const struct i2c_port_t *i2c_port)
-{
-	int i;
-
-	if (!started)
-		return;
-
-	gpio_set_level(i2c_port->sda, 0);
-	i2c_delay();
-
-	gpio_set_level(i2c_port->scl, 1);
-
-	/*
-	 * SMBus 3.0, 4.2.5
-	 *
-	 *  the recommendation is that if SMBDAT is still low tTIMEOUT,MAX after
-	 *  SMBCLK has gone high at the end of a transaction the controller
-	 *  should hold SMBCLK low for at least tTIMEOUT,MAX in an attempt to
-	 *  reset the SMBus interface of all of the devices on the bus.
-	 */
-	for (i = 0; i < 7000; i++) {
-		if (gpio_get_level(i2c_port->scl))
-			break;
-		i2c_delay();
-	}
-	i2c_delay();
-
-	/* SCL is high, set SDA from 0 to 1 */
-	gpio_set_level(i2c_port->sda, 1);
-	i2c_delay();
-
-	started = 0;
-}
-
-static int clock_stretching(const struct i2c_port_t *i2c_port)
-{
-	int i;
-
-	i2c_delay();
-	/* 5us * 7000 iterations ~= 35ms */
-	for (i = 0; i < 7000; i++) {
-		if (gpio_get_level(i2c_port->scl))
-			return 0;
-		i2c_delay();
-	}
-
-	/*
-	 * SMBus 3.0, Note 3
-	 * Devices participating in a transfer can abort the transfer in
-	 * progress and release the bus when any single clock low interval
-	 * exceeds the value of tTIMEOUT,MIN(=25ms).
-	 * After the controller in a transaction detects this condition, it must
-	 * generate a stop condition within or after the current data byte in
-	 * the transfer process.
-	 */
-	i2c_stop_cond(i2c_port);
-	CPUTS("clock low timeout\n");
-
-	return EC_ERROR_TIMEOUT;
-}
-
-static int i2c_start_cond(const struct i2c_port_t *i2c_port)
-{
-	int err;
-
-	if (started) {
-		gpio_set_level(i2c_port->sda, 1);
-		i2c_delay();
-
-		gpio_set_level(i2c_port->scl, 1);
-		err = clock_stretching(i2c_port);
-		if (err)
-			return err;
-		i2c_delay();
-
-		if (gpio_get_level(i2c_port->sda) == 0) {
-			CPUTS("start_cond: arbitration lost\n");
-			started = 0;
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	/* check if bus is idle before starting */
-	if (gpio_get_level(i2c_port->scl) == 0 ||
-	    gpio_get_level(i2c_port->sda) == 0)
-		return EC_ERROR_UNKNOWN;
-
-	gpio_set_level(i2c_port->sda, 0);
-	i2c_delay();
-
-	gpio_set_level(i2c_port->scl, 0);
-	started = 1;
-
-	return 0;
-}
-
-static int i2c_write_bit(const struct i2c_port_t *i2c_port, int bit)
-{
-	int err;
-
-	gpio_set_level(i2c_port->sda, !!bit);
-	i2c_delay();
-
-	gpio_set_level(i2c_port->scl, 1);
-	err = clock_stretching(i2c_port);
-	if (err)
-		return err;
-	i2c_delay();
-
-	if (bit && gpio_get_level(i2c_port->sda) == 0) {
-		CPUTS("write_bit: arbitration lost\n");
-		started = 0;
-		return EC_ERROR_UNKNOWN;
-	}
-
-	gpio_set_level(i2c_port->scl, 0);
-
-	return 0;
-}
-
-static int i2c_read_bit(const struct i2c_port_t *i2c_port, int *bit)
-{
-	int err;
-
-	gpio_set_level(i2c_port->sda, 1);
-	i2c_delay();
-
-	gpio_set_level(i2c_port->scl, 1);
-	err = clock_stretching(i2c_port);
-	if (err)
-		return err;
-	i2c_delay();
-	*bit = gpio_get_level(i2c_port->sda);
-
-	gpio_set_level(i2c_port->scl, 0);
-
-	return 0;
-}
-
-static int i2c_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte)
-{
-	int i, nack, err;
-
-	for (i = 7; i >= 0; i--) {
-		err = i2c_write_bit(i2c_port, byte & (1 << i));
-		if (err)
-			return err;
-	}
-
-	err = i2c_read_bit(i2c_port, &nack);
-	if (err)
-		return err;
-
-	if (nack) {
-		/*
-		 * The peripheral device detects an invalid command or invalid
-		 * data. In this case the peripheral device must NACK the
-		 * received byte. The controller upon detection of this
-		 * condition must generate a STOP condition and retry the
-		 * transaction
-		 */
-		i2c_stop_cond(i2c_port);
-		/* return EC_ERROR_BUSY to indicate i2c_xfer() to retry */
-		return EC_ERROR_BUSY;
-	}
-	return 0;
-}
-
-static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte,
-		int nack)
-{
-	int i;
-
-	*byte = 0;
-	for (i = 0; i < 8; i++) {
-		int bit = 0, err;
-
-		err = i2c_read_bit(i2c_port, &bit);
-		if (err)
-			return err;
-		*byte = (*byte << 1) | bit;
-	}
-
-	return i2c_write_bit(i2c_port, nack);
-}
-
-static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
-		const uint16_t addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
-{
-	uint16_t addr_8bit = addr_flags << 1, err = EC_SUCCESS;
-	int i = 0;
-
-	if (i2c_port->kbps != 100)
-		CPUTS("warning: bitbang driver only supports 100kbps\n");
-
-	if (out_size) {
-		if (flags & I2C_XFER_START) {
-			err = i2c_start_cond(i2c_port);
-			if (err)
-				goto exit;
-			err = i2c_write_byte(i2c_port, addr_8bit);
-			if (err)
-				goto exit;
-		}
-
-		for (i = 0; i < out_size; i++) {
-			err = i2c_write_byte(i2c_port, out[i]);
-			if (err)
-				goto exit;
-		}
-	}
-
-	if (in_size) {
-		if (flags & I2C_XFER_START) {
-			err = i2c_start_cond(i2c_port);
-			if (err)
-				goto exit;
-			err = i2c_write_byte(i2c_port, addr_8bit | 1);
-			if (err)
-				goto exit;
-		}
-
-		for (i = 0; i < in_size; i++) {
-			err = i2c_read_byte(i2c_port, &in[i],
-				(flags & I2C_XFER_STOP) && (i == in_size - 1));
-			if (err)
-				goto exit;
-		}
-	}
-
-	if (flags & I2C_XFER_STOP)
-		i2c_stop_cond(i2c_port);
-
-exit:
-	if (err) {
-		i2c_bitbang_unwedge(i2c_port);
-		started = 0;
-	}
-	return err;
-}
-
-const struct i2c_drv bitbang_drv = {
-	.xfer = &i2c_bitbang_xfer
-};
-
-#ifdef TEST_BUILD
-int bitbang_start_cond(const struct i2c_port_t *i2c_port)
-{
-	return i2c_start_cond(i2c_port);
-}
-
-void bitbang_stop_cond(const struct i2c_port_t *i2c_port)
-{
-	i2c_stop_cond(i2c_port);
-}
-
-int bitbang_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte)
-{
-	return i2c_write_byte(i2c_port, byte);
-}
-
-void bitbang_set_started(int val)
-{
-	started = val;
-}
-#endif
diff --git a/common/i2c_hid_touchpad.c b/common/i2c_hid_touchpad.c
deleted file mode 100644
index 29122f83d6..0000000000
--- a/common/i2c_hid_touchpad.c
+++ /dev/null
@@ -1,797 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c_hid_touchpad.h"
-
-#include "console.h"
-#include "hwtimer.h"
-#include "util.h"
-
-/* 2 bytes for length + 1 byte for report ID */
-#define I2C_HID_HEADER_SIZE			3
-
-/* Report ID */
-#define REPORT_ID_TOUCH				0x01
-#define REPORT_ID_MOUSE				0x02
-#define REPORT_ID_DEVICE_CAPS			0x0A
-#define REPORT_ID_DEVICE_CERT			0x0B
-#define REPORT_ID_INPUT_MODE			0x0C
-#define REPORT_ID_REPORTING			0x0D
-
-#define INPUT_MODE_MOUSE			0x00
-#define INPUT_MODE_TOUCH			0x03
-
-/* VID/PID/FW version */
-#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) || \
-    !defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \
-    !defined(I2C_HID_TOUCHPAD_FW_VERSION)
-#error "Must define touchpad VID/PID/FW version"
-#endif
-/*
- * Touchpad properties
- *
- * Physical dimensions are in the unit of mms.
- */
-#if !defined(I2C_HID_TOUCHPAD_MAX_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_Y) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y)
-#error "Must define finger maximum X/Y and physical dimensions"
-#endif
-/*
- * Maximum width/height of the contact (i.e., touch major/minor in Linux MT-B)
- *
- * According to the Linux's MT protocol, the max value of touch major/minor
- * should be sqrt(X^2+Y^2). However, this is rarely implemented by touchpads
- * in practice. Touchpads often output major/minor in custom units with very
- * different data ranges. It is therefore recommended for the user to check the
- * device's spec and set these values manually.
- */
-#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PRESSURE)
-#error "Must define finger maximum width/height/pressure"
-#endif
-/*
- * The touchpad is expected to provide at least the horizontal/vertical status
- * for each contact (if one is wider than its height). This can be computed
- * simply as bool(WIDTH>HEIGHT).
- */
-#ifndef I2C_HID_TOUCHPAD_MAX_ORIENTATION
-#error "Must define finger maximum orientation value"
-#endif
-/*
- * Conversion factor between the finger movement and the mouse cursor movement.
- * This is a bit similar to the mouse CPI and is used by mouse reports only.
- */
-#if !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_X) || \
-    !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y)
-#error "Must define mouse horizontal/vertical scaling factors"
-#endif
-
-/* Helper bit-op macros */
-#define N_BITS(n) \
-( \
-		(n) < (1 << 1) ? 1 : \
-		(n) < (1 << 2) ? 2 : \
-		(n) < (1 << 3) ? 3 : \
-		(n) < (1 << 4) ? 4 : \
-		(n) < (1 << 5) ? 5 : \
-		(n) < (1 << 6) ? 6 : \
-		(n) < (1 << 7) ? 7 : \
-		(n) < (1 << 8) ? 8 : \
-		(n) < (1 << 9) ? 9 : \
-		(n) < (1 << 10) ? 10 : \
-		(n) < (1 << 11) ? 11 : \
-		(n) < (1 << 12) ? 12 : \
-		(n) < (1 << 13) ? 13 : \
-		(n) < (1 << 14) ? 14 : \
-		(n) < (1 << 15) ? 15 : \
-		16 \
-)
-/* We would need to pad some bits at the end of each finger struct to match
- * the allocation unit's boundary so the array indexing may work correctly.
- */
-#define N_VAR_BITS \
-( \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_X) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) \
-)
-#define N_PADDING_BITS ((DIV_ROUND_UP(N_VAR_BITS, 8) * 8) - N_VAR_BITS)
-#define N_BITS_ORIENTATION \
-	(N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) + N_PADDING_BITS)
-/* Structs for holding input report data
- *
- * These need to be modified in correspondence with the HID input report
- * descriptor below.
- *
- * The HID usage names differ from the Evdev event names in some cases. For
- * example, touch major/minor are put under width/height and orientation is
- * called azimuth.
- */
-struct finger {
-	/*
-	 * Whether a finger is intentional or not. This could be used to
-	 * identify unintended contacts or palms but is up to the OS
-	 * explanation.
-	 */
-	uint8_t confidence:1;
-	/*
-	 * Whether a finger is touching the surface (leaving/left finger gets
-	 * 0).
-	 */
-	uint8_t tip:1;
-	/*
-	 * Whether a finger is within the sensor range. For example, hovering
-	 * fingers would have tip=0 and inrange=1.
-	 */
-	uint8_t inrange:1;
-	/*
-	 * Contact id. This is like slot numbers in Linux MT-B.
-	 */
-	uint8_t id:5;
-	uint16_t x:N_BITS(I2C_HID_TOUCHPAD_MAX_X);
-	uint16_t y:N_BITS(I2C_HID_TOUCHPAD_MAX_Y);
-	uint16_t width:N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH);
-	uint16_t height:N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT);
-	uint16_t pressure:N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE);
-	uint16_t orientation:N_BITS_ORIENTATION;
-} __packed;
-
-struct touch_report {
-	uint8_t button:1;
-	uint8_t count:7;
-	uint16_t timestamp;
-	struct finger finger[I2C_HID_TOUCHPAD_MAX_FINGERS];
-} __packed;
-
-struct mouse_report {
-	uint8_t button1:1;
-	/* Windows expects at least two button usages in a mouse report. Many
-	 * touchpads on the Chromebook are a single clickable surface, so
-	 * button2 isn't used. That said, we may later report a button2 event if
-	 * necessary.
-	 */
-	uint8_t button2:1;
-	uint8_t unused:6;
-	int8_t x;
-	int8_t y;
-} __packed;
-
-/* HID input report descriptor
- *
- * For a complete reference, please see the following docs on usb.org
- *
- * 1. Device Class Definition for HID
- * 2. HID Usage Tables
- */
-static const uint8_t report_desc[] = {
-	/* Mouse Collection */
-	0x05, 0x01,			/* Usage Page (Generic Desktop) */
-	0x09, 0x02,			/* Usage (Mouse) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_MOUSE,		/* Report ID (Mouse) */
-	0x09, 0x01,			/*   Usage (Pointer) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x05, 0x09,			/*     Usage Page (Button) */
-	0x19, 0x01,			/*     Usage Minimum (Button 1) */
-	0x29, 0x02,			/*     Usage Maximum (Button 2) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0x75, 0x01,			/*     Report Size (1) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */
-	0x95, 0x06,			/*     Report Count (6) */
-	0x81, 0x03,			/*     Input (Cnst,Var,Abs) */
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */
-	0x09, 0x30,			/*     Usage (X) */
-	0x09, 0x31,			/*     Usage (Y) */
-	0x15, 0x81,			/*     Logical Minimum (-127) */
-	0x25, 0x7F,			/*     Logical Maximum (127) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x06,			/*     Input (Data,Var,Rel) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
-
-	/* Touchpad Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x05,			/* Usage (Touch Pad) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_TOUCH,		/*   Report ID (Touch) */
-
-	/* Button */
-	0x05, 0x09,			/*   Usage Page (Button) */
-	0x19, 0x01,			/*   Usage Minimum (0x01) */
-	0x29, 0x01,			/*   Usage Maximum (0x01) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x25, 0x01,			/*   Logical Maximum (1) */
-	0x75, 0x01,			/*   Report Size (1) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
-
-	/* Contact count */
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x09, 0x54,			/*   Usage (Contact count) */
-	0x25, I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Logical Max. (MAX_FINGERS) */
-	0x75, 0x07,			/*   Report Size (7) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
-
-	/* Scan time */
-	0x55, 0x0C,			/*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,		/*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,	/*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,	/*   Logical Maximum (65535) */
-	0x75, 0x10,			/*   Report Size (16) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x05, 0x0D,			/*   Usage Page (Digitizers) */
-	0x09, 0x56,			/*   Usage (Scan Time) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
-
-#define FINGER(FINGER_NUMBER)						       \
-	/* Finger FINGER_NUMBER */					       \
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */         \
-	0x09, 0x22,			/*   Usage (Finger) */                 \
-	0xA1, 0x02,			/*   Collection (Logical) */           \
-	0x09, 0x47,			/*     Usage (Confidence) */           \
-	0x09, 0x42,			/*     Usage (Tip Switch) */           \
-	0x09, 0x32,			/*     Usage (In Range) */             \
-	0x15, 0x00,			/*     Logical Minimum (0) */          \
-	0x25, 0x01,			/*     Logical Maximum (1) */          \
-	0x75, 0x01,			/*     Report Size (1) */              \
-	0x95, 0x03,			/*     Report Count (3) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x51,			/*     Usage (Contact identifier) */   \
-	0x25, 0x1F,			/*     Logical Maximum (31) */         \
-	0x75, 0x05,			/*     Report Size (5) */              \
-	0x95, 0x01,			/*     Report Count (1) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */ \
-	0x09, 0x30,			/*     Usage (X) */                    \
-	0x55, 0x0E,			/*     Unit Exponent (-2) */           \
-	0x65, 0x11,			/*     Unit (SI Linear, Length: cm) */ \
-	0x35, 0x00,			/*     Physical Minimum (0) */         \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_X>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_X&0xff, I2C_HID_TOUCHPAD_MAX_X>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x31,			/*     Usage (Y) */                    \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_Y&0xff, I2C_HID_TOUCHPAD_MAX_Y>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x0D,			/*     Usage Page (Digitizer) */       \
-	0x09, 0x48,			/*     Usage (Width) */                \
-	0x26, I2C_HID_TOUCHPAD_MAX_WIDTH&0xff, I2C_HID_TOUCHPAD_MAX_WIDTH>>8,  \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x49,			/*     Usage (Height) */               \
-	0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT&0xff, I2C_HID_TOUCHPAD_MAX_HEIGHT>>8,\
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x30,			/*     Usage (Tip pressure) */         \
-	0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PRESSURE>>8,				       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x3f,			/*     Usage (Azimuth Orientation) */  \
-	0x16, 0x00, 0x00,		/*     Logical Minimum (0) */          \
-	0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_ORIENTATION>>8,			       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS_ORIENTATION,	/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0xC0,				/*   End Collection */
-
-	FINGER(1)
-	FINGER(2)
-	FINGER(3)
-	FINGER(4)
-	FINGER(5)
-
-#undef FINGER
-
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x85, REPORT_ID_DEVICE_CAPS,	/*   Report ID (Device Capabilities) */
-	0x09, 0x55,			/*   Usage (Contact Count Maximum) */
-	0x09, 0x59,			/*   Usage (Pad Type) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x95, 0x02,			/*   Report Count (2) */
-	0x25, 0x0F,			/*   Logical Maximum (15) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0x06, 0x00, 0xFF,		/*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,	/*   Report ID (Device Certification) */
-	0x09, 0xC5,			/*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,		/*   Logical Maximum (255) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x96, 0x00, 0x01,		/*   Report Count (256) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0xC0,				/* End Collection */
-
-	/* Configuration Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x0E,			/* Usage (Configuration) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_INPUT_MODE,	/*   Report ID (Input Mode) */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x02,			/*   Collection (Logical) */
-	0x09, 0x52,			/*     Usage (Input Mode) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x0F,			/*     Logical Maximum (15) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x01,			/*     Report Count (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x85, REPORT_ID_REPORTING,	/*     Report ID (Selective Reporting)*/
-	0x09, 0x57,			/*     Usage (Surface Switch) */
-	0x09, 0x58,			/*     Usage (Button Switch) */
-	0x75, 0x04,			/*     Report Size (4) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
-};
-
-static const uint8_t device_caps[] = {
-	I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Contact Count Maximum */
-	0x00,				/* Pad Type: Depressible click-pad */
-};
-
-/* A 256-byte default blob for the 'device certification status' feature report
- * expected by Windows.
- */
-static const uint8_t device_cert[] = {
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
-};
-
-#define MAX_SIZEOF(a, b) (sizeof(a) > sizeof(b) ? sizeof(a) : sizeof(b))
-
-static struct i2c_hid_descriptor hid_desc = {
-	.wHIDDescLength = I2C_HID_DESC_LENGTH,
-	.bcdVersion = I2C_HID_BCD_VERSION,
-	.wReportDescLength = sizeof(report_desc),
-	.wReportDescRegister = I2C_HID_REPORT_DESC_REGISTER,
-	.wInputRegister = I2C_HID_INPUT_REPORT_REGISTER,
-	.wMaxInputLength = I2C_HID_HEADER_SIZE +
-			   MAX_SIZEOF(struct touch_report, struct mouse_report),
-	.wOutputRegister = 0,
-	.wMaxOutputLength = 0,
-	.wCommandRegister = I2C_HID_COMMAND_REGISTER,
-	.wDataRegister = I2C_HID_DATA_REGISTER,
-	.wVendorID = I2C_HID_TOUCHPAD_VENDOR_ID,
-	.wProductID = I2C_HID_TOUCHPAD_PRODUCT_ID,
-	.wVersionID = I2C_HID_TOUCHPAD_FW_VERSION,
-};
-
-/*
- * In I2C HID, the host would request for an input report immediately following
- * the protocol initialization. The device is required to respond with exactly
- * 2 empty bytes. Furthermore, some hosts may use a single byte SMBUS read to
- * check if the device exists on the specified I2C address.
- *
- * These variables record if such probing/initialization have been done before.
- */
-static bool pending_probe;
-static bool pending_reset;
-
-/* Reports (double buffered) */
-#define MAX_REPORT_CNT	2
-
-static struct touch_report touch_reports[MAX_REPORT_CNT];
-static struct mouse_report mouse_reports[MAX_REPORT_CNT];
-
-/* Current active report buffer index */
-static int report_active_index;
-
-/* Current input mode */
-static uint8_t input_mode;
-
-/*
- * TODO(b/151693566): Selectively report surface contact and button state in
- * input reports based on |reporting.surface_switch| and
- * |reporting.button_switch|, respectively.
- */
-struct selective_reporting {
-	uint8_t surface_switch:4;
-	uint8_t button_switch:4;
-} __packed;
-
-static struct selective_reporting reporting;
-
-/* Function declarations */
-static int i2c_hid_touchpad_command_process(size_t len, uint8_t *buffer,
-					    void (*send_response)(int len),
-					    uint8_t *data);
-
-static size_t fill_report(uint8_t *buffer, uint8_t report_id, const void *data,
-			  size_t data_len)
-{
-	size_t response_len = I2C_HID_HEADER_SIZE + data_len;
-
-	buffer[0] = response_len & 0xFF;
-	buffer[1] = (response_len >> 8) & 0xFF;
-	buffer[2] = report_id;
-	memcpy(buffer + I2C_HID_HEADER_SIZE, data, data_len);
-	return response_len;
-}
-
-/*
- * Extracts report data from |buffer| into |data| for reports from the host.
- *
- * |buffer| is expected to contain the values written to the command register
- * followed by the values written to the data register, upon receiving a
- * SET_REPORT command, in the following byte sequence format:
- *
- *   00 30 - command register address (0x3000)
- *   xx    - report type and ID
- *   03    - SET_REPORT
- *   00 30 - data register address (0x3000)
- *   xx xx - length
- *   xx    - report ID
- *   xx... - report data
- *
- * Note that command register and data register have the same address. Also,
- * any report ID >= 15 requires an extra byte after the SET_REPORT byte, which
- * is not supported here as we don't have any report ID >= 15.
- *
- * In summary, we expect |buffer| contains at least 10 bytes where the report
- * data starts at buffer[9]. If |buffer| contains the incorrect number bytes,
- * we ignore the report.
- */
-static void extract_report(size_t len, const uint8_t *buffer, void *data,
-			   size_t data_len)
-{
-	if (len != 9 + data_len) {
-		ccprints("I2C-HID: SET_REPORT buffer length mismatch");
-		return;
-	}
-	memcpy(data, buffer + 9, data_len);
-}
-
-void i2c_hid_touchpad_init(void)
-{
-	input_mode = INPUT_MODE_MOUSE;
-	reporting.surface_switch = 1;
-	reporting.button_switch = 1;
-	report_active_index = 0;
-
-	// Respond probing requests for now.
-	pending_probe = true;
-	pending_reset = false;
-}
-
-int i2c_hid_touchpad_process(unsigned int len, uint8_t *buffer,
-			     void (*send_response)(int len), uint8_t *data,
-			     int *reg, int *cmd)
-{
-	size_t response_len;
-
-	if (len == 0)
-		*reg = I2C_HID_INPUT_REPORT_REGISTER;
-	else
-		*reg = UINT16_FROM_BYTE_ARRAY_LE(buffer, 0);
-
-	*cmd = 0;
-	switch (*reg) {
-	case I2C_HID_HID_DESC_REGISTER:
-		memcpy(buffer, &hid_desc, sizeof(hid_desc));
-		send_response(sizeof(hid_desc));
-		break;
-	case I2C_HID_REPORT_DESC_REGISTER:
-		memcpy(buffer, &report_desc, sizeof(report_desc));
-		send_response(sizeof(report_desc));
-		break;
-	case I2C_HID_INPUT_REPORT_REGISTER:
-		// Single-byte read probing.
-		if (pending_probe) {
-			buffer[0] = 0;
-			send_response(1);
-			break;
-		}
-		// Reset protocol: 2 empty bytes.
-		if (pending_reset) {
-			pending_reset = false;
-			buffer[0] = 0;
-			buffer[1] = 0;
-			send_response(2);
-			break;
-		}
-		// Common input report requests.
-		if (input_mode == INPUT_MODE_TOUCH) {
-			response_len =
-				fill_report(buffer, REPORT_ID_TOUCH,
-					    &touch_reports[report_active_index],
-					    sizeof(struct touch_report));
-		} else {
-			response_len =
-				fill_report(buffer, REPORT_ID_MOUSE,
-					    &mouse_reports[report_active_index],
-					    sizeof(struct mouse_report));
-		}
-		send_response(response_len);
-		break;
-	case I2C_HID_COMMAND_REGISTER:
-		*cmd = i2c_hid_touchpad_command_process(len, buffer,
-						       send_response, data);
-		break;
-	default:
-		/* Unknown register has been received. */
-		return EC_ERROR_INVAL;
-	}
-	/* Unknown command has been received. */
-	if (*cmd < 0)
-		return EC_ERROR_INVAL;
-	return EC_SUCCESS;
-}
-
-static int i2c_hid_touchpad_command_process(size_t len, uint8_t *buffer,
-					    void (*send_response)(int len),
-					    uint8_t *data)
-{
-	uint8_t command = buffer[3] & 0x0F;
-	uint8_t power_state = buffer[2] & 0x03;
-	uint8_t report_id = buffer[2] & 0x0F;
-	size_t response_len;
-
-	switch (command) {
-	case I2C_HID_CMD_RESET:
-		i2c_hid_touchpad_init();
-		// Wait for the 2-bytes I2C read following the protocol reset.
-		pending_probe = false;
-		pending_reset = true;
-		break;
-	case I2C_HID_CMD_GET_REPORT:
-		switch (report_id) {
-		case REPORT_ID_TOUCH:
-			response_len =
-				fill_report(buffer, report_id,
-					    &touch_reports[report_active_index],
-					    sizeof(struct touch_report));
-			break;
-		case REPORT_ID_MOUSE:
-			response_len =
-				fill_report(buffer, report_id,
-					    &mouse_reports[report_active_index],
-					    sizeof(struct mouse_report));
-			break;
-		case REPORT_ID_DEVICE_CAPS:
-			response_len = fill_report(buffer, report_id,
-						   &device_caps,
-						   sizeof(device_caps));
-			break;
-		case REPORT_ID_DEVICE_CERT:
-			response_len = fill_report(buffer, report_id,
-						   &device_cert,
-						   sizeof(device_cert));
-			break;
-		case REPORT_ID_INPUT_MODE:
-			response_len = fill_report(buffer, report_id,
-						   &input_mode,
-						   sizeof(input_mode));
-			break;
-		case REPORT_ID_REPORTING:
-			response_len = fill_report(buffer, report_id,
-						   &reporting,
-						   sizeof(reporting));
-			break;
-		default:
-			response_len = 2;
-			buffer[0] = response_len;
-			buffer[1] = 0;
-			break;
-		}
-		send_response(response_len);
-		break;
-	case I2C_HID_CMD_SET_REPORT:
-		switch (report_id) {
-		case REPORT_ID_INPUT_MODE:
-			extract_report(len, buffer, &input_mode,
-				       sizeof(input_mode));
-			break;
-		case REPORT_ID_REPORTING:
-			extract_report(len, buffer, &reporting,
-				       sizeof(reporting));
-			break;
-		default:
-			break;
-		}
-		break;
-	case I2C_HID_CMD_SET_POWER:
-		/*
-		 * Return the power setting so the user can actually set the
-		 * touch controller's power state in board level.
-		 */
-		*data = power_state;
-		break;
-	default:
-		return -1;
-	}
-	return command;
-}
-
-void i2c_hid_compile_report(struct touchpad_event *event)
-{
-	/* Save report into back buffer */
-	struct touch_report *touch = &touch_reports[report_active_index ^ 1];
-	struct touch_report *touch_old = &touch_reports[report_active_index];
-	struct mouse_report *mouse = &mouse_reports[report_active_index ^ 1];
-	int contact_num = 0;
-
-	/* Touch report. */
-	memset(touch, 0, sizeof(struct touch_report));
-	for (int i = 0; i < I2C_HID_TOUCHPAD_MAX_FINGERS; i++) {
-		if (event->finger[i].valid) {
-			/*
-			 * Windows considers any contact with width or height
-			 * greater than 25mm to unintended, and expects the
-			 * confidence value to be cleared for such a contact.
-			 * We, however, haven't seen a touchpad that actually
-			 * forwards that information to us.
-			 *
-			 * TODO(b/151692377): Revisit this once we have met such
-			 * a device.
-			 */
-			touch->finger[i].confidence = 1;
-			touch->finger[i].tip = 1;
-			touch->finger[i].inrange = 1;
-			touch->finger[i].x = event->finger[i].x;
-			touch->finger[i].y = event->finger[i].y;
-			touch->finger[i].width = event->finger[i].width;
-			touch->finger[i].height = event->finger[i].height;
-			touch->finger[i].pressure = event->finger[i].pressure;
-			if (event->finger[i].is_palm)
-				touch->finger[i].pressure =
-						I2C_HID_TOUCHPAD_MAX_PRESSURE;
-			touch->finger[i].orientation =
-					event->finger[i].orientation;
-			contact_num++;
-		} else if (touch_old->finger[i].tip) {
-			/*
-			 * When the finger is leaving, we first clear the tip
-			 * bit while retaining the other values. We then clear
-			 * the other values at the next frame where the finger
-			 * has left.
-			 *
-			 * Setting tip to 0 implies that the finger is leaving
-			 * for both CrOS and Windows. A leaving finger would
-			 * never be re-considered by the OS.
-			 */
-
-			/*
-			 * First, copy old values from the previous report.
-			 *
-			 * This is suggested on Windows although no
-			 * obvious problem has been noticed by not doing
-			 * so.
-			 */
-			touch->finger[i] = touch_old->finger[i];
-
-			/*
-			 * Leaving finger is not a palm by definition.
-			 *
-			 * Not clearing the confidence bit is essential
-			 * for tap-to-click to work on Windows.
-			 */
-			touch->finger[i].confidence = 1;
-
-			/* Leaving finger doesn't exist. */
-			touch->finger[i].tip = 0;
-
-			/*
-			 * Assume that the leaving finger is not hovering
-			 * either. We would inject one single fake hovering
-			 * finger later if necessary.
-			 */
-			touch->finger[i].inrange = 0;
-
-			contact_num++;
-		}
-
-		/* id is like slot in Linux MT-B so it is fixed every time. */
-		touch->finger[i].id = i;
-	}
-
-	/* Check for hovering activity if there is no contact report. */
-	if (!contact_num) {
-		if (event->hover) {
-			/* Put a fake finger at slot #0 if hover is detected. */
-			touch->finger[0].inrange = 1;
-			touch->finger[0].x = I2C_HID_TOUCHPAD_MAX_X / 2;
-			touch->finger[0].y = I2C_HID_TOUCHPAD_MAX_Y / 2;
-			contact_num++;
-		} else if (!touch_old->finger[0].tip &&
-			   touch_old->finger[0].inrange) {
-			/* Clear the fake hovering finger for host. */
-			contact_num++;
-		}
-	}
-
-	/* Fill in finger counts and the button state. */
-	touch->count = I2C_HID_TOUCHPAD_MAX_FINGERS;
-	touch->button = event->button;
-
-	/*
-	 * Windows expects scan time to be in units of 100us.  As Windows
-	 * measures the delta of scan times between the first and the current
-	 * report, we simply report the __hw_clock_source_read() value (which
-	 * is in resolution of 1us) divided by 100 as the scan time.
-	 */
-	touch->timestamp = __hw_clock_source_read() / 100;
-
-	/* Mouse report. */
-	mouse->button1 = touch->button;
-	if (touch->finger[0].tip == 1 && touch_old->finger[0].tip == 1) {
-		/*
-		 * The relative X/Y movements in the mouse report are computed
-		 * based on the deltas of absolute X/Y positions between the
-		 * previous and current touch report. The computed deltas need
-		 * to be scaled for a smooth mouse movement.
-		 */
-		mouse->x = (touch->finger[0].x - touch_old->finger[0].x) /
-			   I2C_HID_TOUCHPAD_MOUSE_SCALE_X;
-		mouse->y = (touch->finger[0].y - touch_old->finger[0].y) /
-			   I2C_HID_TOUCHPAD_MOUSE_SCALE_Y;
-	} else {
-		mouse->x = 0;
-		mouse->y = 0;
-	}
-
-	/* Swap buffer */
-	report_active_index ^= 1;
-}
diff --git a/common/i2c_peripheral.c b/common/i2c_peripheral.c
deleted file mode 100644
index 20a4b4b0ae..0000000000
--- a/common/i2c_peripheral.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C peripheral cross-platform code for Chrome EC */
-
-#include "host_command.h"
-#include "i2c.h"
-#include "util.h"
-
-enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = I2C_MAX_HOST_PACKET_SIZE;
-	r->max_response_packet_size = I2C_MAX_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     i2c_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/common/i2c_trace.c b/common/i2c_trace.c
deleted file mode 100644
index 67b8864b22..0000000000
--- a/common/i2c_trace.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "stddef.h"
-#include "stdbool.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-struct i2c_trace_range {
-	bool enabled;
-	int port;
-	int addr_lo; /* Inclusive */
-	int addr_hi; /* Inclusive */
-};
-
-static struct i2c_trace_range trace_entries[8];
-
-void i2c_trace_notify(int port, uint16_t addr_flags,
-		      const uint8_t *out_data, size_t out_size,
-		      const uint8_t *in_data, size_t in_size)
-{
-	size_t i;
-	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
-
-	for (i = 0; i < ARRAY_SIZE(trace_entries); i++)
-		if (trace_entries[i].enabled
-		    && trace_entries[i].port == port
-		    && trace_entries[i].addr_lo <= addr
-		    && trace_entries[i].addr_hi >= addr)
-			goto trace_enabled;
-	return;
-
-trace_enabled:
-	CPRINTF("i2c: %d:0x%X ", port, addr);
-	if (out_size) {
-		CPRINTF("wr ");
-		for (i = 0; i < out_size; i++)
-			CPRINTF("0x%02X ", out_data[i]);
-	}
-	if (in_size) {
-		CPRINTF("  rd ");
-		for (i = 0; i < in_size; i++)
-			CPRINTF("0x%02X ", in_data[i]);
-	}
-	CPRINTF("\n");
-}
-
-static int command_i2ctrace_list(void)
-{
-	size_t i;
-	const struct i2c_port_t *i2c_port;
-
-	ccprintf("id port       address\n");
-	ccprintf("-- ----       -------\n");
-
-	for (i = 0; i < ARRAY_SIZE(trace_entries); i++) {
-		if (trace_entries[i].enabled) {
-			i2c_port = get_i2c_port(trace_entries[i].port);
-			ccprintf("%-2zd %d %-8s 0x%X",
-				 i,
-				 trace_entries[i].port,
-				 i2c_port->name,
-				 trace_entries[i].addr_lo);
-			if (trace_entries[i].addr_hi
-			    != trace_entries[i].addr_lo)
-				ccprintf(" to 0x%X",
-					 trace_entries[i].addr_hi);
-			ccprintf("\n");
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int command_i2ctrace_disable(size_t id)
-{
-	if (id >= ARRAY_SIZE(trace_entries))
-		return EC_ERROR_PARAM2;
-
-	trace_entries[id].enabled = 0;
-	return EC_SUCCESS;
-}
-
-static int command_i2ctrace_enable(int port, int addr_lo,
-				   int addr_hi)
-{
-	struct i2c_trace_range *t;
-	struct i2c_trace_range *new_entry = NULL;
-
-	if (!get_i2c_port(port))
-		return EC_ERROR_PARAM2;
-
-	if (addr_lo > addr_hi)
-		return EC_ERROR_PARAM3;
-
-	/*
-	 * Scan thru existing entries to see if there is one we can
-	 * extend instead of making a new entry
-	 */
-	for (t = trace_entries;
-	     t < trace_entries + ARRAY_SIZE(trace_entries);
-	     t++) {
-		if (t->enabled && t->port == port) {
-			/* Subset of existing range, do nothing */
-			if (t->addr_lo <= addr_lo &&
-			    t->addr_hi >= addr_hi)
-				return EC_SUCCESS;
-
-			/* Extends exising range on both directions, replace */
-			if (t->addr_lo >= addr_lo &&
-			    t->addr_hi <= addr_hi) {
-				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port, addr_lo, addr_hi);
-			}
-
-			/* Extends existing range below */
-			if (t->addr_lo - 1 <= addr_hi &&
-			    t->addr_hi >= addr_hi) {
-				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					addr_lo,
-					t->addr_hi);
-			}
-
-			/* Extends existing range above */
-			if (t->addr_lo <= addr_lo &&
-			    t->addr_hi + 1 >= addr_lo) {
-				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					t->addr_lo,
-					addr_hi);
-			}
-		} else if (!t->enabled && !new_entry) {
-			new_entry = t;
-		}
-	}
-
-	/* We need to allocate a new entry */
-	if (new_entry) {
-		new_entry->enabled = 1;
-		new_entry->port = port;
-		new_entry->addr_lo = addr_lo;
-		new_entry->addr_hi = addr_hi;
-		return EC_SUCCESS;
-	}
-
-	ccprintf("No space to allocate new trace entry. Delete some first.\n");
-	return EC_ERROR_MEMORY_ALLOCATION;
-}
-
-
-static int command_i2ctrace(int argc, char **argv)
-{
-	int id_or_port;
-	int address_low;
-	int address_high;
-	char *end;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "list") && argc == 2)
-		return command_i2ctrace_list();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	id_or_port = strtoi(argv[2], &end, 0);
-	if (*end || id_or_port < 0)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(argv[1], "disable") && argc == 3)
-		return command_i2ctrace_disable(id_or_port);
-
-	if (!strcasecmp(argv[1], "enable")) {
-		address_low = strtoi(argv[3], &end, 0);
-		if (*end || address_low < 0)
-			return EC_ERROR_PARAM3;
-
-		if (argc == 4) {
-			address_high = address_low;
-		} else if (argc == 5) {
-			address_high = strtoi(argv[4], &end, 0);
-			if (*end || address_high < 0)
-				return EC_ERROR_PARAM4;
-		} else {
-			return EC_ERROR_PARAM_COUNT;
-		}
-
-		return command_i2ctrace_enable(
-			id_or_port, address_low, address_high);
-	}
-
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(i2ctrace,
-			command_i2ctrace,
-			"[list | disable <id> | enable <port> <address> | "
-			"enable <port> <address-low> <address-high>]",
-			"Trace I2C transactions");
diff --git a/common/i2c_wedge.c b/common/i2c_wedge.c
deleted file mode 100644
index 48bcac090c..0000000000
--- a/common/i2c_wedge.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Define CONFIG_CMD_I2CWEDGE and I2C_PORT_HOST to enable the 'i2cwedge'
- * console command to allow us to bang the bus into a wedged state. For
- * example, include the following lines in board/pit/board.h to enable it on
- * pit:
- *
- * #define CONFIG_CMD_I2CWEDGE
- * #define I2C_PORT_HOST I2C_PORT_CONTROLLER
- *
- */
-
-#include "console.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * The implementation is based on Wikipedia.
- */
-
-int i2c_bang_started;
-
-static void i2c_bang_delay(void)
-{
-	udelay(5);
-}
-
-static void i2c_bang_start_cond(void)
-{
-	/* Restart if needed */
-	if (i2c_bang_started) {
-		/* set SDA to 1 */
-		i2c_raw_set_sda(I2C_PORT_HOST, 1);
-		i2c_bang_delay();
-
-		/* Clock stretching */
-		i2c_raw_set_scl(I2C_PORT_HOST, 1);
-		while (i2c_raw_get_scl(I2C_PORT_HOST) == 0)
-			; /* TODO(crosbug.com/p/26487): TIMEOUT */
-
-		/* Repeated start setup time, minimum 4.7us */
-		i2c_bang_delay();
-	}
-
-	i2c_raw_set_sda(I2C_PORT_HOST, 1);
-	if (i2c_raw_get_sda(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): arbitration_lost */
-
-	/* SCL is high, set SDA from 1 to 0. */
-	i2c_raw_set_sda(I2C_PORT_HOST, 0);
-	i2c_bang_delay();
-	i2c_raw_set_scl(I2C_PORT_HOST, 0);
-	i2c_bang_started = 1;
-
-	ccputs("BITBANG: send start\n");
-}
-
-static void i2c_bang_stop_cond(void)
-{
-	/* set SDA to 0 */
-	i2c_raw_set_sda(I2C_PORT_HOST, 0);
-	i2c_bang_delay();
-
-	/* Clock stretching */
-	i2c_raw_set_scl(I2C_PORT_HOST, 1);
-	while (i2c_raw_get_scl(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): TIMEOUT */
-
-	/* Stop bit setup time, minimum 4us */
-	i2c_bang_delay();
-
-	/* SCL is high, set SDA from 0 to 1 */
-	i2c_raw_set_sda(I2C_PORT_HOST, 1);
-	if (i2c_raw_get_sda(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): arbitration_lost */
-
-	i2c_bang_delay();
-
-	i2c_bang_started = 0;
-	ccputs("BITBANG: send stop\n");
-}
-
-static void i2c_bang_out_bit(int bit)
-{
-	if (bit)
-		i2c_raw_set_sda(I2C_PORT_HOST, 1);
-	else
-		i2c_raw_set_sda(I2C_PORT_HOST, 0);
-
-	i2c_bang_delay();
-
-	/* Clock stretching */
-	i2c_raw_set_scl(I2C_PORT_HOST, 1);
-	while (i2c_raw_get_scl(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): TIMEOUT */
-
-	/*
-	 * SCL is high, now data is valid
-	 * If SDA is high, check that nobody else is driving SDA
-	 */
-	i2c_raw_set_sda(I2C_PORT_HOST, 1);
-	if (bit && i2c_raw_get_sda(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): arbitration_lost */
-
-	i2c_bang_delay();
-	i2c_raw_set_scl(I2C_PORT_HOST, 0);
-}
-
-static int i2c_bang_in_bit(void)
-{
-	int bit;
-
-	/* Let the peripheral drive data */
-	i2c_raw_set_sda(I2C_PORT_HOST, 1);
-	i2c_bang_delay();
-
-	/* Clock stretching */
-	i2c_raw_set_scl(I2C_PORT_HOST, 1);
-	while (i2c_raw_get_scl(I2C_PORT_HOST) == 0)
-		; /* TODO(crosbug.com/p/26487): TIMEOUT */
-
-	/* SCL is high, now data is valid */
-	bit = i2c_raw_get_sda(I2C_PORT_HOST);
-	i2c_bang_delay();
-	i2c_raw_set_scl(I2C_PORT_HOST, 0);
-
-	return bit;
-}
-
-/* Write a byte to I2C bus. Return 0 if ack by the peripheral. */
-static int i2c_bang_out_byte(int send_start, int send_stop, unsigned char byte)
-{
-	unsigned bit;
-	int nack;
-	int tmp = byte;
-
-	if (send_start)
-		i2c_bang_start_cond();
-
-	for (bit = 0; bit < 8; bit++) {
-		i2c_bang_out_bit((byte & 0x80) != 0);
-		byte <<= 1;
-	}
-
-	nack = i2c_bang_in_bit();
-
-	ccprintf("  write byte: %d     ack/nack=%d\n", tmp, nack);
-
-	if (send_stop)
-		i2c_bang_stop_cond();
-
-	return nack;
-}
-
-static unsigned char i2c_bang_in_byte(int ack, int send_stop)
-{
-	unsigned char byte = 0;
-	int i;
-	for (i = 0; i < 8; ++i)
-		byte = (byte << 1) | i2c_bang_in_bit();
-	i2c_bang_out_bit(ack != 0);
-	if (send_stop)
-		i2c_bang_stop_cond();
-	return byte;
-}
-
-static void i2c_bang_init(void)
-{
-	i2c_bang_started = 0;
-
-	i2c_raw_mode(I2C_PORT_HOST, 1);
-}
-
-static void i2c_bang_xfer(int addr, int reg)
-{
-	int byte;
-
-	i2c_bang_init();
-
-	/* State a write command to 'addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
-	/* Write 'reg' */
-	i2c_bang_out_byte(0 /*start*/, 0 /*stop*/, reg);
-
-	/* Start a read command */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr | 1);
-
-	/* Read two bytes */
-	byte = i2c_bang_in_byte(0, 0); /* ack and no stop */
-	ccprintf("  read byte: %d\n", byte);
-	byte = i2c_bang_in_byte(1, 1); /* nack and stop */
-	ccprintf("  read byte: %d\n", byte);
-}
-
-static void i2c_bang_wedge_write(int addr, int byte, int bit_count,
-	int reboot)
-{
-	int i;
-
-	i2c_bang_init();
-
-	/* State a write command to 'addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
-	/* Send a few bits and stop */
-	for (i = 0; i < bit_count; ++i) {
-		i2c_bang_out_bit((byte & 0x80) != 0);
-		byte <<= 1;
-	}
-	ccprintf("  wedged write after %d bits\n", bit_count);
-
-	if (reboot)
-		system_reset(0);
-}
-
-static void i2c_bang_wedge_read(int addr, int reg, int bit_count,
-	int reboot)
-{
-	int i;
-
-	i2c_bang_init();
-
-	/* State a write command to 'addr' */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr);
-	/* Write 'reg' */
-	i2c_bang_out_byte(0 /*start*/, 0 /*stop*/, reg);
-
-	/* Start a read command */
-	i2c_bang_out_byte(1 /*start*/, 0 /*stop*/, addr | 1);
-
-	/* Read bit_count bits and stop */
-	for (i = 0; i < bit_count; ++i)
-		i2c_bang_in_bit();
-
-	ccprintf("  wedged read after %d bits\n", bit_count);
-
-	if (reboot)
-		system_reset(0);
-}
-
-#define WEDGE_WRITE	1
-#define WEDGE_READ	2
-#define WEDGE_REBOOT	4
-
-static int command_i2c_wedge(int argc, char **argv)
-{
-	int addr, reg, wedge_flag = 0, wedge_bit_count = -1;
-	char *e;
-	enum gpio_signal tmp;
-
-	/* Verify that the I2C_PORT_HOST has SDA and SCL pins defined. */
-	if (get_sda_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS ||
-		get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) {
-		ccprintf("Cannot wedge bus because no SCL and SDA pins are"
-			"defined for this port. Check i2c_ports[].\n");
-		return EC_SUCCESS;
-	}
-
-	if (argc < 3) {
-		ccputs("Usage: i2cwedge addr out_byte "
-			"[wedge_flag [wedge_bit_count]]\n");
-		ccputs("  wedge_flag - (1: wedge out; 2: wedge in;"
-			" 5: wedge out+reboot; 6: wedge in+reboot)]\n");
-		ccputs("  wedge_bit_count - 0 to 8\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	addr = strtoi(argv[1], &e, 0);
-	if (*e) {
-		ccprintf("Invalid addr %s\n", argv[1]);
-		return EC_ERROR_INVAL;
-	}
-	reg = strtoi(argv[2], &e, 0);
-	if (*e) {
-		ccprintf("Invalid out_byte %s\n", argv[2]);
-		return EC_ERROR_INVAL;
-	}
-	if (argc > 3) {
-		wedge_flag = strtoi(argv[3], &e, 0);
-		if (*e) {
-			ccprintf("Invalid wedge_flag %s\n", argv[3]);
-			return EC_ERROR_INVAL;
-		}
-	}
-	if (argc > 4) {
-		wedge_bit_count = strtoi(argv[4], &e, 0);
-		if (*e || wedge_bit_count < 0 || wedge_bit_count > 8) {
-			ccprintf("Invalid wedge_bit_count %s.\n", argv[4]);
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	i2c_lock(I2C_PORT_HOST, 1);
-
-	if (wedge_flag & WEDGE_WRITE) {
-		if (wedge_bit_count < 0)
-			wedge_bit_count = 8;
-		i2c_bang_wedge_write(addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
-	} else if (wedge_flag & WEDGE_READ) {
-		if (wedge_bit_count < 0)
-			wedge_bit_count = 2;
-		i2c_bang_wedge_read(addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
-	} else {
-		i2c_bang_xfer(addr, reg);
-	}
-
-	/* Put it back into normal mode */
-	i2c_raw_mode(I2C_PORT_HOST, 0);
-
-	i2c_lock(I2C_PORT_HOST, 0);
-
-	if (wedge_flag & (WEDGE_WRITE | WEDGE_READ))
-		ccprintf("I2C bus %d is now wedged. Enjoy.\n", I2C_PORT_HOST);
-	else
-		ccprintf("Bit bang xfer complete.\n");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cwedge, command_i2c_wedge,
-			"i2cwedge addr out_byte "
-				"[wedge_flag [wedge_bit_count]]",
-			"Wedge host I2C bus");
-
-static int command_i2c_unwedge(int argc, char **argv)
-{
-	i2c_unwedge(I2C_PORT_HOST);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge,
-	"",
-	"Unwedge host I2C bus");
-
diff --git a/common/inductive_charging.c b/common/inductive_charging.c
deleted file mode 100644
index 793f535afe..0000000000
--- a/common/inductive_charging.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Inductive charging control */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "inductive_charging.h"
-#include "lid_switch.h"
-#include "timer.h"
-
-/*
- * The inductive charger is controlled with two signals:
- *   - BASE_CHG_VDD_EN controls whether the charger is powered.
- *   - CHARGE_EN controls whether to enable charging.
- * Charging status is reported via CHARGE_DONE, but in a tricky way:
- *   - It's 0 if:
- *     + The charger is unpowered. (i.e. BASE_CHG_VDD_EN = 0)
- *     + Or charging is disabled. (i.e. CHARGE_EN = 0)
- *     + Or the charging current is small enough.
- *   - Otherwise, it's 1.
- */
-
-/* Whether we want to process interrupts on CHARGE_DONE or not. */
-static int monitor_charge_done;
-
-/*
- * Start monitoring CHARGE_DONE and fires the interrupt once so that
- * we react to the current value.
- */
-static void inductive_charging_monitor_charge(void)
-{
-	monitor_charge_done = 1;
-	inductive_charging_interrupt(GPIO_CHARGE_DONE);
-}
-DECLARE_DEFERRED(inductive_charging_monitor_charge);
-
-void inductive_charging_interrupt(enum gpio_signal signal)
-{
-	int charger_enabled = gpio_get_level(GPIO_BASE_CHG_VDD_EN);
-	int charge_done = gpio_get_level(GPIO_CHARGE_DONE);
-	static int charge_already_done;
-
-	if (!monitor_charge_done && signal == GPIO_CHARGE_DONE)
-		return;
-
-	if (signal == GPIO_LID_OPEN) {
-		/* The lid has been opened. Clear all states. */
-		charge_done = 0;
-		charge_already_done = 0;
-		monitor_charge_done = 0;
-	} else if (signal == GPIO_CHARGE_DONE) {
-		/*
-		 * Once we see CHARGE_DONE=1, we ignore any change on
-		 * CHARGE_DONE until the next time the lid is opened.
-		 */
-		if (charge_done == 1)
-			charge_already_done = 1;
-		else if (charge_already_done)
-			return;
-	}
-
-	if (!charger_enabled || charge_done) {
-		gpio_set_level(GPIO_CHARGE_EN, 0);
-	} else {
-		gpio_set_level(GPIO_CHARGE_EN, 1);
-		/*
-		 * When the charging is just enabled, there might be a
-		 * blip on CHARGE_DONE. Wait for a second before we start
-		 * looking at CHARGE_DONE.
-		 */
-		if (!monitor_charge_done)
-			hook_call_deferred(
-				&inductive_charging_monitor_charge_data,
-				SECOND);
-	}
-}
-
-static void inductive_charging_deferred_update(void)
-{
-	int lid_open = lid_is_open();
-	gpio_set_level(GPIO_BASE_CHG_VDD_EN, !lid_open);
-	inductive_charging_interrupt(GPIO_LID_OPEN);
-}
-DECLARE_DEFERRED(inductive_charging_deferred_update);
-
-static void inductive_charging_lid_update(void)
-{
-	/*
-	 * When the lid close signal changes, the coils might still be
-	 * unaligned. Delay here to give the coils time to align before
-	 * we try to clear CHARGE_DONE.
-	 */
-	hook_call_deferred(&inductive_charging_deferred_update_data,
-			   5 * SECOND);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, inductive_charging_lid_update, HOOK_PRIO_DEFAULT);
-
-static void inductive_charging_init(void)
-{
-	gpio_enable_interrupt(GPIO_CHARGE_DONE);
-	inductive_charging_lid_update();
-}
-DECLARE_HOOK(HOOK_INIT, inductive_charging_init, HOOK_PRIO_DEFAULT);
diff --git a/common/init_rom.c b/common/init_rom.c
deleted file mode 100644
index 320849c008..0000000000
--- a/common/init_rom.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Init ROM module for Chrome EC */
-
-#include "builtin/assert.h"
-#include "common.h"
-#include "init_rom.h"
-#include "flash.h"
-#include "stdbool.h"
-#include "stddef.h"
-
-const void *init_rom_map(const void *addr, int size)
-{
-	const char *src;
-	uintptr_t offset;
-
-	/*
-	 * When CONFIG_CHIP_INIT_ROM_REGION isn't enabled, .init_rom objects
-	 * are linked into the .rodata section and directly addressable.
-	 * Return the caller's pointer.
-	 */
-	if (!IS_ENABLED(CONFIG_CHIP_INIT_ROM_REGION))
-		return addr;
-
-	/*
-	 * When flash isn't memory mapped, caller's must use init_rom_copy()
-	 * to copy .init_rom data into RAM.
-	 */
-	if (!IS_ENABLED(CONFIG_MAPPED_STORAGE))
-		return NULL;
-
-	/*
-	 * Safe pointer conversion - needed for host tests which can have
-	 * 64-bit pointers.
-	 */
-	offset = (uintptr_t)addr;
-
-	ASSERT(offset <= __INT_MAX__);
-
-	/*
-	 * Convert flash offset to memory mapped address
-	 */
-	if (crec_flash_dataptr((int)offset, size, 1, &src) < 0)
-		return NULL;
-
-	/* Once the flash offset is validated, lock the flash for the caller */
-	crec_flash_lock_mapped_storage(1);
-
-	return src;
-}
-
-/*
- * The addr and size parameters are provided for forward compatibility if
- * the flash API is extended to support locking less than the entire flash.
- */
-void init_rom_unmap(const void *addr, int size)
-{
-	if (IS_ENABLED(CONFIG_CHIP_INIT_ROM_REGION))
-		crec_flash_lock_mapped_storage(0);
-}
-
-int init_rom_copy(int offset, int size, char *data)
-{
-	return crec_flash_read(offset, size, data);
-}
-
diff --git a/common/ioexpander.c b/common/ioexpander.c
deleted file mode 100644
index ccf3cc7c4a..0000000000
--- a/common/ioexpander.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* IO Expander Controller Common Code */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-static uint8_t last_val[(IOEX_COUNT + 7) / 8];
-
-static int last_val_changed(enum ioex_signal signal, int v)
-{
-	const int i = signal - IOEX_SIGNAL_START;
-
-	ASSERT(signal_is_ioex(signal));
-
-	if (v && !(last_val[i / 8] & (BIT(i % 8)))) {
-		last_val[i / 8] |= BIT(i % 8);
-		return 1;
-	} else if (!v && last_val[i / 8] & (BIT(i % 8))) {
-		last_val[i / 8] &= ~(BIT(i % 8));
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-int signal_is_ioex(int signal)
-{
-	return ((signal >= IOEX_SIGNAL_START) && (signal < IOEX_SIGNAL_END));
-}
-
-static const struct ioex_info *ioex_get_signal_info(enum ioex_signal signal)
-{
-	const struct ioex_info *g;
-
-	ASSERT(signal_is_ioex(signal));
-
-	g = ioex_list + signal - IOEX_SIGNAL_START;
-
-	if (ioex_config[g->ioex].flags & IOEX_FLAGS_DISABLED) {
-		CPRINTS("ioex %s disabled", g->name);
-		return NULL;
-	}
-
-	return g;
-}
-
-static int ioex_is_valid_interrupt_signal(enum ioex_signal signal)
-{
-	const struct ioexpander_drv *drv;
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return EC_ERROR_BUSY;
-
-	/* Fail if no interrupt handler */
-	if (signal - IOEX_SIGNAL_START >= ioex_ih_count)
-		return EC_ERROR_PARAM1;
-
-	drv = ioex_config[g->ioex].drv;
-	/*
-	 * Not every IOEX chip can support interrupt, check it before enabling
-	 * the interrupt function
-	 */
-	if (drv->enable_interrupt == NULL) {
-		CPRINTS("IOEX chip port %d doesn't support INT", g->ioex);
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return EC_SUCCESS;
-}
-
-int ioex_enable_interrupt(enum ioex_signal signal)
-{
-	int rv;
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-	const struct ioexpander_drv *drv;
-
-	rv = ioex_is_valid_interrupt_signal(signal);
-	if (rv != EC_SUCCESS)
-		return  rv;
-
-	drv = ioex_config[g->ioex].drv;
-	return drv->enable_interrupt(g->ioex, g->port, g->mask, 1);
-}
-
-int ioex_disable_interrupt(enum ioex_signal signal)
-{
-	int rv;
-	const struct ioexpander_drv *drv;
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	rv = ioex_is_valid_interrupt_signal(signal);
-	if (rv != EC_SUCCESS)
-		return  rv;
-
-	drv = ioex_config[g->ioex].drv;
-	return drv->enable_interrupt(g->ioex, g->port, g->mask, 0);
-}
-
-int ioex_get_flags(enum ioex_signal signal, int *flags)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return EC_ERROR_BUSY;
-
-	return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
-}
-
-int ioex_set_flags(enum ioex_signal signal, int flags)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return EC_ERROR_BUSY;
-
-	return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
-}
-
-int ioex_get_level(enum ioex_signal signal, int *val)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return EC_ERROR_BUSY;
-
-	return ioex_config[g->ioex].drv->get_level(g->ioex, g->port,
-							g->mask, val);
-}
-
-int ioex_set_level(enum ioex_signal signal, int value)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return EC_ERROR_BUSY;
-
-	return ioex_config[g->ioex].drv->set_level(g->ioex, g->port,
-							g->mask, value);
-}
-
-#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-int ioex_get_port(int ioex, int port, int *val)
-{
-	if (ioex_config[ioex].drv->get_port == NULL)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	return ioex_config[ioex].drv->get_port(ioex, port, val);
-}
-#endif
-
-int ioex_init(int ioex)
-{
-	const struct ioex_info *g = ioex_list;
-	const struct ioexpander_drv *drv = ioex_config[ioex].drv;
-	int rv;
-	int i;
-
-	if (ioex_config[ioex].flags & IOEX_FLAGS_DISABLED)
-		return EC_ERROR_BUSY;
-
-	if (drv->init != NULL) {
-		rv = drv->init(ioex);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	/*
-	 * Set all IO expander GPIOs to default flags according to the setting
-	 * in gpio.inc
-	 */
-	for (i = 0; i < IOEX_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (g->ioex == ioex && g->mask && !(flags & GPIO_DEFAULT)) {
-			/* Late-sysJump should not set the output levels */
-			if (system_jumped_late())
-				flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-			drv->set_flags_by_mask(g->ioex, g->port,
-						g->mask, flags);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static void ioex_init_default(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++)
-		ioex_init(i);
-}
-DECLARE_HOOK(HOOK_INIT, ioex_init_default, HOOK_PRIO_INIT_I2C + 1);
-
-const char *ioex_get_name(enum ioex_signal signal)
-{
-	const struct ioex_info *g = ioex_list + signal - IOEX_SIGNAL_START;
-
-	return g->name;
-}
-
-static void print_ioex_info(enum ioex_signal signal)
-{
-	int changed, v, val;
-	int flags = 0;
-	const struct ioex_info *g = ioex_list + signal - IOEX_SIGNAL_START;
-
-	if (ioex_config[g->ioex].flags & IOEX_FLAGS_DISABLED) {
-		ccprintf("  DISABLED %s\n", ioex_get_name(signal));
-		return;
-	}
-
-
-	v = ioex_get_level(signal, &val);
-	if (v) {
-		ccprintf("Fail to get %s level\n", ioex_get_name(signal));
-		return;
-	}
-	v = ioex_get_flags(signal, &flags);
-	if (v) {
-		ccprintf("Fail to get %s flags\n", ioex_get_name(signal));
-		return;
-	}
-
-	changed = last_val_changed(signal, val);
-
-	ccprintf("  %d%c %s%s%s%s%s%s\n", val,
-		 (changed ? '*' : ' '),
-		 (flags & GPIO_INPUT ? "I " : ""),
-		 (flags & GPIO_OUTPUT ? "O " : ""),
-		 (flags & GPIO_LOW ? "L " : ""),
-		 (flags & GPIO_HIGH ? "H " : ""),
-		 (flags & GPIO_OPEN_DRAIN ? "ODR " : ""),
-		ioex_get_name(signal));
-
-	/* Flush console to avoid truncating output */
-	cflush();
-}
-
-static int ioex_get_default_flags(enum ioex_signal signal)
-{
-	const struct ioex_info *g = ioex_get_signal_info(signal);
-
-	if (g == NULL)
-		return 0;
-
-	return g->flags;
-}
-
-/* IO expander commands */
-static enum ioex_signal find_ioex_by_name(const char *name)
-{
-	enum ioex_signal signal;
-
-	if (!name)
-		return IOEX_SIGNAL_END;
-
-	for (signal = IOEX_SIGNAL_START; signal < IOEX_SIGNAL_END; signal++) {
-		if (!strcasecmp(name, ioex_get_name(signal)))
-			return signal;
-	}
-
-	return IOEX_SIGNAL_END;
-}
-
-static enum ec_error_list ioex_set(const char *name, int value)
-{
-	enum ioex_signal signal = find_ioex_by_name(name);
-
-	if (!signal_is_ioex(signal))
-		return EC_ERROR_INVAL;
-
-	if (!(ioex_get_default_flags(signal) & GPIO_OUTPUT))
-		return EC_ERROR_INVAL;
-
-	return ioex_set_level(signal, value);
-}
-
-static int command_ioex_set(int argc, char **argv)
-{
-	char *e;
-	int v;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	v = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	if (ioex_set(argv[1], v) != EC_SUCCESS)
-		return EC_ERROR_PARAM1;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set,
-			"name <0 | 1>",
-			"Set level of a IO expander IO");
-
-static int command_ioex_get(int argc, char **argv)
-{
-	enum ioex_signal signal;
-
-	/* If a signal is specified, print only that one */
-	if (argc == 2) {
-		signal = find_ioex_by_name(argv[1]);
-		if (!signal_is_ioex(signal))
-			return EC_ERROR_PARAM1;
-		print_ioex_info(signal);
-
-		return EC_SUCCESS;
-	}
-
-	/* Otherwise print them all */
-	for (signal = IOEX_SIGNAL_START; signal < IOEX_SIGNAL_END; signal++)
-		print_ioex_info(signal);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get,
-			     "[name]",
-			     "Read level of IO expander pin(s)");
-
diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c
deleted file mode 100644
index 699eaa6687..0000000000
--- a/common/keyboard_8042.c
+++ /dev/null
@@ -1,1328 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * 8042 keyboard protocol
- */
-
-#include "chipset.h"
-#include "button.h"
-#include "common.h"
-#include "console.h"
-#include "device_event.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i8042_protocol.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "lightbar.h"
-#include "lpc.h"
-#include "power_button.h"
-#include "queue.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-#define CPUTS5(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
-#else
-#define CPUTS5(outstr)
-#define CPRINTS5(format, args...)
-#endif
-
-/*
- * This command needs malloc to work. Could we use this instead?
- *
- * #define CMD_KEYBOARD_LOG IS_ENABLED(CONFIG_MALLOC)
- */
-#ifdef CONFIG_MALLOC
-#define CMD_KEYBOARD_LOG	1
-#else
-#define CMD_KEYBOARD_LOG	0
-#endif
-
-static enum {
-	STATE_NORMAL = 0,
-	STATE_SCANCODE,
-	STATE_SETLEDS,
-	STATE_EX_SETLEDS_1,		/* Expect 2-byte parameter */
-	STATE_EX_SETLEDS_2,
-	STATE_WRITE_CMD_BYTE,
-	STATE_WRITE_OUTPUT_PORT,
-	STATE_ECHO_MOUSE,
-	STATE_SETREP,
-	STATE_SEND_TO_MOUSE,
-} data_port_state = STATE_NORMAL;
-
-enum scancode_set_list {
-	SCANCODE_GET_SET = 0,
-	SCANCODE_SET_1,
-	SCANCODE_SET_2,
-	SCANCODE_SET_3,
-	SCANCODE_MAX = SCANCODE_SET_3,
-};
-
-#define MAX_SCAN_CODE_LEN 4
-
-/* Number of bytes host can get behind before we start generating extra IRQs */
-#define KB_TO_HOST_RETRIES 3
-
-/*
- * Mutex to control write access to the to-host buffer head.  Don't need to
- * mutex the tail because reads are only done in one place.
- */
-static mutex_t to_host_mutex;
-
-/* Queue command/data to the host */
-enum {
-	CHAN_KBD = 0,
-	CHAN_AUX,
-};
-struct data_byte {
-	uint8_t chan;
-	uint8_t byte;
-};
-
-static struct queue const to_host = QUEUE_NULL(16, struct data_byte);
-
-/* Queue command/data from the host */
-enum {
-	HOST_COMMAND = 0,
-	HOST_DATA,
-};
-struct host_byte {
-	uint8_t type;
-	uint8_t byte;
-};
-
-/*
- * The buffer for i8042 command from host. So far the largest command
- * we see from kernel is:
- *
- *   d1 -> i8042 (command)    # enable A20 in i8042_platform_init() of
- *   df -> i8042 (parameter)  # serio/i8042-x86ia64io.h file.
- *   ff -> i8042 (command)
- *   20 -> i8042 (command)    # read CTR
- *
- * Hence, 5 (actually 4 plus one spare) is large enough, but use 8 for safety.
- */
-static struct queue const from_host = QUEUE_NULL(8, struct host_byte);
-
-/* Queue aux data to the host from interrupt context. */
-static struct queue const aux_to_host_queue = QUEUE_NULL(16, uint8_t);
-
-static int i8042_keyboard_irq_enabled;
-static int i8042_aux_irq_enabled;
-
-/* i8042 global settings */
-static int keyboard_enabled;	/* default the keyboard is disabled. */
-static int aux_chan_enabled;	/* default the mouse is disabled. */
-static int keystroke_enabled;	/* output keystrokes */
-static uint8_t resend_command[MAX_SCAN_CODE_LEN];
-static uint8_t resend_command_len;
-static uint8_t controller_ram_address;
-static uint8_t controller_ram[0x20] = {
-	/* the so called "command byte" */
-	I8042_XLATE | I8042_AUX_DIS | I8042_KBD_DIS,
-	/* 0x01 - 0x1f are controller RAM */
-};
-static uint8_t A20_status;
-
-/*
- * Scancode settings
- */
-static enum scancode_set_list scancode_set = SCANCODE_SET_2;
-
-/*
- * Typematic delay, rate and counter variables.
- *
- *    7     6     5     4     3     2     1     0
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * |un-  |   delay   |     B     |        D        |
- * | used|  0     1  |  0     1  |  0     1     1  |
- * +-----+-----+-----+-----+-----+-----+-----+-----+
- * Formula:
- *   the inter-char delay = (2 ** B) * (D + 8) / 240 (sec)
- * Default: 500ms delay, 10.9 chars/sec.
- */
-#define DEFAULT_TYPEMATIC_VALUE (BIT(5) | BIT(3) | (3 << 0))
-static uint8_t typematic_value_from_host;
-static int typematic_first_delay;
-static int typematic_inter_delay;
-static int typematic_len;  /* length of typematic_scan_code */
-static uint8_t typematic_scan_code[MAX_SCAN_CODE_LEN];
-static timestamp_t typematic_deadline;
-
-#define KB_SYSJUMP_TAG 0x4b42  /* "KB" */
-#define KB_HOOK_VERSION 2
-/* the previous keyboard state before reboot_ec. */
-struct kb_state {
-	uint8_t codeset;
-	uint8_t ctlram;
-	uint8_t keystroke_enabled;
-};
-
-/*****************************************************************************/
-/* Keyboard event log */
-
-/* Log the traffic between EC and host -- for debug only */
-#define MAX_KBLOG 512  /* Max events in keyboard log */
-
-struct kblog_t {
-	/*
-	 * Type:
-	 *
-	 * s = byte enqueued to send to host
-	 * a = aux byte enqueued to send to host
-	 * t = to-host queue tail pointer before type='s' bytes enqueued
-	 *
-	 * d = data byte from host
-	 * c = command byte from host
-	 *
-	 * k = to-host queue head pointer before byte dequeued
-	 * K = byte actually sent to host via LPC
-	 * A = byte actually sent to host via LPC as AUX
-	 *
-	 * x = to_host queue was cleared
-	 *
-	 * The to-host head and tail pointers are logged pre-wrapping to the
-	 * queue size.  This means that they continually increment as units
-	 * are dequeued and enqueued respectively.  Since only the bottom
-	 * byte of the value is logged they will wrap every 256 units.
-	 */
-	uint8_t type;
-	uint8_t byte;
-};
-
-static struct kblog_t *kblog_buf;	/* Log buffer; NULL if not logging */
-static int kblog_len;			/* Current log length */
-
-/**
- * Add event to keyboard log.
- */
-static void kblog_put(char type, uint8_t byte)
-{
-	if (kblog_buf && kblog_len < MAX_KBLOG) {
-		kblog_buf[kblog_len].type = type;
-		kblog_buf[kblog_len].byte = byte;
-		kblog_len++;
-	}
-}
-
-/*****************************************************************************/
-
-void keyboard_host_write(int data, int is_cmd)
-{
-	struct host_byte h;
-
-	h.type = is_cmd ? HOST_COMMAND : HOST_DATA;
-	h.byte = data;
-	queue_add_unit(&from_host, &h);
-	task_wake(TASK_ID_KEYPROTO);
-}
-
-/**
- * Enable keyboard IRQ generation.
- *
- * @param enable	Enable (!=0) or disable (0) IRQ generation.
- */
-static void keyboard_enable_irq(int enable)
-{
-	CPRINTS("KB IRQ %s", enable ? "enable" : "disable");
-
-	i8042_keyboard_irq_enabled = enable;
-	if (enable)
-		lpc_keyboard_resume_irq();
-}
-
-/**
- * Enable mouse IRQ generation.
- *
- * @param enable	Enable (!=0) or disable (0) IRQ generation.
- */
-static void aux_enable_irq(int enable)
-{
-	CPRINTS("AUX IRQ %s", enable ? "enable" : "disable");
-
-	i8042_aux_irq_enabled = enable;
-}
-
-/**
- * Send a scan code to the host.
- *
- * The EC lib will push the scan code bytes to host via port 0x60 and assert
- * the IBF flag to trigger an interrupt.  The EC lib must queue them if the
- * host cannot read the previous byte away in time.
- *
- * @param len		Number of bytes to send to the host
- * @param to_host	Data to send
- * @param chan		Channel to send data on
- */
-static void i8042_send_to_host(int len, const uint8_t *bytes,
-			       uint8_t chan)
-{
-	int i;
-	struct data_byte data;
-
-	/* Enqueue output data if there's space */
-	mutex_lock(&to_host_mutex);
-
-	for (i = 0; i < len; i++)
-		kblog_put(chan == CHAN_AUX ? 'a' : 's', bytes[i]);
-
-	if (queue_space(&to_host) >= len) {
-		kblog_put('t', to_host.state->tail);
-		for (i = 0; i < len; i++) {
-			data.chan = chan;
-			data.byte = bytes[i];
-			queue_add_unit(&to_host, &data);
-		}
-	}
-	mutex_unlock(&to_host_mutex);
-
-	/* Wake up the task to move from queue to host */
-	task_wake(TASK_ID_KEYPROTO);
-}
-
-/* Change to set 1 if the I8042_XLATE flag is set. */
-static enum scancode_set_list acting_code_set(enum scancode_set_list set)
-{
-	/* Always generate set 1 if keyboard translation is enabled */
-	if (controller_ram[0] & I8042_XLATE)
-		return SCANCODE_SET_1;
-
-	return set;
-}
-
-static int is_supported_code_set(enum scancode_set_list set)
-{
-	return (set == SCANCODE_SET_1 || set == SCANCODE_SET_2);
-}
-
-/**
- * Return the make or break code bytes for the active scancode set.
- *
- * @param make_code	The make code to generate the make or break code from
- * @param pressed	Whether the key or button was pressed
- * @param code_set	The scancode set being used
- * @param scan_code	An array of bytes to store the make or break code in
- * @param len		The number of valid bytes to send in scan_code
- */
-static void scancode_bytes(uint16_t make_code, int8_t pressed,
-			   enum scancode_set_list code_set, uint8_t *scan_code,
-			   int32_t *len)
-{
-	*len = 0;
-
-	/* Output the make code (from table) */
-	if (make_code >= 0x0100) {
-		scan_code[(*len)++] = make_code >> 8;
-		make_code &= 0xff;
-	}
-
-	switch (code_set) {
-	case SCANCODE_SET_1:
-		make_code = scancode_translate_set2_to_1(make_code);
-		scan_code[(*len)++] = pressed ? make_code : (make_code | 0x80);
-		break;
-
-	case SCANCODE_SET_2:
-		if (pressed) {
-			scan_code[(*len)++] = make_code;
-		} else {
-			scan_code[(*len)++] = 0xf0;
-			scan_code[(*len)++] = make_code;
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-static enum ec_error_list matrix_callback(int8_t row, int8_t col,
-					  int8_t pressed,
-					  enum scancode_set_list code_set,
-					  uint8_t *scan_code, int32_t *len)
-{
-	uint16_t make_code;
-
-	ASSERT(scan_code);
-	ASSERT(len);
-
-	if (row >= KEYBOARD_ROWS || col >= keyboard_cols)
-		return EC_ERROR_INVAL;
-
-	make_code = get_scancode_set2(row, col);
-
-#ifdef CONFIG_KEYBOARD_SCANCODE_CALLBACK
-	{
-		enum ec_error_list r = keyboard_scancode_callback(
-				&make_code, pressed);
-		if (r != EC_SUCCESS)
-			return r;
-	}
-#endif
-
-	code_set = acting_code_set(code_set);
-	if (!is_supported_code_set(code_set)) {
-		CPRINTS("KB scancode set %d unsupported", code_set);
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	if (!make_code) {
-		CPRINTS("KB scancode %d:%d missing", row, col);
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	scancode_bytes(make_code, pressed, code_set, scan_code, len);
-	return EC_SUCCESS;
-}
-
-/**
- * Set typematic delays based on host data byte.
- */
-static void set_typematic_delays(uint8_t data)
-{
-	typematic_value_from_host = data;
-	typematic_first_delay = MSEC *
-		(((typematic_value_from_host & 0x60) >> 5) + 1) * 250;
-	typematic_inter_delay = SECOND *
-		(1 << ((typematic_value_from_host & 0x18) >> 3)) *
-		((typematic_value_from_host & 0x7) + 8) / 240;
-}
-
-static void reset_rate_and_delay(void)
-{
-	set_typematic_delays(DEFAULT_TYPEMATIC_VALUE);
-}
-
-void keyboard_clear_buffer(void)
-{
-	CPRINTS("KB Clear Buffer");
-	mutex_lock(&to_host_mutex);
-	kblog_put('x', queue_count(&to_host));
-	queue_init(&to_host);
-	mutex_unlock(&to_host_mutex);
-	lpc_keyboard_clear_buffer();
-}
-
-static void keyboard_wakeup(void)
-{
-	host_set_single_event(EC_HOST_EVENT_KEY_PRESSED);
-}
-
-static void set_typematic_key(const uint8_t *scan_code, int32_t len)
-{
-	typematic_deadline.val = get_time().val + typematic_first_delay;
-	memcpy(typematic_scan_code, scan_code, len);
-	typematic_len = len;
-}
-
-void clear_typematic_key(void)
-{
-	typematic_len = 0;
-}
-
-void keyboard_state_changed(int row, int col, int is_pressed)
-{
-	uint8_t scan_code[MAX_SCAN_CODE_LEN];
-	int32_t len = 0;
-	enum ec_error_list ret;
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-	char mylabel = get_keycap_label(row, col);
-
-	if (mylabel & KEYCAP_LONG_LABEL_BIT)
-		CPRINTS("KB (%d,%d)=%d %s", row, col, is_pressed,
-			get_keycap_long_label(mylabel & KEYCAP_LONG_LABEL_INDEX_BITMASK));
-	else
-		CPRINTS("KB (%d,%d)=%d %c", row, col, is_pressed, mylabel);
-#endif
-
-	ret = matrix_callback(row, col, is_pressed, scancode_set, scan_code,
-			      &len);
-	if (ret == EC_SUCCESS) {
-		ASSERT(len > 0);
-		if (keystroke_enabled)
-			i8042_send_to_host(len, scan_code, CHAN_KBD);
-	}
-
-	if (is_pressed) {
-		keyboard_wakeup();
-		set_typematic_key(scan_code, len);
-		task_wake(TASK_ID_KEYPROTO);
-	} else {
-		clear_typematic_key();
-	}
-}
-
-static void keystroke_enable(int enable)
-{
-	if (!keystroke_enabled && enable)
-		CPRINTS("KS enable");
-	else if (keystroke_enabled && !enable)
-		CPRINTS("KS disable");
-
-	keystroke_enabled = enable;
-}
-
-static void keyboard_enable(int enable)
-{
-	if (!keyboard_enabled && enable)
-		CPRINTS("KB enable");
-	else if (keyboard_enabled && !enable)
-		CPRINTS("KB disable");
-
-	keyboard_enabled = enable;
-}
-
-static void aux_enable(int enable)
-{
-	if (!aux_chan_enabled && enable)
-		CPRINTS("AUX enabled");
-	else if (aux_chan_enabled && !enable)
-		CPRINTS("AUX disabled");
-
-	aux_chan_enabled = enable;
-}
-
-static uint8_t read_ctl_ram(uint8_t addr)
-{
-	if (addr < ARRAY_SIZE(controller_ram))
-		return controller_ram[addr];
-	else
-		return 0;
-}
-
-/**
- * Manipulate the controller_ram[].
- *
- * Some bits change may trigger internal state change.
- */
-static void update_ctl_ram(uint8_t addr, uint8_t data)
-{
-	uint8_t orig;
-
-	if (addr >= ARRAY_SIZE(controller_ram))
-		return;
-
-	orig = controller_ram[addr];
-	controller_ram[addr] = data;
-	CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)",
-		 addr, data, orig);
-
-	if (addr == 0x00) {
-		/* Keyboard enable/disable */
-
-		/* Enable IRQ before enable keyboard (queue chars to host) */
-		if (!(orig & I8042_ENIRQ1) && (data & I8042_ENIRQ1))
-			keyboard_enable_irq(1);
-		if (!(orig & I8042_ENIRQ12) && (data & I8042_ENIRQ12))
-			aux_enable_irq(1);
-
-		/* Handle the I8042_KBD_DIS bit */
-		keyboard_enable(!(data & I8042_KBD_DIS));
-
-		/* Handle the I8042_AUX_DIS bit */
-		aux_enable(!(data & I8042_AUX_DIS));
-
-		/*
-		 * Disable IRQ after disable keyboard so that every char must
-		 * have informed the host.
-		 */
-		if ((orig & I8042_ENIRQ1) && !(data & I8042_ENIRQ1))
-			keyboard_enable_irq(0);
-		if ((orig & I8042_ENIRQ12) && !(data & I8042_ENIRQ12))
-			aux_enable_irq(0);
-	}
-}
-
-/**
- * Handle the port 0x60 writes from host.
- *
- * Returns 1 if the event was handled.
- */
-static int handle_mouse_data(uint8_t data, uint8_t *output, int *count)
-{
-	int out_len = 0;
-
-	switch (data_port_state) {
-	case STATE_ECHO_MOUSE:
-		CPRINTS5("STATE_ECHO_MOUSE: 0x%02x", data);
-		output[out_len++] = data;
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_SEND_TO_MOUSE:
-		CPRINTS5("STATE_SEND_TO_MOUSE: 0x%02x", data);
-		send_aux_data_to_device(data);
-		data_port_state = STATE_NORMAL;
-		break;
-
-	default:  /* STATE_NORMAL */
-		return 0;
-	}
-
-	ASSERT(out_len <= MAX_SCAN_CODE_LEN);
-
-	*count = out_len;
-
-	return 1;
-}
-
-/**
- * Handle the port 0x60 writes from host.
- *
- * This functions returns the number of bytes stored in *output buffer.
- */
-static int handle_keyboard_data(uint8_t data, uint8_t *output)
-{
-	int out_len = 0;
-	int save_for_resend = 1;
-	int i;
-
-	switch (data_port_state) {
-	case STATE_SCANCODE:
-		CPRINTS5("KB eaten by STATE_SCANCODE: 0x%02x", data);
-		if (data == SCANCODE_GET_SET) {
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = scancode_set;
-		} else {
-			scancode_set = data;
-			CPRINTS("KB scancode set to %d", scancode_set);
-			output[out_len++] = I8042_RET_ACK;
-		}
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_SETLEDS:
-		CPRINTS5("KB eaten by STATE_SETLEDS");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_EX_SETLEDS_1:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_1");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_EX_SETLEDS_2;
-		break;
-
-	case STATE_EX_SETLEDS_2:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_2");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_WRITE_CMD_BYTE:
-		CPRINTS5("KB eaten by STATE_WRITE_CMD_BYTE: 0x%02x",
-			 data);
-		update_ctl_ram(controller_ram_address, data);
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_WRITE_OUTPUT_PORT:
-		CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x",
-			 data);
-		A20_status = (data & BIT(1)) ? 1 : 0;
-		data_port_state = STATE_NORMAL;
-		break;
-
-	case STATE_SETREP:
-		CPRINTS5("KB eaten by STATE_SETREP: 0x%02x", data);
-		set_typematic_delays(data);
-
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
-		break;
-
-	default:  /* STATE_NORMAL */
-		switch (data) {
-		case I8042_CMD_GSCANSET:  /* also I8042_CMD_SSCANSET */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SCANCODE;
-			break;
-
-		case I8042_CMD_SETLEDS:
-			/* Chrome OS doesn't have keyboard LEDs, so ignore */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETLEDS;
-			break;
-
-		case I8042_CMD_EX_SETLEDS:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_EX_SETLEDS_1;
-			break;
-
-		case I8042_CMD_DIAG_ECHO:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = I8042_CMD_DIAG_ECHO;
-			break;
-
-		case I8042_CMD_GETID:    /* fall-thru */
-		case I8042_CMD_OK_GETID:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = 0xab;  /* Regular keyboards */
-			output[out_len++] = 0x83;
-			break;
-
-		case I8042_CMD_SETREP:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETREP;
-			break;
-
-		case I8042_CMD_ENABLE:
-			output[out_len++] = I8042_RET_ACK;
-			keystroke_enable(1);
-			keyboard_clear_buffer();
-			break;
-
-		case I8042_CMD_RESET_DIS:
-			output[out_len++] = I8042_RET_ACK;
-			keystroke_enable(0);
-			reset_rate_and_delay();
-			keyboard_clear_buffer();
-			break;
-
-		case I8042_CMD_RESET_DEF:
-			output[out_len++] = I8042_RET_ACK;
-			reset_rate_and_delay();
-			keyboard_clear_buffer();
-			break;
-
-		case I8042_CMD_RESET:
-			reset_rate_and_delay();
-			keyboard_clear_buffer();
-			output[out_len++] = I8042_RET_ACK;
-			break;
-
-		case I8042_CMD_RESEND:
-			save_for_resend = 0;
-			for (i = 0; i < resend_command_len; ++i)
-				output[out_len++] = resend_command[i];
-			break;
-
-		case 0x60: /* fall-thru */
-		case 0x45:
-			/* U-boot hack.  Just ignore; don't reply. */
-			break;
-
-		case I8042_CMD_SETALL_MB:  /* fall-thru */
-		case I8042_CMD_SETALL_MBR:
-		case I8042_CMD_EX_ENABLE:
-		default:
-			output[out_len++] = I8042_RET_NAK;
-			CPRINTS("KB Unsupported i8042 data 0x%02x",
-				data);
-			break;
-		}
-	}
-
-	/* For resend, keep output before leaving. */
-	if (out_len && save_for_resend) {
-		ASSERT(out_len <= MAX_SCAN_CODE_LEN);
-		for (i = 0; i < out_len; ++i)
-			resend_command[i] = output[i];
-		resend_command_len = out_len;
-	}
-
-	ASSERT(out_len <= MAX_SCAN_CODE_LEN);
-	return out_len;
-}
-
-/**
- * Handle the port 0x64 writes from host.
- *
- * This functions returns the number of bytes stored in *output buffer.
- * BUT those bytes will appear at port 0x60.
- */
-static int handle_keyboard_command(uint8_t command, uint8_t *output)
-{
-	int out_len = 0;
-
-	CPRINTS5("KB recv cmd: 0x%02x", command);
-	kblog_put('c', command);
-
-	switch (command) {
-	case I8042_READ_CMD_BYTE:
-		/*
-		 * Ensure that the keyboard buffer is cleared before adding
-		 * command byte to it. Since the host is asking for command
-		 * byte, sending it buffered key press data can confuse the
-		 * host and result in it taking incorrect action.
-		 */
-		keyboard_clear_buffer();
-		output[out_len++] = read_ctl_ram(0);
-		break;
-
-	case I8042_WRITE_CMD_BYTE:
-		data_port_state = STATE_WRITE_CMD_BYTE;
-		controller_ram_address = command - 0x60;
-		break;
-
-	case I8042_DIS_KB:
-		update_ctl_ram(0, read_ctl_ram(0) | I8042_KBD_DIS);
-		reset_rate_and_delay();
-		typematic_len = 0;  /* stop typematic */
-		keyboard_clear_buffer();
-		break;
-
-	case I8042_ENA_KB:
-		update_ctl_ram(0, read_ctl_ram(0) & ~I8042_KBD_DIS);
-		keystroke_enable(1);
-		keyboard_clear_buffer();
-		break;
-
-	case I8042_READ_OUTPUT_PORT:
-		output[out_len++] =
-			(lpc_keyboard_input_pending() ? BIT(5) : 0) |
-			(lpc_keyboard_has_char() ? BIT(4) : 0) |
-			(A20_status ? BIT(1) : 0) |
-			1;  /* Main processor in normal mode */
-		break;
-
-	case I8042_WRITE_OUTPUT_PORT:
-		data_port_state = STATE_WRITE_OUTPUT_PORT;
-		break;
-
-	case I8042_RESET_SELF_TEST:
-		output[out_len++] = 0x55;  /* Self test success */
-		break;
-
-	case I8042_TEST_KB_PORT:
-		output[out_len++] = 0x00;
-		break;
-
-	case I8042_DIS_MOUSE:
-		update_ctl_ram(0, read_ctl_ram(0) | I8042_AUX_DIS);
-		break;
-
-	case I8042_ENA_MOUSE:
-		update_ctl_ram(0, read_ctl_ram(0) & ~I8042_AUX_DIS);
-		break;
-
-	case I8042_TEST_MOUSE:
-		output[out_len++] = 0;  /* No error detected */
-		break;
-
-	case I8042_ECHO_MOUSE:
-		data_port_state = STATE_ECHO_MOUSE;
-		break;
-
-	case I8042_SEND_TO_MOUSE:
-		data_port_state = STATE_SEND_TO_MOUSE;
-		break;
-
-	case I8042_SYSTEM_RESET:
-		chipset_reset(CHIPSET_RESET_KB_SYSRESET);
-		break;
-
-	default:
-		if (command >= I8042_READ_CTL_RAM &&
-		    command <= I8042_READ_CTL_RAM_END) {
-			output[out_len++] = read_ctl_ram(command - 0x20);
-		} else if (command >= I8042_WRITE_CTL_RAM &&
-			   command <= I8042_WRITE_CTL_RAM_END) {
-			data_port_state = STATE_WRITE_CMD_BYTE;
-			controller_ram_address = command - 0x60;
-		} else if (command == I8042_DISABLE_A20) {
-			A20_status = 0;
-		} else if (command == I8042_ENABLE_A20) {
-			A20_status = 1;
-		} else if (command >= I8042_PULSE_START &&
-			   command <= I8042_PULSE_END) {
-			/* Pulse Output Bits,
-			 *   b0=0 to reset CPU, see I8042_SYSTEM_RESET above
-			 *   b1=0 to disable A20 line
-			 */
-			A20_status = command & BIT(1) ? 1 : 0;
-		} else {
-			CPRINTS("KB unsupported cmd: 0x%02x", command);
-			reset_rate_and_delay();
-			keyboard_clear_buffer();
-			output[out_len++] = I8042_RET_NAK;
-			data_port_state = STATE_NORMAL;
-		}
-		break;
-	}
-
-	return out_len;
-}
-
-static void i8042_handle_from_host(void)
-{
-	struct host_byte h;
-	int ret_len;
-	uint8_t output[MAX_SCAN_CODE_LEN];
-	uint8_t chan = CHAN_KBD;
-
-	while (queue_remove_unit(&from_host, &h)) {
-		if (h.type == HOST_COMMAND) {
-			ret_len = handle_keyboard_command(h.byte, output);
-		} else {
-			CPRINTS5("KB recv data: 0x%02x", h.byte);
-			kblog_put('d', h.byte);
-
-			if (IS_ENABLED(CONFIG_8042_AUX) &&
-			    handle_mouse_data(h.byte, output, &ret_len))
-				chan = CHAN_AUX;
-			else
-				ret_len = handle_keyboard_data(h.byte, output);
-		}
-
-		i8042_send_to_host(ret_len, output, chan);
-	}
-}
-
-void keyboard_protocol_task(void *u)
-{
-	int wait = -1;
-	int retries = 0;
-
-	reset_rate_and_delay();
-
-	while (1) {
-		/* Wait for next host read/write */
-		task_wait_event(wait);
-
-		while (1) {
-			timestamp_t t = get_time();
-			struct data_byte entry;
-
-			/* Handle typematic */
-			if (!typematic_len) {
-				/* Typematic disabled; wait for enable */
-				wait = -1;
-			} else if (timestamp_expired(typematic_deadline, &t)) {
-				/* Ready for next typematic keystroke */
-				if (keystroke_enabled)
-					i8042_send_to_host(typematic_len,
-							   typematic_scan_code,
-							   CHAN_KBD);
-				typematic_deadline.val = t.val +
-					typematic_inter_delay;
-				wait = typematic_inter_delay;
-			} else {
-				/* Wait for remaining interval */
-				wait = typematic_deadline.val - t.val;
-			}
-
-			/* Handle command/data write from host */
-			i8042_handle_from_host();
-
-			/* Check if we have data to send to host */
-			if (queue_is_empty(&to_host))
-				break;
-
-			/* Handle data waiting for host */
-			if (lpc_keyboard_has_char()) {
-				/* If interrupts disabled, nothing we can do */
-				if (!i8042_keyboard_irq_enabled &&
-				    !i8042_aux_irq_enabled)
-					break;
-
-				/* Give the host a little longer to respond */
-				if (++retries < KB_TO_HOST_RETRIES)
-					break;
-
-				/*
-				 * We keep getting data, but the host keeps
-				 * ignoring us.  Fine, we're done waiting.
-				 * Hey, host, are you ever gonna get to this
-				 * data?  Send it another interrupt in case it
-				 * somehow missed the first one.
-				 */
-				CPRINTS("KB extra IRQ");
-				lpc_keyboard_resume_irq();
-				retries = 0;
-				break;
-			}
-
-			/* Get a char from buffer. */
-			kblog_put('k', to_host.state->head);
-			queue_remove_unit(&to_host, &entry);
-
-			/* Write to host. */
-			if (entry.chan == CHAN_AUX &&
-			    IS_ENABLED(CONFIG_8042_AUX)) {
-				kblog_put('A', entry.byte);
-				lpc_aux_put_char(entry.byte,
-						 i8042_aux_irq_enabled);
-			} else {
-				kblog_put('K', entry.byte);
-				lpc_keyboard_put_char(
-					entry.byte, i8042_keyboard_irq_enabled);
-			}
-			retries = 0;
-		}
-	}
-}
-
-static void send_aux_data_to_host_deferred(void)
-{
-	uint8_t data;
-
-	if (IS_ENABLED(CONFIG_DEVICE_EVENT) &&
-		chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		device_set_single_event(EC_DEVICE_EVENT_TRACKPAD);
-
-	while (!queue_is_empty(&aux_to_host_queue)) {
-		queue_remove_unit(&aux_to_host_queue, &data);
-		if (aux_chan_enabled && IS_ENABLED(CONFIG_8042_AUX))
-			i8042_send_to_host(1, &data, CHAN_AUX);
-		else
-			CPRINTS("AUX Callback ignored");
-	}
-}
-DECLARE_DEFERRED(send_aux_data_to_host_deferred);
-
-/**
- * Send aux data to host from interrupt context.
- *
- * @param data	Aux response to send to host.
- */
-void send_aux_data_to_host_interrupt(uint8_t data)
-{
-	queue_add_unit(&aux_to_host_queue, &data);
-	hook_call_deferred(&send_aux_data_to_host_deferred_data, 0);
-}
-
-/**
- * Handle button changing state.
- *
- * @param button	Type of button that changed
- * @param is_pressed	Whether the button was pressed or released
- */
-test_mockable void keyboard_update_button(enum keyboard_button_type button,
-					  int is_pressed)
-{
-	uint8_t scan_code[MAX_SCAN_CODE_LEN];
-	uint32_t len;
-	struct button_8042_t button_8042;
-	enum scancode_set_list code_set;
-
-	/*
-	 * Only send the scan code if main chipset is fully awake and
-	 * keystrokes are enabled.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_ON) || !keystroke_enabled)
-		return;
-
-	code_set = acting_code_set(scancode_set);
-	if (!is_supported_code_set(code_set))
-		return;
-
-	button_8042 = buttons_8042[button];
-	scancode_bytes(button_8042.scancode, is_pressed, code_set, scan_code,
-		       &len);
-	ASSERT(len > 0);
-
-	if (button_8042.repeat) {
-		if (is_pressed)
-			set_typematic_key(scan_code, len);
-		else
-			clear_typematic_key();
-	}
-
-	if (keystroke_enabled) {
-		i8042_send_to_host(len, scan_code, CHAN_KBD);
-		task_wake(TASK_ID_KEYPROTO);
-	}
-}
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_KEYBOARD
-static int command_typematic(int argc, char **argv)
-{
-	int i;
-
-	if (argc == 3) {
-		typematic_first_delay = strtoi(argv[1], NULL, 0) * MSEC;
-		typematic_inter_delay = strtoi(argv[2], NULL, 0) * MSEC;
-	}
-
-	ccprintf("From host:   0x%02x\n", typematic_value_from_host);
-	ccprintf("First delay: %3d ms\n", typematic_first_delay / 1000);
-	ccprintf("Inter delay: %3d ms\n", typematic_inter_delay / 1000);
-	ccprintf("Now:         %.6" PRId64 "\n", get_time().val);
-	ccprintf("Deadline:    %.6" PRId64 "\n", typematic_deadline.val);
-
-	ccputs("Repeat scan code: {");
-	for (i = 0; i < typematic_len; ++i)
-		ccprintf("0x%02x, ", typematic_scan_code[i]);
-	ccputs("}\n");
-	return EC_SUCCESS;
-}
-
-static int command_codeset(int argc, char **argv)
-{
-	if (argc == 2) {
-		int set = strtoi(argv[1], NULL, 0);
-		switch (set) {
-		case SCANCODE_SET_1:  /* fall-thru */
-		case SCANCODE_SET_2:  /* fall-thru */
-			scancode_set = set;
-			break;
-		default:
-			return EC_ERROR_PARAM1;
-		}
-	}
-
-	ccprintf("Set: %d\n", scancode_set);
-	ccprintf("I8042_XLATE: %d\n", controller_ram[0] & I8042_XLATE ? 1 : 0);
-	return EC_SUCCESS;
-}
-
-static int command_controller_ram(int argc, char **argv)
-{
-	int index;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	index = strtoi(argv[1], NULL, 0);
-	if (index >= ARRAY_SIZE(controller_ram))
-		return EC_ERROR_PARAM1;
-
-	if (argc >= 3)
-		update_ctl_ram(index, strtoi(argv[2], NULL, 0));
-
-	ccprintf("%d = 0x%02x\n", index, controller_ram[index]);
-	return EC_SUCCESS;
-}
-
-static int command_keyboard_log(int argc, char **argv)
-{
-	int i;
-
-	/* If no args, print log */
-	if (argc == 1) {
-		ccprintf("KBC log (len=%d):\n", kblog_len);
-		for (i = 0; kblog_buf && i < kblog_len; ++i) {
-			ccprintf("%c.%02x ",
-				 kblog_buf[i].type, kblog_buf[i].byte);
-			if ((i & 15) == 15) {
-				ccputs("\n");
-				cflush();
-			}
-		}
-		ccputs("\n");
-		return EC_SUCCESS;
-	}
-
-	/* Otherwise, enable/disable */
-	if (!parse_bool(argv[1], &i))
-		return EC_ERROR_PARAM1;
-
-	if (i) {
-		if (!kblog_buf) {
-			int rv = SHARED_MEM_ACQUIRE_CHECK(
-				sizeof(*kblog_buf) * MAX_KBLOG,
-				(char **)&kblog_buf);
-			if (rv != EC_SUCCESS)
-				kblog_buf = NULL;
-			kblog_len = 0;
-			return rv;
-		}
-	} else {
-		kblog_len = 0;
-		if (kblog_buf)
-			shared_mem_release(kblog_buf);
-		kblog_buf = NULL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int command_keyboard(int argc, char **argv)
-{
-	int ena;
-
-	if (argc > 1) {
-		if (!parse_bool(argv[1], &ena))
-			return EC_ERROR_PARAM1;
-
-		keyboard_enable(ena);
-	}
-
-	ccprintf("Enabled: %d\n", keyboard_enabled);
-	return EC_SUCCESS;
-}
-
-static int command_8042_internal(int argc, char **argv)
-{
-	int i;
-
-	ccprintf("data_port_state=%d\n", data_port_state);
-	ccprintf("i8042_keyboard_irq_enabled=%d\n", i8042_keyboard_irq_enabled);
-	ccprintf("i8042_aux_irq_enabled=%d\n", i8042_aux_irq_enabled);
-	ccprintf("keyboard_enabled=%d\n", keyboard_enabled);
-	ccprintf("keystroke_enabled=%d\n", keystroke_enabled);
-	ccprintf("aux_chan_enabled=%d\n", aux_chan_enabled);
-
-	ccprintf("resend_command[]={");
-	for (i = 0; i < resend_command_len; i++)
-		ccprintf("0x%02x, ", resend_command[i]);
-	ccprintf("}\n");
-
-	ccprintf("controller_ram_address=0x%02x\n", controller_ram_address);
-	ccprintf("A20_status=%d\n", A20_status);
-
-	ccprintf("from_host[]={");
-	for (i = 0; i < queue_count(&from_host); ++i) {
-		struct host_byte entry;
-
-		queue_peek_units(&from_host, &entry, i, 1);
-
-		ccprintf("0x%02x, 0x%02x, ", entry.type, entry.byte);
-	}
-	ccprintf("}\n");
-
-	ccprintf("to_host[]={");
-	for (i = 0; i < queue_count(&to_host); ++i) {
-		struct data_byte entry;
-
-		queue_peek_units(&to_host, &entry, i, 1);
-
-		ccprintf("0x%02x%s, ", entry.byte,
-			 entry.chan == CHAN_AUX ? " aux" : "");
-	}
-	ccprintf("}\n");
-
-	return EC_SUCCESS;
-}
-
-/* Zephyr only provides these as subcommands*/
-#ifndef CONFIG_ZEPHYR
-DECLARE_CONSOLE_COMMAND(typematic, command_typematic,
-			"[first] [inter]",
-			"Get/set typematic delays");
-DECLARE_CONSOLE_COMMAND(codeset, command_codeset,
-			"[set]",
-			"Get/set keyboard codeset");
-DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram,
-			"index [value]",
-			"Get/set keyboard controller RAM");
-DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log,
-			"[on | off]",
-			"Print or toggle keyboard event log");
-DECLARE_CONSOLE_COMMAND(kbd, command_keyboard,
-			"[on | off]",
-			"Print or toggle keyboard info");
-#endif
-
-static int command_8042(int argc, char **argv)
-{
-	if (argc >= 2) {
-		if (!strcasecmp(argv[1], "internal"))
-			return command_8042_internal(argc, argv);
-		else if (!strcasecmp(argv[1], "typematic"))
-			return command_typematic(argc - 1, argv + 1);
-		else if (!strcasecmp(argv[1], "codeset"))
-			return command_codeset(argc - 1, argv + 1);
-		else if (!strcasecmp(argv[1], "ctrlram"))
-			return command_controller_ram(argc - 1, argv + 1);
-		else if (CMD_KEYBOARD_LOG && !strcasecmp(argv[1], "kblog"))
-			return command_keyboard_log(argc - 1, argv + 1);
-		else if (!strcasecmp(argv[1], "kbd"))
-			return command_keyboard(argc - 1, argv + 1);
-		else
-			return EC_ERROR_PARAM1;
-	} else {
-		char *ctlram_argv[] = {"ctrlram", "0"};
-
-		ccprintf("\n- Typematic:\n");
-		command_typematic(argc, argv);
-		ccprintf("\n- Codeset:\n");
-		command_codeset(argc, argv);
-		ccprintf("\n- Control RAM:\n");
-		command_controller_ram(
-			sizeof(ctlram_argv) / sizeof(ctlram_argv[0]),
-			ctlram_argv);
-		if (CMD_KEYBOARD_LOG) {
-			ccprintf("\n- Keyboard log:\n");
-			command_keyboard_log(argc, argv);
-		}
-		ccprintf("\n- Keyboard:\n");
-		command_keyboard(argc, argv);
-		ccprintf("\n- Internal:\n");
-		command_8042_internal(argc, argv);
-		ccprintf("\n");
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(8042, command_8042,
-			"[internal | typematic | codeset | ctrlram |"
-			" kblog | kbd]",
-			"Print 8042 state in one place");
-#endif
-
-
-/*****************************************************************************/
-/* Hooks */
-
-/**
- * Preserve the states of keyboard controller to keep the initialized states
- * between reboot_ec commands. Saving info include:
- *
- *   - code set
- *   - controller_ram[0]:
- *     - XLATE
- *     - KB/TP disabled
- *     - KB/TP IRQ enabled
- */
-static void keyboard_preserve_state(void)
-{
-	struct kb_state state;
-
-	state.codeset = scancode_set;
-	state.ctlram = controller_ram[0];
-	state.keystroke_enabled = keystroke_enabled;
-
-	system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION,
-			    sizeof(state), &state);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, keyboard_preserve_state, HOOK_PRIO_DEFAULT);
-
-/**
- * Restore the keyboard states after reboot_ec command. See above function.
- */
-static void keyboard_restore_state(void)
-{
-	const struct kb_state *prev;
-	int version, size;
-
-	prev = (const struct kb_state *)system_get_jump_tag(KB_SYSJUMP_TAG,
-							    &version, &size);
-	if (prev && version == KB_HOOK_VERSION && size == sizeof(*prev)) {
-		/* Coming back from a sysjump, so restore settings. */
-		scancode_set = prev->codeset;
-		update_ctl_ram(0, prev->ctlram);
-		keystroke_enabled = prev->keystroke_enabled;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, keyboard_restore_state, HOOK_PRIO_DEFAULT);
-
-#if defined(CONFIG_POWER_BUTTON) && !defined(CONFIG_MKBP_INPUT_DEVICES)
-/**
- * Handle power button changing state.
- */
-static void keyboard_power_button(void)
-{
-	keyboard_update_button(KEYBOARD_BUTTON_POWER,
-			       power_button_is_pressed());
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
-	     HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_POWER_BUTTON && !CONFIG_MKBP_INPUT_DEVICES */
-
diff --git a/common/keyboard_8042_sharedlib.c b/common/keyboard_8042_sharedlib.c
deleted file mode 100644
index 1d024d3f47..0000000000
--- a/common/keyboard_8042_sharedlib.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Objects which can be shared between RO and RW for 8042 keyboard protocol.
- */
-
-#include "button.h"
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "libsharedobjs.h"
-#include "util.h"
-
-#ifndef CONFIG_KEYBOARD_CUSTOMIZATION
-/* The standard Chrome OS keyboard matrix table in scan code set 2. */
-static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000},
-	{0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015},
-	{0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024},
-	{0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d},
-	{0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d},
-	{0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043},
-	{0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c},
-	{0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059},
-	{0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d},
-	{0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044},
-	{0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000},
-#ifndef CONFIG_KEYBOARD_KEYPAD
-	{0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b},
-#else
-	{0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b},
-	{0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070},
-	{0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a},
-#endif
-};
-
-uint16_t get_scancode_set2(uint8_t row, uint8_t col)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		return scancode_set2[col][row];
-	return 0;
-}
-
-void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		scancode_set2[col][row] = val;
-}
-
-#endif /* CONFIG_KEYBOARD_CUSTOMIZATION */
-
-/*
- * The translation table from scan code set 2 to set 1.
- * Ref: http://kbd-project.org/docs/scancodes/scancodes-10.html#ss10.3
- * To reduce space, we only keep the translation for 0~127,
- * so a real translation need to do 0x83=>0x41 explicitly (
- * see scancode_translate_set2_to_1 below).
- */
-SHAREDLIB(const uint8_t scancode_translate_table[128] = {
-	0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
-	0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59,
-	0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a,
-	0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b,
-	0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
-	0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d,
-	0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e,
-	0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f,
-	0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60,
-	0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
-	0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e,
-	0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76,
-	0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b,
-	0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f,
-	0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
-	0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
-});
-
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-SHAREDLIB(const
-static char * const keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = {
-	"UNKNOWN", "F1",    "F2",    "F3",
-	"F4",      "F5",    "F6",    "F7",
-	"F8",      "F9",    "F10",   "F11",
-	"F12",     "F13",   "F14",   "F15",
-	"L-ALT",   "R-ALT", "L-CTR", "R-CTR",
-	"L-SHT",   "R-SHT", "ENTER", "SPACE",
-	"B-SPC",   "TAB",   "SEARC", "LEFT",
-	"RIGHT",   "DOWN",  "UP",    "ESC",
-});
-
-const char *get_keycap_long_label(uint8_t idx)
-{
-	if (idx < ARRAY_SIZE(keycap_long_label))
-		return keycap_long_label[idx];
-	return "UNKNOWN";
-}
-
-#ifndef CONFIG_KEYBOARD_CUSTOMIZATION
-static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC,
-			KLLI_R_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_F11,   KLLI_ESC,   KLLI_TAB,   '~',
-			'a',        'z',        '1',        'q'},
-	{KLLI_F1,    KLLI_F4,    KLLI_F3,    KLLI_F2,
-			'd',        'c',        '3',        'e'},
-	{'b',        'g',        't',        '5',
-			'f',        'v',        '4',        'r'},
-	{KLLI_F10,   KLLI_F7,    KLLI_F6,    KLLI_F5,
-			's',        'x',        '2',        'w'},
-	{KLLI_UNKNO, KLLI_F12,   ']',        KLLI_F13,
-			'k',        ',',        '8',        'i'},
-	{'n',        'h',        'y',        '6',
-			'j',        'm',        '7',        'u'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT},
-	{'=',        '\'',       '[',        '-',
-			';',        '/',        '0',        'p'},
-	{KLLI_F14,   KLLI_F9,    KLLI_F8,    KLLI_UNKNO,
-			'|',        '.',        '9',        'o'},
-	{KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO},
-	{KLLI_F15,   KLLI_B_SPC, KLLI_UNKNO, '\\',
-			KLLI_ENTER, KLLI_SPACE, KLLI_DOWN,  KLLI_UP},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT},
-#ifdef CONFIG_KEYBOARD_KEYPAD
-	/* TODO: Populate these */
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-#endif
-};
-
-char get_keycap_label(uint8_t row, uint8_t col)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		return keycap_label[col][row];
-	return KLLI_UNKNO;
-}
-
-void set_keycap_label(uint8_t row, uint8_t col, char val)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
-		keycap_label[col][row] = val;
-}
-#endif /* CONFIG_KEYBOARD_CUSTOMIZATION */
-#endif /* CONFIG_KEYBOARD_DEBUG */
-
-uint8_t scancode_translate_set2_to_1(uint8_t code)
-{
-	if (code & 0x80) {
-		if (code == 0x83)
-			return 0x41;
-		return code;
-	}
-	return scancode_translate_table[code];
-}
-
-/*
- * Button scan codes.
- * Must be in the same order as defined in keyboard_button_type.
- */
-SHAREDLIB(const struct button_8042_t buttons_8042[] = {
-	{SCANCODE_POWER, 0},
-	{SCANCODE_VOLUME_DOWN, 1},
-	{SCANCODE_VOLUME_UP, 1},
-	{SCANCODE_1, 1},
-	{SCANCODE_2, 1},
-	{SCANCODE_3, 1},
-	{SCANCODE_4, 1},
-	{SCANCODE_5, 1},
-	{SCANCODE_6, 1},
-	{SCANCODE_7, 1},
-	{SCANCODE_8, 1},
-});
-BUILD_ASSERT(ARRAY_SIZE(buttons_8042) == KEYBOARD_BUTTON_COUNT);
diff --git a/common/keyboard_backlight.c b/common/keyboard_backlight.c
deleted file mode 100644
index 82312e0776..0000000000
--- a/common/keyboard_backlight.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_backlight.h"
-#include "lid_switch.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-static struct kblight_conf kblight;
-static int current_percent;
-
-void __attribute__((weak)) board_kblight_init(void)
-{ }
-
-static int kblight_init(void)
-{
-	if (!kblight.drv || !kblight.drv->init)
-		return EC_ERROR_UNIMPLEMENTED;
-	return kblight.drv->init();
-}
-
-static void kblight_set_deferred(void)
-{
-	if (!kblight.drv || !kblight.drv->set)
-		return;
-	kblight.drv->set(current_percent);
-}
-DECLARE_DEFERRED(kblight_set_deferred);
-
-/*
- * APIs
- */
-int kblight_set(int percent)
-{
-	if (percent < 0 || 100 < percent)
-		return EC_ERROR_INVAL;
-	current_percent = percent;
-	/* Need to defer i2c in case it's called from an interrupt handler. */
-	hook_call_deferred(&kblight_set_deferred_data, 0);
-	return EC_SUCCESS;
-}
-
-int kblight_get(void)
-{
-	return current_percent;
-}
-
-int kblight_enable(int enable)
-{
-#ifdef GPIO_EN_KEYBOARD_BACKLIGHT
-	gpio_set_level(GPIO_EN_KEYBOARD_BACKLIGHT, enable);
-#endif
-	if (!kblight.drv || !kblight.drv->enable)
-		return -1;
-	return kblight.drv->enable(enable);
-}
-
-int kblight_register(const struct kblight_drv *drv)
-{
-	kblight.drv = drv;
-	CPRINTS("kblight registered");
-	return EC_SUCCESS;
-}
-
-/*
- * Hooks
- */
-static void keyboard_backlight_init(void)
-{
-	/* Uses PWM by default. Can be customized by board_kblight_init */
-#ifdef CONFIG_PWM_KBLIGHT
-	kblight_register(&kblight_pwm);
-#endif
-	board_kblight_init();
-	if (kblight_init())
-		CPRINTS("kblight init failed");
-	/* Don't leave kblight enable state undetermined */
-	kblight_enable(0);
-}
-DECLARE_HOOK(HOOK_INIT, keyboard_backlight_init, HOOK_PRIO_DEFAULT);
-
-static void kblight_suspend(void)
-{
-	kblight_enable(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kblight_suspend, HOOK_PRIO_DEFAULT);
-
-static void kblight_resume(void)
-{
-	if (lid_is_open() && current_percent) {
-		kblight_enable(1);
-		kblight_set(current_percent);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, kblight_resume, HOOK_PRIO_DEFAULT);
-
-static void kblight_lid_change(void)
-{
-	kblight_enable(lid_is_open() && current_percent);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, kblight_lid_change, HOOK_PRIO_DEFAULT);
-
-/*
- * Console and host commands
- */
-static int cc_kblight(int argc, char **argv)
-{
-	if (argc >= 2) {
-		char *e;
-		int i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-		if (kblight_set(i))
-			return EC_ERROR_PARAM1;
-		if (kblight_enable(i > 0))
-			return EC_ERROR_PARAM1;
-	}
-	ccprintf("Keyboard backlight: %d%%\n", kblight_get());
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(kblight, cc_kblight,
-			"percent",
-			"Get/set keyboard backlight");
-
-enum ec_status hc_get_keyboard_backlight(struct host_cmd_handler_args *args)
-{
-	struct ec_response_pwm_get_keyboard_backlight *r = args->response;
-
-	r->percent = kblight_get();
-	r->enabled = 1;			/* Deprecated */
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT,
-		     hc_get_keyboard_backlight,
-		     EC_VER_MASK(0));
-
-enum ec_status hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_keyboard_backlight *p = args->params;
-
-	if (kblight_set(p->percent))
-		return EC_RES_ERROR;
-	if (kblight_enable(p->percent > 0))
-		return EC_RES_ERROR;
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT,
-		     hc_set_keyboard_backlight,
-		     EC_VER_MASK(0));
diff --git a/common/keyboard_mkbp.c b/common/keyboard_mkbp.c
deleted file mode 100644
index d8e9f8d909..0000000000
--- a/common/keyboard_mkbp.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MKBP keyboard protocol
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "host_command.h"
-#include "keyboard_config.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_protocol.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "keyboard_test.h"
-#include "mkbp_event.h"
-#include "mkbp_fifo.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-/* Changes to col,row here need to also be reflected in kernel.
- * drivers/input/mkbp.c ... see KEY_BATTERY.
- */
-#define BATTERY_KEY_COL 0
-#define BATTERY_KEY_ROW 7
-#define BATTERY_KEY_ROW_MASK BIT(BATTERY_KEY_ROW)
-
-#ifndef HAS_TASK_KEYSCAN
-#error "Task KEYSCAN has to be enabled for MKBP keyboard"
-#endif /* !defined(HAS_TASK_KEYSCAN) */
-
-/* Config for mkbp protocol; does not include fields from scan config */
-struct ec_mkbp_protocol_config {
-	uint32_t valid_mask;	/* valid fields */
-	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
-	uint8_t valid_flags;	/* which flags are valid */
-
-	/* maximum depth to allow for fifo (0 = no keyscan output) */
-	uint8_t fifo_max_depth;
-} __packed;
-
-static struct ec_mkbp_protocol_config config = {
-	.valid_mask = EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT |
-		EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
-		EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN |
-		EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH,
-	.valid_flags = EC_MKBP_FLAGS_ENABLE,
-	.flags = EC_MKBP_FLAGS_ENABLE,
-	.fifo_max_depth = FIFO_DEPTH,
-};
-
-/*****************************************************************************/
-/* Interface */
-
-void keyboard_clear_buffer(void)
-{
-	mkbp_fifo_clear_keyboard();
-}
-
-test_mockable int mkbp_keyboard_add(const uint8_t *buffp)
-{
-	/*
-	 * If the keyboard protocol is not enabled, don't save the state to
-	 * the FIFO or trigger an interrupt.
-	 */
-	if (!(config.flags & EC_MKBP_FLAGS_ENABLE))
-		return EC_SUCCESS;
-
-	return mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, buffp);
-}
-
-static int keyboard_get_next_event(uint8_t *out)
-{
-	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_KEY_MATRIX, keyboard_get_next_event);
-
-void keyboard_send_battery_key(void)
-{
-	uint8_t state[KEYBOARD_COLS_MAX];
-
-	/* Copy debounced state and add battery pseudo-key */
-	memcpy(state, keyboard_scan_get_state(), sizeof(state));
-	state[BATTERY_KEY_COL] ^= BATTERY_KEY_ROW_MASK;
-
-	/* Add to FIFO only if AP is on or else it will wake from suspend */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		mkbp_keyboard_add(state);
-}
-
-void clear_typematic_key(void)
-{ }
-
-static void set_keyscan_config(const struct ec_mkbp_config *src,
-			       struct ec_mkbp_protocol_config *dst,
-			       uint32_t valid_mask, uint8_t new_flags)
-{
-	struct keyboard_scan_config *ksc = keyboard_scan_get_config();
-
-	if (valid_mask & EC_MKBP_VALID_SCAN_PERIOD)
-		ksc->scan_period_us = src->scan_period_us;
-
-	if (valid_mask & EC_MKBP_VALID_POLL_TIMEOUT)
-		ksc->poll_timeout_us = src->poll_timeout_us;
-
-	if (valid_mask & EC_MKBP_VALID_MIN_POST_SCAN_DELAY) {
-		/*
-		 * Key scanning is high priority, so we should require at
-		 * least 100us min delay here. Setting this to 0 will cause
-		 * watchdog events. Use 200 to be safe.
-		 */
-		ksc->min_post_scan_delay_us =
-			MAX(src->min_post_scan_delay_us, 200);
-	}
-
-	if (valid_mask & EC_MKBP_VALID_OUTPUT_SETTLE)
-		ksc->output_settle_us = src->output_settle_us;
-
-	if (valid_mask & EC_MKBP_VALID_DEBOUNCE_DOWN)
-		ksc->debounce_down_us = src->debounce_down_us;
-
-	if (valid_mask & EC_MKBP_VALID_DEBOUNCE_UP)
-		ksc->debounce_up_us = src->debounce_up_us;
-
-	/*
-	 * If we just enabled key scanning, kick the task so that it will
-	 * fall out of the task_wait_event() in keyboard_scan_task().
-	 */
-	if ((new_flags & EC_MKBP_FLAGS_ENABLE) &&
-			!(dst->flags & EC_MKBP_FLAGS_ENABLE))
-		task_wake(TASK_ID_KEYSCAN);
-}
-
-static void get_keyscan_config(struct ec_mkbp_config *dst)
-{
-	const struct keyboard_scan_config *ksc = keyboard_scan_get_config();
-
-	/* Copy fields from keyscan config to mkbp config */
-	dst->output_settle_us = ksc->output_settle_us;
-	dst->debounce_down_us = ksc->debounce_down_us;
-	dst->debounce_up_us = ksc->debounce_up_us;
-	dst->scan_period_us = ksc->scan_period_us;
-	dst->min_post_scan_delay_us = ksc->min_post_scan_delay_us;
-	dst->poll_timeout_us = ksc->poll_timeout_us;
-}
-
-/**
- * Copy keyscan configuration from one place to another according to flags
- *
- * This is like a structure copy, except that only selected fields are
- * copied.
- *
- * @param src		Source config
- * @param dst		Destination config
- * @param valid_mask	Bits representing which fields to copy - each bit is
- *			from enum mkbp_config_valid
- * @param valid_flags	Bit mask controlling flags to copy. Any 1 bit means
- *			that the corresponding bit in src->flags is copied
- *			over to dst->flags
- */
-static void keyscan_copy_config(const struct ec_mkbp_config *src,
-				 struct ec_mkbp_protocol_config *dst,
-				 uint32_t valid_mask, uint8_t valid_flags)
-{
-	uint8_t new_flags;
-
-	if (valid_mask & EC_MKBP_VALID_FIFO_MAX_DEPTH) {
-		/* Validity check for fifo depth */
-		dst->fifo_max_depth = MIN(src->fifo_max_depth,
-					  FIFO_DEPTH);
-	}
-
-	new_flags = dst->flags & ~valid_flags;
-	new_flags |= src->flags & valid_flags;
-
-	set_keyscan_config(src, dst, valid_mask, new_flags);
-	dst->flags = new_flags;
-}
-
-static enum ec_status
-host_command_mkbp_set_config(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_mkbp_set_config *req = args->params;
-
-	keyscan_copy_config(&req->config, &config,
-			    config.valid_mask & req->config.valid_mask,
-			    config.valid_flags & req->config.valid_flags);
-
-	mkbp_fifo_depth_update(config.fifo_max_depth);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG,
-		     host_command_mkbp_set_config,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_mkbp_get_config(struct host_cmd_handler_args *args)
-{
-	struct ec_response_mkbp_get_config *resp = args->response;
-	struct ec_mkbp_config *dst = &resp->config;
-
-	memcpy(&resp->config, &config, sizeof(config));
-
-	/* Copy fields from mkbp protocol config to mkbp config */
-	dst->valid_mask = config.valid_mask;
-	dst->flags = config.flags;
-	dst->valid_flags = config.valid_flags;
-	dst->fifo_max_depth = config.fifo_max_depth;
-
-	get_keyscan_config(dst);
-
-	args->response_size = sizeof(*resp);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG,
-		     host_command_mkbp_get_config,
-		     EC_VER_MASK(0));
diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c
deleted file mode 100644
index 6584a55d84..0000000000
--- a/common/keyboard_scan.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard scanner module for Chrome EC */
-
-#include "chipset.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "keyboard_test.h"
-#include "lid_switch.h"
-#include "switch.h"
-#include "system.h"
-#include "tablet_mode.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_api.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-#define CPUTS5(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
-#else
-#define CPUTS5(outstr)
-#define CPRINTS5(format, args...)
-#endif
-
-#define SCAN_TIME_COUNT 32  /* Number of last scan times to track */
-
-/* If we're waiting for a scan to happen, we'll give it this long */
-#define SCAN_TASK_TIMEOUT_US	(100 * MSEC)
-
-#ifndef CONFIG_KEYBOARD_POST_SCAN_CLOCKS
-/*
- * Default delay in clocks; this was experimentally determined to be long
- * enough to avoid watchdog warnings or I2C errors on a typical notebook
- * config on STM32.
- */
-#define CONFIG_KEYBOARD_POST_SCAN_CLOCKS 16000
-#endif
-
-__overridable struct keyboard_scan_config keyscan_config = {
-#ifdef CONFIG_KEYBOARD_COL2_INVERTED
-	/*
-	 * CONFIG_KEYBOARD_COL2_INVERTED is defined for passing the column 2
-	 * to H1 which inverts the signal. The signal passing through H1
-	 * adds more delay. Need a larger delay value. Otherwise, pressing
-	 * Refresh key will also trigger T key, which is in the next scanning
-	 * column line. See http://b/156007029.
-	 */
-	.output_settle_us = 80,
-#else
-	.output_settle_us = 50,
-#endif /* CONFIG_KEYBOARD_COL2_INVERTED */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/* Boot key list.  Must be in same order as enum boot_key. */
-struct boot_key_entry {
-	uint8_t mask_index;
-	uint8_t mask_value;
-};
-
-#ifdef CONFIG_KEYBOARD_BOOT_KEYS
-static const struct boot_key_entry boot_key_list[] = {
-	{KEYBOARD_COL_ESC, KEYBOARD_MASK_ESC},   /* Esc */
-	{KEYBOARD_COL_DOWN, KEYBOARD_MASK_DOWN}, /* Down-arrow */
-	{KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_MASK_LEFT_SHIFT}, /* Left-Shift */
-};
-static uint32_t boot_key_value = BOOT_KEY_NONE;
-#endif
-
-uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
-
-/* Debounced key matrix */
-static uint8_t __bss_slow debounced_state[KEYBOARD_COLS_MAX];
-/* Mask of keys being debounced */
-static uint8_t __bss_slow debouncing[KEYBOARD_COLS_MAX];
-/* Keys simulated-pressed */
-static uint8_t __bss_slow simulated_key[KEYBOARD_COLS_MAX];
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-static uint8_t __bss_slow keyboard_id[KEYBOARD_IDS];
-#endif
-
-/* Times of last scans */
-static uint32_t __bss_slow scan_time[SCAN_TIME_COUNT];
-/* Current scan_time[] index */
-static int __bss_slow scan_time_index;
-
-/* Index into scan_time[] when each key started debouncing */
-static uint8_t __bss_slow scan_edge_index[KEYBOARD_COLS_MAX][KEYBOARD_ROWS];
-
-/* Minimum delay between keyboard scans based on current clock frequency */
-static uint32_t __bss_slow post_scan_clock_us;
-
-/*
- * Print all keyboard scan state changes?  Off by default because it generates
- * a lot of debug output, which makes the saved EC console data less useful.
- */
-static int __bss_slow print_state_changes;
-
-/* Must init to 0 for scanning at boot */
-static volatile uint32_t __bss_slow disable_scanning_mask;
-
-/* Constantly incrementing counter of the number of times we polled */
-static volatile int kbd_polls;
-
-/* If true, we'll force a keyboard poll */
-static volatile int force_poll;
-
-static int keyboard_scan_is_enabled(void)
-{
-	/* NOTE: this is just an instantaneous glimpse of the variable. */
-	return !disable_scanning_mask;
-}
-
-void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask)
-{
-	/* Access atomically */
-	if (enable) {
-		atomic_clear_bits((uint32_t *)&disable_scanning_mask, mask);
-	} else {
-		atomic_or((uint32_t *)&disable_scanning_mask, mask);
-		clear_typematic_key();
-	}
-
-	/* Let the task figure things out */
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-/**
- * Print the keyboard state.
- *
- * @param state		State array to print
- * @param msg		Description of state
- */
-static void print_state(const uint8_t *state, const char *msg)
-{
-	int c;
-
-	CPRINTF("[%pT KB %s:", PRINTF_TIMESTAMP_NOW, msg);
-	for (c = 0; c < keyboard_cols; c++) {
-		if (state[c])
-			CPRINTF(" %02x", state[c]);
-		else
-			CPUTS(" --");
-	}
-	CPUTS("]\n");
-}
-
-/**
- * Ensure that the keyboard has been scanned.
- *
- * Makes sure that we've fully gone through the keyboard scanning loop at
- * least once.
- */
-static void ensure_keyboard_scanned(int old_polls)
-{
-	uint64_t start_time;
-
-	start_time = get_time().val;
-
-	/*
-	 * Ensure we see the poll task run.
-	 *
-	 * Note that the poll task is higher priority than ours so we know that
-	 * while we're running it's not partway through a poll.  That means that
-	 * if kbd_polls changes we've gone through a whole cycle.
-	 */
-	while ((kbd_polls == old_polls) &&
-	       (get_time().val - start_time < SCAN_TASK_TIMEOUT_US))
-		usleep(keyscan_config.scan_period_us);
-}
-
-/**
- * Simulate a keypress.
- *
- * @param row		Row of key
- * @param col		Column of key
- * @param pressed	Non-zero if pressed, zero if released
- */
-static void simulate_key(int row, int col, int pressed)
-{
-	int old_polls;
-
-	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
-
-	simulated_key[col] ^= BIT(row);
-
-	/* Keep track of polls now that we've got keys simulated */
-	old_polls = kbd_polls;
-
-	print_state(simulated_key, "simulated ");
-
-	/* Force a poll even though no keys are pressed */
-	force_poll = 1;
-
-	/* Wake the task to handle changes in simulated keys */
-	task_wake(TASK_ID_KEYSCAN);
-
-	/*
-	 * Make sure that the keyboard task sees the key for long enough.
-	 * That means it needs to have run and for enough time.
-	 */
-	ensure_keyboard_scanned(old_polls);
-	usleep(pressed ?
-	       keyscan_config.debounce_down_us : keyscan_config.debounce_up_us);
-	ensure_keyboard_scanned(kbd_polls);
-}
-
-/**
- * Read the raw keyboard matrix state.
- *
- * Used in pre-init, so must not make task-switching-dependent calls; udelay()
- * is ok because it's a spin-loop.
- *
- * @param state		Destination for new state (must be KEYBOARD_COLS_MAX
- *			long).
- *
- * @return 1 if at least one key is pressed, else zero.
- */
-static int read_matrix(uint8_t *state)
-{
-	int c;
-	int pressed = 0;
-
-	/* 1. Read input pins */
-	for (c = 0; c < keyboard_cols; c++) {
-		/*
-		 * Skip if scanning becomes disabled. Clear the state
-		 * to make sure we don't mix new and old states in the
-		 * same array.
-		 *
-		 * Note, scanning is enabled on boot by default.
-		 */
-		if (!keyboard_scan_is_enabled()) {
-			state[c] = 0;
-			continue;
-		}
-
-		/* Select column, then wait a bit for it to settle */
-		keyboard_raw_drive_column(c);
-		udelay(keyscan_config.output_settle_us);
-
-		/* Read the row state */
-		state[c] = keyboard_raw_read_rows();
-
-		/* Use simulated keyscan sequence instead if testing active */
-		if (IS_ENABLED(CONFIG_KEYBOARD_TEST))
-			state[c] = keyscan_seq_get_scan(c, state[c]);
-	}
-
-	/* 2. Detect transitional ghost */
-	for (c = 0; c < keyboard_cols; c++) {
-		int c2;
-
-		for (c2 = 0; c2 < c; c2++) {
-			/*
-			 * If two columns shares at least one key but their
-			 * states are different, maybe the state changed between
-			 * two "keyboard_raw_read_rows"s. If this happened,
-			 * update both columns to the union of them.
-			 *
-			 * Note that in theory we need to rescan from col 0 if
-			 * anything is updated, to make sure the newly added
-			 * bits does not introduce more inconsistency.
-			 * Let's ignore this rare case for now.
-			 */
-			if ((state[c] & state[c2]) && (state[c] != state[c2])) {
-				uint8_t merged = state[c] | state[c2];
-
-				state[c] = state[c2] = merged;
-			}
-		}
-	}
-
-	/* 3. Fix result */
-	for (c = 0; c < keyboard_cols; c++) {
-		/* Add in simulated keypresses */
-		state[c] |= simulated_key[c];
-
-		/*
-		 * Keep track of what keys appear to be pressed.  Even if they
-		 * don't exist in the matrix, they'll keep triggering
-		 * interrupts, so we can't leave scanning mode.
-		 */
-		pressed |= state[c];
-
-		/* Mask off keys that don't exist on the actual keyboard */
-		state[c] &= keyscan_config.actual_key_mask[c];
-
-	}
-
-	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-
-	return pressed ? 1 : 0;
-}
-
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-/**
- * Read the raw keyboard IDs state.
- *
- * Used in pre-init, so must not make task-switching-dependent calls; udelay()
- * is ok because it's a spin-loop.
- *
- * @param id		Destination for keyboard id (must be KEYBOARD_IDS long).
- *
- */
-static void read_matrix_id(uint8_t *id)
-{
-	int c;
-
-	for (c = 0; c < KEYBOARD_IDS; c++) {
-		/* Select the ID pin, then wait a bit for it to settle.
-		 * Caveat: If a keyboard maker puts ID pins right after scan
-		 * columns, we can't support variable column size with a single
-		 * image. */
-		keyboard_raw_drive_column(KEYBOARD_COLS_MAX + c);
-		udelay(keyscan_config.output_settle_us);
-
-		/* Read the row state */
-		id[c] = keyboard_raw_read_rows();
-
-		CPRINTS("Keyboard ID%u: 0x%02x", c, id[c]);
-	}
-
-	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-}
-#endif
-
-#ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
-
-static uint8_t key_vol_up_row = KEYBOARD_DEFAULT_ROW_VOL_UP;
-static uint8_t key_vol_up_col = KEYBOARD_DEFAULT_COL_VOL_UP;
-
-void set_vol_up_key(uint8_t row, uint8_t col)
-{
-	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) {
-		key_vol_up_row = row;
-		key_vol_up_col = col;
-	}
-}
-
-/**
- * Check special runtime key combinations.
- *
- * @param state		Keyboard state to use when checking keys.
- *
- * @return 1 if a special key was pressed, 0 if not
- */
-static int check_runtime_keys(const uint8_t *state)
-{
-	int num_press = 0;
-	int c;
-
-	/*
-	 * All runtime key combos are (right or left ) alt + volume up + (some
-	 * key NOT on the same col as alt or volume up )
-	 */
-	if (state[key_vol_up_col] != KEYBOARD_ROW_TO_MASK(key_vol_up_row))
-		return 0;
-
-	if (state[KEYBOARD_COL_RIGHT_ALT] != KEYBOARD_MASK_RIGHT_ALT &&
-	    state[KEYBOARD_COL_LEFT_ALT] != KEYBOARD_MASK_LEFT_ALT)
-		return 0;
-
-	/*
-	 * Count number of columns with keys pressed.  We know two columns are
-	 * pressed for volume up and alt, so if only one more key is pressed
-	 * there will be exactly 3 non-zero columns.
-	 */
-	for (c = 0; c < keyboard_cols; c++) {
-		if (state[c])
-			num_press++;
-	}
-
-	if (num_press != 3)
-		return 0;
-
-	/* Check individual keys */
-	if (state[KEYBOARD_COL_KEY_R] == KEYBOARD_MASK_KEY_R) {
-		/* R = reboot */
-		CPRINTS("KB warm reboot");
-		keyboard_clear_buffer();
-		chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT);
-		return 1;
-	} else if (state[KEYBOARD_COL_KEY_H] == KEYBOARD_MASK_KEY_H) {
-		/* H = hibernate */
-		CPRINTS("KB hibernate");
-		system_enter_hibernate(0, 0);
-		return 1;
-	}
-
-	return 0;
-}
-#endif /* CONFIG_KEYBOARD_RUNTIME_KEYS */
-
-/**
- * Check for ghosting in the keyboard state.
- *
- * Assumes that the state has already been masked with the actual key mask, so
- * that coords which don't correspond with actual keys don't trigger ghosting
- * detection.
- *
- * @param state		Keyboard state to check.
- *
- * @return 1 if ghosting detected, else 0.
- */
-static int has_ghosting(const uint8_t *state)
-{
-	int c, c2;
-
-	for (c = 0; c < keyboard_cols; c++) {
-		if (!state[c])
-			continue;
-
-		for (c2 = c + 1; c2 < keyboard_cols; c2++) {
-			/*
-			 * A little bit of cleverness here.  Ghosting happens
-			 * if 2 columns share at least 2 keys.  So we OR the
-			 * columns together and then see if more than one bit
-			 * is set.  x&(x-1) is non-zero only if x has more than
-			 * one bit set.
-			 */
-			uint8_t common = state[c] & state[c2];
-
-			if (common & (common - 1))
-				return 1;
-		}
-	}
-
-	return 0;
-}
-
-/* Inform keyboard module if scanning is enabled */
-static void key_state_changed(int row, int col, uint8_t state)
-{
-	if (!keyboard_scan_is_enabled())
-		return;
-
-	/* No-op for protocols that require full keyboard matrix (e.g. MKBP). */
-	keyboard_state_changed(row, col, !!(state & BIT(row)));
-}
-
-/**
- * Update keyboard state using low-level interface to read keyboard.
- *
- * @param state		Keyboard state to update.
- *
- * @return 1 if any key is still pressed, 0 if no key is pressed.
- */
-static int check_keys_changed(uint8_t *state)
-{
-	int any_pressed = 0;
-	int c, i;
-	int any_change = 0;
-	static uint8_t __bss_slow new_state[KEYBOARD_COLS_MAX];
-	uint32_t tnow = get_time().le.lo;
-
-	/* Save the current scan time */
-	if (++scan_time_index >= SCAN_TIME_COUNT)
-		scan_time_index = 0;
-	scan_time[scan_time_index] = tnow;
-
-	/* Read the raw key state */
-	any_pressed = read_matrix(new_state);
-
-	/* Ignore if so many keys are pressed that we're ghosting. */
-	if (has_ghosting(new_state))
-		return any_pressed;
-
-	/* Check for changes between previous scan and this one */
-	for (c = 0; c < keyboard_cols; c++) {
-		int diff = new_state[c] ^ state[c];
-
-		/* Clear debouncing flag, if sufficient time has elapsed. */
-		for (i = 0; i < KEYBOARD_ROWS && debouncing[c]; i++) {
-			if (!(debouncing[c] & BIT(i)))
-				continue;
-			if (tnow - scan_time[scan_edge_index[c][i]] <
-			    (state[c] ? keyscan_config.debounce_down_us :
-					keyscan_config.debounce_up_us))
-				continue;  /* Not done debouncing */
-			debouncing[c] &= ~BIT(i);
-
-			if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
-				continue;
-			if (!(diff & BIT(i)))
-				/* Debounced but no difference. */
-				continue;
-			any_change = 1;
-			key_state_changed(i, c, new_state[c]);
-			/*
-			 * This makes state[c] == new_state[c] for row i.
-			 * Thus, when diff is calculated below, it won't
-			 * be asserted (for row i).
-			 */
-			state[c] ^= diff & BIT(i);
-		}
-
-		/* Recognize change in state, unless debounce in effect. */
-		diff = (new_state[c] ^ state[c]) & ~debouncing[c];
-		if (!diff)
-			continue;
-		for (i = 0; i < KEYBOARD_ROWS; i++) {
-			if (!(diff & BIT(i)))
-				continue;
-			scan_edge_index[c][i] = scan_time_index;
-
-			if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE)) {
-				any_change = 1;
-				key_state_changed(i, c, new_state[c]);
-			}
-		}
-
-		/* For any keyboard events just sent, turn on debouncing. */
-		debouncing[c] |= diff;
-		/*
-		 * Note: In order to "remember" what was last reported
-		 * (up or down), the state bits are only updated if the
-		 * edge was not suppressed due to debouncing.
-		 */
-		if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
-			state[c] ^= diff;
-	}
-
-	if (any_change) {
-
-#ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE
-		/* Suppress keyboard noise */
-		keyboard_suppress_noise();
-#endif
-
-		if (print_state_changes)
-			print_state(state, "state");
-
-#ifdef CONFIG_KEYBOARD_PRINT_SCAN_TIMES
-		/* Print delta times from now back to each previous scan */
-		CPRINTF("[%pT kb deltaT", PRINTF_TIMESTAMP_NOW);
-		for (i = 0; i < SCAN_TIME_COUNT; i++) {
-			int tnew = scan_time[
-				(SCAN_TIME_COUNT + scan_time_index - i) %
-				SCAN_TIME_COUNT];
-			CPRINTF(" %d", tnow - tnew);
-		}
-		CPRINTF("]\n");
-#endif
-
-#ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
-		/* Swallow special keys */
-		if (check_runtime_keys(state))
-			return 0;
-#endif
-
-#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-		mkbp_keyboard_add(state);
-#endif
-	}
-
-	kbd_polls++;
-
-	return any_pressed;
-}
-
-static uint8_t keyboard_mask_refresh;
-__overridable uint8_t board_keyboard_row_refresh(void)
-{
-	if (IS_ENABLED(CONFIG_KEYBOARD_REFRESH_ROW3))
-		return 3;
-	else
-		return 2;
-}
-
-#ifdef CONFIG_KEYBOARD_BOOT_KEYS
-/*
- * Returns mask of the boot keys that are pressed, with at most the keys used
- * for keyboard-controlled reset also pressed.
- */
-static uint32_t check_key_list(const uint8_t *state)
-{
-	uint8_t curr_state[KEYBOARD_COLS_MAX];
-	int c;
-	uint32_t boot_key_mask = BOOT_KEY_NONE;
-	const struct boot_key_entry *k;
-
-	/* Make copy of current debounced state. */
-	memcpy(curr_state, state, sizeof(curr_state));
-
-#ifdef KEYBOARD_MASK_PWRBTN
-	/*
-	 * Check if KSI2 or KSI3 is asserted for all columns due to power
-	 * button hold, and ignore it if so.
-	 */
-	for (c = 0; c < keyboard_cols; c++)
-		if ((keyscan_config.actual_key_mask[c] & KEYBOARD_MASK_PWRBTN)
-		    && !(curr_state[c] & KEYBOARD_MASK_PWRBTN))
-			break;
-
-	if (c == keyboard_cols)
-		for (c = 0; c < keyboard_cols; c++)
-			curr_state[c] &= ~KEYBOARD_MASK_PWRBTN;
-#endif
-
-	curr_state[KEYBOARD_COL_REFRESH] &= ~keyboard_mask_refresh;
-
-	/* Update mask with all boot keys that were pressed. */
-	k = boot_key_list;
-	for (c = 0; c < ARRAY_SIZE(boot_key_list); c++, k++) {
-		if (curr_state[k->mask_index] & k->mask_value) {
-			boot_key_mask |= BIT(c);
-			curr_state[k->mask_index] &= ~k->mask_value;
-		}
-	}
-
-	/* If any other key was pressed, ignore all boot keys. */
-	for (c = 0; c < keyboard_cols; c++) {
-		if (curr_state[c])
-			return BOOT_KEY_NONE;
-	}
-
-	CPRINTS("KB boot key mask %x", boot_key_mask);
-	return boot_key_mask;
-}
-
-/**
- * Check what boot key is down, if any.
- *
- * @param state		Keyboard state at boot.
- *
- * @return the key which is down, or BOOT_KEY_NONE if an unrecognized
- * key combination is down or this isn't the right type of boot to look at
- * boot keys.
- */
-static uint32_t check_boot_key(const uint8_t *state)
-{
-	/*
-	 * If we jumped to this image, ignore boot keys.  This prevents
-	 * re-triggering events in RW firmware that were already processed by
-	 * RO firmware.
-	 */
-	if (system_jumped_late())
-		return BOOT_KEY_NONE;
-
-	/* If reset was not caused by reset pin, refresh must be held down */
-	if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) &&
-	    !(state[KEYBOARD_COL_REFRESH] & keyboard_mask_refresh))
-		return BOOT_KEY_NONE;
-
-	return check_key_list(state);
-}
-#endif
-
-static void keyboard_freq_change(void)
-{
-	post_scan_clock_us = (CONFIG_KEYBOARD_POST_SCAN_CLOCKS * 1000) /
-		(clock_get_freq() / 1000);
-}
-DECLARE_HOOK(HOOK_FREQ_CHANGE, keyboard_freq_change, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interface */
-
-struct keyboard_scan_config *keyboard_scan_get_config(void)
-{
-	return &keyscan_config;
-}
-
-#ifdef CONFIG_KEYBOARD_BOOT_KEYS
-uint32_t keyboard_scan_get_boot_keys(void)
-{
-	return boot_key_value;
-}
-#endif
-
-const uint8_t *keyboard_scan_get_state(void)
-{
-	return debounced_state;
-}
-
-void keyboard_scan_init(void)
-{
-	if (IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE) &&
-	    keyscan_config.debounce_down_us != keyscan_config.debounce_up_us) {
-		/*
-		 * Strict debouncer is prone to keypress reordering if debounce
-		 * durations for down and up are not equal. crbug.com/547131
-		 */
-		CPRINTS("KB WARN: Debounce durations not equal");
-	}
-
-	/* Configure refresh key matrix */
-	keyboard_mask_refresh = KEYBOARD_ROW_TO_MASK(
-		board_keyboard_row_refresh());
-
-	/* Configure GPIO */
-	keyboard_raw_init();
-
-	/* Tri-state the columns */
-	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-
-	/* Initialize raw state */
-	read_matrix(debounced_state);
-
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-	/* Check keyboard ID state */
-	read_matrix_id(keyboard_id);
-#endif
-
-#ifdef CONFIG_KEYBOARD_BOOT_KEYS
-	/* Check for keys held down at boot */
-	boot_key_value = check_boot_key(debounced_state);
-
-	/*
-	 * If any key other than Esc or Left_Shift was pressed, do not trigger
-	 * recovery.
-	 */
-	if (boot_key_value & ~(BOOT_KEY_ESC | BOOT_KEY_LEFT_SHIFT))
-		return;
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-	if (boot_key_value & BOOT_KEY_ESC) {
-		host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
-		/*
-		 * In recovery mode, we should force clamshell mode in order to
-		 * prevent the keyboard from being disabled unintentionally due
-		 * to unstable accel readings.
-		 *
-		 * You get the same effect if motion sensors or a motion sense
-		 * task are disabled in RO.
-		 */
-		if (IS_ENABLED(CONFIG_TABLET_MODE))
-			tablet_disable();
-		if (boot_key_value & BOOT_KEY_LEFT_SHIFT)
-			host_set_single_event(
-				EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT);
-	}
-#endif
-#endif /* CONFIG_KEYBOARD_BOOT_KEYS */
-}
-
-void keyboard_scan_task(void *u)
-{
-	timestamp_t poll_deadline, start;
-	int wait_time;
-	uint32_t local_disable_scanning = 0;
-
-	print_state(debounced_state, "init state");
-
-	keyboard_raw_task_start();
-
-	/* Set initial clock frequency-based minimum delay between scans */
-	keyboard_freq_change();
-
-	while (1) {
-		/* Enable all outputs */
-		CPRINTS5("KB wait");
-
-		keyboard_raw_enable_interrupt(1);
-
-		/* Wait for scanning enabled and key pressed. */
-		while (1) {
-			uint32_t new_disable_scanning;
-
-			/* Read it once to get consistent glimpse */
-			new_disable_scanning = disable_scanning_mask;
-
-			if (local_disable_scanning != new_disable_scanning)
-				CPRINTS("KB disable_scanning_mask changed: "
-					"0x%08x", new_disable_scanning);
-
-			if (!new_disable_scanning) {
-				/* Enabled now */
-				keyboard_raw_drive_column(KEYBOARD_COLUMN_ALL);
-			} else if (!local_disable_scanning) {
-				/*
-				 * Scanning isn't enabled but it was last time
-				 * we looked.
-				 *
-				 * No race here even though we're basing on a
-				 * glimpse of disable_scanning_mask since if
-				 * someone changes disable_scanning_mask they
-				 * are guaranteed to call task_wake() on us
-				 * afterward so we'll run the loop again.
-				 */
-				keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-				keyboard_clear_buffer();
-			}
-
-			local_disable_scanning = new_disable_scanning;
-
-			/*
-			 * Done waiting if scanning is enabled and a key is
-			 * already pressed.  This prevents a race between the
-			 * user pressing a key and enable_interrupt()
-			 * starting to pay attention to edges.
-			 */
-			if (!local_disable_scanning &&
-			    (keyboard_raw_read_rows() || force_poll))
-				break;
-			else
-				task_wait_event(-1);
-		}
-
-		/* We're about to poll, so any existing forces are fulfilled */
-		force_poll = 0;
-
-		/* Enter polling mode */
-		CPRINTS5("KB poll");
-		keyboard_raw_enable_interrupt(0);
-		keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
-
-		/* Busy polling keyboard state. */
-		while (keyboard_scan_is_enabled()) {
-			start = get_time();
-
-			/* Check for keys down */
-			if (check_keys_changed(debounced_state)) {
-				poll_deadline.val = start.val
-					+ keyscan_config.poll_timeout_us;
-			} else if (timestamp_expired(poll_deadline, &start)) {
-				break;
-			}
-
-			/* Delay between scans */
-			wait_time = keyscan_config.scan_period_us -
-				(get_time().val - start.val);
-
-			if (wait_time < keyscan_config.min_post_scan_delay_us)
-				wait_time =
-					keyscan_config.min_post_scan_delay_us;
-
-			if (wait_time < post_scan_clock_us)
-				wait_time = post_scan_clock_us;
-
-			usleep(wait_time);
-		}
-	}
-}
-
-#ifdef CONFIG_LID_SWITCH
-
-static void keyboard_lid_change(void)
-{
-	if (lid_is_open())
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_CLOSED);
-	else
-		keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_CLOSED);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, keyboard_lid_change, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_INIT, keyboard_lid_change, HOOK_PRIO_INIT_LID + 1);
-
-#endif
-
-#ifdef CONFIG_USB_SUSPEND
-static void keyboard_usb_pm_change(void)
-{
-	/*
-	 * If USB interface is suspended, and host is not asking us to do remote
-	 * wakeup, we can turn off the key scanning.
-	 */
-	if (usb_is_suspended() && !usb_is_remote_wakeup_enabled())
-		keyboard_scan_enable(0, KB_SCAN_DISABLE_USB_SUSPENDED);
-	else
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_USB_SUSPENDED);
-}
-DECLARE_HOOK(HOOK_USB_PM_CHANGE, keyboard_usb_pm_change, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-mkbp_command_simulate_key(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_mkbp_simulate_key *p = args->params;
-
-	/* Only available on unlocked systems */
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (p->col >= keyboard_cols || p->row >= KEYBOARD_ROWS)
-		return EC_RES_INVALID_PARAM;
-
-	simulate_key(p->row, p->col, p->pressed);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY,
-		     mkbp_command_simulate_key,
-		     EC_VER_MASK(0));
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-
-/* Run keyboard factory testing, scan out KSO/KSI if any shorted. */
-int keyboard_factory_test_scan(void)
-{
-	int i, j, flags;
-	uint16_t shorted = 0;
-	int port, id;
-
-	/* Disable keyboard scan while testing */
-	keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_CLOSED);
-	flags = gpio_get_default_flags(GPIO_KBD_KSO2);
-
-	/* Set all of KSO/KSI pins to internal pull-up and input */
-	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
-		if (keyboard_factory_scan_pins[i][0] < 0)
-			continue;
-
-		port = keyboard_factory_scan_pins[i][0];
-		id = keyboard_factory_scan_pins[i][1];
-
-		gpio_set_alternate_function(port, 1 << id,
-					GPIO_ALT_FUNC_NONE);
-		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
-	}
-
-	/*
-	 * Set start pin to output low, then check other pins
-	 * going to low level, it indicate the two pins are shorted.
-	 */
-	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
-		if (keyboard_factory_scan_pins[i][0] < 0)
-			continue;
-
-		port = keyboard_factory_scan_pins[i][0];
-		id = keyboard_factory_scan_pins[i][1];
-
-		gpio_set_flags_by_mask(port, 1 << id, GPIO_OUT_LOW);
-
-		for (j = 0; j < i; j++) {
-
-			if (keyboard_factory_scan_pins[j][0] < 0)
-				continue;
-
-			if (keyboard_raw_is_input_low(
-					keyboard_factory_scan_pins[j][0],
-					keyboard_factory_scan_pins[j][1])) {
-				shorted = i << 8 | j;
-				goto done;
-			}
-		}
-		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
-	}
-done:
-	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
-	gpio_set_flags(GPIO_KBD_KSO2, flags);
-	keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_CLOSED);
-
-	return shorted;
-}
-
-static enum ec_status keyboard_factory_test(struct host_cmd_handler_args *args)
-{
-	struct ec_response_keyboard_factory_test *r = args->response;
-
-	/* Only available on unlocked systems */
-	if (system_is_locked())
-		return EC_RES_ACCESS_DENIED;
-
-	if (keyboard_factory_scan_pins_used == 0)
-		return EC_RES_INVALID_COMMAND;
-
-	r->shorted = keyboard_factory_test_scan();
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST,
-		     keyboard_factory_test,
-		     EC_VER_MASK(0));
-#endif
-
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-int keyboard_get_keyboard_id(void)
-{
-	int c;
-	uint32_t id = 0;
-
-	BUILD_ASSERT(sizeof(id) >= KEYBOARD_IDS);
-
-	for (c = 0; c < KEYBOARD_IDS; c++) {
-		/* Check ID ghosting if more than one bit in any KSIs was set */
-		if (keyboard_id[c] & (keyboard_id[c] - 1))
-			/* ID ghosting is found */
-			return KEYBOARD_ID_UNREADABLE;
-		else
-			id |= keyboard_id[c] << (c * 8);
-	}
-	return id;
-}
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_KEYBOARD
-static int command_ksstate(int argc, char **argv)
-{
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "force")) {
-			print_state_changes = 1;
-			keyboard_scan_enable(1, -1);
-		} else if (!parse_bool(argv[1], &print_state_changes)) {
-			return EC_ERROR_PARAM1;
-		}
-	}
-
-	print_state(debounced_state, "debounced ");
-	print_state(debouncing, "debouncing");
-
-	ccprintf("Keyboard scan disable mask: 0x%08x\n",
-		 disable_scanning_mask);
-	ccprintf("Keyboard scan state printing %s\n",
-		 print_state_changes ? "on" : "off");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate,
-			"ksstate [on | off | force]",
-			"Show or toggle printing keyboard scan state");
-
-static int command_keyboard_press(int argc, char **argv)
-{
-	if (argc == 1) {
-		int i, j;
-
-		ccputs("Simulated keys:\n");
-		for (i = 0; i < keyboard_cols; ++i) {
-			if (simulated_key[i] == 0)
-				continue;
-			for (j = 0; j < KEYBOARD_ROWS; ++j)
-				if (simulated_key[i] & BIT(j))
-					ccprintf("\t%d %d\n", i, j);
-		}
-
-	} else if (argc == 3 || argc == 4) {
-		int r, c, p;
-		char *e;
-
-		c = strtoi(argv[1], &e, 0);
-		if (*e || c < 0 || c >= keyboard_cols)
-			return EC_ERROR_PARAM1;
-
-		r = strtoi(argv[2], &e, 0);
-		if (*e || r < 0 || r >= KEYBOARD_ROWS)
-			return EC_ERROR_PARAM2;
-
-		if (argc == 3) {
-			/* Simulate a press and release */
-			simulate_key(r, c, 1);
-			simulate_key(r, c, 0);
-		} else {
-			p = strtoi(argv[3], &e, 0);
-			if (*e || p < 0 || p > 1)
-				return EC_ERROR_PARAM3;
-
-			simulate_key(r, c, p);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press,
-			"[col row [0 | 1]]",
-			"Simulate keypress");
-#endif
diff --git a/common/keyboard_test.c b/common/keyboard_test.c
deleted file mode 100644
index e7b1dfe501..0000000000
--- a/common/keyboard_test.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <common.h>
-#include <console.h>
-#include <ec_commands.h>
-#include <host_command.h>
-#include <keyboard_test.h>
-#include <task.h>
-#include <util.h>
-
-enum {
-	KEYSCAN_MAX_LENGTH		= 20,
-	KEYSCAN_SEQ_START_DELAY_US	= 10000,
-};
-
-static uint8_t keyscan_seq_count;
-static int8_t keyscan_seq_upto = -1;
-static struct keyscan_item keyscan_items[KEYSCAN_MAX_LENGTH];
-struct keyscan_item *keyscan_seq_cur;
-
-static int keyscan_seq_is_active(void)
-{
-	return keyscan_seq_upto != -1;
-}
-
-/**
- * Get the current item in the keyscan sequence
- *
- * This looks at the current time, and returns the correct key scan for that
- * time.
- *
- * @return pointer to keyscan item, or NULL if none
- */
-static const struct keyscan_item *keyscan_seq_get(void)
-{
-	struct keyscan_item *ksi;
-
-	if (!keyscan_seq_is_active())
-		return NULL;
-
-	ksi = &keyscan_items[keyscan_seq_upto];
-	while (keyscan_seq_upto < keyscan_seq_count) {
-		/*
-		 * If we haven't reached the time for the next one, return
-		 * this one.
-		 */
-		if (!timestamp_expired(ksi->abs_time, NULL)) {
-			/* Yippee, we get to present this one! */
-			if (keyscan_seq_cur)
-				keyscan_seq_cur->done = 1;
-			return keyscan_seq_cur;
-		}
-
-		keyscan_seq_cur = ksi;
-		keyscan_seq_upto++;
-		ksi++;
-	}
-
-	ccprints("keyscan_seq done, upto=%d", keyscan_seq_upto);
-	keyscan_seq_upto = -1;
-	keyscan_seq_cur = NULL;
-	return NULL;
-}
-
-uint8_t keyscan_seq_get_scan(int column, uint8_t scan)
-{
-	const struct keyscan_item *item;
-
-	/* Use simulated keyscan sequence instead if active */
-	item = keyscan_seq_get();
-	if (item) {
-		/* OR all columns together */
-		if (column == -1) {
-			int c;
-
-			scan = 0;
-			for (c = 0; c < keyboard_cols; c++)
-				scan |= item->scan[c];
-		} else {
-			scan = item->scan[column];
-		}
-	}
-
-	return scan;
-}
-
-int keyscan_seq_next_event_delay(void)
-{
-	const struct keyscan_item *ksi;
-	int delay;
-
-	/*
-	 * Make sure we are pointing to the right event. This function will
-	 * return the event that should currently be presented. In fact we
-	 * want to look at the next event to be presented, so we manually
-	 * look that up after calling this function.
-	 */
-	ksi = keyscan_seq_get();
-
-	if (!keyscan_seq_is_active())
-		return -1;
-
-	/* Calculate the delay until the event */
-	ksi = &keyscan_items[keyscan_seq_upto];
-	delay = MAX(ksi->abs_time.val - get_time().val, 0);
-
-	return delay;
-}
-
-static void keyscan_seq_start(void)
-{
-	timestamp_t start;
-	int i;
-
-	start = get_time();
-	start.val += KEYSCAN_SEQ_START_DELAY_US;
-	for (i = 0; i < keyscan_seq_count; i++) {
-		struct keyscan_item *ksi = &keyscan_items[i];
-
-		ksi->abs_time = start;
-		ksi->abs_time.val += ksi->time_us;
-	}
-
-	keyscan_seq_upto = 0;
-	keyscan_seq_cur = NULL;
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-static int keyscan_seq_collect(struct ec_params_keyscan_seq_ctrl *req,
-			       struct ec_result_keyscan_seq_ctrl *resp)
-{
-	struct keyscan_item *ksi;
-	int start, end;
-	int i;
-
-	/* Range check the input values */
-	start = req->collect.start_item;
-	end = start + req->collect.num_items;
-	if (start >= keyscan_seq_count)
-		end = start;
-	else
-		end = MIN(end, keyscan_seq_count);
-	start = MIN(start, end);
-
-	/* Response plus one byte per item */
-	end = MIN(end - start, EC_HOST_PARAM_SIZE - sizeof(*resp));
-	resp->collect.num_items = end - start;
-
-	for (i = start, ksi = keyscan_items; i < end; i++, ksi++)
-		resp->collect.item[i].flags = ksi->done ?
-						EC_KEYSCAN_SEQ_FLAG_DONE : 0;
-
-	return sizeof(*resp) + resp->collect.num_items;
-}
-
-static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args)
-{
-	struct ec_params_keyscan_seq_ctrl req, *msg;
-	struct keyscan_item *ksi;
-
-	/* For now we must do our own alignment */
-	memcpy(&req, args->params, sizeof(req));
-
-	ccprintf("keyscan %d\n", req.cmd);
-	switch (req.cmd) {
-	case EC_KEYSCAN_SEQ_CLEAR:
-		keyscan_seq_count = 0;
-		break;
-	case EC_KEYSCAN_SEQ_ADD:
-		if (keyscan_seq_count == KEYSCAN_MAX_LENGTH)
-			return EC_RES_OVERFLOW;
-
-		ksi = &keyscan_items[keyscan_seq_count];
-		ksi->time_us = req.add.time_us;
-		ksi->done = 0;
-		ksi->abs_time.val = 0;
-		msg = (struct ec_params_keyscan_seq_ctrl *)args->params;
-		memcpy(ksi->scan, msg->add.scan, sizeof(ksi->scan));
-		keyscan_seq_count++;
-		break;
-	case EC_KEYSCAN_SEQ_START:
-		keyscan_seq_start();
-		break;
-	case EC_KEYSCAN_SEQ_COLLECT:
-		args->response_size = keyscan_seq_collect(&req,
-			(struct ec_result_keyscan_seq_ctrl *)args->response);
-		break;
-	default:
-		return EC_RES_INVALID_COMMAND;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL,
-		     keyscan_seq_ctrl,
-		     EC_VER_MASK(0));
diff --git a/common/keyboard_vivaldi.c b/common/keyboard_vivaldi.c
deleted file mode 100644
index 443b475c82..0000000000
--- a/common/keyboard_vivaldi.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Vivali Keyboard code for Chrome EC */
-
-#include "keyboard_8042_sharedlib.h"
-#include "keyboard_scan.h"
-#include "ec_commands.h"
-#include <host_command.h>
-#include <util.h>
-#include <hooks.h>
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-/*
- * Row Column info for Top row keys T1 - T15. This has been sourced from
- * go/vivaldi-matrix (internal link for vivaldi scan matrix spec).
- */
-static const struct key {
-	uint8_t row;
-	uint8_t col;
-} vivaldi_keys[] = {
-	{.row = 0, .col = 2},	/* T1 */
-	{.row = 3, .col = 2},	/* T2 */
-	{.row = 2, .col = 2},	/* T3 */
-	{.row = 1, .col = 2},	/* T4 */
-	{.row = 3, .col = 4},	/* T5 */
-	{.row = 2, .col = 4},	/* T6 */
-	{.row = 1, .col = 4},	/* T7 */
-	{.row = 2, .col = 9},	/* T8 */
-	{.row = 1, .col = 9},	/* T9 */
-	{.row = 0, .col = 4},	/* T10 */
-	{.row = 0, .col = 1},	/* T11 */
-	{.row = 1, .col = 5},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 0, .col = 9},	/* T14 */
-	{.row = 0, .col = 11},	/* T15 */
-};
-BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
-
-/* Scancodes for top row action keys */
-static const uint16_t action_scancodes[] = {
-	[TK_BACK] = SCANCODE_BACK,
-	[TK_FORWARD] = SCANCODE_FORWARD,
-	[TK_REFRESH] = SCANCODE_REFRESH,
-	[TK_FULLSCREEN] = SCANCODE_FULLSCREEN,
-	[TK_OVERVIEW] = SCANCODE_OVERVIEW,
-	[TK_VOL_MUTE] = SCANCODE_VOLUME_MUTE,
-	[TK_VOL_DOWN] = SCANCODE_VOLUME_DOWN,
-	[TK_VOL_UP] = SCANCODE_VOLUME_UP,
-	[TK_PLAY_PAUSE] = SCANCODE_PLAY_PAUSE,
-	[TK_NEXT_TRACK] = SCANCODE_NEXT_TRACK,
-	[TK_PREV_TRACK] = SCANCODE_PREV_TRACK,
-	[TK_SNAPSHOT] = SCANCODE_SNAPSHOT,
-	[TK_BRIGHTNESS_DOWN] = SCANCODE_BRIGHTNESS_DOWN,
-	[TK_BRIGHTNESS_UP] = SCANCODE_BRIGHTNESS_UP,
-	[TK_KBD_BKLIGHT_DOWN] = SCANCODE_KBD_BKLIGHT_DOWN,
-	[TK_KBD_BKLIGHT_UP] = SCANCODE_KBD_BKLIGHT_UP,
-	[TK_PRIVACY_SCRN_TOGGLE] = SCANCODE_PRIVACY_SCRN_TOGGLE,
-	[TK_MICMUTE] = SCANCODE_MICMUTE,
-	[TK_KBD_BKLIGHT_TOGGLE] = SCANCODE_KBD_BKLIGHT_TOGGLE,
-};
-
-static const struct ec_response_keybd_config *vivaldi_keybd;
-
-static enum
-ec_status get_vivaldi_keybd_config(struct host_cmd_handler_args *args)
-{
-	struct ec_response_keybd_config *resp = args->response;
-
-	if (vivaldi_keybd && vivaldi_keybd->num_top_row_keys) {
-		memcpy(resp, vivaldi_keybd, sizeof(*resp));
-		args->response_size = sizeof(*resp);
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_ERROR;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBD_CONFIG, get_vivaldi_keybd_config,
-		     EC_VER_MASK(0));
-
-#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
-
-/*
- * Boards selecting CONFIG_KEYBOARD_CUSTOMIZATION are likely to not
- * want vivaldi code messing with their customized keyboards.
- */
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
-{
-	return NULL;
-}
-
-#else
-
-static const struct ec_response_keybd_config default_keybd = {
-	/* Default Chromeos keyboard config */
-	.num_top_row_keys = 10,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_FORWARD,		/* T2 */
-		TK_REFRESH,		/* T3 */
-		TK_FULLSCREEN,		/* T4 */
-		TK_OVERVIEW,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_VOL_MUTE,		/* T8 */
-		TK_VOL_DOWN,		/* T9 */
-		TK_VOL_UP,		/* T10 */
-	},
-	/* No function keys, no numeric keypad, has screenlock key */
-	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
-};
-
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
-{
-	return &default_keybd;
-}
-
-#endif /* CONFIG_KEYBOARD_CUSTOMIZATION */
-
-static void vivaldi_init(void)
-{
-	uint8_t i;
-
-	/* Allow the boards to change the keyboard config */
-	vivaldi_keybd = board_vivaldi_keybd_config();
-
-	if (!vivaldi_keybd || !vivaldi_keybd->num_top_row_keys) {
-		CPUTS("VIVALDI keybd disabled on board request");
-		return;
-	}
-
-	CPRINTS("VIVALDI: Num top row keys = %u",
-		vivaldi_keybd->num_top_row_keys);
-
-	if (vivaldi_keybd->num_top_row_keys > MAX_TOP_ROW_KEYS ||
-	    vivaldi_keybd->num_top_row_keys < MIN_TOP_ROW_KEYS) {
-		CPRINTS("VIVALDI: Error! num_top_row_keys=%u, disabled vivaldi",
-			vivaldi_keybd->num_top_row_keys);
-		vivaldi_keybd = NULL;
-		return;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(vivaldi_keys); i++) {
-
-		uint8_t row, col, *mask;
-		enum action_key key;
-
-		row = vivaldi_keys[i].row;
-		col = vivaldi_keys[i].col;
-
-		if (col >= KEYBOARD_COLS_MAX || row >= KEYBOARD_ROWS) {
-			CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)",
-				i, row, col);
-			ASSERT(false);
-		}
-
-		mask = &keyscan_config.actual_key_mask[col];
-
-		/*
-		 * Potentially indexing past meaningful data,
-		 * but we bounds check it below.
-		 */
-		key = vivaldi_keybd->action_keys[i];
-
-		if (i < vivaldi_keybd->num_top_row_keys && key != TK_ABSENT) {
-
-			/* Enable the mask */
-			*mask |= BIT(row);
-
-			/* Populate the scancode */
-			set_scancode_set2(row, col, action_scancodes[key]);
-			CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X",
-				i, row, col, action_scancodes[key]);
-
-			if (key == TK_VOL_UP)
-				set_vol_up_key(row, col);
-
-		}
-	}
-}
-DECLARE_HOOK(HOOK_INIT, vivaldi_init, HOOK_PRIO_DEFAULT);
diff --git a/common/lb_common.c b/common/lb_common.c
deleted file mode 100644
index 019e0e254f..0000000000
--- a/common/lb_common.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Lightbar IC interface
- *
- * Here's the API provided by this file.
- *
- * Looking at it from the outside, the lightbar has four "segments", each of
- * which can be independently adjusted to display a unique color such as blue,
- * purple, yellow, pinkish-white, etc. Segment 0 is on the left (looking
- * straight at it from behind).
- *
- * The lb_set_rgb() and lb_get_rgb() functions let you specify the color of a
- * segment using individual Red, Green, and Blue values in the 0x00 to 0xFF
- * range (see https://en.wikipedia.org/wiki/Web_color for background info).
- *
- * The lb_set_brightness() function provides a simple way to set the intensity,
- * over a range of 0x00 (off) to 0xFF (full brightness). It does this by
- * scaling each RGB value proportionally. For example, an RGB value of #FF8000
- * appears orange. To make the segment half as bright, you could specify a RGB
- * value of #7f4000, or you could leave the RGB value unchanged and just set
- * the brightness to 0x80.
- *
- * That covers most of the lb_* functions found in include/lb_common.h, and
- * those functions are what are used to implement the various colors and
- * sequences for displaying power state changes and other events.
- *
- * The internals are a little more messy.
- *
- * Each segment has three individual color emitters - red, green, and blue. A
- * single emitter may consist of 3 to 7 physical LEDs, but they are all wired
- * in parallel so there is only one wire that provides current for any one
- * color emitter. That makes a total of 12 current control wires for the
- * lightbar: four segments, three color emitters per segment.
- *
- * The ICs that we use each have seven independently adjustable
- * current-limiters. We use six of those current limiters (called "Independent
- * Sink Controls", or "ISC"s ) from each of two ICs to control the 12 color
- * emitters in the lightbar. The ICs are not identical, but they're close
- * enough that we can treat them the same. We call the ICs "controller 0" and
- * "controller 1".
- *
- * For no apparent reason, each Chromebook has wired the ICs and the ISCs
- * differently, so there are a couple of lookup tables that ensure that when we
- * call lb_set_rgb() to make segment 1 yellow, it looks the same on all
- * Chromebooks.
- *
- * Each ISC has a control register to set the amount of current that passes
- * through the color emitter control wire. We need to limit the max current so
- * that the current through each of the emitter's LEDs doesn't exceed the
- * manufacturer's specifications. For example, if a particular LED can't handle
- * more than 5 mA, and the emitter is made up of four LEDs in parallel, the
- * maxiumum limit for that particular ISC would be 20 mA.
- *
- * Although the specified maximum currents are usually similar, the three
- * different colors of LEDs have different brightnesses. For any given current,
- * green LEDs are pretty bright, red LEDS are medium, and blue are fairly dim.
- * So we calibrate the max current per ISC differently, depending on which
- * color it controls.
- *
- * First we set one segment to red, one to green, and one to blue, using the
- * ISC register to allow the max current per LED that the LED manufacturer
- * recommends. Then we adjust the current of the brighter segments downward
- * until all three segments appear equally bright to the eye. The MAX_RED,
- * MAX_BLUE, and MAX_GREEN values are the ISC control register values at this
- * point. This means that if we set all ISCs to their MAX_* values, all
- * segments should appear white.
- *
- * To translate the RGB values passed to lb_set_rgb() into ISC values, we
- * perform two transformations. The color value is first scaled according to
- * the current brightness setting, and then that intensity is scaled according
- * to the MAX_* value for the particular color. The result is the ISC register
- * value to use.
- *
- * To add lightbar support for a new Chromebook, you do the following:
- *
- * 1. Figure out the segment-to-IC and color-to-ISC mappings so that
- *    lb_set_rgb() does the same thing as on the other Chromebooks.
- *
- * 2. Calibrate the MAX_RED, MAX_GREEN, and MAX_BLUE values so that white looks
- *    white, and solid red, green, and blue all appear to be the same
- *    brightness.
- *
- * 3. Use lb_set_rgb() to set the colors to what *should be* the Google colors
- *    (at maximum brightness). Tweak the RGB values until the colors match,
- *    then edit common/lightbar.c to set them as the defaults.
- *
- * 4. Curse because the physical variation between the LEDs prevents you from
- *    getting everything exactly right: white looks bluish, yellow turns
- *    orange at lower brightness, segment 3 has a bright spot when displaying
- *    solid red, etc. Go back to step 2, and repeat until deadline.
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "lb_common.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
-
-/******************************************************************************/
-/* How to talk to the controller */
-/******************************************************************************/
-
-/* Since there's absolutely nothing we can do about it if an I2C access
- * isn't working, we're completely ignoring any failures. */
-
-static const uint16_t i2c_addr_flags[] = { 0x2A, 0x2B };
-
-static inline void controller_write(int ctrl_num, uint8_t reg, uint8_t val)
-{
-	uint8_t buf[2];
-
-	buf[0] = reg;
-	buf[1] = val;
-	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
-	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			buf, 2, 0, 0,
-			I2C_XFER_SINGLE);
-}
-
-static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
-{
-	uint8_t buf[1];
-	int rv;
-
-	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
-	rv = i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			&reg, 1, buf, 1, I2C_XFER_SINGLE);
-	return rv ? 0 : buf[0];
-}
-
-/******************************************************************************/
-/* Controller details. We have an ADP8861 and and ADP8863, but we can treat
- * them identically for our purposes */
-/******************************************************************************/
-
-#ifdef BOARD_BDS
-/* We need to limit the total current per ISC to no more than 20mA (5mA per
- * color LED, but we have four LEDs in parallel on each ISC). Any more than
- * that runs the risk of damaging the LED component. A value of 0x67 is as high
- * as we want (assuming Square Law), but the blue LED is the least bright, so
- * I've lowered the other colors until they all appear approximately equal
- * brightness when full on. That's still pretty bright and a lot of current
- * drain on the battery, so we'll probably rarely go that high. */
-#define MAX_RED   0x5c
-#define MAX_GREEN 0x30
-#define MAX_BLUE  0x67
-#endif
-#ifdef BOARD_HOST
-/* For testing only */
-#define MAX_RED   0xff
-#define MAX_GREEN 0xff
-#define MAX_BLUE  0xff
-#endif
-
-/* How we'd like to see the driver chips initialized. The controllers have some
- * auto-cycling capability, but it's not much use for our purposes. For now,
- * we'll just control all color changes actively. */
-struct initdata_s {
-	uint8_t reg;
-	uint8_t val;
-};
-
-static const struct initdata_s init_vals[] = {
-	{0x04, 0x00},				/* no backlight function */
-	{0x05, 0x3f},				/* xRGBRGB per chip */
-	{0x0f, 0x01},				/* square law looks better */
-	{0x10, 0x3f},				/* enable independent LEDs */
-	{0x11, 0x00},				/* no auto cycling */
-	{0x12, 0x00},				/* no auto cycling */
-	{0x13, 0x00},				/* instant fade in/out */
-	{0x14, 0x00},				/* not using LED 7 */
-	{0x15, 0x00},				/* current for LED 6 (blue) */
-	{0x16, 0x00},				/* current for LED 5 (red) */
-	{0x17, 0x00},				/* current for LED 4 (green) */
-	{0x18, 0x00},				/* current for LED 3 (blue) */
-	{0x19, 0x00},				/* current for LED 2 (red) */
-	{0x1a, 0x00},				/* current for LED 1 (green) */
-};
-
-/* Controller register lookup tables. */
-static const uint8_t led_to_ctrl[] = { 1, 1, 0, 0 };
-#ifdef BOARD_BDS
-static const uint8_t led_to_isc[] = { 0x18, 0x15, 0x18, 0x15 };
-#endif
-#ifdef BOARD_HOST
-/* For testing only */
-static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 };
-#endif
-
-/* Scale 0-255 into max value */
-static inline uint8_t scale_abs(int val, int max)
-{
-	return (val * max)/255;
-}
-
-/* This is the overall brightness control. */
-static int brightness = 0xc0;
-
-/* So that we can make brightness changes happen instantly, we need to track
- * the current values. The values in the controllers aren't very helpful. */
-static uint8_t current[NUM_LEDS][3];
-
-/* Scale 0-255 by brightness */
-static inline uint8_t scale(int val, int max)
-{
-	return scale_abs((val * brightness)/255, max);
-}
-
-/* Helper function to set one LED color and remember it for later */
-static void setrgb(int led, int red, int green, int blue)
-{
-	int ctrl, bank;
-	current[led][0] = red;
-	current[led][1] = green;
-	current[led][2] = blue;
-	ctrl = led_to_ctrl[led];
-	bank = led_to_isc[led];
-	i2c_lock(I2C_PORT_LIGHTBAR, 1);
-	controller_write(ctrl, bank, scale(blue, MAX_BLUE));
-	controller_write(ctrl, bank+1, scale(red, MAX_RED));
-	controller_write(ctrl, bank+2, scale(green, MAX_GREEN));
-	i2c_lock(I2C_PORT_LIGHTBAR, 0);
-}
-
-/* LEDs are numbered 0-3, RGB values should be in 0-255.
- * If you specify too large an LED, it sets them all. */
-void lb_set_rgb(unsigned int led, int red, int green, int blue)
-{
-	int i;
-	if (led >= NUM_LEDS)
-		for (i = 0; i < NUM_LEDS; i++)
-			setrgb(i, red, green, blue);
-	else
-		setrgb(led, red, green, blue);
-}
-
-/* Get current LED values, if the LED number is in range. */
-int lb_get_rgb(unsigned int led, uint8_t *red, uint8_t *green, uint8_t *blue)
-{
-	if (led < 0 || led >= NUM_LEDS)
-		return EC_RES_INVALID_PARAM;
-
-	*red = current[led][0];
-	*green = current[led][1];
-	*blue = current[led][2];
-
-	return EC_RES_SUCCESS;
-}
-
-/* Change current display brightness (0-255) */
-void lb_set_brightness(unsigned int newval)
-{
-	int i;
-	CPRINTS("LB_bright 0x%02x", newval);
-	brightness = newval;
-	for (i = 0; i < NUM_LEDS; i++)
-		setrgb(i, current[i][0], current[i][1], current[i][2]);
-}
-
-/* Get current display brightness (0-255) */
-uint8_t lb_get_brightness(void)
-{
-	return brightness;
-}
-
-/* Initialize the controller ICs after reset */
-void lb_init(int use_lock)
-{
-	int i;
-
-	CPRINTF("[%pT LB_init_vals ", PRINTF_TIMESTAMP_NOW);
-	for (i = 0; i < ARRAY_SIZE(init_vals); i++) {
-		CPRINTF("%c", '0' + i % 10);
-		if (use_lock)
-			i2c_lock(I2C_PORT_LIGHTBAR, 1);
-		controller_write(0, init_vals[i].reg, init_vals[i].val);
-		controller_write(1, init_vals[i].reg, init_vals[i].val);
-		if (use_lock)
-			i2c_lock(I2C_PORT_LIGHTBAR, 0);
-	}
-	CPRINTF("]\n");
-	memset(current, 0, sizeof(current));
-}
-
-/* Just go into standby mode. No register values should change. */
-void lb_off(void)
-{
-	CPRINTS("LB_off");
-	i2c_lock(I2C_PORT_LIGHTBAR, 1);
-	controller_write(0, 0x01, 0x00);
-	controller_write(1, 0x01, 0x00);
-	i2c_lock(I2C_PORT_LIGHTBAR, 0);
-}
-
-/* Come out of standby mode. */
-void lb_on(void)
-{
-	CPRINTS("LB_on");
-	i2c_lock(I2C_PORT_LIGHTBAR, 1);
-	controller_write(0, 0x01, 0x20);
-	controller_write(1, 0x01, 0x20);
-	i2c_lock(I2C_PORT_LIGHTBAR, 0);
-}
-
-static const uint8_t dump_reglist[] = {
-	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0a,			  0x0f,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1a
-};
-
-/* Helper for host command to dump controller registers */
-void lb_hc_cmd_dump(struct ec_response_lightbar *out)
-{
-	int i;
-	uint8_t reg;
-
-	BUILD_ASSERT(ARRAY_SIZE(dump_reglist) ==
-		     ARRAY_SIZE(out->dump.vals));
-
-	for (i = 0; i < ARRAY_SIZE(dump_reglist); i++) {
-		reg = dump_reglist[i];
-		out->dump.vals[i].reg = reg;
-		i2c_lock(I2C_PORT_LIGHTBAR, 1);
-		out->dump.vals[i].ic0 = controller_read(0, reg);
-		out->dump.vals[i].ic1 = controller_read(1, reg);
-		i2c_lock(I2C_PORT_LIGHTBAR, 0);
-	}
-}
-
-/* Helper for host command to write controller registers directly */
-void lb_hc_cmd_reg(const struct ec_params_lightbar *in)
-{
-	i2c_lock(I2C_PORT_LIGHTBAR, 1);
-	controller_write(in->reg.ctrl, in->reg.reg, in->reg.value);
-	i2c_lock(I2C_PORT_LIGHTBAR, 0);
-}
diff --git a/common/led_common.c b/common/led_common.c
deleted file mode 100644
index 85879b148f..0000000000
--- a/common/led_common.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for blinking LEDs.
- */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "util.h"
-
-#define LED_AUTO_CONTROL_FLAG(id) (1 << (id))
-
-static uint32_t led_auto_control_flags = ~0x00;
-
-static int led_is_supported(enum ec_led_id led_id)
-{
-	int i;
-	static int supported_leds = -1;
-
-	if (supported_leds == -1) {
-		supported_leds = 0;
-
-		for (i = 0; i < supported_led_ids_count; i++)
-			supported_leds |= (1 << supported_led_ids[i]);
-	}
-
-	return ((1 << (int)led_id) & supported_leds);
-}
-
-void led_auto_control(enum ec_led_id led_id, int enable)
-{
-	if (enable)
-		led_auto_control_flags |= LED_AUTO_CONTROL_FLAG(led_id);
-	else
-		led_auto_control_flags &= ~LED_AUTO_CONTROL_FLAG(led_id);
-}
-
-int led_auto_control_is_enabled(enum ec_led_id led_id)
-{
-	if (!led_is_supported(led_id))
-		return 0;
-
-	return (led_auto_control_flags & LED_AUTO_CONTROL_FLAG(led_id)) != 0;
-}
-
-static enum ec_status led_command_control(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_led_control *p = args->params;
-	struct ec_response_led_control *r = args->response;
-	int i;
-
-	args->response_size = sizeof(*r);
-	memset(r->brightness_range, 0, sizeof(r->brightness_range));
-
-	if (!led_is_supported(p->led_id))
-		return EC_RES_INVALID_PARAM;
-
-	led_get_brightness_range(p->led_id, r->brightness_range);
-	if (p->flags & EC_LED_FLAGS_QUERY)
-		return EC_RES_SUCCESS;
-
-	for (i = 0; i < EC_LED_COLOR_COUNT; i++)
-		if (r->brightness_range[i] == 0 && p->brightness[i] != 0)
-			return EC_RES_INVALID_PARAM;
-
-	if (p->flags & EC_LED_FLAGS_AUTO) {
-		led_auto_control(p->led_id, 1);
-	} else {
-		if (led_set_brightness(p->led_id, p->brightness) != EC_SUCCESS)
-			return EC_RES_INVALID_PARAM;
-		led_auto_control(p->led_id, 0);
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_LED_CONTROL, led_command_control, EC_VER_MASK(1));
-
-__attribute__((weak))
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	/*
-	 * Default weak implementation that does not affect the state of
-	 * LED. Boards can provide their own implementation.
-	 */
-}
diff --git a/common/led_onoff_states.c b/common/led_onoff_states.c
deleted file mode 100644
index 48886e5de3..0000000000
--- a/common/led_onoff_states.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED state control
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * In order to support the battery LED being optional (ex. for Chromeboxes),
- * set up default battery table, setter, and variables.
- */
-__overridable struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
-__overridable const int led_charge_lvl_1;
-__overridable const int led_charge_lvl_2;
-__overridable void led_set_color_battery(enum ec_led_colors color)
-{
-}
-
-#ifndef CONFIG_CHARGER
-/* Include for the sake of compilation */
-int charge_get_percent(void);
-#endif
-
-static int led_get_charge_percent(void)
-{
-	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-}
-
-static enum led_states led_get_state(void)
-{
-	int  charge_lvl;
-	enum led_states new_state = LED_NUM_STATES;
-
-	if (!IS_ENABLED(CONFIG_CHARGER))
-		return new_state;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Get percent charge */
-		charge_lvl = led_get_charge_percent();
-		/* Determine which charge state to use */
-		if (charge_lvl < led_charge_lvl_1)
-			new_state = STATE_CHARGING_LVL_1;
-		else if (charge_lvl < led_charge_lvl_2)
-			new_state = STATE_CHARGING_LVL_2;
-		else
-			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-				new_state = STATE_CHARGING_FULL_S5;
-			else
-				new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-				new_state = STATE_CHARGING_FULL_S5;
-			else
-				new_state = STATE_CHARGING_FULL_CHARGE;
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
-		if (chipset_in_state(CHIPSET_STATE_ON)) {
-#ifdef CONFIG_LED_ONOFF_STATES_BAT_LOW
-			if (led_get_charge_percent() <
-				CONFIG_LED_ONOFF_STATES_BAT_LOW)
-				new_state = STATE_DISCHARGE_S0_BAT_LOW;
-			else
-#endif
-				new_state = STATE_DISCHARGE_S0;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			new_state = STATE_DISCHARGE_S3;
-		else
-			new_state = STATE_DISCHARGE_S5;
-		break;
-	case PWR_STATE_ERROR:
-		new_state = STATE_BATTERY_ERROR;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			new_state = STATE_CHARGING_FULL_S5;
-		else
-			new_state = STATE_CHARGING_FULL_CHARGE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			new_state = STATE_DISCHARGE_S5;
-		else
-			new_state = STATE_DISCHARGE_S0;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	return new_state;
-}
-
-__overridable enum led_states board_led_get_state(enum led_states desired_state)
-{
-	return desired_state;
-}
-
-static void led_update_battery(void)
-{
-	static uint8_t ticks, period;
-	static int led_state = LED_NUM_STATES;
-	int phase;
-	enum led_states desired_state = led_get_state();
-
-	desired_state = board_led_get_state(desired_state);
-
-	/*
-	 * We always need to check the current state since the value could
-	 * have been manually overwritten. If we're in a new valid state,
-	 * update our ticks and period info. If our new state isn't defined,
-	 * continue using the previous one.
-	 */
-	if (desired_state != led_state && desired_state < LED_NUM_STATES) {
-		/*
-		 * Allow optional CHARGING_FULL_S5 state to fall back to
-		 * FULL_CHARGE if not defined.
-		 */
-		if (desired_state == STATE_CHARGING_FULL_S5 &&
-		    led_bat_state_table[desired_state][LED_PHASE_0].time == 0)
-			desired_state = STATE_CHARGING_FULL_CHARGE;
-
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
-		led_set_color_battery(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_battery(led_bat_state_table[led_state][phase].color);
-}
-
-/*
- * In order to support the power LED being optional, set up default power LED
- * table and setter
- */
-__overridable const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
-__overridable void led_set_color_power(enum ec_led_colors color)
-{
-}
-
-static enum pwr_led_states pwr_led_get_state(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		if (extpower_is_present())
-			return PWR_LED_STATE_SUSPEND_AC;
-		else
-			return PWR_LED_STATE_SUSPEND_NO_AC;
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		if (system_can_boot_ap())
-			return PWR_LED_STATE_OFF;
-		else
-			return PWR_LED_STATE_OFF_LOW_POWER;
-	} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-		return PWR_LED_STATE_ON;
-	}
-
-	return PWR_LED_NUM_STATES;
-}
-
-static void led_update_power(void)
-{
-	static uint8_t ticks, period;
-	static enum pwr_led_states led_state = PWR_LED_NUM_STATES;
-	int phase;
-	enum pwr_led_states desired_state = pwr_led_get_state();
-
-	/*
-	 * If we're in a new valid state, update our ticks and period info.
-	 * Otherwise, continue to use old state
-	 */
-	if (desired_state != led_state && desired_state < PWR_LED_NUM_STATES) {
-		/*
-		 * Allow optional OFF_LOW_POWER state to fall back to
-		 * OFF not defined, as indicated by no specified phase 0 time.
-		 */
-		if (desired_state == PWR_LED_STATE_OFF_LOW_POWER &&
-		    led_pwr_state_table[desired_state][LED_PHASE_0].time == 0)
-			desired_state = PWR_LED_STATE_OFF;
-
-		/* State is changing */
-		led_state = desired_state;
-		/* Reset ticks and period when state changes */
-		ticks = 0;
-
-		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
-	}
-
-	/* If this state is undefined, turn the LED off */
-	if (period == 0) {
-		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
-		led_set_color_power(LED_OFF);
-		return;
-	}
-
-	/*
-	 * Determine which phase of the state table to use. The phase is
-	 * determined if it falls within first phase time duration.
-	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
-	ticks = (ticks + 1) % period;
-
-	/* Set the color for the given state and phase */
-	led_set_color_power(led_pwr_state_table[led_state][phase].color);
-
-}
-
-static void led_init(void)
-{
-	/* If battery LED is enabled, set it to "off" to start with */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_color_battery(LED_OFF);
-
-	/* If power LED is enabled, set it to "off" to start with */
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_color_power(LED_OFF);
-
-}
-DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
-
-/* Called by hook task every hook tick (200 msec) */
-static void led_update(void)
-{
-	/*
-	 * If battery LED is enabled, set its state based on our power and
-	 * charge
-	 */
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_update_battery();
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_update_power();
-}
-DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT);
diff --git a/common/led_policy_std.c b/common/led_policy_std.c
deleted file mode 100644
index e9fe4568a2..0000000000
--- a/common/led_policy_std.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Standard Battery LED and Power LED control
- * This assumes a red/green battery led and a single power led.
- */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "led_common.h"
-#include "util.h"
-#include "lid_switch.h"
-
-#ifdef CONFIG_LED_BAT_ACTIVE_LOW
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
-#else
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-#endif
-
-#ifdef CONFIG_LED_POWER_ACTIVE_LOW
-#define POWER_LED_ON 0
-#define POWER_LED_OFF 1
-#else
-#define POWER_LED_ON 1
-#define POWER_LED_OFF 0
-#endif
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_AMBER,
-	LED_GREEN,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static int bat_led_set_color(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		break;
-	case LED_RED:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
-		break;
-	case LED_GREEN:
-		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int pwr_led_set_color(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_POWER_LED, POWER_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_POWER_LED,
-			       lid_is_open() ? POWER_LED_ON : POWER_LED_OFF);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		brightness_range[EC_LED_COLOR_RED] = 1;
-		brightness_range[EC_LED_COLOR_GREEN] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		/* ignore */
-		break;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		gpio_set_level(GPIO_BAT_LED_RED,
-			       (brightness[EC_LED_COLOR_RED] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_GREEN,
-			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
-		break;
-	case EC_LED_ID_POWER_LED:
-		gpio_set_level(GPIO_POWER_LED,
-			       (brightness[EC_LED_COLOR_WHITE] != 0) ?
-					POWER_LED_ON : POWER_LED_OFF);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-#ifdef HAS_TASK_CHIPSET
-static void std_led_shutdown(void)
-{
-	pwr_led_set_color(LED_OFF);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, std_led_shutdown, HOOK_PRIO_DEFAULT);
-#endif
-
-static void std_led_set_power(void)
-{
-	static int power_second;
-
-	power_second++;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		pwr_led_set_color(LED_OFF);
-	else if (chipset_in_state(CHIPSET_STATE_ON))
-		pwr_led_set_color(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		pwr_led_set_color((power_second & 3) ? LED_OFF : LED_WHITE);
-}
-
-static void std_led_set_battery(void)
-{
-	static int battery_second;
-	uint32_t chflags = charge_get_flags();
-
-	battery_second++;
-
-	/* BAT LED behavior:
-	 * Same as the chromeos spec
-	 * Green/Amber for CHARGE_FLAG_FORCE_IDLE
-	 */
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		bat_led_set_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
-		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
-		else
-			bat_led_set_color(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		bat_led_set_color((battery_second & 1) ? LED_OFF : LED_RED);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		bat_led_set_color(LED_GREEN);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/**  * Called by hook task every 1 sec  */
-static void led_second(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		std_led_set_power();
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		std_led_set_battery();
-}
-DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);
-
diff --git a/common/led_pwm.c b/common/led_pwm.c
deleted file mode 100644
index cc946ba522..0000000000
--- a/common/led_pwm.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM LED control to conform to Chrome OS LED behaviour specification. */
-
-/*
- * This assumes that a single logical LED is shared between both power and
- * charging/battery status.  If multiple logical LEDs are present, they all
- * follow the same patterns.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "led_common.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "timer.h"
-#include "util.h"
-
-/* Battery percentage thresholds to blink at different rates. */
-#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
-#define LOW_BATTERY_PERCENTAGE 10
-
-#define PULSE_TICK (250 * MSEC)
-
-static uint8_t led_is_pulsing;
-
-static int get_led_id_color(enum pwm_led_id id, int color)
-{
-#ifdef CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
-	int active_chg_port = charge_manager_get_active_charge_port();
-
-	/* We should always be able to turn off a LED. */
-	if (color == -1)
-		return -1;
-
-	if (led_is_pulsing)
-		return color;
-
-	/* The inactive charge port LEDs should be off. */
-	if ((int)id != active_chg_port)
-		return -1;
-#endif /* CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY */
-	return color;
-}
-
-void set_pwm_led_color(enum pwm_led_id id, int color)
-{
-	struct pwm_led duty = { 0 };
-	const struct pwm_led *led = &pwm_leds[id];
-
-	if ((id >= CONFIG_LED_PWM_COUNT) || (id < 0) ||
-	    (color >= EC_LED_COLOR_COUNT) || (color < -1))
-		return;
-
-	if (color != -1) {
-		duty.ch0 = led_color_map[color].ch0;
-		duty.ch1 = led_color_map[color].ch1;
-		duty.ch2 = led_color_map[color].ch2;
-	}
-
-	if (led->ch0 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->set_duty(led->ch0, duty.ch0);
-	if (led->ch1 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->set_duty(led->ch1, duty.ch1);
-	if (led->ch2 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->set_duty(led->ch2, duty.ch2);
-}
-
-static void set_led_color(int color)
-{
-	/*
-	 *  We must check if auto control is enabled since the LEDs may be
-	 *  controlled from the AP at anytime.
-	 */
-	if ((led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) ||
-	    (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)))
-		set_pwm_led_color(PWM_LED0, get_led_id_color(PWM_LED0, color));
-
-#if CONFIG_LED_PWM_COUNT >= 2
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		set_pwm_led_color(PWM_LED1, get_led_id_color(PWM_LED1, color));
-#endif /* CONFIG_LED_PWM_COUNT >= 2 */
-}
-
-static void set_pwm_led_enable(enum pwm_led_id id, int enable)
-{
-	const struct pwm_led *led = &pwm_leds[id];
-
-	if ((id >= CONFIG_LED_PWM_COUNT) || (id < 0))
-		return;
-
-	if (led->ch0 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->enable(led->ch0, enable);
-	if (led->ch1 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->enable(led->ch1, enable);
-	if (led->ch2 != (enum pwm_channel)PWM_LED_NO_CHANNEL)
-		led->enable(led->ch2, enable);
-}
-
-static void init_leds_off(void)
-{
-	/* Turn off LEDs such that they are in a known state with zero duty. */
-	set_led_color(-1);
-
-	/* Enable pwm modules for each channels of LEDs */
-	set_pwm_led_enable(PWM_LED0, 1);
-
-#if CONFIG_LED_PWM_COUNT >= 2
-	set_pwm_led_enable(PWM_LED1, 1);
-#endif /* CONFIG_LED_PWM_COUNT >= 2 */
-}
-DECLARE_HOOK(HOOK_INIT, init_leds_off, HOOK_PRIO_INIT_PWM + 1);
-
-static uint8_t pulse_period;
-static uint8_t pulse_ontime;
-static enum ec_led_colors pulse_color;
-static void update_leds(void);
-static void pulse_leds_deferred(void);
-DECLARE_DEFERRED(pulse_leds_deferred);
-static void pulse_leds_deferred(void)
-{
-	static uint8_t tick_count;
-
-	if (!led_is_pulsing) {
-		tick_count = 0;
-		/*
-		 * Since we're not pulsing anymore, turn the colors off in case
-		 * we were in the "on" time.
-		 */
-		set_led_color(-1);
-		/* Then show the desired state. */
-		update_leds();
-		return;
-	}
-
-	if (tick_count < pulse_ontime)
-		set_led_color(pulse_color);
-	else
-		set_led_color(-1);
-
-	tick_count = (tick_count + 1) % pulse_period;
-	hook_call_deferred(&pulse_leds_deferred_data, PULSE_TICK);
-}
-
-static void pulse_leds(enum ec_led_colors color, int ontime, int period)
-{
-	pulse_color = color;
-	pulse_ontime = ontime;
-	pulse_period = period;
-	led_is_pulsing = 1;
-	pulse_leds_deferred();
-}
-
-static int show_charge_state(void)
-{
-	enum charge_state chg_st = charge_get_state();
-
-	/*
-	 * The colors listed below are the default, but can be overridden.
-	 *
-	 * Solid Amber == Charging
-	 * Solid Green == Charging (near full)
-	 * Fast Flash Red == Charging error or battery not present
-	 */
-	if (chg_st == PWR_STATE_CHARGE) {
-		led_is_pulsing = 0;
-		set_led_color(CONFIG_LED_PWM_CHARGE_COLOR);
-	} else if (chg_st == PWR_STATE_CHARGE_NEAR_FULL ||
-		   chg_st == PWR_STATE_DISCHARGE_FULL) {
-		led_is_pulsing = 0;
-		set_led_color(CONFIG_LED_PWM_NEAR_FULL_COLOR);
-	} else if ((battery_is_present() != BP_YES) ||
-		   (chg_st == PWR_STATE_ERROR)) {
-		/* 500 ms period, 50% duty cycle. */
-		pulse_leds(CONFIG_LED_PWM_CHARGE_ERROR_COLOR, 1, 2);
-	} else {
-		/* Discharging or not charging. */
-#ifdef CONFIG_LED_PWM_CHARGE_STATE_ONLY
-		/*
-		 * If we only show the charge state, the only reason we
-		 * would pulse the LEDs is if we had an error.  If it no longer
-		 * exists, stop pulsing the LEDs.
-		 */
-		led_is_pulsing = 0;
-#endif /* CONFIG_LED_PWM_CHARGE_STATE_ONLY */
-		return 0;
-	}
-	return 1;
-}
-
-#ifndef CONFIG_LED_PWM_CHARGE_STATE_ONLY
-static int show_battery_state(void)
-{
-	int batt_percentage = charge_get_percent();
-
-	/*
-	 * The colors listed below are the default, but can be overridden.
-	 *
-	 * Fast Flash Amber == Critical Battery
-	 * Slow Flash Amber == Low Battery
-	 */
-	if (batt_percentage < CRITICAL_LOW_BATTERY_PERCENTAGE) {
-		/* Flash amber faster (1 second period, 50% duty cycle) */
-		pulse_leds(CONFIG_LED_PWM_LOW_BATT_COLOR, 2, 4);
-	} else if (batt_percentage < LOW_BATTERY_PERCENTAGE) {
-		/* Flash amber (4 second period, 50% duty cycle) */
-		pulse_leds(CONFIG_LED_PWM_LOW_BATT_COLOR, 8, 16);
-	} else {
-		/* Sufficient charge, no need to show anything for this. */
-		return 0;
-	}
-	return 1;
-}
-
-static int show_chipset_state(void)
-{
-	/* Reflect the SoC state. */
-	led_is_pulsing = 0;
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* The LED must be on in the Active state. */
-		set_led_color(CONFIG_LED_PWM_SOC_ON_COLOR);
-	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-		/* The power LED must pulse in the suspend state. */
-		pulse_leds(CONFIG_LED_PWM_SOC_SUSPEND_COLOR, 4, 16);
-	} else {
-		/* Chipset is off, no need to show anything for this. */
-		return 0;
-	}
-	return 1;
-}
-#endif /* CONFIG_LED_PWM_CHARGE_STATE_ONLY */
-
-static void update_leds(void)
-{
-	/* Reflecting the charge state is the highest priority. */
-	if (show_charge_state())
-		return;
-
-#ifndef CONFIG_LED_PWM_CHARGE_STATE_ONLY
-	if (show_battery_state())
-		return;
-
-	if (show_chipset_state())
-		return;
-#endif /* CONFIG_LED_PWM_CHARGE_STATE_ONLY */
-
-	set_led_color(-1);
-}
-DECLARE_HOOK(HOOK_TICK, update_leds, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CMD_LEDTEST
-int command_ledtest(int argc, char **argv)
-{
-	int enable;
-	int pwm_led_id;
-	int led_id;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	pwm_led_id = atoi(argv[1]);
-	if ((pwm_led_id < 0) || (pwm_led_id >= CONFIG_LED_PWM_COUNT))
-		return EC_ERROR_PARAM1;
-	led_id = supported_led_ids[pwm_led_id];
-
-	if (argc == 2) {
-		ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n",
-			 pwm_led_id, led_id,
-			 led_auto_control_is_enabled(led_id) != 0);
-		return EC_SUCCESS;
-	}
-	if (!parse_bool(argv[2], &enable))
-		return EC_ERROR_PARAM2;
-
-	/* Inverted because this drives auto control. */
-	led_auto_control(led_id, !enable);
-
-	if (argc == 4) {
-		/* Set the color. */
-		if (!strncmp(argv[3], "red", 3))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_RED);
-		else if (!strncmp(argv[3], "green", 5))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_GREEN);
-		else if (!strncmp(argv[3], "amber", 5))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_AMBER);
-		else if (!strncmp(argv[3], "blue", 4))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_BLUE);
-		else if (!strncmp(argv[3], "white", 5))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_WHITE);
-		else if (!strncmp(argv[3], "yellow", 6))
-			set_pwm_led_color(pwm_led_id, EC_LED_COLOR_YELLOW);
-		else if (!strncmp(argv[3], "off", 3))
-			set_pwm_led_color(pwm_led_id, -1);
-		else
-			return EC_ERROR_PARAM3;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ledtest, command_ledtest,
-			"<pwm led idx> <enable|disable> [color|off]", "");
-#endif /* defined(CONFIG_CMD_LEDTEST) */
diff --git a/common/lid_angle.c b/common/lid_angle.c
deleted file mode 100644
index 8a3775b959..0000000000
--- a/common/lid_angle.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lid angle module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_angle.h"
-#include "lid_switch.h"
-#include "math_util.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "tablet_mode.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LIDANGLE, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ## args)
-
-/*
- * Define the number of previous lid angle measurements to keep for determining
- * whether to enable or disable peripherals that are only needed for laptop
- * mode. These incude keyboard and trackpad. Note, that in order to change the
- * enable/disable state of these peripherals, all stored measurements of the
- * lid angle buffer must be in the specified range.
- */
-#define LID_ANGLE_BUFFER_SIZE 4
-
-/*
- * Define two variables to determine if wake source peripherals that are only
- * applicable for laptop mode should be enabled or disabled in S3 based on the
- * current lid angle. Note, the lid angle is bound to [0, 360]. Here are two
- * angles, defined such that we segregate the lid angle space into two regions.
- * The first region is the region in which we enable peripherals in S3 and is
- * when the lid angle CCW of the small_angle and CW of the large_angle. The
- * second region is the region in which we disable peripherals in S3 and is when
- * the lid angle is CCW of the large_angle and CW of the small_angle.
- *
- * Note, the most sensical values are small_angle = 0 and large_angle = 180,
- * but, the angle measurement is not perfect, and we know that if the angle is
- * near 0 and the lid isn't closed, then the lid must be near 360. So, the
- * small_angle is set to a small positive value to make sure we don't swap modes
- * when the lid is open all the way but is measuring a small positive value.
- */
-static int wake_large_angle = 180;
-static const int wake_small_angle = 13;
-
-/* Define hysteresis value to add stability to the flags. */
-#define LID_ANGLE_HYSTERESIS_DEG  2
-
-/* Define max and min values for wake_large_angle. */
-#define LID_ANGLE_MIN_LARGE_ANGLE 0
-#define LID_ANGLE_MAX_LARGE_ANGLE 360
-
-/**
- * Determine if given angle is in region to enable peripherals.
- *
- * @param ang Some lid angle in degrees [0, 360]
- *
- * @return true/false
- */
-static int lid_in_range_to_enable_peripherals(int ang)
-{
-	/*
-	 * If the wake large angle is min or max, then this function should
-	 * return false or true respectively, independent of input angle.
-	 */
-	if (wake_large_angle == LID_ANGLE_MIN_LARGE_ANGLE)
-		return 0;
-	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
-		return 1;
-
-	return  (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) &&
-		(ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG));
-}
-
-/**
- * Determine if given angle is in region to ignore peripherals.
- *
- * @param ang Some lid angle in degrees [0, 360]
- *
- * @return true/false
- */
-static int lid_in_range_to_ignore_peripherals(int ang)
-{
-	/*
-	 * If the wake large angle is min or max, then this function should
-	 * return true or false respectively, independent of input angle.
-	 */
-	if (wake_large_angle == LID_ANGLE_MIN_LARGE_ANGLE)
-		return 1;
-	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
-		return 0;
-
-	return  (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) ||
-		(ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG));
-}
-
-
-int lid_angle_get_wake_angle(void)
-{
-	return wake_large_angle;
-}
-
-void lid_angle_set_wake_angle(int ang)
-{
-	if (ang < LID_ANGLE_MIN_LARGE_ANGLE)
-		ang = LID_ANGLE_MIN_LARGE_ANGLE;
-	else if (ang > LID_ANGLE_MAX_LARGE_ANGLE)
-		ang = LID_ANGLE_MAX_LARGE_ANGLE;
-
-	wake_large_angle = ang;
-}
-
-void lid_angle_update(int lid_ang)
-{
-	static int lidangle_buffer[LID_ANGLE_BUFFER_SIZE];
-	static int index;
-	int i;
-	int accept = 1, ignore = 1;
-
-	/* Record most recent lid angle in circular buffer. */
-	lidangle_buffer[index] = lid_ang;
-	index = (index == LID_ANGLE_BUFFER_SIZE-1) ? 0 : index+1;
-
-	/*
-	 * Manage whether or not peripherals are enabled based on lid angle
-	 * history.
-	 */
-	for (i = 0; i < LID_ANGLE_BUFFER_SIZE; i++) {
-		/*
-		 * If any lid angle samples are unreliable, then
-		 * don't change peripheral state.
-		 */
-		if (lidangle_buffer[i] == LID_ANGLE_UNRELIABLE)
-			return;
-
-		/*
-		 * Force all elements of the lid angle buffer to be
-		 * in range of one of the conditions in order to change
-		 * to the corresponding peripheral state.
-		 */
-		if (!lid_in_range_to_enable_peripherals(lidangle_buffer[i]))
-			accept = 0;
-		if (!lid_in_range_to_ignore_peripherals(lidangle_buffer[i]))
-			ignore = 0;
-	}
-
-	/* Enable or disable peripherals as necessary. */
-	if (accept)
-		lid_angle_peripheral_enable(1);
-	else if (ignore && !accept)
-		lid_angle_peripheral_enable(0);
-}
-
-static void enable_peripherals(void)
-{
-	/*
-	 * Make sure lid angle is not disabling peripherals when AP is running.
-	 */
-	lid_angle_peripheral_enable(1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_peripherals, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_TABLET_MODE
-static void suspend_peripherals(void)
-{
-	/*
-	 * Make sure peripherals are disabled in S3 in tablet mode.
-	 */
-	if (tablet_get_mode())
-		lid_angle_peripheral_enable(0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, suspend_peripherals, HOOK_PRIO_DEFAULT);
-#endif /* CONFIG_TABLET_MODE */
-
-#ifdef TEST_BUILD
-__overridable void lid_angle_peripheral_enable(int enable)
-{
-}
-#else
-__overridable void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-#endif /* TEST_BUILD */
diff --git a/common/lightbar.c b/common/lightbar.c
deleted file mode 100644
index f80287941d..0000000000
--- a/common/lightbar.c
+++ /dev/null
@@ -1,2068 +0,0 @@
-/*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LED controls.
- */
-
-#ifdef LIGHTBAR_SIMULATION
-#include "simulation.h"
-#else
-#include "battery.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lb_common.h"
-#include "lightbar.h"
-#include "lid_switch.h"
-#include "motion_sense.h"
-#include "pwm.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#endif
-
-/*
- * The Link lightbar had no version command, so defaulted to zero. We have
- * added a couple of new commands, so we've updated the version. Any
- * optional features in the current version should be marked with flags.
- */
-#define LIGHTBAR_IMPLEMENTATION_VERSION 1
-#define LIGHTBAR_IMPLEMENTATION_FLAGS   0
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
-
-#define FP_SCALE 10000
-
-/******************************************************************************/
-/* Here's some state that we might want to maintain across sysjumps, just to
- * prevent the lightbar from flashing during normal boot as the EC jumps from
- * RO to RW. */
-static struct p_state {
-	/* What patterns are we showing? */
-	enum lightbar_sequence cur_seq;
-	enum lightbar_sequence prev_seq;
-
-	/* Quantized battery charge level: 0=low 1=med 2=high 3=full. */
-	int battery_level;
-	int battery_percent;
-
-	/* It's either charging or discharging. */
-	int battery_is_charging;
-
-	/* Is power-on prevented due to battery level? */
-	int battery_is_power_on_prevented;
-
-	/* Pattern variables for state S0. */
-	uint16_t w0;				/* primary phase */
-	uint8_t ramp;				/* ramp-in for S3->S0 */
-
-	uint8_t _pad0;				/* next item is __packed */
-
-	/* Tweakable parameters. */
-	union {
-		struct lightbar_params_v1 p;
-		struct {
-			struct lightbar_params_v2_timing timing;
-			struct lightbar_params_v2_tap tap;
-			struct lightbar_params_v2_oscillation osc;
-			struct lightbar_params_v2_brightness bright;
-			struct lightbar_params_v2_thresholds thlds;
-			struct lightbar_params_v2_colors colors;
-		} p_v2;
-	};
-} st;
-
-/* Each of the parameters must be less than 120 bytes
- * (crbug.com/467716)
- */
-#define MAX_PARAM_SIZE 120
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_timing) <= MAX_PARAM_SIZE);
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_tap) <= MAX_PARAM_SIZE);
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_oscillation) <= MAX_PARAM_SIZE);
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_brightness) <= MAX_PARAM_SIZE);
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_thresholds) <= MAX_PARAM_SIZE);
-BUILD_ASSERT(sizeof(struct lightbar_params_v2_colors) <= MAX_PARAM_SIZE);
-#undef MAX_PARAM_SIZE
-
-#define PRIMARY_BLUE 4
-#define PRIMARY_RED 5
-#define PRIMARY_YELLOW 6
-#define PRIMARY_GREEN 7
-
-static const struct lightbar_params_v1 default_params = {
-	.google_ramp_up = 2500,
-	.google_ramp_down = 10000,
-	.s3s0_ramp_up = 2000,
-	.s0_tick_delay = { 45000, 30000 },	/* battery, AC */
-	.s0a_tick_delay = { 5000, 3000 },	/* battery, AC */
-	.s0s3_ramp_down = 2000,
-	.s3_sleep_for = 5 * SECOND,		/* between checks */
-	.s3_ramp_up = 2500,
-	.s3_ramp_down = 10000,
-	.s5_ramp_up = 2500,
-	.s5_ramp_down = 10000,
-	.tap_tick_delay = 5000,			/* oscillation step time */
-	.tap_gate_delay = 200 * MSEC,		/* segment gating delay */
-	.tap_display_time = 3 * SECOND,		/* total sequence time */
-
-	/* TODO (crosbug.com/p/36996): remove unused tap_pct_red */
-	.tap_pct_red = 14,			/* below this is red */
-	.tap_pct_green = 94,			/* above this is green */
-	.tap_seg_min_on = 35,		        /* min intensity (%) for "on" */
-	.tap_seg_max_on = 100,			/* max intensity (%) for "on" */
-	.tap_seg_osc = 50,			/* amplitude for charging osc */
-	.tap_idx = {PRIMARY_RED, PRIMARY_YELLOW, PRIMARY_GREEN}, /* color */
-
-	.osc_min = { 0x60, 0x60 },		/* battery, AC */
-	.osc_max = { 0xd0, 0xd0 },		/* battery, AC */
-	.w_ofs = {24, 24},			/* phase offset, 256 == 2*PI */
-
-	.bright_bl_off_fixed = {0xcc, 0xff},	/* backlight off: battery, AC */
-	.bright_bl_on_min = {0xcc, 0xff},	/* backlight on: battery, AC */
-	.bright_bl_on_max = {0xcc, 0xff},	/* backlight on: battery, AC */
-
-	.battery_threshold = { 14, 40, 99 },	/* percent, lowest to highest */
-	.s0_idx = {
-		/* battery: 0 = red, other = blue */
-		{ PRIMARY_RED, PRIMARY_BLUE, PRIMARY_BLUE, PRIMARY_BLUE },
-		/* AC: always blue */
-		{ PRIMARY_BLUE, PRIMARY_BLUE, PRIMARY_BLUE, PRIMARY_BLUE }
-	},
-	.s3_idx = {
-		/* battery: 0 = red, else off */
-		{ PRIMARY_RED, 0xff, 0xff, 0xff },
-		/* AC: do nothing */
-		{ 0xff, 0xff, 0xff, 0xff }
-	},
-	.s5_idx = PRIMARY_RED,			       /* flash red */
-	.color = {
-		/*
-		 * These values have been optically calibrated for the
-		 * Samus LEDs to best match the official colors, described at
-		 * https://sites.google.com/a/google.com/brandsite/the-colours
-		 * See crosbug.com/p/33017 before making any changes.
-		 */
-		{0x34, 0x70, 0xb4},		/* 0: Google blue */
-		{0xbc, 0x50, 0x2c},		/* 1: Google red */
-		{0xd0, 0xe0, 0x00},		/* 2: Google yellow */
-		{0x50, 0xa0, 0x40},		/* 3: Google green */
-		/* These are primary colors */
-		{0x00, 0x00, 0xff},		/* 4: full blue */
-		{0xff, 0x00, 0x00},		/* 5: full red */
-		{0xff, 0xff, 0x00},		/* 6: full yellow */
-		{0x00, 0xff, 0x00},		/* 7: full green */
-	},
-};
-
-#define LB_SYSJUMP_TAG 0x4c42			/* "LB" */
-static void lightbar_preserve_state(void)
-{
-	system_add_jump_tag(LB_SYSJUMP_TAG, 0, sizeof(st), &st);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, lightbar_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void lightbar_restore_state(void)
-{
-	const uint8_t *old_state = 0;
-	int size;
-
-	old_state = system_get_jump_tag(LB_SYSJUMP_TAG, 0, &size);
-	if (old_state && size == sizeof(st)) {
-		memcpy(&st, old_state, size);
-		CPRINTS("LB state restored: %d %d - %d %d/%d",
-			st.cur_seq, st.prev_seq,
-			st.battery_is_charging,
-			st.battery_percent,
-			st.battery_level);
-	} else {
-		st.cur_seq = st.prev_seq = LIGHTBAR_S5;
-		st.battery_percent = 100;
-		st.battery_level = LB_BATTERY_LEVELS - 1;
-		st.w0 = 0;
-		st.ramp = 0;
-		memcpy(&st.p, &default_params, sizeof(st.p));
-		CPRINTS("LB state initialized");
-	}
-}
-
-/******************************************************************************/
-/* The patterns are generally dependent on the current battery level and AC
- * state. These functions obtain that information, generally by querying the
- * power manager task. In demo mode, the keyboard task forces changes to the
- * state by calling the demo_* functions directly. */
-/******************************************************************************/
-
-#ifdef CONFIG_PWM_KBLIGHT
-static int last_backlight_level;
-#endif
-#ifdef CONFIG_ALS_LIGHTBAR_DIMMING
-test_export_static int google_color_id;
-#endif
-
-static int demo_mode = DEMO_MODE_DEFAULT;
-
-static int quantize_battery_level(int pct)
-{
-	int i, bl = 0;
-	for (i = 0; i < LB_BATTERY_LEVELS - 1; i++)
-		if (pct >= st.p.battery_threshold[i])
-			bl++;
-	return bl;
-}
-
-#ifdef CONFIG_ALS_LIGHTBAR_DIMMING
-test_export_static int lux_level_to_google_color(const int lux)
-{
-	int i;
-
-	if (!lid_is_open()) {
-		/* The lid shades the light sensor, use full brightness. */
-		if (google_color_id != 0) {
-			google_color_id = 0;
-			return 1;
-		} else {
-			return 0;
-		}
-	}
-
-	/* See if we need to decrease brightness */
-	for (i = google_color_id; i < lb_brightness_levels_count ; i++)
-		if (lux >= lb_brightness_levels[i].lux_down)
-			break;
-	if (i > google_color_id) {
-		google_color_id = i;
-		return 1;
-	}
-	/* See if we need to increase brightness */
-	for (i = google_color_id; i > 0;  i--)
-		if (lux < lb_brightness_levels[i - 1].lux_up)
-			break;
-	if (i < google_color_id) {
-		google_color_id = i;
-		return 1;
-	}
-	return 0;
-}
-#endif
-
-/*
- * Update the known state.
- * Return 1 if something changes.
- */
-static int get_battery_level(void)
-{
-	int pct = 0;
-	int bl, change = 0;
-
-	if (demo_mode)
-		return 0;
-
-#ifdef HAS_TASK_CHARGER
-	st.battery_percent = pct = charge_get_percent();
-	st.battery_is_charging = (PWR_STATE_DISCHARGE != charge_get_state());
-	st.battery_is_power_on_prevented = charge_prevent_power_on(0);
-#endif
-
-	/* Find the new battery level */
-	bl = quantize_battery_level(pct);
-
-	/* Use some hysteresis to avoid flickering */
-	if (bl < st.battery_level ||
-	    (bl > st.battery_level
-	     && pct >= (st.p.battery_threshold[st.battery_level] + 1))) {
-		st.battery_level = bl;
-		change = 1;
-	}
-
-#ifdef CONFIG_PWM_KBLIGHT
-	/*
-	 * With nothing else to go on, use the keyboard backlight level to *
-	 * set the brightness. In general, if the keyboard backlight
-	 * is OFF (which it is when ambient is bright), use max brightness for
-	 * lightbar. If keyboard backlight is ON, use keyboard backlight
-	 * brightness. That fails if the keyboard backlight is off because
-	 * someone's watching a movie in the dark, of course. Ideally we should
-	 * just let the AP control it directly.
-	 */
-	if (pwm_get_enabled(PWM_CH_KBLIGHT)) {
-		pct = pwm_get_duty(PWM_CH_KBLIGHT);
-		pct = (255 * pct) / 100;  /* 00 - FF */
-		if (pct > st.p.bright_bl_on_max[st.battery_is_charging])
-			pct = st.p.bright_bl_on_max[st.battery_is_charging];
-		else if (pct < st.p.bright_bl_on_min[st.battery_is_charging])
-			pct = st.p.bright_bl_on_min[st.battery_is_charging];
-	} else
-		pct = st.p.bright_bl_off_fixed[st.battery_is_charging];
-
-	if (pct != last_backlight_level) {
-		last_backlight_level = pct;
-		lb_set_brightness(pct);
-		change = 1;
-	}
-#endif
-#ifdef CONFIG_ALS_LIGHTBAR_DIMMING
-	/* Read last value (in lux) collected by the motion sensor. */
-	/* Convert lux into brightness percentage */
-	if (lux_level_to_google_color(MOTION_SENSE_LUX)) {
-		memcpy(st.p.color, lb_brightness_levels[google_color_id].color,
-		       sizeof(lb_brightness_levels[google_color_id].color));
-		change = 1;
-	}
-#endif
-	return change;
-}
-
-/* Forcing functions for demo mode, called by the keyboard task. */
-
-/* Up/Down keys */
-#define DEMO_CHARGE_STEP 1
-void demo_battery_level(int inc)
-{
-	if (!demo_mode)
-		return;
-
-	st.battery_percent += DEMO_CHARGE_STEP * inc;
-
-	if (st.battery_percent > 100)
-		st.battery_percent = 100;
-	else if (st.battery_percent < 0)
-		st.battery_percent = 0;
-
-	st.battery_level = quantize_battery_level(st.battery_percent);
-
-	CPRINTS("LB demo: battery_percent = %d%%, battery_level=%d",
-		st.battery_percent, st.battery_level);
-}
-
-/* Left/Right keys */
-
-void demo_is_charging(int ischarge)
-{
-	if (!demo_mode)
-		return;
-
-	st.battery_is_charging = ischarge;
-	CPRINTS("LB demo: battery_is_charging=%d",
-		st.battery_is_charging);
-}
-
-/* Bright/Dim keys */
-void demo_brightness(int inc)
-{
-	int b;
-
-	if (!demo_mode)
-		return;
-
-	b = lb_get_brightness() + (inc * 16);
-	if (b > 0xff)
-		b = 0xff;
-	else if (b < 0)
-		b = 0;
-	lb_set_brightness(b);
-}
-
-/* T key */
-void demo_tap(void)
-{
-	if (!demo_mode)
-		return;
-	lightbar_sequence(LIGHTBAR_TAP);
-}
-
-/******************************************************************************/
-/* Helper functions and data. */
-/******************************************************************************/
-
-#define F(x) (x * FP_SCALE)
-static const uint16_t _ramp_table[] = {
-	F(0.000000), F(0.002408), F(0.009607), F(0.021530), F(0.038060),
-	F(0.059039), F(0.084265), F(0.113495), F(0.146447), F(0.182803),
-	F(0.222215), F(0.264302), F(0.308658), F(0.354858), F(0.402455),
-	F(0.450991), F(0.500000), F(0.549009), F(0.597545), F(0.645142),
-	F(0.691342), F(0.735698), F(0.777785), F(0.817197), F(0.853553),
-	F(0.886505), F(0.915735), F(0.940961), F(0.961940), F(0.978470),
-	F(0.990393), F(0.997592), F(1.000000),
-};
-#undef F
-
-/* This function provides a smooth ramp up from 0.0 to 1.0 and back to 0.0,
- * for input from 0x00 to 0xff. */
-static inline int cycle_010(uint8_t i)
-{
-	uint8_t bucket, index;
-
-	if (i == 128)
-		return FP_SCALE;
-	else if (i > 128)
-		i = 256 - i;
-
-	bucket = i >> 2;
-	index = i & 0x3;
-
-	return _ramp_table[bucket] +
-		((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2);
-}
-
-/******************************************************************************/
-/* Here's where we keep messages waiting to be delivered to the lightbar task.
- * If more than one is sent before the task responds, we only want to deliver
- * the latest one. */
-static uint32_t pending_msg;
-/* And here's the task event that we use to trigger delivery. */
-#define PENDING_MSG TASK_EVENT_CUSTOM_BIT(0)
-
-/* Interruptible delay. */
-#define WAIT_OR_RET(A)                                                         \
-	do {                                                                   \
-		uint32_t msg = task_wait_event(A);                             \
-		uint32_t p_msg = pending_msg;                                  \
-		if (msg & PENDING_MSG && p_msg != st.cur_seq)                  \
-			return p_msg;                                          \
-	} while (0)
-
-/******************************************************************************/
-/* Here are the preprogrammed sequences. */
-/******************************************************************************/
-
-/* Pulse google colors once, off to on to off. */
-static uint32_t pulse_google_colors(void)
-{
-	int w, i, r, g, b;
-	int f;
-
-	for (w = 0; w < 128; w += 2) {
-		f = cycle_010(w);
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = st.p.color[i].r * f / FP_SCALE;
-			g = st.p.color[i].g * f / FP_SCALE;
-			b = st.p.color[i].b * f / FP_SCALE;
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(st.p.google_ramp_up);
-	}
-	for (w = 128; w <= 256; w++) {
-		f = cycle_010(w);
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = st.p.color[i].r * f / FP_SCALE;
-			g = st.p.color[i].g * f / FP_SCALE;
-			b = st.p.color[i].b * f / FP_SCALE;
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(st.p.google_ramp_down);
-	}
-
-	return 0;
-}
-
-/* CPU is waking from sleep. */
-static uint32_t sequence_S3S0(void)
-{
-	int w, r, g, b;
-	int f, fmin;
-	int ci;
-	uint32_t res;
-
-	lb_init(1);
-	lb_on();
-	get_battery_level();
-
-	res = pulse_google_colors();
-	if (res)
-		return res;
-
-#ifndef BLUE_PULSING
-	/* next sequence */
-	return LIGHTBAR_S0;
-#endif
-
-	/* Ramp up to starting brightness, using S0 colors */
-	ci = st.p.s0_idx[st.battery_is_charging][st.battery_level];
-	if (ci >= ARRAY_SIZE(st.p.color))
-		ci = 0;
-
-	fmin = st.p.osc_min[st.battery_is_charging] * FP_SCALE / 255;
-
-	for (w = 0; w <= 128; w++) {
-		f = cycle_010(w) * fmin / FP_SCALE;
-		r = st.p.color[ci].r * f / FP_SCALE;
-		g = st.p.color[ci].g * f / FP_SCALE;
-		b = st.p.color[ci].b * f / FP_SCALE;
-		lb_set_rgb(NUM_LEDS, r, g, b);
-		WAIT_OR_RET(st.p.s3s0_ramp_up);
-	}
-
-	/* Initial conditions */
-	st.w0 = -256;				/* start cycle_npn() quietly */
-	st.ramp = 0;
-
-	/* Ready for S0 */
-	return LIGHTBAR_S0;
-}
-
-#ifdef BLUE_PULSING
-
-/* This function provides a pulsing oscillation between -0.5 and +0.5. */
-static inline int cycle_npn(uint16_t i)
-{
-	if ((i / 256) % 4)
-		return -FP_SCALE / 2;
-	return cycle_010(i) - FP_SCALE / 2;
-}
-
-/* CPU is fully on */
-static uint32_t sequence_S0(void)
-{
-	int tick, last_tick;
-	timestamp_t start, now;
-	uint8_t r, g, b;
-	int i, ci;
-	uint8_t w_ofs;
-	uint16_t w;
-	int f, fmin, fmax, base_s0, osc_s0, f_ramp;
-
-	start = get_time();
-	tick = last_tick = 0;
-
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-	lb_on();
-
-	while (1) {
-		now = get_time();
-
-		/* Only check the battery state every few seconds. The battery
-		 * charging task doesn't update as quickly as we do, and isn't
-		 * always valid for a bit after jumping from RO->RW. */
-		tick = (now.le.lo - start.le.lo) / SECOND;
-		if (tick % 4 == 3 && tick != last_tick) {
-			get_battery_level();
-			last_tick = tick;
-		}
-
-		/* Calculate the colors */
-		ci = st.p.s0_idx[st.battery_is_charging][st.battery_level];
-		if (ci >= ARRAY_SIZE(st.p.color))
-			ci = 0;
-		w_ofs = st.p.w_ofs[st.battery_is_charging];
-		fmin = st.p.osc_min[st.battery_is_charging] * FP_SCALE / 255;
-		fmax = st.p.osc_max[st.battery_is_charging] * FP_SCALE / 255;
-		base_s0 = (fmax + fmin) / 2;
-		osc_s0 = fmax - fmin;
-		f_ramp = st.ramp * FP_SCALE / 255;
-
-		for (i = 0; i < NUM_LEDS; i++) {
-			w = st.w0 - i * w_ofs * f_ramp / FP_SCALE;
-			f = base_s0 + osc_s0 * cycle_npn(w) / FP_SCALE;
-			r = st.p.color[ci].r * f / FP_SCALE;
-			g = st.p.color[ci].g * f / FP_SCALE;
-			b = st.p.color[ci].b * f / FP_SCALE;
-			lb_set_rgb(i, r, g, b);
-		}
-
-		/* Increment the phase */
-		if (st.battery_is_charging)
-			st.w0--;
-		else
-			st.w0++;
-
-		/* Continue ramping in if needed */
-		if (st.ramp < 0xff)
-			st.ramp++;
-
-		i = st.p.s0a_tick_delay[st.battery_is_charging];
-		WAIT_OR_RET(i);
-	}
-	return 0;
-}
-
-#else  /* just simple google colors */
-
-static uint32_t sequence_S0(void)
-{
-	int w, i, r, g, b;
-	int f, change;
-
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-	lb_on();
-
-	/* Ramp up */
-	for (w = 0; w < 128; w += 2) {
-		f = cycle_010(w);
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = st.p.color[i].r * f / FP_SCALE;
-			g = st.p.color[i].g * f / FP_SCALE;
-			b = st.p.color[i].b * f / FP_SCALE;
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(st.p.google_ramp_up);
-	}
-
-	while (1) {
-		change = get_battery_level();
-
-		if (change) {
-			/* Not really low use google colors */
-			if (st.battery_level) {
-				for (i = 0; i < NUM_LEDS; i++) {
-					r = st.p.color[i].r;
-					g = st.p.color[i].g;
-					b = st.p.color[i].b;
-					lb_set_rgb(i, r, g, b);
-				}
-			} else {
-				r = st.p.color[PRIMARY_RED].r;
-				g = st.p.color[PRIMARY_RED].g;
-				b = st.p.color[PRIMARY_RED].b;
-				lb_set_rgb(4, r, g, b);
-			}
-		}
-
-		WAIT_OR_RET(1 * SECOND);
-	}
-	return 0;
-}
-
-#endif
-
-/* CPU is going to sleep. */
-static uint32_t sequence_S0S3(void)
-{
-	int w, i, r, g, b;
-	int f;
-	uint8_t drop[NUM_LEDS][3];
-	uint32_t res;
-
-	/* Grab current colors */
-	for (i = 0; i < NUM_LEDS; i++)
-		lb_get_rgb(i, &drop[i][0], &drop[i][1], &drop[i][2]);
-
-	/* Fade down to black */
-	for (w = 128; w <= 256; w++) {
-		f = cycle_010(w);
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = drop[i][0] * f / FP_SCALE;
-			g = drop[i][1] * f / FP_SCALE;
-			b = drop[i][2] * f / FP_SCALE;
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(st.p.s0s3_ramp_down);
-	}
-
-	/* pulse once and done */
-	res = pulse_google_colors();
-	if (res)
-		return res;
-
-	/* next sequence */
-	return LIGHTBAR_S3;
-}
-
-/* CPU is sleeping */
-static uint32_t sequence_S3(void)
-{
-	int r, g, b;
-	int w;
-	int f;
-	int ci;
-
-	lb_off();
-	lb_init(1);
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-	get_battery_level();
-	while (1) {
-		WAIT_OR_RET(st.p.s3_sleep_for);
-
-		/* only pulse if we've been given a valid color index */
-		ci = st.p.s3_idx[st.battery_is_charging][st.battery_level];
-		if (ci >= ARRAY_SIZE(st.p.color))
-			continue;
-
-		/* pulse once */
-		lb_on();
-
-		for (w = 0; w < 128; w += 2) {
-			f = cycle_010(w);
-			r = st.p.color[ci].r * f / FP_SCALE;
-			g = st.p.color[ci].g * f / FP_SCALE;
-			b = st.p.color[ci].b * f / FP_SCALE;
-			lb_set_rgb(NUM_LEDS, r, g, b);
-			WAIT_OR_RET(st.p.s3_ramp_up);
-		}
-		for (w = 128; w <= 256; w++) {
-			f = cycle_010(w);
-			r = st.p.color[ci].r * f / FP_SCALE;
-			g = st.p.color[ci].g * f / FP_SCALE;
-			b = st.p.color[ci].b * f / FP_SCALE;
-			lb_set_rgb(NUM_LEDS, r, g, b);
-			WAIT_OR_RET(st.p.s3_ramp_down);
-		}
-
-		lb_set_rgb(NUM_LEDS, 0, 0, 0);
-		lb_off();
-	}
-	return 0;
-}
-
-
-/* CPU is powering up. We generally boot fast enough that we don't have time
- * to do anything interesting in the S3 state, but go straight on to S0. */
-static uint32_t sequence_S5S3(void)
-{
-	/* The controllers need 100us after power is applied before they'll
-	 * respond. Don't return early, because we still want to initialize the
-	 * lightbar even if another message comes along while we're waiting. */
-	usleep(100);
-	lb_init(1);
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-	lb_on();
-	/* next sequence */
-	return LIGHTBAR_S3;
-}
-
-/* Sleep to off. The S3->S5 transition takes about 10msec, so just wait. */
-static uint32_t sequence_S3S5(void)
-{
-	lb_off();
-	/* next sequence */
-	return LIGHTBAR_S5;
-}
-
-/* Pulse S5 color to indicate that the battery is so critically low that it
- * must charge first before the system can power on. */
-static uint32_t pulse_s5_color(void)
-{
-	int r, g, b;
-	int f;
-	int w;
-	struct rgb_s *color = &st.p.color[st.p.s5_idx];
-
-	for (w = 0; w < 128; w += 2) {
-		f = cycle_010(w);
-		r = color->r * f / FP_SCALE;
-		g = color->g * f / FP_SCALE;
-		b = color->b * f / FP_SCALE;
-		lb_set_rgb(NUM_LEDS, r, g, b);
-		WAIT_OR_RET(st.p.s5_ramp_up);
-	}
-	for (w = 128; w <= 256; w++) {
-		f = cycle_010(w);
-		r = color->r * f / FP_SCALE;
-		g = color->g * f / FP_SCALE;
-		b = color->b * f / FP_SCALE;
-		lb_set_rgb(NUM_LEDS, r, g, b);
-		WAIT_OR_RET(st.p.s5_ramp_down);
-	}
-
-	return 0;
-}
-
-/* CPU is off. Pulse the lightbar if a charger is attached and the battery is
- * so low that the system cannot power on. Otherwise, the lightbar loses power
- * when the CPU is in S5, so there's nothing to do. We'll just wait here until
- * the state changes. */
-static uint32_t sequence_S5(void)
-{
-	int initialized = 0;
-	uint32_t res = 0;
-
-	get_battery_level();
-	while (1) {
-		if (!st.battery_is_power_on_prevented ||
-		    !st.battery_is_charging)
-			break;
-
-		if (!initialized) {
-#ifdef CONFIG_LIGHTBAR_POWER_RAILS
-			/* Request that lightbar power rails be turned on. */
-			if (lb_power(1)) {
-				lb_set_rgb(NUM_LEDS, 0, 0, 0);
-			}
-#endif
-			lb_on();
-			initialized = 1;
-		}
-
-		res = pulse_s5_color();
-		if (res)
-			break;
-	}
-
-#ifdef CONFIG_LIGHTBAR_POWER_RAILS
-	if (initialized)
-		/* Suggest that the lightbar power rails can be shut down. */
-		lb_power(0);
-#endif
-	lb_off();
-	if (!res)
-		WAIT_OR_RET(-1);
-	return res;
-}
-
-/* The AP is going to poke at the lightbar directly, so we don't want the EC
- * messing with it. We'll just sit here and ignore all other messages until
- * we're told to continue (or until we think the AP is shutting down).
- */
-static uint32_t sequence_STOP(void)
-{
-	uint32_t msg;
-
-	do {
-		msg = task_wait_event(-1);
-		CPRINTS("LB %s() got pending_msg %d", __func__, pending_msg);
-	} while (msg != PENDING_MSG || (
-			 pending_msg != LIGHTBAR_RUN &&
-			 pending_msg != LIGHTBAR_S0S3 &&
-			 pending_msg != LIGHTBAR_S3 &&
-			 pending_msg != LIGHTBAR_S3S5 &&
-			 pending_msg != LIGHTBAR_S5));
-	return 0;
-}
-
-/* Telling us to run when we're already running should do nothing. */
-static uint32_t sequence_RUN(void)
-{
-	return 0;
-}
-
-/* We shouldn't come here, but if we do it shouldn't hurt anything. This
- * sequence is to indicate an internal error in the lightbar logic, not an
- * error with the Chromebook itself.
- */
-static uint32_t sequence_ERROR(void)
-{
-	lb_init(1);
-	lb_on();
-
-	lb_set_rgb(0, 255, 255, 255);
-	lb_set_rgb(1, 255, 0, 255);
-	lb_set_rgb(2, 0, 255, 255);
-	lb_set_rgb(3, 255, 255, 255);
-
-	WAIT_OR_RET(10 * SECOND);
-	return 0;
-}
-
-static const struct {
-	uint8_t led;
-	uint8_t r, g, b;
-	unsigned int delay;
-} konami[] = {
-
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0xff, 0xff, 0},
-	{2, 0x00, 0xff, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 150000},
-
-	{1, 0xff, 0x00, 0xff, 0},
-	{3, 0xff, 0x00, 0xff, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 250000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-};
-
-static uint32_t sequence_KONAMI_inner(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(konami); i++) {
-		lb_set_rgb(konami[i].led,
-			   konami[i].r, konami[i].g, konami[i].b);
-		if (konami[i].delay)
-			WAIT_OR_RET(konami[i].delay);
-	}
-
-	return 0;
-}
-
-static uint32_t sequence_KONAMI(void)
-{
-	int tmp;
-	uint32_t r;
-
-	/* First clear all segments */
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-
-	/* Force brightness to max, then restore it */
-	tmp = lb_get_brightness();
-	lb_set_brightness(255);
-	r = sequence_KONAMI_inner();
-	lb_set_brightness(tmp);
-	return r;
-}
-
-#ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
-/* Returns 0.0 to 1.0 for val in [min, min + ofs] */
-static int range(int val, int min, int ofs)
-{
-	if (val <= min)
-		return 0;
-	if (val >= min+ofs)
-		return FP_SCALE;
-	return (val - min) * FP_SCALE / ofs;
-}
-#endif
-
-/* Handy constant */
-#define CUT (100 / NUM_LEDS)
-
-static uint32_t sequence_TAP_inner(int dir)
-{
-	enum { RED, YELLOW, GREEN } base_color;
-	timestamp_t start, now;
-	uint32_t elapsed_time = 0;
-	int i, l, ci, max_led;
-	int f_osc, f_mult;
-	int gi, gr, gate[NUM_LEDS] = {0, 0, 0, 0};
-	uint8_t w = 0;
-#ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
-	int f_min, f_delta, f_power;
-
-	f_min = st.p.tap_seg_min_on * FP_SCALE / 100;
-	f_delta = (st.p.tap_seg_max_on - st.p.tap_seg_min_on) * FP_SCALE / 100;
-#endif
-	f_osc = st.p.tap_seg_osc * FP_SCALE / 100;
-
-	get_battery_level();
-
-	if (st.battery_level == 0)
-		base_color = RED;
-	else if (st.battery_percent > st.p.tap_pct_green)
-		base_color = GREEN;
-	else
-		base_color = YELLOW;
-
-	ci = st.p.tap_idx[base_color];
-	max_led = st.battery_percent / CUT;
-
-	start = get_time();
-	while (1) {
-		/* Enable the segments gradually */
-		gi = elapsed_time / st.p.tap_gate_delay;
-		gr = elapsed_time % st.p.tap_gate_delay;
-		if (gi < NUM_LEDS)
-			gate[gi] = FP_SCALE * gr / st.p.tap_gate_delay;
-		if (gi && gi <= NUM_LEDS)
-			gate[gi - 1] = FP_SCALE;
-
-		for (i = 0; i < NUM_LEDS; i++) {
-
-#ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
-			if (max_led > i) {
-				f_mult = FP_SCALE;
-			} else if (max_led < i) {
-				f_mult = 0;
-			} else {
-				switch (base_color) {
-				case RED:
-					f_power = range(st.battery_percent, 0,
-						st.p.battery_threshold[0] - 1);
-					break;
-				case YELLOW:
-					f_power = range(st.battery_percent,
-							i * CUT, CUT - 1);
-					break;
-				case GREEN:
-					/* green is always full on */
-					f_power = FP_SCALE;
-				}
-				f_mult = f_min + f_power * f_delta / FP_SCALE;
-			}
-#else
-			if (max_led >= i)
-				f_mult = FP_SCALE;
-			else if (max_led < i)
-				f_mult = 0;
-#endif
-
-			f_mult = f_mult * gate[i] / FP_SCALE;
-
-			/* Pulse when charging and not yet full */
-			if (st.battery_is_charging &&
-			    st.battery_percent <= st.p.tap_pct_green) {
-				int scale = (FP_SCALE -
-					     f_osc * cycle_010(w++) / FP_SCALE);
-				f_mult = f_mult * scale / FP_SCALE;
-			}
-
-			l = dir ? i : NUM_LEDS - 1 - i;
-			lb_set_rgb(l, f_mult * st.p.color[ci].r / FP_SCALE,
-				   f_mult * st.p.color[ci].g / FP_SCALE,
-				   f_mult * st.p.color[ci].b / FP_SCALE);
-		}
-
-		WAIT_OR_RET(st.p.tap_tick_delay);
-
-		/* Return after some time has elapsed */
-		now = get_time();
-		elapsed_time = now.le.lo - start.le.lo;
-		if (elapsed_time > st.p.tap_display_time)
-			break;
-	}
-	return 0;
-}
-
-/* Override the tap direction for testing. -1 means ask the PD MCU. */
-static int force_dir = -1;
-
-/* Return 0 (left or none) or 1 (right) */
-static int get_tap_direction(void)
-{
-	static int last_dir;
-	int dir = 0;
-
-	if (force_dir >= 0)
-		dir = force_dir;
-#ifdef HAS_TASK_PDCMD
-	else
-		dir = pd_get_active_charge_port();
-#endif
-	if (dir < 0)
-		dir = last_dir;
-	else if (dir != 1)
-		dir = 0;
-
-	CPRINTS("LB tap direction %d", dir);
-	last_dir = dir;
-	return dir;
-}
-
-static uint32_t sequence_TAP(void)
-{
-	int i;
-	uint32_t r;
-	uint8_t br, save[NUM_LEDS][3];
-	int dir;
-
-	/*
-	 * There's a lot of unavoidable glitchiness on the AC_PRESENT interrupt
-	 * each time the EC boots, resulting in fights between the TAP sequence
-	 * and the S5S3->S3->S3S0->S0 sequences. This delay prevents the lights
-	 * from flickering without reducing the responsiveness to manual taps.
-	 */
-	WAIT_OR_RET(100 * MSEC);
-
-	/* Which direction should the power meter go? */
-	dir = get_tap_direction();
-
-#ifdef CONFIG_LIGHTBAR_POWER_RAILS
-	/* Request that the lightbar power rails be turned on. */
-	if (lb_power(1)) {
-		lb_set_rgb(NUM_LEDS, 0, 0, 0);
-	}
-#endif
-	/* First clear all segments */
-	lb_set_rgb(NUM_LEDS, 0, 0, 0);
-
-	lb_on();
-
-	for (i = 0; i < NUM_LEDS; i++)
-		lb_get_rgb(i, &save[i][0], &save[i][1], &save[i][2]);
-	br = lb_get_brightness();
-	lb_set_brightness(255);
-
-	r = sequence_TAP_inner(dir);
-
-	lb_set_brightness(br);
-	for (i = 0; i < NUM_LEDS; i++)
-		lb_set_rgb(i, save[i][0], save[i][1], save[i][2]);
-
-#ifdef CONFIG_LIGHTBAR_POWER_RAILS
-	/* Suggest that the lightbar power rails can be shut down again. */
-	lb_power(0);
-#endif
-	return r;
-}
-
-/****************************************************************************/
-/* Lightbar bytecode interpreter: Lightbyte. */
-/****************************************************************************/
-
-/* When a program halts, return this. */
-#define PROGRAM_FINISHED 2
-
-static struct lightbar_program cur_prog;
-static struct lightbar_program next_prog;
-static uint8_t pc;
-
-static uint8_t led_desc[NUM_LEDS][LB_CONT_MAX][3];
-static uint32_t lb_wait_delay;
-static uint32_t lb_ramp_delay;
-/* Get one byte of data pointed to by the pc and advance
- * the pc forward.
- */
-static inline uint32_t decode_8(uint8_t *dest)
-{
-	if (pc >= cur_prog.size) {
-		CPRINTS("pc 0x%02x out of bounds", pc);
-		return EC_RES_INVALID_PARAM;
-	}
-	*dest = cur_prog.data[pc++];
-	return EC_SUCCESS;
-}
-
-/* Get four bytes of data pointed to by the pc and advance
- * the pc forward that amount.
- */
-static inline uint32_t decode_32(uint32_t *dest)
-{
-	if (pc >= cur_prog.size - 3) {
-		CPRINTS("pc 0x%02x near or out of bounds", pc);
-		return EC_RES_INVALID_PARAM;
-	}
-	*dest  = cur_prog.data[pc++] << 24;
-	*dest |= cur_prog.data[pc++] << 16;
-	*dest |= cur_prog.data[pc++] <<  8;
-	*dest |= cur_prog.data[pc++];
-	return EC_SUCCESS;
-}
-
-/* ON - turn on lightbar */
-static uint32_t lightbyte_ON(void)
-{
-	lb_on();
-	return EC_SUCCESS;
-}
-
-/* OFF - turn off lightbar */
-static uint32_t lightbyte_OFF(void)
-{
-	lb_off();
-	return EC_SUCCESS;
-}
-
-/* JUMP xx - jump to immediate location
- * Changes the pc to the one-byte immediate argument.
- */
-static uint32_t lightbyte_JUMP(void)
-{
-	return decode_8(&pc);
-}
-
-/* JUMP_BATTERY aa bb - switch on battery level
- * If the battery is low, changes pc to aa.
- * If the battery is high, changes pc to bb.
- * Otherwise, continues execution as normal.
- */
-static uint32_t lightbyte_JUMP_BATTERY(void)
-{
-	uint8_t low_pc, high_pc;
-	if (decode_8(&low_pc) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-	if (decode_8(&high_pc) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	get_battery_level();
-	if (st.battery_level == 0)
-		pc = low_pc;
-	else if (st.battery_level == 3)
-		pc = high_pc;
-
-	return EC_SUCCESS;
-}
-
-/* JUMP_IF_CHARGING xx - conditional jump to location
- * Changes the pc to xx if the device is charging.
- */
-static uint32_t lightbyte_JUMP_IF_CHARGING(void)
-{
-	uint8_t charge_pc;
-	if (decode_8(&charge_pc) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	if (st.battery_is_charging)
-		pc = charge_pc;
-
-	return EC_SUCCESS;
-}
-
-/* SET_WAIT_DELAY xx xx xx xx - set up to yield processor
- * Sets the wait delay to the given four-byte immediate, in
- * microseconds. Future WAIT instructions will wait for this
- * much time.
- */
-static uint32_t lightbyte_SET_WAIT_DELAY(void)
-{
-	return decode_32(&lb_wait_delay);
-}
-
-/* SET_RAMP_DELAY xx xx xx xx - change ramp speed
- * This sets the length of time between ramp/cycle steps to
- * the four-byte immediate argument, which represents a duration
- * in milliseconds.
- */
-static uint32_t lightbyte_SET_RAMP_DELAY(void)
-{
-	return decode_32(&lb_ramp_delay);
-}
-
-/* WAIT - yield processor for some time
- * Yields the processor for some amount of time set by the most
- * recent SET_WAIT_DELAY instruction.
- */
-static uint32_t lightbyte_WAIT(void)
-{
-	if (lb_wait_delay != 0)
-		WAIT_OR_RET(lb_wait_delay);
-
-	return EC_SUCCESS;
-}
-
-/* SET_BRIGHTNESS xx
- * Sets the current brightness to the given one-byte
- * immediate argument.
- */
-static uint32_t lightbyte_SET_BRIGHTNESS(void)
-{
-	uint8_t val;
-	if (decode_8(&val) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	lb_set_brightness(val);
-	return EC_SUCCESS;
-}
-
-/* SET_COLOR_SINGLE cc xx
- * SET_COLOR_RGB cc rr gg bb
- * Stores a color value in the led_desc structure.
- * cc is a bit-packed location to perform the action on.
- *
- * The high four bits are a bitset for which LEDs to operate on.
- * LED 0 is the lowest of the four bits.
- *
- * The next two bits are the control bits. This should be a value
- * in lb_control that is not LB_CONT_MAX, and the corresponding
- * color will be the one the action is performed on.
- *
- * The last two bits are the color bits if this instruction is
- * SET_COLOR_SINGLE. They correspond to a LB_COL value for the
- * channel to set the color for using the next immediate byte.
- * In SET_COLOR_RGB, these bits are don't-cares, as there should
- * always be three bytes that follow, which correspond to a
- * complete RGB specification.
- */
-static uint32_t lightbyte_SET_COLOR_SINGLE(void)
-{
-
-	uint8_t packed_loc, led, control, color, value;
-	int i;
-	if (decode_8(&packed_loc) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-	if (decode_8(&value) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	led = packed_loc >> 4;
-	control = (packed_loc >> 2) & 0x3;
-	color = packed_loc & 0x3;
-
-	if (control >= LB_CONT_MAX)
-		return EC_RES_INVALID_PARAM;
-
-	for (i = 0; i < NUM_LEDS; i++)
-		if (led & BIT(i))
-			led_desc[i][control][color] = value;
-
-	return EC_SUCCESS;
-}
-
-static uint32_t lightbyte_SET_COLOR_RGB(void)
-{
-	uint8_t packed_loc, r, g, b, led, control;
-	int i;
-
-	/* gross */
-	if (decode_8(&packed_loc) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-	if (decode_8(&r) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-	if (decode_8(&g) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-	if (decode_8(&b) != EC_SUCCESS)
-		return EC_RES_INVALID_PARAM;
-
-	led = packed_loc >> 4;
-	control = (packed_loc >> 2) & 0x3;
-
-	if (control >= LB_CONT_MAX)
-		return EC_RES_INVALID_PARAM;
-
-	for (i = 0; i < NUM_LEDS; i++)
-		if (led & BIT(i)) {
-			led_desc[i][control][LB_COL_RED] = r;
-			led_desc[i][control][LB_COL_GREEN] = g;
-			led_desc[i][control][LB_COL_BLUE] = b;
-		}
-
-	return EC_SUCCESS;
-}
-
-/* GET_COLORS - take current colors and push them to the state
- * Gets the current state of the LEDs and puts them in COLOR0.
- * Good for the beginning of a program if you need to fade in.
- */
-static uint32_t lightbyte_GET_COLORS(void)
-{
-	int i;
-	for (i = 0; i < NUM_LEDS; i++)
-		lb_get_rgb(i, &led_desc[i][LB_CONT_COLOR0][LB_COL_RED],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]);
-
-	return EC_SUCCESS;
-}
-
-/* SWAP_COLORS - swaps beginning and end colors in state
- * Exchanges COLOR0 and COLOR1 on all LEDs.
- */
-static uint32_t lightbyte_SWAP_COLORS(void)
-{
-	int i, j, tmp;
-	for (i = 0; i < NUM_LEDS; i++)
-		for (j = 0; j < 3; j++) {
-			tmp = led_desc[i][LB_CONT_COLOR0][j];
-			led_desc[i][LB_CONT_COLOR0][j] =
-				led_desc[i][LB_CONT_COLOR1][j];
-			led_desc[i][LB_CONT_COLOR1][j] = tmp;
-		}
-
-	return EC_SUCCESS;
-}
-
-static inline int get_interp_value(int led, int color, int interp)
-{
-	int base = led_desc[led][LB_CONT_COLOR0][color];
-	int delta = led_desc[led][LB_CONT_COLOR1][color] - base;
-	return base + (delta * interp / FP_SCALE);
-}
-
-static void set_all_leds(int color)
-{
-	int i, r, g, b;
-	for (i = 0; i < NUM_LEDS; i++) {
-		r = led_desc[i][color][LB_COL_RED];
-		g = led_desc[i][color][LB_COL_GREEN];
-		b = led_desc[i][color][LB_COL_BLUE];
-		lb_set_rgb(i, r, g, b);
-	}
-}
-
-static uint32_t ramp_all_leds(int stop_at)
-{
-	int w, i, r, g, b, f;
-	for (w = 0; w < stop_at; w++) {
-		f = cycle_010(w);
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = get_interp_value(i, LB_COL_RED, f);
-			g = get_interp_value(i, LB_COL_GREEN, f);
-			b = get_interp_value(i, LB_COL_BLUE, f);
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(lb_ramp_delay);
-	}
-	return EC_SUCCESS;
-}
-
-/* RAMP_ONCE - simple gradient or color set
- * If the ramp delay is set to zero, then this sets the color of
- * all LEDs to their respective COLOR1.
- * If the ramp delay is nonzero, then this sets their color to
- * their respective COLOR0, and takes them via interpolation to
- * COLOR1, with the delay time passing in between each step.
- */
-static uint32_t lightbyte_RAMP_ONCE(void)
-{
-	/* special case for instantaneous set */
-	if (lb_ramp_delay == 0) {
-		set_all_leds(LB_CONT_COLOR1);
-		return EC_SUCCESS;
-	}
-
-	return ramp_all_leds(128);
-}
-
-/* CYCLE_ONCE - simple cycle or color set
- * If the ramp delay is zero, then this sets the color of all LEDs
- * to their respective COLOR0.
- * If the ramp delay is nonzero, this sets the color of all LEDs
- * to COLOR0, then performs a ramp (as in RAMP_ONCE) to COLOR1,
- * and finally back to COLOR0.
- */
-static uint32_t lightbyte_CYCLE_ONCE(void)
-{
-	/* special case for instantaneous set */
-	if (lb_ramp_delay == 0) {
-		set_all_leds(LB_CONT_COLOR0);
-		return EC_SUCCESS;
-	}
-
-	return ramp_all_leds(256);
-}
-
-/* CYCLE - repeating cycle
- * Indefinitely ramps from COLOR0 to COLOR1, taking into
- * account the PHASE of each component of each color when
- * interpolating. (Different LEDs and different color channels
- * on a single LED can start at different places in the cycle,
- * though they will advance at the same rate.)
- *
- * If the ramp delay is zero, this instruction will error out.
- */
-static uint32_t lightbyte_CYCLE(void)
-{
-	int w, i, r, g, b;
-
-	/* what does it mean to cycle indefinitely with 0 delay? */
-	if (lb_ramp_delay == 0)
-		return EC_RES_INVALID_PARAM;
-
-	for (w = 0;; w++) {
-		for (i = 0; i < NUM_LEDS; i++) {
-			r = get_interp_value(i, LB_COL_RED,
-				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_RED]));
-			g = get_interp_value(i, LB_COL_GREEN,
-				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_GREEN]));
-			b = get_interp_value(i, LB_COL_BLUE,
-				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_BLUE]));
-			lb_set_rgb(i, r, g, b);
-		}
-		WAIT_OR_RET(lb_ramp_delay);
-	}
-	return EC_SUCCESS;
-}
-
-/* HALT - return with success
- * Show's over. Go back to what you were doing before.
- */
-static uint32_t lightbyte_HALT(void)
-{
-	return PROGRAM_FINISHED;
-}
-
-#undef GET_INTERP_VALUE
-
-#define OP(NAME, BYTES, MNEMONIC) NAME,
-#include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) lightbyte_ ## NAME,
-#include "lightbar_opcode_list.h"
-static uint32_t (*lightbyte_dispatch[])(void) = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
-#include "lightbar_opcode_list.h"
-static const char * const lightbyte_names[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-static uint32_t sequence_PROGRAM(void)
-{
-	uint8_t saved_brightness;
-	uint8_t next_inst;
-	uint32_t rc;
-	uint8_t old_pc;
-
-	/* load next program */
-	memcpy(&cur_prog, &next_prog, sizeof(struct lightbar_program));
-
-	/* reset program state */
-	saved_brightness = lb_get_brightness();
-	pc = 0;
-	memset(led_desc, 0, sizeof(led_desc));
-	lb_wait_delay = 0;
-	lb_ramp_delay = 0;
-
-	lb_on();
-	lb_set_brightness(255);
-
-	/* decode-execute loop */
-	for (;;) {
-		old_pc = pc;
-		if (decode_8(&next_inst) != EC_SUCCESS)
-			return EC_RES_INVALID_PARAM;
-
-		if (next_inst >= MAX_OPCODE) {
-			CPRINTS("LB PROGRAM pc: 0x%02x, "
-				"found invalid opcode 0x%02x",
-				old_pc, next_inst);
-			lb_set_brightness(saved_brightness);
-			return EC_RES_INVALID_PARAM;
-		} else {
-			CPRINTS("LB PROGRAM pc: 0x%02x, opcode 0x%02x -> %s",
-				 old_pc, next_inst, lightbyte_names[next_inst]);
-			rc = lightbyte_dispatch[next_inst]();
-			if (rc) {
-				lb_set_brightness(saved_brightness);
-				return rc;
-			}
-		}
-
-		/* yield processor in case we are stuck in a tight loop */
-		WAIT_OR_RET(100);
-	}
-}
-
-/****************************************************************************/
-/* The main lightbar task. It just cycles between various pretty patterns. */
-/****************************************************************************/
-
-/* Distinguish "normal" sequences from one-shot sequences */
-static inline int is_normal_sequence(enum lightbar_sequence seq)
-{
-	return (seq >= LIGHTBAR_S5 && seq <= LIGHTBAR_S3S5);
-}
-
-/* Link each sequence with a command to invoke it. */
-struct lightbar_cmd_t {
-	const char * const string;
-	uint32_t (*sequence)(void);
-};
-
-#define LBMSG(state) { #state, sequence_##state }
-#include "lightbar_msg_list.h"
-static struct lightbar_cmd_t lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
-#undef LBMSG
-
-void lightbar_task(void)
-{
-	uint32_t next_seq;
-
-	CPRINTS("LB task starting");
-
-	lightbar_restore_state();
-
-	while (1) {
-		CPRINTS("LB running cur_seq %d %s. prev_seq %d %s",
-			st.cur_seq, lightbar_cmds[st.cur_seq].string,
-			st.prev_seq, lightbar_cmds[st.prev_seq].string);
-		next_seq = lightbar_cmds[st.cur_seq].sequence();
-		if (next_seq) {
-			CPRINTS("LB cur_seq %d %s returned pending msg %d %s",
-				st.cur_seq, lightbar_cmds[st.cur_seq].string,
-				next_seq, lightbar_cmds[next_seq].string);
-			if (st.cur_seq != next_seq) {
-				if (is_normal_sequence(st.cur_seq))
-					st.prev_seq = st.cur_seq;
-				st.cur_seq = next_seq;
-			}
-		} else {
-			CPRINTS("LB cur_seq %d %s returned value 0",
-				st.cur_seq, lightbar_cmds[st.cur_seq].string);
-			switch (st.cur_seq) {
-			case LIGHTBAR_S5S3:
-				st.cur_seq = LIGHTBAR_S3;
-				break;
-			case LIGHTBAR_S3S0:
-				st.cur_seq = LIGHTBAR_S0;
-				break;
-			case LIGHTBAR_S0S3:
-				st.cur_seq = LIGHTBAR_S3;
-				break;
-			case LIGHTBAR_S3S5:
-				st.cur_seq = LIGHTBAR_S5;
-				break;
-			case LIGHTBAR_STOP:
-			case LIGHTBAR_RUN:
-			case LIGHTBAR_ERROR:
-			case LIGHTBAR_KONAMI:
-			case LIGHTBAR_TAP:
-			case LIGHTBAR_PROGRAM:
-				st.cur_seq = st.prev_seq;
-			default:
-				break;
-			}
-		}
-	}
-}
-
-/* Function to request a preset sequence from the lightbar task. */
-void lightbar_sequence_f(enum lightbar_sequence num, const char *f)
-{
-	if (num > 0 && num < LIGHTBAR_NUM_SEQUENCES) {
-		CPRINTS("LB %s() requests %d %s", f, num,
-			lightbar_cmds[num].string);
-		pending_msg = num;
-		task_set_event(TASK_ID_LIGHTBAR, PENDING_MSG);
-	} else
-		CPRINTS("LB %s() requests %d - ignored", f, num);
-}
-
-/****************************************************************************/
-/* Get notifications from other parts of the system */
-
-static uint8_t manual_suspend_control;
-
-static void lightbar_startup(void)
-{
-	manual_suspend_control = 0;
-	lightbar_sequence(LIGHTBAR_S5S3);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, lightbar_startup, HOOK_PRIO_DEFAULT);
-
-static void lightbar_resume(void)
-{
-	if (!manual_suspend_control)
-		lightbar_sequence(LIGHTBAR_S3S0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, lightbar_resume, HOOK_PRIO_DEFAULT);
-
-static void lightbar_suspend(void)
-{
-	if (!manual_suspend_control)
-		lightbar_sequence(LIGHTBAR_S0S3);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, lightbar_suspend, HOOK_PRIO_DEFAULT);
-
-static void lightbar_shutdown(void)
-{
-	lightbar_sequence(LIGHTBAR_S3S5);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, lightbar_shutdown, HOOK_PRIO_DEFAULT);
-
-/****************************************************************************/
-/* Host commands via LPC bus */
-/****************************************************************************/
-
-static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_lightbar *in = args->params;
-	struct ec_response_lightbar *out = args->response;
-	int rv;
-
-	switch (in->cmd) {
-	case LIGHTBAR_CMD_DUMP:
-		lb_hc_cmd_dump(out);
-		args->response_size = sizeof(out->dump);
-		break;
-	case LIGHTBAR_CMD_OFF:
-		lb_off();
-		break;
-	case LIGHTBAR_CMD_ON:
-		lb_on();
-		break;
-	case LIGHTBAR_CMD_INIT:
-		lb_init(1);
-		break;
-	case LIGHTBAR_CMD_SET_BRIGHTNESS:
-		lb_set_brightness(in->set_brightness.num);
-		break;
-	case LIGHTBAR_CMD_GET_BRIGHTNESS:
-		out->get_brightness.num = lb_get_brightness();
-		args->response_size = sizeof(out->get_brightness);
-		break;
-	case LIGHTBAR_CMD_SEQ:
-		lightbar_sequence(in->seq.num);
-		break;
-	case LIGHTBAR_CMD_REG:
-		lb_hc_cmd_reg(in);
-		break;
-	case LIGHTBAR_CMD_SET_RGB:
-		lb_set_rgb(in->set_rgb.led,
-			   in->set_rgb.red,
-			   in->set_rgb.green,
-			   in->set_rgb.blue);
-		break;
-	case LIGHTBAR_CMD_GET_RGB:
-		rv = lb_get_rgb(in->get_rgb.led,
-				&out->get_rgb.red,
-				&out->get_rgb.green,
-				&out->get_rgb.blue);
-		if (rv == EC_RES_SUCCESS)
-			args->response_size = sizeof(out->get_rgb);
-		return rv;
-	case LIGHTBAR_CMD_GET_SEQ:
-		out->get_seq.num = st.cur_seq;
-		args->response_size = sizeof(out->get_seq);
-		break;
-	case LIGHTBAR_CMD_DEMO:
-		demo_mode = in->demo.num ? 1 : 0;
-		CPRINTS("LB_demo %d", demo_mode);
-		break;
-	case LIGHTBAR_CMD_GET_DEMO:
-		out->get_demo.num = demo_mode;
-		args->response_size = sizeof(out->get_demo);
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V0:
-		CPRINTS("LB_get_params_v0 not supported");
-		return EC_RES_INVALID_VERSION;
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V0:
-		CPRINTS("LB_set_params_v0 not supported");
-		return EC_RES_INVALID_VERSION;
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V1:
-		CPRINTS("LB_get_params_v1");
-		memcpy(&out->get_params_v1, &st.p, sizeof(st.p));
-		args->response_size = sizeof(out->get_params_v1);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V1:
-		CPRINTS("LB_set_params_v1");
-		memcpy(&st.p, &in->set_params_v1, sizeof(st.p));
-		break;
-	case LIGHTBAR_CMD_SET_PROGRAM:
-		CPRINTS("LB_set_program");
-		memcpy(&next_prog,
-		       &in->set_program,
-		       sizeof(struct lightbar_program));
-		break;
-	case LIGHTBAR_CMD_VERSION:
-		CPRINTS("LB_version");
-		out->version.num = LIGHTBAR_IMPLEMENTATION_VERSION;
-		out->version.flags = LIGHTBAR_IMPLEMENTATION_FLAGS;
-		args->response_size = sizeof(out->version);
-		break;
-	case LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL:
-		CPRINTS("LB_manual_suspend_ctrl");
-		manual_suspend_control = in->manual_suspend_ctrl.enable;
-		break;
-	case LIGHTBAR_CMD_SUSPEND:
-		CPRINTS("LB_suspend");
-		lightbar_sequence(LIGHTBAR_S0S3);
-		break;
-	case LIGHTBAR_CMD_RESUME:
-		CPRINTS("LB_resume");
-		lightbar_sequence(LIGHTBAR_S3S0);
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_TIMING:
-		CPRINTS("LB_get_params_v2_timing");
-		memcpy(&out->get_params_v2_timing,
-		       &st.p_v2.timing,
-		       sizeof(st.p_v2.timing));
-		args->response_size = sizeof(out->get_params_v2_timing);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_TIMING:
-		CPRINTS("LB_set_params_v2_timing");
-		memcpy(&st.p_v2.timing,
-		       &in->set_v2par_timing,
-		       sizeof(struct lightbar_params_v2_timing));
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_TAP:
-		CPRINTS("LB_get_params_v2_tap");
-		memcpy(&out->get_params_v2_tap,
-		       &st.p_v2.tap,
-		       sizeof(struct lightbar_params_v2_tap));
-		args->response_size = sizeof(out->get_params_v2_tap);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_TAP:
-		CPRINTS("LB_set_params_v2_tap");
-		memcpy(&st.p_v2.tap,
-		       &in->set_v2par_tap,
-		       sizeof(struct lightbar_params_v2_tap));
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION:
-		CPRINTS("LB_get_params_v2_oscillation");
-		memcpy(&out->get_params_v2_osc, &st.p_v2.osc,
-		       sizeof(struct lightbar_params_v2_oscillation));
-		args->response_size = sizeof(out->get_params_v2_osc);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION:
-		CPRINTS("LB_set_params_v2_oscillation");
-		memcpy(&st.p_v2.osc,
-		       &in->set_v2par_osc,
-		       sizeof(struct lightbar_params_v2_oscillation));
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS:
-		CPRINTS("LB_get_params_v2_brightness");
-		memcpy(&out->get_params_v2_bright,
-		       &st.p_v2.bright,
-		       sizeof(struct lightbar_params_v2_brightness));
-		args->response_size = sizeof(out->get_params_v2_bright);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS:
-		CPRINTS("LB_set_params_v2_brightness");
-		memcpy(&st.p_v2.bright,
-		       &in->set_v2par_bright,
-		       sizeof(struct lightbar_params_v2_brightness));
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS:
-		CPRINTS("LB_get_params_v2_thlds");
-		memcpy(&out->get_params_v2_thlds,
-		       &st.p_v2.thlds,
-		       sizeof(struct lightbar_params_v2_thresholds));
-		args->response_size = sizeof(out->get_params_v2_thlds);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS:
-		CPRINTS("LB_set_params_v2_thlds");
-		memcpy(&st.p_v2.thlds,
-		       &in->set_v2par_thlds,
-		       sizeof(struct lightbar_params_v2_thresholds));
-		break;
-	case LIGHTBAR_CMD_GET_PARAMS_V2_COLORS:
-		CPRINTS("LB_get_params_v2_colors");
-		memcpy(&out->get_params_v2_colors,
-		       &st.p_v2.colors,
-		       sizeof(struct lightbar_params_v2_colors));
-		args->response_size = sizeof(out->get_params_v2_colors);
-		break;
-	case LIGHTBAR_CMD_SET_PARAMS_V2_COLORS:
-		CPRINTS("LB_set_params_v2_colors");
-		memcpy(&st.p_v2.colors,
-		       &in->set_v2par_colors,
-		       sizeof(struct lightbar_params_v2_colors));
-		break;
-	default:
-		CPRINTS("LB bad cmd 0x%x", in->cmd);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD,
-		     lpc_cmd_lightbar,
-		     EC_VER_MASK(0));
-
-/****************************************************************************/
-/* EC console commands */
-/****************************************************************************/
-
-#ifdef CONFIG_CONSOLE_CMDHELP
-static int help(const char *cmd)
-{
-	ccprintf("Usage:\n");
-	ccprintf("  %s                       - dump all regs\n", cmd);
-	ccprintf("  %s off                   - enter standby\n", cmd);
-	ccprintf("  %s on                    - leave standby\n", cmd);
-	ccprintf("  %s init                  - load default vals\n", cmd);
-	ccprintf("  %s brightness [NUM]      - set intensity (0-ff)\n", cmd);
-	ccprintf("  %s seq [NUM|SEQUENCE]    - run given pattern"
-		 " (no arg for list)\n", cmd);
-	ccprintf("  %s CTRL REG VAL          - set LED controller regs\n", cmd);
-	ccprintf("  %s LED RED GREEN BLUE    - set color manually"
-		 " (LED=%d for all)\n", cmd, NUM_LEDS);
-	ccprintf("  %s LED                   - get current LED color\n", cmd);
-	ccprintf("  %s demo [0|1]            - turn demo mode on & off\n", cmd);
-#ifdef LIGHTBAR_SIMULATION
-	ccprintf("  %s program filename      - load lightbyte program\n", cmd);
-#endif
-	ccprintf("  %s version               - show current version\n", cmd);
-	return EC_SUCCESS;
-}
-#endif
-
-static uint8_t find_msg_by_name(const char *str)
-{
-	uint8_t i;
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		if (!strcasecmp(str, lightbar_cmds[i].string))
-			return i;
-
-	return LIGHTBAR_NUM_SEQUENCES;
-}
-
-static void show_msg_names(void)
-{
-	int i;
-	ccprintf("Sequences:");
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		ccprintf(" %s", lightbar_cmds[i].string);
-	ccprintf("\nCurrent = 0x%x %s\n", st.cur_seq,
-		 lightbar_cmds[st.cur_seq].string);
-}
-
-static int command_lightbar(int argc, char **argv)
-{
-	int i;
-	uint8_t num, led, r = 0, g = 0, b = 0;
-	struct ec_response_lightbar out;
-	char *e;
-
-	if (argc == 1) {			/* no args = dump 'em all */
-		lb_hc_cmd_dump(&out);
-		for (i = 0; i < ARRAY_SIZE(out.dump.vals); i++)
-			ccprintf(" %02x     %02x     %02x\n",
-				 out.dump.vals[i].reg,
-				 out.dump.vals[i].ic0,
-				 out.dump.vals[i].ic1);
-
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "init")) {
-		lb_init(1);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "off")) {
-		lb_off();
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "on")) {
-		lb_on();
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "version")) {
-		ccprintf("version %d flags 0x%x\n",
-			 LIGHTBAR_IMPLEMENTATION_VERSION,
-			 LIGHTBAR_IMPLEMENTATION_FLAGS);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "brightness")) {
-		if (argc > 2) {
-			num = 0xff & strtoi(argv[2], &e, 16);
-			lb_set_brightness(num);
-		}
-		ccprintf("brightness is %02x\n", lb_get_brightness());
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "demo")) {
-		if (argc > 2) {
-			if (!strcasecmp(argv[2], "on") ||
-			    argv[2][0] == '1')
-				demo_mode = 1;
-			else if (!strcasecmp(argv[2], "off") ||
-				 argv[2][0] == '0')
-				demo_mode = 0;
-			else
-				return EC_ERROR_PARAM1;
-		}
-		ccprintf("demo mode is %s\n", demo_mode ? "on" : "off");
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "seq")) {
-		if (argc == 2) {
-			show_msg_names();
-			return 0;
-		}
-		num = 0xff & strtoi(argv[2], &e, 16);
-		if (*e)
-			num = find_msg_by_name(argv[2]);
-		if (num >= LIGHTBAR_NUM_SEQUENCES)
-			return EC_ERROR_PARAM2;
-		if (argc > 3)			/* for testing TAP direction */
-			force_dir = strtoi(argv[3], 0, 0);
-		lightbar_sequence(num);
-		return EC_SUCCESS;
-	}
-
-#ifdef LIGHTBAR_SIMULATION
-	/* Load a program. */
-	if (argc >= 3 && !strcasecmp(argv[1], "program")) {
-		return lb_load_program(argv[2], &next_prog);
-	}
-#endif
-
-	if (argc == 4) {
-		struct ec_params_lightbar in;
-		in.reg.ctrl = strtoi(argv[1], &e, 16);
-		in.reg.reg = strtoi(argv[2], &e, 16);
-		in.reg.value = strtoi(argv[3], &e, 16);
-		lb_hc_cmd_reg(&in);
-		return EC_SUCCESS;
-	}
-
-	if (argc == 5) {
-		led = strtoi(argv[1], &e, 16);
-		r = strtoi(argv[2], &e, 16);
-		g = strtoi(argv[3], &e, 16);
-		b = strtoi(argv[4], &e, 16);
-		lb_set_rgb(led, r, g, b);
-		return EC_SUCCESS;
-	}
-
-	/* Only thing left is to try to read an LED value */
-	num = strtoi(argv[1], &e, 16);
-	if (!(e && *e)) {
-		if (num >= NUM_LEDS) {
-			for (i = 0; i < NUM_LEDS; i++) {
-				lb_get_rgb(i, &r, &g, &b);
-				ccprintf("%x: %02x %02x %02x\n", i, r, g, b);
-			}
-		} else {
-			lb_get_rgb(num, &r, &g, &b);
-			ccprintf("%02x %02x %02x\n", r, g, b);
-		}
-		return EC_SUCCESS;
-	}
-
-
-#ifdef CONFIG_CONSOLE_CMDHELP
-	help(argv[0]);
-#endif
-
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar,
-			"[help | COMMAND [ARGS]]",
-			"Get/set lightbar state");
diff --git a/common/mkbp_fifo.c b/common/mkbp_fifo.c
deleted file mode 100644
index 428d6412fc..0000000000
--- a/common/mkbp_fifo.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Matrix KeyBoard Protocol FIFO buffer implementation
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "keyboard_config.h"
-#include "mkbp_event.h"
-#include "mkbp_fifo.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-/*
- * Common FIFO depth.  This needs to be big enough not to overflow if a
- * series of keys is pressed in rapid succession and the kernel is too busy
- * to read them out right away.
- *
- * RAM usage is (depth * #cols); A 16-entry FIFO will consume 16x13=208 bytes,
- * which is non-trivial but not horrible.
- */
-
-static uint32_t fifo_start;	/* first entry */
-static uint32_t fifo_end;	/* last entry */
-static uint32_t fifo_entries;	/* number of existing entries */
-static uint8_t fifo_max_depth = FIFO_DEPTH;
-static struct ec_response_get_next_event fifo[FIFO_DEPTH];
-
-/*
- * Mutex for critical sections of mkbp_fifo_add(), which is called
- * from various tasks.
- */
-K_MUTEX_DEFINE(fifo_add_mutex);
-/*
- * Mutex for critical sections of fifo_remove(), which is called from the
- * hostcmd task and from keyboard_clear_buffer().
- */
-K_MUTEX_DEFINE(fifo_remove_mutex);
-
-static int get_data_size(enum ec_mkbp_event e)
-{
-	switch (e) {
-	case EC_MKBP_EVENT_KEY_MATRIX:
-		return KEYBOARD_COLS_MAX;
-
-#ifdef CONFIG_HOST_EVENT64
-	case EC_MKBP_EVENT_HOST_EVENT64:
-		return sizeof(uint64_t);
-#endif
-
-	case EC_MKBP_EVENT_HOST_EVENT:
-	case EC_MKBP_EVENT_BUTTON:
-	case EC_MKBP_EVENT_SWITCH:
-	case EC_MKBP_EVENT_SYSRQ:
-		return sizeof(uint32_t);
-	default:
-		/* For unknown types, say it's 0. */
-		return 0;
-	}
-}
-
-/**
- * Pop MKBP event data from FIFO
- *
- * @return EC_SUCCESS if entry popped, EC_ERROR_UNKNOWN if FIFO is empty
- */
-static int fifo_remove(uint8_t *buffp)
-{
-	int size;
-
-	mutex_lock(&fifo_remove_mutex);
-	if (!fifo_entries) {
-		/* no entry remaining in FIFO : return last known state */
-		int last = (fifo_start + FIFO_DEPTH - 1) % FIFO_DEPTH;
-
-		size = get_data_size(fifo[last].event_type);
-
-		memcpy(buffp, &fifo[last].data, size);
-		mutex_unlock(&fifo_remove_mutex);
-
-		/*
-		 * Bail out without changing any FIFO indices and let the
-		 * caller know something strange happened. The buffer will
-		 * will contain the last known state of the keyboard.
-		 */
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Return just the event data. */
-	if (buffp) {
-		size = get_data_size(fifo[fifo_start].event_type);
-		/* skip over event_type. */
-		memcpy(buffp, &fifo[fifo_start].data, size);
-	}
-
-	fifo_start = (fifo_start + 1) % FIFO_DEPTH;
-	atomic_sub(&fifo_entries, 1);
-	mutex_unlock(&fifo_remove_mutex);
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Interface */
-
-void mkbp_fifo_depth_update(uint8_t new_max_depth)
-{
-	fifo_max_depth = new_max_depth;
-}
-
-
-void mkbp_fifo_clear_keyboard(void)
-{
-	int i, new_fifo_entries = 0;
-
-	CPRINTS("clear keyboard MKBP fifo");
-
-	/*
-	 * Order of these locks is important to prevent deadlock since
-	 * mkbp_fifo_add() may call fifo_remove().
-	 */
-	mutex_lock(&fifo_add_mutex);
-	mutex_lock(&fifo_remove_mutex);
-
-	/* Reset the end position */
-	fifo_end = fifo_start;
-
-	for (i = 0; i < fifo_entries; i++) {
-		int cur = (fifo_start + i) % FIFO_DEPTH;
-
-		/* Drop keyboard events */
-		if (fifo[cur].event_type == EC_MKBP_EVENT_KEY_MATRIX)
-			continue;
-
-		/* And move other events to the front */
-		memmove(&fifo[fifo_end], &fifo[cur], sizeof(fifo[cur]));
-		fifo_end = (fifo_end + 1) % FIFO_DEPTH;
-		++new_fifo_entries;
-	}
-	fifo_entries = new_fifo_entries;
-
-	mutex_unlock(&fifo_remove_mutex);
-	mutex_unlock(&fifo_add_mutex);
-}
-
-void mkbp_clear_fifo(void)
-{
-	int i;
-
-	CPRINTS("clear MKBP fifo");
-
-	/*
-	 * Order of these locks is important to prevent deadlock since
-	 * mkbp_fifo_add() may call fifo_remove().
-	 */
-	mutex_lock(&fifo_add_mutex);
-	mutex_lock(&fifo_remove_mutex);
-
-	fifo_start = 0;
-	fifo_end = 0;
-	/* This assignment is safe since both mutexes are held. */
-	fifo_entries = 0;
-	for (i = 0; i < FIFO_DEPTH; i++)
-		memset(&fifo[i], 0, sizeof(struct ec_response_get_next_event));
-
-	mutex_unlock(&fifo_remove_mutex);
-	mutex_unlock(&fifo_add_mutex);
-}
-
-test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp)
-{
-	uint8_t size;
-
-	mutex_lock(&fifo_add_mutex);
-	if (fifo_entries >= fifo_max_depth) {
-		mutex_unlock(&fifo_add_mutex);
-		CPRINTS("MKBP common FIFO depth %d reached",
-			fifo_max_depth);
-
-		return EC_ERROR_OVERFLOW;
-	}
-
-	size = get_data_size(event_type);
-	fifo[fifo_end].event_type = event_type;
-	memcpy(&fifo[fifo_end].data, buffp, size);
-	fifo_end = (fifo_end + 1) % FIFO_DEPTH;
-	atomic_add(&fifo_entries, 1);
-
-	/*
-	 * If our event didn't generate an interrupt then the host is still
-	 * asleep. In this case, we don't want to queue our event, except if
-	 * another event just woke the host (and wake is already in progress).
-	 */
-	if (!mkbp_send_event(event_type) && fifo_entries == 1)
-		fifo_remove(NULL);
-
-	mutex_unlock(&fifo_add_mutex);
-	return EC_SUCCESS;
-}
-
-int mkbp_fifo_get_next_event(uint8_t *out, enum ec_mkbp_event evt)
-{
-	uint8_t t = fifo[fifo_start].event_type;
-	uint8_t size;
-
-	if (!fifo_entries)
-		return -1;
-
-	/*
-	 * We need to peek at the next event to check that we were called with
-	 * the correct event.
-	 */
-	if (t != (uint8_t)evt) {
-		/*
-		 * We were called with the wrong event.  The next element in the
-		 * FIFO's event type doesn't match with what we were called
-		 * with.  Return an error that we're busy.  The caller will need
-		 * to call us with the correct event first.
-		 */
-		return -EC_ERROR_BUSY;
-	}
-
-	fifo_remove(out);
-
-	/* Keep sending events if FIFO is not empty */
-	if (fifo_entries)
-		mkbp_send_event(fifo[fifo_start].event_type);
-
-	/* Return the correct size of the data. */
-	size = get_data_size(t);
-	if (size)
-		return size;
-	else
-		return -EC_ERROR_UNKNOWN;
-}
diff --git a/common/mkbp_info.c b/common/mkbp_info.c
deleted file mode 100644
index b3835367cf..0000000000
--- a/common/mkbp_info.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MKBP info host command */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "keyboard_config.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_scan.h"
-#include "mkbp_input_devices.h"
-#include "util.h"
-
-static uint32_t get_supported_buttons(void)
-{
-	uint32_t val = 0;
-
-#ifdef CONFIG_VOLUME_BUTTONS
-	val |= BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN);
-#endif /* defined(CONFIG_VOLUME_BUTTONS) */
-
-#ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
-	val |= BIT(EC_MKBP_RECOVERY);
-#endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
-
-#ifdef CONFIG_POWER_BUTTON
-	val |= BIT(EC_MKBP_POWER_BUTTON);
-#endif /* defined(CONFIG_POWER_BUTTON) */
-
-	return val;
-}
-
-static uint32_t get_supported_switches(void)
-{
-	uint32_t val = 0;
-
-#ifdef CONFIG_LID_SWITCH
-	val |= BIT(EC_MKBP_LID_OPEN);
-#endif
-#ifdef CONFIG_TABLET_MODE_SWITCH
-	val |= BIT(EC_MKBP_TABLET_MODE);
-#endif
-#ifdef CONFIG_BASE_ATTACHED_SWITCH
-	val |= BIT(EC_MKBP_BASE_ATTACHED);
-#endif
-#ifdef CONFIG_FRONT_PROXIMITY_SWITCH
-	val |= BIT(EC_MKBP_FRONT_PROXIMITY);
-#endif
-	return val;
-}
-
-static enum ec_status mkbp_get_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_mkbp_info *p = args->params;
-
-	if (args->params_size == 0 || p->info_type == EC_MKBP_INFO_KBD) {
-		struct ec_response_mkbp_info *r = args->response;
-
-#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-		/* Version 0 just returns info about the keyboard. */
-		r->rows = KEYBOARD_ROWS;
-		r->cols = KEYBOARD_COLS_MAX;
-#else
-		r->rows = 0;
-		r->cols = 0;
-#endif /* CONFIG_KEYBOARD_PROTOCOL_MKBP */
-
-		/* This used to be "switches" which was previously 0. */
-		r->reserved = 0;
-
-		args->response_size = sizeof(struct ec_response_mkbp_info);
-	} else {
-		union ec_response_get_next_data *r = args->response;
-
-		/* Version 1 (other than EC_MKBP_INFO_KBD) */
-		switch (p->info_type) {
-		case EC_MKBP_INFO_SUPPORTED:
-			switch (p->event_type) {
-			case EC_MKBP_EVENT_BUTTON:
-				r->buttons = get_supported_buttons();
-				args->response_size = sizeof(r->buttons);
-				break;
-
-			case EC_MKBP_EVENT_SWITCH:
-				r->switches = get_supported_switches();
-				args->response_size = sizeof(r->switches);
-				break;
-
-			default:
-				/* Don't care for now for other types. */
-				return EC_RES_INVALID_PARAM;
-			}
-			break;
-
-		case EC_MKBP_INFO_CURRENT:
-			switch (p->event_type) {
-#ifdef HAS_TASK_KEYSCAN
-			case EC_MKBP_EVENT_KEY_MATRIX:
-				memcpy(r->key_matrix, keyboard_scan_get_state(),
-				       sizeof(r->key_matrix));
-				args->response_size = sizeof(r->key_matrix);
-				break;
-#endif
-			case EC_MKBP_EVENT_HOST_EVENT:
-				r->host_event = (uint32_t)host_get_events();
-				args->response_size = sizeof(r->host_event);
-				break;
-
-#ifdef CONFIG_HOST_EVENT64
-			case EC_MKBP_EVENT_HOST_EVENT64:
-				r->host_event64 = host_get_events();
-				args->response_size = sizeof(r->host_event64);
-				break;
-#endif
-
-#ifdef CONFIG_MKBP_INPUT_DEVICES
-			case EC_MKBP_EVENT_BUTTON:
-				r->buttons = mkbp_get_button_state();
-				args->response_size = sizeof(r->buttons);
-				break;
-
-			case EC_MKBP_EVENT_SWITCH:
-				r->switches = mkbp_get_switch_state();
-				args->response_size = sizeof(r->switches);
-				break;
-#endif /* CONFIG_MKBP_INPUT_DEVICES */
-
-			default:
-				/* Doesn't make sense for other event types. */
-				return EC_RES_INVALID_PARAM;
-			}
-			break;
-
-		default:
-			/* Unsupported query. */
-			return EC_RES_ERROR;
-		}
-	}
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_INFO, mkbp_get_info,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
diff --git a/common/mkbp_input_devices.c b/common/mkbp_input_devices.c
deleted file mode 100644
index e058c9d320..0000000000
--- a/common/mkbp_input_devices.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Input devices using Matrix Keyboard Protocol [MKBP] events for Chrome EC */
-
-#include "base_state.h"
-#include "button.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "mkbp_event.h"
-#include "mkbp_fifo.h"
-#include "mkbp_input_devices.h"
-#include "power_button.h"
-#include "tablet_mode.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
-
-/* Buttons and switch state. */
-static uint32_t mkbp_button_state;
-static uint32_t mkbp_switch_state;
-
-static bool mkbp_init_done;
-
-uint32_t mkbp_get_switch_state(void)
-{
-	return mkbp_switch_state;
-};
-
-uint32_t mkbp_get_button_state(void)
-{
-	return mkbp_button_state;
-};
-
-void mkbp_button_update(enum keyboard_button_type button, int is_pressed)
-{
-	switch (button) {
-	case KEYBOARD_BUTTON_POWER:
-		mkbp_button_state &= ~BIT(EC_MKBP_POWER_BUTTON);
-		mkbp_button_state |= (is_pressed << EC_MKBP_POWER_BUTTON);
-		break;
-
-	case KEYBOARD_BUTTON_VOLUME_UP:
-		mkbp_button_state &= ~BIT(EC_MKBP_VOL_UP);
-		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_UP);
-		break;
-
-	case KEYBOARD_BUTTON_VOLUME_DOWN:
-		mkbp_button_state &= ~BIT(EC_MKBP_VOL_DOWN);
-		mkbp_button_state |= (is_pressed << EC_MKBP_VOL_DOWN);
-		break;
-
-	case KEYBOARD_BUTTON_RECOVERY:
-		mkbp_button_state &= ~BIT(EC_MKBP_RECOVERY);
-		mkbp_button_state |= (is_pressed << EC_MKBP_RECOVERY);
-		break;
-
-	default:
-		/* ignored. */
-		return;
-	}
-
-	CPRINTS("mkbp buttons: %x", mkbp_button_state);
-
-	mkbp_fifo_add(EC_MKBP_EVENT_BUTTON,
-			(const uint8_t *)&mkbp_button_state);
-};
-
-void mkbp_update_switches(uint32_t sw, int state)
-{
-	mkbp_switch_state &= ~BIT(sw);
-	mkbp_switch_state |= (!!state << sw);
-
-	CPRINTS("mkbp switches: %x", mkbp_switch_state);
-
-	/*
-	 * Only inform AP mkbp changes when all switches initialized, in case
-	 * of the middle states causing the weird behaviour in the AP side,
-	 * especially when sysjumped while AP up.
-	 */
-	if (mkbp_init_done)
-		mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
-				(const uint8_t *)&mkbp_switch_state);
-}
-
-
-/*****************************************************************************/
-/* Hooks */
-
-#ifdef CONFIG_POWER_BUTTON
-/**
- * Handle power button changing state.
- */
-static void keyboard_power_button(void)
-{
-	mkbp_button_update(KEYBOARD_BUTTON_POWER,
-			       power_button_is_pressed());
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
-	     HOOK_PRIO_DEFAULT);
-#endif /* defined(CONFIG_POWER_BUTTON) */
-
-#ifdef CONFIG_LID_SWITCH
-/**
- * Handle lid changing state.
- */
-static void mkbp_lid_change(void)
-{
-	mkbp_update_switches(EC_MKBP_LID_OPEN, lid_is_open());
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, mkbp_lid_change, HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_lid_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-#ifdef CONFIG_TABLET_MODE_SWITCH
-static void mkbp_tablet_mode_change(void)
-{
-	mkbp_update_switches(EC_MKBP_TABLET_MODE, tablet_get_mode());
-}
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, mkbp_tablet_mode_change, HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_tablet_mode_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-#ifdef CONFIG_BASE_ATTACHED_SWITCH
-static void mkbp_base_attached_change(void)
-{
-	mkbp_update_switches(EC_MKBP_BASE_ATTACHED, base_get_state());
-}
-DECLARE_HOOK(HOOK_BASE_ATTACHED_CHANGE, mkbp_base_attached_change,
-	     HOOK_PRIO_LAST);
-DECLARE_HOOK(HOOK_INIT, mkbp_base_attached_change, HOOK_PRIO_INIT_LID+1);
-#endif
-
-static void mkbp_report_switch_on_init(void)
-{
-	/* All switches initialized, report switch state to AP */
-	mkbp_init_done = true;
-	mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
-			(const uint8_t *)&mkbp_switch_state);
-}
-DECLARE_HOOK(HOOK_INIT, mkbp_report_switch_on_init, HOOK_PRIO_LAST);
-
-#ifdef CONFIG_EMULATED_SYSRQ
-void host_send_sysrq(uint8_t key)
-{
-	uint32_t value = key;
-
-	mkbp_fifo_add(EC_MKBP_EVENT_SYSRQ, (const uint8_t *)&value);
-}
-#endif
-
-/*****************************************************************************/
-/* Events */
-
-static int mkbp_button_get_next_event(uint8_t *out)
-{
-	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_BUTTON);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_BUTTON, mkbp_button_get_next_event);
-
-static int switch_get_next_event(uint8_t *out)
-{
-	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_SWITCH);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SWITCH, switch_get_next_event);
-
-#ifdef CONFIG_EMULATED_SYSRQ
-static int sysrq_get_next_event(uint8_t *out)
-{
-	return mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_SYSRQ);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_SYSRQ, sysrq_get_next_event);
-#endif
-
-/************************ Keyboard press simulation ************************/
-#ifndef HAS_TASK_KEYSCAN
-/* Keys simulated-pressed */
-static uint8_t __bss_slow simulated_key[KEYBOARD_COLS_MAX];
-uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
-
-/* For boards without a keyscan task, try and simulate keyboard presses. */
-static void simulate_key(int row, int col, int pressed)
-{
-	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
-
-	simulated_key[col] &= ~BIT(row);
-	if (pressed)
-		simulated_key[col] |= BIT(row);
-
-	mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, simulated_key);
-}
-
-static int command_mkbp_keyboard_press(int argc, char **argv)
-{
-	if (argc == 1) {
-		int i, j;
-
-		ccputs("Simulated keys:\n");
-		for (i = 0; i < keyboard_cols; ++i) {
-			if (simulated_key[i] == 0)
-				continue;
-			for (j = 0; j < KEYBOARD_ROWS; ++j)
-				if (simulated_key[i] & BIT(j))
-					ccprintf("\t%d %d\n", i, j);
-		}
-
-	} else if (argc == 3 || argc == 4) {
-		int r, c, p;
-		char *e;
-
-		c = strtoi(argv[1], &e, 0);
-		if (*e || c < 0 || c >= keyboard_cols)
-			return EC_ERROR_PARAM1;
-
-		r = strtoi(argv[2], &e, 0);
-		if (*e || r < 0 || r >= KEYBOARD_ROWS)
-			return EC_ERROR_PARAM2;
-
-		if (argc == 3) {
-			/* Simulate a press and release */
-			simulate_key(r, c, 1);
-			simulate_key(r, c, 0);
-		} else {
-			p = strtoi(argv[3], &e, 0);
-			if (*e || p < 0 || p > 1)
-				return EC_ERROR_PARAM3;
-
-			simulate_key(r, c, p);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(kbpress, command_mkbp_keyboard_press,
-			"[col row [0 | 1]]",
-			"Simulate keypress");
-
-#endif /* !defined(HAS_TASK_KEYSCAN) */
diff --git a/common/mock/README.md b/common/mock/README.md
deleted file mode 100644
index c7695531b6..0000000000
--- a/common/mock/README.md
+++ /dev/null
@@ -1,88 +0,0 @@
-# Common Mocks
-
-This directory holds mock implementations for use in fuzzers and tests.
-
-Each mock is given some friendly build name, like ROLLBACK or FP_SENSOR. This
-name is defined in [common/mock/build.mk](build.mk) and referenced from unit
-tests and fuzzers' `.mocklist` file.
-
-## Creating a new mock
-
-*   Add the mock source to [common/mock](/common/mock) and the optional header
-    file to [include/mock](/include/mock). Header files are only necessary if
-    you want to expose additional [mock control](#mock-controls)
-    functions/variables. See the [Design Patterns](#design-patterns) section for
-    more detail on design patterns.
-*   Add a new entry in [common/mock/build.mk](build.mk) that is conditioned on
-    your mock's name.
-
-If a unit test or fuzzer requests this mock, the build system will set the
-variable `HAS_MOCK_<BUILD_NAME>` to `y` at build time. This variable is used to
-conditionally include the mock source in [common/mock/build.mk](build.mk).
-
-Example line from [common/mock/build.mk](build.mk):
-
-```make
-# Mocks
-mock-$(HAS_MOCK_ROLLBACK) += mock/rollback_mock.o
-```
-
-## Using a mock
-
-Unit tests and fuzzers can request a particular mock by adding an entry to their
-`.mocklist` file. The mocklist file is similar to a `.tasklist` file, where it
-is named according to the test/fuzz's name followed by `.mocklist`, like
-`fpsensor.mocklist`. The mocklist file is optional, so you may need to create
-one.
-
-Example `.mocklist`:
-
-```c
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST \
-    MOCK(ROLLBACK)             \
-    MOCK(FP_SENSOR)
-```
-
-If you need additional [mock control](#mock-controls) functionality, you may
-need to include the mock's header file, which is prepended with `mock/` in the
-include line.
-
-For example, to control the return values of the rollback mock:
-
-```c
-#include "mock/rollback_mock.h"
-
-void yourfunction() {
-    mock_ctrl_rollback.get_secret_fail = true;
-}
-```
-
-## Mock Controls
-
-Mocks can change their behavior by exposing "mock controls".
-
-We do this, most commonly, by exposing an additional global struct per mock that
-acts as the settings for the mock implementation. The mock user can then modify
-fields of the struct to change the mock's behavior. For example, the
-`fp_sensor_init_return` field may control what value the mocked `fp_sensor_init`
-function returns.
-
-The declaration for these controls are specified in the mock's header file,
-which resides in [include/mock](/include/mock).
-
-## Design Patterns
-
-*   When creating mock controls, consider placing all your mock parameters in
-    one externally facing struct, like in
-    [fp_sensor_mock.h](/include/mock/fp_sensor_mock.h). The primary reason for
-    this is to allow the mock to be easily used by a fuzzer (write random bytes
-    into the struct with memcpy).
-*   When following the above pattern, please provide a macro for resetting
-    default values for this struct, like in
-    [fp_sensor_mock.h](/include/mock/fp_sensor_mock.h). This allows unit tests
-    to quickly reset the mock state/parameters before each unrelated unit test.
diff --git a/common/mock/battery_mock.c b/common/mock/battery_mock.c
deleted file mode 100644
index 63e94c660b..0000000000
--- a/common/mock/battery_mock.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "string.h"
-
-/*****************************************************************************
- * Battery functions needed to enable CONFIG_BATTERY
- */
-static int battery_soc_value = 100;
-int board_get_battery_soc(void)
-{
-	return battery_soc_value;
-}
-void set_battery_soc(int new_value)
-{
-	battery_soc_value = new_value;
-}
-
-static int battery_status_value;
-int battery_status(int *status)
-{
-	*status = battery_status_value;
-	return EC_SUCCESS;
-}
-void set_battery_status(int new_value)
-{
-	battery_status_value = new_value;
-}
-
-static int battery_serial_number_value;
-int battery_serial_number(int *serial)
-{
-	*serial = battery_serial_number_value;
-	return EC_SUCCESS;
-}
-void set_battery_serial_number(int new_value)
-{
-	battery_serial_number_value = new_value;
-}
-
-static int battery_design_voltage_value = 5000;
-int battery_design_voltage(int *voltage)
-{
-	*voltage = battery_design_voltage_value;
-	return EC_SUCCESS;
-}
-void set_battery_design_voltage(int new_value)
-{
-	battery_design_voltage_value = new_value;
-}
-
-static int battery_mode_value;
-int battery_get_mode(int *mode)
-{
-	*mode = battery_mode_value;
-	return EC_SUCCESS;
-}
-void set_battery_mode(int new_value)
-{
-	battery_mode_value = new_value;
-}
-
-static int battery_soc_abs_value = 100;
-int battery_state_of_charge_abs(int *percent)
-{
-	*percent = battery_soc_abs_value;
-	return EC_SUCCESS;
-}
-void set_battery_soc_abs(int new_value)
-{
-	battery_soc_abs_value = new_value;
-}
-
-static int battery_remaining_capacity_value = 100;
-int battery_remaining_capacity(int *capacity)
-{
-	*capacity = battery_remaining_capacity_value;
-	return EC_SUCCESS;
-}
-void set_battery_remaining_capacity(int new_value)
-{
-	battery_remaining_capacity_value = new_value;
-}
-
-static int battery_full_charge_capacity_value = 100;
-int battery_full_charge_capacity(int *capacity)
-{
-	*capacity = battery_full_charge_capacity_value;
-	return EC_SUCCESS;
-}
-void set_battery_full_charge_capacity(int new_value)
-{
-	battery_full_charge_capacity_value = new_value;
-}
-
-static int battery_design_capacity_value = 100;
-int battery_design_capacity(int *capacity)
-{
-	*capacity = battery_design_capacity_value;
-	return EC_SUCCESS;
-}
-void set_battery_design_capacity(int new_value)
-{
-	battery_design_capacity_value = new_value;
-}
-
-static int battery_time_to_empty_value = 60;
-int battery_time_to_empty(int *minutes)
-{
-	*minutes = battery_time_to_empty_value;
-	return EC_SUCCESS;
-}
-void set_battery_time_to_empty(int new_value)
-{
-	battery_time_to_empty_value = new_value;
-}
-
-static int battery_run_time_to_empty_value = 60;
-int battery_run_time_to_empty(int *minutes)
-{
-	*minutes = battery_run_time_to_empty_value;
-	return EC_SUCCESS;
-}
-void set_battery_run_time_to_empty(int new_value)
-{
-	battery_run_time_to_empty_value = new_value;
-}
-
-static int battery_time_to_full_value;
-int battery_time_to_full(int *minutes)
-{
-	*minutes = battery_time_to_full_value;
-	return EC_SUCCESS;
-}
-void set_battery_time_to_full(int new_value)
-{
-	battery_time_to_full_value = new_value;
-}
-
-#define MAX_DEVICE_NAME_LENGTH 40
-static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH+1] = "?";
-int battery_device_name(char *dest, int size)
-{
-	int i;
-
-	for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i)
-		dest[i] = battery_device_name_value[i];
-	for (; i < size; ++i)
-		dest[i] = '\0';
-	return EC_SUCCESS;
-}
-void set_battery_device_name(char *new_value)
-{
-	int i;
-	int size = strlen(new_value);
-
-	for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i)
-		battery_device_name_value[i] = new_value[i];
-	for (; i < MAX_DEVICE_NAME_LENGTH+1; ++i)
-		battery_device_name_value[i] = '\0';
-}
-
-#define MAX_DEVICE_CHEMISTRY_LENGTH 40
-static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH+1] = "?";
-int battery_device_chemistry(char *dest, int size)
-{
-	int i;
-
-	for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i)
-		dest[i] = battery_device_chemistry_value[i];
-	for (; i < size; ++i)
-		dest[i] = '\0';
-	return EC_SUCCESS;
-}
-void set_battery_device_chemistry(char *new_value)
-{
-	int i;
-	int size = strlen(new_value);
-
-	for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i)
-		battery_device_chemistry_value[i] = new_value[i];
-	for (; i < MAX_DEVICE_CHEMISTRY_LENGTH+1; ++i)
-		battery_device_chemistry_value[i] = '\0';
-}
-
-static int battery_current_value = 3000;
-static int battery_desired_current_value = 3000;
-static int battery_desired_voltage_value = 5000;
-static int battery_is_present_value = BP_YES;
-static int battery_temperature_value = 20;
-static int battery_voltage_value = 5000;
-void battery_get_params(struct batt_params *batt)
-{
-	struct batt_params batt_new = {0};
-
-	batt_new.temperature = battery_temperature_value;
-	batt_new.state_of_charge = battery_soc_value;
-	batt_new.voltage = battery_voltage_value;
-	batt_new.current = battery_current_value;
-	batt_new.desired_voltage = battery_desired_voltage_value;
-	batt_new.desired_current = battery_desired_current_value;
-	batt_new.remaining_capacity = battery_remaining_capacity_value;
-	batt_new.full_capacity = battery_full_charge_capacity_value;
-	batt_new.status = battery_status_value;
-	batt_new.is_present = battery_is_present_value;
-
-	memcpy(batt, &batt_new, sizeof(*batt));
-}
diff --git a/common/mock/build.mk b/common/mock/build.mk
deleted file mode 100644
index 91607b2b1e..0000000000
--- a/common/mock/build.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# See common/mock/README.md for more information.
-
-mock-$(HAS_MOCK_BATTERY) += battery_mock.o
-mock-$(HAS_MOCK_CHARGE_MANAGER) += charge_manager_mock.o
-mock-$(HAS_MOCK_FP_SENSOR) += fp_sensor_mock.o
-mock-$(HAS_MOCK_FPSENSOR_DETECT) += fpsensor_detect_mock.o
-mock-$(HAS_MOCK_FPSENSOR_STATE) += fpsensor_state_mock.o
-mock-$(HAS_MOCK_MKBP_EVENTS) += mkbp_events_mock.o
-mock-$(HAS_MOCK_ROLLBACK) += rollback_mock.o
-mock-$(HAS_MOCK_TCPC) += tcpc_mock.o
-mock-$(HAS_MOCK_TCPM) += tcpm_mock.o
-mock-$(HAS_MOCK_TCPCI_I2C) += tcpci_i2c_mock.o
-mock-$(HAS_MOCK_TIMER) += timer_mock.o
-mock-$(HAS_MOCK_USB_MUX) += usb_mux_mock.o
-mock-$(HAS_MOCK_USB_PE_SM) += usb_pe_sm_mock.o
-mock-$(HAS_MOCK_USB_TC_SM) += usb_tc_sm_mock.o
-mock-$(HAS_MOCK_USB_PD_DPM) += usb_pd_dpm_mock.o
-mock-$(HAS_MOCK_DP_ALT_MODE) += dp_alt_mode_mock.o
-mock-$(HAS_MOCK_USB_PRL) += usb_prl_mock.o
diff --git a/common/mock/charge_manager_mock.c b/common/mock/charge_manager_mock.c
deleted file mode 100644
index 11661d2b2e..0000000000
--- a/common/mock/charge_manager_mock.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Mock charge_manager
- */
-
-#include <stdlib.h>
-
-#include "charge_manager.h"
-#include "common.h"
-#include "mock/charge_manager_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-void charge_manager_update_dualrole(int port, enum dualrole_capabilities cap)
-{
-}
-
-void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
-{
-}
-
-int charge_manager_get_selected_charge_port(void)
-{
-	return 0;
-}
-
-int charge_manager_get_active_charge_port(void)
-{
-	return 0;
-}
-
-int charge_manager_get_vbus_voltage(int port)
-{
-	return mock_ctrl_charge_manager.vbus_voltage_mv;
-}
-
-void mock_charge_manager_set_vbus_voltage(int voltage_mv)
-{
-	mock_ctrl_charge_manager.vbus_voltage_mv = voltage_mv;
-}
-
-struct mock_ctrl_charge_manager mock_ctrl_charge_manager =
-MOCK_CTRL_DEFAULT_CHARGE_MANAGER;
diff --git a/common/mock/dp_alt_mode_mock.c b/common/mock/dp_alt_mode_mock.c
deleted file mode 100644
index c489d39830..0000000000
--- a/common/mock/dp_alt_mode_mock.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Mock for DisplayPort alternate mode support
- * Refer to VESA DisplayPort Alt Mode on USB Type-C Standard, version 2.0,
- * section 5.2
- */
-
-#include "usb_dp_alt_mode.h"
-#include "mock/dp_alt_mode_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-void mock_dp_alt_mode_reset(void)
-{
-	/* Nothing to do right now, but in the future ... */
-}
-
-void dp_init(int port)
-{
-	CPRINTS("C%d: DP init", port);
-}
diff --git a/common/mock/fp_sensor_mock.c b/common/mock/fp_sensor_mock.c
deleted file mode 100644
index 363f092ff1..0000000000
--- a/common/mock/fp_sensor_mock.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Mock fpsensor private driver
- */
-
-#include <stdlib.h>
-
-#include "common.h"
-#include "fpsensor.h"
-#include "mock/fp_sensor_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor = MOCK_CTRL_DEFAULT_FP_SENSOR;
-
-int fp_sensor_init(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_init_return;
-}
-
-int fp_sensor_deinit(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_deinit_return;
-}
-
-int fp_sensor_get_info(struct ec_response_fp_info *resp)
-{
-	resp->version = 0;
-	return mock_ctrl_fp_sensor.fp_sensor_get_info_return;
-}
-
-void fp_sensor_low_power(void)
-{
-}
-
-void fp_sensor_configure_detect(void)
-{
-}
-
-enum finger_state fp_sensor_finger_status(void)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_finger_status_return;
-}
-
-int fp_sensor_acquire_image(uint8_t *image_data)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_return;
-}
-
-int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
-{
-	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_with_mode_return;
-}
-
-int fp_finger_match(void *templ, uint32_t templ_count,
-		    uint8_t *image, int32_t *match_index,
-		    uint32_t *update_bitmap)
-{
-	return mock_ctrl_fp_sensor.fp_finger_match_return;
-}
-
-int fp_enrollment_begin(void)
-{
-	return mock_ctrl_fp_sensor.fp_enrollment_begin_return;
-}
-
-int fp_enrollment_finish(void *templ)
-{
-	return mock_ctrl_fp_sensor.fp_enrollment_finish_return;
-}
-
-int fp_finger_enroll(uint8_t *image, int *completion)
-{
-	return mock_ctrl_fp_sensor.fp_finger_enroll_return;
-}
-
-int fp_maintenance(void)
-{
-	return mock_ctrl_fp_sensor.fp_maintenance_return;
-}
diff --git a/common/mock/fpsensor_detect_mock.c b/common/mock/fpsensor_detect_mock.c
deleted file mode 100644
index 6e3ca839f1..0000000000
--- a/common/mock/fpsensor_detect_mock.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/fpsensor_detect_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_ctrl_fpsensor_detect mock_ctrl_fpsensor_detect =
-	MOCK_CTRL_DEFAULT_FPSENSOR_DETECT;
-
-enum fp_sensor_type get_fp_sensor_type(void)
-{
-	return mock_ctrl_fpsensor_detect.get_fp_sensor_type_return;
-}
-
-enum fp_transport_type get_fp_transport_type(void)
-{
-	return mock_ctrl_fpsensor_detect.get_fp_transport_type_return;
-}
-
-enum fp_sensor_spi_select get_fp_sensor_spi_select(void)
-{
-	return mock_ctrl_fpsensor_detect.get_fp_sensor_spi_select_return;
-}
diff --git a/common/mock/fpsensor_state_mock.c b/common/mock/fpsensor_state_mock.c
deleted file mode 100644
index c3092fe860..0000000000
--- a/common/mock/fpsensor_state_mock.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include <string.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "test_util.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-const uint8_t default_fake_tpm_seed[] = {
-	0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60, 0xf8, 0x5a, 0xa0,
-	0xa6, 0x2c, 0xb3, 0xf5, 0xe2, 0xeb, 0xb9, 0xd8, 0x2f, 0xb5, 0x78,
-	0x5c, 0x79, 0x82, 0xce, 0x06, 0x3f, 0xcc, 0x23, 0xb9, 0xe7,
-};
-BUILD_ASSERT(sizeof(default_fake_tpm_seed) == FP_CONTEXT_TPM_BYTES);
-
-int fpsensor_state_mock_set_tpm_seed(
-	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES])
-{
-	struct ec_params_fp_seed params;
-
-	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(params.seed, tpm_seed, FP_CONTEXT_TPM_BYTES);
-
-	return test_send_host_command(EC_CMD_FP_SEED, 0, &params,
-				      sizeof(params), NULL, 0);
-}
diff --git a/common/mock/mkbp_events_mock.c b/common/mock/mkbp_events_mock.c
deleted file mode 100644
index d42c06fdec..0000000000
--- a/common/mock/mkbp_events_mock.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Mock event handling for MKBP keyboard protocol
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "mock/mkbp_events_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events =
-	MOCK_CTRL_DEFAULT_MKBP_EVENTS;
-
-int mkbp_send_event(uint8_t event_type)
-{
-	return mock_ctrl_mkbp_events.mkbp_send_event_return;
-}
diff --git a/common/mock/rollback_mock.c b/common/mock/rollback_mock.c
deleted file mode 100644
index 2b26d9d8d7..0000000000
--- a/common/mock/rollback_mock.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Mock rollback block library
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "util.h"
-#include "mock/rollback_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_ctrl_rollback mock_ctrl_rollback = MOCK_CTRL_DEFAULT_ROLLBACK;
-
-static const uint8_t fake_rollback_secret[] = {
-	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f,
-	0x0d, 0xb6, 0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61,
-	0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09, 0x54, 0x8a,
-	0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,
-};
-
-BUILD_ASSERT(sizeof(fake_rollback_secret) == CONFIG_ROLLBACK_SECRET_SIZE);
-
-/* Mock the rollback for unit or fuzz tests. */
-int rollback_get_secret(uint8_t *secret)
-{
-	if (mock_ctrl_rollback.get_secret_fail)
-		return EC_ERROR_UNKNOWN;
-	memcpy(secret, fake_rollback_secret, sizeof(fake_rollback_secret));
-	return EC_SUCCESS;
-}
diff --git a/common/mock/tcpc_mock.c b/common/mock/tcpc_mock.c
deleted file mode 100644
index 7097837268..0000000000
--- a/common/mock/tcpc_mock.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock for the TCPC interface */
-
-#include "common.h"
-#include "console.h"
-#include "memory.h"
-#include "mock/tcpc_mock.h"
-#include "test_util.h"
-#include "tests/enum_strings.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef CONFIG_COMMON_RUNTIME
-#define cprints(format, args...)
-#endif
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-/* Public API for controlling/inspecting this mock */
-struct mock_tcpc_ctrl mock_tcpc;
-
-void mock_tcpc_reset(void)
-{
-	/* Reset all control values to 0. See also build assert below */
-	memset(&mock_tcpc, 0, sizeof(mock_tcpc));
-
-	/* Reset all last viewed variables to -1 to make them invalid  */
-	memset(&mock_tcpc.last, 0xff, sizeof(mock_tcpc.last));
-}
-BUILD_ASSERT(TYPEC_CC_VOLT_OPEN == 0, "Ensure Open is 0-value for memset");
-
-static int mock_init(int port)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_release(int port)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-		       enum tcpc_cc_voltage_status *cc2)
-{
-	*cc1 = mock_tcpc.cc1;
-	*cc2 = mock_tcpc.cc2;
-	return EC_SUCCESS;
-}
-
-static bool mock_check_vbus_level(int port, enum vbus_level level)
-{
-	if (level == VBUS_PRESENT)
-		return mock_tcpc.vbus_level;
-	else if (level == VBUS_SAFE0V || level == VBUS_REMOVED)
-		return !mock_tcpc.vbus_level;
-
-	/*
-	 * Unknown vbus_level was added, force a failure.
-	 * Note that TCPC drivers and pd_check_vbus_level() implementations
-	 * should be carefully checked on new level additions in case they
-	 * need updated.
-	 */
-	ccprints("[TCPC] Unhandled Vbus check %d", level);
-	TEST_ASSERT(0);
-}
-
-static int mock_select_rp_value(int port, int rp)
-{
-	mock_tcpc.last.rp = rp;
-
-	if (!mock_tcpc.should_print_call)
-		return EC_SUCCESS;
-
-	ccprints("[TCPC] Setting TCPM-side Rp to %s", from_tcpc_rp_value(rp));
-
-	return EC_SUCCESS;
-}
-
-static int mock_set_cc(int port, int pull)
-{
-	mock_tcpc.last.cc = pull;
-
-	if (mock_tcpc.callbacks.set_cc)
-		mock_tcpc.callbacks.set_cc(port, pull);
-
-	if (!mock_tcpc.should_print_call)
-		return EC_SUCCESS;
-
-	ccprints("[TCPC] Setting TCPM-side CC to %s", from_tcpc_cc_pull(pull));
-
-	return EC_SUCCESS;
-}
-
-static int mock_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	mock_tcpc.last.polarity = polarity;
-
-	if (!mock_tcpc.should_print_call)
-		return EC_SUCCESS;
-
-	ccprints("[TCPC] Setting TCPM-side polarity to %s",
-		 from_tcpc_cc_polarity(polarity));
-
-	return EC_SUCCESS;
-}
-
-static int mock_set_vconn(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_set_msg_header(int port, int power_role, int data_role)
-{
-	++mock_tcpc.num_calls_to_set_header;
-
-	mock_tcpc.last.power_role = power_role;
-	mock_tcpc.last.data_role = data_role;
-
-	if (!mock_tcpc.should_print_call)
-		return EC_SUCCESS;
-
-	ccprints("[TCPC] Setting TCPM-side header to %s %s",
-		 from_pd_power_role(power_role),
-		 from_pd_data_role(data_role));
-
-	return EC_SUCCESS;
-}
-
-static int mock_set_rx_enable(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_transmit(int port, enum tcpci_msg_type type,
-			 uint16_t header, const uint32_t *data)
-{
-	return EC_SUCCESS;
-}
-
-void mock_tcpc_alert(int port)
-{
-}
-
-void mock_tcpc_discharge_vbus(int port, int enable)
-{
-}
-
-__maybe_unused static int mock_drp_toggle(int port)
-{
-	/* Only set the time the first time this is called. */
-	if (mock_tcpc.first_call_to_enable_auto_toggle == 0)
-		mock_tcpc.first_call_to_enable_auto_toggle = get_time().val;
-
-	if (!mock_tcpc.should_print_call)
-		return EC_SUCCESS;
-
-	ccprints("[TCPC] Enabling Auto Toggle");
-
-	return EC_SUCCESS;
-}
-
-static int mock_get_chip_info(int port, int live,
-			      struct ec_response_pd_chip_info_v1 *info)
-{
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int mock_set_snk_ctrl(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int mock_set_src_ctrl(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int mock_enter_low_power_mode(int port)
-{
-	return EC_SUCCESS;
-}
-
-int mock_set_frs_enable(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-const struct tcpm_drv mock_tcpc_driver = {
-	.init = &mock_init,
-	.release = &mock_release,
-	.get_cc = &mock_get_cc,
-	.check_vbus_level = &mock_check_vbus_level,
-	.select_rp_value = &mock_select_rp_value,
-	.set_cc = &mock_set_cc,
-	.set_polarity = &mock_set_polarity,
-	.set_vconn = &mock_set_vconn,
-	.set_msg_header = &mock_set_msg_header,
-	.set_rx_enable = &mock_set_rx_enable,
-	.get_message_raw = &mock_get_message_raw,
-	.transmit = &mock_transmit,
-	.tcpc_alert = &mock_tcpc_alert,
-	.tcpc_discharge_vbus = &mock_tcpc_discharge_vbus,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle = &mock_drp_toggle,
-#endif
-	.get_chip_info = &mock_get_chip_info,
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl = &mock_set_snk_ctrl,
-	.set_src_ctrl = &mock_set_src_ctrl,
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode = &mock_enter_low_power_mode,
-#endif
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable = &mock_set_frs_enable,
-#endif
-};
diff --git a/common/mock/tcpci_i2c_mock.c b/common/mock/tcpci_i2c_mock.c
deleted file mode 100644
index 8ec7556fca..0000000000
--- a/common/mock/tcpci_i2c_mock.c
+++ /dev/null
@@ -1,1004 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-#define BUFFER_SIZE 100
-#define VERIFY_TIMEOUT (5 * SECOND)
-
-struct tcpci_reg {
-	uint8_t		offset;
-	uint8_t		size;
-	uint16_t	value;
-	const char	*name;
-};
-
-#define TCPCI_REG(reg_name, reg_size)					\
-	[reg_name] = { .offset = (reg_name), .size = (reg_size),	\
-			.value = 0, .name = #reg_name, }
-
-static struct tcpci_reg tcpci_regs[] = {
-	TCPCI_REG(TCPC_REG_VENDOR_ID, 2),
-	TCPCI_REG(TCPC_REG_PRODUCT_ID, 2),
-	TCPCI_REG(TCPC_REG_BCD_DEV, 2),
-	TCPCI_REG(TCPC_REG_TC_REV, 2),
-	TCPCI_REG(TCPC_REG_PD_REV, 2),
-	TCPCI_REG(TCPC_REG_PD_INT_REV, 2),
-	TCPCI_REG(TCPC_REG_ALERT, 2),
-	TCPCI_REG(TCPC_REG_ALERT_MASK, 2),
-	TCPCI_REG(TCPC_REG_POWER_STATUS_MASK, 1),
-	TCPCI_REG(TCPC_REG_FAULT_STATUS_MASK, 1),
-	TCPCI_REG(TCPC_REG_EXT_STATUS_MASK, 1),
-	TCPCI_REG(TCPC_REG_ALERT_EXTENDED_MASK, 1),
-	TCPCI_REG(TCPC_REG_CONFIG_STD_OUTPUT, 1),
-	TCPCI_REG(TCPC_REG_TCPC_CTRL, 1),
-	TCPCI_REG(TCPC_REG_ROLE_CTRL, 1),
-	TCPCI_REG(TCPC_REG_FAULT_CTRL, 1),
-	TCPCI_REG(TCPC_REG_POWER_CTRL, 1),
-	TCPCI_REG(TCPC_REG_CC_STATUS, 1),
-	TCPCI_REG(TCPC_REG_POWER_STATUS, 1),
-	TCPCI_REG(TCPC_REG_FAULT_STATUS, 1),
-	TCPCI_REG(TCPC_REG_EXT_STATUS, 1),
-	TCPCI_REG(TCPC_REG_ALERT_EXT, 1),
-	TCPCI_REG(TCPC_REG_DEV_CAP_1, 2),
-	TCPCI_REG(TCPC_REG_DEV_CAP_2, 2),
-	TCPCI_REG(TCPC_REG_STD_INPUT_CAP, 1),
-	TCPCI_REG(TCPC_REG_STD_OUTPUT_CAP, 1),
-	TCPCI_REG(TCPC_REG_CONFIG_EXT_1, 1),
-	TCPCI_REG(TCPC_REG_MSG_HDR_INFO, 1),
-	TCPCI_REG(TCPC_REG_RX_DETECT, 1),
-	TCPCI_REG(TCPC_REG_RX_BUFFER, BUFFER_SIZE),
-	TCPCI_REG(TCPC_REG_TRANSMIT, 1),
-	TCPCI_REG(TCPC_REG_TX_BUFFER, BUFFER_SIZE),
-	TCPCI_REG(TCPC_REG_VBUS_VOLTAGE, 2),
-	TCPCI_REG(TCPC_REG_VBUS_SINK_DISCONNECT_THRESH, 2),
-	TCPCI_REG(TCPC_REG_VBUS_STOP_DISCHARGE_THRESH, 2),
-	TCPCI_REG(TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 2),
-	TCPCI_REG(TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG, 2),
-	TCPCI_REG(TCPC_REG_COMMAND, 1),
-};
-
-static uint8_t tx_buffer[BUFFER_SIZE];
-static int tx_pos = -1;
-static int tx_msg_cnt;
-static int tx_retry_cnt = -1;
-static uint8_t rx_buffer[BUFFER_SIZE];
-static int rx_pos = -1;
-
-static const char * const ctrl_msg_name[] = {
-	[0]				= "C-RSVD_0",
-	[PD_CTRL_GOOD_CRC]		= "C-GOODCRC",
-	[PD_CTRL_GOTO_MIN]		= "C-GOTOMIN",
-	[PD_CTRL_ACCEPT]		= "C-ACCEPT",
-	[PD_CTRL_REJECT]		= "C-REJECT",
-	[PD_CTRL_PING]			= "C-PING",
-	[PD_CTRL_PS_RDY]		= "C-PSRDY",
-	[PD_CTRL_GET_SOURCE_CAP]	= "C-GET_SRC_CAP",
-	[PD_CTRL_GET_SINK_CAP]		= "C-GET_SNK_CAP",
-	[PD_CTRL_DR_SWAP]		= "C-DR_SWAP",
-	[PD_CTRL_PR_SWAP]		= "C-PR_SWAP",
-	[PD_CTRL_VCONN_SWAP]		= "C-VCONN_SW",
-	[PD_CTRL_WAIT]			= "C-WAIT",
-	[PD_CTRL_SOFT_RESET]		= "C-SOFT-RESET",
-	[14]				= "C-RSVD_14",
-	[15]				= "C-RSVD_15",
-	[PD_CTRL_NOT_SUPPORTED]		= "C-NOT_SUPPORTED",
-	[PD_CTRL_GET_SOURCE_CAP_EXT]	= "C-GET_SRC_CAP-EXT",
-	[PD_CTRL_GET_STATUS]		= "C-GET-STATUS",
-	[PD_CTRL_FR_SWAP]		= "C-FR_SWAP",
-	[PD_CTRL_GET_PPS_STATUS]	= "C-GET_PPS_STATUS",
-	[PD_CTRL_GET_COUNTRY_CODES]	= "C-GET_COUNTRY_CODES",
-};
-
-static const char * const data_msg_name[] = {
-	[0]				= "D-RSVD_0",
-	[PD_DATA_SOURCE_CAP]		= "D-SRC_CAP",
-	[PD_DATA_REQUEST]		= "D-REQUEST",
-	[PD_DATA_BIST]			= "D-BIST",
-	[PD_DATA_SINK_CAP]		= "D-SNK_CAP",
-	/* 5-14 Reserved for REV 2.0 */
-	[PD_DATA_BATTERY_STATUS]	= "D-BATTERY_STATUS",
-	[PD_DATA_ALERT]			= "D-ALERT",
-	[PD_DATA_GET_COUNTRY_INFO]	= "D-GET_COUNTRY_CODES",
-	/* 8-14 Reserved for REV 3.0 */
-	[PD_DATA_ENTER_USB]		= "D-ENTER_USB",
-	[PD_DATA_VENDOR_DEF]		= "D-VDM",
-};
-
-static const char * const ext_msg_name[] = {
-	[0]				= "X-RSVD_0",
-	[PD_EXT_SOURCE_CAP]		= "X-SRC_CAP",
-	[PD_EXT_STATUS]			= "X-STATUS",
-	[PD_EXT_GET_BATTERY_CAP]	= "X-GET_BATTERY_CAP",
-	[PD_EXT_GET_BATTERY_STATUS]	= "X-GET_BATTERY_STATUS",
-	[PD_EXT_BATTERY_CAP]		= "X-BATTERY_CAP",
-	[PD_EXT_GET_MANUFACTURER_INFO]	= "X-GET_MFR_INFO",
-	[PD_EXT_MANUFACTURER_INFO]	= "X-MFR_INFO",
-	[PD_EXT_SECURITY_REQUEST]	= "X-SECURITY_REQ",
-	[PD_EXT_SECURITY_RESPONSE]	= "X-SECURITY_RESP",
-	[PD_EXT_FIRMWARE_UPDATE_REQUEST] = "X-FW_UP_REQ",
-	[PD_EXT_FIRMWARE_UPDATE_RESPONSE] = "X-FW_UP_RESP",
-	[PD_EXT_PPS_STATUS]		= "X-PPS_STATUS",
-	[PD_EXT_COUNTRY_INFO]		= "X-COUNTRY_INFO",
-	[PD_EXT_COUNTRY_CODES]		= "X-COUNTRY_CODES",
-};
-
-static const char * const rev_name[] = {
-	[PD_REV10] = "1.0",
-	[PD_REV20] = "2.0",
-	[PD_REV30] = "3.0",
-	[3] = "RSVD",
-};
-
-static const char * const drole_name[] = {
-	[PD_ROLE_UFP] = "UFP",
-	[PD_ROLE_DFP] = "DFP",
-};
-
-static const char * const prole_name[] = {
-	[PD_ROLE_SINK] = "SNK",
-	[PD_ROLE_SOURCE] = "SRC",
-};
-
-static void print_header(const char *prefix, uint16_t header)
-{
-	int type  = PD_HEADER_TYPE(header);
-	int drole = PD_HEADER_DROLE(header);
-	int rev   = PD_HEADER_REV(header);
-	int prole = PD_HEADER_PROLE(header);
-	int id    = PD_HEADER_ID(header);
-	int cnt   = PD_HEADER_CNT(header);
-	int ext   = PD_HEADER_EXT(header);
-	const char *name = ext	? ext_msg_name[type]
-				: cnt
-					? data_msg_name[type]
-					: ctrl_msg_name[type];
-
-	ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]",
-		 prefix, header,
-		 name, drole_name[drole], rev_name[rev], prole_name[prole],
-		 id, cnt, ext);
-}
-
-static bool dead_battery(void)
-{
-	return false;
-}
-
-static bool debug_accessory_indicator_supported(void)
-{
-	return true;
-}
-
-static int verify_transmit(enum tcpci_msg_type want_tx_type,
-			   int want_tx_retry,
-			   enum pd_ctrl_msg_type want_ctrl_msg,
-			   enum pd_data_msg_type want_data_msg,
-			   int timeout)
-{
-	uint64_t end_time = get_time().val + timeout;
-
-	/*
-	 * Check that nothing was already transmitted. This ensures that all
-	 * transmits are checked, and the test stays in sync with the code
-	 * being tested.
-	 */
-	TEST_EQ(tcpci_regs[TCPC_REG_TRANSMIT].value, 0, "%d");
-
-	/* Now wait for the expected message to be transmitted. */
-	while (get_time().val < end_time) {
-		if (tcpci_regs[TCPC_REG_TRANSMIT].value != 0) {
-			int tx_type = TCPC_REG_TRANSMIT_TYPE(
-				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			int tx_retry = TCPC_REG_TRANSMIT_RETRY(
-				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			uint16_t header = UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1);
-			int pd_type  = PD_HEADER_TYPE(header);
-			int pd_cnt   = PD_HEADER_CNT(header);
-
-			TEST_EQ(tx_type, want_tx_type, "%d");
-			if (want_tx_retry >= 0)
-				TEST_EQ(tx_retry, want_tx_retry, "%d");
-
-			if (want_ctrl_msg != 0) {
-				TEST_EQ(pd_type, want_ctrl_msg, "0x%x");
-				TEST_EQ(pd_cnt, 0, "%d");
-			}
-			if (want_data_msg != 0) {
-				TEST_EQ(pd_type, want_data_msg, "0x%x");
-				TEST_GE(pd_cnt, 1, "%d");
-			}
-
-			tcpci_regs[TCPC_REG_TRANSMIT].value = 0;
-			return EC_SUCCESS;
-		}
-		task_wait_event(5 * MSEC);
-	}
-	TEST_ASSERT(0);
-	return EC_ERROR_UNKNOWN;
-}
-
-int verify_tcpci_transmit(enum tcpci_msg_type tx_type,
-			  enum pd_ctrl_msg_type ctrl_msg,
-			  enum pd_data_msg_type data_msg)
-{
-	return verify_transmit(tx_type, -1,
-			       ctrl_msg, data_msg,
-			       VERIFY_TIMEOUT);
-}
-
-int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
-			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout)
-{
-	return verify_transmit(tx_type, -1,
-			       ctrl_msg, data_msg,
-			       timeout);
-}
-
-int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
-				enum pd_ctrl_msg_type ctrl_msg,
-				enum pd_data_msg_type data_msg,
-				int retry_count)
-{
-	return verify_transmit(tx_type, retry_count,
-			       ctrl_msg, data_msg,
-			       VERIFY_TIMEOUT);
-}
-
-int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
-			      enum pd_data_msg_type data_msg,
-			      uint8_t *data,
-			      int data_bytes,
-			      int *msg_len,
-			      int timeout)
-{
-	int rv;
-
-	if (timeout <= 0)
-		timeout = VERIFY_TIMEOUT;
-
-	rv = verify_transmit(tx_type, -1,
-			     0, data_msg,
-			     timeout);
-	if (!rv) {
-		TEST_NE(data, NULL, "%p");
-		TEST_GE(data_bytes, tx_msg_cnt, "%d");
-		memcpy(data, tx_buffer, tx_msg_cnt);
-		if (msg_len)
-			*msg_len = tx_msg_cnt;
-	}
-	return rv;
-}
-
-int verify_tcpci_possible_tx(struct possible_tx possible[],
-			     int possible_cnt,
-			     int *found_index,
-			     uint8_t *data,
-			     int data_bytes,
-			     int *msg_len,
-			     int timeout)
-{
-	bool assert_on_timeout = true;
-	uint64_t end_time;
-
-	*found_index = -1;
-
-	if (timeout <= 0) {
-		timeout = VERIFY_TIMEOUT;
-		assert_on_timeout = false;
-	}
-	end_time = get_time().val + timeout;
-
-	/*
-	 * Check that nothing was already transmitted. This ensures that all
-	 * transmits are checked, and the test stays in sync with the code
-	 * being tested.
-	 */
-	TEST_EQ(tcpci_regs[TCPC_REG_TRANSMIT].value, 0, "%d");
-
-	/* Now wait for the expected message to be transmitted. */
-	while (get_time().val < end_time) {
-		if (tcpci_regs[TCPC_REG_TRANSMIT].value != 0) {
-			int i;
-			int tx_type = TCPC_REG_TRANSMIT_TYPE(
-				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			uint16_t header = UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1);
-			int pd_type  = PD_HEADER_TYPE(header);
-			int pd_cnt   = PD_HEADER_CNT(header);
-
-			for (i = 0; i < possible_cnt; ++i) {
-				int want_tx_type = possible[i].tx_type;
-				int want_ctrl_msg = possible[i].ctrl_msg;
-				int want_data_msg = possible[i].data_msg;
-
-				if (tx_type != want_tx_type)
-					continue;
-
-				if (want_ctrl_msg != 0) {
-					if (pd_type != want_ctrl_msg ||
-					    pd_cnt != 0)
-						continue;
-				}
-				if (want_data_msg != 0) {
-					if (pd_type != want_data_msg ||
-					    pd_cnt == 0)
-						continue;
-
-					if (data != NULL) {
-						TEST_GE(data_bytes,
-							tx_msg_cnt, "%d");
-						memcpy(data, tx_buffer,
-						       tx_msg_cnt);
-					}
-					if (msg_len != NULL)
-						*msg_len = tx_msg_cnt;
-				}
-				*found_index = i;
-				tcpci_regs[TCPC_REG_TRANSMIT].value = 0;
-				return EC_SUCCESS;
-			}
-			return EC_ERROR_UNKNOWN;
-		}
-		task_wait_event(5 * MSEC);
-	}
-	if (assert_on_timeout)
-		TEST_ASSERT(0);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
-			uint32_t *payload)
-{
-	int i;
-
-	rx_buffer[0] = 3 + (PD_HEADER_CNT(header) * 4);
-	rx_buffer[1] = sop;
-	rx_buffer[2] = header & 0xFF;
-	rx_buffer[3] = (header >> 8) & 0xFF;
-
-	if (rx_buffer[0] >= BUFFER_SIZE) {
-		ccprints("ERROR: rx too large");
-		return;
-	}
-
-	for (i = 4; i < rx_buffer[0]; i += 4) {
-		rx_buffer[i] = *payload & 0xFF;
-		rx_buffer[i+1] = (*payload >> 8) & 0xFF;
-		rx_buffer[i+2] = (*payload >> 16) & 0xFF;
-		rx_buffer[i+3] = (*payload >> 24) & 0xFF;
-		payload++;
-	}
-
-	rx_pos = 0;
-}
-
-/*****************************************************************************
- * TCPCI register reset values
- *
- * These values are from USB Type-C Port Controller Interface Specification
- * Revision 2.0, Version 1.2,
- */
-static void tcpci_reset_register_masks(void)
-{
-	/*
-	 * Using table 4-1 for default mask values
-	 */
-	tcpci_regs[TCPC_REG_ALERT_MASK].value =			0x7FFF;
-	tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value =		0xFF;
-	tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value =		0xFF;
-	tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value =		0x01;
-	tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value =	0x07;
-}
-
-static void tcpci_reset_register_defaults(void)
-{
-	int i;
-
-	/* Default all registers to 0 and then overwrite if they are not */
-	for (i = 0; i < ARRAY_SIZE(tcpci_regs); i++)
-		tcpci_regs[i].value = 0;
-
-	/* Type-C Release 1,3 */
-	tcpci_regs[TCPC_REG_TC_REV].value =			0x0013;
-	/* PD Revision 3.0 Version 1.2 */
-	tcpci_regs[TCPC_REG_PD_REV].value =			0x3012;
-	/* PD Interface Revision 2.0, Version 1.1 */
-	tcpci_regs[TCPC_REG_PD_INT_REV].value =			0x2011;
-
-	tcpci_reset_register_masks();
-
-	tcpci_regs[TCPC_REG_CONFIG_STD_OUTPUT].value =
-			TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
-			TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
-
-	tcpci_regs[TCPC_REG_POWER_CTRL].value =
-			TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS |
-			TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS;
-
-	tcpci_regs[TCPC_REG_FAULT_STATUS].value =
-			TCPC_REG_FAULT_STATUS_ALL_REGS_RESET;
-
-	tcpci_regs[TCPC_REG_DEV_CAP_1].value =
-			TCPC_REG_DEV_CAP_1_SOURCE_VBUS |
-			TCPC_REG_DEV_CAP_1_SINK_VBUS |
-			TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP |
-			TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF;
-
-	/*
-	 * Using table 4-17 to get the default Role Control and
-	 * Message Header Info register values.
-	 */
-	switch (mock_tcpci_get_reg(TCPC_REG_DEV_CAP_1) &
-			TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK:
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK:
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC:
-		tcpci_regs[TCPC_REG_ROLE_CTRL].value =		0x0A;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
-		break;
-
-	case TCPC_REG_DEV_CAP_1_PWRROLE_DRP:
-		if (dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0A;
-		else if (debug_accessory_indicator_supported())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x4A;
-		else
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0F;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
-		break;
-
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC:
-		if (!dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x05;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x0D;
-		break;
-
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL:
-	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP:
-		if (dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0A;
-		else if (debug_accessory_indicator_supported())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x4A;
-		else
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0F;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
-		break;
-	}
-}
-/*****************************************************************************/
-
-void mock_tcpci_reset(void)
-{
-	tcpci_reset_register_defaults();
-}
-
-void mock_tcpci_set_reg(int reg_offset, uint16_t value)
-{
-	struct tcpci_reg *reg = tcpci_regs + reg_offset;
-
-	reg->value = value;
-	ccprints("TCPCI mock set %s = 0x%x",  reg->name, reg->value);
-}
-
-void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask)
-{
-	struct tcpci_reg *reg = tcpci_regs + reg_offset;
-	uint16_t old_value = reg->value;
-
-	reg->value |= mask;
-	ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x",
-		 reg->name, mask, old_value, reg->value);
-}
-
-void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask)
-{
-	struct tcpci_reg *reg = tcpci_regs + reg_offset;
-	uint16_t old_value = reg->value;
-
-	reg->value &= ~mask;
-	ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x",
-		 reg->name, mask, old_value, reg->value);
-}
-
-uint16_t mock_tcpci_get_reg(int reg_offset)
-{
-	return tcpci_regs[reg_offset].value;
-}
-
-int tcpci_i2c_xfer(int port, uint16_t addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
-{
-	struct tcpci_reg *reg;
-
-	if (port != I2C_PORT_HOST_TCPC) {
-		ccprints("ERROR: wrong I2C port %d", port);
-		return EC_ERROR_UNKNOWN;
-	}
-	if (addr_flags != MOCK_TCPCI_I2C_ADDR_FLAGS) {
-		ccprints("ERROR: wrong I2C address 0x%x", addr_flags);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (rx_pos > 0) {
-		if (rx_pos + in_size > rx_buffer[0] + 1) {
-			ccprints("ERROR: rx in_size");
-			return EC_ERROR_UNKNOWN;
-		}
-		memcpy(in, rx_buffer + rx_pos, in_size);
-		rx_pos	+= in_size;
-		if (rx_pos == rx_buffer[0] + 1) {
-			print_header("RX", UINT16_FROM_BYTE_ARRAY_LE(
-						rx_buffer, 2));
-			rx_pos = -1;
-		}
-		return EC_SUCCESS;
-	}
-
-	if (out_size == 0) {
-		ccprints("ERROR: out_size == 0");
-		return EC_ERROR_UNKNOWN;
-	}
-	if (tx_pos != -1) {
-		if (tx_pos + out_size > BUFFER_SIZE) {
-			ccprints("ERROR: tx out_size");
-			return EC_ERROR_UNKNOWN;
-		}
-		memcpy(tx_buffer + tx_pos, out, out_size);
-		tx_pos += out_size;
-		tx_msg_cnt = tx_pos;
-		if (tx_pos > 0 && tx_pos == tx_buffer[0] + 1) {
-			print_header("TX", UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1));
-			tx_pos = -1;
-			tx_retry_cnt = -1;
-		}
-		return EC_SUCCESS;
-	}
-	reg = tcpci_regs + *out;
-	if (*out >= ARRAY_SIZE(tcpci_regs) || reg->size == 0) {
-		ccprints("ERROR: unknown reg 0x%x", *out);
-		return EC_ERROR_UNKNOWN;
-	}
-	if (reg->offset == TCPC_REG_TX_BUFFER) {
-		if (tx_pos != -1) {
-			ccprints("ERROR: TCPC_REG_TX_BUFFER not ready");
-			return EC_ERROR_UNKNOWN;
-		}
-		tx_pos = 0;
-		tx_msg_cnt = 0;
-		if (out_size != 1) {
-			ccprints("ERROR: TCPC_REG_TX_BUFFER out_size != 1");
-			return EC_ERROR_UNKNOWN;
-		}
-	} else if (reg->offset == TCPC_REG_RX_BUFFER) {
-		if (rx_pos != 0) {
-			ccprints("ERROR: TCPC_REG_RX_BUFFER not ready");
-			return EC_ERROR_UNKNOWN;
-		}
-		if (in_size > BUFFER_SIZE || in_size > rx_buffer[0]) {
-			ccprints("ERROR: TCPC_REG_RX_BUFFER in_size");
-			return EC_ERROR_UNKNOWN;
-		}
-		memcpy(in, rx_buffer, in_size);
-		rx_pos += in_size;
-	} else if (out_size == 1) {
-		if (in_size != reg->size) {
-			ccprints("ERROR: %s in_size %d != %d", reg->name,
-				 in_size, reg->size);
-			return EC_ERROR_UNKNOWN;
-		}
-		if (reg->size == 1)
-			in[0] = reg->value;
-		else if (reg->size == 2) {
-			in[0] = reg->value;
-			in[1] = reg->value >> 8;
-		}
-	} else {
-		uint16_t value = 0;
-
-		if (in_size != 0) {
-			ccprints("ERROR: in_size != 0");
-			return EC_ERROR_UNKNOWN;
-		}
-		if (out_size != reg->size + 1) {
-			ccprints("ERROR: out_size != %d", reg->size + 1);
-			return EC_ERROR_UNKNOWN;
-		}
-		if (reg->size == 1)
-			value = out[1];
-		else if (reg->size == 2)
-			value = out[1] + (out[2] << 8);
-		ccprints("%s TCPCI write %s = 0x%x",
-			 task_get_name(task_get_current()),
-			 reg->name, value);
-		if (reg->offset == TCPC_REG_ALERT)
-			reg->value &= ~value;
-		else
-			reg->value = value;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_TEST_I2C_XFER(tcpci_i2c_xfer);
-
-void tcpci_register_dump(void)
-{
-	int reg;
-	int cc1, cc2;
-
-	ccprints("********* TCPCI Register Dump ***********");
-	reg = mock_tcpci_get_reg(TCPC_REG_ALERT);
-	ccprints("TCPC_REG_ALERT        = 0x%08X", reg);
-	if (reg) {
-		if (reg & BIT(0))
-			ccprints("\t0001: CC Status");
-		if (reg & BIT(1))
-			ccprints("\t0002: Power Status");
-		if (reg & BIT(2))
-			ccprints("\t0004: Received SOP* Message Status");
-		if (reg & BIT(3))
-			ccprints("\t0008: Received Hard Reset");
-		if (reg & BIT(4))
-			ccprints("\t0010: Transmit SOP* Message Failed");
-		if (reg & BIT(5))
-			ccprints("\t0020: Transmit SOP* Message Discarded");
-		if (reg & BIT(6))
-			ccprints("\t0040: Transmit SOP* Message Successful");
-		if (reg & BIT(7))
-			ccprints("\t0080: Vbus Voltage Alarm Hi");
-		if (reg & BIT(8))
-			ccprints("\t0100: Vbus Voltage Alarm Lo");
-		if (reg & BIT(9))
-			ccprints("\t0200: Fault");
-		if (reg & BIT(10))
-			ccprints("\t0400: Rx Buffer Overflow");
-		if (reg & BIT(11))
-			ccprints("\t0800: Vbus Sink Disconnect Detected");
-		if (reg & BIT(12))
-			ccprints("\t1000: Beginning SOP* Message Status");
-		if (reg & BIT(13))
-			ccprints("\t2000: Extended Status");
-		if (reg & BIT(14))
-			ccprints("\t4000: Alert Extended");
-		if (reg & BIT(15))
-			ccprints("\t8000: Vendor Defined Alert");
-	}
-
-	reg = mock_tcpci_get_reg(TCPC_REG_TCPC_CTRL);
-	ccprints("TCPC_REG_TCPC_CTRL    = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Plug Orientation FLIP");
-	if (reg & BIT(1))
-		ccprints("\t02: BIST Test Mode");
-	if (reg & (BIT(2) | BIT(3))) {
-		switch ((reg >> 2) & 3) {
-		case 2:
-			ccprints("\t08: Enable Clock Stretching");
-			break;
-		case 3:
-			ccprints("\t0C: Enable Clock Stretching if !Alert");
-			break;
-		}
-	}
-	if (reg & BIT(4))
-		ccprints("\t10: Debug Accessory controlled by TCPM");
-	if (reg & BIT(5))
-		ccprints("\t20: Watchdog Timer enabled");
-	if (reg & BIT(6))
-		ccprints("\t40: Looking4Connection Alert enabled");
-	if (reg & BIT(7))
-		ccprints("\t80: SMBus PEC enabled");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL);
-	ccprints("TCPC_REG_ROLE_CTRL    = 0x%04X", reg);
-	cc1 = (reg >> 0) & 3;
-	switch (cc1) {
-	case 0:
-		ccprints("\t00: CC1 == Ra");
-		break;
-	case 1:
-		ccprints("\t01: CC1 == Rp");
-		break;
-	case 2:
-		ccprints("\t02: CC1 == Rd");
-		break;
-	case 3:
-		ccprints("\t03: CC1 == OPEN");
-		break;
-	}
-	cc2 = (reg >> 2) & 3;
-	switch (cc2) {
-	case 0:
-		ccprints("\t00: CC2 == Ra");
-		break;
-	case 1:
-		ccprints("\t04: CC2 == Rp");
-		break;
-	case 2:
-		ccprints("\t08: CC2 == Rd");
-		break;
-	case 3:
-		ccprints("\t0C: CC2 == OPEN");
-		break;
-	}
-	switch ((reg >> 4) & 3) {
-	case 0:
-		ccprints("\t00: Rp Value == default");
-		break;
-	case 1:
-		ccprints("\t10: Rp Value == 1.5A");
-		break;
-	case 2:
-		ccprints("\t20: Rp Value == 3A");
-		break;
-	}
-	if (reg & BIT(6))
-		ccprints("\t40: DRP");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_FAULT_CTRL);
-	ccprints("TCPC_REG_FAULT_CTRL   = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Vconn Over Current Fault");
-	if (reg & BIT(1))
-		ccprints("\t02: Vbus OVP Fault");
-	if (reg & BIT(2))
-		ccprints("\t04: Vbus OCP Fault");
-	if (reg & BIT(3))
-		ccprints("\t08: Vbus Discharge Fault");
-	if (reg & BIT(4))
-		ccprints("\t10: Force OFF Vbus");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_POWER_CTRL);
-	ccprints("TCPC_REG_POWER_CTRL   = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Enable Vconn");
-	if (reg & BIT(1))
-		ccprints("\t02: Vconn Power Supported");
-	if (reg & BIT(2))
-		ccprints("\t04: Force Discharge");
-	if (reg & BIT(3))
-		ccprints("\t08: Enable Bleed Discharge");
-	if (reg & BIT(4))
-		ccprints("\t10: Auto Discharge Disconnect");
-	if (reg & BIT(5))
-		ccprints("\t20: Disable Voltage Alarms");
-	if (reg & BIT(6))
-		ccprints("\t40: VBUS_VOLTAGE monitor disabled");
-	if (reg & BIT(7))
-		ccprints("\t80: Fast Role Swap enabled");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_CC_STATUS);
-	ccprints("TCPC_REG_CC_STATUS    = 0x%04X", reg);
-	switch ((reg >> 0) & 3) {
-	case 0:
-		switch (cc1) {
-		case 1:
-			ccprints("\t00: CC1-Rp SRC.Open");
-			break;
-		case 2:
-			ccprints("\t00: CC1-Rd SNK.Open");
-			break;
-		}
-		break;
-	case 1:
-		switch (cc1) {
-		case 1:
-			ccprints("\t01: CC1-Rp SRC.Ra");
-			break;
-		case 2:
-			ccprints("\t01: CC1-Rd SNK.Default");
-			break;
-		}
-		break;
-	case 2:
-		switch (cc1) {
-		case 1:
-			ccprints("\t02: CC1-Rp SRC.Rd");
-			break;
-		case 2:
-			ccprints("\t02: CC1-Rd SNK.Power1.5");
-			break;
-		}
-		break;
-	case 3:
-		switch (cc1) {
-		case 2:
-			ccprints("\t03: CC1-Rd SNK.Power3.0");
-			break;
-		}
-		break;
-	}
-	switch ((reg >> 2) & 3) {
-	case 0:
-		switch (cc2) {
-		case 1:
-			ccprints("\t00: CC2-Rp SRC.Open");
-			break;
-		case 2:
-			ccprints("\t00: CC2-Rd SNK.Open");
-			break;
-		}
-		break;
-	case 1:
-		switch (cc2) {
-		case 1:
-			ccprints("\t04: CC2-Rp SRC.Ra");
-			break;
-		case 2:
-			ccprints("\t04: CC2-Rd SNK.Default");
-			break;
-		}
-		break;
-	case 2:
-		switch (cc2) {
-		case 1:
-			ccprints("\t08: CC2-Rp SRC.Rd");
-			break;
-		case 2:
-			ccprints("\t08: CC2-Rd SNK.Power1.5");
-			break;
-		}
-		break;
-	case 3:
-		switch (cc2) {
-		case 2:
-			ccprints("\t0C: CC2-Rd SNK.Power3.0");
-			break;
-		}
-		break;
-	}
-	if (reg & BIT(4))
-		ccprints("\t10: Presenting Rd");
-	else
-		ccprints("\t00: Presenting Rp");
-	if (reg & BIT(5))
-		ccprints("\t20: Looking4Connection");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_POWER_STATUS);
-	ccprints("TCPC_REG_POWER_STATUS = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Sinking Vbus");
-	if (reg & BIT(1))
-		ccprints("\t02: Vconn Present");
-	if (reg & BIT(2))
-		ccprints("\t04: Vbus Present");
-	if (reg & BIT(3))
-		ccprints("\t08: Vbus Detect enabled");
-	if (reg & BIT(4))
-		ccprints("\t10: Sourcing Vbus");
-	if (reg & BIT(5))
-		ccprints("\t20: Sourcing non-default voltage");
-	if (reg & BIT(6))
-		ccprints("\t40: TCPC Initialization");
-	if (reg & BIT(7))
-		ccprints("\t80: Debug Accessory Connected");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_FAULT_STATUS);
-	ccprints("TCPC_REG_FAULT_STATUS = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: I2C Interface Error");
-	if (reg & BIT(1))
-		ccprints("\t02: Vconn Over Current Fault");
-	if (reg & BIT(2))
-		ccprints("\t04: Vbus OVP Fault");
-	if (reg & BIT(3))
-		ccprints("\t08: Vbus OCP Fault");
-	if (reg & BIT(4))
-		ccprints("\t10: Forced Discharge Failed");
-	if (reg & BIT(5))
-		ccprints("\t20: Auto Discharge Failed");
-	if (reg & BIT(6))
-		ccprints("\t40: Force OFF Vbus");
-	if (reg & BIT(7))
-		ccprints("\t80: TCPCI Registers Reset2Default");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_EXT_STATUS);
-	ccprints("TCPC_REG_EXT_STATUS   = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Vbus is at vSafe0V");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_ALERT_EXT);
-	ccprints("TCPC_REG_ALERT_EXT    = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: SNK Fast Role Swap");
-	if (reg & BIT(1))
-		ccprints("\t02: SRC Fast Role Swap");
-	if (reg & BIT(2))
-		ccprints("\t04: Timer Expired");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_COMMAND);
-	ccprints("TCPC_REG_COMMAND      = 0x%04X", reg);
-	switch (reg) {
-	case 0x11:
-		ccprints("\t11: WakeI2C");
-		break;
-	case 0x22:
-		ccprints("\t22: DisableVbusDetect");
-		break;
-	case 0x33:
-		ccprints("\t33: EnableVbusDetect");
-		break;
-	case 0x44:
-		ccprints("\t44: DisableSinkVbus");
-		break;
-	case 0x55:
-		ccprints("\t55: SinkVbus");
-		break;
-	case 0x66:
-		ccprints("\t66: DisableSourceVbus");
-		break;
-	case 0x77:
-		ccprints("\t77: SourceVbusDefaultVoltage");
-		break;
-	case 0x88:
-		ccprints("\t88: SourceVbusNondefaultVoltage");
-		break;
-	case 0x99:
-		ccprints("\t99: Looking4Connection");
-		break;
-	case 0xAA:
-		ccprints("\tAA: RxOneMore");
-		break;
-	case 0xCC:
-		ccprints("\tCC: SendFRSwapSignal");
-		break;
-	case 0xDD:
-		ccprints("\tDD: ResetTransmitBuffer");
-		break;
-	case 0xEE:
-		ccprints("\tEE: ResetReceiveBuffer");
-		break;
-	case 0xFF:
-		ccprints("\tFF: I2C Idle");
-		break;
-	}
-
-	reg = mock_tcpci_get_reg(TCPC_REG_MSG_HDR_INFO);
-	ccprints("TCPC_REG_MSG_HDR_INFO = 0x%04X", reg);
-	if (reg & BIT(0))
-		ccprints("\t01: Power Role SRC");
-	else
-		ccprints("\t00: Power Role SNK");
-	switch ((reg >> 1) & 3) {
-	case 0:
-		ccprints("\t00: PD Revision 1.0");
-		break;
-	case 1:
-		ccprints("\t02: PD Revision 2.0");
-		break;
-	case 2:
-		ccprints("\t04: PD Revision 3.0");
-		break;
-	}
-	if (reg & BIT(3))
-		ccprints("\t08: Data Role DFP");
-	else
-		ccprints("\t00: Data Role UFP");
-	if (reg & BIT(4))
-		ccprints("\t10: Message originating from Cable Plug");
-	else
-		ccprints("\t00: Message originating from SRC/SNK/DRP");
-
-	reg = mock_tcpci_get_reg(TCPC_REG_RX_BUFFER);
-	ccprints("TCPC_REG_RX_BUFFER    = 0x%04X", reg);
-
-	reg = mock_tcpci_get_reg(TCPC_REG_TRANSMIT);
-	ccprints("TCPC_REG_TRANSMIT     = 0x%04X", reg);
-	ccprints("*****************************************");
-}
diff --git a/common/mock/tcpm_mock.c b/common/mock/tcpm_mock.c
deleted file mode 100644
index 2c212cf8c9..0000000000
--- a/common/mock/tcpm_mock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock for the TCPM interface */
-
-#include "common.h"
-#include "console.h"
-#include "memory.h"
-#include "mock/tcpm_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_tcpm_t mock_tcpm[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/**
- * Gets the next waiting RX message.
- *
- * @param port Type-C port number
- * @param payload Pointer to location to copy payload of PD message
- * @param header The header of PD message
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_dequeue_message(int port, uint32_t *payload, int *header)
-{
-	if (!tcpm_has_pending_message(port))
-		return EC_ERROR_BUSY;
-
-	*header = mock_tcpm[port].mock_header;
-	memcpy(payload, mock_tcpm[port].mock_rx_chk_buf,
-		sizeof(mock_tcpm[port].mock_rx_chk_buf));
-
-	return EC_SUCCESS;
-}
-
-/**
- * Returns true if the tcpm has RX messages waiting to be consumed.
- */
-int tcpm_has_pending_message(int port)
-{
-	return mock_tcpm[port].mock_has_pending_message;
-}
-
-/**
- * Resets all mock TCPM ports
- */
-void mock_tcpm_reset(void)
-{
-	int port;
-
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port)
-		mock_tcpm[port].mock_has_pending_message = 0;
-}
-
-/**
- * Sets up a message to be received, with optional data payload. If cnt==0,
- * then data can be NULL.
- */
-void mock_tcpm_rx_msg(int port, uint16_t header, int cnt, const uint32_t *data)
-{
-	mock_tcpm[port].mock_header = header;
-	if (cnt > 0) {
-		int idx;
-
-		for (idx = 0 ; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE) ; ++idx)
-			mock_tcpm[port].mock_rx_chk_buf[idx] = data[idx];
-	}
-	mock_tcpm[port].mock_has_pending_message = 1;
-}
diff --git a/common/mock/timer_mock.c b/common/mock/timer_mock.c
deleted file mode 100644
index dc83aa24d5..0000000000
--- a/common/mock/timer_mock.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/timer_mock.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-static timestamp_t now;
-
-void set_time(timestamp_t now_)
-{
-	now = now_;
-}
-
-timestamp_t get_time(void)
-{
-	return now;
-};
diff --git a/common/mock/usb_mux_mock.c b/common/mock/usb_mux_mock.c
deleted file mode 100644
index f2db5cf8bd..0000000000
--- a/common/mock/usb_mux_mock.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock USB Type-C mux */
-
-#include "common.h"
-#include "console.h"
-#include "usb_mux.h"
-#include "mock/usb_mux_mock.h"
-#include "memory.h"
-
-#ifndef CONFIG_COMMON_RUNTIME
-#define cprints(format, args...)
-#endif
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-/* Public API for controlling/inspecting this mock */
-struct mock_usb_mux_ctrl mock_usb_mux;
-
-void mock_usb_mux_reset(void)
-{
-	memset(&mock_usb_mux, 0, sizeof(mock_usb_mux));
-}
-
-static int mock_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_set(const struct usb_mux *me, mux_state_t mux_state,
-		    bool *ack_required)
-{
-	/* Mock does not use host command ACKs */
-	*ack_required = false;
-
-	mock_usb_mux.state = mux_state;
-	++mock_usb_mux.num_set_calls;
-	ccprints("[MUX] Set to 0x%02x", mux_state);
-
-	return EC_SUCCESS;
-}
-
-int mock_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	*mux_state = mock_usb_mux.state;
-	return EC_SUCCESS;
-}
-
-static int mock_enter_low_power_mode(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver mock_usb_mux_driver = {
-	.init = &mock_init,
-	.set = &mock_set,
-	.get = &mock_get,
-	.enter_low_power_mode = &mock_enter_low_power_mode,
-};
diff --git a/common/mock/usb_pd_dpm_mock.c b/common/mock/usb_pd_dpm_mock.c
deleted file mode 100644
index 8b6fbaa30e..0000000000
--- a/common/mock/usb_pd_dpm_mock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Mock of Device Policy Manager implementation
- * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
- */
-
-#include "usb_pd.h"
-#include "mock/usb_pd_dpm_mock.h"
-#include "memory.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_dpm_port_t dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_dpm_reset(void)
-{
-	/* Reset all values to 0. */
-	memset(dpm, 0, sizeof(dpm));
-}
-
-void dpm_init(int port)
-{
-	dpm[port].mode_entry_done = false;
-	dpm[port].mode_exit_request = false;
-}
-
-void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
-{
-}
-
-void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
-{
-}
-
-void dpm_set_mode_exit_request(int port)
-{
-}
-
-void dpm_run(int port)
-{
-}
-
-void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
-{
-}
-
-void dpm_add_non_pd_sink(int port)
-{
-}
-
-void dpm_remove_sink(int port)
-{
-}
-
-void dpm_remove_source(int port)
-{
-}
-
-int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnt;
-}
diff --git a/common/mock/usb_pe_sm_mock.c b/common/mock/usb_pe_sm_mock.c
deleted file mode 100644
index 8d1a25324b..0000000000
--- a/common/mock/usb_pe_sm_mock.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mock USB PE state machine */
-
-#include "common.h"
-#include "console.h"
-#include "usb_pd.h"
-#include "usb_pe_sm.h"
-#include "mock/usb_pe_sm_mock.h"
-#include "memory.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef CONFIG_COMMON_RUNTIME
-#define cprints(format, args...)
-#endif
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_pe_port_t mock_pe_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-
-/**
- * Resets all mock PE ports to initial values
- */
-void mock_pe_port_reset(void)
-{
-	int port;
-
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
-		mock_pe_port[port].mock_pe_error = -1;
-		/* These mock variable only get set to 1 by various functions,
-		 * so initialize them to 0. Tests can verify they are still 0
-		 * if that's part of the pass criteria.
-		 */
-		mock_pe_port[port].mock_pe_message_received = 0;
-		mock_pe_port[port].mock_pe_message_sent = 0;
-		mock_pe_port[port].mock_pe_message_discarded = 0;
-		mock_pe_port[port].mock_got_soft_reset = 0;
-		mock_pe_port[port].mock_pe_got_hard_reset = 0;
-		mock_pe_port[port].mock_pe_hard_reset_sent = 0;
-	}
-}
-
-void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
-{
-	mock_pe_port[port].mock_pe_error = e;
-	mock_pe_port[port].sop = type;
-}
-
-void pe_report_discard(int port)
-{
-	mock_pe_port[port].mock_pe_message_discarded = 1;
-}
-
-void pe_got_hard_reset(int port)
-{
-	mock_pe_port[port].mock_pe_got_hard_reset = 1;
-}
-
-void pe_message_received(int port)
-{
-	mock_pe_port[port].mock_pe_message_received = 1;
-}
-
-void pe_message_sent(int port)
-{
-	mock_pe_port[port].mock_pe_message_sent = 1;
-}
-
-void pe_hard_reset_sent(int port)
-{
-	mock_pe_port[port].mock_pe_hard_reset_sent = 1;
-}
-
-void pe_got_soft_reset(int port)
-{
-	mock_pe_port[port].mock_got_soft_reset = 1;
-}
-
-bool pe_in_frs_mode(int port)
-{
-	return false;
-}
-
-bool pe_in_local_ams(int port)
-{
-	/* We will probably want to change this in the future */
-	return false;
-}
-
-const uint32_t * const pd_get_src_caps(int port)
-{
-	return NULL;
-}
-
-uint8_t pd_get_src_cap_cnt(int port)
-{
-	return 0;
-}
-
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-}
-
-void pd_request_power_swap(int port)
-{}
-
-int pd_get_rev(int port, enum tcpci_msg_type type)
-{
-	return IS_ENABLED(CONFIG_USB_PD_REV30) ? PD_REV30 : PD_REV20;
-}
-
-void pe_invalidate_explicit_contract(int port)
-{
-}
diff --git a/common/mock/usb_prl_mock.c b/common/mock/usb_prl_mock.c
deleted file mode 100644
index d5f4781829..0000000000
--- a/common/mock/usb_prl_mock.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Mock Protocol Layer module.
- */
-#include <string.h>
-#include "common.h"
-#include "usb_emsg.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "mock/usb_prl_mock.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-/* Defaults should all be 0 values. */
-struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-struct mock_prl_port_t {
-	enum pd_ctrl_msg_type last_ctrl_msg;
-	enum pd_data_msg_type last_data_msg;
-	enum tcpci_msg_type last_tx_type;
-	bool message_sent;
-	bool message_received;
-	enum pe_error error;
-	enum tcpci_msg_type error_tx_type;
-};
-
-struct mock_prl_port_t mock_prl_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_prl_reset(void)
-{
-	int port;
-
-	/* Reset all values to 0. */
-	memset(rx_emsg, 0, sizeof(rx_emsg));
-	memset(tx_emsg, 0, sizeof(tx_emsg));
-
-	memset(mock_prl_port, 0, sizeof(mock_prl_port));
-
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
-		mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID;
-		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
-	}
-}
-
-void prl_end_ams(int port)
-{}
-
-void prl_execute_hard_reset(int port)
-{
-	mock_prl_port[port].last_ctrl_msg = 0;
-	mock_prl_port[port].last_data_msg = 0;
-	mock_prl_port[port].last_tx_type = TCPCI_MSG_TX_HARD_RESET;
-}
-
-enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type partner)
-{
-	return PD_REV30;
-}
-
-void prl_hard_reset_complete(int port)
-{}
-
-int prl_is_running(int port)
-{
-	return 1;
-}
-
-__overridable bool prl_is_busy(int port)
-{
-	return false;
-}
-
-void prl_reset_soft(int port)
-{}
-
-void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
-	enum pd_ctrl_msg_type msg)
-{
-	mock_prl_port[port].last_ctrl_msg = msg;
-	mock_prl_port[port].last_data_msg = 0;
-	mock_prl_port[port].last_tx_type = type;
-}
-
-void prl_send_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_data_msg_type msg)
-{
-	mock_prl_port[port].last_data_msg = msg;
-	mock_prl_port[port].last_ctrl_msg = 0;
-	mock_prl_port[port].last_tx_type = type;
-}
-
-void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_ext_msg_type msg)
-{}
-
-void prl_set_rev(int port, enum tcpci_msg_type partner,
-	enum pd_rev_type rev)
-{}
-
-
-int mock_prl_wait_for_tx_msg(int port,
-			     enum tcpci_msg_type tx_type,
-			     enum pd_ctrl_msg_type ctrl_msg,
-			     enum pd_data_msg_type data_msg,
-			     int timeout)
-{
-	uint64_t end_time = get_time().val + timeout;
-
-	while (get_time().val < end_time) {
-		if (mock_prl_port[port].last_tx_type != TCPCI_MSG_INVALID) {
-			TEST_EQ(mock_prl_port[port].last_tx_type,
-				tx_type, "%d");
-			TEST_EQ(mock_prl_port[port].last_ctrl_msg,
-				ctrl_msg, "%d");
-			TEST_EQ(mock_prl_port[port].last_data_msg,
-				data_msg, "%d");
-			mock_prl_clear_last_sent_msg(port);
-			return EC_SUCCESS;
-		}
-		task_wait_event(5 * MSEC);
-	}
-	/* A message of the expected type should have been sent by end_time. */
-	TEST_ASSERT(0);
-	return EC_ERROR_UNKNOWN;
-}
-
-enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port)
-{
-	enum pd_ctrl_msg_type last = mock_prl_port[port].last_ctrl_msg;
-
-	mock_prl_clear_last_sent_msg(port);
-	return last;
-}
-
-enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port)
-{
-	enum pd_data_msg_type last = mock_prl_port[port].last_data_msg;
-
-	mock_prl_clear_last_sent_msg(port);
-	return last;
-}
-
-void mock_prl_clear_last_sent_msg(int port)
-{
-	mock_prl_port[port].last_data_msg = 0;
-	mock_prl_port[port].last_ctrl_msg = 0;
-	mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID;
-}
-
-timestamp_t prl_get_tcpc_tx_success_ts(int port)
-{
-	return get_time();
-}
-void mock_prl_message_sent(int port)
-{
-	mock_prl_port[port].message_sent = 1;
-}
-
-void mock_prl_message_received(int port)
-{
-	mock_prl_port[port].message_received = 1;
-}
-
-void mock_prl_report_error(int port, enum pe_error e,
-			   enum tcpci_msg_type tx_type)
-{
-	mock_prl_port[port].error = e;
-	mock_prl_port[port].error_tx_type = tx_type;
-}
-
-void prl_run(int port, int evt, int en)
-{
-	if (mock_prl_port[port].message_sent) {
-		ccprints("message_sent");
-		pe_message_sent(port);
-		mock_prl_port[port].message_sent = 0;
-	}
-	if (mock_prl_port[port].message_received) {
-		ccprints("message_received");
-		pe_message_received(port);
-		mock_prl_port[port].message_received = 0;
-	}
-	if (mock_prl_port[port].error_tx_type != TCPCI_MSG_INVALID) {
-		ccprints("pe_error %d", mock_prl_port[port].error);
-		pe_report_error(port,
-				mock_prl_port[port].error,
-				mock_prl_port[port].error_tx_type);
-		mock_prl_port[port].error = 0;
-		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
-	}
-}
diff --git a/common/mock/usb_tc_sm_mock.c b/common/mock/usb_tc_sm_mock.c
deleted file mode 100644
index d55def12e2..0000000000
--- a/common/mock/usb_tc_sm_mock.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Mock USB TC state machine */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "usb_tc_sm.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "memory.h"
-
-#ifndef CONFIG_COMMON_RUNTIME
-#define cprints(format, args...)
-#endif
-
-#ifndef TEST_BUILD
-#error "Mocks should only be in the test build."
-#endif
-
-struct mock_tc_port_t mock_tc_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_tc_port_reset(void)
-{
-	int port;
-
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
-		mock_tc_port[port].rev = PD_REV30;
-		mock_tc_port[port].pd_enable = 0;
-		mock_tc_port[port].msg_tx_id = 0;
-		mock_tc_port[port].msg_rx_id = 0;
-		mock_tc_port[port].sop = TCPCI_MSG_INVALID;
-		mock_tc_port[port].lcl_rp = TYPEC_RP_RESERVED;
-		mock_tc_port[port].attached_snk = 0;
-		mock_tc_port[port].attached_src = 0;
-		mock_tc_port[port].vconn_src = false;
-		mock_tc_port[port].data_role = PD_ROLE_UFP;
-		mock_tc_port[port].power_role = PD_ROLE_SINK;
-	}
-}
-
-enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	return PD_PLUG_FROM_DFP_UFP;
-}
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return mock_tc_port[port].pd_enable;
-}
-
-void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
-{
-	mock_tc_port[port].lcl_rp = rp;
-}
-
-void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
-{
-}
-
-int tc_is_attached_src(int port)
-{
-	return mock_tc_port[port].attached_src;
-}
-
-int tc_is_attached_snk(int port)
-{
-	return mock_tc_port[port].attached_snk;
-}
-
-void tc_prs_snk_src_assert_rp(int port)
-{
-	mock_tc_port[port].attached_snk = 0;
-	mock_tc_port[port].attached_src = 1;
-}
-
-void tc_prs_src_snk_assert_rd(int port)
-{
-	mock_tc_port[port].attached_snk = 1;
-	mock_tc_port[port].attached_src = 0;
-}
-
-int typec_update_cc(int port)
-{
-	return EC_SUCCESS;
-}
-
-int tc_check_vconn_swap(int port)
-{
-	return 0;
-}
-
-void tc_ctvpd_detected(int port)
-{}
-
-int tc_is_vconn_src(int port)
-{
-	return mock_tc_port[port].vconn_src;
-}
-
-void tc_hard_reset_request(int port)
-{
-	mock_tc_port_reset();
-}
-
-void tc_partner_dr_data(int port, int en)
-{}
-
-void tc_partner_dr_power(int port, int en)
-{}
-
-void tc_partner_unconstrainedpower(int port, int en)
-{}
-
-void tc_partner_usb_comm(int port, int en)
-{}
-
-void tc_pd_connection(int port, int en)
-{}
-
-void tc_pr_swap_complete(int port, bool success)
-{}
-
-void tc_src_power_off(int port)
-{}
-
-void tc_start_error_recovery(int port)
-{}
-
-void tc_snk_power_off(int port)
-{}
-
-void tc_request_power_swap(int port)
-{
-}
-
-enum pd_dual_role_states pd_get_dual_role(int port)
-{
-	return PD_DRP_TOGGLE_ON;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	return mock_tc_port[port].data_role;
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return mock_tc_port[port].power_role;
-}
-
-enum pd_cc_states pd_get_task_cc_state(int port)
-{
-	return PD_CC_NONE;
-}
-
-int pd_is_connected(int port)
-{
-	return 1;
-}
-
-bool pd_is_disconnected(int port)
-{
-	return false;
-}
-
-bool pd_get_partner_usb_comm_capable(int port)
-{
-	return true;
-}
-
-bool pd_get_partner_dual_role_power(int port)
-{
-	return true;
-}
-
-bool pd_capable(int port)
-{
-	return true;
-}
-
-bool pd_waiting_on_partner_src_caps(int port)
-{
-	return false;
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-}
-
-void pd_set_error_recovery(int port)
-{
-}
-
-enum tcpc_cc_polarity pd_get_polarity(int port)
-{
-	return POLARITY_CC1;
-}
-
-void pd_request_data_swap(int port)
-{}
-
-void pd_request_vconn_swap_off(int port)
-{}
-
-void pd_request_vconn_swap_on(int port)
-{}
-
-bool pd_alt_mode_capable(int port)
-{
-	return false;
-}
diff --git a/common/motion_orientation.c b/common/motion_orientation.c
deleted file mode 100644
index 9a20ff8499..0000000000
--- a/common/motion_orientation.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Implement an orientation sensor. */
-
-#include "motion_orientation.h"
-
-/*
- * Orientation mode vectors, must match sequential ordering of
- * known orientations from enum motionsensor_orientation
- */
-static const intv3_t orientation_modes[] = {
-	[MOTIONSENSE_ORIENTATION_LANDSCAPE] = { 0, -1, 0 },
-	[MOTIONSENSE_ORIENTATION_PORTRAIT] = { 1, 0, 0 },
-	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT] = { -1, 0, 0 },
-	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE] = { 0, 1, 0 },
-};
-
-enum motionsensor_orientation motion_orientation_remap(
-		const struct motion_sensor_t *s,
-		enum motionsensor_orientation orientation)
-{
-	enum motionsensor_orientation rotated_orientation;
-	const intv3_t *orientation_v;
-	intv3_t rotated_orientation_v;
-
-	if (orientation == MOTIONSENSE_ORIENTATION_UNKNOWN)
-		return MOTIONSENSE_ORIENTATION_UNKNOWN;
-
-	orientation_v = &orientation_modes[orientation];
-	rotate(*orientation_v, *s->rot_standard_ref, rotated_orientation_v);
-	rotated_orientation = ((2 * rotated_orientation_v[1] +
-			rotated_orientation_v[0] + 4) % 5);
-	return rotated_orientation;
-}
diff --git a/common/newton_fit.c b/common/newton_fit.c
deleted file mode 100644
index ae81a45f07..0000000000
--- a/common/newton_fit.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "newton_fit.h"
-#include "math.h"
-#include "math_util.h"
-#include <string.h>
-
-#define CPRINTS(fmt, args...) cprints(CC_MOTION_SENSE, fmt, ##args)
-
-static fp_t distance_squared(fpv3_t a, fpv3_t b)
-{
-	fpv3_t delta;
-
-	fpv3_init(delta, a[X] - b[X], a[Y] - b[Y], a[Z] - b[Z]);
-	return fpv3_dot(delta, delta);
-}
-
-static fp_t compute_error(struct newton_fit *fit, fpv3_t center)
-{
-	fp_t error = FLOAT_TO_FP(0.0f);
-	struct queue_iterator it;
-	struct newton_fit_orientation *_it;
-
-	for (queue_begin(fit->orientations, &it); it.ptr != NULL;
-	     queue_next(fit->orientations, &it)) {
-		fp_t e;
-
-		_it = (struct newton_fit_orientation *)it.ptr;
-		e = FLOAT_TO_FP(1.0f) -
-			distance_squared(_it->orientation, center);
-		error += fp_mul(e, e);
-	}
-
-	return error;
-}
-
-static bool is_ready_to_compute(struct newton_fit *fit, bool prune)
-{
-	bool has_min_samples = true;
-	struct queue_iterator it;
-	struct newton_fit_orientation *_it;
-
-	/* Not full, not ready to compute. */
-	if (!queue_is_full(fit->orientations))
-		return false;
-
-	/* Inspect all the orientations. */
-	for (queue_begin(fit->orientations, &it); it.ptr != NULL;
-	     queue_next(fit->orientations, &it)) {
-		_it = (struct newton_fit_orientation *)it.ptr;
-		/* If an orientation has too few samples, flag that. */
-		CPRINTS("    orientation %u/%u", _it->nsamples,
-			fit->min_orientation_samples);
-		if (_it->nsamples < fit->min_orientation_samples) {
-			has_min_samples = false;
-			break;
-		}
-	}
-
-	/* If all orientations have the minimum samples, we're done and can
-	 * compute the bias.
-	 */
-	if (has_min_samples)
-		return true;
-
-	/* If we got here and prune is true, then we need to remove the oldest
-	 * entry to make room for new orientations.
-	 */
-	if (prune)
-		queue_advance_head(fit->orientations, 1);
-
-	return false;
-}
-
-void newton_fit_reset(struct newton_fit *fit)
-{
-	queue_init(fit->orientations);
-}
-
-bool newton_fit_accumulate(struct newton_fit *fit, fp_t x, fp_t y, fp_t z)
-{
-	struct queue_iterator it;
-	struct newton_fit_orientation *_it;
-	fpv3_t v, delta;
-
-	fpv3_init(v, x, y, z);
-
-	/* Check if we can merge this new data point with an existing
-	 * orientation.
-	 */
-	for (queue_begin(fit->orientations, &it); it.ptr != NULL;
-	     queue_next(fit->orientations, &it)) {
-		_it = (struct newton_fit_orientation *)it.ptr;
-
-		fpv3_sub(delta, v, _it->orientation);
-		/* Skip entries that are too far away. */
-		if (fpv3_dot(delta, delta) >= fit->nearness_threshold)
-			continue;
-
-		/* Merge new data point with this orientation. */
-		fpv3_scalar_mul(_it->orientation,
-				FLOAT_TO_FP(1.0f) - fit->new_pt_weight);
-		fpv3_scalar_mul(v, fit->new_pt_weight);
-		fpv3_add(_it->orientation, _it->orientation, v);
-		if (_it->nsamples < 0xff)
-			_it->nsamples++;
-		return is_ready_to_compute(fit, false);
-	}
-
-	/* If queue isn't full. */
-	if (!queue_is_full(fit->orientations)) {
-		struct newton_fit_orientation entry;
-
-		entry.nsamples = 1;
-		fpv3_init(entry.orientation, x, y, z);
-		queue_add_unit(fit->orientations, &entry);
-
-		return is_ready_to_compute(fit, false);
-	}
-
-	return is_ready_to_compute(fit, true);
-}
-
-void newton_fit_compute(struct newton_fit *fit, fpv3_t bias, fp_t *radius)
-{
-	struct queue_iterator it;
-	struct newton_fit_orientation *_it;
-	fpv3_t new_bias, offset, delta;
-	fp_t error, new_error;
-	uint32_t iteration = 0;
-	fp_t inv_orient_count;
-
-	if (queue_is_empty(fit->orientations))
-		return;
-
-	inv_orient_count = fp_div(FLOAT_TO_FP(1.0f),
-				  queue_count(fit->orientations));
-
-	memcpy(new_bias, bias, sizeof(fpv3_t));
-	new_error = compute_error(fit, new_bias);
-
-	do {
-		memcpy(bias, new_bias, sizeof(fpv3_t));
-		error = new_error;
-		fpv3_zero(offset);
-
-		for (queue_begin(fit->orientations, &it); it.ptr != NULL;
-		     queue_next(fit->orientations, &it)) {
-			fp_t mag;
-
-			_it = (struct newton_fit_orientation *)it.ptr;
-
-			fpv3_sub(delta, _it->orientation, bias);
-			mag = fpv3_norm(delta);
-			fpv3_scalar_mul(delta,
-					fp_div(mag - FLOAT_TO_FP(1.0f), mag));
-			fpv3_add(offset, offset, delta);
-		}
-
-		fpv3_scalar_mul(offset, inv_orient_count);
-		fpv3_add(new_bias, bias, offset);
-		new_error = compute_error(fit, new_bias);
-		if (new_error > error)
-			memcpy(new_bias, bias, sizeof(fpv3_t));
-		++iteration;
-	} while (iteration < fit->max_iterations && new_error < error &&
-		 new_error > fit->error_threshold);
-
-	memcpy(bias, new_bias, sizeof(fpv3_t));
-
-	if (radius) {
-		*radius = FLOAT_TO_FP(0.0f);
-		for (queue_begin(fit->orientations, &it); it.ptr != NULL;
-		     queue_next(fit->orientations, &it)) {
-			_it = (struct newton_fit_orientation *)it.ptr;
-			fpv3_sub(delta, _it->orientation, bias);
-			*radius += fpv3_norm(delta);
-		}
-		*radius *= inv_orient_count;
-	}
-}
diff --git a/common/ocpc.c b/common/ocpc.c
deleted file mode 100644
index 3bc2a265d3..0000000000
--- a/common/ocpc.c
+++ /dev/null
@@ -1,767 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* OCPC - One Charger IC Per Type-C module */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "math_util.h"
-#include "ocpc.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/*
- * These constants were chosen by tuning the PID loop to reduce oscillations and
- * minimize overshoot.
- */
-#define KP 1
-#define KP_DIV 4
-#define KI 1
-#define KI_DIV 15
-#define KD 1
-#define KD_DIV 10
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINT_VIZ(format, args...) \
-do {							\
-	if (viz_output)				\
-		cprintf(CC_CHARGER, format, ## args);	\
-} while (0)
-#define CPRINTS_DBG(format, args...) \
-do {							\
-	if (debug_output)				\
-		cprints(CC_CHARGER, format, ## args);	\
-} while (0)
-#define CPRINTF_DBG(format, args...) \
-do {							\
-	if (debug_output)				\
-		cprintf(CC_CHARGER, format, ## args);	\
-} while (0)
-
-
-/* Code refactor will be needed if more than 2 charger chips are present */
-BUILD_ASSERT(CHARGER_NUM == 2);
-
-static int k_p = KP;
-static int k_i = KI;
-static int k_d = KD;
-static int k_p_div = KP_DIV;
-static int k_i_div = KI_DIV;
-static int k_d_div = KD_DIV;
-static int debug_output;
-static int viz_output;
-
-#define NUM_RESISTANCE_SAMPLES 8
-#define COMBINED_IDX 0
-#define RBATT_IDX 1
-#define RSYS_IDX 2
-static int resistance_tbl[NUM_RESISTANCE_SAMPLES][3] = {
-	/* Rsys+Rbatt                   Rbatt                    Rsys */
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-};
-static int resistance_tbl_idx;
-static int mean_resistance[3];
-static int stddev_resistance[3];
-static int ub[3];
-static int lb[3];
-
-enum phase {
-	PHASE_UNKNOWN = -1,
-	PHASE_PRECHARGE,
-	PHASE_CC,
-	PHASE_CV_TRIP,
-	PHASE_CV_COMPLETE,
-};
-
-__overridable void board_ocpc_init(struct ocpc_data *ocpc)
-{
-}
-
-static enum ec_error_list ocpc_precharge_enable(bool enable);
-
-static void calc_resistance_stats(struct ocpc_data *ocpc)
-{
-	int i;
-	int j;
-	int sum;
-	int cols = 3;
-	int act_chg = ocpc->active_chg_chip;
-
-	/* Only perform separate stats on Rsys and Rbatt if necessary. */
-	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP))
-		cols = 1;
-
-	/* Calculate mean */
-	for (i = 0; i < cols; i++) {
-		sum = 0;
-		for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++) {
-			sum += resistance_tbl[j][i];
-			CPRINTF_DBG("%d ", resistance_tbl[j][i]);
-		}
-		CPRINTF_DBG("\n");
-
-		mean_resistance[i] = sum / NUM_RESISTANCE_SAMPLES;
-
-		/* Calculate standard deviation */
-		sum = 0;
-		for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++)
-			sum += POW2(resistance_tbl[j][i] - mean_resistance[i]);
-
-		stddev_resistance[i] = fp_sqrtf(INT_TO_FP(sum /
-						       NUM_RESISTANCE_SAMPLES));
-		stddev_resistance[i] = FP_TO_INT(stddev_resistance[i]);
-		/*
-		 * Don't let our stddev collapse to 0 to continually consider
-		 * new values.
-		 */
-		stddev_resistance[i] = MAX(stddev_resistance[i], 1);
-		CPRINTS_DBG("%d: mean: %d stddev: %d", i, mean_resistance[i],
-			    stddev_resistance[i]);
-		lb[i] = MAX(0, mean_resistance[i] - (3 * stddev_resistance[i]));
-		ub[i] = mean_resistance[i] + (3 * stddev_resistance[i]);
-	}
-}
-
-static bool is_within_range(struct ocpc_data *ocpc, int combined, int rbatt,
-			    int rsys)
-{
-	int act_chg = ocpc->active_chg_chip;
-	bool valid;
-
-	/* Discard measurements not within a 6 std. dev. window. */
-	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
-		/* We only know the combined Rsys+Rbatt */
-		valid = (combined > 0) &&
-			(combined <= ub[COMBINED_IDX]) &&
-			(combined >= lb[COMBINED_IDX]);
-	} else {
-		valid = (rsys <= ub[RSYS_IDX]) && (rsys >= lb[RSYS_IDX]) &&
-			(rbatt <= ub[RBATT_IDX]) && (rbatt >= lb[RBATT_IDX]) &&
-			(rsys > 0) && (rbatt > 0);
-	}
-
-	if (!valid)
-		CPRINTS_DBG("Discard Rc:%d Rb:%d Rs:%d", combined, rbatt, rsys);
-
-	return valid;
-}
-
-enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
-					 struct batt_params *battery)
-{
-	int act_chg = ocpc->active_chg_chip;
-	static bool seeded;
-	static int initial_samples;
-	int combined;
-	int rsys = -1;
-	int rbatt = -1;
-
-	/*
-	 * In order to actually calculate the resistance, we need to make sure
-	 * we're actually charging the battery at a significant rate.  The LSB
-	 * of a charger IC can be as high as 96mV.  Assuming a resistance of 60
-	 * mOhms, we would need a current of 1666mA to have a voltage delta of
-	 * 100mV.
-	 */
-	if ((battery->current <= 1666) ||
-	    (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP) &&
-	     (ocpc->isys_ma <= 0)) ||
-	    (ocpc->vsys_aux_mv < ocpc->vsys_mv)) {
-		CPRINTS_DBG("Not charging... won't determine resistance");
-		CPRINTS_DBG("vsys_aux_mv: %dmV vsys_mv: %dmV",
-			    ocpc->vsys_aux_mv, ocpc->vsys_mv);
-		return EC_ERROR_INVALID_CONFIG; /* We must be charging */
-	}
-
-	/*
-	 * The combined system and battery resistance is the delta between Vsys
-	 * and Vbatt divided by Ibatt.
-	 */
-	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
-		/*
-		 * There's no provision to measure Isys, so we cannot separate
-		 * out Rsys from Rbatt.
-		 */
-		combined = ((ocpc->vsys_aux_mv - battery->voltage) * 1000) /
-			    battery->current;
-	} else {
-		rsys = ((ocpc->vsys_aux_mv - ocpc->vsys_mv) * 1000) /
-				 ocpc->isys_ma;
-		rbatt = ((ocpc->vsys_mv - battery->voltage) * 1000) /
-				 battery->current;
-		combined = rsys + rbatt;
-	}
-
-	/* Discard measurements not within a 6 std dev window. */
-	if ((!seeded) ||
-	    (seeded && is_within_range(ocpc, combined, rbatt, rsys))) {
-		if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
-			resistance_tbl[resistance_tbl_idx][RSYS_IDX] =
-				MAX(rsys, 0);
-			resistance_tbl[resistance_tbl_idx][RBATT_IDX] =
-				MAX(rbatt, CONFIG_OCPC_DEF_RBATT_MOHMS);
-		}
-		resistance_tbl[resistance_tbl_idx][COMBINED_IDX] =
-			MAX(combined, CONFIG_OCPC_DEF_RBATT_MOHMS);
-		calc_resistance_stats(ocpc);
-		resistance_tbl_idx = (resistance_tbl_idx + 1) %
-					NUM_RESISTANCE_SAMPLES;
-	}
-
-	if (seeded) {
-		ocpc->combined_rsys_rbatt_mo =
-					MAX(mean_resistance[COMBINED_IDX],
-					    CONFIG_OCPC_DEF_RBATT_MOHMS);
-
-		if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
-			ocpc->rsys_mo = mean_resistance[RSYS_IDX];
-			ocpc->rbatt_mo = MAX(mean_resistance[RBATT_IDX],
-					     CONFIG_OCPC_DEF_RBATT_MOHMS);
-			CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm",
-				    ocpc->rsys_mo, ocpc->rbatt_mo);
-		}
-
-		CPRINTS_DBG("Rsys+Rbatt: %dmOhm", ocpc->combined_rsys_rbatt_mo);
-	} else {
-		seeded = ++initial_samples >= (2 * NUM_RESISTANCE_SAMPLES) ?
-			true : false;
-	}
-
-	return EC_SUCCESS;
-}
-
-int ocpc_config_secondary_charger(int *desired_input_current,
-				  struct ocpc_data *ocpc,
-				  int voltage_mv, int current_ma)
-{
-	int rv = EC_SUCCESS;
-	struct batt_params batt;
-	const struct battery_info *batt_info;
-	struct charger_params charger;
-	int vsys_target = 0;
-	int drive = 0;
-	int i_ma = 0;
-	static int i_ma_CC_CV;
-	int min_vsys_target;
-	int error = 0;
-	int derivative = 0;
-	static enum phase ph;
-	static int prev_limited;
-	int chgnum;
-	enum ec_error_list result;
-	static int iterations;
-	int i_step;
-	static timestamp_t delay;
-	int i, step, loc;
-	bool icl_reached = false;
-	static timestamp_t precharge_exit;
-
-	/*
-	 * There's nothing to do if we're not using this charger.  Should
-	 * there be more than two charger ICs in the future, the following check
-	 * should change to ensure that only the active charger IC is acted
-	 * upon.
-	 */
-	chgnum = charge_get_active_chg_chip();
-	if (chgnum != CHARGER_SECONDARY)
-		return EC_ERROR_INVAL;
-
-	batt_info = battery_get_info();
-
-	if (current_ma == 0) {
-		vsys_target = voltage_mv;
-		goto set_vsys;
-	}
-
-	/*
-	 * Check to see if the charge FET is disabled.  If it's disabled, the
-	 * charging loop is broken and increasing VSYS will not actually help.
-	 * Therefore, don't make any changes at this time.
-	 */
-	if (battery_is_charge_fet_disabled() &&
-	    (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED)) {
-		CPRINTS("CFET disabled; not changing VSYS!");
-
-		/*
-		 * Let's check back in 5 seconds to see if the CFET is enabled
-		 * now.  Note that if this continues to occur, we'll keep
-		 * pushing this out.
-		 */
-		delay = get_time();
-		delay.val += (5 * SECOND);
-		return EC_ERROR_INVALID_CONFIG;
-	}
-
-	/*
-	 * The CFET status changed recently, wait until it's no longer disabled
-	 * for awhile before modifying VSYS.  This could be the fuel gauge
-	 * performing some impedence calculations.
-	 */
-	if (!timestamp_expired(delay, NULL))
-		return EC_ERROR_BUSY;
-
-	result = charger_set_vsys_compensation(chgnum, ocpc, current_ma,
-					       voltage_mv);
-	switch (result) {
-	case EC_SUCCESS:
-		/* No further action required, so we're done here. */
-		return EC_SUCCESS;
-
-	case EC_ERROR_UNIMPLEMENTED:
-		/* Let's get to work */
-		break;
-
-	default:
-		/* Something went wrong configuring the auxiliary charger IC. */
-		CPRINTS("Failed to set VSYS compensation! (%d) (result: %d)",
-			chgnum, result);
-		return result;
-	}
-
-	if (ocpc->last_vsys == OCPC_UNINIT) {
-		ph = PHASE_UNKNOWN;
-		precharge_exit.val = 0;
-		iterations = 0;
-	}
-
-
-	/*
-	 * We need to induce a current flow that matches the requested current
-	 * by raising VSYS.  Let's start by getting the latest data that we
-	 * know of.
-	 */
-	batt_info = battery_get_info();
-	battery_get_params(&batt);
-	ocpc_get_adcs(ocpc);
-	charger_get_params(&charger);
-
-
-	/*
-	 * If the system is in S5/G3, we can calculate the board and battery
-	 * resistances.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_ANY_SUSPEND)) {
-		/*
-		 * In the first few iterations of the loop, charging isn't
-		 * stable/correct so making the calculation then leads to some
-		 * strange values throwing off the loop even more. However,
-		 * after those initial iterations it then begins to behave as
-		 * expected. From there onwards, the resistance values aren't
-		 * changing _too_ rapidly.  This is why we calculate with every
-		 * modulo 4 interval.
-		 */
-		iterations++;
-		if (!(iterations % 4))
-			ocpc_calc_resistances(ocpc, &batt);
-		iterations %= 5;
-	}
-
-	/* Set our current target accordingly. */
-	if (batt.desired_voltage) {
-		if (((batt.voltage < batt_info->voltage_min) ||
-		    ((batt.voltage < batt_info->voltage_normal) &&
-		    (current_ma <= batt_info->precharge_current))) &&
-		    (ph != PHASE_PRECHARGE)) {
-			/*
-			 * If the charger IC doesn't support the linear charge
-			 * feature, proceed to the CC phase.
-			 */
-			result = ocpc_precharge_enable(true);
-			if (result == EC_ERROR_UNIMPLEMENTED) {
-				ph = PHASE_CC;
-			} else if (result == EC_SUCCESS) {
-				CPRINTS("OCPC: Enabling linear precharge");
-				ph = PHASE_PRECHARGE;
-				i_ma = current_ma;
-			}
-		} else if (batt.voltage < batt.desired_voltage) {
-			if ((ph == PHASE_PRECHARGE) &&
-			    (current_ma >
-			     batt_info->precharge_current)) {
-				/*
-				 * Precharge phase is complete.  Now set the
-				 * target VSYS to the battery voltage to prevent
-				 * a large current spike during the transition.
-				 */
-				/*
-				 * If we'd like to exit precharge, let's wait a
-				 * short delay.
-				 */
-				if (!precharge_exit.val) {
-					CPRINTS("OCPC: Preparing to exit "
-						"precharge");
-					precharge_exit = get_time();
-					precharge_exit.val += 3 * SECOND;
-				}
-				if (timestamp_expired(precharge_exit, NULL)) {
-					CPRINTS("OCPC: Precharge complete");
-					charger_set_voltage(CHARGER_SECONDARY,
-							    batt.voltage);
-					ocpc->last_vsys = batt.voltage;
-					ocpc_precharge_enable(false);
-					ph = PHASE_CC;
-					precharge_exit.val = 0;
-				}
-			}
-
-			if ((ph != PHASE_PRECHARGE) && (ph < PHASE_CV_TRIP))
-				ph = PHASE_CC;
-			i_ma = current_ma;
-		} else {
-			/*
-			 * Once the battery voltage reaches the desired voltage,
-			 * we should note that we've reached the CV step and set
-			 * VSYS to the desired CV + offset.
-			 */
-			i_ma = batt.current;
-			ph = ph == PHASE_CC ? PHASE_CV_TRIP : PHASE_CV_COMPLETE;
-			if (ph == PHASE_CV_TRIP)
-				i_ma_CC_CV = batt.current;
-
-		}
-	}
-
-	/* Ensure our target is not negative. */
-	i_ma = MAX(i_ma, 0);
-
-	/* Convert desired mA to what the charger could actually regulate to. */
-	i_step = (int)charger_get_info()->current_step;
-	i_ma = (i_ma / i_step) * i_step;
-
-	/*
-	 * We'll use our current target and our combined Rsys+Rbatt to seed our
-	 * VSYS target.  However, we'll use a PID loop to correct the error and
-	 * help drive VSYS to what it _should_ be in order to reach our current
-	 * target.  The first time through this function, we won't make any
-	 * corrections in order to determine our initial error.
-	 */
-	if (ocpc->last_vsys != OCPC_UNINIT) {
-		error = i_ma - batt.current;
-		/* Add some hysteresis. */
-		if (ABS(error) < (i_step / 2))
-			error = 0;
-
-		/* Make a note if we're significantly over target. */
-		if (error < -100)
-			CPRINTS("OCPC: over target %dmA", error * -1);
-
-		derivative = error - ocpc->last_error;
-		ocpc->last_error = error;
-		ocpc->integral += error;
-		if (ocpc->integral > 500)
-			ocpc->integral = 500;
-	}
-
-	CPRINTS_DBG("phase = %d", ph);
-	CPRINTS_DBG("error = %dmA", error);
-	CPRINTS_DBG("derivative = %d", derivative);
-	CPRINTS_DBG("integral = %d", ocpc->integral);
-	CPRINTS_DBG("batt.voltage = %dmV", batt.voltage);
-	CPRINTS_DBG("batt.desired_voltage = %dmV", batt.desired_voltage);
-	CPRINTS_DBG("batt.desired_current = %dmA", batt.desired_current);
-	CPRINTS_DBG("batt.current = %dmA", batt.current);
-	CPRINTS_DBG("i_ma = %dmA", i_ma);
-
-	min_vsys_target = MIN(batt.voltage, batt.desired_voltage);
-	CPRINTS_DBG("min_vsys_target = %d", min_vsys_target);
-
-	/* Obtain the drive from our PID controller. */
-	if ((ocpc->last_vsys != OCPC_UNINIT) &&
-	    (ph > PHASE_PRECHARGE)) {
-		drive = (k_p * error / k_p_div) +
-			(k_i * ocpc->integral / k_i_div) +
-			(k_d * derivative / k_d_div);
-		/*
-		 * Let's limit upward transitions to 10mV.  It's okay to reduce
-		 * VSYS rather quickly, but we'll be conservative on
-		 * increasing VSYS.
-		 */
-		if (drive > 10)
-			drive = 10;
-		CPRINTS_DBG("drive = %d", drive);
-	}
-
-	/*
-	 * For the pre-charge phase, simply keep the VSYS target at the desired
-	 * voltage.
-	 */
-	if (ph == PHASE_PRECHARGE)
-		vsys_target = batt.desired_voltage;
-
-	/*
-	 * Adjust our VSYS target by applying the calculated drive.  Note that
-	 * we won't apply our drive the first time through this function such
-	 * that we can determine our initial error.
-	 */
-	if ((ocpc->last_vsys != OCPC_UNINIT) && (ph > PHASE_PRECHARGE))
-		vsys_target = ocpc->last_vsys + drive;
-
-	/*
-	 * Once we're in the CV region, all we need to do is keep VSYS at the
-	 * desired voltage.
-	 */
-	if (ph == PHASE_CV_TRIP) {
-		vsys_target = batt.desired_voltage +
-				((i_ma_CC_CV *
-				  ocpc->combined_rsys_rbatt_mo) / 1000);
-		CPRINTS_DBG("i_ma_CC_CV = %d", i_ma_CC_CV);
-	}
-	if (ph == PHASE_CV_COMPLETE)
-		vsys_target = batt.desired_voltage +
-				((batt_info->precharge_current *
-				  ocpc->combined_rsys_rbatt_mo) / 1000);
-
-	/*
-	 * Ensure VSYS is no higher than the specified maximum battery voltage
-	 * plus the voltage drop across the system.
-	 */
-	vsys_target = CLAMP(vsys_target, min_vsys_target,
-			    batt_info->voltage_max +
-			    (i_ma * ocpc->combined_rsys_rbatt_mo / 1000));
-
-	/* If we're input current limited, we cannot increase VSYS any more. */
-	CPRINTS_DBG("OCPC: Inst. Input Current: %dmA (Limit: %dmA)",
-		    ocpc->secondary_ibus_ma, *desired_input_current);
-
-	if (charger_is_icl_reached(chgnum, &icl_reached) != EC_SUCCESS) {
-		/*
-		 * If the charger doesn't support telling us, assume that the
-		 * input current limit is reached if we're consuming more than
-		 * 95% of the limit.
-		 */
-		if (ocpc->secondary_ibus_ma >=
-		     (*desired_input_current * 95 / 100))
-			icl_reached = true;
-	}
-
-	if (icl_reached && (vsys_target > ocpc->last_vsys) &&
-	    (ocpc->last_vsys != OCPC_UNINIT)) {
-		if (!prev_limited)
-			CPRINTS("Input limited! Not increasing VSYS");
-		prev_limited = 1;
-		return rv;
-	}
-	prev_limited = 0;
-
-set_vsys:
-	/* VSYS should never be below the battery's min voltage. */
-	vsys_target = MAX(vsys_target, batt_info->voltage_min);
-	/* To reduce spam, only print when we change VSYS significantly. */
-	if ((ABS(vsys_target - ocpc->last_vsys) > 10) || debug_output)
-		CPRINTS("OCPC: Target VSYS: %dmV", vsys_target);
-	charger_set_voltage(CHARGER_SECONDARY, vsys_target);
-	ocpc->last_vsys = vsys_target;
-
-	/*
-	 * Print a visualization graph of the actual current vs. the target.
-	 * Each position represents 5% of the target current.
-	 */
-	if (i_ma != 0) {
-		step = 5 * i_ma / 100;
-		loc = error / step;
-		loc = CLAMP(loc, -10, 10);
-		CPRINT_VIZ("[");
-		for (i = -10; i <= 10; i++) {
-			if (i == 0)
-				CPRINT_VIZ(loc == 0 ? "#" : "|");
-			else
-				CPRINT_VIZ(i == loc ? "o" : "-");
-		}
-		CPRINT_VIZ("] (actual)%dmA (desired)%dmA\n", batt.current,
-			   i_ma);
-	}
-
-	return rv;
-}
-
-void ocpc_get_adcs(struct ocpc_data *ocpc)
-{
-	int val;
-
-	val = 0;
-	if (!charger_get_vbus_voltage(CHARGER_PRIMARY, &val))
-		ocpc->primary_vbus_mv = val;
-
-	val = 0;
-	if (!charger_get_input_current(CHARGER_PRIMARY, &val))
-		ocpc->primary_ibus_ma = val;
-
-	val = 0;
-	if (!charger_get_actual_voltage(CHARGER_PRIMARY, &val))
-		ocpc->vsys_mv = val;
-
-	if (board_get_charger_chip_count() <= CHARGER_SECONDARY) {
-		ocpc->secondary_vbus_mv = 0;
-		ocpc->secondary_ibus_ma = 0;
-		ocpc->vsys_aux_mv = 0;
-		ocpc->isys_ma = 0;
-		return;
-	}
-
-	val = 0;
-	if (!charger_get_vbus_voltage(CHARGER_SECONDARY, &val))
-		ocpc->secondary_vbus_mv = val;
-
-	val = 0;
-	if (!charger_get_input_current(CHARGER_SECONDARY, &val))
-		ocpc->secondary_ibus_ma = val;
-
-	val = 0;
-	if (!charger_get_actual_voltage(CHARGER_SECONDARY, &val))
-		ocpc->vsys_aux_mv = val;
-
-	val = 0;
-	if (!charger_get_actual_current(CHARGER_SECONDARY, &val))
-		ocpc->isys_ma = val;
-}
-
-__overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
-					  int *ki, int *ki_div,
-					  int *kd, int *kd_div)
-{
-}
-
-static enum ec_error_list ocpc_precharge_enable(bool enable)
-{
-	/* Enable linear charging on the primary charger IC. */
-	int rv = charger_enable_linear_charge(CHARGER_PRIMARY, enable);
-
-	if (rv)
-		CPRINTS("OCPC: Failed to %sble linear charge!", enable ? "ena"
-			: "dis");
-
-	return rv;
-}
-
-void ocpc_reset(struct ocpc_data *ocpc)
-{
-	struct batt_params batt;
-
-	battery_get_params(&batt);
-	ocpc->integral = 0;
-	ocpc->last_error = 0;
-	ocpc->last_vsys = OCPC_UNINIT;
-
-	/*
-	 * Initialize the VSYS target on the aux chargers to the current battery
-	 * voltage to avoid a large spike.
-	 */
-	if (ocpc->active_chg_chip > CHARGER_PRIMARY && batt.voltage > 0) {
-		CPRINTS("OCPC: C%d Init VSYS to %dmV", ocpc->active_chg_chip,
-			batt.voltage);
-		charger_set_voltage(ocpc->active_chg_chip, batt.voltage);
-	}
-
-	/*
-	 * See(b:191347747) When linear precharge is enabled, it may affect
-	 * the charging behavior from the primary charger IC. Therefore as
-	 * a part of the reset process, we need to disable linear precharge.
-	 */
-	ocpc_precharge_enable(false);
-}
-
-static void ocpc_set_pid_constants(void)
-{
-	ocpc_get_pid_constants(&k_p, &k_p_div, &k_i, &k_i_div, &k_d, &k_d_div);
-}
-DECLARE_HOOK(HOOK_INIT, ocpc_set_pid_constants, HOOK_PRIO_DEFAULT);
-
-void ocpc_init(struct ocpc_data *ocpc)
-{
-	/*
-	 * We can start off assuming that the board resistance is 0 ohms
-	 * and later on, we can update this value if we charge the
-	 * system in suspend or off.
-	 */
-	ocpc->combined_rsys_rbatt_mo = CONFIG_OCPC_DEF_RBATT_MOHMS;
-	ocpc->rbatt_mo = CONFIG_OCPC_DEF_RBATT_MOHMS;
-
-	board_ocpc_init(ocpc);
-}
-
-static int command_ocpcdebug(int argc, char **argv)
-{
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strncmp(argv[1], "ena", 3)) {
-		debug_output = true;
-		viz_output = false;
-	} else if (!strncmp(argv[1], "dis", 3)) {
-		debug_output = false;
-		viz_output = false;
-	} else if (!strncmp(argv[1], "viz", 3)) {
-		debug_output = false;
-		viz_output = true;
-	} else if (!strncmp(argv[1], "all", 3)) {
-		debug_output = true;
-		viz_output = true;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ocpcdebug, command_ocpcdebug,
-			     "<enable/viz/all/disable",
-			     "Enable/disable debug prints for OCPC data. "
-			     "Enable turns on text debug, viz shows a graph."
-			     "Each segment is 5% of current target. All shows"
-			     " both. Disable shows no debug output.");
-
-static int command_ocpcpid(int argc, char **argv)
-{
-	int *num, *denom;
-
-	if (argc == 4) {
-		switch (argv[1][0]) {
-		case 'p':
-			num = &k_p;
-			denom = &k_p_div;
-			break;
-
-		case 'i':
-			num = &k_i;
-			denom = &k_i_div;
-			break;
-
-		case 'd':
-			num = &k_d;
-			denom = &k_d_div;
-			break;
-		default:
-			return EC_ERROR_PARAM1;
-		}
-
-		*num = atoi(argv[2]);
-		*denom = atoi(argv[3]);
-	}
-
-	/* Print the current constants */
-	ccprintf("Kp = %d / %d\n", k_p, k_p_div);
-	ccprintf("Ki = %d / %d\n", k_i, k_i_div);
-	ccprintf("Kd = %d / %d\n", k_d, k_d_div);
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ocpcpid, command_ocpcpid,
-			     "[<k/p/d> <numerator> <denominator>]",
-			     "Show/Set PID constants for OCPC PID loop");
diff --git a/common/onewire.c b/common/onewire.c
deleted file mode 100644
index cdb5837255..0000000000
--- a/common/onewire.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* 1-wire interface module for Chrome EC */
-
-#include "common.h"
-#include "gpio.h"
-#include "task.h"
-#include "timer.h"
-
-/*
- * Standard speed; all timings padded by 2 usec for safety.
- *
- * Note that these timing are actually _longer_ than legacy 1-wire standard
- * speed because we're running the 1-wire bus at 3.3V instead of 5V.
- */
-#define T_RSTL 602  /* Reset low pulse; 600-960 us */
-#define T_MSP   72  /* Presence detect sample time; 70-75 us */
-#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin */
-#define T_SLOT  70  /* Timeslot; >67 us */
-#define T_W0L   63  /* Write 0 low; 62-120 us */
-#define T_W1L    7  /* Write 1 low; 5-15 us */
-#define T_RL     7  /* Read low; 5-15 us */
-#define T_MSR    9  /* Read sample time; <15 us.  Must be at least 200 ns after
-		     * T_RL since that's how long the signal takes to be pulled
-		     * up on our board.  */
-
-/**
- * Output low on the bus for <usec> us, then switch back to open-drain input.
- */
-static void output0(int usec)
-{
-	gpio_set_flags(GPIO_ONEWIRE,
-		       GPIO_OPEN_DRAIN | GPIO_OUTPUT | GPIO_OUT_LOW);
-	udelay(usec);
-	gpio_set_flags(GPIO_ONEWIRE, GPIO_INPUT);
-}
-
-/**
- * Read a bit.
- */
-static int readbit(void)
-{
-	int bit;
-
-	/*
-	 * The delay between sending the output pulse and reading the bit is
-	 * extremely timing sensitive, so disable interrupts.
-	 */
-	interrupt_disable();
-
-	/* Output low */
-	output0(T_RL);
-
-	/*
-	 * Delay to let peripheral release the line if it wants to send
-	 * a 1-bit
-	 */
-	udelay(T_MSR - T_RL);
-
-	/* Read bit */
-	bit = gpio_get_level(GPIO_ONEWIRE);
-
-	/*
-	 * Enable interrupt as soon as we've read the bit.  The delay to the
-	 * end of the timeslot is a lower bound, so additional latency here is
-	 * harmless.
-	 */
-	interrupt_enable();
-
-	/* Delay to end of timeslot */
-	udelay(T_SLOT - T_MSR);
-	return bit;
-}
-
-/**
- * Write a bit.
- */
-static void writebit(int bit)
-{
-	/*
-	 * The delays in the output-low signal for sending 0 and 1 bits are
-	 * extremely timing sensitive, so disable interrupts during that time.
-	 * Interrupts can be enabled again as soon as the output is switched
-	 * back to open-drain, since the delay for the rest of the timeslot is
-	 * a lower bound.
-	 */
-	if (bit) {
-		interrupt_disable();
-		output0(T_W1L);
-		interrupt_enable();
-		udelay(T_SLOT - T_W1L);
-	} else {
-		interrupt_disable();
-		output0(T_W0L);
-		interrupt_enable();
-		udelay(T_SLOT - T_W0L);
-	}
-
-}
-
-int onewire_reset(void)
-{
-	/* Start transaction with controller reset pulse */
-	output0(T_RSTL);
-
-	/* Wait for presence detect sample time.
-	 *
-	 * (Alternately, we could poll waiting for a 1-bit indicating our pulse
-	 * has let go, then poll up to max time waiting for a 0-bit indicating
-	 * the peripheral has responded.)
-	 */
-	udelay(T_MSP);
-
-	if (gpio_get_level(GPIO_ONEWIRE))
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Wait for end of presence pulse.
-	 *
-	 * (Alternately, we could poll waiting for a 1-bit.)
-	 */
-	udelay(T_RSTH - T_MSP);
-
-	return EC_SUCCESS;
-}
-
-int onewire_read(void)
-{
-	int data = 0;
-	int i;
-
-	for (i = 0; i < 8; i++)
-		data |= readbit() << i;  /* LSB first */
-
-	return data;
-}
-
-void onewire_write(int data)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		writebit((data >> i) & 0x01);  /* LSB first */
-}
diff --git a/common/online_calibration.c b/common/online_calibration.c
deleted file mode 100644
index 3bc56f85c7..0000000000
--- a/common/online_calibration.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accelgyro.h"
-#include "atomic.h"
-#include "hwtimer.h"
-#include "online_calibration.h"
-#include "common.h"
-#include "mag_cal.h"
-#include "util.h"
-#include "vec3.h"
-#include "task.h"
-#include "ec_commands.h"
-#include "accel_cal.h"
-#include "mkbp_event.h"
-#include "gyro_cal.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
-
-#ifndef CONFIG_MKBP_EVENT
-#error "Must use CONFIG_MKBP_EVENT for online calibration"
-#endif /* CONFIG_MKBP_EVENT */
-
-/** Bitmap telling which online calibration values are valid. */
-static uint32_t sensor_calib_cache_valid_map;
-/** Bitmap telling which online calibration values are dirty. */
-static uint32_t sensor_calib_cache_dirty_map;
-
-struct mutex g_calib_cache_mutex;
-
-static int get_temperature(struct motion_sensor_t *sensor, int *temp)
-{
-	struct online_calib_data *entry = sensor->online_calib_data;
-	uint32_t now;
-
-	if (sensor->drv->read_temp == NULL)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	now = __hw_clock_source_read();
-	if (entry->last_temperature < 0 ||
-	    time_until(entry->last_temperature_timestamp, now) >
-		    CONFIG_TEMP_CACHE_STALE_THRES) {
-		int t;
-		int rc = sensor->drv->read_temp(sensor, &t);
-
-		if (rc == EC_SUCCESS) {
-			entry->last_temperature = t;
-			entry->last_temperature_timestamp = now;
-		} else {
-			return rc;
-		}
-	}
-
-	*temp = entry->last_temperature;
-	return EC_SUCCESS;
-}
-
-static void data_int16_to_fp(const struct motion_sensor_t *s,
-			     const int16_t *data, fpv3_t out)
-{
-	int i;
-	fp_t range = INT_TO_FP(s->current_range);
-
-	for (i = 0; i < 3; ++i) {
-		fp_t v = INT_TO_FP((int32_t)data[i]);
-
-		out[i] = fp_div(v, INT_TO_FP((data[i] >= 0) ? 0x7fff : 0x8000));
-		out[i] = fp_mul(out[i], range);
-		/* Check for overflow */
-		out[i] = CLAMP(out[i], -range, range);
-	}
-}
-
-static void data_fp_to_int16(const struct motion_sensor_t *s, const fpv3_t data,
-			     int16_t *out)
-{
-	int i;
-	fp_t range = INT_TO_FP(s->current_range);
-
-	for (i = 0; i < 3; ++i) {
-		int32_t iv;
-		fp_t v = fp_div(data[i], range);
-
-		v = fp_mul(v, INT_TO_FP(0x7fff));
-		iv = FP_TO_INT(v);
-		/* Check for overflow */
-		out[i] = ec_motion_sensor_clamp_i16(iv);
-	}
-}
-
-/**
- * Check a gyroscope for new bias. This function checks a given sensor (must be
- * a gyroscope) for new bias values. If found, it will update the appropriate
- * caches and notify the AP.
- *
- * @param sensor Pointer to the gyroscope sensor to check.
- */
-static bool check_gyro_cal_new_bias(struct motion_sensor_t *sensor,
-				    fpv3_t bias_out)
-{
-	struct online_calib_data *calib_data =
-		(struct online_calib_data *)sensor->online_calib_data;
-	struct gyro_cal_data *data =
-		(struct gyro_cal_data *)calib_data->type_specific_data;
-	int temp_out;
-	uint32_t timestamp_out;
-
-	/* Check that we have a new bias. */
-	if (data == NULL || calib_data == NULL ||
-	    !gyro_cal_new_bias_available(&data->gyro_cal))
-		return false;
-
-	/* Read the calibration values. */
-	gyro_cal_get_bias(&data->gyro_cal, bias_out, &temp_out, &timestamp_out);
-	return true;
-}
-
-static void set_gyro_cal_cache_values(struct motion_sensor_t *sensor,
-				      fpv3_t bias)
-{
-	size_t sensor_num = sensor - motion_sensors;
-	struct online_calib_data *calib_data =
-		(struct online_calib_data *)sensor->online_calib_data;
-
-	mutex_lock(&g_calib_cache_mutex);
-	/* Convert result to the right scale and save to cache. */
-	data_fp_to_int16(sensor, bias, calib_data->cache);
-	/* Set valid and dirty. */
-	sensor_calib_cache_valid_map |= BIT(sensor_num);
-	sensor_calib_cache_dirty_map |= BIT(sensor_num);
-	mutex_unlock(&g_calib_cache_mutex);
-	/* Notify the AP. */
-	mkbp_send_event(EC_MKBP_EVENT_ONLINE_CALIBRATION);
-}
-
-/**
- * Update the data stream (accel/mag) for a given sensor and data in all
- * gyroscopes that are interested.
- *
- * @param sensor Pointer to the sensor that generated the data.
- * @param data 3 floats/fixed point data points generated by the sensor.
- * @param timestamp The timestamp at which the data was generated.
- */
-static void update_gyro_cal(struct motion_sensor_t *sensor, fpv3_t data,
-			    uint32_t timestamp)
-{
-	int i;
-	fpv3_t gyro_cal_data_out;
-
-	/*
-	 * Find gyroscopes, while we don't currently have instance where more
-	 * than one are present in a board, this loop will work with any number
-	 * of them.
-	 */
-	for (i = 0; i < SENSOR_COUNT; ++i) {
-		struct motion_sensor_t *s = motion_sensors + i;
-		struct gyro_cal_data *gyro_cal_data =
-			(struct gyro_cal_data *)
-				s->online_calib_data->type_specific_data;
-		bool has_new_gyro_cal_bias = false;
-
-		/*
-		 * If we're not looking at a gyroscope OR if the calibration
-		 * data is NULL, skip this sensor.
-		 */
-		if (s->type != MOTIONSENSE_TYPE_GYRO || gyro_cal_data == NULL)
-			continue;
-
-		/*
-		 * Update the appropriate data stream (accel/mag) depending on
-		 * which sensors the gyroscope is tracking.
-		 */
-		if (sensor->type == MOTIONSENSE_TYPE_ACCEL &&
-		    gyro_cal_data->accel_sensor_id == sensor - motion_sensors) {
-			gyro_cal_update_accel(&gyro_cal_data->gyro_cal,
-					      timestamp, data[X], data[Y],
-					      data[Z]);
-			has_new_gyro_cal_bias =
-				check_gyro_cal_new_bias(s, gyro_cal_data_out);
-		} else if (sensor->type == MOTIONSENSE_TYPE_MAG &&
-			   gyro_cal_data->mag_sensor_id ==
-				   sensor - motion_sensors) {
-			gyro_cal_update_mag(&gyro_cal_data->gyro_cal, timestamp,
-					    data[X], data[Y], data[Z]);
-			has_new_gyro_cal_bias =
-				check_gyro_cal_new_bias(s, gyro_cal_data_out);
-		}
-
-		if (has_new_gyro_cal_bias)
-			set_gyro_cal_cache_values(s, gyro_cal_data_out);
-	}
-}
-
-void online_calibration_init(void)
-{
-	size_t i;
-
-	for (i = 0; i < SENSOR_COUNT; i++) {
-		struct motion_sensor_t *s = motion_sensors + i;
-		void *type_specific_data = NULL;
-
-		if (s->online_calib_data) {
-			s->online_calib_data->last_temperature = -1;
-			type_specific_data =
-				s->online_calib_data->type_specific_data;
-		}
-
-		if (!type_specific_data)
-			continue;
-
-		switch (s->type) {
-		case MOTIONSENSE_TYPE_ACCEL: {
-			accel_cal_reset((struct accel_cal *)type_specific_data);
-			break;
-		}
-		case MOTIONSENSE_TYPE_MAG: {
-			init_mag_cal((struct mag_cal_t *)type_specific_data);
-			break;
-		}
-		case MOTIONSENSE_TYPE_GYRO: {
-			init_gyro_cal(
-				&((struct gyro_cal_data *)type_specific_data)
-					 ->gyro_cal);
-			break;
-		}
-		default:
-			break;
-		}
-	}
-}
-
-bool online_calibration_has_new_values(void)
-{
-	bool has_dirty;
-
-	mutex_lock(&g_calib_cache_mutex);
-	has_dirty = sensor_calib_cache_dirty_map != 0;
-	mutex_unlock(&g_calib_cache_mutex);
-
-	return has_dirty;
-}
-
-bool online_calibration_read(struct motion_sensor_t *sensor,
-			     struct ec_response_online_calibration_data *out)
-{
-	int sensor_num = sensor - motion_sensors;
-	bool has_valid;
-
-	mutex_lock(&g_calib_cache_mutex);
-	has_valid = (sensor_calib_cache_valid_map & BIT(sensor_num)) != 0;
-	if (has_valid) {
-		/* Update data in out */
-		memcpy(out->data, sensor->online_calib_data->cache,
-		       sizeof(out->data));
-		/* Clear dirty bit */
-		sensor_calib_cache_dirty_map &= ~(1 << sensor_num);
-	}
-	mutex_unlock(&g_calib_cache_mutex);
-
-	return has_valid;
-}
-
-int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
-				    struct motion_sensor_t *sensor,
-				    uint32_t timestamp)
-{
-	int sensor_num = sensor - motion_sensors;
-	int rc;
-	int temperature;
-	struct online_calib_data *calib_data;
-	fpv3_t fdata;
-	bool is_spoofed = IS_ENABLED(CONFIG_ONLINE_CALIB_SPOOF_MODE) &&
-			  (sensor->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE);
-	bool has_new_calibration_values = false;
-
-	/* Convert data to fp. */
-	data_int16_to_fp(sensor, data->data, fdata);
-
-	calib_data = sensor->online_calib_data;
-	switch (sensor->type) {
-	case MOTIONSENSE_TYPE_ACCEL: {
-		struct accel_cal *cal =
-			(struct accel_cal *)(calib_data->type_specific_data);
-
-		if (is_spoofed) {
-			/* Copy the data to the calibration result. */
-			cal->bias[X] = fdata[X];
-			cal->bias[Y] = fdata[Y];
-			cal->bias[Z] = fdata[Z];
-			has_new_calibration_values = true;
-		} else {
-			/* Possibly update the gyroscope calibration. */
-			update_gyro_cal(sensor, fdata, timestamp);
-
-			/*
-			 * Temperature is required for accelerometer
-			 * calibration.
-			 */
-			rc = get_temperature(sensor, &temperature);
-			if (rc != EC_SUCCESS)
-				return rc;
-
-			has_new_calibration_values = accel_cal_accumulate(
-				cal, timestamp, fdata[X], fdata[Y], fdata[Z],
-				temperature);
-		}
-
-		if (has_new_calibration_values) {
-			mutex_lock(&g_calib_cache_mutex);
-			/* Convert result to the right scale. */
-			data_fp_to_int16(sensor, cal->bias, calib_data->cache);
-			/* Set valid and dirty. */
-			sensor_calib_cache_valid_map |= BIT(sensor_num);
-			sensor_calib_cache_dirty_map |= BIT(sensor_num);
-			mutex_unlock(&g_calib_cache_mutex);
-			/* Notify the AP. */
-			mkbp_send_event(EC_MKBP_EVENT_ONLINE_CALIBRATION);
-		}
-		break;
-	}
-	case MOTIONSENSE_TYPE_MAG: {
-		struct mag_cal_t *cal =
-			(struct mag_cal_t *)(calib_data->type_specific_data);
-		int idata[] = {
-			(int)data->data[X],
-			(int)data->data[Y],
-			(int)data->data[Z],
-		};
-
-		if (is_spoofed) {
-			/* Copy the data to the calibration result. */
-			cal->bias[X] = INT_TO_FP(idata[X]);
-			cal->bias[Y] = INT_TO_FP(idata[Y]);
-			cal->bias[Z] = INT_TO_FP(idata[Z]);
-			has_new_calibration_values = true;
-		} else {
-			/* Possibly update the gyroscope calibration. */
-			update_gyro_cal(sensor, fdata, timestamp);
-
-			has_new_calibration_values = mag_cal_update(cal, idata);
-		}
-
-		if (has_new_calibration_values) {
-			mutex_lock(&g_calib_cache_mutex);
-			/* Copy the values */
-			calib_data->cache[X] = cal->bias[X];
-			calib_data->cache[Y] = cal->bias[Y];
-			calib_data->cache[Z] = cal->bias[Z];
-			/* Set valid and dirty. */
-			sensor_calib_cache_valid_map |= BIT(sensor_num);
-			sensor_calib_cache_dirty_map |= BIT(sensor_num);
-			mutex_unlock(&g_calib_cache_mutex);
-			/* Notify the AP. */
-			mkbp_send_event(EC_MKBP_EVENT_ONLINE_CALIBRATION);
-		}
-		break;
-	}
-	case MOTIONSENSE_TYPE_GYRO: {
-		if (is_spoofed) {
-			/*
-			 * Gyroscope uses fdata to store the calibration
-			 * result, so there's no need to copy anything.
-			 */
-			has_new_calibration_values = true;
-		} else {
-			struct gyro_cal_data *gyro_cal_data =
-				(struct gyro_cal_data *)
-					calib_data->type_specific_data;
-			struct gyro_cal *gyro_cal = &gyro_cal_data->gyro_cal;
-
-			/* Temperature is required for gyro calibration. */
-			rc = get_temperature(sensor, &temperature);
-			if (rc != EC_SUCCESS)
-				return rc;
-
-			/* Update gyroscope calibration. */
-			gyro_cal_update_gyro(gyro_cal, timestamp, fdata[X],
-					     fdata[Y], fdata[Z], temperature);
-			has_new_calibration_values =
-				check_gyro_cal_new_bias(sensor, fdata);
-		}
-
-		if (has_new_calibration_values)
-			set_gyro_cal_cache_values(sensor, fdata);
-		break;
-	}
-	default:
-		break;
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/common/pd_log.c b/common/pd_log.c
deleted file mode 100644
index 3708aad72e..0000000000
--- a/common/pd_log.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "console.h"
-#include "event_log.h"
-#include "host_command.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/*
- * Ensure PD logging parameters are compatible with the generic logging
- * framework that we're calling into.
- */
-BUILD_ASSERT(sizeof(struct ec_response_pd_log) ==
-	     sizeof(struct event_log_entry));
-BUILD_ASSERT(PD_LOG_SIZE_MASK == EVENT_LOG_SIZE_MASK);
-BUILD_ASSERT(PD_LOG_TIMESTAMP_SHIFT == EVENT_LOG_TIMESTAMP_SHIFT);
-BUILD_ASSERT(PD_EVENT_NO_ENTRY == EVENT_LOG_NO_ENTRY);
-
-void pd_log_event(uint8_t type, uint8_t size_port,
-		  uint16_t data, void *payload)
-{
-	uint32_t timestamp = get_time().val >> PD_LOG_TIMESTAMP_SHIFT;
-
-	log_add_event(type, size_port, data, payload, timestamp);
-}
-
-#ifdef HAS_TASK_HOSTCMD
-
-/* number of accessory entries we have queued since last check */
-static volatile int incoming_logs;
-
-void pd_log_recv_vdm(int port, int cnt, uint32_t *payload)
-{
-	struct ec_response_pd_log *r = (void *)&payload[1];
-	/* update port number from MCU point of view */
-	size_t size = PD_LOG_SIZE(r->size_port);
-	uint8_t size_port = PD_LOG_PORT_SIZE(port, size);
-	uint32_t timestamp;
-
-	if ((cnt < 2 + DIV_ROUND_UP(size, sizeof(uint32_t))) ||
-	    !(payload[0] & VDO_SRC_RESPONDER))
-		/* Not a proper log entry, bail out */
-		return;
-
-	if (r->type != PD_EVENT_NO_ENTRY) {
-		timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT)
-			  - r->timestamp;
-		log_add_event(r->type, size_port, r->data, r->payload,
-			      timestamp);
-		/* record that we have enqueued new content */
-		incoming_logs++;
-	}
-}
-
-/* we are a PD MCU/EC, send back the events to the host */
-static enum ec_status hc_pd_get_log_entry(struct host_cmd_handler_args *args)
-{
-	struct ec_response_pd_log *r = args->response;
-
-dequeue_retry:
-	args->response_size = log_dequeue_event((struct event_log_entry *)r);
-	/* if the MCU log no longer has entries, try connected accessories */
-	if (r->type == PD_EVENT_NO_ENTRY) {
-		int i, res;
-		incoming_logs = 0;
-		for (i = 0; i < board_get_usb_pd_port_count(); ++i) {
-			/* only accessories who knows Google logging format */
-			if (pd_get_identity_vid(i) != USB_VID_GOOGLE)
-				continue;
-			res = pd_fetch_acc_log_entry(i);
-			if (res == EC_RES_BUSY) /* host should retry */
-				return EC_RES_BUSY;
-		}
-		/* we have received new entries from an accessory */
-		if (incoming_logs)
-			goto dequeue_retry;
-		/* else the current entry is already "PD_EVENT_NO_ENTRY" */
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY,
-		     hc_pd_get_log_entry,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pd_write_log_entry *p = args->params;
-	uint8_t type = p->type;
-	uint8_t port = p->port;
-
-	if (type < PD_EVENT_MCU_BASE || type >= PD_EVENT_ACC_BASE)
-		return EC_RES_INVALID_PARAM;
-	if (port > 0 && port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	switch (type) {
-	/* Charge event: Log data for all ports */
-	case PD_EVENT_MCU_CHARGE:
-#ifdef CONFIG_CHARGE_MANAGER
-		charge_manager_save_log(port);
-#endif
-		break;
-
-	/* Other events: no extra data, just log event type + port */
-	case PD_EVENT_MCU_CONNECT:
-	case PD_EVENT_MCU_BOARD_CUSTOM:
-	default:
-		pd_log_event(type, PD_LOG_PORT_SIZE(port, 0), 0, NULL);
-		break;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY,
-		     hc_pd_write_log_entry,
-		     EC_VER_MASK(0));
-#else /* !HAS_TASK_HOSTCMD */
-/* we are a PD accessory, send back the events as a VDM (VDO_CMD_GET_LOG) */
-int pd_vdm_get_log_entry(uint32_t *payload)
-{
-	struct ec_response_pd_log *r = (void *)&payload[1];
-	int byte_size;
-
-	byte_size = log_dequeue_event((struct event_log_entry *)r);
-
-	return 1 + DIV_ROUND_UP(byte_size, sizeof(uint32_t));
-}
-#endif /* !HAS_TASK_HOSTCMD */
diff --git a/common/peci.c b/common/peci.c
deleted file mode 100644
index e0f03c95dd..0000000000
--- a/common/peci.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI interface for Chrome EC */
-
-#include "chipset.h"
-#include "console.h"
-#include "peci.h"
-#include "util.h"
-
-static int peci_get_cpu_temp(int *cpu_temp)
-{
-	int rv;
-	uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = {0};
-	struct peci_data peci = {
-		.cmd_code = PECI_CMD_GET_TEMP,
-		.addr = PECI_TARGET_ADDRESS,
-		.w_len = PECI_GET_TEMP_WRITE_LENGTH,
-		.r_len = PECI_GET_TEMP_READ_LENGTH,
-		.w_buf = NULL,
-		.r_buf = r_buf,
-		.timeout_us = PECI_GET_TEMP_TIMEOUT_US,
-	};
-
-	rv = peci_transaction(&peci);
-	if (rv)
-		return rv;
-
-	/* Get relative raw data of temperature. */
-	*cpu_temp = (r_buf[1] << 8) | r_buf[0];
-
-	/* Convert relative raw data to degrees C. */
-	*cpu_temp = ((*cpu_temp ^ 0xFFFF) + 1) >> 6;
-
-	/*
-	 * When the AP transitions into S0, it is possible, depending on the
-	 * timing of the PECI sample, to read an invalid temperature. This is
-	 * very rare, but when it does happen the temperature returned is
-	 * greater than or equal to CONFIG_PECI_TJMAX.
-	 */
-	if (*cpu_temp >= CONFIG_PECI_TJMAX)
-		return EC_ERROR_UNKNOWN;
-
-	/* temperature in K */
-	*cpu_temp = CONFIG_PECI_TJMAX - *cpu_temp + 273;
-
-	return EC_SUCCESS;
-}
-
-int peci_temp_sensor_get_val(int idx, int *temp_ptr)
-{
-	int i, rv;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_STANDBY))
-		return EC_ERROR_NOT_POWERED;
-
-	/*
-	 * Retry reading PECI CPU temperature if the first sample is
-	 * invalid or failed to obtain.
-	 */
-	for (i = 0; i < 2; i++) {
-		rv = peci_get_cpu_temp(temp_ptr);
-		if (!rv)
-			break;
-	}
-
-	return rv;
-}
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_PECI
-static int peci_cmd(int argc, char **argv)
-{
-	uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = {0};
-	uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = {0};
-	struct peci_data peci = {
-		.w_buf = w_buf,
-		.r_buf = r_buf,
-	};
-
-	int param;
-	char *e;
-
-	if ((argc < 6) || (argc > 8))
-		return EC_ERROR_PARAM_COUNT;
-
-	peci.addr = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	peci.w_len = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	peci.r_len = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	peci.cmd_code = strtoi(argv[4], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM4;
-
-	peci.timeout_us = strtoi(argv[5], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM5;
-
-	if (argc > 6) {
-		param = strtoi(argv[6], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM6;
-
-		/* MSB of parameter */
-		w_buf[3] = (uint8_t)(param >> 24);
-		/* LSB of parameter */
-		w_buf[2] = (uint8_t)(param >> 16);
-		/* Index */
-		w_buf[1] = (uint8_t)(param >> 8);
-		/* Host ID[7:1] & Retry[0] */
-		w_buf[0] = (uint8_t)(param >> 0);
-
-		if (argc > 7) {
-			param = strtoi(argv[7], &e, 0);
-			if (*e)
-				return EC_ERROR_PARAM7;
-
-			/* Data (1, 2 or 4 bytes) */
-			w_buf[7] = (uint8_t)(param >> 24);
-			w_buf[6] = (uint8_t)(param >> 16);
-			w_buf[5] = (uint8_t)(param >> 8);
-			w_buf[4] = (uint8_t)(param >> 0);
-		}
-	} else {
-		peci.w_len = 0x00;
-	}
-
-	if (peci_transaction(&peci)) {
-		ccprintf("PECI transaction error\n");
-		return EC_ERROR_UNKNOWN;
-	}
-	ccprintf("PECI read data: %ph\n", HEX_BUF(r_buf, peci.r_len));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(peci, peci_cmd,
-			"addr wlen rlen cmd timeout(us)",
-			"PECI command");
-
-static int command_peci_temp(int argc, char **argv)
-{
-	int t;
-
-	if (peci_get_cpu_temp(&t) != EC_SUCCESS) {
-		ccprintf("PECI get cpu temp error\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	ccprintf("CPU temp: %d K, %d C\n", t, K_TO_C(t));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
-			"Print CPU temperature");
-#endif /* CONFIG_CMD_PECI */
diff --git a/common/peripheral_charger.c b/common/peripheral_charger.c
deleted file mode 100644
index 0a597ad6bd..0000000000
--- a/common/peripheral_charger.c
+++ /dev/null
@@ -1,740 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "chipset.h"
-#include "common.h"
-#include "device_event.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "peripheral_charger.h"
-#include "queue.h"
-#include "stdbool.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Peripheral Charge Manager */
-
-#define CPRINTS(fmt, args...) cprints(CC_PCHG, "PCHG: " fmt, ##args)
-
-/* Currently only used for FW update. */
-static uint32_t pchg_host_events;
-
-static void pchg_queue_event(struct pchg *ctx, enum pchg_event event)
-{
-	mutex_lock(&ctx->mtx);
-	if (queue_add_unit(&ctx->events, &event) == 0) {
-		ctx->dropped_event_count++;
-		CPRINTS("ERR: Queue is full");
-	}
-	mutex_unlock(&ctx->mtx);
-}
-
-static void _send_host_event(const struct pchg *ctx, uint32_t event)
-{
-	int port = PCHG_CTX_TO_PORT(ctx);
-
-	atomic_or(&pchg_host_events, event | port << EC_MKBP_PCHG_PORT_SHIFT);
-	mkbp_send_event(EC_MKBP_EVENT_PCHG);
-}
-
-static const char *_text_state(enum pchg_state state)
-{
-	/* TODO: Use "S%d" for normal build. */
-	static const char * const state_names[] = EC_PCHG_STATE_TEXT;
-	BUILD_ASSERT(ARRAY_SIZE(state_names) == PCHG_STATE_COUNT);
-
-	if (state >= sizeof(state_names))
-		return "UNDEF";
-
-	return state_names[state];
-}
-
-static const char *_text_event(enum pchg_event event)
-{
-	/* TODO: Use "S%d" for normal build. */
-	static const char * const event_names[] = {
-		[PCHG_EVENT_NONE] = "NONE",
-		[PCHG_EVENT_IRQ] = "IRQ",
-		[PCHG_EVENT_RESET] = "RESET",
-		[PCHG_EVENT_INITIALIZED] = "INITIALIZED",
-		[PCHG_EVENT_ENABLED] = "ENABLED",
-		[PCHG_EVENT_DISABLED] = "DISABLED",
-		[PCHG_EVENT_DEVICE_DETECTED] = "DEVICE_DETECTED",
-		[PCHG_EVENT_DEVICE_CONNECTED] = "DEVICE_CONNECTED",
-		[PCHG_EVENT_DEVICE_LOST] = "DEVICE_LOST",
-		[PCHG_EVENT_CHARGE_STARTED] = "CHARGE_STARTED",
-		[PCHG_EVENT_CHARGE_UPDATE] = "CHARGE_UPDATE",
-		[PCHG_EVENT_CHARGE_ENDED] = "CHARGE_ENDED",
-		[PCHG_EVENT_CHARGE_STOPPED] = "CHARGE_STOPPED",
-		[PCHG_EVENT_UPDATE_OPENED] = "UPDATE_OPENED",
-		[PCHG_EVENT_UPDATE_CLOSED] = "UPDATE_CLOSED",
-		[PCHG_EVENT_UPDATE_WRITTEN] = "UPDATE_WRITTEN",
-		[PCHG_EVENT_IN_NORMAL] = "IN_NORMAL",
-		[PCHG_EVENT_CHARGE_ERROR] = "CHARGE_ERROR",
-		[PCHG_EVENT_UPDATE_ERROR] = "UPDATE_ERROR",
-		[PCHG_EVENT_OTHER_ERROR] = "OTHER_ERROR",
-		[PCHG_EVENT_ENABLE] = "ENABLE",
-		[PCHG_EVENT_DISABLE] = "DISABLE",
-		[PCHG_EVENT_UPDATE_OPEN] = "UPDATE_OPEN",
-		[PCHG_EVENT_UPDATE_WRITE] = "UPDATE_WRITE",
-		[PCHG_EVENT_UPDATE_CLOSE] = "UPDATE_CLOSE",
-	};
-	BUILD_ASSERT(ARRAY_SIZE(event_names) == PCHG_EVENT_COUNT);
-
-	if (event >= sizeof(event_names))
-		return "UNDEF";
-
-	return event_names[event];
-}
-
-static void _clear_port(struct pchg *ctx)
-{
-	mutex_lock(&ctx->mtx);
-	queue_init(&ctx->events);
-	mutex_unlock(&ctx->mtx);
-	atomic_clear(&ctx->irq);
-	ctx->battery_percent = 0;
-	ctx->error = 0;
-	ctx->update.data_ready = 0;
-}
-
-static enum pchg_state pchg_reset(struct pchg *ctx)
-{
-	enum pchg_state state = PCHG_STATE_RESET;
-	int rv;
-
-	/*
-	 * In case we get asynchronous reset, clear port though it's redundant
-	 * for a synchronous reset.
-	 */
-	_clear_port(ctx);
-
-	if (ctx->mode == PCHG_MODE_NORMAL) {
-		rv = ctx->cfg->drv->init(ctx);
-		if (rv == EC_SUCCESS) {
-			state = PCHG_STATE_INITIALIZED;
-			pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
-		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
-			CPRINTS("ERR: Failed to reset to normal mode");
-		}
-	} else {
-		state = PCHG_STATE_DOWNLOAD;
-		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_OPEN);
-	}
-
-	return state;
-}
-
-static void pchg_state_reset(struct pchg *ctx)
-{
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_IN_NORMAL:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_initialized(struct pchg *ctx)
-{
-	int rv;
-
-	if (ctx->event == PCHG_EVENT_ENABLE)
-		ctx->error &= ~PCHG_ERROR_HOST;
-
-	/* Spin in INITIALIZED until error condition is cleared. */
-	if (ctx->error)
-		return;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_ENABLE:
-		rv = ctx->cfg->drv->enable(ctx, true);
-		if (rv == EC_SUCCESS)
-			ctx->state = PCHG_STATE_ENABLED;
-		else if (rv != EC_SUCCESS_IN_PROGRESS)
-			CPRINTS("ERR: Failed to enable");
-		break;
-	case PCHG_EVENT_ENABLED:
-		ctx->state = PCHG_STATE_ENABLED;
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_enabled(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_DISABLE:
-		ctx->error |= PCHG_ERROR_HOST;
-		rv = ctx->cfg->drv->enable(ctx, false);
-		if (rv == EC_SUCCESS)
-			ctx->state = PCHG_STATE_INITIALIZED;
-		else if (rv != EC_SUCCESS_IN_PROGRESS)
-			CPRINTS("ERR: Failed to disable");
-		break;
-	case PCHG_EVENT_DISABLED:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	case PCHG_EVENT_DEVICE_DETECTED:
-		ctx->state = PCHG_STATE_DETECTED;
-		break;
-	case PCHG_EVENT_DEVICE_CONNECTED:
-		/*
-		 * Proactively query SOC in case charging info won't be sent
-		 * because device is already charged.
-		 */
-		ctx->cfg->drv->get_soc(ctx);
-		ctx->state = PCHG_STATE_CONNECTED;
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_detected(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_DISABLE:
-		ctx->error |= PCHG_ERROR_HOST;
-		rv = ctx->cfg->drv->enable(ctx, false);
-		if (rv == EC_SUCCESS)
-			ctx->state = PCHG_STATE_INITIALIZED;
-		else if (rv != EC_SUCCESS_IN_PROGRESS)
-			CPRINTS("ERR: Failed to disable");
-		break;
-	case PCHG_EVENT_DISABLED:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	case PCHG_EVENT_DEVICE_CONNECTED:
-		/*
-		 * Proactively query SOC in case charging info won't be sent
-		 * because device is already charged.
-		 */
-		ctx->cfg->drv->get_soc(ctx);
-		ctx->state = PCHG_STATE_CONNECTED;
-		break;
-	case PCHG_EVENT_DEVICE_LOST:
-		ctx->battery_percent = 0;
-		ctx->state = PCHG_STATE_ENABLED;
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_connected(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_DISABLE:
-		ctx->error |= PCHG_ERROR_HOST;
-		rv = ctx->cfg->drv->enable(ctx, false);
-		if (rv == EC_SUCCESS)
-			ctx->state = PCHG_STATE_INITIALIZED;
-		else if (rv != EC_SUCCESS_IN_PROGRESS)
-			CPRINTS("ERR: Failed to disable");
-		break;
-	case PCHG_EVENT_DISABLED:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	case PCHG_EVENT_CHARGE_STARTED:
-		ctx->state = PCHG_STATE_CHARGING;
-		break;
-	case PCHG_EVENT_DEVICE_LOST:
-		ctx->battery_percent = 0;
-		ctx->state = PCHG_STATE_ENABLED;
-		break;
-	case PCHG_EVENT_CHARGE_ERROR:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_charging(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_DISABLE:
-		ctx->error |= PCHG_ERROR_HOST;
-		rv = ctx->cfg->drv->enable(ctx, false);
-		if (rv == EC_SUCCESS)
-			ctx->state = PCHG_STATE_INITIALIZED;
-		else if (rv != EC_SUCCESS_IN_PROGRESS)
-			CPRINTS("ERR: Failed to disable");
-		break;
-	case PCHG_EVENT_DISABLED:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	case PCHG_EVENT_CHARGE_UPDATE:
-		break;
-	case PCHG_EVENT_DEVICE_LOST:
-		ctx->battery_percent = 0;
-		ctx->state = PCHG_STATE_ENABLED;
-		break;
-	case PCHG_EVENT_CHARGE_ERROR:
-		ctx->state = PCHG_STATE_INITIALIZED;
-		break;
-	case PCHG_EVENT_CHARGE_ENDED:
-	case PCHG_EVENT_CHARGE_STOPPED:
-		ctx->state = PCHG_STATE_CONNECTED;
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_download(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_UPDATE_OPEN:
-		rv = ctx->cfg->drv->update_open(ctx);
-		if (rv == EC_SUCCESS) {
-			ctx->state = PCHG_STATE_DOWNLOADING;
-		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
-			_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
-			CPRINTS("ERR: Failed to open");
-		}
-		break;
-	case PCHG_EVENT_UPDATE_OPENED:
-		ctx->state = PCHG_STATE_DOWNLOADING;
-		_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_OPENED);
-		break;
-	case PCHG_EVENT_UPDATE_ERROR:
-		_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
-		break;
-	default:
-		break;
-	}
-}
-
-static void pchg_state_downloading(struct pchg *ctx)
-{
-	int rv;
-
-	switch (ctx->event) {
-	case PCHG_EVENT_RESET:
-		ctx->state = pchg_reset(ctx);
-		break;
-	case PCHG_EVENT_UPDATE_WRITE:
-		if (ctx->update.data_ready == 0)
-			break;
-		rv = ctx->cfg->drv->update_write(ctx);
-		if (rv != EC_SUCCESS && rv != EC_SUCCESS_IN_PROGRESS) {
-			_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
-			CPRINTS("ERR: Failed to write");
-		}
-		break;
-	case PCHG_EVENT_UPDATE_WRITTEN:
-		ctx->update.data_ready = 0;
-		_send_host_event(ctx, EC_MKBP_PCHG_WRITE_COMPLETE);
-		break;
-	case PCHG_EVENT_UPDATE_CLOSE:
-		rv = ctx->cfg->drv->update_close(ctx);
-		if (rv == EC_SUCCESS) {
-			ctx->state = PCHG_STATE_DOWNLOAD;
-		} else if (rv != EC_SUCCESS_IN_PROGRESS) {
-			_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
-			CPRINTS("ERR: Failed to close");
-		}
-		break;
-	case PCHG_EVENT_UPDATE_CLOSED:
-		ctx->state = PCHG_STATE_DOWNLOAD;
-		_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_CLOSED);
-		break;
-	case PCHG_EVENT_UPDATE_ERROR:
-		CPRINTS("ERR: Failed to update");
-		_send_host_event(ctx, EC_MKBP_PCHG_UPDATE_ERROR);
-		break;
-	default:
-		break;
-	}
-}
-
-static int pchg_run(struct pchg *ctx)
-{
-	enum pchg_state previous_state = ctx->state;
-	uint8_t previous_battery = ctx->battery_percent;
-	int port = PCHG_CTX_TO_PORT(ctx);
-	int rv;
-
-	mutex_lock(&ctx->mtx);
-	if (!queue_remove_unit(&ctx->events, &ctx->event)) {
-		mutex_unlock(&ctx->mtx);
-		CPRINTS("P%d No event in queue", port);
-		return 0;
-	}
-	mutex_unlock(&ctx->mtx);
-
-	CPRINTS("P%d Run in STATE_%s for EVENT_%s", port,
-		_text_state(ctx->state), _text_event(ctx->event));
-
-	if (ctx->event == PCHG_EVENT_IRQ) {
-		rv = ctx->cfg->drv->get_event(ctx);
-		if (rv) {
-			CPRINTS("ERR: Failed to get event (%d)", rv);
-			return 0;
-		}
-		CPRINTS("  EVENT_%s", _text_event(ctx->event));
-	}
-
-	if (ctx->event == PCHG_EVENT_NONE)
-		return 0;
-
-	switch (ctx->state) {
-	case PCHG_STATE_RESET:
-		pchg_state_reset(ctx);
-		break;
-	case PCHG_STATE_INITIALIZED:
-		pchg_state_initialized(ctx);
-		break;
-	case PCHG_STATE_ENABLED:
-		pchg_state_enabled(ctx);
-		break;
-	case PCHG_STATE_DETECTED:
-		pchg_state_detected(ctx);
-		break;
-	case PCHG_STATE_CONNECTED:
-		pchg_state_connected(ctx);
-		break;
-	case PCHG_STATE_CHARGING:
-		pchg_state_charging(ctx);
-		break;
-	case PCHG_STATE_DOWNLOAD:
-		pchg_state_download(ctx);
-		break;
-	case PCHG_STATE_DOWNLOADING:
-		pchg_state_downloading(ctx);
-		break;
-	default:
-		CPRINTS("ERR: Unknown state (%d)", ctx->state);
-		return 0;
-	}
-
-	if (previous_state != ctx->state)
-		CPRINTS("->STATE_%s", _text_state(ctx->state));
-
-	if (ctx->battery_percent != previous_battery)
-		CPRINTS("Battery %u%%", ctx->battery_percent);
-
-	/*
-	 * Notify the host of
-	 * - [S0] Charge update with SoC change and all other events.
-	 * - [S3/S0IX] Device attach or detach (for wake-up)
-	 * - [S5/G3] No events.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return 0;
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		return (ctx->event == PCHG_EVENT_DEVICE_DETECTED)
-			|| (ctx->event == PCHG_EVENT_DEVICE_LOST);
-
-	if (ctx->event == PCHG_EVENT_CHARGE_UPDATE)
-		return ctx->battery_percent != previous_battery;
-
-	return ctx->event != PCHG_EVENT_NONE;
-}
-
-void pchg_irq(enum gpio_signal signal)
-{
-	struct pchg *ctx;
-	int i;
-
-	for (i = 0; i < pchg_count; i++) {
-		ctx = &pchgs[i];
-		if (signal == ctx->cfg->irq_pin) {
-			ctx->irq = 1;
-			task_wake(TASK_ID_PCHG);
-			return;
-		}
-	}
-}
-
-
-static void pchg_suspend_complete(void)
-{
-	CPRINTS("%s", __func__);
-	device_enable_event(EC_DEVICE_EVENT_WLC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, pchg_suspend_complete,
-	     HOOK_PRIO_DEFAULT);
-
-static void pchg_startup(void)
-{
-	struct pchg *ctx;
-	int p;
-
-	CPRINTS("%s", __func__);
-
-	for (p = 0; p < pchg_count; p++) {
-		ctx = &pchgs[p];
-		_clear_port(ctx);
-		ctx->mode = PCHG_MODE_NORMAL;
-		ctx->cfg->drv->reset(ctx);
-		gpio_enable_interrupt(ctx->cfg->irq_pin);
-	}
-
-	task_wake(TASK_ID_PCHG);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pchg_startup, HOOK_PRIO_DEFAULT);
-
-static void pchg_shutdown(void)
-{
-	struct pchg *ctx;
-	int p;
-
-	CPRINTS("%s", __func__);
-
-	for (p = 0; p < pchg_count; p++) {
-		ctx = &pchgs[0];
-		gpio_disable_interrupt(ctx->cfg->irq_pin);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pchg_shutdown, HOOK_PRIO_DEFAULT);
-
-void pchg_task(void *u)
-{
-	struct pchg *ctx;
-	int p;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		/* We are here after power-on (because of late sysjump). */
-		pchg_startup();
-
-	while (true) {
-		/* Process pending events for all ports. */
-		int rv = 0;
-
-		for (p = 0; p < pchg_count; p++) {
-			ctx = &pchgs[p];
-			do {
-				if (atomic_clear(&ctx->irq))
-					pchg_queue_event(ctx, PCHG_EVENT_IRQ);
-				rv |= pchg_run(ctx);
-			} while (queue_count(&ctx->events));
-		}
-
-		/* Send one host event for all ports. */
-		if (rv)
-			device_set_single_event(EC_DEVICE_EVENT_WLC);
-
-		task_wait_event(-1);
-	}
-}
-
-static enum ec_status hc_pchg_count(struct host_cmd_handler_args *args)
-{
-	struct ec_response_pchg_count *r = args->response;
-
-	r->port_count = pchg_count;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PCHG_COUNT, hc_pchg_count, EC_VER_MASK(0));
-
-#define HCPRINTS(fmt, args...) cprints(CC_PCHG, "HC:PCHG: " fmt, ##args)
-
-static enum ec_status hc_pchg(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pchg *p = args->params;
-	struct ec_response_pchg *r = args->response;
-	int port = p->port;
-	struct pchg *ctx;
-
-	if (port >= pchg_count)
-		return EC_RES_INVALID_PARAM;
-
-	ctx = &pchgs[port];
-
-	if (ctx->state == PCHG_STATE_CONNECTED
-			&& ctx->battery_percent >= ctx->cfg->full_percent)
-		r->state = PCHG_STATE_FULL;
-	else
-		r->state = ctx->state;
-
-	r->battery_percentage = ctx->battery_percent;
-	r->error = ctx->error;
-	r->fw_version = ctx->fw_version;
-	r->dropped_event_count = ctx->dropped_event_count;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PCHG, hc_pchg, EC_VER_MASK(1));
-
-int pchg_get_next_event(uint8_t *out)
-{
-	uint32_t events = atomic_clear(&pchg_host_events);
-
-	memcpy(out, &events, sizeof(events));
-
-	return sizeof(events);
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_PCHG, pchg_get_next_event);
-
-static enum ec_status hc_pchg_update(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pchg_update *p = args->params;
-	struct ec_response_pchg_update *r = args->response;
-	int port = p->port;
-	struct pchg *ctx;
-
-	if (port >= pchg_count)
-		return EC_RES_INVALID_PARAM;
-
-	ctx = &pchgs[port];
-
-	switch (p->cmd) {
-	case EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL:
-		HCPRINTS("Resetting to normal mode");
-
-		gpio_disable_interrupt(ctx->cfg->irq_pin);
-		_clear_port(ctx);
-		ctx->mode = PCHG_MODE_NORMAL;
-		ctx->cfg->drv->reset(ctx);
-		gpio_enable_interrupt(ctx->cfg->irq_pin);
-		break;
-
-	case EC_PCHG_UPDATE_CMD_OPEN:
-		HCPRINTS("Resetting to download mode");
-
-		gpio_disable_interrupt(ctx->cfg->irq_pin);
-		_clear_port(ctx);
-		ctx->mode = PCHG_MODE_DOWNLOAD;
-		ctx->cfg->drv->reset(ctx);
-		gpio_enable_interrupt(ctx->cfg->irq_pin);
-
-		ctx->update.version = p->version;
-		r->block_size = ctx->cfg->block_size;
-		args->response_size = sizeof(*r);
-		break;
-
-	case EC_PCHG_UPDATE_CMD_WRITE:
-		if (ctx->state != PCHG_STATE_DOWNLOADING)
-			return EC_RES_ERROR;
-		if (p->size > sizeof(ctx->update.data))
-			return EC_RES_OVERFLOW;
-		if (ctx->update.data_ready)
-			return EC_RES_BUSY;
-
-		HCPRINTS("Writing %u bytes to 0x%x", p->size, p->addr);
-		ctx->update.addr = p->addr;
-		ctx->update.size = p->size;
-		memcpy(ctx->update.data, p->data, p->size);
-		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_WRITE);
-		ctx->update.data_ready = 1;
-		break;
-
-	case EC_PCHG_UPDATE_CMD_CLOSE:
-		if (ctx->state != PCHG_STATE_DOWNLOADING)
-			return EC_RES_ERROR;
-		if (ctx->update.data_ready)
-			return EC_RES_BUSY;
-
-		HCPRINTS("Closing update session (crc=0x%x)", p->crc32);
-		ctx->update.crc32 = p->crc32;
-		pchg_queue_event(ctx, PCHG_EVENT_UPDATE_CLOSE);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	task_wake(TASK_ID_PCHG);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PCHG_UPDATE, hc_pchg_update, EC_VER_MASK(0));
-
-static int cc_pchg(int argc, char **argv)
-{
-	int port;
-	char *end;
-	struct pchg *ctx;
-
-	if (argc < 2 || 4 < argc)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &end, 0);
-	if (*end || port < 0 || port >= pchg_count)
-		return EC_ERROR_PARAM1;
-	ctx = &pchgs[port];
-
-	if (argc == 2) {
-		ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n",
-			 port, _text_state(ctx->state), _text_event(ctx->event),
-			 ctx->battery_percent);
-		ccprintf("error=0x%x dropped=%u fw_version=0x%x\n",
-			 ctx->error, ctx->dropped_event_count, ctx->fw_version);
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[2], "reset")) {
-		if (argc == 3)
-			ctx->mode = PCHG_MODE_NORMAL;
-		else if (!strcasecmp(argv[3], "download"))
-			ctx->mode = PCHG_MODE_DOWNLOAD;
-		else
-			return EC_ERROR_PARAM3;
-		gpio_disable_interrupt(ctx->cfg->irq_pin);
-		_clear_port(ctx);
-		ctx->cfg->drv->reset(ctx);
-		gpio_enable_interrupt(ctx->cfg->irq_pin);
-	} else if (!strcasecmp(argv[2], "enable")) {
-		pchg_queue_event(ctx, PCHG_EVENT_ENABLE);
-	} else if (!strcasecmp(argv[2], "disable")) {
-		pchg_queue_event(ctx, PCHG_EVENT_DISABLE);
-	} else {
-		return EC_ERROR_PARAM2;
-	}
-
-	task_wake(TASK_ID_PCHG);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pchg, cc_pchg,
-			"\n\t<port>"
-			"\n\t<port> reset [download]"
-			"\n\t<port> enable"
-			"\n\t<port> disable",
-			"Control peripheral chargers");
diff --git a/common/port80.c b/common/port80.c
deleted file mode 100644
index ab1f112112..0000000000
--- a/common/port80.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "display_7seg.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "port80.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ## args)
-
-#ifdef CONFIG_PORT80_4_BYTE
-typedef uint32_t port80_code_t;
-#else
-typedef uint16_t port80_code_t;
-#endif
-static port80_code_t __bss_slow history[CONFIG_PORT80_HISTORY_LEN];
-static int __bss_slow writes;    /* Number of port 80 writes so far */
-static uint16_t last_boot; /* Last code from previous boot */
-static int __bss_slow scroll;
-
-#ifdef CONFIG_BRINGUP
-#undef CONFIG_PORT80_PRINT_IN_INT
-#define CONFIG_PORT80_PRINT_IN_INT 1
-#endif
-
-static int print_in_int = CONFIG_PORT80_PRINT_IN_INT;
-
-static void port80_dump_buffer(void);
-DECLARE_DEFERRED(port80_dump_buffer);
-
-void port_80_write(int data)
-{
-	/*
-	 * By default print_in_int is disabled if:
-	 * 1. CONFIG_BRINGUP is not defined
-	 * 2. CONFIG_PRINT_IN_INT is set to disable by default
-	 *
-	 * This is done to prevent printing in interrupt context. Boards can
-	 * enable this by either defining CONFIG_BRINGUP or enabling
-	 * CONFIG_PRINT_IN_INT in board configs.
-	 *
-	 * If at runtime, print_in_int is disabled, then this function will
-	 * schedule a deferred call 4 seconds after the last port80 write to
-	 * dump the current port80 buffer to EC console. This is to allow
-	 * developers to help debug BIOS progress by tracing port80 messages.
-	 */
-	if (print_in_int)
-		CPRINTF("%c[%pT Port 80: 0x%02x]",
-			scroll ? '\n' : '\r', PRINTF_TIMESTAMP_NOW, data);
-
-	hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND);
-
-	/* Save current port80 code if system is resetting */
-	if (data == PORT_80_EVENT_RESET && writes) {
-		port80_code_t prev = history[(writes-1) % ARRAY_SIZE(history)];
-
-		/*
-		 * last_boot only reports 8-bit codes.
-		 * Ignore special event codes and 4-byte codes.
-		 */
-		if (prev < 0x100)
-			last_boot = prev;
-	}
-
-	history[writes % ARRAY_SIZE(history)] = data;
-	writes++;
-}
-
-static void port80_dump_buffer(void)
-{
-	int printed = 0;
-	int i;
-	int head, tail;
-	int last_e = 0;
-
-	/*
-	 * Print the port 80 writes so far, clipped to the length of our
-	 * history buffer.
-	 *
-	 * Technically, if a port 80 write comes in while we're printing this,
-	 * we could print an incorrect history.  Probably not worth the
-	 * complexity to work around that.
-	 */
-	head = writes;
-	if (head > ARRAY_SIZE(history))
-		tail = head - ARRAY_SIZE(history);
-	else
-		tail = 0;
-
-	ccputs("Port 80 writes:");
-	for (i = tail; i < head; i++) {
-		int e = history[i % ARRAY_SIZE(history)];
-		switch (e) {
-		case PORT_80_EVENT_RESUME:
-			ccprintf("\n(S3->S0)");
-			printed = 0;
-			break;
-		case PORT_80_EVENT_RESET:
-			ccprintf("\n(RESET)");
-			printed = 0;
-			break;
-		default:
-			if (!(printed++ % 20)) {
-				ccputs("\n ");
-				cflush();
-			}
-			ccprintf(" %02x", e);
-			last_e = e;
-		}
-	}
-	ccputs(" <--new\n");
-
-	/* Displaying last port80 msg on 7-segment if it is enabled */
-	if (IS_ENABLED(CONFIG_SEVEN_SEG_DISPLAY) && last_e)
-		display_7seg_write(SEVEN_SEG_PORT80_DISPLAY, last_e);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_port80(int argc, char **argv)
-{
-	/*
-	 * 'port80 scroll' toggles whether port 80 output begins with a newline
-	 * (scrolling) or CR (non-scrolling).
-	 */
-	if (argc > 1) {
-		if (!strcasecmp(argv[1], "scroll")) {
-			scroll = !scroll;
-			ccprintf("scroll %sabled\n", scroll ? "en" : "dis");
-			return EC_SUCCESS;
-		} else if (!strcasecmp(argv[1], "intprint")) {
-			print_in_int = !print_in_int;
-			ccprintf("printing in interrupt %sabled\n",
-				 print_in_int ? "en" : "dis");
-			return EC_SUCCESS;
-		} else if (!strcasecmp(argv[1], "flush")) {
-			writes = 0;
-			return EC_SUCCESS;
-		} else {
-			return EC_ERROR_PARAM1;
-		}
-	}
-
-	port80_dump_buffer();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(port80, command_port80,
-			"[scroll | intprint | flush]",
-			"Print port80 writes or toggle port80 scrolling");
-
-enum ec_status port80_last_boot(struct host_cmd_handler_args *args)
-{
-	struct ec_response_port80_last_boot *r = args->response;
-
-	args->response_size = sizeof(*r);
-	r->code = last_boot;
-
-	return EC_RES_SUCCESS;
-}
-
-enum ec_status port80_command_read(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_port80_read *p = args->params;
-	uint32_t offset = p->read_buffer.offset;
-	uint32_t entries = p->read_buffer.num_entries;
-	int i;
-	struct ec_response_port80_read *rsp = args->response;
-
-	if (args->version == 0)
-		return port80_last_boot(args);
-
-	if (p->subcmd == EC_PORT80_GET_INFO) {
-		rsp->get_info.writes = writes;
-		rsp->get_info.history_size = ARRAY_SIZE(history);
-		args->response_size = sizeof(rsp->get_info);
-		return EC_RES_SUCCESS;
-	} else if (p->subcmd == EC_PORT80_READ_BUFFER) {
-		/* do not allow bad offset or size */
-		if (offset >= ARRAY_SIZE(history) || entries == 0 ||
-			entries > args->response_max)
-			return EC_RES_INVALID_PARAM;
-
-		for (i = 0; i < entries; i++) {
-			uint16_t e = history[(i + offset) %
-				ARRAY_SIZE(history)];
-			rsp->data.codes[i] = e;
-		}
-
-		args->response_size = entries*sizeof(uint16_t);
-		return EC_RES_SUCCESS;
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ,
-		port80_command_read,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static void port80_log_resume(void)
-{
-	/* Store port 80 event so we know where resume happened */
-	port_80_write(PORT_80_EVENT_RESUME);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, port80_log_resume, HOOK_PRIO_DEFAULT);
diff --git a/common/power_button.c b/common/power_button.c
deleted file mode 100644
index 1ac3893492..0000000000
--- a/common/power_button.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power button module for Chrome EC */
-
-#include "button.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
-
-/* By default the power button is active low */
-#ifndef CONFIG_POWER_BUTTON_FLAGS
-#define CONFIG_POWER_BUTTON_FLAGS 0
-#endif
-
-static int debounced_power_pressed;	/* Debounced power button state */
-static int simulate_power_pressed;
-static volatile int power_button_is_stable = 1;
-
-static const struct button_config power_button = {
-	.name = "power button",
-	.gpio = GPIO_POWER_BUTTON_L,
-	.debounce_us = BUTTON_DEBOUNCE_US,
-	.flags = CONFIG_POWER_BUTTON_FLAGS,
-};
-
-int power_button_signal_asserted(void)
-{
-	return !!(gpio_get_level(power_button.gpio)
-		== (power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ? 1 : 0);
-}
-
-/**
- * Get raw power button signal state.
- *
- * @return 1 if power button is pressed, 0 if not pressed.
- */
-static int raw_power_button_pressed(void)
-{
-	if (simulate_power_pressed)
-		return 1;
-
-#ifndef CONFIG_POWER_BUTTON_IGNORE_LID
-	/*
-	 * Always indicate power button released if the lid is closed.
-	 * This prevents waking the system if the device is squashed enough to
-	 * press the power button through the closed lid.
-	 */
-	if (!lid_is_open())
-		return 0;
-#endif
-
-	return power_button_signal_asserted();
-}
-
-int power_button_is_pressed(void)
-{
-	return debounced_power_pressed;
-}
-
-int power_button_wait_for_release(int timeout_us)
-{
-	timestamp_t deadline;
-	timestamp_t now = get_time();
-
-	deadline.val = now.val + timeout_us;
-
-	while (!power_button_is_stable || power_button_is_pressed()) {
-		now = get_time();
-		if (timeout_us >= 0 && timestamp_expired(deadline, &now)) {
-			CPRINTS("%s not released in time", power_button.name);
-			return EC_ERROR_TIMEOUT;
-		}
-		/*
-		 * We use task_wait_event() instead of usleep() here. It will
-		 * be woken up immediately if the power button is debouned and
-		 * changed. However, it is not guaranteed, like the cases that
-		 * the power button is debounced but not changed, or the power
-		 * button has not been debounced.
-		 */
-		task_wait_event(MIN(power_button.debounce_us,
-				    deadline.val - now.val));
-	}
-
-	CPRINTS("%s released in time", power_button.name);
-	return EC_SUCCESS;
-}
-
-/**
- * Handle power button initialization.
- */
-static void power_button_init(void)
-{
-	if (raw_power_button_pressed())
-		debounced_power_pressed = 1;
-
-	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(power_button.gpio);
-}
-DECLARE_HOOK(HOOK_INIT, power_button_init, HOOK_PRIO_INIT_POWER_BUTTON);
-
-#ifdef CONFIG_POWER_BUTTON_INIT_IDLE
-/*
- * Set/clear AP_IDLE flag. It's set when the system gracefully shuts down and
- * it's cleared when the system boots up. The result is the system tries to
- * go back to the previous state upon AC plug-in. If the system uncleanly
- * shuts down, it boots immediately. If the system shuts down gracefully,
- * it'll stay at S5 and wait for power button press.
- */
-static void pb_chipset_startup(void)
-{
-	chip_save_reset_flags(chip_read_reset_flags() & ~EC_RESET_FLAG_AP_IDLE);
-	system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE);
-	CPRINTS("Cleared AP_IDLE flag");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pb_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void pb_chipset_shutdown(void)
-{
-	chip_save_reset_flags(chip_read_reset_flags() | EC_RESET_FLAG_AP_IDLE);
-	system_set_reset_flags(EC_RESET_FLAG_AP_IDLE);
-	CPRINTS("Saved AP_IDLE flag");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pb_chipset_shutdown,
-	     /*
-	      * Slightly higher than handle_pending_reboot because
-	      * it may clear AP_IDLE flag.
-	      */
-	     HOOK_PRIO_DEFAULT - 1);
-#endif
-
-/**
- * Handle debounced power button changing state.
- */
-static void power_button_change_deferred(void)
-{
-	const int new_pressed = raw_power_button_pressed();
-
-	/* Re-enable keyboard scanning if power button is no longer pressed */
-	if (!new_pressed)
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_POWER_BUTTON);
-
-	/* If power button hasn't changed state, nothing to do */
-	if (new_pressed == debounced_power_pressed) {
-		power_button_is_stable = 1;
-		return;
-	}
-
-	debounced_power_pressed = new_pressed;
-	power_button_is_stable = 1;
-
-	CPRINTS("%s %s",
-		power_button.name, new_pressed ? "pressed" : "released");
-
-	/* Call hooks */
-	hook_notify(HOOK_POWER_BUTTON_CHANGE);
-
-	/* Notify host if power button has been pressed */
-	if (new_pressed)
-		host_set_single_event(EC_HOST_EVENT_POWER_BUTTON);
-}
-DECLARE_DEFERRED(power_button_change_deferred);
-
-void power_button_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * If power button is pressed, disable the matrix scan as soon as
-	 * possible to reduce the risk of false-reboot triggered by those keys
-	 * on the same column with refresh key.
-	 */
-	if (raw_power_button_pressed())
-		keyboard_scan_enable(0, KB_SCAN_DISABLE_POWER_BUTTON);
-
-	/* Reset power button debounce time */
-	power_button_is_stable = 0;
-	hook_call_deferred(&power_button_change_deferred_data,
-			   power_button.debounce_us);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_powerbtn(int argc, char **argv)
-{
-	int ms = 200;  /* Press duration in ms */
-	char *e;
-
-	if (argc > 1) {
-		ms = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Simulating %d ms %s press.\n", ms, power_button.name);
-	simulate_power_pressed = 1;
-	power_button_is_stable = 0;
-	hook_call_deferred(&power_button_change_deferred_data, 0);
-
-	if (ms > 0)
-		msleep(ms);
-
-	ccprintf("Simulating %s release.\n", power_button.name);
-	simulate_power_pressed = 0;
-	power_button_is_stable = 0;
-	hook_call_deferred(&power_button_change_deferred_data, 0);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn,
-			"[msec]",
-			"Simulate power button press");
-
diff --git a/common/power_button_x86.c b/common/power_button_x86.c
deleted file mode 100644
index 661f9b2a3d..0000000000
--- a/common/power_button_x86.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power button state machine for x86 platforms */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "switch.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
-
-/*
- * x86 chipsets have a hardware timer on the power button input which causes
- * them to reset when the button is pressed for more than 4 seconds.  This is
- * problematic for Chrome OS, which needs more time than that to transition
- * through the lock and logout screens.  So when the system is on, we need to
- * stretch the power button signal so that the chipset will hard-reboot after 8
- * seconds instead of 4.
- *
- * When the button is pressed, we initially send a short pulse (t0); this
- * allows the chipset to process its initial power button interrupt and do
- * things like wake from suspend.  We then deassert the power button signal to
- * the chipset for (t1 = 4 sec - t0), which keeps the chipset from starting its
- * hard reset timer.  If the power button is still pressed after this period,
- * we again assert the power button signal for the remainder of the press
- * duration.  Since (t0+t1) causes a 4-second offset, the hard reset timeout in
- * the chipset triggers after 8 seconds as desired.
- *
- *   PWRBTN#   ---                      ----
- *     to EC     |______________________|
- *
- *
- *   PWRBTN#   ---  ---------           ----
- *    to PCH     |__|       |___________|
- *                t0    t1    held down
- *
- *   scan code   |                      |
- *    to host    v                      v
- *     @S0   make code             break code
- */
-#define PWRBTN_DELAY_T0    (32 * MSEC)  /* 32ms (PCH requires >16ms) */
-#define PWRBTN_DELAY_T1    (4 * SECOND - PWRBTN_DELAY_T0)  /* 4 secs - t0 */
-/*
- * Length of time to stretch initial power button press to give chipset a
- * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
- * pulse length for simulated power button presses when the system is off.
- */
-#define PWRBTN_INITIAL_US  (200 * MSEC)
-
-enum power_button_state {
-	/* Button up; state machine idle */
-	PWRBTN_STATE_IDLE = 0,
-	/* Button pressed; debouncing done */
-	PWRBTN_STATE_PRESSED,
-	/* Button down, chipset on; sending initial short pulse */
-	PWRBTN_STATE_T0,
-	/* Button down, chipset on; delaying until we should reassert signal */
-	PWRBTN_STATE_T1,
-	/* Button down, signal asserted to chipset */
-	PWRBTN_STATE_HELD,
-	/* Force pulse due to lid-open event */
-	PWRBTN_STATE_LID_OPEN,
-	/* Button released; debouncing done */
-	PWRBTN_STATE_RELEASED,
-	/* Ignore next button release */
-	PWRBTN_STATE_EAT_RELEASE,
-	/*
-	 * Need to power on system after init, but waiting to find out if
-	 * sufficient battery power.
-	 */
-	PWRBTN_STATE_INIT_ON,
-	/* Forced pulse at EC boot due to keyboard controlled reset */
-	PWRBTN_STATE_BOOT_KB_RESET,
-	/* Power button pressed when chipset was off; stretching pulse */
-	PWRBTN_STATE_WAS_OFF,
-};
-static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE;
-
-static const char * const state_names[] = {
-	"idle",
-	"pressed",
-	"t0",
-	"t1",
-	"held",
-	"lid-open",
-	"released",
-	"eat-release",
-	"init-on",
-	"recovery",
-	"was-off",
-};
-
-/*
- * Time for next state transition of power button state machine, or 0 if the
- * state doesn't have a timeout.
- */
-static uint64_t tnext_state;
-
-/*
- * Record the time when power button task starts. It can be used by any code
- * path that needs to compare the current time with power button task start time
- * to identify any timeouts e.g. PB state machine checks current time to
- * identify if it should wait more for charger and battery to be initialized. In
- * case of recovery using buttons (where the user could be holding the buttons
- * for >30seconds), it is not right to compare current time with the time when
- * EC was reset since the tasks would not have started. Hence, this variable is
- * being added to record the time at which power button task starts.
- */
-static uint64_t tpb_task_start;
-
-/*
- * Determines whether to execute power button pulse (t0 stage)
- */
-static int power_button_pulse_enabled = 1;
-
-static void set_pwrbtn_to_pch(int high, int init)
-{
-	/*
-	 * If the battery is discharging and low enough we'd shut down the
-	 * system, don't press the power button. Also, don't press the
-	 * power button if the battery is charging but the battery level
-	 * is too low.
-	 */
-#ifdef CONFIG_CHARGER
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high &&
-	   (charge_want_shutdown() || charge_prevent_power_on(!init))) {
-		CPRINTS("PB PCH pwrbtn ignored due to battery level");
-		high = 1;
-	}
-#endif
-	CPRINTS("PB PCH pwrbtn=%s", high ? "HIGH" : "LOW");
-	if (IS_ENABLED(CONFIG_POWER_BUTTON_TO_PCH_CUSTOM))
-		board_pwrbtn_to_pch(high);
-	else
-		gpio_set_level(GPIO_PCH_PWRBTN_L, high);
-}
-
-void power_button_pch_press(void)
-{
-	CPRINTS("PB PCH force press");
-
-	/* Assert power button signal to PCH */
-	if (!power_button_is_pressed())
-		set_pwrbtn_to_pch(0, 0);
-}
-
-void power_button_pch_release(void)
-{
-	CPRINTS("PB PCH force release");
-
-	/* Deassert power button signal to PCH */
-	set_pwrbtn_to_pch(1, 0);
-
-	/*
-	 * If power button is actually pressed, eat the next release so we
-	 * don't send an extra release.
-	 */
-	if (power_button_is_pressed())
-		pwrbtn_state = PWRBTN_STATE_EAT_RELEASE;
-	else
-		pwrbtn_state = PWRBTN_STATE_IDLE;
-}
-
-void power_button_pch_pulse(void)
-{
-	CPRINTS("PB PCH pulse");
-
-	chipset_exit_hard_off();
-	set_pwrbtn_to_pch(0, 0);
-	pwrbtn_state = PWRBTN_STATE_LID_OPEN;
-	tnext_state = get_time().val + PWRBTN_INITIAL_US;
-	task_wake(TASK_ID_POWERBTN);
-}
-
-/**
- * Handle debounced power button down.
- */
-static void power_button_pressed(uint64_t tnow)
-{
-	CPRINTS("PB pressed");
-	pwrbtn_state = PWRBTN_STATE_PRESSED;
-	tnext_state = tnow;
-}
-
-/**
- * Handle debounced power button up.
- */
-static void power_button_released(uint64_t tnow)
-{
-	CPRINTS("PB released");
-	pwrbtn_state = PWRBTN_STATE_RELEASED;
-	tnext_state = tnow;
-}
-
-/**
- * Set initial power button state.
- */
-static void set_initial_pwrbtn_state(void)
-{
-	uint32_t reset_flags = system_get_reset_flags();
-
-	if (system_jumped_to_this_image() &&
-	    chipset_in_state(CHIPSET_STATE_ON)) {
-		/*
-		 * Jumped to this image while the chipset was already on, so
-		 * simply reflect the actual power button state unless power
-		 * button pulse is disabled. If power button SMI pulse is
-		 * enabled, then it should be honored, else setting power
-		 * button to PCH could lead to x86 platform shutting down. If
-		 * power button is still held by the time control reaches
-		 * state_machine(), it would take the appropriate action there.
-		 */
-		if (power_button_is_pressed() && power_button_pulse_enabled) {
-			CPRINTS("PB init-jumped-held");
-			set_pwrbtn_to_pch(0, 0);
-		} else {
-			CPRINTS("PB init-jumped");
-		}
-		return;
-	} else if ((reset_flags & EC_RESET_FLAG_AP_OFF) ||
-		   (keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW)) {
-		/* Clear AP_OFF so that it won't be carried over to RW. */
-		system_clear_reset_flags(EC_RESET_FLAG_AP_OFF);
-		/*
-		 * Reset triggered by keyboard-controlled reset, and down-arrow
-		 * was held down.  Or reset flags request AP off.
-		 *
-		 * Leave the main processor off.  This is a fail-safe
-		 * combination for debugging failures booting the main
-		 * processor.
-		 *
-		 * Don't let the PCH see that the power button was pressed.
-		 * Otherwise, it might power on.
-		 */
-		CPRINTS("PB init-off");
-		power_button_pch_release();
-		return;
-	} else if (reset_flags & EC_RESET_FLAG_AP_IDLE) {
-		system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE);
-		pwrbtn_state = PWRBTN_STATE_IDLE;
-		CPRINTS("PB idle");
-		return;
-	}
-
-#ifdef CONFIG_BRINGUP
-	pwrbtn_state = PWRBTN_STATE_IDLE;
-#else
-	pwrbtn_state = PWRBTN_STATE_INIT_ON;
-#endif
-	CPRINTS("PB %s",
-		pwrbtn_state == PWRBTN_STATE_INIT_ON ? "init-on" : "idle");
-}
-
-/**
- * Power button state machine.
- *
- * @param tnow		Current time from usec counter
- */
-static void state_machine(uint64_t tnow)
-{
-	/* Not the time to move onto next state */
-	if (tnow < tnext_state)
-		return;
-
-	/* States last forever unless otherwise specified */
-	tnext_state = 0;
-
-	switch (pwrbtn_state) {
-	case PWRBTN_STATE_PRESSED:
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/*
-			 * Chipset is off, so wake the chipset and send it a
-			 * long enough pulse to wake up.  After that we'll
-			 * reflect the true power button state.  If we don't
-			 * stretch the pulse here, the user may release the
-			 * power button before the chipset finishes waking from
-			 * hard off state.
-			 */
-			chipset_exit_hard_off();
-			tnext_state = tnow + PWRBTN_INITIAL_US;
-			pwrbtn_state = PWRBTN_STATE_WAS_OFF;
-			set_pwrbtn_to_pch(0, 0);
-		} else {
-			if (power_button_pulse_enabled) {
-				/* Chipset is on, so send the chipset a pulse */
-				tnext_state = tnow + PWRBTN_DELAY_T0;
-				pwrbtn_state = PWRBTN_STATE_T0;
-				set_pwrbtn_to_pch(0, 0);
-			} else {
-				tnext_state = tnow + PWRBTN_DELAY_T1;
-				pwrbtn_state = PWRBTN_STATE_T1;
-			}
-		}
-		break;
-	case PWRBTN_STATE_T0:
-		tnext_state = tnow + PWRBTN_DELAY_T1;
-		pwrbtn_state = PWRBTN_STATE_T1;
-		set_pwrbtn_to_pch(1, 0);
-		break;
-	case PWRBTN_STATE_T1:
-		/*
-		 * If the chipset is already off, don't tell it the power
-		 * button is down; it'll just cause the chipset to turn on
-		 * again.
-		 */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			CPRINTS("PB chipset already off");
-		else
-			set_pwrbtn_to_pch(0, 0);
-		pwrbtn_state = PWRBTN_STATE_HELD;
-		break;
-	case PWRBTN_STATE_RELEASED:
-	case PWRBTN_STATE_LID_OPEN:
-		set_pwrbtn_to_pch(1, 0);
-		pwrbtn_state = PWRBTN_STATE_IDLE;
-		break;
-	case PWRBTN_STATE_INIT_ON:
-
-		/*
-		 * Before attempting to power the system on, we need to allow
-		 * time for charger, battery and USB-C PD initialization to be
-		 * ready to supply sufficient power. Check every 100
-		 * milliseconds, and give up CONFIG_POWER_BUTTON_INIT_TIMEOUT
-		 * seconds after the PB task was started. Here, it is
-		 * important to check the current time against PB task start
-		 * time to prevent unnecessary timeouts happening in recovery
-		 * case where the tasks could start as late as 30 seconds
-		 * after EC reset.
-		 */
-
-		if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) {
-			if (tnow >
-				(tpb_task_start +
-				 CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
-				pwrbtn_state = PWRBTN_STATE_IDLE;
-				break;
-			}
-
-			if (IS_ENABLED(CONFIG_CHARGER)) {
-				tnext_state = tnow + 100 * MSEC;
-				break;
-			}
-		}
-
-		/*
-		 * Power the system on if possible.  Gating due to insufficient
-		 * battery is handled inside set_pwrbtn_to_pch().
-		 */
-		chipset_exit_hard_off();
-#ifdef CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-		/* Check if power button is ready. If not, we'll come back. */
-		if (get_time().val - get_time_dsw_pwrok() <
-				CONFIG_DSW_PWROK_TO_PWRBTN_US) {
-			tnext_state = get_time_dsw_pwrok() +
-					CONFIG_DSW_PWROK_TO_PWRBTN_US;
-			break;
-		}
-#endif
-
-		set_pwrbtn_to_pch(0, 1);
-		tnext_state = get_time().val + PWRBTN_INITIAL_US;
-		pwrbtn_state = PWRBTN_STATE_BOOT_KB_RESET;
-		break;
-
-	case PWRBTN_STATE_BOOT_KB_RESET:
-		/* Initial forced pulse is done.  Ignore the actual power
-		 * button until it's released, so that holding down the
-		 * recovery combination doesn't cause the chipset to shut back
-		 * down. */
-		set_pwrbtn_to_pch(1, 0);
-		if (power_button_is_pressed())
-			pwrbtn_state = PWRBTN_STATE_EAT_RELEASE;
-		else
-			pwrbtn_state = PWRBTN_STATE_IDLE;
-		break;
-	case PWRBTN_STATE_WAS_OFF:
-		/* Done stretching initial power button signal, so show the
-		 * true power button state to the PCH. */
-		if (power_button_is_pressed()) {
-			/* User is still holding the power button */
-			pwrbtn_state = PWRBTN_STATE_HELD;
-		} else {
-			/* Stop stretching the power button press */
-			power_button_released(tnow);
-		}
-		break;
-	case PWRBTN_STATE_IDLE:
-	case PWRBTN_STATE_HELD:
-	case PWRBTN_STATE_EAT_RELEASE:
-		/* Do nothing */
-		break;
-	}
-}
-
-void power_button_task(void *u)
-{
-	uint64_t t;
-	uint64_t tsleep;
-
-	/*
-	 * Record the time when the task starts so that the state machine can
-	 * use this to identify any timeouts.
-	 */
-	tpb_task_start = get_time().val;
-
-	while (1) {
-		t = get_time().val;
-
-		/* Update state machine */
-		CPRINTS("PB task %d = %s", pwrbtn_state,
-			state_names[pwrbtn_state]);
-
-		state_machine(t);
-
-		/* Sleep until our next timeout */
-		tsleep = -1;
-		if (tnext_state && tnext_state < tsleep)
-			tsleep = tnext_state;
-		t = get_time().val;
-		if (tsleep > t) {
-			unsigned d = tsleep == -1 ? -1 : (unsigned)(tsleep - t);
-			/*
-			 * (Yes, the conversion from uint64_t to unsigned could
-			 * theoretically overflow if we wanted to sleep for
-			 * more than 2^32 us, but our timeouts are small enough
-			 * that can't happen - and even if it did, we'd just go
-			 * back to sleep after deciding that we woke up too
-			 * early.)
-			 */
-			CPRINTS("PB task %d = %s, wait %d", pwrbtn_state,
-			state_names[pwrbtn_state], d);
-			task_wait_event(d);
-		}
-	}
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void powerbtn_x86_init(void)
-{
-	set_initial_pwrbtn_state();
-}
-DECLARE_HOOK(HOOK_INIT, powerbtn_x86_init, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_LID_SWITCH
-/**
- * Handle switch changes based on lid event.
- */
-static void powerbtn_x86_lid_change(void)
-{
-	/* If chipset is off, pulse the power button on lid open to wake it. */
-	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF)
-	    && pwrbtn_state != PWRBTN_STATE_INIT_ON)
-		power_button_pch_pulse();
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, powerbtn_x86_lid_change, HOOK_PRIO_DEFAULT);
-#endif
-
-/**
- * Handle debounced power button changing state.
- */
-static void powerbtn_x86_changed(void)
-{
-	if (pwrbtn_state == PWRBTN_STATE_BOOT_KB_RESET ||
-	    pwrbtn_state == PWRBTN_STATE_INIT_ON ||
-	    pwrbtn_state == PWRBTN_STATE_LID_OPEN ||
-	    pwrbtn_state == PWRBTN_STATE_WAS_OFF) {
-		/* Ignore all power button changes during an initial pulse */
-		CPRINTS("PB ignoring change");
-		return;
-	}
-
-	if (power_button_is_pressed()) {
-		/* Power button pressed */
-		power_button_pressed(get_time().val);
-	} else {
-		/* Power button released */
-		if (pwrbtn_state == PWRBTN_STATE_EAT_RELEASE) {
-			/*
-			 * Ignore the first power button release if we already
-			 * told the PCH the power button was released.
-			 */
-			CPRINTS("PB ignoring release");
-			pwrbtn_state = PWRBTN_STATE_IDLE;
-			return;
-		}
-
-		power_button_released(get_time().val);
-	}
-
-	/* Wake the power button task */
-	task_wake(TASK_ID_POWERBTN);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_x86_changed, HOOK_PRIO_DEFAULT);
-
-/**
- * Handle configuring the power button behavior through a host command
- */
-static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_config_power_button *p = args->params;
-
-	power_button_pulse_enabled =
-		!!(p->flags & EC_POWER_BUTTON_ENABLE_PULSE);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86,
-		     EC_VER_MASK(0));
-
-
-/*
- * Currently, the only reason why we disable power button pulse is to allow
- * detachable menu on AP to use power button for selection purpose without
- * triggering SMI. Thus, re-enable the pulse any time there is a chipset
- * state transition event.
- */
-static void power_button_pulse_setting_reset(void)
-{
-	power_button_pulse_enabled = 1;
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, power_button_pulse_setting_reset,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, power_button_pulse_setting_reset,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset,
-	     HOOK_PRIO_DEFAULT);
-
-#define POWER_BUTTON_SYSJUMP_TAG		0x5042 /* PB */
-#define POWER_BUTTON_HOOK_VERSION		1
-
-static void power_button_pulse_setting_restore_state(void)
-{
-	const int *state;
-	int version, size;
-
-	state = (const int *)system_get_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
-						 &version, &size);
-
-	if (state && (version == POWER_BUTTON_HOOK_VERSION) &&
-	    (size == sizeof(power_button_pulse_enabled)))
-		power_button_pulse_enabled = *state;
-}
-DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state,
-	     HOOK_PRIO_INIT_POWER_BUTTON + 1);
-
-static void power_button_pulse_setting_preserve_state(void)
-{
-	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
-			    POWER_BUTTON_HOOK_VERSION,
-			    sizeof(power_button_pulse_enabled),
-			    &power_button_pulse_enabled);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, power_button_pulse_setting_preserve_state,
-	     HOOK_PRIO_DEFAULT);
diff --git a/common/pstore_commands.c b/common/pstore_commands.c
deleted file mode 100644
index 52270cd1cf..0000000000
--- a/common/pstore_commands.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Persistent storage commands for Chrome EC */
-
-#include "common.h"
-#include "eeprom.h"
-#include "host_command.h"
-#include "util.h"
-
-enum ec_status pstore_command_get_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_pstore_info *r = args->response;
-
-	ASSERT(EEPROM_BLOCK_START_PSTORE + EEPROM_BLOCK_COUNT_PSTORE <=
-	       eeprom_get_block_count());
-
-	r->pstore_size = EEPROM_BLOCK_COUNT_PSTORE * eeprom_get_block_size();
-	r->access_size = sizeof(uint32_t);
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO,
-		     pstore_command_get_info,
-		     EC_VER_MASK(0));
-
-enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pstore_read *p = args->params;
-	char *dest = args->response;
-	int block_size = eeprom_get_block_size();
-	int block = p->offset / block_size + EEPROM_BLOCK_START_PSTORE;
-	int offset = p->offset % block_size;
-	int bytes_left = p->size;
-
-	if (p->size > args->response_max)
-		return EC_RES_INVALID_PARAM;
-
-	while (bytes_left) {
-		/* Read what we can from the current block */
-		int bytes_this = MIN(bytes_left, block_size - offset);
-
-		if (block >=
-		    EEPROM_BLOCK_START_PSTORE + EEPROM_BLOCK_COUNT_PSTORE)
-			return EC_RES_ERROR;
-
-		if (eeprom_read(block, offset, bytes_this, dest))
-			return EC_RES_ERROR;
-
-		/* Continue to the next block if necessary */
-		offset = 0;
-		block++;
-		bytes_left -= bytes_this;
-		dest += bytes_this;
-	}
-
-	args->response_size = p->size;
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ,
-		     pstore_command_read,
-		     EC_VER_MASK(0));
-
-enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pstore_write *p = args->params;
-
-	const char *src = p->data;
-	int block_size = eeprom_get_block_size();
-	int block = p->offset / block_size + EEPROM_BLOCK_START_PSTORE;
-	int offset = p->offset % block_size;
-	int bytes_left = p->size;
-
-	if (p->size > sizeof(p->data))
-		return EC_RES_ERROR;
-
-	while (bytes_left) {
-		/* Write what we can to the current block */
-		int bytes_this = MIN(bytes_left, block_size - offset);
-
-		if (block >=
-		    EEPROM_BLOCK_START_PSTORE + EEPROM_BLOCK_COUNT_PSTORE)
-			return EC_RES_ERROR;
-
-		if (eeprom_write(block, offset, bytes_this, src))
-			return EC_RES_ERROR;
-
-		/* Continue to the next block if necessary */
-		offset = 0;
-		block++;
-		bytes_left -= bytes_this;
-		src += bytes_this;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE,
-		     pstore_command_write,
-		     EC_VER_MASK(0));
diff --git a/common/pwm.c b/common/pwm.c
deleted file mode 100644
index 41989a94e0..0000000000
--- a/common/pwm.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "pwm.h"
-#include "util.h"
-
-#ifdef CONFIG_ZEPHYR
-#include "pwm/pwm.h"
-#endif
-
-#ifdef CONFIG_PWM
-
-/*
- * Get target channel based on type / index host command parameters.
- * Returns 0 if a valid channel is selected, -1 on error.
- */
-static int get_target_channel(enum pwm_channel *channel, int type, int index)
-{
-	switch (type) {
-	case EC_PWM_TYPE_GENERIC:
-		*channel = index;
-		break;
-#ifdef CONFIG_PWM_KBLIGHT
-	case EC_PWM_TYPE_KB_LIGHT:
-		*channel = PWM_CH_KBLIGHT;
-		break;
-#endif
-#ifdef CONFIG_PWM_DISPLIGHT
-	case EC_PWM_TYPE_DISPLAY_LIGHT:
-		*channel = PWM_CH_DISPLIGHT;
-		break;
-#endif
-	default:
-		return -1;
-	}
-
-	return *channel >= PWM_CH_COUNT;
-}
-
-__attribute__((weak)) void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
-{
-	int percent;
-
-	/* Convert 16 bit duty to percent on [0, 100] */
-	percent = DIV_ROUND_NEAREST((uint32_t)duty * 100, 65535);
-	pwm_set_duty(ch, percent);
-}
-
-__attribute__((weak)) uint16_t pwm_get_raw_duty(enum pwm_channel ch)
-{
-	return (pwm_get_duty(ch) * 65535) / 100;
-}
-
-static enum ec_status
-host_command_pwm_set_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_set_duty *p = args->params;
-	enum pwm_channel channel;
-
-	if (get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	pwm_set_raw_duty(channel, p->duty);
-	pwm_enable(channel, p->duty > 0);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_pwm_get_duty(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pwm_get_duty *p = args->params;
-	struct ec_response_pwm_get_duty *r = args->response;
-
-	enum pwm_channel channel;
-
-	if (get_target_channel(&channel, p->pwm_type, p->index))
-		return EC_RES_INVALID_PARAM;
-
-	r->duty = pwm_get_raw_duty(channel);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
-		     EC_VER_MASK(0));
-
-/**
- * Print status of a PWM channel.
- *
- * @param ch		Channel to print.
- */
-static void print_channel(enum pwm_channel ch, int max_duty)
-{
-	if (pwm_get_enabled(ch))
-		if (max_duty == 100)
-			ccprintf("  %d: %d%%\n", ch, pwm_get_duty(ch));
-		else
-			ccprintf("  %d: %d\n", ch, pwm_get_raw_duty(ch));
-	else
-		ccprintf("  %d: disabled\n", ch);
-}
-
-static int cc_pwm_duty(int argc, char **argv)
-{
-	int value = 0;
-	int max_duty = 100;
-	int ch;
-	char *e;
-	char *raw;
-
-	if (argc < 2) {
-		ccprintf("PWM channels:\n");
-		for (ch = 0; ch < PWM_CH_COUNT; ch++)
-			print_channel(ch, max_duty);
-		return EC_SUCCESS;
-	}
-
-	ch = strtoi(argv[1], &e, 0);
-	if (*e || ch < 0 || ch >= PWM_CH_COUNT)
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		raw = argv[2];
-		if (!strcasecmp(raw, "raw")) {
-			/* use raw duty */
-			value = strtoi(argv[3], &e, 0);
-			max_duty = EC_PWM_MAX_DUTY;
-		} else {
-			/* use percent duty */
-			value = strtoi(argv[2], &e, 0);
-			max_duty = 100;
-		}
-
-		if (*e || value > max_duty) {
-			/* Bad param */
-			return EC_ERROR_PARAM2;
-		} else if (value < 0) {
-			/* Negative = disable */
-			pwm_enable(ch, 0);
-		} else {
-			ccprintf("Setting channel %d to %d\n", ch, value);
-			pwm_enable(ch, 1);
-			(max_duty == 100) ? pwm_set_duty(ch, value) :
-				pwm_set_raw_duty(ch, value);
-		}
-	}
-
-	print_channel(ch, max_duty);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pwmduty, cc_pwm_duty,
-			"[channel [<percent> | -1=disable] | [raw <value>]]",
-			"Get/set PWM duty cycles ");
-#endif /* CONFIG_PWM */
-
-#ifndef CONFIG_ZEPHYR
-/*
- * Initialize all PWM pins as functional.  This is not required under
- * Zephyr as pin configuration is automatically performed by chip driver
- */
-static void pwm_pin_init(void)
-{
-	gpio_config_module(MODULE_PWM, 1);
-}
-/* HOOK_PRIO_INIT_PWM may be used for chip PWM unit init, so use PRIO + 1 */
-DECLARE_HOOK(HOOK_INIT, pwm_pin_init, HOOK_PRIO_INIT_PWM + 1);
-#endif /* CONFIG_ZEPHYR */
diff --git a/common/pwm_kblight.c b/common/pwm_kblight.c
deleted file mode 100644
index 4967d36df5..0000000000
--- a/common/pwm_kblight.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PWM control module for keyboard backlight. */
-
-#include "common.h"
-#include "keyboard_backlight.h"
-#include "pwm.h"
-#include "system.h"
-#include "util.h"
-
-const enum pwm_channel kblight_pwm_ch = PWM_CH_KBLIGHT;
-
-static int kblight_pwm_set(int percent)
-{
-	pwm_set_duty(kblight_pwm_ch, percent);
-	return EC_SUCCESS;
-}
-
-static int kblight_pwm_get(void)
-{
-	return pwm_get_duty(kblight_pwm_ch);
-}
-
-static int kblight_pwm_init(void)
-{
-	/* dnojiri: Why do we need save/restore setting over sysjump? */
-	kblight_pwm_set(0);
-	pwm_enable(kblight_pwm_ch, 0);
-	return EC_SUCCESS;
-}
-
-static int kblight_pwm_enable(int enable)
-{
-	pwm_enable(kblight_pwm_ch, enable);
-	return EC_SUCCESS;
-}
-
-const struct kblight_drv kblight_pwm = {
-	.init = kblight_pwm_init,
-	.set = kblight_pwm_set,
-	.get = kblight_pwm_get,
-	.enable = kblight_pwm_enable,
-};
diff --git a/common/regulator.c b/common/regulator.c
deleted file mode 100644
index c3f5d0b99d..0000000000
--- a/common/regulator.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Regulator control module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "regulator.h"
-
-static enum ec_status
-hc_regulator_get_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_regulator_get_info *p = args->params;
-	struct ec_response_regulator_get_info *r = args->response;
-	int rv;
-
-	rv = board_regulator_get_info(p->index, r->name, &r->num_voltages,
-				      r->voltages_mv);
-
-	if (rv)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_GET_INFO, hc_regulator_get_info,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_regulator_enable(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_regulator_enable *p = args->params;
-	int rv;
-
-	rv = board_regulator_enable(p->index, p->enable);
-
-	if (rv)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_ENABLE, hc_regulator_enable,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_regulator_is_enabled(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_regulator_is_enabled *p = args->params;
-	struct ec_response_regulator_is_enabled *r = args->response;
-	int rv;
-
-	rv = board_regulator_is_enabled(p->index, &r->enabled);
-
-	if (rv)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_IS_ENABLED, hc_regulator_is_enabled,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_regulator_get_voltage(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_regulator_get_voltage *p = args->params;
-	struct ec_response_regulator_get_voltage *r = args->response;
-	int rv;
-
-	rv = board_regulator_get_voltage(p->index, &r->voltage_mv);
-
-	if (rv)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_GET_VOLTAGE, hc_regulator_get_voltage,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-hc_regulator_set_voltage(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_regulator_set_voltage *p = args->params;
-	int rv;
-
-	rv = board_regulator_set_voltage(p->index, p->min_mv, p->max_mv);
-
-	if (rv)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_SET_VOLTAGE, hc_regulator_set_voltage,
-		     EC_VER_MASK(0));
diff --git a/common/rollback.c b/common/rollback.c
deleted file mode 100644
index 984058c49a..0000000000
--- a/common/rollback.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Rollback protection logic. */
-
-#include "common.h"
-#include "console.h"
-#ifdef CONFIG_LIBCRYPTOC
-#include "cryptoc/util.h"
-#endif
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#ifdef CONFIG_MPU
-#include "mpu.h"
-#endif
-#include "rollback.h"
-#include "rollback_private.h"
-#include "sha256.h"
-#include "system.h"
-#include "task.h"
-#include "trng.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/* Number of rollback regions */
-#define ROLLBACK_REGIONS 2
-
-static int get_rollback_offset(int region)
-{
-#ifdef CONFIG_FLASH_MULTIPLE_REGION
-	int rv;
-	int rollback_start_bank = crec_flash_bank_index(CONFIG_ROLLBACK_OFF);
-
-	rv = crec_flash_bank_start_offset(rollback_start_bank + region);
-	ASSERT(rv >= 0);
-	return rv;
-#else
-	return CONFIG_ROLLBACK_OFF + region * CONFIG_FLASH_ERASE_SIZE;
-#endif
-}
-
-#ifdef SECTION_IS_RO
-static int get_rollback_erase_size_bytes(int region)
-{
-	int erase_size;
-
-#ifndef CONFIG_FLASH_MULTIPLE_REGION
-	erase_size = CONFIG_FLASH_ERASE_SIZE;
-#else
-	int rollback_start_bank = crec_flash_bank_index(CONFIG_ROLLBACK_OFF);
-
-	erase_size = crec_flash_bank_erase_size(rollback_start_bank + region);
-#endif
-	ASSERT(erase_size > 0);
-	ASSERT(ROLLBACK_REGIONS * erase_size <= CONFIG_ROLLBACK_SIZE);
-	ASSERT(sizeof(struct rollback_data) <= erase_size);
-	return erase_size;
-}
-#endif
-
-/*
- * When MPU is available, read rollback with interrupts disabled, to minimize
- * time protection is left open.
- */
-static void lock_rollback(void)
-{
-#ifdef CONFIG_ROLLBACK_MPU_PROTECT
-	mpu_lock_rollback(1);
-	interrupt_enable();
-#endif
-}
-
-static void unlock_rollback(void)
-{
-#ifdef CONFIG_ROLLBACK_MPU_PROTECT
-	interrupt_disable();
-	mpu_lock_rollback(0);
-#endif
-}
-
-static void clear_rollback(struct rollback_data *data)
-{
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-	always_memset(data->secret, 0, sizeof(data->secret));
-#endif
-}
-
-int read_rollback(int region, struct rollback_data *data)
-{
-	int offset;
-	int ret = EC_SUCCESS;
-
-	offset = get_rollback_offset(region);
-
-	unlock_rollback();
-	if (crec_flash_read(offset, sizeof(*data), (char *)data))
-		ret = EC_ERROR_UNKNOWN;
-	lock_rollback();
-
-	return ret;
-}
-
-/*
- * Get the most recent rollback information.
- *
- * @data: Returns most recent rollback data block. The data is filled
- *        with zeros if no valid rollback block is present
- *
- * Return most recent region index on success (>= 0, or 0 if no rollback
- * region is valid), negative value on error.
- */
-static int get_latest_rollback(struct rollback_data *data)
-{
-	int ret = -1;
-	int region;
-	int min_region = -1;
-	int max_id = -1;
-	struct rollback_data tmp_data;
-
-	for (region = 0; region < ROLLBACK_REGIONS; region++) {
-		if (read_rollback(region, &tmp_data))
-			goto failed;
-
-		/* Check if not initialized or invalid cookie. */
-		if (tmp_data.cookie != CROS_EC_ROLLBACK_COOKIE)
-			continue;
-
-		if (tmp_data.id > max_id) {
-			min_region = region;
-			max_id = tmp_data.id;
-		}
-	}
-
-	if (min_region >= 0) {
-		if (read_rollback(min_region, data))
-			goto failed;
-	} else {
-		min_region = 0;
-		clear_rollback(data);
-	}
-	ret = min_region;
-
-failed:
-	clear_rollback(&tmp_data);
-	return ret;
-}
-
-int32_t rollback_get_minimum_version(void)
-{
-	struct rollback_data data;
-	int32_t ret = -1;
-
-	if (get_latest_rollback(&data) < 0)
-		goto failed;
-	ret = data.rollback_min_version;
-
-failed:
-	clear_rollback(&data);
-	return ret;
-}
-
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-test_mockable int rollback_get_secret(uint8_t *secret)
-{
-	int ret = EC_ERROR_UNKNOWN;
-	struct rollback_data data;
-
-	if (get_latest_rollback(&data) < 0)
-		goto failed;
-
-	/* Check that secret is not full of 0x00 or 0xff */
-	if (bytes_are_trivial(data.secret, sizeof(data.secret)))
-		goto failed;
-
-	memcpy(secret, data.secret, sizeof(data.secret));
-	ret = EC_SUCCESS;
-failed:
-	clear_rollback(&data);
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_ROLLBACK_UPDATE
-
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int add_entropy(uint8_t *dst, const uint8_t *src,
-		       const uint8_t *add, unsigned int add_len)
-{
-	int ret = 0;
-#ifdef CONFIG_SHA256
-BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
-	struct sha256_ctx ctx;
-	uint8_t *hash;
-#ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-	uint8_t extra;
-	int i;
-#endif
-
-	SHA256_init(&ctx);
-	SHA256_update(&ctx, src, CONFIG_ROLLBACK_SECRET_SIZE);
-	SHA256_update(&ctx, add, add_len);
-#ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-	/* Add some locally produced entropy */
-	for (i = 0; i < CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE; i++) {
-		if (!board_get_entropy(&extra, 1))
-			goto failed;
-		SHA256_update(&ctx, &extra, 1);
-	}
-#endif
-	hash = SHA256_final(&ctx);
-
-	memcpy(dst, hash, CONFIG_ROLLBACK_SECRET_SIZE);
-	ret = 1;
-
-#ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-failed:
-#endif
-	always_memset(&ctx, 0, sizeof(ctx));
-#else
-#error "Adding entropy to secret in rollback region requires SHA256."
-#endif
-	return ret;
-}
-#endif /* CONFIG_ROLLBACK_SECRET_SIZE */
-
-/**
- * Update rollback block.
- *
- * @param next_min_version	Minimum version to update in rollback block. Can
- *				be a negative value if entropy is provided (in
- *				that case the current minimum version is kept).
- * @param entropy		Entropy to be added to rollback block secret
- *				(can be NULL, in that case no entropy is added).
- * @param len			entropy length
- *
- * @return EC_SUCCESS on success, EC_ERROR_* on error.
- */
-static int rollback_update(int32_t next_min_version,
-			   const uint8_t *entropy, unsigned int length)
-{
-	/*
-	 * When doing flash_write operation, the data needs to be in blocks
-	 * of CONFIG_FLASH_WRITE_SIZE, pad rollback_data as required.
-	 */
-	uint8_t block[CONFIG_FLASH_WRITE_SIZE *
-		DIV_ROUND_UP(sizeof(struct rollback_data),
-			CONFIG_FLASH_WRITE_SIZE)];
-	struct rollback_data *data = (struct rollback_data *)block;
-	BUILD_ASSERT(sizeof(block) >= sizeof(*data));
-	int erase_size, offset, region, ret;
-
-	if (crec_flash_get_protect() & EC_FLASH_PROTECT_ROLLBACK_NOW) {
-		ret = EC_ERROR_ACCESS_DENIED;
-		goto out;
-	}
-
-	/* Initialize the rest of the block. */
-	memset(&block[sizeof(*data)], 0xff, sizeof(block)-sizeof(*data));
-
-	region = get_latest_rollback(data);
-
-	if (region < 0) {
-		ret = EC_ERROR_UNKNOWN;
-		goto out;
-	}
-
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-	if (entropy) {
-		/* Do not accept to decrease the value. */
-		if (next_min_version < data->rollback_min_version)
-			next_min_version = data->rollback_min_version;
-	} else
-#endif
-	{
-		/* Do not accept to decrease the value. */
-		if (next_min_version < data->rollback_min_version) {
-			ret = EC_ERROR_INVAL;
-			goto out;
-		}
-
-		/* No need to update if version is already correct. */
-		if (next_min_version == data->rollback_min_version) {
-			ret = EC_SUCCESS;
-			goto out;
-		}
-	}
-
-	/* Use the other region. */
-	region = (region + 1) % ROLLBACK_REGIONS;
-
-	offset = get_rollback_offset(region);
-
-	data->id = data->id + 1;
-	data->rollback_min_version = next_min_version;
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-	/*
-	 * If we are provided with some entropy, add it to secret. Otherwise,
-	 * data.secret is left untouched and written back to the other region.
-	 */
-	if (entropy) {
-		if (!add_entropy(data->secret, data->secret, entropy, length)) {
-			ret = EC_ERROR_UNCHANGED;
-			goto out;
-		}
-	}
-#endif
-	data->cookie = CROS_EC_ROLLBACK_COOKIE;
-
-	erase_size = get_rollback_erase_size_bytes(region);
-
-	if (erase_size < 0) {
-		ret = EC_ERROR_UNKNOWN;
-		goto out;
-	}
-
-	/* Offset should never be part of active image. */
-	if (system_unsafe_to_overwrite(offset, erase_size)) {
-		ret = EC_ERROR_UNKNOWN;
-		goto out;
-	}
-
-	unlock_rollback();
-	if (crec_flash_erase(offset, erase_size)) {
-		ret = EC_ERROR_UNKNOWN;
-		lock_rollback();
-		goto out;
-	}
-
-	ret = crec_flash_write(offset, sizeof(block), block);
-	lock_rollback();
-
-out:
-	clear_rollback(data);
-	return ret;
-}
-
-int rollback_update_version(int32_t next_min_version)
-{
-	return rollback_update(next_min_version, NULL, 0);
-}
-
-int rollback_add_entropy(const uint8_t *data, unsigned int len)
-{
-	return rollback_update(-1, data, len);
-}
-
-static int command_rollback_update(int argc, char **argv)
-{
-	int32_t min_version;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	min_version = strtoi(argv[1], &e, 0);
-
-	if (*e || min_version < 0)
-		return EC_ERROR_PARAM1;
-
-	return rollback_update_version(min_version);
-}
-DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update,
-			"min_version",
-			"Update rollback info");
-
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int command_rollback_add_entropy(int argc, char **argv)
-{
-	int len;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	len = strlen(argv[1]);
-
-	return rollback_add_entropy(argv[1], len);
-}
-DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy,
-			"data",
-			"Add entropy to rollback block");
-
-#ifdef CONFIG_RNG
-static int add_entropy_action;
-static int add_entropy_rv = EC_RES_UNAVAILABLE;
-
-static void add_entropy_deferred(void)
-{
-	uint8_t rand[CONFIG_ROLLBACK_SECRET_SIZE];
-	int repeat = 1;
-
-	/*
-	 * If asked to reset the old secret, just add entropy multiple times,
-	 * which will ping-pong between the blocks.
-	 */
-	if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC)
-		repeat = ROLLBACK_REGIONS;
-
-	init_trng();
-	do {
-		rand_bytes(rand, sizeof(rand));
-		if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) {
-			add_entropy_rv = EC_RES_ERROR;
-			goto out;
-		}
-	} while (--repeat);
-
-	add_entropy_rv = EC_RES_SUCCESS;
-out:
-	exit_trng();
-}
-DECLARE_DEFERRED(add_entropy_deferred);
-
-static enum ec_status
-hc_rollback_add_entropy(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rollback_add_entropy *p = args->params;
-
-	switch (p->action) {
-	case ADD_ENTROPY_ASYNC:
-	case ADD_ENTROPY_RESET_ASYNC:
-		if (add_entropy_rv == EC_RES_BUSY)
-			return EC_RES_BUSY;
-
-		add_entropy_action = p->action;
-		add_entropy_rv = EC_RES_BUSY;
-		hook_call_deferred(&add_entropy_deferred_data, 0);
-
-		return EC_RES_SUCCESS;
-
-	case ADD_ENTROPY_GET_RESULT:
-		return add_entropy_rv;
-	}
-
-	return EC_RES_INVALID_PARAM;
-}
-DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY,
-		     hc_rollback_add_entropy,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_RNG */
-#endif /* CONFIG_ROLLBACK_SECRET_SIZE */
-#endif /* CONFIG_ROLLBACK_UPDATE */
-
-static int command_rollback_info(int argc, char **argv)
-{
-	int ret = EC_ERROR_UNKNOWN;
-	int region, min_region;
-	int32_t rw_rollback_version;
-	struct rollback_data data;
-
-	min_region = get_latest_rollback(&data);
-
-	if (min_region < 0)
-		goto failed;
-
-	rw_rollback_version = system_get_rollback_version(EC_IMAGE_RW);
-
-	ccprintf("rollback minimum version: %d\n", data.rollback_min_version);
-	ccprintf("RW rollback version: %d\n", rw_rollback_version);
-
-	for (region = 0; region < ROLLBACK_REGIONS; region++) {
-		ret = read_rollback(region, &data);
-		if (ret)
-			goto failed;
-
-		ccprintf("rollback %d: %08x %08x %08x",
-			region, data.id, data.rollback_min_version,
-			data.cookie);
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-		if (!system_is_locked()) {
-			/* If system is unlocked, show some of the secret. */
-			ccprintf(" [%02x..%02x]", data.secret[0],
-				data.secret[CONFIG_ROLLBACK_SECRET_SIZE-1]);
-		}
-#endif
-		if (min_region == region)
-			ccprintf(" *");
-		ccprintf("\n");
-	}
-	ret = EC_SUCCESS;
-
-failed:
-	clear_rollback(&data);
-	return ret;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info,
-			     NULL,
-			     "Print rollback info");
-
-static enum ec_status
-host_command_rollback_info(struct host_cmd_handler_args *args)
-{
-	int ret = EC_RES_UNAVAILABLE;
-	struct ec_response_rollback_info *r = args->response;
-	int min_region;
-	struct rollback_data data;
-
-	min_region = get_latest_rollback(&data);
-
-	if (min_region < 0)
-		goto failed;
-
-	r->id = data.id;
-	r->rollback_min_version = data.rollback_min_version;
-	r->rw_rollback_version = system_get_rollback_version(EC_IMAGE_RW);
-
-	args->response_size = sizeof(*r);
-	ret = EC_RES_SUCCESS;
-
-failed:
-	clear_rollback(&data);
-	return ret;
-}
-DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO,
-		     host_command_rollback_info,
-		     EC_VER_MASK(0));
diff --git a/common/rollback_private.h b/common/rollback_private.h
deleted file mode 100644
index c757882f4f..0000000000
--- a/common/rollback_private.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/** Internal header file for rollback.
- *
- * EC code should not normally include this. These are exposed so they can be
- * used by unit test code.
- */
-
-#ifndef __CROS_EC_ROLLBACK_PRIVATE_H
-#define __CROS_EC_ROLLBACK_PRIVATE_H
-
-#include "config.h"
-
-/*
- * Note: Do not change this structure without also updating
- * common/firmware_image.S .image.ROLLBACK section.
- */
-struct rollback_data {
-	int32_t id; /* Incrementing number to indicate which region to use. */
-	int32_t rollback_min_version;
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-	uint8_t secret[CONFIG_ROLLBACK_SECRET_SIZE];
-#endif
-	/* cookie must always be last, as it validates the rest of the data. */
-	uint32_t cookie;
-};
-
-int read_rollback(int region, struct rollback_data *data);
-
-#endif /* __CROS_EC_ROLLBACK_PRIVATE_H */
diff --git a/common/rsa.c b/common/rsa.c
deleted file mode 100644
index 10f0afa4b4..0000000000
--- a/common/rsa.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Implementation of RSA signature verification which uses a pre-processed key
- * for computation.
- */
-
-#include "rsa.h"
-#include "sha256.h"
-#include "util.h"
-
-/**
- * a[] -= mod
- */
-static void sub_mod(const struct rsa_public_key *key, uint32_t *a)
-{
-	int64_t A = 0;
-	uint32_t i;
-	for (i = 0; i < RSANUMWORDS; ++i) {
-		A += (uint64_t)a[i] - key->n[i];
-		a[i] = (uint32_t)A;
-		A >>= 32;
-	}
-}
-
-/**
- * Return a[] >= mod
- */
-static int ge_mod(const struct rsa_public_key *key, const uint32_t *a)
-{
-	uint32_t i;
-	for (i = RSANUMWORDS; i;) {
-		--i;
-		if (a[i] < key->n[i])
-			return 0;
-		if (a[i] > key->n[i])
-			return 1;
-	}
-	return 1;  /* equal */
-}
-
-/**
- * Montgomery c[] += a * b[] / R % mod
- */
-static void mont_mul_add(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t a,
-			 const uint32_t *b)
-{
-	uint64_t A = mula32(a, b[0], c[0]);
-	uint32_t d0 = (uint32_t)A * key->n0inv;
-	uint64_t B = mula32(d0, key->n[0], A);
-	uint32_t i;
-
-	for (i = 1; i < RSANUMWORDS; ++i) {
-		A = mulaa32(a, b[i], c[i], A >> 32);
-		B = mulaa32(d0, key->n[i], A, B >> 32);
-		c[i - 1] = (uint32_t)B;
-	}
-
-	A = (A >> 32) + (B >> 32);
-
-	c[i - 1] = (uint32_t)A;
-
-	if (A >> 32)
-		sub_mod(key, c);
-}
-
-#ifdef CONFIG_RSA_EXPONENT_3
-/**
- * Montgomery c[] += 0 * b[] / R % mod
- */
-static void mont_mul_add_0(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t *b)
-{
-	uint32_t d0 = c[0] * key->n0inv;
-	uint64_t B = mula32(d0, key->n[0], c[0]);
-	uint32_t i;
-
-	for (i = 1; i < RSANUMWORDS; ++i) {
-		B = mulaa32(d0, key->n[i], c[i], B >> 32);
-		c[i - 1] = (uint32_t)B;
-	}
-
-	c[i - 1] = B >> 32;
-}
-
-/* Montgomery c[] = a[] * 1 / R % key. */
-static void mont_mul_1(const struct rsa_public_key *key,
-		       uint32_t *c,
-		       const uint32_t *a)
-{
-	int i;
-
-	for (i = 0; i < RSANUMWORDS; ++i)
-		c[i] = 0;
-
-	mont_mul_add(key, c, 1, a);
-	for (i = 1; i < RSANUMWORDS; ++i)
-		mont_mul_add_0(key, c, a);
-}
-#endif
-
-/**
- * Montgomery c[] = a[] * b[] / R % mod
- */
-static void mont_mul(const struct rsa_public_key *key,
-		     uint32_t *c,
-		     const uint32_t *a,
-		     const uint32_t *b)
-{
-	uint32_t i;
-	for (i = 0; i < RSANUMWORDS; ++i)
-		c[i] = 0;
-
-	for (i = 0; i < RSANUMWORDS; ++i)
-		mont_mul_add(key, c, a[i], b);
-}
-
-/**
- * In-place public exponentiation.
- * Exponent depends on the configuration (65537 (default), or 3).
- *
- * @param key		Key to use in signing
- * @param inout		Input and output big-endian byte array
- * @param workbuf32	Work buffer; caller must verify this is
- *			3 x RSANUMWORDS elements long.
- */
-static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
-		    uint32_t *workbuf32)
-{
-	uint32_t *a = workbuf32;
-	uint32_t *a_r = a + RSANUMWORDS;
-	uint32_t *aa_r = a_r + RSANUMWORDS;
-	uint32_t *aaa = aa_r;  /* Re-use location. */
-	int i;
-
-	/* Convert from big endian byte array to little endian word array. */
-	for (i = 0; i < RSANUMWORDS; ++i) {
-		uint32_t tmp =
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0);
-		a[i] = tmp;
-	}
-
-	/* TODO(drinkcat): This operation could be precomputed to save time. */
-	mont_mul(key, a_r, a, key->rr);  /* a_r = a * RR / R mod M */
-#ifdef CONFIG_RSA_EXPONENT_3
-	mont_mul(key, aa_r, a_r, a_r);
-	mont_mul(key, a, aa_r, a_r);
-	mont_mul_1(key, aaa, a);
-#else
-	/* Exponent 65537 */
-	for (i = 0; i < 16; i += 2) {
-		mont_mul(key, aa_r, a_r, a_r); /* aa_r = a_r * a_r / R mod M */
-		mont_mul(key, a_r, aa_r, aa_r);/* a_r = aa_r * aa_r / R mod M */
-	}
-	mont_mul(key, aaa, a_r, a);  /* aaa = a_r * a / R mod M */
-#endif
-
-	/* Make sure aaa < mod; aaa is at most 1x mod too large. */
-	if (ge_mod(key, aaa))
-		sub_mod(key, aaa);
-
-	/* Convert to bigendian byte array */
-	for (i = RSANUMWORDS - 1; i >= 0; --i) {
-		uint32_t tmp = aaa[i];
-		*inout++ = (uint8_t)(tmp >> 24);
-		*inout++ = (uint8_t)(tmp >> 16);
-		*inout++ = (uint8_t)(tmp >>  8);
-		*inout++ = (uint8_t)(tmp >>  0);
-	}
-}
-
-/*
- * PKCS#1 padding (from the RSA PKCS#1 v2.1 standard)
- *
- * The DER-encoded padding is defined as follows :
- * 0x00 || 0x01 || PS || 0x00 || T
- *
- * T: DER Encoded DigestInfo value which depends on the hash function used,
- * for SHA-256:
- * (0x)30 31 30 0d 06 09 60 86 48 01 65 03 04 02 01 05 00 04 20 || H.
- *
- * Length(T) = 51 octets for SHA-256
- *
- * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF
- */
-static const uint8_t sha256_tail[] = {
-	0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
-	0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01,
-	0x05, 0x00, 0x04, 0x20
-};
-
-#define PKCS_PAD_SIZE (RSANUMBYTES - SHA256_DIGEST_SIZE)
-
-/**
- * Check PKCS#1 padding bytes
- *
- * @param sig  Signature to verify
- * @return 0 if the padding is correct.
- */
-static int check_padding(const uint8_t *sig)
-{
-	uint8_t *ptr = (uint8_t *)sig;
-	int result = 0;
-	int i;
-
-	/* First 2 bytes are always 0x00 0x01 */
-	result |= *ptr++ ^ 0x00;
-	result |= *ptr++ ^ 0x01;
-
-	/* Then 0xff bytes until the tail */
-	for (i = 0; i < PKCS_PAD_SIZE - sizeof(sha256_tail) - 2; i++)
-		result |= *ptr++ ^ 0xff;
-
-	/* Check the tail. */
-	result |= memcmp(ptr, sha256_tail, sizeof(sha256_tail));
-
-	return !!result;
-}
-
-/*
- * Verify a SHA256WithRSA PKCS#1 v1.5 signature against an expected
- * SHA256 hash.
- *
- * @param key           RSA public key
- * @param signature     RSA signature
- * @param sha           SHA-256 digest of the content to verify
- * @param workbuf32     Work buffer; caller must verify this is
- *                      3 x RSANUMWORDS elements long.
- * @return 0 on failure, 1 on success.
- */
-int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature,
-	       const uint8_t *sha, uint32_t *workbuf32)
-{
-	uint8_t buf[RSANUMBYTES];
-
-	/* Copy input to local workspace. */
-	memcpy(buf, signature, RSANUMBYTES);
-
-	mod_pow(key, buf, workbuf32); /* In-place exponentiation. */
-
-	/* Check the PKCS#1 padding */
-	if (check_padding(buf) != 0)
-		return 0;
-
-	/* Check the digest. */
-	if (memcmp(buf + PKCS_PAD_SIZE, sha, SHA256_DIGEST_SIZE) != 0)
-		return 0;
-
-	return 1;  /* All checked out OK. */
-}
diff --git a/common/rtc.c b/common/rtc.c
deleted file mode 100644
index 670e86d707..0000000000
--- a/common/rtc.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* RTC cross-platform code for Chrome EC */
-/* TODO(chromium:733844): Move this conversion to kernel rtc-cros-ec driver */
-
-#include "rtc.h"
-
-static uint16_t days_since_year_start[12] = {
-	0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
-};
-
-/* Conversion between calendar date and seconds eclapsed since 1970-01-01 */
-uint32_t date_to_sec(struct calendar_date time)
-{
-	int i;
-	uint32_t sec;
-
-	sec = time.year * SECS_PER_YEAR;
-	for (i = 0; i < time.year; i++) {
-		if (IS_LEAP_YEAR(i))
-			sec += SECS_PER_DAY;
-	}
-
-	sec += (days_since_year_start[time.month - 1] +
-		(IS_LEAP_YEAR(time.year) && time.month > 2) +
-		(time.day - 1)) * SECS_PER_DAY;
-
-	/* add the accumulated time in seconds from 1970 to 2000 */
-	return sec + SECS_TILL_YEAR_2K;
-}
-
-struct calendar_date sec_to_date(uint32_t sec)
-{
-	struct calendar_date time;
-	int day_tmp; /* for intermediate calculation */
-	int i;
-
-	/* RTC time must be after year 2000. */
-	sec = (sec > SECS_TILL_YEAR_2K) ? (sec - SECS_TILL_YEAR_2K) : 0;
-
-	day_tmp = sec / SECS_PER_DAY;
-	time.year = day_tmp / 365;
-	day_tmp %= 365;
-	for (i = 0; i < time.year; i++) {
-		if (IS_LEAP_YEAR(i))
-			day_tmp -= 1;
-	}
-	day_tmp++;
-	if (day_tmp <= 0) {
-		time.year -= 1;
-		day_tmp += IS_LEAP_YEAR(time.year) ? 366 : 365;
-	}
-	for (i = 1; i < 12; i++) {
-		if (days_since_year_start[i] +
-		    (IS_LEAP_YEAR(time.year) && (i >= 2)) >= day_tmp)
-			break;
-	}
-	time.month = i;
-
-	day_tmp -= days_since_year_start[time.month - 1] +
-		   (IS_LEAP_YEAR(time.year) && (time.month > 2));
-	time.day = day_tmp;
-
-	return time;
-}
diff --git a/common/rwsig.c b/common/rwsig.c
deleted file mode 100644
index 418a69c1a1..0000000000
--- a/common/rwsig.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Implementation of the RW firmware signature verification and jump.
- */
-
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "flash.h"
-#include "host_command.h"
-#include "rollback.h"
-#include "rsa.h"
-#include "rwsig.h"
-#include "sha256.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "vb21_struct.h"
-#include "vboot.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#if !defined(CONFIG_MAPPED_STORAGE)
-#error rwsig implementation assumes mem-mapped storage.
-#endif
-
-/* RW firmware reset vector */
-static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
-
-
-void rwsig_jump_now(void)
-{
-	/* Protect all flash before jumping to RW. */
-
-	/* This may do nothing if WP is not enabled, RO is not protected. */
-	crec_flash_set_protect(EC_FLASH_PROTECT_ALL_NOW, -1);
-
-	/*
-	 * For chips that does not support EC_FLASH_PROTECT_ALL_NOW, use
-	 * EC_FLASH_PROTECT_ALL_AT_BOOT.
-	 */
-	if (system_is_locked() &&
-	    !(crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)) {
-		crec_flash_set_protect(EC_FLASH_PROTECT_ALL_AT_BOOT, -1);
-
-		if (!(crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW) &&
-		    crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_AT_BOOT) {
-			/*
-			 * If flash protection is still not enabled (some chips
-			 * may be able to enable it immediately), reboot.
-			 */
-			cflush();
-			system_reset(SYSTEM_RESET_HARD |
-				     SYSTEM_RESET_PRESERVE_FLAGS);
-		}
-	}
-
-	/* When system is locked, only boot to RW if all flash is protected. */
-	if (!system_is_locked() ||
-	    crec_flash_get_protect() & EC_FLASH_PROTECT_ALL_NOW)
-		system_run_image_copy(EC_IMAGE_RW);
-}
-
-/*
- * Check that memory between rwdata[start] and rwdata[len-1] is filled
- * with ones. data, start and len must be aligned on 4-byte boundary.
- */
-static int check_padding(const uint8_t *data,
-			 unsigned int start, unsigned int len)
-{
-	unsigned int i;
-	const uint32_t *data32 = (const uint32_t *)data;
-
-	if ((start % 4) != 0 || (len % 4) != 0)
-		return 0;
-
-	for (i = start/4; i < len/4; i++) {
-		if (data32[i] != 0xffffffff)
-			return 0;
-	}
-
-	return 1;
-}
-
-int rwsig_check_signature(void)
-{
-	struct sha256_ctx ctx;
-	int res;
-	const struct rsa_public_key *key;
-	const uint8_t *sig;
-	uint8_t *hash;
-	uint32_t *rsa_workbuf = NULL;
-	const uint8_t *rwdata = (uint8_t *)CONFIG_PROGRAM_MEMORY_BASE
-					+ CONFIG_RW_MEM_OFF;
-	int good = 0;
-
-	unsigned int rwlen;
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-	const struct vb21_packed_key *vb21_key;
-	const struct vb21_signature *vb21_sig;
-#endif
-#ifdef CONFIG_ROLLBACK
-	int32_t rw_rollback_version;
-	int32_t min_rollback_version;
-#endif
-
-	/* Check if we have a RW firmware flashed */
-	if (*rw_rst == 0xffffffff)
-		goto out;
-
-	CPRINTS("Verifying RW image...");
-
-#ifdef CONFIG_ROLLBACK
-	rw_rollback_version = system_get_rollback_version(EC_IMAGE_RW);
-	min_rollback_version = rollback_get_minimum_version();
-
-	if (rw_rollback_version < 0 || min_rollback_version < 0 ||
-	    rw_rollback_version < min_rollback_version) {
-		CPRINTS("Rollback error (%d < %d)",
-			rw_rollback_version, min_rollback_version);
-		goto out;
-	}
-#endif
-
-	/* Large buffer for RSA computation : could be re-use afterwards... */
-	res = SHARED_MEM_ACQUIRE_CHECK(3 * RSANUMBYTES, (char **)&rsa_workbuf);
-	if (res) {
-		CPRINTS("No memory for RW verification");
-		goto out;
-	}
-
-#ifdef CONFIG_RWSIG_TYPE_USBPD1
-	key = (const struct rsa_public_key *)CONFIG_RO_PUBKEY_ADDR;
-	sig = (const uint8_t *)CONFIG_RW_SIG_ADDR;
-	rwlen = CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE;
-#elif defined(CONFIG_RWSIG_TYPE_RWSIG)
-	vb21_key = vb21_get_packed_key();
-	vb21_sig = (const struct vb21_signature *)CONFIG_RW_SIG_ADDR;
-
-	if (vb21_key->c.magic != VB21_MAGIC_PACKED_KEY ||
-	    vb21_key->key_size != sizeof(struct rsa_public_key)) {
-		CPRINTS("Invalid key.");
-		goto out;
-	}
-
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
-
-	/*
-	 * TODO(crbug.com/690773): We could verify other parameters such
-	 * as sig_alg/hash_alg actually matches what we build for.
-	 */
-	if (vb21_sig->c.magic != VB21_MAGIC_SIGNATURE ||
-	    vb21_sig->sig_size != RSANUMBYTES ||
-	    vb21_key->sig_alg != vb21_sig->sig_alg ||
-	    vb21_key->hash_alg != vb21_sig->hash_alg ||
-	    /* Validity check signature offset and data size. */
-	    vb21_sig->sig_offset < sizeof(vb21_sig) ||
-	    (vb21_sig->sig_offset + RSANUMBYTES) > CONFIG_RW_SIG_SIZE ||
-	    vb21_sig->data_size > (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)) {
-		CPRINTS("Invalid signature.");
-		goto out;
-	}
-
-	sig = (const uint8_t *)vb21_sig + vb21_sig->sig_offset;
-	rwlen = vb21_sig->data_size;
-#endif
-
-	/*
-	 * Check that unverified RW region is actually filled with ones.
-	 */
-	good = check_padding(rwdata, rwlen,
-			CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
-	if (!good) {
-		CPRINTS("Invalid padding.");
-		goto out;
-	}
-
-	/* SHA-256 Hash of the RW firmware */
-	SHA256_init(&ctx);
-	SHA256_update(&ctx, rwdata, rwlen);
-	hash = SHA256_final(&ctx);
-
-	good = rsa_verify(key, sig, hash, rsa_workbuf);
-	if (!good)
-		goto out;
-
-#ifdef CONFIG_ROLLBACK
-	/*
-	 * Signature verified: we know that rw_rollback_version is valid, check
-	 * if rollback information should be updated.
-	 *
-	 * If the RW region can be protected independently
-	 * (CONFIG_FLASH_PROTECT_RW is defined), and system is locked, we only
-	 * increment the rollback if RW is currently protected.
-	 *
-	 * Otherwise, we immediately increment the rollback version.
-	 */
-	if (rw_rollback_version != min_rollback_version
-#ifdef CONFIG_FLASH_PROTECT_RW
-		&& ((!system_is_locked() ||
-				crec_flash_get_protect() &
-				EC_FLASH_PROTECT_RW_NOW))
-#endif
-			) {
-		/*
-		 * This will fail if the rollback block is protected (RW image
-		 * will unprotect that block later on).
-		 */
-		int ret = rollback_update_version(rw_rollback_version);
-
-		if (ret == 0) {
-			CPRINTS("Rollback updated to %d",
-				rw_rollback_version);
-		} else if (ret != EC_ERROR_ACCESS_DENIED) {
-			CPRINTS("Rollback update error %d", ret);
-			good = 0;
-		}
-	}
-#endif
-out:
-	CPRINTS("RW verify %s", good ? "OK" : "FAILED");
-
-	if (!good) {
-		pd_log_event(PD_EVENT_ACC_RW_FAIL, 0, 0, NULL);
-		/* RW firmware is invalid : do not jump there */
-		if (system_is_locked())
-			system_disable_jump();
-	}
-	if (rsa_workbuf)
-		shared_mem_release(rsa_workbuf);
-
-	return good;
-}
-
-#ifdef HAS_TASK_RWSIG
-#define TASK_EVENT_ABORT TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_CONTINUE TASK_EVENT_CUSTOM_BIT(1)
-
-static enum rwsig_status rwsig_status;
-
-enum rwsig_status rwsig_get_status(void)
-{
-	return rwsig_status;
-}
-
-void rwsig_abort(void)
-{
-	task_set_event(TASK_ID_RWSIG, TASK_EVENT_ABORT);
-}
-
-void rwsig_continue(void)
-{
-	task_set_event(TASK_ID_RWSIG, TASK_EVENT_CONTINUE);
-}
-
-void rwsig_task(void *u)
-{
-	uint32_t evt;
-
-	if (system_get_image_copy() != EC_IMAGE_RO)
-		goto exit;
-
-	/* Stay in RO if we were asked to when reset. */
-	if (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO) {
-		rwsig_status = RWSIG_ABORTED;
-		goto exit;
-	}
-
-	rwsig_status = RWSIG_IN_PROGRESS;
-	if (!rwsig_check_signature()) {
-		rwsig_status = RWSIG_INVALID;
-		goto exit;
-	}
-	rwsig_status = RWSIG_VALID;
-
-	/* Jump to RW after a timeout */
-	evt = task_wait_event(CONFIG_RWSIG_JUMP_TIMEOUT);
-
-	/* Jump now if we timed out, or were told to continue. */
-	if (evt == TASK_EVENT_TIMER || evt == TASK_EVENT_CONTINUE)
-		rwsig_jump_now();
-	else
-		rwsig_status = RWSIG_ABORTED;
-
-exit:
-	/* We're done, yield forever. */
-	while (1)
-		task_wait_event(-1);
-}
-
-enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rwsig_action *p = args->params;
-
-	switch (p->action) {
-	case RWSIG_ACTION_ABORT:
-		rwsig_abort();
-		break;
-	case RWSIG_ACTION_CONTINUE:
-		rwsig_continue();
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	args->response_size = 0;
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION,
-		     rwsig_cmd_action,
-		     EC_VER_MASK(0));
-
-#else /* !HAS_TASK_RWSIG */
-enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rwsig_check_status *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->status = rwsig_check_signature();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS,
-		     rwsig_cmd_check_status,
-		     EC_VER_MASK(0));
-#endif
diff --git a/common/sha256.c b/common/sha256.c
deleted file mode 120000
index 8c0778c3e6..0000000000
--- a/common/sha256.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/sha2//sha256.c
\ No newline at end of file
diff --git a/common/shmalloc.c b/common/shmalloc.c
deleted file mode 100644
index b1705b52d1..0000000000
--- a/common/shmalloc.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Malloc/free memory module for Chrome EC */
-#include <stdint.h>
-
-#include "common.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-static struct mutex shmem_lock;
-
-#ifndef TEST_SHMALLOC
-#define set_map_bit(x)
-#define TEST_GLOBAL static
-#else
-#define TEST_GLOBAL
-#endif
-
-/*
- * At the beginning there is a single free memory chunk which includes all
- * memory available in the system. It then gets fragmented/defragmented based
- * on actual allocations/releases.
- */
-TEST_GLOBAL struct shm_buffer *free_buf_chain;
-
-/* At the beginning there is no allocated buffers */
-TEST_GLOBAL struct shm_buffer *allocced_buf_chain;
-
-/* The size of the biggest ever allocated buffer. */
-static int max_allocated_size;
-
-static void shared_mem_init(void)
-{
-	/*
-	 * Use all the RAM we can. The shared memory buffer is the last thing
-	 * allocated from the start of RAM, so we can use everything up to the
-	 * jump data at the end of RAM.
-	 */
-	free_buf_chain = (struct shm_buffer *)__shared_mem_buf;
-	free_buf_chain->next_buffer = NULL;
-	free_buf_chain->prev_buffer = NULL;
-	free_buf_chain->buffer_size = system_usable_ram_end() -
-		(uintptr_t)__shared_mem_buf;
-}
-DECLARE_HOOK(HOOK_INIT, shared_mem_init, HOOK_PRIO_FIRST);
-
-/* Called with the mutex lock acquired. */
-static void do_release(struct shm_buffer *ptr)
-{
-	struct shm_buffer *pfb;
-	struct shm_buffer *top;
-	size_t released_size;
-
-	/* Take the buffer out of the allocated buffers chain. */
-	if (ptr == allocced_buf_chain) {
-		if (ptr->next_buffer) {
-			set_map_bit(BIT(20));
-			ptr->next_buffer->prev_buffer = NULL;
-		} else {
-			set_map_bit(BIT(21));
-		}
-		allocced_buf_chain = ptr->next_buffer;
-	} else {
-		/*
-		 * Saninty check: verify that the buffer is in the allocated
-		 * buffers chain.
-		 */
-		for (pfb = allocced_buf_chain->next_buffer;
-		     pfb;
-		     pfb = pfb->next_buffer)
-			if (pfb == ptr)
-				break;
-		if (!pfb)
-			return;
-
-		ptr->prev_buffer->next_buffer = ptr->next_buffer;
-		if (ptr->next_buffer) {
-			set_map_bit(BIT(22));
-			ptr->next_buffer->prev_buffer = ptr->prev_buffer;
-		} else {
-			set_map_bit(BIT(23));
-		}
-	}
-
-	/*
-	 * Let's bring the released buffer back into the fold. Cache its size
-	 * for quick reference.
-	 */
-	released_size = ptr->buffer_size;
-	if (!free_buf_chain) {
-		/*
-		 * All memory had been allocated - this buffer is going to be
-		 * the only available free space.
-		 */
-		set_map_bit(BIT(0));
-		free_buf_chain = ptr;
-		free_buf_chain->buffer_size = released_size;
-		free_buf_chain->next_buffer = NULL;
-		free_buf_chain->prev_buffer = NULL;
-		return;
-	}
-
-	if (ptr < free_buf_chain) {
-		/*
-		 * Insert this buffer in the beginning of the chain, possibly
-		 * merging it with the first buffer of the chain.
-		 */
-		pfb = (struct shm_buffer *)((uintptr_t)ptr + released_size);
-		if (pfb == free_buf_chain) {
-			set_map_bit(BIT(1));
-			/* Merge the two buffers. */
-			ptr->buffer_size = free_buf_chain->buffer_size +
-				released_size;
-			ptr->next_buffer =
-				free_buf_chain->next_buffer;
-		} else {
-			set_map_bit(BIT(2));
-			ptr->buffer_size = released_size;
-			ptr->next_buffer = free_buf_chain;
-			free_buf_chain->prev_buffer = ptr;
-		}
-		if (ptr->next_buffer) {
-			set_map_bit(BIT(3));
-			ptr->next_buffer->prev_buffer = ptr;
-		} else {
-			set_map_bit(BIT(4));
-		}
-		ptr->prev_buffer = NULL;
-		free_buf_chain = ptr;
-		return;
-	}
-
-	/*
-	 * Need to merge the new free buffer into the existing chain. Find a
-	 * spot for it, it should be above the highest address buffer which is
-	 * still below the new one.
-	 */
-	pfb = free_buf_chain;
-	while (pfb->next_buffer && (pfb->next_buffer < ptr))
-		pfb = pfb->next_buffer;
-
-	top = (struct shm_buffer *)((uintptr_t)pfb + pfb->buffer_size);
-	if (top == ptr) {
-		/*
-		 * The returned buffer is adjacent to an existing free buffer,
-		 * below it, merge the two buffers.
-		 */
-		pfb->buffer_size += released_size;
-
-		/*
-		 * Is the returned buffer the exact gap between two free
-		 * buffers?
-		 */
-		top = (struct shm_buffer *)((uintptr_t)ptr + released_size);
-		if (top == pfb->next_buffer) {
-			/* Yes, it is. */
-			pfb->buffer_size += pfb->next_buffer->buffer_size;
-			pfb->next_buffer =
-				pfb->next_buffer->next_buffer;
-			if (pfb->next_buffer) {
-				set_map_bit(BIT(5));
-				pfb->next_buffer->prev_buffer = pfb;
-			} else {
-				set_map_bit(BIT(6));
-			}
-		}
-		return;
-	}
-
-	top = (struct shm_buffer *)((uintptr_t)ptr + released_size);
-	if (top == pfb->next_buffer) {
-		/* The new buffer is adjacent with the one right above it. */
-		set_map_bit(BIT(7));
-		ptr->buffer_size = released_size +
-			pfb->next_buffer->buffer_size;
-		ptr->next_buffer = pfb->next_buffer->next_buffer;
-	} else {
-		/* Just include the new free buffer into the chain. */
-		set_map_bit(BIT(8));
-		ptr->next_buffer = pfb->next_buffer;
-		ptr->buffer_size = released_size;
-	}
-	ptr->prev_buffer = pfb;
-	pfb->next_buffer = ptr;
-	if (ptr->next_buffer) {
-		set_map_bit(BIT(9));
-		ptr->next_buffer->prev_buffer = ptr;
-	} else {
-		set_map_bit(BIT(10));
-	}
-}
-
-/* Called with the mutex lock acquired. */
-static int do_acquire(int size, struct shm_buffer **dest_ptr)
-{
-	int headroom = 0x10000000; /* we'll never have this much. */
-	struct shm_buffer *pfb;
-	struct shm_buffer *candidate = 0;
-
-	/* To keep things simple let's align the size. */
-	size = (size + sizeof(int) - 1) & ~(sizeof(int) - 1);
-
-	/* And let's allocate room to fit the buffer header. */
-	size += sizeof(struct shm_buffer);
-
-	pfb = free_buf_chain;
-	while (pfb) {
-		if ((pfb->buffer_size >= size) &&
-		    ((pfb->buffer_size - size) < headroom)) {
-			/* this is a new candidate. */
-			headroom = pfb->buffer_size - size;
-			candidate = pfb;
-		}
-		pfb = pfb->next_buffer;
-	}
-
-	if (!candidate) {
-		set_map_bit(BIT(11));
-		return EC_ERROR_BUSY;
-	}
-
-	*dest_ptr = candidate;
-
-	/* Now let's take the candidate out of the free buffer chain. */
-	if (headroom <= sizeof(struct shm_buffer)) {
-		/*
-		 * The entire buffer should be allocated, there is no need to
-		 * re-define its tail as a new free buffer.
-		 */
-		if (candidate == free_buf_chain) {
-			/*
-			 * The next buffer becomes the head of the free buffer
-			 * chain.
-			 */
-			free_buf_chain = candidate->next_buffer;
-			if (free_buf_chain) {
-				set_map_bit(BIT(12));
-				free_buf_chain->prev_buffer = 0;
-			} else {
-				set_map_bit(BIT(13));
-			}
-		} else {
-			candidate->prev_buffer->next_buffer =
-				candidate->next_buffer;
-			if (candidate->next_buffer) {
-				set_map_bit(BIT(14));
-				candidate->next_buffer->prev_buffer =
-					candidate->prev_buffer;
-			} else {
-				set_map_bit(BIT(15));
-			}
-		}
-		return EC_SUCCESS;
-	}
-
-	candidate->buffer_size = size;
-
-	/* Candidate's tail becomes a new free buffer. */
-	pfb = (struct shm_buffer *)((uintptr_t)candidate + size);
-	pfb->buffer_size = headroom;
-	pfb->next_buffer = candidate->next_buffer;
-	pfb->prev_buffer = candidate->prev_buffer;
-
-	if (pfb->next_buffer) {
-		set_map_bit(BIT(16));
-		pfb->next_buffer->prev_buffer = pfb;
-	} else {
-		set_map_bit(BIT(17));
-	}
-
-	if (candidate == free_buf_chain) {
-		set_map_bit(BIT(18));
-		free_buf_chain = pfb;
-	} else {
-		set_map_bit(BIT(19));
-		pfb->prev_buffer->next_buffer = pfb;
-	}
-	return EC_SUCCESS;
-}
-
-int shared_mem_size(void)
-{
-	struct shm_buffer *pfb;
-	size_t max_available = 0;
-
-	mutex_lock(&shmem_lock);
-
-	/* Find the maximum available buffer size. */
-	pfb = free_buf_chain;
-	while (pfb) {
-		if (pfb->buffer_size > max_available)
-			max_available = pfb->buffer_size;
-		pfb = pfb->next_buffer;
-	}
-
-	mutex_unlock(&shmem_lock);
-	/* Leave room for shmem header */
-	max_available -= sizeof(struct shm_buffer);
-	return max_available;
-}
-
-int shared_mem_acquire(int size, char **dest_ptr)
-{
-	int rv;
-	struct shm_buffer *new_buf;
-
-	*dest_ptr = NULL;
-
-	if (in_interrupt_context())
-		return EC_ERROR_INVAL;
-
-	if (!free_buf_chain)
-		return EC_ERROR_BUSY;
-
-	mutex_lock(&shmem_lock);
-	rv = do_acquire(size, &new_buf);
-	if (rv == EC_SUCCESS) {
-		new_buf->next_buffer = allocced_buf_chain;
-		new_buf->prev_buffer = NULL;
-		if (allocced_buf_chain)
-			allocced_buf_chain->prev_buffer = new_buf;
-
-		allocced_buf_chain = new_buf;
-
-		*dest_ptr = (void *)(new_buf + 1);
-
-		if (size > max_allocated_size)
-			max_allocated_size = size;
-	}
-	mutex_unlock(&shmem_lock);
-
-	return rv;
-}
-
-void shared_mem_release(void *ptr)
-{
-	if (in_interrupt_context())
-		return;
-
-	mutex_lock(&shmem_lock);
-	do_release((struct shm_buffer *)ptr - 1);
-	mutex_unlock(&shmem_lock);
-}
-
-#ifdef CONFIG_CMD_SHMEM
-
-static int command_shmem(int argc, char **argv)
-{
-	size_t allocated_size;
-	size_t free_size;
-	size_t max_free;
-	struct shm_buffer *buf;
-
-	allocated_size = free_size = max_free = 0;
-
-	mutex_lock(&shmem_lock);
-
-	for (buf = free_buf_chain; buf; buf = buf->next_buffer) {
-		size_t buf_room;
-
-		buf_room = buf->buffer_size;
-
-		free_size += buf_room;
-		if (buf_room > max_free)
-			max_free = buf_room;
-	}
-
-	for (buf = allocced_buf_chain; buf;
-	     buf = buf->next_buffer)
-		allocated_size += buf->buffer_size;
-
-	mutex_unlock(&shmem_lock);
-
-	ccprintf("Total:         %6zd\n", allocated_size + free_size);
-	ccprintf("Allocated:     %6zd\n", allocated_size);
-	ccprintf("Free:          %6zd\n", free_size);
-	ccprintf("Max free buf:  %6zd\n", max_free);
-	ccprintf("Max allocated: %6d\n", max_allocated_size);
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem,
-			     NULL,
-			     "Print shared memory stats");
-
-#endif  /* CONFIG_CMD_SHMEM  ^^^^^^^ defined */
diff --git a/common/spi_commands.c b/common/spi_commands.c
deleted file mode 100644
index 1a70a5be82..0000000000
--- a/common/spi_commands.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI transfer command for debugging SPI devices.
- */
-
-#include "common.h"
-#include "console.h"
-#include "spi.h"
-#include "timer.h"
-#include "util.h"
-
-static int command_spixfer(int argc, char **argv)
-{
-	int dev_id;
-	uint8_t offset;
-	int v = 0;
-	uint8_t data[32];
-	char *e;
-	int rv = 0;
-
-	if (argc != 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	dev_id = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	offset = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	v = strtoi(argv[4], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM4;
-
-	if (strcasecmp(argv[1], "rlen") == 0) {
-		uint8_t cmd = 0x80 | offset;
-
-		/* Arbitrary length read; param4 = len */
-		if (v < 0 || v > sizeof(data))
-			return EC_ERROR_PARAM4;
-
-		rv = spi_transaction(&spi_devices[dev_id], &cmd, 1, data, v);
-
-		if (!rv)
-			ccprintf("Data: %ph\n", HEX_BUF(data, v));
-
-	} else if (strcasecmp(argv[1], "w") == 0) {
-		/* 8-bit write */
-		uint8_t cmd[2] = { offset, v };
-
-		rv = spi_transaction(&spi_devices[dev_id], cmd, 2, NULL, 0);
-
-		/*
-		 * Some SPI device needs a delay before accepting other
-		 * commands, otherwise the write might be ignored.
-		 */
-		msleep(1);
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spixfer, command_spixfer,
-			"rlen/w id offset [value | len]",
-			"Read write spi. id is spi_devices array index");
-
diff --git a/common/spi_flash.c b/common/spi_flash.c
deleted file mode 100644
index e202e1e17d..0000000000
--- a/common/spi_flash.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI flash driver for Chrome EC.
- */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "spi_flash_reg.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-#include "ec_commands.h"
-#include "flash.h"
-
-/*
- * Time to sleep when chip is busy
- */
-#define SPI_FLASH_SLEEP_USEC	100
-
-/*
- * This is the max time for 32kb flash erase
- */
-#define SPI_FLASH_TIMEOUT_USEC	(800*MSEC)
-
-/* Internal buffer used by SPI flash driver */
-static uint8_t buf[SPI_FLASH_MAX_MESSAGE_SIZE];
-
-/**
- * Waits for chip to finish current operation. Must be called after
- * erase/write operations to ensure successive commands are executed.
- *
- * @return EC_SUCCESS or error on timeout
- */
-int spi_flash_wait(void)
-{
-	timestamp_t timeout;
-
-	timeout.val = get_time().val + SPI_FLASH_TIMEOUT_USEC;
-	/* Wait until chip is not busy */
-	while (spi_flash_get_status1() & SPI_FLASH_SR1_BUSY) {
-		usleep(SPI_FLASH_SLEEP_USEC);
-
-		if (get_time().val > timeout.val)
-			return EC_ERROR_TIMEOUT;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set the write enable latch
- */
-static int spi_flash_write_enable(void)
-{
-	uint8_t cmd = SPI_FLASH_WRITE_ENABLE;
-	return spi_transaction(SPI_FLASH_DEVICE, &cmd, 1, NULL, 0);
-}
-
-/**
- * Returns the contents of SPI flash status register 1
- * @return register contents or 0xff on error
- */
-uint8_t spi_flash_get_status1(void)
-{
-	uint8_t cmd = SPI_FLASH_READ_SR1;
-	uint8_t resp;
-
-	if (spi_transaction(SPI_FLASH_DEVICE, &cmd, 1, &resp, 1) != EC_SUCCESS)
-		return 0xff;
-
-	return resp;
-}
-
-/**
- * Returns the contents of SPI flash status register 2
- * @return register contents or 0xff on error
- */
-uint8_t spi_flash_get_status2(void)
-{
-	uint8_t cmd = SPI_FLASH_READ_SR2;
-	uint8_t resp;
-
-	/* Second status register not present */
-#ifndef CONFIG_SPI_FLASH_HAS_SR2
-	return 0;
-#endif
-
-	if (spi_transaction(SPI_FLASH_DEVICE, &cmd, 1, &resp, 1) != EC_SUCCESS)
-		return 0xff;
-
-	return resp;
-}
-
-/**
- * Sets the SPI flash status registers (non-volatile bits only)
- * Pass reg2 == -1 to only set reg1.
- *
- * @param reg1 Status register 1
- * @param reg2 Status register 2 (optional)
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_set_status(int reg1, int reg2)
-{
-	uint8_t cmd[3] = {SPI_FLASH_WRITE_SR, reg1, reg2};
-	int rv = EC_SUCCESS;
-
-	/* fail if both HW pin is asserted and SRP(s) is 1 */
-	if (spi_flash_check_wp() != SPI_WP_NONE &&
-		(crec_flash_get_protect() &
-		EC_FLASH_PROTECT_GPIO_ASSERTED) != 0)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Enable writing to SPI flash */
-	rv = spi_flash_write_enable();
-	if (rv)
-		return rv;
-
-	/* Second status register not present */
-#ifndef CONFIG_SPI_FLASH_HAS_SR2
-	reg2 = -1;
-#endif
-
-	if (reg2 == -1)
-		rv = spi_transaction(SPI_FLASH_DEVICE, cmd, 2, NULL, 0);
-	else
-		rv = spi_transaction(SPI_FLASH_DEVICE, cmd, 3, NULL, 0);
-	if (rv)
-		return rv;
-
-	/* SRP update takes up to 10 ms, so wait for transaction to finish */
-	spi_flash_wait();
-
-	return rv;
-}
-
-/**
- * Returns the content of SPI flash
- *
- * @param buf_usr Buffer to write flash contents
- * @param offset Flash offset to start reading from
- * @param bytes Number of bytes to read.
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes)
-{
-	int i, read_size, ret, spi_addr;
-	uint8_t cmd[4];
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-	cmd[0] = SPI_FLASH_READ;
-	for (i = 0; i < bytes; i += read_size) {
-		spi_addr = offset + i;
-		cmd[1] = (spi_addr >> 16) & 0xFF;
-		cmd[2] = (spi_addr >> 8) & 0xFF;
-		cmd[3] = spi_addr & 0xFF;
-		read_size = MIN((bytes - i), SPI_FLASH_MAX_READ_SIZE);
-		ret = spi_transaction(SPI_FLASH_DEVICE,
-			cmd,
-			4,
-			buf_usr + i,
-			read_size);
-		if (ret != EC_SUCCESS)
-			break;
-		msleep(CONFIG_SPI_FLASH_READ_WAIT_MS);
-	}
-	return ret;
-}
-
-/**
- * Erase a block of SPI flash.
- *
- * @param offset Flash offset to start erasing
- * @param block Block size in kb (4 or 32)
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-static int spi_flash_erase_block(unsigned int offset, unsigned int block)
-{
-	uint8_t cmd[4];
-	int rv = EC_SUCCESS;
-
-	/* Invalid block size */
-	if (block != 4 && block != 32)
-		return EC_ERROR_INVAL;
-
-	/* Not block aligned */
-	if ((offset % (block * 1024)) != 0)
-		return EC_ERROR_INVAL;
-
-	/* Enable writing to SPI flash */
-	rv = spi_flash_write_enable();
-	if (rv)
-		return rv;
-
-	/* Compose instruction */
-	cmd[0] = (block == 4) ? SPI_FLASH_ERASE_4KB : SPI_FLASH_ERASE_32KB;
-	cmd[1] = (offset >> 16) & 0xFF;
-	cmd[2] = (offset >> 8) & 0xFF;
-	cmd[3] = offset & 0xFF;
-
-	rv = spi_transaction(SPI_FLASH_DEVICE, cmd, 4, NULL, 0);
-	if (rv)
-		return rv;
-
-	/* Wait for previous operation to complete */
-	return spi_flash_wait();
-}
-
-/**
- * Erase SPI flash.
- *
- * @param offset Flash offset to start erasing
- * @param bytes Number of bytes to erase
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_erase(unsigned int offset, unsigned int bytes)
-{
-	int rv = EC_SUCCESS;
-
-	/* Invalid input */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Not aligned to sector (4kb) */
-	if (offset % 4096 || bytes % 4096)
-		return EC_ERROR_INVAL;
-
-	/* Largest unit is block (32kb) */
-	if (offset % (32 * 1024) == 0) {
-		while (bytes != (bytes % (32 * 1024))) {
-			rv = spi_flash_erase_block(offset, 32);
-			if (rv)
-				return rv;
-
-			bytes -= 32 * 1024;
-			offset += 32 * 1024;
-			/*
-			 * Refresh watchdog since we may be erasing a large
-			 * number of blocks.
-			 */
-			watchdog_reload();
-		}
-	}
-
-	/* Largest unit is sector (4kb) */
-	while (bytes != (bytes % (4 * 1024))) {
-		rv = spi_flash_erase_block(offset, 4);
-		if (rv)
-			return rv;
-
-		bytes -= 4 * 1024;
-		offset += 4 * 1024;
-	}
-
-	return rv;
-}
-
-/**
- * Write to SPI flash. Assumes already erased.
- * Limited to SPI_FLASH_MAX_WRITE_SIZE by chip.
- *
- * @param offset Flash offset to write
- * @param bytes Number of bytes to write
- * @param data Data to write to flash
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_write(unsigned int offset, unsigned int bytes,
-	const uint8_t *data)
-{
-	int rv, write_size;
-
-	/* Invalid input */
-	if (!data || offset + bytes > CONFIG_FLASH_SIZE_BYTES ||
-	    bytes > SPI_FLASH_MAX_WRITE_SIZE)
-		return EC_ERROR_INVAL;
-
-	while (bytes > 0) {
-		watchdog_reload();
-		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, SPI_FLASH_MAX_WRITE_SIZE -
-		(offset & (SPI_FLASH_MAX_WRITE_SIZE - 1)));
-
-		/* Wait for previous operation to complete */
-		rv = spi_flash_wait();
-		if (rv)
-			return rv;
-
-		/* Enable writing to SPI flash */
-		rv = spi_flash_write_enable();
-		if (rv)
-			return rv;
-
-		/* Copy data to send buffer; buffers may overlap */
-		memmove(buf + 4, data, write_size);
-
-		/* Compose instruction */
-		buf[0] = SPI_FLASH_PAGE_PRGRM;
-		buf[1] = (offset) >> 16;
-		buf[2] = (offset) >> 8;
-		buf[3] = offset;
-
-		rv = spi_transaction(SPI_FLASH_DEVICE,
-				     buf, 4 + write_size, NULL, 0);
-		if (rv)
-			return rv;
-
-		data += write_size;
-		offset += write_size;
-		bytes -= write_size;
-	}
-
-	/* Wait for previous operation to complete */
-	return spi_flash_wait();
-}
-
-/**
- * Gets the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity)
- *
- * @param dest		Destination buffer; must be 3 bytes long
- * @return EC_SUCCESS or non-zero on error
- */
-int spi_flash_get_jedec_id(uint8_t *dest)
-{
-	uint8_t cmd = SPI_FLASH_JEDEC_ID;
-
-	return spi_transaction(SPI_FLASH_DEVICE, &cmd, 1, dest, 3);
-}
-
-/**
- * Gets the SPI flash manufacturer and device ID
- *
- * @param dest		Destination buffer; must be 2 bytes long
- * @return EC_SUCCESS or non-zero on error
- */
-int spi_flash_get_mfr_dev_id(uint8_t *dest)
-{
-	uint8_t cmd[4] = {SPI_FLASH_MFR_DEV_ID, 0, 0, 0};
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 2);
-}
-
-/**
- * Gets the SPI flash unique ID (serial)
- *
- * @param dest		Destination buffer; must be 8 bytes long
- * @return EC_SUCCESS or non-zero on error
- */
-int spi_flash_get_unique_id(uint8_t *dest)
-{
-	uint8_t cmd[5] = {SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0};
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 8);
-}
-
-/**
- * Check for SPI flash status register write protection
- * Cannot sample WP pin, so caller should sample it if necessary, if
- * SPI_WP_HARDWARE is returned.
- *
- * @return enum spi_flash_wp status based on protection
- */
-enum spi_flash_wp spi_flash_check_wp(void)
-{
-	int sr1_prot = spi_flash_get_status1() & SPI_FLASH_SR1_SRP0;
-	int sr2_prot = spi_flash_get_status2() & SPI_FLASH_SR2_SRP1;
-
-	if (sr2_prot)
-		return sr1_prot ? SPI_WP_PERMANENT : SPI_WP_POWER_CYCLE;
-	else if (sr1_prot)
-		return SPI_WP_HARDWARE;
-
-	return SPI_WP_NONE;
-}
-
-/**
- * Set SPI flash status register write protection
- *
- * @param wp Status register write protection mode
- *
- * @return EC_SUCCESS for no protection, or non-zero if error.
- */
-int spi_flash_set_wp(enum spi_flash_wp w)
-{
-	int sr1 = spi_flash_get_status1();
-	int sr2 = spi_flash_get_status2();
-
-	switch (w) {
-	case SPI_WP_NONE:
-		sr1 &= ~SPI_FLASH_SR1_SRP0;
-		sr2 &= ~SPI_FLASH_SR2_SRP1;
-		break;
-	case SPI_WP_HARDWARE:
-		sr1 |= SPI_FLASH_SR1_SRP0;
-		sr2 &= ~SPI_FLASH_SR2_SRP1;
-		break;
-	case SPI_WP_POWER_CYCLE:
-		sr1 &= ~SPI_FLASH_SR1_SRP0;
-		sr2 |= SPI_FLASH_SR2_SRP1;
-		break;
-	case SPI_WP_PERMANENT:
-		sr1 |= SPI_FLASH_SR1_SRP0;
-		sr2 |= SPI_FLASH_SR2_SRP1;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	return spi_flash_set_status(sr1, sr2);
-}
-
-/**
- * Check for SPI flash block write protection
- *
- * @param offset Flash block offset to check
- * @param bytes Flash block length to check
- *
- * @return EC_SUCCESS for no protection, or non-zero if error.
- */
-int spi_flash_check_protect(unsigned int offset, unsigned int bytes)
-{
-	uint8_t sr1 = spi_flash_get_status1();
-	uint8_t sr2 = spi_flash_get_status2();
-	unsigned int start;
-	unsigned int len;
-	int rv = EC_SUCCESS;
-
-	/* Invalid value */
-	if (sr1 == 0xff || sr2 == 0xff ||
-	    offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute current protect range */
-	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
-	if (rv)
-		return rv;
-
-	/* Check if ranges overlap */
-	if (MAX(start, offset) < MIN(start + len, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Set SPI flash block write protection
- * If offset == bytes == 0, remove protection.
- *
- * @param offset Flash block offset to protect
- * @param bytes Flash block length to protect
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int spi_flash_set_protect(unsigned int offset, unsigned int bytes)
-{
-	int rv;
-	uint8_t sr1 = spi_flash_get_status1();
-	uint8_t sr2 = spi_flash_get_status2();
-
-	/* Invalid values */
-	if (sr1 == 0xff || sr2 == 0xff ||
-	    offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute desired protect range */
-	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
-	if (rv)
-		return rv;
-
-	return spi_flash_set_status(sr1, sr2);
-}
-
-static int command_spi_flashinfo(int argc, char **argv)
-{
-	uint8_t jedec[3];
-	uint8_t unique[8];
-	int rv;
-
-	/* TODO(tomhughes): use board function to get devices. */
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	/* Wait for previous operation to complete */
-	rv = spi_flash_wait();
-	if (rv)
-		return rv;
-
-	spi_flash_get_jedec_id(jedec);
-	spi_flash_get_unique_id(unique);
-
-	ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n",
-		 jedec[0], jedec[1], jedec[2]);
-	ccprintf("Unique ID: %02x %02x %02x %02x %02x %02x %02x %02x\n",
-		 unique[0], unique[1], unique[2], unique[3],
-		 unique[4], unique[5], unique[6], unique[7]);
-	ccprintf("Capacity: %4d kB\n", SPI_FLASH_SIZE(jedec[2]) / 1024);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo,
-	NULL,
-	"Print SPI flash info");
-
-#ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
-static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_flash_spi_info *r = args->response;
-
-	spi_flash_get_jedec_id(r->jedec);
-	r->reserved0 = 0;
-	spi_flash_get_mfr_dev_id(r->mfr_dev_id);
-	r->sr1 = spi_flash_get_status1();
-	r->sr2 = spi_flash_get_status2();
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
-		     EC_VER_MASK(0));
-#endif  /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
-
-#ifdef CONFIG_CMD_SPI_FLASH
-static int command_spi_flasherase(int argc, char **argv)
-{
-	int offset = -1;
-	int bytes = 4096;
-	int rv = parse_offset_size(argc, argv, 1, &offset, &bytes);
-
-	if (rv)
-		return rv;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	/* Chip has protection */
-	if (spi_flash_check_protect(offset, bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	ccprintf("Erasing %d bytes at 0x%x...\n", bytes, offset);
-	return spi_flash_erase(offset, bytes);
-}
-DECLARE_CONSOLE_COMMAND(spi_flasherase, command_spi_flasherase,
-	"offset [bytes]",
-	"Erase flash");
-
-static int command_spi_flashwrite(int argc, char **argv)
-{
-	int offset = -1;
-	int bytes = SPI_FLASH_MAX_WRITE_SIZE;
-	int write_len;
-	int rv = EC_SUCCESS;
-	int i;
-
-	rv = parse_offset_size(argc, argv, 1, &offset, &bytes);
-	if (rv)
-		return rv;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	/* Chip has protection */
-	if (spi_flash_check_protect(offset, bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fill the data buffer with a pattern */
-	for (i = 0; i < SPI_FLASH_MAX_WRITE_SIZE; i++)
-		buf[i] = i;
-
-	ccprintf("Writing %d bytes to 0x%x...\n", bytes, offset);
-	while (bytes > 0) {
-		/* First write multiples of 256, then (bytes % 256) last */
-		write_len = ((bytes % SPI_FLASH_MAX_WRITE_SIZE) == bytes) ?
-					bytes : SPI_FLASH_MAX_WRITE_SIZE;
-
-		/* Perform write */
-		rv = spi_flash_write(offset, write_len, buf);
-		if (rv)
-			return rv;
-
-		offset += write_len;
-		bytes -= write_len;
-	}
-
-	ASSERT(bytes == 0);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spi_flashwrite, command_spi_flashwrite,
-	"offset [bytes]",
-	"Write pattern to flash");
-
-static int command_spi_flashread(int argc, char **argv)
-{
-	int i;
-	int offset = -1;
-	int bytes = -1;
-	int read_len;
-	int rv;
-
-	rv = parse_offset_size(argc, argv, 1, &offset, &bytes);
-	if (rv)
-		return rv;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	/* Can't read past size of memory */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Wait for previous operation to complete */
-	rv = spi_flash_wait();
-	if (rv)
-		return rv;
-
-	ccprintf("Reading %d bytes from 0x%x...\n", bytes, offset);
-	/* Read <= 256 bytes to avoid allocating another buffer */
-	while (bytes > 0) {
-		watchdog_reload();
-
-		/* First read (bytes % 256), then in multiples of 256 */
-		read_len = (bytes % SPI_FLASH_MAX_READ_SIZE) ?
-					(bytes % SPI_FLASH_MAX_READ_SIZE) :
-					SPI_FLASH_MAX_READ_SIZE;
-
-		rv = spi_flash_read(buf, offset, read_len);
-		if (rv)
-			return rv;
-
-		for (i = 0; i < read_len; i++) {
-			if (i % 16 == 0)
-				ccprintf("%02x:", offset + i);
-
-			ccprintf(" %02x", buf[i]);
-
-			if (i % 16 == 15 || i == read_len - 1)
-				ccputs("\n");
-		}
-
-		offset += read_len;
-		bytes -= read_len;
-	}
-
-	ASSERT(bytes == 0);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread,
-	"offset bytes",
-	"Read flash");
-
-static int command_spi_flashread_sr(int argc, char **argv)
-{
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	ccprintf("Status Register 1: 0x%02x\n", spi_flash_get_status1());
-	ccprintf("Status Register 2: 0x%02x\n", spi_flash_get_status2());
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr,
-	NULL,
-	"Read status registers");
-
-static int command_spi_flashwrite_sr(int argc, char **argv)
-{
-	int val1 = 0;
-	int val2 = 0;
-	int rv = parse_offset_size(argc, argv, 1, &val1, &val2);
-
-	if (rv)
-		return rv;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	ccprintf("Writing 0x%02x to status register 1, ", val1);
-	ccprintf("0x%02x to status register 2...\n", val2);
-	return spi_flash_set_status(val1, val2);
-}
-DECLARE_CONSOLE_COMMAND(spi_flash_wsr, command_spi_flashwrite_sr,
-	"value1 value2",
-	"Write to status registers");
-
-static int command_spi_flashprotect(int argc, char **argv)
-{
-	int val1 = 0;
-	int val2 = 0;
-	int rv = parse_offset_size(argc, argv, 1, &val1, &val2);
-
-	if (rv)
-		return rv;
-
-	spi_enable(SPI_FLASH_DEVICE, 1);
-
-	ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1, val1+val2);
-	return spi_flash_set_protect(val1, val2);
-}
-DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect,
-	"offset len",
-	"Set block protection");
-#endif
diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c
deleted file mode 100644
index ee8d31fa06..0000000000
--- a/common/spi_flash_reg.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI flash protection register translation functions for Chrome OS EC.
- */
-
-#include "common.h"
-#include "spi_flash_reg.h"
-#include "util.h"
-
-/* Bit state for protect range table */
-enum bit_state {
-	OFF = 0,
-	ON = 1,
-	IGN = -1, /* Don't care / Ignore */
-};
-
-struct protect_range {
-	enum bit_state cmp;
-	enum bit_state sec;
-	enum bit_state tb;
-	enum bit_state bp[3];    /* Ordered {BP2, BP1, BP0} */
-	uint32_t protect_start;
-	uint32_t protect_len;
-};
-
-/* Compare macro for (x =? b) for 'IGN' comparison */
-#define COMPARE_BIT(a, b) ((a) != IGN && (a) != !!(b))
-/* Assignment macro where 'IGN' = 0 */
-#define GET_BIT(a) ((a) == IGN ? 0 : (a))
-
-/*
- * Define flags and protect table for each SPI ROM part. It's not necessary
- * to define all ranges in the datasheet since we'll usually protect only
- * none or half of the ROM. The table is searched sequentially, so ordering
- * according to likely configurations improves performance slightly.
- */
-#if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B)
-static const struct protect_range spi_flash_protect_ranges[] = {
-	{ IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 },     /* No protection */
-	{ IGN, IGN, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
-	{ IGN, IGN, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */
-};
-
-#elif defined(CONFIG_SPI_FLASH_W25Q40) || defined(CONFIG_SPI_FLASH_GD25LQ40)
-/* Verified for W25Q40BV and W25Q40EW */
-/* For GD25LQ40, BP3 and BP4 have same meaning as TB and SEC */
-static const struct protect_range spi_flash_protect_ranges[] = {
-	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },         /* No protection */
-	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 },       /* Lower 1/4 */
-	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
-	/* CMP = 1 */
-	{ 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
-	{ 1, 0, IGN, { 1, IGN, IGN }, 0, 0 },       /* None (W25Q40EW only) */
-};
-
-#elif defined(CONFIG_SPI_FLASH_W25Q64)
-static const struct protect_range spi_flash_protect_ranges[] = {
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },    /* No protection */
-	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */
-	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */
-};
-
-#elif defined(CONFIG_SPI_FLASH_W25Q80)
-static const struct protect_range spi_flash_protect_ranges[] = {
-	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
-	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */
-	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */
-	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */
-};
-#elif defined(CONFIG_SPI_FLASH_W25Q128)
-static const struct protect_range spi_flash_protect_ranges[] = {
-	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
-	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x20000 }, /* Lower 1/8 */
-	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x40000 }, /* Lower 1/4 */
-	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x80000 }, /* Lower 1/2 */
-};
-#endif
-
-/**
- * Computes block write protection range from registers
- * Returns start == len == 0 for no protection
- *
- * @param sr1 Status register 1
- * @param sr2 Status register 2
- * @param start Output pointer for protection start offset
- * @param len Output pointer for protection length
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
-			     unsigned int *len)
-{
-	const struct protect_range *range;
-	int i;
-	uint8_t cmp;
-	uint8_t sec;
-	uint8_t tb;
-	uint8_t bp;
-
-	/* Determine flags */
-	cmp = (sr2 & SPI_FLASH_SR2_CMP) ? 1 : 0;
-	sec = (sr1 & SPI_FLASH_SR1_SEC) ? 1 : 0;
-	tb = (sr1 & SPI_FLASH_SR1_TB) ? 1 : 0;
-	bp = (sr1 & (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0))
-		 >> 2;
-
-	/* Bad pointers or invalid data */
-	if (!start || !len || sr1 == 0xff || sr2 == 0xff)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < ARRAY_SIZE(spi_flash_protect_ranges); ++i) {
-		range = &spi_flash_protect_ranges[i];
-		if (COMPARE_BIT(range->cmp, cmp))
-			continue;
-		if (COMPARE_BIT(range->sec, sec))
-			continue;
-		if (COMPARE_BIT(range->tb, tb))
-			continue;
-		if (COMPARE_BIT(range->bp[0], bp & 0x4))
-			continue;
-		if (COMPARE_BIT(range->bp[1], bp & 0x2))
-			continue;
-		if (COMPARE_BIT(range->bp[2], bp & 0x1))
-			continue;
-
-		*start = range->protect_start;
-		*len = range->protect_len;
-		return EC_SUCCESS;
-	}
-
-	/* Invalid range, or valid range missing from our table */
-	return EC_ERROR_INVAL;
-}
-
-/**
- * Computes block write protection registers from range
- *
- * @param start Desired protection start offset
- * @param len Desired protection length
- * @param sr1 Output pointer for status register 1
- * @param sr2 Output pointer for status register 2
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
-			     uint8_t *sr2)
-{
-	const struct protect_range *range;
-	int i;
-	char cmp = 0;
-	char sec = 0;
-	char tb = 0;
-	char bp = 0;
-
-	/* Bad pointers */
-	if (!sr1 || !sr2)
-		return EC_ERROR_INVAL;
-
-	/* Invalid data */
-	if ((start && !len) || start + len > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	for (i = 0; i < ARRAY_SIZE(spi_flash_protect_ranges); ++i) {
-		range = &spi_flash_protect_ranges[i];
-		if (range->protect_start == start &&
-		    range->protect_len == len) {
-			cmp = GET_BIT(range->cmp);
-			sec = GET_BIT(range->sec);
-			tb = GET_BIT(range->tb);
-			bp = GET_BIT(range->bp[0]) << 2 |
-			     GET_BIT(range->bp[1]) << 1 |
-			     GET_BIT(range->bp[2]);
-
-			*sr1 = (sec ? SPI_FLASH_SR1_SEC : 0) |
-			       (tb ? SPI_FLASH_SR1_TB : 0) |
-			       (bp << 2);
-			*sr2 = (cmp ? SPI_FLASH_SR2_CMP : 0);
-			return EC_SUCCESS;
-		}
-	}
-
-	/* Invalid range, or valid range missing from our table */
-	return EC_ERROR_INVAL;
-}
diff --git a/common/spi_nor.c b/common/spi_nor.c
deleted file mode 100644
index 0a719d63b3..0000000000
--- a/common/spi_nor.c
+++ /dev/null
@@ -1,1091 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SFDP-based Serial NOR flash device module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "spi_nor.h"
-#include "shared_mem.h"
-#include "util.h"
-#include "task.h"
-#include "spi.h"
-#include "sfdp.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#ifdef CONFIG_SPI_NOR_DEBUG
-#define CPRINTS(dev, string, args...) \
-	cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ## args)
-#else
-#define CPRINTS(dev, string, args...)
-#endif
-
-/* Time to sleep while serial NOR flash write is in progress. */
-#define SPI_NOR_WIP_SLEEP_USEC 10
-
-/* This driver only supports v1.* SFDP. */
-#define SPI_NOR_SUPPORTED_SFDP_MAJOR_VERSION 1
-
-/* Ensure a Serial NOR Flash read command in 4B addressing mode fits. */
-BUILD_ASSERT(CONFIG_SPI_NOR_MAX_READ_SIZE + 5 <=
-	     CONFIG_SPI_NOR_MAX_MESSAGE_SIZE);
-/* The maximum write size must be a power of two so it can be used as an
- * emulated maximum page size. */
-BUILD_ASSERT(POWER_OF_TWO(CONFIG_SPI_NOR_MAX_WRITE_SIZE));
-/* Ensure a Serial NOR Flash page program command in 4B addressing mode fits. */
-BUILD_ASSERT(CONFIG_SPI_NOR_MAX_WRITE_SIZE + 5 <=
-	     CONFIG_SPI_NOR_MAX_MESSAGE_SIZE);
-
-/* A single mutex is used to protect the single buffer, SPI port, and all of the
- * device mutable board defined device states, if the contention is too high it
- * may be worthwhile to change the global mutex granularity to a finer-grained
- * mutex granularity. */
-static struct mutex driver_mutex;
-
-/* Single internal buffer used to stage serial NOR flash commands for the
- * public APIs (read, write, erase). */
-static uint8_t buf[CONFIG_SPI_NOR_MAX_MESSAGE_SIZE];
-
-/******************************************************************************/
-/* Internal driver functions. */
-
-/**
- * Blocking read of the Serial Flash's first status register.
- */
-static int spi_nor_read_status(const struct spi_nor_device_t *spi_nor_device,
-			       uint8_t *status_register_value)
-{
-	uint8_t cmd = SPI_NOR_OPCODE_READ_STATUS;
-
-	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			       &cmd, 1, status_register_value, 1);
-}
-
-/**
- * Set the write enable latch. Device and shared buffer mutexes must be held!
- */
-static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device)
-{
-	uint8_t cmd = SPI_NOR_OPCODE_WRITE_ENABLE;
-	uint8_t status_register_value;
-	int rv = EC_SUCCESS;
-
-	/* Set the write enable latch. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, NULL, 0);
-	if (rv)
-		return rv;
-
-	/* Verify the write enabled latch got set. */
-	rv = spi_nor_read_status(spi_nor_device, &status_register_value);
-	if (rv)
-		return rv;
-	if ((status_register_value & SPI_NOR_STATUS_REGISTER_WEL) == 0)
-		return EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
-
-	return rv;
-}
-
-/**
- * Read from the extended address register.
- * @param  spi_nor_device The Serial NOR Flash device to use.
- * @param  value          The value to read to.
- * @return                ec_error_list (non-zero on error and timeout).
- */
-static int spi_nor_read_ear(const struct spi_nor_device_t *spi_nor_device,
-			    uint8_t *value)
-{
-	uint8_t command = SPI_NOR_OPCODE_RDEAR;
-
-	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			&command, sizeof(command), value, 1);
-}
-
-int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
-		      const uint8_t value)
-{
-	uint8_t buf[2];
-	int rv;
-	uint8_t ear;
-
-	mutex_lock(&driver_mutex);
-
-	rv = spi_nor_write_enable(spi_nor_device);
-	if (rv) {
-		CPRINTS(spi_nor_device, "Failed to write enable");
-		goto err_free;
-	}
-
-	buf[0] = SPI_NOR_OPCODE_WREAR;
-	buf[1] = value;
-
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     buf, sizeof(buf), NULL, 0);
-	if (rv) {
-		CPRINTS(spi_nor_device, "Failed to write EAR, rv=%d", rv);
-		goto err_free;
-	}
-
-	rv = spi_nor_read_ear(spi_nor_device, &ear);
-	if (rv)
-		goto err_free;
-
-	if (ear != value) {
-		CPRINTS(spi_nor_device,
-			"Write EAR error: write=%d, read=%d", value, ear);
-		rv = EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
-		goto err_free;
-	}
-
-err_free:
-	mutex_unlock(&driver_mutex);
-	return rv;
-}
-
-/**
- * Block until the Serial NOR Flash clears the BUSY/WIP bit in its status reg.
- */
-static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device)
-{
-	int rv = EC_SUCCESS;
-	timestamp_t timeout;
-	uint8_t status_register_value;
-
-	rv = spi_nor_read_status(spi_nor_device, &status_register_value);
-	if (rv)
-		return rv;
-	timeout.val =
-		get_time().val + spi_nor_device->timeout_usec;
-	while (status_register_value & SPI_NOR_STATUS_REGISTER_WIP) {
-		/* Reload the watchdog before sleeping. */
-		watchdog_reload();
-		usleep(SPI_NOR_WIP_SLEEP_USEC);
-
-		/* Give up if the deadline has been exceeded. */
-		if (get_time().val > timeout.val)
-			return EC_ERROR_TIMEOUT;
-
-		/* Re-read the status register. */
-		rv = spi_nor_read_status(spi_nor_device,
-					 &status_register_value);
-		if (rv)
-			return rv;
-	}
-
-	return rv;
-}
-
-/**
- * Read the Manufacturer bank and ID out of the JEDEC ID.
- */
-static int spi_nor_read_jedec_mfn_id(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_mfn_bank,
-		uint8_t *out_mfn_id)
-{
-	int rv = EC_SUCCESS;
-	uint8_t jedec_id[SPI_NOR_JEDEC_ID_BANKS];
-	size_t i;
-	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
-
-	/* Read the standardized part of the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, jedec_id, SPI_NOR_JEDEC_ID_BANKS);
-	if (rv)
-		return rv;
-
-	*out_mfn_bank = 0;
-	/* Go through the JEDEC ID a byte a time to looking for a manufacturer
-	 * ID instead of the next bank indicator (0x7F). */
-	for (i = 0; i < SPI_NOR_JEDEC_ID_BANKS; i++) {
-		*out_mfn_id = jedec_id[i];
-		if (*out_mfn_id != 0x7F)
-			return EC_SUCCESS;
-		*out_mfn_bank += 1;
-	}
-	/* JEDEC Manufacturer ID should be available, perhaps there is a bus
-	 * problem or the JEP106 specification has grown the number of banks? */
-	return EC_ERROR_UNKNOWN;
-}
-
-/**
- * Read a doubleword out of a SFDP table (DWs are 1-based like the SFDP spec).
- */
-static int spi_nor_read_sfdp_dword(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint32_t table_offset,
-		uint8_t table_double_word,
-		uint32_t *out_dw) {
-	uint8_t sfdp_cmd[5];
-	/* Calculate the byte offset based on the double word. */
-	uint32_t sfdp_offset = table_offset + ((table_double_word - 1) * 4);
-
-	/* Read the DW out of the SFDP region. */
-	sfdp_cmd[0] = SPI_NOR_OPCODE_SFDP;
-	sfdp_cmd[1] = (sfdp_offset & 0xFF0000) >> 16;
-	sfdp_cmd[2] = (sfdp_offset & 0xFF00) >> 8;
-	sfdp_cmd[3] = (sfdp_offset & 0xFF);
-	sfdp_cmd[4] = 0;  /* Required extra cycle. */
-	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			       sfdp_cmd, 5, (uint8_t *)out_dw, 4);
-}
-
-/**
- * Returns a bool (1 or 0) based on whether the parameter header double words
- * are for a SFDP v1.* Basic SPI Flash NOR Parameter Table.
- */
-static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev,
-					  uint8_t sfdp_minor_rev,
-					  uint32_t parameter_header_dw1,
-					  uint32_t parameter_header_dw2)
-{
-	if (sfdp_major_rev == 1 && sfdp_minor_rev < 5) {
-		return (SFDP_GET_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_ID,
-					  parameter_header_dw1) ==
-			BASIC_FLASH_PARAMETER_TABLE_1_0_ID);
-	} else if (sfdp_major_rev == 1 && sfdp_minor_rev >= 5) {
-		return ((SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB,
-					  parameter_header_dw1) ==
-			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_LSB) &&
-			(SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB,
-					  parameter_header_dw2) ==
-			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_MSB));
-	}
-
-	return 0;
-}
-
-/**
- * Helper function to locate the SFDP Basic SPI Flash NOR Parameter Table.
- */
-static int locate_sfdp_basic_parameter_table(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_sfdp_major_rev,
-		uint8_t *out_sfdp_minor_rev,
-		uint8_t *out_table_major_rev,
-		uint8_t *out_table_minor_rev,
-		uint32_t *out_table_offset,
-		size_t *out_table_size)
-{
-	int rv = EC_SUCCESS;
-	uint8_t number_parameter_headers;
-	uint32_t table_offset = 0;
-	int table_found = 0;
-	uint32_t dw1;
-	uint32_t dw2;
-
-	/* Read the SFDP header. */
-	rv = spi_nor_read_sfdp_dword(spi_nor_device, 0, 1, &dw1);
-	rv |= spi_nor_read_sfdp_dword(spi_nor_device, 0, 2, &dw2);
-	if (rv)
-		return rv;
-
-	/* Ensure the SFDP table is valid. Note the versions are not checked
-	 * through the SFDP table header, as there may be a backwards
-	 * compatible, older basic parameter tables which are compatible with
-	 * this driver in the parameter headers. */
-	if (!SFDP_HEADER_DW1_SFDP_SIGNATURE_VALID(dw1)) {
-		CPRINTS(spi_nor_device, "SFDP signature invalid");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	*out_sfdp_major_rev =
-		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, dw2);
-	*out_sfdp_minor_rev =
-		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, dw2);
-	CPRINTS(spi_nor_device, "SFDP v%d.%d discovered",
-		*out_sfdp_major_rev, *out_sfdp_minor_rev);
-
-	/* NPH is 0-based, so add 1. */
-	number_parameter_headers =
-		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_NPH, dw2) + 1;
-	CPRINTS(spi_nor_device, "There are %d SFDP parameter headers",
-		number_parameter_headers);
-
-	/* Search for the newest, compatible basic flash parameter table. */
-	*out_table_major_rev = 0;
-	*out_table_minor_rev = 0;
-	while (number_parameter_headers) {
-		uint8_t major_rev, minor_rev;
-
-		table_offset += 8;
-		number_parameter_headers--;
-
-		/* Read this parameter header's two dwords. */
-		rv = spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 1, &dw1);
-		rv |= spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 2, &dw2);
-		if (rv)
-			return rv;
-
-		/* Ensure it's the basic flash parameter table. */
-		if (!is_basic_flash_parameter_table(*out_sfdp_major_rev,
-						    *out_sfdp_minor_rev,
-						    dw1, dw2))
-			continue;
-
-		/* The parameter header major and minor versioning is still the
-		 * same as SFDP 1.0. */
-		major_rev = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MAJOR, dw1);
-		minor_rev = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MINOR, dw1);
-
-		/* Skip incompatible parameter tables. */
-		if (major_rev != SPI_NOR_SUPPORTED_SFDP_MAJOR_VERSION)
-			continue;
-
-		/* If this parameter table has a lower revision compared to a
-		 * previously found compatible table, skip it. */
-		if (minor_rev < *out_table_minor_rev)
-			continue;
-
-		table_found = 1;
-		*out_table_major_rev = major_rev;
-		*out_table_minor_rev = minor_rev;
-		/* The parameter header ptp and ptl are still the same as
-		 * SFDP 1.0. */
-		*out_table_offset = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW2_PTP, dw2);
-		/* Convert the size from DW to Bytes. */
-		*out_table_size = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW1_PTL, dw1) * 4;
-	}
-
-	if (!table_found) {
-		CPRINTS(spi_nor_device,
-			"No compatible Basic Flash Parameter Table found");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	CPRINTS(spi_nor_device, "Using Basic Flash Parameter Table v%d.%d",
-		*out_sfdp_major_rev, *out_sfdp_minor_rev);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Helper function to lookup the part's page size in the SFDP Basic SPI Flash
- * NOR Parameter Table.
- */
-static int spi_nor_device_discover_sfdp_page_size(
-	struct spi_nor_device_t *spi_nor_device,
-	uint8_t basic_parameter_table_major_version,
-	uint8_t basic_parameter_table_minor_version,
-	uint32_t basic_parameter_table_offset,
-	size_t *page_size)
-{
-	int rv = EC_SUCCESS;
-	uint32_t dw;
-
-	if (basic_parameter_table_major_version == 1 &&
-	    basic_parameter_table_minor_version < 5) {
-		/* Use the Basic Flash Parameter v1.0 page size reporting. */
-		rv = spi_nor_read_sfdp_dword(
-			spi_nor_device, basic_parameter_table_offset, 1, &dw);
-		if (rv)
-			return rv;
-		if (SFDP_GET_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, dw))
-			*page_size = 64;
-		else
-			*page_size = 1;
-
-	} else if (basic_parameter_table_major_version == 1 &&
-		   basic_parameter_table_minor_version >= 5) {
-		/* Use the Basic Flash Parameter v1.5 page size reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 11, &dw);
-		if (rv)
-			return rv;
-		*page_size =
-			1 << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * Helper function to lookup the part's capacity in the SFDP Basic SPI Flash
- * NOR Parameter Table.
- */
-static int spi_nor_device_discover_sfdp_capacity(
-		struct spi_nor_device_t *spi_nor_device,
-		uint8_t basic_parameter_table_major_version,
-		uint8_t basic_parameter_table_minor_version,
-		uint32_t basic_parameter_table_offset,
-		uint32_t *capacity)
-{
-	int rv = EC_SUCCESS;
-	uint32_t dw;
-
-	/* First attempt to discover the device's capacity. */
-	if (basic_parameter_table_major_version == 1) {
-		/* Use the Basic Flash Parameter v1.0 capacity reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 2, &dw);
-		if (rv)
-			return rv;
-
-		if (SFDP_GET_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, dw)) {
-			/* Ensure the capacity is less than 4GiB. */
-			uint64_t tmp_capacity = 1 <<
-				(SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3);
-			if (tmp_capacity > UINT32_MAX)
-				return EC_ERROR_OVERFLOW;
-			*capacity = tmp_capacity;
-		} else {
-			*capacity =
-				1 +
-				(SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) >> 3);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
-				 uint32_t offset, size_t size, uint8_t *data)
-{
-	int rv;
-
-	/* Split up the read operation into multiple transactions if the size
-	 * is larger than the maximum read size.
-	 */
-	while (size > 0) {
-		size_t read_size =
-			MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE);
-		size_t read_command_size;
-
-		/* Set up the read command in the TX buffer. */
-		buf[0] = SPI_NOR_OPCODE_SLOW_READ;
-		if (spi_nor_device->in_4b_addressing_mode) {
-			buf[1] = (offset & 0xFF000000) >> 24;
-			buf[2] = (offset & 0xFF0000) >> 16;
-			buf[3] = (offset & 0xFF00) >> 8;
-			buf[4] = (offset & 0xFF);
-			read_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
-			buf[1] = (offset & 0xFF0000) >> 16;
-			buf[2] = (offset & 0xFF00) >> 8;
-			buf[3] = (offset & 0xFF);
-			read_command_size = 4;
-		}
-
-		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, read_command_size, data, read_size);
-		if (rv)
-			return rv;
-
-		data += read_size;
-		offset += read_size;
-		size -= read_size;
-	}
-	return EC_SUCCESS;
-}
-
-/******************************************************************************/
-/* External Serial NOR Flash API available to other modules. */
-
-/**
- * Initialize the module, assumes the Serial NOR Flash devices are currently
- * all available for initialization. As part of the initialization the driver
- * will check if the part has a compatible SFDP Basic Flash Parameter table
- * and update the part's page_size, capacity, and forces the addressing mode.
- * Parts with more than 16MiB of capacity are initialized into 4B addressing
- * and parts with less are initialized into 3B addressing mode.
- *
- * WARNING: This must successfully return before invoking any other Serial NOR
- * Flash APIs.
- */
-int spi_nor_init(void)
-{
-	int rv = EC_SUCCESS;
-	size_t i;
-
-	/* Initialize the state for each serial NOR flash device. */
-	for (i = 0; i < SPI_NOR_DEVICE_COUNT; i++) {
-		uint8_t sfdp_major_rev, sfdp_minor_rev;
-		uint8_t table_major_rev, table_minor_rev;
-		uint32_t table_offset;
-		size_t table_size;
-		struct spi_nor_device_t *spi_nor_device =
-			&spi_nor_devices[i];
-
-		rv |= locate_sfdp_basic_parameter_table(spi_nor_device,
-							&sfdp_major_rev,
-							&sfdp_minor_rev,
-							&table_major_rev,
-							&table_minor_rev,
-							&table_offset,
-							&table_size);
-
-		/* If we failed to find a compatible SFDP Basic Flash Parameter
-		 * table, use the default capacity, page size, and addressing
-		 * mode values. */
-		if (rv == EC_SUCCESS) {
-			size_t page_size = 0;
-			uint32_t capacity = 0;
-
-			rv |= spi_nor_device_discover_sfdp_page_size(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&page_size);
-			rv |= spi_nor_device_discover_sfdp_capacity(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&capacity);
-			if (rv == EC_SUCCESS) {
-				mutex_lock(&driver_mutex);
-				spi_nor_device->capacity = capacity;
-				spi_nor_device->page_size = page_size;
-				CPRINTS(spi_nor_device,
-					"Updated to SFDP params: %dKiB w/ %dB pages",
-					spi_nor_device->capacity >> 10,
-					spi_nor_device->page_size);
-				mutex_unlock(&driver_mutex);
-			}
-		}
-
-		/* Ensure the device is in a determined addressing state by
-		 * forcing a 4B addressing mode entry or exit depending on the
-		 * device capacity. If the device is larger than 16MiB, enter
-		 * 4B addressing mode. */
-		rv |= spi_nor_set_4b_mode(spi_nor_device,
-					  spi_nor_device->capacity > 0x1000000);
-	}
-
-	return rv;
-}
-
-/**
- * Forces the Serial NOR Flash device to enter (or exit) 4 Byte addressing mode.
- *
- * WARNING:
- * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
- * 2) If there's a second SPI controller communicating with this Serial
- *    NOR Flash part on the board, the user is responsible for ensuring
- *    addressing mode compatibility and cooperation.
- * 3) The user must ensure that multiple users do not trample on each other
- *    by having multiple parties changing the device's addressing mode.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param enter_4b_addressing_mode Whether to enter (1) or exit (0) 4B mode.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
-			int enter_4b_addressing_mode)
-{
-	uint8_t cmd;
-	int rv;
-
-	rv = spi_nor_write_enable(spi_nor_device);
-	if (rv)
-		return rv;
-
-	if (enter_4b_addressing_mode)
-		cmd = SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B;
-	else
-		cmd = SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B;
-
-	/* Claim the driver mutex to modify the device state. */
-	mutex_lock(&driver_mutex);
-
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, NULL, 0);
-	if (rv == EC_SUCCESS) {
-		spi_nor_device->in_4b_addressing_mode =
-			enter_4b_addressing_mode;
-	}
-
-	CPRINTS(spi_nor_device, "Entered %s Addressing Mode",
-		enter_4b_addressing_mode ? "4-Byte" : "3-Byte");
-
-	/* Release the driver mutex. */
-	mutex_unlock(&driver_mutex);
-	return rv;
-}
-
-/**
- * Read JEDEC Identifier.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param size Number of Bytes to read.
- * @param data Destination buffer for data.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
-			  size_t size, uint8_t *data) {
-	int rv;
-	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
-
-	if (size > CONFIG_SPI_NOR_MAX_READ_SIZE)
-		return EC_ERROR_INVAL;
-	/* Claim the driver mutex. */
-	mutex_lock(&driver_mutex);
-	/* Read the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, data, size);
-	/* Release the driver mutex. */
-	mutex_unlock(&driver_mutex);
-
-	return rv;
-}
-
-/**
- * Read from the Serial NOR Flash device.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to read.
- * @param size Number of Bytes to read.
- * @param data Destination buffer for data.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data)
-{
-	int rv;
-
-	/* Claim the driver mutex. */
-	mutex_lock(&driver_mutex);
-	rv = spi_nor_read_internal(spi_nor_device, offset, size, data);
-	/* Release the driver mutex. */
-	mutex_unlock(&driver_mutex);
-
-	return rv;
-}
-
-/**
- * Erase flash on the Serial Flash Device.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to erase, must be aligned to the minimum physical
- *               erase size.
- * @param size Number of Bytes to erase, must be a multiple of the the minimum
- *             physical erase size.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
-		  uint32_t offset, size_t size)
-{
-	int rv = EC_SUCCESS;
-	size_t erase_command_size, erase_size;
-	uint8_t erase_opcode;
-#ifdef CONFIG_SPI_NOR_SMART_ERASE
-	BUILD_ASSERT((CONFIG_SPI_NOR_MAX_READ_SIZE % 4) == 0);
-	uint8_t buffer[CONFIG_SPI_NOR_MAX_READ_SIZE] __aligned(4);
-	size_t verify_offset, read_offset, read_size, read_left;
-#endif
-
-	/* Invalid input */
-	if ((offset % 4096 != 0) || (size % 4096 != 0) || (size < 4096))
-		return EC_ERROR_INVAL;
-
-	/* Claim the driver mutex. */
-	mutex_lock(&driver_mutex);
-
-	while (size > 0) {
-		erase_opcode = SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE;
-		erase_size = 4096;
-
-		/* Wait for the previous operation to finish. */
-		rv = spi_nor_wait(spi_nor_device);
-		if (rv)
-			goto err_free;
-
-#ifdef CONFIG_SPI_NOR_BLOCK_ERASE
-		if (!(offset % 65536) && size >= 65536) {
-			erase_opcode =
-				SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE;
-			erase_size = 65536;
-		}
-#endif
-#ifdef CONFIG_SPI_NOR_SMART_ERASE
-		read_offset = offset;
-		read_left = erase_size;
-		while (read_left) {
-			read_size = MIN(read_left,
-					CONFIG_SPI_NOR_MAX_READ_SIZE);
-			/* Since CONFIG_SPI_NOR_MAX_READ_SIZE & erase_size are
-			 * both guaranteed to be multiples of 4.
-			 */
-			assert(read_size >= 4 && (read_size % 4) == 0);
-			rv = spi_nor_read_internal(spi_nor_device, read_offset,
-						   read_size, buffer);
-
-			/* Note: the return value here is lost below
-			 * at the write enable, this is not a problem,
-			 * as this code is only an optimisation, if it
-			 * fails, the full erase functionality still
-			 * gets done, and the error from that returned
-			 */
-			if (rv != EC_SUCCESS)
-				break;
-			/* Aligned word verify reduced the overall (read +
-			 * verify) time by ~20% (vs bytewise verify) on
-			 * an m3@24MHz & SPI@24MHz.
-			 */
-			verify_offset = 0;
-			while (verify_offset <= read_size - 4) {
-				if (*(uint32_t *)(buffer + verify_offset)
-				    != 0xffffffff) {
-					break;
-				}
-				verify_offset += 4;
-			}
-			if (verify_offset != read_size)
-				break;
-			read_offset += read_size;
-			read_left -= read_size;
-			watchdog_reload();
-		}
-		if (!read_left) {
-			/* Sector/block already erased. */
-			CPRINTS(spi_nor_device,
-				"Skipping erase [%x:%x] "
-				"(already erased)",
-				offset, erase_size);
-			offset += erase_size;
-			size -= erase_size;
-			continue;
-		}
-#endif
-		/* Enable writing to serial NOR flash. */
-		rv = spi_nor_write_enable(spi_nor_device);
-		if (rv)
-			goto err_free;
-
-		/* Set up the erase instruction. */
-		buf[0] = erase_opcode;
-		if (spi_nor_device->in_4b_addressing_mode) {
-			buf[1] = (offset & 0xFF000000) >> 24;
-			buf[2] = (offset & 0xFF0000) >> 16;
-			buf[3] = (offset & 0xFF00) >> 8;
-			buf[4] = (offset & 0xFF);
-			erase_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
-			buf[1] = (offset & 0xFF0000) >> 16;
-			buf[2] = (offset & 0xFF00) >> 8;
-			buf[3] = (offset & 0xFF);
-			erase_command_size = 4;
-		}
-
-		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, erase_command_size, NULL, 0);
-		if (rv)
-			goto err_free;
-
-		offset += erase_size;
-		size -= erase_size;
-	}
-
-	/* Wait for the previous operation to finish. */
-	rv = spi_nor_wait(spi_nor_device);
-
-err_free:
-	/* Release the driver mutex. */
-	mutex_unlock(&driver_mutex);
-
-	return rv;
-}
-
-/**
- * Write to the Serial NOR Flash device. Assumes already erased.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to write.
- * @param size Number of Bytes to write.
- * @param data Data to write to flash.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
-		  uint32_t offset, size_t size, const uint8_t *data)
-{
-	int rv = EC_SUCCESS;
-	size_t effective_page_size;
-
-	/* Claim the driver mutex. */
-	mutex_lock(&driver_mutex);
-
-	/* Ensure the device's page size fits in the driver's buffer, if not
-	 * emulate a smaller page size based on the buffer size. */
-	effective_page_size = MIN(spi_nor_device->page_size,
-			       CONFIG_SPI_NOR_MAX_WRITE_SIZE);
-
-	/* Split the write into multiple writes if the size is too large. */
-	while (size > 0) {
-		size_t prefix_size;
-		/* Figure out the size of the next write within 1 page. */
-		uint32_t page_offset = offset & (effective_page_size - 1);
-		size_t write_size =
-			MIN(size, effective_page_size - page_offset);
-
-		/* Wait for the previous operation to finish. */
-		rv = spi_nor_wait(spi_nor_device);
-		if (rv)
-			goto err_free;
-
-		/* Enable writing to serial NOR flash. */
-		rv = spi_nor_write_enable(spi_nor_device);
-		if (rv)
-			goto err_free;
-
-		/* Set up the page program command. */
-		buf[0] = SPI_NOR_OPCODE_PAGE_PROGRAM;
-		if (spi_nor_device->in_4b_addressing_mode) {
-			buf[1] = (offset & 0xFF000000) >> 24;
-			buf[2] = (offset & 0xFF0000) >> 16;
-			buf[3] = (offset & 0xFF00) >> 8;
-			buf[4] = (offset & 0xFF);
-			prefix_size = 5;
-		} else {  /* in 3 byte addressing mode */
-			buf[1] = (offset & 0xFF0000) >> 16;
-			buf[2] = (offset & 0xFF00) >> 8;
-			buf[3] = (offset & 0xFF);
-			prefix_size = 4;
-		}
-		/* Copy data to write into the buffer after the prefix. */
-		memmove(buf + prefix_size, data, write_size);
-
-		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, prefix_size + write_size, NULL, 0);
-		if (rv)
-			goto err_free;
-
-		data += write_size;
-		offset += write_size;
-		size -= write_size;
-	}
-
-	/* Wait for the previous operation to finish. */
-	rv = spi_nor_wait(spi_nor_device);
-
-err_free:
-	/* Release the driver mutex. */
-	mutex_unlock(&driver_mutex);
-
-	return rv;
-}
-
-/******************************************************************************/
-/* Serial NOR Flash console commands. */
-
-#ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_info(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-
-	uint8_t sfdp_major_rev, sfdp_minor_rev;
-	uint8_t table_major_rev, table_minor_rev;
-	uint32_t table_offset;
-	uint8_t mfn_bank = 0, mfn_id = 0;
-	size_t table_size;
-	const struct spi_nor_device_t *spi_nor_device = 0;
-	int spi_nor_device_index = 0;
-	int spi_nor_device_index_limit = spi_nor_devices_used - 1;
-
-	/* Set the device index limits if a device was specified. */
-	if (argc == 2) {
-		spi_nor_device_index = strtoi(argv[1], NULL, 0);
-		if (spi_nor_device_index >= spi_nor_devices_used)
-			return EC_ERROR_PARAM1;
-		spi_nor_device_index_limit = spi_nor_device_index;
-	} else if (argc != 1) {
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	for (; spi_nor_device_index <= spi_nor_device_index_limit;
-	     spi_nor_device_index++) {
-		spi_nor_device = &spi_nor_devices[spi_nor_device_index];
-
-		ccprintf("Serial NOR Flash Device %d:\n", spi_nor_device_index);
-		ccprintf("\tName: %s\n", spi_nor_device->name);
-		ccprintf("\tSPI controller index: %d\n",
-			 spi_nor_device->spi_controller);
-		ccprintf("\tTimeout: %d uSec\n",
-			 spi_nor_device->timeout_usec);
-		ccprintf("\tCapacity: %d KiB\n",
-			 spi_nor_device->capacity >> 10),
-		ccprintf("\tAddressing: %s addressing mode\n",
-			 spi_nor_device->in_4b_addressing_mode ? "4B" : "3B");
-		ccprintf("\tPage Size: %d Bytes\n",
-			 spi_nor_device->page_size);
-
-		/* Get JEDEC ID info. */
-		rv = spi_nor_read_jedec_mfn_id(spi_nor_device, &mfn_bank,
-					       &mfn_id);
-		if (rv != EC_SUCCESS)
-			return rv;
-		ccprintf("\tJEDEC ID bank %d manufacturing code 0x%x\n",
-			 mfn_bank, mfn_id);
-
-		/* Get SFDP info. */
-		if (locate_sfdp_basic_parameter_table(
-			spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
-			&table_major_rev, &table_minor_rev, &table_offset,
-			&table_size) != EC_SUCCESS) {
-			ccputs("\tNo JEDEC SFDP support detected\n");
-			continue;  /* Go on to the next device. */
-		}
-		ccprintf("\tSFDP v%d.%d\n", sfdp_major_rev, sfdp_minor_rev);
-		ccprintf("\tFlash Parameter Table v%d.%d (%dB @ 0x%x)\n",
-			 table_major_rev, table_minor_rev,
-			 table_size, table_offset);
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info,
-			"[device]",
-			"Report Serial NOR Flash device information");
-#endif  /* CONFIG_CMD_SPI_NOR */
-
-#ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_erase(int argc, char **argv)
-{
-	const struct spi_nor_device_t *spi_nor_device;
-	int spi_nor_device_index;
-	int offset = 0;
-	int size = 4096;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	spi_nor_device_index = strtoi(argv[1], NULL, 0);
-	if (spi_nor_device_index >= spi_nor_devices_used)
-		return EC_ERROR_PARAM1;
-	spi_nor_device = &spi_nor_devices[spi_nor_device_index];
-
-	rv = parse_offset_size(argc, argv, 2, &offset, &size);
-	if (rv)
-		return rv;
-
-	ccprintf("Erasing %d bytes at 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
-	return spi_nor_erase(spi_nor_device, offset, size);
-}
-DECLARE_CONSOLE_COMMAND(spinorerase, command_spi_nor_erase,
-			"device [offset] [size]",
-			"Erase flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
-
-#ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_write(int argc, char **argv)
-{
-	const struct spi_nor_device_t *spi_nor_device;
-	int spi_nor_device_index;
-	int offset = 0;
-	int size = CONFIG_SPI_NOR_MAX_WRITE_SIZE;
-	int rv;
-	char *data;
-	int i;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	spi_nor_device_index = strtoi(argv[1], NULL, 0);
-	if (spi_nor_device_index >= spi_nor_devices_used)
-		return EC_ERROR_PARAM1;
-	spi_nor_device = &spi_nor_devices[spi_nor_device_index];
-
-	rv = parse_offset_size(argc, argv, 2, &offset, &size);
-	if (rv)
-		return rv;
-
-	if (size > shared_mem_size())
-		size = shared_mem_size();
-
-	/* Acquire the shared memory buffer */
-	rv = shared_mem_acquire(size, &data);
-	if (rv) {
-		ccputs("Can't get shared mem\n");
-		return rv;
-	}
-
-	/* Fill the data buffer with a pattern */
-	for (i = 0; i < size; i++)
-		data[i] = i;
-
-	ccprintf("Writing %d bytes to 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
-	rv = spi_nor_write(spi_nor_device, offset, size, data);
-
-	/* Free the buffer */
-	shared_mem_release(data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spinorwrite, command_spi_nor_write,
-			"device [offset] [size]",
-			"Write pattern to flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
-
-#ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_read(int argc, char **argv)
-{
-	const struct spi_nor_device_t *spi_nor_device;
-	int spi_nor_device_index;
-	int offset = 0;
-	int size = CONFIG_SPI_NOR_MAX_READ_SIZE;
-	int rv;
-	char *data;
-	int i;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	spi_nor_device_index = strtoi(argv[1], NULL, 0);
-	if (spi_nor_device_index >= spi_nor_devices_used)
-		return EC_ERROR_PARAM1;
-	spi_nor_device = &spi_nor_devices[spi_nor_device_index];
-
-	rv = parse_offset_size(argc, argv, 2, &offset, &size);
-	if (rv)
-		return rv;
-
-	if (size > shared_mem_size())
-		size = shared_mem_size();
-
-	/* Acquire the shared memory buffer */
-	rv = shared_mem_acquire(size, &data);
-	if (rv) {
-		ccputs("Can't get shared mem\n");
-		return rv;
-	}
-
-	/* Read the data */
-	ccprintf("Reading %d bytes from %s...",
-		 size, spi_nor_device->name);
-	if (spi_nor_read(spi_nor_device, offset, size, data)) {
-		rv = EC_ERROR_INVAL;
-		goto err_free;
-	}
-
-	/* Dump it */
-	for (i = 0; i < size; i++) {
-		if ((offset + i) % 16) {
-			ccprintf(" %02x", data[i]);
-		} else {
-			ccprintf("\n%08x: %02x", offset + i, data[i]);
-			cflush();
-		}
-	}
-	ccprintf("\n");
-
-err_free:
-	/* Free the buffer */
-	shared_mem_release(data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(spinorread, command_spi_nor_read,
-			"device [offset] [size]",
-			"Read flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
diff --git a/common/stillness_detector.c b/common/stillness_detector.c
deleted file mode 100644
index c33472aa22..0000000000
--- a/common/stillness_detector.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "stillness_detector.h"
-#include "timer.h"
-#include <string.h>
-
-static void still_det_reset(struct still_det *still_det)
-{
-	still_det->num_samples = 0;
-	still_det->acc_x = FLOAT_TO_FP(0.0f);
-	still_det->acc_y = FLOAT_TO_FP(0.0f);
-	still_det->acc_z = FLOAT_TO_FP(0.0f);
-	still_det->acc_xx = FLOAT_TO_FP(0.0f);
-	still_det->acc_yy = FLOAT_TO_FP(0.0f);
-	still_det->acc_zz = FLOAT_TO_FP(0.0f);
-}
-
-static bool stillness_batch_complete(struct still_det *still_det,
-				     uint32_t sample_time)
-{
-	bool complete = false;
-	uint32_t batch_window = time_until(still_det->window_start_time,
-					   sample_time);
-
-	/* Checking if enough data is accumulated */
-	if (batch_window >= still_det->min_batch_window &&
-	    still_det->num_samples > still_det->min_batch_size) {
-		if (batch_window <= still_det->max_batch_window) {
-			complete = true;
-		} else {
-			/* Checking for too long batch window, reset and start
-			 * over
-			 */
-			still_det_reset(still_det);
-		}
-	} else if (batch_window > still_det->min_batch_window &&
-		   still_det->num_samples < still_det->min_batch_size) {
-		/* Not enough samples collected, reset and start over */
-		still_det_reset(still_det);
-	}
-	return complete;
-}
-
-static inline fp_t compute_variance(fp_t acc_squared, fp_t acc, fp_t inv)
-{
-	/* (acc^2 - (acc * acc * inv)) * inv */
-	return fp_mul((acc_squared - fp_mul(fp_sq(acc), inv)), inv);
-}
-
-bool still_det_update(struct still_det *still_det, uint32_t sample_time,
-		      fp_t x, fp_t y, fp_t z)
-{
-	fp_t inv = FLOAT_TO_FP(0.0f), var_x, var_y, var_z;
-	bool complete = false;
-
-	/* Accumulate for mean and VAR */
-	still_det->acc_x += x;
-	still_det->acc_y += y;
-	still_det->acc_z += z;
-	still_det->acc_xx += fp_mul(x, x);
-	still_det->acc_yy += fp_mul(y, y);
-	still_det->acc_zz += fp_mul(z, z);
-
-	switch (++still_det->num_samples) {
-	case 0:
-		/* If we rolled over, go back. */
-		still_det->num_samples--;
-		break;
-	case 1:
-		/* Set a new start time if new batch. */
-		still_det->window_start_time = sample_time;
-		break;
-	}
-
-	if (stillness_batch_complete(still_det, sample_time)) {
-		/*
-		 * Compute 1/num_samples and check for num_samples == 0 (should
-		 * never happen, but just in case)
-		 */
-		if (still_det->num_samples) {
-			inv = fp_div(1.0f, INT_TO_FP(still_det->num_samples));
-		} else {
-			still_det_reset(still_det);
-			return complete;
-		}
-		/* Calculating the VAR = sum(x^2)/n - sum(x)^2/n^2 */
-		var_x = compute_variance(
-			still_det->acc_xx, still_det->acc_x, inv);
-		var_y = compute_variance(
-			still_det->acc_yy, still_det->acc_y, inv);
-		var_z = compute_variance(
-			still_det->acc_zz, still_det->acc_z, inv);
-		/* Checking if sensor is still */
-		if (var_x < still_det->var_threshold &&
-		    var_y < still_det->var_threshold &&
-		    var_z < still_det->var_threshold) {
-			still_det->mean_x = fp_mul(still_det->acc_x, inv);
-			still_det->mean_y = fp_mul(still_det->acc_y, inv);
-			still_det->mean_z = fp_mul(still_det->acc_z, inv);
-			complete = true;
-		}
-		/* Reset and start over */
-		still_det_reset(still_det);
-	}
-	return complete;
-}
diff --git a/common/switch.c b/common/switch.c
deleted file mode 100644
index 2c1ea804a8..0000000000
--- a/common/switch.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Switch module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "switch.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
-
-static uint8_t *memmap_switches;
-
-/**
- * Update status of non-debounced switches.
- *
- * Note that deferred functions are called in the same context as lid and
- * power button changes, so we don't need a mutex.
- */
-static void switch_update(void)
-{
-	static uint8_t prev;
-
-	/* Make sure this is safe to call before power_button_init() */
-	if (!memmap_switches)
-		return;
-
-	prev = *memmap_switches;
-
-	if (power_button_is_pressed())
-		*memmap_switches |= EC_SWITCH_POWER_BUTTON_PRESSED;
-	else
-		*memmap_switches &= ~EC_SWITCH_POWER_BUTTON_PRESSED;
-
-	if (!IS_ENABLED(CONFIG_LID_SWITCH) || lid_is_open())
-		*memmap_switches |= EC_SWITCH_LID_OPEN;
-	else
-		*memmap_switches &= ~EC_SWITCH_LID_OPEN;
-
-	if ((crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) == 0)
-		*memmap_switches |= EC_SWITCH_WRITE_PROTECT_DISABLED;
-	else
-		*memmap_switches &= ~EC_SWITCH_WRITE_PROTECT_DISABLED;
-
-#ifdef CONFIG_SWITCH_DEDICATED_RECOVERY
-	if (gpio_get_level(GPIO_RECOVERY_L) == 0)
-		*memmap_switches |= EC_SWITCH_DEDICATED_RECOVERY;
-	else
-		*memmap_switches &= ~EC_SWITCH_DEDICATED_RECOVERY;
-#endif
-
-	if (prev != *memmap_switches)
-		CPRINTS("SW 0x%02x", *memmap_switches);
-}
-DECLARE_DEFERRED(switch_update);
-DECLARE_HOOK(HOOK_LID_CHANGE, switch_update, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, switch_update, HOOK_PRIO_DEFAULT);
-
-static void switch_init(void)
-{
-	/* Set up memory-mapped switch positions */
-	memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
-	*memmap_switches = 0;
-
-	switch_update();
-
-	/* Switch data is now present */
-	*host_get_memmap(EC_MEMMAP_SWITCHES_VERSION) = 1;
-
-#ifdef CONFIG_SWITCH_DEDICATED_RECOVERY
-	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_RECOVERY_L);
-#endif
-
-	/*
-	 * TODO(crosbug.com/p/23793): It's weird that flash_common.c owns
-	 * reading the write protect signal, but we enable the interrupt for it
-	 * here.  Take ownership of WP back, or refactor it to its own module.
-	 */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	gpio_enable_interrupt(GPIO_WP);
-#else
-	gpio_enable_interrupt(GPIO_WP_L);
-#endif
-}
-DECLARE_HOOK(HOOK_INIT, switch_init, HOOK_PRIO_INIT_SWITCH);
-
-void switch_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&switch_update_data, 0);
-}
-
-#ifdef CONFIG_CMD_MMAPINFO
-static int command_mmapinfo(int argc, char **argv)
-{
-	uint8_t *memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
-	uint8_t val = *memmap_switches;
-	int i;
-	const char *explanation[] = {
-		"lid_open",
-		"powerbtn",
-		"wp_off",
-		"kbd_rec",
-		"gpio_rec",
-		"fake_dev",
-	};
-	ccprintf("memmap switches = 0x%x\n", val);
-	for (i = 0; i < ARRAY_SIZE(explanation); i++)
-		if (val & BIT(i))
-			ccprintf(" %s\n", explanation[i]);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo,
-			NULL,
-			"Print memmap switch state");
-#endif
diff --git a/common/temp_sensor.c b/common/temp_sensor.c
deleted file mode 100644
index 69d440a6d5..0000000000
--- a/common/temp_sensor.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "timer.h"
-#include "util.h"
-
-#ifdef CONFIG_ZEPHYR
-#include "temp_sensor/temp_sensor.h"
-#endif
-
-int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
-{
-	const struct temp_sensor_t *sensor;
-
-	if (id < 0 || id >= TEMP_SENSOR_COUNT)
-		return EC_ERROR_INVAL;
-	sensor = temp_sensors + id;
-
-#ifdef CONFIG_ZEPHYR
-	return sensor->read(sensor, temp_ptr);
-#else
-	return sensor->read(sensor->idx, temp_ptr);
-#endif
-}
-
-static void update_mapped_memory(void)
-{
-	int i, t;
-	uint8_t *mptr = host_get_memmap(EC_MEMMAP_TEMP_SENSOR);
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; i++, mptr++) {
-		/*
-		 * Switch to second range if first one is full, or stop if
-		 * second range is also full.
-		 */
-		if (i == EC_TEMP_SENSOR_ENTRIES)
-			mptr = host_get_memmap(EC_MEMMAP_TEMP_SENSOR_B);
-		else if (i >= EC_TEMP_SENSOR_ENTRIES +
-			 EC_TEMP_SENSOR_B_ENTRIES)
-			break;
-
-		switch (temp_sensor_read(i, &t)) {
-		case EC_ERROR_NOT_POWERED:
-			*mptr = EC_TEMP_SENSOR_NOT_POWERED;
-			break;
-		case EC_ERROR_NOT_CALIBRATED:
-			*mptr = EC_TEMP_SENSOR_NOT_CALIBRATED;
-			break;
-		case EC_SUCCESS:
-			*mptr = t - EC_TEMP_SENSOR_OFFSET;
-			break;
-		default:
-			*mptr = EC_TEMP_SENSOR_ERROR;
-		}
-	}
-}
-/* Run after other TEMP tasks, so sensors will have updated first. */
-DECLARE_HOOK(HOOK_SECOND, update_mapped_memory, HOOK_PRIO_TEMP_SENSOR_DONE);
-
-static void temp_sensor_init(void)
-{
-	int i;
-	uint8_t *base, *base_b;
-
-	/*
-	 * Initialize memory-mapped data so that if a temperature value is read
-	 * before we actually poll the sensors, we don't return an impossible
-	 * or out-of-range value.
-	 */
-	base = host_get_memmap(EC_MEMMAP_TEMP_SENSOR);
-	base_b = host_get_memmap(EC_MEMMAP_TEMP_SENSOR_B);
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		if (i < EC_TEMP_SENSOR_ENTRIES)
-			base[i] = EC_TEMP_SENSOR_DEFAULT;
-		else
-			base_b[i - EC_TEMP_SENSOR_ENTRIES] =
-				EC_TEMP_SENSOR_DEFAULT;
-	}
-
-	/* Set the rest of memory region to SENSOR_NOT_PRESENT */
-	for (; i < EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES; ++i) {
-		if (i < EC_TEMP_SENSOR_ENTRIES)
-			base[i] = EC_TEMP_SENSOR_NOT_PRESENT;
-		else
-			base_b[i - EC_TEMP_SENSOR_ENTRIES] =
-				EC_TEMP_SENSOR_NOT_PRESENT;
-	}
-
-	/* Temp sensor data is present, with B range supported. */
-	*host_get_memmap(EC_MEMMAP_THERMAL_VERSION) = 2;
-}
-DECLARE_HOOK(HOOK_INIT, temp_sensor_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-int console_command_temps(int argc, char **argv)
-{
-	int t, i;
-	int rv, rv1 = EC_SUCCESS;
-
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-		ccprintf("  %-20s: ", temp_sensors[i].name);
-		rv = temp_sensor_read(i, &t);
-		if (rv)
-			rv1 = rv;
-
-		switch (rv) {
-		case EC_SUCCESS:
-			ccprintf("%d K = %d C", t, K_TO_C(t));
-#ifdef CONFIG_THROTTLE_AP
-			if (thermal_params[i].temp_fan_off &&
-			    thermal_params[i].temp_fan_max)
-				ccprintf("  %d%%",
-					 thermal_fan_percent(
-						 thermal_params[i].temp_fan_off,
-						 thermal_params[i].temp_fan_max,
-						 t));
-#endif
-			ccprintf("\n");
-			break;
-		case EC_ERROR_NOT_POWERED:
-			ccprintf("Not powered\n");
-			break;
-		case EC_ERROR_NOT_CALIBRATED:
-			ccprintf("Not calibrated\n");
-			break;
-		default:
-			ccprintf("Error %d\n", rv);
-		}
-	}
-
-	return rv1;
-}
-DECLARE_CONSOLE_COMMAND(temps, console_command_temps,
-			NULL,
-			"Print temp sensors");
-#endif
-
-/*****************************************************************************/
-/* Host commands */
-
-enum ec_status temp_sensor_command_get_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_temp_sensor_get_info *p = args->params;
-	struct ec_response_temp_sensor_get_info *r = args->response;
-	int id = p->id;
-
-	if (id >= TEMP_SENSOR_COUNT)
-		return EC_RES_ERROR;
-
-	strzcpy(r->sensor_name, temp_sensors[id].name, sizeof(r->sensor_name));
-	r->sensor_type = temp_sensors[id].type;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO,
-		     temp_sensor_command_get_info,
-		     EC_VER_MASK(0));
diff --git a/common/test_util.c b/common/test_util.c
deleted file mode 100644
index b23f85509b..0000000000
--- a/common/test_util.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test utilities.
- */
-
-#if defined(TEST_COVERAGE) || defined(TEST_HOSTTEST)
-/* We need signal() and exit() only when building to run on the host. */
-#include <signal.h>
-#include <stdlib.h>
-#endif
-
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "util.h"
-
-struct test_util_tag {
-	uint8_t error_count;
-};
-
-#define TEST_UTIL_SYSJUMP_TAG 0x5455 /* "TU" */
-#define TEST_UTIL_SYSJUMP_VERSION 1
-
-int __test_error_count;
-
-/* Weak reference function as an entry point for unit test */
-test_mockable void run_test(int argc, char **argv) { }
-
-/* Default mock test init */
-test_mockable void test_init(void) { }
-
-/* Default mock before test */
-test_mockable void before_test(void) { }
-
-/* Default mock after test */
-test_mockable void after_test(void) { }
-
-#ifdef TEST_COVERAGE
-extern void __gcov_flush(void);
-
-void emulator_flush(void)
-{
-	__gcov_flush();
-}
-#else
-void emulator_flush(void)
-{
-}
-#endif
-
-#if defined(TEST_HOSTTEST) || defined(TEST_COVERAGE)
-/* Host-based unit tests need to exit(0) when they receive a SIGTERM. */
-void test_end_hook(int sig)
-{
-	emulator_flush();
-	exit(0);
-}
-
-void register_test_end_hook(void)
-{
-	signal(SIGTERM, test_end_hook);
-}
-#else
-void register_test_end_hook(void)
-{
-}
-#endif
-
-void test_reset(void)
-{
-	if (!system_jumped_to_this_image())
-		__test_error_count = 0;
-}
-
-void test_pass(void)
-{
-	ccprintf("Pass!\n");
-}
-
-void test_fail(void)
-{
-	ccprintf("Fail!\n");
-}
-
-void test_print_result(void)
-{
-	if (__test_error_count)
-		ccprintf("Fail! (%d tests)\n", __test_error_count);
-	else
-		ccprintf("Pass!\n");
-}
-
-int test_get_error_count(void)
-{
-	return __test_error_count;
-}
-
-uint32_t test_get_state(void)
-{
-	uint32_t state;
-
-	system_get_scratchpad(&state);
-	return state;
-}
-
-test_mockable void test_clean_up(void)
-{
-}
-
-void test_reboot_to_next_step(enum test_state_t step)
-{
-	ccprintf("Rebooting to next test step...\n");
-	cflush();
-	system_set_scratchpad(TEST_STATE_MASK(step));
-	system_reset(SYSTEM_RESET_HARD);
-}
-
-test_mockable void test_run_step(uint32_t state)
-{
-}
-
-void test_run_multistep(void)
-{
-	uint32_t state = test_get_state();
-
-	if (state & TEST_STATE_MASK(TEST_STATE_PASSED)) {
-		test_clean_up();
-		system_set_scratchpad(0);
-		test_pass();
-	} else if (state & TEST_STATE_MASK(TEST_STATE_FAILED)) {
-		test_clean_up();
-		system_set_scratchpad(0);
-		test_fail();
-	}
-
-	if (state & TEST_STATE_STEP_1 || state == 0) {
-		task_wait_event(-1); /* Wait for run_test() */
-		test_run_step(TEST_STATE_MASK(TEST_STATE_STEP_1));
-	} else {
-		test_run_step(state);
-	}
-}
-
-#ifdef HAS_TASK_HOSTCMD
-int test_send_host_command(int command, int version, const void *params,
-			   int params_size, void *resp, int resp_size)
-{
-	struct host_cmd_handler_args args;
-
-	args.version = version;
-	args.command = command;
-	args.params = params;
-	args.params_size = params_size;
-	args.response = resp;
-	args.response_max = resp_size;
-	args.response_size = 0;
-
-	return host_command_process(&args);
-}
-#endif  /* TASK_HAS_HOSTCMD */
-
-/* Linear congruential pseudo random number generator */
-uint32_t prng(uint32_t seed)
-{
-	return 22695477 * seed + 1;
-}
-
-uint32_t prng_no_seed(void)
-{
-	static uint32_t seed = 0x1234abcd;
-	return seed = prng(seed);
-}
-
-static void restore_state(void)
-{
-	const struct test_util_tag *tag;
-	int version, size;
-
-	tag = (const struct test_util_tag *)system_get_jump_tag(
-		TEST_UTIL_SYSJUMP_TAG, &version, &size);
-	if (tag && version == TEST_UTIL_SYSJUMP_VERSION &&
-	    size == sizeof(*tag))
-		__test_error_count = tag->error_count;
-	else
-		__test_error_count = 0;
-}
-DECLARE_HOOK(HOOK_INIT, restore_state, HOOK_PRIO_DEFAULT);
-
-static void preserve_state(void)
-{
-	struct test_util_tag tag;
-	tag.error_count = __test_error_count;
-	system_add_jump_tag(TEST_UTIL_SYSJUMP_TAG, TEST_UTIL_SYSJUMP_VERSION,
-			    sizeof(tag), &tag);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, preserve_state, HOOK_PRIO_DEFAULT);
-
-static int command_run_test(int argc, char **argv)
-{
-	run_test(argc, argv);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(runtest, command_run_test,
-			NULL, NULL);
-
-#ifndef CONFIG_ZEPHYR
-void z_ztest_run_test_suite(const char *name, struct unit_test *suite)
-{
-	test_reset();
-
-	while (suite->test) {
-		suite->setup();
-		RUN_TEST(suite->test);
-		suite->teardown();
-		suite++;
-	}
-
-	ccprintf("%s: ", name);
-	test_print_result();
-}
-#endif /* CONFIG_ZEPHYR */
diff --git a/common/thermal.c b/common/thermal.c
deleted file mode 100644
index e9750931be..0000000000
--- a/common/thermal.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NEW thermal engine module for Chrome EC. This is a completely different
- * implementation from the original version that shipped on Link.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "temp_sensor.h"
-#include "thermal.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "util.h"
-
-#ifdef CONFIG_ZEPHYR
-#include "temp_sensor/temp_sensor.h"
-#endif
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-/*****************************************************************************/
-/* EC-specific thermal controls */
-
-test_mockable_static void smi_sensor_failure_warning(void)
-{
-	CPRINTS("can't read any temp sensors!");
-	host_set_single_event(EC_HOST_EVENT_THERMAL);
-}
-
-int thermal_fan_percent(int low, int high, int cur)
-{
-	if (cur < low)
-		return 0;
-	if (cur > high)
-		return 100;
-	return 100 * (cur - low) / (high - low);
-}
-
-/* The logic below is hard-coded for only three thresholds: WARN, HIGH, HALT.
- * This is just a validity check to be sure we catch any changes in thermal.h
- */
-BUILD_ASSERT(EC_TEMP_THRESH_COUNT == 3);
-
-/* Keep track of which thresholds have triggered */
-static cond_t cond_hot[EC_TEMP_THRESH_COUNT];
-
-/* thermal sensor read delay */
-#if defined(CONFIG_TEMP_SENSOR_POWER_GPIO) && \
-	defined(CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS)
-static int first_read_delay = CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS;
-#endif
-
-static void thermal_control(void)
-{
-	int i, j, t, rv, f;
-	int count_over[EC_TEMP_THRESH_COUNT];
-	int count_under[EC_TEMP_THRESH_COUNT];
-	int num_valid_limits[EC_TEMP_THRESH_COUNT];
-	int num_sensors_read;
-	int fmax;
-	int temp_fan_configured;
-
-#ifdef CONFIG_CUSTOM_FAN_CONTROL
-	int temp[TEMP_SENSOR_COUNT];
-#endif
-
-	/* add delay to ensure thermal sensor is ready when EC boot */
-#if defined(CONFIG_TEMP_SENSOR_POWER_GPIO) && \
-	defined(CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS)
-	if (first_read_delay != 0) {
-		msleep(first_read_delay);
-		first_read_delay = 0;
-	}
-#endif
-
-	/* Get ready to count things */
-	memset(count_over, 0, sizeof(count_over));
-	memset(count_under, 0, sizeof(count_under));
-	memset(num_valid_limits, 0, sizeof(num_valid_limits));
-	num_sensors_read = 0;
-	fmax = 0;
-	temp_fan_configured = 0;
-
-	/* go through all the sensors */
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-
-		/* read one */
-		rv = temp_sensor_read(i, &t);
-
-#ifdef CONFIG_CUSTOM_FAN_CONTROL
-		/* Store all sensors value */
-		temp[i] = K_TO_C(t);
-#endif
-
-		if (rv != EC_SUCCESS)
-			continue;
-		else
-			num_sensors_read++;
-
-		/* check all the limits */
-		for (j = 0; j < EC_TEMP_THRESH_COUNT; j++) {
-			int limit = thermal_params[i].temp_host[j];
-			int release = thermal_params[i].temp_host_release[j];
-			if (limit) {
-				num_valid_limits[j]++;
-				if (t > limit) {
-					count_over[j]++;
-				} else if (release) {
-					if (t < release)
-						count_under[j]++;
-				} else if (t < limit) {
-					count_under[j]++;
-				}
-			}
-		}
-
-		/* figure out the max fan needed, too */
-		if (thermal_params[i].temp_fan_off &&
-		    thermal_params[i].temp_fan_max) {
-			f = thermal_fan_percent(thermal_params[i].temp_fan_off,
-						thermal_params[i].temp_fan_max,
-						t);
-			if (f > fmax)
-				fmax = f;
-
-			temp_fan_configured = 1;
-		}
-	}
-
-	if (!num_sensors_read) {
-		/*
-		 * Trigger a SMI event if we can't read any sensors.
-		 *
-		 * In theory we could do something more elaborate like forcing
-		 * the system to shut down if no sensors are available after
-		 * several retries.  This is a very unlikely scenario -
-		 * particularly on LM4-based boards, since the LM4 has its own
-		 * internal temp sensor.  It's most likely to occur during
-		 * bringup of a new board, where we haven't debugged the I2C
-		 * bus to the sensors; forcing a shutdown in that case would
-		 * merely hamper board bringup.
-		 *
-		 * If in G3, then there is no need trigger an SMI event since
-		 * the AP is off and this can be an expected state if
-		 * temperature sensors are powered by a power rail that's only
-		 * on if the AP is out of G3. Note this could be 'ANY_OFF' as
-		 * well, but that causes the thermal unit test to fail.
-		 */
-		if (!chipset_in_state(CHIPSET_STATE_HARD_OFF))
-			smi_sensor_failure_warning();
-		return;
-	}
-
-	/* See what the aggregated limits are. Any temp over the limit
-	 * means it's hot, but all temps have to be under the limit to
-	 * be cool again.
-	 */
-	for (j = 0; j < EC_TEMP_THRESH_COUNT; j++) {
-		if (count_over[j])
-			cond_set_true(&cond_hot[j]);
-		else if (count_under[j] == num_valid_limits[j])
-			cond_set_false(&cond_hot[j]);
-	}
-
-	/* What do we do about it? (note hard-coded logic). */
-
-	if (cond_went_true(&cond_hot[EC_TEMP_THRESH_HALT])) {
-		CPRINTS("thermal SHUTDOWN");
-
-		/* Print temperature sensor values before shutting down AP */
-		if (IS_ENABLED(CONFIG_CMD_TEMP_SENSOR)) {
-			console_command_temps(1, NULL);
-			cflush();
-		}
-
-		chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
-	} else if (cond_went_false(&cond_hot[EC_TEMP_THRESH_HALT])) {
-		/* We don't reboot automatically - the user has to push
-		 * the power button. It's likely that we can't even
-		 * detect this sensor transition until then, but we
-		 * do have to check in order to clear the cond_t.
-		 */
-		CPRINTS("thermal no longer shutdown");
-	}
-
-	if (cond_went_true(&cond_hot[EC_TEMP_THRESH_HIGH])) {
-		CPRINTS("thermal HIGH");
-		throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_THERMAL);
-	} else if (cond_went_false(&cond_hot[EC_TEMP_THRESH_HIGH])) {
-		CPRINTS("thermal no longer high");
-		throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_THERMAL);
-	}
-
-	if (cond_went_true(&cond_hot[EC_TEMP_THRESH_WARN])) {
-		CPRINTS("thermal WARN");
-		throttle_ap(THROTTLE_ON, THROTTLE_SOFT, THROTTLE_SRC_THERMAL);
-	} else if (cond_went_false(&cond_hot[EC_TEMP_THRESH_WARN])) {
-		CPRINTS("thermal no longer warn");
-		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT, THROTTLE_SRC_THERMAL);
-	}
-
-	if (temp_fan_configured) {
-#ifdef CONFIG_FANS
-#ifdef CONFIG_CUSTOM_FAN_CONTROL
-		for (i = 0; i < fan_get_count(); i++) {
-			if (!is_thermal_control_enabled(i))
-				continue;
-
-			board_override_fan_control(i, temp);
-		}
-#else
-		/* TODO(crosbug.com/p/23797): For now, we just treat all
-		 * fans the same. It would be better if we could assign
-		 * different thermal profiles to each fan - in case one
-		 * fan cools the CPU while another cools the radios or
-		 * battery.
-		 */
-		for (i = 0; i < fan_get_count(); i++)
-			fan_set_percent_needed(i, fmax);
-#endif
-#endif
-	}
-}
-
-/* Wait until after the sensors have been read */
-DECLARE_HOOK(HOOK_SECOND, thermal_control, HOOK_PRIO_TEMP_SENSOR_DONE);
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_thermalget(int argc, char **argv)
-{
-	int i;
-
-	ccprintf("sensor  warn  high  halt   fan_off fan_max   name\n");
-	for (i = 0; i < TEMP_SENSOR_COUNT; i++) {
-		ccprintf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-			 i,
-			 thermal_params[i].temp_host[EC_TEMP_THRESH_WARN],
-			 thermal_params[i].temp_host[EC_TEMP_THRESH_HIGH],
-			 thermal_params[i].temp_host[EC_TEMP_THRESH_HALT],
-			 thermal_params[i].temp_fan_off,
-			 thermal_params[i].temp_fan_max,
-			 temp_sensors[i].name);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget,
-			NULL,
-			"Print thermal parameters (degrees Kelvin)");
-
-
-static int command_thermalset(int argc, char **argv)
-{
-	unsigned int n;
-	int i, val;
-	char *e;
-
-	if (argc < 3 || argc > 7)
-		return EC_ERROR_PARAM_COUNT;
-
-	n = (unsigned int)strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	for (i = 2; i < argc; i++) {
-		val = strtoi(argv[i], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1 + i - 1;
-		if (val < 0)
-			continue;
-		switch (i) {
-		case 2:
-			thermal_params[n].temp_host[EC_TEMP_THRESH_WARN] = val;
-			break;
-		case 3:
-			thermal_params[n].temp_host[EC_TEMP_THRESH_HIGH] = val;
-			break;
-		case 4:
-			thermal_params[n].temp_host[EC_TEMP_THRESH_HALT] = val;
-			break;
-		case 5:
-			thermal_params[n].temp_fan_off = val;
-			break;
-		case 6:
-			thermal_params[n].temp_fan_max = val;
-			break;
-		}
-	}
-
-	command_thermalget(0, 0);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(thermalset, command_thermalset,
-			"sensor warn [high [shutdown [fan_off [fan_max]]]]",
-			"Set thermal parameters (degrees Kelvin)."
-			" Use -1 to skip.");
-
-/*****************************************************************************/
-/* Host commands. We'll reuse the host command number, but this is version 1,
- * not version 0. Different structs, different meanings.
- */
-
-static enum ec_status
-thermal_command_set_threshold(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_thermal_set_threshold_v1 *p = args->params;
-
-	if (p->sensor_num >= TEMP_SENSOR_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	thermal_params[p->sensor_num] = p->cfg;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_THERMAL_SET_THRESHOLD,
-		     thermal_command_set_threshold,
-		     EC_VER_MASK(1));
-
-static enum ec_status
-thermal_command_get_threshold(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_thermal_get_threshold_v1 *p = args->params;
-	struct ec_thermal_config *r = args->response;
-
-	if (p->sensor_num >= TEMP_SENSOR_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	*r = thermal_params[p->sensor_num];
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_THERMAL_GET_THRESHOLD,
-		     thermal_command_get_threshold,
-		     EC_VER_MASK(1));
diff --git a/common/throttle_ap.c b/common/throttle_ap.c
deleted file mode 100644
index cfa97d93a5..0000000000
--- a/common/throttle_ap.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common chipset throttling code for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "dptf.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "task.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-#define PROCHOT_IN_DEBOUNCE_US		(100 * MSEC)
-
-/*****************************************************************************/
-/* This enforces the virtual OR of all throttling sources. */
-K_MUTEX_DEFINE(throttle_mutex);
-static uint32_t throttle_request[NUM_THROTTLE_TYPES];
-static int debounced_prochot_in;
-static enum gpio_signal gpio_prochot_in = GPIO_COUNT;
-
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
-		 enum throttle_sources source)
-{
-	uint32_t tmpval, bitmask;
-
-	mutex_lock(&throttle_mutex);
-
-	bitmask = BIT(source);
-
-	switch (level) {
-	case THROTTLE_ON:
-		throttle_request[type] |= bitmask;
-		break;
-	case THROTTLE_OFF:
-		throttle_request[type] &= ~bitmask;
-		break;
-	}
-
-	tmpval = throttle_request[type];	/* save for printing */
-
-	switch (type) {
-	case THROTTLE_SOFT:
-#ifdef HAS_TASK_HOSTCMD
-		host_throttle_cpu(tmpval);
-#endif
-		break;
-	case THROTTLE_HARD:
-#ifdef CONFIG_CHIPSET_CAN_THROTTLE
-		chipset_throttle_cpu(tmpval);
-#endif
-		break;
-
-	case NUM_THROTTLE_TYPES:
-		/* Make the compiler shut up. Don't use 'default', because
-		 * we still want to catch any new types.
-		 */
-		break;
-	}
-
-	mutex_unlock(&throttle_mutex);
-
-	/* print outside the mutex */
-	CPRINTS("set AP throttling type %d to %s (0x%08x)",
-		type, tmpval ? "on" : "off", tmpval);
-
-}
-
-static void prochot_input_deferred(void)
-{
-	int prochot_in;
-
-	/*
-	 * Shouldn't be possible, but better to protect against buffer
-	 * overflow
-	 */
-	ASSERT(signal_is_gpio(gpio_prochot_in));
-
-	prochot_in = gpio_get_level(gpio_prochot_in);
-
-	if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW))
-		prochot_in = !prochot_in;
-
-	if (prochot_in == debounced_prochot_in)
-		return;
-
-	/*
-	 * b/173180788 Confirmed from Intel internal that SLP_S3# asserts low
-	 * about 10us before PROCHOT# asserts low, which means that
-	 * the CPU is already in reset and therefore the PROCHOT#
-	 * asserting low is normal behavior and not a concern
-	 * for PROCHOT# event.  Ignore all PROCHOT changes while the AP is off
-	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return;
-
-	debounced_prochot_in = prochot_in;
-
-	if (debounced_prochot_in) {
-		CPRINTS("External PROCHOT assertion detected");
-#ifdef CONFIG_FANS
-		dptf_set_fan_duty_target(100);
-#endif
-	} else {
-		CPRINTS("External PROCHOT condition cleared");
-#ifdef CONFIG_FANS
-		/* Revert to automatic control of the fan */
-		dptf_set_fan_duty_target(-1);
-#endif
-	}
-}
-DECLARE_DEFERRED(prochot_input_deferred);
-
-void throttle_ap_prochot_input_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Save the PROCHOT signal that generated the interrupt so we don't
-	 * rely on a specific pin name.
-	 */
-	if (gpio_prochot_in == GPIO_COUNT)
-		gpio_prochot_in = signal;
-
-	/*
-	 * Trigger deferred notification of PROCHOT change so we can ignore
-	 * any pulses that are too short.
-	 */
-	hook_call_deferred(&prochot_input_deferred_data,
-		PROCHOT_IN_DEBOUNCE_US);
-}
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_APTHROTTLE
-static int command_apthrottle(int argc, char **argv)
-{
-	int i;
-	uint32_t tmpval;
-
-	for (i = 0; i < NUM_THROTTLE_TYPES; i++) {
-		mutex_lock(&throttle_mutex);
-		tmpval = throttle_request[i];
-		mutex_unlock(&throttle_mutex);
-
-		ccprintf("AP throttling type %d is %s (0x%08x)\n", i,
-			 tmpval ? "on" : "off", tmpval);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle,
-			NULL,
-			"Display the AP throttling state");
-#endif
diff --git a/common/update_fw.c b/common/update_fw.c
deleted file mode 100644
index 068758e7b0..0000000000
--- a/common/update_fw.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "byteorder.h"
-#include "console.h"
-#include "flash.h"
-#include "hooks.h"
-#include "include/compile_time_macros.h"
-#include "rollback.h"
-#include "rwsig.h"
-#include "sha256.h"
-#include "system.h"
-#include "uart.h"
-#include "update_fw.h"
-#include "util.h"
-#include "vb21_struct.h"
-#include "vboot.h"
-
-#if defined(CONFIG_TOUCHPAD_VIRTUAL_OFF) && defined(CONFIG_TOUCHPAD_HASH_FW)
-#define CONFIG_TOUCHPAD_FW_CHUNKS \
-	(CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE)
-
-#include "touchpad_fw_hash.h"
-
-BUILD_ASSERT(sizeof(touchpad_fw_hashes) ==
-		(CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE));
-BUILD_ASSERT(sizeof(touchpad_fw_hashes[0]) == SHA256_DIGEST_SIZE);
-
-BUILD_ASSERT(sizeof(touchpad_fw_full_hash) == SHA256_DIGEST_SIZE);
-#endif
-
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/* Section to be updated (i.e. not the current section). */
-struct {
-	uint32_t base_offset;
-	uint32_t top_offset;
-} update_section;
-
-#ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
-/*
- * Check if a block is within touchpad FW virtual address region, and
- * is therefore meant to be flashed to the touchpad.
- */
-static int is_touchpad_block(uint32_t block_offset, size_t body_size)
-{
-	return (block_offset >= CONFIG_TOUCHPAD_VIRTUAL_OFF) &&
-	       (block_offset + body_size) <=
-			(CONFIG_TOUCHPAD_VIRTUAL_OFF +
-				CONFIG_TOUCHPAD_VIRTUAL_SIZE);
-}
-#endif
-
-/*
- * Verify that the passed in block fits into the valid area. If it does, and
- * is destined to the base address of the area - erase the area contents.
- *
- * Return success, or indication of an erase failure or chunk not fitting into
- * valid area.
- *
- * TODO(b/36375666): Each board/chip should be able to re-define this.
- */
-static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
-{
-	uint32_t base;
-	uint32_t size;
-
-	/* Is this an RW chunk? */
-	if (update_section.base_offset != update_section.top_offset &&
-	    (block_offset >= update_section.base_offset) &&
-	    ((block_offset + body_size) <= update_section.top_offset)) {
-
-		base = update_section.base_offset;
-		size = update_section.top_offset -
-			 update_section.base_offset;
-		/*
-		 * If this is the first chunk for this section, it needs to
-		 * be erased.
-		 */
-		if (block_offset == base) {
-			if (crec_flash_physical_erase(base, size) !=
-				EC_SUCCESS) {
-				CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n",
-					__func__, __LINE__, base, size);
-				return UPDATE_ERASE_FAILURE;
-			}
-		}
-
-		return UPDATE_SUCCESS;
-	}
-
-#ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
-	if (is_touchpad_block(block_offset, body_size))
-		return UPDATE_SUCCESS;
-#endif
-
-	CPRINTF("%s:%d %x, %d section base %x top %x\n",
-		__func__, __LINE__,
-		block_offset, body_size,
-		update_section.base_offset,
-		update_section.top_offset);
-
-	return UPDATE_BAD_ADDR;
-
-}
-
-int update_pdu_valid(struct update_command *cmd_body, size_t cmd_size)
-{
-	return 1;
-}
-
-static int chunk_came_too_soon(uint32_t block_offset)
-{
-	return 0;
-}
-
-static void new_chunk_written(uint32_t block_offset)
-{
-}
-
-static int contents_allowed(uint32_t block_offset,
-			    size_t body_size, void *update_data)
-{
-#if defined(CONFIG_TOUCHPAD_VIRTUAL_OFF) && defined(CONFIG_TOUCHPAD_HASH_FW)
-	if (is_touchpad_block(block_offset, body_size)) {
-		struct sha256_ctx ctx;
-		uint8_t *tmp;
-		uint32_t fw_offset = block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF;
-		unsigned int chunk = fw_offset / CONFIG_UPDATE_PDU_SIZE;
-		int good = 0;
-
-		if (chunk >= CONFIG_TOUCHPAD_FW_CHUNKS ||
-				(fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) {
-			CPRINTF("%s: TP invalid offset %08x\n",
-				__func__, fw_offset);
-			return 0;
-		}
-
-		SHA256_init(&ctx);
-		SHA256_update(&ctx, update_data, body_size);
-		tmp = SHA256_final(&ctx);
-
-		good = !memcmp(tmp, touchpad_fw_hashes[chunk],
-				SHA256_DIGEST_SIZE);
-
-		CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__,
-			fw_offset, tmp[0], tmp[31], good ? "GOOD" : "BAD");
-
-		return good;
-	}
-#endif
-	return 1;
-}
-
-/*
- * Setup internal state (e.g. valid sections, and fill first response).
- *
- * Assumes rpdu is already prefilled with 0, and that version has already
- * been set. May set a return_value != 0 on error.
- */
-void fw_update_start(struct first_response_pdu *rpdu)
-{
-	const char *version;
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-	const struct vb21_packed_key *vb21_key;
-#endif
-
-	rpdu->header_type = htobe16(UPDATE_HEADER_TYPE_COMMON);
-
-	/* Determine the valid update section. */
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RO:
-		/* RO running, so update RW */
-		update_section.base_offset = CONFIG_RW_MEM_OFF;
-		update_section.top_offset = CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE;
-		version = system_get_version(EC_IMAGE_RW);
-		break;
-	case EC_IMAGE_RW:
-		/* RW running, so update RO */
-		update_section.base_offset = CONFIG_RO_MEM_OFF;
-		update_section.top_offset = CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE;
-		version = system_get_version(EC_IMAGE_RO);
-		break;
-	default:
-		CPRINTF("%s:%d\n", __func__, __LINE__);
-		rpdu->return_value = htobe32(UPDATE_GEN_ERROR);
-		return;
-	}
-
-	rpdu->common.maximum_pdu_size = htobe32(CONFIG_UPDATE_PDU_SIZE);
-	rpdu->common.flash_protection = htobe32(crec_flash_get_protect());
-	rpdu->common.offset = htobe32(update_section.base_offset);
-	if (version)
-		memcpy(rpdu->common.version, version,
-			sizeof(rpdu->common.version));
-
-#ifdef CONFIG_ROLLBACK
-	rpdu->common.min_rollback = htobe32(rollback_get_minimum_version());
-#else
-	rpdu->common.min_rollback = htobe32(-1);
-#endif
-
-#ifdef CONFIG_RWSIG_TYPE_RWSIG
-	vb21_key = vb21_get_packed_key();
-	rpdu->common.key_version = htobe32(vb21_key->key_version);
-#endif
-
-#ifdef HAS_TASK_RWSIG
-	/* Do not allow the update to start if RWSIG is still running. */
-	if (rwsig_get_status() == RWSIG_IN_PROGRESS) {
-		CPRINTF("RWSIG in progress\n");
-		rpdu->return_value = htobe32(UPDATE_RWSIG_BUSY);
-	}
-#endif
-}
-
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
-			       size_t *response_size)
-{
-	struct update_command *cmd_body = body;
-	void *update_data;
-	uint8_t *error_code = body;  /* Cache the address for code clarity. */
-	size_t body_size;
-	uint32_t block_offset;
-
-	*response_size = 1; /* One byte response unless this is a start PDU. */
-
-	if (cmd_size < sizeof(struct update_command)) {
-		CPRINTF("%s:%d\n", __func__, __LINE__);
-		*error_code = UPDATE_GEN_ERROR;
-		return;
-	}
-	body_size = cmd_size - sizeof(struct update_command);
-
-	if (!cmd_body->block_base && !body_size) {
-		struct first_response_pdu *rpdu = body;
-
-		/*
-		 * This is the connection establishment request, the response
-		 * allows the server to decide what sections of the image to
-		 * send to program into the flash.
-		 */
-
-		/* First, prepare the response structure. */
-		memset(rpdu, 0, sizeof(*rpdu));
-		/*
-		 * TODO(b/36375666): The response size can be shorter depending
-		 * on which board-specific type of response we provide. This
-		 * may send trailing 0 bytes, which should be harmless.
-		 */
-		*response_size = sizeof(*rpdu);
-		rpdu->protocol_version = htobe16(UPDATE_PROTOCOL_VERSION);
-
-		/* Setup internal state (e.g. valid sections, and fill rpdu) */
-		fw_update_start(rpdu);
-		return;
-	}
-
-	block_offset = be32toh(cmd_body->block_base);
-
-	if (!update_pdu_valid(cmd_body, cmd_size)) {
-		*error_code = UPDATE_DATA_ERROR;
-		return;
-	}
-
-	update_data = cmd_body + 1;
-	if (!contents_allowed(block_offset, body_size, update_data)) {
-		*error_code = UPDATE_ROLLBACK_ERROR;
-		return;
-	}
-
-	/* Check if the block will fit into the valid area. */
-	*error_code = check_update_chunk(block_offset, body_size);
-	if (*error_code)
-		return;
-
-	if (chunk_came_too_soon(block_offset)) {
-		*error_code = UPDATE_RATE_LIMIT_ERROR;
-		return;
-	}
-
-#ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
-	if (is_touchpad_block(block_offset, body_size)) {
-		if (touchpad_update_write(
-				block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF,
-				body_size, update_data)	!= EC_SUCCESS) {
-			*error_code = UPDATE_WRITE_FAILURE;
-			CPRINTF("%s:%d update write error\n",
-				__func__, __LINE__);
-			return;
-		}
-
-		new_chunk_written(block_offset);
-
-		*error_code = UPDATE_SUCCESS;
-		return;
-	}
-#endif
-
-	CPRINTF("update: 0x%x\n", block_offset + CONFIG_PROGRAM_MEMORY_BASE);
-	if (crec_flash_physical_write(block_offset, body_size, update_data)
-	    != EC_SUCCESS) {
-		*error_code = UPDATE_WRITE_FAILURE;
-		CPRINTF("%s:%d update write error\n", __func__, __LINE__);
-		return;
-	}
-
-	new_chunk_written(block_offset);
-
-	/* Verify that data was written properly. */
-	if (memcmp(update_data, (void *)
-		   (block_offset + CONFIG_PROGRAM_MEMORY_BASE),
-		   body_size)) {
-		*error_code = UPDATE_VERIFY_ERROR;
-		CPRINTF("%s:%d update verification error\n",
-			__func__, __LINE__);
-		return;
-	}
-
-	*error_code = UPDATE_SUCCESS;
-}
-
-void fw_update_complete(void)
-{
-}
diff --git a/common/usb_charger.c b/common/usb_charger.c
deleted file mode 100644
index b8e8038811..0000000000
--- a/common/usb_charger.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * USB charger interface routines. This code assumes that CONFIG_CHARGE_MANAGER
- * is defined and implemented.
- * usb_charger_set_switches() must be implemented by a companion
- * usb_switch driver.
- * In addition,  USB switch-specific usb_charger task or interrupt routine
- * is necessary to update charge_manager with detected charger attributes.
- */
-
-#include "charge_manager.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "stddef.h"
-#include "task.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usb_pd_flags.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-static void update_vbus_supplier(int port, int vbus_level)
-{
-	struct charge_port_info charge = {0};
-
-	if (vbus_level && !usb_charger_port_is_sourcing_vbus(port)) {
-		charge.voltage = USB_CHARGER_VOLTAGE_MV;
-		charge.current = USB_CHARGER_MIN_CURR_MA;
-	}
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, port, &charge);
-}
-
-#ifdef CONFIG_USB_PD_5V_EN_CUSTOM
-#define USB_5V_EN(port) board_is_sourcing_vbus(port)
-#elif defined(CONFIG_USBC_PPC)
-#define USB_5V_EN(port) ppc_is_sourcing_vbus(port)
-#elif defined(CONFIG_USB_PD_PPC)
-#define USB_5V_EN(port) tcpci_tcpm_get_src_ctrl(port)
-#elif defined(CONFIG_USB_PD_5V_CHARGER_CTRL)
-#define USB_5V_EN(port) charger_is_sourcing_otg_power(port)
-#elif defined(CONFIG_USB_PD_5V_EN_ACTIVE_LOW)
-#define USB_5V_EN(port) !gpio_get_level(GPIO_USB_C##port##_5V_EN_L)
-#else
-#define USB_5V_EN(port) gpio_get_level(GPIO_USB_C##port##_5V_EN)
-#endif
-
-int usb_charger_port_is_sourcing_vbus(int port)
-{
-	if (port == 0)
-		return USB_5V_EN(0);
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	else if (port == 1)
-		return USB_5V_EN(1);
-#endif
-	/* Not a valid port */
-	return 0;
-}
-
-void usb_charger_vbus_change(int port, int vbus_level)
-{
-	/* If VBUS has transitioned low, notify PD module directly */
-	if (!vbus_level)
-		pd_vbus_low(port);
-
-	/* Update VBUS supplier and signal VBUS change to USB_CHG task */
-	update_vbus_supplier(port, vbus_level);
-
-#ifdef HAS_TASK_USB_CHG_P0
-	/* USB Charger task(s) */
-	task_set_event(USB_CHG_PORT_TO_TASK_ID(port), USB_CHG_EVENT_VBUS);
-
-	/* If we swapped to sourcing, drop any related charge suppliers */
-	if (usb_charger_port_is_sourcing_vbus(port))
-		usb_charger_reset_charge(port);
-#endif
-
-	if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_CHARGER) ||
-		(get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) {
-		/* USB PD task */
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void usb_charger_reset_charge(int port)
-{
-	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER,
-				     port, NULL);
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     port, NULL);
-#endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP,
-				     port, NULL);
-#endif
-
-}
-
-static void usb_charger_init(void)
-{
-	int i;
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		usb_charger_reset_charge(i);
-		/* Initialize VBUS supplier based on whether VBUS is present. */
-		update_vbus_supplier(i, pd_is_vbus_present(i));
-	}
-}
-DECLARE_HOOK(HOOK_INIT, usb_charger_init, HOOK_PRIO_CHARGE_MANAGER_INIT + 1);
-
-void usb_charger_task(void *u)
-{
-	int port = TASK_ID_TO_USB_CHG_PORT(task_get_current());
-
-	ASSERT(bc12_ports[port].drv->usb_charger_task);
-	bc12_ports[port].drv->usb_charger_task(port);
-}
diff --git a/common/usb_common.c b/common/usb_common.c
deleted file mode 100644
index 786bd118cf..0000000000
--- a/common/usb_common.c
+++ /dev/null
@@ -1,1027 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Contains common USB functions shared between the old (i.e. usb_pd_protocol)
- * and the new (i.e. usb_sm_*) USB-C PD stacks.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "stdbool.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "usb_api.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_flags.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-/*
- * If we are trying to upgrade PD firmwares (TCPC chips, retimer, etc), we
- * need to ensure the battery has enough charge for this process. 100mAh
- * is about 5% of most batteries, and it should be enough charge to get us
- * through the EC jump to RW and PD upgrade.
- */
-#define MIN_BATTERY_FOR_PD_UPGRADE_MAH 100 /* mAH */
-
-#if defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH)
-int hex8tou32(char *str, uint32_t *val)
-{
-	char *ptr = str;
-	uint32_t tmp = 0;
-
-	while (*ptr) {
-		char c = *ptr++;
-
-		if (c >= '0' && c <= '9')
-			tmp = (tmp << 4) + (c - '0');
-		else if (c >= 'A' && c <= 'F')
-			tmp = (tmp << 4) + (c - 'A' + 10);
-		else if (c >= 'a' && c <= 'f')
-			tmp = (tmp << 4) + (c - 'a' + 10);
-		else
-			return EC_ERROR_INVAL;
-	}
-	if (ptr != str + 8)
-		return EC_ERROR_INVAL;
-	*val = tmp;
-	return EC_SUCCESS;
-}
-
-int remote_flashing(int argc, char **argv)
-{
-	int port, cnt, cmd;
-	uint32_t data[VDO_MAX_SIZE-1];
-	char *e;
-	static int flash_offset[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-	if (argc < 4 || argc > (VDO_MAX_SIZE + 4 - 1))
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &e, 10);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-
-	cnt = 0;
-	if (!strcasecmp(argv[3], "erase")) {
-		cmd = VDO_CMD_FLASH_ERASE;
-		flash_offset[port] = 0;
-		ccprintf("ERASE ...");
-	} else if (!strcasecmp(argv[3], "reboot")) {
-		cmd = VDO_CMD_REBOOT;
-		ccprintf("REBOOT ...");
-	} else if (!strcasecmp(argv[3], "signature")) {
-		cmd = VDO_CMD_ERASE_SIG;
-		ccprintf("ERASE SIG ...");
-	} else if (!strcasecmp(argv[3], "info")) {
-		cmd = VDO_CMD_READ_INFO;
-		ccprintf("INFO...");
-	} else if (!strcasecmp(argv[3], "version")) {
-		cmd = VDO_CMD_VERSION;
-		ccprintf("VERSION...");
-	} else {
-		int i;
-
-		argc -= 3;
-		for (i = 0; i < argc; i++)
-			if (hex8tou32(argv[i+3], data + i))
-				return EC_ERROR_INVAL;
-		cmd = VDO_CMD_FLASH_WRITE;
-		cnt = argc;
-		ccprintf("WRITE %d @%04x ...", argc * 4,
-			 flash_offset[port]);
-		flash_offset[port] += argc * 4;
-	}
-
-	pd_send_vdm(port, USB_VID_GOOGLE, cmd, data, cnt);
-
-	/* Wait until VDM is done */
-	while (pd[port].vdm_state > 0)
-		task_wait_event(100*MSEC);
-
-	ccprintf("DONE %d\n", pd[port].vdm_state);
-	return EC_SUCCESS;
-}
-#endif /* defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH) */
-
-bool pd_firmware_upgrade_check_power_readiness(int port)
-{
-	if (IS_ENABLED(HAS_TASK_CHARGER)) {
-		struct batt_params batt = { 0 };
-		/*
-		 * Cannot rely on the EC's active charger data as the
-		 * EC may just rebooted into RW and has not necessarily
-		 * picked the active charger yet. Charger task may not
-		 * initialized, so check battery directly.
-		 * Prevent the upgrade if the battery doesn't have enough
-		 * charge to finish the upgrade.
-		 */
-		battery_get_params(&batt);
-		if (batt.flags & BATT_FLAG_BAD_REMAINING_CAPACITY ||
-			batt.remaining_capacity <
-				MIN_BATTERY_FOR_PD_UPGRADE_MAH) {
-			CPRINTS("C%d: Cannot suspend for upgrade, not "
-					"enough battery (%dmAh)!",
-					port, batt.remaining_capacity);
-			return false;
-		}
-	} else {
-		/* VBUS is present on the port (it is either a
-		 * source or sink) to provide power, so don't allow
-		 * PD firmware upgrade on the port.
-		 */
-		if (pd_is_vbus_present(port))
-			return false;
-	}
-
-	return true;
-}
-
-int usb_get_battery_soc(void)
-{
-#if defined(CONFIG_CHARGER)
-	return charge_get_percent();
-#elif defined(CONFIG_BATTERY)
-	return board_get_battery_soc();
-#else
-	return 0;
-#endif
-}
-
-#if defined(CONFIG_USB_PD_PREFER_MV) && defined(PD_PREFER_LOW_VOLTAGE) + \
-	defined(PD_PREFER_HIGH_VOLTAGE) > 1
-#error "PD preferred voltage strategy should be mutually exclusive."
-#endif
-
-/*
- * CC values for regular sources and Debug sources (aka DTS)
- *
- * Source type  Mode of Operation   CC1    CC2
- * ---------------------------------------------
- * Regular      Default USB Power   RpUSB  Open
- * Regular      USB-C @ 1.5 A       Rp1A5  Open
- * Regular      USB-C @ 3 A	    Rp3A0  Open
- * DTS		Default USB Power   Rp3A0  Rp1A5
- * DTS		USB-C @ 1.5 A       Rp1A5  RpUSB
- * DTS		USB-C @ 3 A	    Rp3A0  RpUSB
- */
-
-typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
-{
-	typec_current_t charge = 0;
-	enum tcpc_cc_voltage_status cc;
-	enum tcpc_cc_voltage_status cc_alt;
-
-	cc = polarity_rm_dts(polarity) ? cc2 : cc1;
-	cc_alt = polarity_rm_dts(polarity) ? cc1 : cc2;
-
-	switch (cc) {
-	case TYPEC_CC_VOLT_RP_3_0:
-		if (!cc_is_rp(cc_alt) || cc_alt == TYPEC_CC_VOLT_RP_DEF)
-			charge = 3000;
-		else if (cc_alt == TYPEC_CC_VOLT_RP_1_5)
-			charge = 500;
-		break;
-	case TYPEC_CC_VOLT_RP_1_5:
-		charge = 1500;
-		break;
-	case TYPEC_CC_VOLT_RP_DEF:
-		charge = 500;
-		break;
-	default:
-		break;
-	}
-
-	if (IS_ENABLED(CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF) && charge == 500)
-		charge = 0;
-
-	if (cc_is_rp(cc_alt))
-		charge |= TYPEC_CURRENT_DTS_MASK;
-
-	return charge;
-}
-
-enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
-{
-	/* The following assumes:
-	 *
-	 * TYPEC_CC_VOLT_RP_3_0 > TYPEC_CC_VOLT_RP_1_5
-	 * TYPEC_CC_VOLT_RP_1_5 > TYPEC_CC_VOLT_RP_DEF
-	 * TYPEC_CC_VOLT_RP_DEF > TYPEC_CC_VOLT_OPEN
-	 */
-	if (cc_is_src_dbg_acc(cc1, cc2))
-		return (cc1 > cc2) ? POLARITY_CC1_DTS : POLARITY_CC2_DTS;
-
-	return (cc1 > cc2) ? POLARITY_CC1 : POLARITY_CC2;
-}
-
-enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
-{
-	return (cc1 == TYPEC_CC_VOLT_RD) ? POLARITY_CC1 : POLARITY_CC2;
-}
-
-enum pd_cc_states pd_get_cc_state(
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
-{
-	/* Port partner is a SNK */
-	if (cc_is_snk_dbg_acc(cc1, cc2))
-		return PD_CC_UFP_DEBUG_ACC;
-	if (cc_is_at_least_one_rd(cc1, cc2))
-		return PD_CC_UFP_ATTACHED;
-	if (cc_is_audio_acc(cc1, cc2))
-		return PD_CC_UFP_AUDIO_ACC;
-
-	/* Port partner is a SRC */
-	if (cc_is_rp(cc1) && cc_is_rp(cc2))
-		return PD_CC_DFP_DEBUG_ACC;
-	if (cc_is_rp(cc1) || cc_is_rp(cc2))
-		return PD_CC_DFP_ATTACHED;
-
-	/*
-	 * 1) Both lines are Vopen or
-	 * 2) Only an e-marked cabled without a partner on the other side
-	 */
-	return PD_CC_NONE;
-}
-
-/**
- * This function checks the current CC status of the port partner
- * and returns true if the attached partner is debug accessory.
- */
-bool pd_is_debug_acc(int port)
-{
-	enum pd_cc_states cc_state = pd_get_task_cc_state(port);
-
-	return cc_state == PD_CC_UFP_DEBUG_ACC ||
-		cc_state == PD_CC_DFP_DEBUG_ACC;
-}
-
-void pd_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	tcpm_set_polarity(port, polarity);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_POLARITY))
-		ppc_set_polarity(port, polarity);
-}
-
-__overridable int pd_board_check_request(uint32_t rdo, int pdo_cnt)
-{
-	return EC_SUCCESS;
-}
-
-int pd_check_requested_voltage(uint32_t rdo, const int port)
-{
-	int max_ma = rdo & 0x3FF;
-	int op_ma = (rdo >> 10) & 0x3FF;
-	int idx = RDO_POS(rdo);
-	uint32_t pdo;
-	uint32_t pdo_ma;
-#if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)
-	const uint32_t *src_pdo;
-	const int pdo_cnt = dpm_get_source_pdo(&src_pdo, port);
-#elif defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
-	const uint32_t *src_pdo;
-	const int pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
-#else
-	const uint32_t *src_pdo = pd_src_pdo;
-	const int pdo_cnt = pd_src_pdo_cnt;
-#endif
-
-	/* Check for invalid index */
-	if (!idx || idx > pdo_cnt)
-		return EC_ERROR_INVAL;
-
-	/* Board specific check for this request */
-	if (pd_board_check_request(rdo, pdo_cnt))
-		return EC_ERROR_INVAL;
-
-	/* check current ... */
-	pdo = src_pdo[idx - 1];
-	pdo_ma = (pdo & 0x3ff);
-
-	if (op_ma > pdo_ma)
-		return EC_ERROR_INVAL; /* too much op current */
-
-	if (max_ma > pdo_ma && !(rdo & RDO_CAP_MISMATCH))
-		return EC_ERROR_INVAL; /* too much max current */
-
-	CPRINTF("Requested %d mV %d mA (for %d/%d mA)\n",
-		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
-		 op_ma * 10, max_ma * 10);
-
-	/* Accept the requested voltage */
-	return EC_SUCCESS;
-}
-
-__overridable uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-__overridable bool board_is_usb_pd_port_present(int port)
-{
-	/*
-	 * Use board_get_usb_pd_port_count() instead of checking
-	 * CONFIG_USB_PD_PORT_MAX_COUNT directly here for legacy boards
-	 * that implement board_get_usb_pd_port_count() but do not
-	 * implement board_is_usb_pd_port_present().
-	 */
-
-	return (port >= 0) && (port < board_get_usb_pd_port_count());
-}
-
-__overridable bool board_is_dts_port(int port)
-{
-	return true;
-}
-
-int pd_get_retry_count(int port, enum tcpci_msg_type type)
-{
-	/* PD 3.0 6.7.7: nRetryCount = 2; PD 2.0 6.6.9: nRetryCount = 3 */
-	return pd_get_rev(port, type) == PD_REV30 ? 2 : 3;
-}
-
-enum pd_drp_next_states drp_auto_toggle_next_state(
-	uint64_t *drp_sink_time,
-	enum pd_power_role power_role,
-	enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported)
-{
-	const bool hardware_debounced_unattached =
-				((drp_state == PD_DRP_TOGGLE_ON) &&
-				 auto_toggle_supported);
-
-	/* Set to appropriate port state */
-	if (cc_is_open(cc1, cc2)) {
-		/*
-		 * If nothing is attached then use drp_state to determine next
-		 * state. If DRP auto toggle is still on, then remain in the
-		 * DRP_AUTO_TOGGLE state. Otherwise, stop dual role toggling
-		 * and go to a disconnected state.
-		 */
-		switch (drp_state) {
-		case PD_DRP_TOGGLE_OFF:
-			return DRP_TC_DEFAULT;
-		case PD_DRP_FREEZE:
-			if (power_role == PD_ROLE_SINK)
-				return DRP_TC_UNATTACHED_SNK;
-			else
-				return DRP_TC_UNATTACHED_SRC;
-		case PD_DRP_FORCE_SINK:
-			return DRP_TC_UNATTACHED_SNK;
-		case PD_DRP_FORCE_SOURCE:
-			return DRP_TC_UNATTACHED_SRC;
-		case PD_DRP_TOGGLE_ON:
-		default:
-			if (!auto_toggle_supported) {
-				if (power_role == PD_ROLE_SINK)
-					return DRP_TC_UNATTACHED_SNK;
-				else
-					return DRP_TC_UNATTACHED_SRC;
-			}
-
-			return DRP_TC_DRP_AUTO_TOGGLE;
-		}
-	} else if ((cc_is_rp(cc1) || cc_is_rp(cc2)) &&
-		drp_state != PD_DRP_FORCE_SOURCE) {
-		/* SNK allowed unless ForceSRC */
-		if (hardware_debounced_unattached)
-			return DRP_TC_ATTACHED_WAIT_SNK;
-		return DRP_TC_UNATTACHED_SNK;
-	} else if (cc_is_at_least_one_rd(cc1, cc2) ||
-					cc_is_audio_acc(cc1, cc2)) {
-		/*
-		 * SRC allowed unless ForceSNK or Toggle Off
-		 *
-		 * Ideally we wouldn't use auto-toggle when drp_state is
-		 * TOGGLE_OFF/FORCE_SINK, but for some TCPCs, auto-toggle can't
-		 * be prevented in low power mode. Try being a sink in case the
-		 * connected device is dual-role (this ensures reliable charging
-		 * from a hub, b/72007056). 100 ms is enough time for a
-		 * dual-role partner to switch from sink to source. If the
-		 * connected device is sink-only, then we will attempt
-		 * TC_UNATTACHED_SNK twice (due to debounce time), then return
-		 * to low power mode (and stay there). After 200 ms, reset
-		 * ready for a new connection.
-		 */
-		if (drp_state == PD_DRP_TOGGLE_OFF ||
-			drp_state == PD_DRP_FORCE_SINK) {
-			if (get_time().val > *drp_sink_time + 200*MSEC)
-				*drp_sink_time = get_time().val;
-			if (get_time().val < *drp_sink_time + 100*MSEC)
-				return DRP_TC_UNATTACHED_SNK;
-			else
-				return DRP_TC_DRP_AUTO_TOGGLE;
-		} else {
-			if (hardware_debounced_unattached)
-				return DRP_TC_ATTACHED_WAIT_SRC;
-			return DRP_TC_UNATTACHED_SRC;
-		}
-	} else {
-		/* Anything else, keep toggling */
-		if (!auto_toggle_supported) {
-			if (power_role == PD_ROLE_SINK)
-				return DRP_TC_UNATTACHED_SNK;
-			else
-				return DRP_TC_UNATTACHED_SRC;
-		}
-
-		return DRP_TC_DRP_AUTO_TOGGLE;
-	}
-}
-
-__overridable bool usb_ufp_check_usb3_enable(int port)
-{
-	return false;
-}
-
-mux_state_t get_mux_mode_to_set(int port)
-{
-	/*
-	 * If the SoC is down, then we disconnect the MUX to save power since
-	 * no one cares about the data lines.
-	 */
-	if (IS_ENABLED(CONFIG_POWER_COMMON) &&
-	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return USB_PD_MUX_NONE;
-
-	/*
-	 * When PD stack is disconnected, then mux should be disconnected, which
-	 * is also what happens in the set_state disconnection code. Once the
-	 * PD state machine progresses out of disconnect, the MUX state will
-	 * be set correctly again.
-	 */
-	if (pd_is_disconnected(port))
-		return USB_PD_MUX_NONE;
-
-	/*
-	 * For type-c only connections, there may be a need to enable USB3.1
-	 * mode when the port is in a UFP data role, independent of any other
-	 * conditions which are checked below. The default function returns
-	 * false, so only boards that override this check will be affected.
-	 */
-	if (usb_ufp_check_usb3_enable(port) && pd_get_data_role(port)
-	    == PD_ROLE_UFP)
-		return USB_PD_MUX_USB_ENABLED;
-
-	/* If new data role isn't DFP & we only support DFP, also disconnect. */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    IS_ENABLED(CONFIG_USBC_SS_MUX_DFP_ONLY) &&
-	    pd_get_data_role(port) != PD_ROLE_DFP)
-		return USB_PD_MUX_NONE;
-
-	/* If new data role isn't UFP & we only support UFP then disconnect. */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    IS_ENABLED(CONFIG_USBC_SS_MUX_UFP_ONLY) &&
-	    pd_get_data_role(port) != PD_ROLE_UFP)
-		return USB_PD_MUX_NONE;
-
-	/*
-	 * If the power role is sink and the PD partner device is not capable
-	 * of USB communication then disconnect.
-	 *
-	 * On an entry into Unattached.SNK, the partner may be PD capable but
-	 * hasn't yet sent source capabilities. In this case, hold off enabling
-	 * USB3 termination until the PD capability is resolved.
-	 *
-	 * TODO(b/188588458): TCPMv2: Delay enabling USB3 termination when USB4
-	 * is supported.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    pd_get_power_role(port) == PD_ROLE_SINK &&
-	    (pd_capable(port) || pd_waiting_on_partner_src_caps(port)) &&
-	    !pd_get_partner_usb_comm_capable(port))
-		return USB_PD_MUX_NONE;
-
-	/* Otherwise connect mux since we are in S3+ */
-	return USB_PD_MUX_USB_ENABLED;
-}
-
-void set_usb_mux_with_current_data_role(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-		mux_state_t mux_mode = get_mux_mode_to_set(port);
-		enum usb_switch usb_switch_mode =
-				(mux_mode == USB_PD_MUX_NONE) ?
-				USB_SWITCH_DISCONNECT : USB_SWITCH_CONNECT;
-
-		usb_mux_set(port, mux_mode, usb_switch_mode,
-				polarity_rm_dts(pd_get_polarity(port)));
-	}
-}
-
-void usb_mux_set_safe_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-		usb_mux_set(port, IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) ?
-			USB_PD_MUX_SAFE_MODE : USB_PD_MUX_NONE,
-			USB_SWITCH_CONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
-	}
-
-	/* Isolate the SBU lines. */
-	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-		ppc_set_sbu(port, 0);
-}
-
-void usb_mux_set_safe_mode_exit(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-
-	/* Isolate the SBU lines. */
-	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-		ppc_set_sbu(port, 0);
-}
-
-static void pd_send_hard_reset(int port)
-{
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_SEND_HARD_RESET);
-}
-
-#ifdef CONFIG_USBC_OCP
-
-static uint32_t port_oc_reset_req;
-
-static void re_enable_ports(void)
-{
-	uint32_t ports = atomic_clear(&port_oc_reset_req);
-
-	while (ports) {
-		int port = __fls(ports);
-
-		ports &= ~BIT(port);
-
-		/*
-		 * Let the board know that the overcurrent is
-		 * over since we're going to attempt re-enabling
-		 * the port.
-		 */
-		board_overcurrent_event(port, 0);
-
-		pd_send_hard_reset(port);
-		/*
-		 * TODO(b/117854867): PD3.0 to send an alert message
-		 * indicating OCP after explicit contract.
-		 */
-	}
-}
-DECLARE_DEFERRED(re_enable_ports);
-
-void pd_handle_overcurrent(int port)
-{
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return;
-	}
-
-	CPRINTS("C%d: overcurrent!", port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_LOGGING))
-		pd_log_event(PD_EVENT_PS_FAULT, PD_LOG_PORT_SIZE(port, 0),
-			     PS_FAULT_OCP, NULL);
-
-	/* No action to take if disconnected, just log. */
-	if (pd_is_disconnected(port))
-		return;
-
-	/* Keep track of the overcurrent events. */
-	usbc_ocp_add_event(port);
-
-	/* Let the board specific code know about the OC event. */
-	board_overcurrent_event(port, 1);
-
-	/* Wait 1s before trying to re-enable the port. */
-	atomic_or(&port_oc_reset_req, BIT(port));
-	hook_call_deferred(&re_enable_ports_data, SECOND);
-}
-
-#endif /* CONFIG_USBC_OCP */
-
-__maybe_unused void pd_handle_cc_overvoltage(int port)
-{
-	pd_send_hard_reset(port);
-}
-
-__overridable int pd_board_checks(void)
-{
-	return EC_SUCCESS;
-}
-
-__overridable int pd_check_data_swap(int port,
-	enum pd_data_role data_role)
-{
-	/* Allow data swap if we are a UFP, otherwise don't allow. */
-	return (data_role == PD_ROLE_UFP) ? 1 : 0;
-}
-
-__overridable int pd_check_power_swap(int port)
-{
-	/*
-	 * Allow power swap if we are acting as a dual role device.  If we are
-	 * not acting as dual role (ex. suspended), then only allow power swap
-	 * if we are sourcing when we could be sinking.
-	 */
-	if (pd_get_dual_role(port) == PD_DRP_TOGGLE_ON)
-		return 1;
-	else if (pd_get_power_role(port) == PD_ROLE_SOURCE)
-		return 1;
-
-	return 0;
-}
-
-__overridable void pd_execute_data_swap(int port,
-	enum pd_data_role data_role)
-{
-}
-
-__overridable enum pd_dual_role_states pd_get_drp_state_in_suspend(void)
-{
-	/* Disable dual role when going to suspend */
-	return PD_DRP_TOGGLE_OFF;
-}
-
-__overridable void pd_try_execute_vconn_swap(int port, int flags)
-{
-	/*
-	 * If partner is dual-role power and vconn swap is enabled, consider
-	 * if vconn swapping is necessary.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    IS_ENABLED(CONFIG_USBC_VCONN_SWAP))
-		pd_try_vconn_src(port);
-}
-
-__overridable int pd_is_valid_input_voltage(int mv)
-{
-	return 1;
-}
-
-__overridable void pd_transition_voltage(int idx)
-{
-	/* Most devices are fixed 5V output. */
-}
-
-__overridable void typec_set_source_current_limit(int p, enum tcpc_rp_value rp)
-{
-	if (IS_ENABLED(CONFIG_USBC_PPC))
-		ppc_set_vbus_source_current_limit(p, rp);
-}
-
-/* ---------------- Power Data Objects (PDOs) ----------------- */
-#ifndef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-const uint32_t pd_src_pdo_max[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000,
-		  GENERIC_MIN((PD_OPERATING_POWER_MW / 5), PD_MAX_CURRENT_MA),
-		  PDO_FIXED_FLAGS),
-	PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_OPERATING_POWER_MW),
-	PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-#endif /* CONFIG_USB_PD_CUSTOM_PDO */
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#if defined(CONFIG_USB_PE_SM) && !defined(CONFIG_USB_VPD) && \
-	!defined(CONFIG_USB_CTVPD)
-__overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-				uint32_t **rpayload)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-	uint16_t dev_id = 0;
-	int is_rw, is_latest;
-
-	/* make sure we have some payload */
-	if (cnt == 0)
-		return 0;
-
-	/* Only handle custom requests for SVID Google */
-	if (PD_VDO_VID(*payload) != USB_VID_GOOGLE)
-		return 0;
-
-	switch (cmd) {
-	case VDO_CMD_VERSION:
-		/* guarantee last byte of payload is null character */
-		*(payload + cnt - 1) = 0;
-		CPRINTF("version: %s\n", (char *)(payload+1));
-		break;
-	case VDO_CMD_READ_INFO:
-	case VDO_CMD_SEND_INFO:
-		/* copy hash */
-		if (cnt == 7) {
-			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
-			is_rw = VDO_INFO_IS_RW(payload[6]);
-
-			is_latest = pd_dev_store_rw_hash(
-				port, dev_id, payload + 1,
-				is_rw ? EC_IMAGE_RW : EC_IMAGE_RO);
-
-			/*
-			 * Send update host event unless our RW hash is
-			 * already known to be the latest update RW.
-			 */
-			if (!is_rw || !is_latest)
-				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
-
-			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
-				HW_DEV_ID_MAJ(dev_id),
-				HW_DEV_ID_MIN(dev_id),
-				VDO_INFO_SW_DBG_VER(payload[6]),
-				is_rw);
-		} else if (cnt == 6) {
-			/* really old devices don't have last byte */
-			pd_dev_store_rw_hash(port, dev_id, payload + 1,
-					     EC_IMAGE_UNKNOWN);
-		}
-		break;
-	case VDO_CMD_CURRENT:
-		CPRINTF("Current: %dmA\n", payload[1]);
-		break;
-	case VDO_CMD_FLIP:
-		if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-			usb_mux_flip(port);
-		break;
-#ifdef CONFIG_USB_PD_LOGGING
-	case VDO_CMD_GET_LOG:
-		pd_log_recv_vdm(port, cnt, payload);
-		break;
-#endif /* CONFIG_USB_PD_LOGGING */
-	}
-
-	return 0;
-}
-#endif /* CONFIG_USB_PE_SM && !CONFIG_USB_VPD && !CONFIG_USB_CTVPD */
-
-__overridable bool vboot_allow_usb_pd(void)
-{
-	return false;
-}
-
-/* VDM utility functions */
-static void pd_usb_billboard_deferred(void)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE) &&
-		!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) &&
-		!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) &&
-		IS_ENABLED(CONFIG_USB_BOS)) {
-		/*
-		 * TODO(tbroch)
-		 * 1. Will we have multiple type-C port UFPs
-		 * 2. Will there be other modes applicable to DFPs besides DP
-		 */
-		if (!pd_alt_mode(0, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT))
-			usb_connect();
-	}
-}
-DECLARE_DEFERRED(pd_usb_billboard_deferred);
-
-#ifdef CONFIG_USB_PD_DISCHARGE
-static void gpio_discharge_vbus(int port, int enable)
-{
-#ifdef CONFIG_USB_PD_DISCHARGE_GPIO
-	enum gpio_signal dischg_gpio[] = {
-		GPIO_USB_C0_DISCHARGE,
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		GPIO_USB_C1_DISCHARGE,
-#endif
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 2
-		GPIO_USB_C2_DISCHARGE,
-#endif
-	};
-	BUILD_ASSERT(ARRAY_SIZE(dischg_gpio) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	gpio_set_level(dischg_gpio[port], enable);
-#endif /* CONFIG_USB_PD_DISCHARGE_GPIO */
-}
-
-void pd_set_vbus_discharge(int port, int enable)
-{
-	static mutex_t discharge_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
-#ifdef CONFIG_ZEPHYR
-	static bool inited[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-	if (!inited[port]) {
-		(void)k_mutex_init(&discharge_lock[port]);
-		inited[port] = true;
-	}
-#endif
-	if (port >= board_get_usb_pd_port_count())
-		return;
-
-	mutex_lock(&discharge_lock[port]);
-	enable &= !board_vbus_source_enabled(port);
-
-	if (get_usb_pd_discharge() == USB_PD_DISCHARGE_GPIO) {
-		gpio_discharge_vbus(port, enable);
-	} else if (get_usb_pd_discharge() == USB_PD_DISCHARGE_TCPC) {
-#ifdef CONFIG_USB_PD_DISCHARGE_PPC
-		tcpc_discharge_vbus(port, enable);
-#endif
-	} else if (get_usb_pd_discharge() == USB_PD_DISCHARGE_PPC) {
-#ifdef CONFIG_USB_PD_DISCHARGE_PPC
-		ppc_discharge_vbus(port, enable);
-#endif
-	}
-
-	mutex_unlock(&discharge_lock[port]);
-}
-#endif /* CONFIG_USB_PD_DISCHARGE */
-
-#ifdef CONFIG_USB_PD_TCPM_TCPCI
-static uint32_t pd_ports_to_resume;
-static void resume_pd_port(void)
-{
-	uint32_t port;
-	uint32_t suspended_ports = atomic_clear(&pd_ports_to_resume);
-
-	while (suspended_ports) {
-		port = __builtin_ctz(suspended_ports);
-		suspended_ports &= ~BIT(port);
-		pd_set_suspend(port, 0);
-	}
-}
-DECLARE_DEFERRED(resume_pd_port);
-
-void pd_deferred_resume(int port)
-{
-	atomic_or(&pd_ports_to_resume, 1 << port);
-	hook_call_deferred(&resume_pd_port_data, 5 * SECOND);
-}
-#endif /* CONFIG_USB_PD_TCPM_TCPCI */
-
-__overridable int pd_snk_is_vbus_provided(int port)
-{
-	return EC_SUCCESS;
-}
-
-/*
- * Check the specified Vbus level
- *
- * Note that boards may override this function if they have a method outside the
- * TCPCI driver to verify vSafe0V.
- */
-__overridable bool pd_check_vbus_level(int port, enum vbus_level level)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
-		(get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) {
-		return tcpm_check_vbus_level(port, level);
-	}
-	else if (level == VBUS_PRESENT)
-		return pd_snk_is_vbus_provided(port);
-	else
-		return !pd_snk_is_vbus_provided(port);
-}
-
-int pd_is_vbus_present(int port)
-{
-	return pd_check_vbus_level(port, VBUS_PRESENT);
-}
-
-#ifdef CONFIG_USB_PD_FRS
-__overridable int board_pd_set_frs_enable(int port, int enable)
-{
-	return EC_SUCCESS;
-}
-
-int pd_set_frs_enable(int port, int enable)
-{
-	int rv = EC_SUCCESS;
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
-		rv = ppc_set_frs_enable(port, enable);
-	if (rv == EC_SUCCESS && IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
-		rv = tcpm_set_frs_enable(port, enable);
-	if (rv == EC_SUCCESS)
-		rv = board_pd_set_frs_enable(port, enable);
-	return rv;
-}
-#endif /* defined(CONFIG_USB_PD_FRS) */
-
-#ifdef CONFIG_CMD_TCPC_DUMP
-/*
- * Dump TCPC registers.
- */
-void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
-			  int count)
-{
-	int i, val;
-
-	for (i = 0; i < count; i++, reg++) {
-		switch (reg->size) {
-		case 1:
-			tcpc_read(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) =   0x%02x\n",
-				reg->name, reg->addr, (uint8_t)val);
-			break;
-		case 2:
-			tcpc_read16(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) = 0x%04x\n",
-				reg->name, reg->addr, (uint16_t)val);
-			break;
-		}
-		cflush();
-	}
-
-}
-
-static int command_tcpc_dump(int argc, char **argv)
-{
-	int port;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-	/* Dump TCPC registers. */
-	tcpm_dump_registers(port);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(tcpci_dump, command_tcpc_dump, "<Type-C port>",
-			"dump the TCPC regs");
-#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
-
-void pd_srccaps_dump(int port)
-{
-	int i;
-	const uint32_t *const srccaps = pd_get_src_caps(port);
-
-	for (i = 0; i < pd_get_src_cap_cnt(port); ++i) {
-		uint32_t max_ma, max_mv, min_mv;
-
-		pd_extract_pdo_power(srccaps[i], &max_ma, &max_mv, &min_mv);
-
-		if ((srccaps[i] & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-			if (IS_ENABLED(CONFIG_USB_PD_REV30))
-				ccprintf("%d: %dmV-%dmV/%dmA\n", i, min_mv,
-					 max_mv, max_ma);
-		} else {
-			ccprintf("%d: %dmV/%dmA\n", i, max_mv, max_ma);
-		}
-	}
-}
-
-int pd_build_alert_msg(uint32_t *msg, uint32_t *len, enum pd_power_role pr)
-{
-	if (msg == NULL || len == NULL)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * SOURCE: currently only supports OCP
-	 * SINK:   currently only supports OVP
-	 */
-	if (pr == PD_ROLE_SOURCE)
-		*msg = ADO_OCP_EVENT;
-	else
-		*msg = ADO_OVP_EVENT;
-
-	/* Alert data is 4 bytes */
-	*len = 4;
-
-	return EC_SUCCESS;
-}
diff --git a/common/usb_console_stream.c b/common/usb_console_stream.c
deleted file mode 100644
index 13dd7f8264..0000000000
--- a/common/usb_console_stream.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "crc.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "task.h"
-#include "timer.h"
-#include "usb-stream.h"
-
-#ifdef CONFIG_USB_CONSOLE
-/*
- * CONFIG_USB_CONSOLE and CONFIG_USB_CONSOLE_STREAM should be defined
- * exclusively each other.
- */
-#error "Do not enable CONFIG_USB_CONSOLE."
-#endif
-
-/* Console output macro */
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-#define QUEUE_SIZE_USB_TX     CONFIG_USB_CONSOLE_TX_BUF_SIZE
-#define QUEUE_SIZE_USB_RX     USB_MAX_PACKET_SIZE
-
-static void usb_console_wr(struct queue_policy const *policy, size_t count);
-static void uart_console_rd(struct queue_policy const *policy, size_t count);
-
-
-static int last_tx_ok = 1;
-
-/*
- * Start enabled, so we can queue early debug output before the board gets
- * around to calling usb_console_enable().
- */
-static int is_enabled = 1;
-
-/*
- * But start read-only, so we don't accept console input until we explicitly
- * decide that we're ready for it.
- */
-static int is_readonly = 1;
-
-/*
- * This is a usb_console producer policy, which wakes up CONSOLE task whenever
- * rx_q gets new data added. This shall be called by rx_stream_handler() in
- * usb-stream.c.
- */
-static struct queue_policy const usb_console_policy = {
-	.add    = usb_console_wr,
-	.remove = uart_console_rd,
-};
-
-static struct queue const tx_q = QUEUE_NULL(QUEUE_SIZE_USB_TX, uint8_t);
-static struct queue const rx_q = QUEUE(QUEUE_SIZE_USB_RX, uint8_t,
-				       usb_console_policy);
-
-struct usb_stream_config const usb_console;
-
-USB_STREAM_CONFIG(usb_console,
-		  USB_IFACE_CONSOLE,
-		  USB_STR_CONSOLE_NAME,
-		  USB_EP_CONSOLE,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  rx_q,
-		  tx_q)
-
-static void usb_console_wr(struct queue_policy const *policy, size_t count)
-{
-	console_has_input();
-}
-
-static void uart_console_rd(struct queue_policy const *policy, size_t count)
-{
-	/* do nothing */
-}
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	usb_console.consumer.ops->written(&usb_console.consumer, 1);
-}
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !tx_fifo_is_ready(&usb_console))
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE ||
-		       !*usb_console.is_reset) {
-			if (timestamp_expired(deadline, NULL) ||
-			    in_interrupt_context()) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-	} else {
-		last_tx_ok = queue_space(&tx_q);
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_CONSOLE_CRC
-static uint32_t usb_tx_crc_ctx;
-
-void usb_console_crc_init(void)
-{
-	crc32_ctx_init(&usb_tx_crc_ctx);
-}
-
-uint32_t usb_console_crc(void)
-{
-	return crc32_ctx_result(&usb_tx_crc_ctx);
-}
-#endif
-
-static int __tx_char(void *context, int c)
-{
-	int ret;
-
-	if (c == '\n') {
-		ret = __tx_char(NULL, '\r');
-		if (ret)
-			return ret;
-	}
-
-#ifdef CONFIG_USB_CONSOLE_CRC
-	crc32_ctx_hash8(&usb_tx_crc_ctx, c);
-
-	while (queue_add_unit(&tx_q, &c) != 1)
-		usleep(500);
-
-	return EC_SUCCESS;
-#else
-	/* Return 0 on success */
-	return queue_add_unit(&tx_q, &c) ? EC_SUCCESS : EC_ERROR_OVERFLOW;
-#endif
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c;
-
-	if (is_readonly || !is_enabled)
-		return -1;
-
-	if (!queue_remove_unit(&rx_q, &c))
-		return -1;
-
-	return c;
-}
-
-int usb_puts(const char *outstr)
-{
-	int ret;
-
-	if (!is_enabled)
-		return EC_SUCCESS;
-
-	ret  = usb_wait_console();
-	if (ret)
-		return ret;
-
-	while (*outstr) {
-		ret = __tx_char(NULL, *outstr++);
-		if (ret)
-			break;
-	}
-	handle_output();
-
-	return ret;
-}
-
-int usb_putc(int c)
-{
-	static char string[2] = { 0, '\0' };
-
-	string[0] = c;
-
-	return usb_puts(string);
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-
-	if (!is_enabled)
-		return EC_SUCCESS;
-
-	ret = usb_wait_console();
-	if (ret)
-		return ret;
-
-	ret = vfnprintf(__tx_char, NULL, format, args);
-
-	handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
-
-int usb_console_tx_blocked(void)
-{
-	return is_enabled && (queue_space(&tx_q) < USB_MAX_PACKET_SIZE);
-}
diff --git a/common/usb_i2c.c b/common/usb_i2c.c
deleted file mode 100644
index ace2e7139c..0000000000
--- a/common/usb_i2c.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "i2c.h"
-#include "usb_descriptor.h"
-#include "util.h"
-
-#include "common.h"
-#include "console.h"
-#include "consumer.h"
-#include "producer.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "task.h"
-#include "usb-stream.h"
-#include "usb_i2c.h"
-
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-
-USB_I2C_CONFIG(i2c,
-	       USB_IFACE_I2C,
-	       USB_STR_I2C_NAME,
-	       USB_EP_I2C)
-
-static int (*cros_cmd_handler)(void *data_in,
-			       size_t in_size,
-			       void *data_out,
-			       size_t out_size);
-
-static int16_t usb_i2c_map_error(int error)
-{
-	switch (error) {
-	case EC_SUCCESS:       return USB_I2C_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_I2C_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_I2C_BUSY;
-	default:               return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff);
-	}
-}
-
-/*
- * Return value should be large enough to accommodate the entire read queue
- * buffer size. Let's use 4 bytes in case future designs have a lot of RAM and
- * allow for large buffers.
- */
-static uint32_t usb_i2c_read_packet(struct usb_i2c_config const *config)
-{
-	return QUEUE_REMOVE_UNITS(config->consumer.queue, config->buffer,
-		queue_count(config->consumer.queue));
-}
-
-static void usb_i2c_write_packet(struct usb_i2c_config const *config,
-				 size_t count)
-{
-	QUEUE_ADD_UNITS(config->tx_queue, config->buffer, count);
-}
-
-static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
-{
-	static size_t expected_size;
-
-	if (!expected_size) {
-		uint8_t peek[4];
-
-		/*
-		 * In order to support larger write payload, we need to peek
-		 * the queue to see if we need to wait for more data.
-		 */
-		if (queue_peek_units(config->consumer.queue,
-				     peek, 0, sizeof(peek))
-		    != sizeof(peek)) {
-			/* Not enough data to calculate expected_size. */
-			return 0;
-		}
-		/*
-		 * The first four bytes of the packet will describe its
-		 * expected size.
-		 */
-		/* Header bytes  and extra rc bytes, if present. */
-		if (peek[3] & 0x80)
-			expected_size = 6;
-		else
-			expected_size = 4;
-
-		/* write count */
-		expected_size += (((size_t)peek[0] & 0xf0) << 4) | peek[2];
-	}
-
-
-	if (queue_count(config->consumer.queue) >= expected_size) {
-		expected_size = 0;
-		return 1;
-	}
-
-	return 0;
-}
-
-static void usb_i2c_execute(struct usb_i2c_config const *config)
-{
-	/* Payload is ready to execute. */
-	uint32_t count      = usb_i2c_read_packet(config);
-	int portindex       = (config->buffer[0] >> 0) & 0xf;
-	uint16_t addr_flags = (config->buffer[0] >> 8) & 0x7f;
-	int write_count     = ((config->buffer[0] << 4) & 0xf00) |
-		((config->buffer[1] >> 0) & 0xff);
-	int read_count      = (config->buffer[1] >> 8) & 0xff;
-	int offset          = 0;    /* Offset for extended reading header. */
-
-	config->buffer[0] = 0;
-	config->buffer[1] = 0;
-
-	if (read_count & 0x80) {
-		read_count = ((config->buffer[2] & 0xff) << 7) |
-			(read_count & 0x7f);
-		offset = 2;
-	}
-
-	if (!count || (!read_count && !write_count))
-		return;
-
-	if (!usb_i2c_board_is_enabled()) {
-		config->buffer[0] = USB_I2C_DISABLED;
-	} else if (write_count > CONFIG_USB_I2C_MAX_WRITE_COUNT ||
-		write_count != (count - 4 - offset)) {
-		config->buffer[0] = USB_I2C_WRITE_COUNT_INVALID;
-	} else if (read_count > CONFIG_USB_I2C_MAX_READ_COUNT) {
-		config->buffer[0] = USB_I2C_READ_COUNT_INVALID;
-	} else if (portindex >= i2c_ports_used) {
-		config->buffer[0] = USB_I2C_PORT_INVALID;
-	} else if (addr_flags == USB_I2C_CMD_ADDR_FLAGS) {
-		/*
-		 * This is a non-i2c command, invoke the handler if it has
-		 * been registered, if not - report the appropriate error.
-		 */
-		if (!cros_cmd_handler)
-			config->buffer[0] = USB_I2C_MISSING_HANDLER;
-		else
-			config->buffer[0] = cros_cmd_handler(config->buffer + 2,
-							     write_count,
-							     config->buffer + 2,
-							     read_count);
-	} else {
-		int ret;
-
-		/*
-		 * TODO (crbug.com/750397): Add security.  This currently
-		 * blindly passes through ALL I2C commands on any bus the EC
-		 * knows about.  It should behave closer to
-		 * EC_CMD_I2C_PASSTHRU, which can protect ports and ranges.
-		 */
-		ret = i2c_xfer(i2c_ports[portindex].port, addr_flags,
-			       (uint8_t *)(config->buffer + 2) + offset,
-			       write_count,
-			       (uint8_t *)(config->buffer + 2),
-			       read_count);
-		config->buffer[0] = usb_i2c_map_error(ret);
-	}
-	usb_i2c_write_packet(config, read_count + 4);
-}
-
-void usb_i2c_deferred(struct usb_i2c_config const *config)
-{
-	/* Check if we can proceed the queue. */
-	if (usb_i2c_executable(config))
-		usb_i2c_execute(config);
-}
-
-static void usb_i2c_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_i2c_config const *config =
-		DOWNCAST(consumer, struct usb_i2c_config, consumer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-struct consumer_ops const usb_i2c_consumer_ops = {
-	.written = usb_i2c_written,
-};
-
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size))
-{
-	if (cros_cmd_handler)
-		return -1;
-	cros_cmd_handler = cmd_handler;
-	return 0;
-}
diff --git a/common/usb_pd_alt_mode_dfp.c b/common/usb_pd_alt_mode_dfp.c
deleted file mode 100644
index d7048f4c8e..0000000000
--- a/common/usb_pd_alt_mode_dfp.c
+++ /dev/null
@@ -1,1543 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternate Mode Downstream Facing Port (DFP) USB-PD module.
- */
-
-#include "chipset.h"
-#include "console.h"
-#include "task.h"
-#include "task_id.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_charge.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_tbt_alt_mode.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-#ifndef PORT_TO_HPD
-#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
-#endif /* PORT_TO_HPD */
-
-/* Tracker for which task is waiting on sysjump prep to finish */
-static volatile task_id_t sysjump_task_waiting = TASK_ID_INVALID;
-
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.  Since this is used in overridable functions, this
- * has to be global.
- */
-uint64_t svdm_hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Console command multi-function preference set for a PD port. */
-
-__maybe_unused bool dp_port_mf_allow[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-		[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true};
-
-
-__overridable const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-static int pd_get_mode_idx(int port, enum tcpci_msg_type type,
-		uint16_t svid)
-{
-	int amode_idx;
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-
-	for (amode_idx = 0; amode_idx < PD_AMODE_COUNT; amode_idx++) {
-		if (active->amodes[amode_idx].fx &&
-		    (active->amodes[amode_idx].fx->svid == svid))
-			return amode_idx;
-	}
-	return -1;
-}
-
-static int pd_allocate_mode(int port, enum tcpci_msg_type type,
-		uint16_t svid)
-{
-	int i, j;
-	struct svdm_amode_data *modep;
-	int mode_idx = pd_get_mode_idx(port, type, svid);
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	assert(active);
-
-	if (mode_idx != -1)
-		return mode_idx;
-
-	/* There's no space to enter another mode */
-	if (active->amode_idx == PD_AMODE_COUNT) {
-		CPRINTF("ERR:NO AMODE SPACE\n");
-		return -1;
-	}
-
-	/* Allocate ...  if SVID == 0 enter default supported policy */
-	for (i = 0; i < supported_modes_cnt; i++) {
-		for (j = 0; j < disc->svid_cnt; j++) {
-			const struct svid_mode_data *svidp = &disc->svids[j];
-
-			/*
-			 * Looking for a match between supported_modes and
-			 * discovered SVIDs; must also match the passed-in SVID
-			 * if that was non-zero. Otherwise, go to the next
-			 * discovered SVID.
-			 * TODO(b/155890173): Support AP-directed mode entry
-			 * where the mode is unknown to the TCPM.
-			 */
-			if ((svidp->svid != supported_modes[i].svid) ||
-			    (svid && (svidp->svid != svid)))
-				continue;
-
-			modep = &active->amodes[active->amode_idx];
-			modep->fx = &supported_modes[i];
-			modep->data = &disc->svids[j];
-			active->amode_idx++;
-			return active->amode_idx - 1;
-		}
-	}
-	return -1;
-}
-
-static int validate_mode_request(struct svdm_amode_data *modep,
-				 uint16_t svid, int opos)
-{
-	if (!modep->fx)
-		return 0;
-
-	if (svid != modep->fx->svid) {
-		CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n",
-			svid, modep->fx->svid);
-		return 0;
-	}
-
-	if (opos != modep->opos) {
-		CPRINTF("ERR:opos r:%d != c:%d\n",
-			opos, modep->opos);
-		return 0;
-	}
-
-	return 1;
-}
-
-void pd_prepare_sysjump(void)
-{
-	int i;
-
-	/* Exit modes before sysjump so we can cleanly enter again later */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		/*
-		 * If the port is not capable of Alternate mode no need to
-		 * send the event.
-		 */
-		if (!pd_alt_mode_capable(i))
-			continue;
-
-		sysjump_task_waiting = task_get_current();
-		task_set_event(PD_PORT_TO_TASK_ID(i), PD_EVENT_SYSJUMP);
-		task_wait_event_mask(TASK_EVENT_SYSJUMP_READY, -1);
-		sysjump_task_waiting = TASK_ID_INVALID;
-	}
-}
-
-/*
- * This algorithm defaults to choosing higher pin config over lower ones in
- * order to prefer multi-function if desired.
- *
- *  NAME | SIGNALING | OUTPUT TYPE | MULTI-FUNCTION | PIN CONFIG
- * -------------------------------------------------------------
- *  A    |  USB G2   |  ?          | no             | 00_0001
- *  B    |  USB G2   |  ?          | yes            | 00_0010
- *  C    |  DP       |  CONVERTED  | no             | 00_0100
- *  D    |  PD       |  CONVERTED  | yes            | 00_1000
- *  E    |  DP       |  DP         | no             | 01_0000
- *  F    |  PD       |  DP         | yes            | 10_0000
- *
- * if UFP has NOT asserted multi-function preferred code masks away B/D/F
- * leaving only A/C/E.  For single-output dongles that should leave only one
- * possible pin config depending on whether its a converter DP->(VGA|HDMI) or DP
- * output.  If UFP is a USB-C receptacle it may assert C/D/E/F.  The DFP USB-C
- * receptacle must always choose C/D in those cases.
- */
-int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
-{
-	struct svdm_amode_data *modep =
-		pd_get_amode_data(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	uint32_t mode_caps;
-	uint32_t pin_caps;
-	int mf_pref;
-
-	/*
-	 * Default dp_port_mf_allow is true, we allow mf operation
-	 * if UFP_D supports it.
-	 */
-
-	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
-	else
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-
-	if (!modep)
-		return 0;
-
-	mode_caps = modep->data->mode_vdo[modep->opos - 1];
-
-	/* TODO(crosbug.com/p/39656) revisit with DFP that can be a sink */
-	pin_caps = PD_DP_PIN_CAPS(mode_caps);
-
-	/* if don't want multi-function then ignore those pin configs */
-	if (!mf_pref)
-		pin_caps &= ~MODE_DP_PIN_MF_MASK;
-
-	/* TODO(crosbug.com/p/39656) revisit if DFP drives USB Gen 2 signals */
-	pin_caps &= ~MODE_DP_PIN_BR2_MASK;
-
-	/* if C/D present they have precedence over E/F for USB-C->USB-C */
-	if (pin_caps & (MODE_DP_PIN_C | MODE_DP_PIN_D))
-		pin_caps &= ~(MODE_DP_PIN_E | MODE_DP_PIN_F);
-
-	/* get_next_bit returns undefined for zero */
-	if (!pin_caps)
-		return 0;
-
-	return 1 << get_next_bit(&pin_caps);
-}
-
-struct svdm_amode_data *pd_get_amode_data(int port,
-		enum tcpci_msg_type type, uint16_t svid)
-{
-	int idx = pd_get_mode_idx(port, type, svid);
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	assert(active);
-
-	return (idx == -1) ? NULL : &active->amodes[idx];
-}
-
-/*
- * Enter default mode ( payload[0] == 0 ) or attempt to enter mode via svid &
- * opos
- */
-uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type,
-		uint16_t svid, int opos)
-{
-	int mode_idx = pd_allocate_mode(port, type, svid);
-	struct svdm_amode_data *modep;
-	uint32_t mode_caps;
-
-	if (mode_idx == -1)
-		return 0;
-	modep = &pd_get_partner_active_modes(port, type)->amodes[mode_idx];
-
-	if (!opos) {
-		/* choose the lowest as default */
-		modep->opos = 1;
-	} else if (opos <= modep->data->mode_cnt) {
-		modep->opos = opos;
-	} else {
-		CPRINTS("C%d: Invalid opos %d for SVID %x", port, opos, svid);
-		return 0;
-	}
-
-	mode_caps = modep->data->mode_vdo[modep->opos - 1];
-	if (modep->fx->enter(port, mode_caps) == -1)
-		return 0;
-
-	/*
-	 * Strictly speaking, this should only happen when the request
-	 * has been ACKed.
-	 * For TCPMV1, still set modal flag pre-emptively. For TCPMv2, the modal
-	 * flag is set when the ENTER command is ACK'd for each alt mode that is
-	 * supported.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1))
-		pd_set_dfp_enter_mode_flag(port, true);
-
-	/* SVDM to send to UFP for mode entry */
-	return VDO(modep->fx->svid, 1, CMD_ENTER_MODE | VDO_OPOS(modep->opos));
-}
-
-/* TODO(b/170372521) : Incorporate exit mode specific changes to DPM SM */
-int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
-		int opos)
-{
-	struct svdm_amode_data *modep;
-	struct partner_active_modes *active =
-		pd_get_partner_active_modes(port, type);
-	int idx;
-
-	/*
-	 * Empty svid signals we should reset DFP VDM state by exiting all
-	 * entered modes then clearing state.  This occurs when we've
-	 * disconnected or for hard reset.
-	 */
-	if (!svid) {
-		for (idx = 0; idx < PD_AMODE_COUNT; idx++)
-			if (active->amodes[idx].fx)
-				active->amodes[idx].fx->exit(port);
-
-		pd_dfp_mode_init(port);
-		return 0;
-	}
-
-	/*
-	 * TODO(crosbug.com/p/33946) : below needs revisited to allow multiple
-	 * mode exit.  Additionally it should honor OPOS == 7 as DFP's request
-	 * to exit all modes.  We currently don't have any UFPs that support
-	 * multiple modes on one SVID.
-	 */
-	modep = pd_get_amode_data(port, type, svid);
-	if (!modep || !validate_mode_request(modep, svid, opos))
-		return 0;
-
-	/* call DFPs exit function */
-	modep->fx->exit(port);
-
-	pd_set_dfp_enter_mode_flag(port, false);
-
-	/* exit the mode */
-	modep->opos = 0;
-	return 1;
-}
-
-/*
- * Check if the SVID has been recorded previously. Some peripherals provide
- * duplicated SVID.
- */
-static bool is_svid_duplicated(const struct pd_discovery *disc, uint16_t svid)
-{
-	int i;
-
-	for (i = 0; i < disc->svid_cnt; ++i)
-		if (disc->svids[i].svid == svid) {
-			CPRINTF("ERR:SVIDDUP\n");
-			return true;
-		}
-
-	return false;
-}
-
-void dfp_consume_attention(int port, uint32_t *payload)
-{
-	uint16_t svid = PD_VDO_VID(payload[0]);
-	int opos = PD_VDO_OPOS(payload[0]);
-	struct svdm_amode_data *modep =
-		pd_get_amode_data(port, TCPCI_MSG_SOP, svid);
-
-	if (!modep || !validate_mode_request(modep, svid, opos))
-		return;
-
-	if (modep->fx->attention)
-		modep->fx->attention(port, payload);
-}
-
-void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
-{
-	int ptype;
-	struct pd_discovery *disc;
-	size_t identity_size;
-
-	if (type == TCPCI_MSG_SOP_PRIME &&
-	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		CPRINTF("ERR:Unexpected cable response\n");
-		return;
-	}
-
-	ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
-	disc = pd_get_am_discovery_and_notify_access(port, type);
-	identity_size = MIN(sizeof(union disc_ident_ack),
-				   (cnt - 1) * sizeof(uint32_t));
-
-	/* Note: only store VDOs, not the VDM header */
-	memcpy(disc->identity.raw_value, payload + 1, identity_size);
-	disc->identity_cnt = identity_size / sizeof(uint32_t);
-
-	switch (ptype) {
-	case IDH_PTYPE_AMA:
-		/* Leave vbus ON if the following macro is false */
-		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-			IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) {
-			/* Adapter is requesting vconn, try to supply it */
-			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]))
-				pd_try_vconn_src(port);
-
-			/* Only disable vbus if vconn was requested */
-			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]) &&
-				!PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)]))
-				pd_power_supply_reset(port);
-		}
-		break;
-	default:
-		break;
-	}
-	pd_set_identity_discovery(port, type, PD_DISC_COMPLETE);
-}
-
-void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
-{
-	int i;
-	uint32_t *ptr = payload + 1;
-	int vdo = 1;
-	uint16_t svid0, svid1;
-	struct pd_discovery *disc =
-			pd_get_am_discovery_and_notify_access(port, type);
-
-	for (i = disc->svid_cnt; i < disc->svid_cnt + 12; i += 2) {
-		if (i >= SVID_DISCOVERY_MAX) {
-			CPRINTF("ERR:SVIDCNT\n");
-			break;
-		}
-		/*
-		 * Verify we're still within the valid packet (count will be one
-		 * for the VDM header + xVDOs)
-		 */
-		if (vdo >= cnt)
-			break;
-
-		svid0 = PD_VDO_SVID_SVID0(*ptr);
-		if (!svid0)
-			break;
-
-		if (!is_svid_duplicated(disc, svid0))
-			disc->svids[disc->svid_cnt++].svid = svid0;
-
-		svid1 = PD_VDO_SVID_SVID1(*ptr);
-		if (!svid1)
-			break;
-
-		if (!is_svid_duplicated(disc, svid1))
-			disc->svids[disc->svid_cnt++].svid = svid1;
-
-		ptr++;
-		vdo++;
-	}
-	/* TODO(tbroch) need to re-issue discover svids if > 12 */
-	if (i && ((i % 12) == 0))
-		CPRINTF("ERR:SVID+12\n");
-
-	pd_set_svids_discovery(port, type, PD_DISC_COMPLETE);
-}
-
-void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
-{
-	int svid_idx;
-	struct svid_mode_data *mode_discovery = NULL;
-	struct pd_discovery *disc =
-			pd_get_am_discovery_and_notify_access(port, type);
-	uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
-
-	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
-		uint16_t svid = disc->svids[svid_idx].svid;
-
-		if (svid == response_svid) {
-			mode_discovery = &disc->svids[svid_idx];
-			break;
-		}
-	}
-	if (!mode_discovery) {
-		const struct svid_mode_data *requested_mode_data =
-			pd_get_next_mode(port, type);
-		CPRINTF("C%d: Mode response for undiscovered SVID %x, but TCPM "
-				"requested SVID %x\n",
-				port, response_svid, requested_mode_data->svid);
-		/*
-		 * Although SVIDs discovery seemed like it succeeded before, the
-		 * partner is now responding with undiscovered SVIDs. Discovery
-		 * cannot reasonably continue under these circumstances.
-		 */
-		pd_set_modes_discovery(port, type, requested_mode_data->svid,
-				PD_DISC_FAIL);
-		return;
-	}
-
-	mode_discovery->mode_cnt = cnt - 1;
-	if (mode_discovery->mode_cnt < 1) {
-		CPRINTF("ERR:NOMODE\n");
-		pd_set_modes_discovery(port, type, mode_discovery->svid,
-				PD_DISC_FAIL);
-		return;
-	}
-
-	memcpy(mode_discovery->mode_vdo, &payload[1],
-			sizeof(uint32_t) * mode_discovery->mode_cnt);
-	disc->svid_idx++;
-	pd_set_modes_discovery(port, type, mode_discovery->svid,
-			PD_DISC_COMPLETE);
-}
-
-int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
-{
-	struct svdm_amode_data *modep = pd_get_amode_data(port, type, svid);
-
-	return (modep) ? modep->opos : -1;
-}
-
-void pd_set_identity_discovery(int port, enum tcpci_msg_type type,
-			       enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
-
-	pd->identity_discovery = disc;
-}
-
-enum pd_discovery_state pd_get_identity_discovery(int port,
-						  enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->identity_discovery;
-}
-
-const union disc_ident_ack *pd_get_identity_response(int port,
-					       enum tcpci_msg_type type)
-{
-	if (type >= DISCOVERY_TYPE_COUNT)
-		return NULL;
-
-	return &pd_get_am_discovery(port, type)->identity;
-}
-
-uint16_t pd_get_identity_vid(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
-
-	return resp->idh.usb_vendor_id;
-}
-
-uint16_t pd_get_identity_pid(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
-
-	return resp->product.product_id;
-}
-
-uint8_t pd_get_product_type(int port)
-{
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
-
-	return resp->idh.product_type;
-}
-
-void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
-			       enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
-
-	pd->svids_discovery = disc;
-}
-
-enum pd_discovery_state pd_get_svids_discovery(int port,
-		enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids_discovery;
-}
-
-int pd_get_svid_count(int port, enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svid_cnt;
-}
-
-uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids[svid_idx].svid;
-}
-
-void pd_set_modes_discovery(int port, enum tcpci_msg_type type,
-		uint16_t svid, enum pd_discovery_state disc)
-{
-	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
-	int svid_idx;
-
-	for (svid_idx = 0; svid_idx < pd->svid_cnt; ++svid_idx) {
-		struct svid_mode_data *mode_data = &pd->svids[svid_idx];
-
-		if (mode_data->svid != svid)
-			continue;
-
-		mode_data->discovery = disc;
-		return;
-	}
-}
-
-enum pd_discovery_state pd_get_modes_discovery(int port,
-		enum tcpci_msg_type type)
-{
-	const struct svid_mode_data *mode_data = pd_get_next_mode(port, type);
-
-	/*
-	 * If there are no SVIDs for which to discover modes, mode discovery is
-	 * trivially complete.
-	 */
-	if (!mode_data)
-		return PD_DISC_COMPLETE;
-
-	return mode_data->discovery;
-}
-
-int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid, uint32_t *vdo_out)
-{
-	int idx;
-	const struct pd_discovery *disc;
-
-	if (type >= DISCOVERY_TYPE_COUNT)
-		return 0;
-
-	disc = pd_get_am_discovery(port, type);
-
-	for (idx = 0; idx < disc->svid_cnt; ++idx) {
-		if (pd_get_svid(port, idx, type) == svid) {
-			memcpy(vdo_out, disc->svids[idx].mode_vdo,
-			       sizeof(uint32_t) * disc->svids[idx].mode_cnt);
-			return disc->svids[idx].mode_cnt;
-		}
-	}
-	return 0;
-}
-
-const struct svid_mode_data *pd_get_next_mode(int port,
-		enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	const struct svid_mode_data *failed_mode_data = NULL;
-	bool svid_good_discovery = false;
-	int svid_idx;
-
-	/* Walk through all of the discovery mode entries */
-	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
-		const struct svid_mode_data *mode_data = &disc->svids[svid_idx];
-
-		/* Discovery is needed, so send this one back now */
-		if (mode_data->discovery == PD_DISC_NEEDED)
-			return mode_data;
-
-		/* Discovery already succeeded, save that it was seen */
-		if (mode_data->discovery == PD_DISC_COMPLETE)
-			svid_good_discovery = true;
-		/* Discovery already failed, save first failure */
-		else if (!failed_mode_data)
-			failed_mode_data = mode_data;
-	}
-
-	/* If no good entries were located, then return last failed */
-	if (!svid_good_discovery)
-		return failed_mode_data;
-
-	/*
-	 * Mode discovery has been attempted for every discovered SVID (if
-	 * any exist)
-	 */
-	return NULL;
-}
-
-const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
-		enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-
-	return disc->svids[svid_idx].mode_vdo;
-}
-
-bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid)
-{
-	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
-	const struct svid_mode_data *mode_data;
-
-	for (mode_data = disc->svids; mode_data < disc->svids + disc->svid_cnt;
-			++mode_data) {
-		if (mode_data->svid == svid &&
-				mode_data->discovery == PD_DISC_COMPLETE)
-			return true;
-	}
-
-	return false;
-}
-
-void notify_sysjump_ready(void)
-{
-	/*
-	 * If event was set from pd_prepare_sysjump, wake the
-	 * task waiting on us to complete.
-	 */
-	if (sysjump_task_waiting != TASK_ID_INVALID)
-		task_set_event(sysjump_task_waiting, TASK_EVENT_SYSJUMP_READY);
-}
-
-static inline bool is_pd_rev3(int port, enum tcpci_msg_type type)
-{
-	return pd_get_rev(port, type) == PD_REV30;
-}
-
-/*
- * ############################################################################
- *
- * (Charge Through) Vconn Powered Device functions
- *
- * ############################################################################
- */
-bool is_vpd_ct_supported(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.ct_support;
-}
-
-uint8_t get_vpd_ct_gnd_impedance(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.gnd_impedance;
-}
-
-uint8_t get_vpd_ct_vbus_impedance(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.vbus_impedance;
-}
-
-uint8_t get_vpd_ct_current_support(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.ct_current_support;
-}
-
-uint8_t get_vpd_ct_max_vbus_voltage(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.max_vbus_voltage;
-}
-
-uint8_t get_vpd_ct_vdo_version(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.vdo_version;
-}
-
-uint8_t get_vpd_ct_firmware_verion(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.firmware_version;
-}
-
-uint8_t get_vpd_ct_hw_version(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.hw_version;
-}
-
-/*
- * ############################################################################
- *
- * Cable communication functions
- *
- * ############################################################################
- */
-enum idh_ptype get_usb_pd_cable_type(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	return disc->identity.idh.product_type;
-}
-
-bool is_usb2_cable_support(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	return disc->identity.idh.product_type == IDH_PTYPE_PCABLE ||
-	       pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
-	       disc->identity.product_t2.a2_rev30.usb_20_support ==
-							USB2_SUPPORTED;
-}
-
-bool is_cable_speed_gen2_capable(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	switch (pd_get_rev(port, TCPCI_MSG_SOP_PRIME)) {
-	case PD_REV20:
-		return disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
-
-	case PD_REV30:
-		return disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
-		       disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
-	default:
-		return false;
-	}
-}
-
-bool is_active_cable_element_retimer(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	/* Ref: USB PD Spec 2.0 Table 6-29 Active Cable VDO
-	 * Revision 2 Active cables do not have Active element support.
-	 */
-	return is_pd_rev3(port, TCPCI_MSG_SOP_PRIME) &&
-		disc->identity.idh.product_type == IDH_PTYPE_ACABLE &&
-		disc->identity.product_t2.a2_rev30.active_elem ==
-							ACTIVE_RETIMER;
-}
-
-/*
- * ############################################################################
- *
- * Thunderbolt-Compatible functions
- *
- * ############################################################################
- */
-
-uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type)
-{
-	uint32_t tbt_mode_vdo[PDO_MODES];
-
-	return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL,
-					tbt_mode_vdo) ? tbt_mode_vdo[0] : 0;
-}
-
-/* TODO (b/148528713): Need to enable Thunderbolt-compatible mode on TCPMv2 */
-void set_tbt_compat_mode_ready(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-	    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-		/* Connect the SBU and USB lines to the connector. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		/* Set usb mux to Thunderbolt-compatible mode */
-		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
-			USB_SWITCH_CONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
-	}
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure F-1 TBT3 Discovery Flow
- */
-static bool is_tbt_cable_superspeed(int port)
-{
-	const struct pd_discovery *disc;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ||
-	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		return false;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	/* Product type is Active cable, hence don't check for speed */
-	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)
-		return true;
-
-	if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE)
-		return false;
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	   is_pd_rev3(port, TCPCI_MSG_SOP_PRIME))
-		return  disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN1 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
-
-	return  disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1 ||
-		disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
-}
-
-static enum tbt_compat_cable_speed usb_rev30_to_tbt_speed(enum usb_rev30_ss ss)
-{
-	switch (ss) {
-	case USB_R30_SS_U32_U40_GEN1:
-		return TBT_SS_U31_GEN1;
-	case USB_R30_SS_U32_U40_GEN2:
-		return TBT_SS_U32_GEN1_GEN2;
-	case USB_R30_SS_U40_GEN3:
-		return TBT_SS_TBT_GEN3;
-	default:
-		return TBT_SS_U32_GEN1_GEN2;
-	}
-}
-
-enum tbt_compat_cable_speed get_tbt_cable_speed(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp;
-	enum tbt_compat_cable_speed max_tbt_speed;
-	enum tbt_compat_cable_speed cable_tbt_speed;
-
-	if (!is_tbt_cable_superspeed(port))
-		return TBT_SS_RES_0;
-
-	cable_mode_resp.raw_value =
-		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-	max_tbt_speed = board_get_max_tbt_speed(port);
-
-	/*
-	 * Ref: TBT4 PD Discovery Flow Application Notes Revision 0.9, Figure 2
-	 * For passive cable, if cable doesn't support USB_VID_INTEL, enter
-	 * Thunderbolt alternate mode with speed from USB Highest Speed field of
-	 * the Passive Cable VDO
-	 * For active cable, if the cable doesn't support USB_VID_INTEL, do not
-	 * enter Thunderbolt alternate mode.
-	 */
-	if (!cable_mode_resp.raw_value) {
-		const struct pd_discovery *disc;
-
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			return TBT_SS_RES_0;
-
-		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		cable_tbt_speed =
-		   usb_rev30_to_tbt_speed(disc->identity.product_t1.p_rev30.ss);
-	} else {
-		cable_tbt_speed = cable_mode_resp.tbt_cable_speed;
-	}
-
-	return max_tbt_speed < cable_tbt_speed ?
-		max_tbt_speed : cable_tbt_speed;
-}
-
-int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop,
-			uint32_t *payload)
-{
-	union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 };
-	union tbt_mode_resp_device dev_mode_resp;
-	union tbt_mode_resp_cable cable_mode_resp;
-	enum tcpci_msg_type enter_mode_sop =
-					sop == TCPCI_MSG_SOP_PRIME_PRIME ?
-						TCPCI_MSG_SOP_PRIME : sop;
-
-	/* Table F-12 TBT3 Cable Enter Mode Command */
-	/*
-	 * The port doesn't query Discover SOP'' to the cable so, the port
-	 * doesn't have opos for SOP''. Hence, send Enter Mode SOP'' with same
-	 * opos and revision as SOP'.
-	 */
-	payload[0] = pd_dfp_enter_mode(port, enter_mode_sop, USB_VID_INTEL, 0) |
-		     VDO_CMDT(CMDT_INIT) |
-		     VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop));
-
-	/*
-	 * Enter safe mode before sending Enter mode SOP/SOP'/SOP''
-	 * Ref: Tiger Lake Platform PD Controller Interface Requirements for
-	 * Integrated USB C, section A.1.2 TBT as DFP.
-	 */
-	usb_mux_set_safe_mode(port);
-
-	/* For TBT3 Cable Enter Mode Command, number of Objects is 1 */
-	if ((sop == TCPCI_MSG_SOP_PRIME) ||
-	    (sop == TCPCI_MSG_SOP_PRIME_PRIME))
-		return 1;
-
-	dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
-	cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-	/* Table F-13 TBT3 Device Enter Mode Command */
-	enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1;
-	enter_dev_mode.vendor_spec_b0 = dev_mode_resp.vendor_spec_b0;
-	enter_dev_mode.intel_spec_b0 = dev_mode_resp.intel_spec_b0;
-
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
-		enter_dev_mode.cable = TBT_ENTER_ACTIVE_CABLE;
-
-	enter_dev_mode.lsrx_comm = cable_mode_resp.lsrx_comm;
-	enter_dev_mode.retimer_type = cable_mode_resp.retimer_type;
-	enter_dev_mode.tbt_cable = cable_mode_resp.tbt_cable;
-	enter_dev_mode.tbt_rounded = cable_mode_resp.tbt_rounded;
-	enter_dev_mode.tbt_cable_speed = get_tbt_cable_speed(port);
-	enter_dev_mode.tbt_alt_mode = TBT_ALTERNATE_MODE;
-
-	payload[1] = enter_dev_mode.raw_value;
-
-	/* For TBT3 Device Enter Mode Command, number of Objects are 2 */
-	return 2;
-}
-
-enum tbt_compat_rounded_support get_tbt_rounded_support(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
-
-	/* tbt_rounded_support is zero when uninitialized */
-	return cable_mode_resp.tbt_rounded;
-}
-
-__overridable enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	return TBT_SS_TBT_GEN3;
-}
-/*
- * ############################################################################
- *
- * USB4 functions
- *
- * ############################################################################
- */
-
-/*
- * For Cable rev 3.0: USB4 cable speed is set according to speed supported by
- * the port and the response received from the cable, whichever is least.
- *
- * For Cable rev 2.0: If get_tbt_cable_speed() is less than
- * TBT_SS_U31_GEN1, return USB_R30_SS_U2_ONLY speed since the board
- * doesn't support superspeed else the USB4 cable speed is set according to
- * the cable response.
- */
-enum usb_rev30_ss get_usb4_cable_speed(int port)
-{
-	enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port);
-	enum usb_rev30_ss max_usb4_speed;
-
-
-	if (tbt_speed < TBT_SS_U31_GEN1)
-		return USB_R30_SS_U2_ONLY;
-
-	/*
-	 * Converting Thunderbolt-Compatible board speed to equivalent USB4
-	 * speed.
-	 */
-	max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ?
-		USB_R30_SS_U40_GEN3 : USB_R30_SS_U32_U40_GEN2;
-
-	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) &&
-	     is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) {
-		const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		union active_cable_vdo1_rev30 a_rev30 =
-			disc->identity.product_t1.a_rev30;
-
-		if (a_rev30.vdo_ver >= VDO_VERSION_1_3) {
-			return max_usb4_speed < a_rev30.ss ?
-			       max_usb4_speed : a_rev30.ss;
-		}
-	}
-
-	return max_usb4_speed;
-}
-
-uint32_t get_enter_usb_msg_payload(int port)
-{
-	/*
-	 * Ref: USB Power Delivery Specification Revision 3.0, Version 2.0
-	 * Table 6-47 Enter_USB Data Object
-	 */
-	union enter_usb_data_obj eudo;
-	const struct pd_discovery *disc;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4))
-		return 0;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	eudo.mode = USB_PD_40;
-	eudo.usb4_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB4_DRD);
-	eudo.usb3_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB32_DRD);
-	eudo.cable_speed = get_usb4_cable_speed(port);
-
-	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE) {
-		if (is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) {
-			enum retimer_active_element active_element =
-				disc->identity.product_t2.a2_rev30.active_elem;
-			eudo.cable_type = active_element == ACTIVE_RETIMER ?
-				CABLE_TYPE_ACTIVE_RETIMER :
-				CABLE_TYPE_ACTIVE_REDRIVER;
-		} else {
-			cable_mode_resp.raw_value =
-				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-			eudo.cable_type =
-				cable_mode_resp.retimer_type  == USB_RETIMER ?
-				CABLE_TYPE_ACTIVE_RETIMER :
-				CABLE_TYPE_ACTIVE_REDRIVER;
-		}
-	} else {
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-		eudo.cable_type =
-			cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-			CABLE_TYPE_ACTIVE_REDRIVER : CABLE_TYPE_PASSIVE;
-	}
-
-	switch (disc->identity.product_t1.p_rev20.vbus_cur) {
-	case USB_VBUS_CUR_3A:
-		eudo.cable_current = USB4_CABLE_CURRENT_3A;
-		break;
-	case USB_VBUS_CUR_5A:
-		eudo.cable_current = USB4_CABLE_CURRENT_5A;
-		break;
-	default:
-		eudo.cable_current = USB4_CABLE_CURRENT_INVALID;
-		break;
-	}
-	eudo.pcie_supported = IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING);
-	eudo.dp_supported = IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP);
-	eudo.tbt_supported = IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE);
-	eudo.host_present = 1;
-
-	return eudo.raw_value;
-}
-
-__overridable bool board_is_tbt_usb4_port(int port)
-{
-	return true;
-}
-
-__overridable void svdm_safe_dp_mode(int port)
-{
-	/* make DP interface safe until configure */
-	dp_flags[port] = 0;
-	dp_status[port] = 0;
-
-	usb_mux_set_safe_mode(port);
-}
-
-__overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps)
-{
-	/*
-	 * Don't enter the mode if the SoC is off.
-	 *
-	 * There's no need to enter the mode while the SoC is off; we'll
-	 * actually enter the mode on the chipset resume hook.  Entering DP Alt
-	 * Mode twice will confuse some monitors and require and unplug/replug
-	 * to get them to work again.  The DP Alt Mode on USB-C spec says that
-	 * if we don't need to maintain HPD connectivity info in a low power
-	 * mode, then we shall exit DP Alt Mode.  (This is why we don't enter
-	 * when the SoC is off as opposed to suspend where adding a display
-	 * could cause a wake up.)  When in S5->S3 transition state, we
-	 * should treat it as a SoC off state.
-	 */
-#ifdef HAS_TASK_CHIPSET
-	if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON))
-		return -1;
-#endif
-
-	/*
-	 * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL.
-	 * DisplayPort Alternate mode requires that the SBU lines are used for
-	 * AUX communication.
-	 * However, in Chromebooks SBU signals are repurposed as USB2 signals
-	 * for CCD. This functionality is accomplished by override fets whose
-	 * state is controlled by CCD_MODE_ODL.
-	 *
-	 * This condition helps in debugging unexpected AUX timeout issues by
-	 * indicating the state of the CCD override fets.
-	 */
-#ifdef GPIO_CCD_MODE_ODL
-	if (!gpio_get_level(GPIO_CCD_MODE_ODL))
-		CPRINTS("WARNING: Tried to EnterMode DP with [CCD on AUX/SBU]");
-#endif
-
-	/* Only enter mode if device is DFP_D capable */
-	if (mode_caps & MODE_DP_SNK) {
-		svdm_safe_dp_mode(port);
-
-		if (IS_ENABLED(CONFIG_MKBP_EVENT) &&
-		    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			/*
-			 * Wake the system up since we're entering DP AltMode.
-			 */
-			pd_notify_dp_alt_mode_entry(port);
-
-		return 0;
-	}
-
-	return -1;
-}
-
-__overridable int svdm_dp_status(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_STATUS | VDO_OPOS(opos));
-	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
-				   0, /* HPD level ... not applicable */
-				   0, /* exit DP? ... no */
-				   0, /* usb mode? ... no */
-				   0, /* multi-function ... no */
-				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
-				   0, /* power low? ... no */
-				   (!!DP_FLAGS_DP_ON));
-	return 2;
-};
-
-__overridable uint8_t get_dp_pin_mode(int port)
-{
-	return pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-}
-
-static mux_state_t svdm_dp_get_mux_mode(int port)
-{
-	int pin_mode = get_dp_pin_mode(port);
-	/* Default dp_port_mf_allow is true */
-	int mf_pref;
-
-	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
-	else
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-
-	/*
-	 * Multi-function operation is only allowed if that pin config is
-	 * supported.
-	 */
-	if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref)
-		return USB_PD_MUX_DOCK;
-	else
-		return USB_PD_MUX_DP_ENABLED;
-}
-
-__overridable int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	uint8_t pin_mode = get_dp_pin_mode(port);
-	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
-	/* Default dp_port_mf_allow is true */
-	int mf_pref;
-
-	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
-	else
-		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
-
-	if (!pin_mode)
-		return 0;
-
-	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
-
-	/*
-	 * Place the USB Type-C pins that are to be re-configured to DisplayPort
-	 * Configuration into the Safe state. For USB_PD_MUX_DOCK, the
-	 * superspeed signals can remain connected. For USB_PD_MUX_DP_ENABLED,
-	 * disconnect the superspeed signals here, before the pins are
-	 * re-configured to DisplayPort (in svdm_dp_post_config, when we receive
-	 * the config ack).
-	 */
-	if (mux_mode == USB_PD_MUX_DP_ENABLED)
-		usb_mux_set_safe_mode(port);
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,	       /* DPv1.3 signaling */
-				2);	       /* UFP connected */
-	return 2;
-};
-
-#if defined(CONFIG_USB_PD_DP_HPD_GPIO) && \
-	!defined(CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM)
-void svdm_set_hpd_gpio(int port, int en)
-{
-	gpio_set_level(PORT_TO_HPD(port), en);
-}
-
-int svdm_get_hpd_gpio(int port)
-{
-	return gpio_get_level(PORT_TO_HPD(port));
-}
-#endif
-
-__overridable void svdm_dp_post_config(int port)
-{
-	mux_state_t mux_mode = svdm_dp_get_mux_mode(port);
-	/* Connect the SBU and USB lines to the connector. */
-	if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-		ppc_set_sbu(port, 1);
-	usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
-		polarity_rm_dts(pd_get_polarity(port)));
-
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
-		return;
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 1);
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 1);
-#endif
-}
-
-__overridable int svdm_dp_attention(int port, uint32_t *payload)
-{
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	int cur_lvl = svdm_get_hpd_gpio(port);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		if (IS_ENABLED(CONFIG_MKBP_EVENT))
-			pd_notify_dp_alt_mode_entry(port);
-
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl)
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		return 1;
-	}
-
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	if (irq && !lvl) {
-		/*
-		 * IRQ can only be generated when the level is high, because
-		 * the IRQ is signaled by a short low pulse from the high level.
-		 */
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0; /* nak */
-	}
-
-	if (irq && cur_lvl) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* generate IRQ_HPD pulse */
-		svdm_set_hpd_gpio(port, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		svdm_set_hpd_gpio(port, 1);
-	} else {
-		svdm_set_hpd_gpio(port, lvl);
-	}
-
-	/* set the minimum time delay (2ms) for the next HPD IRQ */
-	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, lvl);
-#endif
-
-	/* ack */
-	return 1;
-}
-
-__overridable void svdm_exit_dp_mode(int port)
-{
-	dp_flags[port] = 0;
-	dp_status[port] = 0;
-#ifdef CONFIG_USB_PD_DP_HPD_GPIO
-	svdm_set_hpd_gpio(port, 0);
-#endif /* CONFIG_USB_PD_DP_HPD_GPIO */
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-#ifdef USB_PD_PORT_TCPC_MST
-	if (port == USB_PD_PORT_TCPC_MST)
-		baseboard_mst_enable_control(port, 0);
-#endif
-}
-
-__overridable int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
-{
-	/* Always enter GFU mode */
-	return 0;
-}
-
-__overridable void svdm_exit_gfu_mode(int port)
-{
-}
-
-__overridable int svdm_gfu_status(int port, uint32_t *payload)
-{
-	/*
-	 * This is called after enter mode is successful, send unstructured
-	 * VDM to read info.
-	 */
-	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
-	return 0;
-}
-
-__overridable int svdm_gfu_config(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_gfu_attention(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
-__overridable int svdm_tbt_compat_enter_mode(int port, uint32_t mode_caps)
-{
-	return 0;
-}
-
-__overridable void svdm_tbt_compat_exit_mode(int port)
-{
-}
-
-__overridable int svdm_tbt_compat_status(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_tbt_compat_config(int port, uint32_t *payload)
-{
-	return 0;
-}
-
-__overridable int svdm_tbt_compat_attention(int port, uint32_t *payload)
-{
-	return 0;
-}
-#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
-
-/*
- * TODO: b:169262276: For TCPMv2, move alternate mode specific entry, exit and
- * configuration to Device Policy Manager.
- */
-const struct svdm_amode_fx supported_modes[] = {
-	{
-		.svid = USB_SID_DISPLAYPORT,
-		.enter = &svdm_enter_dp_mode,
-		.status = &svdm_dp_status,
-		.config = &svdm_dp_config,
-		.post_config = &svdm_dp_post_config,
-		.attention = &svdm_dp_attention,
-		.exit = &svdm_exit_dp_mode,
-	},
-
-	{
-		.svid = USB_VID_GOOGLE,
-		.enter = &svdm_enter_gfu_mode,
-		.status = &svdm_gfu_status,
-		.config = &svdm_gfu_config,
-		.attention = &svdm_gfu_attention,
-		.exit = &svdm_exit_gfu_mode,
-	},
-#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
-	{
-		.svid = USB_VID_INTEL,
-		.enter = &svdm_tbt_compat_enter_mode,
-		.status = &svdm_tbt_compat_status,
-		.config = &svdm_tbt_compat_config,
-		.attention = &svdm_tbt_compat_attention,
-		.exit = &svdm_tbt_compat_exit_mode,
-	},
-#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
-};
-const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
-
-#ifdef CONFIG_CMD_MFALLOW
-static int command_mfallow(int argc, char **argv)
-{
-	char *e;
-	int port;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &e, 10);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(argv[2], "true"))
-		dp_port_mf_allow[port] = true;
-	else if (!strcasecmp(argv[2], "false"))
-		dp_port_mf_allow[port] = false;
-	else
-		return EC_ERROR_PARAM1;
-
-	ccprintf("Port: %d multi function allowed is %s ", port, argv[2]);
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(mfallow, command_mfallow, "port [true | false]",
-		"Controls Multifunction choice during DP Altmode.");
-#endif
diff --git a/common/usb_pd_alt_mode_ufp.c b/common/usb_pd_alt_mode_ufp.c
deleted file mode 100644
index 3db60166d2..0000000000
--- a/common/usb_pd_alt_mode_ufp.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Alternate Mode Upstream Facing Port (UFP) USB-PD module.
- */
-#include "usb_pd.h"
-#include "usb_tbt_alt_mode.h"
-
-static uint32_t ufp_enter_mode[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Save port partner's enter mode message */
-void pd_ufp_set_enter_mode(int port, uint32_t *payload)
-{
-	ufp_enter_mode[port] = payload[1];
-}
-
-/* Return port partner's enter mode message */
-uint32_t pd_ufp_get_enter_mode(int port)
-{
-	return ufp_enter_mode[port];
-}
diff --git a/common/usb_pd_console_cmd.c b/common/usb_pd_console_cmd.c
deleted file mode 100644
index 3ad1944494..0000000000
--- a/common/usb_pd_console_cmd.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Console commands for USB-PD module.
- */
-
-#include "console.h"
-#include "usb_pd.h"
-#include "util.h"
-#include "usb_pd_tcpm.h"
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-#ifdef CONFIG_CMD_USB_PD_PE
-static void dump_pe(int port)
-{
-	int i, j, idh_ptype;
-	struct svdm_amode_data *modep;
-	uint32_t mode_caps;
-	const union disc_ident_ack *resp;
-	enum tcpci_msg_type type;
-	/* TODO(b/152417597): Output SOP' discovery results */
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP);
-
-	static const char * const idh_ptype_names[]  = {
-		"UNDEF", "Hub", "Periph", "PCable", "ACable", "AMA",
-		"RSV6", "RSV7"};
-	static const char * const tx_names[] = {"SOP", "SOP'", "SOP''"};
-
-	for (type = TCPCI_MSG_SOP; type < DISCOVERY_TYPE_COUNT; type++) {
-		resp = pd_get_identity_response(port, type);
-		if (pd_get_identity_discovery(port, type) != PD_DISC_COMPLETE) {
-			ccprintf("No %s identity discovered yet.\n",
-								tx_names[type]);
-			continue;
-		}
-
-		idh_ptype = resp->idh.product_type;
-		ccprintf("IDENT %s:\n", tx_names[type]);
-		ccprintf("\t[ID Header] %08x :: %s, VID:%04x\n",
-			 resp->raw_value[0],
-			 idh_ptype_names[idh_ptype],
-			 resp->idh.usb_vendor_id);
-
-		ccprintf("\t[Cert Stat] %08x\n", resp->cert.xid);
-		for (i = 2; i < ARRAY_SIZE(resp->raw_value); i++) {
-			ccprintf("\t");
-			if (resp->raw_value[i])
-				ccprintf("[%d] %08x ", i, resp->raw_value[i]);
-		}
-		ccprintf("\n");
-	}
-
-	if (pd_get_svid_count(port, TCPCI_MSG_SOP) < 1) {
-		ccprintf("No SVIDS discovered yet.\n");
-		return;
-	}
-
-	/* TODO(b/152418267): Display discovered SVIDs and modes for SOP' */
-	for (i = 0; i < pd_get_svid_count(port, TCPCI_MSG_SOP); i++) {
-		ccprintf("SVID[%d]: %04x MODES:", i, disc->svids[i].svid);
-		for (j = 0; j < disc->svids[j].mode_cnt; j++)
-			ccprintf(" [%d] %08x", j + 1,
-					disc->svids[i].mode_vdo[j]);
-		ccprintf("\n");
-
-		modep = pd_get_amode_data(port, TCPCI_MSG_SOP,
-				disc->svids[i].svid);
-		if (modep) {
-			mode_caps = modep->data->mode_vdo[modep->opos - 1];
-			ccprintf("MODE[%d]: svid:%04x caps:%08x\n", modep->opos,
-				 modep->fx->svid, mode_caps);
-		}
-	}
-}
-
-static int command_pe(int argc, char **argv)
-{
-	int port;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* command: pe <port> <subcmd> <args> */
-	port = strtoi(argv[1], &e, 10);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-	if (!strncasecmp(argv[2], "dump", 4))
-		dump_pe(port);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pe, command_pe,
-			"<port> dump",
-			"USB PE");
-#endif /* CONFIG_CMD_USB_PD_PE */
-
-#ifdef CONFIG_CMD_USB_PD_CABLE
-static const char * const cable_type[] = {
-	[IDH_PTYPE_PCABLE] = "Passive",
-	[IDH_PTYPE_ACABLE] = "Active",
-};
-
-static const char * const cable_curr[] = {
-	[USB_VBUS_CUR_3A] = "3A",
-	[USB_VBUS_CUR_5A] = "5A",
-};
-
-static int command_cable(int argc, char **argv)
-{
-	int port;
-	char *e;
-	const struct pd_discovery *disc;
-	enum idh_ptype ptype;
-	int cable_rev;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &e, 0);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-
-	ptype = get_usb_pd_cable_type(port);
-
-	ccprintf("Cable Type: ");
-	if (ptype != IDH_PTYPE_PCABLE &&
-		ptype != IDH_PTYPE_ACABLE) {
-		ccprintf("Not Emark Cable\n");
-		return EC_SUCCESS;
-	}
-	ccprintf("%s\n", cable_type[ptype]);
-
-	cable_rev = pd_get_rev(port, TCPCI_MSG_SOP_PRIME);
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	cable_mode_resp.raw_value =
-		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-
-	/* Cable revision */
-	ccprintf("Cable Rev: %d.0\n", cable_rev + 1);
-
-	/*
-	 * For rev 2.0, rev 3.0 active and passive cables have same bits for
-	 * connector type (Bit 19:18) and current handling capability bit 6:5
-	 */
-	ccprintf("Connector Type: %d\n",
-				disc->identity.product_t1.p_rev20.connector);
-
-	if (disc->identity.product_t1.p_rev20.vbus_cur) {
-		ccprintf("Cable Current: %s\n",
-		   disc->identity.product_t1.p_rev20.vbus_cur >
-		      ARRAY_SIZE(cable_curr) ? "Invalid" :
-		      cable_curr[disc->identity.product_t1.p_rev20.vbus_cur]);
-	} else
-		ccprintf("Cable Current: Invalid\n");
-
-	/*
-	 * For Rev 3.0 passive cables and Rev 2.0 active and passive cables,
-	 * USB Superspeed Signaling support have same bits 2:0
-	 */
-	if (ptype == IDH_PTYPE_PCABLE)
-		ccprintf("USB Superspeed Signaling support: %d\n",
-			disc->identity.product_t1.p_rev20.ss);
-
-	/*
-	 * For Rev 3.0 active cables and Rev 2.0 active and passive cables,
-	 * SOP" controller preset have same bit 3
-	 */
-	if (ptype == IDH_PTYPE_ACABLE)
-		ccprintf("SOP'' Controller: %s present\n",
-		      disc->identity.product_t1.a_rev20.sop_p_p ? "" : "Not");
-
-	if (cable_rev == PD_REV30) {
-		/*
-		 * For Rev 3.0 active and passive cables, Max Vbus vtg have
-		 * same bits 10:9.
-		 */
-		ccprintf("Max vbus voltage: %d\n",
-			20 + 10 * disc->identity.product_t1.p_rev30.vbus_max);
-
-		/* For Rev 3.0 Active cables */
-		if (ptype == IDH_PTYPE_ACABLE) {
-			ccprintf("SS signaling: USB_SS_GEN%u\n",
-				disc->identity.product_t2.a2_rev30.usb_gen ?
-									2 : 1);
-			ccprintf("Number of SS lanes supported: %u\n",
-				disc->identity.product_t2.a2_rev30.usb_lanes);
-		}
-	}
-
-	if (!cable_mode_resp.raw_value)
-		return EC_SUCCESS;
-
-	ccprintf("Rounded support: %s\n",
-		cable_mode_resp.tbt_rounded ==
-			TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ? "Yes" : "No");
-
-	ccprintf("Optical cable: %s\n",
-		cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No");
-
-	ccprintf("Retimer support: %s\n",
-		cable_mode_resp.retimer_type == USB_RETIMER ?
-			"Yes" : "No");
-
-	ccprintf("Link training: %s-directional\n",
-		cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni");
-
-	ccprintf("Thunderbolt cable type: %s\n",
-		cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-		"Active" : "Passive");
-
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(pdcable, command_cable,
-			"<port>",
-			"Cable Characteristics");
-#endif /* CONFIG_CMD_USB_PD_CABLE */
-
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/common/usb_pd_dual_role.c b/common/usb_pd_dual_role.c
deleted file mode 100644
index 52042c5439..0000000000
--- a/common/usb_pd_dual_role.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Dual Role (Source & Sink) USB-PD module.
- */
-
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "dps.h"
-#include "system.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* The macro is used to prevent a DBZ exception while decoding PDOs. */
-#define PROCESS_ZERO_DIVISOR(x) ((x) == 0 ? 1 : (x))
-
-#if defined(PD_MAX_VOLTAGE_MV) && defined(PD_OPERATING_POWER_MW)
-/*
- * As a sink, this is the max voltage (in millivolts) we can request
- * before getting source caps
- */
-static unsigned int max_request_mv = PD_MAX_VOLTAGE_MV;
-
-/* TODO(b:169532537): deprecate CONFIG_USB_PD_PREFER_MV */
-STATIC_IF_NOT(CONFIG_USB_PD_PREFER_MV)
-struct pd_pref_config_t __maybe_unused pd_pref_config;
-
-void pd_set_max_voltage(unsigned int mv)
-{
-	max_request_mv = mv;
-}
-
-unsigned int pd_get_max_voltage(void)
-{
-	return max_request_mv;
-}
-
-/*
- * Zinger implements a board specific usb policy that does not define
- * PD_MAX_VOLTAGE_MV and PD_OPERATING_POWER_MW. And in turn, does not
- * use the following functions.
- */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-					int max_mv, uint32_t *selected_pdo)
-{
-	int i, uw, mv;
-	int ret = 0;
-	int cur_uw = 0;
-	int has_preferred_pdo;
-	int prefer_cur;
-	int desired_uw = 0;
-	const int prefer_mv = pd_pref_config.mv;
-	const int type = pd_pref_config.type;
-
-	int __attribute__((unused)) cur_mv = 0;
-
-	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV))
-		desired_uw = charge_get_plt_plus_bat_desired_mw() * 1000;
-
-	/* max voltage is always limited by this boards max request */
-	max_mv = MIN(max_mv, PD_MAX_VOLTAGE_MV);
-
-	/* Get max power that is under our max voltage input */
-	for (i = 0; i < src_cap_cnt; i++) {
-		if (IS_ENABLED(CONFIG_USB_PD_ONLY_FIXED_PDOS) &&
-		    (src_caps[i] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-			continue;
-		/* its an unsupported Augmented PDO (PD3.0) */
-		if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED)
-			continue;
-
-		mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
-		/* Skip invalid voltage */
-		if (!mv)
-			continue;
-		/* Skip any voltage not supported by this board */
-		if (!pd_is_valid_input_voltage(mv))
-			continue;
-
-		if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-			uw = 250000 * (src_caps[i] & 0x3FF);
-		} else {
-			int ma = (src_caps[i] & 0x3FF) * 10;
-
-			ma = MIN(ma, PD_MAX_CURRENT_MA);
-			uw = ma * mv;
-		}
-
-		if (mv > max_mv)
-			continue;
-		uw = MIN(uw, PD_MAX_POWER_MW * 1000);
-		prefer_cur = 0;
-
-		/* Apply special rules in favor of voltage  */
-		if (IS_ENABLED(PD_PREFER_LOW_VOLTAGE)) {
-			if (uw == cur_uw && mv < cur_mv)
-				prefer_cur = 1;
-		} else if (IS_ENABLED(PD_PREFER_HIGH_VOLTAGE)) {
-			if (uw == cur_uw && mv > cur_mv)
-				prefer_cur = 1;
-		} else if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
-			/* Pick if the PDO provides more than desired. */
-			if (uw >= desired_uw) {
-				/* pick if cur_uw is less than desired watt */
-				if (cur_uw < desired_uw)
-					prefer_cur = 1;
-				else if (type == PD_PREFER_BUCK) {
-					/*
-					 * pick the smallest mV above prefer_mv
-					 */
-					if (mv >= prefer_mv && mv < cur_mv)
-						prefer_cur = 1;
-					/*
-					 * pick if cur_mv is less than
-					 * prefer_mv, and we have higher mV
-					 */
-					else if (cur_mv < prefer_mv &&
-						 mv > cur_mv)
-						prefer_cur = 1;
-				} else if (type == PD_PREFER_BOOST) {
-					/*
-					 * pick the largest mV below prefer_mv
-					 */
-					if (mv <= prefer_mv && mv > cur_mv)
-						prefer_cur = 1;
-					/*
-					 * pick if cur_mv is larger than
-					 * prefer_mv, and we have lower mV
-					 */
-					else if (cur_mv > prefer_mv &&
-						 mv < cur_mv)
-						prefer_cur = 1;
-				}
-			/*
-			 * pick the largest power if we don't see one staisfy
-			 * desired power
-			 */
-			} else if (cur_uw == 0 || uw > cur_uw) {
-				prefer_cur = 1;
-			}
-		}
-
-		/* Prefer higher power, except for tiebreaker */
-		has_preferred_pdo =
-			prefer_cur ||
-			(!IS_ENABLED(CONFIG_USB_PD_PREFER_MV) && uw > cur_uw);
-
-		if (has_preferred_pdo) {
-			ret = i;
-			cur_uw = uw;
-			cur_mv = mv;
-		}
-	}
-
-	if (selected_pdo)
-		*selected_pdo = src_caps[ret];
-
-	return ret;
-}
-
-void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
-			  uint32_t *min_mv)
-{
-	int max_ma, mw;
-
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
-		*max_mv = PDO_FIXED_VOLTAGE(pdo);
-		*min_mv = *max_mv;
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-		*max_mv = PDO_AUG_MAX_VOLTAGE(pdo);
-		*min_mv = PDO_AUG_MIN_VOLTAGE(pdo);
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
-		*max_mv = PDO_VAR_MAX_VOLTAGE(pdo);
-		*min_mv = PDO_VAR_MIN_VOLTAGE(pdo);
-	} else {
-		*max_mv = PDO_BATT_MAX_VOLTAGE(pdo);
-		*min_mv = PDO_BATT_MIN_VOLTAGE(pdo);
-	}
-
-	if (*max_mv == 0) {
-		*ma = 0;
-		*min_mv = 0;
-		return;
-	}
-
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
-		max_ma = PDO_FIXED_CURRENT(pdo);
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-		max_ma = PDO_AUG_MAX_CURRENT(pdo);
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
-		max_ma = PDO_VAR_MAX_CURRENT(pdo);
-	} else {
-		mw = PDO_BATT_MAX_POWER(pdo);
-		max_ma = 1000 * mw / PROCESS_ZERO_DIVISOR(*min_mv);
-	}
-	max_ma = MIN(max_ma,
-		     PD_MAX_POWER_MW * 1000 / PROCESS_ZERO_DIVISOR(*min_mv));
-	*ma = MIN(max_ma, PD_MAX_CURRENT_MA);
-}
-
-void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port)
-{
-	uint32_t pdo;
-	int pdo_index, flags = 0;
-	int uw;
-	int max_or_min_ma;
-	int max_or_min_mw;
-	int max_vbus;
-	int vpd_vbus_dcr;
-	int vpd_gnd_dcr;
-	uint32_t src_cap_cnt = pd_get_src_cap_cnt(port);
-	const uint32_t * const src_caps = pd_get_src_caps(port);
-	int charging_allowed;
-	int max_request_allowed;
-	uint32_t max_request_mv = pd_get_max_voltage();
-	uint32_t unused;
-
-	/*
-	 * If this port is the current charge port, or if there isn't an active
-	 * charge port, set this value to true. If CHARGE_PORT_NONE isn't
-	 * considered, then there can be a race condition in PD negotiation and
-	 * the charge manager which forces an incorrect request for
-	 * vSafe5V. This can then lead to a brownout condition when the input
-	 * current limit gets incorrectly set to 0.5A.
-	 */
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		int chg_port = charge_manager_get_selected_charge_port();
-
-		charging_allowed =
-			(chg_port == port || chg_port == CHARGE_PORT_NONE);
-	} else {
-		charging_allowed = 1;
-	}
-
-	if (IS_ENABLED(CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED))
-		max_request_allowed = pd_is_max_request_allowed();
-	else
-		max_request_allowed = 1;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled())
-		max_request_mv =
-			MIN(max_request_mv, dps_get_dynamic_voltage());
-
-	/*
-	 * If currently charging on a different port, or we are not allowed to
-	 * request the max voltage, then select vSafe5V
-	 */
-	if (charging_allowed && max_request_allowed) {
-		/* find pdo index for max voltage we can request */
-		pdo_index = pd_find_pdo_index(src_cap_cnt, src_caps,
-						max_request_mv, &pdo);
-	} else {
-		/* src cap 0 should be vSafe5V */
-		pdo_index = 0;
-		pdo = src_caps[0];
-	}
-
-	pd_extract_pdo_power(pdo, ma, mv, &unused);
-
-	/*
-	 * Adjust VBUS current if CTVPD device was detected.
-	 */
-	if (vpd_vdo > 0) {
-		max_vbus = VPD_VDO_MAX_VBUS(vpd_vdo);
-		vpd_vbus_dcr = VPD_VDO_VBUS_IMP(vpd_vdo) << 1;
-		vpd_gnd_dcr = VPD_VDO_GND_IMP(vpd_vdo);
-
-		/*
-		 * Valid max_vbus values:
-		 *   00b - 20000 mV
-		 *   01b - 30000 mV
-		 *   10b - 40000 mV
-		 *   11b - 50000 mV
-		 */
-		max_vbus = 20000 + max_vbus * 10000;
-		if (*mv > max_vbus)
-			*mv = max_vbus;
-
-		/*
-		 * 5000 mA cable: 150 = 750000 / 50000
-		 * 3000 mA cable: 250 = 750000 / 30000
-		 */
-		if (*ma > 3000)
-			*ma = 750000 / (150 + vpd_vbus_dcr + vpd_gnd_dcr);
-		else
-			*ma = 750000 / (250 + vpd_vbus_dcr + vpd_gnd_dcr);
-	}
-
-	uw = *ma * *mv;
-	/* Mismatch bit set if less power offered than the operating power */
-	if (uw < (1000 * PD_OPERATING_POWER_MW))
-		flags |= RDO_CAP_MISMATCH;
-
-#ifdef CONFIG_USB_PD_GIVE_BACK
-		/* Tell source we are give back capable. */
-		flags |= RDO_GIVE_BACK;
-
-		/*
-		 * BATTERY PDO: Inform the source that the sink will reduce
-		 * power to this minimum level on receipt of a GotoMin Request.
-		 */
-		max_or_min_mw = PD_MIN_POWER_MW;
-
-		/*
-		 * FIXED or VARIABLE PDO: Inform the source that the sink will
-		 * reduce current to this minimum level on receipt of a GotoMin
-		 * Request.
-		 */
-		max_or_min_ma = PD_MIN_CURRENT_MA;
-#else
-		/*
-		 * Can't give back, so set maximum current and power to
-		 * operating level.
-		 */
-		max_or_min_ma = *ma;
-		max_or_min_mw = uw / 1000;
-#endif
-
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-		int mw = uw / 1000;
-		*rdo = RDO_BATT(pdo_index + 1, mw, max_or_min_mw, flags);
-	} else {
-		*rdo = RDO_FIXED(pdo_index + 1, *ma, max_or_min_ma, flags);
-	}
-
-	/*
-	 * Ref: USB Power Delivery Specification
-	 * (Revision 3.0, Version 2.0 / Revision 2.0, Version 1.3)
-	 * 6.4.2.4 USB Communications Capable
-	 * 6.4.2.5 No USB Suspend
-	 *
-	 * If the port partner is capable of USB communication set the
-	 * USB Communications Capable flag.
-	 * If the port partner is sink device do not suspend USB as the
-	 * power can be used for charging.
-	 */
-	if (pd_get_partner_usb_comm_capable(port)) {
-		*rdo |= RDO_COMM_CAP;
-		if (pd_get_power_role(port) == PD_ROLE_SINK)
-			*rdo |= RDO_NO_SUSPEND;
-	}
-}
-
-void pd_process_source_cap(int port, int cnt, uint32_t *src_caps)
-{
-	pd_set_src_caps(port, cnt, src_caps);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		uint32_t ma, mv, pdo, unused;
-		uint32_t max_mv = pd_get_max_voltage();
-
-		if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled())
-			max_mv = MIN(max_mv, dps_get_dynamic_voltage());
-
-		/* Get max power info that we could request */
-		pd_find_pdo_index(pd_get_src_cap_cnt(port),
-					pd_get_src_caps(port),
-					max_mv, &pdo);
-		pd_extract_pdo_power(pdo, &ma, &mv, &unused);
-
-		/* Set max. limit, but apply 500mA ceiling */
-		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, PD_MIN_MA);
-		pd_set_input_current_limit(port, ma, mv);
-	}
-}
-#endif /* defined(PD_MAX_VOLTAGE_MV) && defined(PD_OPERATING_POWER_MW) */
-
-bool pd_is_battery_capable(void)
-{
-	bool capable;
-
-	/* Battery is present and at some minimum percentage. */
-	capable = (usb_get_battery_soc() >=
-		   CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC);
-
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-	/*
-	 * Not capable if the battery is in the disconnect state. The discharge
-	 * FET may not be enabled and so attempting being a SRC may cut off
-	 * our only power source at the time.
-	 */
-	capable &= (battery_get_disconnect_state() ==
-		    BATTERY_NOT_DISCONNECTED);
-#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	defined(CONFIG_BATTERY_PRESENT_GPIO)
-	/*
-	 * When battery is cutoff in ship mode it may not be reliable to
-	 * check if battery is present with its state of charge.
-	 * Also check if battery is initialized and ready to provide power.
-	 */
-	capable &= (battery_is_present() == BP_YES);
-#endif /* CONFIG_BATTERY_PRESENT_[CUSTOM|GPIO] */
-
-	return capable;
-}
-
-#ifdef CONFIG_USB_PD_TRY_SRC
-bool pd_is_try_source_capable(void)
-{
-	int i;
-	uint8_t try_src = 0;
-	bool new_try_src;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		try_src |= (pd_get_dual_role(i) == PD_DRP_TOGGLE_ON);
-
-	/*
-	 * Enable try source when dual-role toggling AND battery is capable
-	 * of powering the whole system.
-	 */
-	new_try_src = (try_src && pd_is_battery_capable());
-
-#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	/*
-	 * If a dedicated supplier is present, power is not a concern and
-	 * therefore allow Try.Src if we're toggling.
-	 */
-	new_try_src = try_src && (charge_manager_get_supplier() ==
-			     CHARGE_SUPPLIER_DEDICATED);
-#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
-
-	return new_try_src;
-}
-#endif /* CONFIG_USB_PD_TRY_SRC */
-
-static int get_bbram_idx(uint8_t port)
-{
-	if (port < MAX_SYSTEM_BBRAM_IDX_PD_PORTS)
-		return (port + SYSTEM_BBRAM_IDX_PD0);
-
-	return -1;
-}
-
-int pd_get_saved_port_flags(int port, uint8_t *flags)
-{
-	if (system_get_bbram(get_bbram_idx(port), flags) != EC_SUCCESS) {
-#ifndef CHIP_HOST
-		ccprintf("PD NVRAM FAIL");
-#endif
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void pd_set_saved_port_flags(int port, uint8_t flags)
-{
-	if (system_set_bbram(get_bbram_idx(port), flags) != EC_SUCCESS) {
-#ifndef CHIP_HOST
-		ccprintf("PD NVRAM FAIL");
-#endif
-	}
-}
-
-void pd_update_saved_port_flags(int port, uint8_t flag, uint8_t do_set)
-{
-	uint8_t saved_flags;
-
-	if (pd_get_saved_port_flags(port, &saved_flags) != EC_SUCCESS)
-		return;
-
-	if (do_set)
-		saved_flags |= flag;
-	else
-		saved_flags &= ~flag;
-
-	pd_set_saved_port_flags(port, saved_flags);
-}
diff --git a/common/usb_pd_host_cmd.c b/common/usb_pd_host_cmd.c
deleted file mode 100644
index 4261e8c1f0..0000000000
--- a/common/usb_pd_host_cmd.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Host commands for USB-PD module.
- */
-
-#include <string.h>
-
-#include "atomic.h"
-#include "battery.h"
-#include "charge_manager.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "tcpm/tcpm.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-#ifdef CONFIG_COMMON_RUNTIME
-struct ec_params_usb_pd_rw_hash_entry rw_hash_table[RW_HASH_ENTRIES];
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif /* CONFIG_COMMON_RUNTIME */
-
-#ifdef HAS_TASK_HOSTCMD
-
-static enum ec_status hc_pd_ports(struct host_cmd_handler_args *args)
-{
-	struct ec_response_usb_pd_ports *r = args->response;
-
-	r->num_ports = board_get_usb_pd_port_count();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS,
-		     hc_pd_ports,
-		     EC_VER_MASK(0));
-
-#ifdef CONFIG_HOSTCMD_RWHASHPD
-static enum ec_status
-hc_remote_rw_hash_entry(struct host_cmd_handler_args *args)
-{
-	int i, idx = 0, found = 0;
-	const struct ec_params_usb_pd_rw_hash_entry *p = args->params;
-	static int rw_hash_next_idx;
-
-	if (!p->dev_id)
-		return EC_RES_INVALID_PARAM;
-
-	for (i = 0; i < RW_HASH_ENTRIES; i++) {
-		if (p->dev_id == rw_hash_table[i].dev_id) {
-			idx = i;
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		idx = rw_hash_next_idx;
-		rw_hash_next_idx = rw_hash_next_idx + 1;
-		if (rw_hash_next_idx == RW_HASH_ENTRIES)
-			rw_hash_next_idx = 0;
-	}
-	memcpy(&rw_hash_table[idx], p, sizeof(*p));
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY,
-		     hc_remote_rw_hash_entry,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_RWHASHPD */
-
-#if defined(CONFIG_EC_CMD_PD_CHIP_INFO) && !defined(CONFIG_USB_PD_TCPC)
-static enum ec_status hc_remote_pd_chip_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_pd_chip_info *p = args->params;
-	struct ec_response_pd_chip_info_v1 info;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (tcpm_get_chip_info(p->port, p->live, &info))
-		return EC_RES_ERROR;
-
-	/*
-	 * Take advantage of the fact that v0 and v1 structs have the
-	 * same layout for v0 data. (v1 just appends data)
-	 */
-	args->response_size =
-		args->version ? sizeof(struct ec_response_pd_chip_info_v1)
-			      : sizeof(struct ec_response_pd_chip_info);
-
-	memcpy(args->response, &info, args->response_size);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO,
-		     hc_remote_pd_chip_info,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-#endif /* CONFIG_EC_CMD_PD_CHIP_INFO && !CONFIG_USB_PD_TCPC */
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_set_mode_request *p = args->params;
-
-	if ((p->port >= board_get_usb_pd_port_count()) ||
-	    (!p->svid) || (!p->opos))
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->cmd) {
-	case PD_EXIT_MODE:
-		if (pd_dfp_exit_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos))
-			pd_send_vdm(p->port, p->svid,
-				    CMD_EXIT_MODE | VDO_OPOS(p->opos), NULL, 0);
-		else {
-			CPRINTF("Failed exit mode\n");
-			return EC_RES_ERROR;
-		}
-		break;
-	case PD_ENTER_MODE:
-		if (pd_dfp_enter_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos))
-			pd_send_vdm(p->port, p->svid, CMD_ENTER_MODE |
-				    VDO_OPOS(p->opos), NULL, 0);
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE,
-		     hc_remote_pd_set_amode,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args)
-{
-	const uint8_t *port = args->params;
-	struct ec_params_usb_pd_discovery_entry *r = args->response;
-
-	if (*port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	r->vid = pd_get_identity_vid(*port);
-	r->ptype = pd_get_product_type(*port);
-
-	/* pid only included if vid is assigned */
-	if (r->vid)
-		r->pid = pd_get_identity_pid(*port);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY,
-		     hc_remote_pd_discovery,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
-{
-	struct svdm_amode_data *modep;
-	const struct ec_params_usb_pd_get_mode_request *p = args->params;
-	struct ec_params_usb_pd_get_mode_response *r = args->response;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	/* no more to send */
-	/* TODO(b/148528713): Use TCPMv2's separate storage for SOP'. */
-	if (p->svid_idx >= pd_get_svid_count(p->port, TCPCI_MSG_SOP)) {
-		r->svid = 0;
-		args->response_size = sizeof(r->svid);
-		return EC_RES_SUCCESS;
-	}
-
-	r->svid = pd_get_svid(p->port, p->svid_idx, TCPCI_MSG_SOP);
-	r->opos = 0;
-	memcpy(r->vdo, pd_get_mode_vdo(p->port, p->svid_idx, TCPCI_MSG_SOP),
-		sizeof(uint32_t) * PDO_MODES);
-	modep = pd_get_amode_data(p->port, TCPCI_MSG_SOP, r->svid);
-
-	if (modep)
-		r->opos = pd_alt_mode(p->port, TCPCI_MSG_SOP, r->svid);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE,
-		     hc_remote_pd_get_amode,
-		     EC_VER_MASK(0));
-
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
-
-#ifdef CONFIG_COMMON_RUNTIME
-static enum ec_status hc_remote_pd_dev_info(struct host_cmd_handler_args *args)
-{
-	const uint8_t *port = args->params;
-	struct ec_params_usb_pd_rw_hash_entry *r = args->response;
-	uint16_t dev_id;
-	uint32_t current_image;
-
-	if (*port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	pd_dev_get_rw_hash(*port, &dev_id, r->dev_rw_hash, &current_image);
-
-	r->dev_id = dev_id;
-	r->current_image = current_image;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO,
-		     hc_remote_pd_dev_info,
-		     EC_VER_MASK(0));
-
-static const enum pd_dual_role_states dual_role_map[USB_PD_CTRL_ROLE_COUNT] = {
-	[USB_PD_CTRL_ROLE_TOGGLE_ON]    = PD_DRP_TOGGLE_ON,
-	[USB_PD_CTRL_ROLE_TOGGLE_OFF]   = PD_DRP_TOGGLE_OFF,
-	[USB_PD_CTRL_ROLE_FORCE_SINK]   = PD_DRP_FORCE_SINK,
-	[USB_PD_CTRL_ROLE_FORCE_SOURCE] = PD_DRP_FORCE_SOURCE,
-	[USB_PD_CTRL_ROLE_FREEZE]       = PD_DRP_FREEZE,
-};
-
-static const mux_state_t typec_mux_map[USB_PD_CTRL_MUX_COUNT] = {
-	[USB_PD_CTRL_MUX_NONE] = USB_PD_MUX_NONE,
-	[USB_PD_CTRL_MUX_USB]  = USB_PD_MUX_USB_ENABLED,
-	[USB_PD_CTRL_MUX_AUTO] = USB_PD_MUX_DP_ENABLED,
-	[USB_PD_CTRL_MUX_DP]   = USB_PD_MUX_DP_ENABLED,
-	[USB_PD_CTRL_MUX_DOCK] = USB_PD_MUX_DOCK,
-};
-
-/*
- * Combines the following information into a single byte
- * Bit 0: Active/Passive cable
- * Bit 1: Optical/Non-optical cable
- * Bit 2: Legacy Thunderbolt adapter
- * Bit 3: Active Link Uni-Direction/Bi-Direction
- */
-static uint8_t get_pd_control_flags(int port)
-{
-	union tbt_mode_resp_cable cable_resp;
-	union tbt_mode_resp_device device_resp;
-	uint8_t control_flags = 0;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		return 0;
-
-	cable_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-	device_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
-
-	/*
-	 * Ref: USB Type-C Cable and Connector Specification
-	 * Table F-11 TBT3 Cable Discover Mode VDO Responses
-	 * For Passive cables, Active Cable Plug link training is set to 0
-	 */
-	control_flags |= (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-			 cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ?
-			 USB_PD_CTRL_ACTIVE_CABLE : 0;
-	control_flags |= cable_resp.tbt_cable == TBT_CABLE_OPTICAL ?
-			 USB_PD_CTRL_OPTICAL_CABLE : 0;
-	control_flags |= device_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY ?
-			 USB_PD_CTRL_TBT_LEGACY_ADAPTER : 0;
-	control_flags |= cable_resp.lsrx_comm == UNIDIR_LSRX_COMM ?
-			 USB_PD_CTRL_ACTIVE_LINK_UNIDIR : 0;
-
-	return control_flags;
-}
-
-static uint8_t pd_get_role_flags(int port)
-{
-	return (pd_get_power_role(port) == PD_ROLE_SOURCE ?
-			PD_CTRL_RESP_ROLE_POWER : 0) |
-		(pd_get_data_role(port) == PD_ROLE_DFP ?
-			PD_CTRL_RESP_ROLE_DATA : 0) |
-		(pd_get_vconn_state(port) ?
-			PD_CTRL_RESP_ROLE_VCONN : 0) |
-		(pd_get_partner_dual_role_power(port) ?
-			PD_CTRL_RESP_ROLE_DR_POWER : 0) |
-		(pd_get_partner_data_swap_capable(port) ?
-			PD_CTRL_RESP_ROLE_DR_DATA : 0) |
-		(pd_get_partner_usb_comm_capable(port) ?
-			PD_CTRL_RESP_ROLE_USB_COMM : 0) |
-		(pd_get_partner_unconstr_power(port) ?
-			PD_CTRL_RESP_ROLE_UNCONSTRAINED : 0);
-}
-
-static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_control *p = args->params;
-	struct ec_response_usb_pd_control_v2 *r_v2 = args->response;
-	struct ec_response_usb_pd_control_v1 *r_v1 = args->response;
-	struct ec_response_usb_pd_control *r = args->response;
-	const char *task_state_name;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (p->role >= USB_PD_CTRL_ROLE_COUNT ||
-	    p->mux >= USB_PD_CTRL_MUX_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	if (p->role != USB_PD_CTRL_ROLE_NO_CHANGE) {
-		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE))
-			pd_set_dual_role(p->port, dual_role_map[p->role]);
-		else
-			return EC_RES_INVALID_PARAM;
-	}
-
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-		p->mux != USB_PD_CTRL_MUX_NO_CHANGE)
-		usb_mux_set(p->port, typec_mux_map[p->mux],
-			    typec_mux_map[p->mux] == USB_PD_MUX_NONE ?
-			    USB_SWITCH_DISCONNECT :
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(p->port)));
-
-	if (p->swap == USB_PD_CTRL_SWAP_DATA) {
-		pd_request_data_swap(p->port);
-	} else if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) {
-		if (p->swap == USB_PD_CTRL_SWAP_POWER)
-			pd_request_power_swap(p->port);
-		else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-			p->swap == USB_PD_CTRL_SWAP_VCONN)
-			pd_request_vconn_swap(p->port);
-	}
-
-	switch (args->version) {
-	case 0:
-		r->enabled = pd_comm_is_enabled(p->port);
-		r->polarity = pd_get_polarity(p->port);
-		r->role = pd_get_power_role(p->port);
-		r->state = pd_get_task_state(p->port);
-		args->response_size = sizeof(*r);
-		break;
-	case 1:
-	case 2:
-		r_v2->enabled =
-			(pd_comm_is_enabled(p->port) ?
-				PD_CTRL_RESP_ENABLED_COMMS : 0) |
-			(pd_is_connected(p->port) ?
-				PD_CTRL_RESP_ENABLED_CONNECTED : 0) |
-			(pd_capable(p->port) ?
-				PD_CTRL_RESP_ENABLED_PD_CAPABLE : 0);
-		r_v2->role = pd_get_role_flags(p->port);
-		r_v2->polarity = pd_get_polarity(p->port);
-
-		r_v2->cc_state =  pd_get_task_cc_state(p->port);
-		task_state_name = pd_get_task_state_name(p->port);
-		if (task_state_name)
-			strzcpy(r_v2->state, task_state_name,
-				sizeof(r_v2->state));
-		else
-			r_v2->state[0] = '\0';
-
-		r_v2->control_flags = get_pd_control_flags(p->port);
-		if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-			r_v2->dp_mode = get_dp_pin_mode(p->port);
-			r_v2->cable_speed = get_tbt_cable_speed(p->port);
-			r_v2->cable_gen = get_tbt_rounded_support(p->port);
-		}
-
-		if (args->version == 1)
-			args->response_size = sizeof(*r_v1);
-		else
-			args->response_size = sizeof(*r_v2);
-
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL,
-		     hc_usb_pd_control,
-		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
-#endif /* CONFIG_COMMON_RUNTIME */
-
-#if defined(CONFIG_HOSTCMD_FLASHPD) && defined(CONFIG_USB_PD_TCPMV2)
-static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_fw_update *p = args->params;
-	int port = p->port;
-	int rv = EC_RES_SUCCESS;
-	const uint32_t *data = &(p->size) + 1;
-	int i, size;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (p->size + sizeof(*p) > args->params_size)
-		return EC_RES_INVALID_PARAM;
-
-#if defined(CONFIG_CHARGE_MANAGER) && defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||   \
-	 defined(CONFIG_BATTERY_PRESENT_GPIO))
-	/*
-	 * Do not allow PD firmware update if no battery and this port
-	 * is sinking power, because we will lose power.
-	 */
-	if (battery_is_present() != BP_YES &&
-			charge_manager_get_active_charge_port() == port)
-		return EC_RES_UNAVAILABLE;
-#endif
-
-	switch (p->cmd) {
-	case USB_PD_FW_REBOOT:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_REBOOT, NULL, 0);
-		/*
-		 * Return immediately to free pending i2c bus.  Host needs to
-		 * manage this delay.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_FLASH_ERASE:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_ERASE, NULL, 0);
-		/*
-		 * Return immediately.  Host needs to manage delays here which
-		 * can be as long as 1.2 seconds on 64KB RW flash.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_ERASE_SIG:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0);
-		break;
-
-	case USB_PD_FW_FLASH_WRITE:
-		/* Data size must be a multiple of 4 */
-		if (!p->size || p->size % 4)
-			return EC_RES_INVALID_PARAM;
-
-		size = p->size / 4;
-		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
-				data + i, MIN(size - i, VDO_MAX_SIZE - 1));
-		}
-		return EC_RES_SUCCESS;
-
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return rv;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-			hc_remote_flash,
-			EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_FLASHPD && CONFIG_USB_PD_TCPMV2 */
-
-#ifdef CONFIG_MKBP_EVENT
-__overridable void pd_notify_dp_alt_mode_entry(int port)
-{
-	(void)port;
-	CPRINTS("Notifying AP of DP Alt Mode Entry...");
-	mkbp_send_event(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED);
-}
-#endif /* CONFIG_MKBP_EVENT */
-
-__overridable enum ec_pd_port_location board_get_pd_port_location(int port)
-{
-	(void)port;
-	return EC_PD_PORT_LOCATION_UNKNOWN;
-}
-
-static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_get_pd_port_caps *p = args->params;
-	struct ec_response_get_pd_port_caps *r = args->response;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	/* Power Role */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE))
-		r->pd_power_role_cap = EC_PD_POWER_ROLE_DUAL;
-	else
-		r->pd_power_role_cap = EC_PD_POWER_ROLE_SINK;
-
-	/* Try-Power Role */
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_SOURCE;
-	else
-		r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_NONE;
-
-	if (IS_ENABLED(CONFIG_USB_VPD) ||
-	    IS_ENABLED(CONFIG_USB_CTVPD))
-		r->pd_data_role_cap = EC_PD_DATA_ROLE_UFP;
-	else
-		r->pd_data_role_cap = EC_PD_DATA_ROLE_DUAL;
-
-	/* Allow boards to override the locations from UNKNOWN if desired */
-	r->pd_port_location = board_get_pd_port_location(p->port);
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS,
-		     hc_get_pd_port_caps,
-		     EC_VER_MASK(0));
-
-#ifdef CONFIG_HOSTCMD_PD_CONTROL
-static enum ec_status pd_control(struct host_cmd_handler_args *args)
-{
-	static int pd_control_disabled[CONFIG_USB_PD_PORT_MAX_COUNT];
-	const struct ec_params_pd_control *cmd = args->params;
-	int enable = 0;
-
-	if (cmd->chip >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	/* Always allow disable command */
-	if (cmd->subcmd == PD_CONTROL_DISABLE) {
-		pd_control_disabled[cmd->chip] = 1;
-		return EC_RES_SUCCESS;
-	}
-
-	if (pd_control_disabled[cmd->chip])
-		return EC_RES_ACCESS_DENIED;
-
-	if (cmd->subcmd == PD_SUSPEND) {
-		if (!pd_firmware_upgrade_check_power_readiness(cmd->chip))
-			return EC_RES_BUSY;
-		enable = 0;
-	} else if (cmd->subcmd == PD_RESUME) {
-		enable = 1;
-	} else if (cmd->subcmd == PD_RESET) {
-#ifdef HAS_TASK_PDCMD
-		board_reset_pd_mcu();
-#else
-		return EC_RES_INVALID_COMMAND;
-#endif
-	} else if (cmd->subcmd == PD_CHIP_ON && board_set_tcpc_power_mode) {
-		board_set_tcpc_power_mode(cmd->chip, 1);
-		return EC_RES_SUCCESS;
-	} else {
-		return EC_RES_INVALID_COMMAND;
-	}
-
-	pd_comm_enable(cmd->chip, enable);
-	pd_set_suspend(cmd->chip, !enable);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_CONTROL, pd_control, EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_PD_CONTROL */
-
-#if !defined(CONFIG_USB_PD_TCPM_STUB) && !defined(TEST_BUILD)
-/*
- * PD host event status for host command
- * Note: this variable must be aligned on 4-byte boundary because we pass the
- * address to atomic_ functions which use assembly to access them.
- */
-static uint32_t pd_host_event_status __aligned(4);
-
-static enum ec_status
-hc_pd_host_event_status(struct host_cmd_handler_args *args)
-{
-	struct ec_response_host_event_status *r = args->response;
-
-	/* Read and clear the host event status to return to AP */
-	r->status = atomic_clear(&pd_host_event_status);
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_PD_HOST_EVENT_STATUS, hc_pd_host_event_status,
-		     EC_VER_MASK(0));
-
-/* Send host event up to AP */
-void pd_send_host_event(int mask)
-{
-	/* mask must be set */
-	if (!mask)
-		return;
-
-	atomic_or(&pd_host_event_status, mask);
-	/* interrupt the AP */
-	host_set_single_event(EC_HOST_EVENT_PD_MCU);
-}
-#endif /* ! CONFIG_USB_PD_TCPM_STUB && ! TEST_BUILD */
-
-#endif /* HAS_TASK_HOSTCMD */
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
deleted file mode 100644
index de6fc63a60..0000000000
--- a/common/usb_pd_policy.c
+++ /dev/null
@@ -1,969 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "mkbp_event.h"
-#include "registers.h"
-#include "rsa.h"
-#include "sha256.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-/*
- * This file is currently only used for TCPMv1, and would need changes before
- * being used for TCPMv2. One example: PD_FLAGS_* are TCPMv1 only.
- */
-#ifndef CONFIG_USB_PD_TCPMV1
-#error This file must only be used with TCPMv1
-#endif
-
-static int rw_flash_changed = 1;
-
-__overridable void pd_check_pr_role(int port, enum pd_power_role pr_role,
-				    int flags)
-{
-	/*
-	 * If partner is dual-role power and dualrole toggling is on, consider
-	 * if a power swap is necessary.
-	 */
-	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
-	    pd_get_dual_role(port) == PD_DRP_TOGGLE_ON) {
-		/*
-		 * If we are a sink and partner is not unconstrained, then
-		 * swap to become a source. If we are source and partner is
-		 * unconstrained, swap to become a sink.
-		 */
-		int partner_unconstrained = flags & PD_FLAGS_PARTNER_UNCONSTR;
-
-		if ((!partner_unconstrained && pr_role == PD_ROLE_SINK) ||
-		    (partner_unconstrained && pr_role == PD_ROLE_SOURCE))
-			pd_request_power_swap(port);
-	}
-}
-
-__overridable void pd_check_dr_role(int port, enum pd_data_role dr_role,
-				    int flags)
-{
-	/* If UFP, try to switch to DFP */
-	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
-		pd_request_data_swap(port);
-}
-
-#ifdef CONFIG_MKBP_EVENT
-static int dp_alt_mode_entry_get_next_event(uint8_t *data)
-{
-	return EC_SUCCESS;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED,
-		     dp_alt_mode_entry_get_next_event);
-#endif /* CONFIG_MKBP_EVENT */
-
-/* Last received source cap */
-static uint32_t pd_src_caps[CONFIG_USB_PD_PORT_MAX_COUNT][PDO_MAX_OBJECTS];
-static uint8_t pd_src_cap_cnt[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-const uint32_t * const pd_get_src_caps(int port)
-{
-	return pd_src_caps[port];
-}
-
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-	int i;
-
-	pd_src_cap_cnt[port] = cnt;
-
-	for (i = 0; i < cnt; i++)
-		pd_src_caps[port][i] = *src_caps++;
-}
-
-uint8_t pd_get_src_cap_cnt(int port)
-{
-	return pd_src_cap_cnt[port];
-}
-
-static struct pd_cable cable[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-enum pd_rev_type get_usb_pd_cable_revision(int port)
-{
-	return cable[port].rev;
-}
-
-bool consume_sop_prime_repeat_msg(int port, uint8_t msg_id)
-{
-	if (cable[port].last_sop_p_msg_id != msg_id) {
-		cable[port].last_sop_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-bool consume_sop_prime_prime_repeat_msg(int port, uint8_t msg_id)
-{
-	if (cable[port].last_sop_p_p_msg_id != msg_id) {
-		cable[port].last_sop_p_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-__maybe_unused static uint8_t is_sop_prime_ready(int port)
-{
-	/*
-	 * Ref: USB PD 3.0 sec 2.5.4: When an Explicit Contract is in place the
-	 * VCONN Source (either the DFP or the UFP) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP’’ Packets
-	 *
-	 * Ref: USB PD 2.0 sec 2.4.4: When an Explicit Contract is in place the
-	 * DFP (either the Source or the Sink) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP� Packets.
-	 * Sec 3.6.11 : Before communicating with a Cable Plug a Port Should
-	 * ensure that it is the Vconn Source
-	 */
-	return (pd_get_vconn_state(port) &&
-		(IS_ENABLED(CONFIG_USB_PD_REV30) ||
-		 (pd_get_data_role(port) == PD_ROLE_DFP)));
-}
-
-void reset_pd_cable(int port)
-{
-	memset(&cable[port], 0, sizeof(cable[port]));
-	cable[port].last_sop_p_msg_id = INVALID_MSG_ID_COUNTER;
-	cable[port].last_sop_p_p_msg_id = INVALID_MSG_ID_COUNTER;
-}
-
-bool should_enter_usb4_mode(int port)
-{
-	return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	       cable[port].flags & CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void enable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void disable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-#ifdef CONFIG_USB_PD_ALT_MODE
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-
-static struct pd_discovery discovery[CONFIG_USB_PD_PORT_MAX_COUNT]
-				    [DISCOVERY_TYPE_COUNT];
-static struct partner_active_modes partner_amodes[CONFIG_USB_PD_PORT_MAX_COUNT]
-						 [AMODE_TYPE_COUNT];
-
-static bool is_vdo_present(int cnt, int index)
-{
-	return cnt > index;
-}
-
-static bool is_modal(int port, int cnt, const uint32_t *payload)
-{
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-	       PD_IDH_IS_MODAL(payload[VDO_INDEX_IDH]);
-}
-
-static bool is_tbt_compat_mode(int port, int cnt, const uint32_t *payload)
-{
-	/*
-	 * Ref: USB Type-C cable and connector specification
-	 * F.2.5 TBT3 Device Discover Mode Responses
-	 */
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-	       PD_VDO_RESP_MODE_INTEL_TBT(payload[VDO_INDEX_IDH]);
-}
-
-static bool cable_supports_tbt_speed(int port)
-{
-	enum tbt_compat_cable_speed tbt_cable_speed = get_tbt_cable_speed(port);
-
-	return (tbt_cable_speed == TBT_SS_TBT_GEN3 ||
-		tbt_cable_speed == TBT_SS_U32_GEN1_GEN2);
-}
-
-static bool is_tbt_compat_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-		(cable[port].flags & CABLE_FLAGS_TBT_COMPAT_ENABLE));
-}
-
-static void enable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void disable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags &= ~CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void limit_tbt_cable_speed(int port)
-{
-	/* Cable flags are cleared when cable reset is called */
-	cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED;
-}
-
-static inline bool is_limit_tbt_cable_speed(int port)
-{
-	return !!(cable[port].flags & CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED);
-}
-
-static bool is_intel_svid(int port, enum tcpci_msg_type type)
-{
-	int i;
-
-	for (i = 0; i < discovery[port][type].svid_cnt; i++) {
-		if (pd_get_svid(port, i, type) == USB_VID_INTEL)
-			return true;
-	}
-
-	return false;
-}
-
-static inline bool is_usb4_mode_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-		(cable[port].flags & CABLE_FLAGS_USB4_CAPABLE));
-}
-
-static inline void enable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_USB4_CAPABLE;
-}
-
-static inline void disable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_USB4_CAPABLE;
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure 5-1 USB4 Discovery and Entry Flow Model.
- *
- * Note: USB Type-C Cable and Connector Specification
- * doesn't include details for Revision 2 cables.
- *
- *                         Passive Cable
- *                                |
- *                -----------------------------------
- *                |                                 |
- *           Revision 2                        Revision 3
- *          USB Signalling                   USB Signalling
- *             |                                     |
- *     ------------------            -------------------------
- *     |       |        |            |       |       |       |
- * USB2.0   USB3.1    USB3.1       USB3.2   USB4   USB3.2   USB2
- *   |      Gen1      Gen1 Gen2    Gen2     Gen3   Gen1       |
- *   |       |          |           |        |       |       Exit
- *   --------           ------------         --------        USB4
- *      |                    |                  |          Discovery.
- *    Exit          Is DFP Gen3 Capable?     Enter USB4
- *    USB4                  |                with respective
- *   Discovery.   --- No ---|--- Yes ---     cable speed.
- *                |                    |
- *    Enter USB4 with             Is Cable TBT3
- *    respective cable                 |
- *    speed.                 --- No ---|--- Yes ---
- *                           |                    |
- *                   Enter USB4 with        Enter USB4 with
- *                   TBT Gen2 passive       TBT Gen3 passive
- *                   cable.                 cable.
- *
- */
-static bool is_cable_ready_to_enter_usb4(int port, int cnt)
-{
-	/* TODO: USB4 enter mode for Active cables */
-	struct pd_discovery *disc = &discovery[port][TCPCI_MSG_SOP_PRIME];
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	    (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) &&
-	    is_vdo_present(cnt, VDO_INDEX_PTYPE_CABLE1)) {
-		switch (cable[port].rev) {
-		case PD_REV30:
-			switch (disc->identity.product_t1.p_rev30.ss) {
-			case USB_R30_SS_U40_GEN3:
-			case USB_R30_SS_U32_U40_GEN1:
-				return true;
-			case USB_R30_SS_U32_U40_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-			}
-		case PD_REV20:
-			switch (disc->identity.product_t1.p_rev20.ss) {
-			case USB_R20_SS_U31_GEN1_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-			}
-		default:
-			disable_usb4_mode(port);
-		}
-	}
-	return false;
-}
-
-void pd_dfp_discovery_init(int port)
-{
-	memset(&discovery[port], 0, sizeof(struct pd_discovery));
-}
-
-void pd_dfp_mode_init(int port)
-{
-	memset(&partner_amodes[port], 0, sizeof(partner_amodes[0]));
-}
-
-static int dfp_discover_ident(uint32_t *payload)
-{
-	payload[0] = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT);
-	return 1;
-}
-
-static int dfp_discover_svids(uint32_t *payload)
-{
-	payload[0] = VDO(USB_SID_PD, 1, CMD_DISCOVER_SVID);
-	return 1;
-}
-
-struct pd_discovery *pd_get_am_discovery_and_notify_access(
-				int port, enum tcpci_msg_type type)
-{
-	return (struct pd_discovery *)pd_get_am_discovery(port, type);
-}
-
-const struct pd_discovery *pd_get_am_discovery(int port,
-			enum tcpci_msg_type type)
-{
-	return &discovery[port][type];
-}
-
-struct partner_active_modes *
-pd_get_partner_active_modes(int port, enum tcpci_msg_type type)
-{
-	assert(type < AMODE_TYPE_COUNT);
-	return &partner_amodes[port][type];
-}
-
-/* Note: Enter mode flag is not needed by TCPMv1 */
-void pd_set_dfp_enter_mode_flag(int port, bool set)
-{
-}
-
-/**
- * Return the discover alternate mode payload data
- *
- * @param port    USB-C port number
- * @param payload Pointer to payload data to fill
- * @return 1 if valid SVID present else 0
- */
-static int dfp_discover_modes(int port, uint32_t *payload)
-{
-	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
-	uint16_t svid = disc->svids[disc->svid_idx].svid;
-
-	if (disc->svid_idx >= disc->svid_cnt)
-		return 0;
-
-	payload[0] = VDO(svid, 1, CMD_DISCOVER_MODES);
-
-	return 1;
-}
-
-static bool is_usb4_vdo(int port, int cnt, uint32_t *payload)
-{
-	enum idh_ptype ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
-
-	if (IS_PD_IDH_UFP_PTYPE(ptype)) {
-		/*
-		 * Ref: USB Type-C Cable and Connector Specification
-		 * Figure 5-1 USB4 Discovery and Entry Flow Model
-		 * Device USB4 VDO detection.
-		 */
-		return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-		       is_vdo_present(cnt, VDO_INDEX_PTYPE_UFP1_VDO) &&
-		       PD_PRODUCT_IS_USB4(payload[VDO_INDEX_PTYPE_UFP1_VDO]);
-	}
-	return false;
-}
-
-static int process_am_discover_ident_sop(int port, int cnt, uint32_t head,
-					 uint32_t *payload,
-					 enum tcpci_msg_type *rtype)
-{
-	pd_dfp_discovery_init(port);
-	pd_dfp_mode_init(port);
-	dfp_consume_identity(port, TCPCI_MSG_SOP, cnt, payload);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) && is_sop_prime_ready(port) &&
-	    board_is_tbt_usb4_port(port)) {
-		/* Enable USB4 mode if USB4 VDO present and port partner
-		 * supports USB Rev 3.0.
-		 */
-		if (is_usb4_vdo(port, cnt, payload) &&
-		    PD_HEADER_REV(head) == PD_REV30)
-			enable_usb4_mode(port);
-
-		/*
-		 * Enable Thunderbolt-compatible mode if the modal operation is
-		 * supported.
-		 */
-		if (is_modal(port, cnt, payload))
-			enable_tbt_compat_mode(port);
-
-		if (is_modal(port, cnt, payload) ||
-		    is_usb4_vdo(port, cnt, payload)) {
-			*rtype = TCPCI_MSG_SOP_PRIME;
-			return dfp_discover_ident(payload);
-		}
-	}
-
-	return dfp_discover_svids(payload);
-}
-
-static int process_am_discover_ident_sop_prime(int port, int cnt, uint32_t head,
-					       uint32_t *payload)
-{
-	dfp_consume_identity(port, TCPCI_MSG_SOP_PRIME, cnt, payload);
-	cable[port].rev = PD_HEADER_REV(head);
-
-	/*
-	 * Enter USB4 mode if the cable supports USB4 operation and has USB4
-	 * VDO.
-	 */
-	if (is_usb4_mode_enabled(port) &&
-	    is_cable_ready_to_enter_usb4(port, cnt)) {
-		enable_enter_usb4_mode(port);
-		usb_mux_set_safe_mode(port);
-		/*
-		 * To change the mode of operation from USB4 the port needs to
-		 * be reconfigured.
-		 * Ref: USB Type-C Cable and Connectot Spec section 5.4.4.
-		 */
-		disable_tbt_compat_mode(port);
-		return 0;
-	}
-
-	/*
-	 * Disable Thunderbolt-compatible mode if the cable does not support
-	 * superspeed.
-	 */
-	if (is_tbt_compat_enabled(port) &&
-	    get_tbt_cable_speed(port) < TBT_SS_U31_GEN1)
-		disable_tbt_compat_mode(port);
-
-	return dfp_discover_svids(payload);
-}
-
-static int process_am_discover_svids(int port, int cnt, uint32_t *payload,
-				     enum tcpci_msg_type sop,
-				     enum tcpci_msg_type *rtype)
-{
-	/*
-	 * The pd_discovery structure stores SOP and SOP' discovery results
-	 * separately, but TCPMv1 depends on one-dimensional storage of SVIDs
-	 * and modes. Therefore, always use TCPCI_MSG_SOP in TCPMv1.
-	 */
-	dfp_consume_svids(port, sop, cnt, payload);
-
-	/*
-	 * Ref: USB Type-C Cable and Connector Specification,
-	 * figure F-1: TBT3 Discovery Flow
-	 *
-	 * For USB4 mode if device or cable doesn't have Intel SVID,
-	 * disable Thunderbolt-Compatible mode directly enter USB4 mode
-	 * with USB3.2 Gen1/Gen2 speed.
-	 *
-	 * For Thunderbolt-compatible, check if 0x8087 is received for
-	 * Discover SVID SOP. If not, disable Thunderbolt-compatible mode
-	 *
-	 * If 0x8087 is not received for Discover SVID SOP' limit to TBT
-	 * passive Gen 2 cable.
-	 */
-	if (is_tbt_compat_enabled(port)) {
-		bool intel_svid = is_intel_svid(port, sop);
-		if (!intel_svid) {
-			if (is_usb4_mode_enabled(port)) {
-				disable_tbt_compat_mode(port);
-				cable[port].cable_mode_resp.tbt_cable_speed =
-					TBT_SS_U32_GEN1_GEN2;
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-
-			if (sop == TCPCI_MSG_SOP_PRIME)
-				limit_tbt_cable_speed(port);
-			else
-				disable_tbt_compat_mode(port);
-		} else if (sop == TCPCI_MSG_SOP) {
-			*rtype = TCPCI_MSG_SOP_PRIME;
-			return dfp_discover_svids(payload);
-		}
-	}
-
-	return dfp_discover_modes(port, payload);
-}
-
-static int process_tbt_compat_discover_modes(int port,
-					     enum tcpci_msg_type sop,
-					     uint32_t *payload,
-					     enum tcpci_msg_type *rtype)
-{
-	int rsize;
-
-	/* Initialize transmit type to SOP */
-	*rtype = TCPCI_MSG_SOP;
-
-	/*
-	 * For active cables, Enter mode: SOP', SOP'', SOP
-	 * Ref: USB Type-C Cable and Connector Specification, figure F-1: TBT3
-	 * Discovery Flow and Section F.2.7 TBT3 Cable Enter Mode Command.
-	 */
-	if (sop == TCPCI_MSG_SOP_PRIME) {
-		/* Store Discover Mode SOP' response */
-		cable[port].cable_mode_resp.raw_value = payload[1];
-
-		if (is_usb4_mode_enabled(port)) {
-			/*
-			 * If Cable is not Thunderbolt Gen 3
-			 * capable or Thunderbolt Gen1_Gen2
-			 * capable, disable USB4 mode and
-			 * continue flow for
-			 * Thunderbolt-compatible mode
-			 */
-			if (cable_supports_tbt_speed(port)) {
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-			disable_usb4_mode(port);
-		}
-
-		/*
-		 * Send TBT3 Cable Enter Mode (SOP') for active cables,
-		 * otherwise send TBT3 Device Enter Mode (SOP).
-		 */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			*rtype = TCPCI_MSG_SOP_PRIME;
-
-		rsize = enter_tbt_compat_mode(port, *rtype, payload);
-	} else {
-		/* Store Discover Mode SOP response */
-		cable[port].dev_mode_resp.raw_value = payload[1];
-
-		if (is_limit_tbt_cable_speed(port)) {
-			/*
-			 * Passive cable has Nacked for Discover SVID.
-			 * No need to do Discover modes of cable.
-			 * Enter into device Thunderbolt-compatible mode.
-			 */
-			rsize = enter_tbt_compat_mode(port, *rtype, payload);
-		} else {
-			/* Discover modes for SOP' */
-			discovery[port][TCPCI_MSG_SOP].svid_idx--;
-			rsize = dfp_discover_modes(port, payload);
-			*rtype = TCPCI_MSG_SOP_PRIME;
-		}
-	}
-
-	return rsize;
-}
-
-static int obj_cnt_enter_tbt_compat_mode(int port, enum tcpci_msg_type sop,
-					 uint32_t *payload,
-					 enum tcpci_msg_type *rtype)
-{
-	struct pd_discovery *disc = &discovery[port][TCPCI_MSG_SOP_PRIME];
-
-	/* Enter mode SOP' for active cables */
-	if (sop == TCPCI_MSG_SOP_PRIME) {
-		/* Check if the cable has a SOP'' controller */
-		if (disc->identity.product_t1.a_rev20.sop_p_p)
-			*rtype = TCPCI_MSG_SOP_PRIME_PRIME;
-		return enter_tbt_compat_mode(port, *rtype, payload);
-	}
-
-	/* Enter Mode SOP'' for active cables with SOP'' controller */
-	if (sop == TCPCI_MSG_SOP_PRIME_PRIME)
-		return enter_tbt_compat_mode(port, *rtype, payload);
-
-	/* Update Mux state to Thunderbolt-compatible mode. */
-	set_tbt_compat_mode_ready(port);
-	/* No response once device (and cable) acks */
-	return 0;
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
-
-int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-	    uint32_t head, enum tcpci_msg_type *rtype)
-{
-	int cmd = PD_VDO_CMD(payload[0]);
-	int cmd_type = PD_VDO_CMDT(payload[0]);
-	int (*func)(int port, uint32_t *payload) = NULL;
-
-	int rsize = 1; /* VDM header at a minimum */
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	enum tcpci_msg_type sop = PD_HEADER_GET_SOP(head);
-#endif
-
-	/* Transmit SOP messages by default */
-	*rtype = TCPCI_MSG_SOP;
-
-	payload[0] &= ~VDO_CMDT_MASK;
-	*rpayload = payload;
-
-	if (cmd_type == CMDT_INIT) {
-		switch (cmd) {
-		case CMD_DISCOVER_IDENT:
-			func = svdm_rsp.identity;
-			break;
-		case CMD_DISCOVER_SVID:
-			func = svdm_rsp.svids;
-			break;
-		case CMD_DISCOVER_MODES:
-			func = svdm_rsp.modes;
-			break;
-		case CMD_ENTER_MODE:
-			func = svdm_rsp.enter_mode;
-			break;
-		case CMD_DP_STATUS:
-			if (svdm_rsp.amode)
-				func = svdm_rsp.amode->status;
-			break;
-		case CMD_DP_CONFIG:
-			if (svdm_rsp.amode)
-				func = svdm_rsp.amode->config;
-			break;
-		case CMD_EXIT_MODE:
-			func = svdm_rsp.exit_mode;
-			break;
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-		case CMD_ATTENTION:
-			/*
-			 * attention is only SVDM with no response
-			 * (just goodCRC) return zero here.
-			 */
-			dfp_consume_attention(port, payload);
-			return 0;
-#endif
-		default:
-			CPRINTF("ERR:CMD:%d\n", cmd);
-			rsize = 0;
-		}
-		if (func)
-			rsize = func(port, payload);
-		else /* not supported : NACK it */
-			rsize = 0;
-		if (rsize >= 1)
-			payload[0] |= VDO_CMDT(CMDT_RSP_ACK);
-		else if (!rsize) {
-			payload[0] |= VDO_CMDT(CMDT_RSP_NAK);
-			rsize = 1;
-		} else {
-			payload[0] |= VDO_CMDT(CMDT_RSP_BUSY);
-			rsize = 1;
-		}
-		payload[0] |=
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-	} else if (cmd_type == CMDT_RSP_ACK) {
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-		struct svdm_amode_data *modep;
-
-		modep = pd_get_amode_data(port, TCPCI_MSG_SOP,
-					  PD_VDO_VID(payload[0]));
-#endif
-		switch (cmd) {
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-		case CMD_DISCOVER_IDENT:
-			/* Received a SOP' Discover Ident msg */
-			if (sop == TCPCI_MSG_SOP_PRIME) {
-				rsize = process_am_discover_ident_sop_prime(
-					port, cnt, head, payload);
-				/* Received a SOP Discover Ident Message */
-			} else {
-				rsize = process_am_discover_ident_sop(
-					port, cnt, head, payload, rtype);
-			}
-			break;
-		case CMD_DISCOVER_SVID:
-			rsize = process_am_discover_svids(port, cnt, payload,
-							  sop, rtype);
-			break;
-		case CMD_DISCOVER_MODES:
-			dfp_consume_modes(port, sop, cnt, payload);
-			if (is_tbt_compat_enabled(port) &&
-			    is_tbt_compat_mode(port, cnt, payload)) {
-				rsize = process_tbt_compat_discover_modes(
-					port, sop, payload, rtype);
-				break;
-			}
-
-			rsize = dfp_discover_modes(port, payload);
-			/* enter the default mode for DFP */
-			if (!rsize) {
-				/*
-				 * Disabling Thunderbolt-Compatible mode if
-				 * discover mode response doesn't include Intel
-				 * SVID.
-				 */
-				disable_tbt_compat_mode(port);
-				payload[0] = pd_dfp_enter_mode(
-					port, TCPCI_MSG_SOP, 0, 0);
-				if (payload[0])
-					rsize = 1;
-			}
-			break;
-		case CMD_ENTER_MODE:
-			if (is_tbt_compat_enabled(port)) {
-				rsize = obj_cnt_enter_tbt_compat_mode(
-					port, sop, payload, rtype);
-				/*
-				 * Continue with PD flow if
-				 * Thunderbolt-compatible mode is disabled.
-				 */
-			} else if (!modep) {
-				rsize = 0;
-			} else {
-				if (!modep->opos)
-					pd_dfp_enter_mode(port, TCPCI_MSG_SOP,
-							0, 0);
-
-				if (modep->opos) {
-					rsize = modep->fx->status(port,
-								  payload);
-					payload[0] |= PD_VDO_OPOS(modep->opos);
-				}
-			}
-			break;
-		case CMD_DP_STATUS:
-			/* DP status response & UFP's DP attention have same
-			   payload */
-			dfp_consume_attention(port, payload);
-			if (modep && modep->opos)
-				rsize = modep->fx->config(port, payload);
-			else
-				rsize = 0;
-			break;
-		case CMD_DP_CONFIG:
-			if (modep && modep->opos && modep->fx->post_config)
-				modep->fx->post_config(port);
-			/* no response after DFPs ack */
-			rsize = 0;
-			break;
-		case CMD_EXIT_MODE:
-			/* no response after DFPs ack */
-			rsize = 0;
-			break;
-#endif
-		case CMD_ATTENTION:
-			/* no response after DFPs ack */
-			rsize = 0;
-			break;
-		default:
-			CPRINTF("ERR:CMD:%d\n", cmd);
-			rsize = 0;
-		}
-
-		payload[0] |= VDO_CMDT(CMDT_INIT);
-		payload[0] |=
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	} else if (cmd_type == CMDT_RSP_BUSY) {
-		switch (cmd) {
-		case CMD_DISCOVER_IDENT:
-		case CMD_DISCOVER_SVID:
-		case CMD_DISCOVER_MODES:
-			/* resend if its discovery */
-			rsize = 1;
-			break;
-		case CMD_ENTER_MODE:
-			/* Error */
-			CPRINTF("ERR:ENTBUSY\n");
-			rsize = 0;
-			break;
-		case CMD_EXIT_MODE:
-			rsize = 0;
-			break;
-		default:
-			rsize = 0;
-		}
-	} else if (cmd_type == CMDT_RSP_NAK) {
-		/* Passive cable Nacked for Discover SVID */
-		if (cmd == CMD_DISCOVER_SVID && is_tbt_compat_enabled(port) &&
-		    sop == TCPCI_MSG_SOP_PRIME &&
-		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
-			limit_tbt_cable_speed(port);
-			rsize = dfp_discover_modes(port, payload);
-		} else {
-			rsize = 0;
-		}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
-	} else {
-		CPRINTF("ERR:CMDT:%d\n", cmd);
-		/* do not answer */
-		rsize = 0;
-	}
-	return rsize;
-}
-
-#else
-
-int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-	    uint32_t head, enum tcpci_msg_type *rtype)
-{
-	return 0;
-}
-
-#endif /* CONFIG_USB_PD_ALT_MODE */
-
-#define FW_RW_END                                                 \
-	(CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF + \
-	 CONFIG_RW_SIZE)
-
-uint8_t *flash_hash_rw(void)
-{
-	static struct sha256_ctx ctx;
-
-	/* re-calculate RW hash when changed as its time consuming */
-	if (rw_flash_changed) {
-		rw_flash_changed = 0;
-		SHA256_init(&ctx);
-		SHA256_update(&ctx,
-			      (void *)CONFIG_PROGRAM_MEMORY_BASE +
-				      CONFIG_RW_MEM_OFF,
-			      CONFIG_RW_SIZE - RSANUMBYTES);
-		return SHA256_final(&ctx);
-	} else {
-		return ctx.buf;
-	}
-}
-
-void pd_get_info(uint32_t *info_data)
-{
-	void *rw_hash = flash_hash_rw();
-
-	/* copy first 20 bytes of RW hash */
-	memcpy(info_data, rw_hash, 5 * sizeof(uint32_t));
-	/* copy other info into data msg */
-#if defined(CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR) && \
-	defined(CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR)
-	info_data[5] = VDO_INFO(CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR,
-				CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR,
-				ver_get_num_commits(system_get_image_copy()),
-				(system_get_image_copy() != EC_IMAGE_RO));
-#else
-	info_data[5] = 0;
-#endif
-}
-
-int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
-{
-	static int flash_offset;
-	int rsize = 1; /* default is just VDM header returned */
-
-	switch (PD_VDO_CMD(payload[0])) {
-	case VDO_CMD_VERSION:
-		memcpy(payload + 1, &current_image_data.version, 24);
-		rsize = 7;
-		break;
-	case VDO_CMD_REBOOT:
-		/* ensure the power supply is in a safe state */
-		pd_power_supply_reset(0);
-		system_reset(0);
-		break;
-	case VDO_CMD_READ_INFO:
-		/* copy info into response */
-		pd_get_info(payload + 1);
-		rsize = 7;
-		break;
-	case VDO_CMD_FLASH_ERASE:
-		/* do not kill the code under our feet */
-		if (system_get_image_copy() != EC_IMAGE_RO)
-			break;
-		pd_log_event(PD_EVENT_ACC_RW_ERASE, 0, 0, NULL);
-		flash_offset =
-			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
-		crec_flash_physical_erase(CONFIG_EC_WRITABLE_STORAGE_OFF +
-					  CONFIG_RW_STORAGE_OFF,
-					  CONFIG_RW_SIZE);
-		rw_flash_changed = 1;
-		break;
-	case VDO_CMD_FLASH_WRITE:
-		/* do not kill the code under our feet */
-		if ((system_get_image_copy() != EC_IMAGE_RO) ||
-		    (flash_offset <
-		     CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF))
-			break;
-		crec_flash_physical_write(flash_offset, 4 * (cnt - 1),
-				     (const char *)(payload + 1));
-		flash_offset += 4 * (cnt - 1);
-		rw_flash_changed = 1;
-		break;
-	case VDO_CMD_ERASE_SIG:
-		/* this is not touching the code area */
-		{
-			uint32_t zero = 0;
-			int offset;
-			/* zeroes the area containing the RSA signature */
-			for (offset = FW_RW_END - RSANUMBYTES;
-			     offset < FW_RW_END; offset += 4)
-				crec_flash_physical_write(offset, 4,
-						     (const char *)&zero);
-		}
-		break;
-	default:
-		/* Unknown : do not answer */
-		return 0;
-	}
-	return rsize;
-}
diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c
deleted file mode 100644
index abf75e8004..0000000000
--- a/common/usb_pd_protocol.c
+++ /dev/null
@@ -1,5449 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "battery.h"
-#include "battery_smart.h"
-#include "board.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "printf.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_flags.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_tcpc.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-#include "vboot.h"
-
-/* Flags to clear on a disconnect */
-#define PD_FLAGS_RESET_ON_DISCONNECT_MASK (PD_FLAGS_PARTNER_DR_POWER | \
-					   PD_FLAGS_PARTNER_DR_DATA | \
-					   PD_FLAGS_CHECK_IDENTITY | \
-					   PD_FLAGS_SNK_CAP_RECVD | \
-					   PD_FLAGS_TCPC_DRP_TOGGLE | \
-					   PD_FLAGS_EXPLICIT_CONTRACT | \
-					   PD_FLAGS_PREVIOUS_PD_CONN | \
-					   PD_FLAGS_CHECK_PR_ROLE | \
-					   PD_FLAGS_CHECK_DR_ROLE | \
-					   PD_FLAGS_PARTNER_UNCONSTR | \
-					   PD_FLAGS_VCONN_ON | \
-					   PD_FLAGS_TRY_SRC | \
-					   PD_FLAGS_PARTNER_USB_COMM | \
-					   PD_FLAGS_UPDATE_SRC_CAPS | \
-					   PD_FLAGS_TS_DTS_PARTNER | \
-					   PD_FLAGS_SNK_WAITING_BATT | \
-					   PD_FLAGS_CHECK_VCONN_STATE)
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static int tcpc_prints(const char *string, int port)
-{
-	return CPRINTS("TCPC p%d %s", port, string);
-}
-
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= EC_USB_PD_MAX_PORTS);
-
-/*
- * Debug log level - higher number == more log
- *   Level 0: Log state transitions
- *   Level 1: Level 0, plus state name
- *   Level 2: Level 1, plus packet info
- *   Level 3: Level 2, plus ping packet and packet dump on error
- *
- * Note that higher log level causes timing changes and thus may affect
- * performance.
- *
- * Can be limited to constant debug_level by CONFIG_USB_PD_DEBUG_LEVEL
- */
-#ifdef CONFIG_USB_PD_DEBUG_LEVEL
-static const int debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
-#else
-static int debug_level;
-#endif
-
-/*
- * PD communication enabled flag. When false, PD state machine still
- * detects source/sink connection and disconnection, and will still
- * provide VBUS, but never sends any PD communication.
- */
-static uint8_t pd_comm_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#define tcpc_prints(string, port)
-static const int debug_level;
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-#define DUAL_ROLE_IF_ELSE(port, sink_clause, src_clause) \
-	(pd[port].power_role == PD_ROLE_SINK ? (sink_clause) : (src_clause))
-#else
-#define DUAL_ROLE_IF_ELSE(port, sink_clause, src_clause) (src_clause)
-#endif
-
-#define READY_RETURN_STATE(port) DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, \
-							 PD_STATE_SRC_READY)
-
-/* Type C supply voltage (mV) */
-#define TYPE_C_VOLTAGE	5000 /* mV */
-
-/* PD counter definitions */
-#define PD_MESSAGE_ID_COUNT 7
-#define PD_HARD_RESET_COUNT 2
-#define PD_CAPS_COUNT 50
-#define PD_SNK_CAP_RETRIES 3
-
-/*
- * The time that we allow the port partner to send any messages after an
- * explicit contract is established.  200ms was chosen somewhat arbitrarily as
- * it should be long enough for sources to decide to send a message if they were
- * going to, but not so long that a "low power charger connected" notification
- * would be shown in the chrome OS UI.
- */
-#define SNK_READY_HOLD_OFF_US (200 * MSEC)
-/*
- * For the same purpose as SNK_READY_HOLD_OFF_US, but this delay can be longer
- * since the concern over "low power charger" is not relevant when connected as
- * a source and the additional delay avoids a race condition where the partner
- * port sends a power role swap request close to when the VDM discover identity
- * message gets sent.
- */
-#define SRC_READY_HOLD_OFF_US (400 * MSEC)
-
-enum ams_seq {
-	AMS_START,
-	AMS_RESPONSE,
-};
-
-enum vdm_states {
-	VDM_STATE_ERR_BUSY = -3,
-	VDM_STATE_ERR_SEND = -2,
-	VDM_STATE_ERR_TMOUT = -1,
-	VDM_STATE_DONE = 0,
-	/* Anything >0 represents an active state */
-	VDM_STATE_READY = 1,
-	VDM_STATE_BUSY = 2,
-	VDM_STATE_WAIT_RSP_BUSY = 3,
-};
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-/* Port dual-role state */
-enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
-
-/* Enable variable for Try.SRC states */
-static bool pd_try_src_enable;
-#endif
-
-#ifdef CONFIG_USB_PD_REV30
-/*
- * The spec. revision is the argument for this macro.
- *  Rev 0 (PD 1.0) - return PD_CTRL_REJECT
- *  Rev 1 (PD 2.0) - return PD_CTRL_REJECT
- *  Rev 2 (PD 3.0) - return PD_CTRL_NOT_SUPPORTED
- *
- * Note: this should only be used in locations where responding on a lower
- * revision with a Reject is valid (ex. a source refusing a PR_Swap).  For
- * other uses of Not_Supported, use PD_CTRL_NOT_SUPPORTED directly.
- */
-#define NOT_SUPPORTED(r) (r < 2 ? PD_CTRL_REJECT : PD_CTRL_NOT_SUPPORTED)
-#else
-#define NOT_SUPPORTED(r) PD_CTRL_REJECT
-#endif
-
-#ifdef CONFIG_USB_PD_REV30
-/*
- * The spec. revision is used to index into this array.
- *  Rev 0 (VDO 1.0) - return VDM_VER10
- *  Rev 1 (VDO 1.0) - return VDM_VER10
- *  Rev 2 (VDO 2.0) - return VDM_VER20
- */
-static const uint8_t vdo_ver[] = {
-	VDM_VER10, VDM_VER10, VDM_VER20};
-#define VDO_VER(v) vdo_ver[v]
-#else
-#define VDO_VER(v) VDM_VER10
-#endif
-
-static struct pd_protocol {
-	/* current port power role (SOURCE or SINK) */
-	enum pd_power_role power_role;
-	/* current port data role (DFP or UFP) */
-	enum pd_data_role data_role;
-	/* 3-bit rolling message ID counter */
-	uint8_t msg_id;
-	/* port polarity */
-	enum tcpc_cc_polarity polarity;
-	/* PD state for port */
-	enum pd_states task_state;
-	/* PD state when we run state handler the last time */
-	enum pd_states last_state;
-	/* bool: request state change to SUSPENDED */
-	uint8_t req_suspend_state;
-	/* The state to go to after timeout */
-	enum pd_states timeout_state;
-	/* port flags, see PD_FLAGS_* */
-	uint32_t flags;
-	/* Timeout for the current state. Set to 0 for no timeout. */
-	uint64_t timeout;
-	/* Time for source recovery after hard reset */
-	uint64_t src_recover;
-	/* Time for CC debounce end */
-	uint64_t cc_debounce;
-	/* The cc state */
-	enum pd_cc_states cc_state;
-	/* status of last transmit */
-	uint8_t tx_status;
-
-	/* Last received */
-	uint8_t last_msg_id;
-
-	/* last requested voltage PDO index */
-	int requested_idx;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/* Current limit / voltage based on the last request message */
-	uint32_t curr_limit;
-	uint32_t supply_voltage;
-	/* Signal charging update that affects the port */
-	int new_power_request;
-	/* Store previously requested voltage request */
-	int prev_request_mv;
-	/* Time for Try.SRC states */
-	uint64_t try_src_marker;
-	uint64_t try_timeout;
-#endif
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/* Time to enter low power mode */
-	uint64_t low_power_time;
-	/* Time to debounce exit low power mode */
-	uint64_t low_power_exit_time;
-	/* Tasks to notify after TCPC has been reset */
-	int tasks_waiting_on_reset;
-	/* Tasks preventing TCPC from entering low power mode */
-	int tasks_preventing_lpm;
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	/*
-	 * Timer for handling TOGGLE_OFF/FORCE_SINK mode when auto-toggle
-	 * enabled. See drp_auto_toggle_next_state() for details.
-	 */
-	uint64_t drp_sink_time;
-#endif
-
-	/*
-	 * Time to ignore Vbus absence due to external IC debounce detection
-	 * logic immediately after a power role swap.
-	 */
-	uint64_t vbus_debounce_time;
-
-	/* PD state for Vendor Defined Messages */
-	enum vdm_states vdm_state;
-	/* Timeout for the current vdm state.  Set to 0 for no timeout. */
-	timestamp_t vdm_timeout;
-	/* next Vendor Defined Message to send */
-	uint32_t vdo_data[VDO_MAX_SIZE];
-	/* type of transmit message (SOP/SOP'/SOP'') */
-	enum tcpci_msg_type xmit_type;
-	uint8_t vdo_count;
-	/* VDO to retry if UFP responder replied busy. */
-	uint32_t vdo_retry;
-
-	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
-	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
-	enum ec_image current_image;
-#ifdef CONFIG_USB_PD_REV30
-	/* protocol revision */
-	uint8_t rev;
-#endif
-	/*
-	 * Some port partners are really chatty after an explicit contract is
-	 * established.  Therefore, we allow this time for the port partner to
-	 * send any messages in order to avoid a collision of sending messages
-	 * of our own.
-	 */
-	uint64_t ready_state_holdoff_timer;
-	/*
-	 * PD 2.0 spec, section 6.5.11.1
-	 * When we can give up on a HARD_RESET transmission.
-	 */
-	uint64_t hard_reset_complete_timer;
-} pd[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#ifdef CONFIG_USB_PD_TCPMV1_DEBUG
-static const char * const pd_state_names[] = {
-	"DISABLED", "SUSPENDED",
-	"SNK_DISCONNECTED", "SNK_DISCONNECTED_DEBOUNCE",
-	"SNK_HARD_RESET_RECOVER",
-	"SNK_DISCOVERY", "SNK_REQUESTED", "SNK_TRANSITION", "SNK_READY",
-	"SNK_SWAP_INIT", "SNK_SWAP_SNK_DISABLE",
-	"SNK_SWAP_SRC_DISABLE", "SNK_SWAP_STANDBY", "SNK_SWAP_COMPLETE",
-	"SRC_DISCONNECTED", "SRC_DISCONNECTED_DEBOUNCE",
-	"SRC_HARD_RESET_RECOVER", "SRC_STARTUP",
-	"SRC_DISCOVERY", "SRC_NEGOCIATE", "SRC_ACCEPTED", "SRC_POWERED",
-	"SRC_TRANSITION", "SRC_READY", "SRC_GET_SNK_CAP", "DR_SWAP",
-	"SRC_SWAP_INIT", "SRC_SWAP_SNK_DISABLE", "SRC_SWAP_SRC_DISABLE",
-	"SRC_SWAP_STANDBY",
-	"VCONN_SWAP_SEND", "VCONN_SWAP_INIT", "VCONN_SWAP_READY",
-	"SOFT_RESET", "HARD_RESET_SEND", "HARD_RESET_EXECUTE", "BIST_RX",
-	"BIST_TX",
-	"DRP_AUTO_TOGGLE",
-	"ENTER_USB",
-};
-BUILD_ASSERT(ARRAY_SIZE(pd_state_names) == PD_STATE_COUNT);
-#endif
-
-int pd_comm_is_enabled(int port)
-{
-#ifdef CONFIG_COMMON_RUNTIME
-	return pd_comm_enabled[port];
-#else
-	return 1;
-#endif
-}
-
-bool pd_alt_mode_capable(int port)
-{
-	/*
-	 * PD is alternate mode capable only if PD communication is enabled and
-	 * the port is not suspended.
-	 */
-	return pd_comm_is_enabled(port) &&
-		!(pd[port].task_state == PD_STATE_SUSPENDED);
-}
-
-static inline void set_state_timeout(int port,
-				     uint64_t timeout,
-				     enum pd_states timeout_state)
-{
-	pd[port].timeout = timeout;
-	pd[port].timeout_state = timeout_state;
-}
-
-int pd_get_rev(int port, enum tcpci_msg_type type)
-{
-#ifdef CONFIG_USB_PD_REV30
-	/* TCPMv1 Only stores PD revision for SOP and SOP' types */
-	ASSERT(type < NUM_SOP_STAR_TYPES - 1);
-
-	if (type == TCPCI_MSG_SOP_PRIME)
-		return get_usb_pd_cable_revision(port);
-
-	return pd[port].rev;
-#else
-	return PD_REV20;
-#endif
-}
-
-int pd_get_vdo_ver(int port, enum tcpci_msg_type type)
-{
-#ifdef CONFIG_USB_PD_REV30
-	if (type == TCPCI_MSG_SOP_PRIME)
-		return vdo_ver[get_usb_pd_cable_revision(port)];
-
-	return vdo_ver[pd[port].rev];
-#else
-	return VDM_VER10;
-#endif
-}
-
-/* Return flag for pd state is connected */
-int pd_is_connected(int port)
-{
-	if (pd[port].task_state == PD_STATE_DISABLED)
-		return 0;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	if (pd[port].task_state == PD_STATE_DRP_AUTO_TOGGLE)
-		return 0;
-#endif
-
-	return DUAL_ROLE_IF_ELSE(port,
-		/* sink */
-		pd[port].task_state != PD_STATE_SNK_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE,
-		/* source */
-		pd[port].task_state != PD_STATE_SRC_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
-}
-
-/* Return true if partner port is known to be PD capable. */
-bool pd_capable(int port)
-{
-	return !!(pd[port].flags & PD_FLAGS_PREVIOUS_PD_CONN);
-}
-
-/*
- * For TCPMv1, this routine always returns false so that the USB3 signals
- * are connected without delay when the initial connection is UFP.
- */
-bool pd_waiting_on_partner_src_caps(int port)
-{
-	return false;
-}
-
-/*
- * Return true if partner port is capable of communication over USB data
- * lines.
- */
-bool pd_get_partner_usb_comm_capable(int port)
-{
-	return !!(pd[port].flags & PD_FLAGS_PARTNER_USB_COMM);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-void pd_vbus_low(int port)
-{
-	pd[port].flags &= ~PD_FLAGS_VBUS_NEVER_LOW;
-}
-#endif
-
-
-#ifdef CONFIG_USBC_VCONN
-static void set_vconn(int port, int enable)
-{
-	/*
-	 * Disable PPC Vconn first then TCPC in case the voltage feeds back
-	 * to TCPC and damages.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && !enable)
-		ppc_set_vconn(port, 0);
-
-	/*
-	 * Some TCPCs/PPC combinations can trigger OVP if the TCPC doesn't
-	 * source VCONN. This happens if the TCPC will trip OVP with 5V, and the
-	 * PPC doesn't isolate the TCPC from VCONN when sourcing. But, some PPCs
-	 * which do isolate the TCPC can't handle 5V on its host-side CC pins,
-	 * so the TCPC shouldn't source VCONN in those cases.
-	 *
-	 * In the first case, both TCPC and PPC will potentially source Vconn,
-	 * but that should be okay since Vconn has "make before break"
-	 * electrical requirements when swapping anyway.
-	 *
-	 * See b/72961003 and b/180973460
-	 */
-	tcpm_set_vconn(port, enable);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && enable)
-		ppc_set_vconn(port, 1);
-}
-#endif /* defined(CONFIG_USBC_VCONN) */
-
-#ifdef CONFIG_USB_PD_REV30
-/* Note: rp should be set to either SINK_TX_OK or SINK_TX_NG */
-static void sink_can_xmit(int port, int rp)
-{
-	tcpm_select_rp_value(port, rp);
-	tcpm_set_cc(port, TYPEC_CC_RP);
-
-	/* We must wait tSinkTx before sending a message */
-	if (rp == SINK_TX_NG)
-		usleep(PD_T_SINK_TX);
-}
-#endif
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-
-/* 10 ms is enough time for any TCPC transaction to complete. */
-#define PD_LPM_DEBOUNCE_US (10 * MSEC)
-/* 25 ms on LPM exit to ensure TCPC is settled */
-#define PD_LPM_EXIT_DEBOUNCE_US (25 * MSEC)
-
-/* This is only called from the PD tasks that owns the port. */
-static void handle_device_access(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	pd[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
-	if (pd[port].flags & PD_FLAGS_LPM_ENGAGED) {
-		tcpc_prints("Exit Low Power Mode", port);
-		pd[port].flags &= ~(PD_FLAGS_LPM_ENGAGED |
-				    PD_FLAGS_LPM_REQUESTED);
-		pd[port].flags |= PD_FLAGS_LPM_EXIT;
-
-		pd[port].low_power_exit_time = get_time().val
-			+ PD_LPM_EXIT_DEBOUNCE_US;
-		/*
-		 * Wake to ensure we make another pass through the main task
-		 * loop after clearing the flags.
-		 */
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-static int pd_device_in_low_power(int port)
-{
-	/*
-	 * If we are actively waking the device up in the PD task, do not
-	 * let TCPC operation wait or retry because we are in low power mode.
-	 */
-	if (port == TASK_ID_TO_PD_PORT(task_get_current()) &&
-	    (pd[port].flags & PD_FLAGS_LPM_TRANSITION))
-		return 0;
-
-	return pd[port].flags & PD_FLAGS_LPM_ENGAGED;
-}
-
-static int reset_device_and_notify(int port)
-{
-	int rv;
-	int task, waiting_tasks;
-
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	pd[port].flags |= PD_FLAGS_LPM_TRANSITION;
-	rv = tcpm_init(port);
-	pd[port].flags &= ~PD_FLAGS_LPM_TRANSITION;
-
-	if (rv == EC_SUCCESS)
-		tcpc_prints("init ready", port);
-	else
-		tcpc_prints("init failed!", port);
-
-	/*
-	 * Before getting the other tasks that are waiting, clear the reset
-	 * event from this PD task to prevent multiple reset/init events
-	 * occurring.
-	 *
-	 * The double reset event happens when the higher priority PD interrupt
-	 * task gets an interrupt during the above tcpm_init function. When that
-	 * occurs, the higher priority task waits correctly for us to finish
-	 * waking the TCPC, but it has also set PD_EVENT_TCPC_RESET again, which
-	 * would result in a second, unnecessary init.
-	 */
-	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-			  PD_EVENT_TCPC_RESET);
-
-	waiting_tasks = atomic_clear(&pd[port].tasks_waiting_on_reset);
-
-	/*
-	 * Now that we are done waking up the device, handle device access
-	 * manually because we ignored it while waking up device.
-	 */
-	handle_device_access(port);
-
-	/* Clear SW LPM state; the state machine will set it again if needed */
-	pd[port].flags &= ~PD_FLAGS_LPM_REQUESTED;
-
-	/* Wake up all waiting tasks. */
-	while (waiting_tasks) {
-		task = __fls(waiting_tasks);
-		waiting_tasks &= ~BIT(task);
-		task_set_event(task, TASK_EVENT_PD_AWAKE);
-	}
-
-	return rv;
-}
-
-static void pd_wait_for_wakeup(int port)
-{
-	if (port == TASK_ID_TO_PD_PORT(task_get_current())) {
-		/* If we are in the PD task, we can directly reset */
-		reset_device_and_notify(port);
-	} else {
-		/* Otherwise, we need to wait for the TCPC reset to complete */
-		atomic_or(&pd[port].tasks_waiting_on_reset,
-			  1 << task_get_current());
-		/*
-		 * NOTE: We could be sending the PD task the reset event while
-		 * it is already processing the reset event. If that occurs,
-		 * then we will reset the TCPC multiple times, which is
-		 * undesirable but most likely benign. Empirically, this doesn't
-		 * happen much, but it if starts occurring, we can add a guard
-		 * to prevent/reduce it.
-		 */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
-		task_wait_event_mask(TASK_EVENT_PD_AWAKE, -1);
-	}
-}
-
-void pd_wait_exit_low_power(int port)
-{
-	if (pd_device_in_low_power(port))
-		pd_wait_for_wakeup(port);
-}
-
-/*
- * This can be called from any task. If we are in the PD task, we can handle
- * immediately. Otherwise, we need to notify the PD task via event.
- */
-void pd_device_accessed(int port)
-{
-	if (port == TASK_ID_TO_PD_PORT(task_get_current())) {
-		/* Ignore any access to device while it is waking up */
-		if (pd[port].flags & PD_FLAGS_LPM_TRANSITION)
-			return;
-
-		handle_device_access(port);
-	} else {
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_DEVICE_ACCESSED);
-	}
-}
-
-void pd_prevent_low_power_mode(int port, int prevent)
-{
-	const int current_task_mask = (1 << task_get_current());
-
-	if (prevent)
-		atomic_or(&pd[port].tasks_preventing_lpm, current_task_mask);
-	else
-		atomic_clear_bits(&pd[port].tasks_preventing_lpm,
-				  current_task_mask);
-}
-
-/* This is only called from the PD tasks that owns the port. */
-static void exit_low_power_mode(int port)
-{
-	if (pd[port].flags & PD_FLAGS_LPM_ENGAGED)
-		reset_device_and_notify(port);
-	else
-		pd[port].flags &= ~PD_FLAGS_LPM_REQUESTED;
-}
-
-#else /* !CONFIG_USB_PD_TCPC_LOW_POWER */
-
-/* We don't need to notify anyone if low power mode isn't involved. */
-static int reset_device_and_notify(int port)
-{
-	const int rv = tcpm_init(port);
-
-	if (rv == EC_SUCCESS)
-		tcpc_prints("init ready", port);
-	else
-		tcpc_prints("init failed!", port);
-
-	return rv;
-}
-
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-/**
- * Invalidate last message received at the port when the port gets disconnected
- * or reset(soft/hard). This is used to identify and handle the duplicate
- * messages.
- *
- * @param port USB PD TCPC port number
- */
-static void invalidate_last_message_id(int port)
-{
-	pd[port].last_msg_id = INVALID_MSG_ID_COUNTER;
-}
-
-static bool consume_sop_repeat_message(int port, uint8_t msg_id)
-{
-	if (pd[port].last_msg_id != msg_id) {
-		pd[port].last_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d Repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-/**
- * Identify and drop any duplicate messages received at the port.
- *
- * @param port USB PD TCPC port number
- * @param msg_header Message Header containing the RX message ID
- * @return True if the received message is a duplicate one, False otherwise.
- *
- * From USB PD version 1.3 section 6.7.1, the port which communicates
- * using SOP* Packets Shall maintain copies of the last MessageID for
- * each type of SOP* it uses.
- */
-static bool consume_repeat_message(int port, uint32_t msg_header)
-{
-	uint8_t msg_id = PD_HEADER_ID(msg_header);
-	enum tcpci_msg_type sop = PD_HEADER_GET_SOP(msg_header);
-
-	/* If repeat message ignore, except softreset control request. */
-	if (PD_HEADER_TYPE(msg_header) == PD_CTRL_SOFT_RESET &&
-	    PD_HEADER_CNT(msg_header) == 0) {
-		return false;
-	} else if (sop == TCPCI_MSG_SOP_PRIME) {
-		return consume_sop_prime_repeat_msg(port, msg_id);
-	} else if (sop == TCPCI_MSG_SOP_PRIME_PRIME) {
-		return consume_sop_prime_prime_repeat_msg(port, msg_id);
-	} else {
-		return consume_sop_repeat_message(port, msg_id);
-	}
-
-}
-
-/**
- * Returns true if the port is currently in the try src state.
- */
-static inline int is_try_src(int port)
-{
-	return pd[port].flags & PD_FLAGS_TRY_SRC;
-}
-
-static inline void set_state(int port, enum pd_states next_state)
-{
-	enum pd_states last_state = pd[port].task_state;
-#if defined(CONFIG_LOW_POWER_IDLE) && !defined(CONFIG_USB_PD_TCPC_ON_CHIP)
-	int i;
-#endif
-	int not_auto_toggling = 1;
-
-	set_state_timeout(port, 0, 0);
-	pd[port].task_state = next_state;
-
-	if (last_state == next_state)
-		return;
-
-#if defined(CONFIG_USBC_PPC) && defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)
-	/* If we're entering DRP_AUTO_TOGGLE, there is no sink connected. */
-	if (next_state == PD_STATE_DRP_AUTO_TOGGLE) {
-		ppc_dev_is_connected(port, PPC_DEV_DISCONNECTED);
-		/* Disable Auto Discharge Disconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 0);
-
-		if (IS_ENABLED(CONFIG_USBC_OCP)) {
-			usbc_ocp_snk_is_connected(port, false);
-			/*
-			 * Clear the overcurrent event counter
-			 * since we've detected a disconnect.
-			 */
-			usbc_ocp_clear_event_counter(port);
-		}
-	}
-#endif /* CONFIG_USBC_PPC &&  CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	if (last_state != PD_STATE_DRP_AUTO_TOGGLE)
-		/* Clear flag to allow DRP auto toggle when possible */
-		pd[port].flags &= ~PD_FLAGS_TCPC_DRP_TOGGLE;
-	else
-		/* This is an auto toggle instead of disconnect */
-		not_auto_toggling = 0;
-#endif
-
-	/* Ignore dual-role toggling between sink and source */
-	if ((last_state == PD_STATE_SNK_DISCONNECTED &&
-	     next_state == PD_STATE_SRC_DISCONNECTED) ||
-	    (last_state == PD_STATE_SRC_DISCONNECTED &&
-	     next_state == PD_STATE_SNK_DISCONNECTED))
-		return;
-
-	if (next_state == PD_STATE_SRC_DISCONNECTED ||
-	    next_state == PD_STATE_SNK_DISCONNECTED) {
-#ifdef CONFIG_USBC_PPC
-		enum tcpc_cc_voltage_status cc1, cc2;
-
-		tcpm_get_cc(port, &cc1, &cc2);
-		/*
-		 * Neither a debug accessory nor UFP attached.
-		 * Tell the PPC module that there is no device connected.
-		 */
-		if (!cc_is_at_least_one_rd(cc1, cc2)) {
-			ppc_dev_is_connected(port, PPC_DEV_DISCONNECTED);
-
-			if (IS_ENABLED(CONFIG_USBC_OCP)) {
-				usbc_ocp_snk_is_connected(port, false);
-				/*
-				 * Clear the overcurrent event counter
-				 * since we've detected a disconnect.
-				 */
-				usbc_ocp_clear_event_counter(port);
-			}
-		}
-#endif /* CONFIG_USBC_PPC */
-
-		/* Clear the holdoff timer since the port is disconnected. */
-		pd[port].ready_state_holdoff_timer = 0;
-
-		/*
-		 * We should not clear any flags when transitioning back to the
-		 * disconnected state from the debounce state as the two states
-		 * here are really the same states in the state diagram.
-		 */
-		if (last_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE &&
-		    last_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE) {
-			pd[port].flags &= ~PD_FLAGS_RESET_ON_DISCONNECT_MASK;
-			reset_pd_cable(port);
-		}
-
-		/* Clear the input current limit */
-		pd_set_input_current_limit(port, 0, 0);
-#ifdef CONFIG_CHARGE_MANAGER
-		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
-					CHARGE_CEIL_NONE);
-#endif
-#ifdef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
-		/*
-		 * When data role set events are used to enable BC1.2, then CC
-		 * detach events are used to notify BC1.2 that it can be powered
-		 * down.
-		 */
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_CC_OPEN);
-#endif /* CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER */
-#ifdef CONFIG_USBC_VCONN
-		set_vconn(port, 0);
-#endif /* defined(CONFIG_USBC_VCONN) */
-		pd_update_saved_port_flags(port, PD_BBRMFLG_EXPLICIT_CONTRACT,
-					   0);
-#else /* CONFIG_USB_PD_DUAL_ROLE */
-	if (next_state == PD_STATE_SRC_DISCONNECTED) {
-#ifdef CONFIG_USBC_VCONN
-		set_vconn(port, 0);
-#endif /* CONFIG_USBC_VCONN */
-#endif /* !CONFIG_USB_PD_DUAL_ROLE */
-		/* If we are source, make sure VBUS is off and restore RP */
-		if (pd[port].power_role == PD_ROLE_SOURCE) {
-			/* Restore non-active ports to CONFIG_USB_PD_PULLUP */
-			pd_power_supply_reset(port);
-			tcpm_set_cc(port, TYPEC_CC_RP);
-		}
-#ifdef CONFIG_USB_PD_REV30
-		/* Adjust rev to highest level*/
-		pd[port].rev = PD_REV30;
-#endif
-		pd[port].dev_id = 0;
-#ifdef CONFIG_CHARGE_MANAGER
-		charge_manager_update_dualrole(port, CAP_UNKNOWN);
-#endif
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-		if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0))
-			usb_mux_set_safe_mode(port);
-#endif
-		/*
-		 * Indicate that the port is disconnected by setting role to
-		 * DFP as SoCs have special signals when they are the UFP ports
-		 * (e.g. OTG signals)
-		 */
-		pd_execute_data_swap(port, PD_ROLE_DFP);
-#ifdef CONFIG_USBC_SS_MUX
-		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
-			    pd[port].polarity);
-#endif
-		/* Disable TCPC RX */
-		tcpm_set_rx_enable(port, 0);
-
-		/* Invalidate message IDs. */
-		invalidate_last_message_id(port);
-
-		if (not_auto_toggling)
-			/* Disable Auto Discharge Disconnect */
-			tcpm_enable_auto_discharge_disconnect(port, 0);
-
-		/* detect USB PD cc disconnect */
-		if (IS_ENABLED(CONFIG_COMMON_RUNTIME))
-			hook_notify(HOOK_USB_PD_DISCONNECT);
-	}
-
-#ifdef CONFIG_USB_PD_REV30
-	/* Upon entering SRC_READY, it is safe for the sink to transmit */
-	if (next_state == PD_STATE_SRC_READY) {
-		if (pd[port].rev == PD_REV30 &&
-			pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
-			sink_can_xmit(port, SINK_TX_OK);
-	}
-#endif
-
-#if defined(CONFIG_LOW_POWER_IDLE) && !defined(CONFIG_USB_PD_TCPC_ON_CHIP)
-	/* If a PD device is attached then disable deep sleep */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (pd_capable(i))
-			break;
-	}
-	if (i == board_get_usb_pd_port_count())
-		enable_sleep(SLEEP_MASK_USB_PD);
-	else
-		disable_sleep(SLEEP_MASK_USB_PD);
-#endif
-
-#ifdef CONFIG_USB_PD_TCPMV1_DEBUG
-	if (debug_level > 0)
-		CPRINTF("C%d st%d %s\n", port, next_state,
-					 pd_state_names[next_state]);
-	else
-#endif
-		CPRINTF("C%d st%d\n", port, next_state);
-}
-
-/* increment message ID counter */
-static void inc_id(int port)
-{
-	pd[port].msg_id = (pd[port].msg_id + 1) & PD_MESSAGE_ID_COUNT;
-}
-
-void pd_transmit_complete(int port, int status)
-{
-	if (status == TCPC_TX_COMPLETE_SUCCESS)
-		inc_id(port);
-
-	pd[port].tx_status = status;
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
-}
-
-static int pd_transmit(int port, enum tcpci_msg_type type,
-		       uint16_t header, const uint32_t *data, enum ams_seq ams)
-{
-	int evt;
-	int res;
-#ifdef CONFIG_USB_PD_REV30
-	int sink_ng = 0;
-#endif
-
-	/* If comms are disabled, do not transmit, return error */
-	if (!pd_comm_is_enabled(port))
-		return -1;
-
-	 /* Don't try to transmit anything until we have processed
-	  * all RX messages.
-	  */
-	if (tcpm_has_pending_message(port))
-		return -1;
-
-#ifdef CONFIG_USB_PD_REV30
-	/* Source-coordinated collision avoidance */
-	/*
-	 * USB PD Rev 3.0, Version 2.0: Section 2.7.3.2
-	 * Collision Avoidance - Protocol Layer
-	 *
-	 * In order to avoid message collisions due to asynchronous Messaging
-	 * sent from the Sink, the Source sets Rp to SinkTxOk (3A) to indicate
-	 * to the Sink that it is ok to initiate an AMS. When the Source wishes
-	 * to initiate an AMS, it sets Rp to SinkTxNG (1.5A).
-	 * When the Sink detects that Rp is set to SinkTxOk, it May initiate an
-	 * AMS. When the Sink detects that Rp is set to SinkTxNG it Shall Not
-	 * initiate an AMS and Shall only send Messages that are part of an AMS
-	 * the Source has initiated.
-	 * Note that this restriction applies to SOP* AMS’s i.e. for both Port
-	 * to Port and Port to Cable Plug communications.
-	 *
-	 * This starts after an Explicit Contract is in place (see section 2.5.2
-	 * SOP* Collision Avoidance).
-	 *
-	 * Note: a Sink can still send Hard Reset signaling at any time.
-	 */
-	if ((pd[port].rev == PD_REV30) && ams == AMS_START &&
-		(pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) {
-		if (pd[port].power_role == PD_ROLE_SOURCE) {
-			/*
-			 * Inform Sink that it can't transmit. If a sink
-			 * transmission is in progress and a collision occurs,
-			 * a reset is generated. This should be rare because
-			 * all extended messages are chunked. This effectively
-			 * defaults to PD REV 2.0 collision avoidance.
-			 */
-			sink_can_xmit(port, SINK_TX_NG);
-			sink_ng = 1;
-		} else if (type != TCPCI_MSG_TX_HARD_RESET) {
-			enum tcpc_cc_voltage_status cc1, cc2;
-
-			tcpm_get_cc(port, &cc1, &cc2);
-			if (cc1 == TYPEC_CC_VOLT_RP_1_5 ||
-				cc2 == TYPEC_CC_VOLT_RP_1_5) {
-				/* Sink can't transmit now. */
-				/* Return failure, pd_task can retry later */
-				return -1;
-			}
-		}
-	}
-#endif
-	tcpm_transmit(port, type, header, data);
-
-	/* Wait until TX is complete */
-	evt = task_wait_event_mask(PD_EVENT_TX, PD_T_TCPC_TX_TIMEOUT);
-
-	if (evt & TASK_EVENT_TIMER)
-		return -1;
-
-	/* TODO: give different error condition for failed vs discarded */
-	res = pd[port].tx_status == TCPC_TX_COMPLETE_SUCCESS ? 1 : -1;
-
-#ifdef CONFIG_USB_PD_REV30
-	/* If the AMS transaction failed to start, reset CC to OK */
-	if (res < 0 && sink_ng)
-		sink_can_xmit(port, SINK_TX_OK);
-#endif
-	return res;
-}
-
-static void pd_update_roles(int port)
-{
-	/* Notify TCPC of role update */
-	tcpm_set_msg_header(port, pd[port].power_role, pd[port].data_role);
-}
-
-static int send_control(int port, int type)
-{
-	int bit_len;
-	uint16_t header = PD_HEADER(type, pd[port].power_role,
-				pd[port].data_role, pd[port].msg_id, 0,
-				pd_get_rev(port, TCPCI_MSG_SOP), 0);
-	/*
-	 * For PD 3.0, collision avoidance logic needs to know if this message
-	 * will begin a new Atomic Message Sequence (AMS)
-	 */
-	enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK)
-			    ? AMS_START : AMS_RESPONSE;
-
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, NULL, ams);
-	if (debug_level >= 2)
-		CPRINTF("C%d CTRL[%d]>%d\n", port, type, bit_len);
-
-	return bit_len;
-}
-
-/*
- * Note: Source capabilities may either be in an existing AMS (ex. as a
- * response to Get_Source_Cap), or the beginning of an AMS for a power
- * negotiation.
- */
-static int send_source_cap(int port, enum ams_seq ams)
-{
-	int bit_len;
-#if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
-	const uint32_t *src_pdo;
-	const int src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
-#else
-	const uint32_t *src_pdo = pd_src_pdo;
-	const int src_pdo_cnt = pd_src_pdo_cnt;
-#endif
-	uint16_t header;
-
-	if (src_pdo_cnt == 0)
-		/* No source capabilities defined, sink only */
-		header = PD_HEADER(PD_CTRL_REJECT, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 0,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-	else
-		header = PD_HEADER(PD_DATA_SOURCE_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, src_pdo_cnt,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, src_pdo, ams);
-	if (debug_level >= 2)
-		CPRINTF("C%d srcCAP>%d\n", port, bit_len);
-
-	return bit_len;
-}
-
-#ifdef CONFIG_USB_PD_REV30
-static int send_battery_cap(int port, uint32_t *payload)
-{
-	int bit_len;
-	uint16_t msg[6] = {0, 0, 0, 0, 0, 0};
-	uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
-				    3, /* Number of Data Objects */
-				    pd[port].rev,
-				    1  /* This is an exteded message */
-				   );
-
-	/* Set extended header */
-	msg[0] = PD_EXT_HEADER(0, /* Chunk Number */
-			       0, /* Request Chunk */
-			       9  /* Data Size in bytes */
-			      );
-	/* Set VID */
-	msg[1] = USB_VID_GOOGLE;
-
-	/* Set PID */
-	msg[2] = CONFIG_USB_PID;
-
-	if (battery_is_present()) {
-		/*
-		 * We only have one fixed battery,
-		 * so make sure batt cap ref is 0.
-		 */
-		if (BATT_CAP_REF(payload[0]) != 0) {
-			/* Invalid battery reference */
-			msg[5] = 1;
-		} else {
-			uint32_t v;
-			uint32_t c;
-
-			/*
-			 * The Battery Design Capacity field shall return the
-			 * Battery’s design capacity in tenths of Wh. If the
-			 * Battery is Hot Swappable and is not present, the
-			 * Battery Design Capacity field shall be set to 0. If
-			 * the Battery is unable to report its Design Capacity,
-			 * it shall return 0xFFFF
-			 */
-			msg[3] = 0xffff;
-
-			/*
-			 * The Battery Last Full Charge Capacity field shall
-			 * return the Battery’s last full charge capacity in
-			 * tenths of Wh. If the Battery is Hot Swappable and
-			 * is not present, the Battery Last Full Charge Capacity
-			 * field shall be set to 0. If the Battery is unable to
-			 * report its Design Capacity, the Battery Last Full
-			 * Charge Capacity field shall be set to 0xFFFF.
-			 */
-			msg[4] = 0xffff;
-
-			if (battery_design_voltage(&v) == 0) {
-				if (battery_design_capacity(&c) == 0) {
-					/*
-					 * Wh = (c * v) / 1000000
-					 * 10th of a Wh = Wh * 10
-					 */
-					msg[3] = DIV_ROUND_NEAREST((c * v),
-								100000);
-				}
-
-				if (battery_full_charge_capacity(&c) == 0) {
-					/*
-					 * Wh = (c * v) / 1000000
-					 * 10th of a Wh = Wh * 10
-					 */
-					msg[4] = DIV_ROUND_NEAREST((c * v),
-								100000);
-				}
-			}
-		}
-	}
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, (uint32_t *)msg,
-			      AMS_RESPONSE);
-	if (debug_level >= 2)
-		CPRINTF("C%d batCap>%d\n", port, bit_len);
-	return bit_len;
-}
-
-static int send_battery_status(int port,  uint32_t *payload)
-{
-	int bit_len;
-	uint32_t msg = 0;
-	uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
-				    1, /* Number of Data Objects */
-				    pd[port].rev,
-				    0 /* This is NOT an extended message */
-				  );
-
-	if (battery_is_present()) {
-		/*
-		 * We only have one fixed battery,
-		 * so make sure batt cap ref is 0.
-		 */
-		if (BATT_CAP_REF(payload[0]) != 0) {
-			/* Invalid battery reference */
-			msg |= BSDO_INVALID;
-		} else {
-			uint32_t v;
-			uint32_t c;
-
-			if (battery_design_voltage(&v) != 0 ||
-					battery_remaining_capacity(&c) != 0) {
-				msg |= BSDO_CAP(BSDO_CAP_UNKNOWN);
-			} else {
-				/*
-				 * Wh = (c * v) / 1000000
-				 * 10th of a Wh = Wh * 10
-				 */
-				msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								100000));
-			}
-
-			/* Battery is present */
-			msg |= BSDO_PRESENT;
-
-			/*
-			 * For drivers that are not smart battery compliant,
-			 * battery_status() returns EC_ERROR_UNIMPLEMENTED and
-			 * the battery is assumed to be idle.
-			 */
-			if (battery_status(&c) != 0) {
-				msg |= BSDO_IDLE; /* assume idle */
-			} else {
-				if (c & STATUS_FULLY_CHARGED)
-					/* Fully charged */
-					msg |= BSDO_IDLE;
-				else if (c & STATUS_DISCHARGING)
-					/* Discharging */
-					msg |= BSDO_DISCHARGING;
-				/* else battery is charging.*/
-			}
-		}
-	} else {
-		msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
-	}
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &msg, AMS_RESPONSE);
-	if (debug_level >= 2)
-		CPRINTF("C%d batStat>%d\n", port, bit_len);
-
-	return bit_len;
-}
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-static void send_sink_cap(int port)
-{
-	int bit_len;
-	uint16_t header = PD_HEADER(PD_DATA_SINK_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, pd_snk_pdo_cnt,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, pd_snk_pdo,
-			      AMS_RESPONSE);
-	if (debug_level >= 2)
-		CPRINTF("C%d snkCAP>%d\n", port, bit_len);
-}
-
-static int send_request(int port, uint32_t rdo)
-{
-	int bit_len;
-	uint16_t header = PD_HEADER(PD_DATA_REQUEST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	/* Note: ams will need to be AMS_START if used for PPS keep alive */
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &rdo, AMS_RESPONSE);
-	if (debug_level >= 2)
-		CPRINTF("C%d REQ>%d\n", port, bit_len);
-
-	return bit_len;
-}
-
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-#ifdef CONFIG_COMMON_RUNTIME
-static int send_bist_cmd(int port)
-{
-	/* currently only support sending bist carrier 2 */
-	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
-	int bit_len;
-	uint16_t header = PD_HEADER(PD_DATA_BIST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &bdo, AMS_START);
-	CPRINTF("C%d BIST>%d\n", port, bit_len);
-
-	return bit_len;
-}
-#endif
-
-static void queue_vdm(int port, uint32_t *header, const uint32_t *data,
-			     int data_cnt, enum tcpci_msg_type type)
-{
-	pd[port].vdo_count = data_cnt + 1;
-	pd[port].vdo_data[0] = header[0];
-	pd[port].xmit_type = type;
-	memcpy(&pd[port].vdo_data[1], data,
-		sizeof(uint32_t) * data_cnt);
-	/* Set ready, pd task will actually send */
-	pd[port].vdm_state = VDM_STATE_READY;
-}
-
-static void handle_vdm_request(int port, int cnt, uint32_t *payload,
-				uint32_t head)
-{
-	int rlen = 0;
-	uint32_t *rdata;
-	enum tcpci_msg_type rtype = TCPCI_MSG_SOP;
-
-	if (pd[port].vdm_state == VDM_STATE_BUSY) {
-		/* If UFP responded busy retry after timeout */
-		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_BUSY) {
-			pd[port].vdm_timeout.val = get_time().val +
-				PD_T_VDM_BUSY;
-			pd[port].vdm_state = VDM_STATE_WAIT_RSP_BUSY;
-			pd[port].vdo_retry = (payload[0] & ~VDO_CMDT_MASK) |
-				CMDT_INIT;
-			return;
-		} else {
-			pd[port].vdm_state = VDM_STATE_DONE;
-#ifdef CONFIG_USB_PD_REV30
-			if (pd[port].rev == PD_REV30 &&
-			    pd[port].power_role == PD_ROLE_SOURCE &&
-			    pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
-				sink_can_xmit(port, SINK_TX_OK);
-#endif
-		}
-	}
-
-	if (PD_VDO_SVDM(payload[0]))
-		rlen = pd_svdm(port, cnt, payload, &rdata, head, &rtype);
-	else
-		rlen = pd_custom_vdm(port, cnt, payload, &rdata);
-
-	if (rlen > 0) {
-		queue_vdm(port, rdata, &rdata[1], rlen - 1, rtype);
-		return;
-	}
-
-	if (debug_level >= 2)
-		CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n",
-			port, PD_VDO_VID(payload[0]), payload[0] & 0xFFFF);
-}
-
-bool pd_is_disconnected(int port)
-{
-	return pd[port].task_state == PD_STATE_SRC_DISCONNECTED
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	       || pd[port].task_state == PD_STATE_SNK_DISCONNECTED
-#endif
-		;
-}
-
-static void pd_set_data_role(int port, enum pd_data_role role)
-{
-	pd[port].data_role = role;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	pd_update_saved_port_flags(port, PD_BBRMFLG_DATA_ROLE, role);
-#endif /* defined(CONFIG_USB_PD_DUAL_ROLE) */
-	pd_execute_data_swap(port, role);
-
-	set_usb_mux_with_current_data_role(port);
-	pd_update_roles(port);
-#ifdef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
-	/*
-	 * For BC1.2 detection that is triggered on data role change events
-	 * instead of VBUS changes, need to set an event to wake up the USB_CHG
-	 * task and indicate the current data role.
-	 */
-	if (role == PD_ROLE_UFP)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_DR_UFP);
-	else if (role == PD_ROLE_DFP)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_DR_DFP);
-#endif /* CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER */
-}
-
-#ifdef CONFIG_USBC_VCONN
-static void pd_set_vconn_role(int port, int role)
-{
-	if (role == PD_ROLE_VCONN_ON)
-		pd[port].flags |= PD_FLAGS_VCONN_ON;
-	else
-		pd[port].flags &= ~PD_FLAGS_VCONN_ON;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	pd_update_saved_port_flags(port, PD_BBRMFLG_VCONN_ROLE, role);
-#endif
-}
-#endif /* CONFIG_USBC_VCONN */
-
-void pd_execute_hard_reset(int port)
-{
-	int hard_rst_tx = pd[port].last_state == PD_STATE_HARD_RESET_SEND;
-
-	CPRINTF("C%d HARD RST %cX\n", port, hard_rst_tx ? 'T' : 'R');
-
-	pd[port].msg_id = 0;
-	invalidate_last_message_id(port);
-	tcpm_set_rx_enable(port, 0);
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0))
-		usb_mux_set_safe_mode(port);
-#endif
-
-#ifdef CONFIG_USB_PD_REV30
-	pd[port].rev = PD_REV30;
-#endif
-	/*
-	 * Fake set last state to hard reset to make sure that the next
-	 * state to run knows that we just did a hard reset.
-	 */
-	pd[port].last_state = PD_STATE_HARD_RESET_EXECUTE;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If we are swapping to a source and have changed to Rp, restore back
-	 * to Rd and turn off vbus to match our power_role.
-	 */
-	if (pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
-	    pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE) {
-		tcpm_set_cc(port, TYPEC_CC_RD);
-		pd_power_supply_reset(port);
-	}
-
-	if (pd[port].power_role == PD_ROLE_SINK) {
-		/* Initial data role for sink is UFP */
-		pd_set_data_role(port, PD_ROLE_UFP);
-
-		/* Clear the input current limit */
-		pd_set_input_current_limit(port, 0, 0);
-#ifdef CONFIG_CHARGE_MANAGER
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
-					CHARGE_CEIL_NONE);
-#endif /* CONFIG_CHARGE_MANAGER */
-
-#ifdef CONFIG_USBC_VCONN
-		/*
-		 * Sink must turn off Vconn after a hard reset if it was being
-		 * sourced previously
-		 */
-		if (pd[port].flags & PD_FLAGS_VCONN_ON) {
-			set_vconn(port, 0);
-			pd_set_vconn_role(port, PD_ROLE_VCONN_OFF);
-		}
-#endif
-
-		set_state(port, PD_STATE_SNK_HARD_RESET_RECOVER);
-		return;
-	} else {
-		/* Initial data role for source is DFP */
-		pd_set_data_role(port, PD_ROLE_DFP);
-	}
-
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-	if (!hard_rst_tx)
-		usleep(PD_T_PS_HARD_RESET);
-
-	/* We are a source, cut power */
-	pd_power_supply_reset(port);
-	pd[port].src_recover = get_time().val + PD_T_SRC_RECOVER;
-#ifdef CONFIG_USBC_VCONN
-	set_vconn(port, 0);
-#endif
-	set_state(port, PD_STATE_SRC_HARD_RESET_RECOVER);
-}
-
-static void execute_soft_reset(int port)
-{
-	invalidate_last_message_id(port);
-	set_state(port, DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCOVERY,
-						PD_STATE_SRC_DISCOVERY));
-	CPRINTF("C%d Soft Rst\n", port);
-}
-
-void pd_soft_reset(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i)
-		if (pd_is_connected(i)) {
-			set_state(i, PD_STATE_SOFT_RESET);
-			task_wake(PD_PORT_TO_TASK_ID(i));
-		}
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-/*
- * Request desired charge voltage from source.
- * Returns EC_SUCCESS on success or non-zero on failure.
- */
-static int pd_send_request_msg(int port, int always_send_request)
-{
-	uint32_t rdo, curr_limit, supply_voltage;
-	int res;
-
-	/* Clear new power request */
-	pd[port].new_power_request = 0;
-
-	/* Build and send request RDO */
-	pd_build_request(0, &rdo, &curr_limit, &supply_voltage, port);
-
-	if (!always_send_request) {
-		/* Don't re-request the same voltage */
-		if (pd[port].prev_request_mv == supply_voltage)
-			return EC_SUCCESS;
-#ifdef CONFIG_CHARGE_MANAGER
-		/* Limit current to PD_MIN_MA during transition */
-		else
-			charge_manager_force_ceil(port, PD_MIN_MA);
-#endif
-	}
-
-	CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-		supply_voltage, curr_limit);
-	if (rdo & RDO_CAP_MISMATCH)
-		CPRINTF(" Mismatch");
-	CPRINTF("\n");
-
-	pd[port].curr_limit = curr_limit;
-	pd[port].supply_voltage = supply_voltage;
-	pd[port].prev_request_mv = supply_voltage;
-	res = send_request(port, rdo);
-	if (res < 0)
-		return res;
-	set_state(port, PD_STATE_SNK_REQUESTED);
-	return EC_SUCCESS;
-}
-#endif
-
-static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
-{
-	/* can only parse PDO flags if type is fixed */
-	if ((pdos[0] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-		return;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	if (pdos[0] & PDO_FIXED_DUAL_ROLE)
-		pd[port].flags |= PD_FLAGS_PARTNER_DR_POWER;
-	else
-		pd[port].flags &= ~PD_FLAGS_PARTNER_DR_POWER;
-
-	if (pdos[0] & PDO_FIXED_UNCONSTRAINED)
-		pd[port].flags |= PD_FLAGS_PARTNER_UNCONSTR;
-	else
-		pd[port].flags &= ~PD_FLAGS_PARTNER_UNCONSTR;
-
-	if (pdos[0] & PDO_FIXED_COMM_CAP)
-		pd[port].flags |= PD_FLAGS_PARTNER_USB_COMM;
-	else
-		pd[port].flags &= ~PD_FLAGS_PARTNER_USB_COMM;
-#endif
-
-	if (pdos[0] & PDO_FIXED_DATA_SWAP)
-		pd[port].flags |= PD_FLAGS_PARTNER_DR_DATA;
-	else
-		pd[port].flags &= ~PD_FLAGS_PARTNER_DR_DATA;
-
-	/*
-	 * Treat device as a dedicated charger (meaning we should charge
-	 * from it) if:
-	 *   - it does not support power swap, or
-	 *   - it is unconstrained power, or
-	 *   - it presents at least 27 W of available power
-	 */
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		uint32_t max_ma, max_mv, max_pdo, max_mw, unused;
-
-		/*
-		 * Get max power that the partner offers (not necessarily what
-		 * this board will request)
-		 */
-		pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE,
-				  &max_pdo);
-		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
-		max_mw = max_ma * max_mv / 1000;
-
-		if (!(pdos[0] & PDO_FIXED_DUAL_ROLE) ||
-		    (pdos[0] & PDO_FIXED_UNCONSTRAINED) ||
-		    max_mw >= PD_DRP_CHARGE_POWER_MIN)
-			charge_manager_update_dualrole(port, CAP_DEDICATED);
-		else
-			charge_manager_update_dualrole(port, CAP_DUALROLE);
-	}
-}
-
-static void handle_data_request(int port, uint32_t head,
-		uint32_t *payload)
-{
-	int type = PD_HEADER_TYPE(head);
-	int cnt = PD_HEADER_CNT(head);
-
-	switch (type) {
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	case PD_DATA_SOURCE_CAP:
-		if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-			|| (pd[port].task_state == PD_STATE_SNK_TRANSITION)
-			|| (pd[port].task_state == PD_STATE_SNK_REQUESTED)
-			|| ((get_usb_pd_vbus_detect() ==
-					USB_PD_VBUS_DETECT_NONE)
-				&& (pd[port].task_state ==
-					PD_STATE_SNK_HARD_RESET_RECOVER))
-			|| (pd[port].task_state == PD_STATE_SNK_READY)) {
-#ifdef CONFIG_USB_PD_REV30
-			/*
-			 * Only adjust sink rev if source rev is higher.
-			 */
-			if (PD_HEADER_REV(head) < pd[port].rev)
-				pd[port].rev = PD_HEADER_REV(head);
-#endif
-			/* Port partner is now known to be PD capable */
-			pd[port].flags |= PD_FLAGS_PREVIOUS_PD_CONN;
-
-			/* src cap 0 should be fixed PDO */
-			pd_update_pdo_flags(port, cnt, payload);
-
-			pd_process_source_cap(port, cnt, payload);
-
-			/* Source will resend source cap on failure */
-			pd_send_request_msg(port, 1);
-		}
-		break;
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-	case PD_DATA_REQUEST:
-		if ((pd[port].power_role == PD_ROLE_SOURCE) && (cnt == 1)) {
-#ifdef CONFIG_USB_PD_REV30
-			/*
-			 * Adjust the rev level to what the sink supports. If
-			 * they're equal, no harm done.
-			 */
-			pd[port].rev = PD_HEADER_REV(head);
-#endif
-			if (!pd_check_requested_voltage(payload[0], port)) {
-				if (send_control(port, PD_CTRL_ACCEPT) < 0)
-					/*
-					 * if we fail to send accept, do
-					 * nothing and let sink timeout and
-					 * send hard reset
-					 */
-					return;
-
-				/* explicit contract is now in place */
-				pd[port].flags |= PD_FLAGS_EXPLICIT_CONTRACT;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-				pd_update_saved_port_flags(
-					port, PD_BBRMFLG_EXPLICIT_CONTRACT, 1);
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-				pd[port].requested_idx = RDO_POS(payload[0]);
-				set_state(port, PD_STATE_SRC_ACCEPTED);
-				return;
-			}
-		}
-		/* the message was incorrect or cannot be satisfied */
-		send_control(port, PD_CTRL_REJECT);
-		/* keep last contract in place (whether implicit or explicit) */
-		set_state(port, PD_STATE_SRC_READY);
-		break;
-	case PD_DATA_BIST:
-		/* If not in READY state, then don't start BIST */
-		if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY)) {
-			/* currently only support sending bist carrier mode 2 */
-			if ((payload[0] >> 28) == 5) {
-				/* bist data object mode is 2 */
-				pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0,
-					    NULL, AMS_RESPONSE);
-				/* Set to appropriate port disconnected state */
-				set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
-						PD_STATE_SRC_DISCONNECTED));
-			}
-		}
-		break;
-	case PD_DATA_SINK_CAP:
-		pd[port].flags |= PD_FLAGS_SNK_CAP_RECVD;
-		/* snk cap 0 should be fixed PDO */
-		pd_update_pdo_flags(port, cnt, payload);
-		if (pd[port].task_state == PD_STATE_SRC_GET_SINK_CAP)
-			set_state(port, PD_STATE_SRC_READY);
-		break;
-#ifdef CONFIG_USB_PD_REV30
-	case PD_DATA_BATTERY_STATUS:
-		break;
-	/* TODO : Add case PD_DATA_RESET for exiting USB4 */
-
-	/*
-	 * TODO : Add case PD_DATA_ENTER_USB to accept or reject
-	 * Enter_USB request from port partner.
-	 */
-#endif
-	case PD_DATA_VENDOR_DEF:
-		handle_vdm_request(port, cnt, payload, head);
-		break;
-	default:
-		CPRINTF("C%d Unhandled data message type %d\n", port, type);
-	}
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-void pd_request_power_swap(int port)
-{
-	if (pd[port].task_state == PD_STATE_SRC_READY)
-		set_state(port, PD_STATE_SRC_SWAP_INIT);
-	else if (pd[port].task_state == PD_STATE_SNK_READY)
-		set_state(port, PD_STATE_SNK_SWAP_INIT);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-#ifdef CONFIG_USBC_VCONN_SWAP
-void pd_request_vconn_swap(int port)
-{
-	if (pd[port].task_state == PD_STATE_SRC_READY ||
-	    pd[port].task_state == PD_STATE_SNK_READY)
-		set_state(port, PD_STATE_VCONN_SWAP_SEND);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void pd_try_vconn_src(int port)
-{
-	/*
-	 * If we don't currently provide vconn, and we can supply it, send
-	 * a vconn swap request.
-	 */
-	if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
-		if (pd_check_vconn_swap(port))
-			pd_request_vconn_swap(port);
-	}
-}
-#endif
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-void pd_request_data_swap(int port)
-{
-	if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY))
-		set_state(port, PD_STATE_DR_SWAP);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-static void pd_set_power_role(int port, enum pd_power_role role)
-{
-	pd[port].power_role = role;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	pd_update_saved_port_flags(port, PD_BBRMFLG_POWER_ROLE, role);
-#endif /* defined(CONFIG_USB_PD_DUAL_ROLE) */
-}
-
-static void pd_dr_swap(int port)
-{
-	pd_set_data_role(port, !pd[port].data_role);
-	pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
-}
-
-static void handle_ctrl_request(int port, uint32_t head,
-		uint32_t *payload)
-{
-	int type = PD_HEADER_TYPE(head);
-	int res;
-
-	switch (type) {
-	case PD_CTRL_GOOD_CRC:
-		/* should not get it */
-		break;
-	case PD_CTRL_PING:
-		/* Nothing else to do */
-		break;
-	case PD_CTRL_GET_SOURCE_CAP:
-		if (pd[port].task_state == PD_STATE_SRC_READY)
-			set_state(port, PD_STATE_SRC_DISCOVERY);
-		else {
-			res = send_source_cap(port, AMS_RESPONSE);
-			if ((res >= 0) &&
-			    (pd[port].task_state == PD_STATE_SRC_DISCOVERY))
-				set_state(port, PD_STATE_SRC_NEGOCIATE);
-		}
-		break;
-	case PD_CTRL_GET_SINK_CAP:
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		send_sink_cap(port);
-#else
-		send_control(port, NOT_SUPPORTED(pd[port].rev));
-#endif
-		break;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	case PD_CTRL_GOTO_MIN:
-#ifdef CONFIG_USB_PD_GIVE_BACK
-		if (pd[port].task_state == PD_STATE_SNK_READY) {
-			/*
-			 * Reduce power consumption now!
-			 *
-			 * The source will restore power to this sink
-			 * by sending a new source cap message at a
-			 * later time.
-			 */
-			pd_snk_give_back(port, &pd[port].curr_limit,
-				&pd[port].supply_voltage);
-			set_state(port, PD_STATE_SNK_TRANSITION);
-		}
-#endif
-
-		break;
-	case PD_CTRL_PS_RDY:
-		if (pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE) {
-			set_state(port, PD_STATE_SNK_SWAP_STANDBY);
-		} else if (pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY) {
-			/* reset message ID and swap roles */
-			pd[port].msg_id = 0;
-			invalidate_last_message_id(port);
-			pd_set_power_role(port, PD_ROLE_SINK);
-			pd_update_roles(port);
-			/*
-			 * Give the state machine time to read VBUS as high.
-			 * Note: This is empirically determined, not strictly
-			 * part of the USB PD spec.
-			 */
-			pd[port].vbus_debounce_time =
-				get_time().val + PD_T_DEBOUNCE;
-			set_state(port, PD_STATE_SNK_DISCOVERY);
-#ifdef CONFIG_USBC_VCONN_SWAP
-		} else if (pd[port].task_state == PD_STATE_VCONN_SWAP_INIT) {
-			/*
-			 * If VCONN is on, then this PS_RDY tells us it's
-			 * ok to turn VCONN off
-			 */
-			if (pd[port].flags & PD_FLAGS_VCONN_ON)
-				set_state(port, PD_STATE_VCONN_SWAP_READY);
-#endif
-		} else if (pd[port].task_state == PD_STATE_SNK_DISCOVERY) {
-			/* Don't know what power source is ready. Reset. */
-			set_state(port, PD_STATE_HARD_RESET_SEND);
-		} else if (pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY) {
-			/* Do nothing, assume this is a redundant PD_RDY */
-		} else if (pd[port].power_role == PD_ROLE_SINK) {
-			/*
-			 * Give the source some time to send any messages before
-			 * we start our interrogation.  Add some jitter of up to
-			 * ~192ms to prevent multiple collisions.
-			 */
-			if (pd[port].task_state == PD_STATE_SNK_TRANSITION)
-				pd[port].ready_state_holdoff_timer =
-					get_time().val + SNK_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
-
-			set_state(port, PD_STATE_SNK_READY);
-			pd_set_input_current_limit(port, pd[port].curr_limit,
-						   pd[port].supply_voltage);
-#ifdef CONFIG_CHARGE_MANAGER
-			/* Set ceiling based on what's negotiated */
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
-						pd[port].curr_limit);
-#endif
-		}
-		break;
-#endif
-	case PD_CTRL_REJECT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/*
-			 * Since Enter USB sets the mux state to SAFE mode,
-			 * resetting the mux state back to USB mode on
-			 * recieveing a NACK.
-			 */
-			usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-			break;
-		}
-	case PD_CTRL_WAIT:
-		if (pd[port].task_state == PD_STATE_DR_SWAP) {
-			if (type == PD_CTRL_WAIT) /* try again ... */
-				pd[port].flags |= PD_FLAGS_CHECK_DR_ROLE;
-			set_state(port, READY_RETURN_STATE(port));
-		}
-#ifdef CONFIG_USBC_VCONN_SWAP
-		else if (pd[port].task_state == PD_STATE_VCONN_SWAP_SEND)
-			set_state(port, READY_RETURN_STATE(port));
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		else if (pd[port].task_state == PD_STATE_SRC_SWAP_INIT)
-			set_state(port, PD_STATE_SRC_READY);
-		else if (pd[port].task_state == PD_STATE_SNK_SWAP_INIT)
-			set_state(port, PD_STATE_SNK_READY);
-		else if (pd[port].task_state == PD_STATE_SNK_REQUESTED) {
-			/*
-			 * On reception of a WAIT message, transition to
-			 * PD_STATE_SNK_READY after PD_T_SINK_REQUEST ms to
-			 * send another request.
-			 *
-			 * On reception of a REJECT message, transition to
-			 * PD_STATE_SNK_READY but don't resend the request if
-			 * we already have a contract in place.
-			 *
-			 * On reception of a REJECT message without a contract,
-			 * transition to PD_STATE_SNK_DISCOVERY instead.
-			 */
-			if (type == PD_CTRL_WAIT) {
-				/*
-				 * Trigger a new power request when
-				 * we enter PD_STATE_SNK_READY
-				 */
-				pd[port].new_power_request = 1;
-
-				/*
-				 * After the request is triggered,
-				 * make sure the request is sent.
-				 */
-				pd[port].prev_request_mv = 0;
-
-				/*
-				 * Transition to PD_STATE_SNK_READY
-				 * after PD_T_SINK_REQUEST ms.
-				 */
-				set_state_timeout(port,
-						  get_time().val +
-							  PD_T_SINK_REQUEST,
-						  PD_STATE_SNK_READY);
-			} else {
-				/* The request was rejected */
-				const int in_contract =
-					pd[port].flags &
-					PD_FLAGS_EXPLICIT_CONTRACT;
-				set_state(port,
-					  in_contract ? PD_STATE_SNK_READY
-						      : PD_STATE_SNK_DISCOVERY);
-			}
-		}
-#endif
-		break;
-	case PD_CTRL_ACCEPT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/* Connect the SBU and USB lines to the connector */
-			if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-				ppc_set_sbu(port, 1);
-
-			/* Set usb mux to USB4 mode */
-			usb_mux_set(port, USB_PD_MUX_USB4_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-		} else if (pd[port].task_state == PD_STATE_SOFT_RESET) {
-			/*
-			 * For the case that we sent soft reset in SNK_DISCOVERY
-			 * on startup due to VBUS never low, clear the flag.
-			 */
-			pd[port].flags &= ~PD_FLAGS_VBUS_NEVER_LOW;
-			execute_soft_reset(port);
-		} else if (pd[port].task_state == PD_STATE_DR_SWAP) {
-			/* switch data role */
-			pd_dr_swap(port);
-			set_state(port, READY_RETURN_STATE(port));
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-#ifdef CONFIG_USBC_VCONN_SWAP
-		} else if (pd[port].task_state == PD_STATE_VCONN_SWAP_SEND) {
-			/* switch vconn */
-			set_state(port, PD_STATE_VCONN_SWAP_INIT);
-#endif
-		} else if (pd[port].task_state == PD_STATE_SRC_SWAP_INIT) {
-			/* explicit contract goes away for power swap */
-			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
-			set_state(port, PD_STATE_SRC_SWAP_SNK_DISABLE);
-		} else if (pd[port].task_state == PD_STATE_SNK_SWAP_INIT) {
-			/* explicit contract goes away for power swap */
-			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
-			set_state(port, PD_STATE_SNK_SWAP_SNK_DISABLE);
-		} else if (pd[port].task_state == PD_STATE_SNK_REQUESTED) {
-			/* explicit contract is now in place */
-			pd[port].flags |= PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   1);
-			set_state(port, PD_STATE_SNK_TRANSITION);
-#endif
-		}
-		break;
-	case PD_CTRL_SOFT_RESET:
-		execute_soft_reset(port);
-		pd[port].msg_id = 0;
-		/* We are done, acknowledge with an Accept packet */
-		send_control(port, PD_CTRL_ACCEPT);
-		break;
-	case PD_CTRL_PR_SWAP:
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		if (pd_check_power_swap(port)) {
-			send_control(port, PD_CTRL_ACCEPT);
-			/*
-			 * Clear flag for checking power role to avoid
-			 * immediately requesting another swap.
-			 */
-			pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
-			set_state(port,
-				  DUAL_ROLE_IF_ELSE(port,
-					PD_STATE_SNK_SWAP_SNK_DISABLE,
-					PD_STATE_SRC_SWAP_SNK_DISABLE));
-		} else {
-			send_control(port, PD_CTRL_REJECT);
-		}
-#else
-		send_control(port, NOT_SUPPORTED(pd[port].rev));
-#endif
-		break;
-	case PD_CTRL_DR_SWAP:
-		if (pd_check_data_swap(port, pd[port].data_role)) {
-			/*
-			 * Accept switch and perform data swap. Clear
-			 * flag for checking data role to avoid
-			 * immediately requesting another swap.
-			 */
-			pd[port].flags &= ~PD_FLAGS_CHECK_DR_ROLE;
-			if (send_control(port, PD_CTRL_ACCEPT) >= 0)
-				pd_dr_swap(port);
-		} else {
-			send_control(port, PD_CTRL_REJECT);
-
-		}
-		break;
-	case PD_CTRL_VCONN_SWAP:
-#ifdef CONFIG_USBC_VCONN_SWAP
-		if (pd[port].task_state == PD_STATE_SRC_READY ||
-		    pd[port].task_state == PD_STATE_SNK_READY) {
-			if (pd_check_vconn_swap(port)) {
-				if (send_control(port, PD_CTRL_ACCEPT) > 0)
-					set_state(port,
-						  PD_STATE_VCONN_SWAP_INIT);
-			} else {
-				send_control(port, PD_CTRL_REJECT);
-			}
-		}
-#else
-		send_control(port, NOT_SUPPORTED(pd[port].rev));
-#endif
-		break;
-	default:
-#ifdef CONFIG_USB_PD_REV30
-		send_control(port, PD_CTRL_NOT_SUPPORTED);
-#endif
-		CPRINTF("C%d Unhandled ctrl message type %d\n", port, type);
-	}
-}
-
-#ifdef CONFIG_USB_PD_REV30
-static void handle_ext_request(int port, uint16_t head, uint32_t *payload)
-{
-	int type = PD_HEADER_TYPE(head);
-
-	switch (type) {
-	case PD_EXT_GET_BATTERY_CAP:
-		send_battery_cap(port, payload);
-		break;
-	case PD_EXT_GET_BATTERY_STATUS:
-		send_battery_status(port, payload);
-		break;
-	case PD_EXT_BATTERY_CAP:
-		break;
-	default:
-		send_control(port, PD_CTRL_NOT_SUPPORTED);
-	}
-}
-#endif
-
-static void handle_request(int port, uint32_t head,
-		uint32_t *payload)
-{
-	int cnt = PD_HEADER_CNT(head);
-	int data_role = PD_HEADER_DROLE(head);
-	int p;
-
-	/* dump received packet content (only dump ping at debug level 3) */
-	if ((debug_level == 2 && PD_HEADER_TYPE(head) != PD_CTRL_PING) ||
-	    debug_level >= 3) {
-		CPRINTF("C%d RECV %04x/%d ", port, head, cnt);
-		for (p = 0; p < cnt; p++)
-			CPRINTF("[%d]%08x ", p, payload[p]);
-		CPRINTF("\n");
-	}
-
-	/*
-	 * If we are in disconnected state, we shouldn't get a request. Do
-	 * a hard reset if we get one.
-	 */
-	if (!pd_is_connected(port))
-		set_state(port, PD_STATE_HARD_RESET_SEND);
-
-	/*
-	 * When a data role conflict is detected, USB-C ErrorRecovery
-	 * actions shall be performed, and transitioning to unattached state
-	 * is one such legal action.
-	 */
-	if (pd[port].data_role == data_role) {
-		/*
-		 * If the port doesn't support removing the terminations, just
-		 * go to the unattached state.
-		 */
-		if (tcpm_set_cc(port, TYPEC_CC_OPEN) == EC_SUCCESS) {
-			/* Do not drive VBUS or VCONN. */
-			pd_power_supply_reset(port);
-#ifdef CONFIG_USBC_VCONN
-			set_vconn(port, 0);
-#endif /* defined(CONFIG_USBC_VCONN) */
-			usleep(PD_T_ERROR_RECOVERY);
-
-			/* Restore terminations. */
-			tcpm_set_cc(port, DUAL_ROLE_IF_ELSE(port, TYPEC_CC_RD,
-							    TYPEC_CC_RP));
-		}
-		set_state(port,
-			  DUAL_ROLE_IF_ELSE(port,
-					    PD_STATE_SNK_DISCONNECTED,
-					    PD_STATE_SRC_DISCONNECTED));
-		return;
-	}
-
-#ifdef CONFIG_USB_PD_REV30
-	/* Check if this is an extended chunked data message. */
-	if (pd[port].rev == PD_REV30 && PD_HEADER_EXT(head)) {
-		handle_ext_request(port, head, payload);
-		return;
-	}
-#endif
-	if (cnt)
-		handle_data_request(port, head, payload);
-	else
-		handle_ctrl_request(port, head, payload);
-}
-
-void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-		 int count)
-{
-	if (count > VDO_MAX_SIZE - 1) {
-		CPRINTF("C%d VDM over max size\n", port);
-		return;
-	}
-
-	/* set VDM header with VID & CMD */
-	pd[port].vdo_data[0] = VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?
-				   1 : (PD_VDO_CMD(cmd) <= CMD_ATTENTION), cmd);
-#ifdef CONFIG_USB_PD_REV30
-	pd[port].vdo_data[0] |= VDO_SVDM_VERS(vdo_ver[pd[port].rev]);
-#endif
-	queue_vdm(port, pd[port].vdo_data, data, count, TCPCI_MSG_SOP);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-static inline int pdo_busy(int port)
-{
-	/*
-	 * Note, main PDO state machine (pd_task) uses READY state exclusively
-	 * to denote port partners have successfully negociated a contract.  All
-	 * other protocol actions force state transitions.
-	 */
-	int rv = (pd[port].task_state != PD_STATE_SRC_READY);
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	rv &= (pd[port].task_state != PD_STATE_SNK_READY);
-#endif
-	return rv;
-}
-
-static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr)
-{
-	uint64_t timeout;
-	int cmd = PD_VDO_CMD(vdm_hdr);
-
-	/* its not a structured VDM command */
-	if (!PD_VDO_SVDM(vdm_hdr))
-		return 500*MSEC;
-
-	switch (PD_VDO_CMDT(vdm_hdr)) {
-	case CMDT_INIT:
-		if ((cmd == CMD_ENTER_MODE) || (cmd == CMD_EXIT_MODE))
-			timeout = PD_T_VDM_WAIT_MODE_E;
-		else
-			timeout = PD_T_VDM_SNDR_RSP;
-		break;
-	default:
-		if ((cmd == CMD_ENTER_MODE) || (cmd == CMD_EXIT_MODE))
-			timeout = PD_T_VDM_E_MODE;
-		else
-			timeout = PD_T_VDM_RCVR_RSP;
-		break;
-	}
-	return timeout;
-}
-
-static void exit_tbt_mode_sop_prime(int port)
-{
-	/* Exit Thunderbolt-Compatible mode SOP' */
-	uint16_t header;
-	int opos;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		return;
-
-	opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL);
-	if (opos <= 0)
-		return;
-
-	CPRINTS("C%d Cable exiting TBT Compat mode", port);
-	/*
-	 * Note: TCPMv2 contemplates separate discovery structures for each SOP
-	 * type. TCPMv1 only uses one discovery structure, so all accesses
-	 * specify TCPCI_MSG_SOP.
-	 */
-	if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL, opos))
-		usb_mux_set_safe_mode(port);
-	else
-		return;
-
-	header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id,
-			(int)pd[port].vdo_count,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	pd[port].vdo_data[0] = VDO(USB_VID_INTEL, 1,
-				   CMD_EXIT_MODE | VDO_OPOS(opos));
-
-	pd_transmit(port, TCPCI_MSG_SOP_PRIME, header, pd[port].vdo_data,
-		    AMS_START);
-
-	usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
-		   polarity_rm_dts(pd_get_polarity(port)));
-}
-
-static void pd_vdm_send_state_machine(int port)
-{
-	int res;
-	uint16_t header;
-	enum tcpci_msg_type msg_type = pd[port].xmit_type;
-
-	switch (pd[port].vdm_state) {
-	case VDM_STATE_READY:
-		/* Only transmit VDM if connected. */
-		if (!pd_is_connected(port)) {
-			pd[port].vdm_state = VDM_STATE_ERR_BUSY;
-			break;
-		}
-
-		/*
-		 * if there's traffic or we're not in PDO ready state don't send
-		 * a VDM.
-		 */
-		if (pdo_busy(port))
-			break;
-
-		/*
-		 * To communicate with the cable plug, an explicit contract
-		 * should be established, VCONN should be enabled and data role
-		 * that can communicate with the cable plug should be in place.
-		 * For USB3.0, UFP/DFP can communicate whereas in case of
-		 * USB2.0 only DFP can talk to the cable plug.
-		 *
-		 * For communication between USB2.0 UFP and cable plug,
-		 * data role swap takes place during source and sink
-		 * negotiation and in case of failure, a soft reset is issued.
-		 */
-		if ((msg_type == TCPCI_MSG_SOP_PRIME) ||
-		    (msg_type == TCPCI_MSG_SOP_PRIME_PRIME)) {
-			/* Prepare SOP'/SOP'' header and send VDM */
-			header = PD_HEADER(
-				PD_DATA_VENDOR_DEF,
-				PD_PLUG_FROM_DFP_UFP,
-				0,
-				pd[port].msg_id,
-				(int)pd[port].vdo_count,
-				pd_get_rev(port, TCPCI_MSG_SOP),
-				0);
-			res = pd_transmit(port, msg_type, header,
-					  pd[port].vdo_data, AMS_START);
-			/*
-			 * In the case of SOP', if there is no response from
-			 * the cable, it's a non-emark cable and therefore the
-			 * pd flow should continue irrespective of cable
-			 * response, sending discover_identity so the pd flow
-			 * remains intact.
-			 *
-			 * In the case of SOP'', if there is no response from
-			 * the cable, exit Thunderbolt-Compatible mode
-			 * discovery, reset the mux state since, the mux will
-			 * be set to a safe state before entering
-			 * Thunderbolt-Compatible mode and enter the default
-			 * mode.
-			 */
-			if (res < 0) {
-				header = PD_HEADER(PD_DATA_VENDOR_DEF,
-						   pd[port].power_role,
-						   pd[port].data_role,
-						   pd[port].msg_id,
-						   (int)pd[port].vdo_count,
-						   pd_get_rev
-							(port, TCPCI_MSG_SOP),
-						   0);
-
-				if ((msg_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-				     IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-					exit_tbt_mode_sop_prime(port);
-				} else if (msg_type == TCPCI_MSG_SOP_PRIME) {
-					pd[port].vdo_data[0] = VDO(USB_SID_PD,
-						1, CMD_DISCOVER_SVID);
-				}
-				res = pd_transmit(port, TCPCI_MSG_SOP, header,
-						  pd[port].vdo_data, AMS_START);
-				reset_pd_cable(port);
-			}
-		} else {
-			/* Prepare SOP header and send VDM */
-			header = PD_HEADER(PD_DATA_VENDOR_DEF,
-					   pd[port].power_role,
-					   pd[port].data_role,
-					   pd[port].msg_id,
-					   (int)pd[port].vdo_count,
-					   pd_get_rev(port, TCPCI_MSG_SOP), 0);
-			res = pd_transmit(port, TCPCI_MSG_SOP, header,
-					  pd[port].vdo_data, AMS_START);
-		}
-
-		if (res < 0) {
-			pd[port].vdm_state = VDM_STATE_ERR_SEND;
-		} else {
-			pd[port].vdm_state = VDM_STATE_BUSY;
-			pd[port].vdm_timeout.val = get_time().val +
-				vdm_get_ready_timeout(pd[port].vdo_data[0]);
-		}
-		break;
-	case VDM_STATE_WAIT_RSP_BUSY:
-		/* wait and then initiate request again */
-		if (get_time().val > pd[port].vdm_timeout.val) {
-			pd[port].vdo_data[0] = pd[port].vdo_retry;
-			pd[port].vdo_count = 1;
-			pd[port].vdm_state = VDM_STATE_READY;
-		}
-		break;
-	case VDM_STATE_BUSY:
-		/* Wait for VDM response or timeout */
-		if (pd[port].vdm_timeout.val &&
-		    (get_time().val > pd[port].vdm_timeout.val)) {
-			pd[port].vdm_state = VDM_STATE_ERR_TMOUT;
-		}
-		break;
-	case VDM_STATE_ERR_SEND:
-		/* Sending the VDM failed, so try again. */
-		CPRINTF("C%d VDMretry\n", port);
-		pd[port].vdm_state = VDM_STATE_READY;
-		break;
-	default:
-		break;
-	}
-}
-
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-static inline void pd_dev_dump_info(uint16_t dev_id, uint8_t *hash)
-{
-	int j;
-	ccprintf("DevId:%d.%d Hash:", HW_DEV_ID_MAJ(dev_id),
-		 HW_DEV_ID_MIN(dev_id));
-	for (j = 0; j < PD_RW_HASH_SIZE; j += 4) {
-		ccprintf(" 0x%02x%02x%02x%02x", hash[j + 3], hash[j + 2],
-			 hash[j + 1], hash[j]);
-	}
-	ccprintf("\n");
-}
-#endif /* CONFIG_CMD_PD_DEV_DUMP_INFO */
-
-int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
-			 uint32_t current_image)
-{
-#ifdef CONFIG_COMMON_RUNTIME
-	int i;
-#endif
-
-	pd[port].dev_id = dev_id;
-	memcpy(pd[port].dev_rw_hash, rw_hash, PD_RW_HASH_SIZE);
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-	if (debug_level >= 2)
-		pd_dev_dump_info(dev_id, (uint8_t *)rw_hash);
-#endif
-	pd[port].current_image = current_image;
-
-#ifdef CONFIG_COMMON_RUNTIME
-	/* Search table for matching device / hash */
-	for (i = 0; i < RW_HASH_ENTRIES; i++)
-		if (dev_id == rw_hash_table[i].dev_id)
-			return !memcmp(rw_hash,
-				       rw_hash_table[i].dev_rw_hash,
-				       PD_RW_HASH_SIZE);
-#endif
-	return 0;
-}
-
-void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
-{
-	*dev_id = pd[port].dev_id;
-	*current_image = pd[port].current_image;
-	if (*dev_id)
-		memcpy(rw_hash, pd[port].dev_rw_hash, PD_RW_HASH_SIZE);
-}
-
-__maybe_unused static void exit_supported_alt_mode(int port)
-{
-	int i;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		return;
-
-	for (i = 0; i < supported_modes_cnt; i++) {
-		int opos = pd_alt_mode(port, TCPCI_MSG_SOP,
-				supported_modes[i].svid);
-
-		if (opos > 0 && pd_dfp_exit_mode(port, TCPCI_MSG_SOP,
-					supported_modes[i].svid, opos)) {
-			CPRINTS("C%d Exiting ALT mode with SVID = 0x%x", port,
-				supported_modes[i].svid);
-			usb_mux_set_safe_mode(port);
-			pd_send_vdm(port, supported_modes[i].svid,
-				    CMD_EXIT_MODE | VDO_OPOS(opos), NULL, 0);
-			/* Wait for an ACK from port-partner */
-			pd_vdm_send_state_machine(port);
-		}
-	}
-}
-
-#ifdef CONFIG_POWER_COMMON
-static void handle_new_power_state(int port)
-{
-
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
-		/*
-		 * The SoC will negotiate the alternate mode again when
-		 * it boots up.
-		 */
-		exit_supported_alt_mode(port);
-	}
-#ifdef CONFIG_USBC_VCONN_SWAP
-	else {
-		/* Request for Vconn Swap */
-		pd_try_vconn_src(port);
-	}
-#endif
-	/* Ensure mux is set properly after chipset transition */
-	set_usb_mux_with_current_data_role(port);
-}
-#endif /* CONFIG_POWER_COMMON */
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-enum pd_dual_role_states pd_get_dual_role(int port)
-{
-	return drp_state[port];
-}
-
-#ifdef CONFIG_USB_PD_TRY_SRC
-static void pd_update_try_source(void)
-{
-	int i;
-
-	pd_try_src_enable = pd_is_try_source_capable();
-
-	/*
-	 * Clear this flag to cover case where a TrySrc
-	 * mode went from enabled to disabled and trying_source
-	 * was active at that time.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		pd[i].flags &= ~PD_FLAGS_TRY_SRC;
-}
-#endif /* CONFIG_USB_PD_TRY_SRC */
-
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-static void pd_update_snk_reset(void)
-{
-	int i;
-	int batt_soc = usb_get_battery_soc();
-
-	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
-	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
-		return;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (pd[i].flags & PD_FLAGS_SNK_WAITING_BATT) {
-			/*
-			 * Battery has gained sufficient charge to kick off PD
-			 * negotiation and withstand a hard reset.  Clear the
-			 * flag and let reset begin if task is waiting in
-			 * SNK_DISCOVERY.
-			 */
-			pd[i].flags &= ~PD_FLAGS_SNK_WAITING_BATT;
-
-			if (pd[i].task_state == PD_STATE_SNK_DISCOVERY) {
-				CPRINTS("C%d: Starting soft reset timer", i);
-				set_state_timeout(i,
-					get_time().val + PD_T_SINK_WAIT_CAP,
-					PD_STATE_SOFT_RESET);
-			}
-		}
-	}
-}
-#endif
-
-#if defined(CONFIG_USB_PD_TRY_SRC) || defined(CONFIG_USB_PD_RESET_MIN_BATT_SOC)
-static void pd_update_battery_soc_change(void)
-{
-#ifdef CONFIG_USB_PD_TRY_SRC
-	pd_update_try_source();
-#endif
-
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-	pd_update_snk_reset();
-#endif
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pd_update_battery_soc_change,
-	     HOOK_PRIO_DEFAULT);
-#endif /* CONFIG_USB_PD_TRY_SRC || CONFIG_USB_PD_RESET_MIN_BATT_SOC */
-
-static inline void pd_set_dual_role_no_wakeup(int port,
-					      enum pd_dual_role_states state)
-{
-	drp_state[port] = state;
-
-#ifdef CONFIG_USB_PD_TRY_SRC
-	pd_update_try_source();
-#endif
-}
-
-void pd_set_dual_role(int port, enum pd_dual_role_states state)
-{
-	pd_set_dual_role_no_wakeup(port, state);
-
-	/* Wake task up to process change */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_UPDATE_DUAL_ROLE);
-}
-
-static int pd_is_power_swapping(int port)
-{
-	/* return true if in the act of swapping power roles */
-	return  pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY;
-}
-
-/* This must only be called from the PD task */
-static void pd_update_dual_role_config(int port)
-{
-	/*
-	 * Change to sink if port is currently a source AND (new DRP
-	 * state is force sink OR new DRP state is toggle off and we are in the
-	 * source disconnected state).
-	 */
-	if (pd[port].power_role == PD_ROLE_SOURCE &&
-	    (drp_state[port] == PD_DRP_FORCE_SINK
-	     || (drp_state[port] == PD_DRP_TOGGLE_OFF
-		 && pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) {
-		pd_set_power_role(port, PD_ROLE_SINK);
-		set_state(port, PD_STATE_SNK_DISCONNECTED);
-		tcpm_set_cc(port, TYPEC_CC_RD);
-		/* Make sure we're not sourcing VBUS. */
-		pd_power_supply_reset(port);
-	}
-
-	/*
-	 * Change to source if port is currently a sink and the
-	 * new DRP state is force source. If we are performing
-	 * power swap we won't change anything because
-	 * changing state will disrupt power swap process
-	 * and we are power swapping to desired power role.
-	 */
-	if (pd[port].power_role == PD_ROLE_SINK &&
-	    drp_state[port] == PD_DRP_FORCE_SOURCE &&
-	    !pd_is_power_swapping(port)) {
-		pd_set_power_role(port, PD_ROLE_SOURCE);
-		set_state(port, PD_STATE_SRC_DISCONNECTED);
-		tcpm_set_cc(port, TYPEC_CC_RP);
-	}
-}
-
-/*
- * Provide Rp to ensure the partner port is in a known state (eg. not
- * PD negotiated, not sourcing 20V).
- */
-static void pd_partner_port_reset(int port)
-{
-	uint64_t timeout;
-	uint8_t flags;
-
-	/*
-	 * If there is no contract in place (or if we fail to read the BBRAM
-	 * flags), there is no need to reset the partner.
-	 */
-	if (pd_get_saved_port_flags(port, &flags) != EC_SUCCESS ||
-	    !(flags & PD_BBRMFLG_EXPLICIT_CONTRACT))
-		return;
-
-	/*
-	 * If we reach here, an explicit contract is in place.
-	 *
-	 * If PD communications are allowed, don't apply Rp.  We'll issue a
-	 * SoftReset later on and renegotiate our contract.  This particular
-	 * condition only applies to unlocked RO images with an explicit
-	 * contract in place.
-	 */
-	if (pd_comm_is_enabled(port))
-		return;
-
-	/* If we just lost power, don't apply Rp. */
-	if (system_get_reset_flags() &
-	    (EC_RESET_FLAG_BROWNOUT | EC_RESET_FLAG_POWER_ON))
-		return;
-
-	/*
-	 * Clear the active contract bit before we apply Rp in case we
-	 * intentionally brown out because we cut off our only power supply.
-	 */
-	pd_update_saved_port_flags(port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
-
-	/* Provide Rp for 200 msec. or until we no longer have VBUS. */
-	CPRINTF("C%d Apply Rp!\n", port);
-	cflush();
-	tcpm_set_cc(port, TYPEC_CC_RP);
-	timeout = get_time().val + 200 * MSEC;
-
-	while (get_time().val < timeout && pd_is_vbus_present(port))
-		msleep(10);
-}
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return pd[port].power_role;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	return pd[port].data_role;
-}
-
-enum pd_cc_states pd_get_task_cc_state(int port)
-{
-	return pd[port].cc_state;
-}
-
-uint8_t pd_get_task_state(int port)
-{
-	return pd[port].task_state;
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-uint32_t pd_get_requested_voltage(int port)
-{
-	return pd[port].supply_voltage;
-}
-
-uint32_t pd_get_requested_current(int port)
-{
-	return pd[port].curr_limit;
-}
-#endif
-
-const char *pd_get_task_state_name(int port)
-{
-#ifdef CONFIG_USB_PD_TCPMV1_DEBUG
-	if (debug_level > 0)
-		return pd_state_names[pd[port].task_state];
-#endif
-	return "";
-}
-
-bool pd_get_vconn_state(int port)
-{
-	return !!(pd[port].flags & PD_FLAGS_VCONN_ON);
-}
-
-bool pd_get_partner_dual_role_power(int port)
-{
-	return !!(pd[port].flags & PD_FLAGS_PARTNER_DR_POWER);
-}
-
-bool pd_get_partner_unconstr_power(int port)
-{
-	return !!(pd[port].flags & PD_FLAGS_PARTNER_UNCONSTR);
-}
-
-enum tcpc_cc_polarity pd_get_polarity(int port)
-{
-	return pd[port].polarity;
-}
-
-bool pd_get_partner_data_swap_capable(int port)
-{
-	/* return data swap capable status of port partner */
-	return !!(pd[port].flags & PD_FLAGS_PARTNER_DR_DATA);
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-void pd_comm_enable(int port, int enable)
-{
-	/* We don't check port >= CONFIG_USB_PD_PORT_MAX_COUNT deliberately */
-	pd_comm_enabled[port] = enable;
-
-	/* If type-C connection, then update the TCPC RX enable */
-	if (pd_is_connected(port))
-		tcpm_set_rx_enable(port, enable);
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If communications are enabled, start hard reset timer for
-	 * any port in PD_SNK_DISCOVERY.
-	 */
-	if (enable && pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-		set_state_timeout(port,
-				  get_time().val + PD_T_SINK_WAIT_CAP,
-				  PD_STATE_HARD_RESET_SEND);
-#endif
-}
-#endif
-
-void pd_ping_enable(int port, int enable)
-{
-	if (enable)
-		pd[port].flags |= PD_FLAGS_PING_ENABLED;
-	else
-		pd[port].flags &= ~PD_FLAGS_PING_ENABLED;
-}
-
-__overridable uint8_t board_get_src_dts_polarity(int port)
-{
-	/*
-	 * If the port in SRC DTS, the polarity is determined by the board,
-	 * i.e. what Rp impedance the CC lines are pulled. If this function
-	 * is not overridden, assume CC1 is primary.
-	 */
-	return 0;
-}
-
-#if defined(CONFIG_CHARGE_MANAGER)
-
-/**
- * Signal power request to indicate a charger update that affects the port.
- */
-void pd_set_new_power_request(int port)
-{
-	pd[port].new_power_request = 1;
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-#endif /* CONFIG_CHARGE_MANAGER */
-
-#if defined(CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP) && defined(CONFIG_USBC_SS_MUX)
-/*
- * Backwards compatible DFP does not support USB SS because it applies VBUS
- * before debouncing CC and setting USB SS muxes, but SS detection will fail
- * before we are done debouncing CC.
- */
-#error "Backwards compatible DFP does not support USB"
-#endif
-
-#ifdef CONFIG_COMMON_RUNTIME
-
-/* Initialize globals based on system state. */
-static void pd_init_tasks(void)
-{
-	static int initialized;
-	int enable = 1;
-	int i;
-
-	/* Initialize globals once, for all PD tasks.  */
-	if (initialized)
-		return;
-
-#if defined(HAS_TASK_CHIPSET) && defined(CONFIG_USB_PD_DUAL_ROLE)
-	/* Set dual-role state based on chipset power state */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		for (i = 0; i < board_get_usb_pd_port_count(); i++)
-			drp_state[i] = PD_DRP_FORCE_SINK;
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		for (i = 0; i < board_get_usb_pd_port_count(); i++)
-			drp_state[i] = PD_DRP_TOGGLE_OFF;
-	else /* CHIPSET_STATE_ON */
-		for (i = 0; i < board_get_usb_pd_port_count(); i++)
-			drp_state[i] = PD_DRP_TOGGLE_ON;
-#endif
-
-#if defined(CONFIG_USB_PD_COMM_DISABLED)
-	enable = 0;
-#elif defined(CONFIG_USB_PD_COMM_LOCKED)
-	/* Disable PD communication if we're in RO, WP is enabled, and EFS
-	 * didn't register NO_BOOT. */
-	if (!system_is_in_rw() && system_is_locked() && !vboot_allow_usb_pd())
-		enable = 0;
-#endif
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		pd_comm_enabled[i] = enable;
-	CPRINTS("PD comm %sabled", enable ? "en" : "dis");
-
-	initialized = 1;
-}
-#endif /* CONFIG_COMMON_RUNTIME */
-
-#if !defined(CONFIG_USB_PD_TCPC) && defined(CONFIG_USB_PD_DUAL_ROLE)
-static int pd_restart_tcpc(int port)
-{
-	if (board_set_tcpc_power_mode) {
-		/* force chip reset */
-		board_set_tcpc_power_mode(port, 0);
-	}
-	return tcpm_init(port);
-}
-#endif
-
-static void pd_send_enter_usb(int port, int *timeout)
-{
-	uint32_t usb4_payload;
-	uint16_t header;
-	int res;
-
-	/*
-	 * TODO: Enable Enter USB for cables (SOP').
-	 * This is needed for active cables
-	 */
-	if (!IS_ENABLED(CONFIG_USBC_SS_MUX) ||
-	    !IS_ENABLED(CONFIG_USB_PD_USB4) ||
-	    !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		return;
-
-	usb4_payload = get_enter_usb_msg_payload(port);
-
-	header = PD_HEADER(PD_DATA_ENTER_USB,
-		pd[port].power_role,
-		pd[port].data_role,
-		pd[port].msg_id,
-		1,
-		PD_REV30,
-		0);
-
-	res = pd_transmit(port, TCPCI_MSG_SOP, header, &usb4_payload,
-			AMS_START);
-	if (res < 0) {
-		*timeout = 10*MSEC;
-		/*
-		 * If failed to get goodCRC, send soft reset, otherwise ignore
-		 * failure.
-		 */
-		set_state(port, res == -1 ?
-			   PD_STATE_SOFT_RESET :
-			   READY_RETURN_STATE(port));
-		return;
-	}
-
-	/* Disable Enter USB4 mode prevent re-entry */
-	disable_enter_usb4_mode(port);
-
-	set_state(port, PD_STATE_ENTER_USB);
-}
-
-void pd_task(void *u)
-{
-	uint32_t head;
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-	uint32_t payload[7];
-	int timeout = 10*MSEC;
-	enum tcpc_cc_voltage_status cc1, cc2;
-	int res, incoming_packet = 0;
-	int hard_reset_count = 0;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	uint64_t next_role_swap = PD_T_DRP_SNK;
-	uint8_t saved_flgs = 0;
-#ifndef CONFIG_USB_PD_VBUS_DETECT_NONE
-	int snk_hard_reset_vbus_off = 0;
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	const int auto_toggle_supported = tcpm_auto_toggle_supported(port);
-#endif
-#if defined(CONFIG_CHARGE_MANAGER)
-	typec_current_t typec_curr = 0, typec_curr_change = 0;
-#endif /* CONFIG_CHARGE_MANAGER */
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-	enum pd_states this_state;
-	enum pd_cc_states new_cc_state;
-	timestamp_t now;
-	uint64_t next_src_cap = 0;
-	int caps_count = 0, hard_reset_sent = 0;
-	int snk_cap_count = 0;
-	int evt;
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	/*
-	 * Set the ports in Low Power Mode so that other tasks wait until
-	 * TCPC is initialized and ready.
-	 */
-	pd[port].flags |= PD_FLAGS_LPM_ENGAGED;
-#endif
-
-#ifdef CONFIG_COMMON_RUNTIME
-	pd_init_tasks();
-#endif
-
-	/*
-	 * Ensure the power supply is in the default state and ensure we are not
-	 * sourcing Vconn
-	 */
-	pd_power_supply_reset(port);
-#ifdef CONFIG_USBC_VCONN
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If we were previously a sink but also the VCONN source, we should
-	 * still continue to source VCONN. Otherwise, we should turn off VCONN
-	 * since we are also going to turn off VBUS.
-	 */
-	if (pd_comm_is_enabled(port) &&
-	    (pd_get_saved_port_flags(port, &saved_flgs) == EC_SUCCESS) &&
-	    ((saved_flgs & PD_BBRMFLG_POWER_ROLE) == PD_ROLE_SINK) &&
-	    (saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT) &&
-	    (saved_flgs & PD_BBRMFLG_VCONN_ROLE))
-		set_vconn(port, 1);
-	else
-#endif
-		set_vconn(port, 0);
-#endif
-
-#ifdef CONFIG_USB_PD_TCPC_BOARD_INIT
-	/* Board specific TCPC init */
-	board_tcpc_init();
-#endif
-
-	/* Initialize TCPM driver and wait for TCPC to be ready */
-	res = reset_device_and_notify(port);
-	invalidate_last_message_id(port);
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	pd_partner_port_reset(port);
-#endif
-
-	this_state = res ? PD_STATE_SUSPENDED : PD_DEFAULT_STATE(port);
-#ifndef CONFIG_USB_PD_TCPC
-	if (!res) {
-		struct ec_response_pd_chip_info_v1 info;
-
-		if (tcpm_get_chip_info(port, 0, &info) ==
-		    EC_SUCCESS) {
-			CPRINTS("TCPC p%d VID:0x%x PID:0x%x DID:0x%x "
-				"FWV:0x%" PRIx64,
-				port, info.vendor_id, info.product_id,
-				info.device_id, info.fw_version_number);
-		}
-	}
-#endif
-
-#ifdef CONFIG_USB_PD_REV30
-	/* Set Revision to highest */
-	pd[port].rev = PD_REV30;
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If VBUS is high, then initialize flag for VBUS has always been
-	 * present. This flag is used to maintain a PD connection after a
-	 * reset by sending a soft reset.
-	 */
-	pd[port].flags |=
-		pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW : 0;
-#endif
-
-	/* Disable TCPC RX until connection is established */
-	tcpm_set_rx_enable(port, 0);
-
-#ifdef CONFIG_USBC_SS_MUX
-	/* Initialize USB mux to its default state */
-	usb_mux_init(port);
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If there's an explicit contract in place, let's restore the data and
-	 * power roles such that any messages we send to the port partner will
-	 * still be valid.
-	 */
-	if (pd_comm_is_enabled(port) &&
-	    (pd_get_saved_port_flags(port, &saved_flgs) == EC_SUCCESS) &&
-	    (saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT)) {
-		/* Only attempt to maintain previous sink contracts */
-		if ((saved_flgs & PD_BBRMFLG_POWER_ROLE) == PD_ROLE_SINK) {
-			pd_set_power_role(port,
-					  (saved_flgs & PD_BBRMFLG_POWER_ROLE) ?
-					  PD_ROLE_SOURCE : PD_ROLE_SINK);
-			pd_set_data_role(port,
-					 (saved_flgs & PD_BBRMFLG_DATA_ROLE) ?
-					 PD_ROLE_DFP : PD_ROLE_UFP);
-#ifdef CONFIG_USBC_VCONN
-			pd_set_vconn_role(port,
-					  (saved_flgs & PD_BBRMFLG_VCONN_ROLE) ?
-					  PD_ROLE_VCONN_ON : PD_ROLE_VCONN_OFF);
-#endif /* CONFIG_USBC_VCONN */
-
-			/*
-			 * Since there is an explicit contract in place, let's
-			 * issue a SoftReset such that we can renegotiate with
-			 * our port partner in order to synchronize our state
-			 * machines.
-			 */
-			this_state = PD_STATE_SOFT_RESET;
-
-			/*
-			 * Re-discover any alternate modes we may have been
-			 * using with this port partner.
-			 */
-			pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
-		} else {
-			/*
-			 * Vbus was turned off during the power supply reset
-			 * earlier, so clear the contract flag and re-start as
-			 * default role
-			 */
-			pd_update_saved_port_flags(port,
-					PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
-
-		}
-		/*
-		 * Set the TCPC reset event such that we can set our CC
-		 * terminations, determine polarity, and enable RX so we
-		 * can hear back from our port partner if maintaining our old
-		 * connection.
-		 */
-		task_set_event(task_get_current(), PD_EVENT_TCPC_RESET);
-	}
-#endif /* defined(CONFIG_USB_PD_DUAL_ROLE) */
-	/* Set the power role if we haven't already. */
-	if (this_state != PD_STATE_SOFT_RESET)
-		pd_set_power_role(port, PD_ROLE_DEFAULT(port));
-
-	/* Initialize PD protocol state variables for each port. */
-	pd[port].vdm_state = VDM_STATE_DONE;
-	set_state(port, this_state);
-	tcpm_select_rp_value(port, CONFIG_USB_PD_PULLUP);
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	/*
-	 * If we're not in an explicit contract, set our terminations to match
-	 * our default power role.
-	 */
-	if (!(saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT))
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-		tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-			    TYPEC_CC_RP : TYPEC_CC_RD);
-
-#ifdef CONFIG_USBC_PPC
-	/*
-	 * Wait to initialize the PPC after setting the correct Rd values in
-	 * the TCPC otherwise the TCPC might not be pulling the CC lines down
-	 * when the PPC connects the CC lines from the USB connector to the
-	 * TCPC cause the source to drop Vbus causing a brown out.
-	 */
-	ppc_init(port);
-#endif
-
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	/* Initialize PD Policy engine */
-	pd_dfp_discovery_init(port);
-	pd_dfp_mode_init(port);
-#endif
-
-#ifdef CONFIG_CHARGE_MANAGER
-	/* Initialize PD and type-C supplier current limits to 0 */
-	pd_set_input_current_limit(port, 0, 0);
-	typec_set_input_current_limit(port, 0, 0);
-	charge_manager_update_dualrole(port, CAP_UNKNOWN);
-#endif
-
-	/*
-	 * Since most boards configure the TCPC interrupt as edge
-	 * and it is possible that the interrupt line was asserted between init
-	 * and calling set_state, we need to process any pending interrupts now.
-	 * Otherwise future interrupts will never fire because another edge
-	 * never happens. Note this needs to happen after set_state() is called.
-	 */
-	if (IS_ENABLED(CONFIG_HAS_TASK_PD_INT))
-		schedule_deferred_pd_interrupt(port);
-
-	while (1) {
-		/* process VDM messages last */
-		pd_vdm_send_state_machine(port);
-
-		/* Verify board specific health status : current, voltages... */
-		res = pd_board_checks();
-		if (res != EC_SUCCESS) {
-			/* cut the power */
-			pd_execute_hard_reset(port);
-			/* notify the other side of the issue */
-			pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL,
-				    AMS_START);
-		}
-
-		/* wait for next event/packet or timeout expiration */
-		evt = task_wait_event(timeout);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-		if (evt & (PD_EXIT_LOW_POWER_EVENT_MASK | TASK_EVENT_WAKE))
-			exit_low_power_mode(port);
-		if (evt & PD_EVENT_DEVICE_ACCESSED)
-			handle_device_access(port);
-#endif
-#ifdef CONFIG_POWER_COMMON
-		if (evt & PD_EVENT_POWER_STATE_CHANGE)
-			handle_new_power_state(port);
-#endif
-
-#if defined(CONFIG_USB_PD_ALT_MODE_DFP)
-		if (evt & PD_EVENT_SYSJUMP) {
-			exit_supported_alt_mode(port);
-			notify_sysjump_ready();
-		}
-#endif
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		if (evt & PD_EVENT_UPDATE_DUAL_ROLE)
-			pd_update_dual_role_config(port);
-#endif
-
-#ifdef CONFIG_USB_PD_TCPC
-		/*
-		 * run port controller task to check CC and/or read incoming
-		 * messages
-		 */
-		tcpc_run(port, evt);
-#else
-		/* if TCPC has reset, then need to initialize it again */
-		if (evt & PD_EVENT_TCPC_RESET) {
-			reset_device_and_notify(port);
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-		}
-
-		if ((evt & PD_EVENT_TCPC_RESET) &&
-		    (pd[port].task_state != PD_STATE_DRP_AUTO_TOGGLE)) {
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-			if (pd[port].task_state == PD_STATE_SOFT_RESET) {
-				enum tcpc_cc_voltage_status cc1, cc2;
-
-				/*
-				 * Set the terminations to match our power
-				 * role.
-				 */
-				tcpm_set_cc(port, pd[port].power_role ?
-					    TYPEC_CC_RP : TYPEC_CC_RD);
-
-				/* Determine the polarity. */
-				tcpm_get_cc(port, &cc1, &cc2);
-				if (pd[port].power_role == PD_ROLE_SINK) {
-					pd[port].polarity =
-						get_snk_polarity(cc1, cc2);
-				} else if (cc_is_snk_dbg_acc(cc1, cc2)) {
-					pd[port].polarity =
-						board_get_src_dts_polarity(
-								port);
-				} else {
-					pd[port].polarity =
-						get_src_polarity(cc1, cc2);
-				}
-			} else
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-			{
-				/* Ensure CC termination is default */
-				tcpm_set_cc(port, PD_ROLE_DEFAULT(port) ==
-					    PD_ROLE_SOURCE ? TYPEC_CC_RP :
-					    TYPEC_CC_RD);
-			}
-
-			/*
-			 * If we have a stable contract in the default role,
-			 * then simply update TCPC with some missing info
-			 * so that we can continue without resetting PD comms.
-			 * Otherwise, go to the default disconnected state
-			 * and force renegotiation.
-			 */
-			if (pd[port].vdm_state == VDM_STATE_DONE && (
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK &&
-			     pd[port].task_state == PD_STATE_SNK_READY) ||
-			     (pd[port].task_state == PD_STATE_SOFT_RESET) ||
-#endif
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE &&
-			     pd[port].task_state == PD_STATE_SRC_READY))) {
-				pd_set_polarity(port, pd[port].polarity);
-				tcpm_set_msg_header(port, pd[port].power_role,
-						    pd[port].data_role);
-				tcpm_set_rx_enable(port, 1);
-			} else {
-				/* Ensure state variables are at default */
-				pd_set_power_role(port, PD_ROLE_DEFAULT(port));
-				pd[port].vdm_state = VDM_STATE_DONE;
-				set_state(port, PD_DEFAULT_STATE(port));
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-				pd_update_dual_role_config(port);
-#endif
-			}
-		}
-#endif
-
-#ifdef CONFIG_USBC_PPC
-		/*
-		 * TODO: Useful for non-PPC cases as well, but only needed
-		 * for PPC cases right now. Revisit later.
-		 */
-		if (evt & PD_EVENT_SEND_HARD_RESET)
-			set_state(port, PD_STATE_HARD_RESET_SEND);
-#endif /* defined(CONFIG_USBC_PPC) */
-
-		if (evt & PD_EVENT_RX_HARD_RESET)
-			pd_execute_hard_reset(port);
-
-		/* process any potential incoming message */
-		incoming_packet = tcpm_has_pending_message(port);
-		if (incoming_packet) {
-			/* Dequeue and consume duplicate message ID. */
-			if (tcpm_dequeue_message(port, payload, &head) ==
-								EC_SUCCESS
-			    && !consume_repeat_message(port, head)
-			   )
-				handle_request(port, head, payload);
-
-			/* Check if there are any more messages */
-			if (tcpm_has_pending_message(port))
-				task_set_event(PD_PORT_TO_TASK_ID(port),
-					       TASK_EVENT_WAKE);
-		}
-
-		if (pd[port].req_suspend_state)
-			set_state(port, PD_STATE_SUSPENDED);
-
-		/* if nothing to do, verify the state of the world in 500ms */
-		this_state = pd[port].task_state;
-		timeout = 500*MSEC;
-		switch (this_state) {
-		case PD_STATE_DISABLED:
-			/* Nothing to do */
-			break;
-		case PD_STATE_SRC_DISCONNECTED:
-			timeout = 10*MSEC;
-			pd_set_src_caps(port, 0, NULL);
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-			/*
-			 * If SW decided we should be in a low power state and
-			 * the CC lines did not change, then don't talk with the
-			 * TCPC otherwise we might wake it up.
-			 */
-			if (pd[port].flags & PD_FLAGS_LPM_REQUESTED &&
-			    !(evt & PD_EVENT_CC))
-				break;
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-			tcpm_get_cc(port, &cc1, &cc2);
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-			/*
-			 * Attempt TCPC auto DRP toggle if it is
-			 * not already auto toggling and not try.src
-			 */
-			if (auto_toggle_supported &&
-			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2)) {
-				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
-				break;
-			}
-#endif
-			/*
-			 * Transition to DEBOUNCE if we detect appropriate
-			 * signals
-			 *
-			 * (from 4.5.2.2.10.2 Exiting from Try.SRC State)
-			 * If try_src -and-
-			 *    have only one Rd (not both) => DEBOUNCE
-			 *
-			 * (from 4.5.2.2.7.2 Exiting from Unattached.SRC State)
-			 * If not try_src -and-
-			 *    have at least one Rd => DEBOUNCE -or-
-			 *    have audio access => DEBOUNCE
-			 *
-			 * try_src should not exit if both pins are Rd
-			 */
-			if ((is_try_src(port) && cc_is_only_one_rd(cc1, cc2)) ||
-			    (!is_try_src(port) &&
-			     (cc_is_at_least_one_rd(cc1, cc2) ||
-			      cc_is_audio_acc(cc1, cc2)))) {
-#ifdef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
-				/* Enable VBUS */
-				if (pd_set_power_supply_ready(port))
-					break;
-#endif
-				pd[port].cc_state = PD_CC_NONE;
-				set_state(port,
-					PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
-				break;
-			}
-#if defined(CONFIG_USB_PD_DUAL_ROLE)
-			now = get_time();
-			/*
-			 * Try.SRC state is embedded here. The port
-			 * shall transition to TryWait.SNK after
-			 * tDRPTry (PD_T_DRP_TRY) and Vbus is within
-			 * vSafe0V, or after tTryTimeout
-			 * (PD_T_TRY_TIMEOUT). Otherwise we should stay
-			 * within Try.SRC (break).
-			 */
-			if (is_try_src(port)) {
-				if (now.val < pd[port].try_src_marker) {
-					break;
-				} else if (now.val < pd[port].try_timeout) {
-					if (pd_is_vbus_present(port))
-						break;
-				}
-
-				/*
-				 * Transition to TryWait.SNK now, so set
-				 * state and update src marker time.
-				 */
-				set_state(port, PD_STATE_SNK_DISCONNECTED);
-				pd_set_power_role(port, PD_ROLE_SINK);
-				tcpm_set_cc(port, TYPEC_CC_RD);
-				pd[port].try_src_marker =
-					get_time().val + PD_T_DEBOUNCE;
-				timeout = 2 * MSEC;
-				break;
-			}
-
-			/*
-			 * If Try.SRC state is not active, then handle
-			 * the normal DRP toggle from SRC->SNK.
-			 */
-			if (now.val < next_role_swap ||
-			    drp_state[port] == PD_DRP_FORCE_SOURCE ||
-			    drp_state[port] == PD_DRP_FREEZE)
-				break;
-
-			/*
-			 * Transition to SNK now, so set state and
-			 * update next role swap time.
-			 */
-			set_state(port, PD_STATE_SNK_DISCONNECTED);
-			pd_set_power_role(port, PD_ROLE_SINK);
-			tcpm_set_cc(port, TYPEC_CC_RD);
-			next_role_swap = get_time().val + PD_T_DRP_SNK;
-			/* Swap states quickly */
-			timeout = 2 * MSEC;
-#endif
-			break;
-		case PD_STATE_SRC_DISCONNECTED_DEBOUNCE:
-			timeout = 20*MSEC;
-			tcpm_get_cc(port, &cc1, &cc2);
-
-			if (cc_is_snk_dbg_acc(cc1, cc2)) {
-				/* Debug accessory */
-				new_cc_state = PD_CC_UFP_DEBUG_ACC;
-			} else if (cc_is_at_least_one_rd(cc1, cc2)) {
-				/* UFP attached */
-				new_cc_state = PD_CC_UFP_ATTACHED;
-			} else if (cc_is_audio_acc(cc1, cc2)) {
-				/* Audio accessory */
-				new_cc_state = PD_CC_UFP_AUDIO_ACC;
-			} else {
-				/* No UFP */
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				timeout = 5*MSEC;
-				break;
-			}
-
-			/* Set debounce timer */
-			if (new_cc_state != pd[port].cc_state) {
-				pd[port].cc_debounce =
-					get_time().val +
-					(is_try_src(port) ? PD_T_DEBOUNCE
-							  : PD_T_CC_DEBOUNCE);
-				pd[port].cc_state = new_cc_state;
-				break;
-			}
-
-			/* Debounce the cc state */
-			if (get_time().val < pd[port].cc_debounce)
-				break;
-
-			/* Debounce complete */
-			if (IS_ENABLED(CONFIG_COMMON_RUNTIME))
-				hook_notify(HOOK_USB_PD_CONNECT);
-
-#ifdef CONFIG_USBC_PPC
-			/*
-			 * If the port is latched off, just continue to
-			 * monitor for a detach.
-			 */
-			if (usbc_ocp_is_port_latched_off(port))
-				break;
-#endif /* CONFIG_USBC_PPC */
-
-			/* UFP is attached */
-			if (new_cc_state == PD_CC_UFP_ATTACHED ||
-			    new_cc_state == PD_CC_UFP_DEBUG_ACC) {
-#ifdef CONFIG_USBC_PPC
-				/* Inform PPC that a sink is connected. */
-				ppc_dev_is_connected(port, PPC_DEV_SNK);
-#endif /* CONFIG_USBC_PPC */
-				if (IS_ENABLED(CONFIG_USBC_OCP))
-					usbc_ocp_snk_is_connected(port, true);
-				if (new_cc_state == PD_CC_UFP_DEBUG_ACC) {
-					pd[port].polarity =
-						board_get_src_dts_polarity(
-							port);
-				} else {
-					pd[port].polarity =
-						get_src_polarity(cc1, cc2);
-				}
-				pd_set_polarity(port, pd[port].polarity);
-
-				/* initial data role for source is DFP */
-				pd_set_data_role(port, PD_ROLE_DFP);
-
-				/* Enable Auto Discharge Disconnect */
-				tcpm_enable_auto_discharge_disconnect(port, 1);
-
-				if (new_cc_state == PD_CC_UFP_DEBUG_ACC)
-					pd[port].flags |=
-						PD_FLAGS_TS_DTS_PARTNER;
-
-#ifdef CONFIG_USBC_VCONN
-				/*
-				 * Do not source Vconn when debug accessory is
-				 * detected. Section 4.5.2.2.17.1 in USB spec
-				 * v1-3
-				 */
-				if (new_cc_state != PD_CC_UFP_DEBUG_ACC) {
-					/*
-					 * Start sourcing Vconn before Vbus to
-					 * ensure we are within USB Type-C
-					 * Spec 1.3 tVconnON.
-					 */
-					set_vconn(port, 1);
-					pd_set_vconn_role(port,
-							  PD_ROLE_VCONN_ON);
-				}
-#endif
-
-#ifndef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
-				/* Enable VBUS */
-				if (pd_set_power_supply_ready(port)) {
-#ifdef CONFIG_USBC_VCONN
-					/* Stop sourcing Vconn if Vbus failed */
-					set_vconn(port, 0);
-					pd_set_vconn_role(port,
-							  PD_ROLE_VCONN_OFF);
-#endif /* CONFIG_USBC_VCONN */
-#ifdef CONFIG_USBC_SS_MUX
-					usb_mux_set(port, USB_PD_MUX_NONE,
-						    USB_SWITCH_DISCONNECT,
-						    pd[port].polarity);
-#endif /* CONFIG_USBC_SS_MUX */
-					break;
-				}
-				/*
-				 * Set correct Rp value determined during
-				 * pd_set_power_supply_ready.  This should be
-				 * safe because Vconn is being sourced,
-				 * preventing incorrect CCD detection.
-				 */
-				tcpm_set_cc(port, TYPEC_CC_RP);
-#endif /* CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP */
-				/* If PD comm is enabled, enable TCPC RX */
-				if (pd_comm_is_enabled(port))
-					tcpm_set_rx_enable(port, 1);
-
-				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
-						  PD_FLAGS_CHECK_DR_ROLE;
-				hard_reset_count = 0;
-				timeout = 5*MSEC;
-
-				set_state(port, PD_STATE_SRC_STARTUP);
-			}
-			/*
-			 * AUDIO_ACC will remain in this state indefinitely
-			 * until disconnect.
-			 */
-			break;
-		case PD_STATE_SRC_HARD_RESET_RECOVER:
-			/* Do not continue until hard reset recovery time */
-			if (get_time().val < pd[port].src_recover) {
-				timeout = 50*MSEC;
-				break;
-			}
-
-#ifdef CONFIG_USBC_VCONN
-			/*
-			 * Start sourcing Vconn again and set the flag, in case
-			 * it was 0 due to a previous swap
-			 */
-			set_vconn(port, 1);
-			pd_set_vconn_role(port, PD_ROLE_VCONN_ON);
-#endif
-
-			/* Enable VBUS */
-			timeout = 10*MSEC;
-			if (pd_set_power_supply_ready(port)) {
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				break;
-			}
-#if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB)
-			/*
-			 * After transmitting hard reset, TCPM writes
-			 * to RECEIVE_DETECT register to enable
-			 * PD message passing.
-			 */
-			if (pd_comm_is_enabled(port))
-				tcpm_set_rx_enable(port, 1);
-#endif /* CONFIG_USB_PD_TCPM_TCPCI  || CONFIG_USB_PD_TCPM_STUB */
-
-			pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
-					  PD_FLAGS_CHECK_DR_ROLE;
-			set_state(port, PD_STATE_SRC_STARTUP);
-			break;
-		case PD_STATE_SRC_STARTUP:
-			/* Reset cable attributes and flags */
-			reset_pd_cable(port);
-			/* Wait for power source to enable */
-			if (pd[port].last_state != pd[port].task_state) {
-				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
-				/* reset various counters */
-				caps_count = 0;
-				pd[port].msg_id = 0;
-				snk_cap_count = 0;
-				set_state_timeout(
-					port,
-#ifdef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
-					/*
-					 * delay for power supply to start up.
-					 * subtract out debounce time if coming
-					 * from debounce state since vbus is
-					 * on during debounce.
-					 */
-					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY -
-					  (pd[port].last_state ==
-					   PD_STATE_SRC_DISCONNECTED_DEBOUNCE
-						? PD_T_CC_DEBOUNCE : 0),
-#else
-					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
-#endif
-					PD_STATE_SRC_DISCOVERY);
-			}
-			break;
-		case PD_STATE_SRC_DISCOVERY:
-			now = get_time();
-			if (pd[port].last_state != pd[port].task_state) {
-				caps_count = 0;
-				next_src_cap = now.val;
-				/*
-				 * If we have had PD connection with this port
-				 * partner, then start NoResponseTimer.
-				 */
-				if (pd_capable(port))
-					set_state_timeout(port,
-						get_time().val +
-						PD_T_NO_RESPONSE,
-						hard_reset_count <
-						  PD_HARD_RESET_COUNT ?
-						    PD_STATE_HARD_RESET_SEND :
-						    PD_STATE_SRC_DISCONNECTED);
-			}
-
-			/* Send source cap some minimum number of times */
-			if (caps_count < PD_CAPS_COUNT  &&
-						next_src_cap <= now.val) {
-				/* Query capabilities of the other side */
-				res = send_source_cap(port, AMS_START);
-				/* packet was acked => PD capable device) */
-				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
-					timeout = 10*MSEC;
-					hard_reset_count = 0;
-					caps_count = 0;
-					/* Port partner is PD capable */
-					pd[port].flags |=
-						PD_FLAGS_PREVIOUS_PD_CONN;
-				} else { /* failed, retry later */
-					timeout = PD_T_SEND_SOURCE_CAP;
-					next_src_cap = now.val +
-							PD_T_SEND_SOURCE_CAP;
-					caps_count++;
-				}
-			} else if (caps_count < PD_CAPS_COUNT) {
-				timeout = next_src_cap - now.val;
-			}
-			break;
-		case PD_STATE_SRC_NEGOCIATE:
-			/* wait for a "Request" message */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  PD_STATE_HARD_RESET_SEND);
-			break;
-		case PD_STATE_SRC_ACCEPTED:
-			/* Accept sent, wait for enabling the new voltage */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(
-					port,
-					get_time().val +
-					PD_T_SINK_TRANSITION,
-					PD_STATE_SRC_POWERED);
-			break;
-		case PD_STATE_SRC_POWERED:
-			/* Switch to the new requested voltage */
-			if (pd[port].last_state != pd[port].task_state) {
-				pd[port].flags |= PD_FLAGS_CHECK_VCONN_STATE;
-				pd_transition_voltage(pd[port].requested_idx);
-				set_state_timeout(
-					port,
-					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
-					PD_STATE_SRC_TRANSITION);
-			}
-			break;
-		case PD_STATE_SRC_TRANSITION:
-			/* the voltage output is good, notify the source */
-			res = send_control(port, PD_CTRL_PS_RDY);
-			if (res >= 0) {
-				timeout = 10*MSEC;
-
-				/*
-				 * Give the sink some time to send any messages
-				 * before we may send messages of our own.  Add
-				 * some jitter of up to ~192ms, to prevent
-				 * multiple collisions. This delay also allows
-				 * the sink device to request power role swap
-				 * and allow the the accept message to be sent
-				 * prior to CMD_DISCOVER_IDENT being sent in the
-				 * SRC_READY state.
-				 */
-				pd[port].ready_state_holdoff_timer =
-					get_time().val + SRC_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
-
-				/* it's time to ping regularly the sink */
-				set_state(port, PD_STATE_SRC_READY);
-			} else {
-				/* The sink did not ack, cut the power... */
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-			}
-			break;
-		case PD_STATE_SRC_READY:
-			timeout = PD_T_SOURCE_ACTIVITY;
-
-			/*
-			 * Don't send any traffic yet until our holdoff timer
-			 * has expired.  Some devices are chatty once we reach
-			 * the SRC_READY state and we may end up in a collision
-			 * of messages if we try to immediately send our
-			 * interrogations.
-			 */
-			if (get_time().val <=
-			    pd[port].ready_state_holdoff_timer)
-				break;
-
-			/*
-			 * Don't send any PD traffic if we woke up due to
-			 * incoming packet or if VDO response pending to avoid
-			 * collisions.
-			 */
-			if (incoming_packet ||
-			    (pd[port].vdm_state == VDM_STATE_BUSY))
-				break;
-
-			/* Send updated source capabilities to our partner */
-			if (pd[port].flags & PD_FLAGS_UPDATE_SRC_CAPS) {
-				res = send_source_cap(port, AMS_START);
-				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
-					pd[port].flags &=
-						~PD_FLAGS_UPDATE_SRC_CAPS;
-				}
-				break;
-			}
-
-			/* Send get sink cap if haven't received it yet */
-			if (!(pd[port].flags & PD_FLAGS_SNK_CAP_RECVD)) {
-				if (++snk_cap_count <= PD_SNK_CAP_RETRIES) {
-					/* Get sink cap to know if dual-role device */
-					send_control(port, PD_CTRL_GET_SINK_CAP);
-					set_state(port, PD_STATE_SRC_GET_SINK_CAP);
-					break;
-				} else if (debug_level >= 2 &&
-					   snk_cap_count == PD_SNK_CAP_RETRIES+1) {
-					CPRINTF("C%d ERR SNK_CAP\n", port);
-				}
-			}
-
-			/* Check power role policy, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_PR_ROLE) {
-				pd_check_pr_role(port, PD_ROLE_SOURCE,
-						 pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
-			}
-
-
-			/* Check data role policy, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_DR_ROLE) {
-				pd_check_dr_role(port, pd[port].data_role,
-						 pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_DR_ROLE;
-				break;
-			}
-
-			/* Check for Vconn source, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_VCONN_STATE) {
-				/*
-				 * Ref: Section 2.6.1 of both
-				 * USB-PD Spec Revision 2.0, Version 1.3 &
-				 * USB-PD Spec Revision 3.0, Version 2.0
-				 * During Explicit contract the Sink can
-				 * initiate or receive a request an exchange
-				 * of VCONN Source.
-				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
-				break;
-			}
-
-			/* Send discovery SVDMs last */
-			if (pd[port].data_role == PD_ROLE_DFP &&
-			    (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
-#ifndef CONFIG_USB_PD_SIMPLE_DFP
-				pd_send_vdm(port, USB_SID_PD,
-					    CMD_DISCOVER_IDENT, NULL, 0);
-#endif
-				pd[port].flags &= ~PD_FLAGS_CHECK_IDENTITY;
-				break;
-			}
-
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
-			if (!(pd[port].flags & PD_FLAGS_PING_ENABLED))
-				break;
-
-			/* Verify that the sink is alive */
-			res = send_control(port, PD_CTRL_PING);
-			if (res >= 0)
-				break;
-
-			/* Ping dropped. Try soft reset. */
-			set_state(port, PD_STATE_SOFT_RESET);
-			timeout = 10 * MSEC;
-			break;
-		case PD_STATE_SRC_GET_SINK_CAP:
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  PD_STATE_SRC_READY);
-			break;
-		case PD_STATE_DR_SWAP:
-			if (pd[port].last_state != pd[port].task_state) {
-				res = send_control(port, PD_CTRL_DR_SWAP);
-				if (res < 0) {
-					timeout = 10*MSEC;
-					/*
-					 * If failed to get goodCRC, send
-					 * soft reset, otherwise ignore
-					 * failure.
-					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
-					break;
-				}
-				/* Wait for accept or reject */
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  READY_RETURN_STATE(port));
-			}
-			break;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		case PD_STATE_SRC_SWAP_INIT:
-			if (pd[port].last_state != pd[port].task_state) {
-				res = send_control(port, PD_CTRL_PR_SWAP);
-				if (res < 0) {
-					timeout = 10*MSEC;
-					/*
-					 * If failed to get goodCRC, send
-					 * soft reset, otherwise ignore
-					 * failure.
-					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SRC_READY);
-					break;
-				}
-				/* Wait for accept or reject */
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  PD_STATE_SRC_READY);
-			}
-			break;
-		case PD_STATE_SRC_SWAP_SNK_DISABLE:
-			/* Give time for sink to stop drawing current */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_TRANSITION,
-						  PD_STATE_SRC_SWAP_SRC_DISABLE);
-			break;
-		case PD_STATE_SRC_SWAP_SRC_DISABLE:
-			if (pd[port].last_state != pd[port].task_state) {
-				/* Turn power off */
-				pd_power_supply_reset(port);
-
-				/*
-				 * Switch to Rd and swap roles to sink
-				 *
-				 * The reason we do this as early as possible is
-				 * to help prevent CC disconnection cases where
-				 * both partners are applying an Rp.  Certain PD
-				 * stacks (e.g. qualcomm), reflexively apply
-				 * their Rp once VBUS falls beneath
-				 * ~3.67V. (b/77827528).
-				 */
-				tcpm_set_cc(port, TYPEC_CC_RD);
-				pd_set_power_role(port, PD_ROLE_SINK);
-
-				/* Inform TCPC of power role update. */
-				pd_update_roles(port);
-
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_POWER_SUPPLY_TURN_OFF_DELAY,
-						  PD_STATE_SRC_SWAP_STANDBY);
-			}
-			break;
-		case PD_STATE_SRC_SWAP_STANDBY:
-			/* Send PS_RDY to let sink know our power is off */
-			if (pd[port].last_state != pd[port].task_state) {
-				/* Send PS_RDY */
-				res = send_control(port, PD_CTRL_PS_RDY);
-				if (res < 0) {
-					timeout = 10*MSEC;
-					set_state(port,
-						  PD_STATE_SRC_DISCONNECTED);
-					break;
-				}
-				/* Wait for PS_RDY from new source */
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_PS_SOURCE_ON,
-						  PD_STATE_SNK_DISCONNECTED);
-			}
-			break;
-		case PD_STATE_SUSPENDED: {
-#ifndef CONFIG_USB_PD_TCPC
-			int rstatus;
-#endif
-			tcpc_prints("suspended!", port);
-			pd[port].req_suspend_state = 0;
-#ifdef CONFIG_USB_PD_TCPC
-			pd_rx_disable_monitoring(port);
-			pd_hw_release(port);
-			pd_power_supply_reset(port);
-#else
-			pd_power_supply_reset(port);
-#ifdef CONFIG_USBC_VCONN
-			set_vconn(port, 0);
-#endif
-			rstatus = tcpm_release(port);
-			if (rstatus != 0 && rstatus != EC_ERROR_UNIMPLEMENTED)
-				tcpc_prints("release failed!", port);
-#endif
-			/* Drain any outstanding software message queues. */
-			tcpm_clear_pending_messages(port);
-
-			/* Wait for resume */
-			while (pd[port].task_state == PD_STATE_SUSPENDED) {
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-				int evt = task_wait_event(-1);
-
-				if (evt & PD_EVENT_SYSJUMP)
-					/* Nothing to do for sysjump prep */
-					notify_sysjump_ready();
-#else
-				task_wait_event(-1);
-#endif
-			}
-#ifdef CONFIG_USB_PD_TCPC
-			pd_hw_init(port, PD_ROLE_DEFAULT(port));
-			tcpc_prints("resumed!", port);
-#else
-			if (rstatus != EC_ERROR_UNIMPLEMENTED &&
-			    pd_restart_tcpc(port) != 0) {
-				/* stay in PD_STATE_SUSPENDED */
-				tcpc_prints("restart failed!", port);
-				break;
-			}
-			/* Set the CC termination and state back to default */
-			tcpm_set_cc(port,
-				    PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-					TYPEC_CC_RP :
-					TYPEC_CC_RD);
-			set_state(port, PD_DEFAULT_STATE(port));
-			tcpc_prints("resumed!", port);
-#endif
-			break;
-		}
-		case PD_STATE_SNK_DISCONNECTED:
-#ifdef CONFIG_USB_PD_LOW_POWER
-			timeout = (drp_state[port] !=
-				PD_DRP_TOGGLE_ON ? SECOND : 10*MSEC);
-#else
-			timeout = 10*MSEC;
-#endif
-			pd_set_src_caps(port, 0, NULL);
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-			/*
-			 * If SW decided we should be in a low power state and
-			 * the CC lines did not change, then don't talk with the
-			 * TCPC otherwise we might wake it up.
-			 */
-			if (pd[port].flags & PD_FLAGS_LPM_REQUESTED &&
-			    !(evt & PD_EVENT_CC))
-				break;
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-			tcpm_get_cc(port, &cc1, &cc2);
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-			/*
-			 * Attempt TCPC auto DRP toggle if it is not already
-			 * auto toggling and not try.src, and dual role toggling
-			 * is allowed.
-			 */
-			if (auto_toggle_supported &&
-			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2) &&
-				(drp_state[port] == PD_DRP_TOGGLE_ON)) {
-				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
-				break;
-			}
-#endif
-
-			/* Source connection monitoring */
-			if (!cc_is_open(cc1, cc2)) {
-				pd[port].cc_state = PD_CC_NONE;
-				hard_reset_count = 0;
-				new_cc_state = PD_CC_NONE;
-				pd[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
-				set_state(port,
-					PD_STATE_SNK_DISCONNECTED_DEBOUNCE);
-				timeout = 10*MSEC;
-				break;
-			}
-
-			/*
-			 * If Try.SRC is active and failed to detect a SNK,
-			 * then it transitions to TryWait.SNK. Need to prevent
-			 * normal dual role toggle until tDRPTryWait timer
-			 * expires.
-			 */
-			if (pd[port].flags & PD_FLAGS_TRY_SRC) {
-				if (get_time().val > pd[port].try_src_marker)
-					pd[port].flags &= ~PD_FLAGS_TRY_SRC;
-				break;
-			}
-
-			/* If no source detected, check for role toggle. */
-			if (drp_state[port] == PD_DRP_TOGGLE_ON &&
-			    get_time().val >= next_role_swap) {
-				/* Swap roles to source */
-				pd_set_power_role(port, PD_ROLE_SOURCE);
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				tcpm_set_cc(port, TYPEC_CC_RP);
-				next_role_swap = get_time().val + PD_T_DRP_SRC;
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-				/*
-				 * Clear low power mode flag as we are swapping
-				 * states quickly.
-				 */
-				pd[port].flags &= ~PD_FLAGS_LPM_REQUESTED;
-#endif
-
-				/* Swap states quickly */
-				timeout = 2*MSEC;
-				break;
-			}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-			/*
-			 * If we are remaining in the SNK_DISCONNECTED state,
-			 * let's go into low power mode and wait for a change on
-			 * CC status.
-			 */
-			pd[port].flags |= PD_FLAGS_LPM_REQUESTED;
-#endif/* CONFIG_USB_PD_TCPC_LOW_POWER */
-			break;
-
-		case PD_STATE_SNK_DISCONNECTED_DEBOUNCE:
-			tcpm_get_cc(port, &cc1, &cc2);
-
-			if (cc_is_rp(cc1) && cc_is_rp(cc2)) {
-				/* Debug accessory */
-				new_cc_state = PD_CC_DFP_DEBUG_ACC;
-			} else if (cc_is_rp(cc1) || cc_is_rp(cc2)) {
-				new_cc_state = PD_CC_DFP_ATTACHED;
-			} else {
-				/* No connection any more */
-				set_state(port, PD_STATE_SNK_DISCONNECTED);
-				timeout = 5*MSEC;
-				break;
-			}
-
-			timeout = 20*MSEC;
-
-			/* Debounce the cc state */
-			if (new_cc_state != pd[port].cc_state) {
-				pd[port].cc_debounce = get_time().val +
-					PD_T_CC_DEBOUNCE;
-				pd[port].cc_state = new_cc_state;
-				break;
-			}
-			/* Wait for CC debounce and VBUS present */
-			if (get_time().val < pd[port].cc_debounce ||
-			    !pd_is_vbus_present(port))
-				break;
-
-			if (pd_try_src_enable &&
-			    !(pd[port].flags & PD_FLAGS_TRY_SRC)) {
-				/*
-				 * If TRY_SRC is enabled, but not active,
-				 * then force attempt to connect as source.
-				 */
-				pd[port].try_src_marker = get_time().val
-					+ PD_T_DRP_TRY;
-				pd[port].try_timeout = get_time().val
-					+ PD_T_TRY_TIMEOUT;
-				/* Swap roles to source */
-				pd_set_power_role(port, PD_ROLE_SOURCE);
-				tcpm_set_cc(port, TYPEC_CC_RP);
-				timeout = 2*MSEC;
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				/* Set flag after the state change */
-				pd[port].flags |= PD_FLAGS_TRY_SRC;
-				break;
-			}
-
-			/* We are attached */
-			if (IS_ENABLED(CONFIG_COMMON_RUNTIME))
-				hook_notify(HOOK_USB_PD_CONNECT);
-			pd[port].polarity = get_snk_polarity(cc1, cc2);
-			pd_set_polarity(port, pd[port].polarity);
-			/* reset message ID  on connection */
-			pd[port].msg_id = 0;
-			/* initial data role for sink is UFP */
-			pd_set_data_role(port, PD_ROLE_UFP);
-			/* Enable Auto Discharge Disconnect */
-			tcpm_enable_auto_discharge_disconnect(port, 1);
-#if defined(CONFIG_CHARGE_MANAGER)
-			typec_curr = usb_get_typec_current_limit(
-				pd[port].polarity, cc1, cc2);
-			typec_set_input_current_limit(
-				port, typec_curr, TYPE_C_VOLTAGE);
-#endif
-
-#ifdef CONFIG_USBC_PPC
-			/* Inform PPC that a source is connected. */
-			ppc_dev_is_connected(port, PPC_DEV_SRC);
-#endif /* CONFIG_USBC_PPC */
-			if (IS_ENABLED(CONFIG_USBC_OCP))
-				usbc_ocp_snk_is_connected(port, false);
-
-			/* If PD comm is enabled, enable TCPC RX */
-			if (pd_comm_is_enabled(port))
-				tcpm_set_rx_enable(port, 1);
-
-			/* DFP is attached */
-			if (new_cc_state == PD_CC_DFP_ATTACHED ||
-			    new_cc_state == PD_CC_DFP_DEBUG_ACC) {
-				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
-						  PD_FLAGS_CHECK_DR_ROLE |
-						  PD_FLAGS_CHECK_IDENTITY;
-				/* Reset cable attributes and flags */
-				reset_pd_cable(port);
-
-				if (new_cc_state == PD_CC_DFP_DEBUG_ACC)
-					pd[port].flags |=
-						PD_FLAGS_TS_DTS_PARTNER;
-				set_state(port, PD_STATE_SNK_DISCOVERY);
-				timeout = 10*MSEC;
-				hook_call_deferred(
-					&pd_usb_billboard_deferred_data,
-					PD_T_AME);
-			}
-			break;
-		case PD_STATE_SNK_HARD_RESET_RECOVER:
-			if (pd[port].last_state != pd[port].task_state)
-				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
-
-			if (get_usb_pd_vbus_detect() ==
-					USB_PD_VBUS_DETECT_NONE) {
-				/*
-				 * Can't measure vbus state so this is the
-				 * maximum recovery time for the source.
-				 */
-				if (pd[port].last_state != pd[port].task_state)
-					set_state_timeout(port, get_time().val +
-						  PD_T_SAFE_0V +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
-			} else {
-#ifndef CONFIG_USB_PD_VBUS_DETECT_NONE
-				/* Wait for VBUS to go low and then high*/
-				if (pd[port].last_state !=
-						pd[port].task_state) {
-					snk_hard_reset_vbus_off = 0;
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SAFE_0V,
-						  hard_reset_count <
-						    PD_HARD_RESET_COUNT ?
-						     PD_STATE_HARD_RESET_SEND :
-						     PD_STATE_SNK_DISCOVERY);
-				}
-
-				if (!pd_is_vbus_present(port) &&
-				    !snk_hard_reset_vbus_off) {
-					/* VBUS has gone low, reset timeout */
-					snk_hard_reset_vbus_off = 1;
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
-				}
-				if (pd_is_vbus_present(port) &&
-				    snk_hard_reset_vbus_off) {
-					/* VBUS went high again */
-					set_state(port, PD_STATE_SNK_DISCOVERY);
-					timeout = 10*MSEC;
-				}
-
-				/*
-				 * Don't need to set timeout because VBUS
-				 * changing will trigger an interrupt and
-				 * wake us up.
-				 */
-#endif
-			}
-			break;
-		case PD_STATE_SNK_DISCOVERY:
-			/* Wait for source cap expired only if we are enabled */
-			if ((pd[port].last_state != pd[port].task_state)
-			    && pd_comm_is_enabled(port)) {
-#if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB)
-				/*
-				 * If we come from hard reset recover state,
-				 * then we can process the source capabilities
-				 * form partner now, so enable PHY layer
-				 * receiving function.
-				 */
-				if (pd[port].last_state ==
-				    PD_STATE_SNK_HARD_RESET_RECOVER)
-					tcpm_set_rx_enable(port, 1);
-#endif /* CONFIG_USB_PD_TCPM_TCPCI  || CONFIG_USB_PD_TCPM_STUB */
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-				/*
-				 * If the battery has not met a configured safe
-				 * level for hard resets, refrain from starting
-				 * reset timers as a hard reset could brown out
-				 * the board.  Note this may mean that
-				 * high-power chargers will stay at 15W until a
-				 * reset is sent, depending on boot timing.
-				 */
-				int batt_soc = usb_get_battery_soc();
-
-				if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
-				    battery_get_disconnect_state() !=
-						BATTERY_NOT_DISCONNECTED)
-					pd[port].flags |=
-						    PD_FLAGS_SNK_WAITING_BATT;
-				else
-					pd[port].flags &=
-						    ~PD_FLAGS_SNK_WAITING_BATT;
-#endif
-
-				if (pd[port].flags &
-						    PD_FLAGS_SNK_WAITING_BATT) {
-#ifdef CONFIG_CHARGE_MANAGER
-					/*
-					 * Configure this port as dedicated for
-					 * now, so it won't be de-selected by
-					 * the charge manager leaving safe mode.
-					 */
-					charge_manager_update_dualrole(port,
-								CAP_DEDICATED);
-#endif
-					CPRINTS("C%d: Battery low. "
-						"Hold reset timer", port);
-				/*
-				 * If VBUS has never been low, and we timeout
-				 * waiting for source cap, try a soft reset
-				 * first, in case we were already in a stable
-				 * contract before this boot.
-				 */
-				} else if (pd[port].flags &
-						PD_FLAGS_VBUS_NEVER_LOW) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_SOFT_RESET);
-				/*
-				 * If we haven't passed hard reset counter,
-				 * start SinkWaitCapTimer, otherwise start
-				 * NoResponseTimer.
-				 */
-				} else if (hard_reset_count <
-						PD_HARD_RESET_COUNT) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_HARD_RESET_SEND);
-				} else if (pd_capable(port)) {
-					/* ErrorRecovery */
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_NO_RESPONSE,
-						  PD_STATE_SNK_DISCONNECTED);
-				}
-#if defined(CONFIG_CHARGE_MANAGER)
-				/*
-				 * If we didn't come from disconnected, must
-				 * have come from some path that did not set
-				 * typec current limit. So, set to 0 so that
-				 * we guarantee this is revised below.
-				 */
-				if (pd[port].last_state !=
-				    PD_STATE_SNK_DISCONNECTED_DEBOUNCE)
-					typec_curr = 0;
-#endif
-			}
-
-#if defined(CONFIG_CHARGE_MANAGER)
-			timeout = PD_T_SINK_ADJ - PD_T_DEBOUNCE;
-
-			/* Check if CC pull-up has changed */
-			tcpm_get_cc(port, &cc1, &cc2);
-			if (typec_curr != usb_get_typec_current_limit(
-						pd[port].polarity, cc1, cc2)) {
-				/* debounce signal by requiring two reads */
-				if (typec_curr_change) {
-					/* set new input current limit */
-					typec_curr =
-						usb_get_typec_current_limit(
-							pd[port].polarity,
-							cc1, cc2);
-					typec_set_input_current_limit(
-					  port, typec_curr, TYPE_C_VOLTAGE);
-				} else {
-					/* delay for debounce */
-					timeout = PD_T_DEBOUNCE;
-				}
-				typec_curr_change = !typec_curr_change;
-			} else {
-				typec_curr_change = 0;
-			}
-#endif
-			break;
-		case PD_STATE_SNK_REQUESTED:
-			/* Wait for ACCEPT or REJECT */
-			if (pd[port].last_state != pd[port].task_state) {
-				pd[port].flags |= PD_FLAGS_CHECK_VCONN_STATE;
-				hard_reset_count = 0;
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  PD_STATE_HARD_RESET_SEND);
-			}
-			break;
-		case PD_STATE_SNK_TRANSITION:
-			/* Wait for PS_RDY */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_PS_TRANSITION,
-						  PD_STATE_HARD_RESET_SEND);
-			break;
-		case PD_STATE_SNK_READY:
-			timeout = 20*MSEC;
-
-			/*
-			 * Don't send any traffic yet until our holdoff timer
-			 * has expired.  Some devices are chatty once we reach
-			 * the SNK_READY state and we may end up in a collision
-			 * of messages if we try to immediately send our
-			 * interrogations.
-			 */
-			if (get_time().val <=
-			    pd[port].ready_state_holdoff_timer)
-				break;
-
-			/*
-			 * Don't send any PD traffic if we woke up due to
-			 * incoming packet or if VDO response pending to avoid
-			 * collisions.
-			 */
-			if (incoming_packet ||
-			    (pd[port].vdm_state == VDM_STATE_BUSY))
-				break;
-
-			/* Check for new power to request */
-			if (pd[port].new_power_request) {
-				if (pd_send_request_msg(port, 0) != EC_SUCCESS)
-					set_state(port, PD_STATE_SOFT_RESET);
-				break;
-			}
-
-			/* Check power role policy, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_PR_ROLE) {
-				pd_check_pr_role(port, PD_ROLE_SINK,
-						 pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
-				break;
-			}
-
-			/* Check data role policy, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_DR_ROLE) {
-				pd_check_dr_role(port, pd[port].data_role,
-						 pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_DR_ROLE;
-				break;
-			}
-
-			/* Check for Vconn source, which may trigger a swap */
-			if (pd[port].flags & PD_FLAGS_CHECK_VCONN_STATE) {
-				/*
-				 * Ref: Section 2.6.2 of both
-				 * USB-PD Spec Revision 2.0, Version 1.3 &
-				 * USB-PD Spec Revision 3.0, Version 2.0
-				 * During Explicit contract the Sink can
-				 * initiate or receive a request an exchange
-				 * of VCONN Source.
-				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
-				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
-				break;
-			}
-
-			/* If DFP, send discovery SVDMs */
-			if (pd[port].data_role == PD_ROLE_DFP &&
-			     (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
-				pd_send_vdm(port, USB_SID_PD,
-					    CMD_DISCOVER_IDENT, NULL, 0);
-				pd[port].flags &= ~PD_FLAGS_CHECK_IDENTITY;
-				break;
-			}
-
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
-			/* Sent all messages, don't need to wake very often */
-			timeout = 200*MSEC;
-			break;
-		case PD_STATE_SNK_SWAP_INIT:
-			if (pd[port].last_state != pd[port].task_state) {
-				res = send_control(port, PD_CTRL_PR_SWAP);
-				if (res < 0) {
-					timeout = 10*MSEC;
-					/*
-					 * If failed to get goodCRC, send
-					 * soft reset, otherwise ignore
-					 * failure.
-					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SNK_READY);
-					break;
-				}
-				/* Wait for accept or reject */
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  PD_STATE_SNK_READY);
-			}
-			break;
-		case PD_STATE_SNK_SWAP_SNK_DISABLE:
-			/* Stop drawing power */
-			pd_set_input_current_limit(port, 0, 0);
-#ifdef CONFIG_CHARGE_MANAGER
-			typec_set_input_current_limit(port, 0, 0);
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
-						CHARGE_CEIL_NONE);
-#endif
-			set_state(port, PD_STATE_SNK_SWAP_SRC_DISABLE);
-			timeout = 10*MSEC;
-			break;
-		case PD_STATE_SNK_SWAP_SRC_DISABLE:
-			/* Wait for PS_RDY */
-			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_PS_SOURCE_OFF,
-						  PD_STATE_HARD_RESET_SEND);
-			break;
-		case PD_STATE_SNK_SWAP_STANDBY:
-			if (pd[port].last_state != pd[port].task_state) {
-				/* Switch to Rp and enable power supply. */
-				tcpm_set_cc(port, TYPEC_CC_RP);
-				if (pd_set_power_supply_ready(port)) {
-					/* Restore Rd */
-					tcpm_set_cc(port, TYPEC_CC_RD);
-					timeout = 10*MSEC;
-					set_state(port,
-						  PD_STATE_SNK_DISCONNECTED);
-					break;
-				}
-				/* Wait for power supply to turn on */
-				set_state_timeout(
-					port,
-					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
-					PD_STATE_SNK_SWAP_COMPLETE);
-			}
-			break;
-		case PD_STATE_SNK_SWAP_COMPLETE:
-			/* Send PS_RDY and change to source role */
-			res = send_control(port, PD_CTRL_PS_RDY);
-			if (res < 0) {
-				/* Restore Rd */
-				tcpm_set_cc(port, TYPEC_CC_RD);
-				pd_power_supply_reset(port);
-				timeout = 10 * MSEC;
-				set_state(port, PD_STATE_SNK_DISCONNECTED);
-				break;
-			}
-
-			/* Don't send GET_SINK_CAP on swap */
-			snk_cap_count = PD_SNK_CAP_RETRIES+1;
-			caps_count = 0;
-			pd[port].msg_id = 0;
-			pd_set_power_role(port, PD_ROLE_SOURCE);
-			pd_update_roles(port);
-			set_state(port, PD_STATE_SRC_DISCOVERY);
-			timeout = 10*MSEC;
-			break;
-#ifdef CONFIG_USBC_VCONN_SWAP
-		case PD_STATE_VCONN_SWAP_SEND:
-			if (pd[port].last_state != pd[port].task_state) {
-				res = send_control(port, PD_CTRL_VCONN_SWAP);
-				if (res < 0) {
-					timeout = 10*MSEC;
-					/*
-					 * If failed to get goodCRC, send
-					 * soft reset, otherwise ignore
-					 * failure.
-					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
-					break;
-				}
-				/* Wait for accept or reject */
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
-						  READY_RETURN_STATE(port));
-			}
-			break;
-		case PD_STATE_VCONN_SWAP_INIT:
-			if (pd[port].last_state != pd[port].task_state) {
-				if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
-					/* Turn VCONN on and wait for it */
-					set_vconn(port, 1);
-					set_state_timeout(port,
-						get_time().val +
-						CONFIG_USBC_VCONN_SWAP_DELAY_US,
-						PD_STATE_VCONN_SWAP_READY);
-				} else {
-					set_state_timeout(port,
-						get_time().val +
-							PD_T_VCONN_SOURCE_ON,
-						READY_RETURN_STATE(port));
-				}
-			}
-			break;
-		case PD_STATE_VCONN_SWAP_READY:
-			if (pd[port].last_state != pd[port].task_state) {
-				if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
-					/* VCONN is now on, send PS_RDY */
-					pd_set_vconn_role(port,
-							PD_ROLE_VCONN_ON);
-					res = send_control(port,
-							PD_CTRL_PS_RDY);
-					if (res == -1) {
-						timeout = 10*MSEC;
-						/*
-						 * If failed to get goodCRC,
-						 * send soft reset
-						 */
-						set_state(port,
-							PD_STATE_SOFT_RESET);
-						break;
-					}
-					set_state(port,
-						READY_RETURN_STATE(port));
-				} else {
-					/* Turn VCONN off and wait for it */
-					set_vconn(port, 0);
-					pd_set_vconn_role(port,
-							PD_ROLE_VCONN_OFF);
-					set_state_timeout(port,
-						get_time().val +
-						CONFIG_USBC_VCONN_SWAP_DELAY_US,
-						READY_RETURN_STATE(port));
-				}
-			}
-			break;
-#endif /* CONFIG_USBC_VCONN_SWAP */
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-		case PD_STATE_SOFT_RESET:
-			if (pd[port].last_state != pd[port].task_state) {
-				/* Message ID of soft reset is always 0 */
-				invalidate_last_message_id(port);
-				pd[port].msg_id = 0;
-				res = send_control(port, PD_CTRL_SOFT_RESET);
-
-				/* if soft reset failed, try hard reset. */
-				if (res < 0) {
-					set_state(port,
-						  PD_STATE_HARD_RESET_SEND);
-					timeout = 5*MSEC;
-					break;
-				}
-
-				set_state_timeout(
-					port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					PD_STATE_HARD_RESET_SEND);
-			}
-			break;
-		case PD_STATE_HARD_RESET_SEND:
-			hard_reset_count++;
-			if (pd[port].last_state != pd[port].task_state) {
-				hard_reset_sent = 0;
-				pd[port].hard_reset_complete_timer = 0;
-			}
-#ifdef CONFIG_CHARGE_MANAGER
-			if (pd[port].last_state == PD_STATE_SNK_DISCOVERY ||
-			    (pd[port].last_state == PD_STATE_SOFT_RESET &&
-			     (pd[port].flags & PD_FLAGS_VBUS_NEVER_LOW))) {
-				pd[port].flags &= ~PD_FLAGS_VBUS_NEVER_LOW;
-				/*
-				 * If discovery timed out, assume that we
-				 * have a dedicated charger attached. This
-				 * may not be a correct assumption according
-				 * to the specification, but it generally
-				 * works in practice and the harmful
-				 * effects of a wrong assumption here
-				 * are minimal.
-				 */
-				charge_manager_update_dualrole(port,
-							       CAP_DEDICATED);
-			}
-#endif
-
-			if (hard_reset_sent)
-				break;
-
-			if (pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL,
-				AMS_START) < 0) {
-				/*
-				 * likely a non-idle channel
-				 * TCPCI r2.0 v1.0 4.4.15:
-				 * the TCPC does not retry HARD_RESET
-				 * but we can try periodically until the timer
-				 * expires.
-				 */
-				now = get_time();
-				if (pd[port].hard_reset_complete_timer == 0) {
-					pd[port].hard_reset_complete_timer =
-						now.val +
-						PD_T_HARD_RESET_COMPLETE;
-					timeout = PD_T_HARD_RESET_RETRY;
-					break;
-				}
-				if (now.val <
-				    pd[port].hard_reset_complete_timer) {
-					CPRINTS("C%d: Retrying hard reset",
-						port);
-					timeout = PD_T_HARD_RESET_RETRY;
-					break;
-				}
-				/*
-				 * PD 2.0 spec, section 6.5.11.1
-				 * Pretend TX_HARD_RESET succeeded after
-				 * timeout.
-				 */
-			}
-
-			hard_reset_sent = 1;
-			/*
-			 * If we are source, delay before cutting power
-			 * to allow sink time to get hard reset.
-			 */
-			if (pd[port].power_role == PD_ROLE_SOURCE) {
-				set_state_timeout(port,
-					get_time().val + PD_T_PS_HARD_RESET,
-						  PD_STATE_HARD_RESET_EXECUTE);
-			} else {
-				set_state(port, PD_STATE_HARD_RESET_EXECUTE);
-				timeout = 10 * MSEC;
-			}
-			break;
-		case PD_STATE_HARD_RESET_EXECUTE:
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-			/*
-			 * If hard reset while in the last stages of power
-			 * swap, then we need to restore our CC resistor.
-			 */
-			if (pd[port].last_state == PD_STATE_SNK_SWAP_STANDBY)
-				tcpm_set_cc(port, TYPEC_CC_RD);
-#endif
-
-			/* reset our own state machine */
-			pd_execute_hard_reset(port);
-			timeout = 10*MSEC;
-			break;
-#ifdef CONFIG_COMMON_RUNTIME
-		case PD_STATE_BIST_RX:
-			send_bist_cmd(port);
-			/* Delay at least enough for partner to finish BIST */
-			timeout = PD_T_BIST_RECEIVE + 20*MSEC;
-			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
-						PD_STATE_SRC_DISCONNECTED));
-			break;
-		case PD_STATE_BIST_TX:
-			pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL,
-				    AMS_START);
-			/* Delay at least enough to finish sending BIST */
-			timeout = PD_T_BIST_TRANSMIT + 20*MSEC;
-			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
-						PD_STATE_SRC_DISCONNECTED));
-			break;
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-		case PD_STATE_DRP_AUTO_TOGGLE:
-		{
-			enum pd_drp_next_states next_state;
-
-			assert(auto_toggle_supported);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-			/*
-			 * If SW decided we should be in a low power state and
-			 * the CC lines did not change, then don't talk with the
-			 * TCPC otherwise we might wake it up.
-			 */
-			if (pd[port].flags & PD_FLAGS_LPM_REQUESTED &&
-			    !(evt & PD_EVENT_CC))
-				break;
-
-			/*
-			 * Debounce low power mode exit.  Some TCPCs need time
-			 * for the CC_STATUS register to be stable after exiting
-			 * low power mode.
-			 */
-			if (pd[port].flags & PD_FLAGS_LPM_EXIT) {
-				uint64_t now;
-
-				now = get_time().val;
-				if (now < pd[port].low_power_exit_time)
-					break;
-
-				CPRINTS("TCPC p%d Exit Low Power Mode done",
-					port);
-				pd[port].flags &= ~PD_FLAGS_LPM_EXIT;
-			}
-#endif
-
-			/*
-			 * Check for connection
-			 *
-			 * Send FALSE for supports_auto_toggle to not change
-			 * the current return value of UNATTACHED instead of
-			 * the auto-toggle ATTACHED_WAIT response for TCPMv1.
-			 */
-			tcpm_get_cc(port, &cc1, &cc2);
-
-			next_state = drp_auto_toggle_next_state(
-						&pd[port].drp_sink_time,
-						pd[port].power_role,
-						drp_state[port],
-						cc1, cc2, false);
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-			/*
-			 * The next state is not determined just by what is
-			 * attached, but also depends on DRP_STATE. Regardless
-			 * of next state, if nothing is attached, then always
-			 * request low power mode.
-			 */
-			if (cc_is_open(cc1, cc2))
-				pd[port].flags |= PD_FLAGS_LPM_REQUESTED;
-#endif
-			if (next_state == DRP_TC_DEFAULT) {
-				if (PD_DEFAULT_STATE(port) ==
-						PD_STATE_SNK_DISCONNECTED)
-					next_state = DRP_TC_UNATTACHED_SNK;
-				else
-					next_state = DRP_TC_UNATTACHED_SRC;
-			}
-
-			if (next_state == DRP_TC_UNATTACHED_SNK) {
-				/*
-				 * The TCPCI comes out of auto toggle with
-				 * a prospective connection.  It is expecting
-				 * us to set the CC lines to what it is
-				 * thinking is best or it goes direct back to
-				 * unattached.  So get the SNK polarity to
-				 * be able to setup the CC lines to avoid this.
-				 */
-				pd[port].polarity = get_snk_polarity(cc1, cc2);
-
-				tcpm_set_cc(port, TYPEC_CC_RD);
-				pd_set_power_role(port, PD_ROLE_SINK);
-				timeout = 2*MSEC;
-				set_state(port, PD_STATE_SNK_DISCONNECTED);
-			} else if (next_state == DRP_TC_UNATTACHED_SRC) {
-				/*
-				 * The TCPCI comes out of auto toggle with
-				 * a prospective connection.  It is expecting
-				 * us to set the CC lines to what it is
-				 * thinking is best or it goes direct back to
-				 * unattached.  So get the SNK polarity to
-				 * be able to setup the CC lines to avoid this.
-				 */
-				pd[port].polarity = get_src_polarity(cc1, cc2);
-
-				tcpm_set_cc(port, TYPEC_CC_RP);
-				pd_set_power_role(port, PD_ROLE_SOURCE);
-				timeout = 2*MSEC;
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-			} else {
-				/*
-				 * We are staying in PD_STATE_DRP_AUTO_TOGGLE,
-				 * therefore enable auto-toggle.
-				 */
-				tcpm_enable_drp_toggle(port);
-				pd[port].flags |= PD_FLAGS_TCPC_DRP_TOGGLE;
-				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-			}
-
-			break;
-		}
-#endif
-		case PD_STATE_ENTER_USB:
-			if (pd[port].last_state != pd[port].task_state) {
-				set_state_timeout(port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					READY_RETURN_STATE(port));
-			}
-			break;
-		default:
-			break;
-		}
-
-		pd[port].last_state = this_state;
-
-		/*
-		 * Check for state timeout, and if not check if need to adjust
-		 * timeout value to wake up on the next state timeout.
-		 */
-		now = get_time();
-		if (pd[port].timeout) {
-			if (now.val >= pd[port].timeout) {
-				set_state(port, pd[port].timeout_state);
-				/* On a state timeout, run next state soon */
-				timeout = timeout < 10*MSEC ? timeout : 10*MSEC;
-			} else if (pd[port].timeout - now.val < timeout) {
-				timeout = pd[port].timeout - now.val;
-			}
-		}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-		/* Determine if we need to put the TCPC in low power mode */
-		if (pd[port].flags & PD_FLAGS_LPM_REQUESTED &&
-		    !(pd[port].flags & PD_FLAGS_LPM_ENGAGED)) {
-			int64_t time_left;
-
-			/* If any task prevents LPM, wait another debounce */
-			if (pd[port].tasks_preventing_lpm) {
-				pd[port].low_power_time =
-					PD_LPM_DEBOUNCE_US + now.val;
-			}
-
-			time_left = pd[port].low_power_time - now.val;
-			if (time_left <= 0) {
-				pd[port].flags |= PD_FLAGS_LPM_ENGAGED;
-				pd[port].flags |= PD_FLAGS_LPM_TRANSITION;
-				tcpm_enter_low_power_mode(port);
-				pd[port].flags &= ~PD_FLAGS_LPM_TRANSITION;
-				tcpc_prints("Enter Low Power Mode", port);
-				timeout = -1;
-			} else if (timeout < 0 || timeout > time_left) {
-				timeout = time_left;
-			}
-		}
-#endif
-
-		/* Check for disconnection if we're connected */
-		if (!pd_is_connected(port))
-			continue;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		if (pd_is_power_swapping(port))
-			continue;
-#endif
-		if (pd[port].power_role == PD_ROLE_SOURCE) {
-			/* Source: detect disconnect by monitoring CC */
-			tcpm_get_cc(port, &cc1, &cc2);
-			if (polarity_rm_dts(pd[port].polarity))
-				cc1 = cc2;
-			if (cc1 == TYPEC_CC_VOLT_OPEN) {
-				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				/* Debouncing */
-				timeout = 10*MSEC;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-				/*
-				 * If Try.SRC is configured, then ATTACHED_SRC
-				 * needs to transition to TryWait.SNK. Change
-				 * power role to SNK and start state timer.
-				 */
-				if (pd_try_src_enable) {
-					/* Swap roles to sink */
-					pd_set_power_role(port, PD_ROLE_SINK);
-					tcpm_set_cc(port, TYPEC_CC_RD);
-					/* Set timer for TryWait.SNK state */
-					pd[port].try_src_marker = get_time().val
-						+ PD_T_DEBOUNCE;
-					/* Advance to TryWait.SNK state */
-					set_state(port,
-						  PD_STATE_SNK_DISCONNECTED);
-					/* Mark state as TryWait.SNK */
-					pd[port].flags |= PD_FLAGS_TRY_SRC;
-				}
-#endif
-			}
-		}
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-		/*
-		 * Sink disconnect if VBUS is low and
-		 *  1) we are not waiting for VBUS to debounce after a power
-		 *     role swap.
-		 *  2) we are not recovering from a hard reset.
-		 */
-		if (pd[port].power_role == PD_ROLE_SINK &&
-		    pd[port].vbus_debounce_time < get_time().val &&
-		    !pd_is_vbus_present(port) &&
-		    pd[port].task_state != PD_STATE_SNK_HARD_RESET_RECOVER &&
-		    pd[port].task_state != PD_STATE_HARD_RESET_EXECUTE) {
-			/* Sink: detect disconnect by monitoring VBUS */
-			set_state(port, PD_STATE_SNK_DISCONNECTED);
-			/* set timeout small to reconnect fast */
-			timeout = 5*MSEC;
-		}
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-	}
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-static void pd_chipset_resume(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-#ifdef CONFIG_CHARGE_MANAGER
-		if (charge_manager_get_active_charge_port() != i)
-#endif
-			pd[i].flags |= PD_FLAGS_CHECK_PR_ROLE |
-				       PD_FLAGS_CHECK_DR_ROLE;
-		pd_set_dual_role(i, PD_DRP_TOGGLE_ON);
-	}
-
-	CPRINTS("PD:S3->S0");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pd_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_suspend(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		pd_set_dual_role(i, PD_DRP_TOGGLE_OFF);
-	CPRINTS("PD:S0->S3");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, pd_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_startup(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		pd_set_dual_role_no_wakeup(i, PD_DRP_TOGGLE_OFF);
-		pd[i].flags |= PD_FLAGS_CHECK_IDENTITY;
-		/* Reset cable attributes and flags */
-		reset_pd_cable(i);
-		task_set_event(PD_PORT_TO_TASK_ID(i),
-			       PD_EVENT_POWER_STATE_CHANGE |
-				       PD_EVENT_UPDATE_DUAL_ROLE);
-	}
-	CPRINTS("PD:S5->S3");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pd_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_shutdown(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		pd_set_dual_role_no_wakeup(i, PD_DRP_FORCE_SINK);
-		task_set_event(PD_PORT_TO_TASK_ID(i),
-			       PD_EVENT_POWER_STATE_CHANGE |
-				       PD_EVENT_UPDATE_DUAL_ROLE);
-	}
-	CPRINTS("PD:S3->S5");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pd_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-#ifdef CONFIG_COMMON_RUNTIME
-
-static void pd_control_resume(int port)
-{
-	if (pd[port].task_state != PD_STATE_SUSPENDED)
-		return;
-
-	set_state(port, PD_DEFAULT_STATE(port));
-	/*
-	 * Since we did not service interrupts while we were suspended,
-	 * see if there is a waiting interrupt to be serviced. If the
-	 * interrupt line isn't asserted, we won't communicate with the
-	 * TCPC.
-	 */
-	if (IS_ENABLED(HAS_TASK_PD_INT_C0))
-		schedule_deferred_pd_interrupt(port);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-/*
- * (suspend=1) request pd_task transition to the suspended state.  hang
- * around for a while until we observe the state change.  this can
- * take a while (like 300ms) on startup when pd_task is sleeping in
- * tcpci_tcpm_init.
- *
- * (suspend=0) force pd_task out of the suspended state and into the
- * port's default state.
- */
-
-void pd_set_suspend(int port, int suspend)
-{
-	int tries = 300;
-
-	if (suspend) {
-		pd[port].req_suspend_state = 1;
-		do {
-			task_wake(PD_PORT_TO_TASK_ID(port));
-			if (pd[port].task_state == PD_STATE_SUSPENDED)
-				break;
-			msleep(1);
-		} while (--tries != 0);
-		if (!tries)
-			tcpc_prints("set_suspend failed!", port);
-	} else {
-		pd_control_resume(port);
-	}
-}
-
-int pd_is_port_enabled(int port)
-{
-	switch (pd[port].task_state) {
-	case PD_STATE_DISABLED:
-	case PD_STATE_SUSPENDED:
-		return 0;
-	default:
-		return 1;
-	}
-}
-
-#if defined(CONFIG_USB_PD_ALT_MODE) && !defined(CONFIG_USB_PD_ALT_MODE_DFP)
-void pd_send_hpd(int port, enum hpd_event hpd)
-{
-	uint32_t data[1];
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	if (!opos)
-		return;
-
-	data[0] = VDO_DP_STATUS((hpd == hpd_irq),  /* IRQ_HPD */
-				(hpd != hpd_low),  /* HPD_HI|LOW */
-				0,		      /* request exit DP */
-				0,		      /* request exit USB */
-				0,		      /* MF pref */
-				1,                    /* enabled */
-				0,		      /* power low */
-				0x2);
-	pd_send_vdm(port, USB_SID_DISPLAYPORT,
-		    VDO_OPOS(opos) | CMD_ATTENTION, data, 1);
-	/* Wait until VDM is done. */
-	while (pd[0].vdm_state > 0)
-		task_wait_event(USB_PD_RX_TMOUT_US *
-				(CONFIG_PD_RETRY_COUNT + 1));
-}
-#endif
-
-int pd_fetch_acc_log_entry(int port)
-{
-	timestamp_t timeout;
-
-	/* Cannot send a VDM now, the host should retry */
-	if (pd[port].vdm_state > 0)
-		return pd[port].vdm_state == VDM_STATE_BUSY ?
-				EC_RES_BUSY : EC_RES_UNAVAILABLE;
-
-	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_GET_LOG, NULL, 0);
-	timeout.val = get_time().val + 75*MSEC;
-
-	/* Wait until VDM is done */
-	while ((pd[port].vdm_state > 0) &&
-	       (get_time().val < timeout.val))
-		task_wait_event(10*MSEC);
-
-	if (pd[port].vdm_state > 0)
-		return EC_RES_TIMEOUT;
-	else if (pd[port].vdm_state < 0)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-void pd_request_source_voltage(int port, int mv)
-{
-	pd_set_max_voltage(mv);
-
-	if (pd[port].task_state == PD_STATE_SNK_READY ||
-	    pd[port].task_state == PD_STATE_SNK_TRANSITION) {
-		/* Set flag to send new power request in pd_task */
-		pd[port].new_power_request = 1;
-	} else {
-		pd_set_power_role(port, PD_ROLE_SINK);
-		tcpm_set_cc(port, TYPEC_CC_RD);
-		set_state(port, PD_STATE_SNK_DISCONNECTED);
-	}
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void pd_set_external_voltage_limit(int port, int mv)
-{
-	pd_set_max_voltage(mv);
-
-	if (pd[port].task_state == PD_STATE_SNK_READY ||
-	    pd[port].task_state == PD_STATE_SNK_TRANSITION) {
-		/* Set flag to send new power request in pd_task */
-		pd[port].new_power_request = 1;
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_update_contract(int port)
-{
-	if ((pd[port].task_state >= PD_STATE_SRC_NEGOCIATE) &&
-	    (pd[port].task_state <= PD_STATE_SRC_GET_SINK_CAP)) {
-		pd[port].flags |= PD_FLAGS_UPDATE_SRC_CAPS;
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-
-static int command_pd(int argc, char **argv)
-{
-	int port;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "dump")) {
-		if (argc >= 3) {
-#ifdef CONFIG_USB_PD_DEBUG_LEVEL
-			return EC_ERROR_PARAM2;
-#else
-			int level = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM2;
-			debug_level = level;
-#endif
-		}
-		ccprintf("debug=%d\n", debug_level);
-
-		return EC_SUCCESS;
-	}
-
-#ifdef CONFIG_CMD_PD
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-	else if (!strncasecmp(argv[1], "rwhashtable", 3)) {
-		int i;
-		struct ec_params_usb_pd_rw_hash_entry *p;
-		for (i = 0; i < RW_HASH_ENTRIES; i++) {
-			p = &rw_hash_table[i];
-			pd_dev_dump_info(p->dev_id, p->dev_rw_hash);
-		}
-		return EC_SUCCESS;
-	}
-#endif /* CONFIG_CMD_PD_DEV_DUMP_INFO */
-#ifdef CONFIG_USB_PD_TRY_SRC
-	else if (!strncasecmp(argv[1], "trysrc", 6)) {
-		int enable;
-
-		if (argc >= 3) {
-			enable = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			pd_try_src_enable = enable ? 1 : 0;
-		}
-
-		ccprintf("Try.SRC %s\n", pd_try_src_enable ? "on" : "off");
-		return EC_SUCCESS;
-	}
-#endif
-#endif
-	else if (!strcasecmp(argv[1], "version")) {
-		ccprintf("%d\n", PD_STACK_VERSION);
-		return EC_SUCCESS;
-	}
-
-	/* command: pd <port> <subcmd> [args] */
-	port = strtoi(argv[1], &e, 10);
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-#if defined(CONFIG_CMD_PD) && defined(CONFIG_USB_PD_DUAL_ROLE)
-
-	if (!strcasecmp(argv[2], "tx")) {
-		set_state(port, PD_STATE_SNK_DISCOVERY);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strcasecmp(argv[2], "bist_rx")) {
-		set_state(port, PD_STATE_BIST_RX);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strcasecmp(argv[2], "bist_tx")) {
-		if (*e)
-			return EC_ERROR_PARAM3;
-		set_state(port, PD_STATE_BIST_TX);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strcasecmp(argv[2], "charger")) {
-		pd_set_power_role(port, PD_ROLE_SOURCE);
-		tcpm_set_cc(port, TYPEC_CC_RP);
-		set_state(port, PD_STATE_SRC_DISCONNECTED);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strncasecmp(argv[2], "dev", 3)) {
-		int max_volt;
-		if (argc >= 4)
-			max_volt = strtoi(argv[3], &e, 10) * 1000;
-		else
-			max_volt = pd_get_max_voltage();
-
-		pd_request_source_voltage(port, max_volt);
-		ccprintf("max req: %dmV\n", max_volt);
-	} else if (!strcasecmp(argv[2], "disable")) {
-		pd_comm_enable(port, 0);
-		ccprintf("Port C%d disable\n", port);
-		return EC_SUCCESS;
-	} else if (!strcasecmp(argv[2], "enable")) {
-		pd_comm_enable(port, 1);
-		ccprintf("Port C%d enabled\n", port);
-		return EC_SUCCESS;
-	} else if (!strncasecmp(argv[2], "hard", 4)) {
-		set_state(port, PD_STATE_HARD_RESET_SEND);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strncasecmp(argv[2], "info", 4)) {
-		int i;
-		ccprintf("Hash ");
-		for (i = 0; i < PD_RW_HASH_SIZE / 4; i++)
-			ccprintf("%08x ", pd[port].dev_rw_hash[i]);
-		ccprintf("\nImage %s\n",
-			 ec_image_to_string(pd[port].current_image));
-	} else if (!strncasecmp(argv[2], "soft", 4)) {
-		set_state(port, PD_STATE_SOFT_RESET);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	} else if (!strncasecmp(argv[2], "swap", 4)) {
-		if (argc < 4)
-			return EC_ERROR_PARAM_COUNT;
-
-		if (!strncasecmp(argv[3], "power", 5))
-			pd_request_power_swap(port);
-		else if (!strncasecmp(argv[3], "data", 4))
-			pd_request_data_swap(port);
-#ifdef CONFIG_USBC_VCONN_SWAP
-		else if (!strncasecmp(argv[3], "vconn", 5))
-			pd_request_vconn_swap(port);
-#endif
-		else
-			return EC_ERROR_PARAM3;
-	} else if (!strncasecmp(argv[2], "srccaps", 7)) {
-		pd_srccaps_dump(port);
-	} else if (!strncasecmp(argv[2], "ping", 4)) {
-		int enable;
-
-		if (argc > 3) {
-			enable = strtoi(argv[3], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM3;
-			pd_ping_enable(port, enable);
-		}
-
-		ccprintf("Pings %s\n",
-			 (pd[port].flags & PD_FLAGS_PING_ENABLED) ?
-			 "on" : "off");
-	} else if (!strncasecmp(argv[2], "vdm", 3)) {
-		if (argc < 4)
-			return EC_ERROR_PARAM_COUNT;
-
-		if (!strncasecmp(argv[3], "ping", 4)) {
-			uint32_t enable;
-			if (argc < 5)
-				return EC_ERROR_PARAM_COUNT;
-			enable = strtoi(argv[4], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM4;
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_PING_ENABLE,
-				    &enable, 1);
-		} else if (!strncasecmp(argv[3], "curr", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT,
-				    NULL, 0);
-		} else if (!strncasecmp(argv[3], "vers", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION,
-				    NULL, 0);
-		} else {
-			return EC_ERROR_PARAM_COUNT;
-		}
-#if defined(CONFIG_CMD_PD) && defined(CONFIG_CMD_PD_FLASH)
-	} else if (!strncasecmp(argv[2], "flash", 4)) {
-		return remote_flashing(argc, argv);
-#endif
-#if defined(CONFIG_CMD_PD) && defined(CONFIG_USB_PD_DUAL_ROLE)
-	} else if (!strcasecmp(argv[2], "dualrole")) {
-		if (argc < 4) {
-			ccprintf("dual-role toggling: ");
-			switch (drp_state[port]) {
-			case PD_DRP_TOGGLE_ON:
-				ccprintf("on\n");
-				break;
-			case PD_DRP_TOGGLE_OFF:
-				ccprintf("off\n");
-				break;
-			case PD_DRP_FREEZE:
-				ccprintf("freeze\n");
-				break;
-			case PD_DRP_FORCE_SINK:
-				ccprintf("force sink\n");
-				break;
-			case PD_DRP_FORCE_SOURCE:
-				ccprintf("force source\n");
-				break;
-			}
-		} else {
-			if (!strcasecmp(argv[3], "on"))
-				pd_set_dual_role(port, PD_DRP_TOGGLE_ON);
-			else if (!strcasecmp(argv[3], "off"))
-				pd_set_dual_role(port, PD_DRP_TOGGLE_OFF);
-			else if (!strcasecmp(argv[3], "freeze"))
-				pd_set_dual_role(port, PD_DRP_FREEZE);
-			else if (!strcasecmp(argv[3], "sink"))
-				pd_set_dual_role(port, PD_DRP_FORCE_SINK);
-			else if (!strcasecmp(argv[3], "source"))
-				pd_set_dual_role(port,
-					PD_DRP_FORCE_SOURCE);
-			else
-				return EC_ERROR_PARAM4;
-		}
-		return EC_SUCCESS;
-#endif
-	} else
-#endif
-	if (!strncasecmp(argv[2], "state", 5)) {
-		ccprintf("Port C%d CC%d, %s - Role: %s-%s%s "
-			 "State: %d(%s), Flags: 0x%04x\n",
-			port, pd[port].polarity + 1,
-			pd_comm_is_enabled(port) ? "Ena" : "Dis",
-			pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK",
-			pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP",
-			(pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "",
-			pd[port].task_state,
-			debug_level > 0 ? pd_get_task_state_name(port) : "",
-			pd[port].flags);
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pd, command_pd,
-			"version"
-			"|dump"
-#ifdef CONFIG_USB_PD_TRY_SRC
-			"|trysrc"
-#endif
-			" [0|1|2]"
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-			"|rwhashtable"
-#endif
-			"\n\t<port> state"
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-			"|tx|bist_rx|bist_tx|charger|dev"
-			"\n\t<port> disable|enable|soft|info|hard|ping"
-			"\n\t<port> dualrole [on|off|freeze|sink|source]"
-			"\n\t<port> swap [power|data|vconn]"
-			"\n\t<port> vdm [ping|curr|vers]"
-#ifdef CONFIG_CMD_PD_FLASH
-			"\n\t<port> flash [erase|reboot|signature|info|version]"
-#endif /* CONFIG_CMD_PD_FLASH */
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-			"\n\t<port> srccaps",
-			"USB PD");
-
-#ifdef HAS_TASK_HOSTCMD
-
-#ifdef CONFIG_HOSTCMD_FLASHPD
-static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_fw_update *p = args->params;
-	int port = p->port;
-	const uint32_t *data = &(p->size) + 1;
-	int i, size, rv = EC_RES_SUCCESS;
-	timestamp_t timeout;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (p->size + sizeof(*p) > args->params_size)
-		return EC_RES_INVALID_PARAM;
-
-#if defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	 defined(CONFIG_BATTERY_PRESENT_GPIO))
-	/*
-	 * Do not allow PD firmware update if no battery and this port
-	 * is sinking power, because we will lose power.
-	 */
-	if (battery_is_present() != BP_YES &&
-	    charge_manager_get_active_charge_port() == port)
-		return EC_RES_UNAVAILABLE;
-#endif
-
-	/*
-	 * Busy still with a VDM that host likely generated.  1 deep VDM queue
-	 * so just return for retry logic on host side to deal with.
-	 */
-	if (pd[port].vdm_state > 0)
-		return EC_RES_BUSY;
-
-	switch (p->cmd) {
-	case USB_PD_FW_REBOOT:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_REBOOT, NULL, 0);
-
-		/*
-		 * Return immediately to free pending i2c bus.	Host needs to
-		 * manage this delay.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_FLASH_ERASE:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_ERASE, NULL, 0);
-
-		/*
-		 * Return immediately.	Host needs to manage delays here which
-		 * can be as long as 1.2 seconds on 64KB RW flash.
-		 */
-		return EC_RES_SUCCESS;
-
-	case USB_PD_FW_ERASE_SIG:
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0);
-		timeout.val = get_time().val + 500*MSEC;
-		break;
-
-	case USB_PD_FW_FLASH_WRITE:
-		/* Data size must be a multiple of 4 */
-		if (!p->size || p->size % 4)
-			return EC_RES_INVALID_PARAM;
-
-		size = p->size / 4;
-		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
-				    data + i, MIN(size - i, VDO_MAX_SIZE - 1));
-			timeout.val = get_time().val + 500*MSEC;
-
-			/* Wait until VDM is done */
-			while ((pd[port].vdm_state > 0) &&
-			       (get_time().val < timeout.val))
-				task_wait_event(10*MSEC);
-
-			if (pd[port].vdm_state > 0)
-				return EC_RES_TIMEOUT;
-		}
-		return EC_RES_SUCCESS;
-
-	default:
-		return EC_RES_INVALID_PARAM;
-		break;
-	}
-
-	/* Wait until VDM is done or timeout */
-	while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val))
-		task_wait_event(50*MSEC);
-
-	if ((pd[port].vdm_state > 0) ||
-	    (pd[port].vdm_state == VDM_STATE_ERR_TMOUT))
-		rv = EC_RES_TIMEOUT;
-	else if (pd[port].vdm_state < 0)
-		rv = EC_RES_ERROR;
-
-	return rv;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-		     hc_remote_flash,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HOSTCMD_FLASHPD */
-
-#endif /* HAS_TASK_HOSTCMD */
-
-
-#endif /* CONFIG_COMMON_RUNTIME */
diff --git a/common/usb_pd_tcpc.c b/common/usb_pd_tcpc.c
deleted file mode 100644
index 1aaee29abc..0000000000
--- a/common/usb_pd_tcpc.c
+++ /dev/null
@@ -1,1468 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "crc.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_config.h"
-#include "usb_pd_tcpm.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/*
- * Debug log level - higher number == more log
- *   Level 0: Log state transitions
- *   Level 1: Level 0, plus packet info
- *   Level 2: Level 1, plus ping packet and packet dump on error
- *
- * Note that higher log level causes timing changes and thus may affect
- * performance.
- */
-static int debug_level;
-
-static struct mutex pd_crc_lock;
-#else
-#define CPRINTF(format, args...)
-static const int debug_level;
-#endif
-
-/* Encode 5 bits using Biphase Mark Coding */
-#define BMC(x)   ((x &  1 ? 0x001 : 0x3FF) \
-		^ (x &  2 ? 0x004 : 0x3FC) \
-		^ (x &  4 ? 0x010 : 0x3F0) \
-		^ (x &  8 ? 0x040 : 0x3C0) \
-		^ (x & 16 ? 0x100 : 0x300))
-
-/* 4b/5b + Bimark Phase encoding */
-static const uint16_t bmc4b5b[] = {
-/* 0 = 0000 */ BMC(0x1E) /* 11110 */,
-/* 1 = 0001 */ BMC(0x09) /* 01001 */,
-/* 2 = 0010 */ BMC(0x14) /* 10100 */,
-/* 3 = 0011 */ BMC(0x15) /* 10101 */,
-/* 4 = 0100 */ BMC(0x0A) /* 01010 */,
-/* 5 = 0101 */ BMC(0x0B) /* 01011 */,
-/* 6 = 0110 */ BMC(0x0E) /* 01110 */,
-/* 7 = 0111 */ BMC(0x0F) /* 01111 */,
-/* 8 = 1000 */ BMC(0x12) /* 10010 */,
-/* 9 = 1001 */ BMC(0x13) /* 10011 */,
-/* A = 1010 */ BMC(0x16) /* 10110 */,
-/* B = 1011 */ BMC(0x17) /* 10111 */,
-/* C = 1100 */ BMC(0x1A) /* 11010 */,
-/* D = 1101 */ BMC(0x1B) /* 11011 */,
-/* E = 1110 */ BMC(0x1C) /* 11100 */,
-/* F = 1111 */ BMC(0x1D) /* 11101 */,
-/* Sync-1      K-code       11000 Startsynch #1 */
-/* Sync-2      K-code       10001 Startsynch #2 */
-/* RST-1       K-code       00111 Hard Reset #1 */
-/* RST-2       K-code       11001 Hard Reset #2 */
-/* EOP         K-code       01101 EOP End Of Packet */
-/* Reserved    Error        00000 */
-/* Reserved    Error        00001 */
-/* Reserved    Error        00010 */
-/* Reserved    Error        00011 */
-/* Reserved    Error        00100 */
-/* Reserved    Error        00101 */
-/* Reserved    Error        00110 */
-/* Reserved    Error        01000 */
-/* Reserved    Error        01100 */
-/* Reserved    Error        10000 */
-/* Reserved    Error        11111 */
-};
-
-static const uint8_t dec4b5b[] = {
-/* Error    */ 0x10 /* 00000 */,
-/* Error    */ 0x10 /* 00001 */,
-/* Error    */ 0x10 /* 00010 */,
-/* Error    */ 0x10 /* 00011 */,
-/* Error    */ 0x10 /* 00100 */,
-/* Error    */ 0x10 /* 00101 */,
-/* Error    */ 0x10 /* 00110 */,
-/* RST-1    */ 0x13 /* 00111 K-code: Hard Reset #1 */,
-/* Error    */ 0x10 /* 01000 */,
-/* 1 = 0001 */ 0x01 /* 01001 */,
-/* 4 = 0100 */ 0x04 /* 01010 */,
-/* 5 = 0101 */ 0x05 /* 01011 */,
-/* Error    */ 0x10 /* 01100 */,
-/* EOP      */ 0x15 /* 01101 K-code: EOP End Of Packet */,
-/* 6 = 0110 */ 0x06 /* 01110 */,
-/* 7 = 0111 */ 0x07 /* 01111 */,
-/* Error    */ 0x10 /* 10000 */,
-/* Sync-2   */ 0x12 /* 10001 K-code: Startsynch #2 */,
-/* 8 = 1000 */ 0x08 /* 10010 */,
-/* 9 = 1001 */ 0x09 /* 10011 */,
-/* 2 = 0010 */ 0x02 /* 10100 */,
-/* 3 = 0011 */ 0x03 /* 10101 */,
-/* A = 1010 */ 0x0A /* 10110 */,
-/* B = 1011 */ 0x0B /* 10111 */,
-/* Sync-1   */ 0x11 /* 11000 K-code: Startsynch #1 */,
-/* RST-2    */ 0x14 /* 11001 K-code: Hard Reset #2 */,
-/* C = 1100 */ 0x0C /* 11010 */,
-/* D = 1101 */ 0x0D /* 11011 */,
-/* E = 1110 */ 0x0E /* 11100 */,
-/* F = 1111 */ 0x0F /* 11101 */,
-/* 0 = 0000 */ 0x00 /* 11110 */,
-/* Error    */ 0x10 /* 11111 */,
-};
-
-/* Start of Packet sequence : three Sync-1 K-codes, then one Sync-2 K-code */
-#define PD_SOP (PD_SYNC1 | (PD_SYNC1<<5) | (PD_SYNC1<<10) | (PD_SYNC2<<15))
-#define PD_SOP_PRIME	(PD_SYNC1 | (PD_SYNC1<<5) | \
-			(PD_SYNC3<<10) | (PD_SYNC3<<15))
-#define PD_SOP_PRIME_PRIME	(PD_SYNC1 | (PD_SYNC3<<5) | \
-				(PD_SYNC1<<10) | (PD_SYNC3<<15))
-
-/* Hard Reset sequence : three RST-1 K-codes, then one RST-2 K-code */
-#define PD_HARD_RESET (PD_RST1 | (PD_RST1 << 5) |\
-		      (PD_RST1 << 10) | (PD_RST2 << 15))
-
-/*
- * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector
- * Specification)
- *
- * CC1    CC2    STATE             POSITION
- * ----------------------------------------
- * open   open   NC                N/A
- * Rd     open   UFP attached      1
- * open   Rd     UFP attached      2
- * open   Ra     pwr cable no UFP  N/A
- * Ra     open   pwr cable no UFP  N/A
- * Rd     Ra     pwr cable & UFP   1
- * Ra     Rd     pwr cable & UFP   2
- * Rd     Rd     dbg accessory     N/A
- * Ra     Ra     audio accessory   N/A
- *
- * Note, V(Rd) > V(Ra)
- */
-#ifndef PD_SRC_RD_THRESHOLD
-#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
-#endif
-#ifndef PD_SRC_VNC
-#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
-#endif
-
-#ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < PD_SRC_RD_THRESHOLD)
-#endif
-#define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
-#ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
-#endif
-
-/*
- * Polarity based on 'UFP Perspective'.
- *
- * CC1    CC2    STATE             POSITION
- * ----------------------------------------
- * open   open   NC                N/A
- * Rp     open   DFP attached      1
- * open   Rp     DFP attached      2
- * Rp     Rp     Accessory attached N/A
- */
-#ifndef PD_SNK_VA
-#define PD_SNK_VA PD_SNK_VA_MV
-#endif
-
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
-
-/*
- * Type C power source charge current limits are identified by their cc
- * voltage (set by selecting the proper Rd resistor). Any voltage below
- * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
- */
-#define TYPE_C_SRC_500_THRESHOLD	PD_SRC_RD_THRESHOLD
-#define TYPE_C_SRC_1500_THRESHOLD	660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD	1230 /* mV */
-
-/* Convert TCPC Alert register to index into pd.alert[] */
-#define ALERT_REG_TO_INDEX(reg) (reg - TCPC_REG_ALERT)
-
-/* PD transmit errors */
-enum pd_tx_errors {
-	PD_TX_ERR_GOODCRC = -1, /* Failed to receive goodCRC */
-	PD_TX_ERR_DISABLED = -2, /* Attempted transmit even though disabled */
-	PD_TX_ERR_INV_ACK = -4, /* Received different packet instead of gCRC */
-	PD_TX_ERR_COLLISION = -5 /* Collision detected during transmit */
-};
-
-/* PD Header with SOP* encoded in bits 31 - 28 */
-union pd_header_sop {
-	uint16_t pd_header;
-	uint32_t head;
-};
-
-/*
- * If TCPM is not on this chip, and PD low power is defined, then use low
- * power task delay logic.
- */
-#if !defined(CONFIG_USB_POWER_DELIVERY) && defined(CONFIG_USB_PD_LOW_POWER)
-#define TCPC_LOW_POWER
-#endif
-
-/*
- * Receive message buffer size. Buffer physical size is RX_BUFFER_SIZE + 1,
- * but only RX_BUFFER_SIZE of that memory is used to store messages that can
- * be retrieved from TCPM. The last slot is a temporary buffer for collecting
- * a message before deciding whether or not to keep it.
- */
-#ifdef CONFIG_USB_POWER_DELIVERY
-#define RX_BUFFER_SIZE 1
-#else
-#define RX_BUFFER_SIZE 2
-#endif
-
-static struct pd_port_controller {
-	/* current port power role (SOURCE or SINK) */
-	uint8_t power_role;
-	/* current port data role (DFP or UFP) */
-	uint8_t data_role;
-	/* Port polarity : 0 => CC1 is CC line, 1 => CC2 is CC line */
-	uint8_t polarity;
-	/* Our CC pull resistor setting */
-	uint8_t cc_pull;
-	/* CC status */
-	uint8_t cc_status[2];
-	/* TCPC alert status */
-	uint16_t alert;
-	uint16_t alert_mask;
-	/* RX enabled */
-	uint8_t rx_enabled;
-	/* Power status */
-	uint8_t power_status;
-	uint8_t power_status_mask;
-
-#ifdef TCPC_LOW_POWER
-	/* Timestamp beyond which we allow low power task sampling */
-	timestamp_t low_power_ts;
-#endif
-
-	/* Last received */
-	int rx_head[RX_BUFFER_SIZE+1];
-	uint32_t rx_payload[RX_BUFFER_SIZE+1][7];
-	int rx_buf_head, rx_buf_tail;
-
-	/* Next transmit */
-	enum tcpci_msg_type tx_type;
-	uint16_t tx_head;
-	uint32_t tx_payload[7];
-	const uint32_t *tx_data;
-} pd[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int rx_buf_is_full(int port)
-{
-	/*
-	 * TODO: Refactor these to use the incrementing-counter idiom instead of
-	 * the wrapping-counter idiom to reclaim the last buffer entry.
-	 *
-	 * Buffer is full if the tail is 1 ahead of head.
-	 */
-	int diff = pd[port].rx_buf_tail - pd[port].rx_buf_head;
-	return (diff == 1) || (diff == -RX_BUFFER_SIZE);
-}
-
-int rx_buf_is_empty(int port)
-{
-	/* Buffer is empty if the head and tail are the same */
-	return pd[port].rx_buf_tail == pd[port].rx_buf_head;
-}
-
-void rx_buf_clear(int port)
-{
-	pd[port].rx_buf_tail = pd[port].rx_buf_head;
-}
-
-static void rx_buf_increment(int port, int *buf_ptr)
-{
-	*buf_ptr = *buf_ptr == RX_BUFFER_SIZE ? 0 : *buf_ptr + 1;
-}
-
-static inline int encode_short(int port, int off, uint16_t val16)
-{
-	off = pd_write_sym(port, off, bmc4b5b[(val16 >> 0) & 0xF]);
-	off = pd_write_sym(port, off, bmc4b5b[(val16 >> 4) & 0xF]);
-	off = pd_write_sym(port, off, bmc4b5b[(val16 >> 8) & 0xF]);
-	return pd_write_sym(port, off, bmc4b5b[(val16 >> 12) & 0xF]);
-}
-
-int encode_word(int port, int off, uint32_t val32)
-{
-	off = encode_short(port, off, (val32 >> 0) & 0xFFFF);
-	return encode_short(port, off, (val32 >> 16) & 0xFFFF);
-}
-
-/* prepare a 4b/5b-encoded PD message to send */
-int prepare_message(int port, uint16_t header, uint8_t cnt,
-		   const uint32_t *data)
-{
-	int off, i;
-	/* 64-bit preamble */
-	off = pd_write_preamble(port);
-#if defined(CONFIG_USB_VPD) || defined(CONFIG_USB_CTVPD)
-	/* Start Of Packet Prime: 2x Sync-1 + 2x Sync-3 */
-	off = pd_write_sym(port, off, BMC(PD_SYNC1));
-	off = pd_write_sym(port, off, BMC(PD_SYNC1));
-	off = pd_write_sym(port, off, BMC(PD_SYNC3));
-	off = pd_write_sym(port, off, BMC(PD_SYNC3));
-#else
-	/* Start Of Packet: 3x Sync-1 + 1x Sync-2 */
-	off = pd_write_sym(port, off, BMC(PD_SYNC1));
-	off = pd_write_sym(port, off, BMC(PD_SYNC1));
-	off = pd_write_sym(port, off, BMC(PD_SYNC1));
-	off = pd_write_sym(port, off, BMC(PD_SYNC2));
-#endif
-	/* header */
-	off = encode_short(port, off, header);
-
-#ifdef CONFIG_COMMON_RUNTIME
-	mutex_lock(&pd_crc_lock);
-#endif
-
-	crc32_init();
-	crc32_hash16(header);
-	/* data payload */
-	for (i = 0; i < cnt; i++) {
-		off = encode_word(port, off, data[i]);
-		crc32_hash32(data[i]);
-	}
-	/* CRC */
-	off = encode_word(port, off, crc32_result());
-
-#ifdef CONFIG_COMMON_RUNTIME
-	mutex_unlock(&pd_crc_lock);
-#endif
-
-	/* End Of Packet */
-	off = pd_write_sym(port, off, BMC(PD_EOP));
-	/* Ensure that we have a final edge */
-	return pd_write_last_edge(port, off);
-}
-
-static int send_hard_reset(int port)
-{
-	int off;
-
-	if (debug_level >= 1)
-		CPRINTF("C%d Send hard reset\n", port);
-
-	/* 64-bit preamble */
-	off = pd_write_preamble(port);
-	/* Hard-Reset: 3x RST-1 + 1x RST-2 */
-	off = pd_write_sym(port, off, BMC(PD_RST1));
-	off = pd_write_sym(port, off, BMC(PD_RST1));
-	off = pd_write_sym(port, off, BMC(PD_RST1));
-	off = pd_write_sym(port, off, BMC(PD_RST2));
-	/* Ensure that we have a final edge */
-	off = pd_write_last_edge(port, off);
-	/* Transmit the packet */
-	if (pd_start_tx(port, pd[port].polarity, off) < 0)
-		return PD_TX_ERR_COLLISION;
-	pd_tx_done(port, pd[port].polarity);
-	/* Keep RX monitoring on */
-	pd_rx_enable_monitoring(port);
-	return 0;
-}
-
-static int send_validate_message(int port, uint16_t header,
-				 const uint32_t *data)
-{
-	int r;
-	static uint32_t payload[7];
-	uint8_t expected_msg_id = PD_HEADER_ID(header);
-	uint8_t cnt = PD_HEADER_CNT(header);
-	int retries = PD_HEADER_TYPE(header) == PD_DATA_SOURCE_CAP ?
-				    0 :
-				    CONFIG_PD_RETRY_COUNT;
-
-	/* retry 3 times if we are not getting a valid answer */
-	for (r = 0; r <= retries; r++) {
-		int bit_len, head;
-		/* write the encoded packet in the transmission buffer */
-		bit_len = prepare_message(port, header, cnt, data);
-		/* Transmit the packet */
-		if (pd_start_tx(port, pd[port].polarity, bit_len) < 0) {
-			/*
-			 * Collision detected, return immediately so we can
-			 * respond to what we have received.
-			 */
-			return PD_TX_ERR_COLLISION;
-		}
-		pd_tx_done(port, pd[port].polarity);
-		/*
-		 * If this is the first attempt, leave RX monitoring off,
-		 * and do a blocking read of the channel until timeout or
-		 * packet received. If we failed the first try, enable
-		 * interrupt and yield to other tasks, so that we don't
-		 * starve them.
-		 */
-		if (r) {
-			pd_rx_enable_monitoring(port);
-			/* Wait for message receive timeout */
-			if (task_wait_event(USB_PD_RX_TMOUT_US) ==
-			    TASK_EVENT_TIMER)
-				continue;
-			/*
-			 * Make sure we woke up due to rx recd, otherwise
-			 * we need to manually start
-			 */
-			if (!pd_rx_started(port)) {
-				pd_rx_disable_monitoring(port);
-				pd_rx_start(port);
-			}
-		} else {
-			/* starting waiting for GoodCrc */
-			pd_rx_start(port);
-		}
-		/* read the incoming packet if any */
-		head = pd_analyze_rx(port, payload);
-		pd_rx_complete(port);
-		/* keep RX monitoring on to avoid collisions */
-		pd_rx_enable_monitoring(port);
-		if (head > 0) { /* we got a good packet, analyze it */
-			int type = PD_HEADER_TYPE(head);
-			int nb = PD_HEADER_CNT(head);
-			uint8_t id = PD_HEADER_ID(head);
-			if (type == PD_CTRL_GOOD_CRC && nb == 0 &&
-			    id == expected_msg_id) {
-				/* got the GoodCRC we were expecting */
-				/* do not catch last edges as a new packet */
-				udelay(20);
-				return bit_len;
-			} else {
-				/*
-				 * we have received a good packet
-				 * but not the expected GoodCRC,
-				 * the other side is trying to contact us,
-				 * bail out immediately so we can get the retry.
-				 */
-				return PD_TX_ERR_INV_ACK;
-			}
-		}
-	}
-	/* we failed all the re-transmissions */
-	if (debug_level >= 1)
-		CPRINTF("TX NOACK%d %04x/%d\n", port, header, cnt);
-	return PD_TX_ERR_GOODCRC;
-}
-
-static void send_goodcrc(int port, int id)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_GOOD_CRC, pd[port].power_role,
-			pd[port].data_role, id, 0, 0, 0);
-	int bit_len = prepare_message(port, header, 0, NULL);
-
-	if (pd_start_tx(port, pd[port].polarity, bit_len) < 0)
-		/* another packet recvd before we could send goodCRC */
-		return;
-	pd_tx_done(port, pd[port].polarity);
-	/* Keep RX monitoring on */
-	pd_rx_enable_monitoring(port);
-}
-
-#if 0
-/* TODO: when/how do we trigger this ? */
-static int analyze_rx_bist(int port);
-
-void bist_mode_2_rx(int port)
-{
-	int analyze_bist = 0;
-	int num_bits;
-	timestamp_t start_time;
-
-	/* monitor for incoming packet */
-	pd_rx_enable_monitoring(port);
-
-	/* loop until we start receiving data */
-	start_time.val = get_time().val;
-	while ((get_time().val - start_time.val) < (500*MSEC)) {
-		task_wait_event(10*MSEC);
-		/* incoming packet ? */
-		if (pd_rx_started(port)) {
-			analyze_bist = 1;
-			break;
-		}
-	}
-
-	if (analyze_bist) {
-		/*
-		 * once we start receiving bist data, analyze 40 bytes
-		 * every 10 msec. Continue analyzing until BIST data
-		 * is no longer received. The standard limits the max
-		 * BIST length to 60 msec.
-		 */
-		start_time.val = get_time().val;
-		while ((get_time().val - start_time.val)
-			< (PD_T_BIST_RECEIVE)) {
-			num_bits = analyze_rx_bist(port);
-			pd_rx_complete(port);
-			/*
-			 * If no data was received, then analyze_rx_bist()
-			 * will return a -1 and there is no need to stay
-			 * in this mode
-			 */
-			if (num_bits == -1)
-				break;
-			msleep(10);
-			pd_rx_enable_monitoring(port);
-		}
-	} else {
-		CPRINTF("BIST RX TO\n");
-	}
-}
-#endif
-
-static void bist_mode_2_tx(int port)
-{
-	int bit;
-
-	CPRINTF("BIST 2: p%d\n", port);
-	/*
-	 * build context buffer with 5 bytes, where the data is
-	 * alternating 1's and 0's.
-	 */
-	bit = pd_write_sym(port, 0,   BMC(0x15));
-	bit = pd_write_sym(port, bit, BMC(0x0a));
-	bit = pd_write_sym(port, bit, BMC(0x15));
-	bit = pd_write_sym(port, bit, BMC(0x0a));
-
-	/* start a circular DMA transfer */
-	pd_tx_set_circular_mode(port);
-	pd_start_tx(port, pd[port].polarity, bit);
-
-	task_wait_event(PD_T_BIST_TRANSMIT);
-
-	/* clear dma circular mode, will also stop dma */
-	pd_tx_clear_circular_mode(port);
-	/* finish and cleanup transmit */
-	pd_tx_done(port, pd[port].polarity);
-}
-
-static inline int decode_short(int port, int off, uint16_t *val16)
-{
-	uint32_t w;
-	int end;
-
-	end = pd_dequeue_bits(port, off, 20, &w);
-
-#if 0 /* DEBUG */
-	CPRINTS("%d-%d: %05x %x:%x:%x:%x",
-		off, end, w,
-		dec4b5b[(w >> 15) & 0x1f], dec4b5b[(w >> 10) & 0x1f],
-		dec4b5b[(w >>  5) & 0x1f], dec4b5b[(w >>  0) & 0x1f]);
-#endif
-	*val16 = dec4b5b[w & 0x1f] |
-		(dec4b5b[(w >>  5) & 0x1f] << 4) |
-		(dec4b5b[(w >> 10) & 0x1f] << 8) |
-		(dec4b5b[(w >> 15) & 0x1f] << 12);
-	return end;
-}
-
-static inline int decode_word(int port, int off, uint32_t *val32)
-{
-	off = decode_short(port, off, (uint16_t *)val32);
-	return decode_short(port, off, ((uint16_t *)val32 + 1));
-}
-
-#ifdef CONFIG_COMMON_RUNTIME
-#if 0
-/*
- * TODO: when/how do we trigger this ? Could add custom vendor command
- * to TCPCI to enter bist verification? Is there an easier way?
- */
-static int count_set_bits(int n)
-{
-	int count = 0;
-	while (n) {
-		n &= (n - 1);
-		count++;
-	}
-	return count;
-}
-
-static int analyze_rx_bist(int port)
-{
-	int i = 0, bit = -1;
-	uint32_t w, match;
-	int invalid_bits = 0;
-	int bits_analyzed = 0;
-	static int total_invalid_bits;
-
-	/* dequeue bits until we see a full byte of alternating 1's and 0's */
-	while (i < 10 && (bit < 0 || (w != 0xaa && w != 0x55)))
-		bit = pd_dequeue_bits(port, i++, 8, &w);
-
-	/* if we didn't find any bytes that match criteria, display error */
-	if (i == 10) {
-		CPRINTF("invalid pattern\n");
-		return -1;
-	}
-	/*
-	 * now we know what matching byte we are looking for, dequeue a bunch
-	 * more data and count how many bits differ from expectations.
-	 */
-	match = w;
-	bit = i - 1;
-	for (i = 0; i < 40; i++) {
-		bit = pd_dequeue_bits(port, bit, 8, &w);
-		if (i && (i % 20 == 0))
-			CPRINTF("\n");
-		CPRINTF("%02x ", w);
-		bits_analyzed += 8;
-		invalid_bits += count_set_bits(w ^ match);
-	}
-
-	total_invalid_bits += invalid_bits;
-
-	CPRINTF("\nInvalid: %d/%d\n",
-		invalid_bits, total_invalid_bits);
-	return bits_analyzed;
-}
-#endif
-#endif
-
-int pd_analyze_rx(int port, uint32_t *payload)
-{
-	int bit;
-	char *msg = "---";
-	uint32_t val = 0;
-	union pd_header_sop phs;
-	uint32_t pcrc, ccrc;
-	int p, cnt;
-	uint32_t eop;
-
-	pd_init_dequeue(port);
-
-	/* Detect preamble */
-	bit = pd_find_preamble(port);
-	if (bit == PD_RX_ERR_HARD_RESET || bit == PD_RX_ERR_CABLE_RESET) {
-		/* Hard reset or cable reset */
-		return bit;
-	} else if (bit < 0) {
-		msg = "Preamble";
-		goto packet_err;
-	}
-
-	/* Find the Start Of Packet sequence */
-	while (bit > 0) {
-		bit = pd_dequeue_bits(port, bit, 20, &val);
-#if defined(CONFIG_USB_VPD) || defined(CONFIG_USB_CTVPD)
-		if (val == PD_SOP_PRIME) {
-			break;
-		} else if (val == PD_SOP) {
-			CPRINTF("SOP\n");
-			return PD_RX_ERR_UNSUPPORTED_SOP;
-		} else if (val == PD_SOP_PRIME_PRIME) {
-			CPRINTF("SOP''\n");
-			return PD_RX_ERR_UNSUPPORTED_SOP;
-		}
-#else /* CONFIG_USB_VPD || CONFIG_USB_CTVPD */
-#ifdef CONFIG_USB_PD_DECODE_SOP
-		if (val == PD_SOP || val == PD_SOP_PRIME ||
-						val == PD_SOP_PRIME_PRIME)
-			break;
-#else
-		if (val == PD_SOP) {
-			break;
-		} else if (val == PD_SOP_PRIME) {
-			CPRINTF("SOP'\n");
-			return PD_RX_ERR_UNSUPPORTED_SOP;
-		} else if (val == PD_SOP_PRIME_PRIME) {
-			CPRINTF("SOP''\n");
-			return PD_RX_ERR_UNSUPPORTED_SOP;
-		}
-#endif /* CONFIG_USB_PD_DECODE_SOP */
-#endif /* CONFIG_USB_VPD || CONFIG_USB_CTVPD */
-	}
-	if (bit < 0) {
-#ifdef CONFIG_USB_PD_DECODE_SOP
-		if (val == PD_SOP)
-			msg = "SOP";
-		else if (val == PD_SOP_PRIME)
-			msg = "SOP'";
-		else if (val == PD_SOP_PRIME_PRIME)
-			msg = "SOP''";
-		else
-			msg = "SOP*";
-#else
-		msg = "SOP";
-#endif
-		goto packet_err;
-	}
-
-	phs.head = 0;
-
-	/* read header */
-	bit = decode_short(port, bit, &phs.pd_header);
-
-#ifdef CONFIG_COMMON_RUNTIME
-	mutex_lock(&pd_crc_lock);
-#endif
-
-	crc32_init();
-	crc32_hash16(phs.pd_header);
-	cnt = PD_HEADER_CNT(phs.pd_header);
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	/* Encode message address */
-	if (val == PD_SOP) {
-		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP);
-	} else if (val == PD_SOP_PRIME) {
-		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME);
-	} else if (val == PD_SOP_PRIME_PRIME) {
-		phs.head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME_PRIME);
-	} else {
-		msg = "SOP*";
-		goto packet_err;
-	}
-#endif
-
-	/* read payload data */
-	for (p = 0; p < cnt && bit > 0; p++) {
-		bit = decode_word(port, bit, payload+p);
-		crc32_hash32(payload[p]);
-	}
-	ccrc = crc32_result();
-
-#ifdef CONFIG_COMMON_RUNTIME
-	mutex_unlock(&pd_crc_lock);
-#endif
-
-	if (bit < 0) {
-		msg = "len";
-		goto packet_err;
-	}
-
-	/* check transmitted CRC */
-	bit = decode_word(port, bit, &pcrc);
-	if (bit < 0 || pcrc != ccrc) {
-		msg = "CRC";
-		if (pcrc != ccrc)
-			bit = PD_RX_ERR_CRC;
-		if (debug_level >= 1)
-			CPRINTF("CRC%d %08x <> %08x\n", port, pcrc, ccrc);
-		goto packet_err;
-	}
-
-	/*
-	 * Check EOP. EOP is 5 bits, but last bit may not be able to
-	 * be dequeued, depending on ending state of CC line, so stop
-	 * at 4 bits (assumes last bit is 0).
-	 */
-	bit = pd_dequeue_bits(port, bit, 4, &eop);
-	if (bit < 0 || eop != PD_EOP) {
-		msg = "EOP";
-		goto packet_err;
-	}
-
-	return phs.head;
-packet_err:
-	if (debug_level >= 2)
-		pd_dump_packet(port, msg);
-	else
-		CPRINTF("RXERR%d %s\n", port, msg);
-	return bit;
-}
-
-static void handle_request(int port, uint16_t head)
-{
-	int cnt = PD_HEADER_CNT(head);
-
-	if (PD_HEADER_TYPE(head) != PD_CTRL_GOOD_CRC || cnt)
-		send_goodcrc(port, PD_HEADER_ID(head));
-	else
-		/* keep RX monitoring on to avoid collisions */
-		pd_rx_enable_monitoring(port);
-}
-
-/* Convert CC voltage to CC status */
-static int cc_voltage_to_status(int port, int cc_volt, int cc_sel)
-{
-	/* If we have a pull-up, then we are source, check for Rd. */
-	if (pd[port].cc_pull == TYPEC_CC_RP) {
-		if (CC_NC(port, cc_volt, cc_sel))
-			return TYPEC_CC_VOLT_OPEN;
-		else if (CC_RA(port, cc_volt, cc_sel))
-			return TYPEC_CC_VOLT_RA;
-		else
-			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
-	}
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	else if (pd[port].cc_pull == TYPEC_CC_RD) {
-		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_3_0;
-		else if (cc_volt >= TYPE_C_SRC_1500_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_1_5;
-		else if (CC_RP(cc_volt))
-			return TYPEC_CC_VOLT_RP_DEF;
-		else
-			return TYPEC_CC_VOLT_OPEN;
-	}
-#endif
-	/* If we are open, then always return 0 */
-	else
-		return 0;
-}
-
-static void alert(int port, int mask)
-{
-	/* Always update the Alert status register */
-	pd[port].alert |= mask;
-	/*
-	 * Only send interrupt to TCPM if corresponding
-	 * bit in the alert_enable register is set.
-	 */
-	if (pd[port].alert_mask & mask)
-		tcpc_alert(port);
-}
-
-int tcpc_run(int port, int evt)
-{
-	int cc, i, res;
-
-	/* Don't do anything when port is not available */
-	if (port >= board_get_usb_pd_port_count())
-		return -1;
-
-	/* incoming packet ? */
-	if (pd_rx_started(port) && pd[port].rx_enabled) {
-		/* Get message and place at RX buffer head */
-		res = pd[port].rx_head[pd[port].rx_buf_head] =
-			pd_analyze_rx(port,
-				pd[port].rx_payload[pd[port].rx_buf_head]);
-		pd_rx_complete(port);
-
-		/*
-		 * If there is space in buffer, then increment head to keep
-		 * the message and send goodCRC. If this is a hard reset,
-		 * send alert regardless of rx buffer status. Else if there is
-		 * no space in buffer, then do not send goodCRC and drop
-		 * message.
-		 */
-		if (res > 0 && !rx_buf_is_full(port)) {
-			rx_buf_increment(port, &pd[port].rx_buf_head);
-			handle_request(port, res);
-			alert(port, TCPC_REG_ALERT_RX_STATUS);
-		} else if (res == PD_RX_ERR_HARD_RESET) {
-			alert(port, TCPC_REG_ALERT_RX_HARD_RST);
-		}
-	}
-
-	/* outgoing packet ? */
-	if ((evt & PD_EVENT_TX) && pd[port].rx_enabled) {
-		switch (pd[port].tx_type) {
-#if defined(CONFIG_USB_VPD) || defined(CONFIG_USB_CTVPD)
-		case TCPCI_MSG_SOP_PRIME:
-#else
-		case TCPCI_MSG_SOP:
-#endif
-			res = send_validate_message(port,
-					pd[port].tx_head,
-					pd[port].tx_data);
-			break;
-		case TCPCI_MSG_TX_BIST_MODE_2:
-			bist_mode_2_tx(port);
-			res = 0;
-			break;
-		case TCPCI_MSG_TX_HARD_RESET:
-			res = send_hard_reset(port);
-			break;
-		default:
-			res = PD_TX_ERR_DISABLED;
-			break;
-		}
-
-		/* send appropriate alert for tx completion */
-		if (res >= 0)
-			alert(port, TCPC_REG_ALERT_TX_SUCCESS);
-		else if (res == PD_TX_ERR_GOODCRC)
-			alert(port, TCPC_REG_ALERT_TX_FAILED);
-		else
-			alert(port, TCPC_REG_ALERT_TX_DISCARDED);
-	} else {
-		/* If we have nothing to transmit, then sample CC lines */
-
-		/* CC pull changed, wait 1ms for CC voltage to stabilize */
-		if (evt & PD_EVENT_CC)
-			usleep(MSEC);
-
-		/* check CC lines */
-		for (i = 0; i < 2; i++) {
-			/* read CC voltage */
-			cc = pd_adc_read(port, i);
-
-			/* convert voltage to status, and check status change */
-			cc = cc_voltage_to_status(port, cc, i);
-			if (pd[port].cc_status[i] != cc) {
-				pd[port].cc_status[i] = cc;
-				alert(port, TCPC_REG_ALERT_CC_STATUS);
-			}
-		}
-	}
-
-	/* make sure PD monitoring is enabled to wake on PD RX */
-	if (pd[port].rx_enabled)
-		pd_rx_enable_monitoring(port);
-
-#ifdef TCPC_LOW_POWER
-	/*
-	 * If we are presenting Rd with no connection, and timestamp is
-	 * past the low power timestamp, then we don't need to sample
-	 * CC lines as often. In this case, our connection delay should not
-	 * actually increased because we will get an interrupt on VBUS detect.
-	 */
-	return (get_time().val >= pd[port].low_power_ts.val &&
-		pd[port].cc_pull == TYPEC_CC_RD &&
-		cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1]))
-		       ? 200 * MSEC
-		       : 10 * MSEC;
-#else
-	return 10*MSEC;
-#endif
-}
-
-#if !defined(CONFIG_USB_POWER_DELIVERY)
-void pd_task(void *u)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-	int timeout = 10*MSEC;
-	int evt;
-
-	/* initialize phy task */
-	tcpc_init(port);
-
-	/* we are now initialized */
-	pd[port].power_status &= ~TCPC_REG_POWER_STATUS_UNINIT;
-
-	while (1) {
-		/* wait for next event/packet or timeout expiration */
-		evt = task_wait_event(timeout);
-
-		/* run phy task once */
-		timeout = tcpc_run(port, evt);
-	}
-}
-#endif
-
-void pd_rx_event(int port)
-{
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-}
-
-int tcpc_alert_status(int port, int *alert)
-{
-	/* return the value of the TCPC Alert register */
-	uint16_t ret = pd[port].alert;
-	*alert = ret;
-	return EC_SUCCESS;
-}
-
-int tcpc_alert_status_clear(int port, uint16_t mask)
-{
-	/*
-	 * If the RX status alert is attempting to be cleared, then increment
-	 * rx buffer tail pointer. if the RX buffer is not empty, then keep
-	 * the RX status alert active.
-	 */
-	if (mask & TCPC_REG_ALERT_RX_STATUS) {
-		if (!rx_buf_is_empty(port)) {
-			rx_buf_increment(port, &pd[port].rx_buf_tail);
-			if (!rx_buf_is_empty(port))
-				/* buffer is not empty, keep alert active */
-				mask &= ~TCPC_REG_ALERT_RX_STATUS;
-		}
-	}
-
-	/* clear only the bits specified by the TCPM */
-	pd[port].alert &= ~mask;
-#ifndef CONFIG_USB_POWER_DELIVERY
-	/* Set Alert# inactive if all alert bits clear */
-	if (!pd[port].alert)
-		tcpc_alert_clear(port);
-#endif
-	return EC_SUCCESS;
-}
-
-int tcpc_alert_mask_set(int port, uint16_t mask)
-{
-	/* Update the alert mask as specificied by the TCPM */
-	pd[port].alert_mask = mask;
-	return EC_SUCCESS;
-}
-
-int tcpc_set_cc(int port, int pull)
-{
-	/* If CC pull resistor not changing, then nothing to do */
-	if (pd[port].cc_pull == pull)
-		return EC_SUCCESS;
-
-	/* Change CC pull resistor */
-	pd[port].cc_pull = pull;
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	pd_set_host_mode(port, pull == TYPEC_CC_RP);
-#endif
-
-#ifdef TCPC_LOW_POWER
-	/*
-	 * Reset the low power timestamp every time CC termination toggles,
-	 * because we only want to go into low power mode when we are not
-	 * dual-role toggling.
-	 */
-	pd[port].low_power_ts.val = get_time().val +
-					2*(PD_T_DRP_SRC + PD_T_DRP_SNK);
-#endif
-
-	/*
-	 * Before CC pull can be changed and the task can read the new
-	 * status, we should set the CC status to open, in case TCPM
-	 * asks before it is known for sure.
-	 */
-	pd[port].cc_status[0] = TYPEC_CC_VOLT_OPEN;
-	pd[port].cc_status[1] = pd[port].cc_status[0];
-
-	/* Wake the PD phy task with special CC event mask */
-	/* TODO: use top case if no TCPM on same CPU */
-#ifdef CONFIG_USB_POWER_DELIVERY
-	tcpc_run(port, PD_EVENT_CC);
-#else
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-#endif
-	return EC_SUCCESS;
-}
-
-int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	*cc2 = pd[port].cc_status[1];
-	*cc1 = pd[port].cc_status[0];
-
-	return EC_SUCCESS;
-}
-
-int board_select_rp_value(int port, int rp) __attribute__((weak));
-
-int tcpc_select_rp_value(int port, int rp)
-{
-	if (board_select_rp_value)
-		return board_select_rp_value(port, rp);
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-}
-
-int tcpc_set_polarity(int port, int polarity)
-{
-	pd[port].polarity = polarity;
-	pd_select_polarity(port, pd[port].polarity);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS
-static int tcpc_set_power_status(int port, int vbus_present)
-{
-	/* Update VBUS present bit */
-	if (vbus_present)
-		pd[port].power_status |= TCPC_REG_POWER_STATUS_VBUS_PRES;
-	else
-		pd[port].power_status &= ~TCPC_REG_POWER_STATUS_VBUS_PRES;
-
-	/* Set bit Port Power Status bit in Alert register */
-	if (pd[port].power_status_mask & TCPC_REG_POWER_STATUS_VBUS_PRES)
-		alert(port, TCPC_REG_ALERT_POWER_STATUS);
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_USB_PD_TCPC_TRACK_VBUS */
-
-int tcpc_set_power_status_mask(int port, uint8_t mask)
-{
-	pd[port].power_status_mask = mask;
-	return EC_SUCCESS;
-}
-
-int tcpc_set_vconn(int port, int enable)
-{
-#ifdef CONFIG_USBC_VCONN
-	pd_set_vconn(port, pd[port].polarity, enable);
-#endif
-	return EC_SUCCESS;
-}
-
-int tcpc_set_rx_enable(int port, int enable)
-{
-#if defined(CONFIG_LOW_POWER_IDLE) && !defined(CONFIG_USB_POWER_DELIVERY)
-	int i;
-#endif
-	pd[port].rx_enabled = enable;
-
-	if (!enable)
-		pd_rx_disable_monitoring(port);
-
-#if defined(CONFIG_LOW_POWER_IDLE) && !defined(CONFIG_USB_POWER_DELIVERY)
-	/* If any PD port is connected, then disable deep sleep */
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i)
-		if (pd[i].rx_enabled)
-			break;
-
-	if (i == board_get_usb_pd_port_count())
-		enable_sleep(SLEEP_MASK_USB_PD);
-	else
-		disable_sleep(SLEEP_MASK_USB_PD);
-#endif
-	return EC_SUCCESS;
-}
-
-int tcpc_transmit(int port, enum tcpci_msg_type type, uint16_t header,
-		  const uint32_t *data)
-{
-	/* Store data to transmit and wake task to send it */
-	pd[port].tx_type = type;
-	pd[port].tx_head = header;
-	pd[port].tx_data = data;
-	/* TODO: use top case if no TCPM on same CPU */
-#ifdef CONFIG_USB_POWER_DELIVERY
-	tcpc_run(port, PD_EVENT_TX);
-#else
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
-#endif
-	return EC_SUCCESS;
-}
-
-int tcpc_set_msg_header(int port, int power_role, int data_role)
-{
-	pd[port].power_role = power_role;
-	pd[port].data_role = data_role;
-
-	return EC_SUCCESS;
-}
-
-int tcpc_get_message(int port, uint32_t *payload, int *head)
-{
-	/* Get message at tail of RX buffer */
-	int idx = pd[port].rx_buf_tail;
-
-	memcpy(payload, pd[port].rx_payload[idx],
-	       sizeof(pd[port].rx_payload[idx]));
-	*head = pd[port].rx_head[idx];
-	return EC_SUCCESS;
-}
-
-void tcpc_pre_init(void)
-{
-	int i;
-
-	/* Mark as uninitialized */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		pd[i].power_status |= TCPC_REG_POWER_STATUS_UNINIT |
-				      TCPC_REG_POWER_STATUS_VBUS_DET;
-}
-/* Must be prioritized above i2c init */
-DECLARE_HOOK(HOOK_INIT, tcpc_pre_init, HOOK_PRIO_INIT_I2C - 1);
-
-void tcpc_init(int port)
-{
-	int i;
-
-	if (port >= board_get_usb_pd_port_count())
-		return;
-
-	/* Initialize physical layer */
-	pd_hw_init(port, PD_ROLE_DEFAULT(port));
-	pd[port].cc_pull = PD_ROLE_DEFAULT(port) ==
-		PD_ROLE_SOURCE ? TYPEC_CC_RP : TYPEC_CC_RD;
-#ifdef TCPC_LOW_POWER
-	/* Don't use low power immediately after boot */
-	pd[port].low_power_ts.val = get_time().val + SECOND;
-#endif
-
-	/* make sure PD monitoring is disabled initially */
-	pd[port].rx_enabled = 0;
-
-	/* make initial readings of CC voltages */
-	for (i = 0; i < 2; i++) {
-		pd[port].cc_status[i] = cc_voltage_to_status(port,
-							     pd_adc_read(port, i),
-							     i);
-	}
-
-#ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	tcpc_set_power_status(port, !gpio_get_level(port ?
-			      GPIO_USB_C1_VBUS_WAKE_L :
-			      GPIO_USB_C0_VBUS_WAKE_L));
-#else
-	tcpc_set_power_status(port, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT >= 2 */
-#endif /* CONFIG_USB_PD_TCPC_TRACK_VBUS */
-
-	/* set default alert and power mask register values */
-	pd[port].alert_mask = TCPC_REG_ALERT_MASK_ALL;
-	pd[port].power_status_mask = TCPC_REG_POWER_STATUS_MASK_ALL;
-
-	/* set power status alert since the UNINIT bit has been set */
-	alert(port, TCPC_REG_ALERT_POWER_STATUS);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS
-void pd_vbus_evt_p0(enum gpio_signal signal)
-{
-	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C0),
-				 !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
-	task_wake(TASK_ID_PD_C0);
-}
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-void pd_vbus_evt_p1(enum gpio_signal signal)
-{
-	if (board_get_usb_pd_port_count() == 1)
-		return;
-
-	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C1),
-				 !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
-	task_wake(TASK_ID_PD_C1);
-}
-#endif /* PD_PORT_COUNT >= 2 */
-#endif /* CONFIG_USB_PD_TCPC_TRACK_VBUS */
-
-#ifndef CONFIG_USB_POWER_DELIVERY
-static void tcpc_i2c_write(int port, int reg, int len, uint8_t *payload)
-{
-	uint16_t alert;
-
-	/* If we are not yet initialized, ignore any write command */
-	if (pd[port].power_status & TCPC_REG_POWER_STATUS_UNINIT)
-		return;
-
-	switch (reg) {
-	case TCPC_REG_ROLE_CTRL:
-		tcpc_set_cc(port, TCPC_REG_ROLE_CTRL_CC1(payload[1]));
-		break;
-	case TCPC_REG_POWER_CTRL:
-		tcpc_set_vconn(port, TCPC_REG_POWER_CTRL_VCONN(payload[1]));
-		break;
-	case TCPC_REG_TCPC_CTRL:
-		tcpc_set_polarity(port,
-				  TCPC_REG_TCPC_CTRL_POLARITY(payload[1]));
-		break;
-	case TCPC_REG_MSG_HDR_INFO:
-		tcpc_set_msg_header(port,
-				    TCPC_REG_MSG_HDR_INFO_PROLE(payload[1]),
-				    TCPC_REG_MSG_HDR_INFO_DROLE(payload[1]));
-		break;
-	case TCPC_REG_ALERT:
-		alert = payload[1];
-		alert |= (payload[2] << 8);
-		/* clear alert bits specified by the TCPM */
-		tcpc_alert_status_clear(port, alert);
-		break;
-	case TCPC_REG_ALERT_MASK:
-		alert = payload[1];
-		alert |= (payload[2] << 8);
-		tcpc_alert_mask_set(port, alert);
-		break;
-	case TCPC_REG_RX_DETECT:
-		tcpc_set_rx_enable(port, payload[1] &
-					 TCPC_REG_RX_DETECT_SOP_HRST_MASK);
-		break;
-	case TCPC_REG_POWER_STATUS_MASK:
-		tcpc_set_power_status_mask(port, payload[1]);
-		break;
-	case TCPC_REG_TX_HDR:
-		pd[port].tx_head = (payload[2] << 8) | payload[1];
-		break;
-	case TCPC_REG_TX_DATA:
-		memcpy(pd[port].tx_payload, &payload[1], len - 1);
-		break;
-	case TCPC_REG_TRANSMIT:
-		tcpc_transmit(port, TCPC_REG_TRANSMIT_TYPE(payload[1]),
-			      pd[port].tx_head, pd[port].tx_payload);
-		break;
-	}
-}
-
-static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-	int alert;
-
-	switch (reg) {
-	case TCPC_REG_VENDOR_ID:
-		*(uint16_t *)payload = USB_VID_GOOGLE;
-		return 2;
-	case TCPC_REG_CC_STATUS:
-		tcpc_get_cc(port, &cc1, &cc2);
-		payload[0] = TCPC_REG_CC_STATUS_SET(
-				pd[port].cc_pull == TYPEC_CC_RD,
-				pd[port].cc_status[0], pd[port].cc_status[1]);
-		return 1;
-	case TCPC_REG_ROLE_CTRL:
-		payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0,
-						    pd[port].cc_pull,
-						    pd[port].cc_pull);
-		return 1;
-	case TCPC_REG_TCPC_CTRL:
-		payload[0] = TCPC_REG_TCPC_CTRL_SET(pd[port].polarity);
-		return 1;
-	case TCPC_REG_MSG_HDR_INFO:
-		payload[0] = TCPC_REG_MSG_HDR_INFO_SET(pd[port].data_role,
-						       pd[port].power_role);
-		return 1;
-	case TCPC_REG_RX_DETECT:
-		payload[0] = pd[port].rx_enabled ?
-				TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0;
-		return 1;
-	case TCPC_REG_ALERT:
-		tcpc_alert_status(port, &alert);
-		payload[0] = alert & 0xff;
-		payload[1] = (alert >> 8) & 0xff;
-		return 2;
-	case TCPC_REG_ALERT_MASK:
-		payload[0] = pd[port].alert_mask & 0xff;
-		payload[1] = (pd[port].alert_mask >> 8) & 0xff;
-		return 2;
-	case TCPC_REG_RX_BYTE_CNT:
-		payload[0] = 3 + 4 *
-			PD_HEADER_CNT(pd[port].rx_head[pd[port].rx_buf_tail]);
-		return 1;
-	case TCPC_REG_RX_HDR:
-		payload[0] = pd[port].rx_head[pd[port].rx_buf_tail] & 0xff;
-		payload[1] =
-			(pd[port].rx_head[pd[port].rx_buf_tail] >> 8) & 0xff;
-		return 2;
-	case TCPC_REG_RX_DATA:
-		memcpy(payload, pd[port].rx_payload[pd[port].rx_buf_tail],
-		       sizeof(pd[port].rx_payload[pd[port].rx_buf_tail]));
-		return sizeof(pd[port].rx_payload[pd[port].rx_buf_tail]);
-	case TCPC_REG_POWER_STATUS:
-		payload[0] = pd[port].power_status;
-		return 1;
-	case TCPC_REG_POWER_STATUS_MASK:
-		payload[0] = pd[port].power_status_mask;
-		return 1;
-	case TCPC_REG_TX_HDR:
-		payload[0] = pd[port].tx_head & 0xff;
-		payload[1] = (pd[port].tx_head >> 8) & 0xff;
-		return 2;
-	case TCPC_REG_TX_DATA:
-		memcpy(payload, pd[port].tx_payload,
-		       sizeof(pd[port].tx_payload));
-		return sizeof(pd[port].tx_payload);
-	default:
-		return 0;
-	}
-}
-
-void tcpc_i2c_process(int read, int port, int len, uint8_t *payload,
-		      void (*send_response)(int))
-{
-	int i, reg;
-
-	if (debug_level >= 1) {
-		CPRINTF("tcpci p%d: ", port);
-		for (i = 0; i < len; i++)
-			CPRINTF("0x%02x ", payload[i]);
-		CPRINTF("\n");
-	}
-
-	/* length must always be at least 1 */
-	if (len == 0) {
-		/*
-		 * if this is a read, we must call send_response() for
-		 * i2c transaction to finishe properly
-		 */
-		if (read)
-			(*send_response)(0);
-	}
-
-	/* if this is a write, length must be at least 2 */
-	if (!read && len < 2)
-		return;
-
-	/* register is always first byte */
-	reg = payload[0];
-
-	/* perform read or write */
-	if (read) {
-		len = tcpc_i2c_read(port, reg, payload);
-		(*send_response)(len);
-	} else {
-		tcpc_i2c_write(port, reg, len, payload);
-	}
-}
-#endif
-
-#ifdef CONFIG_COMMON_RUNTIME
-static int command_tcpc(int argc, char **argv)
-{
-	int port;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "dump")) {
-		int level;
-
-		if (argc < 3)
-			ccprintf("lvl: %d\n", debug_level);
-		else {
-			level = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM2;
-			debug_level = level;
-		}
-		return EC_SUCCESS;
-	}
-
-	/* command: pd <port> <subcmd> [args] */
-	port = strtoi(argv[1], &e, 10);
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(argv[2], "clock")) {
-		int freq;
-
-		if (argc < 4)
-			return EC_ERROR_PARAM2;
-
-		freq = strtoi(argv[3], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		pd_set_clock(port, freq);
-		ccprintf("set TX frequency to %d Hz\n", freq);
-		return EC_SUCCESS;
-	} else if (!strncasecmp(argv[2], "state", 5)) {
-		ccprintf("Port C%d, %s - CC:%d, CC0:%d, CC1:%d\n"
-			 "Alert: 0x%02x Mask: 0x%04x\n"
-			 "Power Status: 0x%02x Mask: 0x%02x\n", port,
-			 pd[port].rx_enabled ? "Ena" : "Dis",
-			 pd[port].cc_pull,
-			 pd[port].cc_status[0], pd[port].cc_status[1],
-			 pd[port].alert, pd[port].alert_mask,
-			 pd[port].power_status, pd[port].power_status_mask);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(tcpc, command_tcpc,
-			"dump [0|1]\n\t<port> [clock|state]",
-			"Type-C Port Controller");
-#endif
diff --git a/common/usb_port_power_dumb.c b/common/usb_port_power_dumb.c
deleted file mode 100644
index 09c7e29033..0000000000
--- a/common/usb_port_power_dumb.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB charging control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "usb_charge.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-static uint8_t charge_mode[USB_PORT_COUNT];
-
-static void usb_port_set_enabled(int port_id, int en)
-{
-	gpio_set_level(usb_port_enable[port_id], en);
-	charge_mode[port_id] = en;
-}
-
-__maybe_unused static void usb_port_all_ports_on(void)
-{
-	int i;
-	for (i = 0; i < USB_PORT_COUNT; i++)
-		usb_port_set_enabled(i, 1);
-}
-
-static void usb_port_all_ports_off(void)
-{
-	int i;
-	for (i = 0; i < USB_PORT_COUNT; i++)
-		usb_port_set_enabled(i, 0);
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-int usb_charge_set_mode(int port_id, enum usb_charge_mode mode,
-			enum usb_suspend_charge inhibit_charge)
-{
-	CPRINTS("USB port p%d %d", port_id, mode);
-
-	if (port_id < 0 || port_id >= USB_PORT_COUNT)
-		return EC_ERROR_INVAL;
-
-	switch (mode) {
-	case USB_CHARGE_MODE_DISABLED:
-		usb_port_set_enabled(port_id, 0);
-		break;
-	case USB_CHARGE_MODE_ENABLED:
-		usb_port_set_enabled(port_id, 1);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static enum ec_status
-usb_port_command_set_mode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_charge_set_mode *p = args->params;
-
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-		p->inhibit_charge) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_port_command_set_mode,
-		     EC_VER_MASK(0));
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_set_mode(int argc, char **argv)
-{
-	int port_id = -1;
-	int mode = -1;
-	int i;
-	char *e;
-
-	switch (argc) {
-	case 3:
-		port_id = strtoi(argv[1], &e, 0);
-		if (*e || port_id < 0 || port_id >= USB_PORT_COUNT)
-			return EC_ERROR_PARAM1;
-
-		if (!parse_bool(argv[2], &mode))
-			return EC_ERROR_PARAM2;
-
-		usb_port_set_enabled(port_id, mode);
-		/* fallthrough */
-	case 1:
-		for (i = 0; i < USB_PORT_COUNT; i++)
-			ccprintf("Port %d: %s\n",
-				 i, charge_mode[i] ? "on" : "off");
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_PARAM_COUNT;
-}
-DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode,
-			"[<port> <on | off>]",
-			"Set USB charge mode");
-
-
-/*****************************************************************************/
-/* Hooks */
-
-static void usb_port_preserve_state(void)
-{
-	system_add_jump_tag(USB_SYSJUMP_TAG, USB_HOOK_VERSION,
-			    sizeof(charge_mode), charge_mode);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, usb_port_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void usb_port_init(void)
-{
-	const uint8_t *prev;
-	int version, size, i;
-
-	prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
-	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
-		usb_port_all_ports_off();
-		return;
-	}
-
-	for (i = 0; i < USB_PORT_COUNT; i++)
-		usb_port_set_enabled(i, prev[i]);
-}
-DECLARE_HOOK(HOOK_INIT, usb_port_init, HOOK_PRIO_DEFAULT);
-
-#ifndef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-static void usb_port_startup(void)
-{
-	/* Turn on USB ports on as we go into S0 from S5. */
-	usb_port_all_ports_on();
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_port_startup, HOOK_PRIO_DEFAULT);
-
-static void usb_port_shutdown(void)
-{
-	/* Turn on USB ports off as we go back to S5. */
-	usb_port_all_ports_off();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_port_shutdown, HOOK_PRIO_DEFAULT);
-#endif  /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */
diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c
deleted file mode 100644
index 170180cbab..0000000000
--- a/common/usb_port_power_smart.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB charging control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "usb_charge.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-#ifndef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2
-#endif
-
-struct charge_mode_t {
-	uint8_t mode:7;
-	uint8_t inhibit_charging_in_suspend:1;
-} __pack;
-
-static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT];
-
-#ifdef CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-/*
- * If we only support CDP and SDP, the control signals are hard-wired so
- * there's nothing to do.  The only to do is set ILIM_SEL.
- */
-static void usb_charge_set_control_mode(int port_id, int mode) {}
-#else /* !defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */
-static void usb_charge_set_control_mode(int port_id, int mode)
-{
-#ifdef CONFIG_USB_PORT_POWER_SMART_SIMPLE
-	/*
-	 * One single shared control signal, so the last mode set to either
-	 * port wins.  Also, only CTL1 can be set; the other pins are
-	 * hard-wired.
-	 */
-	gpio_or_ioex_set_level(GPIO_USB_CTL1, mode & 0x4);
-#else
-	if (port_id == 0) {
-		gpio_or_ioex_set_level(GPIO_USB1_CTL1, mode & 0x4);
-		gpio_or_ioex_set_level(GPIO_USB1_CTL2, mode & 0x2);
-		gpio_or_ioex_set_level(GPIO_USB1_CTL3, mode & 0x1);
-	} else {
-		gpio_or_ioex_set_level(GPIO_USB2_CTL1, mode & 0x4);
-		gpio_or_ioex_set_level(GPIO_USB2_CTL2, mode & 0x2);
-		gpio_or_ioex_set_level(GPIO_USB2_CTL3, mode & 0x1);
-	}
-#endif /* defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) */
-}
-#endif /* defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */
-
-static void usb_charge_set_enabled(int port_id, int en)
-{
-	ASSERT(port_id < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT);
-	gpio_or_ioex_set_level(usb_port_enable[port_id], en);
-}
-
-static void usb_charge_set_ilim(int port_id, int sel)
-{
-	int ilim_sel;
-
-#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) ||	\
-	defined(CONFIG_USB_PORT_POWER_SMART_INVERTED)
-	/* ILIM_SEL is inverted. */
-	sel = !sel;
-#endif
-
-	ilim_sel = GPIO_USB1_ILIM_SEL;
-#if !defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) && \
-	CONFIG_USB_PORT_POWER_SMART_PORT_COUNT == 2
-	if (port_id != 0)
-		ilim_sel = GPIO_USB2_ILIM_SEL;
-#endif
-
-	gpio_or_ioex_set_level(ilim_sel, sel);
-}
-
-static void usb_charge_all_ports_ctrl(enum usb_charge_mode mode)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
-}
-
-int usb_charge_set_mode(int port_id, enum usb_charge_mode mode,
-			enum usb_suspend_charge inhibit_charge)
-{
-	CPRINTS("USB charge p%d m%d i%d", port_id, mode, inhibit_charge);
-
-	if (port_id >= CONFIG_USB_PORT_POWER_SMART_PORT_COUNT)
-		return EC_ERROR_INVAL;
-
-	if (mode == USB_CHARGE_MODE_DEFAULT)
-		mode = CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE;
-
-	switch (mode) {
-	case USB_CHARGE_MODE_DISABLED:
-		usb_charge_set_enabled(port_id, 0);
-		break;
-	case USB_CHARGE_MODE_SDP2:
-		usb_charge_set_control_mode(port_id, 7);
-		usb_charge_set_ilim(port_id, 0);
-		usb_charge_set_enabled(port_id, 1);
-		break;
-	case USB_CHARGE_MODE_CDP:
-		usb_charge_set_control_mode(port_id, 7);
-		usb_charge_set_ilim(port_id, 1);
-		usb_charge_set_enabled(port_id, 1);
-		break;
-#ifndef CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-	case USB_CHARGE_MODE_DCP_SHORT:
-		usb_charge_set_control_mode(port_id, 4);
-		usb_charge_set_enabled(port_id, 1);
-		break;
-#endif /* !defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	charge_mode[port_id].mode = mode;
-	charge_mode[port_id].inhibit_charging_in_suspend = inhibit_charge;
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_set_mode(int argc, char **argv)
-{
-	int port_id = -1;
-	int mode = -1, inhibit_charge = 0;
-	char *e;
-	int i;
-
-	if (argc == 1) {
-		for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-			ccprintf("Port %d: %d,%d\n", i, charge_mode[i].mode,
-				charge_mode[i].inhibit_charging_in_suspend);
-		return EC_SUCCESS;
-	}
-
-	if (argc != 3 && argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	port_id = strtoi(argv[1], &e, 0);
-	if (*e || port_id < 0 ||
-	    port_id >= CONFIG_USB_PORT_POWER_SMART_PORT_COUNT)
-		return EC_ERROR_PARAM1;
-
-	mode = strtoi(argv[2], &e, 0);
-	if (*e || mode < 0 || mode >= USB_CHARGE_MODE_COUNT)
-		return EC_ERROR_PARAM2;
-
-	if (argc == 4) {
-		inhibit_charge = strtoi(argv[3], &e, 0);
-		if (*e || (inhibit_charge != 0 && inhibit_charge != 1))
-			return EC_ERROR_PARAM3;
-	}
-
-	return usb_charge_set_mode(port_id, mode, inhibit_charge);
-}
-DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode,
-			"[<port> <0 | 1 | 2 | 3> [<0 | 1>]]",
-			"Set USB charge mode");
-
-/*****************************************************************************/
-/* Host commands */
-
-static enum ec_status
-usb_charge_command_set_mode(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_charge_set_mode *p = args->params;
-
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-				p->inhibit_charge) != EC_SUCCESS)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_charge_command_set_mode,
-		     EC_VER_MASK(0));
-
-/*****************************************************************************/
-/* Hooks */
-
-static void usb_charge_preserve_state(void)
-{
-	system_add_jump_tag(USB_SYSJUMP_TAG, USB_HOOK_VERSION,
-			    sizeof(charge_mode), charge_mode);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, usb_charge_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void usb_charge_init(void)
-{
-	const struct charge_mode_t *prev;
-	int version, size, i;
-
-	prev = (const struct charge_mode_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
-
-	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
-		usb_charge_all_ports_ctrl(USB_CHARGE_MODE_DISABLED);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i, prev[i].mode,
-			prev[i].inhibit_charging_in_suspend);
-}
-DECLARE_HOOK(HOOK_INIT, usb_charge_init, HOOK_PRIO_DEFAULT);
-
-static void usb_charge_resume(void)
-{
-	int i;
-
-	/* Turn on USB ports on as we go into S0 from S3 or S5. */
-	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i,
-			CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			charge_mode[i].inhibit_charging_in_suspend);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, usb_charge_resume, HOOK_PRIO_DEFAULT);
-
-static void usb_charge_suspend(void)
-{
-	int i;
-
-	/*
-	 * Inhibit charging during suspend if the inhibit_charging_in_suspend
-	 * is set to 1.
-	 */
-	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		if (charge_mode[i].inhibit_charging_in_suspend)
-			usb_charge_set_enabled(i, 0 /* disabled */);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, usb_charge_suspend, HOOK_PRIO_DEFAULT);
-
-static void usb_charge_shutdown(void)
-{
-	/* Turn on USB ports off as we go back to S5. */
-	usb_charge_all_ports_ctrl(USB_CHARGE_MODE_DISABLED);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_charge_shutdown, HOOK_PRIO_DEFAULT);
diff --git a/common/usb_update.c b/common/usb_update.c
deleted file mode 100644
index 3b307ede9a..0000000000
--- a/common/usb_update.c
+++ /dev/null
@@ -1,594 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "byteorder.h"
-#include "common.h"
-#include "console.h"
-#include "consumer.h"
-#include "curve25519.h"
-#include "flash.h"
-#include "queue_policies.h"
-#include "host_command.h"
-#include "rollback.h"
-#include "rwsig.h"
-#include "sha256.h"
-#include "system.h"
-#include "uart.h"
-#include "update_fw.h"
-#include "usb-stream.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-/*
- * This file is an adaptation layer between the USB interface and the firmware
- * update engine. The engine expects to receive long blocks of data, 1K or so
- * in size, prepended by the offset where the data needs to be programmed into
- * the flash and a 4 byte integrity check value.
- *
- * The USB transfer, on the other hand, operates on much shorter chunks of
- * data, typically 64 bytes in this case. This module reassembles firmware
- * programming blocks from the USB chunks, and invokes the programmer passing
- * it the full block.
- *
- * The programmer reports results by putting the return value into the same
- * buffer where the block was passed in. This wrapper retrieves the
- * programmer's return value, and sends it back to the host. The return value
- * is usually one byte in size, the only exception is the connection
- * establishment phase where the return value is 16 bytes in size.
- *
- * In the end of the successful image transfer and programming, the host sends
- * the reset command, and the device reboots itself.
- */
-
-struct consumer const update_consumer;
-struct usb_stream_config const usb_update;
-
-static struct queue const update_to_usb = QUEUE_DIRECT(64, uint8_t,
-						     null_producer,
-						     usb_update.consumer);
-static struct queue const usb_to_update = QUEUE_DIRECT(64, uint8_t,
-						     usb_update.producer,
-						     update_consumer);
-
-USB_STREAM_CONFIG_FULL(usb_update,
-		       USB_IFACE_UPDATE,
-		       USB_CLASS_VENDOR_SPEC,
-		       USB_SUBCLASS_GOOGLE_UPDATE,
-		       USB_PROTOCOL_GOOGLE_UPDATE,
-		       USB_STR_UPDATE_NAME,
-		       USB_EP_UPDATE,
-		       USB_MAX_PACKET_SIZE,
-		       USB_MAX_PACKET_SIZE,
-		       usb_to_update,
-		       update_to_usb)
-
-
-/* The receiver can be in one of the states below. */
-enum rx_state {
-	rx_idle,	   /* Nothing happened yet. */
-	rx_inside_block,   /* Assembling a block to pass to the programmer. */
-	rx_outside_block,  /* Waiting for the next block to start or for the
-			      reset command. */
-};
-
-enum rx_state rx_state_ = rx_idle;
-static uint8_t block_buffer[sizeof(struct update_command) +
-			    CONFIG_UPDATE_PDU_SIZE];
-static uint32_t block_size;
-static uint32_t block_index;
-
-#ifdef CONFIG_USB_PAIRING
-#define KEY_CONTEXT "device-identity"
-
-static int pair_challenge(struct pair_challenge *challenge)
-{
-	uint8_t response;
-
-	/* Scratchpad for device secret and x25519 public/shared key. */
-	uint8_t tmp[32];
-	BUILD_ASSERT(sizeof(tmp) >= X25519_PUBLIC_VALUE_LEN);
-	BUILD_ASSERT(sizeof(tmp) >= X25519_PRIVATE_KEY_LEN);
-	BUILD_ASSERT(sizeof(tmp) >= CONFIG_ROLLBACK_SECRET_SIZE);
-
-	/* Scratchpad for device_private and authenticator. */
-	uint8_t tmp2[32];
-	BUILD_ASSERT(sizeof(tmp2) >= X25519_PRIVATE_KEY_LEN);
-	BUILD_ASSERT(sizeof(tmp2) >= SHA256_DIGEST_SIZE);
-
-	/* tmp = device_secret */
-	if (rollback_get_secret(tmp) != EC_SUCCESS) {
-		response = EC_RES_UNAVAILABLE;
-		QUEUE_ADD_UNITS(&update_to_usb, &response, sizeof(response));
-		return 1;
-	}
-
-	/*
-	 * Nothing can fail from now on, let's push data to the queue as soon as
-	 * possible to save some temporary variables.
-	 */
-	response = EC_RES_SUCCESS;
-	QUEUE_ADD_UNITS(&update_to_usb, &response, sizeof(response));
-
-	/*
-	 * tmp2 = device_private
-	 *      = HMAC_SHA256(device_secret, "device-identity")
-	 */
-	hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE,
-		    KEY_CONTEXT, sizeof(KEY_CONTEXT) - 1);
-
-	/* tmp = device_public = x25519(device_private, x25519_base_point) */
-	X25519_public_from_private(tmp, tmp2);
-	QUEUE_ADD_UNITS(&update_to_usb, tmp, sizeof(tmp));
-
-	/* tmp = shared_secret = x25519(device_private, host_public) */
-	X25519(tmp, tmp2, challenge->host_public);
-
-	/* tmp2 = authenticator = HMAC_SHA256(shared_secret, nonce) */
-	hmac_SHA256(tmp2, tmp, sizeof(tmp),
-		    challenge->nonce, sizeof(challenge->nonce));
-	QUEUE_ADD_UNITS(&update_to_usb, tmp2,
-		member_size(struct pair_challenge_response, authenticator));
-	return 1;
-}
-#endif
-
-/*
- * Fetches a transfer start frame from the queue. This can be either an update
- * start frame (block_size = 0, all of cmd = 0), or the beginning of a frame
- * (block_size > 0, valid block_base in cmd).
- */
-static int fetch_transfer_start(struct consumer const *consumer, size_t count,
-				struct update_frame_header *pupfr)
-{
-	int i;
-
-	/*
-	 * Let's just make sure we drain the queue no matter what the contents
-	 * are. This way they won't be in the way during next callback, even
-	 * if these contents are not what's expected.
-	 *
-	 * Note: If count > sizeof(*pupfr), pupfr will be corrupted. This is
-	 * ok as we will immediately fail after this.
-	 */
-	i = count;
-	while (i > 0) {
-		QUEUE_REMOVE_UNITS(consumer->queue, pupfr,
-				   MIN(i, sizeof(*pupfr)));
-		i -= sizeof(*pupfr);
-	}
-
-	if (count != sizeof(struct update_frame_header)) {
-		CPRINTS("FW update: wrong first block, size %d", count);
-		return 0;
-	}
-
-	return 1;
-}
-
-static int try_vendor_command(struct consumer const *consumer, size_t count)
-{
-	char buffer[USB_MAX_PACKET_SIZE];
-	struct update_frame_header *cmd_buffer = (void *)buffer;
-	int rv = 0;
-
-	/* Validate count (too short, or too long). */
-	if (count < sizeof(*cmd_buffer) || count > sizeof(buffer))
-		return 0;
-
-	/*
-	 * Let's copy off the queue the update frame header, to see if this
-	 * is a channeled vendor command.
-	 */
-	queue_peek_units(consumer->queue, cmd_buffer, 0, sizeof(*cmd_buffer));
-	if (be32toh(cmd_buffer->cmd.block_base) != UPDATE_EXTRA_CMD)
-		return 0;
-
-	if (be32toh(cmd_buffer->block_size) != count) {
-		CPRINTS("%s: problem: block size and count mismatch (%d != %d)",
-			__func__, be32toh(cmd_buffer->block_size), count);
-		return 0;
-	}
-
-	/* Get the entire command, don't remove it from the queue just yet. */
-	queue_peek_units(consumer->queue, cmd_buffer, 0, count);
-
-	/* Looks like this is a vendor command, let's verify it. */
-	if (update_pdu_valid(&cmd_buffer->cmd,
-			  count - offsetof(struct update_frame_header, cmd))) {
-		enum update_extra_command subcommand;
-		uint8_t response;
-		size_t response_size = sizeof(response);
-		int __attribute__((unused)) header_size;
-		int __attribute__((unused)) data_count;
-
-		/* looks good, let's process it. */
-		rv = 1;
-
-		/* Now remove it from the queue. */
-		queue_advance_head(consumer->queue, count);
-
-		subcommand = be16toh(*((uint16_t *)(cmd_buffer + 1)));
-
-		/*
-		 * header size: update frame header + 2 bytes for subcommand
-		 * data_count: Some commands take in extra data as parameter
-		 */
-		header_size = sizeof(*cmd_buffer) + sizeof(uint16_t);
-		data_count = count - header_size;
-
-		switch (subcommand) {
-		case UPDATE_EXTRA_CMD_IMMEDIATE_RESET:
-			CPRINTS("Rebooting!");
-			CPRINTF("\n\n");
-			cflush();
-			system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED);
-			/* Unreachable, unless something bad happens. */
-			response = EC_RES_ERROR;
-			break;
-		case UPDATE_EXTRA_CMD_JUMP_TO_RW:
-#ifdef CONFIG_RWSIG
-			/*
-			 * Tell rwsig task to jump to RW. This does nothing if
-			 * verification failed, and will only jump later on if
-			 * verification is still in progress.
-			 */
-			rwsig_continue();
-
-			switch (rwsig_get_status()) {
-			case RWSIG_VALID:
-				response = EC_RES_SUCCESS;
-				break;
-			case RWSIG_INVALID:
-				response = EC_RES_INVALID_CHECKSUM;
-				break;
-			case RWSIG_IN_PROGRESS:
-				response = EC_RES_IN_PROGRESS;
-				break;
-			default:
-				response = EC_RES_ERROR;
-			}
-#else
-			system_run_image_copy(EC_IMAGE_RW);
-#endif
-			break;
-#ifdef CONFIG_RWSIG
-		case UPDATE_EXTRA_CMD_STAY_IN_RO:
-			rwsig_abort();
-			response = EC_RES_SUCCESS;
-			break;
-#endif
-		case UPDATE_EXTRA_CMD_UNLOCK_RW:
-			crec_flash_set_protect(EC_FLASH_PROTECT_RW_AT_BOOT, 0);
-			response = EC_RES_SUCCESS;
-			break;
-#ifdef CONFIG_ROLLBACK
-		case UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK:
-			crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT
-					       , 0);
-			response = EC_RES_SUCCESS;
-			break;
-#ifdef CONFIG_ROLLBACK_SECRET_SIZE
-#ifdef CONFIG_ROLLBACK_UPDATE
-		case UPDATE_EXTRA_CMD_INJECT_ENTROPY: {
-			if (data_count < CONFIG_ROLLBACK_SECRET_SIZE) {
-				CPRINTS("Entropy too short");
-				response = EC_RES_INVALID_PARAM;
-				break;
-			}
-
-			CPRINTS("Adding %db of entropy", data_count);
-			/* Add the entropy to secret. */
-			rollback_add_entropy(buffer + header_size, data_count);
-			break;
-		}
-#endif /* CONFIG_ROLLBACK_UPDATE */
-#ifdef CONFIG_USB_PAIRING
-		case UPDATE_EXTRA_CMD_PAIR_CHALLENGE: {
-			if (data_count < sizeof(struct pair_challenge)) {
-				CPRINTS("Challenge data too short");
-				response = EC_RES_INVALID_PARAM;
-				break;
-			}
-
-			/* pair_challenge takes care of answering */
-			return pair_challenge((struct pair_challenge *)
-						(buffer + header_size));
-		}
-#endif
-#endif /* CONFIG_ROLLBACK_SECRET_SIZE */
-#endif /* CONFIG_ROLLBACK */
-#ifdef CONFIG_TOUCHPAD
-		case UPDATE_EXTRA_CMD_TOUCHPAD_INFO: {
-			struct touchpad_info tp = { 0 };
-
-			if (data_count != 0) {
-				response = EC_RES_INVALID_PARAM;
-				break;
-			}
-
-			response_size = touchpad_get_info(&tp);
-			if (response_size < 1) {
-				response = EC_RES_ERROR;
-				break;
-			}
-
-#ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
-			tp.fw_address = CONFIG_TOUCHPAD_VIRTUAL_OFF;
-			tp.fw_size = CONFIG_TOUCHPAD_VIRTUAL_SIZE;
-
-#ifdef CONFIG_TOUCHPAD_HASH_FW
-			memcpy(tp.allowed_fw_hash, touchpad_fw_full_hash,
-				sizeof(tp.allowed_fw_hash));
-#endif
-#endif /* CONFIG_TOUCHPAD_VIRTUAL_OFF */
-			QUEUE_ADD_UNITS(&update_to_usb,
-					&tp, response_size);
-			return 1;
-		}
-		case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: {
-			uint8_t *data = NULL;
-			unsigned int write_count = 0;
-
-			/*
-			 * Let the touchpad driver decide what it wants to do
-			 * with the payload data, and put the response in data.
-			 */
-			response = touchpad_debug(buffer + header_size,
-					data_count, &data, &write_count);
-
-			/*
-			 * On error, or if there is no data to write back, just
-			 * write back response.
-			 */
-			if (response != EC_RES_SUCCESS || write_count == 0)
-				break;
-
-			/* Check that we can write all the data to the queue. */
-			if (write_count > queue_space(&update_to_usb))
-				return EC_RES_BUSY;
-
-			QUEUE_ADD_UNITS(&update_to_usb, data, write_count);
-			return 1;
-		}
-#endif
-#ifdef CONFIG_USB_CONSOLE_READ
-		/*
-		 * TODO(b/112877237): move this to a new interface, so we can
-		 * support reading log and other commands at the same time?
-		 */
-		case UPDATE_EXTRA_CMD_CONSOLE_READ_INIT:
-			response = uart_console_read_buffer_init();
-			break;
-		case UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT: {
-			uint8_t *data = buffer + header_size;
-			uint8_t output[64];
-			uint16_t write_count = 0;
-
-			if (data_count != 1) {
-				response = EC_RES_INVALID_PARAM;
-				break;
-			}
-
-			response = uart_console_read_buffer(
-					data[0],
-					(char *)output,
-					MIN(sizeof(output),
-					    queue_space(&update_to_usb)),
-					&write_count);
-			if (response != EC_RES_SUCCESS || write_count == 0)
-				break;
-
-			QUEUE_ADD_UNITS(&update_to_usb, output, write_count);
-			return 1;
-		}
-#endif
-		default:
-			response = EC_RES_INVALID_COMMAND;
-		}
-
-		QUEUE_ADD_UNITS(&update_to_usb, &response, response_size);
-	}
-
-	return rv;
-}
-
-/*
- * When was last time a USB callback was called, in microseconds, free running
- * timer.
- */
-static uint64_t prev_activity_timestamp;
-
-/*
- * A flag indicating that at least one valid PDU containing flash update block
- * has been received in the current transfer session.
- */
-static uint8_t  data_was_transferred;
-
-/* Reply with an error to remote side, reset state. */
-static void send_error_reset(uint8_t resp_value)
-{
-	QUEUE_ADD_UNITS(&update_to_usb, &resp_value, 1);
-	rx_state_ = rx_idle;
-	data_was_transferred = 0;
-}
-
-/* Called to deal with data from the host */
-static void update_out_handler(struct consumer const *consumer, size_t count)
-{
-	struct update_frame_header upfr;
-	size_t resp_size;
-	uint8_t resp_value;
-	uint64_t delta_time;
-
-	/* How much time since the previous USB callback? */
-	delta_time = get_time().val - prev_activity_timestamp;
-	prev_activity_timestamp += delta_time;
-
-	/* If timeout exceeds 5 seconds - let's start over. */
-	if ((delta_time > 5000000) && (rx_state_ != rx_idle)) {
-		rx_state_ = rx_idle;
-		CPRINTS("FW update: recovering after timeout");
-	}
-
-	if (rx_state_ == rx_idle) {
-		/*
-		 * The payload must be an update initiating PDU.
-		 *
-		 * The size of the response returned in the same buffer will
-		 * exceed the received frame size; Let's make sure there is
-		 * enough room for the response in the buffer.
-		 */
-		union {
-			struct update_frame_header upfr;
-			struct {
-				uint32_t unused;
-				struct first_response_pdu startup_resp;
-			};
-		} u;
-
-		/* Check is this is a channeled TPM extension command. */
-		if (try_vendor_command(consumer, count))
-			return;
-
-		/*
-		 * An update start PDU is a command without any payload, with
-		 * digest = 0, and base = 0.
-		 */
-		if (!fetch_transfer_start(consumer, count, &u.upfr) ||
-			be32toh(u.upfr.block_size) !=
-					sizeof(struct update_frame_header) ||
-				u.upfr.cmd.block_digest != 0 ||
-				u.upfr.cmd.block_base != 0) {
-			/*
-			 * Something is wrong, this payload is not a valid
-			 * update start PDU. Let'w indicate this by returning
-			 * a single byte error code.
-			 */
-			CPRINTS("FW update: invalid start.");
-			send_error_reset(UPDATE_GEN_ERROR);
-			return;
-		}
-
-		CPRINTS("FW update: starting...");
-		fw_update_command_handler(&u.upfr.cmd, count -
-					   offsetof(struct update_frame_header,
-						    cmd),
-					   &resp_size);
-
-		if (!u.startup_resp.return_value) {
-			rx_state_ = rx_outside_block;  /* We're in business. */
-			data_was_transferred = 0;   /* No data received yet. */
-		}
-
-		/* Let the host know what updater had to say. */
-		QUEUE_ADD_UNITS(&update_to_usb, &u.startup_resp, resp_size);
-		return;
-	}
-
-	if (rx_state_ == rx_outside_block) {
-		/*
-		 * Expecting to receive the beginning of the block or the
-		 * reset command if all data blocks have been processed.
-		 */
-		if (count == 4) {
-			uint32_t command;
-
-			QUEUE_REMOVE_UNITS(consumer->queue, &command,
-					   sizeof(command));
-			command = be32toh(command);
-			if (command == UPDATE_DONE) {
-				CPRINTS("FW update: done");
-
-				if (data_was_transferred) {
-					fw_update_complete();
-					data_was_transferred = 0;
-				}
-
-				resp_value = 0;
-				QUEUE_ADD_UNITS(&update_to_usb,
-						&resp_value, 1);
-				rx_state_ = rx_idle;
-				return;
-			}
-		}
-
-		/*
-		 * At this point we expect a block start message. It is
-		 * sizeof(upfr) bytes in size.
-		 */
-		if (!fetch_transfer_start(consumer, count, &upfr)) {
-			CPRINTS("Invalid block start.");
-			send_error_reset(UPDATE_GEN_ERROR);
-			return;
-		}
-
-		/* Let's allocate a large enough buffer. */
-		block_size = be32toh(upfr.block_size) -
-			offsetof(struct update_frame_header, cmd);
-
-		/*
-		 * Only update start PDU is allowed to have a size 0 payload.
-		 */
-		if (block_size <= sizeof(struct update_command) ||
-		    block_size > sizeof(block_buffer)) {
-			CPRINTS("Invalid block size (%d).", block_size);
-			send_error_reset(UPDATE_GEN_ERROR);
-			return;
-		}
-
-		/*
-		 * Copy the rest of the message into the block buffer to pass
-		 * to the updater.
-		 */
-		block_index = sizeof(upfr) -
-			offsetof(struct update_frame_header, cmd);
-		memcpy(block_buffer, &upfr.cmd, block_index);
-		block_size -= block_index;
-		rx_state_ = rx_inside_block;
-		return;
-	}
-
-	/* Must be inside block. */
-	QUEUE_REMOVE_UNITS(consumer->queue, block_buffer + block_index, count);
-	block_index += count;
-	block_size -= count;
-
-	if (block_size) {
-		if (count <= sizeof(upfr)) {
-			/*
-			 * A block header size instead of chunk size message
-			 * has been received, let's abort the transfer.
-			 */
-			CPRINTS("Unexpected header");
-			send_error_reset(UPDATE_GEN_ERROR);
-			return;
-		}
-		return;	/* More to come. */
-	}
-
-	/*
-	 * Ok, the entire block has been received and reassembled, pass it to
-	 * the updater for verification and programming.
-	 */
-	fw_update_command_handler(block_buffer, block_index, &resp_size);
-
-	/*
-	 * There was at least an attempt to program the flash, set the
-	 * flag.
-	 */
-	data_was_transferred = 1;
-	resp_value = block_buffer[0];
-	QUEUE_ADD_UNITS(&update_to_usb, &resp_value, sizeof(resp_value));
-	rx_state_ = rx_outside_block;
-}
-
-struct consumer const update_consumer = {
-	.queue = &usb_to_update,
-	.ops   = &((struct consumer_ops const) {
-		.written = update_out_handler,
-	}),
-};
diff --git a/common/usbc/build.mk b/common/usbc/build.mk
deleted file mode 100644
index 48ab5351b8..0000000000
--- a/common/usbc/build.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Build for USB Type-C and Power Delivery
-
-# Note that this variable includes the trailing "/"
-_usbc_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-ifneq ($(CONFIG_USB_PD_TCPMV2),)
-all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_pd_timer.o
-all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_sm.o
-all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usbc_task.o
-
-# Type-C state machines
-ifneq ($(CONFIG_USB_TYPEC_SM),)
-all-obj-$(CONFIG_USB_VPD)+=$(_usbc_dir)usb_tc_vpd_sm.o
-all-obj-$(CONFIG_USB_CTVPD)+=$(_usbc_dir)usb_tc_ctvpd_sm.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usb_tc_drp_acc_trysrc_sm.o
-endif # CONFIG_USB_TYPEC_SM
-
-# Protocol state machine
-ifneq ($(CONFIG_USB_PRL_SM),)
-all-obj-$(CONFIG_USB_PD_TCPMV2)+=$(_usbc_dir)usb_prl_sm.o
-endif # CONFIG_USB_PRL_SM
-
-# Policy Engine state machines
-ifneq ($(CONFIG_USB_PE_SM),)
-all-obj-$(CONFIG_USB_VPD)+=$(_usbc_dir)usb_pe_ctvpd_sm.o
-all-obj-$(CONFIG_USB_CTVPD)+=$(_usbc_dir)usb_pe_ctvpd_sm.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usbc_pd_policy.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usb_pe_drp_sm.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)usb_pd_dpm.o
-all-obj-$(CONFIG_USB_DRP_ACC_TRYSRC)+=$(_usbc_dir)dp_alt_mode.o
-all-obj-$(CONFIG_USB_PD_TBT_COMPAT_MODE)+=$(_usbc_dir)tbt_alt_mode.o
-all-obj-$(CONFIG_USB_PD_USB4)+=$(_usbc_dir)usb_mode.o
-all-obj-$(CONFIG_CMD_PD)+=$(_usbc_dir)usb_pd_console.o
-all-obj-$(CONFIG_USB_PD_HOST_CMD)+=$(_usbc_dir)usb_pd_host.o
-endif # CONFIG_USB_PE_SM
-
-# Retimer firmware update
-all-obj-$(CONFIG_USBC_RETIMER_FW_UPDATE)+=$(_usbc_dir)usb_retimer_fw_update.o
-
-# ALT-DP mode for UFP ports
-all-obj-$(CONFIG_USB_PD_ALT_MODE_UFP_DP)+=$(_usbc_dir)usb_pd_dp_ufp.o
-endif # CONFIG_USB_PD_TCPMV2
-
-# For testing
-all-obj-$(CONFIG_TEST_USB_PE_SM)+=$(_usbc_dir)usbc_pd_policy.o
-all-obj-$(CONFIG_TEST_USB_PE_SM)+=$(_usbc_dir)usb_pe_drp_sm.o
-all-obj-$(CONFIG_TEST_SM)+=$(_usbc_dir)usb_sm.o
diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c
deleted file mode 100644
index 9a3493c6e1..0000000000
--- a/common/usbc/dp_alt_mode.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * DisplayPort alternate mode support
- * Refer to VESA DisplayPort Alt Mode on USB Type-C Standard, version 2.0,
- * section 5.2
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "assert.h"
-#include "usb_common.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* The state of the DP negotiation */
-enum dp_states {
-	DP_START = 0,
-	DP_ENTER_ACKED,
-	DP_ENTER_NAKED,
-	DP_STATUS_ACKED,
-	DP_ACTIVE,
-	DP_ENTER_RETRY,
-	DP_INACTIVE,
-	DP_STATE_COUNT
-};
-static enum dp_states dp_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * Map of states to expected VDM commands in responses.
- * Default of 0 indicates no command expected.
- */
-static const uint8_t state_vdm_cmd[DP_STATE_COUNT] = {
-	[DP_START] = CMD_ENTER_MODE,
-	[DP_ENTER_ACKED] = CMD_DP_STATUS,
-	[DP_STATUS_ACKED] = CMD_DP_CONFIG,
-	[DP_ACTIVE] = CMD_EXIT_MODE,
-	[DP_ENTER_NAKED] = CMD_EXIT_MODE,
-	[DP_ENTER_RETRY] = CMD_ENTER_MODE,
-};
-
-bool dp_is_active(int port)
-{
-	return dp_state[port] == DP_ACTIVE;
-}
-
-void dp_init(int port)
-{
-	dp_state[port] = DP_START;
-}
-
-bool dp_entry_is_done(int port)
-{
-	return dp_state[port] == DP_ACTIVE ||
-		dp_state[port] == DP_INACTIVE;
-}
-
-static void dp_entry_failed(int port)
-{
-	CPRINTS("C%d: DP alt mode protocol failed!", port);
-	dp_state[port] = DP_INACTIVE;
-}
-
-static bool dp_response_valid(int port, enum tcpci_msg_type type,
-			     char *cmdt, int vdm_cmd)
-{
-	enum dp_states st = dp_state[port];
-
-	/*
-	 * Check for an unexpected response.
-	 * If DP is inactive, ignore the command.
-	 */
-	if (type != TCPCI_MSG_SOP ||
-	    (st != DP_INACTIVE && state_vdm_cmd[st] != vdm_cmd)) {
-		CPRINTS("C%d: Received unexpected DP VDM %s (cmd %d) from"
-			" %s in state %d", port, cmdt, vdm_cmd,
-			type == TCPCI_MSG_SOP ? "port partner" : "cable plug",
-			st);
-		dp_entry_failed(port);
-		return false;
-	}
-	return true;
-}
-
-static void dp_exit_to_usb_mode(int port)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-
-	pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT, opos);
-	set_usb_mux_with_current_data_role(port);
-
-	CPRINTS("C%d: Exited DP mode", port);
-    /*
-     * If the EC exits an alt mode autonomously, don't try to enter it again. If
-     * the AP commands the EC to exit DP mode, it might command the EC to enter
-     * again later, so leave the state machine ready for that possibility.
-     */
-	dp_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY)
-		? DP_START : DP_INACTIVE;
-}
-
-void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
-{
-	const struct svdm_amode_data *modep =
-		pd_get_amode_data(port, type, USB_SID_DISPLAYPORT);
-	const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]);
-
-	if (!dp_response_valid(port, type, "ACK", vdm_cmd))
-		return;
-
-	/* TODO(b/155890173): Validate VDO count for specific commands */
-
-	switch (dp_state[port]) {
-	case DP_START:
-	case DP_ENTER_RETRY:
-		dp_state[port] = DP_ENTER_ACKED;
-		/* Inform PE layer that alt mode is now active */
-		pd_set_dfp_enter_mode_flag(port, true);
-		break;
-	case DP_ENTER_ACKED:
-		/* DP status response & UFP's DP attention have same payload. */
-		dfp_consume_attention(port, vdm);
-		dp_state[port] = DP_STATUS_ACKED;
-		break;
-	case DP_STATUS_ACKED:
-		if (modep && modep->opos && modep->fx->post_config)
-			modep->fx->post_config(port);
-		dp_state[port] = DP_ACTIVE;
-		CPRINTS("C%d: Entered DP mode", port);
-		break;
-	case DP_ACTIVE:
-		/*
-		 * Request to exit mode successful, so put the module in an
-		 * inactive state.
-		 */
-		dp_exit_to_usb_mode(port);
-		break;
-	case DP_ENTER_NAKED:
-		/*
-		 * The request to exit the mode was successful,
-		 * so try to enter the mode again.
-		 */
-		dp_state[port] = DP_ENTER_RETRY;
-		break;
-	case DP_INACTIVE:
-		/*
-		 * This can occur if the mode is shutdown because
-		 * the CPU is being turned off, and an exit mode
-		 * command has been sent.
-		 */
-		break;
-	default:
-		/* Invalid or unexpected negotiation state */
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
-		dp_entry_failed(port);
-		break;
-	}
-}
-
-void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
-{
-	if (!dp_response_valid(port, type, "NAK", vdm_cmd))
-		return;
-
-	switch (dp_state[port]) {
-	case DP_START:
-		/*
-		 * If a request to enter DP mode is NAK'ed, this likely
-		 * means the partner is already in DP alt mode, so
-		 * request to exit the mode first before retrying
-		 * the enter command. This can happen if the EC
-		 * is restarted (e.g to go into recovery mode) while
-		 * DP alt mode is active.
-		 */
-		dp_state[port] = DP_ENTER_NAKED;
-		break;
-	case DP_ENTER_RETRY:
-		/*
-		 * Another NAK on the second attempt to enter DP mode.
-		 * Give up.
-		 */
-		dp_entry_failed(port);
-		break;
-	case DP_ACTIVE:
-		/* Treat an Exit Mode NAK the same as an Exit Mode ACK. */
-		dp_exit_to_usb_mode(port);
-		break;
-	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, dp_state[port]);
-		dp_entry_failed(port);
-		break;
-	}
-}
-
-int dp_setup_next_vdm(int port, int vdo_count, uint32_t *vdm)
-{
-	const struct svdm_amode_data *modep = pd_get_amode_data(port,
-			TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	int vdo_count_ret;
-
-	if (vdo_count < VDO_MAX_SIZE)
-		return -1;
-
-	switch (dp_state[port]) {
-	case DP_START:
-	case DP_ENTER_RETRY:
-		/* Enter the first supported mode for DisplayPort. */
-		vdm[0] = pd_dfp_enter_mode(port, TCPCI_MSG_SOP,
-				USB_SID_DISPLAYPORT, 0);
-		if (vdm[0] == 0)
-			return -1;
-		/* CMDT_INIT is 0, so this is a no-op */
-		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-		vdo_count_ret = 1;
-		if (dp_state[port] == DP_START)
-			CPRINTS("C%d: Attempting to enter DP mode", port);
-		break;
-	case DP_ENTER_ACKED:
-		if (!(modep && modep->opos))
-			return -1;
-
-		vdo_count_ret = modep->fx->status(port, vdm);
-		if (vdo_count_ret == 0)
-			return -1;
-		vdm[0] |= PD_VDO_OPOS(modep->opos);
-		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-		break;
-	case DP_STATUS_ACKED:
-		if (!(modep && modep->opos))
-			return -1;
-
-		vdo_count_ret = modep->fx->config(port, vdm);
-		if (vdo_count_ret == 0)
-			return -1;
-		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-		break;
-	case DP_ENTER_NAKED:
-	case DP_ACTIVE:
-		/*
-		 * Called to exit DP alt mode, either when the mode
-		 * is active and the system is shutting down, or
-		 * when an initial request to enter the mode is NAK'ed.
-		 * This can happen if the EC is restarted (e.g to go
-		 * into recovery mode) while DP alt mode is active.
-		 * It would be good to invoke modep->fx->exit but
-		 * this doesn't set up the VDM, it clears state.
-		 * TODO(b/159856063): Clean up the API to the fx functions.
-		 */
-		if (!(modep && modep->opos))
-			return -1;
-
-		usb_mux_set_safe_mode_exit(port);
-
-		vdm[0] = VDO(USB_SID_DISPLAYPORT,
-			     1, /* structured */
-			     CMD_EXIT_MODE);
-
-		vdm[0] |= VDO_OPOS(modep->opos);
-		vdm[0] |= VDO_CMDT(CMDT_INIT);
-		vdm[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-		vdo_count_ret = 1;
-		break;
-	case DP_INACTIVE:
-		/*
-		 * DP mode is inactive.
-		 */
-		return -1;
-	default:
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
-		return -1;
-	}
-	return vdo_count_ret;
-}
diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c
deleted file mode 100644
index 73e2796345..0000000000
--- a/common/usbc/tbt_alt_mode.c
+++ /dev/null
@@ -1,579 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Thunderbolt alternate mode support
- * Refer to USB Type-C Cable and Connector Specification Release 2.0 Section F
- */
-
-#include "atomic.h"
-#include <stdbool.h>
-#include <stdint.h>
-#include "compile_time_macros.h"
-#include "console.h"
-#include "tcpm/tcpm.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pe_sm.h"
-#include "usb_tbt_alt_mode.h"
-
-/*
- * Enter/Exit TBT mode with active cable
- *
- *
- *                      TBT_START                           |------------
- *                 retry_done = false                       |           |
- *                           |                              v           |
- *                           |<------------------|    Exit Mode SOP     |
- *                           | retry_done = true |          |           |
- *                           v                   |          | ACK/NAK   |
- *                    Enter Mode SOP'            |  --------|---------  |
- *                       ACK | NAK               |    Exit Mode SOP''   |
- *                    |------|------|            |          |           |
- *                    |             |            |          | ACK/NAK   |
- *                    v             |            |  --------|---------  |
- *             Enter Mode SOP''     |            |     Exit Mode SOP'   |
- *                    |             |            |          |           |
- *                ACK | NAK         |            |          | ACK/NAK   |
- *             |------|------|      |            |  ------------------  |
- *             |             |      |            | retry_done == true?  |
- *             v             |      |            |          |           |
- *       Enter Mode SOP      |      |            |   No     |           |
- *             |             |      |            |-----------           |
- *         ACK | NAK         |      |                       |Yes        |
- *     |-------|------|      |      |                       v           |
- *     |              |      |      |                  TBT_INACTIVE     |
- *     v              |      |      |              retry_done = false   |
- * TBT_ACTIVE         |      |      |                                   |
- * retry_done = true  |      |      |                                   |
- *     |              |      |      |                                   |
- *     v              v      v      v                                   |
- *     -----------------------------------------------------------------|
- */
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/*
- * If a partner sends an Enter Mode NAK, Exit Mode and try again. This has
- * happened when the EC loses state after previously entering an alt mode
- * with a partner. It may be fixed in b/159495742, in which case this
- * logic is unneeded.
- */
-#define TBT_FLAG_RETRY_DONE       BIT(0)
-#define TBT_FLAG_EXIT_DONE        BIT(1)
-#define TBT_FLAG_CABLE_ENTRY_DONE BIT(2)
-
-static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define TBT_SET_FLAG(port, flag) (tbt_flags[port] |= (flag))
-#define TBT_CLR_FLAG(port, flag) (tbt_flags[port] &= (~flag))
-#define TBT_CHK_FLAG(port, flag) (tbt_flags[port] & (flag))
-
-static int tbt_prints(const char *string, int port)
-{
-	return CPRINTS("C%d: TBT %s", port, string);
-}
-
-/* The states of Thunderbolt negotiation */
-enum tbt_states {
-	TBT_START = 0,
-	TBT_ENTER_SOP,
-	TBT_ACTIVE,
-	TBT_EXIT_SOP,
-	TBT_INACTIVE,
-	/* Active cable only */
-	TBT_ENTER_SOP_PRIME,
-	TBT_ENTER_SOP_PRIME_PRIME,
-	TBT_EXIT_SOP_PRIME,
-	TBT_EXIT_SOP_PRIME_PRIME,
-	TBT_STATE_COUNT,
-};
-static enum tbt_states tbt_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static const uint8_t state_vdm_cmd[TBT_STATE_COUNT] = {
-	[TBT_ENTER_SOP] = CMD_ENTER_MODE,
-	[TBT_ACTIVE] = CMD_EXIT_MODE,
-	[TBT_EXIT_SOP] = CMD_EXIT_MODE,
-	/* Active cable only */
-	[TBT_ENTER_SOP_PRIME] = CMD_ENTER_MODE,
-	[TBT_ENTER_SOP_PRIME_PRIME] = CMD_ENTER_MODE,
-	[TBT_EXIT_SOP_PRIME] = CMD_EXIT_MODE,
-	[TBT_EXIT_SOP_PRIME_PRIME] = CMD_EXIT_MODE,
-};
-
-void tbt_init(int port)
-{
-	tbt_state[port] = TBT_START;
-	TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
-	TBT_SET_FLAG(port, TBT_FLAG_EXIT_DONE);
-	TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
-}
-
-bool tbt_is_active(int port)
-{
-	return tbt_state[port] != TBT_INACTIVE &&
-	       tbt_state[port] != TBT_START;
-}
-
-bool tbt_entry_is_done(int port)
-{
-	return tbt_state[port] == TBT_ACTIVE ||
-		tbt_state[port] == TBT_INACTIVE;
-}
-
-bool tbt_cable_entry_is_done(int port)
-{
-	return TBT_CHK_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
-}
-
-static void tbt_exit_done(int port)
-{
-    /*
-     * If the EC exits an alt mode autonomously, don't try to enter it again. If
-     * the AP commands the EC to exit DP mode, it might command the EC to enter
-     * again later, so leave the state machine ready for that possibility.
-     */
-	tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY)
-		? TBT_START : TBT_INACTIVE;
-	TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
-	TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
-
-	if (!TBT_CHK_FLAG(port, TBT_FLAG_EXIT_DONE)) {
-		TBT_SET_FLAG(port, TBT_FLAG_EXIT_DONE);
-		tbt_prints("Exited alternate mode", port);
-		return;
-	}
-
-	tbt_prints("alt mode protocol failed!", port);
-}
-
-void tbt_exit_mode_request(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
-	TBT_CLR_FLAG(port, TBT_FLAG_EXIT_DONE);
-	/*
-	 * If the port has entered USB4 mode with Thunderbolt mode for the
-	 * cable, on request to exit, only exit Thunderbolt mode for the
-	 * cable.
-	 * TODO (b/156749387): Remove once data reset feature is in place.
-	 */
-	if (tbt_state[port] == TBT_ENTER_SOP) {
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-		/*
-		 * For Linear re-driver cables, the port enters USB4 mode
-		 * with Thunderbolt mode for SOP prime. Hence, on request to
-		 * exit, only exit Thunderbolt mode SOP prime
-		 */
-		tbt_state[port] =
-			cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-			TBT_EXIT_SOP_PRIME : TBT_EXIT_SOP_PRIME_PRIME;
-	}
-}
-
-static bool tbt_response_valid(int port, enum tcpci_msg_type type,
-				char *cmdt, int vdm_cmd)
-{
-	enum tbt_states st = tbt_state[port];
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
-
-	/*
-	 * Check for an unexpected response.
-	 * 1. invalid command
-	 * 2. invalid Tx type for passive cable
-	 * If Thunderbolt is inactive, ignore the command.
-	 */
-	if ((st != TBT_INACTIVE && state_vdm_cmd[st] != vdm_cmd) ||
-	    (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
-	     cable_mode_resp.tbt_active_passive == TBT_CABLE_PASSIVE &&
-	     type != TCPCI_MSG_SOP)) {
-		tbt_exit_done(port);
-		return false;
-	}
-	return true;
-}
-
-/* Exit Mode process is complete, but retry Enter Mode process */
-static void tbt_retry_enter_mode(int port)
-{
-	tbt_state[port] = TBT_START;
-	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
-}
-
-/* Send Exit Mode to SOP''(if supported), or SOP' */
-static void tbt_active_cable_exit_mode(int port)
-{
-	const struct pd_discovery *disc;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	if (disc->identity.product_t1.a_rev20.sop_p_p)
-		tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
-	else
-		tbt_state[port] = TBT_EXIT_SOP_PRIME;
-}
-
-bool tbt_cable_entry_required_for_usb4(int port)
-{
-	const struct pd_discovery *disc_sop_prime;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	/* Request to enter Thunderbolt mode for the cable prior to entering
-	 * USB4 mode if -
-	 * 1. Thunderbolt Mode SOP' VDO active/passive bit (B25) is
-	 *    TBT_CABLE_ACTIVE or
-	 * 2. It's an active cable with VDM version < 2.0 or
-	 *    VDO version < 1.3
-	 */
-	if (tbt_cable_entry_is_done(port))
-		return false;
-
-	cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-	if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
-		return true;
-
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
-		disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
-		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
-							VDO_VERSION_1_3)
-			return true;
-	}
-	return false;
-}
-
-void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
-{
-	const struct pd_discovery *disc;
-	const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]);
-	int opos_sop, opos_sop_prime;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	if (!tbt_response_valid(port, type, "ACK", vdm_cmd))
-		return;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	switch (tbt_state[port]) {
-	case TBT_ENTER_SOP_PRIME:
-		tbt_prints("enter mode SOP'", port);
-		cable_mode_resp.raw_value =
-				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-		/* For LRD cables, Enter mode SOP' -> Enter mode SOP */
-		if (disc->identity.product_t1.a_rev20.sop_p_p &&
-		    cable_mode_resp.tbt_active_passive != TBT_CABLE_ACTIVE) {
-			tbt_state[port] = TBT_ENTER_SOP_PRIME_PRIME;
-		} else {
-			TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
-			tbt_state[port] = TBT_ENTER_SOP;
-		}
-		break;
-	case TBT_ENTER_SOP_PRIME_PRIME:
-		tbt_prints("enter mode SOP''", port);
-		TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
-		tbt_state[port] = TBT_ENTER_SOP;
-		break;
-	case TBT_ENTER_SOP:
-		set_tbt_compat_mode_ready(port);
-		tbt_state[port] = TBT_ACTIVE;
-		tbt_prints("enter mode SOP", port);
-		TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
-		/* Indicate to PE layer that alt mode is active */
-		pd_set_dfp_enter_mode_flag(port, true);
-		break;
-	case TBT_ACTIVE:
-		tbt_prints("exit mode SOP", port);
-		opos_sop = pd_alt_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL);
-
-		/* Clear Thunderbolt related signals */
-		pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL, opos_sop);
-		set_usb_mux_with_current_data_role(port);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
-			tbt_active_cable_exit_mode(port);
-		} else {
-			/*
-			 * Exit Mode process is complete; go to inactive state.
-			 */
-			tbt_exit_done(port);
-		}
-		break;
-	case TBT_EXIT_SOP:
-		set_usb_mux_with_current_data_role(port);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
-				/* retried enter mode, still failed, give up */
-				tbt_exit_done(port);
-			else
-				tbt_retry_enter_mode(port);
-		}
-		break;
-	case TBT_EXIT_SOP_PRIME_PRIME:
-		tbt_prints("exit mode SOP''", port);
-		tbt_state[port] = TBT_EXIT_SOP_PRIME;
-		set_usb_mux_with_current_data_role(port);
-		break;
-	case TBT_EXIT_SOP_PRIME:
-		tbt_prints("exit mode SOP'", port);
-		if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) {
-			/*
-			 * Exit mode process is complete; go to inactive state.
-			 */
-			tbt_exit_done(port);
-			opos_sop_prime =
-				pd_alt_mode(port, TCPCI_MSG_SOP_PRIME,
-					    USB_VID_INTEL);
-
-			/* Clear Thunderbolt related signals */
-			pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME,
-					USB_VID_INTEL, opos_sop_prime);
-			set_usb_mux_with_current_data_role(port);
-		} else {
-			tbt_retry_enter_mode(port);
-		}
-		break;
-	case TBT_INACTIVE:
-		/*
-		 * This can occur if the mode is shutdown because
-		 * the CPU is being turned off, and an exit mode
-		 * command has been sent.
-		 */
-		break;
-	default:
-		/* Invalid or unexpected negotiation state */
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
-		tbt_exit_done(port);
-		break;
-	}
-}
-
-void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
-{
-	if (!tbt_response_valid(port, type, "NAK", vdm_cmd))
-		return;
-
-	switch (tbt_state[port]) {
-	case TBT_ENTER_SOP_PRIME:
-	case TBT_ENTER_SOP_PRIME_PRIME:
-	case TBT_ENTER_SOP:
-		/*
-		 * If a request to enter Thunderbolt mode is NAK'ed, this
-		 * likely means the partner is already in Thunderbolt alt mode,
-		 * so request to exit the mode first before retrying the enter
-		 * command. This can happen if the EC is restarted
-		 */
-		tbt_state[port] = TBT_EXIT_SOP;
-		break;
-	case TBT_ACTIVE:
-		/* Exit SOP got NAK'ed */
-		set_usb_mux_with_current_data_role(port);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			tbt_prints("exit mode SOP failed", port);
-			tbt_state[port] = TBT_INACTIVE;
-			TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
-		}
-		break;
-	case TBT_EXIT_SOP:
-		/* Exit SOP got NAK'ed */
-		tbt_prints("exit mode SOP failed", port);
-		set_usb_mux_with_current_data_role(port);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
-			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
-				/* Retried enter mode, still failed, give up */
-				tbt_exit_done(port);
-			else
-				tbt_retry_enter_mode(port);
-		}
-		break;
-	case TBT_EXIT_SOP_PRIME_PRIME:
-		set_usb_mux_with_current_data_role(port);
-		tbt_prints("exit mode SOP'' failed", port);
-		tbt_state[port] = TBT_EXIT_SOP_PRIME;
-		break;
-	case TBT_EXIT_SOP_PRIME:
-		set_usb_mux_with_current_data_role(port);
-		if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) {
-			/*
-			 * Exit mode process is complete; go to inactive state.
-			 */
-			tbt_prints("exit mode SOP' failed", port);
-			tbt_exit_done(port);
-		} else {
-			tbt_retry_enter_mode(port);
-		}
-		break;
-	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, tbt_state[port]);
-		tbt_exit_done(port);
-		break;
-	}
-}
-
-static bool tbt_mode_is_supported(int port, int vdo_count)
-{
-	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
-
-	if (!disc->identity.idh.modal_support)
-		return false;
-
-	if (get_tbt_cable_speed(port) < TBT_SS_U31_GEN1)
-		return false;
-
-	/*
-	 * TBT4 PD Discovery Flow Application Notes Revision 0.9:
-	 * Figure 2: for active cable, SOP' should support
-	 * SVID USB_VID_INTEL to enter Thunderbolt alt mode
-	 */
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE &&
-		!pd_is_mode_discovered_for_svid(
-			port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL))
-		return false;
-
-	return true;
-}
-
-int tbt_setup_next_vdm(int port, int vdo_count, uint32_t *vdm,
-		enum tcpci_msg_type *tx_type)
-{
-	struct svdm_amode_data *modep;
-	int vdo_count_ret = 0;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	*tx_type = TCPCI_MSG_SOP;
-
-	if (vdo_count < VDO_MAX_SIZE)
-		return -1;
-
-	switch (tbt_state[port]) {
-	case TBT_START:
-		if (!tbt_mode_is_supported(port, vdo_count))
-			return 0;
-
-		if (!TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
-			tbt_prints("attempt to enter mode", port);
-		else
-			tbt_prints("retry to enter mode", port);
-
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-		/* Active cable and LRD cables send Enter Mode SOP' first */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-		    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
-			vdo_count_ret = enter_tbt_compat_mode(port,
-						TCPCI_MSG_SOP_PRIME, vdm);
-			*tx_type = TCPCI_MSG_SOP_PRIME;
-			tbt_state[port] = TBT_ENTER_SOP_PRIME;
-		} else {
-			/* Passive cable send Enter Mode SOP */
-			vdo_count_ret =
-				enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm);
-			tbt_state[port] = TBT_ENTER_SOP;
-		}
-		break;
-	case TBT_ENTER_SOP_PRIME:
-		vdo_count_ret =
-			enter_tbt_compat_mode(port, TCPCI_MSG_SOP_PRIME, vdm);
-		*tx_type = TCPCI_MSG_SOP_PRIME;
-		break;
-	case TBT_ENTER_SOP_PRIME_PRIME:
-		vdo_count_ret =
-			enter_tbt_compat_mode(
-				port, TCPCI_MSG_SOP_PRIME_PRIME, vdm);
-		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
-		break;
-	case TBT_ENTER_SOP:
-		vdo_count_ret =
-			enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm);
-		break;
-	case TBT_EXIT_SOP:
-	case TBT_ACTIVE:
-		/*
-		 * Called to exit Thunderbolt alt mode, either when the mode is
-		 * active and the system is shutting down, or when an initial
-		 * request to enter the mode is NAK'ed. This can happen if EC
-		 * is restarted while Thunderbolt mode is active.
-		 */
-		modep = pd_get_amode_data(port,
-					  TCPCI_MSG_SOP, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
-
-		usb_mux_set_safe_mode_exit(port);
-
-		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(
-				pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-		vdo_count_ret = 1;
-		break;
-	case TBT_EXIT_SOP_PRIME_PRIME:
-		modep = pd_get_amode_data(port,
-			TCPCI_MSG_SOP_PRIME, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
-
-		usb_mux_set_safe_mode_exit(port);
-
-		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port,
-				TCPCI_MSG_SOP_PRIME_PRIME));
-		vdo_count_ret = 1;
-		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
-		break;
-	case TBT_EXIT_SOP_PRIME:
-		modep = pd_get_amode_data(port,
-				TCPCI_MSG_SOP_PRIME, USB_VID_INTEL);
-		if (!(modep && modep->opos))
-			return -1;
-
-		usb_mux_set_safe_mode_exit(port);
-
-		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port,
-						TCPCI_MSG_SOP_PRIME));
-		vdo_count_ret = 1;
-		*tx_type = TCPCI_MSG_SOP_PRIME;
-		break;
-	case TBT_INACTIVE:
-		/* Thunderbolt mode is inactive */
-		return 0;
-	default:
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
-		return -1;
-	}
-
-	return vdo_count_ret;
-}
diff --git a/common/usbc/usb_mode.c b/common/usbc/usb_mode.c
deleted file mode 100644
index b9dc4973bc..0000000000
--- a/common/usbc/usb_mode.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * USB4 mode support
- * Refer USB Type-C Cable and Connector Specification Release 2.0 Section 5 and
- * USB Power Delivery Specification Revision 3.0, Version 2.0 Section 6.4.8
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "compile_time_macros.h"
-#include "console.h"
-#include "tcpm/tcpm.h"
-#include "usb_common.h"
-#include "usb_mode.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pe_sm.h"
-#include "usbc_ppc.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-enum usb4_mode_status {
-	USB4_MODE_FAILURE,
-	USB4_MODE_SUCCESS,
-};
-
-enum usb4_states {
-	USB4_START,
-	USB4_ENTER_SOP,
-	USB4_ENTER_SOP_PRIME,
-	USB4_ENTER_SOP_PRIME_PRIME,
-	USB4_ACTIVE,
-	USB4_INACTIVE,
-	USB4_STATE_COUNT,
-};
-
-/*
- * USB4 PD flow:
- *
- *                            Cable type
- *                                 |
- *            |-------- Passive ---|---- Active -----|
- *            |                                      |
- *      USB Highest Speed         Structured VDM version
- *            |                   (cable revision)-- <2.0---->|
- *    --------|--------|------|       |                       |
- *    |       |        |      |       >=2.0                   |
- *  >=Gen3   Gen2    Gen1  USB2.0     |                       |
- *    |       |        |      |   VDO version--- <1.3 ---> Modal op? -- N --|
- * Enter USB  |        |      |   (B21:23 of                  |             |
- * SOP  with  |        |      |    Discover ID SOP'-          y             |
- * Gen3 cable |        |    Skip   Active cable VDO1)         |             |
- * speed      |        |    USB4      |                    TBT SVID? -- N --|
- *            |        |    mode      >=1.3                   |             |
- *    Is modal op?     |    entry     |                       y             |
- *            |        |            Cable USB4  - N           |             |
- *            y        |            support?      |       Gen4 cable? - N - Skip
- *            |        |               |      Skip USB4       |             USB4
- *    Is TBT SVID? -N- Enter           |      mode entry      |             mode
- *            |       USB4 SOP         |                      |            entry
- *            y       with Gen2        y                      |
- *            |       cable speed      |                      |
- *            |                        |                      |
- *    Is Discover mode                 |                      |
- *    SOP' B25? - N - Enter      Enter USB4 mode              |
- *            |     USB4 SOP     (SOP, SOP', SOP'')           |
- *            |     with speed                                |
- *            y     from TBT mode                             |
- *            |     SOP' VDO                                  |
- *            |                           |<-- NAK -- Enter mode TBT SOP'<---|
- * |---->Enter TBT SOP'-------NAK------>| |                   |              |
- * |          |                         | |                  ACK             |
- * |         ACK                        | |                   |              |
- * |          |                         | |<-- NAK -- Enter mode TBT SOP''   |
- * |     Enter USB4 SOP                 | |                   |              |
- * |     with speed from         Exit TBT mode SOP           ACK             |
- * |     TBT mode SOP' VDO              | |                   |              |
- * |                                  ACK/NAK          Enter USB4 SOP        |
- * |                                    | |            with speed from       |
- * |                             Exit TBT mode SOP''   TBT mode SOP' VDO     |
- * |                                    | |                                  |
- * |                                  ACK/NAK                                |
- * |                                    | |                                  |
- * |                             Exit TBT mode SOP'                          |
- * |                                    | |                                  |
- * |                                   ACK/NAK                               |
- * |                                    | |                                  |
- * |---- N ----Retry done? -------------| |--------Retry done? ---- N -------|
- *                  |                                   |
- *                  y                                   y
- *                  |                                   |
- *           Skip USB4 mode entry                 Skip USB4 mode entry
- */
-
-static enum usb4_states usb4_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static void usb4_debug_prints(int port, enum usb4_mode_status usb4_status)
-{
-	CPRINTS("C%d: USB4: State:%d Status:%d", port, usb4_state[port],
-		usb4_status);
-}
-
-bool enter_usb_entry_is_done(int port)
-{
-	return usb4_state[port] == USB4_ACTIVE ||
-		usb4_state[port] == USB4_INACTIVE;
-}
-
-void usb4_exit_mode_request(int port)
-{
-	usb4_state[port] = USB4_START;
-	usb_mux_set_safe_mode_exit(port);
-	set_usb_mux_with_current_data_role(port);
-}
-
-void enter_usb_init(int port)
-{
-	usb4_state[port] = USB4_START;
-}
-
-void enter_usb_failed(int port)
-{
-	/*
-	 * Since Enter USB sets the mux state to SAFE mode, fall back
-	 * to USB mode on receiving a NAK.
-	 */
-	usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
-		    polarity_rm_dts(pd_get_polarity(port)));
-
-	usb4_debug_prints(port, USB4_MODE_FAILURE);
-	usb4_state[port] = USB4_INACTIVE;
-}
-
-static bool enter_usb_response_valid(int port, enum tcpci_msg_type type)
-{
-	/*
-	 * Check for an unexpected response.
-	 */
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
-	     type != TCPCI_MSG_SOP) {
-		enter_usb_failed(port);
-		return false;
-	}
-	return true;
-}
-
-bool enter_usb_port_partner_is_capable(int port)
-{
-	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
-
-	if (usb4_state[port] == USB4_INACTIVE)
-		return false;
-
-	if (!PD_PRODUCT_IS_USB4(disc->identity.product_t1.raw_value))
-		return false;
-
-	return true;
-}
-
-bool enter_usb_cable_is_capable(int port)
-{
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
-		if (get_usb4_cable_speed(port) < USB_R30_SS_U32_U40_GEN1)
-			return false;
-	} else if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
-		const struct pd_discovery *disc_sop_prime =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) >= VDM_VER20 &&
-		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver >=
-							VDO_VERSION_1_3) {
-			union active_cable_vdo2_rev30 a2_rev30 =
-				disc_sop_prime->identity.product_t2.a2_rev30;
-			/*
-			 * For VDM version >= 2.0 and VD0 version is >= 1.3,
-			 * do not enter USB4 mode if the cable isn't USB4
-			 * capable.
-			 */
-			if (a2_rev30.usb_40_support == USB4_NOT_SUPPORTED)
-				return false;
-		/*
-		 * For VDM version < 2.0 or VDO version < 1.3, do not enter USB4
-		 * mode if the cable -
-		 * doesn't support modal operation or
-		 * doesn't support Intel SVID or
-		 * doesn't have rounded support.
-		 */
-		} else {
-			const struct pd_discovery *disc =
-				pd_get_am_discovery(port, TCPCI_MSG_SOP);
-			union tbt_mode_resp_cable cable_mode_resp = {
-				.raw_value = pd_get_tbt_mode_vdo(port,
-							TCPCI_MSG_SOP_PRIME) };
-
-			if (!disc->identity.idh.modal_support ||
-			   !pd_is_mode_discovered_for_svid(port,
-					TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) ||
-			    cable_mode_resp.tbt_rounded !=
-					TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED)
-				return false;
-		}
-	} else {
-		/* Not Emark cable */
-		return false;
-	}
-
-	return true;
-}
-
-void enter_usb_accepted(int port, enum tcpci_msg_type type)
-{
-	const struct pd_discovery *disc;
-
-	if (!enter_usb_response_valid(port, type))
-		return;
-
-	switch (usb4_state[port]) {
-	case USB4_ENTER_SOP_PRIME:
-		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		if (disc->identity.product_t1.a_rev20.sop_p_p)
-			usb4_state[port] = USB4_ENTER_SOP_PRIME_PRIME;
-		else
-			usb4_state[port] = USB4_ENTER_SOP;
-		break;
-	case USB4_ENTER_SOP_PRIME_PRIME:
-		usb4_state[port] = USB4_ENTER_SOP;
-		break;
-	case USB4_ENTER_SOP:
-		/* Connect the SBU and USB lines to the connector */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		usb4_state[port] = USB4_ACTIVE;
-
-		/* Set usb mux to USB4 mode */
-		usb_mux_set(port, USB_PD_MUX_USB4_ENABLED, USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-
-		usb4_debug_prints(port, USB4_MODE_SUCCESS);
-		break;
-	case USB4_ACTIVE:
-		break;
-	default:
-		enter_usb_failed(port);
-	}
-}
-
-void enter_usb_rejected(int port, enum tcpci_msg_type type)
-{
-	if (!enter_usb_response_valid(port, type) ||
-	    usb4_state[port] == USB4_ACTIVE)
-		return;
-
-	enter_usb_failed(port);
-}
-
-uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type)
-{
-	const struct pd_discovery *disc_sop_prime;
-
-	switch (usb4_state[port]) {
-	case USB4_START:
-		disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		/*
-		 * Ref: Tiger Lake Platform PD Controller Interface Requirements
-		 * for Integrated USBC, section A.2.2: USB4 as DFP.
-		 * Enter safe mode before sending Enter USB SOP/SOP'/SOP''
-		 * TODO (b/156749387): Remove once data reset feature is in
-		 * place.
-		 */
-		usb_mux_set_safe_mode(port);
-
-		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
-		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
-							VDO_VERSION_1_3 ||
-		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
-			usb4_state[port] = USB4_ENTER_SOP;
-		} else {
-			usb4_state[port] = USB4_ENTER_SOP_PRIME;
-			*type = TCPCI_MSG_SOP_PRIME;
-		}
-		break;
-	case USB4_ENTER_SOP_PRIME:
-		*type = TCPCI_MSG_SOP_PRIME;
-		break;
-	case USB4_ENTER_SOP_PRIME_PRIME:
-		*type = TCPCI_MSG_SOP_PRIME_PRIME;
-		break;
-	case USB4_ENTER_SOP:
-		*type = TCPCI_MSG_SOP;
-		break;
-	case USB4_ACTIVE:
-		return -1;
-	default:
-		return 0;
-	}
-	return get_enter_usb_msg_payload(port);
-}
diff --git a/common/usbc/usb_pd_console.c b/common/usbc/usb_pd_console.c
deleted file mode 100644
index bbee776611..0000000000
--- a/common/usbc/usb_pd_console.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "usb_common.h"
-#include "usb_pd_timer.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_pd.h"
-#include "util.h"
-
-test_export_static int command_pd(int argc, char **argv)
-{
-	int port;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "dump")) {
-		if (argc >= 3) {
-			int level = strtoi(argv[2], &e, 10);
-
-			if (*e)
-				return EC_ERROR_PARAM2;
-
-			if (level < DEBUG_DISABLE)
-				level = DEBUG_DISABLE;
-			else if (level > DEBUG_LEVEL_MAX)
-				level = DEBUG_LEVEL_MAX;
-
-			prl_set_debug_level(level);
-			pe_set_debug_level(level);
-			tc_set_debug_level(level);
-			ccprintf("debug=%d\n", level);
-			return EC_SUCCESS;
-		}
-	} else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
-				!strcasecmp(argv[1], "trysrc")) {
-		enum try_src_override_t ov = tc_get_try_src_override();
-
-		if (argc >= 3) {
-			ov = strtoi(argv[2], &e, 10);
-			if (*e || ov > TRY_SRC_NO_OVERRIDE)
-				return EC_ERROR_PARAM3;
-			tc_try_src_override(ov);
-		}
-
-		if (ov == TRY_SRC_NO_OVERRIDE)
-			ccprintf("Try.SRC System controlled\n");
-		else
-			ccprintf("Try.SRC Forced %s\n", ov ? "ON" : "OFF");
-
-		return EC_SUCCESS;
-	} else if (!strcasecmp(argv[1], "version")) {
-		ccprintf("%d\n", PD_STACK_VERSION);
-		return EC_SUCCESS;
-	}
-
-	/* command: pd <port> <subcmd> [args] */
-	port = strtoi(argv[1], &e, 10);
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (*e || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
-		return EC_ERROR_PARAM2;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) {
-		if (!strcasecmp(argv[2], "tx")) {
-			pd_dpm_request(port, DPM_REQUEST_SNK_STARTUP);
-		} else if (!strcasecmp(argv[2], "charger")) {
-			pd_dpm_request(port, DPM_REQUEST_SRC_STARTUP);
-		} else if (!strcasecmp(argv[2], "dev")) {
-			int max_volt;
-
-			if (argc >= 4) {
-				max_volt = strtoi(argv[3], &e, 10) * 1000;
-				if (*e)
-					return EC_ERROR_PARAM3;
-			} else {
-				max_volt = pd_get_max_voltage();
-			}
-			pd_request_source_voltage(port, max_volt);
-			pd_dpm_request(port, DPM_REQUEST_NEW_POWER_LEVEL);
-			ccprintf("max req: %dmV\n", max_volt);
-		} else if (!strcasecmp(argv[2], "disable")) {
-			pd_comm_enable(port, 0);
-			ccprintf("Port C%d disable\n", port);
-			return EC_SUCCESS;
-		} else if (!strcasecmp(argv[2], "enable")) {
-			pd_comm_enable(port, 1);
-			ccprintf("Port C%d enabled\n", port);
-			return EC_SUCCESS;
-		} else if (!strcasecmp(argv[2], "hard")) {
-			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
-		} else if (!strcasecmp(argv[2], "soft")) {
-			pd_dpm_request(port, DPM_REQUEST_SOFT_RESET_SEND);
-		} else if (!strcasecmp(argv[2], "swap")) {
-			if (argc < 4)
-				return EC_ERROR_PARAM_COUNT;
-
-			if (!strcasecmp(argv[3], "power"))
-				pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
-			else if (!strcasecmp(argv[3], "data"))
-				pd_dpm_request(port, DPM_REQUEST_DR_SWAP);
-			else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-					!strcasecmp(argv[3], "vconn"))
-				pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
-			else
-				return EC_ERROR_PARAM3;
-		} else if (!strcasecmp(argv[2], "dualrole")) {
-			if (argc < 4) {
-				cflush();
-				ccprintf("dual-role toggling: ");
-				switch (pd_get_dual_role(port)) {
-				case PD_DRP_TOGGLE_ON:
-					ccprintf("on\n");
-					break;
-				case PD_DRP_TOGGLE_OFF:
-					ccprintf("off\n");
-					break;
-				case PD_DRP_FREEZE:
-					ccprintf("freeze\n");
-					break;
-				case PD_DRP_FORCE_SINK:
-					ccprintf("force sink\n");
-					break;
-				case PD_DRP_FORCE_SOURCE:
-					ccprintf("force source\n");
-					break;
-				cflush();
-				}
-			} else {
-				if (!strcasecmp(argv[3], "on"))
-					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_ON);
-				else if (!strcasecmp(argv[3], "off"))
-					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_OFF);
-				else if (!strcasecmp(argv[3], "freeze"))
-					pd_set_dual_role(port, PD_DRP_FREEZE);
-				else if (!strcasecmp(argv[3], "sink"))
-					pd_set_dual_role(port,
-							PD_DRP_FORCE_SINK);
-				else if (!strcasecmp(argv[3], "source"))
-					pd_set_dual_role(port,
-							PD_DRP_FORCE_SOURCE);
-				else
-					return EC_ERROR_PARAM4;
-			}
-			return EC_SUCCESS;
-		}
-	}
-
-	if (!strcasecmp(argv[2], "state")) {
-		cflush();
-		ccprintf("Port C%d CC%d, %s - Role: %s-%s",
-		port, pd_get_polarity(port) + 1,
-		pd_comm_is_enabled(port) ? "Enable" : "Disable",
-		pd_get_power_role(port) ==
-					PD_ROLE_SOURCE ? "SRC" : "SNK",
-		pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP");
-
-		if (IS_ENABLED(CONFIG_USBC_VCONN))
-			ccprintf("%s ", tc_is_vconn_src(port) ? "-VC" : "");
-
-		ccprintf("TC State: %s, Flags: 0x%04x",
-			tc_get_current_state(port),
-			tc_get_flags(port));
-
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			ccprintf(" PE State: %s, Flags: 0x%04x\n",
-				pe_get_current_state(port),
-				pe_get_flags(port));
-		else
-			ccprintf("\n");
-
-		cflush();
-	} else if (!strcasecmp(argv[2], "srccaps")) {
-		pd_srccaps_dump(port);
-	}
-
-	if (IS_ENABLED(CONFIG_CMD_PD_TIMER) &&
-	    !strcasecmp(argv[2], "timer")) {
-		pd_timer_dump(port);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pd, command_pd,
-	 "version"
-	 "\ndump [0|1|2|3]"
-#ifdef CONFIG_USB_PD_TRY_SRC
-	"\ntrysrc [0|1|2]"
-#endif
-	"\n\t<port> state"
-	"\n\t<port> srccaps"
-#ifdef CONFIG_CMD_PD_TIMER
-	"\n\t<port> timer"
-#endif /* CONFIG_CMD_PD_TIMER */
-#ifdef CONFIG_USB_PD_DUAL_ROLE
-	"|tx|charger|dev"
-	"\n\t<port> disable|enable|soft|hard"
-	"\n\t<port> dualrole [on|off|freeze|sink|source]"
-	"\n\t<port> swap [power|data|vconn]"
-#endif /* CONFIG_USB_PD_DUAL_ROLE */
-	,
-	"USB PD");
diff --git a/common/usbc/usb_pd_dp_ufp.c b/common/usbc/usb_pd_dp_ufp.c
deleted file mode 100644
index 0009b5c710..0000000000
--- a/common/usbc/usb_pd_dp_ufp.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Functions required for UFP_D operation
- */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_pd_dp_ufp.h"
-
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-enum hpd_state {
-	LOW_WAIT,
-	HIGH_CHECK,
-	HIGH_WAIT,
-	LOW_CHECK,
-	IRQ_CHECK,
-};
-
-#define EDGE_QUEUE_DEPTH BIT(3)
-#define EDGE_QUEUE_MASK (EDGE_QUEUE_DEPTH - 1)
-#define HPD_QUEUE_DEPTH BIT(2)
-#define HPD_QUEUE_MASK (HPD_QUEUE_DEPTH - 1)
-#define HPD_T_IRQ_MIN_PULSE 250
-#define HPD_T_IRQ_MAX_PULSE (2 * MSEC)
-#define HPD_T_MIN_DP_ATTEN (10 * MSEC)
-
-struct hpd_mark {
-	int level;
-	uint64_t ts;
-};
-
-struct hpd_edge {
-	int overflow;
-	uint32_t head;
-	uint32_t tail;
-	struct hpd_mark buffer[EDGE_QUEUE_DEPTH];
-};
-
-struct hpd_info {
-	enum hpd_state state;
-	int count;
-	int send_enable;
-	uint64_t timer;
-	uint64_t last_send_ts;
-	enum hpd_event queue[HPD_QUEUE_DEPTH];
-	struct hpd_edge edges;
-};
-
-static struct hpd_info hpd;
-static struct mutex hpd_mutex;
-
-static int alt_dp_mode_opos[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void pd_ufp_set_dp_opos(int port, int opos)
-{
-	alt_dp_mode_opos[port] = opos;
-}
-
-int pd_ufp_get_dp_opos(int port)
-{
-	return alt_dp_mode_opos[port];
-}
-
-void pd_ufp_enable_hpd_send(int port)
-{
-	/*
-	 * This control is used ensure that a DP_ATTENTION message is not sent
-	 * to the DFP-D before a DP_CONFIG messaage has been received. This
-	 * control is not strictly required by the spec, but some port partners
-	 * will get confused if DP_ATTENTION is sent prior to DP_CONFIG.
-	 */
-	hpd.send_enable = 1;
-}
-
-static void hpd_to_dp_attention(void)
-{
-	int port = hpd_config.port;
-	int evt_index = hpd.count - 1;
-	uint32_t vdm[2];
-	uint32_t svdm_header;
-	enum hpd_event evt;
-	int opos = pd_ufp_get_dp_opos(port);
-
-	if (!opos)
-		return;
-
-	/* Get the next hpd event from the queue */
-	evt = hpd.queue[evt_index];
-	/* Save timestamp of when most recent DP attention message was sent */
-	hpd.last_send_ts = get_time().val;
-
-	/*
-	 * Construct DP Attention message. This consists of the VDM header and
-	 * the DP_STATUS VDO.
-	 */
-	svdm_header = VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) |
-			       VDO_OPOS(opos) | CMD_ATTENTION;
-	vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, svdm_header);
-
-	vdm[1] = VDO_DP_STATUS((evt == hpd_irq), /* IRQ_HPD */
-				(evt != hpd_low), /* HPD_HI|LOW */
-				0, /* request exit DP */
-				0, /* request exit USB */
-				dock_get_mf_preference(), /* MF pref */
-				1, /* enabled */
-				0, /* power low */
-				0x2);
-
-	/* Send request to DPM to send an attention VDM */
-	pd_request_vdm_attention(port, vdm, ARRAY_SIZE(vdm));
-
-	/* If there are still events, need to shift the buffer */
-	if (--hpd.count) {
-		int i;
-
-		for (i = 0; i < hpd.count; i++)
-			hpd.queue[i] = hpd.queue[i + 1];
-	}
-}
-
-static void hpd_queue_event(enum hpd_event evt)
-{
-	/*
-	 * HPD events are put into a queue. However, this queue is not a typical
-	 * FIFO queue. Instead there are special rules based on which type of
-	 * event is being added.
-	 *     HPD_LOW -> always resets the queue and must be in slot 0
-	 *     HPD_HIGH -> must follow a HPD_LOW, so can only be in slot 0 or
-	 *                 slot 1.
-	 *     HPD_IRQ  -> There shall never be more than 2 HPD_IRQ events
-	 *                 stored in the queue and HPD_IRQ must follow HPD_HIGH
-	 *
-	 * Worst case for queueing HPD events is 4 events in the queue:
-	 *    0 - HPD_LOW
-	 *    1 - HPD_HIGH
-	 *    2 - HPD_IRQ
-	 *    3 - HPD_IRQ
-	 *
-	 * The above rules mean that HPD_LOW and HPD_HIGH events can always be
-	 * added to the queue since high must follow low and a low event resets
-	 * the queue. HPD_IRQ events are checked to make sure that they don't
-	 * overflow the queue and to ensure that no more than 2 hpd_irq events
-	 * are kept in the queue.
-	 */
-	if (evt == hpd_irq) {
-		if ((hpd.count >= HPD_QUEUE_DEPTH) || ((hpd.count  >= 2) &&
-			(hpd.queue[hpd.count - 2] == hpd_irq))) {
-			CPRINTS("hpd: discard hpd: count - %d",
-				hpd.count);
-			return;
-		}
-	}
-
-	if (evt == hpd_low) {
-		hpd.count = 0;
-	}
-
-	/* Add event to the queue */
-	hpd.queue[hpd.count++] = evt;
-}
-
-static void hpd_to_pd_converter(int level, uint64_t ts)
-{
-	/*
-	 * HPD edges are marked in the irq routine. The converter state machine
-	 * runs in the hooks task and so there will be some delay between when
-	 * the edge was captured and when that edge is processed here in the
-	 * state machine. This means that the delitch timer (250 uSec) may have
-	 * already expired or is about to expire.
-	 *
-	 * If transitioning to timing dependent state, need to ensure the state
-	 * machine is executed again. All timers are relative to the ts value
-	 * passed into this routine. The timestamps passed into this routine
-	 * are either the values latched in the irq routine, or the current
-	 * time latched by the calling function. From the perspective of the
-	 * state machine, ts represents the current time.
-	 *
-	 * Note that all hpd queue events are contingent on detecting edges
-	 * on the incoming hpd gpio signal. The hpd->dp attention converter is
-	 * enabled/disabled as part of the svdm dp enter/exit response handler
-	 * functions. When the converter is disabled, gpio interrupts for the
-	 * hpd gpio signal are disabled so it will never execute, unless the
-	 * converter is enabled, and the converter is only enabled when the
-	 * UFP-D is actively in ALT-DP mode.
-	 */
-	switch (hpd.state) {
-	case LOW_WAIT:
-		/*
-		 * In this state only expected event is a level change from low
-		 * to high.
-		 */
-		if (level) {
-			hpd.state = HIGH_CHECK;
-			hpd.timer = ts + HPD_T_IRQ_MIN_PULSE;
-		}
-		break;
-	case HIGH_CHECK:
-		/*
-		 * In this state if level is high and deglitch timer is
-		 * exceeded, then state advances to HIGH_WAIT, otherwise return
-		 * to LOW_WAIT state.
-		 */
-		if (!level || (ts <= hpd.timer)) {
-			hpd.state = LOW_WAIT;
-		} else {
-			hpd.state = HIGH_WAIT;
-			hpd_queue_event(hpd_high);
-		}
-		break;
-	case HIGH_WAIT:
-		/*
-		 * In this state, only expected event is a level change from
-		 * high to low. If current level is low, then advance to
-		 * LOW_CHECK for deglitch checking.
-		 */
-		if (!level) {
-			hpd.state = LOW_CHECK;
-			hpd.timer = ts + HPD_T_IRQ_MIN_PULSE;
-		}
-		break;
-	case LOW_CHECK:
-		/*
-		 * This state is used to deglitch high->low level
-		 * change. However, due to processing latency, it's possible to
-		 * detect hpd_irq event if level is high and low pulse width was
-		 * valid.
-		 */
-		if (!level) {
-			/* Still low, now wait for IRQ or LOW determination */
-			hpd.timer = ts + (HPD_T_IRQ_MAX_PULSE -
-					  HPD_T_IRQ_MIN_PULSE);
-			hpd.state = IRQ_CHECK;
-
-		} else {
-			uint64_t irq_ts = hpd.timer + HPD_T_IRQ_MAX_PULSE -
-				HPD_T_IRQ_MIN_PULSE;
-			/*
-			 * If hpd is high now, this must have been an edge
-			 * event, but still need to determine if the pulse width
-			 * is longer than hpd_irq min pulse width. State will
-			 * advance to HIGH_WAIT, but if pulse width is < 2 msec,
-			 * must send hpd_irq event.
-			 */
-			if ((ts >= hpd.timer) && (ts <= irq_ts)) {
-				/* hpd irq detected */
-				hpd_queue_event(hpd_irq);
-			}
-			hpd.state = HIGH_WAIT;
-		}
-		break;
-	case IRQ_CHECK:
-		/*
-		 * In this state deglitch time has already passed. If current
-		 * level is low and hpd_irq timer has expired, then go to
-		 * LOW_WAIT as hpd_low event has been detected. If level is high
-		 * and low pulse is < hpd_irq, hpd_irq event has been detected.
-		 */
-		if (level) {
-			hpd.state = HIGH_WAIT;
-			if (ts <= hpd.timer) {
-				hpd_queue_event(hpd_irq);
-			}
-		} else if (ts >  hpd.timer) {
-			hpd.state = LOW_WAIT;
-			hpd_queue_event(hpd_low);
-		}
-		break;
-	}
-}
-
-static void manage_hpd(void);
-DECLARE_DEFERRED(manage_hpd);
-
-static void manage_hpd(void)
-{
-	int level;
-	uint64_t ts = get_time().val;
-	uint32_t num_hpd_events = (hpd.edges.head - hpd.edges.tail) &
-		EDGE_QUEUE_MASK;
-
-	/*
-	 * HPD edges are detected via GPIO interrupts. The ISR routine adds edge
-	 * info to a queue and scheudles this routine. If this routine is called
-	 * without a new edge detected, then it is being called due to a timer
-	 * event.
-	 */
-
-	/* First check to see overflow condition has occurred */
-	if (hpd.edges.overflow) {
-		/* Disable hpd interrupts */
-		usb_pd_hpd_converter_enable(0);
-		/* Re-enable hpd converter */
-		usb_pd_hpd_converter_enable(1);
-	}
-
-	if (num_hpd_events) {
-		while(num_hpd_events-- > 0) {
-			int idx = hpd.edges.tail;
-
-			level = hpd.edges.buffer[idx].level;
-			ts = hpd.edges.buffer[idx].ts;
-
-			hpd_to_pd_converter(level, ts);
-			hpd.edges.tail = (hpd.edges.tail + 1) & EDGE_QUEUE_MASK;
-		}
-	} else {
-		/* no new edge event, so get current time and level */
-		level = gpio_get_level(hpd_config.signal);
-		ts = get_time().val;
-		hpd_to_pd_converter(level, ts);
-	}
-
-	/*
-	 * If min time spacing requirement is exceeded and a hpd_event is
-	 * queued, then send DP_ATTENTION message.
-	 */
-	if (hpd.count > 0) {
-		/*
-		 * If at least one hpd event is pending in the queue, send
-		 * a DP_ATTENTION message if a DP_CONFIG message has been
-		 * received and have passed the minimum spacing interval.
-		 */
-		if (hpd.send_enable &&
-		    ((get_time().val - hpd.last_send_ts) >
-		     HPD_T_MIN_DP_ATTEN)) {
-			/* Generate DP_ATTENTION event pending in queue */
-			hpd_to_dp_attention();
-		} else {
-			uint32_t callback_us;
-
-			/*
-			 * Need to wait until until min spacing requirement of
-			 * DP attention messages. Set callback time to the min
-			 * value required. This callback time could be changed
-			 * based on hpd interrupts.
-			 *
-			 * This wait is also used to prevent a DP_ATTENTION
-			 * message from being sent before at least one DP_CONFIG
-			 * message has been received. If DP_ATTENTION messages
-			 * need to be delayed for this reason, then just wait
-			 * the minimum time spacing.
-			 */
-			callback_us = HPD_T_MIN_DP_ATTEN -
-				(get_time().val - hpd.last_send_ts);
-			if (callback_us <= 0 ||
-			    callback_us > HPD_T_MIN_DP_ATTEN)
-				callback_us = HPD_T_MIN_DP_ATTEN;
-			hook_call_deferred(&manage_hpd_data, callback_us);
-		}
-	}
-
-	/*
-	 * Because of the delay between gpio edge irq, and when those edge
-	 * events are processed here, all timers must be done relative to the
-	 * timing marker stored in the hpd edge queue. If the state machine
-	 * required a new timer, then hpd.timer will be advanced relative to the
-	 * ts that was passed into the state machine.
-	 *
-	 * If the deglitch timer is active, then it can likely already have been
-	 * expired when the edge gets processed. So if the timer is active the
-	 * deferred callback must be requested.
-	 *.
-	 */
-	if (hpd.timer > ts) {
-		uint64_t callback_us = 0;
-		uint64_t now = get_time().val;
-
-		/* If timer is in the future, adjust the callback timer */
-		if (now < hpd.timer)
-			callback_us = (hpd.timer - now) & 0xffffffff;
-
-		hook_call_deferred(&manage_hpd_data, callback_us);
-	}
-}
-
-void usb_pd_hpd_converter_enable(int enable)
-{
-	/*
-	 * The hpd converter should be enabled as part of the UFP-D enter mode
-	 * response function. Likewise, the converter should be disabled by the
-	 * exit mode function. In addition, the coverter may get disabled so
-	 * that it can be reset in the case that the input gpio edges queue
-	 * overflows. A muxtex must be used here since this function may be
-	 * called from the PD task (enter/exit response mode functions) or from
-	 * the hpd event handler state machine (hook task).
-	 */
-	mutex_lock(&hpd_mutex);
-
-	if (enable) {
-		gpio_disable_interrupt(hpd_config.signal);
-		/* Reset HPD event queue */
-		hpd.state = LOW_WAIT;
-		hpd.count = 0;
-		hpd.timer = 0;
-	        hpd.last_send_ts = 0;
-		hpd.send_enable = 0;
-
-		/* Reset hpd signal edges queue */
-		hpd.edges.head = 0;
-		hpd.edges.tail = 0;
-		hpd.edges.overflow = 0;
-
-		/* If signal is high, need to ensure state machine executes */
-		if (gpio_get_level(hpd_config.signal))
-			hook_call_deferred(&manage_hpd_data, 0);
-
-		/* Enable hpd edge detection */
-		gpio_enable_interrupt(hpd_config.signal);
-	} else {
-		gpio_disable_interrupt(hpd_config.signal);
-		hook_call_deferred(&manage_hpd_data, -1);
-	}
-
-	mutex_unlock(&hpd_mutex);
-}
-
-void usb_pd_hpd_edge_event(int signal)
-{
-	int  next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK;
-	struct hpd_mark mark;
-
-	/* Get current timestamp and level */
-	mark.ts = get_time().val;
-	mark.level = gpio_get_level(hpd_config.signal);
-
-	/* Add this edge to the buffer if there is space */
-	if (next_head != hpd.edges.tail) {
-		hpd.edges.buffer[hpd.edges.head].ts = mark.ts;
-		hpd.edges.buffer[hpd.edges.head].level = mark.level;
-		hpd.edges.head = next_head;
-	} else {
-		/* Edge queue is overflowing, need to reset the converter */
-		hpd.edges.overflow = 1;
-	}
-	/* Schedule HPD state machine to run ASAP */
-	hook_call_deferred(&manage_hpd_data, 0);
-}
diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c
deleted file mode 100644
index eb2dfc52c0..0000000000
--- a/common/usbc/usb_pd_dpm.c
+++ /dev/null
@@ -1,704 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Device Policy Manager implementation
- * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
- */
-
-#include "charge_state.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mode.h"
-#include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_tcpm.h"
-#include "usb_tbt_alt_mode.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* Max Attention length is header + 1 VDO */
-#define DPM_ATTENION_MAX_VDO 2
-
-static struct {
-	uint32_t flags;
-	uint32_t vdm_attention[DPM_ATTENION_MAX_VDO];
-	int vdm_cnt;
-	mutex_t vdm_attention_mutex;
-} dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define DPM_SET_FLAG(port, flag) atomic_or(&dpm[(port)].flags, (flag))
-#define DPM_CLR_FLAG(port, flag) atomic_clear_bits(&dpm[(port)].flags, (flag))
-#define DPM_CHK_FLAG(port, flag) (dpm[(port)].flags & (flag))
-
-/* Flags for internal DPM state */
-#define DPM_FLAG_MODE_ENTRY_DONE BIT(0)
-#define DPM_FLAG_EXIT_REQUEST    BIT(1)
-#define DPM_FLAG_ENTER_DP        BIT(2)
-#define DPM_FLAG_ENTER_TBT       BIT(3)
-#define DPM_FLAG_ENTER_USB4      BIT(4)
-#define DPM_FLAG_SEND_ATTENTION  BIT(5)
-
-#ifdef CONFIG_ZEPHYR
-static int init_vdm_attention_mutex(const struct device *dev)
-{
-	int port;
-
-	ARG_UNUSED(dev);
-
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-		k_mutex_init(&dpm[port].vdm_attention_mutex);
-
-	return 0;
-}
-SYS_INIT(init_vdm_attention_mutex, POST_KERNEL, 50);
-#endif /* CONFIG_ZEPHYR */
-
-enum ec_status pd_request_vdm_attention(int port, const uint32_t *data,
-					int vdo_count)
-{
-	mutex_lock(&dpm[port].vdm_attention_mutex);
-
-	/* Only one Attention message may be pending */
-	if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_ATTENTION)) {
-		mutex_unlock(&dpm[port].vdm_attention_mutex);
-		return EC_RES_UNAVAILABLE;
-	}
-
-	/* SVDM Attention message must be 1 or 2 VDOs in length */
-	if (!vdo_count || (vdo_count > DPM_ATTENION_MAX_VDO)) {
-		mutex_unlock(&dpm[port].vdm_attention_mutex);
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/* Save contents of Attention message */
-	memcpy(dpm[port].vdm_attention, data, vdo_count * sizeof(uint32_t));
-	dpm[port].vdm_cnt = vdo_count;
-
-	/*
-	 * Indicate to DPM that an Attention message needs to be sent. This flag
-	 * will be cleared when the Attention message is sent to the policy
-	 * engine.
-	 */
-	DPM_SET_FLAG(port, DPM_FLAG_SEND_ATTENTION);
-
-	mutex_unlock(&dpm[port].vdm_attention_mutex);
-
-	return EC_RES_SUCCESS;
-}
-
-enum ec_status pd_request_enter_mode(int port, enum typec_mode mode)
-{
-	if (port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	/* Only one enter request may be active at a time. */
-	if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP |
-				DPM_FLAG_ENTER_TBT |
-				DPM_FLAG_ENTER_USB4))
-		return EC_RES_BUSY;
-
-	switch (mode) {
-	case TYPEC_MODE_DP:
-		DPM_SET_FLAG(port, DPM_FLAG_ENTER_DP);
-		break;
-#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
-	case TYPEC_MODE_TBT:
-		DPM_SET_FLAG(port, DPM_FLAG_ENTER_TBT);
-		break;
-#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
-#ifdef CONFIG_USB_PD_USB4
-	case TYPEC_MODE_USB4:
-		DPM_SET_FLAG(port, DPM_FLAG_ENTER_USB4);
-		break;
-#endif
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
-	DPM_CLR_FLAG(port, DPM_FLAG_EXIT_REQUEST);
-
-	return EC_RES_SUCCESS;
-}
-
-void dpm_init(int port)
-{
-	dpm[port].flags = 0;
-}
-
-static void dpm_set_mode_entry_done(int port)
-{
-	DPM_SET_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
-	DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
-			DPM_FLAG_ENTER_USB4);
-}
-
-void dpm_set_mode_exit_request(int port)
-{
-	DPM_SET_FLAG(port, DPM_FLAG_EXIT_REQUEST);
-}
-
-static void dpm_clear_mode_exit_request(int port)
-{
-	DPM_CLR_FLAG(port, DPM_FLAG_EXIT_REQUEST);
-}
-
-/*
- * Returns true if the current policy requests that the EC try to enter this
- * mode on this port. If the EC is in charge of policy, the answer is always
- * yes.
- */
-static bool dpm_mode_entry_requested(int port, enum typec_mode mode)
-{
-	/* If the AP isn't controlling policy, the EC is. */
-	if (!IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY))
-		return true;
-
-	switch (mode) {
-	case TYPEC_MODE_DP:
-		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP);
-	case TYPEC_MODE_TBT:
-		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_TBT);
-	case TYPEC_MODE_USB4:
-		return !!DPM_CHK_FLAG(port, DPM_FLAG_ENTER_USB4);
-	default:
-		return false;
-	}
-}
-
-void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
-{
-	const uint16_t svid = PD_VDO_VID(vdm[0]);
-
-	assert(vdo_count >= 1);
-
-	switch (svid) {
-	case USB_SID_DISPLAYPORT:
-		dp_vdm_acked(port, type, vdo_count, vdm);
-		break;
-	case USB_VID_INTEL:
-		if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-			intel_vdm_acked(port, type, vdo_count, vdm);
-			break;
-		}
-	default:
-		CPRINTS("C%d: Received unexpected VDM ACK for SVID %d", port,
-				svid);
-	}
-}
-
-void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
-{
-	switch (svid) {
-	case USB_SID_DISPLAYPORT:
-		dp_vdm_naked(port, type, vdm_cmd);
-		break;
-	case USB_VID_INTEL:
-		if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-			intel_vdm_naked(port, type, vdm_cmd);
-			break;
-		}
-	default:
-		CPRINTS("C%d: Received unexpected VDM NAK for SVID %d", port,
-				svid);
-	}
-}
-
-/*
- * Requests that the PE send one VDM, whichever is next in the mode entry
- * sequence. This only happens if preconditions for mode entry are met. If
- * CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY is enabled, this function waits for the
- * AP to direct mode entry.
- */
-static void dpm_attempt_mode_entry(int port)
-{
-	int vdo_count = 0;
-	uint32_t vdm[VDO_MAX_SIZE];
-	enum tcpci_msg_type tx_type = TCPCI_MSG_SOP;
-	bool enter_mode_requested =
-		IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ?  false : true;
-
-	if (pd_get_data_role(port) != PD_ROLE_DFP) {
-		if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP |
-					DPM_FLAG_ENTER_TBT |
-					DPM_FLAG_ENTER_USB4))
-			DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP |
-					DPM_FLAG_ENTER_TBT |
-					DPM_FLAG_ENTER_USB4);
-		/*
-		 * TODO(b/168030639): Notify the AP that the enter mode request
-		 * failed.
-		 */
-		return;
-	}
-
-#ifdef HAS_TASK_CHIPSET
-	/*
-	 * Do not try to enter mode while CPU is off.
-	 * CPU transitions (e.g b/158634281) can occur during the discovery
-	 * phase or during enter/exit negotiations, and the state
-	 * of the modes can get out of sync, causing the attempt to
-	 * enter the mode to fail prematurely.
-	 */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
-		return;
-#endif
-	/*
-	 * If discovery has not occurred for modes, do not attempt to switch
-	 * to alt mode.
-	 */
-	if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) != PD_DISC_COMPLETE ||
-	    pd_get_modes_discovery(port, TCPCI_MSG_SOP) != PD_DISC_COMPLETE)
-		return;
-
-	if (dp_entry_is_done(port) ||
-	   (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-				tbt_entry_is_done(port)) ||
-	   (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) {
-		dpm_set_mode_entry_done(port);
-		return;
-	}
-
-	/* Check if port, port partner and cable support USB4. */
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	    board_is_tbt_usb4_port(port) &&
-	    enter_usb_port_partner_is_capable(port) &&
-	    enter_usb_cable_is_capable(port) &&
-	    dpm_mode_entry_requested(port, TYPEC_MODE_USB4)) {
-		/*
-		 * For certain cables, enter Thunderbolt alt mode with the
-		 * cable and USB4 mode with the port partner.
-		 */
-		if (tbt_cable_entry_required_for_usb4(port)) {
-			vdo_count = tbt_setup_next_vdm(port,
-				ARRAY_SIZE(vdm), vdm, &tx_type);
-		} else {
-			pd_dpm_request(port, DPM_REQUEST_ENTER_USB);
-			return;
-		}
-	}
-
-	/* If not, check if they support Thunderbolt alt mode. */
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-			board_is_tbt_usb4_port(port) &&
-			pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
-				USB_VID_INTEL) &&
-			dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) {
-		enter_mode_requested = true;
-		vdo_count = tbt_setup_next_vdm(port,
-			ARRAY_SIZE(vdm), vdm, &tx_type);
-	}
-
-	/* If not, check if they support DisplayPort alt mode. */
-	if (vdo_count == 0 && !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE) &&
-	    pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
-				USB_SID_DISPLAYPORT) &&
-	    dpm_mode_entry_requested(port, TYPEC_MODE_DP)) {
-		enter_mode_requested = true;
-		vdo_count = dp_setup_next_vdm(port, ARRAY_SIZE(vdm), vdm);
-	}
-
-	/*
-	 * If the PE didn't discover any supported (requested) alternate mode,
-	 * just mark setup done and get out of here.
-	 */
-	if (vdo_count == 0 && !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) {
-		if (enter_mode_requested) {
-			/*
-			 * TODO(b/168030639): Notify the AP that mode entry
-			 * failed.
-			 */
-			CPRINTS("C%d: No supported alt mode discovered", port);
-		}
-		/*
-		 * If the AP did not request mode entry, it may do so in the
-		 * future, but the DPM is done trying for now.
-		 */
-		dpm_set_mode_entry_done(port);
-		return;
-	}
-
-	if (vdo_count < 0) {
-		dpm_set_mode_entry_done(port);
-		CPRINTS("C%d: Couldn't construct alt mode VDM", port);
-		return;
-	}
-
-	/*
-	 * TODO(b/155890173): Provide a host command to request that the PE send
-	 * an arbitrary VDM via this mechanism.
-	 */
-	if (!pd_setup_vdm_request(port, tx_type, vdm, vdo_count)) {
-		dpm_set_mode_entry_done(port);
-		return;
-	}
-
-	pd_dpm_request(port, DPM_REQUEST_VDM);
-}
-
-static void dpm_attempt_mode_exit(int port)
-{
-	uint32_t vdm = 0;
-	int vdo_count = 0;
-	enum tcpci_msg_type tx_type = TCPCI_MSG_SOP;
-
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	    enter_usb_entry_is_done(port)) {
-		CPRINTS("C%d: USB4 teardown", port);
-		usb4_exit_mode_request(port);
-	}
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-	    tbt_is_active(port)) {
-		/*
-		 * When the port is in USB4 mode and receives an exit request,
-		 * it leaves USB4 SOP in active state.
-		 * TODO(b/156749387): Support Data Reset for exiting USB4 SOP.
-		 */
-		CPRINTS("C%d: TBT teardown", port);
-		tbt_exit_mode_request(port);
-		vdo_count = tbt_setup_next_vdm(port, VDO_MAX_SIZE, &vdm,
-					&tx_type);
-	} else if (dp_is_active(port)) {
-		CPRINTS("C%d: DP teardown", port);
-		vdo_count = dp_setup_next_vdm(port, VDO_MAX_SIZE, &vdm);
-	} else {
-		/* Clear exit mode request */
-		dpm_clear_mode_exit_request(port);
-		return;
-	}
-
-	if (!pd_setup_vdm_request(port, tx_type, &vdm, vdo_count)) {
-		dpm_clear_mode_exit_request(port);
-		return;
-	}
-
-	pd_dpm_request(port, DPM_REQUEST_VDM);
-}
-
-static void dpm_send_attention_vdm(int port)
-{
-	/* Set up VDM ATTEN msg that was passed in previously */
-	if (pd_setup_vdm_request(port, TCPCI_MSG_SOP, dpm[port].vdm_attention,
-				 dpm[port].vdm_cnt) == true)
-		/* Trigger PE to start a VDM command run */
-		pd_dpm_request(port, DPM_REQUEST_VDM);
-
-	/* Clear flag after message is sent to PE layer */
-	DPM_CLR_FLAG(port, DPM_FLAG_SEND_ATTENTION);
-}
-
-void dpm_run(int port)
-{
-	if (pd_get_data_role(port) == PD_ROLE_DFP) {
-		/* Run DFP related DPM requests */
-		if (DPM_CHK_FLAG(port, DPM_FLAG_EXIT_REQUEST))
-			dpm_attempt_mode_exit(port);
-		else if (!DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE))
-			dpm_attempt_mode_entry(port);
-	} else {
-		/* Run UFP related DPM requests */
-		if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_ATTENTION))
-			dpm_send_attention_vdm(port);
-	}
-}
-
-/*
- * Source-out policy variables and APIs
- *
- * Priority for the available 3.0 A ports is given in the following order:
- * - sink partners which report requiring > 1.5 A in their Sink_Capabilities
- */
-
-/*
- * Bitmasks of port numbers in each following category
- *
- * Note: request bitmasks should be accessed atomically as other ports may alter
- * them
- */
-static uint32_t		max_current_claimed;
-K_MUTEX_DEFINE(max_current_claimed_lock);
-
-/* Ports with PD sink needing > 1.5 A */
-static uint32_t sink_max_pdo_requested;
-/* Ports with FRS source needing > 1.5 A */
-static uint32_t source_frs_max_requested;
-/* Ports with non-PD sinks, so current requirements are unknown */
-static uint32_t non_pd_sink_max_requested;
-
-#define LOWEST_PORT(p) __builtin_ctz(p)  /* Undefined behavior if p == 0 */
-
-static int count_port_bits(uint32_t bitmask)
-{
-	int i, total = 0;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (bitmask & BIT(i))
-			total++;
-	}
-
-	return total;
-}
-
-/*
- * Centralized, mutex-controlled updates to the claimed 3.0 A ports
- */
-static void balance_source_ports(void);
-DECLARE_DEFERRED(balance_source_ports);
-
-static void balance_source_ports(void)
-{
-	uint32_t removed_ports, new_ports;
-	static bool deferred_waiting;
-
-	if (task_get_current() == TASK_ID_HOOKS)
-		deferred_waiting = false;
-
-	/*
-	 * Ignore balance attempts while we're waiting for a downgraded port to
-	 * finish the downgrade.
-	 */
-	if (deferred_waiting)
-		return;
-
-	mutex_lock(&max_current_claimed_lock);
-
-	/* Remove any ports which no longer require 3.0 A */
-	removed_ports = max_current_claimed & ~(sink_max_pdo_requested |
-						source_frs_max_requested |
-						non_pd_sink_max_requested);
-	max_current_claimed &= ~removed_ports;
-
-	/* Allocate 3.0 A to new PD sink ports that need it */
-	new_ports = sink_max_pdo_requested & ~max_current_claimed;
-	while (new_ports) {
-		int new_max_port = LOWEST_PORT(new_ports);
-
-		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
-			max_current_claimed |= BIT(new_max_port);
-			typec_select_src_current_limit_rp(new_max_port,
-							  TYPEC_RP_3A0);
-		} else if (non_pd_sink_max_requested & max_current_claimed) {
-			/* Always downgrade non-PD ports first */
-			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
-						     max_current_claimed);
-			typec_select_src_current_limit_rp(rem_non_pd,
-				typec_get_default_current_limit_rp(rem_non_pd));
-			max_current_claimed &= ~BIT(rem_non_pd);
-
-			/* Wait tSinkAdj before using current */
-			deferred_waiting = true;
-			hook_call_deferred(&balance_source_ports_data,
-					   PD_T_SINK_ADJ);
-			goto unlock;
-		} else if (source_frs_max_requested & max_current_claimed) {
-			/* Downgrade lowest FRS port from 3.0 A slot */
-			int rem_frs = LOWEST_PORT(source_frs_max_requested &
-						 max_current_claimed);
-			pd_dpm_request(rem_frs, DPM_REQUEST_FRS_DET_DISABLE);
-			max_current_claimed &= ~BIT(rem_frs);
-
-			/* Give 20 ms for the PD task to process DPM flag */
-			deferred_waiting = true;
-			hook_call_deferred(&balance_source_ports_data,
-					   20 * MSEC);
-			goto unlock;
-		} else {
-			/* No lower priority ports to downgrade */
-			goto unlock;
-		}
-		new_ports &= ~BIT(new_max_port);
-	}
-
-	/* Allocate 3.0 A to any new FRS ports that need it */
-	new_ports = source_frs_max_requested & ~max_current_claimed;
-	while (new_ports) {
-		int new_frs_port = LOWEST_PORT(new_ports);
-
-		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
-			max_current_claimed |= BIT(new_frs_port);
-			pd_dpm_request(new_frs_port,
-				       DPM_REQUEST_FRS_DET_ENABLE);
-		} else if (non_pd_sink_max_requested & max_current_claimed) {
-			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
-						     max_current_claimed);
-			typec_select_src_current_limit_rp(rem_non_pd,
-				typec_get_default_current_limit_rp(rem_non_pd));
-			max_current_claimed &= ~BIT(rem_non_pd);
-
-			/* Wait tSinkAdj before using current */
-			deferred_waiting = true;
-			hook_call_deferred(&balance_source_ports_data,
-					   PD_T_SINK_ADJ);
-			goto unlock;
-		} else {
-			/* No lower priority ports to downgrade */
-			goto unlock;
-		}
-		new_ports &= ~BIT(new_frs_port);
-	}
-
-	/* Allocate 3.0 A to any non-PD ports which could need it */
-	new_ports = non_pd_sink_max_requested & ~max_current_claimed;
-	while (new_ports) {
-		int new_max_port = LOWEST_PORT(new_ports);
-
-		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
-			max_current_claimed |= BIT(new_max_port);
-			typec_select_src_current_limit_rp(new_max_port,
-							  TYPEC_RP_3A0);
-		} else {
-			/* No lower priority ports to downgrade */
-			goto unlock;
-		}
-		new_ports &= ~BIT(new_max_port);
-	}
-unlock:
-	mutex_unlock(&max_current_claimed_lock);
-}
-
-/* Process port's first Sink_Capabilities PDO for port current consideration */
-void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
-{
-	/* Verify partner supplied valid vSafe5V fixed object first */
-	if ((vsafe5v_pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-		return;
-
-	if (PDO_FIXED_VOLTAGE(vsafe5v_pdo) != 5000)
-		return;
-
-	if (pd_get_power_role(port) == PD_ROLE_SOURCE) {
-		if (CONFIG_USB_PD_3A_PORTS == 0)
-			return;
-
-		/* Valid PDO to process, so evaluate whether >1.5A is needed */
-		if (PDO_FIXED_CURRENT(vsafe5v_pdo) <= 1500)
-			return;
-
-		atomic_or(&sink_max_pdo_requested, BIT(port));
-	} else {
-		int frs_current = vsafe5v_pdo & PDO_FIXED_FRS_CURR_MASK;
-
-		if (!IS_ENABLED(CONFIG_USB_PD_FRS))
-			return;
-
-		/* FRS is only supported in PD 3.0 and higher */
-		if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV20)
-			return;
-
-		if ((vsafe5v_pdo & PDO_FIXED_DUAL_ROLE) && frs_current) {
-			/* Always enable FRS when 3.0 A is not needed */
-			if (frs_current == PDO_FIXED_FRS_CURR_DFLT_USB_POWER ||
-			    frs_current == PDO_FIXED_FRS_CURR_1A5_AT_5V) {
-				pd_dpm_request(port,
-					       DPM_REQUEST_FRS_DET_ENABLE);
-				return;
-			}
-
-			if (CONFIG_USB_PD_3A_PORTS == 0)
-				return;
-
-			atomic_or(&source_frs_max_requested, BIT(port));
-		} else {
-			return;
-		}
-	}
-
-	balance_source_ports();
-}
-
-void dpm_add_non_pd_sink(int port)
-{
-	if (CONFIG_USB_PD_3A_PORTS == 0)
-		return;
-
-	atomic_or(&non_pd_sink_max_requested, BIT(port));
-
-	balance_source_ports();
-}
-
-void dpm_remove_sink(int port)
-{
-	if (CONFIG_USB_PD_3A_PORTS == 0)
-		return;
-
-	if (!(BIT(port) & sink_max_pdo_requested) &&
-	    !(BIT(port) & non_pd_sink_max_requested))
-		return;
-
-	atomic_clear_bits(&sink_max_pdo_requested, BIT(port));
-	atomic_clear_bits(&non_pd_sink_max_requested, BIT(port));
-
-	/* Restore selected default Rp on the port */
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
-
-	balance_source_ports();
-}
-
-void dpm_remove_source(int port)
-{
-	if (CONFIG_USB_PD_3A_PORTS == 0)
-		return;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_FRS))
-		return;
-
-	if (!(BIT(port) & source_frs_max_requested))
-		return;
-
-	atomic_clear_bits(&source_frs_max_requested, BIT(port));
-
-	balance_source_ports();
-}
-
-/*
- * Note: all ports receive the 1.5 A source offering until they are found to
- * match a criteria on the 3.0 A priority list (ex. through sink capability
- * probing), at which point they will be offered a new 3.0 A source capability.
- */
-__overridable int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	/* Max PDO may not exist on boards which don't offer 3 A */
-#if CONFIG_USB_PD_3A_PORTS > 0
-	if (max_current_claimed & BIT(port)) {
-		*src_pdo = pd_src_pdo_max;
-		return pd_src_pdo_max_cnt;
-	}
-#endif
-
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnt;
-}
-
-int dpm_get_source_current(const int port)
-{
-	if (pd_get_power_role(port) == PD_ROLE_SINK)
-		return 0;
-
-	if (max_current_claimed & BIT(port))
-		return 3000;
-	else if (typec_get_default_current_limit_rp(port) == TYPEC_RP_1A5)
-		return 1500;
-	else
-		return 500;
-}
diff --git a/common/usbc/usb_pd_host.c b/common/usbc/usb_pd_host.c
deleted file mode 100644
index 4d0fadeec3..0000000000
--- a/common/usbc/usb_pd_host.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Host commands for TCPMv2 USB PD module
- */
-
-#include <string.h>
-
-#include "console.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Retrieve all discovery results for the given port and transmit type */
-static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_typec_discovery *p = args->params;
-	struct ec_response_typec_discovery *r = args->response;
-	const struct pd_discovery *disc;
-	enum tcpci_msg_type type;
-
-	/* Confirm the number of HC VDOs matches our stored VDOs */
-	BUILD_ASSERT(sizeof(r->discovery_vdo) == sizeof(union disc_ident_ack));
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (p->partner_type > TYPEC_PARTNER_SOP_PRIME)
-		return EC_RES_INVALID_PARAM;
-
-	type = p->partner_type == TYPEC_PARTNER_SOP ?
-		TCPCI_MSG_SOP : TCPCI_MSG_SOP_PRIME;
-
-	/*
-	 * Clear out access mask so we can track if tasks have touched data
-	 * since read started.
-	 */
-	pd_discovery_access_clear(p->port, type);
-
-	disc = pd_get_am_discovery_and_notify_access(p->port, type);
-
-	/* Initialize return size to that of discovery with no SVIDs */
-	args->response_size = sizeof(*r);
-
-	if (pd_get_identity_discovery(p->port, type) == PD_DISC_COMPLETE) {
-		r->identity_count = disc->identity_cnt;
-		memcpy(r->discovery_vdo,
-		       pd_get_identity_response(p->port, type)->raw_value,
-		       sizeof(r->discovery_vdo));
-	} else {
-		r->identity_count = 0;
-		return EC_RES_SUCCESS;
-	}
-
-	if (pd_get_modes_discovery(p->port, type) == PD_DISC_COMPLETE) {
-		int svid_i;
-		int max_resp_svids = (args->response_max - args->response_size)/
-				      sizeof(struct svid_mode_info);
-
-		if (disc->svid_cnt > max_resp_svids) {
-			CPRINTS("Warn: SVIDS exceeded HC response");
-			r->svid_count = max_resp_svids;
-		} else {
-			r->svid_count = disc->svid_cnt;
-		}
-
-		for (svid_i = 0; svid_i < r->svid_count; svid_i++) {
-			r->svids[svid_i].svid = disc->svids[svid_i].svid;
-			r->svids[svid_i].mode_count =
-						disc->svids[svid_i].mode_cnt;
-			memcpy(r->svids[svid_i].mode_vdo,
-			       disc->svids[svid_i].mode_vdo,
-			       sizeof(r->svids[svid_i].mode_vdo));
-			args->response_size += sizeof(struct svid_mode_info);
-		}
-	} else {
-		r->svid_count = 0;
-	}
-
-	/*
-	 * Verify that another task did not access this data during the duration
-	 * of the copy.  If the data was accessed, return BUSY so the AP will
-	 * try retrieving again and get the updated data.
-	 */
-	if (!pd_discovery_access_validate(p->port, type)) {
-		CPRINTS("[C%d] %s returns EC_RES_BUSY!!\n", p->port, __func__);
-		return EC_RES_BUSY;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY,
-		     hc_typec_discovery,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_typec_control *p = args->params;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	switch (p->command) {
-	case TYPEC_CONTROL_COMMAND_EXIT_MODES:
-		pd_dpm_request(p->port, DPM_REQUEST_EXIT_MODES);
-		break;
-	case TYPEC_CONTROL_COMMAND_CLEAR_EVENTS:
-		pd_clear_events(p->port, p->clear_events_mask);
-		break;
-	case TYPEC_CONTROL_COMMAND_ENTER_MODE:
-		return pd_request_enter_mode(p->port, p->mode_to_enter);
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_CONTROL, hc_typec_control, EC_VER_MASK(0));
-
-static enum ec_status hc_typec_status(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_typec_status *p = args->params;
-	struct ec_response_typec_status *r = args->response;
-	const char *tc_state_name;
-
-	if (p->port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (args->response_max < sizeof(*r))
-		return EC_RES_RESPONSE_TOO_BIG;
-
-	args->response_size = sizeof(*r);
-
-	r->pd_enabled = pd_comm_is_enabled(p->port);
-	r->dev_connected = pd_is_connected(p->port);
-	r->sop_connected = pd_capable(p->port);
-
-	r->power_role = pd_get_power_role(p->port);
-	r->data_role = pd_get_data_role(p->port);
-	r->vconn_role = pd_get_vconn_state(p->port) ? PD_ROLE_VCONN_SRC :
-						      PD_ROLE_VCONN_OFF;
-	r->polarity = pd_get_polarity(p->port);
-	r->cc_state = pd_get_task_cc_state(p->port);
-	r->dp_pin = get_dp_pin_mode(p->port);
-	r->mux_state = usb_mux_get(p->port);
-
-	tc_state_name = pd_get_task_state_name(p->port);
-	strzcpy(r->tc_state, tc_state_name, sizeof(r->tc_state));
-
-	r->events = pd_get_events(p->port);
-
-	r->sop_revision = r->sop_connected ?
-		PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port, TCPCI_MSG_SOP)) : 0;
-	r->sop_prime_revision =
-		pd_get_identity_discovery(p->port, TCPCI_MSG_SOP_PRIME) ==
-		PD_DISC_COMPLETE ?
-		PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port,
-					TCPCI_MSG_SOP_PRIME))
-		: 0;
-
-	r->source_cap_count = pd_get_src_cap_cnt(p->port);
-	memcpy(r->source_cap_pdos, pd_get_src_caps(p->port),
-	       r->source_cap_count * sizeof(uint32_t));
-
-	r->sink_cap_count = pd_get_snk_cap_cnt(p->port);
-	memcpy(r->sink_cap_pdos, pd_get_snk_caps(p->port),
-	       r->sink_cap_count * sizeof(uint32_t));
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_STATUS, hc_typec_status, EC_VER_MASK(0));
diff --git a/common/usbc/usb_pd_timer.c b/common/usbc/usb_pd_timer.c
deleted file mode 100644
index 67a574904f..0000000000
--- a/common/usbc/usb_pd_timer.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "assert.h"
-#include "common.h"
-#include "console.h"
-#include "limits.h"
-#include "system.h"
-#include "usb_pd_timer.h"
-#include "usb_tc_sm.h"
-
-#define MAX_PD_PORTS	CONFIG_USB_PD_PORT_MAX_COUNT
-#define MAX_PD_TIMERS	PD_TIMER_COUNT
-#define PD_TIMERS_ALL_MASK ((uint32_t)(((uint64_t)1 << PD_TIMER_COUNT) - 1))
-
-#define MAX_EXPIRE	(0x7FFFFFFF)
-#define NO_TIMEOUT	(-1)
-#define EXPIRE_NOW	(0)
-
-#define PD_SET_ACTIVE(p, m)	atomic_or(&timer_active[p], (m))
-#define PD_CLR_ACTIVE(p, m)	atomic_clear_bits(&timer_active[p], (m))
-#define PD_CHK_ACTIVE(p, m)	(timer_active[p] & (m))
-
-#define PD_SET_DISABLED(p, m)	atomic_or(&timer_disabled[p], (m))
-#define PD_CLR_DISABLED(p, m)	atomic_clear_bits(&timer_disabled[p], (m))
-#define PD_CHK_DISABLED(p, m)	(timer_disabled[p] & (m))
-
-static uint32_t timer_active[MAX_PD_PORTS];
-static uint32_t timer_disabled[MAX_PD_PORTS];
-static uint64_t timer_expires[MAX_PD_PORTS][MAX_PD_TIMERS];
-
-/*
- * CONFIG_CMD_PD_TIMER debug variables
- */
-static int count[MAX_PD_PORTS];
-static int max_count[MAX_PD_PORTS];
-
-__maybe_unused static __const_data const char * const pd_timer_names[] = {
-	[PE_TIMER_BIST_CONT_MODE]	= "PE-BIST_CONT_MODE",
-	[PE_TIMER_CHUNKING_NOT_SUPPORTED] = "PE-CHUNKING_NOT_SUPPORTED",
-	[PE_TIMER_DISCOVER_IDENTITY]	= "PE-DISCOVER_IDENTITY",
-	[PE_TIMER_NO_RESPONSE]		= "PE-NO_RESPONSE",
-	[PE_TIMER_PR_SWAP_WAIT]		= "PE-PR_SWAP_WAIT",
-	[PE_TIMER_PS_HARD_RESET]	= "PE-PS_HARD_RESET",
-	[PE_TIMER_PS_SOURCE]		= "PE-PS_SOURCE",
-	[PE_TIMER_PS_TRANSITION]	= "PE-PS_TRANSITION",
-	[PE_TIMER_SENDER_RESPONSE]	= "PE-SENDER_RESPONSE",
-	[PE_TIMER_SINK_REQUEST]		= "PE-SINK_REQUEST",
-	[PE_TIMER_SOURCE_CAP]		= "PE-SOURCE_CAP",
-	[PE_TIMER_SRC_TRANSITION]	= "PE-SRC_TRANSITION",
-	[PE_TIMER_SWAP_SOURCE_START]	= "PE-SWAP_SOURCE_START",
-	[PE_TIMER_TIMEOUT]		= "PE-TIMEOUT",
-	[PE_TIMER_VCONN_ON]		= "PE-VCONN_ON",
-	[PE_TIMER_VDM_RESPONSE]		= "PE-VDM_RESPONSE",
-	[PE_TIMER_WAIT_AND_ADD_JITTER]	= "PE-WAIT_AND_ADD_JITTER",
-
-	[PR_TIMER_CHUNK_SENDER_REQUEST]	= "PR-CHUNK_SENDER_REQUEST",
-	[PR_TIMER_CHUNK_SENDER_RESPONSE] = "PR-CHUNK_SENDER_RESPONSE",
-	[PR_TIMER_HARD_RESET_COMPLETE]	= "PR-HARD_RESET_COMPLETE",
-	[PR_TIMER_SINK_TX]		= "PR-SINK_TX",
-	[PR_TIMER_TCPC_TX_TIMEOUT]	= "PR-TCPC_TX_TIMEOUT",
-
-	[TC_TIMER_CC_DEBOUNCE]		= "TC-CC_DEBOUNCE",
-	[TC_TIMER_LOW_POWER_EXIT_TIME]	= "TC-LOW_POWER_EXIT_TIME",
-	[TC_TIMER_LOW_POWER_TIME]	= "TC-LOW_POWER_TIME",
-	[TC_TIMER_NEXT_ROLE_SWAP]	= "TC-NEXT_ROLE_SWAP",
-	[TC_TIMER_PD_DEBOUNCE]		= "TC-PD_DEBOUNCE",
-	[TC_TIMER_TIMEOUT]		= "TC-TIMEOUT",
-	[TC_TIMER_TRY_WAIT_DEBOUNCE]	= "TC-TRY_WAIT_DEBOUNCE",
-	[TC_TIMER_VBUS_DEBOUNCE]	= "TC-VBUS_DEBOUNCE",
-};
-
-/*****************************************************************************
- * PD_TIMER private functions
- *
- * The view of timers to the outside world is enabled and disabled. Internally
- * timers that are enabled are in the active and inactive states. An active
- * timer has a valid timeout value that gets checked for expiration and can
- * adjust the task wakeup time.  An inactive timer is assumed to have expired
- * already and will always return that it is still expired.  This timer state
- * will not adjust the task scheduling timeout value.
- */
-static void pd_timer_inactive(int port, enum pd_task_timer timer)
-{
-	uint32_t mask = 1 << timer;
-
-	if (PD_CHK_ACTIVE(port, mask)) {
-		PD_CLR_ACTIVE(port, mask);
-
-		if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
-			count[port]--;
-	}
-	PD_CLR_DISABLED(port, mask);
-}
-
-static bool pd_timer_is_active(int port, enum pd_task_timer timer)
-{
-	uint32_t mask = 1 << timer;
-
-	return PD_CHK_ACTIVE(port, mask);
-}
-
-static bool pd_timer_is_inactive(int port, enum pd_task_timer timer)
-{
-	uint32_t mask = 1 << timer;
-
-	return !PD_CHK_ACTIVE(port, mask) && !PD_CHK_DISABLED(port, mask);
-}
-
-/*****************************************************************************
- * PD_TIMER public functions
- */
-void pd_timer_init(int port)
-{
-	if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
-		count[port] = 0;
-
-	PD_CLR_ACTIVE(port, PD_TIMERS_ALL_MASK);
-	PD_SET_DISABLED(port, PD_TIMERS_ALL_MASK);
-}
-
-void pd_timer_enable(int port, enum pd_task_timer timer, uint32_t expires_us)
-{
-	uint32_t mask = 1 << timer;
-
-	if (!PD_CHK_ACTIVE(port, mask)) {
-		PD_SET_ACTIVE(port, mask);
-
-		if (IS_ENABLED(CONFIG_CMD_PD_TIMER)) {
-			count[port]++;
-			if (count[port] > max_count[port])
-				max_count[port] = count[port];
-		}
-	}
-	PD_CLR_DISABLED(port, mask);
-	timer_expires[port][timer] = get_time().val + expires_us;
-}
-
-void pd_timer_disable(int port, enum pd_task_timer timer)
-{
-	uint32_t mask = 1 << timer;
-
-	if (PD_CHK_ACTIVE(port, mask)) {
-		PD_CLR_ACTIVE(port, mask);
-
-		if (IS_ENABLED(CONFIG_CMD_PD_TIMER))
-			count[port]--;
-	}
-	PD_SET_DISABLED(port, mask);
-}
-
-void pd_timer_disable_range(int port, enum pd_timer_range range)
-{
-	int start, end;
-	enum pd_task_timer timer;
-
-	switch (range) {
-	case PE_TIMER_RANGE:
-		start	= PE_TIMER_START;
-		end	= PE_TIMER_END;
-		break;
-	case PR_TIMER_RANGE:
-		start	= PR_TIMER_START;
-		end	= PR_TIMER_END;
-		break;
-	case TC_TIMER_RANGE:
-		start	= TC_TIMER_START;
-		end	= TC_TIMER_END;
-		break;
-	default:
-		return;
-	}
-
-	for (timer = start; timer <= end; ++timer)
-		pd_timer_disable(port, timer);
-}
-
-bool pd_timer_is_disabled(int port, enum pd_task_timer timer)
-{
-	uint32_t mask = 1 << timer;
-
-	return PD_CHK_DISABLED(port, mask);
-}
-
-bool pd_timer_is_expired(int port, enum pd_task_timer timer)
-{
-	if (pd_timer_is_active(port, timer)) {
-		if (get_time().val >= timer_expires[port][timer]) {
-			pd_timer_inactive(port, timer);
-			return true;
-		}
-		return false;
-	}
-	return pd_timer_is_inactive(port, timer);
-}
-
-void pd_timer_manage_expired(int port)
-{
-	int timer;
-
-	if (timer_active[port])
-		for (timer = 0; timer < MAX_PD_TIMERS; ++timer)
-			if (pd_timer_is_active(port, timer) &&
-			    pd_timer_is_expired(port, timer))
-				pd_timer_inactive(port, timer);
-}
-
-int pd_timer_next_expiration(int port)
-{
-	int timer;
-	int ret_value = MAX_EXPIRE;
-	uint64_t now = get_time().val;
-
-	for (timer = 0; timer < MAX_PD_TIMERS; ++timer) {
-		/* Only use active timers for the next expired value */
-		if (pd_timer_is_active(port, timer)) {
-			int delta;
-			uint64_t t_value = timer_expires[port][timer];
-
-			if (t_value <= now) {
-				ret_value = EXPIRE_NOW;
-				break;
-			}
-
-			delta = t_value - now;
-			if (ret_value > delta)
-				ret_value = delta;
-		}
-	}
-
-	if (ret_value == MAX_EXPIRE)
-		ret_value = NO_TIMEOUT;
-
-	return ret_value;
-}
-
-#ifdef CONFIG_CMD_PD_TIMER
-void pd_timer_dump(int port)
-{
-	int timer;
-	uint64_t now = get_time().val;
-
-	ccprints("Timers(%d): cur=%d max=%d",
-		port, count[port], max_count[port]);
-
-	for (timer = 0; timer < MAX_PD_TIMERS; ++timer) {
-		if (pd_timer_is_disabled(port, timer)) {
-			continue;
-		} else if (pd_timer_is_active(port, timer)) {
-			uint32_t delta = 0;
-
-			if (now < timer_expires[port][timer])
-				delta = timer_expires[port][timer] - now;
-
-			ccprints("[%2d] Active:   %s (%d%s)",
-				timer, pd_timer_names[timer], (uint32_t)delta,
-				tc_event_loop_is_paused(port)
-					? "-PAUSED"
-					: "");
-		} else {
-			ccprints("[%2d] Inactive: %s",
-				timer, pd_timer_names[timer]);
-		}
-	}
-}
-#endif /* CONFIG_CMD_PD_TIMER */
diff --git a/common/usbc/usb_pe_ctvpd_sm.c b/common/usbc/usb_pe_ctvpd_sm.c
deleted file mode 100644
index 346a57a461..0000000000
--- a/common/usbc/usb_pe_ctvpd_sm.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "task.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_pd_tcpm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
-#include "usb_sm.h"
-
-/* USB Policy Engine Charge-Through VCONN Powered Device module */
-
-/* Policy Engine Flags */
-#define PE_FLAGS_MSG_RECEIVED BIT(0)
-
-/**
- * This is the PE Port object that contains information needed to
- * implement a VCONN and Charge-Through VCONN Powered Device.
- */
-static struct policy_engine {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* port flags, see PE_FLAGS_* */
-	uint32_t flags;
-} pe[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* List of all policy-engine-level states */
-enum usb_pe_state {
-	PE_REQUEST,
-};
-
-/* Forward declare the full list of states. This is indexed by usb_pe_states */
-static const struct usb_state pe_states[];
-
-static void set_state_pe(const int port, enum usb_pe_state new_state)
-{
-	set_state(port, &pe[port].ctx, &pe_states[new_state]);
-}
-
-static void pe_init(int port)
-{
-	const struct sm_ctx cleared = {};
-
-	pe[port].flags = 0;
-	pe[port].ctx = cleared;
-	set_state_pe(port, PE_REQUEST);
-}
-
-bool pe_in_frs_mode(int port)
-{
-	/* Will never be in FRS mode */
-	return false;
-}
-
-bool pe_in_local_ams(int port)
-{
-	/* We never start a local AMS */
-	return false;
-}
-
-void pe_run(int port, int evt, int en)
-{
-	static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-	switch (local_state[port]) {
-	case SM_PAUSED:
-		if (!en)
-			break;
-		/* fall through */
-	case SM_INIT:
-		pe_init(port);
-		local_state[port] = SM_RUN;
-		/* fall through */
-	case SM_RUN:
-		if (en)
-			run_state(port, &pe[port].ctx);
-		else
-			local_state[port] = SM_PAUSED;
-		break;
-	}
-}
-
-void pe_message_received(int port)
-{
-	pe[port].flags |= PE_FLAGS_MSG_RECEIVED;
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-/**
- * NOTE:
- *	The Charge-Through Vconn Powered Device's Policy Engine is very
- *	simple and no implementation is needed for the following functions
- *	that might be called by the Protocol Layer.
- */
-
-void pe_hard_reset_sent(int port)
-{
-	/* No implementation needed by this policy engine */
-}
-
-void pe_got_hard_reset(int port)
-{
-	/* No implementation needed by this policy engine */
-}
-
-void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
-{
-	/* No implementation needed by this policy engine */
-}
-
-void pe_report_discard(int port)
-{
-	/* No implementation needed by this policy engine */
-}
-
-void pe_got_soft_reset(int port)
-{
-	/* No implementation needed by this policy engine */
-}
-
-void pe_message_sent(int port)
-{
-	/* No implementation needed by this policy engine */
-}
-
-static void pe_request_run(const int port)
-{
-	uint32_t *payload = (uint32_t *)tx_emsg[port].buf;
-	uint32_t header = rx_emsg[port].header;
-	uint32_t vdo = *(uint32_t *)rx_emsg[port].buf;
-
-	if (pe[port].flags & PE_FLAGS_MSG_RECEIVED) {
-		pe[port].flags &= ~PE_FLAGS_MSG_RECEIVED;
-
-		/*
-		 * Only support Structured VDM Discovery
-		 * Identity message
-		 */
-
-		if (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF)
-			return;
-
-		if (PD_HEADER_CNT(header) == 0)
-			return;
-
-		if (!PD_VDO_SVDM(vdo))
-			return;
-
-		if (PD_VDO_CMD(vdo) != CMD_DISCOVER_IDENT)
-			return;
-
-#ifdef CONFIG_USB_CTVPD
-		/*
-		 * We have a valid DISCOVER IDENTITY message.
-		 * Attempt to reset support timer
-		 */
-		tc_reset_support_timer(port);
-#endif
-		/* Prepare to send ACK */
-
-		/* VDM Header */
-		payload[0] = VDO(
-			USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-
-		/* ID Header VDO */
-		payload[1] = VDO_IDH(
-			0, /* Not a USB Host */
-			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
-			USB_VID_GOOGLE);
-
-		/* Cert State VDO */
-		payload[2] = 0;
-
-		/* Product VDO */
-		payload[3] = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
-
-		/* VPD VDO */
-		payload[4] = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-							VPD_VBUS_IMPEDANCE)
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-							VPD_GND_IMPEDANCE)
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						     : VPD_CTS_NOT_SUPPORTED);
-
-		/* 20 bytes, 5 data objects */
-		tx_emsg[port].len = 20;
-
-		/* Set to highest revision supported by both ports. */
-		prl_set_rev(port, TCPCI_MSG_SOP_PRIME,
-					(PD_HEADER_REV(header) > PD_REV30) ?
-					PD_REV30 : PD_HEADER_REV(header));
-		/* Send the ACK */
-		prl_send_data_msg(port, TCPCI_MSG_SOP_PRIME,
-					PD_DATA_VENDOR_DEF);
-	}
-}
-
-/* All policy-engine-level states. */
-static const struct usb_state pe_states[] = {
-	[PE_REQUEST] = {
-		.run    = pe_request_run,
-	},
-};
-
-#ifdef TEST_BUILD
-const struct test_sm_data test_pe_sm_data[] = {
-	{
-		.base = pe_states,
-		.size = ARRAY_SIZE(pe_states),
-	},
-};
-const int test_pe_sm_data_size = ARRAY_SIZE(test_pe_sm_data);
-#endif
diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c
deleted file mode 100644
index 096f689b0a..0000000000
--- a/common/usbc/usb_pe_drp_sm.c
+++ /dev/null
@@ -1,7486 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "dps.h"
-#include "driver/tcpm/tcpm.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "stdbool.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "util.h"
-#include "usb_common.h"
-#include "usb_dp_alt_mode.h"
-#include "usb_mode.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_policy.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_timer.h"
-#include "usb_pe_sm.h"
-#include "usb_tbt_alt_mode.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
-#include "usb_sm.h"
-#include "usbc_ppc.h"
-
-/*
- * USB Policy Engine Sink / Source module
- *
- * Based on Revision 3.0, Version 1.2 of
- * the USB Power Delivery Specification.
- */
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTF(format, ## args); \
-	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTS(format, ## args); \
-	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
-
-#define PE_SET_FLAG(port, flag) atomic_or(&pe[port].flags, (flag))
-#define PE_CLR_FLAG(port, flag) atomic_clear_bits(&pe[port].flags, (flag))
-#define PE_CHK_FLAG(port, flag) (pe[port].flags & (flag))
-
-/*
- * These macros SET, CLEAR, and CHECK, a DPM (Device Policy Manager)
- * Request. The Requests are listed in usb_pe_sm.h.
- */
-#define PE_SET_DPM_REQUEST(port, req) atomic_or(&pe[port].dpm_request, (req))
-#define PE_CLR_DPM_REQUEST(port, req) \
-	atomic_clear_bits(&pe[port].dpm_request, (req))
-#define PE_CHK_DPM_REQUEST(port, req) (pe[port].dpm_request & (req))
-
-/*
- * Policy Engine Layer Flags
- * These are reproduced in test/usb_pe.h. If they change here, they must change
- * there.
- */
-
-/* At least one successful PD communication packet received from port partner */
-#define PE_FLAGS_PD_CONNECTION               BIT(0)
-/* Accept message received from port partner */
-#define PE_FLAGS_ACCEPT                      BIT(1)
-/* Power Supply Ready message received from port partner */
-#define PE_FLAGS_PS_READY                    BIT(2)
-/* Protocol Error was determined based on error recovery current state */
-#define PE_FLAGS_PROTOCOL_ERROR              BIT(3)
-/* Set if we are in Modal Operation */
-#define PE_FLAGS_MODAL_OPERATION             BIT(4)
-/* A message we requested to be sent has been transmitted */
-#define PE_FLAGS_TX_COMPLETE                 BIT(5)
-/* A message sent by a port partner has been received */
-#define PE_FLAGS_MSG_RECEIVED                BIT(6)
-/* A hard reset has been requested but has not been sent, not currently used */
-#define PE_FLAGS_HARD_RESET_PENDING          BIT(7)
-/* Port partner sent a Wait message. Wait before we resend our message */
-#define PE_FLAGS_WAIT                        BIT(8)
-/* An explicit contract is in place with our port partner */
-#define PE_FLAGS_EXPLICIT_CONTRACT           BIT(9)
-/* Waiting for Sink Capabailities timed out.  Used for retry error handling */
-#define PE_FLAGS_SNK_WAIT_CAP_TIMEOUT        BIT(10)
-/* Power Supply voltage/current transition timed out */
-#define PE_FLAGS_PS_TRANSITION_TIMEOUT       BIT(11)
-/* Flag to note current Atomic Message Sequence is interruptible */
-#define PE_FLAGS_INTERRUPTIBLE_AMS           BIT(12)
-/* Flag to note Power Supply reset has completed */
-#define PE_FLAGS_PS_RESET_COMPLETE           BIT(13)
-/* VCONN swap operation has completed */
-#define PE_FLAGS_VCONN_SWAP_COMPLETE         BIT(14)
-/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
-#define PE_FLAGS_VDM_SETUP_DONE              BIT(15)
-/* Flag to note PR Swap just completed for Startup entry */
-#define PE_FLAGS_PR_SWAP_COMPLETE	     BIT(16)
-/* Flag to note Port Discovery port partner replied with BUSY */
-#define PE_FLAGS_VDM_REQUEST_BUSY            BIT(17)
-/* Flag to note Port Discovery port partner replied with NAK */
-#define PE_FLAGS_VDM_REQUEST_NAKED           BIT(18)
-/* Flag to note FRS/PRS context in shared state machine path */
-#define PE_FLAGS_FAST_ROLE_SWAP_PATH         BIT(19)
-/* Flag to note if FRS listening is enabled */
-#define PE_FLAGS_FAST_ROLE_SWAP_ENABLED      BIT(20)
-/* Flag to note TCPC passed on FRS signal from port partner */
-#define PE_FLAGS_FAST_ROLE_SWAP_SIGNALED     BIT(21)
-/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */
-#define PE_FLAGS_DR_SWAP_TO_DFP              BIT(22)
-/*
- * TODO: POLICY decision
- * Flag to trigger a message resend after receiving a WAIT from port partner
- */
-#define PE_FLAGS_WAITING_PR_SWAP             BIT(23)
-/* FLAG is set when an AMS is initiated locally. ie. AP requested a PR_SWAP */
-#define PE_FLAGS_LOCALLY_INITIATED_AMS       BIT(24)
-/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY */
-#define PE_FLAGS_FIRST_MSG                   BIT(25)
-/* Flag to continue a VDM request if it was interrupted */
-#define PE_FLAGS_VDM_REQUEST_CONTINUE        BIT(26)
-/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */
-#define PE_FLAGS_VCONN_SWAP_TO_ON	     BIT(27)
-/* FLAG to track that VDM request to port partner timed out */
-#define PE_FLAGS_VDM_REQUEST_TIMEOUT	     BIT(28)
-/* FLAG to note message was discarded due to incoming message */
-#define PE_FLAGS_MSG_DISCARDED		     BIT(29)
-/* FLAG to note that hard reset can't be performed due to battery low */
-#define PE_FLAGS_SNK_WAITING_BATT	     BIT(30)
-
-/* Message flags which should not persist on returning to ready state */
-#define PE_FLAGS_READY_CLR		     (PE_FLAGS_LOCALLY_INITIATED_AMS \
-					     | PE_FLAGS_MSG_DISCARDED \
-					     | PE_FLAGS_VDM_REQUEST_TIMEOUT \
-					     | PE_FLAGS_INTERRUPTIBLE_AMS)
-
-/*
- * Combination to check whether a reply to a message was received.  Our message
- * should have sent (i.e. not been discarded) and a partner message is ready to
- * process.
- *
- * When chunking is disabled (ex. for PD 2.0), these flags will set
- * on the same run cycle.  With chunking, received message will take an
- * additional cycle to be flagged.
- */
-#define PE_CHK_REPLY(port)	(PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \
-				 !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED))
-
-/* 6.7.3 Hard Reset Counter */
-#define N_HARD_RESET_COUNT 2
-
-/* 6.7.4 Capabilities Counter */
-#define N_CAPS_COUNT 25
-
-/* 6.7.5 Discover Identity Counter */
-/*
- * NOTE: The Protocol Layer tries to send a message 3 time before giving up,
- * so a Discover Identity SOP' message will be sent 3*6 = 18 times (slightly
- * less than spec maximum of 20).  This counter applies only to cable plug
- * discovery.
- */
-#define N_DISCOVER_IDENTITY_COUNT 6
-
-/*
- * It is permitted to send SOP' Discover Identity messages before a PD contract
- * is in place. However, this is only beneficial if the cable powers up quickly
- * solely from VCONN. Limit the number of retries without a contract to
- * ensure we attempt some cable discovery after a contract is in place.
- */
-#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT	2
-
-/*
- * Once this limit of SOP' Discover Identity messages has been set, downgrade
- * to PD 2.0 in case the cable is non-compliant about GoodCRC-ing higher
- * revisions.  This limit should be higher than the precontract limit.
- */
-#define N_DISCOVER_IDENTITY_PD3_0_LIMIT		4
-
-/*
- * tDiscoverIdentity is only defined while an explicit contract is in place, so
- * extend the interval between retries pre-contract.
- */
-#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT	(200*MSEC)
-
-/*
- * Only VCONN source can communicate with the cable plug. Hence, try VCONN swap
- * 3 times before giving up.
- *
- * Note: This is not a part of power delivery specification
- */
-#define N_VCONN_SWAP_COUNT 3
-
-/*
- * Counter to track how many times to attempt SRC to SNK PR swaps before giving
- * up.
- *
- * Note: This is not a part of power delivery specification
- */
-#define N_SNK_SRC_PR_SWAP_COUNT 5
-
-/*
- * ChromeOS policy:
- *   For PD2.0, We must be DFP before sending Discover Identity message
- *   to the port partner. Attempt to DR SWAP from UFP to DFP
- *   N_DR_SWAP_ATTEMPT_COUNT times before giving up on sending a
- *   Discover Identity message.
- */
-#define N_DR_SWAP_ATTEMPT_COUNT 5
-
-#define TIMER_DISABLED 0xffffffffffffffff /* Unreachable time in future */
-
-/*
- * The time that we allow the port partner to send any messages after an
- * explicit contract is established.  200ms was chosen somewhat arbitrarily as
- * it should be long enough for sources to decide to send a message if they were
- * going to, but not so long that a "low power charger connected" notification
- * would be shown in the chrome OS UI. Setting t0o large a delay can cause
- * problems if the PD discovery time exceeds 1s (tAMETimeout)
- */
-#define SRC_SNK_READY_HOLD_OFF_US (200 * MSEC)
-
-/*
- * Function pointer to a Structured Vendor Defined Message (SVDM) response
- * function defined in the board's usb_pd_policy.c file.
- */
-typedef int (*svdm_rsp_func)(int port, uint32_t *payload);
-
-/* List of all Policy Engine level states */
-enum usb_pe_state {
-	/* Super States */
-	PE_PRS_FRS_SHARED,
-	PE_VDM_SEND_REQUEST,
-
-	/* Normal States */
-	PE_SRC_STARTUP,
-	PE_SRC_DISCOVERY,
-	PE_SRC_SEND_CAPABILITIES,
-	PE_SRC_NEGOTIATE_CAPABILITY,
-	PE_SRC_TRANSITION_SUPPLY,
-	PE_SRC_READY,
-	PE_SRC_DISABLED,
-	PE_SRC_CAPABILITY_RESPONSE,
-	PE_SRC_HARD_RESET,
-	PE_SRC_HARD_RESET_RECEIVED,
-	PE_SRC_TRANSITION_TO_DEFAULT,
-	PE_SNK_STARTUP,
-	PE_SNK_DISCOVERY,
-	PE_SNK_WAIT_FOR_CAPABILITIES,
-	PE_SNK_EVALUATE_CAPABILITY,
-	PE_SNK_SELECT_CAPABILITY,
-	PE_SNK_READY,
-	PE_SNK_HARD_RESET,
-	PE_SNK_TRANSITION_TO_DEFAULT,
-	PE_SNK_GIVE_SINK_CAP,
-	PE_SNK_GET_SOURCE_CAP,
-	PE_SNK_TRANSITION_SINK,
-	PE_SEND_SOFT_RESET,
-	PE_SOFT_RESET,
-	PE_SEND_NOT_SUPPORTED,
-	PE_SRC_PING,
-	PE_DRS_EVALUATE_SWAP,
-	PE_DRS_CHANGE,
-	PE_DRS_SEND_SWAP,
-	PE_PRS_SRC_SNK_EVALUATE_SWAP,
-	PE_PRS_SRC_SNK_TRANSITION_TO_OFF,
-	PE_PRS_SRC_SNK_ASSERT_RD,
-	PE_PRS_SRC_SNK_WAIT_SOURCE_ON,
-	PE_PRS_SRC_SNK_SEND_SWAP,
-	PE_PRS_SNK_SRC_EVALUATE_SWAP,
-	PE_PRS_SNK_SRC_TRANSITION_TO_OFF,
-	PE_PRS_SNK_SRC_ASSERT_RP,
-	PE_PRS_SNK_SRC_SOURCE_ON,
-	PE_PRS_SNK_SRC_SEND_SWAP,
-	PE_VCS_EVALUATE_SWAP,
-	PE_VCS_SEND_SWAP,
-	PE_VCS_WAIT_FOR_VCONN_SWAP,
-	PE_VCS_TURN_ON_VCONN_SWAP,
-	PE_VCS_TURN_OFF_VCONN_SWAP,
-	PE_VCS_SEND_PS_RDY_SWAP,
-	PE_VCS_CBL_SEND_SOFT_RESET,
-	PE_VDM_IDENTITY_REQUEST_CBL,
-	PE_INIT_PORT_VDM_IDENTITY_REQUEST,
-	PE_INIT_VDM_SVIDS_REQUEST,
-	PE_INIT_VDM_MODES_REQUEST,
-	PE_VDM_REQUEST_DPM,
-	PE_VDM_RESPONSE,
-	PE_HANDLE_CUSTOM_VDM_REQUEST,
-	PE_WAIT_FOR_ERROR_RECOVERY,
-	PE_BIST_TX,
-	PE_DEU_SEND_ENTER_USB,
-	PE_DR_GET_SINK_CAP,
-	PE_DR_SNK_GIVE_SOURCE_CAP,
-	PE_DR_SRC_GET_SOURCE_CAP,
-
-	/* PD3.0 only states below here*/
-	PE_FRS_SNK_SRC_START_AMS,
-	PE_GIVE_BATTERY_CAP,
-	PE_GIVE_BATTERY_STATUS,
-	PE_SEND_ALERT,
-	PE_SRC_CHUNK_RECEIVED,
-	PE_SNK_CHUNK_RECEIVED,
-	PE_VCS_FORCE_VCONN,
-};
-
-/*
- * The result of a previously sent DPM request; used by PE_VDM_SEND_REQUEST to
- * indicate to child states when they need to handle a response.
- */
-enum vdm_response_result {
-	/* The parent state is still waiting for a response. */
-	VDM_RESULT_WAITING,
-	/*
-	 * The parent state parsed a message, but there is nothing for the child
-	 * to handle, e.g. BUSY.
-	 */
-	VDM_RESULT_NO_ACTION,
-	/* The parent state processed an ACK response. */
-	VDM_RESULT_ACK,
-	/*
-	 * The parent state processed a NAK-like response (NAK, Not Supported,
-	 * or response timeout.
-	 */
-	VDM_RESULT_NAK,
-};
-
-/* Forward declare the full list of states. This is indexed by usb_pe_state */
-static const struct usb_state pe_states[];
-
-/*
- * We will use DEBUG LABELS if we will be able to print (COMMON RUNTIME)
- * and either CONFIG_USB_PD_DEBUG_LEVEL is not defined (no override) or
- * we are overriding and the level is not DISABLED.
- *
- * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
- * then the DEBUG LABELS will be removed from the build.
- */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
-#define USB_PD_DEBUG_LABELS
-#endif
-
-/* List of human readable state names for console debugging */
-__maybe_unused static __const_data const char * const pe_state_names[] = {
-	/* Super States */
-#ifdef CONFIG_USB_PD_REV30
-	[PE_PRS_FRS_SHARED] = "SS:PE_PRS_FRS_SHARED",
-#endif
-	[PE_VDM_SEND_REQUEST] = "SS:PE_VDM_Send_Request",
-
-	/* Normal States */
-	[PE_SRC_STARTUP] = "PE_SRC_Startup",
-	[PE_SRC_DISCOVERY] = "PE_SRC_Discovery",
-	[PE_SRC_SEND_CAPABILITIES] = "PE_SRC_Send_Capabilities",
-	[PE_SRC_NEGOTIATE_CAPABILITY] = "PE_SRC_Negotiate_Capability",
-	[PE_SRC_TRANSITION_SUPPLY] = "PE_SRC_Transition_Supply",
-	[PE_SRC_READY] = "PE_SRC_Ready",
-	[PE_SRC_DISABLED] = "PE_SRC_Disabled",
-	[PE_SRC_CAPABILITY_RESPONSE] = "PE_SRC_Capability_Response",
-	[PE_SRC_HARD_RESET] = "PE_SRC_Hard_Reset",
-	[PE_SRC_HARD_RESET_RECEIVED] = "PE_SRC_Hard_Reset_Received",
-	[PE_SRC_TRANSITION_TO_DEFAULT] = "PE_SRC_Transition_to_default",
-	[PE_SNK_STARTUP] = "PE_SNK_Startup",
-	[PE_SNK_DISCOVERY] = "PE_SNK_Discovery",
-	[PE_SNK_WAIT_FOR_CAPABILITIES] = "PE_SNK_Wait_for_Capabilities",
-	[PE_SNK_EVALUATE_CAPABILITY] = "PE_SNK_Evaluate_Capability",
-	[PE_SNK_SELECT_CAPABILITY] = "PE_SNK_Select_Capability",
-	[PE_SNK_READY] = "PE_SNK_Ready",
-	[PE_SNK_HARD_RESET] = "PE_SNK_Hard_Reset",
-	[PE_SNK_TRANSITION_TO_DEFAULT] = "PE_SNK_Transition_to_default",
-	[PE_SNK_GIVE_SINK_CAP] = "PE_SNK_Give_Sink_Cap",
-	[PE_SNK_GET_SOURCE_CAP] = "PE_SNK_Get_Source_Cap",
-	[PE_SNK_TRANSITION_SINK] = "PE_SNK_Transition_Sink",
-	[PE_SEND_SOFT_RESET] = "PE_Send_Soft_Reset",
-	[PE_SOFT_RESET] = "PE_Soft_Reset",
-	[PE_SEND_NOT_SUPPORTED] = "PE_Send_Not_Supported",
-	[PE_SRC_PING] = "PE_SRC_Ping",
-	[PE_DRS_EVALUATE_SWAP] = "PE_DRS_Evaluate_Swap",
-	[PE_DRS_CHANGE] = "PE_DRS_Change",
-	[PE_DRS_SEND_SWAP] = "PE_DRS_Send_Swap",
-	[PE_PRS_SRC_SNK_EVALUATE_SWAP] = "PE_PRS_SRC_SNK_Evaluate_Swap",
-	[PE_PRS_SRC_SNK_TRANSITION_TO_OFF] = "PE_PRS_SRC_SNK_Transition_To_Off",
-	[PE_PRS_SRC_SNK_ASSERT_RD] = "PE_PRS_SRC_SNK_Assert_Rd",
-	[PE_PRS_SRC_SNK_WAIT_SOURCE_ON] = "PE_PRS_SRC_SNK_Wait_Source_On",
-	[PE_PRS_SRC_SNK_SEND_SWAP] = "PE_PRS_SRC_SNK_Send_Swap",
-	[PE_PRS_SNK_SRC_EVALUATE_SWAP] = "PE_PRS_SNK_SRC_Evaluate_Swap",
-	[PE_PRS_SNK_SRC_TRANSITION_TO_OFF] = "PE_PRS_SNK_SRC_Transition_To_Off",
-	[PE_PRS_SNK_SRC_ASSERT_RP] = "PE_PRS_SNK_SRC_Assert_Rp",
-	[PE_PRS_SNK_SRC_SOURCE_ON] = "PE_PRS_SNK_SRC_Source_On",
-	[PE_PRS_SNK_SRC_SEND_SWAP] = "PE_PRS_SNK_SRC_Send_Swap",
-#ifdef CONFIG_USBC_VCONN
-	[PE_VCS_EVALUATE_SWAP] = "PE_VCS_Evaluate_Swap",
-	[PE_VCS_SEND_SWAP] = "PE_VCS_Send_Swap",
-	[PE_VCS_WAIT_FOR_VCONN_SWAP] = "PE_VCS_Wait_For_Vconn_Swap",
-	[PE_VCS_TURN_ON_VCONN_SWAP] = "PE_VCS_Turn_On_Vconn_Swap",
-	[PE_VCS_TURN_OFF_VCONN_SWAP] = "PE_VCS_Turn_Off_Vconn_Swap",
-	[PE_VCS_SEND_PS_RDY_SWAP] = "PE_VCS_Send_Ps_Rdy_Swap",
-	[PE_VCS_CBL_SEND_SOFT_RESET] = "PE_VCS_CBL_Send_Soft_Reset",
-#endif
-	[PE_VDM_IDENTITY_REQUEST_CBL] = "PE_VDM_Identity_Request_Cbl",
-	[PE_INIT_PORT_VDM_IDENTITY_REQUEST] =
-					   "PE_INIT_PORT_VDM_Identity_Request",
-	[PE_INIT_VDM_SVIDS_REQUEST] = "PE_INIT_VDM_SVIDs_Request",
-	[PE_INIT_VDM_MODES_REQUEST] = "PE_INIT_VDM_Modes_Request",
-	[PE_VDM_REQUEST_DPM] = "PE_VDM_Request_DPM",
-	[PE_VDM_RESPONSE] = "PE_VDM_Response",
-	[PE_HANDLE_CUSTOM_VDM_REQUEST] = "PE_Handle_Custom_Vdm_Request",
-	[PE_WAIT_FOR_ERROR_RECOVERY] = "PE_Wait_For_Error_Recovery",
-	[PE_BIST_TX] = "PE_Bist_TX",
-	[PE_DEU_SEND_ENTER_USB]  = "PE_DEU_Send_Enter_USB",
-	[PE_DR_GET_SINK_CAP] = "PE_DR_Get_Sink_Cap",
-	[PE_DR_SNK_GIVE_SOURCE_CAP] = "PE_DR_SNK_Give_Source_Cap",
-	[PE_DR_SRC_GET_SOURCE_CAP] = "PE_DR_SRC_Get_Source_Cap",
-
-	/* PD3.0 only states below here*/
-#ifdef CONFIG_USB_PD_REV30
-	[PE_FRS_SNK_SRC_START_AMS] = "PE_FRS_SNK_SRC_Start_Ams",
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	[PE_GIVE_BATTERY_CAP] = "PE_Give_Battery_Cap",
-	[PE_GIVE_BATTERY_STATUS] = "PE_Give_Battery_Status",
-	[PE_SEND_ALERT] = "PE_Send_Alert",
-#else
-	[PE_SRC_CHUNK_RECEIVED] = "PE_SRC_Chunk_Received",
-	[PE_SNK_CHUNK_RECEIVED] = "PE_SNK_Chunk_Received",
-#endif
-#ifdef CONFIG_USBC_VCONN
-	[PE_VCS_FORCE_VCONN] = "PE_VCS_Force_Vconn",
-#endif
-#endif /* CONFIG_USB_PD_REV30 */
-};
-
-#ifndef CONFIG_USBC_VCONN
-GEN_NOT_SUPPORTED(PE_VCS_EVALUATE_SWAP);
-#define PE_VCS_EVALUATE_SWAP PE_VCS_EVALUATE_SWAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_VCS_SEND_SWAP);
-#define PE_VCS_SEND_SWAP PE_VCS_SEND_SWAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_VCS_WAIT_FOR_VCONN_SWAP);
-#define PE_VCS_WAIT_FOR_VCONN_SWAP PE_VCS_WAIT_FOR_VCONN_SWAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_VCS_TURN_ON_VCONN_SWAP);
-#define PE_VCS_TURN_ON_VCONN_SWAP PE_VCS_TURN_ON_VCONN_SWAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_VCS_TURN_OFF_VCONN_SWAP);
-#define PE_VCS_TURN_OFF_VCONN_SWAP PE_VCS_TURN_OFF_VCONN_SWAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_VCS_SEND_PS_RDY_SWAP);
-#define PE_VCS_SEND_PS_RDY_SWAP PE_VCS_SEND_PS_RDY_SWAP_NOT_SUPPORTED
-#endif /* CONFIG_USBC_VCONN */
-
-#ifndef CONFIG_USB_PD_REV30
-GEN_NOT_SUPPORTED(PE_FRS_SNK_SRC_START_AMS);
-#define PE_FRS_SNK_SRC_START_AMS PE_FRS_SNK_SRC_START_AMS_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_PRS_FRS_SHARED);
-#define PE_PRS_FRS_SHARED PE_PRS_FRS_SHARED_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_SRC_CHUNK_RECEIVED);
-#define PE_SRC_CHUNK_RECEIVED PE_SRC_CHUNK_RECEIVED_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED);
-#define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_REV30 */
-
-#if !defined(CONFIG_USBC_VCONN) || !defined(CONFIG_USB_PD_REV30)
-GEN_NOT_SUPPORTED(PE_VCS_FORCE_VCONN);
-#define PE_VCS_FORCE_VCONN PE_VCS_FORCE_VCONN_NOT_SUPPORTED
-#endif
-
-#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
-GEN_NOT_SUPPORTED(PE_GIVE_BATTERY_CAP);
-#define PE_GIVE_BATTERY_CAP PE_GIVE_BATTERY_CAP_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_GIVE_BATTERY_STATUS);
-#define PE_GIVE_BATTERY_STATUS PE_GIVE_BATTERY_STATUS_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_SEND_ALERT);
-#define PE_SEND_ALERT PE_SEND_ALERT_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-GEN_NOT_SUPPORTED(PE_SRC_CHUNK_RECEIVED);
-#define PE_SRC_CHUNK_RECEIVED PE_SRC_CHUNK_RECEIVED_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED);
-#define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * Common message send checking
- *
- * PE_MSG_SEND_PENDING:   A message has been requested to be sent.  It has
- *                        not been GoodCRCed or Discarded.
- * PE_MSG_SEND_COMPLETED: The message that was requested has been sent.
- *                        This will only be returned one time and any other
- *                        request for message send status will just return
- *                        PE_MSG_SENT. This message actually includes both
- *                        The COMPLETED and the SENT bit for easier checking.
- *                        NOTE: PE_MSG_SEND_COMPLETED will only be returned
- *                        a single time, directly after TX_COMPLETE.
- * PE_MSG_SENT:           The message that was requested to be sent has
- *                        successfully been transferred to the partner.
- * PE_MSG_DISCARDED:      The message that was requested to be sent was
- *                        discarded.  The partner did not receive it.
- *                        NOTE: PE_MSG_DISCARDED will only be returned
- *                        one time and it is up to the caller to process
- *                        what ever is needed to handle the Discard.
- * PE_MSG_DPM_DISCARDED:  The message that was requested to be sent was
- *                        discarded and an active DRP_REQUEST was active.
- *                        The DRP_REQUEST that was current will be moved
- *                        back to the drp_requests so it can be performed
- *                        later if needed.
- *                        NOTE: PE_MSG_DPM_DISCARDED will only be returned
- *                        one time and it is up to the caller to process
- *                        what ever is needed to handle the Discard.
- */
-enum pe_msg_check {
-	PE_MSG_SEND_PENDING	= BIT(0),
-	PE_MSG_SENT		= BIT(1),
-	PE_MSG_DISCARDED	= BIT(2),
-
-	PE_MSG_SEND_COMPLETED	= BIT(3) | PE_MSG_SENT,
-	PE_MSG_DPM_DISCARDED	= BIT(4) | PE_MSG_DISCARDED,
-};
-static void pe_sender_response_msg_entry(const int port);
-static enum pe_msg_check pe_sender_response_msg_run(const int port);
-static void pe_sender_response_msg_exit(const int port);
-
-/* Debug log level - higher number == more log */
-#ifdef CONFIG_USB_PD_DEBUG_LEVEL
-static const enum debug_level pe_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
-#else
-static enum debug_level pe_debug_level = DEBUG_LEVEL_1;
-#endif
-
-/*
- * Policy Engine State Machine Object
- */
-static struct policy_engine {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* current port power role (SOURCE or SINK) */
-	enum pd_power_role power_role;
-	/* current port data role (DFP or UFP) */
-	enum pd_data_role data_role;
-	/* state machine flags */
-	uint32_t flags;
-	/* Device Policy Manager Request */
-	uint32_t dpm_request;
-	uint32_t dpm_curr_request;
-	/* last requested voltage PDO index */
-	int requested_idx;
-
-	/*
-	 * Port events - PD_STATUS_EVENT_* values
-	 * Set from PD task but may be cleared by host command
-	 */
-	uint32_t events;
-
-	/* port address where soft resets are sent */
-	enum tcpci_msg_type soft_reset_sop;
-
-	/* Current limit / voltage based on the last request message */
-	uint32_t curr_limit;
-	uint32_t supply_voltage;
-
-	/* PD_VDO_INVALID is used when there is an invalid VDO */
-	int32_t ama_vdo;
-	int32_t vpd_vdo;
-	/* Alternate mode discovery results */
-	struct pd_discovery discovery[DISCOVERY_TYPE_COUNT];
-	/* Active alternate modes */
-	struct partner_active_modes partner_amodes[AMODE_TYPE_COUNT];
-
-	/* Partner type to send */
-	enum tcpci_msg_type tx_type;
-
-	/* VDM - used to send information to shared VDM Request state */
-	uint32_t vdm_cnt;
-	uint32_t vdm_data[VDO_HDR_SIZE + VDO_MAX_SIZE];
-	uint8_t vdm_ack_min_data_objects;
-
-	/* Counters */
-
-	/*
-	 * This counter is used to retry the Hard Reset whenever there is no
-	 * response from the remote device.
-	 */
-	uint32_t hard_reset_counter;
-
-	/*
-	 * This counter is used to count the number of Source_Capabilities
-	 * Messages which have been sent by a Source at power up or after a
-	 * Hard Reset.
-	 */
-	uint32_t caps_counter;
-
-	/*
-	 * This counter maintains a count of Discover Identity Messages sent
-	 * to a cable.  If no GoodCRC messages are received after
-	 * nDiscoverIdentityCount, the port shall not send any further
-	 * SOP'/SOP'' messages.
-	 */
-	uint32_t discover_identity_counter;
-	/*
-	 * For PD2.0, we need to be a DFP before sending a discovery identity
-	 * message to our port partner. This counter keeps track of how
-	 * many attempts to DR SWAP from UFP to DFP.
-	 */
-	uint32_t dr_swap_attempt_counter;
-
-	/*
-	 * This counter tracks how many PR Swap messages are sent when the
-	 * partner responds with a Wait message. Only used during SRC to SNK
-	 * PR swaps
-	 */
-	uint8_t src_snk_pr_swap_counter;
-
-	/*
-	 * This counter maintains a count of VCONN swap requests. If VCONN swap
-	 * isn't successful after N_VCONN_SWAP_COUNT, the port calls
-	 * dpm_vdm_naked().
-	 */
-	uint8_t vconn_swap_counter;
-
-	/* Last received source cap */
-	uint32_t src_caps[PDO_MAX_OBJECTS];
-	int src_cap_cnt; /* -1 on error retrieving source caps */
-
-	/* Last received sink cap */
-	uint32_t snk_caps[PDO_MAX_OBJECTS];
-	int snk_cap_cnt;
-
-	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
-	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
-	enum ec_image current_image;
-} pe[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-test_export_static enum usb_pe_state get_state_pe(const int port);
-test_export_static void set_state_pe(const int port,
-				     const enum usb_pe_state new_state);
-static void pe_set_dpm_curr_request(const int port, const int request);
-/*
- * The spec. revision is used to index into this array.
- *  PD 1.0 (VDO 1.0) - return VDM_VER10
- *  PD 2.0 (VDO 1.0) - return VDM_VER10
- *  PD 3.0 (VDO 2.0) - return VDM_VER20
- */
-static const uint8_t vdo_ver[] = {
-	[PD_REV10] = VDM_VER10,
-	[PD_REV20] = VDM_VER10,
-	[PD_REV30] = VDM_VER20,
-};
-
-int pd_get_rev(int port, enum tcpci_msg_type type)
-{
-	return prl_get_rev(port, type);
-}
-
-int pd_get_vdo_ver(int port, enum tcpci_msg_type type)
-{
-	enum pd_rev_type rev = prl_get_rev(port, type);
-
-	if (rev < PD_REV30)
-		return vdo_ver[rev];
-	else
-		return VDM_VER20;
-}
-
-static void pe_set_ready_state(int port)
-{
-	if (pe[port].power_role == PD_ROLE_SOURCE)
-		set_state_pe(port, PE_SRC_READY);
-	else
-		set_state_pe(port, PE_SNK_READY);
-}
-
-static inline void send_data_msg(int port, enum tcpci_msg_type type,
-				 enum pd_data_msg_type msg)
-{
-	/* Clear any previous TX status before sending a new message */
-	PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-	prl_send_data_msg(port, type, msg);
-}
-
-static __maybe_unused inline void send_ext_data_msg(
-	int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg)
-{
-	/* Clear any previous TX status before sending a new message */
-	PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-	prl_send_ext_data_msg(port, type, msg);
-}
-
-static inline void send_ctrl_msg(int port, enum tcpci_msg_type type,
-				 enum pd_ctrl_msg_type msg)
-{
-	/* Clear any previous TX status before sending a new message */
-	PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-	prl_send_ctrl_msg(port, type, msg);
-}
-
-static void set_cable_rev(int port)
-{
-	/*
-	 * If port partner runs PD 2.0, cable communication must
-	 * also be PD 2.0
-	 */
-	if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
-	/*
-	 * If the cable supports PD 3.0, but the port partner supports PD 2.0,
-	 * redo the cable discover with PD 2.0
-	 */
-		if (prl_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30 &&
-		    pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-					PD_DISC_COMPLETE) {
-			pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME,
-					PD_DISC_NEEDED);
-		}
-		prl_set_rev(port, TCPCI_MSG_SOP_PRIME, PD_REV20);
-	}
-}
-
-/* Compile-time insurance to ensure this code does not call into prl directly */
-#define prl_send_data_msg DO_NOT_USE
-#define prl_send_ext_data_msg DO_NOT_USE
-#define prl_send_ctrl_msg DO_NOT_USE
-
-static void pe_init(int port)
-{
-	pe[port].flags = 0;
-	pe[port].dpm_request = 0;
-	pe[port].dpm_curr_request = 0;
-	pd_timer_disable_range(port, PE_TIMER_RANGE);
-	pe[port].data_role = pd_get_data_role(port);
-	pe[port].tx_type = TCPCI_MSG_INVALID;
-	pe[port].events = 0;
-
-	tc_pd_connection(port, 0);
-
-	if (pd_get_power_role(port) == PD_ROLE_SOURCE)
-		set_state_pe(port, PE_SRC_STARTUP);
-	else
-		set_state_pe(port, PE_SNK_STARTUP);
-}
-
-int pe_is_running(int port)
-{
-	return local_state[port] == SM_RUN;
-}
-
-bool pe_in_frs_mode(int port)
-{
-	return PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
-}
-
-bool pe_in_local_ams(int port)
-{
-	return !!PE_CHK_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-}
-
-void pe_set_debug_level(enum debug_level debug_level)
-{
-#ifndef CONFIG_USB_PD_DEBUG_LEVEL
-	pe_debug_level = debug_level;
-#endif
-}
-
-void pe_run(int port, int evt, int en)
-{
-	switch (local_state[port]) {
-	case SM_PAUSED:
-		if (!en)
-			break;
-		/* fall through */
-	case SM_INIT:
-		pe_init(port);
-		local_state[port] = SM_RUN;
-		/* fall through */
-	case SM_RUN:
-		if (!en) {
-			local_state[port] = SM_PAUSED;
-			/*
-			 * While we are paused, exit all states and wait until
-			 * initialized again.
-			 */
-			set_state(port, &pe[port].ctx, NULL);
-			break;
-		}
-
-		/*
-		 * 8.3.3.3.8 PE_SNK_Hard_Reset State
-		 * The Policy Engine Shall transition to the PE_SNK_Hard_Reset
-		 * state from any state when:
-		 * - Hard Reset request from Device Policy Manager
-		 *
-		 * USB PD specification clearly states that we should go to
-		 * PE_SNK_Hard_Reset from ANY state (including states in which
-		 * port is source) when DPM requests that. This can lead to
-		 * execute Hard Reset path for sink when actually our power
-		 * role is source. In our implementation we will choose Hard
-		 * Reset path depending on current power role.
-		 */
-		if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_HARD_RESET_SEND)) {
-			pe_set_dpm_curr_request(port, DPM_REQUEST_HARD_RESET_SEND);
-			if (pd_get_power_role(port) == PD_ROLE_SOURCE)
-				set_state_pe(port, PE_SRC_HARD_RESET);
-			else
-				set_state_pe(port, PE_SNK_HARD_RESET);
-		}
-
-		/*
-		 * Check for Fast Role Swap signal
-		 * This is not a typical pattern for adding state changes.
-		 * I added this here because FRS SIGNALED can happen at any
-		 * state once we are listening for the signal and we want to
-		 * make sure to handle it immediately.
-		 */
-		if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-		PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) {
-			PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
-			set_state_pe(port, PE_FRS_SNK_SRC_START_AMS);
-		}
-
-		/* Run state machine */
-		run_state(port, &pe[port].ctx);
-		break;
-	}
-}
-
-int pe_is_explicit_contract(int port)
-{
-	return PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT);
-}
-
-void pe_message_received(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	PE_SET_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void pe_hard_reset_sent(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	PE_CLR_FLAG(port, PE_FLAGS_HARD_RESET_PENDING);
-}
-
-void pe_got_hard_reset(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	/*
-	 * Transition from any state to the PE_SRC_Hard_Reset_Received or
-	 *  PE_SNK_Transition_to_default state when:
-	 *  1) Hard Reset Signaling is detected.
-	 */
-	pe[port].power_role = pd_get_power_role(port);
-
-	/* Exit BIST Test mode, in case the TCPC entered it. */
-	tcpc_set_bist_test_mode(port, false);
-
-	if (pe[port].power_role == PD_ROLE_SOURCE)
-		set_state_pe(port, PE_SRC_HARD_RESET_RECEIVED);
-	else
-		set_state_pe(port, PE_SNK_TRANSITION_TO_DEFAULT);
-}
-
-#ifdef CONFIG_USB_PD_REV30
-/*
- * pd_got_frs_signal
- *
- * Called by the handler that detects the FRS signal in order to
- * switch PE states to complete the FRS that the hardware has
- * started.
- *
- * If the PE is not running, generate an error recovery to turn off
- * Vbus and get the port back into a known state.
- */
-void pd_got_frs_signal(int port)
-{
-	if (pe_is_running(port))
-		PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
-	else
-		pd_set_error_recovery(port);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-#endif /* CONFIG_USB_PD_REV30 */
-
-/*
- * PE_Set_FRS_Enable
- *
- * This function should be called every time an explicit contract
- * is disabled, to disable FRS.
- *
- * Enabling an explicit contract is not enough to enable FRS, it
- * also requires a Sink Capability power requirement from a Source
- * that supports FRS so we can determine if this is something we
- * can handle.
- */
-static void pe_set_frs_enable(int port, int enable)
-{
-	int current = PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
-
-	/* This should only be called from the PD task */
-	if (!IS_ENABLED(TEST_BUILD))
-		assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	if (!IS_ENABLED(CONFIG_USB_PD_FRS) || !IS_ENABLED(CONFIG_USB_PD_REV30))
-		return;
-
-	/* Request an FRS change, only if the state has changed */
-	if (!!current == !!enable)
-		return;
-
-	pd_set_frs_enable(port, enable);
-	if (enable) {
-		int curr_limit = *pd_get_snk_caps(port)
-						& PDO_FIXED_FRS_CURR_MASK;
-
-		typec_select_src_current_limit_rp(port,
-						  curr_limit ==
-						  PDO_FIXED_FRS_CURR_3A0_AT_5V ?
-						  TYPEC_RP_3A0 : TYPEC_RP_1A5);
-		PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
-	} else {
-		PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
-	}
-}
-
-void pe_set_explicit_contract(int port)
-{
-	PE_SET_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT);
-
-	/* Set Rp for collision avoidance */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		typec_update_cc(port);
-}
-
-void pe_invalidate_explicit_contract(int port)
-{
-	pe_set_frs_enable(port, 0);
-
-	PE_CLR_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT);
-
-	/* Set Rp for current limit if still attached */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pd_is_connected(port))
-		typec_update_cc(port);
-}
-
-void pd_notify_event(int port, uint32_t event_mask)
-{
-	atomic_or(&pe[port].events, event_mask);
-
-	/* Notify the host that new events are available to read */
-	pd_send_host_event(PD_EVENT_TYPEC);
-}
-
-void pd_clear_events(int port, uint32_t clear_mask)
-{
-	atomic_clear_bits(&pe[port].events, clear_mask);
-}
-
-uint32_t pd_get_events(int port)
-{
-	return pe[port].events;
-}
-
-void pe_set_snk_caps(int port, int cnt, uint32_t *snk_caps)
-{
-	pe[port].snk_cap_cnt = cnt;
-
-	memcpy(pe[port].snk_caps, snk_caps, sizeof(uint32_t) * cnt);
-}
-
-const uint32_t * const pd_get_snk_caps(int port)
-{
-	return pe[port].snk_caps;
-}
-
-uint8_t pd_get_snk_cap_cnt(int port)
-{
-	return pe[port].snk_cap_cnt;
-}
-
-uint32_t pd_get_requested_voltage(int port)
-{
-	return pe[port].supply_voltage;
-}
-
-uint32_t pd_get_requested_current(int port)
-{
-	return pe[port].curr_limit;
-}
-
-/*
- * Determine if this port may communicate with the cable plug.
- *
- * In both PD 2.0 and 3.0 (2.5.4 SOP'/SOP'' Communication with Cable Plugs):
- *
- * When no Contract or an Implicit Contract is in place (e.g. after a Power Role
- * Swap or Fast Role Swap) only the Source port that is supplying Vconn is
- * allowed to send packets to a Cable Plug
- *
- * When in an explicit contract, PD 3.0 requires that a port be Vconn source to
- * communicate with the cable.  PD 2.0 requires that a port be DFP to
- * communicate with the cable plug, with an implication that it must be Vconn
- * source as well (6.3.11 VCONN_Swap Message).
- */
-static bool pe_can_send_sop_prime(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
-		if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) {
-			if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20)
-				return tc_is_vconn_src(port) &&
-					pe[port].data_role == PD_ROLE_DFP;
-			else
-				return tc_is_vconn_src(port);
-		} else {
-			return tc_is_vconn_src(port) &&
-				pe[port].power_role == PD_ROLE_SOURCE;
-		}
-	} else {
-		return false;
-	}
-}
-
-/*
- * Determine if this port may send the given VDM type
- *
- * For PD 2.0, "Only the DFP Shall be an Initrator of Structured VDMs except for
- * the Attention Command that Shall only be initiated by the UFP"
- *
- * For PD 3.0, "Either port May be an Initiator of Structured VDMs except for
- * the Enter Mode and Exit Mode Commands which shall only be initiated by the
- * DFP" (6.4.4.2 Structured VDM)
- *
- * In both revisions, VDMs may only be initiated while in an explicit contract,
- * with the only exception being for cable plug discovery.
- */
-static bool pe_can_send_sop_vdm(int port, int vdm_cmd)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) {
-		if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
-			if (pe[port].data_role == PD_ROLE_UFP &&
-			    vdm_cmd != CMD_ATTENTION) {
-				return false;
-			}
-		} else {
-			if (pe[port].data_role == PD_ROLE_UFP &&
-			    (vdm_cmd == CMD_ENTER_MODE ||
-			     vdm_cmd == CMD_EXIT_MODE)) {
-				return false;
-			}
-		}
-		return true;
-	}
-
-	return false;
-}
-
-static void pe_send_soft_reset(const int port, enum tcpci_msg_type type)
-{
-	pe[port].soft_reset_sop = type;
-	set_state_pe(port, PE_SEND_SOFT_RESET);
-}
-
-void pe_report_discard(int port)
-{
-	/*
-	 * Clear local AMS indicator as our AMS message was discarded, and flag
-	 * the discard for the PE
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-	PE_SET_FLAG(port, PE_FLAGS_MSG_DISCARDED);
-
-	/* TODO(b/157228506): Ensure all states are checking discard */
-}
-
-/*
- * Utility function to check for an outgoing message discard during states which
- * send a message as a part of an AMS and wait for the transmit to complete.
- * Note these states should not be power transitioning.
- *
- * In these states, discard due to an incoming message is a protocol error.
- */
-static bool pe_check_outgoing_discard(int port)
-{
-	/*
-	 * On outgoing discard, soft reset with SOP* of incoming message
-	 *
-	 * See Table 6-65 Response to an incoming Message (except VDM) in PD 3.0
-	 * Version 2.0 Specification.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED) &&
-				PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		enum tcpci_msg_type sop =
-				PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		pe_send_soft_reset(port, sop);
-		return true;
-	}
-
-	return false;
-}
-
-void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	/*
-	 * If there is a timeout error while waiting for a chunk of a chunked
-	 * message, there is no requirement to trigger a soft reset.
-	 */
-	if (e == ERR_RCH_CHUNK_WAIT_TIMEOUT)
-		return;
-
-	/*
-	 * Generate Hard Reset if Protocol Error occurred
-	 * while in PE_Send_Soft_Reset state.
-	 */
-	if (get_state_pe(port) == PE_SEND_SOFT_RESET) {
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
-		return;
-	}
-
-	/*
-	 * The following states require custom handling of protocol errors,
-	 * because they either need special handling of the no GoodCRC case
-	 * (cable identity request, send capabilities), occur before explicit
-	 * contract (discovery), or happen during a power transition.
-	 *
-	 * TODO(b/150774779): TCPMv2: Improve pe_error documentation
-	 */
-	if ((get_state_pe(port) == PE_SRC_SEND_CAPABILITIES ||
-			get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY ||
-			get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
-			get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON ||
-			get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON ||
-			get_state_pe(port) == PE_SRC_DISABLED ||
-			get_state_pe(port) == PE_SRC_DISCOVERY ||
-			get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET ||
-			get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) ||
-			(pe_in_frs_mode(port) &&
-			    get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP)
-			) {
-		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		return;
-	}
-
-	/*
-	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State:
-	 *
-	 * The PE_Send_Soft_Reset state shall be entered from
-	 * any state when
-	 * * A Protocol Error is detected by Protocol Layer during a
-	 *   Non-Interruptible AMS or
-	 * * A message has not been sent after retries or
-	 * * When not in an explicit contract and
-	 *   * Protocol Errors occurred on SOP during an Interruptible AMS or
-	 *   * Protocol Errors occurred on SOP during any AMS where the first
-	 *     Message in the sequence has not yet been sent i.e. an unexpected
-	 *     Message is received instead of the expected GoodCRC Message
-	 *     response.
-	 */
-	/* All error types besides transmit errors are Protocol Errors. */
-	if ((e != ERR_TCH_XMIT &&
-				!PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS))
-			|| e == ERR_TCH_XMIT
-			|| (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) &&
-				type == TCPCI_MSG_SOP)) {
-		pe_send_soft_reset(port, type);
-	}
-	/*
-	 * Transition to PE_Snk_Ready or PE_Src_Ready by a Protocol
-	 * Error during an Interruptible AMS.
-	 */
-	else {
-		pe_set_ready_state(port);
-	}
-}
-
-void pe_got_soft_reset(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	/*
-	 * The PE_SRC_Soft_Reset state Shall be entered from any state when a
-	 * Soft_Reset Message is received from the Protocol Layer.
-	 */
-	set_state_pe(port, PE_SOFT_RESET);
-}
-
-__overridable bool pd_can_charge_from_device(int port, const int pdo_cnt,
-				      const uint32_t *pdos)
-{
-	/*
-	 * Don't attempt to charge from a device we have no SrcCaps from. Or, if
-	 * drp_state is FORCE_SOURCE then don't attempt a PRS.
-	 */
-	if (pdo_cnt == 0 || pd_get_dual_role(port) == PD_DRP_FORCE_SOURCE)
-		return false;
-
-	/*
-	 * Treat device as a dedicated charger (meaning we should charge
-	 * from it) if:
-	 *   - it does not support power swap, or
-	 *   - it is unconstrained power, or
-	 *   - it presents at least 27 W of available power
-	 */
-
-	/* Unconstrained Power or NOT Dual Role Power we can charge from */
-	if (pdos[0] & PDO_FIXED_UNCONSTRAINED ||
-	    (pdos[0] & PDO_FIXED_DUAL_ROLE) == 0)
-		return true;
-
-	/* [virtual] allow_list */
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		uint32_t max_ma, max_mv, max_pdo, max_mw, unused;
-
-		/*
-		 * Get max power that the partner offers (not necessarily what
-		 * this board will request)
-		 */
-		pd_find_pdo_index(pdo_cnt, pdos,
-				  PD_REV3_MAX_VOLTAGE,
-				  &max_pdo);
-		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
-		max_mw = max_ma * max_mv / 1000;
-
-		if (max_mw >= PD_DRP_CHARGE_POWER_MIN)
-			return true;
-	}
-	return false;
-}
-
-void pd_resume_check_pr_swap_needed(int port)
-{
-	/*
-	 * Explicit contract, current power role of SNK, the device
-	 * indicates it should not power us, and device isn't selected
-	 * as the charging port (ex. through the GUI) then trigger a PR_Swap
-	 */
-	if (pe_is_explicit_contract(port) &&
-	    pd_get_power_role(port) == PD_ROLE_SINK &&
-	    !pd_can_charge_from_device(port, pd_get_src_cap_cnt(port),
-				       pd_get_src_caps(port)) &&
-	    (!IS_ENABLED(CONFIG_CHARGE_MANAGER) ||
-	     charge_manager_get_active_charge_port() != port))
-		pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
-}
-
-void pd_dpm_request(int port, enum pd_dpm_request req)
-{
-	PE_SET_DPM_REQUEST(port, req);
-}
-
-void pe_vconn_swap_complete(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	PE_SET_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-}
-
-void pe_ps_reset_complete(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	PE_SET_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE);
-}
-
-void pe_message_sent(int port)
-{
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	PE_SET_FLAG(port, PE_FLAGS_TX_COMPLETE);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-						int count)
-{
-	/* Copy VDM Header */
-	pe[port].vdm_data[0] =
-		VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?  1 :
-				(PD_VDO_CMD(cmd) <= CMD_ATTENTION),
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) |
-				cmd);
-
-	/*
-	 * Copy VDOs after the VDM Header. Note that the count refers to VDO
-	 * count.
-	 */
-	memcpy((pe[port].vdm_data + 1), data, count * sizeof(uint32_t));
-
-	pe[port].vdm_cnt = count + 1;
-
-	/*
-	 * The PE transmit routine assumes that tx_type was set already. Note,
-	 * that this function is likely called from outside the PD task.
-	 * (b/180465870)
-	 */
-	pe[port].tx_type = TCPCI_MSG_SOP;
-	pd_dpm_request(port, DPM_REQUEST_VDM);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-#ifdef TEST_BUILD
-/*
- * Allow unit tests to access this function to clear internal state data between
- * runs
- */
-void pe_clear_port_data(int port)
-#else
-static void pe_clear_port_data(int port)
-#endif /* TEST_BUILD */
-{
-	/*
-	 * PD 3.0 Section 8.3.3.3.8
-	 * Note: The HardResetCounter is reset on a power cycle or Detach.
-	 */
-	pe[port].hard_reset_counter = 0;
-
-	/* Reset port events */
-	pd_clear_events(port, GENMASK(31, 0));
-
-	/* But then set disconnected event */
-	pd_notify_event(port, PD_STATUS_EVENT_DISCONNECTED);
-
-	/* Tell Policy Engine to invalidate the explicit contract */
-	pe_invalidate_explicit_contract(port);
-
-	/*
-	 * Saved Source and Sink Capabilities are no longer valid on disconnect
-	 */
-	pd_set_src_caps(port, 0, NULL);
-	pe_set_snk_caps(port, 0, NULL);
-
-	dpm_remove_sink(port);
-	dpm_remove_source(port);
-
-	/* Exit BIST Test mode, in case the TCPC entered it. */
-	tcpc_set_bist_test_mode(port, false);
-}
-
-static void pe_handle_detach(void)
-{
-	const int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	pe_clear_port_data(port);
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, pe_handle_detach, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-static void pe_update_waiting_batt_flag(void)
-{
-	int i;
-	int batt_soc = usb_get_battery_soc();
-
-	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
-	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
-		return;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (PE_CHK_FLAG(i, PE_FLAGS_SNK_WAITING_BATT)) {
-			/*
-			 * Battery has gained sufficient charge to kick off PD
-			 * negotiation and withstand a hard reset. Clear the
-			 * flag and perform Hard Reset.
-			 */
-			PE_CLR_FLAG(i, PE_FLAGS_SNK_WAITING_BATT);
-			CPRINTS("C%d: Battery has enough charge (%d%%) " \
-			    "to withstand a hard reset", i, batt_soc);
-			pd_dpm_request(i, DPM_REQUEST_HARD_RESET_SEND);
-		}
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pe_update_waiting_batt_flag,
-							HOOK_PRIO_DEFAULT);
-#endif
-
-/*
- * Private functions
- */
-static void pe_set_dpm_curr_request(const int port,
-				    const int request)
-{
-	PE_CLR_DPM_REQUEST(port, request);
-	pe[port].dpm_curr_request = request;
-}
-
-/* Set the TypeC state machine to a new state. */
-test_export_static void set_state_pe(const int port,
-				     const enum usb_pe_state new_state)
-{
-	set_state(port, &pe[port].ctx, &pe_states[new_state]);
-}
-
-/* Get the current TypeC state. */
-test_export_static enum usb_pe_state get_state_pe(const int port)
-{
-	return pe[port].ctx.current - &pe_states[0];
-}
-
-/*
- * Handle common DPM requests to both source and sink.
- *
- * Note: it is assumed the calling state set PE_FLAGS_LOCALLY_INITIATED_AMS
- *
- * Returns true if state was set and calling run state should now return.
- */
-static bool common_src_snk_dpm_requests(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT);
-		set_state_pe(port, PE_SEND_ALERT);
-		return true;
-	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_VCONN_SWAP);
-		set_state_pe(port, PE_VCS_SEND_SWAP);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_BIST_TX)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_BIST_TX);
-		set_state_pe(port, PE_BIST_TX);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SNK_STARTUP)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SNK_STARTUP);
-		set_state_pe(port, PE_SNK_STARTUP);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SRC_STARTUP)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SRC_STARTUP);
-		set_state_pe(port, PE_SRC_STARTUP);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SOFT_RESET_SEND)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SOFT_RESET_SEND);
-		/* Currently only support sending soft reset to SOP */
-		pe_send_soft_reset(port, TCPCI_MSG_SOP);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_PORT_DISCOVERY)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_PORT_DISCOVERY);
-		if (!PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION)) {
-			/*
-			 * Clear counters and reset timer to trigger a
-			 * port discovery, and also clear any pending VDM send
-			 * requests.
-			 */
-			pd_dfp_discovery_init(port);
-			/*
-			 * TODO(b/189353401): Do not reinitialize modes when no
-			 * longer required.
-			 */
-			pd_dfp_mode_init(port);
-			pe[port].dr_swap_attempt_counter = 0;
-			pe[port].discover_identity_counter = 0;
-			pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
-					PD_T_DISCOVER_IDENTITY);
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_VDM);
-		}
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VDM)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_VDM);
-		/* Send previously set up SVDM. */
-		set_state_pe(port, PE_VDM_REQUEST_DPM);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_ENTER_USB)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_ENTER_USB);
-		set_state_pe(port, PE_DEU_SEND_ENTER_USB);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_EXIT_MODES)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_EXIT_MODES);
-		dpm_set_mode_exit_request(port);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SNK_CAPS)) {
-		pe_set_dpm_curr_request(port,
-					DPM_REQUEST_GET_SNK_CAPS);
-		set_state_pe(port, PE_DR_GET_SINK_CAP);
-		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-				      DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND)) {
-		pe_set_dpm_curr_request(port,
-			DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
-		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
-		set_state_pe(port, PE_VCS_CBL_SEND_SOFT_RESET);
-		return true;
-	}
-
-	return false;
-}
-
-/*
- * Handle source-specific DPM requests
- *
- * Returns true if state was set and calling run state should now return.
- */
-static bool source_dpm_requests(int port)
-{
-	/*
-	 * Ignore sink-specific request:
-	 *   DPM_REQUEST_NEW_POWER_LEVEL
-	 *   DPM_REQUEST_SOURCE_CAP
-	 *   DPM_REQUEST_FRS_DET_ENABLE
-	 *   DPM_REQURST_FRS_DET_DISABLE
-	 */
-	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_NEW_POWER_LEVEL |
-				 DPM_REQUEST_SOURCE_CAP |
-				 DPM_REQUEST_FRS_DET_ENABLE |
-				 DPM_REQUEST_FRS_DET_DISABLE);
-
-	if (pe[port].dpm_request) {
-		uint32_t dpm_request = pe[port].dpm_request;
-
-		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-
-		if (PE_CHK_DPM_REQUEST(port,
-				       DPM_REQUEST_DR_SWAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_DR_SWAP);
-			if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-				set_state_pe(port, PE_SRC_HARD_RESET);
-			else
-				set_state_pe(port, PE_DRS_SEND_SWAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_PR_SWAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_PR_SWAP);
-			set_state_pe(port, PE_PRS_SRC_SNK_SEND_SWAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_GOTO_MIN)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GOTO_MIN);
-			set_state_pe(port, PE_SRC_TRANSITION_SUPPLY);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_SRC_CAP_CHANGE)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SRC_CAP_CHANGE);
-			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_GET_SRC_CAPS)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GET_SRC_CAPS);
-			set_state_pe(port, PE_DR_SRC_GET_SOURCE_CAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_SEND_PING)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SEND_PING);
-			set_state_pe(port, PE_SRC_PING);
-			return true;
-		} else if (common_src_snk_dpm_requests(port)) {
-			return true;
-		}
-
-		CPRINTF("Unhandled DPM Request %x received\n",
-			dpm_request);
-		PE_CLR_DPM_REQUEST(port, dpm_request);
-		PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-	}
-	return false;
-}
-
-/*
- * Handle sink-specific DPM requests
- *
- * Returns true if state was set and calling run state should now return.
- */
-static bool sink_dpm_requests(int port)
-{
-	/*
-	 * Ignore source specific requests:
-	 *   DPM_REQUEST_GOTO_MIN
-	 *   DPM_REQUEST_SRC_CAP_CHANGE,
-	 *   DPM_REQUEST_SEND_PING
-	 */
-	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN |
-			   DPM_REQUEST_SRC_CAP_CHANGE |
-			   DPM_REQUEST_SEND_PING);
-
-	if (pe[port].dpm_request) {
-		uint32_t dpm_request = pe[port].dpm_request;
-
-		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-
-		if (PE_CHK_DPM_REQUEST(port,
-				       DPM_REQUEST_DR_SWAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_DR_SWAP);
-			if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-				set_state_pe(port, PE_SNK_HARD_RESET);
-			else
-				set_state_pe(port, PE_DRS_SEND_SWAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_PR_SWAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_PR_SWAP);
-			set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_SOURCE_CAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SOURCE_CAP);
-			set_state_pe(port, PE_SNK_GET_SOURCE_CAP);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_NEW_POWER_LEVEL)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_NEW_POWER_LEVEL);
-			set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
-			return true;
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_FRS_DET_ENABLE)) {
-			pe_set_frs_enable(port, 1);
-
-			/* Requires no state change, fall through to false */
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_FRS_DET_ENABLE);
-		} else if (PE_CHK_DPM_REQUEST(port,
-					      DPM_REQUEST_FRS_DET_DISABLE)) {
-			pe_set_frs_enable(port, 0);
-			/* Restore a default port current limit */
-			typec_select_src_current_limit_rp(port,
-							  CONFIG_USB_PD_PULLUP);
-
-			/* Requires no state change, fall through to false */
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_FRS_DET_DISABLE);
-		} else if (common_src_snk_dpm_requests(port)) {
-			return true;
-		} else {
-			CPRINTF("Unhandled DPM Request %x received\n",
-				dpm_request);
-			PE_CLR_DPM_REQUEST(port, dpm_request);
-		}
-
-		PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-	}
-	return false;
-}
-
-/* Get the previous TypeC state. */
-static enum usb_pe_state get_last_state_pe(const int port)
-{
-	return pe[port].ctx.previous - &pe_states[0];
-}
-
-static void print_current_state(const int port)
-{
-	const char *mode = "";
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			pe_in_frs_mode(port))
-		mode = " FRS-MODE";
-
-	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
-		CPRINTS_L1("C%d: %s%s", port,
-			pe_state_names[get_state_pe(port)], mode);
-	else
-		CPRINTS("C%d: pe-st%d", port, get_state_pe(port));
-}
-
-static void send_source_cap(int port)
-{
-	const uint32_t *src_pdo;
-	const int src_pdo_cnt = dpm_get_source_pdo(&src_pdo, port);
-
-	if (src_pdo_cnt == 0) {
-		/* No source capabilities defined, sink only */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-	}
-
-	tx_emsg[port].len = src_pdo_cnt * 4;
-	memcpy(tx_emsg[port].buf, (uint8_t *)src_pdo, tx_emsg[port].len);
-
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP);
-}
-
-/*
- * Request desired charge voltage from source.
- */
-static void pe_send_request_msg(int port)
-{
-	uint32_t vpd_vdo = 0;
-	uint32_t rdo;
-	uint32_t curr_limit;
-	uint32_t supply_voltage;
-
-	/*
-	 * If we are charging through a VPD, the requested voltage and current
-	 * might need adjusting.
-	 */
-	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
-						is_vpd_ct_supported(port)) {
-		union vpd_vdo vpd = pd_get_am_discovery(port,
-				TCPCI_MSG_SOP_PRIME)->identity.product_t1.vpd;
-
-		/* The raw vpd_vdo is passed to pd_build_request */
-		vpd_vdo = vpd.raw_value;
-	}
-
-	/* Build and send request RDO */
-	pd_build_request(vpd_vdo, &rdo, &curr_limit,
-			&supply_voltage, port);
-
-	CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-					supply_voltage, curr_limit);
-	if (rdo & RDO_CAP_MISMATCH)
-		CPRINTF(" Mismatch");
-	CPRINTF("\n");
-
-	pe[port].curr_limit = curr_limit;
-	pe[port].supply_voltage = supply_voltage;
-
-	tx_emsg[port].len = 4;
-
-	memcpy(tx_emsg[port].buf, (uint8_t *)&rdo, tx_emsg[port].len);
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_REQUEST);
-}
-
-static void pe_update_src_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
-{
-	/*
-	 * Only parse PDO flags if type is fixed
-	 *
-	 * Note: From 6.4.1 Capabilities Message "The vSafe5V Fixed Supply
-	 * Object Shall always be the first object." so hitting this condition
-	 * would mean the partner is voilating spec.
-	 */
-	if ((pdos[0] & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-		return;
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		if (pd_can_charge_from_device(port, pdo_cnt, pdos)) {
-			charge_manager_update_dualrole(port, CAP_DEDICATED);
-		} else {
-			charge_manager_update_dualrole(port, CAP_DUALROLE);
-		}
-	}
-}
-
-/*
- * Evaluate whether our PR role is in the middle of changing, meaning we our
- * current PR role is not the one we expect to have very shortly.
- */
-bool pe_is_pr_swapping(int port)
-{
-	enum usb_pe_state cur_state = get_state_pe(port);
-
-	if (cur_state == PE_PRS_SRC_SNK_EVALUATE_SWAP ||
-	    cur_state == PE_PRS_SRC_SNK_TRANSITION_TO_OFF ||
-	    cur_state == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
-	    cur_state == PE_PRS_SNK_SRC_TRANSITION_TO_OFF)
-		return true;
-
-	return false;
-}
-
-void pd_request_power_swap(int port)
-{
-	/* Ignore requests when the board does not wish to swap */
-	if (!pd_check_power_swap(port))
-		return;
-
-	/* Ignore requests when our power role is transitioning */
-	if (pe_is_pr_swapping(port))
-		return;
-
-	/*
-	 * Always reset the SRC to SNK PR swap counter when a PR swap is
-	 * requested by policy.
-	 */
-	pe[port].src_snk_pr_swap_counter = 0;
-	pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
-}
-
-/* The function returns true if there is a PE state change, false otherwise */
-static bool port_try_vconn_swap(int port)
-{
-	if (pe[port].vconn_swap_counter < N_VCONN_SWAP_COUNT) {
-		pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
-		set_state_pe(port, get_last_state_pe(port));
-		return true;
-	}
-	return false;
-}
-
-/*
- * Run discovery at our leisure from PE_SNK_Ready or PE_SRC_Ready, after
- * attempting to get into the desired default policy of DFP/Vconn source
- *
- * Return indicates whether set_state was called, in which case the calling
- * function should return as well.
- */
-__maybe_unused static bool pe_attempt_port_discovery(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-
-	/*
-	 * DONE set once modal entry is successful, discovery completes, or
-	 * discovery results in a NAK
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_SETUP_DONE))
-		return false;
-
-	/* Apply Port Discovery DR Swap Policy */
-	if (port_discovery_dr_swap_policy(port, pe[port].data_role,
-			PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) {
-		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-		PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
-		set_state_pe(port, PE_DRS_SEND_SWAP);
-		return true;
-	}
-
-	/* Apply Port Discovery VCONN Swap Policy */
-	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			port_discovery_vconn_swap_policy(port,
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) {
-		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
-		set_state_pe(port, PE_VCS_SEND_SWAP);
-		return true;
-	}
-
-	/* If mode entry was successful, disable the timer */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_SETUP_DONE)) {
-		pd_timer_disable(port, PE_TIMER_DISCOVER_IDENTITY);
-		return false;
-	}
-
-	/*
-	 * Run discovery functions when the timer indicating either cable
-	 * discovery spacing or BUSY spacing runs out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
-		if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED) {
-			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
-			set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
-			return true;
-		} else if (pd_get_identity_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) {
-			pe[port].tx_type = TCPCI_MSG_SOP;
-			set_state_pe(port,
-				     PE_INIT_PORT_VDM_IDENTITY_REQUEST);
-			return true;
-		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) {
-			pe[port].tx_type = TCPCI_MSG_SOP;
-			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
-			return true;
-		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) {
-			pe[port].tx_type = TCPCI_MSG_SOP;
-			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
-			return true;
-		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME)
-				== PD_DISC_NEEDED) {
-			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
-			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
-			return true;
-		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED) {
-			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
-			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
-			return true;
-		}
-	}
-
-	return false;
-}
-
-bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type,
-		uint32_t *vdm, uint32_t vdo_cnt)
-{
-	if (vdo_cnt < VDO_HDR_SIZE || vdo_cnt > VDO_MAX_SIZE)
-		return false;
-
-	pe[port].tx_type = tx_type;
-	memcpy(pe[port].vdm_data, vdm, vdo_cnt * sizeof(*vdm));
-	pe[port].vdm_cnt = vdo_cnt;
-
-	return true;
-}
-
-int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
-					uint32_t current_image)
-{
-	pe[port].dev_id = dev_id;
-	memcpy(pe[port].dev_rw_hash, rw_hash, PD_RW_HASH_SIZE);
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-	pd_dev_dump_info(dev_id, rw_hash);
-#endif
-	pe[port].current_image = current_image;
-
-	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD)) {
-		int i;
-
-		/* Search table for matching device / hash */
-		for (i = 0; i < RW_HASH_ENTRIES; i++)
-			if (dev_id == rw_hash_table[i].dev_id)
-				return !memcmp(rw_hash,
-					       rw_hash_table[i].dev_rw_hash,
-					       PD_RW_HASH_SIZE);
-	}
-
-	return 0;
-}
-
-void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
-{
-	*dev_id = pe[port].dev_id;
-	*current_image = pe[port].current_image;
-	if (*dev_id)
-		memcpy(rw_hash, pe[port].dev_rw_hash, PD_RW_HASH_SIZE);
-}
-
-/*
- * This function must only be called from the PE_SNK_READY entry and
- * PE_SRC_READY entry State.
- *
- * TODO(b:181339670) Rethink jitter timer restart if this is the first
- * message but the partner gets a message in first, may not want to
- * disable and restart it.
- */
-static void pe_update_wait_and_add_jitter_timer(int port)
-{
-	/*
-	 * In PD2.0 Mode
-	 *
-	 * For Source:
-	 * Give the sink some time to send any messages
-	 * before we may send messages of our own.  Add
-	 * some jitter of up to ~345ms, to prevent
-	 * multiple collisions. This delay also allows
-	 * the sink device to request power role swap
-	 * and allow the the accept message to be sent
-	 * prior to CMD_DISCOVER_IDENT being sent in the
-	 * SRC_READY state.
-	 *
-	 * For Sink:
-	 * Give the source some time to send any messages before
-	 * we start our interrogation.  Add some jitter of up to
-	 * ~345ms to prevent multiple collisions.
-	 */
-	if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20 &&
-	    PE_CHK_FLAG(port, PE_FLAGS_FIRST_MSG) &&
-	    pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
-		pd_timer_enable(port, PE_TIMER_WAIT_AND_ADD_JITTER,
-				SRC_SNK_READY_HOLD_OFF_US +
-				(get_time().le.lo & 0xf) * 23 * MSEC);
-	}
-}
-
-/**
- * Common sender response message handling
- *
- * This is setup like a pseudo state machine parent state.  It
- * centralizes the SenderResponseTimer for the calling states, as
- * well as checking message send status.
- */
-/*
- * pe_sender_response_msg_entry
- * Initialization for handling sender response messages.
- *
- * @param port USB-C Port number
- */
-static void pe_sender_response_msg_entry(const int port)
-{
-	/* Stop sender response timer */
-	pd_timer_disable(port, PE_TIMER_SENDER_RESPONSE);
-}
-
-/*
- * pe_sender_response_msg_run
- * Check status of sender response messages.
- *
- * The normal progression of pe_sender_response_msg_entry is:
- *    PENDING -> (COMPLETED/SENT) -> SENT -> SENT ...
- * or
- *    PENDING -> DISCARDED
- *    PENDING -> DPM_DISCARDED
- *
- * NOTE: it is not valid to call this function for a message after
- * receiving either PE_MSG_DISCARDED or PE_MSG_DPM_DISCARDED until
- * another message has been sent and pe_sender_response_msg_entry is called
- * again.
- *
- * @param port USB-C Port number
- * @return the current pe_msg_check
- */
-static enum pe_msg_check pe_sender_response_msg_run(const int port)
-{
-	timestamp_t tx_success_ts;
-	uint32_t offset;
-	if (pd_timer_is_disabled(port, PE_TIMER_SENDER_RESPONSE)) {
-		/* Check for Discard */
-		if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-			int dpm_request = pe[port].dpm_curr_request;
-
-			PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
-			/* Restore the DPM Request */
-			if (dpm_request) {
-				PE_SET_DPM_REQUEST(port, dpm_request);
-				return PE_MSG_DPM_DISCARDED;
-			}
-			return PE_MSG_DISCARDED;
-		}
-
-		/* Check for GoodCRC */
-		if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-			PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-			/* TCPC TX success time stamp */
-			tx_success_ts = prl_get_tcpc_tx_success_ts(port);
-			/* Calculate the delay from TX success to PE */
-			offset = time_since32(tx_success_ts);
-
-			/*
-			 * Initialize and run the SenderResponseTimer by
-			 * offsetting it with TX transmit success time.
-			 * This would remove the effect of the latency from
-			 * propagating the TX status.
-			 */
-			pd_timer_enable(port, PE_TIMER_SENDER_RESPONSE,
-					PD_T_SENDER_RESPONSE - offset);
-			return PE_MSG_SEND_COMPLETED;
-		}
-		return PE_MSG_SEND_PENDING;
-	}
-	return PE_MSG_SENT;
-}
-
-/*
- * pe_sender_response_msg_exit
- * Exit cleanup for handling sender response messages.
- *
- * @param port USB-C Port number
- */
-static void pe_sender_response_msg_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_SENDER_RESPONSE);
-}
-
-/**
- * PE_SRC_Startup
- */
-static void pe_src_startup_entry(int port)
-{
-	print_current_state(port);
-
-	/* Reset CapsCounter */
-	pe[port].caps_counter = 0;
-
-	/* Reset the protocol layer */
-	prl_reset_soft(port);
-
-	/* Set initial data role */
-	pe[port].data_role = pd_get_data_role(port);
-
-	/* Set initial power role */
-	pe[port].power_role = PD_ROLE_SOURCE;
-
-	/* Clear explicit contract. */
-	pe_invalidate_explicit_contract(port);
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
-		/*
-		 * Protocol layer reset clears the message IDs for all SOP
-		 * types. Indicate that a SOP' soft reset is required before any
-		 * other messages are sent to the cable.
-		 *
-		 * Note that other paths into this state are for the initial
-		 * connection and for a hard reset. In both cases the cable
-		 * should also automatically clear the message IDs so don't
-		 * generate an SOP' soft reset for those cases. Sending
-		 * unnecessary SOP' soft resets causes bad behavior with
-		 * some devices. See b/179325862.
-		 */
-		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
-
-		/* Start SwapSourceStartTimer */
-		pd_timer_enable(port, PE_TIMER_SWAP_SOURCE_START,
-				PD_T_SWAP_SOURCE_START);
-
-		/*
-		 * Evaluate port's sink caps for preferred current, if
-		 * already available
-		 */
-		if (pd_get_snk_cap_cnt(port) > 0)
-			dpm_evaluate_sink_fixed_pdo(port,
-						    *pd_get_snk_caps(port));
-
-		/*
-		 * Remove prior FRS claims to 3.0 A now that sink current has
-		 * been claimed, to avoid issues with lower priority ports
-		 * potentially receiving a 3.0 A claim between calls.
-		 */
-		dpm_remove_source(port);
-	} else {
-		/*
-		 * SwapSourceStartTimer delay is not needed, so trigger now.
-		 * We can't use set_state_pe here, since we need to ensure that
-		 * the protocol layer is running again (done in run function).
-		 */
-		pd_timer_enable(port, PE_TIMER_SWAP_SOURCE_START, 0);
-
-		/*
-		 * Set DiscoverIdentityTimer to trigger when we enter
-		 * src_discovery for the first time.  After initial startup
-		 * set, vdm_identity_request_cbl will handle the timer updates.
-		 */
-		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, 0);
-
-		/* Clear port discovery/mode flags */
-		pd_dfp_discovery_init(port);
-		pd_dfp_mode_init(port);
-		pe[port].ama_vdo = PD_VDO_INVALID;
-		pe[port].vpd_vdo = PD_VDO_INVALID;
-		pe[port].discover_identity_counter = 0;
-
-		/* Reset dr swap attempt counter */
-		pe[port].dr_swap_attempt_counter = 0;
-
-		/* Reset VCONN swap counter */
-		pe[port].vconn_swap_counter = 0;
-
-		/* Request partner sink caps if a feature requires them */
-		if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) ||
-						CONFIG_USB_PD_3A_PORTS > 0 ||
-						IS_ENABLED(CONFIG_USB_PD_FRS))
-			pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
-	}
-}
-
-static void pe_src_startup_run(int port)
-{
-	/* Wait until protocol layer is running */
-	if (!prl_is_running(port))
-		return;
-
-	if (pd_timer_is_expired(port, PE_TIMER_SWAP_SOURCE_START))
-		set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-}
-
-static void pe_src_startup_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_SWAP_SOURCE_START);
-}
-
-/**
- * PE_SRC_Discovery
- */
-static void pe_src_discovery_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * Initialize and run the SourceCapabilityTimer in order
-	 * to trigger sending a Source_Capabilities Message.
-	 *
-	 * The SourceCapabilityTimer Shall continue to run during
-	 * identity discover and Shall Not be initialized on re-entry
-	 * to PE_SRC_Discovery.
-	 *
-	 * Note: Cable identity is the only valid VDM to probe before a contract
-	 * is in place.  All other probing must happen from ready states.
-	 */
-	if (get_last_state_pe(port) != PE_VDM_IDENTITY_REQUEST_CBL)
-		pd_timer_enable(port, PE_TIMER_SOURCE_CAP,
-				PD_T_SEND_SOURCE_CAP);
-}
-
-static void pe_src_discovery_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Send_Capabilities state when:
-	 *   1) The SourceCapabilityTimer times out and
-	 *      CapsCounter ≤ nCapsCount.
-	 *
-	 * Transition to the PE_SRC_Disabled state when:
-	 *   1) The Port Partners are not presently PD Connected
-	 *   2) And the SourceCapabilityTimer times out
-	 *   3) And CapsCounter > nCapsCount.
-	 *
-	 * Transition to the PE_SRC_VDM_Identity_request state when:
-	 *   1) DPM requests the identity of the cable plug and
-	 *   2) DiscoverIdentityCounter < nDiscoverIdentityCount
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_SOURCE_CAP)) {
-		if (pe[port].caps_counter <= N_CAPS_COUNT) {
-			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-			return;
-		} else if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION)) {
-			set_state_pe(port, PE_SRC_DISABLED);
-			return;
-		}
-	}
-
-	/*
-	 * Note: While the DiscoverIdentityTimer is only required in an explicit
-	 * contract, we use it here to ensure we space any potential BUSY
-	 * requests properly.
-	 */
-	if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED
-			&& pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)
-			&& pe_can_send_sop_prime(port)
-			&& (pe[port].discover_identity_counter <
-				N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) {
-		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
-		set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
-		return;
-	}
-
-	/*
-	 * Transition to the PE_SRC_Disabled state when:
-	 *   1) The Port Partners have not been PD Connected.
-	 *   2) And the NoResponseTimer times out.
-	 *   3) And the HardResetCounter > nHardResetCount.
-	 */
-	if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION) &&
-	    pd_timer_is_expired(port, PE_TIMER_NO_RESPONSE) &&
-	    pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
-		set_state_pe(port, PE_SRC_DISABLED);
-		return;
-	}
-}
-
-/**
- * PE_SRC_Send_Capabilities
- */
-static void pe_src_send_capabilities_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send PD Capabilities message */
-	send_source_cap(port);
-	pe_sender_response_msg_entry(port);
-
-	/* Increment CapsCounter */
-	pe[port].caps_counter++;
-}
-
-static void pe_src_send_capabilities_run(int port)
-{
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Handle Discarded message
-	 *	PE_SNK/SRC_READY if DPM_REQUEST
-	 *	PE_SEND_SOFT_RESET otherwise
-	 */
-	if (msg_check == PE_MSG_DPM_DISCARDED) {
-		set_state_pe(port, PE_SRC_READY);
-		return;
-	} else if (msg_check == PE_MSG_DISCARDED) {
-		pe_send_soft_reset(port, TCPCI_MSG_SOP);
-		return;
-	}
-
-	/*
-	 * Handle message that was just sent
-	 */
-	if (msg_check == PE_MSG_SEND_COMPLETED) {
-		/*
-		 * If a GoodCRC Message is received then the Policy Engine
-		 * Shall:
-		 *  1) Stop the NoResponseTimer.
-		 *  2) Reset the HardResetCounter and CapsCounter to zero.
-		 *  3) Initialize and run the SenderResponseTimer.
-		 */
-		/* Stop the NoResponseTimer */
-		pd_timer_disable(port, PE_TIMER_NO_RESPONSE);
-
-		/* Reset the HardResetCounter to zero */
-		pe[port].hard_reset_counter = 0;
-
-		/* Reset the CapsCounter to zero */
-		pe[port].caps_counter = 0;
-	}
-
-	/*
-	 * Transition to the PE_SRC_Negotiate_Capability state when:
-	 *  1) A Request Message is received from the Sink
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/*
-		 * Request Message Received?
-		 */
-		if (PD_HEADER_CNT(rx_emsg[port].header) > 0 &&
-			PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_REQUEST) {
-
-			/*
-			 * Set to highest revision supported by both
-			 * ports.
-			 */
-			prl_set_rev(port, TCPCI_MSG_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
-
-			set_cable_rev(port);
-
-			/* We are PD connected */
-			PE_SET_FLAG(port, PE_FLAGS_PD_CONNECTION);
-			tc_pd_connection(port, 1);
-
-			/*
-			 * Handle the Sink Request in
-			 * PE_SRC_Negotiate_Capability state
-			 */
-			set_state_pe(port, PE_SRC_NEGOTIATE_CAPABILITY);
-			return;
-		}
-
-		/*
-		 * We have a Protocol Error.
-		 *	PE_SEND_SOFT_RESET
-		 */
-		pe_send_soft_reset(port,
-				   PD_HEADER_GET_SOP(rx_emsg[port].header));
-		return;
-	}
-
-	/*
-	 * Transition to the PE_SRC_Discovery state when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are presently not Connected
-	 *
-	 * Send soft reset when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are already Connected
-	 *
-	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State and section
-	 * 8.3.3.2.3 PE_SRC_Send_Capabilities State.
-	 *
-	 * NOTE: The PE_FLAGS_PROTOCOL_ERROR is set if a GoodCRC Message
-	 *       is not received.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION))
-			set_state_pe(port, PE_SRC_DISCOVERY);
-		else
-			pe_send_soft_reset(port, TCPCI_MSG_SOP);
-		return;
-	}
-
-	/*
-	 * Transition to the PE_SRC_Disabled state when:
-	 *  1) The Port Partners have not been PD Connected
-	 *  2) The NoResponseTimer times out
-	 *  3) And the HardResetCounter > nHardResetCount.
-	 *
-	 * Transition to the Error Recovery state when:
-	 *  1) The Port Partners have previously been PD Connected
-	 *  2) The NoResponseTimer times out
-	 *  3) And the HardResetCounter > nHardResetCount.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_NO_RESPONSE)) {
-		if (pe[port].hard_reset_counter <= N_HARD_RESET_COUNT)
-			set_state_pe(port, PE_SRC_HARD_RESET);
-		else if (PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION))
-			set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
-		else
-			set_state_pe(port, PE_SRC_DISABLED);
-		return;
-	}
-
-	/*
-	 * Transition to the PE_SRC_Hard_Reset state when:
-	 *  1) The SenderResponseTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
-		set_state_pe(port, PE_SRC_HARD_RESET);
-		return;
-	}
-}
-
-static void pe_src_send_capabilities_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/**
- * PE_SRC_Negotiate_Capability
- */
-static void pe_src_negotiate_capability_entry(int port)
-{
-	uint32_t payload;
-
-	print_current_state(port);
-
-	/* Get message payload */
-	payload = *(uint32_t *)(&rx_emsg[port].buf);
-
-	/*
-	 * Evaluate the Request from the Attached Sink
-	 */
-
-	/*
-	 * Transition to the PE_SRC_Capability_Response state when:
-	 *  1) The Request cannot be met.
-	 *  2) Or the Request can be met later from the Power Reserve
-	 *
-	 * Transition to the PE_SRC_Transition_Supply state when:
-	 *  1) The Request can be met
-	 *
-	 */
-	if (pd_check_requested_voltage(payload, port) != EC_SUCCESS) {
-		set_state_pe(port, PE_SRC_CAPABILITY_RESPONSE);
-	} else {
-		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		pe[port].requested_idx = RDO_POS(payload);
-		set_state_pe(port, PE_SRC_TRANSITION_SUPPLY);
-	}
-}
-
-/**
- * PE_SRC_Transition_Supply
- */
-static void pe_src_transition_supply_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a GotoMin Message or otherwise an Accept Message */
-	if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	} else {
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GOTO_MIN);
-	}
-}
-
-static void pe_src_transition_supply_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Ready state when:
-	 *  1) The power supply is ready.
-	 *
-	 *  NOTE: This code block is executed twice:
-	 *        First Pass)
-	 *            When PE_FLAGS_TX_COMPLETE is set due to the
-	 *            PD_CTRL_ACCEPT or PD_CTRL_GOTO_MIN messages
-	 *            being sent.
-	 *
-	 *        Second Pass)
-	 *            When PE_FLAGS_TX_COMPLETE is set due to the
-	 *            PD_CTRL_PS_RDY message being sent.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/*
-		 * NOTE: If a message was received,
-		 * pe_src_ready state will handle it.
-		 */
-
-		if (PE_CHK_FLAG(port, PE_FLAGS_PS_READY)) {
-			PE_CLR_FLAG(port, PE_FLAGS_PS_READY);
-
-			/*
-			 * Set first message flag to trigger a wait and add
-			 * jitter delay when operating in PD2.0 mode. Skip
-			 * if we already have a contract.
-			 */
-			if (!pe_is_explicit_contract(port)) {
-				PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
-				pd_timer_disable(port,
-						PE_TIMER_WAIT_AND_ADD_JITTER);
-			}
-
-			/* NOTE: Second pass through this code block */
-			/* Explicit Contract is now in place */
-			pe_set_explicit_contract(port);
-
-			/*
-			 * Setup to get Device Policy Manager to request
-			 * Source Capabilities, if needed, for possible
-			 * PR_Swap.  Get the number directly to avoid re-probing
-			 * if the partner generated an error and left -1 for the
-			 * count.
-			 */
-			if (pe[port].src_cap_cnt == 0)
-				pd_dpm_request(port, DPM_REQUEST_GET_SRC_CAPS);
-
-			set_state_pe(port, PE_SRC_READY);
-		} else {
-			/* NOTE: First pass through this code block */
-			/* Wait for tSrcTransition before changing supply. */
-			pd_timer_enable(port, PE_TIMER_SRC_TRANSITION,
-					PD_T_SRC_TRANSITION);
-		}
-
-		return;
-	}
-
-	if (pd_timer_is_expired(port, PE_TIMER_SRC_TRANSITION)) {
-		pd_timer_disable(port, PE_TIMER_SRC_TRANSITION);
-		/* Transition power supply and send PS_RDY. */
-		pd_transition_voltage(pe[port].requested_idx);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
-		PE_SET_FLAG(port, PE_FLAGS_PS_READY);
-	}
-
-	/*
-	 * Transition to the PE_SRC_Hard_Reset state when:
-	 *  1) A Protocol Error occurs.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		set_state_pe(port, PE_SRC_HARD_RESET);
-	}
-}
-
-static void pe_src_transition_supply_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_SRC_TRANSITION);
-}
-
-/*
- * Transitions state after receiving a Not Supported extended message. Under
- * appropriate conditions, transitions to a PE_{SRC,SNK}_Chunk_Received.
- */
-static void extended_message_not_supported(int port, uint32_t *payload)
-{
-	uint16_t ext_header = GET_EXT_HEADER(*payload);
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PD_EXT_HEADER_CHUNKED(ext_header) &&
-			PD_EXT_HEADER_DATA_SIZE(ext_header) >
-			PD_MAX_EXTENDED_MSG_CHUNK_LEN) {
-		set_state_pe(port,
-				pe[port].power_role == PD_ROLE_SOURCE ?
-				PE_SRC_CHUNK_RECEIVED : PE_SNK_CHUNK_RECEIVED);
-		return;
-	}
-
-	set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-}
-
-/**
- * PE_SRC_Ready
- */
-static void pe_src_ready_entry(int port)
-{
-	print_current_state(port);
-
-	/* Ensure any message send flags are cleaned up */
-	PE_CLR_FLAG(port, PE_FLAGS_READY_CLR);
-
-	/* Clear DPM Current Request */
-	pe[port].dpm_curr_request = 0;
-
-	/*
-	 * Wait and add jitter if we are operating in PD2.0 mode and no messages
-	 * have been sent since enter this state.
-	 */
-	pe_update_wait_and_add_jitter_timer(port);
-}
-
-static void pe_src_ready_run(int port)
-{
-	/*
-	 * Handle incoming messages before discovery and DPMs other than hard
-	 * reset
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint8_t ext = PD_HEADER_EXT(rx_emsg[port].header);
-		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/* Extended Message Requests */
-		if (ext > 0) {
-			switch (type) {
-#if defined(CONFIG_USB_PD_EXTENDED_MESSAGES) && defined(CONFIG_BATTERY)
-			case PD_EXT_GET_BATTERY_CAP:
-				set_state_pe(port, PE_GIVE_BATTERY_CAP);
-				break;
-			case PD_EXT_GET_BATTERY_STATUS:
-				set_state_pe(port, PE_GIVE_BATTERY_STATUS);
-				break;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES && CONFIG_BATTERY */
-			default:
-				extended_message_not_supported(port, payload);
-			}
-			return;
-		}
-		/* Data Message Requests */
-		else if (cnt > 0) {
-			switch (type) {
-			case PD_DATA_REQUEST:
-				set_state_pe(port, PE_SRC_NEGOTIATE_CAPABILITY);
-				return;
-			case PD_DATA_SINK_CAP:
-				break;
-			case PD_DATA_VENDOR_DEF:
-				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
-					if (PD_VDO_SVDM(*payload)) {
-						set_state_pe(port,
-							PE_VDM_RESPONSE);
-					} else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
-				}
-				return;
-			case PD_DATA_BIST:
-				set_state_pe(port, PE_BIST_TX);
-				return;
-			default:
-				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-				return;
-			}
-		}
-		/* Control Message Requests */
-		else {
-			switch (type) {
-			case PD_CTRL_GOOD_CRC:
-				break;
-			case PD_CTRL_NOT_SUPPORTED:
-				break;
-			case PD_CTRL_PING:
-				break;
-			case PD_CTRL_GET_SOURCE_CAP:
-				set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-				return;
-			case PD_CTRL_GET_SINK_CAP:
-				set_state_pe(port, PE_SNK_GIVE_SINK_CAP);
-				return;
-			case PD_CTRL_GOTO_MIN:
-				break;
-			case PD_CTRL_PR_SWAP:
-				set_state_pe(port,
-					PE_PRS_SRC_SNK_EVALUATE_SWAP);
-				return;
-			case PD_CTRL_DR_SWAP:
-				if (PE_CHK_FLAG(port,
-						PE_FLAGS_MODAL_OPERATION)) {
-					set_state_pe(port, PE_SRC_HARD_RESET);
-					return;
-				}
-
-				set_state_pe(port, PE_DRS_EVALUATE_SWAP);
-				return;
-			case PD_CTRL_VCONN_SWAP:
-				if (IS_ENABLED(CONFIG_USBC_VCONN))
-					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
-				else
-					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
-				return;
-			/*
-			 * USB PD 3.0 6.8.1:
-			 * Receiving an unexpected message shall be responded
-			 * to with a soft reset message.
-			 */
-			case PD_CTRL_ACCEPT:
-			case PD_CTRL_REJECT:
-			case PD_CTRL_WAIT:
-			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
-				return;
-			/*
-			 * Receiving an unknown or unsupported message
-			 * shall be responded to with a not supported message.
-			 */
-			default:
-				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-				return;
-			}
-		}
-	}
-
-	/*
-	 * Make sure the PRL layer isn't busy with receiving or transmitting
-	 * chunked messages before attempting to transmit a new message.
-	 */
-	if (prl_is_busy(port))
-		return;
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE);
-		set_state_pe(port, PE_VDM_REQUEST_DPM);
-		return;
-	}
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_WAITING_PR_SWAP) &&
-	    pd_timer_is_expired(port, PE_TIMER_PR_SWAP_WAIT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_WAITING_PR_SWAP);
-		PE_SET_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
-	}
-
-	if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) ||
-	    pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
-
-		PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG);
-		pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
-
-		/*
-		 * Handle Device Policy Manager Requests
-		 */
-		if (source_dpm_requests(port))
-			return;
-
-		/*
-		 * Attempt discovery if possible, and return if state was
-		 * changed for that discovery.
-		 */
-		if (pe_attempt_port_discovery(port))
-			return;
-
-		/* No DPM requests; attempt mode entry/exit if needed */
-		dpm_run(port);
-	}
-}
-
-/**
- * PE_SRC_Disabled
- */
-static void pe_src_disabled_entry(int port)
-{
-	print_current_state(port);
-
-	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
-						is_vpd_ct_supported(port)) {
-		/*
-		 * Inform the Device Policy Manager that a Charge-Through VCONN
-		 * Powered Device was detected.
-		 */
-		tc_ctvpd_detected(port);
-	}
-
-	if (pd_get_power_role(port) == PD_ROLE_SOURCE)
-		dpm_add_non_pd_sink(port);
-
-	/*
-	 * Unresponsive to USB Power Delivery messaging, but not to Hard Reset
-	 * Signaling. See pe_got_hard_reset
-	 */
-}
-
-/**
- * PE_SRC_Capability_Response
- */
-static void pe_src_capability_response_entry(int port)
-{
-	print_current_state(port);
-
-	/* NOTE: Wait messaging should be implemented. */
-
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-}
-
-static void pe_src_capability_response_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Ready state when:
-	 *  1) There is an Explicit Contract and
-	 *  2) A Reject Message has been sent and the present Contract is still
-	 *     Valid or
-	 *  3) A Wait Message has been sent.
-	 *
-	 * Transition to the PE_SRC_Hard_Reset state when:
-	 *  1) There is an Explicit Contract and
-	 *  2) The Reject Message has been sent and the present
-	 *     Contract is Invalid
-	 *
-	 * Transition to the PE_SRC_Wait_New_Capabilities state when:
-	 *  1) There is no Explicit Contract and
-	 *  2) A Reject Message has been sent or
-	 *  3) A Wait Message has been sent.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT))
-			/*
-			 * NOTE: The src capabilities listed in
-			 *       board/xxx/usb_pd_policy.c will not
-			 *       change so the present contract will
-			 *       never be invalid.
-			 */
-			set_state_pe(port, PE_SRC_READY);
-		else
-			/*
-			 * NOTE: The src capabilities listed in
-			 *       board/xxx/usb_pd_policy.c will not
-			 *       change, so no need to resending them
-			 *       again. Transition to disabled state.
-			 */
-			set_state_pe(port, PE_SRC_DISABLED);
-	}
-}
-
-/**
- * PE_SRC_Hard_Reset
- */
-static void pe_src_hard_reset_entry(int port)
-{
-	print_current_state(port);
-
-	/* Generate Hard Reset Signal */
-	prl_execute_hard_reset(port);
-
-	/* Increment the HardResetCounter */
-	pe[port].hard_reset_counter++;
-
-	/* Start NoResponseTimer */
-	pd_timer_enable(port, PE_TIMER_NO_RESPONSE, PD_T_NO_RESPONSE);
-
-	/* Start PSHardResetTimer */
-	pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET);
-
-	/* Clear error flags */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_NAKED |
-			  PE_FLAGS_PROTOCOL_ERROR |
-			  PE_FLAGS_VDM_REQUEST_BUSY);
-}
-
-static void pe_src_hard_reset_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Transition_to_default state when:
-	 *  1) The PSHardResetTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_HARD_RESET))
-		set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
-}
-
-static void pe_src_hard_reset_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_HARD_RESET);
-}
-
-/**
- * PE_SRC_Hard_Reset_Received
- */
-static void pe_src_hard_reset_received_entry(int port)
-{
-	print_current_state(port);
-
-	/* Start NoResponseTimer */
-	pd_timer_enable(port, PE_TIMER_NO_RESPONSE, PD_T_NO_RESPONSE);
-
-	/* Start PSHardResetTimer */
-	pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET);
-}
-
-static void pe_src_hard_reset_received_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Transition_to_default state when:
-	 *  1) The PSHardResetTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_HARD_RESET))
-		set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
-}
-
-static void pe_src_hard_reset_received_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_HARD_RESET);
-}
-
-/**
- * PE_SRC_Transition_To_Default
- */
-static void pe_src_transition_to_default_entry(int port)
-{
-	print_current_state(port);
-
-	/* Reset flags */
-	pe[port].flags = 0;
-
-	/* Reset DPM Request */
-	pe[port].dpm_request = 0;
-
-	/*
-	 * Request Device Policy Manager to request power
-	 * supply Hard Resets to vSafe5V via vSafe0V
-	 * Reset local HW
-	 * Request Device Policy Manager to set Port Data
-	 * Role to DFP and turn off VCONN
-	 */
-	tc_hard_reset_request(port);
-}
-
-static void pe_src_transition_to_default_run(int port)
-{
-	/*
-	 * Transition to the PE_SRC_Startup state when:
-	 *   1) The power supply has reached the default level.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE);
-		/* Inform the Protocol Layer that the Hard Reset is complete */
-		prl_hard_reset_complete(port);
-		set_state_pe(port, PE_SRC_STARTUP);
-	}
-}
-
-/**
- * PE_SNK_Startup State
- */
-static void pe_snk_startup_entry(int port)
-{
-	print_current_state(port);
-
-	/* Reset the protocol layer */
-	prl_reset_soft(port);
-
-	/* Set initial data role */
-	pe[port].data_role = pd_get_data_role(port);
-
-	/* Set initial power role */
-	pe[port].power_role = PD_ROLE_SINK;
-
-	/* Invalidate explicit contract */
-	pe_invalidate_explicit_contract(port);
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
-		/*
-		 * Protocol layer reset clears the message IDs for all SOP
-		 * types. Indicate that a SOP' soft reset is required before any
-		 * other messages are sent to the cable.
-		 *
-		 * Note that other paths into this state are for the initial
-		 * connection and for a hard reset. In both cases the cable
-		 * should also automatically clear the message IDs so don't
-		 * generate an SOP' soft reset for those cases. Sending
-		 * unnecessary SOP' soft resets causes bad behavior with
-		 * some devices. See b/179325862.
-		 */
-		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
-
-		/*
-		 * Some port partners may violate spec and attempt to
-		 * communicate with the cable after power role swaps, despite
-		 * not being Vconn source.  Disable our SOP' receiving here to
-		 * avoid GoodCRC-ing any erroneous cable probes, and re-enable
-		 * after our contract is in place.
-		 */
-		if (tc_is_vconn_src(port))
-			tcpm_sop_prime_enable(port, false);
-
-		dpm_remove_sink(port);
-	} else {
-		/*
-		 * Set DiscoverIdentityTimer to trigger when we enter
-		 * snk_ready for the first time.
-		 */
-		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, 0);
-
-		/* Clear port discovery/mode flags */
-		pd_dfp_discovery_init(port);
-		pd_dfp_mode_init(port);
-		pe[port].discover_identity_counter = 0;
-
-		/* Reset dr swap attempt counter */
-		pe[port].dr_swap_attempt_counter = 0;
-
-		/* Reset VCONN swap counter */
-		pe[port].vconn_swap_counter = 0;
-		/*
-		 * TODO: POLICY decision:
-		 * Mark that we'd like to try being Vconn source and DFP
-		 */
-		PE_SET_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
-		PE_SET_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
-	}
-
-	/*
-	 * Request sink caps for FRS, output power consideration, or reporting
-	 * to the AP through host commands.
-	 *
-	 * On entry to the PE_SNK_Ready state if the Sink supports Fast Role
-	 * Swap, then the Policy Engine Shall do the following:
-	 * - Send a Get_Sink_Cap Message
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) ||
-					CONFIG_USB_PD_3A_PORTS > 0 ||
-					IS_ENABLED(CONFIG_USB_PD_FRS))
-		pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
-
-}
-
-static void pe_snk_startup_run(int port)
-{
-	/* Wait until protocol layer is running */
-	if (!prl_is_running(port))
-		return;
-
-	/*
-	 * Once the reset process completes, the Policy Engine Shall
-	 * transition to the PE_SNK_Discovery state
-	 */
-	set_state_pe(port, PE_SNK_DISCOVERY);
-}
-
-/**
- * PE_SNK_Discovery State
- */
-static void pe_snk_discovery_entry(int port)
-{
-	print_current_state(port);
-}
-
-static void pe_snk_discovery_run(int port)
-{
-	/*
-	 * Transition to the PE_SNK_Wait_for_Capabilities state when:
-	 *   1) VBUS has been detected
-	 */
-	if (!pd_check_vbus_level(port, VBUS_REMOVED))
-		set_state_pe(port, PE_SNK_WAIT_FOR_CAPABILITIES);
-}
-
-/**
- * PE_SNK_Wait_For_Capabilities State
- */
-static void pe_snk_wait_for_capabilities_entry(int port)
-{
-	print_current_state(port);
-
-	/* Initialize and start the SinkWaitCapTimer */
-	pd_timer_enable(port, PE_TIMER_TIMEOUT, PD_T_SINK_WAIT_CAP);
-}
-
-static void pe_snk_wait_for_capabilities_run(int port)
-{
-	uint8_t type;
-	uint8_t cnt;
-	uint8_t ext;
-
-	/*
-	 * Transition to the PE_SNK_Evaluate_Capability state when:
-	 *  1) A Source_Capabilities Message is received.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt > 0) && (type == PD_DATA_SOURCE_CAP)) {
-			set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
-			return;
-		}
-	}
-
-	/* When the SinkWaitCapTimer times out, perform a Hard Reset. */
-	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
-		PE_SET_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT);
-		set_state_pe(port, PE_SNK_HARD_RESET);
-	}
-}
-
-static void pe_snk_wait_for_capabilities_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_TIMEOUT);
-}
-
-/**
- * PE_SNK_Evaluate_Capability State
- */
-static void pe_snk_evaluate_capability_entry(int port)
-{
-	uint32_t *pdo = (uint32_t *)rx_emsg[port].buf;
-	uint32_t num = rx_emsg[port].len >> 2;
-
-	print_current_state(port);
-
-	/* Reset Hard Reset counter to zero */
-	pe[port].hard_reset_counter = 0;
-
-	/* Set to highest revision supported by both ports. */
-	prl_set_rev(port, TCPCI_MSG_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
-
-	set_cable_rev(port);
-
-	/* Parse source caps if they have changed */
-	if (pe[port].src_cap_cnt != num ||
-	    memcmp(pdo, pe[port].src_caps, num << 2)) {
-		/*
-		 * If port policy preference is to be a power role source,
-		 * then request a power role swap.  If we'd previously queued a
-		 * PR swap but can now charge from this device, clear it.
-		 */
-		if (!pd_can_charge_from_device(port, num, pdo))
-			pd_request_power_swap(port);
-		else
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
-	}
-
-	pe_update_src_pdo_flags(port, num, pdo);
-	pd_set_src_caps(port, num, pdo);
-
-	/* Evaluate the options based on supplied capabilities */
-	pd_process_source_cap(port, pe[port].src_cap_cnt, pe[port].src_caps);
-
-	/* Device Policy Response Received */
-	set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
-
-#ifdef HAS_TASK_DPS
-	/* Wake DPS task to evaluate the SrcCaps */
-	task_wake(TASK_ID_DPS);
-#endif
-}
-
-/**
- * PE_SNK_Select_Capability State
- */
-static void pe_snk_select_capability_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send Request */
-	pe_send_request_msg(port);
-	pe_sender_response_msg_entry(port);
-
-	/* We are PD Connected */
-	PE_SET_FLAG(port, PE_FLAGS_PD_CONNECTION);
-	tc_pd_connection(port, 1);
-}
-
-static void pe_snk_select_capability_run(int port)
-{
-	uint8_t type;
-	uint8_t cnt;
-	enum tcpci_msg_type sop;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Handle discarded message
-	 */
-	if (msg_check & PE_MSG_DISCARDED) {
-		/*
-		 * The sent REQUEST message was discarded.  This can be at
-		 * the start of an AMS or in the middle.  Handle what to
-		 * do based on where we came from.
-		 * 1) SE_SNK_EVALUATE_CAPABILITY: sends SoftReset
-		 * 2) SE_SNK_READY: goes back to SNK Ready
-		 */
-		if (get_last_state_pe(port) == PE_SNK_EVALUATE_CAPABILITY)
-			pe_send_soft_reset(port, TCPCI_MSG_SOP);
-		else
-			set_state_pe(port, PE_SNK_READY);
-		return;
-	}
-
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		/*
-		 * Transition to the PE_SNK_Transition_Sink state when:
-		 *  1) An Accept Message is received from the Source.
-		 *
-		 * Transition to the PE_SNK_Wait_for_Capabilities state when:
-		 *  1) There is no Explicit Contract in place and
-		 *  2) A Reject Message is received from the Source or
-		 *  3) A Wait Message is received from the Source.
-		 *
-		 * Transition to the PE_SNK_Ready state when:
-		 *  1) There is an Explicit Contract in place and
-		 *  2) A Reject Message is received from the Source or
-		 *  3) A Wait Message is received from the Source.
-		 *
-		 * Transition to the PE_SNK_Hard_Reset state when:
-		 *  1) A SenderResponseTimer timeout occurs.
-		 */
-
-		/* Only look at control messages */
-		if (cnt == 0) {
-			/*
-			 * Accept Message Received
-			 */
-			if (type == PD_CTRL_ACCEPT) {
-				/* explicit contract is now in place */
-				pe_set_explicit_contract(port);
-
-				set_state_pe(port, PE_SNK_TRANSITION_SINK);
-
-				return;
-			}
-			/*
-			 * Reject or Wait Message Received
-			 */
-			else if (type == PD_CTRL_REJECT ||
-							type == PD_CTRL_WAIT) {
-				if (type == PD_CTRL_WAIT)
-					PE_SET_FLAG(port, PE_FLAGS_WAIT);
-
-				pd_timer_disable(port, PE_TIMER_SINK_REQUEST);
-
-				/*
-				 * We had a previous explicit contract, so
-				 * transition to PE_SNK_Ready
-				 */
-				if (PE_CHK_FLAG(port,
-						PE_FLAGS_EXPLICIT_CONTRACT))
-					set_state_pe(port, PE_SNK_READY);
-				/*
-				 * No previous explicit contract, so transition
-				 * to PE_SNK_Wait_For_Capabilities
-				 */
-				else
-					set_state_pe(port,
-						PE_SNK_WAIT_FOR_CAPABILITIES);
-				return;
-			}
-			/*
-			 * Unexpected Control Message Received
-			 */
-			else {
-				/* Send Soft Reset */
-				pe_send_soft_reset(port, sop);
-				return;
-			}
-		}
-		/*
-		 * Unexpected Data Message
-		 */
-		else {
-			/* Send Soft Reset */
-			pe_send_soft_reset(port, sop);
-			return;
-		}
-	}
-
-	/* SenderResponsetimer timeout */
-	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		set_state_pe(port, PE_SNK_HARD_RESET);
-}
-
-void pe_snk_select_capability_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/**
- * PE_SNK_Transition_Sink State
- */
-static void pe_snk_transition_sink_entry(int port)
-{
-	print_current_state(port);
-
-	/* Initialize and run PSTransitionTimer */
-	pd_timer_enable(port, PE_TIMER_PS_TRANSITION, PD_T_PS_TRANSITION);
-}
-
-static void pe_snk_transition_sink_run(int port)
-{
-	/*
-	 * Transition to the PE_SNK_Ready state when:
-	 *  1) A PS_RDY Message is received from the Source.
-	 *
-	 * Transition to the PE_SNK_Hard_Reset state when:
-	 *  1) A Protocol Error occurs.
-	 */
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/*
-		 * PS_RDY message received
-		 */
-		if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) &&
-			   (PD_HEADER_TYPE(rx_emsg[port].header) ==
-			   PD_CTRL_PS_RDY)) {
-			/*
-			 * Set first message flag to trigger a wait and add
-			 * jitter delay when operating in PD2.0 mode.
-			 */
-			PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
-			pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
-
-			/*
-			 * If we've successfully completed our new power
-			 * contract, ensure SOP' communication is enabled before
-			 * entering PE_SNK_READY.  It may have been disabled
-			 * during a power role swap to avoid interoperability
-			 * issues with out-of-spec partners.
-			 */
-			if (tc_is_vconn_src(port))
-				tcpm_sop_prime_enable(port, true);
-
-			/*
-			 * Evaluate port's sink caps for FRS current, if
-			 * already available
-			 */
-			if (pd_get_snk_cap_cnt(port) > 0)
-				dpm_evaluate_sink_fixed_pdo(port,
-							*pd_get_snk_caps(port));
-
-			set_state_pe(port, PE_SNK_READY);
-		} else {
-			/*
-			 * Protocol Error
-			 */
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		}
-		return;
-	}
-
-	/*
-	 * Timeout will lead to a Hard Reset
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_TRANSITION) &&
-	    pe[port].hard_reset_counter <= N_HARD_RESET_COUNT) {
-		PE_SET_FLAG(port, PE_FLAGS_PS_TRANSITION_TIMEOUT);
-
-		set_state_pe(port, PE_SNK_HARD_RESET);
-	}
-}
-
-static void pe_snk_transition_sink_exit(int port)
-{
-	/* Transition Sink's power supply to the new power level */
-	pd_set_input_current_limit(port,
-				pe[port].curr_limit, pe[port].supply_voltage);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		/* Set ceiling based on what's negotiated */
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, pe[port].curr_limit);
-
-	pd_timer_disable(port, PE_TIMER_PS_TRANSITION);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DPS))
-		if (charge_manager_get_active_charge_port() == port)
-			dps_update_stabilized_time(port);
-}
-
-
-/**
- * PE_SNK_Ready State
- */
-static void pe_snk_ready_entry(int port)
-{
-	print_current_state(port);
-
-	/* Ensure any message send flags are cleaned up */
-	PE_CLR_FLAG(port, PE_FLAGS_READY_CLR);
-
-	/* Clear DPM Current Request */
-	pe[port].dpm_curr_request = 0;
-
-	/*
-	 * On entry to the PE_SNK_Ready state as the result of a wait,
-	 * then do the following:
-	 *   1) Initialize and run the SinkRequestTimer
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_WAIT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_WAIT);
-		pd_timer_enable(port, PE_TIMER_SINK_REQUEST,
-				PD_T_SINK_REQUEST);
-	}
-
-	/*
-	 * Wait and add jitter if we are operating in PD2.0 mode and no messages
-	 * have been sent since enter this state.
-	 */
-	pe_update_wait_and_add_jitter_timer(port);
-}
-
-static void pe_snk_ready_run(int port)
-{
-	/*
-	 * Handle incoming messages before discovery and DPMs other than hard
-	 * reset
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint8_t ext = PD_HEADER_EXT(rx_emsg[port].header);
-		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/* Extended Message Request */
-		if (ext > 0) {
-			switch (type) {
-#if defined(CONFIG_USB_PD_EXTENDED_MESSAGES) && defined(CONFIG_BATTERY)
-			case PD_EXT_GET_BATTERY_CAP:
-				set_state_pe(port, PE_GIVE_BATTERY_CAP);
-				break;
-			case PD_EXT_GET_BATTERY_STATUS:
-				set_state_pe(port, PE_GIVE_BATTERY_STATUS);
-				break;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES && CONFIG_BATTERY */
-			default:
-				extended_message_not_supported(port, payload);
-			}
-			return;
-		}
-		/* Data Messages */
-		else if (cnt > 0) {
-			switch (type) {
-			case PD_DATA_SOURCE_CAP:
-				set_state_pe(port,
-					PE_SNK_EVALUATE_CAPABILITY);
-				break;
-			case PD_DATA_VENDOR_DEF:
-				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
-					if (PD_VDO_SVDM(*payload))
-						set_state_pe(port,
-							PE_VDM_RESPONSE);
-					else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
-				}
-				break;
-			case PD_DATA_BIST:
-				set_state_pe(port, PE_BIST_TX);
-				break;
-			default:
-				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-			}
-			return;
-		}
-		/* Control Messages */
-		else {
-			switch (type) {
-			case PD_CTRL_GOOD_CRC:
-				/* Do nothing */
-				break;
-			case PD_CTRL_PING:
-				/* Do nothing */
-				break;
-			case PD_CTRL_GET_SOURCE_CAP:
-				set_state_pe(port, PE_DR_SNK_GIVE_SOURCE_CAP);
-				return;
-			case PD_CTRL_GET_SINK_CAP:
-				set_state_pe(port, PE_SNK_GIVE_SINK_CAP);
-				return;
-			case PD_CTRL_GOTO_MIN:
-				set_state_pe(port, PE_SNK_TRANSITION_SINK);
-				return;
-			case PD_CTRL_PR_SWAP:
-				set_state_pe(port,
-						PE_PRS_SNK_SRC_EVALUATE_SWAP);
-				return;
-			case PD_CTRL_DR_SWAP:
-				if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
-					set_state_pe(port, PE_SNK_HARD_RESET);
-				else
-					set_state_pe(port,
-							PE_DRS_EVALUATE_SWAP);
-				return;
-			case PD_CTRL_VCONN_SWAP:
-				if (IS_ENABLED(CONFIG_USBC_VCONN))
-					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
-				else
-					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
-				return;
-			case PD_CTRL_NOT_SUPPORTED:
-				/* Do nothing */
-				break;
-			/*
-			 * USB PD 3.0 6.8.1:
-			 * Receiving an unexpected message shall be responded
-			 * to with a soft reset message.
-			 */
-			case PD_CTRL_ACCEPT:
-			case PD_CTRL_REJECT:
-			case PD_CTRL_WAIT:
-			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
-				return;
-			/*
-			 * Receiving an unknown or unsupported message
-			 * shall be responded to with a not supported message.
-			 */
-			default:
-				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-				return;
-			}
-		}
-	}
-
-	/*
-	 * Make sure the PRL layer isn't busy with receiving or transmitting
-	 * chunked messages before attempting to transmit a new message.
-	 */
-	if (prl_is_busy(port))
-		return;
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE);
-		set_state_pe(port, PE_VDM_REQUEST_DPM);
-		return;
-	}
-
-	if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) ||
-	    pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
-		PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG);
-		pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
-
-		if (pd_timer_is_expired(port, PE_TIMER_SINK_REQUEST)) {
-			pd_timer_disable(port, PE_TIMER_SINK_REQUEST);
-			set_state_pe(port, PE_SNK_SELECT_CAPABILITY);
-			return;
-		}
-
-		/*
-		 * Handle Device Policy Manager Requests
-		 */
-		if (sink_dpm_requests(port))
-			return;
-
-		/*
-		 * Attempt discovery if possible, and return if state was
-		 * changed for that discovery.
-		 */
-		if (pe_attempt_port_discovery(port))
-			return;
-
-		/* No DPM requests; attempt mode entry/exit if needed */
-		dpm_run(port);
-
-	}
-}
-
-/**
- * PE_SNK_Hard_Reset
- */
-static void pe_snk_hard_reset_entry(int port)
-{
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-	int batt_soc;
-#endif
-
-	print_current_state(port);
-
-	/*
-	 * Note: If the SinkWaitCapTimer times out and the HardResetCounter is
-	 *       greater than nHardResetCount the Sink Shall assume that the
-	 *       Source is non-responsive.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT) &&
-			pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
-		set_state_pe(port, PE_SRC_DISABLED);
-		return;
-	}
-
-	/*
-	 * If we're about to kill our active charge port and have no battery to
-	 * supply power, disable the PE layer instead.  If we have no battery,
-	 * but we haven't determined our active charge port yet, also avoid
-	 * performing the HardReset.  It might be that this port was our active
-	 * charge port.
-	 *
-	 * Note: On systems without batteries (ex. chromeboxes), it's preferable
-	 * to brown out rather than leave the port only semi-functional for a
-	 * customer.  For systems which should have a battery, this condition is
-	 * not expected to be encountered by a customer.
-	 */
-	if (IS_ENABLED(CONFIG_BATTERY) && (battery_is_present() == BP_NO) &&
-	    IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
-	    ((port == charge_manager_get_active_charge_port() ||
-	     (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) &&
-	    system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) {
-		CPRINTS("C%d: Disabling port to avoid brown out, "
-			"please reboot EC to enable port again", port);
-		set_state_pe(port, PE_SRC_DISABLED);
-		return;
-
-	}
-
-#ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
-	/*
-	 * If the battery has not met a configured safe level for hard
-	 * resets, set state to PE_SRC_Disabled as a hard
-	 * reset could brown out the board.
-	 * Note this may mean that high-power chargers will stay at
-	 * 15W until a reset is sent, depending on boot timing.
-	 *
-	 * PE_FLAGS_SNK_WAITING_BATT flags will be cleared and
-	 * PE state will be switched to PE_SNK_Startup when
-	 * battery reaches CONFIG_USB_PD_RESET_MIN_BATT_SOC.
-	 * See pe_update_waiting_batt_flag() for more details.
-	 */
-	batt_soc = usb_get_battery_soc();
-
-	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
-	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED) {
-		PE_SET_FLAG(port, PE_FLAGS_SNK_WAITING_BATT);
-		CPRINTS("C%d: Battery low %d%%! Stay in disabled state " \
-			"until battery level reaches %d%%", port, batt_soc,
-			CONFIG_USB_PD_RESET_MIN_BATT_SOC);
-		set_state_pe(port, PE_SRC_DISABLED);
-		return;
-	}
-#endif
-
-	PE_CLR_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT |
-			  PE_FLAGS_VDM_REQUEST_NAKED |
-			  PE_FLAGS_PROTOCOL_ERROR |
-			  PE_FLAGS_VDM_REQUEST_BUSY);
-
-	/* Request the generation of Hard Reset Signaling by the PHY Layer */
-	prl_execute_hard_reset(port);
-
-	/* Increment the HardResetCounter */
-	pe[port].hard_reset_counter++;
-
-	/*
-	 * Transition the Sink’s power supply to the new power level if
-	 * PSTransistionTimer timeout occurred.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_PS_TRANSITION_TIMEOUT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PS_TRANSITION_TIMEOUT);
-
-		/* Transition Sink's power supply to the new power level */
-		pd_set_input_current_limit(port, pe[port].curr_limit,
-						pe[port].supply_voltage);
-		if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-			/* Set ceiling based on what's negotiated */
-			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
-							pe[port].curr_limit);
-	}
-}
-
-static void pe_snk_hard_reset_run(int port)
-{
-	/*
-	 * Transition to the PE_SNK_Transition_to_default state when:
-	 *  1) The Hard Reset is complete.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_HARD_RESET_PENDING))
-		return;
-
-	set_state_pe(port, PE_SNK_TRANSITION_TO_DEFAULT);
-}
-
-/**
- * PE_SNK_Transition_to_default
- */
-static void pe_snk_transition_to_default_entry(int port)
-{
-	print_current_state(port);
-
-	/* Reset flags */
-	pe[port].flags = 0;
-
-	/* Reset DPM Request */
-	pe[port].dpm_request = 0;
-
-	/* Inform the TC Layer of Hard Reset */
-	tc_hard_reset_request(port);
-}
-
-static void pe_snk_transition_to_default_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PS_RESET_COMPLETE);
-		/* Inform the Protocol Layer that the Hard Reset is complete */
-		prl_hard_reset_complete(port);
-		set_state_pe(port, PE_SNK_STARTUP);
-	}
-}
-
-/**
- * PE_SNK_Get_Source_Cap
- */
-static void pe_snk_get_source_cap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a Get_Source_Cap Message */
-	tx_emsg[port].len = 0;
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP);
-}
-
-static void pe_snk_get_source_cap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		set_state_pe(port, PE_SNK_READY);
-	}
-}
-
-/**
- * PE_SNK_Send_Soft_Reset and PE_SRC_Send_Soft_Reset
- */
-static void pe_send_soft_reset_entry(int port)
-{
-	print_current_state(port);
-
-	/* Reset Protocol Layer (softly) */
-	prl_reset_soft(port);
-
-	pe_sender_response_msg_entry(port);
-
-	/*
-	 * Mark the temporary timer PE_TIMER_TIMEOUT as expired to limit
-	 * to sending a single SoftReset message.
-	 */
-	pd_timer_enable(port, PE_TIMER_TIMEOUT, 0);
-}
-
-static void pe_send_soft_reset_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/* Wait until protocol layer is running */
-	if (!prl_is_running(port))
-		return;
-
-	/*
-	 * Protocol layer is running, so need to send a single SoftReset.
-	 * Use temporary timer to act as a flag to keep this as a single
-	 * message send.
-	 */
-	if (!pd_timer_is_disabled(port, PE_TIMER_TIMEOUT)) {
-		pd_timer_disable(port, PE_TIMER_TIMEOUT);
-
-		/*
-		 * TODO(b/150614211): Soft reset type should match
-		 * unexpected incoming message type
-		 */
-		/* Send Soft Reset message */
-		send_ctrl_msg(port,
-			pe[port].soft_reset_sop, PD_CTRL_SOFT_RESET);
-
-		return;
-	}
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Handle discarded message
-	 */
-	if (msg_check == PE_MSG_DISCARDED) {
-		pe_set_ready_state(port);
-		return;
-	}
-
-	/*
-	 * Transition to the PE_SNK_Send_Capabilities or
-	 * PE_SRC_Send_Capabilities state when:
-	 *   1) An Accept Message has been received.
-	 */
-	if (msg_check == PE_MSG_SENT &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_ACCEPT)) {
-			if (pe[port].power_role == PD_ROLE_SINK)
-				set_state_pe(port,
-						PE_SNK_WAIT_FOR_CAPABILITIES);
-			else
-				set_state_pe(port,
-						PE_SRC_SEND_CAPABILITIES);
-			return;
-		}
-	}
-
-	/*
-	 * Transition to PE_SNK_Hard_Reset or PE_SRC_Hard_Reset on Sender
-	 * Response Timer Timeout or Protocol Layer or Protocol Error
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
-		return;
-	}
-}
-
-static void pe_send_soft_reset_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-	pd_timer_disable(port, PE_TIMER_TIMEOUT);
-}
-
-/**
- * PE_SNK_Soft_Reset and PE_SNK_Soft_Reset
- */
-static void pe_soft_reset_entry(int port)
-{
-	print_current_state(port);
-
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-}
-
-static void  pe_soft_reset_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_WAIT_FOR_CAPABILITIES);
-		else
-			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-
-		if (pe[port].power_role == PD_ROLE_SINK)
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SRC_HARD_RESET);
-	}
-}
-
-/**
- * PE_SRC_Not_Supported and PE_SNK_Not_Supported
- *
- * 6.7.1 Soft Reset and Protocol Error (Revision 2.0, Version 1.3)
- * An unrecognized or unsupported Message (except for a Structured VDM),
- * received in the PE_SNK_Ready or PE_SRC_Ready states, Shall Not cause
- * a Soft_Reset Message to be generated but instead a Reject Message
- * Shall be generated.
- */
-static void pe_send_not_supported_entry(int port)
-{
-	print_current_state(port);
-
-	/* Request the Protocol Layer to send a Not_Supported Message. */
-	if (prl_get_rev(port, TCPCI_MSG_SOP) > PD_REV20)
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED);
-	else
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-}
-
-static void pe_send_not_supported_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		pe_set_ready_state(port);
-
-	}
-}
-
-/**
- * PE_SRC_Chunk_Received and PE_SNK_Chunk_Received
- *
- * 6.11.2.1.1 Architecture of Device Including Chunking Layer (Revision 3.0,
- * Version 2.0): If a PD Device or Cable Marker has no requirement to handle any
- * message requiring more than one Chunk of any Extended Message, it May omit
- * the Chunking Layer. In this case it Shall implement the
- * ChunkingNotSupportedTimer to ensure compatible operation with partners which
- * support Chunking.
- *
- * See also:
- * 6.6.18.1 ChunkingNotSupportedTimer
- * 8.3.3.6  Not Supported Message State Diagrams
- */
-__maybe_unused static void pe_chunk_received_entry(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-	    IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-		assert(0);
-
-	print_current_state(port);
-	pd_timer_enable(port, PE_TIMER_CHUNKING_NOT_SUPPORTED,
-			PD_T_CHUNKING_NOT_SUPPORTED);
-}
-
-__maybe_unused static void pe_chunk_received_run(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-	    IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-		assert(0);
-
-	if (pd_timer_is_expired(port, PE_TIMER_CHUNKING_NOT_SUPPORTED))
-		set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-}
-
-__maybe_unused static void pe_chunk_received_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_CHUNKING_NOT_SUPPORTED);
-}
-
-/**
- * PE_SRC_Ping
- */
-static void pe_src_ping_entry(int port)
-{
-	print_current_state(port);
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PING);
-}
-
-static void pe_src_ping_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		set_state_pe(port, PE_SRC_READY);
-	}
-}
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-/**
- * PE_Give_Battery_Cap
- */
-static void pe_give_battery_cap_entry(int port)
-{
-	uint8_t *payload = rx_emsg[port].buf;
-	uint16_t *msg = (uint16_t *)tx_emsg[port].buf;
-
-	if (!IS_ENABLED(CONFIG_BATTERY))
-		return;
-	print_current_state(port);
-
-	/* Set VID */
-	msg[BCDB_VID] = USB_VID_GOOGLE;
-
-	/* Set PID */
-	msg[BCDB_PID] = CONFIG_USB_PID;
-
-	if (battery_is_present()) {
-		/*
-		 * We only have one fixed battery,
-		 * so make sure batt cap ref is 0.
-		 * This value is the first byte after the headers.
-		 */
-		if (payload[0] != 0) {
-			/* Invalid battery reference */
-			msg[BCDB_DESIGN_CAP] = 0;
-			msg[BCDB_FULL_CAP] = 0;
-			/* Set invalid battery bit in response bit 0, byte 8 */
-			msg[BCDB_BATT_TYPE] = 1;
-		} else {
-			/*
-			 * The Battery Design Capacity field shall return the
-			 * Battery’s design capacity in tenths of Wh. If the
-			 * Battery is Hot Swappable and is not present, the
-			 * Battery Design Capacity field shall be set to 0. If
-			 * the Battery is unable to report its Design Capacity,
-			 * it shall return 0xFFFF
-			 */
-			msg[BCDB_DESIGN_CAP] = 0xffff;
-
-			/*
-			 * The Battery Last Full Charge Capacity field shall
-			 * return the Battery’s last full charge capacity in
-			 * tenths of Wh. If the Battery is Hot Swappable and
-			 * is not present, the Battery Last Full Charge Capacity
-			 * field shall be set to 0. If the Battery is unable to
-			 * report its Design Capacity, the Battery Last Full
-			 * Charge Capacity field shall be set to 0xFFFF.
-			 */
-			msg[BCDB_FULL_CAP] = 0xffff;
-
-
-			if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
-			    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
-				int design_volt, design_cap, full_cap;
-
-				design_volt = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_DVLT);
-				design_cap = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_DCAP);
-				full_cap = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_LFCC);
-
-				/*
-				 * Wh = (c * v) / 1000000
-				 * 10th of a Wh = Wh * 10
-				 */
-				msg[BCDB_DESIGN_CAP] = DIV_ROUND_NEAREST(
-						(design_cap * design_volt),
-						 100000);
-				/*
-				 * Wh = (c * v) / 1000000
-				 * 10th of a Wh = Wh * 10
-				 */
-				msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST(
-						(design_cap * full_cap),
-						 100000);
-			} else {
-				uint32_t v;
-				uint32_t c;
-
-				if (battery_design_voltage(&v) == 0) {
-					if (battery_design_capacity(&c) == 0) {
-						/*
-						 * Wh = (c * v) / 1000000
-						 * 10th of a Wh = Wh * 10
-						 */
-						msg[BCDB_DESIGN_CAP] =
-							DIV_ROUND_NEAREST(
-							(c * v),
-							 100000);
-					}
-
-					if (battery_full_charge_capacity(&c)
-									== 0) {
-						/*
-						 * Wh = (c * v) / 1000000
-						 * 10th of a Wh = Wh * 10
-						 */
-						msg[BCDB_FULL_CAP] =
-							DIV_ROUND_NEAREST(
-							(c * v),
-							 100000);
-					}
-				}
-
-			}
-			/* Valid battery selected */
-			msg[BCDB_BATT_TYPE] = 0;
-		}
-	} else {
-		/* Battery not present indicated by 0's in the capacity */
-		msg[BCDB_DESIGN_CAP] = 0;
-		msg[BCDB_FULL_CAP] = 0;
-		if (payload[0] != 0)
-			msg[BCDB_BATT_TYPE] = 1;
-		else
-			msg[BCDB_BATT_TYPE] = 0;
-	}
-
-	/* Extended Battery Cap data is 9 bytes */
-	tx_emsg[port].len = 9;
-
-	send_ext_data_msg(port, TCPCI_MSG_SOP, PD_EXT_BATTERY_CAP);
-}
-
-static void pe_give_battery_cap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		pe_set_ready_state(port);
-	}
-}
-
-/**
- * PE_Give_Battery_Status
- */
-static void pe_give_battery_status_entry(int port)
-{
-	uint8_t *payload = rx_emsg[port].buf;
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-
-	if (!IS_ENABLED(CONFIG_BATTERY))
-		return;
-	print_current_state(port);
-
-	if (battery_is_present()) {
-		/*
-		 * We only have one fixed battery,
-		 * so make sure batt cap ref is 0.
-		 * This value is the first byte after the headers.
-		 */
-		if (payload[0] != 0) {
-			/* Invalid battery reference */
-			*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
-			*msg |= BSDO_INVALID;
-		} else {
-			uint32_t v;
-			uint32_t c;
-
-			*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
-
-			if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
-			    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
-				v = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_DVLT);
-				c = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_CAP);
-
-				/*
-				 * Wh = (c * v) / 1000000
-				 * 10th of a Wh = Wh * 10
-				 */
-				*msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-						 100000));
-			} else if (battery_design_voltage(&v) == 0 &&
-				   battery_remaining_capacity(&c) == 0) {
-				/*
-				 * Wh = (c * v) / 1000000
-				 * 10th of a Wh = Wh * 10
-				 */
-				*msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								  100000));
-			}
-
-			/* Battery is present */
-			*msg |= BSDO_PRESENT;
-
-			/*
-			 * For drivers that are not smart battery compliant,
-			 * battery_status() returns EC_ERROR_UNIMPLEMENTED and
-			 * the battery is assumed to be idle.
-			 */
-			if (battery_status(&c) != 0) {
-				*msg |= BSDO_IDLE; /* assume idle */
-			} else {
-				if (c & STATUS_FULLY_CHARGED)
-					/* Fully charged */
-					*msg |= BSDO_IDLE;
-				else if (c & STATUS_DISCHARGING)
-					/* Discharging */
-					*msg |= BSDO_DISCHARGING;
-				/* else battery is charging.*/
-			}
-		}
-	} else {
-		*msg = BSDO_CAP(BSDO_CAP_UNKNOWN);
-		if (payload[0] != 0)
-			*msg |= BSDO_INVALID;
-	}
-
-	/* Battery Status data is 4 bytes */
-	tx_emsg[port].len = 4;
-
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_BATTERY_STATUS);
-}
-
-static void pe_give_battery_status_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		set_state_pe(port, PE_SRC_READY);
-	}
-}
-
-/**
- * PE_SRC_Send_Source_Alert and
- * PE_SNK_Send_Sink_Alert
- */
-static void pe_send_alert_entry(int port)
-{
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-	uint32_t *len = &tx_emsg[port].len;
-
-	print_current_state(port);
-
-	if (pd_build_alert_msg(msg, len, pe[port].power_role) != EC_SUCCESS)
-		pe_set_ready_state(port);
-
-	/* Request the Protocol Layer to send Alert Message. */
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_ALERT);
-}
-
-static void pe_send_alert_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		pe_set_ready_state(port);
-	}
-}
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-/**
- * PE_DRS_Evaluate_Swap
- */
-static void pe_drs_evaluate_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Get evaluation of Data Role Swap request from DPM */
-	if (pd_check_data_swap(port, pe[port].data_role)) {
-		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		/*
-		 * PE_DRS_UFP_DFP_Evaluate_Swap and
-		 * PE_DRS_DFP_UFP_Evaluate_Swap states embedded here.
-		 */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	} else {
-		/*
-		 * PE_DRS_UFP_DFP_Reject_Swap and PE_DRS_DFP_UFP_Reject_Swap
-		 * states embedded here.
-		 */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-	}
-}
-
-static void pe_drs_evaluate_swap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/* Accept Message sent. Transtion to PE_DRS_Change */
-		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
-			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-			set_state_pe(port, PE_DRS_CHANGE);
-		} else {
-			/*
-			 * Message sent. Transition back to PE_SRC_Ready or
-			 * PE_SNK_Ready.
-			 */
-			pe_set_ready_state(port);
-		}
-	}
-}
-
-/**
- * PE_DRS_Change
- */
-static void pe_drs_change_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * PE_DRS_UFP_DFP_Change_to_DFP and PE_DRS_DFP_UFP_Change_to_UFP
-	 * states embedded here.
-	 */
-	/* Request DPM to change port data role */
-	pd_request_data_swap(port);
-}
-
-static void pe_drs_change_run(int port)
-{
-	/* Wait until the data role is changed */
-	if (pe[port].data_role == pd_get_data_role(port))
-		return;
-
-	/* Update the data role */
-	pe[port].data_role = pd_get_data_role(port);
-
-	if (pe[port].data_role == PD_ROLE_DFP)
-		PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
-
-	/*
-	 * Port changed. Transition back to PE_SRC_Ready or
-	 * PE_SNK_Ready.
-	 */
-	pe_set_ready_state(port);
-}
-
-/**
- * PE_DRS_Send_Swap
- */
-static void pe_drs_send_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * PE_DRS_UFP_DFP_Send_Swap and PE_DRS_DFP_UFP_Send_Swap
-	 * states embedded here.
-	 */
-	/* Request the Protocol Layer to send a DR_Swap Message */
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DR_SWAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_drs_send_swap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Transition to PE_DRS_Change when:
-	 *   1) An Accept Message is received.
-	 *
-	 * Transition to PE_SRC_Ready or PE_SNK_Ready state when:
-	 *   1) A Reject Message is received.
-	 *   2) Or a Wait Message is received.
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt == 0)) {
-			if (type == PD_CTRL_ACCEPT) {
-				set_state_pe(port, PE_DRS_CHANGE);
-				return;
-			} else if ((type == PD_CTRL_REJECT) ||
-					(type == PD_CTRL_WAIT) ||
-					(type == PD_CTRL_NOT_SUPPORTED)) {
-				pe_set_ready_state(port);
-				return;
-			}
-		}
-	}
-
-	/*
-	 * Transition to PE_SRC_Ready or PE_SNK_Ready state when:
-	 *   1) the SenderResponseTimer times out.
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		pe_set_ready_state(port);
-}
-
-static void pe_drs_send_swap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/**
- * PE_PRS_SRC_SNK_Evaluate_Swap
- */
-static void pe_prs_src_snk_evaluate_swap_entry(int port)
-{
-	print_current_state(port);
-
-	if (!pd_check_power_swap(port)) {
-		/* PE_PRS_SRC_SNK_Reject_PR_Swap state embedded here */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-	} else {
-		tc_request_power_swap(port);
-		/* PE_PRS_SRC_SNK_Accept_Swap state embedded here */
-		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	}
-}
-
-static void pe_prs_src_snk_evaluate_swap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
-			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-
-			/*
-			 * Clear any pending DPM power role swap request so we
-			 * don't trigger a power role swap request back to src
-			 * power role.
-			 */
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
-			/*
-			 * Power Role Swap OK, transition to
-			 * PE_PRS_SRC_SNK_Transition_to_off
-			 */
-			set_state_pe(port, PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
-		} else {
-			/* Message sent, return to PE_SRC_Ready */
-			set_state_pe(port, PE_SRC_READY);
-		}
-	}
-}
-
-/**
- * PE_PRS_SRC_SNK_Transition_To_Off
- */
-static void pe_prs_src_snk_transition_to_off_entry(int port)
-{
-	print_current_state(port);
-
-	/* Contract is invalid */
-	pe_invalidate_explicit_contract(port);
-
-	/* Tell TypeC to power off the source */
-	tc_src_power_off(port);
-
-	pd_timer_enable(port, PE_TIMER_PS_SOURCE,
-			PD_POWER_SUPPLY_TURN_OFF_DELAY);
-}
-
-static void pe_prs_src_snk_transition_to_off_run(int port)
-{
-	/*
-	 * This is a non-interruptible AMS and power is transitioning - hard
-	 * reset on interruption.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		tc_pr_swap_complete(port, 0);
-		set_state_pe(port, PE_SRC_HARD_RESET);
-	}
-
-	/* Give time for supply to power off */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE) &&
-	    pd_check_vbus_level(port, VBUS_SAFE0V))
-		set_state_pe(port, PE_PRS_SRC_SNK_ASSERT_RD);
-}
-
-static void pe_prs_src_snk_transition_to_off_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-}
-
-/**
- * PE_PRS_SRC_SNK_Assert_Rd
- */
-static void pe_prs_src_snk_assert_rd_entry(int port)
-{
-	print_current_state(port);
-
-	/* Tell TypeC to swap from Attached.SRC to Attached.SNK */
-	tc_prs_src_snk_assert_rd(port);
-}
-
-static void pe_prs_src_snk_assert_rd_run(int port)
-{
-	/* Wait until Rd is asserted */
-	if (tc_is_attached_snk(port))
-		set_state_pe(port, PE_PRS_SRC_SNK_WAIT_SOURCE_ON);
-}
-
-/**
- * PE_PRS_SRC_SNK_Wait_Source_On
- */
-static void pe_prs_src_snk_wait_source_on_entry(int port)
-{
-	print_current_state(port);
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
-}
-
-static void pe_prs_src_snk_wait_source_on_run(int port)
-{
-	if (pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/* Update pe power role */
-		pe[port].power_role = pd_get_power_role(port);
-		pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_ON);
-	}
-
-	/*
-	 * Transition to PE_SNK_Startup when:
-	 *   1) A PS_RDY Message is received.
-	 */
-	if (!pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		int type = PD_HEADER_TYPE(rx_emsg[port].header);
-		int cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		int ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_PS_RDY)) {
-			PE_SET_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
-			set_state_pe(port, PE_SNK_STARTUP);
-		} else {
-			int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-			/*
-			 * USB PD 3.0 6.8.1:
-			 * Receiving an unexpected message shall be responded
-			 * to with a soft reset message.
-			 */
-			pe_send_soft_reset(port, sop);
-		}
-		return;
-	}
-
-	/*
-	 * Transition to ErrorRecovery state when:
-	 *   1) The PSSourceOnTimer times out.
-	 *   2) PS_RDY not sent after retries.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE) ||
-	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-
-		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
-		return;
-	}
-}
-
-static void pe_prs_src_snk_wait_source_on_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
-}
-
-/**
- * PE_PRS_SRC_SNK_Send_Swap
- */
-static void pe_prs_src_snk_send_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Making an attempt to PR_Swap, clear we were possibly waiting */
-	pd_timer_disable(port, PE_TIMER_PR_SWAP_WAIT);
-
-	/* Request the Protocol Layer to send a PR_Swap Message. */
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_prs_src_snk_send_swap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Transition to PE_PRS_SRC_SNK_Transition_To_Off when:
-	 *   1) An Accept Message is received.
-	 *
-	 * Transition to PE_SRC_Ready state when:
-	 *   1) A Reject Message is received.
-	 *   2) Or a Wait Message is received.
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt == 0)) {
-			if (type == PD_CTRL_ACCEPT) {
-				pe[port].src_snk_pr_swap_counter = 0;
-				tc_request_power_swap(port);
-				set_state_pe(port,
-					PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
-			} else if (type == PD_CTRL_REJECT) {
-				pe[port].src_snk_pr_swap_counter = 0;
-				set_state_pe(port, PE_SRC_READY);
-			} else if (type == PD_CTRL_WAIT) {
-				if (pe[port].src_snk_pr_swap_counter <
-				    N_SNK_SRC_PR_SWAP_COUNT) {
-					PE_SET_FLAG(port,
-						PE_FLAGS_WAITING_PR_SWAP);
-					pd_timer_enable(port,
-							PE_TIMER_PR_SWAP_WAIT,
-							PD_T_PR_SWAP_WAIT);
-				}
-				pe[port].src_snk_pr_swap_counter++;
-				set_state_pe(port, PE_SRC_READY);
-			}
-			return;
-		}
-	}
-
-	/*
-	 * Transition to PE_SRC_Ready state when:
-	 *   1) Or the SenderResponseTimer times out.
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		set_state_pe(port, PE_SRC_READY);
-}
-
-static void pe_prs_src_snk_send_swap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/**
- * PE_PRS_SNK_SRC_Evaluate_Swap
- */
-static void pe_prs_snk_src_evaluate_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * Cancel any pending PR swap request due to a received Wait since the
-	 * partner just sent us a PR swap message.
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_WAITING_PR_SWAP);
-	pe[port].src_snk_pr_swap_counter = 0;
-
-	if (!pd_check_power_swap(port)) {
-		/* PE_PRS_SNK_SRC_Reject_Swap state embedded here */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-	} else {
-		tc_request_power_swap(port);
-		/* PE_PRS_SNK_SRC_Accept_Swap state embedded here */
-		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	}
-}
-
-static void pe_prs_snk_src_evaluate_swap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
-			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-
-			/*
-			 * Clear any pending DPM power role swap request so we
-			 * don't trigger a power role swap request back to sink
-			 * power role.
-			 */
-			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_PR_SWAP);
-			/*
-			 * Accept message sent, transition to
-			 * PE_PRS_SNK_SRC_Transition_to_off
-			 */
-			set_state_pe(port, PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
-		} else {
-			/* Message sent, return to PE_SNK_Ready */
-			set_state_pe(port, PE_SNK_READY);
-		}
-	}
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		/*
-		 * Protocol Error occurs while PR swap, this may
-		 * brown out if the port-parnter can't hold VBUS
-		 * for tSrcTransition. Notify TC that we end the PR
-		 * swap and start to watch VBUS.
-		 *
-		 * TODO(b:155181980): issue soft reset on protocol error.
-		 */
-		tc_pr_swap_complete(port, 0);
-	}
-}
-
-/**
- * PE_PRS_SNK_SRC_Transition_To_Off
- * PE_FRS_SNK_SRC_Transition_To_Off
- *
- * NOTE: Shared action code used for Power Role Swap and Fast Role Swap
- */
-static void pe_prs_snk_src_transition_to_off_entry(int port)
-{
-	print_current_state(port);
-
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!pe_in_frs_mode(port))
-		tc_snk_power_off(port);
-
-	pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_OFF);
-}
-
-static void pe_prs_snk_src_transition_to_off_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-
-	/*
-	 * Transition to ErrorRecovery state when:
-	 *   1) The PSSourceOffTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_PS_SOURCE))
-		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
-
-	/*
-	 * Transition to PE_PRS_SNK_SRC_Assert_Rp when:
-	 *   1) An PS_RDY Message is received.
-	 */
-	else if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_PS_RDY)) {
-			/*
-			 * FRS: We are always ready to drive vSafe5v, so just
-			 * skip PE_FRS_SNK_SRC_Vbus_Applied and go direct to
-			 * PE_FRS_SNK_SRC_Assert_Rp
-			 */
-			set_state_pe(port, PE_PRS_SNK_SRC_ASSERT_RP);
-		}
-	}
-}
-
-static void pe_prs_snk_src_transition_to_off_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-}
-
-/**
- * PE_PRS_SNK_SRC_Assert_Rp
- * PE_FRS_SNK_SRC_Assert_Rp
- *
- * NOTE: Shared action code used for Power Role Swap and Fast Role Swap
- */
-static void pe_prs_snk_src_assert_rp_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * Tell TypeC to Power/Fast Role Swap (PRS/FRS) from
-	 * Attached.SNK to Attached.SRC
-	 */
-	tc_prs_snk_src_assert_rp(port);
-}
-
-static void pe_prs_snk_src_assert_rp_run(int port)
-{
-	/* Wait until TypeC is in the Attached.SRC state */
-	if (tc_is_attached_src(port)) {
-		if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!pe_in_frs_mode(port)) {
-			/* Contract is invalid now */
-			pe_invalidate_explicit_contract(port);
-		}
-		set_state_pe(port, PE_PRS_SNK_SRC_SOURCE_ON);
-	}
-}
-
-/**
- * PE_PRS_SNK_SRC_Source_On
- * PE_FRS_SNK_SRC_Source_On
- *
- * NOTE: Shared action code used for Power Role Swap and Fast Role Swap
- */
-static void pe_prs_snk_src_source_on_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * VBUS was enabled when the TypeC state machine entered
-	 * Attached.SRC state
-	 */
-	pd_timer_enable(port, PE_TIMER_PS_SOURCE,
-			PD_POWER_SUPPLY_TURN_ON_DELAY);
-}
-
-static void pe_prs_snk_src_source_on_run(int port)
-{
-	/* Wait until power supply turns on */
-	if (!pd_timer_is_disabled(port, PE_TIMER_PS_SOURCE)) {
-		if (!pd_timer_is_expired(port, PE_TIMER_PS_SOURCE))
-			return;
-
-		/* update pe power role */
-		pe[port].power_role = pd_get_power_role(port);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
-		/* reset timer so PD_CTRL_PS_RDY isn't sent again */
-		pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-	}
-
-	/*
-	 * Transition to ErrorRecovery state when:
-	 *   1) On protocol error
-	 */
-	else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
-	}
-
-	else if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/* Run swap source timer on entry to pe_src_startup */
-		PE_SET_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE);
-		set_state_pe(port, PE_SRC_STARTUP);
-	}
-}
-
-static void pe_prs_snk_src_source_on_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
-}
-
-/**
- * PE_PRS_SNK_SRC_Send_Swap
- * PE_FRS_SNK_SRC_Send_Swap
- *
- * NOTE: Shared action code used for Power Role Swap and Fast Role Swap
- */
-static void pe_prs_snk_src_send_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * PRS_SNK_SRC_SEND_SWAP
-	 *     Request the Protocol Layer to send a PR_Swap Message.
-	 *
-	 * FRS_SNK_SRC_SEND_SWAP
-	 *     Hardware should have turned off sink power and started
-	 *     bringing Vbus to vSafe5.
-	 *     Request the Protocol Layer to send a FR_Swap Message.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		send_ctrl_msg(port,
-			TCPCI_MSG_SOP,
-			pe_in_frs_mode(port)
-				? PD_CTRL_FR_SWAP
-				: PD_CTRL_PR_SWAP);
-	} else {
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP);
-	}
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_prs_snk_src_send_swap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Handle discarded message
-	 */
-	if (msg_check & PE_MSG_DISCARDED) {
-		if (pe_in_frs_mode(port))
-			set_state_pe(port, PE_SNK_HARD_RESET);
-		else
-			set_state_pe(port, PE_SNK_READY);
-		return;
-	}
-
-	/*
-	 * Transition to PE_PRS_SNK_SRC_Transition_to_off when:
-	 *   1) An Accept Message is received.
-	 *
-	 * PRS: Transition to PE_SNK_Ready state when:
-	 * FRS: Transition to ErrorRecovery state when:
-	 *   1) A Reject Message is received.
-	 *   2) Or a Wait Message is received.
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if ((ext == 0) && (cnt == 0)) {
-			if (type == PD_CTRL_ACCEPT) {
-				tc_request_power_swap(port);
-				set_state_pe(port,
-					     PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
-			} else if ((type == PD_CTRL_REJECT) ||
-						(type == PD_CTRL_WAIT)) {
-				if (IS_ENABLED(CONFIG_USB_PD_REV30))
-					set_state_pe(port,
-						pe_in_frs_mode(port)
-					   ? PE_WAIT_FOR_ERROR_RECOVERY
-					   : PE_SNK_READY);
-				else
-					set_state_pe(port, PE_SNK_READY);
-			}
-			return;
-		}
-	}
-
-	/*
-	 * PRS: Transition to PE_SNK_Ready state when:
-	 * FRS: Transition to ErrorRecovery state when:
-	 *   1) The SenderResponseTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
-		if (IS_ENABLED(CONFIG_USB_PD_REV30))
-			set_state_pe(port,
-				pe_in_frs_mode(port)
-				? PE_WAIT_FOR_ERROR_RECOVERY
-				: PE_SNK_READY);
-		else
-			set_state_pe(port, PE_SNK_READY);
-		return;
-	}
-	/*
-	 * FRS Only: Transition to ErrorRecovery state when:
-	 *   2) The FR_Swap Message is not sent after retries (a GoodCRC Message
-	 *      has not been received). A soft reset Shall Not be initiated in
-	 *      this case.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	    pe_in_frs_mode(port) &&
-		PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
-	}
-}
-
-static void pe_prs_snk_src_send_swap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/**
- * PE_FRS_SNK_SRC_Start_AMS
- */
-__maybe_unused static void pe_frs_snk_src_start_ams_entry(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
-		assert(0);
-
-	print_current_state(port);
-
-	/* Contract is invalid now */
-	pe_invalidate_explicit_contract(port);
-
-	/* Inform Protocol Layer this is start of AMS */
-	PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
-
-	/* Shared PRS/FRS code, indicate FRS path */
-	PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
-	set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
-}
-
-/**
- * PE_PRS_FRS_SHARED
- */
-__maybe_unused static void pe_prs_frs_shared_entry(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
-		assert(0);
-
-	/*
-	 * Shared PRS/FRS code, assume PRS path
-	 *
-	 * This is the super state entry. It will be called before
-	 * the first entry state to get into the PRS/FRS path.
-	 * For FRS, PE_FRS_SNK_SRC_START_AMS entry will be called
-	 * after this and that will set for the FRS path.
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
-}
-
-__maybe_unused static void pe_prs_frs_shared_exit(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30))
-		assert(0);
-
-	/*
-	 * Shared PRS/FRS code, when not in shared path
-	 * indicate PRS path
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_PATH);
-}
-
-/**
- * PE_BIST_TX
- */
-static void pe_bist_tx_entry(int port)
-{
-	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
-	uint8_t mode = BIST_MODE(payload[0]);
-	int vbus_mv;
-	int ibus_ma;
-
-	print_current_state(port);
-
-	/* Get the current nominal VBUS value */
-	if (pe[port].power_role == PD_ROLE_SOURCE) {
-		const uint32_t *src_pdo;
-		uint32_t unused;
-
-		dpm_get_source_pdo(&src_pdo, port);
-		pd_extract_pdo_power(src_pdo[pe[port].requested_idx - 1],
-				     &ibus_ma, &vbus_mv, &unused);
-	} else {
-		vbus_mv = pe[port].supply_voltage;
-	}
-
-	/* If VBUS is not at vSafe5V, then don't enter BIST test mode */
-	if (vbus_mv != PD_V_SAFE5V_NOM) {
-		pe_set_ready_state(port);
-		return;
-	}
-
-	if (mode == BIST_CARRIER_MODE_2) {
-		/*
-		 * PE_BIST_Carrier_Mode embedded here.
-		 * See PD 3.0 section 6.4.3.1 BIST Carrier Mode 2: With a BIST
-		 * Carrier Mode 2 BIST Data Object, the UUT Shall send out a
-		 * continuous string of BMC-encoded alternating "1"s and “0�s.
-		 * The UUT Shall exit the Continuous BIST Mode within
-		 * tBISTContMode of this Continuous BIST Mode being enabled.
-		 */
-		send_ctrl_msg(port, TCPCI_MSG_TX_BIST_MODE_2, 0);
-		pd_timer_enable(port, PE_TIMER_BIST_CONT_MODE,
-				PD_T_BIST_CONT_MODE);
-	} else if (mode == BIST_TEST_DATA) {
-		/*
-		 * See PD 3.0 section 6.4.3.2 BIST Test Data:
-		 * With a BIST Test Data BIST Data Object, the UUT Shall return
-		 * a GoodCRC Message and Shall enter a test mode in which it
-		 * sends no further Messages except for GoodCRC Messages in
-		 * response to received Messages.... The test Shall be ended by
-		 * sending Hard Reset Signaling to reset the UUT.
-		 */
-		if (tcpc_set_bist_test_mode(port, true) != EC_SUCCESS)
-			CPRINTS("C%d: Failed to enter BIST Test Mode", port);
-	} else {
-		/* Ignore unsupported BIST messages. */
-		pe_set_ready_state(port);
-		return;
-	}
-}
-
-static void pe_bist_tx_run(int port)
-{
-	if (pd_timer_is_expired(port, PE_TIMER_BIST_CONT_MODE)) {
-		/*
-		 * Entry point to disable BIST in TCPC if that's not already
-		 * handled automatically by the TCPC. Unless this method is
-		 * implemented in a TCPM driver, this function does nothing.
-		 */
-		tcpm_reset_bist_type_2(port);
-
-		if (pe[port].power_role == PD_ROLE_SOURCE)
-			set_state_pe(port, PE_SRC_TRANSITION_TO_DEFAULT);
-		else
-			set_state_pe(port, PE_SNK_TRANSITION_TO_DEFAULT);
-	} else {
-		/*
-		 * We are in test data mode and no further Messages except for
-		 * GoodCRC Messages in response to received Messages will
-		 * be sent.
-		 */
-		if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED))
-			PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-	}
-}
-
-static void pe_bist_tx_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_BIST_CONT_MODE);
-}
-
-/**
- * Give_Sink_Cap Message
- */
-static void pe_snk_give_sink_cap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a Sink_Capabilities Message */
-	tx_emsg[port].len = pd_snk_pdo_cnt * 4;
-	memcpy(tx_emsg[port].buf, (uint8_t *)pd_snk_pdo, tx_emsg[port].len);
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SINK_CAP);
-}
-
-static void pe_snk_give_sink_cap_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		pe_set_ready_state(port);
-		return;
-	}
-
-	if (pe_check_outgoing_discard(port))
-		return;
-}
-
-/**
- * Wait For Error Recovery
- */
-static void pe_wait_for_error_recovery_entry(int port)
-{
-	print_current_state(port);
-	tc_start_error_recovery(port);
-}
-
-static void pe_wait_for_error_recovery_run(int port)
-{
-	/* Stay here until error recovery is complete */
-}
-
-/**
- * PE_Handle_Custom_Vdm_Request
- */
-static void pe_handle_custom_vdm_request_entry(int port)
-{
-	/* Get the message */
-	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
-	int cnt = PD_HEADER_CNT(rx_emsg[port].header);
-	int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-	int rlen = 0;
-	uint32_t *rdata;
-
-	print_current_state(port);
-
-	/* This is an Interruptible AMS */
-	PE_SET_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-
-	rlen = pd_custom_vdm(port, cnt, payload, &rdata);
-	if (rlen > 0) {
-		tx_emsg[port].len = rlen * 4;
-		memcpy(tx_emsg[port].buf, (uint8_t *)rdata, tx_emsg[port].len);
-		send_data_msg(port, sop, PD_DATA_VENDOR_DEF);
-	} else {
-		if (prl_get_rev(port, TCPCI_MSG_SOP) > PD_REV20) {
-			set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-		} else {
-			PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-			pe_set_ready_state(port);
-		}
-	}
-}
-
-static void pe_handle_custom_vdm_request_run(int port)
-{
-	/* Wait for ACCEPT, WAIT or Reject message to send. */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/*
-		 * Message sent. Transition back to
-		 * PE_SRC_Ready or PE_SINK_Ready
-		 */
-		pe_set_ready_state(port);
-	}
-}
-
-static void pe_handle_custom_vdm_request_exit(int port)
-{
-	PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-}
-
-static enum vdm_response_result parse_vdm_response_common(int port)
-{
-	/* Retrieve the message information */
-	uint32_t *payload;
-	int sop;
-	uint8_t type;
-	uint8_t cnt;
-	uint8_t ext;
-
-	if (!PE_CHK_REPLY(port))
-		return VDM_RESULT_WAITING;
-	PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-	payload = (uint32_t *)rx_emsg[port].buf;
-	sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-	type = PD_HEADER_TYPE(rx_emsg[port].header);
-	cnt = PD_HEADER_CNT(rx_emsg[port].header);
-	ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-	if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1
-			&& ext == 0) {
-		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_ACK &&
-				cnt >= pe[port].vdm_ack_min_data_objects) {
-			/* Handle ACKs in state-specific code. */
-			return VDM_RESULT_ACK;
-		} else if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_NAK) {
-			/* Handle NAKs in state-specific code. */
-			return VDM_RESULT_NAK;
-		} else if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_BUSY) {
-			/*
-			 * Don't fill in the discovery field so we re-probe in
-			 * tVDMBusy
-			 */
-			CPRINTS("C%d: Partner BUSY, request will be retried",
-					port);
-			pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
-					PD_T_VDM_BUSY);
-
-			return VDM_RESULT_NO_ACTION;
-		} else if (PD_VDO_CMDT(payload[0]) == CMDT_INIT) {
-			/*
-			 * Unexpected VDM REQ received. Let Src.Ready or
-			 * Snk.Ready handle it.
-			 */
-			PE_SET_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-			return VDM_RESULT_NO_ACTION;
-		}
-
-		/*
-		 * Partner gave us an incorrect size or command; mark discovery
-		 * as failed.
-		 */
-		CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x",
-				port, rx_emsg[port].header, payload[0]);
-		return VDM_RESULT_NAK;
-	} else if (sop == pe[port].tx_type && ext == 0 && cnt == 0 &&
-			type == PD_CTRL_NOT_SUPPORTED) {
-		/*
-		 * A NAK would be more expected here, but Not Supported is still
-		 * allowed with the same meaning.
-		 */
-		return VDM_RESULT_NAK;
-	}
-
-	/* Unexpected Message Received. Src.Ready or Snk.Ready can handle it. */
-	PE_SET_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-	return VDM_RESULT_NO_ACTION;
-}
-
-/**
- * PE_VDM_SEND_REQUEST
- * Shared parent to manage VDM timer and other shared parts of the VDM request
- * process
- */
-static void pe_vdm_send_request_entry(int port)
-{
-	if (pe[port].tx_type == TCPCI_MSG_INVALID) {
-		if (IS_ENABLED(USB_PD_DEBUG_LABELS))
-			CPRINTS("C%d: %s: Tx type expected to be set, "
-				"returning",
-				port, pe_state_names[get_state_pe(port)]);
-		set_state_pe(port, get_last_state_pe(port));
-		return;
-	}
-
-	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
-	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	    !tc_is_vconn_src(port) && port_discovery_vconn_swap_policy(port,
-		PE_FLAGS_VCONN_SWAP_TO_ON)) {
-		if (port_try_vconn_swap(port))
-			return;
-	}
-
-	/* All VDM sequences are Interruptible */
-	PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS |
-			PE_FLAGS_INTERRUPTIBLE_AMS);
-}
-
-static void pe_vdm_send_request_run(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) &&
-	    pd_timer_is_disabled(port, PE_TIMER_VDM_RESPONSE)) {
-		/* Message was sent */
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		/* Start no response timer */
-		/* TODO(b/155890173): Support DPM-supplied timeout */
-		pd_timer_enable(port, PE_TIMER_VDM_RESPONSE,
-				PD_T_VDM_SNDR_RSP);
-	}
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-		/*
-		 * Go back to ready on first AMS message discard
-		 * (ready states will clear the discard flag)
-		 */
-		pe_set_ready_state(port);
-		return;
-	}
-
-	/*
-	 * Check the VDM timer, child will be responsible for processing
-	 * messages and reacting appropriately to unexpected messages.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_VDM_RESPONSE)) {
-		CPRINTF("VDM %s Response Timeout\n",
-				pe[port].tx_type == TCPCI_MSG_SOP ?
-				"Port" : "Cable");
-		/*
-		 * Flag timeout so child state can mark appropriate discovery
-		 * item as failed.
-		 */
-		PE_SET_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
-
-		set_state_pe(port, get_last_state_pe(port));
-	}
-}
-
-static void pe_vdm_send_request_exit(int port)
-{
-	/*
-	 * Clear TX complete in case child called set_state_pe() before parent
-	 * could process transmission
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-
-	/* Invalidate TX type so it must be set before next call */
-	pe[port].tx_type = TCPCI_MSG_INVALID;
-
-	pd_timer_disable(port, PE_TIMER_VDM_RESPONSE);
-}
-
-/**
- * PE_VDM_IDENTITY_REQUEST_CBL
- * Combination of PE_INIT_PORT_VDM_Identity_Request State specific to the
- * cable and PE_SRC_VDM_Identity_Request State.
- * pe[port].tx_type must be set (to SOP') prior to entry.
- */
-static void pe_vdm_identity_request_cbl_entry(int port)
-{
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-
-	print_current_state(port);
-
-	if (!pe_can_send_sop_prime(port)) {
-		/*
-		 * The parent state already tried to enable SOP' traffic. If it
-		 * is still disabled, there's nothing left to try.
-		 */
-		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		set_state_pe(port, get_last_state_pe(port));
-		return;
-	}
-
-	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
-	tx_emsg[port].len = sizeof(uint32_t);
-
-	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
-
-	pe[port].discover_identity_counter++;
-
-	/*
-	 * Valid DiscoverIdentity responses should have at least 4 objects
-	 * (header, ID header, Cert Stat, Product VDO).
-	 */
-	pe[port].vdm_ack_min_data_objects = 4;
-}
-
-static void pe_vdm_identity_request_cbl_run(int port)
-{
-	/* Retrieve the message information */
-	uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
-	int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-	uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
-	uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-	uint8_t ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-	switch (parse_vdm_response_common(port)) {
-	case VDM_RESULT_WAITING:
-		/*
-		 * The common code didn't parse a message. Handle protocol
-		 * errors; otherwise, continue waiting.
-		 */
-		if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-			/*
-			 * No Good CRC: See section 6.4.4.3.1 - Discover
-			 * Identity.
-			 *
-			 * Discover Identity Command request sent to SOP' Shall
-			 * Not cause a Soft Reset if a GoodCRC Message response
-			 * is not returned since this can indicate a non-PD
-			 * Capable cable.
-			 */
-			PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-			set_state_pe(port, get_last_state_pe(port));
-		}
-		return;
-	case VDM_RESULT_NO_ACTION:
-		/*
-		 * If the received message doesn't change the discovery state,
-		 * there is nothing to do but return to the previous ready
-		 * state.
-		 */
-		if (get_last_state_pe(port) == PE_SRC_DISCOVERY &&
-					(sop != pe[port].tx_type ||
-					 type != PD_DATA_VENDOR_DEF ||
-					 cnt == 0 || ext != 0)) {
-			/*
-			 * Unexpected non-VDM received: Before an explicit
-			 * contract, an unexpected message shall generate a soft
-			 * reset using the SOP* of the incoming message.
-			 */
-			pe_send_soft_reset(port, sop);
-			return;
-		}
-		break;
-	case VDM_RESULT_ACK:
-		/* PE_INIT_PORT_VDM_Identity_ACKed embedded here */
-		dfp_consume_identity(port, sop, cnt, payload);
-
-		/*
-		 * Note: If port partner runs PD 2.0, we must use PD 2.0 to
-		 * communicate with the cable plug when in an explicit contract.
-		 *
-		 * PD Spec Table 6-2: Revision Interoperability during an
-		 * Explicit Contract
-		 */
-		if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20)
-			prl_set_rev(port, sop,
-					PD_HEADER_REV(rx_emsg[port].header));
-		break;
-	case VDM_RESULT_NAK:
-		/* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */
-		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		break;
-	}
-
-	/* Return to calling state (PE_{SRC,SNK}_Ready or PE_SRC_Discovery) */
-	set_state_pe(port, get_last_state_pe(port));
-}
-
-static void pe_vdm_identity_request_cbl_exit(int port)
-{
-	/*
-	 * When cable GoodCRCs but does not reply, down-rev to PD 2.0 and try
-	 * again.
-	 *
-	 * PD 3.0 Rev 2.0 6.2.1.1.5 Specification Revision
-	 *
-	 * "When a Cable Plug does not respond to a Revision 3.0 Discover
-	 * Identity REQ with a Discover Identity ACK or BUSY the Vconn Source
-	 * May repeat steps 1-4 using a Revision 2.0 Discover Identity REQ in
-	 * step 1 before establishing that there is no Cable Plug to
-	 * communicate with"
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
-		prl_set_rev(port, TCPCI_MSG_SOP_PRIME, PD_REV20);
-	}
-
-	/*
-	 * 6.6.15 DiscoverIdentityTimer
-	 *
-	 * No more than nDiscoverIdentityCount Discover Identity Messages
-	 * without a GoodCRC Message response Shall be sent. If no GoodCRC
-	 * Message response is received after nDiscoverIdentityCount Discover
-	 * Identity Command requests have been sent by a Port, the Port Shall
-	 * Not send any further SOP’/SOP’’ Messages.
-	 */
-	if (pe[port].discover_identity_counter >= N_DISCOVER_IDENTITY_COUNT)
-		pd_set_identity_discovery(port, pe[port].tx_type,
-				PD_DISC_FAIL);
-	else if (pe[port].discover_identity_counter ==
-			N_DISCOVER_IDENTITY_PD3_0_LIMIT)
-		/*
-		 * Downgrade to PD 2.0 if the partner hasn't replied before
-		 * all retries are exhausted in case the cable is
-		 * non-compliant about GoodCRC-ing higher revisions
-		 */
-		prl_set_rev(port, TCPCI_MSG_SOP_PRIME, PD_REV20);
-
-	/*
-	 * Set discover identity timer unless BUSY case already did so.
-	 */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_NEEDED
-	    && pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
-		/*
-		 * The tDiscoverIdentity timer is used during an explicit
-		 * contract when discovering whether a cable is PD capable.
-		 *
-		 * Pre-contract, slow the rate Discover Identity commands are
-		 * sent. This permits operation with captive cable devices that
-		 * power the SOP' responder from VBUS instead of VCONN.
-		 */
-		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
-				pe_is_explicit_contract(port)
-					? PD_T_DISCOVER_IDENTITY
-					: PE_T_DISCOVER_IDENTITY_NO_CONTRACT);
-	}
-
-	/* Do not attempt further discovery if identity discovery failed. */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
-		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-	}
-}
-
-/**
- * PE_INIT_PORT_VDM_Identity_Request
- *
- * Specific to SOP requests, as cables require additions for the discover
- * identity counter, must tolerate not receiving a GoodCRC, and need to set the
- * cable revision based on response.
- * pe[port].tx_type must be set (to SOP) prior to entry.
- */
-static void pe_init_port_vdm_identity_request_entry(int port)
-{
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-
-	print_current_state(port);
-
-	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
-	tx_emsg[port].len = sizeof(uint32_t);
-
-	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
-
-	/*
-	 * Valid DiscoverIdentity responses should have at least 4 objects
-	 * (header, ID header, Cert Stat, Product VDO).
-	 */
-	pe[port].vdm_ack_min_data_objects = 4;
-}
-
-static void pe_init_port_vdm_identity_request_run(int port)
-{
-	switch (parse_vdm_response_common(port)) {
-	case VDM_RESULT_WAITING:
-		/* If common code didn't parse a message, continue waiting. */
-		return;
-	case VDM_RESULT_NO_ACTION:
-		/*
-		 * If the received message doesn't change the discovery state,
-		 * there is nothing to do but return to the previous ready
-		 * state.
-		 */
-		break;
-	case VDM_RESULT_ACK: {
-		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
-		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-
-		/* PE_INIT_PORT_VDM_Identity_ACKed embedded here */
-		dfp_consume_identity(port, sop, cnt, payload);
-
-		break;
-		}
-	case VDM_RESULT_NAK:
-		/* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */
-		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		break;
-	}
-
-	/* Return to calling state (PE_{SRC,SNK}_Ready) */
-	set_state_pe(port, get_last_state_pe(port));
-}
-
-static void pe_init_port_vdm_identity_request_exit(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
-		/*
-		 * Mark failure to respond as discovery failure.
-		 *
-		 * For PD 2.0 partners (6.10.3 Applicability of Structured VDM
-		 * Commands Note 3):
-		 *
-		 * If Structured VDMs are not supported, a Structured VDM
-		 * Command received by a DFP or UFP Shall be Ignored.
-		 */
-		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-	}
-
-	/* Do not attempt further discovery if identity discovery failed. */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
-		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-	}
-}
-
-/**
- * PE_INIT_VDM_SVIDs_Request
- *
- * Used for SOP and SOP' requests, selected by pe[port].tx_type prior to entry.
- */
-static void pe_init_vdm_svids_request_entry(int port)
-{
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-
-	print_current_state(port);
-
-	if (pe[port].tx_type == TCPCI_MSG_SOP_PRIME &&
-	    !pe_can_send_sop_prime(port)) {
-		/*
-		 * The parent state already tried to enable SOP' traffic. If it
-		 * is still disabled, there's nothing left to try.
-		 */
-		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		set_state_pe(port, get_last_state_pe(port));
-		return;
-	}
-
-	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_SVID);
-	tx_emsg[port].len = sizeof(uint32_t);
-
-	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
-
-	/*
-	 * Valid Discover SVIDs ACKs should have at least 2 objects (VDM header
-	 * and at least 1 SVID VDO).
-	 */
-	pe[port].vdm_ack_min_data_objects = 2;
-}
-
-static void pe_init_vdm_svids_request_run(int port)
-{
-	switch (parse_vdm_response_common(port)) {
-	case VDM_RESULT_WAITING:
-		/* If common code didn't parse a message, continue waiting. */
-		return;
-	case VDM_RESULT_NO_ACTION:
-		/*
-		 * If the received message doesn't change the discovery state,
-		 * there is nothing to do but return to the previous ready
-		 * state.
-		 */
-		break;
-	case VDM_RESULT_ACK: {
-		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
-		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-
-		/* PE_INIT_VDM_SVIDs_ACKed embedded here */
-		dfp_consume_svids(port, sop, cnt, payload);
-		break;
-		}
-	case VDM_RESULT_NAK:
-		/* PE_INIT_VDM_SVIDs_NAKed embedded here */
-		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		break;
-	}
-
-	/* Return to calling state (PE_{SRC,SNK}_Ready) */
-	set_state_pe(port, get_last_state_pe(port));
-}
-
-static void pe_init_vdm_svids_request_exit(int port)
-{
-	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
-		/*
-		 * Mark failure to respond as discovery failure.
-		 *
-		 * For PD 2.0 partners (6.10.3 Applicability of Structured VDM
-		 * Commands Note 3):
-		 *
-		 * If Structured VDMs are not supported, a Structured VDM
-		 * Command received by a DFP or UFP Shall be Ignored.
-		 */
-		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-	}
-
-	/* If SVID discovery failed, discovery is done at this point */
-	if (pd_get_svids_discovery(port, pe[port].tx_type) == PD_DISC_FAIL)
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-}
-
-/**
- * PE_INIT_VDM_Modes_Request
- *
- * Used for SOP and SOP' requests, selected by pe[port].tx_type prior to entry.
- */
-static void pe_init_vdm_modes_request_entry(int port)
-{
-	uint32_t *msg = (uint32_t *)tx_emsg[port].buf;
-	const struct svid_mode_data *mode_data =
-		pd_get_next_mode(port, pe[port].tx_type);
-	uint16_t svid;
-	/*
-	 * The caller should have checked that there was something to discover
-	 * before entering this state.
-	 */
-	assert(mode_data);
-	assert(mode_data->discovery == PD_DISC_NEEDED);
-	svid = mode_data->svid;
-
-	print_current_state(port);
-
-	if (pe[port].tx_type == TCPCI_MSG_SOP_PRIME &&
-	    !pe_can_send_sop_prime(port)) {
-		/*
-		 * The parent state already tried to enable SOP' traffic. If it
-		 * is still disabled, there's nothing left to try.
-		 */
-		pd_set_modes_discovery(port, pe[port].tx_type, svid,
-				PD_DISC_FAIL);
-		set_state_pe(port, get_last_state_pe(port));
-		return;
-	}
-
-	msg[0] = VDO((uint16_t) svid, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_MODES);
-	tx_emsg[port].len = sizeof(uint32_t);
-
-	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
-
-	/*
-	 * Valid Discover Modes responses should have at least 2 objects (VDM
-	 * header and at least 1 mode VDO).
-	 */
-	pe[port].vdm_ack_min_data_objects = 2;
-}
-
-static void pe_init_vdm_modes_request_run(int port)
-{
-	const struct svid_mode_data *mode_data;
-	uint16_t requested_svid;
-
-	mode_data = pd_get_next_mode(port, pe[port].tx_type);
-
-	assert(mode_data);
-	assert(mode_data->discovery == PD_DISC_NEEDED);
-	requested_svid = mode_data->svid;
-
-	switch (parse_vdm_response_common(port)) {
-	case VDM_RESULT_WAITING:
-		/* If common code didn't parse a message, continue waiting. */
-		return;
-	case VDM_RESULT_NO_ACTION:
-		/*
-		 * If the received message doesn't change the discovery state,
-		 * there is nothing to do but return to the previous ready
-		 * state.
-		 */
-		break;
-	case VDM_RESULT_ACK: {
-		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
-		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
-
-		/*
-		 * Accept ACK if the request and response SVIDs are equal;
-		 * otherwise, treat this as a NAK of the request SVID.
-		 *
-		 * TODO(b:169242812): support valid mode checking in
-		 * dfp_consume_modes.
-		 */
-		if (requested_svid == response_svid) {
-			/* PE_INIT_VDM_Modes_ACKed embedded here */
-			dfp_consume_modes(port, sop, cnt, payload);
-			break;
-		}
-		}
-		/* Fall Through */
-	case VDM_RESULT_NAK:
-		/* PE_INIT_VDM_Modes_NAKed embedded here */
-		pd_set_modes_discovery(port, pe[port].tx_type, requested_svid,
-				PD_DISC_FAIL);
-		break;
-	}
-
-	/* Return to calling state (PE_{SRC,SNK}_Ready) */
-	set_state_pe(port, get_last_state_pe(port));
-}
-
-static void pe_init_vdm_modes_request_exit(int port)
-{
-	if (pd_get_modes_discovery(port, pe[port].tx_type) != PD_DISC_NEEDED)
-		/* Mode discovery done, notify the AP */
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-
-}
-
-/**
- * PE_VDM_REQUEST_DPM
- *
- * Makes a VDM request with contents and SOP* type previously set up by the DPM.
- */
-
-static void pe_vdm_request_dpm_entry(int port)
-{
-	print_current_state(port);
-
-	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
-	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	     !pe_can_send_sop_prime(port)) {
-		/*
-		 * The parent state already tried to enable SOP' traffic. If it
-		 * is still disabled, there's nothing left to try.
-		 */
-		dpm_vdm_naked(port, pe[port].tx_type,
-			      PD_VDO_VID(pe[port].vdm_data[0]),
-			      PD_VDO_CMD(pe[port].vdm_data[0]));
-		set_state_pe(port, get_last_state_pe(port));
-		return;
-	}
-
-	/* Copy Vendor Data Objects (VDOs) into message buffer */
-	if (pe[port].vdm_cnt > 0) {
-		/* Copy data after header */
-		memcpy(&tx_emsg[port].buf,
-			(uint8_t *)pe[port].vdm_data,
-			pe[port].vdm_cnt * 4);
-		/* Update len with the number of VDO bytes */
-		tx_emsg[port].len = pe[port].vdm_cnt * 4;
-	}
-
-	/*
-	 * Clear the VDM nak'ed flag so that each request is
-	 * treated separately (NAKs are handled by the
-	 * DPM layer). Otherwise previous NAKs received will
-	 * cause the state to exit early.
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_NAKED);
-	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
-
-	/*
-	 * In general, valid VDM ACKs must have a VDM header. Other than that,
-	 * ACKs must be validated based on the command and SVID.
-	 */
-	pe[port].vdm_ack_min_data_objects = 1;
-}
-
-static void pe_vdm_request_dpm_run(int port)
-{
-	uint32_t vdm_hdr;
-
-	switch (parse_vdm_response_common(port)) {
-	case VDM_RESULT_WAITING:
-		/*
-		 * USB-PD 3.0 Rev 1.1 - 6.4.4.2.5
-		 * Structured VDM command consists of a command request and a
-		 * command response (ACK, NAK, or BUSY). An exception is made
-		 * for the Attention command which shall have no response.
-		 *
-		 * Since Attention commands do not have an expected reply,
-		 * the SVDM command is complete once the Attention command
-		 * transmit is complete.
-		 */
-		vdm_hdr = pe[port].vdm_data[0];
-		if(PD_VDO_SVDM(vdm_hdr) &&
-		   (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) {
-			if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-				PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-				break;
-			}
-		}
-		/*
-		 * If common code didn't parse a message, and the VDM
-		 * just sent was not an Attention message, then continue
-		 * waiting.
-		 */
-		return;
-	case VDM_RESULT_NO_ACTION:
-		/*
-		 * If the received message doesn't change the discovery state,
-		 * there is nothing to do but return to the previous ready
-		 * state. This includes Attention commands which have no
-		 * expected SVDM response.
-		 */
-		break;
-	case VDM_RESULT_ACK: {
-		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
-		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint16_t svid = PD_VDO_VID(payload[0]);
-		uint8_t vdm_cmd = PD_VDO_CMD(payload[0]);
-
-		/*
-		 * PE initiator VDM-ACKed state for requested VDM, like
-		 * PE_INIT_VDM_FOO_ACKed, embedded here.
-		 */
-		dpm_vdm_acked(port, sop, cnt, payload);
-
-		if (sop == TCPCI_MSG_SOP && svid == USB_SID_DISPLAYPORT &&
-				vdm_cmd == CMD_DP_CONFIG) {
-			PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
-		}
-		break;
-		}
-	case VDM_RESULT_NAK:
-		/*
-		 * PE initiator VDM-NAKed state for requested VDM, like
-		 * PE_INIT_VDM_FOO_NAKed, embedded here.
-		 */
-		PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
-
-		/*
-		 * Because Not Supported messages or response timeouts are
-		 * treated as NAKs, there may not be a NAK message to parse.
-		 * Extract the needed information from the sent VDM.
-		 */
-		dpm_vdm_naked(port, pe[port].tx_type,
-				PD_VDO_VID(pe[port].vdm_data[0]),
-				PD_VDO_CMD(pe[port].vdm_data[0]));
-		break;
-	}
-
-	/* Return to calling state (PE_{SRC,SNK}_Ready) */
-	set_state_pe(port, get_last_state_pe(port));
-}
-
-static void pe_vdm_request_dpm_exit(int port)
-{
-	/*
-	 * Force Tx type to be reset before reentering a VDM state, unless the
-	 * current VDM request will be resumed.
-	 */
-	if (!PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_CONTINUE))
-		pe[port].tx_type = TCPCI_MSG_INVALID;
-}
-
-/**
- * PE_VDM_Response
- */
-static void pe_vdm_response_entry(int port)
-{
-	int vdo_len = 0;
-	uint32_t *rx_payload;
-	uint32_t *tx_payload;
-	uint8_t vdo_cmd;
-	svdm_rsp_func func = NULL;
-
-	print_current_state(port);
-
-	/* This is an Interruptible AMS */
-	PE_SET_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-
-	/* Get the message */
-	rx_payload = (uint32_t *)rx_emsg[port].buf;
-
-	/* Extract VDM command from the VDM header */
-	vdo_cmd = PD_VDO_CMD(rx_payload[0]);
-	/* This must be a command request to proceed further */
-	if (PD_VDO_CMDT(rx_payload[0]) != CMDT_INIT) {
-		CPRINTF("ERR:CMDT:%d:%d\n", PD_VDO_CMDT(rx_payload[0]),
-			vdo_cmd);
-
-		pe_set_ready_state(port);
-		return;
-	}
-
-	tx_payload = (uint32_t *)tx_emsg[port].buf;
-	/*
-	 * Designed in TCPMv1, svdm_response functions use same
-	 * buffer to take received data and overwrite with response
-	 * data. To work with this interface, here copy rx data to
-	 * tx buffer and pass tx_payload to func.
-	 * TODO(b/166455363): change the interface to pass both rx
-	 * and tx buffer.
-	 *
-	 * The SVDM header is dependent on both VDM command request being
-	 * replied to and the result of response function. The SVDM command
-	 * message is copied into tx_payload. tx_payload[0] is the VDM header
-	 * for the response message. The SVDM response function takes the role
-	 * of the DPM layer and will indicate the response type (ACK/NAK/BUSY)
-	 * by its return value (vdo_len)
-	 *    vdo_len > 0  --> ACK
-	 *    vdo_len == 0 --> NAK
-	 *    vdo_len < 0  --> BUSY
-	 */
-	memcpy(tx_payload, rx_payload, PD_HEADER_CNT(rx_emsg[port].header) * 4);
-	/*
-	 * Clear fields in SVDM response message that will be set based on the
-	 * result of the svdm response function.
-	 */
-	tx_payload[0] &= ~VDO_CMDT_MASK;
-	tx_payload[0] &= ~VDO_SVDM_VERS(0x3);
-
-	/* Add SVDM structured version being used */
-	tx_payload[0] |= VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
-
-	/* Use VDM command to select the response handler function */
-	switch (vdo_cmd) {
-	case CMD_DISCOVER_IDENT:
-		func = svdm_rsp.identity;
-		break;
-	case CMD_DISCOVER_SVID:
-		func = svdm_rsp.svids;
-		break;
-	case CMD_DISCOVER_MODES:
-		func = svdm_rsp.modes;
-		break;
-	case CMD_ENTER_MODE:
-		func = svdm_rsp.enter_mode;
-		break;
-	case CMD_DP_STATUS:
-		if (svdm_rsp.amode)
-			func = svdm_rsp.amode->status;
-		break;
-	case CMD_DP_CONFIG:
-		if (svdm_rsp.amode)
-			func = svdm_rsp.amode->config;
-		break;
-	case CMD_EXIT_MODE:
-		func = svdm_rsp.exit_mode;
-		break;
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-	case CMD_ATTENTION:
-		/*
-		 * attention is only SVDM with no response
-		 * (just goodCRC) return zero here.
-		 */
-		dfp_consume_attention(port, rx_payload);
-		pe_set_ready_state(port);
-		return;
-#endif
-	default:
-		CPRINTF("VDO ERR:CMD:%d\n", vdo_cmd);
-	}
-
-	/*
-	 * If the port partner is PD_REV20 and our data role is DFP, we must
-	 * reply to any SVDM command with a NAK. If the SVDM was an Attention
-	 * command, it does not have a response, and exits the function above.
-	 */
-	if (func && (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20 ||
-		     pe[port].data_role == PD_ROLE_UFP)) {
-		/*
-		 * Execute SVDM response function selected above and set the
-		 * correct response type in the VDM header.
-		 */
-		vdo_len = func(port, tx_payload);
-		if (vdo_len > 0) {
-			tx_payload[0] |= VDO_CMDT(CMDT_RSP_ACK);
-			/*
-			 * If command response is an ACK and if the command was
-			 * either enter/exit mode, then update the PE modal flag
-			 * accordingly.
-			 */
-			if (vdo_cmd == CMD_ENTER_MODE)
-				PE_SET_FLAG(port, PE_FLAGS_MODAL_OPERATION);
-			if (vdo_cmd == CMD_EXIT_MODE)
-				PE_CLR_FLAG(port, PE_FLAGS_MODAL_OPERATION);
-		} else if (!vdo_len) {
-			tx_payload[0] |= VDO_CMDT(CMDT_RSP_NAK);
-			vdo_len = 1;
-		} else {
-			tx_payload[0] |= VDO_CMDT(CMDT_RSP_BUSY);
-			vdo_len = 1;
-		}
-	} else {
-		/*
-		 * Received at VDM command which is not supported.  PD 2.0 may
-		 * NAK or ignore the message (see TD.PD.VNDI.E1. VDM Identity
-		 * steps), but PD 3.0 must send Not_Supported (PD 3.0 Ver 2.0 +
-		 * ECNs 2020-12-10 Table 6-64 Response to an incoming
-		 * VDM or TD.PD.VNDI3.E3 VDM Identity steps)
-		 */
-		if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-			set_state_pe(port, PE_SEND_NOT_SUPPORTED);
-			return;
-		}
-		tx_payload[0] |= VDO_CMDT(CMDT_RSP_NAK);
-		vdo_len = 1;
-	}
-
-	/* Send response message. Note len is in bytes, not VDO objects */
-	tx_emsg[port].len = (vdo_len * sizeof(uint32_t));
-	send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF);
-}
-
-static void pe_vdm_response_run(int port)
-{
-	/*
-	 * This state waits for a VDM response message to be sent. Return to the
-	 * ready state once the message has been sent, a protocol error was
-	 * detected, or if the VDM response msg was discarded based on being
-	 * interrupted by another rx message. Since VDM sequences are AMS
-	 * interruptible, there is no need to soft reset regardless of exit
-	 * reason.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) ||
-	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE |
-			    PE_FLAGS_PROTOCOL_ERROR |
-			    PE_FLAGS_MSG_DISCARDED);
-
-		pe_set_ready_state(port);
-	}
-}
-
-static void pe_vdm_response_exit(int port)
-{
-	PE_CLR_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS);
-}
-
-/**
- * PE_DEU_SEND_ENTER_USB
- */
-static void pe_enter_usb_entry(int port)
-{
-	uint32_t usb4_payload;
-
-	print_current_state(port);
-
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4)) {
-		pe_set_ready_state(port);
-		return;
-	}
-
-	/* Port is already in USB4 mode, do not send enter USB message again */
-	if (enter_usb_entry_is_done(port)) {
-		pe_set_ready_state(port);
-		return;
-	}
-
-	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
-	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	     !tc_is_vconn_src(port)) {
-		if (port_try_vconn_swap(port))
-			return;
-	}
-
-	pe[port].tx_type = TCPCI_MSG_SOP;
-	usb4_payload = enter_usb_setup_next_msg(port, &pe[port].tx_type);
-
-	if (!usb4_payload) {
-		enter_usb_failed(port);
-		pe_set_ready_state(port);
-		return;
-	}
-
-	tx_emsg[port].len = sizeof(usb4_payload);
-
-	memcpy(tx_emsg[port].buf, &usb4_payload, tx_emsg[port].len);
-	send_data_msg(port, pe[port].tx_type, PD_DATA_ENTER_USB);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_enter_usb_run(int port)
-{
-	enum pe_msg_check msg_check;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4)) {
-		pe_set_ready_state(port);
-		return;
-	}
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Handle Discarded message, return to PE_SNK/SRC_READY
-	 */
-	if (msg_check & PE_MSG_DISCARDED) {
-		pe_set_ready_state(port);
-		return;
-	} else if (msg_check == PE_MSG_SEND_PENDING) {
-		/* Wait until message is sent */
-		return;
-	}
-
-	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
-		pe_set_ready_state(port);
-		enter_usb_failed(port);
-		return;
-	}
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		int cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		int type = PD_HEADER_TYPE(rx_emsg[port].header);
-		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/* Only look at control messages */
-		if (cnt == 0) {
-			/* Accept message received */
-			if (type == PD_CTRL_ACCEPT) {
-				enter_usb_accepted(port, sop);
-			} else if (type == PD_CTRL_REJECT) {
-				enter_usb_rejected(port, sop);
-			} else {
-				/*
-				 * Unexpected control message received.
-				 * Send Soft Reset.
-				 */
-				pe_send_soft_reset(port, sop);
-				return;
-			}
-		} else {
-			/* Unexpected data message received. Send Soft reset */
-			pe_send_soft_reset(port, sop);
-			return;
-		}
-		pe_set_ready_state(port);
-	}
-}
-
-static void pe_enter_usb_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-#ifdef CONFIG_USBC_VCONN
-/*
- * PE_VCS_Evaluate_Swap
- */
-static void pe_vcs_evaluate_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/*
-	 * Request the DPM for an evaluation of the VCONN Swap request.
-	 * Note: Ports that are presently the VCONN Source must always
-	 * accept a VCONN
-	 */
-
-	/*
-	 * Transition to the PE_VCS_Accept_Swap state when:
-	 *  1) The Device Policy Manager indicates that a VCONN Swap is ok.
-	 *
-	 * Transition to the PE_VCS_Reject_Swap state when:
-	 *  1)  Port is not presently the VCONN Source and
-	 *  2) The DPM indicates that a VCONN Swap is not ok or
-	 *  3) The DPM indicates that a VCONN Swap cannot be done at this time.
-	 */
-
-	/* DPM rejects a VCONN Swap and port is not a VCONN source*/
-	if (!tc_check_vconn_swap(port) && tc_is_vconn_src(port) < 1) {
-		/* NOTE: PE_VCS_Reject_Swap State embedded here */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_REJECT);
-	}
-	/* Port is not ready to perform a VCONN swap */
-	else if (tc_is_vconn_src(port) < 0) {
-		/* NOTE: PE_VCS_Reject_Swap State embedded here */
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_WAIT);
-	}
-	/* Port is ready to perform a VCONN swap */
-	else {
-		/* NOTE: PE_VCS_Accept_Swap State embedded here */
-		PE_SET_FLAG(port, PE_FLAGS_ACCEPT);
-		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	}
-}
-
-static void pe_vcs_evaluate_swap_run(int port)
-{
-	/* Wait for ACCEPT, WAIT or Reject message to send. */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-
-		if (PE_CHK_FLAG(port, PE_FLAGS_ACCEPT)) {
-			PE_CLR_FLAG(port, PE_FLAGS_ACCEPT);
-			/* Accept Message sent and Presently VCONN Source */
-			if (tc_is_vconn_src(port))
-				set_state_pe(port, PE_VCS_WAIT_FOR_VCONN_SWAP);
-			/* Accept Message sent and Not presently VCONN Source */
-			else
-				set_state_pe(port, PE_VCS_TURN_ON_VCONN_SWAP);
-		} else {
-			/*
-			 * Message sent. Transition back to PE_SRC_Ready or
-			 * PE_SINK_Ready
-			 */
-			pe_set_ready_state(port);
-		}
-		return;
-	}
-
-	if (pe_check_outgoing_discard(port))
-		return;
-}
-
-/*
- * PE_VCS_Send_Swap
- */
-static void pe_vcs_send_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a VCONN_Swap Message */
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_VCONN_SWAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_vcs_send_swap_run(int port)
-{
-	uint8_t type;
-	uint8_t cnt;
-	enum tcpci_msg_type sop;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/* Increment once message has successfully sent */
-		pe[port].vconn_swap_counter++;
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		/* Only look at control messages */
-		if (cnt == 0) {
-			/*
-			 * Transition to the PE_VCS_Wait_For_VCONN state when:
-			 *   1) Accept Message Received and
-			 *   2) The Port is presently the VCONN Source.
-			 *
-			 * Transition to the PE_VCS_Turn_On_VCONN state when:
-			 *   1) Accept Message Received and
-			 *   2) The Port is not presently the VCONN Source.
-			 */
-			if (type == PD_CTRL_ACCEPT) {
-				if (tc_is_vconn_src(port)) {
-					set_state_pe(port,
-						PE_VCS_WAIT_FOR_VCONN_SWAP);
-				} else {
-					set_state_pe(port,
-						PE_VCS_TURN_ON_VCONN_SWAP);
-				}
-				return;
-			}
-			/*
-			 * Transition back to either the PE_SRC_Ready or
-			 * PE_SNK_Ready state when:
-			 *   2) Reject message is received or
-			 *   3) Wait message Received.
-			 */
-			if (type == PD_CTRL_REJECT || type == PD_CTRL_WAIT) {
-				pe_set_ready_state(port);
-				return;
-			}
-
-			/*
-			 * The Policy Engine May transition to the
-			 * PE_VCS_Force_Vconn state when:
-			 * - A Not_Supported Message is received and
-			 * - The Port is not presently the VCONN Source
-			 */
-			if (type == PD_CTRL_NOT_SUPPORTED) {
-				if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-							!tc_is_vconn_src(port))
-					set_state_pe(port, PE_VCS_FORCE_VCONN);
-				else
-					pe_set_ready_state(port);
-				return;
-			}
-		}
-		/*
-		 * Unexpected Message Received, send soft reset with SOP* of
-		 * incoming message.
-		 */
-		pe_send_soft_reset(port, sop);
-		return;
-	}
-
-	/*
-	 * Transition back to either the PE_SRC_Ready or
-	 * PE_SNK_Ready state when:
-	 *   1) SenderResponseTimer Timeout
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		pe_set_ready_state(port);
-}
-
-static void pe_vcs_send_swap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/*
- * PE_VCS_Wait_for_VCONN_Swap
- */
-static void pe_vcs_wait_for_vconn_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Start the VCONNOnTimer */
-	pd_timer_enable(port, PE_TIMER_VCONN_ON, PD_T_VCONN_SOURCE_ON);
-
-	/*
-	 * The USB PD 3.0 spec indicates that the initial VCONN source
-	 * shall cease sourcing VCONN within tVCONNSourceOff (25ms)
-	 * after receiving the PS_RDY message. However, some partners
-	 * begin sending SOP' messages only 1 ms after sending PS_RDY
-	 * during VCONN swap.
-	 *
-	 * Preemptively disable receipt of SOP' and SOP'' messages while
-	 * we wait for PS_RDY so we don't attempt to process messages
-	 * directed at the cable.
-	 *
-	 * We continue to source VCONN while we wait as required by the
-	 * spec.
-	 */
-	tcpm_sop_prime_enable(port, false);
-}
-
-static void pe_vcs_wait_for_vconn_swap_run(int port)
-{
-	/*
-	 * Transition to the PE_VCS_Turn_Off_VCONN state when:
-	 *  1) A PS_RDY Message is received.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		/*
-		 * PS_RDY message received
-		 *
-		 * Note: intentionally leave the receive flag set to indicate
-		 * our route on exit when PS_RDY is received.
-		 */
-		if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) &&
-		    (PD_HEADER_EXT(rx_emsg[port].header) == 0) &&
-		    (PD_HEADER_TYPE(rx_emsg[port].header) == PD_CTRL_PS_RDY)) {
-			set_state_pe(port, PE_VCS_TURN_OFF_VCONN_SWAP);
-			return;
-		} else {
-			/*
-			 * Unexpected message received - reset with the SOP* of
-			 * the incoming message.
-			 */
-			PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-			pe_send_soft_reset(port,
-				PD_HEADER_GET_SOP(rx_emsg[port].header));
-			return;
-		}
-	}
-
-	/*
-	 * Transition to either the PE_SRC_Hard_Reset or
-	 * PE_SNK_Hard_Reset state when:
-	 *   1) The VCONNOnTimer times out.
-	 */
-	if (pd_timer_is_expired(port, PE_TIMER_VCONN_ON)) {
-		if (pe[port].power_role == PD_ROLE_SOURCE)
-			set_state_pe(port, PE_SRC_HARD_RESET);
-		else
-			set_state_pe(port, PE_SNK_HARD_RESET);
-	}
-}
-
-static void pe_vcs_wait_for_vconn_swap_exit(int port)
-{
-	/*
-	 * If we exited without getting PS_RDY, re-enable SOP' messaging since
-	 * we are still the Vconn source.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED))
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-	else
-		tcpm_sop_prime_enable(port, true);
-
-	pd_timer_disable(port, PE_TIMER_VCONN_ON);
-}
-
-/*
- * PE_VCS_Turn_On_VCONN_Swap
- */
-static void pe_vcs_turn_on_vconn_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Request DPM to turn on VCONN */
-	pd_request_vconn_swap_on(port);
-}
-
-static void pe_vcs_turn_on_vconn_swap_run(int port)
-{
-
-	/*
-	 * Transition to the PE_VCS_Send_Ps_Rdy state when:
-	 *  1) The Port’s VCONN is on.
-	 */
-	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-		pd_timer_enable(port, PE_TIMER_TIMEOUT,
-				CONFIG_USBC_VCONN_SWAP_DELAY_US);
-	}
-
-	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT))
-		set_state_pe(port, PE_VCS_SEND_PS_RDY_SWAP);
-}
-
-static void pe_vcs_turn_on_vconn_swap_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_TIMEOUT);
-}
-
-/*
- * PE_VCS_Turn_Off_VCONN_Swap
- */
-static void pe_vcs_turn_off_vconn_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Request DPM to turn off VCONN */
-	pd_request_vconn_swap_off(port);
-}
-
-static void pe_vcs_turn_off_vconn_swap_run(int port)
-{
-	/* Wait for VCONN to turn off */
-	if (PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-
-		/*
-		 * A VCONN Swap Shall reset the DiscoverIdentityCounter
-		 * to zero
-		 */
-		pe[port].discover_identity_counter = 0;
-		pe[port].dr_swap_attempt_counter = 0;
-
-		pe_set_ready_state(port);
-		return;
-	}
-}
-
-/*
- * PE_VCS_Send_PS_Rdy_Swap
- */
-static void pe_vcs_send_ps_rdy_swap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Check for any interruptions to this non-interruptible AMS */
-	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		enum tcpci_msg_type sop =
-				PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		/* Soft reset with the SOP* of the incoming message */
-		pe_send_soft_reset(port, sop);
-		return;
-	}
-
-	/* Send a PS_RDY Message */
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PS_RDY);
-}
-
-static void pe_vcs_send_ps_rdy_swap_run(int port)
-{
-	/*
-	 * After a VCONN Swap the VCONN Source needs to reset
-	 * the Cable Plug’s Protocol Layer in order to ensure
-	 * MessageID synchronization.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		/*
-		 * A VCONN Swap Shall reset the
-		 * DiscoverIdentityCounter to zero
-		 */
-		pe[port].discover_identity_counter = 0;
-		pe[port].dr_swap_attempt_counter = 0;
-
-		/* A SOP' soft reset is required after VCONN swap */
-		pd_dpm_request(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
-		pe_set_ready_state(port);
-	}
-
-	if (pe_check_outgoing_discard(port))
-		return;
-
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		/* PS_RDY didn't send, soft reset */
-		pe_send_soft_reset(port, TCPCI_MSG_SOP);
-	}
-}
-
-/*
- * PE_VCS_Force_Vconn
- */
-__maybe_unused static void pe_vcs_force_vconn_entry(int port)
-{
-	print_current_state(port);
-
-	/* Request DPM to turn on VCONN */
-	pd_request_vconn_swap_on(port);
-}
-
-__maybe_unused static void pe_vcs_force_vconn_run(int port)
-{
-	/*
-	 * The Policy Engine Shall transition back to either the PE_SRC_Ready
-	 * or PE_SNK_Ready state when:
-	 *  1) The Port’s VCONN is on.
-	 *
-	 *  Note we'll wait CONFIG_USBC_VCONN_SWAP_DELAY_US, as defined by the
-	 *  board, to ensure Vconn is on.
-	 */
-	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
-		pd_timer_enable(port, PE_TIMER_TIMEOUT,
-				CONFIG_USBC_VCONN_SWAP_DELAY_US);
-	}
-
-	if (pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
-		/*
-		 * Note: A cable soft reset shouldn't be necessary as a
-		 * Not_Supported reply means the partner doesn't support
-		 * sourcing Vconn and did not communicate with the cable.
-		 */
-		pe_set_ready_state(port);
-		return;
-	}
-}
-
-__maybe_unused static void pe_vcs_force_vconn_exit(int port)
-{
-	pd_timer_disable(port, PE_TIMER_TIMEOUT);
-}
-
-/*
- * PE_VCS_CBL_SEND_SOFT_RESET
- * Note - Entry is only when directed by the DPM. Protocol errors are handled
- * by the PE_SEND_SOFT_RESET state.
- */
-static void pe_vcs_cbl_send_soft_reset_entry(int port)
-{
-	print_current_state(port);
-
-	if (!pe_can_send_sop_prime(port)) {
-		/*
-		 * If we're not VCONN source, return the appropriate state.
-		 * A VCONN swap re-triggers sending SOP' soft reset
-		 */
-		if (pe_is_explicit_contract(port)) {
-			/* Return to PE_{SRC,SNK}_Ready state */
-			pe_set_ready_state(port);
-		} else {
-			/*
-			 * Not in Explicit Contract, so we must be a SRC,
-			 * return to PE_Src_Send_Capabilities.
-			 */
-			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-		}
-		return;
-	}
-
-	send_ctrl_msg(port, TCPCI_MSG_SOP_PRIME, PD_CTRL_SOFT_RESET);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_vcs_cbl_send_soft_reset_run(int port)
-{
-	bool cable_soft_reset_complete = false;
-	enum pe_msg_check msg_check;
-
-	msg_check = pe_sender_response_msg_run(port);
-
-	/* Got ACCEPT or REJECT from Cable Plug */
-	if ((msg_check & PE_MSG_SENT) &&
-				PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-		cable_soft_reset_complete = true;
-
-		/*
-		 * Note: If port partner runs PD 2.0, we must use PD 2.0 to
-		 * communicate with the cable plug when in an explicit contract.
-		 *
-		 * PD Spec Table 6-2: Revision Interoperability during an
-		 * Explicit Contract
-		 */
-		if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV20)
-			prl_set_rev(port, TCPCI_MSG_SOP_PRIME,
-					PD_HEADER_REV(rx_emsg[port].header));
-	}
-
-	/* No GoodCRC received, cable is not present */
-	if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
-		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
-		/*
-		 * TODO(b/171823328): TCPMv2: Implement cable reset
-		 * Cable reset will only be done here if we know for certain
-		 * a cable is present (we've received the SOP' DiscId response).
-		 */
-		cable_soft_reset_complete = true;
-	}
-
-	if (cable_soft_reset_complete ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
-	    (msg_check & PE_MSG_DISCARDED)) {
-		if (pe_is_explicit_contract(port)) {
-			/* Return to PE_{SRC,SNK}_Ready state */
-			pe_set_ready_state(port);
-		} else {
-			/*
-			 * Not in Explicit Contract, so we must be a SRC,
-			 * return to PE_Src_Send_Capabilities.
-			 */
-			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
-		}
-	}
-}
-
-static void pe_vcs_cbl_send_soft_reset_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-#endif /* CONFIG_USBC_VCONN */
-
-/*
- * PE_DR_SNK_Get_Sink_Cap and PE_SRC_Get_Sink_Cap State (shared)
- */
-static void pe_dr_get_sink_cap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a Get Sink Cap Message */
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_dr_get_sink_cap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-	enum tcpci_msg_type sop;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Transition to PE_[SRC,SNK]_Ready when:
-	 *   1) A Sink_Capabilities Message is received
-	 *   2) Or SenderResponseTimer times out
-	 *   3) Or a Reject Message is received.
-	 *
-	 * Transition to PE_SEND_SOFT_RESET state when:
-	 *   1) An unexpected message is received
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-		sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
-
-		if (ext == 0 && sop == TCPCI_MSG_SOP) {
-			if ((cnt > 0) && (type == PD_DATA_SINK_CAP)) {
-				uint32_t *payload =
-					(uint32_t *)rx_emsg[port].buf;
-				uint8_t cap_cnt = rx_emsg[port].len /
-							sizeof(uint32_t);
-
-				pe_set_snk_caps(port, cap_cnt, payload);
-
-				dpm_evaluate_sink_fixed_pdo(port, payload[0]);
-				pe_set_ready_state(port);
-				return;
-			} else if (cnt == 0 && (type == PD_CTRL_REJECT ||
-				   type == PD_CTRL_NOT_SUPPORTED)) {
-				pe_set_ready_state(port);
-				return;
-			}
-			/* Unexpected messages fall through to soft reset */
-		}
-
-		pe_send_soft_reset(port, sop);
-		return;
-	}
-
-	/*
-	 * Transition to PE_[SRC,SNK]_Ready state when:
-	 *   1) SenderResponseTimer times out.
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		pe_set_ready_state(port);
-}
-
-static void pe_dr_get_sink_cap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-/*
- * PE_DR_SNK_Give_Source_Cap
- */
-static void pe_dr_snk_give_source_cap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send source capabilities. */
-	send_source_cap(port);
-}
-
-static void pe_dr_snk_give_source_cap_run(int port)
-{
-	/*
-	 * Transition back to PE_SNK_Ready when the Source_Capabilities message
-	 * has been successfully sent.
-	 *
-	 * Get Source Capabilities AMS is uninterruptible, but in case the
-	 * partner violates the spec then send a soft reset rather than get
-	 * stuck here.
-	 */
-	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
-		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
-		set_state_pe(port, PE_SNK_READY);
-	} else if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-		pe_send_soft_reset(port, TCPCI_MSG_SOP);
-	}
-}
-
-/*
- * PE_DR_SRC_Get_Source_Cap
- */
-static void pe_dr_src_get_source_cap_entry(int port)
-{
-	print_current_state(port);
-
-	/* Send a Get_Source_Cap Message */
-	tx_emsg[port].len = 0;
-	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP);
-	pe_sender_response_msg_entry(port);
-}
-
-static void pe_dr_src_get_source_cap_run(int port)
-{
-	int type;
-	int cnt;
-	int ext;
-	enum pe_msg_check msg_check;
-
-	/*
-	 * Check the state of the message sent
-	 */
-	msg_check = pe_sender_response_msg_run(port);
-
-	/*
-	 * Transition to PE_SRC_Ready when:
-	 *   1) A Source Capabilities Message is received.
-	 *   2) A Reject Message is received.
-	 */
-	if ((msg_check & PE_MSG_SENT) &&
-	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
-		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-
-		type = PD_HEADER_TYPE(rx_emsg[port].header);
-		cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		ext = PD_HEADER_EXT(rx_emsg[port].header);
-
-		if (ext == 0) {
-			if ((cnt > 0) && (type == PD_DATA_SOURCE_CAP)) {
-				uint32_t *payload =
-					(uint32_t *)rx_emsg[port].buf;
-
-				pd_set_src_caps(port, cnt, payload);
-
-				/*
-				 * If we'd prefer to charge from this partner,
-				 * then propose a PR swap.
-				 */
-				if (pd_can_charge_from_device(port, cnt,
-							      payload))
-					pd_request_power_swap(port);
-
-				/*
-				 * Report dual role power capability to the
-				 * charge manager if present
-				 */
-				if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
-				    pd_get_partner_dual_role_power(port))
-					charge_manager_update_dualrole(port,
-								CAP_DUALROLE);
-
-				set_state_pe(port, PE_SRC_READY);
-			} else if ((cnt == 0) && (type == PD_CTRL_REJECT ||
-					type == PD_CTRL_NOT_SUPPORTED)) {
-				pd_set_src_caps(port, -1, NULL);
-				set_state_pe(port, PE_SRC_READY);
-			} else {
-				/*
-				 * On protocol error, consider source cap
-				 * retrieval a failure
-				 */
-				pd_set_src_caps(port, -1, NULL);
-				set_state_pe(port, PE_SEND_SOFT_RESET);
-			}
-			return;
-		} else {
-			pd_set_src_caps(port, -1, NULL);
-			set_state_pe(port, PE_SEND_SOFT_RESET);
-			return;
-		}
-	}
-
-	/*
-	 * Transition to PE_SRC_Ready state when:
-	 *   1) the SenderResponseTimer times out.
-	 *   2) Message was discarded.
-	 */
-	if ((msg_check & PE_MSG_DISCARDED) ||
-	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
-		set_state_pe(port, PE_SRC_READY);
-}
-
-static void pe_dr_src_get_source_cap_exit(int port)
-{
-	pe_sender_response_msg_exit(port);
-}
-
-const uint32_t * const pd_get_src_caps(int port)
-{
-	return pe[port].src_caps;
-}
-
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-	int i;
-
-	pe[port].src_cap_cnt = cnt;
-
-	for (i = 0; i < cnt; i++)
-		pe[port].src_caps[i] = *src_caps++;
-}
-
-uint8_t pd_get_src_cap_cnt(int port)
-{
-	if (pe[port].src_cap_cnt > 0)
-		return pe[port].src_cap_cnt;
-
-	return 0;
-}
-
-/* Track access to the PD discovery structures during HC execution */
-uint32_t task_access[CONFIG_USB_PD_PORT_MAX_COUNT][DISCOVERY_TYPE_COUNT];
-
-void pd_dfp_discovery_init(int port)
-{
-	atomic_or(&task_access[port][TCPCI_MSG_SOP], BIT(task_get_current()));
-	atomic_or(&task_access[port][TCPCI_MSG_SOP_PRIME],
-		  BIT(task_get_current()));
-
-	memset(pe[port].discovery, 0, sizeof(pe[port].discovery));
-
-}
-
-void pd_dfp_mode_init(int port)
-{
-	/*
-	 * Clear the VDM Setup Done and Modal Operation flags so we will
-	 * have a fresh discovery
-	 */
-	PE_CLR_FLAG(port, PE_FLAGS_VDM_SETUP_DONE |
-			  PE_FLAGS_MODAL_OPERATION);
-
-	memset(pe[port].partner_amodes, 0, sizeof(pe[port].partner_amodes));
-
-	/* Reset the DPM and DP modules to enable alternate mode entry. */
-	dpm_init(port);
-	dp_init(port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		tbt_init(port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		enter_usb_init(port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_UFP_DP))
-		pd_ufp_set_dp_opos(port, 0);
-}
-
-__maybe_unused void pd_discovery_access_clear(int port,
-			enum tcpci_msg_type type)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-
-	atomic_clear_bits(&task_access[port][type], 0xFFFFFFFF);
-}
-
-__maybe_unused bool pd_discovery_access_validate(int port,
-			enum tcpci_msg_type type)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-
-	return !(task_access[port][type] & ~BIT(task_get_current()));
-}
-
-__maybe_unused struct pd_discovery *pd_get_am_discovery_and_notify_access(
-				int port, enum tcpci_msg_type type)
-{
-	atomic_or(&task_access[port][type], BIT(task_get_current()));
-	return (struct pd_discovery *)pd_get_am_discovery(port, type);
-}
-
-__maybe_unused const struct pd_discovery *pd_get_am_discovery(int port,
-			enum tcpci_msg_type type)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-	ASSERT(type < DISCOVERY_TYPE_COUNT);
-
-	return &pe[port].discovery[type];
-}
-
-__maybe_unused struct partner_active_modes *pd_get_partner_active_modes(
-			int port, enum tcpci_msg_type type)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-	ASSERT(type < AMODE_TYPE_COUNT);
-	return &pe[port].partner_amodes[type];
-}
-
-__maybe_unused void pd_set_dfp_enter_mode_flag(int port, bool set)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		assert(0);
-
-	if (set)
-		PE_SET_FLAG(port, PE_FLAGS_MODAL_OPERATION);
-	else
-		PE_CLR_FLAG(port, PE_FLAGS_MODAL_OPERATION);
-}
-
-const char *pe_get_current_state(int port)
-{
-	if (pe_is_running(port) && IS_ENABLED(USB_PD_DEBUG_LABELS))
-		return pe_state_names[get_state_pe(port)];
-	else
-		return "";
-}
-
-uint32_t pe_get_flags(int port)
-{
-	return pe[port].flags;
-}
-
-static __const_data const struct usb_state pe_states[] = {
-	/* Super States */
-#ifdef CONFIG_USB_PD_REV30
-	[PE_PRS_FRS_SHARED] = {
-		.entry = pe_prs_frs_shared_entry,
-		.exit  = pe_prs_frs_shared_exit,
-	},
-#endif
-	[PE_VDM_SEND_REQUEST] = {
-		.entry = pe_vdm_send_request_entry,
-		.run   = pe_vdm_send_request_run,
-		.exit  = pe_vdm_send_request_exit,
-	},
-
-	/* Normal States */
-	[PE_SRC_STARTUP] = {
-		.entry = pe_src_startup_entry,
-		.run   = pe_src_startup_run,
-		.exit  = pe_src_startup_exit,
-	},
-	[PE_SRC_DISCOVERY] = {
-		.entry = pe_src_discovery_entry,
-		.run   = pe_src_discovery_run,
-	},
-	[PE_SRC_SEND_CAPABILITIES] = {
-		.entry = pe_src_send_capabilities_entry,
-		.run   = pe_src_send_capabilities_run,
-		.exit  = pe_src_send_capabilities_exit,
-	},
-	[PE_SRC_NEGOTIATE_CAPABILITY] = {
-		.entry = pe_src_negotiate_capability_entry,
-	},
-	[PE_SRC_TRANSITION_SUPPLY] = {
-		.entry = pe_src_transition_supply_entry,
-		.run   = pe_src_transition_supply_run,
-		.exit  = pe_src_transition_supply_exit,
-	},
-	[PE_SRC_READY] = {
-		.entry = pe_src_ready_entry,
-		.run   = pe_src_ready_run,
-	},
-	[PE_SRC_DISABLED] = {
-		.entry = pe_src_disabled_entry,
-	},
-	[PE_SRC_CAPABILITY_RESPONSE] = {
-		.entry = pe_src_capability_response_entry,
-		.run   = pe_src_capability_response_run,
-	},
-	[PE_SRC_HARD_RESET] = {
-		.entry = pe_src_hard_reset_entry,
-		.run   = pe_src_hard_reset_run,
-		.exit  = pe_src_hard_reset_exit,
-	},
-	[PE_SRC_HARD_RESET_RECEIVED] = {
-		.entry = pe_src_hard_reset_received_entry,
-		.run = pe_src_hard_reset_received_run,
-		.exit = pe_src_hard_reset_received_exit,
-	},
-	[PE_SRC_TRANSITION_TO_DEFAULT] = {
-		.entry = pe_src_transition_to_default_entry,
-		.run = pe_src_transition_to_default_run,
-	},
-	[PE_SNK_STARTUP] = {
-		.entry = pe_snk_startup_entry,
-		.run = pe_snk_startup_run,
-	},
-	[PE_SNK_DISCOVERY] = {
-		.entry = pe_snk_discovery_entry,
-		.run = pe_snk_discovery_run,
-	},
-	[PE_SNK_WAIT_FOR_CAPABILITIES] = {
-		.entry = pe_snk_wait_for_capabilities_entry,
-		.run = pe_snk_wait_for_capabilities_run,
-		.exit = pe_snk_wait_for_capabilities_exit,
-	},
-	[PE_SNK_EVALUATE_CAPABILITY] = {
-		.entry = pe_snk_evaluate_capability_entry,
-	},
-	[PE_SNK_SELECT_CAPABILITY] = {
-		.entry = pe_snk_select_capability_entry,
-		.run = pe_snk_select_capability_run,
-		.exit = pe_snk_select_capability_exit,
-	},
-	[PE_SNK_READY] = {
-		.entry = pe_snk_ready_entry,
-		.run   = pe_snk_ready_run,
-	},
-	[PE_SNK_HARD_RESET] = {
-		.entry = pe_snk_hard_reset_entry,
-		.run   = pe_snk_hard_reset_run,
-	},
-	[PE_SNK_TRANSITION_TO_DEFAULT] = {
-		.entry = pe_snk_transition_to_default_entry,
-		.run   = pe_snk_transition_to_default_run,
-	},
-	[PE_SNK_GIVE_SINK_CAP] = {
-		.entry = pe_snk_give_sink_cap_entry,
-		.run = pe_snk_give_sink_cap_run,
-	},
-	[PE_SNK_GET_SOURCE_CAP] = {
-		.entry = pe_snk_get_source_cap_entry,
-		.run   = pe_snk_get_source_cap_run,
-	},
-	[PE_SNK_TRANSITION_SINK] = {
-		.entry = pe_snk_transition_sink_entry,
-		.run   = pe_snk_transition_sink_run,
-		.exit   = pe_snk_transition_sink_exit,
-	},
-	[PE_SEND_SOFT_RESET] = {
-		.entry = pe_send_soft_reset_entry,
-		.run = pe_send_soft_reset_run,
-		.exit = pe_send_soft_reset_exit,
-	},
-	[PE_SOFT_RESET] = {
-		.entry = pe_soft_reset_entry,
-		.run = pe_soft_reset_run,
-	},
-	[PE_SEND_NOT_SUPPORTED] = {
-		.entry = pe_send_not_supported_entry,
-		.run = pe_send_not_supported_run,
-	},
-	[PE_SRC_PING] = {
-		.entry = pe_src_ping_entry,
-		.run   = pe_src_ping_run,
-	},
-	[PE_DRS_EVALUATE_SWAP] = {
-		.entry = pe_drs_evaluate_swap_entry,
-		.run   = pe_drs_evaluate_swap_run,
-	},
-	[PE_DRS_CHANGE] = {
-		.entry = pe_drs_change_entry,
-		.run   = pe_drs_change_run,
-	},
-	[PE_DRS_SEND_SWAP] = {
-		.entry = pe_drs_send_swap_entry,
-		.run   = pe_drs_send_swap_run,
-		.exit  = pe_drs_send_swap_exit,
-	},
-	[PE_PRS_SRC_SNK_EVALUATE_SWAP] = {
-		.entry = pe_prs_src_snk_evaluate_swap_entry,
-		.run   = pe_prs_src_snk_evaluate_swap_run,
-	},
-	[PE_PRS_SRC_SNK_TRANSITION_TO_OFF] = {
-		.entry = pe_prs_src_snk_transition_to_off_entry,
-		.run   = pe_prs_src_snk_transition_to_off_run,
-		.exit  = pe_prs_src_snk_transition_to_off_exit,
-	},
-	[PE_PRS_SRC_SNK_ASSERT_RD] = {
-		.entry = pe_prs_src_snk_assert_rd_entry,
-		.run   = pe_prs_src_snk_assert_rd_run,
-	},
-	[PE_PRS_SRC_SNK_WAIT_SOURCE_ON] = {
-		.entry = pe_prs_src_snk_wait_source_on_entry,
-		.run   = pe_prs_src_snk_wait_source_on_run,
-		.exit  = pe_prs_src_snk_wait_source_on_exit,
-	},
-	[PE_PRS_SRC_SNK_SEND_SWAP] = {
-		.entry = pe_prs_src_snk_send_swap_entry,
-		.run   = pe_prs_src_snk_send_swap_run,
-		.exit  = pe_prs_src_snk_send_swap_exit,
-	},
-	[PE_PRS_SNK_SRC_EVALUATE_SWAP] = {
-		.entry = pe_prs_snk_src_evaluate_swap_entry,
-		.run   = pe_prs_snk_src_evaluate_swap_run,
-	},
-	/*
-	 * Some of the Power Role Swap actions are shared with the very
-	 * similar actions of Fast Role Swap.
-	 */
-	/* State actions are shared with PE_FRS_SNK_SRC_TRANSITION_TO_OFF */
-	[PE_PRS_SNK_SRC_TRANSITION_TO_OFF] = {
-		.entry = pe_prs_snk_src_transition_to_off_entry,
-		.run   = pe_prs_snk_src_transition_to_off_run,
-		.exit  = pe_prs_snk_src_transition_to_off_exit,
-#ifdef CONFIG_USB_PD_REV30
-		.parent = &pe_states[PE_PRS_FRS_SHARED],
-#endif /* CONFIG_USB_PD_REV30 */
-	},
-	/* State actions are shared with PE_FRS_SNK_SRC_ASSERT_RP */
-	[PE_PRS_SNK_SRC_ASSERT_RP] = {
-		.entry = pe_prs_snk_src_assert_rp_entry,
-		.run   = pe_prs_snk_src_assert_rp_run,
-#ifdef CONFIG_USB_PD_REV30
-		.parent = &pe_states[PE_PRS_FRS_SHARED],
-#endif /* CONFIG_USB_PD_REV30 */
-	},
-	/* State actions are shared with PE_FRS_SNK_SRC_SOURCE_ON */
-	[PE_PRS_SNK_SRC_SOURCE_ON] = {
-		.entry = pe_prs_snk_src_source_on_entry,
-		.run   = pe_prs_snk_src_source_on_run,
-		.exit  = pe_prs_snk_src_source_on_exit,
-#ifdef CONFIG_USB_PD_REV30
-		.parent = &pe_states[PE_PRS_FRS_SHARED],
-#endif /* CONFIG_USB_PD_REV30 */
-	},
-	/* State actions are shared with PE_FRS_SNK_SRC_SEND_SWAP */
-	[PE_PRS_SNK_SRC_SEND_SWAP] = {
-		.entry = pe_prs_snk_src_send_swap_entry,
-		.run   = pe_prs_snk_src_send_swap_run,
-		.exit  = pe_prs_snk_src_send_swap_exit,
-#ifdef CONFIG_USB_PD_REV30
-		.parent = &pe_states[PE_PRS_FRS_SHARED],
-#endif /* CONFIG_USB_PD_REV30 */
-	},
-#ifdef CONFIG_USBC_VCONN
-	[PE_VCS_EVALUATE_SWAP] = {
-		.entry = pe_vcs_evaluate_swap_entry,
-		.run   = pe_vcs_evaluate_swap_run,
-	},
-	[PE_VCS_SEND_SWAP] = {
-		.entry = pe_vcs_send_swap_entry,
-		.run   = pe_vcs_send_swap_run,
-		.exit  = pe_vcs_send_swap_exit,
-	},
-	[PE_VCS_WAIT_FOR_VCONN_SWAP] = {
-		.entry = pe_vcs_wait_for_vconn_swap_entry,
-		.run   = pe_vcs_wait_for_vconn_swap_run,
-		.exit  = pe_vcs_wait_for_vconn_swap_exit,
-	},
-	[PE_VCS_TURN_ON_VCONN_SWAP] = {
-		.entry = pe_vcs_turn_on_vconn_swap_entry,
-		.run   = pe_vcs_turn_on_vconn_swap_run,
-		.exit  = pe_vcs_turn_on_vconn_swap_exit,
-	},
-	[PE_VCS_TURN_OFF_VCONN_SWAP] = {
-		.entry = pe_vcs_turn_off_vconn_swap_entry,
-		.run   = pe_vcs_turn_off_vconn_swap_run,
-	},
-	[PE_VCS_SEND_PS_RDY_SWAP] = {
-		.entry = pe_vcs_send_ps_rdy_swap_entry,
-		.run   = pe_vcs_send_ps_rdy_swap_run,
-	},
-	[PE_VCS_CBL_SEND_SOFT_RESET] = {
-		.entry  = pe_vcs_cbl_send_soft_reset_entry,
-		.run    = pe_vcs_cbl_send_soft_reset_run,
-		.exit   = pe_vcs_cbl_send_soft_reset_exit,
-	},
-#endif /* CONFIG_USBC_VCONN */
-	[PE_VDM_IDENTITY_REQUEST_CBL] = {
-		.entry  = pe_vdm_identity_request_cbl_entry,
-		.run    = pe_vdm_identity_request_cbl_run,
-		.exit   = pe_vdm_identity_request_cbl_exit,
-		.parent = &pe_states[PE_VDM_SEND_REQUEST],
-	},
-	[PE_INIT_PORT_VDM_IDENTITY_REQUEST] = {
-		.entry  = pe_init_port_vdm_identity_request_entry,
-		.run    = pe_init_port_vdm_identity_request_run,
-		.exit	= pe_init_port_vdm_identity_request_exit,
-		.parent = &pe_states[PE_VDM_SEND_REQUEST],
-	},
-	[PE_INIT_VDM_SVIDS_REQUEST] = {
-		.entry	= pe_init_vdm_svids_request_entry,
-		.run	= pe_init_vdm_svids_request_run,
-		.exit	= pe_init_vdm_svids_request_exit,
-		.parent = &pe_states[PE_VDM_SEND_REQUEST],
-	},
-	[PE_INIT_VDM_MODES_REQUEST] = {
-		.entry	= pe_init_vdm_modes_request_entry,
-		.run	= pe_init_vdm_modes_request_run,
-		.exit   = pe_init_vdm_modes_request_exit,
-		.parent = &pe_states[PE_VDM_SEND_REQUEST],
-	},
-	[PE_VDM_REQUEST_DPM] = {
-		.entry = pe_vdm_request_dpm_entry,
-		.run   = pe_vdm_request_dpm_run,
-		.exit  = pe_vdm_request_dpm_exit,
-		.parent = &pe_states[PE_VDM_SEND_REQUEST],
-	},
-	[PE_VDM_RESPONSE] = {
-		.entry = pe_vdm_response_entry,
-		.run   = pe_vdm_response_run,
-		.exit  = pe_vdm_response_exit,
-	},
-	[PE_HANDLE_CUSTOM_VDM_REQUEST] = {
-		.entry = pe_handle_custom_vdm_request_entry,
-		.run   = pe_handle_custom_vdm_request_run,
-		.exit  = pe_handle_custom_vdm_request_exit,
-	},
-	[PE_DEU_SEND_ENTER_USB] = {
-		.entry = pe_enter_usb_entry,
-		.run = pe_enter_usb_run,
-		.exit = pe_enter_usb_exit,
-	},
-	[PE_WAIT_FOR_ERROR_RECOVERY] = {
-		.entry = pe_wait_for_error_recovery_entry,
-		.run   = pe_wait_for_error_recovery_run,
-	},
-	[PE_BIST_TX] = {
-		.entry = pe_bist_tx_entry,
-		.run   = pe_bist_tx_run,
-		.exit  = pe_bist_tx_exit,
-	},
-	[PE_DR_GET_SINK_CAP] = {
-		.entry = pe_dr_get_sink_cap_entry,
-		.run   = pe_dr_get_sink_cap_run,
-		.exit  = pe_dr_get_sink_cap_exit,
-	},
-	[PE_DR_SNK_GIVE_SOURCE_CAP] = {
-		.entry = pe_dr_snk_give_source_cap_entry,
-		.run = pe_dr_snk_give_source_cap_run,
-	},
-	[PE_DR_SRC_GET_SOURCE_CAP] = {
-		.entry = pe_dr_src_get_source_cap_entry,
-		.run   = pe_dr_src_get_source_cap_run,
-		.exit  = pe_dr_src_get_source_cap_exit,
-	},
-#ifdef CONFIG_USB_PD_REV30
-	[PE_FRS_SNK_SRC_START_AMS] = {
-		.entry = pe_frs_snk_src_start_ams_entry,
-		.parent = &pe_states[PE_PRS_FRS_SHARED],
-	},
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	[PE_GIVE_BATTERY_CAP] = {
-		.entry = pe_give_battery_cap_entry,
-		.run   = pe_give_battery_cap_run,
-	},
-	[PE_GIVE_BATTERY_STATUS] = {
-		.entry = pe_give_battery_status_entry,
-		.run   = pe_give_battery_status_run,
-	},
-	[PE_SEND_ALERT] = {
-		.entry = pe_send_alert_entry,
-		.run   = pe_send_alert_run,
-	},
-#else
-	[PE_SRC_CHUNK_RECEIVED] = {
-		.entry = pe_chunk_received_entry,
-		.run   = pe_chunk_received_run,
-		.exit  = pe_chunk_received_exit,
-	},
-	[PE_SNK_CHUNK_RECEIVED] = {
-		.entry = pe_chunk_received_entry,
-		.run   = pe_chunk_received_run,
-		.exit  = pe_chunk_received_exit,
-	},
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-#ifdef CONFIG_USBC_VCONN
-	[PE_VCS_FORCE_VCONN] = {
-		.entry = pe_vcs_force_vconn_entry,
-		.run   = pe_vcs_force_vconn_run,
-		.exit  = pe_vcs_force_vconn_exit,
-	},
-#endif /* CONFIG_USBC_VCONN */
-#endif /* CONFIG_USB_PD_REV30 */
-};
-
-#ifdef TEST_BUILD
-/* TODO(b/173791979): Unit tests shouldn't need to access internal states */
-const struct test_sm_data test_pe_sm_data[] = {
-	{
-		.base = pe_states,
-		.size = ARRAY_SIZE(pe_states),
-		.names = pe_state_names,
-		.names_size = ARRAY_SIZE(pe_state_names),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pe_states) == ARRAY_SIZE(pe_state_names));
-const int test_pe_sm_data_size = ARRAY_SIZE(test_pe_sm_data);
-
-void pe_set_flag(int port, int flag)
-{
-	PE_SET_FLAG(port, flag);
-}
-void pe_clr_flag(int port, int flag)
-{
-	PE_CLR_FLAG(port, flag);
-}
-int pe_chk_flag(int port, int flag)
-{
-	return PE_CHK_FLAG(port, flag);
-}
-int pe_get_all_flags(int port)
-{
-	return pe[port].flags;
-}
-void pe_set_all_flags(int port, int flags)
-{
-	pe[port].flags = flags;
-}
-void pe_clr_dpm_requests(int port)
-{
-	pe[port].dpm_request = 0;
-}
-#endif
diff --git a/common/usbc/usb_prl_sm.c b/common/usbc/usb_prl_sm.c
deleted file mode 100644
index a58a579775..0000000000
--- a/common/usbc/usb_prl_sm.c
+++ /dev/null
@@ -1,2471 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "board.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "util.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_timer.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-#include "usb_emsg.h"
-#include "usb_sm.h"
-#include "vpd_api.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/*
- * Define DEBUG_PRINT_FLAG_NAMES to print flag names when set and cleared.
- */
-#undef DEBUG_PRINT_FLAG_NAMES
-
-#ifdef DEBUG_PRINT_FLAG_NAMES
-__maybe_unused static void print_flag(const char *group,
-				      int set_or_clear,
-				      int flag);
-#define SET_FLAG(group, flags, flag)                     \
-	do {                                             \
-		print_flag(group, 1, flag);              \
-		atomic_or(flags, (flag));                \
-	} while (0)
-#define CLR_FLAG(group, flags, flag)                     \
-	do {                                             \
-		int before = *flags;                     \
-		atomic_clear_bits(flags, (flag));        \
-		if (*flags != before)                    \
-			print_flag(group, 0, flag);      \
-	} while (0)
-#else
-#define SET_FLAG(group, flags, flag) atomic_or(flags, (flag))
-#define CLR_FLAG(group, flags, flag) atomic_clear_bits(flags, (flag))
-#endif
-
-
-#define RCH_SET_FLAG(port, flag) SET_FLAG("RCH", &rch[port].flags, (flag))
-#define RCH_CLR_FLAG(port, flag) CLR_FLAG("RCH", &rch[port].flags, (flag))
-#define RCH_CHK_FLAG(port, flag) (rch[port].flags & (flag))
-
-#define TCH_SET_FLAG(port, flag) SET_FLAG("TCH", &tch[port].flags, (flag))
-#define TCH_CLR_FLAG(port, flag) CLR_FLAG("TCH", &tch[port].flags, (flag))
-#define TCH_CHK_FLAG(port, flag) (tch[port].flags & (flag))
-
-#define PRL_TX_SET_FLAG(port, flag) \
-	SET_FLAG("PRL_TX", &prl_tx[port].flags, (flag))
-#define PRL_TX_CLR_FLAG(port, flag) \
-	CLR_FLAG("PRL_TX", &prl_tx[port].flags, (flag))
-#define PRL_TX_CHK_FLAG(port, flag) (prl_tx[port].flags & (flag))
-
-#define PRL_HR_SET_FLAG(port, flag) \
-	SET_FLAG("PRL_HR", &prl_hr[port].flags, (flag))
-#define PRL_HR_CLR_FLAG(port, flag) \
-	CLR_FLAG("PRL_HR", &prl_hr[port].flags, (flag))
-#define PRL_HR_CHK_FLAG(port, flag) (prl_hr[port].flags & (flag))
-
-#define PDMSG_SET_FLAG(port, flag) SET_FLAG("PDMSG", &pdmsg[port].flags, (flag))
-#define PDMSG_CLR_FLAG(port, flag) CLR_FLAG("PDMSG", &pdmsg[port].flags, (flag))
-#define PDMSG_CHK_FLAG(port, flag) (pdmsg[port].flags & (flag))
-
-/* Protocol Layer Flags */
-/*
- * NOTE:
- *	These flags are used in multiple state machines and could have
- *	different meanings in each state machine.
- */
-/* Flag to note message transmission completed */
-#define PRL_FLAGS_TX_COMPLETE             BIT(0)
-/* Flag to note that PRL requested to set SINK_NG CC state */
-#define PRL_FLAGS_SINK_NG                 BIT(1)
-/* Flag to note PRL waited for SINK_OK CC state before transmitting */
-#define PRL_FLAGS_WAIT_SINK_OK            BIT(2)
-/* Flag to note transmission error occurred */
-#define PRL_FLAGS_TX_ERROR                BIT(3)
-/* Flag to note PE triggered a hard reset */
-#define PRL_FLAGS_PE_HARD_RESET           BIT(4)
-/* Flag to note hard reset has completed */
-#define PRL_FLAGS_HARD_RESET_COMPLETE     BIT(5)
-/* Flag to note port partner sent a hard reset */
-#define PRL_FLAGS_PORT_PARTNER_HARD_RESET BIT(6)
-/*
- * Flag to note a message transmission has been requested. It is only cleared
- * when we send the message to the TCPC layer.
- */
-#define PRL_FLAGS_MSG_XMIT                BIT(7)
-/* Flag to note a message was received */
-#define PRL_FLAGS_MSG_RECEIVED            BIT(8)
-/* Flag to note aborting current TX message, not currently set */
-#define PRL_FLAGS_ABORT                   BIT(9)
-/* Flag to note current TX message uses chunking */
-#define PRL_FLAGS_CHUNKING                BIT(10)
-
-struct bit_name {
-	int		value;
-	const char	*name;
-};
-
-static __const_data struct bit_name flag_bit_names[] = {
-	{ PRL_FLAGS_TX_COMPLETE, "PRL_FLAGS_TX_COMPLETE" },
-	{ PRL_FLAGS_SINK_NG, "PRL_FLAGS_SINK_NG" },
-	{ PRL_FLAGS_WAIT_SINK_OK, "PRL_FLAGS_WAIT_SINK_OK" },
-	{ PRL_FLAGS_TX_ERROR, "PRL_FLAGS_TX_ERROR" },
-	{ PRL_FLAGS_PE_HARD_RESET, "PRL_FLAGS_PE_HARD_RESET" },
-	{ PRL_FLAGS_HARD_RESET_COMPLETE, "PRL_FLAGS_HARD_RESET_COMPLETE" },
-	{ PRL_FLAGS_PORT_PARTNER_HARD_RESET,
-		"PRL_FLAGS_PORT_PARTNER_HARD_RESET" },
-	{ PRL_FLAGS_MSG_XMIT, "PRL_FLAGS_MSG_XMIT" },
-	{ PRL_FLAGS_MSG_RECEIVED, "PRL_FLAGS_MSG_RECEIVED" },
-	{ PRL_FLAGS_ABORT, "PRL_FLAGS_ABORT" },
-	{ PRL_FLAGS_CHUNKING, "PRL_FLAGS_CHUNKING" },
-};
-
-__maybe_unused static void print_bits(const char *group,
-				      const char *desc,
-				      int value,
-				      struct bit_name *names,
-				      int names_size)
-{
-	int i;
-
-	CPRINTF("%s %s 0x%x : ", group, desc, value);
-	for (i = 0; i < names_size; i++) {
-		if (value & names[i].value)
-			CPRINTF("%s | ", names[i].name);
-		value &= ~names[i].value;
-	}
-	if (value != 0)
-		CPRINTF("0x%x", value);
-	CPRINTF("\n");
-}
-
-__maybe_unused static void print_flag(const char *group,
-				      int set_or_clear,
-				      int flag)
-{
-	print_bits(group, set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
-		   ARRAY_SIZE(flag_bit_names));
-}
-
-/* PD counter definitions */
-#define PD_MESSAGE_ID_COUNT 7
-
-/* Size of PDMSG Chunk Buffer */
-#define CHK_BUF_SIZE 7
-#define CHK_BUF_SIZE_BYTES 28
-
-/*
- * Debug log level - higher number == more log
- *   Level 0: disabled
- *   Level 1: not currently used
- *   Level 2: plus non-ping messages
- *   Level 3: plus ping packet and PRL states
- *
- * Note that higher log level causes timing changes and thus may affect
- * performance.
- */
-#ifdef CONFIG_USB_PD_DEBUG_LEVEL
-static const enum debug_level prl_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
-#else
-static enum debug_level prl_debug_level = DEBUG_LEVEL_1;
-#endif
-
-static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Protocol Transmit States (Section 6.11.2.2) */
-enum usb_prl_tx_state {
-	PRL_TX_PHY_LAYER_RESET,
-	PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
-	PRL_TX_LAYER_RESET_FOR_TRANSMIT,
-	PRL_TX_WAIT_FOR_PHY_RESPONSE,
-	PRL_TX_SRC_SOURCE_TX,
-	PRL_TX_SNK_START_AMS,
-	PRL_TX_SRC_PENDING,
-	PRL_TX_SNK_PENDING,
-	PRL_TX_DISCARD_MESSAGE,
-};
-
-/* Protocol Hard Reset States (Section 6.11.2.4) */
-enum usb_prl_hr_state {
-	PRL_HR_WAIT_FOR_REQUEST,
-	PRL_HR_RESET_LAYER,
-	PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
-	PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
-};
-
-/* Chunked Rx states (Section 6.11.2.1.2) */
-enum usb_rch_state {
-	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
-	RCH_PASS_UP_MESSAGE,
-	RCH_PROCESSING_EXTENDED_MESSAGE,
-	RCH_REQUESTING_CHUNK,
-	RCH_WAITING_CHUNK,
-	RCH_REPORT_ERROR,
-};
-
-/* Chunked Tx states (Section 6.11.2.1.3) */
-enum usb_tch_state {
-	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
-	TCH_WAIT_FOR_TRANSMISSION_COMPLETE,
-	TCH_CONSTRUCT_CHUNKED_MESSAGE,
-	TCH_SENDING_CHUNKED_MESSAGE,
-	TCH_WAIT_CHUNK_REQUEST,
-	TCH_MESSAGE_RECEIVED,
-	TCH_MESSAGE_SENT,
-	TCH_REPORT_ERROR,
-};
-
-static const char * const prl_tx_state_names[] = {
-	[PRL_TX_PHY_LAYER_RESET] = "PRL_TX_PHY_LAYER_RESET",
-	[PRL_TX_WAIT_FOR_MESSAGE_REQUEST] = "PRL_TX_WAIT_FOR_MESSAGE_REQUEST",
-	[PRL_TX_LAYER_RESET_FOR_TRANSMIT] = "PRL_TX_LAYER_RESET_FOR_TRANSMIT",
-	[PRL_TX_WAIT_FOR_PHY_RESPONSE] = "PRL_TX_WAIT_FOR_PHY_RESPONSE",
-	[PRL_TX_SRC_SOURCE_TX] = "PRL_TX_SRC_SOURCE_TX",
-	[PRL_TX_SNK_START_AMS] = "PRL_TX_SNK_START_AMS",
-	[PRL_TX_SRC_PENDING] = "PRL_TX_SRC_PENDING",
-	[PRL_TX_SNK_PENDING] = "PRL_TX_SNK_PENDING",
-	[PRL_TX_DISCARD_MESSAGE] = "PRL_TX_DISCARD_MESSAGE",
-};
-
-static const char * const prl_hr_state_names[] = {
-	[PRL_HR_WAIT_FOR_REQUEST] = "PRL_HR_WAIT_FOR_REQUEST",
-	[PRL_HR_RESET_LAYER] = "PRL_HR_RESET_LAYER",
-	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE",
-	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE",
-};
-
-__maybe_unused static const char * const rch_state_names[] = {
-	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER]
-		= "RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER",
-	[RCH_PASS_UP_MESSAGE] = "RCH_PASS_UP_MESSAGE",
-	[RCH_PROCESSING_EXTENDED_MESSAGE] = "RCH_PROCESSING_EXTENDED_MESSAGE",
-	[RCH_REQUESTING_CHUNK] = "RCH_REQUESTING_CHUNK",
-	[RCH_WAITING_CHUNK] = "RCH_WAITING_CHUNK",
-	[RCH_REPORT_ERROR] = "RCH_REPORT_ERROR",
-};
-
-__maybe_unused static const char * const tch_state_names[] = {
-	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE]
-		= "TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE",
-	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE]
-		= "TCH_WAIT_FOR_TRANSMISSION_COMPLETE",
-	[TCH_CONSTRUCT_CHUNKED_MESSAGE] = "TCH_CONSTRUCT_CHUNKED_MESSAGE",
-	[TCH_SENDING_CHUNKED_MESSAGE] = "TCH_SENDING_CHUNKED_MESSAGE",
-	[TCH_WAIT_CHUNK_REQUEST] = "TCH_WAIT_CHUNK_REQUEST",
-	[TCH_MESSAGE_RECEIVED] = "TCH_MESSAGE_RECEIVED",
-	[TCH_MESSAGE_SENT] = "TCH_MESSAGE_SENT",
-	[TCH_REPORT_ERROR] = "TCH_REPORT_ERROR",
-};
-
-/* Forward declare full list of states. Index by above enums. */
-static const struct usb_state prl_tx_states[];
-static const struct usb_state prl_hr_states[];
-
-__maybe_unused static const struct usb_state rch_states[];
-__maybe_unused static const struct usb_state tch_states[];
-
-/* Chunked Rx State Machine Object */
-static struct rx_chunked {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* PRL_FLAGS */
-	uint32_t flags;
-	/* error to report when moving to rch_report_error state */
-	enum pe_error error;
-} rch[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Chunked Tx State Machine Object */
-static struct tx_chunked {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* state machine flags */
-	uint32_t flags;
-	/* error to report when moving to tch_report_error state */
-	enum pe_error error;
-} tch[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Message Reception State Machine Object */
-static struct protocol_layer_rx {
-	/* received message type */
-	enum tcpci_msg_type sop;
-	/* message ids for all valid port partners */
-	int msg_id[NUM_SOP_STAR_TYPES];
-} prl_rx[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Message Transmission State Machine Object */
-static struct protocol_layer_tx {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* state machine flags */
-	uint32_t flags;
-	/* last message type we transmitted */
-	enum tcpci_msg_type last_xmit_type;
-	/* message id counters for all 6 port partners */
-	uint32_t msg_id_counter[NUM_SOP_STAR_TYPES];
-	/* transmit status */
-	int xmit_status;
-} prl_tx[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Hard Reset State Machine Object */
-static struct protocol_hard_reset {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* state machine flags */
-	uint32_t flags;
-} prl_hr[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Chunking Message Object */
-static struct pd_message {
-	/* message status flags */
-	uint32_t flags;
-	/* SOP* */
-	enum tcpci_msg_type xmit_type;
-	/* type of message */
-	uint8_t msg_type;
-	/* PD revision */
-	enum pd_rev_type rev[NUM_SOP_STAR_TYPES];
-	/* Number of 32-bit objects in chk_buf */
-	uint16_t data_objs;
-	/* temp chunk buffer */
-	uint32_t tx_chk_buf[CHK_BUF_SIZE];
-	uint32_t rx_chk_buf[CHK_BUF_SIZE];
-	uint32_t chunk_number_expected;
-	uint32_t num_bytes_received;
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	/* extended message */
-	uint8_t ext;
-	uint32_t chunk_number_to_send;
-	uint32_t send_offset;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-} pdmsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Common Protocol Layer Message Transmission */
-static void prl_tx_construct_message(int port);
-static void prl_rx_wait_for_phy_message(const int port, int evt);
-static void prl_copy_msg_to_buffer(int port);
-
-#ifndef CONFIG_USB_PD_REV30
-GEN_NOT_SUPPORTED(PRL_TX_SRC_SOURCE_TX);
-#define PRL_TX_SRC_SOURCE_TX PRL_TX_SRC_SOURCE_TX_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(PRL_TX_SNK_START_AMS);
-#define PRL_TX_SNK_START_AMS PRL_TX_SNK_START_AMS_NOT_SUPPORTED
-
-GEN_NOT_SUPPORTED(RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-#define RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER \
-		RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(RCH_PASS_UP_MESSAGE);
-#define RCH_PASS_UP_MESSAGE RCH_PASS_UP_MESSAGE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(RCH_PROCESSING_EXTENDED_MESSAGE);
-#define RCH_PROCESSING_EXTENDED_MESSAGE \
-		RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(RCH_REQUESTING_CHUNK);
-#define RCH_REQUESTING_CHUNK RCH_REQUESTING_CHUNK_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(RCH_WAITING_CHUNK);
-#define RCH_WAITING_CHUNK RCH_WAITING_CHUNK_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(RCH_REPORT_ERROR);
-#define RCH_REPORT_ERROR RCH_REPORT_ERROR_NOT_SUPPORTED
-
-GEN_NOT_SUPPORTED(TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-#define TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE \
-		TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
-#define TCH_WAIT_FOR_TRANSMISSION_COMPLETE \
-		TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_CONSTRUCT_CHUNKED_MESSAGE);
-#define TCH_CONSTRUCT_CHUNKED_MESSAGE \
-		TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_SENDING_CHUNKED_MESSAGE);
-#define TCH_SENDING_CHUNKED_MESSAGE TCH_SENDING_CHUNKED_MESSAGE_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_WAIT_CHUNK_REQUEST);
-#define TCH_WAIT_CHUNK_REQUEST TCH_WAIT_CHUNK_REQUEST_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_MESSAGE_RECEIVED);
-#define TCH_MESSAGE_RECEIVED TCH_MESSAGE_RECEIVED_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_MESSAGE_SENT);
-#define TCH_MESSAGE_SENT TCH_MESSAGE_SENT_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TCH_REPORT_ERROR);
-#define TCH_REPORT_ERROR TCH_REPORT_ERROR_NOT_SUPPORTED
-#endif /* !CONFIG_USB_PD_REV30 */
-
-/* To store the time stamp when TCPC sets TX Complete Success */
-static timestamp_t tcpc_tx_success_ts[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Set the protocol transmit statemachine to a new state. */
-static void set_state_prl_tx(const int port,
-			     const enum usb_prl_tx_state new_state)
-{
-	set_state(port, &prl_tx[port].ctx, &prl_tx_states[new_state]);
-}
-
-/* Get the protocol transmit statemachine's current state. */
-test_export_static enum usb_prl_tx_state prl_tx_get_state(const int port)
-{
-	return prl_tx[port].ctx.current - &prl_tx_states[0];
-}
-
-/* Print the protocol transmit statemachine's current state. */
-static void print_current_prl_tx_state(const int port)
-{
-	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				prl_tx_state_names[prl_tx_get_state(port)]);
-}
-
-/* Set the hard reset statemachine to a new state. */
-static void set_state_prl_hr(const int port,
-			     const enum usb_prl_hr_state new_state)
-{
-	set_state(port, &prl_hr[port].ctx, &prl_hr_states[new_state]);
-}
-
-/* Get the hard reset statemachine's current state. */
-enum usb_prl_hr_state prl_hr_get_state(const int port)
-{
-	return prl_hr[port].ctx.current - &prl_hr_states[0];
-}
-
-/* Print the hard reset statemachine's current state. */
-static void print_current_prl_hr_state(const int port)
-{
-	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				prl_hr_state_names[prl_hr_get_state(port)]);
-}
-
-/* Set the chunked Rx statemachine to a new state. */
-static void set_state_rch(const int port, const enum usb_rch_state new_state)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-		set_state(port, &rch[port].ctx, &rch_states[new_state]);
-}
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-/* Get the chunked Rx statemachine's current state. */
-test_export_static enum usb_rch_state rch_get_state(const int port)
-{
-	return rch[port].ctx.current - &rch_states[0];
-}
-
-/* Print the chunked Rx statemachine's current state. */
-static void print_current_rch_state(const int port)
-{
-	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				rch_state_names[rch_get_state(port)]);
-}
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-/* Set the chunked Tx statemachine to a new state. */
-static void set_state_tch(const int port, const enum usb_tch_state new_state)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-		set_state(port, &tch[port].ctx, &tch_states[new_state]);
-}
-
-/* Get the chunked Tx statemachine's current state. */
-test_export_static enum usb_tch_state tch_get_state(const int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-		return tch[port].ctx.current - &tch_states[0];
-	else
-		return 0;
-}
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-/* Print the chunked Tx statemachine's current state. */
-static void print_current_tch_state(const int port)
-{
-	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				tch_state_names[tch_get_state(port)]);
-}
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-
-timestamp_t prl_get_tcpc_tx_success_ts(int port)
-{
-	return tcpc_tx_success_ts[port];
-}
-
-/* Sets the time stamp when TCPC reports TX success. */
-static void set_tcpc_tx_success_ts(int port)
-{
-	tcpc_tx_success_ts[port] = get_time();
-}
-
-void pd_transmit_complete(int port, int status)
-{
-	if (status == TCPC_TX_COMPLETE_SUCCESS)
-		set_tcpc_tx_success_ts(port);
-	prl_tx[port].xmit_status = status;
-}
-
-void pd_execute_hard_reset(int port)
-{
-	/* Only allow async. function calls when state machine is running */
-	if (!prl_is_running(port))
-		return;
-
-	PRL_HR_SET_FLAG(port, PRL_FLAGS_PORT_PARTNER_HARD_RESET);
-	set_state_prl_hr(port, PRL_HR_RESET_LAYER);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void prl_execute_hard_reset(int port)
-{
-	/* Only allow async. function calls when state machine is running */
-	if (!prl_is_running(port))
-		return;
-
-	PRL_HR_SET_FLAG(port, PRL_FLAGS_PE_HARD_RESET);
-	set_state_prl_hr(port, PRL_HR_RESET_LAYER);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-int prl_is_running(int port)
-{
-	return local_state[port] == SM_RUN;
-}
-
-static void prl_init(int port)
-{
-	int i;
-	const struct sm_ctx cleared = {};
-
-	/*
-	 * flags without PRL_FLAGS_SINK_NG present means we are initially
-	 * in SinkTxOK state
-	 */
-	prl_tx[port].flags = 0;
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		typec_select_src_collision_rp(port, SINK_TX_OK);
-	prl_tx[port].last_xmit_type = TCPCI_MSG_SOP;
-	prl_tx[port].xmit_status = TCPC_TX_UNSET;
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		tch[port].flags = 0;
-		rch[port].flags = 0;
-	}
-
-	pdmsg[port].flags = 0;
-
-	prl_hr[port].flags = 0;
-
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
-	}
-
-	pd_timer_disable_range(port, PR_TIMER_RANGE);
-
-	/* Clear state machines and set initial states */
-	prl_tx[port].ctx = cleared;
-	set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
-
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		rch[port].ctx = cleared;
-		set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-
-		tch[port].ctx = cleared;
-		set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-	}
-
-	prl_hr[port].ctx = cleared;
-	set_state_prl_hr(port, PRL_HR_WAIT_FOR_REQUEST);
-}
-
-bool prl_is_busy(int port)
-{
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	return rch_get_state(port) !=
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER ||
-		tch_get_state(port) !=
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE;
-#else
-	return false;
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-}
-
-void prl_set_debug_level(enum debug_level debug_level)
-{
-#ifndef CONFIG_USB_PD_DEBUG_LEVEL
-	prl_debug_level = debug_level;
-#endif
-}
-
-void prl_hard_reset_complete(int port)
-{
-	PRL_HR_SET_FLAG(port, PRL_FLAGS_HARD_RESET_COMPLETE);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void prl_send_ctrl_msg(int port,
-		      enum tcpci_msg_type type,
-		      enum pd_ctrl_msg_type msg)
-{
-	pdmsg[port].xmit_type = type;
-	pdmsg[port].msg_type = msg;
-	pdmsg[port].data_objs = 0;
-	tx_emsg[port].len = 0;
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	pdmsg[port].ext = 0;
-
-	TCH_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#else
-	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void prl_send_data_msg(int port,
-		      enum tcpci_msg_type type,
-		      enum pd_data_msg_type msg)
-{
-	pdmsg[port].xmit_type = type;
-	pdmsg[port].msg_type = msg;
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	pdmsg[port].ext = 0;
-
-	TCH_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#else
-	prl_copy_msg_to_buffer(port);
-	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-void prl_send_ext_data_msg(int port,
-			  enum tcpci_msg_type type,
-			  enum pd_ext_msg_type msg)
-{
-	pdmsg[port].xmit_type = type;
-	pdmsg[port].msg_type = msg;
-	pdmsg[port].ext = 1;
-
-	TCH_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-void prl_set_default_pd_revision(int port)
-{
-	/*
-	 * Initialize to highest revision supported. If the port or cable
-	 * partner doesn't support this revision, the Protocol Engine will
-	 * lower this value to the revision supported by the partner.
-	 */
-	pdmsg[port].rev[TCPCI_MSG_SOP] = PD_REVISION;
-	pdmsg[port].rev[TCPCI_MSG_SOP_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPCI_MSG_SOP_PRIME_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPCI_MSG_SOP_DEBUG_PRIME] = PD_REVISION;
-	pdmsg[port].rev[TCPCI_MSG_SOP_DEBUG_PRIME_PRIME] = PD_REVISION;
-}
-
-void prl_reset_soft(int port)
-{
-	/* Do not change negotiated PD Revision Specification level */
-	local_state[port] = SM_INIT;
-
-	/* Ensure we process the reset quickly */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void prl_run(int port, int evt, int en)
-{
-	switch (local_state[port]) {
-	case SM_PAUSED:
-		if (!en)
-			break;
-		/* fall through */
-	case SM_INIT:
-		prl_init(port);
-		local_state[port] = SM_RUN;
-		/* fall through */
-	case SM_RUN:
-		if (!en) {
-			/* Disable RX */
-			if (IS_ENABLED(CONFIG_USB_CTVPD) ||
-			    IS_ENABLED(CONFIG_USB_VPD))
-				vpd_rx_enable(0);
-			else
-				tcpm_set_rx_enable(port, 0);
-
-			local_state[port] = SM_PAUSED;
-			break;
-		}
-
-		/* Run Protocol Layer Hard Reset state machine */
-		run_state(port, &prl_hr[port].ctx);
-
-		/*
-		 * If the Hard Reset state machine is active, then there is no
-		 * need to execute any other PRL state machines. When the hard
-		 * reset is complete, all PRL state machines will have been
-		 * reset.
-		 */
-		if (prl_hr_get_state(port) == PRL_HR_WAIT_FOR_REQUEST) {
-
-			/* Run Protocol Layer Message Reception */
-			prl_rx_wait_for_phy_message(port, evt);
-
-
-			if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-				/*
-				 * Run RX Chunked state machine after prl_rx.
-				 * This is what informs the PE of incoming
-				 * message. Its input is prl_rx
-				 */
-				run_state(port, &rch[port].ctx);
-
-				/*
-				 * Run TX Chunked state machine before prl_tx
-				 * in case we need to split an extended message
-				 * and prl_tx can send it for us
-				 */
-				run_state(port, &tch[port].ctx);
-			}
-
-			/* Run Protocol Layer Message Tx state machine */
-			run_state(port, &prl_tx[port].ctx);
-
-			if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-				/*
-				 * Run TX Chunked state machine again after
-				 * prl_tx so we can handle passing TX_COMPLETE
-				 * (or failure) up to PE in a single iteration.
-				 */
-				run_state(port, &tch[port].ctx);
-		}
-		break;
-	}
-}
-
-void prl_set_rev(int port, enum tcpci_msg_type type,
-						enum pd_rev_type rev)
-{
-	/* We only store revisions for SOP* types. */
-	ASSERT(type < NUM_SOP_STAR_TYPES);
-
-	pdmsg[port].rev[type] = rev;
-}
-
-enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type)
-{
-	/* We only store revisions for SOP* types. */
-	ASSERT(type < NUM_SOP_STAR_TYPES);
-
-	return pdmsg[port].rev[type];
-}
-
-static void prl_copy_msg_to_buffer(int port)
-{
-	/*
-	 * Control Messages will have a length of 0 and
-	 * no need to spend time with the tx_chk_buf
-	 * for this path
-	 */
-	if (tx_emsg[port].len == 0) {
-		pdmsg[port].data_objs = 0;
-		return;
-	}
-
-	/*
-	 * Make sure the Policy Engine isn't sending
-	 * more than CHK_BUF_SIZE_BYTES. If so,
-	 * truncate len. This will surely send a
-	 * malformed packet resulting in the port
-	 * partner soft\hard resetting us.
-	 */
-	if (tx_emsg[port].len > CHK_BUF_SIZE_BYTES)
-		tx_emsg[port].len = CHK_BUF_SIZE_BYTES;
-
-	/* Copy message to chunked buffer */
-	memset((uint8_t *)pdmsg[port].tx_chk_buf, 0, CHK_BUF_SIZE_BYTES);
-	memcpy((uint8_t *)pdmsg[port].tx_chk_buf, (uint8_t *)tx_emsg[port].buf,
-		tx_emsg[port].len);
-	/*
-	 * Pad length to 4-byte boundary and
-	 * convert to number of 32-bit objects.
-	 * Since the value is shifted right by 2,
-	 * no need to explicitly clear the lower
-	 * 2-bits.
-	 */
-	pdmsg[port].data_objs = (tx_emsg[port].len + 3) >> 2;
-}
-
-static __maybe_unused int pdmsg_xmit_type_is_rev30(const int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES)
-		&& (prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30));
-	else
-		return 0;
-}
-
-/* Returns true if the SOP port partner operates at PD rev3.0 */
-static bool is_sop_rev30(const int port)
-{
-	return IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	       prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV30;
-}
-
-/* Common Protocol Layer Message Transmission */
-static void prl_tx_phy_layer_reset_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	if (IS_ENABLED(CONFIG_USB_CTVPD)
-	 || IS_ENABLED(CONFIG_USB_VPD)) {
-		vpd_rx_enable(pd_is_connected(port));
-	} else {
-		/* Note: can't clear PHY messages due to TCPC architecture */
-		/* Enable communications*/
-		tcpm_set_rx_enable(port, pd_is_connected(port));
-	}
-	set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-}
-
-static void prl_tx_wait_for_message_request_entry(const int port)
-{
-	/* No phy layer response is pending */
-	prl_tx[port].xmit_status = TCPC_TX_UNSET;
-	print_current_prl_tx_state(port);
-}
-
-static void prl_tx_wait_for_message_request_run(const int port)
-{
-	/* Clear any AMS flags and state if we are no longer in an AMS */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) && !pe_in_local_ams(port)) {
-		/* Note PRL_Tx_Src_Sink_Tx is embedded here. */
-		if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_SINK_NG)) {
-			typec_select_src_collision_rp(port, SINK_TX_OK);
-			typec_update_cc(port);
-		}
-		PRL_TX_CLR_FLAG(port,
-				PRL_FLAGS_SINK_NG | PRL_FLAGS_WAIT_SINK_OK);
-	}
-
-	/*
-	 * Check if we are starting an AMS and need to wait and/or set the CC
-	 * lines appropriately.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) && is_sop_rev30(port) &&
-	    pe_in_local_ams(port)) {
-		if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_SINK_NG |
-					  PRL_FLAGS_WAIT_SINK_OK)) {
-			/*
-			 * If we are already in an AMS then allow the
-			 * multi-message AMS to continue, even if we
-			 * swap power roles.
-			 *
-			 * Fall Through using the current AMS
-			 */
-		} else {
-			/*
-			 * Start of SRC AMS notification received from
-			 * Policy Engine
-			 */
-			if (pd_get_power_role(port) == PD_ROLE_SOURCE) {
-				PRL_TX_SET_FLAG(port, PRL_FLAGS_SINK_NG);
-				set_state_prl_tx(port, PRL_TX_SRC_SOURCE_TX);
-			} else {
-				PRL_TX_SET_FLAG(port, PRL_FLAGS_WAIT_SINK_OK);
-				set_state_prl_tx(port, PRL_TX_SNK_START_AMS);
-			}
-			return;
-		}
-	}
-
-	/* Handle non Rev 3.0 or subsequent messages in AMS sequence */
-	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-		PRL_TX_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-		/*
-		 * Soft Reset Message Message pending
-		 */
-		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-						(tx_emsg[port].len == 0)) {
-			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
-		}
-		/*
-		 * Message pending (except Soft Reset)
-		 */
-		else {
-			/* NOTE: PRL_TX_Construct_Message State embedded here */
-			prl_tx_construct_message(port);
-			set_state_prl_tx(port, PRL_TX_WAIT_FOR_PHY_RESPONSE);
-		}
-
-		return;
-	}
-}
-
-static void increment_msgid_counter(int port)
-{
-	/* If the last message wasn't an SOP* message, no need to increment */
-	if (prl_tx[port].last_xmit_type >= NUM_SOP_STAR_TYPES)
-		return;
-
-	prl_tx[port].msg_id_counter[prl_tx[port].last_xmit_type] =
-		(prl_tx[port].msg_id_counter[prl_tx[port].last_xmit_type] + 1) &
-		PD_MESSAGE_ID_COUNT;
-}
-
-/*
- * PrlTxDiscard
- */
-static void prl_tx_discard_message_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	/*
-	 * Discard queued message
-	 * Note: We differ from spec here, which allows us to not discard on
-	 * incoming SOP' or SOP''.  However this would get the TCH out of sync.
-	 *
-	 * prl_tx will be set to this state following message reception in
-	 * prl_rx. So this path will be entered following each rx message. If
-	 * this state is entered, and there is either a message from the PE
-	 * pending, or if a message was passed to the phy and there is either no
-	 * response yet, or it was discarded in the phy layer, then a tx message
-	 * discard event has been detected.
-	 */
-	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT) ||
-	    prl_tx[port].xmit_status == TCPC_TX_WAIT ||
-	    prl_tx[port].xmit_status == TCPC_TX_COMPLETE_DISCARDED) {
-		PRL_TX_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-		increment_msgid_counter(port);
-		pe_report_discard(port);
-	}
-
-	set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
-}
-
-#ifdef CONFIG_USB_PD_REV30
-/*
- * PrlTxSrcSourceTx
- */
-static void prl_tx_src_source_tx_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	/* Set Rp = SinkTxNG */
-	typec_select_src_collision_rp(port, SINK_TX_NG);
-	typec_update_cc(port);
-}
-
-static void prl_tx_src_source_tx_run(const int port)
-{
-	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-		/*
-		 * Don't clear pending XMIT flag here. Wait until we send so
-		 * we can detect if we dropped this message or not.
-		 */
-		set_state_prl_tx(port, PRL_TX_SRC_PENDING);
-	}
-}
-
-/*
- * PrlTxSnkStartAms
- */
-static void prl_tx_snk_start_ams_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-}
-
-static void prl_tx_snk_start_ams_run(const int port)
-{
-	if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-		/*
-		 * Don't clear pending XMIT flag here. Wait until we send so
-		 * we can detect if we dropped this message or not.
-		 */
-		set_state_prl_tx(port, PRL_TX_SNK_PENDING);
-	}
-}
-#endif /* CONFIG_USB_PD_REV30 */
-
-/*
- * PrlTxLayerResetForTransmit
- */
-static void prl_tx_layer_reset_for_transmit_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	if (pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) {
-		/*
-		 * This state is only used during soft resets. Reset only the
-		 * matching message type.
-		 *
-		 * From section 6.3.13 Soft Reset Message in the USB PD 3.0
-		 * v2.0 spec, Soft_Reset Message Shall be targeted at a
-		 * specific entity depending on the type of SOP* Packet used.
-		 */
-		prl_tx[port].msg_id_counter[pdmsg[port].xmit_type] = 0;
-
-		/*
-		 * From section 6.11.2.3.2, the MessageID should be cleared
-		 * from the PRL_Rx_Layer_Reset_for_Receive state. However, we
-		 * don't implement a full state machine for PRL RX states so
-		 * clear the MessageID here.
-		 */
-		prl_rx[port].msg_id[pdmsg[port].xmit_type] = -1;
-	}
-}
-
-static void prl_tx_layer_reset_for_transmit_run(const int port)
-{
-	/* NOTE: PRL_Tx_Construct_Message State embedded here */
-	prl_tx_construct_message(port);
-	set_state_prl_tx(port, PRL_TX_WAIT_FOR_PHY_RESPONSE);
-}
-
-static uint32_t get_sop_star_header(const int port)
-{
-	const int is_sop_packet = pdmsg[port].xmit_type == TCPCI_MSG_SOP;
-	int ext;
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	ext = pdmsg[port].ext;
-#else
-	ext = 0;
-#endif
-
-	/* SOP vs SOP'/SOP" headers are different. Replace fields as needed */
-	return PD_HEADER(
-		pdmsg[port].msg_type,
-		is_sop_packet ?
-			pd_get_power_role(port) : tc_get_cable_plug(port),
-		is_sop_packet ?
-			pd_get_data_role(port) : 0,
-		prl_tx[port].msg_id_counter[pdmsg[port].xmit_type],
-		pdmsg[port].data_objs,
-		pdmsg[port].rev[pdmsg[port].xmit_type],
-		ext);
-}
-
-static void prl_tx_construct_message(const int port)
-{
-	/* The header is unused for hard reset, etc. */
-	const uint32_t header = pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES ?
-		get_sop_star_header(port) : 0;
-
-	/* Save SOP* so the correct msg_id_counter can be incremented */
-	prl_tx[port].last_xmit_type = pdmsg[port].xmit_type;
-
-	/* Indicate that a tx message is being passed to the phy layer */
-	prl_tx[port].xmit_status = TCPC_TX_WAIT;
-	/*
-	 * PRL_FLAGS_TX_COMPLETE could be set if this function is called before
-	 * the Policy Engine is informed of the previous transmission. Clear the
-	 * flag so that this message can be sent.
-	 */
-	PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-
-	/*
-	 * Pass message to PHY Layer. It handles retries in hardware as the EC
-	 * cannot handle the required timing ~ 1ms (tReceive + tRetry).
-	 *
-	 * Note if we ever start sending large, extendend messages, then we
-	 * should not retry those messages. We do not support that and probably
-	 * never will (since we support chunking).
-	 */
-	tcpm_transmit(port, pdmsg[port].xmit_type, header,
-		      pdmsg[port].tx_chk_buf);
-}
-
-/*
- * PrlTxWaitForPhyResponse
- */
-static void prl_tx_wait_for_phy_response_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	pd_timer_enable(port, PR_TIMER_TCPC_TX_TIMEOUT, PD_T_TCPC_TX_TIMEOUT);
-}
-
-static void prl_tx_wait_for_phy_response_run(const int port)
-{
-	/* Wait until TX is complete */
-
-	/*
-	 * NOTE: The TCPC will set xmit_status to TCPC_TX_COMPLETE_DISCARDED
-	 *       when a GoodCRC containing an incorrect MessageID is received.
-	 *       This condition satisfies the PRL_Tx_Match_MessageID state
-	 *       requirement.
-	 */
-
-	if (prl_tx[port].xmit_status == TCPC_TX_COMPLETE_SUCCESS) {
-		/* NOTE: PRL_TX_Message_Sent State embedded here. */
-		/* Increment messageId counter */
-		increment_msgid_counter(port);
-
-		/* Inform Policy Engine Message was sent */
-		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES))
-			PDMSG_SET_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-		else
-			pe_message_sent(port);
-
-		/*
-		 * This event reduces the time of informing the policy engine of
-		 * the transmission by one state machine cycle
-		 */
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-	} else if (pd_timer_is_expired(port, PR_TIMER_TCPC_TX_TIMEOUT) ||
-		   prl_tx[port].xmit_status == TCPC_TX_COMPLETE_FAILED) {
-		/*
-		 * NOTE: PRL_Tx_Transmission_Error State embedded
-		 * here.
-		 */
-
-		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-			/*
-			 * State tch_wait_for_transmission_complete will
-			 * inform policy engine of error
-			 */
-			PDMSG_SET_FLAG(port, PRL_FLAGS_TX_ERROR);
-		} else {
-			/* Report Error To Policy Engine */
-			pe_report_error(port, ERR_TCH_XMIT,
-					prl_tx[port].last_xmit_type);
-		}
-
-		/* Increment message id counter */
-		increment_msgid_counter(port);
-		set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-	}
-}
-
-static void prl_tx_wait_for_phy_response_exit(const int port)
-{
-	pd_timer_disable(port, PR_TIMER_TCPC_TX_TIMEOUT);
-}
-
-/* Source Protocol Layer Message Transmission */
-/*
- * PrlTxSrcPending
- */
-static void prl_tx_src_pending_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-
-	/* Start SinkTxTimer */
-	pd_timer_enable(port, PR_TIMER_SINK_TX, PD_T_SINK_TX);
-}
-
-static void prl_tx_src_pending_run(const int port)
-{
-	if (pd_timer_is_expired(port, PR_TIMER_SINK_TX)) {
-		/*
-		 * We clear the pending XMIT flag here right before we send so
-		 * we can detect if we discarded this message or not
-		 */
-		PRL_TX_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-
-		/*
-		 * Soft Reset Message pending &
-		 * SinkTxTimer timeout
-		 */
-		if ((tx_emsg[port].len == 0) &&
-			(pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) {
-			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
-		}
-		/* Message pending (except Soft Reset) &
-		 * SinkTxTimer timeout
-		 */
-		else {
-			prl_tx_construct_message(port);
-			set_state_prl_tx(port, PRL_TX_WAIT_FOR_PHY_RESPONSE);
-		}
-
-		return;
-	}
-}
-
-static void prl_tx_src_pending_exit(int port)
-{
-	pd_timer_disable(port, PR_TIMER_SINK_TX);
-}
-
-/*
- * PrlTxSnkPending
- */
-static void prl_tx_snk_pending_entry(const int port)
-{
-	print_current_prl_tx_state(port);
-}
-
-static void prl_tx_snk_pending_run(const int port)
-{
-	bool start_tx = false;
-
-	/*
-	 * Wait unit the SRC applies SINK_TX_OK so we can transmit. In FRS mode,
-	 * don't wait for SINK_TX_OK since either the source (and Rp) could be
-	 * gone or the TCPC CC_STATUS update time could be too long to meet
-	 * tFRSwapInit.
-	 */
-	if (pe_in_frs_mode(port)) {
-		/* shortcut to save some i2c_xfer calls on the FRS path. */
-		start_tx = true;
-	} else {
-		enum tcpc_cc_voltage_status cc1, cc2;
-
-		tcpm_get_cc(port, &cc1, &cc2);
-		start_tx = (cc1 == TYPEC_CC_VOLT_RP_3_0 ||
-			    cc2 == TYPEC_CC_VOLT_RP_3_0);
-	}
-	if (start_tx) {
-		/*
-		 * We clear the pending XMIT flag here right before we send so
-		 * we can detect if we discarded this message or not
-		 */
-		PRL_TX_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-
-		/*
-		 * Soft Reset Message Message pending &
-		 * Rp = SinkTxOk
-		 */
-		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-					(tx_emsg[port].len == 0)) {
-			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
-		}
-		/*
-		 * Message pending (except Soft Reset) &
-		 * Rp = SinkTxOk
-		 */
-		else {
-			prl_tx_construct_message(port);
-			set_state_prl_tx(port, PRL_TX_WAIT_FOR_PHY_RESPONSE);
-		}
-		return;
-	}
-}
-
-/* Hard Reset Operation */
-void prl_hr_send_msg_to_phy(const int port)
-{
-	/* Header is not used for hard reset */
-	const uint32_t header = 0;
-
-	pdmsg[port].xmit_type = TCPCI_MSG_TX_HARD_RESET;
-
-	/*
-	 * These flags could be set if this function is called before the
-	 * Policy Engine is informed of the previous transmission. Clear the
-	 * flags so that this message can be sent.
-	 */
-	prl_tx[port].xmit_status = TCPC_TX_UNSET;
-	PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-
-	/* Pass message to PHY Layer */
-	tcpm_transmit(port, pdmsg[port].xmit_type, header,
-		      pdmsg[port].tx_chk_buf);
-}
-
-static void prl_hr_wait_for_request_entry(const int port)
-{
-	print_current_prl_hr_state(port);
-
-	prl_hr[port].flags = 0;
-}
-
-static void prl_hr_wait_for_request_run(const int port)
-{
-	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET |
-				PRL_FLAGS_PORT_PARTNER_HARD_RESET))
-		set_state_prl_hr(port, PRL_HR_RESET_LAYER);
-}
-
-/*
- * PrlHrResetLayer
- */
-static void prl_hr_reset_layer_entry(const int port)
-{
-	int i;
-
-	print_current_prl_hr_state(port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		tch[port].flags = 0;
-		rch[port].flags = 0;
-	}
-
-	pdmsg[port].flags = 0;
-
-	/* Hard reset resets messageIDCounters for all TX types */
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
-	}
-
-	/* Disable RX */
-	if (IS_ENABLED(CONFIG_USB_CTVPD) ||
-	    IS_ENABLED(CONFIG_USB_VPD))
-		vpd_rx_enable(0);
-	else
-		tcpm_set_rx_enable(port, 0);
-
-	/*
-	 * PD r3.0 v2.0, ss6.2.1.1.5:
-	 * After a physical or logical (USB Type-C Error Recovery) Attach, a
-	 * Port discovers the common Specification Revision level between itself
-	 * and its Port Partner and/or the Cable Plug(s), and uses this
-	 * Specification Revision level until a Detach, Hard Reset or Error
-	 * Recovery happens.
-	 *
-	 * This covers the Hard Reset case.
-	 */
-	prl_set_default_pd_revision(port);
-
-	/* Inform the AP of Hard Reset */
-	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD))
-		pd_notify_event(port, PD_STATUS_EVENT_HARD_RESET);
-
-	/*
-	 * Protocol Layer message transmission transitions to
-	 * PRL_Tx_Wait_For_Message_Request state.
-	 */
-	set_state_prl_tx(port, PRL_TX_WAIT_FOR_MESSAGE_REQUEST);
-
-	return;
-}
-
-static void prl_hr_reset_layer_run(const int port)
-{
-	/*
-	 * Protocol Layer reset Complete &
-	 * Hard Reset was initiated by Policy Engine
-	 */
-	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET)) {
-		/*
-		 * Request PHY to perform a Hard Reset. Note
-		 * PRL_HR_Request_Reset state is embedded here.
-		 */
-		prl_hr_send_msg_to_phy(port);
-		set_state_prl_hr(port, PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE);
-	}
-	/*
-	 * Protocol Layer reset complete &
-	 * Hard Reset was initiated by Port Partner
-	 */
-	else {
-		/* Inform Policy Engine of the Hard Reset */
-		pe_got_hard_reset(port);
-		set_state_prl_hr(port, PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE);
-	}
-}
-
-/*
- * PrlHrWaitForPhyHardResetComplete
- */
-static void prl_hr_wait_for_phy_hard_reset_complete_entry(const int port)
-{
-	print_current_prl_hr_state(port);
-
-	/* Start HardResetCompleteTimer */
-	pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE,
-			PD_T_PS_HARD_RESET);
-}
-
-static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port)
-{
-	/*
-	 * Wait for hard reset from PHY
-	 * or timeout
-	 */
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE) ||
-	    pd_timer_is_expired(port, PR_TIMER_HARD_RESET_COMPLETE)) {
-		/* PRL_HR_PHY_Hard_Reset_Requested */
-
-		/* Inform Policy Engine Hard Reset was sent */
-		pe_hard_reset_sent(port);
-		set_state_prl_hr(port, PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE);
-
-		return;
-	}
-}
-
-static void prl_hr_wait_for_phy_hard_reset_complete_exit(int port)
-{
-	pd_timer_disable(port, PR_TIMER_HARD_RESET_COMPLETE);
-}
-
-/*
- * PrlHrWaitForPeHardResetComplete
- */
-static void prl_hr_wait_for_pe_hard_reset_complete_entry(const int port)
-{
-	print_current_prl_hr_state(port);
-}
-
-static void prl_hr_wait_for_pe_hard_reset_complete_run(const int port)
-{
-	/*
-	 * Wait for Hard Reset complete indication from Policy Engine
-	 */
-	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_HARD_RESET_COMPLETE))
-		set_state_prl_hr(port, PRL_HR_WAIT_FOR_REQUEST);
-}
-
-static void prl_hr_wait_for_pe_hard_reset_complete_exit(const int port)
-{
-	/* Exit from Hard Reset */
-
-	set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-		set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-	}
-}
-
-static void copy_chunk_to_ext(int port)
-{
-	/* Calculate number of bytes */
-	pdmsg[port].num_bytes_received =
-				(PD_HEADER_CNT(rx_emsg[port].header) * 4);
-
-	/* Copy chunk into extended message */
-	memcpy((uint8_t *)rx_emsg[port].buf, (uint8_t *)pdmsg[port].rx_chk_buf,
-		pdmsg[port].num_bytes_received);
-
-	/* Set extended message length */
-	rx_emsg[port].len = pdmsg[port].num_bytes_received;
-}
-
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-/*
- * Chunked Rx State Machine
- */
-/*
- * RchWaitForMessageFromProtocolLayer
- */
-static void rch_wait_for_message_from_protocol_layer_entry(const int port)
-{
-	print_current_rch_state(port);
-
-	/* Clear Abort flag */
-	PDMSG_CLR_FLAG(port, PRL_FLAGS_ABORT);
-
-	/* All Messages are chunked */
-	rch[port].flags = PRL_FLAGS_CHUNKING;
-}
-
-static void rch_wait_for_message_from_protocol_layer_run(const int port)
-{
-	if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		RCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		/*
-		 * Are we communicating with a PD3.0 device and is
-		 * this an extended message?
-		 */
-		if (pdmsg_xmit_type_is_rev30(port)
-		    && PD_HEADER_EXT(rx_emsg[port].header)) {
-			uint16_t exhdr =
-					GET_EXT_HEADER(*pdmsg[port].rx_chk_buf);
-			uint8_t chunked = PD_EXT_HEADER_CHUNKED(exhdr);
-
-			/*
-			 * Received Extended Message &
-			 * (Chunking = 1 & Chunked = 1)
-			 */
-			if ((RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) &&
-								chunked) {
-				/*
-				 * RCH_Processing_Extended_Message first chunk
-				 * entry processing embedded here
-				 *
-				 * This is the first chunk:
-				 * Set Chunk_number_expected = 0 and
-				 * Num_Bytes_Received = 0
-				 */
-				pdmsg[port].chunk_number_expected = 0;
-				pdmsg[port].num_bytes_received = 0;
-				pdmsg[port].msg_type =
-					PD_HEADER_TYPE(rx_emsg[port].header);
-
-				set_state_rch(port,
-					      RCH_PROCESSING_EXTENDED_MESSAGE);
-			}
-			/*
-			 * (Received Extended Message &
-			 * (Chunking = 0 & Chunked = 0))
-			 */
-			else if (!RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING) &&
-								!chunked) {
-				/* Copy chunk to extended buffer */
-				copy_chunk_to_ext(port);
-				set_state_rch(port, RCH_PASS_UP_MESSAGE);
-			}
-			/*
-			 * Chunked != Chunking
-			 */
-			else {
-				rch[port].error = ERR_RCH_CHUNKED;
-				set_state_rch(port, RCH_REPORT_ERROR);
-			}
-		}
-		/*
-		 * Received Non-Extended Message
-		 */
-		else if (!PD_HEADER_EXT(rx_emsg[port].header)) {
-			/* Copy chunk to extended buffer */
-			copy_chunk_to_ext(port);
-			set_state_rch(port, RCH_PASS_UP_MESSAGE);
-		}
-		/*
-		 * Received an Extended Message while communicating at a
-		 * revision lower than PD3.0
-		 */
-		else {
-			rch[port].error = ERR_RCH_CHUNKED;
-			set_state_rch(port, RCH_REPORT_ERROR);
-		}
-	}
-}
-
-/*
- * RchPassUpMessage
- */
-static void rch_pass_up_message_entry(const int port)
-{
-	print_current_rch_state(port);
-
-	/* Pass Message to Policy Engine */
-	pe_message_received(port);
-	set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-}
-
-/*
- * RchProcessingExtendedMessage
- */
-static void rch_processing_extended_message_entry(const int port)
-{
-	print_current_rch_state(port);
-}
-
-static void rch_processing_extended_message_run(const int port)
-{
-	uint16_t exhdr = GET_EXT_HEADER(pdmsg[port].rx_chk_buf[0]);
-	uint8_t chunk_num = PD_EXT_HEADER_CHUNK_NUM(exhdr);
-	uint32_t data_size = PD_EXT_HEADER_DATA_SIZE(exhdr);
-	uint32_t byte_num;
-
-	/*
-	 * Abort Flag Set
-	 */
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_ABORT))
-		set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-
-	/*
-	 * If expected Chunk Number:
-	 *   Append data to Extended_Message_Buffer
-	 *   Increment Chunk_number_Expected
-	 *   Adjust Num Bytes Received
-	 */
-	else if (chunk_num == pdmsg[port].chunk_number_expected) {
-		byte_num = data_size - pdmsg[port].num_bytes_received;
-
-		if (byte_num >= PD_MAX_EXTENDED_MSG_CHUNK_LEN)
-			byte_num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-		/* Make sure extended message buffer does not overflow */
-		if (pdmsg[port].num_bytes_received +
-					byte_num > EXTENDED_BUFFER_SIZE) {
-			rch[port].error = ERR_RCH_CHUNKED;
-			set_state_rch(port, RCH_REPORT_ERROR);
-			return;
-		}
-
-		/* Append data */
-		/* Add 2 to chk_buf to skip over extended message header */
-		memcpy(((uint8_t *)rx_emsg[port].buf +
-				pdmsg[port].num_bytes_received),
-				(uint8_t *)pdmsg[port].rx_chk_buf + 2,
-				byte_num);
-		/* increment chunk number expected */
-		pdmsg[port].chunk_number_expected++;
-		/* adjust num bytes received */
-		pdmsg[port].num_bytes_received += byte_num;
-
-		/* Was that the last chunk? */
-		if (pdmsg[port].num_bytes_received >= data_size) {
-			rx_emsg[port].len = pdmsg[port].num_bytes_received;
-			 /* Pass Message to Policy Engine */
-			set_state_rch(port, RCH_PASS_UP_MESSAGE);
-		}
-		/*
-		 * Message not Complete
-		 */
-		else
-			set_state_rch(port, RCH_REQUESTING_CHUNK);
-	}
-	/*
-	 * Unexpected Chunk Number
-	 */
-	else {
-		rch[port].error = ERR_RCH_CHUNKED;
-		set_state_rch(port, RCH_REPORT_ERROR);
-	}
-}
-
-/*
- * RchRequestingChunk
- */
-static void rch_requesting_chunk_entry(const int port)
-{
-	print_current_rch_state(port);
-
-	/*
-	 * Send Chunk Request to Protocol Layer
-	 * with chunk number = Chunk_Number_Expected
-	 */
-	pdmsg[port].tx_chk_buf[0] = PD_EXT_HEADER(
-				pdmsg[port].chunk_number_expected,
-				1, /* Request Chunk */
-				0 /* Data Size */
-				);
-
-	pdmsg[port].data_objs = 1;
-	pdmsg[port].ext = 1;
-	pdmsg[port].xmit_type = prl_rx[port].sop;
-	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
-}
-
-static void rch_requesting_chunk_run(const int port)
-{
-	/*
-	 * Message Transmitted received from Protocol Layer
-	 */
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE)) {
-		PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-		set_state_rch(port, RCH_WAITING_CHUNK);
-	} else if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_ERROR)) {
-		/* Transmission Error from Protocol Layer detetected */
-		rch[port].error = ERR_RCH_CHUNKED;
-		set_state_rch(port, RCH_REPORT_ERROR);
-	} else if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		/*
-		 * It is possible to have both message received and the chunk
-		 * request transmit complete before a full PRL SM run. But, the
-		 * PRL_RX state machine runs prior to RCH, but before PRL_TX, so
-		 * PRL_FLAGS_MSG_RECEIVED can be set without
-		 * PRL_FLAGS_TX_COMPLETE set at this point (though it will be
-		 * set as soon as PRL_TX is executed next.
-		 */
-		set_state_rch(port, RCH_WAITING_CHUNK);
-	}
-}
-
-/*
- * RchWaitingChunk
- */
-static void rch_waiting_chunk_entry(const int port)
-{
-	print_current_rch_state(port);
-
-	/*
-	 * Start ChunkSenderResponseTimer
-	 */
-	pd_timer_enable(port, PR_TIMER_CHUNK_SENDER_RESPONSE,
-			PD_T_CHUNK_SENDER_RESPONSE);
-}
-
-static void rch_waiting_chunk_run(const int port)
-{
-	if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		/*
-		 * Because of the 5 msec tick time, it is possible to have both
-		 * msg_received and tx_complete flags set for a given PRL sm
-		 * run. Since prl_rx runs prior to the tx state machines, clear
-		 * the tx_complete flag as the next chunk has already been
-		 * received.
-		 */
-		if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE))
-			PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-
-		/*
-		 * Leave PRL_FLAGS_MSG_RECEIVED flag set just in case an error
-		 * is detected. If an error is detected, PRL_FLAGS_MSG_RECEIVED
-		 * will be cleared in rch_report_error state.
-		 */
-
-		if (PD_HEADER_EXT(rx_emsg[port].header)) {
-			uint16_t exhdr =
-				GET_EXT_HEADER(pdmsg[port].rx_chk_buf[0]);
-			/*
-			 * Other Message Received from Protocol Layer
-			 */
-			if (PD_EXT_HEADER_REQ_CHUNK(exhdr) ||
-			    !PD_EXT_HEADER_CHUNKED(exhdr)) {
-				rch[port].error = ERR_RCH_CHUNKED;
-				set_state_rch(port, RCH_REPORT_ERROR);
-			}
-			/*
-			 * Chunk response Received from Protocol Layer
-			 */
-			else {
-				/*
-				 * No error was detected, so clear
-				 * PRL_FLAGS_MSG_RECEIVED flag.
-				 */
-				RCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-				set_state_rch(port,
-					      RCH_PROCESSING_EXTENDED_MESSAGE);
-			}
-		}
-	}
-	/*
-	 * ChunkSenderResponseTimer Timeout
-	 */
-	else if (pd_timer_is_expired(port, PR_TIMER_CHUNK_SENDER_RESPONSE)) {
-		rch[port].error = ERR_RCH_CHUNK_WAIT_TIMEOUT;
-		set_state_rch(port, RCH_REPORT_ERROR);
-	}
-}
-
-static void rch_waiting_chunk_exit(int port)
-{
-	pd_timer_disable(port, PR_TIMER_CHUNK_SENDER_RESPONSE);
-}
-
-/*
- * RchReportError
- */
-static void rch_report_error_entry(const int port)
-{
-	print_current_rch_state(port);
-
-	/*
-	 * If the state was entered because a message was received,
-	 * this message is passed to the Policy Engine.
-	 */
-	if (RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		RCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-
-		/* Copy chunk to extended buffer */
-		copy_chunk_to_ext(port);
-		/* Pass Message to Policy Engine */
-		pe_message_received(port);
-		/* Report error */
-		pe_report_error(port, ERR_RCH_MSG_REC, prl_rx[port].sop);
-	} else {
-		pe_report_error(port, rch[port].error, prl_rx[port].sop);
-	}
-}
-
-static void rch_report_error_run(const int port)
-{
-	set_state_rch(port, RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-}
-
-/*
- * Chunked Tx State Machine
- */
-
-/*
- * TchWaitForMessageRequestFromPe
- */
-static void tch_wait_for_message_request_from_pe_entry(const int port)
-{
-	print_current_tch_state(port);
-
-	/* Clear Abort flag */
-	PDMSG_CLR_FLAG(port, PRL_FLAGS_ABORT);
-
-	/* All Messages are chunked */
-	tch[port].flags = PRL_FLAGS_CHUNKING;
-}
-
-static void tch_wait_for_message_request_from_pe_run(const int port)
-{
-	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-	} else if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-		/*
-		 * Rx Chunking State != RCH_Wait_For_Message_From_Protocol_Layer
-		 * & Abort Supported
-		 *
-		 * Discard the Message
-		 */
-		if (rch_get_state(port) !=
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) {
-			tch[port].error = ERR_TCH_XMIT;
-			set_state_tch(port, TCH_REPORT_ERROR);
-		} else {
-			/*
-			 * Extended Message Request & Chunking
-			 */
-			if (pdmsg_xmit_type_is_rev30(port)
-			    && pdmsg[port].ext
-			    && TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) {
-				/*
-				 * NOTE: TCH_Prepare_To_Send_Chunked_Message
-				 * embedded here.
-				 */
-				pdmsg[port].send_offset = 0;
-				pdmsg[port].chunk_number_to_send = 0;
-				set_state_tch(port,
-					      TCH_CONSTRUCT_CHUNKED_MESSAGE);
-			} else
-			/*
-			 * Non-Extended Message Request
-			 */
-			{
-				/* NOTE: TCH_Pass_Down_Message embedded here */
-				prl_copy_msg_to_buffer(port);
-
-				/* Pass Message to Protocol Layer */
-				PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-				set_state_tch(port,
-					TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
-			}
-		}
-	}
-}
-
-/*
- * TchWaitForTransmissionComplete
- */
-static void tch_wait_for_transmission_complete_entry(const int port)
-{
-	print_current_tch_state(port);
-}
-
-static void tch_wait_for_transmission_complete_run(const int port)
-{
-	/*
-	 * Inform Policy Engine that Message was sent.
-	 */
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_COMPLETE)) {
-		PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_COMPLETE);
-		set_state_tch(port, TCH_MESSAGE_SENT);
-		return;
-	}
-	/*
-	 * Inform Policy Engine of Tx Error
-	 */
-	else if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_ERROR)) {
-		PDMSG_CLR_FLAG(port, PRL_FLAGS_TX_ERROR);
-		tch[port].error = ERR_TCH_XMIT;
-		set_state_tch(port, TCH_REPORT_ERROR);
-		return;
-	}
-	/*
-	 * A message was received while TCH is waiting for the phy to complete
-	 * sending a tx message.
-	 *
-	 * Because of our prl_sm architecture and I2C access delays for TCPCs,
-	 * it's possible to have a message received and the prl_tx state not be
-	 * in its default waiting state. To avoid a false protocol error, only
-	 * jump to TCH_MESSAGE_RECEIVED if the phy layer has not indicated that
-	 * the tx message was sent successfully.
-	 */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED) &&
-	     prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-		return;
-	}
-}
-
-/*
- * TchConstructChunkedMessage
- */
-static void tch_construct_chunked_message_entry(const int port)
-{
-	uint16_t *ext_hdr;
-	uint8_t *data;
-	uint16_t num;
-
-	print_current_tch_state(port);
-
-	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-		return;
-	}
-
-	/* Prepare to copy chunk into chk_buf */
-
-	ext_hdr = (uint16_t *)pdmsg[port].tx_chk_buf;
-	data = ((uint8_t *)pdmsg[port].tx_chk_buf + 2);
-	num = tx_emsg[port].len - pdmsg[port].send_offset;
-
-	if (num > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
-		num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-	/* Set the chunks extended header */
-	*ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send,
-				 0, /* Chunk Request */
-				 tx_emsg[port].len);
-
-	/* Copy the message chunk into chk_buf */
-	memset(data, 0, 28);
-	memcpy(data, tx_emsg[port].buf + pdmsg[port].send_offset, num);
-	pdmsg[port].send_offset += num;
-
-	/*
-	 * Add in 2 bytes for extended header
-	 * pad out to 4-byte boundary
-	 * convert to number of 4-byte words
-	 * Since the value is shifted right by 2,
-	 * no need to explicitly clear the lower
-	 * 2-bits.
-	 */
-	pdmsg[port].data_objs = (num + 2 + 3) >> 2;
-
-	/* Pass message chunk to Protocol Layer */
-	PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-}
-
-static void tch_construct_chunked_message_run(const int port)
-{
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_ABORT))
-		set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-	else
-		set_state_tch(port, TCH_SENDING_CHUNKED_MESSAGE);
-}
-
-/*
- * TchSendingChunkedMessage
- */
-static void tch_sending_chunked_message_entry(const int port)
-{
-	print_current_tch_state(port);
-}
-
-static void tch_sending_chunked_message_run(const int port)
-{
-	/*
-	 * Transmission Error
-	 */
-	if (PDMSG_CHK_FLAG(port, PRL_FLAGS_TX_ERROR)) {
-		tch[port].error = ERR_TCH_XMIT;
-		set_state_tch(port, TCH_REPORT_ERROR);
-	}
-	/*
-	 * Message Transmitted from Protocol Layer &
-	 * Last Chunk
-	 */
-	else if (tx_emsg[port].len == pdmsg[port].send_offset)
-		set_state_tch(port, TCH_MESSAGE_SENT);
-	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 */
-	else if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-	}
-	/*
-	 * Message Transmitted from Protocol Layer &
-	 * Not Last Chunk
-	 */
-	else
-		set_state_tch(port, TCH_WAIT_CHUNK_REQUEST);
-}
-
-/*
- * TchWaitChunkRequest
- */
-static void tch_wait_chunk_request_entry(const int port)
-{
-	print_current_tch_state(port);
-
-	/* Increment Chunk Number to Send */
-	pdmsg[port].chunk_number_to_send++;
-	/* Start Chunk Sender Request Timer */
-	pd_timer_enable(port, PR_TIMER_CHUNK_SENDER_REQUEST,
-			PD_T_CHUNK_SENDER_REQUEST);
-}
-
-static void tch_wait_chunk_request_run(const int port)
-{
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-
-		if (PD_HEADER_EXT(rx_emsg[port].header)) {
-			uint16_t exthdr;
-
-			exthdr = GET_EXT_HEADER(pdmsg[port].rx_chk_buf[0]);
-			if (PD_EXT_HEADER_REQ_CHUNK(exthdr)) {
-				/*
-				 * Chunk Request Received &
-				 * Chunk Number = Chunk Number to Send
-				 */
-				if (PD_EXT_HEADER_CHUNK_NUM(exthdr) ==
-				    pdmsg[port].chunk_number_to_send) {
-					set_state_tch(port,
-						TCH_CONSTRUCT_CHUNKED_MESSAGE);
-				}
-				/*
-				 * Chunk Request Received &
-				 * Chunk Number != Chunk Number to Send
-				 */
-				else {
-					tch[port].error = ERR_TCH_CHUNKED;
-					set_state_tch(port, TCH_REPORT_ERROR);
-				}
-				return;
-			}
-		}
-
-		/*
-		 * Other message received
-		 */
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-	}
-	/*
-	 * ChunkSenderRequestTimer timeout
-	 */
-	else if (pd_timer_is_expired(port, PR_TIMER_CHUNK_SENDER_REQUEST))
-		set_state_tch(port, TCH_MESSAGE_SENT);
-}
-
-static void tch_wait_chunk_request_exit(int port)
-{
-	pd_timer_disable(port, PR_TIMER_CHUNK_SENDER_REQUEST);
-}
-
-/*
- * TchMessageReceived
- */
-static void tch_message_received_entry(const int port)
-{
-	print_current_tch_state(port);
-
-	/* Pass message to chunked Rx */
-	RCH_SET_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-
-	/* Clear extended message objects */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_XMIT);
-		pe_report_discard(port);
-	}
-	pdmsg[port].data_objs = 0;
-}
-
-static void tch_message_received_run(const int port)
-{
-	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-}
-
-/*
- * TchMessageSent
- */
-static void tch_message_sent_entry(const int port)
-{
-	print_current_tch_state(port);
-
-	/* Tell PE message was sent */
-	pe_message_sent(port);
-
-	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 * MUST be checked after notifying PE
-	 */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-		return;
-	}
-
-
-
-	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-}
-
-/*
- * TchReportError
- */
-static void tch_report_error_entry(const int port)
-{
-	print_current_tch_state(port);
-
-	/* Report Error To Policy Engine */
-	pe_report_error(port, tch[port].error, prl_tx[port].last_xmit_type);
-
-	/*
-	 * Any message received and not in state TCH_Wait_Chunk_Request
-	 * MUST be checked after notifying PE
-	 */
-	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED)) {
-		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		set_state_tch(port, TCH_MESSAGE_RECEIVED);
-		return;
-	}
-
-
-	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-}
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-
-/*
- * Protocol Layer Message Reception State Machine
- */
-static void prl_rx_wait_for_phy_message(const int port, int evt)
-{
-	uint32_t header;
-	uint8_t type;
-	uint8_t cnt;
-	int8_t msid;
-
-	/*
-	 * If PD3, wait for the RX chunk SM to copy the pdmsg into the extended
-	 * buffer before overwriting pdmsg.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-	    RCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED))
-		return;
-
-	/* If we don't have any message, just stop processing now. */
-	if (!tcpm_has_pending_message(port) ||
-	    tcpm_dequeue_message(port, pdmsg[port].rx_chk_buf, &header))
-		return;
-
-	rx_emsg[port].header = header;
-	type = PD_HEADER_TYPE(header);
-	cnt = PD_HEADER_CNT(header);
-	msid = PD_HEADER_ID(header);
-	prl_rx[port].sop = PD_HEADER_GET_SOP(header);
-
-	/* Make sure an incorrect count doesn't overflow the chunk buffer */
-	if (cnt > CHK_BUF_SIZE)
-		cnt = CHK_BUF_SIZE;
-
-	/* dump received packet content (only dump ping at debug level MAX) */
-	if ((prl_debug_level >= DEBUG_LEVEL_2 && type != PD_CTRL_PING) ||
-		prl_debug_level >= DEBUG_LEVEL_3) {
-		int p;
-
-		ccprintf("C%d: RECV %04x/%d ", port, header, cnt);
-		for (p = 0; p < cnt; p++)
-			ccprintf("[%d]%08x ", p, pdmsg[port].rx_chk_buf[p]);
-		ccprintf("\n");
-	}
-
-	/*
-	 * Ignore messages sent to the cable from our
-	 * port partner if we aren't Vconn powered device.
-	 */
-	if (!IS_ENABLED(CONFIG_USB_CTVPD) &&
-	    !IS_ENABLED(CONFIG_USB_VPD) &&
-	    PD_HEADER_GET_SOP(header) != TCPCI_MSG_SOP &&
-	    PD_HEADER_PROLE(header) == PD_PLUG_FROM_DFP_UFP)
-		return;
-
-	/* Handle incoming soft reset as special case */
-	if (cnt == 0 && type == PD_CTRL_SOFT_RESET) {
-		/* Clear MessageIdCounter */
-		prl_tx[port].msg_id_counter[prl_rx[port].sop] = 0;
-		/* Clear stored MessageID value */
-		prl_rx[port].msg_id[prl_rx[port].sop] = -1;
-
-		/* Soft Reset occurred */
-		set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
-
-		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-			set_state_rch(port,
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
-			set_state_tch(port,
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
-		}
-
-		/*
-		 * Inform Policy Engine of Soft Reset. Note perform this after
-		 * performing the protocol layer reset, otherwise we will lose
-		 * the PE's outgoing ACCEPT message to the soft reset.
-		 */
-		pe_got_soft_reset(port);
-
-		return;
-	}
-
-	/*
-	 * Ignore if this is a duplicate message. Stop processing.
-	 */
-	if (prl_rx[port].msg_id[prl_rx[port].sop] == msid)
-		return;
-
-	/*
-	 * Discard any pending tx message if this is
-	 * not a ping message (length must be checked to verify this is a
-	 * control message, rather than data)
-	 */
-	if ((cnt > 0) || (type != PD_CTRL_PING)) {
-		/*
-		 * Note: Spec dictates that we always go into
-		 * PRL_Tx_Discard_Message upon receivng a message.  However, due
-		 * to our TCPC architecture we may be receiving a transmit
-		 * complete at the same time as a response so only do this if a
-		 * message is pending.
-		 */
-		if (prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS ||
-		    PRL_TX_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT))
-			set_state_prl_tx(port, PRL_TX_DISCARD_MESSAGE);
-	}
-
-	/* Store Message Id */
-	prl_rx[port].msg_id[prl_rx[port].sop] = msid;
-
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		/* RTR Chunked Message Router States. */
-		/*
-		 * Received Ping from Protocol Layer
-		 */
-		if (cnt == 0 && type == PD_CTRL_PING) {
-			/* NOTE: RTR_PING State embedded here. */
-			rx_emsg[port].len = 0;
-			pe_message_received(port);
-			return;
-		}
-		/*
-		 * Message (not Ping) Received from
-		 * Protocol Layer & Doing Tx Chunks
-		 *
-		 * Also, handle the case where a message has been
-		 * queued for sending but a message is received before
-		 * tch_wait_for_message_request_from_pe has been run
-		 */
-		else if (tch_get_state(port) !=
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE ||
-			 TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
-			/* NOTE: RTR_TX_CHUNKS State embedded here. */
-			/*
-			 * Send Message to Tx Chunk
-			 * Chunk State Machine
-			 */
-			TCH_SET_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		}
-		/*
-		 * Message (not Ping) Received from
-		 * Protocol Layer & Not Doing Tx Chunks
-		 */
-		else {
-			/* NOTE: RTR_RX_CHUNKS State embedded here. */
-			/*
-			 * Send Message to Rx
-			 * Chunk State Machine
-			 */
-			RCH_SET_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
-		}
-	} else {
-		/* Copy chunk to extended buffer */
-		copy_chunk_to_ext(port);
-		/* Send message to Policy Engine */
-		pe_message_received(port);
-	}
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-/* All necessary Protocol Transmit States (Section 6.11.2.2) */
-static __const_data const struct usb_state prl_tx_states[] = {
-	[PRL_TX_PHY_LAYER_RESET] = {
-		.entry  = prl_tx_phy_layer_reset_entry,
-	},
-	[PRL_TX_WAIT_FOR_MESSAGE_REQUEST] = {
-		.entry  = prl_tx_wait_for_message_request_entry,
-		.run    = prl_tx_wait_for_message_request_run,
-	},
-	[PRL_TX_LAYER_RESET_FOR_TRANSMIT] = {
-		.entry  = prl_tx_layer_reset_for_transmit_entry,
-		.run    = prl_tx_layer_reset_for_transmit_run,
-	},
-	[PRL_TX_WAIT_FOR_PHY_RESPONSE] = {
-		.entry  = prl_tx_wait_for_phy_response_entry,
-		.run    = prl_tx_wait_for_phy_response_run,
-		.exit   = prl_tx_wait_for_phy_response_exit,
-	},
-#ifdef CONFIG_USB_PD_REV30
-	[PRL_TX_SRC_SOURCE_TX] = {
-		.entry  = prl_tx_src_source_tx_entry,
-		.run    = prl_tx_src_source_tx_run,
-	},
-	[PRL_TX_SNK_START_AMS] = {
-		.entry  = prl_tx_snk_start_ams_entry,
-		.run    = prl_tx_snk_start_ams_run,
-	},
-#endif /* CONFIG_USB_PD_REV30 */
-	[PRL_TX_SRC_PENDING] = {
-		.entry  = prl_tx_src_pending_entry,
-		.run    = prl_tx_src_pending_run,
-		.exit	= prl_tx_src_pending_exit,
-	},
-	[PRL_TX_SNK_PENDING] = {
-		.entry  = prl_tx_snk_pending_entry,
-		.run    = prl_tx_snk_pending_run,
-	},
-	[PRL_TX_DISCARD_MESSAGE] = {
-		.entry  = prl_tx_discard_message_entry,
-	},
-};
-
-/* All necessary Protocol Hard Reset States (Section 6.11.2.4) */
-static __const_data const struct usb_state prl_hr_states[] = {
-	[PRL_HR_WAIT_FOR_REQUEST] = {
-		.entry  = prl_hr_wait_for_request_entry,
-		.run    = prl_hr_wait_for_request_run,
-	},
-	[PRL_HR_RESET_LAYER] = {
-		.entry  = prl_hr_reset_layer_entry,
-		.run    = prl_hr_reset_layer_run,
-	},
-	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] = {
-		.entry  = prl_hr_wait_for_phy_hard_reset_complete_entry,
-		.run    = prl_hr_wait_for_phy_hard_reset_complete_run,
-		.exit	= prl_hr_wait_for_phy_hard_reset_complete_exit,
-	},
-	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] = {
-		.entry  = prl_hr_wait_for_pe_hard_reset_complete_entry,
-		.run    = prl_hr_wait_for_pe_hard_reset_complete_run,
-		.exit   = prl_hr_wait_for_pe_hard_reset_complete_exit,
-	},
-};
-
-/* All necessary Chunked Rx states (Section 6.11.2.1.2) */
-__maybe_unused static const struct usb_state rch_states[] = {
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] = {
-		.entry  = rch_wait_for_message_from_protocol_layer_entry,
-		.run    = rch_wait_for_message_from_protocol_layer_run,
-	},
-	[RCH_PASS_UP_MESSAGE] = {
-		.entry  = rch_pass_up_message_entry,
-	},
-	[RCH_PROCESSING_EXTENDED_MESSAGE] = {
-		.entry  = rch_processing_extended_message_entry,
-		.run    = rch_processing_extended_message_run,
-	},
-	[RCH_REQUESTING_CHUNK] = {
-		.entry  = rch_requesting_chunk_entry,
-		.run    = rch_requesting_chunk_run,
-	},
-	[RCH_WAITING_CHUNK] = {
-		.entry  = rch_waiting_chunk_entry,
-		.run    = rch_waiting_chunk_run,
-		.exit	= rch_waiting_chunk_exit,
-	},
-	[RCH_REPORT_ERROR] = {
-		.entry  = rch_report_error_entry,
-		.run    = rch_report_error_run,
-	},
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-};
-
-/* All necessary Chunked Tx states (Section 6.11.2.1.3) */
-__maybe_unused static const struct usb_state tch_states[] = {
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] = {
-		.entry  = tch_wait_for_message_request_from_pe_entry,
-		.run    = tch_wait_for_message_request_from_pe_run,
-	},
-	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE] = {
-		.entry  = tch_wait_for_transmission_complete_entry,
-		.run    = tch_wait_for_transmission_complete_run,
-	},
-	[TCH_CONSTRUCT_CHUNKED_MESSAGE] = {
-		.entry  = tch_construct_chunked_message_entry,
-		.run    = tch_construct_chunked_message_run,
-	},
-	[TCH_SENDING_CHUNKED_MESSAGE] = {
-		.entry  = tch_sending_chunked_message_entry,
-		.run    = tch_sending_chunked_message_run,
-	},
-	[TCH_WAIT_CHUNK_REQUEST] = {
-		.entry  = tch_wait_chunk_request_entry,
-		.run    = tch_wait_chunk_request_run,
-		.exit	= tch_wait_chunk_request_exit,
-	},
-	[TCH_MESSAGE_RECEIVED] = {
-		.entry  = tch_message_received_entry,
-		.run    = tch_message_received_run,
-	},
-	[TCH_MESSAGE_SENT] = {
-		.entry  = tch_message_sent_entry,
-	},
-	[TCH_REPORT_ERROR] = {
-		.entry  = tch_report_error_entry,
-	},
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-};
-
-#ifdef TEST_BUILD
-
-const struct test_sm_data test_prl_sm_data[] = {
-	{
-		.base = prl_tx_states,
-		.size = ARRAY_SIZE(prl_tx_states),
-		.names = prl_tx_state_names,
-		.names_size = ARRAY_SIZE(prl_tx_state_names),
-	},
-	{
-		.base = prl_hr_states,
-		.size = ARRAY_SIZE(prl_hr_states),
-		.names = prl_hr_state_names,
-		.names_size = ARRAY_SIZE(prl_hr_state_names),
-	},
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-	{
-		.base = rch_states,
-		.size = ARRAY_SIZE(rch_states),
-		.names = rch_state_names,
-		.names_size = ARRAY_SIZE(rch_state_names),
-	},
-	{
-		.base = tch_states,
-		.size = ARRAY_SIZE(tch_states),
-		.names = tch_state_names,
-		.names_size = ARRAY_SIZE(tch_state_names),
-	},
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-};
-BUILD_ASSERT(ARRAY_SIZE(prl_tx_states) == ARRAY_SIZE(prl_tx_state_names));
-BUILD_ASSERT(ARRAY_SIZE(prl_hr_states) == ARRAY_SIZE(prl_hr_state_names));
-#ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-BUILD_ASSERT(ARRAY_SIZE(rch_states) == ARRAY_SIZE(rch_state_names));
-BUILD_ASSERT(ARRAY_SIZE(tch_states) == ARRAY_SIZE(tch_state_names));
-#endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-const int test_prl_sm_data_size = ARRAY_SIZE(test_prl_sm_data);
-#endif
diff --git a/common/usbc/usb_retimer_fw_update.c b/common/usbc/usb_retimer_fw_update.c
deleted file mode 100644
index 1ff198c78f..0000000000
--- a/common/usbc/usb_retimer_fw_update.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "timer.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_tc_sm.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-/*
- * Retimer firmware update is initiated by AP.
- * The operations requested by AP are:
- * 0 - USB_RETIMER_FW_UPDATE_QUERY_PORT
- * 1 - USB_RETIMER_FW_UPDATE_SUSPEND_PD
- * 2 - USB_RETIMER_FW_UPDATE_RESUME_PD
- * 3 - USB_RETIMER_FW_UPDATE_GET_MUX
- * 4 - USB_RETIMER_FW_UPDATE_SET_USB
- * 5 - USB_RETIMER_FW_UPDATE_SET_SAFE
- * 6 - USB_RETIMER_FW_UPDATE_SET_TBT
- * 7 - USB_RETIMER_FW_UPDATE_DISCONNECT
- *
- * Operation 0 is processed immediately.
- * Operations 1 to 7 are deferred and processed inside tc_run().
- * Operations 1/2/3 can be processed any time; while 4/5/6/7 have
- * to be processed when PD task is suspended.
- * Two TC flags are created for this situation.
- * If Op 1/2/3 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN
- * is set, PD task will be waken up and process it.
- * If 4/5/6/7 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN is
- * set, PD task should be in suspended mode and process it.
- *
- */
-
-#define SUSPEND 1
-#define RESUME  0
-
-/* Track current port AP requested to update retimer firmware */
-static int cur_port;
-static int last_op; /* Operation received from AP via ACPI_WRITE */
-/* Operation result returned to ACPI_READ */
-static int last_result;
-
-int usb_retimer_fw_update_get_result(void)
-{
-	int result = 0;
-
-	switch (last_op) {
-	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
-		if (last_result == USB_RETIMER_FW_UPDATE_ERR) {
-			result = last_result;
-			break;
-		}
-		/* fall through */
-	case USB_RETIMER_FW_UPDATE_RESUME_PD:
-		result = pd_is_port_enabled(cur_port);
-		break;
-	case USB_RETIMER_FW_UPDATE_QUERY_PORT:
-		result = usb_mux_retimer_fw_update_port_info();
-		break;
-	case USB_RETIMER_FW_UPDATE_GET_MUX:
-	case USB_RETIMER_FW_UPDATE_SET_USB:
-	case USB_RETIMER_FW_UPDATE_SET_SAFE:
-	case USB_RETIMER_FW_UPDATE_SET_TBT:
-	case USB_RETIMER_FW_UPDATE_DISCONNECT:
-		result = last_result;
-		break;
-	default:
-		break;
-	}
-
-	return result;
-}
-
-static void deferred_pd_suspend(void)
-{
-	pd_set_suspend(cur_port, SUSPEND);
-}
-DECLARE_DEFERRED(deferred_pd_suspend);
-
-static inline mux_state_t retimer_fw_update_usb_mux_get(int port)
-{
-	return usb_mux_get(port) & USB_RETIMER_FW_UPDATE_MUX_MASK;
-}
-
-void usb_retimer_fw_update_process_op_cb(int port)
-{
-	switch (last_op) {
-	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
-		last_result = 0;
-		/*
-		 * Do not perform retimer firmware update process
-		 * if battery is not present, or battery level is low.
-		 */
-		if (!pd_firmware_upgrade_check_power_readiness(port)) {
-			last_result = USB_RETIMER_FW_UPDATE_ERR;
-			break;
-		}
-
-		/*
-		 * If the port has entered low power mode, the PD task
-		 * is paused and will not complete processing of
-		 * pd_set_suspend(). Move pd_set_suspend() into a deferred
-		 * call so that it runs from the HOOKS task and can generate
-		 * a wake event to the PD task and enter suspended mode.
-		 */
-		hook_call_deferred(&deferred_pd_suspend_data, 0);
-		break;
-	case USB_RETIMER_FW_UPDATE_RESUME_PD:
-		pd_set_suspend(port, RESUME);
-		break;
-	case USB_RETIMER_FW_UPDATE_GET_MUX:
-		last_result = retimer_fw_update_usb_mux_get(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_SET_USB:
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
-		last_result = retimer_fw_update_usb_mux_get(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_SET_SAFE:
-		usb_mux_set_safe_mode(port);
-		last_result = retimer_fw_update_usb_mux_get(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_SET_TBT:
-		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
-		last_result = retimer_fw_update_usb_mux_get(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_DISCONNECT:
-		usb_mux_set(port, USB_PD_MUX_NONE,
-			USB_SWITCH_DISCONNECT, pd_get_polarity(port));
-		last_result = retimer_fw_update_usb_mux_get(port);
-		break;
-	default:
-		break;
-	}
-}
-
-void usb_retimer_fw_update_process_op(int port, int op)
-{
-	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	/*
-	 * TODO(b/179220036): check not overlapping requests;
-	 * not change cur_port if retimer scan is in progress
-	 */
-	last_op = op;
-
-	switch (op) {
-	case USB_RETIMER_FW_UPDATE_QUERY_PORT:
-		break;
-	/* Operations can't be processed in ISR, defer to later */
-	case USB_RETIMER_FW_UPDATE_GET_MUX:
-		last_result = USB_RETIMER_FW_UPDATE_INVALID_MUX;
-		tc_usb_firmware_fw_update_run(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_SUSPEND_PD:
-	case USB_RETIMER_FW_UPDATE_RESUME_PD:
-		cur_port = port;
-		tc_usb_firmware_fw_update_run(port);
-		break;
-	case USB_RETIMER_FW_UPDATE_SET_USB:
-	case USB_RETIMER_FW_UPDATE_SET_SAFE:
-	case USB_RETIMER_FW_UPDATE_SET_TBT:
-	case USB_RETIMER_FW_UPDATE_DISCONNECT:
-		if (pd_is_port_enabled(port)) {
-			last_result = USB_RETIMER_FW_UPDATE_ERR;
-		} else {
-			last_result = USB_RETIMER_FW_UPDATE_INVALID_MUX;
-			tc_usb_firmware_fw_update_limited_run(port);
-		}
-		break;
-	default:
-		break;
-	}
-}
diff --git a/common/usbc/usb_sm.c b/common/usbc/usb_sm.c
deleted file mode 100644
index 04b7193c0f..0000000000
--- a/common/usbc/usb_sm.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "stdbool.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* Private structure (to this file) used to track state machine context */
-struct internal_ctx {
-	usb_state_ptr last_entered;
-	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
-};
-BUILD_ASSERT(sizeof(struct internal_ctx) ==
-	     member_size(struct sm_ctx, internal));
-
-/* Gets the first shared parent state between a and b (inclusive) */
-static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
-{
-	const usb_state_ptr orig_b = b;
-
-	/* There are no common ancestors */
-	if (b == NULL)
-		return NULL;
-
-	/* This assumes that both A and B are NULL terminated without cycles */
-	while (a != NULL) {
-		/* We found a match return */
-		if (a == b)
-			return a;
-
-		/*
-		 * Otherwise, increment b down the list for comparison until we
-		 * run out, then increment a and start over on b for comparison
-		 */
-		if (b->parent == NULL) {
-			a = a->parent;
-			b = orig_b;
-		} else {
-			b = b->parent;
-		}
-	}
-
-	return NULL;
-}
-
-/*
- * Call all entry functions of parents before children. If set_state is called
- * during one of the entry functions, then do not call any remaining entry
- * functions.
- */
-static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
-{
-	if (current == stop)
-		return;
-
-	call_entry_functions(port, internal, stop, current->parent);
-
-	/*
-	 * If the previous entry function called set_state, then don't enter
-	 * remaining states.
-	 */
-	if (!internal->enter)
-		return;
-
-	/* Track the latest state that was entered, so we can exit properly. */
-	internal->last_entered = current;
-	if (current->entry)
-		current->entry(port);
-}
-
-/*
- * Call all exit functions of children before parents. Note set_state is ignored
- * during an exit function.
- */
-static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
-{
-	if (current == stop)
-		return;
-
-	if (current->exit)
-		current->exit(port);
-
-	call_exit_functions(port, stop, current->parent);
-}
-
-void set_state(const int port, struct sm_ctx *const ctx,
-	       const usb_state_ptr new_state)
-{
-	struct internal_ctx * const internal = (void *) ctx->internal;
-	usb_state_ptr last_state;
-	usb_state_ptr shared_parent;
-
-	/*
-	 * It does not make sense to call set_state in an exit phase of a state
-	 * since we are already in a transition; we would always ignore the
-	 * intended state to transition into.
-	 */
-	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
-		return;
-	}
-
-	/*
-	 * Determine the last state that was entered. Normally it is current,
-	 * but we could have called set_state within an entry phase, so we
-	 * shouldn't exit any states that weren't fully entered.
-	 */
-	last_state = internal->enter ? internal->last_entered : ctx->current;
-
-	/* We don't exit and re-enter shared parent states */
-	shared_parent = shared_parent_state(last_state, new_state);
-
-	/*
-	 * Exit all of the non-common states from the last state.
-	 */
-	internal->exit = true;
-	call_exit_functions(port, shared_parent, last_state);
-	internal->exit = false;
-
-	ctx->previous = ctx->current;
-	ctx->current = new_state;
-
-	/*
-	 * Enter all new non-common states. last_entered will contain the last
-	 * state that successfully entered before another set_state was called.
-	 */
-	internal->last_entered = NULL;
-	internal->enter = true;
-	call_entry_functions(port, internal, shared_parent, ctx->current);
-	/*
-	 * Setting enter to false ensures that all pending entry calls will be
-	 * skipped (in the case of a parent state calling set_state, which means
-	 * we should not enter any child states)
-	 */
-	internal->enter = false;
-
-	/*
-	 * If we set_state while we are running a child state, then stop running
-	 * any remaining parent states.
-	 */
-	internal->running = false;
-
-	/*
-	 * Since we are changing states, we want to ensure that we process the
-	 * next state's run method as soon as we can to ensure that we don't
-	 * delay important processing until the next task interval.
-	 */
-	if (IS_ENABLED(HAS_TASK_PD_C0))
-		task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-/*
- * Call all run functions of children before parents. If set_state is called
- * during one of the entry functions, then do not call any remaining entry
- * functions.
- */
-static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
-{
-	if (!current)
-		return;
-
-	/* If set_state is called during run, don't call remain functions. */
-	if (!internal->running)
-		return;
-
-	if (current->run)
-		current->run(port);
-
-	call_run_functions(port, internal, current->parent);
-}
-
-void run_state(const int port, struct sm_ctx *const ctx)
-{
-	struct internal_ctx * const internal = (void *) ctx->internal;
-
-	internal->running = true;
-	call_run_functions(port, internal, ctx->current);
-	internal->running = false;
-}
diff --git a/common/usbc/usb_tc_ctvpd_sm.c b/common/usbc/usb_tc_ctvpd_sm.c
deleted file mode 100644
index a2babe754a..0000000000
--- a/common/usbc/usb_tc_ctvpd_sm.c
+++ /dev/null
@@ -1,1716 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-#include "usb_tc_sm.h"
-#include "vpd_api.h"
-
-/* USB Type-C CTVPD module */
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
-
-#define SUPPORT_TIMER_RESET_INIT     0
-#define SUPPORT_TIMER_RESET_REQUEST  1
-#define SUPPORT_TIMER_RESET_COMPLETE 2
-
-/**
- * This is the Type-C Port object that contains information needed to
- * implement a Charge Through VCONN Powered Device.
- */
-static struct type_c {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* Higher-level power deliver state machines are enabled if true. */
-	uint8_t pd_enable;
-	/* port flags, see TC_FLAGS_* */
-	uint32_t flags;
-	/*
-	 * Time a charge-through port shall wait before it can determine it
-	 * is attached
-	 */
-	uint64_t cc_debounce;
-	/* Time a host port shall wait before it can determine it is attached */
-	uint64_t host_cc_debounce;
-	/* Time a Sink port shall wait before it can determine it is detached
-	 * due to the potential for USB PD signaling on CC as described in
-	 * the state definitions.
-	 */
-	uint64_t pd_debounce;
-	/* Maintains state of billboard device */
-	int billboard_presented;
-	/*
-	 * Time a port shall wait before it can determine it is
-	 * re-attached during the try-wait process.
-	 */
-	uint64_t try_wait_debounce;
-	/* charge-through support timer */
-	uint64_t support_timer;
-	/* reset the charge-through support timer */
-	uint8_t support_timer_reset;
-	/* VPD host port cc state */
-	enum pd_cc_states host_cc_state;
-	uint8_t ct_cc;
-	/* The cc state */
-	enum pd_cc_states cc_state;
-	uint64_t next_role_swap;
-} tc[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* List of all TypeC-level states */
-enum usb_tc_state {
-	/* Normal States */
-	TC_DISABLED,
-	TC_UNATTACHED_SNK,
-	TC_ATTACH_WAIT_SNK,
-	TC_ATTACHED_SNK,
-	TC_ERROR_RECOVERY,
-	TC_TRY_SNK,
-	TC_UNATTACHED_SRC,
-	TC_ATTACH_WAIT_SRC,
-	TC_TRY_WAIT_SRC,
-	TC_ATTACHED_SRC,
-	TC_CT_TRY_SNK,
-	TC_CT_ATTACH_WAIT_UNSUPPORTED,
-	TC_CT_ATTACHED_UNSUPPORTED,
-	TC_CT_UNATTACHED_UNSUPPORTED,
-	TC_CT_UNATTACHED_VPD,
-	TC_CT_DISABLED_VPD,
-	TC_CT_ATTACHED_VPD,
-	TC_CT_ATTACH_WAIT_VPD,
-	/* Super States */
-	TC_VBUS_CC_ISO,
-	TC_HOST_RARD_CT_RD,
-	TC_HOST_OPEN_CT_OPEN,
-	TC_HOST_RP3_CT_RD,
-	TC_HOST_RP3_CT_RPU,
-	TC_HOST_RPU_CT_RD,
-};
-
-/* Forward declare the full list of states. This is indexed by usb_tc_state */
-static const struct usb_state tc_states[];
-
-
-/* List of human readable state names for console debugging */
-__maybe_unused const char * const tc_state_names[] = {
-#ifdef CONFIG_COMMON_RUNTIME
-	[TC_DISABLED] = "Disabled",
-	[TC_UNATTACHED_SNK] = "Unattached.SNK",
-	[TC_ATTACH_WAIT_SNK] = "AttachWait.SNK",
-	[TC_ATTACHED_SNK] = "Attached.SNK",
-	[TC_ERROR_RECOVERY] = "ErrorRecovery",
-	[TC_TRY_SNK] = "Try.SNK",
-	[TC_UNATTACHED_SRC] = "Unattached.SRC",
-	[TC_ATTACH_WAIT_SRC] = "AttachWait.SRC",
-	[TC_TRY_WAIT_SRC] = "TryWait.SRC",
-	[TC_ATTACHED_SRC] = "Attached.SRC",
-	[TC_CT_TRY_SNK] = "CTTry.SNK",
-	[TC_CT_ATTACH_WAIT_UNSUPPORTED] = "CTAttachWait.Unsupported",
-	[TC_CT_ATTACHED_UNSUPPORTED] = "CTAttached.Unsupported",
-	[TC_CT_UNATTACHED_UNSUPPORTED] = "CTUnattached.Unsupported",
-	[TC_CT_UNATTACHED_VPD] = "CTUnattached.VPD",
-	[TC_CT_DISABLED_VPD] = "CTDisabled.VPD",
-	[TC_CT_ATTACHED_VPD] = "CTAttached.VPD",
-	[TC_CT_ATTACH_WAIT_VPD] = "CTAttachWait.VPD",
-#endif
-};
-
-/* Forward declare private, common functions */
-static void set_state_tc(const int port, enum usb_tc_state new_state);
-
-/* Public TypeC functions */
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	/* Vconn power device is always the sink */
-	return PD_ROLE_SINK;
-}
-
-enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	/* Vconn power device is always the cable */
-	return PD_PLUG_FROM_CABLE;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	/* Vconn power device doesn't have a data role, but UFP matches SNK */
-	return PD_ROLE_UFP;
-}
-
-/* Note tc_set_power_role and tc_set_data_role are unimplemented */
-
-uint8_t tc_get_polarity(int port)
-{
-	/* Does not track polarity */
-	return 0;
-}
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return tc[port].pd_enable;
-}
-
-void tc_reset_support_timer(int port)
-{
-	tc[port].support_timer_reset |= SUPPORT_TIMER_RESET_REQUEST;
-}
-
-/*
- * TCPC CC/Rp management
- *
- * Stub for linking purposes.
- * This is not supported for ctvpd, we are never the SOP partner.
- */
-void typec_select_pull(int port, enum tcpc_cc_pull pull)
-{
-}
-void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
-{
-}
-void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
-{
-}
-int typec_update_cc(int port)
-{
-	return EC_SUCCESS;
-}
-
-void tc_state_init(int port)
-{
-	int res = 0;
-
-	res = tcpm_init(port);
-
-	CPRINTS("C%d: init %s", port, res ? "failed" : "ready");
-
-	/* Disable if restart failed, otherwise start in default state. */
-	set_state_tc(port, res ? TC_DISABLED : TC_UNATTACHED_SNK);
-
-	/* Disable pd state machines */
-	tc[port].pd_enable = 0;
-	tc[port].billboard_presented = 0;
-	tc[port].flags = 0;
-}
-
-void tc_event_check(int port, int evt)
-{
-	/* Do Nothing */
-}
-
-void tc_run(const int port)
-{
-	run_state(port, &tc[port].ctx);
-}
-
-/* Internal Functions */
-
-/* Set the TypeC state machine to a new state. */
-static void set_state_tc(const int port, enum usb_tc_state new_state)
-{
-	set_state(port, &tc[port].ctx, &tc_states[new_state]);
-}
-
-/* Get the current TypeC state. */
-test_export_static enum usb_tc_state get_state_tc(const int port)
-{
-	return tc[port].ctx.current - &tc_states[0];
-}
-
-/* Get the previous TypeC state. */
-static enum usb_tc_state get_last_state_tc(const int port)
-{
-	return tc[port].ctx.previous - &tc_states[0];
-}
-
-test_mockable_static void print_current_state(const int port)
-{
-	CPRINTS("C%d: %s", port, tc_state_names[get_state_tc(port)]);
-}
-
-int pd_is_connected(int port)
-{
-	return (get_state_tc(port) == TC_ATTACHED_SNK) ||
-			(get_state_tc(port) == TC_ATTACHED_SRC) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_VPD);
-}
-
-bool pd_is_disconnected(int port)
-{
-	return !pd_is_connected(port);
-}
-
-/**
- * Disabled
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Remove the terminations from Host
- *   Remove the terminations from Charge-Through
- */
-static void tc_disabled_entry(const int port)
-{
-	print_current_state(port);
-}
-
-static void tc_disabled_run(const int port)
-{
-	task_wait_event(-1);
-}
-
-static void tc_disabled_exit(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC)) {
-		if (tcpm_init(port) != 0) {
-			CPRINTS("C%d: restart failed!", port);
-			return;
-		}
-	}
-
-	CPRINTS("C%d: resumed!", port);
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-	/*
-	 * This shouldn't happen. If it does, we need to send an event to the
-	 * PD task to put the SM into the disabled state. It is not safe to
-	 * directly set_state here since this may be in another task.
-	 */
-	assert(false);
-}
-
-/**
- * ErrorRecovery
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Remove the terminations from Host
- *   Remove the terminations from Charge-Through
- */
-static void tc_error_recovery_entry(const int port)
-{
-	print_current_state(port);
-	/* Use cc_debounce state variable for error recovery timeout */
-	tc[port].cc_debounce = get_time().val + PD_T_ERROR_RECOVERY;
-}
-
-static void tc_error_recovery_run(const int port)
-{
-	if (get_time().val > tc[port].cc_debounce)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-}
-
-/**
- * Unattached.SNK
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place Ra on VCONN and Rd on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_unattached_snk_entry(const int port)
-{
-	if (get_last_state_tc(port) != TC_UNATTACHED_SRC)
-		print_current_state(port);
-
-	tc[port].flags &= ~TC_FLAGS_VCONN_ON;
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_unattached_snk_run(const int port)
-{
-	int host_cc;
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	/*
-	 * Transition to AttachWait.SNK when a Source connection is
-	 * detected, as indicated by the SNK.Rp state on its Host-side
-	 * port’s CC pin.
-	 */
-	if (cc_is_rp(host_cc)) {
-		set_state_tc(port, TC_ATTACH_WAIT_SNK);
-		return;
-	}
-
-	/* Check Charge-Through CCs for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (cc_is_rp(cc1) != cc_is_rp(cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		new_cc_state = PD_CC_NONE;
-
-	/* Debounce Charge-Through CC state */
-	if (tc[port].cc_state != new_cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
-	}
-
-	/* If we are here, Host CC must be open */
-
-	/* Wait for Charge-Through CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Unattached.SRC when the state of the Host-side port’s CC pin is
-	 * SNK.Open for tDRP − dcSRC.DRP ∙ tDRP and both of the following
-	 * is detected on the Charge-Through port.
-	 *   1) SNK.Rp state is detected on exactly one of the CC1 or CC2
-	 *      pins for at least tCCDebounce
-	 *   2) VBUS is detected
-	 */
-	if (vpd_is_ct_vbus_present() &&
-				tc[port].cc_state == PD_CC_DFP_ATTACHED) {
-		set_state_tc(port, TC_UNATTACHED_SRC);
-		return;
-	}
-}
-
-/**
- * AttachWait.SNK
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place Ra on VCONN and Rd on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_attach_wait_snk_entry(const int port)
-{
-	print_current_state(port);
-	tc[port].host_cc_state = PD_CC_UNSET;
-}
-
-static void tc_attach_wait_snk_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (cc_is_rp(host_cc))
-		host_new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
-		else
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
-		return;
-	}
-
-	/* Wait for Host CC debounce */
-	if (get_time().val < tc[port].host_cc_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Attached.SNK after the state of the Host-side port’s CC pin is
-	 * SNK.Rp for at least tCCDebounce and either host-side VCONN or
-	 * VBUS is detected.
-	 *
-	 * Transition to Unattached.SNK when the state of both the CC1 and
-	 * CC2 pins is SNK.Open for at least tPDDebounce.
-	 */
-	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
-		set_state_tc(port, TC_ATTACHED_SNK);
-	else if (tc[port].host_cc_state == PD_CC_NONE)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-}
-
-/**
- * Attached.SNK
- */
-static void tc_attached_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	/*
-	 * This state can only be entered from states AttachWait.SNK
-	 * and Try.SNK. So the Host port is isolated from the
-	 * Charge-Through port. We only need to High-Z the
-	 * Charge-Through ports CC1 and CC2 pins.
-	 */
-	vpd_ct_set_pull(TYPEC_CC_OPEN, 0);
-
-	tc[port].host_cc_state = PD_CC_UNSET;
-
-	/* Start Charge-Through support timer */
-	tc[port].support_timer_reset = SUPPORT_TIMER_RESET_INIT;
-	tc[port].support_timer = get_time().val + PD_T_AME;
-}
-
-static void tc_attached_snk_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/* Has host vbus and vconn been removed */
-	if (!vpd_is_host_vbus_present() && !vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 * Reset the Charge-Through Support Timer when it first
-	 * receives any USB PD Structured VDM Command it supports,
-	 * which is the Discover Identity command. And this is only
-	 * done one time.
-	 */
-	if (tc[port].support_timer_reset == SUPPORT_TIMER_RESET_REQUEST) {
-		tc[port].support_timer_reset |= SUPPORT_TIMER_RESET_COMPLETE;
-		tc[port].support_timer = get_time().val + PD_T_AME;
-	}
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (cc_is_rp(host_cc))
-		host_new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		tc[port].host_cc_debounce = get_time().val + PD_T_VPDCTDD;
-		return;
-	}
-
-	/* Wait for Host CC debounce */
-	if (get_time().val < tc[port].host_cc_debounce)
-		return;
-
-	if (vpd_is_vconn_present()) {
-		if (!(tc[port].flags & TC_FLAGS_VCONN_ON)) {
-			/* VCONN detected. Remove RA */
-			vpd_host_set_pull(TYPEC_CC_RD, 0);
-			tc[port].flags |= TC_FLAGS_VCONN_ON;
-		}
-
-		/*
-		 * A Charge-Through VCONN-Powered USB Device shall transition
-		 * to CTUnattached.VPD if VCONN is present and the state of
-		 * its Host-side port’s CC pin is SNK.Open for tVPDCTDD.
-		 */
-		if (tc[port].host_cc_state == PD_CC_NONE) {
-			set_state_tc(port, TC_CT_UNATTACHED_VPD);
-			return;
-		}
-	}
-
-	/* Check the Support Timer */
-	if (get_time().val > tc[port].support_timer &&
-					!tc[port].billboard_presented) {
-		/*
-		 * Present USB Billboard Device Class interface
-		 * indicating that Charge-Through is not supported
-		 */
-		tc[port].billboard_presented = 1;
-		vpd_present_billboard(BB_SNK);
-	}
-}
-
-static void tc_attached_snk_exit(const int port)
-{
-	tc[port].billboard_presented = 0;
-	vpd_present_billboard(BB_NONE);
-}
-
-/**
- * Super State HOST_RA_CT_RD
- */
-static void tc_host_rard_ct_rd_entry(const int port)
-{
-	/* Place Ra on VCONN and Rd on Host CC */
-	vpd_host_set_pull(TYPEC_CC_RA_RD, 0);
-
-	/* Place Rd on Charge-Through CCs */
-	vpd_ct_set_pull(TYPEC_CC_RD, 0);
-}
-
-/**
- * Super State HOST_OPEN_CT_OPEN
- */
-static void tc_host_open_ct_open_entry(const int port)
-{
-	/* Remove the terminations from Host */
-	vpd_host_set_pull(TYPEC_CC_OPEN, 0);
-
-	/* Remove the terminations from Charge-Through */
-	vpd_ct_set_pull(TYPEC_CC_OPEN, 0);
-}
-
-/**
- * Super State VBUS_CC_ISO
- */
-static void tc_vbus_cc_iso_entry(const int port)
-{
-	/* Isolate the Host-side port from the Charge-Through port */
-	vpd_vbus_pass_en(0);
-
-	/* Remove Charge-Through side port CCs */
-	vpd_ct_cc_sel(CT_OPEN);
-
-	/* Enable mcu communication and cc */
-	vpd_mcu_cc_en(1);
-}
-
-/**
- * Unattached.SRC
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place RpUSB on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_unattached_src_entry(const int port)
-{
-	if (get_last_state_tc(port) != TC_UNATTACHED_SNK)
-		print_current_state(port);
-
-	/* Get power from VBUS */
-	vpd_vconn_pwr_sel_odl(PWR_VBUS);
-
-	/* Make sure it's the Charge-Through Port's VBUS */
-	if (!vpd_is_ct_vbus_present()) {
-		set_state_tc(port, TC_ERROR_RECOVERY);
-		return;
-	}
-
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_SRC;
-}
-
-static void tc_unattached_src_run(const int port)
-{
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	/*
-	 * Transition to AttachWait.SRC when host-side VBUS is
-	 * vSafe0V and SRC.Rd state is detected on the Host-side
-	 * port’s CC pin.
-	 */
-	if (!vpd_is_host_vbus_present() && host_cc == TYPEC_CC_VOLT_RD) {
-		set_state_tc(port, TC_ATTACH_WAIT_SRC);
-		return;
-	}
-
-	/*
-	 * Transition to Unattached.SNK within tDRPTransition or
-	 * if Charge-Through VBUS is removed.
-	 */
-	if (!vpd_is_ct_vbus_present() ||
-				get_time().val > tc[port].next_role_swap) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-}
-
-/**
- * AttachWait.SRC
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place RpUSB on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_attach_wait_src_entry(const int port)
-{
-	print_current_state(port);
-
-	tc[port].host_cc_state = PD_CC_UNSET;
-}
-
-static void tc_attach_wait_src_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (host_cc == TYPEC_CC_VOLT_RD)
-		host_new_cc_state = PD_CC_UFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition
-	 * to Unattached.SNK when the SRC.Open state is detected on the
-	 * Host-side port’s CC or if Charge-Through VBUS falls below
-	 * vSinkDisconnect. The Charge-Through VCONN-Powered USB Device
-	 * shall detect the SRC.Open state within tSRCDisconnect, but
-	 * should detect it as quickly as possible.
-	 */
-	if (host_new_cc_state == PD_CC_NONE || !vpd_is_ct_vbus_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
-		return;
-	}
-
-	/* Wait for Host CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Try.SNK when the host-side VBUS is at vSafe0V and the SRC.Rd
-	 * state is on the Host-side port’s CC pin for at least tCCDebounce.
-	 */
-	if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
-		set_state_tc(port, TC_TRY_SNK);
-		return;
-	}
-}
-
-/**
- * Attached.SRC
- */
-static void tc_attached_src_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	/* Connect Charge-Through VBUS to Host VBUS */
-	vpd_vbus_pass_en(1);
-
-	/*
-	 * Get power from VBUS. No need to test because
-	 * the Host VBUS is connected to the Charge-Through
-	 * VBUS
-	 */
-	vpd_vconn_pwr_sel_odl(PWR_VBUS);
-}
-
-static void tc_attached_src_run(const int port)
-{
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Unattached.SNK when VBUS falls below vSinkDisconnect or the
-	 * Host-side port’s CC pin is SRC.Open. The Charge-Through
-	 * VCONNPowered USB Device shall detect the SRC.Open state within
-	 * tSRCDisconnect, but should detect it as quickly as possible.
-	 */
-	if (!vpd_is_ct_vbus_present() || host_cc == TYPEC_CC_VOLT_OPEN)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-}
-
-/**
- * Super State HOST_RPU_CT_RD
- */
-static void tc_host_rpu_ct_rd_entry(const int port)
-{
-	/* Place RpUSB on Host CC */
-	vpd_host_set_pull(TYPEC_CC_RP, TYPEC_RP_USB);
-
-	/* Place Rd on Charge-Through CCs */
-	vpd_ct_set_pull(TYPEC_CC_RD, 0);
-}
-
-/**
- * Try.SNK
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place Ra on VCONN and Rd on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_try_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Get power from VBUS */
-	vpd_vconn_pwr_sel_odl(PWR_VBUS);
-
-	/* Make sure it's the Charge-Through Port's VBUS */
-	if (!vpd_is_ct_vbus_present()) {
-		set_state_tc(port, TC_ERROR_RECOVERY);
-		return;
-	}
-
-	tc[port].host_cc_state = PD_CC_UNSET;
-
-	/* Using next_role_swap timer as try_src timer */
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_TRY;
-}
-
-static void tc_try_snk_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/*
-	 * Wait for tDRPTry before monitoring the Charge-Through
-	 * port’s CC pins for the SNK.Rp
-	 */
-	if (get_time().val < tc[port].next_role_swap)
-		return;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (cc_is_rp(host_cc))
-		host_new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_DEBOUNCE;
-		return;
-	}
-
-	/* Wait for Host CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * The Charge-Through VCONN-Powered USB Device shall then transition to
-	 * Attached.SNK when the SNK.Rp state is detected on the Host-side
-	 * port’s CC pin for at least tTryCCDebounce and VBUS or VCONN is
-	 * detected on Host-side port.
-	 *
-	 * Alternatively, the Charge-Through VCONN-Powered USB Device shall
-	 * transition to TryWait.SRC if Host-side SNK.Rp state is not detected
-	 * for tTryCCDebounce.
-	 */
-	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_host_vbus_present() || vpd_is_vconn_present()))
-		set_state_tc(port, TC_ATTACHED_SNK);
-	else if (tc[port].host_cc_state == PD_CC_NONE)
-		set_state_tc(port, TC_TRY_WAIT_SRC);
-}
-
-/**
- * TryWait.SRC
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place RpUSB on Host CC
- *   Place Rd on Charge-Through CCs
- */
-static void tc_try_wait_src_entry(const int port)
-{
-	print_current_state(port);
-
-	tc[port].host_cc_state = PD_CC_UNSET;
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_TRY;
-}
-
-static void tc_try_wait_src_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (host_cc == TYPEC_CC_VOLT_RD)
-		host_new_cc_state = PD_CC_UFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		tc[port].host_cc_debounce =
-					get_time().val + PD_T_TRY_CC_DEBOUNCE;
-		return;
-	}
-
-	if (get_time().val > tc[port].host_cc_debounce) {
-		/*
-		 * A Charge-Through VCONN-Powered USB Device shall transition
-		 * to Attached.SRC when host-side VBUS is at vSafe0V and the
-		 * SRC.Rd state is detected on the Host-side port’s CC pin for
-		 * at least tTryCCDebounce.
-		 */
-		if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
-			set_state_tc(port, TC_ATTACHED_SRC);
-			return;
-		}
-	}
-
-	if (get_time().val > tc[port].next_role_swap) {
-		/*
-		 * The Charge-Through VCONN-Powered USB Device shall transition
-		 * to Unattached.SNK after tDRPTry if the Host-side port’s CC
-		 * pin is not in the SRC.Rd state.
-		 */
-		if (tc[port].host_cc_state == PD_CC_NONE) {
-			set_state_tc(port, TC_UNATTACHED_SNK);
-			return;
-		}
-	}
-}
-
-/**
- * CTTry.SNK
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Place RP3A0 on Host CC
- *   Connect Charge-Through Rd
- *   Get power from VCONN
- */
-static void tc_ct_try_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	tc[port].cc_state = PD_CC_UNSET;
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_TRY;
-}
-
-static void tc_ct_try_snk_run(const int port)
-{
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/*
-	 * Wait for tDRPTry before monitoring the Charge-Through
-	 * port’s CC pins for the SNK.Rp
-	 */
-	if (get_time().val < tc[port].next_role_swap)
-		return;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (cc_is_rp(cc1) || cc_is_rp(cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		new_cc_state = PD_CC_NONE;
-
-	/*
-	 * The Charge-Through VCONN-Powered USB Device shall transition
-	 * to Unattached.SNK if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Debounce the CT CC state */
-	if (tc[port].cc_state != new_cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_DEBOUNCE;
-		tc[port].try_wait_debounce = get_time().val + PD_T_TRY_WAIT;
-
-		return;
-	}
-
-	if (get_time().val > tc[port].cc_debounce) {
-		/*
-		 * The Charge-Through VCONN-Powered USB Device shall then
-		 * transition to CTAttached.VPD when the SNK.Rp state is
-		 * detected on the Charge-Through port’s CC pins for at
-		 * least tTryCCDebounce and VBUS is detected on
-		 * Charge-Through port.
-		 */
-		if (tc[port].cc_state == PD_CC_DFP_ATTACHED &&
-				vpd_is_ct_vbus_present()) {
-			set_state_tc(port, TC_CT_ATTACHED_VPD);
-			return;
-		}
-	}
-
-	if (get_time().val > tc[port].try_wait_debounce) {
-		/*
-		 * A Charge-Through VCONN-Powered USB Device shall transition
-		 * to CTAttached.Unsupported if SNK.Rp state is not detected
-		 * for tDRPTryWait.
-		 */
-		if (tc[port].cc_state == PD_CC_NONE) {
-			set_state_tc(port,
-					TC_CT_ATTACHED_UNSUPPORTED);
-			return;
-		}
-	}
-}
-
-static void tc_ct_try_snk_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-}
-
-/**
- * CTAttachWait.Unsupported
- *
- *  Super State Entry Actions:
- *    Isolate the Host-side port from the Charge-Through port
- *    Enable mcu communication
- *    Place RP3A0 on Host CC
- *    Place RPUSB on Charge-Through CC
- *    Get power from VCONN
- */
-static void tc_ct_attach_wait_unsupported_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_ct_attach_wait_unsupported_run(const int port)
-{
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (cc_is_at_least_one_rd(cc1, cc2))
-		new_cc_state = PD_CC_UFP_ATTACHED;
-	else if (cc_is_audio_acc(cc1, cc2))
-		new_cc_state = PD_CC_UFP_AUDIO_ACC;
-	else /* (cc1 == TYPEC_CC_VOLT_OPEN or cc2 == TYPEC_CC_VOLT_OPEN */
-		new_cc_state = PD_CC_NONE;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Unattached.SNK if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Debounce the cc state */
-	if (tc[port].cc_state != new_cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
-		return;
-	}
-
-	/* Wait for CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTUnattached.VPD when the state of either the Charge-Through
-	 * Port’s CC1 or CC2 pin is SRC.Open for at least tCCDebounce.
-	 *
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTTry.SNK if the state of at least one of the Charge-Through
-	 * port’s CC pins is SRC.Rd, or if the state of both the CC1 and CC2
-	 * pins is SRC.Ra. for at least tCCDebounce.
-	 */
-	if (new_cc_state == PD_CC_NONE)
-		set_state_tc(port, TC_CT_UNATTACHED_VPD);
-	else /* PD_CC_UFP_ATTACHED or PD_CC_UFP_AUDIO_ACC */
-		set_state_tc(port, TC_CT_TRY_SNK);
-}
-
-static void tc_ct_attach_wait_unsupported_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-}
-
-/**
- * CTAttached.Unsupported
- *
- *  Super State Entry Actions:
- *    Isolate the Host-side port from the Charge-Through port
- *    Enable mcu communication
- *    Place RP3A0 on Host CC
- *    Place RPUSB on Charge-Through CC
- *    Get power from VCONN
- */
-static void tc_ct_attached_unsupported_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Present Billboard device */
-	vpd_present_billboard(BB_SNK);
-}
-
-static void tc_ct_attached_unsupported_run(const int port)
-{
-	int cc1;
-	int cc2;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 * The Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTUnattached.VPD when SRC.Open state is detected on both the
-	 * Charge-Through port’s CC pins or the SRC.Open state is detected
-	 * on one CC pin and SRC.Ra is detected on the other CC pin.
-	 */
-	if ((cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN) ||
-	    (cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_RA) ||
-	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_OPEN)) {
-		set_state_tc(port, TC_CT_UNATTACHED_VPD);
-		return;
-	}
-}
-
-static void tc_ct_attached_unsupported_exit(const int port)
-{
-	vpd_present_billboard(BB_NONE);
-}
-
-/**
- * CTUnattached.Unsupported
- *
- *  Super State Entry Actions:
- *    Isolate the Host-side port from the Charge-Through port
- *    Enable mcu communication
- *    Place RP3A0 on Host CC
- *    Place RPUSB on Charge-Through CC
- *    Get power from VCONN
- */
-static void tc_ct_unattached_unsupported_entry(const int port)
-{
-	if (get_last_state_tc(port) != TC_CT_UNATTACHED_VPD)
-		print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	tc[port].next_role_swap = get_time().val + PD_T_DRP_SRC;
-}
-
-static void tc_ct_unattached_unsupported_run(const int port)
-{
-	int cc1;
-	int cc2;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTAttachWait.Unsupported when a Sink connection is detected on
-	 * the Charge-Through port, as indicated by the SRC.Rd state on at
-	 * least one of the Charge-Through port’s CC pins or SRC.Ra state
-	 * on both the CC1 and CC2 pins.
-	 */
-	if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2)) {
-		set_state_tc(port,
-				TC_CT_ATTACH_WAIT_UNSUPPORTED);
-		return;
-	}
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Unattached.SNK if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTUnattached.VPD within tDRPTransition after dcSRC.DRP ∙ tDRP.
-	 */
-	if (get_time().val > tc[port].next_role_swap) {
-		set_state_tc(port, TC_CT_UNATTACHED_VPD);
-		return;
-	}
-}
-
-static void tc_ct_unattached_unsupported_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-}
-
-/**
- * CTUnattached.VPD
- *
- *  Super State Entry Actions:
- *    Isolate the Host-side port from the Charge-Through port
- *    Enable mcu communication
- *    Place RP3A0 on Host CC
- *    Connect Charge-Through Rd
- *    Get power from VCONN
- */
-static void tc_ct_unattached_vpd_entry(const int port)
-{
-	if (get_last_state_tc(port) != TC_CT_UNATTACHED_UNSUPPORTED)
-		print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_ct_unattached_vpd_run(const int port)
-{
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (cc_is_rp(cc1) != cc_is_rp(cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else if (!cc_is_rp(cc1) && !cc_is_rp(cc2))
-		new_cc_state = PD_CC_NONE;
-	else
-		new_cc_state = PD_CC_UNSET;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTAttachWait.VPD when a Source connection is detected on the
-	 * Charge-Through port, as indicated by the SNK.Rp state on
-	 * exactly one of the Charge-Through port’s CC pins.
-	 */
-	if (new_cc_state == PD_CC_DFP_ATTACHED) {
-		set_state_tc(port, TC_CT_ATTACH_WAIT_VPD);
-		return;
-	}
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * Unattached.SNK if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_DRP_SRC;
-		return;
-	}
-
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTUnattached.Unsupported within tDRPTransition after the state
-	 * of both the Charge-Through port’s CC1 and CC2 pins is SNK.Open
-	 * for tDRP-dcSRC.DRP ∙ tDRP, or if directed.
-	 */
-	if (tc[port].cc_state == PD_CC_NONE) {
-		set_state_tc(port, TC_CT_UNATTACHED_UNSUPPORTED);
-		return;
-	}
-}
-
-static void tc_ct_unattached_vpd_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-}
-
-/**
- * CTDisabled.VPD
- *
- * Super State Entry Actions:
- *   Isolate the Host-side port from the Charge-Through port
- *   Enable mcu communication
- *   Remove the terminations from Host
- *   Remove the terminations from Charge-Through
- */
-static void tc_ct_disabled_vpd_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Get power from VBUS */
-	vpd_vconn_pwr_sel_odl(PWR_VBUS);
-
-	tc[port].next_role_swap = get_time().val + PD_T_VPDDISABLE;
-}
-
-static void tc_ct_disabled_vpd_run(const int port)
-{
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition
-	 * to Unattached.SNK after tVPDDisable.
-	 */
-	if (get_time().val > tc[port].next_role_swap)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-}
-
-/**
- * CTAttached.VPD
- */
-static void tc_ct_attached_vpd_entry(const int port)
-{
-	int cc1;
-	int cc2;
-	print_current_state(port);
-
-	/* Get power from VCONN */
-	vpd_vconn_pwr_sel_odl(PWR_VCONN);
-
-	/*
-	 * Detect which of the Charge-Through port’s CC1 or CC2
-	 * pins is connected through the cable
-	 */
-	vpd_ct_get_cc(&cc1, &cc2);
-	tc[port].ct_cc  = cc_is_rp(cc2) ? CT_CC2 : CT_CC1;
-
-	/*
-	 * 1. Remove or reduce any additional capacitance on the
-	 *    Host-side CC port
-	 */
-	vpd_mcu_cc_en(0);
-
-	/*
-	 * 2. Disable the Rp termination advertising 3.0 A on the
-	 *    host port’s CC pin
-	 */
-	vpd_host_set_pull(TYPEC_CC_OPEN, 0);
-
-	/*
-	 * 3. Passively multiplex the detected Charge-Through port’s
-	 *    CC pin through to the host port’s CC
-	 */
-	vpd_ct_cc_sel(tc[port].ct_cc);
-
-	/*
-	 * 4. Disable the Rd on the Charge-Through port’s CC1 and CC2
-	 *    pins
-	 */
-	vpd_ct_set_pull(TYPEC_CC_OPEN, 0);
-
-	/*
-	 * 5. Connect the Charge-Through port’s VBUS through to the
-	 *    host port’s VBUS
-	 */
-	vpd_vbus_pass_en(1);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_ct_attached_vpd_run(const int port)
-{
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTDisabled.VPD if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_CT_DISABLED_VPD);
-		return;
-	}
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-	if ((tc[port].ct_cc ? cc2 : cc1) == TYPEC_CC_VOLT_OPEN)
-		new_cc_state = PD_CC_NONE;
-	else
-		new_cc_state = PD_CC_DFP_ATTACHED;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val + PD_T_VPDCTDD;
-		return;
-	}
-
-	if (get_time().val < tc[port].pd_debounce)
-		return;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTUnattached.VPD when VBUS falls below vSinkDisconnect and the
-	 * state of the passed-through CC pin is SNK.Open for tVPDCTDD.
-	 */
-	if (tc[port].cc_state == PD_CC_NONE && !vpd_is_ct_vbus_present())
-		set_state_tc(port, TC_CT_UNATTACHED_VPD);
-}
-
-/**
- * CTAttachWait.VPD
- *
- *  Super State Entry Actions:
- *    Isolate the Host-side port from the Charge-Through port
- *    Enable mcu communication
- *    Place RP3A0 on Host CC
- *    Connect Charge-Through Rd
- *    Get power from VCONN
- */
-static void tc_ct_attach_wait_vpd_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_ct_attach_wait_vpd_run(const int port)
-{
-	int new_cc_state;
-	int cc1;
-	int cc2;
-
-	/* Check CT CC for connection */
-	vpd_ct_get_cc(&cc1, &cc2);
-
-	if (cc_is_rp(cc1) != cc_is_rp(cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else if (!cc_is_rp(cc1) && !cc_is_rp(cc2))
-		new_cc_state = PD_CC_NONE;
-	else
-		new_cc_state = PD_CC_UNSET;
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall transition to
-	 * CTDisabled.VPD if VCONN falls below vVCONNDisconnect.
-	 */
-	if (!vpd_is_vconn_present()) {
-		set_state_tc(port, TC_CT_DISABLED_VPD);
-		return;
-	}
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val +
-						PD_T_CC_DEBOUNCE;
-		tc[port].pd_debounce = get_time().val +
-						PD_T_PD_DEBOUNCE;
-		return;
-	}
-
-	if (get_time().val > tc[port].pd_debounce) {
-		/*
-		 * A Charge-Through VCONN-Powered USB Device shall transition
-		 * to CTUnattached.VPD when the state of both the Charge-Through
-		 * port’s CC1 and CC2 pins are SNK.Open for at least
-		 * tPDDebounce.
-		 */
-		if (tc[port].cc_state  == PD_CC_NONE) {
-			set_state_tc(port, TC_CT_UNATTACHED_VPD);
-			return;
-		}
-	}
-
-	if (get_time().val > tc[port].cc_debounce) {
-		/*
-		 * A Charge-Through VCONN-Powered USB Device shall transition to
-		 * CTAttached.VPD after the state of only one of the
-		 * Charge-Through port’s CC1 or CC2 pins is SNK.Rp for at
-		 * least tCCDebounce and VBUS on the Charge-Through port is
-		 * detected.
-		 */
-		if (tc[port].cc_state  == PD_CC_DFP_ATTACHED &&
-						vpd_is_ct_vbus_present()) {
-			set_state_tc(port, TC_CT_ATTACHED_VPD);
-			return;
-		}
-	}
-}
-
-static void tc_ct_attach_wait_vpd_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-}
-
-/**
- * Super State HOST_RP3_CT_RD
- */
-static void tc_host_rp3_ct_rd_entry(const int port)
-{
-	/* Place RP3A0 on Host CC */
-	vpd_host_set_pull(TYPEC_CC_RP, TYPEC_RP_3A0);
-
-	/* Connect Charge-Through Rd */
-	vpd_ct_set_pull(TYPEC_CC_RD, 0);
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall
-	 * ensure that it is powered by VCONN
-	 */
-
-	/* Make sure vconn is on */
-	if (!vpd_is_vconn_present())
-		set_state_tc(port, TC_ERROR_RECOVERY);
-
-	/* Get power from VCONN */
-	vpd_vconn_pwr_sel_odl(PWR_VCONN);
-}
-
-/**
- * Super State HOST_RP3_CT_RPU
- */
-static void tc_host_rp3_ct_rpu_entry(const int port)
-{
-	/* Place RP3A0 on Host CC */
-	vpd_host_set_pull(TYPEC_CC_RP, TYPEC_RP_3A0);
-
-	/* Place RPUSB on Charge-Through CC */
-	vpd_ct_set_pull(TYPEC_CC_RP, TYPEC_RP_USB);
-
-	/*
-	 * A Charge-Through VCONN-Powered USB Device shall
-	 * ensure that it is powered by VCONN
-	 */
-
-	/* Make sure vconn is on */
-	if (!vpd_is_vconn_present())
-		set_state_tc(port, TC_ERROR_RECOVERY);
-
-	/* Get power from VCONN */
-	vpd_vconn_pwr_sel_odl(PWR_VCONN);
-}
-
-/* All necessary Type-C states */
-
-/*
- * Type-C State Hierarchy (Sub-States are listed inside the boxes)
- *
- * | TC_VBUS_CC_ISO ------------------------------------------------------|
- * |                                                                      |
- * |  | TC_HOST_RARD_CT_RD -----------| | TC_HOST_OPEN_CT_OPEN ---------| |
- * |  |                               | |                               | |
- * |  | TC_UNATTACHED_SNK             | | TC_DISABLED                   | |
- * |  | TC_ATTACH_WAIT_SNK            | | TC_ERROR_RECOVERY             | |
- * |  | TC_TRY_SNK                    | |-------------------------------| |
- * |  |-------------------------------|                                   |
- * |                                                                      |
- * |  | TC_HOST_RP3_CT_RD ------------| | TC_HOST_RPU_CT_RD ------------| |
- * |  |                               | |                               | |
- * |  | TC_CT_TRY_SNK                 | | TC_UNATTACHED_SRC             | |
- * |  | TC_CT_UNATTACHED_VPD          | | TC_ATTACH_WAIT_SRC            | |
- * |  | TC_CT_ATTACH_WAIT_VPD         | | TC_TRY_WAIT_SR                | |
- * |  |-------------------------------| |-------------------------------| |
- * |                                                                      |
- * |  | TC_HOST_RP3_CT_RPU -----------|                                   |
- * |  |                               |                                   |
- * |  | TC_CT_ATTACH_WAIT_UNSUPPORTED |                                   |
- * |  | TC_CT_ATTACHED_UNSUPPORTED    |                                   |
- * |  | TC_CT_UNATTACHED_UNSUPPORTED  |                                   |
- * |  |-------------------------------|                                   |
- * |----------------------------------------------------------------------|
- *
- * TC_ATTACHED_SNK
- * TC_ATTACHED_SRC
- * TC_CT_ATTACHED_VPD
- *
- */
-static const struct usb_state tc_states[] = {
-	/* Super States */
-	[TC_VBUS_CC_ISO] = {
-		.entry  = tc_vbus_cc_iso_entry,
-	},
-	[TC_HOST_RARD_CT_RD] = {
-		.entry  = tc_host_rard_ct_rd_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	[TC_HOST_OPEN_CT_OPEN] = {
-		.entry  = tc_host_open_ct_open_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	[TC_HOST_RP3_CT_RD] = {
-		.entry  = tc_host_rp3_ct_rd_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	[TC_HOST_RP3_CT_RPU] = {
-		.entry  = tc_host_rp3_ct_rpu_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	[TC_HOST_RPU_CT_RD] = {
-		.entry  = tc_host_rpu_ct_rd_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	/* Normal States */
-	[TC_DISABLED] = {
-		.entry  = tc_disabled_entry,
-		.run    = tc_disabled_run,
-		.exit   = tc_disabled_exit,
-		.parent = &tc_states[TC_HOST_OPEN_CT_OPEN],
-	},
-	[TC_UNATTACHED_SNK] = {
-		.entry  = tc_unattached_snk_entry,
-		.run    = tc_unattached_snk_run,
-		.parent = &tc_states[TC_HOST_RARD_CT_RD],
-	},
-	[TC_ATTACH_WAIT_SNK] = {
-		.entry  = tc_attach_wait_snk_entry,
-		.run    = tc_attach_wait_snk_run,
-		.parent = &tc_states[TC_HOST_RARD_CT_RD],
-	},
-	[TC_ATTACHED_SNK] = {
-		.entry  = tc_attached_snk_entry,
-		.run    = tc_attached_snk_run,
-		.exit   = tc_attached_snk_exit,
-	},
-	[TC_ERROR_RECOVERY] = {
-		.entry  = tc_error_recovery_entry,
-		.run    = tc_error_recovery_run,
-		.parent = &tc_states[TC_HOST_OPEN_CT_OPEN],
-	},
-	[TC_TRY_SNK] = {
-		.entry  = tc_try_snk_entry,
-		.run    = tc_try_snk_run,
-		.parent = &tc_states[TC_HOST_RARD_CT_RD],
-	},
-	[TC_UNATTACHED_SRC] = {
-		.entry  = tc_unattached_src_entry,
-		.run    = tc_unattached_src_run,
-		.parent = &tc_states[TC_HOST_RPU_CT_RD],
-	},
-	[TC_ATTACH_WAIT_SRC] = {
-		.entry  = tc_attach_wait_src_entry,
-		.run    = tc_attach_wait_src_run,
-		.parent = &tc_states[TC_HOST_RPU_CT_RD],
-	},
-	[TC_TRY_WAIT_SRC] = {
-		.entry  = tc_try_wait_src_entry,
-		.run    = tc_try_wait_src_run,
-		.parent = &tc_states[TC_HOST_RPU_CT_RD],
-	},
-	[TC_ATTACHED_SRC] = {
-		.entry  = tc_attached_src_entry,
-		.run    = tc_attached_src_run,
-	},
-	[TC_CT_TRY_SNK] = {
-		.entry  = tc_ct_try_snk_entry,
-		.run    = tc_ct_try_snk_run,
-		.exit   = tc_ct_try_snk_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RD],
-	},
-	[TC_CT_ATTACH_WAIT_UNSUPPORTED] = {
-		.entry  = tc_ct_attach_wait_unsupported_entry,
-		.run    = tc_ct_attach_wait_unsupported_run,
-		.exit   = tc_ct_attach_wait_unsupported_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RPU],
-	},
-	[TC_CT_ATTACHED_UNSUPPORTED] = {
-		.entry  = tc_ct_attached_unsupported_entry,
-		.run    = tc_ct_attached_unsupported_run,
-		.exit   = tc_ct_attached_unsupported_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RPU],
-	},
-	[TC_CT_UNATTACHED_UNSUPPORTED] = {
-		.entry  = tc_ct_unattached_unsupported_entry,
-		.run    = tc_ct_unattached_unsupported_run,
-		.exit   = tc_ct_unattached_unsupported_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RPU],
-	},
-	[TC_CT_UNATTACHED_VPD] = {
-		.entry  = tc_ct_unattached_vpd_entry,
-		.run    = tc_ct_unattached_vpd_run,
-		.exit   = tc_ct_unattached_vpd_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RD],
-	},
-	[TC_CT_DISABLED_VPD] = {
-		.entry  = tc_ct_disabled_vpd_entry,
-		.run    = tc_ct_disabled_vpd_run,
-		.parent = &tc_states[TC_HOST_OPEN_CT_OPEN],
-	},
-	[TC_CT_ATTACHED_VPD] = {
-		.entry  = tc_ct_attached_vpd_entry,
-		.run    = tc_ct_attached_vpd_run,
-	},
-	[TC_CT_ATTACH_WAIT_VPD] = {
-		.entry  = tc_ct_attach_wait_vpd_entry,
-		.run    = tc_ct_attach_wait_vpd_run,
-		.exit   = tc_ct_attach_wait_vpd_exit,
-		.parent = &tc_states[TC_HOST_RP3_CT_RD],
-	},
-};
-
-#ifdef TEST_BUILD
-const struct test_sm_data test_tc_sm_data[] = {
-	{
-		.base = tc_states,
-		.size = ARRAY_SIZE(tc_states),
-		.names = tc_state_names,
-		.names_size = ARRAY_SIZE(tc_state_names),
-	},
-};
-const int test_tc_sm_data_size = ARRAY_SIZE(test_tc_sm_data);
-#endif
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c
deleted file mode 100644
index 182ea686ec..0000000000
--- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c
+++ /dev/null
@@ -1,4160 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_dpm.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_timer.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-#include "vboot.h"
-
-/*
- * USB Type-C DRP with Accessory and Try.SRC module
- *   See Figure 4-16 in Release 1.4 of USB Type-C Spec.
- */
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTF(format, ## args); \
-	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTS(format, ## args); \
-	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
-
-/*
- * Define DEBUG_PRINT_FLAG_AND_EVENT_NAMES to print flag names when set and
- * cleared, and event names when handled by tc_event_check().
- */
-#undef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
-
-#ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
-void print_flag(int port, int set_or_clear, int flag);
-#define TC_SET_FLAG(port, flag)                     \
-	do {                                        \
-		print_flag(port, 1, flag);          \
-		atomic_or(&tc[port].flags, (flag)); \
-	} while (0)
-#define TC_CLR_FLAG(port, flag)                             \
-	do {                                                \
-		print_flag(port, 0, flag);                  \
-		atomic_clear_bits(&tc[port].flags, (flag)); \
-	} while (0)
-#else
-#define TC_SET_FLAG(port, flag) atomic_or(&tc[port].flags, (flag))
-#define TC_CLR_FLAG(port, flag) atomic_clear_bits(&tc[port].flags, (flag))
-#endif
-#define TC_CHK_FLAG(port, flag) (tc[port].flags & (flag))
-
-/* Type-C Layer Flags */
-/* Flag to note we are sourcing VCONN */
-#define TC_FLAGS_VCONN_ON               BIT(0)
-/* Flag to note port partner has Rp/Rp or Rd/Rd */
-#define TC_FLAGS_TS_DTS_PARTNER         BIT(1)
-/* Flag to note VBus input has never been low */
-#define TC_FLAGS_VBUS_NEVER_LOW         BIT(2)
-/* Flag to note Low Power Mode transition is currently happening */
-#define TC_FLAGS_LPM_TRANSITION         BIT(3)
-/* Flag to note Low Power Mode is currently on */
-#define TC_FLAGS_LPM_ENGAGED            BIT(4)
-/* Flag to note CVTPD has been detected */
-#define TC_FLAGS_CTVPD_DETECTED         BIT(5)
-/* Flag to note request to swap to VCONN on */
-#define TC_FLAGS_REQUEST_VC_SWAP_ON     BIT(6)
-/* Flag to note request to swap to VCONN off */
-#define TC_FLAGS_REQUEST_VC_SWAP_OFF    BIT(7)
-/* Flag to note request to swap VCONN is being rejected */
-#define TC_FLAGS_REJECT_VCONN_SWAP      BIT(8)
-/* Flag to note request to power role swap */
-#define TC_FLAGS_REQUEST_PR_SWAP        BIT(9)
-/* Flag to note request to data role swap */
-#define TC_FLAGS_REQUEST_DR_SWAP        BIT(10)
-/* Flag to note request to power off sink */
-#define TC_FLAGS_POWER_OFF_SNK          BIT(11)
-/* Flag to note port partner is Power Delivery capable */
-#define TC_FLAGS_PARTNER_PD_CAPABLE     BIT(12)
-/* Flag to note hard reset has been requested */
-#define TC_FLAGS_HARD_RESET_REQUESTED   BIT(13)
-/* Flag to note we are currently performing PR Swap */
-#define TC_FLAGS_PR_SWAP_IN_PROGRESS    BIT(14)
-/* Flag to note we should check for connection */
-#define TC_FLAGS_CHECK_CONNECTION       BIT(15)
-/* Flag to note request from pd_set_suspend to enter TC_DISABLED state */
-#define TC_FLAGS_REQUEST_SUSPEND        BIT(16)
-/* Flag to note we are in TC_DISABLED state */
-#define TC_FLAGS_SUSPENDED              BIT(17)
-/* Flag to indicate the port current limit has changed */
-#define TC_FLAGS_UPDATE_CURRENT		BIT(18)
-/* Flag to indicate USB mux should be updated */
-#define TC_FLAGS_UPDATE_USB_MUX		BIT(19)
-/* Flag for retimer firmware update */
-#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN     BIT(20)
-#define TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN BIT(21)
-/* Flag for asynchronous call to request Error Recovery */
-#define TC_FLAGS_REQUEST_ERROR_RECOVERY	BIT(22)
-
-/* For checking flag_bit_names[] array */
-#define TC_FLAGS_COUNT			23
-
-/* On disconnect, clear most of the flags. */
-#define CLR_FLAGS_ON_DISCONNECT(port) TC_CLR_FLAG(port, \
-	~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | TC_FLAGS_SUSPENDED))
-
-/*
- * 10 ms is enough time for any TCPC transaction to complete
- *
- * This value must be below ~39.7 ms to put ANX7447 into LPM due to bug in
- * silicon (see b/77544959 and b/149761477 for more details).
- */
-#define PD_LPM_DEBOUNCE_US (10 * MSEC)
-
-/*
- * This delay is not part of the USB Type-C specification or the USB port
- * controller specification. Some TCPCs require extra time before the CC_STATUS
- * register is updated when exiting low power mode.
- *
- * This delay can be possibly shortened or removed by checking VBUS state
- * before trying to re-enter LPM.
- *
- * TODO(b/162347811): TCPMv2: Wait for debounce on Vbus and CC lines
- */
-#define PD_LPM_EXIT_DEBOUNCE_US CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-
-/*
- * The TypeC state machine uses this bit to disable/enable PD
- * This bit corresponds to bit-0 of pd_disabled_mask
- */
-#define PD_DISABLED_NO_CONNECTION  BIT(0)
-/*
- * Console and Host commands use this bit to override the
- * PD_DISABLED_NO_CONNECTION bit that was set by the TypeC
- * state machine.
- * This bit corresponds to bit-1 of pd_disabled_mask
- */
-#define PD_DISABLED_BY_POLICY       BIT(1)
-
-/* Unreachable time in future */
-#define TIMER_DISABLED 0xffffffffffffffff
-
-enum ps_reset_sequence {
-	PS_STATE0,
-	PS_STATE1,
-	PS_STATE2,
-};
-
-/* List of all TypeC-level states */
-enum usb_tc_state {
-	/* Super States */
-	TC_CC_OPEN,
-	TC_CC_RD,
-	TC_CC_RP,
-	/* Normal States */
-	TC_DISABLED,
-	TC_ERROR_RECOVERY,
-	TC_UNATTACHED_SNK,
-	TC_ATTACH_WAIT_SNK,
-	TC_ATTACHED_SNK,
-	TC_UNATTACHED_SRC,
-	TC_ATTACH_WAIT_SRC,
-	TC_ATTACHED_SRC,
-	TC_TRY_SRC,
-	TC_TRY_WAIT_SNK,
-	TC_DRP_AUTO_TOGGLE,
-	TC_LOW_POWER_MODE,
-	TC_CT_UNATTACHED_SNK,
-	TC_CT_ATTACHED_SNK,
-
-	TC_STATE_COUNT,
-};
-/* Forward declare the full list of states. This is indexed by usb_tc_state */
-static const struct usb_state tc_states[];
-
-/*
- * Remove all of the states that aren't support at link time. This allows
- * IS_ENABLED to work.
- */
-#ifndef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-GEN_NOT_SUPPORTED(TC_DRP_AUTO_TOGGLE);
-#define TC_DRP_AUTO_TOGGLE TC_DRP_AUTO_TOGGLE_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
-
-#ifndef CONFIG_USB_PD_TCPC_LOW_POWER
-GEN_NOT_SUPPORTED(TC_LOW_POWER_MODE);
-#define TC_LOW_POWER_MODE TC_LOW_POWER_MODE_NOT_SUPPORTED
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-#ifndef CONFIG_USB_PE_SM
-GEN_NOT_SUPPORTED(TC_CT_UNATTACHED_SNK);
-#define TC_CT_UNATTACHED_SNK TC_CT_UNATTACHED_SNK_NOT_SUPPORTED
-GEN_NOT_SUPPORTED(TC_CT_ATTACHED_SNK);
-#define TC_CT_ATTACHED_SNK TC_CT_ATTACHED_SNK_NOT_SUPPORTED
-#endif /* CONFIG_USB_PE_SM */
-
-/*
- * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then
- * _GPIO_CCD_MODE_ODL is not needed. Declare as extern so IS_ENABLED will work.
- */
-#ifndef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-extern int _GPIO_CCD_MODE_ODL;
-#else
-#define _GPIO_CCD_MODE_ODL GPIO_CCD_MODE_ODL
-#endif /* CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT */
-
-/*
- * We will use DEBUG LABELS if we will be able to print (COMMON RUNTIME)
- * and either CONFIG_USB_PD_DEBUG_LEVEL is not defined (no override) or
- * we are overriding and the level is not DISABLED.
- *
- * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
- * then the DEBUG LABELS will be removed from the build.
- */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
-#define USB_PD_DEBUG_LABELS
-#endif
-
-/*
- * Helper Macro to determine if the machine is in state
- * TC_ATTACHED_SRC
- */
-#define IS_ATTACHED_SRC(port) (get_state_tc(port) == TC_ATTACHED_SRC)
-
-/*
- * Helper Macro to determine if the machine is in state
- * TC_ATTACHED_SNK
- */
-#define IS_ATTACHED_SNK(port) (get_state_tc(port) == TC_ATTACHED_SNK)
-
-
-/* List of human readable state names for console debugging */
-__maybe_unused static __const_data const char * const tc_state_names[] = {
-#ifdef USB_PD_DEBUG_LABELS
-	[TC_DISABLED] = "Disabled",
-	[TC_ERROR_RECOVERY] = "ErrorRecovery",
-	[TC_UNATTACHED_SNK] = "Unattached.SNK",
-	[TC_ATTACH_WAIT_SNK] = "AttachWait.SNK",
-	[TC_ATTACHED_SNK] = "Attached.SNK",
-	[TC_UNATTACHED_SRC] = "Unattached.SRC",
-	[TC_ATTACH_WAIT_SRC] = "AttachWait.SRC",
-	[TC_ATTACHED_SRC] = "Attached.SRC",
-	[TC_TRY_SRC] = "Try.SRC",
-	[TC_TRY_WAIT_SNK] = "TryWait.SNK",
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	[TC_DRP_AUTO_TOGGLE] = "DRPAutoToggle",
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	[TC_LOW_POWER_MODE] = "LowPowerMode",
-#endif
-#ifdef CONFIG_USB_PE_SM
-	[TC_CT_UNATTACHED_SNK] =  "CTUnattached.SNK",
-	[TC_CT_ATTACHED_SNK] = "CTAttached.SNK",
-#endif
-	/* Super States */
-	[TC_CC_OPEN] = "SS:CC_OPEN",
-	[TC_CC_RD] = "SS:CC_RD",
-	[TC_CC_RP] = "SS:CC_RP",
-
-	[TC_STATE_COUNT] = "",
-#endif
-};
-
-/* Debug log level - higher number == more log */
-#ifdef CONFIG_USB_PD_DEBUG_LEVEL
-static const enum debug_level tc_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
-#else
-static enum debug_level tc_debug_level = DEBUG_LEVEL_1;
-#endif
-
-#ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
-struct bit_name {
-	int		value;
-	const char	*name;
-};
-
-static struct bit_name flag_bit_names[] = {
-	{ TC_FLAGS_VCONN_ON, "VCONN_ON" },
-	{ TC_FLAGS_TS_DTS_PARTNER, "TS_DTS_PARTNER" },
-	{ TC_FLAGS_VBUS_NEVER_LOW, "VBUS_NEVER_LOW" },
-	{ TC_FLAGS_LPM_TRANSITION, "LPM_TRANSITION" },
-	{ TC_FLAGS_LPM_ENGAGED, "LPM_ENGAGED" },
-	{ TC_FLAGS_CTVPD_DETECTED, "CTVPD_DETECTED" },
-	{ TC_FLAGS_REQUEST_VC_SWAP_ON, "REQUEST_VC_SWAP_ON" },
-	{ TC_FLAGS_REQUEST_VC_SWAP_OFF, "REQUEST_VC_SWAP_OFF" },
-	{ TC_FLAGS_REJECT_VCONN_SWAP, "REJECT_VCONN_SWAP" },
-	{ TC_FLAGS_REQUEST_PR_SWAP, "REQUEST_PR_SWAP" },
-	{ TC_FLAGS_REQUEST_DR_SWAP, "REQUEST_DR_SWAP" },
-	{ TC_FLAGS_POWER_OFF_SNK, "POWER_OFF_SNK" },
-	{ TC_FLAGS_PARTNER_PD_CAPABLE, "PARTNER_PD_CAPABLE" },
-	{ TC_FLAGS_HARD_RESET_REQUESTED, "HARD_RESET_REQUESTED" },
-	{ TC_FLAGS_PR_SWAP_IN_PROGRESS, "PR_SWAP_IN_PROGRESS" },
-	{ TC_FLAGS_CHECK_CONNECTION, "CHECK_CONNECTION" },
-	{ TC_FLAGS_REQUEST_SUSPEND, "REQUEST_SUSPEND" },
-	{ TC_FLAGS_SUSPENDED, "SUSPENDED" },
-	{ TC_FLAGS_UPDATE_CURRENT, "UPDATE_CURRENT" },
-	{ TC_FLAGS_UPDATE_USB_MUX, "UPDATE_USB_MUX" },
-	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN,
-			"USB_RETIMER_FW_UPDATE_RUN" },
-	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN,
-			"USB_RETIMER_FW_UPDATE_LTD_RUN" },
-	{ TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY"},
-};
-BUILD_ASSERT(ARRAY_SIZE(flag_bit_names) == TC_FLAGS_COUNT);
-
-static struct bit_name event_bit_names[] = {
-	{ TASK_EVENT_SYSJUMP_READY, "SYSJUMP_READY" },
-	{ TASK_EVENT_IPC_READY, "IPC_READY" },
-	{ TASK_EVENT_PD_AWAKE, "PD_AWAKE" },
-	{ TASK_EVENT_PECI_DONE, "PECI_DONE" },
-	{ TASK_EVENT_I2C_IDLE, "I2C_IDLE" },
-#ifdef TASK_EVENT_PS2_DONE
-	{ TASK_EVENT_PS2_DONE, "PS2_DONE" },
-#endif
-	{ TASK_EVENT_DMA_TC, "DMA_TC" },
-	{ TASK_EVENT_ADC_DONE, "ADC_DONE" },
-	{ TASK_EVENT_RESET_DONE, "RESET_DONE" },
-	{ TASK_EVENT_WAKE, "WAKE" },
-	{ TASK_EVENT_MUTEX, "MUTEX" },
-	{ TASK_EVENT_TIMER, "TIMER" },
-	{ PD_EVENT_TX, "TX" },
-	{ PD_EVENT_CC, "CC" },
-	{ PD_EVENT_TCPC_RESET, "TCPC_RESET" },
-	{ PD_EVENT_UPDATE_DUAL_ROLE, "UPDATE_DUAL_ROLE" },
-	{ PD_EVENT_DEVICE_ACCESSED, "DEVICE_ACCESSED" },
-	{ PD_EVENT_POWER_STATE_CHANGE, "POWER_STATE_CHANGE" },
-	{ PD_EVENT_SEND_HARD_RESET, "SEND_HARD_RESET" },
-	{ PD_EVENT_SYSJUMP, "SYSJUMP" },
-};
-
-static void print_bits(int port, const char *desc, int value,
-		       struct bit_name *names, int names_size)
-{
-	int i;
-
-	CPRINTF("C%d: %s 0x%x : ", port, desc, value);
-	for (i = 0; i < names_size; i++) {
-		if (value & names[i].value)
-			CPRINTF("%s | ", names[i].name);
-		value &= ~names[i].value;
-	}
-	if (value != 0)
-		CPRINTF("0x%x", value);
-	CPRINTF("\n");
-}
-
-void print_flag(int port, int set_or_clear, int flag)
-{
-	print_bits(port, set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
-		   ARRAY_SIZE(flag_bit_names));
-}
-#endif /* DEBUG_PRINT_FLAG_AND_EVENT_NAMES */
-
-#ifndef CONFIG_USB_PD_TRY_SRC
-extern int TC_TRY_SRC_UNDEFINED;
-extern int TC_TRY_WAIT_SNK_UNDEFINED;
-#define TC_TRY_SRC	TC_TRY_SRC_UNDEFINED
-#define TC_TRY_WAIT_SNK	TC_TRY_WAIT_SNK_UNDEFINED
-#endif
-
-static struct type_c {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* current port power role (SOURCE or SINK) */
-	enum pd_power_role power_role;
-	/* current port data role (DFP or UFP) */
-	enum pd_data_role data_role;
-	/*
-	 * Higher-level power deliver state machines are enabled if false,
-	 * else they're disabled if bits PD_DISABLED_NO_CONNECTION or
-	 * PD_DISABLED_BY_POLICY are set.
-	 */
-	uint32_t pd_disabled_mask;
-	/*
-	 * Timer for handling TOGGLE_OFF/FORCE_SINK mode when auto-toggle
-	 * enabled. See drp_auto_toggle_next_state() for details.
-	 */
-	uint64_t drp_sink_time;
-#ifdef CONFIG_USB_PE_SM
-	/* Power supply reset sequence during a hard reset */
-	enum ps_reset_sequence ps_reset_state;
-#endif
-	/* Port polarity */
-	enum tcpc_cc_polarity polarity;
-	/* port flags, see TC_FLAGS_* */
-	uint32_t flags;
-	/* The cc state */
-	enum pd_cc_states cc_state;
-	/* Tasks to notify after TCPC has been reset */
-	int tasks_waiting_on_reset;
-	/* Tasks preventing TCPC from entering low power mode */
-	int tasks_preventing_lpm;
-	/* Voltage on CC pin */
-	enum tcpc_cc_voltage_status cc_voltage;
-	/* Type-C current */
-	typec_current_t typec_curr;
-	/* Type-C current change */
-	typec_current_t typec_curr_change;
-
-	/* Selected TCPC CC/Rp values */
-	enum tcpc_cc_pull select_cc_pull;
-	enum tcpc_rp_value select_current_limit_rp;
-	enum tcpc_rp_value select_collision_rp;
-} tc[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Port dual-role state */
-static volatile __maybe_unused
-enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
-
-static void set_vconn(int port, int enable);
-
-/* Forward declare common, private functions */
-static __maybe_unused int reset_device_and_notify(int port);
-static __maybe_unused void check_drp_connection(const int port);
-static void sink_power_sub_states(int port);
-static void set_ccd_mode(int port, bool enable);
-
-__maybe_unused static void handle_new_power_state(int port);
-
-static void pd_update_dual_role_config(int port);
-
-/* Forward declare common, private functions */
-static void set_state_tc(const int port, const enum usb_tc_state new_state);
-test_export_static enum usb_tc_state get_state_tc(const int port);
-
-/* Enable variable for Try.SRC states */
-static uint32_t pd_try_src;
-static volatile enum try_src_override_t pd_try_src_override;
-static void pd_update_try_source(void);
-
-static void sink_stop_drawing_current(int port);
-
-__maybe_unused static bool is_try_src_enabled(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		assert(0);
-
-	return ((pd_try_src_override == TRY_SRC_OVERRIDE_ON) ||
-		(pd_try_src_override == TRY_SRC_NO_OVERRIDE && pd_try_src));
-}
-
-/*
- * Public Functions
- *
- * NOTE: Functions prefixed with pd_ are defined in usb_pd.h
- *       Functions prefixed with tc_ are defined int usb_tc_sm.h
- */
-
-#ifndef CONFIG_USB_PRL_SM
-
-/*
- * These pd_ functions are implemented in common/usb_prl_sm.c
- */
-
-void pd_transmit_complete(int port, int status)
-{
-	/* DO NOTHING */
-}
-
-void pd_execute_hard_reset(int port)
-{
-	/* DO NOTHING */
-}
-
-__overridable void pd_set_vbus_discharge(int port, int enable)
-{
-	/* DO NOTHING */
-}
-
-#endif /* !CONFIG_USB_PRL_SM */
-
-#ifndef CONFIG_USB_PE_SM
-
-/*
- * These pd_ functions are implemented in the PE layer
- */
-const uint32_t * const pd_get_src_caps(int port)
-{
-	return NULL;
-}
-
-uint8_t pd_get_src_cap_cnt(int port)
-{
-	return 0;
-}
-
-const uint32_t * const pd_get_snk_caps(int port)
-{
-	return NULL;
-}
-
-uint8_t pd_get_snk_cap_cnt(int port)
-{
-	return 0;
-}
-
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-}
-
-int pd_get_rev(int port, enum tcpci_msg_type type)
-{
-	return PD_REV30;
-}
-
-#endif /* !CONFIG_USB_PR_SM */
-
-#ifndef HAS_TASK_CHIPSET
-__overridable enum pd_dual_role_states board_tc_get_initial_drp_mode(int port)
-{
-	/*
-	 * DRP state is typically adjusted as the chipset state is changed. For
-	 * projects which don't include an AP this function can be used for to
-	 * specify what the starting DRP state should be.
-	 */
-	return PD_DRP_FORCE_SINK;
-}
-#endif
-
-void pd_update_contract(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (IS_ATTACHED_SRC(port))
-			pd_dpm_request(port, DPM_REQUEST_SRC_CAP_CHANGE);
-	}
-}
-
-void pd_request_source_voltage(int port, int mv)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		pd_set_max_voltage(mv);
-
-		if (IS_ATTACHED_SNK(port))
-			pd_dpm_request(port, DPM_REQUEST_NEW_POWER_LEVEL);
-		else
-			pd_dpm_request(port, DPM_REQUEST_PR_SWAP);
-
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_set_external_voltage_limit(int port, int mv)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		pd_set_max_voltage(mv);
-
-		/* Must be in Attached.SNK when this function is called */
-		if (get_state_tc(port) == TC_ATTACHED_SNK)
-			pd_dpm_request(port, DPM_REQUEST_NEW_POWER_LEVEL);
-
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_set_new_power_request(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		/* Must be in Attached.SNK when this function is called */
-		if (get_state_tc(port) == TC_ATTACHED_SNK)
-			pd_dpm_request(port, DPM_REQUEST_NEW_POWER_LEVEL);
-	}
-}
-
-void tc_request_power_swap(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		/*
-		 * Must be in Attached.SRC or Attached.SNK
-		 */
-		if (IS_ATTACHED_SRC(port) || IS_ATTACHED_SNK(port)) {
-			TC_SET_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
-
-			/* Let tc_pr_swap_complete start the Vbus debounce */
-			pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
-		}
-
-		/*
-		 * TCPCI Rev2 V1.1 4.4.5.4.4
-		 * Disconnect Detection by the Sink TCPC during a Connection
-		 *
-		 * Upon reception of or prior to transmitting a PR_Swap
-		 * message, the TCPM acting as a Sink shall disable the Sink
-		 * disconnect detection to retain PD message delivery when
-		 * Power Role Swap happens. Disable AutoDischargeDisconnect.
-		 */
-		if (IS_ATTACHED_SNK(port))
-			tcpm_enable_auto_discharge_disconnect(port, 0);
-	}
-}
-
-/* Flag to indicate PD comm is disabled on init */
-static int pd_disabled_on_init;
-
-static void pd_update_pd_comm(void)
-{
-	int i;
-
-	/*
-	 * Some batteries take much longer time to report its SOC.
-	 * The init function disabled PD comm on startup. Need this
-	 * hook to enable PD comm when the battery level is enough.
-	 */
-	if (pd_disabled_on_init && pd_is_battery_capable()) {
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-			pd_comm_enable(i, 1);
-		pd_disabled_on_init = 0;
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pd_update_pd_comm, HOOK_PRIO_DEFAULT);
-
-static bool pd_comm_allowed_by_policy(void)
-{
-	if (system_is_in_rw())
-		return true;
-
-	if (vboot_allow_usb_pd())
-		return true;
-
-	/*
-	 * If enable PD in RO on a non-EFS2 device, a hard reset will be issued
-	 * when sysjump to RW that makes the device brownout on the dead-battery
-	 * case. Disable PD for this special case as a workaround.
-	 */
-	if (!system_is_locked()) {
-		if (IS_ENABLED(CONFIG_VBOOT_EFS2))
-			return true;
-
-		if (pd_is_battery_capable())
-			return true;
-
-		pd_disabled_on_init = 1;
-	}
-
-	return false;
-}
-
-static void tc_policy_pd_enable(int port, int en)
-{
-	if (en)
-		atomic_clear_bits(&tc[port].pd_disabled_mask,
-				  PD_DISABLED_BY_POLICY);
-	else
-		atomic_or(&tc[port].pd_disabled_mask, PD_DISABLED_BY_POLICY);
-
-	CPRINTS("C%d: PD comm policy %sabled", port, en ? "en" : "dis");
-}
-
-static void tc_enable_pd(int port, int en)
-{
-	if (en)
-		atomic_clear_bits(&tc[port].pd_disabled_mask,
-				  PD_DISABLED_NO_CONNECTION);
-	else
-		atomic_or(&tc[port].pd_disabled_mask,
-			  PD_DISABLED_NO_CONNECTION);
-}
-
-__maybe_unused static void tc_enable_try_src(int en)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		assert(0);
-
-	if (en)
-		atomic_or(&pd_try_src, 1);
-	else
-		atomic_clear_bits(&pd_try_src, 1);
-}
-
-/*
- * Exit all modes due to a detach event
- * Note: this skips the ExitMode VDM steps in the PE because it is assumed the
- * partner is not present to receive them, and the PE will no longer be running.
- */
-static void tc_set_modes_exit(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-			IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-		pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0);
-		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, 0, 0);
-		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME_PRIME, 0, 0);
-	}
-}
-
-static void tc_detached(int port)
-{
-	TC_CLR_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
-	hook_notify(HOOK_USB_PD_DISCONNECT);
-	tc_pd_connection(port, 0);
-	tcpm_debug_accessory(port, 0);
-	set_ccd_mode(port, 0);
-	tc_set_modes_exit(port);
-	if (IS_ENABLED(CONFIG_USB_PRL_SM))
-		prl_set_default_pd_revision(port);
-
-	/* Clear any mux connection on detach */
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		usb_mux_set(port, USB_PD_MUX_NONE,
-			    USB_SWITCH_DISCONNECT, tc[port].polarity);
-}
-
-static inline void pd_set_dual_role_and_event(int port,
-				enum pd_dual_role_states state, uint32_t event)
-{
-	drp_state[port] = state;
-
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		pd_update_try_source();
-
-	if (event != 0)
-		task_set_event(PD_PORT_TO_TASK_ID(port), event);
-}
-
-void pd_set_dual_role(int port, enum pd_dual_role_states state)
-{
-	pd_set_dual_role_and_event(port, state, PD_EVENT_UPDATE_DUAL_ROLE);
-}
-
-int pd_comm_is_enabled(int port)
-{
-	return tc_get_pd_enabled(port);
-}
-
-void pd_request_data_swap(int port)
-{
-	/*
-	 * Must be in Attached.SRC, Attached.SNK, DebugAccessory.SNK,
-	 * or UnorientedDebugAccessory.SRC when this function
-	 * is called
-	 */
-	if (IS_ATTACHED_SRC(port) || IS_ATTACHED_SNK(port)) {
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_DR_SWAP);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-/* Return true if partner port is known to be PD capable. */
-bool pd_capable(int port)
-{
-	return !!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE);
-}
-
-/*
- * Return true if we transition through Unattached.SNK, but we're still waiting
- * to receive source caps from the partner. This indicates that the PD
- * capabilities are not yet known.
- */
-bool pd_waiting_on_partner_src_caps(int port)
-{
-	return !pd_get_src_cap_cnt(port);
-}
-
-enum pd_dual_role_states pd_get_dual_role(int port)
-{
-	return drp_state[port];
-}
-
-#ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
-static inline void pd_dev_dump_info(uint16_t dev_id, uint32_t *hash)
-{
-	int j;
-
-	ccprintf("DevId:%d.%d Hash:", HW_DEV_ID_MAJ(dev_id),
-		 HW_DEV_ID_MIN(dev_id));
-	for (j = 0; j < PD_RW_HASH_SIZE / 4; j++)
-		ccprintf(" %08x ", hash[j]);
-	ccprintf("\n");
-}
-#endif /* CONFIG_CMD_PD_DEV_DUMP_INFO */
-
-const char *tc_get_current_state(int port)
-{
-	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
-		return tc_state_names[get_state_tc(port)];
-	else
-		return "";
-}
-
-uint32_t tc_get_flags(int port)
-{
-	return tc[port].flags;
-}
-
-int tc_is_attached_src(int port)
-{
-	return IS_ATTACHED_SRC(port);
-}
-
-int tc_is_attached_snk(int port)
-{
-	return IS_ATTACHED_SNK(port);
-}
-
-void tc_pd_connection(int port, int en)
-{
-	if (en) {
-		bool new_pd_capable = false;
-
-		if (!TC_CHK_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE))
-			new_pd_capable = true;
-
-		TC_SET_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE);
-		/* If a PD device is attached then disable deep sleep */
-		if (IS_ENABLED(CONFIG_LOW_POWER_IDLE) &&
-		    !IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP)) {
-			disable_sleep(SLEEP_MASK_USB_PD);
-		}
-
-		/*
-		 * Update the mux state, only when the PD capable flag
-		 * transitions from 0 to 1. This ensures that PD charger
-		 * devices, without data capability are not marked as having
-		 * USB.
-		 */
-		if (new_pd_capable)
-			set_usb_mux_with_current_data_role(port);
-	} else {
-		TC_CLR_FLAG(port, TC_FLAGS_PARTNER_PD_CAPABLE);
-		/* If a PD device isn't attached then enable deep sleep */
-		if (IS_ENABLED(CONFIG_LOW_POWER_IDLE) &&
-		    !IS_ENABLED(CONFIG_USB_PD_TCPC_ON_CHIP)) {
-			int i;
-
-			/* If all ports are not connected, allow the sleep */
-			for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-				if (pd_capable(i))
-					break;
-			}
-			if (i == board_get_usb_pd_port_count())
-				enable_sleep(SLEEP_MASK_USB_PD);
-		}
-	}
-}
-
-void tc_ctvpd_detected(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_CTVPD_DETECTED);
-}
-
-void pd_try_vconn_src(int port)
-{
-	set_vconn(port, 1);
-}
-
-int tc_check_vconn_swap(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
-		if (TC_CHK_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP))
-			return 0;
-
-		return pd_check_vconn_swap(port);
-	} else
-		return 0;
-}
-
-void tc_pr_swap_complete(int port, bool success)
-{
-	if (IS_ATTACHED_SNK(port)) {
-		/*
-		 * Give the ADCs in the TCPC or PPC time to react following
-		 * a PS_RDY message received during a SRC to SNK swap.
-		 * Note: This is empirically determined, not strictly
-		 * part of the USB PD spec.
-		 * Note: Swap in progress should not be cleared until the
-		 * debounce is completed.
-		 */
-		pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE, PD_T_DEBOUNCE);
-	} else {
-		/* PR Swap is no longer in progress */
-		TC_CLR_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
-
-		/*
-		 * AutoDischargeDisconnect was turned off near the SNK->SRC
-		 * PR-Swap message. If the swap was a success, Vbus should be
-		 * valid, so re-enable AutoDischargeDisconnect
-		 */
-		if (success)
-			tcpm_enable_auto_discharge_disconnect(port, 1);
-	}
-}
-
-void tc_prs_src_snk_assert_rd(int port)
-{
-	/*
-	 * Must be in Attached.SRC or UnorientedDebugAccessory.SRC
-	 * when this function is called
-	 */
-	if (IS_ATTACHED_SRC(port)) {
-		/*
-		 * Transition to Attached.SNK to
-		 * DebugAccessory.SNK assert Rd
-		 */
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void tc_prs_snk_src_assert_rp(int port)
-{
-	/*
-	 * Must be in Attached.SNK or DebugAccessory.SNK
-	 * when this function is called
-	 */
-	if (IS_ATTACHED_SNK(port)) {
-		/*
-		 * Transition to Attached.SRC or
-		 * UnorientedDebugAccessory.SRC to assert Rp
-		 */
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-/*
- * Hard Reset is being requested.  This should not allow a TC connection
- * to go to an unattached state until the connection is recovered from
- * the hard reset.  It is possible for a Hard Reset to cause a timeout
- * in trying to recover and an additional Hard Reset would be issued.
- * During this entire process it is important that the TC is not allowed
- * to go to an unattached state.
- *
- * Type-C Spec Rev 2.0 section 4.5.2.2.5.2
- * Exiting from Attached.SNK State
- * A port that is not a V CONN-Powered USB Device and is not in the
- * process of a USB PD PR_Swap or a USB PD Hard Reset or a USB PD
- * FR_Swap shall transition to Unattached.SNK
- */
-void tc_hard_reset_request(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void tc_try_src_override(enum try_src_override_t ov)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		assert(0);
-
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) {
-		switch (ov) {
-		case TRY_SRC_OVERRIDE_OFF: /* 0 */
-			pd_try_src_override = TRY_SRC_OVERRIDE_OFF;
-			break;
-		case TRY_SRC_OVERRIDE_ON: /* 1 */
-			pd_try_src_override = TRY_SRC_OVERRIDE_ON;
-			break;
-		default:
-			pd_try_src_override = TRY_SRC_NO_OVERRIDE;
-		}
-	}
-}
-
-enum try_src_override_t tc_get_try_src_override(void)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		assert(0);
-
-	return pd_try_src_override;
-}
-
-void tc_snk_power_off(int port)
-{
-	if (IS_ATTACHED_SNK(port)) {
-		TC_SET_FLAG(port, TC_FLAGS_POWER_OFF_SNK);
-		sink_stop_drawing_current(port);
-	}
-}
-
-int tc_src_power_on(int port)
-{
-	/*
-	 * Check our OC event counter.  If we've exceeded our threshold, then
-	 * let's latch our source path off to prevent continuous cycling.  When
-	 * the PD state machine detects a disconnection on the CC lines, we will
-	 * reset our OC event counter.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_OCP) && usbc_ocp_is_port_latched_off(port))
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (IS_ATTACHED_SRC(port))
-		return pd_set_power_supply_ready(port);
-
-	return 0;
-}
-
-void tc_src_power_off(int port)
-{
-	/* Remove VBUS */
-	pd_power_supply_reset(port);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
-					CHARGE_CEIL_NONE);
-}
-
-/* Set what role the partner is right now, for the PPC and OCP module */
-static void tc_set_partner_role(int port, enum ppc_device_role role)
-{
-	if (IS_ENABLED(CONFIG_USBC_PPC))
-		ppc_dev_is_connected(port, role);
-
-	if (IS_ENABLED(CONFIG_USBC_OCP)) {
-		usbc_ocp_snk_is_connected(port, role == PPC_DEV_SNK);
-		/*
-		 * Clear the overcurrent event counter
-		 * since we've detected a disconnect.
-		 */
-		if (role == PPC_DEV_DISCONNECTED)
-			usbc_ocp_clear_event_counter(port);
-	}
-}
-
-/*
- * Depending on the load on the processor and the tasks running
- * it can take a while for the task associated with this port
- * to run.  So build in 1ms delays, for up to 300ms, to wait for
- * the suspend to actually happen.
- */
-#define SUSPEND_SLEEP_DELAY	1
-#define SUSPEND_SLEEP_RETRIES	300
-
-void pd_set_suspend(int port, int suspend)
-{
-	if (pd_is_port_enabled(port) == !suspend)
-		return;
-
-	/* Track if we are suspended or not */
-	if (suspend) {
-		int wait = 0;
-
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
-
-		/*
-		 * Avoid deadlock when running from task
-		 * which we are going to suspend
-		 */
-		if (PD_PORT_TO_TASK_ID(port) == task_get_current())
-			return;
-
-		task_wake(PD_PORT_TO_TASK_ID(port));
-
-		/* Sleep this task if we are not suspended */
-		while (pd_is_port_enabled(port)) {
-			if (++wait > SUSPEND_SLEEP_RETRIES) {
-				CPRINTS("C%d: NOT SUSPENDED after %dms",
-					port, wait * SUSPEND_SLEEP_DELAY);
-				return;
-			}
-			msleep(SUSPEND_SLEEP_DELAY);
-		}
-	} else {
-		TC_CLR_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_set_error_recovery(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY);
-}
-
-int pd_is_port_enabled(int port)
-{
-	/*
-	 * Checking get_state_tc(port) from another task isn't safe since it
-	 * can return TC_DISABLED before tc_cc_open_entry and tc_disabled_entry
-	 * are complete. So check TC_FLAGS_SUSPENDED instead.
-	 */
-	return !TC_CHK_FLAG(port, TC_FLAGS_SUSPENDED);
-}
-
-int pd_fetch_acc_log_entry(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PE_SM))
-		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_GET_LOG, NULL, 0);
-
-	return EC_RES_SUCCESS;
-}
-
-enum tcpc_cc_polarity pd_get_polarity(int port)
-{
-	return tc[port].polarity;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	return tc[port].data_role;
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return tc[port].power_role;
-}
-
-enum pd_cc_states pd_get_task_cc_state(int port)
-{
-	return tc[port].cc_state;
-}
-
-uint8_t pd_get_task_state(int port)
-{
-	return get_state_tc(port);
-}
-
-bool pd_get_vconn_state(int port)
-{
-	return !!TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON);
-}
-
-const char *pd_get_task_state_name(int port)
-{
-	return tc_get_current_state(port);
-}
-
-void pd_vbus_low(int port)
-{
-	TC_CLR_FLAG(port, TC_FLAGS_VBUS_NEVER_LOW);
-}
-
-int pd_is_connected(int port)
-{
-	return (IS_ATTACHED_SRC(port) ||
-		(IS_ENABLED(CONFIG_USB_PE_SM) &&
-		((get_state_tc(port) == TC_CT_UNATTACHED_SNK) ||
-		(get_state_tc(port) == TC_CT_ATTACHED_SNK))) ||
-		IS_ATTACHED_SNK(port));
-}
-
-bool pd_is_disconnected(int port)
-{
-	return !pd_is_connected(port);
-}
-
-/*
- * PD functions which query our fixed PDO flags.  Both the source and sink
- * capabilities can present these values, and they should match between the two
- * for compliant partners.
- */
-static bool pd_check_fixed_flag(int port, uint32_t flag)
-{
-	uint32_t fixed_pdo;
-
-	if (pd_get_src_cap_cnt(port) != 0)
-		fixed_pdo = *pd_get_src_caps(port);
-	else if (pd_get_snk_cap_cnt(port) != 0)
-		fixed_pdo = *pd_get_snk_caps(port);
-	else
-		return false;
-
-	/*
-	 * Error check that first PDO is fixed, as 6.4.1 Capabilities requires
-	 * in the Power Delivery Specification.
-	 * "The vSafe5V Fixed Supply Object Shall always be the first object"
-	 */
-	if ((fixed_pdo & PDO_TYPE_MASK) != PDO_TYPE_FIXED)
-		return false;
-
-	return fixed_pdo & flag;
-}
-
-bool pd_get_partner_data_swap_capable(int port)
-{
-	return pd_check_fixed_flag(port, PDO_FIXED_DATA_SWAP);
-}
-
-bool pd_get_partner_usb_comm_capable(int port)
-{
-	return pd_check_fixed_flag(port, PDO_FIXED_COMM_CAP);
-}
-
-bool pd_get_partner_dual_role_power(int port)
-{
-	return pd_check_fixed_flag(port, PDO_FIXED_DUAL_ROLE);
-}
-
-bool pd_get_partner_unconstr_power(int port)
-{
-	return pd_check_fixed_flag(port, PDO_FIXED_UNCONSTRAINED);
-}
-
-static void bc12_role_change_handler(int port, enum pd_data_role prev_data_role,
-	enum pd_data_role data_role)
-{
-	int event = 0;
-	int task_id = USB_CHG_PORT_TO_TASK_ID(port);
-	bool role_changed = (data_role != prev_data_role);
-
-	if (!IS_ENABLED(CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER))
-		return;
-
-	/* Get the data role of our device */
-	switch (data_role) {
-	case PD_ROLE_UFP:
-		/* Only trigger BC12 detection on a role change */
-		if (role_changed)
-			event = USB_CHG_EVENT_DR_UFP;
-		break;
-	case PD_ROLE_DFP:
-		/* Only trigger BC12 host mode on a role change */
-		if (role_changed)
-			event = USB_CHG_EVENT_DR_DFP;
-		break;
-	case PD_ROLE_DISCONNECTED:
-		event = USB_CHG_EVENT_CC_OPEN;
-		break;
-	default:
-		return;
-	}
-
-	if (event)
-		task_set_event(task_id, event);
-}
-
-/*
- * TCPC CC/Rp management
- */
-static void typec_select_pull(int port, enum tcpc_cc_pull pull)
-{
-	tc[port].select_cc_pull = pull;
-}
-void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
-{
-	tc[port].select_current_limit_rp = rp;
-	if (IS_ATTACHED_SRC(port))
-		TC_SET_FLAG(port, TC_FLAGS_UPDATE_CURRENT);
-}
-__overridable int typec_get_default_current_limit_rp(int port)
-{
-	return CONFIG_USB_PD_PULLUP;
-}
-void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
-{
-	tc[port].select_collision_rp = rp;
-}
-static enum tcpc_rp_value typec_get_active_select_rp(int port)
-{
-	/* Explicit contract will use the collision Rp */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	    pe_is_explicit_contract(port))
-		return tc[port].select_collision_rp;
-	return tc[port].select_current_limit_rp;
-}
-int typec_update_cc(int port)
-{
-	int rv;
-	enum tcpc_cc_pull pull = tc[port].select_cc_pull;
-	enum tcpc_rp_value rp = typec_get_active_select_rp(port);
-
-	rv = tcpm_select_rp_value(port, rp);
-	if (rv)
-		return rv;
-
-	return tcpm_set_cc(port, pull);
-}
-
-#ifdef CONFIG_USB_PE_SM
-/*
- * This function performs a source hard reset. It should be called
- * repeatedly until a true value is returned, signaling that the
- * source hard reset is complete. A false value is returned otherwise.
- */
-static bool tc_perform_src_hard_reset(int port)
-{
-	switch (tc[port].ps_reset_state) {
-	case PS_STATE0:
-		/* Remove VBUS */
-		tc_src_power_off(port);
-
-		/* Turn off VCONN */
-		set_vconn(port, 0);
-
-		/* Set role to DFP */
-		tc_set_data_role(port, PD_ROLE_DFP);
-
-		tc[port].ps_reset_state = PS_STATE1;
-		pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SRC_RECOVER);
-		return false;
-	case PS_STATE1:
-		/* Enable VBUS */
-		tc_src_power_on(port);
-
-		/* Update the Rp Value */
-		typec_update_cc(port);
-
-		/* Turn off VCONN */
-		set_vconn(port, 1);
-
-		tc[port].ps_reset_state = PS_STATE2;
-		pd_timer_enable(port, TC_TIMER_TIMEOUT,
-				PD_POWER_SUPPLY_TURN_ON_DELAY);
-		return false;
-	case PS_STATE2:
-		/* Tell Policy Engine Hard Reset is complete */
-		pe_ps_reset_complete(port);
-
-		tc[port].ps_reset_state = PS_STATE0;
-		return true;
-	}
-
-	/*
-	 * This return is added to appease the compiler. It should
-	 * never be reached because the switch handles all possible
-	 * cases of the enum ps_reset_sequence type.
-	 */
-	return true;
-}
-
-/*
- * Wait for recovery after a hard reset.  Call repeatedly until true is
- * returned, signaling that the hard reset is complete.
- */
-static bool tc_perform_snk_hard_reset(int port)
-{
-	switch (tc[port].ps_reset_state) {
-	case PS_STATE0:
-		/* Hard reset sets us back to default data role */
-		tc_set_data_role(port, PD_ROLE_UFP);
-
-		/*
-		 * When VCONN is supported, the Hard Reset Shall cause
-		 * the Port with the Rd resistor asserted to turn off
-		 * VCONN.
-		 */
-		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-		    TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON))
-			set_vconn(port, 0);
-
-		/* Wait up to tVSafe0V for Vbus to disappear */
-		tc[port].ps_reset_state = PS_STATE1;
-		pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SAFE_0V);
-		return false;
-	case PS_STATE1:
-		if (pd_check_vbus_level(port, VBUS_SAFE0V)) {
-			/*
-			 * Partner dropped Vbus, reduce our current consumption
-			 * and await its return.
-			 */
-			sink_stop_drawing_current(port);
-
-			tcpm_enable_auto_discharge_disconnect(port, 0);
-
-			/* Move on to waiting for the return of Vbus */
-			tc[port].ps_reset_state = PS_STATE2;
-			pd_timer_enable(port, TC_TIMER_TIMEOUT,
-					PD_T_SRC_RECOVER_MAX +
-					PD_T_SRC_TURN_ON);
-		}
-
-		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
-			/*
-			 * No Vbus drop likely indicates a non-PD port partner,
-			 * move to the next stage anyway.
-			 */
-			tc[port].ps_reset_state = PS_STATE2;
-			pd_timer_enable(port, TC_TIMER_TIMEOUT,
-					PD_T_SRC_RECOVER_MAX +
-					PD_T_SRC_TURN_ON);
-		}
-		return false;
-	case PS_STATE2:
-		/*
-		 * Look for the voltage to be above disconnect.  Since we didn't
-		 * drop our draw on non-PD partners, they may have dipped below
-		 * vSafe5V but still be in a valid connected voltage.
-		 */
-		if (!pd_check_vbus_level(port, VBUS_REMOVED)) {
-			/*
-			 * Inform policy engine that power supply
-			 * reset is complete
-			 */
-			tc[port].ps_reset_state = PS_STATE0;
-			pe_ps_reset_complete(port);
-
-			/*
-			 * Now that VBUS is back, let's notify charge manager
-			 * regarding the source's current capabilities.
-			 * sink_power_sub_states() reacts to changes in CC
-			 * terminations, however during a HardReset, the
-			 * terminations of a non-PD port partner will not
-			 * change.  Therefore, set the debounce time to right
-			 * now, such that we'll actually reset the correct input
-			 * current limit.
-			 */
-			pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, 0);
-			sink_power_sub_states(port);
-
-			/* Power is back, Enable AutoDischargeDisconnect */
-			tcpm_enable_auto_discharge_disconnect(port, 1);
-			return true;
-		}
-		/*
-		 * If Vbus isn't back after wait + tSrcTurnOn, go unattached
-		 */
-		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
-			tc[port].ps_reset_state = PS_STATE0;
-			set_state_tc(port, TC_UNATTACHED_SNK);
-			return true;
-		}
-	}
-
-	return false;
-}
-#endif /* CONFIG_USB_PE_SM */
-
-void tc_start_error_recovery(int port)
-{
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	/*
-	 *   The port should transition to the ErrorRecovery state
-	 *   from any other state when directed.
-	 */
-	set_state_tc(port, TC_ERROR_RECOVERY);
-}
-
-static void restart_tc_sm(int port, enum usb_tc_state start_state)
-{
-	int res;
-
-	/* Clear flags before we transitions states */
-	tc[port].flags = 0;
-
-	res = tcpm_init(port);
-
-	CPRINTS("C%d: TCPC init %s", port, res ? "failed" : "ready");
-
-	/*
-	 * Update the Rp Value. We don't need to update CC lines though as that
-	 * happens in below set_state transition.
-	 */
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
-
-	/* Disable if restart failed, otherwise start in default state. */
-	set_state_tc(port, res ? TC_DISABLED : start_state);
-
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		/* Initialize USB mux to its default state */
-		usb_mux_init(port);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC)) {
-		/*
-		 * Wait to initialize the PPC after tcpc, which sets
-		 * the correct Rd values; otherwise the TCPC might
-		 * not be pulling the CC lines down when the PPC connects the
-		 * CC lines from the USB connector to the TCPC cause the source
-		 * to drop Vbus causing a brown out.
-		 */
-		ppc_init(port);
-	}
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		/*
-		 * Only initialize PD supplier current limit to 0.
-		 * Defer initializing type-C supplier current limit
-		 * to Unattached.SNK or Attached.SNK.
-		 */
-		pd_set_input_current_limit(port, 0, 0);
-		charge_manager_update_dualrole(port, CAP_UNKNOWN);
-	}
-
-	/*
-	 * PD r3.0 v2.0, ss6.2.1.1.5:
-	 * After a physical or logical (USB Type-C Error Recovery) Attach, a
-	 * Port discovers the common Specification Revision level between itself
-	 * and its Port Partner and/or the Cable Plug(s), and uses this
-	 * Specification Revision level until a Detach, Hard Reset or Error
-	 * Recovery happens.
-	 *
-	 * This covers the Error Recovery case, because TC_ERROR_RECOVERY
-	 * reinitializes the TC state machine. This also covers the implicit
-	 * case when PD is suspended and resumed or when the state machine is
-	 * first initialized.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PRL_SM))
-		prl_set_default_pd_revision(port);
-
-#ifdef CONFIG_USB_PE_SM
-	tc_enable_pd(port, 0);
-	tc[port].ps_reset_state = PS_STATE0;
-#endif
-}
-
-void tc_state_init(int port)
-{
-	enum usb_tc_state first_state;
-
-	/* For test builds, replicate static initialization */
-	if (IS_ENABLED(TEST_BUILD)) {
-		int i;
-
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; ++i) {
-			memset(&tc[i], 0, sizeof(tc[i]));
-			drp_state[i] = CONFIG_USB_PD_INITIAL_DRP_STATE;
-		}
-	}
-
-	/* If port is not available, there is nothing to initialize */
-	if (port >= board_get_usb_pd_port_count()) {
-		tc_enable_pd(port, 0);
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_SUSPEND);
-		return;
-	}
-
-
-	/* Allow system to set try src enable */
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		tc_try_src_override(TRY_SRC_NO_OVERRIDE);
-
-	/*
-	 * Set initial PD communication policy.
-	 */
-	tc_policy_pd_enable(port, pd_comm_allowed_by_policy());
-
-#ifdef HAS_TASK_CHIPSET
-	/* Set dual-role state based on chipset power state */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		pd_set_dual_role_and_event(port, PD_DRP_FORCE_SINK, 0);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(), 0);
-	else /* CHIPSET_STATE_ON */
-		pd_set_dual_role_and_event(port, PD_DRP_TOGGLE_ON, 0);
-#else
-	pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port), 0);
-#endif
-
-	/*
-	 * We are going to apply CC open (start with ErrorRecovery state)
-	 * unless there is something which forbids us to do that (one of
-	 * conditions below is true)
-	 */
-	first_state = TC_ERROR_RECOVERY;
-
-	/*
-	 * If we just lost power, don't apply CC open. Otherwise we would boot
-	 * loop, and if this is a fresh power on, then we know there isn't any
-	 * stale PD state as well.
-	 */
-	if (system_get_reset_flags() &
-	    (EC_RESET_FLAG_BROWNOUT | EC_RESET_FLAG_POWER_ON)) {
-		first_state = TC_UNATTACHED_SNK;
-	}
-
-	/*
-	 * If this is non-EFS2 device, battery is not present and EC RO doesn't
-	 * keep power-on reset flag after reset caused by H1, then don't apply
-	 * CC open because it will cause brown out.
-	 *
-	 * Please note that we are checking if CONFIG_BOARD_RESET_AFTER_POWER_ON
-	 * is defined now, but actually we need to know if it was enabled in
-	 * EC RO! It was assumed that if CONFIG_BOARD_RESET_AFTER_POWER_ON is
-	 * defined now it was defined in EC RO too.
-	 */
-	if (!IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-	    !IS_ENABLED(CONFIG_VBOOT_EFS2) && IS_ENABLED(CONFIG_BATTERY) &&
-	    (battery_is_present() == BP_NO)) {
-		first_state = TC_UNATTACHED_SNK;
-	}
-
-	if (first_state == TC_UNATTACHED_SNK) {
-		/* Turn off any previous sourcing */
-		tc_src_power_off(port);
-		set_vconn(port, 0);
-	}
-
-#ifdef CONFIG_USB_PD_TCPC_BOARD_INIT
-	/* Board specific TCPC init */
-	board_tcpc_init();
-#endif
-
-	/*
-	 * Start with ErrorRecovery state if we can to put us in
-	 * a clean state from any previous boots.
-	 */
-	restart_tc_sm(port, first_state);
-}
-
-enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	/*
-	 * Messages sent by this state machine are always from a DFP/UFP,
-	 * i.e. the chromebook.
-	 */
-	return PD_PLUG_FROM_DFP_UFP;
-}
-
-void pd_comm_enable(int port, int en)
-{
-	tc_policy_pd_enable(port, en);
-}
-
-uint8_t tc_get_polarity(int port)
-{
-	return tc[port].polarity;
-}
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return !tc[port].pd_disabled_mask;
-}
-
-bool pd_alt_mode_capable(int port)
-{
-	return IS_ENABLED(CONFIG_USB_PE_SM) && tc_get_pd_enabled(port);
-}
-
-void tc_set_power_role(int port, enum pd_power_role role)
-{
-	tc[port].power_role = role;
-}
-
-/*
- * Private Functions
- */
-
-/* Set GPIO_CCD_MODE_ODL gpio */
-static void set_ccd_mode(const int port, const bool enable)
-{
-	if (IS_ENABLED(CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT) &&
-	    port == CONFIG_CCD_USBC_PORT_NUMBER) {
-		if (enable)
-			CPRINTS("Asserting GPIO_CCD_MODE_ODL");
-		gpio_set_level(_GPIO_CCD_MODE_ODL, !enable);
-	}
-}
-
-/* Set the TypeC state machine to a new state. */
-static void set_state_tc(const int port, const enum usb_tc_state new_state)
-{
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	set_state(port, &tc[port].ctx, &tc_states[new_state]);
-}
-
-/* Get the current TypeC state. */
-test_export_static enum usb_tc_state get_state_tc(const int port)
-{
-	/* Default to returning TC_STATE_COUNT if no state has been set */
-	if (tc[port].ctx.current == NULL)
-		return TC_STATE_COUNT;
-	else
-		return tc[port].ctx.current - &tc_states[0];
-}
-
-/* Get the previous TypeC state. */
-static enum usb_tc_state get_last_state_tc(const int port)
-{
-	return tc[port].ctx.previous - &tc_states[0];
-}
-
-static void print_current_state(const int port)
-{
-	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
-		CPRINTS_L1("C%d: %s", port, tc_state_names[get_state_tc(port)]);
-	else
-		CPRINTS("C%d: tc-st%d", port, get_state_tc(port));
-}
-
-static void handle_device_access(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
-	    get_state_tc(port) == TC_LOW_POWER_MODE) {
-		tc_start_event_loop(port);
-		pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME,
-				PD_LPM_DEBOUNCE_US);
-	}
-}
-
-void tc_event_check(int port, int evt)
-{
-#ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
-	if (evt != TASK_EVENT_TIMER)
-		print_bits(port, "Event", evt, event_bit_names,
-			   ARRAY_SIZE(event_bit_names));
-#endif
-
-	if (evt & PD_EXIT_LOW_POWER_EVENT_MASK)
-		TC_SET_FLAG(port, TC_FLAGS_CHECK_CONNECTION);
-
-	if (evt & PD_EVENT_DEVICE_ACCESSED)
-		handle_device_access(port);
-
-	if (evt & PD_EVENT_TCPC_RESET)
-		reset_device_and_notify(port);
-
-	if (evt & PD_EVENT_RX_HARD_RESET)
-		pd_execute_hard_reset(port);
-
-	if (evt & PD_EVENT_SEND_HARD_RESET) {
-		/* Pass Hard Reset request to PE layer if available */
-		if (IS_ENABLED(CONFIG_USB_PE_SM) && tc_get_pd_enabled(port))
-			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
-	}
-
-#ifdef CONFIG_POWER_COMMON
-	if (IS_ENABLED(CONFIG_POWER_COMMON)) {
-		if (evt & PD_EVENT_POWER_STATE_CHANGE)
-			handle_new_power_state(port);
-	}
-#endif /* CONFIG_POWER_COMMON */
-
-	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-		int i;
-
-		/*
-		 * Notify all ports of sysjump
-		 */
-		if (evt & PD_EVENT_SYSJUMP) {
-			for (i = 0; i <
-				CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-				dpm_set_mode_exit_request(i);
-			notify_sysjump_ready();
-		}
-	}
-
-	if (evt & PD_EVENT_UPDATE_DUAL_ROLE)
-		pd_update_dual_role_config(port);
-}
-
-/*
- * CC values for regular sources and Debug sources (aka DTS)
- *
- * Source type  Mode of Operation   CC1    CC2
- * ---------------------------------------------
- * Regular      Default USB Power   RpUSB  Open
- * Regular      USB-C @ 1.5 A       Rp1A5  Open
- * Regular      USB-C @ 3 A         Rp3A0  Open
- * DTS          Default USB Power   Rp3A0  Rp1A5
- * DTS          USB-C @ 1.5 A       Rp1A5  RpUSB
- * DTS          USB-C @ 3 A         Rp3A0  RpUSB
- */
-
-void tc_set_data_role(int port, enum pd_data_role role)
-{
-	enum pd_data_role prev_data_role;
-
-	prev_data_role = tc[port].data_role;
-	tc[port].data_role = role;
-
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		set_usb_mux_with_current_data_role(port);
-
-	/*
-	 * Run any board-specific code for role swap (e.g. setting OTG signals
-	 * to SoC).
-	 */
-	pd_execute_data_swap(port, role);
-
-	/*
-	 * For BC1.2 detection that is triggered on data role change events
-	 * instead of VBUS changes, need to set an event to wake up the USB_CHG
-	 * task and indicate the current data role.
-	 */
-	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
-
-	/* Notify TCPC of role update */
-	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
-}
-
-static void sink_stop_drawing_current(int port)
-{
-	pd_set_input_current_limit(port, 0, 0);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE);
-	}
-}
-
-static void pd_update_try_source(void)
-{
-#ifdef CONFIG_USB_PD_TRY_SRC
-	tc_enable_try_src(pd_is_try_source_capable());
-#endif
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pd_update_try_source, HOOK_PRIO_DEFAULT);
-
-static void set_vconn(int port, int enable)
-{
-	if (enable)
-		TC_SET_FLAG(port, TC_FLAGS_VCONN_ON);
-	else
-		TC_CLR_FLAG(port, TC_FLAGS_VCONN_ON);
-
-	/*
-	 * Check our OC event counter.  If we've exceeded our threshold, then
-	 * let's latch our source path off to prevent continuous cycling.  When
-	 * the PD state machine detects a disconnection on the CC lines, we will
-	 * reset our OC event counter.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_OCP) &&
-	    enable && usbc_ocp_is_port_latched_off(port))
-		return;
-
-	/*
-	 * Disable PPC Vconn first then TCPC in case the voltage feeds back
-	 * to TCPC and damages.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && !enable)
-		ppc_set_vconn(port, 0);
-
-	/*
-	 * Some TCPCs/PPC combinations can trigger OVP if the TCPC doesn't
-	 * source VCONN. This happens if the TCPC will trip OVP with 5V, and the
-	 * PPC doesn't isolate the TCPC from VCONN when sourcing. But, some PPCs
-	 * which do isolate the TCPC can't handle 5V on its host-side CC pins,
-	 * so the TCPC shouldn't source VCONN in those cases.
-	 *
-	 * In the first case, both TCPC and PPC will potentially source Vconn,
-	 * but that should be okay since Vconn has "make before break"
-	 * electrical requirements when swapping anyway.
-	 *
-	 * See b/72961003 and b/180973460
-	 */
-	tcpm_set_vconn(port, enable);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_VCONN) && enable)
-		ppc_set_vconn(port, 1);
-}
-
-/* This must only be called from the PD task */
-static void pd_update_dual_role_config(int port)
-{
-	if (tc[port].power_role == PD_ROLE_SOURCE &&
-			(drp_state[port] == PD_DRP_FORCE_SINK ||
-			(drp_state[port] == PD_DRP_TOGGLE_OFF &&
-			get_state_tc(port) == TC_UNATTACHED_SRC))) {
-		/*
-		 * Change to sink if port is currently a source AND (new DRP
-		 * state is force sink OR new DRP state is toggle off and we are
-		 * in the source disconnected state).
-		 */
-		set_state_tc(port, TC_UNATTACHED_SNK);
-	} else if (tc[port].power_role == PD_ROLE_SINK &&
-			drp_state[port] == PD_DRP_FORCE_SOURCE) {
-		/*
-		 * Change to source if port is currently a sink and the
-		 * new DRP state is force source.
-		 */
-		set_state_tc(port, TC_UNATTACHED_SRC);
-	}
-}
-
-__maybe_unused static void handle_new_power_state(int port)
-{
-	if (!IS_ENABLED(CONFIG_POWER_COMMON))
-		assert(0);
-
-	if (IS_ENABLED(CONFIG_POWER_COMMON) &&
-	    IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (chipset_in_or_transitioning_to_state(
-					CHIPSET_STATE_ANY_OFF)) {
-			/*
-			 * The SoC will negotiate alternate mode again when it
-			 * boots up
-			 */
-			dpm_set_mode_exit_request(port);
-		}
-	}
-
-	/*
-	 * If the sink port was sourcing Vconn, and can no longer, request a
-	 * hard reset on this port to restore Vconn to the source.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (tc_is_vconn_src(port) && tc_is_attached_snk(port) &&
-						!pd_check_vconn_swap(port))
-			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
-	}
-
-	/*
-	 * TC_FLAGS_UPDATE_USB_MUX is set on chipset startup and shutdown.
-	 * Set the USB mux according to the new power state.  If the chipset
-	 * is transitioning to OFF, this disconnects USB and DP mux.
-	 *
-	 * Transitions to and from suspend states do not change the USB mux
-	 * or the alternate mode configuration.
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_USB_MUX)) {
-		TC_CLR_FLAG(port, TC_FLAGS_UPDATE_USB_MUX);
-		set_usb_mux_with_current_data_role(port);
-	}
-}
-
-#ifdef CONFIG_USBC_VCONN_SWAP
-void pd_request_vconn_swap_off(int port)
-{
-	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_request_vconn_swap_on(int port)
-{
-	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
-		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
-		task_wake(PD_PORT_TO_TASK_ID(port));
-	}
-}
-
-void pd_request_vconn_swap(int port)
-{
-	pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
-}
-#endif
-
-int tc_is_vconn_src(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_VCONN))
-		return TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON);
-	else
-		return 0;
-}
-
-static __maybe_unused int reset_device_and_notify(int port)
-{
-	int rv;
-	int task, waiting_tasks;
-
-	/* This should only be called from the PD task */
-	assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-	TC_SET_FLAG(port, TC_FLAGS_LPM_TRANSITION);
-	rv = tcpm_init(port);
-	TC_CLR_FLAG(port, TC_FLAGS_LPM_TRANSITION);
-	TC_CLR_FLAG(port, TC_FLAGS_LPM_ENGAGED);
-	tc_start_event_loop(port);
-
-	CPRINTS("C%d: TCPC init %s", port, rv ? "failed!" : "ready");
-
-	/*
-	 * Before getting the other tasks that are waiting, clear the reset
-	 * event from this PD task to prevent multiple reset/init events
-	 * occurring.
-	 *
-	 * The double reset event happens when the higher priority PD interrupt
-	 * task gets an interrupt during the above tcpm_init function. When that
-	 * occurs, the higher priority task waits correctly for us to finish
-	 * waking the TCPC, but it has also set PD_EVENT_TCPC_RESET again, which
-	 * would result in a second, unnecessary init.
-	 */
-	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-			  PD_EVENT_TCPC_RESET);
-
-	waiting_tasks = atomic_clear(&tc[port].tasks_waiting_on_reset);
-
-	/* Wake up all waiting tasks. */
-	while (waiting_tasks) {
-		task = __fls(waiting_tasks);
-		waiting_tasks &= ~BIT(task);
-		task_set_event(task, TASK_EVENT_PD_AWAKE);
-	}
-
-	return rv;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-void pd_wait_exit_low_power(int port)
-{
-	if (!TC_CHK_FLAG(port, TC_FLAGS_LPM_ENGAGED))
-		return;
-
-	if (port == TASK_ID_TO_PD_PORT(task_get_current())) {
-		if (!TC_CHK_FLAG(port, TC_FLAGS_LPM_TRANSITION))
-			reset_device_and_notify(port);
-	} else {
-		/* Otherwise, we need to wait for the TCPC reset to complete */
-		atomic_or(&tc[port].tasks_waiting_on_reset,
-			  1 << task_get_current());
-		/*
-		 * NOTE: We could be sending the PD task the reset event while
-		 * it is already processing the reset event. If that occurs,
-		 * then we will reset the TCPC multiple times, which is
-		 * undesirable but most likely benign. Empirically, this doesn't
-		 * happen much, but it if starts occurring, we can add a guard
-		 * to prevent/reduce it.
-		 */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
-		task_wait_event_mask(TASK_EVENT_PD_AWAKE, -1);
-	}
-}
-
-/*
- * This can be called from any task. If we are in the PD task, we can handle
- * immediately. Otherwise, we need to notify the PD task via event.
- */
-void pd_device_accessed(int port)
-{
-	if (port == TASK_ID_TO_PD_PORT(task_get_current()))
-		handle_device_access(port);
-	else
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_DEVICE_ACCESSED);
-}
-
-/*
- * TODO(b/137493121): Move this function to a separate file that's shared
- * between the this and the original stack.
- */
-void pd_prevent_low_power_mode(int port, int prevent)
-{
-	const int current_task_mask = (1 << task_get_current());
-
-	if (prevent)
-		atomic_or(&tc[port].tasks_preventing_lpm, current_task_mask);
-	else
-		atomic_clear_bits(&tc[port].tasks_preventing_lpm,
-				  current_task_mask);
-}
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-static void sink_power_sub_states(int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2, cc;
-	enum tcpc_cc_voltage_status new_cc_voltage;
-
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	cc = polarity_rm_dts(tc[port].polarity) ? cc2 : cc1;
-
-	if (cc == TYPEC_CC_VOLT_RP_DEF)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_DEF;
-	else if (cc == TYPEC_CC_VOLT_RP_1_5)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_1_5;
-	else if (cc == TYPEC_CC_VOLT_RP_3_0)
-		new_cc_voltage = TYPEC_CC_VOLT_RP_3_0;
-	else
-		new_cc_voltage = TYPEC_CC_VOLT_OPEN;
-
-	/* Debounce the cc state */
-	if (new_cc_voltage != tc[port].cc_voltage) {
-		tc[port].cc_voltage = new_cc_voltage;
-		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE,
-				PD_T_RP_VALUE_CHANGE);
-		return;
-	}
-
-	if (!pd_timer_is_disabled(port, TC_TIMER_CC_DEBOUNCE)) {
-		if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
-			return;
-
-		pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-
-		if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-			tc[port].typec_curr = usb_get_typec_current_limit(
-				tc[port].polarity, cc1, cc2);
-
-			typec_set_input_current_limit(port,
-				tc[port].typec_curr, TYPE_C_VOLTAGE);
-			charge_manager_update_dualrole(port, CAP_DEDICATED);
-		}
-	}
-}
-
-
-/*
- * TYPE-C State Implementations
- */
-
-/**
- * Disabled
- *
- * Super State Entry Actions:
- *   Remove the terminations from CC
- *   Set VBUS and VCONN off
- */
-static void tc_disabled_entry(const int port)
-{
-	print_current_state(port);
-	/*
-	 * We have completed tc_cc_open_entry (our super state), so set flag
-	 * to indicate to pd_is_port_enabled that we are now suspended.
-	 */
-	TC_SET_FLAG(port, TC_FLAGS_SUSPENDED);
-}
-
-static void tc_disabled_run(const int port)
-{
-	/* If pd_set_suspend clears the request, go to TC_UNATTACHED_SNK/SRC. */
-	if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
-		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
-			     TC_UNATTACHED_SRC : TC_UNATTACHED_SNK);
-	} else {
-		if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) {
-			if (TC_CHK_FLAG(port,
-				TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) {
-				TC_CLR_FLAG(port,
-				TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
-				usb_retimer_fw_update_process_op_cb(port);
-			}
-		}
-		tc_pause_event_loop(port);
-	}
-}
-
-static void tc_disabled_exit(const int port)
-{
-	int rv;
-
-	tc_start_event_loop(port);
-	TC_CLR_FLAG(port, TC_FLAGS_SUSPENDED);
-
-	rv = tcpm_init(port);
-	CPRINTS("C%d: TCPC init %s", port, rv ? "failed!" : "ready");
-}
-
-/**
- * ErrorRecovery
- *
- * Super State Entry Actions:
- *   Remove the terminations from CC
- *   Set's VBUS and VCONN off
- */
-static void tc_error_recovery_entry(const int port)
-{
-	print_current_state(port);
-
-	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_ERROR_RECOVERY);
-
-	TC_CLR_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY);
-}
-
-static void tc_error_recovery_run(const int port)
-{
-	enum usb_tc_state start_state;
-
-	if (!pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
-		return;
-
-	/*
-	 * If we transitioned to error recovery as the first state and we
-	 * didn't brown out, we don't need to reinitialized the tc statemachine
-	 * because we just did that. So transition to the state directly.
-	 */
-	if (tc[port].ctx.previous == NULL) {
-		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
-			     TC_UNATTACHED_SRC : TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 * If try src support is active (e.g. in S0). Then try to become the
-	 * SRC, otherwise we should try to be the sink.
-	 */
-	start_state = TC_UNATTACHED_SNK;
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-		if (is_try_src_enabled(port) ||
-		    drp_state[port] == PD_DRP_FORCE_SOURCE)
-			start_state = TC_UNATTACHED_SRC;
-
-	restart_tc_sm(port, start_state);
-}
-
-static void tc_error_recovery_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-}
-
-/**
- * Unattached.SNK
- */
-static void tc_unattached_snk_entry(const int port)
-{
-	enum pd_data_role prev_data_role;
-
-	if (get_last_state_tc(port) != TC_UNATTACHED_SRC) {
-		tc_detached(port);
-		print_current_state(port);
-	}
-
-	/*
-	 * We are in an unattached state and considering to be a SNK
-	 * searching for a SRC partner.  We set the CC pull value to
-	 * to indicate our intent to be SNK in hopes a partner SRC
-	 * will is there to attach to.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rd.
-	 *
-	 * Restore default current limit Rp in case we swap to source
-	 *
-	 * Run any debug detaches needed before setting CC, as some TCPCs may
-	 * require we set CC Open before changing power roles with a debug
-	 * accessory.
-	 */
-	tcpm_debug_detach(port);
-	typec_select_pull(port, TYPEC_CC_RD);
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
-	typec_update_cc(port);
-
-
-	prev_data_role = tc[port].data_role;
-	tc[port].data_role = PD_ROLE_DISCONNECTED;
-	/*
-	 * When data role set events are used to enable BC1.2, then CC
-	 * detach events are used to notify BC1.2 that it can be powered
-	 * down.
-	 */
-	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		charge_manager_update_dualrole(port, CAP_UNKNOWN);
-
-	tc_set_partner_role(port, PPC_DEV_DISCONNECTED);
-
-	/*
-	 * Indicate that the port is disconnected so the board
-	 * can restore state from any previous data swap.
-	 */
-	pd_execute_data_swap(port, PD_ROLE_DISCONNECTED);
-	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SNK);
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_FLAGS_ON_DISCONNECT(port);
-		tc_enable_pd(port, 0);
-	}
-}
-
-static void tc_unattached_snk_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	/*
-	 * TODO(b/137498392): Add wait before sampling the CC
-	 * status after role changes
-	 */
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-			TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-			tc_set_data_role(port, PD_ROLE_UFP);
-			/* Inform Policy Engine that hard reset is complete */
-			pe_ps_reset_complete(port);
-		}
-	}
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	/*
-	 * The port shall transition to AttachWait.SNK when a Source
-	 * connection is detected, as indicated by the SNK.Rp state
-	 * on at least one of its CC pins.
-	 *
-	 * A DRP shall transition to Unattached.SRC within tDRPTransition
-	 * after the state of both CC pins is SNK.Open for
-	 * tDRP − dcSRC.DRP ∙ tDRP.
-	 */
-	if (cc_is_rp(cc1) || cc_is_rp(cc2)) {
-		/* Connection Detected */
-		set_state_tc(port, TC_ATTACH_WAIT_SNK);
-		return;
-	}
-
-	/*
-	 * Debounce the CC open status. Some TCPC needs time to get the CC
-	 * status valid. Before that, CC open is reported by default. Wait
-	 * to make sure the CC is really open. Reuse the role toggle timer.
-	 */
-	if (!pd_timer_is_expired(port, TC_TIMER_NEXT_ROLE_SWAP))
-		return;
-
-	/*
-	 * Initialize type-C supplier current limits to 0. The charge
-	 * manage is now seeded if it was not.
-	 */
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		typec_set_input_current_limit(port, 0, 0);
-
-	/*
-	 * Attempt TCPC auto DRP toggle if it is
-	 * not already auto toggling.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) &&
-	    drp_state[port] == PD_DRP_TOGGLE_ON &&
-	    tcpm_auto_toggle_supported(port)) {
-		set_state_tc(port, TC_DRP_AUTO_TOGGLE);
-	} else if (drp_state[port] == PD_DRP_TOGGLE_ON) {
-		/* DRP Toggle. The timer was checked above. */
-		set_state_tc(port, TC_UNATTACHED_SRC);
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
-		   (drp_state[port] == PD_DRP_FORCE_SINK ||
-		    drp_state[port] == PD_DRP_TOGGLE_OFF)) {
-		set_state_tc(port, TC_LOW_POWER_MODE);
-	}
-}
-
-static void tc_unattached_snk_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_NEXT_ROLE_SWAP);
-}
-
-/**
- * AttachWait.SNK
- *
- * Super State Entry Actions:
- *   Vconn Off
- *   Place Rd on CC
- *   Set power role to SINK
- */
-static void tc_attach_wait_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_attach_wait_snk_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-	enum pd_cc_states new_cc_state;
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	if (cc_is_rp(cc1) && cc_is_rp(cc2) && board_is_dts_port(port))
-		new_cc_state = PD_CC_DFP_DEBUG_ACC;
-	else if (cc_is_rp(cc1) || cc_is_rp(cc2))
-		new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		new_cc_state = PD_CC_NONE;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
-		pd_timer_enable(port, TC_TIMER_PD_DEBOUNCE, PD_T_PD_DEBOUNCE);
-		tc[port].cc_state = new_cc_state;
-		return;
-	}
-
-	/*
-	 * A DRP shall transition to Unattached.SRC when the state of both
-	 * the CC1 and CC2 pins is SNK.Open for at least tPDDebounce, however
-	 * when DRP state prevents switch to SRC the next state should be
-	 * Unattached.SNK.
-	 */
-	if (new_cc_state == PD_CC_NONE &&
-	    pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) {
-		/* We are detached */
-		if (drp_state[port] == PD_DRP_TOGGLE_OFF
-		    || drp_state[port] == PD_DRP_FREEZE
-		    || drp_state[port] == PD_DRP_FORCE_SINK)
-			set_state_tc(port, TC_UNATTACHED_SNK);
-		else
-			set_state_tc(port, TC_UNATTACHED_SRC);
-		return;
-	}
-
-	/* Wait for CC debounce */
-	if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
-		return;
-
-	/*
-	 * The port shall transition to Attached.SNK after the state of only
-	 * one of the CC1 or CC2 pins is SNK.Rp for at least tCCDebounce and
-	 * VBUS is detected.
-	 *
-	 * A DRP that strongly prefers the Source role may optionally
-	 * transition to Try.SRC instead of Attached.SNK when the state of only
-	 * one CC pin has been SNK.Rp for at least tCCDebounce and VBUS is
-	 * detected.
-	 *
-	 * If the port supports Debug Accessory Mode, the port shall transition
-	 * to DebugAccessory.SNK if the state of both the CC1 and CC2 pins is
-	 * SNK.Rp for at least tCCDebounce and VBUS is detected.
-	 */
-	if (pd_is_vbus_present(port)) {
-		if (new_cc_state == PD_CC_DFP_ATTACHED) {
-			if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
-			    is_try_src_enabled(port))
-				set_state_tc(port, TC_TRY_SRC);
-			else
-				set_state_tc(port, TC_ATTACHED_SNK);
-		} else {
-			/* new_cc_state is PD_CC_DFP_DEBUG_ACC */
-			CPRINTS("C%d: Debug accessory detected", port);
-			TC_SET_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
-			set_state_tc(port, TC_ATTACHED_SNK);
-		}
-
-		if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-				IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
-			hook_call_deferred(&pd_usb_billboard_deferred_data,
-								PD_T_AME);
-		}
-	}
-}
-
-static void tc_attach_wait_snk_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_PD_DEBOUNCE);
-}
-
-/**
- * Attached.SNK, shared with Debug Accessory.SNK
- */
-static void tc_attached_snk_entry(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	print_current_state(port);
-
-	/*
-	 * Known state of attach is SNK.  We need to apply this pull value
-	 * to make it set in hardware at the correct time but set the common
-	 * pull here.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rd.
-	 */
-	typec_select_pull(port, TYPEC_CC_RD);
-
-	/* Inform the PPC and OCP module that a source is connected */
-	tc_set_partner_role(port, PPC_DEV_SRC);
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-	    TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
-		/* Flipping power role - Disable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 0);
-
-		/* Apply Rd */
-		typec_update_cc(port);
-
-		/* Change role to sink */
-		tc_set_power_role(port, PD_ROLE_SINK);
-		tcpm_set_msg_header(port, tc[port].power_role,
-							tc[port].data_role);
-
-		/*
-		 * Maintain VCONN supply state, whether ON or OFF, and its
-		 * data role / usb mux connections. Do not re-enable
-		 * AutoDischargeDisconnect until the swap is completed
-		 * and tc_pr_swap_complete is called.
-		 */
-	} else {
-		/* Get connector orientation */
-		tcpm_get_cc(port, &cc1, &cc2);
-		tc[port].polarity = get_snk_polarity(cc1, cc2);
-		pd_set_polarity(port, tc[port].polarity);
-
-		tc_set_data_role(port, PD_ROLE_UFP);
-
-		hook_notify(HOOK_USB_PD_CONNECT);
-
-		if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-			tc[port].typec_curr =
-			usb_get_typec_current_limit(tc[port].polarity,
-								cc1, cc2);
-			typec_set_input_current_limit(port,
-					tc[port].typec_curr, TYPE_C_VOLTAGE);
-			/*
-			 * Start new connections as dedicated until source caps
-			 * are received, at which point the PE will update the
-			 * flag.
-			 */
-			charge_manager_update_dualrole(port, CAP_DEDICATED);
-		}
-
-		/* Apply Rd */
-		typec_update_cc(port);
-
-		/*
-		 * Attached.SNK - enable AutoDischargeDisconnect
-		 * Do this after applying Rd to CC lines to avoid
-		 * TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL (b/171567398)
-		 */
-		tcpm_enable_auto_discharge_disconnect(port, 1);
-	}
-
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-
-	/* Enable PD */
-	if (IS_ENABLED(CONFIG_USB_PE_SM))
-		tc_enable_pd(port, 1);
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
-		tcpm_debug_accessory(port, 1);
-		set_ccd_mode(port, 1);
-	}
-}
-
-/*
- * Check whether Vbus has been removed on this port, accounting for some Vbus
- * debounce if FRS is enabled.
- *
- * Returns true if a new state was set and the calling run should exit.
- */
-static bool tc_snk_check_vbus_removed(const int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
-		/*
-		 * Debounce Vbus presence when FRS is enabled. Note that we may
-		 * lose Vbus before the FRS signal comes in to let us know
-		 * we're PR swapping, but we must still transition to unattached
-		 * within tSinkDisconnect.
-		 *
-		 * We may safely re-use the Vbus debounce timer here
-		 * since a PR swap would no longer be in progress when Vbus
-		 * removal is checked.
-		 */
-		if (pd_check_vbus_level(port, VBUS_REMOVED)) {
-			if (pd_timer_is_disabled(port,
-						 TC_TIMER_VBUS_DEBOUNCE)) {
-				pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE,
-						PD_T_FRS_VBUS_DEBOUNCE);
-			} else if (pd_timer_is_expired(port,
-						TC_TIMER_VBUS_DEBOUNCE)) {
-				set_state_tc(port, TC_UNATTACHED_SNK);
-				return true;
-			}
-		} else {
-			pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
-		}
-	} else if (pd_check_vbus_level(port, VBUS_REMOVED)) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return true;
-	}
-
-	return false;
-}
-
-static void tc_attached_snk_run(const int port)
-{
-#ifdef CONFIG_USB_PE_SM
-	/*
-	 * Perform Hard Reset
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-		/*
-		 * Wait to clear the hard reset request until Vbus has returned
-		 * to default (or, if it didn't return, we transition to
-		 * unattached)
-		 */
-		if (tc_perform_snk_hard_reset(port))
-			TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-
-		return;
-	}
-
-	/*
-	 * From 4.5.2.2.5.2 Exiting from Attached.SNK State:
-	 *
-	 * "A port that is not a Vconn-Powered USB Device and is not in the
-	 * process of a USB PD PR_Swap or a USB PD Hard Reset or a USB PD
-	 * FR_Swap shall transition to Unattached.SNK within tSinkDisconnect
-	 * when Vbus falls below vSinkDisconnect for Vbus operating at or
-	 * below 5 V or below vSinkDisconnectPD when negotiated by USB PD
-	 * to operate above 5 V."
-	 *
-	 * TODO(b/149530538): Use vSinkDisconnectPD when above 5V
-	 */
-
-	/*
-	 * Debounce Vbus before we drop that we are doing a PR_Swap
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS) &&
-	    pd_timer_is_expired(port, TC_TIMER_VBUS_DEBOUNCE)) {
-		/* PR Swap is no longer in progress */
-		TC_CLR_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS);
-		pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
-
-		/*
-		 * AutoDischargeDisconnect was turned off when we
-		 * hit Safe0V on SRC->SNK PR-Swap. We now are done
-		 * with the swap and should have Vbus, so re-enable
-		 * AutoDischargeDisconnect.
-		 */
-		if (!pd_check_vbus_level(port, VBUS_REMOVED))
-			tcpm_enable_auto_discharge_disconnect(port, 1);
-	}
-
-	/*
-	 * The sink will be powered off during a power role swap but we don't
-	 * want to trigger a disconnect.
-	 */
-	if (!TC_CHK_FLAG(port, TC_FLAGS_POWER_OFF_SNK) &&
-	    !TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
-		/*
-		 * Detach detection
-		 */
-		if (tc_snk_check_vbus_removed(port))
-			return;
-
-		if (!pe_is_explicit_contract(port))
-			sink_power_sub_states(port);
-	}
-
-	/*
-	 * PD swap commands
-	 */
-	if (tc_get_pd_enabled(port) && prl_is_running(port)) {
-		/*
-		 * Power Role Swap
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP)) {
-			/*
-			 * We may want to verify partner is applying Rd before
-			 * we swap. However, some TCPCs (such as TUSB422) will
-			 * not report the correct CC status before VBUS falls to
-			 * vSafe0V, so this will be problematic in the FRS case.
-			 */
-			set_state_tc(port, TC_ATTACHED_SRC);
-			return;
-		}
-
-		/*
-		 * Data Role Swap
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_DR_SWAP)) {
-			TC_CLR_FLAG(port, TC_FLAGS_REQUEST_DR_SWAP);
-
-			/* Perform Data Role Swap */
-			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_UFP ?
-					PD_ROLE_DFP : PD_ROLE_UFP);
-		}
-
-		/*
-		 * VCONN Swap
-		 * UnorientedDebugAccessory.SRC shall not drive Vconn
-		 */
-		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
-			if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON)) {
-				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
-
-				set_vconn(port, 1);
-				/*
-				 * Inform policy engine that vconn swap is
-				 * complete
-				 */
-				pe_vconn_swap_complete(port);
-			} else if (TC_CHK_FLAG(port,
-					       TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
-				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
-
-				set_vconn(port, 0);
-				/*
-				 * Inform policy engine that vconn swap is
-				 * complete
-				 */
-				pe_vconn_swap_complete(port);
-			}
-		}
-
-		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
-			/*
-			 * If the port supports Charge-Through VCONN-Powered USB
-			 * devices, and an explicit PD contract has failed to be
-			 * negotiated, the port shall query the identity of the
-			 * cable via USB PD on SOP’
-			 */
-			if (!pe_is_explicit_contract(port) &&
-			    TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
-				/*
-				 * A port that via SOP’ has detected an
-				 * attached Charge-Through VCONN-Powered USB
-				 * device shall transition to Unattached.SRC
-				 * if an explicit PD contract has failed to
-				 * be negotiated.
-				 */
-				/* CTVPD detected */
-				set_state_tc(port, TC_UNATTACHED_SRC);
-			}
-		}
-	}
-
-#else /* CONFIG_USB_PE_SM */
-
-	/* Detach detection */
-	if (tc_snk_check_vbus_removed(port))
-		return;
-
-	/* Run Sink Power Sub-State */
-	sink_power_sub_states(port);
-#endif /* CONFIG_USB_PE_SM */
-}
-
-static void tc_attached_snk_exit(const int port)
-{
-	if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP)) {
-		/*
-		 * If supplying VCONN, the port shall cease to supply
-		 * it within tVCONNOFF of exiting Attached.SNK if not
-		 * PR swapping.
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON))
-			set_vconn(port, 0);
-
-		/*
-		 * Attached.SNK exit - disable AutoDischargeDisconnect
-		 * NOTE: This should not happen if we are suspending. It will
-		 * happen in tc_cc_open_entry if that is the path we are
-		 * taking.
-		 */
-		if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND))
-			tcpm_enable_auto_discharge_disconnect(port, 0);
-	}
-
-	/* Clear flags after checking Vconn status */
-	TC_CLR_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP | TC_FLAGS_POWER_OFF_SNK);
-
-	/* Stop drawing power */
-	sink_stop_drawing_current(port);
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-		tcpm_debug_detach(port);
-
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-	pd_timer_disable(port, TC_TIMER_VBUS_DEBOUNCE);
-}
-
-/**
- * Unattached.SRC
- */
-static void tc_unattached_src_entry(const int port)
-{
-	enum pd_data_role prev_data_role;
-
-	if (get_last_state_tc(port) != TC_UNATTACHED_SNK) {
-		tc_detached(port);
-		print_current_state(port);
-	}
-
-	/*
-	 * We are in an unattached state and considering to be a SRC
-	 * searching for a SNK partner.  We set the CC pull value to
-	 * to indicate our intent to be SRC in hopes a partner SNK
-	 * will is there to attach to.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rp.
-	 *
-	 * Restore default current limit Rp.
-	 *
-	 * Run any debug detaches needed before setting CC, as some TCPCs may
-	 * require we set CC Open before changing power roles with a debug
-	 * accessory.
-	 */
-	tcpm_debug_detach(port);
-	typec_select_pull(port, TYPEC_CC_RP);
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
-	typec_update_cc(port);
-
-	prev_data_role = tc[port].data_role;
-	tc[port].data_role = PD_ROLE_DISCONNECTED;
-
-	/*
-	 * When data role set events are used to enable BC1.2, then CC
-	 * detach events are used to notify BC1.2 that it can be powered
-	 * down.
-	 */
-	bc12_role_change_handler(port, prev_data_role, tc[port].data_role);
-
-	tc_set_partner_role(port, PPC_DEV_DISCONNECTED);
-
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		charge_manager_update_dualrole(port, CAP_UNKNOWN);
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_FLAGS_ON_DISCONNECT(port);
-		tc_enable_pd(port, 0);
-	}
-
-	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SRC);
-}
-
-static void tc_unattached_src_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-			TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-			tc_set_data_role(port, PD_ROLE_DFP);
-			/* Inform Policy Engine that hard reset is complete */
-			pe_ps_reset_complete(port);
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_USBC_OCP)) {
-		/*
-		 * If the port is latched off, just continue to
-		 * monitor for a detach.
-		 */
-		if (usbc_ocp_is_port_latched_off(port))
-			return;
-	}
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	/*
-	 * Transition to AttachWait.SRC when:
-	 *   1) The SRC.Rd state is detected on either CC1 or CC2 pin or
-	 *   2) The SRC.Ra state is detected on both the CC1 and CC2 pins.
-	 *
-	 * A DRP shall transition to Unattached.SNK within tDRPTransition
-	 * after dcSRC.DRP ∙ tDRP
-	 */
-	if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2))
-		set_state_tc(port, TC_ATTACH_WAIT_SRC);
-	else if (pd_timer_is_expired(port, TC_TIMER_NEXT_ROLE_SWAP) &&
-		 drp_state[port] != PD_DRP_FORCE_SOURCE &&
-		 drp_state[port] != PD_DRP_FREEZE)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-	/*
-	 * Attempt TCPC auto DRP toggle
-	 */
-	else if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) &&
-		 drp_state[port] == PD_DRP_TOGGLE_ON &&
-		 tcpm_auto_toggle_supported(port) && cc_is_open(cc1, cc2))
-		set_state_tc(port, TC_DRP_AUTO_TOGGLE);
-	else if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER) &&
-		 (drp_state[port] == PD_DRP_FORCE_SOURCE ||
-		  drp_state[port] == PD_DRP_TOGGLE_OFF))
-		set_state_tc(port, TC_LOW_POWER_MODE);
-}
-
-static void tc_unattached_src_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_NEXT_ROLE_SWAP);
-}
-
-/**
- * AttachWait.SRC
- *
- * Super State Entry Actions:
- *   Vconn Off
- *   Place Rp on CC
- *   Set power role to SOURCE
- */
-static void tc_attach_wait_src_entry(const int port)
-{
-	print_current_state(port);
-
-	tc[port].cc_state = PD_CC_UNSET;
-}
-
-static void tc_attach_wait_src_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-	enum pd_cc_states new_cc_state;
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	if (cc_is_snk_dbg_acc(cc1, cc2) && board_is_dts_port(port)) {
-		/*
-		 * Debug accessory.
-		 * A debug accessory in a non-DTS port will be
-		 * recognized by at_least_one_rd as UFP attached.
-		 */
-		new_cc_state = PD_CC_UFP_DEBUG_ACC;
-	} else if (cc_is_at_least_one_rd(cc1, cc2)) {
-		/* UFP attached */
-		new_cc_state = PD_CC_UFP_ATTACHED;
-	} else if (cc_is_audio_acc(cc1, cc2)) {
-		/* AUDIO Accessory not supported. Just ignore */
-		new_cc_state = PD_CC_UFP_AUDIO_ACC;
-	} else {
-		/* No UFP */
-		if (drp_state[port] == PD_DRP_FORCE_SOURCE)
-			set_state_tc(port, TC_UNATTACHED_SRC);
-		else
-			set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
-		tc[port].cc_state = new_cc_state;
-		return;
-	}
-
-	/* Wait for CC debounce */
-	if (!pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
-		return;
-
-	/*
-	 * The port shall transition to Attached.SRC when VBUS is at vSafe0V
-	 * and the SRC.Rd state is detected on exactly one of the CC1 or CC2
-	 * pins for at least tCCDebounce.
-	 *
-	 * If the port supports Debug Accessory Mode, it shall transition to
-	 * UnorientedDebugAccessory.SRC when VBUS is at vSafe0V and the SRC.Rd
-	 * state is detected on both the CC1 and CC2 pins for at least
-	 * tCCDebounce.
-	 */
-	if (pd_check_vbus_level(port, VBUS_SAFE0V)) {
-		if (new_cc_state == PD_CC_UFP_ATTACHED) {
-			set_state_tc(port, TC_ATTACHED_SRC);
-			return;
-		} else if (new_cc_state == PD_CC_UFP_DEBUG_ACC) {
-			CPRINTS("C%d: Debug accessory detected", port);
-			TC_SET_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
-			set_state_tc(port, TC_ATTACHED_SRC);
-			return;
-		}
-	}
-}
-
-static void tc_attach_wait_src_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-}
-
-/**
- * Attached.SRC, shared with UnorientedDebugAccessory.SRC
- */
-static void tc_attached_src_entry(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	print_current_state(port);
-
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-
-	/*
-	 * Known state of attach is SRC.  We need to apply this pull value
-	 * to make it set in hardware at the correct time but set the common
-	 * pull here.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * pulled up through Rp.
-	 *
-	 * Set selected current limit in the hardware.
-	 */
-	typec_select_pull(port, TYPEC_CC_RP);
-	typec_set_source_current_limit(port, tc[port].select_current_limit_rp);
-
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
-			/* Change role to source */
-			tc_set_power_role(port, PD_ROLE_SOURCE);
-			tcpm_set_msg_header(port,
-					tc[port].power_role,
-					tc[port].data_role);
-
-			/* Enable VBUS */
-			tc_src_power_on(port);
-
-			/* Apply Rp */
-			typec_update_cc(port);
-
-			/*
-			 * Maintain VCONN supply state, whether ON or OFF, and
-			 * its data role / usb mux connections. Do not
-			 * re-enable AutoDischargeDisconnect until the swap is
-			 * completed and tc_pr_swap_complete is called.
-			 */
-		} else {
-			/*
-			 * Set up CC's, Vconn, and ADD before Vbus, as per
-			 * Figure 4-24. DRP Initialization and Connection
-			 * Detection in TCPCI r2 v1.2 specification.
-			 */
-
-			/* Get connector orientation */
-			tcpm_get_cc(port, &cc1, &cc2);
-			tc[port].polarity = get_src_polarity(cc1, cc2);
-			pd_set_polarity(port, tc[port].polarity);
-
-			/* Attached.SRC - enable AutoDischargeDisconnect */
-			tcpm_enable_auto_discharge_disconnect(port, 1);
-
-			/* Apply Rp */
-			typec_update_cc(port);
-
-			/*
-			 * Initial data role for sink is DFP
-			 * This also sets the usb mux
-			 */
-			tc_set_data_role(port, PD_ROLE_DFP);
-
-			/*
-			 * Start sourcing Vconn before Vbus to ensure
-			 * we are within USB Type-C Spec 1.4 tVconnON
-			 *
-			 * UnorientedDebugAccessory.SRC shall not drive Vconn
-			 */
-			if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-				set_vconn(port, 1);
-
-			/* Enable VBUS */
-			if (tc_src_power_on(port)) {
-				/* Stop sourcing Vconn if Vbus failed */
-				if (IS_ENABLED(CONFIG_USBC_VCONN))
-					set_vconn(port, 0);
-
-				if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-					usb_mux_set(port,
-						USB_PD_MUX_NONE,
-						USB_SWITCH_DISCONNECT,
-						tc[port].polarity);
-			}
-
-			tc_enable_pd(port, 0);
-			pd_timer_enable(port, TC_TIMER_TIMEOUT,
-					MAX(PD_POWER_SUPPLY_TURN_ON_DELAY,
-					    PD_T_VCONN_STABLE));
-		}
-	} else {
-		/*
-		 * Set up CC's, Vconn, and ADD before Vbus, as per
-		 * Figure 4-24. DRP Initialization and Connection
-		 * Detection in TCPCI r2 v1.2 specification.
-		 */
-
-		/* Get connector orientation */
-		tcpm_get_cc(port, &cc1, &cc2);
-		tc[port].polarity = get_src_polarity(cc1, cc2);
-		pd_set_polarity(port, tc[port].polarity);
-
-		/* Attached.SRC - enable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 1);
-
-		/* Apply Rp */
-		typec_update_cc(port);
-
-		/*
-		 * Initial data role for sink is DFP
-		 * This also sets the usb mux
-		 */
-		tc_set_data_role(port, PD_ROLE_DFP);
-
-		/*
-		 * Start sourcing Vconn before Vbus to ensure
-		 * we are within USB Type-C Spec 1.4 tVconnON
-		 *
-		 * UnorientedDebugAccessory.SRC shall not drive Vconn
-		 */
-		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-			set_vconn(port, 1);
-
-		/* Enable VBUS */
-		if (tc_src_power_on(port)) {
-			/* Stop sourcing Vconn if Vbus failed */
-			if (IS_ENABLED(CONFIG_USBC_VCONN))
-				set_vconn(port, 0);
-
-			if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-				usb_mux_set(port, USB_PD_MUX_NONE,
-				USB_SWITCH_DISCONNECT, tc[port].polarity);
-		}
-	}
-
-	/* Inform PPC and OCP module that a sink is connected. */
-	tc_set_partner_role(port, PPC_DEV_SNK);
-
-	/* Initialize type-C supplier to seed the charge manger */
-	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
-		typec_set_input_current_limit(port, 0, 0);
-
-	/*
-	 * Only notify if we're not performing a power role swap.  During a
-	 * power role swap, the port partner is not disconnecting/connecting.
-	 */
-	if (!TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
-		hook_notify(HOOK_USB_PD_CONNECT);
-	}
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
-		tcpm_debug_accessory(port, 1);
-		set_ccd_mode(port, 1);
-	}
-
-	/*
-	 * Some TCPCs require time to correctly return CC status after
-	 * changing the ROLE_CONTROL register. Due to that, we have to ignore
-	 * CC_NONE state until PD_T_SRC_DISCONNECT delay has elapsed.
-	 * From the "Universal Serial Bus Type-C Cable and Connector
-	 * Specification" Release 2.0 paragraph 4.5.2.2.9.2:
-	 * The Source shall detect the SRC.Open state within tSRCDisconnect,
-	 * but should detect it as quickly as possible
-	 */
-	pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_SRC_DISCONNECT);
-}
-
-static void tc_attached_src_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	if (polarity_rm_dts(tc[port].polarity))
-		cc1 = cc2;
-
-	if (cc1 == TYPEC_CC_VOLT_OPEN)
-		tc[port].cc_state = PD_CC_NONE;
-	else
-		tc[port].cc_state = PD_CC_UFP_ATTACHED;
-
-	/*
-	 * When the SRC.Open state is detected on the monitored CC pin, a DRP
-	 * shall transition to Unattached.SNK unless it strongly prefers the
-	 * Source role. In that case, it shall transition to TryWait.SNK.
-	 * This transition to TryWait.SNK is needed so that two devices that
-	 * both prefer the Source role do not loop endlessly between Source
-	 * and Sink. In other words, a DRP that would enter Try.SRC from
-	 * AttachWait.SNK shall enter TryWait.SNK for a Sink detach from
-	 * Attached.SRC.
-	 */
-	if (tc[port].cc_state == PD_CC_NONE &&
-	    pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE)) {
-		bool tryWait;
-		enum usb_tc_state new_tc_state = TC_UNATTACHED_SNK;
-
-		if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-			tryWait = is_try_src_enabled(port) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
-
-		if (drp_state[port] == PD_DRP_FORCE_SOURCE)
-			new_tc_state = TC_UNATTACHED_SRC;
-		else if(IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-			new_tc_state = tryWait ?
-				TC_TRY_WAIT_SNK : TC_UNATTACHED_SNK;
-
-		set_state_tc(port, new_tc_state);
-		return;
-	}
-
-#ifdef CONFIG_USB_PE_SM
-	/*
-	 * Enable PD communications after power supply has fully
-	 * turned on
-	 */
-	if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
-		tc_enable_pd(port, 1);
-		pd_timer_disable(port, TC_TIMER_TIMEOUT);
-	}
-
-	if (!tc_get_pd_enabled(port))
-		return;
-
-	/*
-	 * Handle Hard Reset from Policy Engine
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-		/* Ignoring Hard Resets while the power supply is resetting.*/
-		if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT) &&
-		    !pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
-			return;
-
-		if (tc_perform_src_hard_reset(port))
-			TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-
-		return;
-	}
-
-	/*
-	 * PD swap commands
-	 */
-	if (tc_get_pd_enabled(port) && prl_is_running(port)) {
-		/*
-		 * Power Role Swap Request
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP)) {
-			/* Clear TC_FLAGS_REQUEST_PR_SWAP on exit */
-			return set_state_tc(port, TC_ATTACHED_SNK);
-		}
-
-		/*
-		 * Data Role Swap Request
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_DR_SWAP)) {
-			TC_CLR_FLAG(port, TC_FLAGS_REQUEST_DR_SWAP);
-
-			/* Perform Data Role Swap */
-			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_DFP ?
-					PD_ROLE_UFP : PD_ROLE_DFP);
-		}
-
-		/*
-		 * Vconn Swap Request
-		 * UnorientedDebugAccessory.SRC shall not drive Vconn
-		 */
-		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
-			/*
-			 * VCONN Swap Request
-			 */
-			if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON)) {
-				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
-				set_vconn(port, 1);
-				pe_vconn_swap_complete(port);
-			} else if (TC_CHK_FLAG(port,
-						TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
-				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
-				set_vconn(port, 0);
-				pe_vconn_swap_complete(port);
-			}
-		}
-
-		/*
-		 * A DRP that supports Charge-Through VCONN-Powered USB Devices
-		 * shall transition to CTUnattached.SNK if the connected device
-		 * identifies itself as a Charge-Through VCONN-Powered USB
-		 * Device in its Discover Identity Command response.
-		 */
-
-		/*
-		 * A DRP that supports Charge-Through VCONN-Powered USB Devices
-		 * shall transition to CTUnattached.SNK if the connected device
-		 * identifies itself as a Charge-Through VCONN-Powered USB
-		 * Device in its Discover Identity Command response.
-		 *
-		 * If it detects that it is connected to a VCONN-Powered USB
-		 * Device, the port may remove VBUS and discharge it to
-		 * vSafe0V, while continuing to remain in this state with VCONN
-		 * applied.
-		 */
-		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER) &&
-			TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
-
-			set_state_tc(port, TC_CT_UNATTACHED_SNK);
-		}
-	}
-#endif
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_CURRENT)) {
-		TC_CLR_FLAG(port, TC_FLAGS_UPDATE_CURRENT);
-		typec_set_source_current_limit(port,
-					tc[port].select_current_limit_rp);
-		pd_update_contract(port);
-
-		/* Update Rp if no contract is present */
-		if (!IS_ENABLED(CONFIG_USB_PE_SM) ||
-						!pe_is_explicit_contract(port))
-			typec_update_cc(port);
-	}
-}
-
-static void tc_attached_src_exit(const int port)
-{
-	/*
-	 * A port shall cease to supply VBUS within tVBUSOFF of exiting
-	 * Attached.SRC.
-	 */
-	tc_src_power_off(port);
-
-	if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP)) {
-		/* Attached.SRC exit - disable AutoDischargeDisconnect */
-		tcpm_enable_auto_discharge_disconnect(port, 0);
-
-		/*
-		 * Disable VCONN if not power role swapping and
-		 * a CTVPD was not detected
-		 */
-		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED))
-			set_vconn(port, 0);
-	}
-
-	/* Clear CTVPD detected after checking for Vconn */
-	TC_CLR_FLAG(port, TC_FLAGS_CTVPD_DETECTED);
-
-	/* Clear PR swap flag after checking for Vconn */
-	TC_CLR_FLAG(port, TC_FLAGS_REQUEST_PR_SWAP);
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER))
-		tcpm_debug_detach(port);
-
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-}
-
-static __maybe_unused void check_drp_connection(const int port)
-{
-	enum pd_drp_next_states next_state;
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	TC_CLR_FLAG(port, TC_FLAGS_CHECK_CONNECTION);
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	tc[port].drp_sink_time = get_time().val;
-
-	/* Get the next toggle state */
-	next_state = drp_auto_toggle_next_state(&tc[port].drp_sink_time,
-		tc[port].power_role, drp_state[port], cc1, cc2,
-		tcpm_auto_toggle_supported(port));
-
-	if (next_state == DRP_TC_DEFAULT)
-		next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE)
-				? DRP_TC_UNATTACHED_SRC
-				: DRP_TC_UNATTACHED_SNK;
-
-	switch (next_state) {
-	case DRP_TC_UNATTACHED_SNK:
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		break;
-	case DRP_TC_ATTACHED_WAIT_SNK:
-		set_state_tc(port, TC_ATTACH_WAIT_SNK);
-		break;
-	case DRP_TC_UNATTACHED_SRC:
-		set_state_tc(port, TC_UNATTACHED_SRC);
-		break;
-	case DRP_TC_ATTACHED_WAIT_SRC:
-		set_state_tc(port, TC_ATTACH_WAIT_SRC);
-		break;
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	case DRP_TC_DRP_AUTO_TOGGLE:
-		set_state_tc(port, TC_DRP_AUTO_TOGGLE);
-		break;
-#endif
-
-	default:
-		CPRINTS("C%d: Error: DRP next state %d", port, next_state);
-		break;
-	}
-}
-
-/**
- * DrpAutoToggle
- */
-__maybe_unused static void tc_drp_auto_toggle_entry(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE))
-		assert(0);
-
-	print_current_state(port);
-
-	/*
-	 * We need to ensure that we are waiting in the previous Rd or Rp state
-	 * for the minimum of DRP SNK or SRC so the first toggle cause by
-	 * transition into auto toggle doesn't violate spec timing.
-	 */
-	pd_timer_enable(port, TC_TIMER_TIMEOUT,
-			MAX(PD_T_DRP_SNK, PD_T_DRP_SRC));
-}
-
-__maybe_unused static void tc_drp_auto_toggle_run(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE))
-		assert(0);
-
-	/*
-	 * A timer is running, but if a connection comes in while waiting
-	 * then allow that to take higher priority.
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_CHECK_CONNECTION))
-		check_drp_connection(port);
-
-	else if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT)) {
-		if (!pd_timer_is_expired(port, TC_TIMER_TIMEOUT))
-			return;
-
-		pd_timer_disable(port, TC_TIMER_TIMEOUT);
-		tcpm_enable_drp_toggle(port);
-
-		if (IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER)) {
-			set_state_tc(port, TC_LOW_POWER_MODE);
-		}
-	}
-}
-
-__maybe_unused static void tc_drp_auto_toggle_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-}
-
-__maybe_unused static void tc_low_power_mode_entry(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER))
-		assert(0);
-
-	print_current_state(port);
-	pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME, PD_LPM_DEBOUNCE_US);
-}
-
-__maybe_unused static void tc_low_power_mode_run(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC_LOW_POWER))
-		assert(0);
-
-	if (TC_CHK_FLAG(port, TC_FLAGS_CHECK_CONNECTION)) {
-		tc_start_event_loop(port);
-		if (pd_timer_is_disabled(port, TC_TIMER_LOW_POWER_EXIT_TIME)) {
-			pd_timer_enable(port, TC_TIMER_LOW_POWER_EXIT_TIME,
-					PD_LPM_EXIT_DEBOUNCE_US);
-		} else if (pd_timer_is_expired(port,
-					       TC_TIMER_LOW_POWER_EXIT_TIME)) {
-			CPRINTS("C%d: Exit Low Power Mode", port);
-			check_drp_connection(port);
-		}
-		return;
-	}
-
-	if (tc[port].tasks_preventing_lpm)
-		pd_timer_enable(port, TC_TIMER_LOW_POWER_TIME,
-				PD_LPM_DEBOUNCE_US);
-
-	if (pd_timer_is_expired(port, TC_TIMER_LOW_POWER_TIME)) {
-		CPRINTS("C%d: TCPC Enter Low Power Mode", port);
-		TC_SET_FLAG(port, TC_FLAGS_LPM_ENGAGED);
-		TC_SET_FLAG(port, TC_FLAGS_LPM_TRANSITION);
-		tcpm_enter_low_power_mode(port);
-		TC_CLR_FLAG(port, TC_FLAGS_LPM_TRANSITION);
-		tc_pause_event_loop(port);
-
-		pd_timer_disable(port, TC_TIMER_LOW_POWER_EXIT_TIME);
-	}
-}
-
-__maybe_unused static void tc_low_power_mode_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_LOW_POWER_TIME);
-	pd_timer_disable(port, TC_TIMER_LOW_POWER_EXIT_TIME);
-}
-
-/**
- * Try.SRC
- *
- * Super State Entry Actions:
- *   Vconn Off
- *   Place Rp on CC
- *   Set power role to SOURCE
- */
-#ifdef CONFIG_USB_PD_TRY_SRC
-static void tc_try_src_entry(const int port)
-{
-	print_current_state(port);
-
-	tc[port].cc_state = PD_CC_UNSET;
-	pd_timer_enable(port, TC_TIMER_TRY_WAIT_DEBOUNCE, PD_T_DRP_TRY);
-	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_TRY_TIMEOUT);
-
-	/*
-	 * We are a SNK but would prefer to be a SRC.  Set the pull to
-	 * indicate we want to be a SRC and looking for a SNK.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rp.
-	 */
-	typec_select_pull(port, TYPEC_CC_RP);
-
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
-
-	/* Apply Rp */
-	typec_update_cc(port);
-}
-
-static void tc_try_src_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-	enum pd_cc_states new_cc_state;
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 != TYPEC_CC_VOLT_RD) ||
-	     (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD))
-		new_cc_state = PD_CC_UFP_ATTACHED;
-	else
-		new_cc_state = PD_CC_NONE;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_CC_DEBOUNCE);
-	}
-
-	/*
-	 * The port shall transition to Attached.SRC when the SRC.Rd state is
-	 * detected on exactly one of the CC1 or CC2 pins for at least
-	 * tTryCCDebounce.
-	 */
-	if (new_cc_state == PD_CC_UFP_ATTACHED &&
-	    pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE))
-		set_state_tc(port, TC_ATTACHED_SRC);
-
-	/*
-	 * The port shall transition to TryWait.SNK after tDRPTry and the
-	 * SRC.Rd state has not been detected and VBUS is within vSafe0V,
-	 * or after tTryTimeout and the SRC.Rd state has not been detected.
-	 */
-	if (new_cc_state == PD_CC_NONE) {
-		if ((pd_timer_is_expired(port, TC_TIMER_TRY_WAIT_DEBOUNCE) &&
-		     pd_check_vbus_level(port, VBUS_SAFE0V)) ||
-		    pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
-			set_state_tc(port, TC_TRY_WAIT_SNK);
-		}
-	}
-}
-
-static void tc_try_src_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-	pd_timer_disable(port, TC_TIMER_TRY_WAIT_DEBOUNCE);
-}
-
-/**
- * TryWait.SNK
- *
- * Super State Entry Actions:
- *   Vconn Off
- *   Place Rd on CC
- *   Set power role to SINK
- */
-static void tc_try_wait_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	tc_enable_pd(port, 0);
-	tc[port].cc_state = PD_CC_UNSET;
-	pd_timer_enable(port, TC_TIMER_TRY_WAIT_DEBOUNCE, PD_T_CC_DEBOUNCE);
-
-	/*
-	 * We were a SNK, tried to be a SRC and it didn't work out. Try to
-	 * go back to being a SNK.  Set the pull to indicate we want to be
-	 * a SNK and looking for a SRC.
-	 *
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rd.
-	 */
-	typec_select_pull(port, TYPEC_CC_RD);
-
-	/* Apply Rd */
-	typec_update_cc(port);
-}
-
-static void tc_try_wait_snk_run(const int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-	enum pd_cc_states new_cc_state;
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	/* We only care about CCs being open */
-	if (cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN)
-		new_cc_state = PD_CC_NONE;
-	else
-		new_cc_state = PD_CC_UNSET;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		pd_timer_enable(port, TC_TIMER_PD_DEBOUNCE, PD_T_PD_DEBOUNCE);
-	}
-
-	/*
-	 * The port shall transition to Unattached.SNK when the state of both
-	 * of the CC1 and CC2 pins is SNK.Open for at least tPDDebounce.
-	 */
-	if (new_cc_state == PD_CC_NONE &&
-	    pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 * The port shall transition to Attached.SNK after tCCDebounce if or
-	 * when VBUS is detected.
-	 */
-	if (pd_timer_is_expired(port, TC_TIMER_TRY_WAIT_DEBOUNCE) &&
-	    pd_is_vbus_present(port))
-		set_state_tc(port, TC_ATTACHED_SNK);
-}
-
-static void tc_try_wait_snk_exit(const int port)
-{
-	pd_timer_disable(port, TC_TIMER_PD_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_TRY_WAIT_DEBOUNCE);
-}
-#endif
-
-/*
- * CTUnattached.SNK
- */
-__maybe_unused static void tc_ct_unattached_snk_entry(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		assert(0);
-
-	print_current_state(port);
-
-	/*
-	 * Both CC1 and CC2 pins shall be independently terminated to
-	 * ground through Rd.
-	 */
-	typec_select_pull(port, TYPEC_CC_RD);
-	typec_update_cc(port);
-
-	tc[port].cc_state = PD_CC_UNSET;
-
-	/* Set power role to sink */
-	tc_set_power_role(port, PD_ROLE_SINK);
-	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
-
-	/*
-	 * The policy engine is in the disabled state. Disable PD and
-	 * re-enable it
-	 */
-	tc_enable_pd(port, 0);
-
-	pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_POWER_SUPPLY_TURN_ON_DELAY);
-}
-
-__maybe_unused static void tc_ct_unattached_snk_run(int port)
-{
-	enum tcpc_cc_voltage_status cc1;
-	enum tcpc_cc_voltage_status cc2;
-	enum pd_cc_states new_cc_state;
-
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		assert(0);
-
-	if (!pd_timer_is_disabled(port, TC_TIMER_TIMEOUT)) {
-		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
-			tc_enable_pd(port, 1);
-			pd_timer_disable(port, TC_TIMER_TIMEOUT);
-		} else {
-			return;
-		}
-	}
-
-	/* Wait until Protocol Layer is ready */
-	if (!prl_is_running(port))
-		return;
-
-	/*
-	 * Hard Reset is sent when the PE layer is disabled due to a
-	 * CTVPD connection.
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-		TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-		/* Nothing to do. Just signal hard reset completion */
-		pe_ps_reset_complete(port);
-	}
-
-	/* Check for connection */
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	/* We only care about CCs being open */
-	if (cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN)
-		new_cc_state = PD_CC_NONE;
-	else
-		new_cc_state = PD_CC_UNSET;
-
-	/* Debounce the cc state */
-	if (new_cc_state != tc[port].cc_state) {
-		tc[port].cc_state = new_cc_state;
-		pd_timer_enable(port, TC_TIMER_CC_DEBOUNCE, PD_T_VPDDETACH);
-	}
-
-	/*
-	 * The port shall transition to Unattached.SNK if the state of
-	 * the CC pin is SNK.Open for tVPDDetach after VBUS is vSafe0V.
-	 */
-	else if (pd_timer_is_expired(port, TC_TIMER_CC_DEBOUNCE)) {
-		if (new_cc_state == PD_CC_NONE &&
-		    pd_check_vbus_level(port, VBUS_SAFE0V)) {
-			set_state_tc(port, TC_UNATTACHED_SNK);
-			return;
-		}
-	}
-
-	/*
-	 * The port shall transition to CTAttached.SNK when VBUS is detected.
-	 */
-	if (pd_is_vbus_present(port))
-		set_state_tc(port, TC_CT_ATTACHED_SNK);
-}
-
-__maybe_unused static void tc_ct_unattached_snk_exit(int port)
-{
-	pd_timer_disable(port, TC_TIMER_CC_DEBOUNCE);
-	pd_timer_disable(port, TC_TIMER_TIMEOUT);
-}
-
-/**
- * CTAttached.SNK
- */
-__maybe_unused static void tc_ct_attached_snk_entry(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		assert(0);
-
-	print_current_state(port);
-
-	/* The port shall reject a VCONN swap request. */
-	TC_SET_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP);
-}
-
-__maybe_unused static void tc_ct_attached_snk_run(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		assert(0);
-
-	/*
-	 * Hard Reset is sent when the PE layer is disabled due to a
-	 * CTVPD connection.
-	 */
-	if (TC_CHK_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED)) {
-		TC_CLR_FLAG(port, TC_FLAGS_HARD_RESET_REQUESTED);
-		/* Nothing to do. Just signal hard reset completion */
-		pe_ps_reset_complete(port);
-	}
-
-	/*
-	 * A port that is not in the process of a USB PD Hard Reset shall
-	 * transition to CTUnattached.SNK within tSinkDisconnect when VBUS
-	 * falls below vSinkDisconnect
-	 */
-	if (pd_check_vbus_level(port, VBUS_REMOVED)) {
-		set_state_tc(port, TC_CT_UNATTACHED_SNK);
-		return;
-	}
-
-	/*
-	 *  The port shall operate in one of the Sink Power Sub-States
-	 *  and remain within the Sink Power Sub-States, until either VBUS is
-	 *  removed or a USB PD contract is established with the source.
-	 */
-	if (!pe_is_explicit_contract(port))
-		sink_power_sub_states(port);
-}
-
-__maybe_unused static void tc_ct_attached_snk_exit(int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		assert(0);
-
-	/* Stop drawing power */
-	sink_stop_drawing_current(port);
-
-	TC_CLR_FLAG(port, TC_FLAGS_REJECT_VCONN_SWAP);
-}
-
-/**
- * Super State CC_RD
- */
-static void tc_cc_rd_entry(const int port)
-{
-	/* Disable VCONN */
-	if (IS_ENABLED(CONFIG_USBC_VCONN))
-		set_vconn(port, 0);
-
-	/* Set power role to sink */
-	tc_set_power_role(port, PD_ROLE_SINK);
-	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
-}
-
-
-/**
- * Super State CC_RP
- */
-static void tc_cc_rp_entry(const int port)
-{
-	/* Disable VCONN */
-	if (IS_ENABLED(CONFIG_USBC_VCONN))
-		set_vconn(port, 0);
-
-	/* Set power role to source */
-	tc_set_power_role(port, PD_ROLE_SOURCE);
-	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
-}
-
-/**
- * Super State CC_OPEN
- */
-static void tc_cc_open_entry(const int port)
-{
-	/* Ensure we are not sourcing Vbus */
-	tc_src_power_off(port);
-
-	/* Disable VCONN */
-	set_vconn(port, 0);
-
-	/*
-	 * Ensure we disable discharging before setting CC lines to open.
-	 * If we were sourcing above, then we already drained Vbus. If partner
-	 * is sourcing Vbus they will drain Vbus if they are PD-capable. This
-	 * should only be done if a battery is present as a batteryless
-	 * device will brown out when AutoDischargeDisconnect is disabled and
-	 * we do not want this to happen until the set_cc open/open to make
-	 * sure the TCPC has managed its internal states for disconnecting
-	 * the only source of power it has.
-	 */
-	if (battery_is_present())
-		tcpm_enable_auto_discharge_disconnect(port, 0);
-
-	/*
-	 * We may brown out after applying CC open, so flush console first.
-	 * Console flush can take a long time, so if we aren't in danger of
-	 * browning out, don't do it so we can meet certain compliance timing
-	 * requirements.
-	 */
-	CPRINTS("C%d: Applying CC Open!", port);
-	if (!battery_is_present())
-		cflush();
-
-	/* Remove terminations from CC */
-	typec_select_pull(port, TYPEC_CC_OPEN);
-	typec_update_cc(port);
-
-	tc_set_partner_role(port, PPC_DEV_DISCONNECTED);
-	tc_detached(port);
-}
-
-void tc_set_debug_level(enum debug_level debug_level)
-{
-#ifndef CONFIG_USB_PD_DEBUG_LEVEL
-	tc_debug_level = debug_level;
-#endif
-}
-
-void tc_usb_firmware_fw_update_limited_run(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void tc_usb_firmware_fw_update_run(int port)
-{
-	TC_SET_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-}
-
-void tc_run(const int port)
-{
-	/*
-	 * If pd_set_suspend set TC_FLAGS_REQUEST_SUSPEND, go directly to
-	 * TC_DISABLED.
-	 */
-	if (get_state_tc(port) != TC_DISABLED
-	    && TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
-		/* Invalidate a contract, if there is one */
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			pe_invalidate_explicit_contract(port);
-
-		set_state_tc(port, TC_DISABLED);
-	}
-
-	/* If error recovery has been requested, transition now */
-	if (TC_CHK_FLAG(port, TC_FLAGS_REQUEST_ERROR_RECOVERY)) {
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			pe_invalidate_explicit_contract(port);
-		set_state_tc(port, TC_ERROR_RECOVERY);
-	}
-
-	if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) {
-		if (TC_CHK_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN)) {
-			TC_CLR_FLAG(port, TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN);
-			usb_retimer_fw_update_process_op_cb(port);
-		}
-	}
-
-	run_state(port, &tc[port].ctx);
-}
-
-static void pd_chipset_resume(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if(IS_ENABLED(CONFIG_USB_PE_SM))
-			pd_resume_check_pr_swap_needed(i);
-
-		pd_set_dual_role_and_event(i,
-					   PD_DRP_TOGGLE_ON,
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
-	}
-
-	CPRINTS("PD:S3->S0");
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, pd_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_suspend(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
-	}
-
-	CPRINTS("PD:S0->S3");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, pd_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_reset(void)
-{
-	int i;
-
-	if (!IS_ENABLED(CONFIG_USB_PE_SM))
-		return;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		enum tcpci_msg_type tx;
-
-		/* Do not notify the AP of irrelevant past Hard Resets. */
-		pd_clear_events(i, PD_STATUS_EVENT_HARD_RESET);
-
-		/*
-		 * Re-set events for SOP and SOP' discovery complete so the
-		 * kernel knows to consume discovery information for them.
-		 */
-		for (tx = TCPCI_MSG_SOP; tx <= TCPCI_MSG_SOP_PRIME; tx++) {
-			if (pd_get_identity_discovery(i, tx) != PD_DISC_NEEDED
-			    && pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED
-			    && pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED)
-				pd_notify_event(i, tx == TCPCI_MSG_SOP ?
-					PD_STATUS_EVENT_SOP_DISC_DONE :
-					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-		}
-
-		/* Exit mode so AP can enter mode again after reset */
-		if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY))
-			dpm_set_mode_exit_request(i);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, pd_chipset_reset, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_startup(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
-		/*
-		 * Request port discovery to restore any
-		 * alt modes.
-		 * TODO(b/158042116): Do not start port discovery if there
-		 * is an existing connection.
-		 */
-		if (IS_ENABLED(CONFIG_USB_PE_SM))
-			pd_dpm_request(i, DPM_REQUEST_PORT_DISCOVERY);
-	}
-
-	CPRINTS("PD:S5->S3");
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pd_chipset_startup, HOOK_PRIO_DEFAULT);
-
-static void pd_chipset_shutdown(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
-		pd_set_dual_role_and_event(i,
-					   PD_DRP_FORCE_SINK,
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
-	}
-
-	CPRINTS("PD:S3->S5");
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pd_chipset_shutdown, HOOK_PRIO_DEFAULT);
-
-static void pd_set_power_change(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		task_set_event(PD_PORT_TO_TASK_ID(i),
-			       PD_EVENT_POWER_STATE_CHANGE);
-	}
-}
-DECLARE_DEFERRED(pd_set_power_change);
-
-static void pd_chipset_hard_off(void)
-{
-	/*
-	 * Wait 1 second to check our Vconn sourcing status, as the power rails
-	 * which were supporting it may take some time to change after entering
-	 * G3.
-	 */
-	hook_call_deferred(&pd_set_power_change_data, 1 * SECOND);
-}
-DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, pd_chipset_hard_off, HOOK_PRIO_DEFAULT);
-
-/*
- * Type-C State Hierarchy (Sub-States are listed inside the boxes)
- *
- * |TC_CC_RD --------------|	|TC_CC_RP ------------------------|
- * |			   |	|				  |
- * |	TC_UNATTACHED_SNK  |	|	TC_UNATTACHED_SRC         |
- * |	TC_ATTACH_WAIT_SNK |	|	TC_ATTACH_WAIT_SRC        |
- * |	TC_TRY_WAIT_SNK    |	|	TC_TRY_SRC                |
- * |-----------------------|	|---------------------------------|
- *
- * |TC_CC_OPEN -----------|
- * |                      |
- * |	TC_DISABLED       |
- * |	TC_ERROR_RECOVERY |
- * |----------------------|
- *
- * TC_ATTACHED_SNK    TC_ATTACHED_SRC    TC_DRP_AUTO_TOGGLE    TC_LOW_POWER_MODE
- *
- */
-static __const_data const struct usb_state tc_states[] = {
-	/* Super States */
-	[TC_CC_OPEN] = {
-		.entry	= tc_cc_open_entry,
-	},
-	[TC_CC_RD] = {
-		.entry	= tc_cc_rd_entry,
-	},
-	[TC_CC_RP] = {
-		.entry	= tc_cc_rp_entry,
-	},
-	/* Normal States */
-	[TC_DISABLED] = {
-		.entry	= tc_disabled_entry,
-		.run	= tc_disabled_run,
-		.exit	= tc_disabled_exit,
-		.parent = &tc_states[TC_CC_OPEN],
-	},
-	[TC_ERROR_RECOVERY] = {
-		.entry	= tc_error_recovery_entry,
-		.run	= tc_error_recovery_run,
-		.exit   = tc_error_recovery_exit,
-		.parent = &tc_states[TC_CC_OPEN],
-	},
-	[TC_UNATTACHED_SNK] = {
-		.entry	= tc_unattached_snk_entry,
-		.run	= tc_unattached_snk_run,
-		.exit	= tc_unattached_snk_exit,
-		.parent = &tc_states[TC_CC_RD],
-	},
-	[TC_ATTACH_WAIT_SNK] = {
-		.entry	= tc_attach_wait_snk_entry,
-		.run	= tc_attach_wait_snk_run,
-		.exit	= tc_attach_wait_snk_exit,
-		.parent = &tc_states[TC_CC_RD],
-	},
-	[TC_ATTACHED_SNK] = {
-		.entry	= tc_attached_snk_entry,
-		.run	= tc_attached_snk_run,
-		.exit	= tc_attached_snk_exit,
-	},
-	[TC_UNATTACHED_SRC] = {
-		.entry	= tc_unattached_src_entry,
-		.run	= tc_unattached_src_run,
-		.exit	= tc_unattached_src_exit,
-		.parent = &tc_states[TC_CC_RP],
-	},
-	[TC_ATTACH_WAIT_SRC] = {
-		.entry	= tc_attach_wait_src_entry,
-		.run	= tc_attach_wait_src_run,
-		.exit	= tc_attach_wait_src_exit,
-		.parent = &tc_states[TC_CC_RP],
-	},
-	[TC_ATTACHED_SRC] = {
-		.entry	= tc_attached_src_entry,
-		.run	= tc_attached_src_run,
-		.exit	= tc_attached_src_exit,
-	},
-#ifdef CONFIG_USB_PD_TRY_SRC
-	[TC_TRY_SRC] = {
-		.entry	= tc_try_src_entry,
-		.run	= tc_try_src_run,
-		.exit	= tc_try_src_exit,
-		.parent = &tc_states[TC_CC_RP],
-	},
-	[TC_TRY_WAIT_SNK] = {
-		.entry	= tc_try_wait_snk_entry,
-		.run	= tc_try_wait_snk_run,
-		.exit	= tc_try_wait_snk_exit,
-		.parent = &tc_states[TC_CC_RD],
-	},
-#endif /* CONFIG_USB_PD_TRY_SRC */
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	[TC_DRP_AUTO_TOGGLE] = {
-		.entry = tc_drp_auto_toggle_entry,
-		.run   = tc_drp_auto_toggle_run,
-		.exit  = tc_drp_auto_toggle_exit,
-	},
-#endif /* CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE */
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	[TC_LOW_POWER_MODE] = {
-		.entry = tc_low_power_mode_entry,
-		.run   = tc_low_power_mode_run,
-		.exit  = tc_low_power_mode_exit,
-	},
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-#ifdef CONFIG_USB_PE_SM
-	[TC_CT_UNATTACHED_SNK] = {
-		.entry = tc_ct_unattached_snk_entry,
-		.run   = tc_ct_unattached_snk_run,
-		.exit  = tc_ct_unattached_snk_exit,
-	},
-	[TC_CT_ATTACHED_SNK] = {
-		.entry = tc_ct_attached_snk_entry,
-		.run   = tc_ct_attached_snk_run,
-		.exit  = tc_ct_attached_snk_exit,
-	},
-#endif
-};
-
-#if defined(TEST_BUILD) && defined(USB_PD_DEBUG_LABELS)
-const struct test_sm_data test_tc_sm_data[] = {
-	{
-		.base = tc_states,
-		.size = ARRAY_SIZE(tc_states),
-		.names = tc_state_names,
-		.names_size = ARRAY_SIZE(tc_state_names),
-	},
-};
-const int test_tc_sm_data_size = ARRAY_SIZE(test_tc_sm_data);
-#endif
diff --git a/common/usbc/usb_tc_vpd_sm.c b/common/usbc/usb_tc_vpd_sm.c
deleted file mode 100644
index f230d15003..0000000000
--- a/common/usbc/usb_tc_vpd_sm.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-#include "usb_tc_sm.h"
-#include "usb_sm.h"
-#include "vpd_api.h"
-
-/* USB Type-C VCONN Powered Device module */
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#else /* CONFIG_COMMON_RUNTIME */
-#define CPRINTF(format, args...)
-#define CPRINTS(format, args...)
-#endif
-
-/* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
-
-/**
- * This is the Type-C Port object that contains information needed to
- * implement a VCONN Powered Device.
- */
-static struct type_c {
-	/* state machine context */
-	struct sm_ctx ctx;
-	/* Higher-level power deliver state machines are enabled if true. */
-	uint8_t pd_enable;
-	/* port flags, see TC_FLAGS_* */
-	uint32_t flags;
-	/* Time a port shall wait before it can determine it is attached */
-	uint64_t cc_debounce;
-	/* VPD host port cc state */
-	enum pd_cc_states host_cc_state;
-	uint8_t ct_cc;
-} tc[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* List of all TypeC-level states */
-enum usb_tc_state {
-	/* Normal States */
-	TC_DISABLED,
-	TC_UNATTACHED_SNK,
-	TC_ATTACH_WAIT_SNK,
-	TC_ATTACHED_SNK,
-	/* Super States */
-	TC_VBUS_CC_ISO,
-	TC_HOST_RARD,
-	TC_HOST_OPEN,
-};
-/* Forward declare the full list of states. This is indexed by usb_tc_state */
-static const struct usb_state tc_states[];
-
-/* List of human readable state names for console debugging */
-__maybe_unused static const char * const tc_state_names[] = {
-#ifdef CONFIG_COMMON_RUNTIME
-	[TC_DISABLED] = "Disabled",
-	[TC_UNATTACHED_SNK] = "Unattached.SNK",
-	[TC_ATTACH_WAIT_SNK] = "AttachWait.SNK",
-	[TC_ATTACHED_SNK] = "Attached.SNK",
-#endif
-};
-
-/* Forward declare private, common functions */
-static void set_state_tc(const int port, enum usb_tc_state new_state);
-
-/*
- * TCPC CC/Rp management
- *
- * Stub for linking purposes.
- * This is not supported for vpd, it uses a different mechanism to update
- * cc values.
- */
-void typec_select_pull(int port, enum tcpc_cc_pull pull)
-{
-}
-void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp)
-{
-}
-void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
-{
-}
-int typec_update_cc(int port)
-{
-	return EC_SUCCESS;
-}
-
-/* Public TypeC functions */
-
-void tc_state_init(int port)
-{
-	int res = 0;
-
-	res = tcpm_init(port);
-
-	CPRINTS("C%d: init %s", port, res ? "failed" : "ready");
-
-	/* Disable TCPC RX until connection is established */
-	tcpm_set_rx_enable(port, 0);
-
-	set_state_tc(port, res ? TC_DISABLED : TC_UNATTACHED_SNK);
-
-	/* Disable pd state machines */
-	tc[port].pd_enable = 0;
-	tc[port].flags = 0;
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	/* Vconn power device is always the sink */
-	return PD_ROLE_SINK;
-}
-
-enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	/* Vconn power device is always the cable */
-	return PD_PLUG_FROM_CABLE;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	/* Vconn power device doesn't have a data role, but UFP match SNK */
-	return PD_ROLE_UFP;
-}
-
-/* Note tc_set_power_role and tc_set_data_role are unimplemented */
-
-uint8_t tc_get_polarity(int port)
-{
-	/* Does not track polarity yet */
-	return 0;
-}
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return tc[port].pd_enable;
-}
-
-void tc_event_check(int port, int evt)
-{
-	/* Do Nothing */
-}
-
-/*
- * Private Functions
- */
-
-/* Set the TypeC state machine to a new state. */
-static void set_state_tc(const int port, const enum usb_tc_state new_state)
-{
-	set_state(port, &tc[port].ctx, &tc_states[new_state]);
-}
-
-/* Get the current TypeC state. */
-test_export_static enum usb_tc_state get_state_tc(const int port)
-{
-	return tc[port].ctx.current - &tc_states[0];
-}
-
-test_mockable_static void print_current_state(const int port)
-{
-	CPRINTS("C%d: %s", port, tc_state_names[get_state_tc(port)]);
-}
-
-/**
- * Disabled
- *
- * Super State Entries:
- *   Enable mcu communication
- *   Remove the terminations from Host CC
- */
-static void tc_disabled_entry(const int port)
-{
-	print_current_state(port);
-}
-
-static void tc_disabled_run(const int port)
-{
-	task_wait_event(-1);
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-	/*
-	 * This shouldn't happen. If it does, we need to send an event to the
-	 * PD task to put the SM into the disabled state. It is not safe to
-	 * directly set_state here since this may be in another task.
-	 */
-	assert(false);
-}
-
-static void tc_disabled_exit(const int port)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPC)) {
-		if (tcpm_init(port) != 0) {
-			CPRINTS("C%d: restart failed!", port);
-			return;
-		}
-	}
-
-	CPRINTS("C%d: resumed!", port);
-}
-
-/**
- * Unattached.SNK
- *
- * Super State Entry:
- *   Enable mcu communication
- *   Place Ra on VCONN and Rd on Host CC
- */
-static void tc_unattached_snk_entry(const int port)
-{
-	print_current_state(port);
-}
-
-static void tc_unattached_snk_run(const int port)
-{
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	/*
-	 * Transition to AttachWait.SNK when a Source connection is
-	 * detected, as indicated by the SNK.Rp state on its Host-side
-	 * port’s CC pin.
-	 */
-	if (cc_is_rp(host_cc))
-		set_state_tc(port, TC_ATTACH_WAIT_SNK);
-}
-
-/**
- * AttachedWait.SNK
- *
- * Super State Entry:
- *   Enable mcu communication
- *   Place Ra on VCONN and Rd on Host CC
- */
-static void tc_attach_wait_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Forces an initial debounce in run function */
-	tc[port].host_cc_state = -1;
-}
-
-static void tc_attach_wait_snk_run(const int port)
-{
-	int host_new_cc_state;
-	int host_cc;
-
-	/* Check Host CC for connection */
-	vpd_host_get_cc(&host_cc);
-
-	if (cc_is_rp(host_cc))
-		host_new_cc_state = PD_CC_DFP_ATTACHED;
-	else
-		host_new_cc_state = PD_CC_NONE;
-
-	/* Debounce the Host CC state */
-	if (tc[port].host_cc_state != host_new_cc_state) {
-		tc[port].host_cc_state = host_new_cc_state;
-		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
-		else
-			tc[port].cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
-
-		return;
-	}
-
-	/* Wait for Host CC debounce */
-	if (get_time().val < tc[port].cc_debounce)
-		return;
-
-	/*
-	 * A VCONN-Powered USB Device shall transition to
-	 * Attached.SNK after the state of the Host-side port’s CC pin is
-	 * SNK.Rp for at least tCCDebounce and either host-side VCONN or
-	 * VBUS is detected.
-	 *
-	 * Transition to Unattached.SNK when the state of both the CC1 and
-	 * CC2 pins is SNK.Open for at least tPDDebounce.
-	 */
-	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
-		set_state_tc(port, TC_ATTACHED_SNK);
-	else if (tc[port].host_cc_state == PD_CC_NONE)
-		set_state_tc(port, TC_UNATTACHED_SNK);
-}
-
-/**
- * Attached.SNK
- */
-static void tc_attached_snk_entry(const int port)
-{
-	print_current_state(port);
-
-	/* Enable PD */
-	tc[port].pd_enable = 1;
-	pd_set_polarity(port, 0);
-}
-
-static void tc_attached_snk_run(const int port)
-{
-	/* Has host vbus and vconn been removed */
-	if (!vpd_is_host_vbus_present() && !vpd_is_vconn_present()) {
-		set_state_tc(port, TC_UNATTACHED_SNK);
-		return;
-	}
-
-	if (vpd_is_vconn_present()) {
-		if (!(tc[port].flags & TC_FLAGS_VCONN_ON)) {
-			/* VCONN detected. Remove RA */
-			vpd_host_set_pull(TYPEC_CC_RD, 0);
-			tc[port].flags |= TC_FLAGS_VCONN_ON;
-		}
-	}
-}
-
-static void tc_attached_snk_exit(const int port)
-{
-	/* Disable PD */
-	tc[port].pd_enable = 0;
-	tc[port].flags &= ~TC_FLAGS_VCONN_ON;
-}
-
-/**
- * Super State HOST_RARD
- */
-static void tc_host_rard_entry(const int port)
-{
-	/* Place Ra on VCONN and Rd on Host CC */
-	vpd_host_set_pull(TYPEC_CC_RA_RD, 0);
-}
-
-/**
- * Super State HOST_OPEN
- */
-static void tc_host_open_entry(const int port)
-{
-	/* Remove the terminations from Host CC */
-	vpd_host_set_pull(TYPEC_CC_OPEN, 0);
-}
-
-/**
- * Super State VBUS_CC_ISO
- */
-static void tc_vbus_cc_iso_entry(const int port)
-{
-	/* Enable mcu communication and cc */
-	vpd_mcu_cc_en(1);
-}
-
-void tc_run(const int port)
-{
-	run_state(port, &tc[port].ctx);
-}
-
-/*
- * Type-C State Hierarchy (Sub-States are listed inside the boxes)
- *
- * | TC_VBUS_CC_ISO ----------------------------------------|
- * |                                                        |
- * |  | TC_HOST_RARD -----------| | TC_HOST_OPEN ---------| |
- * |  |                         | |                       | |
- * |  | TC_UNATTACHED_SNK       | | TC_DISABLED           | |
- * |  | TC_ATTACH_WAIT_SNK      | |-----------------------| |
- * |  |-------------------------|                           |
- * |--------------------------------------------------------|
- *
- * TC_ATTACHED_SNK
- */
-static const struct usb_state tc_states[] = {
-	/* Super States */
-	[TC_VBUS_CC_ISO] = {
-		.entry  = tc_vbus_cc_iso_entry,
-	},
-	[TC_HOST_RARD] = {
-		.entry  = tc_host_rard_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	[TC_HOST_OPEN] = {
-		.entry  = tc_host_open_entry,
-		.parent = &tc_states[TC_VBUS_CC_ISO],
-	},
-	/* Normal States */
-	[TC_DISABLED] = {
-		.entry  = tc_disabled_entry,
-		.run    = tc_disabled_run,
-		.exit   = tc_disabled_exit,
-		.parent = &tc_states[TC_HOST_OPEN],
-	},
-	[TC_UNATTACHED_SNK] = {
-		.entry  = tc_unattached_snk_entry,
-		.run    = tc_unattached_snk_run,
-		.parent = &tc_states[TC_HOST_RARD],
-	},
-	[TC_ATTACH_WAIT_SNK] = {
-		.entry  = tc_attach_wait_snk_entry,
-		.run    = tc_attach_wait_snk_run,
-		.parent = &tc_states[TC_HOST_RARD],
-	},
-	[TC_ATTACHED_SNK] = {
-		.entry  = tc_attached_snk_entry,
-		.run    = tc_attached_snk_run,
-		.exit   = tc_attached_snk_exit,
-	},
-};
-
-#ifdef TEST_BUILD
-const struct test_sm_data test_tc_sm_data[] = {
-	{
-		.base = tc_states,
-		.size = ARRAY_SIZE(tc_states),
-		.names = tc_state_names,
-		.names_size = ARRAY_SIZE(tc_state_names),
-	},
-};
-const int test_tc_sm_data_size = ARRAY_SIZE(test_tc_sm_data);
-#endif
diff --git a/common/usbc/usbc_pd_policy.c b/common/usbc/usbc_pd_policy.c
deleted file mode 100644
index 6a06d4014f..0000000000
--- a/common/usbc/usbc_pd_policy.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "usb_pe_sm.h"
-#include "usb_tc_sm.h"
-
-/*
- * TODO(b:159715784): Implement a more robust solution
- * to managing PD Policies.
- */
-
-/*
- * Default Port Discovery DR Swap Policy.
- *
- * 1) If dr_swap_to_dfp_flag == true and port data role is UFP,
- *    transition to pe_drs_send_swap
- */
-__overridable bool port_discovery_dr_swap_policy(int port,
-	enum pd_data_role dr, bool dr_swap_flag)
-{
-	if (dr_swap_flag && dr == PD_ROLE_UFP)
-		return true;
-
-	/* Do not perform a DR swap */
-	return false;
-}
-
-/*
- * Default Port Discovery VCONN Swap Policy.
- *
- * 1) If vconn_swap_to_on_flag == true, and vconn is currently off,
- * 2) Sourcing VCONN is possible
- *    then transition to pe_vcs_send_swap
- */
-__overridable bool port_discovery_vconn_swap_policy(int port,
-		bool vconn_swap_flag)
-{
-	if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag &&
-		!tc_is_vconn_src(port) && tc_check_vconn_swap(port))
-		return true;
-
-	/* Do not perform a VCONN swap */
-	return false;
-}
diff --git a/common/usbc/usbc_task.c b/common/usbc/usbc_task.c
deleted file mode 100644
index 09be36cd5e..0000000000
--- a/common/usbc/usbc_task.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "board.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_timer.h"
-#include "usb_prl_sm.h"
-#include "tcpm/tcpm.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "usbc_ppc.h"
-
-#define USBC_EVENT_TIMEOUT (5 * MSEC)
-#define USBC_MIN_EVENT_TIMEOUT (1 * MSEC)
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/*
- * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then
- * _GPIO_CCD_MODE_ODL is not needed. Declare as extern so IS_ENABLED will work.
- */
-#ifndef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-extern int _GPIO_CCD_MODE_ODL;
-#else
-#define _GPIO_CCD_MODE_ODL GPIO_CCD_MODE_ODL
-#endif /* CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT */
-
-static uint8_t paused[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void tc_pause_event_loop(int port)
-{
-	paused[port] = 1;
-}
-
-bool tc_event_loop_is_paused(int port)
-{
-	return paused[port];
-}
-
-void tc_start_event_loop(int port)
-{
-	/*
-	 * Only generate TASK_EVENT_WAKE event if state
-	 * machine is transitioning to un-paused
-	 */
-	if (paused[port]) {
-		paused[port] = 0;
-		task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-	}
-}
-
-static void pd_task_init(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_TYPEC_SM))
-		tc_state_init(port);
-	paused[port] = 0;
-
-	/*
-	 * Since most boards configure the TCPC interrupt as edge
-	 * and it is possible that the interrupt line was asserted between init
-	 * and calling set_state, we need to process any pending interrupts now.
-	 * Otherwise future interrupts will never fire because another edge
-	 * never happens. Note this needs to happen after set_state() is called.
-	 */
-	if (IS_ENABLED(CONFIG_HAS_TASK_PD_INT))
-		schedule_deferred_pd_interrupt(port);
-
-	/*
-	 * GPIO_CCD_MODE_ODL must be initialized with GPIO_ODR_HIGH
-	 * when CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is enabled
-	 */
-	if (IS_ENABLED(CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT))
-		ASSERT(gpio_get_default_flags(_GPIO_CCD_MODE_ODL) &
-		       GPIO_ODR_HIGH);
-}
-
-static int pd_task_timeout(int port)
-{
-	int timeout;
-
-	if (paused[port])
-		timeout = -1;
-	else {
-		timeout = pd_timer_next_expiration(port);
-		if (timeout < 0 || timeout > USBC_EVENT_TIMEOUT)
-			timeout = USBC_EVENT_TIMEOUT;
-		else if (timeout < USBC_MIN_EVENT_TIMEOUT)
-			timeout = USBC_MIN_EVENT_TIMEOUT;
-	}
-	return timeout;
-}
-
-static bool pd_task_loop(int port)
-{
-	/* wait for next event/packet or timeout expiration */
-	const uint32_t evt = task_wait_event(pd_task_timeout(port));
-
-	/* Manage expired PD Timers on timeouts */
-	if (evt & TASK_EVENT_TIMER)
-		pd_timer_manage_expired(port);
-
-	/*
-	 * Re-use TASK_EVENT_RESET_DONE in tests to restart the USB task
-	 * if this code is running in a unit test.
-	 */
-	if (IS_ENABLED(TEST_BUILD) && (evt & TASK_EVENT_RESET_DONE))
-		return false;
-
-	/* handle events that affect the state machine as a whole */
-	if (IS_ENABLED(CONFIG_USB_TYPEC_SM))
-		tc_event_check(port, evt);
-
-	/*
-	 * run port controller task to check CC and/or read incoming
-	 * messages
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_TCPC))
-		tcpc_run(port, evt);
-
-	/* Run policy engine state machine */
-	if (IS_ENABLED(CONFIG_USB_PE_SM))
-		pe_run(port, evt, tc_get_pd_enabled(port));
-
-	/* Run protocol state machine */
-	if (IS_ENABLED(CONFIG_USB_PRL_SM) || IS_ENABLED(CONFIG_TEST_USB_PE_SM))
-		prl_run(port, evt, tc_get_pd_enabled(port));
-
-	/* Run TypeC state machine */
-	if (IS_ENABLED(CONFIG_USB_TYPEC_SM))
-		tc_run(port);
-
-	return true;
-}
-
-void pd_task(void *u)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	/*
-	 * If port does not exist, return
-	 */
-	if (port >= board_get_usb_pd_port_count())
-		return;
-
-	while (1) {
-		pd_timer_init(port);
-		pd_task_init(port);
-
-		/* As long as pd_task_loop returns true, keep running the loop.
-		 * pd_task_loop returns false when the code needs to re-init
-		 * the task, so once the code breaks out of the inner while
-		 * loop, the re-init code at the top of the outer while loop
-		 * will run.
-		 */
-		while (pd_task_loop(port))
-			continue;
-	}
-}
diff --git a/common/usbc_intr_task.c b/common/usbc_intr_task.c
deleted file mode 100644
index 0532645a35..0000000000
--- a/common/usbc_intr_task.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* High-priority interrupt tasks implementations */
-
-#include <stdint.h>
-
-#include "assert.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Events for pd_interrupt_handler_task */
-#define PD_PROCESS_INTERRUPT  BIT(0)
-
-/*
- * Theoretically, we may need to support up to 480 USB-PD packets per second for
- * intensive operations such as FW update over PD. This value has tested well
- * preventing watchdog resets with a single bad port partner plugged in.
- */
-#define ALERT_STORM_MAX_COUNT   480
-#define ALERT_STORM_INTERVAL    SECOND
-
-static uint8_t pd_int_task_id[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void schedule_deferred_pd_interrupt(const int port)
-{
-	/*
-	 * Don't set event to idle task if task id is 0. This happens when
-	 * not all the port have pd int task, the pd_int_task_id of port
-	 * that doesn't have pd int task is 0.
-	 */
-	if (pd_int_task_id[port] != 0)
-		task_set_event(pd_int_task_id[port], PD_PROCESS_INTERRUPT);
-}
-
-static struct {
-	int count;
-	timestamp_t time;
-} storm_tracker[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static void service_one_port(int port)
-{
-	timestamp_t now;
-
-	tcpc_alert(port);
-
-	now = get_time();
-	if (timestamp_expired(storm_tracker[port].time,
-			      &now)) {
-		/* Reset timer into future */
-		storm_tracker[port].time.val = now.val + ALERT_STORM_INTERVAL;
-
-		/*
-		 * Start at 1 since we are processing an interrupt right
-		 * now
-		 */
-		storm_tracker[port].count = 1;
-	} else if (++storm_tracker[port].count > ALERT_STORM_MAX_COUNT) {
-		CPRINTS("C%d: Interrupt storm detected."
-			" Disabling port temporarily",
-			port);
-
-		pd_set_suspend(port, 1);
-		pd_deferred_resume(port);
-	}
-}
-
-__overridable void board_process_pd_alert(int port)
-{
-}
-
-/*
- * Main task entry point that handles PD interrupts for a single port.  These
- * interrupts usually come from a TCPC, but may also come from PD-related chips
- * sharing the TCPC interrupt line.
- *
- * @param p The PD port number for which to handle interrupts (pointer is
- * reinterpreted as an integer directly).
- */
-void pd_interrupt_handler_task(void *p)
-{
-	const int port = (int) ((intptr_t) p);
-	const int port_mask = (PD_STATUS_TCPC_ALERT_0 << port);
-
-	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	/*
-	 * If port does not exist, return
-	 */
-	if (port >= board_get_usb_pd_port_count())
-		return;
-
-	pd_int_task_id[port] = task_get_current();
-
-	while (1) {
-		const int evt = task_wait_event(-1);
-
-		if ((evt & PD_PROCESS_INTERRUPT) == 0)
-			continue;
-		/*
-		 * While the interrupt signal is asserted; we have more
-		 * work to do. This effectively makes the interrupt a
-		 * level-interrupt instead of an edge-interrupt without
-		 * having to enable/disable a real level-interrupt in
-		 * multiple locations.
-		 *
-		 * Also, if the port is disabled do not process
-		 * interrupts. Upon existing suspend, we schedule a
-		 * PD_PROCESS_INTERRUPT to check if we missed anything.
-		 */
-		while ((tcpc_get_alert_status() & port_mask) &&
-		       pd_is_port_enabled(port)) {
-
-			service_one_port(port);
-		}
-
-		board_process_pd_alert(port);
-	}
-}
-
-/*
- * This code assumes port alert masks are adjacent to each other.
- */
-BUILD_ASSERT(PD_STATUS_TCPC_ALERT_3 == (PD_STATUS_TCPC_ALERT_0 << 3));
-
-/*
- * Shared TCPC interrupt handler. The function argument in ec.tasklist
- * is the mask of ports to handle. For example:
- *
- *    BIT(USBC_PORT_C2) | BIT(USBC_PORT_C0)
- *
- * Note that this bitmask is 0-based while PD_STATUS_TCPC_ALERT_<port>
- * is not.
- */
-
-void pd_shared_alert_task(void *p)
-{
-	const int sources_mask = (int) ((intptr_t) p);
-	int want_alerts = 0;
-	int port;
-	int port_mask;
-
-	CPRINTS("%s: port mask 0x%02x", __func__, sources_mask);
-
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
-		if ((sources_mask & BIT(port)) == 0)
-			continue;
-		if (!board_is_usb_pd_port_present(port))
-			continue;
-
-		port_mask = PD_STATUS_TCPC_ALERT_0 << port;
-		want_alerts |= port_mask;
-		pd_int_task_id[port] = task_get_current();
-	}
-
-	if (want_alerts == 0) {
-		/*
-		 * None of the configured alert sources are available.
-		 */
-		return;
-	}
-
-	while (1) {
-		const int evt = task_wait_event(-1);
-		int have_alerts;
-
-		if ((evt & PD_PROCESS_INTERRUPT) == 0)
-			continue;
-
-		/*
-		 * While the interrupt signal is asserted; we have more
-		 * work to do. This effectively makes the interrupt a
-		 * level-interrupt instead of an edge-interrupt without
-		 * having to enable/disable a real level-interrupt in
-		 * multiple locations.
-		 *
-		 * Also, if the port is disabled do not process
-		 * interrupts. Upon existing suspend, we schedule a
-		 * PD_PROCESS_INTERRUPT to check if we missed anything.
-		 */
-		do {
-			have_alerts = tcpc_get_alert_status();
-			have_alerts &= want_alerts;
-
-			for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT;
-			     ++port) {
-				port_mask = PD_STATUS_TCPC_ALERT_0 << port;
-				if ((have_alerts & port_mask) == 0) {
-					/* skip quiet port */
-					continue;
-				}
-				if (!pd_is_port_enabled(port)) {
-					/* filter out disabled port */
-					have_alerts &= ~port_mask;
-					continue;
-				}
-				service_one_port(port);
-			}
-		} while (have_alerts != 0);
-	}
-}
diff --git a/common/usbc_ocp.c b/common/usbc_ocp.c
deleted file mode 100644
index e20cf9f1f8..0000000000
--- a/common/usbc_ocp.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB-C Overcurrent Protection Common Code */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_ocp.h"
-#include "util.h"
-
-#ifndef TEST_BUILD
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(args...)
-#define CPRINTS(args...)
-#endif
-
-/*
- * Number of times a port may overcurrent before we latch off the port until a
- * physical disconnect is detected.
- */
-#define OCP_CNT_THRESH 3
-
-/*
- * Number of seconds until a latched-off port is re-enabled for sourcing after
- * detecting a physical disconnect.
- */
-#define OCP_COOLDOWN_DELAY_US (2 * SECOND)
-
-/*
- * A per-port table that indicates how many VBUS overcurrent events have
- * occurred.  This table is cleared after detecting a physical disconnect of the
- * sink.
- */
-static uint8_t oc_event_cnt_tbl[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* A flag for ports with sink device connected. */
-static uint32_t snk_connected_ports;
-
-static void clear_oc_tbl(void)
-{
-	int port;
-
-	for (port = 0; port < board_get_usb_pd_port_count(); port++)
-		/*
-		 * Only clear the table if the port partner is no longer
-		 * attached after debouncing.
-		 */
-		if ((!(BIT(port) & snk_connected_ports)) &&
-		    oc_event_cnt_tbl[port]) {
-			oc_event_cnt_tbl[port] = 0;
-			CPRINTS("C%d: OC events cleared", port);
-		}
-}
-DECLARE_DEFERRED(clear_oc_tbl);
-
-int usbc_ocp_add_event(int port)
-{
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	oc_event_cnt_tbl[port]++;
-
-	/* The port overcurrented, so don't clear it's OC events. */
-	atomic_clear_bits(&snk_connected_ports, 1 << port);
-
-	if (oc_event_cnt_tbl[port] >= OCP_CNT_THRESH)
-		CPRINTS("C%d: OC event limit reached! "
-			   "Source path disabled until physical disconnect.",
-			   port);
-	return EC_SUCCESS;
-}
-
-
-int usbc_ocp_clear_event_counter(int port)
-{
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * If we are clearing our event table in quick succession, we may be in
-	 * an overcurrent loop where we are also detecting a disconnect on the
-	 * CC pins.  Therefore, let's not clear it just yet and the let the
-	 * limit be reached.  This way, we won't send the hard reset and
-	 * actually detect the physical disconnect.
-	 */
-	if (oc_event_cnt_tbl[port]) {
-		hook_call_deferred(&clear_oc_tbl_data,
-				   OCP_COOLDOWN_DELAY_US);
-	}
-	return EC_SUCCESS;
-}
-
-int usbc_ocp_is_port_latched_off(int port)
-{
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return 0;
-	}
-
-	return oc_event_cnt_tbl[port] >= OCP_CNT_THRESH;
-}
-
-void usbc_ocp_snk_is_connected(int port, bool connected)
-{
-	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return;
-	}
-
-	if (connected)
-		atomic_or(&snk_connected_ports, 1 << port);
-	else
-		atomic_clear_bits(&snk_connected_ports, 1 << port);
-}
-
-__overridable void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* Do nothing by default.  Boards with overcurrent GPIOs may override */
-}
diff --git a/common/usbc_ppc.c b/common/usbc_ppc.c
deleted file mode 100644
index 0281ceaf64..0000000000
--- a/common/usbc_ppc.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB-C Power Path Controller Common Code */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#ifndef TEST_BUILD
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#else
-#define CPRINTF(args...)
-#define CPRINTS(args...)
-#endif
-
-int ppc_prints(const char *string, int port)
-{
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s", port, string);
-#else
-	return 0;
-#endif
-}
-
-int ppc_err_prints(const char *string, int port, int error)
-{
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s (%d)", port, string, error);
-#else
-	return 0;
-#endif
-}
-
-/* Simple wrappers to dispatch to the drivers. */
-
-int ppc_init(int port)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->init) {
-		rv = ppc->drv->init(port);
-		if (rv)
-			ppc_err_prints("init failed!", port, rv);
-		else
-			ppc_prints("init'd.", port);
-	}
-
-	return rv;
-}
-
-int ppc_is_sourcing_vbus(int port)
-{
-	int rv = 0;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return 0;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->is_sourcing_vbus)
-		rv = ppc->drv->is_sourcing_vbus(port);
-
-	return rv;
-}
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-int ppc_set_polarity(int port, int polarity)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->set_polarity)
-		rv = ppc->drv->set_polarity(port, polarity);
-
-	return rv;
-}
-#endif
-
-int ppc_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->set_vbus_source_current_limit)
-		rv = ppc->drv->set_vbus_source_current_limit(port, rp);
-
-	return rv;
-}
-
-int ppc_discharge_vbus(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->discharge_vbus)
-		rv = ppc->drv->discharge_vbus(port, enable);
-
-	return rv;
-}
-
-#ifdef CONFIG_USBC_PPC_SBU
-int ppc_set_sbu(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->set_sbu)
-		rv = ppc->drv->set_sbu(port, enable);
-
-	return rv;
-}
-#endif /* defined(CONFIG_USBC_PPC_SBU) */
-
-#ifdef CONFIG_USBC_PPC_VCONN
-int ppc_set_vconn(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->set_vconn)
-		rv = ppc->drv->set_vconn(port, enable);
-
-	return rv;
-}
-#endif
-
-int ppc_dev_is_connected(int port, enum ppc_device_role dev)
-{
-	int rv = EC_SUCCESS;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->dev_is_connected)
-		rv = ppc->drv->dev_is_connected(port, dev);
-
-	return rv;
-}
-
-int ppc_vbus_sink_enable(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->vbus_sink_enable)
-		rv = ppc->drv->vbus_sink_enable(port, enable);
-
-	return rv;
-}
-
-int ppc_enter_low_power_mode(int port)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->enter_low_power_mode)
-		rv = ppc->drv->enter_low_power_mode(port);
-
-	return rv;
-}
-
-int ppc_vbus_source_enable(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->vbus_source_enable)
-		rv = ppc->drv->vbus_source_enable(port, enable);
-
-	return rv;
-}
-
-#ifdef CONFIG_USB_PD_FRS_PPC
-int ppc_set_frs_enable(int port, int enable)
-{
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-
-	if (ppc->drv->set_frs_enable)
-		rv = ppc->drv->set_frs_enable(port,enable);
-
-	return rv;
-}
-#endif /* defined(CONFIG_USB_PD_FRS_PPC) */
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int ppc_is_vbus_present(int port)
-{
-	int rv = 0;
-	const struct ppc_config_t *ppc;
-
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return 0;
-	}
-
-	ppc = &ppc_chips[port];
-
-	if (ppc->drv->is_vbus_present)
-		rv = ppc->drv->is_vbus_present(port);
-
-	return rv;
-}
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-
-#ifdef CONFIG_CMD_PPC_DUMP
-static int command_ppc_dump(int argc, char **argv)
-{
-	int port;
-	int rv = EC_ERROR_UNIMPLEMENTED;
-	const struct ppc_config_t *ppc;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = atoi(argv[1]);
-	if ((port < 0) || (port >= ppc_cnt)) {
-		CPRINTS("%s(%d) Invalid port!", __func__, port);
-		return EC_ERROR_INVAL;
-	}
-
-	ppc = &ppc_chips[port];
-	if (ppc->drv->reg_dump)
-		rv = ppc->drv->reg_dump(port);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ppc_dump, command_ppc_dump, "<Type-C port>",
-			"dump the PPC regs");
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
diff --git a/common/vboot/common.c b/common/vboot/common.c
deleted file mode 100644
index 39f8c193c7..0000000000
--- a/common/vboot/common.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "rsa.h"
-#include "sha256.h"
-#include "shared_mem.h"
-#include "vboot.h"
-
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ## args)
-
-int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end)
-{
-	const uint32_t *data32 = (const uint32_t *)data;
-	int i;
-
-	if (start > end)
-		return EC_ERROR_INVAL;
-
-	if (start % 4 || end % 4)
-		return EC_ERROR_INVAL;
-
-	for (i = start / 4; i < end / 4; i++) {
-		if (data32[i] != 0xffffffff)
-			return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-int vboot_verify(const uint8_t *data, int len,
-		 const struct rsa_public_key *key, const uint8_t *sig)
-{
-	struct sha256_ctx ctx;
-	uint8_t *hash;
-	uint32_t *workbuf;
-	int err = EC_SUCCESS;
-
-	if (SHARED_MEM_ACQUIRE_CHECK(3 * RSANUMBYTES, (char **)&workbuf))
-		return EC_ERROR_MEMORY_ALLOCATION;
-
-	/* Compute hash of the RW firmware */
-	SHA256_init(&ctx);
-	SHA256_update(&ctx, data, len);
-	hash = SHA256_final(&ctx);
-
-	/* Verify the data */
-	if (rsa_verify(key, sig, hash, workbuf) != 1)
-		err = EC_ERROR_VBOOT_DATA_VERIFY;
-
-	shared_mem_release(workbuf);
-
-	return err;
-}
diff --git a/common/vboot/efs2.c b/common/vboot/efs2.c
deleted file mode 100644
index e5c3b64f04..0000000000
--- a/common/vboot/efs2.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Early Firmware Selection ver.2.
- *
- * Verify and jump to a RW image. Register boot mode to Cr50.
- */
-
-#include "battery.h"
-#include "chipset.h"
-#include "clock.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "crc8.h"
-#include "flash.h"
-#include "hooks.h"
-#include "sha256.h"
-#include "system.h"
-#include "task.h"
-#include "usb_pd.h"
-#include "uart.h"
-#include "vboot.h"
-#include "vboot_hash.h"
-
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
-
-static const char *boot_mode_to_string(uint8_t mode)
-{
-	static const char *boot_mode_str[] = {
-		[BOOT_MODE_NORMAL] =		"NORMAL",
-		[BOOT_MODE_NO_BOOT] =		"NO_BOOT",
-	};
-	if (mode < ARRAY_SIZE(boot_mode_str))
-		return boot_mode_str[mode];
-	return "UNDEF";
-}
-
-/*
- * Check whether the session has successfully ended or not. ERR_TIMEOUT is
- * excluded because it's an internal error produced by EC itself.
- */
-static bool is_valid_cr50_response(enum cr50_comm_err code)
-{
-	return code != CR50_COMM_ERR_TIMEOUT
-			&& (code >> 8) == CR50_COMM_ERR_PREFIX;
-}
-
-__overridable void board_enable_packet_mode(bool enable)
-{
-	/*
-	 * This can be done by set_flags(INPUT|PULL_UP). We don't need it now
-	 * because Cr50 never initiates communication.
-	 */
-	gpio_set_level(GPIO_PACKET_MODE_EN, enable ? 1 : 0);
-}
-
-static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
-{
-	timestamp_t until;
-	int i, timeout = 0;
-	uint32_t lock_key;
-	struct cr50_comm_response res = {};
-
-	/* This will wake up (if it's sleeping) and interrupt Cr50. */
-	board_enable_packet_mode(true);
-
-	uart_flush_output();
-	uart_clear_input();
-
-	if (uart_shell_stop()) {
-		/* Failed to stop the shell. */
-		board_enable_packet_mode(false);
-		return CR50_COMM_ERR_UNKNOWN;
-	}
-
-	/*
-	 * Send packet. No traffic control, assuming Cr50 consumes stream much
-	 * faster. TX buffer shouldn't overflow because it's cleared above and
-	 * much bigger than the max packet size.
-	 *
-	 * Disable interrupts so that the data frame will be stored in the Tx
-	 * buffer in one piece.
-	 */
-	lock_key = irq_lock();
-	uart_put_raw(data, size);
-	irq_unlock(lock_key);
-
-	uart_flush_output();
-
-	until.val = get_time().val + CR50_COMM_TIMEOUT;
-
-	/*
-	 * Make sure console task won't steal the response in case we exchange
-	 * packets after tasks start.
-	 */
-#ifndef CONFIG_ZEPHYR
-	if (task_start_called())
-		task_disable_task(TASK_ID_CONSOLE);
-#endif /* !CONFIG_ZEPHYR */
-
-	/* Wait for response from Cr50 */
-	for (i = 0; i < sizeof(res); i++) {
-		while (!timeout) {
-			int c = uart_getc();
-			if (c != -1) {
-				res.error = res.error | c << (i*8);
-				break;
-			}
-			msleep(1);
-			timeout = timestamp_expired(until, NULL);
-		}
-	}
-
-	uart_shell_start();
-#ifndef CONFIG_ZEPHYR
-	if (task_start_called())
-		task_enable_task(TASK_ID_CONSOLE);
-#endif /* CONFIG_ZEPHYR */
-
-	/* Exit packet mode */
-	board_enable_packet_mode(false);
-
-	CPRINTS("Received 0x%04x", res.error);
-
-	if (timeout) {
-		CPRINTS("Timeout");
-		return CR50_COMM_ERR_TIMEOUT;
-	}
-
-	return res.error;
-}
-
-static enum cr50_comm_err cmd_to_cr50(enum cr50_comm_cmd cmd,
-				      const uint8_t *data, size_t size)
-{
-	/*
-	 * This is on the stack instead of .bss because vboot_main currently is
-	 * called only once (from main). Keeping the space unused in .bss would
-	 * be wasteful.
-	 */
-	struct {
-		uint8_t preamble[CR50_UART_RX_BUFFER_SIZE];
-		uint8_t packet[CR50_COMM_MAX_REQUEST_SIZE];
-	} __packed s;
-	struct cr50_comm_request *p = (struct cr50_comm_request *)s.packet;
-	int retry = CR50_COMM_MAX_RETRY;
-	enum cr50_comm_err rv;
-
-	/* compose a frame = preamble + packet */
-	memset(s.preamble, CR50_COMM_PREAMBLE, sizeof(s.preamble));
-	p->magic = CR50_PACKET_MAGIC;
-	p->struct_version = CR50_COMM_PACKET_VERSION;
-	p->type = cmd;
-	p->size = size;
-	memcpy(p->data, data, size);
-	p->crc = cros_crc8((uint8_t *)&p->type,
-		      sizeof(p->type) + sizeof(p->size) + size);
-
-	do {
-		rv = send_to_cr50((uint8_t *)&s,
-				  sizeof(s.preamble) + sizeof(*p) + p->size);
-		if (is_valid_cr50_response(rv))
-			break;
-		msleep(5);
-	} while (--retry);
-
-	return rv;
-}
-
-static enum cr50_comm_err verify_hash(void)
-{
-	const uint8_t *hash;
-	int rv;
-
-	/* Wake up Cr50 beforehand in case it's asleep. */
-	board_enable_packet_mode(true);
-	CPRINTS("Ping Cr50");
-	msleep(1);
-	board_enable_packet_mode(false);
-
-	rv = vboot_get_rw_hash(&hash);
-	if (rv)
-		return rv;
-
-	CPRINTS("Verifying hash");
-	return cmd_to_cr50(CR50_COMM_CMD_VERIFY_HASH, hash, SHA256_DIGEST_SIZE);
-}
-
-static enum cr50_comm_err set_boot_mode(uint8_t mode)
-{
-	enum cr50_comm_err rv;
-
-	CPRINTS("Setting boot mode to %s(%d)", boot_mode_to_string(mode), mode);
-	rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE,
-			 &mode, sizeof(enum boot_mode));
-	if (rv != CR50_COMM_SUCCESS)
-		CPRINTS("Failed to set boot mode");
-	return rv;
-}
-
-static bool pd_comm_enabled;
-
-static void enable_pd(void)
-{
-	CPRINTS("Enable USB-PD");
-	pd_comm_enabled = true;
-}
-
-bool vboot_allow_usb_pd(void)
-{
-	return pd_comm_enabled;
-}
-
-__overridable void show_critical_error(void)
-{
-	CPRINTS("%s", __func__);
-}
-
-static void verify_and_jump(void)
-{
-	enum cr50_comm_err rv = verify_hash();
-
-	switch (rv) {
-	case CR50_COMM_ERR_BAD_PAYLOAD:
-		/* Cr50 should have set NO_BOOT. */
-		CPRINTS("Hash mismatch");
-		enable_pd();
-		break;
-	case CR50_COMM_SUCCESS:
-		system_set_reset_flags(EC_RESET_FLAG_EFS);
-		rv = system_run_image_copy(EC_IMAGE_RW);
-		CPRINTS("Failed to jump (0x%x)", rv);
-		system_clear_reset_flags(EC_RESET_FLAG_EFS);
-		show_critical_error();
-		break;
-	default:
-		CPRINTS("Failed to verify RW (0x%x)", rv);
-		show_critical_error();
-	}
-}
-
-__overridable void show_power_shortage(void)
-{
-	CPRINTS("%s", __func__);
-}
-
-static bool is_battery_ready(void)
-{
-	/* TODO: Add battery check (https://crbug.com/1045216) */
-	return true;
-}
-
-void vboot_main(void)
-{
-	CPRINTS("Main");
-
-	if (system_is_in_rw()) {
-		/*
-		 * We come here and immediately return. LED shows power shortage
-		 * but it will be immediately corrected if the adapter can
-		 * provide enough power.
-		 */
-		CPRINTS("Already in RW");
-		show_power_shortage();
-		return;
-	}
-
-	if (system_is_manual_recovery() ||
-	    (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO)) {
-		if (system_is_manual_recovery())
-			CPRINTS("In recovery mode");
-		if (!IS_ENABLED(CONFIG_BATTERY)
-				&& !IS_ENABLED(HAS_TASK_KEYSCAN)) {
-			/*
-			 * For Chromeboxes, we relax security by allowing PD in
-			 * RO. Attackers don't gain meaningful advantage on
-			 * built-in-keyboard-less systems.
-			 *
-			 * Alternatively, we can use NO_BOOT to show a firmware
-			 * screen, strictly requiring BJ adapter and keeping PD
-			 * disabled.
-			 */
-			enable_pd();
-			return;
-		}
-
-		/*
-		 * If battery is drained or bad, we will boot in NO_BOOT mode to
-		 * inform the user of the problem.
-		 */
-		if (!is_battery_ready()) {
-			CPRINTS("Battery not ready or bad");
-			if (set_boot_mode(BOOT_MODE_NO_BOOT) ==
-					CR50_COMM_SUCCESS)
-				enable_pd();
-		}
-
-		/* We'll enter recovery mode immediately, later, or never. */
-		return;
-	}
-
-	verify_and_jump();
-
-	/*
-	 * EFS failed. EC-RO may be able to boot AP if:
-	 *
-	 *   - Battery is charged or
-	 *   - AC adapter supply in RO >= Boot threshold or
-	 *   - BJ adapter is plugged.
-	 *
-	 * Once AP boots, software sync will fix the mismatch. If that's the
-	 * reason of the failure, we won't come back here next time.
-	 */
-	CPRINTS("Exit");
-}
-
-void hook_shutdown(void)
-{
-	CPRINTS("%s", __func__);
-
-	/*
-	 * We filter the cases which can be interfered with if we execute
-	 * system_reset in HOOK_CHIPSET_SHUTDOWN context. Most cases are
-	 * filtered out by system_is_in_rw (e.g. system_common_shutdown,
-	 * check_pending_cutoff).
-	 */
-	if (system_is_in_rw())
-		return;
-
-	/*
-	 * We can't reset here because it'll completely tear down the power
-	 * and disturb the PCH's power sequence. We instead sysjump.
-	 *
-	 * Note that this does not reduce the security. Even if it's hijacked in
-	 * NO_BOOT mode, an RO still needs to go through a cold reset to clear
-	 * NO_BOOT flag since Cr50 rejects to switch from NO_BOOT to NORMAL.
-	 * If a spoofed matching hash is passed to Cr50, Cr50 would reset EC.
-	 */
-	system_set_reset_flags(EC_RESET_FLAG_AP_IDLE);
-	verify_and_jump();
-}
-/*
- * There can be hooks which are needed to set external chips to a certain state
- * in S5. If the initial state (i.e. AP_OFF state) is different from what those
- * hooks realize, they need to be considered. This hook runs last (i.e.
- * HOOK_PRIO_LAST) to make our landing on S5 as mild as possible.
- */
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, hook_shutdown, HOOK_PRIO_LAST);
diff --git a/common/vboot/vb21_lib.c b/common/vboot/vb21_lib.c
deleted file mode 100644
index 4e215c14e5..0000000000
--- a/common/vboot/vb21_lib.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Common utility APIs for vboot 2.1
- */
-
-#include "common.h"
-#include "host_command.h"
-#include "rsa.h"
-#include "rwsig.h"
-#include "system.h"
-#include "vb21_struct.h"
-#include "vboot.h"
-
-int vb21_is_packed_key_valid(const struct vb21_packed_key *key)
-{
-	if (key->c.magic != VB21_MAGIC_PACKED_KEY)
-		return EC_ERROR_VBOOT_KEY_MAGIC;
-	if (key->key_size != sizeof(struct rsa_public_key))
-		return EC_ERROR_VBOOT_KEY_SIZE;
-	return EC_SUCCESS;
-}
-
-int vb21_is_signature_valid(const struct vb21_signature *sig,
-			    const struct vb21_packed_key *key)
-{
-	if (sig->c.magic != VB21_MAGIC_SIGNATURE)
-		return EC_ERROR_VBOOT_SIG_MAGIC;
-	if (sig->sig_size != RSANUMBYTES)
-		return EC_ERROR_VBOOT_SIG_SIZE;
-	if (key->sig_alg != sig->sig_alg)
-		return EC_ERROR_VBOOT_SIG_ALGORITHM;
-	if (key->hash_alg != sig->hash_alg)
-		return EC_ERROR_VBOOT_HASH_ALGORITHM;
-	/* Validity check signature offset and data size. */
-	if (sig->sig_offset < sizeof(*sig))
-		return EC_ERROR_VBOOT_SIG_OFFSET;
-	if (sig->sig_offset + RSANUMBYTES > CONFIG_RW_SIG_SIZE)
-		return EC_ERROR_VBOOT_SIG_OFFSET;
-	if (sig->data_size > CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-		return EC_ERROR_VBOOT_DATA_SIZE;
-	return EC_SUCCESS;
-}
-
-const struct vb21_packed_key *vb21_get_packed_key(void)
-{
-	return (const struct vb21_packed_key *)(CONFIG_RO_PUBKEY_ADDR);
-}
-
-static void read_rwsig_info(struct ec_response_rwsig_info *r)
-{
-
-	const struct vb21_packed_key *vb21_key;
-	int rv;
-
-	vb21_key = vb21_get_packed_key();
-
-	r->sig_alg = vb21_key->sig_alg;
-	r->hash_alg = vb21_key->hash_alg;
-	r->key_version = vb21_key->key_version;
-	{ BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id),
-		       "key ID sizes must match"); }
-	{ BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw),
-		       "key ID sizes must match"); }
-	memcpy(r->key_id, vb21_key->id.raw, sizeof(r->key_id));
-
-	rv = vb21_is_packed_key_valid(vb21_key);
-	r->key_is_valid = (rv == EC_SUCCESS);
-}
-
-static int command_rwsig_info(int argc, char **argv)
-{
-	int i;
-	struct ec_response_rwsig_info r;
-
-	read_rwsig_info(&r);
-
-	ccprintf("sig_alg: %d\n", r.sig_alg);
-	ccprintf("key_version: %d\n", r.key_version);
-	ccprintf("hash_alg: %d\n", r.hash_alg);
-	ccprintf("key_is_valid: %d\n", r.key_is_valid);
-
-	ccprintf("key_id: ");
-	for (i = 0; i < sizeof(r.key_id); i++)
-		ccprintf("%x", r.key_id[i]);
-	ccprintf("\n");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rwsiginfo, command_rwsig_info, NULL,
-			"Display rwsig info on console.");
-
-static enum ec_status
-host_command_rwsig_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rwsig_info *r = args->response;
-
-	read_rwsig_info(r);
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_INFO, host_command_rwsig_info,
-		     EC_VER_MASK(EC_VER_RWSIG_INFO));
diff --git a/common/vboot/vboot.c b/common/vboot/vboot.c
deleted file mode 100644
index 910156335d..0000000000
--- a/common/vboot/vboot.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Verify and jump to a RW image if power supply is not sufficient.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "clock.h"
-#include "console.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "rsa.h"
-#include "rwsig.h"
-#include "stdbool.h"
-#include "sha256.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "usb_pd.h"
-#include "vboot.h"
-#include "vb21_struct.h"
-
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
-
-static int has_matrix_keyboard(void)
-{
-	return 0;
-}
-
-static int verify_slot(enum ec_image slot)
-{
-	const struct vb21_packed_key *vb21_key;
-	const struct vb21_signature *vb21_sig;
-	const struct rsa_public_key *key;
-	const uint8_t *sig;
-	const uint8_t *data;
-	int len;
-	int rv;
-
-	CPRINTS("Verifying %s", ec_image_to_string(slot));
-
-	vb21_key = (const struct vb21_packed_key *)(
-			CONFIG_MAPPED_STORAGE_BASE +
-			CONFIG_EC_PROTECTED_STORAGE_OFF +
-			CONFIG_RO_PUBKEY_STORAGE_OFF);
-	rv = vb21_is_packed_key_valid(vb21_key);
-	if (rv) {
-		CPRINTS("Invalid key (%d)", rv);
-		return EC_ERROR_VBOOT_KEY;
-	}
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
-
-	if (slot == EC_IMAGE_RW_A) {
-		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_SIGN_STORAGE_OFF);
-	} else {
-		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_SIGN_STORAGE_OFF);
-	}
-
-	rv = vb21_is_signature_valid(vb21_sig, vb21_key);
-	if (rv) {
-		CPRINTS("Invalid signature (%d)", rv);
-		return EC_ERROR_INVAL;
-	}
-	sig = (const uint8_t *)vb21_sig + vb21_sig->sig_offset;
-	len = vb21_sig->data_size;
-
-	if (vboot_is_padding_valid(data, len,
-				   CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)) {
-		CPRINTS("Invalid padding");
-		return EC_ERROR_INVAL;
-	}
-
-	rv = vboot_verify(data, len, key, sig);
-	if (rv) {
-		CPRINTS("Invalid data (%d)", rv);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTS("Verified %s", ec_image_to_string(slot));
-
-	return EC_SUCCESS;
-}
-
-static enum ec_status hc_verify_slot(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_efs_verify *p = args->params;
-	enum ec_image slot;
-
-	switch (p->region) {
-	case EC_FLASH_REGION_ACTIVE:
-		slot = system_get_active_copy();
-		break;
-	case EC_FLASH_REGION_UPDATE:
-		slot = system_get_update_copy();
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	return verify_slot(slot) ? EC_RES_ERROR : EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_EFS_VERIFY, hc_verify_slot, EC_VER_MASK(0));
-
-static int verify_and_jump(void)
-{
-	enum ec_image slot;
-	int rv;
-
-	/* 1. Decide which slot to try */
-	slot = system_get_active_copy();
-
-	/* 2. Verify the slot */
-	rv = verify_slot(slot);
-	if (rv) {
-		if (rv == EC_ERROR_VBOOT_KEY)
-			/* Key error. The other slot isn't worth trying. */
-			return rv;
-		slot = system_get_update_copy();
-		/* TODO(chromium:767050): Skip reading key again. */
-		rv = verify_slot(slot);
-		if (rv)
-			/* Both slots failed */
-			return rv;
-
-		/* Proceed with the other slot. If this slot isn't expected, AP
-		 * will catch it and request recovery after a few attempts. */
-		if (system_set_active_copy(slot))
-			CPRINTS("Failed to activate %s",
-				ec_image_to_string(slot));
-	}
-
-	/* 3. Jump (and reboot) */
-	rv = system_run_image_copy(slot);
-	CPRINTS("Failed to jump (%d)", rv);
-
-	return rv;
-}
-
-/* Request more power: charging battery or more powerful AC adapter */
-__overridable void show_power_shortage(void)
-{
-	CPRINTS("%s", __func__);
-}
-
-__overridable void show_critical_error(void)
-{
-	CPRINTS("%s", __func__);
-}
-
-static bool pd_comm_enabled;
-
-bool vboot_allow_usb_pd(void)
-{
-	return pd_comm_enabled;
-}
-
-void vboot_main(void)
-{
-	CPRINTS("Main");
-
-	if (system_is_in_rw()) {
-		/*
-		 * We come here and immediately return. LED shows power shortage
-		 * but it will be immediately corrected if the adapter can
-		 * provide enough power.
-		 */
-		CPRINTS("Already in RW. Wait for power...");
-		show_power_shortage();
-		return;
-	}
-
-	if (!(crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)) {
-		/*
-		 * If hardware WP is disabled, PD communication is enabled.
-		 * We can return and wait for more power.
-		 * Note: If software WP is disabled, we still perform EFS even
-		 * though PD communication is enabled.
-		 */
-		CPRINTS("HW-WP not asserted.");
-		show_power_shortage();
-		return;
-	}
-
-	if (system_is_manual_recovery() ||
-	    (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO)) {
-		if (system_is_manual_recovery())
-			CPRINTS("Manual recovery");
-
-		if (battery_is_present() || has_matrix_keyboard()) {
-			show_power_shortage();
-			return;
-		}
-		/* We don't request_power because we don't want to assume all
-		 * devices support a non type-c charger. We open up a security
-		 * hole by allowing EC-RO to do PD negotiation but attackers
-		 * don't gain meaningful advantage on devices without a matrix
-		 * keyboard */
-		CPRINTS("Enable PD comm");
-		pd_comm_enabled = true;
-		return;
-	}
-
-	clock_enable_module(MODULE_FAST_CPU, 1);
-	/* If successful, this won't return. */
-	verify_and_jump();
-	clock_enable_module(MODULE_FAST_CPU, 0);
-
-	/* Failed to jump. Need recovery. */
-	show_critical_error();
-}
diff --git a/common/vboot_hash.c b/common/vboot_hash.c
deleted file mode 100644
index 33172e7c74..0000000000
--- a/common/vboot_hash.c
+++ /dev/null
@@ -1,498 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Verified boot hash computing module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "sha256.h"
-#include "shared_mem.h"
-#include "stdbool.h"
-#include "stdint.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_VBOOT, outstr)
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
-
-struct vboot_hash_tag {
-	uint8_t hash[SHA256_DIGEST_SIZE];
-	uint32_t offset;
-	uint32_t size;
-};
-
-#define CHUNK_SIZE 1024       /* Bytes to hash per deferred call */
-#define WORK_INTERVAL_US 100  /* Delay between deferred calls */
-
-/* Check that CHUNK_SIZE fits in shared memory. */
-SHARED_MEM_CHECK_SIZE(CHUNK_SIZE);
-
-static uint32_t data_offset;
-static uint32_t data_size;
-static uint32_t curr_pos;
-static const uint8_t *hash;   /* Hash, or NULL if not valid */
-static int want_abort;
-static int in_progress;
-#define VBOOT_HASH_DEFERRED	true
-#define VBOOT_HASH_BLOCKING	false
-
-static struct sha256_ctx ctx;
-
-int vboot_hash_in_progress(void)
-{
-	return in_progress;
-}
-
-/**
- * Abort hash currently in progress, and invalidate any completed hash.
- */
-void vboot_hash_abort(void)
-{
-	if (in_progress) {
-		want_abort = 1;
-	} else {
-		CPRINTS("hash abort");
-		want_abort = 0;
-		data_size = 0;
-		hash = NULL;
-#ifdef CONFIG_SHA256_HW_ACCELERATE
-		SHA256_abort(&ctx);
-#endif
-	}
-}
-
-static void vboot_hash_next_chunk(void);
-DECLARE_DEFERRED(vboot_hash_next_chunk);
-
-#ifndef CONFIG_MAPPED_STORAGE
-
-static int read_and_hash_chunk(int offset, int size)
-{
-	char *buf;
-	int rv;
-
-	if (size == 0)
-		return EC_SUCCESS;
-
-	rv = shared_mem_acquire(size, &buf);
-	if (rv == EC_ERROR_BUSY) {
-		/* Couldn't update hash right now; try again later */
-		hook_call_deferred(&vboot_hash_next_chunk_data,
-				   WORK_INTERVAL_US);
-		return rv;
-	} else if (rv != EC_SUCCESS) {
-		vboot_hash_abort();
-		return rv;
-	}
-
-	rv = crec_flash_read(offset, size, buf);
-	if (rv == EC_SUCCESS)
-		SHA256_update(&ctx, (const uint8_t *)buf, size);
-	else
-		vboot_hash_abort();
-
-	shared_mem_release(buf);
-	return rv;
-}
-
-#endif
-
-#ifdef CONFIG_CONSOLE_VERBOSE
-#define SHA256_PRINT_SIZE SHA256_DIGEST_SIZE
-#else
-#define SHA256_PRINT_SIZE 4
-#endif
-
-static void hash_next_chunk(size_t size)
-{
-#ifdef CONFIG_MAPPED_STORAGE
-	crec_flash_lock_mapped_storage(1);
-	SHA256_update(&ctx, (const uint8_t *)
-				((uintptr_t)CONFIG_MAPPED_STORAGE_BASE +
-				 data_offset + curr_pos), size);
-	crec_flash_lock_mapped_storage(0);
-#else
-	if (read_and_hash_chunk(data_offset + curr_pos, size) != EC_SUCCESS)
-		return;
-#endif
-}
-
-static void vboot_hash_all_chunks(void)
-{
-	do {
-		size_t size = MIN(CHUNK_SIZE, data_size - curr_pos);
-		hash_next_chunk(size);
-		curr_pos += size;
-	} while (curr_pos < data_size);
-
-	hash = SHA256_final(&ctx);
-	CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
-	in_progress = 0;
-	clock_enable_module(MODULE_FAST_CPU, 0);
-
-	return;
-}
-
-/**
- * Do next chunk of hashing work, if any.
- */
-static void vboot_hash_next_chunk(void)
-{
-	int size;
-
-	/* Handle abort */
-	if (want_abort) {
-		in_progress = 0;
-		clock_enable_module(MODULE_FAST_CPU, 0);
-		vboot_hash_abort();
-		return;
-	}
-
-	/* Compute the next chunk of hash */
-	size = MIN(CHUNK_SIZE, data_size - curr_pos);
-	hash_next_chunk(size);
-
-	curr_pos += size;
-	if (curr_pos >= data_size) {
-		/* Store the final hash */
-		hash = SHA256_final(&ctx);
-		CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
-
-		in_progress = 0;
-
-		clock_enable_module(MODULE_FAST_CPU, 0);
-
-		/* Handle receiving abort during finalize */
-		if (want_abort)
-			vboot_hash_abort();
-
-		return;
-	}
-
-	/* If we're still here, more work to do; come back later */
-	hook_call_deferred(&vboot_hash_next_chunk_data, WORK_INTERVAL_US);
-}
-
-/**
- *
- * If nonce_size is non-zero, prefixes the <nonce> onto the data to be hashed.
- * Returns non-zero if error.
- */
-/**
- * Start computing a hash of <size> bytes of data at flash offset <offset>.
- *
- * @param offset	start address of data on flash to compute hash for.
- * @param size		size of data to compute hash for.
- * @param nonce		nonce to differentiate hash.
- * @param nonce_size	size of nonce.
- * @param deferred	True to hash progressively through deferred calls.
- * 			False to hash with a blocking single call.
- * @return		ec_error_list.
- */
-static int vboot_hash_start(uint32_t offset, uint32_t size,
-			    const uint8_t *nonce, int nonce_size, bool deferred)
-{
-	/* Fail if hash computation is already in progress */
-	if (in_progress)
-		return EC_ERROR_BUSY;
-
-	/*
-	 * Make sure request fits inside flash.  That is, you can't use this
-	 * command to peek at other memory.
-	 */
-	if (offset > CONFIG_FLASH_SIZE_BYTES ||
-	    size > CONFIG_FLASH_SIZE_BYTES ||
-	    offset + size > CONFIG_FLASH_SIZE_BYTES || nonce_size < 0) {
-		return EC_ERROR_INVAL;
-	}
-
-	clock_enable_module(MODULE_FAST_CPU, 1);
-	/* Save new hash request */
-	data_offset = offset;
-	data_size = size;
-	curr_pos = 0;
-	hash = NULL;
-	want_abort = 0;
-	in_progress = 1;
-
-	/* Restart the hash computation */
-	CPRINTS("hash start 0x%08x 0x%08x", offset, size);
-	SHA256_init(&ctx);
-	if (nonce_size)
-		SHA256_update(&ctx, nonce, nonce_size);
-
-	if (deferred)
-		hook_call_deferred(&vboot_hash_next_chunk_data, 0);
-	else
-		vboot_hash_all_chunks();
-
-	return EC_SUCCESS;
-}
-
-int vboot_hash_invalidate(int offset, int size)
-{
-	/* Don't invalidate if passed an invalid region */
-	if (offset < 0 || size <= 0 || offset + size < 0)
-		return 0;
-
-	/* Don't invalidate if hash is already invalid */
-	if (!hash)
-		return 0;
-
-	/*
-	 * Always invalidate zero-size hash. No overlap if passed region is off
-	 * either end of hashed region.
-	 */
-	if (data_size > 0 &&
-	    (offset + size <= data_offset || offset >= data_offset + data_size))
-		return 0;
-
-	/* Invalidate the hash */
-	CPRINTS("hash invalidated 0x%08x 0x%08x", offset, size);
-	vboot_hash_abort();
-	return 1;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-/**
- * Returns the size of a RW copy to be hashed as expected by Softsync.
- */
-static uint32_t get_rw_size(void)
-{
-#ifdef CONFIG_VBOOT_EFS		/* Only needed for EFS, which signs and verifies
-				 * entire RW, thus not needed for EFS2, which
-				 * verifies only the used image size. */
-	return CONFIG_RW_SIZE;
-#else
-	return system_get_image_used(EC_IMAGE_RW);
-#endif
-}
-
-static void vboot_hash_init(void)
-{
-#ifdef CONFIG_HOSTCMD_EVENTS
-	/*
-	 * Don't auto-start hash computation if we've asked the host to enter
-	 * recovery mode since we probably won't need the hash. Although
-	 * the host is capable of clearing this host event, the host is
-	 * likely not even up and running yet in the case of cold boot, due to
-	 * the power sequencing task not having run yet.
-	 */
-	if (!(host_get_events() &
-	      EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
-#endif
-	{
-		/* Start computing the hash of RW firmware */
-		vboot_hash_start(flash_get_rw_offset(system_get_active_copy()),
-				 get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, vboot_hash_init, HOOK_PRIO_INIT_VBOOT_HASH);
-
-int vboot_get_rw_hash(const uint8_t **dst)
-{
-	int rv = vboot_hash_start(flash_get_rw_offset(system_get_active_copy()),
-				  get_rw_size(), NULL, 0, VBOOT_HASH_BLOCKING);
-	*dst = hash;
-	return rv;
-}
-
-/**
- * Returns the offset of RO or RW image if the either region is specifically
- * requested otherwise return the current hash offset.
- */
-static int get_offset(int offset)
-{
-	if (offset == EC_VBOOT_HASH_OFFSET_RO)
-		return CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
-	if (offset == EC_VBOOT_HASH_OFFSET_ACTIVE)
-		return flash_get_rw_offset(system_get_active_copy());
-	if (offset == EC_VBOOT_HASH_OFFSET_UPDATE)
-		return flash_get_rw_offset(system_get_update_copy());
-	return offset;
-}
-
-/****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_HASH
-static int command_hash(int argc, char **argv)
-{
-	uint32_t offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-			  CONFIG_RW_STORAGE_OFF;
-	uint32_t size = CONFIG_RW_SIZE;
-	char *e;
-
-	if (argc == 1) {
-		ccprintf("Offset: 0x%08x\n", data_offset);
-		ccprintf("Size:   0x%08x (%d)\n", data_size, data_size);
-		ccprintf("Digest: ");
-		if (want_abort)
-			ccprintf("(aborting)\n");
-		else if (in_progress)
-			ccprintf("(in progress)\n");
-		else if (hash)
-			ccprintf("%ph\n", HEX_BUF(hash, SHA256_DIGEST_SIZE));
-		else
-			ccprintf("(invalid)\n");
-
-		return EC_SUCCESS;
-	}
-
-	if (argc == 2) {
-		if (!strcasecmp(argv[1], "abort")) {
-			vboot_hash_abort();
-			return EC_SUCCESS;
-		} else if (!strcasecmp(argv[1], "rw")) {
-			return vboot_hash_start(
-					get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE),
-					get_rw_size(),
-					NULL, 0, VBOOT_HASH_DEFERRED);
-		} else if (!strcasecmp(argv[1], "ro")) {
-			return vboot_hash_start(
-				CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF,
-				system_get_image_used(EC_IMAGE_RO),
-				NULL, 0, VBOOT_HASH_DEFERRED);
-		}
-		return EC_ERROR_PARAM2;
-	}
-
-	if (argc >= 3) {
-		offset = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		size = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	if (argc == 4) {
-		int nonce = strtoi(argv[3], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-
-		return vboot_hash_start(offset, size,
-					(const uint8_t *)&nonce,
-					sizeof(nonce), VBOOT_HASH_DEFERRED);
-	} else
-		return vboot_hash_start(offset, size,
-					NULL, 0, VBOOT_HASH_DEFERRED);
-}
-DECLARE_CONSOLE_COMMAND(hash, command_hash,
-			"[abort | ro | rw] | [<offset> <size> [<nonce>]]",
-			"Request hash recomputation");
-#endif /* CONFIG_CMD_HASH */
-/****************************************************************************/
-/* Host commands */
-
-/* Fill in the response with the current hash status */
-static void fill_response(struct ec_response_vboot_hash *r,
-			  int request_offset)
-{
-	if (in_progress)
-		r->status = EC_VBOOT_HASH_STATUS_BUSY;
-	else if (get_offset(request_offset) == data_offset && hash &&
-		 !want_abort) {
-		r->status = EC_VBOOT_HASH_STATUS_DONE;
-		r->hash_type = EC_VBOOT_HASH_TYPE_SHA256;
-		r->digest_size = SHA256_DIGEST_SIZE;
-		r->reserved0 = 0;
-		r->offset = data_offset;
-		r->size = data_size;
-		ASSERT(SHA256_DIGEST_SIZE < sizeof(r->hash_digest));
-		memcpy(r->hash_digest, hash, SHA256_DIGEST_SIZE);
-	} else
-		r->status = EC_VBOOT_HASH_STATUS_NONE;
-}
-
-/**
- * Start computing a hash, with validity checking on params.
- *
- * @return EC_RES_SUCCESS if success, or other result code on error.
- */
-static int host_start_hash(const struct ec_params_vboot_hash *p)
-{
-	int offset = p->offset;
-	int size = p->size;
-	int rv;
-
-	/* Validity-check input params */
-	if (p->hash_type != EC_VBOOT_HASH_TYPE_SHA256)
-		return EC_RES_INVALID_PARAM;
-	if (p->nonce_size > sizeof(p->nonce_data))
-		return EC_RES_INVALID_PARAM;
-
-	/* Handle special offset values */
-	if (offset == EC_VBOOT_HASH_OFFSET_RO)
-		size = system_get_image_used(EC_IMAGE_RO);
-	else if ((offset == EC_VBOOT_HASH_OFFSET_ACTIVE) ||
-			(offset == EC_VBOOT_HASH_OFFSET_UPDATE))
-		size = get_rw_size();
-	offset = get_offset(offset);
-	rv = vboot_hash_start(offset, size, p->nonce_data, p->nonce_size,
-			      VBOOT_HASH_DEFERRED);
-
-	if (rv == EC_SUCCESS)
-		return EC_RES_SUCCESS;
-	else if (rv == EC_ERROR_INVAL)
-		return EC_RES_INVALID_PARAM;
-	else
-		return EC_RES_ERROR;
-}
-
-static enum ec_status
-host_command_vboot_hash(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_vboot_hash *p = args->params;
-	struct ec_response_vboot_hash *r = args->response;
-	int rv;
-
-	switch (p->cmd) {
-	case EC_VBOOT_HASH_GET:
-		if (p->offset || p->size)
-			fill_response(r, p->offset);
-		else
-			fill_response(r, data_offset);
-
-		args->response_size = sizeof(*r);
-		return EC_RES_SUCCESS;
-
-	case EC_VBOOT_HASH_ABORT:
-		vboot_hash_abort();
-		return EC_RES_SUCCESS;
-
-	case EC_VBOOT_HASH_START:
-	case EC_VBOOT_HASH_RECALC:
-		rv = host_start_hash(p);
-		if (rv != EC_RES_SUCCESS)
-			return rv;
-
-		/* Wait for hash to finish if command is RECALC */
-		if (p->cmd == EC_VBOOT_HASH_RECALC)
-			while (in_progress)
-				usleep(1000);
-
-		fill_response(r, p->offset);
-		args->response_size = sizeof(*r);
-		return EC_RES_SUCCESS;
-
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-}
-DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH,
-		     host_command_vboot_hash,
-		     EC_VER_MASK(0));
diff --git a/common/virtual_battery.c b/common/virtual_battery.c
deleted file mode 100644
index 0f0167556c..0000000000
--- a/common/virtual_battery.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Virtual battery cross-platform code for Chrome EC */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "i2c.h"
-#include "system.h"
-#include "util.h"
-#include "virtual_battery.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define BATT_MODE_UNINITIALIZED -1
-
-/*
- * The state machine used to parse smart battery command
- * to support virtual battery.
- */
-enum batt_cmd_parse_state {
-	IDLE = 0, /* initial state */
-	START = 1, /* received the register address (command code) */
-	WRITE_VB, /* writing data bytes to the peripheral */
-	READ_VB, /* reading data bytes to the peripheral */
-};
-
-static enum batt_cmd_parse_state sb_cmd_state;
-static uint8_t cache_hit;
-static const uint8_t *batt_cmd_head;
-static int acc_write_len;
-
-int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
-				   int in_len, int *err_code, int xferflags,
-				   int read_len, int write_len,
-				   const uint8_t *out)
-{
-
-#if defined(CONFIG_BATTERY_PRESENT_GPIO) || \
-	defined(CONFIG_BATTERY_PRESENT_CUSTOM)
-	/*
-	 * If the battery isn't present, return a NAK (which we
-	 * would have gotten anyways had we attempted to talk to
-	 * the battery.)
-	 */
-	if (battery_is_present() != BP_YES) {
-		resp->i2c_status = EC_I2C_STATUS_NAK;
-		return EC_ERROR_INVAL;
-	}
-#endif
-	switch (sb_cmd_state) {
-	case IDLE:
-		/*
-		 * A legal battery command must start
-		 * with a i2c write for reg index.
-		 */
-		if (write_len == 0) {
-			resp->i2c_status = EC_I2C_STATUS_NAK;
-			return EC_ERROR_INVAL;
-		}
-		/* Record the head of battery command. */
-		batt_cmd_head = out;
-		sb_cmd_state = START;
-		*err_code = 0;
-		break;
-	case START:
-		if (write_len > 0) {
-			sb_cmd_state = WRITE_VB;
-			*err_code = 0;
-		} else {
-			sb_cmd_state = READ_VB;
-			*err_code = virtual_battery_operation(batt_cmd_head,
-						NULL, 0, 0);
-			/*
-			 * If the reg is not handled by virtual battery, we
-			 * do not support it.
-			 */
-			if (*err_code)
-				return EC_ERROR_INVAL;
-			cache_hit = 1;
-		}
-		break;
-	case WRITE_VB:
-		if (write_len == 0) {
-			resp->i2c_status = EC_I2C_STATUS_NAK;
-			reset_parse_state();
-			return EC_ERROR_INVAL;
-		}
-		*err_code = 0;
-		break;
-	case READ_VB:
-		if (read_len == 0) {
-			resp->i2c_status = EC_I2C_STATUS_NAK;
-			reset_parse_state();
-			return EC_ERROR_INVAL;
-		}
-		/*
-		 * Do not send the command to battery
-		 * if the reg is cached.
-		 */
-		if (cache_hit)
-			*err_code = 0;
-		break;
-	default:
-		reset_parse_state();
-		return EC_ERROR_INVAL;
-	}
-
-	acc_write_len += write_len;
-
-	/* the last message */
-	if (xferflags & I2C_XFER_STOP) {
-		switch (sb_cmd_state) {
-		/* write to virtual battery */
-		case START:
-		case WRITE_VB:
-			virtual_battery_operation(batt_cmd_head,
-						NULL,
-						0,
-						acc_write_len);
-			break;
-		/* read from virtual battery */
-		case READ_VB:
-			if (cache_hit) {
-				read_len += in_len;
-				memset(&resp->data[0], 0, read_len);
-				virtual_battery_operation(batt_cmd_head,
-							&resp->data[0],
-							read_len,
-							0);
-			}
-			break;
-		default:
-			reset_parse_state();
-			return EC_ERROR_INVAL;
-
-		}
-		/* Reset the state in the end of messages */
-		reset_parse_state();
-	}
-	return EC_RES_SUCCESS;
-}
-
-void reset_parse_state(void)
-{
-	sb_cmd_state = IDLE;
-	cache_hit = 0;
-	acc_write_len = 0;
-}
-
-/*
- * Copy memmap string data from offset to dest, up to size len, in the format
- * expected by SBS (first byte of dest contains strlen).
- */
-void copy_memmap_string(uint8_t *dest, int offset, int len)
-{
-	uint8_t *memmap_str;
-	uint8_t memmap_strlen;
-
-	if (len == 0)
-		return;
-	memmap_str = host_get_memmap(offset);
-	/* memmap_str might not be NULL terminated */
-	memmap_strlen = *(memmap_str + EC_MEMMAP_TEXT_MAX - 1) == '\0' ?
-			strlen(memmap_str) : EC_MEMMAP_TEXT_MAX;
-	dest[0] = memmap_strlen;
-	memcpy(dest + 1, memmap_str, MIN(memmap_strlen, len - 1));
-}
-
-int virtual_battery_operation(const uint8_t *batt_cmd_head,
-			      uint8_t *dest,
-			      int read_len,
-			      int write_len)
-{
-	int val;
-	int year, month, day;
-	/*
-	 * We cache battery operational mode locally for both read and write
-	 * commands. If MODE_CAPACITY bit is set, battery capacity will be
-	 * reported in 10mW/10mWh, instead of the default unit, mA/mAh.
-	 * Note that we don't update the cached capacity: We do a real-time
-	 * conversion and return the converted values.
-	 */
-	static int batt_mode_cache = BATT_MODE_UNINITIALIZED;
-	const struct batt_params *curr_batt;
-	/*
-	 * Don't allow host reads into arbitrary memory space, most params
-	 * are two bytes.
-	 */
-	int bounded_read_len = MIN(read_len, 2);
-
-	curr_batt = charger_current_battery_params();
-	switch (*batt_cmd_head) {
-	case SB_BATTERY_MODE:
-		if (write_len == 3) {
-			batt_mode_cache = batt_cmd_head[1] |
-					  (batt_cmd_head[2] << 8);
-		} else if (read_len > 0) {
-			if (batt_mode_cache == BATT_MODE_UNINITIALIZED)
-				/*
-				 * Read the battery operational mode from
-				 * the battery to initialize batt_mode_cache.
-				 * This may cause an i2c transaction.
-				 */
-				if (battery_get_mode(&batt_mode_cache) ==
-				    EC_ERROR_UNIMPLEMENTED)
-					/*
-					 * Register not supported, choose
-					 * typical SB defaults.
-					 */
-					batt_mode_cache =
-					   MODE_INTERNAL_CHARGE_CONTROLLER |
-					   MODE_ALARM |
-					   MODE_CHARGER;
-
-			memcpy(dest, &batt_mode_cache, bounded_read_len);
-		}
-		break;
-	case SB_SERIAL_NUMBER:
-		val = strtoi(host_get_memmap(EC_MEMMAP_BATT_SERIAL), NULL, 16);
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_VOLTAGE:
-		if (curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
-			return EC_ERROR_BUSY;
-		memcpy(dest, &(curr_batt->voltage), bounded_read_len);
-		break;
-	case SB_RELATIVE_STATE_OF_CHARGE:
-		if (curr_batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
-			return EC_ERROR_BUSY;
-		memcpy(dest, &(curr_batt->state_of_charge), bounded_read_len);
-		break;
-	case SB_TEMPERATURE:
-		if (curr_batt->flags & BATT_FLAG_BAD_TEMPERATURE)
-			return EC_ERROR_BUSY;
-		memcpy(dest, &(curr_batt->temperature), bounded_read_len);
-		break;
-	case SB_CURRENT:
-		if (curr_batt->flags & BATT_FLAG_BAD_CURRENT)
-			return EC_ERROR_BUSY;
-		memcpy(dest, &(curr_batt->current), bounded_read_len);
-		break;
-	case SB_AVERAGE_CURRENT:
-		/* This may cause an i2c transaction */
-		if (curr_batt->flags & BATT_FLAG_BAD_AVERAGE_CURRENT)
-			return EC_ERROR_BUSY;
-		val = battery_get_avg_current();
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_MAX_ERROR:
-		/* report as 3% to make kernel happy */
-		val = BATTERY_LEVEL_SHUTDOWN;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_FULL_CHARGE_CAPACITY:
-		if (curr_batt->flags & BATT_FLAG_BAD_FULL_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
-			return EC_ERROR_BUSY;
-		val = curr_batt->full_capacity;
-		if (batt_mode_cache & MODE_CAPACITY)
-			val = val * curr_batt->voltage / 10000;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_BATTERY_STATUS:
-		if (curr_batt->flags & BATT_FLAG_BAD_STATUS)
-			return EC_ERROR_BUSY;
-		memcpy(dest, &(curr_batt->status), bounded_read_len);
-		break;
-	case SB_CYCLE_COUNT:
-		memcpy(dest, (int *)host_get_memmap(EC_MEMMAP_BATT_CCNT),
-		       bounded_read_len);
-		break;
-	case SB_DESIGN_CAPACITY:
-		if (curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
-			return EC_ERROR_BUSY;
-		val = *(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
-		if (batt_mode_cache & MODE_CAPACITY)
-			val = val * curr_batt->voltage / 10000;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_DESIGN_VOLTAGE:
-		memcpy(dest, (int *)host_get_memmap(EC_MEMMAP_BATT_DVLT),
-		       bounded_read_len);
-		break;
-	case SB_REMAINING_CAPACITY:
-		if (curr_batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
-			return EC_ERROR_BUSY;
-		val = curr_batt->remaining_capacity;
-		if (batt_mode_cache & MODE_CAPACITY)
-			val = val * curr_batt->voltage / 10000;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_MANUFACTURER_NAME:
-		copy_memmap_string(dest, EC_MEMMAP_BATT_MFGR, read_len);
-		break;
-	case SB_DEVICE_NAME:
-		copy_memmap_string(dest, EC_MEMMAP_BATT_MODEL, read_len);
-		break;
-	case SB_DEVICE_CHEMISTRY:
-		copy_memmap_string(dest, EC_MEMMAP_BATT_TYPE, read_len);
-		break;
-	case SB_AVERAGE_TIME_TO_FULL:
-		/* This may cause an i2c transaction */
-		if (battery_time_to_full(&val))
-			return EC_ERROR_INVAL;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_AVERAGE_TIME_TO_EMPTY:
-		/* This may cause an i2c transaction */
-		if (battery_time_to_empty(&val))
-			return EC_ERROR_INVAL;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_CHARGING_CURRENT:
-		if (curr_batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT)
-			return EC_ERROR_BUSY;
-		val = curr_batt->desired_current;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_CHARGING_VOLTAGE:
-		if (curr_batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE)
-			return EC_ERROR_BUSY;
-		val = curr_batt->desired_voltage;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_MANUFACTURE_DATE:
-		/* This may cause an i2c transaction */
-		if (!battery_manufacture_date(&year, &month, &day)) {
-			/* Encode in Smart Battery Spec format */
-			val = ((year - 1980) << 9) + (month << 5) + day;
-		} else {
-			/*
-			 * Return 0 on error. The kernel is unhappy with
-			 * returning an error code.
-			 */
-			val = 0;
-		}
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	case SB_MANUFACTURER_ACCESS:
-		/* No manuf. access reg access allowed over VB interface */
-		return EC_ERROR_INVAL;
-	case SB_SPECIFICATION_INFO:
-		/* v1.1 without PEC, no scale factor to voltage and current */
-		val = 0x0011;
-		memcpy(dest, &val, bounded_read_len);
-		break;
-	default:
-		CPRINTS("Unhandled VB reg %x", *batt_cmd_head);
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
-
diff --git a/common/vstore.c b/common/vstore.c
deleted file mode 100644
index 9b4636397c..0000000000
--- a/common/vstore.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Temporary secure storage commands for use by the host for verified boot
- * related activities such as storing the hash of verified firmware for use
- * in suspend/resume.
- *
- * There are a configurable number of vstore slots, with all slots having
- * the same size of EC_VSTORE_SLOT_SIZE (64 bytes).
- *
- * Slots can be written once per AP power-on and will then be locked and
- * cannot be written again until it is cleared in the CHIPSET_SHUTDOWN
- * or CHIPSET_RESET hooks.
- */
-
-#include "common.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "util.h"
-
-#define VSTORE_SYSJUMP_TAG  0x5653 /* "VS" */
-#define VSTORE_HOOK_VERSION 1
-
-struct vstore_slot {
-	uint8_t locked;
-	uint8_t data[EC_VSTORE_SLOT_SIZE];
-};
-
-static struct vstore_slot vstore_slots[CONFIG_VSTORE_SLOT_COUNT];
-static const int vstore_size =
-		sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT;
-BUILD_ASSERT(ARRAY_SIZE(vstore_slots) <= EC_VSTORE_SLOT_MAX);
-
-/*
- * vstore_info - Get slot count and mask of locked slots.
- */
-static enum ec_status vstore_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_vstore_info *r = args->response;
-	int i;
-
-	r->slot_count = CONFIG_VSTORE_SLOT_COUNT;
-	r->slot_locked = 0;
-	for (i = 0; i < CONFIG_VSTORE_SLOT_COUNT; i++)
-		if (vstore_slots[i].locked)
-			r->slot_locked |= 1 << i;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_VSTORE_INFO, vstore_info, EC_VER_MASK(0));
-
-/*
- * vstore_read - Read slot from temporary secure storage.
- *
- * Response is EC_VSTORE_SLOT_SIZE bytes of data.
- */
-static enum ec_status vstore_read(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_vstore_read *p = args->params;
-	struct ec_response_vstore_read *r = args->response;
-
-	if (p->slot >= CONFIG_VSTORE_SLOT_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	memcpy(r->data, vstore_slots[p->slot].data, EC_VSTORE_SLOT_SIZE);
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_VSTORE_READ, vstore_read, EC_VER_MASK(0));
-
-/*
- * vstore_write - Write temporary secure storage slot and lock it.
- */
-static enum ec_status vstore_write(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_vstore_write *p = args->params;
-	struct vstore_slot *slot;
-
-	if (p->slot >= CONFIG_VSTORE_SLOT_COUNT)
-		return EC_RES_INVALID_PARAM;
-	slot = &vstore_slots[p->slot];
-
-	if (slot->locked)
-		return EC_RES_ACCESS_DENIED;
-	slot->locked = 1;
-	memcpy(slot->data, p->data, EC_VSTORE_SLOT_SIZE);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_VSTORE_WRITE, vstore_write, EC_VER_MASK(0));
-
-static void vstore_clear_lock(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_VSTORE_SLOT_COUNT; i++)
-		vstore_slots[i].locked = 0;
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, vstore_clear_lock, HOOK_PRIO_DEFAULT);
-
-static void vstore_preserve_state(void)
-{
-	system_add_jump_tag(VSTORE_SYSJUMP_TAG, VSTORE_HOOK_VERSION,
-			    vstore_size, vstore_slots);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, vstore_preserve_state, HOOK_PRIO_DEFAULT);
-
-static void vstore_init(void)
-{
-	const struct vstore_slot *prev;
-	int version, size;
-
-	prev = (const struct vstore_slot *)system_get_jump_tag(
-		VSTORE_SYSJUMP_TAG, &version, &size);
-
-	if (prev && version == VSTORE_HOOK_VERSION && size == vstore_size)
-		memcpy(vstore_slots, prev, vstore_size);
-}
-DECLARE_HOOK(HOOK_INIT, vstore_init, HOOK_PRIO_DEFAULT);
diff --git a/common/webusb_desc.c b/common/webusb_desc.c
deleted file mode 100644
index 41d39006e0..0000000000
--- a/common/webusb_desc.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* WebUSB platform descriptor */
-
-#include "common.h"
-#include "usb_descriptor.h"
-#include "util.h"
-
-#ifndef CONFIG_USB_BOS
-#error "CONFIG_USB_BOS must be defined to use WebUSB descriptor"
-#endif
-
-const void *webusb_url = USB_URL_DESC(HTTPS, CONFIG_WEBUSB_URL);
-
-/*
- * Platform Descriptor in the device Binary Object Store
- * as defined by USB 3.1 spec chapter 9.6.2.
- */
-static struct {
-	struct usb_bos_hdr_descriptor bos;
-	struct usb_platform_descriptor platform;
-} bos_desc = {
-	.bos = {
-		.bLength = USB_DT_BOS_SIZE,
-		.bDescriptorType = USB_DT_BOS,
-		.wTotalLength = (USB_DT_BOS_SIZE + USB_DT_PLATFORM_SIZE),
-		.bNumDeviceCaps = 1,  /* platform caps */
-	},
-	.platform = {
-		.bLength = USB_DT_PLATFORM_SIZE,
-		.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_DC_DTYPE_PLATFORM,
-		.bReserved = 0,
-		.PlatformCapUUID = USB_PLAT_CAP_WEBUSB,
-		.bcdVersion = 0x0100,
-		.bVendorCode = 0x01,
-		.iLandingPage = 1,
-	},
-};
-
-const struct bos_context bos_ctx = {
-	.descp = (void *)&bos_desc,
-	.size = sizeof(bos_desc),
-};
diff --git a/common/wireless.c b/common/wireless.c
deleted file mode 100644
index d1f5cad645..0000000000
--- a/common/wireless.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wireless power management */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "util.h"
-#include "wireless.h"
-
-/* Unless told otherwise, disable wireless in suspend */
-#ifndef CONFIG_WIRELESS_SUSPEND
-#define CONFIG_WIRELESS_SUSPEND 0
-#endif
-
-/*
- * Flags which will be left on when suspending.  Other flags will be disabled
- * when suspending.
- */
-static int suspend_flags = CONFIG_WIRELESS_SUSPEND;
-
-/**
- * Set wireless switch state.
- *
- * @param flags		Enable flags from ec_commands.h (EC_WIRELESS_SWITCH_*),
- *			0 to turn all wireless off, or -1 to turn all wireless
- *			on.
- * @param mask		Which of those flags to set
- */
-static void wireless_enable(int flags)
-{
-#ifdef WIRELESS_GPIO_WLAN
-	gpio_set_level(WIRELESS_GPIO_WLAN,
-		       flags & EC_WIRELESS_SWITCH_WLAN);
-#endif
-
-#ifdef WIRELESS_GPIO_WWAN
-	gpio_set_level(WIRELESS_GPIO_WWAN,
-		       flags & EC_WIRELESS_SWITCH_WWAN);
-#endif
-
-#ifdef WIRELESS_GPIO_BLUETOOTH
-	gpio_set_level(WIRELESS_GPIO_BLUETOOTH,
-		       flags & EC_WIRELESS_SWITCH_BLUETOOTH);
-#endif
-
-#ifdef WIRELESS_GPIO_WLAN_POWER
-#ifndef CONFIG_WLAN_POWER_ACTIVE_LOW
-	gpio_set_level(WIRELESS_GPIO_WLAN_POWER,
-		       flags & EC_WIRELESS_SWITCH_WLAN_POWER);
-#else
-	gpio_set_level(WIRELESS_GPIO_WLAN_POWER,
-		       !(flags & EC_WIRELESS_SWITCH_WLAN_POWER));
-#endif /* CONFIG_WLAN_POWER_ACTIVE_LOW */
-#endif
-
-}
-
-static int wireless_get(void)
-{
-	int flags = 0;
-
-#ifdef WIRELESS_GPIO_WLAN
-	if (gpio_get_level(WIRELESS_GPIO_WLAN))
-		flags |= EC_WIRELESS_SWITCH_WLAN;
-#endif
-
-#ifdef WIRELESS_GPIO_WWAN
-	if (gpio_get_level(WIRELESS_GPIO_WWAN))
-		flags |= EC_WIRELESS_SWITCH_WWAN;
-#endif
-
-#ifdef WIRELESS_GPIO_BLUETOOTH
-	if (gpio_get_level(WIRELESS_GPIO_BLUETOOTH))
-		flags |= EC_WIRELESS_SWITCH_BLUETOOTH;
-#endif
-
-#ifdef WIRELESS_GPIO_WLAN_POWER
-#ifndef CONFIG_WLAN_POWER_ACTIVE_LOW
-	if (gpio_get_level(WIRELESS_GPIO_WLAN_POWER))
-#else
-	if (!gpio_get_level(WIRELESS_GPIO_WLAN_POWER))
-#endif /* CONFIG_WLAN_POWER_ACTIVE_LOW */
-		flags |= EC_WIRELESS_SWITCH_WLAN_POWER;
-#endif
-
-	return flags;
-}
-
-void wireless_set_state(enum wireless_power_state state)
-{
-	switch (state) {
-	case WIRELESS_OFF:
-		wireless_enable(0);
-		break;
-	case WIRELESS_SUSPEND:
-		/*
-		 * When suspending, only turn things off.  If the AP has
-		 * disabled WiFi power, going into S3 should not re-enable it.
-		 */
-		wireless_enable(wireless_get() & suspend_flags);
-		break;
-	case WIRELESS_ON:
-		wireless_enable(EC_WIRELESS_SWITCH_ALL);
-		break;
-	}
-}
-
-static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_switch_enable_wireless_v1 *p = args->params;
-	struct ec_response_switch_enable_wireless_v1 *r = args->response;
-
-	if (args->version == 0) {
-		/* Ver.0 command just set all current flags */
-		wireless_enable(p->now_flags);
-		return EC_RES_SUCCESS;
-	}
-
-	/* Ver.1 can set flags based on mask */
-	wireless_enable((wireless_get() & ~p->now_mask) |
-			(p->now_flags & p->now_mask));
-
-	suspend_flags = (suspend_flags & ~p->suspend_mask) |
-		(p->suspend_flags & p->suspend_mask);
-
-	/* And return the current flags */
-	r->now_flags = wireless_get();
-	r->suspend_flags = suspend_flags;
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS,
-		     wireless_enable_cmd,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-static int command_wireless(int argc, char **argv)
-{
-	char *e;
-	int i;
-
-	if (argc >= 2) {
-		i = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		wireless_enable(i);
-	}
-
-	if (argc >= 3) {
-		i = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		suspend_flags = i;
-	}
-
-	ccprintf("Wireless flags: now=0x%x, suspend=0x%x\n", wireless_get(),
-		 suspend_flags);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(wireless, command_wireless,
-			"[now [suspend]]",
-			"Get/set wireless flags");
diff --git a/core/cortex-m/aes.S b/core/cortex-m/aes.S
deleted file mode 120000
index 39d1286943..0000000000
--- a/core/cortex-m/aes.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/boringssl/core/cortex-m/aes.S
\ No newline at end of file
diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h
deleted file mode 100644
index e9b96f6fd5..0000000000
--- a/core/cortex-m/atomic.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atomic operations for ARMv7 */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include "common.h"
-
-typedef int atomic_t;
-typedef atomic_t atomic_val_t;
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_clear(atomic_t *addr)
-{
-	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
-}
-
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
deleted file mode 100644
index ad7ab6eacc..0000000000
--- a/core/cortex-m/build.mk
+++ /dev/null
@@ -1,34 +0,0 @@
-# -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Cortex-M4 core OS files build
-#
-
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
-# FPU compilation flags
-CFLAGS_FPU-$(CONFIG_FPU)=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
-
-# CPU specific compilation flags
-CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog
-CFLAGS_CPU+=-mno-unaligned-access
-CFLAGS_CPU+=$(CFLAGS_FPU-y)
-
-ifneq ($(CONFIG_LTO),)
-CFLAGS_CPU+=-flto
-LDFLAGS_EXTRA+=-flto
-endif
-
-core-y=cpu.o debug.o init.o ldivmod.o llsr.o uldivmod.o vecttable.o
-core-$(CONFIG_AES)+=aes.o
-core-$(CONFIG_AES_GCM)+=ghash.o
-core-$(CONFIG_ARMV7M_CACHE)+=cache.o
-core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
-core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
-core-$(CONFIG_WATCHDOG)+=watchdog.o
-core-$(CONFIG_MPU)+=mpu.o
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S
deleted file mode 100644
index 0a3d3bb67d..0000000000
--- a/core/cortex-m/cache.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ARMv7-M architectural caches maintenance operations.
- */
-
-.syntax unified
-.text
-.thumb
-
-/* System Control Block: cache registers */
-#define SCB_CCSIDR 0xe000ed80
-#define SCB_CCSELR 0xe000ed84
-#define SCB_DCISW  0xe000ef60
-#define SCB_DCCISW 0xe000ef74
-
-.macro dcache_set_way_op name register
-@
-@ Perform an operation on all D-cache sets/ways.
-@
-@ Note: implemented in assembly to guarantee that we are not touching the
-@ D-cache in the middle of the loop.
-@
-.thumb_func
-.section .text.\name
-.global \name
-\name:
-	/* Select Level-1 Data cache (for operations on CCSIDR). */
-	ldr  r1, =SCB_CCSELR
-	movs r0, #0
-	ldr  r2, =SCB_CCSIDR
-	str  r0, [r1]  /* set CCSELR = 0 */
-
-	/* Ensure the CCSELR write is effective before reading CCSIDR. */
-	dsb
-	/* CCSIDR contains the cache geometry. */
-	ldr  r3, [r2]  /* [27:13] Number of sets -1  [12:3] Number of ways -1 */
-
-	/* register used to do the set/way cache operation. */
-	ldr  r0, =\register
-	/* r2 is the number of cache 'sets' - 1 */
-	ubfx r2, r3, #13, #15
-	/* r12 is the number of cache 'ways' - 1 */
-	ubfx r12, r3, #3, #10
-
-1:
-	mov  r1, r12    /* reset way index */
-2:
-	/*
-	 * Build address Set/Way operation e.g DC(C)ISW
-	 * [31:30] way index [13:5] set index
-	 */
-	lsls r3, r2, #5 /* set index */
-	/* TODO(crbug.com/848704) remove cache geometry assumptions */
-	orr  r3, r3, r1, lsl #30 /* way index */
-	/* Perform operation (e.g invalidate) on a D-cache line */
-	str  r3, [r0]
-	/* go to previous way */
-	subs r1, #1
-	bcs  2b
-	/* go to previous set */
-	subs r2, #1
-	bcs  1b
-
-	/* Ensure everything has propagated and return. */
-	dsb
-	isb
-	bx  lr
-.endm
-
-/* D-cache Invalidate by set-way */
-dcache_set_way_op cpu_invalidate_dcache SCB_DCISW
-
-/* D-cache Clean and Invalidate by set-way, to Point of Coherency */
-dcache_set_way_op cpu_clean_invalidate_dcache SCB_DCCISW
diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h
deleted file mode 100644
index 0665b28852..0000000000
--- a/core/cortex-m/config_core.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CORE_H
-#define __CROS_EC_CONFIG_CORE_H
-
-/* Linker binary architecture and format */
-#define BFD_ARCH arm
-#define BFD_FORMAT "elf32-littlearm"
-
-#define CONFIG_SOFTWARE_PANIC
-
-#endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c
deleted file mode 100644
index 7c31892c18..0000000000
--- a/core/cortex-m/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Set up the Cortex-M core
- */
-
-#include "common.h"
-#include "cpu.h"
-#include "hooks.h"
-
-void cpu_init(void)
-{
-	/* Catch divide by 0 and unaligned access */
-	CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP;
-
-	/* Enable reporting of memory faults, bus faults and usage faults */
-	CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
-		CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
-}
-
-#ifdef CONFIG_ARMV7M_CACHE
-static void cpu_invalidate_icache(void)
-{
-	/*
-	 * Invalidates the entire instruction cache to the point of
-	 * unification.
-	 */
-	CPU_SCB_ICIALLU = 0;
-	asm volatile("dsb; isb");
-}
-
-void cpu_enable_caches(void)
-{
-	/* Check whether the I-cache is already enabled */
-	if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_ICACHE)) {
-		/* Invalidate the I-cache first */
-		cpu_invalidate_icache();
-		/* Turn on the caching */
-		CPU_NVIC_CCR |= CPU_NVIC_CCR_ICACHE;
-		asm volatile("dsb; isb");
-	}
-	/* Check whether the D-cache is already enabled */
-	if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_DCACHE)) {
-		/* Invalidate the D-cache first */
-		cpu_invalidate_dcache();
-		/* Turn on the caching */
-		CPU_NVIC_CCR |= CPU_NVIC_CCR_DCACHE;
-		asm volatile("dsb; isb");
-	}
-}
-
-void cpu_disable_caches(void)
-{
-	/*
-	 * Disable the I-cache and the D-cache
-	 * The I-cache will be invalidated after the reboot/sysjump if needed
-	 * (e.g after a flash update).
-	 */
-	cpu_clean_invalidate_dcache();
-	CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE);
-	asm volatile("dsb; isb");
-}
-DECLARE_HOOK(HOOK_SYSJUMP, cpu_disable_caches, HOOK_PRIO_LAST);
-#endif /* CONFIG_ARMV7M_CACHE */
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
deleted file mode 100644
index 0b03302bfc..0000000000
--- a/core/cortex-m/cpu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for Cortex-MLM4x processor
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-#include <stdint.h>
-#include "compile_time_macros.h"
-
-/* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
-
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
-
-/* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
-/* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
-/* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
-/* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
-
-enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
-
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
-
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
-
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
-};
-
-/* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
-
-/* Set up the cpu to detect faults */
-void cpu_init(void);
-/* Enable the CPU I-cache and D-cache if they are not already enabled */
-void cpu_enable_caches(void);
-/* Disable the CPU I-cache and D-cache */
-void cpu_disable_caches(void);
-/* Invalidate the D-cache */
-void cpu_invalidate_dcache(void);
-/* Clean and Invalidate the D-cache to the Point of Coherency */
-void cpu_clean_invalidate_dcache(void);
-
-/* Invalidate a single range of the D-cache */
-void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length);
-/* Clean and Invalidate a single range of the D-cache */
-void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length);
-
-/* Set the priority of the given IRQ in the NVIC (0 is highest). */
-static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
-{
-	const uint32_t prio_shift = irq % 4 * 8 + 5;
-
-	if (priority > 7)
-		priority = 7;
-
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
-}
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c
deleted file mode 100644
index db8891b5d8..0000000000
--- a/core/cortex-m/debug.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "debug.h"
-#include "stdbool.h"
-
-bool debugger_is_connected(void)
-{
-	return CPU_DHCSR & DHCSR_C_DEBUGEN;
-}
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
deleted file mode 100644
index ae5ef08d06..0000000000
--- a/core/cortex-m/debug.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
-
-#include "common.h"
-#include "stdbool.h"
-
-/* For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR"
- * in the ARMv6-M Architecture Reference Manual.
- *
- * For other Cortex-M, see
- * "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M
- * Architecture Reference Manual or
- * https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register.
- */
-#define CPU_DHCSR REG32(0xE000EDF0)
-#define DHCSR_C_DEBUGEN BIT(0)
-#define DHCSR_C_HALT BIT(1)
-#define DHCSR_C_STEP BIT(2)
-#define DHCSR_C_MASKINTS BIT(3)
-#ifndef CHIP_CORE_CORTEX_M0
-#define DHCSR_C_SNAPSTALL BIT(5) /* Not available on Cortex-M0 */
-#endif
-#define DHCSR_S_REGRDY BIT(16)
-#define DHCSR_S_HALT BIT(17)
-#define DHCSR_S_SLEEP BIT(18)
-#define DHCSR_S_LOCKUP BIT(19)
-#define DHCSR_S_RETIRE_ST BIT(24)
-#define DHCSR_S_RESET_ST BIT(25)
-
-bool debugger_is_connected(void);
-
-#endif /* __CROS_EC_DEBUG_H */
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
deleted file mode 100644
index 7b08be81a6..0000000000
--- a/core/cortex-m/ec.lds.S
+++ /dev/null
@@ -1,721 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "rwsig.h"
-
-#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z
-#define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , )
-#define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, )
-#define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z)
-
-#define STRINGIFY0(name) #name
-#define STRINGIFY(name) STRINGIFY0(name)
-
-#ifdef RW_B_LDS
-#define FW_MEM_OFF_(section) CONFIG_##section##_B_MEM_OFF
-#else
-#define FW_MEM_OFF_(section) CONFIG_##section##_MEM_OFF
-#endif
-#define FW_MEM_OFF(section) (FW_MEM_OFF_(section))
-#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(section))
-
-#define FW_SIZE_(section) CONFIG_##section##_SIZE
-#define FW_SIZE(section) FW_SIZE_(section)
-
-/*
- * Define the VMA (virtual memory address) of the ROM_RESIDENT region within
- * the EC image. This is full 32-bit address starting from
- * CONFIG_PROGRAM_MEMORY_BASE.
- */
-#define ROM_RES_OFF(section) FW_OFF(CONCAT2(section, _ROM_RESIDENT))
-#define ROM_RES_SIZE(section) FW_SIZE(CONCAT2(section, _ROM_RESIDENT))
-
-/*
- * Define the VMA (virtual memory address) of the ROM_RESIDENT region.  Instead
- * of a full 32-bit address, set the VMA to be an offset within the flash memory
- * section.  Objects linked into this section can pass the address of the
- * object unmodified to the public APIs of the flash and init_rom modules.
- */
-#ifdef SECTION_IS_RO
-#define ROM_RES_FLASH_OFF(section) \
-	FW_MEM_OFF(CONCAT2(section, _ROM_RESIDENT)) + \
-	CONFIG_EC_PROTECTED_STORAGE_OFF
-#else
-#define ROM_RES_FLASH_OFF(section) \
-	FW_MEM_OFF(CONCAT2(section, _ROM_RESIDENT)) + \
-	CONFIG_EC_WRITABLE_STORAGE_OFF
-#endif
-
-/* Indicates where .data LMA should reside. */
-#undef DATA_LMA_MEM_REGION
-
-OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
-OUTPUT_ARCH(BFD_ARCH)
-ENTRY(reset)
-
-MEMORY
-{
-#if !defined(CONFIG_FLASH_PHYSICAL)
-	IROM (rx) : ORIGIN = CONFIG_ROM_BASE, LENGTH = CONFIG_ROM_SIZE
-#else
-#if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER)
-	/*
-	 * Header structure used by npcx booter in RO region.
-	 * Please notice the location of header must be in front of FW
-	 * which needs copy. But header itself won't be copied to code ram
-	 * by booter.
-	 */
-	FLASH_HDR (rx) : ORIGIN = FW_OFF(RO_HDR), LENGTH = FW_SIZE(RO_HDR)
-	FLASH (rx) : ORIGIN = FW_OFF(SECTION) + FW_SIZE(RO_HDR), \
-		     LENGTH = FW_SIZE(SECTION) - FW_SIZE(RO_HDR)
-#else
-	FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
-#endif
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-	ROM_RESIDENT (r) : \
-		ORIGIN = ROM_RES_OFF(SECTION), \
-		LENGTH = ROM_RES_SIZE(SECTION)
-
-	ROM_RESIDENT_VMA (r) : \
-		ORIGIN = ROM_RES_FLASH_OFF(SECTION), \
-		LENGTH = ROM_RES_SIZE(SECTION)
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-#ifdef CONFIG_SHAREDLIB
-	SHARED_LIB (rx) : ORIGIN = FW_OFF(SHAREDLIB), \
-			  LENGTH = FW_SIZE(SHAREDLIB)
-#endif
-#endif /* !CONFIG_FLASH_PHYSICAL */
-	IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-
-#ifdef CONFIG_EXTERNAL_STORAGE
-	CDRAM (rx) : \
-		ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(SECTION), \
-		LENGTH = FW_SIZE(SECTION)
-#endif /* CONFIG_EXTERNAL_STORAGE */
-
-#ifdef CONFIG_CHIP_MEMORY_REGIONS
-#define REGION(name, attr, start, size) \
-	name(attr) : ORIGIN = (start), LENGTH = (size)
-#define REGION_LOAD REGION
-#include "memory_regions.inc"
-#undef REGION
-#undef REGION_LOAD
-#endif /* CONFIG_MEMORY_REGIONS */
-
-#ifdef CONFIG_DRAM_BASE
-	DRAM (rwx) : ORIGIN = CONFIG_DRAM_BASE, LENGTH = CONFIG_DRAM_SIZE
-#endif
-}
-
-/*
- * Convenience macros for determining the correct output memory section.
- */
-#if !defined(CONFIG_FLASH_PHYSICAL)
-	#define EC_IMAGE_LMA_MEM_REGION		IROM
-	#define EC_IMAGE_VMA_MEM_REGION		IROM
-	#define DATA_LMA_MEM_REGION		IROM
-#else
-	#define EC_IMAGE_LMA_MEM_REGION		FLASH
-	#ifdef CONFIG_EXTERNAL_STORAGE
-		#define EC_IMAGE_VMA_MEM_REGION	CDRAM
-	#else
-		#define EC_IMAGE_VMA_MEM_REGION	FLASH
-	#endif
-
-	#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
-		#define DATA_LMA_MEM_REGION	ROM_RESIDENT
-	#else
-		#define DATA_LMA_MEM_REGION	FLASH
-	#endif
-#endif
-
-SECTIONS
-{
-#if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER)
-	.header : {
-		KEEP(*(.header))
-	} > FLASH_HDR
-#endif
-#ifdef CONFIG_SHAREDLIB
-	.roshared : {
-		KEEP(*(.roshared*))
-	} > SHARED_LIB
-#endif
-	.text : {
-#ifdef SECTION_IS_RO
-		. = . +  CONFIG_RO_HEAD_ROOM;
-#endif
-#ifdef SECTION_IS_RW
-		. = . +  CONFIG_RW_HEAD_ROOM;
-#endif
-		*(.text.vecttable)
-		. = ALIGN(4);
-		__image_data_offset = .;
-		KEEP(*(.rodata.ver))
-
-		. = ALIGN(4);
-		KEEP(*(.rodata.pstate))
-
-		. = ALIGN(4);
-		STRINGIFY(OUTDIR/core/CORE/init.o) (.text)
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 && !defined(CONFIG_HIBERNATE_PSL)
-		/* Keep hibernate utility in last code ram block */
-		. = ALIGN(4);
-		KEEP(*(.after_init))
-		__after_init_end = .;
-#endif
-		*(.text*)
-#ifdef CONFIG_EXTERNAL_STORAGE
-		. = ALIGN(4);
-		__flash_lpfw_start = .;
-		/* Entering deep idle FW for better power consumption */
-		KEEP(*(.lowpower_ram))
-		. = ALIGN(4);
-		__flash_lpfw_end = .;
-		__flash_lplfw_start = .;
-		/* GDMA utilities for better FW download speed */
-		KEEP(*(.lowpower_ram2))
-		. = ALIGN(4);
-		__flash_lplfw_end = .;
-#endif /* CONFIG_EXTERNAL_STORAGE */
-	} > EC_IMAGE_VMA_MEM_REGION AT > EC_IMAGE_LMA_MEM_REGION
-
-	. = ALIGN(4);
-	.rodata : {
-		/* Symbols defined here are declared in link_defs.h */
-		__irqprio = .;
-		KEEP(*(.rodata.irqprio))
-		__irqprio_end = .;
-
-		. = ALIGN(4);
-		__cmds = .;
-		KEEP(*(SORT(.rodata.cmds*)))
-		__cmds_end = .;
-
-		. = ALIGN(4);
-		__extension_cmds = .;
-		KEEP(*(.rodata.extensioncmds))
-		__extension_cmds_end = .;
-
-		. = ALIGN(4);
-		__hcmds = .;
-		KEEP(*(SORT(.rodata.hcmds*)))
-		__hcmds_end = .;
-
-		. = ALIGN(4);
-		__mkbp_evt_srcs = .;
-		KEEP(*(.rodata.evtsrcs))
-		__mkbp_evt_srcs_end = .;
-
-		. = ALIGN(4);
-		__hooks_init = .;
-		KEEP(*(.rodata.HOOK_INIT))
-		__hooks_init_end = .;
-
-		__hooks_pre_freq_change = .;
-		KEEP(*(.rodata.HOOK_PRE_FREQ_CHANGE))
-		__hooks_pre_freq_change_end = .;
-
-		__hooks_freq_change = .;
-		KEEP(*(.rodata.HOOK_FREQ_CHANGE))
-		__hooks_freq_change_end = .;
-
-		__hooks_sysjump = .;
-		KEEP(*(.rodata.HOOK_SYSJUMP))
-		__hooks_sysjump_end = .;
-
-		__hooks_chipset_pre_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_PRE_INIT))
-		__hooks_chipset_pre_init_end = .;
-
-		__hooks_chipset_startup = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_STARTUP))
-		__hooks_chipset_startup_end = .;
-
-		__hooks_chipset_resume = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME))
-		__hooks_chipset_resume_end = .;
-
-		__hooks_chipset_suspend = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND))
-		__hooks_chipset_suspend_end = .;
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		__hooks_chipset_resume_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME_INIT))
-		__hooks_chipset_resume_init_end = .;
-
-		__hooks_chipset_suspend_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND_COMPLETE))
-		__hooks_chipset_suspend_complete_end = .;
-#endif
-
-		__hooks_chipset_shutdown = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN))
-		__hooks_chipset_shutdown_end = .;
-
-		__hooks_chipset_shutdown_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
-		__hooks_chipset_shutdown_complete_end = .;
-
-		__hooks_chipset_hard_off = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
-		__hooks_chipset_hard_off_end = .;
-
-		__hooks_chipset_reset = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
-		__hooks_chipset_reset_end = .;
-
-		__hooks_ac_change = .;
-		KEEP(*(.rodata.HOOK_AC_CHANGE))
-		__hooks_ac_change_end = .;
-
-		__hooks_lid_change = .;
-		KEEP(*(.rodata.HOOK_LID_CHANGE))
-		__hooks_lid_change_end = .;
-
-		__hooks_tablet_mode_change = .;
-		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
-		__hooks_tablet_mode_change_end = .;
-
-		__hooks_base_attached_change = .;
-		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
-		__hooks_base_attached_change_end = .;
-
-		__hooks_pwrbtn_change = .;
-		KEEP(*(.rodata.HOOK_POWER_BUTTON_CHANGE))
-		__hooks_pwrbtn_change_end = .;
-
-		__hooks_battery_soc_change = .;
-		KEEP(*(.rodata.HOOK_BATTERY_SOC_CHANGE))
-		__hooks_battery_soc_change_end = .;
-
-#ifdef CONFIG_USB_SUSPEND
-		__hooks_usb_change = .;
-		KEEP(*(.rodata.HOOK_USB_PM_CHANGE))
-		__hooks_usb_change_end = .;
-#endif
-
-		__hooks_tick = .;
-		KEEP(*(.rodata.HOOK_TICK))
-		__hooks_tick_end = .;
-
-		__hooks_second = .;
-		KEEP(*(.rodata.HOOK_SECOND))
-		__hooks_second_end = .;
-
-		__hooks_usb_pd_disconnect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_DISCONNECT))
-		__hooks_usb_pd_disconnect_end = .;
-
-		__hooks_usb_pd_connect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
-		__hooks_usb_pd_connect_end = .;
-
-		__deferred_funcs = .;
-		KEEP(*(.rodata.deferred))
-		__deferred_funcs_end = .;
-
-		__usb_desc = .;
-		KEEP(*(.rodata.usb_desc_conf))
-		KEEP(*(SORT(.rodata.usb_desc*)))
-		__usb_desc_end = .;
-		. = ALIGN(4);
-		KEEP(*(.rodata.usb_ep))
-		KEEP(*(.rodata.usb_ep.usb_ep_tx))
-		KEEP(*(.rodata.usb_ep.usb_ep_rx))
-		KEEP(*(.rodata.usb_ep.usb_ep_reset))
-		KEEP(*(.rodata.usb_ep.usb_iface_request))
-
-		. = ALIGN(4);
-		*(.rodata*)
-
-#ifndef CONFIG_CHIP_INIT_ROM_REGION
-		/*
-		 * When a separate ROM resident section isn't enabled, ensure
-		 * the corresponding data objects are linked into the .rodata
-		 * section.
-		 */
-		. = ALIGN(4);
-		__init_rom_start = .;
-		*(.init.rom)
-		__init_rom_end = .;
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
-		. = ALIGN(64);
-		KEEP(*(.google))
-#endif
-
-		. = ALIGN(4);
-	} > EC_IMAGE_VMA_MEM_REGION AT > EC_IMAGE_LMA_MEM_REGION
-
-#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
-	__data_lma_start = ORIGIN(ROM_RESIDENT_VMA);
-	#define INIT_ROM_LMA	(ORIGIN(ROM_RESIDENT_VMA) + SIZEOF(.data))
-#else
-	__data_lma_start = .;
-	#define INIT_ROM_LMA	ORIGIN(ROM_RESIDENT_VMA)
-#endif
-
-#ifdef CONFIG_PRESERVE_LOGS
-	.preserve_logs(NOLOAD) : {
-		. = ALIGN(8);
-		*(SORT(.preserved_logs.*))
-		. = ALIGN(8);
-		__preserved_logs_end = .;
-	} > IRAM
-
-	ASSERT((SIZEOF(.preserve_logs) + CONFIG_RAM_BASE) ==
-	       __preserved_logs_end,
-	       "preserve_logs must be at CONFIG_RAM_BASE.")
-#endif
-
-	.bss : {
-		/*
-		 * Align to 512 bytes. This is convenient when some memory block
-		 * needs big alignment. This is the beginning of the RAM,
-		 * so there is usually no penalty on aligning this.
-		 */
-		. = ALIGN(512);
-		__bss_start = .;
-		*(.bss.big_align)
-		/* Stacks must be 64-bit aligned */
-		. = ALIGN(8);
-		*(.bss.system_stack)
-		/* Rest of .bss takes care of its own alignment */
-
-		/* Group libtpm2 data so it can be cleared on system reset */
-		__bss_libtpm2_start = .;
-		/* TPM registers should be cleared at the same time */
-		STRINGIFY(OUTDIR/common/tpm_registers.o*)(.bss)
-			*(.bss.Tpm2_common)
-		__bss_libtpm2_end = .;
-
-		*(.bss)
-
-		/*
-		 * Reserve space for deferred function firing times.
-		 * Each time is a uint64_t, each func is a 32-bit pointer,
-		 * thus the scaling factor of two. The 8 byte alignment of
-		 * uint64_t is required by the ARM ABI.
-		 */
-		. = ALIGN(8);
-		__deferred_until = .;
-		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
-		__deferred_until_end = .;
-	} > IRAM
-
-	.bss.slow : {
-		/* Region of RAM reclaimed from the little firmware(LFW). */
-		*(.bss.slow)
-		/*
-		 * Not replacing the loader, so .bss.slow is part of .bss.
-		 * It needs to be followed by __bss_end so that .bss.slow
-		 * will be zeroed by init.
-		 */
-		. = ALIGN(4);
-		__bss_end = .;
-	} > IRAM
-
-	.data : {
-		. = ALIGN(4);
-		__data_start = .;
-		*(.data.tasks)
-
-		/*
-		 * Group libtpm2 data so it can be reinitialized on
-		 * system reset
-		 */
-		__data_libtpm2_start = .;
-		Tpm2_*(.data)
-		/* TPM registers should be reinitialized at the same time */
-		STRINGIFY(OUTDIR/common/tpm_registers.o*)(.data)
-		__data_libtpm2_end = .;
-
-		/*
-		 * TPM reset currently only clears BSS for the TPM library.
-		 * It does not reset any initialized variables in data.
-		 * So, make sure there aren't any.
-		 */
-		ASSERT(__data_libtpm2_start == __data_libtpm2_end,
-		       "libtpm2 .data section is nonzero");
-
-		*(.data*)
-#ifdef CONFIG_MPU
-		/*
-		 * It has to be aligned by 32 bytes to be a valid
-		 * MPU region.
-		 */
-		. = ALIGN(32);
-		__iram_text_start = .;
-#else
-		. = ALIGN(4);
-#endif
-		*(.iram.text)
-#ifdef CONFIG_MPU
-		. = ALIGN(32);
-		__iram_text_end = .;
-#else
-		. = ALIGN(4);
-#endif
-		__data_end = .;
-
-		/*
-		 * Shared memory buffer must be at the end of preallocated
-		 * RAM, so it can expand to use all the remaining RAM.
-		 */
-		__shared_mem_buf = .;
-
-		/* NOTHING MAY GO AFTER THIS! */
-	} > IRAM AT > DATA_LMA_MEM_REGION
-
-	ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <=
-	       (CONFIG_RAM_BASE + CONFIG_RAM_SIZE),
-	       "Not enough space for shared memory.")
-
-	__ram_free = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE) -
-		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
-
-#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
-	/*
-	 * .data is ROM resident, last section in the EC image is the .rodata
-	 * section.
-	 */
-	#define FLASH_USED_END	(LOADADDR(.rodata) + SIZEOF(.rodata))
-#else
-	/*
-	 * .data is included in the EC image and copied to RAM by the loader.
-	 */
-	#define FLASH_USED_END	(LOADADDR(.data) + SIZEOF(.data))
-#endif
-
-	/*
-	 * __flash_used is used in flash free calculations by the makefile.
-	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
-	 */
-	__flash_used = FLASH_USED_END - ORIGIN(EC_IMAGE_LMA_MEM_REGION);
-#ifndef CONFIG_CHIP_INIT_ROM_REGION
-#if !(defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 4))
-	__image_size = __flash_used;
-#else
-	.rw_image_size_alignment :
-	{
-		. = ORIGIN(FLASH) + __flash_used;
-		BYTE(0xFF);
-		. = ALIGN (CONFIG_FLASH_WRITE_SIZE);
-	} > FLASH = 0xFF
-
-	__image_size = __flash_used + SIZEOF(.rw_image_size_alignment);
-#endif
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-
-#ifdef CONFIG_FLASH_CROS
-        /*
-         * These linker labels are just for analysis and not used in the code.
-         */
-	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
-	__config_ro_size = CONFIG_RO_SIZE;
-	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
-	__config_rw_size = CONFIG_RW_SIZE;
-	__config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-#endif
-
-	/*
-	 * The linker won't notice if the .data section is too big to fit,
-	 * apparently because we're sending it into IRAM, not FLASH.
-	 * Verify that all sections linked into the FLASH region will fit.
-	 */
-	ASSERT((LENGTH(EC_IMAGE_LMA_MEM_REGION)
-#if defined(CONFIG_RWSIG) && defined(SECTION_IS_RO)
-	       - CONFIG_RO_PUBKEY_SIZE
-#endif
-#if defined(CONFIG_RWSIG) && defined(SECTION_IS_RW)
-	       - CONFIG_RW_SIG_SIZE
-#endif
-	       ) >= __flash_used,
-	       "No room left in the flash")
-
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-	/*
-	 * Image layout when ROM_RESIDENT region is used (lower addresses
-	 * at the top). This layout is setup by the LMA assignment.
-	 *
-	 *	EC image layout (LMA)		VMA
-	 *	.header (if RO image)		none
-	 *	.text				code RAM
-	 *	.rodata				code RAM + .text size
-	 *	.data				data RAM
-	 *	.fill				none
-	 *	.init_rom			flash offset
-	 *
-	 * The loader code copies the .text, .rodata, and .data sections into
-	 * the code RAM of the EC.  The .header and .init_rom sections are not
-	 * copied by the loader.
-	 *
-	 * Image layout when ROM_RESIDENT region is used, and
-	 * CONFIG_CHIP_DATA_IN_INIT_ROM is enabled.
-	 *
-	 *	EC image layout (LMA)		VMA
-	 *	.header (if RO image)		none
-	 *	.text				code RAM
-	 *	.rodata				code RAM + .text size
-	 *	.fill				none
-	 *	.data				data RAM
-	 *	.init_rom			flash offset
-	 *
-	 * The loader code copies the .text and .rodata sections into the code
-	 * RAM of the EC.  The .header, .data, and .init_rom sections are not
-	 * copied by the loader.
-	 *
-	 * EC initialization code copies the .data directly from flash to
-	 * data RAM at runtime.
-	 */
-
-	/*
-	 * The layout assumes the ROM_RESIDENT region follows the FLASH
-	 * region.
-	 */
-	ASSERT((ORIGIN(FLASH) + LENGTH(FLASH)) == ORIGIN(ROM_RESIDENT),
-		".init_rom section must follow the flash section")
-
-	.init_rom INIT_ROM_LMA : {
-		. = ALIGN(4);
-		__init_rom_start = .;
-		*(.init.rom)
-		__init_rom_end = .;
-	} > ROM_RESIDENT_VMA AT > ROM_RESIDENT
-
-	/*
-	 * The ROM_RESIDENT section is assumed to be in the same physical
-	 * flash as the FLASH section. Fill the space between.
-	 */
-	.fill : {
-		. = FLASH_USED_END;
-		. = ALIGN(4);
-		__fill_start = .;
-		FILL(0xFF);
-		. = ORIGIN(FLASH) + LENGTH(FLASH) - 1;
-		/* Need at least one byte so section is not omitted */
-		BYTE(0xFF);
-		__fill_end = .;
-	} > FLASH
-
-	/*
-	 * The end of the .fill region should also be the start of the ROM
-	 * resident region.
-	 */
-	ASSERT(__fill_end == ORIGIN(ROM_RESIDENT),
-		".fill region end not aligned to start of ROM_RESIDENT region")
-
-	/*
-	 * __image_size is used for hash calculation.  When
-	 * CONFIG_CHIP_INIT_ROM_REGION is enabled, this includes the entire
-	 * FLASH region and the bytes used in the .init_rom section.
-	 */
-#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
-	__image_size = LENGTH(FLASH) + SIZEOF(.init_rom) + SIZEOF(.data);
-#else
-	__image_size = LENGTH(FLASH) + SIZEOF(.init_rom);
-#endif /* CONFIG_CHIP_DATA_IN_INIT_ROM */
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-
-#ifdef CONFIG_CHIP_MEMORY_REGIONS
-#define REGION(name, attr, start, size) \
-	.name(NOLOAD) : { \
-		__##name##_start = .; \
-		KEEP(*(SORT(.name.keep.*))) \
-		*(SORT(.name.*)) \
-	} > name
-#define REGION_LOAD(name, attr, start, size) \
-	.name : { \
-		__##name##_start = .; \
-		KEEP(*(SORT(.name.keep.*))) \
-		*(SORT(.name.*)) \
-	} > name
-#include "memory_regions.inc"
-#undef REGION
-#undef REGION_LOAD
-#endif /* CONFIG_CHIP_MEMORY_REGIONS */
-
-#ifdef CONFIG_DRAM_BASE
-
-	/*
-	 * Sections in DRAM region are constructed as like in non-DRAM regions:
-	 * .dram.data LMA is for preserving initialized data across resets.
-	 * The only difference is that they are all in the DRAM region:
-	 * .dram.text     | LOAD
-	 * .dram.rodata   | LOAD
-	 * .dram.data LMA | LOAD
-	 * .dram.data VMA |
-	 * .dram.bss      | NOLOAD
-	 * TODO(b:123269246): Enable MPU protectable DRAM section.  This might
-	 * introduce a RO-DRAM section for .dram.text, .dram.rodata and
-	 * .dram.data LMA.
-	 */
-
-	.dram.text : {
-		. = ALIGN(4);
-		KEEP(*(SORT(.dram.text.keep.*)))
-		*(SORT(.dram.text.*))
-		. = ALIGN(4);
-	} > DRAM
-
-	.dram.rodata : {
-		. = ALIGN(4);
-		KEEP(*(SORT(.dram.rodata.keep.*)))
-		*(SORT(.dram.rodata.*))
-		. = ALIGN(4);
-	} > DRAM
-
-	__dram_data_lma_start = ADDR(.dram.rodata) + SIZEOF(.dram.rodata);
-
-	/* Place .dram.data LMA in between .dram.rodata and .dram.data VMA. */
-#ifdef __clang__
-	/*
-	 * The evaluation timing for SIZEOF() and symbols are different in
-	 * ld and lld.
-	 */
-	.dram.data __dram_data_lma_start + SIZEOF(.dram.data) : {
-#else
-	.dram.data __dram_data_lma_start +
-		(__dram_data_end - __dram_data_start) : {
-#endif /* __clang__ */
-		. = ALIGN(4);
-		__dram_data_start = .;
-		*(.dram.data*)
-		. = ALIGN(4);
-		__dram_data_end = .;
-
-	/*
-	 * Normally, '> DRAM AT > DRAM' should be the same as '> DRAM',
-	 * and they  will be at the same address. However, if the address
-	 * of VMA specified, LMA and VMA might have different addresses:
-	 * '> DRAM' places VMA at the address where section declaration
-	 * specified.
-	 * 'AT > DRAM' places LMA at the location counter's address.
-	 */
-	} > DRAM AT > DRAM
-
-	/*
-	 * ld assigns correct attribute for .bss, but not for other .*.bss,
-	 * we need an explicltly NOLOAD.
-	 */
-	.dram.bss(NOLOAD) : {
-		. = ALIGN(4);
-		__dram_bss_start = .;
-		*(SORT(.dram.bss*))
-		. = ALIGN(4);
-		__dram_bss_end = .;
-	} > DRAM
-#endif
-
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
-	/DISCARD/ : { *(.google) }
-#endif
-	/DISCARD/ : { *(.ARM.*) }
-}
diff --git a/core/cortex-m/ghash.S b/core/cortex-m/ghash.S
deleted file mode 120000
index e9acbf4b25..0000000000
--- a/core/cortex-m/ghash.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/boringssl/core/cortex-m/ghash.S
\ No newline at end of file
diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h
deleted file mode 100644
index 0949d336e2..0000000000
--- a/core/cortex-m/include/fpu.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for ARMv7 */
-
-#ifndef __CROS_EC_FPU_H
-#define __CROS_EC_FPU_H
-
-#ifdef CONFIG_FPU
-static inline float sqrtf(float v)
-{
-	float root;
-	asm volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-	return root;
-}
-
-static inline float fabsf(float v)
-{
-	float root;
-	asm volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-	return root;
-}
-#endif  /* CONFIG_FPU */
-
-#endif  /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
deleted file mode 100644
index 610728b501..0000000000
--- a/core/cortex-m/include/mpu.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MPU module for Cortex-M3 */
-
-#ifndef __CROS_EC_MPU_H
-#define __CROS_EC_MPU_H
-
-#include "common.h"
-#include "config.h" /* chips might override MPU attribute settings */
-
-/*
- * ARMv7-M SRAM region
- */
-#define CORTEX_M_SRAM_BASE	0x20000000
-
-/*
- * Region assignment. 7 as the highest, a higher index has a higher priority.
- * For example, using 7 for .iram.text allows us to mark entire RAM XN except
- * .iram.text, which is used for hibernation.
- * Region assignment is currently wasteful and can be changed if more
- * regions are needed in the future. For example, a second region may not
- * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be
- * made mutually exclusive.
- */
-enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
-	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
-};
-
-#define MPU_TYPE		REG32(0xe000ed90)
-#define MPU_CTRL		REG32(0xe000ed94)
-#define MPU_NUMBER		REG32(0xe000ed98)
-#define MPU_BASE		REG32(0xe000ed9c)
-#define MPU_SIZE		REG16(0xe000eda0)
-#define MPU_ATTR		REG16(0xe000eda2)
-
-/*
- * See ARM v7-M Architecture Reference Manual
- * Section B3.5.5 MPU Type Register, MPU_TYPE
- */
-#define MPU_TYPE_UNIFIED_MASK	0x00FF0001
-#define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
-
-#define MPU_CTRL_PRIVDEFEN	BIT(2)
-#define MPU_CTRL_HFNMIENA	BIT(1)
-#define MPU_CTRL_ENABLE		BIT(0)
-
-/*
- * Minimum region size is 32 bytes, 5 bits of address space
- */
-#define MPU_SIZE_BITS_MIN	5
-
-/*
- * XN (execute never) bit. It's bit 12 if accessed by halfword.
- *   0: XN off
- *   1: XN on
- */
-#define MPU_ATTR_XN		BIT(12)
-
-/* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
-#define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
-#define MPU_ATTR_RW_NO (1 << 8)  /* previleged ReadWrite, unprev no access */
-#define MPU_ATTR_RW_RO (2 << 8)  /* previleged ReadWrite, unprev Read-only */
-#define MPU_ATTR_RW_RW (3 << 8)  /* previleged ReadWrite, unprev ReadWrite */
-#define MPU_ATTR_RO_NO (5 << 8)  /* previleged Read-only, unprev no access */
-
-/* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
- * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
-#ifndef MPU_ATTR_INTERNAL_SRAM
-#define MPU_ATTR_INTERNAL_SRAM  6  /* for Internal SRAM */
-#endif
-#ifndef MPU_ATTR_FLASH_MEMORY
-#define MPU_ATTR_FLASH_MEMORY   2  /* for flash memory */
-#endif
-
-/* Represent RW with at most 2 MPU regions. */
-#define MAX_RW_REGIONS 2
-struct mpu_rw_regions {
-	int num_regions;
-	uint32_t addr[MAX_RW_REGIONS];
-	uint32_t size[MAX_RW_REGIONS];
-};
-
-/**
- * Enable MPU
- */
-void mpu_enable(void);
-
-/**
- * Returns the value of MPU type register
- *
- * Bit fields:
- * [15:8] Number of the data regions implemented or 0 if MPU is not present.
- * [1]    0: unified (no distinction between instruction and data)
- *        1: separated
- */
-uint32_t mpu_get_type(void);
-
-/* Location of iram.text */
-extern char __iram_text_start;
-extern char __iram_text_end;
-
-/**
- * Protect RAM from code execution
- */
-int mpu_protect_data_ram(void);
-
-/**
- * Protect code RAM from being overwritten
- */
-int mpu_protect_code_ram(void);
-
-/**
- * Protect internal mapped flash memory from code execution
- */
-int mpu_lock_ro_flash(void);
-int mpu_lock_rw_flash(void);
-
-/**
- * Protect/unprotect rollback region readback.
- */
-int mpu_lock_rollback(int lock);
-
-/**
- * Initialize MPU.
- * It disables all regions if MPU is implemented. Otherwise, returns
- * EC_ERROR_UNIMPLEMENTED.
- */
-int mpu_pre_init(void);
-
-#endif /* __CROS_EC_MPU_H */
diff --git a/core/cortex-m/include/mpu_private.h b/core/cortex-m/include/mpu_private.h
deleted file mode 100644
index e6030114c2..0000000000
--- a/core/cortex-m/include/mpu_private.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Private header file. Not meant to be used outside of mpu.c and tests.
- */
-
-#ifndef __CROS_EC_MPU_PRIVATE_H
-#define __CROS_EC_MPU_PRIVATE_H
-
-int mpu_num_regions(void);
-bool has_mpu(void);
-bool mpu_is_unified(void);
-void mpu_disable(void);
-int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
-		      uint16_t attr, uint8_t enable, uint8_t srd);
-int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
-		      uint16_t attr, uint8_t enable);
-struct mpu_rw_regions mpu_get_rw_regions(void);
-
-#endif /* __CROS_EC_MPU_PRIVATE_H */
diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S
deleted file mode 100644
index bc650c4c64..0000000000
--- a/core/cortex-m/init.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cortex-M CPU initialization
- */
-
-#include "config.h"
-
-.text
-.syntax unified
-.code 16
-
-.global reset
-.thumb_func
-reset:
-	/*
-	 * Ensure we're in privileged mode with main stack.  Necessary if
-	 * we've jumped directly here from another image after task_start().
-	 */
-#ifdef CONFIG_FPU
-	mov r0, #(1 << 2)    @ priv. mode / main stack / floating point on
-#else
-	mov r0, #0           @ priv. mode / main stack / no floating point
-#endif
-	msr control, r0
-	isb                  @ ensure the write is done
-
-	/* Set the vector table on our current code */
-	ldr r1, =vectors
-	ldr r2, =0xE000ED08   /* VTABLE register in SCB*/
-	str r1, [r2]
-
-	/* Clear BSS */
-	mov r0, #0
-	ldr r1,_bss_start
-	ldr r2,_bss_end
-bss_loop:
-	cmp r1, r2
-	it lt
-	strlt r0, [r1], #4
-	blt bss_loop
-
-	/* Copy initialized data to Internal RAM */
-	ldr r0,_data_lma_start
-
-	/*
-	 * When the .data section is linked into the .init_rom section,
-	 * _data_lma_start is defined as a flash offset instead of a full
-	 * 32-bit address by the linker script. Add the 32-bit flash base
-	 * address to get a full 32-bit address.
-	 *
-	 * Flash locking isn't needed here as no tasks have been started.
-	 */
-#ifdef CONFIG_CHIP_DATA_IN_INIT_ROM
-	ldr r1, =CONFIG_MAPPED_STORAGE_BASE
-	add r0, r0, r1
-#endif
-
-	ldr r1,_data_start
-	ldr r2,_data_end
-data_loop:
-	ldr r3, [r0], #4
-	cmp r1, r2
-	it lt
-	strlt r3, [r1], #4
-	blt data_loop
-
-	/*
-	 * Set stack pointer.  Already done by Cortex-M hardware, but re-doing
-	 * this here allows software to jump directly to the reset vector.
-	 */
-	ldr r0, =stack_end
-	mov sp, r0
-
-#ifdef CONFIG_FPU
-	/* Enable FPU */
-	/* CPACR is located at address 0xE000ED88 */
-	ldr r0, =0xE000ED88
-	/* Read CPACR */
-	ldr r1, [r0]
-	/* Set bits 20-23 to enable CP10 and CP11 coprocessors */
-	orr r1, r1, #(0xF << 20)
-	/* Write back the modified value to the CPACR */
-	str r1, [r0] /* wait for store to complete */
-	dsb
-	/* reset pipeline now the FPU is enabled */
-	isb
-#endif /* CONFIG_FPU */
-
-#ifdef CONFIG_DEBUG_DISABLE_WRITE_BUFFER
-	/* Disable write buffer used for default memory map accesses */
-	ldr r0, =0xE000E008 /* Load address of ACTLR */
-	ldr r1, [r0]        /* Read ACTLR */
-	orr r1, r1, #2      /* Set DISDEFWBUF bit */
-	str r1, [r0]        /* Write back ACTLR */
-	dsb                 /* Wait for store to complete */
-	isb                 /* Reset pipeline */
-#endif /* CONFIG_DEBUG_DISABLE_WRITE_BUFFER */
-
-	/* Jump to C code */
-	bl main
-
-	/* That should not return.  If it does, loop forever. */
-fini_loop:
-	b fini_loop
-
-.align 2
-_bss_start:
-.long __bss_start
-_bss_end:
-.long __bss_end
-_data_start:
-.long __data_start
-_data_end:
-.long __data_end
-_data_lma_start:
-.long __data_lma_start
-
-/* Mock functions to avoid linker complaints */
-.global __aeabi_unwind_cpp_pr0
-.global __aeabi_unwind_cpp_pr1
-.global __aeabi_unwind_cpp_pr2
-__aeabi_unwind_cpp_pr0:
-__aeabi_unwind_cpp_pr1:
-__aeabi_unwind_cpp_pr2:
-	bx lr
-
-/* Reserve space for system stack */
-.section .bss.system_stack
-stack_start:
-.space CONFIG_STACK_SIZE, 0
-stack_end:
-.global stack_end
-
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
deleted file mode 100644
index ae5d95cd94..0000000000
--- a/core/cortex-m/irq_handler.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helper to declare IRQ handling routines */
-
-#ifndef __CROS_EC_IRQ_HANDLER_H
-#define __CROS_EC_IRQ_HANDLER_H
-
-#ifdef CONFIG_TASK_PROFILING
-#define bl_task_start_irq_handler "bl task_start_irq_handler\n"
-#else
-#define bl_task_start_irq_handler ""
-#endif
-
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
-/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void) __attribute__((naked));	\
-	typedef struct {					\
-		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];	\
-	} irq_num_check_##irq;					\
-	void __keep routine(void);				\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		asm volatile("mov r0, lr\n"			\
-			     "push {r0, lr}\n"			\
-			     bl_task_start_irq_handler		\
-			     "bl "#routine"\n"			\
-			     "pop {r0, lr}\n"			\
-			     "b task_resched_if_needed\n"	\
-			    );					\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m/ldivmod.S b/core/cortex-m/ldivmod.S
deleted file mode 120000
index afdeb4ec1f..0000000000
--- a/core/cortex-m/ldivmod.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S
\ No newline at end of file
diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c
deleted file mode 100644
index 0827121e97..0000000000
--- a/core/cortex-m/llsr.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Enable the use of right shift for uint64_t. */
-
-#include <console.h>
-#include <compile_time_macros.h>
-#include <stdint.h>
-
-union words {
-	uint64_t u64;
-	uint32_t w[2];
-};
-
-uint64_t __attribute__((used)) __aeabi_llsr(uint64_t v, uint32_t shift)
-{
-	union words val;
-	union words res;
-
-	val.u64 = v;
-	res.w[1] = val.w[1] >> shift;
-	res.w[0] = val.w[0] >> shift;
-	res.w[0] |= val.w[1] >> (shift - 32); /* Handle shift >= 32*/
-	res.w[0] |= val.w[1] << (32 - shift); /* Handle shift <= 32*/
-	return res.u64;
-}
-
-#ifdef CONFIG_LLSR_TEST
-
-static int command_llsr(int argc, char **argv)
-{
-	/* Volatile to prevent compilier optimization from interfering. */
-	volatile uint64_t start = 0x123456789ABCDEF0ull;
-	uint32_t x;
-
-	const struct {
-		uint32_t shift_by;
-		uint64_t result;
-	} cases[] = {
-		{0, start},
-		{16, 0x123456789ABCull},
-		{32, 0x12345678u},
-		{48, 0x1234u},
-		{64, 0u}
-	};
-
-	for (x = 0; x < ARRAY_SIZE(cases); ++x) {
-		if ((start >> cases[x].shift_by) != cases[x].result) {
-			ccprintf("FAILED %d\n", cases[x].shift_by);
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	ccprintf("SUCCESS\n");
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(
-		llsrtest, command_llsr,
-		"",
-		"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
-
-#endif  /* CONFIG_LLSR_TEST */
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
deleted file mode 100644
index 29da931a28..0000000000
--- a/core/cortex-m/mpu.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MPU module for Chrome EC */
-
-#include "mpu.h"
-#include "console.h"
-#include "cpu.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/**
- * @return Number of regions supported by the MPU. 0 means the processor does
- * not implement an MPU.
- */
-int mpu_num_regions(void)
-{
-	return MPU_TYPE_REG_COUNT(mpu_get_type());
-}
-
-/**
- * @return true if processor has MPU, false otherwise
- */
-bool has_mpu(void)
-{
-	return mpu_num_regions() != 0;
-}
-
-/**
- * @return true if MPU has unified instruction and data maps, false otherwise
- */
-bool mpu_is_unified(void)
-{
-	return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
-}
-
-
-/**
- * Update a memory region.
- *
- * region: index of the region to update
- * addr: base address of the region
- * size_bit: size of the region in power of two.
- * attr: attribute bits. Current value will be overwritten if enable is true.
- * enable: enables the region if non zero. Otherwise, disables the region.
- * srd: subregion mask to partition region into 1/8ths, 0 = subregion enabled.
- *
- * Based on 3.1.4.1 'Updating an MPU Region' of Stellaris LM4F232H5QC Datasheet
- */
-int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
-		      uint16_t attr, uint8_t enable, uint8_t srd)
-{
-	/*
-	 * Note that on the Cortex-M3, Cortex-M4, and Cortex-M7, the base
-	 * address used for an MPU region must be aligned to the size of the
-	 * region:
-	 *
-	 * https://developer.arm.com/docs/dui0553/a/cortex-m4-peripherals/optional-memory-protection-unit/mpu-region-base-address-register
-	 * https://developer.arm.com/docs/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-region-base-address-register
-	 * https://developer.arm.com/docs/dui0646/a/cortex-m7-peripherals/optional-memory-protection-unit/mpu-region-base-address-register#BABDAHJG
-	 */
-	if (!is_aligned(addr, BIT(size_bit)))
-		return -EC_ERROR_INVAL;
-
-	if (region >= mpu_num_regions())
-		return -EC_ERROR_INVAL;
-
-	if (size_bit < MPU_SIZE_BITS_MIN)
-		return -EC_ERROR_INVAL;
-
-	asm volatile("isb; dsb;");
-
-	MPU_NUMBER = region;
-	MPU_SIZE &= ~1;					/* Disable */
-	if (enable) {
-		MPU_BASE = addr;
-		/*
-		 * MPU_ATTR = attr;
-		 * MPU_SIZE = (srd << 8) | ((size_bit - 1) << 1) | 1;
-		 *
-		 * WORKAROUND: the 2 half-word accesses above should work
-		 * according to the doc, but they don't ..., do a single 32-bit
-		 * one.
-		 */
-		REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
-				 | (srd << 8) | ((size_bit - 1) << 1) | 1;
-	}
-
-	asm volatile("isb; dsb;");
-
-	return EC_SUCCESS;
-}
-
-/*
- * Greedily configure the largest possible part of the given region from the
- * base address.
- *
- * Returns EC_SUCCESS on success and sets *consumed to the number of bytes
- * mapped from the base address. In case of error, the value of *consumed is
- * unpredictable.
- *
- * For instance, if addr is 0x10070000 and size is 0x30000 then memory in the
- * range 0x10070000-0x10080000 will be configured and *consumed will be set to
- * 0x10000.
- */
-static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
-				    uint32_t size, uint16_t attr,
-				    uint8_t enable, uint32_t *consumed)
-{
-	/*
-	 * Compute candidate alignment to be used for the MPU region.
-	 *
-	 * This is the minimum of the base address and size alignment, since
-	 * regions must be naturally aligned to their size.
-	 */
-	uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
-				     alignment_log2(size));
-	uint8_t subregion_disable = 0;
-
-	if (natural_alignment >= 5) {
-		int sr_idx;
-		uint32_t subregion_base, subregion_size;
-		/*
-		 * For MPU regions larger than 256 bytes we can use subregions,
-		 * (which are a minimum of 32 bytes in size) making the actual
-		 * MPU region 8x larger. Depending on the address alignment this
-		 * can allow us to cover a larger area (and never a smaller
-		 * one).
-		 */
-		natural_alignment += 3;
-		/* Region size cannot exceed 4GB. */
-		if (natural_alignment > 32)
-			natural_alignment = 32;
-
-		/*
-		 * Generate the subregion mask by walking through each,
-		 * disabling if it is not completely contained in the requested
-		 * range.
-		 */
-		subregion_base = addr & ~((1 << natural_alignment) - 1);
-		subregion_size = 1 << (natural_alignment - 3);
-		*consumed = 0;
-		for (sr_idx = 0; sr_idx < 8; sr_idx++) {
-			if (subregion_base < addr ||
-			    (subregion_base + subregion_size) > (addr + size))
-				/* lsb of subregion mask is lowest address */
-				subregion_disable |= 1 << sr_idx;
-			else
-				/* not disabled means consumed */
-				*consumed += subregion_size;
-
-			subregion_base += subregion_size;
-		}
-	} else {
-		/* Not using subregions; all enabled */
-		*consumed = 1 << natural_alignment;
-	}
-
-	return mpu_update_region(region,
-			       addr & ~((1 << natural_alignment) - 1),
-			       natural_alignment,
-			       attr, enable, subregion_disable);
-}
-
-/**
- * Configure a region
- *
- * region: index of the region to update
- * addr: Base address of the region
- * size: Size of the region in bytes
- * attr: Attribute bits. Current value will be overwritten if enable is set.
- * enable: Enables the region if non zero. Otherwise, disables the region.
- *
- * Returns EC_SUCCESS on success, -EC_ERROR_OVERFLOW if it is not possible to
- * fully configure the given region, or -EC_ERROR_INVAL if a parameter is
- * invalid (such as the address or size having unsupported alignment).
- */
-int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
-		      uint16_t attr, uint8_t enable)
-{
-	int rv;
-	uint32_t consumed;
-
-	/* Zero size doesn't require configuration */
-	if (size == 0)
-		return EC_SUCCESS;
-
-	rv = mpu_config_region_greedy(region, addr, size,
-				      attr, enable, &consumed);
-	if (rv != EC_SUCCESS)
-		return rv;
-	ASSERT(consumed <= size);
-	addr += consumed;
-	size -= consumed;
-
-	/* Regions other than DATA_RAM_TEXT may use two MPU regions */
-	if (size > 0 && region != REGION_DATA_RAM_TEXT) {
-		rv = mpu_config_region_greedy(region + 1, addr, size,
-					      attr, enable, &consumed);
-		if (rv != EC_SUCCESS)
-			return rv;
-		ASSERT(consumed <= size);
-		addr += consumed;
-		size -= consumed;
-	}
-
-	if (size > 0)
-		return EC_ERROR_OVERFLOW;
-	return EC_SUCCESS;
-}
-
-/**
- * Set a region executable and read-write.
- *
- * region: index of the region
- * addr: base address of the region
- * size: size of the region in bytes
- * texscb: TEX and SCB bit field
- */
-static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
-			     uint8_t texscb)
-{
-	return mpu_config_region(region, addr, size,
-				 MPU_ATTR_RW_RW | texscb, 1);
-}
-
-void mpu_enable(void)
-{
-	MPU_CTRL |= MPU_CTRL_PRIVDEFEN | MPU_CTRL_HFNMIENA | MPU_CTRL_ENABLE;
-}
-
-void mpu_disable(void)
-{
-	MPU_CTRL &= ~(MPU_CTRL_PRIVDEFEN | MPU_CTRL_HFNMIENA | MPU_CTRL_ENABLE);
-}
-
-uint32_t mpu_get_type(void)
-{
-	return MPU_TYPE;
-}
-
-int mpu_protect_data_ram(void)
-{
-	int ret;
-
-	/* Prevent code execution from data RAM */
-	ret = mpu_config_region(REGION_DATA_RAM,
-				CONFIG_RAM_BASE,
-				CONFIG_DATA_RAM_SIZE,
-				MPU_ATTR_XN |
-				MPU_ATTR_RW_RW |
-				MPU_ATTR_INTERNAL_SRAM,
-				1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Exempt the __iram_text section */
-	return mpu_unlock_region(
-		REGION_DATA_RAM_TEXT, (uint32_t)&__iram_text_start,
-		(uint32_t)(&__iram_text_end - &__iram_text_start),
-		MPU_ATTR_INTERNAL_SRAM);
-}
-
-#if defined(CONFIG_EXTERNAL_STORAGE) || !defined(CONFIG_FLASH_PHYSICAL)
-int mpu_protect_code_ram(void)
-{
-	/* Prevent write access to code RAM */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_CODE_RAM_SIZE,
-				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
-				 1);
-}
-#else
-int mpu_lock_ro_flash(void)
-{
-	/* Prevent execution from internal mapped RO flash */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_RO_SIZE,
-				 MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				 MPU_ATTR_FLASH_MEMORY, 1);
-}
-
-/* Represent RW with at most 2 MPU regions. */
-struct mpu_rw_regions mpu_get_rw_regions(void)
-{
-	int aligned_size_bit;
-	struct mpu_rw_regions regions = {};
-
-	regions.addr[0] = CONFIG_MAPPED_STORAGE_BASE + CONFIG_RW_MEM_OFF;
-
-	/*
-	 * Least significant set bit of the address determines the max size of
-	 * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
-	 * address used for an MPU region must be aligned to the size.
-	 */
-	aligned_size_bit =
-		__fls(regions.addr[0] & -regions.addr[0]);
-	regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
-	regions.addr[1] = regions.addr[0] + regions.size[0];
-	regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
-	regions.num_regions = (regions.size[1] == 0) ? 1 : 2;
-
-	return regions;
-}
-
-int mpu_lock_rw_flash(void)
-{
-	/* Prevent execution from internal mapped RW flash */
-	const uint16_t mpu_attr = MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				  MPU_ATTR_FLASH_MEMORY;
-	const struct mpu_rw_regions regions = mpu_get_rw_regions();
-	int rv;
-
-	rv = mpu_config_region(REGION_STORAGE, regions.addr[0], regions.size[0],
-			       mpu_attr, 1);
-	if ((rv != EC_SUCCESS) || (regions.num_regions == 1))
-		return rv;
-
-	/* If this fails then it's impossible to represent with two regions. */
-	return mpu_config_region(REGION_STORAGE2, regions.addr[1],
-				 regions.size[1], mpu_attr, 1);
-}
-#endif /* !CONFIG_EXTERNAL_STORAGE */
-
-#ifdef CONFIG_ROLLBACK_MPU_PROTECT
-int mpu_lock_rollback(int lock)
-{
-	int rv;
-	int num_mpu_regions = mpu_num_regions();
-
-	const uint32_t rollback_region_start_address =
-		CONFIG_MAPPED_STORAGE_BASE + CONFIG_ROLLBACK_OFF;
-	const uint32_t rollback_region_total_size = CONFIG_ROLLBACK_SIZE;
-	const uint16_t mpu_attr =
-		MPU_ATTR_XN /* Execute never */ |
-		MPU_ATTR_NO_NO /* No access (privileged or unprivileged */;
-
-	/*
-	 * Originally rollback MPU support was added on Cortex-M7, which
-	 * supports 16 MPU regions and has rollback region aligned in a way
-	 * that we can use a single region.
-	 */
-	uint8_t rollback_mpu_region = REGION_ROLLBACK;
-
-	if (rollback_mpu_region < num_mpu_regions) {
-		rv = mpu_config_region(rollback_mpu_region,
-				       rollback_region_start_address,
-				       rollback_region_total_size, mpu_attr,
-				       lock);
-		return rv;
-	}
-
-	/*
-	 * If we get here, we can't use REGION_ROLLBACK because our MPU doesn't
-	 * have enough regions. Instead, we choose unused MPU regions.
-	 *
-	 * Note that on the Cortex-M3, Cortex-M4, and Cortex-M7, the base
-	 * address used for an MPU region must be aligned to the size of the
-	 * region, so it's not possible to use a single region to protect the
-	 * entire rollback flash on the STM32F412 (bloonchipper); we have to
-	 * use two.
-	 *
-	 * See mpu_update_region for alignment details.
-	 */
-
-	rollback_mpu_region = REGION_CHIP_RESERVED;
-	rv = mpu_config_region(rollback_mpu_region,
-			       rollback_region_start_address,
-			       rollback_region_total_size / 2, mpu_attr, lock);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rollback_mpu_region = REGION_CODE_RAM;
-	rv = mpu_config_region(rollback_mpu_region,
-			       rollback_region_start_address +
-				       (rollback_region_total_size / 2),
-			       rollback_region_total_size / 2, mpu_attr, lock);
-	return rv;
-}
-#endif
-
-#ifdef CONFIG_CHIP_UNCACHED_REGION
-/* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
-	static const uint32_t CONCAT2(_region_start_, _name) \
-		__attribute__((unused, section(".unused"))) = _start; \
-	static const uint32_t CONCAT2(_region_size_, _name) \
-		__attribute__((unused, section(".unused"))) = _size;
-#include "memory_regions.inc"
-#undef REGION
-#endif /* CONFIG_CHIP_UNCACHED_REGION */
-
-int mpu_pre_init(void)
-{
-	int i;
-	int num_mpu_regions;
-	int rv;
-
-	if (!has_mpu())
-		return EC_ERROR_HW_INTERNAL;
-
-	num_mpu_regions = mpu_num_regions();
-
-	/* Supports MPU with 8 or 16 unified regions */
-	if (!mpu_is_unified() ||
-	    (num_mpu_regions != 8 && num_mpu_regions != 16))
-		return EC_ERROR_UNIMPLEMENTED;
-
-	mpu_disable();
-
-	for (i = 0; i < num_mpu_regions; ++i) {
-		/*
-		 * Disable all regions.
-		 *
-		 * We use the smallest possible size (32 bytes), but it
-		 * doesn't really matter since the regions are disabled.
-		 *
-		 * Use the fixed SRAM region base to ensure base is aligned
-		 * to the region size.
-		 */
-		rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
-			0, 0, 0);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	if (IS_ENABLED(CONFIG_ROLLBACK_MPU_PROTECT)) {
-		rv = mpu_lock_rollback(1);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	if (IS_ENABLED(CONFIG_ARMV7M_CACHE)) {
-#ifdef CONFIG_CHIP_UNCACHED_REGION
-		rv = mpu_config_region(
-			REGION_UNCACHED_RAM,
-			CONCAT2(_region_start_, CONFIG_CHIP_UNCACHED_REGION),
-			CONCAT2(_region_size_, CONFIG_CHIP_UNCACHED_REGION),
-			MPU_ATTR_XN | MPU_ATTR_RW_RW, 1);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-#endif
-	}
-
-	mpu_enable();
-
-	if (IS_ENABLED(CONFIG_ARMV7M_CACHE))
-		cpu_enable_caches();
-
-	return EC_SUCCESS;
-}
diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h
deleted file mode 100644
index 1a58afa8a2..0000000000
--- a/core/cortex-m/panic-internal.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PANIC_INTERNAL_H
-#define __CROS_EC_PANIC_INTERNAL_H
-
-void exception_panic(void) __attribute__((naked));
-
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
deleted file mode 100644
index da6900b1b9..0000000000
--- a/core/cortex-m/panic.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "panic-internal.h"
-#include "printf.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Whether bus fault is ignored */
-static int bus_fault_ignored;
-
-
-/* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
-
-/* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
-static const uint32_t pstack_addr = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE
-				     - sizeof(struct panic_data)) & ~7;
-
-/**
- * Print the name and value of a register
- *
- * This is a convenient helper function for displaying a register value.
- * It shows the register name in a 3 character field, followed by a colon.
- * The register value is regs[index], and this is shown in hex. If regs is
- * NULL, then we display spaces instead.
- *
- * After displaying the value, either a space or \n is displayed depending
- * on the register number, so that (assuming the caller passes all 16
- * registers in sequence) we put 4 values per line like this
- *
- * r0 :0000000b r1 :00000047 r2 :60000000 r3 :200012b5
- * r4 :00000000 r5 :08004e64 r6 :08004e1c r7 :200012a8
- * r8 :08004e64 r9 :00000002 r10:00000000 r11:00000000
- * r12:0000003f sp :200009a0 lr :0800270d pc :0800351a
- *
- * @param regnum	Register number to display (0-15)
- * @param regs		Pointer to array holding the registers, or NULL
- * @param index		Index into array where the register value is present
- */
-static void print_reg(int regnum, const uint32_t *regs, int index)
-{
-	static const char regname[] = "r10r11r12sp lr pc ";
-	static char rname[3] = "r  ";
-	const char *name;
-
-	rname[1] = '0' + regnum;
-	name = regnum < 10 ? rname : &regname[(regnum - 10) * 3];
-	panic_printf("%c%c%c:", name[0], name[1], name[2]);
-	if (regs)
-		panic_printf("%08x", regs[index]);
-	else
-		panic_puts("        ");
-	panic_puts((regnum & 3) == 3 ? "\n" : " ");
-}
-
-/*
- * Returns non-zero if the exception frame was created on the main stack, or
- * zero if it's on the process stack.
- *
- * See B1.5.8 "Exception return behavior" of ARM DDI 0403D for details.
- */
-static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
-{
-	return (exc_return & 0xf) == 1 || (exc_return & 0xf) == 9;
-}
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-/* Names for each of the bits in the cfs register, starting at bit 0 */
-static const char * const cfsr_name[32] = {
-	/* MMFSR */
-	[0] = "Instruction access violation",
-	[1] = "Data access violation",
-	[3] = "Unstack from exception violation",
-	[4] = "Stack from exception violation",
-
-	/* BFSR */
-	[8] = "Instruction bus error",
-	[9] = "Precise data bus error",
-	[10] = "Imprecise data bus error",
-	[11] = "Unstack from exception bus fault",
-	[12] = "Stack from exception bus fault",
-
-	/* UFSR */
-	[16] = "Undefined instructions",
-	[17] = "Invalid state",
-	[18] = "Invalid PC",
-	[19] = "No coprocessor",
-	[24] = "Unaligned",
-	[25] = "Divide by 0",
-};
-
-/* Names for the first 5 bits in the DFSR */
-static const char * const dfsr_name[] = {
-	"Halt request",
-	"Breakpoint",
-	"Data watchpoint/trace",
-	"Vector catch",
-	"External debug request",
-};
-
-/**
- * Helper function to display a separator after the previous item
- *
- * If items have been displayed already, we display a comma separator.
- * In any case, the count of items displayed is incremeneted.
- *
- * @param count		Number of items displayed so far (0 for none)
- */
-static void do_separate(int *count)
-{
-	if (*count)
-		panic_puts(", ");
-	(*count)++;
-}
-
-/**
- * Show a textual representaton of the fault registers
- *
- * A list of detected faults is shown, with no trailing newline.
- *
- * @param cfsr		Value of Configurable Fault Status
- * @param hfsr		Value of Hard Fault Status
- * @param dfsr		Value of Debug Fault Status
- */
-static void show_fault(uint32_t cfsr, uint32_t hfsr, uint32_t dfsr)
-{
-	unsigned int upto;
-	int count = 0;
-
-	for (upto = 0; upto < 32; upto++) {
-		if ((cfsr & BIT(upto)) && cfsr_name[upto]) {
-			do_separate(&count);
-			panic_puts(cfsr_name[upto]);
-		}
-	}
-
-	if (hfsr & CPU_NVIC_HFSR_DEBUGEVT) {
-		do_separate(&count);
-		panic_puts("Debug event");
-	}
-	if (hfsr & CPU_NVIC_HFSR_FORCED) {
-		do_separate(&count);
-		panic_puts("Forced hard fault");
-	}
-	if (hfsr & CPU_NVIC_HFSR_VECTTBL) {
-		do_separate(&count);
-		panic_puts("Vector table bus fault");
-	}
-
-	for (upto = 0; upto < 5; upto++) {
-		if ((dfsr & BIT(upto))) {
-			do_separate(&count);
-			panic_puts(dfsr_name[upto]);
-		}
-	}
-}
-
-/*
- * Returns the size of the exception frame.
- *
- * See B1.5.7 "Stack alignment on exception entry" of ARM DDI 0403D for details.
- * In short, the exception frame size can be either 0x20, 0x24, 0x68, or 0x6c
- * depending on FPU context and padding for 8-byte alignment.
- */
-static uint32_t get_exception_frame_size(const struct panic_data *pdata)
-{
-	uint32_t frame_size = 0;
-
-	/* base exception frame */
-	frame_size += 8 * sizeof(uint32_t);
-
-	/* CPU uses xPSR[9] to indicate whether it padded the stack for
-	 * alignment or not. */
-	if (pdata->cm.frame[7] & BIT(9))
-		frame_size += sizeof(uint32_t);
-
-#ifdef CONFIG_FPU
-	/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
-	 * frame for FPU or not. */
-	if (!(pdata->cm.regs[11] & BIT(4)))
-		frame_size += 18 * sizeof(uint32_t);
-#endif
-
-	return frame_size;
-}
-
-/*
- * Returns the position of the process stack before the exception frame.
- * It computes the size of the exception frame and adds it to psp.
- * If the exception happened in the exception context, it returns psp as is.
- */
-static uint32_t get_process_stack_position(const struct panic_data *pdata)
-{
-	uint32_t psp = pdata->cm.regs[0];
-
-	if (!is_frame_in_handler_stack(pdata->cm.regs[11]))
-		psp += get_exception_frame_size(pdata);
-
-	return psp;
-}
-
-/*
- * Show extra information that might be useful to understand a panic()
- *
- * We show fault register information, including the fault address registers
- * if valid.
- */
-static void panic_show_extra(const struct panic_data *pdata)
-{
-	show_fault(pdata->cm.cfsr, pdata->cm.hfsr, pdata->cm.dfsr);
-	if (pdata->cm.cfsr & CPU_NVIC_CFSR_BFARVALID)
-		panic_printf(", bfar = %x", pdata->cm.bfar);
-	if (pdata->cm.cfsr & CPU_NVIC_CFSR_MFARVALID)
-		panic_printf(", mfar = %x", pdata->cm.mfar);
-	panic_printf("\ncfsr = %x, ", pdata->cm.cfsr);
-	panic_printf("shcsr = %x, ", pdata->cm.shcsr);
-	panic_printf("hfsr = %x, ", pdata->cm.hfsr);
-	panic_printf("dfsr = %x\n", pdata->cm.dfsr);
-}
-
-/*
- * Prints process stack contents stored above the exception frame.
- */
-static void panic_show_process_stack(const struct panic_data *pdata)
-{
-	panic_printf("\n=========== Process Stack Contents ===========");
-	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID) {
-		uint32_t psp = get_process_stack_position(pdata);
-		int i;
-		for (i = 0; i < 16; i++) {
-			if (psp + sizeof(uint32_t) >
-			    CONFIG_RAM_BASE + CONFIG_RAM_SIZE)
-				break;
-			if (i % 4 == 0)
-				panic_printf("\n%08x:", psp);
-			panic_printf(" %08x", *(uint32_t *)psp);
-			psp += sizeof(uint32_t);
-		}
-	} else {
-		panic_printf("\nBad psp");
-	}
-}
-#endif /* CONFIG_DEBUG_EXCEPTIONS */
-
-/*
- * Print panic data
- */
-void panic_data_print(const struct panic_data *pdata)
-{
-	const uint32_t *lregs = pdata->cm.regs;
-	const uint32_t *sregs = NULL;
-	const int32_t in_handler =
-		is_frame_in_handler_stack(pdata->cm.regs[11]);
-	int i;
-
-	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
-		sregs = pdata->cm.frame;
-
-	panic_printf("\n=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
-		     in_handler ? "HANDLER" : "PROCESS",
-		     lregs[1] & 0xff, sregs ? sregs[7] : -1);
-	for (i = 0; i < 4; i++)
-		print_reg(i, sregs, i);
-	for (i = 4; i < 10; i++)
-		print_reg(i, lregs, i - 1);
-	print_reg(10, lregs, 9);
-	print_reg(11, lregs, 10);
-	print_reg(12, sregs, 4);
-	print_reg(13, lregs, in_handler ? 2 : 0);
-	print_reg(14, sregs, 5);
-	print_reg(15, sregs, 6);
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-	panic_show_extra(pdata);
-#endif
-}
-
-void __keep report_panic(void)
-{
-	/*
-	 * Don't need to get pointer via get_panic_data_write()
-	 * because memory below pdata_ptr is stack now (see exception_panic())
-	 */
-	struct panic_data *pdata = pdata_ptr;
-	uint32_t sp;
-
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = sizeof(*pdata);
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_CORTEX_M;
-	pdata->flags = 0;
-	pdata->reserved = 0;
-
-	/* Choose the right sp (psp or msp) based on EXC_RETURN value */
-	sp = is_frame_in_handler_stack(pdata->cm.regs[11])
-		? pdata->cm.regs[2] : pdata->cm.regs[0];
-	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
-	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
-		const uint32_t *sregs = (const uint32_t *)sp;
-		int i;
-
-		/* Skip r0-r3 and r12 registers if necessary */
-		for (i = CORTEX_PANIC_FRAME_REGISTER_R0;
-		    i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
-			if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR))
-				pdata->cm.frame[i] = 0;
-			else
-				pdata->cm.frame[i] = sregs[i];
-
-		for (i = CORTEX_PANIC_FRAME_REGISTER_LR;
-		    i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
-			pdata->cm.frame[i] = sregs[i];
-
-		pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
-	}
-
-	/* Save extra information */
-	pdata->cm.cfsr = CPU_NVIC_CFSR;
-	pdata->cm.bfar = CPU_NVIC_BFAR;
-	pdata->cm.mfar = CPU_NVIC_MFAR;
-	pdata->cm.shcsr = CPU_NVIC_SHCSR;
-	pdata->cm.hfsr = CPU_NVIC_HFSR;
-	pdata->cm.dfsr = CPU_NVIC_DFSR;
-
-#ifdef CONFIG_UART_PAD_SWITCH
-	uart_reset_default_pad_panic();
-#endif
-	panic_data_print(pdata);
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-	panic_show_process_stack(pdata);
-	/*
-	 * TODO(crosbug.com/p/23760): Dump main stack contents as well if the
-	 * exception happened in a handler's context.
-	 */
-#endif
-
-	/* Make sure that all changes are saved into RAM */
-	if (IS_ENABLED(CONFIG_ARMV7M_CACHE))
-		cpu_clean_invalidate_dcache();
-
-	panic_reboot();
-}
-
-/**
- * Default exception handler, which reports a panic.
- *
- * Declare this as a naked call so we can extract raw LR and IPSR values.
- */
-void exception_panic(void)
-{
-	/* Save registers and branch directly to panic handler */
-	asm volatile(
-		"mov r0, %[pregs]\n"
-		"mrs r1, psp\n"
-		"mrs r2, ipsr\n"
-		"mov r3, sp\n"
-#ifdef CONFIG_PANIC_STRIP_GPR
-		/*
-		 * Check if we are in exception. This is similar to
-		 * in_interrupt_context(). Exception bits are 9 LSB, so
-		 * we can perform left shift for 23 bits and check if result
-		 * is 0 (lsls instruction is setting appropriate flags).
-		 */
-		"lsls r6, r2, #23\n"
-		/*
-		 * If this is software panic (shift result == 0) then register
-		 * r4 and r5 contain additional info about panic.
-		 * Clear r6-r11 always and r4, r5 only if this is exception
-		 * panic. To clear r4 and r5, 'movne' conditional instruction
-		 * is used. It works only when flags contain information that
-		 * result was != 0. Itt is pseudo instruction which is used
-		 * to make sure we are using correct conditional instructions.
-		 */
-		"itt ne\n"
-		"movne r4, #0\n"
-		"movne r5, #0\n"
-		"mov r6, #0\n"
-		"mov r7, #0\n"
-		"mov r8, #0\n"
-		"mov r9, #0\n"
-		"mov r10, #0\n"
-		"mov r11, #0\n"
-#endif
-		"stmia r0, {r1-r11, lr}\n"
-		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
-			"r10", "r11", "cc", "memory"
-		);
-}
-
-#ifdef CONFIG_SOFTWARE_PANIC
-void software_panic(uint32_t reason, uint32_t info)
-{
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
-	__builtin_unreachable();
-}
-
-void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
-{
-	struct panic_data * const pdata = get_panic_data_write();
-	uint32_t *lregs;
-
-	lregs = pdata->cm.regs;
-
-	/* Setup panic data structure */
-	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_CORTEX_M;
-
-	/* Log panic cause */
-	lregs[1] = exception;
-	lregs[3] = reason;
-	lregs[4] = info;
-}
-
-void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
-{
-	struct panic_data * const pdata = panic_get_data();
-	uint32_t *lregs;
-
-	if (pdata && pdata->struct_version == 2) {
-		lregs = pdata->cm.regs;
-		*exception = lregs[1];
-		*reason = lregs[3];
-		*info = lregs[4];
-	} else {
-		*exception = *reason = *info = 0;
-	}
-}
-#endif
-
-void bus_fault_handler(void)
-{
-	if (!bus_fault_ignored)
-		exception_panic();
-}
-
-void ignore_bus_fault(int ignored)
-{
-	if (IS_ENABLED(CHIP_FAMILY_STM32H7)) {
-		if (ignored == 0)
-			asm volatile("dsb; isb");
-	}
-
-	/*
-	 * Flash code might call this before cpu_init(),
-	 * ensure that the bus faults really go through our handler.
-	 */
-	CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_BUSFAULTENA;
-	bus_fault_ignored = ignored;
-}
diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S
deleted file mode 100644
index f56c5e4c74..0000000000
--- a/core/cortex-m/switch.S
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Context swtching
- */
-
-#include "config.h"
-
-.text
-
-.syntax unified
-.code 16
-
-/**
- * Task context switching
- *
- * Change the task scheduled after returning from the exception.
- *
- * Save the registers of the current task below the exception context on
- * its task, then restore the live registers of the next task and set the
- * process stack pointer to the new stack.
- *
- * r0: pointer to the task to switch from
- * r1: pointer to the task to switch to
- *
- * must be called from interrupt context
- *
- * the structure of the saved context on the stack is :
- *     r0, r1, r2, r3, r12, lr, pc, psr, r4, r5, r6, r7, r8, r9, r10, r11
- *       exception frame              <|> additional registers
- *
- * if using the FPU, then to store FPU context, add FP regs to the stack. in
- * this case the exception frame by default contains:
- *     r0, r1, r2, r3, r12, lr, pc, psr,
- *     s0 - s15, FPSCR, +1 word for 64-bit alignment
- * then in addition we store the following registers:
- *     r4, r5, r6, r7, r8, r9, r10, r11
- *     s16 - s31 (stored iff FP was used by the task (see EXC_RETURN[4]))
- * note that for the context switch to know if the next task has the extra FP
- * regs on the stack or not, we make use of the least significant bit of the
- * stack pointer. lsb of stack pointer is 1 if task has FP regs on stack, and
- * 0 otherwise.
- *
- */
-.global __switchto
-.thumb_func
-__switchto:
-  mrs r3, psp            @ get the task stack where the context has been saved
-  ldr r2, [r1]           @ get the new scheduled task stack pointer
-  stmdb r3!, {r4-r11}    @ save additional r4-r11 in the task stack
-
-#ifdef CONFIG_FPU
-  tst lr, #(1<<4)        @ test EXC_RETURN[4] for old task
-  itt eq                 @ if EXC_RETURN[4] is zero, add FP regs to stack
-  vstmdbeq r3!, {s16-s31}@ save additional FP s16-s31 in the task stack.
-                         @ if using lazy stacking, this will trigger saving
-                         @ s0-s15 in the reserved stack space.
-  orreq r3, #1           @ set lsb of old stack pointer high to represent this
-                         @ task uses FPU. note stack pointer should be 64-bit
-                         @ aligned, so using this bit should be safe.
-
-  tst r2, #1             @ test lsb of next stack pointer
-  ittte ne               @ if lsb is 1, then next task has FP regs on stack
-  bicne r2, #1           @ clear lsb of new stack pointer
-  bicne lr, #(1<<4)      @ clear EXC_RETURN[4] for next task
-  vldmiane r2!, {s16-s31}@ restore s16-s31 for the next task context
-  orreq lr, #(1<<4)      @ else if new stack doesn't use FP, set EXC_RETURN[4]
-#endif
-
-  ldmia r2!, {r4-r11}    @ restore r4-r11 for the next task context
-  str r3, [r0]           @ save the task stack pointer in its context
-  msr psp, r2            @ set the process stack pointer to exception context
-  bx lr                  @ return from exception
-
-/**
- * Start the task scheduling.  r0 is a pointer to task_stack_ready, which is
- * set to 1 after the task stack is set up.
- */
-.global __task_start
-.thumb_func
-__task_start:
-  ldr r2,=scratchpad     @ area used as thread stack for the first switch
-  mov r3, #2             @ use : priv. mode / thread stack / no floating point
-                         @ setting FP to unused here means first context switch
-                         @ will not store FP regs
-  add r2, #17*4          @ put the pointer at the top of the stack
-  mov r1, #0             @ __Schedule parameter : re-schedule nothing
-  msr psp, r2            @ setup a thread stack up to the first context switch
-  mov r2, #1
-  isb                    @ ensure the write is done
-  msr control, r3
-  mov r3, r0
-  mov r0, #0             @ __Schedule parameter : de-schedule nothing
-  isb                    @ ensure the write is done
-  str r2, [r3]           @ Task scheduling is now active
-  bl __schedule          @ execute the task with the highest priority
-  /* we should never return here */
-  mov r0, #1             @ set to EC_ERROR_UNKNOWN
-  bx lr
-
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
deleted file mode 100644
index bf0eb5b397..0000000000
--- a/core/cortex-m/task.c
+++ /dev/null
@@ -1,1088 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Task scheduling / events module for Chrome EC operating system */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "link_defs.h"
-#include "panic.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-typedef union {
-	struct {
-		/*
-		 * Note that sp must be the first element in the task struct
-		 * for __switchto() to work.
-		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
-	};
-} task_;
-
-/* Value to store in unused stack */
-#define STACK_UNUSED_VALUE 0xdeadd00d
-
-/* declare task routine prototypes */
-#define TASK(n, r, d, s) void r(void *);
-void __idle(void);
-CONFIG_TASK_LIST
-CONFIG_TEST_TASK_LIST
-CONFIG_CTS_TASK_LIST
-#undef TASK
-
-/* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-};
-#undef TASK
-
-#ifdef CONFIG_TASK_PROFILING
-static uint64_t task_start_time; /* Time task scheduling started */
-/*
- * We only keep 32-bit values for exception start/end time, to avoid
- * accounting errors when we service interrupt when the timer wraps around.
- */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
-#endif
-
-extern void __switchto(task_ *from, task_ *to);
-extern int __task_start(int *task_stack_ready);
-
-#ifndef CONFIG_LOW_POWER_IDLE
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	while (1) {
-#ifdef CHIP_NPCX
-
-		/*
-		 * Using host access to make sure M4 core clock will
-		 * return when the eSPI accesses the Host modules if
-		 * CSAE bit is set. Please notice this symptom only
-		 * occurs at npcx5.
-		 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
-		/* Enable Host access wakeup */
-		SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
-#endif
-
-		/*
-		 * TODO (ML): A interrupt that occurs shortly before entering
-		 * idle mode starts getting services while the Core transitions
-		 * into idle mode. The results in a hard fault when the Core,
-		 * shortly therefore, resumes execution on exiting idle mode.
-		 * Workaround: Replace the idle function with the followings
-		 */
-		asm (
-			"cpsid i\n"             /* Disable interrupt */
-			"push {r0-r5}\n"        /* Save needed registers */
-			"wfi\n"                 /* Wait for int to enter idle */
-			"ldm %0, {r0-r5}\n"     /* Add a delay after WFI */
-			"pop {r0-r5}\n" /* Restore regs before enabling ints */
-			"isb\n"                 /* Flush the cpu pipeline */
-			"cpsie i\n" :: "r" (0x100A8000)  /* Enable interrupts */
-		);
-#else
-		/*
-		 * Wait for the next irq event.  This stops the CPU clock
-		 * (sleep / deep sleep, depending on chip config).
-		 */
-		asm("wfi");
-#endif
-	}
-}
-#endif /* !CONFIG_LOW_POWER_IDLE */
-
-static void task_exit_trap(void)
-{
-	int i = task_get_current();
-	cprints(CC_TASK, "Task %d (%s) exited!", i, task_names[i]);
-	/* Exited tasks simply sleep forever */
-	while (1)
-		task_wait_event(-1);
-}
-
-/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
-static const struct {
-	uint32_t r0;
-	uint32_t pc;
-	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-};
-#undef TASK
-
-/* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT];
-
-/* Reset constants and state for all tasks */
-#define TASK_RESET_SUPPORTED		BIT(31)
-#define TASK_RESET_LOCK			BIT(30)
-#define TASK_RESET_STATE_MASK		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_WAITERS_MASK		~TASK_RESET_STATE_MASK
-#define TASK_RESET_UNSUPPORTED		0
-#define TASK_RESET_STATE_LOCKED		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_STATE_UNLOCKED	TASK_RESET_SUPPORTED
-
-#ifdef CONFIG_TASK_RESET_LIST
-#define ENABLE_RESET(n) \
-	[TASK_ID_##n] = TASK_RESET_SUPPORTED,
-static uint32_t task_reset_state[TASK_ID_COUNT] = {
-#ifdef CONFIG_TASK_RESET_LIST
-	CONFIG_TASK_RESET_LIST
-#endif
-};
-#undef ENABLE_RESET
-#endif /* CONFIG_TASK_RESET_LIST */
-
-/* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
-BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK);
-
-/* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
-
-#undef TASK
-
-/* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[17];
-
-static task_ *current_task = (task_ *)scratchpad;
-
-/*
- * Should IRQs chain to svc_handler()?  This should be set if either of the
- * following is true:
- *
- * 1) Task scheduling has started, and task profiling is enabled.  Task
- * profiling does its tracking in svc_handler().
- *
- * 2) An event was set by an interrupt; this could result in a higher-priority
- * task unblocking.  After checking for a task switch, svc_handler() will clear
- * the flag (unless profiling is also enabled; then the flag remains set).
- */
-static int need_resched_or_profiling;
-
-/*
- * Bitmap of all tasks ready to be run.
- *
- * Start off with only the hooks task marked as ready such that all the modules
- * can do their init within a task switching context.  The hooks task will then
- * make a call to enable all tasks.
- */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
-/*
- * Initially allow only the HOOKS and IDLE task to run, regardless of ready
- * status, in order for HOOK_INIT to complete before other tasks.
- * task_enable_all_tasks() will open the flood gates.
- */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-
-static int start_called;  /* Has task swapping started */
-
-static inline task_ *__task_id_to_ptr(task_id_t id)
-{
-	return tasks + id;
-}
-
-void interrupt_disable(void)
-{
-	asm("cpsid i");
-}
-
-void interrupt_enable(void)
-{
-	asm("cpsie i");
-}
-
-inline int is_interrupt_enabled(void)
-{
-	int primask;
-
-	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
-
-	return !(primask & 0x1);
-}
-
-inline int in_interrupt_context(void)
-{
-	int ret;
-	asm("mrs %0, ipsr \n"             /* read exception number */
-	    "lsl %0, #23  \n":"=r"(ret)); /* exception bits are the 9 LSB */
-	return ret;
-}
-
-#ifdef CONFIG_TASK_PROFILING
-static inline int get_interrupt_context(void)
-{
-	int ret;
-	asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */
-	return ret & 0x1ff;               /* exception bits are the 9 LSB */
-}
-#endif
-
-task_id_t task_get_current(void)
-{
-#ifdef CONFIG_DEBUG_BRINGUP
-	/* If we haven't done a context switch then our task ID isn't valid */
-	ASSERT(current_task != (task_ *)scratchpad);
-#endif
-	return current_task - tasks;
-}
-
-uint32_t *task_get_event_bitmap(task_id_t tskid)
-{
-	task_ *tsk = __task_id_to_ptr(tskid);
-	return &tsk->events;
-}
-
-int task_start_called(void)
-{
-	return start_called;
-}
-
-/**
- * Scheduling system call
- */
-void svc_handler(int desched, task_id_t resched)
-{
-	task_ *current, *next;
-#ifdef CONFIG_TASK_PROFILING
-	int exc = get_interrupt_context();
-	uint32_t t;
-#endif
-
-	/*
-	 * Push the priority to -1 until the return, to avoid being
-	 * interrupted.
-	 */
-	asm volatile("cpsid f\n"
-		     "isb\n");
-
-#ifdef CONFIG_TASK_PROFILING
-	/*
-	 * SVCall isn't triggered via DECLARE_IRQ(), so it needs to track its
-	 * start time explicitly.
-	 */
-	if (exc == 0xb) {
-		exc_start_time = get_time().le.lo;
-		svc_calls++;
-	}
-#endif
-
-	current = current_task;
-
-#ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current->stack != STACK_UNUSED_VALUE) {
-		panic_printf("\n\nStack overflow in %s task!\n",
-			     task_names[current - tasks]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks);
-#endif
-	}
-#endif
-
-	if (desched && !current->events) {
-		/*
-		 * Remove our own ready bit (current - tasks is same as
-		 * task_get_current())
-		 */
-		tasks_ready &= ~(1 << (current - tasks));
-	}
-	ASSERT(resched <= TASK_ID_COUNT);
-	tasks_ready |= 1 << resched;
-
-	ASSERT(tasks_ready & tasks_enabled);
-	next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
-
-#ifdef CONFIG_TASK_PROFILING
-	/* Track time in interrupts */
-	t = get_time().le.lo;
-	exc_total_time += (t - exc_start_time);
-
-	/*
-	 * Bill the current task for time between the end of the last interrupt
-	 * and the start of this one.
-	 */
-	current->runtime += (exc_start_time - exc_end_time);
-	exc_end_time = t;
-#else
-	/*
-	 * Don't chain here from interrupts until the next time an interrupt
-	 * sets an event.
-	 */
-	need_resched_or_profiling = 0;
-#endif
-
-	/* Nothing to do */
-	if (next == current)
-		return;
-
-	/* Switch to new task */
-#ifdef CONFIG_TASK_PROFILING
-	task_switches++;
-#endif
-	current_task = next;
-	__switchto(current, next);
-}
-
-void __schedule(int desched, int resched)
-{
-	register int p0 asm("r0") = desched;
-	register int p1 asm("r1") = resched;
-
-	asm("svc 0"::"r"(p0),"r"(p1));
-}
-
-#ifdef CONFIG_TASK_PROFILING
-void __keep task_start_irq_handler(void *excep_return)
-{
-	/*
-	 * Get time before checking depth, in case this handler is
-	 * pre-empted.
-	 */
-	uint32_t t = get_time().le.lo;
-	int irq = get_interrupt_context() - 16;
-
-	/*
-	 * Track IRQ distribution.  No need for atomic add, because an IRQ
-	 * can't pre-empt itself.
-	 */
-	if (irq < ARRAY_SIZE(irq_dist))
-		irq_dist[irq]++;
-
-	/*
-	 * Continue iff a rescheduling event happened or profiling is active,
-	 * and we are not called from another exception (this must match the
-	 * logic for when we chain to svc_handler() below).
-	 */
-	if (!need_resched_or_profiling || (((uint32_t)excep_return & 0xf) == 1))
-		return;
-
-	exc_start_time = t;
-}
-#endif
-
-void __keep task_resched_if_needed(void *excep_return)
-{
-	/*
-	 * Continue iff a rescheduling event happened or profiling is active,
-	 * and we are not called from another exception.
-	 */
-	if (!need_resched_or_profiling || (((uint32_t)excep_return & 0xf) == 1))
-		return;
-
-	svc_handler(0, 0);
-}
-
-static uint32_t __wait_evt(int timeout_us, task_id_t resched)
-{
-	task_ *tsk = current_task;
-	task_id_t me = tsk - tasks;
-	uint32_t evt;
-	int ret __attribute__((unused));
-
-	/*
-	 * Scheduling task when interrupts are disabled will result in Forced
-	 * Hard Fault because:
-	 * - Disabling interrupt using 'cpsid i' also disables SVCall handler
-	 *   (because it has configurable priority)
-	 * - Escalation to Hard Fault (also known as 'priority escalation')
-	 *   occurs when handler for that fault is not enabled
-	 */
-	ASSERT(is_interrupt_enabled());
-	ASSERT(!in_interrupt_context());
-
-	if (timeout_us > 0) {
-		timestamp_t deadline = get_time();
-		deadline.val += timeout_us;
-		ret = timer_arm(deadline, me);
-		ASSERT(ret == EC_SUCCESS);
-	}
-	while (!(evt = atomic_clear(&tsk->events))) {
-		/* Remove ourself and get the next task in the scheduler */
-		__schedule(1, resched);
-		resched = TASK_ID_IDLE;
-	}
-	if (timeout_us > 0) {
-		timer_cancel(me);
-		/* Ensure timer event is clear, we no longer care about it */
-		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
-	}
-	return evt;
-}
-
-uint32_t task_set_event(task_id_t tskid, uint32_t event)
-{
-	task_ *receiver = __task_id_to_ptr(tskid);
-	ASSERT(receiver);
-
-	/* Set the event bit in the receiver message bitmap */
-	atomic_or(&receiver->events, event);
-
-	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context() || !is_interrupt_enabled()) {
-		/* The receiver might run again */
-		atomic_or(&tasks_ready, 1 << tskid);
-#ifndef CONFIG_TASK_PROFILING
-		if (start_called)
-			need_resched_or_profiling = 1;
-#endif
-	} else {
-		__schedule(0, tskid);
-	}
-
-	return 0;
-}
-
-uint32_t task_wait_event(int timeout_us)
-{
-	return __wait_evt(timeout_us, TASK_ID_IDLE);
-}
-
-uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint64_t deadline = get_time().val + timeout_us;
-	uint32_t events = 0;
-	int time_remaining_us = timeout_us;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(events & event_mask)) {
-		/* Collect events to re-post later */
-		events |= __wait_evt(time_remaining_us, TASK_ID_IDLE);
-
-		time_remaining_us = deadline - get_time().val;
-		if (timeout_us > 0 && time_remaining_us <= 0) {
-			/* Ensure we return a TIMER event if we timeout */
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-	}
-
-	/* Re-post any other events collected */
-	if (events & ~event_mask)
-		atomic_or(&current_task->events, events & ~event_mask);
-
-	return events & event_mask;
-}
-
-void task_enable_all_tasks(void)
-{
-	/* Mark all tasks as ready and able to run. */
-	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
-	/* Reschedule the highest priority task. */
-	if (is_interrupt_enabled())
-		__schedule(0, 0);
-}
-
-void task_enable_task(task_id_t tskid)
-{
-	atomic_or(&tasks_enabled, BIT(tskid));
-}
-
-void task_disable_task(task_id_t tskid)
-{
-	atomic_clear_bits(&tasks_enabled, BIT(tskid));
-
-	if (!in_interrupt_context() && is_interrupt_enabled() &&
-	    tskid == task_get_current())
-		__schedule(0, 0);
-}
-
-void task_enable_irq(int irq)
-{
-	CPU_NVIC_EN(irq / 32) = 1 << (irq % 32);
-}
-
-void __keep task_disable_irq(int irq)
-{
-	CPU_NVIC_DIS(irq / 32) = 1 << (irq % 32);
-}
-
-void task_clear_pending_irq(int irq)
-{
-	CPU_NVIC_UNPEND(irq / 32) = 1 << (irq % 32);
-}
-
-void task_trigger_irq(int irq)
-{
-	CPU_NVIC_SWTRIG = irq;
-}
-
-static uint32_t init_task_context(task_id_t id)
-{
-	uint32_t *sp;
-	/* Stack size in words */
-	uint32_t ssize = tasks_init[id].stack_size / 4;
-
-	/*
-	 * Update stack used by first frame: 8 words for the normal
-	 * stack, plus 8 for R4-R11. Even if using FPU, the first frame
-	 * does not store FP regs.
-	 */
-	sp = tasks[id].stack + ssize - 16;
-	tasks[id].sp = (uint32_t)sp;
-
-	/* Initial context on stack (see __switchto()) */
-	sp[8] = tasks_init[id].r0;          /* r0 */
-	sp[13] = (uint32_t)task_exit_trap;  /* lr */
-	sp[14] = tasks_init[id].pc;         /* pc */
-	sp[15] = 0x01000000;                /* psr */
-
-	/* Fill unused stack; also used to detect stack overflow. */
-	for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++)
-		*sp = STACK_UNUSED_VALUE;
-
-	return ssize;
-}
-
-#ifdef CONFIG_TASK_RESET_LIST
-
-/*
- * Re-initializes a task stack to its initial state, and marks it ready.
- * The task reset lock must be held prior to calling this function.
- */
-static void do_task_reset(task_id_t id)
-{
-	interrupt_disable();
-	init_task_context(id);
-	tasks_ready |= 1 << id;
-	/* TODO: Clear all pending events? */
-	interrupt_enable();
-}
-
-/* We can't pass a parameter to a deferred call. Use this instead. */
-/* Mask of task IDs waiting to be reset. */
-static uint32_t deferred_reset_task_ids;
-
-/* Tasks may call this function if they want to reset themselves. */
-static void deferred_task_reset(void)
-{
-	while (deferred_reset_task_ids) {
-		task_id_t reset_id = __fls(deferred_reset_task_ids);
-
-		atomic_clear_bits(&deferred_reset_task_ids, 1 << reset_id);
-		do_task_reset(reset_id);
-	}
-}
-DECLARE_DEFERRED(deferred_task_reset);
-
-/*
- * Helper for updating task_reset state atomically. Checks the current state,
- * and if it matches if_value, updates the state to new_value, and returns
- * TRUE.
- */
-static int update_reset_state(uint32_t *state,
-			      uint32_t if_value,
-			      uint32_t to_value)
-{
-	int update;
-
-	interrupt_disable();
-	update = *state == if_value;
-	if (update)
-		*state = to_value;
-	interrupt_enable();
-
-	return update;
-}
-
-/*
- * Helper that acquires the reset lock iff it is not currently held.
- * Returns TRUE if the lock was acquired.
- */
-static inline int try_acquire_reset_lock(uint32_t *state)
-{
-	return update_reset_state(state,
-				  /* if the lock is not held */
-				  TASK_RESET_STATE_UNLOCKED,
-				  /* acquire it */
-				  TASK_RESET_STATE_LOCKED);
-}
-
-/*
- * Helper that releases the reset lock iff it is currently held, and there
- * are no pending resets. Returns TRUE if the lock was released.
- */
-static inline int try_release_reset_lock(uint32_t *state)
-{
-	return update_reset_state(state,
-				  /* if the lock is held, with no waiters */
-				  TASK_RESET_STATE_LOCKED,
-				  /* release it */
-				  TASK_RESET_STATE_UNLOCKED);
-}
-
-/*
- * Helper to cause the current task to sleep indefinitely; useful if the
- * calling task just needs to block until it is reset.
- */
-static inline void sleep_forever(void)
-{
-	while (1)
-		usleep(-1);
-}
-
-void task_enable_resets(void)
-{
-	task_id_t id = task_get_current();
-	uint32_t *state = &task_reset_state[id];
-
-	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id: %d",
-			__func__, id);
-		return;
-	}
-
-	/*
-	 * A correctly written resettable task will only call this function
-	 * if resets are currently disabled; this implies that this task
-	 * holds the reset lock.
-	 */
-
-	if (*state == TASK_RESET_STATE_UNLOCKED) {
-		cprints(CC_TASK,
-			"%s called, but resets already enabled, id: %d",
-			__func__, id);
-		return;
-	}
-
-	/*
-	 * Attempt to release the lock. If we cannot, it means there are tasks
-	 * waiting for a reset.
-	 */
-	if (try_release_reset_lock(state))
-		return;
-
-	/* People are waiting for us to reset; schedule a reset. */
-	atomic_or(&deferred_reset_task_ids, 1 << id);
-	/*
-	 * This will always trigger a deferred call after our new ID was
-	 * written. If the hook call is currently executing, it will run
-	 * again.
-	 */
-	hook_call_deferred(&deferred_task_reset_data, 0);
-	/* Wait to be reset. */
-	sleep_forever();
-}
-
-void task_disable_resets(void)
-{
-	task_id_t id = task_get_current();
-	uint32_t *state = &task_reset_state[id];
-
-	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id %d",
-			__func__, id);
-		return;
-	}
-
-	/*
-	 * A correctly written resettable task will only call this function
-	 * if resets are currently enabled; this implies that this task does
-	 * not hold the reset lock.
-	 */
-
-	if (try_acquire_reset_lock(state))
-		return;
-
-	/*
-	 * If we can't acquire the lock, we are about to be reset by another
-	 * task.
-	 */
-	sleep_forever();
-}
-
-int task_reset_cleanup(void)
-{
-	task_id_t id = task_get_current();
-	uint32_t *state = &task_reset_state[id];
-
-	/*
-	 * If the task has never started before, state will be
-	 * TASK_RESET_ENABLED.
-	 *
-	 * If the task was reset, the TASK_RESET_LOCK bit will be set, and
-	 * there may additionally be bits representing tasks we must notify
-	 * that we have reset.
-	 */
-
-	/*
-	 * Only this task can unset the lock bit so we can read this safely,
-	 * even though other tasks may be modifying the state to add themselves
-	 * as waiters.
-	 */
-	int cleanup_req = *state & TASK_RESET_LOCK;
-
-	/*
-	 * Attempt to release the lock. We can only do this when there are no
-	 * tasks waiting to be notified that we have been reset, so we loop
-	 * until no tasks are waiting.
-	 *
-	 * Other tasks may still be trying to reset us at this point; if they
-	 * do, they will add themselves to the list of tasks we must notify. We
-	 * will simply notify them (multiple times if necessary) until we are
-	 * free to unlock.
-	 */
-	if (cleanup_req) {
-		while (!try_release_reset_lock(state)) {
-			/* Find the first waiter to notify. */
-			task_id_t notify_id = __fls(
-			    *state & TASK_RESET_WAITERS_MASK);
-			/*
-			 * Remove the task from waiters first, so that
-			 * when it wakes after being notified, it is in
-			 * a consistent state (it should not be waiting
-			 * to be notified and running).
-			 * After being notified, the task may try to
-			 * reset us again; if it does, it will just add
-			 * itself back to the list of tasks to notify,
-			 * and we will notify it again.
-			 */
-			atomic_clear_bits(state, 1 << notify_id);
-			/*
-			 * Skip any invalid ids set by tasks that
-			 * requested a non-blocking reset.
-			 */
-			if (notify_id < TASK_ID_COUNT)
-				task_set_event(notify_id,
-					       TASK_EVENT_RESET_DONE);
-		}
-	}
-
-	return cleanup_req;
-}
-
-int task_reset(task_id_t id, int wait)
-{
-	task_id_t current = task_get_current();
-	uint32_t *state = &task_reset_state[id];
-	uint32_t waiter_id;
-	int resets_disabled;
-
-	if (id == current)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * This value is only set at compile time, and will never be modified.
-	 */
-	if (*state == TASK_RESET_UNSUPPORTED)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * If we are not blocking for reset, we use an invalid task id to notify
-	 * the task that _someone_ wanted it to reset, but didn't want to be
-	 * notified when the reset is complete.
-	 */
-	waiter_id = 1 << (wait ? current : TASK_ID_COUNT);
-
-	/*
-	 * Try and take the lock. If we can't have it, just notify the task we
-	 * tried; it will reset itself when it next tries to release the lock.
-	 */
-	interrupt_disable();
-	resets_disabled = *state & TASK_RESET_LOCK;
-	if (resets_disabled)
-		*state |= waiter_id;
-	else
-		*state |= TASK_RESET_LOCK;
-	interrupt_enable();
-
-	if (!resets_disabled) {
-		/* We got the lock, do the reset immediately. */
-		do_task_reset(id);
-	} else if (wait) {
-		/*
-		 * We couldn't get the lock, and have been asked to block for
-		 * reset. We have asked the task to reset itself; it will notify
-		 * us when it has.
-		 */
-		task_wait_event_mask(TASK_EVENT_RESET_DONE, -1);
-	}
-
-	return EC_SUCCESS;
-}
-
-#endif /* CONFIG_TASK_RESET_LIST */
-
-/*
- * Initialize IRQs in the NVIC and set their priorities as defined by the
- * DECLARE_IRQ statements.
- */
-static void __nvic_init_irqs(void)
-{
-	/* Get the IRQ priorities section from the linker */
-	int exc_calls = __irqprio_end - __irqprio;
-	int i;
-
-	/* Mask and clear all pending interrupts */
-	for (i = 0; i < 5; i++) {
-		CPU_NVIC_DIS(i) = 0xffffffff;
-		CPU_NVIC_UNPEND(i) = 0xffffffff;
-	}
-
-	/*
-	 * Re-enable global interrupts in case they're disabled.  On a reboot,
-	 * they're already enabled; if we've jumped here from another image,
-	 * they're not.
-	 */
-	interrupt_enable();
-
-	/* Set priorities */
-	for (i = 0; i < exc_calls; i++) {
-		cpu_set_interrupt_priority(__irqprio[i].irq,
-					   __irqprio[i].priority);
-	}
-}
-
-void mutex_lock(struct mutex *mtx)
-{
-	uint32_t value;
-	uint32_t id;
-
-	/*
-	 * mutex_lock() must not be used in interrupt context (because we wait
-	 * if there is contention).
-	 */
-	ASSERT(!in_interrupt_context());
-
-	/*
-	 * Task ID is not valid before task_start() (since current_task is
-	 * scratchpad), and no need for mutex locking before task switching has
-	 * begun.
-	 */
-	if (!task_start_called())
-		return;
-
-	id = 1 << task_get_current();
-
-	atomic_or(&mtx->waiters, id);
-
-	do {
-		/* Try to get the lock (set 1 into the lock field) */
-		__asm__ __volatile__("   ldrex   %0, [%1]\n"
-				     "   teq     %0, #0\n"
-				     "   it eq\n"
-				     "   strexeq %0, %2, [%1]\n"
-				     : "=&r" (value)
-				     : "r" (&mtx->lock), "r" (2) : "cc");
-		/*
-		 * "value" is equals to 1 if the store conditional failed,
-		 * 2 if somebody else owns the mutex, 0 else.
-		 */
-		if (value == 2)
-			/* Contention on the mutex */
-			task_wait_event_mask(TASK_EVENT_MUTEX, 0);
-	} while (value);
-
-	atomic_clear_bits(&mtx->waiters, id);
-}
-
-void mutex_unlock(struct mutex *mtx)
-{
-	uint32_t waiters;
-	task_ *tsk = current_task;
-
-	/*
-	 * Add a critical section to keep the unlock and the snapshotting of
-	 * waiters atomic in case a task switching occurs between them.
-	 */
-	interrupt_disable();
-	waiters = mtx->waiters;
-	mtx->lock = 0;
-	interrupt_enable();
-
-	while (waiters) {
-		task_id_t id = __fls(waiters);
-		waiters &= ~BIT(id);
-
-		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX);
-	}
-
-	/* Ensure no event is remaining from mutex wake-up */
-	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
-}
-
-void task_print_list(void)
-{
-	int i;
-
-	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
-
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
-		uint32_t *sp;
-
-		int stackused = tasks_init[i].stack_size;
-
-		for (sp = tasks[i].stack;
-		     sp < (uint32_t *)tasks[i].sp && *sp == STACK_UNUSED_VALUE;
-		     sp++)
-			stackused -= sizeof(uint32_t);
-
-		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
-			 stackused, tasks_init[i].stack_size);
-		cflush();
-	}
-}
-
-int command_task_info(int argc, char **argv)
-{
-#ifdef CONFIG_TASK_PROFILING
-	int total = 0;
-	int i;
-#endif
-
-	task_print_list();
-
-#ifdef CONFIG_TASK_PROFILING
-	ccputs("IRQ counts by type:\n");
-	cflush();
-	for (i = 0; i < ARRAY_SIZE(irq_dist); i++) {
-		if (irq_dist[i]) {
-			ccprintf("%4d %8d\n", i, irq_dist[i]);
-			total += irq_dist[i];
-		}
-	}
-	ccprintf("Service calls:          %11d\n", svc_calls);
-	ccprintf("Total exceptions:       %11d\n", total + svc_calls);
-	ccprintf("Task switches:          %11d\n", task_switches);
-	ccprintf("Task switching started: %11.6lld s\n", task_start_time);
-	ccprintf("Time in tasks:          %11.6lld s\n",
-		 get_time().val - task_start_time);
-	ccprintf("Time in exceptions:     %11.6lld s\n", exc_total_time);
-#endif
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
-			     "Print task info");
-
-#ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
-{
-	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
-	} else {
-		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
-		__schedule(0, 0);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
-			"Print/set ready tasks");
-#endif
-
-void task_pre_init(void)
-{
-	uint32_t *stack_next = (uint32_t *)task_stacks;
-	int i;
-
-	/* Fill the task memory with initial values */
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		tasks[i].stack = stack_next;
-		stack_next += init_task_context(i);
-	}
-
-	/*
-	 * Fill in guard value in scratchpad to prevent stack overflow
-	 * detection failure on the first context switch.  This works because
-	 * the first word in the scratchpad is where the switcher will store
-	 * sp, so it's ok to blow away.
-	 */
-	((task_ *)scratchpad)->stack = (uint32_t *)scratchpad;
-	*(uint32_t *)scratchpad = STACK_UNUSED_VALUE;
-
-	/* Initialize IRQs */
-	__nvic_init_irqs();
-}
-
-void task_clear_fp_used(void)
-{
-	int ctrl;
-
-	/* Clear the CONTROL.FPCA bit, which represents FP context active. */
-	asm volatile("mrs %0, control" : "=r"(ctrl));
-	ctrl &= ~0x4;
-	asm volatile("msr control, %0" : : "r"(ctrl));
-
-	/* Flush pipeline before returning. */
-	asm volatile("isb");
-}
-
-int task_start(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	timestamp_t t = get_time();
-
-	task_start_time = t.val;
-	exc_end_time = t.le.lo;
-#endif
-	start_called = 1;
-
-	return __task_start(&need_resched_or_profiling);
-}
-
-#ifdef CONFIG_CMD_TASK_RESET
-static int command_task_reset(int argc, char **argv)
-{
-	task_id_t id;
-	char *e;
-
-	if (argc == 2) {
-		id = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-		ccprintf("Resetting task %d\n", id);
-		return task_reset(id, 1);
-	}
-
-	return EC_ERROR_PARAM_COUNT;
-}
-DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset,
-			"task_id",
-			"Reset a task");
-#endif  /* CONFIG_CMD_TASK_RESET */
diff --git a/core/cortex-m/uldivmod.S b/core/cortex-m/uldivmod.S
deleted file mode 120000
index 7047a8c5d4..0000000000
--- a/core/cortex-m/uldivmod.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
\ No newline at end of file
diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c
deleted file mode 100644
index 10b4b22422..0000000000
--- a/core/cortex-m/vecttable.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cortex-M CPU vector table
- */
-
-#ifndef ___INIT
-#define ___INIT
-#include "config.h"
-#include <task.h>
-#endif
-
-typedef void (*func)(void);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#if PASS == 1
-/* Default exception handler */
-void __attribute__((used, naked)) default_handler(void);
-void default_handler()
-{
-	asm(
-	".thumb_func\n"
-	"	b exception_panic"
-	);
-}
-
-#define table(x) x
-
-#define weak_with_default __attribute__((used,weak,alias("default_handler")))
-
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
-
-#define item(name) extern void name(void);
-#define null
-
-extern void stack_end(void); /* not technically correct, it's just a pointer */
-extern void reset(void);
-
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-/* Call default_handler if svc_handler is not found (task.c is not built) */
-void weak_with_default svc_handler(int desched, task_id_t resched);
-#pragma GCC diagnostic pop
-
-/*
- * SVC handler helper
- *
- * Work around issue where a late exception can corrupt r0 to r3,
- * see section 2.7 (svc) of Cortex-M3 Application Note 179:
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0179b/AppsNote179.pdf
- *
- * This approach differs slightly from the one in the document,
- * it only loads r0 (desched) and r1 (resched) for svc_handler.
- */
-void __attribute__((used,naked)) svc_helper_handler(void);
-void svc_helper_handler()
-{
-	asm(
-	".thumb_func\n"
-	"	tst lr, #4		/* see if called from supervisor mode */\n"
-	"	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
-	"	it ne\n"
-	"	mrsne r2, psp\n"
-	"	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
-	"	ldr r0, [r2]\n"
-	"	b %0			/* call svc_handler */\n"
-	:
-	: "i"(svc_handler)
-	);
-}
-
-#endif /* PASS 1 */
-
-#if PASS == 2
-#undef table
-#undef vec
-#undef irq
-#undef item
-#undef null
-
-/* number of elements before the first irq vector */
-#define IRQ_OFFSET 16
-/* element in the table that is null: extra IRQs are routed there,
- * then finally overwritten
- */
-#define IRQ_UNUSED_OFFSET 8
-
-/* Disable warning that "initializer overrides prior initialization of this
- * subobject", since we are explicitly doing this to handle the unused IRQs.
- */
-#ifdef __clang__
-#pragma clang diagnostic push
-#pragma clang diagnostic ignored "-Winitializer-overrides"
-#endif /* __clang__ */
-
-#define table(x)								\
-	const func vectors[] __attribute__((section(".text.vecttable"))) = {	\
-		x								\
-		[IRQ_UNUSED_OFFSET] = null					\
-	};
-
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
-
-#define item(name) name,
-#define null (void*)0,
-#endif /* PASS 2 */
-
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	item(svc_helper_handler)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-	irq(32)
-	irq(33)
-	irq(34)
-	irq(35)
-	irq(36)
-	irq(37)
-	irq(38)
-	irq(39)
-	irq(40)
-	irq(41)
-	irq(42)
-	irq(43)
-	irq(44)
-	irq(45)
-	irq(46)
-	irq(47)
-	irq(48)
-	irq(49)
-	irq(50)
-	irq(51)
-	irq(52)
-	irq(53)
-	irq(54)
-	irq(55)
-	irq(56)
-	irq(57)
-	irq(58)
-	irq(59)
-	irq(60)
-	irq(61)
-	irq(62)
-	irq(63)
-	irq(64)
-	irq(65)
-	irq(66)
-	irq(67)
-	irq(68)
-	irq(69)
-	irq(70)
-	irq(71)
-	irq(72)
-	irq(73)
-	irq(74)
-	irq(75)
-	irq(76)
-	irq(77)
-	irq(78)
-	irq(79)
-	irq(80)
-	irq(81)
-	irq(82)
-	irq(83)
-	irq(84)
-	irq(85)
-	irq(86)
-	irq(87)
-	irq(88)
-	irq(89)
-	irq(90)
-	irq(91)
-	irq(92)
-	irq(93)
-	irq(94)
-	irq(95)
-	irq(96)
-	irq(97)
-	irq(98)
-	irq(99)
-	irq(100)
-	irq(101)
-	irq(102)
-	irq(103)
-	irq(104)
-	irq(105)
-	irq(106)
-	irq(107)
-	irq(108)
-	irq(109)
-	irq(110)
-	irq(111)
-	irq(112)
-	irq(113)
-	irq(114)
-	irq(115)
-	irq(116)
-	irq(117)
-	irq(118)
-	irq(119)
-	irq(120)
-	irq(121)
-	irq(122)
-	irq(123)
-	irq(124)
-	irq(125)
-	irq(126)
-	irq(127)
-	irq(128)
-	irq(129)
-	irq(130)
-	irq(131)
-	irq(132)
-	irq(133)
-	irq(134)
-	irq(135)
-	irq(136)
-	irq(137)
-	irq(138)
-	irq(139)
-	irq(140)
-	irq(141)
-	irq(142)
-	irq(143)
-	irq(144)
-	irq(145)
-	irq(146)
-	irq(147)
-	irq(148)
-	irq(149)
-	irq(150)
-	irq(151)
-	irq(152)
-	irq(153)
-	irq(154)
-	irq(155)
-	irq(156)
-	irq(157)
-	irq(158)
-	irq(159)
-	irq(160)
-	irq(161)
-	irq(162)
-	irq(163)
-	irq(164)
-	irq(165)
-	irq(166)
-	irq(167)
-	irq(168)
-	irq(169)
-	irq(170)
-	irq(171)
-	irq(172)
-	irq(173)
-	irq(174)
-	irq(175)
-	irq(176)
-	irq(177)
-	irq(178)
-	irq(179)
-	irq(180)
-	irq(181)
-	irq(182)
-	irq(183)
-	irq(184)
-	irq(185)
-	irq(186)
-	irq(187)
-	irq(188)
-	irq(189)
-	irq(190)
-	irq(191)
-	irq(192)
-	irq(193)
-	irq(194)
-	irq(195)
-	irq(196)
-	irq(197)
-	irq(198)
-	irq(199)
-	irq(200)
-	irq(201)
-	irq(202)
-	irq(203)
-	irq(204)
-	irq(205)
-	irq(206)
-	irq(207)
-	irq(208)
-	irq(209)
-	irq(210)
-	irq(211)
-	irq(212)
-	irq(213)
-	irq(214)
-	irq(215)
-	irq(216)
-	irq(217)
-	irq(218)
-	irq(219)
-	irq(220)
-	irq(221)
-	irq(222)
-	irq(223)
-	irq(224)
-	irq(225)
-	irq(226)
-	irq(227)
-	irq(228)
-	irq(229)
-	irq(230)
-	irq(231)
-	irq(232)
-	irq(233)
-	irq(234)
-	irq(235)
-	irq(236)
-	irq(237)
-	irq(238)
-	irq(239)
-	irq(240)
-	irq(241)
-	irq(242)
-	irq(243)
-	irq(244)
-	irq(245)
-	irq(246)
-	irq(247)
-	irq(248)
-	irq(249)
-	irq(250)
-	irq(251)
-	irq(252)
-	irq(253)
-	irq(254)
-)
-
-#if PASS == 2
-#ifdef __clang__
-#pragma clang diagnostic pop
-#endif /* __clang__ */
-#endif
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "vecttable.c"
-#endif
diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c
deleted file mode 100644
index c9faf54b2b..0000000000
--- a/core/cortex-m/watchdog.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog common code */
-
-#include "common.h"
-#include "cpu.h"
-#include "panic.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * As defined by Armv7-M Reference Manual B1.5.6 "Exception Entry Behavior",
- * the structure of the saved context on the stack is:
- * r0, r1, r2, r3, r12, lr, pc, psr, ...
- */
-#define STACK_IDX_REG_LR 5
-#define STACK_IDX_REG_PC 6
-
-void __keep watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
-{
-	uint32_t psp;
-	uint32_t *stack;
-
-	asm("mrs %0, psp" : "=r"(psp));
-	if ((excep_lr & 0xf) == 1) {
-		/* we were already in exception context */
-		stack = (uint32_t *)excep_sp;
-	} else {
-		/* we were in task context */
-		stack = (uint32_t *)psp;
-	}
-
-	panic_set_reason(PANIC_SW_WATCHDOG, stack[STACK_IDX_REG_PC],
-			 (excep_lr & 0xf) == 1 ? 0xff : task_get_current());
-
-	/*
-	 * This is our last breath, the last opportunity to sort out all
-	 * matters. Flush and invalidate D-cache if cache enabled.
-	 */
-	if (IS_ENABLED(CONFIG_ARMV7M_CACHE))
-		cpu_clean_invalidate_dcache();
-
-	panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ",
-		     stack[STACK_IDX_REG_PC], stack[STACK_IDX_REG_LR], psp);
-	if ((excep_lr & 0xf) == 1)
-		panic_puts("(exc) ###\n");
-	else
-		panic_printf("(task %d) ###\n", task_get_current());
-
-	/* If we are blocked in a high priority IT handler, the following debug
-	 * messages might not appear but they are useless in that situation. */
-	timer_print_info();
-	task_print_list();
-}
diff --git a/core/cortex-m0/__builtin.c b/core/cortex-m0/__builtin.c
deleted file mode 100644
index 4bf495a011..0000000000
--- a/core/cortex-m0/__builtin.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-/*
- * __builtin_ffs:
- * Returns one plus the index of the least significant 1-bit of x,
- * or if x is zero, returns zero.
- */
-int __keep __ffssi2(int x)
-{
-	return 32 - __builtin_clz(x & -x);
-}
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h
deleted file mode 100644
index 0c58e71e41..0000000000
--- a/core/cortex-m0/atomic.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atomic operations for ARMv6-M */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include "common.h"
-
-typedef int atomic_t;
-typedef atomic_t atomic_val_t;
-
-/**
- * Implements atomic arithmetic operations on 32-bit integers.
- *
- * There is no load/store exclusive on ARMv6-M, just disable interrupts
- */
-#define ATOMIC_OP(asm_op, a, v)					\
-({								\
-	uint32_t reg0, reg1;					\
-								\
-	__asm__ __volatile__("   cpsid i\n"			\
-			     "   ldr  %0, [%2]\n"		\
-			     "   mov  %1, %0\n"			\
-			     #asm_op" %0, %0, %3\n"		\
-			     "   str  %0, [%2]\n"		\
-			     "   cpsie i\n"			\
-			     : "=&l"(reg0), "=&l"(reg1)		\
-			     : "l"(a), "r"(v)			\
-			     : "cc", "memory");			\
-	reg1;							\
-})
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	return ATOMIC_OP(bic, addr, bits);
-}
-
-static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
-{
-	return ATOMIC_OP(orr, addr, bits);
-}
-
-static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
-{
-	return ATOMIC_OP(add, addr, value);
-}
-
-static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
-{
-	return ATOMIC_OP(sub, addr, value);
-}
-
-static inline atomic_val_t atomic_clear(atomic_t *addr)
-{
-	atomic_t ret;
-
-	__asm__ __volatile__("   mov     %2, #0\n"
-			     "   cpsid   i\n"
-			     "   ldr     %0, [%1]\n"
-			     "   str     %2, [%1]\n"
-			     "   cpsie   i\n"
-			     : "=&l" (ret)
-			     : "l" (addr), "r" (0)
-			     : "cc", "memory");
-
-	return ret;
-}
-
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
deleted file mode 100644
index b0136f347e..0000000000
--- a/core/cortex-m0/build.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Cortex-M0 core OS files build
-#
-
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
-# CPU specific compilation flags
-CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog
-CFLAGS_CPU+=-mno-unaligned-access
-
-ifneq ($(CONFIG_LTO),)
-CFLAGS_CPU+=-flto
-LDFLAGS_EXTRA+=-flto
-endif
-
-core-y=cpu.o debug.o init.o thumb_case.o div.o lmul.o ldivmod.o mula.o uldivmod.o
-core-y+=vecttable.o __builtin.o
-core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
-core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
-
-dirs-y += core/$(CORE)/curve25519
-
-core-$(CONFIG_CURVE25519)+=curve25519/mpy121666.o
-core-$(CONFIG_CURVE25519)+=curve25519/reduce25519.o
-core-$(CONFIG_CURVE25519)+=curve25519/mul.o
-core-$(CONFIG_CURVE25519)+=curve25519/scalarmult.o
-core-$(CONFIG_CURVE25519)+=curve25519/sqr.o
-
-core-$(CONFIG_WATCHDOG)+=watchdog.o
diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h
deleted file mode 100644
index c31adc471c..0000000000
--- a/core/cortex-m0/config_core.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CORE_H
-#define __CROS_EC_CONFIG_CORE_H
-
-/* Linker binary architecture and format */
-#define BFD_ARCH arm
-#define BFD_FORMAT "elf32-littlearm"
-
-/* Emulate the CLZ/CTZ instructions since the CPU core is lacking support */
-#define CONFIG_SOFTWARE_CLZ
-#define CONFIG_SOFTWARE_CTZ
-#define CONFIG_SOFTWARE_PANIC
-
-#define CONFIG_ASSEMBLY_MULA32
-
-#endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/cortex-m0/cpu.c b/core/cortex-m0/cpu.c
deleted file mode 100644
index b354cc03e2..0000000000
--- a/core/cortex-m0/cpu.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Set up the Cortex-M0 core
- */
-
-#include "cpu.h"
-
-void cpu_init(void)
-{
-	/* Catch unaligned access */
-	CPU_NVIC_CCR |= CPU_NVIC_CCR_UNALIGN_TRAP;
-
-	/* Set supervisor call (SVC) to priority 0 */
-	CPU_NVIC_SHCSR2 = 0;
-
-	/* Set lowest priority for PendSV */
-	CPU_NVIC_SHCSR3 = (0xff << 16);
-}
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
deleted file mode 100644
index ac184090f9..0000000000
--- a/core/cortex-m0/cpu.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for Cortex-M0 processor
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-#include <stdint.h>
-#include "compile_time_macros.h"
-
-/* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
-
-/* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100)
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180)
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280)
-#define CPU_NVIC_ISPR(x)       CPUREG(0xe000e200)
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
-
-/* System Control Block */
-#define CPU_SCB_ICSR           CPUREG(0xe000ed04)
-
-/* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0U)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
-/* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR2        CPUREG(0xe000ed1c)
-#define CPU_NVIC_SHCSR3        CPUREG(0xe000ed20)
-
-#define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
-
-/* Set up the cpu to detect faults */
-void cpu_init(void);
-
-/* Set the priority of the given IRQ in the NVIC (0 is highest). */
-static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
-{
-	const uint32_t prio_shift = irq % 4 * 8 + 6;
-
-	if (priority > 3)
-		priority = 3;
-
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(3 << prio_shift)) |
-		(priority << prio_shift);
-}
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/curve25519 b/core/cortex-m0/curve25519
deleted file mode 120000
index ee9cb3b4a9..0000000000
--- a/core/cortex-m0/curve25519
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/unacl-curve25519/core/cortex-m0/curve25519
\ No newline at end of file
diff --git a/core/cortex-m0/debug.c b/core/cortex-m0/debug.c
deleted file mode 120000
index 3cada87897..0000000000
--- a/core/cortex-m0/debug.c
+++ /dev/null
@@ -1 +0,0 @@
-../cortex-m/debug.c
\ No newline at end of file
diff --git a/core/cortex-m0/debug.h b/core/cortex-m0/debug.h
deleted file mode 120000
index d79be16190..0000000000
--- a/core/cortex-m0/debug.h
+++ /dev/null
@@ -1 +0,0 @@
-../cortex-m/debug.h
\ No newline at end of file
diff --git a/core/cortex-m0/div.S b/core/cortex-m0/div.S
deleted file mode 120000
index 776b7d2405..0000000000
--- a/core/cortex-m0/div.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m0/div.S
\ No newline at end of file
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
deleted file mode 100644
index bc461b90de..0000000000
--- a/core/cortex-m0/ec.lds.S
+++ /dev/null
@@ -1,360 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "rwsig.h"
-
-#define STRINGIFY0(name) #name
-#define STRINGIFY(name) STRINGIFY0(name)
-
-#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
-
-#define FW_SIZE_(section) CONFIG_##section##_SIZE
-#define FW_SIZE(section) FW_SIZE_(section)
-
-OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
-OUTPUT_ARCH(BFD_ARCH)
-ENTRY(reset)
-
-MEMORY
-{
-#ifdef CONFIG_SHAREDLIB
-	SHARED_LIB (rx) : ORIGIN = FW_OFF(SHAREDLIB),
-			  LENGTH = FW_SIZE(SHAREDLIB)
-#endif
-	FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
-	IRAM (rw)  : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-
-#ifdef CONFIG_CHIP_MEMORY_REGIONS
-#define REGION(name, attr, start, size) \
-	name(attr) : ORIGIN = (start), LENGTH = (size)
-#include "memory_regions.inc"
-#undef REGION
-#endif /* CONFIG_MEMORY_REGIONS */
-}
-
-SECTIONS
-{
-#ifdef CONFIG_SHAREDLIB
-	.roshared : {
-		KEEP(*(.roshared*))
-	} > SHARED_LIB
-#endif
-	.text : {
-		*(.text.vecttable)
-		. = ALIGN(4);
-		__image_data_offset = .;
-		KEEP(*(.rodata.ver))
-
-		. = ALIGN(4);
-		KEEP(*(.rodata.pstate))
-
-		. = ALIGN(4);
-		STRINGIFY(OUTDIR/core/CORE/init.o) (.text)
-		*(.text*)
-	} > FLASH
-
-	. = ALIGN(4);
-	.rodata : {
-		/* Symbols defined here are declared in link_defs.h */
-		__irqprio = .;
-		KEEP(*(.rodata.irqprio))
-		__irqprio_end = .;
-
-		. = ALIGN(4);
-		__cmds = .;
-		KEEP(*(SORT(.rodata.cmds*)))
-		__cmds_end = .;
-
-		. = ALIGN(4);
-		__extension_cmds = .;
-		KEEP(*(.rodata.extensioncmds))
-		__extension_cmds_end = .;
-
-		. = ALIGN(4);
-		__hcmds = .;
-		KEEP(*(SORT(.rodata.hcmds*)))
-		__hcmds_end = .;
-
-		. = ALIGN(4);
-		__mkbp_evt_srcs = .;
-		KEEP(*(.rodata.evtsrcs))
-		__mkbp_evt_srcs_end = .;
-
-		. = ALIGN(4);
-		__hooks_init = .;
-		KEEP(*(.rodata.HOOK_INIT))
-		__hooks_init_end = .;
-
-		__hooks_pre_freq_change = .;
-		KEEP(*(.rodata.HOOK_PRE_FREQ_CHANGE))
-		__hooks_pre_freq_change_end = .;
-
-		__hooks_freq_change = .;
-		KEEP(*(.rodata.HOOK_FREQ_CHANGE))
-		__hooks_freq_change_end = .;
-
-		__hooks_sysjump = .;
-		KEEP(*(.rodata.HOOK_SYSJUMP))
-		__hooks_sysjump_end = .;
-
-		__hooks_chipset_pre_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_PRE_INIT))
-		__hooks_chipset_pre_init_end = .;
-
-		__hooks_chipset_startup = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_STARTUP))
-		__hooks_chipset_startup_end = .;
-
-		__hooks_chipset_resume = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME))
-		__hooks_chipset_resume_end = .;
-
-		__hooks_chipset_suspend = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND))
-		__hooks_chipset_suspend_end = .;
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		__hooks_chipset_resume_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME_INIT))
-		__hooks_chipset_resume_init_end = .;
-
-		__hooks_chipset_suspend_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND_COMPLETE))
-		__hooks_chipset_suspend_complete_end = .;
-#endif
-
-		__hooks_chipset_shutdown = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN))
-		__hooks_chipset_shutdown_end = .;
-
-		__hooks_chipset_shutdown_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
-		__hooks_chipset_shutdown_complete_end = .;
-
-		__hooks_chipset_hard_off = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
-		__hooks_chipset_hard_off_end = .;
-
-		__hooks_chipset_reset = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
-		__hooks_chipset_reset_end = .;
-
-		__hooks_ac_change = .;
-		KEEP(*(.rodata.HOOK_AC_CHANGE))
-		__hooks_ac_change_end = .;
-
-		__hooks_lid_change = .;
-		KEEP(*(.rodata.HOOK_LID_CHANGE))
-		__hooks_lid_change_end = .;
-
-		__hooks_tablet_mode_change = .;
-		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
-		__hooks_tablet_mode_change_end = .;
-
-		__hooks_base_attached_change = .;
-		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
-		__hooks_base_attached_change_end = .;
-
-		__hooks_pwrbtn_change = .;
-		KEEP(*(.rodata.HOOK_POWER_BUTTON_CHANGE))
-		__hooks_pwrbtn_change_end = .;
-
-		__hooks_battery_soc_change = .;
-		KEEP(*(.rodata.HOOK_BATTERY_SOC_CHANGE))
-		__hooks_battery_soc_change_end = .;
-
-#ifdef CONFIG_USB_SUSPEND
-		__hooks_usb_change = .;
-		KEEP(*(.rodata.HOOK_USB_PM_CHANGE))
-		__hooks_usb_change_end = .;
-#endif
-
-		__hooks_tick = .;
-		KEEP(*(.rodata.HOOK_TICK))
-		__hooks_tick_end = .;
-
-		__hooks_second = .;
-		KEEP(*(.rodata.HOOK_SECOND))
-		__hooks_second_end = .;
-
-		__hooks_usb_pd_disconnect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_DISCONNECT))
-		__hooks_usb_pd_disconnect_end = .;
-
-		__hooks_usb_pd_connect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
-		__hooks_usb_pd_connect_end = .;
-
-		__deferred_funcs = .;
-		KEEP(*(.rodata.deferred))
-		__deferred_funcs_end = .;
-
-		__usb_desc = .;
-		KEEP(*(.rodata.usb_desc_conf))
-		KEEP(*(SORT(.rodata.usb_desc*)))
-		__usb_desc_end = .;
-		. = ALIGN(4);
-		KEEP(*(.rodata.usb_ep))
-		KEEP(*(.rodata.usb_ep.usb_ep_tx))
-		KEEP(*(.rodata.usb_ep.usb_ep_rx))
-		KEEP(*(.rodata.usb_ep.usb_ep_event))
-		KEEP(*(.rodata.usb_ep.usb_iface_request))
-
-		. = ALIGN(4);
-		*(.rodata*)
-
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-	ASSERT(0, "CONFIG_CHIP_INIT_ROM_REGION not supported by linker script")
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-		/*
-		 * This linker file does not yet support a separate ROM resident
-		 * section. Ensure the corresponding data objects are linked
-		 * into the .rodata section.
-		 */
-		. = ALIGN(4);
-		__init_rom_start = .;
-		*(.init.rom)
-		__init_rom_end = .;
-
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
-		. = ALIGN(64);
-		KEEP(*(.google))
-#endif
-		. = ALIGN(4);
-	} > FLASH
-
-	__data_lma_start = . ;
-	.vtable : {
-		/*
-		 * Vector table must be at the base of SRAM. The vector
-		 * table section contains a RAM copy of the vector table used on
-		 * STM chips for relocating the vector table.
-		 */
-		. = ALIGN(8);
-		*(.bss.vector_table)
-		. = ALIGN(8);
-	} > IRAM
-
-#ifdef CONFIG_PRESERVE_LOGS
-	.preserve_logs(NOLOAD) : {
-		/*
-		 * The size of the vector table is fixed. Thus, the address of
-		 * the preserved logs is also fixed.
-		 */
-		. = ALIGN(8);
-		*(SORT(.preserved_logs.*))
-		. = ALIGN(8);
-		__preserved_logs_end = .;
-	} > IRAM
-
-	ASSERT((SIZEOF(.vtable) + SIZEOF(.preserve_logs) + CONFIG_RAM_BASE) ==
-	       __preserved_logs_end,
-	       "preserve_logs must be right after vtable")
-#endif
-
-	.bss : {
-		. = ALIGN(8);
-		__bss_start = .;
-		/* Stacks must be 64-bit aligned */
-		. = ALIGN(8);
-		*(.bss.system_stack)
-		/* Rest of .bss takes care of its own alignment */
-		*(.bss)
-		*(.bss.slow)
-
-		/*
-		 * Reserve space for deferred function firing times.
-		 * Each time is a uint64_t, each func is a 32-bit pointer,
-		 * thus the scaling factor of two. The 8 byte alignment of
-		 * uint64_t is required by the ARM ABI.
-		 */
-		. = ALIGN(8);
-		__deferred_until = .;
-		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
-		__deferred_until_end = .;
-
-		. = ALIGN(4);
-		__bss_end = .;
-	} > IRAM
-
-	.data : AT(ADDR(.rodata) + SIZEOF(.rodata)) {
-		. = ALIGN(4);
-		__data_start = .;
-		*(.data.tasks)
-		*(.data)
-		. = ALIGN(4);
-		*(.iram.text)
-		. = ALIGN(4);
-		__data_end = .;
-
-		/*
-		 * Shared memory buffer must be at the end of preallocated
-		 * RAM, so it can expand to use all the remaining RAM.
-		 */
-		__shared_mem_buf = .;
-
-		/* NOTHING MAY GO AFTER THIS! */
-	} > IRAM
-
-	ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <=
-	       (CONFIG_RAM_BASE + CONFIG_RAM_SIZE),
-	       "Not enough space for shared memory.")
-
-	__ram_free = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE) -
-		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
-
-	/*
-	 * __flash_used is used in flash free calculations by the makefile.
-	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
-	 */
-	__flash_used = LOADADDR(.data) + SIZEOF(.data) - ORIGIN(FLASH);
-	__image_size = __flash_used;
-
-#ifdef CONFIG_FLASH_CROS
-        /*
-         * These linker labels are just for analysis and not used in the code.
-         */
-	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
-	__config_ro_size = CONFIG_RO_SIZE;
-	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
-	__config_rw_size = CONFIG_RW_SIZE;
-	__config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-#endif
-
-	/*
-	 * The linker won't notice if the .data section is too big to fit,
-	 * apparently because we're sending it into IRAM, not FLASH.
-	 * Verify that all sections linked into the FLASH region will fit.
-	 */
-	ASSERT((LENGTH(FLASH)
-#if defined(CONFIG_RWSIG) && defined(SECTION_IS_RO)
-	       - CONFIG_RO_PUBKEY_SIZE
-#endif
-#if defined(CONFIG_RWSIG) && defined(SECTION_IS_RW)
-	       - CONFIG_RW_SIG_SIZE
-#endif
-	       ) >= __flash_used,
-	       "No room left in the flash")
-
-	__image_size = __flash_used;
-
-#ifdef CONFIG_CHIP_MEMORY_REGIONS
-#define REGION(name, attr, start, size) \
-	.name(NOLOAD) : { \
-		__##name##_start = .; \
-		*(SORT(.name.*)) \
-	} > name
-#include "memory_regions.inc"
-#undef REGION
-#endif /* CONFIG_CHIP_MEMORY_REGIONS */
-
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
-    /DISCARD/ : { *(.google) }
-#endif
-    /DISCARD/ : { *(.ARM.*) }
-}
diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h
deleted file mode 100644
index 3acec557a7..0000000000
--- a/core/cortex-m0/include/fpu.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for ARMv6-M */
-
-#ifndef __CROS_EC_FPU_H
-#define __CROS_EC_FPU_H
-
-#endif  /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
deleted file mode 100644
index 5047d18380..0000000000
--- a/core/cortex-m0/init.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cortex-M0 CPU initialization
- */
-
-#include "config.h"
-
-#ifdef CHIP_FAMILY_STM32F0
-/* Allocate space for SRAM vector table at SRAM based address */
-.section .bss.vector_table
-sram_vtable: .skip (48*4)
-#endif
-
-.text
-.syntax unified
-.code 16
-
-.global reset
-.thumb_func
-reset:
-	/*
-	 * Ensure we're in privileged mode with main stack.  Necessary if
-	 * we've jumped directly here from another image after task_start().
-	 */
-	movs r0, #0          @ priv. mode / main stack / no floating point
-	msr control, r0
-	isb                  @ ensure the write is done
-
-	/* Clear BSS */
-	movs r0, #0
-	ldr  r1,_bss_start
-	ldr  r2,_bss_end
-bss_loop:
-	str  r0, [r1]
-	adds r1, #4
-	cmp  r1, r2
-	blt bss_loop
-
-#ifdef CHIP_FAMILY_STM32F0
-	/*
-	 * STM32F0 parts don't have the VTOR register for relocating
-	 * the vector table. Instead, we must copy the vector table from
-	 * flash into SRAM.
-	 */
-	ldr r1, =vectors
-	ldr r2, =sram_vtable
-	movs r0, #0
-vtable_loop:
-	ldr r3, [r1]
-	str r3, [r2]
-	adds r1, #4
-	adds r2, #4
-	adds r0, #1
-	cmp r0, #48
-	blt vtable_loop
-
-	/* Set SYSCFG_CFGR1 mem_mode to load vector table from SRAM */
-	movs r0, #3
-	ldr r1, =0x40010000
-	str r0, [r1]
-#else
-	/* Set the vector table on our current code */
-	ldr r1, =vectors
-	ldr r2, =0xE000ED08   /* VTOR register in SCB*/
-	str r1, [r2]
-#endif
-
-	/* Copy initialized data to Internal RAM */
-	ldr r0,_data_lma_start
-	ldr r1,_data_start
-	ldr r2,_data_end
-data_loop:
-	ldr  r3, [r0]
-	adds r0, #4
-	str  r3, [r1]
-	adds r1, #4
-	cmp  r1, r2
-	blt data_loop
-
-	/*
-	 * Set stack pointer.  Already done by Cortex-M hardware, but re-doing
-	 * this here allows software to jump directly to the reset vector.
-	 */
-	ldr r0, =stack_end
-	mov sp, r0
-
-	/* Jump to C code */
-	bl main
-
-	/* That should not return.  If it does, loop forever. */
-fini_loop:
-	b fini_loop
-
-/* Default exception handler */
-.thumb_func
-default_handler:
-	ldr r0, =exception_panic
-	bx r0
-
-.align 2
-_bss_start:
-.long __bss_start
-_bss_end:
-.long __bss_end
-_data_start:
-.long __data_start
-_data_end:
-.long __data_end
-_data_lma_start:
-.long __data_lma_start
-
-/* Mock functions to avoid linker complaints */
-.global __aeabi_unwind_cpp_pr0
-.global __aeabi_unwind_cpp_pr1
-.global __aeabi_unwind_cpp_pr2
-__aeabi_unwind_cpp_pr0:
-__aeabi_unwind_cpp_pr1:
-__aeabi_unwind_cpp_pr2:
-	bx lr
-
-/* Reserve space for system stack */
-.section .bss.system_stack
-stack_start:
-.space CONFIG_STACK_SIZE, 0
-stack_end:
-.global stack_end
-
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
deleted file mode 100644
index de36ef7623..0000000000
--- a/core/cortex-m0/irq_handler.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helper to declare IRQ handling routines */
-
-#ifndef __CROS_EC_IRQ_HANDLER_H
-#define __CROS_EC_IRQ_HANDLER_H
-
-#include "cpu.h"
-
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
-
-/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#ifdef CONFIG_TASK_PROFILING
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void routine(void);					\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_end_irq_handler(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#else /* CONFIG_TASK_PROFILING */
-/* No Profiling : connect directly the IRQ vector */
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void routine(void);					\
-	void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif /* CONFIG_TASK_PROFILING */
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m0/ldivmod.S b/core/cortex-m0/ldivmod.S
deleted file mode 120000
index 603ea316c8..0000000000
--- a/core/cortex-m0/ldivmod.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S
\ No newline at end of file
diff --git a/core/cortex-m0/lmul.S b/core/cortex-m0/lmul.S
deleted file mode 120000
index ab5bfc3cb2..0000000000
--- a/core/cortex-m0/lmul.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m0/lmul.S
\ No newline at end of file
diff --git a/core/cortex-m0/mula.S b/core/cortex-m0/mula.S
deleted file mode 100644
index 02e617c328..0000000000
--- a/core/cortex-m0/mula.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cortex-M0 multiply-accumulate[-accumulate] functions
- */
-
-	.syntax unified
-	.text
-	.thumb
-
-@ uint64_t mula32(uint32_t a, uint32_t b, uint32_t c)
-@
-@ Multiply a (r0) and b (r1), add c (r2) and return the product in r1:r0
-@
-	.thumb_func
-	.section .text.mula32
-	.global mula32
-mula32:
-
-	push	{r4, r5}
-	uxth	r4, r0		/* r4 = a.lo16 */
-	uxth	r5, r1		/* r5 = b.lo16 */
-	uxth	r3, r2		/* r3 = c.lo16 */
-	muls	r4, r5		/* r4 = a.lo16 * b.lo16 */
-	adds	r4, r3		/* r4 = a.lo16 * b.lo16 + c.lo16 == r.lo32 */
-	lsrs	r3, r0, 16	/* r3 = a.hi16 */
-	lsrs	r2, r2, 16	/* r2 = c.hi16 */
-	muls	r5, r3		/* r5 = a.hi16 * b.lo16 */
-	adds	r5, r2		/* r5 = a.hi16 * b.lo16 + c.hi16 == r.mid32.1 */
-	uxth	r2, r0		/* r2 = a.lo16 */
-	lsrs	r1, r1, 16	/* r1 = b.hi16 */
-	muls	r2, r1		/* r2 = a.lo16 * b.hi16 == r.mid32.2 */
-	muls	r1, r3		/* r1 = b.hi16 * a.hi16 == r.hi32 */
-	movs	r3, 0		/* r3 = 0 */
-	adds	r5, r2		/* r5 = (r.mid32.1 + r.mid32.2).lo32 == r.mid.lo32 */
-	adcs	r3, r3		/* r3 = (r.mid32.1 + r.mid32.2).hi32 == r.mid.hi32 */
-	lsls	r0, r5, 16	/* r0 = r.mid.lo32.lo16 << 16 == r.mid.inpos.lo32 */
-	lsrs	r5, r5, 16	/* r5 = r.mid.lo32.hi16 >> 16 */
-	lsls	r3, r3, 16	/* r3 = r.mid.hi.lo16 << 16 */
-	adds	r3, r5		/* r3 = r5 + r3 = r.mid.inpos.hi32 */
-	adds	r0, r4		/* r0 = r.lo32 */
-	adcs	r1, r3		/* r1 = r.hi32 */
-	pop	{r4, r5}
-	bx	lr
-
-@ uint64_t mulaa32(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
-@
-@ Multiply a (r0) and b (r1), add c (r2), add d (r3) and return the product in
-@ r1:r0
-	.thumb_func
-	.section .text.mulaa32
-	.global mulaa32
-mulaa32:
-
-	push	{r4, r5, r6}
-	uxth	r5, r0		/* r5 = a.lo16 */
-	uxth	r6, r1		/* r6 = b.lo16 */
-	uxth	r4, r2		/* r4 = c.lo16 */
-	muls	r5, r6		/* r5 = a.lo16 * b.lo16 */
-	adds	r5, r4		/* r5 = a.lo16 * b.lo16 + c.lo16 == r.lo32 */
-	lsrs	r4, r0, 16	/* r4 = a.hi16 */
-	lsrs	r2, r2, 16	/* r2 = c.hi16 */
-	muls	r6, r4		/* r6 = a.hi16 * b.lo16 */
-	adds	r6, r2		/* r6 = a.hi16 * b.lo16 + c.hi16 == r.mid32.1 */
-	uxth	r2, r0		/* r2 = a.lo16 */
-	lsrs	r1, r1, 16	/* r1 = b.hi16 */
-	muls	r2, r1		/* r2 = a.lo16 * b.hi16 == r.mid32.2 */
-	muls	r1, r4		/* r1 = b.hi16 * a.hi16 == r.hi32 */
-	movs	r4, 0		/* r4 = 0 */
-	adds	r6, r2		/* r6 = (r.mid32.1 + r.mid32.2).lo32 == r.mid.lo32 */
-	adcs	r4, r4		/* r4 = (r.mid32.1 + r.mid32.2).hi32 == r.mid.hi32 */
-	lsls	r0, r6, 16	/* r0 = r.mid.lo32.lo16 << 16 == r.mid.inpos.lo32 */
-	lsrs	r6, r6, 16	/* r6 = r.mid.lo32.hi16 >> 16 */
-	lsls	r4, r4, 16	/* r4 = r.mid.hi.lo16 << 16 */
-	adds	r0, r3		/* r0 = r.mid.inposition.lo32 + d */
-	adcs	r4, r6		/* r4 = r6 + r4 + carry = r.mid.inpos.hi32 */
-	adds	r0, r5		/* r0 = r.lo32 */
-	adcs	r1, r4		/* r1 = r.hi32 */
-	pop	{r4, r5, r6}
-	bx	lr
diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h
deleted file mode 100644
index 51c12f65b2..0000000000
--- a/core/cortex-m0/panic-internal.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PANIC_INTERNAL_H
-#define __CROS_EC_PANIC_INTERNAL_H
-
-#include <stdnoreturn.h>
-
-noreturn void exception_panic(void) __attribute__((naked));
-
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c
deleted file mode 100644
index 4fe69fddb1..0000000000
--- a/core/cortex-m0/panic.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "host_command.h"
-#include "panic.h"
-#include "panic-internal.h"
-#include "printf.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Whether bus fault is ignored */
-static int bus_fault_ignored;
-
-
-/* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
-
-/* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
-static const uint32_t pstack_addr = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE
-				     - sizeof(struct panic_data)) & ~7;
-
-/**
- * Print the name and value of a register
- *
- * This is a convenient helper function for displaying a register value.
- * It shows the register name in a 3 character field, followed by a colon.
- * The register value is regs[index], and this is shown in hex. If regs is
- * NULL, then we display spaces instead.
- *
- * After displaying the value, either a space or \n is displayed depending
- * on the register number, so that (assuming the caller passes all 16
- * registers in sequence) we put 4 values per line like this
- *
- * r0 :0000000b r1 :00000047 r2 :60000000 r3 :200012b5
- * r4 :00000000 r5 :08004e64 r6 :08004e1c r7 :200012a8
- * r8 :08004e64 r9 :00000002 r10:00000000 r11:00000000
- * r12:0000003f sp :200009a0 lr :0800270d pc :0800351a
- *
- * @param regnum	Register number to display (0-15)
- * @param regs		Pointer to array holding the registers, or NULL
- * @param index		Index into array where the register value is present
- */
-static void print_reg(int regnum, const uint32_t *regs, int index)
-{
-	static const char regname[] = "r10r11r12sp lr pc ";
-	static char rname[3] = "r  ";
-	const char *name;
-
-	rname[1] = '0' + regnum;
-	name = regnum < 10 ? rname : &regname[(regnum - 10) * 3];
-	panic_printf("%c%c%c:", name[0], name[1], name[2]);
-	if (regs)
-		panic_printf("%08x", regs[index]);
-	else
-		panic_puts("        ");
-	panic_puts((regnum & 3) == 3 ? "\n" : " ");
-}
-
-/*
- * Returns non-zero if the exception frame was created on the main stack, or
- * zero if it's on the process stack.
- *
- * See B1.5.8 "Exception return behavior" of ARM DDI 0403D for details.
- */
-static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
-{
-	return (exc_return & 0xf) == 1 || (exc_return & 0xf) == 9;
-}
-
-/*
- * Print panic data
- */
-void panic_data_print(const struct panic_data *pdata)
-{
-	const uint32_t *lregs = pdata->cm.regs;
-	const uint32_t *sregs = NULL;
-	const int32_t in_handler =
-		is_frame_in_handler_stack(pdata->cm.regs[11]);
-	int i;
-
-	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
-		sregs = pdata->cm.frame;
-
-	panic_printf("\n=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
-		     in_handler ? "HANDLER" : "PROCESS",
-		     lregs[1] & 0xff, sregs ? sregs[7] : -1);
-	for (i = 0; i < 4; i++)
-		print_reg(i, sregs, i);
-	for (i = 4; i < 10; i++)
-		print_reg(i, lregs, i - 1);
-	print_reg(10, lregs, 9);
-	print_reg(11, lregs, 10);
-	print_reg(12, sregs, 4);
-	print_reg(13, lregs, in_handler ? 2 : 0);
-	print_reg(14, sregs, 5);
-	print_reg(15, sregs, 6);
-}
-
-void __keep report_panic(void)
-{
-	/*
-	 * Don't need to get pointer via get_panic_data_write()
-	 * because memory below pdata_ptr is stack now (see exception_panic())
-	 */
-	struct panic_data *pdata = pdata_ptr;
-	uint32_t sp;
-
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = sizeof(*pdata);
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_CORTEX_M;
-	pdata->flags = 0;
-	pdata->reserved = 0;
-
-	/* Choose the right sp (psp or msp) based on EXC_RETURN value */
-	sp = is_frame_in_handler_stack(pdata->cm.regs[11])
-		? pdata->cm.regs[2] : pdata->cm.regs[0];
-	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
-	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
-		const uint32_t *sregs = (const uint32_t *)sp;
-		int i;
-		for (i = 0; i < 8; i++)
-			pdata->cm.frame[i] = sregs[i];
-		pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
-	}
-
-	panic_data_print(pdata);
-	panic_reboot();
-}
-
-/**
- * Default exception handler, which reports a panic.
- *
- * Declare this as a naked call so we can extract raw LR and IPSR values.
- */
-void exception_panic(void)
-{
-	/* Save registers and branch directly to panic handler */
-	asm volatile(
-		"mov r0, %[pregs]\n"
-		"mrs r1, psp\n"
-		"mrs r2, ipsr\n"
-		"mov r3, sp\n"
-		"stmia r0!, {r1-r7}\n"
-		"mov r1, r8\n"
-		"mov r2, r9\n"
-		"mov r3, r10\n"
-		"mov r4, r11\n"
-		"mov r5, lr\n"
-		"stmia r0!, {r1-r5}\n"
-		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
-			"r10", "r11", "cc", "memory"
-		);
-}
-
-#ifdef CONFIG_SOFTWARE_PANIC
-void software_panic(uint32_t reason, uint32_t info)
-{
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
-	__builtin_unreachable();
-}
-
-void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
-{
-	struct panic_data * const pdata = get_panic_data_write();
-	uint32_t *lregs;
-
-	lregs = pdata->cm.regs;
-
-	/* Setup panic data structure */
-	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_CORTEX_M;
-
-	/* Log panic cause */
-	lregs[1] = exception;
-	lregs[3] = reason;
-	lregs[4] = info;
-}
-
-void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
-{
-	struct panic_data * const pdata = panic_get_data();
-	uint32_t *lregs;
-
-	if (pdata && pdata->struct_version == 2) {
-		lregs = pdata->cm.regs;
-		*exception = lregs[1];
-		*reason = lregs[3];
-		*info = lregs[4];
-	} else {
-		*exception = *reason = *info = 0;
-	}
-}
-#endif
-
-void bus_fault_handler(void)
-{
-	if (!bus_fault_ignored)
-		exception_panic();
-}
-
-void ignore_bus_fault(int ignored)
-{
-	bus_fault_ignored = ignored;
-}
diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S
deleted file mode 100644
index a75daad939..0000000000
--- a/core/cortex-m0/switch.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Context swtching
- */
-
-#include "config.h"
-
-#define CPU_SCB_ICSR		0xe000ed04
-
-.text
-
-.syntax unified
-.code 16
-
-/**
- * Task context switching
- *
- * Change the task scheduled after returning from the exception.
- *
- * Save the registers of the current task below the exception context on
- * its task, then restore the live registers of the next task and set the
- * process stack pointer to the new stack.
- *
- * r0: pointer to the task to switch from
- * r1: pointer to the task to switch to
- *
- * must be called from interrupt context
- *
- * the structure of the saved context on the stack is :
- *     r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr
- *     additional registers            <|> exception frame
- */
-.global __switchto
-.thumb_func
-__switchto:
-  mrs r2, psp            @ get the task stack where the context has been saved
-  mov r3, sp
-  mov sp, r2
-  push {r4-r7}           @ save additional r4-r7 in the task stack
-  mov r4, r8
-  mov r5, r9
-  mov r6, r10
-  mov r7, r11
-  push {r4-r7}           @ save additional r8-r11 in the task stack
-  mov r2, sp             @ prepare to save former task stack pointer
-  mov sp, r3             @ restore system stack pointer
-  str r2, [r0]           @ save the task stack pointer in its context
-  ldr r2, [r1]           @ get the new scheduled task stack pointer
-  ldmia r2!, {r4-r7}     @ restore r8-r11 for the next task context
-  mov r8, r4
-  mov r9, r5
-  mov r10, r6
-  mov r11, r7
-  ldmia r2!, {r4-r7}     @ restore r4-r7 for the next task context
-  msr psp, r2            @ set the process stack pointer to exception context
-  bx lr                  @ return from exception
-
-/**
- * Start the task scheduling.  r0 is a pointer to task_stack_ready, which is
- * set to 1 after the task stack is set up.
- */
-.global __task_start
-.thumb_func
-__task_start:
-  ldr  r2,=scratchpad     @ area used as thread stack for the first switch
-  movs r3, #2             @ use : priv. mode / thread stack / no floating point
-  adds r2, #17*4          @ put the pointer at the top of the stack
-  movs r1, #0             @ __Schedule parameter : re-schedule nothing
-  msr  psp, r2            @ setup a thread stack up to the first context switch
-  movs r2, #1             @ r2 = TASK_SCHEDULER_INIT
-  isb                     @ ensure the write is done
-  msr control, r3
-  movs r3, r0
-  movs r0, #0             @ __Schedule parameter : de-schedule nothing
-  isb                     @ ensure the write is done
-  str  r2, [r3]           @ Task scheduling is now active
-  bl __schedule           @ execute the task with the highest priority
-  /* we should never return here */
-  movs r0, #1             @ set to EC_ERROR_UNKNOWN
-  bx lr
-
-/**
- * SVC exception handler
- */
-.global svc_handler
-.thumb_func
-svc_handler:
-  push {r3, lr}              @ save link register and keep stack aligned
-  bl __svc_handler           @ call svc handler helper
-  ldr r3,=current_task       @ load the current task's address
-  ldr r1, [r3]               @ load the current task
-  cmp r0, r1                 @ compare with previous task returned by helper
-  beq svc_handler_return     @ return if they are the same
-  bl __switchto              @ context switch to the next task
-svc_handler_return:
-  pop {r3, pc}               @ return from exception or return to caller
-
-/**
- * PendSVC exception handler
- */
-.global pendsv_handler
-.thumb_func
-pendsv_handler:
-  push {r3, lr}              @ save link register and keep stack aligned
-  ldr r0, =CPU_SCB_ICSR      @ load CPU_SCB_ICSR's address
-  movs r1, #1                @ prepare left shift (1 << 27)
-  lsls r1, #27               @ shift the bit
-  str r1, [r0]               @ clear pending flag
-  cpsid i                    @ ensure we have priority 0 during re-scheduling
-  movs r1, #0                @ desched nothing
-  movs r0, #0                @ resched nothing
-  bl svc_handler             @ re-schedule the highest priority task
-  cpsie i                    @ leave priority 0
-  pop {r3, pc}               @ return from exception
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
deleted file mode 100644
index ba40b667b6..0000000000
--- a/core/cortex-m0/task.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Task scheduling / events module for Chrome EC operating system */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "link_defs.h"
-#include "panic.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-typedef union {
-	struct {
-		/*
-		 * Note that sp must be the first element in the task struct
-		 * for __switchto() to work.
-		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
-	};
-} task_;
-
-/* Value to store in unused stack */
-#define STACK_UNUSED_VALUE 0xdeadd00d
-
-/* declare task routine prototypes */
-#define TASK(n, r, d, s) void r(void *);
-void __idle(void);
-CONFIG_TASK_LIST
-CONFIG_TEST_TASK_LIST
-CONFIG_CTS_TASK_LIST
-#undef TASK
-
-/* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-};
-#undef TASK
-
-#ifdef CONFIG_TASK_PROFILING
-static uint64_t task_start_time; /* Time task scheduling started */
-/*
- * We only keep 32-bit values for exception start/end time, to avoid
- * accounting errors when we service interrupt when the timer wraps around.
- */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
-#endif
-
-extern int __task_start(int *task_stack_ready);
-
-#ifndef CONFIG_LOW_POWER_IDLE
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	while (1) {
-		/*
-		 * Wait for the next irq event.  This stops the CPU clock
-		 * (sleep / deep sleep, depending on chip config).
-		 */
-		asm("wfi");
-	}
-}
-#endif /* !CONFIG_LOW_POWER_IDLE */
-
-static void task_exit_trap(void)
-{
-	int i = task_get_current();
-	cprints(CC_TASK, "Task %d (%s) exited!", i, task_names[i]);
-	/* Exited tasks simply sleep forever */
-	while (1)
-		task_wait_event(-1);
-}
-
-/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
-static const struct {
-	uint32_t r0;
-	uint32_t pc;
-	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-};
-#undef TASK
-
-/* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT];
-/* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
-BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-
-
-/* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
-
-#undef TASK
-
-/* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[17];
-
-task_ *current_task = (task_ *)scratchpad;
-
-/*
- * Bitmap of all tasks ready to be run.
- *
- * Start off with only the hooks task marked as ready such that all the modules
- * can do their init within a task switching context.  The hooks task will then
- * make a call to enable all tasks.
- */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
-/*
- * Initially allow only the HOOKS and IDLE task to run, regardless of ready
- * status, in order for HOOK_INIT to complete before other tasks.
- * task_enable_all_tasks() will open the flood gates.
- */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-
-static int start_called;  /* Has task swapping started */
-
-static inline task_ *__task_id_to_ptr(task_id_t id)
-{
-	return tasks + id;
-}
-
-void interrupt_disable(void)
-{
-	asm("cpsid i");
-}
-
-void interrupt_enable(void)
-{
-	asm("cpsie i");
-}
-
-inline int is_interrupt_enabled(void)
-{
-	int primask;
-
-	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
-
-	return !(primask & 0x1);
-}
-
-inline int in_interrupt_context(void)
-{
-	int ret;
-	asm("mrs %0, ipsr\n"              /* read exception number */
-	    "lsl %0, #23\n" : "=r"(ret)); /* exception bits are the 9 LSB */
-	return ret;
-}
-
-static inline int get_interrupt_context(void)
-{
-	int ret;
-	asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */
-	return ret & 0x1ff;                /* exception bits are the 9 LSB */
-}
-
-task_id_t task_get_current(void)
-{
-#ifdef CONFIG_DEBUG_BRINGUP
-	/* If we haven't done a context switch then our task ID isn't valid */
-	ASSERT(current_task != (task_ *)scratchpad);
-#endif
-	return current_task - tasks;
-}
-
-uint32_t *task_get_event_bitmap(task_id_t tskid)
-{
-	task_ *tsk = __task_id_to_ptr(tskid);
-	return &tsk->events;
-}
-
-int task_start_called(void)
-{
-	return start_called;
-}
-
-/**
- * Scheduling system call
- */
-task_  __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
-{
-	task_ *current, *next;
-#ifdef CONFIG_TASK_PROFILING
-	int exc = get_interrupt_context();
-	uint32_t t;
-#endif
-
-	/* Priority is already at 0 we cannot be interrupted */
-
-#ifdef CONFIG_TASK_PROFILING
-	/*
-	 * SVCall isn't triggered via DECLARE_IRQ(), so it needs to track its
-	 * start time explicitly.
-	 */
-	if (exc == 0xb) {
-		t = get_time().le.lo;
-		current_task->runtime += (t - exc_end_time);
-		exc_end_time = t;
-		svc_calls++;
-	}
-#endif
-
-	current = current_task;
-
-#ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current->stack != STACK_UNUSED_VALUE) {
-		panic_printf("\n\nStack overflow in %s task!\n",
-			     task_names[current - tasks]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks);
-#endif
-	}
-#endif
-
-	if (desched && !current->events) {
-		/*
-		 * Remove our own ready bit (current - tasks is same as
-		 * task_get_current())
-		 */
-		tasks_ready &= ~(1 << (current - tasks));
-	}
-	tasks_ready |= 1 << resched;
-
-	ASSERT(tasks_ready & tasks_enabled);
-	next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
-
-#ifdef CONFIG_TASK_PROFILING
-	/* Track additional time in re-sched exception context */
-	t = get_time().le.lo;
-	exc_total_time += (t - exc_end_time);
-
-	exc_end_time = t;
-#endif
-
-	/* Switch to new task */
-#ifdef CONFIG_TASK_PROFILING
-	if (next != current)
-		task_switches++;
-#endif
-	current_task = next;
-	return current;
-}
-
-void __schedule(int desched, int resched)
-{
-	register int p0 asm("r0") = desched;
-	register int p1 asm("r1") = resched;
-
-	asm("svc 0" : : "r"(p0), "r"(p1));
-}
-
-#ifdef CONFIG_TASK_PROFILING
-void task_start_irq_handler(void *excep_return)
-{
-	/*
-	 * Get time before checking depth, in case this handler is
-	 * pre-empted.
-	 */
-	uint32_t t = get_time().le.lo;
-	int irq = get_interrupt_context() - 16;
-
-	/*
-	 * Track IRQ distribution.  No need for atomic add, because an IRQ
-	 * can't pre-empt itself.
-	 */
-	if (irq < ARRAY_SIZE(irq_dist))
-		irq_dist[irq]++;
-
-	/*
-	 * Continue iff the tasks are ready and we are not called from another
-	 * exception (as the time accouting is done in the outer irq).
-	 */
-	if (!start_called || ((uint32_t)excep_return & 0xf) == 1)
-		return;
-
-	exc_start_time = t;
-	/*
-	 * Bill the current task for time between the end of the last interrupt
-	 * and the start of this one.
-	 */
-	current_task->runtime += (exc_start_time - exc_end_time);
-}
-
-void task_end_irq_handler(void *excep_return)
-{
-	uint32_t t = get_time().le.lo;
-	/*
-	 * Continue iff the tasks are ready and we are not called from another
-	 * exception (as the time accouting is done in the outer irq).
-	 */
-	if (!start_called || ((uint32_t)excep_return & 0xf) == 1)
-		return;
-
-	/* Track time in interrupts */
-	exc_total_time += (t - exc_start_time);
-	exc_end_time = t;
-}
-#endif
-
-static uint32_t __wait_evt(int timeout_us, task_id_t resched)
-{
-	task_ *tsk = current_task;
-	task_id_t me = tsk - tasks;
-	uint32_t evt;
-	int ret __attribute__((unused));
-
-	/*
-	 * Scheduling task when interrupts are disabled will result in Forced
-	 * Hard Fault because disabling interrupt using 'cpsid i' also disables
-	 * SVCall handler (because it has configurable priority)
-	 */
-	ASSERT(is_interrupt_enabled());
-	ASSERT(!in_interrupt_context());
-
-	if (timeout_us > 0) {
-		timestamp_t deadline = get_time();
-		deadline.val += timeout_us;
-		ret = timer_arm(deadline, me);
-		ASSERT(ret == EC_SUCCESS);
-	}
-	while (!(evt = atomic_clear(&tsk->events))) {
-		/*
-		 * We need to ensure that the execution priority is actually
-		 * decreased after the "cpsie i" in the atomic operation above
-		 * else the "svc" in the __schedule call below will trigger
-		 * a HardFault. Use a barrier to force it at that point.
-		 */
-		asm volatile("isb");
-		/* Remove ourself and get the next task in the scheduler */
-		__schedule(1, resched);
-		resched = TASK_ID_IDLE;
-	}
-	if (timeout_us > 0) {
-		timer_cancel(me);
-		/* Ensure timer event is clear, we no longer care about it */
-		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
-	}
-	return evt;
-}
-
-uint32_t task_set_event(task_id_t tskid, uint32_t event)
-{
-	task_ *receiver = __task_id_to_ptr(tskid);
-	ASSERT(receiver);
-
-	/* Set the event bit in the receiver message bitmap */
-	atomic_or(&receiver->events, event);
-
-	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context() || !is_interrupt_enabled()) {
-		/* The receiver might run again */
-		atomic_or(&tasks_ready, 1 << tskid);
-		if (start_called) {
-			/*
-			 * Trigger the scheduler when there's
-			 * no other irqs happening.
-			 */
-			CPU_SCB_ICSR = BIT(28);
-		}
-	} else {
-		/*
-		 * We need to ensure that the execution priority is
-		 * actually decreased after the "cpsie i" in the atomic
-		 * operation above else the "svc" in the __schedule
-		 * call below will trigger a HardFault.
-		 * Use a barrier to force it at that point.
-		 */
-		asm volatile("isb");
-		__schedule(0, tskid);
-	}
-
-	return 0;
-}
-
-uint32_t task_wait_event(int timeout_us)
-{
-	return __wait_evt(timeout_us, TASK_ID_IDLE);
-}
-
-uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint64_t deadline = get_time().val + timeout_us;
-	uint32_t events = 0;
-	int time_remaining_us = timeout_us;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(events & event_mask)) {
-		/* Collect events to re-post later */
-		events |= __wait_evt(time_remaining_us, TASK_ID_IDLE);
-
-		time_remaining_us = deadline - get_time().val;
-		if (timeout_us > 0 && time_remaining_us <= 0) {
-			/* Ensure we return a TIMER event if we timeout */
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-	}
-
-	/* Re-post any other events collected */
-	if (events & ~event_mask)
-		atomic_or(&current_task->events, events & ~event_mask);
-
-	return events & event_mask;
-}
-
-void task_enable_all_tasks(void)
-{
-	/* Mark all tasks as ready and able to run. */
-	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
-	/* Reschedule the highest priority task. */
-	if (is_interrupt_enabled())
-		__schedule(0, 0);
-}
-
-void task_enable_task(task_id_t tskid)
-{
-	atomic_or(&tasks_enabled, BIT(tskid));
-}
-
-void task_disable_task(task_id_t tskid)
-{
-	atomic_clear_bits(&tasks_enabled, BIT(tskid));
-
-	if (!in_interrupt_context() && is_interrupt_enabled() &&
-	    tskid == task_get_current())
-		__schedule(0, 0);
-}
-
-void task_enable_irq(int irq)
-{
-	CPU_NVIC_EN(0) = 1 << irq;
-}
-
-void task_disable_irq(int irq)
-{
-	CPU_NVIC_DIS(0) = 1 << irq;
-}
-
-void task_clear_pending_irq(int irq)
-{
-	CPU_NVIC_UNPEND(0) = 1 << irq;
-}
-
-void task_trigger_irq(int irq)
-{
-	CPU_NVIC_ISPR(0) = 1 << irq;
-}
-
-/*
- * Initialize IRQs in the NVIC and set their priorities as defined by the
- * DECLARE_IRQ statements.
- */
-static void __nvic_init_irqs(void)
-{
-	/* Get the IRQ priorities section from the linker */
-	int exc_calls = __irqprio_end - __irqprio;
-	int i;
-
-	/* Mask and clear all pending interrupts */
-	CPU_NVIC_DIS(0) = 0xffffffff;
-	CPU_NVIC_UNPEND(0) = 0xffffffff;
-
-	/*
-	 * Re-enable global interrupts in case they're disabled.  On a reboot,
-	 * they're already enabled; if we've jumped here from another image,
-	 * they're not.
-	 */
-	interrupt_enable();
-
-	/* Set priorities */
-	for (i = 0; i < exc_calls; i++) {
-		cpu_set_interrupt_priority(__irqprio[i].irq,
-					   __irqprio[i].priority);
-	}
-}
-
-void mutex_lock(struct mutex *mtx)
-{
-	uint32_t id = 1 << task_get_current();
-
-	ASSERT(id != TASK_ID_INVALID);
-	atomic_or(&mtx->waiters, id);
-
-	while (1) {
-		/* Try to get the lock (set 2 into the lock field) */
-		__asm__ __volatile__("cpsid i");
-		if (mtx->lock == 0)
-			break;
-		__asm__ __volatile__("cpsie i");
-		/* Contention on the mutex */
-		task_wait_event_mask(TASK_EVENT_MUTEX, 0);
-	}
-	mtx->lock = 2;
-	__asm__ __volatile__("cpsie i");
-
-	atomic_clear_bits(&mtx->waiters, id);
-}
-
-void mutex_unlock(struct mutex *mtx)
-{
-	uint32_t waiters;
-	task_ *tsk = current_task;
-
-	/*
-	 * Add a critical section to keep the unlock and the snapshotting of
-	 * waiters atomic in case a task switching occurs between them.
-	 */
-	interrupt_disable();
-	waiters = mtx->waiters;
-	mtx->lock = 0;
-	interrupt_enable();
-
-	while (waiters) {
-		task_id_t id = __fls(waiters);
-		waiters &= ~BIT(id);
-
-		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX);
-	}
-
-	/* Ensure no event is remaining from mutex wake-up */
-	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
-}
-
-void task_print_list(void)
-{
-	int i;
-
-	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
-
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
-		uint32_t *sp;
-
-		int stackused = tasks_init[i].stack_size;
-
-		for (sp = tasks[i].stack;
-		     sp < (uint32_t *)tasks[i].sp && *sp == STACK_UNUSED_VALUE;
-		     sp++)
-			stackused -= sizeof(uint32_t);
-
-		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
-			 stackused, tasks_init[i].stack_size);
-		cflush();
-	}
-}
-
-int command_task_info(int argc, char **argv)
-{
-#ifdef CONFIG_TASK_PROFILING
-	int total = 0;
-	int i;
-#endif
-
-	task_print_list();
-
-#ifdef CONFIG_TASK_PROFILING
-	ccputs("IRQ counts by type:\n");
-	cflush();
-	for (i = 0; i < ARRAY_SIZE(irq_dist); i++) {
-		if (irq_dist[i]) {
-			ccprintf("%4d %8d\n", i, irq_dist[i]);
-			total += irq_dist[i];
-		}
-	}
-	ccprintf("Service calls:          %11d\n", svc_calls);
-	ccprintf("Total exceptions:       %11d\n", total + svc_calls);
-	ccprintf("Task switches:          %11d\n", task_switches);
-	ccprintf("Task switching started: %11.6lld s\n", task_start_time);
-	ccprintf("Time in tasks:          %11.6lld s\n",
-		 get_time().val - task_start_time);
-	ccprintf("Time in exceptions:     %11.6lld s\n", exc_total_time);
-#endif
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
-
-#ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
-{
-	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
-	} else {
-		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
-		__schedule(0, 0);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
-			"Print/set ready tasks");
-#endif
-
-void task_pre_init(void)
-{
-	uint32_t *stack_next = (uint32_t *)task_stacks;
-	int i;
-
-	/* Fill the task memory with initial values */
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		uint32_t *sp;
-		/* Stack size in words */
-		uint32_t ssize = tasks_init[i].stack_size / 4;
-
-		tasks[i].stack = stack_next;
-
-		/*
-		 * Update stack used by first frame: 8 words for the normal
-		 * stack, plus 8 for R4-R11. With FP enabled, we need another
-		 * 18 words for S0-S15 and FPCSR and to align to 64-bit.
-		 */
-		sp = stack_next + ssize - 16;
-		tasks[i].sp = (uint32_t)sp;
-
-		/* Initial context on stack (see __switchto()) */
-		sp[8] = tasks_init[i].r0;           /* r0 */
-		sp[13] = (uint32_t)task_exit_trap;  /* lr */
-		sp[14] = tasks_init[i].pc;          /* pc */
-		sp[15] = 0x01000000;                /* psr */
-
-		/* Fill unused stack; also used to detect stack overflow. */
-		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
-			*sp = STACK_UNUSED_VALUE;
-
-		stack_next += ssize;
-	}
-
-	/*
-	 * Fill in guard value in scratchpad to prevent stack overflow
-	 * detection failure on the first context switch.  This works because
-	 * the first word in the scratchpad is where the switcher will store
-	 * sp, so it's ok to blow away.
-	 */
-	((task_ *)scratchpad)->stack = (uint32_t *)scratchpad;
-	*(uint32_t *)scratchpad = STACK_UNUSED_VALUE;
-
-	/* Initialize IRQs */
-	__nvic_init_irqs();
-}
-
-int task_start(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	timestamp_t t = get_time();
-
-	task_start_time = t.val;
-	exc_end_time = t.le.lo;
-#endif
-
-	return __task_start(&start_called);
-}
diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
deleted file mode 100644
index 5628361a94..0000000000
--- a/core/cortex-m0/thumb_case.S
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Thumb mode toolchain helpers for compact switch/case statement.
- */
-
-#include "config.h"
-
-.text
-
-.syntax unified
-.code 16
-
-/*
- * Helpers for compact switch
- *
- * r0: the table index
- * lr: the table base address (need to clear bit 0)
- *
- * r0 and lr must be PRESERVED.
- * r12 can be clobbered.
- */
-.section .text.__gnu_thumb1_case_uqi
-.global __gnu_thumb1_case_uqi
-.thumb_func
-__gnu_thumb1_case_uqi:
-	mov     r12, r1
-	mov     r1, lr
-	lsrs    r1, r1, #1
-	lsls    r1, r1, #1
-	ldrb    r1, [r1, r0]
-	lsls    r1, r1, #1
-	add     lr, lr, r1
-	mov     r1, r12
-	bx      lr
-
-.section .text.__gnu_thumb1_case_sqi
-.global __gnu_thumb1_case_sqi
-.thumb_func
-__gnu_thumb1_case_sqi:
-	mov     r12, r1
-	mov     r1, lr
-	lsrs    r1, r1, #1
-	lsls    r1, r1, #1
-	ldrsb   r1, [r1, r0]
-	lsls    r1, r1, #1
-	add     lr, lr, r1
-	mov     r1, r12
-	bx      lr
-
-.section .text.__gnu_thumb1_case_uhi
-.global __gnu_thumb1_case_uhi
-.thumb_func
-__gnu_thumb1_case_uhi:
-	push    {r0, r1}
-	mov     r1, lr
-	lsrs    r1, r1, #1
-	lsls    r0, r0, #1
-	lsls    r1, r1, #1
-	ldrh    r1, [r1, r0]
-	lsls    r1, r1, #1
-	add     lr, lr, r1
-	pop     {r0, r1}
-	bx      lr
-
-.section .text.__gnu_thumb1_case_shi
-.global __gnu_thumb1_case_shi
-.thumb_func
-__gnu_thumb1_case_shi:
-	push    {r0, r1}
-	mov     r1, lr
-	lsrs    r1, r1, #1
-	lsls    r0, r0, #1
-	lsls    r1, r1, #1
-	ldrsh   r1, [r1, r0]
-	lsls    r1, r1, #1
-	add     lr, lr, r1
-	pop     {r0, r1}
-	bx      lr
-
-.section .text.__gnu_thumb1_case_si
-.global __gnu_thumb1_case_si
-.thumb_func
-__gnu_thumb1_case_si:
-	push	{r0, r1}
-	mov	r1, lr
-	adds.n	r1, r1, #2
-	lsrs	r1, r1, #2
-	lsls	r0, r0, #2
-	lsls	r1, r1, #2
-	ldr	r0, [r1, r0]
-	adds	r0, r0, r1
-	mov	lr, r0
-	pop	{r0, r1}
-	mov	pc, lr
diff --git a/core/cortex-m0/uldivmod.S b/core/cortex-m0/uldivmod.S
deleted file mode 120000
index 6d1e5e1998..0000000000
--- a/core/cortex-m0/uldivmod.S
+++ /dev/null
@@ -1 +0,0 @@
-../../third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
\ No newline at end of file
diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c
deleted file mode 100644
index b1eaa957e0..0000000000
--- a/core/cortex-m0/vecttable.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cortex-M CPU vector table
- */
-
-#ifndef ___INIT
-#define ___INIT
-#include <stddef.h>
-#include <stdint.h>
-
-#include "config.h"
-#include "panic-internal.h"
-#include "task.h"
-#endif  /* __INIT */
-
-typedef void (*func)(void);
-
-#ifndef PASS
-#define PASS 1
-#endif
-
-#if PASS == 1
-
-void __attribute__((naked)) default_handler(void)
-{
-	/*
-	 * An (enforced) long tail call to preserve exn_return in lr without
-	 * restricting the relative placement of default_handler and
-	 * exception_panic.
-	 */
-	asm volatile("bx %0\n" : : "r" (exception_panic));
-}
-
-#define table(x) x
-
-/* Note: the alias target must be defined in this translation unit */
-#define weak_with_default __attribute__((used, weak, alias("default_handler")))
-
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
-
-#define item(name) extern void name(void);
-#define null
-
-extern void stack_end(void); /* not technically correct, it's just a pointer */
-extern void reset(void);
-
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-#pragma GCC diagnostic pop
-
-#endif /* PASS 1 */
-
-#if PASS == 2
-#undef table
-#undef vec
-#undef irq
-#undef item
-#undef null
-
-/* number of elements before the first irq vector */
-#define IRQ_OFFSET 16
-/* element in the table that is null: extra IRQs are routed there,
- * then finally overwritten
- */
-#define IRQ_UNUSED_OFFSET 8
-
-#define table(x) func vectors[] __attribute__((section(".text.vecttable,\"a\" @"))) = { x[IRQ_UNUSED_OFFSET] = null };
-
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
-
-#define item(name) name,
-#define null (void *)0,
-#endif /* PASS 2 */
-
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	vec(svc)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-)
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "vecttable.c"
-#endif
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c
deleted file mode 100644
index 9961922ee5..0000000000
--- a/core/cortex-m0/watchdog.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog common code */
-
-#include "common.h"
-#include "panic.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * As defined by Armv7-M Reference Manual B1.5.6 "Exception Entry Behavior",
- * the structure of the saved context on the stack is:
- * r0, r1, r2, r3, r12, lr, pc, psr, ...
- */
-#define STACK_IDX_REG_LR 5
-#define STACK_IDX_REG_PC 6
-
-void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
-{
-	uint32_t psp;
-	uint32_t *stack;
-
-	asm("mrs %0, psp" : "=r"(psp));
-	if ((excep_lr & 0xf) == 1) {
-		/* we were already in exception context */
-		stack = (uint32_t *)excep_sp;
-	} else {
-		/* we were in task context */
-		stack = (uint32_t *)psp;
-	}
-
-	/* Log PC. If we were in task context, log task id too. */
-#ifdef CONFIG_SOFTWARE_PANIC
-	panic_set_reason(PANIC_SW_WATCHDOG, stack[STACK_IDX_REG_PC],
-			 (excep_lr & 0xf) == 1 ? 0xff : task_get_current());
-#endif
-
-	panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ",
-		     stack[STACK_IDX_REG_PC], stack[STACK_IDX_REG_LR], psp);
-	if ((excep_lr & 0xf) == 1)
-		panic_puts("(exc) ###\n");
-	else
-		panic_printf("(task %d) ###\n", task_get_current());
-
-	/* If we are blocked in a high priority IT handler, the following debug
-	 * messages might not appear but they are useless in that situation. */
-	timer_print_info();
-	task_print_list();
-}
diff --git a/core/host/atomic.h b/core/host/atomic.h
deleted file mode 100644
index 83786de904..0000000000
--- a/core/host/atomic.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atomic operations for emulator */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include "common.h"
-
-typedef int atomic_t;
-typedef atomic_t atomic_val_t;
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_clear(atomic_t *addr)
-{
-	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
-}
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/core/host/build.mk b/core/host/build.mk
deleted file mode 100644
index 503aa5538a..0000000000
--- a/core/host/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# emulator specific files build
-#
-
-CFLAGS_CPU=-fno-builtin
-
-core-y=main.o task.o timer.o panic.o disabled.o stack_trace.o
diff --git a/core/host/cpu.h b/core/host/cpu.h
deleted file mode 100644
index d990e06afa..0000000000
--- a/core/host/cpu.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* CPU specific header file */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-static inline void cpu_init(void) { }
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/core/host/disabled.c b/core/host/disabled.c
deleted file mode 100644
index 759c215ebd..0000000000
--- a/core/host/disabled.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Disabled functions */
-
-#define DISABLED(proto) proto { }
-
-DISABLED(void clock_init(void));
diff --git a/core/host/host_exe.lds b/core/host/host_exe.lds
deleted file mode 100644
index ab8d352ecc..0000000000
--- a/core/host/host_exe.lds
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-SECTIONS {
-	.rodata.ec_sections : {
-		/* Symbols defined here are declared in link_defs.h */
-		__irqprio = .;
-		*(.rodata.irqprio)
-		__irqprio_end = .;
-
-		. = ALIGN(8);
-		__cmds = .;
-		*(SORT(.rodata.cmds*))
-		__cmds_end = .;
-
-		. = ALIGN(8);
-		__hcmds = .;
-		*(SORT(.rodata.hcmds*))
-		__hcmds_end = .;
-
-		. = ALIGN(4);
-		__mkbp_evt_srcs = .;
-		KEEP(*(.rodata.evtsrcs))
-		__mkbp_evt_srcs_end = .;
-
-		. = ALIGN(8);
-		__hooks_init = .;
-		*(.rodata.HOOK_INIT)
-		__hooks_init_end = .;
-
-		__hooks_pre_freq_change = .;
-		*(.rodata.HOOK_PRE_FREQ_CHANGE)
-		__hooks_pre_freq_change_end = .;
-
-		__hooks_freq_change = .;
-		*(.rodata.HOOK_FREQ_CHANGE)
-		__hooks_freq_change_end = .;
-
-		__hooks_sysjump = .;
-		*(.rodata.HOOK_SYSJUMP)
-		__hooks_sysjump_end = .;
-
-		__hooks_chipset_pre_init = .;
-		*(.rodata.HOOK_CHIPSET_PRE_INIT)
-		__hooks_chipset_pre_init_end = .;
-
-		__hooks_chipset_startup = .;
-		*(.rodata.HOOK_CHIPSET_STARTUP)
-		__hooks_chipset_startup_end = .;
-
-		__hooks_chipset_resume = .;
-		*(.rodata.HOOK_CHIPSET_RESUME)
-		__hooks_chipset_resume_end = .;
-
-		__hooks_chipset_suspend = .;
-		*(.rodata.HOOK_CHIPSET_SUSPEND)
-		__hooks_chipset_suspend_end = .;
-
-		__hooks_chipset_shutdown = .;
-		*(.rodata.HOOK_CHIPSET_SHUTDOWN)
-		__hooks_chipset_shutdown_end = .;
-
-		__hooks_chipset_shutdown_complete = .;
-		*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE)
-		__hooks_chipset_shutdown_complete_end = .;
-
-		__hooks_chipset_hard_off = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
-		__hooks_chipset_hard_off_end = .;
-
-		__hooks_chipset_reset = .;
-		*(.rodata.HOOK_CHIPSET_RESET)
-		__hooks_chipset_reset_end = .;
-
-		__hooks_ac_change = .;
-		*(.rodata.HOOK_AC_CHANGE)
-		__hooks_ac_change_end = .;
-
-		__hooks_lid_change = .;
-		*(.rodata.HOOK_LID_CHANGE)
-		__hooks_lid_change_end = .;
-
-		__hooks_tablet_mode_change = .;
-		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
-		__hooks_tablet_mode_change_end = .;
-
-		__hooks_base_attached_change = .;
-		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
-		__hooks_base_attached_change_end = .;
-
-		__hooks_pwrbtn_change = .;
-		*(.rodata.HOOK_POWER_BUTTON_CHANGE)
-		__hooks_pwrbtn_change_end = .;
-
-		__hooks_battery_soc_change = .;
-		*(.rodata.HOOK_BATTERY_SOC_CHANGE)
-		__hooks_battery_soc_change_end = .;
-
-		__hooks_tick = .;
-		*(.rodata.HOOK_TICK)
-		__hooks_tick_end = .;
-
-		__hooks_second = .;
-		*(.rodata.HOOK_SECOND)
-		__hooks_second_end = .;
-
-		__hooks_usb_pd_disconnect = .;
-		*(.rodata.HOOK_USB_PD_DISCONNECT)
-		__hooks_usb_pd_disconnect_end = .;
-
-		__hooks_usb_pd_connect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
-		__hooks_usb_pd_connect_end = .;
-
-		__deferred_funcs = .;
-		*(.rodata.deferred)
-		__deferred_funcs_end = .;
-
-		__test_i2c_xfer = .;
-		*(.rodata.test_i2c.xfer)
-		__test_i2c_xfer_end = .;
-	}
-}
-INSERT BEFORE .rodata;
-
-SECTIONS {
-	.bss.ec_sections : {
-		/* Symbols defined here are declared in link_defs.h */
-		. = ALIGN(8);
-		__deferred_until = .;
-		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
-		__deferred_until_end = .;
-	}
-}
-INSERT BEFORE .bss;
diff --git a/core/host/host_task.h b/core/host/host_task.h
deleted file mode 100644
index 30cd2ff594..0000000000
--- a/core/host/host_task.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Emulator task scheduling module */
-
-#ifndef __CROS_EC_HOST_TASK_H
-#define __CROS_EC_HOST_TASK_H
-
-#include <pthread.h>
-
-#include "task.h"
-
-/**
- * Returns the thread corresponding to the task.
- */
-pthread_t task_get_thread(task_id_t tskid);
-
-/**
- * Returns the ID of the active task, regardless of current thread
- * context.
- */
-task_id_t task_get_running(void);
-
-/**
- * Initializes the interrupt semaphore and associates a signal handler with
- * SIGNAL_INTERRUPT.
- */
-void task_register_interrupt(void);
-
-/**
- * Returns the process ID of the calling process.
- */
-pid_t getpid(void);
-
-#endif  /* __CROS_EC_HOST_TASK_H */
diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h
deleted file mode 100644
index f905f463c1..0000000000
--- a/core/host/irq_handler.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helper to declare IRQ handling routines */
-
-#ifndef __CROS_EC_IRQ_HANDLER_H
-#define __CROS_EC_IRQ_HANDLER_H
-
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
-/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#define DECLARE_IRQ(irq, routine, priority)                     \
-	void routine(void);					\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/host/main.c b/core/host/main.c
deleted file mode 100644
index ed7032eb63..0000000000
--- a/core/host/main.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Entry point of unit test executable */
-
-#include "console.h"
-#include "flash.h"
-#include "hooks.h"
-#include "host_task.h"
-#include "keyboard_scan.h"
-#include "stack_trace.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "uart.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-const char *__prog_name;
-
-const char *__get_prog_name(void)
-{
-	return __prog_name;
-}
-
-static int test_main(void)
-{
-	/*
-	 * In order to properly service IRQs before task switching is enabled,
-	 * we must set up our signal handler for the main thread.
-	 */
-	task_register_interrupt();
-
-	task_register_tracedump();
-
-	register_test_end_hook();
-
-	crec_flash_pre_init();
-	system_pre_init();
-	system_common_pre_init();
-
-	test_init();
-
-	timer_init();
-#ifdef HAS_TASK_KEYSCAN
-	keyboard_scan_init();
-#endif
-	uart_init();
-
-	if (system_jumped_to_this_image()) {
-		CPRINTS("Emulator initialized after sysjump");
-	} else {
-		CPUTS("\n\n--- Emulator initialized after reboot ---\n");
-		CPUTS("[Reset cause: ");
-		system_print_reset_flags();
-		CPUTS("]\n");
-	}
-
-	task_start();
-
-	return 0;
-}
-
-#ifdef TEST_FUZZ
-/*
- * Fuzzing tests need to start the main function in a thread, so that
- * LLVMFuzzerTestOneInput can run freely.
- */
-void *_main_thread(void *a)
-{
-	test_main();
-	return NULL;
-}
-
-int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
-{
-	static int initialized;
-	static pthread_t main_t;
-	/*
-	 * We lose the program name as LLVM fuzzer takes over main function:
-	 * make up one.
-	 */
-	static const char *name = STRINGIFY(PROJECT)".exe";
-
-	if (!initialized) {
-		__prog_name = name;
-		pthread_create(&main_t, NULL, _main_thread, NULL);
-		initialized = 1;
-		/* We can't sleep yet, busy loop waiting for tasks to start. */
-		wait_for_task_started_nosleep();
-		/* Let tasks settle. */
-		msleep(50 * MSEC);
-	}
-
-	return test_fuzz_one_input(data, size);
-}
-#else
-int main(int argc, char **argv)
-{
-	__prog_name = argv[0];
-	return test_main();
-}
-#endif
diff --git a/core/host/panic.c b/core/host/panic.c
deleted file mode 100644
index 7b0829989d..0000000000
--- a/core/host/panic.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "stack_trace.h"
-
-void panic_assert_fail(const char *msg, const char *func, const char *fname,
-		       int linenum)
-{
-	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n",
-		fname, linenum, func, msg);
-	task_dump_trace();
-
-	puts("Fail!"); /* Inform test runner */
-	fflush(stdout);
-
-	exit(1);
-}
diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c
deleted file mode 100644
index adef66dd44..0000000000
--- a/core/host/stack_trace.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <execinfo.h>
-#include <signal.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "host_task.h"
-#include "host_test.h"
-#include "timer.h"
-
-#define SIGNAL_TRACE_DUMP SIGTERM
-#define MAX_TRACE 30
-/*
- * When trace dump is requested from signal handler, skip:
- *   _task_dump_trace_impl
- *   _task_dump_trace_dispath
- *   A function in libc
- */
-#define SIGNAL_TRACE_OFFSET 3
-/*
- * When trace dump is requested from task_dump_trace(), skip:
- *   task_dump_trace
- *   _task_dump_trace_impl
- */
-#define DIRECT_TRACE_OFFSET 2
-
-static pthread_t main_thread;
-
-static void __attribute__((noinline)) _task_dump_trace_impl(int offset)
-{
-	void *trace[MAX_TRACE];
-	size_t sz;
-	char **messages;
-	char buf[256];
-	FILE *file;
-	int i, nb;
-
-	sz = backtrace(trace, MAX_TRACE);
-	messages = backtrace_symbols(trace + offset, sz - offset);
-
-	for (i = 0; i < sz - offset; ++i) {
-		fprintf(stderr, "#%-2d %s\n", i, messages[i]);
-		/* %p is correct (as opposed to %pP) since this is the host */
-		sprintf(buf, "addr2line %p -e %s",
-			trace[i + offset], __get_prog_name());
-		file = popen(buf, "r");
-		if (file) {
-			nb = fread(buf, 1, sizeof(buf) - 1, file);
-			buf[nb] = '\0';
-			fprintf(stderr, "    %s", buf);
-			pclose(file);
-		}
-	}
-	fflush(stderr);
-	free(messages);
-}
-
-void __attribute__((noinline)) task_dump_trace(void)
-{
-	_task_dump_trace_impl(DIRECT_TRACE_OFFSET);
-}
-
-static void __attribute__((noinline)) _task_dump_trace_dispatch(int sig)
-{
-	int need_dispatch = 1;
-	task_id_t running = task_get_running();
-
-	if (!pthread_equal(pthread_self(), main_thread)) {
-		need_dispatch = 0;
-	} else if (!task_start_called()) {
-		fprintf(stderr, "Stack trace of main thread:\n");
-		need_dispatch = 0;
-	} else if (in_interrupt_context()) {
-		fprintf(stderr, "Stack trace of ISR:\n");
-	} else {
-		fprintf(stderr, "Stack trace of task %d (%s):\n",
-				running, task_get_name(running));
-	}
-
-	if (need_dispatch) {
-		pthread_kill(task_get_thread(running), SIGNAL_TRACE_DUMP);
-	} else {
-		_task_dump_trace_impl(SIGNAL_TRACE_OFFSET);
-		exit(1);
-	}
-}
-
-void task_register_tracedump(void)
-{
-	/* Trace dumper MUST be registered from main thread */
-	main_thread = pthread_self();
-	signal(SIGNAL_TRACE_DUMP, _task_dump_trace_dispatch);
-}
diff --git a/core/host/task.c b/core/host/task.c
deleted file mode 100644
index be7ed3c579..0000000000
--- a/core/host/task.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Task scheduling / events module for Chrome EC operating system */
-
-#include <malloc.h>
-#include <pthread.h>
-#include <semaphore.h>
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "host_task.h"
-#include "task.h"
-#include "task_id.h"
-#include "test_util.h"
-#include "timer.h"
-
-#define SIGNAL_INTERRUPT SIGUSR1
-
-struct emu_task_t {
-	pthread_t thread;
-	pthread_cond_t resume;
-	uint32_t event;
-	timestamp_t wake_time;
-	uint8_t started;
-};
-
-struct task_args {
-	void (*routine)(void *);
-	void *d;
-};
-
-static struct emu_task_t tasks[TASK_ID_COUNT];
-static pthread_cond_t scheduler_cond;
-static pthread_mutex_t run_lock;
-static task_id_t running_task_id;
-static int task_started;
-
-static sem_t interrupt_sem;
-static pthread_mutex_t interrupt_lock;
-static pthread_t interrupt_thread;
-static int in_interrupt;
-static int interrupt_disabled;
-static void (*pending_isr)(void);
-static int generator_sleeping;
-static timestamp_t generator_sleep_deadline;
-static int has_interrupt_generator = 1;
-
-/* thread local task id */
-static __thread task_id_t my_task_id = TASK_ID_INVALID;
-
-static void task_enable_all_tasks_callback(void);
-
-#define TASK(n, r, d, s) void r(void *);
-CONFIG_TASK_LIST
-CONFIG_TEST_TASK_LIST
-CONFIG_CTS_TASK_LIST
-#undef TASK
-
-/* usleep that uses OS functions, instead of emulated timer. */
-void _usleep(int usec)
-{
-	struct timespec req;
-
-	req.tv_sec = usec / 1000000;
-	req.tv_nsec = (usec % 1000000) * 1000;
-
-	nanosleep(&req, NULL);
-}
-
-/* msleep that uses OS functions, instead of emulated timer. */
-void _msleep(int msec)
-{
-	_usleep(1000 * msec);
-}
-
-/* Idle task */
-void __idle(void *d)
-{
-	while (1)
-		task_wait_event(-1);
-}
-
-void _run_test(void *d)
-{
-	run_test(0, NULL);
-}
-
-#define TASK(n, r, d, s) {r, d},
-const struct task_args task_info[TASK_ID_COUNT] = {
-	{__idle, NULL},
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-	{_run_test, NULL},
-};
-#undef TASK
-
-#define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-	"<< test runner >>",
-};
-#undef TASK
-
-void task_pre_init(void)
-{
-	/* Nothing */
-}
-
-int in_interrupt_context(void)
-{
-	return !!in_interrupt;
-}
-
-test_mockable void interrupt_disable(void)
-{
-	pthread_mutex_lock(&interrupt_lock);
-	interrupt_disabled = 1;
-	pthread_mutex_unlock(&interrupt_lock);
-}
-
-test_mockable void interrupt_enable(void)
-{
-	pthread_mutex_lock(&interrupt_lock);
-	interrupt_disabled = 0;
-	pthread_mutex_unlock(&interrupt_lock);
-}
-
-inline int is_interrupt_enabled(void)
-{
-	return !interrupt_disabled;
-}
-
-static void _task_execute_isr(int sig)
-{
-	in_interrupt = 1;
-	pending_isr();
-	sem_post(&interrupt_sem);
-	in_interrupt = 0;
-}
-
-void task_register_interrupt(void)
-{
-	sem_init(&interrupt_sem, 0, 0);
-	signal(SIGNAL_INTERRUPT, _task_execute_isr);
-}
-
-void task_trigger_test_interrupt(void (*isr)(void))
-{
-	pid_t main_pid;
-	pthread_mutex_lock(&interrupt_lock);
-	if (interrupt_disabled) {
-		pthread_mutex_unlock(&interrupt_lock);
-		return;
-	}
-
-	/* Suspend current task and excute ISR */
-	pending_isr = isr;
-	if (task_started) {
-		pthread_kill(tasks[running_task_id].thread, SIGNAL_INTERRUPT);
-	} else {
-		main_pid = getpid();
-		kill(main_pid, SIGNAL_INTERRUPT);
-	}
-
-	/* Wait for ISR to complete */
-	sem_wait(&interrupt_sem);
-	while (in_interrupt)
-		_usleep(10);
-	pending_isr = NULL;
-
-	pthread_mutex_unlock(&interrupt_lock);
-}
-
-void interrupt_generator_udelay(unsigned us)
-{
-	generator_sleep_deadline.val = get_time().val + us;
-	generator_sleeping = 1;
-	while (get_time().val < generator_sleep_deadline.val)
-		;
-	generator_sleeping = 0;
-}
-
-const char *task_get_name(task_id_t tskid)
-{
-	return task_names[tskid];
-}
-
-pthread_t task_get_thread(task_id_t tskid)
-{
-	return tasks[tskid].thread;
-}
-
-uint32_t task_set_event(task_id_t tskid, uint32_t event)
-{
-	atomic_or(&tasks[tskid].event, event);
-	return 0;
-}
-
-uint32_t *task_get_event_bitmap(task_id_t tskid)
-{
-	return &tasks[tskid].event;
-}
-
-uint32_t task_wait_event(int timeout_us)
-{
-	int tid = task_get_current();
-	int ret;
-	pthread_mutex_lock(&interrupt_lock);
-	if (timeout_us > 0)
-		tasks[tid].wake_time.val = get_time().val + timeout_us;
-
-	/* Transfer control to scheduler */
-	pthread_cond_signal(&scheduler_cond);
-	pthread_cond_wait(&tasks[tid].resume, &run_lock);
-
-	/* Resume */
-	ret = atomic_clear(&tasks[tid].event);
-	pthread_mutex_unlock(&interrupt_lock);
-	return ret;
-}
-
-uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint64_t deadline = get_time().val + timeout_us;
-	uint32_t events = 0;
-	int time_remaining_us = timeout_us;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(events & event_mask)) {
-		/* Collect events to re-post later */
-		events |= task_wait_event(time_remaining_us);
-
-		time_remaining_us = deadline - get_time().val;
-		if (timeout_us > 0 && time_remaining_us <= 0) {
-			/* Ensure we return a TIMER event if we timeout */
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-	}
-
-	/* Re-post any other events collected */
-	if (events & ~event_mask)
-		atomic_or(&tasks[task_get_current()].event,
-			  events & ~event_mask);
-
-	return events & event_mask;
-}
-
-void mutex_lock(struct mutex *mtx)
-{
-	int value = 0;
-	int id = 1 << task_get_current();
-
-	mtx->waiters |= id;
-
-	do {
-		if (mtx->lock == 0) {
-			mtx->lock = 1;
-			value = 1;
-		}
-
-		if (!value)
-			task_wait_event_mask(TASK_EVENT_MUTEX, 0);
-	} while (!value);
-
-	mtx->waiters &= ~id;
-}
-
-void mutex_unlock(struct mutex *mtx)
-{
-	int v;
-	mtx->lock = 0;
-
-	for (v = 31; v >= 0; --v)
-		if ((1ul << v) & mtx->waiters) {
-			mtx->waiters &= ~(1ul << v);
-			task_set_event(v, TASK_EVENT_MUTEX);
-			break;
-		}
-}
-
-task_id_t task_get_current(void)
-{
-	return my_task_id;
-}
-
-task_id_t task_get_running(void)
-{
-	return running_task_id;
-}
-
-void task_print_list(void)
-{
-	int i;
-
-	ccputs("Name         Events\n");
-
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		ccprintf("%4d %-16s %08x\n", i, task_names[i], tasks[i].event);
-		cflush();
-	}
-}
-
-int command_task_info(int argc, char **argv)
-{
-	task_print_list();
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
-			     "Print task info");
-
-static void _wait_for_task_started(int can_sleep)
-{
-	int i, ok;
-
-	while (1) {
-		ok = 1;
-		for (i = 0; i < TASK_ID_COUNT - 1; ++i) {
-			if (!tasks[i].started) {
-				if (can_sleep)
-					msleep(10);
-				else
-					_msleep(10);
-				ok = 0;
-				break;
-			}
-		}
-		if (ok)
-			return;
-	}
-}
-
-void wait_for_task_started(void)
-{
-	_wait_for_task_started(1);
-}
-
-void wait_for_task_started_nosleep(void)
-{
-	_wait_for_task_started(0);
-}
-
-static task_id_t task_get_next_wake(void)
-{
-	int i;
-	timestamp_t min_time;
-	int which_task = TASK_ID_INVALID;
-
-	min_time.val = ~0ull;
-
-	for (i = TASK_ID_COUNT - 1; i >= 0; --i)
-		if (min_time.val >= tasks[i].wake_time.val) {
-			min_time.val = tasks[i].wake_time.val;
-			which_task = i;
-		}
-
-	return which_task;
-}
-
-static int fast_forward(void)
-{
-	/*
-	 * No task has event pending, and thus the next time we have an
-	 * event to process must be either of:
-	 *   1. Interrupt generator triggers an interrupt
-	 *   2. The next wake alarm is reached
-	 * So we should check whether an interrupt may happen, and fast
-	 * forward to the nearest among:
-	 *   1. When interrupt generator wakes up
-	 *   2. When the next task wakes up
-	 */
-	int task_id = task_get_next_wake();
-
-	if (!has_interrupt_generator) {
-		if (task_id == TASK_ID_INVALID) {
-			return TASK_ID_IDLE;
-		} else {
-			force_time(tasks[task_id].wake_time);
-			return task_id;
-		}
-	}
-
-	if (!generator_sleeping)
-		return TASK_ID_IDLE;
-
-	if (task_id != TASK_ID_INVALID &&
-	    tasks[task_id].thread != (pthread_t)NULL &&
-	    tasks[task_id].wake_time.val < generator_sleep_deadline.val) {
-		force_time(tasks[task_id].wake_time);
-		return task_id;
-	} else {
-		force_time(generator_sleep_deadline);
-		return TASK_ID_IDLE;
-	}
-}
-
-int task_start_called(void)
-{
-	return task_started;
-}
-
-void task_scheduler(void)
-{
-	int i;
-	timestamp_t now;
-
-	task_started = 1;
-
-	while (1) {
-		now = get_time();
-		i = TASK_ID_COUNT - 1;
-		while (i >= 0) {
-			/*
-			 * Only tasks with spawned threads are valid to be
-			 * resumed.
-			 */
-			if (tasks[i].thread) {
-				if (tasks[i].event ||
-				    now.val >= tasks[i].wake_time.val)
-					break;
-			}
-			--i;
-		}
-		if (i < 0)
-			i = fast_forward();
-
-		now = get_time();
-		if (now.val >= tasks[i].wake_time.val)
-			tasks[i].event |= TASK_EVENT_TIMER;
-		tasks[i].wake_time.val = ~0ull;
-		running_task_id = i;
-		tasks[i].started = 1;
-		pthread_cond_signal(&tasks[i].resume);
-		pthread_cond_wait(&scheduler_cond, &run_lock);
-	}
-}
-
-void *_task_start_impl(void *a)
-{
-	long tid = (long)a;
-	const struct task_args *arg = task_info + tid;
-	my_task_id = tid;
-	pthread_mutex_lock(&run_lock);
-
-	/* Wait for scheduler */
-	task_wait_event(1);
-	tasks[tid].event = 0;
-
-	/* Start the task routine */
-	(arg->routine)(arg->d);
-
-	/* Catch exited routine */
-	while (1)
-		task_wait_event(-1);
-}
-
-test_mockable void interrupt_generator(void)
-{
-	has_interrupt_generator = 0;
-}
-
-void *_task_int_generator_start(void *d)
-{
-	my_task_id = TASK_ID_INT_GEN;
-	interrupt_generator();
-	return NULL;
-}
-
-int task_start(void)
-{
-	int i = TASK_ID_HOOKS;
-
-	pthread_mutex_init(&run_lock, NULL);
-	pthread_mutex_init(&interrupt_lock, NULL);
-	pthread_cond_init(&scheduler_cond, NULL);
-
-	pthread_mutex_lock(&run_lock);
-
-	/*
-	 * Initialize the hooks task first.  After its init, it will callback to
-	 * enable the remaining tasks.
-	 */
-	tasks[i].event = TASK_EVENT_WAKE;
-	tasks[i].wake_time.val = ~0ull;
-	tasks[i].started = 0;
-	pthread_cond_init(&tasks[i].resume, NULL);
-	pthread_create(&tasks[i].thread, NULL, _task_start_impl,
-		       (void *)(uintptr_t)i);
-	pthread_cond_wait(&scheduler_cond, &run_lock);
-	/*
-	 * Interrupt lock is grabbed by the task which just started.
-	 * Let's unlock it so the next task can be started.
-	 */
-	pthread_mutex_unlock(&interrupt_lock);
-
-	/*
-	 * The hooks task is  waiting in task_wait_event(). Lock interrupt_lock
-	 * here so the first task chosen sees it locked.
-	 */
-	pthread_mutex_lock(&interrupt_lock);
-
-	pthread_create(&interrupt_thread, NULL,
-		       _task_int_generator_start, NULL);
-
-	/*
-	 * Tell the hooks task to continue so that it can call back to enable
-	 * the other tasks.
-	 */
-	pthread_cond_signal(&tasks[i].resume);
-	pthread_cond_wait(&scheduler_cond, &run_lock);
-	task_enable_all_tasks_callback();
-
-	task_scheduler();
-
-	return 0;
-}
-
-static void task_enable_all_tasks_callback(void)
-{
-	int i;
-
-	/* Initialize the remaning tasks. */
-	for (i = 0; i < TASK_ID_COUNT; ++i) {
-		if (tasks[i].thread != (pthread_t)NULL)
-			continue;
-
-		tasks[i].event = TASK_EVENT_WAKE;
-		tasks[i].wake_time.val = ~0ull;
-		tasks[i].started = 0;
-		pthread_cond_init(&tasks[i].resume, NULL);
-		pthread_create(&tasks[i].thread, NULL, _task_start_impl,
-			       (void *)(uintptr_t)i);
-		/*
-		 * Interrupt lock is grabbed by the task which just started.
-		 * Let's unlock it so the next task can be started.
-		 */
-		pthread_mutex_unlock(&interrupt_lock);
-		pthread_cond_wait(&scheduler_cond, &run_lock);
-	}
-
-}
-
-void task_enable_all_tasks(void)
-{
-	/* Signal to the scheduler to enable the remaining tasks. */
-	pthread_cond_signal(&scheduler_cond);
-}
diff --git a/core/host/timer.c b/core/host/timer.c
deleted file mode 100644
index 3c3695cad4..0000000000
--- a/core/host/timer.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Timer module */
-
-#include <stdint.h>
-#include <stdio.h>
-
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static timestamp_t boot_time;
-static int time_set;
-
-void usleep(unsigned us)
-{
-	if (!task_start_called() || task_get_current() == TASK_ID_INVALID) {
-		udelay(us);
-		return;
-	}
-
-	ASSERT(!in_interrupt_context() &&
-	       task_get_current() != TASK_ID_INT_GEN);
-
-	task_wait_event(us);
-}
-
-timestamp_t _get_time(void)
-{
-	static timestamp_t time;
-
-	/*
-	 * We just monotonically increase the microsecond every time we check
-	 * the time. Do not depend on host system time as this introduces
-	 * flakyness in tests. The time is periodically fast forwarded with
-	 * force_time() during the host's task scheduler implementation.
-	 */
-	++time.val;
-	return time;
-}
-
-test_mockable timestamp_t get_time(void)
-{
-	timestamp_t ret = _get_time();
-	ret.val -= boot_time.val;
-	return ret;
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	return get_time().le.lo;
-}
-
-void force_time(timestamp_t ts)
-{
-	timestamp_t now = _get_time();
-	boot_time.val = now.val - ts.val;
-	time_set = 1;
-}
-
-void udelay(unsigned us)
-{
-	timestamp_t deadline;
-
-	if (!in_interrupt_context() && task_get_current() == TASK_ID_INT_GEN) {
-		interrupt_generator_udelay(us);
-		return;
-	}
-
-	deadline.val = get_time().val + us;
-	while (get_time().val < deadline.val)
-		;
-}
-
-int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
-{
-	timestamp_t now_val;
-
-	if (!now) {
-		now_val = get_time();
-		now = &now_val;
-	}
-
-	return ((int64_t)(now->val - deadline.val) >= 0);
-}
-
-void timer_init(void)
-{
-
-	if (!time_set) {
-		/*
-		 * Start the timer just before the 64-bit rollover to try
-		 * and catch 32-bit rollover/truncation bugs.
-		 */
-		timestamp_t ts = {
-			.val = 0xFFFFFFF0
-		};
-
-		force_time(ts);
-	}
-}
diff --git a/core/nds32/__builtin.c b/core/nds32/__builtin.c
deleted file mode 100644
index 7b1d5eea62..0000000000
--- a/core/nds32/__builtin.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-/*
- * __builtin_ffs:
- * Returns one plus the index of the least significant 1-bit of x,
- * or if x is zero, returns zero.
- */
-int __keep __ffssi2(int x)
-{
-	return 32 - __builtin_clz(x & -x);
-}
diff --git a/core/nds32/__divdi3.S b/core/nds32/__divdi3.S
deleted file mode 100644
index d86e8f6273..0000000000
--- a/core/nds32/__divdi3.S
+++ /dev/null
@@ -1,372 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * __divdi3.S: signed 64 bit division
- */
-
-#define NREGS	 $r6
-#define DREGS	 $r8
-#define P1H	 $r1
-#define P1L	 $r0
-#define P2H	 $r3
-#define P2L	 $r2
-#define NUMHI	 $r7
-#define NUMLO	 $r6
-#define DENHI	 $r9
-#define DENLO	 $r8
-#define OFFSET_L 0
-#define OFFSET_H 4
-#define MHI	 P1H
-#define MLO	 P1L
-#define W2	 $r3
-#define W1	 $r5
-#define W0	 $r4
-#define T2	 P1L
-#define NHI	 P1H
-#define NLO	 P1L
-#define D	 $r2
-#define DLO	 $r3
-#define DHI	 $r10
-#define Q	 NHI
-#define QHI	 W0
-#define R	 NLO
-#define RHI	 NHI
-#define M	 T2
-#define M2       DLO
-
-	.text
-	.align	2
-	.globl	umul_ppmm
-	.type	umul_ppmm, @function
-	! =====================================================================
-	! uint64_t umul_ppmm(uint32_t a, uint32_t b)
-	!
-	! This function multiplies `a' by `b' to obtain a 64-bit product. The
-	! product is broken into two 32-bit pieces which are stored in the zl
-	! (low-part at P1L) and zh (high-part at P1H).
-	! =====================================================================
-umul_ppmm:
-	zeh	P2L, $r0	        ! al=a&0xffff
-	srli	P2H, $r0, 16	        ! ah=a>>16
-	zeh	P1L, $r1	        ! bl=b&0xffff
-	srli	P1H, $r1, 16	        ! bh=b>>16
-	mul	W1,  P2L, P1H	        ! zA=al*bh
-	mul	P2L, P2L, P1L	        ! zl=al*bl
-	mul	P1L, P2H, P1L	        ! zB=ah*bl
-	add	W1,  W1,  P1L	        ! zA+=zB
-	slt	$ta, W1,  P1L	        ! zA<zB
-	slli	$ta, $ta, 16	        ! (zA<zB)<<16
-	maddr32 $ta, P2H, P1H	        ! zh=ah*bh+((zA<zB)<<16)
-	srli	P1H, W1,  16	        ! zA>>16
-	add	P1H, P1H, $ta	        ! zh+=(zA>>16)
-	slli	P1L, W1,  16	        ! zA<<=16
-	add	P1L, P1L, P2L	        ! zl+=zA
-	slt	$ta, P1L, P2L	        ! zl<zA
-	add	P1H, P1H, $ta	        ! zh+=(zl<zA)
-	ret
-	.size	umul_ppmm, .-umul_ppmm
-
-	.text
-	.align	2
-	.type	fudiv_qrnnd, @function
-	! =====================================================================
-	! uint64_t fudiv_qrnnd(uint64_t n, uint32_t d)
-	!
-	! This function divides 64-bit numerator n by 32-bit denominator d. The
-	! 64-bit return value contains remainder (low-part at P1L) and quotient
-	! (high-part at P1H).
-	! This function uses a custom calling convention,
-	! with register DHI ($r10) call-clobbered instead of callee-saved.
-	! =====================================================================
-fudiv_qrnnd:
-	srli	DHI, D, 16		! d1 = ll_highpart (d)
-	zeh	W1,  NLO		! ll_lowpart (n0)
-	srli	T2,  NLO, 16		! ll_highpart (n0)
-	divr	QHI, RHI, NHI, DHI	! q1 = n1 / __d1, r1 = n1 % __d1
-	zeh	DLO, D			! d0 = ll_lowpart (d)
-	slli	RHI, RHI, 16		! r1 << 16
-	or	RHI, RHI, T2		! __r1 = (__r1 << 16) | ll_highpart(n0)
-	mul	M,   QHI, DLO		! m =  __q1*__d0
-	slt	$ta, RHI, M		! __r1 < __m
-	beqz	$ta, .L2		! if no, skip
-	addi	QHI, QHI, -1		! __q1--
-	add	RHI, RHI, D		! __r1 += d
-	slt	$ta, RHI, D		! __r1 < d
-	bnez	$ta, .L2		! if yes, skip
-	slt	$ta, RHI, M		! __r1 < __m
-	beqz	$ta, .L2		! if no, skip
-	addi	QHI, QHI, -1		! __q1--
-	add	RHI, RHI, D		! __r1 += d
-.L2:
-	sub	RHI, RHI, M		! __r1 -= __m
-	divr	Q, T2, RHI, DHI		! __q0 = r1 / __d1, __r0 = r1 % __d1
-	slli	T2, T2, 16		! __r0 << 16
-	or	R, T2, W1		! __r0 = (__r0 << 16) | ll_lowpart(n0)
-	mul	M2, DLO, Q		! __m = __q0 * __d0
-	slt	$ta, R, M2		! __r0 < __m
-	beqz	$ta, .L5		! if no, skip
-	add	R, R, D			! __r0 += d
-	addi	Q, Q, -1		! __q0--
-	slt	$ta, R, D		! __r0 < d
-	bnez	$ta, .L5		! if yes, skip
-	slt	$ta, R, M2		! __r0 < __m
-	beqz	$ta, .L5		! if no, skip
-	add	R, R, D			! __r0 += d
-	addi	Q, Q, -1		! __q0--
-
-.L5:
-	sub	R, R, M2		! r = r0 = __r0 - __m
-	slli	QHI, QHI, 16		! __q1 << 16
-	or	Q, Q, QHI		! q = (__q1 << 16) | __q0
-	ret
-	.size	fudiv_qrnnd, .-fudiv_qrnnd
-
-	.align	2
-	.globl	__udivmoddi4
-	.type	__udivmoddi4, @function
-	! =====================================================================
-	! uint64_t __udivmoddi4(uint64_t n, uint64_t d, uint64_t *r)
-	!
-	! This function divides 64-bit numerator n by 64-bit denominator d. The
-	! quotient is returned as 64-bit return value and the 64-bit remainder
-	! is stored at the input address r.
-	! stack allocation:
-	! sp+40 +------------------+
-	!       | q                |
-	! sp+32 +------------------+
-	!       | bm               |
-	! sp+28 +------------------+
-	!       | $lp              |
-	! sp+24 +------------------+
-	!       | $fp              |
-	! sp+20 +------------------+
-	!       | $r10             |
-	! sp+16 +------------------+
-	!       | $r6 - $r9        |
-	! sp    +------------------+
-	! =====================================================================
-__udivmoddi4:
-	addi	$sp, $sp, -40
-	smw.bi	$r6, [$sp], $r10 , 10
-	movd44	NREGS, $r0		! (n1,n0)
-	movd44	DREGS, $r2		! (d1,d0)
-	move	$fp, $r4		! rp
-	bnez	P2H, .L9		! if d1 != 0, skip
-	slt	$ta, NUMHI, DENLO	! n1 < d0
-	beqz	$ta, .L10		! if no, skip
-	move	$r0, DENLO
-	bal	__clzsi2
-	swi	$r0,  [$sp+(28)]	! bm
-	beqz	$r0, .LZskipnorm1	! if bm == 0, skip
-	sll	DENLO, DENLO, $r0	! d0 <<= bm
-	subri	W1, $r0, 32		! 32 - bm
-	srl	W1, NUMLO, W1		! n0 >> (32 - bm)
-	sll	NUMHI, NUMHI, $r0	! n1 << bm
-	or	NUMHI, NUMHI, W1	! n1 =  (n1 << bm) | (n0 >> (32 - bm))
-	sll	NUMLO, NUMLO, $r0	! n0 <<= bm
-.LZskipnorm1:
-	movd44	$r0, NREGS		! (n1,n0)
-	move	$r2, DENLO		! d0
-	bal	fudiv_qrnnd		! calculate q0 n0
-	swi	P1H, [$sp+(32+OFFSET_L)]! q0
-	move	NUMLO, P1L		! n0
-	move	W1, 0
-	swi	W1, [$sp+(32+OFFSET_H)]	! q1 = 0
-	b	.L19
-.L10:
-	beqz	P2L, .LZdivzero		! if d0 != 0, skip
-	move	$r0, DENLO
-	bal	__clzsi2
-	swi	$r0, [$sp+(28)]		! bm
-	bnez	$r0, .LZnorm1		! if bm != 0, skip
-	sub	NUMHI, NUMHI, DENLO	! n1 -= d0
-	movi	W1, 1
-	swi	W1, [$sp+(32+OFFSET_H)]	! q1 = 1
-	b	.L29
-
-	! to eliminate unaligned branch target
-	.align	2
-.LZnorm1:
-	subri	$ta, $r0, 32		! b = 32 - bm
-	sll	DENLO, DENLO, $r0	! d0 <<= bm
-	move	$r2, DENLO
-	srl	W0, NUMLO, $ta		! n0 >> b
-	sll	W1, NUMHI, $r0		! n1 << bm
-	sll	NUMLO, NUMLO, $r0	! n0 <<= bm
-	or	P1L, W1, W0		! n1 = (n1 << bm) | (n0 >> b)
-	srl	P1H, NUMHI, $ta		! n2 = n1 >> b
-	bal	fudiv_qrnnd		! caculate q1, n1
-	swi	P1H, [$sp+(32+OFFSET_H)]! q1
-	move	NUMHI, P1L		! n1
-.L29:
-	movd44	$r0, NREGS		! (n1,n0)
-	move	$r2, DENLO		! d0
-	bal	fudiv_qrnnd		! calcuate q0, n0
-	swi	P1H, [$sp+(32+OFFSET_L)]
-	move	NUMLO, P1L
-
-	! to eliminate unaligned branch target
-	.align	2
-.L19:
-	beqz	$fp, .LZsetq		! if rp == 0, skip
-	lwi	W2, [$sp+(28)]		! bm
-	movi	NUMHI, 0
-	srl	NUMLO, NUMLO, W2	! n0 >> bm
-	b	.LZsetr
-
-	! to eliminate unaligned branch target
-	.align	2
-.LZdivzero:
-	! divide-by-zero exception or quotient = 0 and remainder = 0 returned
-	divr	NUMHI, NUMLO, DENLO, DENLO
-.LZqzero:
-	movi	P1H, 0
-	movi	P1L, 0
-	beqz	$fp, .LZret		! if rp == NULL, skip
-	swi	NUMLO, [$fp+OFFSET_L]	! *rp
-	swi	NUMHI, [$fp+OFFSET_H]
-	b	.LZret
-.L9:
-	slt	$ta, NUMHI, DENHI	! n1 < d1
-	bnez	$ta, .LZqzero		! if yes, skip
-	move	$r0, DENHI
-	bal	__clzsi2
-	swi	$r0, [$sp+(28)]		! bm
-	beqz	$r0, .LZskipnorm2	! if bm == 0, skip
-	subri	W0, $r0, 32		! b = 32 - bm
-	srl	W1, DENLO, W0		! d0 >> b
-	sll	$r2, DENHI, $r0		! d1 << bm
-	or	$r2, $r2, W1		! d1 = (d0 >> b) | (d1 << bm)
-	move	DENHI, $r2
-	sll	DENLO, DENLO, $r0	! d0 <<= bm
-	srl	W2, NUMLO, W0		! n0 >> b
-	sll	NUMLO, NUMLO, $r0	! n0 <<= bm
-	sll	P1L, NUMHI, $r0		! n1 << bm
-	srl	P1H, NUMHI, W0		! n2 = n1 >> b
-	or	P1L, P1L, W2		! n1 = (n0 >> b) | (n1 << bm)
-	bal	fudiv_qrnnd		! calculate  q0, n1
-	swi	P1H, [$sp+(32+OFFSET_L)]
-	move	NUMHI, P1L
-	move	P1L, DENLO		! d0
-	bal	umul_ppmm
-	slt	$ta, NUMHI, MHI		! n1 < m1
-	bnez	$ta, .L46		! if yes, skip
-	bne	MHI, NUMHI, .L45	! if m1 != n1, skip
-	slt	$ta, NUMLO, MLO		! n0 < m0
-	beqz	$ta, .L45		! if no, skip
-.L46:
-	lwi	W2, [$sp+(32+OFFSET_L)]
-	sub	MHI, MHI, DENHI		! m1 - d1
-	addi	W2, W2, -1		! q0--
-	swi	W2, [$sp+(32+OFFSET_L)]
-	sub	W2, MLO, DENLO		! __x = m0 - d0
-	slt	$ta, MLO, W2		! m0 < __x
-	sub	MHI, MHI, $ta		! m1 = m1 - d1 - (__x > m0)
-	move	MLO, W2			! m0 = __x
-.L45:
-	movi	W2, 0
-	swi	W2, [$sp+(32+OFFSET_H)]	! q1 = 0
-	beqz	$fp, .LZsetq		! if yes, skip
-	sub	P1L, NUMLO, MLO		! __x = n0 - m0
-	sub	P1H, NUMHI, MHI		! n1 - m1
-	slt	$ta, NUMLO, P1L		! n0 < __x
-	sub	P1H, P1H, $ta		! n1 = n1 - m1 - (__x > n0)
-	lwi	W2, [$sp+(28)]		! bm
-	subri	W0, W2, 32		! b
-	sll	NUMHI, P1H, W0		! n1 << b
-	srl	NUMLO, P1L, W2		! n0 >> bm
-	or	NUMLO, NUMLO, NUMHI	! (n1 << b) | (n0 >> bm)
-	srl	NUMHI, P1H, W2		! n1 >> bm
-.LZsetr:
-	swi	NUMLO, [$fp+OFFSET_L]	! remainder
-	swi	NUMHI, [$fp+OFFSET_H]
-.LZsetq:
-	lwi	P1L, [$sp+(32+OFFSET_L)]! quotient
-	lwi	P1H, [$sp+(32+OFFSET_H)]
-
-	! to eliminate unaligned branch target
-	.align	2
-.LZret:
-	lmw.bi	$r6, [$sp], $r10 , 10
-	addi	$sp, $sp, 40
-	ret
-
-.LZskipnorm2:
-	move	W2, 0
-	slt	$ta, DENHI, NUMHI	! n1 > d1
-	bnez	$ta, .L52		! if yes, skip
-	slt	$ta, NUMLO, DENLO	! n0 < d0
-	bnez	$ta, .L51		! if yes, skip
-.L52:
-	move	W1, 1
-	swi	W1, [$sp+(32+OFFSET_L)]	! q0 = 1
-	sub	W0, NUMLO, DENLO	! __x = n0 - d0
-	sub	NUMHI, NUMHI, DENHI	! n1 - d1
-	slt	$ta, NUMLO, W0		! n0 < __x
-	sub	NUMHI, NUMHI, $ta	! n1 = n1 -d1 - (_-x > n0)
-	move	NUMLO, W0		! n0 = __x
-	b	.L54
-.L51:
-	swi	W2, [$sp+(32+OFFSET_L)]	! q0 = 0
-.L54:
-	swi	W2, [$sp+(32+OFFSET_H)]	! q1 = 0
-	bnez	$fp, .LZsetr
-	b	.LZsetq
-	.size	__udivmoddi4, .-__udivmoddi4
-
-	.text
-	.align	2
-	.globl	__divdi3
-	.type	__divdi3, @function
-__divdi3:
-	! =====================================================================
-	! uint64_t __divdi3(uint64_t n, uint64-t d)
-	!
-	! This function divides n by d and returns the quotient.
-	!
-	! stack allocation:
-	! sp+8  +-----------------------+
-	!       | $lp                   |
-	! sp+4  +-----------------------+
-	!       | $r6                   |
-	! sp    +-----------------------+
-	! =====================================================================
-	smw.adm	$r6, [$sp], $r6, 2
-
-	xor	$r6, P1H, P2H
-	srai45	$r6, 31			! signof(numerator xor denominator)
-	! abs(denominator)
-	bgez	P2H, .L80
-	neg	P2H, P2H
-	beqz	P2L, .L80
-	neg	P2L, P2L
-	addi	P2H, P2H, -1
-
-.L80:
-	! abs(numerator)
-	bgez	P1H, .L81
-	neg	P1H, P1H
-	beqz	P1L, .L81
-	neg	P1L, P1L
-	addi	P1H, P1H, -1
-
-.L81:
-	! abs(numerator) / abs(denominator)
-	movi	$r4, 0			! ignore remainder
-	bal	__udivmoddi4
-	! numerator / denominator
-	beqz	$r6, .L82
-	or	$r4, P1H, P1L
-	beqz	$r4, .L82
-	neg	P1H, P1H
-	beqz	P1L, .L82
-	neg	P1L, P1L
-	addi	P1H, P1H, -1
-
-	! to eliminate unaligned branch target
-	.align	2
-.L82:
-	lmw.bim	$r6, [$sp], $r6, 2
-	ret
-	.size	__divdi3, .-__divdi3
diff --git a/core/nds32/__libsoftfpu.S b/core/nds32/__libsoftfpu.S
deleted file mode 100644
index 672e6bbb3d..0000000000
--- a/core/nds32/__libsoftfpu.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-	.text
-	.align	2
-	.global	__gtsf2
-	.type	__gtsf2, @function
-__gtsf2:
-	! ---------------------------------------------------------------------
-	! int __gtsf2(float a, float b):
-	! This function returns a value greater than zero if neither argument
-	! is NaN and a is strictly greater than b.
-	! ---------------------------------------------------------------------
-	.global	__gesf2
-	.type	__gesf2, @function
-__gesf2:
-	! ---------------------------------------------------------------------
-	! int __gesf2(float a, float b):
-	! This function returns a value greater than or equal to zero if
-	! neither argument is NaN and a is greater than or equal to b.
-	! ---------------------------------------------------------------------
-	move	$r4, #-1
-	b	.LA
-
-	.global	__eqsf2
-	.type	__eqsf2, @function
-__eqsf2:
-	! ---------------------------------------------------------------------
-	! int __eqsf2(float a, float b):
-	! This function returns zero value if neither argument is NaN,
-	! and a and b are equal.
-	! ---------------------------------------------------------------------
-	.global	__nesf2
-	.type	__nesf2, @function
-__nesf2:
-	! ---------------------------------------------------------------------
-	! int __nesf2(float a, float b):
-	! This function returns a nonzero value if either argument is NaN or if
-	! a and b are unequal.
-	! ---------------------------------------------------------------------
-	.global	__lesf2
-	.type	__lesf2, @function
-__lesf2:
-	! ---------------------------------------------------------------------
-	! int __lesf2(float a, float b):
-	! This function returns a value less than or equal to zero if neither
-	! argument is NaN and a is less than b.
-	! ---------------------------------------------------------------------
-	.global	__ltsf2
-	.type	__ltsf2, @function
-__ltsf2:
-	! ---------------------------------------------------------------------
-	! int __ltsf2(float a, float b):
-	! This function returns a value less than zero if neither argument is
-	! NaN and a is strictly less than b.
-	! ---------------------------------------------------------------------
-	.global	__cmpsf2
-	.type	__cmpsf2, @function
-__cmpsf2:
-	! ---------------------------------------------------------------------
-	! int __cmpsf2(float a, float b);
-	! This function calculates a <=> b. That is, if a is less than b, it
-	! returns -1; if a if greater than b, it returns 1; and if a and b are
-	! equal, it returns 0. If either argument is NaN, it returns 1, But you
-	! should not rely on this; If NaN is a possibility, use higher-level
-	! comparison function __unordsf2().
-	! ---------------------------------------------------------------------
-	move    $r4, #1
-
-	.align	2
-.LA:
-	move    $r5, #0xff000000
-	slli	$r2, $r0, #1
-	slt	$r15, $r5, $r2
-	bnez    $r15, .LMnan		! a is NaN
-	slli	$r3, $r1, #1
-	slt	$r15, $r5, $r3
-	bnez    $r15, .LMnan		! b is NaN
-	xor     $r5, $r0, $r1	        ! a and b have same sign?
-	bgez    $r5, .LSameSign
-.LDiffSign:
-	or      $r2, $r2, $r3
-	beqz	$r2, .LMequ		! 0.0f and -0.0f are equal
-	move    $r2, #1			! when a==0.0f, return 1
-	cmovz   $r0, $r2, $r0		! otherwise, simply return a
-	ret5    $lp
-.LSameSign:
-	sltsi   $r15, $r0, 0		! a < 0 ?
-	bnez	$r15, .LSameSignNeg
-.LSameSignPos:
-	! a >= 0 && b >= 0, return a - b
-	sub     $r0, $r0, $r1
-	ret5    $lp
-.LSameSignNeg:
-	! a < 0 && b < 0, return b - a
-	sub     $r0, $r1, $r0
-	ret5    $lp
-.LMequ:
-	move    $r0, #0
-	ret5    $lp
-.LMnan:
-	move    $r0, $r4
-	ret5    $lp
-	.size   __cmpsf2, .-__cmpsf2
-	.size   __ltsf2, .-__ltsf2
-	.size   __lesf2, .-__lesf2
-	.size   __nesf2, .-__nesf2
-	.size   __eqsf2, .-__eqsf2
-	.size   __gesf2, .-__gesf2
-	.size   __gtsf2, .-__gtsf2
-
-#define MANTA	$r0
-#define EXPOA	$r1
-	.text
-	.align	2
-	.global	__floatsisf
-	.type	__floatsisf, @function
-__floatsisf:
-	beqz	$r0, .LKzero		! A is zero
-	move	$r4, #0x80000000
-	and	$r2, $r0, $r4		! sign(A)
-	beqz	$r2, .LKcont
-	subri	$r0, $r0, #0
-	! abs(A)
-.LKcont:
-	move	EXPOA, #0x9e
-	move	$r5, 16
-	move	$r3, 0
-.LKloop:
-	add	$r3, $r3, $r5
-	srl	$r15, MANTA, $r3
-	bnez	$r15, .LKloop2
-	sll	MANTA, MANTA, $r5
-	sub	EXPOA, EXPOA, $r5
-.LKloop2:
-	srli	$r5, $r5, #1
-	bnez	$r5, .LKloop
-	! do rounding
-	srli	$r4, $r4, #24		! 0x80
-	add	MANTA, MANTA, $r4
-	slt	$r15, MANTA, $r4
-	add	EXPOA, EXPOA, $r15
-	srai	$r4, MANTA, #8
-	andi	$r4, $r4, #1
-	sub	MANTA, MANTA, $r4
-	slli	MANTA, MANTA, #1	! shift out implied 1
-	! pack
-	srli	MANTA, MANTA, #9
-	slli	$r4, EXPOA, #23
-	or	$r0, MANTA, $r4
-	or	$r0, $r0, $r2
-.LKzero:
-	ret5	$lp
-	.size	__floatsisf, .-__floatsisf
-
-#undef EXPOA
-#undef MANTA
-#define VALUA	$r1
-#define EXPOA	VALUA
-#define MANTA	$r2
-#define W0	$r4
-#define W1	$r5
-	.text
-	.align	2
-	.global	__fixsfsi
-	.type	__fixsfsi, @function
-__fixsfsi:
-	slli	VALUA, $r0, #1
-	slli	MANTA, VALUA, #7
-	srli	EXPOA, VALUA, #24
-	subri	EXPOA, EXPOA, #0x9e
-	move	W1, #0x80000000
-	blez	EXPOA, .LJover		! number is too big
-	sltsi	$r15, EXPOA, #0x20
-	beqz	$r15, .LJzero		! number is too small
-	or	MANTA, MANTA, W1
-	srl	MANTA, MANTA, EXPOA
-	sltsi	$r15, $r0, #0
-	subri	$r0, MANTA, #0
-	cmovz	$r0, MANTA, $r15
-	ret5	$lp
-.LJzero:
-	move	$r0, #0
-	ret5	$lp
-.LJover:
-	move	W0, #0x7f800000
-	slt	$r15, W0, $r0
-	beqzs8	.LJnan
-	move	$r0, W1
-	ret5	$lp
-.LJnan:
-	addi	$r0, W1, -1
-	ret5	$lp
-	.size	__fixsfsi, .-__fixsfsi
diff --git a/core/nds32/__muldi3.S b/core/nds32/__muldi3.S
deleted file mode 100644
index ef4a491183..0000000000
--- a/core/nds32/__muldi3.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * __muldi3.S: signed 64 bit multiplication
- */
-
-#define P1H	$r1
-#define P1L	$r0
-#define P2H	$r3
-#define P2L	$r2
-
-	.text
-	.align	2
-	.globl	__muldi3
-	.type	__muldi3, @function
-__muldi3:
-	mul	$r5, P1H, P2L	! (ah=a>>31)*(bl=b&0xffffffff)
-	srli	P1H, P1L, 16	! alh=al>>16
-	maddr32	$r5, P1L, P2H	! ah*bl+(bh=b>>31)*(al=a&0xffffffff)
-	zeh	P1L, P1L	! all=al&0xffff
-	srli	P2H, P2L, 16	! blh=bl>>16
-	zeh	P2L, P2L	! bll=bl&0xffff
-
-	mul	$ta, P1L, P2H	! zA=all*blh
-	mul	$r4, P1L, P2L	! zl=all*bll
-	mul	P2L, P1H, P2L	! zB=alh*bll
-	add	P1L, $ta, P2L	! zA+=zB
-	slt	$ta, P1L, P2L	! zA<zB
-	slli	$ta, $ta, 16	! (zA<zB)<<16
-	slli	P2L, P1L, 16	! zA<<16
-	maddr32	$ta, P1H, P2H	! zh=alh*blh+((zA<zB)<<16)
-	srli	P1H, P1L, 16	! zA>>16
-	add	P1H, P1H, $ta	! zh+=(zA>>16)
-	add	P1L, $r4, P2L	! zl+=(zA<<16)
-	slt	$ta, P1L, $r4	! zl<zA
-	add	P1H, P1H, $ta	! zh+=(zl<zA)
-	add	P1H, P1H, $r5	! zh+=ah*bl+bh*al
-	ret
-	.size	__muldi3, .-__muldi3
diff --git a/core/nds32/__udivdi3.S b/core/nds32/__udivdi3.S
deleted file mode 100644
index 4cb3b058fe..0000000000
--- a/core/nds32/__udivdi3.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * __udivdi3.S: unsigned 64 bit division
- */
-
-	.text
-	.align	2
-	.globl	__udivdi3
-	.type	__udivdi3, @function
-__udivdi3:
-	movi	$r4, 0			! ignore remainder
-	b	__udivmoddi4
-	.size	__udivdi3, .-__udivdi3
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
deleted file mode 100644
index b634c3a551..0000000000
--- a/core/nds32/atomic.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atomic operations for Andes */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include "common.h"
-#include "cpu.h"
-#include "task.h"
-
-typedef int atomic_t;
-typedef atomic_t atomic_val_t;
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	atomic_val_t ret;
-	atomic_t volatile *ptr = addr;
-	uint32_t int_mask = read_clear_int_mask();
-
-	ret = *ptr;
-	*ptr &= ~bits;
-	set_int_mask(int_mask);
-	return ret;
-}
-
-static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
-{
-	atomic_val_t ret;
-	atomic_t volatile *ptr = addr;
-	uint32_t int_mask = read_clear_int_mask();
-
-	ret = *ptr;
-	*ptr |= bits;
-	set_int_mask(int_mask);
-	return ret;
-}
-
-static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
-{
-	atomic_val_t ret;
-	atomic_t volatile *ptr = addr;
-	uint32_t int_mask = read_clear_int_mask();
-
-	ret = *ptr;
-	*ptr += value;
-	set_int_mask(int_mask);
-	return ret;
-}
-
-static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
-{
-	atomic_val_t ret;
-	atomic_t volatile *ptr = addr;
-	uint32_t int_mask = read_clear_int_mask();
-
-	ret = *ptr;
-	*ptr -= value;
-	set_int_mask(int_mask);
-	return ret;
-}
-
-static inline atomic_val_t atomic_clear(atomic_t *addr)
-{
-	atomic_val_t ret;
-	atomic_t volatile *ptr = addr;
-	uint32_t int_mask = read_clear_int_mask();
-
-	ret = *ptr;
-	*ptr = 0;
-	set_int_mask(int_mask);
-	return ret;
-}
-
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/core/nds32/build.mk b/core/nds32/build.mk
deleted file mode 100644
index ddd65c680b..0000000000
--- a/core/nds32/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Andestar v3m architecture core OS files build
-#
-
-# Set coreboot-sdk as the default toolchain for nds32
-NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
-
-# Select Andes bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
-
-# CPU specific compilation flags
-CFLAGS_CPU+=-march=v3m -Os
-LDFLAGS_EXTRA+=-mrelax
-
-ifneq ($(CONFIG_LTO),)
-CFLAGS_CPU+=-flto
-LDFLAGS_EXTRA+=-flto
-endif
-
-core-y=cpu.o init.o panic.o task.o switch.o __muldi3.o math.o __builtin.o
-core-y+=__divdi3.o __udivdi3.o
-core-$(CONFIG_FPU)+=__libsoftfpu.o
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h
deleted file mode 100644
index 7670e5cfad..0000000000
--- a/core/nds32/config_core.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CORE_H
-#define __CROS_EC_CONFIG_CORE_H
-
-/* Linker binary architecture and format */
-#define BFD_ARCH nds32
-#define BFD_FORMAT "elf32-nds32le"
-
-#define CONFIG_SOFTWARE_PANIC
-
-/*
- * The Andestar v3m architecture has no CLZ/CTZ instructions (contrary to v3),
- * so let's use the software implementation.
- */
-#define CONFIG_SOFTWARE_CLZ
-#define CONFIG_SOFTWARE_CTZ
-
-#endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c
deleted file mode 100644
index 6a3f3b5bc4..0000000000
--- a/core/nds32/cpu.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Set up the N8 core
- */
-
-#include "cpu.h"
-#include "registers.h"
-
-void cpu_init(void)
-{
-	/* DLM initialization is done in init.S */
-	/* Global interrupt enable */
-	asm volatile ("setgie.e");
-}
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
deleted file mode 100644
index 3bd5a93efc..0000000000
--- a/core/nds32/cpu.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for Andes cores
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-/*
- * This is the space required by both irq_x_ and __switch_task to store all
- * of the caller and callee registers for each task context before switching.
- */
-#define TASK_SCRATCHPAD_SIZE (18)
-
-/* Process Status Word bits */
-#define PSW_GIE		BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT	1        /* Interrupt Stack Level */
-#define PSW_INTL_MASK	(0x3 << PSW_INTL_SHIFT)
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/* write Process Status Word privileged register */
-static inline void set_psw(uint32_t val)
-{
-	asm volatile ("mtsr %0, $PSW" : : "r"(val));
-}
-
-/* read Process Status Word privileged register */
-static inline uint32_t get_psw(void)
-{
-	uint32_t ret;
-	asm volatile ("mfsr %0, $PSW" : "=r"(ret));
-	return ret;
-}
-
-/* write Interruption Program Counter privileged register */
-static inline void set_ipc(uint32_t val)
-{
-	asm volatile ("mtsr %0, $IPC" : : "r"(val));
-}
-
-/* read Interruption Program Counter privileged register */
-static inline uint32_t get_ipc(void)
-{
-	uint32_t ret;
-	asm volatile ("mfsr %0, $IPC" : "=r"(ret));
-	return ret;
-}
-
-/* read Interruption Type privileged register */
-static inline uint32_t get_itype(void)
-{
-	uint32_t ret;
-	asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
-	return ret;
-}
-
-/* Generic CPU core initialization */
-void cpu_init(void);
-
-extern uint32_t ilp;
-extern uint32_t ec_reset_lp;
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
deleted file mode 100644
index 2c21b94761..0000000000
--- a/core/nds32/ec.lds.S
+++ /dev/null
@@ -1,321 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "config.h"
-
-#define STRINGIFY0(name) #name
-#define STRINGIFY(name) STRINGIFY0(name)
-
-#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
-
-#define FW_SIZE_(section) CONFIG_##section##_SIZE
-#define FW_SIZE(section) FW_SIZE_(section)
-
-
-OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
-OUTPUT_ARCH(BFD_ARCH)
-ENTRY(reset)
-
-MEMORY
-{
-	FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
-	IRAM (rw)  : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
-	H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE
-#endif
-}
-
-SECTIONS
-{
-	.text : {
-		/*
-		 * We put "__flash_dma_start" at the beginning of
-		 * the text section to avoid gap.
-		 */
-		__flash_dma_start = .;
-		ASSERT((__flash_dma_start == 0),
-		       "__flash_dma_start has to be 4k-byte aligned");
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vecttable))
-		. = ALIGN(4);
-		__image_data_offset = .;
-		KEEP(*(.rodata.ver))
-		. = ALIGN(4);
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vectirq))
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text))
-		KEEP(*(.flash_direct_map))
-		. = ALIGN(16);
-		KEEP(*(.ram_code))
-		__flash_dma_size = . - __flash_dma_start;
-		ASSERT((__flash_dma_size < IT83XX_ILM_BLOCK_SIZE),
-		       "__flash_dma_size < IT83XX_ILM_BLOCK_SIZE");
-		. = ALIGN(IT83XX_ILM_BLOCK_SIZE);
-		__flash_text_start = .;
-		*(.text*)
-	} > FLASH
-	. = ALIGN(4);
-	.rodata :  {
-		/* Symbols defined here are declared in link_defs.h */
-		__irqprio = .;
-		KEEP(*(.rodata.irqprio))
-		__irqprio_end = .;
-
-		. = ALIGN(4);
-		__irqhandler = .;
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.rodata.vecthandlers))
-
-		. = ALIGN(4);
-		__cmds = .;
-		KEEP(*(SORT(.rodata.cmds*)))
-		__cmds_end = .;
-
-		. = ALIGN(4);
-		__hcmds = .;
-		KEEP(*(SORT(.rodata.hcmds*)))
-		__hcmds_end = .;
-
-		. = ALIGN(4);
-		__mkbp_evt_srcs = .;
-		KEEP(*(.rodata.evtsrcs))
-		__mkbp_evt_srcs_end = .;
-
-		. = ALIGN(4);
-		__hooks_init = .;
-		KEEP(*(.rodata.HOOK_INIT))
-		__hooks_init_end = .;
-
-		__hooks_pre_freq_change = .;
-		KEEP(*(.rodata.HOOK_PRE_FREQ_CHANGE))
-		__hooks_pre_freq_change_end = .;
-
-		__hooks_freq_change = .;
-		KEEP(*(.rodata.HOOK_FREQ_CHANGE))
-		__hooks_freq_change_end = .;
-
-		__hooks_sysjump = .;
-		KEEP(*(.rodata.HOOK_SYSJUMP))
-		__hooks_sysjump_end = .;
-
-		__hooks_chipset_pre_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_PRE_INIT))
-		__hooks_chipset_pre_init_end = .;
-
-		__hooks_chipset_startup = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_STARTUP))
-		__hooks_chipset_startup_end = .;
-
-		__hooks_chipset_resume = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME))
-		__hooks_chipset_resume_end = .;
-
-		__hooks_chipset_suspend = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND))
-		__hooks_chipset_suspend_end = .;
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		__hooks_chipset_resume_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME_INIT))
-		__hooks_chipset_resume_init_end = .;
-
-		__hooks_chipset_suspend_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND_COMPLETE))
-		__hooks_chipset_suspend_complete_end = .;
-#endif
-
-		__hooks_chipset_shutdown = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN))
-		__hooks_chipset_shutdown_end = .;
-
-		__hooks_chipset_shutdown_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
-		__hooks_chipset_shutdown_complete_end = .;
-
-		__hooks_chipset_hard_off = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
-		__hooks_chipset_hard_off_end = .;
-
-		__hooks_chipset_reset = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
-		__hooks_chipset_reset_end = .;
-
-		__hooks_ac_change = .;
-		KEEP(*(.rodata.HOOK_AC_CHANGE))
-		__hooks_ac_change_end = .;
-
-		__hooks_lid_change = .;
-		KEEP(*(.rodata.HOOK_LID_CHANGE))
-		__hooks_lid_change_end = .;
-
-		__hooks_tablet_mode_change = .;
-		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
-		__hooks_tablet_mode_change_end = .;
-
-		__hooks_base_attached_change = .;
-		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
-		__hooks_base_attached_change_end = .;
-
-		__hooks_pwrbtn_change = .;
-		KEEP(*(.rodata.HOOK_POWER_BUTTON_CHANGE))
-		__hooks_pwrbtn_change_end = .;
-
-		__hooks_battery_soc_change = .;
-		KEEP(*(.rodata.HOOK_BATTERY_SOC_CHANGE))
-		__hooks_battery_soc_change_end = .;
-
-#ifdef CONFIG_USB_SUSPEND
-		__hooks_usb_change = .;
-		KEEP(*(.rodata.HOOK_USB_PM_CHANGE))
-		__hooks_usb_change_end = .;
-#endif
-
-		__hooks_tick = .;
-		KEEP(*(.rodata.HOOK_TICK))
-		__hooks_tick_end = .;
-
-		__hooks_second = .;
-		KEEP(*(.rodata.HOOK_SECOND))
-		__hooks_second_end = .;
-
-		__hooks_usb_pd_disconnect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_DISCONNECT))
-		__hooks_usb_pd_disconnect_end = .;
-
-		__hooks_usb_pd_connect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
-		__hooks_usb_pd_connect_end = .;
-
-		__deferred_funcs = .;
-		KEEP(*(.rodata.deferred))
-		__deferred_funcs_end = .;
-
-		. = ALIGN(4);
-		*(.rodata*)
-
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-	ASSERT(0, "CONFIG_CHIP_INIT_ROM_REGION not supported by linker script")
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-		/*
-		 * This linker file does not yet support a separate ROM resident
-		 * section. Ensure the corresponding data objects are linked
-		 * into the .rodata section.
-		 */
-		. = ALIGN(4);
-		__init_rom_start = .;
-		*(.init.rom)
-		__init_rom_end = .;
-
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
-		. = ALIGN(64);
-		KEEP(*(.google))
-#endif
-		. = ALIGN(4);
-	} >FLASH
-
-	__data_lma_start = . ;
-
-	.data : {
-		. = ALIGN(4);
-		__data_start = .;
-		*(.data.tasks)
-		*(.data)
-#ifdef CONFIG_MPU
-		/* It has to be aligned by 32 bytes to be a valid MPU region. */
-		. = ALIGN(32);
-		__iram_text_start = .;
-#else
-		. = ALIGN(4);
-#endif
-		*(.iram.text)
-#ifdef CONFIG_MPU
-		. = ALIGN(32);
-		__iram_text_end = .;
-#else
-		. = ALIGN(4);
-#endif
-		__data_end = .;
-
-	} > IRAM AT>FLASH
-
-	.bss : {
-		/* Stacks must be 64-bit aligned */
-		. = ALIGN(8);
-		__bss_start = .;
-		*(.bss.tasks)
-		. = ALIGN(8);
-		*(.bss.system_stack)
-		. = ALIGN(8);
-		*(.bss.task_scratchpad)
-		/* Rest of .bss takes care of its own alignment */
-		*(.bss)
-		*(.bss.slow)
-
-		/*
-		 * Reserve space for deferred function firing times.
-		 * Each time is a uint64_t, each func is a 32-bit pointer,
-		 * thus the scaling factor of two.
-		 */
-		. = ALIGN(8);
-		__deferred_until = .;
-		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
-		__deferred_until_end = .;
-
-		. = ALIGN(4);
-		__bss_end = .;
-
-		/*
-		 * Shared memory buffer must be at the end of preallocated RAM,
-		 * so it can expand to use all the remaining RAM.
-		 */
-		__shared_mem_buf = .;
-
-	} > IRAM
-
-	ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <=
-	       (CONFIG_RAM_BASE + CONFIG_RAM_SIZE),
-	       "Not enough space for shared memory.")
-	__ram_free = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE) -
-		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
-
-	/*
-	 * __flash_used is used in flash free calculations by the makefile.
-	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
-	 */
-	__flash_used = LOADADDR(.data) + SIZEOF(.data) - FW_OFF(SECTION);
-	__image_size = __flash_used;
-
-#ifdef CONFIG_FLASH_CROS
-        /*
-         * These linker labels are just for analysis and not used in the code.
-         */
-	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
-	__config_ro_size = CONFIG_RO_SIZE;
-	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
-	__config_rw_size = CONFIG_RW_SIZE;
-	__config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-#endif
-
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
-	.h2ram (NOLOAD) : {
-		. += CONFIG_H2RAM_HOST_LPC_IO_BASE;
-		*(.h2ram.pool.hostcmd)
-		. = ALIGN(256);
-		*(.h2ram.pool.acpiec)
-#ifdef CONFIG_I2C_PERIPHERAL
-		. = ALIGN(256);
-		*(.h2ram.pool.i2cslv)
-#endif
-		__h2ram_end = .;
-	} > H2RAM
-
-	ASSERT((__h2ram_end) <= (CONFIG_H2RAM_BASE + CONFIG_H2RAM_SIZE),
-	       "Not enough space for h2ram section.")
-#endif
-
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
-	/DISCARD/ : { *(.google) }
-#endif
-
-	/DISCARD/ : { *(.ARM.*) }
-}
diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h
deleted file mode 100644
index 4f3efc2e5a..0000000000
--- a/core/nds32/include/fpu.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for N8 */
-
-#ifndef __CROS_EC_FPU_H
-#define __CROS_EC_FPU_H
-
-float sqrtf(float x);
-float fabsf(float x);
-
-#endif  /* __CROS_EC_FPU_H */
diff --git a/core/nds32/init.S b/core/nds32/init.S
deleted file mode 100644
index b8e109c434..0000000000
--- a/core/nds32/init.S
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * N8 CPU initialization
- */
-
-#include "config.h"
-
-/* magic macro to implement IRQ prefix / exit */
-.macro vector name, entry_number
-.weak \name\()_handler
-.set \name\()_handler, unhandled_irq
-j __entry_\()\name
-.pushsection .text.vectirq
-.global __entry_\()\name
-__entry_\()\name:
-	/* the context is stored on the current task stack*/
-	/* save r15, fp, lp and sp */
-	smw.adm $r15, [$sp], $r15, 0xb
-	/* r0-r5 are caller saved */
-	smw.adm $r0,  [$sp], $r5, 0
-	/* store link pointer register */
-	swi.gp  $lp, [ + ilp]
-	/* switch to system stack if we are called from process stack */
-	la $r3, stack_end
-	mov55 $fp, $sp
-	slt45 $r3, $sp /* if sp > end of system stack, then r15 = 1 and */
-	cmovn $sp, $r3, $r15 /* point sp to the top of the system stack */
-	/* save entry number of HW interrupt */
-	movi55  $r3, \entry_number\()
-	swi.gp  $r3, [ + cpu_int_entry_number]
-	/* isr entry */
-	jal start_irq_handler
-	/* C routine handler */
-	jal \name\()_handler
-	/* check whether we need to change the scheduled task */
-	lwi.gp  $r2, [ + need_resched]
-	bnez $r2, __switch_task
-	/* isr exit */
-	jal end_irq_handler
-	/* restore r0-r5 */
-	lmw.bim $r0, [$fp], $r5, 0
-	/* restore r15, fp, lp and sp */
-	lmw.bi $r15, [$fp], $r15, 0xb
-	/* restore PC and PSW */
-	iret
-.popsection
-.pushsection .rodata.vecthandlers
-.long \name\()_handler
-.popsection
-.endm
-
-.section .text.vecttable
-
-/* Exceptions vector */
-vectors:
-j reset		/* reset / NMI */
-j excep_handler	/* TLB fill */
-j excep_handler	/* PTE not present */
-j excep_handler	/* TLB misc */
-j excep_handler	/* TLB VLPT miss */
-j excep_handler	/* Machine error */
-j excep_handler	/* Debug related */
-j excep_handler	/* General exception */
-vector syscall, -1	/* Syscall */
-vector irq_0,    0	/* HW  0 */
-vector irq_1,    1	/* HW  1 */
-vector irq_2,    2	/* HW  2 */
-vector irq_3,    3	/* HW  3 */
-vector irq_4,    4	/* HW  4 */
-vector irq_5,    5	/* HW  5 */
-vector irq_6,    6	/* HW  6 */
-vector irq_7,    7	/* HW  7 */
-vector irq_8,    8	/* HW  8 */
-vector irq_9,    9	/* HW  9 */
-vector irq_10,   10	/* HW 10 */
-vector irq_11,   11	/* HW 11 */
-vector irq_12,   12	/* HW 12 */
-vector irq_13,   13	/* HW 13 */
-vector irq_14,   14	/* HW 14 */
-vector irq_15,   15	/* HW 15 */
-
-/* E-flash signature */
-.org 0x80
-.balign 16
-.global eflash_sig
-eflash_sig:
-.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
-.byte 0xA4 /* eSPI */
-#else
-.byte 0xA5 /* LPC */
-#endif
-.byte 0xB4 /* flag of signature */
-.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
-/* flags: internal oscillator + implicit location */
-
-.text
-
-.global reset
-reset:
-        /*
-         * GIE (global interrupt) is always disabled here. the first
-         * "iret" instruction of syscall interrupt (triggered by __task_start)
-         * will restore PSW from IPSW, and will enable GIE.
-         * Firmware will not change GIE settings (set/clear) until the next
-         * reset, unless there's an interrupt event.
-         * When there is an interrupt event, N8 CPU will save PSW register to
-         * IPSW register and clear GIE then jump to interrupt service routine.
-         * N8 will restore PSW from IPSW after "iret" instruction.
-         */
-        setgie.d
-        dsb
-
-	/* GP register is used to access .data and .bss */
-	la $gp, _SDA_BASE_
-
-	/* Set system stack pointer. */
-	la $sp, stack_end
-
-	/*
-	 * move content of lp into r5 and then store the content
-	 * into variable "ec_reset_lp" later after memory initialization.
-	 */
-	mov55 $r5, $lp
-
-	/* map/enable the 16kB of DLM at 0x00080000 */
-	li   $r0, 0x00080005
-	mtsr $r0, $mr7
-
-	/* Set ROM address at 0x80000 (disabled). */
-	li  $r1, 0x00F0109B
-	movi $r0, #0x8
-	sbi $r0, [$r1]
-
-	/* Enable DLM 8k~12K(bit2) and DLM 12k~16k(bit3) */
-	li  $r1, 0x00F02030
-	lbi $r0, [$r1]
-	ori $r0, $r0, 0x0C
-	sbi $r0, [$r1]
-
-	/* Enable DLM 16k~36K bit[2-6] */
-	li  $r1, 0x00F0203E
-	lbi $r0, [$r1]
-	ori $r0, $r0, 0x7C
-	sbi $r0, [$r1]
-
-	/* Enable DLM 36k~48K bit[0-2] */
-	li  $r1, 0x00F02044
-	lbi $r0, [$r1]
-	ori $r0, $r0, 0x7
-	sbi $r0, [$r1]
-
-	/* Clear BSS */
-	la   $r0, _bss_start
-	lwi  $r1, [$r0]
-	la   $r0, _bss_end
-	lwi  $r2, [$r0]
-	movi $r0, #0
-bss_loop:
-	swi.bi $r0, [$r1], 4
-	bne $r1, $r2, bss_loop
-
-	/* Copy initialized data to DLM */
-	la $r0, _data_start
-	lwi  $r1, [$r0]
-	la $r0, _data_end
-	lwi  $r2, [$r0]
-	la $r0, _data_lma_start
-	lwi  $r0, [$r0]
-data_loop:
-	lwi.bi $r3, [$r0], 4
-	swi.bi $r3, [$r1], 4
-	bne $r1, $r2, data_loop
-
-	/* store the content of r5 (lp after reset) into "ec_reset_lp" */
-	swi.gp  $r5, [ + ec_reset_lp]
-
-	/* we switch to our own exception vectors */
-	/* go back to it level 0 with HW interrupts globally disabled */
-	li   $r4, 0x70008
-	mtsr $r4, $PSW
-	/* IT8380 specific: set vectors at 0 */
-	li   $r5, 0x0F02041 /* IVTBAR in GCTRL */
-	movi $r15, 0
-	sbi  $r15, [$r5]
-	/* Interrupt vectors are every 4 bytes */
-	li   $r5, 0x00000007
-	mtsr $r5, $IVB
-
-	/* clear BRAM if it is not valid */
-	jal chip_bram_valid
-	/* Jump to C routine */
-	jal main
-
-	/* That should not return.  If it does, loop forever. */
-	j .
-
-.global unhandled_irq
-unhandled_irq:
-	mfsr $gp, $ITYPE
-	sethi $r15, 0xBAD0
-	or   $r15, $r15, $gp
-	mtsr $r15, $ITYPE
-	dsb
-	j excep_handler /* display exception with ITYPE=bad00<irq> */
-
-.global excep_handler
-excep_handler:
-#ifdef CONFIG_FPU
-	/*
-	 * We have to restore ALU so that we can continue the next
-	 * sequence if arithmetic instructions are used.
-	 * (Apply to floating point division by zero)
-	 */
-	sethi   $gp, 0x80
-	ori     $gp, $gp,0x9
-	mtsr    $gp, $dlmb
-	dsb
-#endif
-	/* safety: reload GP even though it should be already set */
-	la $gp, _SDA_BASE_
-	/* save r0 to free one register */
-	swi.gp  $r0, [ + saved_regs]
-	/* save the remaining 15 registers */
-	la      $r0, saved_regs + 4
-	smw.bim $r1, [$r0], $r10, 0
-	smw.bim $r15,[$r0], $r15, 0xF
-	/* put a valid stack pointer */
-	la $sp, stack_end
-	/* add IPC, IPSW to the context */
-	mfsr    $r1, $IPC
-	mfsr    $r2, $IPSW
-	smw.bi  $r1, [$r0], $r2, 0
-	/* pass ir6/ITYPE as the second parameter */
-	mfsr    $r1, $ITYPE
-	/* exception context pointer as first parameter */
-	addi    $r0, $r0, -16*4
-	/* jump to panic dump C routine */
-	jal report_panic
-	/* we never return: exceptions are fatal */
-	j .
-
-.align 2
-_bss_start:
-.long __bss_start
-_bss_end:
-.long __bss_end
-_data_start:
-.long __data_start
-_data_end:
-.long __data_end
-_data_lma_start:
-.long __data_lma_start
-
-/* Reserve space for system stack */
-.section .bss.system_stack
-stack_start:
-.space CONFIG_STACK_SIZE, 0
-stack_end:
-.global stack_end
-/* registers state at exception entry */
-.global saved_regs
-saved_regs:
-.long 0, 0, 0, 0, 0, 0, 0, 0
-.long 0, 0, 0, 0, 0, 0, 0, 0
-/* IPC, IPSW for convenient access */
-.long 0, 0
diff --git a/core/nds32/irq_chip.h b/core/nds32/irq_chip.h
deleted file mode 100644
index ca517558b3..0000000000
--- a/core/nds32/irq_chip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Chip-specific part of the IRQ handling.
- */
-
-#ifndef __CROS_EC_IRQ_CHIP_H
-#define __CROS_EC_IRQ_CHIP_H
-
-/**
- * Enable an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- */
-void chip_enable_irq(int irq);
-
-/**
- * Disable an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- */
-void chip_disable_irq(int irq);
-
-/**
- * Clear a pending IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- *
- * Note that most interrupts can be removed from the pending state simply by
- * handling whatever caused the interrupt in the first place.  This only needs
- * to be called if an interrupt handler disables itself without clearing the
- * reason for the interrupt, and then the interrupt is re-enabled from a
- * different context.
- */
-void chip_clear_pending_irq(int irq);
-
-/**
- * Software-trigger an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- * @return CPU interrupt number to trigger if any, -1 else.
- */
-int chip_trigger_irq(int irq);
-
-/**
- * Initialize chip interrupt controller.
- */
-void chip_init_irqs(void);
-
-/**
- * Return external interrupt number.
- */
-int chip_get_ec_int(void);
-
-/**
- * Return group number of the given external interrupt number.
- */
-int chip_get_intc_group(int irq);
-
-#endif /* __CROS_EC_IRQ_CHIP_H */
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
deleted file mode 100644
index eb55d9e233..0000000000
--- a/core/nds32/irq_handler.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helper to declare IRQ handling routines */
-
-#ifndef __CROS_EC_IRQ_HANDLER_H
-#define __CROS_EC_IRQ_HANDLER_H
-
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
-/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	void routine(void);						\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
-
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/nds32/math.c b/core/nds32/math.c
deleted file mode 100644
index 496fcc0e5d..0000000000
--- a/core/nds32/math.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#ifdef CONFIG_FPU
-union ieee_float_shape_type {
-	float value;
-	uint32_t word;
-};
-
-/* Get a 32 bit int from a float.  */
-#define GET_FLOAT_WORD(i, d) \
-	do { \
-		union ieee_float_shape_type gf_u; \
-		gf_u.value = (d); \
-		(i) = gf_u.word; \
-	} while (0)
-
-/* Set a float from a 32 bit int. */
-#define SET_FLOAT_WORD(d, i) \
-	do { \
-		union ieee_float_shape_type sf_u; \
-		sf_u.word = (i); \
-		(d) = sf_u.value; \
-	} while (0)
-
-float fabsf(float x)
-{
-	uint32_t ix;
-
-	GET_FLOAT_WORD(ix, x);
-	SET_FLOAT_WORD(x, (ix & 0x7fffffff));
-
-	return x;
-}
-
-#define FLT_UWORD_IS_ZERO(x) ((x) == 0)
-#define FLT_UWORD_IS_SUBNORMAL(x) ((x) < 0x00800000L)
-#define FLT_UWORD_IS_FINITE(x) ((x) < 0x7f800000L)
-
-static const float one = 1.0f, tiny = 1.0e-30f;
-static float __ieee754_sqrtf(float x)
-{
-	float z;
-	uint32_t r, hx;
-	int32_t ix, s, q, m, t, i;
-
-	GET_FLOAT_WORD(ix, x);
-	hx = ix & 0x7fffffff;
-
-	/*
-	 * take care of Inf and NaN
-	 * sqrt(NaN)=NaN, sqrt(+inf)=+inf, sqrt(-inf)=sNaN
-	 */
-	if (!FLT_UWORD_IS_FINITE(hx))
-		return x * x + x;
-	/* take care of zero and -ves */
-	if (FLT_UWORD_IS_ZERO(hx))
-		return x;
-	if (ix < 0)
-		return (x - x) / (x - x);
-
-	m = (ix >> 23);
-	if (FLT_UWORD_IS_SUBNORMAL(hx)) {
-		for (i = 0; (ix & 0x00800000L) == 0; i++)
-			ix <<= 1;
-		m -= i - 1;
-	}
-
-	m -= 127;
-	ix = (ix & 0x007fffffL) | 0x00800000L;
-	if (m & 1)
-		ix += ix;
-
-	m >>= 1;
-	ix += ix;
-	q = s = 0;
-	r = 0x01000000L;
-
-	while (r != 0) {
-		t = s + r;
-		if (t <= ix) {
-			s = t + r;
-			ix -= t;
-			q += r;
-		}
-		ix += ix;
-		r >>= 1;
-	}
-
-	if (ix != 0) {
-		z = one - tiny;
-		if (z >= one) {
-			z = one + tiny;
-			if (z > one)
-				q += 2;
-			else
-				q += (q & 1);
-		}
-	}
-
-	ix = (q >> 1) + 0x3f000000L;
-	ix += (m << 23);
-	SET_FLOAT_WORD(z, ix);
-
-	return z;
-}
-
-float sqrtf(float x)
-{
-	return __ieee754_sqrtf(x);
-}
-#endif
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
deleted file mode 100644
index 70e2cae3e0..0000000000
--- a/core/nds32/panic.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "panic.h"
-#include "printf.h"
-#include "software_panic.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* General purpose register (r6) for saving software panic reason */
-#define SOFT_PANIC_GPR_REASON 6
-/* General purpose register (r7) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   7
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-/**
- * bit[4] @ ITYPE, Indicates if an exception is caused by an instruction fetch
- * or a data memory access for the following exceptions:
- * -TLB fill
- * -TLB VLPT miss
- * -TLB read protection
- * -TLB write protection
- * -TLB non-executable page
- * -TLB page modified
- * -TLB Access bit
- * -PTE not present (all)
- * -Reserved PTE Attribute
- * -Alignment check
- * -Branch target alignment
- * -Machine error
- * -Precise bus error
- * -Imprecise bus error
- * -Nonexistent local memory address
- * -MPZIU Control
- * -Cache locking error
- * -TLB locking error
- * -TLB multiple hit
- * -Parity/ECC error
- * All other exceptions not in the abovetable should have the INST field of
- * the ITYPE register set to 0.
- */
-static const char * const itype_inst[2] = {
-	"a data memory access",
-	"an instruction fetch access",
-};
-
-/**
- * bit[3-0] @ ITYPE, general exception type information.
- */
-static const char * const itype_exc_type[16] = {
-	"Alignment check",
-	"Reserved instruction",
-	"Trap",
-	"Arithmetic",
-	"Precise bus error",
-	"Imprecise bus error",
-	"Coprocessor",
-	"Privileged instruction",
-
-	"Reserved value",
-	"Nonexistent local memory address",
-	"MPZIU Control",
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-};
-#endif /* CONFIG_DEBUG_EXCEPTIONS */
-
-#ifdef CONFIG_SOFTWARE_PANIC
-void software_panic(uint32_t reason, uint32_t info)
-{
-	asm volatile ("mov55  $r6, %0" : : "r"(reason));
-	asm volatile ("mov55  $r7, %0" : : "r"(info));
-	if (in_interrupt_context())
-		asm("j excep_handler");
-	else
-		asm("break 0");
-	__builtin_unreachable();
-}
-
-void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
-{
-	/*
-	 * It is safe to get pointer using get_panic_data_write().
-	 * If it was called earlier (eg. when saving nds_n8.ipc) calling it
-	 * once again won't remove any data
-	 */
-	struct panic_data * const pdata = get_panic_data_write();
-	uint32_t warning_ipc;
-	uint32_t *regs;
-
-	regs = pdata->nds_n8.regs;
-
-	/* Setup panic data structure */
-	if (reason != PANIC_SW_WATCHDOG) {
-		memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-	} else {
-		warning_ipc = pdata->nds_n8.ipc;
-		memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-		pdata->nds_n8.ipc = warning_ipc;
-	}
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_NDS32_N8;
-
-	/* Log panic cause */
-	pdata->nds_n8.itype = exception;
-	regs[SOFT_PANIC_GPR_REASON] = reason;
-	regs[SOFT_PANIC_GPR_INFO] = info;
-}
-
-void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
-{
-	struct panic_data * const pdata = panic_get_data();
-	uint32_t *regs;
-
-	if (pdata && pdata->struct_version == 2) {
-		regs = pdata->nds_n8.regs;
-		*exception = pdata->nds_n8.itype;
-		*reason = regs[SOFT_PANIC_GPR_REASON];
-		*info = regs[SOFT_PANIC_GPR_INFO];
-	} else {
-		*exception = *reason = *info = 0;
-	}
-}
-#endif /* CONFIG_SOFTWARE_PANIC */
-
-static void print_panic_information(uint32_t *regs, uint32_t itype,
-					uint32_t ipc, uint32_t ipsw)
-{
-	panic_printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	panic_printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
-	if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) {
-		/* 2nd level exception */
-		uint32_t oipc;
-
-		asm volatile("mfsr %0, $OIPC" : "=r"(oipc));
-		panic_printf("OIPC %08x\n", oipc);
-	}
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-	panic_printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff));
-	if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		panic_printf("Software panic reason %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-					  PANIC_SW_BASE)]);
-		panic_printf("Software panic info 0x%x\n",
-			regs[SOFT_PANIC_GPR_INFO]);
-#endif
-	} else {
-		panic_printf("Exception type: General exception [%s]\n",
-			itype_exc_type[(itype & 0xf)]);
-		panic_printf("Exception is caused by %s\n",
-			itype_inst[(itype & BIT(4))]);
-	}
-#endif
-}
-
-void report_panic(uint32_t *regs, uint32_t itype)
-{
-	int i;
-	struct panic_data * const pdata = get_panic_data_write();
-
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_NDS32_N8;
-	pdata->flags = 0;
-	pdata->reserved = 0;
-
-	pdata->nds_n8.itype = itype;
-	for (i = 0; i < 16; i++)
-		pdata->nds_n8.regs[i] = regs[i];
-	pdata->nds_n8.ipc = regs[16];
-	pdata->nds_n8.ipsw = regs[17];
-
-	print_panic_information(regs, itype, regs[16], regs[17]);
-	panic_reboot();
-}
-
-void panic_data_print(const struct panic_data *pdata)
-{
-	uint32_t itype, *regs, ipc, ipsw;
-	itype = pdata->nds_n8.itype;
-	regs = (uint32_t *)pdata->nds_n8.regs;
-	ipc = pdata->nds_n8.ipc;
-	ipsw = pdata->nds_n8.ipsw;
-
-	print_panic_information(regs, itype, ipc, ipsw);
-}
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
deleted file mode 100644
index 631b0e0fe2..0000000000
--- a/core/nds32/switch.S
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Context switching
- */
-
-#include "config.h"
-#include "cpu.h"
-
-.section .ram_code
-
-/**
- * Task context switching
- *
- * Change the task scheduled after returning from an interruption.
- *
- * This function must be called in interrupt context.
- *
- * Save the registers of the current task below the interrupt context on
- * its task, then restore the live registers of the next task and set the
- * process stack pointer to the new stack.
- *
- * $r0: pointer to the task to switch from
- * $r1: pointer to the task to switch to
- * $r2: pointer to the stack where the interrupt entry context is saved
- *
- * the structure of the saved context on the stack is :
- * (top to bottom)
- *  sp, lp, fp, r15, r5, r4, r3, r2, r1, r0, r10, r9, r8, r7, r6, ipc, ipsw
- *       interrupt entry frame            <|>
- */
-.global __switch_task
-__switch_task:
-	/* get the (new) highest priority task pointer in r0 */
-	jal next_sched_task
-	movi55 $r3, 0
-	/* pointer to the current task (which are switching from) */
-	lwi.gp  $r1, [ + current_task]
-	/* reset the re-scheduling request */
-	swi.gp  $r3, [ + need_resched]
-	/* Nothing to do: let's return to keep the same task scheduled */
-	beq $r1, $r0, 1f
-	/* save our new scheduled task  */
-	swi.gp  $r0, [ + current_task]
-	/* get the program status word saved at exception entry */
-	mfsr $r4, $IPSW /* to save SP_ADJ bit */
-	/* get the task program counter saved at exception entry */
-	mfsr $r5, $IPC
-	/* get the new scheduled task stack pointer */
-	lw   $r3, [$r0]
-	/* save ipsw, ipc, r6, r7, r8, r9, r10 on the current process stack */
-	smw.adm $r4, [$fp], $r10, 0
-	/* restore ipsw, ipc, r6, r7, r8, r9, r10 from the next stack context */
-	lmw.bim $r4, [$r3], $r10, 0
-	/* set the program status word to restore SP_ADJ bit */
-	mtsr $r4, $IPSW
-	/* set the task program counter to restore at exception exit */
-	mtsr $r5, $IPC
-	/* save the task stack pointer in its context */
-	sw   $fp, [$r1]
-	/* barrier: ensure IPC is taken into account before IRET */
-	dsb
-	/* exception frame pointer for the new task */
-	mov55 $fp, $r3
-1:      /* un-pile the interruption entry context */
-	/* isr exit */
-	jal end_irq_handler
-	/* restore r0-r5 */
-	lmw.bim $r0, [$fp], $r5, 0
-	/* restore r15, fp, lp and sp */
-	lmw.bi $r15, [$fp], $r15, 0xb
-	/* restore PC and PSW */
-	iret
-
-.text
-/**
- * Start the task scheduling.
- *
- * $r0 is a pointer to task_stack_ready, which is set to 1 after
- * the task stack is set up.
- */
-.global __task_start
-__task_start:
-	/*
-	 * Disable global interrupt here to ensure below sequence won't be
-	 * broken. The "iret" instruction of ISR will enable GIE again.
-	 */
-	setgie.d
-	/* area used as thread stack for the first switch */
-	la $r3, scratchpad
-
-	movi55 $r4, 1
-	movi55 $r2, 0    /* syscall 3rd parameter : not an IRQ emulation */
-	movi55 $r1, 0    /* syscall 2nd parameter : re-schedule nothing */
-	movi55 $r0, 0    /* syscall 1st parameter : de-schedule nothing */
-
-	/* put the stack pointer at the top of the stack in scratchpad */
-	addi $sp, $r3, 4 * TASK_SCRATCHPAD_SIZE
-	/* we are ready to re-schedule */
-	swi.gp  $r4, [ + need_resched]
-	swi.gp  $r4, [ + start_called]
-
-	/* trigger scheduling to execute the task with the highest priority */
-	syscall 0
-	/* we should never return here: set code to EC_ERROR_UNKNOWN */
-	movi55 $r0, 0x1
-	ret5   $lp
-
diff --git a/core/nds32/task.c b/core/nds32/task.c
deleted file mode 100644
index edacb7975e..0000000000
--- a/core/nds32/task.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Task scheduling / events module for Chrome EC operating system */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "cpu.h"
-#include "hwtimer_chip.h"
-#include "intc.h"
-#include "irq_chip.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-typedef union {
-	struct {
-		/*
-		 * Note that sp must be the first element in the task struct
-		 * for __switchto() to work.
-		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		uint32_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
-	};
-} task_;
-
-/* Value to store in unused stack */
-#define STACK_UNUSED_VALUE 0xdeadd00d
-
-/* declare task routine prototypes */
-#define TASK(n, r, d, s) void r(void *);
-void __idle(void);
-CONFIG_TASK_LIST
-CONFIG_TEST_TASK_LIST
-#undef TASK
-
-/* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
-#undef TASK
-
-#ifdef CONFIG_TASK_PROFILING
-static int task_will_switch;
-static uint32_t exc_sub_time;
-static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
-#endif
-
-extern int __task_start(void);
-
-#ifndef CONFIG_LOW_POWER_IDLE
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	cprints(CC_TASK, "idle task started");
-
-	while (1) {
-#ifdef CHIP_FAMILY_IT83XX
-		/* doze mode */
-		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
-#endif
-		asm volatile ("dsb");
-		/*
-		 * Wait for the next irq event.  This stops the CPU clock
-		 * (sleep / deep sleep, depending on chip config).
-		 */
-		asm("standby wake_grant");
-	}
-}
-#endif /* !CONFIG_LOW_POWER_IDLE */
-
-static void task_exit_trap(void)
-{
-	int i = task_get_current();
-	cprints(CC_TASK, "Task %d (%s) exited!", i, task_names[i]);
-	/* Exited tasks simply sleep forever */
-	while (1)
-		task_wait_event(-1);
-}
-
-/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
-static const struct {
-	uint32_t r0;
-	uint32_t pc;
-	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
-#undef TASK
-
-/* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT];
-/* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
-BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-
-
-/* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
-
-#undef TASK
-
-/* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
-
-task_ *current_task = (task_ *)scratchpad;
-
-/*
- * Should IRQs chain to svc_handler()?  This should be set if either of the
- * following is true:
- *
- * 1) Task scheduling has started, and task profiling is enabled.  Task
- * profiling does its tracking in svc_handler().
- *
- * 2) An event was set by an interrupt; this could result in a higher-priority
- * task unblocking.  After checking for a task switch, svc_handler() will clear
- * the flag (unless profiling is also enabled; then the flag remains set).
- */
-int need_resched;
-
-/*
- * Bitmap of all tasks ready to be run.
- *
- * Start off with only the hooks task marked as ready such that all the modules
- * can do their init within a task switching context.  The hooks task will then
- * make a call to enable all tasks.
- */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
-/*
- * Initially allow only the HOOKS and IDLE task to run, regardless of ready
- * status, in order for HOOK_INIT to complete before other tasks.
- * task_enable_all_tasks() will open the flood gates.
- */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-
-int start_called;  /* Has task swapping started */
-
-/* interrupt number of sw interrupt */
-static int sw_int_num;
-
-/*
- * This variable is used to save link pointer register,
- * and it is updated at the beginning of each ISR.
- */
-uint32_t ilp;
-
-/* This variable is used to save link pointer register at EC reset. */
-uint32_t ec_reset_lp;
-
-static inline task_ *__task_id_to_ptr(task_id_t id)
-{
-	return tasks + id;
-}
-
-/*
- * We use INT_MASK to enable (interrupt_enable)/
- * disable (interrupt_disable) all maskable interrupts.
- * And, EC modules share HW2 ~ HW15 interrupts. If corresponding
- * bit of INT_MASK is set, it will never be cleared
- * (see chip_disable_irq()). To enable/disable individual
- * interrupt of EC module, we can use corresponding EXT_IERx registers.
- *
- * ------------     -----------
- * |          |     | ------- |
- * |EC modules|     | | HW2 | |
- * |          |     | ------- |
- * | INT 0    |     | ------- |    -------    -------
- * | ~        | --> | | HW3 | | -> | GIE | -> | CPU |
- * | INT 167  |     | ------- |    -------    -------
- * |          |     |   ...   |       |
- * |          |     |   ...   |        - clear by HW while
- * |          |     | ------- |          interrupt occur and
- * |          |     | | HW15| |          restore from IPSW after
- * |          |     | ------- |          instruction "iret".
- * | EXT_IERx |     | INT_MASK|
- * ------------     -----------
- */
-void __ram_code interrupt_disable(void)
-{
-	/* Mask all interrupts, only keep division by zero exception */
-	uint32_t val = BIT(30);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-	asm volatile ("dsb");
-}
-
-void __ram_code interrupt_enable(void)
-{
-	/* Enable HW2 ~ HW15 and division by zero exception interrupts */
-	uint32_t val = (BIT(30) | 0xFFFC);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-}
-
-inline int is_interrupt_enabled(void)
-{
-	uint32_t val = 0;
-
-	asm volatile ("mfsr %0, $INT_MASK" : "=r"(val));
-
-	/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
-	return !!(val & 0xFFFC);
-}
-
-inline int in_interrupt_context(void)
-{
-	/* check INTL (Interrupt Stack Level) bits */
-	return get_psw() & PSW_INTL_MASK;
-}
-
-task_id_t task_get_current(void)
-{
-#ifdef CONFIG_DEBUG_BRINGUP
-	/* If we haven't done a context switch then our task ID isn't valid */
-	ASSERT(current_task != (task_ *)scratchpad);
-#endif
-	/* return invalid task id if task scheduling is not yet start */
-	return start_called ? (current_task - tasks) : TASK_ID_INVALID;
-}
-
-uint32_t *task_get_event_bitmap(task_id_t tskid)
-{
-	task_ *tsk = __task_id_to_ptr(tskid);
-	return &tsk->events;
-}
-
-int task_start_called(void)
-{
-	return start_called;
-}
-
-/**
- * Scheduling system call
- *
- * Also includes emulation of software triggering interrupt vector
- */
-void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
-{
-	/* are we emulating an interrupt ? */
-	if (swirq) {
-		void (*handler)(void) = __irqhandler[swirq + 1];
-		/* adjust IPC to return *after* the syscall instruction */
-		set_ipc(get_ipc() + 4);
-		/* call the regular IRQ handler */
-		handler();
-		sw_int_num = 0;
-		return;
-	}
-
-	if (desched && !current_task->events) {
-		/*
-		 * Remove our own ready bit (current - tasks is same as
-		 * task_get_current())
-		 */
-		tasks_ready &= ~(1 << (current_task - tasks));
-	}
-	tasks_ready |= 1 << resched;
-
-	/* trigger a re-scheduling on exit */
-	need_resched = 1;
-
-#ifdef CONFIG_TASK_PROFILING
-	svc_calls++;
-#endif
-
-	/* adjust IPC to return *after* the syscall instruction */
-	set_ipc(get_ipc() + 4);
-}
-
-task_ *next_sched_task(void)
-{
-	task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
-
-#ifdef CONFIG_TASK_PROFILING
-	if (current_task != new_task) {
-		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
-		task_will_switch = 1;
-	}
-#endif
-
-#ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current_task->stack != STACK_UNUSED_VALUE) {
-		int i = task_get_current();
-
-		panic_printf("\n\nStack overflow in %s task!\n", task_names[i]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, i);
-#endif
-	}
-#endif
-
-	return new_task;
-}
-
-static inline void __schedule(int desched, int resched, int swirq)
-{
-	register int p0 asm("$r0") = desched;
-	register int p1 asm("$r1") = resched;
-	register int p2 asm("$r2") = swirq;
-
-	asm("syscall 0" : : "r"(p0), "r"(p1), "r"(p2));
-}
-
-void update_exc_start_time(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	exc_start_time = get_time().le.lo;
-#endif
-}
-
-/* Interrupt number of EC modules */
-volatile int ec_int;
-
-void __ram_code start_irq_handler(void)
-{
-	/* save r0, r1, and r2 for syscall */
-	asm volatile ("smw.adm $r0, [$sp], $r2, 0");
-	/* If this is a SW interrupt */
-	if (get_itype() & 8)
-		ec_int = sw_int_num;
-	else
-		ec_int = chip_get_ec_int();
-
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CHIP_FAMILY_IT83XX)
-	clock_sleep_mode_wakeup_isr();
-#endif
-#ifdef CONFIG_TASK_PROFILING
-	update_exc_start_time();
-
-	/*
-	 * Track IRQ distribution.  No need for atomic add, because an IRQ
-	 * can't pre-empt itself.
-	 */
-	if ((ec_int > 0) && (ec_int < ARRAY_SIZE(irq_dist)))
-		irq_dist[ec_int]++;
-#endif
-	/* restore r0, r1, and r2 */
-	asm volatile ("lmw.bim $r0, [$sp], $r2, 0");
-}
-
-void end_irq_handler(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	uint32_t t, p;
-	/*
-	 * save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp
-	 * while interrupt exit.
-	 */
-	asm volatile ("smw.adm $r0, [$sp], $r0, 8");
-
-	t = get_time().le.lo;
-	p = t - exc_start_time;
-
-	exc_total_time += p;
-	exc_sub_time += p;
-	if (task_will_switch) {
-		task_will_switch = 0;
-		exc_sub_time = 0;
-		exc_end_time = t;
-		task_switches++;
-	}
-
-	/* restore r0 and fp */
-	asm volatile ("lmw.bim $r0, [$sp], $r0, 8");
-#endif
-}
-
-static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
-{
-	task_ *tsk = current_task;
-	task_id_t me = tsk - tasks;
-	uint32_t evt;
-	int ret;
-
-	ASSERT(!in_interrupt_context());
-
-	if (timeout_us > 0) {
-		timestamp_t deadline = get_time();
-		deadline.val += timeout_us;
-		ret = timer_arm(deadline, me);
-		ASSERT(ret == EC_SUCCESS);
-	}
-	while (!(evt = atomic_clear(&tsk->events))) {
-		/* Remove ourself and get the next task in the scheduler */
-		__schedule(1, resched, 0);
-		resched = TASK_ID_IDLE;
-	}
-	if (timeout_us > 0) {
-		timer_cancel(me);
-		/* Ensure timer event is clear, we no longer care about it */
-		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
-	}
-	return evt;
-}
-
-uint32_t __ram_code task_set_event(task_id_t tskid, uint32_t event)
-{
-	task_ *receiver = __task_id_to_ptr(tskid);
-	ASSERT(receiver);
-
-	/* Set the event bit in the receiver message bitmap */
-	atomic_or(&receiver->events, event);
-
-	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context()) {
-		/* The receiver might run again */
-		atomic_or(&tasks_ready, 1 << tskid);
-		if (start_called)
-			need_resched = 1;
-	} else {
-		__schedule(0, tskid, 0);
-	}
-
-	return 0;
-}
-
-uint32_t __ram_code task_wait_event(int timeout_us)
-{
-	return __wait_evt(timeout_us, TASK_ID_IDLE);
-}
-
-uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint64_t deadline = get_time().val + timeout_us;
-	uint32_t events = 0;
-	int time_remaining_us = timeout_us;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(events & event_mask)) {
-		/* Collect events to re-post later */
-		events |= __wait_evt(time_remaining_us, TASK_ID_IDLE);
-
-		time_remaining_us = deadline - get_time().val;
-		if (timeout_us > 0 && time_remaining_us <= 0) {
-			/* Ensure we return a TIMER event if we timeout */
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-	}
-
-	/* Re-post any other events collected */
-	if (events & ~event_mask)
-		atomic_or(&current_task->events, events & ~event_mask);
-
-	return events & event_mask;
-}
-
-uint32_t __ram_code read_clear_int_mask(void)
-{
-	uint32_t int_mask, int_dis = BIT(30);
-
-	asm volatile(
-		"mfsr %0, $INT_MASK\n\t"
-		"mtsr %1, $INT_MASK\n\t"
-		"dsb\n\t"
-		: "=&r"(int_mask)
-		: "r"(int_dis));
-
-	return int_mask;
-}
-
-void __ram_code set_int_mask(uint32_t val)
-{
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-}
-
-static void set_int_priority(uint32_t val)
-{
-	asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
-}
-
-uint32_t get_int_ctrl(void)
-{
-	uint32_t ret;
-
-	asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
-	return ret;
-}
-
-void set_int_ctrl(uint32_t val)
-{
-	asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
-}
-
-void task_enable_all_tasks(void)
-{
-	/* Mark all tasks as ready and able to run. */
-	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
-	/* Reschedule the highest priority task. */
-	__schedule(0, 0, 0);
-}
-
-void task_enable_task(task_id_t tskid)
-{
-	atomic_or(&tasks_enabled, BIT(tskid));
-}
-
-void task_disable_task(task_id_t tskid)
-{
-	atomic_clear_bits(&tasks_enabled, BIT(tskid));
-
-	if (!in_interrupt_context() && tskid == task_get_current())
-		__schedule(0, 0, 0);
-}
-
-void __ram_code task_enable_irq(int irq)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	chip_enable_irq(irq);
-	set_int_mask(int_mask);
-}
-
-void __ram_code task_disable_irq(int irq)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	chip_disable_irq(irq);
-	set_int_mask(int_mask);
-}
-
-void __ram_code task_clear_pending_irq(int irq)
-{
-	chip_clear_pending_irq(irq);
-}
-
-void __ram_code task_trigger_irq(int irq)
-{
-	int cpu_int = chip_trigger_irq(irq);
-
-	if (cpu_int > 0) {
-		sw_int_num = irq;
-		__schedule(0, 0, cpu_int);
-	}
-}
-
-/*
- * Initialize IRQs in the IVIC and set their priorities as defined by the
- * DECLARE_IRQ statements.
- */
-static void ivic_init_irqs(void)
-{
-	/* Get the IRQ priorities section from the linker */
-	int exc_calls = __irqprio_end - __irqprio;
-	int i;
-	uint32_t all_priorities = 0;
-
-	/* chip-specific interrupt controller initialization */
-	chip_init_irqs();
-
-	/*
-	 * bit0 @ INT_CTRL = 0,
-	 * Interrupts still keep programmable priority level.
-	 */
-	set_int_ctrl((get_int_ctrl() & ~BIT(0)));
-
-	/*
-	 * Re-enable global interrupts in case they're disabled.  On a reboot,
-	 * they're already enabled; if we've jumped here from another image,
-	 * they're not.
-	 */
-	interrupt_enable();
-
-	/* Set priorities */
-	for (i = 0; i < exc_calls; i++) {
-		uint8_t irq = __irqprio[i].irq;
-		uint8_t prio = __irqprio[i].priority;
-		all_priorities |= (prio & 0x3)  << (irq * 2);
-	}
-	set_int_priority(all_priorities);
-}
-
-void __ram_code mutex_lock(struct mutex *mtx)
-{
-	uint32_t id = 1 << task_get_current();
-
-	ASSERT(id != TASK_ID_INVALID);
-
-	/* critical section with interrupts off */
-	interrupt_disable();
-	mtx->waiters |= id;
-	while (1) {
-		if (!mtx->lock) { /* we got it ! */
-			mtx->lock = 2;
-			mtx->waiters &= ~id;
-			/* end of critical section : re-enable interrupts */
-			interrupt_enable();
-			return;
-		} else { /* Contention on the mutex */
-			/* end of critical section : re-enable interrupts */
-			interrupt_enable();
-			/* Sleep waiting for our turn */
-			task_wait_event_mask(TASK_EVENT_MUTEX, 0);
-			/* re-enter critical section */
-			interrupt_disable();
-		}
-	}
-}
-
-void __ram_code mutex_unlock(struct mutex *mtx)
-{
-	uint32_t waiters;
-	task_ *tsk = current_task;
-
-	/*
-	 * we need to read to waiters after giving the lock back
-	 * otherwise we might miss a waiter between the two calls.
-	 *
-	 * prevent compiler reordering
-	 */
-	asm volatile(
-		/* give back the lock */
-		"movi %0, #0\n\t"
-		"lwi %1, [%2]\n\t"
-		: "=&r"(mtx->lock), "=&r"(waiters)
-		: "r"(&mtx->waiters));
-
-	while (waiters) {
-		task_id_t id = __fls(waiters);
-		waiters &= ~BIT(id);
-
-		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX);
-	}
-
-	/* Ensure no event is remaining from mutex wake-up */
-	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
-}
-
-void task_print_list(void)
-{
-	int i;
-
-	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
-
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
-		uint32_t *sp;
-
-		int stackused = tasks_init[i].stack_size;
-
-		for (sp = tasks[i].stack;
-		     sp < (uint32_t *)tasks[i].sp && *sp == STACK_UNUSED_VALUE;
-		     sp++)
-			stackused -= sizeof(uint32_t);
-
-		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
-			 stackused, tasks_init[i].stack_size);
-		cflush();
-	}
-}
-
-int command_task_info(int argc, char **argv)
-{
-#ifdef CONFIG_TASK_PROFILING
-	int total = 0;
-	int i;
-#endif
-
-	task_print_list();
-
-#ifdef CONFIG_TASK_PROFILING
-	ccputs("IRQ counts by type:\n");
-	cflush();
-	for (i = 0; i < ARRAY_SIZE(irq_dist); i++) {
-		if (irq_dist[i]) {
-			ccprintf("%4d %8d\n", i, irq_dist[i]);
-			total += irq_dist[i];
-		}
-	}
-
-	ccprintf("Service calls:          %11d\n", svc_calls);
-	ccprintf("Total exceptions:       %11d\n", total + svc_calls);
-	ccprintf("Task switches:          %11d\n", task_switches);
-	ccprintf("Task switching started: %11.6lld s\n", task_start_time);
-	ccprintf("Time in tasks:          %11.6lld s\n",
-		 get_time().val - task_start_time);
-	ccprintf("Time in exceptions:     %11.6lld s\n", exc_total_time);
-#endif
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
-
-static int command_task_ready(int argc, char **argv)
-{
-	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
-	} else {
-		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
-		__schedule(0, 0, 0);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
-			"Print/set ready tasks");
-
-void task_pre_init(void)
-{
-	uint32_t *stack_next = (uint32_t *)task_stacks;
-	int i;
-
-	/* Fill the task memory with initial values */
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		uint32_t *sp;
-		/* Stack size in words */
-		uint32_t ssize = tasks_init[i].stack_size / 4;
-
-		tasks[i].stack = stack_next;
-
-		/*
-		 * Update stack used by first frame: 15 regs + PC + PSW
-		 */
-		sp = stack_next + ssize - 17;
-		tasks[i].sp = (uint32_t)sp;
-
-		/* Initial context on stack (see __switchto()) */
-		sp[7] = tasks_init[i].r0;           /* r0 */
-		sp[15] = (uint32_t)task_exit_trap;  /* lr */
-		sp[1] = tasks_init[i].pc;           /* pc */
-		sp[0] = 0x70009;                    /* psw */
-		sp[16] = (uint32_t)(sp + 17);       /* sp */
-
-		/* Fill unused stack; also used to detect stack overflow. */
-		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
-			*sp = STACK_UNUSED_VALUE;
-
-		stack_next += ssize;
-	}
-
-	/*
-	 * Fill in guard value in scratchpad to prevent stack overflow
-	 * detection failure on the first context switch.  This works because
-	 * the first word in the scratchpad is where the switcher will store
-	 * sp, so it's ok to blow away.
-	 */
-	((task_ *)scratchpad)->stack = (uint32_t *)scratchpad;
-	*(uint32_t *)scratchpad = STACK_UNUSED_VALUE;
-
-	/* Initialize IRQs */
-	ivic_init_irqs();
-}
-
-int task_start(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	task_start_time = get_time().val;
-	exc_end_time = get_time().le.lo;
-#endif
-
-	return __task_start();
-}
diff --git a/core/riscv-rv32i/__builtin.c b/core/riscv-rv32i/__builtin.c
deleted file mode 100644
index 4bf495a011..0000000000
--- a/core/riscv-rv32i/__builtin.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-/*
- * __builtin_ffs:
- * Returns one plus the index of the least significant 1-bit of x,
- * or if x is zero, returns zero.
- */
-int __keep __ffssi2(int x)
-{
-	return 32 - __builtin_clz(x & -x);
-}
diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h
deleted file mode 100644
index e92beb2ca0..0000000000
--- a/core/riscv-rv32i/atomic.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Atomic operations for RISC_V */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include "common.h"
-#include "cpu.h"
-#include "task.h"
-
-typedef int atomic_t;
-typedef atomic_t atomic_val_t;
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_and(addr, ~bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits)
-{
-	return __atomic_fetch_or(addr, bits, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_clear(atomic_t *addr)
-{
-	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_read_add(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_add(addr, value, __ATOMIC_SEQ_CST);
-}
-
-static inline atomic_val_t atomic_read_sub(atomic_t *addr, atomic_val_t value)
-{
-	return __atomic_fetch_sub(addr, value, __ATOMIC_SEQ_CST);
-}
-
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk
deleted file mode 100644
index 34f059e70c..0000000000
--- a/core/riscv-rv32i/build.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-# -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# RISC-V core OS files build
-#
-
-# Select RISC-V bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
-	/opt/coreboot-sdk/bin/riscv64-elf-)
-
-# Enable FPU extension if config option of FPU is enabled.
-_FPU_EXTENSION=$(if $(CONFIG_FPU),f,)
-# CPU specific compilation flags
-CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os
-# RISC-V does not trap division by zero, enable the sanitizer to check those.
-# With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the
-# exact issue, but the added code is as small as it gets.
-CFLAGS_CPU+=-fsanitize=integer-divide-by-zero -fsanitize-undefined-trap-on-error
-LDFLAGS_EXTRA+=-mrelax
-LDFLAGS_EXTRA+=-static-libgcc -lgcc
-
-ifneq ($(CONFIG_LTO),)
-CFLAGS_CPU+=-flto
-LDFLAGS_EXTRA+=-flto
-endif
-
-core-y=cpu.o init.o panic.o task.o switch.o __builtin.o math.o
diff --git a/core/riscv-rv32i/config_core.h b/core/riscv-rv32i/config_core.h
deleted file mode 100644
index fe6135683d..0000000000
--- a/core/riscv-rv32i/config_core.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CORE_H
-#define __CROS_EC_CONFIG_CORE_H
-
-/* Linker binary architecture and format */
-#define BFD_ARCH riscv
-#define BFD_FORMAT "elf32-littleriscv"
-
-/*
- * The hardware doesn't support the risc-v bit manipulation
- * extension (CLZ/CTZ instructions) so let's use the software implementation.
- */
-#define CONFIG_SOFTWARE_CLZ
-#define CONFIG_SOFTWARE_CTZ
-#define CONFIG_SOFTWARE_PANIC
-
-#endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c
deleted file mode 100644
index fd18896846..0000000000
--- a/core/riscv-rv32i/cpu.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Set up the RISC-V core
- */
-
-#include "cpu.h"
-
-void cpu_init(void)
-{
-	/* bit3: Global interrupt enable (M-mode) */
-	asm volatile ("csrsi mstatus, 0x8");
-}
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h
deleted file mode 100644
index e46b893ad6..0000000000
--- a/core/riscv-rv32i/cpu.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for RISC-V cores
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-/*
- * This is the space required by both __irq_isr and __switch_task to store all
- * of the caller and callee registers for each task context before switching.
- */
-#ifdef CONFIG_FPU
-/* additional space to save FP registers (fcsr, ft0-11, fa0-7, fs0-11) */
-#define TASK_SCRATCHPAD_SIZE (62)
-#else
-#define TASK_SCRATCHPAD_SIZE (29)
-#endif
-
-#ifndef __ASSEMBLER__
-#include <stdint.h>
-
-/* write Exception Program Counter register */
-static inline void set_mepc(uint32_t val)
-{
-	asm volatile ("csrw mepc, %0" : : "r"(val));
-}
-
-/* read Exception Program Counter register */
-static inline uint32_t get_mepc(void)
-{
-	uint32_t ret;
-
-	asm volatile ("csrr %0, mepc" : "=r"(ret));
-	return ret;
-}
-
-/* read Trap cause register */
-static inline uint32_t get_mcause(void)
-{
-	uint32_t ret;
-
-	asm volatile ("csrr %0, mcause" : "=r"(ret));
-	return ret;
-}
-
-/* Generic CPU core initialization */
-void cpu_init(void);
-extern uint32_t ec_reset_lp;
-extern uint32_t ira;
-#endif
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S
deleted file mode 100644
index e8963c1b14..0000000000
--- a/core/riscv-rv32i/ec.lds.S
+++ /dev/null
@@ -1,458 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-
-#define STRINGIFY0(name) #name
-#define STRINGIFY(name) STRINGIFY0(name)
-
-#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
-
-#define FW_SIZE_(section) CONFIG_##section##_SIZE
-#define FW_SIZE(section) FW_SIZE_(section)
-
-OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
-OUTPUT_ARCH(BFD_ARCH)
-ENTRY(__reset)
-
-MEMORY
-{
-#if defined(CONFIG_FLASH_PHYSICAL)
-	FLASH (rx) : ORIGIN = FW_OFF(SECTION) - CHIP_ILM_BASE, \
-		     LENGTH = FW_SIZE(SECTION)
-#else
-	IROM (rx) : ORIGIN = CONFIG_ROM_BASE, LENGTH = CONFIG_ROM_SIZE
-#endif
-
-#if defined(CHIP_FAMILY_IT8XXX2)
-	/*
-	 * On IT8XXX2 family, it reserves space for ramcode, h2ram, and
-	 * immu sections.
-	 */
-	IRAM (rw) : ORIGIN = CONFIG_RAM_BASE + CHIP_RAM_SPACE_RESERVED,
-		    LENGTH = CONFIG_RAM_SIZE - CHIP_RAM_SPACE_RESERVED
-	/*
-	 * ILM (Instruction Local Memory).
-	 * We connect ILM to internal flash so we are able to
-	 * boot from the flash.
-	 */
-	ILM (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
-
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
-	H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE
-#endif
-#else
-	IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
-#endif /* CHIP_FAMILY_IT8XXX2 */
-
-#ifdef CONFIG_DRAM_BASE
-	DRAM (rwx) : ORIGIN = CONFIG_DRAM_BASE, LENGTH = CONFIG_DRAM_SIZE
-#endif
-}
-
-SECTIONS
-{
-	.text : {
-#if defined(CHIP_FAMILY_IT8XXX2)
-		/*
-		 * We put "__flash_dma_start" at the beginning of the
-		 * text section to avoid gap.
-		 */
-		__flash_dma_start = .;
-		ASSERT((__flash_dma_start == 0),
-		       "__flash_dma_start has to be 4k-byte aligned");
-#endif
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vecttable))
-		. = ALIGN(4);
-		__image_data_offset = .;
-		KEEP(*(.rodata.ver))
-
-		. = ALIGN(4);
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vectirq))
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text))
-#if defined(CHIP_FAMILY_IT8XXX2)
-		KEEP(*(.flash_direct_map))
-		. = ALIGN(16);
-		KEEP(*(.ram_code))
-
-		__flash_dma_size = . - __flash_dma_start;
-		ASSERT((__flash_dma_size < IT83XX_ILM_BLOCK_SIZE),
-		       "__flash_dma_size < IT83XX_ILM_BLOCK_SIZE");
-		. = ALIGN(IT83XX_ILM_BLOCK_SIZE);
-		__ilm0_ram_code = .;
-		OUTDIR/chip/it83xx/i2c.o (.text*)
-		OUTDIR/chip/it83xx/i2c.o (.rodata)
-		OUTDIR/chip/it83xx/hwtimer.o (.text*)
-		OUTDIR/chip/it83xx/hwtimer.o (.rodata)
-		. = ALIGN(16);
-#endif
-		*(.text*)
-		. = ALIGN(4);
-#if defined(CONFIG_FLASH_PHYSICAL)
-#	if defined(CHIP_FAMILY_IT8XXX2)
-	} > ILM AT > FLASH
-#	else
-	} > FLASH
-#	endif
-#else
-	} > IROM
-#endif /* CONFIG_FLASH_PHYSICAL */
-
-	. = ALIGN(4);
-	.rodata : {
-		/* Symbols defined here are declared in link_defs.h */
-		__irqprio = .;
-		KEEP(*(.rodata.irqprio))
-		__irqprio_end = .;
-
-		. = ALIGN(4);
-		__irqhandler = .;
-		KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.rodata.vecthandlers))
-
-		. = ALIGN(4);
-		__cmds = .;
-		KEEP(*(SORT(.rodata.cmds*)))
-		__cmds_end = .;
-
-		. = ALIGN(4);
-		__hcmds = .;
-		KEEP(*(SORT(.rodata.hcmds*)))
-		__hcmds_end = .;
-
-		. = ALIGN(4);
-		__mkbp_evt_srcs = .;
-		KEEP(*(.rodata.evtsrcs))
-		__mkbp_evt_srcs_end = .;
-
-		. = ALIGN(4);
-		__hooks_init = .;
-		KEEP(*(.rodata.HOOK_INIT))
-		__hooks_init_end = .;
-
-		__hooks_pre_freq_change = .;
-		KEEP(*(.rodata.HOOK_PRE_FREQ_CHANGE))
-		__hooks_pre_freq_change_end = .;
-
-		__hooks_freq_change = .;
-		KEEP(*(.rodata.HOOK_FREQ_CHANGE))
-		__hooks_freq_change_end = .;
-
-		__hooks_sysjump = .;
-		KEEP(*(.rodata.HOOK_SYSJUMP))
-		__hooks_sysjump_end = .;
-
-		__hooks_chipset_pre_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_PRE_INIT))
-		__hooks_chipset_pre_init_end = .;
-
-		__hooks_chipset_startup = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_STARTUP))
-		__hooks_chipset_startup_end = .;
-
-		__hooks_chipset_resume = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME))
-		__hooks_chipset_resume_end = .;
-
-		__hooks_chipset_suspend = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND))
-		__hooks_chipset_suspend_end = .;
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		__hooks_chipset_resume_init = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESUME_INIT))
-		__hooks_chipset_resume_init_end = .;
-
-		__hooks_chipset_suspend_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SUSPEND_COMPLETE))
-		__hooks_chipset_suspend_complete_end = .;
-#endif
-
-		__hooks_chipset_shutdown = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN))
-		__hooks_chipset_shutdown_end = .;
-
-		__hooks_chipset_shutdown_complete = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_SHUTDOWN_COMPLETE))
-		__hooks_chipset_shutdown_complete_end = .;
-
-		__hooks_chipset_hard_off = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_HARD_OFF))
-		__hooks_chipset_hard_off_end = .;
-
-		__hooks_chipset_reset = .;
-		KEEP(*(.rodata.HOOK_CHIPSET_RESET))
-		__hooks_chipset_reset_end = .;
-
-		__hooks_ac_change = .;
-		KEEP(*(.rodata.HOOK_AC_CHANGE))
-		__hooks_ac_change_end = .;
-
-		__hooks_lid_change = .;
-		KEEP(*(.rodata.HOOK_LID_CHANGE))
-		__hooks_lid_change_end = .;
-
-		__hooks_tablet_mode_change = .;
-		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
-		__hooks_tablet_mode_change_end = .;
-
-		__hooks_base_attached_change = .;
-		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
-		__hooks_base_attached_change_end = .;
-
-		__hooks_pwrbtn_change = .;
-		KEEP(*(.rodata.HOOK_POWER_BUTTON_CHANGE))
-		__hooks_pwrbtn_change_end = .;
-
-		__hooks_battery_soc_change = .;
-		KEEP(*(.rodata.HOOK_BATTERY_SOC_CHANGE))
-		__hooks_battery_soc_change_end = .;
-
-#ifdef CONFIG_USB_SUSPEND
-		__hooks_usb_change = .;
-		KEEP(*(.rodata.HOOK_USB_PM_CHANGE))
-		__hooks_usb_change_end = .;
-#endif
-
-		__hooks_tick = .;
-		KEEP(*(.rodata.HOOK_TICK))
-		__hooks_tick_end = .;
-
-		__hooks_second = .;
-		KEEP(*(.rodata.HOOK_SECOND))
-		__hooks_second_end = .;
-
-		__hooks_usb_pd_disconnect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_DISCONNECT))
-		__hooks_usb_pd_disconnect_end = .;
-
-		__hooks_usb_pd_connect = .;
-		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
-		__hooks_usb_pd_connect_end = .;
-
-		__deferred_funcs = .;
-		KEEP(*(.rodata.deferred))
-		__deferred_funcs_end = .;
-
-		. = ALIGN(4);
-		*(.rodata*)
-
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-	ASSERT(0, "CONFIG_CHIP_INIT_ROM_REGION not supported by linker script")
-#endif /* CONFIG_CHIP_INIT_ROM_REGION */
-		/*
-		 * This linker file does not yet support a separate ROM resident
-		 * section. Ensure the corresponding data objects are linked
-		 * into the .rodata section.
-		 */
-		. = ALIGN(4);
-		__init_rom_start = .;
-		*(.init.rom)
-		__init_rom_end = .;
-
-		. = ALIGN(4);
-		*(.srodata*)
-#if defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS)
-		. = ALIGN(64);
-		KEEP(*(.google))
-#endif
-		. = ALIGN(4);
-#if defined(CONFIG_FLASH_PHYSICAL)
-#	if defined(CHIP_FAMILY_IT8XXX2)
-	} > ILM AT > FLASH
-#	else
-	} > FLASH
-#	endif
-#else
-	} > IROM
-#endif /* CONFIG_FLASH_PHYSICAL */
-
-	__data_lma_start = .;
-
-#ifdef CONFIG_PRESERVE_LOGS
-	.preserve_logs(NOLOAD) : {
-		/*
-		 * The address of the preserved logs is fixed at the beginning
-		 * of memory.
-		 */
-		. = ALIGN(8);
-		__preserved_logs_start = .;
-		*(SORT(.preserved_logs.*))
-		. = ALIGN(8);
-		__preserved_logs_end = .;
-	} > IRAM
-	__preserved_logs_size = __preserved_logs_end - __preserved_logs_start;
-#ifdef CONFIG_IT83XX_HARD_RESET_BY_GPG1
-	ASSERT(__preserved_logs_size <= CHIP_FLASH_PRESERVE_LOGS_SIZE,
-	       "Not enough flash space to save EC logs.")
-#endif
-#endif /* CONFIG_PRESERVE_LOGS */
-
-	.data : {
-		. = ALIGN(4);
-		__data_start = .;
-		*(.data)
-		*(.sdata)
-		. = ALIGN(4);
-		__data_end = .;
-#if defined(CONFIG_FLASH_PHYSICAL)
-	} > IRAM AT > FLASH
-#else
-	} > IRAM AT > IROM
-#endif
-
-	.bss : {
-		/* Stacks must be 128-bit aligned */
-		. = ALIGN(16);
-		__bss_start = .;
-		*(.bss.tasks)
-		. = ALIGN(16);
-		*(.bss.system_stack)
-		. = ALIGN(16);
-		*(.bss.task_scratchpad)
-		. = ALIGN(16);
-		__global_pointer$ = .;
-		*(.sbss)
-		. = ALIGN(4);
-		/* Rest of .bss takes care of its own alignment */
-		*(.bss)
-		*(.bss.slow)
-
-		/*
-		 * Reserve space for deferred function firing times.
-		 * Each time is a uint64_t, each func is a 32-bit pointer,
-		 * thus the scaling factor of two.
-		 */
-		. = ALIGN(8);
-		__deferred_until = .;
-		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
-		__deferred_until_end = .;
-
-		. = ALIGN(4);
-		__bss_end = .;
-
-		/*
-		 * Shared memory buffer must be at the end of preallocated RAM,
-		 * so it can expand to use all the remaining RAM.
-		 */
-		__shared_mem_buf = .;
-	} > IRAM
-
-	ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <=
-	       (CONFIG_RAM_BASE + CONFIG_RAM_SIZE),
-	       "Not enough space for shared memory.")
-
-	__ram_free = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE) -
-		     (__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE);
-
-	/*
-	 * __flash_used is used in flash free calculations by the makefile.
-	 * __image_size is stored in the struct image_data header and used
-	 * in hash calcuations.
-	 */
-#if defined(CHIP_FAMILY_IT8XXX2)
-	__flash_used = LOADADDR(.data) + SIZEOF(.data) + \
-		       CHIP_ILM_BASE - FW_OFF(SECTION);
-#else
-	__flash_used = LOADADDR(.data) + SIZEOF(.data) - FW_OFF(SECTION);
-#endif
-	__image_size = __flash_used;
-
-#ifdef CONFIG_FLASH_CROS
-        /*
-         * These linker labels are just for analysis and not used in the code.
-         */
-	__config_flash_size = CONFIG_FLASH_SIZE_BYTES;
-	__config_ro_size = CONFIG_RO_SIZE;
-	__config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE;
-	__config_rw_size = CONFIG_RW_SIZE;
-	__config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
-#endif
-
-#if defined(CHIP_FAMILY_IT8XXX2)
-#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL)
-	.h2ram (NOLOAD) : {
-		. += CONFIG_H2RAM_HOST_LPC_IO_BASE;
-		*(.h2ram.pool.hostcmd)
-		. = ALIGN(256);
-		*(.h2ram.pool.acpiec)
-#ifdef CONFIG_I2C_PERIPHERAL
-		. = ALIGN(256);
-		*(.h2ram.pool.i2cslv)
-#endif
-		__h2ram_end = .;
-	} > H2RAM
-
-	ASSERT((__h2ram_end) <= (CONFIG_H2RAM_BASE + CONFIG_H2RAM_SIZE),
-	       "Not enough space for h2ram section.")
-#endif
-#endif /* CHIP_FAMILY_IT8XXX2 */
-
-#ifdef CONFIG_DRAM_BASE
-	/*
-	 * Sections in DRAM region are constructed as like in non-DRAM regions:
-	 * .dram.data LMA is for preserving initialized data across resets.
-	 * The only difference is that they are all in the DRAM region:
-	 * .dram.text     | LOAD
-	 * .dram.rodata   | LOAD
-	 * .dram.data LMA | LOAD
-	 * .dram.data VMA |
-	 * .dram.bss      | NOLOAD
-	 */
-
-	.dram.text : {
-		. = ALIGN(4);
-		KEEP(*(SORT(.dram.text.keep.*)))
-		*(SORT(.dram.text.*))
-		. = ALIGN(4);
-	} > DRAM
-
-	.dram.rodata : {
-		. = ALIGN(4);
-		KEEP(*(SORT(.dram.rodata.keep.*)))
-		*(SORT(.dram.rodata.*))
-		. = ALIGN(4);
-	} > DRAM
-
-	__dram_data_lma_start = ADDR(.dram.rodata) + SIZEOF(.dram.rodata);
-
-	/* Place .dram.data LMA in between .dram.rodata and .dram.data VMA. */
-	.dram.data __dram_data_lma_start +
-		(__dram_data_end - __dram_data_start) : {
-		. = ALIGN(4);
-		__dram_data_start = .;
-		*(.dram.data*)
-		. = ALIGN(4);
-		__dram_data_end = .;
-
-	/*
-	 * Normally, '> DRAM AT > DRAM' should be the same as '> DRAM',
-	 * and they  will be at the same address. However, if the address
-	 * of VMA specified, LMA and VMA might have different addresses:
-	 * '> DRAM' places VMA at the address where section declaration
-	 * specified.
-	 * 'AT > DRAM' places LMA at the location counter's address.
-	 */
-	} > DRAM AT > DRAM
-
-	/*
-	 * ld assigns correct attribute for .bss, but not for other .*.bss,
-	 * we need an explicltly NOLOAD.
-	 */
-	.dram.bss(NOLOAD) : {
-		. = ALIGN(4);
-		__dram_bss_start = .;
-		*(SORT(.dram.bss*))
-		. = ALIGN(4);
-		__dram_bss_end = .;
-	} > DRAM
-#endif /* CONFIG_DRAM_BASE */
-
-#if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH_CROS))
-	/DISCARD/ : { *(.google) }
-#endif
-
-	/DISCARD/ : { *(.ARM.*) }
-}
diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h
deleted file mode 100644
index 25d83f228f..0000000000
--- a/core/riscv-rv32i/include/fpu.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Math utility functions for RISC-V */
-
-#ifndef __CROS_EC_FPU_H
-#define __CROS_EC_FPU_H
-
-float sqrtf(float x);
-
-#endif  /* __CROS_EC_FPU_H */
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S
deleted file mode 100644
index 5715478356..0000000000
--- a/core/riscv-rv32i/init.S
+++ /dev/null
@@ -1,454 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * RISC-V CPU initialization
- */
-
-#include "config.h"
-
-.macro vector name
-.set \name\()_handler, unhandled_ec_irq
-.weak \name\()_handler
-j __entry_\()\name
-.pushsection .text.vectirq
-.global __entry_\()\name
-__entry_\()\name:
-        /* C routine handler */
-        j \name\()_handler
-.popsection
-.pushsection .rodata.vecthandlers
-.long \name\()_handler
-.popsection
-.endm
-
-.section .text.vecttable
-.align 2
-__startup:
-        j __reset       /* reset */
-__irq:
-        j __irq_isr     /* interrupts / exceptions */
-
-.align 2
-__ec_intc:
-        vector irq_0    /* INT GROUP  0 */
-        vector irq_1    /* INT GROUP  1 */
-        vector irq_2    /* INT GROUP  2 */
-        vector irq_3    /* INT GROUP  3 */
-        vector irq_4    /* INT GROUP  4 */
-        vector irq_5    /* INT GROUP  5 */
-        vector irq_6    /* INT GROUP  6 */
-        vector irq_7    /* INT GROUP  7 */
-        vector irq_8    /* INT GROUP  8 */
-        vector irq_9    /* INT GROUP  9 */
-        vector irq_10   /* INT GROUP 10 */
-        vector irq_11   /* INT GROUP 11 */
-        vector irq_12   /* INT GROUP 12 */
-        vector irq_13   /* INT GROUP 13 */
-        vector irq_14   /* INT GROUP 14 */
-        vector irq_15   /* INT GROUP 15 */
-        vector syscall  /* system call (emulate INT GROUP 16) */
-
-#ifdef CHIP_FAMILY_IT8XXX2
-/*
- * E-flash signature used to enable specific function after power-on reset.
- * (HW mechanism)
- * The content of 16-bytes must be the following and at offset 0x80 of binary.
- * ----------------------------------------------------------------------------
- * 1st 2nd 3rd 4th 5th 6th   7th    8th  9th 10th 11th 12th 13th 14th 15th 16th
- * ----------------------------------------------------------------------------
- * A5h A5h A5h A5h A5h A5h [host] [flag] 85h  12h  5Ah  5Ah  AAh  AAh  55h  55h
- * ----------------------------------------------------------------------------
- * [host]: A4h = enable eSPI, A5h = enable LPC
- * [flag]:
- * bit7: it must be 1b.
- * bit6: it must be 0b.
- * bit5: it must be 1b.
- * bit4: 1b = 32.768KHz is from the internal clock generator.
- * bit3: it must be 0b.
- * bit2: it must be 1b.
- * bit1: it must be 0b.
- * bit0: it must be 0b.
- */
-.org 0x80
-.balign 16
-.global eflash_sig
-eflash_sig:
-.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
-.byte 0xA4 /* eSPI */
-#else
-.byte 0xA5 /* LPC */
-#endif
-.byte 0xB4 /* flag of signature */
-.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
-/* flags: internal oscillator + implicit location */
-#endif /* CHIP_FAMILY_IT8XXX2 */
-
-
-.align 2
-.section .text.vectirq
-__irq_isr:
-        /* save t2 to scratch register */
-        csrw mscratch, t2
-        /* save registers (sp, ra, t0, and t1) state at exception entry */
-        la t2, excep_entry_saved_regs
-        sw sp, 0*4(t2)
-        sw ra, 1*4(t2)
-        sw t0, 2*4(t2)
-        sw t1, 3*4(t2)
-        /* store return address register */
-        la t2, ira
-        sw ra, 0(t2)
-        /* restore t2 */
-        csrr t2, mscratch
-        /* save ra, a0-7, t0-t6 (high memory address to low) */
-        sw t6, -16*4(sp)
-        sw t5, -15*4(sp)
-        sw t4, -14*4(sp)
-        sw t3, -13*4(sp)
-        sw t2, -12*4(sp)
-        sw t1, -11*4(sp)
-        sw t0, -10*4(sp)
-        sw a7, -9*4(sp)
-        sw a6, -8*4(sp)
-        sw a5, -7*4(sp)
-        sw a4, -6*4(sp)
-        sw a3, -5*4(sp)
-        sw a2, -4*4(sp)
-        sw a1, -3*4(sp)
-        /* Don't change index of ra and a0 (see task_pre_init()) */
-        sw a0, -2*4(sp)
-        sw ra, -1*4(sp)
-#ifdef CONFIG_FPU
-        /* save ft0-11, fa0-7, and fcsr. */
-        csrr t0, fcsr
-        sw t0,    -37*4(sp)
-        fsw fa7,  -36*4(sp)
-        fsw fa6,  -35*4(sp)
-        fsw fa5,  -34*4(sp)
-        fsw fa4,  -33*4(sp)
-        fsw fa3,  -32*4(sp)
-        fsw fa2,  -31*4(sp)
-        fsw fa1,  -30*4(sp)
-        fsw fa0,  -29*4(sp)
-        fsw ft11, -28*4(sp)
-        fsw ft10, -27*4(sp)
-        fsw ft9,  -26*4(sp)
-        fsw ft8,  -25*4(sp)
-        fsw ft7,  -24*4(sp)
-        fsw ft6,  -23*4(sp)
-        fsw ft5,  -22*4(sp)
-        fsw ft4,  -21*4(sp)
-        fsw ft3,  -20*4(sp)
-        fsw ft2,  -19*4(sp)
-        fsw ft1,  -18*4(sp)
-        fsw ft0,  -17*4(sp)
-        /*
-         * Note: we never execute on this stack frame, so it does not need to
-         * be 16-byte aligned.
-         */
-        addi sp, sp, -37*4
-#else
-        /*
-         * Note: we never execute on this stack frame, so it does not need to
-         * be 16-byte aligned.
-         */
-        addi sp, sp, -16*4
-#endif
-        /* Save sp to scratch register */
-        csrw mscratch, sp
-        /* Load top of system stack address into t0 for comparison */
-        la t0, stack_end
-        /*
-         * Switch to system stack (which is in lower memory than task stack)
-         * if we are not already operating with the system stack
-         */
-        bltu sp, t0, __sp_16byte_aligned
-        mv sp, t0
-__sp_16byte_aligned:
-	/* in_interrupt = 1 */
-	li t0, 1
-	la t1, in_interrupt
-        sb t0, 0(t1)
-        /*
-         * This ensures sp is 16-byte aligned. This only applies to when there
-         * is an interrupt before tasks start. Otherwise stack_end is already
-         * 16-byte aligned.
-         */
-        andi sp, sp, -16
-        /* read exception cause */
-        csrr t0, mcause
-        /* isolate exception cause */
-        andi t1, t0, 0x1f
-        /* mcause = 11: external interrupt or environment call from M-mode */
-        addi t1, t1, -11
-        beqz t1, __irq_handler
-        /* branch if this is an exceptoin (the interrupt bit of mcause is 0) */
-        bgez t0, excep_handler
-        /* This interrupt is unhandled */
-        j unhandled_interrupt
-__irq_handler:
-        /* save a0, a1, and a2 for syscall */
-        addi sp, sp, -4*3
-        sw a0, 0(sp)
-        sw a1, 1*4(sp)
-        sw a2, 2*4(sp)
-        jal start_irq_handler
-        /* a0 = -1 if it cannot find the corresponding interrupt source */
-        bltz a0, unhandled_interrupt
-        /* restore a0, a1, and a2 */
-        lw a0, 0(sp)
-        lw a1, 1*4(sp)
-        lw a2, 2*4(sp)
-        addi sp, sp, 4*3
-        /* get EC interrupt group 0-15 or 16:ecall */
-        la t0, ec_int_group
-        /* get corresponding isr */
-        lw t1, 0(t0)
-        slli t1, t1, 2
-        la t0, __ec_intc
-        add t0, t0, t1
-        /* handle irq */
-        jalr t0
-        /* check whether we need to change the scheduled task */
-        la t0, need_resched
-        lw t1, 0(t0)
-        bnez t1, __switch_task
-.global __irq_exit
-__irq_exit:
-        jal end_irq_handler
-	/* in_interrupt = 0 */
-	la t0, in_interrupt
-	sb zero, 0(t0)
-        /* restore sp from scratch register */
-        csrr sp, mscratch
-#ifdef CONFIG_FPU
-        addi sp, sp, 37*4
-        /* restore ft0-11, fa0-7, and fcsr. */
-        lw t0,    -37*4(sp)
-        csrw fcsr, t0
-        flw fa7,  -36*4(sp)
-        flw fa6,  -35*4(sp)
-        flw fa5,  -34*4(sp)
-        flw fa4,  -33*4(sp)
-        flw fa3,  -32*4(sp)
-        flw fa2,  -31*4(sp)
-        flw fa1,  -30*4(sp)
-        flw fa0,  -29*4(sp)
-        flw ft11, -28*4(sp)
-        flw ft10, -27*4(sp)
-        flw ft9,  -26*4(sp)
-        flw ft8,  -25*4(sp)
-        flw ft7,  -24*4(sp)
-        flw ft6,  -23*4(sp)
-        flw ft5,  -22*4(sp)
-        flw ft4,  -21*4(sp)
-        flw ft3,  -20*4(sp)
-        flw ft2,  -19*4(sp)
-        flw ft1,  -18*4(sp)
-        flw ft0,  -17*4(sp)
-#else
-        addi sp, sp, 16*4
-#endif
-        /* restore ra, a0-a7, t0-t6 */
-        lw t6, -16*4(sp)
-        lw t5, -15*4(sp)
-        lw t4, -14*4(sp)
-        lw t3, -13*4(sp)
-        lw t2, -12*4(sp)
-        lw t1, -11*4(sp)
-        lw t0, -10*4(sp)
-        lw a7, -9*4(sp)
-        lw a6, -8*4(sp)
-        lw a5, -7*4(sp)
-        lw a4, -6*4(sp)
-        lw a3, -5*4(sp)
-        lw a2, -4*4(sp)
-        lw a1, -3*4(sp)
-        lw a0, -2*4(sp)
-        lw ra, -1*4(sp)
-        mret
-
-.text
-.global __reset
-__reset:
-        /* disable interrupts */
-        csrw mie, zero
-.option push
-.option norelax
-        /* GP register is used to access .data and .bss (address +/- 2048) */
-        la gp, __global_pointer$
-.option pop
-        /* Set system stack pointer. */
-        la sp, stack_end
-#ifdef CONFIG_FPU
-        li t0, 0x6000
-        csrw mstatus, t0
-        csrw fcsr, zero
-#else
-        csrw mstatus, zero
-#endif
-        /*
-         * move content of return address(ra) into t5 and then store the content
-         * into variable "ec_reset_lp" later after memory initialization.
-         */
-        mv t5, ra
-        /* Clear the link register */
-        li ra, 0
-        /* Clear the thread pointer register */
-        li tp, 0
-        /* set machine trap-handler base address */
-        la t0, __irq
-        csrw mtvec, t0
-        /* reset scratch register */
-        csrw mscratch, zero
-        /* The M-mode handles interrupt/exception */
-        csrwi mideleg, 0
-        csrwi medeleg, 0
-#if defined(IT83XX_CHIP_FLASH_SIZE_1MB) && defined(CHIP_FAMILY_IT8XXX2)
-        /* ILM size is 1M bytes */
-        la t0, IT83XX_GCTRL_EIDSR
-        lb t1, 0(t0)
-        andi t1, t1, 0xf0
-        ori  t1, t1, 0x8
-        sb t1, 0(t0)
-#endif
-        /* Clear BSS */
-        la t0, __bss_start
-        la t1, __bss_end
-bss_loop:
-        sw zero, 0(t0)
-        addi t0, t0, 4
-        bltu t0, t1, bss_loop
-        /* Copy initialized data to data section */
-        la t0, __data_start
-        la t1, __data_end
-        la t2, __data_lma_start
-data_loop:
-        lw t3, 0(t2)
-        sw t3, 0(t0)
-        addi t0, t0, 4
-        addi t2, t2, 4
-        bltu t0, t1, data_loop
-        /* store the content of t5 (ra after reset) into "ec_reset_lp" */
-        la t0, ec_reset_lp
-        sw t5, 0(t0)
-#ifdef CHIP_FAMILY_IT8XXX2
-        /* clear BRAM if it is not valid */
-        jal chip_bram_valid
-#endif
-        /* Jump to C routine */
-        jal main
-        /* That should not return.  If it does, loop forever. */
-        j .
-
-.global unhandled_ec_irq
-.global unhandled_interrupt
-unhandled_ec_irq:
-        li tp, 0xBAD1
-        j __unhandled_irq
-unhandled_interrupt:
-        li tp, 0xBAD0
-__unhandled_irq:
-        slli tp, tp, 16
-        la t0, ec_int
-        lw t0, 0(t0)
-        add tp, tp, t0
-        j excep_handler /* display exception with TP bad[0|1]<ec_int> */
-
-.global excep_handler
-excep_handler:
-        /* save t2 */
-        csrw mscratch, t2
-        /* restore registers (sp, ra, t0, and t1) state */
-        la t2, excep_entry_saved_regs
-        lw sp, 0*4(t2)
-        lw ra, 1*4(t2)
-        lw t0, 2*4(t2)
-        lw t1, 3*4(t2)
-        /* restore t2 */
-        csrr t2, mscratch
-        /* save sp to scratch register */
-        csrw mscratch, sp
-        la sp, saved_regs
-        /* save sp, ra, gp, tp , a0-a7, t0-t6, and s0-s11 registers */
-        sw s11, 0*4(sp)
-        sw s10, 1*4(sp)
-        sw s9, 2*4(sp)
-        sw s8, 3*4(sp)
-        sw s7, 4*4(sp)
-        sw s6, 5*4(sp)
-        sw s5, 6*4(sp)
-        sw s4, 7*4(sp)
-        sw s3, 8*4(sp)
-        sw s2, 9*4(sp)
-        sw s1, 10*4(sp)
-        sw s0, 11*4(sp)
-        sw t6, 12*4(sp)
-        sw t5, 13*4(sp)
-        sw t4, 14*4(sp)
-        sw t3, 15*4(sp)
-        sw t2, 16*4(sp)
-        sw t1, 17*4(sp)
-        sw t0, 18*4(sp)
-        sw a7, 19*4(sp)
-        sw a6, 20*4(sp)
-        sw a5, 21*4(sp)
-        sw a4, 22*4(sp)
-        sw a3, 23*4(sp)
-        sw a2, 24*4(sp)
-        sw a1, 25*4(sp)
-        sw a0, 26*4(sp)
-        sw tp, 27*4(sp)
-        sw gp, 28*4(sp)
-        sw ra, 29*4(sp)
-        la a0, saved_regs
-        csrr sp, mscratch
-        sw sp, 30*4(a0)
-        /* put a valid stack pointer */
-        la sp, stack_end
-        /* jump to panic dump C routine */
-        jal report_panic
-        j .
-
-.align 2
-_bss_start:
-.long __bss_start
-_bss_end:
-.long __bss_end
-_data_start:
-.long __data_start
-_data_end:
-.long __data_end
-_data_lma_start:
-.long __data_lma_start
-
-/*
- * Reserve space for system stack.
- *
- * Main routine and ISR will share this space before tasks start.
- * This space is then dedicated to ISRs after tasks start.
- *
- * NOTE: Location of system stack (.bss.system_stack) must be less than
- * tasks stacks (task_stacks@.bss) and scratchpad for first context switch
- * (scratchpad[]@.bss.task_scratchpad).
- */
-.section .bss.system_stack
-stack_start:
-.space CONFIG_STACK_SIZE, 0
-stack_end:
-.global stack_end
-
-/* sp, ra, t0, t1 registers state at exception entry */
-.global excep_entry_saved_regs
-excep_entry_saved_regs:
-.long 0, 0, 0, 0
-
-/* registers state at exception entry */
-.global saved_regs
-saved_regs:
-.long 0, 0, 0, 0, 0, 0, 0, 0
-.long 0, 0, 0, 0, 0, 0, 0, 0
-.long 0, 0, 0, 0, 0, 0, 0, 0
-.long 0, 0, 0, 0, 0, 0, 0, 0
diff --git a/core/riscv-rv32i/irq_chip.h b/core/riscv-rv32i/irq_chip.h
deleted file mode 100644
index 45cabf346e..0000000000
--- a/core/riscv-rv32i/irq_chip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Chip-specific part of the IRQ handling.
- */
-
-#ifndef __CROS_EC_IRQ_CHIP_H
-#define __CROS_EC_IRQ_CHIP_H
-
-/**
- * Enable an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- */
-void chip_enable_irq(int irq);
-
-/**
- * Disable an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- */
-void chip_disable_irq(int irq);
-
-/**
- * Clear a pending IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- *
- * Note that most interrupts can be removed from the pending state simply by
- * handling whatever caused the interrupt in the first place.  This only needs
- * to be called if an interrupt handler disables itself without clearing the
- * reason for the interrupt, and then the interrupt is re-enabled from a
- * different context.
- */
-void chip_clear_pending_irq(int irq);
-
-/**
- * Software-trigger an IRQ in the chip interrupt controller.
- *
- * @param irq interrupt request index.
- * @return CPU interrupt number to trigger if any, -1 else.
- */
-int chip_trigger_irq(int irq);
-
-/**
- * Initialize chip interrupt controller.
- */
-void chip_init_irqs(void);
-
-/**
- * Return external interrupt number.
- */
-int chip_get_ec_int(void);
-
-/**
- * Return group number of the given external interrupt number.
- */
-int chip_get_intc_group(int irq);
-
-#endif /* __CROS_EC_IRQ_CHIP_H */
diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h
deleted file mode 100644
index 6414f90c7f..0000000000
--- a/core/riscv-rv32i/irq_handler.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helper to declare IRQ handling routines */
-
-#ifndef __CROS_EC_IRQ_HANDLER_H
-#define __CROS_EC_IRQ_HANDLER_H
-
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
-
-#ifndef CPU_INT
-#define CPU_INT(irq) irq
-#endif
-
-/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	void routine(void);						\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
-
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c
deleted file mode 100644
index 591a67eb8f..0000000000
--- a/core/riscv-rv32i/math.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#ifdef CONFIG_FPU
-/* Single precision floating point square root. */
-float sqrtf(float x)
-{
-	asm volatile (
-		"fsqrt.s %0, %1"
-		: "=f" (x)
-		: "f" (x));
-
-	return x;
-}
-#endif
diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c
deleted file mode 100644
index b339fdf76c..0000000000
--- a/core/riscv-rv32i/panic.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cpu.h"
-#include "panic.h"
-#include "task.h"
-#include "util.h"
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-/**
- * bit[3-0] @ mcause, general exception type information.
- */
-static const char * const exc_type[16] = {
-	"Instruction address misaligned",
-	"Instruction access fault",
-	"Illegal instruction",
-	"Breakpoint",
-	"Load address misaligned",
-	"Load access fault",
-	"Store/AMO address misaligned",
-	"Store/AMO access fault",
-
-	NULL,
-	NULL,
-	NULL,
-	"Environment call from M-mode",
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-};
-#endif /* CONFIG_DEBUG_EXCEPTIONS */
-
-#ifdef CONFIG_SOFTWARE_PANIC
-/* General purpose register (s0) for saving software panic reason */
-#define SOFT_PANIC_GPR_REASON 11
-/* General purpose register (s1) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   10
-
-void software_panic(uint32_t reason, uint32_t info)
-{
-	asm volatile ("mv s0, %0" : : "r"(reason) : "s0");
-	asm volatile ("mv s1, %0" : : "r"(info)   : "s1");
-	if (in_interrupt_context())
-		asm("j excep_handler");
-	else
-		asm("ebreak");
-	__builtin_unreachable();
-}
-
-void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
-{
-	/*
-	 * It is safe to get pointer using get_panic_data_write().
-	 * If it was called earlier (eg. when saving riscv.mepc) calling it
-	 * once again won't remove any data
-	 */
-	struct panic_data * const pdata = get_panic_data_write();
-	uint32_t warning_mepc;
-	uint32_t *regs;
-
-	regs = pdata->riscv.regs;
-
-	/* Setup panic data structure */
-	if (reason != PANIC_SW_WATCHDOG) {
-		memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-	} else {
-		warning_mepc = pdata->riscv.mepc;
-		memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-		pdata->riscv.mepc = warning_mepc;
-	}
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_RISCV_RV32I;
-
-	/* Log panic cause */
-	pdata->riscv.mcause = exception;
-	regs[SOFT_PANIC_GPR_REASON] = reason;
-	regs[SOFT_PANIC_GPR_INFO] = info;
-}
-
-void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
-{
-	struct panic_data * const pdata = panic_get_data();
-	uint32_t *regs;
-
-	if (pdata && pdata->struct_version == 2) {
-		regs = pdata->riscv.regs;
-		*exception = pdata->riscv.mcause;
-		*reason = regs[SOFT_PANIC_GPR_REASON];
-		*info = regs[SOFT_PANIC_GPR_INFO];
-	} else {
-		*exception = *reason = *info = 0;
-	}
-}
-#endif /* CONFIG_SOFTWARE_PANIC */
-
-static void print_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
-{
-	panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
-	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
-
-#ifdef CONFIG_DEBUG_EXCEPTIONS
-	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
-#ifdef CONFIG_SOFTWARE_PANIC
-		panic_printf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
-		panic_printf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
-#endif
-	} else {
-		panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
-	}
-#endif
-}
-
-void report_panic(uint32_t *regs)
-{
-	uint32_t i, mcause, mepc;
-	struct panic_data * const pdata = get_panic_data_write();
-
-	mepc = get_mepc();
-	mcause = get_mcause();
-
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH_RISCV_RV32I;
-	pdata->flags = 0;
-	pdata->reserved = 0;
-
-	pdata->riscv.mcause = mcause;
-	pdata->riscv.mepc = mepc;
-	for (i = 0; i < 31; i++)
-		pdata->riscv.regs[i] = regs[i];
-
-	print_panic_information(regs, mcause, mepc);
-	panic_reboot();
-}
-
-void panic_data_print(const struct panic_data *pdata)
-{
-	uint32_t *regs, mcause, mepc;
-
-	regs = (uint32_t *)pdata->riscv.regs;
-	mcause = pdata->riscv.mcause;
-	mepc = pdata->riscv.mepc;
-	print_panic_information(regs, mcause, mepc);
-}
diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S
deleted file mode 100644
index 8760667c6b..0000000000
--- a/core/riscv-rv32i/switch.S
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Context switching
- */
-
-#include "config.h"
-#include "cpu.h"
-
-#ifdef __RAM_CODE_SECTION_NAME
-.section __RAM_CODE_SECTION_NAME
-#endif
-
-/**
- * Task context switching
- *
- * Change the task scheduled after returning from an interruption.
- *
- * This function must be called in interrupt context.
- *
- * Save the registers of the current task below the interrupt context on
- * its task, then restore the live registers of the next task and set the
- * process stack pointer to the new stack.
- *
- * the structure of the saved context on the stack is :
- * ra, a0-a7, t0-t6 (caller saved) ,  s0-s11 (callee saved), mepc
- * interrupt entry frame          <|> additional registers
- * if enabling the FPU:
- * ra, a0-a7, t0-t6, ft0-ft11, fa0-fa7, and fcsr <|>
- * s0-s11, fs0-fs11, and mepc
- *
- */
-.global __switch_task
-__switch_task:
-	/* get the (new) highest priority task pointer in a0 */
-	jal next_sched_task
-	/* pointer to the current task (which are switching from) */
-	la t1, current_task
-	lw t0, 0(t1)
-	/* reset the re-scheduling request */
-	la t2, need_resched
-	sw zero, 0(t2)
-	/* Nothing to do: let's return to keep the same task scheduled */
-	beq a0, t0, __irq_exit
-	/* save our new scheduled task  */
-	sw a0, 0(t1)
-        /* save our current location in system stack so we can restore at end */
-        add t3, sp, zero
-        /* restore current process stack pointer */
-        csrr sp, mscratch
-        /* get the task program counter saved at exception entry */
-	csrr t5, mepc
-	/* save s0-s11 on the current process stack */
-        sw s11, -12*4(sp)
-        sw s10, -11*4(sp)
-        sw s9,  -10*4(sp)
-        sw s8,  -9*4(sp)
-        sw s7,  -8*4(sp)
-        sw s6,  -7*4(sp)
-        sw s5,  -6*4(sp)
-        sw s4,  -5*4(sp)
-        sw s3,  -4*4(sp)
-        sw s2,  -3*4(sp)
-        sw s1,  -2*4(sp)
-        sw s0,  -1*4(sp)
-#ifdef CONFIG_FPU
-        /* save fs0-fs11 on the current process stack */
-        fsw fs11, -24*4(sp)
-        fsw fs10, -23*4(sp)
-        fsw fs9,  -22*4(sp)
-        fsw fs8,  -21*4(sp)
-        fsw fs7,  -20*4(sp)
-        fsw fs6,  -19*4(sp)
-        fsw fs5,  -18*4(sp)
-        fsw fs4,  -17*4(sp)
-        fsw fs3,  -16*4(sp)
-        fsw fs2,  -15*4(sp)
-        fsw fs1,  -14*4(sp)
-        fsw fs0,  -13*4(sp)
-        /* save program counter on the current process stack */
-        sw t5,       -25*4(sp)
-        /*
-         * Note: we never execute on this stack frame, so it does not need to
-         * be 16-byte aligned.
-         */
-        addi sp, sp, -25*4
-#else
-	/* save program counter on the current process stack */
-        sw t5,       -13*4(sp)
-        /*
-         * Note: we never execute on this stack frame, so it does not need to
-         * be 16-byte aligned.
-         */
-        addi sp, sp, -13*4
-#endif
-        /* save the task stack pointer in its context */
-        sw sp, 0(t0)
-        /* get the new scheduled task stack pointer */
-        lw sp, 0(a0)
-#ifdef CONFIG_FPU
-        addi sp, sp, 25*4
-        /* get mepc */
-        lw t0,    -25*4(sp)
-        /* restore FP registers (fs0-fs11) from the next stack context */
-        flw fs11, -24*4(sp)
-        flw fs10, -23*4(sp)
-        flw fs9,  -22*4(sp)
-        flw fs8,  -21*4(sp)
-        flw fs7,  -20*4(sp)
-        flw fs6,  -19*4(sp)
-        flw fs5,  -18*4(sp)
-        flw fs4,  -17*4(sp)
-        flw fs3,  -16*4(sp)
-        flw fs2,  -15*4(sp)
-        flw fs1,  -14*4(sp)
-        flw fs0,  -13*4(sp)
-#else
-        addi sp, sp, 13*4
-        /* get mepc */
-        lw t0,      -13*4(sp)
-#endif
-        /* restore program counter from the next stack context */
-        csrw mepc, t0
-        /* restore registers from the next stack context */
-        lw s11, -12*4(sp)
-        lw s10, -11*4(sp)
-        lw s9,  -10*4(sp)
-        lw s8,  -9*4(sp)
-        lw s7,  -8*4(sp)
-        lw s6,  -7*4(sp)
-        lw s5,  -6*4(sp)
-        lw s4,  -5*4(sp)
-        lw s3,  -4*4(sp)
-        lw s2,  -3*4(sp)
-        lw s1,  -2*4(sp)
-        lw s0,  -1*4(sp)
-        /*
-         * save sp to scratch register and switch to system stack.
-         * __irq_exit will restore sp from scratch register again before mret.
-         */
-        csrw mscratch, sp
-        /* restore system stack */
-        add sp, t3, zero
-        j __irq_exit
-
-.text
-/**
- * Start the task scheduling.
- */
-.global __task_start
-__task_start:
-	csrci mstatus, 0x8
-	/* area used as thread stack for the first switch */
-	la a3, scratchpad
-	li a4, 1
-	li a2, 0    /* system call 3rd parameter : not an IRQ emulation */
-	li a1, 0    /* system call 2nd parameter : re-schedule nothing */
-	li a0, 0    /* system call 1st parameter : de-schedule nothing */
-	/* put the stack pointer at the top of the stack in scratchpad */
-	addi sp, a3, 4 * TASK_SCRATCHPAD_SIZE
-	/* we are ready to re-schedule */
-	la t0, need_resched
-	sw a4, 0(t0)
-        la t0, start_called
-        sw a4, 0(t0)
-        csrsi mstatus, 0x8
-	/* trigger scheduling to execute the task with the highest priority */
-	ecall
-	/* we should never return here */
-	j .
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
deleted file mode 100644
index 558177e969..0000000000
--- a/core/riscv-rv32i/task.c
+++ /dev/null
@@ -1,725 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Task scheduling / events module for Chrome EC operating system */
-
-#include "atomic.h"
-#include "console.h"
-#include "cpu.h"
-#include "irq_chip.h"
-#include "link_defs.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-typedef struct {
-	/*
-	 * Note that sp must be the first element in the task struct
-	 * for __switchto() to work.
-	 */
-	uint32_t sp;       /* Saved stack pointer for context switch */
-	uint32_t events;   /* Bitmaps of received events */
-	uint64_t runtime;  /* Time spent in task */
-	uint32_t *stack;   /* Start of stack */
-} task_;
-
-/* Value to store in unused stack */
-#define STACK_UNUSED_VALUE 0xdeadd00d
-
-/* declare task routine prototypes */
-#define TASK(n, r, d, s) void r(void *);
-void __idle(void);
-CONFIG_TASK_LIST
-CONFIG_TEST_TASK_LIST
-#undef TASK
-
-/* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
-#undef TASK
-
-#ifdef CONFIG_TASK_PROFILING
-static int task_will_switch;
-static uint32_t exc_sub_time;
-static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
-#endif
-
-extern int __task_start(void);
-
-#if defined(CHIP_FAMILY_IT83XX)
-extern void clock_sleep_mode_wakeup_isr(void);
-#endif
-
-#ifndef CONFIG_LOW_POWER_IDLE
-/* Idle task.  Executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	/*
-	 * Print when the idle task starts.  This is the lowest priority task,
-	 * so this only starts once all other tasks have gotten a chance to do
-	 * their task inits and have gone to sleep.
-	 */
-	cprints(CC_TASK, "idle task started");
-
-	while (1) {
-#if defined(CHIP_FAMILY_IT83XX)
-		/* doze mode */
-		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
-		clock_cpu_standby();
-#else
-		asm("wfi");
-#endif
-	}
-}
-#endif /* !CONFIG_LOW_POWER_IDLE */
-
-static void task_exit_trap(void)
-{
-	int i = task_get_current();
-
-	cprints(CC_TASK, "Task %d (%s) exited!", i, task_names[i]);
-	/* Exited tasks simply sleep forever */
-	while (1)
-		task_wait_event(-1);
-}
-
-/* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.a0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
-static const struct {
-	uint32_t a0;
-	uint32_t pc;
-	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
-#undef TASK
-
-/* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks")));
-/* Validity checks about static task invariants */
-BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8));
-BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
-
-/* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
-
-#undef TASK
-
-/* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
-
-task_ *current_task = (task_ *)scratchpad;
-
-/*
- * Should IRQs chain to svc_handler()?  This should be set if either of the
- * following is true:
- *
- * 1) Task scheduling has started, and task profiling is enabled.  Task
- * profiling does its tracking in svc_handler().
- *
- * 2) An event was set by an interrupt; this could result in a higher-priority
- * task unblocking.  After checking for a task switch, svc_handler() will clear
- * the flag (unless profiling is also enabled; then the flag remains set).
- */
-int need_resched;
-
-/*
- * Bitmap of all tasks ready to be run.
- *
- * Start off with only the hooks task marked as ready such that all the modules
- * can do their init within a task switching context.  The hooks task will then
- * make a call to enable all tasks.
- */
-static uint32_t tasks_ready = BIT(TASK_ID_HOOKS);
-/*
- * Initially allow only the HOOKS and IDLE task to run, regardless of ready
- * status, in order for HOOK_INIT to complete before other tasks.
- * task_enable_all_tasks() will open the flood gates.
- */
-static uint32_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
-
-int start_called;  /* Has task swapping started */
-
-/* in interrupt context */
-volatile bool in_interrupt;
-/* Interrupt number of EC modules */
-volatile int ec_int;
-/* Interrupt group of EC INTC modules */
-volatile int ec_int_group;
-/* interrupt number of sw interrupt */
-static int sw_int_num;
-/* This variable is used to save return address register at EC reset. */
-uint32_t ec_reset_lp;
-/*
- * This variable is used to save return address register,
- * and it is updated at the beginning of each ISR.
- */
-uint32_t ira;
-
-static inline task_ *__task_id_to_ptr(task_id_t id)
-{
-	return tasks + id;
-}
-
-void __ram_code interrupt_disable(void)
-{
-	/* bit11: disable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrc mie, t0");
-}
-
-void __ram_code interrupt_enable(void)
-{
-	/* bit11: enable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrs  mie, t0");
-}
-
-inline int is_interrupt_enabled(void)
-{
-	int mie = 0;
-
-	asm volatile ("csrr %0, mie" : "=r"(mie));
-
-	/* Check if MEIE bit is set in MIE register */
-	return !!(mie & 0x800);
-}
-
-inline int in_interrupt_context(void)
-{
-	return in_interrupt;
-}
-
-int in_soft_interrupt_context(void)
-{
-	/* group 16 is reserved for soft-irq */
-	return in_interrupt_context() && ec_int_group == 16;
-}
-
-task_id_t __ram_code task_get_current(void)
-{
-#ifdef CONFIG_DEBUG_BRINGUP
-	/* If we haven't done a context switch then our task ID isn't valid */
-	ASSERT(current_task != (task_ *)scratchpad);
-#endif
-	return current_task - tasks;
-}
-
-uint32_t * __ram_code task_get_event_bitmap(task_id_t tskid)
-{
-	task_ *tsk = __task_id_to_ptr(tskid);
-
-	return &tsk->events;
-}
-
-int task_start_called(void)
-{
-	return start_called;
-}
-
-/**
- * Scheduling system call
- *
- * Also includes emulation of software triggering interrupt vector
- */
-void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
-{
-	/* are we emulating an interrupt ? */
-	if (swirq) {
-		void (*handler)(void) = __irqhandler[swirq];
-		/* adjust IPC to return *after* the syscall instruction */
-		set_mepc(get_mepc() + 4);
-		/* call the regular IRQ handler */
-		handler();
-		sw_int_num = 0;
-		return;
-	}
-
-	if (desched && !current_task->events) {
-		/*
-		 * Remove our own ready bit (current - tasks is same as
-		 * task_get_current())
-		 */
-		tasks_ready &= ~(1 << (current_task - tasks));
-	}
-	tasks_ready |= 1 << resched;
-
-	/* trigger a re-scheduling on exit */
-	need_resched = 1;
-
-#ifdef CONFIG_TASK_PROFILING
-	svc_calls++;
-#endif
-	/* adjust IPC to return *after* the syscall instruction */
-	set_mepc(get_mepc() + 4);
-}
-
-task_ * __ram_code next_sched_task(void)
-{
-	task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
-
-#ifdef CONFIG_TASK_PROFILING
-	if (current_task != new_task) {
-		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
-		task_will_switch = 1;
-	}
-#endif
-
-#ifdef CONFIG_DEBUG_STACK_OVERFLOW
-	if (*current_task->stack != STACK_UNUSED_VALUE) {
-		int i = task_get_current();
-
-		panic_printf("\n\nStack overflow in %s task!\n", task_names[i]);
-#ifdef CONFIG_SOFTWARE_PANIC
-		software_panic(PANIC_SW_STACK_OVERFLOW, i);
-#endif
-	}
-#endif
-
-	return new_task;
-}
-
-static inline void __schedule(int desched, int resched, int swirq)
-{
-	register int p0 asm("a0") = desched;
-	register int p1 asm("a1") = resched;
-	register int p2 asm("a2") = swirq;
-
-	asm("ecall" : : "r"(p0), "r"(p1), "r"(p2));
-}
-
-void __ram_code update_exc_start_time(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	exc_start_time = get_time().le.lo;
-#endif
-}
-
-/**
- * The beginning of interrupt handler of c language code.
- *
- * @param  none
- * @return -1 if it cannot find the corresponding interrupt source.
- */
-int __ram_code start_irq_handler(void)
-{
-	/* If this is a SW interrupt */
-	if (get_mcause() == 11) {
-		ec_int = sw_int_num;
-		ec_int_group = 16;
-	} else {
-		/*
-		 * Determine interrupt number.
-		 * -1 if it cannot find the corresponding interrupt source.
-		 */
-		if (chip_get_ec_int() == -1)
-			return -1;
-		ec_int_group = chip_get_intc_group(ec_int);
-	}
-
-#if defined(CONFIG_LOW_POWER_IDLE) && defined(CHIP_FAMILY_IT83XX)
-	clock_sleep_mode_wakeup_isr();
-#endif
-#ifdef CONFIG_TASK_PROFILING
-	update_exc_start_time();
-
-	/*
-	 * Track IRQ distribution.  No need for atomic add, because an IRQ
-	 * can't pre-empt itself.
-	 */
-	if ((ec_int > 0) && (ec_int < ARRAY_SIZE(irq_dist)))
-		irq_dist[ec_int]++;
-#endif
-
-	return EC_SUCCESS;
-}
-
-void __ram_code end_irq_handler(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	uint32_t t, p;
-
-	t = get_time().le.lo;
-	p = t - exc_start_time;
-
-	exc_total_time += p;
-	exc_sub_time += p;
-	if (task_will_switch) {
-		task_will_switch = 0;
-		exc_sub_time = 0;
-		exc_end_time = t;
-		task_switches++;
-	}
-#endif
-}
-
-static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
-{
-	task_ *tsk = current_task;
-	task_id_t me = tsk - tasks;
-	uint32_t evt;
-	int ret;
-
-	ASSERT(!in_interrupt_context());
-
-	if (timeout_us > 0) {
-		timestamp_t deadline = get_time();
-
-		deadline.val += timeout_us;
-		ret = timer_arm(deadline, me);
-		ASSERT(ret == EC_SUCCESS);
-	}
-	while (!(evt = atomic_clear(&tsk->events))) {
-		/* Remove ourself and get the next task in the scheduler */
-		__schedule(1, resched, 0);
-		resched = TASK_ID_IDLE;
-	}
-	if (timeout_us > 0) {
-		timer_cancel(me);
-		/* Ensure timer event is clear, we no longer care about it */
-		atomic_clear_bits(&tsk->events, TASK_EVENT_TIMER);
-	}
-	return evt;
-}
-
-uint32_t __ram_code task_set_event(task_id_t tskid, uint32_t event)
-{
-	task_ *receiver = __task_id_to_ptr(tskid);
-
-	ASSERT(receiver);
-
-	/* Set the event bit in the receiver message bitmap */
-	atomic_or(&receiver->events, event);
-
-	/* Re-schedule if priorities have changed */
-	if (in_interrupt_context()) {
-		/* The receiver might run again */
-		atomic_or(&tasks_ready, 1 << tskid);
-		if (start_called)
-			need_resched = 1;
-	} else {
-		__schedule(0, tskid, 0);
-	}
-
-	return 0;
-}
-
-uint32_t __ram_code task_wait_event(int timeout_us)
-{
-	return __wait_evt(timeout_us, TASK_ID_IDLE);
-}
-
-uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	uint64_t deadline = get_time().val + timeout_us;
-	uint32_t events = 0;
-	int time_remaining_us = timeout_us;
-
-	/* Add the timer event to the mask so we can indicate a timeout */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(events & event_mask)) {
-		/* Collect events to re-post later */
-		events |= __wait_evt(time_remaining_us, TASK_ID_IDLE);
-
-		time_remaining_us = deadline - get_time().val;
-		if (timeout_us > 0 && time_remaining_us <= 0) {
-			/* Ensure we return a TIMER event if we timeout */
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-	}
-
-	/* Re-post any other events collected */
-	if (events & ~event_mask)
-		atomic_or(&current_task->events, events & ~event_mask);
-
-	return events & event_mask;
-}
-
-uint32_t __ram_code read_clear_int_mask(void)
-{
-	uint32_t mie, meie = BIT(11);
-
-	/* Read and clear MEIE bit of MIE register. */
-	asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
-
-	return mie;
-}
-
-void __ram_code set_int_mask(uint32_t val)
-{
-	asm volatile ("csrw mie, %0" : : "r"(val));
-}
-
-void task_enable_all_tasks(void)
-{
-	/* Mark all tasks as ready and able to run. */
-	tasks_ready = tasks_enabled = BIT(TASK_ID_COUNT) - 1;
-	/* Reschedule the highest priority task. */
-	__schedule(0, 0, 0);
-}
-
-void task_enable_task(task_id_t tskid)
-{
-	atomic_or(&tasks_enabled, BIT(tskid));
-}
-
-void task_disable_task(task_id_t tskid)
-{
-	atomic_clear_bits(&tasks_enabled, BIT(tskid));
-
-	if (!in_interrupt_context() && tskid == task_get_current())
-		__schedule(0, 0, 0);
-}
-
-void __ram_code task_enable_irq(int irq)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	chip_enable_irq(irq);
-	set_int_mask(int_mask);
-}
-
-void __ram_code task_disable_irq(int irq)
-{
-	uint32_t int_mask = read_clear_int_mask();
-
-	chip_disable_irq(irq);
-	set_int_mask(int_mask);
-}
-
-void __ram_code task_clear_pending_irq(int irq)
-{
-	chip_clear_pending_irq(irq);
-}
-
-void __ram_code task_trigger_irq(int irq)
-{
-	int cpu_int = chip_trigger_irq(irq);
-
-	if (cpu_int > 0) {
-		sw_int_num = irq;
-		__schedule(0, 0, cpu_int);
-	}
-}
-
-/*
- * Initialize IRQs in the IVIC and set their priorities as defined by the
- * DECLARE_IRQ statements.
- */
-static void ivic_init_irqs(void)
-{
-	/* chip-specific interrupt controller initialization */
-	chip_init_irqs();
-	/*
-	 * Re-enable global interrupts in case they're disabled.  On a reboot,
-	 * they're already enabled; if we've jumped here from another image,
-	 * they're not.
-	 */
-	interrupt_enable();
-}
-
-void __ram_code mutex_lock(struct mutex *mtx)
-{
-	uint32_t locked;
-	uint32_t id = 1 << task_get_current();
-
-	ASSERT(id != TASK_ID_INVALID);
-	atomic_or(&mtx->waiters, id);
-
-	while (1) {
-		asm volatile (
-			/* set lock value */
-			"li %0, 2\n\t"
-			/* attempt to acquire lock */
-			"amoswap.w.aq %0, %0, %1\n\t"
-			: "=&r" (locked), "+A" (mtx->lock));
-		/* we got it ! */
-		if (!locked)
-			break;
-		/* Contention on the mutex */
-		/* Sleep waiting for our turn */
-		task_wait_event_mask(TASK_EVENT_MUTEX, 0);
-	}
-
-	atomic_clear_bits(&mtx->waiters, id);
-}
-
-void __ram_code mutex_unlock(struct mutex *mtx)
-{
-	uint32_t waiters;
-	task_ *tsk = current_task;
-
-	/* give back the lock */
-	asm volatile (
-		"amoswap.w.aqrl zero, zero, %0\n\t"
-		: "+A" (mtx->lock));
-	waiters = mtx->waiters;
-
-	while (waiters) {
-		task_id_t id = __fls(waiters);
-
-		waiters &= ~BIT(id);
-
-		/* Somebody is waiting on the mutex */
-		task_set_event(id, TASK_EVENT_MUTEX);
-	}
-
-	/* Ensure no event is remaining from mutex wake-up */
-	atomic_clear_bits(&tsk->events, TASK_EVENT_MUTEX);
-}
-
-void task_print_list(void)
-{
-	int i;
-
-	ccputs("Task Ready Name         Events      Time (s)  StkUsed\n");
-
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		char is_ready = (tasks_ready & (1<<i)) ? 'R' : ' ';
-		uint32_t *sp;
-
-		int stackused = tasks_init[i].stack_size;
-
-		for (sp = tasks[i].stack;
-		     sp < (uint32_t *)tasks[i].sp && *sp == STACK_UNUSED_VALUE;
-		     sp++)
-			stackused -= sizeof(uint32_t);
-
-		ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i, is_ready,
-			 task_names[i], tasks[i].events, tasks[i].runtime,
-			 stackused, tasks_init[i].stack_size);
-		cflush();
-	}
-}
-
-int command_task_info(int argc, char **argv)
-{
-#ifdef CONFIG_TASK_PROFILING
-	unsigned int total = 0;
-	int i;
-#endif
-
-	task_print_list();
-
-#ifdef CONFIG_TASK_PROFILING
-	ccputs("IRQ counts by type:\n");
-	cflush();
-	for (i = 0; i < ARRAY_SIZE(irq_dist); i++) {
-		if (irq_dist[i]) {
-			ccprintf("%4d %8d\n", i, irq_dist[i]);
-			total += irq_dist[i];
-		}
-	}
-
-	ccprintf("Service calls:          %11u\n", svc_calls);
-	ccprintf("Total exceptions:       %11u\n", total + svc_calls);
-	ccprintf("Task switches:          %11u\n", task_switches);
-	ccprintf("Task switching started: %11.6llu s\n", task_start_time);
-	ccprintf("Time in tasks:          %11.6llu s\n",
-		 get_time().val - task_start_time);
-	ccprintf("Time in exceptions:     %11.6llu s\n", exc_total_time);
-#endif
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
-
-static int command_task_ready(int argc, char **argv)
-{
-	if (argc < 2) {
-		ccprintf("tasks_ready: 0x%08x\n", tasks_ready);
-	} else {
-		tasks_ready = strtoi(argv[1], NULL, 16);
-		ccprintf("Setting tasks_ready to 0x%08x\n", tasks_ready);
-		__schedule(0, 0, 0);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
-			"Print/set ready tasks");
-
-void task_pre_init(void)
-{
-	uint32_t *stack_next = (uint32_t *)task_stacks;
-	int i;
-
-	/* Fill the task memory with initial values */
-	for (i = 0; i < TASK_ID_COUNT; i++) {
-		uint32_t *sp;
-		/* Stack size in words */
-		uint32_t ssize = tasks_init[i].stack_size / 4;
-
-		tasks[i].stack = stack_next;
-
-		/*
-		 * Update stack used by first frame: 28 regs + MEPC + (FP regs)
-		 */
-		sp = stack_next + ssize - TASK_SCRATCHPAD_SIZE;
-		tasks[i].sp = (uint32_t)sp;
-
-		/* Initial context on stack (see __switchto()) */
-		sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0;         /* a0 */
-		sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */
-		sp[0] = tasks_init[i].pc;  /* pc/mepc */
-
-		/* Fill unused stack; also used to detect stack overflow. */
-		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
-			*sp = STACK_UNUSED_VALUE;
-
-		stack_next += ssize;
-	}
-
-	/*
-	 * Fill in guard value in scratchpad to prevent stack overflow
-	 * detection failure on the first context switch.  This works because
-	 * the first word in the scratchpad is where the switcher will store
-	 * sp, so it's ok to blow away.
-	 */
-	((task_ *)scratchpad)->stack = (uint32_t *)scratchpad;
-	*(uint32_t *)scratchpad = STACK_UNUSED_VALUE;
-
-	/* Initialize IRQs */
-	ivic_init_irqs();
-}
-
-int task_start(void)
-{
-#ifdef CONFIG_TASK_PROFILING
-	task_start_time = get_time().val;
-	exc_end_time = get_time().le.lo;
-#endif
-
-	return __task_start();
-}
diff --git a/cts/README b/cts/README
deleted file mode 100644
index 3a22e9846f..0000000000
--- a/cts/README
+++ /dev/null
@@ -1,6 +0,0 @@
-The first time you use this with a particular th,
-connect only th and run ./cts/cts.py --th from
-the ec directory.
-
-Then connect both boards and you can run
-./cts/cts to flash both boards.
\ No newline at end of file
diff --git a/cts/build.mk b/cts/build.mk
deleted file mode 100644
index 817b69b25c..0000000000
--- a/cts/build.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-# -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CFLAGS_CTS=-DCTS_MODULE=$(EMPTY) -DCTS_TASKFILE=cts.tasklist
-
-ifeq "$(CTS_MODULE)" "gpio"
-CFLAGS_CTS+=-DCTS_MODULE_GPIO=$(EMPTY)
-endif
-
-ifeq "$(CTS_MODULE)" "i2c"
-CFLAGS_CTS+=-DCTS_MODULE_I2C=$(EMPTY)
-CONFIG_I2C=y
-ifneq ($(BOARD),stm32l476g-eval)
-CONFIG_I2C_CONTROLLER=y
-endif
-endif
-
-cts-y+=common/cts_common.o
-
-ifeq ($(BOARD),stm32l476g-eval)
-	cts-y+=$(CTS_MODULE)/th.o
-	cts-y+=common/th_common.o
-else
-	cts-y+=$(CTS_MODULE)/dut.o
-	cts-y+=common/dut_common.o
-endif
diff --git a/cts/common/__init__.py b/cts/common/__init__.py
deleted file mode 100644
index e69de29bb2..0000000000
--- a/cts/common/__init__.py
+++ /dev/null
diff --git a/cts/common/board.py b/cts/common/board.py
deleted file mode 100644
index d2c8e02b04..0000000000
--- a/cts/common/board.py
+++ /dev/null
@@ -1,388 +0,0 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-from abc import ABCMeta
-from abc import abstractmethod
-import os
-import shutil
-import subprocess as sp
-import serial
-
-import six
-
-
-OCD_SCRIPT_DIR = '/usr/share/openocd/scripts'
-OPENOCD_CONFIGS = {
-    'stm32l476g-eval': 'board/stm32l4discovery.cfg',
-    'nucleo-f072rb': 'board/st_nucleo_f0.cfg',
-    'nucleo-f411re': 'board/st_nucleo_f4.cfg',
-}
-FLASH_OFFSETS = {
-    'stm32l476g-eval': '0x08000000',
-    'nucleo-f072rb': '0x08000000',
-    'nucleo-f411re': '0x08000000',
-}
-REBOOT_MARKER = 'UART initialized after reboot'
-
-
-def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
-
-
-class Board(six.with_metaclass(ABCMeta, object)):
-  """Class representing a single board connected to a host machine.
-
-  Attributes:
-    board: String containing actual type of board, i.e. nucleo-f072rb
-    config: Directory of board config file relative to openocd's
-        scripts directory
-    hla_serial: String containing board's hla_serial number (if board
-    is an stm32 board)
-    tty_port: String that is the path to the tty port which board's
-        UART outputs to
-    tty: String of file descriptor for tty_port
-  """
-
-  def __init__(self, board, module, hla_serial=None):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: String containing board name
-      module: String of the test module you are building,
-        i.e. gpio, timer, etc.
-      hla_serial: Serial number if board's adaptor is an HLA
-
-    Raises:
-      RuntimeError: Board is not supported
-    """
-    if board not in OPENOCD_CONFIGS:
-      msg = 'OpenOcd configuration not found for ' + board
-      raise RuntimeError(msg)
-    if board not in FLASH_OFFSETS:
-      msg = 'Flash offset not found for ' + board
-      raise RuntimeError(msg)
-    self.board = board
-    self.flash_offset = FLASH_OFFSETS[self.board]
-    self.openocd_config = OPENOCD_CONFIGS[self.board]
-    self.module = module
-    self.hla_serial = hla_serial
-    self.tty_port = None
-    self.tty = None
-
-  def reset_log_dir(self):
-    """Reset log directory."""
-    if os.path.isdir(self.log_dir):
-      shutil.rmtree(self.log_dir)
-    os.makedirs(self.log_dir)
-
-  @staticmethod
-  def get_stlink_serials():
-    """Gets serial numbers of all st-link v2.1 board attached to host.
-
-    Returns:
-      List of serials
-    """
-    usb_args = ['sudo', 'lsusb', '-v', '-d', '0x0483:0x374b']
-    st_link_info = sp.check_output(usb_args, **get_subprocess_args())
-    st_serials = []
-    for line in st_link_info.split('\n'):
-      if 'iSerial' not in line:
-        continue
-      words = line.split()
-      if len(words) <= 2:
-        continue
-      st_serials.append(words[2].strip())
-    return st_serials
-
-  @abstractmethod
-  def get_serial(self):
-    """Subclass should implement this."""
-    pass
-
-  def send_openocd_commands(self, commands):
-    """Send a command to the board via openocd.
-
-    Args:
-      commands: A list of commands to send
-
-    Returns:
-      True if execution is successful or False otherwise.
-    """
-    args = ['sudo', 'openocd', '-s', OCD_SCRIPT_DIR,
-            '-f', self.openocd_config, '-c', 'hla_serial ' + self.hla_serial]
-
-    for cmd in commands:
-      args += ['-c', cmd]
-    args += ['-c', 'shutdown']
-
-    rv = 1
-    with open(self.openocd_log, 'a') as output:
-      rv = sp.call(args, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_openocd_log()
-
-    return rv == 0
-
-  def dump_openocd_log(self):
-    with open(self.openocd_log) as log:
-      print(log.read())
-
-  def build(self, ec_dir):
-    """Builds test suite module for board.
-
-    Args:
-      ec_dir: String of the ec directory path
-
-    Returns:
-      True if build is successful or False otherwise.
-    """
-    cmds = ['make',
-            '--directory=' + ec_dir,
-            'BOARD=' + self.board,
-            'CTS_MODULE=' + self.module,
-            '-j']
-
-    rv = 1
-    with open(self.build_log, 'a') as output:
-      rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_build_log()
-
-    return rv == 0
-
-  def dump_build_log(self):
-    with open(self.build_log) as log:
-      print(log.read())
-
-  def flash(self, image_path):
-    """Flashes board with most recent build ec.bin."""
-    cmd = ['reset_config connect_assert_srst',
-           'init',
-           'reset init',
-           'flash write_image erase %s %s' % (image_path, self.flash_offset)]
-    return self.send_openocd_commands(cmd)
-
-  def to_string(self):
-    s = ('Type: Board\n'
-         'board: ' + self.board + '\n'
-         'hla_serial: ' + self.hla_serial + '\n'
-         'openocd_config: ' + self.openocd_config + '\n'
-         'tty_port: ' + self.tty_port + '\n'
-         'tty: ' + str(self.tty) + '\n')
-    return s
-
-  def reset_halt(self):
-    """Reset then halt board."""
-    return self.send_openocd_commands(['init', 'reset halt'])
-
-  def resume(self):
-    """Resume halting board."""
-    return self.send_openocd_commands(['init', 'resume'])
-
-  def setup_tty(self):
-    """Call this before calling read_tty for the first time.
-
-    This is not in the initialization because caller only should call
-    this function after serial numbers are setup
-    """
-    self.get_serial()
-    self.reset_halt()
-    self.identify_tty_port()
-
-    tty = None
-    try:
-      tty = serial.Serial(self.tty_port, 115200, timeout=1)
-    except serial.SerialException:
-      raise ValueError('Failed to open ' + self.tty_port + ' of ' + self.board +
-                       '. Please make sure the port is available and you have' +
-                       ' permission to read it. Create dialout group and run:' +
-                       ' sudo usermod -a -G dialout <username>.')
-    self.tty = tty
-
-  def read_tty(self, max_boot_count=1):
-    """Read info from a serial port described by a file descriptor.
-
-    Args:
-      max_boot_count: Stop reading if boot count exceeds this number
-
-    Returns:
-      result: characters read from tty
-      boot: boot counts
-    """
-    buf = []
-    line = []
-    boot = 0
-    while True:
-      c = self.tty.read().decode('utf-8')
-      if not c:
-        break
-      line.append(c)
-      if c == '\n':
-        l = ''.join(line)
-        buf.append(l)
-        if REBOOT_MARKER in l:
-          boot += 1
-        line = []
-        if boot > max_boot_count:
-          break
-
-    l = ''.join(line)
-    buf.append(l)
-    result = ''.join(buf)
-
-    return result, boot
-
-  def identify_tty_port(self):
-    """Saves this board's serial port."""
-    dev_dir = '/dev'
-    id_prefix = 'ID_SERIAL_SHORT='
-    com_devices = [f for f in os.listdir(dev_dir) if f.startswith('ttyACM')]
-
-    for device in com_devices:
-      self.tty_port = os.path.join(dev_dir, device)
-      properties = sp.check_output(
-          ['udevadm', 'info', '-a', '-n', self.tty_port, '--query=property'],
-          **get_subprocess_args())
-      for line in [l.strip() for l in properties.split('\n')]:
-        if line.startswith(id_prefix):
-          if self.hla_serial == line[len(id_prefix):]:
-            return
-
-    # If we get here without returning, something is wrong
-    raise RuntimeError('The device dev path could not be found')
-
-  def close_tty(self):
-    """Close tty."""
-    self.tty.close()
-
-
-class TestHarness(Board):
-  """Subclass of Board representing a Test Harness.
-
-  Attributes:
-    serial_path: Path to file containing serial number
-  """
-
-  def __init__(self, board, module, log_dir, serial_path):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: board name
-      module: module name
-      log_dir: Directory where log file is stored
-      serial_path: Path to file containing serial number
-    """
-    Board.__init__(self, board, module)
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_th.log')
-    self.build_log = os.path.join(log_dir, 'build_th.log')
-    self.serial_path = serial_path
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Loads serial number from saved location."""
-    if self.hla_serial:
-      return  # serial was already loaded
-    try:
-      with open(self.serial_path, mode='r') as f:
-        s = f.read()
-        self.hla_serial = s.strip()
-        return
-    except IOError:
-      msg = ('Your TH board has not been identified.\n'
-             'Connect only TH and run the script --setup, then try again.')
-      raise RuntimeError(msg)
-
-  def save_serial(self):
-    """Saves the TH serial number to a file."""
-    serials = Board.get_stlink_serials()
-    if len(serials) > 1:
-      msg = ('There are more than one test board connected to the host.'
-             '\nConnect only the test harness and remove other boards.')
-      raise RuntimeError(msg)
-    if len(serials) < 1:
-      msg = ('No test boards were found.\n'
-             'Check boards are connected.')
-      raise RuntimeError(msg)
-
-    s = serials[0]
-    serial_dir = os.path.dirname(self.serial_path)
-    if not os.path.exists(serial_dir):
-      os.makedirs(serial_dir)
-    with open(self.serial_path, mode='w') as f:
-      f.write(s)
-      self.hla_serial = s
-
-    print('Your TH serial', s, 'has been saved as', self.serial_path)
-    return
-
-
-class DeviceUnderTest(Board):
-  """Subclass of Board representing a DUT board.
-
-  Attributes:
-    th: Reference to test harness board to which this DUT is attached
-  """
-
-  def __init__(self, board, th, module, log_dir, hla_ser=None):
-    """Initializes a DUT object.
-
-    Args:
-      board: String containing board name
-      th: Reference to test harness board to which this DUT is attached
-      module: module name
-      log_dir: Directory where log file is stored
-      hla_ser: Serial number if board uses an HLA adaptor
-    """
-    Board.__init__(self, board, module, hla_serial=hla_ser)
-    self.th = th
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_dut.log')
-    self.build_log = os.path.join(log_dir, 'build_dut.log')
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Get serial number.
-
-    Precondition: The DUT and TH must both be connected, and th.hla_serial
-    must hold the correct value (the th's serial #)
-
-    Raises:
-      RuntimeError: DUT isn't found or multiple DUTs are found.
-    """
-    if self.hla_serial is not None:
-      # serial was already set ('' is a valid serial)
-      return
-
-    serials = Board.get_stlink_serials()
-    dut = [s for s in serials if self.th.hla_serial != s]
-
-    # If len(dut) is 0 then your dut doesn't use an st-link device, so we
-    # don't have to worry about its serial number
-    if not dut:
-      msg = ('Failed to find serial for DUT.\n'
-             'Is ' + self.board + ' connected?')
-      raise RuntimeError(msg)
-    if len(dut) > 1:
-      msg = ('Found multiple DUTs.\n'
-             'You can connect only one DUT at a time. This may be caused by\n'
-             'an incorrect TH serial. Check if ' + self.th.serial_path + '\n'
-             'contains a correct serial.')
-      raise RuntimeError(msg)
-
-    # Found your other st-link device serial!
-    self.hla_serial = dut[0]
-    return
diff --git a/cts/common/cts.rc b/cts/common/cts.rc
deleted file mode 100644
index 264b982655..0000000000
--- a/cts/common/cts.rc
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This file is included by cts_common.h as an enumeration of error codes,
- * as well as being processed by cts.py to get error code names. The format
- * must be either of the followings:
- *
- *   CTS_RC_<NAME>,
- *   CTS_RC_<NAME> = X,
- *
- * where <NAME> will be printed on the result screen.
- */
-
-/*
- * Host only return codes. Should not be needed by th.c or dut.c.
- */
-/* Test didn't run */
-CTS_RC_DID_NOT_START = -1,
-/* Test didn't end */
-CTS_RC_DID_NOT_END = -2,
-/* Results were reported twice or more */
-CTS_RC_DUPLICATE_RUN = -3,
-/* Error in parsing return code. Probably it was null or not an integer. */
-CTS_RC_INVALID_RC = -4,
-
-/*
- * Regular return codes. Used by DUT and TH.
- */
-CTS_RC_SUCCESS = 0,
-CTS_RC_FAILURE,
-CTS_RC_BAD_SYNC,
-CTS_RC_TIMEOUT,
diff --git a/cts/common/cts_common.c b/cts/common/cts_common.c
deleted file mode 100644
index 8975636655..0000000000
--- a/cts/common/cts_common.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "cts_common.h"
-
-__attribute__((weak)) void clean_state(void)
-{
-	/* Each test overrides as needed */
-}
-
-void cts_main_loop(const struct cts_test* tests, const char *name)
-{
-	enum cts_rc rc;
-	int i;
-
-	cflush();
-	for (i = 0; i < cts_test_count; i++) {
-		CPRINTF("\n%s start\n", tests[i].name);
-		cflush();
-		clean_state();
-		sync();
-		rc = tests[i].run();
-		CPRINTF("\n%s end %d\n", tests[i].name, rc);
-		cflush();
-	}
-
-	CPRINTS("%s test suite finished", name);
-}
diff --git a/cts/common/cts_common.h b/cts/common/cts_common.h
deleted file mode 100644
index 13a435e655..0000000000
--- a/cts/common/cts_common.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CTS_COMMON_H
-#define __CTS_COMMON_H
-
-#include "console.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTL(format, args...) CPRINTS("%s:%d: "format, \
-					 __func__, __LINE__, ## args)
-
-#define READ_WAIT_TIME_MS		100
-#define CTS_INTERRUPT_TRIGGER_DELAY_US	(250 * MSEC)
-
-enum cts_rc {
-	#include "cts.rc"
-};
-
-struct cts_test {
-	enum cts_rc (*run)(void);
-	char *name;
-};
-
-extern const int cts_test_count;
-
-/**
- * Main loop where each test in a suite is executed
- *
- * A test suite can implement its custom loop as needed.
- *
- * Args:
- * @test: List of tests to run
- * @name: Name of the test to be printed on EC console
- */
-void cts_main_loop(const struct cts_test* tests, const char *name);
-
-/**
- * Callback function called at the beginning of the main loop
- */
-void clean_state(void);
-
-/**
- * Synchronize DUT and TH
- *
- * @return CTS_RC_SUCCESS if sync is successful
- */
-enum cts_rc sync(void);
-
-#endif
diff --git a/cts/common/cts_testlist.h b/cts/common/cts_testlist.h
deleted file mode 100644
index 1586c1348e..0000000000
--- a/cts/common/cts_testlist.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "util.h"
-
-/*
- * CTS_TEST macro takes the following arguments:
- *
- * @test: Function running the test
- * @th_rc: Expected CTS_RC_* from TH
- * @th_string: Expected string printed by TH
- * @dut_rc: Expected CTR_RC_* from DUT
- * @dut_string: Expected string printed by DUT
- *
- * CTS_TEST macro is processed in multiple places. One is here for creating
- * an array of test functions. Only @test is used.
- *
- * Another is in cts.py for evaluating the test results against expectations.
- */
-
-#undef CTS_TEST
-#define CTS_TEST(test, th_rc, th_string, dut_rc, dut_string) \
-	{test, STRINGIFY(test)},
-struct cts_test tests[] = {
-#include "cts.testlist"
-};
-
-const int cts_test_count = ARRAY_SIZE(tests);
diff --git a/cts/common/dut_common.c b/cts/common/dut_common.c
deleted file mode 100644
index 6e62a280e2..0000000000
--- a/cts/common/dut_common.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cts_common.h"
-#include "gpio.h"
-#include "watchdog.h"
-
-enum cts_rc sync(void)
-{
-	int input_level;
-
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 0);
-	do {
-		watchdog_reload();
-		input_level = gpio_get_level(GPIO_HANDSHAKE_INPUT);
-	} while (!input_level);
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 1);
-	do {
-		watchdog_reload();
-		input_level = gpio_get_level(GPIO_HANDSHAKE_INPUT);
-	} while (input_level);
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 0);
-
-	return CTS_RC_SUCCESS;
-}
-
diff --git a/cts/common/th_common.c b/cts/common/th_common.c
deleted file mode 100644
index 1d692b7843..0000000000
--- a/cts/common/th_common.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "timer.h"
-#include "watchdog.h"
-#include "cts_common.h"
-
-/* Return SUCCESS if and only if we reach end of function
- * Returning success here means sync was successful
- */
-enum cts_rc sync(void)
-{
-	int input_level;
-
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 0);
-	do {
-		watchdog_reload();
-		input_level = gpio_get_level(GPIO_HANDSHAKE_INPUT);
-	} while (input_level);
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 1);
-	do {
-		watchdog_reload();
-		input_level = gpio_get_level(GPIO_HANDSHAKE_INPUT);
-	} while (!input_level);
-	gpio_set_level(GPIO_HANDSHAKE_OUTPUT, 0);
-	do {
-		watchdog_reload();
-		input_level = gpio_get_level(GPIO_HANDSHAKE_INPUT);
-	} while (input_level);
-
-	return CTS_RC_SUCCESS;
-}
diff --git a/cts/cts.py b/cts/cts.py
deleted file mode 100755
index c3e0335cab..0000000000
--- a/cts/cts.py
+++ /dev/null
@@ -1,443 +0,0 @@
-#!/usr/bin/env python
-#
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# A script which builds, flashes, and runs EC CTS
-#
-# Software prerequisites:
-# - openocd version 0.10 or above
-# - lsusb
-# - udevadm
-#
-# To try it out, hook two boards (DEFAULT_TH and DEFAULT_DUT) with USB cables
-# to the host and execute the script:
-#   $ ./cts.py
-# It'll run mock tests. The result will be stored in CTS_TEST_RESULT_DIR.
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import argparse
-import os
-import shutil
-import time
-import common.board as board
-
-
-CTS_RC_PREFIX = 'CTS_RC_'
-DEFAULT_TH = 'stm32l476g-eval'
-DEFAULT_DUT = 'nucleo-f072rb'
-MAX_SUITE_TIME_SEC = 5
-CTS_TEST_RESULT_DIR = '/tmp/ects'
-
-# Host only return codes. Make sure they match values in cts.rc
-CTS_RC_DID_NOT_START = -1          # test did not run.
-CTS_RC_DID_NOT_END = -2            # test did not run.
-CTS_RC_DUPLICATE_RUN = -3          # test was run multiple times.
-CTS_RC_INVALID_RETURN_CODE = -4    # failed to parse return code
-
-
-class Cts(object):
-  """Class that represents a eCTS run.
-
-  Attributes:
-    dut: DeviceUnderTest object representing DUT
-    th: TestHarness object representing a test harness
-    module: Name of module to build/run tests for
-    testlist: List of strings of test names contained in given module
-    return_codes: Dict of strings of return codes, with a code's integer
-      value being the index for the corresponding string representation
-  """
-
-  def __init__(self, ec_dir, th, dut, module):
-    """Initializes cts class object with given arguments.
-
-    Args:
-      ec_dir: Path to ec directory
-      th: Name of the test harness board
-      dut: Name of the device under test board
-      module: Name of module to build/run tests for (e.g. gpio, interrupt)
-    """
-    self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module)
-    if os.path.isdir(self.results_dir):
-      shutil.rmtree(self.results_dir)
-    else:
-      os.makedirs(self.results_dir)
-    self.ec_dir = ec_dir
-    self.module = module
-    serial_path = os.path.join(CTS_TEST_RESULT_DIR, 'th_serial')
-    self.th = board.TestHarness(th, module, self.results_dir, serial_path)
-    self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir)
-    cts_dir = os.path.join(self.ec_dir, 'cts')
-    testlist_path = os.path.join(cts_dir, self.module, 'cts.testlist')
-    return_codes_path = os.path.join(cts_dir, 'common', 'cts.rc')
-    self.get_return_codes(return_codes_path)
-    self.testlist = self.get_macro_args(testlist_path, 'CTS_TEST')
-
-  def build(self):
-    """Build images for DUT and TH."""
-    print('Building DUT image...')
-    if not self.dut.build(self.ec_dir):
-      raise RuntimeError('Building module %s for DUT failed' % (self.module))
-    print('Building TH image...')
-    if not self.th.build(self.ec_dir):
-      raise RuntimeError('Building module %s for TH failed' % (self.module))
-
-  def flash_boards(self):
-    """Flashes TH and DUT with their most recently built ec.bin."""
-    cts_module = 'cts_' + self.module
-    image_path = os.path.join('build', self.th.board, cts_module, 'ec.bin')
-    self.identify_boards()
-    print('Flashing TH with', image_path)
-    if not self.th.flash(image_path):
-      raise RuntimeError('Flashing TH failed')
-    image_path = os.path.join('build', self.dut.board, cts_module, 'ec.bin')
-    print('Flashing DUT with', image_path)
-    if not self.dut.flash(image_path):
-      raise RuntimeError('Flashing DUT failed')
-
-  def setup(self):
-    """Setup boards."""
-    self.th.save_serial()
-
-  def identify_boards(self):
-    """Updates serials of TH and DUT in that order (order matters)."""
-    self.th.get_serial()
-    self.dut.get_serial()
-
-  def get_macro_args(self, filepath, macro):
-    """Get list of args of a macro in a file when macro.
-
-    Args:
-      filepath: String containing absolute path to the file
-      macro: String containing text of macro to get args of
-
-    Returns:
-      List of dictionaries where each entry is:
-        'name': Test name,
-        'th_string': Expected string from TH,
-        'dut_string': Expected string from DUT,
-    """
-    tests = []
-    with open(filepath, 'r') as f:
-      lines = f.readlines()
-      joined = ''.join(lines).replace('\\\n', '').splitlines()
-      for l in joined:
-        if not l.strip().startswith(macro):
-          continue
-        d = {}
-        l = l.strip()[len(macro):]
-        l = l.strip('()').split(',')
-        d['name'] = l[0].strip()
-        d['th_rc'] = self.get_return_code_value(l[1].strip().strip('"'))
-        d['th_string'] = l[2].strip().strip('"')
-        d['dut_rc'] = self.get_return_code_value(l[3].strip().strip('"'))
-        d['dut_string'] = l[4].strip().strip('"')
-        tests.append(d)
-    return tests
-
-  def get_return_codes(self, filepath):
-    """Read return code names from the return code definition file."""
-    self.return_codes = {}
-    val = 0
-    with open(filepath, 'r') as f:
-      for line in f:
-        line = line.strip()
-        if not line.startswith(CTS_RC_PREFIX):
-          continue
-        line = line.split(',')[0]
-        if '=' in line:
-          tokens = line.split('=')
-          line = tokens[0].strip()
-          val = int(tokens[1].strip())
-        self.return_codes[line] = val
-        val += 1
-
-  def parse_output(self, output):
-    """Parse console output from DUT or TH.
-
-    Args:
-      output: String containing consoule output
-
-    Returns:
-      List of dictionaries where each key and value are:
-        name = 'ects_test_x',
-        started = True/False,
-        ended = True/False,
-        rc = CTS_RC_*,
-        output = All text between 'ects_test_x start' and 'ects_test_x end'
-    """
-    results = []
-    i = 0
-    for test in self.testlist:
-      results.append({})
-      results[i]['name'] = test['name']
-      results[i]['started'] = False
-      results[i]['rc'] = CTS_RC_DID_NOT_START
-      results[i]['string'] = False
-      results[i]['output'] = []
-      i += 1
-
-    i = 0
-    for ln in [ln.strip() for ln in output.split('\n')]:
-      if i + 1 > len(results):
-        break
-      tokens = ln.split()
-      if len(tokens) >= 2:
-        if tokens[0].strip() == results[i]['name']:
-          if tokens[1].strip() == 'start':
-            # start line found
-            if results[i]['started']:   # Already started
-              results[i]['rc'] = CTS_RC_DUPLICATE_RUN
-            else:
-              results[i]['rc'] = CTS_RC_DID_NOT_END
-              results[i]['started'] = True
-            continue
-          elif results[i]['started'] and tokens[1].strip() == 'end':
-            # end line found
-            results[i]['rc'] = CTS_RC_INVALID_RETURN_CODE
-            if len(tokens) == 3:
-              try:
-                results[i]['rc'] = int(tokens[2].strip())
-              except ValueError:
-                pass
-            # Since index is incremented when 'end' is encountered, we don't
-            # need to check duplicate 'end'.
-            i += 1
-            continue
-      if results[i]['started']:
-        results[i]['output'].append(ln)
-
-    return results
-
-  def get_return_code_name(self, code, strip_prefix=False):
-    name = ''
-    for k, v in self.return_codes.items():
-      if v == code:
-        if strip_prefix:
-          name = k[len(CTS_RC_PREFIX):]
-        else:
-          name = k
-    return name
-
-  def get_return_code_value(self, name):
-    if name:
-      return self.return_codes[name]
-    return  0
-
-  def evaluate_run(self, dut_output, th_output):
-    """Parse outputs to derive test results.
-
-    Args:
-      dut_output: String output of DUT
-      th_output: String output of TH
-
-    Returns:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    th_results = self.parse_output(th_output)
-    dut_results = self.parse_output(dut_output)
-
-    # Search for expected string in each output
-    for i, v in enumerate(self.testlist):
-      if v['th_string'] in th_results[i]['output'] or not v['th_string']:
-        th_results[i]['string'] = True
-      if v['dut_string'] in dut_results[i]['output'] or not v['dut_string']:
-        dut_results[i]['string'] = True
-
-    return th_results, dut_results
-
-  def print_result(self, th_results, dut_results):
-    """Print results to the screen.
-
-    Args:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    len_test_name = max(len(s['name']) for s in self.testlist)
-    len_code_name = max(len(self.get_return_code_name(v, True))
-                        for v in self.return_codes.values())
-
-    head = '{:^' + str(len_test_name) + '} '
-    head += '{:^' + str(len_code_name) + '} '
-    head += '{:^' + str(len_code_name) + '}'
-    head += '{:^' + str(len(' TH_STR')) + '}'
-    head += '{:^' + str(len(' DUT_STR')) + '}'
-    head += '{:^' + str(len(' RESULT')) + '}\n'
-    fmt = '{:' + str(len_test_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '}'
-    fmt += '{:>' + str(len(' TH_STR')) + '}'
-    fmt += '{:>' + str(len(' DUT_STR')) + '}'
-    fmt += '{:>' + str(len(' RESULT')) + '}\n'
-
-    self.formatted_results = head.format(
-        'TEST NAME', 'TH_RC', 'DUT_RC',
-        ' TH_STR', ' DUT_STR', ' RESULT')
-    for i, d in enumerate(dut_results):
-      th_cn = self.get_return_code_name(th_results[i]['rc'], True)
-      dut_cn = self.get_return_code_name(dut_results[i]['rc'], True)
-      th_res = self.evaluate_result(th_results[i],
-                                    self.testlist[i]['th_rc'],
-                                    self.testlist[i]['th_string'])
-      dut_res = self.evaluate_result(dut_results[i],
-                                     self.testlist[i]['dut_rc'],
-                                     self.testlist[i]['dut_string'])
-      self.formatted_results += fmt.format(
-          d['name'], th_cn, dut_cn,
-          'YES' if th_results[i]['string'] else 'NO',
-          'YES' if dut_results[i]['string'] else 'NO',
-          'PASS' if th_res and dut_res else 'FAIL')
-
-  def evaluate_result(self, result, expected_rc, expected_string):
-    if result['rc'] != expected_rc:
-      return False
-    if expected_string and expected_string not in result['output']:
-      return False
-    return True
-
-  def run(self):
-    """Resets boards, records test results in results dir."""
-    print('Reading serials...')
-    self.identify_boards()
-    print('Opening DUT tty...')
-    self.dut.setup_tty()
-    print('Opening TH tty...')
-    self.th.setup_tty()
-
-    # Boards might be still writing to tty. Wait a few seconds before flashing.
-    time.sleep(3)
-
-    # clear buffers
-    print('Clearing DUT tty...')
-    self.dut.read_tty()
-    print('Clearing TH tty...')
-    self.th.read_tty()
-
-    # Resets the boards and allows them to run tests
-    # Due to current (7/27/16) version of sync function,
-    # both boards must be rest and halted, with the th
-    # resuming first, in order for the test suite to run in sync
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-    print('Resuming TH...')
-    if not self.th.resume():
-      raise RuntimeError('Failed to resume TH')
-    print('Resuming DUT...')
-    if not self.dut.resume():
-      raise RuntimeError('Failed to resume DUT')
-
-    time.sleep(MAX_SUITE_TIME_SEC)
-
-    print('Reading DUT tty...')
-    dut_output, _ = self.dut.read_tty()
-    self.dut.close_tty()
-    print('Reading TH tty...')
-    th_output, _ = self.th.read_tty()
-    self.th.close_tty()
-
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-
-    if not dut_output or not th_output:
-      raise ValueError('Output missing from boards. If you have a process '
-                       'reading ttyACMx, please kill that process and try '
-                       'again.')
-
-      print('Pursing results...')
-    th_results, dut_results = self.evaluate_run(dut_output, th_output)
-
-    # Print out results
-    self.print_result(th_results, dut_results)
-
-    # Write results
-    dest = os.path.join(self.results_dir, 'results.log')
-    with open(dest, 'w') as fl:
-      fl.write(self.formatted_results)
-
-    # Write UART outputs
-    dest = os.path.join(self.results_dir, 'uart_th.log')
-    with open(dest, 'w') as fl:
-      fl.write(th_output)
-    dest = os.path.join(self.results_dir, 'uart_dut.log')
-    with open(dest, 'w') as fl:
-      fl.write(dut_output)
-
-    print(self.formatted_results)
-
-    # TODO(chromium:735652): Should set exit code for the shell
-
-
-def main():
-  ec_dir = os.path.realpath(os.path.join(
-      os.path.dirname(os.path.abspath(__file__)), '..'))
-  os.chdir(ec_dir)
-
-  dut = DEFAULT_DUT
-  module = 'meta'
-
-  parser = argparse.ArgumentParser(description='Used to build/flash boards')
-  parser.add_argument('-d',
-                      '--dut',
-                      help='Specify DUT you want to build/flash')
-  parser.add_argument('-m',
-                      '--module',
-                      help='Specify module you want to build/flash')
-  parser.add_argument('-s',
-                      '--setup',
-                      action='store_true',
-                      help='Connect only the TH to save its serial')
-  parser.add_argument('-b',
-                      '--build',
-                      action='store_true',
-                      help='Build test suite (no flashing)')
-  parser.add_argument('-f',
-                      '--flash',
-                      action='store_true',
-                      help='Flash boards with most recent images')
-  parser.add_argument('-r',
-                      '--run',
-                      action='store_true',
-                      help='Run tests without flashing')
-
-  args = parser.parse_args()
-
-  if args.module:
-    module = args.module
-
-  if args.dut:
-    dut = args.dut
-
-  cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module)
-
-  if args.setup:
-    cts.setup()
-  elif args.build:
-    cts.build()
-  elif args.flash:
-    cts.flash_boards()
-  elif args.run:
-    cts.run()
-  else:
-    cts.build()
-    cts.flash_boards()
-    cts.run()
-
-if __name__ == '__main__':
-  main()
diff --git a/cts/cts.tasklist b/cts/cts.tasklist
deleted file mode 100644
index 152b0d02b2..0000000000
--- a/cts/cts.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-
-/* Default task list for suites which don't define its own */
-#define CONFIG_CTS_TASK_LIST \
-	TASK_ALWAYS(CTS, cts_task, NULL, TASK_STACK_SIZE)
diff --git a/cts/gpio/cts.testlist b/cts/gpio/cts.testlist
deleted file mode 100644
index 113d2b405f..0000000000
--- a/cts/gpio/cts.testlist
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Test whether sync completes successfully */
-CTS_TEST(sync_test,,,,)
-
-/* Check if the dut can set a line low */
-CTS_TEST(set_low_test,,,,)
-
-/* Check if the dut can set a line high */
-CTS_TEST(set_high_test,,,,)
-
-/* Check if the dut can read a line that is low */
-CTS_TEST(read_high_test,,,,)
-
-/* Check if the dut can read a line that is high */
-CTS_TEST(read_low_test,,,,)
-
-/* Check if the dut reads its true pin level (success)
-   or its register level when configured as a low open drain output pin */
-CTS_TEST(od_read_high_test,,,,)
diff --git a/cts/gpio/dut.c b/cts/gpio/dut.c
deleted file mode 100644
index 828996db8e..0000000000
--- a/cts/gpio/dut.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "watchdog.h"
-#include "uart.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-#include "cts_common.h"
-
-enum cts_rc sync_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc set_high_test(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
-	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc set_low_test(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
-	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read_high_test(void)
-{
-	int level;
-
-	gpio_set_flags(GPIO_INPUT_TEST, GPIO_INPUT | GPIO_PULL_UP);
-	msleep(READ_WAIT_TIME_MS);
-	level = gpio_get_level(GPIO_INPUT_TEST);
-	if (level)
-		return CTS_RC_SUCCESS;
-	else
-		return CTS_RC_FAILURE;
-}
-
-enum cts_rc read_low_test(void)
-{
-	int level;
-
-	gpio_set_flags(GPIO_INPUT_TEST, GPIO_INPUT | GPIO_PULL_UP);
-	msleep(READ_WAIT_TIME_MS);
-	level = gpio_get_level(GPIO_INPUT_TEST);
-	if (!level)
-		return CTS_RC_SUCCESS;
-	else
-		return CTS_RC_FAILURE;
-}
-
-enum cts_rc od_read_high_test(void)
-{
-	int level;
-
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_HIGH | GPIO_PULL_UP);
-	msleep(READ_WAIT_TIME_MS);
-	level = gpio_get_level(GPIO_OUTPUT_TEST);
-	if (!level)
-		return CTS_RC_SUCCESS;
-	else
-		return CTS_RC_FAILURE;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "GPIO");
-	task_wait_event(-1);
-}
diff --git a/cts/gpio/th.c b/cts/gpio/th.c
deleted file mode 100644
index 6c628b0ad5..0000000000
--- a/cts/gpio/th.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "watchdog.h"
-#include "uart.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-#include "cts_common.h"
-
-enum cts_rc sync_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc set_high_test(void)
-{
-	int level;
-
-	gpio_set_flags(GPIO_INPUT_TEST, GPIO_INPUT | GPIO_PULL_UP);
-	msleep(READ_WAIT_TIME_MS);
-	level = gpio_get_level(GPIO_INPUT_TEST);
-	if (level)
-		return CTS_RC_SUCCESS;
-	else
-		return CTS_RC_FAILURE;
-}
-
-enum cts_rc set_low_test(void)
-{
-	int level;
-
-	gpio_set_flags(GPIO_INPUT_TEST, GPIO_INPUT | GPIO_PULL_UP);
-	msleep(READ_WAIT_TIME_MS);
-	level = gpio_get_level(GPIO_INPUT_TEST);
-	if (!level)
-		return CTS_RC_SUCCESS;
-	else
-		return CTS_RC_FAILURE;
-}
-
-enum cts_rc read_high_test(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
-	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read_low_test(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
-	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc od_read_high_test(void)
-{
-	gpio_set_flags(GPIO_INPUT_TEST, GPIO_OUTPUT | GPIO_ODR_LOW);
-	msleep(READ_WAIT_TIME_MS*2);
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "GPIO");
-	task_wait_event(-1);
-}
diff --git a/cts/hook/cts.testlist b/cts/hook/cts.testlist
deleted file mode 100644
index 97b25575d4..0000000000
--- a/cts/hook/cts.testlist
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test HOOK_INIT
- */
-CTS_TEST(test_init_hook,,,,)
-
-/*
- * Test HOOK_TICK and HOOK_SECOND
- */
-CTS_TEST(test_ticks,,,,)
-
-/*
- * Test hook priority
- */ 
-CTS_TEST(test_priority,,,,)
-
-/*
- * Test deferred calls
- */
-CTS_TEST(test_deferred,,,,)
\ No newline at end of file
diff --git a/cts/hook/dut.c b/cts/hook/dut.c
deleted file mode 100644
index f3a52ddaf4..0000000000
--- a/cts/hook/dut.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test hooks.
- */
-
-#include "common.h"
-#include "console.h"
-#include "cts_common.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-static int init_hook_count;
-static int tick_hook_count;
-static int tick2_hook_count;
-static int tick_count_seen_by_tick2;
-static timestamp_t tick_time[2];
-static int second_hook_count;
-static timestamp_t second_time[2];
-static int deferred_call_count;
-
-static void init_hook(void)
-{
-	init_hook_count++;
-}
-DECLARE_HOOK(HOOK_INIT, init_hook, HOOK_PRIO_DEFAULT);
-
-static void tick_hook(void)
-{
-	tick_hook_count++;
-	tick_time[0] = tick_time[1];
-	tick_time[1] = get_time();
-}
-DECLARE_HOOK(HOOK_TICK, tick_hook, HOOK_PRIO_DEFAULT);
-
-static void tick2_hook(void)
-{
-	tick2_hook_count++;
-	tick_count_seen_by_tick2 = tick_hook_count;
-}
-/* tick2_hook() prio means it should be called after tick_hook() */
-DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1);
-
-static void second_hook(void)
-{
-	second_hook_count++;
-	second_time[0] = second_time[1];
-	second_time[1] = get_time();
-}
-DECLARE_HOOK(HOOK_SECOND, second_hook, HOOK_PRIO_DEFAULT);
-
-static void deferred_func(void)
-{
-	deferred_call_count++;
-}
-DECLARE_DEFERRED(deferred_func);
-
-static void invalid_deferred_func(void)
-{
-	deferred_call_count++;
-}
-
-static const struct deferred_data invalid_deferred_func_data = {
-	invalid_deferred_func
-};
-
-static enum cts_rc test_init_hook(void)
-{
-	if (init_hook_count != 1)
-		return CTS_RC_FAILURE;
-	return CTS_RC_SUCCESS;
-}
-
-static enum cts_rc test_ticks(void)
-{
-	int64_t interval;
-	int error_pct;
-
-	/*
-	 * HOOK_SECOND must have been fired at least once when HOOK
-	 * task starts. We only need to wait for just more than a second
-	 * to allow it fires for the second time.
-	 */
-	msleep(1300);
-
-	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
-	if (error_pct < -10 || 10 < error_pct) {
-		CPRINTS("tick error=%d%% interval=%lld", error_pct, interval);
-		return CTS_RC_FAILURE;
-	}
-
-	interval = second_time[1].val - second_time[0].val;
-	error_pct = (interval - SECOND) * 100 / SECOND;
-	if (error_pct < -10 || 10 < error_pct) {
-		CPRINTS("second error=%d%% interval=%lld", error_pct, interval);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-static enum cts_rc test_priority(void)
-{
-	usleep(HOOK_TICK_INTERVAL);
-	if (tick_hook_count != tick2_hook_count)
-		return CTS_RC_FAILURE;
-	if (tick_hook_count != tick_count_seen_by_tick2)
-		return CTS_RC_FAILURE;
-	return CTS_RC_SUCCESS;
-}
-
-static enum cts_rc test_deferred(void)
-{
-	deferred_call_count = 0;
-	hook_call_deferred(&deferred_func_data, 50 * MSEC);
-	if (deferred_call_count != 0) {
-		CPRINTL("deferred_call_count=%d", deferred_call_count);
-		return CTS_RC_FAILURE;
-	}
-	msleep(100);
-	if (deferred_call_count != 1) {
-		CPRINTL("deferred_call_count=%d", deferred_call_count);
-		return CTS_RC_FAILURE;
-	}
-
-	/* Test cancellation */
-	deferred_call_count = 0;
-	hook_call_deferred(&deferred_func_data, 50 * MSEC);
-	msleep(25);
-	hook_call_deferred(&deferred_func_data, -1);
-	msleep(75);
-	if (deferred_call_count != 0) {
-		CPRINTL("deferred_call_count=%d", deferred_call_count);
-		return CTS_RC_FAILURE;
-	}
-
-	/* Invalid deferred function */
-	deferred_call_count = 0;
-	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC)
-			== EC_SUCCESS) {
-		CPRINTL("non_deferred_func_data");
-		return CTS_RC_FAILURE;
-	}
-	msleep(100);
-	if (deferred_call_count != 0) {
-		CPRINTL("deferred_call_count=%d", deferred_call_count);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "Hook");
-	task_wait_event(-1);
-}
diff --git a/cts/hook/th.c b/cts/hook/th.c
deleted file mode 120000
index 41eab28462..0000000000
--- a/cts/hook/th.c
+++ /dev/null
@@ -1 +0,0 @@
-dut.c
\ No newline at end of file
diff --git a/cts/i2c/cts.testlist b/cts/i2c/cts.testlist
deleted file mode 100644
index 7b6461e84d..0000000000
--- a/cts/i2c/cts.testlist
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test i2c write for 8, 16, and 32 bits. DUT runs as a master and TH
- * runs as a slave.
- */
-CTS_TEST(write8_test,,,,)
-CTS_TEST(write16_test,,,,)
-CTS_TEST(write32_test,,,,)
-
-/*
- * Test i2c read for 8, 16, and 32 bits. DUT runs as a master and TH
- * runs as a slave. You need external pull-ups (10 kohms) on SDL and SDA
- * to make read16_test and read32_test pass.
- */
-CTS_TEST(read8_test,,,,)
-CTS_TEST(read16_test,,,,)
-CTS_TEST(read32_test,,,,)
\ No newline at end of file
diff --git a/cts/i2c/cts_i2c.h b/cts/i2c/cts_i2c.h
deleted file mode 100644
index 2914d92a99..0000000000
--- a/cts/i2c/cts_i2c.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-enum cts_i2c_packets {
-	WRITE8_OFF,
-	WRITE16_OFF,
-	WRITE32_OFF,
-	READ8_OFF,
-	READ16_OFF,
-	READ32_OFF,
-};
-
-#define WRITE8_DATA	0x42
-#define WRITE16_DATA	0x1234
-#define WRITE32_DATA	0xDEADBEEF
-#define READ8_DATA	0x23
-#define READ16_DATA	0xACED
-#define READ32_DATA	0x01ABCDEF
diff --git a/cts/i2c/dut.c b/cts/i2c/dut.c
deleted file mode 100644
index c7a3f9fccf..0000000000
--- a/cts/i2c/dut.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "cts_i2c.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "watchdog.h"
-
-#define TH_ADDR_FLAGS 0x1e
-
-enum cts_rc write8_test(void)
-{
-	if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       WRITE8_OFF, WRITE8_DATA))
-		return CTS_RC_FAILURE;
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc write16_test(void)
-{
-	if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE16_OFF, WRITE16_DATA))
-		return CTS_RC_FAILURE;
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc write32_test(void)
-{
-	if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE32_OFF, WRITE32_DATA))
-		return CTS_RC_FAILURE;
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read8_test(void)
-{
-	int data;
-
-	if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		      READ8_OFF, &data))
-		return CTS_RC_FAILURE;
-	if (data != READ8_DATA) {
-		CPRINTL("Expecting 0x%x but read 0x%x", READ8_DATA, data);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read16_test(void)
-{
-	int data;
-
-	if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ16_OFF, &data))
-		return CTS_RC_FAILURE;
-	if (data != READ16_DATA) {
-		CPRINTL("Expecting 0x%x but read 0x%x", READ16_DATA, data);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read32_test(void)
-{
-	int data;
-
-	if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ32_OFF, &data))
-		return CTS_RC_FAILURE;
-	if (data != READ32_DATA) {
-		CPRINTL("Read 0x%x expecting 0x%x", data, READ32_DATA);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "I2C");
-	task_wait_event(-1);
-}
diff --git a/cts/i2c/th.c b/cts/i2c/th.c
deleted file mode 100644
index 78035cb1b2..0000000000
--- a/cts/i2c/th.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <string.h>
-#include "common.h"
-#include "cts_common.h"
-#include "cts_i2c.h"
-#include "i2c.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "watchdog.h"
-
-static uint8_t inbox[I2C_MAX_HOST_PACKET_SIZE + 2];
-static char data_received;
-
-void i2c_data_received(int port, uint8_t *buf, int len)
-{
-	memcpy(inbox, buf, len);
-	data_received = 1;
-}
-
-/* CTS I2C protocol implementation */
-int i2c_set_response(int port, uint8_t *buf, int len)
-{
-	switch (buf[0]) {
-	case READ8_OFF:
-		buf[0] = READ8_DATA;
-		return 1;
-	case READ16_OFF:
-		buf[0] = READ16_DATA & 0xFF;
-		buf[1] = (READ16_DATA >> 8) & 0xFF;
-		return 2;
-	case READ32_OFF:
-		buf[0] = READ32_DATA & 0xFF;
-		buf[1] = (READ32_DATA >> 8) & 0xFF;
-		buf[2] = (READ32_DATA >> 16) & 0xFF;
-		buf[3] = (READ32_DATA >> 24) & 0xFF;
-		return 4;
-	default:
-		return 0;
-	}
-}
-
-static int wait_for_in_flag(uint32_t timeout_ms)
-{
-	uint64_t start_time, end_time;
-
-	start_time = get_time().val;
-	end_time = start_time + timeout_ms * 1000;
-
-	while (get_time().val < end_time) {
-		if (data_received)
-			return 0;
-		msleep(5);
-		watchdog_reload();
-	}
-	return 1;
-}
-
-void clean_state(void)
-{
-	memset(inbox, 0, sizeof(inbox));
-	data_received = 0;
-}
-
-enum cts_rc write8_test(void)
-{
-	int in;
-
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != WRITE8_OFF)
-		return CTS_RC_FAILURE;
-	in = inbox[1];
-	if (in != WRITE8_DATA)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc write16_test(void)
-{
-	int in;
-
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != WRITE16_OFF)
-		return CTS_RC_FAILURE;
-	in = inbox[2] << 8 | inbox[1] << 0;
-	if (in != WRITE16_DATA)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc write32_test(void)
-{
-	int in;
-
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != WRITE32_OFF)
-		return CTS_RC_FAILURE;
-	in = inbox[4] << 24 | inbox[3] << 16 | inbox[2] << 8 | inbox[1];
-	if (in != WRITE32_DATA)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read8_test(void)
-{
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != READ8_OFF)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read16_test(void)
-{
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != READ16_OFF)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc read32_test(void)
-{
-	if (wait_for_in_flag(100))
-		return CTS_RC_TIMEOUT;
-	if (inbox[0] != READ32_OFF)
-		return CTS_RC_FAILURE;
-
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "I2C");
-	task_wait_event(-1);
-}
diff --git a/cts/interrupt/cts.testlist b/cts/interrupt/cts.testlist
deleted file mode 100644
index 0fdaf6fca2..0000000000
--- a/cts/interrupt/cts.testlist
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Test interrupt_enable/disable */
-CTS_TEST(test_interrupt_enable,,,,)
-CTS_TEST(test_interrupt_disable,,,,)
-
-/* Test task_wait_for_event */
-CTS_TEST(test_task_wait_event,,,,)
-
-/* Test task_disable_irq */
-CTS_TEST(test_task_disable_irq,,,,)
-
-/* Test nested interrupt. Lower priority IRQ is fired, followed by
- * higher priority IRQ. Handler executions should be nested.
- *
- * P1                    *-----*
- *                      /       \
- * P2             *----*         *----*
- *               /                     \
- * task_cts ----*                       *----
- *                A      B     C      D
- */
-CTS_TEST(test_nested_interrupt_low_high,,,,)
-
-/* Test nested interrupt. Higher priority IRQ is fired, followed by
- * lower priority IRQ. Handlers should be executed sequentially.
- *
- * P1               *-----*
- *                 /       \
- * P2             /         *-----*
- *               /                 \
- * task_cts ----*                   *----
- *                  B     C A     D
- */
-CTS_TEST(test_nested_interrupt_high_low,,,,)
-
-/*
- * Other ideas
- *
- * Test back-to-back interrupts, NVIC, Priorities
- */
\ No newline at end of file
diff --git a/cts/interrupt/dut.c b/cts/interrupt/dut.c
deleted file mode 100644
index 3c83e5701f..0000000000
--- a/cts/interrupt/dut.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <string.h>
-#include "common.h"
-#include "cts_common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-static int got_interrupt;
-static int wake_me_up;
-static int state_index;
-static char state[4];
-
-/*
- * Raw busy loop. Returns 1 if loop finishes before interrupt is triggered.
- * Loop length is controlled by busy_loop_timeout. It has to be set to the
- * value which makes the loop last longer than CTS_INTERRUPT_TRIGGER_DELAY_US.
- */
-static int busy_loop(void)
-{
-	/* TODO: Derive a proper value from clock speed */
-	const uint32_t busy_loop_timeout = 0xfffff;
-	uint32_t counter = 0;
-
-	while (counter++ < busy_loop_timeout) {
-		if (got_interrupt)
-			break;
-		watchdog_reload();
-	}
-	if (counter > busy_loop_timeout)
-		return 1;
-
-	return 0;
-}
-
-/*
- * Interrupt handler.
- */
-void cts_irq1(enum gpio_signal signal)
-{
-	state[state_index++] = 'B';
-
-	got_interrupt = in_interrupt_context();
-
-	/* Wake up the CTS task */
-	if (wake_me_up)
-		task_wake(TASK_ID_CTS);
-
-	busy_loop();
-
-	state[state_index++] = 'C';
-}
-
-void cts_irq2(enum gpio_signal signal)
-{
-	state[state_index++] = 'A';
-	busy_loop();
-	state[state_index++] = 'D';
-}
-
-void clean_state(void)
-{
-	uint32_t *event;
-
-	interrupt_enable();
-	got_interrupt = 0;
-	wake_me_up = 0;
-	state_index = 0;
-	memset(state, '_', sizeof(state));
-	event = task_get_event_bitmap(TASK_ID_CTS);
-	*event = 0;
-}
-
-enum cts_rc test_task_wait_event(void)
-{
-	uint32_t event;
-
-	wake_me_up = 1;
-
-	/* Sleep and wait for interrupt. This shouldn't time out. */
-	event = task_wait_event(CTS_INTERRUPT_TRIGGER_DELAY_US * 2);
-	if (event != TASK_EVENT_WAKE) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-	if (!got_interrupt) {
-		CPRINTS("Interrupt context not detected");
-		return CTS_RC_TIMEOUT;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_task_disable_irq(void)
-{
-	uint32_t event;
-
-	wake_me_up = 1;
-
-	task_disable_irq(CTS_IRQ_NUMBER);
-	/* Sleep and wait for interrupt. This should time out. */
-	event = task_wait_event(CTS_INTERRUPT_TRIGGER_DELAY_US * 2);
-	if (event != TASK_EVENT_TIMER) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-	task_enable_irq(CTS_IRQ_NUMBER);
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_interrupt_enable(void)
-{
-	if (busy_loop()) {
-		CPRINTS("Timeout before interrupt");
-		return CTS_RC_TIMEOUT;
-	}
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_interrupt_disable(void)
-{
-	interrupt_disable();
-	if (!busy_loop()) {
-		CPRINTS("Expected timeout but didn't");
-		return CTS_RC_FAILURE;
-	}
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_nested_interrupt_low_high(void)
-{
-	uint32_t event;
-
-	event = task_wait_event(CTS_INTERRUPT_TRIGGER_DELAY_US * 4);
-	if (event != TASK_EVENT_TIMER) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-	if (!got_interrupt) {
-		CPRINTS("Interrupt context not detected");
-		return CTS_RC_TIMEOUT;
-	}
-	if (memcmp(state, "ABCD", sizeof(state))) {
-		CPRINTS("State transition differs from expectation");
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_nested_interrupt_high_low(void)
-{
-	uint32_t event;
-
-	event = task_wait_event(CTS_INTERRUPT_TRIGGER_DELAY_US * 4);
-	if (event != TASK_EVENT_TIMER) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-
-	if (memcmp(state, "BCAD", sizeof(state))) {
-		CPRINTS("State transition differs from expectation");
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	gpio_enable_interrupt(GPIO_CTS_IRQ1);
-	gpio_enable_interrupt(GPIO_CTS_IRQ2);
-	cts_main_loop(tests, "Interrupt");
-	task_wait_event(-1);
-}
diff --git a/cts/interrupt/th.c b/cts/interrupt/th.c
deleted file mode 100644
index 1639a1868c..0000000000
--- a/cts/interrupt/th.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "gpio.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-void clean_state(void)
-{
-	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	gpio_set_level(GPIO_CTS_IRQ2, 1);
-}
-
-static void trigger_interrupt1(void)
-{
-	usleep(CTS_INTERRUPT_TRIGGER_DELAY_US);
-	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	usleep(CTS_INTERRUPT_TRIGGER_DELAY_US);
-}
-
-static void trigger_interrupt2(void)
-{
-	usleep(CTS_INTERRUPT_TRIGGER_DELAY_US);
-	gpio_set_level(GPIO_CTS_IRQ2, 0);
-	usleep(CTS_INTERRUPT_TRIGGER_DELAY_US);
-}
-
-enum cts_rc test_task_wait_event(void)
-{
-	trigger_interrupt1();
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_task_disable_irq(void)
-{
-	trigger_interrupt1();
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_interrupt_enable(void)
-{
-	trigger_interrupt1();
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_interrupt_disable(void)
-{
-	trigger_interrupt1();
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_nested_interrupt_low_high(void)
-{
-	trigger_interrupt2();
-	trigger_interrupt1();
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_nested_interrupt_high_low(void)
-{
-	trigger_interrupt1();
-	trigger_interrupt2();
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_HIGH);
-	cts_main_loop(tests, "Interrupt");
-	task_wait_event(-1);
-}
diff --git a/cts/meta/cts.testlist b/cts/meta/cts.testlist
deleted file mode 100644
index 28ac7e325f..0000000000
--- a/cts/meta/cts.testlist
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test SUCCESS from both TH and DUT
- */
-CTS_TEST(success_test,,,,)
-
-/*
- * Test FAILURE from DUT
- */
-CTS_TEST(fail_dut_test,,, CTS_RC_FAILURE,)
-
-/*
- * Test FAILURE from TH
- */
-CTS_TEST(fail_th_test, CTS_RC_FAILURE,,,)
-
-/*
- * Test failure from both TH and DUT.
- */
-CTS_TEST(fail_both_test, CTS_RC_FAILURE,, CTS_RC_FAILURE,)
-
-/*
- * Test bad sync for TH
- */
-CTS_TEST(bad_sync_test, CTS_RC_BAD_SYNC,,,)
-
-/*
- * Test should fail with bad sync.
- */
-CTS_TEST(bad_sync_both_test, CTS_RC_BAD_SYNC,, CTS_RC_BAD_SYNC,)
-
-/*
- * Test hang on DUT
- */
-CTS_TEST(hang_test, CTS_RC_SUCCESS,, CTS_RC_DID_NOT_END,)
-
-/*
- * Test CTS_RC_DID_NOT_START
- *
- * Since the previous test hung on DUT, this test won't run on DUT. 
- * TH will wait forever in sync(), thus won't end.
- */
- CTS_TEST(did_not_start_test, CTS_RC_DID_NOT_END,, CTS_RC_DID_NOT_START,)
-
-/*
- * TODO: Add test for expected string
- * TODO: Make sync() return CTS_RC_BAD_SYNC when it times out.
- */
\ No newline at end of file
diff --git a/cts/meta/dut.c b/cts/meta/dut.c
deleted file mode 100644
index c321676aec..0000000000
--- a/cts/meta/dut.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "watchdog.h"
-
-enum cts_rc success_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc fail_dut_test(void)
-{
-	return CTS_RC_FAILURE;
-}
-
-enum cts_rc fail_th_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc fail_both_test(void)
-{
-	return CTS_RC_FAILURE;
-}
-
-enum cts_rc bad_sync_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc bad_sync_both_test(void)
-{
-	return CTS_RC_BAD_SYNC;
-}
-
-enum cts_rc hang_test(void)
-{
-	while (1) {
-		watchdog_reload();
-		sleep(1);
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc did_not_start_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "Meta");
-	task_wait_event(-1);
-}
diff --git a/cts/meta/th.c b/cts/meta/th.c
deleted file mode 100644
index 57b2f492bd..0000000000
--- a/cts/meta/th.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "task.h"
-#include "timer.h"
-#include "uart.h"
-#include "watchdog.h"
-
-enum cts_rc success_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc fail_dut_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc fail_th_test(void)
-{
-	return CTS_RC_FAILURE;
-}
-
-enum cts_rc fail_both_test(void)
-{
-	return CTS_RC_FAILURE;
-}
-
-enum cts_rc bad_sync_test(void)
-{
-	return CTS_RC_BAD_SYNC;
-}
-
-enum cts_rc bad_sync_both_test(void)
-{
-	return CTS_RC_BAD_SYNC;
-}
-
-enum cts_rc hang_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc did_not_start_test(void)
-{
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "Meta");
-	task_wait_event(-1);
-}
diff --git a/cts/mutex/cts.tasklist b/cts/mutex/cts.tasklist
deleted file mode 100644
index 3387e1de09..0000000000
--- a/cts/mutex/cts.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_CTS_TASK_LIST \
-	TASK_ALWAYS(MTX3C, mutex_random_task, NULL, 384) \
-	TASK_ALWAYS(MTX3B, mutex_random_task, NULL, 384) \
-	TASK_ALWAYS(MTX3A, mutex_random_task, NULL, 384) \
-	TASK_ALWAYS(MTX2, mutex_second_task, NULL, 384) \
-	TASK_ALWAYS(CTS, cts_task, NULL, TASK_STACK_SIZE)
diff --git a/cts/mutex/cts.testlist b/cts/mutex/cts.testlist
deleted file mode 100644
index 5b1cdb1dae..0000000000
--- a/cts/mutex/cts.testlist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test mutex lock and unlock
- */
-CTS_TEST(lock_unlock_test,,,,)
\ No newline at end of file
diff --git a/cts/mutex/dut.c b/cts/mutex/dut.c
deleted file mode 100644
index 9cbbd8badb..0000000000
--- a/cts/mutex/dut.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- * Copyright 2011 Google Inc.
- *
- * Tasks for mutexes basic tests.
- */
-
-#include "console.h"
-#include "common.h"
-#include "cts_common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static struct mutex mtx;
-
-/* period between 50us and 3.2ms */
-#define PERIOD_US(num) (((num % 64) + 1) * 50)
-/* one of the 3 MTX3x tasks */
-#define RANDOM_TASK(num) (TASK_ID_MTX3C + (num % 3))
-
-int mutex_random_task(void *unused)
-{
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
-	/* wait to be activated */
-
-	while (1) {
-		task_wait_event(0);
-		ccprintf("%c+\n", letter);
-		mutex_lock(&mtx);
-		ccprintf("%c=\n", letter);
-		task_wait_event(0);
-		ccprintf("%c-\n", letter);
-		mutex_unlock(&mtx);
-	}
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-int mutex_second_task(void *unused)
-{
-	task_id_t id = task_get_current();
-
-	ccprintf("\n[Mutex second task %d]\n", id);
-
-	task_wait_event(0);
-	ccprintf("MTX2: locking...");
-	mutex_lock(&mtx);
-	ccprintf("done\n");
-	task_wake(TASK_ID_CTS);
-	ccprintf("MTX2: unlocking...\n");
-	mutex_unlock(&mtx);
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-static enum cts_rc lock_unlock_test(void)
-{
-	task_id_t id = task_get_current();
-	uint32_t rdelay = (uint32_t)0x0bad1dea;
-	uint32_t rtask = (uint32_t)0x1a4e1dea;
-	int i;
-
-	ccprintf("\n[Mutex main task %d]\n", id);
-
-	/* --- Lock/Unlock without contention --- */
-	ccprintf("No contention :");
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	ccprintf("done.\n");
-
-	/* --- Serialization to test simple contention --- */
-	ccprintf("Simple contention :\n");
-	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
-	task_wait_event(0);
-	/* block on the mutex */
-	ccprintf("MTX1: blocking...\n");
-	mutex_lock(&mtx);
-	ccprintf("MTX1: get lock\n");
-	mutex_unlock(&mtx);
-
-	/* --- mass lock-unlocking from several tasks --- */
-	ccprintf("Massive locking/unlocking :\n");
-	for (i = 0; i < 500; i++) {
-		/* Wake up a random task */
-		task_wake(RANDOM_TASK(rtask));
-		/* next pseudo random delay */
-		rtask = prng(rtask);
-		/* Wait for a "random" period */
-		task_wait_event(PERIOD_US(rdelay));
-		/* next pseudo random delay */
-		rdelay = prng(rdelay);
-	}
-
-	return EC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	wait_for_task_started();
-	cts_main_loop(tests, "Mutex");
-	task_wait_event(-1);
-}
diff --git a/cts/mutex/th.c b/cts/mutex/th.c
deleted file mode 100644
index 9cbbd8badb..0000000000
--- a/cts/mutex/th.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- * Copyright 2011 Google Inc.
- *
- * Tasks for mutexes basic tests.
- */
-
-#include "console.h"
-#include "common.h"
-#include "cts_common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static struct mutex mtx;
-
-/* period between 50us and 3.2ms */
-#define PERIOD_US(num) (((num % 64) + 1) * 50)
-/* one of the 3 MTX3x tasks */
-#define RANDOM_TASK(num) (TASK_ID_MTX3C + (num % 3))
-
-int mutex_random_task(void *unused)
-{
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
-	/* wait to be activated */
-
-	while (1) {
-		task_wait_event(0);
-		ccprintf("%c+\n", letter);
-		mutex_lock(&mtx);
-		ccprintf("%c=\n", letter);
-		task_wait_event(0);
-		ccprintf("%c-\n", letter);
-		mutex_unlock(&mtx);
-	}
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-int mutex_second_task(void *unused)
-{
-	task_id_t id = task_get_current();
-
-	ccprintf("\n[Mutex second task %d]\n", id);
-
-	task_wait_event(0);
-	ccprintf("MTX2: locking...");
-	mutex_lock(&mtx);
-	ccprintf("done\n");
-	task_wake(TASK_ID_CTS);
-	ccprintf("MTX2: unlocking...\n");
-	mutex_unlock(&mtx);
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-static enum cts_rc lock_unlock_test(void)
-{
-	task_id_t id = task_get_current();
-	uint32_t rdelay = (uint32_t)0x0bad1dea;
-	uint32_t rtask = (uint32_t)0x1a4e1dea;
-	int i;
-
-	ccprintf("\n[Mutex main task %d]\n", id);
-
-	/* --- Lock/Unlock without contention --- */
-	ccprintf("No contention :");
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	ccprintf("done.\n");
-
-	/* --- Serialization to test simple contention --- */
-	ccprintf("Simple contention :\n");
-	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
-	task_wait_event(0);
-	/* block on the mutex */
-	ccprintf("MTX1: blocking...\n");
-	mutex_lock(&mtx);
-	ccprintf("MTX1: get lock\n");
-	mutex_unlock(&mtx);
-
-	/* --- mass lock-unlocking from several tasks --- */
-	ccprintf("Massive locking/unlocking :\n");
-	for (i = 0; i < 500; i++) {
-		/* Wake up a random task */
-		task_wake(RANDOM_TASK(rtask));
-		/* next pseudo random delay */
-		rtask = prng(rtask);
-		/* Wait for a "random" period */
-		task_wait_event(PERIOD_US(rdelay));
-		/* next pseudo random delay */
-		rdelay = prng(rdelay);
-	}
-
-	return EC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	wait_for_task_started();
-	cts_main_loop(tests, "Mutex");
-	task_wait_event(-1);
-}
diff --git a/cts/task/cts.tasklist b/cts/task/cts.tasklist
deleted file mode 100644
index 6477d74c2c..0000000000
--- a/cts/task/cts.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_CTS_TASK_LIST \
-	TASK_ALWAYS(A, task_abc, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(B, task_abc, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(C, task_abc, NULL, TASK_STACK_SIZE) \
-	TASK_ALWAYS(TICK, task_tick, NULL, 256) \
-	TASK_ALWAYS(CTS, cts_task, NULL, TASK_STACK_SIZE)
diff --git a/cts/task/cts.testlist b/cts/task/cts.testlist
deleted file mode 100644
index c4b7bc3231..0000000000
--- a/cts/task/cts.testlist
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test task switching. Task A wakes up B and goes to sleep. Task B wakes
- * up C then goes to sleep. Task C wakes up A then goes to sleep. This is
- * repeated TEST_COUNT times. It's expected all tasks to run exactly
- * TEST_COUNT times. Tick task runs to inject some irregularity.
- */
-CTS_TEST(test_task_switch,,,,)
-
-/*
- * Test task priority. CTS task wakes up A and C then goes to sleep. Since C
- * has a higher priority, C should run first. This should result in C running
- * one more time than A (or B).
- */
-CTS_TEST(test_task_priority,,,,)
-
-/*
- * Test stack overflow. CTS task overflows the stack and it should be detected
- * when task switch happens. Reboot is expected.
- */
-CTS_TEST(test_stack_overflow,\
-	 CTS_RC_DID_NOT_END, "Stack overflow in CTS task!",\
-	 CTS_RC_DID_NOT_END, "Stack overflow in CTS task!")
diff --git a/cts/task/dut.c b/cts/task/dut.c
deleted file mode 100644
index 71fe4050ec..0000000000
--- a/cts/task/dut.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tasks for scheduling test.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "task.h"
-#include "timer.h"
-
-static int repeat_count;
-static int wake_count[3];
-
-void clean_state(void)
-{
-	wake_count[0] = wake_count[1] = wake_count[2] = 0;
-}
-
-void task_abc(void *data)
-{
-	int task_id = task_get_current();
-	int id = task_id - TASK_ID_A;
-	task_id_t next = task_id + 1;
-
-	if (next > TASK_ID_C)
-		next = TASK_ID_A;
-
-	task_wait_event(-1);
-
-	CPRINTS("%c Starting", 'A' + id);
-	cflush();
-
-	while (1) {
-		wake_count[id]++;
-		if (id == 2 && wake_count[id] == repeat_count) {
-			task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE);
-			task_wait_event(0);
-		} else {
-			task_set_event(next, TASK_EVENT_WAKE);
-			task_wait_event(0);
-		}
-	}
-}
-
-void task_tick(void *data)
-{
-	task_wait_event(-1);
-	ccprintf("\n[starting Task T]\n");
-
-	/* Wake up every tick */
-	while (1)
-		/* Wait for timer interrupt message */
-		usleep(3000);
-}
-
-enum cts_rc test_task_switch(void)
-{
-	uint32_t event;
-
-	repeat_count = 3000;
-
-	task_wake(TASK_ID_A);
-	event = task_wait_event(5 * SECOND);
-
-	if (event != TASK_EVENT_WAKE) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-
-	if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
-		return CTS_RC_FAILURE;
-	}
-
-	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
-		CPRINTS("Events are pending");
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-enum cts_rc test_task_priority(void)
-{
-	uint32_t event;
-
-	repeat_count = 2;
-
-	task_wake(TASK_ID_A);
-	task_wake(TASK_ID_C);
-
-	event = task_wait_event(5 * SECOND);
-
-	if (event != TASK_EVENT_WAKE) {
-		CPRINTS("Woken up by unexpected event: 0x%08x", event);
-		return CTS_RC_FAILURE;
-	}
-
-	if (wake_count[0] != repeat_count - 1
-			|| wake_count[1] != repeat_count - 1) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
-		return CTS_RC_FAILURE;
-	}
-
-	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
-		CPRINTS("Events are pending");
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-static void recurse(int x)
-{
-	CPRINTS("+%d", x);
-	msleep(1);
-	recurse(x + 1);
-	CPRINTS("-%d", x);
-}
-
-enum cts_rc test_stack_overflow(void)
-{
-	recurse(0);
-	return CTS_RC_FAILURE;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	task_wake(TASK_ID_TICK);
-	cts_main_loop(tests, "Task");
-	task_wait_event(-1);
-}
diff --git a/cts/task/th.c b/cts/task/th.c
deleted file mode 120000
index 41eab28462..0000000000
--- a/cts/task/th.c
+++ /dev/null
@@ -1 +0,0 @@
-dut.c
\ No newline at end of file
diff --git a/cts/timer/cts.testlist b/cts/timer/cts.testlist
deleted file mode 100644
index 9b5da0d6c9..0000000000
--- a/cts/timer/cts.testlist
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test timer accuracy
- *
- * After sync, DUT and TH start counting down one second. After one second,
- * DUT raises GPIO level, which triggers an interrupt on TH. TH determines
- * whether the test passes or not based on how much more or less time elapsed
- * than one second.
- *
- * Requirements:
- * - Sync connection
- * - GPIO_OUTPUT connection for sending notification from DUT
- * - Calibrated TH timer
- */
-CTS_TEST(timer_calibration_test,,,,)
diff --git a/cts/timer/dut.c b/cts/timer/dut.c
deleted file mode 100644
index 96d7c5a3cf..0000000000
--- a/cts/timer/dut.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "gpio.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-static enum cts_rc timer_calibration_test(void)
-{
-	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_HIGH);
-
-	sync();
-	sleep(1);
-	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "Timer");
-	task_wait_event(-1);
-}
diff --git a/cts/timer/th.c b/cts/timer/th.c
deleted file mode 100644
index e82cac71ab..0000000000
--- a/cts/timer/th.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "cts_common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * Interrupt handler
- *
- * DUT is supposed to trigger an interrupt when it's done counting down,
- * causing this function to be invoked.
- */
-void cts_irq(enum gpio_signal signal)
-{
-	/* Wake up the CTS task */
-	task_wake(TASK_ID_CTS);
-}
-
-static enum cts_rc timer_calibration_test(void)
-{
-	/* Error margin: +/-2 msec (0.2% for one second) */
-	const int32_t margin = 2 * MSEC;
-	int32_t elapsed, delta;
-	timestamp_t t0, t1;
-
-	gpio_enable_interrupt(GPIO_CTS_NOTIFY);
-	interrupt_enable();
-
-	sync();
-	t0 = get_time();
-	/* Wait for interrupt */
-	task_wait_event(-1);
-	t1 = get_time();
-
-	elapsed = (int32_t)(t1.val - t0.val);
-	delta = elapsed - SECOND;
-	if (delta < -margin) {
-		CPRINTS("DUT clock runs too fast: %+d usec", delta);
-		return CTS_RC_FAILURE;
-	}
-	if (margin < delta) {
-		CPRINTS("DUT clock runs too slow: %+d usec", delta);
-		return CTS_RC_FAILURE;
-	}
-
-	return CTS_RC_SUCCESS;
-}
-
-#include "cts_testlist.h"
-
-void cts_task(void)
-{
-	cts_main_loop(tests, "Timer");
-	task_wait_event(-1);
-}
diff --git a/docs/ap-ec-comm.md b/docs/ap-ec-comm.md
deleted file mode 100644
index 5cd6fd82d9..0000000000
--- a/docs/ap-ec-comm.md
+++ /dev/null
@@ -1,152 +0,0 @@
-# Application Processor to EC communication
-
-[TOC]
-
-## Overview
-
-The Application Processor (sometimes called the host) communicates with the EC
-by issuing *host commands*, which are identified by a command ID and version
-number, and then reading a response. When a host command is issued through
-`ectool`, two or three software components are involved:
-
-*   `ectool`, the user-space binary,
-*   normally the `cros-ec` Kernel driver, and
-*   the code on the EC itself. This can be thought of as two parts:
-    *   a chip-specific driver for the appropriate transport, and
-    *   the generic host command handling code (mostly in the
-        [host command task]).
-
-We'll go into detail of each of these, as well as the traffic on the wire, in
-the following sections.
-
-### `ectool`
-
-`ectool` contains wrapper functions for the host commands exposed by the EC,
-providing a CLI. They call one of the transport-specific `ec_command`
-implementations in the `util/comm-*.c` files to send and receive from the EC.
-
-### EC kernel driver
-
-In most cases, `ectool` communicates via the [`cros-ec` Kernel driver], rather
-than directly from userspace. It sends raw commands to the Kernel driver, which
-sends them on to the EC, bypassing a lot of the other Kernel driver
-functionality.
-
-There are other CrOS EC-related Kernel drivers, which use host commands to act
-as adapters to existing Linux APIs. For example, sensors from the EC are mapped
-to the Linux [Industrial I/O] system.
-
-### On the wire
-
-Now we come to the protocol itself. All transactions take this general form:
-
-*   Host writes the request packet, consisting of:
-    *   a transport-specific header;
-    *   a `struct ec_host_request` containing the command ID, data length, and a
-        checksum; and
-    *   zero or more bytes of parameters for the command, the format of which
-        depends on the command.
-*   Host reads the response to its request, consisting of:
-    *   a transport-specific header;
-    *   a `struct ec_host_response` containing the result code, data length, and
-        a checksum; and
-    *   zero or more bytes of response from the command, again with a
-        command-specific format.
-
-### On the EC
-
-The host packet is received on the EC by some chip-specific code which checks
-its transport-specific header, then passes it on to the common host command
-code, starting at `host_packet_receive`. The common code validates the packet
-and then sends it on to the handler function (annotated with the
-`DECLARE_HOST_COMMAND` macro), which runs in the `HOSTCMD` task. The handler can
-set a response by modifying its arguments struct, which is sent back to the host
-via the chip-specific code.
-
-While this is happening, the EC needs to indicate to the host that it is busy
-processing and not yet ready to give a response. How it does this depends on the
-transport method used (see [Transport-specific details] below).
-
-## Versions
-
-There are two different concepts of "version" involved in host commands: version
-of the overarching protocol, and versions of individual commands.
-
-### Protocol versions
-
-There have been three protocol versions so far, and this document describes
-version 3. Version 1 was superseded by 2 before it shipped, so no devices use it
-anymore. Version 2 is generally deprecated, but you might still encounter it
-occasionally.
-
-Which version is in use can be determined using the `EC_CMD_GET_PROTOCOL_INFO`
-command. This was only introduced in version 3, however, so if errors,
-`EC_CMD_HELLO` should be sent in version 2. If the hello command succeeds, the
-EC speaks version 2.
-
-### Command versions
-
-Individual commands also have versions, independent of the protocol version
-they're being called with. Different versions of a command may have different
-parameter or response formats. `EC_CMD_GET_CMD_VERSIONS` returns the versions of
-the given command supported by the EC. These version numbers start at 0.
-
-## Transport-specific details
-
-Although the command and response formats are the same across all transports,
-some details of how they are transmitted differ, which may be of interest when
-implementing the EC side of the protocol on a new chip.
-
-### I<sup>2</sup>C
-
-I<sup>2</sup>C is very flexible with its timing, so when the EC receives a
-packet from the host, it should stretch the clock, holding it low until it is
-ready for the host to read the response.
-
-If the host tries to read more bytes than were in the response, the EC should
-respond with an obvious filler byte (such as 0xEC). For example, if a command
-that normally returns 50 bytes errors, its response will only be 8 bytes (the
-size of the response struct). The host will probably try to read 50 bytes
-anyway, so the EC should send the 8 bytes of the struct followed by 42 copies of
-the filler byte.
-
-### SPI
-
-The SPI bus is similar to I<sup>2</sup>C, but with two major exceptions. First,
-there's a minimum speed on the SPI bus. If slave devices don't respond quickly
-enough, the master will assume they're broken and give up. Second, every
-transaction is bidirectional. When bits are being clocked from master to slave
-on the MOSI line, the master will simultaneously read bits in the other
-direction on the MISO line.
-
-Hardware devices can usually handle this, and often some hardware-based flow
-control used to "stretch" the transaction by a bit or byte if the slave device
-needs a little extra time to respond to the master's demands.
-
-When exchanging messages with the EC on the SPI bus, the EC's host commands are
-communicated using our own software flow-control scheme, because most of the
-embedded controllers either aren't fast enough or don't have any support for
-hardware flow-control.
-
-It works like this: When the AP sends a byte to the EC, if the EC doesn't have a
-response queued up in advance, a default byte is returned. The EC preconfigures
-that default response byte to indicate its status (ready, busy, waiting for more
-input, etc.). Once the AP has sent a complete command message, it continues
-clocking bytes to the EC (which the EC ignores) and just looks at the response
-byte that comes back. Once the EC has parsed the AP's command and is ready to
-reply, it sends a "start of frame" byte, followed by the actual response. The AP
-continues to read and ignore bytes from the EC until it sees the start of frame
-byte, and then it knows that the EC's response is starting with the next byte.
-
-Once the response packet has been read, any additional reads should return
-`EC_SPI_PAST_END`.
-
-### LPC or eSPI
-
-The EC should set `EC_LPC_STATUS_PROCESSING` in its command status register
-after receiving a host packet and before it has a response ready.
-
-[`cros-ec` Kernel driver]: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/mfd/cros_ec_dev.c
-[Industrial I/O]: https://www.kernel.org/doc/html/v4.14/driver-api/iio/index.html
-[host command task]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/host_command.c
-[Transport-specific details]: #Transport_specific-details
diff --git a/docs/case_closed_debugging.md b/docs/case_closed_debugging.md
deleted file mode 100644
index 8310970652..0000000000
--- a/docs/case_closed_debugging.md
+++ /dev/null
@@ -1,2 +0,0 @@
-The has been moved into a
-[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md)
diff --git a/docs/case_closed_debugging_cr50.md b/docs/case_closed_debugging_cr50.md
deleted file mode 100644
index ac518c0153..0000000000
--- a/docs/case_closed_debugging_cr50.md
+++ /dev/null
@@ -1,2 +0,0 @@
-The has been moved into a
-[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md)
diff --git a/docs/ccd_howtos.md b/docs/ccd_howtos.md
deleted file mode 100644
index 44deecd16d..0000000000
--- a/docs/ccd_howtos.md
+++ /dev/null
@@ -1,2 +0,0 @@
-The has been moved into a
-[different branch](https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/ccd_howtos.md)
diff --git a/docs/code_coverage.md b/docs/code_coverage.md
deleted file mode 100644
index ec8053ca93..0000000000
--- a/docs/code_coverage.md
+++ /dev/null
@@ -1,50 +0,0 @@
-# Code Coverage
-
-Provides an overview of how to use code coverage tools when running the unit
-tests in the EC codebase.
-
-[TOC]
-
-## Availability
-
-Code coverage is only available for host-based unit tests, as opposed to manual
-tests that run on target hardware.
-
-## Building for code coverage
-
-To build host-based unit tests for code coverage, invoke `make` with the
-`coverage` target, as follows:
-
-`make coverage -j`
-
-This target will compile and link the unit tests with `--coverage` flag (which
-pulls in the `gcov` libraries), run the tests, and then process the profiling
-data into a code coverage report using the `lcov` and `genhtml` tools.
-
-The coverage report top-level page is `build/coverage/coverage_rpt/index.html`.
-
-### Noise in the build output
-
-When building for code coverage, you may see multiple warnings of the form
-`geninfo: WARNING: no data found for
-/mnt/host/source/src/platform/ec/core/host/cpu.h` and `genhtml: WARNING:
-function data mismatch at
-/mnt/host/source/src/platform/ec/common/math_util.c:134`
-
-These warnings can be ignored. (FYI, the "function data mismatch" warnings
-appear to be caused in part by using relative paths instead of absolute paths.)
-
-## Zephyr ztest code coverage
-
-To build the Zephyr unit tests for code coverage run:
-
-`zmake coverage build/ztest-coverage`
-
-This target will compile, without linking, all zephyr projects with
-`CONFIG_COVERAGE` Kconfig option enabled, run the tests, and then process the
-profiling data into a code coverage report using the `lcov` and `genhtml`
-tools. This requires the `HAS_COVERAGE_SUPPORT` option, which can only be
-selected in `Kconfig.board`.
-
-The coverage report top-level page is
-`build/ztest-coverage/coverage_rpt/index.html`.
diff --git a/docs/code_reviews.md b/docs/code_reviews.md
deleted file mode 100644
index a8e77c3fd8..0000000000
--- a/docs/code_reviews.md
+++ /dev/null
@@ -1,54 +0,0 @@
-# Code Reviews
-
-The `platform/ec` repository makes use of a code review system that tries to
-evenly distribute code reviews among available reviewers.
-
-[TOC]
-
-## How to request a review
-
-Add `cros-ec-reviewers@google.com` to the reviewer line in Gerrit. A background
-job will come around and replace the `cros-ec-reviewers@google.com` address with
-the next available reviewer in the EC reviewer rotation. This typically takes on
-the order of minutes.
-
-Optionally, you can click the [FIND OWNERS] button in the UI, and select
-`cros-ec-reviewers@google.com`.
-
-## When to use review system
-
-If you are modifying code in `common/`, `chip/`, or `core/`, feel free to use
-the `cros-ec-reviewers@google.com` system. It is **never** a requirement to use
-`cros-ec-reviewers@google.com`. You can always request a review from a specific
-person.
-
-## Responsibilities of reviewers
-
-If the selected reviewer is unfamiliar with code in a CL, then that reviewer
-should at least ensure that EC style and paradigms are being followed. Once EC
-styles and paradigms are being followed, then the reviewer can give a +1 and add
-the appropriate domain expert for that section of code.
-
-Reviewers should try to give an initial response within 1 business day of
-receiving a review request. Thereafter, they should try to respond to new
-comments by the author within 1 business day.
-
-## Review guidelines
-
-Authors and reviewers should follow the Chrome OS firmware review
-[guidelines][2] while publishing and reviewing code.
-
-## How can I join the rotation?
-
-Add your name to the [list of reviewers][1].
-
-## Reference
-
-*   [Chrome OS firmware review guidelines][2]
-*   [Coreboot Gerrit Guidelines][3]
-*   [Google small CL guidelines][5]
-
-[1]: http://google3/chrome/crosinfra/gwsq/ec_reviewers
-[2]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/firmware_code_reviews.md
-[3]: https://doc.coreboot.org/getting_started/gerrit_guidelines.html
-[5]: https://google.github.io/eng-practices/review/developer/small-cls.html
diff --git a/docs/configuration/ap_power_sequencing.md b/docs/configuration/ap_power_sequencing.md
deleted file mode 100644
index c5073d5809..0000000000
--- a/docs/configuration/ap_power_sequencing.md
+++ /dev/null
@@ -1,253 +0,0 @@
-# Configure AP Power Sequencing
-
-This section details the configuration related to managing the system power
-states (G3, S5, S3, S0, S0iX, etc). This includes the following tasks:
-
--   Selecting the AP chipset type.
--   Configure output GPIOs that enable voltage rails.
--   Configure input GPIOs that monitor the voltage rail status (power good
-    signals).
--   Configure input GPIOs that monitor the AP sleep states.
--   Pass through power sequencing signals from the board to the AP, often with
-    delays or other sequencing control.
-
-## Config options
-
-The AP chipset options are grouped together in [config.h]. Select exactly one of
-the available AP chipset options (e.g. `CONFIG_CHIPSET_APOLLOLAKE`,
-`CONFIG_CHIPSET_BRASWELL`, etc). If the AP chipset support is not available,
-select `CONFIG_CHIPSET_ECDRIVEN` to enable basic support for handling S3 and S0
-power states.
-
-After selecting the chipset, search for additional options that start with
-`CONFIG_CHIPSET*` and evaluate whether each option is appropriate to add to
-`baseboard.h` or `board.h`.
-
-Finally, evaluate the `CONFIG_POWER_` options for use on your board. In
-particular, the `CONFIG_POWER_BUTTON`, and `CONFIG_POWER_COMMON` should be
-defined.
-
-The `CONFIG_BRINGUP` option is especially useful option during the initial power
-up of a new board. This option is discussed in more detail in the
-[Testing and Debugging](#Testing-and-Debugging) section.
-
-## Feature Parameters
-
-None needed in this section.
-
-## GPIOs and Alternate Pins
-
-### EC Outputs to the board
-
-The board should connect the enable signal of one or more voltage rails to the
-EC. These enable signals will vary based on the AP type, but are typically
-active high signals. For Intel Ice Lake chipsets, this includes enable signals
-for the primary 3.3V and primary 5V rails.
-
-```c
-GPIO(EN_PP3300_A, PIN(A, 3), GPIO_OUT_LOW)
-GPIO(EN_PP5000,   PIN(A, 4), GPIO_OUT_LOW)
-```
-
-### EC Outputs to AP
-
-For boards with an x86 AP, the following signals can be connected between the EC
-and AP/PCH. Create `GPIO()` entries for any signals used on your board.
-
--   `GPIO_PCH_PWRBTN_L` - Output from the EC that proxies the status of the EC
-    input `GPIO_POWER_BUTTON_L` (driven by the H1). Only used when
-    `CONFIG_POWER_BUTTON_X86` is defined.
--   `GPIO_PCH_RSMRST_L` - Output from the EC that proxies the status of the EC
-    input `GPIO_RSMRST_L_PGOOD` (driven by the PMIC or voltage regulators on the
-    board).
--   `GPIO_PCH_SYS_PWROK` - Output from the EC that indicates when the system
-    power is good and the AP can power up.
--   `GPIO_PCH_WAKE_L` - Output from the EC, driven low when there is a wake
-    event.
-
-### Power Signal Interrupts
-
-For each power signal defined in the `power_signal_list[]` array, define a
-`GPIO_INT()` entry that connects to the `power_signal_interrupt`. The interrupts
-are configured to trigger on both rising edge and falling edge.
-
-The example below shows the power signals used with Ice Lake processors.
-
-```c
-GPIO_INT(SLP_S0_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S4_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(PG_EC_ALL_SYS_PWRGD, PIN(F, 4), GPIO_INT_BOTH,   power_signal_interrupt)
-GPIO_INT(PP5000_A_PG_OD, PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
-```
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Data structures
-
--   `const struct power_signal_info power_signal_list[]` - This array defines
-    the signals from the AP and from the power subsystem on the board that
-    control the power state. For some Intel chipsets, including Apollo Lake and
-    Ice Lake, this power signal list is already defined by the corresponding
-    chipset file under the `./power` directory.
-
-## Tasks
-
-The `CHIPSET` task monitors and handles the power state changes. This task
-should always be enabled with a priority higher than the `CHARGER` task, but
-lower than the `HOSTCMD` and `CONSOLE` tasks.
-
-```c
-    TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
-```
-
-The `POWERBTN` and task should be enabled when using x86 based AP chipsets. The
-typical priority is higher than the `CONSOLE` task, but lower than the `KEYSCAN`
-task.
-
-```c
-    TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
-```
-
-## Testing and Debugging
-
-During the first power on of prototype devices, it is recommended to enable
-`CONFIG_BRINGUP`. This option prevents the EC from automatically powering on the
-AP. You can use the EC console commands `gpioget` and `gpioset` to manually
-check power good signals and enable power rails in a controlled manner. This
-option also enables extra debug to log all power signal transitions to the EC
-console. With `CONFIG_BRINGUP` enabled, you can trigger the automatic power
-sequencing by running the `powerbtn` from the EC console.
-
-The EC console displays the following text when `CONFIG_BRINGUP` is enabled:
-
-```
-WARNING: BRINGUP BUILD
-```
-
-Once you manually press the power button, or execute the `powerbtn` command, the
-EC console displays both the power state changes and the detected transitions of
-all power signals. An example is shown below.
-
-```
-> powerbtn
-Simulating 200 ms power button press.
-[6.790816 power button pressed]
-[6.791133 PB pressed]
-[6.791410 PB task 1 = pressed]
-[6.791755 PB PCH pwrbtn=LOW]
-[6.792049 PB task 10 = was-off, wait 199362]
-RTC: 0x000067bc (26556.00 s)
-[6.792786 power state 5 = G3->S5, in 0x0000]
-[6.793190 Set EN_PP3300_A: 1]
-[6.793905 SW 0x03]
-[6.817627 Set PCH_DSW_PWROK: 1]
-[6.818007 Pass thru GPIO_DSW_PWROK: 1]
-[6.818351 Set EN_PP5000_A: 1]
-RTC: 0x000067bc (26556.00 s)
-[6.903830 power state 1 = S5, in 0x0029]
-[6.918735 Pass through GPIO_RSMRST_L_PGOOD: 1]
-i2c 7 recovery! error code is 13, current state is 0
-Simulating power button release.
-> [6.991576 power button released]
-[6.992009 PB task 10 = was-off]
-[6.992376 PB released]
-[6.992635 PB task 6 = released]
-[6.992958 PB PCH pwrbtn=HIGH]
-[6.993256 PB task 0 = idle, wait -1]
-[6.993806 PB released]
-[6.994149 PB task 6 = released]
-[6.994512 PB PCH pwrbtn=HIGH]
-[6.994812 PB task 0 = idle, wait -1]
-[6.995768 SW 0x01]
-3 signal changes:
-  6.807298  +0.000000  DSW_PWROK => 1
-  6.903417  +0.096119  SLP_SUS_L => 1
-  6.908471  +0.005054  PG_EC_RSMRST_ODL => 1
-1 signal changes:
-  7.909941  +0.000000  SLP_S0_L => 1
-[9.026429 Fan 0 stalled!]
-RTC: 0x000067bf (26559.00 s)
-[9.124643 power state 6 = S5->S3, in 0x003f]
-i2c 3 recovery! error code is 13, current state is 0
-[9.126543 mux config:2, port:1, res:1]
-[9.127109 PD:S5->S3]
-RTC: 0x000067bf (26559.00 s)
-[9.127985 power state 2 = S3, in 0x003f]
-RTC: 0x000067bf (26559.00 s)
-[9.128640 power state 7 = S3->S0, in 0x003f]
-```
-
-This example shows successful power on of the AP as the AP transitions from the
-G3 state all the way to the S0 state.
-
-The console messages shown in brackets `[]` include a timestamp. This timestamp
-records when the corresponding console message was printed.
-
-The power signal changes are preceded by the message `<N> signal changes:`.
-Power signal changes are recorded at interrupt priority into a special buffer
-and are not displayed in real time. Instead, printing of the buffer is deferred
-until the EC is no longer executing at interrupt priority. This causes the power
-signal changes shown on the console to be out of order with respect to the other
-EC messages.
-
-The power signal changes include a timestamp to help you correlate when the
-actual power signal changed compared to other messages. From the example above,
-the first power signal change recorded is the `DSW_PWROK` signal transitioning
-from 0 to 1, and this is recorded at timestamp `6.807298`. Using the regular EC
-console timestamp, you can reconstruct the real power sequence to look like the
-following:
-
-```
-> powerb
-Simulating 200 ms power button press.
-[6.790816 power button pressed]
-[6.791133 PB pressed]
-[6.791410 PB task 1 = pressed]
-[6.791755 PB PCH pwrbtn=LOW]
-[6.792049 PB task 10 = was-off, wait 199362]
-RTC: 0x000067bc (26556.00 s)
-[6.792786 power state 5 = G3->S5, in 0x0000]
-[6.793190 Set EN_PP3300_A: 1]
-[6.793905 SW 0x03]
-  6.807298  +0.000000  DSW_PWROK => 1             // Manually re-ordered entry
-[6.817627 Set PCH_DSW_PWROK: 1]
-[6.818007 Pass thru GPIO_DSW_PWROK: 1]
-[6.818351 Set EN_PP5000_A: 1]
-RTC: 0x000067bc (26556.00 s)
-  6.903417  +0.096119  SLP_SUS_L => 1              // Manually re-ordered entry
-[6.903830 power state 1 = S5, in 0x0029]
-  6.908471  +0.005054  PG_EC_RSMRST_ODL => 1       // Manually re-ordered entry
-[6.918735 Pass through GPIO_RSMRST_L_PGOOD: 1]
-i2c 7 recovery! error code is 13, current state is 0
-Simulating power button release.
-> [6.991576 power button released]
-[6.992009 PB task 10 = was-off]
-[6.992376 PB released]
-[6.992635 PB task 6 = released]
-[6.992958 PB PCH pwrbtn=HIGH]
-[6.993256 PB task 0 = idle, wait -1]
-[6.993806 PB released]
-[6.994149 PB task 6 = released]
-[6.994512 PB PCH pwrbtn=HIGH]
-[6.994812 PB task 0 = idle, wait -1]
-[6.995768 SW 0x01]
-1 signal changes:
-  7.909941  +0.000000  SLP_S0_L => 1
-[9.026429 Fan 0 stalled!]
-RTC: 0x000067bf (26559.00 s)
-[9.124643 power state 6 = S5->S3, in 0x003f]
-i2c 3 recovery! error code is 13, current state is 0
-[9.126543 mux config:2, port:1, res:1]
-[9.127109 PD:S5->S3]
-RTC: 0x000067bf (26559.00 s)
-[9.127985 power state 2 = S3, in 0x003f]
-RTC: 0x000067bf (26559.00 s)
-[9.128640 power state 7 = S3->S0, in 0x003f]
-```
-
-*TODO ([b/147808790](http://issuetracker.google.com/147808790)) Add
-documentation specific to each x86 processor type.*
-
-[config.h]: ../new_board_checklist.md#config_h
diff --git a/docs/configuration/cbi.md b/docs/configuration/cbi.md
deleted file mode 100644
index f89ee78454..0000000000
--- a/docs/configuration/cbi.md
+++ /dev/null
@@ -1,39 +0,0 @@
-# Configure CrOS Board Information (CBI)
-
-If your board includes an EEPROM to store [CBI], then this feature must be
-enabled and configured. Note that the [I2C buses] must be configured and working
-before enabling CBI.
-
-## Config options
-
-Add the following config options to `baseboard.h` or `board.h`.
-
--   `CONFIG_BOARD_VERSION_CBI`
--   `CONFIG_CBI_EEPROM`
-
-## Feature Parameters
-
--   `I2C_ADDR_EEPROM_FLAGS <7-bit addr>` - Defines the 7-bit slave address for
-    the EEPROM containing CBI.
-
-## GPIOs and Alternate Pins
-
-None needed - the I2C pins should be configured automatically when initializing
-the I2C buses.
-
-## Data Structures
-
-None required by this feature.
-
-## Tasks
-
-None required by this feature.
-
-## Testing and Debugging
-
-Refer to the [I2C debugging information] to verify communication with the CBI
-EEPROM.
-
-[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
-[I2C buses]: ./i2c.md
-[I2C debugging information]: ./i2c.md#
diff --git a/docs/configuration/config_ap_to_ec_comm.md b/docs/configuration/config_ap_to_ec_comm.md
deleted file mode 100644
index 24b309feb7..0000000000
--- a/docs/configuration/config_ap_to_ec_comm.md
+++ /dev/null
@@ -1,73 +0,0 @@
-# Configure AP to EC Communication
-
-This document provides details on how to configure the AP to EC communication
-channel used on your board. The [AP to EC Communication] document provides
-details a system level of the operation of this feature.
-
-## Config options
-
-Configure the AP to EC communication channel, picking exactly one of the
-following options.
-
--   `CONFIG_HOSTCMD_SHI` - [SPI Host Interface](../ec_terms.md#shi) (SHI)
--   `CONFIG_HOSTCMD_HECI` - HECI interface
--   `CONFIG_HOSTCMD_LPC` - [LPC](../ec_terms.md#lpc) bus
--   `CONFIG_HOSTCMD_ESPI` - [eSPI](../ec_terms.md#espi) bus
-
-In [config.h], search for options that start with the same name as your selected
-communication interface. Override defaults as needed.
-
-## Feature Parameters
-
-None needed in this section.
-
-## GPIOs and Alternate Pins
-
-The EC code requires the following signals between the AP and the EC to be
-defined by each board variant.
-
--   `GPIO_ENTERING_RW` - Output from the EC, active high signal indicates when
-    the EC code transitions from RO to RW code.
-
-    ```c
-    GPIO(EC_ENTERING_RW,           PIN(E, 3), GPIO_OUT_LOW)
-    ```
-
--   `GPIO_SYS_RESET_L` - Output from the EC, active low signal used to put the
-    AP into reset.
-
-    ```c
-    GPIO(SYS_RST_ODL,              PIN(C, 5), GPIO_ODR_HIGH)
-    ```
-
-Create `ALTERNATE()` entries for all EC signals used for AP communication. This
-step can be skipped for any pins that default to communication channel
-functionality.
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Data structures
-
-None needed in this section.
-
-## Tasks
-
-The `HOSTCMD` task is responsible for processing commands sent by the AP and is
-always required. The typical priority is higher than the `CHIPSET` task, but
-lower than the `CONSOLE` task.
-
-```c
-    TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE, 0) \
-```
-
-## Testing and Debugging
-
-For Nuvoton EC chipsets, the file [./chip/npcx/registers.h] provides a
-collection of `DEBUG_*` macros that can be used to enable extra console messages
-related to a specific interface. For AP to EC communication, the `DEBUG_LPC` and
-`DEBUG_ESPI` macros can help troubleshoot communication issues.
-
-[./chip/npcx/registers.h]: ../../chip/npcx/registers.h
-[AP to EC Communication]: ../ap-ec-comm.md
-[config.h]: ../new_board_checklist.md#config_h
diff --git a/docs/configuration/ec_chipset.md b/docs/configuration/ec_chipset.md
deleted file mode 100644
index defc27eec8..0000000000
--- a/docs/configuration/ec_chipset.md
+++ /dev/null
@@ -1,116 +0,0 @@
-# Configure EC Chipset
-
-## Config options
-
-The EC chipset is selected using board specific make file [build.mk]. The
-following configuration options specify the type and size of flash memory used
-by the EC.
-
--   `CONFIG_SPI_FLASH_REGS` - Should always be defined when using internal or
-    external SPI flash.
--   `CONFIG_SPI_FLASH` - Define only if your board uses an external flash.
--   `CONFIG_SPI_FLASH_<device_type>` - Select exactly one the supported flash
-    devices to compile in the required driver. This is needed even when using
-    the internal SPI flash of the EC chipset.
--   Additional EC Chipset options are prefixed with `CONFIG_HIBERNATE*` and
-    should be evaluated for relevance on your board.
-
-## Feature Parameters
-
--   `CONFIG_FLASH_SIZE_BYTES <bytes>` - Set to the size of the internal flash of
-    the EC. Must be defined to link the final image.
--   `CONFIG_SPI_FLASH_PORT <port>` - Only used if your board as an external
-    flash.
-
-## GPIOs and Alternate Pins
-
-Configure the signals which will wakeup the EC from hibernate or deep sleep.
-Typical wakeup sources include:
-
--   `GPIO_LID_OPEN` - An active high signal that indicates the lid has been
-    opened. The source of the signal is typically from a
-    [GMR](../ec_terms.md#gmr) or Hall-Effect sensor. The `GPIO_INT()` entry for
-    this signal should be connected to the `lid_interrupt()` routine.
--   `GPIO_AC_PRESENT` - A signal from the battery charger that indicates the
-    device is connected to AC power. This signal is connected to the
-    `power_interrupt()` routine.
--   `GPIO_POWER_BUTTON_L` - An active low signal from the power switch. This
-    signal is connected to the `power_button_interrupt()` routine.
--   `GPIO_EC_RST_ODL` - On some Nuvoton EC chipsets, the reset signal is
-    dual-routed to both a dedicated reset pin and a GPIO. In this case, no
-    interrupt handler needs to be registered to the GPIO signal, but the GPIO
-    pin must still be configured to wake on both edge types. The GPIO pin should
-    also be locked prevent the pin configuration from changing after the EC
-    read-only code runs.
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Data structures
-
--   `const enum gpio_signal hibernate_wake_pins[]` - add all GPIO signals that
-    should trigger a wakeup of the EC.
--   `const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);` -
-    configures the number of wake signals used on the board.
-
-All ChromeOS wake sources are documented on the ChromeOS partner site in the
-[Wake Sources and Battery Life] section. The EC specific wake sources are found
-under the Deep Sleep and Shipping states and include:
-
--   Power button
--   AC insert
--   Lid open
-
-## Tasks
-
-None required by this feature.
-
-## Testing and Debugging
-
-## Example
-
-For the Volteer reference board, the following wake sources are defined in
-[gpio.inc]. Note that configuration of `GPIO(EC_RST_ODL)` is located after all
-`GPIO_INT()` entries required by the board.
-
-```c
-/* Wake Source interrupts */
-GPIO_INT(EC_LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(EC_WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(H1_EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
-GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-
-/* EC_RST_ODL - PSL input but must be locked */
-GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_LOCKED)
-```
-
-For the NPCx7 chipset, the alternate function must also be configured to connect
-the wakeup pins to the PSL (power switch logic).
-
-```c
-/* GPIOD2 = EC_LID_OPEN */
-ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)
-/* GPIO00 = ACOK_OD,
-   GPIO01 = H1_EC_PWR_BTN_ODL
-   GPIO02 = EC_RST_ODL */
-ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)
-```
-
-The final step is to add the hibernate signals array to Volteer [baseboard.c]
-file:
-
-```c
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-    GPIO_LID_OPEN,
-    GPIO_ACOK_OD,
-    GPIO_POWER_BUTTON_L,
-    GPIO_EC_RST_ODL,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-```
-
-[gpio.inc]: ../../board/volteer/gpio.inc
-[baseboard.c]: ../../baseboard/volteer/baseboard.c
-[build.mk]: ../new_board_checklist.md#board_build_mk
-[Wake Sources and Battery Life]: https://chromeos.google.com/partner/dlm/docs/latest-requirements/chromebook.html#wake-sources-and-battery-life
diff --git a/docs/configuration/gpio.md b/docs/configuration/gpio.md
deleted file mode 100644
index f4a5c4719a..0000000000
--- a/docs/configuration/gpio.md
+++ /dev/null
@@ -1,160 +0,0 @@
-# GPIO Configuration
-
-GPIO setup is done for every board variant, but never for the baseboard, by
-configuring the file `./board/<board>/gpio.inc`. This file configures all the
-the pins on the EC chipset through the following macros.
-
--   `GPIO(<name>, ...)` - Configures simple GPIO input and outputs
--   `GPIO_INT(<name>, ...)` - Configures GPIO inputs that connect to an
-    interrupt service routine. Historically these entries are defined first, but
-    this no longer required.
--   `ALTERNATE(...)` - Configures a pin for an alternate function (e.g I2C, ADC,
-    SPI, etc)
--   `UNIMPLEMENTED(<name>, ...)` - Creates a fake GPIO entry
-
-The `GPIO()`, `GPIO_INT()`, and `UNIMPLEMENTED()` macros create a C enumeration
-of the form `GPIO_<name>` that can be used in the code. As noted in
-[GPIO Naming](../new_board_checklist.md#GPIO-Naming), the `<name>` parameter
-should always match the schematic net name.
-
-## `GPIO()` macro
-
-### Prototype
-
-`GPIO(name, pin, flags)`
-
--   `name` - Defines the schematic net name, which is expanded to the
-    enumeration `GPIO_name` by the macro.
--   `pin` - Use the `PIN(group,pin)` macro to define the GPIO group and pin
-    number. Note that on a few EC chipsets, the PIN macro is just `PIN(pin)`.
--   `flags` - Define attributes of the pin (direction, pullup/pulldown, open
-    drain, voltage level, etc). All supported flags are found following the
-    `GPIO_FLAG_NONE` definition in [./include/gpio.h](../../include/gpio.h).
-
-### Example
-
-![GPIO Example]
-
-```c
-GPIO(EC_ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW)
-```
-
-The EC common code requires the enum `GPIO_ENTERING_RW` to be defined, so you
-should also map the net name to the EC name in the `board.h` file.
-
-```c
-#define GPIO_ENTERING_RW    GPIO_EC_ENTERING_RW
-```
-
-## `GPIO_INT()` macro
-
-### Prototype
-
-`GPIO_INT(name, pin, flags, signal)`
-
--   `name` - Defines the schematic net name, which is expanded to the
-    enumeration `GPIO_name` by the macro.
--   `pin` - Same definition as `GPIO()` macro.
--   `flags` - Same definition as `GPIO()` macro. Should always have one of the
-    `GPIO_INT_*` flags set.
--   `signal` - Interrupt service routine called when the pin asserts according
-    to the flags set.
-
-### Example
-
-![GPIO_INT Example]
-
-```c
-GPIO_INT(EC_LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-```
-
-The EC common code requires the enum `GPIO_LID_OPEN` to be defined, so you als
-need to map the net name to the EC name in the `board.h` file.
-
-```c
-#define GPIO_LID_OPEN       GPIO_EC_LID_OPEN
-```
-
-## `ALTERNATE()` macro
-
-### Prototype
-
-`ALTERNATE(pinmask, function, module, flags)`
-
--   `pinmask` - Defines a set of pins in the same GPIO group to assign to a
-    different function.
--   `function` - A chip-specific function number. Only used if the EC chipset
-    provides multiple alternate functions in addition to GPIO (e.g. pin can be
-    UART, I2C, SPI, or GPIO). The permitted values for this parameter vary based
-    on the EC chipset type.
-    -   STM32 - 0 to 7
-    -   Maxim - 1 to 3
-    -   Microchip - 0 to 3
-    -   MediaTek - 0 to 7
-    -   All others (Nuvton, ITE, TI Stellaris, ) only support one alternate
-        function per pin, so this parameter should be set to 0.
--   `module` - One of the enum module_id values defined in
-    [./include/module_id.h](../../include/module_id.h).
--   `flags` - Same definition as `GPIO()` macro.
-
-### Notes
-
-At runtime there are two mechanisms for switching a pin between GPIO mode and
-alternate function mode.
-
--   `gpio_config_module(enum module_id id, int enable)` - Configures all pins
-    matching the module enumeration `id`.
--   `gpio_config_pin(enum module_id id, enum gpio_signal signal, int enable)` -
-    Configures a single pin matching the GPIO enumeration `signal`.
-
-For both routines, if `enable` is 1, then the corresponding pins are configured
-for alternate mode operation. If `enable` is 0, then the corresponding pins are
-configure for GPIO mode.
-
-`gpio_config_module()` is automatically called at runtime for all enabled
-interfaces (I2C, SPI, UART, etc). You can use `gpio_config_pin()` to temporarily
-configure a pin for GPIO operation, and to restore the original alternate
-function. The I2C bus error recovery employs this mechanism to temporarily
-driver the I2C SCL and SDA signals to known states, without interference by the
-I2C controller in the EC chipset.
-
-The general recipe for overriding alternate functions is shown below.
-
-```c
-    /* Disconnect I2C1_SDA pin from I2C controller */
-    gpio_config_pin(MODULE_I2C, GPIO_I2C1_SDA, 0);
-
-    /* Setup I2C1_SDA as an GPIO open drain output and drive initial state low */
-    gpio_set_flags(GPIO_I2C1_SDA, GPIO_ODR_LOW);
-
-    /* Set GPIO high (or low) as required */
-    gpio_set_level (GPIO_I2C1_SDA, 1);
-
-    /* Restore I2C1_SDA pin to I2C function */'
-    gpio_config_pin(MODULE_I2C, GPIO_I2C1_SDA, 1);
-```
-
-### Example
-
-![ALTERNATE Example]
-
-```c
-ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V))
-```
-
-<!-- Images -->
-
-<!-- If you make changes to the docs below make sure to regenerate the PNGs by
-     appending "export/png" to the Google Drive link. -->
-
-<!-- https://docs.google.com/drawings/d/18cWTYQRRCpypYDOLlvKQJTObwcj6wOjUga02B0oZXBg -->
-
-[GPIO Example]: ../images/gpio_example.png
-
-<!-- https://docs.google.com/drawings/d/1X6p5XfB6BBmUUKCrwOg56Bz6LZj9P_WPQXsOdk-OIiI -->
-
-[GPIO_INT Example]: ../images/gpio_int_example.png
-
-<!-- https://docs.google.com/drawings/d/1-kroVezQuA_KdQLzqYPs8u94EBg37z3k6lKzkSLRv-0 -->
-
-[ALTERNATE Example]: ../images/alternate_example.png
diff --git a/docs/configuration/i2c.md b/docs/configuration/i2c.md
deleted file mode 100644
index 36464bb371..0000000000
--- a/docs/configuration/i2c.md
+++ /dev/null
@@ -1,203 +0,0 @@
-# Configure I2C Buses
-
-## Config options
-
-The I2C options are prefixed with `CONFIG_I2C*`. Evaluate whether each option is
-appropriate to add to your board.
-
-A typical EC and board should at a minimum set `CONFIG_I2C` and
-`CONFIG_I2C_CONTROLLER`.
-
-## Feature Parameters
-
-The following parameters control the behavior of the I2C library. [config.h]
-defines a reasonable default value, but you may need to change the default value
-for your board.
-
--   `CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE <bytes>`
--   `CONFIG_I2C_NACK_RETRY_COUNT <count>`
--   `CONFIG_I2C_EXTRA_PACKET_SIZE <bytes>` - Only used on STM32 EC's if
-    `CONFIG_HOSTCMD_I2C_ADDR_FLAGS` is defined.
-
-## GPIOs and Alternate Pins
-
-In the gpio.inc file, you need to define a GPIO for the clock (SCL) and data
-(SDA) pin used on each active I2C bus. The corresponding GPIOs are then included
-in the `i2c_ports[]` array. This permits the I2C library to perform common bus
-recovery actions using bit-banging without involvement by the EC-specific I2C
-device driver.
-
-You also need to define the alternate function assignment for all I2C pins using
-the `ALTERNATE()` macro. This step can be skipped for any pins that default to
-I2C functionality.
-
-Note that many I2C buses only support 1.8V operation. This is determined by I2C
-devices connected to the bus. In this case you need to include `GPIO_SEL_1P8V`
-as part of the `flags` field in both the `GPIO()` and `ALTERNATE()` macros. I2C
-bus 0 in the example below demonstrates configuring the SCL and SDA pins for
-1.8V operation.
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Data Structures
-
--   `const struct i2c_port_t i2c_ports[]` - This array should be defined in your
-    baseboard.c or board.c file. This array defines the mapping of internal I2C
-    port numbers used by the I2C library to the physical I2C ports connected to
-    the EC.
--   `const unsigned int i2c_port_used = ARRAY_SIZE(i2c_ports)` - Defines the
-    number of internal I2C ports accessible by the I2C library.
-
-## Tasks
-
-None required by this feature.
-
-## Testing and Debugging
-
-### Console Commands
-
--   `i2cscan` - Provides a quick look of all I2C devices found on all configured
-    buses.
--   `i2cxfer` - Allows you to read and write individual registers on an I2C
-    device.
-
-For runtime troubleshooting of an I2C device, enable and the
-[I2C tracing](../i2c-debugging.md) module to log all I2C transactions initiated
-by the EC code.
-
-## Example
-
-The image below shows the I2C bus assignment for the Volteer reference board.
-
-![I2C Example]
-
-The `gpio.inc` file for Volteer defines both `GPIO()` and `ALTERNATE()` entries
-for all I2C buses used in the design.
-
-```c
-/* I2C pins - Alternate function below configures I2C module on these pins */
-GPIO(EC_I2C0_SENSOR_SCL,       PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C0_SENSOR_SDA,       PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C1_USB_C0_SCL,       PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C1_USB_C0_SDA,       PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SCL,       PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C2_USB_C1_SDA,       PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SCL,    PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C3_USB_1_MIX_SDA,    PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SCL,        PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C5_POWER_SDA,        PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SCL,       PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C7_EEPROM_SDA,       PIN(B, 2), GPIO_INPUT)
-
-/* Alternate functions GPIO definitions */
-ALTERNATE(PIN_MASK(B, BIT(5) | BIT(4)), 0, MODULE_I2C, (GPIO_INPUT | GPIO_SEL_1P8V)) /* I2C0 */
-ALTERNATE(PIN_MASK(9, BIT(0) | BIT(2) | BIT(1)), 0, MODULE_I2C, 0)                   /* I2C1 SCL / I2C2 */
-ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)                                     /* I2C1 SDA */
-ALTERNATE(PIN_MASK(D, BIT(1) | BIT(0)), 0, MODULE_I2C, 0)                            /* I2C3 */
-ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)                            /* I2C5 */
-ALTERNATE(PIN_MASK(B, BIT(3) | BIT(2)), 0, MODULE_I2C, 0)                            /* I2C7 */
-```
-
-The `i2c_ports[]` array requires the `.port` field to be assigned to an EC
-chipset specific enumeration. For the NPCx7 I2C bus names are defined in
-[./chip/npcx/registers.h]. The Volteer `baseboard.h` file creates a mapping from
-the schematic net name to the NPCx7 I2C bus enumeration.
-
-```c
-#define CONFIG_I2C
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1     NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX  NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER      NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-```
-
-The last piece for I2C configuration is to create the `i2c_ports[]` array using
-the macros and enumerations added to `baseboard.h` and `gpio.inc`.
-
-```c
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-    {
-        .name = "sensor",
-        .port = I2C_PORT_SENSOR,
-        .kbps = 400,
-        .scl = GPIO_EC_I2C0_SENSOR_SCL,
-        .sda = GPIO_EC_I2C0_SENSOR_SDA,
-        .flags = 0,
-    },
-    {
-        .name = "usb_c0",
-        .port = I2C_PORT_USB_C0,
-        /*
-         * I2C buses used for PD communication must be set for 400 kbps
-         * or greater. Set to the maximum speed supported by all devices.
-         */
-        .kbps = 1000,
-        .scl = GPIO_EC_I2C1_USB_C0_SCL,
-        .sda = GPIO_EC_I2C1_USB_C0_SDA,
-    },
-    {
-        .name = "usb_c1",
-        .port = I2C_PORT_USB_C1,
-        /*
-         * I2C buses used for PD communication must be set for 400 kbps
-         * or greater. Set to the maximum speed supported by all devices.
-         */
-        .scl = GPIO_EC_I2C2_USB_C1_SCL,
-        .sda = GPIO_EC_I2C2_USB_C1_SDA,
-    },
-    {
-        .name = "usb_1_mix",
-        .port = I2C_PORT_USB_1_MIX,
-        .kbps = 100,
-        .scl = GPIO_EC_I2C3_USB_1_MIX_SCL,
-        .sda = GPIO_EC_I2C3_USB_1_MIX_SDA,
-    },
-    {
-        .name = "power",
-        .port = I2C_PORT_POWER,
-        .kbps = 100,
-        .scl = GPIO_EC_I2C5_POWER_SCL,
-        .sda = GPIO_EC_I2C5_POWER_SDA,
-    },
-    {
-        .name = "eeprom",
-        .port = I2C_PORT_EEPROM,
-        .kbps = 400,
-        .scl = GPIO_EC_I2C7_EEPROM_SCL,
-        .sda = GPIO_EC_I2C7_EEPROM_SDA,
-    },
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-```
-
-The `.flags` field is optional when using the default I2C bus setup. See
-[./include/i2c.h] for the full list of supported flags.
-
-The flag `I2C_PORT_FLAG_DYNAMIC_SPEED` allows the I2C bus frequency to be
-changed at runtime. The typical use case is to set the I2C bus frequency to
-different speeds based on the BOARD_VERSION in [CBI]. For example board version
-1 supports 100 kbps operation but board version 2 and greater supports 400 kbps
-operation. `I2C_PORT_FLAG_DYNAMIC_SPEED` is not used to change the I2C bus
-frequency on the fly depending on the addressed slave device.
-
-An example of changing the I2C bus frequency from the
-[Kodama board](../../board/kodama/board.c) is shown below.
-
-```c
-static void board_i2c_init(void)
-{
-    if (board_get_version() < 2)
-        i2c_set_freq(1,  I2C_FREQ_100KHZ);
-}
-DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C);
-```
-
-[config.h]: ../new_board_checklist.md#config_h
-[./chip/npcx/registers.h]: ../../chip/npcx/registers.h
-[./include/i2c.h]: ../../include/i2c.h
-[I2C Example]: ../images/i2c_example.png
-[CBI]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
diff --git a/docs/configuration/keyboard.md b/docs/configuration/keyboard.md
deleted file mode 100644
index 8398fefbde..0000000000
--- a/docs/configuration/keyboard.md
+++ /dev/null
@@ -1,87 +0,0 @@
-## Configure Keyboard
-
-## Config options
-
-Keyboard options start with `CONFIG_KEYBOARD*`. Evaluate whether each option is
-appropriate to add to `baseboard.h` or `board.h`.
-
-Your board should select only one of these options to configure the protocol
-used to send keyboard events to the AP.
-
--   `CONFIG_KEYBOARD_PROTOCOL_8042` - Systems with an x86 AP use the 8042
-    protocol.
--   `CONFIG_KEYBOARD_PROTOCOL_MKBP` - Systems without an x86 AP (e.g. ARM)
-    typically use the MKBP protocol.
-
-## Feature Parameters
-
--   `CONFIG_KEYBOARD_KSO_BASE <pin>` - Evaluate whether this parameter is
-    required by your board.
-
-## GPIOs and Alternate Pins
-
-Define `ALTERNATE()` pin entries for all keyboard matrix signals, to connect the
-signals to the keyboard controller of the EC chipset.
-
-Note that KSO_02 is purposely not configured for for alternate mode. See the
-[H1 Special Requirements](#H1-Special-Requirements) below for details.
-
-```c
-/* Example Keyboard pin setup */
-#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_00-01 */
-ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* KSI_02-07 */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */
-ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */
-ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */
-ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14    */
-```
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Data structures
-
--   `struct keyboard_scan_config keyscan_config` - This can be used to customize
-    the keyboard scanner (e.g. scan frequency, debounce duration, etc.).
-
-## Tasks
-
-The `KEYSCAN` task monitors the keyboard matrix for new key presses and is
-required by this feature. The priority is set as one of the highest priority
-tasks in the system, typically only below the `PD_Cn` and `PD_INT_Cn` tasks.
-
-```c
-    TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
-```
-
-The `KEYPROTO` task handles sending and receiving 8042 protocol messages from
-the AP and is required when `CONFIG_KEYBOARD_PROTOCOL_8042` is used. The typical
-priority is lower than the `HOSTCMD` task.
-
-```c
-    TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-```
-
-## Additional Notes
-
--   If you're including keyboard support, you should also define
-    `CONFIG_CMD_KEYBOARD` to enable keyboard debug commands from the EC console.
--   `CONFIG_KEYBOARD_PROTOCOL_MKBP` automatically enables `CONFIG_MKBP_EVENT`.
--   Boards that enable `CONFIG_KEYBOARD_PROTOCOL_8042` will often also define
-    `CONFIG_MKBP_EVENT` for sensor events. In this case only motion sensor data
-    is reported using the MKBP protocol, keyboard events are provided using the
-    8042 protocol. Refer to [Configuring Sensors](./motion_sensors.md) for more
-    information.
-
-### H1 Special Requirements
-
-On Boards that use the H1 secure microcontroller, one KSI (keyboard scan input)
-signal and one KSO (keyboard scan output) signal are routed through the H1
-microcontroller. There are additional GPIO and configuration options that must
-be enabled in this case. - The KSO_02/COL2 signal is always inverted. Explicitly
-configure the GPIO to default low. `c GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /*
-KSO_02 inverted */` - Add the define `CONFIG_KEYBOARD_COL2_INVERTED` to
-`baseboard.h` or `board.h`. - If required by the board, define one of the
-following options to configure the KSI pin routed to the H1 microcontroller. -
-`CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2` - `CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3`
diff --git a/docs/configuration/leds.md b/docs/configuration/leds.md
deleted file mode 100644
index c4fe7894af..0000000000
--- a/docs/configuration/leds.md
+++ /dev/null
@@ -1,88 +0,0 @@
-# Configure LEDs
-
-LEDs provide status about the following:
-
--   Dedicated battery state/charging state
--   Chromebook power
--   Adapter power
--   Left side USB-C port (battery state/charging state)
--   Right side USB-C port (battery state/charging state)
--   Recovery mode
--   Debug mode
-
-LEDs can be configured as simple GPIOs, with on/off control only, or as PWM with
-adjustment brightness and color.
-
-## Config options
-
-In [config.h], search for options that start with `CONFIG_LED*` and evaluate
-whether each option is appropriate to add to `baseboard.h` or `board.h`.
-
--   `CONFIG_LED_COMMON` - Should be defined for both GPIO and PWM style LEDs.
--   `CONFIG_LED_ONOFF_STATES` - used for GPIO controlled LEDs
--   `CONFIG_LED_PWM` - used for PWM controlled LEDs. You must also define
-    `CONFIG_PWM` when using PWM controlled LEDs.
-
-## Feature Parameters
-
--   `CONFIG_LED_PWM_COUNT <count>` - Must be defined when using PWM LEDs
-
-Override the following parameters when using PWM LEDs if you don't want to use
-the recommended LED color settings. - `CONFIG_LED_PWM_CHARGE_COLOR
-<ec_led_color>` - `CONFIG_LED_PWM_NEAR_FULL_COLOR <ec_led_color>` -
-`CONFIG_LED_PWM_CHARGE_ERROR_COLOR <ec_led_color>` -
-`CONFIG_LED_PWM_SOC_ON_COLOR <ec_led_color>` - `CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-<ec_led_color>` - `CONFIG_LED_PWM_LOW_BATT_COLOR <ec_led_color>`
-
-## GPIOs and Alternate Pins
-
-For GPIO based LEDs, create `GPIO()` entries for all signals that connect to
-platform LEDs. The default state of the pins should be set so that the LED is
-off (typically high output).
-
-For PWM LEDs, configure the `ALTERNATE()` macro, setting the module type to
-`MODULE_PWM`.
-
-## Data structures
-
-For GPIO based LEDs: - `struct led_descriptor
-led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]` - Must be defined when
-`CONFIG_LED_ONOFF_STATES` is used. Defines the LED states for the platform for
-various charging states.
-
-For PWM based LEDs: - `const enum ec_led_id supported_led_ids[]` - Defines the
-LED type for all PWM LEDs in the system. See [./include/ec_commands.h] for a
-description of the supported LED types. - `struct pwm_led led_color_map[]` -
-Defines the PWM intensity of the individual LEDs to generate the corresponding
-color. This table allows for custom tuning of the LED brightness and color. -
-`const struct pwm_channels[]` - Configures the PWM module, refer to the
-[Configuring PWM](./pwm.md) section for details.
-
-See the [GPIO](./gpio.md) documentation for additional details on the GPIO
-macros.
-
-## Tasks
-
-None required by this feature.
-
-## Testing and Debugging
-
-### Console Commands
-
--   `pwmduty` - *TODO* add description.
--   `gpioset` - For GPIO based LEDs, this command lets you directly change the
-    state of the LED.
--   `gpioget` - For GPIO based LEDs, this reads current state of the pin. If the
-    current state does not track changes made with `gpioset`, check your board
-    for stuck at high or stuck at low condition.
-
-If you're having problems with a PWM LED, try reconfiguring the pin as a GPIO to
-verify the board operation independent of the PWM module.
-
-## LED Driver Chips
-
-LED driver chips are used to control the LCD panel backlight. The backlight
-control is separate from the platform LEDs.
-
-[config.h]: ../new_board_checklist.md#config_h
-[./include/ec_commands.h]: ../../include/ec_commands.h
diff --git a/docs/configuration/motion_sensors.md b/docs/configuration/motion_sensors.md
deleted file mode 100644
index 6e84fc3307..0000000000
--- a/docs/configuration/motion_sensors.md
+++ /dev/null
@@ -1,50 +0,0 @@
-# Configure Motion Sensors
-
-EC sensors are used for the following capabilities:
-
--   Accelerometers in base and lid measure lid angle to toggle between laptop
-    and tablet modes.
--   Ambient light sensors control display backlight level.
--   All sensor types, including gyroscope, e-compass, and pressure, are used by
-    Android apps.
--   Special sync sensor type, synchronizes sensor events with AP.
-
-*TODO* - there is good content available in the most recent [Chrome EC] overview
-presentation that can be added here.
-
-## Config options
-
-*TODO*
-
-## Feature Parameters
-
-*TODO*
-
-## GPIOs and Alternate Pins
-
-*TODO*
-
--   `GPIO_EC_INT_L` - Output from the EC, driven low to indicate an event on the
-    EC is ready for servicing by the AP.
-
-## Data Structures
-
-*TODO*
-
-## Tasks
-
-*TODO*
-
-## Testing and Debugging
-
-*TODO*
-
-### Console Commands
-
-*TODO*
-
-## Example
-
-*TODO*
-
-[Chrome EC]: https://docs.google.com/presentation/d/1Y3PwNSnCQoCqDfL5rYqfaBP_ZqbMOTw_x83_ry4cro8/view#slide=id.g63bdbcea4b_0_27
diff --git a/docs/configuration/template.md b/docs/configuration/template.md
deleted file mode 100644
index be4d2378a5..0000000000
--- a/docs/configuration/template.md
+++ /dev/null
@@ -1,51 +0,0 @@
-# EC Feature Configuration Template
-
-*Short description of the EC feature and the capabilities provided*
-
-## Config options
-
-In [config.h], search for options that start with `CONFIG_<feature>*` and
-evaluate whether each option is appropriate to add to `baseboard.h` or
-`board.h`.
-
-*Note - Avoid documenting `CONFIG_` options in the markdown as `config.h`
-contains the authoritative definition.*
-
-## Feature Parameters
-
-*Detail `CONFIG_*` options that must be assigned to a value for this EC feature
-to compile and operate.*
-
-## GPIOs and Alternate Pins
-
-*Document any hard-coded GPIO enumeration names required by the EC feature.*
-
-*For pins that require an alternate function, note the module required by the EC
-feature.*
-
-## Data Structures
-
-*Document any data structures that must be defined in the board.c or baseboard.c
-files in order for the EC feature to compile and operate.*
-
-*Document any functions that must be implemented in the board.c and baseboard.c
-files.*
-
-## Tasks
-
-*Document any EC tasks that must be enabled by the feature.*
-
-## Testing and Debugging
-
-*Provide any tips for testing and debugging the EC feature.*
-
-### Console Commands
-
-*Document an EC console commands related to the feature.*
-
-## Example
-
-*Optional - provide code snippets from a working board to walk the user through
-all code that must be created to enable this feature.*
-
-[config.h]: ../new_board_checklist.md#config_h
diff --git a/docs/core_runtime.md b/docs/core_runtime.md
deleted file mode 100644
index 4a45136234..0000000000
--- a/docs/core_runtime.md
+++ /dev/null
@@ -1,329 +0,0 @@
-# Chromium OS Embedded Controller Runtime
-
-## Design Principles
-
-1.  Never do at runtime what you can do at compile time The goal is saving flash
-    space and computations. Compile-time configuration until you really need to
-    switch at runtime.
-
-2.  Real-time: guarantee low latency (eg < 20 us) no interrupt disabling ...
-    bounded code in interrupt handlers.
-
-3.  Keep it simple: design for the subset of microcontroller we use targeted at
-    32-bit single core CPU for small systems : 4kB to 64kB data RAM, possibly
-    execute-in-place from flash.
-
-## Execution Contexts
-
-This is a pre-emptible runtime with static tasks. It has only 2 possible
-execution contexts:
-
--   the regular [tasks](#tasks)
--   the [interrupt handlers](#interrupts)
-
-The initial startup is an exception as described in the
-[dedicated paragraph](#startup).
-
-### Tasks
-
-The tasks are statically defined at compile-time. They are described for each
-*board* in the [board/$board/ec.tasklist](../board/host/ec.tasklist) file.
-
-They also have a static fixed priority implicitly defined at compile-time by
-their order in the [ec.tasklist](../board/host/ec.tasklist) file (the top-most
-one being the lowest priority aka *task* *1*). As a consequence, two different
-tasks cannot have the same priority.
-
-In order to store its context, each task has its own stack whose (*small*) size
-is defined at compile-time in the [ec.tasklist](../board/host/ec.tasklist) file.
-
-A task can normally be preempted at any time by either interrupts or higher
-priority tasks, see the [preemption section](#scheduling-and-preemption) for
-details and the [locking section](#locking-and-atomicity) for the few cases
-where you need to avoid it.
-
-### Interrupts
-
-The hardware interrupt requests are connected to the interruption handling *C*
-routines declared by the `DECLARE_IRQ` macros, through some chip/core specific
-mechanisms (e.g. depending on whether we have a vectored interrupt controller,
-slave interrupt controllers...)
-
-The interrupts can be nested (ie interrupted by a higher priority interrupt).
-All the interrupt vectors are assigned a priority as defined in their
-`DECLARE_IRQ` macro. The number of available priority level is
-architecture-specific (e.g. 4 on Cortex-M0, 8 on Cortex-M3/M4) and several
-interrupt handlers can have the same priority. An interrupt handler can only be
-interrupted by a handler having a priority **strictly** **greater** than its
-own.
-
-In most cases, the exceptions (e.g data/prefetch aborts, software interrupt) can
-be seen as interrupts with a priority strictly greater than all IRQ vectors. So
-they can interrupt any IRQ handler using the same nesting mechanism. All fatal
-exceptions should ultimately lead to a reboot.
-
-### Events
-
-Each task has a *pending* events bitmap[1] implemented as a 32-bit word. Several
-events are pre-defined for all tasks, the most significant bits on the 32-bit
-bitmap are reserved for them : the timer pending event on bit 31
-([see the corresponding section](#time)), the requested task wake (bit 29), the
-event to kick the waiters on a mutex (bit 30), along with a few hardware
-specific events. The 19 least significant bits are available for task-specific
-meanings.
-
-Those event bits are used in inter-task communication and scheduling mechanism,
-other tasks **and** interrupt handlers can atomically set them to request
-specific actions from the task. Therefore, the presence of pending events in a
-task bitmap has an impact on its scheduling as described in the
-[scheduling section](#scheduling-and-preemption). These requests are done using
-the `task_set_event()` and `task_wake()` primitives.
-
-The two typical use-cases are:
-
--   a task sends a message to another task (simply use some common memory
-    structures [see explanation](#single-address-space) and want it to process
-    it now.
--   a hardware IRQ occurred, and we need to do some long processing to respond
-    to it (e.g. an I2C transaction). The associated interrupt handler cannot do
-    it (for latency reason), so it will raise an event to ask a task to do it.
-
-The task code chooses to consume them (or a subset of them) when it's running
-through the `task_wait_event()` and `task_wait_event_mask()` primitives.
-
-### Scheduling and Preemption
-
-The system has a global bitmap[1] called `tasks_ready` containing one bit per
-task and indicating whether it is *ready* *to* *run* (ie want/need to be
-scheduled). The task ready bit can only be cleared when it's calling itself one
-of the functions explicitly triggering a re-scheduling (e.g. `task_wait_event()`
-or `task_set_event()`) **and** it has no pending event. The task ready bit is
-set by any task or interrupt handler setting an event bit for the task (ie
-`task_set_event()`).
-
-The scheduling is based on (and *only* on) the `tasks_ready` bitmap (which is
-derived from all the events bitmap of the tasks as explained above).
-
-Then, the scheduling policy to find which task should run is just finding the
-most significant bit set in the tasks_ready bitmap and schedule the
-corresponding task.
-
-Important note: the re-scheduling happens **only** when we are exiting the
-interrupt context. It is done in a non-preemptible context (likely with the
-highest priority). Indeed, a re-scheduling is actually needed only when the
-highest priority task ready has changed. There are 3 distinct cases where this
-can happen:
-
--   an interrupt handler sets a new event for a task. In this case,
-    `task_set_event` will detect that it is executed in interrupt context and
-    record in the `need_resched_or_profiling` variable that it might need to
-    re-schedule at interrupt return. When the current interrupt is going to
-    return, it will see this bit and decide to take the slow path making a new
-    scheduling decision and eventually a context switch instead of the fast path
-    returning to the interrupt task.
--   a task sets an event on another task. The runtime will trigger a software
-    interrupt to force a re-scheduling at its exit.
--   the running task voluntarily relinquish its current execution rights by
-    calling `task_wait_event()` or a similar function. This will call the
-    software interrupt similarly to the previous case.
-
-On the re-scheduling path, if the highest-priority ready task is not matching
-the currently running one, it will perform a context-switch by saving all the
-processor registers on the current task stack, switch the stack pointer to the
-newly scheduled task, and restore the registers from the previously saved
-context from there.
-
-### Hooks and Deferred Functions
-
-The lowest priority task (ie Task 1, aka TASK_ID_HOOKS) is reserved to execute
-repetitive actions and future actions deferred in time without blocking the
-current task or creating a dedicated task (whose stack memory allocation would
-be wasting precious RAM).
-
-The HOOKS task has a list of deferred functions and their next deadline. Every
-time it is waken up, it runs through the list and calls the ones whose deadline
-is expired. Before going back to sleep, it arms a timer to the closest deadline.
-The deferred functions can be created using the `DECLARED_DEFERRED()` macro.
-Similarly, the HOOK_SECOND and HOOK_TICK hooks are called periodically by the
-HOOKS task loop (the *tick* duration is platform-defined and shorter than the
-second).
-
-Note: be specially careful about priority inversions when accessing resources
-protected by a mutex (e.g. a shared I2C controller) in a deferred function.
-Indeed being the lowest priority task, it might be de-scheduled for long time
-and starve higher priority tasks trying to access the resource given there is no
-priority boosting implemented for this case. Also, be careful about long delays
-(> x 100us) in hook or deferred function handlers, since those will starve other
-hooks of execution time. It is better to implement a state machine where you set
-up a subsequent call to a deferred function than have a long delay in your
-handler.
-
-### Watchdog
-
-The system is always protected against misbehaving tasks and interrupt handlers
-by a hardware watchdog rebooting the CPU when it is not attended.
-
-The watchdog is petted in the HOOKS task, typically by declaring a HOOK_TICK
-doing it as regular intervals. Given this is the lowest priority task, this
-guarantees that all tasks are getting some run time during the watchdog period.
-
-Note: that's also why one should not sprinkle its code with `watchdog_reload()`
-to paper over long-running routine issues.
-
-To help debug bad sequences triggering watchdog reboots, most platforms
-implement a warning mechanism defined under `CONFIG_WATCHDOG_HELP`. It's a timer
-firing at the middle of the watchdog period if it hasn't been petted by then,
-and dumping on the console the current state of the execution mainly to help
-find a stuck task or handler. The normal execution is resumed though after this
-alert.
-
-### Startup
-
-The startup sequence goes through the following steps:
-
--   the assembly entry routine clears the .bss (uninitialized data), copies the
-    initialized data (and optionally the code if we are not executing from
-    flash), sets a stack pointer.
--   we can jump to the `main()` C routine at this point.
--   then we go through the hardware pre-init (before we have all the clocks to
-    run the peripherals normal) and init routines, in this rough order: memory
-    protection if any, gpios in their default state, prepare the interrupt
-    controller, set the clocks, then timers, enable interrupts, init the debug
-    UART and the watchdog.
--   finally, start tasks.
-
-For the tasks startup, initially only the HOOKS task is marked as ready, so it
-is the first to start and can call all the HOOK_INIT handlers performing
-initializations before actually executing any real task code. Then all tasks are
-marked as ready, and the highest priority one is given the control.
-
-During all the startup sequence until the control is given the first task, we
-are using a special stack called 'system stack' which will be later re-used as
-the interrupts and exception stack.
-
-To prepare the first context switch, the code in `task_pre_init()` is stuffing
-all the tasks stacks with a *fake* saved context whose program counter contains
-the task start address, and the stack pointer is pointing to its reserved stack
-space.
-
-### Locking and Atomicity
-
-The two main concurrency primitives are lightweight atomic variables and heavier
-mutexes.
-
-The atomic variables are 32-bit integers (which can usually be loaded/stored
-atomically on the architecture we are supporting). The `atomic.h` headers
-include primitives to do atomically various bit and arithmetic operations using
-either load-linked/load-exclusive, store-conditional/store-exclusive or simple
-depending on what is available.
-
-The mutexes are actually statically allocated binary semaphores. In case of
-contention, they will make the waiting task sleep (removing its ready bit) and
-use the [event mechanism](#events) to wake-up the other waiters on unlocking.
-
-Note: the mutexes are NOT triggering any priority boosting to avoid the priority
-inversion phenomenon.
-
-Given the runtime is running on single core CPU, spinlocks would be equivalent
-to masking interrupts with `interrupt_disable()` spinlocks, but it's strongly
-discouraged to avoid harming the real-time characteristics of the runtime.
-
-## Time
-
-### Time Keeping
-
-In the runtime, the time is accounted everywhere using a **64-bit**
-**microsecond** count since the microcontroller **cold** **boot**.
-
-Note: The runtime has no notion of wall-time/date, even though a few platforms
-have an RTC inside the microcontroller.
-
-These microsecond timestamps are implemented in the code using the `timestamp_t`
-type, and the current timestamp is returned by the `get_time()` function.
-
-The time-keeping is preferably implemented using a 32-bit hardware free running
-counter at 1Mhz plus a 32-bit word in memory keeping track of the high word of
-the 64-bit absolute time. This word is incremented by the 32-bit timer rollback
-interrupt.
-
-Note: as a consequence of this implementation, when the 64-bit timestamp is read
-in interrupt context in a handler having a higher priority than the timer IRQ
-(which is somewhat rare), the high 32-bit word might be incoherent (off by one).
-
-### Timer Event
-
-The runtime offers *one* (and only one) timer per task. All the task timers are
-multiplexed on a single hardware timer. (can be just a *match* *interrupt* on
-the free running counter mentioned in the [previous paragraph](#time-keeping))
-Every time a timer is armed or expired, the runtime finds the task timer having
-the closest deadline and programs it in the hardware to get an interrupt. At the
-same time, it sets the TASK_EVENT_TIMER event in all tasks whose timer deadline
-has expired. The next deadline is computed in interrupt context.
-
-Note: given each task has a **single** timer which is also used to wake-up the
-task when `task_wait_event()` is called with a timeout, one needs to be careful
-when using directly the `timer_arm()` function because there is an eventuality
-that this timer is still running on the next `task_wait_event()` call, the call
-will fail due to the lack of available timer.
-
-## Memory
-
-### Single Address Space
-
-There is no memory isolation between tasks (ie they all live in the same address
-space). Some architectures implement memory protection mechanism albeit only to
-differentiate executable area (eg `.code`) from writable area (eg `.bss` or
-`.data`) as there is a **single** **privilege** level for all execution
-contexts.
-
-As all the memory is implicitly shared between the task, the inter-task
-communication can be done by simply writing the data structures in memory and
-using events to wake the other task (given we properly thought the concurrent
-accesses on those structures).
-
-### Heap
-
-The data structure should be statically allocated at compile time.
-
-Note: there is no dynamic allocator available (e.g. `malloc()`), not due to
-impossibility to create one but to avoid the negative side effects of having
-one: ie poor/unpredictable real-time behavior and possible leaks leading to a
-long-tail of failures.
-
--   TODO: talk about shared memory
--   TODO: where/how we store *panic* *memory* and *sysjump* *parameters*.
-
-### Stacks
-
-Each task has its own stack, in addition there is a system stack used for
-startup and interrupts/exceptions.
-
-Note 1: Each task stack is relatively small (e.g. 512 bytes), so one needs to be
-careful about stack usage when implementing features.
-
-Note 2: At the same time, the total size of RAM used by stacks is a big chunk of
-the total RAM consumption, so their sizes need to be carefully tuned. (please
-refer to the [debugging paragraph](#debugging) for additional input on this
-topic.
-
-## Firmware Code Organization and Multiple Copies
-
--   TODO: Details the classical RO / RW partitions and how we sysjump.
-
-## Power Management
-
--   TODO: talk about the idle task + WFI (note: interrupts are disabled!)
--   TODO: more about low power idle and the sleep-disable bitmap
--   TODO: adjusting the microsecond timer at wake-up
-
-## Debugging
-
--   TODO: our main tool: serial console ... (but non-blocking / discard
-    overflow, cflush DO/DONT)
--   TODO: else JTAG stop and go: careful with watchdog and timer
--   TODO: panics and software panics
--   TODO: stack size tuning and canarying
-
--   TODO: Address the rest of the comments from https://crrev.com/c/445941
-
-\[1]: bitmap: array of bits.
diff --git a/docs/detachable_base_verified_boot.md b/docs/detachable_base_verified_boot.md
deleted file mode 100644
index c1eec3fc0b..0000000000
--- a/docs/detachable_base_verified_boot.md
+++ /dev/null
@@ -1,432 +0,0 @@
-# Detachable Base Verified Boot
-
-Authors: rspangler@google.com, drinkcat@google.com
-
-Last Updated: 2016-11-16
-
-Original: http://go/detachable-base-vboot
-
-[TOC]
-
-## Introduction
-
-### What's a Base?
-
-Detachable Chromebooks such as `Poppy` have a tablet-like `Lid` and a detachable
-keyboard `Base`. Effectively, the `Base` is a USB keyboard+trackpad which plugs
-into the `Lid`.
-
-The `Lid` contains most of the components, including:
-
-*   AP
-*   ECDisplay
-*   Storage
-*   Battery
-
-The `Base` connects to the `Lid` via USB pogo pins, and contains:
-
-*   EC ([STM32F072]). To minimize confusion with the main EC in the `Lid`, this
-    will always be called the `BaseEC`.
-*   Matrixed keyboard
-*   Touchpad
-
-The `Base` always gets its power from the `Lid` USB port. This means that
-attaching the base always triggers a power-on reset.
-
-### Verified Boot Requirements
-
-The `BaseEC` will be responsible for handling user input from the keyboard and
-touchpad. This means that a compromised `BaseEC` could implement a keylogger. To
-prevent this, we will use verified boot to protect the `BaseEC` firmware.
-
-We need a way to securely update the `BaseEC` firmware from the AP. We cannot
-use EC Software Sync as implemented on existing Chromebooks (and as still used
-in the `Lid`) because the `Base` cannot trust that it is talking to an official
-`Lid` firmware/OS. All the Base knows is that _something_ on the other end of
-USB is trying to send it an update. So the BaseEC will need to do its own public
-key verification of the firmware update. This includes rollback protection.
-
-Updating the `BaseEC` firmware should not require rebooting the lid. This means
-the update will take place after the OS has already booted on the lid. Ideally,
-it should also not require the user to detach/reattach the base during the
-update process. If the update takes longer than a few seconds, we should tell
-the user, because the keyboard and trackpad will be unavailable during the
-update.
-
-The solution should also have low (or no) BOM cost, and minimal flash size
-requirement.
-
-## Proposal
-
-`BaseEC` RO region includes a public key, whose private counterpart is kept
-safely on our signers. On boot, RO checks RW signature (RW image is signed by
-our signers), and will only jump to RW if the signature is valid.
-
-We also include a rollback region (RB) to implement rollback protection (and
-prevent rollback to a correctly signed, but compromised, RW). This region can
-only be updated by RO.
-
-We also devise a scheme to update RW firmware (the details are documented in
-[EC Update over USB]).
-
-Note: This proposal is very specific to the STM32 flash architecture. Other ECs
-(particularly ones with external SPI flash) may need additional external logic
-and/or a I2C EEPROM to hold the rollback info block.
-
-### Flash
-
-STM32F072 has 128KB flash, with 2KB erase sectors and 4KB protection blocks.
-
-We will divide flash into three sections:
-
-*   `BaseEC`-RO firmware.
-    *   Not updatable in production.
-    *   Only capable of USB update, not keyboard/trackpad.
-    *   Contains public key to verify RW image (RSA-3072).
-*   `BaseEC`-RW firmware.
-    *   Fully functional.
-    *   Updatable from AP.
-    *   Signature (SHA-256 + RSA-3072).
-*   `BaseEC`-RB: Rollback info block (4KB).
-    *   Contains minimum RW version that RO will accept to jump to.
-    *   Updatable from RO.
-
-Each of those sections can be locked independently: In production, RO is always
-locked, and only RO can write to RB (RO will always make sure to lock RB before
-jumping to RW).
-
-Flash protection is a little entertaining on STM32:
-
-*   The flash protection bits for the \*next\* boot are stored in a non-volatile
-    `WRPx` register (in EC code, this is abstracted as
-    `EC_FLASH_PROTECT_[REGION]_AT_BOOT` flags)..
-*   On chip reset, `WRPx` is copied into a read-only `FLASH_WRPR` register; that
-    controls which blocks are protected for this boot. This is abstracted as
-    `EC_FLASH_PROTECT_[REGION]_NOW` in the EC code.
-
-### Rollback Info Block
-
-The Rollback Info Block (aka "RB") is a 4KB block of flash.
-
-It has two 2KB erase sectors. We will ping-pong writes to those sectors, so that
-interrupting power during an erase-write cannot cause data loss. If both sectors
-are valid, the stricter (i.e. the highest value) of the 2 sectors is used.
-
-We will use the RB to hold the following:
-
-*   Minimum **RW rollback firmware** version: a 32-bit integer. Used for
-    rollback protection. This number is independent of the actual EC version,
-    and is stored a 32-bit integer as part of the `BaseEC`-RW region (see
-    [CL:452815] for a possible implementation)
-*   A magic signature that indicates that the RB section is valid.
-
-### RO Verified Boot Flow
-
-#### Write-Protect RO think test before this handles corrupt RW.
-
-Write protect of RO firmware works the same way it does now:
-
-*   Early RO code looks at a write protect (WP) GPIO and a global PSTATE
-    variable (part of the RO image itself). When we switch to RO that contains
-    the MP key, we set the PSTATE to locked.
-*   If both of those are set:
-    *   RO code sets `EC_FLASH_PROTECT_RO_AT_BOOT` to protect itself. This
-        ensures RO code is never writable past this point.
-    *   If `_AT_BOOT` flags protects more than the current write protect range
-        (`_NOW` flags), RO reboots so that changes take effect.
-*   Otherwise, someone has physically disconnected WP. Set `WRPx=0` to unprotect
-    all flash and reboot.
-
-#### Check if AP Wants To Update RW
-
-Next, RO needs to find out if the AP wants to update RW. RO initializes USB and
-starts a 1 second timer to give the AP an opportunity to send a command before
-RO jumps to RW. This delay gives us a way to regain control of the base, if the
-previous RW firmware is properly signed but bad/nonfunctional.
-
-That command can be:
-
-*   `STOP_IN_RO`: Yes, I might want to update you. Stick around.
-    *   `UNLOCK_RW`: Tells EC to unlock RW region, if it is currently locked, so
-        that it can be reprogrammed. This also locks RB region. EC reboots if
-        needed.
-*   `JUMP_TO_RW`: No, I don't want to update you. Go ahead and jump to your RW
-    code if it verifies.
-
-RO will start verifying RW while it waits for the AP to send it a command or for
-the timeout. If a command is received, RO will stop the 1-second timer, and wait
-for more commands from the AP. This allows the AP to update RW.
-
-Verifying RW will take ~200 ms, and the AP should be able to send a command to
-the base within ~100 ms of it appearing on USB, so this check should not cause
-any delay to the base's boot process.
-
-#### Verify RW
-
-RO calculates the hash of RW.
-
-*   Use the public key stored in RO to check if the hash matches the RSA-signed
-    RW signature. On failure, go back to waiting for an update from the AP.
-*   Check the RW rollback version against the stored minimum version in RB. If
-    the RW version is too low, fail. Go back to waiting for an update from the
-    AP.
-*   If RO is protected, then also set `EC_FLASH_PROTECT_RW_AT_BOOT` so that RW
-    will be protected on the next boot, the reboot.
-
-#### Roll Forward
-
-If `EC_FLASH_PROTECT_ROLLBACK_NOW` is set (RB is protected), do not attempt to
-roll forward. We know RW firmware is properly signed, but not if it's
-functional.
-
-If `EC_FLASH_PROTECT_ROLLBACK_NOW` is not set (RB is unprotected), \_and\_ the
-RW signature is correct, then update RB:
-
-*   Erase/write the older sector of RB.
-*   Set the stored minimum version to the RW rollback version.
-*   If RO is protected, then also set `EC_FLASH_PROTECT_ROLLBACK_NOW` so that RB
-    will be protected on the next boot.
-
-#### Jump to RW
-
-If the 1-second timer for the AP to send a command to RO has not expired, RO
-waits for it to expire or the AP to send a command, whichever happens first.
-
-If RB or RW is unprotected (`EC_FLASH_PROTECT_RW/ROLLBACK_NOW` are not set),
-protect it and reboot (we never want RW to be able to update RB on its own).
-
-Otherwise, jump to RW firmware.
-
-### RW Verified Boot Flow
-
-RW firmware provides the keyboard and trackpad functionality.
-
-#### AP Wants To Update RW
-
-At some point the AP may want to update RW. To do so, it sends `UNLOCK_RW`
-command, to ask RW to unlock itself and reboot, then follow the update steps
-above.
-
-#### AP Wants to Roll Forward RW
-
-After the update, the base boots to the new RW firmware. At that point, the AP
-knows the new RW firmware is good enough to talk to, so it tells RW to prepare
-for roll forward.
-
-*   `UNLOCK_ROLLBACK` command: RW unprotects RB.
-*   On next boot (not necessarily urgent, but can be forced), RO will update RB
-    according to the steps above.
-
-### Write Protect GPIO
-
-The `BaseEC` needs a write protect (WP) GPIO signal to decide whether to keep RO
-firmware protected or not. This is the same requirement as on existing ECs.
-
-In an assembled base, the WP signal will be physically asserted. De-asserting
-the signal requires disassembling the base and disconnecting something.
-
-Typically, the `BaseEC` will apply a weak pull-up to the WP GPIO; the presence
-of the WP screw/flex will short the pin to ground.
-
-#### RO Updates During Development
-
-If RO is unprotected (i.e. during development), RW can also update it.
-
-If the key is \_not\_ the same (dev->premp, premp->mp updates) we can't update
-RW first (it won't verify). These steps should work though, if current RW is
-recent enough and stable enough to update RO:
-
-*   Make sure RW is active
-*   Update RO, reboot
-*   Update RW from RO
-
-If the key is the same, we can update RW first.
-
-### Signer, image format, and verification process
-
-Memory map:
-
-RO                                                | RB  | RW
-------------------------------------------------- | --- | ---
-`...` \| `Public key` \| `...` \| `FMAP` \| `...` |     | `EC code and data` \| `Blank (0xff)` \| `Signature`
-
-*   RO contains an embedded RSA public key (`vb21_packed_key` format), at a
-    variable location.
-*   RW contains a signature (`vb21_signature`), packed at the end of the RW
-    region.
-    *   The signature also contains the actual length of the EC code and image
-        (ignoring 0xff padding)
-    *   RO validates signature against the provided length, then checks that the
-        rest of the RW region (up to the signature itself) is filled with ones
-        (padding).
-        *   This speeds up verification significantly, as SHA-256 is an
-            expensive process.
-*   RO contains an FMAP that allows futility to find the RO key, RW region, and
-    RW signature location.
-
-For re-signing, `futility` (rwsig type) does this:
-
-*   Look for FMAP to find RO public key RW region, and RW signature locations.
-*   Resign RW region, using the length provided in existing RW signature.
-*   Replace RO public key with the one used for signing.
-
-`vb21_packed_key` (public key) has a field for key version, that we can use to
-increment from dev keys, to premp, and final mp keys. BaseEC will need to report
-the key version, to avoid incorrect updates.
-
-## Example Boot / Update Flows
-
-The base starts in the following state:
-
-*   Powered off
-*   WP GPIO is asserted
-*   PSTATE is set to protect RO firmware
-*   RW firmware is valid, and currently version M
-*   `EC_FLASH_PROTECT_[REGION]_AT_BOOT/_NOW` protects RO+RW+RB (that is,
-    everything)
-
-All AP operations are done from the `Lid` OS.
-
-Base updates will interrupt keyboard/trackpad functionality, so the user should
-be informed when an update is taking place.
-
-Reboots of the `Base` do not cause or require reboots of the `Lid`, do not
-require action on the part of the user, and will not be visible to the user
-(other than the previously noted lack of functionality).
-
-### Power On, No Update
-
-Step                                                                                          | RW  | RB contents | `_AT_BOOT` | `_NOW`
---------------------------------------------------------------------------------------------- | --- | ----------- | ---------- | ------
-(initial state)                                                                               | M   | 1/blank     | RO/RW/RB   | RO/RW/RB
-1. RO waits 1 second for an update request from AP                                            |     |             |            |
-2. RO verifies RW signature => RW is good                                                     |     |             |            |
-3. RO notes that `_AT_BOOT` and `_NOW` already protect everything, so no reboot is necessary. |     |             |            |
-4. RO jumps to RW                                                                             |     |             |            |
-
-### Updating RW
-
-Assume AP now has a new `BaseEC`-RW, version N>M. The base is already running RW
-version M. In this card, the rollback version in both version is identical
-("1"), so RB does not require an update.
-
-Step                                                    | RW  | RB contents | `_AT_BOOT`     | `_NOW`
-------------------------------------------------------- | --- | ----------- | -------------- | ------
-RW is running                                           | M   | 1/blank     | RO/RW/RB       | RO/RW/RB
-AP tells RW to prepare for an update (UNLOCK_RW)        |     |             |                |
-RW unsets `EC_FLASH_PROTECT_RW_AT_BOOT` to unprotect RW |     |             | **RO/\_\_/RB** |
-RW reboots to update `EC_FLASH_PROTECT_RW_NOW`          |     |             |                | **RO/\_\_/RB**
-
-The next base boot is where the update takes place:
-
-Step                                                                                                                                                             | RW    | RB contents | `_AT_BOOT`   | `_NOW`
----------------------------------------------------------------------------------------------------------------------------------------------------------------- | ----- | ----------- | ------------ | ------
-RO waits 2 seconds for an update request from the AP                                                                                                             | M     | 1/blank     | RO/\_\_/RB   | RO/\_\_/RB
-AP tells RO an update is coming (`STOP_IN_RO`)                                                                                                                   |       |             |              |
-AP tells the user that a base update is taking place. UI should say: "Please don't be surprised that your keyboard and trackpad won't work for a few seconds..." |       |             |              |
-AP writes RW version N                                                                                                                                           | **N** |             |              |
-AP tells RO to reboot (`IMMEDIATE_RESET`)                                                                                                                        |       |             |              |
-RO reboots, verifies RW signature => RW is good                                                                                                                  |       |             |              |
-RO checks RW rollback version N (1) and sees it's greater or equal than RB rollback version 1. So, RW is good.                                                   |       |             |              |
-RO sets `RW_AT_BOOT` to protect RW on the next boot.                                                                                                             |       |             | **RO/RW/RB** |
-RO reboots                                                                                                                                                       |       |             |              | **RO/RW/RB**
-
-The next base boot is where we first run the new RW firmware.
-
-### Roll forward
-
-Now let's assume we followed the steps above, and we now have a RW version O
-that has rollback version 2.
-
-Step                                                                                                           | RW    | RB contents | `_AT_BOOT`     | `_NOW`
--------------------------------------------------------------------------------------------------------------- | ----- | ----------- | -------------- | ------
-RO verifies RW signature => RW is good                                                                         | **O** | 1/blank     | RO/RW/RB       | RO/RW/RB
-RO checks RW rollback version O (2) and sees it's greater or equal than RB rollback version 1. So, RW is good. |       |             |                |
-RO jumps to RW                                                                                                 |       |             |                |
-AP is satisfied that the base works, so it tells RW to prepare for a                                           |       |             |                |
-roll-forward (`UNLOCK_ROLLBACK`)                                                                               |       |             |                |
-RW unsets `ROLLBACK_AT_BOOT`                                                                                   |       |             | **RO/RW/\_\_** |
-RW may reboot (or just wait for next reattach)                                                                 |       |             |                | **RO/RW/\_\_**
-
-On next boot, RB will be updated:
-
-Step                                                                                                                                      | RW  | RB contents | `_AT_BOOT`   | `_NOW`
------------------------------------------------------------------------------------------------------------------------------------------ | --- | ----------- | ------------ | ------
-RO verifies RW signature => RW is good                                                                                                    | O   | 1/blank     | RO/RW/\_\_   | RO/RW/\_\_
-RO sees that RB is unprotected, and sees RW rollback version O (2) and sees is greater than RB rollback version 1. So RB needs an update. |     |             |              |
-RO updates RB's second block                                                                                                              | O   | **1/2**     |              |
-RO sets `ROLLBACK_AT_BOOT` to protect RB on the next boot.                                                                                |     |             | **RO/RW/RB** |
-RO reboots.                                                                                                                               |     |             |              | **RO/RW/RB**
-
-## Details
-
-### STM32 Flash Protection
-
-At a high level, flash protection works on the STM32F072 chip works in the
-following manner:
-
-*   128KB flash total flash, organized as 32 independently protectable 4KB
-    blocks. Each block has 2 independently erasable 2KB sectors.
-*   `FLASH_WRPR` is the register controlling flash write protect of these
-    blocks. It is not directly writable. In EC common code, these bits are
-    abstracted as `EC_FLASH_PROTECT_[REGION]_NOW`.
-*   Instead, there is a non-volatile register called `WRPx`, which is stored in
-    a separate information block of flash. This is always writable. In EC common
-    code, these bits are abstracted as `EC_FLASH_PROTECT_[REGION]_AT_BOOT`. On
-    chip reset, `WRPx` is copied to the `FLASH_WRPR` register.
-
-Here's the interesting part. The only way to change read-only firmware is to
-change `WRPx` and then reset the chip, so that `WRPx` is copied into
-`FLASH_WRPR`. At that point, read-only firmware could be writable. But that same
-reset also transfers control back to the read-only firmware. If the read-only
-firmware doesn't want to be writable, all it has to do is change `WRPx` back to
-protect itself, and then reboot again. We do that already on all devices which
-use the STM32 chips.
-
-Flash protection works similarly on other STM32F chips, if we need to move to a
-larger or more capable EC for the base to support a more complex base.
-
-### Flash Contents
-
-The 128KB `BaseEC` flash will be divided into three parts.
-
-*   Read-only firmware (`Base`-EC-RO, or just "RO" in this document)
-    *   ~40KB
-    *   Minimal functionality, so it can be small.
-    *   Verifies the rewritable firmware.
-    *   Updates the rewritable firmware over USB.
-    *   Does NOT have keyboard or trackpad support.
-    *   Includes the `Base-EC` root key.
-*   Rewritable firmware (`Base-EC`-RW, or just "RW" in this document)
-    *   ~84KB
-    *   Supports keyboard and trackpad.
-    *   Trackpad drivers may be non-trivial in size.
-    *   Future bases may include type-C ports, sensors, or batteries, all of
-        which will increase RW size.
-    *   As with the main EC, it is unlikely we will have space for multiple
-        copies of RW (so, no RW-A and RW-B).
-    *   Updates the read-only firmware over USB (pre-production devices only).
-*   Rollback block (`Base-EC`-RB, or just "RB" in this document)
-    *   4KB (one protection block)
-    *   Contains rollback version information for RW
-    *   Only writable by RO.
-    *   Updates alternate between the 2 2KB erase sectors. We only erase one of
-        them at a time, so an interrupted erase/write will not cause data loss.
-
-Adding the RB will decrease the total amount of flash available for RO and RW,
-but doesn't require any additional external components. This is acceptable
-because RO will be smaller (since it only has update/verify functionality).
-
-### Verification Speed
-
-On a STM32F072 chip running at 48 MHz,
-
-*   SHA-256 of a 64KB RW image takes 200 ms (~3 ms/KB)
-    *   Reducing RW image size reduces verification time almost proportionally
-        (even if we need to check that the rest of the image is erased).
-*   RSA-2048 (exponent 3) signature verification takes ~50 ms
-*   RSA-3072 (exponent 3) signature verification takes ~100 ms
-
-[STM32F072]: http://www.st.com/content/ccc/resource/technical/document/reference_manual/c2/f8/8a/f2/18/e6/43/96/DM00031936.pdf/files/DM00031936.pdf
-[EC Update over USB]: ./usb_updater.md
-[CL:452815]: https://chromium-review.googlesource.com/c/452815/2
diff --git a/docs/ec-3po-design.md b/docs/ec-3po-design.md
deleted file mode 100644
index 79ec3ecf0f..0000000000
--- a/docs/ec-3po-design.md
+++ /dev/null
@@ -1,326 +0,0 @@
-# EC-3PO: The EC console interpreter
-
-[TOC]
-
-## Introduction
-
-Today, the Chromium OS Embedded Controller (EC) has a very rich debug console
-that is very helpful and has features including command history, editing,
-timestamps, channels and much more. However, all of these features currently use
-up valuable flash space that a number of our boards desperately need. We
-constantly run into this problem where boards are running out of space and
-people have to hack out a lot of code just so the image will fit. It's been
-occurring with more frequency lately and I imagine it will continue to occur as
-we add more features to our EC code base. What we could do instead is move all
-of that console functionality out to a separate utility and turn the EC console
-into a binary mode which would only speak in host command packets and debug
-output packets. EC-3PO would serve as the interpreter translating from the
-traditional EC console that we all know and love to host command packets sent
-down to the EC and vice versa.
-
-## Benefits
-
-The benefits to be gained are numerous and can all occur without changing
-people's existing workflow. The only slight impact might be that we instruct
-people to `emerge hdctools` every so often. All people would notice would be
-that the EC images would be getting smaller and/or more console features.
-
-### Testing & FAFT
-
-Currently, [FAFT](https://www.chromium.org/for-testers/faft) runs its tests
-while trying to parse strings from the EC console. This method can be fairly
-fragile as debug output can be interleaved with the console input. A lot of
-items could be improved by switching to this host command packet interface.
-
-*   Communicating in packets makes testing easier and more robust.
-    *   When FAFT is running, the EC could be in a binary mode where it only
-        communicates in host command packets. These packets are easier to parse,
-        create, and filter on.
-    *   With filtering, you get the added bonus of not having unwanted debug
-        output.
-    *   It allows us to really test the host command interface which is how the
-        EC talks to the AP anyways.
-*   Better testing of existing host command handlers.
-    *   By speaking in host command packets, we can reuse the existing host
-        command handlers which is nice since we'll be using the same handlers
-        that are used to respond to the AP.
-*   FAFT would no longer have to worry about the console dropping characters.
-    *   We can add error checking to the interpreter which would automatically
-        retry errors. This alleviates FAFT from trying to check if the EC had
-        properly received a line of input. (Ctrl+L)
-
-With better and more reliable tests, we can improve the quality of our EC
-codebase.
-
-### Space Savings
-
-By moving the console functionality off of the EC, we would be able to shave off
-a considerable amount of bytes from the EC images. People wouldn't have to worry
-as much about creating a debug console print with the fear of bloating up the
-image size. Smaller stack requirements by changing `printf` formatting to only
-count bytes while moving common strings off the EC. Additionally, most of these
-savings will come for free as it will apply to every EC with a console. We won't
-be restricted by the type of chip.
-
-### A richer EC console
-
-*   We could do things like on-the-fly console channel filtering.
-*   Coloring specific channels such as "mark all USB PD messages in green".
-*   Adding colors in general.
-*   Adding temporary console commands.
-*   Longer command history which survives EC reboot
-*   Searching command history
-*   Redirecting debug output to log files (which causes no interleaving of
-    command and debug output)
-*   Bang commands (`!foo`)
-
-### Better debuggability
-
-Sometimes, there will be an issue with the EC (or believed to be an EC issue)
-such as the keyboard locking up on certain keys or rows. At times like that, it
-would be nice to have an EC console to see what's going on. Other times maybe
-having a servo connected might make the issue not present itself.
-
-*   We could do cool things like having an EC console without having to hook up
-    servo.
-*   Run `ectool` from the chroot using a PTY interface.
-
-## Deployment Strategy
-
-There are many facets to this feature, but here's a deployment strategy which
-will gradually take us from the current EC console today, to a future where the
-console is completely removed from the EC. The goal will be to make this change
-as transparent as possible to developers.
-
-### Phase 1: Insertion
-
-_[[Merged to ToT](https://crrev.com/c/320629) on 2016-02-07]_
-
-Phase 1 will most likely consist of getting EC-3PO in place in between servo and
-the EC while not modifying the behavior of the console too much. In this phase,
-we can replicate the console interface and achieve the following things.
-
-*   Replicate command editing.
-*   Save command history.
-*   Add error checking to the console commands.
-
-### Phase 2: Assimilation
-
-Phase 2 will start to introduce the host command packet communication.
-
-*   Printing will be done via packets and assembled in EC-3PO.
-*   Console commands now are sent using the host command packets.
-    *   This will be incremental as console commands are converted.
-*   Add debug output filtering and redirection/logging.
-
-### Phase 3: Expansion
-
-Phase 3 will expand the feature set of EC-3PO.
-
-*   Add PTY interface to `ectool`.
-*   Add on-device console without `servod`.
-*   Colored output.
-*   Command history search.
-*   Bang commands (`!foo`)
-
-## High Level Design & Highlights
-
-![Diagram with three boxes. EC-3PO with an incoming PTY communicates with the
-Serial Driver over another PTY. The Serial Driver communicates with the EC
-UART.](./images/ec-3po-high-level-design.png)
-
-### EC Interface
-
-Each host command is a 16-bit command value. Commands which take parameters or
-return response data specify `struct`s for that data. See
-[`include/ec_commands.h`](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/include/ec_commands.h)
-for the current format of request and replies. Currently, there are no changes
-made to the format of the host request and response structures.
-
-On the EC, we essentially need to create a UART host command handler. This
-handler will be watching the console input for a byte sequence to switch into
-this host command mode. The starting sequence for an incoming host command
-packet will be `0xDA`, a byte signifying `EC_COMMAND_PROTOCOL_3`. Once this byte
-is seen, the EC will transition to its "host command processing mode" and
-receive the host command. It will then process the host command, send the binary
-host response, and then transition back into normal mode. Ideally, there should
-be some locking of the UART to prevent other writes while this is taking place.
-
-By the end of the assimilation (Phase 2), there would be no "normal mode" and
-everything would be in the binary host command mode.
-
-### Host Interface
-
-The host interface is where the bulk of the work will be. This will be
-converting from the received host commands to console prints as well as
-converting the console inputs to host commands. It will also be responsible for
-replicating the console. This includes things like moving back and forth for
-command editing.
-
-The interpreter should also open a PTY and `dut-control` should return this PTY
-as the `ec_uart_pty`. This is to ensure that the change is as transparent as
-possible to developers.
-
-### Features
-
-The following are an explanation of a few of the planned features.
-
-#### Command Error Checking
-
-EC-3PO and the EC can perform error checking when sending the commands to the
-EC. This feature would be implemented prior to switching to the binary format.
-The interpreter can package the command in the following manner.
-
-*   2 Ampersands
-*   2 hex digits representing the length of the command
-*   2 hex digits representing the CRC-8 of the command
-*   1 Ampersand
-*   The command itself
-*   2 newline characters.
-
-This is robust because no commands currently start with `&`. If the EC does not
-see ‘`&&`', then one of the ampersands has been dropped. If the EC doesn't see
-an ampersand after 4 hex digits, it either dropped a hex digit or the ampersand.
-Two newlines, so dropping one of those is alright. Once the EC gets the command
-and newline, it can verify the command string hasn't been corrupted.
-
-In the event that the command string was corrupted, the EC can return an error
-string back of `&&EE`. If the translator reads a line with at least one
-ampersand followed by one "E", then an error had occurred and the translator can
-simply retry the console command. This creates a reliable input to the console,
-a great win for FAFT.
-
-#### PTY interface to `ectool`
-
-Once the UART host command handler is functional, we could add the UART as one
-of the interfaces to `ectool`. This would allow `ectool` to be run from the
-chroot simply by having `ectool` communicate over the PTY. Since `ectool`
-communicates using host commands anyways, everything should just workâ„¢. The
-benefits of this include faster development of `ectool` and host commands as
-well as a more robust interface for FAFT.
-
-#### On-device EC console without Servo
-
-Once the transition is complete and the console speaks entirely in host
-commands, it's no longer necessary to have the console talk solely over the
-UART. EC-3PO, or a variant, could exist as a standalone application that could
-be bundled in the system image, just like `ectool`. It would then send and
-receive host commands using the same interface that `ectool` uses whether it be
-LPC or I2C. This would essentially give us a console without having to hook up
-servo.
-
-Note for security reasons, this must be locked down to only allow a subset of
-commands and debug output when the system is ready to ship.
-
-#### Replacing `cprintf()`
-
-All prints will need to become packets. In these packets will contain the format
-string, but all `cprintf()` has to do is parse to format string to determine how
-many bytes the parameters take up. Then, `cprintf()` will send the format string
-and the parameters to EC-3PO which will create the proper string using that
-information. That makes `cprintf()` on the EC smaller and use less stack space
-than it would have used for formatting.
-
-We could also have a table of common format strings which the EC could just
-provide an index and the parameters.
-
-## Internal Design
-
-EC-3PO is a Python package which aims to migrate the rich debug console from the
-EC itself to the host. It is composed of two modules: console and interpreter.
-
-![Diagram of EC-3PO internal design. Within an outer box labelled EC-3PO are the
-Console and Interpreter modules. A bidirectional command pipe links the two, and
-a debug pipe goes from the Interpreter to the
-Console.](./images/ec-3po-internal-design.png)
-
-### Console module
-
-The console module provides the interactive console interface between the user
-and the interpreter. It handles the presentation of the EC console including
-editing methods as well as session-persistent command history.
-
-The console runs in an infinite loop listening for activity on three things
-using the `select()` system call: the PTY served to the user, the command pipe,
-and the debug pipe. The debug pipe is a unidirectional pipe from the interpreter
-to the console. From this pipe are debug prints that originate from the attached
-EC and the console currently writes these strings as is to the user PTY. The
-command pipe is bidirectional and is used between the console and the
-interpreter for command traffic. An example transaction would be a host command
-request and response.
-
-#### Enhanced EC image negotiation
-
-When the user transmits a character on the PTY, the console begins to scan every
-byte and perform the appropriate actions. Since not every EC image will support
-these enhanced features, the console must perform an interrogation to determine
-what behaviour to take. If the interrogation mode is set to auto, this
-negotiation takes place every time the enter key is pressed. The interrogation
-is very simple 2 way handshake. The console sends down a byte, `EC_SYN` and
-waits a timeout period to receive a byte, `EC_ACK`. This timeout period is 300ms
-for non-enhanced EC images and 1 second for enhanced EC images. Enhanced EC
-images will try to immediately respond to an `EC_SYN` with an `EC_ACK` to
-indicate to EC-3PO that the current EC images is enhanced. The non-enhanced EC
-image timeout period is intended to be short because non-enhanced EC images will
-never reply to the `EC_SYN`. By keeping this timeout short, we are essentially
-inserting a slight pause after each command. However, this timeout is long
-enough for an enhanced EC image to send its reply of `EC_ACK`. Once the `EC_ACK`
-is received by the console, the console increases the timeout to 1 second for
-stability purposes just in case the enhanced EC image takes a bit longer to send
-its reply for some reason. This negotiation allows EC-3PO to behave correctly
-for both enhanced and non-enhanced EC images.
-
-If a user knows that they are not using an enhanced EC image, they can disable
-the interrogation by issuing a OOBM command. This will cause the console to
-never initiate a negotiation, eliminating the delay. See the "interrogate"
-command in the Out of Band Management section for usage.
-
-#### Enhanced vs. Non-Enhanced EC images
-
-All EC images which don't explicitly enable the new features (or were built
-before the features were implemented in the code base) are non-enhanced images.
-Non-enhanced EC images will be handling the presentation of the console
-including editing methods (and history if enabled). Therefore, the EC-3PO
-console and interpreter behave as a simple pipe for this case forwarding
-everything straight to the EC to handle. For the enhanced EC images, all console
-presentation (including editing methods) is handled locally by the EC-3PO
-console. Enhanced EC images will also support all of the other features
-discussed in this document.
-
-#### Out of Band Management
-
-The interactive console also has an Out of Band Management (OOBM) interface.
-This allows commands to be entered that can alter the behavior of the console
-and interpreter during runtime. From the console, one can bring up the OOBM
-prompt by pressing ‘%' . These were originally added for debug purposes.
-
-##### Supported Commands
-
-*   `loglevel <integer>`
-    *   Allows setting the effective loglevel of the console and interpreter.
-*   `interrogate <never | always | auto> [enhanced]`
-    *   Allows control of when and how often interrogation occurs.
-
-### Interpreter module
-
-The interpreter provides the interpretation layer between the EC UART and the
-user. Similar to the console module, the interpreter starts an infinite loop of
-servicing the user and the EC by means of a `select()` system call. It receives
-commands through its command pipe, formats the commands for the EC, and sends
-the command to the EC. It also presents data from the EC to either be displayed
-via the interactive console module or some other consumer.
-
-The interpreter also keeps track of whether the EC image it's communicating with
-is enhanced or not. This is required so that the interpreter can communicate
-correctly with the EC. For enhanced EC images, the interpreter will pack
-incoming commands in a particular format. This could be the "packed plaintext"
-form or the binary host command format. With the packed plaintext form, the
-interpreter also supports command retrying by monitoring the response of the EC
-and automatically retrying the command with no input from the user.
-
-### Other users
-
-Since the interpreter communicates using pipes, it's not necessary that the user
-use the console module. For example, FAFT could directly connect to the
-interpreter and send down commands and receive command responses instead of
-having to deal with the PTY and instead just deal with python objects.
diff --git a/docs/ec-3po.md b/docs/ec-3po.md
deleted file mode 100644
index dae7b9babb..0000000000
--- a/docs/ec-3po.md
+++ /dev/null
@@ -1,82 +0,0 @@
-# EC-3PO
-
-[TOC]
-
-## What is EC-3PO?
-
-EC-3PO is the console interpreter that will one day replace the EC console that
-we have today. EC-3PO aims to migrate our rich debug console from the EC itself
-to the host. This allows us to maintain our rich debug console without impacting
-our EC image sizes while also allowing us to add new features.
-
-For more information, see [the design doc](./ec-3po-design.md).
-
-## How do I use EC-3PO?
-
-If you're using `servod` to connect to your EC, chances are you're already using
-it. EC-3PO was grafted into `servod` on Feb 7th 2016. If you're not running
-`servod`, you can run EC-3PO manually by running `console.py` in the
-`util/ec3po` directory from the EC checkout. You will need to provide the PTY
-that you get from elsewhere though.
-
-To obtain the EC console PTY, inside the chroot run:
-
-```shell
-$ dut-control ec_uart_pty
-```
-
-**NOTE: It's important to use `dut-control` to query the PTY instead of just
-eyeballing the `servod` output.** The former PTY (now known as
-`raw_ec_uart_pty`) will be sending raw binary data. Trying to use that console
-with an enhanced EC image will definitely fail and you won't be able to
-send/receive any commands.
-
-Then use your favorite serial terminal program to connect to the PTY. Since
-`servod` is run as root, you'll need to run your serial terminal program as root
-as well using `sudo`. This is because the permissions have changed from 666 to
-660.
-
-EC-3PO has been tested with `minicom`, `screen`, `socat`, and `cu`. However, if
-you're using `cu` you'll have to do the following to get it to work because
-apparently, `cu` wants group write permissions. On Ubuntu at least, the PTY is
-created with the `tty` group. If on your machine it's not, then just replace
-`tty` with whatever group it's created with.
-
-1.  Create a `tty` group if you don't have one already.
-1.  Add root to the `tty` group.
-1.  Rerun `cu` with `sudo` and it should work now.
-
-## Why does the console seem "laggier" than before?
-
-This is because there's a ~300ms delay after entering each console command. This
-is due to the interrogation that the console interpreter performs to determine
-if the EC image it's currently talking to is enhanced or not. Debug prints
-coming from the EC should be the same speed. Since most people aren't currently
-using the enhanced EC images, you can go ahead and run this command if the 300ms
-delay is unbearable.
-
-To disable the delay:
-
-1.  Open the EC console.
-1.  Press `%`
-1.  Enter `interrogate never`
-1.  Then press enter.
-
-\**For `socat` users, due to the line buffered nature, you'll have to just enter
-`%interrogate never`. Notice the lack of the space character between `%` and the
-command.*
-
-The interrogation delay should now be gone and you can have your 300ms/cmd back.
-
-## How do I try out this "enhanced" EC image you speak of?
-
-You simply add this to your board.h file.
-
-```c
-#define CONFIG_EXPERIMENTAL_CONSOLE
-```
-
-## I can't open the EC console
-
-Make sure you try with `sudo`. If you're using `cu`, make sure root is a member
-of the group of the created PTY.
diff --git a/docs/ec_terms.md b/docs/ec_terms.md
deleted file mode 100644
index 3b9f88416e..0000000000
--- a/docs/ec_terms.md
+++ /dev/null
@@ -1,248 +0,0 @@
-# EC Acronyms and Technologies
-
-## Glossary
-
-*   **8042 Interface** {#8042}
-
-    Interface for sending keyboard events to the [AP](#ap) and for receiving
-    commands from the AP. Only supported by x86 based APs.
-
-*   **ACCEL - Accelerometer** {#accel}
-
-    A sensor that measures acceleration, typically over 3-axis. Nominally
-    provides information about the orientation of a device. On Chromebook 2-in-1
-    devices, there is an accelerometer in the base and one in the lid. Combining
-    the measurements from both accelerometers allows for a precise calculation
-    of the lid angle, used to switch between tablet and laptop mode.
-
-*   **ACCELGYRO - Accelerometer/Gyroscope** {#accelgyro}
-
-    A combination [accelerometer](#accel) and [gyroscope](#gyro) sensor that
-    provides more precise orientation information by measuring both linear and
-    rotational motion.
-
-*   **ADC - Analog to Digital Converter** {#adc}
-
-    A sensor that converts an analog voltage to a digital reading.
-
-*   **ALS - Ambient Light Sensor** {#als}
-
-    A sensor that measures the ambient light present. Used to automatically
-    control the screen and keyboard backlight level.
-
-*   **AP - Application Processor** {#ap}
-
-    The processor on the board that boots and runs ChromeOS.
-
-*   **BAR - Barometer** {#bar}
-
-    A sensor that measures atmospheric pressure.
-
-*   **BC12 - Battery Charging** {#bc12}
-
-    A device that implements the USB Battery Charging specification, version
-    1.2. The complete [BC 1.2 Specification] is available from the USB
-    Implementers Forum.
-
-*   **CBI - CROS Board Information** {#cbi}
-
-    A collection of properties describing the board. This includes board
-    version, SKU, model name, and other fields. More details are found in the
-    [CrOS Board Info] documentation.
-
-*   **CEC - Consumer Electronics Control** {#cec}
-
-    A one-wire bidirectional bus. More details are on the [CEC Wikipedia page].
-
-*   **DPTF - Dynamic Power and Thermal Framework (Intel)** {#dptf}
-
-    Intel's platform based power and thermal management. See the [DPTF Readme]
-    for details on the implementation used in ChromeOS.
-
-*   **EC - Embedded Controller** {#ec}
-
-    The [MCU](#mcu) used to control the keyboard, battery charging, USB port
-    switching, sensor management, and other functions, offloading these tasks
-    from the [AP](#ap).
-
-*   **EC-3PO** {#ec-3po}
-
-    A replacement of the current UART-based console which moves much of the code
-    off the EC into a host tool, reducing the amount of flash space required.
-
-*   **E-Mark - Electronically Marked Cable** {#emark}
-
-    See the [USB-C documentation](./usb-c.md#emark) for more details.
-
-*   **eSPI - Enhanced Serial Peripheral Interface (Intel)** {#espi}
-
-    Intel's synchronous communication interface between the [AP](#ap) and the
-    [EC](#ec). Supports quad I/O mode and clock speeds up to 66 Mhz, providing
-    bandwidth up to 264 Mbps. The full [eSPI Specification] is available from
-    Intel.
-
-*   **FAFT - Fully Automated Firmware Tests** {#faft}
-
-    A collection of tests and related infrastructure that exercise and verify
-    capabilities of Chrome OS. See the [FAFT design doc] and
-    [chromium.org documentation](https://www.chromium.org/for-testers/faft) for
-    more details. Replaced [SAFT](#saft).
-
-*   **GMR - Giant Magnetoresistance Sensor** {#gmr}
-
-    A sensor device that detects a magnetic field. These sensors differ from
-    [MAG](#mag) sensors, in that they only detect magnetic fields in close
-    proximity to the sensor. On Chromebooks, GMR sensors are used to detect when
-    the lid is opened. On convertible Chromebooks, the GMR sensor also detects
-    tablet mode when lid the is opened a full 360 degrees.
-
-*   **GPIO - General Purpose Input/Output** {#gpio}
-
-    An individual signal that can independently controlled and read. GPIOs are
-    used to enable/disable power rails, drive reset signals, and receive
-    interrupts from devices connected to the EC. GPIOs may also be connected to
-    [I/O expanders](#ioexpander).
-
-*   **GYRO - Gyroscope** {#gyro}
-
-    A sensor that measures angular momentum, providing information about
-    rotational motion of the device.
-
-*   **I/O Expander** {#ioexpander}
-
-    An [I2C](#i2c) peripheral device that provides additional GPIO signals
-    (anywhere from 8 - 32 signals). GPIOs behind an I/O expander are written and
-    read using I2C register accesses from the I2C controller in the EC.
-
-*   **I2C - Inter-Integrated Circuit** {#i2c}
-
-    A 2-wire synchronous communication bus, consisting of a clock signal and a
-    bidirectional data signal. An I2C bus typically contains one controller
-    device and one or more peripheral devices. The I2C standard defines
-    supported clock speeds of 100 KHz and 400 KHz. The full [I2C Specification]
-    is available from NXP (formerly Phillips).
-
-*   **LED - Light Emitting Diode** {#led}
-
-    A Light Emitting Diode is a semiconductor that emits light when current
-    flows through it.
-
-*   **LPC - [Low Pin Count bus]** {#lpc}
-
-    Legacy communication bus between the [AP](#ap) and [EC](#ec). Runs at 33
-    MHz, providing a 133 Mbps bandwidth connection. Replaced by the
-    [eSPI](#espi) interface.
-
-*   **MAG - Magnetometer** {#mag}
-
-    A digital compass sensor, providing orientation for navigation.
-
-*   **MCU - Microcontroller Unit** {#mcu}
-
-    A small integrated chip containing a CPU core, on-chip ROM, on-chip RAM.
-    Also contains multiple peripheral interfaces, including GPIO, I2C buses, SPI
-    buses, ADC, PWM, etc.
-
-*   **MKBP - Matrix Keyboard Protocol** {#mkbp}
-
-    Message based protocol for communicating asynchronous events from the
-    [EC](#ec) to the [AP](#ap). Events are not limited to keyboard events with
-    the sensor subsystem as one of the main users. An EC board implementation
-    can be configured to send keyboard events through MKBP or using the
-    [8042 interface](#8042). This is the [EC MKBP driver] implementation.
-
-*   **MST - Multi Stream Transport** {#mst}
-
-    Part of the Display Port 1.2 standard, used to drive multiple independent
-    video streams from a single display port. The EC code is typically
-    responsible for enabling and disabling the MST hub chipset.
-
-*   **OOBM - Out of Band Management** {#oobm}
-
-    A command in the [EC-3PO protocol](#ec-3po) that allows commands to be
-    entered to alter the behaviour of the console and interpreter during
-    runtime.
-
-*   **PD - USB Power Delivery** {#pd}
-
-    See the [USB-C documentation](./usb-c.md#pd) for more details.
-
-*   **PMIC - Power Management IC** {#pmic}
-
-    An integrated circuit used to turn power rails on and off.
-
-*   **PPC - USB Power Path Controller** {#ppc}
-
-    See the [USB-C documentation](./usb-c.md#ppc) for more details.
-
-*   **PWM - Pulse Width Modulation** {#pwm}
-
-    Method of varying the duty cycle of a signal to control another device. A
-    typical application is to control fan speeds or the brightness of a
-    backlight.
-
-*   **SAFT - Semi-Automated Firmware Tests** {#saft}
-
-    A suite of tests for firmware, succeeded by [FAFT](#faft). See the
-    [chromium.org documentation](https://www.chromium.org/for-testers/saft) for
-    more details.
-
-*   **SHI - SPI Host Interface** {#shi}
-
-    [SPI](#spi) host interface used for communication between the AP and the EC.
-    In this configuration, the AP provides the SPI controller and the EC
-    provides the SPI peripheral. This interface is only used for non-x86 base
-    APs.
-
-    x86-based APs use either the [eSPI](#espi) or [LPC](#lpc) interface.
-
-*   **SPI - Serial Peripheral Interconnect** {#spi}
-
-    A 4-wire synchronous communication bus consisting of the signals CLK
-    (clock), SDO (Serial Data Out), SDI (Serial Data In), and CS (chip-select,
-    one per SPI peripheral). The SDO and SDI pins are defined from the
-    perspective of the device: the SPI controller's SDO pin connects to the SPI
-    peripheral's SDI pin and vice-versa. Clock speeds over 100 MHz are
-    supported. SPI communication involves the following sequence:
-
-    *   SPI controller asserts CS.
-    *   SPI controller transmits one or bytes on its SDO signal, received by the
-        SPI peripheral on its SDI signal.
-    *   SPI peripheral transmits zero or more bytes on its SDO signal, received
-        by the SPI controller on its SDI signal.
-    *   SPI controller de-asserts CS.
-
-    The specific contents of a SPI frame varies based on the SPI peripheral
-    type.
-
-*   **SVDM - Structured Vendor Defined Messages** {#svdm}
-
-    See the [USB-C documentation](./usb-c.md#svdm) for more details.
-
-*   **TCPC - USB Type-C Port Controller** {#tcpc}
-
-    See the [USB-C documentation](./usb-c.md#tcpc) for more details.
-
-*   **UART - Universal Asynchronous Receiver Transceiver** {#uart}
-
-    Also known as a serial port. An asynchronous communication channel between
-    two devices with a dedicated receive pin, transmit pin, and ground. Optional
-    hardware flow control signals require additional connections between the
-    devices. Standard transmission rates are slow (up to 115200 bits per
-    second). Typical use is to provide a debug console to the EC. [RS-232] is
-    the protocol standard used by UARTs.
-
-*   **VCONN - Connector Voltage** {#vconn}
-
-    See the [USB-C documentation](./usb-c.md#vconn) for more details.
-
-[BC 1.2 Specification]: <https://www.usb.org/document-library/battery-charging-v12-spec-and-adopters-agreement>
-[CrOS Board Info]: <https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md>
-[CEC Wikipedia page]: <https://en.wikipedia.org/wiki/Consumer_Electronics_Control>
-[DPTF Readme]: <https://github.com/intel/dptf/blob/master/README.txt>
-[eSPI Specification]: <https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0.pdf>
-[FAFT design doc]: <https://chromium.googlesource.com/chromiumos/third_party/autotest/+/HEAD/docs/faft-design-doc.md>
-[I2C Specification]: <https://www.nxp.com/docs/en/user-guide/UM10204.pdf>
-[RS-232]: <https://en.wikipedia.org/wiki/RS-232>
-[EC MKBP driver]: <https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/keyboard_mkbp.c>
-[Low Pin Count bus]: https://en.wikipedia.org/wiki/Low_Pin_Count
diff --git a/docs/fingerprint/OWNERS b/docs/fingerprint/OWNERS
deleted file mode 100644
index ba92c193e0..0000000000
--- a/docs/fingerprint/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../common/fpsensor/OWNERS
diff --git a/docs/fingerprint/fingerprint-authentication-design-doc.md b/docs/fingerprint/fingerprint-authentication-design-doc.md
deleted file mode 100644
index 7db552405a..0000000000
--- a/docs/fingerprint/fingerprint-authentication-design-doc.md
+++ /dev/null
@@ -1,772 +0,0 @@
-# Fingerprint Authentication on Chrome OS
-
-Authors: norvez@google.com, vpalatin@google.com
-
-Reviewers: kerrnel@google.com, mnissler@google.com
-
-Last Updated: 2019-01-14
-
-[TOC]
-
-## Objective
-
-### Goals
-
-*   Let users securely unlock their device with just their fingerprint
-*   Reuse the same architecture on all future platforms, don’t be tied to a
-    specific technology ([Arm TrustZone], [Intel SGX]).
-*   Support Android’s [fingerprint authentication framework] so users can for
-    example authorise payments in Android apps with their fingerprint. The
-    fingerprint implementation needs to comply with Android’s [CDD].
-
-### Non-goals
-
-*   Let users log in with their fingerprint
-    *   Users will have to use other authentication methods (e.g. password or
-        PIN) to log into their account.
-    *   Once logged in, users will be able to unlock the screen with their
-        fingerprint
-
-## Background
-
-To unlock their Chromebook users have to enter their password or a PIN.
-[Windows] and [macOS] let the user authenticate with their fingerprint for
-faster unlocking, we want to bring that capability to Chrome OS.
-
-### Fingerprint matching basics
-
-#### Fingerprint enrollment
-
-When a user wants to register their finger for fingerprint authentication, they
-go through the _enrollment_ operation. They are asked to touch the sensor
-multiple times with different parts of their fingerprint. The
-[matching algorithm] uses the images captured during enrollment to build a model
-of that fingerprint (known as a _template_).
-
-#### Fingerprint matching
-
-When the user puts their finger on the sensor, an image of the fingerprint is
-captured and compared to the fingerprint templates of the enrolled fingerprints
-to determine if the fingerprint matches one of the templates.
-
-#### Template update (TU)
-
-When the matching algorithm determines that a fingerprint matches a template
-with a high level of certainty, it can (and normally will) use that fingerprint
-image to update the template to improve the accuracy of future matching
-operations.
-
-### Threat model
-
-There are two main objectives for potential attackers:
-
-*   Large scale collection of biometric data from users by opportunistic
-    attackers
-    *   This attack is only valuable remotely. In case an attacker has physical
-        access to the device they are already able to collect fingerprint data
-        left by the user on the device itself without having to attack the
-        software.
-*   Target a specific user, typically with physical access to the device in
-    order to either:
-    *   Allow the attacker to enroll their own fingerprint to unlock the device
-        at will later on (the “abusive partner� model).
-    *   Spoof positive fingerprint matches to let the rest of the system believe
-        that a user has successfully identified, for example to break [2FA]
-        \("spy" trying to gain access to an organisation’s resources via the
-        victim’s computer).
-
-### Privacy and security
-
-*   Biometric data is particularly sensitive, so all operations on fingerprint
-    data must happen in a _Secure Biometric Processor_ (**SBP**). Attackers must
-    not gain access to the user’s fingerprints even if they have exploited the
-    software running on the AP.
-*   To protect the user’s privacy, fingerprint data must not be accessible
-    without the user’s consent, even by Google. Typically it will protected by
-    the user’s password.
-*   Fingerprint data must not leave the device.
-*   For added security, only the specific Chromebook used to enroll the
-    fingerprint can use it. Other Chromebooks, even of the same model, must not
-    be able to use the enrolled fingerprint.
-
-### Scalability
-
-For Eve, we [considered][Old Design Doc] using SGX as the SBP. However the
-complexity of the solution makes that option unattractive, both because of the
-amount of dev work required and because of the large resulting attack surface.
-It’s also exclusive to Intel, we would have to develop a completely different
-architecture for other platforms, which would add more dev work and increase the
-attack surface again.
-
-## Overview {#overview}
-
-Devices have a dedicated microcontroller (MCU) running a firmware based on the
-[Chromium OS EC] codebase that is used as the _Secure Biometric Processor_
-(**SBP**), where all enrollment and matching operations take place. Even if
-attackers gained control of the AP, they still would not be able to access the
-fingerprint (FP) data since it never leaves the SBP unencrypted.
-
-The SBP controls the sensor directly over a dedicated SPI bus. The SBP is
-connected to the host with a different SPI bus, the host has no direct access to
-the FP data coming from the sensor.
-
-Enrolled templates for a particular user are stored in the user’s [cryptohome]
-but not synced/backed up to the cloud. They are thus encrypted with a key
-(`User_Key`) derived from the user’s password, preventing 3rd parties (including
-Google) from accessing the fingerprint templates if the user hasn’t entered
-their password.
-
-On top of that, enrolled templates are also encrypted by a device-specific
-`HW_Key`. `HW_Key` is derived from a secret that has been randomly generated by
-the SBP, which prevents decrypting the templates on another device.
-
-### Architecture
-
-![Fingerprint Architecture]
-
-### Typical workflows
-
-#### FP enrollment
-
-1.  User starts the enrollment flow from the Settings UI.
-1.  SBP starts the enrollment operation.
-1.  SBP captures a number of FP images (exact number depends on the sensor,
-    typically 3-4 to 10-12) and builds the template in the SBP’s volatile memory
-1.  SBP encrypts the template with `HW_Key` and sends the encrypted template to
-    the AP.
-1.  AP encrypts the template with `User_Key` and saves it to non-volatile
-    storage.
-1.  User goes back to step 1 to enroll another finger. A user can typically
-    enroll 3 to 5 fingers, depending on how many templates the SBP can hold in
-    its internal volatile storage at the same time.
-
-#### User login
-
-1.  User logs in by typing their password.
-1.  FP templates of that user go through the first level of decryption, with
-    `User_Key`.
-1.  FP templates are uploaded to the SBP.
-1.  FP templates go through the second level of decryption in the SBP, with
-    `HW_Key`.
-1.  Deciphered FP templates are kept in the SBP’s volatile memory, ready to use
-    for matching operations.
-
-#### Screen unlocking operation
-
-1.  User touches the sensor with their finger.
-1.  SBP verifies that the FP image matches one of the user’s templates.
-1.  SBP wakes up the AP and sends a “FP matched� message to the AP
-1.  The AP unlocks the screen.
-1.  Matcher updates the template in the SBP’s volatile memory.
-1.  SBP encrypts the updated template with `HW_Key` and sends the encrypted
-    template to the AP.
-1.  AP encrypts the template with `User_Key` and saves it to non-volatile
-    storage.
-
-## Detailed Design {#detailed-design}
-
-### FP template encryption {#template-encryption}
-
-FP templates are encrypted "twice". First, the templates are encrypted by the
-SBP with a hardware-bound key that is unique to this SBP and that only the SBP
-knows. On top of that, the AP also encrypts the FP templates with a key bound to
-the user password.
-
-#### User-bound encryption
-
-The FP templates are stored in a "[cryptohome daemon store folder]" which is
-encrypted by [cryptohome] with a key tied to the user password. We plan to
-replace this post-launch with a mechanism similar to
-[Authentication-Time User Secrets]. Separate design doc to come.
-
-#### Hardware-bound encryption
-
-FP templates are AES-encrypted with `HW_Key`. `HW_Key` is bound to this specific
-SBP so encrypted templates can only be deciphered by this specific SBP. To
-ensure that a powerwash/recovery/WP toggle/.../ makes the encryption key
-impossible to recover, `HW_Key` also depends on a secret held by the TPM.
-
-We use an AEAD cipher (AES-GCM) to detect if the encrypted templates have been
-tampered with by an attacker controlling the AP.
-
-##### SBP secret generation
-
-The SBP generates a new 128-bit random number `SBP_Src_Key` every time the user
-goes through recovery or powerwashes the device. The [clobber-state] script
-sends a command to the SBP to make it immediately regenerate a new `SBP_Src_Key`
-immediately after requesting a TPM clear.
-
-`SBP_Src_Key` is stored by the SBP’s internal Flash and never shared with the
-AP.
-
-##### TPM-held Secret
-
-To avoid potential bugs where `SBP_Src_Key` would not always be made
-unrecoverable in some corner cases of recovery or powerwash, we make the
-encryption key `HW_Key` depend on a secret that is held by the TPM and deleted
-every time the TPM is cleared, for example if someone attempts to do a
-"[ccd open]" to disable the hardware WP.
-
-The following is a summary of the mechanism, see the specific design doc
-[TPM Seed for Fingerprint MCU] for details.
-
-The TPM already holds a "[system key]" `Cros_Sys_Key` in NVRAM space that is
-used to derive the encryption key of the stateful partition. That "system key"
-can only be read once per boot, typically by [mount_encrypted].
-
-We modify mount_encrypted so that right after reading the seed, it derives a key
-`TPM_Seed`:
-
-```
-TPM_Seed = HMAC-SHA256(Cros_Sys_Key, "biod")
-```
-
-`TPM_Seed` is then uploaded to the SBP where it will part of the
-[Input Key Material (IKM)] and immediately cleared from the AP’s memory, while
-the attack surface is very small (e.g. no network connections, stateful
-partition not yet mounted) to prevent attackers from accessing it.
-
-##### `HW_Key` derivation {#hw-key-derivation}
-
-The `HW_Key` 128-bit AES key for every FP template on the device is derived from
-the SBP’s secret and the TPM’s secret to ensure uniqueness. Therefore, even two
-identical devices would have different encryption keys. The user ID is also used
-as an input for key derivation, so 2 users on the same device won’t share
-encryption keys either. Summing up, the key used to encrypt a template depends
-on:
-
-*   Device-bound `TPM_Seed`, randomly generated on recovery/powerwash
-*   SBP-specific `SBP_Src_Key`, randomly generated on recovery/powerwash
-*   User ID on the device
-*   Encryption salt, randomly generated before every encryption
-
-###### Salt for key derivation
-
-Every time we update a template, we generate a new random 128-bit salt.
-
-The salt is not required to be secret, so we store `User_Salt` in cleartext next
-to the user’s encrypted FP templates on the disk.
-
-On user login, biod sends the salt and the encrypted FP templates to the SBP.
-biod also sends the User ID to the SBP. The SBP derives the AES key using [HKDF]
-with HMAC-SHA256:
-
-```
-HW_Key = HKDF(HMAC-SHA256, SBP_Src_Key, TPM_Seed, User_Salt, User_ID)
-```
-
-At that point, the SBP [authenticates and deciphers](#aead) the FP templates.
-The SBP then generates a new 128-bit salt `User_Salt_New` randomly and derives a
-new AES key:
-
-```
-HW_Key_New = HKDF(HMAC-SHA256, SBP_Src_Key, TPM_Seed, User_Salt_New, User_ID)
-```
-
-Updated FP templates are then encrypted with `HW_Key_New` before being stored on
-the host, along with the new salt `User_Salt_New`.
-
-*Note*: The SBP has a unique serial number hwID that could also be used as an
-additional input to the KDF (though it never changes). The entropy is pretty low
-and though not easily accessible an attacker who had stolen the device could
-gain access to it. After consulting with the security team, using the hwID was
-deemed unnecessary since it wasn’t adding real entropy.
-
-##### AEAD (AES-GCM) Encryption {#aead}
-
-To encrypt the FP templates with `HW_Key` we use BoringSSL’s implementation of
-AES-GCM128.
-
-###### Initialisation Vector
-
-The encryption operations are done by the R/W firmware that doesn’t have write
-access to the Flash, so it can’t keep track of IVs that could have already been
-used during previous boots since it has no way to persist state. Instead, the
-SBP will generate a random 96-bit IV every time it needs to encrypt a template
-with `HW_Key` before sending it back to the host for storage. This only happens
-every time a user successfully matches their finger, which assuming 1 match
-every second for 10 years would result in 3600\*24\*365\*10 < 350,000,000, so
-the risk of reusing an IV is acceptable. To ensure that a compromised host could
-not try to generate too many messages to find collisions, the SBP rate-limits
-the number of encryption operations to 1 per second.
-
-The IV will be stored on the host with the salt, the encrypted templates and the
-16-byte tag for authentication.
-
-###### Authentication Tag
-
-To authenticate the encrypted templates, we use a 128-bit tag that we store in
-clear text with the encrypted template.
-
-Authentication of the encrypted templates prevents attackers from generating
-random templates to try to attack directly the matching libraries rather than
-the AES-GCM128 implementation. It also prevents attackers from trying to pass
-their own template instead of the user’s FP template.
-
-###### Encryption Flowchart
-
-Encryption of the FP template in the SBP before the ciphered data is sent to the
-AP for storage.
-
-![Encryption Flowchart]
-
-###### Decryption Flowchart
-
-Decryption of the ciphered FP template coming from the AP when the user logs in.
-
-![Decryption Flowchart]
-
-#### FP template disk format
-
-Encrypted templates are stored in a “[cryptohome daemon store folder]� that is
-only mounted/decrypted when the user has logged in. The templates are stored as
-JSON files with the following fields:
-
-```JSON
-{
-  "biomanager": “CrosFpBiometricsManager� string
-  "version": integer describing the version of the file format. Set to 1 at launch
-  "data": Base64-encoded string containing the `HW_Key`-encrypted template
-  "label": user-configurable human-readable string listed in the UI
-  "record_id": UUID of that template generated at enrollment time
-}
-```
-
-##### `HW_Key`-encrypted template format
-
-The content of the "data" field is the encrypted template that can be deciphered
-by the SBP.
-
-Field Name | Field description                                                     | Field size (bytes) | Field offset (bytes)
----------- | --------------------------------------------------------------------- | ------------------ | --------------------
-Version    | Number describing the version of the file format. Set to 3 at launch. | 2                  | 0
-Reserved   | Reserved bytes, set to 0                                              | 2                  | 2
-Nonce      | Randomly-generated IV                                                 | 12                 | 4
-Salt       | Randomly-generated salt                                               | 16                 | 16
-Tag        | AES-GCM Authentication Tag                                            | 16                 | 32
-Template   | Encrypted template                                                    | 47552              | 48
-
-When the user logs in, the cryptohome daemon store folder of that user is
-mounted and the JSON files become available to biod. For every enrolled finger,
-biod sends the `HW_Key`-encrypted template to the SBP. The SBP
-[derives `HW_Key`](#hw-key-derivation) for that template and deciphers the
-template.
-
-### Protection of the SBP
-
-To access the unencrypted data and/or `HW_Key`, attackers have 3 main options:
-
-*   Temporarily gain read or even execution access in the SBP through a firmware
-    bug
-    *   Would allow an attacker to gain access to the clear text FP data and/or
-        the encryption key
-    *   Mitigation strategy in [Prevent RW exploits](#prevent-rw-exploits)
-*   Turn a temporary compromise of the SBP’s firmware into a permanent exploit
-    by replacing the SBP’s firmware with a firmware controlled by the attacker
-    *   Would allow an attacker to gain access to the clear text FP data and/or
-        the encryption key
-    *   Would allow an attacker to spoof positive FP matches, defeating 2FA
-    *   Mitigation in [Verified firmware](#verified-firmware)
-*   Use physical access and control of WP to load a compromised firmware to the
-    SBP
-    *   Mitigation in [Control WP/BOOT0](#control-wp-boot0)
-
-#### Verified firmware {#verified-firmware}
-
-To verify the integrity of the firmware we use a mechanism similar to the one
-used to protect the EC in detachable keyboards as described in
-[Detachable Base Verified Boot].
-
-The SBP has a minimalistic RO firmware that contains the public part of an
-RSA-3072 exponent 3 key pair. The corresponding private key is only accessible
-by the Chrome OS signers and is used to sign SBP firmwares. On boot the RO
-firmware verifies the signature of the RW firmware. If the RW signature is
-valid, the RO firmware protects itself by setting the WP bit of the Flash then
-jumps to RW.
-
-##### Anti-rollback
-
-On top of verifying the signature of the RW firmware, the RO firmware must
-verify that the RW firmware is not an outdated version with known
-vulnerabilities. This is required to prevent attackers from loading valid but
-vulnerable RW firmwares. This is achieved with an anti-rollback mechanism as
-described in
-[Detachable Base Verified Boot][Detachable Base Verified Boot Anti-Rollback].
-
-###### Nocturne-specific anti-rollback
-
-On nocturne, the SBP is an STM32H7 MCU, with 128K Flash blocks. We still need 2
-pingpong RB blocks to prevent data loss, so the Flash map looks like this:
-
-Name                | Size
-------------------- | -------
-RO firmware         | 128 KB
-Blank               | 640 KB
-RB1 + `SBP_Src_Key` | 128 KB
-RB2 + `SBP_Src_Key` | 128 KB
-RW firmware         | 1024 KB
-
-The Nocturne SBP uses the same Flash block for the anti-rollback mechanism and
-`SBP_Src_Key`. Most of the anti-rollback mechanism is identical to the one
-described in
-[Detachable Base Verified Boot][Detachable Base Verified Boot Anti-Rollback],
-and the key is similar to the entropy/secret stored for
-[Detachable Base Swap Detection].
-
-The rollback minimum version is updated whenever RO has verified RW signature,
-and the RW rollback version is larger than what is stored in the RB block.
-
-When re-keying is desired, `SBP_Src_Key` is updated by doing the following
-operation:
-
-```
-SHA256(SBP_Src_Key || entropy)
-```
-
-where `entropy` is generated from STM32H7 True Random Number Generator (see
-[RM0433] Chapter 33 for details). Since there are 2 rollback blocks, and we
-ping-pong between them, re-keying should involve updating `SBP_Src_Key` twice,
-so that both blocks are erased, and no remnant of the previous key is left over.
-
-#### Prevent RW exploits {#prevent-rw-exploits}
-
-Even non-persistent exploits in the RW firmware would be problematic if the
-attacker was able to read the content of the memory or the Flash, e.g. via a
-buffer overflow, since they could gain access to the clear text FP data and/or
-the encryption key. If the attacker was also able to execute code in RW, they
-would be able to spoof positive FP matches.
-
-##### Attack through host command interface {#attack-host-command}
-
-The AP can send a number of commands to the SBP, for example to wait for a match
-or to update the RW firmware. In case of a vulnerability in the protocol an
-attacker with (potentially remote) access to the AP<->SBP SPI bus could send bad
-specially crafted commands to the SBP and potentially gain read, write or even
-execute permissions in the SBP.
-
-###### Mitigation strategies
-
-*   Limit the size of the API exposed by the SBP to the AP
-*   Fuzz the host command interface
-
-##### Attack through crafted templates uploaded to the SBP {#template-attack}
-
-The AP partially deciphers (with `User_Key`) the templates stored on the disk
-then sends the `HW_Key`-encrypted templates to the SBP where they will be
-deciphered and then passed to the matching algorithm. An attacker could submit a
-carefully crafted template to the SBP that would exploit holes in the closed
-source matching algorithm library.
-
-###### Mitigation strategies
-
-We use AEAD to decipher and authenticate the templates received from the AP,
-they are not passed directly to the matching library. Bad templates will be
-intercepted by the decryption code.
-
-##### RAM noexec
-
-Even if an attacker gained some level of access to the SBP, the RAM is not
-executable so it would be hard for the attacker to execute compromised code, for
-example to spoof successful authentication and break 2FA or to attempt to turn
-into a persistent compromission of the SBP by writing a new compromised firmware
-to Flash.
-
-#### Control WP/BOOT0 {#control-wp-boot0}
-
-The BOOT0 pin of the MCU is gated by the WP controlled by Haven. Since toggling
-the WP bit from Haven requires physical access to the device, remote attackers
-can’t toggle the BOOT0 pin to make the MCU start in bootloader mode and
-read/write the Flash from the AP.
-
-However, with physical access (> 5 minutes) an attacker could disable the WP
-signal from Haven and toggle the BOOT0 pin to start the MCU in bootloader mode.
-
-##### Flash protected with RDP Level 1
-
-We will set the Flash in [Global Read-out Protection (RDP) mode Level 1]. This
-means that attackers with physical access who would manage to start the MCU in
-bootloader mode would not be able to read `SBP_Src_Key` from the Flash.
-Attackers would still be able to read the content of the RAM and registers but
-at that point the MCU would just have rebooted and the RAM would be empty.
-
-If the attacker attempted to write their own code to the Flash (for example to
-replace RO), RDP Level 1 would only allow that after a complete erasure of the
-Flash that would wipe `SBP_Src_Key`, preventing the user from decrypting FP
-templates.
-
-*Note*: An attacker with that level of access could in theory replace the RO
-firmware with their own firmware. This would however have wiped enrolled
-fingers, giving the user an indication that their device might have been
-tampered with. This wouldn’t give access to existing FP templates or images to
-the attacker, only future enrollments.
-
-##### RMA
-
-To ensure that a device is clean after e.g. refurbishing, the RMA procedure
-would require that the operator disabled the WP bit from Haven and toggled BOOT0
-to switch to bootloader mode. After that a known good RO and RW firmware can be
-written to the Flash and the operator will reenable the WP bit from Haven.
-
-## Security Considerations
-
-### Security boundaries
-
-#### Chrome to system services
-
-Biod and Chrome communicate over D-Bus (defined [here][biod D-Bus API]).
-
-*   Chrome lets biod know when the user has signed in, so biod can load the
-    templates to the [SBP](#overview).
-*   Biod lets Chrome know when the SBP has detected a positive or negative match
-    so Chrome can unlock the screen.
-*   Chrome tells biod to start/end enrolling a finger.
-*   Chrome tells biod to start/end authentication (matching) mode.
-
-#### Kernel to firmware
-
-The SBP uses the `cros_ec` interface, same as the EC. There are additional
-SBP-specific host commands that the AP can send to the SBP, see
-[Attack through host command interface](#attack-host-command).
-
-### Privileges
-
-#### Sandboxing
-
-Biod uses Minijail ([upstart script][biod upstart script]) for [sandboxing], and
-has a [seccomp filter].
-
-### Untrusted input
-
-Encrypted templates are read from the stateful partition where they could be
-corrupted or tampered with. Biod itself doesn’t parse that input -it’s still
-encrypted by the SBP- and merely marshalls the data around to and from the SBP.
-To ensure the integrity of the input, we use [AEAD] with an
-[implementation][AEAD implementation] based on BoringSSL.
-
-The encrypted templates are wrapped inside JSON files that could be corrupted or
-tampered with. Biod does parse and interpret some fields of those JSON files.
-That input is [fuzzed].
-
-### Sensitive data
-
-The SBP handles biometric data, see the [Detailed Design](#detailed-design)
-section that describes how we keep that data protected from attackers.
-
-### Attack surface
-
-#### Libraries
-
-*   Biod uses libbrillo and libchrome
-*   The SBP firmware is based on the cros_ec code already used in the EC. Two
-    significant additions:
-    *   Parts of BoringSSL (AES and AES-GCM) ported to cros_ec
-    *   3rd-party proprietary blob used for matching, see
-        [Closed source blobs in the SBP](#closed-source-blobs).
-
-#### Remote attacks
-
-Neither biod nor the SBP are exposed directly to remote attackers. Since biod
-communicates with Chrome over D-Bus, and attacker who had compromised Chrome
-could start sending D-Bus commands to biod.
-
-#### Closed source blobs in the SBP {#closed-source-blobs}
-
-The enrollment/matching and image capture libraries are provided by a 3rd-party
-vendor in binary form. That proprietary blob went through a security audit by a
-3rd party auditor (see the auditor’s [report][Security Audit Report].
-
-On top of the security audit of the 3rd-party proprietary code, we limit the
-attack surface of those libraries by not directly exposing them to user input.
-Data (e.g. FP templates) that is fed to those libraries isn’t directly coming
-from untrusted user input, it is sanitized by the opensource glue logic and
-wrappers. For example, we use AEAD to ensure that the encrypted data that is
-deciphered before being passed to the 3rd-party libraries has been generated by
-the SBP itself. For more details, see section
-[Attack through crafted templates uploaded to the SBP](#template-attack).
-
-### Implementation robustness
-
-#### biod (userspace daemon)
-
-##### Multi-threading/multi-process
-
-biod uses `base::MessageLoopForIO`, no custom multi-thread or multi-process
-implementation.
-
-##### State machine implementation
-
-biod has 3 main states:
-
-*   Idle
-*   Waiting for a match: controlled by the [AuthSession] object
-*   Enrolling a new fingerprint: controlled by the [EnrollSession] object.
-
-#### cros_fp (SBP firmware)
-
-##### Multi-threading/multi-process
-
-We use the [primitives][EC primitives] of the Chromium OS EC: tasks, hooks, and
-deferred functions.
-
-##### Memory allocation
-
-Most buffers (e.g. for FP images and templates) are [statically allocated]. The
-vendor libraries do require some dynamic memory allocation, we provide
-[wrappers functions] that use the [malloc/free memory module for Chrome EC].
-
-##### State machine implementation
-
-There is one main [state machine] that configures the matching/enrollment code
-to be ready for a match or to enroll a finger.
-
-### Cryptography
-
-See detailed discussion in the ["FP template encryption"](#template-encryption)
-section.
-
-### Metrics {#metrics}
-
-Metrics related to security that we’re collecting through UMA:
-
-*   `Ash.Login.Lock.AuthMethod.Used.ClamShellMode` to know if FP is used to
-    authenticate
-*   `Ash.Login.Lock.AuthMethod.Used.TabletMode` to know if FP is used to
-    authenticate
-*   `Fingerprint.Unlock.AuthSuccessful` tracks whether FP authentication was
-    successful or not
-*   `Fingerprint.Unlock.AttemptsCountBeforeSuccess` tracks how many attempts it
-    takes for users to unlock with their fingerprint
-*   `Fingerprint.UnlockEnabled` tracks whether FP unlocking is enabled or not
-*   `Fingerprint.Unlock.EnrolledFingerCount` reports the number of fingers that
-    users have enrolled
-
-Complete list of metrics collected via UMA:
-[New UKM collection review - CrOS FP Unlock]
-
-### Potential attacks
-
-#### Enroll a rogue fingerprint
-
-An attacker with physical access to the device could enroll their own
-fingerprint under the victim’s account and use it to unlock the device at-will
-in the future.
-
-*   Enrollment UI requires the user password before telling biod to start an
-    enrollment session, so the attacker would need some form of exploit to
-    bypass Chrome and trigger the enrollment. We plan to replace this
-    post-launch with a mechanism similar to [Authentication-Time User Secrets].
-    Separate design doc to come.
-*   Even if it’s not a persistent exploit, a rogue enrolled fingerprint would
-    persist.
-*   The victim’s fingerprint data would still be secure.
-*   The enrollment UI shows how many fingers are enrolled.
-
-## Privacy Considerations
-
-### Fingerprint data is kept locally on the device
-
-The raw fingerprint images themselves never leave the SBP. The fingerprint
-templates are kept on the local storage (encrypted both with the `HW_Key` and
-the `User_Key`) of the device and not synced to the cloud, encrypted or not.
-
-### Fingerprint data decryption requires the user password
-
-The fingerprint templates are stored in a "[cryptohome daemon store folder]"
-which is only mounted when the user logs in. To do so, they must have entered
-their password.
-
-### FP matching is not used for login, only unlocking
-
-Before using their fingerprint to unlock the device the user must have logged
-in, typically with the Google Account password.
-
-### Lock screen will display a FP icon if enabled
-
-If a user has enabled FP unlocking, a FP icon will be associated to that user on
-the lock screen. This potentially lets others know that a user has enabled FP
-unlocking. This seems reasonable when the small resulting decrease in privacy is
-weighed against the fact that adding an icon greatly improves UX.
-
-### Metrics collection
-
-We collect anonymous metrics through [UMA], see section [Metrics](#metrics) for
-details.
-
-### Logs
-
-Biod, the SBP, and Chrome have logs related to the fingerprint process.
-[Privacy fields for Fingerprints] lists the log entries and their privacy
-implications. Full [PDD is here].
-
-#### Biod
-
-The log files are in `/var/log/biod/`.
-
-#### SBP
-
-The log file is `/var/log/cros_fp.log`.
-
-<!-- Links -->
-
-[2FA]: https://en.wikipedia.org/wiki/Multi-factor_authentication
-[AEAD implementation]: https://chromium.googlesource.com/chromiumos/platform/ec/+/aed008f87c3c880edecf7608ab24eaa4bee1bc46/common/fpsensor.c#574
-[AEAD]: https://en.wikipedia.org/wiki/Authenticated_encryption
-[Arm TrustZone]: https://www.arm.com/products/security-on-arm/trustzone
-[Authentication-Time User Secrets]: http://go/authentication-time-user-secrets
-[AuthSession]: https://chromium.googlesource.com/chromiumos/platform2/+/eae39a9ad1239f8fbfa8164255578b306ff6ba5c/biod/biometrics_manager.h#96
-[biod D-Bus API]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/system_api/dbus/biod/
-[biod upstart script]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/init/biod.conf
-[ccd open]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Open-CCD
-[CDD]: https://source.android.com/compatibility/android-cdd#7_3_10_fingerprint_sensor
-[Chromium OS EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md
-[clobber-state]: https://chromium.googlesource.com/chromiumos/platform2/+/962ab1bc481db0cf504b5449eb3a3d5008ea7601/init/clobber_state.cc#475
-[cryptohome daemon store folder]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/sandboxing.md#securely-mounting-cryptohome-daemon-store-folders
-[cryptohome]: https://www.chromium.org/chromium-os/chromiumos-design-docs/protecting-cached-user-data
-[Detachable Base Swap Detection]: https://docs.google.com/document/d/1WYdkkSAL_RHVc5mUXnAvBBfAeM7Wj3ABa1dbeTdvm74/edit#heading=h.g74ijelumqop
-[Detachable Base Verified Boot Anti-Rollback]: http://go/detachable-base-vboot#heading=h.fimcm174ok3
-[Detachable Base Verified Boot]: http://go/detachable-base-vboot#heading=h.dolfbdpggye6
-[EC primitives]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md#Software-Features
-[EnrollSession]: https://chromium.googlesource.com/chromiumos/platform2/+/eae39a9ad1239f8fbfa8164255578b306ff6ba5c/biod/biometrics_manager.h#92
-[fingerprint authentication framework]: https://developer.android.com/about/versions/marshmallow/android-6.0.html#fingerprint-authentication
-[fuzzed]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/biod_storage_fuzzer.cc
-[Global Read-out Protection (RDP) mode Level 1]: https://www.st.com/content/ccc/resource/technical/document/application_note/b4/14/62/81/18/57/48/05/DM00075930.pdf/files/DM00075930.pdf/jcr:content/translations/en.DM00075930.pdf
-[HKDF]: https://tools.ietf.org/html/rfc5869
-[Input Key Material (IKM)]: https://en.wikipedia.org/wiki/HKDF
-[Intel SGX]: https://software.intel.com/en-us/sgx
-[macOS]: https://support.apple.com/en-us/HT207054
-[malloc/free memory module for Chrome EC]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/shmalloc.c
-[matching algorithm]: https://en.wikipedia.org/wiki/Fingerprint#Algorithms
-[mount_encrypted]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/cryptohome/mount_encrypted
-[New UKM collection review - CrOS FP Unlock]: https://docs.google.com/document/d/1qjDCMcBcrhSeg_uwyEIRsXHKmzUTJahcg6a4YVhkuLo
-[Old Design Doc]: https://docs.google.com/document/d/1MdPRmCDkVg1HO9DdbvPT5fDZS2ICg5ys9_ok_K95EEU
-[PDD is here]: http://go/cros-fingerprint-pdd
-[Privacy fields for Fingerprints]: https://docs.google.com/spreadsheets/d/1jLfnuhfbrImpoxuj92OkAxS_GGrm7QkpQhsUQCkO9ec
-[Privacy fields for Fingerprints]: https://docs.google.com/spreadsheets/d/1jLfnuhfbrImpoxuj92OkAxS_GGrm7QkpQhsUQCkO9ec/
-[RM0433]: https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/c9/a3/76/fa/55/46/45/fa/DM00314099/files/DM00314099.pdf/jcr:content/translations/en.DM00314099.pdf
-[sandboxing]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/sandboxing.md
-[seccomp filter]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/init/seccomp/biod-seccomp-amd64.policy
-[Security Audit Report]: https://drive.google.com/a/google.com/file/d/0B1HHKpeDpzYnMDdocGxwWUhpckpWM0hMU0tPa2ZjdEFnLU53/
-[state machine]: https://chromium.googlesource.com/chromiumos/platform/ec/+/90d177e3f0ae729bea7e24934a3c6ef9f2520d45/common/fpsensor.c#252
-[statically allocated]: https://chromium.googlesource.com/chromiumos/platform/ec/+/90d177e3f0ae729bea7e24934a3c6ef9f2520d45/common/fpsensor.c#57
-[system key]: https://chromium.googlesource.com/chromiumos/platform2/+/23b79133514ac2cd986bce21c398fb6658bda248/cryptohome/mount_encrypted/encryption_key.h#125
-[UMA]: http://go/uma
-[Windows]: https://www.microsoft.com/en-us/windows/windows-hello
-[wrappers functions]: https://chrome-internal.googlesource.com/chromeos/platform/ec-private/+/9ebb3f10c611afff695f679aaeed1a35551a116b/fpc_sensor_pal.c#52
-[TPM Seed for Fingerprint MCU]: ../fingerprint/fingerprint-tpm-seed.md
-
-<!-- Images -->
-
-<!-- If you make changes to the docs below make sure to regenerate the PNGs by
-     appending "export/png" to the Google Drive link. -->
-
-<!-- https://docs.google.com/drawings/d/1-JUWTF7sUTND29BfhDvIudzX_S6g-iwoxG1InPedmVw -->
-
-[Decryption Flowchart]: ../images/cros_fingerprint_decryption_flowchart.png
-
-<!-- https://drive.google.com/open?id=1uUprgLsTUZZ2G2QWRYcRn6zBAh6ejvJagVRD7eZQv-k -->
-
-[Encryption Flowchart]: ../images/cros_fingerprint_encryption_flowchart.png
-
-<!-- https://docs.google.com/drawings/d/1DFEdxfDXEtYY3LNOOJFAxVw2A7rKouH98tnb1yiXLAA -->
-
-[Fingerprint Architecture]: ../images/cros_fingerprint_architecture_diagram.png
diff --git a/docs/fingerprint/fingerprint-debugging.md b/docs/fingerprint/fingerprint-debugging.md
deleted file mode 100644
index c77874e7bb..0000000000
--- a/docs/fingerprint/fingerprint-debugging.md
+++ /dev/null
@@ -1,254 +0,0 @@
-# Fingerprint Debugging
-
-This document describes how to attach a debugger with SWD in order to debug the
-FPMCU with [`gdb`](#gdb) or to [flash the FPMCU](#flash).
-
-[TOC]
-
-## Overview
-
-### SWD
-
-`SWD` (Single Wire Debug) was introduced by ARM with the Cortex-M family to
-reduce the pin count required by JTAG. JTAG requires 5 pins, but SWD can be done
-with only 3 pins. Furthermore, one of the freed up pins can be repurposed for
-tracing.
-
-See [CoreSight Connectors] for details on the three standard types of connectors
-used for JTAG and SWD for ARM devices.
-
-## Hardware Required
-
-*   JTAG/SWD Debugger Probe: Any debug probe that supports SWD will work, but
-    this document assumes that you're using a
-    [Segger J-Trace PRO for Cortex-M][J-Trace].
-*   [Dragonclaw v0.2 Development board][FPMCU dev board] or
-    [Icetower v0.1 Development board][FPMCU dev board].
-*   [Servo Micro].
-
-## Software Required
-
-*   [JLink Software] \(when using [J-Trace] or other Segger debug probes). This
-    is the only software required for flashing.
-*   In order to perform breakpoint debugging, you will need a tool that supports
-    connecting `gdbserver`. This document will assume [CLion] \(Googlers see
-    [CLion for Chrome OS]) and was tested with `JLink_Linux_V684a_x86_64`.
-    Alternatively, you can use [Ozone], a standalone debugger from Segger.
-
-## JLink Software {#software}
-
-Download the [JLink Software], choosing the `J-Link Software and Documentation
-pack for Linux, TGZ archive, 64-bit` version. This version is recommended
-because it's simple to extract the tarball into a directory that is accessible
-to the Chrome OS chroot. The instructions in this document assume that you have
-extracted the tarball in
-`~/chromiumos/src/platform/ec/JLink_Linux_V684a_x86_64`.
-
-## Connecting SWD {#connect-swd}
-
-### Dragonclaw v0.2
-
-The connector for SWD is `J4` on Dragonclaw v0.2.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: Pay attention to the location of pin 1 (red wire) in the
-photos below so that you connect with the correct orientation.
-
-`SW2` on the bottom of Dragonclaw must be set to `CORESIGHT`.
-
-If you want to connect a 20-Pin ARM Standard JTAG Connector (0.10" / 2.54 mm),
-you can use the following [adapter][JTAG to SWD Adapter] and [cable][SWD Cable].
-***
-<!-- mdformat on -->
-
-Dragonclaw v0.2 with 20-pin SWD (0.05" / 1.27mm) on J4. Only half the pins are connected. |
------------------------------------------------------------------------------------------ |
-![Dragonclaw with 20-pin SWD]                                                             |
-
-Dragonclaw v0.2 with 10-pin SWD (0.05" / 1.27mm) on J4. |
-------------------------------------------------------- |
-![Dragonclaw with 10-pin SWD]                           |
-
-### Icetower v0.1
-
-The connector for SWD is `J4` on Icetower v0.1.
-
-`SW2` on Icetower must be set to `CORESIGHT` (not `SERVO`).
-
-Icetower v0.1 with 20-pin SWD (0.05" / 1.27mm) on J4. |
------------------------------------------------------ |
-![Icetower with 20-pin SWD]                           |
-
-## Powering the Board {#power}
-
-[Servo Micro] can provide both the 3.3V for the MCU and 1.8V for the sensor.
-
-Run the following to start `servod`, which will enable power to these rails by
-default:
-
-```bash
-(chroot) $ sudo servod --board=<BOARD>
-```
-
-where `<BOARD>` is the board you are working with
-([`dartmonkey` or `bloonchipper`][fingerprint hardware]).
-
-Theoretically, it's also possible to power through J-Trace, though the
-[power pin] on J-Trace only outputs 5V, whereas the MCU runs at 3.3V and the
-sensor runs at 1.8V. The pin is also not connected on the current designs.
-
-## Flashing the FPMCU with JLink {#flash}
-
-*   Install the [JLink Software](#software).
-*   [Connect SWD](#connect-swd).
-*   [Power the board with servo](#power).
-*   Start the JLink server:
-
-```bash
-(chroot) $ cd ~/trunk/src/platform/ec
-```
-
-```bash
-# JLinkRemoteServerCLExe will listen on port 19020 (among others) by default.
-# This can be overridden with the -Port argument.
-(outside) $ ./JLink_Linux_V684a_x86_64/JLinkRemoteServerCLExe -select USB
-```
-
-You should see the following:
-
-```bash
-SEGGER J-Link Remote Server V6.84a
-Compiled Sep  7 2020 18:28:13
-
-'q' to quit '?' for help
-
-Connected to J-Link with S/N 123456
-
-Waiting for client connections...
-```
-
-*   Build the FPMCU image:
-
-```bash
-(chroot) $ cd ~/trunk/src/platform/ec
-```
-
-```bash
-(chroot) $ make BOARD=<BOARD> -j
-```
-
-replacing `<BOARD>` with [`bloonchipper` or `dartmonkey`][fingerprint hardware].
-
-*   Run the [`flash_jlink.py`] script:
-
-```bash
-(chroot) $ ~/trunk/src/platform/ec/util/flash_jlink.py --board <BOARD> --image ./build/<BOARD>/ec.bin
-```
-
-replacing `<BOARD>` with [`bloonchipper` or `dartmonkey`][fingerprint hardware].
-
-## Using JLink gdbserver {#gdb}
-
-Start the JLink gdbserver for the appropriate MCU type:
-
-*   Dragonclaw / [Nucleo STM32F412ZG]: `STM32F412CG`
-*   Icetower / [Nucleo STM32H743ZI]: `STM32H743ZI`
-
-```bash
-(outside) $ ./JLink_Linux_V684a_x86_64/JLinkGDBServerCLExe -select USB -device STM32F412CG -endian little -if SWD -speed auto -noir -noLocalhostOnly
-```
-
-You should see the port that `gdbserver` is running on in the output:
-
-```bash
-Connecting to J-Link...
-J-Link is connected.
-Firmware: J-Trace PRO V2 Cortex-M compiled Dec 13 2019 11:19:22
-Hardware: V2.00
-S/N: XXXXX
-Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
-Checking target voltage...
-Target voltage: 3.30 V
-Listening on TCP/IP port 2331    <--- gdbserver port
-Connecting to target...
-Connected to target
-Waiting for GDB connection...
-```
-
-Configure your editor to use this [`.gdbinit`], taking care to set the correct
-environment variables for the `BOARD` and `GDBSERVER` being used. For CLion, if
-you want to use a `.gdbinit` outside of your `HOME` directory, you'll need to
-[configure `~/.gdbinit`].
-
-In your editor, specify the IP address and port for `gdbserver`:
-
-```
-127.0.0.1:2331
-```
-
-You will also want to provide the symbol files:
-
-*   RW image: `build/<board>/RW/ec.RW.elf`
-*   RO image: `build/<board>/RO.ec.RO.elf`
-
-Also, since we're compiling the firmware in the chroot, but your editor is
-running outside of the chroot, you'll want to remap the source code path to
-account for this:
-
-*   "Remote source" is the path inside the chroot:
-    `/home/<username>/trunk/src/platform/ec`
-*   "Local source" is the path outside the chroot:
-    `${HOME}/chromiumos/src/platform/ec`
-
-To debug with CLion, you will create a new [GDB Remote Debug Configuration]
-called `EC Debug`, with:
-
-*   `'target remote' args` (gdbserver IP and port from above): `127.0.0.1:2331`
-*   `Symbol file` (RW or RO ELF): `/path/to/build/<board>/RW/ec.RW.elf`
-*   `Path mapping`: Add remote to local source path mapping as described above.
-
-After configuring this if you select the `EC Debug` target in CLion and
-[click the debug icon][CLion Start Remote Debug], CLion and JLink will handle
-automatically flashing the ELF file and stepping through breakpoints in the
-code. Even if not debugging, this may help with your iterative development flow
-since the JLink tool can flash very quickly since it performs a differential
-flash. Note that you still need to recompile after making changes to the source
-code before launching the debugger.
-
-## Using Ozone
-
-Ozone is a free standalone debugger provided by Segger that works with the
-[J-Trace]. You may want to use it if you need more powerful debug features than
-gdbserver can provide. For example, Ozone has a register mapping for the MCUs we
-use, so you can easily inspect CPU registers. It can also be automated with a
-scripting language and show code coverage when used with a [J-Trace] that is
-connected to the trace pins on a board. Note that the Dragonclaw v0.2 uses an
-STM32F412 package that does not have the synchronous trace pins, but the
-[Nucleo STM32F412ZG] does have the trace pins.
-
-[CoreSight Connectors]: http://www2.keil.com/coresight/coresight-connectors
-[FPMCU dev board]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
-[J-Trace]: https://www.segger.com/products/debug-probes/j-trace/models/j-trace/
-[JLink Software]: https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
-[Servo Micro]: ./fingerprint-dev-for-partners.md#Servo-Micro
-[JTAG to SWD Adapter]: https://www.adafruit.com/product/2094
-[SWD Cable]: https://www.adafruit.com/product/1675
-[Ozone]: https://www.segger.com/products/development-tools/ozone-j-link-debugger/
-[CLion]: https://www.jetbrains.com/clion/
-[CLion for Chrome OS]: http://go/clion-for-chromeos
-[GDB Remote Debug Configuration]: https://www.jetbrains.com/help/clion/remote-debug.html#remote-config
-[CLion Start Remote Debug]: https://www.jetbrains.com/help/clion/remote-debug.html#start-remote-debug
-[Nucleo STM32F412ZG]: https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
-[Nucleo STM32H743ZI]: https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
-[`.gdbinit`]: /util/gdbinit
-[configure `~/.gdbinit`]: https://www.jetbrains.com/help/clion/configuring-debugger-options.html#gdbinit-lldbinit
-[power pin]: https://www.segger.com/products/debug-probes/j-link/technology/interface-description/
-[fingerprint hardware]: ./fingerprint.md#hardware
-[`flash_jlink.py`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_jlink.py
-
-<!-- Images -->
-
-[Dragonclaw with 20-pin SWD]: ../images/dragonclaw_with_20_pin_swd.jpg
-[Dragonclaw with 10-pin SWD]: ../images/dragonclaw_with_10_pin_swd.jpg
-[Icetower with 20-pin SWD]: ../images/icetower_with_20_pin_swd.jpg
diff --git a/docs/fingerprint/fingerprint-dev-for-partners.md b/docs/fingerprint/fingerprint-dev-for-partners.md
deleted file mode 100644
index 2d9332db5b..0000000000
--- a/docs/fingerprint/fingerprint-dev-for-partners.md
+++ /dev/null
@@ -1,657 +0,0 @@
-# FPMCU Development for Partners
-
-This document is intended to help partners (sensor vendors, MCU vendors, etc)
-that are currently (or interested in) developing fingerprint solutions for
-Chromebooks. The document assumes that you're using Linux to do the development;
-preferably a recent version of Ubuntu or Debian. Some partners have had success
-developing in a VM, but please note that we don't test that configuration.
-
-See the [FPMCU documentation] for additional development information.
-
-[TOC]
-
-## Hardware Required for Standalone Development (no Chromebook)
-
-The following hardware components can be used to set up a standalone development
-environment for FPMCU development (i.e., it does not rely on a Chromebook).
-Development for other [EC]s is often done in a similar manner, but some of them
-have their own standalone development or evaluation kits that don't require the
-use of [servo].
-
-You will need an [FPMCU reference board](#fpmcu-dev-board) and a
-[servo debugger](#servo).
-
-### FPMCU board {#fpmcu-dev-board}
-
-The Fingerprint MCU (FPMCU) board has the MCU that handles all
-fingerprint-related functionality (matching, encryption, etc). The fingerprint
-sensor itself connects to the FPMCU board.
-
-This FPMCU board is the Dragonclaw Rev 0.2. |
-------------------------------------------- |
-![Dragonclaw board]                         |
-
-Download the [Dragonclaw schematics, layout, and BOM][dragonclaw schematics].
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**Googlers**: You can pick up the Dragonclaw development board at Chromestop.
-**Partners**: You can request a Dragonclaw development board from Google.
-***
-
-*** note
-Dragonclaw Rev 0.2 needs a [rework](#dragonclaw-rev-0.2-rework) for the FPC
-sensor to work while being powered through Servo. All of the boards at Chromestop
-have already been reworked.
-***
-<!-- mdformat on -->
-
-This FPMCU board is the Dartmonkey Rev 0.1. |
-------------------------------------------- |
-![Dartmonkey board]                         |
-
-### Servo
-
-Servo is a general purpose debug board that connects to a header on the FPMCU
-board. Among other things, the servo supplies power to the FPMCU and can be used
-to program the FPMCU, interact with the EC console, take power measurements, and
-debug a running program. It supports SPI, UART, I2C, as well as JTAG/SWD.
-
-There are two different servo debugger setups supported, the
-[Servo Micro](#servo-micro) and the [Servo V2 + Yoshi](#servo-v2-yoshi). The
-servo micro is recommended for its simplicity. It lacks builtin JTAG/SWD support
-for single step debugging, but Dragonclaw v0.2 has an
-[SWD connector](#servo-micro-swd) that can be used.
-
-[Servo Micro](#servo-micro) | [ServoV2 + Yoshi](#servo-v2-yoshi)
---------------------------- | ----------------------------------
-![Servo Micro]              | ServoV2 ![Servo v2] Yoshi Flex ![Standard Yoshi Flex]
-
-<!-- mdformat off(b/139308852) -->
-*** note
-For more information about both servos, see [servo].
-***
-<!-- mdformat on -->
-
-### Servo Micro
-
-Unlike the Servo V2, the newer servo micro does not require any adapters to
-interface with the FPMCU board.
-
-As you can see below, one end connects to the FPMCU board and the other connect
-to the developer's computer over micro USB.
-
-![Servo Micro with Dragonclaw]
-
-<!-- mdformat off(b/139308852) -->
-*** note
-For more information about Servo Micro, see [Servo Micro Info].
-***
-<!-- mdformat on -->
-
-#### Using SWD (Optional) {#servo-micro-swd}
-
-Instructions for setup are described in [Fingerprint Debugging].
-
-### Servo V2 + Yoshi
-
-Servo V2 is the original full featured debugger. It requires a
-[Yoshi Flex Cable](#yoshi-flex-cable) to interface with the FPMCU.
-
-![Servo v2]
-
-<!-- mdformat off(b/139308852) -->
-*** note
-NOTE: More information on servo can be found in the [servo] documentation.
-***
-<!-- mdformat on -->
-
-#### Yoshi Flex Cable
-
-The Yoshi Flex cable is used to connect Servo v2 to the FPMCU board. The
-standard cable does not work with SWD, but a simple rework can be performed to
-support SWD.
-
-Standard Yoshi Flex    | Yoshi Flex Reworked to Support SWD
----------------------- | -------------------------------------
-![Standard Yoshi Flex] | ![Yoshi Flex Reworked to Support SWD]
-
-Rework steps:
-
-*   Remove R18 and R19
-*   Wire from Pin 6 of U21 to right side of R18
-*   Wire from Pin 6 of U21 to right side of R19
-
-#### Micro USB Cable
-
-A micro USB cable is needed to connect the the servo v2 board to your host Linux
-development machine.
-
-*   [Micro USB Cable]
-
-#### Servo V2 Hardware Setup
-
-1.  Connect the Yoshi Flex cable to servo, paying attention to the pin
-    numbering.
-
-    ![Connect Yoshi Flex] ![Another Yoshi Flex image]
-
-2.  Connect the other end of the Yoshi Flex cable to the servo header on the
-    FPMCU board.
-
-    ![Connect Yoshi Flex to FPMCU board] ![Another image]
-
-3.  Connect the fingerprint sensor to the header on the FPMCU board.
-
-4.  Connect the micro USB cable to servo's `HOST_IN` port. The other end of the
-    USB cable should be plugged into your host development machine.
-
-    ![Connect USB to Servo]
-
-5.  Optional: Connect SWD Debugger
-
-    If you want to use SWD for debugging, connect your debugger to the `JTAG`
-    header on servo v2.
-
-    ![Connect SWD Debugger]
-
-## Software Setup
-
-### Get the Chromium OS source code
-
-*   First, make sure you [have the prerequisites].
-*   Then [get the source].
-*   Create and [enter the `chroot`].
-    *   You can stop after the `enter the chroot` step.
-
-### Build the [EC]\ (embedded controller) codebase
-
-Open **two** terminals and enter the chroot in each:
-
-```bash
-# from a terminal on your machine
-(outside chroot) $ cd ~/chromiumos/src
-
-# enter the chroot (the flag is important)
-(outside chroot) $ cros_sdk --no-ns-pid
-```
-
-<!-- mdformat off(b/139308852) -->
-*** note
-NOTE: More information on servo can be found in the [servo] documentation.
-***
-<!-- mdformat on -->
-
-In one of the terminals, build and start `servod`
-
-Build and install `servod` in the chroot:
-
-```bash
-(chroot) $ sudo emerge hdctools
-```
-
-<!-- mdformat off(b/139308852) -->
-*** note
-In all of the following commands, replace `<BOARD>` in the command with
-`bloonchipper` or `dartmonkey` depending on the development board you are using.
-***
-<!-- mdformat on -->
-
-Run `servod`:
-
-```bash
-(chroot) $ sudo servod --board=<BOARD>
-```
-
-You should see something like this. Leave it running:
-
-```bash
-2019-04-11 15:21:53,715 - servod - INFO - Start
-2019-04-11 15:21:53,765 - servod - INFO - Found servo, vid: 0x18d1 pid: 0x5002 sid: 911416-00789
-2019-04-11 15:21:53,766 - servod - INFO - Found XML overlay for board zerblebarn
-2019-04-11 15:21:53,766 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_v2_r1.xml, None, 0)
-2019-04-11 15:21:53,767 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_v2_r0.xml, None, 0)
-2019-04-11 15:21:53,771 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/common.xml, None, 0)
-2019-04-11 15:21:53,772 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/power_tools.xml, None, 0)
-2019-04-11 15:21:53,774 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/keyboard.xml, None, 0)
-2019-04-11 15:21:53,775 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/uart_common.xml, None, 0)
-2019-04-11 15:21:53,777 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/ftdii2c_cmd.xml, None, 0)
-2019-04-11 15:21:53,777 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/usb_image_management.xml, None, 0)
-2019-04-11 15:21:53,784 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servo_zerblebarn_overlay.xml, None, 0)
-2019-04-11 15:21:53,785 - SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/servoflex_v2_r0_p50.xml, None, 0)
-2019-04-11 15:21:53,792 - Servod - INFO - Initializing interface 1 to ftdi_empty
-2019-04-11 15:21:53,792 - Servod - INFO - Initializing interface 2 to ftdi_i2c
-2019-04-11 15:21:53,795 - Servod - INFO - Initializing interface 3 to ftdi_uart
-2019-04-11 15:21:53,799 - Servod - INFO - /dev/pts/8
-2019-04-11 15:21:53,799 - Servod - INFO - Initializing interface 4 to ftdi_uart
-2019-04-11 15:21:53,802 - Servod - INFO - /dev/pts/9
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 5 to ftdi_empty
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 6 to ftdi_empty
-2019-04-11 15:21:53,802 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,802 - Servod - INFO - Initializing interface 7 to ftdi_uart
-2019-04-11 15:21:53,805 - Servod - INFO - /dev/pts/10
-2019-04-11 15:21:53,805 - Servod - INFO - Use the next FTDI part @ pid = 0x5003
-2019-04-11 15:21:53,805 - Servod - INFO - Initializing interface 8 to ftdi_uart
-2019-04-11 15:21:53,808 - Servod - INFO - /dev/pts/11
-2019-04-11 15:21:53,808 - Servod - INFO - Initializing interface 9 to ec3po_uart
-2019-04-11 15:21:53,811 - PD/Cr50 - EC3PO Interface - INFO - -------------------- PD/Cr50 console on: /dev/pts/12
-2019-04-11 15:21:53,811 - Servod - INFO - Initializing interface 10 to ec3po_uart
-2019-04-11 15:21:53,812 - EC - EC3PO Interface - INFO - -------------------- EC console on: /dev/pts/14
-2019-04-11 15:21:54,316 - Servod - INFO - Initialized i2c_mux to rem
-2019-04-11 15:21:54,317 - Servod - INFO - Initialized i2c_mux_en to on
-2019-04-11 15:21:54,319 - Servod - INFO - Initialized pch_disable to off
-2019-04-11 15:21:54,320 - Servod - INFO - Initialized jtag_buf_on_flex_en to off
-2019-04-11 15:21:54,321 - Servod - INFO - Initialized cold_reset to off
-2019-04-11 15:21:54,322 - Servod - INFO - Initialized warm_reset to off
-2019-04-11 15:21:54,323 - Servod - INFO - Initialized spi1_buf_on_flex_en to off
-2019-04-11 15:21:54,324 - Servod - INFO - Initialized spi_hold to off
-2019-04-11 15:21:54,326 - Servod - INFO - Initialized pwr_button to release
-2019-04-11 15:21:54,327 - Servod - INFO - Initialized lid_open to yes
-2019-04-11 15:21:54,328 - Servod - INFO - Initialized spi2_buf_on_flex_en to off
-2019-04-11 15:21:54,330 - Servod - INFO - Initialized rec_mode to off
-2019-04-11 15:21:54,331 - Servod - INFO - Initialized fw_up to off
-2019-04-11 15:21:54,332 - Servod - INFO - Initialized usb_mux_sel1 to dut_sees_usbkey
-2019-04-11 15:21:54,333 - Servod - INFO - Initialized prtctl4_pwren to on
-2019-04-11 15:21:54,334 - Servod - INFO - Initialized uart3_en to on
-2019-04-11 15:21:54,334 - Servod - INFO - Initialized dut_hub_pwren to on
-2019-04-11 15:21:54,335 - Servod - INFO - Initialized kbd_en to off
-2019-04-11 15:21:54,337 - Servod - INFO - Initialized spi1_vref to pp3300
-2019-04-11 15:21:54,338 - Servod - INFO - Initialized spi2_vref to pp1800
-2019-04-11 15:21:54,339 - Servod - INFO - Initialized uart2_en to on
-2019-04-11 15:21:54,340 - Servod - INFO - Initialized uart1_en to on
-2019-04-11 15:21:54,341 - Servod - INFO - Initialized jtag_buf_en to off
-2019-04-11 15:21:54,342 - Servod - INFO - Initialized fw_wp_en to off
-2019-04-11 15:21:54,343 - Servod - INFO - Initialized sd_vref_sel to off
-2019-04-11 15:21:54,343 - Servod - INFO - Initialized ec_ec3po_interp_connect to on
-2019-04-11 15:21:54,344 - Servod - INFO - Initialized uart3_vref to off
-2019-04-11 15:21:54,345 - Servod - INFO - Initialized jtag_vref_sel0 to pp3300
-2019-04-11 15:21:54,346 - Servod - INFO - Initialized jtag_vref_sel1 to pp3300
-2019-04-11 15:21:54,346 - Servod - INFO - Initialized fpmcu_ec3po_interp_connect to on
-2019-04-11 15:21:54,349 - ServoDeviceWatchdog - INFO - Watchdog setup for devices: set([(6353, 20482, '911416-00789')])
-2019-04-11 15:21:54,351 - servod - INFO - Listening on localhost port 9999
-```
-
-In the other terminal, build and flash the firmware:
-
-Navigate to the EC source:
-
-```bash
-(chroot) $ cd ../platform/ec
-```
-
-Build the firmware:
-
-```bash
-(chroot) $ make BOARD=<BOARD> -j
-```
-
-The resulting file will be in `build/<BOARD>/ec.bin`
-
-Flash the firmware file:
-
-```bash
-(chroot) $ ./util/flash_ec --board=<BOARD> --image=./build/<BOARD>/ec.bin
-```
-
-Prepare a serial terminal in your chroot:
-
-```bash
-(chroot) $ sudo emerge screen
-```
-
-Connect to the UART pty:
-
-```bash
-(chroot) $ sudo screen $(dut-control raw_fpmcu_console_uart_pty | cut -d: -f2)
-```
-
-Press enter key several times (may need to wait up to 20 seconds). Then you will
-see a prompt:
-
-```
->
-```
-
-At this point you are connected to the MCU's serial (UART) console. You can list
-all of the available console commands with "help":
-
-```
-> help
-```
-
-```bash
-Known commands:
-  chan           fpcapture      hcdebugsherase     fpenroll       history        spixfer        waitms
-  flashinfo      fpmatch        hostevent      sysinfo
-  flashread      gettime        md             sysjump
-  flashwp        gpioget        panicinfo      syslock
-  flashwrite     gpioset        reboot         taskinfo
-HELP LIST = more info; HELP CMD = help on CMD.
-```
-
-Start a fingerprint enrollment:
-
-```
-> fpenroll
-```
-
-### Measuring Power {#measure-power}
-
-The Dragonclaw reference board has an onboard INA that monitors the voltage and
-power draw of the MCU and FP Sensor independently.
-
-Signal Name     | Description
---------------- | -------------------------------------
-`pp3300_dx_mcu` | 3.3V supplying the MCU
-`pp3300_dx_fp`  | 3.3V supplying the fingerprint sensor
-`pp1800_dx_fp`  | 1.8V supplying the fingerprint sensor
-
-You can monitor all power and voltages by using the following command:
-
-```bash
-(chroot) $ watch -n0.5 dut-control pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
-```
-
-You can get a summary of the power over `N` seconds with:
-
-```bash
-(chroot) $ dut-control -t N pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
-```
-
-<!-- mdformat off(b/139308852) -->
-*** note
-The `_mv` suffix denotes millivolt and `_mw` suffix denotes milliwatt.
-***
-
-*** note
-See [Power Measurement Documentation] for more information.
-***
-<!-- mdformat on -->
-
-### Toggling Hardware Write Protect
-
-When using a fingerprint development board connected to servo, you can toggle
-hardware write protect for testing.
-
-**NOTE**: `servod` must be running.
-
-Check the state of hardware write protect:
-
-```bash
-(chroot) $ dut-control fw_wp_en
-```
-
-Enable hardware write protect:
-
-```bash
-(chroot) $ dut-control fw_wp_en:on
-```
-
-Disable hardware write protect:
-
-```bash
-(chroot) $ dut-control fw_wp_en:off
-```
-
-### Contributing Changes
-
-#### Using Gerrit and git
-
-If you’re not familiar with `git`, Gerrit (code review) and `repo`, here are
-some docs to help you get started:
-
-*   [Git and Gerrit Intro for Chromium OS]: Useful to get started as quickly as
-    possible, but does not explain how `git` works under the hood.
-*   [Set your editor]: Use your favorite editor when writing `git` commit
-    messages.
-*   [Chromium OS Contributing Guide]: Detailed overview of contributing changes
-    to Chromium OS and the workflow we use.
-*   [Git: Concepts and Workflow]: Good overview of how `git` actually works.
-*   [Gerrit: Concepts and Workflow]: Good overview of how Gerrit works; assumes
-    you understand `git` basics.
-*   [Life of a patch]: Android workflow, but similar to Chrome OS.
-
-The Gerrit dashboard that will show your pending reviews (and ones we have for
-you):
-
-*   [Public Gerrit]
-*   [Internal Gerrit]
-
-#### Registering for a chromium.org *Internal* Account
-
-If your partnership agreement requires non-public code sharing you will need to
-register for an account on the [Internal Gerrit]. Refer to the
-[Gerrit Credentials Setup] page for details. Once you register for an internal
-account, your contact at Google can make sure you have the necessary permissions
-to access the private repository.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: In order to use a private repository you will have to manually add it
-to the repo manifest file before running `repo sync`. Check with your contact
-at Google for the exact values to use below:
-
-**`(outside) $ ~/chromiumos/.repo/manifests/default.xml`**
-
-```xml
-<project remote="cros-internal"
-         path="CHECK WITH GOOGLE"
-         groups="firmware"
-         name="CHECK WITH GOOGLE" />
-```
-
-**`(outside) $ ~/chromiumos/.repo/manifests/remote.xml`**
-
-```xml
-<remote name="cros-internal"
-        fetch="https://chrome-internal.googlesource.com"
-        review="https://chrome-internal-review.googlesource.com" />
-```
-***
-<!-- mdformat on -->
-
-### Tracking Issues and Communication
-
-Development issue tracking and communication is done through the
-[Partner Issue Tracker]. You will use your [Partner Domain] account to access
-the [Partner Issue Tracker]. If you do not already have a [Partner Domain]
-account, please request one from your Google contact.
-
-In order to make sure that you receive email notifications for issues, please
-make sure that you [set up email forwarding] and set your
-[notification settings] appropriately. Communication should primarily be done
-through the [Partner Issue Tracker] and not email so that it can be more easily
-tracked by multiple people and a record is preserved for posterity.
-
-[Partner Issue Tracker]: https://developers.google.com/issue-tracker/guides/partner-access
-[Partner Domain]: https://developers.google.com/issue-tracker/guides/partner-domains
-[set up email forwarding]: https://developers.google.com/issue-tracker/guides/partner-domains#email_forwarding
-[notification settings]: https://developers.google.com/issue-tracker/guides/set-notification-preferences
-
-## Working with Chromebooks
-
-Chromebooks have an FPMCU (e.g., Dragonclaw) board attached to the motherboard.
-You can use the device to run `ectool` commands and test the fingerprint sensor
-from the UI.
-
-### Developer Mode and Write Protection
-
-Make sure that your fingerprint-equipped Chrome OS device is in [developer mode]
-with a *test* image flashed and [hardware write protection] disabled. Using the
-test image will allow you to SSH into the device and disabling hardware write
-protection allows you to have full access to flashing the FPMCU firmware.
-
-See [Installing Chromium] for details on flashing test images and enabling
-[developer mode].
-
-### Connecting
-
-In general, most of our development is done by connecting to the DUT (device
-under test) via SSH. We usually connect the DUT to ethernet (e.g., via USB-C to
-Ethernet converter), but WiFi should also work (assuming corporate firewall
-restrictions don’t block SSH port 22). To get the IP address, tap the
-battery/time icon in the lower right corner. Then tap on “Ethernet� followed by
-the gear icon in the upper right.
-
-```bash
-(chroot) $ ssh root@<IP_ADDRESS>
-Password: test0000
-```
-
-Once you have SSH’ed into the DUT, you should be able to run `ectool` commands.
-
-**Example**: Capture a "test_reset" image from the sensor and write it to a
-[PNM] file (viewable with the ImageMagick `display` command):
-
-```bash
-(device) $ ectool --name=cros_fp fpmode capture test_reset; ectool --name=cros_fp waitevent 5 500; ectool --name=cros_fp fpframe > /tmp/test_reset.pnm
-```
-
-Alternatively, you can access a shell via the UI on device by pressing
-`CTRL+ALT+F2` (third key on top row). Log in with `root` and `test0000`.
-
-### Flashing FPMCU from DUT
-
-Copy the firmware to the DUT:
-
-```bash
-(chroot) $ scp ./build/bloonchipper/ec.bin <DUT_IP>:/tmp/ec.bin
-```
-
-From the DUT, flash the firmware you copied:
-
-```bash
-(device) $ flash_fp_mcu /tmp/ec.bin
-```
-
-## Commit-queue Prototype Environment
-
-![CQ Prototype Environment]
-
-## Troubleshooting
-
-### Dragonclaw Rev 0.2 Rework {#dragonclaw-rev-0.2-rework}
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: All Dragonclaw v0.2 boards have been reworked, so it is not necessary
-to perform the rework yourself.
-***
-<!-- mdformat on -->
-
-Dragonclaw **Rev 0.2** has two load switches (`U4` and `U6`) that enable the
-1.8V power rail from the servo connector or motherboard connector. However, this
-switch is not compatible with 1.8V, so will always output 0V.
-
-The [rework document][Dragonclaw Rev 0.2 1.8V Rework] describes replacing these
-two switches with ones compatible with 1.8V.
-
-### Dragonclaw Rev 0.1 Servo Fix
-
-Dragonclaw **Rev 0.1** has a known issue with UART and JTAG. Most notably, this
-issue causes servo micro to fail to program the FPMCU over UART.
-
-This issue can be fixed with the following rework steps:
-
-*   Connect servo header pin 13 to pin 18
-*   Connect servo header pin 13 to pin 29
-
-![Dragonclaw servo fix diagram]
-
-### Verify that servo and debugger are connected to USB {#servo-connected}
-
-Check whether servo is enumerating on USB. If you are using a debugger
-(Lauterbach, J-Link, etc), also check to make sure it enumerates. Depending on
-the debugger being used, it may need to be powered with an external power
-supply.
-
-```bash
-(chroot) $ lsusb
-
-Bus 002 Device 003: ID 0897:0004 Lauterbach  # � This is my Lauterbach (debugger)
-Bus 001 Device 013: ID 18d1:5002 Google Inc. # � This is servo
-```
-
-### "No servos found" when running servod
-
-If you get the following message, make sure that
-[servo is connected to USB](#servo-connected). You may also want to try
-restarting your machine (or VM).
-
-```bash
-(chroot) $ sudo servod --board=bloonchipper
-2019-04-12 14:53:42,236 - servod - INFO - Start
-2019-04-12 14:53:42,270 - servod - ERROR - No servos found
-```
-
-### Losing characters in servo UART console
-
-Make sure that this interface is disabled:
-
-```bash
-(chroot) $ dut-control usbpd_ec3po_interp_connect:off
-```
-
-### FPMCU console commands
-
-*   Once the console is working you can use `help` to see the commands.
-*   There should be fingerprint commands that start with `fp` (see `fpsensor.c`
-    in the [EC] code).
-
-<!-- Links -->
-
-[EC]: https://chromium.googlesource.com/chromiumos/platform/ec
-[ectool_servo_spi]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/comm-servo-spi.c#15
-[servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/README.md
-[developer mode]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/debug_buttons.md#firmware-keyboard-interface
-[hardware write protection]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md
-[have the prerequisites]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Prerequisites
-[get the source]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source
-[enter the `chroot`]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#building-chromium-os
-[Chromium OS Contributing Guide]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/contributing.md
-[Servo Micro Info]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_micro.md
-[Set your editor]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Set-your-editor
-[Life of a patch]: https://source.android.com/setup/contribute/life-of-a-patch
-[Git: Concepts and Workflow]: https://docs.google.com/presentation/d/1IQCRPHEIX-qKo7QFxsD3V62yhyGA9_5YsYXFOiBpgkk/
-[Gerrit: Concepts and Workflow]: https://docs.google.com/presentation/d/1C73UgQdzZDw0gzpaEqIC6SPujZJhqamyqO1XOHjH-uk/
-[Public Gerrit]: https://chromium-review.googlesource.com
-[Power Measurement Documentation]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/power_measurement.md
-[Internal Gerrit]: https://chrome-internal-review.googlesource.com
-[Gerrit Credentials Setup]: https://www.chromium.org/chromium-os/developer-guide/gerrit-guide
-[Micro USB Cable]: https://www.monoprice.com/product?p_id=9762
-[PNM]: https://en.wikipedia.org/wiki/Netpbm_format
-[Git and Gerrit Intro for Chromium OS]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/git_and_gerrit_intro.md
-[Installing Chromium]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#installing-chromium-os-on-your-device
-[FPMCU documentation]: ./fingerprint.md
-[Fingerprint Debugging]: ./fingerprint-debugging.md
-[dragonclaw schematics]: ../schematics/dragonclaw
-
-<!-- Images -->
-
-[Servo Micro]: ../images/servo_micro.jpg
-[Servo Micro with Dragonclaw]: ../images/servomicro_dragonclaw.jpg
-[Servo v2]: ../images/servo_v2.jpg
-[Standard Yoshi Flex]: ../images/yoshi_flex.jpg
-[Yoshi Flex Reworked to Support SWD]: ../images/yoshi_flex_swd_rework.jpg
-[Dragonclaw board]: ../images/dragonclaw_rev_0.2.jpg
-[Dragonclaw servo fix diagram]: ../images/dragonclaw_servo_fix.jpg
-[Connect USB to Servo]: ../images/servo_v2_with_micro_usb.jpg
-[Connect Yoshi Flex]: ../images/servo_v2_with_yoshi_flex.jpg
-[Another Yoshi Flex image]: ../images/servo_v2_with_yoshi_flex2.jpg
-[Connect Yoshi Flex to FPMCU board]: ../images/dragonclaw_yoshi_flex_header.jpg
-[Another image]: ../images/dragonclaw_yoshi_flex_header2.jpg
-[Connect SWD Debugger]: ../images/servo_v2_jtag_header.jpg
-[Dartmonkey board]: ../images/dartmonkey.jpg
-
-<!-- If you make changes to the docs below make sure to regenerate the JPEGs by
-     appending "export/pdf" to the Google Drive link. -->
-
-<!-- https://docs.google.com/drawings/d/1YhOUD-Qf69NUdugT6n0cX7o7CWvb5begcdmJwv7ch6I -->
-
-[Dragonclaw Rev 0.2 1.8V Rework]: https://github.com/coreboot/chrome-ec/blob/master/docs/images/dragonclaw_rev_0.2_1.8v_load_switch_rework.pdf
-
-<!-- https://docs.google.com/drawings/d/1w2qbb4AsSxY-KTK2vXZ6TKeWHveWvS3Dkgh61ocu0wc -->
-
-[CQ Prototype Environment]: ../images/CQ_Prototype_Environment.jpg
diff --git a/docs/fingerprint/fingerprint-factory-quick-guide.md b/docs/fingerprint/fingerprint-factory-quick-guide.md
deleted file mode 100644
index c9478bf99a..0000000000
--- a/docs/fingerprint/fingerprint-factory-quick-guide.md
+++ /dev/null
@@ -1,97 +0,0 @@
-# Chrome OS Fingerprint Sensor: Quick Factory Guide
-
-The goal of this document is to outline how ODM partners can make use of the
-existing Chrome OS factory scripts to meet Chrome OS FPS factory requirements.
-
-[TOC]
-
-## Factory Requirements
-
-### Flash firmware for fingerprint sensor microcontroller (FPMCU)
-
-FPMCU firmware must be flashed before fingerprint functional test is run. ODM
-partners may work with the module house to preflash FPMCU firmware before
-factory SMT. However, this way ODM partners have to coordinate with the module
-house to make sure the preflash FPMCU firmware blob is extracted from the FSI
-release image (from /opt/google/biod/fw/). If the FPMCU firmware doesn’t match
-the FPMCU firmware blob checked into the release image, the end users will see
-the ‘critical update’ screen in their out-of-box experience, because
-bio\_fw\_updater tries to update FPMCU firmware at boot time. This is a bad user
-experience we want to avoid. Most importantly, in PVT/MP build, only the FPMCU
-firmware in the release image would be signed by MP key. So you **MUST** ensure
-FPMCU is flashed with the MP-signed firmware blob extracted from FSI, before
-shipping the devices.
-
-As opposed to pre-flashing FPMCU in the module house, ODM partners are
-encouraged to make use of
-[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/e5e903d0a0d8327dd8b9e47d2c808fd845ed73a4/py/test/pytests/update_fpmcu_firmware.py)
-to update FPMCU firmware in the factory flow. This script can detect fingerprint
-MCU board name, find the right FPMCU firmware blob for the DUT from the release
-partition, and then flash FPMCU by flash\_fp\_mcu tool. Please note that this
-script may take more than 30 secs to complete, which is slow.
-
-Since bio\_fw\_update has been disabled in factory test image via
-[crrev/c/1913645](https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1913645),
-in the factory flow, the FPMCU firmware should not be overwritten by
-boot-update-firmware service during reboot.
-
-### Run fingerprint sensor functional test
-
-Please add
-[fingerprint\_mcu.py](https://chromium.git.corp.google.com/chromiumos/platform/factory/+/a283609cd8446ba4a4b75c2e1d84c9ba24ea8422/py/test/pytests/fingerprint_mcu.py)
-to your device test list. A more detailed description about this test can be
-found
-[here](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-factory-requirements.md).
-
-### Initialize FPMCU entropy in factory finalization
-
-The support for FPMCU entropy initialization has been integrated into the
-factory finalization script. So FPMCU entropy should be automatically
-initialized in factory finalization, if a FPMCU is found on DUT. Note that FPMCU
-entropy initialization would fail if rollback\_block\_id is not equal to zero,
-which means the entropy has been initialized before. It is usually caused by
-biod trying to initialize FPMCU entropy and increment rollback\_block\_id at
-boot time. Since we have disabled biod and bio\_crypto\_init in factory test
-image via
-[crrev/c/1910290](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1910290),
-we expect rollback\_block\_id would stay zero during the factory flow, and FPMCU
-entropy initialization should succeed in factory finalization. So just run
-factory finalization as any other CrOS boards.
-
-### Enable FPMCU software write protection (SWWP) in factory finalization in PVT/MP
-
-The support for FPMCU SWWP has been integrated into factory finalization script.
-So FPMCU SWWP should be automatically enabled in factory finalization together
-with AP/EC SWWP when write\_protection arg is set to true and a FPMCU is found
-on DUT. Just run factory finalization as any other CrOS boards.
-
-### Reset entropy for factory re-finalization (in case of RMA or OQC)
-
-For the boards that have been finalized, FPMCU entropy has been initialized. So
-running re-finalization for those boards are expected to fail at FPMCU entropy
-initialization. Before running re-finalization for those boards, ODM partners
-have to remove hardware write protection (HWWP) and then run
-[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/d399a0a1bdeb7249de2721b269e7365e4486e23c/py/test/pytests/update_fpmcu_firmware.py)
-to reset rollback\_block\_id and entropy. So the follow-up re-finalization
-(which re-initialize entropy) can succeed.
-
-## References
-
-*   CrOS fingerprint factory requirements:
-    [doc link](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-factory-requirements.md)
-*   The summary of CLs:
-    *   Add a factory script to update FPMCU firmware:
-        [crrev/c/1918679](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1918679),
-        [crrev/c/1913493](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1913493),
-        [crrev/c/1927149](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1927149),
-        [crrev/c/1984618](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1984618),
-        [crrev/c/2036574](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/2036574)
-    *   Disable FPS-related services that will interfere with the factory flow:
-        [crrev/c/1913645](https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1913645),
-        [crrev/c/1910290](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1910290)
-    *   Support FPMCU in factory finalization:
-        [crrev/c/1868795](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1868795),
-        [crrev/c/1902267](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1902267),
-        [crrev/c/1900503](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1900503),
-        [crrev/c/1925927](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1925927),
-        [crrev/c/1948163](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1948163)
diff --git a/docs/fingerprint/fingerprint-factory-requirements.md b/docs/fingerprint/fingerprint-factory-requirements.md
deleted file mode 100644
index 0fc99e2740..0000000000
--- a/docs/fingerprint/fingerprint-factory-requirements.md
+++ /dev/null
@@ -1,502 +0,0 @@
-# Chrome OS Fingerprint Factory Requirements
-
-This document provides an overview of factory requirements and testing for the
-fingerprint sensor.
-
-[TOC]
-
-## Contact
-
-For questions regarding this document, please contact the
-[Chrome OS Fingerprint Team].
-
-## Terminology
-
-*   `AP`: Application Processor.
-*   `FPMCU`: Fingerprint Microcontroller.
-*   `FATP`: Final Assembly, Test, and Pack
-*   `FP sensor`: Fingerprint sensor. Directly connected to the FPMCU, not the
-    AP.
-*   `firmware`: Software that runs on the FPMCU.
-*   `finalization`: Process that is run in the factory before the device being
-    built leaves the factory.
-*   `entropy`: Cryptographically secure random bytes stored in FPMCU flash. Used
-    for encrypting/decrypting fingerprint templates.
-*   `software write protect`: Prevents the RO portion of the FPMCU’s flash from
-    being overwritten. Full details in [EC docs][Software Write Protect].
-*   `ITS`: In-Device Test Specification.
-*   `MTS`: Module Test Specification.
-*   `MQT`: Module Quality Test.
-*   `MQT2`: Module Quality Test 2.
-
-## Documents
-
-*   [FPC1025: Module Test Specification]
-*   [FPC1145: Module Test Specification]
-*   [FPC In-Device Test Specification]
-*   [Factory Fingerprint Sensor Testing for `nocturne` ]
-
-## FPMCU Firmware Location
-
-The binaries for the FPMCU firmware are located in `/opt/google/biod/fw`. Now
-that Chrome OS supports unibuild, there may be multiple firmware binaries in the
-directory since multiple sensors may be used across a single "board" (e.g., the
-`hatch` board can use either `bloonchipper` or `dartmonkey`).
-
-The correct firmware type to use for a given board can be discovered with the
-[Chrome OS Config] tool:
-
-```bash
-(dut) $ cros_config /fingerprint board
-dartmonkey
-```
-
-OR
-
-```bash
-(chroot) $  cros_config_host -c /build/<BOARD>/usr/share/chromeos-config/yaml/config.yaml -m <MODEL> get /fingerprint board
-dartmonkey
-```
-
-The corresponding firmware for the above command would be
-`/opt/google/biod/fw/dartmonkey_*.bin`.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: If you get an empty response when running the above commands, the
-Chrome OS Config settings may not have been updated for the Chrome OS board.
-See the instructions on [updating Chrome OS Config] for fingerprint.
-***
-<!-- mdformat on -->
-
-Note that the fingerprint team continuously releases updates to the firmware, so
-SIEs should watch for version changes in ToT if they are maintaining a separate
-factory branch.
-
-## Flashing the FPMCU
-
-When the FPMCU is completely blank a low-level flashing tool must be used to
-program an initial version of the FPMCU firmware. It’s possible to use the
-[`flash_fp_mcu`] script as this low-level flashing tool, though since it
-requires the AP and is not necessarily robust against failures, it is not
-recommended for mass-production. More details about [`flash_fp_mcu`] are in the
-[Fingerprint flashing documentation].
-
-The initial version of the FPMCU firmware should be flashed either by the module
-house or by the factory. Once an initial version of the FPMCU firmware has been
-flashed (i.e., the FPMCU is not blank), the `bio_fw_updater` tool runs on
-startup and handles updating the FPMCU firmware to match the version that is in
-the rootfs. Note that this update process can take around 30 seconds; if that
-length of time is an issue then the factory or module house should pre-flash the
-latest firmware beforehand.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: If the FPMCU is not flashed in the factory as part of development
-builds (EVT, etc.), it's possible for developers (or Chromestop) to manually
-run [`flash_fp_mcu`], as long as they can disable [hardware write protect].
-Obviously this only applies during development, not mass production.
-***
-<!-- mdformat on -->
-
-## biod and timberslide
-
-Since `biod` communicates with the FPMCU, it’s best to disable it when running
-the fingerprint factory tests. This can be done with upstart:
-
-```bash
-(dut) $ stop biod
-```
-
-Once testing is complete `biod` should be restarted (or you can reboot the
-device).
-
-`timberslide` is the daemon that periodically sends commands to the FPMCU to
-read the latest FPMCU logs. It writes the results to `/var/log/cros_fp.log`. It
-should be fine to leave running during tests, though it should be stopped before
-running the [`flash_fp_mcu`] script, since that script erases the entire FPMCU:
-
-```bash
-(dut) $ stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
-```
-
-## Factory Tests
-
-### Fingerprint Sensor (standalone module)
-
-When using an FPC sensor (e.g., FPC 1025, FPC 1145), the fingerprint sensor
-itself must be tested by the module manufacturer with FPC’s tools. FPC provides
-a Module Test Tool (MTT), which requires additional hardware (FPC Module Test
-Card). FPC also provides design drawings for the rubber stamp. The stamp,
-test-fixture and test station need to be implemented by the OEM/ODM/Module House
-(often only module house).
-
-The `MTS` _must_ be followed by the module manufacturer, but Google does not
-provide direct support for this testing. FPC is the main point of contact.
-
-The module testing procedure is documented in the following:
-
-[FPC1025: Module Test Specification]
-
-[FPC1145: Module Test Specification]
-
-### Fingerprint Sensor + FPMCU (in device)
-
-In-device tests are run during the `FATP` process once the device has been fully
-assembled. Google provides source code for these tests in
-[`fingerprint_mcu.py`].
-
-Hardware Required: Chrome OS DUT before finalization.
-
-Documentation: [FPC In-Device Test Specification]
-
-#### Test Image Checkerboard and Inverted Checkerboard Test (CB/ICB)
-
-##### Purpose
-
-Capture a checkerboard (and inverted checkerboard) pattern and verify that the
-values of the individual pixels do not deviate from the median.
-
-##### Implementation
-
-Use `ectool` to capture the first checkerboard pattern image:
-
-```bash
-(dut) $ ectool --name=cros_fp fpmode capture pattern0; ectool --name=cros_fp waitevent 5 500
-FP mode: (0x20000008) capture
-MKBP event 5 data: 00 00 00 80
-```
-
-Copy the first checkerboard image to a file:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe > /tmp/pattern0.pnm
-```
-
-Use `ectool` to capture the second checkerboard pattern image:
-
-```bash
-(dut) $ ectool --name=cros_fp fpmode capture pattern1; ectool --name=cros_fp waitevent 5 500
-FP mode: (0x30000008) capture
-MKBP event 5 data: 00 00 00 80
-```
-
-Copy the second checkerboard image to a different file:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe > /tmp/pattern1.pnm
-```
-
-Perform median analysis on the resulting image as described in the `MTS`
-document. The factory toolkit does this in
-[`fingerprint_mcu.py`][Checkerboard Test].
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**TIP**: You can view the `.pnm` files generated by the commands below on your
-Linux desktop with ImageMagick: `display /path/to/file.pnm`.
-***
-<!-- mdformat on -->
-
-##### Success/Failure
-
-The median pixel value (type 1 and type 2), pixel errors, finger detect zone
-errors, and pixel error deviation limit must fall within the acceptance criteria
-limits specified in "4.3.5 Acceptance Criteria Test Image CB / iCB" in the `MTS`
-document for the sensor being tested.
-
-#### Hardware Reset Test (aka IRQ test)
-
-##### Purpose
-
-Perform a hardware reset of the sensor and test that the IRQ line is asserted
-after 5 ms. See "Section 4.1 Reset test pattern procedure" and "2.8 HW Reset" in
-the FPC `MTS` document for the sensor being tested.
-
-##### Implementation
-
-This is implemented by the FPMCU on every boot. The results can be checked with
-the `ectool` command. The factory toolkit does this in
-[`fpmcu_utils.py`][GetSensorIdErrors].
-
-##### Success/Failure
-
-The `Error flags` line of the `fpinfo` `ectool` command must be empty.
-
-```bash
-(dut) $ ectool --name=cros_fp fpinfo
-
-Fingerprint sensor: vendor 20435046 product 9 model 1401 version 1
-Image: size 56x192 8 bpp
-Error flags:
-Dead pixels: UNKNOWN
-Templates: version 4 size 47616 count 0/5 dirty bitmap 0
-```
-
-#### Hardware ID (HWID) check
-
-##### Purpose
-
-Ensure that communications between the sensor and the FPMCU are working and that
-the correct sensor has been assembled.
-
-##### Implementation
-
-`ectool` can be used to request the hardware ID, which can be compared with the
-expected hardware ID. The factory toolkit does this in
-[`fpmcu_utils.py`][GetSensorId].
-
-##### Success/Failure
-
-The `Fingerprint sensor` line of the `fpinfo` `ectool` command must show the
-expected ID and the `Error flags` line must be empty:
-
-```bash
-(dut) $ ectool --name=cros_fp fpinfo
-
-Fingerprint sensor: vendor 20435046 product 9 model 1401 version 1  # FPC 1145
-Image: size 56x192 8 bpp
-Error flags:
-Dead pixels: UNKNOWN
-Templates: version 4 size 47616 count 0/5 dirty bitmap 0
-```
-
-#### Reset Pixel (RP)
-
-##### Purpose
-
-Capture a white image, compare the individual pixel values and ensure that the
-deviation to the median is within the specified range.
-
-##### Implementation
-
-Capture the test image with `ectool` and analyze the output. The factory toolkit
-does this in [`fingerprint_mcu.py`][ProcessResetPixelImage].
-
-Switch to correct capture mode and wait:
-
-```bash
-(dut) $ ectool --name=cros_fp fpmode capture test_reset; ectool --name=cros_fp waitevent 5 500
-FP mode: (0x50000008) capture
-MKBP event 5 data: 00 00 00 80
-```
-
-Retrieve the test image:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe > /tmp/test_reset.pnm
-```
-
-##### Success/Failure
-
-A pixel is considered to be a bad pixel ("reset pixel error") if the value read
-out deviates more than a defined value from the median. The median value and the
-max number of pixels that have "reset pixel error" are defined in section "Reset
-Pixel" (4.4 or 4.5) of the MTS for the given sensor.
-
-#### Module Quality Test (or Module Quality Test 2) with Rubber Stamp Zebra (Optional)
-
-##### Purpose
-
-The Module Quality Test (`MQT`) uses a rubber stamp with a "zebra" pattern to
-characterize module performance and image quality after the top layer (including
-stack-up) is applied. Although this test is optional, OEMs are strongly
-encouraged to perform it.
-
-##### Implementation
-
-Capture the image when the rubber stamp is applied:
-
-```bash
-(dut) $ ectool --name=cros_fp fpmode capture qual
-FP mode: (0x40000008) capture
-```
-
-Wait for the capture to be finished, timeout after 10s:
-
-```bash
-(dut) $ ectool --name=cros_fp waitevent 5 10000
-MKBP event 5 data: 00 00 00 80
-```
-
-Copy the raw captured from to the AP:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe raw > /tmp/fp.raw
-```
-
-Run the analysis tool on the captured frame:
-
-```bash
-(dut) $ /usr/local/opt/fpc/fputils.py --mqt /tmp/fp.raw
-Error, MQT status : (5)
-MQT failed (-1)
-```
-
-The factory toolkit does this in [`fingerprint_mcu.py`][rubber_finger_present].
-
-##### Success/Failure
-
-See "Section 5.1.5" Acceptance Criteria for `MQT2` or "Section 5.2.5 Acceptance
-Criteria" in the MTS for the given sensor.
-
-## Finalization
-
-The finalization process must perform two tasks:
-
-1.  Initialize the FPMCU’s `entropy`.
-1.  When building for PVT or mass production, enable `software write protect`.
-
-### Initialize FPMCU Entropy
-
-The `bio_wash` tool is intended to support both the first time factory
-initialization and RMA, depending on the flag. When run with the
-`--factory_init` argument (`bio_wash --factory_init`), it will ensure that the
-`entropy` is set. If the `entropy` has already been set it will do nothing.
-
-A side-effect of running `bio_wash` is that the `rollback_id` changes (`ectool
---name=cros_fp rollbackinfo`). Initially when the firmware is first flashed, the
-`rollback_id` should be zero. After `entropy` is initialized the `rollback_id`
-should be set to 1.
-
-Note that for new devices coming out of the factory we expect `rollback_id` to
-be 1, which indicates that the entropy has been set exactly once.
-
-### Enable Software Write Protect
-
-`Software write protect` must be enabled for PVT and mass production devices. It
-ensures that the RO portion of the FPMCU firmware cannot be overwritten, so it
-is critical for FPMCU security.
-
-The following commands will enable software write protection:
-
-```bash
-(dut) $ ectool --name=cros_fp flashprotect enable    # enable
-(dut) $ sleep 2
-(dut) $ ectool --name=cros_fp reboot_ec              # reboot so it takes effect
-(dut) $ sleep 2
-```
-
-To validate that software write protection has taken effect, run the following:
-
-```bash
-(dut) $ ectool --name=cros_fp flashprotect   # get flashprotect state
-
-# output should match below
-Flash protect flags: 0x0000000b wp_gpio_asserted ro_at_boot ro_now
-Valid flags:         0x0000003f wp_gpio_asserted ro_at_boot ro_now all_now STUCK INCONSISTENT
-Writable flags:      0x00000004 all_now
-```
-
-If software write protection is not enabled, you will see the following instead:
-
-```bash
-(dut) $ ectool --name=cros_fp flashprotect  # get flashprotect state
-
-# not protected
-Flash protect flags: 0x00000000
-Valid flags:         0x0000003f wp_gpio_asserted ro_at_boot ro_now all_now STUCK INCONSISTENT
-Writable flags:      0x00000001 ro_at_boot
-```
-
-Capturing a raw frame from the sensor will only work when software write
-protection is not enabled, so the test should check the following command works
-*before* write protection is enabled and then fails *after* write protection is
-enabled:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe raw
-
-# write protection disabled, exit code 0 and output will be raw bytes
-
-# write protection enabled, exit code 1 and output will be
-EC result 4 (ACCESS_DENIED)
-Failed to get FP sensor frame
-```
-
-## RMA Process
-
-As part of the RMA process, the `entropy` needs to be reset so that the new
-device owner has a new unique encryption key.
-
-The `bio_wash` tool is intended to support both the first time factory
-initialization and RMA, depending on the flag. When run without any arguments
-(`bio_wash`), it will forcibly reset the entropy.
-
-The RMA process should either run `bio_wash` without any arguments or re-flash
-the FPMCU firmware and then run `bio_wash --factory_init` to make sure that the
-entropy has been reset.
-
-## Miscellaneous Commands for Test Implementations
-
-### FPMCU Image Version
-
-```bash
-(dut) $ ectool --name=cros_fp version
-
-RO version:    nocturne_fp_v2.2.64-58cf5974e
-RW version:    nocturne_fp_v2.2.110-b936c0a3c
-Firmware copy: RW
-Build info:    nocturne_fp_v2.2.110-b936c0a3c 2018-11-02 14:16:46 @swarm-cros-461
-Tool version:  v2.0.2144-1524c164f 2019-09-09 06:50:36 @chromeos-ci-legacy-us-central2-d-x32-7-3ay8
-```
-
-### Capture Raw Images
-
-Put your finger on the sensor, then run:
-
-```bash
-(dut) $ ectool --name=cros_fp fpmode capture vendor
-```
-
-Wait for the capture to be finished, timeout after 10s:
-
-```bash
-(dut) $ ectool --name=cros_fp waitevent 5 10000
-MKBP event 5 data: 00 00 00 80
-```
-
-Remove the finger from the sensor, then start the retrieval of the frame from
-the MCU to the AP:
-
-```bash
-(dut) $ ectool --name=cros_fp fpframe raw > /tmp/fp.raw
-```
-
-To convert the images from FPC’s proprietary format to PNG, you will need to
-have `cros deploy`’d `libfputils-nocturne`, which will install the required
-utilities in `/opt/fpc`.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: As of 2019-05-21, the `libfputils` library only works for the FPC 1145
-sensor (in nocturne), not the FPC 1025 sensor (hatch).
-***
-<!-- mdformat on -->
-
-Convert the buffer in proprietary format into png:
-
-```bash
-(dut) $ /opt/fpc/fputils.py /tmp/fp.raw --png
-Extraction found 2 images
-Wrote /tmp/fp.0.png (14085 bytes)
-Wrote /tmp/fp.1.png (14025 bytes)
-```
-
-[Software Write Protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md#Software-Write-Protect
-[hardware write protect]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/write_protection.md#hw_wp
-[FPC1025: Module Test Specification]: http://go/cros-fingerprint-fpc1025-module-test-spec
-[FPC1145: Module Test Specification]: http://go/cros-fingerprint-fpc1145-module-test-spec
-[FPC In-Device Test Specification]: http://go/cros-fingerprint-fpc-indevice-test-spec
-[`fingerprint_mcu.py`]: https://chromium.googlesource.com/chromiumos/platform/factory/+/HEAD/py/test/pytests/fingerprint_mcu.py
-[Checkerboard Test]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#166
-[GetSensorIdErrors]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/utils/fpmcu_utils.py#73
-[GetSensorId]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/utils/fpmcu_utils.py#65
-[ProcessResetPixelImage]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#268
-[rubber_finger_present]: https://chromium.googlesource.com/chromiumos/platform/factory/+/d23ebc7eeb074760e8a720e3acac4cfe4073b2ae/py/test/pytests/fingerprint_mcu.py#330
-[Chrome OS Fingerprint Team]: http://go/cros-fingerprint-docs
-[Factory Fingerprint Sensor Testing for `nocturne`]: http://go/fingerprint-factory-testing-nocturne
-[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_fp_mcu
-[Fingerprint flashing documentation]: ./fingerprint.md#factory-rma-dev-updates
-[Chrome OS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md
-[updating Chrome OS Config]: ./fingerprint.md#update-chromeos-config
diff --git a/docs/fingerprint/fingerprint-firmware-testing-for-partners.md b/docs/fingerprint/fingerprint-firmware-testing-for-partners.md
deleted file mode 100644
index 3432bb0aac..0000000000
--- a/docs/fingerprint/fingerprint-firmware-testing-for-partners.md
+++ /dev/null
@@ -1,112 +0,0 @@
-# Fingerprint Firmware Testing Instructions for Partners
-
-This document is intended to help partners (sensor vendors, MCU vendors, etc)
-run the Chrome OS fingerprint team's firmware tests, as part of the AVL process.
-The document assumes that you‘re using Linux to do the development; preferably a
-recent version of Ubuntu or Debian. It may be possible to use a virtual machine,
-but that is not a configuration we test.
-
-[TOC]
-
-## Hardware Requirements
-
-You will need a Chromebook with the fingerprint sensor and fingerprint MCU
-(FPMCU), and a [servo debugger].
-
-### Chromebook with fingerprint sensor
-
-The Chromebook needs to be in [developer mode] and running a test image so that
-the test can ssh into it. The fingerprint firmware tests will run a series of
-bash commands, including flashing the FPMCU firmware and rebooting the
-Chromebook. You do not need [CCD] because servo will handle the firmware write
-protection for you.
-
-### Servo
-
-Servo is a general purpose debug board used in many automated tests in Chromium
-OS. Among other things, servo enables the tests to toggle hardware write
-protect.
-
-While there are multiple versions of servo, for firmware tests we strongly
-recommend [Servo V4] as that's the simplest and most often used in autotests.
-This document will assume you are using Servo V4.
-
-### Hardware Setup
-
-*   Connect the "HOST" side of Servo V4 to your host machine (which should have
-    a Chromium OS chroot).
-*   Connect the other side of Servo V4 to a USB port on the Chromebook with
-    fingerprint sensor.
-*   Connect the "DUT POWER" side of Servo V4 to power supply.
-*   Make sure the USB cable from the host machine to Servo V4 is in data
-    transfer mode (i.e. if there's an LED, it should be yellow instead of
-    green).
-*   Make sure the you can ssh into the Chromebook from the chroot on the host
-    machine.
-
-## Software Setup
-
-### Get the Chromium OS source code.
-
-*   First, make sure you [have the prerequisites].
-*   Then [get the source].
-
-### Build the autotest codebase
-
-```bash
-# from a terminal on your machine
-(outside chroot) $ cd ~/chromiumos/src
-
-# enter the chroot (the flag is important)
-(outside chroot) $ cros_sdk --no-ns-pid
-
-# build autotest for the board to be tested
-(chroot) $ emerge-<BOARD> autotest
-```
-
-### Start servod
-
-```bash
-(chroot) $ sudo servod --board=<BOARD>
-```
-
-At this point the servod daemon should be running and listening to port 9999 by
-default. If it isn't, check the hardware connection.
-
-## Run a Single Fingerprint Firmware Test
-
-Use another terminal and enter the chroot like before:
-
-```bash
-(outside chroot) $ cd ~/chromiumos/src
-(outside chroot) $ cros_sdk --no-ns-pid
-```
-
-To run a single test, use this command in your chroot:
-
-```bash
-test_that --board=<BOARD> <IP> <test name>
-```
-
-For example:
-
-```bash
-test_that --board=nocturne <IP> firmware_Fingerprint.ReadFlash
-```
-
-## Run the Entire Fingerprint Firmware Test Suite
-
-To run the entire suite, use this command in your chroot:
-
-```bash
-test_that --board=<BOARD> <IP> suite:fingerprint
-```
-
-<!-- Links -->
-
-[servo debugger]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo.md
-[developer mode]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md
-[CCD]: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/cr50_stab/docs/case_closed_debugging.md
-[Servo V4]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_v4.md
-[have the prerequisites]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Prerequisites
-[get the source]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source
diff --git a/docs/fingerprint/fingerprint-tpm-seed.md b/docs/fingerprint/fingerprint-tpm-seed.md
deleted file mode 100644
index 904fb7243a..0000000000
--- a/docs/fingerprint/fingerprint-tpm-seed.md
+++ /dev/null
@@ -1,324 +0,0 @@
-# TPM Seed for Fingerprint MCU
-
-Authors: pmalani@google.com, norvez@google.com
-
-Reviewers: semenzato@google.com, apronin@google.com, mnissler@google.com and
-others
-
-Last Updated: 2018-11-01
-
-[TOC]
-
-## Objective
-
-Increase security for Fingerprint (FP) templates by using a TPM-sourced seed in
-addition to internal FPMCU entropy while encrypting FP templates. The
-TPM-sourced seed will be derived from the system key which is loaded from the
-TPM during boot in mount-encrypted.
-
-## Background
-
-Fingerprint authorization in Chrome OS, relies on encrypted FP templates which
-are stored in each user’s mount directory. These templates are created and
-encrypted by the FPMCU during FP enrollment, before being sent back to the AP
-(Application Processor). When the user logs in, these templates are sent to the
-FPMCU where they get decrypted and loaded.
-
-The encryption is performed in the FPMCU using entropy which is internal to the
-MCU and never leaves the MCU. That way, even if the templates are somehow
-obtained by and attacker from the user mount directory, they cannot be
-decrypted, since the attacker will not have access to the MCU entropy. This
-entropy gets reset on every powerwash/recovery.
-
-The complete design doc is [Fingerprint Authentication on Chrome OS].
-
-## Requirements and Scale
-
-The solution proposed should exhibit the following attributes:
-
-*   Strengthens security of FP templates.
-*   Does not compromise the security of other sub-systems.
-*   Works fast and doesn’t affect time to boot, or reduce boot-time stability.
-
-## Design Ideas
-
-In addition to FPMCU entropy, we include a TPM-sourced seed (derived from the
-system key) while performing template encryption. The TPM system key gets
-regenerated during powerwash/recovery, so in the event that the FP templates are
-accessed due to a runtime exploit, a power-wash / recovery from the user will
-ensure:
-
-*   The raw templates cannot be decrypted, since the TPM-seed would have been
-    lost irrevocably.
-*   Since a new TPM-seed is generated (since a new system key is created), old
-    templates can’t be re-used, even if the attacker could somehow gain access
-    to the FP MCU entropy.
-
-The overall design consists of two components:
-
-*   Generating a TPM-seed and sending it to the Biometric sensor managers.
-*   The Bio sensor managers sending the seed to the FPMCU and programming it
-    into the encryption / decryption operations of FP templates.
-
-### TPM seed generation {#seed-generation}
-
-![TPM Seed Diagram]
-
-The TPM seed generation would proceed as follows:
-
-1.  During mount-encrypted execution, after the `System_key` is loaded, the
-    TPM-backed system key will be HMAC-ed with a simple salt (the string
-    `biod`):
-
-    ```
-    TPM_Seed = HMAC_SHA256(System_key, "biod")
-    ```
-
-2.  The resulting 256-bit seed (called `TPM_Seed`) will be maintained in a
-    `brillo::SecureBlob`.
-
-3.  The `TPM_seed` will be saved into a tmpfs file
-    (`/run/biod_crypto_init/seed`) for consumption by `bio_crypto_init`. This
-    file's ownership will be set up such that only user/group `biod` can access
-    it.
-
-4.  `bio_crypto_init` (the binary which sends the seed to the FPMCU) will be
-    spawned after mount-encrypted completes. This is ensured by setting the
-    `bio_crypto_init` upstart rules to depend on `starting boot-services`
-
-5.  On the `bio_crypto_init` side, the `TPM_seed` will be retrieved from the
-    tmpfs file and forwarded to the FP MCU via the various BiometricManagers.
-    Immediately after reading from the tmpfs file, `bio_crypto_init` will nuke
-    (write all 0’s and then delete) the tmpfs file.
-
-6.  The upstart rules of biod will be modified such that it will start after
-    `bio_crypto_init` stops (this modification can be made in the `.conf` file
-    of biod)
-
-#### IPC Mechanism {#ipc}
-
-(For a discussion of various alternatives, please see the
-[Alternatives Considered] section)
-
-The IPC mechanism selected should have the following features:
-
-*   Allow to quickly pass the `TPM_seed` between mount-encrypted and
-    `bio_crypto_init`.
-*   Minimize the presence of extra/asynchronously deleted copies of the
-    `TPM_seed` buffer in kernel and memory. This is crucial to minimize the risk
-    of access to this seed.
-
-The currently proposed method of passing the `TPM_seed` is to use a **file in
-tmpfs**. The sequence would be as follows:
-
-*   mount-encrypted will write the `TPM_Seed` to a file in `/run`
-    (`/run/bio_crypto_init/seed`). `/run` is a tmpfs created by the OS for use
-    by various system services.
-*   `bio_crypto_init` will read the `TPM_Seed` from the known tmpfs file.
-*   As soon as `bio_crypto_init` reads the `TPM_Seed`, it will first overwrite
-    (`/run/biod_crypto_init/seed`) with all 0s, and immediately after will
-    delete `/run/biod_crypto_init/seed`.
-*   `bio_crypto_init` can then instantiate its BiometricManager classes and send
-    the data to the FP MCU. This way, even if the sending of data fails, there
-    will not be any stray copy of the `TPM_seed` in a process’s memory, or in
-    tmpfs.
-
-##### Advantages
-
-*   No/minimal buffering of copies of `TPM_Seed` in kernel.
-*   No need to create and pass FDs between mount-encrypted and
-    `bio_crypto_init`.
-
-##### Disadvantages
-
-*   If `bio_crypto_init` crashes / fails to start, the tmpfs file remains in the
-    system, i.e cleanup of tmpfs is reliant on `bio_crypto_init`.
-
-### Programming TPM_Seed into MCU
-
-#### Entropy addition v/s programming TPM Seed
-
-When a device boots up for the first time after going through
-recovery/powerwash, biod will force an "Add Entropy" step. This involves:
-
-*   rebooting the FP MCU to RO
-*   Performing an entropy addition step
-*   Rebooting the FP MCU to RW
-*   Verifying that the entropy addition has taken place (by checking the block
-    ID of the rollback info on the MCU).
-
-Unfortunately, since the `TPM_Seed` will be stored in MCU RAM, the reboot of the
-FPMCU will lead to the `TPM_Seed` being lost until the next boot. In the absence
-of a `TPM_Seed`, all FPMCU operations will fail (until the next boot). There is
-no opportunity to reprogram the `TPM_Seed`, because that must take place during
-mount-encrypted, which must necessarily run before `biod` starts.
-
-There are two proposals to work around this issue. The one eventually selected
-has been included here, and the other alternative has been placed in the
-[Alternatives Considered] section.
-
-##### Make bio_crypto_init solely set the TPM_Seed (don't perform entropy_add)
-
-In this method, `bio_crypto_init` will not perform any reboot on the MCU, and
-solely program the `TPM_Seed`. This would mean that if a device was to boot for
-a first time without having done any previous powerwash/recovery, the first boot
-would not have FP functionality. FP functionality would be regained on all
-subsequent boot (since the entropy would have been added/initialized by then).
-
-The downside of this approach is a poor user experience.
-
-The benefit is a simple implementation of the `bio_crypto_init` tool, which will
-consequently also take less time to execute (booting to RO/RW are time consuming
-operations).
-
-In practice all devices leaving the factory floor would have `bio_wash
---factory_init` done on them during finalisation to initialise the entropy, and
-so this shouldn't affect a large majority of end users.
-
-### Signaling biod to start
-
-In order to avoid races which might occur because both `bio_crypto_init` and
-`biod` will try to access the `BiometricManagers`' hardware. We need to ensure
-that `biod` only starts after `bio_crypto_init` ends.
-
-To accomplish this, `biod.conf` will be modified to include a dependency on
-`bio_crypto_init` to start the daemon. So, the relevant portion of `biod.conf`
-will now be:
-
-```
-start on started system-services and started uinput and stopped bio_crypto_init
-```
-
-### Formula to calculate IKM used for encryption in MCU
-
-In the FPMCU we will use the concatenation of `TPM_Seed` and [`SBP_Src_Key`] as
-Input Key Material (IKM) to derive an encryption key. Combined with a random
-salt, the pseudo random key (PRK) would be derived as:
-
-```
-PRK = HMAC_SHA256(Random_Salt, SBP_Src_Key || TPM_Seed)
-```
-
-## Alternatives Considered {#alt-considered}
-
-A few alternatives are being considered for the IPC Mechanism
-
-#### pipe/socketpair
-
-##### Disadvantages
-
-*   The data written to pipes is buffered in internal kernel buffers till it is
-    read out from the other end of the pipe/socketpair. In the case of a
-    `bio_crypto_init` crashing, this will leave a copy in the internal kernel
-    buffers. Question: How long before those internal buffers get cleared in the
-    case of the pipe not being read from?
-
-#### Anonymous file (memfd_create) / Anonymous mmap
-
-##### Disadvantages
-
-*   Question: When all references to the anonymous file are dropped, are the
-    contents of the anonymous file re-allocated, overwritten, or is the
-    corresponding inode simply destroyed (and the data blocks still stick around
-    and are reallocated lazily ?)
-
-There was also another alternative considered for the sequence of programming
-the TPM seed and initializing the FPMCU: make `bio_crypto_init` add entropy and
-then set TPM.
-
-## Security Considerations
-
-### Security boundaries
-
-*   A new minijailed process (`bio_crypto_init`) is run when `starting
-    boot-services` is signaled.
-*   An IPC takes place between mount-encrypted and `bio_crypto_init` via a tmpfs
-    file. The reading and deletion of the tmpfs file is detailed in the
-    [IPC Mechanism] section.
-
-### Privileges
-
-*   `bio_crypto_init` runs minijail-ed and runs with user/group `biod`. Only the
-    files required for its functioning (i.e., the tmpfs file `/run/`, the
-    devnode to access the FPMCU, log directory inside
-    `/var/log/bio_crypto_init`) are mounted and visible inside the sandbox. See
-    the [minijail0 arguments] for a full explanation.
-
-### Untrusted input
-
-*   The only input is the `System_key` which is retrieved from the TPM anyway
-    during mount-encrypted execution. Thus, no additional or new input is being
-    fed to the feature.
-*   Additionally, the derived TPM-seed is saved in a tmpfs file which has a
-    user/group ownership as `biod` so only users `root` or `biod` can access the
-    file. Since `bio_crypto_init` runs only during `starting boot-services` and
-    the process along with the conf file ensures that the file is deleted after
-    execution, there is no additional threat of the `/tmp` file being corrupted.
-
-### Sensitive data
-
-*   The feature involves the storage of a `TPM_Seed` derived from the
-    `System_key` from TPM, in a file on tmpfs (the file is zeroed and deleted
-    once read by `bio_crypto_init`).
-
-### Attack surface
-
-*   In the event of the contents of the tmp file being read, the `TPM_Seed`
-    would not be of much use to the attacker, since the use of `HMAC_SHA256`
-    means the attacker would still not have access to the system key (brute
-    force trial of HMAC 256 would be required to guess the system salt required
-    to produce the TPM-seed).
-*   In the unlikely event of the contents of the tmp file being modified before
-    they are programmed into the FPMCU, FP unlock would fail (since the
-    encrypted templates would not longer be decrypted correctly, since the FPMCU
-    encryption key would have changed). The FP templates encryption key is a
-    combination of both the `TPM_seed` as well as the internal `SBP_Src_Key`
-    combined with a random salt, and since only the encrypted templates are
-    stored on the rootfs, the templates would simply be rendered useless. A
-    powerwash/recovery can help restore functionality of FP unlock, but new
-    templates would have to be registered.
-*   This code should not be accessible to remote attackers.
-
-### Implementation robustness
-
-*   `bio_crypto_init` uses two processes. A child process is spawned by
-    `bio_crypto_init` and the FPMCU programming is done on the child process.
-    The parent process waits for the child process to complete, or kills the
-    process if it exceeds a timeout limit. This ensures that the process doesn't
-    hang indefinitely.
-*   The feature uses tmpfs (`/run/bio_crypto_init/seed`) as an IPC mechanism to
-    transfer the `TPM_Seed` between mount-encrypted and `bio_crypto_init`.
-    Please see the [Alternatives Considered] and [Design Ideas] section
-    regarding rationale behind choosing tmpfs vis a vis socketpair/pipe.
-
-### Cryptography
-
-*   `HMAC_SHA256` is used to derived `TPM_Seed` from the `System_key` as
-    described in section [TPM seed generation].
-
-*   `HMAC_SHA256` is also used to derive the FPMCU’s encryption key. This is the
-    same as it was earlier; the only change is that source key has been updated
-    to also include the `TPM_Seed`.
-
-## Privacy Considerations
-
-This implementation should not have any adverse implications on Privacy (over
-and above existing functionality on Chrome OS). This provides security hardening
-for the fingerprint templates to prevent their retrieval and mis-use.
-
-[Fingerprint Authentication on Chrome OS]: ../fingerprint/fingerprint-authentication-design-doc.md
-[`SBP_Src_Key`]: ../fingerprint/fingerprint-authentication-design-doc.md#sbp-secret-generation
-[IPC Mechanism]: #ipc
-[minijail0 arguments]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform2/biod/init/bio_crypto_init.conf;l=36;drc=1fcefaa166e868069ad1b81091333ff75e0657f6
-[Design Ideas]: #design-ideas
-[TPM seed generation]: #seed-generation
-[Alternatives Considered]: #alt-considered
-
-<!-- Images -->
-
-<!-- If you make changes to the docs below make sure to regenerate the PNGs by
-     appending "export/png" to the Google Drive link. -->
-
-<!-- https://docs.google.com/drawings/d/1d0ocdnEjsO26c3usP1FwgTZ7VwEr-4ydnC0WMhOnbLY -->
-
-[TPM Seed Diagram]: ../images/cros_fingerprint_tpm_seed.png
diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md
deleted file mode 100644
index 39785f5afb..0000000000
--- a/docs/fingerprint/fingerprint.md
+++ /dev/null
@@ -1,590 +0,0 @@
-# Fingerprint Firmware (FPMCU)
-
-[TOC]
-
-<!-- mdformat off(b/139308852) -->
-*** note
-NOTE: The build commands assume you are in the `~/trunk/src/platform/ec`
-directory inside the chroot.
-***
-<!-- mdformat on -->
-
-<!-- mdformat off(b/139308852) -->
-*** note
-WARNING: When switching branches in the EC codebase, you probably want to nuke
-the `build` directory or at least the board you're working on: `rm -rf
-build/<board>` or `make clobber` to prevent compilation errors.
-***
-<!-- mdformat on -->
-
-## Software
-
-The main source code for fingerprint sensor functionality lives in the
-[`common/fpsensor`] directory. The driver code for specific sensors lives in the
-[`driver/fingerprint`] directory.
-
-## Hardware {#hardware}
-
-The following "boards" (specified by the `BOARD` environment variable when
-building the EC code) are for fingerprint:
-
-MCU                    | Sensor     | Firmware (EC "board")                          | Dev Board                                    | Nucleo Board
----------------------- | ---------- | ---------------------------------------------- | -------------------------------------------- | ------------
-[STM32H743] \(Cortex-M7) | [FPC 1145] | `dartmonkey`<br>(aka `nocturne_fp`, `nami_fp`) | [Icetower v0.2] <br>(Previously Dragontalon) | [Nucleo H743ZI2]
-[STM32F412] \(Cortex-M4) | [FPC 1025] | `bloonchipper`<br>(aka `hatch_fp`)             | [Dragonclaw v0.2]                            | [Nucleo F412ZG]
-
-### Sensor Template Sizes
-
-Sensor     | Fingerprint Template Size
----------- | --------------------------------
-[FPC 1145] | [~48 KB][FPC 1145 Template Size]
-[FPC 1025] | [~5 KB][FPC 1025 Template Size]
-
-### Determining Hardware {#chromeos-config-fingerprint}
-
-If you have access to a shell on your Chromebook, you can use [Chrome OS Config]
-to determine the FPMCU that it contains:
-
-```bash
-(dut) $ cros_config /fingerprint board
-```
-
-Alternatively, if you have a Chromium OS build, you can use [Chrome OS Config]
-in the chroot to determine the FPMCU:
-
-```bash
-(chroot) $  cros_config_host -c /build/<BOARD>/usr/share/chromeos-config/yaml/config.yaml -m <MODEL> get /fingerprint board
-```
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: If you get an empty response when running these commands, the
-[Chrome OS Config] properties for fingerprint may not have been set up yet. See
-the [section on updating Chrome OS Config](#update-chromeos-config).
-***
-<!-- mdformat on -->
-
-## Building FPMCU Firmware Locally
-
-### See `Makefile` target options
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make help
-```
-
-### Build
-
-Replace `<BOARD_NAME>` in the command below with the fingerprint MCU that you
-are targeting (e.g., `nocturne_fp`, `dartmonkey`, `bloonchipper`).
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make BOARD=<BOARD_NAME> -j
-```
-
-### Verbose Build output
-
-Use `V=1` to see the complete compiler output (all flags).
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make V=1 BOARD=nocturne_fp -j
-```
-
-## Building all EC firmware (before "repo upload")
-
-Before uploading a change to Gerrit via `repo upload`, you'll need to build
-*all* the boards in the EC codebase to make sure your changes do not break any
-others.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-NOTE: If you forget to do this, do not worry. `repo upload` will warn you and
-prevent you from uploading.
-***
-<!-- mdformat on -->
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make buildall -j
-```
-
-## Building and running unit tests
-
-See the [Unit Tests] documentation for details on how to [run the unit tests].
-
-## Build ectool
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make BOARD=nocturne_fp utils-host -j
-```
-
-## Build and run the `host_command` fuzz test
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make run-host_command_fuzz
-```
-
-## Logs
-
-[`timberslide`] is a simple daemon that collects logs from the FPMCU and writes
-them to disk. [`timberslide`] reads from sysfs, where the kernel driver
-[periodically dumps the FPMCU console output][cros_ec_debugfs]. [`timberslide`]
-writes the resulting logs to `/var/log/cros_fp.log`. There are multiple
-instances of [`timberslide`] that run; one for each MCU running the EC codebase.
-
-### Starting timberslide
-
-```bash
-(dut)$ start timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
-```
-
-### Stopping timberslide
-
-```bash
-(dut)$ stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
-```
-
-### Manually running timberslide
-
-```bash
-(dut)$ timberslide --device_log=/sys/kernel/debug/cros_fp/console_log
-```
-
-### Reading logs from kernel
-
-If [`timberslide`] is not running you can just `cat` the logs directly from the
-kernel:
-
-```bash
-(dut)$ cat /sys/kernel/debug/cros_fp/console_log
-```
-
-## Production Updates (Auto-Update)
-
-### `fp_updater.sh` and `bio_fw_updater`
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: The auto-update process requires a working version of the firmware
-running on the FPMCU. See [Fingerprint Factory Requirements] for details on
-flashing in the factory.
-***
-<!-- mdformat on -->
-
-[`fp_updater.sh`] and [`bio_fw_updater`] are wrappers around [`flashrom`] and
-require already-functioning RO firmware running on the FPMCU. It’s meant to be
-used in production to update the RW firmware. `fp_updater.sh` was used prior to
-M77; `bio_fw_updater` replaces it.
-
-It's also possible to use the updater to update the RO firmware if you disable
-*both* HW and SW write protect, which we use for updating development devices
-that do not have write protect enabled (dogfood devices, EVT, etc.)
-
-In production, only the RW portion of the firmware can be updated (unless the
-user disables [hardware write protection]).
-
-## Factory / RMA / Development Updates {#factory-rma-dev-updates}
-
-### `flash_fp_mcu`
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: This tool is really just for us to use during development or during
-the RMA flow (must go through finalization again in that case). We never update
-RO in the field (can’t by design). See [Fingerprint Factory Requirements] for
-details on flashing in the factory.
-***
-<!-- mdformat on -->
-
-[`flash_fp_mcu`] enables spidev and toggles some GPIOs to put the FPMCU (STM32)
-into bootloader mode. At that point it uses [`stm32mon`] to rewrite the entire
-flash (both RO and RW). The FPMCU can only be put into bootloader mode when
-[hardware write protection] is disabled, which means [`flash_fp_mcu`] can only
-be used when [hardware write protection] is disabled.
-
-[`flash_fp_mcu`] is available in the [Chromium OS test image].
-
-### `stm32mon`
-
-[`stm32mon`] is a tool used to send commands to the STM32 bootloader. We use it
-for development (through [`flash_fp_mcu`]) to erase and flash the entire chip.
-
-[`stm32mon`] is available in the [Chromium OS test image].
-
-## Keys
-
-The `RO` section of the fingerprint firmware contains the public portion of the
-key used to sign the RW firmware. The RO firmware uses the public key to
-validate the signature of the RW firmware before jumping to it. It is not
-possible to update the public key stored in the RO firmware once a device has
-been shipped (i.e., once [hardware write protection] is enabled).
-
-Different keys are used to sign the firmware during development and production.
-The `dev` key is used for local builds and development and is not private; it is
-called `dev_key.pem` and located in the "board" directory for the given FPMCU
-(e.g., [`board/nocturne_fp/dev_key.pem`]). After doing a build, the `ec.bin` in
-the `build` directory (e.g., `build/nocturne_fp/ec.bin`) will be signed with the
-`dev` key.
-
-The two other types of keys are `premp` and `mp`, which stand for "pre-mass
-production" and "mass production", respectively. Both the `premp` and `mp` keys
-are only available to the buildbots as part of the official build. The `premp`
-is typically used during bringup of new hardware to validate the signing flow of
-the buildbots, while the `mp` key is used for PVT and production devices.
-
-Switching keys is only possible when the `RO` firmware is not write protected,
-since the public portion of the keypair is stored in the `RO` firmware.
-
-### Generate Key
-
-For testing, you can generate a new key by using the following openssl command:
-
-```bash
-openssl genrsa -3 -out board/$BOARD/dev_key.pem 3072
-```
-
-### Resources
-
-*   https://sites.google.com/a/google.com/chromeos/resources/engineering/releng/signer-documentation
-*   https://sites.google.com/a/google.com/chromeos/paygen---payload
-*   https://b.corp.google.com/issues/77882970
-
-## Signing
-
-[`futility`] is used to sign EC firmware. There’s a wrapper script around it for
-signing called [`sign_official_build.sh`].
-
-### Key ID
-
-The output of `futility show` will show a `Public Key File` and `Signature`
-section, each of which have an `ID` field. This ID lets you match the key to the
-signature in case there is more than one.
-[It’s just a sha1sum of the public key,][vboot_key_id] so it lets you
-[uniquely identify the key being used][vb2_public_key].
-
-If you have the key (e.g., in PEM format), you can compute the `ID` with the
-`futility show` command:
-
-```bash
-(chroot) $ futility show ./path/to/key.pem
-```
-
-#### Example
-
-If you are building the `hatch_fp` "board" on your local machine (which signs
-the resulting `ec.bin` with the `dev` key, you can check the `ID` with:
-
-```bash
-(chroot)$ futility show board/hatch_fp/dev_key.pem
-```
-
-```
-Private Key file:      board/hatch_fp/dev_key.pem
-  Key length:          3072
-  Key sha1sum:         61382804da86b4156d666cc9a976088f8b647d44
-```
-
-```bash
-(chroot)$ futility show build/hatch_fp/ec.bin
-```
-
-```
-Public Key file:       build/hatch_fp/ec.bin
-  Vboot API:           2.1
-  Desc:                ""
-  Signature Algorithm: 7 RSA3072EXP3
-  Hash Algorithm:      2 SHA256
-  Version:             0x00000001
-  ID:                  61382804da86b4156d666cc9a976088f8b647d44
-Signature:             build/hatch_fp/ec.bin
-  Vboot API:           2.1
-  Desc:                ""
-  Signature Algorithm: 7 RSA3072EXP3
-  Hash Algorithm:      2 SHA256
-  Total size:          0x1b8 (440)
-  ID:                  61382804da86b4156d666cc9a976088f8b647d44
-  Data size:           0x2864c (165452)
-Signature verification succeeded.
-```
-
-### Showing Key ID (fingerprint) for running FW
-
-[Asked on chromeos-chatty-firmware][chatty-firmware-q] about adding an EC
-command to show the Key ID (fingerprint) from the RO version. This would make it
-a lot easier during both development and testing.
-
-## Power
-
-See [Measuring Power] for instructions on how to measure power with the
-fingerprint development boards.
-
-### Dragonclaw v0.2
-
-```bash
-(chroot) $ dut-control -t 60 pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
-```
-
-**Firmware Version**:
-`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.7314-3dfc5ff6-RW.bin`
-
-#### MCU is idle
-
-```
-(chroot) $ dut-control fpmcu_slp_alt:off
-```
-
-```
-@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    113   533.56   40.91   658.52   447.06
-@@    pp1800_dx_fp_mv    113  1800.00    0.00  1800.00  1800.00
-@@    pp1800_dx_fp_mw    113     0.00    0.00     0.00     0.00
-@@    pp3300_dx_fp_mv    113  3280.00    0.00  3280.00  3280.00
-@@    pp3300_dx_fp_mw    113     0.01    0.05     0.26     0.00
-@@   pp3300_dx_mcu_mv    113  3280.00    0.00  3280.00  3280.00
-@@   pp3300_dx_mcu_mw    113    24.67    0.00    24.67    24.67
-```
-
-#### MCU in low power mode (suspend)
-
-```
-(chroot) $ dut-control fpmcu_slp_alt:on
-```
-
-```
-@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    115   526.56   36.79   607.60   426.58
-@@    pp1800_dx_fp_mv    115  1800.00    0.00  1800.00  1800.00
-@@    pp1800_dx_fp_mw    115     0.00    0.00     0.00     0.00
-@@    pp3300_dx_fp_mv    115  3287.30    2.25  3288.00  3280.00
-@@    pp3300_dx_fp_mw    115     0.00    0.02     0.26     0.00
-@@   pp3300_dx_mcu_mv    115  3280.97    2.62  3288.00  3280.00
-@@   pp3300_dx_mcu_mw    115     4.02    0.64    10.76     3.94
-```
-
-### Icetower v0.1
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: Icetower v0.1 has a hardware bug in the INA connections, so you cannot
-measure the 1.8V fingerprint sensor rail. See http://b/178098140.
-
-Additionally, before https://crrev.com/c/2689101, the sleep GPIOs were not
-configured correctly, so the change needs to be cherry-picked in order to
-measure releases before that point.
-***
-<!-- mdformat on -->
-
-```bash
-(chroot) $ dut-control -t 60 pp3300_dx_mcu_mv pp3300_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw
-```
-
-**Firmware Version**:
-`dartmonkey_v2.0.2887-311310808-RO_v2.0.7304-441100b93-RW.bin`
-
-#### MCU is idle
-
-```
-(chroot) $ dut-control fpmcu_slp_alt:off
-```
-
-```
-@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    178   337.13   20.91   404.32   289.82
-@@    pp3300_dx_fp_mv    178  3256.00    0.00  3256.00  3256.00
-@@    pp3300_dx_fp_mw    178     0.00    0.00     0.00     0.00
-@@   pp3300_dx_mcu_mv    178  3248.00    0.00  3248.00  3248.00
-@@   pp3300_dx_mcu_mw    178    45.17    0.09    45.21    44.95
-```
-
-#### MCU in low power mode (suspend)
-
-```
-(chroot) $ dut-control fpmcu_slp_alt:on
-```
-
-```
-@@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    174   345.60   31.93   457.62   283.00
-@@    pp3300_dx_fp_mv    174  3264.00    0.00  3264.00  3264.00
-@@    pp3300_dx_fp_mw    174     0.00    0.00     0.00     0.00
-@@   pp3300_dx_mcu_mv    174  3260.69    3.94  3264.00  3256.00
-@@   pp3300_dx_mcu_mw    174     5.47    0.10     5.48     4.17
-```
-
-## Chrome OS Build (portage / ebuild)
-
-In order to use the fingerprint sensor with a given [Chrome OS board], a few
-things need to be configured for the [Chrome OS board].
-
-### Enable biod USE flag
-
-The biod [`USE` flag] needs to be enabled for the [Chrome OS board]. This `USE`
-flag
-[determines whether the `biod` daemon is built and installed][biod chromium-os].
-
-To enable the `USE` flag, update the `make.defaults` for the [Chrome OS board].
-See the [`make.defaults` for the Hatch board][hatch make.defaults] as an
-example.
-
-#### Verifying biod is installed in the rootfs
-
-After enabling the `biod` [`USE` flag] and building the `biod` package for your
-target [Chrome OS board], the `biod` binary should be in the build directory:
-
-```bash
-(chroot) $ emerge-<BOARD> biod
-```
-
-```bash
-(chroot) $ ls /build/<BOARD>/usr/bin/biod
-/build/<BOARD>/usr/bin/biod
-```
-
-### Update FPMCU_FIRMWARE
-
-`FPMCU_FIRMWARE` should be set to the set of fingerprint firmware that should be
-built and installed for the [Chrome OS board].
-
-`FPMCU_FIRMWARE` is a [`USE_EXPAND` variable][`USE` flag],
-[defined in the base `make.defaults`][FPMCU_FIRMWARE make.defaults].
-
-The `biod` ebuild uses the resulting [`USE` flags] to
-[determine which FPMCU release firmware to build][biod release firmware] and the
-[`chromeos-firmware-fpmcu` ebuild] uses the resulting [`USE` flags] to
-[determine which firmware to install][firmware ebuild] to the rootfs in
-`/opt/google/biod/fw`.
-
-Possible values for `FPMCU_FIRMWARE` can be found by looking at the
-`FIRMWARE_EC_BOARD` values in the [`chromeos-fpmcu-release*` ebuilds], which
-correspond to the [FPMCU hardware](#hardware).
-
-See the [Hatch baseboard `make.defaults`] for an example.
-
-#### Verifying FPMCU firmware is installed in the rootfs
-
-Once you have added the `FPMCU_FIRMWARE` flag and rebuilt the
-[`chromeos-firmware-fpmcu` ebuild], the firmware will show up in the the chroot:
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**NOTE**: This requires access to the [internal manifest].
-***
-<!-- mdformat on -->
-
-```bash
-(chroot) $ emerge-<BOARD> chromeos-firmware-fpmcu
-```
-
-```bash
-(chroot) $ ls /build/<BOARD>/opt/google/biod/fw
-bloonchipper_v2.0.2626-3c315108.bin  dartmonkey_v2.0.2887-311310808.bin
-```
-
-The above output assumes you selected the `bloonchipper` and `dartmonkey`
-firmware by setting `FPMCU_FIRMWARE="bloonchipper dartmonkey"`. The actual
-version numbers displayed will not necessarily match since the firmware is
-constantly updated.
-
-### Update Chrome OS Config {#update-chromeos-config}
-
-With "unibuild", the same OS image (build) for a given [Chrome OS board] is used
-across multiple devices. Often there will be some devices that have a
-fingerprint sensor, some that do not, and even different sensors for the same
-board.
-
-Determining what fingerprint hardware is on a given [Chrome OS board] is thus
-done at runtime, using [Chrome OS Config].
-
-The `fingerprint` config needs to be in the `model.yaml` for the given
-[Chrome OS board]. The [Chrome OS Config fingerprint] section describes the
-attributes for the `fingerprint` config in more detail.
-
-The [`ec_extras` attribute] needs to be set to the list of fingerprint firmware
-that should be built as part of the build.
-
-See the [`model.yaml` for the Hatch board][hatch model.yaml] as an example.
-
-Instead of crafting the `model.yaml` by hand, newer boards are moving to the
-[Chrome OS Project Configuration] model, where the config is generated using
-[Starlark]. The common [`create_fingerprint`] function can be used across models
-to configure the fingerprint settings. See the [Morphius `config.star`] for an
-example of how to call `create_fingerprint`. After you modify a `config.star`
-file you will need to [regenerate the config]. If you need to change many
-projects (e.g., modifying [`create_fingerprint`]), you can use the [`CLFactory`]
-tool.
-
-Once you have updated the config, you can test your changes by
-[running `cros_config`](#chromeos-config-fingerprint). The Chrome OS Config
-documentation has a [section on testing properties] that describes this in more
-detail.
-
-### SKUs
-
-The fingerprint sensor may only be included on certain SKUs for a given device.
-The fingerprint code uses [Chrome OS Config] to determine whether a device has a
-fingerprint sensor or not. For each SKU, there is an associated
-[fingerprint config][Chrome OS Config fingerprint]. [Chrome OS Config]
-determines the [SKU information][Chrome OS Config SKU] (and thus the
-[fingerprint config][Chrome OS Config fingerprint]) from [CBI Info]. The SKU for
-a given device can be found by viewing `chrome://system/#platform_identity_sku`.
-
-[`common/fpsensor`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/common/fpsensor/
-[`driver/fingerprint`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/driver/fingerprint
-[`nocturne_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nocturne_fp/
-[`nami_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nami_fp/
-[`hatch_fp`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/hatch_fp/
-[`bloonchipper`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/bloonchipper/
-[`dartmonkey`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/dartmonkey/
-[hardware write protection]: ../write_protection.md
-[`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_fp_mcu
-[`stm32mon`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/e1f3f89e7ea7945adddd0c2e6838f5e59856cff2/util/stm32mon.c#14
-[`futility`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/HEAD/futility/
-[`sign_official_build.sh`]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/HEAD/scripts/image_signing/sign_official_build.sh
-[vboot_key_id]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/e7db36856ce418552637d1981c173d22dfe5bf39/firmware/2lib/include/2id.h#5
-[vb2_public_key]: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/e7db36856ce418552637d1981c173d22dfe5bf39/firmware/2lib/include/2rsa.h#14
-[chatty-firmware-q]: https://groups.google.com/a/google.com/d/msg/chromeos-chatty-firmware/ZSg423wsFPg/26UbdGwjFQAJ
-[`fp_updater.sh`]: http://go/cros-fp-updater-nocturne-source
-[`bio_fw_updater`]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/biod/tools
-[`flashrom`]: https://chromium.googlesource.com/chromiumos/third_party/flashrom/
-[STM32F412]: https://www.st.com/resource/en/reference_manual/dm00180369.pdf
-[STM32H743]: https://www.st.com/resource/en/reference_manual/dm00314099.pdf
-[`board/nocturne_fp/dev_key.pem`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/nocturne_fp/dev_key.pem
-[`timberslide`]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/timberslide
-[cros_ec_debugfs]: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9db44685934a2e4bc9180ea2de87a6c429672395/drivers/platform/chrome/cros_ec_debugfs.c
-[Fingerprint Factory Requirements]: ./fingerprint-factory-requirements.md
-[Chromium OS test image]: https://chromium.googlesource.com/chromiumos/platform/factory/+/HEAD/README.md#building-test-image
-[Chrome OS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md
-[Chrome OS Config fingerprint]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#fingerprint
-[section on testing properties]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#adding-and-testing-new-properties
-[Chrome OS board]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#Select-a-board
-[biod chromium-os]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/virtual/target-chromium-os/target-chromium-os-1.ebuild#154
-[hatch make.defaults]: https://chromium.googlesource.com/chromiumos/overlays/board-overlays/+/2f075f0e7ce09d3eb460f3c529da463a6201276c/overlay-hatch/profiles/base/make.defaults#22
-[Hatch baseboard `make.defaults`]: https://chrome-internal.googlesource.com/chromeos/overlays/baseboard-hatch-private/+/HEAD/profiles/base/make.defaults#17
-[hatch model.yaml]: https://chrome-internal.googlesource.com/chromeos/overlays/overlay-hatch-private/+/HEAD/chromeos-base/chromeos-config-bsp-hatch-private/files/model.yaml
-[`ec_extras` attribute]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#build_targets
-[FPMCU_FIRMWARE make.defaults]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/profiles/base/make.defaults#157
-[`USE` flag]: https://devmanual.gentoo.org/general-concepts/use-flags/index.html
-[`USE` flags]: https://devmanual.gentoo.org/general-concepts/use-flags/index.html
-[biod release firmware]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/4ea72b588af3394cb9fd1c330dcf726472183dfd/chromeos-base/biod/biod-9999.ebuild#49
-[`chromeos-firmware-fpmcu` ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/HEAD/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild
-[firmware ebuild]: https://chrome-internal.googlesource.com/chromeos/overlays/chromeos-overlay/+/HEAD/chromeos-base/chromeos-firmware-fpmcu/chromeos-firmware-fpmcu-9999.ebuild#40
-[`chromeos-fpmcu-release*` ebuilds]: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/HEAD/sys-firmware
-[internal manifest]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md#get-the-source-code
-[Unit Tests]: ../unit_tests.md
-[run the unit tests]: ../unit_tests.md#running
-[Measuring Power]: ./fingerprint-dev-for-partners.md#measure-power
-[dragonclaw]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
-[FPC 1145]: ../../driver/fingerprint/fpc/libfp/fpc1145_private.h
-[FPC 1025]: ../../driver/fingerprint/fpc/bep/fpc1025_private.h
-[FPC 1145 Template Size]: https://chromium.googlesource.com/chromiumos/platform/ec/+/127521b109be8aac352e80e319e46ed123360408/driver/fingerprint/fpc/libfp/fpc1145_private.h#46
-[FPC 1025 Template Size]: https://chromium.googlesource.com/chromiumos/platform/ec/+/127521b109be8aac352e80e319e46ed123360408/driver/fingerprint/fpc/bep/fpc1025_private.h#44
-[Dragonclaw v0.2]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
-[Icetower v0.2]: ./fingerprint-dev-for-partners.md#fpmcu-dev-board
-[Nucleo F412ZG]: https://www.digikey.com/en/products/detail/stmicroelectronics/NUCLEO-F412ZG/6137573
-[Nucleo H743ZI2]: https://www.digikey.com/en/products/detail/stmicroelectronics/NUCLEO-H743ZI2/10130892
-[CBI Info]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
-[Chrome OS Config SKU]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md#identity
-[Chrome OS Project Configuration]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md
-[Starlark]: https://docs.bazel.build/versions/master/skylark/language.html
-[`create_fingerprint`]: https://chromium.googlesource.com/chromiumos/config/+/e1fa0d7f56eb3dd6e9378e4326de086ada46b7d3/util/hw_topology.star#444
-[Morphius `config.star`]: https://chrome-internal.googlesource.com/chromeos/project/zork/morphius/+/593b657a776ed6b320c826916adc9cd845faf709/config.star#85
-[regenerate the config]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md#making-configuration-changes-for-your-project
-[`CLFactory`]: https://chromium.googlesource.com/chromiumos/config/+/HEAD/README.md#making-bulk-changes-across-repos
diff --git a/docs/getting_started_quickly.md b/docs/getting_started_quickly.md
deleted file mode 100644
index 325bef39b0..0000000000
--- a/docs/getting_started_quickly.md
+++ /dev/null
@@ -1,125 +0,0 @@
-# Get Started Building EC Images (Quickly)
-
-[TOC]
-
-The
-[Chromium OS Developer Guide](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_guide.md)
-and [README](../README.md) walk through the steps needed to fetch and build
-Chromium OS source. These steps can be followed to retrieve and build EC source
-as well. On the other hand, if your sole interest is building an EC image, the
-general developer guide contains some extra unneeded steps.
-
-The fastest possible way to build an EC image is to skip the Chromium OS chroot
-install entirely. The following steps have been tested on an Ubuntu 15.10 (Wily
-Werewolf) 64-bit host machine. Other distros / versions may be used, but
-toolchain incompatibilities may require extra debug.
-
-## Building
-
-1.  Install build / dev tools:
-
-    ```bash
-    sudo apt-get install git libftdi-dev libusb-dev libncurses5-dev gcc-arm-none-eabi
-    ```
-
-1.  Sync the cros-ec git repo:
-
-    ```bash
-    git clone https://chromium.googlesource.com/chromiumos/platform/ec
-    ```
-
-1.  Build your EC image:
-
-    ```bash
-    HOSTCC=x86_64-linux-gnu-gcc CROSS_COMPILE_arm=arm-none-eabi- make BOARD=${BOARD}
-    ```
-
-    Note: the EC supports multiple architectures, check `core/*/build.mk` files
-    for other supported `CROSS_COMPILE_` variables.
-
-## External Dependencies
-
-Most boards are buildable, but some will fail due to dependencies on external
-binaries (such as [`futility`](#building-futility)). Also, some related tools
-(such as `flash_ec` and `servod`) must be run from the Chromium OS chroot. Here
-is a set of steps to setup a minimal development environment to build EC images
-from the Chromium OS chroot:
-
-1.  Create a folder for your chroot:
-
-    ```bash
-    mkdir cros-src; cd cros-src
-    ```
-
-1.  Run
-
-    ```bash
-    repo init -u https://chromium.googlesource.com/chromiumos/manifest -g minilayout,firmware
-    ```
-
-1.  Run `repo sync`:
-
-    ```bash
-    repo sync -j <number of cores on your workstatsion>
-    ```
-
-1.  Enter the chroot and enter your password for `sudo` if prompted:
-
-    ```bash
-    ./chromite/bin/cros_sdk
-    ```
-
-1.  Set up your board:
-
-    ```bash
-    setup_board --board=${BOARD}
-    ```
-
-    (ex. `setup_board --board=glados`)
-
-1.  Build EC:
-
-    ```bash
-    ./build_packages --board=${BOARD} chromeos-ec
-    ```
-
-1.  Now, EC images for any board can be built with:
-
-    ```bash
-    cd ~/trunk/src/platform/ec; make BOARD=${BOARD} -j
-    ```
-
-## Building `futility` outside the chroot {#building-futility}
-
-If you want to build the `futility` host tool outside the normal Chrome OS
-chroot self-contained environment, you can try the following
-
-1.  Install futility build dependencies:
-
-    ```bash
-    sudo apt-get install uuid-dev liblzma-dev libyaml-dev libssl-dev
-    ```
-
-1.  Get the vboot reference sources:
-
-    ```bash
-    git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference
-    ```
-
-1.  Build it:
-
-    ```bash
-    cd vboot_reference ; make
-    ```
-
-1.  Install it in `/usr/local/bin`:
-
-    ```bash
-    sudo make install
-    ```
-
-1.  Add `/usr/local/bin` to your default `PATH`:
-
-    ```bash
-    export PATH="${PATH}:/usr/local/bin"
-    ```
diff --git a/docs/hammer.md b/docs/hammer.md
deleted file mode 100644
index 6048f1c441..0000000000
--- a/docs/hammer.md
+++ /dev/null
@@ -1,199 +0,0 @@
-# Hammer care and feeding
-
-Original: [go/hammercare](http://go/hammercare)
-
-Last updated: 2021-03-18
-
-[TOC]
-
-## Servo
-
-### Start servod
-
-```
-cros_sdk --no-ns-pid
-sudo servod --port=9000 -b hammer -c hammer.xml
-```
-
-### UART console
-
-The simplest solution for most people is to use the `dut-console` script.
-
-First, add this line into your .bashrc (or other shell init script; needed once
-only):
-``` bash
-alias dut-console="~/chromiumos/src/platform/dev/contrib/dut-console"
-```
-
-Then simply run `dut-console -c ec`. `dut-console` uses `cu` under the hood, and
-works like ssh - to leave, press `<ENTER> <~> <.> <ENTER>`.
-
-
-``` bash
-src/platform/dev/contrib/dut-console -p 9000 -c ec
-```
-
-## Build EC
-
-(Inside chroot)
-``` bash
-cd ~/trunk/src/platform/ec
-make BOARD=<BOARD> -j
-```
-
-## Flash EC
-
-### Prerequisites
-
-#### Find the USB VID:PID of the device
-
-USB VID:PID is listed in [hammer/variants.h](../board/hammer/variants.h).
-Many scripts below requires correct PID to work.
-
-#### Stop hammerd
-
-Remove rootfs verification:
-``` bash
-/usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --force
-```
-
-Reboot the DUT then rename hammerd
-``` bash
-mv /usr/bin/hammerd /usr/bin/hammerd.bak
-```
-
-### Hammer connected to Chromebook, flash via USB
-
-(Inside chroot) Copy-paste the script below to a file named
-"flash_hammer.usbremote", run
-``` bash
-bash flash_hammer.usbremote <BOARD> <VID:PID> <IP> [ro]
-```
-
-``` bash
-#!/bin/bash
-# flash_hammer.usbremote
-set -x -e
-
-BOARD=$1
-ID=$2
-IP=$3
-EXTRA="-d $ID"
-
-ssh $IP sh -c "'rm -f /usr/local/ec.bin'"
-scp ~/trunk/src/platform/ec/build/${BOARD}/ec.bin $IP:/usr/local/ec.bin
-
-if [ "$4" = 'ro' ]; then
-   ssh $IP sh -x -c "'usb_updater2 $EXTRA -j;
-   sleep 1.0;
-   usb_updater2 $EXTRA /usr/local/ec.bin;
-   sleep 0.5;
-   usb_updater2 $EXTRA -s;
-   usb_updater2 $EXTRA /usr/local/ec.bin'"
-else
-   ssh $IP sh -x -c "'usb_updater2 $EXTRA -w;
-   usb_updater2 $EXTRA -r; sleep 0.5;
-   usb_updater2 $EXTRA -s;
-   usb_updater2 $EXTRA /usr/local/ec.bin'"
-fi
-```
-
-### Hammer connected to Chromebook, flash via servo
-
-(Inside chroot) Copy-paste the script below to a file named "flash_hammer",
-run `bash flash_hammer <IP> </path/to/ec.bin>`
-
-``` bash
-#!/bin/bash
-# Recommended to use a USB 3.0 Ethernet adapter for this to work, otherwise the
-# network on the DUT will temporarily go down when the root USB hub is taken
-# down.
-
-set -e
-IP=$1
-shift
-
-# USB 2.0 root hub
-USBID="usb1"
-
-set -x
-
-# unbind, then rebind, the root hub (in the mean time, we'll start programming)
-ssh $IP sh -c "'echo $USBID > /sys/bus/usb/drivers/usb/unbind; sleep 3; echo $USBID > /sys/bus/usb/drivers/usb/bind'" &
-
-util/flash_ec --board=hammer --port 9000 --image "$@"
-```
-
-### Hammer connected via servo only
-
-Do not connect hammer to Chromebook in this case, or at least make sure
-Chromebook is either suspended (S3) or off (when put into programming mode,
-STM32 always prefers USB interface when available)
-
-For Servo V2:
-
-``` bash
-dut-control -p 9000 spi1_vref:pp3300 spi1_buf_en:on spi1_buf_on_flex_en:on
-util/flash_ec --board=hammer --port=9000 [--image=/path/to/ec.bin]
-
-# To disable power from servo to Hammer
-dut-control -p 9000 spi1_vref:off spi1_buf_en:off spi1_buf_on_flex_en:off
-```
-
-For Servo Micro (there is only one buffer in the power delivery path,
-so don't include the spi1_buf_on_flex_en control):
-
-``` bash
-dut-control -p 9000 spi1_vref:pp3300 spi1_buf_en:on
-util/flash_ec --board=hammer --port=9000 [--image=/path/to/ec.bin]
-
-# To disable power from servo to Hammer
-dut-control -p 9000 spi1_vref:off spi1_buf_en:off
-```
-
-### Hammer connected via POGO-PIN-USB to Linux
-
-So this is very similar to Hammer connected to poppy, flash via USB, but you
-are directly running commands on the machine connected to Hammer, so you don’t
-need to SSH to it.
-
-``` bash
-#!/bin/bash
-# flash_hammer.usblocal
-
-EXTRA=
-EC=build/${BOARD:-hammer}/ec.bin
-UPDATER=usb_updater2
-
-if [ -n "$ID" ]; then
-   EXTRA="-d $ID"
-fi
-
-if [ "$1" = 'ro' ]; then
-   "${UPDATER}" $EXTRA -j;
-   sleep 1.0;
-   "${UPDATER}" $EXTRA "${EC}";
-   sleep 1.0;
-   "${UPDATER}" $EXTRA -s;
-   "${UPDATER}" $EXTRA "${EC}";
-else
-   "${UPDATER}" $EXTRA -w;
-   "${UPDATER}" $EXTRA -r;
-   sleep 1.0;
-   "${UPDATER}" $EXTRA -s;
-   "${UPDATER}" $EXTRA "${EC}";
-fi
-
-# To use this script: BOARD=<BOARD> ID=<VID:PID> ./flash_hammer.usblocal [ro]
-```
-
-## Update touchpad firmware
-
-(Inside DUT)
-``` bash
-usb_updater2 --tp_update <FILE> --device=<VID:PID>
-```
-or
-``` bash
-ec_touchpad_updater -p <PID> <FILE>
-```
diff --git a/docs/i2c-debugging.md b/docs/i2c-debugging.md
deleted file mode 100644
index 125e72b777..0000000000
--- a/docs/i2c-debugging.md
+++ /dev/null
@@ -1,51 +0,0 @@
-# I²C Debugging Tips
-
-The EC codebase has functionality to help you debug I²C errors without pulling
-out the scope. Some of the debug functionality is disabled by default to save
-space, but can be enabled with the `CONFIG_I2C_DEBUG` option.
-
-## Tracing
-
-You can use the `i2ctrace` command to monitor (ranges of) addresses:
-
-```
-i2ctrace [list
-        | disable <id>
-        | enable <port> <address>
-        | enable <port> <address-low> <address-high>]
-```
-
-For example:
-
-```
-> i2ctrace enable 0 0x10 0x30
-> i2ctrace enable 1 0x20
-> i2ctrace list
-id port address
--- ---- -------
-0     0 0x10 to 0x30
-1     1 0x40 to 0x50
-... debug spam may follow ...
-i2c: 1:0x20 wr 0x10   rd 0x01 0x00
-i2c: 1:0x20 wr 0x10 0x01 0x00
-...
-> i2ctrace disable 1
-> i2ctrace list
-id port address
--- ---- -------
-0     0 0x10 to 0x30
-```
-
-A maximum of 8 debug entries are supported at a single time.
-
-Note that `i2ctrace enable` will merge debug entries when possible:
-
-```
-> i2ctrace enable 0 0x10 0x30
-> i2ctrace enable 0 0x40 0x50
-> i2ctrace enable 0 0x31 0x3f
-> i2ctrace list
-id port address
--- ---- -------
-0     0 0x10 to 0x50
-```
diff --git a/docs/ide-support.md b/docs/ide-support.md
deleted file mode 100644
index cec196be58..0000000000
--- a/docs/ide-support.md
+++ /dev/null
@@ -1,57 +0,0 @@
-# IDE Support
-
-[TOC]
-
-## Odd File Types
-
-EC uses a few odd file types/names. Some are included from other header files
-and used to generate data structures, thus it is important for your IDE to index
-them.
-
-Patterns                                              | Vague Type
------------------------------------------------------ | ----------
-`README.*`                                            | Text
-`Makefile.rules`, `Makefile.toolchain`                | Makefile
-`gpio.wrap`                                           | C Header
-`gpio.inc`                                            | C Header
-`*.tasklist`, `*.irqlist`, `*.mocklist`, `*.testlist` | C Header
-
-## IDE Configuration Primitives
-
-Due to the way most EC code has been structured, you can typically only safely
-inspect a configuration for a single image (RO or RW) for a single board. Thus,
-you need to specify the specific board/image pair when requesting defines and
-includes.
-
-Command                                      | Description
--------------------------------------------- | ------------------------------
-`make print-defines BOARD=$BOARD BLD=RW/RO`  | List compiler injected defines
-`make print-includes BOARD=$BOARD BLD=RW/RO` | List compiler include paths
-
-## VSCode
-
-You can use the `ide-config.sh` tool to generate a VSCode configuration that
-includes selectable sub-configurations for every board/image pair.
-
-1.  From the root `ec` directory, do the following:
-
-    ```bash
-    mkdir -p .vscode
-    ./util/ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
-    ```
-
-2.  Open VSCode and navigate to some C source file.
-
-3.  Run `C/C++ Reset IntelliSense Database` from the `Ctrl-Shift-P` menu
-
-4.  Select the config in the bottom right, next to the `Select Language Mode`.
-    You will only see this option when a C/C++ file is open. Additionally, you
-    can select a configuration by pressing `Ctrl-Shift-P` and selecting the
-    `C/C++ Select a Configuration...` option.
-
-5.  Add the EC specific file associations and style settings. Do the following
-    to copy the default settings to `.vscode/settings.json`:
-
-    ```bash
-    cp .vscode/settings.json.default .vscode/settings.json
-    ```
diff --git a/docs/images/CQ_Prototype_Environment.jpg b/docs/images/CQ_Prototype_Environment.jpg
deleted file mode 100644
index 77b39d9470..0000000000
--- a/docs/images/CQ_Prototype_Environment.jpg
+++ /dev/null
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deleted file mode 100644
index 7068829e31..0000000000
--- a/docs/images/TCPMv2-ExampleStates.png
+++ /dev/null
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deleted file mode 100644
index da88a143a8..0000000000
--- a/docs/images/TCPMv2-ExampleTransitions.png
+++ /dev/null
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deleted file mode 100644
index 7429e8f9b1..0000000000
--- a/docs/images/TCPMv2-TaskLayers.png
+++ /dev/null
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deleted file mode 100644
index 1c0bb218fe..0000000000
--- a/docs/images/TCPMv2-TaskLoop.png
+++ /dev/null
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deleted file mode 100644
index b2fcdb51e1..0000000000
--- a/docs/images/alternate_example.png
+++ /dev/null
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deleted file mode 100644
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--- a/docs/images/cros_fingerprint_architecture_diagram.png
+++ /dev/null
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deleted file mode 100644
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--- a/docs/images/cros_fingerprint_decryption_flowchart.png
+++ /dev/null
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-# Configuring the EC for Low-Battery Startup
-
-Near the bottom of charge, starting up a ChromeOS device can be a tricky
-proposition. Several features interact to make it difficult to reliably turn on
-the machine without browning out. Over the years, a variety of configuration
-options have been written to maximize ChromeOS's compatibility with the basic
-user expectation,
-
-"I plugged it in, therefore it should turn on."
-
-When creating a new board configuration, this document should aid the engineer
-in navigating and choosing correct values for these options.
-
-The first section describes the various features which interact with each other
-to create a complex environment for the EC during boot, especially at a low
-state of charge.
-
-Second, we'll provide some reference configurations which cover many
-Chromebooks' use cases.
-
-Finally, we'll close out with a detailed review of the configuration parameters
-which are available.
-
-## Interacting Features
-
-### Battery and Charging Circuit
-
-For the most part, ChromeOS device power systems are much like other laptop
-battery power systems. A variable-voltage rail is connected to the battery via a
-series of cutoff MOSFETs. Several system power rails derive their power from the
-system's variable-voltage rail. Mains power is delivered to the variable-voltage
-system rail by a buck/boost charging circuit. Mains power is itself rectified,
-isolated, and stepped down by an external power supply.
-
-During most of the battery charge, the charger operates in current mode, acting
-as a constant current source that delivers current to the variable-voltage rail.
-Load transients are served by the capacitance on the rail and the battery. By
-superposition, load transients during the charge don't necessarily draw current
-from the battery, they may just reduce the current flow into the battery.
-
-References to AC power in the EC codebase are actually references to an external
-power supply's DC source. External supplies that are actually USB-PD-speaking
-battery packs are indistinguishable from AC/DC adapters as far as the EC is
-concerned. Variables and functions which refer to external supplies all refer to
-them as 'AC', though.
-
-### Source Current Negotiation
-
-A device may draw power from an AC adapter via a few methods.
-
-#### USB BC1.2 Current Sources
-
-BC1.2 negotiation is usually managed entirely by an external IC. Once it is
-complete, the EC limits itself to 2.4A max. Additionally, the charger may be
-configured to switch to an input voltage regulation mode if the input voltage
-begins to sag too low.
-
-Ideally, the input source provides a voltage droop, such that it is not quite
-overloaded at the input voltage regulation setpoint of about 4.5V. Thus, 4.5V
-serves as a reasonable reference voltage for the charger to use when it is in an
-input voltage-regulation mode.
-
-In effect, the EC limits to both a maximum current of 2.4A and minimum voltage
-of 4.5V, for about 12W of power draw from a BC1.2 source.
-
-See also `driver/bc12/max14637.c:bc12_detect()`.
-
-#### USB-PD Sources
-
-High-current power supplies are negotiated via the USB Type C Current Source and
-USB Power Delivery specifications (PD). PD sources must support Type-C Current
-Source, but the reverse is not true. Both types of current sources are managed
-via the PD protocol module in the EC codebase.
-
-Type-C Current Source capabilities of up to 15W (3A, 5V) are advertised via
-analog signaling alone. Via digital communication in the PD protocol, much
-higher power states may be negotiated. However, higher power states also usually
-run at a higher voltage state as well. Any time the voltage level is changing,
-the power sink (the ChromeOS device) must lower its power consumption during the
-transient. The standby current level is governed by
-`CONFIG_CHARGER_INPUT_CURRENT`.
-
-PD port partners are capable of both soft and hard resets. Hard resets will
-cause a dead-bus state for a brief interval before PD can renegotiate, from
-scratch, because it is intended to emulate a cable disconnect. Therefore, a hard
-reset without a connected battery will brownout the Chromebook.
-
-### Locked and Unlocked Firmware
-
-The Verified Boot implementation normally limits the complexity of the code
-which executes in the locked Read-Only firmware package. The consequences for
-the EC are:
-
--   Locked RO EC firmware does not process any digital PD messages at all, it
-    only recognizes the analog advertisement of USB Current Source (15W max).
--   Installation of user-provided firmware is supported, but the write-protect
-    pin must be cleared to enable it.
--   On recent systems, write-protect is cleared by removing the system battery.
-
-### ChromeOS `powerd`
-
-The power management daemon provided by ChromeOS displays a "low-power charger"
-warning message via the system tray whenever the charger is limited to less than
-20W. Therefore, if a USB-PD source is restricted to analog signaling, or a BC1.2
-source is connected, the user gets alerted to the situation.
-
-Systems that can run on very little power may be rapidly charged with a 15W
-charger, while a high power system may require a 40W state or more for a decent
-battery charging user experience. Therefore, a board's overlay may override the
-warning threshold by replacing `/usr/share/power_manager/usb_min_ac_watts` in
-the board's filesystem.
-
-See also `platform2/power_manager/` source code.
-
-### Cell Imbalance
-
-Under normal conditions, the battery pack is equipped with a management IC which
-is solely responsible for the safety of the battery, measurement of the state of
-charge, and the balance of its cells. Examples include (but are not limited to)
-the TI BQ40Z50 and Renesas RAJ240.
-
-However, after very long periods of rest without a battery charging cycle, the
-natural self-discharge rate of each cell will cause them to diverge somewhat
-from each other.
-
-Some IC's can be configured to report a pack total state of charge of zero if
-any one cell's voltage is below a certain threshold. However, many do not.
-Therefore, after an extended rest period, one cell can be very close to the cell
-undervoltage cutoff threshold, even though the pack as a whole is considered to
-be at 3% charge or more.
-
-### Power Profile During Boot
-
-The power profile during the boot sequence is substantially different than that
-seen during typical use. Dynamic voltage and frequency scaling of the AP is
-partially governed by the temperature of the processor core. As the processor
-gets hotter, it will reduce its maximum core voltage and frequency to settle out
-at some maximum design junction temperature for the core. For passively cooled
-devices, the profile may also be chosen to limit the external case temperature.
-
-At startup, the case and core are cold. The bootloaders and kernel are also
-optimized to boot as fast as possible for a responsive user experience. So, the
-power drawn during the boot is much higher than that seen during typical
-productivity and entertainment tasks.
-
-### Depthcharge Power Verification
-
-After verification and optional update of the EC's RW firwmare, Depthcharge will
-poll the EC to verify that it is allowed to proceed to boot to the kernel.
-
-It does this by polling via the: - `EC_CMD_CHARGE_STATE` host command. -
-`CHARGE_STATE_CMD_GET_PARAM` subcommand. - `CS_PARAM_LIMIT_POWER` parameter.
-
-When the EC returns 0, power draw by the AP is unlimited and depthcharge resumes
-the boot. If the EC fails to return 0 in three seconds, depthcharge shuts down.
-
-See also vb2ex_ec_vboot_done() in Depthcharge, and option
-`CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW` in the EC. By default, this option is
-not set, and the EC immediately allows the boot to proceed.
-
-## Example Low-Battery Boot Sequences and Configurations
-
-Most ChromeOS devices power needs will be met by one of the following templates.
-
-### Low-Power Device
-
-Low-power devices require 15W or less of power to boot the AP. The battery pack
-is robust enough to support the device during brief intervals of PD negotiation
-without browning out.
-
-```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
-```
-
-A detailed boot sequence under this configuration, with a low battery and
-available AC power via a USB-PD charger:
-
-1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1.  RO firmware negotiates a 15W state via Current Source analog signaling and
-    begins charging the battery with it.
-1.  RO firmware verifies conditions to begin booting the AP:
-    -   Battery state of charge > 1%
-    -   OR charger power greater or equal to 15W (met by Current Source analog
-        signaling).
-1.  AP firmware performs verification of the EC's RW image, upgrades it if
-    necessary, and sysjumps the EC to it.
-1.  AP firmware queries the charge state limit power flag via EC-host command,
-    and the EC immediately responds that it is clear.
-1.  Depthcharge continues the boot.
-    1.  In parallel with kernel loading and Linux's boot, the EC performs PD
-        negotiation. Charger power lowers to 2.5W for up to 500ms as the source
-        transitions from vSafe5V to its highest supported voltage (15V or 20V
-        are typical). During this transition time some power is drawn from the
-        battery.
-    1.  After PD negotiation is complete, the EC raises the charger current
-        limit to the negotiated limit (45W is typical).
-
-### Low-Power Device Startup With Marginal Battery Compatibility
-
-Similar in configuration to the low-power device startup, this system enables
-additional options to maximize its compatibility with marginal batteries near
-the bottom of charge. The Grunt family is an exemplar. This system will complete
-software sync with less than 15W of power, but may require more power to boot
-the kernel and get to the login screen.
-
-```
-/* Limit battery impact during PD voltage changes. */
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-
-/* Distrust the battery SOC measurement a bit. */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
-
-/*
- * Require PD negotiation to be complete prior to booting Linux, but don't
- * care about how much power we negotiate.
- */
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15001
-
-/* Extra paranoia about imbalanced cells. */
-#define CONFIG_BATTERY_MEASURE_IMBALANCE
-```
-
-Additionally, in order to take advantage of cell imbalance detection, the system
-battery must support per-cell voltage measurement.
-
-A detailed boot sequence under this configuration, with a low battery and
-available AC power:
-
-1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1.  RO firmware negotiates a 15W state via Current Source analog signaling and
-    begins charging the battery with it.
-1.  RO firmware verifies conditions to begin booting the AP:
-    -   battery state of charge >= 3% AND cell imbalance < 200 mV
-    -   OR battery state of charge >= 5%
-    -   OR charger power greater or equal to 15W (met by Current Source analog
-        signaling).
-1.  AP firmware performs verification of the EC's RW image, upgrades it if
-    necessary, and sysjumps the EC to it.
-1.  AP firmware polls the charge state limit power flag via EC-host command for
-    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
-    so long as the charger power is < 15.001W and the battery is less than 3%.
-    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
-        for up to 500ms as the source transitions from vSafe5V to its highest
-        supported voltage (15V or 20V are typical).
-    1.  After negotiation is complete, the EC raises the charger current limit
-        to the negotiated limit (45W is typical).
-    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1.  Depthcharge continues to boot Linux.
-
-### High-Power Boot Device Startup
-
-A "high-power device" in this case is one that requires significantly more than
-15W of power to boot the AP. These devices may complete software sync at 15W or
-less. Very briefly drawing current out of the battery does not cause a brownout.
-
-Example configuration:
-
-```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15000
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
-```
-
-Where the low-power device specified a threshold that just barely requires PD
-negotiation to happen before booting, this device has a definite minimum power
-to boot Linux (27W). A detailed boot sequence under this configuration, with a
-low battery and available AC power:
-
-1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1.  RO firmware negotiates a 15W state via Current Source analog signaling and
-    begins charging the battery with it.
-1.  RO firmware verifies conditions to begin booting the AP:
-    -   battery state of charge >= 3%
-    -   OR charger power greater or equal to 15W (met by Current Source analog
-        signaling).
-1.  AP firmware performs verification of the EC's RW image, upgrades it if
-    necessary, and sysjumps the EC to it.
-1.  AP firmware polls the charge state limit power flag via EC-host command for
-    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
-    so long as the charger power is < 27W and the battery is less than 3%.
-    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
-        for up to 500ms as the source transitions from vSafe5V to its highest
-        supported voltage (15V or 20V are typical).
-    1.  After negotiation is complete, the EC raises the charger current limit
-        to the negotiated limit (45W is typical).
-    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1.  Depthcharge continues to boot Linux.
-
-### High-Power SwSync Device Startup
-
-Like the high-power boot device startup, these devices draw less than 15W during
-most of the software sync process, but may briefly exceed 15W during short
-intervals of software sync. However, there is substantial risk of brownout
-during those intervals unless the battery is charged up a bit first. Therefore,
-they strictly require 1% battery capacity to perform software sync.
-Additionally, this configuration requires PD negotiation to be complete prior to
-performing a no-battery boot. Nami is an exemplar.
-
-Example configuration:
-
-```
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
-
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000
-
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3
-#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
-```
-
-1.  EC ROM bootloader loads and jumps to the EC's read-only firmware image.
-1.  RO firmware negotiates a 15W state via Current Source analog signaling and
-    begins charging the battery with it.
-1.  RO firmware verifies conditions to begin booting the AP:
-    -   Battery state of charge is greater than 1% AND charger power is greater
-        than 15W (met after a minute or so of charging on analog signaling)
-    -   OR Battery state of charge is greater than 3%
-    -   OR Charger power is greater than 27W (met after PD negotiation in
-        unlocked RO firmware).
-1.  AP firmware performs verification of the EC's RW image, upgrades it if
-    necessary, and sysjumps the EC to it.
-1.  AP firmware polls the charge state limit power flag via EC-host command for
-    up to 3 seconds, in 50ms intervals. The EC will return `1` (power limited)
-    so long as the charger power is < 27W and the battery is less than 3%.
-    1.  Meanwhile, the EC performs PD negotiation. Charger power lowers to 2.5W
-        for up to 500ms as the source transitions from vSafe5V to its highest
-        supported voltage (15V or 20V are typical).
-    1.  After negotiation is complete, the EC raises the charger current limit
-        to the negotiated limit (45W is typical).
-    1.  The EC returns 0 (unlimited) on the next `LIMIT_POWER` request.
-1.  Depthcharge continues to boot Linux.
-
-## Configuration Option Details
-
-### `CONFIG_CHARGER_INPUT_CURRENT`
-
-Required.
-
-The lowest current limit programmed into the charger. This determines both the
-default level used on startup, and the value used during the voltage transients
-in PD negotiation.
-
-It should not be higher than 512 mA unless the device ships with a discrete
-power supply. Raising this term above 512 mA is contrary to USB-PD. It may be
-lowered in order to improve compatibility with marginal BC1.2 chargers.
-
-### `CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON`
-
-Required.
-
-The minimum battery state of charge to start up the AP, in percent of full
-charge.
-
-#### `CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON`
-
-Default: 15000 (15W)
-
-The minimum charger power level to start the AP even when the battery is less
-than `CHARGER_MIN_BAT_PCT_FOR_POWER_ON`, in milliwatts.
-
-### `CONFIG_BATTERY_MEASURE_IMBALANCE`
-
-Optional. Only set this option if one or more batteries shipped with this board
-support per-cell battery voltage measurement.
-
-When enabled, the EC will query the attached battery for its per-cell voltages.
-If the cell voltage is excessively imbalanced at a low state of charge, the boot
-is inhibited.
-
-#### `CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON`
-
-Default: 5%. Above this battery state of charge, cell voltage balance is
-ignored.
-
-#### `CONFIG_BATTERY_MAX_IMBALANCE_MV`
-
-Default: 200 mV. If the difference between the highest and lowest cell exceeds
-this value, then the pack is considered to be imbalanced.
-
-Note that lithium chemistry cells will almost always read similar voltages. It
-is only near the top and bottom of charge that the slope of dV/dQ increases
-enough for small cell imbalances to be visible as a voltage difference.
-
-### `CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW`
-
-Optional.
-
-The minimum charger power level to allow Depthcharge to start up the kernel,
-even when the battery state of charge is less than
-`CHARGER_LIMIT_POWER_THRESH_BAT_PCT`, in milliwatts.
-
-When this term is `#undef`ined (the default), kernel startup is immediately
-allowed.
-
-#### `CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT`
-
-Optional.
-
-The minimum battery state of charge to allow Depthcharge to start up the kernel.
-When using this feature, start with `CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON`
-
-### `CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC`
-
-Optional.
-
-Similar to `MIN_BAT_PCT_FOR_POWER_ON`, but used to define a secondary threshold
-for this feature.
-
-#### `CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT`
-
-Optional.
-
-Similar to `CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON`, this is the minimum
-charger power needed to boot even when the battery is less than
-`CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC`
diff --git a/docs/new_board_checklist.md b/docs/new_board_checklist.md
deleted file mode 100644
index 7fe89d4121..0000000000
--- a/docs/new_board_checklist.md
+++ /dev/null
@@ -1,179 +0,0 @@
-# Creating a new EC board
-
-[TOC]
-
-## Overview
-
-This document describes the high-level steps needed to create a new EC board. If
-you're creating a new board based on existing baseboard, you can jump straight
-to the relevant link found under
-[Configuring EC Features](#Configure-EC-Features) and focus on known board
-changes.
-
-## Conventions
-
-### Key Files
-
-Before you get started, it's important to understand the role of a few key files
-in the EC codebase.
-
--   [`include/config.h`](../include/config.h) {#config_h} - Contains the list of
-    top-level configuration options for the Chrome EC codebase. Each
-    configuration option is documented inline and is considered the
-    authoritative definition.
-
--   `baseboard/<name>/` - This directory contains header files and source files
-    shared by all boards in a baseboard family.
-
-    -   `baseboard.h` - Contains the EC configuration options shared by all
-        devices in the baseboard family.
-    -   `baseboard.c` - Contains code shared by all devices in the baseboard
-        family.
-    -   `build.mk` - The board family makefile specifies C source files compiled
-        into all boards in the baseboard family.
-
--   `board/<board>` - Files in this directory are only built for a single board.
-
-    -   `board.h` - EC configuration options specific to a single board.
-    -   `board.c` - Code built only on this board.
-    -   `build.mk` {#board_build_mk} - The board makefile defines the EC chipset
-        family, defines the baseboard name, and specifies the C source files
-        that are compiled.
-    -   `gpio.inc` - This C header file defines the interrupts, GPIOs, and
-        alternate function selection for all pins on the EC chipset.
-    -   `ec.tasklist` - This C header defines the lists of tasks that are
-        enabled on the board. See the main EC documentation more details on
-        [EC tasks].
-
-### GPIO Naming
-
-Many drivers and libraries in the common EC code rely on board variants defining
-an exact GPIO signal name. Examples include the `GPIO_LID_OPEN`,
-`GPIO_ENTERING_RW`, and `GPIO_SYS_RESET_L` signals. The net names in schematics
-often do not match these names exactly. When this occurs, best practice is that
-all the `GPIO_INT()`, `GPIO()`, `ALTERNATE()`, and `UNIMPLEMENTED()` definitions
-in `gpio.inc` use the schematic net name. You then create `#define` macros in
-`board.h` to map the net names to the EC common names.
-
-Below is an example configuration for the SYS_RESET_L signal. The schematic net
-name of this signal is EC_RST_ODL and the signal connects to the EC chipset pin
-GPIO02.
-
-```c
-/* From gpio.inc */
-GPIO(EC_RST_ODL,  PIN(0, 2), GPIO_ODR_HIGH)
-
-/* From board.h */
-/* Map the schematic net name to the required EC name */
-#define GPIO_SYS_RESET_L  GPIO_EC_RST_ODL
-```
-
-Please see the [GPIO](./configuration/gpio.md) documentation for additional
-details on the GPIO macros.
-
-## How to use this document
-
-Each of the following sections details a single feature set that may need to be
-modified or configured for your new board. The feature sets are organized so
-they can be implemented with a reasonably sized change list, and can be worked
-on independently.
-
-Each configuration feature document includes the following sub-tasks:
-
--   **Config Options** - This section details the `CONFIG_*` options relevant to
-    the feature. Use the documentation found in [config.h] to determine whether
-    each option should be enabled (using #define) or disabled (using #undef) in
-    the relevant `baseboard.h` or `board.h` file.
--   **Feature Parameters** - This section details parameters that control the
-    operation of the feature. Similar to the config options, feature parameters
-    are defined in [config.h] and prefixed with `CONFIG_*`. However, feature
-    parameters are assigned a default value, which can be overridden in by
-    `baseboard.h` or `board.h` using an `#undef/#define` pair. `c #undef
-    CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096`
--   **GPIOs and Alternate Pins** - This section details signals and pins
-    relevant to the feature. Add the required `GPIO_INT()`, `GPIO()`,
-    `ALTERNATE()`, and `UNIMPLEMENTED()` definitions to `gpio.inc`, making sure
-    to follow the [GPIO naming conventions].
--   **Data Structures** - This section details the data structures required to
-    configure the feature for correct operation. Add the data structures to
-    `baseboard.c` or `board.c`. Note that most data structures required by the
-    common EC code should be declared `const` to save on RAM usage.
--   **Tasks** - This section details the tasks that the EC feature requires for
-    operation.
--   **Testing and Debugging** - This section details strategies for testing the
-    EC feature set and for debugging issues. This section also documents EC
-    console commands related to the feature set.
--   **Example** - When present, this section walks through a complete example
-    for configuring an EC feature based on an existing board implementation.
-
-## Create the new EC board
-
-The first step when creating a new EC board, is to create the required files in
-the `./baseboard` and `./board` directories. When adding a new board for an
-existing baseboard family, use the python script [new_variant.py] to
-automatically copy the `./board` directory from an existing EC board to get you
-started. The [new_variant.py] script performs additional operations not directly
-related to the EC code, including copying coreboot files and modifying the yaml
-files. If you want to copy the EC board files only, you can directly call the
-[create_initial_ec_image.sh] script. The instructions for running this script
-are found in the corresponding [README.md] documentation.
-
-The [new_variant.py] script also verifies the new EC board compiles and prepares
-a changelist to upload to Gerrit. You should upload this changelist unmodified
-for review and submission (you may need to run `make buildall -k` to satisfy the
-EC pre-submit tests).
-
-The next step is to review the following sections to make any needed
-modifications to your new board files, test the changes, and upload the changes
-for review.
-
-### Creating a new reference board
-
-If you are creating a new reference board, it is recommended that you manually
-create new directories under the `./baseboard` and `./board` directories and
-populate these directories with the minimum set of files required compile the EC
-board. The initial changelists for the Hatch and Volteer reference boards
-provide good examples for how to start.
-
-*   [Volteer EC skeleton build]
-*   [Hatch EC skeleton build]
-
-After submitting the skeleton builds, review the following sections and add each
-feature set as required by your design.
-
-## Configure EC Features
-
-The checklist below provides an overview of EC features that must be configured
-for correct operation of a Chromebook. The "Needed for Power On" column
-indicates which features are critical for board bringup. These features take
-priority and should be ready before the first prototypes arrive. Use the
-documentation link for details about the code changes required to implement each
-feature.
-
-EC Feature                                                                  | Needed for Power On
-:-------------------------------------------------------------------------- | ------------------:
-[Configure EC Chipset](./configuration/ec_chipset.md)                       | yes
-[Configure AP to EC Communication](./configuration/config_ap_to_ec_comm.md) | yes
-[Configure AP Power Sequencing](./configuration/ap_power_sequencing.md)     | yes
-[Configure USB-C](./usb-c.md)                                               | yes
-[Configure Charger (TODO)](./configuration/template.md)                     | yes
-[Configure I2C Buses](./configuration/i2c.md)                               | no
-[Configure CrOS Board Information (CBI)](./configuration/cbi.md)            | no
-[Configure Keyboard](./configuration/keyboard.md)                           | no
-[Configure LEDs](./configuration/leds.md)                                   | no
-[Configure Motion Sensors (TODO)](./configuration/motion_sensors.md)        | no
-[Configure BC1.2 Charger Detector (TODO)](./configuration/template.md)      | no
-[Configure Battery (TODO)](./configuration/template.md)                     | no
-
-After finishing the changes required for all EC features, it is recommended that
-you make one final pass over all the GPIOs and pin assignments used on your
-board. Refer to the [GPIO](./configuration/gpio.md) documentation for details.
-
-[README.md]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/README.md
-[new_variant.py]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/new_variant.py
-[create_initial_ec_image.sh]:https://chromium.googlesource.com/chromiumos/platform/dev-util/+/HEAD/contrib/variant/create_initial_ec_image.sh
-[Volteer EC skeleton build]:https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1758532
-[Hatch EC skeleton build]:https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1377569/
-[config.h]: ./new_board_checklist.md#config_h
-[EC tasks]: ../README.md#Tasks
-[GPIO naming conventions]: ./new_board_checklist.md#GPIO-Naming
diff --git a/docs/reducing_ec_image_size.md b/docs/reducing_ec_image_size.md
deleted file mode 100644
index a165f165ff..0000000000
--- a/docs/reducing_ec_image_size.md
+++ /dev/null
@@ -1,459 +0,0 @@
-# Reducing the EC image size
-
-The EC ToT codebase continues grows as new features are added and for bug
-fixes. This puts pressure on older boards that have limited flash space
-remaining. This document provides some tips for reducing the EC image size.
-
-[TOC]
-
-## Checking the EC image footprint
-
-The EC codebase supports two build types:
-
-1. `cros-ec` builds are the legacy EC images built using Make (e.g. `make
-   BOARD=volteer`)
-1. `zephyr-ec` builds are the EC images built using the Zephyr RTOS kernel using
-   zmake/Cmake (e.g. `zmake configure -b zephyr/projects/volteer/volteer`)
-
-### Checking a single cros-ec build
-
-Building a single cros-ec board using `make BOARD=<board> -j` reports the the
-number of bytes free in flash and RAM for both the RO and RW images.  An example
-from building the juniper board is shown below.
-
-```
-$ make BOARD=juniper -j
-    ...
-  *** 668 bytes in flash and 10308 bytes in RAM still available on juniper RO ****
-  *** 3224 bytes in flash and 7460 bytes in RAM still available on juniper RW ****
-```
-
-### Checking all cros-ec builds
-
-Running `make buildall -j` shows a summary of the three boards with the smallest
-RO flash footprint, FW flash footprint, and RW RAM footprint.
-
-```
-$ make buildall -j
-    ...
-buildall completed successfully!
-Smallest free spaces in RO flash (bytes):
-servo_v4  :    104
-scarlet   :    108
-mushu     :    160
-Smallest free spaces in RW flash (bytes):
-mushu     :     96
-bobba     :    232
-trondo    :    376
-Tightest boards' RW RAM images, bytes free:
-whiskers  :    244
-minimuffin:    284
-zinger    :    284
-```
-
-### Comparing cros-ec image sizes
-
-The cros-ec makefile provides two make targets for helping track the impact of
-code changes.
-
-`make savesizes` saves the EC footprint information for all boards, providing
-the baseline for comparison.  `make newsizes` compares the sizes of the current
-build against the EC footprint information saved by most recent invocation of
-`make savesizes`.
-
-General workflow:
-1. Checkout branch you need to compare against.  For example `repo start
-   check-ec-size -r cros/main` or `repo start check-ec-size -r <hash>`.
-1. Run `make buildall -j`.
-1. Run `make savesizes`.
-1. Apply your code change (e.g. change the local branch, cherry-pick your
-   changes, or directly edit source files).
-1. Run `make buildall -j` again.
-1. Run `make newsizes` to generate report of size changes.
-
-Example report from `make newsizes` shown below:
-
-```
-$ make newsizes
-build/burnet/RO/space_free_flash grew by 576 bytes: (488 to 1064)
-build/burnet/RW/space_free_flash grew by 552 bytes: (1324 to 1876)
-build/cerise/RO/space_free_flash grew by 512 bytes: (276 to 788)
-build/cerise/RW/space_free_flash grew by 548 bytes: (7076 to 7624)
-    ...
-```
-
-### Checking a single zephyr-ec build
-
-By default all the information messages from the `zmake` tool are hidden during
-builds of zephyr-ec boards.
-
-Changing the logging level to INFO, displays the flash and SRAM usage of board.
-
-```
-$ zmake -l INFO configure -b zephyr/projects/volteer/volteer
-INFO: Clearing old build directory /mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer
-    ...
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:ro]Memory region         Used Size  Region Size  %age Used
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:ro]FLASH:      238852 B       512 KB     45.56%
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:ro]SRAM:       57144 B        62 KB     90.01%
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:ro]IDT_LIST:          0 GB         2 KB      0.00%
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:rw]Memory region         Used Size  Region Size  %age Used
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:rw]FLASH:      238852 B       512 KB     45.56%
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:rw]SRAM:       57144 B        62 KB     90.01%
-INFO: [/mnt/host/source/src/platform/ec/build/zephyr/projects/volteer/volteer:rw]IDT_LIST:          0 GB         2 KB      0.00%
-```
-
-For easier to read output, you can run the ninja build tool directly and see the
-RO and RW footprint.
-
-```
-$ zmake configure zephyr/projects/volteer/volteer/
-$ ninja -C build/zephyr/projects/volteer/volteer/build-ro
-ninja: Entering directory 'build/zephyr/projects/volteer/volteer/build-ro'
-[1/324] Preparing syscall dependency handling
-
-[317/324] Linking C executable zephyr/zephyr_prebuilt.elf
-
-[324/324] Linking C executable zephyr/zephyr.elf
-Memory region         Used Size  Region Size  %age Used
-           FLASH:      238852 B       512 KB     45.56%
-            SRAM:       57144 B        62 KB     90.01%
-        IDT_LIST:          0 GB         2 KB      0.00%
-```
-
-Note, that the flash region size listed above represents the total flash
-available on the EC. The actual available region size is only half the reported
-value in order to store two images (RO+RW).
-
-#### Other Zephyr utilities
-
-The Cmake system utilized by Zephyr provides two build targets `rom_report` and
-`ram_report` which generate a list of all the compiled objects in tabular form.
-This can be useful for identifying particular modules that contribute to the
-image size.
-
-The `rom_report` and `ram_report` targets are currently only supported when
-working outside the chroot.  Follow the [instructions][1] for building zephyr-ec
-images outside chroot before running the commands below.
-
-```
-# Configure the Volteer zephyr project, storing the build files in /tmp/zephyr-volteer
-$ zmake configure -B /tmp/zephyr-volteer zephyr/projects/volteer/volteer -t zephyr
-
-# Build the RO image
-$ ninja -C /tmp/zephyr-volteer/build-ro
-
-# Generate the ROM report, report sent to stdout
-$ ninja -C /tmp/zephyr-volteer/build-ro rom_report
-```
-
-Please refer to the [Zephyr Optimization Tools][3] documentation for details on
-the `rom_report` and `ram_report` targets.
-
-## Disable console commands
-
-The lowest hanging fruit for reducing the EC image size is by disabling console
-commands that provide debug information only and don't impact the user or the
-automated testing.  Any console command that is not used by the FAFT tests and
-suites is safe to disable in the EC images.
-
-For cros-ec builds, add `#undef CONFIG_CMD_<name>` to the board.h or baseboard.h
-file to disable the console command.
-
-For zephyr-ec builds, add `CONFIG_PLATFORM_EC_CONSOLE_CMD_<name>=n` to the board
-prj.conf file to disable the console command.
-
-* TODO: Create new CONFIG/Kconfig option that disables all console commands not
-  required by FAFT.
-
-| Used by FAFT | config.h option | Console commands | Notes |
-|:---|:---|:---|:---|
-|  | CONFIG_CMD_ACCELS | `accelrange`<br>`accelres`<br>`accelrate`<br>`accelread`<br>`accelinit`<br>`accelinfo` | |
-|  | CONFIG_CMD_ACCELSPOOF | `accelspoof` | |
-| | CONFIG_CMD_ACCEL_FIFO | `fiforead` | |
-| | CONFIG_CMD_ACCEL_INFO | `accelinfo` | |
-| | CONFIG_CMD_ADC | `adc` | Note firmware_ECAdc uses the `temps` command. |
-| | CONFIG_CMD_ALS | `als` | |
-| | CONFIG_CMD_APTHROTTLE | `apthrottle` | |
-| | CONFIG_CMD_AP_RESET_LOG |??? | |
-| | CONFIG_CMD_BATDEBUG | `fgunseal`<br>`fgseal`<br>`fginit`<br>`fgprobe`<br>`fgrd`<br>`fgcmd`<br>`fcmdrd` | |
-| | CONFIG_CMD_BATTFAKE | `battfake` | |
-| | CONFIG_CMD_BATT_MFG_ACCESS | `battmfgacc` | |
-| | CONFIG_CMD_CBI | `cbi` | firmwareECCbiEeprom uses `ectool` on AP to test CBI |
-| x | CONFIG_CMD_CHARGEN | `chargen` | Used by firmware_Cr50CCDUartStress, included in faft_ccd, faft_cr50_prepvt, and faft_cr50_pvt suites |
-| | CONFIG_CMD_CHARGER | `bd9995x`<br>`sy21612` | |
-| | CONFIG_CMD_CHARGER_ADC_AMON_BMON | `amonbmon` | |
-| | CONFIG_CMD_CHARGER_DUMP | `charger_dump` | |
-| | CONFIG_CMD_CHARGER_PROFILE_OVERRIDE | `fastcharge` | |
-| | CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST | `fastchgtest` | |
-| | CONFIG_CMD_CHARGE_SUPPLIER_INFO | `chgsup` | |
-| | CONFIG_CMD_CHGRAMP | `chgramp` | |
-| | CONFIG_CMD_CLOCKGATES | `clockgates` | |
-| | CONFIG_CMD_COMXTEST | `comxtest` | |
-| x | CONFIG_CMD_CRASH | `crash` | |
-| | CONFIG_CMD_DEVICE_EVENT | `deviceevent` | |
-| | CONFIG_CMD_DLOG | `dlog` | |
-| | CONFIG_CMD_ECTEMP | `ectemp` | |
-| | CONFIG_CMD_FASTCHARGE | `fastcharge` | Obsolete? use CONFIG_CMD_CHARGER_PROFILE_OVERRIDE? |
-| | CONFIG_CMD_FLASH | `flasherase`<br>`flashwrite`<br>`flashread` | |
-| | CONFIG_CMD_FLASHINFO | `flashinfo` | |
-| | CONFIG_CMD_FLASH_TRISTATE | `fpcapture`<br>`flash_tristate` | |
-| | CONFIG_CMD_FLASH_WP | `flashwp` | |
-| | CONFIG_CMD_FORCETIME | `forcetime` | |
-| | CONFIG_CMD_FPSENSOR_DEBUG | `fpcapture`<br>`fpenroll`<br>`fpmatch`<br>`fpclear`<br>`fpmaintenance` | |
-| | CONFIG_CMD_GETTIME | `gettime` | Used by Cr50 tests, not by FAFT EC |
-| | CONFIG_CMD_GL3590 | `gl3590` | |
-| | CONFIG_CMD_GPIO_EXTENDED | Adds options to `gpioget` and `gpioset`. | Should be renamed to CONFIG_GPOI_EXTENDED |
-| | CONFIG_CMD_GPIO_POWER_DOWN | Not a valid config. | Should be CONFIG_GPIO_POWER_DOWN |
-| | CONFIG_CMD_GT7288 | `gt7288_desc`<br>`gt7288_repdesc`<br>`gt7288_ver`<br>`gt7288_report` | |
-| | CONFIG_CMD_HASH | `hash` | firmware_ECHash uses `ectool echash` |
-| x | CONFIG_CMD_HCDEBUG | `hcdebug` | firmware_ECBootTime.py |
-| x | CONFIG_CMD_HOSTCMD | `hostcmd` | |
-| | CONFIG_CMD_I2CWEDGE | `i2cwedge`<br>`i2cunwedge` | |
-| | CONFIG_CMD_I2C_PROTECT | `i2cprotect` | |
-| | CONFIG_CMD_I2C_SCAN | `i2cscan` | |
-| | CONFIG_CMD_I2C_STRESS_TEST | `i2ctest` | |
-| | CONFIG_CMD_I2C_STRESS_TEST_ACCEL | Not a console command | |
-| | CONFIG_CMD_I2C_STRESS_TEST_ALS | Not a console command | |
-| | CONFIG_CMD_I2C_STRESS_TEST_BATTERY | Not a console command | |
-| | CONFIG_CMD_I2C_STRESS_TEST_CHARGER | Not a console command | |
-| | CONFIG_CMD_I2C_STRESS_TEST_TCPC | `Not a console command | |
-| | CONFIG_CMD_I2C_XFER | `i2cxfer` | firmware_ECCbiEeprom uses `ectool i2cxfer` which is not guarded by CONFIG_CMD_I2C_XFER |
-| | CONFIG_CMD_I2C_XFER_RAW |  | Adds options to `i2cxfer` |
-| | CONFIG_CMD_IDLE_STATS | `idlestats` | |
-| | CONFIG_CMD_INA | `ina` | |
-| | CONFIG_CMD_JUMPTAGS | `jumptags` | |
-| x | CONFIG_CMD_KEYBOARD | `8042`<br>`ksstate`<br>`kbpress` | |
-| | CONFIG_CMD_LEDTEST | `ledtest` | |
-| | CONFIG_CMD_MCDP | `mcdp` | |
-| | CONFIG_CMD_MD | `md` | |
-| | CONFIG_CMD_MEM | | Not a console command - gates `md` and `rw` |
-| | CONFIG_CMD_MFALLOW | `mfallow` | |
-| | CONFIG_CMD_MMAPINFO | `mmapinfo` | |
-| x | CONFIG_CMD_PD | `pd` | Used by FAFT PD |
-| | CONFIG_CMD_PD_DEV_DUMP_INFO | | Not a console command |
-| | CONFIG_CMD_PD_FLASH | `pd flash` | Not supported by TCPMv2 |
-| | CONFIG_CMD_PECI | `peci` | firmware_ECThermal uses `ectool tempsinfo` |
-| | CONFIG_CMD_PLL | `pll` | only used by lm4 chip |
-| | CONFIG_CMD_POWERINDEBUG | `powerindebug` | |
-| | CONFIG_CMD_POWERLED | `powerled` | |
-| x | CONFIG_CMD_POWER_AP | `apreset`<br>`apshutdown` | Used by power_Monitoring.py |
-| | CONFIG_CMD_PPC_DUMP | `ppc_dump` | |
-| | CONFIG_CMD_PS2 | `ps2ench`<br>`ps2write` | Used only on NPCX |
-| | CONFIG_CMD_PWR_AVG | `pwr_avg` | |
-| | CONFIG_CMD_RAND | `rand` | Used only on STM32 |
-| | CONFIG_CMD_REGULATOR | `ir357x` | |
-| | CONFIG_CMD_RESET_FLAGS | `rflags` | |
-| | CONFIG_CMD_RETIMER | `bb`<br>`kbxfer` | |
-| | CONFIG_CMD_RTC | `rtc` | |
-| | CONFIG_CMD_RTC_ALARM | `rtc_alarm` | |
-| | CONFIG_CMD_RW | `rw` | |
-| | CONFIG_CMD_SCRATCHPAD | `scratchpad` | |
-| | CONFIG_CMD_SEVEN_SEG_DISPLAY | `seg` | |
-| | CONFIG_CMD_SHA256_TEST | `???` | |
-| x | CONFIG_CMD_SHMEM | `shmem` | Used by firmware_ECSharedMem |
-| | CONFIG_CMD_SLEEP | `sleep` | used only lm4 |
-| | CONFIG_CMD_SLEEPMASK | `sleepmask` | Only used for Cr50 tests |
-| | CONFIG_CMD_SLEEPMASK_SET | | Adds options to `sleepmask` |
-| | CONFIG_CMD_SPI_FLASH | `spi_flasherase`<br>`spi_flashwrite`<br>`spi_flashread`<br>`spi_flash_rsr`<br>`spi_flash_wsr`<br>`spi_flash_wsr` | |
-| | CONFIG_CMD_SPI_NOR | `spinorinfo`<br>`spinorerase`<br>`spinorwrite`<br>`spinorread` | |
-| | CONFIG_CMD_SPI_XFER | `spixfer` | |
-| | CONFIG_CMD_STACKOVERFLOW | `crash stack` | Adds option to `crash` command. |
-| x | CONFIG_CMD_SYSINFO | `sysinfo` | Used by firmware_ECSystemLocked |
-| x | CONFIG_CMD_SYSJUMP | `sysjump` | Used by firmware_ECSharedMem |
-| | CONFIG_CMD_SYSLOCK | `syslock` | |
-| | CONFIG_CMD_TASKREADY | `taskready` | |
-| | CONFIG_CMD_TASK_RESET | `taskreset` | |
-| | CONFIG_CMD_TCPC_DUMP | `tcpci_dump` | |
-| x | CONFIG_CMD_TEMP_SENSOR | `temps` | |
-| | CONFIG_CMD_TIMERINFO | `timerinfo` | |
-| | CONFIG_CMD_TYPEC | `typec` | |
-| | CONFIG_CMD_USART_INFO | `usart_info` | |
-| | CONFIG_CMD_USB_PD_CABLE | `pdcable` | |
-| x | CONFIG_CMD_USB_PD_PE | `pe` | Doesn't appear to be used but might be by FAFT PD |
-| x | CONFIG_CMD_WAITMS | `waitms` | firmware_ECWatchdog | |
-
-## Reduce or eliminate USB-C debugging
-
-The TCPM (Type-C Port manager) implementation is one of the more complex modules
-implemented by the EC code. This module includes extensive debugging and is
-enabled by default due to the value provided during both board bringup and on
-production systems.
-
-The TCPM provides the following debug levels:
-* `DEBUG_DISABLE` (0) - Debugging disabled, no runtime messages displayed
-* `DEBUG_LEVEL_1` (1) - Displays all the state transitions for the TC (Type-C)
-  and PE (Policy Engine) state machines
-* `DEBUG_LEVEL_2` (2) - Displays the raw contents of received PD (Power
-  Delivery) packets, excluding PING packets
-* `DEBUG_LEVEL_3` (3) - Enables debug messages in the PRL Also displays received
-  PING packets.
-
-When `CONFIG_USB_PD_DEBUG_LEVEL` is undefined, the EC allows runtime
-configuration of the USB-C debug level using the `pd dump <level>` EC console
-command. In this configuration, the strings from all debug levels are included
-in the image.
-
-Enabling a fixed debug level removes runtime control of the debug level and also
-removes the strings for the higher debug levels.
-
-For cros-ec builds, add the following to your board.h/baseboard.h file:
-
-```c
-    #define CONFIG_USB_PD_DEBUG_LEVEL <level>
-```
-
-For zephyr-ec builds, add the following to your prj.conf file:
-
-```
-    CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
-    CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=<level>
-```
-
-Approximate flash space savings from each fixed level setting:
-
-Fixed Debug Level | Relative Saving | Cumulative Saving
---- | --- | ---
-Disabled | 0 | 0
-3 | 100 bytes | 100 bytes
-2 | 500-600 bytes | 600-700 bytes
-1 | 100 bytes | 700-800 bytes
-0 | 2000 bytes | 2700-2800 bytes
-
-The recommended setting is setting the fixed debug level to `DEBUG_LEVEL_2` (2).
-This adds details about received PD packets in the EC log stored by the kernel
-and can help troubleshoot PD issues when a PD analyzer isn't available.
-
-It is not recommended to set the fixed debug level to `DEBUG_DISABLE` (0) on any
-shipping firmware.
-
-### TCPMv1 Configuration
-
-Many older platforms still use the legacy TCPMv1 (`CONFIG_USB_PD_TCPMV1`)
-implementation.  Specific to TCPMv1, the PD protocol state names can be removed
-from the debug output by adding the following to the board.h/baseboard.h file.
-
-```c
-#undef CONFIG_USB_PD_TCPMV1_DEBUG
-```
-
-This saves around 900 bytes of flash space. TCPMv2 does not currently provide an
-equivalent configuration option, so there is also no Kconfig equivalent.
-
-## Other optional features
-
-### ASSERT() Calls
-
-By default, `ASSERT()` calls generate a console message of the following form:
-
-```
-    ASSERTION FAILURE '<expr>' in function() at file:line
-```
-
-There are two options available that reduce the size of strings stored with the
-`ASSERT()` calls.
-
-Description | cros-ec setting | zephyr-ec setting | Total Savings
-:--- | :--- | :--- | :---
-Display only file and line number | `#define CONFIG_DEBUG_ASSERT_BRIEF` | `CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF=y` | 2000-2500 bytes
-Disable all debug from ASSERT() calls.<br> EC is reset using a software breakpoint. | `#undef CONFIG_DEBUG_ASSERT_REBOOTS` | `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS=n`<br>`CONFIG_PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT=y` | 3000-4000 bytes
-
-It is not recommended to disable `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS` on
-shipping firmware.
-
-### Disable console help
-
-The help strings can be removed from the final build, saving about 5000 bytes of
-flash space.
-
-For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` to the
-board.h/baseboard.h file.
-
-zephyr-ec builds use Zephyr's shell subsystem and by default enable the
-`CONFIG_SHELL_MINIMAL` option.  This option already disables shell help along
-with many other non-critical features. Refer to the shell subsystem [Kconfig][2]
-source file for the complete list of shell features than can be configured.
-
-### Link time optimizaiton
-
-Link time optimization (LTO) is a feature of the linker to identify and remove
-unused code.
-
-For cros-ec builds, LTO is enabled by adding this to the board.h/baseboard.h
-file.
-
-```c
-#define CONFIG_LTO
-```
-
-For zephyr-ec builds, LTO is enabled by default and is controlled with Kconfig.
-
-```
-CONFIG_LTO=y
-```
-
-Note that for zephyr-ec builds, LTO is only turned on for the source files found
-under `platform/ec`.  The upstream Zephyr code does not currently support LTO
-due to some auto-generated code that breaks the assumptions made by the linker.
-This [Github issue][4] tracks the effort to support LTO in the Zephyr kernel.
-
-### CONFIG_CHIP_INIT_ROM_REGION
-
-The config option `CONFIG_CHIP_INIT_ROM_REGION` creates a new linker section to
-store data that remains resident in ROM/flash at runtime. This reduces the
-effective cros-ec image size by identifying data structures that do not need to
-be copied into the code RAM section at startup.
-
-This option has the following requirements:
-1. EC executes code from RAM
-2. The ROM/flash size is larger than 2 times the code RAM size.
-3. The RO code released for the board includes this
-   [change](https://crrev.com/c/2428566).
-
-The only EC chip that matches these prerequisites is the Nuvoton NPCX7.
-
-Due to the RO code requirement, take care before enabling this option for boards
-released prior to 2021.
-
-If the above requirements are meant, add the following to the
-board.h/baseboard.h file:
-
-```c
-#define CONFIG_CHIP_INIT_ROM_REGION
-#define CONFIG_CHIP_DATA_IN_INIT_ROM
-```
-
-These options are not supported for zephyr-ec builds.
-
-### Enable short GPIO names
-
-The [GPIO macros](./configuration/gpio.md) defined by the board get stored as
-descriptive strings for use with the `gpioget` and `gpioset` console commands.
-
-The names of the GPIOs can be shorted by enabling the
-`CONFIG_COMMON_GPIO_SHORTNAMES` option.
-
-For example, the Kukui board defines this GPIO:
-
-```c
-GPIO(PMIC_FORCE_RESET_ODL, PIN(A, 2),  GPIO_ODR_HIGH)
-```
-
-Normally, the GPIO name is stored exactly as specified by the macro:
-`PMIC_FORCE_RESET_ODL`.  However, when `CONFIG_COMMON_GPIO_SHORTNAMES` is
-defined, then the GPIO name is shortened to only include port and pin number:
-`A2`.
-
-This option is currently only supported by the STM32 chip and it is not
-supported by zephyr-ec builds.
-
-Note that there are some [FAFT tests][5] that rely on the GPIO name. If you
-enable this option, you may also need to change firmware testing configuration
-[file][6].
-
-[1]:./zephyr_build.md#Working-outside-the-chroot
-[2]:https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/shell/Kconfig
-[3]:https://docs.zephyrproject.org/latest/guides/optimizations/tools.html
-[4]:https://github.com/zephyrproject-rtos/zephyr/issues/2112
-[5]:https://chromium.googlesource.com/chromiumos/third_party/autotest/+/069cb4b0/server/site_tests/firmware_ECUsbPorts/firmware_ECUsbPorts.py#81
-[6]:https://chromium.googlesource.com/chromiumos/platform/fw-testing-configs/+/e2e9547e/volteer.json#26
diff --git a/docs/schematics/dragonclaw/LICENSE b/docs/schematics/dragonclaw/LICENSE
deleted file mode 100644
index d1b237d529..0000000000
--- a/docs/schematics/dragonclaw/LICENSE
+++ /dev/null
@@ -1,318 +0,0 @@
-Creative Commons Attribution 4.0 International Public License
-
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diff --git a/docs/schematics/dragonclaw/README.md b/docs/schematics/dragonclaw/README.md
deleted file mode 100644
index 66fde41df8..0000000000
--- a/docs/schematics/dragonclaw/README.md
+++ /dev/null
@@ -1,10 +0,0 @@
-# Dragonclaw Fingerprint Development Board Schematics
-
-The schematics are in the [HTML file][schematic] and viewable with any browser.
-Note that you'll need to download and save the HTML file from
-[this link][schematic]; you cannot view it directly from the server.
-
-The layout file is in the [`.brd`] file.
-
-[`.brd`]: https://raw.githubusercontent.com/coreboot/chrome-ec/master/docs/schematics/dragonclaw/dragonclaw_v0.2.brd
-[schematic]: https://raw.githubusercontent.com/coreboot/chrome-ec/master/docs/schematics/dragonclaw/dragonclaw_v0.2.html
diff --git a/docs/schematics/dragonclaw/dragonclaw_v0.2.brd b/docs/schematics/dragonclaw/dragonclaw_v0.2.brd
deleted file mode 100644
index 37e8b3190d..0000000000
--- a/docs/schematics/dragonclaw/dragonclaw_v0.2.brd
+++ /dev/null
diff --git a/docs/schematics/dragonclaw/dragonclaw_v0.2.html b/docs/schematics/dragonclaw/dragonclaw_v0.2.html
deleted file mode 100644
index c3241ae00f..0000000000
--- a/docs/schematics/dragonclaw/dragonclaw_v0.2.html
+++ /dev/null
@@ -1,7087 +0,0 @@
-<!DOCTYPE html>
-<html lang="en"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
-
-<link rel="icon" href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAEgAAABIAQMAAABvIyEEAAAABlBMVEUAAAAAAAClZ7nPAAAAAXRSTlMAQObYZgAAAFdJREFUKM9jYGBg+A+EEEANFvN/EDgAZMmDWT+ALHsw6w+QVQ9m/UNh/YcAXCyo6VRiAc38D8ZUYoH9/R9qBxVYNHAfVcOPQGxhi19E7CNSBCKVUDf9AQBM1TcCCjMB0AAAAABJRU5ErkJggg==">
-<title>dragonclaw.cpm - ab219060b29f55c904192cae83fe7d668b73d4b9</title>
-</head><body>
-<script>/* Javascript code for DiffUI. Directly embedded. */
-
-var zoom = 1;
-var dark = null;
-
-/** Activates or deactivates animations referenced by diff id.
- * classname -- used to select which animations to trigger
- * state -- whether to animate (or reset)
- * conflictswith -- classname this diff conflicts with.
- *                  Conflicting animations will not be started.
- */
-var setAnimation = function(classname, state, conflictswith='') {
-  var anims = document.getElementsByClassName(classname);
-  for (var i = 0; i < anims.length; i++) {
-    anims[i].setAttribute('fill', 'freeze');
-    if (conflictswith) {
-      var attr = anims[i].getAttribute('attr');
-      var siblings = anims[i].parentElement.children;
-      for (var j = 0; j < siblings.length; j++) {
-        if (siblings[j].classList.contains(conflictswith)
-            && attr === siblings[j].getAttribute('attr'))
-          break;
-      }
-      if (j !== siblings.length)
-        continue;
-    }
-    anims[i].beginElement();
-    anims[i].setAttribute('dur', state ? '1s': 'indefinite');
-  }
-};
-
-/** Callback for when a diff checkbox is clicked.
- * Animates the diff and, if checked, unsets any conflicting diffs.
- */
-var onDiffClick = function(target) {
-  setAnimation(target.name, target.checked);
-  if (!target.checked)
-    return;
-  var row = target;
-  var td = undefined;
-  while (row.tagName !== 'TR') {
-    td = row;
-    row = row.parentElement;
-  }
-  for (var i = 0; i < row.children.length; i++) {
-    if (row.children[i] === td)
-      continue;
-    var checkboxes = row.children[i].getElementsByTagName('input');
-    for (var j = 0; j < checkboxes.length; j++) {
-      if (checkboxes[j].checked) {
-        checkboxes[j].checked = false;
-        setAnimation(checkboxes[j].name, false, target.name);
-      }
-    }
-  }
-};
-
-/** Handles restarting animations when a page header is held down.
- * Also updates the history to include the page number.
- */
-var onHeaderMouse = function(evt, down) {
-  pushHash(evt.target.parentElement.id);
-  for (var tag in {animate:0, animateTransform:0}) {
-    var anims = evt.target.parentElement.getElementsByTagName(tag);
-    for (var i = 0; i < anims.length; i++) {
-      var hasattr = anims[i].hasAttribute('oldDur');
-      if (down && !hasattr) {
-        var olddur = anims[i].getAttribute('dur');
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- */
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-  // TODO: determine if it's faster to do this via css variables, in order to
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-.highlight {
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-<div id="page1">
-<h1>dragonclaw/page1: TABLE OF CONTENTS</h1>
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-<text stroke="none" x="150" y="-150" font-size="24">THIS WORK IS LICENSED UNDER A CREATIVE COMMONS ATTRIBUTION 4.0 BY LICENSE.</text>
-<text stroke="none" x="250" y="-25" font-size="40" text-anchor="middle">1</text>
-<text stroke="none" x="6279" y="-191" font-size="30">DESIGN:</text>
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-<text stroke="none" x="7154" y="-191" font-size="30">DOC NUMBER:</text>
-<text stroke="none" x="8007" y="-81" font-size="30">FLAT:</text>
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-<text stroke="none" x="8462" y="-2750" font-size="40" text-anchor="middle">F</text>
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-<text stroke="none" x="8462" y="-1250" font-size="40" text-anchor="middle">C</text>
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-<text stroke="none" x="38" y="-2750" font-size="40" text-anchor="middle">F</text>
-<text stroke="none" x="38" y="-2250" font-size="40" text-anchor="middle">E</text>
-<text stroke="none" x="38" y="-1750" font-size="40" text-anchor="middle">D</text>
-<text stroke="none" x="38" y="-1250" font-size="40" text-anchor="middle">C</text>
-<text stroke="none" x="38" y="-750" font-size="40" text-anchor="middle">B</text>
-<text stroke="none" x="250" y="-5450" font-size="40" text-anchor="middle">1</text>
-<text stroke="none" x="750" y="-5450" font-size="40" text-anchor="middle">2</text>
-<text stroke="none" x="1250" y="-5450" font-size="40" text-anchor="middle">3</text>
-<text stroke="none" x="2250" y="-5450" font-size="40" text-anchor="middle">5</text>
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-<text stroke="none" x="4750" y="-5450" font-size="40" text-anchor="middle">10</text>
-<text stroke="none" x="5250" y="-5450" font-size="40" text-anchor="middle">11</text>
-<text stroke="none" x="5750" y="-5450" font-size="40" text-anchor="middle">12</text>
-<text stroke="none" x="6250" y="-5450" font-size="40" text-anchor="middle">13</text>
-<text stroke="none" x="6750" y="-5450" font-size="40" text-anchor="middle">14</text>
-<text stroke="none" x="7750" y="-5450" font-size="40" text-anchor="middle">16</text>
-<text stroke="none" x="1750" y="-25" font-size="40" text-anchor="middle">4</text>
-<text stroke="none" x="2250" y="-25" font-size="40" text-anchor="middle">5</text>
-<text stroke="none" x="2750" y="-25" font-size="40" text-anchor="middle">6</text>
-<text stroke="none" x="3250" y="-25" font-size="40" text-anchor="middle">7</text>
-<text stroke="none" x="3750" y="-25" font-size="40" text-anchor="middle">8</text>
-<text stroke="none" x="4250" y="-25" font-size="40" text-anchor="middle">9</text>
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-<text stroke="none" x="8007" y="-116" font-size="30">PAGE:</text>
-<text stroke="none" x="8007" y="-192" font-size="30">REV:</text>
-<text stroke="none" x="38" y="-4750" font-size="34" text-anchor="middle">K</text>
-<text stroke="none" x="6279" y="-115" font-size="30">MODIFIED:</text>
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-<text stroke="none" x="4750" y="-25" font-size="40" text-anchor="middle">10</text>
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j0IA1dgxbuQDqQQdzITE6XI5c/mBsb36YAvod22Z/cS925npEapHJJBbUFx11e783tuNqoirXWf+H8j8zio4hoW8j/5ot9iLfiUfS3v+EcDE61UTXwprbSv0p4WxQnqPJn73OnkfnFfYXdlKG/N/pvIxQXEgVv8AnflWgueQPzscEWu7fRAYA9XvtoHkEoJ2CdL66e87aBn1e8RXInrzrWvzHdqK70Sm29gcGJbb3n9A22rjXcGQIBNg5O5DcmPMjbTziC68KE10NdtfSxsa0vfWl8NGbo5Pyck9hcOddYmSjm7jQWcDS7OBrdyTYWdhFvdfrau+unyOu4qqgGwSCRhe+vXmO1rc7EvZ3sRkhOxGmgHc3L6HS5u+ju4tzjteg/x056a3oOZwbn3u2z3LFm7b31vGQiW91WcbWsdhyY77++LW8/civOvTmOnVXkL6NbnTXv1PIch5mMtCGA5gWbYWLA8mDEnXoItrjmwNSee/KprVI5epucV1udNnbWzH4gCx+EZEtBVtb3Wa3+Eb8z5AfQ5K4l594W5hhs18OM5ZlyRmSCUksTrK06j5LHlCHEuGHefgXmVRME4UAREDEh6DimiWYlh1pS2lZlFiFbhs9NTh9XU0VSj8s6mmrkrAseElChxJV+8hQUhQspJBEfLzFlTLecMMm4JmnAcJzDhU8K9rQ4xQ01fTlZSpPtUIqZcwSZ8sEmVUSjLnyVtMlTUTEhUZxOy77cfMsmdg8r9q7K4zXLVqhYdnihkKXQUszFCXDT8TmbJzSoSRzltZWIl2LywrL78G0w40xl6bvRLfuO6Mt+MdTKKabM1N95l/hAxKilolz0X4VKqKQFEmaCSCVU/sCgJIEmaVDh89PF/+j1wmvRUYx4M4wcGqkibNXlDMlVPq8Ln24kSsJx1Yn4hQKTwmWiRi4xKXPXMQuZidEiUv2mwxwo4x8LuOeUYTPfCPPOX8+5Vi1BoTSQxgeVBxZYZiVS2by95LMzkU3Zh4iHeiJPOoKAmkM2+yqIhGg4jvd64biuHYxSprMLrJFbTKLe0kr4ihbBRlzUFpkmaApJVKnIRNSCOJAcR5jZzyLm/w8xudl3O2XsSy5jEgFZpMRkcAnyeNcoVVDUyzMpMRolzJcxEquoJ9TRzVS1iVPWUKbsvH0I4nDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEW+bTeVSCVzCdz2Zy+TSWUQUTMZrN5rGQ8vlksl8G0t+LjphHxbjMLBwcKwhb0RExDrbLLSFOOLShJIjmzZUiXMnTpiJUmUhUybNmLSiXLloBUta1qIShCUglSlEAAEktGTRUVZiVZS4fh1JU19fWz5VLR0VHIm1VXV1U9aZUimpqaQhc6fPnTFJlypMpC5kxakpQkqIEa9nbW9tPCSt6bcN+yB9mmUcy5FS6a8bJzL24mVMOoSplZ4dyGPbUzNnGniS1mbMUKuUOFhZl0inEDFQk4T0Zm/wAXEyzNw/KvDMmJKpc3F5qAqWk3STQSFhprK0qZ6TJPCfZyZyVImj028AvsET6yXRZr8bva0tNMTJqqPIFBUqlVk1BImJGaMSplpXRImIACsKwucK1ImJ+9YjQz5U6iOvFmXOuac95gmebM7ZjnebczzqI+0zef5jmkbOZzMogIS2lyMmMwefinlNtNoaZ77pS0y22y0ENNoQnoWqq6qtnzKqsnzquonK45s+omrmzlq0da5hUtQAAAST+EABLAcMen2D4Dg2XMMpMFwDCsPwXB6GX7GjwzC6ORQ0NLLKisok0tMiXJlFS1KmLKUAzFqVMWVLUVRBbd3Brz1rW1lDwA0tXWmoxzcC7H909N2GhB+TxlzJb3sW+gCzNc6i+8T2n6UANvUgAV8+hHxU0BrXFH1e3I7HX07EveMZSHNwR77fDz6X0aLg3EV3vpXenKpFDXrfypUeos+vw7G+vTqIgVLcP0t7yWuxG4Fix7tPQ9epNhvvfQ01A9RS17VEPfrq4BvyI52A0Lb3jHVJbTTz6bO40a14ltxJ1rX0tShJ0PPVQB3NxamjA37uDfkp2fo4tu0QlDOW89jzfQsOxb3xJTFCl/6EaUJAOnhf5CpJ69mf4c+bkdoiMoEX89i77h2PbhIHrFYRKdK0Bvag8LUBr+umDvb8J53+THf0+Nhk9CknRiCe4uAH0ZnjmIogUqelzb5fWuKW5I9f8A0w9kf7yh0OvkygB5vH4YkDc1J3+tx60GK6ahIfkf4D+EPYF78XTi0fyMUjFDb5AgHxHdFxzGv0OSW7aDnu5JDe/0i8SgNgCGdyfh+FzvoTEZUUb6aa69TtTyJIGB1253ueQIF2G7+rXi8S3Fn7aeRuHs17u+sQ1v13qfKl6UpanQgA8hzBvdzJ+AOltz3GrzJlH1Hx3fe2rDoRq8Nx8CtTW1tdq02BO2pHhagPrqTd/K3QB+m/YmMhEoDYHk/L383vzG5D292I7wrXUa+VqUAqBsAQka1w3vci7Db5eZbpGQlDdXt7/W/IW2L2e3rdrXoRU+VgbW8BTcUBoTVuZfcC1uWwJ3+g8ZCJZOum4/W/mw6RbnnwK/FsamtzrqeQ0GpN9CMV199+WnrrsDpGSlLWDM1ybdPIDlfX1tTzwuSdLgaA0JvWlh09epn6DfuXfbzDX9L5KEaM+tz2fUPpfT1e4i3Ou/vKPgnSvIkaV5eHPSptYfm+HO/LmT+XvGQlOw03P1qdgLnSOz+C/aE4v9nTOcNnzg7nmdZLn7K2PtiYCIK5RPoSHWpxMrzLI4gOynMErJccJgZrCRLTK1/aIYMRSG32/q4RjWKYDVJrMKrJtJOSU+0KC8qelJJ9nPkl5c+WXICJqVN+ZJSr8Q4dnzwzyR4o4FOy9nrL1Dj2GLTM+7mpl8Ndh86akJNXhOISuCswyrHCl6iinSVzAn2U0zJBUhW032GPbA8Ku0a9J+GvGtuU8H+M8X3IOAiXYwscOM9xpLaGmZBNZjELfy7PYxxakM5ZnkTENRTqWmZPP5rHRaZZD7H5P8TsOx0yqDFhKwvFSyEqKuGgrF2AEiZMUTInKNhTzlEKLCVOmLUJY8fftD/Ygzj4Wors15BVW54yHJ4p9TKTI9pmnLtOONS14lR0spMvFMOkJSFLxbD5MtclBXMrsOpKeQqrm5l8dpxolDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR03x34+8KuzZw6m/FDi9mmEyzliVJ90wlX+sTefTV1KjBSDLUpbUIqczuPUhQh4OGT3GWUPx8wfgpXBxsdDfLxjGsOwGhm4jidQmnp5dh+9NnTCDwSKeUPxTZyyPwoToAVrKJaVrTzrw68Ns4+K2aKHKGSMHnYti9YeOYR/ZUOG0aCBPxLFa1Q9jQYfTAgzJ808UyYqXTU0uorJ9PTzdO/tze0t4udsmcRmW4NyN4dcC4KLBkvDWXR6vez9MJFCIgp5xCjoYtpzBNy61DRcNKAVZckDsPDCWQ0VM2ImfTLVrOWfcTzVNVTpK6HBkq/ssPlrvP4VcSJtctJHt5hZKhK/zEghJlBSwZ033I+zz9lDJfgXQyMVnIkZn8RJ8kivzVVU6eHDTOk+yqMPyxTzgo4ZRhC50mdWFsUxKXNm/e5smlmSsNpcdjbwNKkA0pWtajW4G/I89KmuOA3HbXiYeY7dN7ux12hKeVxyvppvr1G3aLg09cA69b8/MjXqAb3IwIGx9N9nYvfnbXRwLQKQDcNo2nbv1d7c9zFxaiCKGvhU263NK6mx02odLXdhcdGt1/mCzt0EYypbbB2FnsdmflewOruHie2+DS9KC9BUelPhtrSosLVqQJuxHO2r9iLG3meQa8KpbliAPL3tt5ExObf59L+OuoA8a60p3RW1GbQtfTV/W+2x0jHVKIv57nV9x73sGd9CZaIkgWOl6UH4ingbDU0OHMkEdRfr+puPe0QmW2o+Y+LbDQjTlEoRXPQWrUHahJIFwKUp3vMXwBc6g67s3kNR37veLDLB66/p79y46CJCYoGgrem4qBtyVc05+W4XOzE6nXTmxB+P6RqkhtH00e/lcevxiqIpJ/etzH+O53pvc1rioNnuG5vt3ufreIzJS7Eatbf1c66/zjl9qT/Fbyr9PxxbxD+8fT/0xd7D/ABNy4v4/KOKopINQq2p/wr+FPLFwIZxcDkL+n16Rb7BIIDeRu/m7RTVFC97EWIFBvb7oF60qT5nTFOdne4f+JLeQH6SCSOTX0vbtoD6/xjqixcjn5a3Gh0prUDY2xU6XYON767cree8XiW3IXPy9x5OGiMuJJ33ItQnfSgNeYvzA3GKO+jq06Bxv6jr5AxIEasH1976377h+8RFv6XrS177C42150NQOZw7lg2g28xf0A0bm8yZRPIX2vz3Fr3ve452MJyIFNb35gX60qdxal9b1IrYWD9h/HnzOu0TJlAbcu+2/e1rcrxAdia2FKCvLTwvSgprf0FHfcaM/y09G31EZCUGw9B0HnbkN32i2uP8AUlWo0sbm1b60+I78jQmoD6lunnz+LPvZQ0yEyxvttyNrvv0OzDqIgOvU1uaig5G/qrwA1BoK3qHOhsDrsL+TsRvfrYNOlPTqBz/QbP6RbnXtSTUn1FPW3hcU7wtfADYeZt2fQFrOdBoOpnRLe5Ftg+xOpfQdSXIJ0sItjz9KitTy5aXJGxrTQi1jW+Lm6MO5JJLOAzO/Nj0LM2WmXuQwA+hr0sN99CBbXHKVNak/oW0rTQCwHTW4czZOybXe/n0HP35aUaOGa4HwNjryH72pswGdP2eXtk828F35Jwf7Uk0nGfOEQU1LpDxFfEROM9cNYYpbZhoaaLQHphnTJ0ItJqw99qzTI4R1aJVEzeWwMsy2x3DknxPqsLMrDMwzJlXhjiXIrVAzKyhTZKEzCHXVUqSNDxVEpJPslTJaJcgedv2nPsL4LnxGIZ38IKOiy5nYhdViOVpZlUWXc0zXWubNpASmmwHHqgEfjlmTg9fNQlVZKoaqoq8VmbZWWM0Zbzrl6T5tyfPpPmjK+YIBiaSLMMgmMJNpNN5dFIC4eOl0ygXX4SMhnkmqHmHVoNCK1BA2MkVEiqkyqimnSqinnIEyVOkrTMlTEKulaFoJSpJ2IJEeMeLYRiuA4nXYNjeHVuEYvhlTMo8RwzEqWdRV1FVSVcM2nqqWoRLnSJqDZSJiEqFizEGL7iaPnQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEeZ+1b2r+E/Y+4VzHifxTmhSkl2AynlOAcZVmXPOYvcl2HkUghHVpClU7r0zmT/dl8mge/GRzqR7lp/wCDmLMWHZZw+ZiGITLXRT0yCDPq54S4kyUnXnMmH8EpDqWRYHtjwb8Gs5eN+cKXKOT6QEsipxrGqlMwYTl7C/aBE3EcSnoBYOSikpJb1NdUcMinQTxrl6Qna17Y3FztlcS4nP3EyZmHlkEuKhckZClsTEnKuQ5K+tomBk0K6sh+YxqYeFdn2YX2xMJ5GMMqe+zy+Elstl+pmZszYnmmvVW16+FCCpNJRIUv7tSSSQ6JSTZS1sj285X4pykgnhQiWhH6BPBbwMyT4F5TlZaylSe0rJ6ZM7MGY6uVK/rjMdfKStqivmy0/wBnS05mzpeG4dKUaXD5MxYl+1qZ1XV1XmRp8ineJpXWugtrffwoTelaU42bjqbkEb206sebkM4eO21oJsBe22vXQk20I25OXuLb+lTpoR4358x56d4iuLWZ/eNbuw2Fxz063aMaZLBdxcjVnO4uBr0I72ie2/sTVNvCwJNL2/AjUACre1jyPI9+h3f0JIx1oI1BP+tc8m2ueelv7zRObfI0VXoTc33FQDe9qbdKUsQAf487Eb+rEODrEJTzD9W091ux8xExESLCpr/Ca87GlajTY8t6UMRobPd+m73csW3LbjUwqlPYM2rFtQ3yDbBnB5xObiiki+m42v41pQUAI/PFuj7Nz0HZ9tLAjQWERGWRe41sz8+j+XxtEtEWDavmDQ6a2JHjYDkNsVv27HrpcaN1fvERlf6vS1yQzcrAkkgeZGsSUxQ2URcChItToFUAtpT8Kj1AO9wwA8wz+lvWIlSknu99vgzn6N7xVETWg7w61NSegCiKDl41vinCLMS3QlvrtFnsfif5flfYtr+tUxJtcX/m/JR+dMPM+QB+CYtMkjR/R/0j9+19b+Ip6Vwe373fhL/BvdFPZHr/ALp/WPz7Sb3FP7V/TvfQnDzPmAPiIqJJOpPmG/WKZiQL98a6A0VvUnu18z41G+Dbkn1Ye5ou9h138vh1vo3naiqKA1UbEaGh8RVWh8Dv5Aw0A8ruPi58+8XiSnpcht/i/u98R1RdKivKwIIpXqRbla2lBatbuddd25+evUv21iVMo8r9WsPQHvaIbkWTvTauldKam3gBbStDhq372thps47Wu5v12kEo8tG2a2w0cNfbTRrtDcitfiJPIE/SpVrrX64qxO7Cwsz3fUm3OxvpdtJ0y25AcvPn/E9ohORBpc0HKoqNdtE+JNbeJFQwsL7Wvc6ue/q+pcPKlADMG6nduXPsPSILkRYgHfXcn1uelun8ogfvf7o5B7G3qx3dyNZUIJYi1tSzXbTyO79ogOP2N9qE2BN7bACmnTkK0wPL0A6gdzy/hGQiUzNcnV9HDEkancXN9QNmtzr9ahJN979NL3I1vpzsMXAMLhydADc9xytt5xlJltzJ9dXL30Gl7WFrOIgOPU36nQ16/W50Fr2pUjdTPsAOetr7u2z94yUoGp+L2u7OB5ksAX2i2uv1qEkcqg2A3obV6k610oKYuAIDm+4HXncga792JiZKe7bM5Jt+7bf++zagbPbXXtQDrUk67XoQfnvat7YrqfhyG258tXAta5OShAdy3YPz7EsS7q8hzjKB7OX2n2f+xRmmEydmlc1zz2c59MkqzNkkRAiJlkx6MiAqNzdw7+1vNsQsyQVuRc0y4t+Fk+aauIecls2ch53C9hZIz1WZWnppqgzKvBJ0z+3pX4plOpShxVNEFKZCw/FMkcSZU+4JRNInDUX7Uf2SctePeETsdwdNFl7xQw6lIwrH/Z+ypMdRTy+GRgmZvYoVMnUiglMmkxYInV2EHgVLRV0aZmHzt2jhtxJyLxgyLlniXw0zPK845GzhK2Jvl7MMnf8AfwcbCPd5K23EqCIiCmEFEIegJrKo5mGmcnmcNFyuaQkJMISJhmtpaGupMSpJFdQz5dTS1MtM2TOll0qSrYiykLSXRMlrCZktaVS5iUrSpI8Cs1ZVzDkjMOLZUzXhNZgeYMDq5lFieGV0v2c+nnIYpUkgqlz6aolKl1FHWU65tJXUk2RV0k6dTT5U1f3GMqOPwwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR0D2mu0lwy7KHB/M3GXirNfsMhkTX2aVyuGKVzrN2Zopl9Ulyll2FUR9qnM5eYWhsrKIOXQbUZOJrEQUol0fGw/x8dxuhy9hs/E8QmcMmSGly03m1M9QJlU8lP702aQWdkoSFTZikykLWnsjwn8K82eMmd8JyLk6j+8YjiK/a1dXNdNBguEyVyxX41ic4f5mhoZcxKlBPFPqZ65FFRyp9bVU0ibofdrfte8Ue2RxcmvFPiTHFiECoiX5JyXBRLr0gyDlb7Qp2EkMoSpLSYiIKe4/O5y7DtRk9mXvIx9thhMJBQeo2Zcx4hmfEpmIVy2S6kUlMgkyaOn4iUyZYIDki82aUhU2Y61cI4EI/RV4K+CWUPAzJNFlDKsgTJxEuqx/Hp8lCMSzHjHsgifiNYQVmXKB45dBh6Zq5OH0vDIlqmTFTp8/zU0/TRVR0uR89fGxrc0GOPkP0Ojj0v31bnpHaykN08mDHUC1jrYgC2jl4uDT+l97bU3FRXcHqNyBQYt/xbaEWt31BOhdhyL6wlAILgfBux2JY80nyETm3qfdPltS9ed9qjatb4oX0Nw5Lj8wvt56t1iFUvZn6al/gQ4LNd9jE1uJA1NKW2pvSm1DtyA0xaQ9wXfbfzH6d4gVL152J/5dX3tuxc67xObiRqTre1NjXStNa1rptbFL6N5HXTby+XSMdUndiDa6R05M/YAlrA7iJjcTWlSFaa3p1uQfOu/UAGF2JBOr3A+f0LamIVSjsHblYvyIZh5gbXiSiIA/eINKUrUDmLkK8b1A3GFxdgW1Zja50u3kGB56xEUajTooN79PeLxJREkalJ5XoedQDTbS/mdcUZNthvqm/v8AePIRYZb7eYD9eo131ismKvevzpodaEjwofywZtyX5tb0+Y7RaZY7bsQ7RWEWB+/6kA/8wP8Aj6OEsCwPViG82Pu/nZ7Ht0+gB9e7mIux+Ktbgk976rA+WDbkC/Ignz3inse3qf0h9q/nT6YRb7E9fUQMXQfepzNe74aLp8geuKEbgDzLHysTF3se3qf0jgYuv71TrY1r0NCTTT8N8VYs9g7bG/mwGmnK+sV9kOmt9/K4Px9IoqijyPjp6VKRTwv47G6kX6fME+5vhF6ZYGxJPIfFr+/pFFUSdikdK6enjuQCd8Pw9SBp+8/V9fcW3FouEsD91u9hztoPSIy4kH94k6G9K6V0NbbiopvbS697Ad226aaF9ObXiQI0ABPIJHfcsB7/AIRFXE63AF6gGh13oeQ5nWtCLClupO2w9NddreRiRMpXID3qPqO2ib2iG5E9dOZpcVItW1qCtTpfTFb6Dlone7F28zyv1MTpk6G50ub2cC3TdierNpCciamxrqQa2pXx6UoK72NsG5nowufTb5d4yEyujltGc3Ggb4htr3LwXH/4j0pWg0pz2uNTbbF1+wDf49LdrdmD7ROmXpy3FidTvcB2e7nV7awnYim9AAbDXXlXrva+nOoBtw8hci7HZ929G7XmShm66276vuNXOp0dr25187qoPG5/PTpbrbFzMLa8z9CwezG0TJlk7A+Thg/+8Q5/1Q1g0W91+xJPdT6E/P6cvLAB/Q337gAENbpfZnjJTLbvsdd2Y89LAWtfrbXX6ggEhNNtTr1ubbGgvfbF2nUvp1drjnYW7XtGQlF3ZzybqGBt2HCPNtYtzr1rWGutyL0vurWh0Gmwxcx/xE2G4A30sGcdA9umQiW1zcsWcWHlt29GvGUn2YntLs0diHiI3lbOEVMswdm7PM2Y/wAussJXERj2TZlEe5hDxFydBhSgibwjDTCMxyqFbCM1SWFbhnEKm0tkUVB9g5FzpUZWrPu9Utc7BquYDV04dRplqZP32mTtMCQPbISP8plpCWMyXLWjUL7Wv2U8I8f8sqxfA5NLhvipl+jmfs7ixTLky8cpZftJ37L45OYcVFPmKmKwqsmqKsHrpy5qVCiqcRkz957KWbMt57yvl7OuTZ3L8yZTzZJpbmHLc/lMQiKlk5kk3hGo6WzKBiEfC7DRcI+080qx7qwFJSoFI2mp6iTVSJNTTTUTqeolonSZ0shSJkqYkLQtChqlSSCD1j89uM4NiuXcXxPAccoKnCsZwauqsMxTDa2UqTV0NfRTl09VS1EpV0TZE6WuWsXDpcEggn6HE0fMhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPm85Zwyxw+ynmXPWdZ1BZcyjk+RzPMmZp9MnFNwMokcmg3o+ZTCKUhK3C1CwjDrpQ02484Uhtlpx1aEKhqaiRR086qqZqZNPTylzp81ZZEuVLSVrWpnLJSCWAJOgBJAj6uB4Ji2ZcZwrL2A0FRimNY3iFJhWFYdSpCqitxCunopqSmlBRSkLnTpiEBS1IlocqmLQgKUNCX2jHb3zX25uNcTmBpcwkvBzJT0wk3CHJEWoNuQMndebTF5qn8K08/Cqzdmsw0NFzUsuPIlUEzLcvw0TFtSpcxj9Sc65sqM1Yoqc65OG0pXLwymVbhlEjiqJwSpSfvNRwpVMZ/ZpEuSlSgjjX+jX7L32ccG+z5kKVhi001dnrHkU1dnbH5IKkT66WhRk4Ph05cuXOGCYMJs6TRcaUKrKiZV4nNlyV1iaWm8AtPmxSfEHfQ2ob2pWtz1rTHDS99rs/kWdmc3Lkh+mx2SWgj8wbrz0IJ73Lgk66tFwaiATYlJ0psTa3npTX6YtKWfkb2AY7aWZ20tpoLxCpHY2azX1a+4tobsDfV5zcRzNDzGn18DyItca05vvrdxaxvt1DB/K2OqW7tf1s3kCN+mo7Tm4jrUcxep8zTzNPle0pGosfduOXw6FogVLN+Q0dgdNtAeX7pZrOLTURANP3q+up2JrfbXyIpihDM4Nt9/W2lvzDnuLxqQNhfS9jqNCwLaHcM/nKQ/yVytt08vECu+BvuCG/e18jb42di0RKl6NZnNx15gM4dtLEsWiUiJNb3puDS/M3pXpXU7YtIDaEdWcdL6t6+cRKla27FnvewIB7fuuAwsIkoi/5iP7XOo12ANL0rp4YMdmc3cH5M7jW3pERlO9nZ7FiG32dx3ZmiQmKFhUXroaevxU7vQctNiuHJfXRQf4hn9OkRGQNWHMkO/lY3625iK6YobE+RvptcW8zXyxTlZOnb1uL/reIzJ6q0u7KFy7X0Onu86iYutu95X73zWflXywYDUK9fkRaLfYm9rD+8hh/4R8Y5/aa7p/vC/4n1xUEDVS+zhvKwinsTf8AJ5cXnZwB84faerf6/u4q45r9RD2J/wBX/m/WBiqDUD+yNNd7aC9xQYtLFmKzfQkegsTf6eAkl/3OliTfubeUUzF7d+3ME19e/T+u2K8P+qfM2b0A84u9iXYv5It70/MxTMUDbvHxJoDfoTflf02o9tE69yPV+bP6xcJHPj10sB/ugac+ZHrQVF0uSOdzU7XNTfpQfWuK3szl3FgQOwt0csIvEgBrJ3D6vqG0Atvaw2JiMuLuaEnw8OqqbUNPIYMGF0jnd/cAfc8TCVsxBFyNANuQ73dtS4ERlxKq6gV5kk/M9aHWuKtbQ9XZI8+e27nnEqZVzbhboA55mwN7HQ6O1oirfF6qJNDre2umwGtaDxvXFe5A6Is5Gz8+nbmHlEseYvbp1Zz6J20MRHIrr0oLmw6HlzNNCRioBZgANn0P689eHbQOIkSgH1u2j2uTsdTcg2dtohORBvVQSBWlSQT0F9/Ac6jarC5Nz1DAHsWfu/K8TBB5dmZrvdyLtb8ovzNohLf1pbeqvL8OeK3t8dBaxtvt6guYmTK5gDoBb06PcqN3cagRAdidaVUbipNhWo56VFDtS3TFWY3ccyfl5Nbz3jITL3Nn6G45aOpujBuhvAcfuaqqemnK+tRa4237wvi/UE6AbnVruNhd9Bbn1nRLJIYMOZcFuQIFhzAuw8otzz+p73gNuVDU62+7S+ADizgalRtbcW1G/KMhCOQHU2BHpoNTYvraLe8+b1J3oPWm4AH8uvnbF4AH5fXfy09dLaF3jJRL/ugPqTy2tbfn6g7W9x4nW2thpf0t0xcNuXf+frGQEgaX5q0FtQLO9/i5a8Z/vYqe0te4C50lnZV41z/ucEuIU6LPD3MU1fQmE4V5+nMSVJg4mMeWn7DkbOse6GI/3hXBZfzREQs9UICXTXNUyT214aZ0OFVKMBxKb/7sq5rUk6YocNDVzDZJUWKaapWWXqmVPUmaQhEyomR5tfb0+yojxGwKr8YMhYaVZ/yzQBeZcMo5ZM/OOXKGUyp8qRLSfvGYcBp0cdKEAVGJYTLm4ak1NVR4NSHcxxsdHhbDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEai3t7+3/Mc0ZqhexrwtmgGQ8rRjE240TqXxDhZzZniWRKXoDh8HmSGHpTkR4Qs1n7ClRSX84vS6GeagovKCjF6/wDipmpVVO/ZuhmPS06gvEpiFEioqkKdNI4/CZdKoJXNBKuKpKEEJVTni9WP6MDJPh7mCpz/AOJ6cWoMczxknGkZLl4KkJXNyfJxPC5dbNxmaJiSr71mCSqvwegrJASink4TmGhE2dNnVsmj1wYaLS6AtKqcxXQ2sRenjoa1NjfpbZtRsDr6m++9x6AeywCVo4geJJt/rJIsQbuD63u5DRc239AbG1xr1rT71ieSq3OLWO1xuk9NAH72e2hiJUvkxHLtpbnfZ3G0TkP1ArcaVGt9PDlQ2rzoa2M+ljcN9fMWIckWiBUofu668O36HZ7A6dHnNRBtcKHXyG532Oup7tzWhGxt+unpz1vdtGgXLvcMxfdvdcc9xtyMTG4kHQ92lqbddh86HQ60xRrWsG2v/EEndw+1neFUu2ludr+YsexY9dzMREfxAa6imxPIGnlrvhd+eum/kb78tRY7RCqVt7j5PYkp5lwQ1nu0S0RPJQP9oXHrQ1rfXagoMUYEu3LQsdrFvLW/SIjLIsNfo7l2D2ZRbV9olIiik3qOWh33JHjoaaXtTFAkjQ9gRyHPTU8iSzRGUNpsNrH38OnqfjXTFUpcHx+ZFQK9L05Ypw7FI2DgttcnQn05xGqWHDtsC9m83B20F+Z3NcRA1FLjYDTyT+tcU0s5SDzct6gN5E94tMp7t1d9ttSfifS5qCI0+MgfXyNaacqdNcUtq6S/NPvtf1iwy7a6mzjb/e+UVBEqFfj+X5U/HyxUgbpHrwjyBb3WiipWmnmNNLaa8/KP37Ss/v8A1H1wb/U/5ot9l0T6fwjl9pVsoA86p+dACfXDhP8AdJ6FQ+TQ9l27Ekj0NhHH7Uv+P5HAgDVA/wB6HsuifT+EcTEGpJXbnQDXyP6NjhoHZIHV1e8P9d4v9na3nZwPcG159xpFMxFtSdaHUEb7H9a9DgaKHkken84r7K46i3l1KlbdYpqiQKmwrWlh+Vb3HP6lrzVY9A+3T0J7ReJYGoax/e1Iu9iPmxuzRHMWBeo8hWo6Gg0Ntz5UrUAuGAS3Nn63u/S45ReEMxHO4ACQH1DkgX2ILcn2jqiiRWlK0uaDoa0AFN960pSutWfUk9gQC4+nYs+0Xpl9O+7jfca7gkjQsYiLih/FU8gN6HagA06keGKhrs3xPmWtrub83IiRMpx33Oh3fZLtve3URFXEHmEjrr0008rbHBuu/c99hzt6sLRMmULFr8/n7tQDq7m8Q1xA2+Lck+PM0PhUipvsQbmA6ak6G+psGZzsWA90TiX3HxNr2AKn0OwuO8QXIiv3lVpU0BNtbbeYF6Cx5VDtYeZv0YBn32BvqREyJZuwFtCQlvIaaWu5O+rGE5EGpv3dSANd61tbxN9BYgkVAfS5e5Onf4jd2cGJkyu6j1e3635sLk7xBciDse6KG5qa602BJryoBehG1wSHc/iPJ7DTV323ubuxjITL04mJFgAAW6PfezDUb84Dj+tDpqT59La6A1rypTF2vXk2nxLs2pto14nEsMH20SOnx5+93iGtwqNvX6/4m9LYrErNbQA6b7G5bTmHd72uDSwh7oYQjdg9iV7Qd7tLcKXuzzxUnRi+N3BWRQf7GmkcqsbxD4VwqoeVS2bvxBdWuNzJk2IcgpBmV95th+YQEZlqcrdmkzjMwxUNst4Z5uONUBwivm8WJ4ZKT7OYr81ZQJaWiYS54p1MSmVOJYrQqTMJWtU5Q8FPt8/Zql+FWcUeJuT6AScg59xCf9/pKcf2GWc4ThNrKqilyglIp8LxyWioxLCpaFTJdNUyMVoUoo6SThkmbnYx2lHnlDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR4I9oz2uobshdnaeZolMQj/OhnYxOS+FUJ3YZ5UPmONg3Fxea4mGiUuodl2TZeXJutDkJFw0ZN/wBhyaMabh5suJZ4nnLMIy9g82fLI+/VRNLQJ/CSJy0ninkKcFFMh5hdKkqmeylqAExxwPxEzanKOXp9TJUP60riqiwpDJJTUrQSuqUlQUDLo5TzmKFoXO9hJWAmcVDRTz3LIvPEDNXpjFxUyn0VFRE4Eyj4hyMjY6cRDjsRFREdGRTi34l+ZvOvfa4l91Trjz5inVrcSe9q3VcU8KUtRXMWpUwrWorUpaiXKlqJUVLLlSieIkufxOY+f9hH7UVX9l/7QOCZxxSrnKyFm5UvKfihIXNqDxZcxKrQtGY2R7UzsRypiRlY7K45M6bV0cvFsKlLp1Ysupl+UWnHoR1QKVoUhRQ6y4lSFpUhRStC0qopC0KBBCgFJUCDS4x8g2JB2t6fXyj9lNDW09RIpq+gqKeso62nk1dLV0k6XU0dbSVUpM+mqqafJUuTPp6iTMROkVElSpc2UtMyWVIW6voGItLiQpCqg2IOoIoCk7VHQ1NiDocUb3db/rtfXrrH1xwTQFJs731bdiHtyPufVVwbiL6kU0HSx8fWoxQh9Q7eR+WtrWEWLlm5I4g2o131v03t1vE1ERShNb7g9AK7jzsd9NbCk3ANm/KfkSe+2u7h4gVLOgYi7A7e8aC1iNdNIloiK0FQflTexPqTWpppcYoQAzuk+ZGmo823tERlB3/KexL6eZ3/AL3SJSIihFFFJva522FjprU79MUY3txc2fs40c21YjnERlHVgW04SAbau3/l9SHiUiJJ1orS4NPqAa9KfXFGdwe1x7jv7jEJlgPqNQxGg8nHuG8SERQ5qSba3+RFaDwvinDq3xc+QN28ojMvo/bV9WsSP+XSJCYqp+8lVib21526+OKM3S/JvXr6RGZQfRux79U38vOKwiP5TpqFVJ15jrXXrrfC9tfJrdXIB+tOdipQ6HysPNhflc77mKgiqAXUOmv5fj44HdwCOxJ7/LQ84tEp9DfV+I99OJvdptFT7WLVXWlqd38e6fw6YoyW095T32vbtAylbA+/z/d9PoRzEWP4kjxA/wDcJxayb2T/ALx/T4PFplKGpV6J+bfW0fpix/Gg00sPl8GDJ5J/3z+kU9mf7yvRH6xwMWP4gPADrrRNPx64AA6AeSi/I7Rd7JXU9w3wB+to4mL0HfJF/wB2lP1/iMXAJ04fVJ+LfOK+yJ1cdywbv+FttDFNUTXdR86fh+fO2K3br0b5vAyg/Pp+a/rbyAikqJpsBY6q8b0pS16W8N6g/lzOvmAPhEnsgzufhs1/yW6Hv1igqK/n9B+NPxxViSW6ch6k+7SL0yunTzOx8/8AW5RHVEi9ATyJNB5bX6G2DDdreenLb4d4kTLY7PyAfof7xHqAbRGXFE1+IDoAdL2JtSniedMXAE6Am57efI6b9IkTKvoTrd2353N9WcX6mIi4i1bnqTrTpYEepHOmDWuW6emvTcajVr6zJl9QNdBfzOr6NfsBEVyJ5knagsPWmg2sAD0OKhJsWYC7m/u6XawfvEiZQayQANzy33AcdH0eIa4nUV7o1uTf8SKC1afndwvr+I+jC/16bXicS3L/AJjYcm215X6ekQlxHI+Zp4eA8q7Hli5voW+uu3SJghhcsP7o13735687XiIt4qJ1NdeVbeZ+XTFeXbTl8vj31iUBnAHDbuTr6dHOh0O9IknXCGjtZ9buT58ugYdI/MIQwhDCEdy9nzjnnns18ZeH/G7hzHLgs1ZAn8LOIZn3zzMJOZf8UNO8tzX3CkOOybMsnfjpHN2QauQEe+Ed10IWn6WEYpVYLiNJidGvgn0k1MwByEzUXE2RMa5lT5ZVKmDdKjoQCODeJfh9l/xUyNmTIOaKdM/B8yYbNoZq/Zy5k6hqbTaDFaP2gUlFfhVdLp8QophDIqaeWVOjiB/o5dn/AI3ZL7SHBjh1xw4exKojKfEbLkLPYBp1xhyLlcX7x2BnWX5kqGW6wmcZansHMsvzhplxxtmaS2LaQtSUBR3FwnE6bGcNo8UpCTT1klM1AJBUhTlMyUvhJHtJM1K5MwAkCYhQe0fl38ScgY94W57zP4f5llCXjOV8Um4dUrQmYiTVyeFFRQYlSialMw0WK4dPpMToVrSlS6OrkLUlJUQO4cfRjhEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpEe067Vjnam7TmZIySTB6J4YcMVxfD3huwiJLsvjIWWRixmLN8O226uFU5m+dsuxkPGtttxMRluDyzCRlXJclKNY8848cdxucqUsqoaHjpKMO6FoQr+1qAASl6mcCpKwyjJTICroAGlHibmo5nzJUzJEwqwzDOPD8NSFPLWiWtqirSASgmrngrSsAKVTIpkLvLjHs1YA+J8SbAeeOGHU/Ttv56x1voO513tt7wfq3QHFTLBl0xRPoRoiBmi+7FhNO4xMgkkqpQFKY5tKnxXvf6w3ElSk+8bRj509P4uIBn/MP9b5AtuTfYOY/Tx/RFfaqHij4VVHgFm/E5UzPfg/QSVZVVULKKzH/C+ZPFNQJSFKUipqMj1s6Rl+eqUmnEvAazKyDJnz5VfWTOq2nVMq7ybg0CkHRQGlOShqD5G2MePYyVNVKU4uP3knQj9eRi9NPBaUqQapOx1FLEHkQbEbeBuj6SVJWkKRoq7tfW4I0caWZx5NJS+QQakU8/nSv4fTCKlIOwVbUEgv236s7epiQiI/xB+opSviDzIrim+v8AH6bbziMywdDfkfT0tqfk8SkRNrK8v1Uc7Uv1xThHLRgCCx7tYBtfpoiVKbVPVwQfTUWfy2iSiJ5jU7G3lqB1JA5DFOFgWNmdiLaa97ObdxEZl21s37wYXFndz8HiuiK/nI+fPcaU8K9BbFOE3dLvu4Bc6+/R4jMlx+XTU/pr6cvWK4ib6g3/ALJJ6i3SvPytRuhTtuXPXm/Tl1iP2QuxULNe/oX2OlgeYG9YRG9DtXunTpoa9b8vE0YbqbbS9uYHxN4sMrqG/wBYMX7295vr25iLIp8RSK3rQemhPjfqcUAfYE9Xf4gfXaKCUW0B2DHfqyjzHKKgi66LJ8k/U/icV4W1H/MB9bRaZJ1KfeD5flJ3jkIv+e24KfrQeeuKFJGx+PwinsjpwH3X/wCWPost5dzXnJ9cLk/LmYM0xTau45D5akkznj7ayAe4tqWQsUtCqEHuqSDQg0xNIpampJTTU8+oULFMiVMmkE6AiWlREfKxbGMFy/LTOx3FcMwSStPEmdi2I0eGy1JduJMysmSUqS4ZwSHDR25B9lvtRzBsOwHZz47RrSrpcheEme321AioIU3IFAgi9dORNsfSTl7Hlh04Hi6xq6cPqyPJpB+POODT/GbwbpVmXU+KvhtTzAWKJ2eMsy1AjYpViILxFmHZl7TcsBVMOz1xxgQNftfCjPMMAACSauSNANNfDpiOdgeNUyFTKjCMSkS0h1LnUNUhKRa5UZSQPPruImpfGLwgqy1L4peHNT//AAM75bm9P3MS+jaPhorhbxWgnzDRvDPiDCRKbqh4rJ+YYZ8A2qpp2WpcAqDcgHa9McIrM4ZRw+pXR4hmnLtBWIuqlrMZw+mqEh2/FJn1KJqQ4I/Eh3Dc4+/KzxkeegTZGc8qTZRICZsrMGEzZZPILRWKST7m5REVw04m/wCzrPI/9lJ8B5gwN/T8sY/7e5GItnPKx2YY/hIF+1Xp3DlttpxnTJQ/+sMsX1bHcK67iqEUVcNeJwB/83ueBrYZSnoHWv8A1eKjrf8AOoz3kc//AFhlYnrmHCR6f5Xr9dRUZ1yTqc3ZZJ64/hdmu4/ys/HrFBXDTid/s6zyf/ZWe9dKQFR5nFRnvJH+meVBd7Zgwgt//wBdvXSL/wBt8kA/9sMrJ0/+3sKJ6v8A5WT5fh19KKuGfFC9OHeeRp/+k56TSh1/6vqaaUqAb3rq/bzIu+c8qk3d8w4Sm7uCR97e/wAGtF4zxkcm+ccsK0/+3sLa2n/zXvDM1zpEZXDHijU/+bnPZNLf/ZKff/D622+Ib1Bxd+32RR/9aZUA/wD6hwjbmTV6N59YlGeMjv8A9scqp01x/CibuP8A9LJu2gY8ndojL4YcUqEf5uM9jnTKU+PUX/Z9NCbkmo0OH7f5Ev8A/GmU+/7RYR0//bLfDTeJBnrIo/8ArHKyj1zBhQDjX/5tyNrPz5xHVws4pH/9uM9jxylPrf8A+fQYft/kTT9tMpvy/aLCP+si/wDbzIwA/wDjLKzasMfwkC77mr62t53MUzwp4ok34cZ7qf8A+pT75f6hiv7fZE/00yp/xDhHl/8ANw/bzI+2ccrB/wD94MK+JqyffH5/mp4of7Oc9f8AZKff+Aw/b7Iv+mmVP+IcI/6uKft5kfT9ssqvy/aDCf8Aq4f5qeKH+znPX/ZOff8AgMP2+yL/AKZ5U/4hwn/q4r+3mR/9Msrcv+0GE68v/wArj8/zVcTxrw6zyP8A2Tn3/gMV/b3Ix0znlU//AOw4T/1cP27yR/pjlb/iDCv+rj8/zWcTf9neeP8AspPf/AYr+3mR/wDTHK3/ABBhP/Vw/bvJH+mOVv8AiDCv+rh/ms4m/wCzzPH/AGUnv/gcP28yP/pjlb/iDCf+rh+3mR/9Mcrf8QYT/wBXH5/mt4mf7PM7/wDZWef+Bw/bvJB0zjlY/wD+fwr/AKuH7d5I/wBMcrf8QYV/1cbIXsAO0Hn/AIe52zl2SuImWc0yzJ/EBMw4g8NJpOJRN4KEk+epNL2BmjLoXGQSIZEPmvLMAicQ5+0w6IWZZViGm4eLicwrch+8fBjxPytVYqrKEjNGX66dihm1OFU1LjWH1NSuskSTMqaeRTyqhcyZ7WkkrqCJaXQaWYopV7RSk+XH9JBkDKOasCwHxkypj+X67H8uKpss5pocOxPDqqpr8vVtTMVhOJ8FPVKnKm4NitQqimgSZqp1JjEuYuZJlYYlM3a7xtFHjzDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGN72qPaW/8nDsmZxXJphEQPEDix7zhdkVyCd9zGQL0+g4hWZ8wNvodbiYL9iZUZmqoGZQgU/CZijJAlBZL4iWeG56xr+p8AqTLWpNXXvQ0pSQFJM1J9vNdwpIlSBM4VpcpnKki3FxDrnxSzJ+zmU6wyJikYhir4XQlB4Vy1VCVfeagKBC0ewpRNKJiHUioXTtw8XEnSVQBQHeh+Z/p+qY1lP5jyDX5WcjsQDbSNKlmzc/gPoRPbH1AA8AT/Qb1xESwJiFRZPYe8nX4ekUJvJ4aeyqNlUWP9DFslAXSqmHge+xEN0IIWw6EuIvRXd7iwpC1IVirYhjvbW/IcgSC1v0t254CeNWafs8+LmSfFzKE5ZxHKWLyamsw7jCabMGATx91zBluuCgZaqPHMInVVAuYU+1op82TiFHMkV1HS1MrxvMpfFSmPi5bGo93FQT62Hk1qkqQbOIVQd5t1BS40ug7za0qoK0GGoEG/rseo6cunKP23+G/iFlbxXyHlPxIyTiAxPK2c8Docfwaq4TLnCmrpQWqlrZBKlUuI4fPE6gxOjWozKPEKWppZhK5KiY7TymVVF0k1Wnn1H8w0GxFQbaUjncqaZZ5pOo+Y6/HeLwhaXEhaTUHfTxFNQQagg3BGEfSSoKSFJLg6H5dxuI54Rc50/j6cvKOQWodfHCAYWuO3Tp02Zm1vFRL1NRpyJufM2ve2twcIo3FrwnVibEPyO5OhJI6RVEQdK21IVz86inj4X1NCPXR9xrofr1tFpQk24TbdP4m7C7m+ujFoqiJHJJ8Ca6iw+IV9NeYxVn52c8++r/y6RaZY0c8xxA2bcm5BGwZ79DFURIOxGgA5+Nfz1G+9Dp8mf5j6vtFDKJdikuBfn5akaMfcGi/5akOZM5z2WZWyfl+e5rzPOohEJKMu5blMfPJ5NYtZARCy2UyxmKmEdELJHdZhodxw7IO0kimn1c2XT08ibU1Ew8EqRIlrmzpiizJly5SVLWT/dSlRc2ePlYxieEZewysxrHsUw3BMHw6SqfX4ti9fTYbhtFITdU6qrqyZKpaaUAC8yfNQkbmM4fZq9hzxrz61C5i7RWboLgzInmmH2cmyJELmziLFhdFutTJ5l85UyqlLKh7t37fmiPEQHIeNkkCW/eOdq4H4S4nWBM/G58vC5JAIpZPDUVqn1Ewp/yenYMx456+J0qlIZz5yeLv9I94eZaXOwrwpwOp8QMTQuZLXmDElTsDynI4HSmZSS5kn+u8beYCFJ+7YLS+yKJ1PiNSFlCM1/B72W3Yq4PwUC3A8G5RxAm8MlH2rMvFxR4hzGZvooRExMpm0OjJ0KuoSAzJcrSqEFEqVDl0qcX2jhvh9lbDUICcMlVkxIdU/ElGtmLP95cuYkUqTdmlU8tJ14SXJ89c9/bN+0Ln2oqFVOf63K9DO4vY4PkUfsrR0cpQP9jIrqBasfnpuXmYhjVdPuQJvBwoHviU5alUkgISUyWVS+TyqAaSxASuUy+Hl0ugmE17rEHAQTTEJCsJuUtsNIbSSaJGOWy6aVKQmXKly5ctA4US5aRLQgD91KEhKUjoAAI1rrMUrMRqZ9diFZVYhW1SzNqaytqp1ZV1Ew3MyfU1Cpk6dMNnmTJilGzqMXUS9NLNqPShNK7W7tvXpbS72Pbs5+uv00Yv3qwI5tqH+B6D6vVEvNP/AESvPvWPyPlWn1xcJI6e8/HT09YtNQzlwLWGn6dL+7nbJxlGSZigzL5/IpTPYFRJMHOJdCzKGCjUd8MR7ESyFgUIWAFA/dUKCvx8dytlzNNErDMz5fwPMeGqJKqDHsJoMYo+JgCoU2IU9RJTMG0xKAtJAKVAgEZFJjOIYbOFTh+IVeHzwwE6iqp9LNbdJmyJqFlLv+EukvcXjznnfsa8Ic1tOOS2UxeSpoe8pEblqKUiEWpQNERMmjftUuUykkqIgG5bEKJAVElACMaq+If2EvAjO0qZOwjBq/w/xg8SpeIZTrFS6GYpX5ZdZgGI/fcJVToLq4cMk4TVEkBVYZaUyx2RgXjhnTBlpTU1snHKQMDIxSUlU8C/EqVXU/saoTFCwNSuqli5EniU8eHeJ3Y64l5CRFzOTsIz1l6HBdMbI2Hm5zCw6T8Tkfl9anooe6up1cqiJs02wkxL64dtLoa85PGX7D3jJ4XSq/GcvU0rxLynSAz1YhlmlnjMFHRi8ydieVVKn1p9h+JU+ZgtRjcmXTJNZUrpJSZyJHfWU/GvKWZFyKSvmLy/ik0hH3fEJss0M2aSwTT4iyJX4yAEprJdGtUxQlSkzVlBX5ZVBFKlJU33VJUpKkkKCklJKSlQI7yVpUCFA0KTVJAqRjR+ZWqQpaFOlaFLQtKxwKStCilaFJJBCkqCkqBHEFAv+IR28JgUApLFJSOEgcQKSAQUnQgguC7KBe40/Psunwg0OtCNK7DStd9vXFhq1K0e42D+87gw4iXckcxqwvyYaahx73jiYUDVIF61vWhtvSwpzNaabYp7d9Tozv8AHX+QPnFA2zG/1p/O8cTDWNQSRfe1KVoSDoN9gLilsBOAZlalncfJreZHWzwcO4dyx2IuTvrpoTrYO9zxMPXQWsampsb+B08BauLvbANcP09LM7e97m0OfPUBm5e7kQNGtFFUPYilwRoDqNTuRUUoBvXQgYkTPUWKTbRyQLadyzfCxivPbfe7sWbpe931e4ikWCCbCt9a1PLUk3FbEC1rVteiZ16gAu2xHPld769xHJ9ma/U3G1jd79bxRUzetCa6VGx1qTYg7geoqBiQTLgnbdy+oa/qNCG82o3MHQNbk1wHNgxbXTSKC2RyAANagHQU2UaVudh43oZ0zTd1JGx0JvsHubvZvK8VDd99Brpq7kDVt9xEdbQv0PMnewoANNNetd8TIWLC+3QN3Jb0FtG0EV5sNSC7Wu12YlzyYbBthGU1f7tDXS5162t4kEcqa5CFsbkMzu/933W6DU+tL/is/YHpttpyd7ADQRlsKINUUFjsKeZBsfwsSTXEwnJ5vdiQH+Funm/Q3sQ19DdzzuHAJ33fvbS55cnc1yfmORZqkcQIWdZcm8vnkriAVqDUwlcYxGQylgKQVt+9abDrYIDjZWgkpURj7+Xcx4lljHsFzJgs00uLYBitBjGHT9RJrsNqpVZTLKUqHFL9tIT7RHEAtBUgnhURGHiFBS4pQ1uG1iPa0ldSz6Ool6ccirlLkzACXZQQslKmBSoA63G0pwzz5K+J+QMpcQJMktS/NUkg5qiGW4l1yAiXUdyPljzqUpQ5ESuYNxUviFoAQt+GcUj4CDj9Knh1nbDfEjI2Vs9YQky6HM+DUmKIp1LEyZRVE1HBXYdOmJCUrn4bXS6mgnrQAhU6mmFH4SI84Mw4LU5cxzFMDqyFT8MrJtMqYElKZ0tJ4pFQhJJKUVEhUuegEuETEg3ePucc0j40MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGn97bLj9E8T+1UzwolszRE5R4DZeh5GiFhnGnoVWes1Q8DPs4RxeaTVcSxBHLeW4mFcccEvjcvRrQSxEvRqDr54lYsa3HBQIXxU+FSkygkEFP3qelM2pU4F1BPsJKgSeBUlQDFShGo3jTjysTzSnCpc0KpMDkIkBKSlSTXVKE1FWtwLqQn7rTqSSfZrp1pZKlLBw7oFwOVB6XJ+f60x1oXuR1L8wWDeTx04vUdHLdv5RPbGh5BR8bin0odMRrNu5H6/KIl8uqU+jP8ACJzYJNtzQeQJPy08fMYq9ugfrqAPf8PWBRBHx7k3+I6946a4w5VD0KzmmDaSHYRLcLNghJCnIVS/dwsWog0UqHcKYdxSgVll1kd73cNQQrDh9xbYdS/n2Fy2jR7wf0N32qlYTjmK/ZWzjiVQrDcwLxLNXhJNqp3tZFBj0iSqvzZlGnCyqZTyMbopdRmnDaeTwUUvFMPzCsoFfjqDN88Yhj9FEVmHlMKqKlBPxoFL/wAydPj86KFjsQiaTNMpV7oV+Ycv9YdR79DF4QtK0hSCFJIqCPp0I0I1Bsb4R9EEKAUkuCHB6dtj0NxHLCKwwhDCEMIq55mPb3Yp7B3GTtr5yXLcmQ5yzw5kMbDM584qziEddy/ltDzaogy6Ww4dhl5mzVEQ6KweX4CIb9yX4SKncdJ5Y+iPPK8rZQxPNVSUUqfYUMlYTV4hNSTJkOOLgQl0mfUKTdMlBDOlU1cqWoLjXH7RH2mvD/7O2X01eYJoxnNuJ006bljJNBPloxXF1S1iV97rJxlz04NgkmcpqjFKqUr2ns58nDabEK2UqlG472TOxDwD7HmVW5Nwsyuh7NEdAQsJmziZmFEPMM+Ztcao679smvuW0SqVOxI9+1luQsy6Rsltl1cHFR7Ko13ZnLuVcHyzTiVh9ODULQlNRXzgldZUkXPFN4R7OUVXEiSESQQCUqWCs+BPjf8AaL8T/H3GlYhnbGly8FpqqdPwTJ2FKm0mWcDQt0S/u9CZi1V1ciSfZzMXxOZV4lMCpqET5NMsUyPUOac25QyHJYjMWdMwyfLMlhRV2YTeNahGlukEtwsKhxQejo100SxAwbb8XEuENQ8O44QnHNMLwbE8brJdBhGHVOI1kz8sikkKmqCRrMmFI4JMlGsyfOVLkyx+KYtKQ8a9YnjGG4LSTK7FsQpsPpJQ/FPqpyZSSrZEsE8c6as2RJkpXNmK/DLQokCPC2fvaJZClMS5AcNsqTLOTjfeQueTp45ckynP3DAwZh4ucxzX/wDIYuHkqwQQ171Cg4O7MC8A8YqZaZ2YMSp8JSpiKOkQMQrG3E6aFy6SSv8Au+ymVgILrKCOE9L4548YRTTFScAw6pxUhx98q1mgpCrYypXBMqpqP73tUUirEJCgQqPME+7cfHnMD6lwU5kOU4RRIRA5cy9BKQkfuqXGT4z2Yrc7oAcUiMabKiVJZQCEp7Ho/BjJNAgCbR1uJzAzzq+unBR3ITKovucgB9EmUpQAA4yQ567q/GTOlfMJlVlJhso/lk0NFJIA2Jm1hrJ5UwuRNQklyEAECPj3e03xyi1FbvFDNaFE1IhI5uBbv/C1BNw7aRyCUgDlufqJ8O8nSQEoy5higzEzZJnK81TStT9SX6mPlq8Qs4zi6sxYk5v/AGU72I/3ZSEJa9rAchykQ3an48S8hUPxOzE6RtHKgZmk6WKZhCxQJqBuDemhxZM8N8mVFpmXaFIvaSJ1P6ewmS+Z2b4RdL8Rs5yC6MwVym2nGTUaEa/eJUz4HQnW8dm5V9oDxly64lvMsLlbPEDX/S/b5YmSTYISPuw0fIXISAQSAQVxkkj1Kt8SSFY+FiPghlOvSVUEzEcGnN+H2NQaymc3JmSK1M2cpuUqrkAcjpH3sP8AGvNdEQmvl4fjEh/xe3kGkqW0aXPolSpIYfvTaScbOI9f8NO35wXzopmX5yEbwxnTi0Nd+dqbmGV3VOK7qFIzFCNN/Y0JNDEOzqWymEhUkKMY8gOuJ6tzD4I5swoLn4V7HMNIlJWBSJVIxFIS5KVUE1Svaqb8iaSoqZkwuPZJVwpPaGAeNOVcVKZOKe2y/VKUEvVkTsPUSWBFfKSn2QButVXIppUsX9qsBSh7Yh34OYwrEfL4uFj4KMaQ/Bx0DEsxcJFsOJC2n4SKh1uMRDLiaKQ424ttxJBQsgjHT02VNkTFyZ8qZJnSlFE2TOlrlTZa0llImS1hK0LSbKSpIUk2IBjtyVNlT5aJ0iZLnSZqQuXNkrRNlTEKDpXLmSypC0qBcKSopULgkR5m409mTJnFJuJm8A1DZXzqoe8E9goZIhJo6lBQG5/ANd1EZ3/9GlUxZSiZtdxol2KYb+yOaY/aM+xf4deOUitx7CJVLkbxKmD20vNOHUgTQY3ORLKESM2YXTezRiCZoEtKsYp0oxuR7KSVT66mknD53beQ/FrHsnLk0VSubjGXweFWGz5jzqRBVxFeGVMx1SSklRFLMUqjXxLARJmKE5OKfOvD7M3D+fROW81Sx2XTGHCXEVAchI6FUSG46XxSR7mMg3SlSUPNE9xxtyHdDUQw8y14OeJnhtnnwhzXW5Mz7gk/BMaowJ0srPtKDFKGaVCnxTBsQQBIxLDakoWhFVTqV7OfKn0lUinrqappZO52X8xYRmjDZWLYLVyqukmkoWzpnU04AKVTVUlTzKeolggqlzACUqTNlqXKmS1r+QMKeQ3Gn5DbenyxwATy91dbXLvbUv5amPtW1Z7Wsx9S3O2nmIpqhrXCqeBudvvJr4i9Lcr3ieST1JuTe3JiTr5g+QitjoAOgZ7Xct0OuvNtTSMNSlE7GwFTanMV3rod+WJkzyXdugDXHIB3HuPPSwB7gq5HQa9QSw1Go5GKCoc6AGhtTrXrSp8KX5byoneoPRr2A2uddNLQ63vo9vg+789+0UFMEmw5G9QbilqA0rtY1vcbypmszkMHZ9Oe7aNcEdRZ4DS2/m+/0Aw5RSVBuEGiDp+98Ngb2JrQVrXbUdbxUoBJVMe9+C4u1u45ctelRcsd/N376t79i7RRVBU+8oA3FBcV8SBvQ6G/PTEwqd0pJ5EkA8tA/wARaKltWLEbMNzf97e2o7XvHXDtp1BVUDU7UuDSgpcUxPLnLU9+FiQQl+l3JJfVzbaKhiLh2STe+hsz8tmiC4hIBCQEig0HI3+nmcZMskqDkm5YEk6p4tenv9BAXUz6gkPfVPPz827RAeTZQrqD8jU/W36OMxB18vn9fyipuFFtQkj69fLpFud1Pn/ynGdLLl+Y+Yin7pPQf+I/CMx/syeKSpllvOvCKZR5cictRLeb8sQjzilOJkc3eEJP2INBJDcFLp39ijXkAJH23MrjgKy6vuevH9HP4kqxHLmbvCzEK4zKjL1UnNGXKWcsqmJwXFJiafG5FIlyEUdBjCqSrmpZLVeYJkwFZmr4NT/tEZcFPiWE5op5ATLxCUcMxGahICTWUqTMoVzTqqdPoxOlJVf+yw9KbBKXyo49Lo1shhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCPjeIueZFwxyBnfiRmd9UNlzIOUsw5xnjyEFx1Eqy3KYucR/uWgQp6IVDQbiYdhB777ykNNgrWkHHq6mXRUtTWTi0qlkTqiaQHIlyZapi2G54UlhqSwEYeIVsjDaCtxGpUU09BSVFZPUA5EqmlLnTOEbq4UEJSLqLAXMfzxc65vnHEHO+cM/ZheVEz/O+aMwZvnkQtRWt+b5lm0VOZm8pRCSpTsbGvLKiE94qrQVpjUarqJlXVVNVNPFNqZ86fMJOsydMVMWX1upRjz8r6udX11XXVCiufW1NTVz1EuVTqicZ0xRJAJJWsl2HYRZUfeHXX0xhfunkNOdyP0jBXqO3zMTW7U8U/8RUfwGIlmwHf69CYjUXUOpUfcf1ie1qnxUflT8TjGVv0AB8y/wCnvjHVZhzKfkfcIkuwzMXDOQsS2h6GimDDPsrAUh1l5JbebWk2KXELUlQ3BOI1WKj3j62XMyY5k/MeBZsyziNTg+Y8r41h2YMBxakWqXVYZjGD1kjEMMrqeYkhSZ1JWU0mcgggOgAukkHxRm/L7+U8wRsnd7zjKCIiXvrSUGJgHlK+zvCwQpSe6th8t1SIlh5KSe7iwpCmILdLFulgNPpo/bJ9k77Q+B/ag8DcneLGFIp6PEq+RMwfOeCU89M8ZczxhEuRLzBhBIUZiKda51PjGECpCKqdl/FsIrJ0tCqnhj54EEVH69MREMW/X5tGx8V2H1Mq3LZPxJHP+JINu9a4/eHWhwieTOMssboOo5HmOvTcdbxeEqStIUkggioI0PhphH0AQoAguDcERywisMIR779n72FM4dtrikqVh6Ny3whyY9ARvFHPUO2z7+FhIhxS4XKmWvtKXGIjN+Ym2IhuDcdYioKQwLcTPZnDxSIeDlU25lkzKFTmvEDLdcjDKUoXiFWAHSlRJTTyOIFKqmeEqCCQpElAVOmJUEplzNXftTfaYwD7OeSxW+zpsYz7mGXU02S8szVzPZz58pITPxvGPYqRNk4DhK5spVQlE2TU4nUrk4ZRTZCptRXUG7jwq4W5C4MZEy3wz4Y5Yl2UclZUgUS6TSSVtdxppAq7ExkW+sriplNZlErcjpvOJg9FTKbTB+Jj5hExEU846rarD8Po8Lo5FBQSEU1JTI4JUqWLAaqUol1LmLUSuZMWVTJiypa1KUST+dHOec80eIWZsXzjnLGavHsx45UqqsRxKsWCtamCZNPIlICZNHQ0klKKagoKWXJo6GklSqWlkypEpCE+Z+0922cpcDVReTcotwOcOKXulJiJcp1apHlBTsOlcM/mV6GWhcTHKDrb7GXYOIZi1spU5MYuVNOQZje9/DTwbxXOgk4vipnYTlkqSqXUBIFbiwTMKZkvDkTApMuQOBSFYhOQuUFkJp5NUpM32OuPiP4wYXk0zcJwtMnFcycJC5BUo0WFlaAqWvEFy1JVMnHjStFDKmImqRefNpkrkmdhczxxVz1xWzA7mXP+ZZjmKaOfAwYp1KYKXQ/xFMHKJZDpal8qg0HvK+zQMMw244px94ORDrzrm4eC5XwTLNAjDsDw6Rh9Km6xLS86fMs86qqJhVUVU02HtJ0xa0pCUJKZaUITqLjOZcZzNXKxHG8RqK+pNkmYoCTIQD+GVTU6OGRTygS/s5CEBSiqYrimLUtVnhosfCSaHSuxF/xv47jXGRNku9ut7dux+OvOMSVO27+e3TVme/UPF8YjqUv0GnkDQgiupG/LngrktqLDZgH66Hfe/aM5E4NY7Bzr6jfv8dTckTAUA71TyJJP1GvhT1xjmQHcgDn9EfwtGQJ2znycADnp11do4rmAp94Gm1TbkTc/rxxVMgA2AP10HxfSKKnvufNz6ON+vui2REb3rA13ua/971NyDTpjJRJ0tbtcctrfBvOMdc1rktuX1PTZuXwLCLBExQob358qEaX1/wANyT9CVJ6fLv2HvPpGFNmvZ7Ne79Pd07C+vcfBXtScUuAUzbXlSbrmOV3Ylt+b5HnTr0TlyZICkpfXCtFRckkyea+D9qyksPrWiHEc3MIWHEIri2b/AA2y1namUnE6UU+JJlqRS4xSJRKr6csSgTFNw1dOlX4jTVIWhIMz2KpE2YZo5RlPxEzFkqoCsNqlVFAqYldVhFWpUyhqACAsoS5VSVC02FRTFCnCPbJny0CUc7vADtJcO+0Zlpc1ynFmX5iljLJzRkyYvNieZfedUttMQO4EImcniXEK+xTiCQWHkqbZjG4CZB+XsaU568PceyFiApsTle3oKlaxhuL06Vfc65KQFFF3NNVy0qHtqScRMSypklU+n4J69y8j5/wLPdAajDJvsa6nQg4jhM9afvlEpRKQtgwqKWYpP9jVyQZagUompkT+OQj6nirwqy3xUy67JJ4wlmMYDzsknbLTao+Sx6mykOsqNC9BvlLYmEuUtLEay2kFTMSzDRcNqn4+eAeSftBZKqcq5rpk02JUyaipytmmmp5S8Xyxi65JRLqqWYsJVUYdUKTKRjGDTJsulxWmloBXTV1Nh+IUPc+TM6YvknFpeJYbMMyRMKJeI4dMWoUuIUwU5lzAHEuegFRpapKVTKaYo2mSZk+ROw/51yHPchZlmGWJ/DpZj4B0dx1rvOQ8wg3Cr7LMIJwpT76CjG0+8aKkIcQoLh4htmJZeYa/Nj4reGmbvBnPeNeH+dqRNHjGDTv7KokKUvD8YwyaVnD8cwietMtVTheJSUe1p5i5cuokrE2jrZFNX0tVSyN88t5iwzNOD0mNYTMVNpapJ4kLAE6lqEcPtqOpSCUy6inUeFaUqUhSeGdKXMkzJUxfyn7PcOjahUm6qIoO8TUg91XM1oabY66NagX4ypuTqHutf1axtH3mfbpe5vtyY3t00NjHBUtCT8ak6qr3RU1Ar9406bW8Nb0V5IHAk6BuIsNW0D9NdvOAYNvpv7jblFEwjKVAFJVcak7AkWFBTpSnOuJE1M5QP4uHnwvv3JPN7jto1bM4G6h6No7/AKxFWlKUgJSkUSLAAUvfQD9a4yEqUVB1KLvqSdjzJi17jsf/AMPw25RDcFUkdFg87/4188Zqf3fKL9xs/Dp5P7384tbopX+1+dMZksukDcAP5vFPkkg+awYtztiL6pB/Xp+qYzpX7+llfw+u5i9IfXkof+H9T6nnFtd08lYzJf50+X/gVBJuB2b/AHS/y93KID+/9/GdL38vnFdj/gHwVFucFQetL+IUPwFsZsu3D2HvDRa34f8AZPuUD+vrHofsicRUcMu0Lw8ncU4puUzeZf5ITohwNNpl+aQZS3ExClEJ+yy2ZPy+bRAIUS1AK7g953CNkvsp59R4d+OeRcXqZipeGYriX7LYuRMEtCaHMqRhcufUKUQn7th+IzqDFKgEKJl0KuAe04SOAeKmAnMOR8dpJaQqqpaYYpSOkqV7fDSqqVLlgX9pUU8ufSo/1p4c8LxsrY/QrHn3DCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYqfbLcVmuG3YfzlJGn3GZvxczRlThpK/crCXAy/Gu5un63UA+8MG7lzKc1lr6xRsPTKFZdUQ+lp3g3iJXCjyzUygWmV86RRoY6AqNRNJGpSZNPMQdnWl7Fj1d4wYoMOyVWSUkibitTS4dLbXhUs1c8kC/Aaelmy1GweYkF+LhOl+1oOfdH9fwxrirU9z8Y04V+c/7XxEXBH3h5/Q4g/d8h8VRCv8AMfL4CJze3gj6LpiGZt5/KI1apbX8TekTm9U/2V4xzqt+aYhVqny/8Bi4J0RTmj6jEStFdjECtT3PxjrXi1k85ly6Y6CaW7N5GH4uHQ2ApyJgyEmOgwnVSw2lMTDpTVZeY9y2lSnyDbLWEqY6KYatdmFnYvu/ePT7+i0+1Yn7P/jkjImbMSp6Lww8Zp2HZexeorp5p6PLmcpS1ycoZmXPV/YU1LUT6iblzG508yKeXQ4pS4rWVUqnwIJV47beFRSpGtdyCBe33hSlT941pc1BlUgKdru7jRr9dPR7PsI/WcldyCWIJBBDFwwLg7h/Lo15iHAoddeYI5jne1NdKjECkEH+e3N+ly7b8ok10+vPtcmw1iXDvllV6ltX3huk/wASf+8ka66i9kTSZxlljdB1HI8x821EXhKgoBSSCCKgjQjCPo8iLg3B5jmI7S4K8H868fOKeSeEHDyXmYZsz1O4eTy8LChBy5hQXETOeTV4f/hpNIZWxGTibRN1NQEFEFpDr5aac+hhWGVeM4hSYZRI46mrmplIeyEA3mTph/dlSZYVNmK2QhTAlgeFeIuf8ueF2Scx5+zZVfdMCyzhs3EKspY1FXNBTKosNoZZ/wA9iGKVs2nw+gk2EyqqZQWpEvjWnfR7M3Z7yH2XeDuUODXDyGUmT5dg0OzOcRDTDc1zZmWO92ufZsni2EIQ7NJzFJ75SO83AQLUDKIMol8uhGm9wcCwWjy/hdNhdCn+ykJeZNUAJlTULYzqmbwhjMmqDtcIQESk/glpA/MR4weK2Z/GnxAx7xCzZOBr8Xn8FFh8qZNXRYFg1OpacMwLDRNUpSKLD5CuHiLLqqpdTX1HFVVdRMX5r7cXbJHBeXq4XcOJgyrinPoL3s0mrKkuHIEljEVYigC2tk5nmzKlLlEOtRVK4QidRTSS9J0xmz/gj4QftjUDM2YpChlihnlNLSrBSMerZKvxyiQpKxhtKscNVMAAqpwNFLUeCrMnTPxo8WhlGQctZfnpOZa2SFVNUhl/1FRzQOCaxSUHEapBJpZZJNNK/wAsmIHHSCdgmTMYiKiHoqKiHoqKinnYiKiYl1x+JiYl9anX34iIeUt55955anXnXFrcccWVqWpR7yt41U0uVLRJky0SpUpCZcuVLQlCJctACES0S0gIloQlISlCQlISGADMNKRPVNWubNmLmTJilTJkxalTFzJi1FS5i1rJUta1EqWtRKlKJKiSXi/QsXSl+XnqDfYiu4pWm9h86bK1bX5W7HY31G73fMlzWAc2tf6056aM53N9YjQKXsDz5Wpp5mpFK6m9MJckEszHl77N52Di2gjPRN699bm+u4107aARdmo4ilVH1NfzAFfE74w10/T3DnpyPkR7gIyEzuttObHX4NoOdomJjxrc2FgTUdampr5A/OsJp+bjmwt8SImFQwDnt8AN/R/J4LjxfUE8ya15/TYbmvImm/g4+VvnA1BNweh8+lufI9NIgux381utf8fA64nRT2/L7hft9GIFzjz3332J1059zpvaIiMqCK+Vxr6UtU60BPljMlym0D6eXX16A2taMZc1t7bE69fXmWYWOxiwxEXYgHT9frpyBJxnSpJd2fv8Db3XJ3jBmzX3YPfUnkXfbn8L/iueR+JWbuFmbZPnrI07iZFmSSRAfg4tg95p5pRAiZdMIZRDMwlUwZBhphLolK4aLh1rbcTQIUmHGcuYTmXCqvBcao5dbh9YjgnSpjBSFBzLqJEwDikVMhX9pT1EsiZJWEqSRcGfCMwYplvFKXGMGq5lHX0cwLlTEE8K06TJE6USUT6acAZc+RMdExBKVB7p2V+zD2k8r9pnh0zmiVpYleapOYeXZ6yol5xbkinam1rbfhFvJS5ESKcpadi5LGVdq0h+XxLxmUsj20edviV4eYl4dY+vDagzKrC6sTKjBMUKQlNdRpUApE0JJTLraQqRKrJTJ/EZdRLQKeokKV6CeHHiBh3iDgSMRpgimxKk9nT4zhgUoqoqspJC5ZWAqZRVQSqbSTXU6QuQtRnyJwFy498K2eI2V3X5ewk5rkTb0XInUqS2uMbp72Jkjy1gJLccEn7J31tpYmHuHC61Driw752/bW+zPS/aD8NZ9ZglHLPifkilrMTyXUpVKkzMXkhIqMSyfVTZoEtcjGkSnwtU6bIl0WOoopy6qnoZ+KJqNkvCrPkzJePIlVc1X9QYtMlU+KyyFKTTLJ4JGJy0pdQXSFX+UcCVqm0ZmoEuZORTmXipiEqbUttxKkOILiVoWkoWhYJCkrSoApUlQIUkgFJBBAOPzaqlTZMybJnSlyZ0lapM2TNQqXNlTJRKFy5ktYC5cxCgUrQpIUlQKSAQQN7pagtKFJKVJWUqSpJCkqTqlSSCQQpKgQQWILiLY7tXUlR/4aflXqcZMsMA2jJ96gYfXz+ukW5f3uV9OdqfjXGXL0Pv7bfP6aA0G91F9mcAe9/SLc593+6n64zkfmHn8DFNx2PxTEBwgJPOiz1oDT8KYzkaJOw4Yv8A3k/7PwB+MWx3f+1+eM2WGSObMfJ4p/5C/fjDe6Lc7Wo6JA/Xr+r4zZTfj58R+H84vSW9CfK36Hz7iLa7p5K/XyxmS/zpPb/wGCdRzt3/ACl/l9AtAf3/AL+M6Xv5fOK7H/APgqLc4QK8xS3gCfx8dcZssPw9gfd+sW/u9gfepvkYhB52HebfYWpt5hSHmnEmim3W1d9taTspC0hQOxAOPoU02ZImyp0lZlzZM1E2UtJZSJktSVoWk7FKgCDsRCalKwqWsBSVoUlSTopJStKgehBY9I2p+EudmuI/DHIWemi2FZpypJJvFttKKm4aZRMCyZrBBRuowMyTFwaidVsKudcfpd8Mc3S8++HeSs5S/ZhWZMs4PilTLlKK0U9fUUUo4jSBRuo0deKmlUbuqSS51jzYzNhCsBzDjWDK4iMOxKrpZalhlTKeXOV92nEB29tTmVNA5LEdh451Hw4YQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEI1n/8ApA2fmnJz2b+F7EXV+Dlue8+zaBCyAlqZxUjy7l6LW2DRZWuU5nZaWoVb7jyUH/SLp034r1QKsJokqulFTVTEvstUqVKURv8A5ueByuzvGuHj1XAzcvYYlX4kSq6vmofaYunp5CiHYv7KpAcWYtqY1yWtv7I/DHTitT3PxjXZX5z/ALXxEXBH3h+tsQD8p5HQ9iP1iJevl+sTWzp/c+RUDiGZt5/XuiIg8SehIPdv4RPa1T/eH4/Sv6tjHVbi68J8hb4t6xArY8in5JPzi4I+6joGyfCo/LEa/wB7z+cQkXPVRH16xNbFU16qFPEj8sQK18h8BFFliCCRwlJBBIOgDgi452v2jxRxcycco5lVEwTRTJJ2XY6ACTVuGfKgY2ABoC2IdxxLsOhVUiEiGUJWtTLndyJS+NL/AL6fwqZn3/ERoXbTmC0frt/o1ftWD7SPgPQ4ZmbFJdV4q+FSKHKWdhNdNdjWHIplIytnRaSpaZ6sdw6lm0eLVEpQWvMmEYzUTKWjpaygRN6zaeB3OorY18wNf7QpS17UxeQ7vobOR3ex0uwY9WaPRpE0ixY6N1f6256WJic29oLm1tzToaXHPQ6A74hVL1NtfrTqGv1IfbJCgpy+t3739+nIXi4w0T7o0NS0q5H8B/iTtQ/vDwNr4iLsAdtO3Ly9xcdsiTOMshKroPqk3uLOzm/NizkRtM+wv7LjGX8kZp7VmapQj9u56ejcj8LnoxIU9BZJlMahvNeYYBskoYOZszQYkTUU4hMciCypHJhVIlk8eMfsB4R5eEijqMxVMr+2rCukw8rF00kpQFROQNvb1CfYhRAWE0ywlpc08fjV/SXeNy8XzLgfgfgOIqOF5Zl0uZs6oplNKqsxYjTKVgWFVUwMqaMGwao/rRchClUqqjHaZU5K63DJYpc0XaM43yns9cIczcSZkhiLjoJlqU5VlD7wYTPc3TJLyJJK+9X3hYC2XpnMwwHIlqSy6ZxTKFGHttB4cZJq/EHN2GZbplLlSZylVeKVaEFZocIpVINbUt+ULIXLpqb2hTLXW1NNKWoCZHjt4h5zpchZUxLMVQlE2dJSKXDKRawgVuK1KVijpncKKAULqKn2YMxNHT1M1AJlxqzZgzfPc6ZinObczzSJnOYcxTKKm04mcYtTkRGR0W4XXnFEmiEAkNsMN91mGYQ3DsIbYabQj1IocGocGw6jwnDKaXSYfh9NKpKSmlJCZcmTJSEoSANVG6lzC6psxS5kwqWtSj5mVmL1uM19XimJVMyrxCvqJlVV1M1RVMmzpquNai7gC4ShCQEIQEy0JCEpBqQsXSlT9b/IDnevXxsmSjdw40trYW3+N9riKy52jfG3lv5dxF9YjK0odafiBS3Pem40FsYK5LuWte+1tT8bgxmy52lw+vmW5NpbpvrF4ZjiKX2sL9eleYsKfLGFMp3ezuP5ae52jLROZr/WxF/oHVg4uKI8Cl6AdK032Tr6jGKqnbTXb57n0cfrOmo8+2pHy7EbG8SkzAU+9XkdKeiMWewJ5egv74k+8Nvfu/yIgqYCla08qk+qf64exV9N+sDUO+pto7fIAxDcj7WPhtz6V3voPxkTT23c67cuoHKI1Tzcgt3bydy/TYcuttejSa3+uu40rzNeY8K5SKdmLMPLS/X4a894xlzX1L7/ABbXk4BfmNWaLO/GfzbEHa3PTz6fPGdLkgWLBty3O+9ratc6xiTJ1yHNy439x9Pq1hiYsEKvzB2Op8/r+ebLlOWu3xb5dHYM55DCmTXPfcX9LF+vnpt3N2aO0TO+zhxbkOfpeqJipC481KM8yBl5xtvMGUYx9H7Rh/dijS5jL0gTSRuPIUlqawkMldIV2JbXxPxF8PqLxCypXYHPEuVXpQqrwWtWhJVQ4pKQfu6+I/iFPPJNNWJQQqZTTZhT/aJlqTyzw+z3WZBzRRY3TmZMolKTS4zRJUUiuwuatP3iWQ5SZ8hhVUalAhFTLl8X9mqYFbXkoncpzLJZPmOQxsPM5HmCUy6dyaZQi0uwswlU0hmY+XR0M6glLjEXCRLL7K0mim1pI1x5a1tHVYdWVeH10iZTVtBVVFFWU01JTNp6qlmrkVEiYkgFK5U6WuWsEOFJIj01o6ymxCkpa+inS6mjrqaRWUlRKUFS59NUykzpE6WoEhSJspaFpIJBSoGMbPagyAnKmdxmGXw6GpNnAPxxSyAlqGnkOpv9rMFAr3BGF5mZIUe6HnouMS2gJYUB+eb+kW8DZfhl4wIz5gVDKpMp+LCKzGeClliXT4fnOjXITmimVKT+GQMUVVUeYpSzwS6iqxLFZVPLRLoFpTu94HZuVj+WVYPWTlzcSy3wUrzSVLn4ZOCjh00KP5zTCXNolWKkSqenUtRVNBPll0mljWgPQ0URT1AGvM10pjQJGrczblYG3k4Md2biztfXlr8/4xbnDfvV0qa9AKbdadNcZkoWNtWB63d/QEdxa8Bo3IBPqSfSx5xb3aAm/IdKAV18CmvOlfDNQL6de72HwPrFPkHIvZy3noNLxAetrr3L15qJrptY+FqXxmgWAG5YeQ/iPQxUdNh6cIt8B/JxFsdNCd6d4/qnUXxnI0A6j3sfnA+4Aepct9PvpEB0jvEcqAfT52/DGXJdieZJPezD4+sXCwJ/1fibe74Ra3Tr0AHqfyOM6WPxDk6vcOEfP+TiFwotsCPQFvO3xi3vKNFHofqQfWn61xmIGvl8/wBQfOKmwUOQSB/GLc7qfP8A5afUj1xnS7Hyb4e9h5ttAflI6J95JHq43tFvd/e8APQ1/H9GoGXKGu9yfRI/SKq1L3ZJPpofeQR0flGwP7OzNicydmyUSsqKn8k5ozNlh8qPxFL0SzmiGUBr7tMLmRphKh8JUw4KlSVU90vsJZlTj3gBheHFRVOyjmLMGXJpUfxKTMqJWYqdQBb8CafH5UlJA4SqSsOVJWBo7464YaDP9VUD8mLYdh+IIbQFEtWHTAf9YzKBayOSwdCI9043JjpyGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNM322GcXs0duzMMnWoLa4fcOeHeToW4+FmJl8Znp1NhUd2OzpFpINSFVOhGNevEioM7Ms+WdKWjpadPZSFVJ/wCapVGoHjLVmpzvUSiXFDhtDRp3YKlqriO4XWr1MYnEG58CPmB9cdefXrHUpsR9WZ9uw+ETUH4q8yD5EAfniEuARsHA9QSfh9a2L1Fr3H6fGJ7ZoANyDToQbedfr6xr0+t7fOI16vpcH129+sTmzQ+Br6gg+la/KorUYq+fMN7wR9fpGOoFtb6+YJ3vy1+MT0EUtsDX+6dvX6YjLvfe/reIle6xHUEf+mJzRNPE19UjTxUD671xAqxblb3lvc3wixbEf7P6kX6Bvh0j5fP2UGc65YjZQQ0mPS39rk8S4e6IaZQ4Pue84EqUlmJSpUJE/CsJZeWsNrcQ2UxoX7OYTs7KB3BPY6G4PTq0bUfYx+0pin2WvHfK/iImbWzMoVswZb8SMGowJpxfJWLTZQxCbKpVqQmfieA1MqlzFg6UTaabOr8Ml4eqql0VfWy52PVxL0LEPQkS0tiJhXnId9lwd1xl5lZaeaXSoC21oUhQNgQoa4+jrd20uDrysXFyS0ftBwfGMNxvDMOxrBq6mxTB8YoaPFMKxKjX7WkxHDMQp5dXQV1LMAHtKarpZsqokTUgFcqYlRDGJLb53IpQVO2t6gXBrYEEDU4oxAIAOmm2+h5alla6MHj7CJhDEcnZ9idue+nO+jR9dk/Ls3ztmrLWTMvtpfn+b8wSfLEkZVUodm0+mMNKpc0sJClKQuMi2EKKQV0Pwg4vk0q6ufIpZABnVM6VTygQf85OmCXLfdipY1GjsdAcfGcdoMvYLi+P4osy8MwPC6/GMQmJI4kUWGUk2sq1h2SFJkSZihxEJBYKtH9Erg5wzy7wX4XcPuE2VELGX+HmUJFlGWuvJQmKj0ySXQ8G7NY4NjuGYziJbfmsyWj/AEa4+NfcSAkhKdysNoJGF4fRYdTA+xoqaTTIJbiWJSEpVMW1uOaoGYtrFa1ER+WHPWcMV8Qc55pzvjaknFM1Y9ieO1ctClKk0ysRq5tRLoaYq/F90oJK5dFSJV+JNNTykqJIJjB17U3je5m7jLJ+EcseUJDwqlbUTNQHFBEZnXNENDzGLWW0qKFNSnL65NBQ7i0pfZjYueN3ZcbK/Rr7LGR04TkyrzfUoBrs11K0Uh4Q8nBcMmzKeSOIhwqrr01s6YkEoXIlUKrLSoDza+01nNWK5wpcqUyyKHK9KhdVc8M3GMTly6iaW/KU0tAaSTLUQFonTa1LlCkmMaMNGXBB0Guvypt56W5Y2YmSm25sNdNG0OjkjXbSNcZc0Br77czYNzB3v83v0PGbVpz2rfSoFq78rDW+MCZId7DS3J92v8tthpmy51g56c72e3QbW3NhreGI2m/Pz/4aa2N+pOmMBdOQSw23D78nPLr3G2YiboxG36WOunS/J3i6NR+xPjv56Vr8r02xirk809iPncX1015CMhE9mv6nXzZm5P8ApE9EeOe24A1vShSPl+OIFSASdPRjbqSH8ifhE4qPNr2bXyPvaJAjhY1FacwD/wAtsW+wHMev/qi8VHU+/wCYMfhjrGhv0IJN/wCzh7Acx6/+qBqBrc+Z91gIjrjxc18bA1FOXdpi9MkDqOQ/V29SPhEap/lycjTe+2uwiA7Hkix6fMC1vLntSgxOiSdks+pPyY6eZ7DeBc539fI3199mDE9otT0brU1/Q2oKc+gFLiuMtFOd7/T7W6bWDNYRjLm63Gt7n3nftFliI3W+lv18NxvodqUvjPlyG2a/e4Omr+v88WZOcFiOnU353PI/DeLFExYIN9q+I2raw6dN9s2XK0DPfuzEddeml+djgLmM/LqbOG7D03jYa9k9xxdz1wczFwknDpdm/CObMrkrynCoxGSs1vRkdAQ5SpSll2TTyGncMpSfdsIlsZJodtvvMOLXoB9qjJKcDzdh+a6RITSZrpVprEBLCVjOFplSZ0xwAAisoZlFMALrNRJrJiiy0hO+H2Ys4qxnKlfleqWV1WVqpBpFlTmZhGJqmzpMsgkq4qStl1kskMgU86klpDoUVe3O0blVrNPC6fqDQVHZdT/lNAOjVv8AZgWJglVLqbdk7scFJrQuhh4gqaTjyT+3h4Z0viP9nDOc4U/tMZyCiV4hYJUJB46f9nkTTjyF8P4l09RleoxpK5RIlipRR1awpVJLEb1+DuPzMCz3hSSvhpcaJwSsQdFitUn7mQ9kzEYhLpClbE+zM2WGE1UYoXVVJ0NSdyD8NhSvXTkTQG1/zdoHw+N+Z2A5c943uIJ82H625s/MWEW9ehFrkDlfUgX8evxa2xmy0sBrufLkdd332i4/r6Cw59dz8zb3D3q21BPrWnhUX8xXQYzZQue4HmLkH0t2LavFA251IHYDUfE6Pr1eA8dRTQ0Brr3B+dqDrpTGWkXSL8/ruB7x53D947mzNuS9vQ+7WLa4b6XsPH9DXwxmpFgHsAS/v5+WsUto/wC8bi9hYH42fvFudP3tKEq+ZoKbadT90864zZQZIO5AP113frFyiW7EB35D9XL9vK3OG58b+QqfoRjNlDmNBr3NvUC/vvFAHB8gOVyPo73veLc7oRofh9bE+tDXGagWDbn5tF6jY7OT5EaevD7+l7e8bE7mtPMgD17o9dgK4zUb20a773HwP08GDs+4H+6Bvpqz6aHtFudNa1tRVPIDXGbKAAuNQfer+O3MxQ6l7hwPUj9COdgO2YP2Vk6dclfGXLy3CWoWYZOnLLP7rbkfDT6BinAP4nUyyDSroyMer/8ARu4tMXhnirgaphMqmr8rYtJlE/hRMrafGaOpmJDazE4fSpUX/wC6T0jVb7SFIlNVlavCWVNk4rSLVuUyJtHNlp7JNRNI5cZjLfj05jWSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNFb2oc9GYO312kY1CypEJm6UyNI7wUEKy5k/LcheSNQB9olzyinUKUoGmmNaM7TPbZoxdWwny5X/AN1TyZR96CLRpN4mzhPzzmBYuE1kmR/9xR09Ooa/3pZ5eseEEGhHKtvBW/qT6Y4edvQ9xZvQD1jgC7B97P3BZvQD1icjQc6fIH8K4iP5j1YPazhtOpuWvY84sWLA8j9H3RPbNxzBNPMWp/eoT/WmIVflPaIVgsez9gDp7omtn6VpzI2+vpjHWNNLFn2117W98RLAuNr3/wAQH6W1i4NEd0b1Iv0I/wDer0v1xEdebW9LfBv5xCoEsdPw6dbE+57a26RNaPWoCb73SbeZ1r0PWkKgz937vr6Ee/1sIBH1dxf0b3+s5s0ppZVL7A2+p16+NMdYu/MRCXI7Ai3MF/RtO3r5B7QuSDLJlD51lzQTBTd0Qs5S2juhmbJQSxGKCfhpM2W1BxQCVCKh1uLW45GCmdTTOMezNyi6BZ+E6jiN/wAJLdmDWj9I/wDRAfaoVnTI2JfZszhiE6dmbw3olYx4fVNZUe2mYn4eTalEqswGWZhM/wBpkrE6mUmjllcyWnL+L0FDRyqekwBQPnJp+lyanbcU1sajTc1saigOJyCNBbqGIZtRt01BtcR7YomG3a9+pfr0cMTfXSMmPskOHMHxM7evBBqZQ32uUZEjJ/xPjWSkEJjck5fmEwyrEkqCgkQed3Msxlwe/wC57ie4paVp5l4e0Ka7NuFcYKpdKqdXKSdlU0lcyQeyar2Ci9/wgAh41a+2xnCdlP7NniEqknexrsySMNyfTzAWJp8wYnS0uMygxD+3y8MXkAhmMx1AhJSreUejoeXwsTHxay3CQEM9FxK7VQxCNrfdVcjRltatQDTWhNNqpMmZUTpVPJDzZ8yXJlA7zJqwiWPNSgI/O7OnS6eVNnzS0qRLXOmHlLlpK1nUaJSTqO8aYvEHiDMuJPEPO/ECcOBUyznm3MGZ4tKVlTbC51NYmPRBsFVCmEgGXm4ODaACWoSHaaQEIQAPajLuXqXLeXcDy9RJamwXCcPwuUWZcwUVJKp1TpoDgzp65ap05bkqmzFrUSpRMeOuP47U5ix/GserFPU4zitfic0BRKZZrKmZUJky3ZpUlC0yZKABwSpaEgfh4RZ4eMpS4Btvvbr5jSopagxmTZDvbnbUaG/6nTubxhondunu59zfYkO7WvLEbpfXqK9RSmhNuh0FxjCXJPLdh27l3Yerl2N4zETnAvyZrnXfsb6ciSLxd2Y7kSQAdaX515bEVPOwOMVckFw2vkdfR9b7APyjJRP63+XJrAvfsTFybjhz6VsSa38vXQgg2virp+Y62fp5uzWfbtGQmfo5fc6/CxJJfTzG0S0R4FisAV/l6c7itNfAX1xCqmf93zYv8/jEongvsw13fyfS1vgIr/bU8x/vJxH91P8AdPof1iQT9yq/f5Ew+2pH7w9U4fdTyPof1gZ3JXdz8GMR1xw071aVp938L8tSD6YkFO23oDf0AiNU8bbhww5fz2G9ohuxwNaK8zQV01A8ufPpjITTtYB/XbU9ex6CIlT9htzOzPrfmUtvaLY9Gg1+KvmKHS1vGlR1FgLZCJLNa/Qd/IWe3axMYy5z3vytqA242Op8zZw4tL8YL3rXw6emlhoKA2JFMuXJJ2LM+40bU+rs29mvGKub1Zrtvo1ztb3RZYiMF71FtxYEm5+t+laWOM6VIfa/YhtAPdpv3uIxJk5xbqz207dOTAWHSPevswOJkXkntd5Rk6IkolfEmQ5nyLN2FKPu3veS5eZ5O4hJPcEU3P8ALcsaZeKfeJhomNYbKftS+/0V9prLcnGfCXFqwy+Kry5XYbjlItKfxIKKkYZVpJ1MpVBiNUpaPymZKkTFD+zS3d32cMwzcH8VMLpAvhpsw0WI4NVILsoKpziFKQHCRMFdh9OlKmJEuZNQktMvtIRzDEZDxMHEtpehoth2EiWXBVDzDyFNPtLFbpcQ4ttYBFQqxtjyvr6CjxWgrsLxGnl1mH4nRVWHV9JOHFJq6GukTKWrppqbcUqop5syTMDh0LUHj0xkzptPOk1Ehapc+nmy58mYgsqXOkrTMlTEk2CkLSlSSdCBGEWeQC5PNppKHCVLlcxjZctSqBRMDEuwxJFqFSmq0pqepp+SDM2X52V8z5iyxUKUufl3HsXwOctQZS5mEYhUYetSgAGUpVOSWDOWAA09MMNrE4jQUOIS0gJraOmrEAOQPvclE5IHYLsQ5F35xYHVWAGoHKt1G+96DU8iTuMfPQGfr15fAm9ttIzSwPQe/wCdztre0W9ZFSdgCTUW0oK9TfTrblmygWHPTU6na5s1hyNt3czC/T1N3HRrNfXbSLe8q/yNTuqpPjuDf+IUpjLlg8Tv5t2CW+fcPvDQe/m+wtvd+Z1Yavb3FD4vAkV5moHTc77HGYkP2JCWHJx8LesVFyOQAffqfJyduTxbnCKU0oeegFa/OtdLg6YzkAAW5W2d7fDTfTUxUnRtwT3J19zgbuG5PbnTbW/P+0aGp8KnyPPGZLDOeZDBuQAa3PSCRpbVz5AWI8z8Gi3um41p8Sjf0rz1PpjNQLpH0+vxirflDcydrEh/mNi/lFudpXlUgeBArvsCSL10vvjMRptr/D5P56CKh7O9gSW3d203Z+0W9ymh3rX+8fxOM6WLdmHp/Fj8YoG1bcm+rAA+rkHlq1tcmfstJwpnitxJkPfomZ8P2pwpupuqR5klcElVND3RP1iuo79N8ejP9HNiSpPiNn3BgpkV+SZGJqTupWE47h9MlTb8IxtSXu3Fs99eftGUwXlvL9Y15GNLpgf/AOcoKiaR5miB6tGcLHr5GoMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaAXbmjlzDtn9qp9w1LfaA4rwIIr9yW50nEtbGmqEQqRpqmg0rjVvMyuLMONl3bFK5J/2KiYgD0SI0VzuszM3ZnUdU47iiR/8A2aybLHuQ0eYknTw+mteWop05Y46oXJ6/HRvQv19Y4moO55+VlCze9+vPWJqDXyOvQ1oPWhp8qjEStQRu+mvcdxYnYREfxIPZz5XI/T6MTWySAOlvFNaV6WviM2JbTbsbiIy7DkPn59PV4ntq0PLn4UrT1tzBvXGMoaj4d+uj7P3iE2DHX5g2PoWvsUt0nMm9LA0oATuLjTzO9bU6QHy52ffXXty56M0QqFjqzvzLEXb4bMO95zaqEai4URpY2NeVNac611GI1jfmG68ww66fweIxuLdD57c309+jxObIrTb7vPw9QfzNsY6w47X+voxEoXP+8O41a29ifUxDnsjgczySZyGZpKoOawjkM8UgFxpdlMxDRWCgPwsQ2zEsKUCEvNIWQUimLULKCladUnyIL2Ouo4gbaR2H4Q+KWZ/BLxPyV4q5NnplZhyTjlPi1IiZMmyqfEKbhXTYpg1cuQpE7+rMewior8FxREtaVrw/EKlCSFEEYyswyePytPZnl6aI7sbK4pcO4ruqSl9qiXIaKbSr4vcRcMtqKhyDQsuoJNa4+ykpmJCkkjiDgg3Gx8wzGzR+1/we8VcreNXhnkvxUybUioy9nXA6fF6NJnSp8+gnlS6bE8FrlyD7MYpgWK09bg2KSgB7LEaCplFIKWjNx7AaVpmHa/4hzFxAWmRdnrNEW0sgHuxEbxA4ZyxIBuO8uGi4yhGyFihuFdneE8kKzFWLKQPZYPPWG0Cl1dFLYciQpVg4NzaNR/6SLEFU/gflikSoj+sfE7B5K0/3pVPlnNtWSf8ADNkyXIs5Ta4jaY7SWYV5X7OfHzMTDim4mTcGeJ0fBLSTUTBjJc7MuUFA1TWOMOkrp8Ne/U0rjb3wyoE4p4kZAw6YkKlVmdMryJ4LEfd143RfebHVpAmFt2bd48FfEeuVhnh7nvEJZKZtJk7Ms+SQSCKhGDVn3e4uHn+zDjR3jTVh4ugFFct/Cg+9rUeHnj2kmSX0uw110fpe4t10tHj2ic1j5X0bS/MdfIjSL1DxwtVV9zXw/mpavWhF96Ya5OxG3LvruNRfludYzETdLuH+n/XVrbxeWI3Q963j4/zWqNTzB0pXGGundh077227W69YyUzjYufWzevk2w1vFzajyP3j5n8e9Xnev0OMVdOC7i1/P3NdtBr1jJTPu+3dzppz38nuNYntzDT4r+Nr+YrQX33xjGm7nf56MRvfvdonTP2cjTr8eW7PEtEf/NalrmnpX6b761iMgvoPfoNNND9cokE4WLhvN/UW9A3KKojhuoU6G/zXi0yDsn3q/Q/CL/b21/5vr0aPwx4vRQp439Ar6bYewO6f/F+nyHSBnjmf979NfSKS4/8AmseppXwr54vTIL/lHLS/vF3iwzhzAew1fk30NIiOTDfvf8Qtp1NL03GnPEopyGd7dPSzD62aIlTxu56P6v57HybSLe7Hg/vddaC3P4q+BO+thjJRT3snW2ndtgPntYxAuft9cu55873GkWt+OF6q1qKWvborf0IrvjKRTtqNGb9NLe5g12ZsZc7mX18/JvotdtbNER1RTvAUrShPWlq8tN6W0OMyXJ5BtOvnoPXdhfWMZc2zu3NixN/Kz395YuI7a7M+a3MrdpTs/wA9Q4UIl/GnhiuKKSarlr+dJNCTNoUJJL8tfimfBw1ChUHiXiXhScT8N8/USkgmoyZmYSnGlSjBq2bSqJNv7Oplyl7XSzgsY5R4dYmrDvEPI1alRCZGb8uGaQ7mQvGKOVUpcX/HTzJqCdL3BGu6s8qhIrQiqa6WCviV531FNzapPi4LgHnHsKbEjlGHXjFDJgeKXECHAIT/AJVziJSNgiNjHI5CQOQTEhItcUqSbH8u/wBp7CRg32jvG+iQOFH/ALS811stLcIRKxfE5+Ly0JZvwol16UpAuUpTc3VHof4d1BqsiZRnk/i/qDDpKi5PEump00q1E8+KSSeSjpy6rdVtW/1JFehtS1d9TUW6SQLi1umwG3JjuNW6a8x82G/1/EXAiCtVAdBudNE17t7itxTWtNBQVzUhhroGt118tfc8XNcJ6382floBfzvFudVXTfa2/wDS3iKVtfLlJYP6a6egd9+R2vAuXv68gzORYuQ1t2YveIDyrUpvW42Gx8TWleY0qaZcoOR0D2O55dQCH7FwbRVLlyzuW2e7kt5dQO8W51Wt76b35725HWvnjNQOnXpaw+fmA2kUN3630swsOw1826mLe6dwfTS3wjTzNfDnjNlpYAer9bnTfsOtovA1HkNO6m9WsOTgNFvcNSa1pUDyFyfkeeltcZksany+vQesUNySNdr87Wba59x5vbnSb61p4/eNd+VL8wDuRjMQA4Fuemrbt6fxiuxI0sBoGAs+o3dvKLe6fvHlW3hb5E19NMZyAbdfiT+gHqYoA3MOydtTc/He4eMivsvP/wAwGcL1I4Oz8GmlRnTh+fW9D4DTG/n9Hd/+ejM+oB8L8cIfl+1mSB8ifPeOh/tEf9isM1/7VUQv0wnHD83jPJj2WjTOGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCP5+vbah1QvbK7VrSgQVdorjNEAHUJi+IWYItB8FpiAodKa41ZzICnMGOA6/1viCh1C6qaoX6Ai3UtaNFc5oKc25nBDPj+LqvuFV09Q9XfsR5+bGyKV8/Ctulhep5U1x8FYLjqG+bfBhzjiZvbl+Hu36sGHN9N5jRrbxHgbkHXX+tMQq0fl776HodxEY1IvbTkx+m7C2hia0r8xtY6+FqYiO13O937X7Fu4MRsQSPLqd/ewbvaJ7ZtS1rcyKaV2pTX+Y8jiFYv/LoPXTy7RCoXPViH0trZ+THQ2cRMaVfnvTqNjUitRYakioub4x1BvhyBB/Q63YG7MbRKDHcPbrfTt7hfoIuCToda3vQnum/Qa+FhzGIyNt/Qg/KIjY+6zgcrb6M+t+Yiag2F/ukA16Uppp3q3Na1p4YgI9/Lr35afwixYs9ufRruO2zdOV4mtquP5rgbAjXlqK7E2NKi2ICGJF/r6f9IiUHflz3bnpqDZzuw1BMeau0hkL9rShjPEsh1Lj5G39nnCWRVT8lUsrbiykUUVSp9ai4pFT9iinnXT7qCSUZtHN4VGSo/hU5SDsrcf7QHS6Wu8e0P9EP9qYZKztiX2b84YlJkZa8RKxeNeH1RWzPZIw3xAk0wl1+Ay5ymlJlZywunkGilTloCseweko6Ljr8wKlzsg//AEfSZNs9q7i9AKICo7s6TpxhRVSq4Lidwvq33eam4pxyxp3WlVrWuO4/CYgY9iCTqvB5pB6oraFw7t+8SwFmZuXpt/SRylTfBvJM9LkU3ifQIWG0TUZTzcOJ9glclKG3MwaMQdmftgQz0d2Tu0owwFKdRwP4nRoSknvKRLcoTaZutilytTMK4lCE1KyQmh7wGNw/CKoRTeKnhxOmEBAztlqWSdAajFqWnSSdAy5qSSWAZ3DR4O+LElVR4X+IctAJV+xmY5oA1Ip8KqahQDXJKZRAAuSQBrGmpDTCw+LlvQ/83T9UNfZZE7Y30DG+77i/La/dz5ClA21+vr1bYRe2I8Gnxaa1Pht3qdfHyJm/AvoX3/lZ2ufQD920KUn4fXr6Ns0XVmOpSivRWvhVW3I28K4iVI5aM7j+XxDxMmexu999O2nPf5sIuLUwI/eB89deStefyxjGQb2t2Y28rctWblE6Zw3IPMcn68vlyiciYDc8t6mg5fFpy1HzxCZAuOEvt/MD3fQmTOPPo4uOu2vqTuYkpmI/jGtqk1/5rXxEacDlbZv/AExeJwfXTQBwO+hPw0isJgCB8Z/3qfVdfXD7uOl/rk3pF3tyf3gO5L+d4GYAA0WfWv0USOuH3dOtrfWnDeHtj/efsSfgTFBUwT/HpyJ+fx4qKccgen0mLTOGxt2JY9LDXz0iM5MRoDXWwPpX4vy6YlEgacJ8wPn+sWGbu576dLcn8n3iA7MCa/FQeNetAe94/qpxOmQXDjRtveSw+fS8QKnAXfbQfT+nS0W16N1Pe3533t97XfrXUDE6ZATqG3fd32cX7huvOIFTuWvr1fbt0u+0Wp+PAr8d779P7Wg2rpXlTEjoRyJA/TsT5tzaInUv67/q3o8fdcD0vTrjtwRk0N3lxE34x8LpVDoQT31PzHPUhg2UppUhSnHUAUBNdBUEY4lnqtRS5JzlVTCEy6bKWZaiY+gRIwWumrJdgwSg23FtCI5PkqlXU5yyhTS/xTKnNWXKeWA4PHPxmilJZt3VbW7NpfeafcBUs1sVE+Ve93RvW5ruLlNBUY8TBYDsI9lzcnuYxBcbopMRxYz84gghOZItg3BHvIUNQqxufhcZWDyINDUUP5j/ALWlVLrftM+Ns6UXSjPuK0ZIL/2mGy6fDp42uJ9JMSRa4Ym0eg3hnLVK8P8AKKFAgnBaecAR+7UKmVCCO6JqdNY6gWok02H5Ene/+7S2lRQdAykjVuXrt6b7vqTHOufqRo+jX1PUbgekF1dPGmnSnwjal7kVN6m9yMtKXIFmFn2u4O9/TRj0Nb+avr36P/iEW9Zuan/E668uvLwGMxIYdrt8rfLuTqYp0Yudumo/W/TrEB1etNBpypoDqdTXzrU3NMuUki5N1HfZ+dg1m/TSLrB2/wANzoTq/kGBFrRb1qqfOlep8T/jTwGM2WASPJW2gsl/jbRuetBq/IOH3YgD9Lcm5mLe6oXPLptoNCdddKmtRYgDNQPd8d7HcaOLN5xfpzJA6n8SvoevMxAcIpTQ+e9yRroAaDn4Xy5adAe+nncd2B0taKC1xoLnTU2G578rvuGtzqt/FRFedk25HUg6UFN8ZktLnTkB9dPdA2YPoCDqe47a3HI7piA4aevyAqd/EaUJoNjjLQH13v6sBr5P5wFmfk+pFza/k515sNIyL+y6P/3gM3jnwdzAfXO3D63Sm39Mb/8A9HiG8aMz8/8A2X40PTNeSfm5PUmOhvtEf9isLF/+1FEb9cJxs3Hnt1B0jPNj2SjTSGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCNDL2k0jVlzt39pyXLT3DEcSo2fhOgKM0S2W5lSul7uNzYOE2BKqnXGsucJRlZmxhJH5qtS/OchE9JZtxMD7kRpH4hyPu+dcySyGKsRXP8qmXLqAR3E0E9+8eKmlbW5eVtem3hWgtji6g47X+uvLrHB1C56hx30LNu1+4D2ia2qh6n6pr+RxCRqNm9x5+vrESrEEae9iHHnt3LDWJqCAa7a+RrXzrW2ImsRvu+zaN5WGr9ALxrDEHR/lv9conNq0Olu71rqm3yvqTzocRLDjtf8AWI1cwNLjtuH5a928omoOnqKHcC9PpenkcYyxv5Hs/uboD1DREob+lvMeln0azWaJzSwoUqDbl+6RU7AWOtdqb6xkHd9WPfvEKhbvy5iwHWzswHXpNaVSx0sDrvodhrY03vYjESxf1I8mcfMctA+1mobcD1DBwednPTQagCYhR0JoTSnMEX8aEnS1AdjXEC0uH5e/6EREXIZ+VnJG4HUG76i5L713WoeLYehYpluIhYpl2HiYd5PfaeZeSpp5l1JstDralJWk17ySqoNsR31BIUCCDuORHbTzEZWF4rieAYrhuOYLX1WFYxg1fRYrhWKUM0yKzDsTw+ol1dBX0k0AmXU0lTKlVEmYx4JktCmPC0ffeyQa/wAy/tJZJkp5akS3iVw94j5ey0+64CIyDbk3+XjEMXFULkVCJyRGQTzawHHYmFDyEKbdaW52z4WVqU5mp0kgKq6SspSl2/tEShVbk8QUmlJTvcA3EfpVzb46UP2tPsCYd4oSlU6c15PzDlil8ScKp5Xsf6ozfQVErLmJTpVMCtMnDMaRmKhzBhSpUydJk4disuimTU1tFW09Pt5Z2y+3nPJGc8nPAOM5tynmTLDzZIAcZn8mjZS42SqwUpEWpJKqggmpIGNqcFxBWEYzhGLIPCvC8Uw/EkKv+FVDVyapJDXcGUCGvyjzCxnD04tg+LYUscSMUwyvw5aToUV1JOpVA90zSL25xomqefgYuJgYpK2omBiH4SJZWlTbrURDOqYfaWhRC0LbdQpKkKSFIUkgjvAg+19PVInypU6WoKlzkImy1JIUlSJiQtKgQWIKVJPECQQQQWaPGGdTrkzZkmYlSJkmYqVMSoEKTMlqKFoUCxSoFJDFiCCC1mubEwrT4q1pubaX1pawqK9K6DNTOt6nmOz97nR/UmApO4226dtG1ux7GLuzMiB962ouRUHlfYdb89sZKZ7b9Du3nzsNrFjq8RlAOmr2829wfQAcupuTUyr+9YEbn5XsfGmtgbYlEwH8wDl/kC7X2253Ooi3gIYg7WLkP21fTU/rE9EeDQFVCBzVXfrU/LkK4ueWbjm1228hcWt5PB1jc32Z3b3fyfkYkJjhaqqjf71deYJGmnlXlgZaC7Kt6A22sfrTWK+1UPgNbHqDy+jFX7cP4z6n/wB7FvsUbMfQfECK+2X09I/DHAarP/EfW5t42w9ijmPcfgkiHtl8x6RSVHUt3hfl3geupH65a4uEtAuVAD1HY2DdPf1GYouz9rm/TbqxtYxGXH0r8e/81QOu/X8dsHljYH08tBfrodWi38Z5uH6dQ4t8eWj3guzH+a3iRpY0ub1NK3F9RbFpnAaABrdbg7sTtbQ3aAQTvvq293v5adyCYtj0xN/iNthXf+9/Q7d6mIVT3cvz6XG3utfoWGl4QPVwH2tvtvztbTU2d+YG/wAXoTXexuLim1d9wMYyp2v8hps9+9xvs8XpST9dB6nRiSLesevvZ3ZbVnrtsdnyVBCnUSnO3+WrgSCot/5ASuZZ0ZeINQEtxcihrnQ0CSFUx034840MJ8Jc7z+PhVVYQcIS9nGNVMjCVpGl1SayZ3a4YFu3PAzCDi3ivkqSUlQpcW/rZVgQDg1PPxVCuQSmZRovZiRuwjc+ccJqAbU51CQb0reqj5062r5KgOWGpsI9W9IwuZ2mqJxm7NU2QrvomeY53HoWDXvJjJlFPpVW4PfS4CCTShG1MflJ8UscRmvxR8R8yyZgmycw58zdjUqY/EJsrFMfr66UsK3CkTkqcaghnBj0ny3RKw7LuA0CklKqHBsMo1I0IXT0UmUoaW4SguPXVx8e4sAEVFNT4W7oFgL+dRT7wxw5KWA17/E+T/xtH2hfl12uz7OW2Ye4mLe4v1v60pyoQB8xS9KjJloA9x67t+tub6Egix1e9y2oHfdxvzYvrEJ1VAb9COmpOoOn5igqTlITxEC3MnpozsRc+/qLVHM20bk+g12De7eLc6rb09LDTa1dj6DGchPL3bXBO9n0DPuIqeTvqOr7nnfTd76C0QHFH50Nb9SfIWqdCfGmXLSw6nTs1g30fcIqkaPsyraudB1/kNNYDqhuRa58NtNLj5DGYhOgAf17t8tyH3gdhZ7k6b3LvsNW3AHcQHVE2JAvTrcgm/oB1TyF8tA3+uXrc+RHlUc21udWAH5dHA2J5XeLc4oUr/FfrTYX5/M13Jxmy0sL9nHMuSfSw1a3aKO501sDfa537bM76teA6q5G33d/Ek11t8zfXGXLS5FtLiwO7BvMnVtAdou5aMTy2GjkdLh76DYxko9lrBOu8cM9zMD/AEEHwrj4Fw7B2Y5uyi+wOlUSt8i96G2PQf8Ao76OYvxZzfXgf2VL4dVlGthb2ldmXLM6Xf8Aw4fObnc7Rr99oqckZSweQWC5mY5E1Ox4ZGGYmhZblxVKPc8Z28ewsadQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIRpKe2Ty67l/2gPFiKcZLTOaJJw4zJCLUCBEsO5EkUlfeRspKZhJIyHJFfiYWKWONdvECQZeZ65TECdKpJyXGv+TS0EjW3EhY2uI078W6cyM84mtiBUyKCeg2HEDRSJJUD0mSlJ/2dWjGGhXU0018wfO2tr33xwg8+Yf683jrFQs4Fxdtbbj0iag6c/wAqC23K23gRiFQY/W7m+53vv3BiJYcdDvze4ffze4tYgxNQoEa6X8QeYG1tTppbESgxBG7D3+d+QY7lnEWH8SevwI2v6PExtexP5706Hztz2OIzr3uPP4to+8Ra/G/vv7/Vr6zkKre1TWviKWoQK2ptoKnXGOoMSNvr36/KImZ0+nY9NyCbXflyMxpVwa2NbUr4pvufDkACBiEhrcrcn1ZR2a7O78+URENbn31s2nQPZhbW8TkKvXXTTcGh57X3Oh5kYjIcN6d/r6eIiGPd/L3diLCxtExCqgdALjkN+Vq0NgdTawMJGvw+v423MWKD6WOo6d+h8+5YxKQve4071700qOVN9tCSaXhUOEg6jqPj3/VmiMh/kPeU+8ADsG1avJpo/kjiXwh4zyrvt5g4K8RssZ/h1w6HFRUykEpmsI9nDLaQ0FOOs5hy23HwBhkpIiHS1D99pDzro+zl3FDg+M4dXlREunrKebMa/wCBExPtAW2VLK5a+ctaraRuX9i3xzT4Y5xzT4a5nrly/DDx6y5U+HuaUT5qRQYHmGtlT5ORs8zETVIlyTljHapCcQqkzEmRgeIYnWexrJ9DR0x3PpfMYWYwcHMZfFsRsDHwsPHwEdCPNvwsbBxbKYiEjIaIaUpp5iIYcbeh3m1KbeaWhaFFCgRuklSVpSpJCkLSFJUCClSVAFKgRYpUCCCLEFxaO758idSz51NUSplPU006bT1EichUudInyFqlTpM2WsBcubKmJVLmS1gKQtKkqAUCI08PaS8J3+CnbB4oQTUucgMvcQ4//O1lZYQEwkTA55iYqOnggUoSENQ8vzmzmeVtwiUtmEagmm0NiGVDuOep/gJm8Zo8MsuzF1AnV2ByBlzEAS8yXNweXLk0ftiSVKmTsKVQT1TTxCaqaok8ftEp8s/HnKhyt4m5glJkGTQ43POY8PIDS1ysXmTJ9WJLAJTLk4omvp0ywB7JMpKQODgUrxGxMSACDXQnntf7vhUfIk1x3Yie36mz9y/v5ON46ZMsG/qN3521tqB2Di0XVqZbE9aG2m9adOe4qTpjJTPFr9tOfpsT3IZtozK1tz08rjmPVukXJuZDY8tPA9N9zb8MTJndX5v5an378zFnAfre/a3v8onImX83Sh/CqevLamwxKmd101Y2ctr35vr1eLeE+/49dOwfoIkomXUeGv8A3bdbYv8AbfTae/8AWLSkjZvL4bRUEzI/ePz/AARi4Tyd27kj5xRhyHoIGZE6q/XmjAzyN37En5wYch6CKS5l1B/Dy7t/Ei3mcWmfvp5fFz8IuCSRo47Dbv3+miMuZVr8VjsNP+WvyGIzO66XBJ/S53Gv6Q4SdL/XPQ+RMQXJluVeZt8u7rtobHUYiVO6/L3nyHnvF4Qfht387/7PnFsdmOtzvpoB/u/hfrTEKp/XzcHTa57ta4NokEs8r25uGAu7X7dPy2i1PzCoI71NfHW9yOVOVOgxjLn7P5u3vfk2j92iQSwO/r3udXA306sDGer2F/CByZ5s4wdoSZQDhgcvymG4T5SmEQ2DDLnU8el2Z84rgVKTaYymUQGVoVx9HdU1A5ofh+8pMW8lGl/2uc2hGG5ayXTz0+0rKleYsSkoJEwUtIifh+FpmjX2NRUz8QmJQXCp2HoWwMpBO5P2SsqmbiOZM5z5KjKo6ZGXsNnLDy1VVWuTX4mZb/8Af09NJoJalhiJNetBKhMUBn/4qZpOUuH2bJ826GImEk8SzAOlVPdTKYBEuly0/wATiY6LYcCNapOgBJ8rftF5+V4Y+B/iZnORUikxDDcrV1Jg1S7KkY/jfBgWAzpYcFUyTi+JUU5KQbmXf8IJHohkTBBmHOGX8JXL9rIqMSkzauWzhVFRvW1qVaslVLTzkk9bXaMPZPdApyAGuwoVeAGiiRy6j8v0qWEJSkCyQBzLAMB3LdbubtHoqSS5IAJuen8Tqdb2fWILrnXmQT8q/UAeKcZSEOe7cttW3sLXu+ouHbN9HRxb3+VywiEtQ3NgD40H4nnzOtaYykp5Dfyf+A2vYaM7UYmw82Nn92l/edNILi9/IX21AoBzNVG1/nmS0N1Jfb+dm0bbnaL+Tb2GvIORYluWhAG7kRAcVr00G1fl+tNaYykB29f9l99bndm90U17Cw9Q2xYk6nryBEQXFa3tz5getyRseQ2oM1Cd9rN6fIHl2La3aa8wTf8AeO3YdbaX1MW9xViTvrzp+6K6UFL389TjKQk66cje/nqTu3VtQAKC+rEncG7Wd7vyTz184DithvUA77FRJBr0uBztZOMxAuNwNeXT+Xxip0fdRDDp6+ezE6uAYgOq12r+NgOV/Gx6VIzEJsBye/vL66M3O3WKfOwu1tVGxb5MBqGBguq180jXU1JN9fTblplyk2BPfTlYBwex05jYvXY+YGmzsOz6jTmNTGXT2UErC47jZPFIBLUNkeVNOUugPu5mjH2weS/s8MpQoLtpN629QP6OPDQanxWxcoBKKfKWHS5mqkidMx6pnIB5LMiQohv3EuY1g+0jUtKynRg2MzF6hSdiUJoJaCQbgp9pMA/xG7u2ZTHqPGrMMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaqX/AEgnh9+zeNPAbik2P9HnDhpPMixSUI7qUxGQczOztmIdUEgLfiYfiEWUqWorLMtQindaQMdLeKFIUYhhtaP+/o5lMWDfipZxmpJPNQqynshnEazeOtB7PFsExMWFVh06iUALcVDUKnJUS35lJrykFyWlgMAlxr/tqJGuhpsPA23Na9a2NjjqkhifUfMc7aXva4vbok3A9C/1p200OxM1pVRT/AUF9gBUeNB8o1Dfy9dO7G7e+ISGcNYctSCbW3Y9RtExtWnqNrGv631uCK4iI1B+vr+RiPRRfd+wIA6chq7dImoVQiulj5GtCeuunXnTEJFjfQ++w2G7WPe2piNQYvzv5/Xxia2r8BS1jWx5fOleSdY1Bx2/TsfgYjUN+VwNbEaef8eUTEKuPpfU/PTSo9K1xjqGrfEXGra6c2I7lmiJQcP/ADbR+4Lc9RozRNZXUAbkilTW41pXmKior5CmIiGLfTbP15hhESg4fkC458j2e/ruCIloV3SKaVoOgNa35crgDYVpixQcH6c/XRzo4ER8wfo2bnpfkdRExtehB6U6frQ6E7aYgIex+vrffa0WKB/Uc+WxuDt35l5SF0pQ22IP3a0oPMnnQaVFARCQ1iHB9/1t02YtES0pWCCAoEMoG4ULuS+zWIL3cFzrsnezs4xwnErs+SLLDzndzHwlTDZFmcKpaT3pHCMKOTI6HQmqmoIyJpMlaaVQiMy/HhCUMfZxjavwyx4YzlqRTzFk1uD8OH1AUXKpCUk0M4b8KqcCR+K5mU00/lKY3o8KM61Oc8tiZitXOrcewud9yxWqqZhm1VdxAro8SqJyiZk+fVyQUVVTPUuoqq2nqqicta5pWrpL2unZji+NvANjillCBiY7iBwJ/aWYPsUHD/aoifcPY9tg50l6GW0l9cXI0wMFmqDU2XO7BSudwbcK/ETRhxjc77OHiCjKWb14DiE5ErBs2+wozNmL4EUmMySsYZOKieAIqvazcPmghLzZ9JNMxCKdSV8D+0h4frzZlBGPYdJXNxnKRn1nspSOOZWYNOSg4nJCUjjVMpRJlYhKIJaVT1coS1rnoUjU4ZmVgQq1AQQQfOybgbHS9iNB6MpnX1vyHR9QfN36WvfznMvcfXT4W1F3eLo1MtB3vz/5fy863nTO6tbct878/PWLChQ69ouCJlTflp4f2a/S2Jkz2a5/hzccx3i0jmNemrd/oRMRMqU+Ijobjz+HEgn6OR6/Hme5iwoG1vf8b+hESEzPkR4/07oBxIKjd3POz+4xQoD2tzP8Gv6xU/af86fT/wCXD7z19/8A6oez6+7+MP2n/On0/wDlw+89ff8A+qHs+vu/jFJUz5keP6SR5YGobduelx1c6GHAL9mBd/kPRyIjrmVa/ETvyA8KJ08xiIzze7XuHJ9NLDf9Wi4JG9/QfDXzeIS5jqa3O538u7z1FOtd8Rqn63brp2Or69t4uCeQ6aefbrbvFvdmX8wFtAfHT4f1ep5QqndX7XOvM9vN9IuCC2w6fyiXluUZgzvmbL+TcqSuLnmaM1zqW5ey9JoFpb8bNJzN4tqAl8FDNIQVqciIp9ttJoEoBK1kISpSfm4jilHhdFWYlX1EuloaCmnVlXUzlBMuRT08tU2dMWolgEoQSdywAuQIzsPw2rxSuo8Nw+RNq6+vqZNHR00pJVMn1NRMTKkykJAJKlrUkDYamzxvZ9k/gFKuzBwA4dcGZdENx8dluTiJzVOGUIbTPc6TlxUzzXNWkhIUmCdm8REw0obeLkTDySFlkJEPvusLeV5OeIWcKnPmcMazNPSqVLrqkooKZSio0mGUwEjD6ck29omnQhdQUhKF1UyfMSlKVhI9ZPDzJ9NkPJ+C5ZkKTNmUNNx19SlISKvFKpRqMQqEgXEpVTMWimSoqWillyJa1LUgqPUva1z024qSZBg3ipTKk5gnaUKIbS4UuQ0ohXDWq1htcZGPtLAS2hyXup76lAteKH9Jp4uSJ83J/gphVUta6WYjO+b0yltKlT1S6mgythk4oU8yeJE3FcWqaaaAiVLn4JUpMyZNH3fdf7PWV1oTimbqmWEiYk4PhRUAVKQFInYlUIcfhTxopqaXMSSpSkVcv8ISfaeHXHK13+VdKAW+5yAuceTCU9Ow5aXNteZjZ7m3mfXkSC4+mcmGtVfM+FTt4AbD6k4yUpYNyuT/AA93xsLNO7e7X1I12A66Q3HPSnOlSB96lrbAmxFQbYyZaNzsXTzAOxLuCz22N30i4AAFzprbW4tY9nvZx1iA4utq3/O5Og150HqDjLQO3lz0AG2t9TtpaKa8uulh7hu9jctoYguKFDtb5E+f3gOQoOYOMyWgjub9reVgdD5sS4Nwt1uyR1Gp2sLgkDrreILiqn633JFE7mmldtNaWykp0G3y+F7+h3sXyFzuTqTffmObA6AiC6vTnXXruRbRI0voK7hWMxAa/wANOp897fMCoG176h9Bdk35+Rvfrb3FWN7ECnQD1N/11y5aW729duWlz1YiKOSdeg9znUPodQBbQG0QXFa62Phe3gbDnY2rcAYykJdg1vgBbfmer2OgvFddG5DoB17j3W3UIDq9dKCo2rWlztTlfx01zUi132ezM/PVvQ8gAGYddLCw01IDNawHWzt0jPh7MLKK5LwDnWZ4hkIfzrnybRUI/oXpNIoKXSOGSRStWZxDZgFakUWAAkhVfZv7AWWVYT4OYpj86UEzs1ZvxGop5o1m4ZhFJRYTISbay8TkYzoSn8dgDxE6YfaCxMVec6TDkKdGEYNTSpif7tVVzp9XMOrfjpplGW1cXOwyQY3mjomGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCMJHt3+ErmdeyVlziXAwwdmHBriTKJhMXyuhYyjneHdynNUttgd5x1zM7+SHCQoBuGh4lxQoO+jrzxJoTUYJKq0h1UFWhSjykVAMhbDcmcac9ACeo6f8acLNZlenxFCXmYTiEqYtTtw01Yk0sxhuTUKo+gSFEgxqBNK0rSlKGh/msbDwBIFfC1OhlDdnLuH5Ncb6M7G2w3jVA6sHu3Qudr7XI18zE5CqHbxrpvWt9RenhfEZ9x5/V4sUNDq23N9fSJiFbjmafiLeda0JvamIVBj2Af9flZwNHeIlBx5C+vY3207WuDExtVQPXlXmKc+XLmRrEob+Xbkeje8tZ7xYfxAhmPXY/Xu7xLbUNP0R8jblXQcq4jOr+u9/rsNWsIi6GxHx58gNtRsbtE5Cxp4UF7i1/HoKE21JFIljf1+m+tLBojUGPIPfoevIEgag3G0SkLuDrahqdQdPmefgDYDHUGdu4YaFr6bED9W1MSh8fgbjfyIdueoia2vvAdQa6Co/i1Gm513oajuxmx+v4RGoee29jo2/kNL6j96U2sjka22+IX6fevbY354jUnf6GnubkHHa0WAag7e7nblz38gYloXoQbE9TS4FDUi9Bfn40JiUl7H65Xvz2+ERqSQ/vHXRwBr1exEereyB2hIjs8cX5VmSMeilZJzAhvLefoBhZIXIol5CmZu3DkFD8blqNKJrDAJTEPQqZlLIeIh0TR5eOV5IzKrK2OyaqaVnD6kClxKWg2NMtX4agIuFTKRf8AbIFlqQJslKkCcoxzvw3zivJmZaeumKmKwqtAocYlIJPFSLWCmqCLpXOoZpFQgMFqlifIQtAqFKO0TL5hAzWAhY+CioaYSyYwcPGQcZDutRUHHS+NZQ/CxMO82pbMTCRUO6h5l9srbeaWhSFLQoE7eSpqJiJc6TMSuXMQibKmy1BSVoWAuXMQtJIUlSSFIUkkEEEFjG+kuZKqJMudKWidIny0TZUxCkrlTZU1AWhaFAlK5cxCgpKgSlSSCCQY1FvaidhaYdl7iJE8VOHUoeVwB4jzd6IgUwSHnmOGubZi69ExWSo5z3akQ0jjXPfRmSIlx0gwHv8AL7qlRUmbipn6JeBni3Lzrg0vAsaqU/tXg1OlE0zFJQrGqCSkIl4lKALzKqWOGXiiEpDzSirSOCoVLk+dfjt4STckYzMx7BaZRyljVQpcoSkqUnBMQnLK14ZNUQRLpZpKpuGLUoj2QVSKPtKZMyfipamWnxD1BvzrTQbm1+e+wYqNXJ7X/ju2jlnjXwoG1v57c9+fcARPbmRtem1QRXUgmlPClhbXniZM8XvuNN7Pq+o1a/TaLeDbvy+HL16gRMRM/wCaleov6AEeeJBP6976DZnd+ul4s9mHFhvt8mfZ9PnFYTLmpJ31A6X+Hn15ed3t3A67t/H1tFPZjRutyRZ+rRVTMzSykEf2k1+YqPD5Yu9sOnoYt9mOZ9R+kfipmd1I8O8N+dBfxpTD2w5j0MBLHXzIH6RTVMuSk+RB3HQH62162mfa9tA7X+LRd7MOLe8kdrP6fKI65nWvxC1rEVGmtRXmLH0Othn9S7dBa+mz6bfIxXgF7DVtHbqzONNx5F4iLmRv8QvzItvUig+nLxxGqf1azXPuB6A7WffaL+D46+XL+Om0W56ZgBRKwlKRVVwABrUkgUApUnQbkVtCqe+76s2rdtLizDUltRFwRvsA5fTfct0t7jGzv7HLsER+R4OD7XPGOSvQWa59KohngtleZoch4vLuXZxDFiN4hTSEdaacYm2ZpW87L8rw61qEJliNmE0fYciJ5LHJXpB9onxal4uuZkHL1UJmH0s9CsyVslQVLrKynWFS8JkzApSV09FOSJtasJBmVsuVJSpKaWcJ+8f2c/CSZhMuV4gZipVS8Qqqdact0M8KTMo6OoRwTcXnSylJTUVshSpNCglpdDNmz1IK6qSZGdrOmcZXknLc0zLN1n7HLmStDCFJDsZFuEohICHCjRcRFvqQ0ip7iQpTyyGm1qOhPit4l5d8Icg5j8Qc0TVDDMBozMl0klSE1eLYlPPscMwagEwpQqtxOsVLppJURLkpVMqp5RT086YjdXLWXq/NWN0GBYakGorZvCqaoEyqWnR+OprJzAkSaaUFTFsCVEJloBWtIOIvM+ZJlmqezXMM3eL8xm8W5GRKu8ShHfISzDtBR/0cLCsIbhodofC3DMNNpACRT8xue86Y/wCJOdMx57zRUmrx3M+KVGKVyypRlyTNZFLQUiVMZVBhlHLpsOw+QAEU1DS09OgBMsN6IYLg9Fl/CaDBcNliVRYdTS6aSGAUvhBMydMb806omqmT58xzxzpsxb/jL/MqXX9Ur0A0HIDWlq3OONpS3zLe/ctp6R9QjTo5bzdyLuW1G1nuLRHHNR5WOuthf7w3OgHzyEIduWvf0/d6G5NrMWuAaw13PLff3DzOn4YLixU3rzpudheptXw31IrlpT5W1O3Xlo7N5MA4oSNrcvdf0Jbq5ABMQ1qpv58yNiaggClyK8tbHJQjQkBnsGdurcy/PRtzaoDb2Zy+wPkWJGz3A6hoLi9aUqfDXY05AbV8NcZaUt589hydrP2HXR4uPIWLMOg7au19joLsYhrXTfrWoGlyqthcmnje1MZSEW5Hc62P6+VgAXd4pbXVrMdSdg3vJu7nsLe4uu9LU10SNrbq3000BpjLQlz2PqT/ABuf4wI0BZybn1YOdOQtpcXcRCcWTWmt7eAFL+dfG/Q5aQLcti3PU/Adh1io7ty6B9Ws3FYab2s4EBxXnqBf1PlTw8KkDLlI3LXYkXFth1Yi7+bmDtcXFrCxbtblyuAxcXEBxWo0pU+NK8jzPKtTQXuMtCXI1/m3p73AuwNwYW5P5ki51BYDfkdQA8bTfZbyO/w67PnCfKsYwuGmMNlCXzOawzqAh6Em+Yy5mKaQbyRb3kDHTV+DWampYrU64/Q19n7Kc3JPgx4c5eqZS5FZIy1RV+ISJiAibT4jjZXjdfTTUi3tKWrxCbTLIdzJdzrHnb4h4ujHM7ZkxGUtMyTMxSfT08xJdM2moeGhp5qT/dnSaZE0WH59BpHfuO4o4ZDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhHQfal4OM9oHs68ZeDiywiLz7kDMEnkcRFd4w0DmhEGuOylMYgI+NUPLczQkpjn20FK3WYdbaVJK+8PmYzQDE8Kr6CwVU001EonRM8J4pCy12ROShRa5AIj4mZMJGOYDi2EuAutop8qQpT8KKkJK6WYprlMuoRKWoAglKSAQ7x/PHeh4iBiYiCjGXIeKg33YWKhnklDrD7DpaeYdQaFLjLqFoWkmqVApobjGra0KSSlQKVJJBB2UHBB10Lg+e8aHzEKQpSFJKVJUUrSdUrS4UDyIIY2FwXZorNq2JGlzpW5of1bU1oAMY7bAEbi733Gtm5a/lDRGbjsw+PflzG7DUxNbVtWlSK7eGtRtcWsKUAxYoOH1IBYfXuiIhrbMeHU99Pdyd3tEtCqHpcX2P5Heu1MQkWv3+ux5bve0RENfo562t6aHXfUgRMQrfw9fyJrqa+PexGbWL3LCz25NbSxtba7NFqg/wCIcrjmO46ddNIltuaX011323trsa10G0ZGxuD7/r3d4jLKF7k6hu/v7D3xLQvxBHy+WljcnyAqBCtOr3d9foX36d2eIhnHNz35f7Xbm5fQykLpoTrXrtpbmTc1Ota1OIFAjt7t231AGgDbNzjKWPPUHrzHQ+49mImoWCPqOW5pXWlq8611qTZ9fXKIynceR62seV9OTNyArpWR+B/dIsBUcwNDcmwoRUYsUl/q7308zcaam0Wu7hXXa4PIeeoNuxiWlY1Hhe51III+VRWvM0OIiNjp8dD+kRlPJux0NvdZtn00u+YL2eXbFhpB+zeAHE+aoh5TERPuOGWZo95ppiWxcY8gDJMzinHG0ogo6KcW7lqIdqWI992SOvKhYmTswPdXhlndFL7LLWLzgmnWvhwirmKCUyVrUGw+ctRAEuYoqVSLU5RMUqnUrgXITK2O8GfElFH7DJ2PT+CnWvhwKunKSlEiZMUP/ddRMUpIEqbMUVUMwuUTlqpVK9mumTKzH53yZlDiZlDMOQc+yCW5pyfmqWvyjMEhmzPvoKYQMQBVLiUlDsPEsupbiIKOhXWYyXxrEPGwL8PGQ7DrexuGYniGC4hSYphdXOocQoZyZ9LVSFcMyVMTuNUqSpJKJktYVLmy1LlzELlrUk7K4pheH43h9XhWK0kmuw6vkqp6ulnp4pU2UvUFiFJWlQC5cxCkzJUxKJspaJiEqGoZ7QD2ZXEfsnTKa8ROHELOOIfZ4fiDENz2HYdmGYeGrcS86GZVn5mGQVGVw/8AooaDzy00zJ4t16Gg5uJTNYqDh4/fzwq8bcKzvJkYTjC5GFZsSkJVTqWJVJjCkJTxz8MVMLCev8S5mGqUqolhKl05nyETFyvPbxZ8D8XyHOqMXweXPxfKK1laalKVTavBkrWrhp8VShJJko/CiXiaUpp5ilIl1Ap58yWibiqbmQt8XMipBN6n+Kh9D1x3sJ3XkA77Wdx05n3R0Lwh3bn3vbXX1fozRKTM6f8ArKUO5vvWnxW11p64vE8WuwHX5FrfXN6cAt7+v6ekSBM/5/mDX/j+mLxOJFz2sD6W+NvlQy+RPZh/D5RzEyt979ep+uK+36e7+MU9mDqfUfxgZnS/eHn/AIj64e36N5em8PZtofIAfqI4GaWJ79P7wH/fP0OKGcRoX62Deo6dor7Pq/u/X4RHVNK/+srrpv4/Fiwzhzfk5e/k7esVCBvf3eUUURb8U+xCwrb0VExLzcPCw0Ohbz8REPrS0wwwy2VuvPPOLS2000kuOLUEISpRAxDMqUy0LWtSUIQlSlrUQhKEpBUpalKICUgByolkgOWiSXLUtaZctClrmKCEIQFKWtaiEpSlIdSlEkBKQ5KjYORGyH7Nf2RkyRG5f4/drvLbkE3CLhZzkPgVO4ZaIxyJ921Ey/MPFKAeUPsjcMpwOQnD2NaEaqMZBzgxDtMvZejNQ/GDx9QuVVZXyJWe0MwLp8TzLTLBlhDqROpMFmpssr4QF4rLUZfs1H7gpSlJqpe4vg59n6YmbSZpz9RmWJZl1OF5YqUELK+FK5NXjcpX5Eod5eEzEhZmJH9YISlK6SZsgTqfSjLspmU9nszgJPI5LARMym02mUUzCS6WS2AZXERcdGxb6m4eFhIVhC3nnnVoQ2hBUogfFjTmbNlyJUyfOmIlSpSFTJs2YoJRLQgFS1rUogJSlIJUSWADmNxKiokUkidU1M6VT01PKXOnz5y0y5UmVLSVzJkyYshKEISCpSlEAAEkxi34occ4vjNFQ0fL2YyXZHYWt/K0vjmFQsdMIRYUhjMs1g3FKehYucQ6vtMBARQh4mVSiIhoaNgoKcOThpXgX9uX7Qczxf8AEP8AY7L9YVZA8Paqpo6NMpajJxvNA46bF8dnMfZzU0bLwjCWSsSqeXX1Mmdw4tMSnczwByqvDMqS8011JNpcSzXJlVlLJqpIkVdHl5bTMLROlqedInYmhScUqJE0ypsqVOoKSqpZFZRTwrqNazSpvTc2rpqdNf66E40fSkbW95/Ww+nIB77Dvq5O/JtG389dgBvFW7qB1FdyK0NK2AsAdx1OuQiXoTpy5EXDsXOp79AxioHbq7Fturs+g6Pe0QXHPytsLHui/qrf0Bykp+vmbNtYb9AIP79B3a553056mzCIi161O1+g5eJ21O56zy0uXaz/AO8f0u+l9ra1A5XO5se7X25mxtsfxQ1r18Li3kBTw131NhjLQkAP6eYuer9e93eLuTB7gjVyeZO2+urcohLUdTQk20B/ui3ma0F6+GUhPuOhf1PfQt0S7uDQX+L6NcufXR9CCWEQXF6nra51FgNK90VvpS9STbGUlJsBc3c6a6k+73WiugfYAW772s52+T2hOLpb12qbeNAOXgANMZaEgAfrcC/x+FwRaKNzvufgBzLkB3I0uxiC4quluRtbcm9OtCBYmoNKjGShLntqDudh6s9+TizxUDV9f3r8hYcuhCjzd7GIDqxsRyTyA/8AmG1NLXtjMSGsNhqB723PLfQvZ4E3ex2GmrMSbaDqTz0YjtDgPw9ieLHGbh1w/YbU6zmDNMuRNSkpqxIIBwzTMcSAv4FLg5FBTGIabUU++dbQ0FAugjtXwbyPO8Q/E3JOTpUtUyXjOP0SMQI4XlYLRr+/43UAKZClU+EUtbOQhRAmzEIlghUx441nLG0ZcytjmNLVwqocPnmmd/x1s8fdqFBIuBNrJ0lClgEpC1LAZLnbCSlKEpSkBKUgJSBoEgUAHQAUGP0VJSEpCUgBKQEpAsAAGAA5AWEecBJJJNyS5PMmP3FYpDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEaK/tVeAjXZ+7a/FOUyuEcg8rcRn2OMOU0KQlDSYHPkRHRU9hoRDaEMtQEtztCZqlUuh20hMPL4KFZNSgqOumdcM/q3H6xKE8MmqUK6SGAHBUlRmAMAAlFQmdLQB+VCUjYk6ZeJeBpwLN2Jy5aOGlxApxWmSQAOCtVMVOCWYBEusRUykJAZKEIBI1jHg2si9dzTmRrTlUXpyFQTbHD1JcefSxfrsdD6gPHXxsedg7aH+Btc6m+4ichWlOVddv1pXWxvfEZ9Oe1/rXk+1otIceevvHr5HXSJbaq+I86g1PiSCDStzeoFbRKHp8DoOwI100HQGIhxe12PQ7eRHuAuTrLQuljf8AEfr5ailcREOOX19fziLQ9CbbNbTr0t3OkSkKof1cfO9vl0IEZBIL837W6C40BZmsWILmxQa40PLu/ppExtelDcabVrSo1tv15bVsIdwYsIcP2foeY7+7TRnlpWDcf4G553t5UuLaQKS1tvl9Hy9CYiNj5dRyHUk3O3aJCF0p86ag6AgU89eadwDEUs/mR/EvqP46cURqBHJ9+vMdDZuvWxEtDgVy112N9SNjrSh5AVpawi7Mba9PTbraLCl9D0A30sPhY6XL6xISunXXehF6UNNRal62Fq4sKX0tz3/kbnRvnFhJFue+r77932N7xIS7XpfUHfWtrpIIJqN7g2AMZSR/LytsdR1vpFCkHr2Fx2PmOt7jWMw/Y69oWiTw0q4Xcf5o+uXsIZgMscT4pTkS7BMtobZhZXnl5S1vvwraUqahs0hLz7J9y3PW1w32idQ/dmRvEwU6JOD5kmqMpIEukxdZK1S0gAIk4iSSpSAAyKwcS0/hFSCniqE7IeGvjGKVFPgGcJ61SUBMmgx6Y61SkpCUy6fFlFRWuWACEYgApaTwpq0lHHVIzSsRUBNYFDrLsHM5ZMYULbdZcYjoCYQUU2Clba21vQsZCRLK+8hbanWX2lhQK0LBX3zLmgiXOkzAoEJmSpspYIILKRMlzEEgg2UhaSxsQdDGziVSqiUFIVKnyJ0t0qSpE2TOlTE2KVJKkTJa0lwQVJWkuCQYwtdrf2KnBTjLFR+cuz7NoXgJnyLXGRUZlxEC9H8JJ3GPqcfQUyGCpM8irXEL7jruVxGyKEgwlEFkwvNlx3YnI32h8x4AiVQZnlTMy4bLEuWirM0Sscp5aWSXqV/2WJAIDpTWezqVzLzK8pICdcc+/Zvy1mJc7EMqzZeV8UmFa5lIJSpuBVExXEoNTS2nYYVLLKVRCZTIlgCVh4UCV68nHzsCdsDs2ftCN4jcHcyRmVZc48l7P2R2XM85HTDNLKG5hGTmQIiHsvwUWO6uFObIDL8WoLS07CMxIcYRtNlnxXyTmv2UvC8epUVs1KeHDcQUMOxDjIBMpEip4U1UxFws0cypQGKkrUghR1NzT4SZ7ygZ8zFcv1cygkFROK4eP6ww72aVcKZy6im41UiJgIUkVyKaZfhUhK0qSPGH7SUhRQtSkrSSFINUlJBoQpJUCkg6g7645+KjRrvcbgjYggX90dcmUxYgg8h6aXPqY5ftP+f/AIv/AKmLvbn+6Iey6K9P4Q/af8//ABf/AFMPbn+6PUw9l0V6fwivBOR81i2JfK4WMmUfFOoZhoGBhn42MiHnVhtpmHhYZLr7zri1JQ222ha1rUlCUlSgDFMrJcpC5s2YiVLQCpa5qky5aEpDqKlrYJCQHJJYC5MXyqabOmIlSZcybNWoJRKloUuYtSiAEoQgcSlEkABIJci14yednb2R3bQ49xsrjJ5kdzgZkeMSiJi82cXWYqQTNuC7yFH9mcPwhWdY+YxDKi5L2ZlK5DKIrupMVPoBl1t9XUOafHfIuXJc5FNiIzFiCCUoosEUiolGY1va4kSKCVKSphNMmdUz0X4aaYoFMd0ZT8APEDM02VMqsNOWsOWApddjgVTzeBw/scMD4hNmKSSZQmyaenmWCqmUhQWNlPsa+zC7OPY/MtzVBQL/ABP4yQzLvveKed4aDXESmIiW/cxCch5bbMRK8nMe478OiObcmmaVMRUfDP5ldl8auAb1Mz74x5sz0J1FNnDCMBWoNg2HzJgRPQg8SP6yqyUzq9XEyzKIk0QUmWtNIJssTTuB4feC2UMgGTWyZJxnMCEEKxvEZaCuQpaQlf8AVtGOORh6SkFPtUmdWlK5yFVhkzTJHvDP3EbJfC/Ks1ztxBzLKsq5WkzPvo+bzaJ90wlSiEsQsM38URHzCMdKWICWQDMVHzCJWiHg4V95aW1dN1tdSYdTTayuqJVNTSQ65s1QSL2SlI/MuYs/hRLQFTFqIShKlECO0MSxPD8Hop2IYnVyaKjp08U2fPXwpBJZKEC65k2Ypky5MtK5s1ZCJaFKIEYK+JnaozP23+JH+RWWoOZ5Y7NeSI2GnU6l0UsQs34ix8HFuLkKM1iGedbalsXFw7cbCZTZeeh4aGg4qPmcZETUSlMq8+vtg/aMn5QyHV0OBVCqHFcyKn4TlySGNWohKRiOP1KQSmXKwqlmpVRSlGZKRitThy58upSlaJPwvBrB6z7Q/iXIoZlHUSPCzJs2mxvMkuYr2K8enSpy1YNhNcpBV/ZYpVyPaTMOlqZOGUeITZtQmr+5+y7aU4kWtSlABQeASkaDSlKUrpY08OglSiSSSol1E3JJLlSidSSSSTqbk3D+toSwAACUgAAAcKQALBhYW0AFhYABojOOa0NjyNB53qo3Jpzte2MhEvR7nYat2DNsL6EbB4v0bXoG/FyNhoLPa5a6haIi3Otdxp5c7Dbn9MhKRvzvy2t3Je/nuDFpL232AZg/Tnrf01BEVbm5Ph1roE/ncDeuJ0S31FruD11Km62YfoIqA/zL2HN2AZ3/ACuDz2iG44fACulTQ3vzJOmpqOW2UlA8tGPlq/b6Ac3WA3bS4ubWDWt01Lk6OTDWvc2poNe7X6qOw8hbXJSh9dPR2dx0axv3OwFLk/AbAf8Al5ka6C0QnXNRWnnWnofiUbaaWxkpTpuf4drfRPStrubaknU8v9nlz00d4ji9didq6culTb89MZUtDX58xqR3D8I3fyuYHrqxa+3M7Bg787toIguL1Gwsabi9h42rqdx0ykpuG1JJHd9T8B1DGFurai13L3L+4lha+xMJxeulz8VzvsN7b08dajGXLQw00H168/N2Nh6HSxYNYD3X0YFrkbiIDiya/wCFa/gNDXStDpXGVLQ5BOjB/V/0ZjsTAbbOAN7DVnve7bPZmIjKz7LHhYJvnTPHGCYNqVCZSlyMpZe77ZLbk8zAlMVN4xp7vDuxErksKzBKaKVhbOY1LV3VNoKvRz+j88PhiGZ81+JNZLeny5Qoy5g3FLPArFcZAqMRqZc1wEzaDC5EumMtlBcrHCpXCpEsnXD7Q+Yvu2F4TlmQoCZiU9WI1vCpiKSiJl00pSN0VFVNVN4iQQuhYBlKjOHj1djUmGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBz7dPs2xHFDs55e455dgWojMfAKcRD8/922RGxXDfOLsvls6WgtNrdjFZfzBDZcmyGXyGJfJ3czzBC2j75ET174h4UqswuViEpIVNw2YTMYfiVSzylExmBKjLmplLANkoM5Qa4PTvjLl9WJYDIxiQgKqMEmqVOAH410FWZcucQwJWZE9NPNAP4Zco1EwEfiCtQZKqdNDrpyPPmLjnY0v0WpLHodP0jVYjUem7g6/AO933Dhpja6U8qgD7t7baG9NDqDqaQKSQ5HvL8Q3LE6iz82sHaI+muwP11N7tve0TULof0dd+oP63BsIfqDof5aHf0MWKD3GrevToQdDziWhVdNdTpvQ1BrpfavjXWFSW7ba7DTv7vLSJQcX00u+2xtY2HLpbSShdbf189KcvG29Diwh+/wBW+tOoJBs0se199Axc66uGvqLuIlJXTz228jzoPLcWxEQbg7Al9wOXb4O4La2qDXH8nt/B997gEym3N9Ot79Dcb9RQ737xsIex+u0RkAj1t8x29d+bS0r8RSu9x9LUqbWGmthEpLdR2/if115PEZDa3vY8+/IlyHfmWe8V0r8K130NOfXba1qWAxEU8nb3ja3Q7jc6m5IsKe4PvG9xv5i3IOIlIcN6/wCGml7iwsdBqqgIMR+vrnz91osIG/8AA6+hv77OWIkJVW4qLg2F/wC8DXp/ShwI2P1tEZS389e2np7y4iqlwjfmLXTyun16VsTQA4sKOX8fX01B5i+tH5j4vfr17G3VyfXPZ37ZnFvs8uQ8rlUajNmQREpdi8h5giH3Jey2s0iFZcmKQ7HZYi3kFS0mDTESlUVSKj5LHud7vcwyznnG8sKTJkzBWYbxhS8Nq1KMoAn8f3ScxXSLIJIKOKQpbLmU8wx2HkzxLzHkxSKemmpxDB/aBUzB65ajJSD/AJw0M8BUygmEEn+zC6ZUxpk6knKcHNZwW7eXALi8xBwb+ZG+HmbX1oh3cs57fhpUhyJc7qG0ynMa3UyKZtRLqg1CNmMg5s64O67KIfvsB3vjAfEXLeNpRLVVDC61RCTSYipMkFZsPY1RP3aclRsgGZLnE2VIS6eLZ7LHi1lDMiZcpdanBcRUQhVDiy0UyVLUwT93rSoUdQlajwy0mbKqFKsqmQ6OL2o3EGxSok0+8D3hRQIpYhQBG5NFDU0OOd6x2cDyPpyP6iOjeIfZg7NfFz3q+JvAThDniLfSULmuYOHuV4+ftpqSTC5iXLET+BUa/EuCmTCiD3akKpjkWGZvzVgvCMKzHjdAhJcSabE6tFMT/rUvtTTL7LlKA2jjeKZOynjRUrFstYHiExaSkz6nDKRdUEkuQmr9kKmWCbn2c5LnWPLEx9kd7O6ZvriVdnOXwLjqitxEs4icXpfD946+7g2c/iDh0DRLcMyw0kCyBcnmMrxr8TpSAgZomzAkMDNwzBZi26rVhvGo9VKUescIneBXhVOWqYcpypalElQk4rjstBJ5ITifAkdEJSByi9Zc9lN7PTLEW3GwXZnyvMopsgp/ylzTxEzdCGhqA5KczZymkndGv/pZevvCoVUWxBV+MfiXWIMuZmusloOopKTC6NflOpaGTPHlNHSMii8E/C2hmCdJyjRzJidDV1uLVqPOTV4hOkKH+KUdS9rR7KyHwk4R8K2EwvDDhVw64cQyRQMZDyNlbKDVe73CpSMvy2XpWtSahbiwpxdSVqUVEng+I45jWLq48WxjFcUUf3sRxCrrTq4Y1M6awB0AYCzAMI59huBYHgyeHCMGwrCk3JGG4dR0Lk6lX3WTK4lH95SnKiSSSSY+1nE+lEglkbO8wTSXSSTS1hcXMpvOY6Clkrl8K3T3kTHTGOfYhIOHRUd96IebbSSApQJGPjzZsmnlLnT5sqRJlJKpk2dMRKlS0DVS5iylCEjcqIA5xn1FRIpZMypqp8mmp5KTMnVFRNlyZMpA1XNmzVJly0jdS1ADnGNTj57Urgxw3aiZPwpZc4v5uS0+hEVBLdleQpbEAKQyY2fuNiMnhS4UP/ZstwkRBxMOFtKzBL4hSSnrvG/EvB6AKk4Wk4vVAEcaCqXQylXA46gjinMWVw06ShSQR94lqaOoMzeNGXsJC6fA0nH68JUPaSiqThcldwn2lUoBdSXZXBSIVLWl0/e5S9MEnGztB8Y+0nmqGm3EfMcXPn0P/Zsu5XlrRgMtSRcW73EwkgkLK1MtREQ44lhcfFLjZzHISw1HTOLSwwEdJZgzNW4p7bEcbr0IpqSVNqFcZ9hQUFPKQqZOmhDlEtEuUlSps5ZXNKEvMmKCQ2uuM5hzLnfE6ZNdOnV9XUT5dLhuGUqCmQifUzBKk09DRoJBnT5i0SgtRmVM4mWiZNmcKWyP8F+HMPwsyJLZAUMKncUP2nmWMYqsxM4ikNh5pDyqKXCy5ptqXwlEoQtuHVFBlDsS97zxG8cvEqo8V8/4ljyJs8YDQvhOV6SaPZ+wwalmzDLqVyBZFVik5c3EarjK50sz5VGqcqVRyBL9xPs++ElN4O+G2E5dmSqc5hrmxnNtbKPtPvOO1kqUJtNLnllTaPCZCJOGUfAJciaimmViZKZ9bUKX2it3W++t6V3qa3050Jpvc9SJQBoNPXyG5uS/e7Wju1xqPU6joAC3PkNgxERVOa00/wABbfbXXoTTEyUXAZ+n6nRtBycPzgz9ty4t37WYWdrAGIy3KV15nUGtK/Edq1Fhc1rWmMhMsb3I0DeRZPYEgk6FrRcBboX6uTY8I1sAbm7PaIrjl689uelfDau2pvjIShm57W+n6e/QNXQMQP8ADfvc3fdufcMIil8zcV8rbVuoj1O9MZCUbl25cx15X9Ip7z1e3Q7gM5vdW/IxHHNem2wvfvG9SRc/7u9DkpTpzLfJuX87m7NXQdNzuS1m0tsG8m1iGtdOp9OdzS2u3XmSTkoRz/jtYXY99tTFN/gBdhfRjd9202ZrQ3F61r43tWlTcU0JAB8qb5KU9PL4DYtzPUmzxXa+hO1+yRzvq1nsLO0Ja6VPSw5DUkjnWutT51xlS0WBIB5m9zsBpYenwFb8rnQdR8SBqXANhEFxeo2uCdaVpvzqRQVobXtXGUhJJbnd32+W+wIvd7RQcjcXvqC1w3bkN9NDEUJcecQyy24666tLTTTaS4644tXcbbbQkFSlrUoAJSkqUpXdpW2M6VKXMXLlS0qmTJi0oQhCSpcxaiAlCEJBUpalEJSlIKlEhIckQJShJUtQSlKVKWoqCUpABJUSTYAAkk2sVG942meypwg/zI8C8kZJi4NmEzEuB/b+cfdhsuOZqnoRGTJqJeaUpuJdlTZhZA1EIUpLkHKIUIUpCUk/oF+z54bDwq8Jsq5VqKaXTY0qkOMZl4PZla8wYtw1NdLnzZRUifMw9Bp8IROQpSV02HSOBSkBJPnj4i5m/azN2LYtLmqm0InfcsLfiCU4dRvKp1S0KAVLTUK9pWKQQCJlTM4gFEiPROO6Y4RDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIR8/mzKuXs9ZWzHkrNsqhp7lbN0im2WsxyWNCzCTaRzyBfls1l0SG1tuBmMgYl+HcU0426lLhU24hYSoRT5MqpkzaeegTJM+WuTNlq0XLmJKFpLXZSSQWIN7GIKqmkVlNUUlVLTOpqqTNp58pb8MyTOQqXMQpiCy0KKSxBD2IN4/nydq/s85k7LHaA4jcE8xtxKxlWePOZZm0QEEZkyTM/wDrDKWYW3mUIhnVzKSREIuYNw/wS+ctzKUv+7i5fFMt6z43hczCMSqsPmufYzD7JZH+ckL/ABSJoIYHjllPEB+VYWg3SY0czRgNRl3G6/CZ4U9NOV93mqb+3pJrrpagFICSZsgpMwJsicJktQCpZA8+oX4351uN0/kLX3vf4hS1j5b+Y6xx0h+mr6a87bX/ABHcMW0Imtr0Fa60J5bg21sK8tb3rCoNtaztsdiB/dufgW2sLmzX+i/8dGv1iUhfWnI10J50286XruCLSNj9fX1eLFA6i/Mcx+v10MtK6+OpB873OlBpT8cRKS3y/QsNSdC8RkAi1xt5NYsNX0LxJbXsf67XFtfn5iuIyH0sRp/H6+YMbtY3B0P6/ozcuQkpUefK96E8jp/XpUDEZ34rch06a+mmvJxaU7p76+jdtt++0lDg8KctRfUGl/xsDa2LSG10PoYsLHodxty5W87cy8SEroNSbgVpY7abWGltQSRYCIo5M1uh9bv3bbeLCkjRm0bQjz73vvpeJCVeHgb+Y+o6Gtq4iKe4PS3117MdIj4QQe7Ho/MWa/JwA/K9ZLlKUOnqB49Dfw+I3BxGUkfVn7bPbTe2hEWkH153HXt1G2rc5CXRvroaGhF7VFADbTQUOhFsWtZ/TkdN/Pl01iwh7adDdy3O/nvZxzNcLFbGpGux6Cm5/wAU4oRz0Pv+t4t4Trpy3HUvqAdtevOOXe1CiCNPiFut7AnnShO9cW8Iv1+tC4bkCGG0Uvyd9RbTtezaOGD2jubh32huNvChcOOH/E3NuXYSFAS1J0zIzXLhSP3XcsTpuY5eeoPhQp2WKW0Cr3SkE1x9vDMx4/g3D/VmL1lMhH5ZHtPa0jbA0k8TaZTXbilEh7MXMckwXOWaMvFH9T47iFFLR+WmE729CQGYKoaoT6NTbFUhRT+6Q5Mevcu+1F7RUoSy1OJbw5zYlASHXZrl2aS6LdA+8sO5fnsqhGnVCp7wgVtJJsxoBzOl8Wc0yGE+ThdaBZSptNNlLUOYNNUSUBXX2ZT/AKsdi0XjznOmCU1MjBcRAYKVPo58maobkKpKunlpV19iU/6hjt2A9rjmVpsJmfA7L8a7T4ly/iDM5W0pVqkMxWUp0sJqD8JiFWNCo0JP2pfjLWBP9rl2mWprmViUyUkm37q6OeW1txb62vyOV9oiuCQJ+VKSYprqk4xPkJJt+5Mw6pIGtuM94hzf2uGd3m1/sPgxk+Wu90lC5zm2dT9tBAJqpmAk+WVrSLVAfbJofiFbWTvGTEVAinwGjlKP5TPrZ9SBydMuTSE9WUOQiGo+0NiqwRSZYw6Qo/lNTiNVWAHqmTT0JV1AWl9ARrHQObfaedqKftOsyiZ5KyQXAoe+yxlCGiohoEEENLzfE5paSdSFqaUtBHeSpJAI+RU+J+a6lJEqZQ0JUNaWkQtQBbQ1i6sXBsWcPq4eOO13jbnmsSpMidhuFuPzUWHomKAIYkHEF14Sb2dJI1Bdo8PZ/wCKnEjiZGGN4hZ7zbnWIDyoho5ln0xmrEM4sE/6lCRT7kHANoqQ0xAw8PDsNkNMNNtpSkcQrMSxLElceIV1XWrB4gamdNnBJL2loUoolgBwlKEpSkWSkANHXmI43jONTBMxfFK/E5nEVA1tVOnpQp/+6RMWZcoDRKZaUISmyUpAAHWTqjcCxOu+lrGlLctb1roMQJDJL7/AgP8Ap6+WDcHpbcHUgHkdmFttL29edkrhkJ7mCI4iziGSuU5YeMNI232++iLzGtpK1RaQurfdksK8l5s91SxMIqDfZW27BKxpr9sDxSOXsuU/hxg9StGMZrkfeccmSJnAujywicqX92UUlMzixyrkrpVjiCFYdS18icFy6xIO/P2H/BwZkzRUeKeOUyJmC5NqDR5dlTpPtEVua1yZcw1ifaJMtScvUdQiplqIMyXilZh1TTrlzaBRORpTta79dB/gPz51PmgEXHP1N+TWHS2rdo9ZdTz6ve9rcgNQ4tY7gRQU5zNdh89BqdNrHniVMs7uOYdzrubtrtudeYB9b8+mhLkju4Fx6xHU7y1FaHU0r0000FbE0pWgnTLbZhv31Nn1c9b6u0XN/tNrqwLcrufU87xFU5yvSt+XnvcGutzXc4nCeQv8v00bowvaKO5bU3v7rat3D6Al2IiOpwXvU0ra59Nhbe1bUNcTol87nsw31LOXHqC5ZrUuegcOX8tSbs/QOPw3iItw86bVFSQL0AFTQW5m4vUaZCU8tbfp07Pb1Je5gxHIEsTcnmrTvruHawiItwjX0rpy51J3/GtTkol7n158wNttS0ULlrNZmGo67Nozbiw1LQ3HNfMmum9Sq1unXrpkJTp6MPgH15k+Z2EVA7c7G3+zyH970HSIte58QDqb6nwrYbDrplIljfXcjQdB8epvo3FUltB2Hp6FjYdb3LRCcXUa66m+nO1/C9Ba9SAMlCX25e46b7bWO2mtNr35n/8ACN9rgl9zcxBWuu+/TS+vpppTyploTwjS++/l/Kz6bRdp56bcmDchc8xexvHuf2fXAxXF3jfA5knEA5E5K4WmEzXNnXE0hYzMbcQVZSkrhqfel6Yw7s5iIdaFw8RL5HFQUXREahLu332N/CU+IvilSY5idGudlfIRpswYhMUP8mqcalzQrLmFrOkwzaySvE58kpXInUmFVFPUcKamWmZ07405v/ZrKk6gpZwRimYfa4dTgf5yXRKQ2J1SRqkJkTE0iFhQWidVSpkpzKUU7HuPbSNGoYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjBj7bnsaq4x8G4TtIZFlLb/EXgZLok5vahk92NzHwiLjsdNFfC2v7TFZBj3X8ywra3IVDcgjs4LLkVFolsGvr3P8AgX3+hGK06HqsPQROAsqbRE8S9i5plEzU3S0pU+5JSk9O+L2U/wCtsKTj9HKCq/B5ahVBIHHPwskrmaj8SqJZVUJcp4ZC6supXAk6g6F+u45jkL0qK/dHOnInpBSXtuI1ZUkguNdL/WurFmN7cpTa77EEfo6W7o8DtUDSBSdjb9Hv3B626RGoOHHz5s17uTryvufxTEL05GtK2qAdx/S2oGqcQkNZrBtP3X0a1x3OzHYizXv8fkANv00lIXSnLprp4/nbS1MWkecWFLOWudrMfUG/wOu8SkLqdq8ga63r51r4eF4lJb9fgPQM/Pm9oyHG/chhYafLvze0hDlKfXTfQgfPTTFhD2P11HyMRl08yPgG56kaXANnJeJKVdetzca3v/Q68gMRkEdrafpuToP9n8TvFCkKuDfnsYrpc686nx2PKnKnLTXFpTy+trHe/Qai14s0sofR5H1O4fZ7xIS513qakkHmLXA2ppTWpAxYUg6i9x2+vdFpSD5bjb9eY1tfnFcOC1d7XNq1tfr89QNcRlBuR9a7fD6MWEEdeu/WzsQWb3aANVCxb9U5XGhtatxyxGU67H6sQdi9xZ/WLWG22p0sBexL/C7u2sVQ51oNwfiH0rXxxYUkX1N7ixc87s3v20izh1a3u52Y+bgA36sYqpdI001qDXTc94EDoKHcilK4oRq+ugDc+RBu3NvKLSDvfV3t5aE+9+fKOYeF+9SvMpKb8goGv9ByxRn0+IPus3m3KKNbQgche3MguOtn5xzDw5Vr/MT8yBQeflvijWOtuYPye/du8WlI3U1uTe6xO+g89o/fe+P+8j8cGHMe/wDSKhIOjFt2P/mb0ik89RBFTUmmqTbU6U5bm+lDi+WAVXO2z/pfXRjvFwQHcsALnX5k9/KLU65SprvXXnehA5HrW9DUC+UlgGGotcEbW7WA925idAHn2u7kWNjfS3LRyYtzihegrWvPw38a/kDUSp5M93GnY7jo3zZolFi5tqQ1n/g3q4i45Zy7NM5ZilGWZO0XZjOo1qEh6pUpDIUSuIi3wgVRDQUOhyMinKgNwzDq1KSlJOPjZozJheT8u4xmfGpwkYXglDOrqtQUhK5gQAiTSyDMISuqrahcqjo5RLzaqfKlJBUsA8syXlHGM95pwLJ+ASPbYvj+ISMPo08C5iJQmErn1lSJYKkUeH0qJ9dXTfyyKSnnzlqCEKUMyOUctSvJOWZPlWTpKYCSwaIRpa0pDsS6VKdio2IDYS2IiOi3X4t8p+H3zywkd2mPFPOuasTz3mrGs24yp6/GqxdUuSha1yqSQlKZNJQSFrPGqmoKSVJpJBUxMuSlSgFKVH6B8g5Jwfw6yfgGTMCQU4bgGHy6SXOmIlyp1ZUFSp9diNSiV+D71iNbNqK+oCTwidPWEMlKYvxdtqa+p8rCnkDeh+KluNpl2YMB+m/Vxpp+vMGsP3g9tgPLVW/N/WKCnOtTfSu/W/PT5a4kCRyf+HPbqet+TUJF9w46AAer69X5MA8da61rsLitvAml9NOulNJkoLh7X7/R7dGL6Lk31LW56bdL3LjW2sR1u089LX1vRJGwBub9AK4nTLZmt8+Rsez79dIrq79yBYP1Pm/IMdWiKtyv1IJHzpXqKG9Kg7HEyUHYWtf618t35xVw53I0DORzYdQ13Z+WkRlL2BqdK+ug+df8cZKEAbd/Tc7dtegF4tJ5+etmvazAiwFzcsSXtEW5rtz3N6aDcmvp5gzpS7W225B9eQF+vLV4u5ci1xZ+5uw2A1ewiI4v8wDvT95VPkNh1FsmXL3OulvgPgXF976Uv0J0A2Df3R8TZvIxEccvc6nzrUX6U5beNhkJS9hft+u/xJcsRqYbl+Z5HuNTsH013AiEtdev46dPufM30FcZaEcOuv0+939dnJgx1NuQ9bturvpqYQcHGzWPgpXLIWIj5lMYuGgYCBg2VxEXGxsW83DwkLCsNJU48/EPuNssNNpUtxxaUISSUg59DRVWIVdNQ0VNOq62tnyaWkpaaUufUVFTUTEyZNPIkywpc2fOmrRKlSkpKlrUlIBJaLJ06VTyps+fNlyJEiWubPnTVhEuVKlpUtcxa1EJQlCEqWpaiAEgqVYCNo7socB4Ts98HZDk9xpo5qmVMxZ6jW3Ev/ac0TGHYTFQrT6CptcDJoZmGk8F7gpYebglR/dMTHRLrvvr9nvwlpvBzw1wjLS5cs4/W/8AvnNdUhYne3x6slShPkInJKkLpcMkS5GG0xlcMmailVVhPtqqetfnx4jZwmZ0zPWYmlShh0j/ACHCJKklHs8PkLWZcxSCyhNqpiplVN43WlU0SSeCUhKfSmO744JDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEUIqFho6GiIKNh2IuDi2HoWLhIpluIhoqGiG1NPw8Qw6lbT7D7S1tPMuoU242pSFpUlRBoQFApUAUkEEEAgghiCDYgixBsRFqkpWlSFpStCklKkqAUlSVBlJUkuCkgkEEEEFjaNGr2ofYjjuxzx8jXctS58cEeKERMMzcMJg208YSRqW+XZ3w9iIhSVJTG5UiYhH7NSp11yMyxFyaLW65G/tNqG19zdl9WCYioyUn7hVlU2kUyiEX/tKYkhgqSSOAOeKSqWX4+IDT3xFygvK2NLNOg/1RiKplRhy2VwSnU86hUdPaUyikS3USunVJUT7QL4cayFX662/ep+8KnXn63sTxBSXHXY/LtHXSk7jzFuRseRvr6ixAkoWPHw31uDWgI29BUGghI2NiPrzB+tjEZD+T+WnctzuWdza6paHOtRzppU6Hp5gGtjuYiltA/MPcsC5HPtqNgx4Yt5A2+F9++xb4i8pK6Uofn15/oiugJxY3mPr663aLVJvyPMjUdRof1HSJKXARty02rptzoKWqRfc2FHL478/g/bezRlN2Otyz+8au5/2mGh1isldKX52r9PrWlaHriMgj6+Pw7uIsKSHbubWvz5GzHq+piQlwGhNa+NxWleh6bEnmcWFPJvSxbT65WDC0Wu7gjn59udm035WeuFcjtt06XvuN9dCMWNo40tv00L/qkE8ja0o5en8YrJcpT62I8frp5a4tZ9Pr5chq7lmiw21Bf60tflvYdmrJXyNOo0qLC1KDc1ArW4xaQDqP16/wAYoUgjnt8yx5cy/e0VQ5yobUtqTzodSdyTYV1xaUDbn9abfTjWLSg6Pbkbhuh1ZtGPnvHP3gFa+RNq+J08Kcji3gPft/FvreLeEjbux2vZjrzu/cbVA4RpXyuBXny61GLCgbgX9fXfyJihAGpvexSQP+X5PrHL3h518AD9AcW8CRt7z5bxRh08lN/4h8zDvj+Ef7h/LDh/1lesUbt/vD9YiPugrCR3RRO1rmta8iBz56WxNLSQkm5fRyHPLrEqE22ux1H69+e2jxDdXUG9a3pSmhFOXT/C2JAn8tmD+4uAzWfptptEnCByYG4u4D9LPzG22sQnV1qN6bnQ2pewv0pTE6UgNprctdnc8ywHN9IlDKFuTC3d9dLdC+h0j332UeGwlEqiOI02h1ImM9ZcgsvNup7q4eSIdAio8N/eC5rFMpbYccSlQgYUPMFUNMSpXnf9rzxQGKYrS+GeEVCV0GBzZWI5lmSVFSZ+NLlFVFhhmD8BRhdNPNRVS0KWn7/VS5U32dThykD1W+wz4N/1LglX4uY9SzJeJ5ikz8MylJnp4TTZflzwmuxZMpQ40TMZrJAp6SbMTLUMNo1z5BmUmLJmK9iKdJ28yQBtoB6HTnfGlIQ2gbv83u1u3nHoODqUjmx1Oh5787u2xiipyouajmfhGv6r6dMSCXe79t/5NobP0aDE9Tu2nrYP1uQ24sKK3ABbSngNxQAUJ8DTcUrQYlTLbSwfffS+453uDYaCAABbQ8gHO2pOl+TM4L7xHW6TvSwAsajwAsLHW1wQbVJlSjkH3f8AU+T3s9w1oqGYDQGzC+rC51326XuBEdTmvn1J0udQN7cieoxMmW4c307D4E9m8ooTZhYWADjXnZ+egvZ3FnjLcsbgC9tv631POu9sZCUsdH8i/pt7z20gPjdr37tYFmtu7WBDR1uHrcWpqbUqTsBU8gdhcjEqEvYWFg5u3IAXJ27b7RUb8w1rsGsDs/ndg40DxFuU8f8AhTW1BzIHoNSBbGUiWA1rnV7knr9dbXBPdtSWdxz6bbqIs/MaRDcc19bm29/QGtDypc1xOlJJtq/Ueb2HXsTcbB593c/7OlrEuNRpewiqXyr56kAine05aUJpS4tTKSgJ6n6+u1gAIq2nTQbDuemgJ05ExDW4Njf9bU+7alBc0p45CUF9L8tuTuNDdxty6HGxve521OhOvPezmMtXs0ezKcwTg9oXOkuSuSSCKiIHhtAxjCltzLMTClQ8xzWlLoDLkJl5XvZfJ3QiISqfqjItpcHG5dYW96NfYe8Cv61xH/2xZmokrwzCJ06lyTTVMpRTXYzKKpNbmAJWEyl0+DkLo8OmcE5KsXVU1MtVNVYNIVM1r8d8/fc6X9isKnlNTWoROx2bLWOKRRLAmSMOdP40rrnTPqUkoP3MSpahMk1y0oziY9UY1NhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQhhCGEIYQjzd2sOzFkHtc8E808Gs/NfZ2Zq0JjlfMjMOmImOS85QLMQmQ5qlrZdYLrkA6+6zHwP2iHbm8niplJ332mI9xxHy8ZwmmxqgnUNSGCxxSpoDqkT0giXOSHDlJJCkkgLQpcskBRMfAzNl2hzRhFThVcGE0cdNUBPFMpKtAV7Gplh0uUFRC0cSRNlKmSlEJWSNBrjhwW4hdnXinm/g9xQlBk+cMmTJyBjUsl5yXTOEWkPSyfyKMfh4VcfIZ7AuMTKURyodhb8FEI+0Q0NFJiIVnXLEcPqcMq51HVo9nPkLKVM5QsaomIUQCqXMSQtC2DpUOIAvGlmMYRXYFiNVheJSvZVdLMMtRHEZc1GsudKUpKTMkzpZTMlLZJUkhwlYUkdYJXXqaXpaut9OlOgFbjT56kv0On19e5wfkqSdRY6B/W/rq3zEV0OHUE7DWnkT+OvI3riBSWsR7vg4aIyAduHXVz6ebaWLjUhhKQ5S2vNPp90ix5jQioHTEZTckWPPY/4hqORN+ZEWENrfl07jyIb0dolIXXS3+B1B8+ZsagYj9x+mZn117RQpBF7/H3dGe+7bGJCXCLE+VBTw/pqeZJAxQpBvvzGsWFN3Z+ofi7636cn0IEV0r0oeetjXal78tuZN8RlLe7TTqTa3PzYaRYQC++mgcNu4a2jt5ARWS4Rap+iqV+Y26898WEdAR6j37/VosII0uNLu3PXnpqLdLiKyXAdT+fkL1ttShtvXFhSNrdNvrrqxI0tFHB1Dd9NOZtzFu+kVAvetLc6EdOtedqb4oxGz9g4LdNBZ+V2Cd4oUDY6+n16xUDhFa7c9vMWPqcWsC2z/Wh15ai+gLXtKVDZ9NOnofTvFUOnWp9aj54o36XcX5OQ3vi09Q3ldvcPcNO8cw9pcedfnenp/TBi7Nccr/CH4eo9D+kcg7/MfJZ+hJxQpG6fURaw5D0EfvvbffV8iB/h5eWKMOQ9BFeAEOw9Db/liGtwKUpROp1qnTS9Dy1+eJQg200bR79mvy9D0ioSQOXQg+gs3a/TpEZ1YFaUqDuo/nSht09MXhNwwYPy6HRhdteY7ERIA6ebjUC769yXsd+mpj73hTkKI4kZ0luX0BaJc2r7fPolCi2qFksM419qKHBVSYmLUtqCg+6lSkxMS24pIZbdcR1z4teINJ4ZZIxTMk0y14gU/cMBo5ifaCtxyqlzfucpct0g01NwTa2tJWkfdKWclBM5cqWvuTwM8Kq3xg8RcGylKTNRhIV/WmZ66XM9kaDL1FMl/f5kubwqKaqqMyXh1BwpWfvtXImLSmnlz5svLbCswsvhIaBgmGoOCgodmEhIZhIbZhoaHbSzDsNIqSltppCW0JoKJSBUmhPjlW1VZiVbV4jX1E2srq+pnVlbVz1cU6pqqmaqdPqJqgAlUybNWpayAzqsBYD3ww/D6HCqCiwvDKWRRYdhtJTUNBRUyGk0tHSSUU9NTSUl+GXJky0S5YLnhSOIliTULxAsTfdPqTU2HjQVvrriAIG+nx+Y9T5Rltu1/wDX/Qc9h6RQU8aGhrtUVUo23JNBTkfOgOLwi/5fMhm/l0v3hbm+tk2Hazkud9L3Y2NJTnWm1jVWlN7CngKbcjKmW7O9z2B9b/A62irnQMA/zawcPudC+m7Cgp3XrW9b9d9elzyxOlDeR8vSxPu896M+rA8zfUnQX13cs7kbkxlO7ih31trap30OgN9gQDiQIvpftfyFmFwNrc4rZzs+5/Ny5MNQ2hbbcR1OnUk2qBU32Fh1NflrQHE6ZT6+nwJNnsQ3wIJhYB9ObO/m+7ka/AkCOtzrTUm9z41uNdPwFp0oA5emnbU2HdmtDkHYNtqdbgMTcc+92vEW515gAb66DkKC9TcUNqHGQmXxbW6v8u7eTgMbG0cWvawHN1N5dLdWiKpwnfyOnIXqb86WvSmoOQlITYeZ36/rc9zFQ+9zcO7atpuxO+r6BtIq3L0HrUjzPT8bUJ0nQh+XXfyHMhr8nDkB3o528zvbVhyHP0c6+k+yp2b592lOJMPl5n7VL8lyQwszz7mJgBBlsnW8oNy+AddadY/bk7LL0JKW3G3g33IqZOsPQsviEL7++z94I4r41Z1kYPKE+kyzhSpFbm3GpQAVQ4apZCKOlmzJcyWcVxQy5lPh6FomBHBUVsyTMp6Kcg8B8RM80mRcCXWr9nNxSrEyRg1AokifUhI4p05KVBRpKTiRNqFAoKuKXJStMyegp2g8vZfk2VJFJ8s5dl0PKZDIJbByiTyyFSpMPAy6AYRDQkM131LcUlpltCSt1bjrigXHXFuKUtXu3g+EYZl/CsOwPBqOTh2E4RRU2HYbQ04Ik0lFSSkyKeRL4ipZEuWhKStalzFl1zFrWpSjoFW1tViNZU19dPXU1lZPm1NTUTCCudPnLMyZMUwABUpRLJASkfhSAkAC8Y+lGLDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYxfaYez2y/22eGjc2yw3L5Hx/4fwEW7w9zM/RiHzFLwH4uI4dZmiO+hv9izeLX7+UTSIS47lidLMbDqTLZhP4OZcTzVlqXj1JxyeGXiVMlRpppsJqbk0s4uPwLVeWs3kzPxAhC5qV9e5/yPIzdh/tKcS5ONUSFGiqFfhE+X+JSqGoU4HspizxSpinNPNJWlkTJ6ZmkTmrK2ZciZmn2TM5SSY5azXleaxkkzDIJvDOQUzlE2l764aNgYyGdAW08w6hSFapWnuutqU2ptaugp8ibTzZkifLVJnSVqlzZSxwrRMSWKVJLXBfQF9RqANRKqlqKKfOpauTMp59PMVJnyZqSmbKmoUykTEG4UlTnlqzhQizpcBpU30rSlqXrzG/ysTXEBGx+vlrGKUnUBuxB30+AYvcPtaulZtXpvatToRodeorUXFcQqQR1F/o+X1dojbn1u1vP3W3ZnLtElLm9TUCtQKGo/iAtSt6i9+hOIyl7eRB25tuD006RaUkG1ntrYvsDbzB5dQIkJdFL0tao0r4W+dN/vUxGUkbE6f4m07ejtaw0i3XXU9hc6F+X0NbSEr3BtzOnz0pXela6EYo3K/Tf0/R4tKQe/MfV/OK6Xda01qK/nbb8upsKQem1rdfjFhSe40/D+nU8rbtFULHPkb9dBXXzOt9MWlH0Pi1teQZrM8WsD8wNetiz7uAwFme8VQs7Go9RbwNvlXrixiP00Pv18n6xaUtdyDqRp0diGPk/WOaXeumlDb0r+uWKFPMa8xeKMoG7abuD30P1y0ioHR0B3qKV8aW/XrbwjmRyvp27xR9iD1s4+fTn7o5hwcyOgIV9b/r1t4COR7hh6DU9T/Kn4NwB7j+o93pHLvjkf15jAJUNCPU/DT1EOFJ0PoX/WOK3KJJChWlBYi5sL1wSFOHdt7+vPbpDgHM+79Ii962iR1p/X6+eJeI8z6/Xu8orw9VHo7vFFazempNa6X5nlQg10OlOtwBtfsGc31YXdw1ri5sIvCQGLpG3UDdj2PUXLxk27PvDsZCyW1GTBhLeZM0Jh5lNCtKkvQkIEKVK5SsqAUlUKw8qIi0JSjuR0VEMKLyIZlw+WP2kvEtXiBniZhmGVKpmWMpKqcMw1KC8mtxErSnFsXCU2WmdPkpo6KYpUwKoaWXUS0yVVk+WfbH7JPg6PC7w5k4ri9GiXnHO6KXGcX4pZ+8YdhnAteCYGpawFoVTU9Quur5aUS+HEq2dTTTPTQ002O9y7zIqNKXN+psfkfGt9eBK0d9RrYa+vdie0bVObiwsAGPPewN3vZvO0Ui5YipO57xrz2FvzxIJYB08wL+pbns+8GO77asB2+G190gtFNTttQNgNNuQ100NOtMSBAvbY9T35D084MG2a/wCV92dyT19zOzg0VObabXtXmQNdK2qa7XFReEktqddLnnroH924Aitxc+4OXI322Hu0FjRU5zpy+I0HkAeZ5img5mVMon5MxvYhzZvTXswachzL/i2bX520cD8sR1O6mp318dhbnrppWuJ0ywNh5WcAHW93Gvp3dtrudLPZ3HqOrkuYjLd1ua+pp62uenia2lSglgB5D6s2+uujgiHDvd+o7sw7sSSe5/MIjLcubjpa3O3O5sRprTXGQiU11emnL9B17GKgejamxb5M3TW4cRHWvcknxNzb0FgdKV0ucTBOwsP5D5iK6aBte/Rn6mz25Bi8RHHKa6bXtYmo6n53xkIQCOXPmX07DdtbB2vFt9n7DdjuT0F99js/ZPB3hDnbjpn6UcPsjS8xc0mK/fR0e8h79k5ek7LjaI+fz6KZbd+xyuBDzaVK7qn4qKdhZdANRMxjYKFf7F8NPDbMvinmzDsoZVozPra1XtKqrmJmCgwfDZa0JqsWxSfLlzDTUFIFoBVwqmT6iZIoqWXOrKqnkTOP5nzNhWUcHqcaxeeJciQOCTIQUfeK2pUlRkUdGhak+1qJvCoi4RLlJmzppRIkzJiNofgVwSydwA4eSrh/k5gqZhv9dnc5fbCJhmXMD7DDUwnkwotwIdifs7TUPCocWzL4FiFgGFKah0qV7t+FPhflvwiydQZQy3KeXJ/yrFMSmICKvG8XmypUusxWsZSgmZP9lLlyZCVql0lLKkUsolEkKOgObs14nnLGqjGcUWApf9lSUqC8mhokKWqTSSbJdMvjUqZMKQudOXMnLAUsgdxY7IjjEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEYffae+zDkPbAkERxV4VQ0sy52kctSwNsvOGHl0o4sSeXsL+z5XzPE9xDUNmaGaQ3C5SzZFuJaYbS1l7MTv7CMtmeVuFZsynKxuWayjSiVikpDAlkIrEJFpM5TMJoYCTOVYMJU0+z4VSur/EHw9k5okqxLDRLp8ekS2BJCJOJSpaTw09SWZNQkMmmqlH8IAkTz7HgXT6ZuaMr5lyLmWd5OzlI5rljNOWplFSaf5fncE/LptKJpAulqKgZhBRKEPQ8Qy4khSFpood1aCpspUroydImyJsyRPlLlTpS1omS5gKVoWk3SoKYhQYguG3cjhB1TqaSfRz51LUyJlPUyJi5U+nnJVLmSpiSUrQtCgClQ0YsNxZos6F228Dp/Sx89q944gIN20+n9Ow6sbRjEcV2Lb2v1BG9+Vr6gJiQldaU8aE32pQ1odeZ8QTQRlAOlu1h8IjKSNDyBG29tHG9iD0FhFZLnjzqCQelR1oNuovfEZSRYj57X9N/wBIsKXtp0IHm2+pJ1Poz10uEUIttavd5XBIIN9ietiTiMpfru+hfuBpszadgItIPudidRqWaxHWz7XESEu6VpytSmtNNf8Al5E1xYUkPuL3NjoCeh0O/YbxS29vX+Oupt25RVS4DodDsfnQ/QVN6Yo1+X+K3l/Gw3ihAOoB2f6uP5tFUOEU2ttY0tt5aW6EYoRzDh+4f4Rbw9X6KuP1H1rFQO+o0JF/Cv589cW8I6gcgbd2+tIt4TuLbhJt6Hfkx8tjUDg5mw0B71et7jwH+NpRybvow8rHu38KEdGvYkEfC3dwG67cu+Dv6g/UE/S3XFOA8n6gj4ED4+kU4QzFj2UG9CB8fSP0L5ECvJX5C/rinD/i/wB3+MU4B/dP+5/GOK3NB3t664uQncjoxi9EvU8I5M1/PlFJS7XVXX979XNbYv4RyHoIuUiws1xt39w38ucd89nnh5/ltnFubzFlLmXsqLYmEYlxv3jUdM+8pcqlpC6tqQXWlR0YlSXe/DQghnG0pjUOp16+0f4lHIWSZmGYdPVKzJm1NThmHLlzDLnUGHhCUYviiVIaYiZJkz5dHRrQqUtFZWS6lEx6RaVbX/ZF8G0+JviLLxnF6UTso5FmUmM4qidITNkYniypi14FgqhMHsVyZtRTzMQr5cxM6XMoaGZRzZQFfLmoyVl2orc1uTpv/NY151N/KvlqENYWbYEkegcD0HSPagu92J1/Eoqcnf4vbz1bgXTsR43J8O7oNuR+dbgg68JF+QAPnvvoDDnfk/CG31e79b6bRTLlRuB5AfmPC2pFcXiWQTpY6an5B/XR2sYNr2Aclz2a99xbUi0Ui51vb7uvmTr68rb4lEodSH/e08kjTtrrdMVt3Y6DYbizm2xte1hFFTtNKX0OppW9TX8786YkCALNowuwvpp+unckmjm2g0F9n6B9e+2gZ4oKdtqdaVrUgVv9dNR1rUSJQSzdNrXvp8m3fRnMTe5/xaciyR33Da33igpwHetR5UuLmouaDrsf3jidMrQm3x58ufPe7WAFWf0a/kbBt+bG/QMaC3K3sNegvXrfz9KWEyUgWA/X+UNOvUtqPeNOps50vHU5S9ak1t6moHpz6hN8SJS/bV9rbE+ul/8AFaGnXzs46XJNhzNjpEVbmv52Ap+8b7aXv1xkpls25ttv0GzvyfqNIaks/dtw4s/Unto7GOwuE3CbPfG7O0syFw+lDk0nMwUHop9ffZlkjlTbzLMZPp5GpbdEuk8AX2vtEQUOvvvOQ8BL4eMmUZBQcRz3w98Os1eJ+ZqHKmUcOXX4lVkTJ01XEigwuhRMly6nFcXqghaaPDqQzZftppSubNmTJVLSSamtqKemnfBzJmTCMqYTUYxjNSKelkumWkELqKyoUhapVHRyiUmfUzgg8CHCEJSudOXLkSZs1GzN2aOzVkrs1ZHby5l5CJpmWaJh4rOecoiGbZmWY5m0hQShABcXAyKXKcebkkmQ861BNOvRD7sXM42YR8X7geCXgnljwTysjBcHSmuxquEmfmXMk6QiXW4zWy0nhQkArVS4VRlc1GGYamauXSy1zJs1c+tqayrqND8956xXPWLKrq0mnoacrl4XhiFlUiikKIcqLJTOrJwSg1VUUJVNUlCEJlyJUmTL9HY7njg8MIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhDCEMIQwhGL/ANod7Mzhv22ZA5mmSOS/h/2gpHLwxlviAiF7sszLDQwQIfLPEWHhIdyLmkpDSFQ8qnMOlydZaccbehUzKWNxMgj+J5lyrS49LM1HBT4ihDSqhvwTgPyyqoJBUpGyJgeZJJdPGkGWrr3PGQKDNsk1Ekoosako4ZFbw/2dQlLNT1yUgqmS2HDLnJBnU5IKRMlhUlel9xo4KcUuzxxCnHC/jBlCaZMzjJVBbsvmLaVQ0wgHHn2YSdSKZMKcgJ5IpgqGiPsE5lcRFS+KUy+0h4vw77TXRlfh9XhlTMpKyQuTOl3KF7pchMyWsEpmS1MoIWglJIsXCm1SxfB8QwSum4filLMpaqTcpWPwrQSQmbJmB0TpKyDwTZalIUxD8SVJHWCHPltv5amwt5mgFcYJSNm9dLPd+V+TDmbR8oixfrcP7wPV+gd9DXS6TQVrv18bCh1JPS5rcGwjn9dO4iwpBDtbtZ78ySC3e55ERVSvkamun3SB59P8SL4sKBtaLSkjqDsb+hu7Hvy2isHDemvOlD9NgeW4r1jKSNRb1ixhZ3HQ3A8+7b9LGKqXTfTyHdPTSxI1oKVqKEXGLCkFtbc3PxO+nLpFOHy7aDvoQGO9xd3sYqh4ilSLUA7w031AIqB4E600raUHZxbYuOzEg33vyu2lGOrPva3TSxbsOji8Vg7XUUpyoR8q18KjXzxYQ3IvzdPmx9zltYpb6+vke+0cg4k6EV5Go5+JHPf8hDaggerelj5RRu3r9P5RzCzUAH5gjyrfTW1RhbmObF3+Y98UKRuPkf1+ukcu+rn6AH8PpimsU4E8vef1imVoJua0tTumg1romlb3xeEqa3qCL+/07mLwCBYkPe6v1MSIKFiZjGwcvl8O7FR0dEswcJDMtqU9ERMS4llhlpHd+JxxxSUpFdTe1SMesq6bD6KsxDEKiVSUNDTT62rqqiYmXJpqWllLnVE+bMUQlEuTJQuYtRsEpJJDRm4dhtfjGIUGE4ZSzq/EsTraXD8PoqZJnVFXXVs9FNS00iUl1TJs6fNRLlpAJKlDvGVvhrkyF4eZOleXIchyKaR9rm8UnugRk4ikIVHRAKaD3KFIRCwoNVpg4aHStS3AtavIbxWz3U+JWdcVzJOeXQqX9xwOlUCTR4LSrmCilK4i4nT+OZW1YACfvlVUcATLCEp97vBLwuofCDw7wTJ9PwT8RSj+scx1yAnhxDMNbLlHEZ6ClISqmpzLlYfQEuv+r6Kk9quZNC5ivui6L1APnX1FPDHXQQBuX6W+vJrR2yX/ALoYcym3xt6RxL19daWA89/p41xdwi5bk7kmx77ae6D3IcDRgA50e1hb17iKRdr1O+9L/KmtT1scXhJ5bW2Hbbbl0uIo3MEuBqW9Q5Ol9+3Kmp0ixIGovep2sNK2pS52G+L0ylEP9fEdi3rtFRsOmiR5am/QksxFyIoqdvzBpruDra56/Ikm2JRKAZ7+T+8/p+sVZn0Gt9fj1vq2tjrFJThoa0pTwHLT5Ct+dqAShI0AuYr2D33t19NNHc35mKCneZrQa6C/Ifha/XEgQT66b66OWH8L8oo9+dhowDc9e7P7tTHU7t6ab05U0GvI9MTJl899db93uXPaxu5NqOTZntYBwByvbRujH/ljqd1uDTao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-<use href="#symbol:res.4" fill="green" stroke="green"></use>
-<text stroke="none" x="30" y="-25" fill="orange" font-size="28.999987">
-<title>PACK_TYPE</title>0201</text>
-<text stroke="none" x="20" y="-25" fill="orange" font-size="28.999987" text-anchor="end">
-<title>VALUE</title>100K</text>
-<text stroke="none" x="25" y="-55" fill="black" font-size="28.999987" text-anchor="middle">
-<title>$LOCATION</title>R56</text>
-</g>
-<g id="TP7.1" transform="translate(6600,-1100)">
-<use href="#symbol:testpoint.1" fill="green" stroke="green"></use>
-<text stroke="none" y="-50" fill="orange" font-size="48.000019">
-<title>VALUE</title></text>
-<text stroke="none" x="-10" y="14" fill="green" font-size="28.999987" text-anchor="end">
-<title>$LOCATION</title>TP7</text>
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-<text stroke="none" x="2200" y="-650" fill="purple" font-size="60.000012000000005">BOOT STRAPS</text>
-<text stroke="none" x="2200" y="-1100" fill="purple" font-size="60.000012000000005">BOOT</text>
-<text stroke="none" x="3400" y="-350" fill="purple" font-size="48.000019">IN+ AND IN- SIGNALS MUST BE ROUTED DIFFERENTIALLY</text>
-<text stroke="none" x="2200" y="-1600" fill="purple" font-size="60.000012000000005">INT/RST</text>
-<text stroke="none" x="3400" y="-450" fill="purple" font-size="48.000019">INA ADDR: 0X40</text>
-<text stroke="none" x="300" y="-4300" fill="purple" font-size="38.000017">SPI3</text>
-<text stroke="none" x="2200" y="-2400" fill="purple" font-size="60.000012000000005">SPI - MCU/FPS</text>
-<text stroke="none" x="300" y="-4350" fill="purple" font-size="38.000017">SPI1</text>
-<text stroke="none" x="300" y="-4400" fill="purple" font-size="38.000017">CAN</text>
-<text stroke="none" x="300" y="-4450" fill="purple" font-size="38.000017">USART3</text>
-<text stroke="none" x="300" y="-4500" fill="purple" font-size="38.000017">USART1</text>
-<text stroke="none" x="300" y="-4550" fill="purple" font-size="38.000017">USB</text>
-<text stroke="none" x="300" y="-4650" fill="purple" font-size="38.000017">BOOT PERIPHERALS</text>
-<text stroke="none" x="2200" y="-3000" fill="purple" font-size="60.000012000000005">SPI - MCU/HOST</text>
-<text stroke="none" x="300" y="-4950" fill="purple" font-size="231.000018">STM32F412</text>
-<text stroke="none" x="1100" y="-4300" fill="purple" font-size="38.000017">PA15/PC10/PC11/PC13</text>
-<text stroke="none" x="1100" y="-4350" fill="purple" font-size="38.000017">PA4/PA5/PA6/PA7</text>
-<text stroke="none" x="1100" y="-4400" fill="purple" font-size="38.000017">PB5/PB13</text>
-<text stroke="none" x="1100" y="-4450" fill="purple" font-size="38.000017">PB10/PB11</text>
-<text stroke="none" x="1100" y="-4500" fill="purple" font-size="38.000017">PA9/PA10</text>
-<text stroke="none" x="1100" y="-4550" fill="purple" font-size="38.000017">PA11/PA12</text>
-<text stroke="none" x="1100" y="-4650" fill="purple" font-size="38.000017">PINS</text>
-<text stroke="none" x="2200" y="-3750" fill="purple" font-size="60.000012000000005">UART</text>
-<text stroke="none" x="4350" y="-1750" fill="purple" font-size="30.000006000000003">MAX CURRENT SINK: 32MA</text>
-<text stroke="none" x="5250" y="-1850" fill="purple" font-size="30.000006000000003">FORWARD CURRENT: 10MA</text>
-<text stroke="none" x="5250" y="-1900" fill="purple" font-size="30.000006000000003">FORWARD VOLTAGE: 2.1V</text>
-<text stroke="none" x="3050" y="-4850" fill="purple" font-size="48.000019">PLACE CAPS CLOSE TO MCU</text>
-<text stroke="none" x="6050" y="-1850" fill="purple" font-size="30.000006000000003">DIVIDER AND R1 VS R2 LOCATION **</text>
-<text stroke="none" x="6050" y="-1900" fill="purple" font-size="30.000006000000003">** PLEASE ADD SILKSCREEN TO INDICATE</text>
-<text stroke="none" x="6050" y="-2000" fill="purple" font-size="30.000006000000003">DIVIDER INDICATES TRANSPORT LINE</text>
-<text stroke="none" x="6600" y="-1600" fill="purple" font-size="75.000015">TESTPOINTS</text>
-<text stroke="none" x="7300" y="-1850" fill="purple" font-size="30.000006000000003">DIVIDER AND R1 VS R2 LOCATION **</text>
-<text stroke="none" x="7300" y="-1900" fill="purple" font-size="30.000006000000003">** PLEASE ADD SILKSCREEN TO INDICATE</text>
-<text stroke="none" x="7300" y="-2000" fill="purple" font-size="30.000006000000003">DIVIDER INDICATES TRANSPORT LINE</text>
-<text stroke="none" x="6650" y="-4900" fill="purple" font-size="38.000017">ALL PERIPHERALS, MAX FREQ: TYP = 29MA</text>
-<text stroke="none" x="6650" y="-4950" fill="purple" font-size="38.000017">CURRENT CONSUMPTION</text>
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-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTCK_SWCLK</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>4&nbsp;</text>
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-<g transform="translate(5500,-3650)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTDI</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>4&nbsp;</text>
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-<g transform="translate(7950,-4250)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTDO_SWO</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>4&nbsp;</text>
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-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTMS_SWDIO</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>4&nbsp;</text>
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-<g transform="translate(6700,-1100)">
-<line x2="1150" stroke="goldenrod"></line>
-<text stroke="none" x="340" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTRST</text>
-<text stroke="none" x="1240" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>4&nbsp;</text>
-<text stroke="none" x="1180" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(7950,-4200)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DEBUG_MCU_JTRST</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>4&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(6800,-2600)">
-<line y2="-50" stroke="goldenrod" stroke-width="6"></line>
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-<g transform="translate(6800,-2650)">
-<line x2="-650" stroke="goldenrod" stroke-width="6"></line>
-<text stroke="none" x="-660" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DIVIDER_HIGHSIDE</text>
-<text stroke="none" x="-714" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(8050,-2600)">
-<line y2="-50" stroke="goldenrod" stroke-width="6"></line>
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-<g transform="translate(8050,-2650)">
-<line x2="-650" stroke="goldenrod" stroke-width="6"></line>
-<text stroke="none" x="-660" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DIVIDER_HIGHSIDE</text>
-<text stroke="none" x="-714" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(7950,-4000)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>DIVIDER_HIGHSIDE</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(350,-1600)">
-<line y2="250" stroke="goldenrod"></line>
-</g>
-<g transform="translate(1800,-1350)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-710" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>FP_MCU_INT_L</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(6700,-550)">
-<line x2="1150" stroke="goldenrod"></line>
-<text stroke="none" x="350" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>FP_MCU_INT_L</text>
-<text stroke="none" x="1240" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="1180" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5500,-4400)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>FP_MCU_INT_L</text>
-<text stroke="none" x="-1374" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(6800,-2350)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(6800,-2400)">
-<line x2="-650" stroke="goldenrod"></line>
-<text stroke="none" x="-610" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>FP_SENSOR_SEL</text>
-<text stroke="none" x="-744" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="-684" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
-</g>
-<g transform="translate(6800,-2400)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(7950,-4400)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>FP_SENSOR_SEL</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(4850,-450)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4400,-950)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4850,-500)">
-<line y2="-100" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4850,-500)">
-<line x2="100" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4400,-1000)">
-<line x2="300" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4950,-500)">
-<line y2="-100" stroke="goldenrod"></line>
-</g>
-<g transform="translate(4800,-1900)">
-<line y2="50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(6800,-2200)">
-<line y2="50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(6500,-3300)">
-<line x2="300" stroke="goldenrod"></line>
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-<g transform="translate(6500,-3350)">
-<line x2="300" stroke="goldenrod"></line>
-</g>
-<g transform="translate(6500,-3400)">
-<line x2="300" stroke="goldenrod"></line>
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-<g transform="translate(6500,-3450)">
-<line x2="300" stroke="goldenrod"></line>
-</g>
-<g transform="translate(6800,-3300)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(6800,-3350)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(6800,-3400)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(6800,-3450)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(8050,-2200)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(6800,-3500)">
-<line y2="50" stroke="goldenrod"></line>
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-<g transform="translate(6800,-3500)">
-<line x2="-300" stroke="goldenrod"></line>
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-<g transform="translate(350,-2850)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(1850,-2900)">
-<line x2="-1500" stroke="goldenrod"></line>
-<text stroke="none" x="-760" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_CLK</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5500,-4150)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_CLK</text>
-<text stroke="none" x="-1374" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(850,-3050)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(1850,-3050)">
-<line x2="-1000" stroke="goldenrod"></line>
-<text stroke="none" x="-760" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_CS_ODL</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>4&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(4250,-4200)">
-<line x2="1250" stroke="goldenrod"></line>
-<text stroke="none" x="40" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_CS_ODL</text>
-<text stroke="none" x="-124" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>4&nbsp;</text>
-<text stroke="none" x="-64" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(600,-3100)">
-<line y2="100" stroke="goldenrod"></line>
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-<g transform="translate(1850,-3000)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-760" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_MISO</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5500,-4100)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_MISO</text>
-<text stroke="none" x="-1374" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(350,-3100)">
-<line y2="150" stroke="goldenrod"></line>
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-<g transform="translate(1850,-2950)">
-<line x2="-1500" stroke="goldenrod"></line>
-<text stroke="none" x="-760" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_MOSI</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5500,-4050)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_SPI_MOSI</text>
-<text stroke="none" x="-1374" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(7950,-4050)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>HOST_MCU_WP_OD</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>3&nbsp;</text>
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-<g transform="translate(350,-1050)">
-<line y2="-100" stroke="goldenrod"></line>
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-<g transform="translate(1650,-1150)">
-<line x2="-1300" stroke="goldenrod"></line>
-<text stroke="none" x="-410" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_BOOT0</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5500,-3400)">
-<line x2="-1250" stroke="goldenrod"></line>
-<text stroke="none" x="-1210" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_BOOT0</text>
-<text stroke="none" x="-1374" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="-1314" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(550,-1050)">
-<line y2="-50" stroke="goldenrod"></line>
-</g>
-<g transform="translate(1650,-1100)">
-<line x2="-1100" stroke="goldenrod"></line>
-<text stroke="none" x="-410" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_BOOT1</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(7950,-4300)">
-<line x2="-1450" stroke="goldenrod"></line>
-<text stroke="none" x="-810" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_BOOT1</text>
-<text stroke="none" x="90" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="30" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(750,-1500)">
-<line x2="1050" stroke="goldenrod"></line>
-<text stroke="none" x="340" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_FP_RST_L</text>
-<text stroke="none" x="1140" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="1080" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(750,-1600)">
-<line y2="100" stroke="goldenrod"></line>
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-<g transform="translate(6700,-900)">
-<line x2="1150" stroke="goldenrod"></line>
-<text stroke="none" x="350" y="-10" fill="orange" font-size="38.000017">
-<title>SIG_NAME</title>MCU_FP_RST_L</text>
-<text stroke="none" x="1240" fill="black" font-size="30.000006000000003">
-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="1180" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(7950,-3850)">
-<line x2="-1450" stroke="goldenrod"></line>
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-<div id="page3">
-<h1>dragonclaw/page3: HOST SELECTION</h1>
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-<div id="page4">
-<h1>dragonclaw/page4: HOST CONNECTORS</h1>
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-<title>PAGE_TITLE</title>HOST CONNECTORS</text>
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-<div id="page5">
-<h1>dragonclaw/page5: SENSOR CONNECTORS</h1>
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-<title>$XR2</title>4&nbsp;</text>
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-<title>$XR1</title>3&nbsp;</text>
-<text stroke="none" x="580" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
-</g>
-<g transform="translate(6000,-4100)">
-<line x2="350" stroke="goldenrod" stroke-width="6"></line>
-</g>
-<g transform="translate(6000,-4200)">
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-<title>SIG_NAME</title>PP3300_FP</text>
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-<title>$XR1</title>5&nbsp;</text>
-<text stroke="none" x="-564" fill="black" font-size="30.000006000000003">
-<title>$XR0</title>2&nbsp;</text>
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-<g transform="translate(5350,-4950)">
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-<hr>
-</body></html>
diff --git a/docs/schematics/dragonclaw/dragonclaw_v0.2_bom.csv b/docs/schematics/dragonclaw/dragonclaw_v0.2_bom.csv
deleted file mode 100644
index 13f2a55b6b..0000000000
--- a/docs/schematics/dragonclaw/dragonclaw_v0.2_bom.csv
+++ /dev/null
@@ -1,26 +0,0 @@
-Reference designators,DNP designators,Quantity,Manufacturer,Manufacturer P/N,Description,Sourcing,Mounting Type,Vendor Name,Vendor P/N,URL,Notes

-C1 C3 C4 C5 C7 C10 C11 C14 C15 C16 C18 C19 C20,,13,Yageo,CC0201KRX5R6BB104,0201 0.1 uF 10 V ±10 % Tolerance X5R SMT Multilayer Ceramic Capacitor,tempo,smt,Digi-Key,311-1593-1-ND,https://octopart.com/click/track?ai=8297&sig=067af79&sid=459&ppid=25629481&vpid=193845858&ct=offers,

-C2 C8,,2,TDK,C1005X5R1A475K050BC,C Series 0402 4.7 uF 10 V ±10 % Tolerance X5R SMT Multilayer Ceramic Capacitor,tempo,smt,Digi-Key,445-13820-1-ND,https://octopart.com/click/track?ai=8297&sig=01f98a8&sid=459&ppid=28166959&vpid=73759644&ct=offers,

-C6 C12 C13 C17,,4,Taiyo Yuden,LMK063BBJ105MPLF,CAP CER 1UF 10V X5R 0201,tempo,smt,Digi-Key,587-6263-1-ND,https://octopart.com/click/track?ai=8297&sig=0712f19&sid=459&ppid=59159715&vpid=528035991&ct=offers,

-J1,,1,Panasonic,AXK750147G,"Connector, Receptacle, 50 Position, 2Row; Pitch Spacing:0.4Mm; No. Of Contacts:50Contacts; Gender:receptacle; Product Range:p4 Series; Contact Termination Type:surface Mount; No. Of Rows:2Rows; Contact Plating:gold Plated Contacts Rohs Compliant: Yes",tempo,smt,Digi-Key,255-2533-1-ND,https://octopart.com/click/track?ai=8297&sig=053b57f&sid=459&ppid=6716868&vpid=34098380&ct=offers,

-J4,,1,Samtec,FTSH-105-01-L-DV-P-TR,Connector Systems:wire-To-Board; Pitch Spacing:1.27Mm; No. Of Rows:2Rows; No. Of Contacts:10Contacts; Contact Termination Type:surface Mount; Product Range:ftsh Series; Connector Shroud:unshrouded; Contact Material:phosphor Bronze Rohs Compliant: Yes,tempo,smt,Mouser,200-FTSH10501LDVPTR,https://octopart.com/click/track?ai=8297&sig=062d0da&sid=2401&ppid=9236906&vpid=493091076&ct=offers,

-J3,,1,Hirose,BM10NB(0.8)-16DS-0.4V(51),CONN RCPT 16POS SMD GOLD,tempo,smt,Digi-Key,H11823CT-ND,https://octopart.com/click/track?ai=8297&sig=086fb17&sid=459&ppid=19073631&vpid=33743439&ct=offers,

-J2,,1,Molex,505110-2091,CONN FFC/FPC BOTTOM 20P .5MM R/A,tempo,smt,Digi-Key,WM11287CT-ND,https://octopart.com/click/track?ai=8297&sig=08af8fc&sid=459&ppid=57952888&vpid=213397109&ct=offers,

-J5,,1,Hirose,FH35C-13S-0.3SHW(99),CONN FPC 13POS 0.30MM R/A,tempo,smt,Digi-Key,H122265CT-ND,https://octopart.com/click/track?ai=8297&sig=0682a03&sid=459&ppid=33632612&vpid=120326136&ct=offers,

-U8 U12,,2,Texas Instruments,TS5A23159DGSR,Analog Switch Dual SPDT 10-Pin VSSOP T/R,tempo,smt,Digi-Key,296-18598-1-ND,https://octopart.com/click/track?ai=8297&sig=026eeda&sid=459&ppid=512343&vpid=1735040&ct=offers,

-U14,,1,Texas Instruments,SN74LVC1G07YZVR,Buffer/Driver 1-CH Non-Inverting Open Drain CMOS 4-Pin DSBGA T/R,tempo,leadless,Digi-Key,296-21057-1-ND,https://octopart.com/click/track?ai=8297&sig=0e65ea2&sid=459&ppid=664237&vpid=1799702&ct=offers,

-U9 U10,,2,Texas Instruments,SN74AUP1T97YZPR,IC TRNSLTR UNIDIRECTIONAL 6DSBGA,tempo,leadless,Digi-Key,296-17899-1-ND,https://octopart.com/click/track?ai=8297&sig=0e9ca45&sid=459&ppid=464945&vpid=1674955&ct=offers,

-U1,,1,Texas Instruments,INA3221AIRGVR,IC CURRENT SHUNT MONITOR 16VQFN,tempo,leadless,Digi-Key,296-INA3221AIRGVRCT-ND,https://octopart.com/click/track?ai=8297&sig=0b68a57&sid=459&ppid=22631279&vpid=595207883&ct=offers,

-U2,,1,STMicroelectronics,STM32F412CGU6,IC MCU 32BIT 1MB FLASH 48UFQFPN,tempo,leadless,Mouser,511-STM32F412CGU6,https://octopart.com/click/track?ai=8297&sig=0d8fdb9&sid=2401&ppid=74146039&vpid=458625504&ct=offers,

-U3 U4 U5 U6,,4,Texas Instruments,TPS2559DRCR,IC PWR SWITCH N-CHAN 1:1 10VSON,tempo,leadless,Digi-Key,296-40730-1-ND,https://octopart.com/click/track?ai=8297&sig=0e5279b&sid=459&ppid=47153743&vpid=192871412&ct=offers,

-U7 U13 U15,,3,Texas Instruments,TS3A5018RSVR,IC SWITCH QUAD SPDT 16UQFN,tempo,leadless,Digi-Key,296-27552-1-ND,https://octopart.com/click/track?ai=8297&sig=0179e01&sid=459&ppid=18629953&vpid=34364363&ct=offers,

-DS1,,1,Lite-On,LTST-C190GKT,"Smd, 0603, Grn, 569Nm, 6Mcd, Clr, T/r Rohs Compliant: Yes",tempo,smt,Digi-Key,160-1183-1-ND,https://octopart.com/click/track?ai=8297&sig=0316225&sid=459&ppid=549821&vpid=1103326&ct=offers,

-R37 R38 R47 R49 R51,,5,Vishay,CRCW02010000Z0ED,CRCW Series 0201 0.05 W 0 Ohm Jumper Surface Mount Thick Film Chip Resistor,tempo,smt,Digi-Key,541-0.0AGCT-ND,https://octopart.com/click/track?ai=8297&sig=0ed1c57&sid=459&ppid=39994378&vpid=114977597&ct=offers,

-R35 R36 R40,,3,Vishay,CRCW02011M00FKED,"THICK FILM RESISTOR, 1MOHM, 50mW, ±1%",tempo,smt,Digi-Key,541-1.00MAABCT-ND,https://octopart.com/click/track?ai=8297&sig=0227c5e&sid=459&ppid=41857821&vpid=116456133&ct=offers,

-R31,,1,Vishay,CRCW020110K0FNED,Res Thick Film 0201 10K Ohm 1% 1/20W ±200ppm/°C Molded SMD SMD Paper T/R,tempo,smt,Mouser,71-CRCW0201-10K,https://octopart.com/click/track?ai=8297&sig=0ddf9ae&sid=2401&ppid=39803208&vpid=116516014&ct=offers,

-R48,,1,Vishay,CRCW0402120RFKEDC,D10/crcw0402-C 100 120R 1% Et7 E3,tempo,smt,Digi-Key,541-4077-1-ND,https://octopart.com/click/track?ai=8297&sig=08ebab3&sid=459&ppid=75649391&vpid=454352811&ct=offers,

-R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R17 R18 R21 R22 R27 R28 R30 R33 R39 R41 R44 R50 R52 R55 R56,,26,Vishay,CRCW0201100KFKED,Res Thick Film 0201 100K Ohm 1% 1/20W ±100ppm/°C Molded SMD SMD Paper T/R,tempo,smt,Digi-Key,541-100KAABDKR-ND,https://octopart.com/click/track?ai=8297&sig=0c369aa&sid=459&ppid=41857764&vpid=115224580&ct=offers,

-R26,,1,Vishay,CRCW02011K00FNED,Res Thick Film 0201 1K Ohm 1% 1/20W ±200ppm/°C Molded SMD SMD Paper T/R,tempo,smt,Mouser,71-CRCW02011K00FNED,https://octopart.com/click/track?ai=8297&sig=000b814&sid=2401&ppid=39803573&vpid=116319440&ct=offers,

-R1 R19 R23 R24 R42 R43,,6,Stackpole Electronics,CSR0402FKR500,"Thick Film - Current Sensing 0402, 1%, T&r - 1,000 Pcs/reel, 0.5 Ohms Rohs Compliant: Yes",tempo,smt,Digi-Key,CSR0402FKR500CT-ND,https://octopart.com/click/track?ai=8297&sig=0aa805e&sid=459&ppid=21887093&vpid=203733614&ct=offers,

-Q1 Q2,,2,ON Semiconductor,BSS138,Fet 50V 3.5 Ohm Sot23 Rohs Compliant: Yes,tempo,smt,Digi-Key,BSS138CT-ND,https://octopart.com/click/track?ai=8297&sig=004b419&sid=459&ppid=19021258&vpid=452459305&ct=offers,

-SW1 SW2,,2,C&K Components,JS102011SAQN,"Slide Switch, Spdt, 0.3A, 6Vdc, Smd; Contact Configuration:spdt; Switch Operation:on-On; Switch Mounting:surface Mount; Product Range:js Series; Contact Current Max:300Ma; Contact Voltage Ac Max:-; Contact Voltage Dc Max:6V Rohs Compliant: Yes",tempo,smt,Digi-Key,401-1999-1-ND,https://octopart.com/click/track?ai=8297&sig=0e387fb&sid=459&ppid=7088996&vpid=34441074&ct=offers,

diff --git a/docs/sitemap.md b/docs/sitemap.md
deleted file mode 100644
index 2b9f4aaaf8..0000000000
--- a/docs/sitemap.md
+++ /dev/null
@@ -1,79 +0,0 @@
-# Sitemap
-
-## Getting Started
-
-*   [Getting Started Quickly](./getting_started_quickly.md)
-*   [Core Runtime](./core_runtime.md)
-*   [Write Protection](./write_protection.md)
-*   [EC Acronyms and Technologies](./ec_terms.md)
-
-## EC Bringup
-
-*   [New Board Checklist](./new_board_checklist.md)
-
-## Case Closed Debugging (CCD)
-
-*   [Case Closed Debugging Overview][1]
-*   [Google Security Chip Case Closed Debugging][2]
-*   [Tutorials][3]
-
-## Verified Boot Troubleshooting
-
-*   [Cr50 Verified Boot Troubleshooting][4]
-
-## Fingerprint MCU (FPMCU)
-
-*   [Fingerprint MCU (FPMCU)](./fingerprint/fingerprint.md)
-*   [FPMCU Development for Partners](./fingerprint/fingerprint-dev-for-partners.md)
-*   [FPMCU Firmware Testing for Partners](./fingerprint/fingerprint-firmware-testing-for-partners.md)
-*   [FPMCU Debugging](./fingerprint/fingerprint-debugging.md)
-*   [Fingerprint Authentication Design Doc](./fingerprint/fingerprint-authentication-design-doc.md)
-*   [Fingerprint Factory Requirements](./fingerprint/fingerprint-factory-requirements.md)
-*   [Fingerprint Quick Factory Guide](./fingerprint/fingerprint-factory-quick-guide.md)
-*   [Dragonclaw Schematics and Layout](./schematics/dragonclaw)
-
-## Testing
-
-*   [Unit Tests](./unit_tests.md)
-    *   [Porting EC unit tests to Ztest](./ztest.md)
-*   [Code Coverage](./code_coverage.md)
-
-## Updaters
-
-*   [USB Updater](./usb_updater.md)
-
-## USB
-
-*   [USB-C Power Delivery and Alternate Modes](./usb-c.md)
-*   [USB-A and USB-C Policies for Sourcing Power](./usb_power.md)
-*   [USB-C Power Delivery TCPMv2](./usb-tcpmv2.md)
-
-## Verified Boot
-
-*   [Detachable Base Verified Boot](./detachable_base_verified_boot.md)
-
-## EC-3PO
-
-*   [EC-3PO overview](./ec-3po.md)
-*   [EC-3PO design doc](./ec-3po-design.md)
-
-## Zephyr
-
-*   [Initialization Order](./zephyr_init.md)
-*   [Proof-of-Concept-Device Bringup](./zephyr_poc_device_bringup.md)
-*   [Shimming](./zephyr_shim.md)
-*   [Porting EC unit tests to Ztest](./ztest.md)
-
-## Miscellaneous
-
-*   [Low Battery Startup](./low_battery_startup.md)
-*   [I2C tracing via console commands](./i2c-debugging.md)
-*   [Application Processor to EC communication](./ap-ec-comm.md)
-*   [Reducing EC Image Size](./reducing_ec_image_size.md)
-*   [Code Reviews](./code_reviews.md)
-*   [IDE Support](./ide-support.md)
-
-[1]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md
-[2]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
-[3]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/ccd_howtos.md
-[4]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/cr50_vboot_troubleshooting.md
diff --git a/docs/unit_tests.md b/docs/unit_tests.md
deleted file mode 100644
index f26a8519c8..0000000000
--- a/docs/unit_tests.md
+++ /dev/null
@@ -1,232 +0,0 @@
-# Unit Tests
-
-Provides an overview of how to write and run the unit tests in the EC codebase.
-
-[TOC]
-
-## Running Unit Tests {#running}
-
-The unit tests run on the host machine using the [`host` board].
-
-List available unit tests:
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make print-host-tests
-```
-
-Build and run a specific unit test (the `host_command` test in this example):
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make run-host_command
-```
-
-Build and run all unit tests:
-
-```bash
-(chroot) ~/trunk/src/platform/ec $ make runhosttests -j
-```
-
-## Debugging Unit Tests
-
-You need the host version of gdb:
-
-```bash
-(chroot) sudo emerge -j sys-devel/gdb
-```
-
-Then run gdb on the specific test you want to debug (the `host_command` test in this example):
-
-```
-(chroot) gdb build/host/host_command/host_command.exe
-handle SIGUSR1 noprint nostop
-break test_hostcmd_ok
-run
-```
-
-## Writing Unit Tests
-
-Unit tests live in the [`test`] subdirectory of the CrOS EC codebase.
-
-All new unit tests should be written to use the Zephyr Ztest
-[API](https://docs.zephyrproject.org/latest/guides/test/ztest.html). If you are
-making significant changes to an existing test, you should also look at porting
-the test from the EC test API to the Ztest API.
-
-Using the Ztest API makes the unit tests suitable for submitting upstream to the
-Zephyr project, and reduces the porting work when the EC transitions to the
-Zephyr RTOS.
-
-### File headers
-
-Include [`test_util.h`] and any other required includes. In this example, the
-function being tested is defined in the test, but a real unit test would include
-the header file for the module that defines `some_function`.
-
-`test/my_test.c`:
-
-```c
-#include <stdbool.h>
-#include "test_util.h"
-
-static bool some_function(void)
-{
-    return true;
-}
-```
-
-[`test_util.h`] includes `ztest.h` if `CONFIG_ZEPHYR` is defined, or defines a
-mapping from the `zassert` macros to the EC `TEST_ASSERT` macros if
-`CONFIG_ZEPHYR` is not defined.
-
-### Test cases
-
-Define the test cases. Use the `EC_TEST_RETURN` return type on these functions.
-
-```c
-/* Write a function with the following signature: */
-test_static EC_TEST_RETURN test_my_function(void)
-{
-    /* Run some code */
-    bool condition = some_function();
-
-    /* Check that the expected condition is correct. */
-    zassert_true(condition, NULL);
-
-    return EC_SUCCESS;
-}
-```
-
-`test/my_test.c`:
-
-```c
-/* Write a function with the following signature: */
-test_static EC_TEST_RETURN test_my_function(void)
-{
-    /* Run some code */
-    bool condition = some_function();
-
-    /* Check that the expected condition is correct. */
-    TEST_EQ(condition, true, "%d");
-
-    return EC_SUCCESS;
-}
-```
-
-The only difference between those two versions of `test/my_test.c` is the
-assertion: `c zassert_true(condition, NULL);` versus `c TEST_EQ(condition, true,
-"%d");`
-
-### Specify the test cases to run
-
-The EC test API enumerates the test cases using `RUN_TEST` in the `run_test`
-function, while the Ztest API enumerates the test cases using `ztest_unit_test`
-inside another macro for the test suite, inside of `test_main`.
-
-`test/my_test.c`:
-
-```c
-#ifdef CONFIG_ZEPHYR
-void test_main(void)
-{
-    ztest_test_suite(test_my_unit,
-             ztest_unit_test(test_my_function));
-    ztest_run_test_suite(test_my_unit);
-}
-#else
-/* The test framework will call the function named "run_test" */
-void run_test(int argc, char **argv)
-{
-    /* Each unit test can be run using the RUN_TEST macro: */
-    RUN_TEST(test_my_function);
-
-    /* Report the results of all the tests at the end. */
-    test_print_result();
-}
-#endif /* CONFIG_ZEPHYR */
-```
-
-### Task List
-
-EC unit tests can run additional tasks besides the main test thread. The EC unit
-test implementation provides a phtreads-based implementation of the EC task API.
-We do not yet support running additional tasks in Ztest-based tests.
-
-In the [`test`] subdirectory, create a `tasklist` file for your test that lists
-the tasks that should run as part of the test:
-
-`test/my_test.tasklist`:
-
-```c
-/*
- * No test task in this case, but you can use `TASK_TEST` macro to specify one.
- */
-#define CONFIG_TEST_TASK_LIST
-```
-
-### Makefile
-
-Add the test to the `Makefile` so that it can build as an EC unit test:
-
-`test/build.mk`:
-
-```Makefile
-test-list-host += my_test
-```
-
-and
-
-```Makefile
-my_test-y=my_test.o
-```
-
-Make sure you test shows up in the "host" tests:
-
-```bash
-(chroot) $ make print-host-tests | grep my_test
-host-my_test
-run-my_test
-```
-
-### Build and Run
-
-Build and run the test as an EC unit test:
-
-```bash
-(chroot) $ make run-my_test
-```
-
-For building the test as a Zephyr Ztest unit test, follow the instructions in
-[Porting EC unit tests to Ztest](./ztest.md) to build the unit test for Zephyr's
-"native_posix" host-based target.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-**TIP**: Unit tests should be independent from each other as much as possible.
-This keeps the test (and any system state) simple to reason about and also
-allows running unit tests in parallel. You can use the
-[`before_test` hook][`test_util.h`] to reset the state before each test is run.
-***
-<!-- mdformat on -->
-
-## Mocks
-
-We do not yet support mocks for Zephyr Ztest-based tests. [Mocks][`mock`] enable
-you to simulate behavior for parts of the system that you're not directly
-testing. They can also be useful for testing specific edge cases that are hard
-to exercise during normal use (e.g., error conditions).
-
-See the [Mock README] for details.
-
-### Mock Time
-
-When writing unit tests that rely on a clock, it's best not to rely on a real
-hardware clock. It's very difficult to enforce exact timing with a real clock,
-which leads to test flakiness (and developers ignoring tests since they're flaky
-). Instead, use the [Mock Timer] to adjust the time during the test.
-
-[`mock`]: /include/mock
-[Mock Timer]: /include/mock/timer_mock.h
-[`test`]: /test
-[`host` board]: /board/host/
-[`test_util.h`]: /include/test_util.h
-[Mock README]: /common/mock/README.md
diff --git a/docs/usb-c.md b/docs/usb-c.md
deleted file mode 100644
index 1e009f82b2..0000000000
--- a/docs/usb-c.md
+++ /dev/null
@@ -1,219 +0,0 @@
-# EC Implementation of USB-C Power Delivery and Alternate Modes
-
-USB-C PD requires a complex state machine as USB-C PD can operate in many
-different modes. This includes but isn't limited to:
-
-*   Negotiated power contracts. Either side of the cable can source or sink
-    power up to 100W (if supported by device).
-*   Reversed cable mode. This requires a mux to switch the signals before
-    getting to the SoC (or AP).
-*   Debug accessory mode, e.g. [Case Closed Debugging (CCD)]
-*   Multiple uses for the 4 differential pair signals including
-    *   USB SuperSpeed mode (up to 4 lanes for USB data)
-    *   DisplayPort Alternate Mode (up to 4 lanes for DisplayPort data)
-    *   Dock Mode (2 lanes for USB data, and 2 lanes for DisplayPort)
-    *   Audio Accessory mode. (1 lane is used for L and R analog audio signal)
-
-For a more complete list of USB-C Power Delivery features, see the
-[USB-C PD spec][USB PD Spec Id].
-
-This document covers various touch points to consider for USB-C PD and Alternate
-Modes in the EC codebase.
-
-[TOC]
-
-## Glossary
-
-*   PD {#pd}
-    *   Power Delivery. Protocol over USB-C connector that allows up to 100W of
-        power. Not supported on USB-A or USB-B connectors. A good overview of
-        USB PD is found in the [Introduction to USB Power Delivery] application
-        note.
-*   TCPC {#tcpc}
-    *   Type-C Port Controller. Typically a separate IC connected through I2C,
-        sometimes embedded within the EC as a hardware sub module. The TCPC
-        interprets physical layer signals on CC lines and Vbus, and sends that
-        information to the TCPM to decide what action to take. In older designs,
-        there was a separate EC (running this codebase) that acted as the TCPC
-        that communicated with the main EC (also running this codebase), which
-        acted as the TCPM. More info in the official
-        [TCPC spec][USB TCPM Spec Id].
-*   TCPM {#tcpm}
-    *   Type-C Port Manager. Manages the state of the USB-C connection. Makes
-        decisions about what state to transition to. This is the code running on
-        the EC itself.
-*   PE {#pe}
-    *   Policy Engine. According to the [TypeC spec][USB TC Spec Id], the policy
-        engine is the state machine that decides how the USB-C connection
-        progresses through different states and which USB-C PD features are
-        available, such as Try.SRC
-*   TC {#tc}
-    *   Type-C physical layer.
-*   PPC {#ppc}
-    *   Power Path Controller. An optional, separate IC that isolates various
-        USB-C signals from each other and the rest of the board. This IC should
-        prevent shorts and over current/voltage scenarios for Vbus. Some PPCs
-        will protect signals other than Vbus as well.
-*   SSMUX {#ssmux}
-    *   SuperSpeed Mux. This is typically the same IC as the TCPC; it enables
-        the mirrored orientation of the USB-C cable to go to the correct pins on
-        SoC. Also, allows the SuperSpeed signal to be used for different
-        purposes, such as USB data or DisplayPort.
-*   SVDM {#svdm}
-    *   Structured Vendor Defined Messages are a class of [USB PD](#pd) messages
-        to enable non-power related communication between port partners. SVDMs
-        are used to negotiate and set the display port mode on a USB-C
-        connection.
-*   DRP {#drp}
-    *   Dual Role Power Port. A USB-C port that can act as either a power Source
-        or power Sink.
-*   UFP {#ufp}
-    *   Upstream Facing Port. The USB data role that is typical for a peripheral
-        (e.g. HID keyboard).
-*   DFP {#dfp}
-
-    *   Downstream Facing Port. The USB Data role that is typical for a host
-        machine (e.g. device running ChromeOS).
-
-*   E-Mark {#emark}
-
-    *   Electronically marked cable. A USB-C cable that contains an embedded
-        chip in the cable, used to identify the capabilities of the cable.
-
-*   VCONN {#vconn}
-
-    *   Connector Voltage. A dedicated power supply rail for [E-Mark](#emark)
-        cables and other accessory functions (such as display dongles, and
-        docks). VCONN re-uses one of the CC1/CC2 signals to provide 5 volt, 1
-        watt, of power.
-
-## Different PD stacks
-
-Right now platform/ec has two different implementations of USB-C PD stack.
-
-1.  The older implementation is mainly contained within
-    [`usb_pd_protocol.c`](../common/usb_pd_protocol.c) and
-    [`usb_pd_policy.c`](../common/usb_pd_policy.c)
-2.  The newer implementation is found under [`common/usbc`](../common/usbc) and
-    is broken up into multiple different files and state machines
-    *   Policy engine state machine files, `usb_pe_*_sm.c`.
-    *   Protocol engine state machine file, `usb_prl_*_sm.c`.
-    *   State machine framework file, `usb_sm.c`.
-    *   Type-C physical layer state machine files, `usb_tc_*_sm.c`.
-    *   USB-C PD Task file, `usbc_task.c`.
-
-The older implementation supports firmware for device types other than
-Chromebooks. For example, the older stack supports the Zinger, which is the
-USB-C charging device that shipped with Samus, the Google Chromebook Pixel 2.
-The Zinger implements the charger only side of the USB PD protocol.
-
-To use the newer USB-C PD stack implementation, see
-[TCPMv2 Overview](usb-tcpmv2.md).
-
-## Implementation Considerations
-
-In both older and newer implementations, the following details apply:
-
-*   For each USB-C port, there must be two tasks: `PD_C#` and `PD_INT_C#`, where
-    `#` is the port number starting from `0`.
-    *   The `PD_C#` task runs the state machine (old or new) for the port and
-        communicates with the TCPC, MUX, and PPC. This task needs a large task
-        stack.
-    *   The `PD_INT_C#` tasks run at a higher priority than the state machine
-        task, and its sole job is to receive interrupts from the TCPC as quickly
-        as possible then send appropriate messages to other tasks (including
-        `PD_C#`). This task shouldn't need much stack space, but the i2c
-        recovery code requires a decent amount of stack space so it ends up
-        needing a fair amount too.
-*   Saving PD state between EC jumps
-    *   PD communication is disabled in locked RO images (normal state for
-        customer devices). When the jump from RO to RW happens relatively
-        quickly (e.g. there is not a long memory training step), then there
-        aren't many problems when RW takes over and negotiates higher PD
-        contracts.
-    *   To support factory use cases that don't have a battery (and are
-        therefore unlocked), PD communication is enabled in unlocked RO. This
-        allows systems without software sync enabled to get a higher power
-        contract than 15W in RO.
-    *   We save and restore PD state between RO -> RW and RW -> RO jump to allow
-        us to maintain a higher negotiated power through the full jump and
-        re-initialization process. For example, for each port we save the power
-        role, data role, and Vconn sourcing state in battery-backed or
-        non-volatile RAM. This allows the firmware image that is initializing to
-        restore an existing SNK contract (Chromebook as SNK) without cutting
-        power. We don't cut the power from the external supplier because we
-        issue a SoftReset (leaves Vbus intact) instead of a HardReset (drops
-        Vbus) in this contract resume case.
-    *   Both use cases where we actually are able to restore the PD contract
-        require an unlocked RO (e.g. factory) otherwise RO cannot communicate
-        via PD and will drop the higher PD contract (by applying Rp/Rp on the CC
-        lines temporarily)
-        *   The RO->RW use case is for an unlocked (e.g. factory) device that
-            negotiated power and we want to keep that contract after we jump to
-            RW in the normal software sync boot process. This is especially
-            useful when there is no battery and Vbus is our only power source.
-        *   The RW->RO use case happens when we are performing auxiliary FW
-            upgrades during software sync and BIOS instructs the EC to jump back
-            to RO. We'll also try to maintain contracts over an EC reset when
-            unlocked.
-
-## Configuration
-
-There are many `CONFIG_*` options and driver structs that are needed in the
-board.h and board.c implementation.
-
-### TCPC Config
-
-The `tcpc_config` array of `tcpc_config_t` structs defined in `board.c` (or
-baseboard equivalent) should be defined for every board. The index in the
-`tcpc_config` array corresponds to the USB-C port number. This struct should
-point to the specific TCPC driver that corresponds to the TCPC that is being
-used on that port. The i2c port and address for the TCPC are also specified
-here.
-
-### SSMUX Config
-
-The `usb_muxes` array of `usb_mux` structs defined in `board.c` (or baseboard
-equivalent) should be defined for every board. Normally the standard
-`tcpci_tcpm_usb_mux_driver` driver works, especially if TCPC and MUX are the
-same IC.
-
-If the signal strength for the high-speed data lines needs to be tuned for a
-specific hardware layout, the `board_init` field on the `usb_mux` is called
-every time the mux is woken up from a low power state and should be used for
-setting custom board tuning parameters.
-
-### PPC Config
-
-Some boards have an additional IC that sits between the physical USB-C connector
-and the rest of the board. The PPC IC gates whether the Vbus line is an input or
-output signal, based on i2c settings or gpio pins. A PPC also typically provides
-over voltage and over current protection on multiple USB-C pins.
-
-The `ppc_chips` array of `ppc_config_t` structs defined in `board.c` (or
-baseboard equivalent) sets the appropriate driver and i2c port/address for the
-PPC IC.
-
-### Useful Config Options
-
-Many USB-C policies and features are gated by various `CONFIG_*` options that
-should be defined in `board.h` (or baseboard equivalent).
-
-Most USB-C options will start with `CONFIG_USB_PD_` or `CONFIG_USBC_`. For their
-full descriptions see [config.h][config header link]
-
-## Interactions with other tasks
-
-TODO(https://crbug.com/974302): mention `USB_CHG_P#` and `CHARGER`
-
-## Upgrading FW for TCPCs
-
-TODO(https://crbug.com/974302): Mention how this works even though it is in
-depthcharge. Probing now. Need new driver in depthcharge
-
-[Case Closed Debugging (CCD)]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
-[Introduction to USB Power Delivery]: https://www.microchip.com/wwwAppNotes/AppNotes.aspx?appnote=en575003
-[USB PD Spec Id]: https://www.usb.org/document-library/usb-power-delivery
-[USB TC Spec Id]: https://www.usb.org/document-library/usb-type-cr-cable-and-connector-specification-revision-20-august-2019
-[USB TCPM Spec Id]: https://www.usb.org/document-library/usb-type-ctm-port-controller-interface-specification
-[config header link]: ../include/config.h
diff --git a/docs/usb-tcpmv2.md b/docs/usb-tcpmv2.md
deleted file mode 100644
index b942b048d8..0000000000
--- a/docs/usb-tcpmv2.md
+++ /dev/null
@@ -1,221 +0,0 @@
-# EC USB-C Power Delivery TCPMv2 Overview
-
-As the original USB-C Power Delivery (PD) solution for the ChromeOS Embedded
-Controller has aged, it has grown to the point where it is difficult to add new
-features and address bugs. A new PD stack (generally referred to as TCPMv2) has
-been introduced to the codebase for use moving forward. It implements a layered,
-state-based design which tracks more closely with the USB Type-C and USB PD
-specifications.
-
-[TOC]
-
-## Enabling TCPMv2
-
-Boards may enable TCPMv2 by adding the following defines:
-
-*   `CONFIG_USB_PD_TCPMV2`Configures the board to use the new stack.
-*   `CONFIG_USB_DRP_ACC_TRYSRC`: Configures the type of state machine to run (in
-    this case, a DRP which performs Try.SRC behavior). Currently available are
-    DRP and charge-through Vconn-powered device options
-*   `CONFIG_USB_PD_DECODE_SOP`: Sets up messaging for SOP’ and SOP’’, which is
-    strongly encouraged in the TCPMv2 code moving forward
-*   `CONFIG_USB_PID 0x1234`: Sets the USB Product Identifier. This will be
-    shared for all boards within one reference design, and new PIDs may be
-    requested by sending an email to the ChromeOS FW Team.
-*   `CONFIG_USB_PD_REV30`: The TCPMv2 stack defaults to PD2.0 operation but
-    defining this macro enables PD3.0 functionality.
-
-Other configurations to specify behaviors within the task still apply (ex.
-`CONFIG_USB_PD_ALT_MODE_DFP` and `CONFIG_USB_PD_TCPC_LOW_POWER`).
-
-## State Machine Framework
-
-The basis of the TCPMv2 state machines is a generic state machine framework.
-This framework can be found in common/usbc/usb\_sm.c. For each state, there may
-be defined:
-
-*   Entry: Called upon entering a state
-*   Run: Called while steady in a state
-*   Exit: Called upon leaving a state
-*   Parent: Superstate. Enters, exits, and runs alongside the child state. Only
-    enters and exits when transitioning between states which do not share the
-    parent.
-
-All fields are optional and may be set to NULL. A new state is transitioned to
-with a call into set\_state(), which exits the old state and parents and enters
-the new parents and state. States may be changed with set\_state() in any entry
-or run function, but any call from an exit function is ignored since exit is
-only called when a change is already in progress. While in a state, run\_state()
-executes the run function for the current state and parents. If set\_state() is
-called from either an entry function or a run function, the remaining run or
-entry functions are stopped.
-
-Below is a graphical example of what some states may look like. States 1 and 2
-share Parent State 1, while State 3 has Parent State of 2.
-
-![Example States](images/TCPMv2-ExampleStates.png "Example States")
-
-Translated into code, this would be something like below (note it is not
-necessary that the states be a part of an array, but the TCPMv2 code generally
-organizes the states in this way):
-
-```
-static const struct usb_state test_states[] = {
-        [PARENT_1] = {
-                .entry = parent_1_entry,
-                .run = parent_1_run,
-                .exit = parent_1_exit,
-        },
-        [PARENT_2] = {
-                .entry = parent_2_entry,
-                .run = parent_2_run,
-                .exit = parent_2_exit,
-        },
-        [STATE_1] = {
-                .entry = state_1_entry,
-                .run = state_1_run,
-                .exit = state_1_exit,
-                .parent = &test_states[PARENT_1],
-        },
-        [STATE_2] = {
-                .entry = state_2_entry,
-                .run = state_2_run,
-                .exit = state_2_exit,
-                .parent = &test_states[PARENT_1],
-        },
-        [STATE_3] = {
-                .entry = state_3_entry,
-                .run = state_3_run,
-                .exit = state_3_exit,
-                .parent = &test_states[PARENT_2],
-        },
-};
-```
-
-For this example, each test state is written simply to produce a print of its
-function name. The two exceptions are:
-
-*   parent\_1\_run() calls set\_state() into STATE\_2 when called a second time
-*   state\_2\_entry() calls set\_state() into STATE\_3
-
-Graphically, this is represented below:
-
-![Example Transitions](images/TCPMv2-ExampleTransitions.png "Example state transitions and resulting called functions")
-
-And the following code output is produced:
-
-```
-Calling run_state()
-state_1_run
-parent_1_run
-
-Calling run_state()
-state_1_run
-state_1_run calling set_state() to state 2
-state_1_exit
-state_2_entry
-state_2_entry calling set_state() to state 3
-state_2_exit
-parent_1_exit
-parent_2_entry
-state_3_entry
-
-Calling run_state()
-state_3_run
-parent_2_run
-```
-
-## TCPMv2 PD Task
-
-The TCPMv2 PD task is built upon state machines using the above framework and is
-located in common/usbc/usbc\_task.c. It is separated into three layers which
-track with the USB Type-C and USB PD specification states and run in a loop with
-5 ms periods between executions. A graphical representation of these layers is
-below.
-
-![PD Task Loop](images/TCPMv2-TaskLoop.png "PD task loop state machine calls")
-
-The task is designed such that the Type-C (TC) layer could run independently for
-any application which doesn’t wish to enable PD messaging. Boards define their
-appropriate Policy Engine (PE) and TC state machines through their selection of
-a CONFIG\_USB\_\* define, with current options supporting both Dual-Role Ports
-(DRPs) and Charge-Through Vconn-Powered Device (CTVPD). All boards use the same
-Protocol Layer (PRL) code.
-
-## TCPMv2 Layers
-
-### Overview
-
-The three state machines mentioned above interact with each other and the EC
-drivers in order to orchestrate all Type-C connection behavior. Graphically,
-they are represented below.
-
-![PD Task Layers](images/TCPMv2-TaskLayers.png "PD task layer interactions")
-
-Layers communicate with each other using atomic operations on flags and shared
-buffers. Functions calling into each layer are clearly named to indicate the
-layer they are acting on, and anything calling into the PD task should be doing
-so through pd\_\* named functions.
-
-Some specific examples of how this communication works between layers is below.
-If a port partner sends in a Vconn\_swap request, then:
-
-*   PRL will communicate that a message was received to the PE layer through
-    pe\_message\_received(), which sets PE\_FLAGS\_MSG\_RECEIVED and indicates
-    the receive buffer has a message
-*   PE asks with the TC whether the board is sourcing Vconn with
-    tc\_is\_vconn\_src() which checks TC\_FLAGS\_VCONN\_ON
-*   PE tells the PRL to send an ACCEPT message to the port partner through
-    prl\_send\_ctrl\_msg() which fills in shared message information and sets
-    PRL\_FLAGS\_MSG\_XMIT
-*   PRL lets the PE know that the message transmit was successful through
-    pe\_message\_sent() which sets PE\_FLAGS\_TX\_COMPLETE
-*   TC tells the PE layer that the Vconn swap completed with
-    pe\_vconn\_swap\_complete() which sets PE\_FLAGS\_VCONN\_SWAP\_COMPLETE
-
-### Type-C Layer
-
-Defined in the USB Type-C specification, this layer is responsible for basic
-connection. It takes care of setting the CC lines, detecting and debouncing the
-partner CC lines, and performs most of the interactions needed with the PPC and
-USB mux. Once the TC layer has gotten the connection to the point of being
-Attached.SNK or Attached.SRC, it will enable the PRL and PE layers accordingly.
-
-### Protocol Layer
-
-A part of the USB PD specification, the protocol layer is responsible for the
-actual sending and receiving of PD messages with the TCPCs. The layer is
-actually composed of 4 separate state machines running one after the other.
-These state machines are:
-
-*   Chunked receive (RCH): passes messages up to the PE and requests chunks when
-    chunking
-*   Chunked transmit (TCH): receives messages from the PE and waits for chunk
-    requests when chunking
-*   Protocol transmit (PRL\_TX): passes messages to the TCPCs and handles PD 3.0
-    collision avoidance
-*   Protocol hard reset (PRL\_HR): responds to or transmits hard resets, resets
-    PRL layer variables, notifies PE of hard reset receipt or sent
-
-### Policy Engine Layer
-
-The PE layer states are defined as a part of the USB PD specification. State
-names are meant to track very closely with the specification so they can be
-easily searchable and understood. The PE’s primary responsibility is to send and
-process PD messages in order to implement the port’s policy.
-
-## Best Practices
-
-*   Always call return after set\_state(). Once the state has been changed,
-    nothing further should be done in the current state.
-*   Never call set\_state() from an exit function. The call will be ignored as
-    there is already a state transition taking place.
-*   Never call set\_state() from outside the PD task. The task may be waiting in
-    any number of locations and the context should not change around it while it
-    does so.
-*   Always use flags to communicate between layers, and to communicate with the
-    PD task from other tasks. Flags should be accessed through atomic
-    operations.
-*   Always use pd\_\* functions to access the PD task from other tasks.
-*   Always write unit tests as code is added, to verify new code works and
-    protect against regressions as development continues.
diff --git a/docs/usb_power.md b/docs/usb_power.md
deleted file mode 100644
index 95177dc150..0000000000
--- a/docs/usb_power.md
+++ /dev/null
@@ -1,277 +0,0 @@
-# USB Power Considerations
-
-Users want to be able to charge external devices using their Chromebook USB
-ports, e.g. charge a phone from their Chromebook. We want to provide a fast
-charging experience to end-users, so we prefer to offer high power charging when
-possible.
-
-[TOC]
-
-## Summary of Design Requirements
-
-For explanations of calculations see rest of doc.
-
-### Total System Power
-
-Total current needed for external USB devices at 5V:
-
-```
-((Number of Type-C Ports) * (1800mA)) + 1500mA +
-((Number of Type-A Ports) * (900mA)) + 600mA§
-```
-
-§ The additional 600mA can be omitted if BC1.2 is not supported for Type-A
-
-### Daughter Board Considerations
-
-If a daughter board has 1 Type-A (supporting BC 1.2) and 1 Type-C, the max
-potential current load at 5V is `Type-A Vbus (1500mA) + Type-C Vbus (3000mA) +
-Type-C Vconn (300mA) = 4800mA`
-
-*   The DB ribbon cables need to be able to carry enough current to supply 24W
-    (4.8A * 5V) of power to the DB.
-    *   This may be on a single or multiple power rails depending on hardware
-        design.
-*   The ground path on the ribbon cable from the DB also needs to be able to
-    carry enough current to match the power rails.
-
-## USB Type-A Ports
-
-For Type-A ports, the [BC 1.2 Specification] adds higher power modes on top of
-the [USB 3.2 Specification]. While BC 1.2 support isn't required, it is
-preferred, as it allows end-users to charge their devices more quickly.
-
-[BC 1.2 Specification] defines multiple modes of operation including, but not
-limited to:
-
-*   CDP - Charging Downstream Port
-    *   Allows USB Data. Provides guaranteed 1.5A @ 5V power.
-    *   ChromeOS device can act as a CDP.
-*   SDP - Standard Downstream Port
-    *   Allows USB Data. Provides guaranteed current defined by USB
-        Specifications
-        *   For USB3, provides guaranteed current of 0.9A @ 5V.
-        *   For USB2, provides guaranteed current of 0.5A @ 5V.
-    *   ChromeOS device can act as a SDP.
-*   DCP - Dedicated Charging Port
-    *   No USB Data. Provides max of 1.5A @ 5V power.
-    *   ChromeOS device **will not** act as a DCP.
-
-For detection logic of each mode (e.g. on the D+ and D- pins) and nuance of
-power/current power requirements, see full [BC 1.2 Specification].
-
-Without BC 1.2 support, the max power requirements match that of a Standard
-Downstream Port (SDP) as defined by various specification (e.g.
-[USB 3.2 Specification]).
-
-### ChromeOS as Source - Policy for Type-A
-
-If BC 1.2 is supported on a ChromeOS device, then the first Type-A port in use
-will act as a CDP, providing a maximum current of 1.5A while also enabling USB
-data. All other Type-A ports will only be SDP, providing a maximum current of
-900mA.
-
-Note that the CDP Type-A port allocation is dynamic; the first Type-A port to
-draw more than 900mA gets to be the CDP, with a maximum current of 1.5A. Then
-all other Type-A ports get downgraded to the lower, 900mA current limit (i.e.
-SDP) while the first Type-A port maintains a current draw of more than 900mA. In
-practice, this means that the first Type-A device plugged in gets to consume
-1.5A and any Type-A device inserted after that will only get 900mA.
-
-Once the Type-A device drawing 1.5A stops pulling more than 900mA or is
-physically removed, then the extra 600mA (as well as CDP advertisement) becomes
-available to any Type-A port. In practice, Type-A devices only determine current
-limits when they are first inserted, so any Type-A device that is still plugged
-in when the 1.5A device is removed will not notice that it can pull more
-current. This means that the first Type-A device **inserted** after removing the
-original 1.5A device gets access to 1.5A.
-
-The allocation of the one CDP Type-A port is unaffected by user interaction with
-Type-C ports. Once a Type-A port has been claimed as CDP, inserting a Type-C
-device will not revoke the CDP status of the Type-A port.
-
-For example, the below sequence of events illustrates the above Type-A policy if
-BC 1.2 is supported:
-
-1.  Insert Type-A phone first
-    *   Since no other Type-A port is currently supplying more than 900mA, this
-        port can supply 1.5A as the CDP.
-    *   Phone pulls 1.5A; other Type-A ports are now marked as SDPs limiting
-        current to 900mA, each.
-    *   Current state: `phone @ 1.5A`.
-2.  Insert Type-A mouse second
-    *   Mouse is only allowed 900mA since port is SDP.
-    *   Current state: `phone @ 1.5A` and `mouse @ 900mA`.
-3.  Remove phone
-    *   High-current port status is relinquished. Now first Type-A port to draw
-        more than 900mA will claim the one high-current port status (as the
-        CDP).
-    *   Mouse does not realize that more power is available since most Type-A
-        devices only determine their current limits upon connection.
-    *   Current state: `mouse @ 900ma`.
-4.  Insert Type-A battery pack
-    *   Since no other Type-A port is currently supplying more than 900mA, this
-        port can supply 1.5A as the CDP.
-    *   Battery pack pulls 1.5A; other Type-A ports are now marked as SDPs
-        limiting current to 900mA, each.
-    *   Current state: `mouse @ 900ma` and `battery pack @ 1.5A`.
-
-The total current needed for all Type-A ports at 5V is:
-
-```
-if (BC1.2_Supported)
-    (# Type-A Ports)*(900mA) + 600mA
-else
-    (# Type-A Ports)*(900mA)
-```
-
-## USB Type-C Ports
-
-USB Type-C allows for dynamic negotiation of high power contracts; this is
-accomplished through varying CC resistors and/or USB-C Power Delivery (PD). More
-in-depth information can be found in the [USB Type-C Specification] \(section
-4.5.2.3) and the [USB PD Specification]. CC resistor contracts can range from
-500mA/5V to 3A/5V, while PD contracts can range from 0mA/3.3V to 5A/20V.
-
-### ChromeOS as Source - Policy for Type-C
-
-**Note:** Behavior outlined here is only implemented in the TCPMv2 Device
-Policy Manager (DPM) when a board defines a non-zero maximum number of 3A
-ports supported through `CONFIG_USB_PD_3A_PORTS`.
-
-ChromeOS devices currently source power to external USB devices at 5V with a
-typical current of 1.5A for each Type-C port. In certain scenarios, a Type-C
-port can source up to 3A @ 5V.
-
-ChromeOS prefers that the first PD-capable Type-C device **that requires 3A**
-should get 3A guaranteed at 5V. Once the maximum supported number of PD-capable
-Type-C device has claimed 3A, then other PD-capable Type-C devices will only be
-offered a maximum of 1.5A.
-
-If Fast Role Swap (FRS) is supported and a sourcing port partner reports
-requiring 3A after a fast role swap, then this port should be allocated 3A if
-no more PD-capable sinks require 3A, and FRS detection may be enabled.  Once a
-PD-capable device **that requires 3A** is inserted, the FRS port may have FRS
-detection disabled if the maximum number of 3A ports has been reached.
-
-If there are no PD-capable Type-C devices requiring 3A and no FRS ports
-requiring 3A, then the first non-PD device will be given 3A until a PD-capable
-device **that requires 3A** is inserted, or until an FRS source that requires
-3A is inserted.
-
-Devices will indicate they require 3A operating current in their sink
-capabilities, and this will be used as the trigger to let the EC know to
-offer that port a 3A source contract.  FRS source partners will also
-indicate the need for 3A in their sink capabilities, under their Fast Role
-Swap required current.
-
-This policy is laid out in the following flow chart.  Current policy for the
-"next" port allocation is to select the lowest port number any time more than
-one port meets criteria to receive 3A.
-
-Port balancing will occur when:
-* Sink Capabilities are received for a device
-* Source capabilities are not replied to after nCapsCount, indicating a non-PD
-  sink
-* Power roles are swapped
-* Detach occurs
-
-![Source Port Balancing](images/usb_source_port_balancing.png "Source Port Balancing")
-
-Inserting a Type-A device does not affect the power assignment for Type-C ports;
-only Type-C devices affect the power of Type-C ports.
-
-For example, the below sequence of events illustrates the above Type-C policy
-with a board with a maximum number of 1 3A-ports supported:
-
-1.  A non-PD capable Type-C keyboard is inserted first
-    *   Keyboard will be offered 1.5A initially
-    *   Current state: `keyboard @ 1.5A`.
-2.  Partner is established to be non-PD through reaching PE\_SRC\_Disabled.
-    *   Since there are no other PD-capable devices and this is the first
-        device, offer this device 3A via CC resistor change.
-    *   Current state: `keyboard @ 3A`.
-3.  A non-PD capable Type-C mouse is inserted second
-    *   It will be offered 1.5A since there is already another non-PD device
-        claiming 3A.
-    *   Current state: `keyboard @ 3A` and `mouse @ 1.5A`.
-4.  A PD-capable Type-C hub is inserted third
-    *   Initially negotiate for 1.5A.
-    *   Since this is a PD device, query its operational current through
-        requesting Sink Capabilities.
-    *   Hub does not want high power from Chromebook; hub continues to receive
-        1.5A.
-    *   Keyboard gets to maintain higher 3A current supply.
-    *   Current state: `keyboard @ 3A` and `mouse @ 1.5A` and `hub @ 1.5A`.
-5.  A PD-capable Type-C phone is inserted fourth
-    *   Phone is initially offered 1.5A.
-    *   Since this is a PD device, query its operational current through
-        requesting Sink Capabilities.
-    *   The phone reports it wants 3A.
-    *   Since PD devices are preferred for 3A, the non-PD keyboard will be
-        downgraded from 3A to 1.5A via a CC resistor change.
-    *   After tSinkAdj (60 ms), phone is offered 3A through new Source
-        Capabilities.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
-        and `phone @ 3A`.
-6.  A PD-capable Type-C tablet is inserted fifth
-    *   Tablet is initially offered 1.5A.
-    *   Since this is a PD device, query its operational current through
-        requesting Sink Capabilities.
-    *   Tablet would like 3A, but the board has reached its maximum number of
-        supported 3A ports.  Note this port's desired current for later.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
-        and `phone @ 3A` and `tablet @ 1.5A`.
-7.  The PD-capable phone is removed
-    *   The next PD-capable sink device is offered 3A: the tablet
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
-        and `tablet @ 3A`.
-8.  A FRS-capable dock is inserted
-    *   The dock is sourcing us
-    *   Since this is a PD capable device, query its FRS current through
-        requesting Sink Capabilities.
-    *   Dock reports requiring 3A current after FRS.
-    *   Tablet is currently occupying the 3A port, so note this port's desired
-        FRS current for later.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`
-        and `tablet @ 3A`; dock `FRS detection disabled`
-9.  The PD-capable tablet is removed
-    *   The next PD-capable device requiring 3A is offered 3A. If there are
-        no PD-capable devices requiring 3A, then the next FRS device is
-        allocated 3A.
-    *   The hub only requires 1.5A, so FRS is enabled for the dock.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 1.5A` and `hub @ 1.5A`;
-        dock `FRS detection enabled`
-10.  The FRS dock is removed
-    *   The next PD-capable  device requiring 3A is offered 3A. If there are
-        no PD-capable devices requiring 3A, then the next FRS device is
-        allocated 3A.  If there are no FRS devices, then the next non-PD
-        capable device is given 3A.
-    *   The hub only requires 1.5A, so mouse is given 3A via CC
-        resistor change.
-    *   Current state: `keyboard @ 1.5A` and `mouse @ 3A` and `hub @ 1.5A`.
-11. The non-PD capable mouse is removed
-    *   The hub does not require 3A.
-    *   Current state: `keyboard @ 3A` and `hub @ 1.5A`.
-
-Note: Not all released Chromebooks implement the above policy due to
-pre-existing hardware design constraints.
-
-Type-C ports also need to provide an additional 300mA @ 5V (1.5W) for Vconn on
-every port. Note: the 1.5W for Vconn may also be supplied at other voltages,
-such as 455mA @ 3.3V instead.
-
-The total current needed for all Type-C ports at 5V is:
-
-```
-((Number of Type-C Ports) * (1500mA + 300mA)) + 1500mA
-```
-
-The total maximum current needed for a single Type-C port at 5V is `(3000mA +
-300mA) = 3.3A`. This max current for a single port is especially relevant for
-sizing the daughter board ribbon cable appropriately.
-
-[BC 1.2 Specification]: <https://www.usb.org/document-library/battery-charging-v12-spec-and-adopters-agreement>
-[USB 3.2 Specification]: <https://www.usb.org/document-library/usb-32-specification-released-september-22-2017-and-ecns>
-[USB PD Specification]: https://www.usb.org/document-library/usb-power-delivery
-[USB Type-C Specification]: https://www.usb.org/document-library/usb-type-cr-cable-and-connector-specification-revision-14-march-29-2019
diff --git a/docs/usb_updater.md b/docs/usb_updater.md
deleted file mode 100644
index f1505550d1..0000000000
--- a/docs/usb_updater.md
+++ /dev/null
@@ -1,201 +0,0 @@
-# EC update over USB
-
-chip/g (Cr50) and common code (hammer, servo_micro/v4) update over USB protocols
-share a lot in terms of protocol and ideas, but use different code bases.
-
-chip/g EC-side implementation is found in `chip/g/*upgrade*`, and the userspace
-tool which provides updates over USB among with supporting other features and
-interfaces is found in `extra/usb_updater/gsctool.c`.
-
-Common code uses implementations in `common/*update*.c` and
-`include/*update*.h`, and `extra/usb_updater/usb_updater2.c` for the userspace
-updater.
-
-## Cr50-specific notes
-
-The Cr50 firmware image consists of multiple sections, of interest to the USB
-updater are the RO and RW code sections, two of each. When firmware update
-session is established, the Cr50 device reports locations of backup RW and RO
-sections (those not currently used by the device).
-
-Based on this information the updater carves out the appropriate sections from
-the full Cr50 firmware binary image and sends them to the device for programming
-into flash. Once the new sections are programmed and the device is restarted,
-the new RO and RW are used if they pass verification and are logically newer
-than the existing sections.
-
-There are two ways to communicate with the Cr50 device: USB and `/dev/tpm0`
-(when `gsctool` is running on a chromebook with the Cr50 device). Originally
-different protocols were used to communicate over different channels, starting
-with version 3 the same protocol is used.
-
-## Common-code notes
-
-For non-Cr50 or chip/g devices (common code), the layout is a bit different, as
-devices usually have a single RO and a single RW, where RO is truly read-only in
-production, and verifies RW before jumping to it.
-
-For testing and development, `usb_updater2` is provided, while production code
-will use `hammerd` (in `src/platform/hammerd`) to update the device.
-
-## Update protocol
-
-The host (either a local AP or a workstation) is the master of the firmware
-update protocol, it sends data to the Cr50 device, which processes it and
-responds.
-
-The encapsulation format is different between the `/dev/tpm0` and USB cases:
-
-```
-  4 bytes      4 bytes         4 bytes               variable size
-+-----------+--------------+---------------+----------~~--------------+
-+ total size| block digest |  dest address |           data           |
-+-----------+--------------+---------------+----------~~--------------+
- \           \                                                       /
-  \           \                                                     /
-   \           +----- FW update PDU sent over /dev/tpm0 -----------+
-    \                                                             /
-     +--------- USB frame, requires total size field ------------+
-```
-
-The update protocol data units (PDUs) are passed over `/dev/tpm0`, the
-encapsulation includes integrity verification and destination address of the
-data (more of this later). `/dev/tpm0` transactions pretty much do not have size
-limits, whereas the USB data is sent in chunks of the size determined when the
-USB connection is set up. This is why USB requires an additional encapsulation
-into frames to communicate the PDU size to the client side so that the PDU can
-be reassembled before passing to the programming function.
-
-In general, the protocol consists of two phases: connection establishment and
-actual image transfer.
-
-The very first PDU of the transfer session is used to establish the connection.
-The first PDU does not have any data, and the `dest address` field is set to
-zero. Receiving such a PDU signals the programming function that the host
-intends to transfer a new image.
-
-The response to the first PDU varies depending on the protocol version.
-
-Note that protocol versions before 5 are described here for completeness, but
-are not supported any more.
-
-Version 1 is used over `/dev/tpm0`. The response is either 4 or 1 bytes in size.
-The 4 byte response is the *base address* of the backup RW section, and there is
-no support for RO updates. The one byte response is an error indication,
-possibly reporting flash erase failure, command format error, etc.
-
-Version 2 is used over USB. The response is 8 bytes in size. The first four
-bytes are either the *base address* of the backup RW section (still no RO
-updates), or an error code, the same as in Version 1. The second 4 bytes are the
-protocol version number (set to 2).
-
-All versions above 2 behave the same over `/dev/tpm0` and USB.
-
-Version 3 response is 16 bytes in size. The first 4 bytes are the error code the
-second 4 bytes are the protocol version (set to 3) and then 4 byte *offset* of
-the RO section followed by the 4 byte *offset* of the RW section.
-
-Version 4 response in addition to version 3 provides header revision fields for
-active RO and RW images running on the target.
-
-Once the connection is established, the image to be programmed into flash is
-transferred to the Cr50 in 1K PDUs. In versions 1 and 2 the address in the
-header is the absolute address to place the block to, in version 3 and later it
-is the offset into the flash.
-
-Protocol version 5 includes RO and RW key ID information into the first PDU
-response. The key ID could be used to tell between prod and dev signing modes,
-among other things.
-
-Protocol version 6 does not change the format of the first PDU response, but it
-indicates the target's ability to channel TPM vendor commands through USB
-connection.
-
-Common-code updater also uses protocol version 6, but has a fairly different
-`first_response_pdu` header, indicated by setting `1` in the higher 16-bit for
-the protocol version field (`header_type`). The response includes fields such as
-maximum PDU size (which is not fixed to 1KB like for Cr50), flash protection
-status, version string, and a minimum rollback version.
-
-Details can be found in `include/update_fw.h`.
-
-### State machine (update over USB)
-
-This describes the EC-side state machine for update over USB.
-
-IDLE state:
-
-*   If host sends update start PDU (a command without any payload, digest = 0
-    and base = 0):
-
-    *   Reply with `first_update_pdu` block. Go to OUTSIDE_BLOCK state.
-
-*   If host sends a vendor command (see below), execute that, reply, and stay in
-    IDLE state. Note that vendor commands are only accepted in IDLE state.
-
-OUTSIDE_BLOCK (preparing to receive start of PDU):
-
-*   If no data is received in 5 seconds, go back to IDLE state.
-*   If host sends `UPDATE_DONE` command (by setting `dest address` to
-    `0xb007ab1e`), go back to IDLE state.
-*   If host sends a valid block start with a valid address, copy the rest of the
-    payload and go to INSIDE_BLOCK state.
-
-INSIDE_BLOCK (in a middle of a PDU):
-
-*   If no data is received in 5 seconds, go back to IDLE state.
-*   Copy data to a buffer.
-
-    *   If buffer is full (i.e. matches the total expected PDU size), write the
-        data and go to OUTSIDE_BLOCK.
-    *   Else, stay in INSIDE_BLOCK.
-
-### Vendor commands (channeled TPM command, Cr50)
-
-When channeling TPM vendor commands the USB frame looks as follows:
-
-```
-  4 bytes      4 bytes         4 bytes       2 bytes      variable size
-+-----------+--------------+---------------+-----------+------~~~-------+
-+ total size| block digest |    EXT_CMD    | vend. sub.|      data      |
-+-----------+--------------+---------------+-----------+------~~~-------+
-```
-
-Where `Vend. sub` is the vendor subcommand, and data field is subcommand
-dependent. The target tells between update PDUs and encapsulated vendor
-subcommands by looking at the `EXT_CMD` value - it is set to `0xbaccd00a` and as
-such is guaranteed not to be a valid update PDU destination address.
-
-These commands cannot exceed the USB packet size (typically 64 bytes), as no
-reassembly is performed for such frames.
-
-The vendor command response size is not fixed, it is subcommand dependent.
-
-The Cr50 device responds to each update PDU with a confirmation which is 4 bytes
-in size in protocol version 2, and 1 byte in size in all other versions. Zero
-value means success, non-zero value is the error code reported by Cr50.
-
-Again, vendor command responses are subcommand specific.
-
-### Vendor commands (common code)
-
-Vendor commands for command code look very similar to the TPM vendor commands
-above, except that we use `UPDATE_EXTRA_CMD` (`b007ab1f`) instead of `EXT_CMD`,
-and `Vend. sub.` have a limit set of values (unless otherwise noted, commands
-take no parameter, and reply with a single 1-byte status code):
-
-*   UPDATE_EXTRA_CMD_IMMEDIATE_RESET (0): Tell EC to reboot immediately.
-*   UPDATE_EXTRA_CMD_JUMP_TO_RW (1): Tell EC (in RO) to jump to RW, if the
-    signature verifies.
-*   UPDATE_EXTRA_CMD_STAY_IN_RO (2): Tell EC (in RO), to stay in RO, and not
-    jump to RW automatically. After this command is sent, a reset is necessary
-    for the EC to accept to jump to RW again.
-*   UPDATE_EXTRA_CMD_UNLOCK_RW (3): Tell EC to unlock RW on next reset.
-*   UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK (4): Tell EC to unlock ROLLBACK on next
-    reset.
-*   UPDATE_EXTRA_CMD_INJECT_ENTROPY (5): Inject entropy into the device-specific
-    unique identifier (takes at least CONFIG_ROLLBACK_SECRET_SIZE=32 bytes of
-    data).
-*   UPDATE_EXTRA_CMD_PAIR_CHALLENGE (6): Tell EC to answer a X25519 challenge
-    for pairing. Takes in a `struct pair_challenge` as data, answers with a
-    `struct pair_challenge_response`.
diff --git a/docs/write_protection.md b/docs/write_protection.md
deleted file mode 100644
index 0ce6253a04..0000000000
--- a/docs/write_protection.md
+++ /dev/null
@@ -1,307 +0,0 @@
-# Firmware Write Protection
-
-[TOC]
-
-This is a somewhat tricky topic since write protection implementations can
-differ between chips, and the hardware write protection has changed over time,
-so please edit or open a bug if something is not clear.
-
-## Terminology
-
-## RO and RW
-
-MCUs running the EC code have read-only (RO) and read-write (RW) firmware.
-Coming out of reset, the MCU boots into its RO firmware.
-
-In the case of the EC, the RO firmware boots the host and asks it to verify a
-hash of the RW firmware (software sync). If the RW firmware is invalid, it is
-updated from a copy in the host's RW firmware.
-
-In the case of the FPMCU, the RO firmware uses the public key embedded in it to
-validate the signature of the RW firmware. If the RW firmware is invalid it does
-not jump to the RW firmware.
-
-Once the RW firmware is validated, the MCU jumps to it (without rebooting). The
-RO firmware is locked in the factory and is never changed. The RW firmware can
-be updated later by pushing a new system firmware containing an updated RW
-region.
-
-Note that both the RO and RW firmware regions are normally protected once write
-protect has been turned on.
-
-In the case of the EC, the RW region is unprotected at MCU boot until it has
-been verified by the host. The RW region is protected before the Linux kernel is
-loaded.
-
-In the case of the FPMCU, the RW region is protected before jumping the RO
-firmware jumps to it.
-
-## Hardware Write Protect {#hw_wp}
-
-On modern Chrome OS devices, the Cr50 (aka GSC / TPM) provides a "hardware write
-protect" GPIO that is connected to the AP SPI flash, EC SPI flash, EEPROM, and
-FPMCU via a [GPIO][write_protect_gpio]. This "hardware write protect" can only
-be disabled with [Servo] or [SuzyQ](["CCD open"]) and corresponds to
-[`OverrideWP`] in ccd. Disabling this write protect disables it for everything
-connected to this signal.
-
-In the case of the FPMCU, the hardware write protect GPIO is tied to the STM32
-`BOOT0` pin, which is what tells the MCU to enter the STM32 bootloader mode.
-
-You may see various references to a
-[write protect screw in documentation][wp_screw]. Older Chrome OS devices had a
-write protect screw that had to be physically removed. More details on this
-history can be found here: http://go/cros-wp-status.
-
-Another way of disabling hardware write protection is to remove the battery;
-this method is mainly used during bringup.
-
-Additional reference:
-https://chromium.googlesource.com/chromiumos/docs/+/HEAD/write_protection.md
-
-## Changing Hardware Write Protection
-
-Modifying the state of hardware write protection (via Cr50 GPIO) can be done if
-the ["CCD open"] process has been completed.
-
-<!-- mdformat off(b/139308852) -->
-*** note
-`servod` *must* be running for `dut-control` to work. See the [Servo] page for
-details.
-***
-<!-- mdformat on -->
-
-### Enable Hardware Write Protection
-
-```bash
-(chroot)$ dut-control fw_wp_state:force_on
-```
-
-### Disable Hardware Write Protection
-
-```bash
-(chroot)$ dut-control fw_wp_state:force_off
-```
-
-### Enable/Disable Hardware Write Protection via Cr50 Console
-
-You can use the following commands from the [Cr50 console]:
-
-```bash
-wp disable
-```
-
-```bash
-wp enable
-```
-
-```bash
-wp follow_batt_pres
-```
-
-## Software Write Protect
-
-Software-based write protect state stored in non-volatile memory. If hardware
-write protect is enabled, software write protect can be enabled but can’t be
-disabled. If hardware write protect is disabled, software write protect can be
-enabled or disabled (note that some implementations require an EC reset to
-disable software write protect).
-
-The underlying mechanism implementing software write protect may differ between
-EC chips. However, the common requirements are that software write protect can
-only be disabled when hardware write protect is off and that the RO firmware
-must be protected before jumping to RW firmware if protection is enabled.
-
-Additional reference:
-https://www.google.com/chromeos/partner/fe/docs/cpfe/firmwaretestmanual.html#software-write-protect
-
-## Changing Software Write Protection
-
-<!-- mdformat off(b/139308852) -->
-*** note
-*NOTE*: You cannot disable software write protect if hardware write protect is
-enabled.
-***
-<!-- mdformat on -->
-
-Software write protection can be toggled with `ectool --name=cros_fp
-flashprotect enable/disable`, which sends the `EC_CMD_FLASH_PROTECT` command
-toggling `EC_FLASH_PROTECT_RO_AT_BOOT` (changing `--name` to target different
-ECs).
-
-### Changing Software Write Protection with ectool
-
-#### ectool flashprotect
-
-Print out current flash protection state.
-
-```
-Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now all_now
-Valid flags:         0x0000003f wp_gpio_asserted ro_at_boot ro_now all_now STUCK INCONSISTENT
-Writable flags:      0x00000000
-```
-
-`Flash protect flags` - Current flags that are set.
-
-`Valid flags` - All the options for flash protection.
-
-`Writable flags` - The flags that currently can be changed. (In this case, no
-flags can be changed).
-
-Flags:
-
-*   `wp_gpio_asserted` - Whether the hardware write protect GPIO is currently
-    asserted (read only).
-
-*   `ro_at_boot` - Whether the EC will write protect the RO firmware on the next
-    boot of the EC.
-
-*   `ro_now` - Protect the read-only portion of flash immediately. Requires
-    hardware WP be enabled.
-
-*   `all_now` - Protect the entire flash (including RW) immediately. Requires
-    hardware WP be enabled.
-
-*   `STUCK` - Flash protection settings have been fused and can’t be cleared
-    (should not happen during normal operation. Read only.)
-
-*   `INCONSISTENT` - One or more banks of flash is not protected when it should
-    be (should not happen during normal operation. Read only.).
-
-#### ectool flashprotect enable
-
-Set `ro_at_boot` flag. The next time the EC is reset it will protect the flash.
-Note that this requires a cold reset.
-
-#### ectool flashprotect enable now
-
-Set `ro_at_boot` `ro_now all_now` flags and immediately protect the flash. Note
-that this will fail if hardware write protect is disabled.
-
-#### ectool flashprotect disable
-
-Clear `ro_at_boot` flag. This can only be cleared if the EC booted without
-hardware write protect enabled.
-
-Note that you must reset the EC to clear write protect after removing the screw.
-If the `ro_at_boot` flag set, and the EC resets with the HW gpio disabled, the
-EC will leave the flash unprotected (`ro_now` and `all_now` flags are not set)
-but leave `ro_at_boot` flag set.
-
-### Changing Software Write Protection with flashrom
-
-#### View the current state of software write protection
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x00
-WP: status.srp0: 0
-WP: write protect is disabled.
-WP: write protect range: start=0x00000000, len=0x00000000
-```
-
-#### Enable software write protection
-
-This is immediate. The protection range indicates the RO region of the firmware.
-
-```bash
-(chroot) $ flashrom -p ec --wp-enable
-```
-
-```
-SUCCESS
-```
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x80
-WP: status.srp0: 1
-WP: write protect is enabled.
-WP: write protect range: start=0x00000000, len=0x0001f800
-```
-
-#### Disable software write protection
-
-Disable can only be done with hardware write protect disabled.
-
-```bash
-(chroot) $ flashrom -p ec --wp-disable
-```
-
-```
-FAILED: RO_AT_BOOT is not clear.
-FAILED
-```
-
-Reboot with [hardware write protection](#hw_wp) disabled. Note that protection
-is still enabled, but the protection range is zero.
-
-```bash
-(chroot) $ flashrom -p ec --wp-status
-```
-
-```
-WP: status: 0x80
-WP: status.srp0: 1
-WP: write protect is enabled.
-WP: write protect range: start=0x00000000, len=0x00000000
-```
-
-```bash
-(chroot) $ flashrom -p ec --wp-disable
-```
-
-```
-SUCCESS
-```
-
-## system_is_locked()
-
-The [`system_is_locked()`] function in the EC code returns false if the HW write
-protect GPIO is disabled, or the read-only firmware is not protected.
-
-One way this is used in the FPMCU source is to compile test or debug
-functionality into the firmware. Guarding the test functionality with
-`system_is_locked` allows us to execute the test code in automated testing by
-disabling the hardware write protection; this means we can run the automated
-tests against the exact same firmware we ship, rather than a different version
-that has test functionality compiled in or out.
-
-## RDP1 {#rdp1}
-
-Stands for Readout Protection Level 1.
-
-Protects user flash memory against a debugger (JTAG/SWD) or potential malicious
-code stored in RAM by disabling access (a bus error is generated when read
-access is requested). Otherwise (no debugger connected and no boot in RAM set),
-all read/program/erase operations from/to flash are allowed.
-
-When switching to a lower level of RDP (i.e., setting to 0), the user flash
-memory is mass erased (set to all `0xFF`).
-
-Note that this completely destroys *all* of the firmware, including the RO
-section.
-
-### Additional References
-
-https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1222094
-
-## EC Flash Read/Write Command Write Protection Checks
-
-The EC code command handlers (`command_flash_erase`, `command_flash_write`,
-etc.) return an error if `EC_FLASH_PROTECT_ALL_NOW` is set.
-
-["CCD open"]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Open-CCD
-[Cr50 console]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md#Consoles
-[Servo]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/README.md
-[`OverrideWP`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging_cr50.md
-[`system_is_locked()`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/aaba1d5efd51082d143ce2ac64e6caf9cb14d5e5/common/system.c#195
-[wp_screw]: https://www.chromium.org/chromium-os/firmware-porting-guide/firmware-ec-write-protection
-[write_protect_gpio]: https://chromium.googlesource.com/chromiumos/platform/ec/+/aaba1d5efd51082d143ce2ac64e6caf9cb14d5e5/include/ec_commands.h#1599
-[SuzyQ]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/ccd.md#SuzyQ-SuzyQable
diff --git a/docs/zephyr_build.md b/docs/zephyr_build.md
deleted file mode 100644
index 5a3c809724..0000000000
--- a/docs/zephyr_build.md
+++ /dev/null
@@ -1,164 +0,0 @@
-# Building Zephyr OS
-
-[TOC]
-
-Chromium OS EC uses the `zmake` tool to build Zephyr.
-
-This section describes how to build and use zmake.
-
-## Syncing the source
-
-N.B. The Zephyr build relies on multiple repos and tools which get installed as
-packages into the chroot.  This means that partial syncs are not supported
-(i.e. just doing `repo sync .` in platform/ec). You must run
-`~/trunk/src/scripts/update_chroot` frequently, ideally each time you do a full
-repo sync. This will update zmake and the repos in src/third_party/zephyr
-
-
-## Working inside the chroot
-
-### Install zmake
-
-The `zephyr-build-tools` ebuild builds and installed zmake. This should happen
-automatically, with the caveat above.
-
-To do this manually and run tests:
-
-```bash
-FEATURE=test sudo -E emerge zephyr-build-tools
-```
-
-
-### Building
-
-You can build zephyr with:
-
-```bash
-emerge-volteer chromeos-zephyr
-```
-
-For local development you can run zmake directly; see instruction below.
-
-## Working outside the chroot
-
-Running outside the Chromium OS chroot is useful for upstream work and for
-those using the EC outside the Chromium OS.
-
-
-### Remove west, if installed [b/184654974](http://b/184654974)
-
-Zephyr's Cmake system will try to attach itself to the west tool if it finds it
-installed, conflicting with manual cmake invocations. If you installed west,
-you'll need to remove it:
-
-```bash
-python3 -m pip uninstall west
-```
-
-
-### Install zmake
-
-You can install zmake with pip:
-
-```bash
-cd ~/chromiumos/src/platform/ec
-python3 -m pip install -e zephyr/zmake --user
-```
-
-Ensure that ~/.local/bin in on your PATH
-
-You may also need to install these items:
-
-```bash
-sudo apt-get install cmake ninja-build python3-pyelftools gcc-multilib \
-    python3-pykwalify python3-colorama python3-testfixtures
-```
-
-You must reinstall zmake after any `repo sync` since new features may have been
-added that are needed by the build.
-
-
-### Install binman
-
-First build pylibfdt:
-
-```bash
-cd somewhere
-sudo apt-get install flex bison swig
-git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git
-cd dtc
-make
-make install PREFIX=~/.local         # You can install this where it suits
-```
-
-If you have a Chromium OS checkout then you should do:
-
-```bash
-cd ~/.local/bin
-ln -s ~/chromiumos/src/third_party/u-boot/files/tools/binman/binman
-```
-
-otherwise:
-
-```bash
-cd somewhere
-git clone https://source.denx.de/u-boot/u-boot.git
-cd ~/.local/bin
-ln -s somewhere/u-boot/tools/binman/binman
-```
-
-As above, ensure that `~/.local/bin` in on your PATH
-
-
-### Building
-
-You can use `zmake help` to obtain help on how to use zmake. The following is
-a rough guide.
-
-First configure the build with the project you want:
-
-```bash
-# Use -t zephyr when running outside chroot
-
-zmake configure -B /tmp/z/vol zephyr/projects/volteer/volteer/ -t zephyr
-```
-
-If you are building for posix-ec, change the default toolchain to host to make
-it use the native system one instead of llvm. Make sure to start with a clean
-build directory if zmake returns any build error:
-
-```bash
-zmake configure -B /tmp/posix zephyr/projects/posix-ec -t host
-```
-
-Then build with just the target directory:
-
-```
-zmake build /tmp/z/vol
-```
-
-The output is in that directory:
-
-*   `output/zephyr.bin` - output binary (read-only and read-write packed
-    together)
-*   `output/zephyr.ro.elf` - read-only ELF for debugging
-*   `output/zephyr.rw.elf` - read-write ELF for debugging
-
-You might also find these files useful (using read-only as an example):
-
-*   `build-ro/zephyr/.config` - Kconfig options selected
-*   `build-ro/zephyr/include/generated/devicetree_unfixed.h` - the (large)
-    header file that zephyr uses to provide devicetree information to the C code
-*   `build-ro/zephyr/zephyr.dts` - devicetree that is used
-*   `build-ro/zephyr/zephyr.dts` - map of image
-
-
-### Looking at the Kconfig
-
-It should be possible to do this with:
-
-```bash
-ninja -C /tmp/z/vol/build-ro menuconfig
-```
-
-However at present this does not work [b/184662866](http://b/184662866).
diff --git a/docs/zephyr_init.md b/docs/zephyr_init.md
deleted file mode 100644
index 8822736efb..0000000000
--- a/docs/zephyr_init.md
+++ /dev/null
@@ -1,53 +0,0 @@
-# Zephyr OS-based EC Initialization Order
-
-Zephyr provides Z_INIT_ENTRY_DEFINE() & the extend macro to install the initial
-function. The initialize flow for different levels would be like the following
-(not very detailed):
-*   architecture-specific initialization
-*   `PRE_KERNEL_1` level
-*   `PRE_KERNEL_2` level
-*   `POST_KERNEL` level
-*   `APPLICATION` level
-*   main()
-
-The kernel and driver initial functions separate into specific initialize
-levels. It couldn't put all initial functions in main() for the Zephyr OS-based
-EC. It is also hard to maintain those initial priority which separates into
-different files.
-
-This file defines some Zephyr OS-based EC initial priorities which have critical
-sequence requirement for initializing:
-
-## PRE_KERNEL_1
-*   Priority (0-9) - Reserved for system testability:
-
-    The highest priority could be used in zephyr. Don't use it when system
-    development. Buffer it for the following system development & testing.
-
-*   Priority (10-19) - Chip level system pre-initialization:
-
-    These priorities in this range are used for critical chip initialization,
-    including determining the reset cause and initializing the battery-backed
-    RAM driver. Most chip drivers should only be initialized after
-    `PLATFORM_EC_SYSTEM_PRE_INIT`.
-
-*   Priority (20) - PLATFORM_EC_SYSTEM_PRE_INIT:
-
-    At this initialization priority, the CROS system checks the reset cause and
-    initializing the system reset flags. Any chip level drivers related to
-    determining the reset type must be at a higher priority.
-
-*   TODO
-
-## PRE_KERNEL_2
-*   TODO
-
-## POST_KERNEL
-*   TODO
-
-## APPLICATION
-*   TODO
-
-## main()
-*   TODO
-*   Start the tasks.
diff --git a/docs/zephyr_poc_device_bringup.md b/docs/zephyr_poc_device_bringup.md
deleted file mode 100644
index 394aa4a05b..0000000000
--- a/docs/zephyr_poc_device_bringup.md
+++ /dev/null
@@ -1,52 +0,0 @@
-# Zephyr Proof-of-Concept-Device Bringup
-
-It may be useful to build a Zephyr OS-based EC for a device which
-already has a CrOS EC device build, for the purposes of demonstrating
-the feasibility of Zephyr OS.
-
-This document is a work-in-progress list of tricks & tools that may be
-useful to you.
-
-## Initial Bringup
-
-Initially, you'll want to get a basic UART functioning with nothing
-but a shell and some basic console commands.
-
-An example CL to do this for Lazor can be found
-[here](https://crrev.com/c/2749765).
-
-## Bringing up GPIOs
-
-After you have UART functioning, GPIOs can be an easy target to start
-unblocking further features.
-
-We have a very ugly program to auto-generate the GPIO DTS based on
-gpio.inc for the existing board.  You can find it at
-`util/gpios_to_zephyr_dts.c`, and instructions are in the file on how
-to compile and use it.  You may have to hand-modify the output.
-
-The resultant CL for Lazor can be found [here](https://crrev.com/c/2749768).
-
-## Bring up Host Commands
-
-Set `CONFIG_PLATFORM_EC_HOSTCMD=y` and enable the appropriate
-host-command interface for your platform (e.g., eSPI).
-
-An example CL for Lazor can be found [here](https://crrev.com/c/2749428).
-
-As long as you get this compiling that should be enough to move to the
-next step.  Further testing of the host command layer will require
-power sequencing up and going.
-
-## Enabling some simple GPIO-based buttons and switches
-
-Next, you can:
-
-* [Add the lid switch](https://crrev.com/c/2749768)
-* [Add the power button](https://crrev.com/c/2749426)
-* [Add AC presence detection](https://crrev.com/c/2749428)
-
-## Power Sequencing
-
-TODO(jrosenth): add steps on enabling power sequencing and expand this
-document.
diff --git a/docs/zephyr_shim.md b/docs/zephyr_shim.md
deleted file mode 100644
index fac0383aff..0000000000
--- a/docs/zephyr_shim.md
+++ /dev/null
@@ -1,381 +0,0 @@
-[TOC]
-
-# Zephyr Shimming How-To
-
-## Objective
-
-Allow a subset of the platform/ec code to be built as part of the Zephyr-based
-EC without needing to land code into upstream zephyr, or our zephyr-chrome
-repository.
-
-## Background
-
-Now that Google has joined [Zephyr OS](https://www.zephyrproject.org/), the EC
-team is moving toward it instead of platform/ec code on embedded controllers for
-future Chrome OS devices. See the
-[originally proposed idea](https://goto.google.com/cros-ec-rtos) and a more
-specific [Zephyr process doc](https://goto.google.com/zephyr-structure) of what
-future development on Zephyr will look like.
-
-Simply put, we want to move to Zephyr OS to use an open-source embedded OS that
-has a vibrant community. The embedded OS scene for the industry is very
-fragmented, with various parties using their own custom solution. We see the
-strong open-source community at Zephyr as potentially helping to consolidate
-efforts in the embedded controller space. It will also benefit our partners
-(both chip vendors and OEMs) since they should only have to support one embedded
-OS (i.e., Zephyr) for both their Chrome OS and Windows based devices.
-
-Migrating to use Zephyr fully is going to take a few years. We do not want to
-diverge from the active development happening on platform/ec code. We
-potentially want to ship a product using Zephyr before the migration is
-complete.
-
-## Design ideas
-
-In order to reuse `platform/ec` development , we shim "active" `platform/ec`
-code as a
-[Zephyr Module](https://docs.zephyrproject.org/latest/guides/modules.html). This
-requires us to add some Zephyr specific code in a `zephyr` directory in the
-`platform/ec` codebase. Once we release a Zephyr-based EC, then we can turn down
-platform/ec for future development and work on migrating the platform/ec-module
-code out of the module directory and into a first-class Zephyr code format -- in
-the local
-[Chrome Zephyr repo](https://chromium.googlesource.com/chromiumos/platform/zephyr-chrome/+/HEAD)
-and ultimately [upstream](https://github.com/zephyrproject-rtos/zephyr).
-
-For platform/ec code that is stable and not under active development, the Zephyr
-team may port that code to Zephyr, thus skipping the shimming process.
-
-### Subsystems of interest
-
-#### With Shim
-
-We shim the following subsystems (non-exhaustive).
-
-*   USB-C: TCPC, PPC, MUX, TCPMv2
-*   Charge Manager
-*   SoC Power Sequencing
-*   Sensors, if Intel’s HID-based solution is delayed in getting to Zephyr
-    upstream
-
-#### Little-to-No Shim
-
-We adopt upstream Zephyr or skip the shimming process (non-exhaustive).
-
-*   CBI and dependent EEPROM code
-    *   The format is stable. We pull in the list of CBI tags from platform/ec
-        though
-*   EFS2, Vboot, RO/RW split
-    *   Adjusting flash layout would be difficult to shim, and the concept is
-        very stable.
-    *   We may shim some core EFS2 logic
-*   Host command framework
-*   Sensors, if Intel’s HID-based solution getts to Zephyr upstream and passes
-    CTS
-*   Keyboard and keycode scanning support
-    *   We may shim the newer Vivaldi feature.
-*   Console support
-    *   We allow individual console commands via DECLARE\_CONSOLE\_COMMAND to be
-        shimmed to Zephyr. These convert commands to work with Zephyr's shell
-        subsystem.
-*   I2C
-
-### New content in platform/ec
-
-Add the `src/platform/ec/zephyr` folder with:
-
-*   [Module integration files](https://docs.zephyrproject.org/latest/guides/modules.html#build-system-integration),
-    e.g., module.yml, CMakeLists.txt, and KConfig.
-    *   **module.yml** is the required entry point (must be located at
-        _zephyr/module.yml_ in the repository) for Zephyr modules, and declares
-        the location of Kconfig and CMakeLists.txt files used by the Zephyr
-        build system.
-    *   **CMakeLists.txt** replicates build logic for the files being shimmed,
-        outside of the platform/ec Makefile.
-    *   **Kconfig** will declare any CONFIG\_\* options which are important to
-        expose from platform/ec code to the Zephyr build.
-*   Shim code to translate platform/ec code into Zephyr code
-    *   For example, redefine platform/ec’s
-        [`DECLARE_HOST_COMMAND`](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/HEAD:src/platform/ec/include/host_command.h;l=256;drc=514923bc59f5a3435dbb7cbf348735ed41889ffe)
-        to map to Zephyr's upstream
-        [`EC_HOST_CMD_HANDLER`](https://github.com/zephyrproject-rtos/zephyr/blob/d7468bf836b75c29980441f294a61eae6bf4bc75/include/ec_host_cmd.h#L73)
-        macro. This allows us to compile select platform/ec files in the Zephyr
-        build.
-
-### Namespace Collisions
-
-One significant issue of mixing Zephyr headers with our existing EC code is that
-we currently have many names colliding with the Zephyr code. For example,
-Zephyr's atomic functions also are named `atomic_add`, `atomic_or`, ...,
-however, have a different API from our EC's atomic functions. This is critical,
-since atomic operations are often used in `static inline` functions placed in
-header files.
-
-In some cases, we are able to hack around these collisions by creating macros
-and functions which are compatible with both Zephyr and our EC's usages. For
-example, we can create a modified `IS_ENABLED` which accepts both defined to
-nothing usages (CrOS EC `config.h` style), and defined to `1` usages (Zephyr
-Kconfig style).
-
-However, long term, we may find this to be a continual cause of issues, and
-creating hacks for every colliding macro or function may be unsustainable. We
-propose _gradually_ introducing a namespace prefix to the `platform/ec`
-codebase, for example `crec_`. We can begin at the critical areas of namespace
-collision (e.g., atomics) and continue to improve the naming convention with
-time.
-
-### New CQ check
-
-As long as code from platform/ec is part of the zephyr
-[ebuild](http://cs/chromeos_public/src/third_party/chromiumos-overlay/chromeos-base/chromeos-zephyr-2_3/chromeos-zephyr-2_3-9999.ebuild),
-then we need to run the Zephyr CQ checks on any platform/ec CLs in addition to
-the normal platform/ec CQ checks. This ensures that platform/ec changes aren’t
-breaking the Zephyr builds and requiring the Zephyr team to debug recent
-changes.
-
-For local builds, we can run `emerge-betty chromeos-zephyr-2_3` or `zmake`
-utility to check that an EC CL has not broken anything on the Zephyr side.
-
-We will work with the CI team to enable this.
-
-## How to shim features
-
-Before you get started shimming a feature, it's important to
-understand the general philosophies behind Zephyr OS and shimming:
-
-* Our current EC's OS isn't going away any time soon. Even after we
-  ship our first device with a Zephyr-based EC, we may still be working on
-  other projects using the old OS.  It's important to consider how
-  your feature will apply to both the Zephyr world and CrOS EC OS
-  world.
-
-* We won't be converting old devices to use Zephyr-based firmware.
-  This means that our existing OS and its code will need maintained
-  for bug and security fixes for years to come.  **Do not allow the
-  code you write for the CrOS EC OS to lack in quality or be "throw
-  away code" as it will need to be maintained for a long time.**
-
-* Shimming, by the very nature of the design, will lead to some ugly
-  hacks.  We try and avoid this when we can, but some of them may be
-  completely unavoidable.  This means we need to actively work against
-  nature to keep the code clean.  If we do things right, there's even
-  a possibility that we leave things cleaner than we found them.
-
-* Shimming occasionally digs up landmines.  Be prepared to step on
-  them. 💣
-
-### What code can be shimmed?
-
-Code in the `common/` directory (and other common code directories,
-like `power/`) is the ideal target for shimming, with the exception of
-core OS features which have Zephyr OS equivalents.
-
-Code in the following directories should **never be shimmed**:
-
-- `core/`: this directory contains architecture-specific code which
-  should have a Zephyr OS equivalent feature.
-
-- `chip/`: this directory contains chip-specific code, and similarly
-  should have a Zephyr OS equivalent feature.
-
-In both cases, you should instead determine (or, in rare cases,
-implement upstream) the equivalent Zephyr OS feature, and *implement
-an architecture and chip agnostic* "shim layer" in the `zephyr/shim/`
-directory which translates the APIs as necessary.
-
-As of the time of this document, the shim layer is nearing 100%
-complete, and it should be rare that you encounter an API which needs
-translation.
-
-Finally, code in the following directories should **avoid being
-shimmed, if possible**:
-
-- `board/`: this directory contains variant-specific code.
-
-- `baseboard/`: this directory contains baseboard-specific code.
-
-In both cases, the only value in shimming in code from one of those
-directories would be to enable a Zephyr OS build for a device which
-already has CrOS EC OS support, as *Zephyr-only projects will not have
-these directories*.  You should be thinking about how this would be
-implemented for a Zephyr-only project, and filing bugs to create the
-appropriate device-tree and Kconfig equivalents before shimming this
-code.
-
-See [Zephyr PoC device bringup](zephyr_poc_device_bringup.md) for more
-information about bringing up proof-of-concept devices.
-
-### Configuration
-
-CrOS EC OS uses a special header `config.h`, which sets configuration
-defaults, and includes board and chip specific configurations by
-expecting the headers `board.h` and `config_chip.h` to be present.
-Most of these configuration options start with `CONFIG_`, however the
-rules were loosely defined over the years.
-
-Zephyr OS, on the other hand, uses two different configuration
-systems:
-
-* Kconfig, the configuration system from the Linux Kernel, which
-  fits well within the domain of preprocessor definitions in C.  The
-  schema for our Kconfig files can be found under `zephyr/Kconfig`,
-  and project-specific configurations are made in `prj.conf` files.
-
-  Kconfig is generally used to select which EC software features are
-  enabled, and should be avoided for hardware configurations, such as
-  chip configuration registers and their default settings.
-
-* Open Firmware Device Tree, which you may also be familiar with from
-  the Linux kernel.  This configuration can be found in `*.dts` files.
-
-  Device-tree is generally used for hardware configurations, and
-  should be avoided for EC software feature configuration.
-
-For code which is shimmed, we need to play nicely with both the CrOS
-EC OS configuration system, and Zephyr's configuration systems.  Thus,
-we follow the following pattern:
-
-* EC software features are configured using `Kconfig` and
-  `zephyr/shim/include/config_chip.h` translates them into the
-  appropriate CrOS EC OS configurations using patterns such as below:
-
-  ```c
-  #undef CONFIG_CMD_GETTIME
-  #ifdef CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME
-  #define CONFIG_CMD_GETTIME
-  #endif
-  ```
-
-  The preprocessor code should follow that template exactly, and not
-  use any nesting (Kconfig handles dependencies, there is no reason to
-  do it again in the preprocessor code).
-
-* **The domain of Kconfig options and CrOS EC configuration names
-  should be completely distinct.**  This is because the Kconfig options
-  are included automatically, and including `config.h` may undefine
-  them.  To mitigate this, we follow a convention of using
-  `CONFIG_PLATFORM_EC_` as the prefix for EC software features in
-  Kconfig.
-
-One special configuration option exists, `CONFIG_ZEPHYR`, which you
-can use to detect whether the OS is Zephyr OS.  This is the
-conventional way to add Zephyr-specific (or excluded) code in CrOS EC
-code.
-
-The typical EC macros for reducing `#ifdef` messes (e.g.,
-`IS_ENABLED`, `STATIC_IF`, etc.) work with both CrOS EC OS and Kconfig
-options, and should be used when possible.
-
-### Header Files
-
-Besides the include paths provided by Zephyr OS, the following paths
-are additionally added for shimmed code:
-
-* `include/`
-* `zephyr/include/`
-* `zephyr/shim/include/`
-
-The names of headers in these directories should be completely
-distinct.  C compilers have no mechanism for "include ordering", and
-there is no way to "override a header".
-
-If you feel the need to "override" a header, say `foo.h` in
-`include/`, the best way to do this is to give it a different name
-under `zephyr/shim/include` (e.g., `zephyr_foo_shim.h`), and include
-that in the `foo.h` header with a `#ifdef CONFIG_ZEPHYR` guard.
-
-The typical styling convention for includes (following existing
-conventions in `platform/ec` and other C codebases we have) is:
-
-* Zephyr OS headers in pointy brackets, in alphabetical order.
-
-* One blank line
-
-* CrOS EC OS headers (either from `include/`, `zephyr/shim/include/`,
-  or the current directory), in quotes (not pointy brackets).
-
-### Adding files to Cmake
-
-Zephyr's build system (including shimmed code) uses CMake instead of
-`Makefiles`, and your code will not be compiled for Zephyr unless you
-list the files in `zephyr/CMakeLists.txt`.
-
-### Step-by-step guide to adding a Kconfig
-
-Follow these steps:
-
-1. Make sure you have read the above Configuration section
-
-2. Add your config to one of zephyr/Kconfig* files. Note the PLATFORM_EC_ prefix
-   and try to put it near related things:
-
-  ```kconfig
-   config PLATFORM_EC_CHARGER_BQ25720
-     bool "TI BQ25720 charger"
-     help
-       The TI BQ25720 is a blah blah (describe summary from datasheet,
-       at least 3 lines so take 10 minutes to write something truly useful)
-  ```
-
-   Consider a `depends on PLATFORM_EC_...` line if it depends on an existing
-   feature.
-
-3. Add to zephyr/shim/include/config_chip.h (put it at the bottom):
-
-  ```kconfig
-   #undef CONFIG_CHARGER_BQ25720
-   #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720
-   #define CONFIG_CHARGER_BQ25720
-   #endif
-  ```
-
-4. Add the source file to zephyr/CMakeLists.txt if it is not already there. For
-   ordering check the comments in that file:
-
-   `zephyr_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25720
-                                     "${PLATFORM_EC}/driver/charger/bq25720.c")`
-
-5. Run a build on a board that enables the new CONFIG (in config.h) to make sure
-   there are no problems.
-
-6. If it doesn't work, please email zephyr-task-force@ or file a bug and assign
-   it to sjg@, cc zephyr-task-force@ (please include CL link and the error
-   output).
-
-### Unit Tests
-
-Unit tests, implemented using the Ztest framework, can be found in
-`zephyr/test`.
-
-To run all unit tests, you use `zmake testall`.
-
-## Alternatives Considered
-
-### Translate code and mirror into the zephyr-chrome repository
-
-We could potentially write a script which, via a series of find/replace
-operations, translates a platform/ec module to use Zephyr functions, macros, and
-paradigms. On a frequent basis, we would translate all modules of interest in
-the platform/ec repository and land an "uprev" change in the zephyr-chrome
-repository.
-
-The main disadvantage of this technique is that we can't get any CQ coverage
-when platform/ec CLs land that the modules will continue to work in Zephyr.
-Additionally, the translator script would be delicate and probably require
-frequent maintenance.
-
-However, this technique does have some benefits. With modules directly
-translated to code in the Zephyr paradigm, the process of upstreaming a shimmed
-module to ZephyrOS would be significantly easier. Additionally, it would require
-no shim code in platform/ec.
-
-### Don't do any code sharing
-
-One option is to avoid shimming in any platform/ec code and allow the Zephyr
-team to re-implement features in upstream zephyr, or our local zephyr-chrome
-repository.
-
-Disregarding the infeasible amount of work required to complete this option, the
-platform/ec repository has a far faster development pace as there are many more
-contributors, and the Zephyr features would quickly lose parity during the time
-frame that we are launching both Zephyr-based and platform/ec-based devices.
diff --git a/docs/ztest.md b/docs/ztest.md
deleted file mode 100644
index 021b3391bd..0000000000
--- a/docs/ztest.md
+++ /dev/null
@@ -1,200 +0,0 @@
-# Porting EC unit tests to Ztest
-
-[TOC]
-
-This HOWTO shows the process for porting the EC's `base32` unit test to Zephyr's
-Ztest framework. All of the work is done in `src/platform/ec`.
-
-See
-[Test Framework - Zephyr Project Documentation](https://docs.zephyrproject.org/1.12.0/subsystems/test/ztest.html#quick-start-unit-testing)
-for details about Zephyr's Ztest framework.
-
-For examples of porting an EC unit test to the Ztest API, see: *
-[base32](https://crrev.com/c/2492527) and
-[improvements](https://crrev.com/c/2634401) *
-[accel_cal](https://crrev.com/c/2645198)
-
-## Porting Considerations
-
-Not every EC unit test can be ported to Ztest. This section describes cases that
-are not supported and cases where caveats apply.
-
-### EC Mocks Are Not Supported
-
-If a test has a `$TEST.mocklist` file associated with the unit test, it is using
-the EC mocking framework, which is unsupported in the Ztest framework. Ztest has
-its own mocking framework which the EC does not support.
-
-### Multiple Task Caveats
-
-The EC unit test framework starts a single task to call `run_test`, and this
-task will then call the functions for the various test cases. Some unit tests
-have multiple threads of execution, which is enabled by a `$TEST.tasklist` file
-associated with the unit test. The test runner task has a task ID of
-`TASK_ID_TEST_RUNNER`, which can be used as an argument to any of the task
-functions. See for example the
-[`charge_ramp` unit test](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/test/charge_ramp.c#81)
-and the
-[`host_command` unit test](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/test/host_command.c#32)
-
-When a unit test is ported to Ztest, `test_main` doesn't have a thread ID, so
-`TASK_ID_TEST_RUNNER` is undefined. `charge_ramp` and `host_command` cannot be
-ported at this time. `test_main` also cannot call any of the task functions that
-must be called from a task, such as `task_wake`; these functions can pend the
-calling task, but since `test_main` doesn't have a thread ID, the pend will
-fail. See the
-[`mutex` unit test](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/test/mutex.c#116)
-for an example.
-
-## Determine source files being tested
-
-Determine which C files the unit test requires by finding the test in
-`test/test_config.h`:
-
-```
-#ifdef TEST_BASE32
-#define CONFIG_BASE32
-#endif
-```
-
-Locate the `CONFIG` item(s) in `common/build.mk`:
-
-```
-common-$(CONFIG_BASE32)+=base32.o
-```
-
-So for the `base32` test, we only need to shim `common/base32.c`.
-
-Add the C files to `zephyr/shim/CMakeLists.txt`, in the "Shimmed modules"
-section:
-
-```
-# Shimmed modules
-zephyr_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c")
-```
-
-Refer to [zephyr: shim in base32.c](https://crrev.com/c/2468631).
-
-## Create test directory
-
-Create a new directory for the unit test in `zephyr/test/base32`.
-
-Create `zephyr/test/base32/prj.conf` with these contents:
-
-```
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-```
-
-Create `zephyr/test/base32/CMakeLists.txt` with these contents:
-
-```
-target_sources(app PRIVATE ${PLATFORM_EC}/test/base32.c)
-```
-
-## Modify test source code
-
-### Test cases
-
-In the unit test, replace `run_test` with `TEST_MAIN()`. This will allow both
-platform/ec tests and Ztests to share the same entry point.
-
-Change `RUN_TEST` to `ztest_unit_test` and add the `ztest_test_suite` wrapper
-plus the call to `ztest_run_test_suite`.
-
-```c
-/*
- * Define the test cases to run. We need to do this twice, once in the format
- * that Ztest uses, and again in the format the the EC test framework uses.
- * If you add a test to one of them, make sure to add it to the other.
- */
-TEST_MAIN()
-{
-    ztest_test_suite(test_base32_lib,
-                     ztest_unit_test(test_crc5),
-                     ztest_unit_test(test_encode),
-                     ztest_unit_test(test_decode));
-    ztest_run_test_suite(test_base32_lib);
-}
-```
-
-Each function that is called by `ztest_unit_test` needs to be declared using
-`DECLARE_EC_TEST`. Keep the `return EC_SUCCESS;` at the end of the test
-function. Note that for the EC build, `TEST_MAIN` will call `test_reset` before
-running the test cases, and `test_print_result` after.
-
-### Assert macros
-
-Change the `TEST_ASSERT` macros to `zassert` macros. There are plans to automate
-this process, but for now, it's a manual process involving some intelligent
-find-and-replace.
-
-*   `TEST_ASSERT(n)` to `zassert_true(n, NULL)`
-*   `TEST_EQ(a, b, fmt)` to `zassert_equal(a, b, fmt ## ", " ## fmt, a, b)`
-    *   e.g. `TEST_EQ(a, b, "%d")` becomes `zassert_equal(a, b, "%d, %d", a, b)`
-*   `TEST_NE(a, b, fmt)` to `zassert_not_equal(a, b, fmt ## ", " ## fmt, a, b)`
-*   `TEST_LT(a, b, fmt)` to `zassert_true(a < b, fmt ## ", " ## fmt, a, b)`
-*   `TEST_LE(a, b, fmt)` to `zassert_true(a <= b, fmt ## ", " ## fmt, a, b)`
-*   `TEST_GT(a, b, fmt)` to `zassert_true(a > b, fmt ## ", " ## fmt, a, b)`
-*   `TEST_GE(a, b, fmt)` tp `zassert_true(a >= b, fmt ## ", " ## fmt, a, b)`
-*   `TEST_BITS_SET(a, bits)` to `zassert_true(a & (int)bits == (int)bits, "%u,
-    %u", a & (int)bits, (int)bits)`
-*   `TEST_BITS_CLEARED(a, bits)` to `zassert_true(a & (int)bits == 0, "%u, 0", a
-    & (int)bits)`
-*   `TEST_ASSERT_ARRAY_EQ(s, d, n)` to `zassert_mem_equal(s, d, b, NULL)`
-*   `TEST_CHECK(n)` to `zassert_true(n, NULL)`
-*   `TEST_NEAR(a, b, epsilon, fmt)` to `zassert_within(a, b, epsilon, fmt, a)`
-    *   Currently, every usage of `TEST_NEAR` involves floating point values
-*   `TEST_ASSERT_ABS_LESS(n, t)` to `zassert_true(abs(n) < t, "%d, %d", n, t)`
-    *   Currently, every usage of `TEST_ASSERT_ANS_LESS` involves signed
-        integers.
-
-There isn't a good replacement for `TEST_ASSERT_MEMSET(d, c, n)`, but it is only
-used in two tests, `printf.c` and `utils.c`. If you need this test, you'll need
-to code up a loop over the `n` bytes starting at `d`, and `zassert_equal` that
-each byte is equal to `c`.
-
-Also note that some tests use constructs like `TEST_ASSERT(var == const)`, which
-would have been better write as `TEST_EQ(var, const)`. These should be rewritten
-to use `zassert_equal`.
-
-Refer to
-[test: Allow EC unit test to use Ztest API](https://crrev.com/c/2492527) for the
-changes to the base32.c source code.
-
-### Tasklist
-
-For any test that has a corresponding `${TESTNAME}.tasklist`, add the file
-`shimmed_test_tasks.h` in the zephyr test directory, and in that file,
-`#include` the tasklist file. See [accel_cal](https://crrev.com/c/2645198) for
-an example.
-
-Add `CONFIG_HAS_TEST_TASKS=y` to the `prj.conf` file, as well as the appropriate
-`CONFIG_PLATFORM_EC` defines to include or exclude code that the unit under test
-uses.
-
-## Build and run
-
-Use `zmake` to build and run the test:
-
-```
-(cr) $ zmake -l DEBUG configure --test -B build/ztest/base32 zephyr/test/base32
-...
-UART_0 connected to pseudotty: /dev/pts/1
-*** Booting Zephyr OS build zephyr-v2.4.0-1-g63b2330a85cd  ***
-Running test suite test_base32_lib
-===================================================================
-START - test_crc5
- PASS - test_crc5
-===================================================================
-START - test_encode
- PASS - test_encode
-===================================================================
-START - test_decode
- PASS - test_decode
-===================================================================
-Test suite test_base32_lib succeeded
-===================================================================
-PROJECT EXECUTION SUCCESSFUL
-(cr) $
-```
diff --git a/driver/accel_bma2x2.c b/driver/accel_bma2x2.c
deleted file mode 100644
index 6d2d596bea..0000000000
--- a/driver/accel_bma2x2.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Bosch Accelerometer driver for Chrome EC
- *
- * Supported: BMA255
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "accel_bma2x2.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "spi.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-/* Number of times to attempt to enable sensor before giving up. */
-#define SENSOR_ENABLE_ATTEMPTS 5
-
-/**
- * Read register from accelerometer.
- */
-static inline int raw_read8(const int port, const uint16_t i2c_addr_flags,
-			    const int reg, int *data_ptr)
-{
-	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
-}
-
-/**
- * Write register from accelerometer.
- */
-static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
-			     const int reg, int data)
-{
-	return i2c_write8(port, i2c_addr_flags, reg, data);
-}
-
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int ret,  range_val, reg_val, range_reg_val;
-
-	/* Range has to be between 2G-16G */
-	if (range < 2)
-		range = 2;
-	else if (range > 16)
-		range = 16;
-
-	range_val = BMA2x2_RANGE_TO_REG(range);
-	if ((BMA2x2_REG_TO_RANGE(range_val) < range) && rnd)
-		range_val = BMA2x2_RANGE_TO_REG(range * 2);
-
-	mutex_lock(s->mutex);
-
-	/* Determine the new value of control reg and attempt to write it. */
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_RANGE_SELECT_ADDR, &range_reg_val);
-	if (ret != EC_SUCCESS) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-	reg_val = (range_reg_val & ~BMA2x2_RANGE_SELECT_MSK) | range_val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 BMA2x2_RANGE_SELECT_ADDR, reg_val);
-
-	/* If successfully written, then save the range. */
-	if (ret == EC_SUCCESS)
-		s->current_range = BMA2x2_REG_TO_RANGE(range_val);
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	return BMA2x2_RESOLUTION;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
-{
-	int ret, odr_val, odr_reg_val, reg_val;
-	struct accelgyro_saved_data_t *data = s->drv_data;
-
-	/* Rate has to be between 7.8125Hz - 1000Hz */
-	if (rate < 7813) {
-		rate = 7812;
-		odr_val = BMA2x2_BW_7_81HZ;
-	} else if (rate > 1000000) {
-		rate = 1000000;
-		odr_val = BMA2x2_BW_1000HZ;
-	} else {
-		odr_val = BMA2x2_BW_TO_REG(rate);
-		if ((BMA2x2_REG_TO_BW(odr_val) < rate) && rnd)
-			odr_val = BMA2x2_BW_TO_REG(rate * 2);
-	}
-
-	mutex_lock(s->mutex);
-
-	/* Determine the new value of control reg and attempt to write it. */
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_BW_SELECT_ADDR, &odr_reg_val);
-	if (ret != EC_SUCCESS) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-	reg_val = (odr_reg_val & ~BMA2x2_BW_MSK) | odr_val;
-	/* Set output data rate. */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 BMA2x2_BW_SELECT_ADDR, reg_val);
-
-	/* If successfully written, then save the new data rate. */
-	if (ret == EC_SUCCESS)
-		data->odr = BMA2x2_REG_TO_BW(odr_val);
-
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = s->drv_data;
-
-	return data->odr;
-}
-
-static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
-		      int16_t temp)
-{
-	int i, ret;
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	/* temperature is ignored */
-	/* Offset from host is in 1/1024g, 1/128g internally. */
-	for (i = X; i <= Z; i++) {
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 BMA2x2_OFFSET_X_AXIS_ADDR + i, v[i] / 8);
-		if (ret)
-			return ret;
-	}
-	return EC_SUCCESS;
-}
-
-static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		      int16_t *temp)
-{
-	int i, val, ret;
-	intv3_t v;
-
-	for (i = X; i <= Z; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				BMA2x2_OFFSET_X_AXIS_ADDR + i, &val);
-		if (ret)
-			return ret;
-		v[i] = (int8_t)val * 8;
-	}
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t acc[6];
-	int ret, i;
-
-	/* Read 6 bytes starting at X_AXIS_LSB. */
-	mutex_lock(s->mutex);
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     BMA2x2_X_AXIS_LSB_ADDR, acc, 6);
-	mutex_unlock(s->mutex);
-
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Convert acceleration to a signed 16-bit number. Note, based on
-	 * the order of the registers:
-	 *
-	 * acc[0] = X_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[1] = X_AXIS_MSB
-	 * acc[2] = Y_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[3] = Y_AXIS_MSB
-	 * acc[4] = Z_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[5] = Z_AXIS_MSB
-	 */
-	for (i = X; i <= Z; i++)
-		v[i] = (((int8_t)acc[i * 2 + 1]) << 8) | (acc[i * 2] & 0xf0);
-	rotate(v, *s->rot_standard_ref, v);
-
-	return EC_SUCCESS;
-}
-
-static int perform_calib(struct motion_sensor_t *s, int enable)
-{
-	int ret, val, status, rate, range, i;
-	timestamp_t deadline;
-
-	if (!enable)
-		return EC_SUCCESS;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_OFFSET_CTRL_ADDR, &val);
-	if (ret)
-		return ret;
-	if (!(val & BMA2x2_OFFSET_CAL_READY))
-		return EC_ERROR_ACCESS_DENIED;
-
-	rate = get_data_rate(s);
-	range = s->current_range;
-	/*
-	 * Temporary set frequency to 100Hz to get enough data in a short
-	 * period of time.
-	 */
-	set_data_rate(s, 100000, 0);
-	set_range(s, 2, 0);
-
-	/* We assume the device is laying flat for calibration */
-	if (s->rot_standard_ref == NULL ||
-	    (*s->rot_standard_ref)[2][2] > INT_TO_FP(0))
-		val = BMA2x2_OFC_TARGET_PLUS_1G;
-	else
-		val = BMA2x2_OFC_TARGET_MINUS_1G;
-	val = ((BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(X)) |
-	       (BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(Y)) |
-	       (val << BMA2x2_OFC_TARGET_AXIS(Z)));
-	raw_write8(s->port, s->i2c_spi_addr_flags,
-		   BMA2x2_OFC_SETTING_ADDR, val);
-
-	for (i = X; i <= Z; i++) {
-		val = (i + 1) << BMA2x2_OFFSET_TRIGGER_OFF;
-		raw_write8(s->port, s->i2c_spi_addr_flags,
-			   BMA2x2_OFFSET_CTRL_ADDR, val);
-		/*
-		 * The sensor needs 16 samples. At 100Hz/10ms, it needs 160ms to
-		 * complete. Set 400ms to have some margin.
-		 */
-		deadline.val = get_time().val + 400 * MSEC;
-		do {
-			if (timestamp_expired(deadline, NULL)) {
-				ret = EC_RES_TIMEOUT;
-				goto end_perform_calib;
-			}
-			msleep(50);
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					BMA2x2_OFFSET_CTRL_ADDR, &status);
-			if (ret != EC_SUCCESS)
-				goto end_perform_calib;
-		} while ((status & BMA2x2_OFFSET_CAL_READY) == 0);
-	}
-
-end_perform_calib:
-	set_range(s, range, 0);
-	set_data_rate(s, rate, 0);
-	return ret;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tries = 0, val, reg, reset_field;
-
-	/* This driver requires a mutex */
-	ASSERT(s->mutex);
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_CHIP_ID_ADDR, &val);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	if (val != BMA255_CHIP_ID_MAJOR)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Reset the chip to be in a good state */
-	reg = BMA2x2_RST_ADDR;
-	reset_field = BMA2x2_CMD_SOFT_RESET;
-
-	mutex_lock(s->mutex);
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-	if (ret != EC_SUCCESS) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-	val |= reset_field;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, val);
-	if (ret != EC_SUCCESS) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-
-	/* The SRST will be cleared when reset is complete. */
-	do {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-
-		/* Reset complete. */
-		if ((ret == EC_SUCCESS) && !(val & reset_field))
-			break;
-
-		/* Check for tires. */
-		if (tries++ > SENSOR_ENABLE_ATTEMPTS) {
-			ret = EC_ERROR_TIMEOUT;
-			mutex_unlock(s->mutex);
-			return ret;
-		}
-		msleep(1);
-	} while (1);
-	mutex_unlock(s->mutex);
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv bma2x2_accel_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-	.perform_calib = perform_calib,
-};
diff --git a/driver/accel_bma422.h b/driver/accel_bma422.h
deleted file mode 100644
index 0ab580235c..0000000000
--- a/driver/accel_bma422.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMA422 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_BMA422_H
-#define __CROS_EC_ACCEL_BMA422_H
-
-#include "accel_bma4xx.h"
-
-/* Chip ID of BMA422 */
-#define BMA422_CHIP_ID			0x12
-
-#endif /* __CROS_EC_ACCEL_BMA422_H */
diff --git a/driver/accel_bma4xx.c b/driver/accel_bma4xx.c
deleted file mode 100644
index e9502c20b4..0000000000
--- a/driver/accel_bma4xx.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Bosch Accelerometer driver for Chrome EC
- *
- * Supported: BMA422
- */
-
-#include "accelgyro.h"
-#include "accel_bma422.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "spi.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-/**
- * Read 8bit register from accelerometer.
- */
-static inline int bma4_read8(const struct motion_sensor_t *s, const int reg,
-			     int *data_ptr)
-{
-	return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data_ptr);
-}
-
-/**
- * Write 8bit register from accelerometer.
- */
-static inline int bma4_write8(const struct motion_sensor_t *s, const int reg,
-			      int data)
-{
-	int ret;
-
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data);
-
-	/*
-	 * From Bosch: BMA needs a delay of 450us after each write if it
-	 * is in suspend mode, otherwise the operation may be ignored by
-	 * the sensor. Given we are only doing write during init, add
-	 * the delay unconditionally.
-	 */
-	usleep(450);
-
-	return ret;
-}
-
-/*
- * Set specific bit set to certain value of a 8-bit reg.
- */
-static inline int bma4_set_reg8(const struct motion_sensor_t *s, int reg,
-				uint8_t bits, int mask)
-{
-	int val;
-
-	RETURN_ERROR(bma4_read8(s, reg, &val));
-
-	val = (val & ~mask) | bits;
-
-	return bma4_write8(s, reg, val);
-}
-
-static int write_accel_offset(const struct motion_sensor_t *s, intv3_t v)
-{
-	int i, val;
-
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	for (i = X; i <= Z; i++) {
-		val = round_divide((int64_t)v[i] * BMA4_OFFSET_ACC_DIV_MG,
-				   BMA4_OFFSET_ACC_MULTI_MG);
-		if (val > 127)
-			val = 127;
-		if (val < -128)
-			val = -128;
-		if (val < 0)
-			val += 256;
-
-		RETURN_ERROR(bma4_write8(s, BMA4_OFFSET_0_ADDR + i, val));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int set_foc_config(struct motion_sensor_t *s)
-{
-	/* Disabling offset compensation */
-	RETURN_ERROR(bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
-				   (BMA4_DISABLE << BMA4_NV_ACCEL_OFFSET_POS),
-				   BMA4_NV_ACCEL_OFFSET_MSK));
-
-	/* Set accelerometer configurations to 50Hz,CIC, continuous mode */
-	RETURN_ERROR(bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR,
-				 BMA4_FOC_ACC_CONF_VAL));
-
-
-	/* Set accelerometer to normal mode by enabling it */
-	RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR,
-				   (BMA4_ENABLE <<  BMA4_ACCEL_ENABLE_POS),
-				   BMA4_ACCEL_ENABLE_MSK));
-
-	/* Disable advance power save mode */
-	RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CONF_ADDR,
-				   (BMA4_DISABLE
-				    << BMA4_ADVANCE_POWER_SAVE_POS),
-				   BMA4_ADVANCE_POWER_SAVE_MSK));
-
-	return EC_SUCCESS;
-}
-
-static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v)
-{
-	int i;
-
-	/* Retry 5 times */
-	uint8_t reg_data[6] = {0}, try_cnt = 5;
-
-	/* Check if data is ready */
-	while (try_cnt && (!(reg_data[0] & BMA4_STAT_DATA_RDY_ACCEL_MSK))) {
-		/* 20ms delay for 50Hz ODR */
-		msleep(20);
-
-		/* Read the status register */
-		RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
-					    BMA4_STATUS_ADDR, reg_data, 1));
-
-		try_cnt--;
-	}
-
-	if (!(reg_data[0] & 0x80))
-		return EC_ERROR_TIMEOUT;
-
-	/* Read the sensor data */
-	RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
-				    BMA4_DATA_8_ADDR, reg_data, 6));
-
-	for (i = X; i <= Z; i++) {
-		v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8)
-		       | (reg_data[i * 2] & 0xf0);
-
-		/* Since the resolution is only 12 bits*/
-		v[i] = (v[i] / 0x10);
-	}
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	return EC_SUCCESS;
-}
-
-static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
-				int sens_range)
-{
-	intv3_t accel_data, offset;
-
-	/* Structure to store accelerometer data temporarily */
-	int32_t delta_value[3] = {0, 0, 0};
-
-	/* Variable to define count */
-	uint8_t i, loop, sample_count = 0;
-
-	for (loop = 0; loop < BMA4_FOC_SAMPLE_LIMIT; loop++) {
-		RETURN_ERROR(wait_and_read_data(s, accel_data));
-
-		sample_count++;
-
-		/* Store the data in a temporary structure */
-		delta_value[0] += accel_data[0] - target[X];
-		delta_value[1] += accel_data[1] - target[Y];
-		delta_value[2] += accel_data[2] - target[Z];
-	}
-
-	/*
-	 * The data is in LSB so -> [(LSB)*1000*range/2^11*-1]
-	 * (unit of offset:mg)
-	 */
-	for (i = X; i <= Z; ++i) {
-		offset[i] = ((((delta_value[i] * 1000 * sens_range)
-			     / sample_count) / 2048) * -1);
-	}
-
-	RETURN_ERROR(write_accel_offset(s, offset));
-
-	/* Enable the offsets and backup to NVM */
-	RETURN_ERROR(bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
-				   (BMA4_ENABLE << BMA4_NV_ACCEL_OFFSET_POS),
-				   BMA4_NV_ACCEL_OFFSET_MSK));
-
-	return EC_SUCCESS;
-}
-
-static int perform_calib(struct motion_sensor_t *s, int enable)
-{
-	uint8_t config[2];
-	int pwr_ctrl, pwr_conf;
-	intv3_t target = {0, 0, 0};
-	int sens_range = s->current_range;
-
-	if (!enable)
-		return EC_SUCCESS;
-
-	/* Read accelerometer configurations */
-	RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMA4_ACCEL_CONFIG_ADDR, config, 2));
-
-	/* Get accelerometer enable status to be saved */
-	RETURN_ERROR(bma4_read8(s, BMA4_POWER_CTRL_ADDR, &pwr_ctrl));
-
-	/* Get advance power save mode to be saved */
-	RETURN_ERROR(bma4_read8(s, BMA4_POWER_CONF_ADDR, &pwr_conf));
-
-	/* Perform calibration */
-	RETURN_ERROR(set_foc_config(s));
-
-	/* We calibrate considering Z axis is laid flat on the surface */
-	target[Z] = BMA4_ACC_DATA_PLUS_1G(sens_range);
-
-	RETURN_ERROR(perform_accel_foc(s, target, sens_range));
-
-	/* Set the saved sensor configuration */
-	RETURN_ERROR(i2c_write_block(s->port, s->i2c_spi_addr_flags,
-			BMA4_ACCEL_CONFIG_ADDR, config, 2));
-
-	RETURN_ERROR(bma4_write8(s, BMA4_POWER_CTRL_ADDR, pwr_ctrl));
-
-	RETURN_ERROR(bma4_write8(s, BMA4_POWER_CONF_ADDR, pwr_conf));
-
-	return EC_SUCCESS;
-}
-
-static int set_range(struct motion_sensor_t *s, int range, int round)
-{
-	int ret,  range_reg_val;
-
-	range_reg_val = BMA4_RANGE_TO_REG(range);
-
-	/*
-	 * If rounding flag is set then set the range_val to nearest
-	 * valid value.
-	 */
-	if ((BMA4_REG_TO_RANGE(range_reg_val) < range) && round)
-		range_reg_val = BMA4_RANGE_TO_REG(range * 2);
-
-	mutex_lock(s->mutex);
-
-	/* Determine the new value of control reg and attempt to write it. */
-	ret = bma4_set_reg8(s, BMA4_ACCEL_RANGE_ADDR,
-			    range_reg_val << BMA4_ACCEL_RANGE_POS,
-			    BMA4_ACCEL_RANGE_MSK);
-
-	/* If successfully written, then save the range. */
-	if (ret == EC_SUCCESS)
-		s->current_range = BMA4_REG_TO_RANGE(range_reg_val);
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	return BMA4_12_BIT_RESOLUTION;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int round)
-{
-	int ret, odr_reg_val;
-	struct accelgyro_saved_data_t *data = s->drv_data;
-
-	odr_reg_val = BMA4_ODR_TO_REG(rate);
-
-	if ((BMA4_REG_TO_ODR(odr_reg_val) < rate) && round)
-		odr_reg_val = BMA4_ODR_TO_REG(rate * 2);
-
-	mutex_lock(s->mutex);
-
-	/* Determine the new value of control reg and attempt to write it. */
-	ret = bma4_set_reg8(s, BMA4_ACCEL_CONFIG_ADDR,
-			    odr_reg_val << BMA4_ACCEL_ODR_POS,
-			    BMA4_ACCEL_ODR_MSK);
-
-	/* If successfully written, then save the new data rate. */
-	if (ret == EC_SUCCESS)
-		data->odr = BMA4_REG_TO_ODR(odr_reg_val);
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = s->drv_data;
-
-	return data->odr;
-}
-
-static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
-		      int16_t temp)
-{
-	int ret;
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-
-	mutex_lock(s->mutex);
-
-	ret = write_accel_offset(s, v);
-
-	if (ret == EC_SUCCESS) {
-		/* Enable the offsets and backup to NVM */
-		ret = bma4_set_reg8(s, BMA4_NV_CONFIG_ADDR,
-				    (BMA4_ENABLE << BMA4_NV_ACCEL_OFFSET_POS),
-				    BMA4_NV_ACCEL_OFFSET_MSK);
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		      int16_t *temp)
-{
-	int i, val, ret;
-	intv3_t v;
-
-	mutex_lock(s->mutex);
-
-	for (i = X; i <= Z; i++) {
-		ret = bma4_read8(s, BMA4_OFFSET_0_ADDR + i, &val);
-		if (ret) {
-			mutex_unlock(s->mutex);
-			return ret;
-		}
-
-		if (val > 0x7f)
-			val -= -256;
-
-		v[i] = round_divide((int64_t)val * BMA4_OFFSET_ACC_MULTI_MG,
-				    BMA4_OFFSET_ACC_DIV_MG);
-	}
-
-	mutex_unlock(s->mutex);
-
-	/* Offset is in milli-g */
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-
-	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t acc[6];
-	int ret, i;
-
-	mutex_lock(s->mutex);
-
-	/* Read 6 bytes starting at X_AXIS_LSB. */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     BMA4_DATA_8_ADDR, acc, 6);
-
-	mutex_unlock(s->mutex);
-
-	if (ret)
-		return ret;
-
-	/*
-	 * Convert acceleration to a signed 16-bit number. Note, based on
-	 * the order of the registers:
-	 *
-	 * acc[0] = X_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[1] = X_AXIS_MSB
-	 * acc[2] = Y_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[3] = Y_AXIS_MSB
-	 * acc[4] = Z_AXIS_LSB -> bit 7~4 for value, bit 0 for new data bit
-	 * acc[5] = Z_AXIS_MSB
-	 */
-	for (i = X; i <= Z; i++)
-		v[i] = (((int8_t)acc[i * 2 + 1]) << 8) | (acc[i * 2] & 0xf0);
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, reg_val;
-
-	/* This driver requires a mutex. Assert if mutex is not supplied. */
-	ASSERT(s->mutex);
-
-	/* Read accelerometer's CHID ID */
-	RETURN_ERROR(bma4_read8(s, BMA4_CHIP_ID_ADDR, &reg_val));
-
-	if (s->chip != MOTIONSENSE_CHIP_BMA422 || reg_val != BMA422_CHIP_ID)
-		return EC_ERROR_HW_INTERNAL;
-
-	mutex_lock(s->mutex);
-
-	/* Enable accelerometer */
-	ret = bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR,
-			    BMA4_ENABLE << BMA4_ACCEL_ENABLE_POS,
-			    BMA4_ACCEL_ENABLE_MSK);
-
-	mutex_unlock(s->mutex);
-
-	if (ret)
-		return ret;
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv bma4_accel_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-	.perform_calib = perform_calib,
-};
diff --git a/driver/accel_bma4xx.h b/driver/accel_bma4xx.h
deleted file mode 100644
index 13c9da4a92..0000000000
--- a/driver/accel_bma4xx.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMA4XX gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_BMA4XX_H
-#define __CROS_EC_ACCEL_BMA4XX_H
-
-#define BMA4_I2C_ADDR_PRIMARY			0x18
-#define BMA4_I2C_ADDR_SECONDARY			0x19
-#define BMA4_I2C_BMM150_ADDR			0x10
-
-/* Chip-specific registers */
-#define BMA4_CHIP_ID_ADDR			0x00
-#define BMA4_CHIP_ID_MIN			0x10
-#define BMA4_CHIP_ID_MAX			0x15
-
-#define BMA4_ERROR_ADDR				0x02
-#define BMA4_FATAL_ERR_MSK			0x01
-#define BMA4_CMD_ERR_POS			1
-#define BMA4_CMD_ERR_MSK			0x02
-#define BMA4_ERR_CODE_POS			2
-#define BMA4_ERR_CODE_MSK			0x1C
-#define BMA4_FIFO_ERR_POS			6
-#define BMA4_FIFO_ERR_MSK			0x40
-#define BMA4_AUX_ERR_POS			7
-#define BMA4_AUX_ERR_MSK			0x80
-
-#define BMA4_STATUS_ADDR			0x03
-#define BMA4_STAT_DATA_RDY_ACCEL_POS		7
-#define BMA4_STAT_DATA_RDY_ACCEL_MSK		0x80
-
-#define BMA4_DATA_0_ADDR			0x0A
-#define BMA4_DATA_8_ADDR			0x12
-
-#define BMA4_SENSORTIME_0_ADDR			0x18
-#define BMA4_INT_STAT_0_ADDR			0x1C
-#define BMA4_INT_STAT_1_ADDR			0x1D
-#define BMA4_STEP_CNT_OUT_0_ADDR		0x1E
-#define BMA4_HIGH_G_OUT_ADDR			0x1F
-#define BMA4_TEMPERATURE_ADDR			0x22
-
-#define BMA4_FIFO_LENGTH_0_ADDR			0x24
-#define BMA4_FIFO_DATA_ADDR			0x26
-#define BMA4_ACTIVITY_OUT_ADDR			0x27
-#define BMA4_ORIENTATION_OUT_ADDR		0x28
-
-#define BMA4_INTERNAL_STAT			0x2A
-#define BMA4_ASIC_INITIALIZED			0x01
-
-#define BMA4_ACCEL_CONFIG_ADDR			0x40
-#define BMA4_ACCEL_ODR_POS			0
-#define BMA4_ACCEL_ODR_MSK			0x0F
-#define BMA4_ACCEL_BW_POS			4
-#define BMA4_ACCEL_BW_MSK			0x70
-#define BMA4_ACCEL_PERFMODE_POS			7
-#define BMA4_ACCEL_PERFMODE_MSK			0x80
-#define BMA4_OUTPUT_DATA_RATE_0_78HZ		0x01
-#define BMA4_OUTPUT_DATA_RATE_1_56HZ		0x02
-#define BMA4_OUTPUT_DATA_RATE_3_12HZ		0x03
-#define BMA4_OUTPUT_DATA_RATE_6_25HZ		0x04
-#define BMA4_OUTPUT_DATA_RATE_12_5HZ		0x05
-#define BMA4_OUTPUT_DATA_RATE_25HZ		0x06
-#define BMA4_OUTPUT_DATA_RATE_50HZ		0x07
-#define BMA4_OUTPUT_DATA_RATE_100HZ		0x08
-#define BMA4_OUTPUT_DATA_RATE_200HZ		0x09
-#define BMA4_OUTPUT_DATA_RATE_400HZ		0x0A
-#define BMA4_OUTPUT_DATA_RATE_800HZ		0x0B
-#define BMA4_OUTPUT_DATA_RATE_1600HZ		0x0C
-#define BMA4_ACCEL_OSR4_AVG1			0
-#define BMA4_ACCEL_OSR2_AVG2			1
-#define BMA4_ACCEL_NORMAL_AVG4			2
-#define BMA4_ACCEL_CIC_AVG8			3
-#define BMA4_ACCEL_RES_AVG16			4
-#define BMA4_ACCEL_RES_AVG32			5
-#define BMA4_ACCEL_RES_AVG64			6
-#define BMA4_ACCEL_RES_AVG128			7
-#define BMA4_CIC_AVG_MODE			0
-#define BMA4_CONTINUOUS_MODE			1
-
-#define BMA4_ACCEL_RANGE_ADDR			0x41
-#define BMA4_ACCEL_RANGE_POS			0
-#define BMA4_ACCEL_RANGE_MSK			0x03
-#define BMA4_ACCEL_RANGE_2G			0
-#define BMA4_ACCEL_RANGE_4G			1
-#define BMA4_ACCEL_RANGE_8G			2
-#define BMA4_ACCEL_RANGE_16G			3
-
-#define BMA4_RESERVED_REG_5B_ADDR		0x5B
-#define BMA4_RESERVED_REG_5C_ADDR		0x5C
-#define BMA4_FEATURE_CONFIG_ADDR		0x5E
-#define BMA4_INTERNAL_ERROR			0x5F
-#define BMA4_IF_CONFIG_ADDR			0x6B
-#define BMA4_FOC_ACC_CONF_VAL			0xB7
-
-#define BMA4_NV_CONFIG_ADDR			0x70
-#define BMA4_NV_ACCEL_OFFSET_POS		3
-#define BMA4_NV_ACCEL_OFFSET_MSK		0x08
-
-#define BMA4_OFFSET_0_ADDR			0x71
-#define BMA4_OFFSET_1_ADDR			0x72
-#define BMA4_OFFSET_2_ADDR			0x73
-
-#define BMA4_POWER_CONF_ADDR			0x7C
-#define BMA4_ADVANCE_POWER_SAVE_POS		0
-#define BMA4_ADVANCE_POWER_SAVE_MSK		0x01
-
-#define BMA4_POWER_CTRL_ADDR			0x7D
-#define BMA4_ACCEL_ENABLE_POS			2
-#define BMA4_ACCEL_ENABLE_MSK			0x04
-#define BMA4_ENABLE				0x01
-#define BMA4_DISABLE				0x00
-
-#define BMA4_CMD_ADDR				0x7E
-#define BMA4_NVM_PROG				0xA0
-#define BMA4_FIFO_FLUSH				0xB0
-#define BMA4_SOFT_RESET				0xB6
-
-/* Other definitions */
-#define BMA4_X_AXIS				0
-#define BMA4_Y_AXIS				1
-#define BMA4_Z_AXIS				2
-
-#define BMA4_12_BIT_RESOLUTION			12
-#define BMA4_14_BIT_RESOLUTION			14
-#define BMA4_16_BIT_RESOLUTION			16
-
-/*
- * The max positive value of accel data is 0x07FF, equal to range(g)
- * So, in order to get +1g, divide the 0x07FF by range
- */
-#define BMA4_ACC_DATA_PLUS_1G(range)		(0x07FF / (range))
-
-/* For offset registers 1LSB - 3.9mg */
-#define BMA4_OFFSET_ACC_MULTI_MG		(3900 * 1000)
-#define BMA4_OFFSET_ACC_DIV_MG			1000000
-
-#define BMA4_FOC_SAMPLE_LIMIT			32
-
-/* Min and Max sampling frequency in mHz */
-#define BMA4_ACCEL_MIN_FREQ	12500
-#define BMA4_ACCEL_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
-
-#define BMA4_RANGE_TO_REG(_range) \
-	((_range) < 8 ? BMA4_ACCEL_RANGE_2G + ((_range) / 4) : \
-			BMA4_ACCEL_RANGE_8G + ((_range) / 16))
-
-#define BMA4_REG_TO_RANGE(_reg) \
-	((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg) * 2 : \
-					8 + ((_reg) - BMA4_ACCEL_RANGE_8G) * 8)
-
-#define BMA4_ODR_TO_REG(_odr) \
-	((_odr) < 125000 ? \
-	 BMA4_OUTPUT_DATA_RATE_0_78HZ + __fls(((_odr) * 10) / 7800) : \
-	 BMA4_OUTPUT_DATA_RATE_25HZ + __fls((_odr) / 25000))
-
-#define  BMA4_REG_TO_ODR(_reg) \
-	((_reg) < BMA4_OUTPUT_DATA_RATE_25HZ ? \
-	 (7800 << ((_reg) - BMA4_OUTPUT_DATA_RATE_0_78HZ)) / 10 : \
-	 25000 << ((_reg) - BMA4_OUTPUT_DATA_RATE_25HZ))
-
-extern const struct accelgyro_drv bma4_accel_drv;
-
-#endif /* __CROS_EC_ACCEL_BMA4XX_H */
diff --git a/driver/accel_kionix.c b/driver/accel_kionix.c
deleted file mode 100644
index 69f0ca9073..0000000000
--- a/driver/accel_kionix.c
+++ /dev/null
@@ -1,693 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Kionix Accelerometer driver for Chrome EC
- *
- * Supported: KX022, KXCJ9
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "accel_kionix.h"
-#include "accel_kx022.h"
-#include "accel_kxcj9.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_orientation.h"
-#include "spi.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-/* Number of times to attempt to enable sensor before giving up. */
-#define SENSOR_ENABLE_ATTEMPTS 3
-
-#if !defined(CONFIG_ACCEL_KXCJ9) && !defined(CONFIG_ACCEL_KX022)
-#error "Must use either KXCJ9 or KX022"
-#endif
-
-#if defined(CONFIG_ACCEL_KXCJ9) && !defined(CONFIG_ACCEL_KX022)
-#define V(s_) 1
-#elif defined(CONFIG_ACCEL_KX022) && !defined(CONFIG_ACCEL_KXCJ9)
-#define V(s_) 0
-#else
-#define V(s_) ((s_)->chip == MOTIONSENSE_CHIP_KXCJ9)
-#endif
-/* Index for which table to use. */
-#if !defined(CONFIG_ACCEL_KXCJ9) || !defined(CONFIG_ACCEL_KX022)
-#define T(s_) 0
-#else
-#define T(s_) V(s_)
-#endif /* !defined(CONFIG_ACCEL_KXCJ9) || !defined(CONFIG_ACCEL_KX022) */
-
-STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR) int check_orientation_locked(
-					const struct motion_sensor_t *s);
-
-/* List of range values in +/-G's and their associated register values. */
-static const struct accel_param_pair ranges[][3] = {
-#ifdef CONFIG_ACCEL_KX022
-	{ {2, KX022_GSEL_2G},
-	  {4, KX022_GSEL_4G},
-	  {8, KX022_GSEL_8G} },
-#endif /* defined(CONFIG_ACCEL_KX022) */
-#ifdef CONFIG_ACCEL_KXCJ9
-	{ {2, KXCJ9_GSEL_2G},
-	  {4, KXCJ9_GSEL_4G},
-	  {8, KXCJ9_GSEL_8G_14BIT} },
-#endif /* defined(CONFIG_ACCEL_KXCJ9) */
-};
-
-/* List of resolution values in bits and their associated register values. */
-static const struct accel_param_pair resolutions[][2] = {
-#ifdef CONFIG_ACCEL_KX022
-	{ {8,  KX022_RES_8BIT},
-	  {16, KX022_RES_16BIT} },
-#endif /* defined(CONFIG_ACCEL_KX022) */
-#ifdef CONFIG_ACCEL_KXCJ9
-	{ {8,  KXCJ9_RES_8BIT},
-	  {12, KXCJ9_RES_12BIT} },
-#endif /* defined(CONFIG_ACCEL_KXCJ9) */
-};
-
-/* List of ODR values in mHz and their associated register values. */
-static const struct accel_param_pair datarates[][13] = {
-#ifdef CONFIG_ACCEL_KX022
-	/* One duplicate because table sizes must match. */
-	{ {781,     KX022_OSA_0_781HZ},
-	  {781,     KX022_OSA_0_781HZ},
-	  {1563,    KX022_OSA_1_563HZ},
-	  {3125,    KX022_OSA_3_125HZ},
-	  {6250,    KX022_OSA_6_250HZ},
-	  {12500,   KX022_OSA_12_50HZ},
-	  {25000,   KX022_OSA_25_00HZ},
-	  {50000,   KX022_OSA_50_00HZ},
-	  {100000,  KX022_OSA_100_0HZ},
-	  {200000,  KX022_OSA_200_0HZ},
-	  {400000,  KX022_OSA_400_0HZ},
-	  {800000,  KX022_OSA_800_0HZ},
-	  {1600000, KX022_OSA_1600HZ} },
-#endif /* defined(CONFIG_ACCEL_KX022) */
-#ifdef CONFIG_ACCEL_KXCJ9
-	{ {0,       KXCJ9_OSA_0_000HZ},
-	  {781,     KXCJ9_OSA_0_781HZ},
-	  {1563,    KXCJ9_OSA_1_563HZ},
-	  {3125,    KXCJ9_OSA_3_125HZ},
-	  {6250,    KXCJ9_OSA_6_250HZ},
-	  {12500,   KXCJ9_OSA_12_50HZ},
-	  {25000,   KXCJ9_OSA_25_00HZ},
-	  {50000,   KXCJ9_OSA_50_00HZ},
-	  {100000,  KXCJ9_OSA_100_0HZ},
-	  {200000,  KXCJ9_OSA_200_0HZ},
-	  {400000,  KXCJ9_OSA_400_0HZ},
-	  {800000,  KXCJ9_OSA_800_0HZ},
-	  {1600000, KXCJ9_OSA_1600_HZ} },
-#endif /* defined(CONFIG_ACCEL_KXCJ9) */
-};
-
-/**
- * Find index into a accel_param_pair that matches the given engineering value
- * passed in. The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid index. If the request is
- * outside the range of values, it returns the closest valid index.
- */
-static int find_param_index(const int eng_val, const int round_up,
-			    const struct accel_param_pair *pairs,
-			    const int size)
-{
-	int i;
-
-	/* Linear search for index to match. */
-	for (i = 0; i < size - 1; i++) {
-		if (eng_val <= pairs[i].val)
-			return i;
-
-		if (eng_val < pairs[i+1].val) {
-			if (round_up)
-				return i + 1;
-			else
-				return i;
-		}
-	}
-
-	return i;
-}
-
-/**
- * Read register from accelerometer.
- */
-static int raw_read8(const int port,
-		     const uint16_t i2c_spi_addr_flags,
-		     const int reg, int *data_ptr)
-{
-	int rv = EC_ERROR_INVAL;
-
-	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		uint8_t val;
-		uint8_t cmd = 0x80 | reg;
-
-		rv = spi_transaction(
-			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
-			&cmd, 1, &val, 1);
-		if (rv == EC_SUCCESS)
-			*data_ptr = val;
-
-#endif
-	} else {
-		rv = i2c_read8(port, i2c_spi_addr_flags,
-			       reg, data_ptr);
-	}
-	return rv;
-}
-
-/**
- * Write register from accelerometer.
- */
-static int raw_write8(const int port,
-		      const uint16_t i2c_spi_addr_flags,
-		      const int reg, int data)
-{
-	int rv = EC_ERROR_INVAL;
-
-	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		uint8_t cmd[2] = { reg, data };
-
-		rv = spi_transaction(
-			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
-			cmd, 2, NULL, 0);
-#endif
-	} else {
-		rv = i2c_write8(port, i2c_spi_addr_flags,
-				reg, data);
-	}
-	return rv;
-}
-
-static int raw_read_multi(const int port,
-			  const uint16_t i2c_spi_addr_flags,
-			  uint8_t reg, uint8_t *rxdata, int rxlen)
-{
-	int rv = EC_ERROR_INVAL;
-
-	if (ACCEL_ADDR_IS_SPI(i2c_spi_addr_flags)) {
-#ifdef CONFIG_SPI_ACCEL_PORT
-		reg |= 0x80;
-		rv = spi_transaction(
-			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
-			&reg, 1, rxdata, rxlen);
-#endif
-	} else {
-		rv = i2c_read_block(port, i2c_spi_addr_flags,
-				    reg, rxdata, rxlen);
-	}
-	return rv;
-}
-
-/**
- * Disable sensor by taking it out of operating mode. When disabled, the
- * acceleration data does not change.
- *
- * Note: This is intended to be called in a pair with enable_sensor().
- *
- * @param s Pointer to motion sensor data
- * @param reg_val Pointer to location to store control register after disabling
- *
- * @return EC_SUCCESS if successful, EC_ERROR_* otherwise
- */
-static int disable_sensor(const struct motion_sensor_t *s, int *reg_val)
-{
-	int i, ret, reg, pc1_field;
-
-	reg = KIONIX_CTRL1_REG(V(s));
-	pc1_field = KIONIX_PC1_FIELD(V(s));
-
-	/*
-	 * Read the current state of the control register
-	 * so that we can restore it later.
-	 */
-	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, reg_val);
-		if (ret != EC_SUCCESS)
-			continue;
-
-		*reg_val &= ~pc1_field;
-
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, *reg_val);
-		if (ret == EC_SUCCESS)
-			return EC_SUCCESS;
-	}
-	return ret;
-}
-
-/**
- * Enable sensor by placing it in operating mode.
- *
- * Note: This is intended to be called in a pair with disable_sensor().
- *
- * @param s Pointer to motion sensor data
- * @param reg_val Value of the control register to write to sensor
- *
- * @return EC_SUCCESS if successful, EC_ERROR_* otherwise
- */
-static int enable_sensor(const struct motion_sensor_t *s, int reg_val)
-{
-	int i, ret, reg, pc1_field;
-
-	reg = KIONIX_CTRL1_REG(V(s));
-	pc1_field = KIONIX_PC1_FIELD(V(s));
-
-	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, &reg_val);
-		if (ret != EC_SUCCESS)
-			continue;
-
-		/* Enable tilt orientation mode  if lid sensor */
-		if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
-		    (s->location == MOTIONSENSE_LOC_LID) &&
-		    (V(s) == 0))
-			reg_val |= KX022_CNTL1_TPE;
-
-		/* Enable accelerometer based on reg_val value. */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, reg_val | pc1_field);
-
-		/* On first success, we are done. */
-		if (ret == EC_SUCCESS)
-			break;
-	}
-	return ret;
-}
-
-/**
- * Set a register value.
- *
- * @param s Pointer to motion sensor data
- * @param reg     Register to write to
- * @param reg_val Value of the control register to write to sensor
- * @param field   Bitfield to modify.
- *
- * @return EC_SUCCESS if successful, EC_ERROR_* otherwise
- */
-static int set_value(const struct motion_sensor_t *s, int reg, int val,
-		     int field)
-{
-	int ret, reg_val_new, reg_val;
-
-	/* Disable the sensor to allow for changing of critical parameters. */
-	mutex_lock(s->mutex);
-	ret = disable_sensor(s, &reg_val);
-	if (ret != EC_SUCCESS) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-
-	/* Determine new value of control reg and attempt to write it. */
-	reg_val_new = (reg_val & ~field) | val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 reg, reg_val_new);
-
-	/* If successfully written, then save the range. */
-	if (ret == EC_SUCCESS)
-		/* Re-enable the sensor. */
-		ret = enable_sensor(s, reg_val_new);
-
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int ret, index, reg, range_field, range_val;
-
-	/* Find index for interface pair matching the specified range. */
-	index = find_param_index(range, rnd, ranges[T(s)],
-				 ARRAY_SIZE(ranges[T(s)]));
-	range_field = KIONIX_RANGE_FIELD(V(s));
-	reg = KIONIX_CTRL1_REG(V(s));
-	range_val = ranges[T(s)][index].reg;
-
-	ret = set_value(s, reg, range_val, range_field);
-	if (ret == EC_SUCCESS)
-		s->current_range = ranges[T(s)][index].val;
-	return ret;
-}
-
-static int set_resolution(const struct motion_sensor_t *s, int res, int rnd)
-{
-	int ret, index, reg, res_field, res_val;
-	struct kionix_accel_data *data = s->drv_data;
-
-	/* Find index for interface pair matching the specified resolution. */
-	index = find_param_index(res, rnd, resolutions[T(s)],
-				 ARRAY_SIZE(resolutions[T(s)]));
-	res_val = resolutions[T(s)][index].reg;
-	res_field = KIONIX_RES_FIELD(V(s));
-	reg = KIONIX_CTRL1_REG(V(s));
-
-	ret = set_value(s, reg, res_val, res_field);
-	if (ret == EC_SUCCESS)
-		data->sensor_resolution = resolutions[T(s)][index].val;
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	struct kionix_accel_data *data = s->drv_data;
-
-	return data->sensor_resolution;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
-{
-	int ret, index, reg, odr_field, odr_val;
-	struct kionix_accel_data *data = s->drv_data;
-
-	/* Find index for interface pair matching the specified rate. */
-	index = find_param_index(rate, rnd, datarates[T(s)],
-				 ARRAY_SIZE(datarates[T(s)]));
-	odr_val = datarates[T(s)][index].reg;
-	reg = KIONIX_ODR_REG(V(s));
-	odr_field = KIONIX_ODR_FIELD(V(s));
-
-	ret = set_value(s, reg, odr_val, odr_field);
-	if (ret == EC_SUCCESS)
-		data->base.odr =  datarates[T(s)][index].val;
-	return ret;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct kionix_accel_data *data = s->drv_data;
-
-	return data->base.odr;
-}
-
-static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
-		      int16_t temp)
-{
-	/* temperature is ignored */
-	struct kionix_accel_data *data = s->drv_data;
-	data->offset[X] = offset[X];
-	data->offset[Y] = offset[Y];
-	data->offset[Z] = offset[Z];
-	return EC_SUCCESS;
-}
-
-static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		      int16_t *temp)
-{
-	struct kionix_accel_data *data = s->drv_data;
-	offset[X] = data->offset[X];
-	offset[Y] = data->offset[Y];
-	offset[Z] = data->offset[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static __maybe_unused enum motionsensor_orientation kx022_convert_orientation(
-		const struct motion_sensor_t *s,
-		int orientation)
-{
-	enum motionsensor_orientation res = MOTIONSENSE_ORIENTATION_UNKNOWN;
-
-	switch (orientation) {
-	case KX022_ORIENT_PORTRAIT:
-		res = MOTIONSENSE_ORIENTATION_PORTRAIT;
-		break;
-	case KX022_ORIENT_INVERT_PORTRAIT:
-		res = MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT;
-		break;
-	case KX022_ORIENT_LANDSCAPE:
-		res = MOTIONSENSE_ORIENTATION_LANDSCAPE;
-		break;
-	case KX022_ORIENT_INVERT_LANDSCAPE:
-		res = MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE;
-		break;
-	default:
-		break;
-	}
-	res = motion_orientation_remap(s, res);
-	return res;
-}
-
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
-static int check_orientation_locked(const struct motion_sensor_t *s)
-{
-	struct kionix_accel_data *data = s->drv_data;
-	int orientation, raw_orientation;
-	int ret;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			KX022_TSCP, &raw_orientation);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* mask off up and down events, we don't care about those */
-	raw_orientation &= KX022_ORIENT_MASK;
-	if (raw_orientation && (raw_orientation != data->raw_orientation)) {
-		data->raw_orientation = raw_orientation;
-		orientation = kx022_convert_orientation(s, raw_orientation);
-		*motion_orientation_ptr(s) = orientation;
-	}
-	return ret;
-}
-
-bool motion_orientation_changed(const struct motion_sensor_t *s)
-{
-	return ((struct kionix_accel_data *)s->drv_data)->orientation !=
-		((struct kionix_accel_data *)s->drv_data)->last_orientation;
-}
-
-enum motionsensor_orientation *motion_orientation_ptr(
-		const struct motion_sensor_t *s)
-{
-	return &((struct kionix_accel_data *)s->drv_data)->orientation;
-}
-
-void motion_orientation_update(const struct motion_sensor_t *s)
-{
-	((struct kionix_accel_data *)s->drv_data)->last_orientation =
-		((struct kionix_accel_data *)s->drv_data)->orientation;
-}
-
-#endif
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t acc[6];
-	uint8_t reg;
-	int ret, i, resolution;
-	struct kionix_accel_data *data = s->drv_data;
-
-	/* Read 6 bytes starting at XOUT_L. */
-	reg = KIONIX_XOUT_L(V(s));
-	mutex_lock(s->mutex);
-	ret = raw_read_multi(s->port, s->i2c_spi_addr_flags, reg, acc, 6);
-	if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
-	    (s->location == MOTIONSENSE_LOC_LID) &&
-	    (V(s) == 0) &&
-	    (ret == EC_SUCCESS))
-		ret = check_orientation_locked(s);
-	mutex_unlock(s->mutex);
-
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Convert acceleration to a signed 16-bit number. Note, based on
-	 * the order of the registers:
-	 *
-	 * acc[0] = XOUT_L
-	 * acc[1] = XOUT_H
-	 * acc[2] = YOUT_L
-	 * acc[3] = YOUT_H
-	 * acc[4] = ZOUT_L
-	 * acc[5] = ZOUT_H
-	 *
-	 * Add calibration offset before returning the data.
-	 */
-	resolution = get_resolution(s);
-	for (i = X; i <= Z; i++) {
-		if (V(s)) {
-			v[i] = (((int8_t)acc[i * 2 + 1]) << 4) |
-				(acc[i * 2] >> 4);
-			v[i] <<= 16 - resolution;
-		} else {
-			if (resolution == 8)
-				acc[i * 2] = 0;
-			v[i] = (((int8_t)acc[i * 2 + 1]) << 8) | acc[i * 2];
-		}
-	}
-	rotate(v, *s->rot_standard_ref, v);
-
-	/* apply offset in the device coordinates */
-	for (i = X; i <= Z; i++)
-		v[i] += (data->offset[i] << 5) / s->current_range;
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret, val, reg, reset_field;
-	uint8_t timeout;
-
-	mutex_lock(s->mutex);
-	if (V(s)) {
-		/* The chip can take up to 10ms to boot */
-		reg = KIONIX_WHO_AM_I(V(s));
-		timeout = 0;
-		do {
-			msleep(1);
-			/* Read WHO_AM_I to be sure the device has booted */
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
-			if (ret == EC_SUCCESS)
-				break;
-
-			/* Check for timeout. */
-			if (timeout++ > 20) {
-				ret = EC_ERROR_TIMEOUT;
-				break;
-			}
-		} while (1);
-	} else {
-		/* Write 0x00 to the internal register for KX022 */
-		reg = KX022_INTERNAL;
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, 0x0);
-		if (ret != EC_SUCCESS) {
-			/*
-			 * For I2C communication, if ACK was not received
-			 * from the first address, resend the command using
-			 * the second address.
-			 */
-			if (!ACCEL_ADDR_IS_SPI(s->i2c_spi_addr_flags)) {
-				const uint16_t i2c_alt_addr_flags =
-					I2C_STRIP_FLAGS(
-						s->i2c_spi_addr_flags)
-					& ~2;
-				ret = raw_write8(s->port,
-						 i2c_alt_addr_flags,
-						 reg, 0x0);
-			}
-		}
-	}
-
-	if (ret != EC_SUCCESS)
-		goto reset_failed;
-
-	/* Issue a software reset. */
-	reg = KIONIX_CTRL2_REG(V(s));
-	reset_field = KIONIX_RESET_FIELD(V(s));
-
-	if (V(s)) {
-		/* Place the sensor in standby mode to make changes. */
-		ret = disable_sensor(s, &val);
-		if (ret != EC_SUCCESS)
-			goto reset_failed;
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-		if (ret != EC_SUCCESS)
-			goto reset_failed;
-
-		val |= reset_field;
-	} else {
-		/* Write 0 to CTRL2 for KX022 */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, 0x0);
-		if (ret != EC_SUCCESS)
-			goto reset_failed;
-
-		val = reset_field;
-	}
-
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, val);
-	if (ret != EC_SUCCESS)
-		goto reset_failed;
-
-	if (V(s)) {
-		/* The SRST will be cleared when reset is complete. */
-		timeout = 0;
-		do {
-			msleep(1);
-
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
-			/* Reset complete. */
-			if ((ret == EC_SUCCESS) && !(val & reset_field))
-				break;
-			/* Check for timeout. */
-			if (timeout++ > 20) {
-				ret = EC_ERROR_TIMEOUT;
-				goto reset_failed;
-			}
-		} while (1);
-	} else {
-		/* Wait 2 milliseconds for completion of the software reset. */
-		msleep(2);
-
-		reg = KX022_COTR;
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-		if (val != KX022_COTR_VAL_DEFAULT) {
-			CPRINTF("[%s: the software reset failed]\n", s->name);
-			ret = EC_ERROR_HW_INTERNAL;
-			goto reset_failed;
-		}
-	}
-
-	reg = KIONIX_WHO_AM_I(V(s));
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-	if (ret != EC_SUCCESS || val != KIONIX_WHO_AM_I_VAL(V(s))) {
-		ret = EC_ERROR_HW_INTERNAL;
-		goto reset_failed;
-	}
-
-	mutex_unlock(s->mutex);
-
-	/* Initialize with the desired parameters. */
-	if (V(s))
-		ret = set_resolution(s, 12, 1);
-	else
-		ret = set_resolution(s, 16, 1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	return sensor_init_done(s);
-
-reset_failed:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-const struct accelgyro_drv kionix_accel_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.set_resolution = set_resolution,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-struct i2c_stress_test_dev kionix_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = KIONIX_WHO_AM_I(V(s)),
-		.read_val = KIONIX_WHO_AM_I_VAL(V(s)),
-		.write_reg = KIONIX_ODR_REG(V(s)),
-	},
-	.i2c_read = &raw_read8,
-	.i2c_write = &raw_write8,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_ACCEL */
diff --git a/driver/accel_kionix.h b/driver/accel_kionix.h
deleted file mode 100644
index 5ec83411e9..0000000000
--- a/driver/accel_kionix.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Kionix Accelerometer driver for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_KIONIX_H
-#define __CROS_EC_ACCEL_KIONIX_H
-
-#include "common.h"
-#include "accelgyro.h"
-#include "driver/accel_kx022.h"
-#include "driver/accel_kxcj9.h"
-
-/*
- * Struct for pairing an engineering value with the register value for a
- * parameter.
- */
-struct accel_param_pair {
-	int val; /* Value in engineering units. */
-	int reg; /* Corresponding register value. */
-};
-
-struct kionix_accel_data {
-	struct accelgyro_saved_data_t base;
-	/* Current resolution of accelerometer. */
-	int sensor_resolution;
-	int16_t offset[3];
-#ifdef CONFIG_KX022_ORIENTATION_SENSOR
-	int8_t raw_orientation;
-	enum motionsensor_orientation orientation;
-	enum motionsensor_orientation last_orientation;
-#endif
-};
-
-extern const struct accelgyro_drv kionix_accel_drv;
-
-/*
- * The addr field of motion_sensor support both SPI and I2C:
- *
- * +-------------------------------+---+
- * |    7 bit i2c address          | 0 |
- * +-------------------------------+---+
- * Or
- * +-------------------------------+---+
- * |    SPI device ID              | 1 |
- * +-------------------------------+---+
- */
-#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 +	\
-			     (v) * (KXCJ9_CTRL1 - KX022_CNTL1))
-#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 +	\
-			     (v) * (KXCJ9_CTRL2 - KX022_CNTL2))
-#define KIONIX_ODR_REG(v) (KX022_ODCNTL +	\
-			   (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL))
-#define KIONIX_ODR_FIELD(v) (KX022_OSA_FIELD +		\
-			     (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD))
-#define KIONIX_PC1_FIELD(v) (KX022_CNTL1_PC1 +		\
-			     (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1))
-#define KIONIX_RANGE_FIELD(v) (KX022_GSEL_FIELD +	\
-			       (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD))
-#define KIONIX_RES_FIELD(v) (KX022_RES_16BIT +		\
-			     (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT))
-#define KIONIX_RESET_FIELD(v) (KX022_CNTL2_SRST +	\
-			       (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST))
-#define KIONIX_XOUT_L(v) (KX022_XOUT_L +	\
-			  (v) * (KXCJ9_XOUT_L - KX022_XOUT_L))
-
-#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + \
-			    (v) * (KXCJ9_WHOAMI - KX022_WHOAMI))
-
-#define KIONIX_WHO_AM_I_VAL(v) (KX022_WHO_AM_I_VAL + \
-			(v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL))
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev kionix_i2c_stress_test_dev;
-#endif
-
-#endif /* __CROS_EC_ACCEL_KIONIX_H */
diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h
deleted file mode 100644
index a806568c59..0000000000
--- a/driver/accel_kx022.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* KX022 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_KX022_H
-#define __CROS_EC_ACCEL_KX022_H
-
-/*
- * 7-bit address is 001111Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define KX022_ADDR0_FLAGS	0x1e
-#define KX022_ADDR1_FLAGS	0x1f
-#define KX022_WHO_AM_I_VAL	0x14
-
-/* Chip-specific registers */
-#define KX022_XHP_L		0x00
-#define KX022_XHP_H		0x01
-#define KX022_YHP_L		0x02
-#define KX022_YHP_H		0x03
-#define KX022_ZHP_L		0x04
-#define KX022_ZHP_H		0x05
-#define KX022_XOUT_L		0x06
-#define KX022_XOUT_H		0x07
-#define KX022_YOUT_L		0x08
-#define KX022_YOUT_H		0x09
-#define KX022_ZOUT_L		0x0a
-#define KX022_ZOUT_H		0x0b
-#define KX022_COTR		0x0c
-#define KX022_COTR_VAL_COTC	0xAA
-#define KX022_COTR_VAL_DEFAULT	0x55
-#define KX022_WHOAMI		0x0f
-#define KX022_TSCP		0x10
-#define KX022_TSPP		0x11
-#define KX022_INS1		0x12
-#define KX022_INS2		0x13
-#define KX022_INS3		0x14
-#define KX022_STATUS_REG	0x15
-#define KX022_INT_REL		0x17
-#define KX022_CNTL1		0x18
-#define KX022_CNTL2		0x19
-#define KX022_CNTL3		0x1a
-#define KX022_ODCNTL		0x1b
-#define KX022_INC1		0x1c
-#define KX022_INC2		0x1d
-#define KX022_INC3		0x1e
-#define KX022_INC4		0x1f
-#define KX022_INC5		0x20
-#define KX022_INC6		0x21
-#define KX022_TILT_TIMER	0x22
-#define KX022_WUFC		0x23
-#define KX022_TDTRC		0x24
-#define KX022_TDTC		0x25
-#define KX022_TTH		0x26
-#define KX022_TTL		0x27
-#define KX022_FTD		0x28
-#define KX022_STD		0x29
-#define KX022_TLT		0x2a
-#define KX022_TWS		0x2b
-#define KX022_ATH		0x30
-#define KX022_TILT_ANGLE_LL	0x32
-#define KX022_TILT_ANGLE_HL	0x33
-#define KX022_HYST_SET		0x34
-#define KX022_LP_CNTL		0x35
-#define KX022_BUF_CNTL1	0x3a
-#define KX022_BUF_CNTL2	0x3b
-#define KX022_BUF_STATUS_1	0x3c
-#define KX022_BUF_STATUS_2	0x3d
-#define KX022_BUF_CLEAR	0x3e
-#define KX022_BUF_READ		0x3f
-#define KX022_SELF_TEST	0x60
-#define KX022_INTERNAL		0x7f
-
-
-#define KX022_CNTL1_PC1		BIT(7)
-#define KX022_CNTL1_WUFE	BIT(1)
-#define KX022_CNTL1_TPE		BIT(0)
-
-/* TSCP orientations */
-#define KX022_ORIENT_PORTRAIT		BIT(2)
-#define KX022_ORIENT_INVERT_PORTRAIT	BIT(3)
-#define KX022_ORIENT_LANDSCAPE		BIT(4)
-#define KX022_ORIENT_INVERT_LANDSCAPE	BIT(5)
-#define KX022_ORIENT_MASK		(KX022_ORIENT_PORTRAIT | \
-					 KX022_ORIENT_INVERT_PORTRAIT | \
-					 KX022_ORIENT_LANDSCAPE | \
-					 KX022_ORIENT_INVERT_LANDSCAPE)
-
-#define KX022_CNTL2_SRST	BIT(7)
-
-#define KX022_CNTL3_OWUF_FIELD	7
-
-#define KX022_INC1_IEA		BIT(4)
-#define KX022_INC1_IEN		BIT(5)
-
-#define KX022_GSEL_2G		(0 << 3)
-#define KX022_GSEL_4G		BIT(3)
-#define KX022_GSEL_8G		(2 << 3)
-#define KX022_GSEL_FIELD	(3 << 3)
-
-#define KX022_RES_8BIT		(0 << 6)
-#define KX022_RES_16BIT		BIT(6)
-
-#define KX022_OSA_0_781HZ	8
-#define KX022_OSA_1_563HZ	9
-#define KX022_OSA_3_125HZ	0xa
-#define KX022_OSA_6_250HZ	0xb
-#define KX022_OSA_12_50HZ	0
-#define KX022_OSA_25_00HZ	1
-#define KX022_OSA_50_00HZ	2
-#define KX022_OSA_100_0HZ	3
-#define KX022_OSA_200_0HZ	4
-#define KX022_OSA_400_0HZ	5
-#define KX022_OSA_800_0HZ	6
-#define KX022_OSA_1600HZ	7
-#define KX022_OSA_FIELD		0xf
-
-#define KX022_OWUF_0_781HZ	0
-#define KX022_OWUF_1_563HZ	1
-#define KX022_OWUF_3_125HZ	2
-#define KX022_OWUF_6_250HZ	3
-#define KX022_OWUF_12_50HZ	4
-#define KX022_OWUF_25_00HZ	5
-#define KX022_OWUF_50_00HZ	6
-#define KX022_OWUF_100_0HZ	7
-
-#define KX022_INC2_ZPWUE	BIT(0)
-#define KX022_INC2_ZNWUE	BIT(1)
-#define KX022_INC2_YPWUE	BIT(2)
-#define KX022_INC2_YNWUE	BIT(3)
-#define KX022_INC2_XPWUE	BIT(4)
-#define KX022_INC2_XNWUE	BIT(5)
-
-/* Min and Max sampling frequency in mHz */
-#define KX022_ACCEL_MIN_FREQ    12500
-#define KX022_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
-
-#endif /* __CROS_EC_ACCEL_KX022_H */
diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h
deleted file mode 100644
index f7488317f0..0000000000
--- a/driver/accel_kxcj9.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* KXCJ9 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_KXCJ9_H
-#define __CROS_EC_ACCEL_KXCJ9_H
-
-#include "task.h"
-
-/*
- * 7-bit address is 000111Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define KXCJ9_ADDR0_FLAGS	0x0E
-#define KXCJ9_ADDR1_FLAGS	0x0D
-#define KXCJ9_WHO_AM_I_VAL	0x0A
-
-/* Chip-specific registers */
-#define KXCJ9_XOUT_L		0x06
-#define KXCJ9_XOUT_H		0x07
-#define KXCJ9_YOUT_L		0x08
-#define KXCJ9_YOUT_H		0x09
-#define KXCJ9_ZOUT_L		0x0a
-#define KXCJ9_ZOUT_H		0x0b
-#define KXCJ9_DCST_RESP		0x0c
-#define KXCJ9_WHOAMI		0x0f
-#define KXCJ9_INT_SRC1		0x16
-#define KXCJ9_INT_SRC2		0x17
-#define KXCJ9_STATUS		0x18
-#define KXCJ9_INT_REL		0x1a
-#define KXCJ9_CTRL1		0x1b
-#define KXCJ9_CTRL2		0x1d
-#define KXCJ9_INT_CTRL1		0x1e
-#define KXCJ9_INT_CTRL2		0x1f
-#define KXCJ9_DATA_CTRL		0x21
-#define KXCJ9_WAKEUP_TIMER	0x29
-#define KXCJ9_SELF_TEST		0x3a
-#define KXCJ9_WAKEUP_THRESHOLD	0x6a
-
-#define KXCJ9_INT_SRC1_WUFS	BIT(1)
-#define KXCJ9_INT_SRC1_DRDY	BIT(4)
-
-#define KXCJ9_INT_SRC2_ZPWU	BIT(0)
-#define KXCJ9_INT_SRC2_ZNWU	BIT(1)
-#define KXCJ9_INT_SRC2_YPWU	BIT(2)
-#define KXCJ9_INT_SRC2_YNWU	BIT(3)
-#define KXCJ9_INT_SRC2_XPWU	BIT(4)
-#define KXCJ9_INT_SRC2_XNWU	BIT(5)
-
-#define KXCJ9_STATUS_INT	BIT(4)
-
-#define KXCJ9_CTRL1_WUFE	BIT(1)
-#define KXCJ9_CTRL1_DRDYE	BIT(5)
-#define KXCJ9_CTRL1_PC1		BIT(7)
-
-#define KXCJ9_GSEL_2G		(0 << 3)
-#define KXCJ9_GSEL_4G		BIT(3)
-#define KXCJ9_GSEL_8G		(2 << 3)
-#define KXCJ9_GSEL_8G_14BIT	(3 << 3)
-#define KXCJ9_GSEL_ALL          (3 << 3)
-
-#define KXCJ9_RES_8BIT		(0 << 6)
-#define KXCJ9_RES_12BIT		BIT(6)
-
-#define KXCJ9_CTRL2_OWUF	(7 << 0)
-#define KXCJ9_CTRL2_DCST	BIT(4)
-#define KXCJ9_CTRL2_SRST	BIT(7)
-
-#define KXCJ9_OWUF_0_781HZ	0
-#define KXCJ9_OWUF_1_563HZ	1
-#define KXCJ9_OWUF_3_125HZ	2
-#define KXCJ9_OWUF_6_250HZ	3
-#define KXCJ9_OWUF_12_50HZ	4
-#define KXCJ9_OWUF_25_00HZ	5
-#define KXCJ9_OWUF_50_00HZ	6
-#define KXCJ9_OWUF_100_0HZ	7
-
-#define KXCJ9_INT_CTRL1_IEL		BIT(3)
-#define KXCJ9_INT_CTRL1_IEA		BIT(4)
-#define KXCJ9_INT_CTRL1_IEN		BIT(5)
-
-#define KXCJ9_INT_CTRL2_ZPWUE		BIT(0)
-#define KXCJ9_INT_CTRL2_ZNWUE		BIT(1)
-#define KXCJ9_INT_CTRL2_YPWUE		BIT(2)
-#define KXCJ9_INT_CTRL2_YNWUE		BIT(3)
-#define KXCJ9_INT_CTRL2_XPWUE		BIT(4)
-#define KXCJ9_INT_CTRL2_XNWUE		BIT(5)
-
-#define KXCJ9_OSA_0_000HZ	0
-#define KXCJ9_OSA_0_781HZ	8
-#define KXCJ9_OSA_1_563HZ	9
-#define KXCJ9_OSA_3_125HZ	0xa
-#define KXCJ9_OSA_6_250HZ	0xb
-#define KXCJ9_OSA_12_50HZ	0
-#define KXCJ9_OSA_25_00HZ	1
-#define KXCJ9_OSA_50_00HZ	2
-#define KXCJ9_OSA_100_0HZ	3
-#define KXCJ9_OSA_200_0HZ	4
-#define KXCJ9_OSA_400_0HZ	5
-#define KXCJ9_OSA_800_0HZ	6
-#define KXCJ9_OSA_1600_HZ	7
-#define KXCJ9_OSA_FIELD		0xf
-
-/* Min and Max sampling frequency in mHz */
-#define KXCJ9_ACCEL_MIN_FREQ    12500
-#define KXCJ9_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
-
-#endif /* __CROS_EC_ACCEL_KXCJ9_H */
diff --git a/driver/accel_lis2ds.c b/driver/accel_lis2ds.c
deleted file mode 100644
index 93272262ad..0000000000
--- a/driver/accel_lis2ds.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * LIS2DS Accel module for Chrome EC
- * MEMS digital output motion sensor:
- * ultra-low-power high-performance 3-axis "pico" accelerometer
- *
- * For any details on driver implementation please
- * Refer to AN4748 Application Note on www.st.com
- */
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accel_lis2ds.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-/**
- * lis2ds_enable_fifo - Enable/Disable FIFO in LIS2DS12
- * @s: Motion sensor pointer
- * @mode: fifo_modes
- */
-static int lis2ds_enable_fifo(const struct motion_sensor_t *s, int mode)
-{
-	return st_write_data_with_mask(s, LIS2DS_FIFO_CTRL_ADDR,
-				       LIS2DS_FIFO_MODE_MASK, mode);
-}
-
-/**
- * Load data from internal sensor FIFO
- * DIFF8 bits set means FIFO Full because 256 samples -> 0x100
- */
-static int lis2ds_load_fifo(struct motion_sensor_t *s, uint16_t nsamples,
-			    uint32_t saved_ts)
-{
-	int ret, read_len, fifo_len, chunk_len, i;
-	struct ec_response_motion_sensor_data vect;
-	int *axis = s->raw_xyz;
-	uint8_t fifo[FIFO_READ_LEN];
-
-	fifo_len = nsamples * OUT_XYZ_SIZE;
-	read_len = 0;
-
-	while (read_len < fifo_len) {
-		chunk_len = GENERIC_MIN(fifo_len - read_len, sizeof(fifo));
-
-		ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LIS2DS_OUT_X_L_ADDR, fifo, chunk_len);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		for (i = 0; i < chunk_len; i += OUT_XYZ_SIZE) {
-			/* Apply precision, sensitivity and rotation vector */
-			st_normalize(s, axis, &fifo[i]);
-
-			/* Fill vector array */
-			vect.data[0] = axis[0];
-			vect.data[1] = axis[1];
-			vect.data[2] = axis[2];
-			vect.flags = 0;
-			vect.sensor_num = s - motion_sensors;
-			motion_sense_fifo_stage_data(&vect, s, 3, saved_ts);
-		}
-
-		read_len += chunk_len;
-	};
-
-	if (read_len > 0)
-		motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int lis2ds_config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-
-	/* Interrupt trigger level of power-on-reset is HIGH */
-	if (!(s->flags & MOTIONSENSE_FLAG_INT_ACTIVE_HIGH)) {
-		ret = st_write_data_with_mask(s, LIS2DS_H_ACTIVE_ADDR,
-					      LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/*
-		 * Configure FIFO threshold to 1 sample: interrupt on watermark
-		 * will be generated every time a new data sample will be stored
-		 * in FIFO. The interrupr on watermark is cleared only when the
-		 * number or samples still present in FIFO exceeds the
-		 * configured threshold.
-		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LIS2DS_FIFO_THS_ADDR, 1);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Enable interrupt on FIFO watermark and route to int1. */
-		ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR,
-					      LIS2DS_INT1_FTH, LIS2DS_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return ret;
-}
-
-/**
- * lis2ds_interrupt - interrupt from int1 pin of sensor
- * Schedule Motion Sense Task to manage Interrupts
- */
-void lis2ds_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LIS2DS_INT_EVENT);
-}
-
-/**
- * lis2ds_irq_handler - bottom half of the interrupt stack.
- */
-__maybe_unused static int lis2ds_irq_handler(struct motion_sensor_t *s,
-					     uint32_t *event)
-{
-	int ret = EC_SUCCESS;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCEL_LIS2DS_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		uint16_t nsamples = 0;
-		uint8_t fifo_src_samples[2];
-
-		ret = st_raw_read_n_noinc(s->port,
-					  s->i2c_spi_addr_flags,
-					  LIS2DS_FIFO_SRC_ADDR,
-					  (uint8_t *)fifo_src_samples,
-					  sizeof(fifo_src_samples));
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Check if FIFO is full. */
-		if (fifo_src_samples[0] & LIS2DS_FIFO_OVR_MASK)
-			CPRINTS("%s FIFO Overrun", s->name);
-
-		/* DIFF8 = 1 FIFO FULL, 256 unread samples. */
-		nsamples = fifo_src_samples[1] & LIS2DS_FIFO_DIFF_MASK;
-		if (fifo_src_samples[0] & LIS2DS_FIFO_DIFF8_MASK)
-			nsamples = 256;
-
-		ret = lis2ds_load_fifo(s, nsamples, last_interrupt_timestamp);
-	}
-
-	return ret;
-}
-
-/**
- * set_range - set full scale range
- * @s: Motion sensor pointer
- * @range: Range
- * @rnd: Round up/down flag
- */
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int err;
-	uint8_t reg_val;
-	int newrange = ST_NORMALIZE_RATE(range);
-
-	/* Adjust and check rounded value */
-	if (rnd && (newrange < range))
-		newrange <<= 1;
-
-	if (newrange > LIS2DS_ACCEL_FS_MAX_VAL)
-		newrange = LIS2DS_ACCEL_FS_MAX_VAL;
-	else if (newrange < LIS2DS_ACCEL_FS_MIN_VAL)
-		newrange = LIS2DS_ACCEL_FS_MIN_VAL;
-
-	reg_val = LIS2DS_FS_REG(newrange);
-
-	mutex_lock(s->mutex);
-	err = st_write_data_with_mask(s, LIS2DS_FS_ADDR, LIS2DS_FS_MASK,
-				      reg_val);
-	if (err == EC_SUCCESS)
-		/* Save internally gain for speed optimization. */
-		s->current_range = newrange;
-	mutex_unlock(s->mutex);
-
-	return EC_SUCCESS;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
-{
-	int ret, normalized_rate = 0;
-	struct stprivate_data *data = s->drv_data;
-	uint8_t reg_val = 0;
-
-	mutex_lock(s->mutex);
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* FIFO stop collecting events. Restart FIFO in Bypass mode */
-		ret = lis2ds_enable_fifo(s, LIS2DS_FIFO_BYPASS_MODE);
-		if (ret != EC_SUCCESS) {
-			CPRINTS("Failed to disable FIFO. Error: %d", ret);
-			goto unlock_rate;
-		}
-	}
-
-	/* Avoid LIS2DS_ODR_TO_REG to manage 0 mHz rate */
-	if (rate > 0) {
-		reg_val = LIS2DS_ODR_TO_REG(rate);
-		normalized_rate = LIS2DS_REG_TO_ODR(reg_val);
-
-		if (rnd && (normalized_rate < rate)) {
-			reg_val++;
-			normalized_rate = LIS2DS_REG_TO_ODR(rate);
-		}
-
-		if (normalized_rate < LIS2DS_ODR_MIN_VAL ||
-		    normalized_rate > LIS2DS_ODR_MAX_VAL) {
-			ret = EC_RES_INVALID_PARAM;
-			goto unlock_rate;
-		}
-	}
-
-	ret = st_write_data_with_mask(s, LIS2DS_ACC_ODR_ADDR,
-				      LIS2DS_ACC_ODR_MASK, reg_val);
-	if (ret == EC_SUCCESS) {
-		data->base.odr = normalized_rate;
-
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			/* FIFO restart collecting events in Cont. mode. */
-			ret = lis2ds_enable_fifo(s, LIS2DS_FIFO_CONT_MODE);
-			if (ret != EC_SUCCESS)
-				CPRINTS("Failed to enable FIFO. Error: %d",
-					ret);
-		}
-	}
-
-unlock_rate:
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int is_data_ready(const struct motion_sensor_t *s, int *ready)
-{
-	int ret, tmp;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_STATUS_REG, &tmp);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
-		return ret;
-	}
-
-	*ready = (LIS2DS_STS_XLDA_UP == (tmp & LIS2DS_STS_XLDA_UP));
-
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[OUT_XYZ_SIZE];
-	int ret, tmp = 0;
-
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!tmp) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-		return EC_SUCCESS;
-	}
-
-	/* Read 6 bytes starting at xyz_reg */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LIS2DS_OUT_X_L_ADDR, raw,
-				  LIS2DS_OUT_XYZ_SIZE);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
-		return ret;
-	}
-
-	/* Transform from LSB to real data with rotation and gain */
-	st_normalize(s, v, raw);
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp;
-	struct stprivate_data *data = s->drv_data;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_WHO_AM_I_REG, &tmp);
-	if (ret != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (tmp != LIS2DS_WHO_AM_I)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * This sensor can be powered through an EC reboot, so the state of
-	 * the sensor is unknown here. Initiate software reset to restore
-	 * sensor to default.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DS_SOFT_RESET_ADDR, LIS2DS_SOFT_RESET_MASK);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	msleep(20);
-
-	/* Enable BDU */
-	ret = st_write_data_with_mask(s, LIS2DS_BDU_ADDR, LIS2DS_BDU_MASK,
-				      LIS2DS_EN_BIT);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	ret = st_write_data_with_mask(s, LIS2DS_LIR_ADDR, LIS2DS_LIR_MASK,
-				      LIS2DS_EN_BIT);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	ret = st_write_data_with_mask(s, LIS2DS_INT2_ON_INT1_ADDR,
-				      LIS2DS_INT2_ON_INT1_MASK, LIS2DS_EN_BIT);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS))
-		ret = lis2ds_config_interrupt(s);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	mutex_unlock(s->mutex);
-
-	/* Set default resolution */
-	data->resol = LIS2DS_RESOLUTION;
-
-	return sensor_init_done(s);
-
-err_unlock:
-	mutex_unlock(s->mutex);
-	CPRINTS("%s: MS Init type:0x%X Error", s->name, s->type);
-
-	return ret;
-}
-
-const struct accelgyro_drv lis2ds_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = st_get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = st_get_data_rate,
-	.set_offset = st_set_offset,
-	.get_offset = st_get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = lis2ds_irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS */
-};
diff --git a/driver/accel_lis2ds.h b/driver/accel_lis2ds.h
deleted file mode 100644
index e25bc5954f..0000000000
--- a/driver/accel_lis2ds.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LIS2DS accelerometer module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_LIS2DS_H
-#define __CROS_EC_ACCEL_LIS2DS_H
-
-#include "driver/stm_mems_common.h"
-
-/*
- * 7-bit address is 110101Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define LIS2DS_ADDR0_FLAGS		0x1a
-#define LIS2DS_ADDR1_FLAGS		0x1e
-
-/* who am I  */
-#define LIS2DS_WHO_AM_I_REG		0x0f
-#define LIS2DS_WHO_AM_I			0x43
-
-/* X, Y, Z axis data len */
-#define LIS2DS_OUT_XYZ_SIZE		6
-
-/* COMMON DEFINE FOR ACCEL SENSOR */
-#define LIS2DS_EN_BIT			0x01
-#define LIS2DS_DIS_BIT			0x00
-
-#define LIS2DS_CTRL1_ADDR		0x20
-#define LIS2DS_CTRL2_ADDR		0x21
-#define LIS2DS_CTRL3_ADDR		0x22
-#define LIS2DS_TAP_X_EN			0x20
-#define LIS2DS_TAP_Y_EN			0x10
-#define LIS2DS_TAP_Z_EN			0x08
-#define LIS2DS_TAP_EN_MASK		(LIS2DS_TAP_X_EN | \
-					 LIS2DS_TAP_Y_EN | \
-					 LIS2DS_TAP_Z_EN)
-#define LIS2DS_TAP_EN_ALL		0x07
-
-#define LIS2DS_CTRL4_ADDR		0x23
-#define LIS2DS_INT1_FTH			0x02
-#define LIS2DS_INT1_D_TAP		0x08
-#define LIS2DS_INT1_S_TAP		0x40
-
-#define LIS2DS_CTRL5_ADDR		0x24
-#define LIS2DS_FIFO_CTRL_ADDR		0x25
-#define LIS2DS_FIFO_MODE_MASK		0xe0
-#define LIS2DS_FIFO_BYPASS_MODE		0
-#define LIS2DS_FIFO_MODE		1
-#define LIS2DS_FIFO_CONT_MODE		6
-
-#define LIS2DS_STATUS_REG		0x27
-#define LIS2DS_STS_XLDA_UP		0x01
-#define LIS2DS_SINGLE_TAP_UP		0x08
-#define LIS2DS_DOUBLE_TAP_UP		0x10
-#define LIS2DS_FIFO_THS_UP		0x80
-
-#define LIS2DS_OUT_X_L_ADDR		0x28
-#define LIS2DS_FIFO_THS_ADDR		0x2e
-
-#define LIS2DS_FIFO_SRC_ADDR		0x2f
-#define LIS2DS_FIFO_DIFF_MASK		0xff
-#define LIS2DS_FIFO_DIFF8_MASK		0x20
-#define LIS2DS_FIFO_OVR_MASK		0x40
-#define LIS2DS_FIFO_FTH_MASK		0x80
-
-/*
- * Concatenated with DIFF8 bit in FIFO_SRC (2Fh) register, it represents the
- * number of unread samples stored in FIFO. (000000000 = FIFO empty;
- * 100000000 = FIFO full, 256 unread samples).
- */
-#define LIS2DS_FIFO_SAMPLES_ADDR	0x30
-#define LIS2DS_TAP_6D_THS_ADDR		0x31
-#define LIS2DS_INT_DUR_ADDR		0x32
-#define LIS2DS_WAKE_UP_THS_ADDR		0x33
-
-#define LIS2DS_TAP_SRC_ADDR		0x38
-#define LIS2DS_TAP_EVENT_DETECT		0x40
-
-/* Alias Register/Mask */
-#define LIS2DS_ACC_ODR_ADDR		LIS2DS_CTRL1_ADDR
-#define LIS2DS_ACC_ODR_MASK		0xf0
-
-#define LIS2DS_BDU_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_BDU_MASK			0x01
-
-#define LIS2DS_SOFT_RESET_ADDR		LIS2DS_CTRL2_ADDR
-#define LIS2DS_SOFT_RESET_MASK		0x40
-
-#define LIS2DS_LIR_ADDR			LIS2DS_CTRL3_ADDR
-#define LIS2DS_LIR_MASK			0x04
-
-#define LIS2DS_H_ACTIVE_ADDR		LIS2DS_CTRL3_ADDR
-#define LIS2DS_H_ACTIVE_MASK		0x02
-
-#define LIS2DS_INT1_FTH_ADDR		LIS2DS_CTRL4_ADDR
-#define LIS2DS_INT1_FTH_MASK		0x02
-
-#define LIS2DS_INT2_ON_INT1_ADDR	LIS2DS_CTRL5_ADDR
-#define LIS2DS_INT2_ON_INT1_MASK	0x20
-
-#define LIS2DS_DRDY_PULSED_ADDR		LIS2DS_CTRL5_ADDR
-#define LIS2DS_DRDY_PULSED_MASK		0x80
-
-/* Acc data rate for HR mode */
-enum lis2ds_odr {
-	LIS2DS_ODR_POWER_OFF_VAL = 0x00,
-	LIS2DS_ODR_12HZ_VAL,
-	LIS2DS_ODR_25HZ_VAL,
-	LIS2DS_ODR_50HZ_VAL,
-	LIS2DS_ODR_100HZ_VAL,
-	LIS2DS_ODR_200HZ_VAL,
-	LIS2DS_ODR_400HZ_VAL,
-	LIS2DS_ODR_800HZ_VAL,
-	LIS2DS_ODR_LIST_NUM
-};
-
-/* Absolute Acc rate */
-#define LIS2DS_ODR_MIN_VAL		12500
-#define LIS2DS_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(800000, LIS2DS_ODR_MIN_VAL)
-
-/* ODR reg value from selected data rate in mHz */
-#define LIS2DS_ODR_TO_REG(_odr) (__fls(_odr / LIS2DS_ODR_MIN_VAL) + 1)
-
-/* Normalized ODR value from selected ODR register value */
-#define LIS2DS_REG_TO_ODR(_reg) \
-	(LIS2DS_ODR_MIN_VAL << (_reg - LIS2DS_ODR_12HZ_VAL))
-
-/* Full scale range registers */
-#define LIS2DS_FS_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_FS_MASK			0x0c
-
-/* Acc FS value */
-enum lis2ds_fs {
-	LIS2DS_FS_2G_VAL = 0x00,
-	LIS2DS_FS_16G_VAL,
-	LIS2DS_FS_4G_VAL,
-	LIS2DS_FS_8G_VAL,
-	LIS2DS_FS_LIST_NUM
-};
-
-#define LIS2DS_ACCEL_FS_MAX_VAL		16
-#define LIS2DS_ACCEL_FS_MIN_VAL		2
-
-/* Reg value from Full Scale */
-#define LIS2DS_FS_REG(_fs) \
-	(_fs == 2 ? LIS2DS_FS_2G_VAL : \
-	_fs == 16 ? LIS2DS_FS_16G_VAL : \
-	__fls(_fs))
-
-/*
- * Sensor resolution in number of bits. Sensor has two resolution:
- * 10 and 14 bit for LP and HR mode resp.
- */
-#define LIS2DS_RESOLUTION		16
-
-extern const struct accelgyro_drv lis2ds_drv;
-
-void lis2ds_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ACCEL_LIS2DS_H */
diff --git a/driver/accel_lis2dw12.c b/driver/accel_lis2dw12.c
deleted file mode 100644
index 1872e572f2..0000000000
--- a/driver/accel_lis2dw12.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * LIS2DW12 accelerometer module for Chrome EC 3D digital accelerometer.
- * For more details on LIS2DW12 device please refers to www.st.com.
- */
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "accel_lis2dw12.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#if defined(CONFIG_ACCEL_INTERRUPTS) && defined(CONFIG_ACCEL_LIS2DW_AS_BASE)
-/*
- * Enable interrupts and FIFO only when the accelerometer is the main sensor.
- */
-#define LIS2DW12_ENABLE_FIFO
-#endif
-
-#if defined(CONFIG_ZEPHYR) && defined(CONFIG_ACCEL_INTERRUPTS)
-/* Get the motion sensor ID of the LIS2DW12 sensor that generates the
- * interrupt. The interrupt is converted to the event and transferred to
- * motion sense task that actually handles the interrupt.
- *
- * Here we use an alias (lis2dw12_int) to get the motion sensor ID. This alias
- * MUST be defined for this driver to work.
- * aliases {
- *   lis2dw12-int = &lid_accel;
- * };
- */
-#if DT_NODE_EXISTS(DT_ALIAS(lis2dw12_int))
-#define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lis2dw12_int)))
-#endif
-#endif
-
-STATIC_IF(LIS2DW12_ENABLE_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-/**
- * lis2dw12_enable_fifo - Enable/Disable FIFO in LIS2DW12
- * @s: Motion sensor pointer
- * @mode: fifo_modes
- */
-static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s,
-			enum lis2dw12_fmode mode)
-{
-	return st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
-				       LIS2DW12_FIFO_MODE_MASK, mode);
-}
-
-/**
- * Load data from internal sensor FIFO.
- * @s: Motion sensor pointer
- */
-static __maybe_unused int lis2dw12_load_fifo(struct motion_sensor_t *s,
-			 int nsamples, uint32_t *last_fifo_read_ts)
-{
-	int ret, left, length, i;
-	struct ec_response_motion_sensor_data vect;
-	uint32_t interrupt_timestamp = last_interrupt_timestamp;
-	int *axis = s->raw_xyz;
-	uint8_t fifo[FIFO_READ_LEN];
-
-	/* Each sample are OUT_XYZ_SIZE bytes. */
-	left = nsamples * OUT_XYZ_SIZE;
-
-	do {
-		/*
-		 * Limit FIFO read data to burst of FIFO_READ_LEN size because
-		 * read operatios in under i2c mutex lock.
-		 */
-		if (left > FIFO_READ_LEN)
-			length = FIFO_READ_LEN;
-		else
-			length = left;
-
-		ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
-				    LIS2DW12_OUT_X_L_ADDR, fifo, length);
-		*last_fifo_read_ts = __hw_clock_source_read();
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		for (i = 0; i < length; i += OUT_XYZ_SIZE) {
-			/* Apply precision, sensitivity and rotation vector. */
-			st_normalize(s, axis, &fifo[i]);
-
-			/* Fill vector array. */
-			vect.data[X] = axis[X];
-			vect.data[Y] = axis[Y];
-			vect.data[Z] = axis[Z];
-			vect.flags = 0;
-			vect.sensor_num = s - motion_sensors;
-			motion_sense_fifo_stage_data(&vect, s, 3,
-						     interrupt_timestamp);
-		}
-		left -= length;
-	} while (left > 0);
-
-	motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-
-/**
- * lis2dw12_get_fifo_samples - check for stored FIFO samples.
- */
-static __maybe_unused int lis2dw12_get_fifo_samples(struct motion_sensor_t *s,
-						    int *nsamples)
-{
-	int ret, tmp;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DW12_FIFO_SAMPLES_ADDR, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	*nsamples = tmp & LIS2DW12_FIFO_DIFF_MASK;
-
-	return EC_SUCCESS;
-}
-
-static __maybe_unused int fifo_data_avail(struct motion_sensor_t *s)
-{
-	int ret, nsamples;
-
-	if (s->flags & MOTIONSENSE_FLAG_INT_SIGNAL)
-		return gpio_get_level(s->int_signal) ==
-			!!(MOTIONSENSE_FLAG_INT_ACTIVE_HIGH & s->flags);
-
-	ret = lis2dw12_get_fifo_samples(s, &nsamples);
-	/* If we failed to read the FIFO size assume empty. */
-	if (ret != EC_SUCCESS)
-		return 0;
-	return nsamples;
-}
-
-/**
- * lis2dw12_config_interrupt- Configure interrupt for supported features.
- * @s: Motion sensor pointer
- *
- * Must works with interface mutex locked
- */
-static __maybe_unused int lis2dw12_config_interrupt(
-		const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* Configure FIFO watermark level. */
-		ret = st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
-				LIS2DW12_FIFO_THRESHOLD_MASK, 1);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Enable interrupt on FIFO watermark and route to int1. */
-		ret = st_write_data_with_mask(s, LIS2DW12_INT1_FTH_ADDR,
-				LIS2DW12_INT1_FTH_MASK, LIS2DW12_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
-		/*
-		 * Configure D-TAP event detection on 3 axis.
-		 * For more details please refer to AN5038.
-		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_X_ADDR, 0x09);
-		if (ret != EC_SUCCESS)
-			return ret;
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_Y_ADDR, 0x09);
-		if (ret != EC_SUCCESS)
-			return ret;
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_Z_ADDR, 0xE9);
-		if (ret != EC_SUCCESS)
-			return ret;
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_INT_DUR_ADDR, 0x7F);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* Enable D-TAP event detection. */
-		ret = st_write_data_with_mask(s, LIS2DW12_WAKE_UP_THS_ADDR,
-				LIS2DW12_SINGLE_DOUBLE_TAP,
-				LIS2DW12_EN_BIT);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/*
-		 * Enable D-TAP detection on int_1 pad. In any case D-TAP event
-		 * can be detected only if ODR is over 200 Hz.
-		 */
-		ret = st_write_data_with_mask(s, LIS2DW12_INT1_TAP_ADDR,
-				LIS2DW12_INT1_DTAP_MASK,
-				LIS2DW12_EN_BIT);
-	}
-	return ret;
-}
-
-#ifdef LIS2DW12_ENABLE_FIFO
-static void lis2dw12_handle_interrupt_for_fifo(uint32_t ts)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-	    time_after(ts, last_interrupt_timestamp))
-		last_interrupt_timestamp = ts;
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LIS2DW12_INT_EVENT);
-}
-
-/**
- * lis2dw12_interrupt - interrupt from int pin of sensor
- * Schedule Motion Sense Task to manage Interrupts.
- */
-void lis2dw12_interrupt(enum gpio_signal signal)
-{
-	lis2dw12_handle_interrupt_for_fifo(__hw_clock_source_read());
-}
-
-/**
- * lis2dw12_irq_handler - bottom half of the interrupt stack.
- */
-static int lis2dw12_irq_handler(struct motion_sensor_t *s,
-					       uint32_t *event)
-{
-	int ret = EC_SUCCESS;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCEL_LIS2DW12_INT_EVENT))) {
-		return EC_ERROR_NOT_HANDLED;
-	}
-
-	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
-		int status = 0;
-
-		/* Read Status register to check TAP events. */
-		st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			     LIS2DW12_STATUS_TAP, &status);
-		if (status & LIS2DW12_DOUBLE_TAP)
-			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-	}
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		int nsamples;
-		uint32_t last_fifo_read_ts;
-		uint32_t triggering_interrupt_timestamp =
-			last_interrupt_timestamp;
-
-		ret = lis2dw12_get_fifo_samples(s, &nsamples);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		last_fifo_read_ts = __hw_clock_source_read();
-		if (nsamples == 0)
-			return EC_SUCCESS;
-
-		ret = lis2dw12_load_fifo(s, nsamples, &last_fifo_read_ts);
-
-		/*
-		 * Check if FIFO isn't empty and we never got an interrupt.
-		 * This can happen if new entries were added to the FIFO after
-		 * the count was read, but before the FIFO was cleared out.
-		 * In the long term it might be better to use the last
-		 * spread timestamp instead.
-		 */
-		if (fifo_data_avail(s) &&
-		    triggering_interrupt_timestamp == last_interrupt_timestamp)
-			lis2dw12_handle_interrupt_for_fifo(last_fifo_read_ts);
-	}
-
-	return ret;
-}
-#endif
-
-/**
- * set_power_mode - set sensor power mode
- * @s: Motion sensor pointer
- * @mode: LIS2DW12_LOW_POWER, LIS2DW12_HIGH_PERF
- * @lpmode: LIS2DW12_LOW_POWER_MODE_2,
- *          LIS2DW12_LOW_POWER_MODE_3,
- *          LIS2DW12_LOW_POWER_MODE_4
- *
- * TODO: LIS2DW12_LOW_POWER_MODE_1 not implemented because output differ
- *       in resolution
- */
-static int set_power_mode(const struct motion_sensor_t *s,
-			  enum lis2sw12_mode mode,
-			  enum lis2sw12_lpmode lpmode)
-{
-	int ret = EC_SUCCESS;
-
-	if (mode == LIS2DW12_LOW_POWER &&
-	    lpmode == LIS2DW12_LOW_POWER_MODE_1)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* Set Mode and Low Power Mode. */
-	ret = st_write_data_with_mask(s, LIS2DW12_ACC_MODE_ADDR,
-				      LIS2DW12_ACC_MODE_MASK, mode);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = st_write_data_with_mask(s, LIS2DW12_ACC_LPMODE_ADDR,
-				      LIS2DW12_ACC_LPMODE_MASK, lpmode);
-	return ret;
-}
-
-/**
- * set_range - set full scale range
- * @s: Motion sensor pointer
- * @range: Range
- * @rnd: Round up/down flag
- */
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int err = EC_SUCCESS;
-	uint8_t reg_val;
-	int newrange = range;
-
-	/* Adjust and check rounded value. */
-	if (rnd && (newrange < LIS2DW12_NORMALIZE_FS(newrange)))
-		newrange <<= 1;
-
-	if (newrange > LIS2DW12_ACCEL_FS_MAX_VAL)
-		newrange = LIS2DW12_ACCEL_FS_MAX_VAL;
-
-	reg_val = LIS2DW12_FS_REG(newrange);
-
-	mutex_lock(s->mutex);
-	/*
-	 * FIFO stop collecting events. Restart FIFO in Bypass mode.
-	 * If Range is changed all samples in FIFO must be discharged because
-	 * with a different sensitivity.
-	 */
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO)) {
-		err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
-		if (err != EC_SUCCESS)
-			goto unlock_rate;
-	}
-
-	err = st_write_data_with_mask(s, LIS2DW12_FS_ADDR, LIS2DW12_FS_MASK,
-				      reg_val);
-	if (err == EC_SUCCESS)
-		s->current_range = newrange;
-	else
-		goto unlock_rate;
-
-	/* FIFO restart collecting events in Cont. mode. */
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO))
-		err = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
-
-unlock_rate:
-	mutex_unlock(s->mutex);
-
-	return err;
-}
-
-/**
- * ODR reg value from selected data rate in mHz.
- */
-static uint8_t odr_to_reg(int odr)
-{
-	if (odr <= LIS2DW12_ODR_MIN_VAL)
-		return LIS2DW12_ODR_12HZ_VAL;
-
-	return (__fls(odr / LIS2DW12_ODR_MIN_VAL) + LIS2DW12_ODR_12HZ_VAL);
-}
-
-/**
- * Normalized ODR value from selected data rate in mHz.
- */
-static int odr_to_normalize(int odr)
-{
-	if (odr <= LIS2DW12_ODR_MIN_VAL)
-		return LIS2DW12_ODR_MIN_VAL;
-
-	return (LIS2DW12_ODR_MIN_VAL << (__fls(odr / LIS2DW12_ODR_MIN_VAL)));
-}
-
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
-{
-	int ret, normalized_rate;
-	struct stprivate_data *data = s->drv_data;
-	uint8_t reg_val;
-
-	mutex_lock(s->mutex);
-
-	/* FIFO stop collecting events. Restart FIFO in Bypass mode. */
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO)) {
-		ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_BYPASS_MODE);
-		if (ret != EC_SUCCESS)
-			goto unlock_rate;
-	}
-
-	if (rate == 0) {
-		ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR,
-					      LIS2DW12_ACC_ODR_MASK,
-					      LIS2DW12_ODR_POWER_OFF_VAL);
-		if (ret == EC_SUCCESS)
-			data->base.odr = LIS2DW12_ODR_POWER_OFF_VAL;
-
-		goto unlock_rate;
-	}
-
-	reg_val = odr_to_reg(rate);
-	normalized_rate = odr_to_normalize(rate);
-
-	if (rnd && (normalized_rate < rate)) {
-		reg_val++;
-		normalized_rate <<= 1;
-	}
-
-	if (reg_val > LIS2DW12_ODR_1_6kHZ_VAL) {
-		reg_val = LIS2DW12_ODR_1_6kHZ_VAL;
-		normalized_rate = LIS2DW12_ODR_MAX_VAL;
-	} else if (reg_val < LIS2DW12_ODR_12HZ_VAL) {
-		reg_val = LIS2DW12_ODR_12HZ_VAL;
-		normalized_rate = LIS2DW12_ODR_MIN_VAL;
-	}
-
-	/* lis2dwl supports 14 bit resolution only at high performance mode,
-	 * and it will always stay at high performance mode from initialization.
-	 * But lis2dw12 needs switch low power mode according to odr value.
-	 */
-	if (!IS_ENABLED(CONFIG_ACCEL_LIS2DWL)) {
-		if (reg_val > LIS2DW12_ODR_200HZ_VAL)
-			ret = set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
-		else
-			ret = set_power_mode(s, LIS2DW12_LOW_POWER,
-					LIS2DW12_LOW_POWER_MODE_2);
-	}
-
-	ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR,
-				      LIS2DW12_ACC_ODR_MASK, reg_val);
-	if (ret == EC_SUCCESS)
-		data->base.odr = normalized_rate;
-
-	/* FIFO restart collecting events in continuous mode. */
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO))
-		ret = lis2dw12_enable_fifo(s, LIS2DW12_FIFO_CONT_MODE);
-
-unlock_rate:
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int is_data_ready(const struct motion_sensor_t *s, int *ready)
-{
-	int ret, tmp;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DW12_STATUS_REG, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	*ready = (LIS2DW12_STS_DRDY_UP == (tmp & LIS2DW12_STS_DRDY_UP));
-
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[OUT_XYZ_SIZE];
-	int ret, tmp = 0;
-
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!tmp) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-		return EC_SUCCESS;
-	}
-
-	/* Read 6 bytes starting at xyz_reg. */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_OUT_X_L_ADDR, raw,
-				  OUT_XYZ_SIZE);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
-		return ret;
-	}
-
-	/* Transform from LSB to real data with rotation and gain. */
-	st_normalize(s, v, raw);
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp, timeout = 0, status;
-	struct stprivate_data *data = s->drv_data;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DW12_WHO_AM_I_REG, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (tmp != LIS2DW12_WHO_AM_I)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * This sensor can be powered through an EC reboot, so the state of
-	 * the sensor is unknown here. Initiate software reset to restore
-	 * sensor to default.
-	 */
-	mutex_lock(s->mutex);
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DW12_SOFT_RESET_ADDR, LIS2DW12_SOFT_RESET_MASK);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	/* Wait End of Reset. */
-	do {
-		if (timeout > 10) {
-			ret = EC_ERROR_TIMEOUT;
-			goto err_unlock;
-		}
-
-		msleep(1);
-		timeout += 1;
-		ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_SOFT_RESET_ADDR, &status);
-	} while (ret != EC_SUCCESS || (status & LIS2DW12_SOFT_RESET_MASK) != 0);
-
-	/* Enable BDU. */
-	ret = st_write_data_with_mask(s, LIS2DW12_BDU_ADDR, LIS2DW12_BDU_MASK,
-				      LIS2DW12_EN_BIT);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	ret = st_write_data_with_mask(s, LIS2DW12_LIR_ADDR, LIS2DW12_LIR_MASK,
-				      LIS2DW12_EN_BIT);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	/* Interrupt trigger level of power-on-reset is HIGH */
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO) &&
-	    !(MOTIONSENSE_FLAG_INT_ACTIVE_HIGH & s->flags)) {
-		ret = st_write_data_with_mask(s, LIS2DW12_H_ACTIVE_ADDR,
-						LIS2DW12_H_ACTIVE_MASK,
-						LIS2DW12_EN_BIT);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-	}
-
-	if (IS_ENABLED(CONFIG_ACCEL_LIS2DWL))
-		/*
-		 * lis2dwl supports 14 bit resolution only
-		 * at high performance mode
-		 */
-		ret = set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
-	else
-		/* Set default Mode and Low Power Mode. */
-		ret = set_power_mode(s, LIS2DW12_LOW_POWER,
-				     LIS2DW12_LOW_POWER_MODE_2);
-	if (ret != EC_SUCCESS)
-		goto err_unlock;
-
-	if (IS_ENABLED(LIS2DW12_ENABLE_FIFO)) {
-		ret = lis2dw12_config_interrupt(s);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-	}
-	mutex_unlock(s->mutex);
-
-	/* Set default resolution. */
-	data->resol = LIS2DW12_RESOLUTION;
-	return sensor_init_done(s);
-
-err_unlock:
-	mutex_unlock(s->mutex);
-	CPRINTS("%s: MS Init type:0x%X Error(%d)", s->name, s->type, ret);
-	return ret;
-}
-
-const struct accelgyro_drv lis2dw12_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = st_get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = st_get_data_rate,
-	.set_offset = st_set_offset,
-	.get_offset = st_get_offset,
-#ifdef LIS2DW12_ENABLE_FIFO
-	.irq_handler = lis2dw12_irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS && CONFIG_ACCEL_LIS2DW_AS_BASE */
-};
diff --git a/driver/accel_lis2dw12.h b/driver/accel_lis2dw12.h
deleted file mode 100644
index 8e1c97464c..0000000000
--- a/driver/accel_lis2dw12.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * LIS2DW12 accelerometer include file for Chrome EC 3D digital accelerometer.
- * For more details on LIS2DW12 device please refer to www.st.com.
- */
-
-#ifndef __CROS_EC_ACCEL_LIS2DW12_H
-#define __CROS_EC_ACCEL_LIS2DW12_H
-
-#include "driver/accel_lis2dw12_public.h"
-#include "stm_mems_common.h"
-
-/* Who am I. */
-#define LIS2DW12_WHO_AM_I_REG		0x0f
-#define LIS2DW12_WHO_AM_I		0x44
-
-/* Registers sensor. */
-#define LIS2DW12_CTRL1_ADDR		0x20
-#define LIS2DW12_CTRL2_ADDR		0x21
-#define LIS2DW12_CTRL3_ADDR		0x22
-
-#define LIS2DW12_CTRL4_ADDR		0x23
-
-/* CTRL4 bits. */
-#define LIS2DW12_INT1_FTH		0x02
-#define LIS2DW12_INT1_D_TAP		0x08
-#define LIS2DW12_INT1_S_TAP		0x40
-
-#define LIS2DW12_CTRL5_ADDR		0x24
-
-/* CTRL5 bits. */
-#define LIS2DW12_INT2_FTH		0x02
-
-#define LIS2DW12_CTRL6_ADDR		0x25
-#define LIS2DW12_STATUS_REG		0x27
-
-/* STATUS bits. */
-#define LIS2DW12_STS_DRDY_UP		0x01
-#define LIS2DW12_SINGLE_TAP_UP		0x08
-#define LIS2DW12_DOUBLE_TAP_UP		0x10
-#define LIS2DW12_FIFO_THS_UP		0x80
-
-#define LIS2DW12_OUT_X_L_ADDR		0x28
-
-#define LIS2DW12_FIFO_CTRL_ADDR		0x2e
-
-/* FIFO_CTRL bits. */
-#define LIS2DW12_FIFO_MODE_MASK		0xe0
-
-/* List of supported FIFO mode. */
-enum lis2dw12_fmode {
-	LIS2DW12_FIFO_BYPASS_MODE = 0,
-	LIS2DW12_FIFO_MODE,
-	LIS2DW12_FIFO_CONT_MODE = 6
-};
-
-#define LIS2DW12_FIFO_THRESHOLD_MASK	0x1f
-
-#define LIS2DW12_FIFO_SAMPLES_ADDR	0x2f
-#define LIS2DW12_TAP_THS_X_ADDR		0x30
-#define LIS2DW12_TAP_THS_Y_ADDR		0x31
-#define LIS2DW12_TAP_THS_Z_ADDR		0x32
-#define LIS2DW12_INT_DUR_ADDR		0x33
-
-#define LIS2DW12_WAKE_UP_THS_ADDR	0x34
-
-/* TAP bits. */
-#define LIS2DW12_SINGLE_DOUBLE_TAP	0x80
-
-/* FIFO_SAMPLES bits. */
-#define LIS2DW12_FIFO_DIFF_MASK		0x3f
-#define LIS2DW12_FIFO_OVR_MASK		0x40
-#define LIS2DW12_FIFO_FTH_MASK		0x80
-
-#define LIS2DW12_ABS_INT_CFG_ADDR	0x3f
-
-/* INT Configuration bits. */
-#define LIS2DW12_DRDY_PULSED		0x80
-#define LIS2DW12_INT2_ON_INT1		0x40
-#define LIS2DW12_INT_ENABLE		0x20
-
-/* Alias Registers/Masks. */
-#define LIS2DW12_ACC_ODR_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_ODR_MASK		0xf0
-
-#define LIS2DW12_ACC_MODE_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_MODE_MASK		0x0c
-
-/* Power mode selection. */
-enum lis2sw12_mode {
-	LIS2DW12_LOW_POWER = 0,
-	LIS2DW12_HIGH_PERF,
-	LIS2DW12_SINGLE_DC,
-	LIS2DW12_LOW_POWER_LIST_NUM
-};
-
-#define LIS2DW12_ACC_LPMODE_ADDR	LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_LPMODE_MASK	0x03
-
-/*
- * Low power mode selection.
- * TODO: Support all Low Power Mode. Actually is not supported only
- * LOW_POWER_MODE_1.
- */
-enum lis2sw12_lpmode {
-	LIS2DW12_LOW_POWER_MODE_1 = 0,
-	LIS2DW12_LOW_POWER_MODE_2,
-	LIS2DW12_LOW_POWER_MODE_3,
-	LIS2DW12_LOW_POWER_MODE_4,
-	LIS2DW12_LOW_POWER_MODE_LIST_NUM
-};
-
-#define LIS2DW12_BDU_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BDU_MASK		0x08
-
-#define LIS2DW12_SOFT_RESET_ADDR	LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_SOFT_RESET_MASK	0x40
-
-#define LIS2DW12_BOOT_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BOOT_MASK		0x80
-
-#define LIS2DW12_LIR_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_LIR_MASK		0x10
-
-#define LIS2DW12_H_ACTIVE_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_H_ACTIVE_MASK		0x08
-
-#define LIS2DW12_INT1_FTH_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_FTH_MASK		LIS2DW12_INT1_FTH
-
-#define LIS2DW12_INT1_TAP_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_DTAP_MASK		0x08
-#define LIS2DW12_INT1_STAP_MASK		0x40
-
-#define LIS2DW12_INT1_D_TAP_EN		LIS2DW12_INT1_DTAP_MASK
-
-#define LIS2DW12_STATUS_TAP		LIS2DW12_STS_DRDY_UP
-#define LIS2DW12_SINGLE_TAP		LIS2DW12_SINGLE_TAP_UP
-#define LIS2DW12_DOUBLE_TAP		LIS2DW12_DOUBLE_TAP_UP
-
-#define LIS2DW12_INT2_ON_INT1_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_INT2_ON_INT1_MASK	LIS2DW12_INT2_ON_INT1
-
-#define LIS2DW12_DRDY_PULSED_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_DRDY_PULSED_MASK	LIS2DW12_DRDY_PULSED
-
-/* Acc data rate for HR mode. */
-enum lis2dw12_odr {
-	LIS2DW12_ODR_POWER_OFF_VAL = 0x00,
-	LIS2DW12_ODR_12HZ_VAL = 0x02,
-	LIS2DW12_ODR_25HZ_VAL,
-	LIS2DW12_ODR_50HZ_VAL,
-	LIS2DW12_ODR_100HZ_VAL,
-	LIS2DW12_ODR_200HZ_VAL,
-	LIS2DW12_ODR_400HZ_VAL,
-	LIS2DW12_ODR_800HZ_VAL,
-	LIS2DW12_ODR_1_6kHZ_VAL,
-	LIS2DW12_ODR_LIST_NUM
-};
-
-/* Full scale range registers. */
-#define LIS2DW12_FS_ADDR		LIS2DW12_CTRL6_ADDR
-#define LIS2DW12_FS_MASK		0x30
-
-/* Acc FS value. */
-enum lis2dw12_fs {
-	LIS2DW12_FS_2G_VAL = 0x00,
-	LIS2DW12_FS_4G_VAL,
-	LIS2DW12_FS_8G_VAL,
-	LIS2DW12_FS_16G_VAL,
-	LIS2DW12_FS_LIST_NUM
-};
-
-#define LIS2DW12_ACCEL_FS_MAX_VAL	16
-
-/* Acc Gain value. */
-#define LIS2DW12_FS_2G_GAIN		3904
-#define LIS2DW12_FS_4G_GAIN		(LIS2DW12_FS_2G_GAIN << 1)
-#define LIS2DW12_FS_8G_GAIN		(LIS2DW12_FS_2G_GAIN << 2)
-#define LIS2DW12_FS_16G_GAIN		(LIS2DW12_FS_2G_GAIN << 3)
-
-/* FS Full Scale value from Gain. */
-#define LIS2DW12_GAIN_FS(_gain) \
-	(2 << (31 - __builtin_clz(_gain / LIS2DW12_FS_2G_GAIN)))
-
-/* Gain value from selected Full Scale. */
-#define LIS2DW12_FS_GAIN(_fs) \
-	(LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
-
-/* Reg value from Full Scale. */
-#define LIS2DW12_FS_REG(_fs) \
-	(30 - __builtin_clz(_fs))
-
-/* Normalized FS value from Full Scale. */
-#define LIS2DW12_NORMALIZE_FS(_fs) \
-	(1 << (30 - __builtin_clz(_fs)))
-
-/*
- * Sensor resolution in number of bits.
- * Sensor driver support 14 bits resolution.
- * TODO: Support all "LP Power Mode" (res. 12/14 bits).
- */
-#define LIS2DW12_RESOLUTION		14
-
-#endif /* __CROS_EC_ACCEL_LIS2DW12_H */
diff --git a/driver/accelgyro_bmi160.c b/driver/accelgyro_bmi160.c
deleted file mode 100644
index f92f61d181..0000000000
--- a/driver/accelgyro_bmi160.c
+++ /dev/null
@@ -1,780 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * BMI160 accelerometer and gyro module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "accelgyro_bmi_common.h"
-#include "accelgyro_bmi160.h"
-#include "mag_bmm150.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_orientation.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#if defined(CONFIG_ZEPHYR) && defined(CONFIG_ACCEL_INTERRUPTS)
-/* Get the motion sensor ID of the BMI160 sensor that generates the interrupt.
- * The interrupt is converted to the event and transferred to motion sense task
- * that actually handles the interrupt.
- *
- * Here we use an alias (bmi160_int) to get the motion sensor ID. This alias
- * MUST be defined for this driver to work.
- * aliases {
- *   bmi160-int = &base_accel;
- * };
- */
-#if DT_NODE_EXISTS(DT_ALIAS(bmi160_int))
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
-#endif
-#endif
-
-STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) void irq_set_orientation(
-				struct motion_sensor_t *s,
-				int interrupt);
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 4,
-	[MOTIONSENSE_TYPE_GYRO] = 80,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
-
-/**
- * Control access to the compass on the secondary i2c interface:
- * enable values are:
- * 1: manual access, we can issue i2c to the compass
- * 0: data access: BMI160 gather data periodically from the compass.
- */
-static __maybe_unused int bmi160_sec_access_ctrl(
-		const int port,
-		const uint16_t i2c_spi_addr_flags,
-		const int enable)
-{
-	int mag_if_ctrl;
-	bmi_read8(port, i2c_spi_addr_flags,
-		  BMI160_MAG_IF_1, &mag_if_ctrl);
-	if (enable) {
-		mag_if_ctrl |= BMI160_MAG_MANUAL_EN;
-		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
-		mag_if_ctrl |= BMI160_MAG_READ_BURST_1;
-	} else {
-		mag_if_ctrl &= ~BMI160_MAG_MANUAL_EN;
-		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
-		mag_if_ctrl |= BMI160_MAG_READ_BURST_8;
-	}
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_IF_1, mag_if_ctrl);
-}
-
-/**
- * Read register from compass.
- * Assuming we are in manual access mode, read compass i2c register.
- */
-int bmi160_sec_raw_read8(const int port,
-			 const uint16_t i2c_spi_addr_flags,
-			 const uint8_t reg, int *data_ptr)
-{
-	/* Only read 1 bytes */
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_READ_ADDR, reg);
-	return bmi_read8(port, i2c_spi_addr_flags,
-			 BMI160_MAG_I2C_READ_DATA, data_ptr);
-}
-
-/**
- * Write register from compass.
- * Assuming we are in manual access mode, write to compass i2c register.
- */
-int bmi160_sec_raw_write8(const int port,
-			  const uint16_t i2c_spi_addr_flags,
-			  const uint8_t reg, int data)
-{
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_WRITE_DATA, data);
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_I2C_WRITE_ADDR, reg);
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
-{
-	int ret, normalized_rate;
-	uint8_t reg_val;
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	if (rate == 0) {
-		/* FIFO stop collecting events */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			bmi_enable_fifo(s, 0);
-
-		/* go to suspend mode */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
-				 BMI160_CMD_MODE_SUSPEND(s->type));
-		msleep(3);
-		data->odr = 0;
-		if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
-		    (s->type == MOTIONSENSE_TYPE_MAG)) {
-			struct mag_cal_t *moc = BMM150_CAL(s);
-
-			moc->batch_size = 0;
-		}
-
-		return ret;
-	} else if (data->odr == 0) {
-		/* back from suspend mode. */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
-				 BMI160_CMD_MODE_NORMAL(s->type));
-		msleep(wakeup_time[s->type]);
-	}
-
-	ret = bmi_get_normalized_rate(s, rate, rnd, &normalized_rate, &reg_val);
-	if (ret)
-		return ret;
-
-	/*
-	 * Lock accel resource to prevent another task from attempting
-	 * to write accel parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
-	if (ret != EC_SUCCESS)
-		goto accel_cleanup;
-
-	/* Now that we have set the odr, update the driver's value. */
-	data->odr = normalized_rate;
-
-	if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
-	    (s->type == MOTIONSENSE_TYPE_MAG)) {
-		struct mag_cal_t *moc = BMM150_CAL(s);
-
-		/* Reset the calibration */
-		init_mag_cal(moc);
-		/*
-		 * We need at least MIN_BATCH_SIZE amd we must have collected
-		 * for at least MIN_BATCH_WINDOW_US.
-		 * Given odr is in mHz, multiply by 1000x
-		 */
-		moc->batch_size = MAX(
-			MAG_CAL_MIN_BATCH_SIZE,
-			(data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US));
-		CPRINTS("Batch size: %d", moc->batch_size);
-	}
-
-	/*
-	 * FIFO start collecting events.
-	 * They will be discarded if AP does not want them.
-	 */
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		bmi_enable_fifo(s, 1);
-
-accel_cleanup:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	int ret, val98;
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_OFFSET_EN_GYR98, &val98);
-	if (ret != 0)
-		return ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		ret = bmi_set_accel_offset(s, v);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_OFFSET_EN_GYR98,
-				 val98 | BMI160_OFFSET_ACC_EN);
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		ret = bmi_set_gyro_offset(s, v, &val98);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_OFFSET_EN_GYR98,
-				 val98 | BMI160_OFFSET_GYRO_EN);
-		break;
-#ifdef CONFIG_MAG_BMI_BMM150
-	case MOTIONSENSE_TYPE_MAG:
-		ret = bmm150_set_offset(s, v);
-		break;
-#endif /* defined(CONFIG_MAG_BMI_BMM150) */
-	default:
-		ret = EC_RES_INVALID_PARAM;
-	}
-	return ret;
-}
-
-static int perform_calib(struct motion_sensor_t *s, int enable)
-{
-	int ret, val, en_flag, status, rate, range = s->current_range;
-	timestamp_t deadline, timeout;
-
-	if (!enable)
-		return EC_SUCCESS;
-
-	rate = bmi_get_data_rate(s);
-	/*
-	 * Temporary set frequency to 100Hz to get enough data in a short
-	 * period of time.
-	 */
-	ret = set_data_rate(s, 100000, 0);
-	if (ret != EC_SUCCESS)
-		goto end_perform_calib;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* We assume the device is laying flat for calibration */
-		if (s->rot_standard_ref == NULL ||
-		    (*s->rot_standard_ref)[2][2] > INT_TO_FP(0))
-			val = BMI160_FOC_ACC_PLUS_1G;
-		else
-			val = BMI160_FOC_ACC_MINUS_1G;
-		val = (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_X_OFFSET) |
-			(BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) |
-			(val << BMI160_FOC_ACC_Z_OFFSET);
-		en_flag = BMI160_OFFSET_ACC_EN;
-		/*
-		 * Temporary set range to minimum to run calibration with
-		 * full sensitivity
-		 */
-		bmi_set_range(s, 2, 0);
-		/* Timeout for accelerometer calibration */
-		timeout.val = 400 * MSEC;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		val = BMI160_FOC_GYRO_EN;
-		en_flag = BMI160_OFFSET_GYRO_EN;
-		/*
-		 * Temporary set range to minimum to run calibration with
-		 * full sensitivity
-		 */
-		bmi_set_range(s, 125, 0);
-		/* Timeout for gyroscope calibration */
-		timeout.val = 800 * MSEC;
-		break;
-	default:
-		/* Not supported on Magnetometer */
-		ret = EC_RES_INVALID_PARAM;
-		goto end_perform_calib;
-	}
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_FOC_CONF, val);
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_CMD_REG, BMI160_CMD_START_FOC);
-	deadline.val = get_time().val + timeout.val;
-	do {
-		if (timestamp_expired(deadline, NULL)) {
-			ret = EC_RES_TIMEOUT;
-			goto end_perform_calib;
-		}
-		msleep(50);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI160_STATUS, &status);
-		if (ret != EC_SUCCESS)
-			goto end_perform_calib;
-	} while ((status & BMI160_FOC_RDY) == 0);
-
-	/* Calibration is successful, and loaded, use the result */
-	ret = bmi_enable_reg8(s, BMI160_OFFSET_EN_GYR98, en_flag, 1);
-end_perform_calib:
-	bmi_set_range(s, range, 0);
-	set_data_rate(s, rate, 0);
-	return ret;
-}
-
-/*
- * Manage gesture recognition.
- * Defined even if host interface is not defined, to enable double tap even
- * when the host does not deal with gesture.
- */
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-static int manage_activity(const struct motion_sensor_t *s,
-			   enum motionsensor_activity activity,
-			   int enable,
-			   const struct ec_motion_sense_activity *param)
-{
-	int ret;
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-
-	switch (activity) {
-#ifdef CONFIG_GESTURE_SIGMO
-	case MOTIONSENSE_ACTIVITY_SIG_MOTION: {
-		if (enable) {
-			/* We should use parameters from caller */
-			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_3,
-				BMI160_MOTION_PROOF_TIME(
-					CONFIG_GESTURE_SIGMO_PROOF_MS) <<
-				BMI160_MOTION_PROOF_OFF |
-				BMI160_MOTION_SKIP_TIME(
-					CONFIG_GESTURE_SIGMO_SKIP_MS) <<
-				BMI160_MOTION_SKIP_OFF |
-				BMI160_MOTION_SIG_MOT_SEL);
-			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_1,
-				BMI160_MOTION_TH(s,
-					CONFIG_GESTURE_SIGMO_THRES_MG));
-		}
-		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
-				      BMI160_INT_ANYMO_X_EN |
-				      BMI160_INT_ANYMO_Y_EN |
-				      BMI160_INT_ANYMO_Z_EN,
-				      enable);
-		if (ret)
-			ret = EC_RES_UNAVAILABLE;
-		break;
-	}
-#endif
-#ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-	case MOTIONSENSE_ACTIVITY_DOUBLE_TAP: {
-		/* Set double tap interrupt */
-		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
-				      BMI160_INT_D_TAP_EN,
-				      enable);
-		if (ret)
-			ret = EC_RES_UNAVAILABLE;
-		break;
-	}
-#endif
-	default:
-		ret = EC_RES_INVALID_PARAM;
-	}
-	if (ret == EC_RES_SUCCESS) {
-		if (enable) {
-			data->enabled_activities |= 1 << activity;
-			data->disabled_activities &= ~BIT(activity);
-		} else {
-			data->enabled_activities &= ~BIT(activity);
-			data->disabled_activities |= 1 << activity;
-		}
-	}
-	return ret;
-}
-#endif
-
-static __maybe_unused int config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret, tmp;
-
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
-	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_FIFO_FLUSH);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_INT_RESET);
-
-	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_TAP_0,
-				BMI160_TAP_DUR(s, CONFIG_GESTURE_TAP_MAX_INTERSTICE_T));
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_TAP_1,
-				BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG));
-	}
-	/* only use orientation sensor on the lid sensor */
-	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
-	    (s->location == MOTIONSENSE_LOC_LID)) {
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_INT_ORIENT_0,
-				 BMI160_INT_ORIENT_0_INIT_VAL);
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_INT_ORIENT_1,
-				 BMI160_INT_ORIENT_1_INIT_VAL);
-	}
-
-	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT)) {
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_LATCH, BMI160_LATCH_5MS);
-	} else {
-		/* Also, configure int2 as an external input. */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_LATCH,
-				BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS);
-	}
-
-	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_OUT_CTRL,
-			 BMI160_INT_CTRL(1, OUTPUT_EN));
-
-	/* Map activity interrupt to int 1 */
-	tmp = 0;
-	if (IS_ENABLED(CONFIG_GESTURE_SIGMO)) {
-		tmp |= BMI160_INT_ANYMOTION;
-	} else if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
-		tmp |= BMI160_INT_D_TAP;
-	} else if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
-		   (s->location == MOTIONSENSE_LOC_LID)) {
-		/* enable orientation interrupt for lid sensor only */
-		tmp |= BMI160_INT_ORIENT;
-	}
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_MAP_REG(1), tmp);
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* map fifo water mark to int 1 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_INT_FIFO_MAP,
-				 BMI160_INT_MAP(1, FWM) |
-				 BMI160_INT_MAP(1, FFULL));
-
-		/*
-		 * Configure fifo watermark to int whenever there's any data in
-		 * there
-		 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_FIFO_CONFIG_0, 1);
-		if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT))
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI160_FIFO_CONFIG_1,
-					BMI160_FIFO_HEADER_EN);
-		else
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI160_FIFO_CONFIG_1,
-					BMI160_FIFO_TAG_INT2_EN |
-					BMI160_FIFO_HEADER_EN);
-
-		/* Set fifo*/
-		bmi_enable_reg8(s, BMI160_INT_EN_1,
-				BMI160_INT_FWM_EN | BMI160_INT_FFUL_EN, 1);
-	}
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-static void irq_set_orientation(struct motion_sensor_t *s,
-				int interrupt)
-{
-	int shifted_masked_orientation =
-		(interrupt >> 24) & BMI160_ORIENT_XY_MASK;
-	if (BMI_GET_DATA(s)->raw_orientation != shifted_masked_orientation) {
-		enum motionsensor_orientation orientation =
-			MOTIONSENSE_ORIENTATION_UNKNOWN;
-
-		BMI_GET_DATA(s)->raw_orientation =
-			shifted_masked_orientation;
-
-		switch (shifted_masked_orientation) {
-		case BMI160_ORIENT_PORTRAIT:
-			orientation = MOTIONSENSE_ORIENTATION_PORTRAIT;
-			break;
-		case BMI160_ORIENT_PORTRAIT_INVERT:
-			orientation =
-				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT;
-			break;
-		case BMI160_ORIENT_LANDSCAPE:
-			orientation = MOTIONSENSE_ORIENTATION_LANDSCAPE;
-			break;
-		case BMI160_ORIENT_LANDSCAPE_INVERT:
-			orientation =
-				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE;
-			break;
-		default:
-			break;
-		}
-		orientation = motion_orientation_remap(s, orientation);
-		*motion_orientation_ptr(s) = orientation;
-	}
-}
-#endif  /* CONFIG_BMI_ORIENTATION_SENSOR */
-
-/**
- * bmi160_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->irq_handler().
- */
-void bmi160_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI160_INT_EVENT);
-}
-
-/**
- * irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- *
- * For now, we just print out. We should set a bitmask motion sense code will
- * act upon.
- */
-static int irq_handler(struct motion_sensor_t *s,
-				      uint32_t *event)
-{
-	uint32_t interrupt;
-	int8_t has_read_fifo = 0;
-	int rv;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	do {
-		rv = bmi_read16(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_STATUS_0, &interrupt);
-		/*
-		 * Bail out of this loop there was an error reading the register
-		 */
-		if (rv)
-			return rv;
-
-		if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) &&
-		    (interrupt & BMI160_D_TAP_INT))
-			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-		if (IS_ENABLED(CONFIG_GESTURE_SIGMO) &&
-		    (interrupt & BMI160_SIGMOT_INT))
-			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_SIG_MOTION);
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-		    (interrupt & (BMI160_FWM_INT | BMI160_FFULL_INT))) {
-			bmi_load_fifo(s, last_interrupt_timestamp);
-			has_read_fifo = 1;
-		}
-		if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR))
-			irq_set_orientation(s, interrupt);
-	} while (interrupt != 0);
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
-		motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-#endif  /* CONFIG_ACCEL_INTERRUPTS */
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp, i;
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_CHIP_ID, &tmp);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	if (tmp != BMI160_CHIP_ID_MAJOR && tmp != BMI168_CHIP_ID_MAJOR) {
-		/* The device may be lock on paging mode. Try to unlock it. */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B0);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B1);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B2);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_EXT_MODE_ADDR, BMI160_CMD_PAGING_EN);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_EXT_MODE_ADDR, 0);
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-
-		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_SOFT_RESET);
-		msleep(1);
-		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
-		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
-			data->enabled_activities = 0;
-			data->disabled_activities = 0;
-			if (IS_ENABLED(CONFIG_GESTURE_SIGMO))
-				data->disabled_activities |=
-					BIT(MOTIONSENSE_ACTIVITY_SIG_MOTION);
-			if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP))
-				data->disabled_activities |=
-					BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-		}
-		/* To avoid gyro wakeup */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_PMU_TRIGGER, 0);
-	}
-
-#ifdef CONFIG_BMI_SEC_I2C
-	if (s->type == MOTIONSENSE_TYPE_MAG) {
-		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-
-		/*
-		 * To be able to configure the real magnetometer, we must set
-		 * the BMI160 magnetometer part (a pass through) in normal mode.
-		 */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_MODE_NORMAL(s->type));
-		msleep(wakeup_time[s->type]);
-
-		if ((data->flags & BMI_FLAG_SEC_I2C_ENABLED) == 0) {
-			int ext_page_reg;
-			/* Enable secondary interface */
-			/*
-			 * This is not part of the normal configuration but from
-			 * code on Bosh github repo:
-			 * https://github.com/BoschSensortec/BMI160_driver
-			 *
-			 * Magic command sequences
-			 */
-			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B0);
-			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B1);
-			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B2);
-
-			/*
-			 * Change the register page to target mode, to change
-			 * the internal pull ups of the secondary interface.
-			 */
-			bmi_enable_reg8(s, BMI160_CMD_EXT_MODE_ADDR,
-					BMI160_CMD_TARGET_PAGE, 1);
-			bmi_enable_reg8(s, BMI160_CMD_EXT_MODE_ADDR,
-					BMI160_CMD_PAGING_EN, 1);
-			bmi_enable_reg8(s, BMI160_COM_C_TRIM_ADDR,
-					BMI160_COM_C_TRIM, 1);
-			bmi_enable_reg8(s, BMI160_CMD_EXT_MODE_ADDR,
-					BMI160_CMD_TARGET_PAGE, 0);
-			bmi_read8(s->port, s->i2c_spi_addr_flags,
-				  BMI160_CMD_EXT_MODE_ADDR, &ext_page_reg);
-
-			/* Set the i2c address of the compass */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_MAG_IF_0,
-					 I2C_STRIP_FLAGS(
-					     CONFIG_ACCELGYRO_SEC_ADDR_FLAGS)
-					 << 1);
-
-			/* Enable the secondary interface as I2C */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_IF_CONF,
-					 BMI160_IF_MODE_AUTO_I2C <<
-					     BMI160_IF_MODE_OFF);
-			data->flags |= BMI_FLAG_SEC_I2C_ENABLED;
-		}
-
-
-		bmi160_sec_access_ctrl(s->port, s->i2c_spi_addr_flags, 1);
-
-		ret = bmm150_init(s);
-		if (ret)
-			/* Leave the compass open for tinkering. */
-			return ret;
-
-		/* Leave the address for reading the data */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_MAG_I2C_READ_ADDR, BMM150_BASE_DATA);
-		/*
-		 * Put back the secondary interface in normal mode.
-		 * BMI160 will poll based on the configure ODR.
-		 */
-		bmi160_sec_access_ctrl(s->port, s->i2c_spi_addr_flags, 0);
-
-		/*
-		 * Clean interrupt event that may have occurred while the
-		 * BMI160 was in management mode.
-		 */
-		task_set_event(TASK_ID_MOTIONSENSE,
-			       CONFIG_ACCELGYRO_BMI160_INT_EVENT);
-	}
-#endif
-
-	for (i = X; i <= Z; i++)
-		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
-	/*
-	 * The sensor is in Suspend mode at init,
-	 * so set data rate to 0.
-	 */
-	saved_data->odr = 0;
-
-	if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS) &&
-	    (s->type == MOTIONSENSE_TYPE_ACCEL))
-		ret = config_interrupt(s);
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv bmi160_drv = {
-	.init = init,
-	.read = bmi_read,
-	.set_range = bmi_set_range,
-	.get_resolution = bmi_get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = bmi_get_data_rate,
-	.set_offset = set_offset,
-	.get_scale = bmi_get_scale,
-	.set_scale = bmi_set_scale,
-	.get_offset = bmi_get_offset,
-	.perform_calib = perform_calib,
-	.read_temp = bmi_read_temp,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = irq_handler,
-#endif
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-	.manage_activity = manage_activity,
-	.list_activities = bmi_list_activities,
-#endif
-#ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
-#endif
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-struct i2c_stress_test_dev bmi160_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = BMI160_CHIP_ID,
-		.read_val = BMI160_CHIP_ID_MAJOR,
-		.write_reg = BMI160_PMU_TRIGGER,
-	},
-	.i2c_read = &bmi_read8,
-	.i2c_write = &bmi_write8,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_ACCEL */
-
-/*
- * TODO(chingkang): Replace bmi160_get_sensor_temp in some board config to
- *                  bmi_get_sensor_temp. Then, remove this definition.
- */
-int bmi160_get_sensor_temp(int idx, int *temp_ptr)
-{
-	return bmi_get_sensor_temp(idx, temp_ptr);
-}
diff --git a/driver/accelgyro_bmi260.c b/driver/accelgyro_bmi260.c
deleted file mode 100644
index 9fb669e122..0000000000
--- a/driver/accelgyro_bmi260.c
+++ /dev/null
@@ -1,601 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * BMI260 accelerometer and gyro module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "console.h"
-#include "accelgyro_bmi_common.h"
-#include "accelgyro_bmi260.h"
-#include "bmi260/accelgyro_bmi260_config_tbin.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "init_rom.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#if defined(CONFIG_ZEPHYR) && defined(CONFIG_ACCEL_INTERRUPTS)
-/*
- * Get the mostion sensor ID of the BMI260 sensor that
- * generates the interrupt.
- * The interrupt is converted to the event and transferred to motion
- * sense task that actually handles the interrupt.
- *
- * Here, we use alias to get the motion sensor ID
- *
- * e.g) base_accel is the label of a child node in /motionsense-sensors
- * aliases {
- *     bmi260-int = &base_accel;
- * };
- */
-#if DT_NODE_EXISTS(DT_ALIAS(bmi260_int))
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
-#endif
-#endif
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-/*
- * The gyro start-up time is 45ms in normal mode
- *                            2ms in fast start-up mode
- */
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 2,
-	[MOTIONSENSE_TYPE_GYRO] = 45,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
-
-static int enable_sensor(const struct motion_sensor_t *s, int enable)
-{
-	int ret;
-
-	ret = bmi_enable_reg8(s, BMI260_PWR_CTRL,
-			      BMI260_PWR_EN(s->type),
-			      enable);
-	if (ret)
-		return ret;
-
-	if (s->type == MOTIONSENSE_TYPE_GYRO) {
-		/* switch to performance mode */
-		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF |
-				      BMI260_GYR_NOISE_PERF,
-				      enable);
-	} else {
-		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF,
-				      enable);
-	}
-	return ret;
-
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-			 int rate,
-			 int rnd)
-{
-	int ret, normalized_rate;
-	uint8_t reg_val;
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	if (rate == 0) {
-		/* FIFO stop collecting events */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			bmi_enable_fifo(s, 0);
-		/* disable sensor */
-		ret = enable_sensor(s, 0);
-		msleep(3);
-		data->odr = 0;
-		return ret;
-	} else if (data->odr == 0) {
-		/* enable sensor */
-		ret = enable_sensor(s, 1);
-		if (ret)
-			return ret;
-		/* Wait for accel/gyro to wake up */
-		msleep(wakeup_time[s->type]);
-	}
-
-	ret = bmi_get_normalized_rate(s, rate, rnd,
-				      &normalized_rate, &reg_val);
-	if (ret)
-		return ret;
-
-	/*
-	 * Lock accel resource to prevent another task from attempting
-	 * to write accel parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
-	if (ret != EC_SUCCESS)
-		goto accel_cleanup;
-
-	/* Now that we have set the odr, update the driver's value. */
-	data->odr = normalized_rate;
-
-	/*
-	 * FIFO start collecting events.
-	 * They will be discarded if AP does not want them.
-	 */
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		bmi_enable_fifo(s, 1);
-accel_cleanup:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	int ret, val98, val_nv_conf;
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_OFFSET_EN_GYR98, &val98);
-	if (ret)
-		return ret;
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_NV_CONF, &val_nv_conf);
-	if (ret)
-		return ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		ret = bmi_set_accel_offset(s, v);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_NV_CONF,
-				 val_nv_conf | BMI260_ACC_OFFSET_EN);
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		ret = bmi_set_gyro_offset(s, v, &val98);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_OFFSET_EN_GYR98,
-				 val98 | BMI260_OFFSET_GYRO_EN);
-		break;
-	default:
-		ret = EC_RES_INVALID_PARAM;
-	}
-	return ret;
-}
-
-static int wait_and_read_data(const struct motion_sensor_t *s,
-			      intv3_t v, int try_cnt, int msec)
-{
-	uint8_t data[6];
-	int ret, status = 0;
-
-	/* Check if data is ready */
-	while (try_cnt && !(status & BMI260_DRDY_ACC)) {
-		msleep(msec);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI260_STATUS, &status);
-		if (ret)
-			return ret;
-		try_cnt -= 1;
-	}
-	if (!(status & BMI260_DRDY_ACC))
-		return EC_ERROR_TIMEOUT;
-	/* Read 6 bytes starting at xyz_reg */
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 bmi_get_xyz_reg(s), data, 6);
-	bmi_normalize(s, v, data);
-	return ret;
-}
-
-static int calibrate_offset(const struct motion_sensor_t *s,
-			    int range, intv3_t target, int16_t *offset)
-{
-	int ret = EC_ERROR_UNKNOWN;
-	int i, n_sample = 32;
-	int data_diff[3] = {0};
-
-	/* Manually offset compensation */
-	for (i = 0; i < n_sample; ++i) {
-		intv3_t v;
-		/* Wait data for at most 3 * 10 msec */
-		ret = wait_and_read_data(s, v, 3, 10);
-		if (ret)
-			return ret;
-		data_diff[X] += v[X] - target[X];
-		data_diff[Y] += v[Y] - target[Y];
-		data_diff[Z] += v[Z] - target[Z];
-	}
-
-	/* The data LSB: 1000 * range / 32768 (mdps | mg)*/
-	for (i = X; i <= Z; ++i)
-		offset[i] -= ((int64_t)(data_diff[i] / n_sample) *
-			     1000 * range) >> 15;
-	return ret;
-}
-
-static int perform_calib(struct motion_sensor_t *s, int enable)
-{
-	int ret, rate;
-	int16_t temp;
-	int16_t offset[3];
-	intv3_t target = {0, 0, 0};
-	/* Get sensor range for calibration*/
-	int range = s->current_range;
-
-	if (!enable)
-		return EC_SUCCESS;
-	rate = bmi_get_data_rate(s);
-	ret = set_data_rate(s, 100000, 0);
-	if (ret)
-		return ret;
-
-	ret = bmi_get_offset(s, offset, &temp);
-	if (ret)
-		goto end_perform_calib;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		target[Z] = BMI260_ACC_DATA_PLUS_1G(range);
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		break;
-	default:
-		/* Not supported on Magnetometer */
-		ret = EC_RES_INVALID_PARAM;
-		goto end_perform_calib;
-	}
-
-	/* Get the calibrated offset */
-	ret = calibrate_offset(s, range, target, offset);
-	if (ret)
-		goto end_perform_calib;
-
-	ret = set_offset(s, offset, temp);
-	if (ret)
-		goto end_perform_calib;
-
-end_perform_calib:
-	if (ret == EC_ERROR_TIMEOUT)
-		CPRINTS("%s timeout", __func__);
-	set_data_rate(s, rate, 0);
-	return ret;
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
-/**
- * bmi260_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->irq_handler().
- */
-void bmi260_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI260_INT_EVENT);
-}
-
-static int config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret;
-
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
-	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI260_CMD_REG, BMI260_CMD_FIFO_FLUSH);
-
-	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT1_IO_CTRL,
-			 BMI260_INT1_OUTPUT_EN);
-	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
-		/* TODO(chingkang): Test it if we want int2 as an interrupt */
-		/* configure int2 as an interrupt */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI260_INT2_IO_CTRL,
-				BMI260_INT2_OUTPUT_EN);
-	else
-		/* configure int2 as an external input. */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI260_INT2_IO_CTRL,
-				BMI260_INT2_INPUT_EN);
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* map fifo water mark to int 1 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_INT_MAP_DATA,
-				 BMI260_INT_MAP_DATA_REG(1, FWM) |
-				 BMI260_INT_MAP_DATA_REG(1, FFULL));
-
-		/*
-		 * Configure fifo watermark to int whenever there's any data in
-		 * there
-		 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_WTM_0, 1);
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_WTM_1, 0);
-		if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI260_FIFO_CONFIG_1,
-					BMI260_FIFO_HEADER_EN);
-		else
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI260_FIFO_CONFIG_1,
-					(BMI260_FIFO_TAG_INT_LEVEL <<
-					 BMI260_FIFO_TAG_INT2_EN_OFFSET) |
-					BMI260_FIFO_HEADER_EN);
-		/* disable FIFO sensortime frame */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_CONFIG_0, 0);
-	}
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-/**
- * irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- *
- * For now, we just print out. We should set a bitmask motion sense code will
- * act upon.
- */
-static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	/* use uint16_t interrupt can cause error. */
-	uint32_t interrupt = 0;
-	int8_t has_read_fifo = 0;
-	int rv;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	do {
-		rv = bmi_read16(s->port, s->i2c_spi_addr_flags,
-				BMI260_INT_STATUS_0, &interrupt);
-		/*
-		 * Bail out of this loop there was an error reading the register
-		 */
-		if (rv)
-			return rv;
-
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO) &&
-			interrupt & (BMI260_FWM_INT | BMI260_FFULL_INT)) {
-			bmi_load_fifo(s, last_interrupt_timestamp);
-			has_read_fifo = 1;
-		}
-	} while (interrupt != 0);
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
-		motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-#endif  /* CONFIG_ACCEL_INTERRUPTS */
-
-/*
- * If the .init_rom section is not memory mapped, we need a static
- * buffer in RAM to access the BMI configuration data.
- */
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-#define BMI_RAM_BUFFER_SIZE		256
-static uint8_t bmi_ram_buffer[BMI_RAM_BUFFER_SIZE];
-#else
-#define BMI_RAM_BUFFER_SIZE		0
-static uint8_t *bmi_ram_buffer;
-#endif
-
-static int bmi_config_load(const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-	uint16_t i;
-	const uint8_t *bmi_config = NULL;
-	/*
-	 * Due to i2c transaction timeout limit,
-	 * burst_write_len should not be above 2048 to prevent timeout.
-	 */
-	int burst_write_len = 2048;
-
-	/*
-	 * The BMI config data may be linked into .rodata or the .init_rom
-	 * section. Get the actual memory mapped address.
-	 */
-	bmi_config = init_rom_map(g_bmi260_config_tbin,
-				  g_bmi260_config_tbin_len);
-
-	/*
-	 * init_rom_map() only returns NULL when the CONFIG_CHIP_INIT_ROM_REGION
-	 * option is enabled and flash memory is not memory mapped.  In this
-	 * case copy the BMI config data through a RAM buffer and limit the
-	 * I2C burst to the size of the RAM buffer.
-	 */
-	if (!bmi_config)
-		burst_write_len = MIN(BMI_RAM_BUFFER_SIZE, burst_write_len);
-
-	/* We have to write the config even bytes of data every time */
-	ASSERT(((burst_write_len & 1) == 0) && (burst_write_len != 0));
-
-	for (i = 0; i < g_bmi260_config_tbin_len; i += burst_write_len) {
-		uint8_t addr[2];
-		const int len = MIN(burst_write_len,
-				    g_bmi260_config_tbin_len - i);
-
-		addr[0] = (i / 2) & 0xF;
-		addr[1] = (i / 2) >> 4;
-		ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-				  BMI260_INIT_ADDR_0, addr, 2);
-		if (ret)
-			break;
-
-		if (!bmi_config) {
-			/*
-			 * init_rom region isn't memory mapped. Copy the
-			 * data through a RAM buffer.
-			 */
-			ret = init_rom_copy((int)&g_bmi260_config_tbin[i], len,
-				bmi_ram_buffer);
-			if (ret)
-				break;
-
-			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  bmi_ram_buffer, len);
-		} else {
-			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  &bmi_config[i], len);
-		}
-
-		if (ret)
-			break;
-	}
-
-	/*
-	 * Unmap the BMI config data, required when init_rom_map() returns
-	 * a non NULL value.
-	 */
-	if (bmi_config)
-		init_rom_unmap(g_bmi260_config_tbin, g_bmi260_config_tbin_len);
-
-	return ret;
-}
-
-static int init_config(const struct motion_sensor_t *s)
-{
-	int init_status, ret;
-	uint16_t i;
-
-	/* disable advance power save but remain fifo self wakeup*/
-	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_PWR_CONF, 2);
-	msleep(1);
-	/* prepare for config load */
-	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INIT_CTRL, 0);
-
-	/* load config file to INIT_DATA */
-	ret = bmi_config_load(s);
-
-	/* finish config load */
-	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INIT_CTRL, 1);
-	/* return error if load config failed */
-	if (ret)
-		return ret;
-	/* wait INTERNAL_STATUS.message to be 0x1 which take at most 150ms */
-	for (i = 0; i < 15; ++i) {
-		msleep(10);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_INTERNAL_STATUS, &init_status);
-		if (ret)
-			break;
-		init_status &= BMI260_MESSAGE_MASK;
-		if (init_status == BMI260_INIT_OK)
-			break;
-	}
-	if (ret || init_status != BMI260_INIT_OK)
-		return EC_ERROR_INVALID_CONFIG;
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp, i;
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_CHIP_ID, &tmp);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	if (tmp != BMI260_CHIP_ID_MAJOR)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-
-		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_CMD_REG, BMI260_CMD_SOFT_RESET);
-		msleep(2);
-		if (init_config(s))
-			return EC_ERROR_INVALID_CONFIG;
-
-		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
-	}
-
-	for (i = X; i <= Z; i++)
-		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
-	/*
-	 * The sensor is in Suspend mode at init,
-	 * so set data rate to 0.
-	 */
-	saved_data->odr = 0;
-
-	if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS) &&
-	    (s->type == MOTIONSENSE_TYPE_ACCEL))
-		ret = config_interrupt(s);
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv bmi260_drv = {
-	.init = init,
-	.read = bmi_read,
-	.set_range = bmi_set_range,
-	.get_resolution = bmi_get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = bmi_get_data_rate,
-	.set_offset = set_offset,
-	.get_scale = bmi_get_scale,
-	.set_scale = bmi_set_scale,
-	.get_offset = bmi_get_offset,
-	.perform_calib = perform_calib,
-	.read_temp = bmi_read_temp,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = irq_handler,
-#endif
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-	.list_activities = bmi_list_activities,
-#endif
-#ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
-#endif
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-struct i2c_stress_test_dev bmi260_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = BMI260_CHIP_ID,
-		.read_val = BMI260_CHIP_ID_MAJOR,
-		.write_reg = BMI260_PMU_TRIGGER,
-	},
-	.i2c_read = &bmi_read8,
-	.i2c_write = &bmi_write8,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_ACCEL */
diff --git a/driver/accelgyro_bmi323.h b/driver/accelgyro_bmi323.h
deleted file mode 100644
index 544e9a4527..0000000000
--- a/driver/accelgyro_bmi323.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI323 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI323_H
-#define __CROS_EC_ACCELGYRO_BMI323_H
-
-#include "accelgyro_bmi3xx.h"
-
-#define BMI323_CHIP_ID			0x43
-
-#endif /* __CROS_EC_ACCELGYRO_BMI323_H */
diff --git a/driver/accelgyro_bmi3xx.c b/driver/accelgyro_bmi3xx.c
deleted file mode 100644
index ee9b30a9cf..0000000000
--- a/driver/accelgyro_bmi3xx.c
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * BMI3XX accelerometer and gyroscope module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "accelgyro_bmi323.h"
-#include "accelgyro_bmi_common.h"
-#include "console.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "init_rom.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-/* Sensor definition */
-STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) void irq_set_orientation(
-						struct motion_sensor_t *s);
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-static inline int bmi3_read_n(const struct motion_sensor_t *s, const int reg,
-			      uint8_t *data_ptr, const int len)
-{
-	return bmi_read_n(s->port, s->i2c_spi_addr_flags, reg, data_ptr, len);
-}
-
-static inline int bmi3_write_n(const struct motion_sensor_t *s, const int reg,
-			       uint8_t *data_ptr, const int len)
-{
-	return bmi_write_n(s->port, s->i2c_spi_addr_flags, reg, data_ptr, len);
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-
-static void irq_set_orientation(struct motion_sensor_t *s)
-{
-	int ret;
-	uint8_t reg_data[4];
-	uint8_t orient_data;
-
-	enum motionsensor_orientation orientation =
-					MOTIONSENSE_ORIENTATION_UNKNOWN;
-
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_EVENT_EXT, reg_data, 4));
-
-	orient_data = reg_data[2] & BMI3_PORTRAIT_LANDSCAPE_MASK;
-
-	if (BMI_GET_DATA(s)->raw_orientation != orient_data) {
-		BMI_GET_DATA(s)->raw_orientation = orient_data;
-
-		switch (orient_data) {
-		case BMI3_ORIENT_PORTRAIT:
-			orientation = MOTIONSENSE_ORIENTATION_PORTRAIT;
-			break;
-		case BMI3_PORTRAIT_INVERT:
-			orientation =
-				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT;
-			break;
-		case BMI3_LANDSCAPE:
-			orientation = MOTIONSENSE_ORIENTATION_LANDSCAPE;
-			break;
-		case BMI3_LANDSCAPE_INVERT:
-			orientation =
-				MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE;
-			break;
-		default:
-			break;
-		}
-
-		orientation = motion_orientation_remap(s, orientation);
-		*motion_orientation_ptr(s) = orientation;
-	}
-}
-
-#endif  /* CONFIG_BMI_ORIENTATION_SENSOR */
-
-/*
- * bmi3xx_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->irq_handler().
- */
-void bmi3xx_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCELGYRO_BMI3XX_INT_EVENT);
-}
-
-static int enable_fifo(const struct motion_sensor_t *s, int enable)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	/* Set FIFO config to enable accel gyro data */
-	uint8_t reg_data[4];
-
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_CONF, reg_data, 4));
-
-	if (enable) {
-		if (s->type == MOTIONSENSE_TYPE_ACCEL)
-			reg_data[3] |= BMI3_FIFO_ACC_EN;
-		else
-			reg_data[3] |=  BMI3_FIFO_GYR_EN;
-
-		data->flags |= 1 << (s->type + BMI_FIFO_FLAG_OFFSET);
-	} else {
-		if (s->type == MOTIONSENSE_TYPE_ACCEL)
-			reg_data[3] &= ~BMI3_FIFO_ACC_EN;
-		else
-			reg_data[3] &=  ~BMI3_FIFO_GYR_EN;
-
-		data->flags &= ~(1 << (s->type + BMI_FIFO_FLAG_OFFSET));
-	}
-
-	return bmi3_write_n(s, BMI3_REG_FIFO_CONF, &reg_data[2], 2);
-}
-
-static int config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret;
-	uint8_t reg_data[6] = {0};
-
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
-	mutex_lock(s->mutex);
-
-	/* Clear the FIFO using Flush command */
-	reg_data[0] = BMI3_ENABLE;
-	reg_data[1] = 0;
-	ret = bmi3_write_n(s, BMI3_REG_FIFO_CTRL, reg_data, 2);
-	if (ret)
-		goto err_unlock;
-
-	/* Map FIFO water-mark and FIFO full to INT1 pin */
-	ret = bmi3_read_n(s, BMI3_REG_INT_MAP1, reg_data, 6);
-	if (ret)
-		goto err_unlock;
-
-	reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FWM_INT, BMI3_INT1);
-	reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FFULL_INT, BMI3_INT1);
-	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) {
-		/* Map orientation to INT1 pin */
-		reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT,
-						BMI3_INT1);
-	}
-
-	ret = bmi3_write_n(s, BMI3_REG_INT_MAP1, &reg_data[2], 4);
-	if (ret)
-		goto err_unlock;
-
-	/* Set FIFO water-mark to read data whenever available */
-	reg_data[0] = BMI3_FIFO_ENTRY;
-	reg_data[1] = 0;
-
-	ret = bmi3_write_n(s, BMI3_REG_FIFO_WATERMARK, reg_data, 2);
-	if (ret)
-		goto err_unlock;
-
-	/* Get the previous configuration data */
-	ret = bmi3_read_n(s, BMI3_REG_IO_INT_CTRL, reg_data, 4);
-	if (ret)
-		goto err_unlock;
-
-	reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_INT1_LVL,
-					BMI3_INT_ACTIVE_LOW);
-
-	reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD,
-				    BMI3_INT_PUSH_PULL);
-
-	reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OUTPUT_EN,
-				    BMI3_INT_OUTPUT_ENABLE);
-
-	/*
-	 * Set the interrupt pin configurations
-	 */
-	ret = bmi3_write_n(s, BMI3_REG_IO_INT_CTRL, &reg_data[2], 2);
-	if (ret)
-		goto err_unlock;
-
-	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) {
-		/* Enable the orientation feature in BMI3 */
-		ret = bmi3_read_n(s, BMI3_FEATURE_IO_0, reg_data, 4);
-		if (ret)
-			goto err_unlock;
-
-		reg_data[2] |= BMI3_ANY_MOTION_X_EN_MASK;
-		ret = bmi3_write_n(s, BMI3_FEATURE_IO_0, &reg_data[2], 2);
-		if (ret)
-			goto err_unlock;
-
-		/* Write to feature engine */
-		reg_data[0] = 1;
-		reg_data[1] = 0;
-		ret = bmi3_write_n(s, BMI3_FEATURE_IO_STATUS, reg_data, 2);
-	}
-
-err_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static void bmi3_parse_fifo_data(struct motion_sensor_t *s,
-				 struct bmi3_fifo_frame *fifo_frame,
-				 uint32_t last_ts)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	struct ec_response_motion_sensor_data vect;
-	uint16_t reg_data;
-	intv3_t v;
-	int i;
-
-	/* Start index for FIFO parsing after I2C sync word removal */
-	size_t fifo_index = 1;
-
-	/* Variable to store I2C sync data which will get in FIFO data */
-	uint16_t i2c_sync_data, fifo_size;
-
-	if (!(data->flags & (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET))) {
-		/*
-		 * The FIFO was disabled while we were processing it
-		 * Flush potential left over:
-		 * When sensor is resumed, we won't read old data.
-		 */
-
-		/* Clear the FIFO using Flush command */
-		reg_data = BMI3_ENABLE;
-		bmi3_write_n(s, BMI3_REG_FIFO_CTRL, (uint8_t *)&reg_data, 2);
-		return;
-	}
-
-	/* Parse the length of data read excluding I2C sync word */
-	fifo_size = fifo_frame->available_fifo_len - 1;
-
-	while (fifo_size > 0) {
-		for (i = 0; i < NUM_OF_PRIMARY_SENSOR; i++) {
-			struct motion_sensor_t *sens_output = s + i;
-
-			if (data->flags & BIT(i + BMI_FIFO_FLAG_OFFSET)) {
-				/*
-				 * In-case of FIFO read fail it has only
-				 * 0x8000.
-				 */
-				if (fifo_frame->data[fifo_index] == 0x8000)
-					break;
-
-				/*
-				 * In case the frame has been cut, FIFO was
-				 * greater than our buffer.
-				 */
-				if (fifo_size < BMI3_FIFO_ENTRY)
-					break;
-
-				/* Frame is complete, but may have no data. */
-				fifo_size -= BMI3_FIFO_ENTRY;
-				i2c_sync_data = fifo_frame->data[fifo_index++];
-				if (i2c_sync_data ==
-				    BMI3_FIFO_ACCEL_I2C_SYNC_FRAME + i) {
-					fifo_index += 2;
-					continue;
-				}
-
-				v[X] = i2c_sync_data;
-				v[Y] = fifo_frame->data[fifo_index++];
-				v[Z] = fifo_frame->data[fifo_index++];
-
-				rotate(v, *sens_output->rot_standard_ref, v);
-
-				vect.data[X] = v[X];
-				vect.data[Y] = v[Y];
-				vect.data[Z] = v[Z];
-				vect.flags = 0;
-				vect.sensor_num = sens_output - motion_sensors;
-				motion_sense_fifo_stage_data(&vect,
-						sens_output, 3, last_ts);
-			}
-		}
-	}
-}
-
-/*
- * irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- *
- * For now, we just print out. We should set a bitmask motion sense code will
- * act upon.
- */
-static int irq_handler(struct motion_sensor_t *s,
-		uint32_t *event)
-{
-	bool has_read_fifo = false;
-	uint16_t int_status[2];
-	uint16_t reg_data[2];
-	struct bmi3_fifo_frame fifo_frame;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCELGYRO_BMI3XX_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	/* Get the interrupt status */
-	do {
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_INT_STATUS_INT1,
-					 (uint8_t *)int_status, 4));
-
-		if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
-		    (BMI3_INT_STATUS_ORIENTATION & int_status[1]))
-			irq_set_orientation(s);
-
-		if ((int_status[1] &
-		    (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0)
-			break;
-
-		/* Get the FIFO fill level in words */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_FILL_LVL,
-					 (uint8_t *)reg_data, 4));
-
-		reg_data[1] = BMI3_GET_BIT_POS0(reg_data[1],
-						BMI3_FIFO_FILL_LVL);
-
-		/* Add space for the initial 16bit read. */
-		fifo_frame.available_fifo_len = reg_data[1] + 1;
-
-		/*
-		 * If fill level is greater than buffer size then wrap it to
-		 * buffer size.
-		 */
-		if (fifo_frame.available_fifo_len > ARRAY_SIZE(fifo_frame.data))
-			CPRINTS("unexpected large FIFO: %d",
-					fifo_frame.available_fifo_len);
-
-		fifo_frame.available_fifo_len =
-			MIN(fifo_frame.available_fifo_len,
-					ARRAY_SIZE(fifo_frame.data));
-		/* Read FIFO data */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_DATA,
-					 (uint8_t *)fifo_frame.data,
-					 fifo_frame.available_fifo_len *
-					 sizeof(uint16_t)));
-
-		bmi3_parse_fifo_data(s, &fifo_frame, last_interrupt_timestamp);
-		has_read_fifo = true;
-	} while (true);
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO) && has_read_fifo)
-		motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_ACCEL_INTERRUPTS */
-
-static int read_temp(const struct motion_sensor_t *s, int *temp_ptr)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int get_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
-{
-	int i;
-	uint8_t reg_data[14] = { 0 };
-
-	/* Get the accel offset values */
-	RETURN_ERROR(bmi3_read_n(s, GYR_DP_OFF_X, reg_data, 14));
-
-	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x03FF;
-	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x03FF;
-	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x03FF;
-
-	for (i = X; i <= Z; ++i) {
-		if (v[i] > 0x01FF)
-			v[i] = -1024 + v[i];
-
-		v[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_MULTI_MDS,
-				    BMI_OFFSET_GYRO_DIV_MDS);
-	}
-
-	return EC_SUCCESS;
-}
-
-int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t reg_data[6] = { 0 };
-	uint8_t base_addr[2] = { BMI3_GYRO_OFFSET_ADDR, 0 };
-	int i, val[3];
-
-	for (i = X; i <= Z; ++i) {
-		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
-					BMI_OFFSET_GYRO_MULTI_MDS);
-		if (val[i] > 511)
-			val[i] = 511;
-		if (val[i] < -512)
-			val[i] = -512;
-		if (val[i] < 0)
-			val[i] = 1024 + val[i];
-	}
-
-	/*
-	 * Set the user accel offset base address to feature engine
-	 * transmission address to start DMA transaction
-	 */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
-
-	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((val[0] & 0x0300) >> 8);
-	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
-	reg_data[3] = (uint8_t)((val[1] & 0x0300) >> 8);
-	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
-	reg_data[5] = (uint8_t)((val[2] & 0x0300) >> 8);
-
-	/* Set the configuration to the feature engine register */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data,
-			6));
-
-	/* Update the offset to the sensor engine */
-	reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				BMI3_SET_HIGH_BYTE) >> 8);
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	return EC_SUCCESS;
-}
-
-int get_accel_offset(const struct motion_sensor_t *s, intv3_t v)
-{
-	int i;
-	uint8_t reg_data[14] = { 0 };
-
-	/* Get the accel offset values from user registers */
-	RETURN_ERROR(bmi3_read_n(s, ACC_DP_OFF_X, reg_data, 14));
-
-	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x1FFF;
-	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x1FFF;
-	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x1FFF;
-
-	for (i = X; i <= Z; ++i) {
-		if (v[i] > 0x0FFF)
-			v[i] = -8192 + v[i];
-
-		v[i] = round_divide((int64_t)v[i] * BMI3_OFFSET_ACC_MULTI_MG,
-				    BMI_OFFSET_ACC_DIV_MG);
-	}
-
-	return EC_SUCCESS;
-}
-
-int set_accel_offset(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t reg_data[6] = { 0 };
-	uint8_t base_addr[2] = { BMI3_ACC_OFFSET_ADDR, 0 };
-	uint8_t saved_conf[6] = { 0 };
-	int i, val[3];
-
-	for (i = X; i <= Z; ++i) {
-		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
-				      BMI3_OFFSET_ACC_MULTI_MG);
-		if (val[i] > 4095)
-			val[i] = 4095;
-		if (val[i] < -4096)
-			val[i] = -4096;
-		if (val[i] < 0)
-			val[i] += 8192;
-	}
-
-	/* Set the power mode as suspend */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
-
-	/* Ignore two i2c sync bytes and store consecutive bytes in reg_data */
-	reg_data[0] = saved_conf[2];
-	reg_data[1] = 0x00;
-	reg_data[2] = saved_conf[4];
-	reg_data[3] = 0x00;
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, reg_data, 4));
-
-	/*
-	 * Set the user accel offset base address to feature engine
-	 * transmission address to start DMA transaction
-	 */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
-
-	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((val[0] & 0x1F00) >> 8);
-	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
-	reg_data[3] = (uint8_t)((val[1] & 0x1F00) >> 8);
-	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
-	reg_data[5] = (uint8_t)((val[2] & 0x1F00) >> 8);
-
-	/* Set the configuration to the feature engine register */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data,
-				  6));
-
-	/* Restore ACC_CONF by storing saved_conf data */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
-
-	/* Update the offset to the sensor engine */
-	reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				BMI3_SET_LOW_BYTE);
-
-	reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_HIGH_BYTE) >> 8);
-
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	return EC_SUCCESS;
-}
-
-static int wait_and_read_data(const struct motion_sensor_t *s,
-			      intv3_t accel_data)
-{
-	uint8_t reg_data[8] = {0};
-
-	/* Retry 5 times */
-	uint8_t try_cnt = FOC_TRY_COUNT;
-
-	/* Check if data is ready */
-	while (try_cnt && (!(reg_data[2] & BMI3_STAT_DATA_RDY_ACCEL_MSK))) {
-		/* 20ms delay for 50Hz ODR */
-		msleep(FOC_DELAY);
-
-		/* Read the status register */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_STATUS, reg_data, 4));
-		try_cnt--;
-	}
-
-	if (!(reg_data[2] & BMI3_STAT_DATA_RDY_ACCEL_MSK))
-		return EC_ERROR_TIMEOUT;
-
-	/* Read the sensor data */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_DATA_X, reg_data, 8));
-
-	accel_data[0] = ((int16_t)((reg_data[3] << 8) | reg_data[2]));
-	accel_data[1] = ((int16_t)((reg_data[5] << 8) | reg_data[4]));
-	accel_data[2] = ((int16_t)((reg_data[7] << 8) | reg_data[6]));
-
-	rotate(accel_data, *s->rot_standard_ref, accel_data);
-
-	return EC_SUCCESS;
-}
-
-/*!
- * @brief This internal API performs Fast Offset Compensation for accelerometer.
- */
-static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
-				int sens_range)
-{
-	intv3_t accel_data, offset;
-	int32_t delta_value[3] = {0, 0, 0};
-
-	/* Variable to define count */
-	uint8_t i, loop, sample_count = 0;
-
-	for (loop = 0; loop < BMI3_FOC_SAMPLE_LIMIT; loop++) {
-
-		RETURN_ERROR(wait_and_read_data(s, accel_data));
-
-		sample_count++;
-
-		/* Store the data in a temporary structure */
-		delta_value[0] += accel_data[0] - target[X];
-		delta_value[1] += accel_data[1] - target[Y];
-		delta_value[2] += accel_data[2] - target[Z];
-	}
-
-	/* The data is in LSB so -> [(LSB)*1000*range/2^15] (mdps | mg) */
-	for (i = X; i <= Z; ++i) {
-		offset[i] = (((int64_t)(delta_value[i] * 1000 * sens_range
-			     / sample_count) >> 15) * -1);
-	}
-
-	rotate_inv(offset, *s->rot_standard_ref, offset);
-
-	RETURN_ERROR(set_accel_offset(s, offset));
-
-	return EC_SUCCESS;
-}
-
-static int set_gyro_foc_config(struct motion_sensor_t *s)
-{
-	uint8_t reg_data[4] = { 0 };
-	uint8_t base_addr[2] = { BMI3_BASE_ADDR_SC, 0 };
-
-	/*
-	 * Set the user accel offset base address to feature engine
-	 * transmission address to start DMA transaction
-	 */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
-
-	/* Read the configuration from the feature engine register */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data,
-			4));
-	/* Enable self calibration */
-	reg_data[2] |= 0x07;
-
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
-
-	/* Set the configuration to the feature engine register */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-			&reg_data[2], 2));
-
-	/* Trigger bmi3 gyro self calibration */
-	reg_data[0] = (uint8_t)(BMI3_CMD_SELF_CALIB & BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE)
-				>> 8);
-
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	return EC_SUCCESS;
-}
-
-static int get_calib_result(struct motion_sensor_t *s)
-{
-	uint8_t i, reg_data[4];
-
-	for (i = 0; i < 25; i++) {
-		/* A delay of 120ms is required to read this status register */
-		msleep(120);
-
-		/* Read the configuration from the feature engine register */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
-
-		switch (s->type) {
-		case MOTIONSENSE_TYPE_ACCEL:
-			if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE)
-			    && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK)
-			    == BMI3_FEATURE_IO_1_NO_ERROR)) {
-				return EC_SUCCESS;
-			}
-			break;
-		case MOTIONSENSE_TYPE_GYRO:
-			if (reg_data[2] & BMI3_SC_ST_STATUS_MASK) {
-				/* Check calibration result */
-				if (reg_data[2] & BMI3_SC_RESULT_MASK)
-					return EC_SUCCESS;
-			}
-			break;
-		default:
-			return EC_ERROR_UNIMPLEMENTED;
-		}
-	}
-
-	return EC_ERROR_NOT_CALIBRATED;
-}
-
-static int perform_calib(struct motion_sensor_t *s, int enable)
-{
-	int ret;
-	intv3_t target = {0, 0, 0};
-	uint8_t saved_conf[6] = {0};
-
-	/* Sensor is configured to be in 16G range */
-	int sens_range = 16;
-
-	/* Variable to set the accelerometer configuration value 50Hz for FOC */
-	uint8_t acc_conf_data[2] = {BMI3_FOC_ACC_CONF_VAL_LSB,
-					BMI3_FOC_ACC_CONF_VAL_MSB};
-
-	if (!enable)
-		return EC_SUCCESS;
-
-	/* Get default configurations for the type of feature selected. */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf,
-				6));
-
-	ret = bmi3_write_n(s, BMI3_REG_ACC_CONF, acc_conf_data, 2);
-	if (ret)
-		goto end_calib;
-
-	msleep(FOC_DELAY);
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		target[Z] = BMI3_ACC_DATA_PLUS_1G(sens_range);
-
-		/* Perform accel calibration */
-		ret = perform_accel_foc(s, target, sens_range);
-		if (ret)
-			goto end_calib;
-
-		/* Get caliration results */
-		ret = get_calib_result(s);
-		if (ret)
-			goto end_calib;
-
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		ret = set_gyro_foc_config(s);
-		if (ret)
-			goto end_calib;
-
-		ret = get_calib_result(s);
-		if (ret)
-			goto end_calib;
-
-		break;
-	default:
-		/* Not supported on Magnetometer */
-		ret = EC_RES_INVALID_PARAM;
-		goto end_calib;
-	}
-
-
-end_calib:
-	/* Restore ACC_CONF before exiting */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4));
-
-	return ret;
-}
-
-static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		    int16_t *temp)
-{
-	int i;
-	intv3_t v;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/*
-		 * The offset of the accelerometer is a 8 bit
-		 * two-complement number in units of 3.9 mg independent of the
-		 * range selected for the accelerometer.
-		 */
-		RETURN_ERROR(get_accel_offset(s, v));
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* Gyro offset is in milli-dps */
-		RETURN_ERROR(get_gyro_offset(s, v));
-		break;
-	default:
-		for (i = X; i <= Z; i++)
-			v[i] = 0;
-	}
-
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-	/* Saving temperature at calibration not supported yet */
-	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-	return EC_SUCCESS;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-		      const int16_t *offset,
-		      int16_t    temp)
-{
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-	(void)temp;
-
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* Offset should be in units of mg */
-		RETURN_ERROR(set_accel_offset(s, v));
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* Offset should be in units of mdps */
-		RETURN_ERROR(set_gyro_offset(s, v));
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BODY_DETECTION
-int get_rms_noise(const struct motion_sensor_t *s)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-#endif
-
-static int set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
-		     int16_t temp)
-{
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	saved_data->scale[X] = scale[X];
-	saved_data->scale[Y] = scale[Y];
-	saved_data->scale[Z] = scale[Z];
-
-	return EC_SUCCESS;
-}
-
-static int get_scale(const struct motion_sensor_t *s, uint16_t *scale,
-		   int16_t *temp)
-{
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	scale[X] = saved_data->scale[X];
-	scale[Y] = saved_data->scale[Y];
-	scale[Z] = saved_data->scale[Z];
-
-	*temp = (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-	return EC_SUCCESS;
-}
-
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	return saved_data->odr;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-			 int rate, int rnd)
-{
-	int ret;
-	int normalized_rate = 0;
-	uint8_t reg_data[4];
-	uint8_t reg_val = 0;
-
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-
-	if (rate > 0)
-		RETURN_ERROR(bmi_get_normalized_rate(s, rate, rnd,
-						 &normalized_rate, &reg_val));
-
-	/*
-	 * Lock accel resource to prevent another task from attempting
-	 * to write accel parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	/*
-	 * Get default configurations for the type of feature selected.
-	 */
-	ret = bmi3_read_n(s, BMI3_REG_ACC_CONF + s->type, reg_data, 4);
-	if (ret) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		if (rate == 0) {
-			/* FIFO stop collecting events */
-			if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-				ret = enable_fifo(s, 0);
-
-			/*
-			 * Disable accel to set rate equal to zero.
-			 * Accel does not have suspend mode.
-			 */
-			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				BMI3_POWER_MODE,
-				BMI3_ACC_MODE_DISABLE);
-
-			saved_data->odr = 0;
-		} else if (saved_data->odr == 0) {
-			/*
-			 * Power mode changed from suspend to
-			 * normal
-			 */
-			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_ACC_MODE_NORMAL);
-		}
-	} else if (s->type == MOTIONSENSE_TYPE_GYRO) {
-		if (rate == 0) {
-			/* FIFO stop collecting events */
-			if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-				ret = enable_fifo(s, 0);
-
-			/*
-			 * Set gyro to suspend mode to disable gyro
-			 * however keep internal driver enabled
-			 */
-			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_GYR_MODE_SUSPEND);
-
-			saved_data->odr = 0;
-		} else if (saved_data->odr == 0) {
-			/* Power mode changed from suspend to
-			 * normal
-			 */
-			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_GYR_MODE_NORMAL);
-		}
-	}
-
-	/* Set accelerometer ODR */
-	reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_SENS_ODR, reg_val);
-
-	/* Set the accel/gyro configurations. */
-	ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, &reg_data[2], 2);
-	if (ret) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-
-	saved_data->odr = normalized_rate;
-
-	/*
-	 * If rate is non zero, FIFO start collecting events.
-	 * They will be discarded if AP does not want them.
-	 */
-	if (rate > 0)
-		ret = enable_fifo(s, 1);
-
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	return BMI3_16_BIT_RESOLUTION;
-}
-
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int ret;
-	uint8_t index, sens_size = 0;
-	uint8_t reg_data[4] = { 0 };
-	int (*sensor_range)[2];
-
-	int acc_sensor_range[4][2] = {
-		{ 2, BMI3_ACC_RANGE_2G },
-		{ 4, BMI3_ACC_RANGE_4G },
-		{ 8, BMI3_ACC_RANGE_8G },
-		{ 16, BMI3_ACC_RANGE_16G },
-	};
-
-	int gyr_sensor_range[5][2] = {
-		{ 125, BMI3_GYR_RANGE_125DPS },
-		{ 250, BMI3_GYR_RANGE_250DPS },
-		{ 500, BMI3_GYR_RANGE_500DPS },
-		{ 1000, BMI3_GYR_RANGE_1000DPS },
-		{ 2000, BMI3_GYR_RANGE_2000DPS },
-	};
-
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		sens_size = ARRAY_SIZE(acc_sensor_range);
-		sensor_range = acc_sensor_range;
-	} else {
-		sens_size = ARRAY_SIZE(gyr_sensor_range);
-		sensor_range = gyr_sensor_range;
-	}
-
-	for (index = 0; index < sens_size - 1; index++) {
-		if (range <= sensor_range[index][0])
-			break;
-
-		if (range < sensor_range[index + 1][0] && rnd) {
-			index++;
-			break;
-		}
-	}
-
-	mutex_lock(s->mutex);
-
-	/*
-	 * Read the range register from sensor for accelerometer/gyroscope
-	 * s->type should have MOTIONSENSE_TYPE_ACCEL = 0 ;
-	 * MOTIONSENSE_TYPE_GYRO = 1
-	 */
-	ret = bmi3_read_n(s, BMI3_REG_ACC_CONF + s->type, reg_data, 4);
-
-	if (ret == EC_SUCCESS) {
-		/* Set accelerometer/Gyroscope range */
-		/* Gravity range of the sensor (+/- 2G, 4G, 8G, 16G). */
-		reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_SENS_RANGE,
-					    sensor_range[index][1]);
-
-		/* Set the accel/gyro configurations. */
-		ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type,
-				   &reg_data[2], 2);
-
-		/* Now that we have set the range, update the driver's value. */
-		if (ret == EC_SUCCESS)
-			s->current_range = sensor_range[index][0];
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	int ret;
-	uint8_t reg_data[8] = { 0 };
-	uint16_t status_val = 0;
-
-	mutex_lock(s->mutex);
-
-	/* Read the status register */
-	ret = bmi3_read_n(s, BMI3_REG_STATUS, reg_data, 4);
-
-	if (ret == EC_SUCCESS) {
-		status_val = (reg_data[2] | ((uint16_t)reg_data[3] << 8));
-		/*
-		 * If sensor data is not ready, return the previous read data.
-		 * Note: return success so that motion sensor task can read
-		 * again to get the latest updated sensor data quickly.
-		 */
-		if (!(status_val & BMI3_DRDY_MASK(s->type))) {
-			if (v != s->raw_xyz)
-				memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-
-			mutex_unlock(s->mutex);
-
-			return EC_SUCCESS;
-		}
-
-		if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-			/* Read the sensor data */
-			ret = bmi3_read_n(s, BMI3_REG_ACC_DATA_X, reg_data, 8);
-		} else if (s->type == MOTIONSENSE_TYPE_GYRO) {
-			/* Read the sensor data */
-			ret = bmi3_read_n(s, BMI3_REG_GYR_DATA_X, reg_data, 8);
-		}
-
-		if (ret == EC_SUCCESS) {
-			v[0] = ((int16_t)((reg_data[3] << 8) | reg_data[2]));
-			v[1] = ((int16_t)((reg_data[5] << 8) | reg_data[4]));
-			v[2] = ((int16_t)((reg_data[7] << 8) | reg_data[6]));
-
-			rotate(v, *s->rot_standard_ref, v);
-		}
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	/* Status of communication result */
-	uint8_t i;
-	uint8_t reg_data[4] = { 0 };
-
-	/* Store the sensor configurations */
-	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-
-	/* This driver requires a mutex */
-	ASSERT(s->mutex);
-
-	/*
-	 * BMI3xx driver only supports MOTIONSENSE_TYPE_ACCEL and
-	 * MOTIONSENSE_TYPE_GYR0
-	 */
-	if (s->type != MOTIONSENSE_TYPE_ACCEL
-	    && s->type != MOTIONSENSE_TYPE_GYRO)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/* Read chip id */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_CHIP_ID, reg_data, 4));
-
-	if (reg_data[2] != BMI323_CHIP_ID)
-		return EC_ERROR_HW_INTERNAL;
-
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		/* Reset bmi3 device */
-		reg_data[0] = (uint8_t)(BMI3_CMD_SOFT_RESET
-					& BMI3_SET_LOW_BYTE);
-		reg_data[1] = (uint8_t)((BMI3_CMD_SOFT_RESET
-					 & BMI3_SET_HIGH_BYTE) >> 8);
-
-		RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-		/* Delay of 2ms after soft reset*/
-		msleep(2);
-
-		/* Enable feature engine bit */
-		reg_data[0] = BMI3_ENABLE;
-		reg_data[1] = 0;
-
-		RETURN_ERROR(bmi3_write_n(s, BMI3_REG_FEATURE_ENGINE_GLOB_CTRL,
-					  reg_data, 2));
-
-		if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS))
-			RETURN_ERROR(config_interrupt(s));
-	}
-
-	for (i = X; i <= Z; i++)
-		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
-
-	/* The sensor is in Suspend mode at init, so set data rate to 0*/
-	saved_data->odr = 0;
-
-	/* Flags used in FIFO parsing */
-	data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED
-			| (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
-
-	return sensor_init_done(s);
-}
-
-/* Accelerometer/Gyroscope base driver structure */
-const struct accelgyro_drv bmi3xx_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.get_scale = get_scale,
-	.set_scale = set_scale,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-	.perform_calib = perform_calib,
-	.read_temp = read_temp,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = irq_handler,
-#endif
-#ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = get_rms_noise,
-#endif
-};
diff --git a/driver/accelgyro_bmi3xx.h b/driver/accelgyro_bmi3xx.h
deleted file mode 100644
index b52d503f92..0000000000
--- a/driver/accelgyro_bmi3xx.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI3XX gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI3XX_H
-#define __CROS_EC_ACCELGYRO_BMI3XX_H
-
-/* Sensor Specific macros */
-#define BMI3_ADDR_I2C_PRIM			0x68
-#define BMI3_ADDR_I2C_SEC			0x69
-#define BMI3_16_BIT_RESOLUTION			16
-
-/* Chip-specific registers */
-#define BMI3_REG_CHIP_ID			0x00
-
-#define BMI3_REG_STATUS				0x02
-#define BMI3_STAT_DATA_RDY_ACCEL_POS		7
-#define BMI3_STAT_DATA_RDY_ACCEL_MSK		0x80
-
-#define BMI3_REG_ACC_DATA_X			0x03
-#define BMI3_ACC_RANGE_2G			0x00
-#define BMI3_ACC_RANGE_4G			0x01
-#define BMI3_ACC_RANGE_8G			0x02
-#define BMI3_ACC_RANGE_16G			0x03
-#define BMI3_ACC_MODE_DISABLE			0x00
-#define BMI3_ACC_MODE_LOW_PWR			0x03
-#define BMI3_ACC_MODE_NORMAL			0X04
-#define BMI3_ACC_MODE_HIGH_PERF			0x07
-
-#define BMI3_REG_GYR_DATA_X			0x06
-#define BMI3_GYR_RANGE_125DPS			0x00
-#define BMI3_GYR_RANGE_250DPS			0x01
-#define BMI3_GYR_RANGE_500DPS			0x02
-#define BMI3_GYR_RANGE_1000DPS			0x03
-#define BMI3_GYR_RANGE_2000DPS			0x04
-#define BMI3_GYR_MODE_DISABLE			0x00
-#define BMI3_GYR_MODE_SUSPEND			0X01
-#define BMI3_GYR_MODE_ULTRA_LOW_PWR		0X02
-#define BMI3_GYR_MODE_LOW_PWR			0x03
-#define BMI3_GYR_MODE_NORMAL			0X04
-#define BMI3_GYR_MODE_HIGH_PERF			0x07
-
-#define BMI3_REG_INT_STATUS_INT1		0x0D
-#define BMI3_REG_FIFO_FILL_LVL			0x15
-#define BMI3_REG_FIFO_DATA			0x16
-#define BMI3_REG_ACC_CONF			0x20
-#define BMI3_REG_GYR_CONF			0x21
-#define BMI3_REG_INT_MAP1			0x3A
-#define BMI3_REG_FIFO_WATERMARK			0x35
-
-#define BMI3_REG_FIFO_CONF			0x36
-#define BMI3_FIFO_STOP_ON_FULL			0x01
-#define BMI3_FIFO_TIME_EN			0x01
-#define BMI3_FIFO_ACC_EN			0x02
-#define BMI3_FIFO_GYR_EN			0x04
-#define BMI3_FIFO_TEMP_EN			0x08
-#define BMI3_FIFO_ALL_EN			0x0F
-
-#define BMI3_REG_FIFO_CTRL			0x37
-#define BMI3_REG_IO_INT_CTRL			0x38
-#define BMI3_INT1_LVL_MASK			0x01
-#define BMI3_INT1_OD_MASK			0x02
-#define BMI3_INT1_OD_POS			1
-#define BMI3_INT1_OUTPUT_EN_MASK		0x04
-#define BMI3_INT1_OUTPUT_EN_POS			2
-#define BMI3_INT_PUSH_PULL			0
-#define BMI3_INT_OPEN_DRAIN			1
-#define BMI3_INT_ACTIVE_LOW			0
-#define BMI3_INT_ACTIVE_HIGH			1
-
-#define BMI3_REG_IO_INT_CONF			0x39
-#define BMI3_INT_LATCH_EN			1
-#define BMI3_INT_LATCH_DISABLE			0
-
-#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL	0x40
-
-#define BMI3_FEATURE_EVENT_EXT			0x47
-#define BMI3_PORTRAIT_LANDSCAPE_MASK		0x03
-#define BMI3_PORTRAIT				0
-#define BMI3_LANDSCAPE				1
-#define BMI3_PORTRAIT_INVERT			2
-#define BMI3_LANDSCAPE_INVERT			3
-
-#define ACC_DP_OFF_X				0x60
-#define GYR_DP_OFF_X				0x66
-
-#define BMI3_REG_CMD				0x7E
-#define BMI3_CMD_SOFT_RESET			0xDEAF
-
-/* BMI3 Interrupt Output Enable */
-#define BMI3_INT_OUTPUT_DISABLE			0
-#define BMI3_INT_OUTPUT_ENABLE			1
-
-/* FIFO sensor data length (in word), Accel or Gyro */
-#define BMI3_FIFO_ENTRY			0x3
-/* Macro to define accelerometer configuration value for FOC */
-#define BMI3_FOC_ACC_CONF_VAL_LSB		0xB7
-#define BMI3_FOC_ACC_CONF_VAL_MSB		0x40
-/* Macro to define the accel FOC range */
-#define BMI3_ACC_FOC_2G_REF			16384
-#define BMI3_ACC_FOC_4G_REF			8192
-#define BMI3_ACC_FOC_8G_REF			4096
-#define BMI3_ACC_FOC_16G_REF			2048
-#define BMI3_FOC_SAMPLE_LIMIT			32
-
-/* 20ms delay for 50Hz ODR */
-#define FOC_TRY_COUNT				5
-#define FOC_DELAY				20
-#define BMI3_INT_STATUS_FWM			0x4000
-#define BMI3_INT_STATUS_FFULL			0x8000
-#define BMI3_INT_STATUS_ORIENTATION		0x0008
-
-
-#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME		0x7f02
-#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME		0x7f01
-
-/* Gyro self calibration address */
-#define BMI3_BASE_ADDR_SC			0x26
-#define BMI3_CMD_SELF_CALIB			0x0101
-
-/* Feature engine General purpose register 1. */
-#define BMI3_FEATURE_IO_0			0x10
-#define BMI3_ANY_MOTION_X_EN_MASK		0x08
-
-#define BMI3_FEATURE_IO_1			0x11
-#define BMI3_FEATURE_IO_1_ERROR_MASK		0x0F
-#define BMI3_FEATURE_IO_1_NO_ERROR		0x05
-#define BMI3_SC_ST_STATUS_MASK			0x10
-#define BMI3_SC_RESULT_MASK			0x20
-#define BMI3_UGAIN_OFFS_UPD_COMPLETE		0x01
-
-#define BMI3_FEATURE_IO_STATUS			0x14
-
-/*
- * The max positive value of accel data is 0x7FFF, equal to range(g)
- * So, in order to get +1g, divide the 0x7FFF by range
- */
-#define BMI3_ACC_DATA_PLUS_1G(range)  (0x7FFF / (range))
-#define BMI3_ACC_DATA_MINUS_1G(range) (-BMI3_ACC_DATA_PLUS_1G(range))
-
-/* Offset DMA registers */
-#define BMI3_ACC_OFFSET_ADDR			0x40
-#define BMI3_GYRO_OFFSET_ADDR			0x46
-
-/*
- * Start address of the DMA transaction. Has to be written to initiate a
- * transaction.
- */
-#define BMI3_FEATURE_ENGINE_DMA_TX		0x41
-
-/* DMA read/write data. On read transaction expect first word to be zero. */
-#define BMI3_FEATURE_ENGINE_DMA_TX_DATA		0x42
-
-/* Command for offset update */
-#define BMI3_CMD_USR_GAIN_OFFS_UPDATE		0x301
-
-/* 1LSB - 31 Micro-G */
-#define BMI3_OFFSET_ACC_MULTI_MG		(31 * 1000)
-
-/* 1LSB = 61 milli-dps*/
-#define BMI3_OFFSET_GYR_MDPS			(61 * 1000)
-
-#define BMI3_FIFO_BUFFER			32
-
-/* General Macro Definitions */
-/* LSB and MSB mask definitions */
-#define BMI3_SET_LOW_BYTE			0x00FF
-#define BMI3_SET_HIGH_BYTE			0xFF00
-
-/* For enable and disable */
-#define BMI3_ENABLE				0x1
-#define BMI3_DISABLE				0x0
-
-/* Defines mode of operation for Accelerometer */
-#define BMI3_POWER_MODE_MASK			0x70
-#define BMI3_POWER_MODE_POS			4
-
-#define BMI3_SENS_ODR_MASK			0x0F
-
-/* Full scale, Resolution */
-#define BMI3_SENS_RANGE_MASK			0x70
-#define BMI3_SENS_RANGE_POS			4
-
-#define BMI3_CHIP_ID_MASK			0xFF
-
-/* Map FIFO water-mark interrupt to either INT1 or INT2 or IBI */
-#define BMI3_FWM_INT_MASK			0x30
-#define BMI3_FWM_INT_POS			4
-
-/* Map FIFO full interrupt to either INT1 or INT2 or IBI */
-#define BMI3_FFULL_INT_MASK			0xC0
-#define BMI3_FFULL_INT_POS			6
-
-#define BMI3_ORIENT_INT_MASK			0xC0
-#define BMI3_ORIENT_INT_POS			6
-
-
-
-/*  Mask definitions for interrupt pin configuration */
-#define BMI3_INT_LATCH_MASK			0x0001
-
-/**
- * Current fill level of FIFO buffer
- * An empty FIFO corresponds to 0x000. The word counter may be reset by reading
- * out all frames from the FIFO buffer or when the FIFO is reset through
- * fifo_flush. The word counter is updated each time a complete frame was read
- * or written.
- */
-#define BMI3_FIFO_FILL_LVL_MASK			0x07FF
-
-/* Enum to define interrupt lines */
-enum bmi3_hw_int_pin {
-	BMI3_INT_NONE,
-	BMI3_INT1,
-	BMI3_INT2,
-	BMI3_I3C_INT,
-	BMI3_INT_PIN_MAX
-};
-
-/* Structure to define FIFO frame configuration */
-struct bmi3_fifo_frame {
-	uint16_t data[BMI3_FIFO_BUFFER + 1];
-
-	/* Available fifo length */
-	uint16_t available_fifo_len;
-};
-
-enum sensor_index_t {
-	FIRST_CONT_SENSOR = 0,
-	SENSOR_ACCEL = FIRST_CONT_SENSOR,
-	SENSOR_GYRO,
-	NUM_OF_PRIMARY_SENSOR,
-};
-
-#define BMI3_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI3_DRDY_MASK(_sensor)  (1 << BMI3_DRDY_OFF(_sensor))
-
-/* Utility macros */
-#define BMI3_SET_BITS(reg_data, bitname, data)         \
-		     ((reg_data & ~(bitname##_MASK)) | \
-		     ((data << bitname##_POS) & bitname##_MASK))
-
-#define BMI3_GET_BITS(reg_data, bitname)               \
-		     ((reg_data & (bitname##_MASK)) >> \
-		     (bitname##_POS))
-
-#define BMI3_SET_BIT_POS0(reg_data, bitname, data)         \
-			 ((reg_data & ~(bitname##_MASK)) | \
-			 (data & bitname##_MASK))
-
-#define BMI3_GET_BIT_POS0(reg_data, bitname) \
-			 (reg_data & (bitname##_MASK))
-
-extern const struct accelgyro_drv bmi3xx_drv;
-
-void bmi3xx_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ACCELGYRO_BMI3XX_H */
diff --git a/driver/accelgyro_bmi_common.c b/driver/accelgyro_bmi_common.c
deleted file mode 100644
index 2da407427e..0000000000
--- a/driver/accelgyro_bmi_common.c
+++ /dev/null
@@ -1,902 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * BMI accelerometer and gyro module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-
-#include "accelgyro.h"
-#include "console.h"
-#include "accelgyro_bmi_common.h"
-#include "mag_bmm150.h"
-#include "mag_lis2mdl.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#if !defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI260) \
-&& !defined(CONFIG_ACCELGYRO_BMI3XX)
-#error "Must use following sensors BMI160 BMI260 BMI3XX"
-#endif
-
-#if defined(CONFIG_ACCELGYRO_BMI260) && !defined(CONFIG_ACCELGYRO_BMI160)
-#define V(s_) 1
-#elif defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI260)
-#define V(s_) 0
-#else
-#define V(s_) ((s_)->chip == MOTIONSENSE_CHIP_BMI260)
-#endif
-/* Index for which table to use. */
-#if !defined(CONFIG_ACCELGYRO_BMI160) || !defined(CONFIG_ACCELGYRO_BMI260)
-#define T(s_) 0
-#else
-#define T(s_) V(s_)
-#endif
-
-/* List of range values in +/-G's and their associated register values. */
-const struct bmi_accel_param_pair g_ranges[][4] = {
-#ifdef CONFIG_ACCELGYRO_BMI160
-	{ {2,  BMI160_GSEL_2G},
-	  {4,  BMI160_GSEL_4G},
-	  {8,  BMI160_GSEL_8G},
-	  {16, BMI160_GSEL_16G} },
-#endif
-#ifdef CONFIG_ACCELGYRO_BMI260
-	{ {2,  BMI260_GSEL_2G},
-	  {4,  BMI260_GSEL_4G},
-	  {8,  BMI260_GSEL_8G},
-	  {16, BMI260_GSEL_16G} },
-#endif
-};
-
-/*
- * List of angular rate range values in +/-dps's
- * and their associated register values.
- */
-const struct bmi_accel_param_pair dps_ranges[][5] = {
-#ifdef CONFIG_ACCELGYRO_BMI160
-	{ {125,  BMI160_DPS_SEL_125},
-	  {250,  BMI160_DPS_SEL_250},
-	  {500,  BMI160_DPS_SEL_500},
-	  {1000, BMI160_DPS_SEL_1000},
-	  {2000, BMI160_DPS_SEL_2000} },
-#endif
-#ifdef CONFIG_ACCELGYRO_BMI260
-	{ {125,  BMI260_DPS_SEL_125},
-	  {250,  BMI260_DPS_SEL_250},
-	  {500,  BMI260_DPS_SEL_500},
-	  {1000, BMI260_DPS_SEL_1000},
-	  {2000, BMI260_DPS_SEL_2000} },
-#endif
-};
-
-int bmi_get_xyz_reg(const struct motion_sensor_t *s)
-{
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		return BMI_ACC_DATA(V(s));
-	case MOTIONSENSE_TYPE_GYRO:
-		return BMI_GYR_DATA(V(s));
-	case MOTIONSENSE_TYPE_MAG:
-		return BMI_AUX_DATA(V(s));
-	default:
-		return -1;
-	}
-}
-
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize)
-{
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		if (psize)
-			*psize = ARRAY_SIZE(g_ranges[T(s)]);
-		return g_ranges[T(s)];
-	}
-	if (psize)
-		*psize = ARRAY_SIZE(dps_ranges[T(s)]);
-	return dps_ranges[T(s)];
-}
-
-/**
- * @return reg value that matches the given engineering value passed in.
- * The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid reg value. If the request is
- * outside the range of values, it returns the closest valid reg value.
- */
-int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size)
-{
-	int i;
-
-	for (i = 0; i < size - 1; i++) {
-		if (eng_val <= pairs[i].val)
-			break;
-
-		if (eng_val < pairs[i+1].val) {
-			if (round_up)
-				i += 1;
-			break;
-		}
-	}
-	return pairs[i].reg_val;
-}
-
-/**
- * @return engineering value that matches the given reg val
- */
-int bmi_get_engineering_val(const int reg_val,
-			    const struct bmi_accel_param_pair *pairs,
-			    const int size)
-{
-	int i;
-
-	for (i = 0; i < size; i++) {
-		if (reg_val == pairs[i].reg_val)
-			break;
-	}
-	return pairs[i].val;
-}
-
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-static int bmi_spi_raw_read(const int addr, const uint8_t reg,
-		     uint8_t *data, const int len)
-{
-	uint8_t cmd = 0x80 | reg;
-
-	return spi_transaction(&spi_devices[addr], &cmd, 1, data, len);
-}
-#endif
-
-/**
- * Read 8bit register from accelerometer.
- */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr)
-{
-	int rv;
-
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	{
-		uint8_t val;
-
-		rv = bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags),
-				      reg, &val, 1);
-		if (rv == EC_SUCCESS)
-			*data_ptr = val;
-	}
-#else
-	rv = i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
-#endif
-	return rv;
-}
-
-/**
- * Write 8bit register from accelerometer.
- */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data)
-{
-	int rv;
-
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	{
-		uint8_t cmd[2] = { reg, data };
-
-		rv = spi_transaction(
-			&spi_devices[ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags)],
-			cmd, 2, NULL, 0);
-	}
-#else
-	rv = i2c_write8(port, i2c_spi_addr_flags, reg, data);
-#endif
-	/*
-	 * From Bosch:  BMI needs a delay of 450us after each write if it
-	 * is in suspend mode, otherwise the operation may be ignored by
-	 * the sensor. Given we are only doing write during init, add
-	 * the delay unconditionally.
-	 */
-	msleep(1);
-
-	return rv;
-}
-
-/**
- * Read 16bit register from accelerometer.
- */
-int bmi_read16(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr)
-{
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
-				(uint8_t *)data_ptr, 2);
-#else
-	return i2c_read16(port, i2c_spi_addr_flags, reg, data_ptr);
-#endif
-}
-
-/**
- * Write 16bit register from accelerometer.
- */
-int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
-		const int reg, int data)
-{
-	int rv = -EC_ERROR_PARAM1;
-
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	CPRINTS("%s() spi part is not implemented", __func__);
-#else
-	rv = i2c_write16(port, i2c_spi_addr_flags, reg, data);
-#endif
-	/*
-	 * From Bosch:  BMI needs a delay of 450us after each write if it
-	 * is in suspend mode, otherwise the operation may be ignored by
-	 * the sensor. Given we are only doing write during init, add
-	 * the delay unconditionally.
-	 */
-	msleep(1);
-	return rv;
-}
-
-/**
- * Read 32bit register from accelerometer.
- */
-int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr)
-{
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
-				(uint8_t *)data_ptr, 4);
-#else
-	return i2c_read32(port, i2c_spi_addr_flags, reg, data_ptr);
-#endif
-}
-
-/**
- * Read n bytes from accelerometer.
- */
-int bmi_read_n(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, uint8_t *data_ptr, const int len)
-{
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	return bmi_spi_raw_read(ACCEL_GET_SPI_ADDR(i2c_spi_addr_flags), reg,
-				data_ptr, len);
-#else
-	return i2c_read_block(port, i2c_spi_addr_flags, reg, data_ptr, len);
-#endif
-}
-
-/**
- * Write n bytes from accelerometer.
- */
-int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
-		const uint8_t reg, const uint8_t *data_ptr, const int len)
-{
-	int rv = -EC_ERROR_PARAM1;
-
-#ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-	CPRINTS("%s() spi part is not implemented", __func__);
-#else
-	rv = i2c_write_block(port, i2c_spi_addr_flags, reg, data_ptr, len);
-#endif
-	/*
-	 * From Bosch:  BMI needs a delay of 450us after each write if it
-	 * is in suspend mode, otherwise the operation may be ignored by
-	 * the sensor. Given we are only doing write during init, add
-	 * the delay unconditionally.
-	 */
-	msleep(1);
-
-	return rv;
-}
-/*
- * Enable/Disable specific bit set of a 8-bit reg.
- */
-int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
-		    int enable)
-{
-	if (enable)
-		return bmi_set_reg8(s, reg, bits, 0);
-	return bmi_set_reg8(s, reg, 0, bits);
-}
-
-/*
- * Set specific bit set to certain value of a 8-bit reg.
- */
-int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
-		 int mask)
-{
-	int ret, val;
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, reg, &val);
-	if (ret)
-		return ret;
-	val = (val & ~mask) | bits;
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, reg, val);
-	return ret;
-}
-
-void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input)
-{
-	int i;
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	if (IS_ENABLED(CONFIG_MAG_BMI_BMM150) &&
-	    (s->type == MOTIONSENSE_TYPE_MAG)) {
-		bmm150_normalize(s, v, input);
-	} else if (IS_ENABLED(CONFIG_MAG_BMI_LIS2MDL) &&
-		   (s->type == MOTIONSENSE_TYPE_MAG)) {
-		lis2mdl_normalize(s, v, input);
-	} else {
-		v[0] = ((int16_t)((input[1] << 8) | input[0]));
-		v[1] = ((int16_t)((input[3] << 8) | input[2]));
-		v[2] = ((int16_t)((input[5] << 8) | input[4]));
-	}
-	rotate(v, *s->rot_standard_ref, v);
-	for (i = X; i <= Z; i++)
-		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
-}
-
-int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr,
-		      uint32_t last_ts, uint8_t **bp, uint8_t *ep)
-{
-	if ((hdr & BMI_FH_MODE_MASK) == BMI_FH_EMPTY &&
-	    (hdr & BMI_FH_PARM_MASK) != 0) {
-		int i, size = 0;
-		/* Check if there is enough space for the data frame */
-		for (i = MOTIONSENSE_TYPE_MAG; i >= MOTIONSENSE_TYPE_ACCEL;
-		     i--) {
-			if (hdr & (1 << (i + BMI_FH_PARM_OFFSET)))
-				size += (i == MOTIONSENSE_TYPE_MAG ? 8 : 6);
-		}
-		if (*bp + size > ep) {
-			/* frame is not complete, it will be retransmitted. */
-			*bp = ep;
-			return 1;
-		}
-		for (i = MOTIONSENSE_TYPE_MAG; i >= MOTIONSENSE_TYPE_ACCEL;
-		     i--) {
-			struct motion_sensor_t *s = accel + i;
-
-			if (hdr & (1 << (i + BMI_FH_PARM_OFFSET))) {
-				struct ec_response_motion_sensor_data vector;
-				int *v = s->raw_xyz;
-
-				vector.flags = 0;
-				bmi_normalize(s, v, *bp);
-				if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
-				    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
-					v = s->spoof_xyz;
-				vector.data[X] = v[X];
-				vector.data[Y] = v[Y];
-				vector.data[Z] = v[Z];
-				vector.sensor_num = s - motion_sensors;
-				motion_sense_fifo_stage_data(&vector, s, 3,
-							     last_ts);
-				*bp += (i == MOTIONSENSE_TYPE_MAG ? 8 : 6);
-			}
-		}
-
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-enum fifo_state {
-	FIFO_HEADER,
-	FIFO_DATA_SKIP,
-	FIFO_DATA_TIME,
-	FIFO_DATA_CONFIG,
-};
-
-#define BMI_FIFO_BUFFER 64
-static uint8_t bmi_buffer[BMI_FIFO_BUFFER];
-
-int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	uint16_t length;
-	enum fifo_state state = FIFO_HEADER;
-	uint8_t *bp = bmi_buffer;
-	uint8_t *ep;
-	uint32_t beginning;
-
-	if (s->type != MOTIONSENSE_TYPE_ACCEL)
-		return EC_SUCCESS;
-
-	if (!(data->flags & (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET))) {
-		/*
-		 * The FIFO was disabled while we were processing it.
-		 *
-		 * Flush potential left over:
-		 * When sensor is resumed, we won't read old data.
-		 */
-		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI_CMD_REG(V(s)),
-			   BMI_CMD_FIFO_FLUSH);
-		return EC_SUCCESS;
-	}
-
-	bmi_read_n(s->port, s->i2c_spi_addr_flags, BMI_FIFO_LENGTH_0(V(s)),
-		   (uint8_t *)&length, sizeof(length));
-	length &= BMI_FIFO_LENGTH_MASK(V(s));
-
-	/*
-	 * We have not requested timestamp, no extra frame to read.
-	 * if we have too much to read, read the whole buffer.
-	 */
-	if (length == 0) {
-		/*
-		 * Disable this message on BMI260, due to this seems to always
-		 * happen after we complete to read the data.
-		 * TODO(chingkang): check why this happen on BMI260.
-		 */
-		if (V(s) == 0)
-			CPRINTS("unexpected empty FIFO");
-		return EC_SUCCESS;
-	}
-
-	/* Add one byte to get an empty FIFO frame.*/
-	length++;
-
-	if (length > sizeof(bmi_buffer))
-		CPRINTS("unexpected large FIFO: %d", length);
-	length = MIN(length, sizeof(bmi_buffer));
-
-	bmi_read_n(s->port, s->i2c_spi_addr_flags, BMI_FIFO_DATA(V(s)),
-		   bmi_buffer, length);
-	beginning = *(uint32_t *)bmi_buffer;
-	ep = bmi_buffer + length;
-	/*
-	 * FIFO is invalid when reading while the sensors are all
-	 * suspended.
-	 * Instead of returning the empty frame, it can return a
-	 * pattern that looks like a valid header: 84 or 40.
-	 * If we see those, assume the sensors have been disabled
-	 * while this thread was running.
-	 */
-	if (beginning == 0x84848484 || (beginning & 0xdcdcdcdc) == 0x40404040) {
-		CPRINTS("Suspended FIFO: accel ODR/rate: %d/%d: 0x%08x",
-			BASE_ODR(s->config[SENSOR_CONFIG_AP].odr),
-			BMI_GET_SAVED_DATA(s)->odr, beginning);
-		return EC_SUCCESS;
-	}
-
-	while (bp < ep) {
-		switch (state) {
-		case FIFO_HEADER: {
-			enum fifo_header hdr = *bp++;
-
-			if (bmi_decode_header(s, hdr, last_ts, &bp, ep))
-				continue;
-			/* Other cases */
-			hdr &= 0xdc;
-			switch (hdr) {
-			case BMI_FH_EMPTY:
-				return EC_SUCCESS;
-			case BMI_FH_SKIP:
-				state = FIFO_DATA_SKIP;
-				break;
-			case BMI_FH_TIME:
-				state = FIFO_DATA_TIME;
-				break;
-			case BMI_FH_CONFIG:
-				state = FIFO_DATA_CONFIG;
-				break;
-			default:
-				CPRINTS("Unknown header: 0x%02x @ %zd", hdr,
-					bp - bmi_buffer);
-				bmi_write8(s->port, s->i2c_spi_addr_flags,
-					   BMI_CMD_REG(V(s)),
-					   BMI_CMD_FIFO_FLUSH);
-				return EC_ERROR_NOT_HANDLED;
-			}
-			break;
-		}
-		case FIFO_DATA_SKIP:
-			CPRINTS("@ %zd - %d, skipped %d frames",
-				bp - bmi_buffer, length, *bp);
-			bp++;
-			state = FIFO_HEADER;
-			break;
-		case FIFO_DATA_CONFIG:
-			CPRINTS("@ %zd - %d, config change: 0x%02x",
-				bp - bmi_buffer, length, *bp);
-			bp++;
-			if (V(s))
-				state = FIFO_DATA_TIME;
-			else
-				state = FIFO_HEADER;
-			break;
-		case FIFO_DATA_TIME:
-			if (bp + 3 > ep) {
-				bp = ep;
-				continue;
-			}
-			/* We are not requesting timestamp */
-			CPRINTS("timestamp %d",
-				(bp[2] << 16) | (bp[1] << 8) | bp[0]);
-			state = FIFO_HEADER;
-			bp += 3;
-			break;
-		default:
-			CPRINTS("Unknown data: 0x%02x", *bp++);
-			state = FIFO_HEADER;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int bmi_set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int ret, range_tbl_size;
-	uint8_t reg_val, ctrl_reg;
-	const struct bmi_accel_param_pair *ranges;
-
-	if (s->type == MOTIONSENSE_TYPE_MAG) {
-		s->current_range = range;
-		return EC_SUCCESS;
-	}
-
-	ctrl_reg = BMI_RANGE_REG(s->type);
-	ranges = bmi_get_range_table(s, &range_tbl_size);
-	reg_val = bmi_get_reg_val(range, rnd, ranges, range_tbl_size);
-
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, reg_val);
-	/* Now that we have set the range, update the driver's value. */
-	if (ret == EC_SUCCESS)
-		s->current_range = bmi_get_engineering_val(reg_val, ranges,
-							   range_tbl_size);
-	return ret;
-}
-
-int bmi_get_data_rate(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	return data->odr;
-}
-
-int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		   int16_t *temp)
-{
-	int i, ret = EC_SUCCESS;
-	intv3_t v;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/*
-		 * The offset of the accelerometer off_acc_[xyz] is a 8 bit
-		 * two-complement number in units of 3.9 mg independent of the
-		 * range selected for the accelerometer.
-		 */
-		ret = bmi_accel_get_offset(s, v);
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/*
-		 * The offset of the gyroscope off_gyr_[xyz] is a 10 bit
-		 * two-complement number in units of 0.061 °/s.
-		 * Therefore a maximum range that can be compensated is
-		 * -31.25 °/s to +31.25 °/s
-		 */
-		ret = bmi_gyro_get_offset(s, v);
-		break;
-#ifdef CONFIG_MAG_BMI_BMM150
-	case MOTIONSENSE_TYPE_MAG:
-		ret = bmm150_get_offset(s, v);
-		break;
-#endif /* defined(CONFIG_MAG_BMI_BMM150) */
-	default:
-		for (i = X; i <= Z; i++)
-			v[i] = 0;
-	}
-
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-	/* Saving temperature at calibration not supported yet */
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s)
-{
-	int ret;
-	fp_t noise_100hz, rate, sqrt_rate_ratio;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
-		rate = INT_TO_FP(bmi_get_data_rate(s) / 1000);
-		/*
-		 * Since the noise is proportional to sqrt(ODR) in BMI, and we
-		 * have rms noise in 100 Hz, we multiply it with the sqrt(ratio
-		 * of ODR to 100Hz) to get current noise.
-		 */
-		noise_100hz = INT_TO_FP(BMI_ACCEL_RMS_NOISE_100HZ(V(s)));
-		sqrt_rate_ratio =
-			fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
-		ret = FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
-		break;
-	default:
-		CPRINTS("%s with gyro/mag is not implemented", __func__);
-		return 0;
-	}
-	return ret;
-}
-#endif
-
-int bmi_get_resolution(const struct motion_sensor_t *s)
-{
-	return BMI_RESOLUTION;
-}
-
-int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
-		  int16_t temp)
-{
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	data->scale[X] = scale[X];
-	data->scale[Y] = scale[Y];
-	data->scale[Z] = scale[Z];
-	return EC_SUCCESS;
-}
-
-int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
-		  int16_t *temp)
-{
-	struct accelgyro_saved_data_t *data = BMI_GET_SAVED_DATA(s);
-
-	scale[X] = data->scale[X];
-	scale[Y] = data->scale[Y];
-	scale[Z] = data->scale[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-int bmi_enable_fifo(const struct motion_sensor_t *s, int enable)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	int ret;
-
-	/* FIFO start/stop collecting events */
-	ret = bmi_enable_reg8(s, BMI_FIFO_CONFIG_1(V(s)),
-			      BMI_FIFO_SENSOR_EN(V(s), s->type), enable);
-	if (ret)
-		return ret;
-
-	if (enable)
-		data->flags |= 1 << (s->type + BMI_FIFO_FLAG_OFFSET);
-	else
-		data->flags &= ~(1 << (s->type + BMI_FIFO_FLAG_OFFSET));
-
-	return ret;
-}
-
-int bmi_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t data[6];
-	int ret, status = 0;
-
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI_STATUS(V(s)),
-			&status);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!(status & BMI_DRDY_MASK(s->type))) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-		return EC_SUCCESS;
-	}
-
-	/* Read 6 bytes starting at xyz_reg */
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, bmi_get_xyz_reg(s),
-			 data, 6);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
-		return ret;
-	}
-	bmi_normalize(s, v, data);
-	return EC_SUCCESS;
-}
-
-int bmi_read_temp(const struct motion_sensor_t *s, int *temp_ptr)
-{
-	return bmi_get_sensor_temp(s - motion_sensors, temp_ptr);
-}
-
-int bmi_get_sensor_temp(int idx, int *temp_ptr)
-{
-	struct motion_sensor_t *s = &motion_sensors[idx];
-	int16_t temp;
-	int ret;
-
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 BMI_TEMPERATURE_0(V(s)), (uint8_t *)&temp,
-			 sizeof(temp));
-
-	if (ret || temp == (int16_t)BMI_INVALID_TEMP)
-		return EC_ERROR_NOT_POWERED;
-
-	*temp_ptr = C_TO_K(23 + ((temp + 256) >> 9));
-	return 0;
-}
-
-int bmi_get_normalized_rate(const struct motion_sensor_t *s, int rate, int rnd,
-			    int *normalized_rate_ptr, uint8_t *reg_val_ptr)
-{
-	*reg_val_ptr = BMI_ODR_TO_REG(rate);
-	*normalized_rate_ptr = BMI_REG_TO_ODR(*reg_val_ptr);
-	if (rnd && (*normalized_rate_ptr < rate)) {
-		(*reg_val_ptr)++;
-		*normalized_rate_ptr = BMI_REG_TO_ODR(*reg_val_ptr);
-	}
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		if (*normalized_rate_ptr > BMI_ACCEL_MAX_FREQ ||
-		    *normalized_rate_ptr < BMI_ACCEL_MIN_FREQ)
-			return EC_RES_INVALID_PARAM;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		if (*normalized_rate_ptr > BMI_GYRO_MAX_FREQ ||
-		    *normalized_rate_ptr < BMI_GYRO_MIN_FREQ)
-			return EC_RES_INVALID_PARAM;
-		break;
-#ifdef CONFIG_MAG_BMI_BMM150
-	case MOTIONSENSE_TYPE_MAG:
-		/* We use the regular preset we can go about 100Hz */
-		if (*reg_val_ptr > BMI_ODR_100HZ ||
-		    *reg_val_ptr < BMI_ODR_0_78HZ)
-			return EC_RES_INVALID_PARAM;
-		break;
-#endif
-
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-	return EC_SUCCESS;
-}
-
-int bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v)
-{
-	int i, val, ret;
-
-	for (i = X; i <= Z; i++) {
-		ret = bmi_read8(accel->port, accel->i2c_spi_addr_flags,
-				BMI_OFFSET_ACC70(V(accel)) + i, &val);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		if (val > 0x7f)
-			val = -256 + val;
-		v[i] = round_divide((int64_t)val * BMI_OFFSET_ACC_MULTI_MG,
-				    BMI_OFFSET_ACC_DIV_MG);
-	}
-
-	return EC_SUCCESS;
-}
-
-int bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v)
-{
-	int i, val, val98, ret;
-
-	/* Read the MSB first */
-	ret = bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
-			BMI_OFFSET_EN_GYR98(V(gyro)), &val98);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	for (i = X; i <= Z; i++) {
-		ret = bmi_read8(gyro->port, gyro->i2c_spi_addr_flags,
-				BMI_OFFSET_GYR70(V(gyro)) + i, &val);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		val |= ((val98 >> (2 * i)) & 0x3) << 8;
-		if (val > 0x1ff)
-			val = -1024 + val;
-		v[i] = round_divide((int64_t)val * BMI_OFFSET_GYRO_MULTI_MDS,
-				    BMI_OFFSET_GYRO_DIV_MDS);
-	}
-
-	return EC_SUCCESS;
-}
-
-int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v)
-{
-	int i, val, ret;
-
-	for (i = X; i <= Z; ++i) {
-		val = round_divide((int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
-				   BMI_OFFSET_ACC_MULTI_MG);
-		if (val > 127)
-			val = 127;
-		if (val < -128)
-			val = -128;
-		if (val < 0)
-			val = 256 + val;
-		ret = bmi_write8(accel->port, accel->i2c_spi_addr_flags,
-				 BMI_OFFSET_ACC70(V(accel)) + i, val);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr)
-{
-	int i, val, ret;
-
-	for (i = X; i <= Z; i++) {
-		val = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
-				   BMI_OFFSET_GYRO_MULTI_MDS);
-		if (val > 511)
-			val = 511;
-		if (val < -512)
-			val = -512;
-		if (val < 0)
-			val = 1024 + val;
-		ret = bmi_write8(gyro->port, gyro->i2c_spi_addr_flags,
-				 BMI_OFFSET_GYR70(V(gyro)) + i, val & 0xFF);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		*val98_ptr &= ~(0x3 << (2 * i));
-		*val98_ptr |= (val >> 8) << (2 * i);
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-bool motion_orientation_changed(const struct motion_sensor_t *s)
-{
-	return BMI_GET_DATA(s)->orientation !=
-	       BMI_GET_DATA(s)->last_orientation;
-}
-
-enum motionsensor_orientation *
-motion_orientation_ptr(const struct motion_sensor_t *s)
-{
-	return &BMI_GET_DATA(s)->orientation;
-}
-
-void motion_orientation_update(const struct motion_sensor_t *s)
-{
-	BMI_GET_DATA(s)->last_orientation = BMI_GET_DATA(s)->orientation;
-}
-#endif
-
-int bmi_list_activities(const struct motion_sensor_t *s,
-			uint32_t *enabled,
-			uint32_t *disabled)
-{
-	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
-	*enabled = data->enabled_activities;
-	*disabled = data->disabled_activities;
-	return EC_RES_SUCCESS;
-}
diff --git a/driver/accelgyro_icm42607.c b/driver/accelgyro_icm42607.c
deleted file mode 100644
index ae831c5918..0000000000
--- a/driver/accelgyro_icm42607.c
+++ /dev/null
@@ -1,1132 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * ICM-42607 accelerometer and gyroscope module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "console.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm42607.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-static int icm_switch_on_mclk(const struct motion_sensor_t *s)
-{
-	int val;
-	int i, ret;
-
-	ret = icm_field_update8(s, ICM42607_REG_PWR_MGMT0, ICM42607_IDLE,
-				ICM42607_IDLE);
-	if (ret)
-		return ret;
-
-	/* Check if MCLK is ready */
-	for (i = 0; i < 10; ++i) {
-		ret = icm_read8(s, ICM42607_REG_MCLK_RDY, &val);
-		if (ret)
-			return ret;
-
-		if (val & ICM42607_MCLK_RDY)
-			return EC_SUCCESS;
-	}
-
-	return EC_ERROR_HW_INTERNAL;
-}
-
-static int icm_switch_off_mclk(const struct motion_sensor_t *s)
-{
-	return icm_field_update8(s, ICM42607_REG_PWR_MGMT0, ICM42607_IDLE, 0);
-}
-
-static int icm_read_mclk_reg(const struct motion_sensor_t *s, const int reg,
-			     int *buf)
-{
-	const int blk_sel = (reg & 0xFF00) >> 8;
-	const int val = reg & 0x00FF;
-	int ret;
-
-	/* optimize by changing BLK_SEL only if not 0 */
-	if (blk_sel) {
-		ret = icm_write8(s, ICM42607_REG_BLK_SEL_R, blk_sel);
-		if (ret)
-			return ret;
-	}
-
-	ret = icm_write8(s, ICM42607_REG_MADDR_R, val);
-	if (ret)
-		return ret;
-
-	udelay(10);
-
-	ret = icm_read8(s, ICM42607_REG_M_R, buf);
-	if (ret)
-		return ret;
-
-	udelay(10);
-
-	if (blk_sel) {
-		ret = icm_write8(s, ICM42607_REG_BLK_SEL_R, 0);
-		if (ret)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int icm_write_mclk_reg(const struct motion_sensor_t *s, const int reg,
-			      const int buf)
-{
-	const int blk_sel = (reg & 0xFF00) >> 8;
-	const int val = reg & 0x00FF;
-	int ret;
-
-	/* optimize by changing BLK_SEL only if not 0 */
-	if (blk_sel) {
-		ret = icm_write8(s, ICM42607_REG_BLK_SEL_W, blk_sel);
-		if (ret)
-			return ret;
-	}
-
-	ret = icm_write8(s, ICM42607_REG_MADDR_W, val);
-	if (ret)
-		return ret;
-
-	ret = icm_write8(s, ICM42607_REG_M_W, buf);
-	if (ret)
-		return ret;
-
-	udelay(10);
-
-	if (blk_sel) {
-		ret = icm_write8(s, ICM42607_REG_BLK_SEL_W, 0);
-		if (ret)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int icm_field_update_mclk_reg(const struct motion_sensor_t *s,
-				     const int reg, const uint8_t field_mask,
-				     const uint8_t set_value)
-{
-	int val, ret;
-
-	ret = icm_read_mclk_reg(s, reg, &val);
-	if (ret)
-		return ret;
-
-	val = (val & ~field_mask) | set_value;
-
-	return icm_write_mclk_reg(s, reg, val);
-}
-
-static int icm42607_normalize(const struct motion_sensor_t *s, intv3_t v,
-			      const uint8_t *raw)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-	int i;
-
-	/* sensor data is configured as little-endian */
-	v[X] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 0);
-	v[Y] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 2);
-	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
-
-	/* check if data is valid */
-	if (v[X] == ICM42607_INVALID_DATA &&
-	    v[Y] == ICM42607_INVALID_DATA &&
-	    v[Z] == ICM42607_INVALID_DATA) {
-		return EC_ERROR_INVAL;
-	}
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	for (i = X; i <= Z; i++)
-		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
-
-	return EC_SUCCESS;
-}
-
-static int icm42607_check_sensor_stabilized(const struct motion_sensor_t *s,
-					    uint32_t ts)
-{
-	int32_t rem;
-
-	rem = icm_get_sensor_stabilized(s, ts);
-	if (rem == 0)
-		return EC_SUCCESS;
-	if (rem > 0)
-		return EC_ERROR_BUSY;
-
-	/* rem < 0: reset check since ts has passed stabilize_ts */
-	icm_reset_stabilize_ts(s);
-	return EC_SUCCESS;
-}
-
-static int __maybe_unused icm42607_flush_fifo(const struct motion_sensor_t *s)
-{
-	int i, val, ret;
-
-	ret = icm_write8(s, ICM42607_REG_SIGNAL_PATH_RESET,
-			 ICM42607_FIFO_FLUSH);
-	if (ret)
-		return ret;
-
-	udelay(10);
-
-	for (i = 0; i < 10; ++i) {
-		ret = icm_read8(s, ICM42607_REG_SIGNAL_PATH_RESET, &val);
-		if (ret)
-			return ret;
-
-		if (!(val & ICM42607_FIFO_FLUSH))
-			return EC_SUCCESS;
-
-		udelay(1);
-	}
-
-	return EC_ERROR_HW_INTERNAL;
-}
-
-/* use FIFO threshold interrupt on INT1 */
-#define ICM42607_FIFO_INT_EN		ICM42607_FIFO_THS_INT1_EN
-#define ICM42607_FIFO_INT_STATUS	ICM42607_FIFO_THS_INT
-
-static int __maybe_unused icm42607_enable_fifo(const struct motion_sensor_t *s,
-					       int enable)
-{
-	int ret;
-
-	if (enable) {
-		/* enable FIFO interrupts */
-		ret = icm_field_update8(s, ICM42607_REG_INT_SOURCE0,
-					ICM42607_FIFO_INT_EN,
-					ICM42607_FIFO_INT_EN);
-		if (ret)
-			return ret;
-
-		/* enable FIFO in streaming mode */
-		ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1,
-				 ICM42607_FIFO_MODE_STREAM);
-		if (ret)
-			return ret;
-	} else {
-		/* disable FIFO interrupts */
-		ret = icm_field_update8(s, ICM42607_REG_INT_SOURCE0,
-					ICM42607_FIFO_INT_EN, 0);
-		if (ret)
-			return ret;
-
-		/* set FIFO in bypass mode */
-		ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1,
-				 ICM42607_FIFO_BYPASS);
-		if (ret)
-			return ret;
-
-		/* flush FIFO data */
-		ret = icm42607_flush_fifo(s);
-		if (ret)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int __maybe_unused icm42607_config_fifo(const struct motion_sensor_t *s,
-					       int enable)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int val;
-	uint8_t old_fifo_en, fifo_en;
-	int ret;
-
-	mutex_lock(s->mutex);
-
-	/* compute new FIFO enable bits and update FIFO config */
-	fifo_en = st->fifo_en;
-	if (enable)
-		fifo_en |= BIT(s->type);
-	else
-		fifo_en &= ~BIT(s->type);
-
-	val = ICM42607_FIFO_WM_GT_TH;
-	if (fifo_en & BIT(MOTIONSENSE_TYPE_ACCEL))
-		val |= ICM42607_FIFO_ACCEL_EN;
-	if (fifo_en & BIT(MOTIONSENSE_TYPE_GYRO))
-		val |= ICM42607_FIFO_GYRO_EN;
-
-	ret = icm_switch_on_mclk(s);
-	if (ret)
-		goto out_unlock;
-
-	ret = icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, val);
-	if (ret)
-		goto out_unlock;
-
-	ret = icm_switch_off_mclk(s);
-	if (ret)
-		goto out_unlock;
-
-	old_fifo_en = st->fifo_en;
-	st->fifo_en = fifo_en;
-
-	if (!old_fifo_en && st->fifo_en) {
-		/* 1st sensor enabled => turn FIFO on */
-		ret = icm42607_enable_fifo(s, 1);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-	} else if (old_fifo_en && !st->fifo_en) {
-		/* last sensor disabled => turn FIFO off */
-		ret = icm42607_enable_fifo(s, 0);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-	}
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static void __maybe_unused icm42607_push_fifo_data(struct motion_sensor_t *s,
-						const uint8_t *raw, uint32_t ts)
-{
-	intv3_t v;
-	struct ec_response_motion_sensor_data vect;
-	int ret;
-
-	if (s == NULL)
-		return;
-
-	ret = icm42607_normalize(s, v, raw);
-	if (ret == EC_SUCCESS) {
-		vect.data[X] = v[X];
-		vect.data[Y] = v[Y];
-		vect.data[Z] = v[Z];
-		vect.flags = 0;
-		vect.sensor_num = s - motion_sensors;
-		motion_sense_fifo_stage_data(&vect, s, 3, ts);
-	}
-}
-
-static int __maybe_unused icm42607_load_fifo(struct motion_sensor_t *s,
-					     uint32_t ts)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int count, i, size;
-	const uint8_t *accel, *gyro;
-	int ret;
-
-	ret = icm_read16(s, ICM42607_REG_FIFO_COUNT, &count);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (count <= 0)
-		return EC_ERROR_INVAL;
-
-	/* flush FIFO if buffer is not large enough */
-	if (count > ICM_FIFO_BUFFER) {
-		CPRINTS("It should not happen, the EC is too slow for the ODR");
-		/* flush FIFO data */
-		ret = icm42607_flush_fifo(s);
-		if (ret)
-			return ret;
-
-		return EC_ERROR_OVERFLOW;
-	}
-
-	ret = icm_read_n(s, ICM42607_REG_FIFO_DATA, st->fifo_buffer, count);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	for (i = 0; i < count; i += size) {
-		size = icm_fifo_decode_packet(&st->fifo_buffer[i],
-				&accel, &gyro);
-		/* exit if error or FIFO is empty */
-		if (size <= 0)
-			return -size;
-		if (accel != NULL) {
-			ret = icm42607_check_sensor_stabilized(s, ts);
-			if (ret == EC_SUCCESS)
-				icm42607_push_fifo_data(s, accel, ts);
-		}
-		if (gyro != NULL) {
-			ret = icm42607_check_sensor_stabilized(s + 1, ts);
-			if (ret == EC_SUCCESS)
-				icm42607_push_fifo_data(s + 1, gyro, ts);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
-/**
- * icm42607_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->icm42607_irq_handler().
- */
-void icm42607_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCELGYRO_ICM42607_INT_EVENT);
-}
-
-/**
- * icm42607_irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- */
-static int icm42607_irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	int status;
-	int ret;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCELGYRO_ICM42607_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	mutex_lock(s->mutex);
-
-	/* read and clear interrupt status */
-	ret = icm_read8(s, ICM42607_REG_INT_STATUS, &status);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		if (status & ICM42607_FIFO_INT_STATUS) {
-			ret = icm42607_load_fifo(s, last_interrupt_timestamp);
-			if (ret == EC_SUCCESS)
-				motion_sense_fifo_commit_data();
-		}
-	}
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm42607_config_interrupt(const struct motion_sensor_t *s)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int val, mask, ret;
-
-	/* configure INT1 pin: push-pull active low */
-	ret = icm_write8(s, ICM42607_REG_INT_CONFIG, ICM42607_INT1_PUSH_PULL);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/* configure FIFO in little endian */
-		mask = ICM42607_FIFO_COUNT_ENDIAN | ICM42607_SENSOR_DATA_ENDIAN;
-		ret = icm_field_update8(s, ICM42607_REG_INTF_CONFIG0, mask, 0);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = icm_switch_on_mclk(s);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/*
-		 * configure FIFO:
-		 * - enable continuous watermark interrupt
-		 * - disable all FIFO en bits
-		 */
-		val = ICM42607_FIFO_WM_GT_TH;
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, val);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		ret = icm_switch_off_mclk(s);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* clear internal FIFO enable bits tracking */
-		st->fifo_en = 0;
-
-		/* set FIFO watermark to 1 data packet (8 bytes) */
-		ret = icm_write16(s, ICM42607_REG_FIFO_WM, 8);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-#endif	/* CONFIG_ACCEL_INTERRUPTS */
-
-static int icm42607_enable_sensor(const struct motion_sensor_t *s, int enable)
-{
-	uint32_t delay, stop_delay;
-	int32_t rem;
-	uint8_t mask;
-	int val;
-	int ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		mask = ICM42607_ACCEL_MODE_MASK;
-		if (enable) {
-			delay = ICM42607_ACCEL_START_TIME;
-			stop_delay = ICM42607_ACCEL_STOP_TIME;
-			val = ICM42607_ACCEL_MODE(ICM42607_MODE_LOW_POWER);
-		} else {
-			delay = ICM42607_ACCEL_STOP_TIME;
-			val = ICM42607_ACCEL_MODE(ICM42607_MODE_OFF);
-		}
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		mask = ICM42607_GYRO_MODE_MASK;
-		if (enable) {
-			delay = ICM42607_GYRO_START_TIME;
-			stop_delay = ICM42607_GYRO_STOP_TIME;
-			val = ICM42607_GYRO_MODE(ICM42607_MODE_LOW_NOISE);
-		} else {
-			delay = ICM42607_GYRO_STOP_TIME;
-			val = ICM42607_GYRO_MODE(ICM42607_MODE_OFF);
-		}
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* check stop delay and sleep if required */
-	if (enable) {
-		rem = icm_get_sensor_stabilized(s, __hw_clock_source_read());
-		/* rem > stop_delay means counter rollover */
-		if (rem > 0 && rem <= stop_delay)
-			usleep(rem);
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, ICM42607_REG_PWR_MGMT0, mask, val);
-	if (ret == EC_SUCCESS) {
-		icm_set_stabilize_ts(s, delay);
-		/* when turning sensor on block any register write for 200 us */
-		if (enable)
-			usleep(200);
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int icm42607_set_data_rate(const struct motion_sensor_t *s, int rate,
-				  int rnd)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-	int reg, reg2, ret, reg_val, reg2_val;
-	int normalized_rate;
-	int max_rate, min_rate;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM42607_REG_ACCEL_CONFIG0;
-		reg2 = ICM42607_REG_ACCEL_CONFIG1;
-		min_rate = ICM42607_ACCEL_MIN_FREQ;
-		max_rate = ICM42607_ACCEL_MAX_FREQ;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM42607_REG_GYRO_CONFIG0;
-		reg2 = ICM42607_REG_GYRO_CONFIG1;
-		min_rate = ICM42607_GYRO_MIN_FREQ;
-		max_rate = ICM42607_GYRO_MAX_FREQ;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	if (rate == 0) {
-		/* disable data in FIFO */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			icm42607_config_fifo(s, 0);
-		/* disable sensor */
-		ret = icm42607_enable_sensor(s, 0);
-		data->odr = 0;
-		return ret;
-	}
-
-	/* normalize the rate */
-	reg_val = ICM42607_ODR_TO_REG(rate);
-	normalized_rate = ICM42607_REG_TO_ODR(reg_val);
-
-	/* round up the rate */
-	if (rnd && (normalized_rate < rate)) {
-		reg_val = ICM42607_ODR_REG_UP(reg_val);
-		normalized_rate = ICM42607_REG_TO_ODR(reg_val);
-	}
-
-	if (rate > 0) {
-		if ((normalized_rate < min_rate) ||
-				(normalized_rate > max_rate))
-			return EC_RES_INVALID_PARAM;
-	}
-
-	reg2_val = ICM42607_ODR_TO_FILT_BW(reg_val);
-
-	mutex_lock(s->mutex);
-
-	/* update filter bandwidth */
-	ret = icm_field_update8(s, reg2, ICM42607_UI_FILT_BW_MASK,
-				ICM42607_UI_FILT_BW_SET(reg2_val));
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	/* update ODR */
-	ret = icm_field_update8(s, reg, ICM42607_ODR_MASK,
-				ICM42607_ODR(reg_val));
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	mutex_unlock(s->mutex);
-
-	if (data->odr == 0) {
-		/* enable sensor */
-		ret = icm42607_enable_sensor(s, 1);
-		if (ret)
-			return ret;
-		/* enable data in FIFO */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			icm42607_config_fifo(s, 1);
-	}
-
-	data->odr = normalized_rate;
-
-	return EC_SUCCESS;
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm42607_set_range(struct motion_sensor_t *s, int range,
-			      int rnd)
-{
-	int reg, ret, reg_val;
-	int newrange;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM42607_REG_ACCEL_CONFIG0;
-		reg_val = ICM42607_ACCEL_FS_TO_REG(range);
-		newrange = ICM42607_ACCEL_REG_TO_FS(reg_val);
-
-		if (rnd && (newrange < range) && (reg_val > 0)) {
-			reg_val--;
-			newrange = ICM42607_ACCEL_REG_TO_FS(reg_val);
-		}
-
-		if (newrange > ICM42607_ACCEL_FS_MAX_VAL) {
-			newrange = ICM42607_ACCEL_FS_MAX_VAL;
-			reg_val = ICM42607_ACCEL_FS_TO_REG(range);
-		}
-
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM42607_REG_GYRO_CONFIG0;
-		reg_val = ICM42607_GYRO_FS_TO_REG(range);
-		newrange = ICM42607_GYRO_REG_TO_FS(reg_val);
-
-		if (rnd && (newrange < range) && (reg_val > 0)) {
-			reg_val--;
-			newrange = ICM42607_GYRO_REG_TO_FS(reg_val);
-		}
-
-		if (newrange > ICM42607_GYRO_FS_MAX_VAL) {
-			newrange = ICM42607_GYRO_FS_MAX_VAL;
-			reg_val = ICM42607_GYRO_FS_TO_REG(newrange);
-		}
-
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, reg, ICM42607_FS_MASK,
-				ICM42607_FS_SEL(reg_val));
-	if (ret == EC_SUCCESS)
-		s->current_range = newrange;
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int icm42607_get_hw_offset(const struct motion_sensor_t *s,
-				  intv3_t offset)
-{
-	uint8_t raw[5];
-	int i, reg, val, ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM42607_MREG_OFFSET_USER4;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM42607_MREG_OFFSET_USER0;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_switch_on_mclk(s);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	for (i = 0; i < sizeof(raw); ++i) {
-		ret = icm_read_mclk_reg(s, reg + i, &val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-		raw[i] = val;
-	}
-
-	ret = icm_switch_off_mclk(s);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	mutex_unlock(s->mutex);
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/*
-		 * raw[0]: Accel X[11:8] | gyro Z[11:8]
-		 * raw[1]: Accel X[7:0]
-		 * raw[2]: Accel Y[7:0]
-		 * raw[3]: Accel Z[11:8] | Accel Y[11:8]
-		 * raw[4]: Accel Z[7:0]
-		 */
-		offset[X] = (((int)raw[0] << 4) & ~GENMASK(7, 0)) | raw[1];
-		offset[Y] = (((int)raw[3] << 8) & ~GENMASK(7, 0)) | raw[2];
-		offset[Z] = (((int)raw[3] << 4) & ~GENMASK(7, 0)) | raw[4];
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/*
-		 * raw[0]: Gyro X[7:0]
-		 * raw[1]: Gyro Y[11:8] | Gyro X[11:8]
-		 * raw[2]: Gyro Y[7:0]
-		 * raw[3]: Gyro Z[7:0]
-		 * raw[4]: Accel X[11:8] | gyro Z[11:8]
-		 */
-		offset[X] = (((int)raw[1] << 8) & ~GENMASK(7, 0)) | raw[0];
-		offset[Y] = (((int)raw[1] << 4) & ~GENMASK(7, 0)) | raw[2];
-		offset[Z] = (((int)raw[4] << 8) & ~GENMASK(7, 0)) | raw[3];
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* Extend sign-bit of 12 bits signed values */
-	for (i = X; i <= Z; ++i)
-		offset[i] = sign_extend(offset[i], 11);
-
-	return EC_SUCCESS;
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm42607_set_hw_offset(const struct motion_sensor_t *s,
-				  intv3_t offset)
-{
-	int i, val, ret;
-
-	/* value is 12 bits signed maximum */
-	for (i = X; i <= Z; ++i) {
-		if (offset[i] > 2047)
-			offset[i] = 2047;
-		else if (offset[i] < -2048)
-			offset[i] = -2048;
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_switch_on_mclk(s);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* Accel X[11:8] | gyro Z[11:8] */
-		val = (offset[X] >> 4) & GENMASK(7, 4);
-		ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OFFSET_USER4,
-						GENMASK(7, 4), val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel X[7:0] */
-		val = offset[X] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER5, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Y[7:0] */
-		val = offset[Y] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER6, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Z[11:8] | Accel Y[11:8] */
-		val = ((offset[Z] >> 4) & GENMASK(7, 4)) |
-		      ((offset[Y] >> 8) & GENMASK(3, 0));
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER7, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Z[7:0] */
-		val = offset[Z] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER8, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-		break;
-
-	case MOTIONSENSE_TYPE_GYRO:
-		/* Gyro X[7:0] */
-		val = offset[X] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER0, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Y[11:8] | Gyro X[11:8] */
-		val = ((offset[Y] >> 4) & GENMASK(7, 4)) |
-		      ((offset[X] >> 8) & GENMASK(3, 0));
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER1, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Y[7:0] */
-		val = offset[Y] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER2, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Z[7:0] */
-		val = offset[Z] & GENMASK(7, 0);
-		ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER3, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel X[11:8] | gyro Z[11:8] */
-		val = (offset[Z] >> 8) & GENMASK(3, 0);
-		ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OFFSET_USER4,
-						GENMASK(3, 0), val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-		break;
-
-	default:
-		ret = EC_ERROR_INVAL;
-		goto out_unlock;
-	}
-
-	ret = icm_switch_off_mclk(s);
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm42607_set_offset(const struct motion_sensor_t *s,
-			       const int16_t *offset, int16_t temp)
-{
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-	int div1, div2;
-	int i;
-
-	/* rotate back to chip frame */
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
-		div1 = 2;
-		div2 = 1;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
-		div1 = 1;
-		div2 = 32;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	for (i = X; i <= Z; ++i)
-		v[i] = round_divide(v[i] * div1, div2);
-
-	return icm42607_set_hw_offset(s, v);
-}
-
-static int icm42607_get_offset(const struct motion_sensor_t *s, int16_t *offset,
-			       int16_t *temp)
-{
-	intv3_t v;
-	int div1, div2;
-	int i, ret;
-
-	ret = icm42607_get_hw_offset(s, v);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
-		div1 = 1;
-		div2 = 2;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
-		div1 = 32;
-		div2 = 1;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	for (i = X; i <= Z; ++i)
-		v[i] = round_divide(v[i] * div1, div2);
-
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-	return EC_SUCCESS;
-}
-
-static int icm42607_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[6];
-	int reg, ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM42607_REG_ACCEL_DATA_XYZ;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM42607_REG_GYRO_DATA_XYZ;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* read data registers if sensor is stabilized */
-	mutex_lock(s->mutex);
-
-	ret = icm42607_check_sensor_stabilized(s, __hw_clock_source_read());
-	if (ret == EC_SUCCESS)
-		ret = icm_read_n(s, reg, raw, sizeof(raw));
-
-	mutex_unlock(s->mutex);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = icm42607_normalize(s, v, raw);
-	/* if data is invalid return the previous read data */
-	if (ret != EC_SUCCESS) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int icm42607_read_temp(const struct motion_sensor_t *s, int *temp_ptr)
-{
-	int val, ret;
-
-	mutex_lock(s->mutex);
-	ret = icm_read16(s, ICM42607_REG_TEMP_DATA, &val);
-	mutex_unlock(s->mutex);
-
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* ensure correct propagation of 16 bits sign bit */
-	val = sign_extend(val, 15);
-
-	if (val == ICM42607_INVALID_DATA)
-		return EC_ERROR_NOT_POWERED;
-
-	*temp_ptr = C_TO_K((val / 128) + 25);
-	return EC_SUCCESS;
-}
-
-static int icm42607_init_config(const struct motion_sensor_t *s)
-{
-	int mask, val, ret;
-
-	ret = icm_switch_on_mclk(s);
-	if (ret)
-		return ret;
-
-	/* Set otp_copy_mode register field */
-	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CONFIG,
-					ICM42607_OTP_COPY_MODE_MASK,
-					ICM42607_OTP_COPY_TRIM);
-	if (ret)
-		return ret;
-
-	/* Set otp_power_down register field to 0 */
-	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CTRL7,
-					ICM42607_OTP_PWR_DOWN, 0);
-	if (ret)
-		return ret;
-
-	/* Wait for 300us for the OTP to fully power up */
-	usleep(300);
-
-	/* Set otp_reload register field */
-	ret = icm_field_update_mclk_reg(s, ICM42607_MREG_OTP_CTRL7,
-					ICM42607_OTP_RELOAD,
-					ICM42607_OTP_RELOAD);
-	if (ret)
-		return ret;
-
-	/* Wait for 280 us for the OTP to load */
-	usleep(280);
-
-	ret = icm_switch_off_mclk(s);
-	if (ret)
-		return ret;
-
-	/* disable i3c support */
-	mask = ICM42607_I3C_SDR_EN | ICM42607_I3C_DDR_EN;
-	ret = icm_field_update8(s, ICM42607_REG_INTF_CONFIG1, mask, 0);
-	if (ret)
-		return ret;
-
-	/* set averaging filter for accel, 8x is max for 400Hz */
-	if (ICM42607_ACCEL_MAX_FREQ == 400000)
-		val = ICM42607_UI_AVG_SET(ICM42607_UI_AVG_8X);
-	else
-		val = ICM42607_UI_AVG_SET(ICM42607_UI_AVG_32X);
-	ret = icm_field_update8(s, ICM42607_REG_ACCEL_CONFIG1,
-				ICM42607_UI_AVG_MASK, val);
-	if (ret)
-		return ret;
-
-	/* disable all interrupts */
-	ret = icm_write8(s, ICM42607_REG_INT_SOURCE0, 0);
-	if (ret)
-		return ret;
-
-	/* disable FIFO */
-	return icm_write8(s, ICM42607_REG_FIFO_CONFIG1, ICM42607_FIFO_BYPASS);
-}
-
-static int icm42607_init(struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *saved_data = ICM_GET_SAVED_DATA(s);
-	int val;
-	int ret, i;
-
-	mutex_lock(s->mutex);
-
-	/* detect chip using whoami */
-	ret = icm_read8(s, ICM42607_REG_WHO_AM_I, &val);
-	if (ret)
-		goto out_unlock;
-
-	if (val != ICM42607_CHIP_ICM42607P) {
-		CPRINTS("Unknown WHO_AM_I: 0x%02x", val);
-		ret = EC_ERROR_ACCESS_DENIED;
-		goto out_unlock;
-	}
-
-	/* first time init done only for 1st sensor (accel) */
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		/* clear status register */
-		ret = icm_read8(s, ICM42607_REG_INT_STATUS, &val);
-		if (ret)
-			goto out_unlock;
-
-		/* Reset to make sure previous state are not there */
-		ret = icm_write8(s, ICM42607_REG_SIGNAL_PATH_RESET,
-				 ICM42607_SOFT_RESET_DEV_CONFIG);
-		if (ret)
-			goto out_unlock;
-
-		/* Check reset is done, 1ms max */
-		for (i = 0; i < 5; ++i) {
-			usleep(200);
-			ret = icm_read8(s, ICM42607_REG_INT_STATUS, &val);
-			if (ret)
-				goto out_unlock;
-			if (val == ICM42607_RESET_DONE_INT)
-				break;
-		}
-		if (val != ICM42607_RESET_DONE_INT) {
-			ret = EC_ERROR_HW_INTERNAL;
-			goto out_unlock;
-		}
-
-		/* configure sensor */
-		ret = icm42607_init_config(s);
-		if (ret)
-			goto out_unlock;
-
-		if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS)) {
-			ret = icm42607_config_interrupt(s);
-			if (ret)
-				goto out_unlock;
-		}
-	}
-
-	for (i = X; i <= Z; i++)
-		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
-
-	saved_data->odr = 0;
-
-	mutex_unlock(s->mutex);
-
-	return sensor_init_done(s);
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-const struct accelgyro_drv icm42607_drv = {
-	.init = icm42607_init,
-	.read = icm42607_read,
-	.read_temp = icm42607_read_temp,
-	.set_range = icm42607_set_range,
-	.get_resolution = icm_get_resolution,
-	.set_data_rate = icm42607_set_data_rate,
-	.get_data_rate = icm_get_data_rate,
-	.set_offset = icm42607_set_offset,
-	.get_offset = icm42607_get_offset,
-	.set_scale = icm_set_scale,
-	.get_scale = icm_get_scale,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = icm42607_irq_handler,
-#endif
-};
diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h
deleted file mode 100644
index 41747fff7a..0000000000
--- a/driver/accelgyro_icm42607.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ICM-42607 accelerometer and gyroscope for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_ICM42607_H
-#define __CROS_EC_ACCELGYRO_ICM42607_H
-
-#include "accelgyro.h"
-#include "common.h"
-
-/*
- * 7-bit address is 110100Xb. Where 'X' is determined
- * by the logic level on pin AP_AD0.
- */
-#define ICM42607_ADDR0_FLAGS		0x68
-#define ICM42607_ADDR1_FLAGS		0x69
-
-/* Min and Max sampling frequency in mHz */
-#define ICM42607_ACCEL_MIN_FREQ		1562
-#define ICM42607_ACCEL_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
-#define ICM42607_GYRO_MIN_FREQ		12500
-#define ICM42607_GYRO_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-
-/* Min and Max Accel FS in g */
-#define ICM42607_ACCEL_FS_MIN_VAL	2
-#define ICM42607_ACCEL_FS_MAX_VAL	16
-
-/* Min and Max Gyro FS in dps */
-#define ICM42607_GYRO_FS_MIN_VAL	250
-#define ICM42607_GYRO_FS_MAX_VAL	2000
-
-/* accel stabilization time in us */
-#define ICM42607_ACCEL_START_TIME	20000
-#define ICM42607_ACCEL_STOP_TIME	0
-
-/* gyro stabilization time in us */
-#define ICM42607_GYRO_START_TIME	40000
-#define ICM42607_GYRO_STOP_TIME		20000
-
-/* Reg value from Accel FS in G */
-#define ICM42607_ACCEL_FS_TO_REG(_fs)	((_fs) <= 2 ? 3 : \
-					 (_fs) >= 16 ? 0 : \
-					 3 - __fls((_fs) / 2))
-
-/* Accel FSR in G from Reg value */
-#define ICM42607_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
-
-/* Reg value from Gyro FS in dps */
-#define ICM42607_GYRO_FS_TO_REG(_fs)	((_fs) <= 250 ? 3 : \
-					 (_fs) >= 2000 ? 0 : \
-					 3 - __fls((_fs) / 250))
-
-/* Gyro FSR in dps from Reg value */
-#define ICM42607_GYRO_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 250)
-
-/* Reg value from ODR in mHz */
-#define ICM42607_ODR_TO_REG(_odr)	((_odr) == 0 ? 0 : \
-					 (__fls(1600000 / (_odr)) + 5))
-
-/* ODR in mHz from Reg value */
-#define ICM42607_REG_TO_ODR(_reg)	((_reg) <= 5 ? 1600000 : \
-					 (1600000 / (1 << ((_reg) - 5))))
-
-/* Reg value for the next higher ODR */
-#define ICM42607_ODR_REG_UP(_reg)	((_reg) - 1)
-
-/*
- * Filter bandwidth values from ODR reg
- *   >= 400Hz (7) -> 180Hz (1)
- *   200Hz (8) -> 73Hz (3)
- *   100Hz (9) -> 53Hz (4)
- *   50Hz (10) -> 25Hz (6)
- *   <= 25Hz (11) -> 16Hz (7)
- */
-#define ICM42607_ODR_TO_FILT_BW(_odr)	((_odr) <= 7 ? 1 : \
-					 (_odr) <= 9 ? (_odr) - 5 : \
-					 (_odr) == 10 ? 6 : \
-					 7)
-
-/*
- * Register addresses are virtual address on 16 bits.
- * MSB is coding block selection value for MREG registers
- * and LSB real register address.
- * ex: MREG2 (block 0x28) register 03 => 0x2803
- */
-#define ICM42607_REG_MCLK_RDY		0x0000
-#define ICM42607_MCLK_RDY		BIT(3)
-
-#define ICM426XX_REG_DEVICE_CONFIG	0x0001
-#define ICM426XX_SPI_MODE_1_2		BIT(0)
-#define ICM426XX_SPI_AP_4WIRE		BIT(2)
-
-#define ICM42607_REG_SIGNAL_PATH_RESET	0x0002
-#define ICM42607_SOFT_RESET_DEV_CONFIG	BIT(4)
-#define ICM42607_FIFO_FLUSH		BIT(2)
-
-#define ICM42607_REG_DRIVE_CONFIG1	0x0003
-
-#define ICM42607_REG_DRIVE_CONFIG2	0x0004
-
-#define ICM42607_REG_DRIVE_CONFIG3	0x0005
-
-/* default int configuration is pulsed mode, open drain, and active low */
-#define ICM42607_REG_INT_CONFIG		0x0006
-#define ICM42607_INT2_MASK		GENMASK(5, 3)
-#define ICM42607_INT2_LATCHED		BIT(5)
-#define ICM42607_INT2_PUSH_PULL		BIT(4)
-#define ICM42607_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM42607_INT1_MASK		GENMASK(2, 0)
-#define ICM42607_INT1_LATCHED		BIT(2)
-#define ICM42607_INT1_PUSH_PULL		BIT(1)
-#define ICM42607_INT1_ACTIVE_HIGH	BIT(0)
-
-/* data are 16 bits */
-#define ICM42607_REG_TEMP_DATA		0x0009
-
-/* X + Y + Z: 3 * 16 bits */
-#define ICM42607_REG_ACCEL_DATA_XYZ	0x000B
-#define ICM42607_REG_GYRO_DATA_XYZ	0x0011
-
-#define ICM42607_INVALID_DATA		-32768
-
-/* data are 16 bits */
-#define ICM42607_REG_TMST_FSYNCH	0x0017
-
-#define ICM42607_REG_PWR_MGMT0		0x001F
-#define ICM42607_ACCEL_LP_CLK_SEL	BIT(7)
-#define ICM42607_IDLE			BIT(4)
-#define ICM42607_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM42607_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM42607_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM42607_ACCEL_MODE(_m)		((_m) & 0x03)
-
-enum icm42607_sensor_mode {
-	ICM42607_MODE_OFF,
-	ICM42607_MODE_STANDBY,
-	ICM42607_MODE_LOW_POWER,
-	ICM42607_MODE_LOW_NOISE,
-};
-
-#define ICM42607_REG_GYRO_CONFIG0	0x0020
-#define ICM42607_REG_ACCEL_CONFIG0	0x0021
-#define ICM42607_FS_MASK		GENMASK(6, 5)
-#define ICM42607_FS_SEL(_fs)		(((_fs) & 0x03) << 5)
-#define ICM42607_ODR_MASK		GENMASK(3, 0)
-#define ICM42607_ODR(_odr)		((_odr) & 0x0F)
-
-#define ICM42607_REG_TEMP_CONFIG0	0x0022
-
-enum icm42607_ui_avg {
-	ICM42607_UI_AVG_2X,
-	ICM42607_UI_AVG_4X,
-	ICM42607_UI_AVG_8X,
-	ICM42607_UI_AVG_16X,
-	ICM42607_UI_AVG_32X,
-	ICM42607_UI_AVG_64X,
-};
-
-enum icm42607_ui_filt_bw {
-	ICM42607_UI_FILT_BW_DISABLED,
-	ICM42607_UI_FILT_BW_180HZ,
-	ICM42607_UI_FILT_BW_121HZ,
-	ICM42607_UI_FILT_BW_73HZ,
-	ICM42607_UI_FILT_BW_53HZ,
-	ICM42607_UI_FILT_BW_34HZ,
-	ICM42607_UI_FILT_BW_25HZ,
-	ICM42607_UI_FILT_BW_16HZ,
-};
-
-#define ICM42607_REG_GYRO_CONFIG1	0x0023
-#define ICM42607_REG_ACCEL_CONFIG1	0x0024
-#define ICM42607_UI_AVG_MASK		GENMASK(6, 4)
-#define ICM42607_UI_AVG_SET(_avg)	(((_avg) & 0x07) << 4)
-#define ICM42607_UI_FILT_BW_MASK	GENMASK(2, 0)
-#define ICM42607_UI_FILT_BW_SET(_filt)	((_filt) & 0x07)
-
-#define ICM42607_REG_FIFO_CONFIG1	0x0028
-#define ICM42607_FIFO_STOP_ON_FULL_MODE	BIT(1)
-#define ICM42607_FIFO_BYPASS		BIT(0)
-#define ICM42607_FIFO_MODE_STREAM	0x00
-
-/* FIFO watermark value is 16 bits little endian */
-#define ICM42607_REG_FIFO_WM		0x0029
-
-#define ICM42607_REG_INT_SOURCE0	0x002B
-#define ICM42607_ST_INT1_EN		BIT(7)
-#define ICM42607_FSYNC_INT1_EN		BIT(6)
-#define ICM42607_PLL_RDY_INT1_EN	BIT(5)
-#define ICM42607_RESET_DONE_INT1_EN	BIT(4)
-#define ICM42607_DRDY_INT1_EN		BIT(3)
-#define ICM42607_FIFO_THS_INT1_EN	BIT(2)
-#define ICM42607_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM42607_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM42607_REG_INTF_CONFIG0	0x0035
-#define ICM42607_FIFO_COUNT_FORMAT	BIT(6)
-#define ICM42607_FIFO_COUNT_ENDIAN	BIT(5)
-#define ICM42607_SENSOR_DATA_ENDIAN	BIT(4)
-
-#define ICM42607_REG_INTF_CONFIG1	0x0036
-#define ICM42607_I3C_SDR_EN		BIT(3)
-#define ICM42607_I3C_DDR_EN		BIT(2)
-#define ICM42607_CLKSEL_MASK		GENMASK(1, 0)
-#define ICM42607_CLKSEL_PLL_ENABLE	0x01
-
-#define ICM42607_REG_INT_STATUS_DRDY	0x0039
-#define ICM42607_DATA_RDY_INT		BIT(0)
-
-#define ICM42607_REG_INT_STATUS		0x003A
-#define ICM42607_ST_INT			BIT(7)
-#define ICM42607_FSYNC_INT		BIT(6)
-#define ICM42607_PLL_RDY_INT		BIT(5)
-#define ICM42607_RESET_DONE_INT		BIT(4)
-#define ICM42607_FIFO_THS_INT		BIT(2)
-#define ICM42607_FIFO_FULL_INT		BIT(1)
-#define ICM42607_AGC_RDY_INT		BIT(0)
-
-/* FIFO count is 16 bits */
-#define ICM42607_REG_FIFO_COUNT		0x003D
-
-#define ICM42607_REG_FIFO_DATA		0x003F
-
-#define ICM42607_REG_APEX_CONFIG0	0x0025
-#define ICM42607_DMP_SRAM_RESET_APEX	BIT(0)
-
-#define ICM42607_REG_APEX_CONFIG1	0x0026
-#define ICM42607_DMP_ODR_50HZ		BIT(1)
-
-#define ICM42607_REG_WHO_AM_I		0x0075
-#define ICM42607_CHIP_ICM42607P		0x60
-
-/* MREG read access registers */
-#define ICM42607_REG_BLK_SEL_W		0x0079
-#define ICM42607_REG_MADDR_W		0x007A
-#define ICM42607_REG_M_W		0x007B
-
-/* MREG write access registers */
-#define ICM42607_REG_BLK_SEL_R		0x007C
-#define ICM42607_REG_MADDR_R		0x007D
-#define ICM42607_REG_M_R		0x007E
-
-/* USER BANK MREG1 */
-#define ICM42607_MREG_FIFO_CONFIG5	0x0001
-#define ICM42607_FIFO_WM_GT_TH		BIT(5)
-#define ICM42607_FIFO_RESUME_PARTIAL_RD	BIT(4)
-#define ICM42607_FIFO_HIRES_EN		BIT(3)
-#define ICM42607_FIFO_TMST_FSYNC_EN	BIT(2)
-#define ICM42607_FIFO_GYRO_EN		BIT(1)
-#define ICM42607_FIFO_ACCEL_EN		BIT(0)
-
-#define ICM42607_MREG_OTP_CONFIG	0x002B
-#define ICM42607_OTP_COPY_MODE_MASK	GENMASK(3, 2)
-#define ICM42607_OTP_COPY_TRIM		(0x01 << 2)
-#define ICM42607_OTP_COPY_ST_DATA	(0x03 << 2)
-
-#define ICM42607_MREG_OFFSET_USER0	0x004E
-#define ICM42607_MREG_OFFSET_USER1	0x004F
-#define ICM42607_MREG_OFFSET_USER2	0x0050
-#define ICM42607_MREG_OFFSET_USER3	0x0051
-#define ICM42607_MREG_OFFSET_USER4	0x0052
-#define ICM42607_MREG_OFFSET_USER5	0x0053
-#define ICM42607_MREG_OFFSET_USER6	0x0054
-#define ICM42607_MREG_OFFSET_USER7	0x0055
-#define ICM42607_MREG_OFFSET_USER8	0x0056
-
-/* USER BANK MREG2 */
-#define ICM42607_MREG_OTP_CTRL7		0x2806
-#define ICM42607_OTP_RELOAD		BIT(3)
-#define ICM42607_OTP_PWR_DOWN		BIT(1)
-
-extern const struct accelgyro_drv icm42607_drv;
-
-void icm42607_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ACCELGYRO_ICM42607_H */
diff --git a/driver/accelgyro_icm426xx.c b/driver/accelgyro_icm426xx.c
deleted file mode 100644
index 5d09c8e4ef..0000000000
--- a/driver/accelgyro_icm426xx.c
+++ /dev/null
@@ -1,981 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * ICM-426xx accelerometer and gyroscope module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "console.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "motion_sense_fifo.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
-			      const uint8_t *raw)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-	int i;
-
-	/* sensor data is configured as little-endian */
-	v[X] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 0);
-	v[Y] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 2);
-	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
-
-	/* check if data is valid */
-	if (v[X] == ICM426XX_INVALID_DATA &&
-	    v[Y] == ICM426XX_INVALID_DATA &&
-	    v[Z] == ICM426XX_INVALID_DATA) {
-		return EC_ERROR_INVAL;
-	}
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	for (i = X; i <= Z; i++)
-		v[i] = SENSOR_APPLY_SCALE(v[i], data->scale[i]);
-
-	return EC_SUCCESS;
-}
-
-static int icm426xx_check_sensor_stabilized(const struct motion_sensor_t *s,
-					    uint32_t ts)
-{
-	int32_t rem;
-
-	rem = icm_get_sensor_stabilized(s, ts);
-	if (rem == 0)
-		return EC_SUCCESS;
-	if (rem > 0)
-		return EC_ERROR_BUSY;
-
-	/* rem < 0: reset check since ts has passed stabilize_ts */
-	icm_reset_stabilize_ts(s);
-	return EC_SUCCESS;
-}
-
-/* use FIFO threshold interrupt on INT1 */
-#define ICM426XX_FIFO_INT_EN		ICM426XX_FIFO_THS_INT1_EN
-#define ICM426XX_FIFO_INT_STATUS	ICM426XX_FIFO_THS_INT
-
-static int __maybe_unused icm426xx_enable_fifo(const struct motion_sensor_t *s,
-					       int enable)
-{
-	int val, ret;
-
-	if (enable) {
-		/* enable FIFO interrupts */
-		ret = icm_field_update8(s, ICM426XX_REG_INT_SOURCE0,
-					ICM426XX_FIFO_INT_EN,
-					ICM426XX_FIFO_INT_EN);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* flush FIFO data */
-		ret = icm_write8(s, ICM426XX_REG_SIGNAL_PATH_RESET,
-				 ICM426XX_FIFO_FLUSH);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* set FIFO in streaming mode */
-		ret = icm_write8(s, ICM426XX_REG_FIFO_CONFIG,
-				 ICM426XX_FIFO_MODE_STREAM);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* workaround: first read of FIFO count is always 0 */
-		ret = icm_read16(s, ICM426XX_REG_FIFO_COUNT, &val);
-		if (ret != EC_SUCCESS)
-			return ret;
-	} else {
-		/* set FIFO in bypass mode */
-		ret = icm_write8(s, ICM426XX_REG_FIFO_CONFIG,
-				 ICM426XX_FIFO_MODE_BYPASS);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* flush FIFO data */
-		ret = icm_write8(s, ICM426XX_REG_SIGNAL_PATH_RESET,
-				 ICM426XX_FIFO_FLUSH);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* disable FIFO interrupts */
-		ret = icm_field_update8(s, ICM426XX_REG_INT_SOURCE0,
-					ICM426XX_FIFO_INT_EN, 0);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int __maybe_unused icm426xx_config_fifo(const struct motion_sensor_t *s,
-					       int enable)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int mask, val;
-	uint8_t old_fifo_en;
-	int ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		mask = ICM426XX_FIFO_ACCEL_EN;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		mask = ICM426XX_FIFO_GYRO_EN;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	/* temperature data has to be always present in the FIFO */
-	mask |= ICM426XX_FIFO_TEMP_EN;
-
-	val = enable ? mask : 0;
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1, mask, val);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	old_fifo_en = st->fifo_en;
-	if (enable)
-		st->fifo_en |= BIT(s->type);
-	else
-		st->fifo_en &= ~BIT(s->type);
-
-	if (!old_fifo_en && st->fifo_en) {
-		/* 1st sensor enabled => turn FIFO on */
-		ret = icm426xx_enable_fifo(s, 1);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-	} else if (old_fifo_en && !st->fifo_en) {
-		/* last sensor disabled => turn FIFO off */
-		ret = icm426xx_enable_fifo(s, 0);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-	}
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static void __maybe_unused icm426xx_push_fifo_data(struct motion_sensor_t *s,
-						const uint8_t *raw, uint32_t ts)
-{
-	intv3_t v;
-	struct ec_response_motion_sensor_data vect;
-	int ret;
-
-	if (s == NULL)
-		return;
-
-	ret = icm426xx_normalize(s, v, raw);
-	if (ret == EC_SUCCESS) {
-		vect.data[X] = v[X];
-		vect.data[Y] = v[Y];
-		vect.data[Z] = v[Z];
-		vect.flags = 0;
-		vect.sensor_num = s - motion_sensors;
-		motion_sense_fifo_stage_data(&vect, s, 3, ts);
-	}
-}
-
-static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s,
-					     uint32_t ts)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int count, i, size;
-	const uint8_t *accel, *gyro;
-	int ret;
-
-	ret = icm_read16(s, ICM426XX_REG_FIFO_COUNT, &count);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (count <= 0)
-		return EC_ERROR_INVAL;
-
-	/* flush FIFO if buffer is not large enough */
-	if (count > ICM_FIFO_BUFFER) {
-		CPRINTS("It should not happen, the EC is too slow for the ODR");
-		ret = icm_write8(s, ICM426XX_REG_SIGNAL_PATH_RESET,
-				 ICM426XX_FIFO_FLUSH);
-		if (ret != EC_SUCCESS)
-			return ret;
-		return EC_ERROR_OVERFLOW;
-	}
-
-	ret = icm_read_n(s, ICM426XX_REG_FIFO_DATA, st->fifo_buffer, count);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	for (i = 0; i < count; i += size) {
-		size = icm_fifo_decode_packet(&st->fifo_buffer[i],
-				&accel, &gyro);
-		/* exit if error or FIFO is empty */
-		if (size <= 0)
-			return -size;
-		if (accel != NULL) {
-			ret = icm426xx_check_sensor_stabilized(st->accel, ts);
-			if (ret == EC_SUCCESS)
-				icm426xx_push_fifo_data(st->accel, accel, ts);
-		}
-		if (gyro != NULL) {
-			ret = icm426xx_check_sensor_stabilized(st->gyro, ts);
-			if (ret == EC_SUCCESS)
-				icm426xx_push_fifo_data(st->gyro, gyro, ts);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-
-/**
- * icm426xx_interrupt - called when the sensor activates the interrupt line.
- *
- * This is a "top half" interrupt handler, it just asks motion sense ask
- * to schedule the "bottom half", ->icm426xx_irq_handler().
- */
-void icm426xx_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE,
-		       CONFIG_ACCELGYRO_ICM426XX_INT_EVENT);
-}
-
-/**
- * icm426xx_irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- */
-static int icm426xx_irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	int status;
-	int ret;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCELGYRO_ICM426XX_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	mutex_lock(s->mutex);
-
-	/* read and clear interrupt status */
-	ret = icm_read8(s, ICM426XX_REG_INT_STATUS, &status);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		if (status & ICM426XX_FIFO_INT_STATUS) {
-			ret = icm426xx_load_fifo(s, last_interrupt_timestamp);
-			if (ret == EC_SUCCESS)
-				motion_sense_fifo_commit_data();
-		}
-	}
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	int val, ret;
-
-	/* configure INT1 pin */
-	val = ICM426XX_INT1_PUSH_PULL;
-	if (s->flags & MOTIONSENSE_FLAG_INT_ACTIVE_HIGH)
-		val |= ICM426XX_INT1_ACTIVE_HIGH;
-
-	ret = icm_write8(s, ICM426XX_REG_INT_CONFIG, val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* deassert async reset for proper INT pin operation */
-	ret = icm_field_update8(s, ICM426XX_REG_INT_CONFIG1,
-				ICM426XX_INT_ASYNC_RESET, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		/*
-		 * configure FIFO:
-		 * - enable FIFO partial read
-		 * - enable continuous watermark interrupt
-		 * - disable all FIFO en bits
-		 */
-		val = ICM426XX_FIFO_PARTIAL_READ | ICM426XX_FIFO_WM_GT_TH;
-		ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1,
-					GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK,
-					val);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		/* clear internal FIFO enable bits tracking */
-		st->fifo_en = 0;
-
-		/* set FIFO watermark to 1 data packet (8 bytes) */
-		ret = icm_write16(s, ICM426XX_REG_FIFO_WATERMARK, 8);
-		if (ret != EC_SUCCESS)
-			return ret;
-	}
-
-	return ret;
-}
-
-#endif	/* CONFIG_ACCEL_INTERRUPTS */
-
-static int icm426xx_enable_sensor(const struct motion_sensor_t *s, int enable)
-{
-	uint32_t delay, stop_delay;
-	int32_t rem;
-	uint8_t mask, val;
-	int ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		mask = ICM426XX_ACCEL_MODE_MASK;
-		if (enable) {
-			delay = ICM426XX_ACCEL_START_TIME;
-			stop_delay = ICM426XX_ACCEL_STOP_TIME;
-			val = ICM426XX_ACCEL_MODE(ICM426XX_MODE_LOW_POWER);
-		} else {
-			delay = ICM426XX_ACCEL_STOP_TIME;
-			val = ICM426XX_ACCEL_MODE(ICM426XX_MODE_OFF);
-		}
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		mask = ICM426XX_GYRO_MODE_MASK;
-		if (enable) {
-			delay = ICM426XX_GYRO_START_TIME;
-			stop_delay = ICM426XX_GYRO_STOP_TIME;
-			val = ICM426XX_GYRO_MODE(ICM426XX_MODE_LOW_NOISE);
-		} else {
-			delay = ICM426XX_GYRO_STOP_TIME;
-			val = ICM426XX_GYRO_MODE(ICM426XX_MODE_OFF);
-		}
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* check stop delay and sleep if required */
-	if (enable) {
-		rem = icm_get_sensor_stabilized(s, __hw_clock_source_read());
-		/* rem > stop_delay means counter rollover */
-		if (rem > 0 && rem <= stop_delay)
-			usleep(rem);
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, ICM426XX_REG_PWR_MGMT0, mask, val);
-	if (ret == EC_SUCCESS) {
-		icm_set_stabilize_ts(s, delay);
-		/* when turning sensor on block any register write for 200 us */
-		if (enable)
-			usleep(200);
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
-				  int rnd)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-	int reg, ret, reg_val;
-	int normalized_rate;
-	int max_rate, min_rate;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM426XX_REG_ACCEL_CONFIG0;
-		min_rate = ICM426XX_ACCEL_MIN_FREQ;
-		max_rate = ICM426XX_ACCEL_MAX_FREQ;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM426XX_REG_GYRO_CONFIG0;
-		min_rate = ICM426XX_GYRO_MIN_FREQ;
-		max_rate = ICM426XX_GYRO_MAX_FREQ;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/* normalize the rate */
-	reg_val = ICM426XX_ODR_TO_REG(rate);
-	normalized_rate = ICM426XX_REG_TO_ODR(reg_val);
-
-	/* round up the rate */
-	if (rnd && (normalized_rate < rate)) {
-		reg_val = ICM426XX_ODR_REG_UP(reg_val);
-		normalized_rate = ICM426XX_REG_TO_ODR(reg_val);
-	}
-
-	if (rate > 0) {
-		if ((normalized_rate < min_rate) ||
-			(normalized_rate > max_rate))
-			return EC_RES_INVALID_PARAM;
-	}
-
-	if (rate == 0) {
-		/* disable data in FIFO */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			icm426xx_config_fifo(s, 0);
-		/* disable sensor */
-		ret = icm426xx_enable_sensor(s, 0);
-		data->odr = 0;
-		return ret;
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, reg, ICM426XX_ODR_MASK,
-				ICM426XX_ODR(reg_val));
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	mutex_unlock(s->mutex);
-
-	if (data->odr == 0) {
-		/* enable sensor */
-		ret = icm426xx_enable_sensor(s, 1);
-		if (ret)
-			return ret;
-		/* enable data in FIFO */
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			icm426xx_config_fifo(s, 1);
-	}
-
-	data->odr = normalized_rate;
-	return EC_SUCCESS;
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm426xx_set_range(struct motion_sensor_t *s, int range,
-			      int rnd)
-{
-	int reg, ret, reg_val;
-	int newrange;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM426XX_REG_ACCEL_CONFIG0;
-
-		reg_val = ICM426XX_ACCEL_FS_TO_REG(range);
-		newrange = ICM426XX_ACCEL_REG_TO_FS(reg_val);
-
-		if (rnd && (newrange < range) && (reg_val > 0)) {
-			reg_val--;
-			newrange = ICM426XX_ACCEL_REG_TO_FS(reg_val);
-		}
-
-		if (newrange > ICM426XX_ACCEL_FS_MAX_VAL) {
-			newrange = ICM426XX_ACCEL_FS_MAX_VAL;
-			reg_val = ICM426XX_ACCEL_FS_TO_REG(range);
-		}
-
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM426XX_REG_GYRO_CONFIG0;
-
-		reg_val = ICM426XX_GYRO_FS_TO_REG(range);
-		newrange = ICM426XX_GYRO_REG_TO_FS(reg_val);
-
-		if (rnd && (newrange < range) && (reg_val > 0)) {
-			reg_val--;
-			newrange = ICM426XX_GYRO_REG_TO_FS(reg_val);
-		}
-
-		if (newrange > ICM426XX_GYRO_FS_MAX_VAL) {
-			newrange = ICM426XX_GYRO_FS_MAX_VAL;
-			reg_val = ICM426XX_GYRO_FS_TO_REG(newrange);
-		}
-
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	mutex_lock(s->mutex);
-
-	ret = icm_field_update8(s, reg, ICM426XX_FS_MASK,
-				ICM426XX_FS_SEL(reg_val));
-	if (ret == EC_SUCCESS)
-		s->current_range = newrange;
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int icm426xx_get_hw_offset(const struct motion_sensor_t *s,
-				  intv3_t offset)
-{
-	uint8_t raw[5];
-	int i, ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4,
-				raw, sizeof(raw));
-		mutex_unlock(s->mutex);
-		if (ret != EC_SUCCESS)
-			return ret;
-		/*
-		 * raw[0]: Accel X[11:8] | gyro Z[11:8]
-		 * raw[1]: Accel X[0:7]
-		 * raw[2]: Accel Y[7:0]
-		 * raw[3]: Accel Z[11:8] | Accel Y[11:8]
-		 * raw[4]: Accel Z[7:0]
-		 */
-		offset[X] = (((int)raw[0] << 4) & ~GENMASK(7, 0)) | raw[1];
-		offset[Y] = (((int)raw[3] << 8) & ~GENMASK(7, 0)) | raw[2];
-		offset[Z] = (((int)raw[3] << 4) & ~GENMASK(7, 0)) | raw[4];
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0,
-				raw, sizeof(raw));
-		mutex_unlock(s->mutex);
-		if (ret != EC_SUCCESS)
-			return ret;
-		/*
-		 * raw[0]: Gyro X[7:0]
-		 * raw[1]: Gyro Y[11:8] | Gyro X[11:8]
-		 * raw[2]: Gyro Y[7:0]
-		 * raw[3]: Gyro Z[7:0]
-		 * raw[4]: Accel X[11:8] | gyro Z[11:8]
-		 */
-		offset[X] = (((int)raw[1] << 8) & ~GENMASK(7, 0)) | raw[0];
-		offset[Y] = (((int)raw[1] << 4) & ~GENMASK(7, 0)) | raw[2];
-		offset[Z] = (((int)raw[4] << 8) & ~GENMASK(7, 0)) | raw[3];
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* Extend sign-bit of 12 bits signed values */
-	for (i = X; i <= Z; ++i)
-		offset[i] = sign_extend(offset[i], 11);
-
-	return EC_SUCCESS;
-}
-
-static int icm426xx_set_hw_offset(const struct motion_sensor_t *s,
-				  intv3_t offset)
-{
-	int i, val, ret;
-
-	/* value is 12 bits signed maximum */
-	for (i = X; i <= Z; ++i) {
-		if (offset[i] > 2047)
-			offset[i] = 2047;
-		else if (offset[i] < -2048)
-			offset[i] = -2048;
-	}
-
-	mutex_lock(s->mutex);
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* Accel X[11:8] | gyro Z[11:8] */
-		val = (offset[X] >> 4) & GENMASK(7, 4);
-		ret = icm_field_update8(s, ICM426XX_REG_OFFSET_USER4,
-					GENMASK(7, 4), val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel X[7:0] */
-		val = offset[X] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER5, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Y[7:0] */
-		val = offset[Y] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER6, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Z[11:8] | Accel Y[11:8] */
-		val = ((offset[Z] >> 4) & GENMASK(7, 4)) |
-		      ((offset[Y] >> 8) & GENMASK(3, 0));
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER7, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel Z[7:0] */
-		val = offset[Z] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER8, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-		break;
-
-	case MOTIONSENSE_TYPE_GYRO:
-		/* Gyro X[7:0] */
-		val = offset[X] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER0, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Y[11:8] | Gyro X[11:8] */
-		val = ((offset[Y] >> 4) & GENMASK(7, 4)) |
-		      ((offset[X] >> 8) & GENMASK(3, 0));
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER1, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Y[7:0] */
-		val = offset[Y] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER2, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Gyro Z[7:0] */
-		val = offset[Z] & GENMASK(7, 0);
-		ret = icm_write8(s, ICM426XX_REG_OFFSET_USER3, val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-
-		/* Accel X[11:8] | gyro Z[11:8] */
-		val = (offset[Z] >> 8) & GENMASK(3, 0);
-		ret = icm_field_update8(s, ICM426XX_REG_OFFSET_USER4,
-					GENMASK(3, 0), val);
-		if (ret != EC_SUCCESS)
-			goto out_unlock;
-		break;
-
-	default:
-		ret = EC_ERROR_INVAL;
-		break;
-	}
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int icm426xx_set_offset(const struct motion_sensor_t *s,
-			       const int16_t *offset, int16_t temp)
-{
-	intv3_t v = { offset[X], offset[Y], offset[Z] };
-	int div1, div2;
-	int i;
-
-	/* rotate back to chip frame */
-	rotate_inv(v, *s->rot_standard_ref, v);
-
-	/* convert raw data to hardware offset units */
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
-		div1 = 2;
-		div2 = 1;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
-		div1 = 1;
-		div2 = 32;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	for (i = X; i <= Z; ++i)
-		v[i] = round_divide(v[i] * div1, div2);
-
-	return icm426xx_set_hw_offset(s, v);
-}
-
-static int icm426xx_get_offset(const struct motion_sensor_t *s, int16_t *offset,
-			       int16_t *temp)
-{
-	intv3_t v;
-	int div1, div2;
-	int i, ret;
-
-	ret = icm426xx_get_hw_offset(s, v);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* transform offset to raw data */
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* hardware offset is 1/2048g /LSB, EC offset 1/1024g /LSB. */
-		div1 = 1;
-		div2 = 2;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		/* hardware offset is 1/32dps /LSB, EC offset 1/1024dps /LSB. */
-		div1 = 32;
-		div2 = 1;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	for (i = X; i <= Z; ++i)
-		v[i] = round_divide(v[i] * div1, div2);
-
-	rotate(v, *s->rot_standard_ref, v);
-	offset[X] = v[X];
-	offset[Y] = v[Y];
-	offset[Z] = v[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int icm426xx_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[6];
-	int reg, ret;
-
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		reg = ICM426XX_REG_ACCEL_DATA_XYZ;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		reg = ICM426XX_REG_GYRO_DATA_XYZ;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/* read data registers if sensor is stabilized */
-	mutex_lock(s->mutex);
-
-	ret = icm426xx_check_sensor_stabilized(s, __hw_clock_source_read());
-	if (ret == EC_SUCCESS)
-		ret = icm_read_n(s, reg, raw, sizeof(raw));
-
-	mutex_unlock(s->mutex);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = icm426xx_normalize(s, v, raw);
-	/* if data is invalid return the previous read data */
-	if (ret != EC_SUCCESS) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int icm426xx_read_temp(const struct motion_sensor_t *s, int *temp_ptr)
-{
-	int val, ret;
-
-	mutex_lock(s->mutex);
-	ret = icm_read16(s, ICM426XX_REG_TEMP_DATA, &val);
-	mutex_unlock(s->mutex);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* ensure correct propagation of 16 bits sign bit */
-	val = sign_extend(val, 15);
-
-	if (val == ICM426XX_INVALID_DATA)
-		return EC_ERROR_NOT_POWERED;
-
-	*temp_ptr = C_TO_K((val * 100) / 13248 + 25);
-	return EC_SUCCESS;
-}
-
-static int icm426xx_init_config(const struct motion_sensor_t *s)
-{
-	uint8_t mask, val;
-	int ret;
-
-	/*
-	 * serial bus setup (i2c or spi)
-	 *
-	 * Do not check result for INTF_CONFIG6, since it can induce
-	 * interferences on the bus.
-	 */
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	icm_field_update8(
-		s, ICM426XX_REG_INTF_CONFIG6, ICM426XX_INTF_CONFIG6_MASK,
-		ICM426XX_I3C_EN | ICM426XX_I3C_SDR_EN | ICM426XX_I3C_DDR_EN);
-	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
-				ICM426XX_I3C_BUS_MODE, ICM426XX_I3C_BUS_MODE);
-#else
-	icm_field_update8(s, ICM426XX_REG_INTF_CONFIG6,
-			  ICM426XX_INTF_CONFIG6_MASK, ICM426XX_I3C_EN);
-	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG4,
-				ICM426XX_I3C_BUS_MODE, 0);
-#endif
-	if (ret)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	ret = icm_field_update8(
-		s, ICM426XX_REG_DRIVE_CONFIG, ICM426XX_DRIVE_CONFIG_MASK,
-		ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_20NS_60NS) |
-			ICM426XX_SPI_SLEW_RATE(ICM426XX_SLEW_RATE_INF_2NS));
-#else
-	ret = icm_field_update8(
-		s, ICM426XX_REG_DRIVE_CONFIG, ICM426XX_DRIVE_CONFIG_MASK,
-		ICM426XX_I2C_SLEW_RATE(ICM426XX_SLEW_RATE_12NS_36NS) |
-			ICM426XX_SPI_SLEW_RATE(ICM426XX_SLEW_RATE_12NS_36NS));
-#endif
-	if (ret)
-		return ret;
-
-	/*
-	 * Use invalid value in registers and FIFO.
-	 * Data registers in little-endian format.
-	 * Disable unused serial interface.
-	 */
-	mask = ICM426XX_DATA_CONF_MASK | ICM426XX_UI_SIFS_CFG_MASK;
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	val = ICM426XX_UI_SIFS_CFG_I2C_DIS;
-#else
-	val = ICM426XX_UI_SIFS_CFG_SPI_DIS;
-#endif
-
-	ret = icm_field_update8(s, ICM426XX_REG_INTF_CONFIG0, mask, val);
-	if (ret)
-		return ret;
-
-	/* set accel oscillator to RC clock to avoid bad transition with PLL */
-	return icm_field_update8(s, ICM426XX_REG_INTF_CONFIG1,
-				 ICM426XX_ACCEL_LP_CLK_SEL,
-				 ICM426XX_ACCEL_LP_CLK_SEL);
-}
-
-static int icm426xx_init(struct motion_sensor_t *s)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	struct accelgyro_saved_data_t *saved_data = ICM_GET_SAVED_DATA(s);
-	int mask, val;
-	int ret, i;
-
-	mutex_lock(s->mutex);
-
-	/* manually force register bank to 0 */
-	st->bank = 0;
-	ret = icm_write8(s, ICM426XX_REG_BANK_SEL, ICM426XX_BANK_SEL(0));
-	if (ret)
-		goto out_unlock;
-
-	/* detect chip using whoami */
-	ret = icm_read8(s, ICM426XX_REG_WHO_AM_I, &val);
-	if (ret)
-		goto out_unlock;
-
-	if (val != ICM426XX_CHIP_ICM40608 && val != ICM426XX_CHIP_ICM42605) {
-		CPRINTS("Unknown WHO_AM_I: 0x%02x", val);
-		ret = EC_ERROR_ACCESS_DENIED;
-		goto out_unlock;
-	}
-
-	/* first time init done only for 1st sensor (accel) */
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		/* reset the chip and verify it is ready */
-		ret = icm_write8(s, ICM426XX_REG_DEVICE_CONFIG,
-				 ICM426XX_SOFT_RESET_CONFIG);
-		if (ret)
-			goto out_unlock;
-		msleep(1);
-
-		ret = icm_read8(s, ICM426XX_REG_INT_STATUS, &val);
-		if (ret)
-			goto out_unlock;
-		if (!(val & ICM426XX_RESET_DONE_INT)) {
-			ret = EC_ERROR_ACCESS_DENIED;
-			goto out_unlock;
-		}
-
-		/* configure sensor */
-		ret = icm426xx_init_config(s);
-		if (ret)
-			goto out_unlock;
-
-		if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS))
-			ret = icm426xx_config_interrupt(s);
-		if (ret)
-			goto out_unlock;
-	}
-
-	for (i = X; i <= Z; i++)
-		saved_data->scale[i] = MOTION_SENSE_DEFAULT_SCALE;
-
-	saved_data->odr = 0;
-
-	/* set sensor filter */
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		mask = ICM426XX_ACCEL_UI_FILT_MASK;
-		val = ICM426XX_ACCEL_UI_FILT_BW(ICM426XX_FILTER_BW_AVG_16X);
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			st->accel = (struct motion_sensor_t *)s;
-		break;
-	case MOTIONSENSE_TYPE_GYRO:
-		mask = ICM426XX_GYRO_UI_FILT_MASK;
-		val = ICM426XX_GYRO_UI_FILT_BW(ICM426XX_FILTER_BW_ODR_DIV_2);
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			st->gyro = (struct motion_sensor_t *)s;
-		break;
-	default:
-		ret = EC_ERROR_INVAL;
-		goto out_unlock;
-	}
-	ret = icm_field_update8(s, ICM426XX_REG_GYRO_ACCEL_CONFIG0, mask, val);
-	if (ret != EC_SUCCESS)
-		goto out_unlock;
-
-	mutex_unlock(s->mutex);
-
-	return sensor_init_done(s);
-
-out_unlock:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-const struct accelgyro_drv icm426xx_drv = {
-	.init = icm426xx_init,
-	.read = icm426xx_read,
-	.read_temp = icm426xx_read_temp,
-	.set_range = icm426xx_set_range,
-	.get_resolution = icm_get_resolution,
-	.set_data_rate = icm426xx_set_data_rate,
-	.get_data_rate = icm_get_data_rate,
-	.set_offset = icm426xx_set_offset,
-	.get_offset = icm426xx_get_offset,
-	.set_scale = icm_set_scale,
-	.get_scale = icm_get_scale,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = icm426xx_irq_handler,
-#endif
-};
diff --git a/driver/accelgyro_icm426xx.h b/driver/accelgyro_icm426xx.h
deleted file mode 100644
index bcda1174b2..0000000000
--- a/driver/accelgyro_icm426xx.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ICM-426xx accelerometer and gyroscope for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_ICM426XX_H
-#define __CROS_EC_ACCELGYRO_ICM426XX_H
-
-#include "accelgyro.h"
-#include "common.h"
-
-/*
- * 7-bit address is 110100Xb. Where 'X' is determined
- * by the logic level on pin AP_AD0.
- */
-#define ICM426XX_ADDR0_FLAGS		0x68
-#define ICM426XX_ADDR1_FLAGS		0x69
-
-/* Min and Max sampling frequency in mHz */
-#define ICM426XX_ACCEL_MIN_FREQ	3125
-#define ICM426XX_ACCEL_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(500000, 100000)
-#define ICM426XX_GYRO_MIN_FREQ	12500
-#define ICM426XX_GYRO_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000)
-
-/* Min and Max Accel FS in G */
-#define ICM426XX_ACCEL_FS_MIN_VAL	2
-#define ICM426XX_ACCEL_FS_MAX_VAL	16
-
-/* Min and Max Gyro FS in dps */
-#define ICM426XX_GYRO_FS_MIN_VAL	125
-#define ICM426XX_GYRO_FS_MAX_VAL	2000
-
-/* accel stabilization time in us */
-#define ICM426XX_ACCEL_START_TIME	20000
-#define ICM426XX_ACCEL_STOP_TIME	0
-
-/* gyro stabilization time in us */
-#define ICM426XX_GYRO_START_TIME	60000
-#define ICM426XX_GYRO_STOP_TIME		150000
-
-/* Reg value from Accel FS in G */
-#define ICM426XX_ACCEL_FS_TO_REG(_fs)	((_fs) < 2 ? 3 : \
-					(_fs) > 16 ? 0 : \
-					3 - __fls((_fs) / 2))
-
-/* Accel FSR in G from Reg value */
-#define ICM426XX_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
-
-/* Reg value from Gyro FS in dps */
-#define ICM426XX_GYRO_FS_TO_REG(_fs)	((_fs) < 125 ? 4 : \
-					(_fs) > 2000 ? 0 : \
-					4 - __fls((_fs) / 125))
-
-/* Gyro FSR in dps from Reg value */
-#define ICM426XX_GYRO_REG_TO_FS(_reg)	((1 << (4 - (_reg))) * 125)
-
-/* Reg value from ODR in mHz */
-#define ICM426XX_ODR_TO_REG(_odr)	((_odr) <= 200000 ? \
-					13 - __fls((_odr) / 3125) : \
-					(_odr) < 500000 ? 7 : \
-					(_odr) < 1000000 ? 15 : \
-					6 - __fls((_odr) / 1000000))
-
-/* ODR in mHz from Reg value */
-#define ICM426XX_REG_TO_ODR(_reg)	((_reg) == 15 ? 500000 : \
-					(_reg) >= 7 ? \
-					(1 << (13 - (_reg))) * 3125 : \
-					(1 << (6 - (_reg))) * 1000000)
-
-/* Reg value for the next higher ODR */
-#define ICM426XX_ODR_REG_UP(_reg)	((_reg) == 15 ? 6 : \
-					(_reg) == 7 ? 15 : \
-					(_reg) - 1)
-
-/*
- * Register addresses are virtual address on 16 bits.
- * MSB is coding register bank and LSB real register address.
- * ex: bank 4, register 1F => 0x041F
- */
-#define ICM426XX_REG_DEVICE_CONFIG	0x0011
-#define ICM426XX_SOFT_RESET_CONFIG	BIT(0)
-
-enum icm426xx_slew_rate {
-	ICM426XX_SLEW_RATE_20NS_60NS,
-	ICM426XX_SLEW_RATE_12NS_36NS,
-	ICM426XX_SLEW_RATE_6NS_18NS,
-	ICM426XX_SLEW_RATE_4NS_12NS,
-	ICM426XX_SLEW_RATE_2NS_6NS,
-	ICM426XX_SLEW_RATE_INF_2NS,
-};
-#define ICM426XX_REG_DRIVE_CONFIG	0x0013
-#define ICM426XX_DRIVE_CONFIG_MASK	GENMASK(5, 0)
-#define ICM426XX_I2C_SLEW_RATE(_s)	(((_s) & 0x07) << 3)
-#define ICM426XX_SPI_SLEW_RATE(_s)	((_s) & 0x07)
-
-/* default int configuration is pulsed mode, open drain, and active low */
-#define ICM426XX_REG_INT_CONFIG		0x0014
-#define ICM426XX_INT2_LATCHED		BIT(5)
-#define ICM426XX_INT2_PUSH_PULL		BIT(4)
-#define ICM426XX_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM426XX_INT1_LATCHED		BIT(2)
-#define ICM426XX_INT1_PUSH_PULL		BIT(1)
-#define ICM426XX_INT1_ACTIVE_HIGH	BIT(0)
-
-#define ICM426XX_REG_FIFO_CONFIG	0x0016
-#define ICM426XX_FIFO_MODE_BYPASS	(0x00 << 6)
-#define ICM426XX_FIFO_MODE_STREAM	(0x01 << 6)
-#define ICM426XX_FIFO_MODE_STOP_FULL	(0x02 << 6)
-
-/* data are 16 bits */
-#define ICM426XX_REG_TEMP_DATA		0x001D
-/* X + Y + Z: 3 * 16 bits */
-#define ICM426XX_REG_ACCEL_DATA_XYZ	0x001F
-#define ICM426XX_REG_GYRO_DATA_XYZ	0x0025
-
-#define ICM426XX_INVALID_DATA		-32768
-
-#define ICM426XX_REG_INT_STATUS		0x002D
-#define ICM426XX_UI_FSYNC_INT		BIT(6)
-#define ICM426XX_PLL_RDY_INT		BIT(5)
-#define ICM426XX_RESET_DONE_INT		BIT(4)
-#define ICM426XX_DATA_RDY_INT		BIT(3)
-#define ICM426XX_FIFO_THS_INT		BIT(2)
-#define ICM426XX_FIFO_FULL_INT		BIT(1)
-#define ICM426XX_AGC_RDY_INT		BIT(0)
-
-/* FIFO count is 16 bits */
-#define ICM426XX_REG_FIFO_COUNT		0x002E
-#define ICM426XX_REG_FIFO_DATA		0x0030
-
-#define ICM426XX_REG_SIGNAL_PATH_RESET	0x004B
-#define ICM426XX_ABORT_AND_RESET	BIT(3)
-#define ICM426XX_TMST_STROBE		BIT(2)
-#define ICM426XX_FIFO_FLUSH		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG0	0x004C
-#define ICM426XX_DATA_CONF_MASK		GENMASK(7, 4)
-#define ICM426XX_FIFO_HOLD_LAST_DATA	BIT(7)
-#define ICM426XX_FIFO_COUNT_REC		BIT(6)
-#define ICM426XX_FIFO_COUNT_BE		BIT(5)
-#define ICM426XX_SENSOR_DATA_BE		BIT(4)
-#define ICM426XX_UI_SIFS_CFG_MASK	GENMASK(1, 0)
-#define ICM426XX_UI_SIFS_CFG_SPI_DIS	0x02
-#define ICM426XX_UI_SIFS_CFG_I2C_DIS	0x03
-
-#define ICM426XX_REG_INTF_CONFIG1	0x004D
-#define ICM426XX_ACCEL_LP_CLK_SEL	BIT(3)
-
-enum icm426xx_sensor_mode {
-	ICM426XX_MODE_OFF,
-	ICM426XX_MODE_STANDBY,
-	ICM426XX_MODE_LOW_POWER,
-	ICM426XX_MODE_LOW_NOISE,
-};
-#define ICM426XX_REG_PWR_MGMT0		0x004E
-#define ICM426XX_TEMP_DIS		BIT(5)
-#define ICM426XX_IDLE			BIT(4)
-#define ICM426XX_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM426XX_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM426XX_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM426XX_ACCEL_MODE(_m)		((_m) & 0x03)
-
-#define ICM426XX_REG_GYRO_CONFIG0	0x004F
-#define ICM426XX_REG_ACCEL_CONFIG0	0x0050
-#define ICM426XX_FS_MASK		GENMASK(7, 5)
-#define ICM426XX_FS_SEL(_fs)		(((_fs) & 0x07) << 5)
-#define ICM426XX_ODR_MASK		GENMASK(3, 0)
-#define ICM426XX_ODR(_odr)		((_odr) & 0x0F)
-
-enum icm426xx_filter_bw {
-	/* low noise mode */
-	ICM426XX_FILTER_BW_ODR_DIV_2 = 0,
-
-	/* low power mode */
-	ICM426XX_FILTER_BW_AVG_1X = 1,
-	ICM426XX_FILTER_BW_AVG_16X = 6,
-};
-
-#define ICM426XX_REG_GYRO_ACCEL_CONFIG0	0x0052
-#define ICM426XX_ACCEL_UI_FILT_MASK	GENMASK(7, 4)
-#define ICM426XX_ACCEL_UI_FILT_BW(_f)	(((_f) & 0x0F) << 4)
-#define ICM426XX_GYRO_UI_FILT_MASK	GENMASK(3, 0)
-#define ICM426XX_GYRO_UI_FILT_BW(_f)	((_f) & 0x0F)
-
-#define ICM426XX_REG_FIFO_CONFIG1	0x005F
-#define ICM426XX_FIFO_PARTIAL_READ	BIT(6)
-#define ICM426XX_FIFO_WM_GT_TH		BIT(5)
-#define ICM426XX_FIFO_EN_MASK		GENMASK(3, 0)
-#define ICM426XX_FIFO_TMST_FSYNC_EN	BIT(3)
-#define ICM426XX_FIFO_TEMP_EN		BIT(2)
-#define ICM426XX_FIFO_GYRO_EN		BIT(1)
-#define ICM426XX_FIFO_ACCEL_EN		BIT(0)
-
-/* FIFO watermark value is 16 bits little endian */
-#define ICM426XX_REG_FIFO_WATERMARK	0x0060
-
-#define ICM426XX_REG_INT_CONFIG1	0x0064
-#define ICM426XX_INT_PULSE_DURATION	BIT(6)
-#define ICM426XX_INT_TDEASSERT_DIS	BIT(5)
-#define ICM426XX_INT_ASYNC_RESET	BIT(4)
-
-#define ICM426XX_REG_INT_SOURCE0	0x0065
-#define ICM426XX_UI_FSYNC_INT1_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT1_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT1_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT1_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT1_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE3	0x0068
-#define ICM426XX_UI_FSYNC_INT2_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT2_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT2_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT2_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT2_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT2_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT2_EN	BIT(0)
-
-#define ICM426XX_REG_WHO_AM_I		0x0075
-#define ICM426XX_CHIP_ICM40608		0x39
-#define ICM426XX_CHIP_ICM42605		0x42
-
-#define ICM426XX_REG_BANK_SEL		0x0076
-#define ICM426XX_BANK_SEL(_b)		((_b) & 0x07)
-
-#define ICM426XX_REG_INTF_CONFIG4	0x017A
-#define ICM426XX_I3C_BUS_MODE		BIT(6)
-#define ICM426XX_SPI_AP_4WIRE		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG5	0x017B
-#define ICM426XX_PIN9_FUNC_INT2		(0x00 << 1)
-#define ICM426XX_PIN9_FUNC_FSYNC	(0x01 << 1)
-
-#define ICM426XX_REG_INTF_CONFIG6	0x017C
-#define ICM426XX_INTF_CONFIG6_MASK	GENMASK(4, 0)
-#define ICM426XX_I3C_EN			BIT(4)
-#define ICM426XX_I3C_IBI_BYTE_EN	BIT(3)
-#define ICM426XX_I3C_IBI_EN		BIT(2)
-#define ICM426XX_I3C_DDR_EN		BIT(1)
-#define ICM426XX_I3C_SDR_EN		BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE8	0x044F
-#define ICM426XX_FSYNC_IBI_EN		BIT(5)
-#define ICM426XX_PLL_RDY_IBI_EN		BIT(4)
-#define ICM426XX_UI_DRDY_IBI_EN		BIT(3)
-#define ICM426XX_FIFO_THS_IBI_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_IBI_EN	BIT(1)
-#define ICM426XX_AGC_RDY_IBI_EN		BIT(0)
-
-#define ICM426XX_REG_OFFSET_USER0	0x0477
-#define ICM426XX_REG_OFFSET_USER1	0x0478
-#define ICM426XX_REG_OFFSET_USER2	0x0479
-#define ICM426XX_REG_OFFSET_USER3	0x047A
-#define ICM426XX_REG_OFFSET_USER4	0x047B
-#define ICM426XX_REG_OFFSET_USER5	0x047C
-#define ICM426XX_REG_OFFSET_USER6	0x047D
-#define ICM426XX_REG_OFFSET_USER7	0x047E
-#define ICM426XX_REG_OFFSET_USER8	0x047F
-
-extern const struct accelgyro_drv icm426xx_drv;
-
-void icm426xx_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ACCELGYRO_ICM426XX_H */
diff --git a/driver/accelgyro_icm_common.c b/driver/accelgyro_icm_common.c
deleted file mode 100644
index 94db99407d..0000000000
--- a/driver/accelgyro_icm_common.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * ICM accelerometer and gyroscope module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "console.h"
-#include "i2c.h"
-#include "spi.h"
-#include "driver/accelgyro_icm_common.h"
-#include "driver/accelgyro_icm426xx.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-static int icm_spi_raw_read(const int addr, const uint8_t reg,
-			    uint8_t *data, const int len)
-{
-	uint8_t cmd = 0x80 | reg;
-
-	return spi_transaction(&spi_devices[addr], &cmd, 1, data, len);
-}
-
-static int icm_spi_raw_write(const int addr, const uint8_t reg,
-			     const uint8_t *data, const int len)
-{
-	uint8_t cmd[3];
-	int i;
-
-	if (len > 2)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	cmd[0] = reg;
-	for (i = 0; i < len; ++i)
-		cmd[i + 1] = data[i];
-
-	return spi_transaction(&spi_devices[addr], cmd, len + 1, NULL, 0);
-}
-#endif
-
-static int icm_bank_sel(const struct motion_sensor_t *s, const int reg)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	uint8_t bank = ICM426XX_REG_GET_BANK(reg);
-	int ret;
-
-	if (bank == st->bank)
-		return EC_SUCCESS;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	ret = icm_spi_raw_write(ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags),
-				ICM426XX_REG_BANK_SEL, &bank, 1);
-#else
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, ICM426XX_REG_BANK_SEL,
-			 bank);
-#endif
-
-	if (ret == EC_SUCCESS)
-		st->bank = bank;
-
-	return ret;
-}
-
-/**
- * Read 8 bits register
- */
-int icm_read8(const struct motion_sensor_t *s, const int reg, int *data_ptr)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	{
-		uint8_t val;
-
-		ret = icm_spi_raw_read(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
-			sizeof(val));
-		if (ret == EC_SUCCESS)
-			*data_ptr = val;
-	}
-#else
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, addr, data_ptr);
-#endif
-
-	return ret;
-}
-
-/**
- * Write 8 bits register
- */
-int icm_write8(const struct motion_sensor_t *s, const int reg, int data)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	{
-		uint8_t val = data;
-
-		ret = icm_spi_raw_write(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
-			sizeof(val));
-	}
-#else
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, addr, data);
-#endif
-
-	return ret;
-}
-
-/**
- * Read 16 bits register
- */
-int icm_read16(const struct motion_sensor_t *s, const int reg, int *data_ptr)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	{
-		uint8_t val[2];
-
-		ret = icm_spi_raw_read(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, val,
-			sizeof(val));
-		if (ret == EC_SUCCESS) {
-			if (I2C_IS_BIG_ENDIAN(s->i2c_spi_addr_flags))
-				*data_ptr = ((int)val[0] << 8) | val[1];
-			else
-				*data_ptr = ((int)val[1] << 8) | val[0];
-		}
-	}
-#else
-	ret = i2c_read16(s->port, s->i2c_spi_addr_flags,
-			addr, data_ptr);
-#endif
-
-	return ret;
-}
-
-/**
- * Write 16 bits register
- */
-int icm_write16(const struct motion_sensor_t *s, const int reg, int data)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	{
-		uint8_t val[2];
-
-		if (I2C_IS_BIG_ENDIAN(s->i2c_spi_addr_flags)) {
-			val[0] = (data >> 8) & 0xFF;
-			val[1] = data & 0xFF;
-		} else {
-			val[0] = data & 0xFF;
-			val[1] = (data >> 8) & 0xFF;
-		}
-		ret = icm_spi_raw_write(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, val,
-			sizeof(val));
-	}
-#else
-	ret = i2c_write16(s->port, s->i2c_spi_addr_flags, addr, data);
-#endif
-
-	return ret;
-}
-
-/**
- * Read n bytes
- */
-int icm_read_n(const struct motion_sensor_t *s, const int reg,
-	       uint8_t *data_ptr, const int len)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	ret = icm_spi_raw_read(ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr,
-			       data_ptr, len);
-#else
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, addr, data_ptr,
-			     len);
-#endif
-
-	return ret;
-}
-
-int icm_field_update8(const struct motion_sensor_t *s, const int reg,
-		      const uint8_t field_mask, const uint8_t set_value)
-{
-	const uint8_t addr = ICM426XX_REG_GET_ADDR(reg);
-	int ret;
-
-	ret = icm_bank_sel(s, reg);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = EC_ERROR_UNIMPLEMENTED;
-#ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-	{
-		uint8_t val;
-
-		ret = icm_spi_raw_read(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
-			sizeof(val));
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		val = (val & (~field_mask)) | set_value;
-
-		ret = icm_spi_raw_write(
-			ACCEL_GET_SPI_ADDR(s->i2c_spi_addr_flags), addr, &val,
-			sizeof(val));
-	}
-#else
-	ret = i2c_field_update8(s->port, s->i2c_spi_addr_flags, addr,
-				field_mask, set_value);
-#endif
-
-	return ret;
-}
-
-int icm_get_resolution(const struct motion_sensor_t *s)
-{
-	return ICM_RESOLUTION;
-}
-
-int icm_get_data_rate(const struct motion_sensor_t *s)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-
-	return data->odr;
-}
-
-int icm_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
-		  int16_t temp)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-
-	data->scale[X] = scale[X];
-	data->scale[Y] = scale[Y];
-	data->scale[Z] = scale[Z];
-	return EC_SUCCESS;
-}
-
-int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
-		  int16_t *temp)
-{
-	struct accelgyro_saved_data_t *data = ICM_GET_SAVED_DATA(s);
-
-	scale[X] = data->scale[X];
-	scale[Y] = data->scale[Y];
-	scale[Z] = data->scale[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-/* FIFO header: 1 byte */
-#define ICM_FIFO_HEADER_MSG		BIT(7)
-#define ICM_FIFO_HEADER_ACCEL		BIT(6)
-#define ICM_FIFO_HEADER_GYRO		BIT(5)
-#define ICM_FIFO_HEADER_TMST_FSYNC	GENMASK(3, 2)
-#define ICM_FIFO_HEADER_ODR_ACCEL	BIT(1)
-#define ICM_FIFO_HEADER_ODR_GYRO	BIT(0)
-
-/* FIFO data packet */
-struct icm_fifo_sensor_data {
-	int16_t x;
-	int16_t y;
-	int16_t z;
-} __packed;
-
-struct icm_fifo_1sensor_packet {
-	uint8_t header;
-	struct icm_fifo_sensor_data data;
-	int8_t temp;
-} __packed;
-#define ICM_FIFO_1SENSOR_PACKET_SIZE	8
-
-struct icm_fifo_2sensors_packet {
-	uint8_t header;
-	struct icm_fifo_sensor_data accel;
-	struct icm_fifo_sensor_data gyro;
-	int8_t temp;
-	uint16_t timestamp;
-} __packed;
-#define ICM_FIFO_2SENSORS_PACKET_SIZE	16
-
-ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro)
-{
-	const struct icm_fifo_1sensor_packet *pack1 = packet;
-	const struct icm_fifo_2sensors_packet *pack2 = packet;
-	uint8_t header = *((const uint8_t *)packet);
-
-	/* FIFO empty */
-	if (header & ICM_FIFO_HEADER_MSG) {
-		if (accel != NULL)
-			*accel = NULL;
-		if (gyro != NULL)
-			*gyro = NULL;
-		return 0;
-	}
-
-	/* accel + gyro */
-	if ((header & ICM_FIFO_HEADER_ACCEL) &&
-	    (header & ICM_FIFO_HEADER_GYRO)) {
-		if (accel != NULL)
-			*accel = (uint8_t *)&pack2->accel;
-		if (gyro != NULL)
-			*gyro = (uint8_t *)&pack2->gyro;
-		return ICM_FIFO_2SENSORS_PACKET_SIZE;
-	}
-
-	/* accel only */
-	if (header & ICM_FIFO_HEADER_ACCEL) {
-		if (accel != NULL)
-			*accel = (uint8_t *)&pack1->data;
-		if (gyro != NULL)
-			*gyro = NULL;
-		return ICM_FIFO_1SENSOR_PACKET_SIZE;
-	}
-
-	/* gyro only */
-	if (header & ICM_FIFO_HEADER_GYRO) {
-		if (accel != NULL)
-			*accel = NULL;
-		if (gyro != NULL)
-			*gyro = (uint8_t *)&pack1->data;
-		return ICM_FIFO_1SENSOR_PACKET_SIZE;
-	}
-
-	/* invalid packet if here */
-	return -EC_ERROR_INVAL;
-}
diff --git a/driver/accelgyro_icm_common.h b/driver/accelgyro_icm_common.h
deleted file mode 100644
index 8cf3b1e41d..0000000000
--- a/driver/accelgyro_icm_common.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ICM accelerometer and gyroscope common definitions for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_ICM_COMMON_H
-#define __CROS_EC_ACCELGYRO_ICM_COMMON_H
-
-#include "accelgyro.h"
-#include "hwtimer.h"
-#include "timer.h"
-
-#if !defined(CONFIG_ACCELGYRO_ICM_COMM_SPI) && \
-	!defined(CONFIG_ACCELGYRO_ICM_COMM_I2C)
-#error "ICM must use either SPI or I2C communication"
-#endif
-
-#ifdef CONFIG_ACCEL_FIFO
-/* reserve maximum 4 samples of 16 bytes */
-#define ICM_FIFO_BUFFER	64
-#else
-#define ICM_FIFO_BUFFER	0
-#endif
-
-struct icm_drv_data_t {
-	struct accelgyro_saved_data_t saved_data[2];
-	struct motion_sensor_t *accel;
-	struct motion_sensor_t *gyro;
-	uint32_t stabilize_ts[2];
-	uint8_t bank;
-	uint8_t fifo_en;
-	uint8_t fifo_buffer[ICM_FIFO_BUFFER] __aligned(sizeof(long));
-};
-
-#define ICM_GET_DATA(_s) \
-	((struct icm_drv_data_t *)(_s)->drv_data)
-#define ICM_GET_SAVED_DATA(_s) \
-	(&ICM_GET_DATA(_s)->saved_data[(_s)->type])
-
-/*
- * Virtual register address is 16 bits:
- * - 8 bits MSB coding bank number
- * - 8 bits LSB coding physical address
- */
-#define ICM426XX_REG_GET_BANK(_r)	(((_r) & 0xFF00) >> 8)
-#define ICM426XX_REG_GET_ADDR(_r)	((_r) & 0x00FF)
-
-/* Sensor resolution in number of bits */
-#define ICM_RESOLUTION		16
-
-/**
- * sign_extend - sign extend a standard int value using the given sign-bit
- * @value: value to sign extend
- * @index: 0 based bit index to sign bit
- */
-static inline int sign_extend(int value, int index)
-{
-	int shift = (sizeof(int) * 8) - index - 1;
-
-	return (int)(value << shift) >> shift;
-}
-
-/**
- * Read 8 bits register
- */
-int icm_read8(const struct motion_sensor_t *s, const int reg, int *data_ptr);
-
-/**
- * Write 8 bits register
- */
-int icm_write8(const struct motion_sensor_t *s, const int reg, int data);
-
-/**
- * Read 16 bits register
- */
-int icm_read16(const struct motion_sensor_t *s, const int reg, int *data_ptr);
-
-/**
- * Write 16 bits register
- */
-int icm_write16(const struct motion_sensor_t *s, const int reg, int data);
-
-/**
- * Read n bytes
- */
-int icm_read_n(const struct motion_sensor_t *s, const int reg,
-	       uint8_t *data_ptr, const int len);
-
-int icm_field_update8(const struct motion_sensor_t *s, const int reg,
-		      const uint8_t field_mask, const uint8_t set_value);
-
-int icm_get_resolution(const struct motion_sensor_t *s);
-
-int icm_get_range(const struct motion_sensor_t *s);
-
-int icm_get_data_rate(const struct motion_sensor_t *s);
-
-int icm_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
-		  int16_t temp);
-
-int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
-		  int16_t *temp);
-
-ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro);
-
-static inline void icm_set_stabilize_ts(const struct motion_sensor_t *s,
-					uint32_t delay)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	uint32_t stabilize_ts;
-
-	stabilize_ts = __hw_clock_source_read() + delay;
-	/* prevent 0 value used for disabling time checking */
-	st->stabilize_ts[s->type] = stabilize_ts | 1;
-}
-
-static inline void icm_reset_stabilize_ts(const struct motion_sensor_t *s)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-
-	st->stabilize_ts[s->type] = 0;
-}
-
-static inline
-int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s,
-				  uint32_t ts)
-{
-	struct icm_drv_data_t *st = ICM_GET_DATA(s);
-	uint32_t stabilize_ts = st->stabilize_ts[s->type];
-
-	if (stabilize_ts == 0)
-		return 0;
-
-	return time_until(ts, stabilize_ts);
-}
-
-#endif	/* __CROS_EC_ACCELGYRO_ICM_COMMON_H */
diff --git a/driver/accelgyro_lsm6ds0.c b/driver/accelgyro_lsm6ds0.c
deleted file mode 100644
index beee41b815..0000000000
--- a/driver/accelgyro_lsm6ds0.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * LSM6DS0 accelerometer and gyro module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/accelgyro_lsm6ds0.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-/*
- * Struct for pairing an engineering value with the register value for a
- * parameter.
- */
-struct accel_param_pair {
-	int val; /* Value in engineering units. */
-	int reg_val; /* Corresponding register value. */
-};
-
-/* List of range values in +/-G's and their associated register values. */
-static const struct accel_param_pair g_ranges[] = {
-	{2, LSM6DS0_GSEL_2G},
-	{4, LSM6DS0_GSEL_4G},
-	{8, LSM6DS0_GSEL_8G}
-};
-
-/*
- * List of angular rate range values in +/-dps's
- * and their associated register values.
- */
-const struct accel_param_pair dps_ranges[] = {
-	{245, LSM6DS0_DPS_SEL_245},
-	{500, LSM6DS0_DPS_SEL_500},
-	{1000, LSM6DS0_DPS_SEL_1000},
-	{2000, LSM6DS0_DPS_SEL_2000}
-};
-
-static inline const struct accel_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
-{
-	if (MOTIONSENSE_TYPE_ACCEL == type) {
-		if (psize)
-			*psize = ARRAY_SIZE(g_ranges);
-		return g_ranges;
-	} else {
-		if (psize)
-			*psize = ARRAY_SIZE(dps_ranges);
-		return dps_ranges;
-	}
-}
-
-/* List of ODR (gyro off) values in mHz and their associated register values.*/
-const struct accel_param_pair gyro_on_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{15000,    LSM6DS0_ODR_15HZ},
-	{59000,    LSM6DS0_ODR_59HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
-};
-
-/* List of ODR (gyro on) values in mHz and their associated register values. */
-const struct accel_param_pair gyro_off_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{10000,    LSM6DS0_ODR_10HZ},
-	{50000,    LSM6DS0_ODR_50HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
-};
-
-static inline const struct accel_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
-{
-	if (MOTIONSENSE_TYPE_ACCEL == type) {
-		if (psize)
-			*psize = ARRAY_SIZE(gyro_off_odr);
-		return gyro_off_odr;
-	} else {
-		if (psize)
-			*psize = ARRAY_SIZE(gyro_on_odr);
-		return gyro_on_odr;
-	}
-}
-
-static inline int get_ctrl_reg(enum motionsensor_type type)
-{
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_CTRL_REG6_XL : LSM6DS0_CTRL_REG1_G;
-}
-
-static inline int get_xyz_reg(enum motionsensor_type type)
-{
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_OUT_X_L_XL : LSM6DS0_OUT_X_L_G;
-}
-
-/**
- * @return reg value that matches the given engineering value passed in.
- * The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid reg value. If the request is
- * outside the range of values, it returns the closest valid reg value.
- */
-static int get_reg_val(const int eng_val, const int round_up,
-		const struct accel_param_pair *pairs, const int size)
-{
-	int i;
-	for (i = 0; i < size - 1; i++) {
-		if (eng_val <= pairs[i].val)
-			break;
-
-		if (eng_val < pairs[i+1].val) {
-			if (round_up)
-				i += 1;
-			break;
-		}
-	}
-	return pairs[i].reg_val;
-}
-
-/**
- * @return engineering value that matches the given reg val
- */
-static int get_engineering_val(const int reg_val,
-		const struct accel_param_pair *pairs, const int size)
-{
-	int i;
-	for (i = 0; i < size; i++) {
-		if (reg_val == pairs[i].reg_val)
-			break;
-	}
-	return pairs[i].val;
-}
-
-/**
- * Read register from accelerometer.
- */
-static inline int raw_read8(const int port, const uint16_t i2c_addr_flags,
-			    const int reg, int *data_ptr)
-{
-	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
-}
-
-/**
- * Write register from accelerometer.
- */
-static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
-			     const int reg, int data)
-{
-	return i2c_write8(port, i2c_addr_flags, reg, data);
-}
-
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
-{
-	int ret, ctrl_val, range_tbl_size;
-	uint8_t ctrl_reg, reg_val;
-	const struct accel_param_pair *ranges;
-
-	ctrl_reg = get_ctrl_reg(s->type);
-	ranges = get_range_table(s->type, &range_tbl_size);
-
-	reg_val = get_reg_val(range, rnd, ranges, range_tbl_size);
-
-	/*
-	 * Lock accel resource to prevent another task from attempting
-	 * to write accel parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			ctrl_reg, &ctrl_val);
-	if (ret != EC_SUCCESS)
-		goto accel_cleanup;
-
-	ctrl_val = (ctrl_val & ~LSM6DS0_RANGE_MASK) | reg_val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 ctrl_reg, ctrl_val);
-
-	/* Now that we have set the range, update the driver's value. */
-	if (ret == EC_SUCCESS)
-		s->current_range = get_engineering_val(reg_val, ranges,
-						       range_tbl_size);
-
-accel_cleanup:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	return LSM6DS0_RESOLUTION;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
-{
-	int ret, val, odr_tbl_size;
-	uint8_t ctrl_reg, reg_val;
-	const struct accel_param_pair *data_rates;
-	struct lsm6ds0_data *data = s->drv_data;
-
-	ctrl_reg = get_ctrl_reg(s->type);
-	data_rates = get_odr_table(s->type, &odr_tbl_size);
-	reg_val = get_reg_val(rate, rnd, data_rates, odr_tbl_size);
-
-	/*
-	 * Lock accel resource to prevent another task from attempting
-	 * to write accel parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags, ctrl_reg, &val);
-	if (ret != EC_SUCCESS)
-		goto accel_cleanup;
-
-	val = (val & ~LSM6DS0_ODR_MASK) | reg_val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, val);
-
-	/* Now that we have set the odr, update the driver's value. */
-	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
-
-	/* CTRL_REG3_G 12h
-	 * [7] low-power mode = 0;
-	 * [6] high pass filter disabled;
-	 * [5:4] 0 keep const 0
-	 * [3:0] HPCF_G
-	 *       Table 48 Gyroscope high-pass filter cutoff frequency
-	 */
-	if (MOTIONSENSE_TYPE_GYRO == s->type) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				LSM6DS0_CTRL_REG3_G, &val);
-		if (ret != EC_SUCCESS)
-			goto accel_cleanup;
-		val &= ~(0x3 << 4); /* clear bit [5:4] */
-		val = (rate > 119000) ?
-			(val | (1<<7))   /* set high-power mode */ :
-			(val & ~(1<<7)); /* set low-power mode */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 LSM6DS0_CTRL_REG3_G, val);
-	}
-
-accel_cleanup:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct lsm6ds0_data *data = s->drv_data;
-
-	return data->base.odr;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	/* temperature is ignored */
-	struct lsm6ds0_data *data = s->drv_data;
-	data->offset[X] = offset[X];
-	data->offset[Y] = offset[Y];
-	data->offset[Z] = offset[Z];
-	return EC_SUCCESS;
-}
-
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
-{
-	struct lsm6ds0_data *data = s->drv_data;
-	offset[X] = data->offset[X];
-	offset[Y] = data->offset[Y];
-	offset[Z] = data->offset[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int is_data_ready(const struct motion_sensor_t *s, int *ready)
-{
-	int ret, tmp;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_STATUS_REG, &tmp);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
-		return ret;
-	}
-
-	if (MOTIONSENSE_TYPE_ACCEL == s->type)
-		*ready = (LSM6DS0_STS_XLDA_UP == (tmp & LSM6DS0_STS_XLDA_MASK));
-	else
-		*ready = (LSM6DS0_STS_GDA_UP == (tmp & LSM6DS0_STS_GDA_MASK));
-
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[6];
-	uint8_t xyz_reg;
-	int ret, i, tmp = 0;
-	struct lsm6ds0_data *data = s->drv_data;
-
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!tmp) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-		return EC_SUCCESS;
-	}
-
-	xyz_reg = get_xyz_reg(s->type);
-
-	/* Read 6 bytes starting at xyz_reg */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     xyz_reg, raw, 6);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RD XYZ Error",
-			s->name, s->type);
-		return ret;
-	}
-
-	for (i = X; i <= Z; i++)
-		v[i] = (int16_t)((raw[i * 2 + 1] << 8) | raw[i * 2]);
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	/* apply offset in the device coordinates */
-	for (i = X; i <= Z; i++)
-		v[i] += (data->offset[i] << 5) / s->current_range;
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_WHO_AM_I_REG, &tmp);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	if (tmp != LSM6DS0_WHO_AM_I)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * This sensor can be powered through an EC reboot, so the state of
-	 * the sensor is unknown here. Initiate software reset to restore
-	 * sensor to default.
-	 * [6] BDU Enable Block Data Update.
-	 * [0] SW_RESET software reset
-	 *
-	 * lsm6ds0 supports both accel & gyro features
-	 * Board will see two virtual sensor devices: accel & gyro.
-	 * Requirement: Accel need be init before gyro.
-	 * SW_RESET is down for accel only!
-	 */
-	if (MOTIONSENSE_TYPE_ACCEL == s->type) {
-
-		mutex_lock(s->mutex);
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				LSM6DS0_CTRL_REG8, &tmp);
-		if (ret) {
-			mutex_unlock(s->mutex);
-			return EC_ERROR_UNKNOWN;
-		}
-		tmp |= (1 | LSM6DS0_BDU_ENABLE);
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 LSM6DS0_CTRL_REG8, tmp);
-		mutex_unlock(s->mutex);
-
-		if (ret)
-			return ret;
-
-		/* Power Down Gyro */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 LSM6DS0_CTRL_REG1_G, 0x0);
-		if (ret)
-			return ret;
-	}
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv lsm6ds0_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-};
diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h
deleted file mode 100644
index c6b0789c08..0000000000
--- a/driver/accelgyro_lsm6ds0.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LSM6DS0 accelerometer and gyro module for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_LSM6DS0_H
-#define __CROS_EC_ACCELGYRO_LSM6DS0_H
-
-#include "accelgyro.h"
-#include "task.h"
-
-/*
- * 7-bit address is 110101Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define LSM6DS0_ADDR0_FLAGS       0x6a
-#define LSM6DS0_ADDR1_FLAGS       0x6b
-
-/* who am I  */
-#define LSM6DS0_WHO_AM_I          0x68
-
-/* Chip specific registers. */
-#define LSM6DS0_ACT_THS           0x04
-#define LSM6DS0_ACT_DUR           0x05
-#define LSM6DS0_INT_GEN_CFG_XL    0x06
-#define LSM6DS0_INT_GEN_THS_X_XL  0x07
-#define LSM6DS0_INT_GEN_THS_Y_XL  0x08
-#define LSM6DS0_INT_GEN_THS_Z_XL  0x09
-#define LSM6DS0_INT_GEN_DUR_XL    0x0a
-#define LSM6DS0_REFERENCE_G       0x0b
-#define LSM6DS0_INT_CTRL          0x0c
-#define LSM6DS0_WHO_AM_I_REG      0x0f
-#define LSM6DS0_CTRL_REG1_G       0x10
-#define LSM6DS0_CTRL_REG2_G       0x11
-#define LSM6DS0_CTRL_REG3_G       0x12
-#define LSM6DS0_ORIENT_CFG_G      0x13
-#define LSM6DS0_INT_GEN_SRC_G     0x14
-#define LSM6DS0_OUT_TEMP_L        0x15
-#define LSM6DS0_OUT_TEMP_H        0x16
-#define LSM6DS0_OUT_X_L_G         0x18
-#define LSM6DS0_OUT_X_H_G         0x19
-#define LSM6DS0_OUT_Y_L_G         0x1a
-#define LSM6DS0_OUT_Y_H_G         0x1b
-#define LSM6DS0_OUT_Z_L_G         0x1c
-#define LSM6DS0_OUT_Z_H_G         0x1d
-#define LSM6DS0_CTRL_REG4         0x1e
-#define LSM6DS0_CTRL_REG5_XL      0x1f
-#define LSM6DS0_CTRL_REG6_XL      0x20
-#define LSM6DS0_CTRL_REG7_XL      0x21
-#define LSM6DS0_CTRL_REG8         0x22
-#define LSM6DS0_CTRL_REG9         0x23
-#define LSM6DS0_CTRL_REG10        0x24
-#define LSM6DS0_INT_GEN_SRC_XL    0x26
-#define LSM6DS0_STATUS_REG        0x27
-#define LSM6DS0_OUT_X_L_XL        0x28
-#define LSM6DS0_OUT_X_H_XL        0x29
-#define LSM6DS0_OUT_Y_L_XL        0x2a
-#define LSM6DS0_OUT_Y_H_XL        0x2b
-#define LSM6DS0_OUT_Z_L_XL        0x2c
-#define LSM6DS0_OUT_Z_H_XL        0x2d
-#define LSM6DS0_FIFO_CTRL         0x2e
-#define LSM6DS0_FIFO_SRC          0x2f
-#define LSM6DS0_INT_GEN_CFG_G     0x30
-#define LSM6DS0_INT_GEN_THS_XH_G  0x31
-#define LSM6DS0_INT_GEN_THS_XL_G  0x32
-#define LSM6DS0_INT_GEN_THS_YH_G  0x33
-#define LSM6DS0_INT_GEN_THS_YL_G  0x34
-#define LSM6DS0_INT_GEN_THS_ZH_G  0x35
-#define LSM6DS0_INT_GEN_THS_ZL_G  0x36
-#define LSM6DS0_INT_GEN_DUR_G     0x37
-
-#define LSM6DS0_DPS_SEL_245     (0 << 3)
-#define LSM6DS0_DPS_SEL_500     BIT(3)
-#define LSM6DS0_DPS_SEL_1000    (2 << 3)
-#define LSM6DS0_DPS_SEL_2000    (3 << 3)
-#define LSM6DS0_GSEL_2G         (0 << 3)
-#define LSM6DS0_GSEL_4G         (2 << 3)
-#define LSM6DS0_GSEL_8G         (3 << 3)
-
-#define LSM6DS0_RANGE_MASK      (3 << 3)
-
-#define LSM6DS0_ODR_PD          (0 << 5)
-#define LSM6DS0_ODR_10HZ        BIT(5)
-#define LSM6DS0_ODR_15HZ        BIT(5)
-#define LSM6DS0_ODR_50HZ        (2 << 5)
-#define LSM6DS0_ODR_59HZ        (2 << 5)
-#define LSM6DS0_ODR_119HZ       (3 << 5)
-#define LSM6DS0_ODR_238HZ       (4 << 5)
-#define LSM6DS0_ODR_476HZ       (5 << 5)
-#define LSM6DS0_ODR_952HZ       (6 << 5)
-
-#define LSM6DS0_ODR_MASK        (7 << 5)
-
-/*
- * Register      : STATUS_REG
- * Address       : 0X27
- */
-enum lsm6ds0_status {
-	LSM6DS0_STS_DOWN                = 0x00,
-	LSM6DS0_STS_XLDA_UP             = 0x01,
-	LSM6DS0_STS_GDA_UP              = 0x02,
-};
-#define         LSM6DS0_STS_XLDA_MASK       0x01
-#define         LSM6DS0_STS_GDA_MASK        0x02
-
-/*
- * Register      : CTRL_REG8
- * Address       : 0X22
- * Bit Group Name: BDU
- */
-enum lsm6ds0_bdu {
-	LSM6DS0_BDU_DISABLE              = 0x00,
-	LSM6DS0_BDU_ENABLE               = 0x40,
-};
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define LSM6DS0_RESOLUTION      16
-
-/* Min and Max sampling frequency in mHz */
-#define LSM6DS0_ACCEL_MIN_FREQ  14900
-#define LSM6DS0_ACCEL_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
-
-#define LSM6DS0_GYRO_MIN_FREQ   14900
-#define LSM6DS0_GYRO_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
-
-extern const struct accelgyro_drv lsm6ds0_drv;
-struct lsm6ds0_data {
-	struct accelgyro_saved_data_t base;
-	int16_t offset[3];
-};
-
-#endif /* __CROS_EC_ACCELGYRO_LSM6DS0_H */
diff --git a/driver/accelgyro_lsm6dso.c b/driver/accelgyro_lsm6dso.c
deleted file mode 100644
index fbce687f2c..0000000000
--- a/driver/accelgyro_lsm6dso.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * LSM6DSO Accel and Gyro module for Chrome EC
- * 3D digital accelerometer & 3D digital gyroscope
- *
- * For any details on driver implementation please
- * Refer to AN5192 Application Note on www.st.com
- */
-
-#include "driver/accelgyro_lsm6dso.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "task.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-STATIC_IF(CONFIG_ACCEL_INTERRUPTS) int config_interrupt(
-		const struct motion_sensor_t *s);
-
-/*
- * When ODR change, the sensor filters need settling time;
- * Add a counter to discard a well known number of data with
- * incorrect values.
- */
-static uint32_t samples_to_discard[LSM6DSO_FIFO_DEV_NUM];
-
-/**
- * @return output data base register for sensor
- */
-static inline int get_xyz_reg(enum motionsensor_type type)
-{
-	return LSM6DSO_ACCEL_OUT_X_L_ADDR -
-	       (LSM6DSO_ACCEL_OUT_X_L_ADDR - LSM6DSO_GYRO_OUT_X_L_ADDR) * type;
-}
-
-#ifdef CONFIG_ACCEL_INTERRUPTS
-/**
- * Configure interrupt int 1 to fire handler for:
- *
- * FIFO threshold on watermark (1 sample)
- *
- * @s: Motion sensor pointer
- */
-static int config_interrupt(const struct motion_sensor_t *s)
-{
-	int ret = EC_SUCCESS;
-	int int1_ctrl_val;
-
-	if (!IS_ENABLED(CONFIG_ACCEL_FIFO))
-		return ret;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL,
-			   &int1_ctrl_val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * Configure FIFO threshold to 1 sample: interrupt on watermark
-	 * will be generated every time a new data sample will be stored
-	 * in FIFO. The interrupr on watermark is cleared only when the
-	 * number or samples still present in FIFO exceeds the
-	 * configured threshold.
-	 */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSO_FIFO_CTRL1_ADDR, 1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	int1_ctrl_val |= LSM6DSO_INT_FIFO_TH | LSM6DSO_INT_FIFO_OVR |
-		LSM6DSO_INT_FIFO_FULL;
-
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL,
-			    int1_ctrl_val);
-
-	return ret;
-}
-
-/**
- * fifo_disable - set fifo mode to LSM6DSO_FIFO_MODE_BYPASS_VAL
- * @s: Motion sensor pointer: must be MOTIONSENSE_TYPE_ACCEL.
- */
-static int fifo_disable(const struct motion_sensor_t *s)
-{
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSO_FIFO_CTRL4_ADDR,
-			     LSM6DSO_FIFO_MODE_BYPASS_VAL);
-}
-
-/**
- * set_fifo_params - Configure internal FIFO parameters
- *
- * Configure FIFO decimator to have every time the right pattern
- * with acc/gyro
- */
-static int fifo_enable(const struct motion_sensor_t *s)
-{
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSO_FIFO_CTRL4_ADDR,
-			     LSM6DSO_FIFO_MODE_CONTINUOUS_VAL);
-}
-
-/**
- * push_fifo_data - Scan data pattern and push upside
- */
-static void push_fifo_data(struct motion_sensor_t *main_s, uint8_t *fifo,
-			   uint32_t saved_ts)
-{
-	struct ec_response_motion_sensor_data vect;
-	struct motion_sensor_t *sensor;
-	uint8_t tag;
-	int id;
-	int *axis;
-	uint8_t *ptr;
-	uint8_t ag_maps[] = {
-		MOTIONSENSE_TYPE_GYRO,
-		MOTIONSENSE_TYPE_ACCEL,
-	};
-
-	/*
-	 * FIFO pattern is as follow (i.e. Acc/Gyro @ same ODR)
-	 *  ________ ____________ _______ ____________
-	 * | TAG_XL | Acc[x,y,z] | TAG_G | Gyr[x,y,z] |
-	 * |________|____________|_______|____________|
-	 * |<-------- 1 -------->|<-------- 2 ------->| (FIFO Threshold)
-	 *
-	 * First byte is tag, next data.
-	 * Data pattern len is fixed for each sample.
-	 * FIFO threshold is related to sample data (7 byte).
-	 */
-	ptr = fifo + LSM6DSO_TAG_SIZE;
-	tag = (*fifo >> 3) - LSM6DSO_GYRO_TAG;
-	id = ag_maps[tag];
-
-	/* Discard samples every ODR changes. */
-	if (samples_to_discard[id] > 0) {
-		samples_to_discard[id]--;
-		return;
-	}
-
-	sensor = main_s + id;
-	axis = sensor->raw_xyz;
-
-	/* Apply precision, sensitivity and rotation. */
-	st_normalize(sensor, axis, ptr);
-	vect.data[X] = axis[X];
-	vect.data[Y] = axis[Y];
-	vect.data[Z] = axis[Z];
-
-	vect.flags = 0;
-	vect.sensor_num = sensor - motion_sensors;
-	motion_sense_fifo_stage_data(&vect, sensor, 3, saved_ts);
-}
-
-static inline int load_fifo(struct motion_sensor_t *main_s,
-			    const uint16_t fifo_len,
-			    uint32_t saved_ts)
-{
-	uint8_t fifo[LSM6DSO_FIFO_SAMPLE_SIZE];
-	int i, err;
-
-	for (i = 0; i < fifo_len; i++) {
-		err = st_raw_read_n_noinc(main_s->port,
-					  main_s->i2c_spi_addr_flags,
-					  LSM6DSO_FIFO_DATA_ADDR_TAG,
-					  fifo, LSM6DSO_FIFO_SAMPLE_SIZE);
-		if (err != EC_SUCCESS)
-			return err;
-
-		push_fifo_data(main_s, fifo, saved_ts);
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * accelgyro_config_fifo - update mode and ODR for FIFO decimator
- */
-static int accelgyro_config_fifo(const struct motion_sensor_t *s)
-{
-	int err;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
-	uint8_t reg_val;
-	uint8_t fifo_odr_mask;
-
-	/* Changing in ODR must stop FIFO. */
-	err = fifo_disable(s);
-	if (err != EC_SUCCESS)
-		return err;
-
-	/*
-	 * If ODR changes restore to default discard samples number
-	 * the counter related to this sensor.
-	 */
-	samples_to_discard[s->type] = LSM6DSO_DISCARD_SAMPLES;
-
-	fifo_odr_mask = LSM6DSO_FIFO_ODR_MASK(s);
-	reg_val = LSM6DSO_ODR_TO_REG(data->base.odr);
-	err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR,
-				      fifo_odr_mask, reg_val);
-	if (err != EC_SUCCESS)
-		return err;
-
-	return fifo_enable(s);
-}
-
-/**
- * lsm6dso_interrupt - interrupt from int1 pin of sensor
- */
-void lsm6dso_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ACCEL_LSM6DSO_INT_EVENT);
-}
-
-/**
- * irq_handler - bottom half of the interrupt task sheduled by consumer
- */
-static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	int ret = EC_SUCCESS, fifo_len = 0;
-	struct lsm6dso_fstatus fsts;
-	bool has_read_fifo = false;
-
-	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-	    (!(*event & CONFIG_ACCEL_LSM6DSO_INT_EVENT)))
-		return EC_ERROR_NOT_HANDLED;
-
-	if (!IS_ENABLED(CONFIG_ACCEL_FIFO))
-		return EC_SUCCESS;
-
-	do {
-		/* Read how many data patterns on FIFO to read. */
-		ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSO_FIFO_STS1_ADDR,
-					  (uint8_t *)&fsts, sizeof(fsts));
-		if (ret != EC_SUCCESS)
-			break;
-
-		if (fsts.len & (LSM6DSO_FIFO_DATA_OVR | LSM6DSO_FIFO_FULL))
-			CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len);
-
-		fifo_len = fsts.len & LSM6DSO_FIFO_DIFF_MASK;
-		if (fifo_len) {
-			ret = load_fifo(s, fifo_len, last_interrupt_timestamp);
-			has_read_fifo = true;
-		}
-	} while (fifo_len != 0 && ret == EC_SUCCESS);
-
-	if (ret == EC_SUCCESS && has_read_fifo)
-		motion_sense_fifo_commit_data();
-
-	return ret;
-}
-#endif /* CONFIG_ACCEL_INTERRUPTS */
-
-/**
- * set_range - set full scale range
- * @s: Motion sensor pointer
- * @range: Range
- * @rnd: Round up/down flag
- * Note: Range is sensitivity/gain for speed purpose
- */
-static int set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	int err;
-	uint8_t ctrl_reg, reg_val;
-	int newrange = range;
-
-	ctrl_reg = LSM6DSO_RANGE_REG(s->type);
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		/* Adjust and check rounded value for Acc. */
-		if (rnd && (newrange < LSM6DSO_ACCEL_NORMALIZE_FS(newrange)))
-			newrange *= 2;
-
-		if (newrange > LSM6DSO_ACCEL_FS_MAX_VAL)
-			newrange = LSM6DSO_ACCEL_FS_MAX_VAL;
-
-		reg_val = lsm6dso_accel_fs_reg(newrange);
-	} else {
-		/* Adjust and check rounded value for Gyro. */
-		reg_val = LSM6DSO_GYRO_FS_REG(range);
-		if (rnd && (range > LSM6DSO_GYRO_NORMALIZE_FS(reg_val)))
-			reg_val++;
-
-		if (reg_val > LSM6DSO_GYRO_FS_MAX_REG_VAL)
-			reg_val = LSM6DSO_GYRO_FS_MAX_REG_VAL;
-
-		newrange = LSM6DSO_GYRO_NORMALIZE_FS(reg_val);
-	}
-
-	mutex_lock(s->mutex);
-	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK,
-				      reg_val);
-	if (err == EC_SUCCESS)
-		s->current_range = newrange;
-
-	mutex_unlock(s->mutex);
-
-	return EC_SUCCESS;
-}
-
-/**
- * set_data_rate set sensor data rate
- * @s: Motion sensor pointer
- * @range: Rate (mHz)
- * @rnd: Round up/down flag
- */
-static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
-{
-	int ret, normalized_rate = 0;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
-	uint8_t ctrl_reg, reg_val = 0;
-
-	ctrl_reg = LSM6DSO_ODR_REG(s->type);
-	if (rate > 0) {
-		reg_val = LSM6DSO_ODR_TO_REG(rate);
-		normalized_rate = LSM6DSO_REG_TO_ODR(reg_val);
-
-		if (rnd && (normalized_rate < rate)) {
-			reg_val++;
-			normalized_rate = LSM6DSO_REG_TO_ODR(reg_val);
-		}
-
-		if (normalized_rate < LSM6DSO_ODR_MIN_VAL ||
-		    normalized_rate > LSM6DSO_ODR_MAX_VAL)
-			return EC_RES_INVALID_PARAM;
-	}
-
-	mutex_lock(s->mutex);
-	ret = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_ODR_MASK, reg_val);
-	if (ret == EC_SUCCESS) {
-		data->base.odr = normalized_rate;
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			accelgyro_config_fifo(s);
-	}
-
-	mutex_unlock(s->mutex);
-
-	return ret;
-}
-
-static int is_data_ready(const struct motion_sensor_t *s, int *ready)
-{
-	int ret, tmp;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_STATUS_REG, &tmp);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
-
-		return ret;
-	}
-
-	if (MOTIONSENSE_TYPE_ACCEL == s->type)
-		*ready = (LSM6DSO_STS_XLDA_UP == (tmp & LSM6DSO_STS_XLDA_MASK));
-	else
-		*ready = (LSM6DSO_STS_GDA_UP == (tmp & LSM6DSO_STS_GDA_MASK));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Is not very efficient to collect the data in read: better have an interrupt
- * and collect in FIFO, even if it has one item: we don't have to check if the
- * sensor is ready (minimize I2C access).
- */
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[OUT_XYZ_SIZE];
-	uint8_t xyz_reg;
-	int ret, tmp = 0;
-
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!tmp) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-
-		return EC_SUCCESS;
-	}
-
-	xyz_reg = get_xyz_reg(s->type);
-
-	/* Read data bytes starting at xyz_reg. */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  xyz_reg, raw, OUT_XYZ_SIZE);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Apply precision, sensitivity and rotation vector. */
-	st_normalize(s, v, raw);
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_WHO_AM_I_REG, &tmp);
-	if (ret != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	if (tmp != LSM6DSO_WHO_AM_I)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * This sensor can be powered through an EC reboot, so the state of the
-	 * sensor is unknown here so reset it
-	 * LSM6DSO supports both Acc & Gyro features
-	 * Board will see two virtual sensor devices: Acc & Gyro
-	 * Requirement: Acc need be init before Gyro
-	 */
-	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
-		mutex_lock(s->mutex);
-
-		/* Software reset. */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSO_CTRL3_ADDR, LSM6DSO_SW_RESET);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-
-		/*
-		 * Output data not updated until have been read.
-		 * Require interrupt to be active low.
-		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSO_CTRL3_ADDR,
-				    LSM6DSO_BDU | LSM6DSO_IF_INC
-					| LSM6DSO_H_L_ACTIVE);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			ret = fifo_disable(s);
-			if (ret != EC_SUCCESS)
-				goto err_unlock;
-		}
-
-		if (IS_ENABLED(CONFIG_ACCEL_INTERRUPTS))
-			ret = config_interrupt(s);
-		if (ret != EC_SUCCESS)
-			goto err_unlock;
-
-		mutex_unlock(s->mutex);
-	}
-
-	/* Set default resolution common to Acc and Gyro. */
-	data->resol = LSM6DSO_RESOLUTION;
-	return sensor_init_done(s);
-
-err_unlock:
-	mutex_unlock(s->mutex);
-	CPRINTS("%s: MS Init type:0x%X Error", s->name, s->type);
-
-	return ret;
-}
-
-const struct accelgyro_drv lsm6dso_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = st_get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = st_get_data_rate,
-	.set_offset = st_set_offset,
-	.get_offset = st_get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = irq_handler,
-#endif /* CONFIG_ACCEL_INTERRUPTS */
-};
diff --git a/driver/accelgyro_lsm6dso.h b/driver/accelgyro_lsm6dso.h
deleted file mode 100644
index 9a58fe7d36..0000000000
--- a/driver/accelgyro_lsm6dso.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LSM6DSO Accel and Gyro driver for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_LSM6DSO_H
-#define __CROS_EC_ACCELGYRO_LSM6DSO_H
-
-#include "stm_mems_common.h"
-
-/*
- * 7-bit address is 110101xb. Where 'x' is determined
- * by the voltage on the ADDR pin
- */
-#define LSM6DSO_ADDR0_FLAGS		0x6a
-#define LSM6DSO_ADDR1_FLAGS		0x6b
-
-/* Access to embedded sensor hub register bank */
-#define LSM6DSO_FUNC_CFG_ACC_ADDR	0x01
-#define LSM6DSO_FUNC_CFG_EN			0x80
-
-/* Who Am I */
-#define LSM6DSO_WHO_AM_I_REG		0x0f
-#define LSM6DSO_WHO_AM_I		0x6c
-
-/* Common defines for Acc and Gyro sensors */
-#define LSM6DSO_EN_BIT				0x01
-#define LSM6DSO_DIS_BIT				0x00
-
-#define LSM6DSO_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSO_ACCEL_OUT_X_L_ADDR	0x28
-
-#define LSM6DSO_CTRL1_ADDR		0x10
-#define LSM6DSO_CTRL2_ADDR		0x11
-#define LSM6DSO_CTRL3_ADDR		0x12
-#define LSM6DSO_SW_RESET			0x01
-#define LSM6DSO_IF_INC				0x04
-#define LSM6DSO_PP_OD				0x10
-#define LSM6DSO_H_L_ACTIVE			0x20
-#define LSM6DSO_BDU				0x40
-
-#define LSM6DSO_CTRL4_ADDR		0x13
-#define LSM6DSO_INT2_ON_INT1_MASK		0x20
-
-#define LSM6DSO_CTRL5_ADDR		0x14
-#define LSM6DSO_CTRL6_ADDR		0x15
-#define LSM6DSO_CTRL7_ADDR		0x16
-#define LSM6DSO_CTRL8_ADDR		0x17
-#define LSM6DSO_CTRL9_ADDR		0x18
-
-#define LSM6DSO_CTRL10_ADDR		0x19
-#define LSM6DSO_TIMESTAMP_EN    		0x20
-
-#define LSM6DSO_STATUS_REG		0x1e
-
-/* Output data rate registers and masks */
-#define LSM6DSO_ODR_REG(_sensor) \
-	(LSM6DSO_CTRL1_ADDR + (_sensor))
-#define LSM6DSO_ODR_MASK			0xf0
-
-/* FIFO decimator registers and bitmask */
-#define LSM6DSO_FIFO_CTRL1_ADDR		0x07
-#define LSM6DSO_FIFO_CTRL2_ADDR		0x08
-
-#define LSM6DSO_FIFO_CTRL3_ADDR		0x09
-#define LSM6DSO_FIFO_ODR_XL_MASK		0x0f
-#define LSM6DSO_FIFO_ODR_G_MASK			0xf0
-
-#define LSM6DSO_FIFO_CTRL4_ADDR		0x0a
-#define LSM6DSO_FIFO_MODE_MASK			0x07
-
-#define LSM6DSO_INT1_CTRL		0x0d
-#define LSM6DSO_INT2_CTRL		0x0e
-#define LSM6DSO_INT_FIFO_TH			0x08
-#define LSM6DSO_INT_FIFO_OVR			0x10
-#define LSM6DSO_INT_FIFO_FULL			0x20
-
-#define LSM6DSO_FIFO_STS1_ADDR		0x3a
-#define LSM6DSO_FIFO_STS2_ADDR		0x3b
-#define LSM6DSO_FIFO_DIFF_MASK			0x07ff
-#define LSM6DSO_FIFO_FULL			0x2000
-#define LSM6DSO_FIFO_DATA_OVR			0x4000
-#define LSM6DSO_FIFO_WATERMARK			0x8000
-
-/* Out FIFO data register */
-#define LSM6DSO_FIFO_DATA_ADDR_TAG	0x78
-
-/* Registers value for supported FIFO mode */
-#define LSM6DSO_FIFO_MODE_BYPASS_VAL	0x00
-#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL	0x06
-
-/* Define device available in FIFO pattern */
-enum lsm6dso_dev_fifo {
-	LSM6DSO_FIFO_DEV_INVALID = -1,
-	LSM6DSO_FIFO_DEV_GYRO = 0,
-	LSM6DSO_FIFO_DEV_ACCEL,
-	LSM6DSO_FIFO_DEV_NUM,
-};
-
-/* Define FIFO data pattern, tag and len */
-#define LSM6DSO_TAG_SIZE		1
-#define LSM6DSO_FIFO_SAMPLE_SIZE	(OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE)
-
-enum lsm6dso_tag_fifo {
-	LSM6DSO_GYRO_TAG = 0x01,
-	LSM6DSO_ACC_TAG = 0x02,
-};
-
-struct lsm6dso_fstatus {
-	uint16_t len;
-	uint16_t pattern;
-};
-
-/* Absolute maximum rate for Acc and Gyro sensors */
-#define LSM6DSO_ODR_MIN_VAL		13000
-#define LSM6DSO_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(416000, 13000)
-
-/* ODR reg value from selected data rate in mHz */
-#define LSM6DSO_ODR_TO_REG(_odr) (__fls(_odr / LSM6DSO_ODR_MIN_VAL) + 1)
-
-#define LSM6DSO_FIFO_ODR_MASK(_s) \
-	(_s->type == MOTIONSENSE_TYPE_ACCEL ? LSM6DSO_FIFO_ODR_XL_MASK : \
-	 LSM6DSO_FIFO_ODR_G_MASK)
-
-/* Normalized ODR values from selected data rate in mHz */
-#define LSM6DSO_REG_TO_ODR(_reg) (LSM6DSO_ODR_MIN_VAL << (_reg - 1))
-
-/* Full Scale ranges value and gain for Acc */
-#define LSM6DSO_FS_LIST_NUM		4
-
-#define LSM6DSO_ACCEL_FS_ADDR		0x10
-#define LSM6DSO_ACCEL_FS_MASK			0x0c
-
-#define LSM6DSO_ACCEL_FS_2G_VAL		0x00
-#define LSM6DSO_ACCEL_FS_4G_VAL		0x02
-#define LSM6DSO_ACCEL_FS_8G_VAL		0x03
-#define LSM6DSO_ACCEL_FS_16G_VAL	0x01
-
-#define LSM6DSO_ACCEL_FS_MAX_VAL	16
-
-/* Accel reg value from Full Scale range */
-static inline uint8_t lsm6dso_accel_fs_reg(int fs)
-{
-	uint8_t ret;
-
-	switch(fs) {
-	case 2:
-		ret = LSM6DSO_ACCEL_FS_2G_VAL;
-		break;
-	case 16:
-		ret = LSM6DSO_ACCEL_FS_16G_VAL;
-		break;
-	default:
-		ret = __fls(fs);
-		break;
-	}
-
-	return ret;
-}
-
-/* Accel normalized FS value from Full Scale */
-#define LSM6DSO_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs))
-
-/* Full Scale range value and gain for Gyro */
-#define LSM6DSO_GYRO_FS_ADDR		0x11
-#define LSM6DSO_GYRO_FS_MASK			0x0c
-
-/* Minimal Gyro range in mDPS */
-#define LSM6DSO_GYRO_FS_MIN_VAL_MDPS ((8750 << 15) / 1000)
-#define LSM6DSO_GYRO_FS_MAX_REG_VAL 3
-
-/* Gyro reg value for Full Scale selection in DPS */
-#define LSM6DSO_GYRO_FS_REG(_fs) \
-	__fls(MAX(1, (_fs * 1000) / LSM6DSO_GYRO_FS_MIN_VAL_MDPS))
-
-/* Gyro normalized FS value (in DPS) from Full Scale register */
-#define LSM6DSO_GYRO_NORMALIZE_FS(_reg) \
-	((LSM6DSO_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000)
-
-/* FS register address/mask for Acc/Gyro sensors */
-#define LSM6DSO_RANGE_REG(_sensor)  	(LSM6DSO_ACCEL_FS_ADDR + (_sensor))
-#define LSM6DSO_RANGE_MASK  			0x0c
-
-/* Status register bit for Acc/Gyro data ready */
-enum lsm6dso_status {
-	LSM6DSO_STS_DOWN = 0x00,
-	LSM6DSO_STS_XLDA_UP = 0x01,
-	LSM6DSO_STS_GDA_UP = 0x02
-};
-
-/* Status register bitmask for Acc/Gyro data ready */
-#define LSM6DSO_STS_XLDA_MASK			0x01
-#define LSM6DSO_STS_GDA_MASK			0x02
-
-/* Sensor resolution in number of bits: fixed 16 bit */
-#define LSM6DSO_RESOLUTION      	16
-
-/* Aggregate private data for all supported sensor (Acc, Gyro) */
-struct lsm6dso_data {
-	struct stprivate_data st_data[LSM6DSO_FIFO_DEV_NUM];
-};
-
-/*
- * Note: The specific number of samples to discard depends on the filters
- * configured for the chip, as well as the ODR being set. For most of our
- * allowed ODRs, 3 should suffice.
- * See: ST's LSM6DSO application notes (AN5192) Tables 12 and 18 for details
- */
-#define LSM6DSO_DISCARD_SAMPLES 3
-
-#define LSM6DSO_GET_DATA(_s) ((struct stprivate_data *)((_s)->drv_data))
-
-/* Macro to initialize motion_sensors structure */
-#define LSM6DSO_ST_DATA(g, type) (&((g).st_data[type]))
-
-extern const struct accelgyro_drv lsm6dso_drv;
-
-void lsm6dso_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_ACCELGYRO_LSM6DSO_H */
diff --git a/driver/als_al3010.c b/driver/als_al3010.c
deleted file mode 100644
index b129dc2f57..0000000000
--- a/driver/als_al3010.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Dyna-Image AL3010 light sensor driver
- */
-
-#include "driver/als_al3010.h"
-#include "i2c.h"
-
-/**
- * Initialise AL3010 light sensor.
- */
-int al3010_init(void)
-{
-	int ret;
-
-	ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_CONFIG, AL3010_GAIN << 4);
-	if (ret)
-		return ret;
-
-	return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			  AL3010_REG_SYSTEM, AL3010_ENABLE);
-}
-
-/**
- * Read AL3010 light sensor data.
- */
-int al3010_read_lux(int *lux, int af)
-{
-	int ret;
-	int val;
-	long long val64;
-
-	ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_DATA_LOW, &val);
-
-	if (ret)
-		return ret;
-
-	val64 = val;
-	val64 = (val64 * AL3010_GAIN_SCALE) / 10000;
-	val = val64 * af / 100;
-
-	*lux = val;
-
-	return EC_SUCCESS;
-}
diff --git a/driver/als_al3010.h b/driver/als_al3010.h
deleted file mode 100644
index 288e255990..0000000000
--- a/driver/als_al3010.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Dyna-Image AL3010 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_AL3010_H
-#define __CROS_EC_ALS_AL3010_H
-
-/* I2C interface */
-#define AL3010_I2C_ADDR1_FLAGS		0x1C
-#define AL3010_I2C_ADDR2_FLAGS		0x1D
-#define AL3010_I2C_ADDR3_FLAGS		0x1E
-
-/* AL3010 registers */
-#define AL3010_REG_SYSTEM		0x00
-#define AL3010_REG_INT_STATUS		0x01
-#define AL3010_REG_CONFIG		0x10
-#define AL3010_REG_DATA_LOW		0x0C
-
-#define AL3010_ENABLE	0x01
-#define AL3010_GAIN_SELECT 3
-
-#define	AL3010_GAIN_1 0 /* 77806 lx */
-#define	AL3010_GAIN_2 1 /* 19452 lx  */
-#define	AL3010_GAIN_3 2 /* 4863  lx  */
-#define	AL3010_GAIN_4 3 /* 1216  lx  */
-#define AL3010_GAIN	CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT)
-
-#define AL3010_GAIN_SCALE_1 11872	/* 1.1872 lux/count */
-#define AL3010_GAIN_SCALE_2 2968	/* 0.2968 lux/count */
-#define AL3010_GAIN_SCALE_3 742		/* 0.0742 lux/count */
-#define AL3010_GAIN_SCALE_4 186		/* 0.0186 lux/count */
-#define AL3010_GAIN_SCALE CONCAT2(AL3010_GAIN_SCALE_, AL3010_GAIN_SELECT)
-
-int al3010_init(void);
-int al3010_read_lux(int *lux, int af);
-
-#endif	/* __CROS_EC_ALS_AL3010_H */
diff --git a/driver/als_bh1730.c b/driver/als_bh1730.c
deleted file mode 100644
index 56afb86e0b..0000000000
--- a/driver/als_bh1730.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Rohm BH1730 Ambient light sensor driver
- */
-
-#include "accelgyro.h"
-#include "config.h"
-#include "console.h"
-#include "driver/als_bh1730.h"
-#include "i2c.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
-
-/**
- * Convert BH1730 data0, data1 to lux
- */
-static int bh1730_convert_to_lux(uint32_t data0_1)
-{
-	int lux;
-	uint16_t data0 = 0x0000ffff & data0_1;
-	uint16_t data1 = data0_1 >> 16;
-	uint32_t d0_1k = data0 * 1000;
-	uint32_t d1_1k = data1 * 1000;
-	uint32_t d_temp;
-	uint32_t d_lux;
-
-	if (data0 == 0)
-		return 0;
-	else
-		d_temp = d1_1k / data0;
-
-	if(d_temp < BH1730_LUXTH1_1K) {
-		d0_1k = BH1730_LUXTH1_D0_1K * data0;
-		d1_1k = BH1730_LUXTH1_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH2_1K) {
-		d0_1k = BH1730_LUXTH2_D0_1K * data0;
-		d1_1k = BH1730_LUXTH2_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH3_1K) {
-		d0_1k = BH1730_LUXTH3_D0_1K * data0;
-		d1_1k = BH1730_LUXTH3_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH4_1K) {
-		d0_1k = BH1730_LUXTH4_D0_1K * data0;
-		d1_1k = BH1730_LUXTH4_D1_1K * data1;
-	} else
-		return 0;
-
-	d_lux = (d0_1k - d1_1k) / BH1730_GAIN_DIV;
-	d_lux *= 100;
-	lux = d_lux / ITIME_MS_X_1K;
-
-	return lux;
-}
-
-/**
- * Read BH1730 light sensor data.
- */
-static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v)
-{
-	struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s);
-	int ret;
-	int data0_1;
-
-	/* read data0 and data1 from sensor */
-	ret = i2c_read32(s->port, s->i2c_spi_addr_flags,
-			 BH1730_DATA0LOW, &data0_1);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("bh1730_read_lux - fail %d\n", ret);
-		return ret;
-	}
-
-	/* convert sensor data0 and data1 to lux */
-	v[0] = bh1730_convert_to_lux(data0_1);
-	v[1] = 0;
-	v[2] = 0;
-
-	/*
-	 * Return an error when nothing change to prevent filling the
-	 * fifo with useless data.
-	 */
-	if (v[0] == drv_data->last_value)
-		return EC_ERROR_UNCHANGED;
-	else
-		return EC_SUCCESS;
-}
-
-static int bh1730_set_range(struct motion_sensor_t *s, int range,
-			     int rnd)
-{
-	/* Range is fixed by hardware */
-	if (range != s->default_range)
-		return EC_ERROR_INVAL;
-
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int bh1730_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
-{
-	struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s);
-
-	/* now only one rate supported */
-	drv_data->rate = BH1730_10000_MHZ;
-
-	return EC_SUCCESS;
-}
-
-static int bh1730_get_data_rate(const struct motion_sensor_t *s)
-{
-	struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s);
-
-	return drv_data->rate;
-}
-
-static int bh1730_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	return EC_SUCCESS;
-}
-
-static int bh1730_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
-{
-	*offset = 0;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Initialise BH1730 Ambient light sensor.
- */
-static int bh1730_init(struct motion_sensor_t *s)
-{
-	int ret;
-
-	/* power and measurement bit high */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			BH1730_CONTROL,
-			BH1730_CONTROL_POWER_ENABLE
-			      | BH1730_CONTROL_ADC_EN_ENABLE);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTF("bh1730_init_sensor - enable fail %d\n", ret);
-		return ret;
-	}
-
-	/* set timing */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_TIMING, BH1730_CONF_ITIME);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("bh1730_init_sensor - time fail %d\n", ret);
-		return ret;
-	}
-	/* set ADC gain */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_GAIN, BH1730_CONF_GAIN);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTF("bh1730_init_sensor - gain fail %d\n", ret);
-		return ret;
-	}
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv bh1730_drv = {
-	.init = bh1730_init,
-	.read = bh1730_read_lux,
-	.set_range = bh1730_set_range,
-	.set_offset = bh1730_set_offset,
-	.get_offset = bh1730_get_offset,
-	.set_data_rate = bh1730_set_data_rate,
-	.get_data_rate = bh1730_get_data_rate,
-};
-
diff --git a/driver/als_bh1730.h b/driver/als_bh1730.h
deleted file mode 100644
index f49afac76f..0000000000
--- a/driver/als_bh1730.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Rohm BH1730 Ambient light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_BH1730_H
-#define __CROS_EC_ALS_BH1730_H
-
-/* I2C interface */
-#define BH1730_I2C_ADDR_FLAGS	0x29
-
-/* BH1730 registers */
-#define BH1730_CONTROL		0x80
-#define BH1730_TIMING		0x81
-#define BH1730_INTERRUPT	0x82
-#define BH1730_THLLOW		0x83
-#define BH1730_THLHIGH		0x84
-#define BH1730_THHLOW		0x85
-#define BH1730_THHHIGH		0x86
-#define BH1730_GAIN		0x87
-#define BH1730_OPART_ID		0x92
-#define BH1730_DATA0LOW		0x94
-#define BH1730_DATA0HIGH	0x95
-#define BH1730_DATA1LOW		0x96
-#define BH1730_DATA1HIGH	0x97
-/* Software reset */
-#define BH1730_RESET		0xE4
-
-/* Registers bits */
-#define BH1730_CONTROL_ADC_INTR_INACTIVE	(0x00 << 5)
-#define BH1730_CONTROL_ADC_INTR_ACTIVE		(0x01 << 5)
-#define BH1730_CONTROL_ADC_VALID		(0x01 << 4)
-#define BH1730_CONTROL_ONE_TIME_CONTINOUS	(0x00 << 3)
-#define BH1730_CONTROL_ONE_TIME_ONETIME		(0x01 << 3)
-#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1	(0x00 << 2)
-#define BH1730_CONTROL_DATA_SEL_TYPE0		(0x01 << 2)
-#define BH1730_CONTROL_ADC_EN_DISABLE		(0x00 << 1)
-#define BH1730_CONTROL_ADC_EN_ENABLE		(0x01 << 1)
-#define BH1730_CONTROL_POWER_DISABLE		(0x00 << 0)
-#define BH1730_CONTROL_POWER_ENABLE		(0x01 << 0)
-
-#define BH1730_GAIN_GAIN_X1_GAIN		(0x00 << 0)
-#define BH1730_GAIN_GAIN_X2_GAIN		(0x01 << 0)
-#define BH1730_GAIN_GAIN_X64_GAIN		(0x02 << 0)
-#define BH1730_GAIN_GAIN_X128_GAIN		(0x03 << 0)
-
-/* Sensor configuration */
-/* Select Gain */
-#define BH1730_CONF_GAIN BH1730_GAIN_GAIN_X64_GAIN
-#define BH1730_GAIN_DIV 64
-
-/* Select Itime, 0xDA is 102.6ms = 38*2.7ms */
-#define BH1730_CONF_ITIME 0xDA
-#define ITIME_MS_X_10 ((256 - BH1730_CONF_ITIME) * 27)
-#define ITIME_MS_X_1K (ITIME_MS_X_10*100)
-
-/* default Itime is about 10Hz */
-#define BH1730_10000_MHZ (10*1000)
-#define BH1730_MAX_FREQ BH1730_10000_MHZ
-/*
- * 10Hz is too fast for the AP: allow the AP query data less often, the EC will
- * downsample.
- */
-#define BH1730_MIN_FREQ (BH1730_MAX_FREQ / 100)
-
-/*
- * Use default lux calculation formula parameters if board specific
- * parameters are not defined.
- */
-#ifndef CONFIG_ALS_BH1730_LUXTH_PARAMS
-#define BH1730_LUXTH1_1K                260
-#define BH1730_LUXTH1_D0_1K             1290
-#define BH1730_LUXTH1_D1_1K             2733
-#define BH1730_LUXTH2_1K                550
-#define BH1730_LUXTH2_D0_1K             797
-#define BH1730_LUXTH2_D1_1K             859
-#define BH1730_LUXTH3_1K                1090
-#define BH1730_LUXTH3_D0_1K             510
-#define BH1730_LUXTH3_D1_1K             345
-#define BH1730_LUXTH4_1K                2130
-#define BH1730_LUXTH4_D0_1K             276
-#define BH1730_LUXTH4_D1_1K             130
-#endif
-
-#define BH1730_GET_DATA(_s)    ((struct bh1730_drv_data_t *)(_s)->drv_data)
-
-struct bh1730_drv_data_t {
-	int rate;
-	int last_value;
-};
-
-extern const struct accelgyro_drv bh1730_drv;
-
-#endif	/* __CROS_EC_ALS_BH1730_H */
-
diff --git a/driver/als_isl29035.c b/driver/als_isl29035.c
deleted file mode 100644
index db77a19f09..0000000000
--- a/driver/als_isl29035.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Intersil ILS29035 light sensor driver
- */
-
-#include "driver/als_isl29035.h"
-#include "i2c.h"
-
-/* I2C interface */
-#define ILS29035_I2C_ADDR_FLAGS	0x44
-#define ILS29035_REG_COMMAND_I  0
-#define ILS29035_REG_COMMAND_II 1
-#define ILS29035_REG_DATA_LSB   2
-#define ILS29035_REG_DATA_MSB   3
-#define ILS29035_REG_INT_LT_LSB 4
-#define ILS29035_REG_INT_LT_MSB 5
-#define ILS29035_REG_INT_HT_LSB 6
-#define ILS29035_REG_INT_HT_MSB 7
-#define ILS29035_REG_ID         15
-
-int isl29035_init(void)
-{
-	/*
-	 * Tell it to read continually. This uses 70uA, as opposed to nearly
-	 * zero, but it makes the hook/update code cleaner (we don't want to
-	 * wait 90ms to read on demand while processing hook callbacks).
-	 */
-	return i2c_write8(I2C_PORT_ALS, ILS29035_I2C_ADDR_FLAGS,
-			  ILS29035_REG_COMMAND_I, 0xa0);
-}
-
-int isl29035_read_lux(int *lux, int af)
-{
-	int rv, lsb, msb, data;
-
-	/*
-	 * NOTE: It is necessary to read the LSB first, then the MSB. If you do
-	 * it in the opposite order, the results are not correct. This is
-	 * apparently an undocumented "feature". It's especially noticeable in
-	 * one-shot mode.
-	 */
-
-	/* Read lsb */
-	rv = i2c_read8(I2C_PORT_ALS, ILS29035_I2C_ADDR_FLAGS,
-		       ILS29035_REG_DATA_LSB, &lsb);
-	if (rv)
-		return rv;
-
-	/* Read msb */
-	rv = i2c_read8(I2C_PORT_ALS, ILS29035_I2C_ADDR_FLAGS,
-		       ILS29035_REG_DATA_MSB, &msb);
-	if (rv)
-		return rv;
-
-	data = (msb << 8) | lsb;
-
-	/*
-	 * The default power-on values will give 16 bits of precision:
-	 * 0x0000-0xffff indicates 0-1000 lux. We multiply the sensor value by
-	 * a scaling factor to account for attentuation by glass, tinting, etc.
-	 *
-	 * Caution: Don't go nuts with the attentuation factor. If it's
-	 * greater than 32, the signed int math will roll over and you'll get
-	 * very wrong results. Of course, if you have that much attenuation and
-	 * are still getting useful readings, you probably have your sensor
-	 * pointed directly into the sun.
-	 */
-	*lux = data * af * 1000 / 0xffff;
-
-	return EC_SUCCESS;
-}
diff --git a/driver/als_isl29035.h b/driver/als_isl29035.h
deleted file mode 100644
index 153ba148f9..0000000000
--- a/driver/als_isl29035.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Intersil ILS29035 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_ISL29035_H
-#define __CROS_EC_ALS_ISL29035_H
-
-int isl29035_init(void);
-int isl29035_read_lux(int *lux, int af);
-
-#endif	/* __CROS_EC_ALS_ISL29035_H */
diff --git a/driver/als_opt3001.c b/driver/als_opt3001.c
deleted file mode 100644
index 53f2b7df89..0000000000
--- a/driver/als_opt3001.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI OPT3001 light sensor driver
- */
-
-#include "common.h"
-#include "driver/als_opt3001.h"
-#include "i2c.h"
-
-#ifdef HAS_TASK_ALS
-/**
- *  Read register from OPT3001 light sensor.
- */
-static int opt3001_i2c_read(const int reg, int *data_ptr)
-{
-	int ret;
-
-	ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			 reg, data_ptr);
-	if (!ret)
-		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
-
-	return ret;
-}
-
-/**
- *  Write register to OPT3001 light sensor.
- */
-static int opt3001_i2c_write(const int reg, int data)
-{
-	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
-	return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			   reg, data);
-}
-
-/**
- * Initialise OPT3001 light sensor.
- */
-int opt3001_init(void)
-{
-	int data;
-	int ret;
-
-	ret = opt3001_i2c_read(OPT3001_REG_MAN_ID, &data);
-	if (ret)
-		return ret;
-	if (data != OPT3001_MANUFACTURER_ID)
-		return EC_ERROR_UNKNOWN;
-
-	ret = opt3001_i2c_read(OPT3001_REG_DEV_ID, &data);
-	if (ret)
-		return ret;
-	if (data != OPT3001_DEVICE_ID)
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * [15:12]: 0101b Automatic full scale (1310.40lux, 0.32lux/lsb)
-	 * [11]   : 1b    Conversion time 800ms
-	 * [10:9] : 10b   Continuous Mode of conversion operation
-	 * [4]    : 1b    Latched window-style comparison operation
-	 */
-	return opt3001_i2c_write(OPT3001_REG_CONFIGURE, 0x5C10);
-}
-
-/**
- * Read OPT3001 light sensor data.
- */
-int opt3001_read_lux(int *lux, int af)
-{
-	int ret;
-	int data;
-
-	ret = opt3001_i2c_read(OPT3001_REG_RESULT, &data);
-	if (ret)
-		return ret;
-
-	/*
-	 * The default power-on values will give 12 bits of precision:
-	 * 0x0000-0x0fff indicates 0 to 1310.40 lux. We multiply the sensor
-	 * value by a scaling factor to account for attenuation by glass,
-	 * tinting, etc.
-	 */
-
-	/*
-	 * lux = 2EXP[3:0] × R[11:0] / 100
-	 */
-	*lux = (1 << ((data & 0xF000) >> 12)) * (data & 0x0FFF) * af / 100;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ALS
-struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = OPT3001_REG_DEV_ID,
-		.read_val = OPT3001_DEVICE_ID,
-		.write_reg = OPT3001_REG_INT_LIMIT_LSB,
-	},
-	.i2c_read_dev = &opt3001_i2c_read,
-	.i2c_write_dev = &opt3001_i2c_write,
-};
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#else  /* HAS_TASK_ALS */
-#include "accelgyro.h"
-#include "math_util.h"
-
-/**
- *  Read register from OPT3001 light sensor.
- */
-static int opt3001_i2c_read(const int port,
-			    const uint16_t i2c_addr_flags,
-			    const int reg, int *data_ptr)
-{
-	int ret;
-
-	ret = i2c_read16(port, i2c_addr_flags,
-			 reg, data_ptr);
-	if (!ret)
-		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
-
-	return ret;
-}
-
-/**
- *  Write register to OPT3001 light sensor.
- */
-static int opt3001_i2c_write(const int port,
-			     const uint16_t i2c_addr_flags,
-			     const int reg, int data)
-{
-	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
-	return i2c_write16(port, i2c_addr_flags, reg, data);
-}
-
-/**
- * Read OPT3001 light sensor data.
- */
-int opt3001_read_lux(const struct motion_sensor_t *s, intv3_t v)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-	int ret;
-	int data;
-
-	ret = opt3001_i2c_read(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_RESULT, &data);
-	if (ret)
-		return ret;
-
-	/*
-	 * lux = 2EXP[3:0] × R[11:0] / 100
-	 */
-	data = (1 << (data >> 12)) * (data & 0x0FFF);
-	data += drv_data->offset * 100;
-	data = data * drv_data->scale + data * drv_data->uscale / 10000;
-	data /= 100;
-
-	if (data < 0)
-		data = 1;
-
-	v[0] = data;
-	v[1] = 0;
-	v[2] = 0;
-
-	/*
-	 * Return an error when nothing change to prevent filling the
-	 * fifo with useless data.
-	 */
-	if (v[0] == drv_data->last_value)
-		return EC_ERROR_UNCHANGED;
-	else {
-		drv_data->last_value = v[0];
-		return EC_SUCCESS;
-	}
-}
-
-static int opt3001_set_range(struct motion_sensor_t *s, int range,
-			     int rnd)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-
-	drv_data->scale = range >> 16;
-	drv_data->uscale = range & 0xffff;
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int opt3001_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-	int rv;
-	int reg;
-	enum opt3001_mode mode;
-
-	if (rate == 0) {
-		/*
-		 * Suspend driver:
-		 */
-		mode = OPT3001_MODE_SUSPEND;
-	} else {
-		mode = OPT3001_MODE_CONTINUOUS;
-		/*
-		 * We set the sensor for continuous mode,
-		 * integrating over 800ms.
-		 * Do not allow range higher than 1Hz.
-		 */
-		if (rate > OPT3001_LIGHT_MAX_FREQ)
-			rate = OPT3001_LIGHT_MAX_FREQ;
-	}
-	rv = opt3001_i2c_read(s->port, s->i2c_spi_addr_flags,
-			      OPT3001_REG_CONFIGURE, &reg);
-	if (rv)
-		return rv;
-
-	rv = opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_CONFIGURE,
-			       (reg & OPT3001_MODE_MASK) |
-				   (mode << OPT3001_MODE_OFFSET));
-	if (rv)
-		return rv;
-
-	drv_data->rate = rate;
-	return EC_SUCCESS;
-}
-
-static int opt3001_get_data_rate(const struct motion_sensor_t *s)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-
-	return drv_data->rate;
-}
-
-static int opt3001_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-
-	drv_data->offset = offset[X];
-	return EC_SUCCESS;
-}
-
-static int opt3001_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
-{
-	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
-
-	offset[X] = drv_data->offset;
-	offset[Y] = 0;
-	offset[Z] = 0;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-/**
- * Initialise OPT3001 light sensor.
- */
-static int opt3001_init(struct motion_sensor_t *s)
-{
-	int data;
-	int ret;
-
-	ret = opt3001_i2c_read(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_MAN_ID, &data);
-	if (ret)
-		return ret;
-	if (data != OPT3001_MANUFACTURER_ID)
-		return EC_ERROR_ACCESS_DENIED;
-
-	ret = opt3001_i2c_read(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_DEV_ID, &data);
-	if (ret)
-		return ret;
-	if (data != OPT3001_DEVICE_ID)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/*
-	 * [15-12]: 1100b Automatic full-scale setting mode
-	 * [11]   : 1b    Conversion time 800ms
-	 * [4]    : 1b    Latched window-style comparison operation
-	 */
-	opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			  OPT3001_REG_CONFIGURE, 0xC810);
-
-	opt3001_set_range(s, s->default_range, 0);
-
-	return EC_SUCCESS;
-}
-
-const struct accelgyro_drv opt3001_drv = {
-	.init = opt3001_init,
-	.read = opt3001_read_lux,
-	.set_range = opt3001_set_range,
-	.set_offset = opt3001_set_offset,
-	.get_offset = opt3001_get_offset,
-	.set_data_rate = opt3001_set_data_rate,
-	.get_data_rate = opt3001_get_data_rate,
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ALS
-struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = OPT3001_REG_DEV_ID,
-		.read_val = OPT3001_DEVICE_ID,
-		.write_reg = OPT3001_REG_INT_LIMIT_LSB,
-	},
-	.i2c_read = &opt3001_i2c_read,
-	.i2c_write = &opt3001_i2c_write,
-};
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#endif  /* HAS_TASK_ALS */
diff --git a/driver/als_opt3001.h b/driver/als_opt3001.h
deleted file mode 100644
index 96b47232d1..0000000000
--- a/driver/als_opt3001.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI OPT3001 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_OPT3001_H
-#define __CROS_EC_ALS_OPT3001_H
-
-/* I2C interface */
-#define OPT3001_I2C_ADDR1_FLAGS		0x44
-#define OPT3001_I2C_ADDR2_FLAGS		0x45
-#define OPT3001_I2C_ADDR3_FLAGS		0x46
-#define OPT3001_I2C_ADDR4_FLAGS		0x47
-
-/* OPT3001 registers */
-#define OPT3001_REG_RESULT		0x00
-#define OPT3001_REG_CONFIGURE		0x01
-#define OPT3001_RANGE_OFFSET			12
-#define OPT3001_RANGE_MASK			0x0fff
-#define OPT3001_MODE_OFFSET			9
-#define OPT3001_MODE_MASK			0xf9ff
-enum opt3001_mode {
-	OPT3001_MODE_SUSPEND,
-	OPT3001_MODE_FORCED,
-	OPT3001_MODE_CONTINUOUS,
-};
-
-#define OPT3001_REG_INT_LIMIT_LSB	0x02
-#define OPT3001_REG_INT_LIMIT_MSB	0x03
-#define OPT3001_REG_MAN_ID		0x7e
-#define OPT3001_REG_DEV_ID		0x7f
-
-/* OPT3001 register values */
-#define OPT3001_MANUFACTURER_ID		0x5449
-#define OPT3001_DEVICE_ID		0x3001
-
-/*
- * Min and Max sampling frequency in mHz.
- * Due to integration set at 800ms, we limit max frequency to 1Hz.
- */
-#define OPT3001_LIGHT_MIN_FREQ          100
-#define OPT3001_LIGHT_MAX_FREQ          1000
-#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= OPT3001_LIGHT_MAX_FREQ)
-#error "EC too slow for light sensor"
-#endif
-
-#ifdef HAS_TASK_ALS
-int opt3001_init(void);
-int opt3001_read_lux(int *lux, int af);
-#else
-#define OPT3001_GET_DATA(_s)	((struct opt3001_drv_data_t *)(_s)->drv_data)
-
-struct opt3001_drv_data_t {
-	int rate;
-	int last_value;
-	/* the coef is scale.uscale */
-	int16_t scale;
-	uint16_t uscale;
-	int16_t offset;
-};
-
-extern const struct accelgyro_drv opt3001_drv;
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ALS
-extern struct i2c_stress_test_dev opt3001_i2c_stress_test_dev;
-#endif
-
-#endif	/* __CROS_EC_ALS_OPT3001_H */
diff --git a/driver/als_si114x.c b/driver/als_si114x.c
deleted file mode 100644
index 262f3f076b..0000000000
--- a/driver/als_si114x.c
+++ /dev/null
@@ -1,596 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Silicon Image SI1141/SI1142 light sensor driver
- *
- * Started from linux si114x driver.
- */
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/als_si114x.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-static int init(struct motion_sensor_t *s);
-
-/**
- * Read 8bit register from device.
- */
-static inline int raw_read8(const int port, const uint16_t i2c_addr_flags,
-			    const int reg, int *data_ptr)
-{
-	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
-}
-
-/**
- * Write 8bit register from device.
- */
-static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
-			     const int reg, int data)
-{
-	return i2c_write8(port, i2c_addr_flags, reg, data);
-}
-
-/**
- * Read 16bit register from device.
- */
-static inline int raw_read16(const int port, const uint16_t i2c_addr_flags,
-			     const int reg, int *data_ptr)
-{
-	return i2c_read16(port, i2c_addr_flags, reg, data_ptr);
-}
-
-/* helper function to operate on parameter values: op can be query/set/or/and */
-static int si114x_param_op(const struct motion_sensor_t *s,
-			   uint8_t op,
-			   uint8_t param,
-			   int *value)
-{
-	int ret;
-
-	mutex_lock(s->mutex);
-
-	if (op != SI114X_COMMAND_PARAM_QUERY) {
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PARAM_WR, *value);
-		if (ret != EC_SUCCESS)
-			goto error;
-	}
-
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_COMMAND, op | (param & 0x1F));
-	if (ret != EC_SUCCESS)
-		goto error;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_PARAM_RD, value);
-	if (ret != EC_SUCCESS)
-		goto error;
-
-	mutex_unlock(s->mutex);
-
-	*value &= 0xff;
-	return EC_SUCCESS;
-error:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int si114x_read_results(struct motion_sensor_t *s, int nb)
-{
-	int i, ret, val;
-	struct si114x_drv_data_t *data = SI114X_GET_DATA(s);
-	struct si114x_typed_data_t *type_data = SI114X_GET_TYPED_DATA(s);
-
-	/* Read ALX result */
-	for (i = 0; i < nb; i++) {
-		ret = raw_read16(s->port, s->i2c_spi_addr_flags,
-				 type_data->base_data_reg + i * 2,
-				 &val);
-		if (ret)
-			break;
-		if (val == SI114X_OVERFLOW) {
-			/* overflowing, try next time. */
-			return EC_SUCCESS;
-		} else if (val + type_data->offset <= 0) {
-			/* No light */
-			val = 1;
-		} else {
-			/* Add offset, calibration */
-			val += type_data->offset;
-		}
-		/*
-		 * Proximity sensor data is inverse of the distance.
-		 * Return back something proportional to distance,
-		 * we correct later with the scale parameter.
-		 */
-		if (s->type == MOTIONSENSE_TYPE_PROX)
-			val = BIT(16) / val;
-		val = val * type_data->scale +
-			val * type_data->uscale / 10000;
-		s->raw_xyz[i] = val;
-	}
-
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (s->type == MOTIONSENSE_TYPE_PROX)
-		data->covered = (s->raw_xyz[0] < SI114X_COVERED_THRESHOLD);
-	else if (data->covered)
-		/*
-		 * The sensor (proximity & light) is covered. The light data
-		 * will most likely be incorrect (darker than expected), so
-		 * ignore the measurement.
-		 */
-		return EC_SUCCESS;
-
-	/* Add in fifo if changed only */
-	for (i = 0; i < nb; i++) {
-		if (s->raw_xyz[i] != s->xyz[i])
-			break;
-	}
-	if (i == nb)
-		return EC_ERROR_UNCHANGED;
-
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-		struct ec_response_motion_sensor_data vector;
-
-		vector.flags = 0;
-		for (i = 0; i < nb; i++)
-			vector.data[i] = s->raw_xyz[i];
-		for (i = nb; i < 3; i++)
-			vector.data[i] = 0;
-		vector.sensor_num = s - motion_sensors;
-		motion_sense_fifo_stage_data(&vector, s, nb,
-					     __hw_clock_source_read());
-		motion_sense_fifo_commit_data();
-		/*
-		 * TODO: get time at a more accurate spot.
-		 * Like in si114x_interrupt
-		 */
-	}
-	/* Otherwise, we need to copy raw_xyz into xyz with mutex */
-	return EC_SUCCESS;
-}
-
-void si114x_interrupt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_SI114X_INT_EVENT);
-}
-
-#ifdef CONFIG_ALS_SI114X_POLLING
-static void si114x_read_deferred(void)
-{
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_SI114X_INT_EVENT);
-}
-DECLARE_DEFERRED(si114x_read_deferred);
-#endif
-
-/**
- * irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt.
- *
- * For now, we just print out. We should set a bitmask motion sense code will
- * act upon.
- */
-static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	int ret = EC_SUCCESS, val;
-	struct si114x_drv_data_t *data = SI114X_GET_DATA(s);
-	struct si114x_typed_data_t *type_data = SI114X_GET_TYPED_DATA(s);
-
-	if (!(*event & CONFIG_ALS_SI114X_INT_EVENT))
-		return EC_ERROR_NOT_HANDLED;
-
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_IRQ_STATUS, &val);
-	if (ret)
-		return ret;
-
-	if (!(val & type_data->irq_flags))
-		return EC_ERROR_INVAL;
-
-	/* clearing IRQ */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_IRQ_STATUS,
-			 val & type_data->irq_flags);
-	if (ret != EC_SUCCESS)
-		CPRINTS("clearing irq failed");
-
-	switch (data->state) {
-	case SI114X_ALS_IN_PROGRESS:
-	case SI114X_ALS_IN_PROGRESS_PS_PENDING:
-		/* We are only reading the visible light sensor */
-		ret = si114x_read_results(s, 1);
-		/* Fire pending requests */
-		if (data->state == SI114X_ALS_IN_PROGRESS_PS_PENDING) {
-			ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-					 SI114X_COMMAND,
-					 SI114X_COMMAND_PS_FORCE);
-			data->state = SI114X_PS_IN_PROGRESS;
-		} else {
-			data->state = SI114X_IDLE;
-		}
-		break;
-	case SI114X_PS_IN_PROGRESS:
-	case SI114X_PS_IN_PROGRESS_ALS_PENDING:
-		/* Read PS results */
-		ret = si114x_read_results(s, SI114X_NUM_LEDS);
-		if (data->state == SI114X_PS_IN_PROGRESS_ALS_PENDING) {
-			ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-					 SI114X_COMMAND,
-					 SI114X_COMMAND_ALS_FORCE);
-			data->state = SI114X_ALS_IN_PROGRESS;
-		} else {
-			data->state = SI114X_IDLE;
-		}
-		break;
-	case SI114X_IDLE:
-	default:
-		CPRINTS("Invalid state");
-	}
-	return ret;
-}
-
-/* Just trigger a measurement */
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	int ret = 0;
-	uint8_t cmd;
-	struct si114x_drv_data_t *data = SI114X_GET_DATA(s);
-
-	switch (data->state) {
-	case SI114X_ALS_IN_PROGRESS:
-		if (s->type == MOTIONSENSE_TYPE_PROX)
-			data->state = SI114X_ALS_IN_PROGRESS_PS_PENDING;
-#if 0
-		else
-			CPRINTS("Invalid state");
-#endif
-		ret = EC_ERROR_BUSY;
-		break;
-	case SI114X_PS_IN_PROGRESS:
-		if (s->type == MOTIONSENSE_TYPE_LIGHT)
-			data->state = SI114X_PS_IN_PROGRESS_ALS_PENDING;
-#if 0
-		else
-			CPRINTS("Invalid state");
-#endif
-		ret = EC_ERROR_BUSY;
-		break;
-	case SI114X_IDLE:
-		switch (s->type) {
-		case MOTIONSENSE_TYPE_LIGHT:
-			cmd = SI114X_COMMAND_ALS_FORCE;
-			data->state = SI114X_ALS_IN_PROGRESS;
-			break;
-		case MOTIONSENSE_TYPE_PROX:
-			cmd = SI114X_COMMAND_PS_FORCE;
-			data->state = SI114X_PS_IN_PROGRESS;
-			break;
-		default:
-			CPRINTS("Invalid sensor type");
-			return EC_ERROR_INVAL;
-		}
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_COMMAND, cmd);
-#ifdef CONFIG_ALS_SI114X_POLLING
-		hook_call_deferred(&si114x_read_deferred_data,
-				   SI114x_POLLING_DELAY);
-#endif
-		ret = EC_RES_IN_PROGRESS;
-		break;
-	case SI114X_ALS_IN_PROGRESS_PS_PENDING:
-	case SI114X_PS_IN_PROGRESS_ALS_PENDING:
-		ret = EC_ERROR_ACCESS_DENIED;
-		break;
-	case SI114X_NOT_READY:
-		ret = EC_ERROR_NOT_POWERED;
-	}
-#if 0 /* This code is incorrect https://crbug.com/956569 */
-	if (ret == EC_ERROR_ACCESS_DENIED &&
-	    s->type == MOTIONSENSE_TYPE_LIGHT) {
-		timestamp_t ts_now = get_time();
-
-		/*
-		 * We were unable to access the sensor for THRES time.
-		 * We should reset the sensor to clear the interrupt register
-		 * and the state machine.
-		 */
-		if (time_after(ts_now.le.lo,
-			       s->last_collection + SI114X_DENIED_THRESHOLD)) {
-			int ret, val;
-
-			ret = raw_read8(s->port, s->addr,
-					SI114X_IRQ_STATUS, &val);
-			CPRINTS("%d stuck IRQ_STATUS 0x%02x - ret %d",
-				s->name, val, ret);
-			init(s);
-		}
-	}
-#endif
-	return ret;
-}
-
-static int si114x_set_chlist(const struct motion_sensor_t *s)
-{
-	int reg = 0;
-
-	/* Not interested in temperature (AUX nor IR) */
-	reg = SI114X_PARAM_CHLIST_EN_ALS_VIS;
-	switch (SI114X_NUM_LEDS) {
-	case 3:
-		reg |= SI114X_PARAM_CHLIST_EN_PS3;
-	case 2:
-		reg |= SI114X_PARAM_CHLIST_EN_PS3;
-	case 1:
-		reg |= SI114X_PARAM_CHLIST_EN_PS3;
-		break;
-	}
-
-	return si114x_param_op(s, SI114X_COMMAND_PARAM_SET,
-			SI114X_PARAM_CHLIST, &reg);
-}
-
-#ifdef CONFIG_ALS_SI114X_CHECK_REVISION
-static int si114x_revisions(const struct motion_sensor_t *s)
-{
-	int val;
-	int ret = raw_read8(s->port, s->addr, SI114X_PART_ID, &val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (val != CONFIG_ALS_SI114X) {
-		CPRINTS("invalid part");
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	ret = raw_read8(s->port, s->port, s->addr, SI114X_SEQ_ID, &val);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	if (val < SI114X_SEQ_REV_A03)
-		CPRINTS("WARNING: old sequencer revision");
-
-	return 0;
-}
-#endif
-
-static int si114x_initialize(const struct motion_sensor_t *s)
-{
-	int ret, val;
-
-	/* send reset command */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_COMMAND, SI114X_COMMAND_RESET);
-	if (ret != EC_SUCCESS)
-		return ret;
-	msleep(20);
-
-	/* hardware key, magic value */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_HW_KEY, SI114X_HW_KEY_VALUE);
-	if (ret != EC_SUCCESS)
-		return ret;
-	msleep(20);
-
-	/* interrupt configuration, interrupt output enable */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_INT_CFG, SI114X_INT_CFG_INT_OE);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* enable interrupt for certain activities */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_IRQ_ENABLE,
-			 SI114X_IRQ_ENABLE_PS3_IE |
-			 SI114X_IRQ_ENABLE_PS2_IE |
-			 SI114X_IRQ_ENABLE_PS1_IE |
-			 SI114X_IRQ_ENABLE_ALS_IE_INT0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Only forced mode */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_MEAS_RATE, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* measure ALS every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_ALS_RATE, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* measure proximity every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_PS_RATE, 0);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* set LED currents to maximum */
-	switch (SI114X_NUM_LEDS) {
-	case 3:
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PS_LED3, 0x0f);
-		if (ret != EC_SUCCESS)
-			return ret;
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PS_LED21, 0xff);
-		break;
-	case 2:
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PS_LED21, 0xff);
-		break;
-	case 1:
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PS_LED21, 0x0f);
-		break;
-	}
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	ret = si114x_set_chlist(s);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* set normal proximity measurement mode, set high signal range
-	 * PS measurement */
-	val = SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY;
-	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET,
-			      SI114X_PARAM_PS_ADC_MISC, &val);
-	return ret;
-}
-
-static int set_resolution(const struct motion_sensor_t *s,
-				int res,
-				int rnd)
-{
-	int ret, reg1, reg2, val;
-	/* override on resolution: set the gain. between 0 to 7 */
-	if (s->type == MOTIONSENSE_TYPE_PROX) {
-		if (res < 0 || res > 5)
-			return EC_ERROR_PARAM2;
-		reg1 = SI114X_PARAM_PS_ADC_GAIN;
-		reg2 = SI114X_PARAM_PS_ADC_COUNTER;
-	} else {
-		if (res < 0 || res > 7)
-			return EC_ERROR_PARAM2;
-		reg1 = SI114X_PARAM_ALS_VIS_ADC_GAIN;
-		reg2 = SI114X_PARAM_ALS_VIS_ADC_COUNTER;
-	}
-
-	val = res;
-	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET, reg1, &val);
-	if (ret != EC_SUCCESS)
-		return ret;
-	/* set recovery period to one's complement of gain */
-	val = (~res & 0x07) << 4;
-	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_SET, reg2, &val);
-	return ret;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	int ret, reg, val;
-	if (s->type == MOTIONSENSE_TYPE_PROX)
-		reg = SI114X_PARAM_PS_ADC_GAIN;
-	else
-		/* ignore IR led */
-		reg = SI114X_PARAM_ALS_VIS_ADC_GAIN;
-
-	val = 0;
-	ret = si114x_param_op(s, SI114X_COMMAND_PARAM_QUERY, reg, &val);
-	if (ret != EC_SUCCESS)
-		return -1;
-
-	return val & 0x07;
-}
-
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
-{
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	data->scale = range >> 16;
-	data->uscale = range & 0xffff;
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	/* Sensor in forced mode, rate is used by motion_sense */
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	return data->rate;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
-{
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	data->rate = rate;
-	return EC_SUCCESS;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	data->offset = offset[X];
-	return EC_SUCCESS;
-}
-
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
-{
-	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
-	offset[X] = data->offset;
-	offset[Y] = 0;
-	offset[Z] = 0;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret, resol;
-	struct si114x_drv_data_t *data = SI114X_GET_DATA(s);
-
-	/* initialize only once: light must be declared first. */
-	if (s->type == MOTIONSENSE_TYPE_LIGHT) {
-#ifdef CONFIG_ALS_SI114X_CHECK_REVISION
-		ret = si114x_revisions(s);
-		if (ret != EC_SUCCESS)
-			return ret;
-#endif
-		ret = si114x_initialize(s);
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		data->state = SI114X_IDLE;
-		resol = 7;
-	} else {
-		if (data->state == SI114X_NOT_READY)
-			return EC_ERROR_ACCESS_DENIED;
-		resol = 5;
-	}
-
-	/*
-	 * Sensor is most likely behind a glass.
-	 * Max out the gain to get correct measurement
-	 */
-	set_resolution(s, resol, 0);
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv si114x_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.set_resolution = set_resolution,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = irq_handler,
-#endif
-};
diff --git a/driver/als_si114x.h b/driver/als_si114x.h
deleted file mode 100644
index 2084c55f09..0000000000
--- a/driver/als_si114x.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Silicon Image SI1141/SI1142 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_SI114X_H
-#define __CROS_EC_ALS_SI114X_H
-
-#define SI114X_ADDR_FLAGS               0x5a
-
-#define SI114X_PART_ID		0x00
-#define SI114X_SEQ_ID		0x02
-
-#define SI114X_INT_CFG		0x03
-#define SI114X_INT_CFG_INT_OE		BIT(0)
-
-#define SI114X_IRQ_ENABLE	0x04
-#define SI114X_IRQ_ENABLE_PS3_IE	BIT(4)
-#define SI114X_IRQ_ENABLE_PS2_IE	BIT(3)
-#define SI114X_IRQ_ENABLE_PS1_IE	BIT(2)
-#define SI114X_IRQ_ENABLE_ALS_IE_INT1	BIT(1)
-#define SI114X_IRQ_ENABLE_ALS_IE_INT0	BIT(0)
-
-#define SI114X_HW_KEY		0x07
-#define SI114X_HW_KEY_VALUE		0x17
-
-#define SI114X_MEAS_RATE	0x08
-#define SI114X_ALS_RATE		0x09
-#define SI114X_PS_RATE		0x0A
-
-#define SI114X_PS_LED21		0x0F
-#define SI114X_PS_LED3		0x10
-#define SI114X_NUM_LEDS  (CONFIG_ALS_SI114X - 0x40)
-
-#define SI114X_PARAM_WR		0x17
-#define SI114X_COMMAND		0x18
-
-#define SI114X_COMMAND_PARAM_QUERY	0x80
-#define SI114X_COMMAND_PARAM_SET	0xA0
-#define SI114X_PARAM_CHLIST			0x01
-#define SI114X_PARAM_CHLIST_EN_ALS_VIS			BIT(4)
-#define SI114X_PARAM_CHLIST_EN_PS3			BIT(2)
-#define SI114X_PARAM_CHLIST_EN_PS2			BIT(1)
-#define SI114X_PARAM_CHLIST_EN_PS1			BIT(0)
-#define SI114X_PARAM_PS_ADC_COUNTER		0x0A
-#define SI114X_PARAM_PS_ADC_GAIN		0x0B
-#define SI114X_PARAM_PS_ADC_MISC		0x0C
-#define SI114X_PARAM_PS_ADC_MISC_MODE			BIT(2)
-#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY	BIT(2)
-#define SI114X_PARAM_ALS_VIS_ADC_COUNTER	0x10
-#define SI114X_PARAM_ALS_VIS_ADC_GAIN		0x11
-#define SI114X_PARAM_ALS_VIS_ADC_MISC		0x12
-
-#define SI114X_COMMAND_RESET		0x01
-#define SI114X_COMMAND_PS_FORCE		0x05
-#define SI114X_COMMAND_ALS_FORCE	0x06
-
-#define SI114X_IRQ_STATUS	0x21
-#define SI114X_ALS_VIS_DATA0	0x22
-
-#define SI114X_PARAM_RD		0x2E
-
-/* Proximity sensor finds an object within 5 cm, disable light sensor */
-#define SI114X_COVERED_THRESHOLD        5
-#define SI114X_OVERFLOW                 0xffff
-
-/* Time to wait before re-initializing the device if access is denied */
-#define SI114X_DENIED_THRESHOLD		(10 * SECOND)
-
-/* Delay used for deferred callback when polling is enabled */
-#define SI114x_POLLING_DELAY (8 * MSEC)
-
-/* Min and Max sampling frequency in mHz */
-#define SI114X_PROX_MIN_FREQ            504
-#define SI114X_PROX_MAX_FREQ            50000
-#define SI114X_LIGHT_MIN_FREQ           504
-#define SI114X_LIGHT_MAX_FREQ           50000
-#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= SI114X_PROX_MAX_FREQ)
-#error "EC too slow for light sensor"
-#endif
-
-extern const struct accelgyro_drv si114x_drv;
-
-enum si114x_state {
-	SI114X_NOT_READY,
-	SI114X_IDLE,
-	SI114X_ALS_IN_PROGRESS,
-	SI114X_ALS_IN_PROGRESS_PS_PENDING,
-	SI114X_PS_IN_PROGRESS,
-	SI114X_PS_IN_PROGRESS_ALS_PENDING,
-};
-
-struct si114x_typed_data_t {
-	uint8_t base_data_reg;
-	uint8_t irq_flags;
-	/* requested frequency, in mHz */
-	int rate;
-	/* the coef is scale.uscale */
-	int16_t scale;
-	uint16_t uscale;
-	int16_t offset;
-};
-
-struct si114x_drv_data_t {
-	enum si114x_state state;
-	uint8_t covered;
-	struct si114x_typed_data_t type_data[2];
-};
-
-#define SI114X_GET_DATA(_s) \
-	((struct si114x_drv_data_t *)(_s)->drv_data)
-
-#define SI114X_GET_TYPED_DATA(_s) \
-	(&SI114X_GET_DATA(_s)->type_data[(_s)->type - MOTIONSENSE_TYPE_PROX])
-
-void si114x_interrupt(enum gpio_signal signal);
-
-#endif	/* __CROS_EC_ALS_SI114X_H */
diff --git a/driver/als_tcs3400.c b/driver/als_tcs3400.c
deleted file mode 100644
index 30b24c4412..0000000000
--- a/driver/als_tcs3400.c
+++ /dev/null
@@ -1,816 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMS TCS3400 light sensor driver
- */
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "als_tcs3400.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "motion_sense_fifo.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s "fmt, __func__, ## args)
-
-#if defined(CONFIG_ZEPHYR) && defined(CONFIG_ACCEL_INTERRUPTS)
-/*
- * Get the mostion sensor ID of the TCS3400 sensor that
- * generates the interrupt.
- * The interrupt is converted to the event and transferred to motion
- * sense task that actually handles the interrupt.
- *
- * Here, we use alias to get the motion sensor ID
- *
- * e.g) als_clear below is the label of a child node in /motionsense-sensors
- * aliases {
- *     tcs3400-int = &als_clear;
- * };
- */
-#if DT_NODE_EXISTS(DT_ALIAS(tcs3400_int))
-#define CONFIG_ALS_TCS3400_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
-#endif
-#endif
-
-STATIC_IF(CONFIG_ACCEL_FIFO) volatile uint32_t last_interrupt_timestamp;
-
-#ifdef CONFIG_TCS_USE_LUX_TABLE
-/*
- * Stores the number of atime increments/decrements needed to change light value
- * by 1% of saturation for each gain setting for each predefined LUX range.
- *
- * Values in array are TCS_ATIME_GAIN_FACTOR (100x) times actual value to allow
- * for fractions using integers.
- */
-static const uint16_t
-range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN + 1][TCS_MAX_ATIME_RANGES] = {
-{11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575, 2275, 2075},
-{11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577, 525},
-{250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0},
-{790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} };
-
-static void
-decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux, int percent)
-{
-	int atime;
-	uint16_t steps;
-	int lux = MIN(cur_lux, TCS_GAIN_TABLE_MAX_LUX);
-
-	steps = percent * range_atime[sat_p->again][lux / 1000] /
-			TCS_ATIME_GAIN_FACTOR;
-	atime = MAX(sat_p->atime - steps, TCS_MIN_ATIME);
-	sat_p->atime = MIN(atime, TCS_MAX_ATIME);
-}
-
-#else
-
-static void
-decrement_atime(struct tcs_saturation_t *sat_p,
-		uint16_t __attribute__((unused)) cur_lux,
-		int __attribute__((unused)) percent)
-{
-	sat_p->atime = MAX(sat_p->atime - TCS_ATIME_DEC_STEP, TCS_MIN_ATIME);
-}
-
-#endif /* CONFIG_TCS_USE_LUX_TABLE */
-
-static void increment_atime(struct tcs_saturation_t *sat_p)
-{
-	sat_p->atime = MIN(sat_p->atime + TCS_ATIME_INC_STEP, TCS_MAX_ATIME);
-}
-
-static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s,
-				    int reg, int *data)
-{
-	return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data);
-}
-
-static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s,
-				     int reg, int data)
-{
-	return i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data);
-}
-
-static void tcs3400_read_deferred(void)
-{
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_TCS3400_INT_EVENT);
-}
-DECLARE_DEFERRED(tcs3400_read_deferred);
-
-/* convert ATIME register to integration time, in microseconds */
-int tcs3400_get_integration_time(int atime)
-{
-	return TCS_MAX_INTEGRATION_TIME * (TCS_ATIME_GRANULARITY - atime);
-}
-
-static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	int atime, again;
-	int ret;
-
-	/* Chip may have been off, make sure to setup important registers */
-	if (TCS3400_RGB_DRV_DATA(s+1)->calibration_mode) {
-		atime = TCS_CALIBRATION_ATIME;
-		again = TCS_CALIBRATION_AGAIN;
-	} else {
-		atime = TCS3400_RGB_DRV_DATA(s+1)->saturation.atime;
-		again = TCS3400_RGB_DRV_DATA(s+1)->saturation.again;
-	}
-	ret = tcs3400_i2c_write8(s, TCS_I2C_ATIME, atime);
-	if (ret)
-		return ret;
-	ret = tcs3400_i2c_write8(s, TCS_I2C_CONTROL, again);
-	if (ret)
-		return ret;
-
-	/* Enable power, ADC, and interrupt to start cycle */
-	ret = tcs3400_i2c_write8(s, TCS_I2C_ENABLE, TCS3400_MODE_COLLECTING);
-	if (ret)
-		return ret;
-
-	if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		int atime;
-
-		ret = tcs3400_i2c_read8(s, TCS_I2C_ATIME, &atime);
-		if (ret)
-			return ret;
-
-		hook_call_deferred(&tcs3400_read_deferred_data,
-				tcs3400_get_integration_time(atime));
-	}
-
-	/*
-	 * If write succeeded, we've started the read process, but can't
-	 * complete it yet until data is ready, so pass back EC_RES_IN_PROGRESS
-	 * to inform upper level that read data process is under way and data
-	 * will be delivered when available.
-	 */
-	return EC_RES_IN_PROGRESS;
-}
-
-static int tcs3400_rgb_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	ccprintf("WARNING: tcs3400_rgb_read() should never be called\n");
-	return EC_SUCCESS;
-}
-
-/*
- * tcs3400_adjust_sensor_for_saturation() tries to keep CRGB values as
- * close to saturation as possible without saturating by implementing
- * the following logic:
- *
- * If any of the R, G, B, or C channels have saturated, then decrease AGAIN.
- * If AGAIN is already at its minimum, increase ATIME if not at its max already.
- *
- * Else if none of the R, G, B, or C channels have saturated, and
- * all samples read are less than 90% of saturation, then increase
- * AGAIN if it is not already at its maximum, or if it is, decrease
- * ATIME if it is not at it's minimum already.
- */
-static int
-tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
-				     uint16_t cur_lux,
-				     uint16_t *crgb_data,
-				     uint32_t status)
-{
-	struct tcs_saturation_t *sat_p =
-			&TCS3400_RGB_DRV_DATA(s+1)->saturation;
-	const uint8_t save_again = sat_p->again;
-	const uint8_t save_atime = sat_p->atime;
-	uint16_t max_val =  0;
-	int ret;
-	int percent_left = 0;
-
-	/* Adjust for saturation if needed */
-	if (!(status & TCS_I2C_STATUS_RGBC_VALID))
-		return EC_SUCCESS;
-
-	for (int i = 0; i < CRGB_COUNT; i++)
-		max_val = MAX(max_val, crgb_data[i]);
-
-	/* Don't process if status isn't valid yet */
-	if ((status & TCS_I2C_STATUS_ALS_SATURATED) ||
-			(max_val >= TCS_SATURATION_LEVEL)) {
-		/* Saturation occurred, decrease AGAIN if we can */
-		if (sat_p->again > TCS_MIN_AGAIN)
-			sat_p->again--;
-		else if (sat_p->atime < TCS_MAX_ATIME)
-			/* reduce accumulation time by incrementing ATIME reg */
-			increment_atime(sat_p);
-	} else if (max_val < TSC_SATURATION_LOW_BAND_LEVEL) {
-		/* value < 90% saturation, try to increase sensitivity */
-		if (max_val <= TCS_GAIN_SAT_LEVEL) {
-			if (sat_p->again < TCS_MAX_AGAIN) {
-				sat_p->again++;
-			} else if (sat_p->atime > TCS_MIN_ATIME) {
-				/*
-				 * increase accumulation time by decrementing
-				 * ATIME register
-				 */
-				percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
-					(max_val * 100 / TCS_SATURATION_LEVEL);
-				decrement_atime(sat_p, cur_lux, percent_left);
-			}
-		} else if (sat_p->atime > TCS_MIN_ATIME) {
-			/* calculate percentage between current and desired */
-			percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
-				(max_val * 100 / TCS_SATURATION_LEVEL);
-
-			/* increase accumulation time by decrementing ATIME */
-			decrement_atime(sat_p, cur_lux, percent_left);
-		} else if (sat_p->again < TCS_MAX_AGAIN) {
-			/*
-			 * Although we're not at maximum gain yet, we
-			 * can't just increase gain because a 4x change
-			 * in gain under these light conditions would
-			 * saturate on the next sample.  What we can do
-			 * is to adjust atime to reduce sensitivity so
-			 * that we may increase gain without saturation.
-			 * This combination effectively acts as a half
-			 * gain increase (2.5x estimate) instead of a full
-			 * gain increase of > 4x that would result in
-			 * saturation.
-			 */
-			if (max_val < TCS_GAIN_UPSHIFT_LEVEL) {
-				sat_p->atime = TCS_GAIN_UPSHIFT_ATIME;
-				sat_p->again++;
-			}
-		}
-	}
-
-	/* If atime or gain setting changed, update atime and gain registers */
-	if (save_again != sat_p->again) {
-		ret = tcs3400_i2c_write8(s, TCS_I2C_CONTROL,
-				(sat_p->again & TCS_I2C_CONTROL_MASK));
-		if (ret)
-			return ret;
-	}
-
-	if (save_atime != sat_p->atime) {
-		ret = tcs3400_i2c_write8(s, TCS_I2C_ATIME, sat_p->atime);
-		if (ret)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * normalize_channel_data - normalize the light data to remove effect of
- * different atime and again settings from the sample.
- */
-static uint32_t normalize_channel_data(struct motion_sensor_t *s,
-					uint32_t  sample)
-{
-	struct tcs_saturation_t *sat_p =
-				&(TCS3400_RGB_DRV_DATA(s+1)->saturation);
-	const uint16_t cur_gain = (1 << (2 * sat_p->again));
-	const uint16_t cal_again = (1 << (2 * TCS_CALIBRATION_AGAIN));
-
-	return DIV_ROUND_NEAREST(sample * (TCS_ATIME_GRANULARITY -
-				TCS_CALIBRATION_ATIME) * cal_again,
-				(TCS_ATIME_GRANULARITY - sat_p->atime) *
-				cur_gain);
-}
-
-
-__overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
-				     int32_t *crgb_data, int32_t *xyz_data)
-{
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
-	int32_t crgb_prime[CRGB_COUNT];
-	int32_t ir;
-	int i;
-
-	/* normalize the data for atime and again changes */
-	for (i = 0; i < CRGB_COUNT; i++)
-		crgb_data[i] = normalize_channel_data(s, crgb_data[i]);
-
-	/* IR removal */
-	ir = FP_TO_INT(fp_mul(INT_TO_FP(crgb_data[1] + crgb_data[2] +
-			      crgb_data[3] - crgb_data[0]),
-			      rgb_drv_data->calibration.irt) / 2);
-
-	for (i = 0; i < ARRAY_SIZE(crgb_prime); i++) {
-		if (crgb_data[i] < ir)
-			crgb_prime[i] = 0;
-		else
-			crgb_prime[i] = crgb_data[i] - ir;
-	}
-
-	/* if CC == 0, set BC = 0 */
-	if (crgb_prime[CLEAR_CRGB_IDX] == 0)
-		crgb_prime[BLUE_CRGB_IDX] = 0;
-
-	/* regression fit to XYZ space */
-	for (i = 0; i < 3; i++) {
-		const struct rgb_channel_calibration_t *p =
-				&rgb_drv_data->calibration.rgb_cal[i];
-
-		xyz_data[i] = p->offset + FP_TO_INT(
-			(fp_inter_t)p->coeff[RED_CRGB_IDX] *
-					crgb_prime[RED_CRGB_IDX] +
-			(fp_inter_t)p->coeff[GREEN_CRGB_IDX] *
-					crgb_prime[GREEN_CRGB_IDX] +
-			(fp_inter_t)p->coeff[BLUE_CRGB_IDX] *
-					crgb_prime[BLUE_CRGB_IDX] +
-			(fp_inter_t)p->coeff[CLEAR_CRGB_IDX] *
-					crgb_prime[CLEAR_CRGB_IDX]);
-
-		if (xyz_data[i] < 0)
-			xyz_data[i] = 0;
-	}
-}
-
-static void tcs3400_process_raw_data(struct motion_sensor_t *s,
-				    uint8_t *raw_data_buf,
-				    uint16_t *raw_light_data, int32_t *xyz_data)
-{
-	struct als_drv_data_t *als_drv_data = TCS3400_DRV_DATA(s);
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
-	const uint8_t calibration_mode = rgb_drv_data->calibration_mode;
-	uint16_t  k_channel_scale =
-			als_drv_data->als_cal.channel_scale.k_channel_scale;
-	uint16_t cover_scale = als_drv_data->als_cal.channel_scale.cover_scale;
-	int32_t crgb_data[CRGB_COUNT];
-	int i;
-
-	/* adjust for calibration and scale data */
-	for (i = 0; i < CRGB_COUNT; i++) {
-		int index = i * 2;
-
-		/* assemble the light value for this channel */
-		crgb_data[i] = raw_light_data[i] =
-			((raw_data_buf[index+1] << 8) | raw_data_buf[index]);
-
-		/* in calibration mode, we only assemble the raw data */
-		if (calibration_mode)
-			continue;
-
-		/* rgb data at index 1, 2, and 3 owned by rgb driver, not ALS */
-		if (i > 0) {
-			struct als_channel_scale_t *csp =
-				&rgb_drv_data->calibration.rgb_cal[i-1].scale;
-			k_channel_scale = csp->k_channel_scale;
-			cover_scale = csp->cover_scale;
-		}
-
-		/* Step 1: divide by individual channel scale value */
-		crgb_data[i] = SENSOR_APPLY_DIV_SCALE(crgb_data[i],
-							k_channel_scale);
-
-		/* compensate for the light cover */
-		crgb_data[i] = SENSOR_APPLY_SCALE(crgb_data[i], cover_scale);
-	}
-
-	if (!calibration_mode) {
-		/* we're not in calibration mode & we want xyz translation */
-		tcs3400_translate_to_xyz(s, crgb_data, xyz_data);
-	} else {
-		/* normalize the data for atime and again changes */
-		for (i = 0; i < CRGB_COUNT; i++)
-			crgb_data[i] = normalize_channel_data(s, crgb_data[i]);
-
-		/* calibration mode returns raw data */
-		for (i = 0; i < 3; i++)
-			xyz_data[i] = crgb_data[i+1];
-	}
-}
-
-static int32_t get_lux_from_xyz(struct motion_sensor_t *s, int32_t *xyz_data)
-{
-	int32_t lux = xyz_data[Y];
-	const int32_t offset =
-		TCS3400_RGB_DRV_DATA(s+1)->calibration.rgb_cal[Y].offset;
-
-	/*
-	 * Do not include the offset when determining LUX from XYZ.
-	 */
-	lux = MAX(0, lux - offset);
-
-	return lux;
-}
-
-static bool is_spoof(struct motion_sensor_t *s)
-{
-	return IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) &&
-	       (s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE);
-}
-
-static int tcs3400_post_events(struct motion_sensor_t *s,
-			       uint32_t last_ts,
-			       uint32_t status)
-{
-	/*
-	 * Rule says RGB sensor is right after ALS sensor.
-	 * This routine will only get called from ALS sensor driver.
-	 */
-	struct motion_sensor_t *rgb_s = s + 1;
-	const uint8_t is_calibration =
-			TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode;
-	struct ec_response_motion_sensor_data vector = { .flags = 0, };
-	uint8_t buf[TCS_RGBC_DATA_SIZE]; /* holds raw data read from chip */
-	int32_t xyz_data[3] = { 0, 0, 0 };
-	uint16_t raw_data[CRGB_COUNT]; /* holds raw CRGB assembled from buf[] */
-	int *last_v;
-	int32_t lux = 0;
-	int ret;
-
-	if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		int i = 5;	/* 100ms max */
-
-		while (i--) {
-			/* Make sure data is valid */
-			if (status & TCS_I2C_STATUS_RGBC_VALID)
-				break;
-			msleep(20);
-			/*
-			 * When not in interrupt mode, we could have scheduled
-			 * the handler too early.
-			 */
-			ret = tcs3400_i2c_read8(s, TCS_I2C_STATUS, &status);
-			if (ret)
-				return ret;
-		}
-		if (i < 0) {
-			CPRINTS("RGBC invalid (0x%x)", status);
-			return EC_ERROR_UNCHANGED;
-		}
-	}
-
-	/* Read the light registers */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			TCS_DATA_START_LOCATION,
-			buf, sizeof(buf));
-	if (ret)
-		return ret;
-
-	/* Process the raw light data, adjusting for scale and calibration */
-	tcs3400_process_raw_data(s, buf, raw_data, xyz_data);
-
-	/* get lux value */
-	lux = is_calibration ? xyz_data[Y] : get_lux_from_xyz(s, xyz_data);
-
-	/* if clear channel data changed, send illuminance upstream */
-	last_v = s->raw_xyz;
-	if (is_calibration ||
-	    ((raw_data[CLEAR_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-	     (last_v[X] != lux))) {
-		if (is_spoof(s))
-			last_v[X] = s->spoof_xyz[X];
-		else
-			last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] : lux;
-
-		vector.udata[X] = ec_motion_sensor_clamp_u16(last_v[X]);
-		vector.udata[Y] = 0;
-		vector.udata[Z] = 0;
-
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			vector.sensor_num = s - motion_sensors;
-			motion_sense_fifo_stage_data(&vector, s, 3, last_ts);
-		}
-	}
-
-	/*
-	 * If rgb channel data changed since last sample and didn't saturate,
-	 * send it upstream
-	 */
-	last_v = rgb_s->raw_xyz;
-	if (is_calibration ||
-	    (((last_v[X] != xyz_data[X]) || (last_v[Y] != xyz_data[Y]) ||
-	     (last_v[Z] != xyz_data[Z])) &&
-	     ((raw_data[RED_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-	      (raw_data[BLUE_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
-	      (raw_data[GREEN_CRGB_IDX] != TCS_SATURATION_LEVEL)))) {
-
-		if (is_spoof(rgb_s)) {
-			memcpy(last_v, rgb_s->spoof_xyz, sizeof(rgb_s->spoof_xyz));
-		} else if (is_calibration) {
-			last_v[0] = raw_data[RED_CRGB_IDX];
-			last_v[1] = raw_data[GREEN_CRGB_IDX];
-			last_v[2] = raw_data[BLUE_CRGB_IDX];
-		} else {
-			memcpy(last_v, xyz_data, sizeof(xyz_data));
-		}
-
-		ec_motion_sensor_clamp_u16s(vector.udata, last_v);
-
-		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-			vector.sensor_num = rgb_s - motion_sensors;
-			motion_sense_fifo_stage_data(&vector, rgb_s, 3, last_ts);
-		}
-	}
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		motion_sense_fifo_commit_data();
-
-	if (!is_calibration)
-		ret = tcs3400_adjust_sensor_for_saturation(s, xyz_data[Y],
-							   raw_data, status);
-
-	return ret;
-}
-
-void tcs3400_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-		last_interrupt_timestamp = __hw_clock_source_read();
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_ALS_TCS3400_INT_EVENT);
-}
-
-/*
- * tcs3400_irq_handler - bottom half of the interrupt stack.
- * Ran from the motion_sense task, finds the events that raised the interrupt,
- * and posts those events via motion_sense_fifo_stage_data()..
- *
- * This routine will get called for the TCS3400 ALS driver, but NOT for the
- * RGB driver.  We harvest data for both drivers in this routine.  The RGB
- * driver is guaranteed to directly follow the ALS driver in the sensor list
- * (i.e rgb's motion_sensor_t structure can be found at (s+1) ).
- */
-static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	uint32_t status = 0;
-	int ret;
-
-	if (!(*event & CONFIG_ALS_TCS3400_INT_EVENT))
-		return EC_ERROR_NOT_HANDLED;
-
-	ret = tcs3400_i2c_read8(s, TCS_I2C_STATUS, &status);
-	if (ret)
-		return ret;
-
-	/* Disable future interrupts */
-	ret = tcs3400_i2c_write8(s, TCS_I2C_ENABLE, TCS3400_MODE_IDLE);
-	if (ret)
-		return ret;
-
-	if ((status & TCS_I2C_STATUS_RGBC_VALID) ||
-	    IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		ret = tcs3400_post_events(s, last_interrupt_timestamp, status);
-		if (ret)
-			return ret;
-	}
-
-	tcs3400_i2c_write8(s, TCS_I2C_AICLEAR, 0);
-
-	/* Disable ADC and turn off internal oscillator */
-	ret = tcs3400_i2c_write8(s, TCS_I2C_ENABLE, TCS3400_MODE_SUSPEND);
-	if (ret)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
-{
-	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
-
-	scale[X] = rgb_cal[RED_RGB_IDX].scale.k_channel_scale;
-	scale[Y] = rgb_cal[GREEN_RGB_IDX].scale.k_channel_scale;
-	scale[Z] = rgb_cal[BLUE_RGB_IDX].scale.k_channel_scale;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
-{
-	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
-
-	if (scale[X] == 0 || scale[Y] == 0 || scale[Z] == 0)
-		return EC_ERROR_INVAL;
-	rgb_cal[RED_RGB_IDX].scale.k_channel_scale = scale[X];
-	rgb_cal[GREEN_RGB_IDX].scale.k_channel_scale = scale[Y];
-	rgb_cal[BLUE_RGB_IDX].scale.k_channel_scale = scale[Z];
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s,
-				  int16_t *offset,
-				  int16_t *temp)
-{
-	offset[X] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[X].offset;
-	offset[Y] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[Y].offset;
-	offset[Z] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[Z].offset;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_set_offset(const struct motion_sensor_t *s,
-				  const int16_t *offset,
-				  int16_t temp)
-{
-	/* do not allow offset to be changed, it's predetermined */
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s,
-				     int rate,
-				     int rnd)
-{
-	return EC_SUCCESS;
-}
-
-/* Enable/disable special factory calibration mode */
-static int tcs3400_perform_calib(struct motion_sensor_t *s, int enable)
-{
-	TCS3400_RGB_DRV_DATA(s+1)->calibration_mode = enable;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_rgb_set_range(struct motion_sensor_t *s,
-				 int range,
-				 int rnd)
-{
-	return EC_SUCCESS;
-}
-
-static int tcs3400_set_range(struct motion_sensor_t *s,
-			     int range,
-			     int rnd)
-{
-	TCS3400_DRV_DATA(s)->als_cal.scale = range >> 16;
-	TCS3400_DRV_DATA(s)->als_cal.uscale = range & 0xffff;
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
-{
-	scale[X] = TCS3400_DRV_DATA(s)->als_cal.channel_scale.k_channel_scale;
-	scale[Y] = 0;
-	scale[Z] = 0;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
-{
-	if (scale[X] == 0)
-		return EC_ERROR_INVAL;
-	TCS3400_DRV_DATA(s)->als_cal.channel_scale.k_channel_scale = scale[X];
-	return EC_SUCCESS;
-}
-
-static int tcs3400_get_offset(const struct motion_sensor_t *s,
-			      int16_t *offset,
-			      int16_t *temp)
-{
-	offset[X] = TCS3400_DRV_DATA(s)->als_cal.offset;
-	offset[Y] = 0;
-	offset[Z] = 0;
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int tcs3400_set_offset(const struct motion_sensor_t *s,
-			      const int16_t *offset,
-			      int16_t temp)
-{
-	/* do not allow offset to be changed, it's predetermined */
-	return EC_SUCCESS;
-}
-
-static int tcs3400_get_data_rate(const struct motion_sensor_t *s)
-{
-	return TCS3400_DRV_DATA(s)->rate;
-}
-
-static int tcs3400_rgb_get_data_rate(const struct motion_sensor_t *s)
-{
-	return tcs3400_get_data_rate(s - 1);
-}
-
-static int tcs3400_set_data_rate(const struct motion_sensor_t *s,
-				 int rate,
-				 int rnd)
-{
-	enum tcs3400_mode mode;
-	int data;
-	int ret;
-
-	if (rate == 0) {
-		/* Suspend driver */
-		mode = TCS3400_MODE_SUSPEND;
-	} else {
-		/*
-		 * We set the sensor for continuous mode,
-		 * integrating over 800ms.
-		 * Do not allow range higher than 1Hz.
-		 */
-		if (rate > TCS3400_LIGHT_MAX_FREQ)
-			rate = TCS3400_LIGHT_MAX_FREQ;
-		mode = TCS3400_MODE_COLLECTING;
-	}
-	TCS3400_DRV_DATA(s)->rate = rate;
-
-	ret = tcs3400_i2c_read8(s, TCS_I2C_ENABLE, &data);
-	if (ret)
-		return ret;
-
-	data = (data & TCS_I2C_ENABLE_MASK) | mode;
-	ret = tcs3400_i2c_write8(s, TCS_I2C_ENABLE, data);
-
-	return ret;
-}
-
-/**
- * Initialise TCS3400 light sensor.
- */
-static int tcs3400_rgb_init(struct motion_sensor_t *s)
-{
-	return EC_SUCCESS;
-}
-
-static int tcs3400_init(struct motion_sensor_t *s)
-{
-	/*
-	 * These are default power-on register values with two exceptions:
-	 * Set ATIME = 0 (712 ms)
-	 * Set AGAIN = 16 (0x10)  (AGAIN is in CONTROL register)
-	 */
-	const struct reg_data {
-		uint8_t reg;
-		uint8_t data;
-	} defaults[] = {
-		{ TCS_I2C_ENABLE, 0 },
-		{ TCS_I2C_ATIME, TCS_DEFAULT_ATIME },
-		{ TCS_I2C_WTIME, 0xFF },
-		{ TCS_I2C_AILTL, 0 },
-		{ TCS_I2C_AILTH, 0 },
-		{ TCS_I2C_AIHTL, 0 },
-		{ TCS_I2C_AIHTH, 0 },
-		{ TCS_I2C_PERS, 0 },
-		{ TCS_I2C_CONFIG, 0x40 },
-		{ TCS_I2C_CONTROL, (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) },
-		{ TCS_I2C_AUX, 0 },
-		{ TCS_I2C_IR, 0 },
-		{ TCS_I2C_CICLEAR, 0 },
-		{ TCS_I2C_AICLEAR, 0 }
-	};
-	int data = 0;
-	int ret;
-
-	ret = tcs3400_i2c_read8(s, TCS_I2C_ID, &data);
-	if (ret) {
-		CPRINTS("failed reading ID reg 0x%x, ret=%d", TCS_I2C_ID, ret);
-		return ret;
-	}
-	if ((data != TCS340015_DEVICE_ID) && (data != TCS340037_DEVICE_ID)) {
-		CPRINTS("no ID match, data = 0x%x", data);
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* reset chip to default power-on settings, changes ATIME and CONTROL */
-	for (int x = 0; x < ARRAY_SIZE(defaults); x++) {
-		ret = tcs3400_i2c_write8(s, defaults[x].reg, defaults[x].data);
-		if (ret)
-			return ret;
-	}
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv tcs3400_drv = {
-	.init = tcs3400_init,
-	.read = tcs3400_read,
-	.set_range = tcs3400_set_range,
-	.set_offset = tcs3400_set_offset,
-	.get_offset = tcs3400_get_offset,
-	.set_scale = tcs3400_set_scale,
-	.get_scale = tcs3400_get_scale,
-	.set_data_rate = tcs3400_set_data_rate,
-	.get_data_rate = tcs3400_get_data_rate,
-	.perform_calib = tcs3400_perform_calib,
-#ifdef CONFIG_ACCEL_INTERRUPTS
-	.irq_handler = tcs3400_irq_handler,
-#endif
-};
-
-const struct accelgyro_drv tcs3400_rgb_drv = {
-	.init = tcs3400_rgb_init,
-	.read = tcs3400_rgb_read,
-	.set_range = tcs3400_rgb_set_range,
-	.set_offset = tcs3400_rgb_set_offset,
-	.get_offset = tcs3400_rgb_get_offset,
-	.set_scale = tcs3400_rgb_set_scale,
-	.get_scale = tcs3400_rgb_get_scale,
-	.set_data_rate = tcs3400_rgb_set_data_rate,
-	.get_data_rate = tcs3400_rgb_get_data_rate,
-};
diff --git a/driver/amd_stt.c b/driver/amd_stt.c
deleted file mode 100644
index 90fd82523b..0000000000
--- a/driver/amd_stt.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "amd_stt.h"
-#include "common.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/sb_rmi.h"
-#include "hooks.h"
-#include "math_util.h"
-#include "temp_sensor.h"
-#include "util.h"
-
-/* Debug flag can be toggled with console command: stt debug */
-static bool amd_stt_debug;
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-static const char * const amd_stt_sensor_name[] = {
-	[AMD_STT_PCB_SENSOR_APU] = "APU",
-	[AMD_STT_PCB_SENSOR_REMOTE] = "Ambient",
-	[AMD_STT_PCB_SENSOR_GPU] = "GPU",
-};
-
-/**
- * Write temperature sensor value to AP via SB-RMI
- *
- * sensor:
- *	AMD_STT_PCB_SENSOR_APU
- *	AMD_STT_PCB_SENSOR_REMOTE
- *	AMD_STT_PCB_SENSOR_GPU
- *
- * temp_mk:
- *	Temperature in degrees milli kelvin
- */
-static int write_stt_sensor_val(enum amd_stt_pcb_sensor sensor, int temp_mk)
-{
-	uint32_t msgIn = 0;
-	uint32_t msgOut;
-	int temp_mc;
-	int temp_c_fp_msb;
-	int temp_c_fp_lsb;
-
-	temp_mc = MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk);
-
-	if (amd_stt_debug)
-		CPRINTS("STT: %s = %d.%d °C", amd_stt_sensor_name[sensor],
-			temp_mc / 1000, temp_mc % 1000);
-
-	/* Divide by 1000 to get MSB of fixed point temp */
-	temp_c_fp_msb = temp_mc / 1000;
-	/* Modulus 1000 and multiply by 256/1000 to get LSB of fixed point*/
-	temp_c_fp_lsb = ((temp_mc % 1000) << 8) / 1000;
-
-	/*
-	 * [15:0]: temperature as signed integer with 8 fractional bits.
-	 * [23:16]: sensor index
-	 * [31:24]: unused
-	 */
-	msgIn |= (temp_c_fp_lsb & 0xff);
-	msgIn |= (temp_c_fp_msb & 0xff) << 8;
-	msgIn |= (sensor & 0xff) << 16;
-	return sb_rmi_mailbox_xfer(SB_RMI_WRITE_STT_SENSOR_CMD, msgIn, &msgOut);
-}
-
-static void amd_stt_handler(void)
-{
-	int rv;
-	int soc_temp_mk;
-	int ambient_temp_mk;
-
-	/* STT interface is only active in S0 */
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return;
-
-	/*
-	 * TODO(b/192391025): Replace with temp_sensor_read_mk(TEMP_SENSOR_SOC)
-	 */
-	rv = board_get_soc_temp_mk(&soc_temp_mk);
-	if (rv) {
-		CPRINTS("STT: Failed to read SOC temp rv:%d", rv);
-		return;
-	}
-
-	rv = write_stt_sensor_val(AMD_STT_PCB_SENSOR_APU, soc_temp_mk);
-	if (rv) {
-		CPRINTS("STT: Failed to write SOC temp rv:%d", rv);
-		return;
-	}
-
-	/*
-	 * TODO(b/192391025): Replace with
-	 *	temp_sensor_read_mk(TEMP_SENSOR_AMBIENT)
-	 */
-	rv = board_get_ambient_temp_mk(&ambient_temp_mk);
-	if (rv) {
-		CPRINTS("STT: Failed to read AMBIENT temp rv:%d", rv);
-		return;
-	}
-
-	rv = write_stt_sensor_val(AMD_STT_PCB_SENSOR_REMOTE, ambient_temp_mk);
-	if (rv) {
-		CPRINTS("STT: Failed to write AMBIENT temp rv:%d", rv);
-		return;
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR+1);
-
-static int command_stt(int argc, char **argv)
-{
-	int sensor_id;
-	int temp;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM1;
-	else if (!strcasecmp(argv[1], "debug")) {
-		amd_stt_debug = !amd_stt_debug;
-		return EC_SUCCESS;
-	} else if (argc != 3)
-		return EC_ERROR_PARAM2;
-	else if (!strcasecmp(argv[1],
-			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_APU]))
-		sensor_id = AMD_STT_PCB_SENSOR_APU;
-	else if (!strcasecmp(argv[1],
-			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_REMOTE]))
-		sensor_id = AMD_STT_PCB_SENSOR_REMOTE;
-	else if (!strcasecmp(argv[1],
-			     amd_stt_sensor_name[AMD_STT_PCB_SENSOR_GPU]))
-		sensor_id = AMD_STT_PCB_SENSOR_GPU;
-	else
-		return EC_ERROR_PARAM2;
-
-	temp = atoi(argv[2]);
-
-	return write_stt_sensor_val(sensor_id, temp);
-}
-DECLARE_CONSOLE_COMMAND(stt, command_stt,
-			"<apu|ambient|gpu|debug> <temp in mK>",
-			"Write an STT mK temperature to AP");
diff --git a/driver/baro_bmp280.c b/driver/baro_bmp280.c
deleted file mode 100644
index 037a77d963..0000000000
--- a/driver/baro_bmp280.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/*
-****************************************************************************
-* Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
-*
-* File : bmp280.h
-*
-* Date : 2015/03/27
-*
-* Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
-*
-* Usage: Sensor Driver for BMP280 sensor
-*
-****************************************************************************
-*
-* \section License
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
-* OR CONTRIBUTORS BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility
-* for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-**************************************************************************/
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/baro_bmp280.h"
-#include "i2c.h"
-#include "timer.h"
-
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-static const uint16_t standby_durn[] = {1, 63, 125, 250, 500, 1000, 2000, 4000};
-
-/*
- * This function is used to get calibration parameters used for
- * calculation in the registers
- *
- *  parameter | Register address |   bit
- *------------|------------------|----------------
- *	dig_T1    |  0x88 and 0x89   | from 0 : 7 to 8: 15
- *	dig_T2    |  0x8A and 0x8B   | from 0 : 7 to 8: 15
- *	dig_T3    |  0x8C and 0x8D   | from 0 : 7 to 8: 15
- *	dig_P1    |  0x8E and 0x8F   | from 0 : 7 to 8: 15
- *	dig_P2    |  0x90 and 0x91   | from 0 : 7 to 8: 15
- *	dig_P3    |  0x92 and 0x93   | from 0 : 7 to 8: 15
- *	dig_P4    |  0x94 and 0x95   | from 0 : 7 to 8: 15
- *	dig_P5    |  0x96 and 0x97   | from 0 : 7 to 8: 15
- *	dig_P6    |  0x98 and 0x99   | from 0 : 7 to 8: 15
- *	dig_P7    |  0x9A and 0x9B   | from 0 : 7 to 8: 15
- *	dig_P8    |  0x9C and 0x9D   | from 0 : 7 to 8: 15
- *	dig_P9    |  0x9E and 0x9F   | from 0 : 7 to 8: 15
- *
- *	@return results of bus communication function
- *	@retval 0 -> Success
- *
- */
-static int bmp280_get_calib_param(const struct motion_sensor_t *s)
-{
-	int ret;
-
-	uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = {0};
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG,
-			a_data_u8, BMP280_CALIB_DATA_SIZE);
-
-	if (ret)
-		return ret;
-
-	/* read calibration values*/
-	data->calib_param.dig_T1 = (a_data_u8[1] << 8) | a_data_u8[0];
-	data->calib_param.dig_T2 = (a_data_u8[3] << 8  | a_data_u8[2]);
-	data->calib_param.dig_T3 = (a_data_u8[5] << 8) | a_data_u8[4];
-
-	data->calib_param.dig_P1 = (a_data_u8[7] << 8) | a_data_u8[6];
-	data->calib_param.dig_P2 = (a_data_u8[9] << 8) | a_data_u8[8];
-	data->calib_param.dig_P3 = (a_data_u8[11] << 8) | a_data_u8[10];
-	data->calib_param.dig_P4 = (a_data_u8[13] << 8) | a_data_u8[12];
-	data->calib_param.dig_P5 = (a_data_u8[15] << 8) | a_data_u8[14];
-	data->calib_param.dig_P6 = (a_data_u8[17] << 8) | a_data_u8[16];
-	data->calib_param.dig_P7 = (a_data_u8[19] << 8) | a_data_u8[18];
-	data->calib_param.dig_P8 = (a_data_u8[21] << 8) | a_data_u8[20];
-	data->calib_param.dig_P9 = (a_data_u8[23] << 8) | a_data_u8[22];
-
-	return EC_SUCCESS;
-}
-
-static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s,
-					int *uncomp_pres)
-{
-	int ret;
-	uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = {0};
-
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_PRESSURE_MSB_REG,
-			a_data_u8, BMP280_PRESSURE_DATA_SIZE);
-
-	if (ret)
-		return ret;
-
-	*uncomp_pres = (int32_t)((a_data_u8[0] << 12) |
-		     (a_data_u8[1] << 4) |
-		     (a_data_u8[2] >> 4));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Reads actual pressure from uncompensated pressure
- * and returns the value in Pascal(Pa)
- * @note Output value of "96386" equals 96386 Pa =
- * 963.86 hPa = 963.86 millibar
- *
- * Algorithm from BMP280 Datasheet Rev 1.15 Section 8.2
- *
- */
-static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
-					int uncomp_pressure)
-{
-	int var1, var2;
-	uint32_t p;
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-
-	/* calculate x1 */
-	var1 = (((int32_t)data->calib_param.t_fine)
-		>> 1) - 64000;
-	/* calculate x2 */
-	var2 = (((var1 >> 2) * (var1 >> 2)) >> 11)
-		* ((int32_t)data->calib_param.dig_P6);
-	var2 = var2 + ((var1 * ((int32_t)data->calib_param.dig_P5)) << 1);
-	var2 = (var2 >> 2) + (((int32_t)data->calib_param.dig_P4) << 16);
-	/* calculate x1 */
-	var1 = (((data->calib_param.dig_P3 *
-		(((var1 >> 2) * (var1 >> 2)) >> 13)) >> 3) +
-		((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >> 18;
-	var1 = ((((32768 + var1)) *
-		((int32_t)data->calib_param.dig_P1)) >> 15);
-
-	/* Avoid exception caused by division by zero */
-	if (!var1)
-		return 0;
-
-	/* calculate pressure */
-	p = (((uint32_t)((1048576) - uncomp_pressure) -
-		(var2 >> 12))) * 3125;
-
-	/* check overflow */
-	if (p < 0x80000000)
-		p = (p << 1) / ((uint32_t)var1);
-	else
-		p = (p / (uint32_t)var1) << 1;
-
-	/* calculate x1 */
-	var1 = (((int32_t)data->calib_param.dig_P9) *
-		((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >> 12;
-	/* calculate x2 */
-	var2 = (((int32_t)(p >> 2)) *
-		((int32_t)data->calib_param.dig_P8)) >> 13;
-	/* calculate true pressure */
-	return (uint32_t)((int32_t)p + ((var1 + var2 +
-		data->calib_param.dig_P7) >> 4));
-}
-
-/*
- * Set the standby duration
- * standby_durn: The standby duration time value.
- *  value     |  standby duration
- *  ----------|--------------------
- *    0x00    | 1_MS
- *    0x01    | 63_MS
- *    0x02    | 125_MS
- *    0x03    | 250_MS
- *    0x04    | 500_MS
- *    0x05    | 1000_MS
- *    0x06    | 2000_MS
- *    0x07    | 4000_MS
- */
-static int bmp280_set_standby_durn(const struct motion_sensor_t *s,
-				uint8_t durn)
-{
-	int ret, val;
-
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CONFIG_REG, &val);
-
-	if (ret == EC_SUCCESS) {
-		val = (val & 0xE0) | ((durn << 5) & 0xE0);
-		/* write the standby duration*/
-		ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			   BMP280_CONFIG_REG, val);
-	}
-
-	return ret;
-}
-
-static int bmp280_set_power_mode(const struct motion_sensor_t *s,
-				uint8_t power_mode)
-{
-	int val;
-
-	val = (BMP280_OVERSAMP_TEMP << 5) +
-		(BMP280_OVERSAMP_PRES << 2) + power_mode;
-
-	return i2c_write8(s->port, s->i2c_spi_addr_flags,
-			  BMP280_CTRL_MEAS_REG, val);
-}
-
-static int bmp280_set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
-{
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-	/*
-	 * ->range contains the number of bit to right shift in order for the
-	 * measurment to fit into 16 bits (or less if the AP wants to).
-	 */
-	data->range = 15 - __builtin_clz(range);
-	s->current_range = 1 << (16 + data->range);
-	return EC_SUCCESS;
-}
-
-/*
- * bmp280_init() - Used to initialize barometer with default config
- *
- * @return results of bus communication function
- * @retval 0 -> Success
- */
-
-static int bmp280_init(struct motion_sensor_t *s)
-{
-	int val, ret;
-
-	if (!s)
-		return EC_ERROR_INVAL;
-
-	/* Read chip id */
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CHIP_ID_REG, &val);
-	if (ret)
-		return ret;
-
-	if (val != BMP280_CHIP_ID)
-		return EC_ERROR_INVAL;
-
-	/* set power mode */
-	ret = bmp280_set_power_mode(s, BMP280_SLEEP_MODE);
-	if (ret)
-		return ret;
-
-	/* Read bmp280 calibration parameter */
-	ret = bmp280_get_calib_param(s);
-	if (ret)
-		return ret;
-
-	return sensor_init_done(s);
-}
-
-static int bmp280_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	int ret, pres;
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-
-	ret = bmp280_read_uncomp_pressure(s, &pres);
-
-	if (ret)
-		return ret;
-
-	v[0] = bmp280_compensate_pressure(s, pres) >> data->range;
-	v[1] = v[2] = 0;
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set data rate, rate in mHz.
- * Calculate the delay (in ms) to apply.
- */
-static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate,
-							int roundup)
-{
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-	int durn, i, ret;
-	int period; /* Period in ms */
-
-	if (rate == 0) {
-		/* Set to sleep mode */
-		data->rate = 0;
-		return bmp280_set_power_mode(s, BMP280_SLEEP_MODE);
-	} else
-		period = 1000000 / rate;
-
-	/* reset power mode, waking from sleep */
-	if (!data->rate) {
-		ret = bmp280_set_power_mode(s, BMP280_NORMAL_MODE);
-		if (ret)
-			return ret;
-	}
-
-	durn = 0;
-	for (i = BMP280_STANDBY_CNT-1;  i > 0; i--) {
-		if (period >= standby_durn[i] + BMP280_COMPUTE_TIME) {
-			durn = i;
-			break;
-		} else if (period > standby_durn[i-1] + BMP280_COMPUTE_TIME) {
-			durn = roundup ? i-1 : i;
-			break;
-		}
-	}
-	ret = bmp280_set_standby_durn(s, durn);
-	if (ret == EC_SUCCESS)
-		/*
-		 * The maximum frequency is around 76Hz. Be sure it fits in 16
-		 * bits by shifting by one bit.
-		 */
-		data->rate = (1000000 >> BMP280_RATE_SHIFT) /
-			     (standby_durn[durn] + BMP280_COMPUTE_TIME);
-	return ret;
-}
-
-static int bmp280_get_data_rate(const struct motion_sensor_t *s)
-{
-	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
-
-	return data->rate << BMP280_RATE_SHIFT;
-}
-
-const struct accelgyro_drv bmp280_drv = {
-	.init = bmp280_init,
-	.read = bmp280_read,
-	.set_range = bmp280_set_range,
-	.set_data_rate = bmp280_set_data_rate,
-	.get_data_rate = bmp280_get_data_rate,
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-struct i2c_stress_test_dev bmp280_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = BMP280_CHIP_ID_REG,
-		.read_val = BMP280_CHIP_ID,
-		.write_reg = BMP280_CONFIG_REG,
-	},
-	.i2c_read = &i2c_read8,
-	.i2c_write = &i2c_write8,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_ACCEL */
diff --git a/driver/baro_bmp280.h b/driver/baro_bmp280.h
deleted file mode 100644
index ee95bd886f..0000000000
--- a/driver/baro_bmp280.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/** \mainpage
-*
-****************************************************************************
-* Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
-*
-* File : bmp280.h
-*
-* Date : 2015/03/27
-*
-* Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
-*
-* Usage: Sensor Driver for BMP280 sensor
-*
-****************************************************************************
-*
-* \section License
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
-* OR CONTRIBUTORS BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility
-* for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-**************************************************************************/
-/* BMP280 pressure and temperature module for Chrome EC */
-
-#ifndef __CROS_EC_BARO_BMP280_H
-#define __CROS_EC_BARO_BMP280_H
-
-/*
- * The addr field of barometer_sensor for I2C:
- *
- * +-------------------------------+---+
- * |    7 bit i2c address          | 0 |
- * +-------------------------------+---+
- */
-
-/*
- * Bit 1 of 7-bit address: 0 - If SDO is connected to GND
- * Bit 1 of 7-bit address: 1 - If SDO is connected to Vddio
- */
-#define BMP280_I2C_ADDRESS1_FLAGS	0x76
-#define BMP280_I2C_ADDRESS2_FLAGS	0x77
-
-/*
- *     CHIP ID
- */
-#define BMP280_CHIP_ID			0x58
-/************************************************/
-/*	CALIBRATION PARAMETERS DEFINITION       */
-/************************************************/
-
-#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG	0x88
-
-/************************************************/
-/*	REGISTER ADDRESS DEFINITION             */
-/************************************************/
-#define BMP280_CHIP_ID_REG		     0xD0
-#define BMP280_RST_REG                       0xE0  /*Softreset Register */
-#define BMP280_STAT_REG                      0xF3  /*Status Register */
-#define BMP280_CTRL_MEAS_REG                 0xF4  /*Ctrl Measure Register */
-#define BMP280_CONFIG_REG                    0xF5  /*Configuration Register */
-#define BMP280_PRESSURE_MSB_REG              0xF7  /*Pressure MSB Register */
-#define BMP280_PRESSURE_LSB_REG              0xF8  /*Pressure LSB Register */
-#define BMP280_PRESSURE_XLSB_REG             0xF9  /*Pressure XLSB Register */
-/************************************************/
-/*	POWER MODE DEFINITION                   */
-/************************************************/
-/* Sensor Specific constants */
-#define BMP280_SLEEP_MODE                    0x00
-#define BMP280_FORCED_MODE                   0x01
-#define BMP280_NORMAL_MODE                   0x03
-#define BMP280_SOFT_RESET_CODE               0xB6
-/************************************************/
-/*	STANDBY TIME DEFINITION                 */
-/************************************************/
-#define BMP280_STANDBY_TIME_1_MS              0x00
-#define BMP280_STANDBY_TIME_63_MS             0x01
-#define BMP280_STANDBY_TIME_125_MS            0x02
-#define BMP280_STANDBY_TIME_250_MS            0x03
-#define BMP280_STANDBY_TIME_500_MS            0x04
-#define BMP280_STANDBY_TIME_1000_MS           0x05
-#define BMP280_STANDBY_TIME_2000_MS           0x06
-#define BMP280_STANDBY_TIME_4000_MS           0x07
-/************************************************/
-/*	OVERSAMPLING DEFINITION                 */
-/************************************************/
-#define BMP280_OVERSAMP_SKIPPED          0x00
-#define BMP280_OVERSAMP_1X               0x01
-#define BMP280_OVERSAMP_2X               0x02
-#define BMP280_OVERSAMP_4X               0x03
-#define BMP280_OVERSAMP_8X               0x04
-#define BMP280_OVERSAMP_16X              0x05
-/************************************************/
-/*	DEFINITIONS FOR ARRAY SIZE OF DATA      */
-/************************************************/
-#define	BMP280_PRESSURE_DATA_SIZE	3
-#define	BMP280_DATA_FRAME_SIZE		6
-#define	BMP280_CALIB_DATA_SIZE		24
-/*******************************************************/
-/*         SAMPLING PERIOD COMPUTATION CONSTANT	       */
-/*******************************************************/
-#define BMP280_STANDBY_CNT		8
-#define T_INIT_MAX			(20) /* (20/16 = 1.25ms) */
-#define T_MEASURE_PER_OSRS_MAX		(37) /* (37/16 = 2.31ms) */
-#define T_SETUP_PRESSURE_MAX		(10) /* (10/16 = 0.62ms) */
-
-/*
- * This is the measurement time required for pressure and temp
- */
-#define BMP280_COMPUTE_TIME \
-	((T_INIT_MAX + T_MEASURE_PER_OSRS_MAX * \
-	  ((BIT(BMP280_OVERSAMP_TEMP) >> 1) + \
-	   (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \
-	  (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) / 16)
-
-/*
- * These values are selected as per Bosch recommendation for
- * standard handheld devices, with temp sensor not being used
- */
-#define BMP280_OVERSAMP_PRES BMP280_OVERSAMP_4X
-#define BMP280_OVERSAMP_TEMP BMP280_OVERSAMP_SKIPPED
-/*******************************************************/
-/*             GET DRIVER DATA			       */
-/*******************************************************/
-#define BMP280_GET_DATA(_s) \
-	((struct bmp280_drv_data_t *)(_s)->drv_data)
-
-/* Min and Max sampling frequency in mHz based on x4 oversampling used */
-/* FIXME - verify how chip is setup to make sure MAX is correct, manual says
- * "Typical", not Max.
- */
-#define BMP280_BARO_MIN_FREQ  75000
-#define BMP280_BARO_MAX_FREQ  87000
-#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= BMP280_BARO_MAX_FREQ)
-#error "EC too slow for accelerometer"
-#endif
-
-/**************************************************************/
-/*	STRUCTURE and ENUM DEFINITIONS                        */
-/**************************************************************/
-
-/*
- * struct bmp280_calib_param_t - Holds all device specific
- *                                calibration parameters
- *
- * @dig_T1 to dig_T3:   calibration Temp data
- * @dig_P1 to dig_P9:   calibration Pressure data
- * @t_fine:   calibration t_fine data
- *
- */
-struct bmp280_calib_param_t {
-	uint16_t dig_T1;
-	int16_t dig_T2;
-	int16_t dig_T3;
-	uint16_t dig_P1;
-	int16_t dig_P2;
-	int16_t dig_P3;
-	int16_t dig_P4;
-	int16_t dig_P5;
-	int16_t dig_P6;
-	int16_t dig_P7;
-	int16_t dig_P8;
-	int16_t dig_P9;
-
-	int32_t t_fine;
-};
-
-/*
- * struct bmp280_t - This structure holds BMP280 initialization parameters
- * @calib_param:          calibration data
- * @rate:     frequency, in mHz.
- * @range:		bit offset to fit data in 16 bit or less.
- */
-struct bmp280_drv_data_t {
-
-	struct   bmp280_calib_param_t calib_param;
-	uint16_t rate;
-	uint16_t range;
-};
-#define BMP280_RATE_SHIFT 1
-
-extern const struct accelgyro_drv bmp280_drv;
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev bmp280_i2c_stress_test_dev;
-#endif
-
-#endif
diff --git a/driver/battery/bq20z453.c b/driver/battery/bq20z453.c
deleted file mode 100644
index 3cd16e8b8f..0000000000
--- a/driver/battery/bq20z453.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery driver for BQ20Z453.
- */
-
-#include "battery_smart.h"
-#include "hooks.h"
-#include "host_command.h"
-
-#define PARAM_CUT_OFF 0x0010
-
-static void cutoff(void)
-{
-	/* Claim i2c and send cutoff command to battery. */
-	sb_write(SB_MANUFACTURER_ACCESS, PARAM_CUT_OFF);
-}
-DECLARE_DEFERRED(cutoff);
-
-enum ec_status battery_command_cut_off(struct host_cmd_handler_args *args)
-{
-	/*
-	 * Queue battery cutoff.  This must be deferred so we can send the
-	 * response to the host first.  Some platforms (snow) share an I2C bus
-	 * between the EC, AP, and battery, so we need the host to complete the
-	 * transaction and release the I2C bus before we'll be abl eto send the
-	 * cutoff command.
-	 */
-	hook_call_deferred(&cutoff_data, 1000);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_CUT_OFF, battery_command_cut_off,
-		     EC_VER_MASK(0));
diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c
deleted file mode 100644
index b39147092f..0000000000
--- a/driver/battery/bq27541.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for BQ27541/BQ27542/BQ27741/BQ27742.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "console.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-
-#define BQ27541_ADDR_FLAGS          0x55
-#define BQ27541_TYPE_ID             0x0541
-#define BQ27542_TYPE_ID             0x0542
-#define BQ27741_TYPE_ID             0x0741
-#define BQ27742_TYPE_ID             0x0742
-
-#define REG_CTRL                    0x00
-#define REG_AT_RATE                 0x02
-#define REG_AT_RATE_TIME_TO_EMPTY   0x04
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_NOMINAL_CAPACITY        0x0c
-#define REG_FULL_AVAILABLE_CAPACITY 0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_FULL_CHARGE_CAPACITY    0x12
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_TIME_TO_EMPTY           0x16
-#define REG_TIME_TO_FULL            0x18
-#define REG_STANDBY_CURRENT         0x1a
-#define REG_STANDBY_TIME_TO_EMPTY   0x1c
-#define REG_MAX_LOAD_CURRENT        0x1e
-#define REG_MAX_LOAD_TIME_TO_EMPTY  0x20
-#define REG_AVAILABLE_ENERGY        0x22
-#define REG_AVERAGE_POEWR           0x24
-#define REG_TT_EAT_CONSTANT_POWER   0x26
-#define REG_CYCLE_COUNT             0x2a
-#define REG_STATE_OF_CHARGE         0x2c
-#define	REG_DATA_FLASH_BLOCK	    0x3f
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_MANUFACTURER_INFO	    0x52
-#define REG_DEVICE_NAME_LENGTH      0x62
-#define MAX_DEVICE_NAME_LENGTH      7
-#define REG_DEVICE_NAME             0x63
-#define REG_PROTECTOR               0x6d
-
-/* Over-charge */
-#define BQ27542_FLAG_BATHI           BIT(13)
-/* Over Temperature in discharge */
-#define BQ27542_FLAG_OTD             BIT(11)
-/* Over Temperature in charge */
-#define BQ27542_FLAG_OTC             BIT(7)
-/* Charge allowed */
-#define BQ27542_FLAG_CHG             BIT(3)
-/* Discharge */
-#define BQ27542_FLAG_DSG             BIT(0)
-
-static int battery_type_id;
-static int fake_state_of_charge = -1;
-
-static int bq27541_read(int offset, int *data)
-{
-	return i2c_read16(I2C_PORT_BATTERY, BQ27541_ADDR, offset, data);
-}
-
-static int bq27541_read8(int offset, int *data)
-{
-	return i2c_read8(I2C_PORT_BATTERY, BQ27541_ADDR, offset, data);
-}
-
-static int bq27541_write(int offset, int data)
-{
-	return i2c_write16(I2C_PORT_BATTERY, BQ27541_ADDR, offset, data);
-}
-
-int bq27541_probe(void)
-{
-	int rv;
-
-	rv = bq27541_write(REG_CTRL, 0x1);
-	rv |= bq27541_read(REG_CTRL, &battery_type_id);
-	/* Read twice to get the right value */
-	rv |= bq27541_read(REG_CTRL, &battery_type_id);
-	if (rv)
-		return rv;
-	if (battery_type_id == BQ27541_TYPE_ID ||
-	    battery_type_id == BQ27542_TYPE_ID ||
-	    battery_type_id == BQ27741_TYPE_ID ||
-	    battery_type_id == BQ27742_TYPE_ID)
-		return EC_SUCCESS;
-	return EC_ERROR_UNKNOWN;
-}
-
-static void probe_type_id(void)
-{
-	bq27541_probe();
-}
-DECLARE_HOOK(HOOK_INIT, probe_type_id, HOOK_PRIO_DEFAULT);
-
-int battery_device_name(char *device_name, int buf_size)
-{
-	int rv, i, val;
-	int len = MIN(7, buf_size - 1);
-
-	if (battery_type_id == BQ27742_TYPE_ID) {
-		/* No device name register available */
-		strzcpy(device_name, "<BATT>", len);
-		return 0;
-	}
-	/* Battery pack vendor specific */
-	if (battery_type_id == BQ27542_TYPE_ID) {
-		rv = bq27541_write(REG_DATA_FLASH_BLOCK, 0x1);
-		for (i = 0; i < len; ++i) {
-			rv |= bq27541_read8(REG_MANUFACTURER_INFO + i, &val);
-			device_name[i] = val;
-		}
-		device_name[i] = '\0';
-		return rv;
-	}
-
-	rv = bq27541_read8(REG_DEVICE_NAME_LENGTH, &val);
-	if (rv)
-		return rv;
-	len = MIN(len, val);
-
-	for (i = 0; i < len; ++i) {
-		rv |= bq27541_read8(REG_DEVICE_NAME + i, &val);
-		device_name[i] = val;
-	}
-	device_name[i] = '\0';
-
-	return rv;
-}
-
-int battery_state_of_charge_abs(int *percent)
-{
-	return bq27541_read(REG_STATE_OF_CHARGE, percent);
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	return bq27541_read(REG_REMAINING_CAPACITY, capacity);
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	return bq27541_read(REG_FULL_CHARGE_CAPACITY, capacity);
-}
-
-int battery_time_to_empty(int *minutes)
-{
-	return bq27541_read(REG_TIME_TO_EMPTY, minutes);
-}
-
-int battery_time_to_full(int *minutes)
-{
-	return bq27541_read(REG_TIME_TO_FULL, minutes);
-}
-
-int battery_cycle_count(int *count)
-{
-	return bq27541_read(REG_CYCLE_COUNT, count);
-}
-
-int battery_design_capacity(int *capacity)
-{
-	return bq27541_read(REG_DESIGN_CAPACITY, capacity);
-}
-
-int battery_time_at_rate(int rate, int *minutes)
-{
-	int rv;
-
-	if (battery_type_id == BQ27542_TYPE_ID)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	rv = bq27541_write(REG_AT_RATE, rate);
-	if (rv)
-		return rv;
-	return bq27541_read(REG_AT_RATE_TIME_TO_EMPTY, minutes);
-}
-
-int battery_device_chemistry(char *dest, int size)
-{
-	strzcpy(dest, "<unkn>", size);
-
-	return EC_SUCCESS;
-}
-
-int battery_serial_number(int *serial)
-{
-	*serial = 0x0BAD0BAD;
-
-	return EC_SUCCESS;
-}
-
-int battery_manufacture_date(int *year, int *month, int *day)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = battery_get_info()->voltage_normal;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Check if battery allows charging.
- *
- * @param allowed	Non-zero if charging allowed; zero if not allowed.
- * @return non-zero if error.
- */
-static int battery_charging_allowed(int *allowed)
-{
-	int rv, val;
-
-	rv = bq27541_read(REG_FLAGS, &val);
-	if (rv)
-		return rv;
-	if (battery_type_id == BQ27541_TYPE_ID ||
-	    battery_type_id == BQ27741_TYPE_ID)
-		*allowed = (val & 0x100);
-	else /* BQ27742_TYPE_ID, BQ27542_TYPE_ID */
-		*allowed = (val & 0x8);
-
-	return EC_SUCCESS;
-}
-
-int battery_get_mode(int *mode)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_status(int *status)
-{
-	int rv;
-	int flag = 0;
-
-	*status = 0;
-	if (battery_type_id == BQ27542_TYPE_ID) {
-		rv = bq27541_read(REG_FLAGS, &flag);
-		if (rv)
-			return rv;
-
-		if (flag & (BQ27542_FLAG_OTC | BQ27542_FLAG_OTD))
-			*status |= STATUS_OVERTEMP_ALARM;
-		if (flag & BQ27542_FLAG_DSG)
-			*status |= STATUS_DISCHARGING;
-		if (flag & BQ27542_FLAG_BATHI)
-			*status |= STATUS_OVERCHARGED_ALARM;
-
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum battery_present battery_is_present(void)
-{
-	int v;
-	if (bq27541_read(REG_TEMPERATURE, &v))
-		return BP_NO;
-	return BP_YES;
-}
-
-void battery_get_params(struct batt_params *batt)
-{
-	int v;
-	const uint32_t flags_to_check = BATT_FLAG_BAD_TEMPERATURE |
-					BATT_FLAG_BAD_STATE_OF_CHARGE |
-					BATT_FLAG_BAD_VOLTAGE |
-					BATT_FLAG_BAD_CURRENT;
-
-	/* Reset flags */
-	batt->flags = 0;
-
-	if (bq27541_read(REG_TEMPERATURE, &batt->temperature))
-		batt->flags |= BATT_FLAG_BAD_TEMPERATURE;
-
-	if (bq27541_read8(REG_STATE_OF_CHARGE, &v) && fake_state_of_charge < 0)
-		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-
-	batt->state_of_charge = fake_state_of_charge >= 0 ?
-					fake_state_of_charge : v;
-
-	if (bq27541_read(REG_VOLTAGE, &batt->voltage))
-		batt->flags |= BATT_FLAG_BAD_VOLTAGE;
-
-	v = 0;
-	if (bq27541_read(REG_AVERAGE_CURRENT, &v))
-		batt->flags |= BATT_FLAG_BAD_CURRENT;
-	batt->current = (int16_t)v;
-
-	if (battery_remaining_capacity(&batt->remaining_capacity))
-		batt->flags |= BATT_FLAG_BAD_REMAINING_CAPACITY;
-
-	if (battery_full_charge_capacity(&batt->full_capacity))
-		batt->flags |= BATT_FLAG_BAD_FULL_CAPACITY;
-
-	/* Default to not desiring voltage and current */
-	batt->desired_voltage = batt->desired_current = 0;
-
-	/* If any of those reads worked, the battery is responsive */
-	if ((batt->flags & flags_to_check) != flags_to_check) {
-		batt->flags |= BATT_FLAG_RESPONSIVE;
-		batt->is_present = BP_YES;
-	} else {
-
-	/* If all of those reads error, the battery is not present */
-		batt->is_present = BP_NO;
-	}
-
-	/* update the battery status */
-	if (battery_status(&batt->status))
-		batt->flags |= BATT_FLAG_BAD_STATUS;
-
-	v = 0;
-	if (battery_charging_allowed(&v)) {
-		batt->flags |= BATT_FLAG_BAD_ANY;
-	} else if (v) {
-		batt->flags |= BATT_FLAG_WANT_CHARGE;
-
-		/*
-		 * Desired voltage and current are not provided by the battery.
-		 * So ask for battery's max voltage and an arbitrarily large
-		 * current.
-		 */
-		batt->desired_voltage = battery_get_info()->voltage_max;
-		batt->desired_current = 4096;
-	}
-}
-
-/* Wait until battery is totally stable */
-int battery_wait_for_stable(void)
-{
-	/* TODO(crosbug.com/p/30426): implement me */
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-/*
- * Check if battery is in disconnect state, a state entered by pulling
- * BATT_DISCONN_N low, and clear that state if we have external power plugged
- * and no battery faults are detected. Disconnect state resembles battery
- * shutdown mode, but extra steps must be taken to get the battery out of this
- * mode.
- */
-enum battery_disconnect_state battery_get_disconnect_state(void)
-{
-	int val, rv;
-	/*
-	 * Take note if we find that the battery isn't in disconnect state,
-	 * and always return NOT_DISCONNECTED without probing the battery.
-	 * This assumes the battery will not go to disconnect state during
-	 * runtime.
-	 */
-	static int not_disconnected;
-
-	if (not_disconnected)
-		return BATTERY_NOT_DISCONNECTED;
-
-	if (extpower_is_present()) {
-		/* Check DSG_OFF bit */
-		rv = bq27541_read(REG_PROTECTOR, &val);
-		if (rv)
-			return BATTERY_DISCONNECT_ERROR;
-		if (!(val & BIT(6))) {
-			not_disconnected = 1;
-			return BATTERY_NOT_DISCONNECTED;
-		}
-
-		/* DSG_OFF is set. Verify this is not due to a safety fault */
-		if (val & 0x3f)
-			return BATTERY_DISCONNECT_ERROR;
-		rv = bq27541_read(REG_FLAGS, &val);
-		if (rv)
-			return BATTERY_DISCONNECT_ERROR;
-		if (val & 0xfc60)
-			return BATTERY_DISCONNECT_ERROR;
-		return BATTERY_DISCONNECTED;
-	}
-	not_disconnected = 1;
-	return BATTERY_NOT_DISCONNECTED;
-}
-#endif /* CONFIG_BATTERY_REVIVE_DISCONNECT */
-
-static int command_battfake(int argc, char **argv)
-{
-	char *e;
-	int v;
-
-	if (argc == 2) {
-		v = strtoi(argv[1], &e, 0);
-		if (*e || v < -1 || v > 100)
-			return EC_ERROR_PARAM1;
-
-		fake_state_of_charge = v;
-	}
-
-	if (fake_state_of_charge >= 0)
-		ccprintf("Fake batt %d%%\n",
-			 fake_state_of_charge);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(battfake, command_battfake,
-			"percent (-1 = use real level)",
-			"Set fake battery level");
-
-#ifdef CONFIG_CMD_PWR_AVG
-int battery_get_avg_current(void)
-{
-	int current = -EC_ERROR_UNKNOWN;
-
-	bq27541_read(REG_AVERAGE_CURRENT, &current);
-	return current;
-}
-
-int battery_get_avg_voltage(void)
-{
-	/* BQ27541 does not have this parameter */
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-#endif /* CONFIG_CMD_PWR_AVG */
-
diff --git a/driver/battery/bq27621_g1.c b/driver/battery/bq27621_g1.c
deleted file mode 100644
index dbda6f9c65..0000000000
--- a/driver/battery/bq27621_g1.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for BQ27621-G1
- */
-
-#include "battery.h"
-#include "console.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-#include "timer.h"
-
-#define BQ27621_ADDR_FLAGS                  0x55
-#define BQ27621_TYPE_ID                     0x0621
-
-#define REG_CTRL                            0x00
-#define REG_TEMPERATURE                     0x02
-#define REG_VOLTAGE                         0x04
-#define REG_FLAGS                           0x06
-#define REG_NOMINAL_CAPACITY                0x08
-#define REG_FULL_AVAILABLE_CAPACITY         0x0a
-#define REG_REMAINING_CAPACITY              0x0c
-#define REG_FULL_CHARGE_CAPACITY            0x0e
-#define REG_EFFECTIVE_CURRENT               0x10
-#define REG_AVERAGE_POWER                   0x18
-#define REG_STATE_OF_CHARGE                 0x1c
-#define REG_INTERNAL_TEMPERATURE            0x1e
-#define REG_REMAINING_CAPACITY_UNFILTERED   0x28
-#define REG_REMAINING_CAPACITY_FILTERED     0x2a
-#define REG_FULL_CHARGE_CAPACITY_UNFILTERED 0x28
-#define REG_FULL_CHARGE_CAPACITY_FILTERED   0x2a
-#define REG_STATE_OF_CHARGE_UNFILTERED      0x30
-#define REG_OP_CONFIG                       0x3a
-#define REG_DESIGN_CAPACITY                 0x3c
-#define REG_DATA_CLASS                      0x3e
-#define REG_DATA_BLOCK                      0x3f
-#define REG_BLOCK_DATA_CHECKSUM             0x60
-#define REG_BLOCK_DATA_CONTROL              0x61
-
-#define REGISTERS_BLOCK_OFFSET                64
-#define REGISTERS_BLOCK_OP_CONFIG           0x40
-#define REGISTERS_BLOCK_OP_CONFIG_B         0x42
-#define REGISTERS_BLOCK_DF_VERSION          0x43
-
-/* State block */
-#define STATE_BLOCK_OFFSET                    82
-#define STATE_BLOCK_DESIGN_CAPACITY         0x43
-#define STATE_BLOCK_DESIGN_ENERGY           0x45
-#define STATE_BLOCK_TERMINATE_VOLTAGE       0x49
-#define STATE_BLOCK_TAPER_RATE              0x54
-
-/* BQ27621 Control subcommands */
-#define CONTROL_CONTROL_STATUS   0x00
-#define CONTROL_DEVICE_TYPE      0x01
-#define CONTROL_FW_VERSION       0x02
-#define CONTROL_PREV_MACWRITE    0x07
-#define CONTROL_CHEM_ID          0x08
-#define CONTROL_BAT_INSERT       0x0C
-#define CONTROL_BAT_REMOVE       0x0D
-#define CONTROL_TOGGLE_POWERMIN  0x10
-#define CONTROL_SET_HIBERNATE    0x11
-#define CONTROL_CLEAR_HIBERNATE  0x12
-#define CONTROL_SET_CFGUPDATE    0x13
-#define CONTROL_SHUTDOWN_ENABLE  0x1B
-#define CONTROL_SHUTDOWN         0x1C
-#define CONTROL_SEALED           0x20
-#define CONTROL_TOGGLE_GPOUT     0x23
-#define CONTROL_ALT_CHEM1        0x31
-#define CONTROL_ALT_CHEM2        0x32
-#define CONTROL_RESET            0x41
-#define CONTROL_SOFT_RESET       0x42
-#define CONTROL_EXIT_CFGUPDATE   0x43
-#define CONTROL_EXIT_RESIM       0x44
-#define CONTROL_UNSEAL           0x8000
-
-/* BQ27621 Status bits */
-#define STATUS_SHUTDOWNEN        0x8000
-#define STATUS_WDRESET           0x4000
-#define STATUS_SS                0x2000
-#define STATUS_CALMODE           0x1000
-#define STATUS_OCVCMDCOMP        0x0200
-#define STATUS_OCVFAIL           0x0100
-#define STATUS_INITCOMP          0x0080
-#define STATUS_HIBERNATE         0x0040
-#define STATUS_POWERMIN          0x0020
-#define STATUS_SLEEP             0x0010
-#define STATUS_LDMD              0x0008
-#define STATUS_CHEMCHNG          0x0001
-
-/* BQ27621 Flags bits */
-#define FLAGS_OT                 0x8000
-#define FLAGS_UT                 0x4000
-#define FLAGS_FC                 0x0200
-#define FLAGS_CHG                0x0100
-#define FLAGS_OCVTAKEN           0x0080
-#define FLAGS_ITPOR              0x0020
-#define FLAGS_CFGUPD             0x0010
-#define FLAGS_BAT_DET            0x0008
-#define FLAGS_SOC1               0x0004
-#define FLAGS_SOCF               0x0002
-#define FLAGS_DSG                0x0001
-
-/*
- * There are some parameters that need to be defined in the board file:
- * BQ27621_TOGGLE_POWER_MIN -  Put it in minimum power mode
- *    (may affect I2C timing)
- * BQ27621_DESIGN_CAPACITY -   mAh
- * BQ27621_DESIGN_ENERGY -     Design Capacity x 3.7
- * BQ27621_TERMINATE_VOLTAGE - mV
- * BQ27621_TAPER_CURRENT -     mA
- * BQ27621_CHEM_ID -           0x1202 (DEFAULT) 0x1210 (ALT_CHEM1)
- *                             0x354 (ALT_CHEM2)
- *
- * For extra large or extra small batteries, this driver scales everything but
- * voltages.  The recommended range is 150mAh - 6Ah
- *
- */
-
-#define BQ27621_SCALE_FACTOR (BQ27621_DESIGN_CAPACITY < 150 ? 10.0 : \
-				(BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1))
-
-#define BQ27621_UNSCALE(x)   (BQ27621_SCALE_FACTOR == 10 ? (x) / 10 : \
-				(BQ27621_SCALE_FACTOR == 0.1 ? (x) * 10 : (x)))
-
-#define BQ27621_TAPER_RATE  ((int)(BQ27621_DESIGN_CAPACITY/    \
-				(0.1 * BQ27621_TAPER_CURRENT)))
-
-#define BQ27621_SCALED_DESIGN_CAPACITY ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
-#define BQ27621_SCALED_DESIGN_ENERGY   ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
-
-/*
- *Everything is LSB first.  Parameters need to be converted.
- *
- * The values from the data sheet are already LSB-first.
- */
-
-#define ENDIAN_SWAP_2B(x)     ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
-#define DESIGN_CAPACITY       ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY)
-#define DESIGN_ENERGY         ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY)
-#define TAPER_RATE            ENDIAN_SWAP_2B(BQ27621_TAPER_RATE)
-#define TERMINATE_VOLTAGE     ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE)
-
-struct battery_info battery_params;
-
-static int bq27621_read(int offset, int *data)
-{
-	return i2c_read16(I2C_PORT_BATTERY, BQ27621_ADDR, offset, data);
-}
-
-static int bq27621_read8(int offset, int *data)
-{
-	return i2c_read8(I2C_PORT_BATTERY, BQ27621_ADDR, offset, data);
-}
-
-static int bq27621_write(int offset, int data)
-{
-	return i2c_write16(I2C_PORT_BATTERY, BQ27621_ADDR, offset, data);
-}
-
-static int bq27621_write8(int offset, int data)
-{
-	return i2c_write8(I2C_PORT_BATTERY, BQ27621_ADDR, offset, data);
-}
-
-static int bq27621_probe(void)
-{
-	int rv;
-	int battery_type_id;
-
-	/* Delays need to be added for correct operation at > 100Kbps */
-	ASSERT(i2c_ports[I2C_PORT_BATTERY].kbps <= 100);
-
-	rv = bq27621_write(REG_CTRL, CONTROL_DEVICE_TYPE);
-	rv |= bq27621_read(REG_CTRL, &battery_type_id);
-
-	if (rv)
-		return rv;
-	if (battery_type_id == BQ27621_TYPE_ID) {
-		battery_params.voltage_max = BATTERY_VOLTAGE_MAX;
-		battery_params.voltage_normal = BATTERY_VOLTAGE_NORMAL;
-		battery_params.voltage_min = BATTERY_VOLTAGE_MIN;
-		return EC_SUCCESS;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-static inline int bq27621_unseal(void)
-{
-	return bq27621_write(REG_CTRL, CONTROL_UNSEAL) |
-				bq27621_write(REG_CTRL, CONTROL_UNSEAL);
-}
-
-static int bq27621_enter_config_update(void)
-{
-	int tries, flags = 0, rv = EC_SUCCESS;
-
-	/* Enter Config Update Mode (Can take up to a second) */
-	for (tries = 2000; tries > 0 && !(flags & FLAGS_CFGUPD) &&
-					(rv == EC_SUCCESS); tries--) {
-		rv |= bq27621_write(REG_CTRL, CONTROL_SET_CFGUPDATE);
-		rv |= bq27621_read(REG_FLAGS, &flags);
-	}
-
-	if (tries == 0)
-		return EC_ERROR_TIMEOUT;
-	else
-		return EC_SUCCESS;
-}
-
-static int bq27621_enter_block_mode(int block)
-{
-	int rv;
-	rv = bq27621_write8(REG_BLOCK_DATA_CONTROL, 0);
-	rv |= bq27621_write8(REG_DATA_CLASS, block);
-	rv |= bq27621_write8(REG_DATA_BLOCK, 0);
-	udelay(500); /* Shouldn't be needed, doesn't work without it. */
-	return rv;
-}
-
-static int bq27621_seal(void)
-{
-	int rv = 0;
-	int status = 0, param = 0, checksum = 0;
-
-	rv |= bq27621_write(REG_CTRL, CONTROL_CONTROL_STATUS);
-	rv |= bq27621_read(REG_CTRL, &status);
-
-	if (status & STATUS_SS) /* Already sealed */
-		return EC_SUCCESS;
-
-	/* Enter Config Update Mode */
-	rv = bq27621_enter_config_update();
-
-	if (rv)
-		return rv;
-
-	/* Set up block RAM update */
-	rv = bq27621_enter_block_mode(REGISTERS_BLOCK_OFFSET);
-
-	if (rv)
-		return rv;
-
-	rv = bq27621_read8(REG_BLOCK_DATA_CHECKSUM, &checksum);
-
-	if (rv)
-		return rv;
-
-	checksum = 0xff - checksum;
-
-	rv = bq27621_read8(REGISTERS_BLOCK_OP_CONFIG_B, &param);
-	checksum -= param; /* 1B */
-
-	param |= 1<<5; /* Set DEF_SEAL */
-
-	rv = bq27621_write8(REGISTERS_BLOCK_OP_CONFIG_B, param);
-	checksum += param; /* 1B */
-
-	checksum = 0xff - (0xff & checksum);
-
-	rv = bq27621_write8(REG_BLOCK_DATA_CHECKSUM, checksum);
-
-	if (rv)
-		return rv;
-
-	/* Exit Update */
-	rv = bq27621_write(REG_CTRL, CONTROL_SOFT_RESET);
-
-	return rv;
-}
-
-#define CHECKSUM_2B(x) ((x & 0xff) + ((x>>8) & 0xff))
-
-static int bq27621_init(void)
-{
-	int rv;
-	int status = 0, param = 0, checksum = 0;
-
-	rv = bq27621_probe();
-
-	if (rv)
-		return rv;
-
-	/* Unseal the device if necessary */
-	rv |= bq27621_write(REG_CTRL, CONTROL_CONTROL_STATUS);
-	rv |= bq27621_read(REG_CTRL, &status);
-
-	if (status & STATUS_SS)
-		rv |= bq27621_unseal();
-
-	if (rv)
-		return rv;
-
-	/* Select the alternate chemistry if needed */
-	rv = bq27621_write(REG_CTRL, CONTROL_CHEM_ID);
-	rv |= bq27621_read(REG_CTRL, &param);
-
-	if (param != BQ27621_CHEM_ID) { /* Change needed */
-
-		if (BQ27621_CHEM_ID == 0x1202) { /* Return to default */
-			rv |= bq27621_write(REG_CTRL, CONTROL_RESET);
-		} else {
-			rv |= bq27621_enter_config_update();
-
-			if (BQ27621_CHEM_ID == 0x1210)
-				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM1);
-			if (BQ27621_CHEM_ID == 0x0354)
-				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM2);
-
-		/*
-		 * The datasheet recommends checking the status here.
-		 *
-		 * If the CHEMCHG is active, it wasn't successful.
-		 *
-		 * There's no recommendation for what to do if it isn't.
-		 */
-
-			rv |= bq27621_write(REG_CTRL, CONTROL_EXIT_CFGUPDATE);
-		}
-	}
-
-	if (rv)
-		return rv;
-
-	rv = bq27621_enter_config_update();
-
-	if (rv)
-		return rv;
-
-	/* Set up block RAM update */
-	rv = bq27621_enter_block_mode(STATE_BLOCK_OFFSET);
-
-	if (rv)
-		return rv;
-
-	rv = bq27621_read8(REG_BLOCK_DATA_CHECKSUM, &checksum);
-	if (rv)
-		return rv;
-
-	checksum = 0xff - checksum;
-
-	rv = bq27621_read(STATE_BLOCK_DESIGN_CAPACITY, &param);
-	checksum -= CHECKSUM_2B(param);
-
-	rv |= bq27621_read(STATE_BLOCK_DESIGN_ENERGY, &param);
-	checksum -= CHECKSUM_2B(param);
-
-	rv |= bq27621_read(STATE_BLOCK_TERMINATE_VOLTAGE, &param);
-	checksum -= CHECKSUM_2B(param);
-
-	rv |= bq27621_read(STATE_BLOCK_TAPER_RATE, &param);
-	checksum -= CHECKSUM_2B(param);
-
-	if (rv)
-		return rv;
-
-	rv = bq27621_write(STATE_BLOCK_DESIGN_CAPACITY, DESIGN_CAPACITY);
-	checksum += CHECKSUM_2B(DESIGN_CAPACITY);
-
-	rv |= bq27621_write(STATE_BLOCK_DESIGN_ENERGY, DESIGN_ENERGY);
-	checksum += CHECKSUM_2B(DESIGN_ENERGY);
-
-	rv |= bq27621_write(STATE_BLOCK_TERMINATE_VOLTAGE, TERMINATE_VOLTAGE);
-	checksum += CHECKSUM_2B(TERMINATE_VOLTAGE);
-
-	rv |= bq27621_write(STATE_BLOCK_TAPER_RATE, TAPER_RATE);
-	checksum += CHECKSUM_2B(TAPER_RATE);
-
-	checksum = 0xff - (0xff & checksum);
-
-
-	if (rv)
-		return rv;
-
-	rv = bq27621_write8(REG_BLOCK_DATA_CHECKSUM, checksum);
-
-	rv |= bq27621_write(REG_CTRL, CONTROL_SOFT_RESET);
-
-	if (rv)
-		return rv;
-
-	bq27621_seal();
-
-	return rv;
-}
-
-static void probe_type_id_init(void)
-{
-	int rv = EC_SUCCESS;
-
-	rv = bq27621_probe();
-
-	if (rv)
-		return;
-
-	rv = bq27621_init();
-
-	if (rv) { /* Try it once more */
-		rv = bq27621_write(REG_CTRL, CONTROL_RESET);
-	  rv |= bq27621_init();
-	}
-}
-
-DECLARE_HOOK(HOOK_INIT, probe_type_id_init, HOOK_PRIO_DEFAULT);
-
-/* Some of the functions to make this battery "smart" */
-
-int battery_device_name(char *device_name, int buf_size)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_state_of_charge_abs(int *percent)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	int scaled_value, err_code;
-
-	err_code = bq27621_read(REG_REMAINING_CAPACITY, &scaled_value);
-
-	*capacity = BQ27621_UNSCALE(scaled_value);
-
-	return err_code;
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	int scaled_value, err_code;
-
-	err_code = bq27621_read(REG_FULL_CHARGE_CAPACITY, &scaled_value);
-
-	*capacity = BQ27621_UNSCALE(scaled_value);
-
-	return err_code;
-}
-
-int battery_time_to_empty(int *minutes)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_time_to_full(int *minutes)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_cycle_count(int *count)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_design_capacity(int *capacity)
-{
-	int scaled_value, err_code;
-
-	err_code = bq27621_read(REG_DESIGN_CAPACITY, &scaled_value);
-
-	*capacity = BQ27621_UNSCALE(scaled_value);
-
-	return err_code;
-}
-
-int battery_time_at_rate(int rate, int *minutes)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_device_chemistry(char *dest, int size)
-{
-	uint32_t rv;
-	int param;
-
-	rv = bq27621_write(REG_CTRL, CONTROL_CHEM_ID);
-	rv |= bq27621_read(REG_CTRL, &param);
-
-	if (param == 0x1202)
-		strzcpy(dest, "0x1202 (default)", size);
-	if (param == 0x1210)
-		strzcpy(dest, "0x1210 (ALT_CHEM1)", size);
-	if (param == 0x0354)
-		strzcpy(dest, "0x0354 (ALT_CHEM2)", size);
-
-	return EC_SUCCESS;
-}
-
-int battery_serial_number(int *serial)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_manufacture_date(int *year, int *month, int *day)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = BATTERY_VOLTAGE_NORMAL;
-
-	return EC_SUCCESS;
-}
-
-int battery_get_mode(int *mode)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_status(int *status)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-enum battery_present battery_is_present(void)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void battery_get_params(struct batt_params *batt)
-{
-	/* Reset flags */
-	batt->flags = 0;
-
-	if (bq27621_read(REG_TEMPERATURE, &batt->temperature))
-		batt->flags |= BATT_FLAG_BAD_TEMPERATURE;
-	else
-		batt->flags |= BATT_FLAG_RESPONSIVE; /* Battery is responding */
-
-	if (bq27621_read8(REG_STATE_OF_CHARGE, &batt->state_of_charge))
-		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-
-	if (bq27621_read(REG_VOLTAGE, &batt->voltage))
-		batt->flags |= BATT_FLAG_BAD_VOLTAGE;
-
-	batt->flags |= BATT_FLAG_BAD_CURRENT;
-	batt->current = 0;
-
-	/* Default to not desiring voltage and current */
-	batt->desired_voltage = batt->desired_current = 0;
-}
-
-/* Wait until battery is totally stable */
-int battery_wait_for_stable(void)
-{
-	/* TODO(crosbug.com/p/30426): implement me */
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_BATDEBUG
-	#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#else
-	#define CPRINTF(format, args...)
-#endif
-
-#ifdef CONFIG_CMD_BATDEBUG
-
-static int command_fgunseal(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	rv = bq27621_unseal();
-
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal,
-			"",
-			"Unseal the fg");
-
-static int command_fgseal(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-
-	if (argc > 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	rv = bq27621_seal();
-
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal,
-			"",
-			"Seal the fg");
-
-static int command_fginit(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-	int force = 0;
-	int flags = 0;
-	int unconfigured = 0;
-	char *e;
-
-	if (argc > 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (argc == 2) {
-		force = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	rv = bq27621_read(REG_FLAGS, &flags);
-	unconfigured = flags & FLAGS_ITPOR;
-
-	if (!unconfigured && force) {
-		rv |= bq27621_write(REG_CTRL, CONTROL_RESET);
-		unconfigured = (rv == EC_SUCCESS);
-	}
-
-	if (unconfigured)
-		rv |= bq27621_init();
-
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fginit, command_fginit,
-			"[force]",
-			"Initialize the fg");
-
-static int command_fgprobe(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-
-	if (argc != 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	rv = bq27621_probe();
-
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe,
-			"",
-			"Probe the fg");
-
-static int command_fgrd(int argc, char **argv)
-{
-	int cmd, len;
-	int rv = EC_SUCCESS;
-	int data;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	cmd = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	len = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	if (len == 2)
-		rv = bq27621_read(cmd, &data);
-	else if (len == 1)
-		rv = bq27621_read8(cmd, &data);
-	else
-		return EC_ERROR_PARAM2;
-
-	CPRINTF("Read %d bytes @0xaa %0x: 0x%0x\n", len, cmd, data);
-
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd,
-			"cmd len",
-			"Read _len_ words from the fg");
-
-static int command_fgcmd(int argc, char **argv)
-{
-	int cmd, data, byte = 0;
-	char *e;
-
-	if (argc < 3 || argc > 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	cmd = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	data = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 4) {
-		byte = strtoi(argv[3], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-	}
-
-	if (byte) {
-		CPRINTF("Write a byte @0xaa %0x: 0x%0x\n", cmd, data);
-		return bq27621_write8(cmd, data);
-	} else {
-		CPRINTF("Write 2 bytes @0xaa %0x: 0x%0x\n", cmd, data);
-		return bq27621_write(cmd, data);
-	}
-
-}
-
-DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd,
-			"cmd data [byte]",
-			"Send a cmd to the fg");
-
-static int command_fgcmdrd(int argc, char **argv)
-{
-	int cmd, data, val;
-	int rv = EC_SUCCESS;
-	char *e;
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	cmd = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	data = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	rv = bq27621_write(cmd, data);
-	rv |= bq27621_read(cmd, &val);
-
-	CPRINTF("Read: @0xaa (%x %x) %x\n", cmd, data, val);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(fgcmdrd, command_fgcmdrd,
-			"cmd data",
-			"Send a 2-byte cmd to the fg, read back the 2-byte result");
-
-#endif /* CONFIG_CMD_BATDEBUG */
-
diff --git a/driver/battery/bq4050.c b/driver/battery/bq4050.c
deleted file mode 100644
index 684ade47e6..0000000000
--- a/driver/battery/bq4050.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery driver for TI BQ4050 family, including BQ40Z50 (and -R1, -R2),
- * BQ40Z552, and BQ40Z60.
- */
-
-#include "battery_smart.h"
-#include "util.h"
-
-#include <stdint.h>
-
-int battery_bq4050_imbalance_mv(void)
-{
-	/*
-	 * The BQ4050 family can manage up to four cells.  In testing it always
-	 * returns a voltage for each cell, regardless of the number of cells
-	 * actually installed in the pack.  Unpopulated cells read exactly zero.
-	 */
-	static const uint8_t cell_voltage_address[4] = {
-		0x3c, 0x3d, 0x3e, 0x3f
-	};
-	int i, res, cell_voltage;
-	int n_cells = 0;
-	int max_voltage = 0;
-	int min_voltage = 0xffff;
-
-	for (i = 0; i != ARRAY_SIZE(cell_voltage_address); ++i) {
-		res = sb_read(cell_voltage_address[i], &cell_voltage);
-		if (res == EC_SUCCESS && cell_voltage != 0) {
-			n_cells++;
-			max_voltage = MAX(max_voltage, cell_voltage);
-			min_voltage = MIN(min_voltage, cell_voltage);
-		}
-	}
-	return (n_cells == 0) ? 0 : max_voltage - min_voltage;
-}
-
diff --git a/driver/battery/max17055.c b/driver/battery/max17055.c
deleted file mode 100644
index bb0b941937..0000000000
--- a/driver/battery/max17055.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for MAX17055.
- */
-
-#include "battery.h"
-#include "console.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "max17055.h"
-#include "printf.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/*
- * For max17055 to finish battery presence detection, this is the minimal time
- * we have to wait since the last POR. LSB = 175ms.
- */
-#define RELIABLE_BATT_DETECT_TIME	0x10
-
-/*
- * Convert the register values to the units that match
- * smart battery protocol.
- */
-
-/* Voltage reg value to mV */
-#define VOLTAGE_CONV(REG)       ((REG * 5) >> 6)
-/* Current reg value to mA */
-#define CURRENT_CONV(REG)       (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE)
-/* Capacity reg value to mAh */
-#define CAPACITY_CONV(REG)      (REG * 5 / BATTERY_MAX17055_RSENSE)
-/* Time reg value to minute */
-#define TIME_CONV(REG)          ((REG * 3) >> 5)
-/* Temperature reg value to 0.1K */
-#define TEMPERATURE_CONV(REG)   (((REG * 10) >> 8) + 2731)
-/* Percentage reg value to 1% */
-#define PERCENTAGE_CONV(REG)    (REG >> 8)
-/* Cycle count reg value (LSB = 1%) to absolute count (100%) */
-#define CYCLE_COUNT_CONV(REG)	((REG * 5) >> 9)
-
-/* Useful macros */
-#define MAX17055_READ_DEBUG(offset, ptr_reg) \
-	do { \
-		if (max17055_read(offset, ptr_reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
-	} while (0)
-#define MAX17055_WRITE_DEBUG(offset, reg) \
-	do { \
-		if (max17055_write(offset, reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
-	} while (0)
-
-static int fake_state_of_charge = -1;
-
-static int max17055_read(int offset, int *data)
-{
-	return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			  offset, data);
-}
-
-static int max17055_write(int offset, int data)
-{
-	return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			   offset, data);
-}
-
-/* Return 1 if the device id is correct. */
-static int max17055_probe(void)
-{
-	int dev_id;
-
-	if (max17055_read(REG_DEVICE_NAME, &dev_id))
-		return 0;
-	if (dev_id == MAX17055_DEVICE_ID)
-		return 1;
-	return 0;
-}
-
-int battery_device_name(char *device_name, int buf_size)
-{
-	int dev_id;
-	int rv;
-
-	rv = max17055_read(REG_DEVICE_NAME, &dev_id);
-	if (!rv)
-		snprintf(device_name, buf_size, "0x%04x", dev_id);
-
-	return rv;
-}
-
-int battery_state_of_charge_abs(int *percent)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_REMAINING_CAPACITY, &reg);
-	if (!rv)
-		*capacity = CAPACITY_CONV(reg);
-	return rv;
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_FULL_CHARGE_CAPACITY, &reg);
-	if (!rv)
-		*capacity = CAPACITY_CONV(reg);
-	return rv;
-}
-
-int battery_time_to_empty(int *minutes)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_TIME_TO_EMPTY, &reg);
-	if (!rv)
-		*minutes = TIME_CONV(reg);
-	return rv;
-}
-
-int battery_time_to_full(int *minutes)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_TIME_TO_FULL, &reg);
-	if (!rv)
-		*minutes = TIME_CONV(reg);
-	return rv;
-}
-
-int battery_cycle_count(int *count)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_CYCLE_COUNT, &reg);
-	if (!rv)
-		*count = CYCLE_COUNT_CONV(reg);
-	return rv;
-}
-
-int battery_design_capacity(int *capacity)
-{
-	int rv;
-	int reg;
-
-	rv = max17055_read(REG_DESIGN_CAPACITY, &reg);
-	if (!rv)
-		*capacity = CAPACITY_CONV(reg);
-	return rv;
-}
-
-int battery_time_at_rate(int rate, int *minutes)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_device_chemistry(char *dest, int size)
-{
-	strzcpy(dest, "<unkn>", size);
-
-	return EC_SUCCESS;
-}
-
-int battery_serial_number(int *serial)
-{
-	/* TODO(philipchen): Implement this function. */
-	*serial = 0xFFFFFFFF;
-	return EC_SUCCESS;
-}
-
-int battery_manufacture_date(int *year, int *month, int *day)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = battery_get_info()->voltage_normal;
-
-	return EC_SUCCESS;
-}
-
-int battery_get_mode(int *mode)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_status(int *status)
-{
-	int rv;
-	int reg;
-
-	*status = 0;
-
-	rv = max17055_read(REG_FSTAT, &reg);
-	if (rv)
-		return rv;
-	if (reg & FSTAT_FQ)
-		*status |= BATTERY_FULLY_CHARGED;
-
-	rv = max17055_read(REG_AVERAGE_CURRENT, &reg);
-	if (rv)
-		return rv;
-	if (reg >> 15)
-		*status |= BATTERY_DISCHARGING;
-
-	return EC_SUCCESS;
-}
-
-enum battery_present battery_is_present(void)
-{
-	int reg = 0;
-	static uint8_t batt_pres_sure;
-
-	if (max17055_read(REG_STATUS, &reg))
-		return BP_NOT_SURE;
-
-	if (reg & STATUS_BST)
-		return BP_NO;
-
-	if (!batt_pres_sure) {
-		/*
-		 * The battery detection result is not reliable within
-		 * ~2.8 secs since POR.
-		 */
-		if (!max17055_read(REG_TIMERH, &reg)) {
-			/*
-			 * The LSB of TIMERH reg is 3.2 hrs. If the reg has a
-			 * nonzero value, battery detection must have been
-			 * settled.
-			 */
-			if (reg) {
-				batt_pres_sure = 1;
-				return BP_YES;
-			}
-			if (!max17055_read(REG_TIMER, &reg) &&
-			    ((uint32_t)reg > RELIABLE_BATT_DETECT_TIME)) {
-				batt_pres_sure = 1;
-				return BP_YES;
-			}
-		}
-		return BP_NOT_SURE;
-	}
-	return BP_YES;
-}
-
-void battery_get_params(struct batt_params *batt)
-{
-	int reg = 0;
-	struct batt_params batt_new = {0};
-
-	/*
-	 * Assuming the battery is responsive as long as
-	 * max17055 finds battery is present.
-	 */
-	batt_new.is_present = battery_is_present();
-
-	if (batt_new.is_present == BP_YES)
-		batt_new.flags |= BATT_FLAG_RESPONSIVE;
-	else if (batt_new.is_present == BP_NO)
-		/* Battery is not present, gauge won't report useful info. */
-		goto batt_out;
-
-	if (max17055_read(REG_TEMPERATURE, &reg))
-		batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE;
-
-	batt_new.temperature = TEMPERATURE_CONV((int16_t)reg);
-
-	if (max17055_read(REG_STATE_OF_CHARGE, &reg) &&
-	    fake_state_of_charge < 0)
-		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-
-	batt_new.state_of_charge = fake_state_of_charge >= 0 ?
-				fake_state_of_charge : PERCENTAGE_CONV(reg);
-
-	if (max17055_read(REG_VOLTAGE, &reg))
-		batt_new.flags |= BATT_FLAG_BAD_VOLTAGE;
-
-	batt_new.voltage = VOLTAGE_CONV(reg);
-
-	if (max17055_read(REG_AVERAGE_CURRENT, &reg))
-		batt_new.flags |= BATT_FLAG_BAD_CURRENT;
-
-	batt_new.current = CURRENT_CONV((int16_t)reg);
-
-	batt_new.desired_voltage = battery_get_info()->voltage_max;
-	batt_new.desired_current = BATTERY_DESIRED_CHARGING_CURRENT;
-
-	if (battery_remaining_capacity(&batt_new.remaining_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_REMAINING_CAPACITY;
-
-	if (battery_full_charge_capacity(&batt_new.full_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_FULL_CAPACITY;
-
-	/*
-	 * Charging allowed if both desired voltage and current are nonzero
-	 * and battery isn't full (and we read them all correctly).
-	 */
-	if (!(batt_new.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
-	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
-		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
-
-	if (battery_status(&batt_new.status))
-		batt_new.flags |= BATT_FLAG_BAD_STATUS;
-
-batt_out:
-	/* Update visible battery parameters */
-	memcpy(batt, &batt_new, sizeof(*batt));
-}
-
-#ifdef CONFIG_CMD_PWR_AVG
-int battery_get_avg_current(void)
-{
-	/* TODO(crbug.com/752320) implement this */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_get_avg_voltage(void)
-{
-	/* TODO(crbug.com/752320) implement this */
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-#endif /* CONFIG_CMD_PWR_AVG */
-
-/* Wait until battery is totally stable. */
-int battery_wait_for_stable(void)
-{
-	/* TODO(philipchen): Implement this function. */
-	return EC_SUCCESS;
-}
-
-static int max17055_poll_flag_clear(int regno, int mask, int timeout)
-{
-	int reg;
-
-	do {
-		if (max17055_read(regno, &reg))
-			return EC_ERROR_UNKNOWN;
-
-		if (!(mask & reg))
-			return EC_SUCCESS;
-
-		msleep(10);
-		timeout -= 10;
-	} while (timeout > 0);
-
-	return EC_ERROR_TIMEOUT;
-}
-
-static int max17055_load_ocv_table(const struct max17055_batt_profile *config)
-{
-	int i;
-	int reg;
-	int retries = 3;
-
-	/* Unlock ocv table */
-	if (max17055_write(REG_LOCK1, 0x0059) ||
-	    max17055_write(REG_LOCK2, 0x00c4))
-		return EC_ERROR_UNKNOWN;
-
-	ASSERT(config->ocv_table);
-
-	/* Write ocv data */
-	for (i = 0; i < MAX17055_OCV_TABLE_SIZE; i++) {
-		if (max17055_write(REG_OCV_TABLE_START + i,
-				   config->ocv_table[i]))
-			return EC_ERROR_UNKNOWN;
-	}
-
-	/* Read and compare ocv data */
-	for (i = 0; i < MAX17055_OCV_TABLE_SIZE; i++) {
-		if (max17055_read(REG_OCV_TABLE_START + i, &reg) ||
-		    reg != config->ocv_table[i])
-			return EC_ERROR_UNKNOWN;
-	}
-
-	while (--retries) {
-		/* Lock ocv table */
-		if (max17055_write(REG_LOCK1, 0x0000) ||
-		    max17055_write(REG_LOCK2, 0x0000))
-			return EC_ERROR_UNKNOWN;
-
-		/*
-		 * If the ocv table remains unlocked, the MAX17055 cannot
-		 * monitor the capacity of the battery. Therefore, it is very
-		 * critical that the ocv table is locked. To verify it is
-		 * locked, simply read back the values. However, this time,
-		 * all values should be read as 0x0000.
-		 */
-		for (i = 0; i < MAX17055_OCV_TABLE_SIZE; i++) {
-			reg = 0xff;
-			if (max17055_read(REG_OCV_TABLE_START + i, &reg))
-				return EC_ERROR_UNKNOWN;
-			if (reg)
-				break;
-		}
-		if (i == MAX17055_OCV_TABLE_SIZE)
-			break;
-		msleep(20);
-	}
-	if (!retries)
-		return EC_ERROR_TIMEOUT;
-
-	/*
-	 * Delay 180ms is to prepare the environment to load the custom
-	 * battery parameters. Otherwise, the initialization operation
-	 * has a very small probability of failure.
-	 */
-	msleep(180);
-
-	return EC_SUCCESS;
-}
-
-static int max17055_exit_hibernate(void)
-{
-	/*
-	 * Write REG_COMMAND with 0x90 to force the firmware to stop running.
-	 * Write REG_HIBCFG with 0x00 to exit hibernate mode immediately.
-	 * Write REG_COMMAND with 0x00 to run the firmware again.
-	 */
-	if (max17055_write(REG_COMMAND, 0x90) ||
-	    max17055_write(REG_HIBCFG, 0x00) ||
-	    max17055_write(REG_COMMAND, 0x00))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Configured MAX17055 with the battery parameters for full model. */
-static int max17055_load_batt_model_full(void)
-{
-	int reg;
-	int hib_cfg;
-
-	const struct max17055_batt_profile *config;
-
-	config = max17055_get_batt_profile();
-
-	/* Store the original HibCFG value. */
-	if (max17055_read(REG_HIBCFG, &hib_cfg))
-		return EC_ERROR_UNKNOWN;
-
-	/* Force exit from hibernate */
-	if (max17055_exit_hibernate())
-		return EC_ERROR_UNKNOWN;
-
-	/* Write LearnCFG with LS 7 */
-	if (max17055_write(REG_LEARNCFG, config->learn_cfg | 0x0070))
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Unlock ocv table access, write/compare/verify custom ocv table,
-	 * lock ocv table access.
-	 */
-	if (max17055_load_ocv_table(config))
-		return EC_ERROR_UNKNOWN;
-
-	/* Write custom parameters */
-	if (max17055_write(REG_DESIGN_CAPACITY, config->design_cap) ||
-	    max17055_write(REG_DQACC, config->design_cap >> 4) ||
-	    max17055_write(REG_DPACC, 0x0c80) ||
-	    max17055_write(REG_CHARGE_TERM_CURRENT, config->ichg_term) ||
-	    max17055_write(REG_EMPTY_VOLTAGE, config->v_empty_detect))
-		return EC_ERROR_UNKNOWN;
-
-	if (max17055_write(REG_RCOMP0, config->rcomp0) ||
-	    max17055_write(REG_TEMPCO, config->tempco) ||
-	    max17055_write(REG_QR_TABLE00, config->qr_table00) ||
-	    max17055_write(REG_QR_TABLE10, config->qr_table10))
-		return EC_ERROR_UNKNOWN;
-
-	/* Update required capacity registers */
-	if (max17055_write(REG_REMAINING_CAPACITY, 0x0000) ||
-	    max17055_read(REG_VFSOC, &reg))
-		return EC_ERROR_UNKNOWN;
-
-	if (max17055_write(REG_VFSOC0, reg) ||
-	    max17055_write(REG_FULL_CHARGE_CAPACITY, config->design_cap) ||
-	    max17055_write(REG_FULLCAPNOM, config->design_cap))
-		return EC_ERROR_UNKNOWN;
-
-	/* Prepare to Load Model */
-	if (max17055_write(REG_REMAINING_CAPACITY, 0x0000) ||
-	    max17055_write(REG_MIXCAP, config->design_cap))
-		return EC_ERROR_UNKNOWN;
-
-	/* Initiate model loading */
-	if (max17055_read(REG_CONFIG2, &reg) ||
-	    max17055_write(REG_CONFIG2, reg | CONFIG2_LDMDL))
-		return EC_ERROR_UNKNOWN;
-
-	if (max17055_poll_flag_clear(REG_CONFIG2, CONFIG2_LDMDL, 500))
-		return EC_ERROR_UNKNOWN;
-
-	/* Write LearnCFG with LS 0 */
-	if (max17055_write(REG_LEARNCFG, config->learn_cfg & 0xff8f) ||
-	    max17055_write(REG_QR_TABLE20, config->qr_table20) ||
-	    max17055_write(REG_QR_TABLE30, config->qr_table30))
-		return EC_ERROR_UNKNOWN;
-
-	/* Restore the original HibCFG value. */
-	if (max17055_write(REG_HIBCFG, hib_cfg))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/*
- * Configured MAX17055 with the battery parameters for short model or ez model
- */
-static int max17055_load_batt_model_short_or_ez(void)
-{
-	int hib_cfg;
-	int dqacc;
-	int dpacc;
-
-	const struct max17055_batt_profile *config;
-
-	config = max17055_get_batt_profile();
-
-	if (config->is_ez_config) {
-		dqacc = config->design_cap / 32;
-		/* Choose the model for charge voltage > 4.275V. */
-		dpacc = dqacc * 51200 / config->design_cap;
-	} else {
-		dqacc = config->design_cap / 16;
-		dpacc = config->dpacc;
-	}
-
-	if (max17055_write(REG_DESIGN_CAPACITY, config->design_cap) ||
-	    max17055_write(REG_DQACC, dqacc) ||
-	    max17055_write(REG_CHARGE_TERM_CURRENT, config->ichg_term) ||
-	    max17055_write(REG_EMPTY_VOLTAGE, config->v_empty_detect))
-		return EC_ERROR_UNKNOWN;
-
-	if (!config->is_ez_config) {
-		if (max17055_write(REG_LEARNCFG, config->learn_cfg))
-			return EC_ERROR_UNKNOWN;
-	}
-
-	/* Store the original HibCFG value. */
-	if (max17055_read(REG_HIBCFG, &hib_cfg))
-		return EC_ERROR_UNKNOWN;
-
-	/* Force exit from hibernate */
-	if (max17055_exit_hibernate())
-		return EC_ERROR_UNKNOWN;
-
-	if (max17055_write(REG_DPACC, dpacc) ||
-	    max17055_write(REG_MODELCFG, (MODELCFG_REFRESH | MODELCFG_VCHG)))
-		return EC_ERROR_UNKNOWN;
-
-	/* Delay up to 500 ms until MODELCFG.REFRESH bit == 0. */
-	if (max17055_poll_flag_clear(REG_MODELCFG, MODELCFG_REFRESH, 500))
-		return EC_ERROR_UNKNOWN;
-
-	if (!config->is_ez_config) {
-		if (max17055_write(REG_RCOMP0, config->rcomp0) ||
-		    max17055_write(REG_TEMPCO, config->tempco) ||
-		    max17055_write(REG_QR_TABLE00, config->qr_table00) ||
-		    max17055_write(REG_QR_TABLE10, config->qr_table10) ||
-		    max17055_write(REG_QR_TABLE20, config->qr_table20) ||
-		    max17055_write(REG_QR_TABLE30, config->qr_table30))
-			return EC_ERROR_UNKNOWN;
-	}
-
-	/* Restore the original HibCFG value. */
-	if (max17055_write(REG_HIBCFG, hib_cfg))
-		return EC_ERROR_UNKNOWN;
-	return EC_SUCCESS;
-}
-
-static int max17055_load_batt_model(void)
-{
-	if (IS_ENABLED(CONFIG_BATTERY_MAX17055_FULL_MODEL))
-		return max17055_load_batt_model_full();
-	else
-		return max17055_load_batt_model_short_or_ez();
-}
-
-static void max17055_init(void)
-{
-	int reg;
-	int retries = 80;
-#ifdef CONFIG_BATTERY_MAX17055_ALERT
-	const struct max17055_alert_profile *alert_profile =
-		max17055_get_alert_profile();
-#endif
-
-	if (!max17055_probe()) {
-		CPRINTS("Wrong max17055 id!");
-		return;
-	}
-
-	/*
-	 * Set CONFIG.TSEL to measure temperature using external thermistor.
-	 * Set it as early as possible because max17055 takes up to 1000ms to
-	 * have the first reliable external temperature reading.
-	 */
-	MAX17055_READ_DEBUG(REG_CONFIG, &reg);
-	MAX17055_WRITE_DEBUG(REG_CONFIG, (reg | CONF_TSEL));
-
-	MAX17055_READ_DEBUG(REG_STATUS, &reg);
-
-	/* Check for POR */
-	if (STATUS_POR & reg) {
-		/* Delay up to 800 ms until FSTAT.DNR bit == 0. */
-		while (--retries) {
-			MAX17055_READ_DEBUG(REG_FSTAT, &reg);
-			if (!(FSTAT_DNR & reg))
-				break;
-			msleep(10);
-		}
-		if (!retries) {
-			CPRINTS("%s: timeout waiting for FSTAT.DNR cleared",
-				__func__);
-			return;
-		}
-
-		if (max17055_load_batt_model()) {
-			CPRINTS("max17055 configuration failed!");
-			return;
-		}
-
-		/* Clear POR bit */
-		MAX17055_READ_DEBUG(REG_STATUS, &reg);
-		MAX17055_WRITE_DEBUG(REG_STATUS, (reg & ~STATUS_POR));
-	} else {
-		const struct max17055_batt_profile *config;
-
-		config = max17055_get_batt_profile();
-		MAX17055_READ_DEBUG(REG_DESIGN_CAPACITY, &reg);
-
-		/*
-		 * Reload the battery model if the current running one
-		 * is wrong.
-		 */
-		if (config->design_cap != reg) {
-			CPRINTS("max17055 reconfig...");
-			if (max17055_load_batt_model()) {
-				CPRINTS("max17055 configuration failed!");
-				return;
-			}
-		}
-	}
-
-#ifdef CONFIG_BATTERY_MAX17055_ALERT
-	/* Set voltage alert range */
-	MAX17055_WRITE_DEBUG(REG_VALRTTH, alert_profile->v_alert_mxmn);
-	/* Set temperature alert range */
-	MAX17055_WRITE_DEBUG(REG_TALRTTH, alert_profile->t_alert_mxmn);
-	/* Set state-of-charge alert range */
-	MAX17055_WRITE_DEBUG(REG_SALRTTH, alert_profile->s_alert_mxmn);
-	/* Set current alert range */
-	MAX17055_WRITE_DEBUG(REG_IALRTTH, alert_profile->i_alert_mxmn);
-
-	/* Disable all sticky bits; enable alert AEN */
-	MAX17055_READ_DEBUG(REG_CONFIG, &reg);
-	MAX17055_WRITE_DEBUG(REG_CONFIG, (reg & ~CONF_ALL_STICKY) | CONF_AEN);
-
-	/* Clear alerts */
-	MAX17055_READ_DEBUG(REG_STATUS, &reg);
-	MAX17055_WRITE_DEBUG(REG_STATUS, reg & ~STATUS_ALL_ALRT);
-#endif
-
-	CPRINTS("max17055 configuration succeeded!");
-}
-DECLARE_HOOK(HOOK_INIT, max17055_init, HOOK_PRIO_DEFAULT);
diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h
deleted file mode 100644
index 0f97fb90f0..0000000000
--- a/driver/battery/max17055.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for MAX17055.
- */
-
-#ifndef __CROS_EC_MAX17055_H
-#define __CROS_EC_MAX17055_H
-
-#define MAX17055_ADDR_FLAGS         0x36
-#define MAX17055_DEVICE_ID          0x4010
-#define MAX17055_OCV_TABLE_SIZE     48
-
-#define REG_STATUS                  0x00
-#define REG_VALRTTH                 0x01
-#define REG_TALRTTH                 0x02
-#define REG_SALRTTH                 0x03
-#define REG_AT_RATE                 0x04
-#define REG_REMAINING_CAPACITY      0x05
-#define REG_STATE_OF_CHARGE         0x06
-#define REG_TEMPERATURE             0x08
-#define REG_VOLTAGE                 0x09
-#define REG_CURRENT                 0x0a
-#define REG_AVERAGE_CURRENT         0x0b
-#define REG_MIXCAP                  0x0f
-#define REG_FULL_CHARGE_CAPACITY    0x10
-#define REG_TIME_TO_EMPTY           0x11
-#define REG_QR_TABLE00              0x12
-#define REG_CONFIG                  0x1D
-#define REG_AVERAGE_TEMPERATURE     0x16
-#define REG_CYCLE_COUNT             0x17
-#define REG_DESIGN_CAPACITY         0x18
-#define REG_AVERAGE_VOLTAGE         0x19
-#define REG_MAX_MIN_TEMP            0x1a
-#define REG_MAX_MIN_VOLT            0x1b
-#define REG_MAX_MIN_CURR            0x1c
-#define REG_CHARGE_TERM_CURRENT     0x1e
-#define REG_TIME_TO_FULL            0x20
-#define REG_DEVICE_NAME             0x21
-#define REG_QR_TABLE10              0x22
-#define REG_FULLCAPNOM              0x23
-#define REG_LEARNCFG                0x28
-#define REG_QR_TABLE20              0x32
-#define REG_RCOMP0                  0x38
-#define REG_TEMPCO                  0x39
-#define REG_EMPTY_VOLTAGE           0x3a
-#define REG_FSTAT                   0x3d
-#define REG_TIMER                   0x3e
-#define REG_QR_TABLE30              0x42
-#define REG_DQACC                   0x45
-#define REG_DPACC                   0x46
-#define REG_VFSOC0                  0x48
-#define REG_COMMAND                 0x60
-#define REG_LOCK1                   0x62
-#define REG_LOCK2                   0x63
-#define REG_OCV_TABLE_START         0x80
-#define REG_STATUS2                 0xb0
-#define REG_IALRTTH                 0xb4
-#define REG_HIBCFG                  0xba
-#define REG_CONFIG2                 0xbb
-#define REG_TIMERH                  0xbe
-#define REG_MODELCFG                0xdb
-#define REG_VFSOC                   0xff
-
-/* Status reg (0x00) flags */
-#define STATUS_POR                  BIT(1)
-#define STATUS_IMN                  BIT(2)
-#define STATUS_BST                  BIT(3)
-#define STATUS_IMX                  BIT(6)
-#define STATUS_VMN                  BIT(8)
-#define STATUS_TMN                  BIT(9)
-#define STATUS_SMN                  BIT(10)
-#define STATUS_VMX                  BIT(12)
-#define STATUS_TMX                  BIT(13)
-#define STATUS_SMX                  BIT(14)
-#define STATUS_ALL_ALRT                                                        \
-	(STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN |      \
-	 STATUS_TMX | STATUS_SMN | STATUS_SMX)
-
-/* Alert disable values (0x01, 0x02, 0x03, 0xb4) */
-#define VALRT_DISABLE               0xff00
-#define TALRT_DISABLE               0x7f80
-#define SALRT_DISABLE               0xff00
-#define IALRT_DISABLE               0x7f80
-
-/* Config reg (0x1d) flags */
-#define CONF_AEN                    BIT(2)
-#define CONF_IS                     BIT(11)
-#define CONF_VS                     BIT(12)
-#define CONF_TS                     BIT(13)
-#define CONF_SS                     BIT(14)
-#define CONF_TSEL                   BIT(15)
-#define CONF_ALL_STICKY             (CONF_IS | CONF_VS | CONF_TS | CONF_SS)
-
-/* FStat reg (0x3d) flags */
-#define FSTAT_DNR                   0x0001
-#define FSTAT_FQ                    0x0080
-
-/* Config2 reg (0xbb) flags */
-#define CONFIG2_LDMDL               BIT(5)
-
-/* ModelCfg reg (0xdb) flags */
-#define MODELCFG_REFRESH            BIT(15)
-#define MODELCFG_VCHG               BIT(10)
-
-/* Smart battery status bits (sbs reg 0x16) */
-#define BATTERY_DISCHARGING         0x40
-#define BATTERY_FULLY_CHARGED       0x20
-
-/*
- * Before we have the battery fully characterized, we use these macros to
- * convert basic battery parameters to max17055 reg values for ez config.
- */
-
-/* Convert design capacity in mAh to max17055 0x18 reg value */
-#define MAX17055_DESIGNCAP_REG(bat_cap_mah) \
-	(bat_cap_mah * BATTERY_MAX17055_RSENSE / 5)
-/* Convert charge termination current in mA to max17055 0x1e reg value */
-#define MAX17055_ICHGTERM_REG(term_cur_ma) \
-	(((term_cur_ma * BATTERY_MAX17055_RSENSE) << 4) / 25)
-/*
- * This macro converts empty voltage target (VE) and recovery voltage (VR)
- * in mV to max17055 0x3a reg value. max17055 declares 0% (empty battery) at
- * VE. max17055 reenables empty detection when the cell voltage rises above VR.
- * VE ranges from 0 to 5110mV, and VR ranges from 0 to 5080mV.
- */
-#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) \
-	(((ve_mv / 10) << 7) | (vr_mv / 40))
-
-#define MAX17055_MAX_MIN_REG(mx, mn) ((((int16_t)(mx)) << 8) | ((mn)))
-/* Converts voltages alert range for VALRTTH_REG */
-#define MAX17055_VALRTTH_RESOLUTION 20
-#define MAX17055_VALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION),      \
-			     (uint8_t)(mn / MAX17055_VALRTTH_RESOLUTION))
-/* Converts temperature alert range for TALRTTH_REG */
-#define MAX17055_TALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG((int8_t)(mx), (int8_t)(mn))
-/* Converts state-of-charge alert range for SALRTTH_REG */
-#define MAX17055_SALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG((uint8_t)(mx), (uint8_t)(mn))
-/* Converts current alert range for IALRTTH_REG */
-/* Current resolution: 0.4mV/RSENSE */
-#define MAX17055_IALRTTH_MUL (10 * BATTERY_MAX17055_RSENSE)
-#define MAX17055_IALRTTH_DIV 4
-#define MAX17055_IALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG(                                                  \
-		(int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV),    \
-		(int8_t)(mn * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV))
-
-/*
- * max17055 needs some special battery parameters for fuel gauge
- * learning algorithm. Maxim can help characterize the battery pack
- * to get a full parameter list. We create a data structure to store
- * the battery parameters in the format of max17055 register values.
- */
-struct max17055_batt_profile {
-	/* Design capacity of the cell (LSB = 5uVH / Rsense) */
-	uint16_t design_cap;
-	/* Charge termination current (LSB = 1.5625uV / Rsense) */
-	uint16_t ichg_term;
-	/* The combination of empty voltage target and recovery voltage */
-	uint16_t v_empty_detect;
-
-	/*
-	 * The parameters below are used for advanced (non-EZ) config
-	 * (dpacc, learn_cfg, tempco, qr_table00, qr_table10,
-	 * qr_table20, and qr_table30)
-	 */
-
-	/* Change in battery SOC between relaxation points (LSB = pct / 16) */
-	uint16_t dpacc;
-	/* Magic cell tuning parameters */
-	uint16_t learn_cfg;
-	uint16_t rcomp0;
-	uint16_t tempco;
-	uint16_t qr_table00;
-	uint16_t qr_table10;
-	uint16_t qr_table20;
-	uint16_t qr_table30;
-
-	/*
-	 * If is_ez_config is nonzero, we only use design_cap, ichg_term,
-	 * and v_empty_detect to config max17055 (a.k.a. EZ-config).
-	 */
-	uint8_t is_ez_config;
-
-	/* Used only for full model */
-	const uint16_t *ocv_table;
-};
-
-/* Return the special battery parameters max17055 needs. */
-const struct max17055_batt_profile *max17055_get_batt_profile(void);
-
-#ifdef CONFIG_BATTERY_MAX17055_ALERT
-/*
- * max17055 supports alert on voltage, current, state-of-charge, and
- * temperature.  To enable this feature, the information of the limit range is
- * needed.
- */
-struct max17055_alert_profile {
-	/*
-	 * Sets voltage upper and lower limits that generate an alert if
-	 * voltage is outside of the v_alert_mxmn range.
-	 * The upper 8 bits set the maximum value and the lower 8 bits set the
-	 * minimum value. Interrupt threshold limits are selectable with 20mV
-	 * resolution.
-	 * Use MAX17055_VALRTTH_REG(max, min) to setup the desired range,
-	 * VALRT_DISABLE to disable the alert.
-	 */
-	const uint16_t v_alert_mxmn;
-	/*
-	 * Sets temperature upper and lower limits that generate an alert if
-	 * temperature is outside of the t_alert_mxmn range.
-	 * The upper 8 bits set the maximum value and the lower 8 bits set the
-	 * minimum value. Interrupt threshold limits are stored in
-	 * 2’s-complement format with 1°C resolution.
-	 * Use MAX17055_TALRTTH_REG(max, min) to setup the desired range,
-	 * TALRT_DISABLE to disable the alert.
-	 */
-	const uint16_t t_alert_mxmn;
-	/*
-	 * Sets reported state-of-charge upper and lower limits that generate
-	 * an alert if SOC is outside of the s_alert_mxmn range.
-	 * The upper 8 bits set the maximum value and the lower 8 bits set the
-	 * minimum value. Interrupt threshold limits are configurable with 1%
-	 * resolution.
-	 * Use MAX17055_SALRTTH_REG(max, min) to setup the desired range,
-	 * SALRT_DISABLE to disable the alert.
-	 */
-	const uint16_t s_alert_mxmn;
-	/*
-	 * Sets current upper and lower limits that generate an alert if
-	 * current is outside of the i_alert_mxmn range.
-	 * The upper 8 bits set the maximum value and the lower 8 bits set the
-	 * minimum value. Interrupt threshold limits are selectable with
-	 * 0.4mV/R SENSE resolution.
-	 * Use MAX17055_IALRTTH_REG(max, min) to setup the desired range,
-	 * IALRT_DISABLE to disable the alert.
-	 */
-	const uint16_t i_alert_mxmn;
-};
-
-/*
- * Return the battery/system's alert threshoulds that max17055 needs.
- */
-const struct max17055_alert_profile *max17055_get_alert_profile(void);
-#endif /* CONFIG_BATTERY_MAX17055_ALERT */
-#endif /* __CROS_EC_MAX17055_H */
diff --git a/driver/battery/mm8013.c b/driver/battery/mm8013.c
deleted file mode 100644
index 04503da2f5..0000000000
--- a/driver/battery/mm8013.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for MM8013.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "console.h"
-#include "i2c.h"
-#include "mm8013.h"
-#include "timer.h"
-#include "util.h"
-
-#define BATTERY_PACK_INFO_LENGTH 8
-
-/* MM8013 requires a 100us wait time after a read operation. */
-#define I2C_WAIT_TIME 100
-
-static int mm8013_read16(int offset, int *data)
-{
-	int rv;
-
-	*data = 0;
-	rv = i2c_read16(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS, offset, data);
-	usleep(I2C_WAIT_TIME);
-	if (rv)
-		return rv;
-	return EC_SUCCESS;
-}
-
-static int mm8013_read_block(int offset, uint8_t *data, int len)
-{
-	int rv;
-
-	rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS,
-			    offset, data, len);
-	usleep(I2C_WAIT_TIME);
-	if (rv)
-		return rv;
-	return EC_SUCCESS;
-}
-
-static int battery_flag(int *flag)
-{
-	return mm8013_read16(REG_FLAGS, flag);
-}
-
-static int battery_current(int *current)
-{
-	int16_t tmp;
-	int rv;
-
-	rv = mm8013_read_block(REG_AVERAGE_CURRENT,
-			(uint8_t *)&tmp, sizeof(int16_t));
-	if (rv)
-		return rv;
-	*current = tmp;
-
-	return EC_SUCCESS;
-}
-
-int battery_device_name(char *device_name, int buf_size)
-{
-	int rv;
-	char out_buf[BATTERY_PACK_INFO_LENGTH + 1];
-
-	rv = mm8013_read_block(REG_PRODUCT_INFORMATION,
-			(uint8_t *)out_buf, BATTERY_PACK_INFO_LENGTH);
-	if (rv)
-		return rv;
-
-	out_buf[BATTERY_PACK_INFO_LENGTH] = '\0';
-	strzcpy(device_name, out_buf, buf_size);
-
-	return EC_SUCCESS;
-}
-
-int battery_state_of_charge_abs(int *percent)
-{
-	return mm8013_read16(REG_STATE_OF_CHARGE, percent);
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	return mm8013_read16(REG_REMAINING_CAPACITY, capacity);
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	return mm8013_read16(REG_FULL_CHARGE_CAPACITY, capacity);
-}
-
-int battery_time_to_empty(int *minutes)
-{
-	return mm8013_read16(REG_AVERAGE_TIME_TO_EMPTY, minutes);
-}
-
-int battery_time_to_full(int *minutes)
-{
-	return mm8013_read16(REG_AVERAGE_TIME_TO_FULL, minutes);
-}
-
-int battery_cycle_count(int *count)
-{
-	return mm8013_read16(REG_CYCLE_COUNT, count);
-}
-
-int battery_design_capacity(int *capacity)
-{
-	return mm8013_read16(REG_DESIGN_CAPACITY, capacity);
-}
-
-int battery_time_at_rate(int rate, int *minutes)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_device_chemistry(char *dest, int size)
-{
-	strzcpy(dest, "<unkn>", size);
-
-	return EC_SUCCESS;
-}
-
-int battery_serial_number(int *serial)
-{
-	*serial = 0xFFFFFFFF;
-	return EC_SUCCESS;
-}
-
-int battery_manufacture_date(int *year, int *month, int *day)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = battery_get_info()->voltage_normal;
-
-	return EC_SUCCESS;
-}
-
-int battery_get_mode(int *mode)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_status(int *status)
-{
-	int rv;
-	int flag = 0;
-
-	*status = 0;
-
-	rv = battery_flag(&flag);
-	if (rv)
-		return rv;
-
-	if (flag & (MM8013_FLAG_OTC | MM8013_FLAG_OTD))
-		*status |= STATUS_OVERTEMP_ALARM;
-	if (flag & MM8013_FLAG_FC)
-		*status |= STATUS_FULLY_CHARGED;
-	if (flag & MM8013_FLAG_DSG)
-		*status |= STATUS_DISCHARGING;
-	if (flag & MM8013_FLAG_BATHI)
-		*status |= STATUS_OVERCHARGED_ALARM;
-
-	return EC_SUCCESS;
-}
-
-enum battery_present battery_is_present(void)
-{
-	int temp;
-
-	if (mm8013_read16(REG_TEMPERATURE, &temp))
-		return BP_NO;
-	return BP_YES;
-}
-
-void battery_get_params(struct batt_params *batt)
-{
-	struct batt_params batt_new = {0};
-	int flag = 0;
-
-	/*
-	 * Assuming the battery is responsive as long as
-	 * mm8013 finds battery is present.
-	 */
-	batt_new.is_present = battery_is_present();
-
-	if (batt_new.is_present == BP_YES)
-		batt_new.flags |= BATT_FLAG_RESPONSIVE;
-	else if (batt_new.is_present == BP_NO)
-		/* Battery is not present, gauge won't report useful info. */
-		goto batt_out;
-
-	if (mm8013_read16(REG_TEMPERATURE, &batt_new.temperature))
-		batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE;
-
-	if (mm8013_read16(REG_STATE_OF_CHARGE, &batt_new.state_of_charge))
-		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-
-	if (mm8013_read16(REG_VOLTAGE, &batt_new.voltage))
-		batt_new.flags |= BATT_FLAG_BAD_VOLTAGE;
-
-	if (battery_current(&batt_new.current))
-		batt_new.flags |= BATT_FLAG_BAD_CURRENT;
-
-	batt_new.desired_voltage = battery_get_info()->voltage_max;
-	batt_new.desired_current = BATTERY_DESIRED_CHARGING_CURRENT;
-
-	if (battery_remaining_capacity(&batt_new.remaining_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_REMAINING_CAPACITY;
-
-	if (battery_full_charge_capacity(&batt_new.full_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_FULL_CAPACITY;
-
-	if (battery_status(&batt_new.status))
-		batt_new.flags |= BATT_FLAG_BAD_STATUS;
-
-	if (!battery_flag(&flag) && (flag & MM8013_FLAG_CHG))
-		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
-
-batt_out:
-	/* Update visible battery parameters */
-	memcpy(batt, &batt_new, sizeof(*batt));
-}
-
-#ifdef CONFIG_CMD_PWR_AVG
-int battery_get_avg_current(void)
-{
-	/* TODO(crbug.com/752320) implement this */
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-
-int battery_get_avg_voltage(void)
-{
-	/* TODO(crbug.com/752320) implement this */
-	return -EC_ERROR_UNIMPLEMENTED;
-}
-#endif /* CONFIG_CMD_PWR_AVG */
-
-/* Wait until battery is totally stable. */
-int battery_wait_for_stable(void)
-{
-	/* TODO(phoenixshen): Implement this function. */
-	return EC_SUCCESS;
-}
diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h
deleted file mode 100644
index 2ffaca7b5d..0000000000
--- a/driver/battery/mm8013.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for MM8013.
- */
-
-#ifndef __CROS_EC_MM8013_H
-#define __CROS_EC_MM8013_H
-
-#define MM8013_ADDR_FLAGS           0x55
-
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_FULL_CHARGE_CAPACITY    0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_AVERAGE_TIME_TO_EMPTY   0x16
-#define REG_AVERAGE_TIME_TO_FULL    0x18
-#define REG_STATE_OF_CHARGE         0x2c
-#define REG_CYCLE_COUNT             0x2a
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_PRODUCT_INFORMATION     0x64
-
-/* Over Temperature in charge */
-#define MM8013_FLAG_OTC             BIT(15)
-/* Over Temperature in discharge */
-#define MM8013_FLAG_OTD             BIT(14)
-/* Over-charge */
-#define MM8013_FLAG_BATHI           BIT(13)
-/* Full Charge */
-#define MM8013_FLAG_FC              BIT(9)
-/* Charge allowed */
-#define MM8013_FLAG_CHG             BIT(8)
-/* Discharge */
-#define MM8013_FLAG_DSG             BIT(0)
-
-
-#endif /* __CROS_EC_MM8013_H */
diff --git a/driver/battery/smart.c b/driver/battery/smart.c
deleted file mode 100644
index 3704618e36..0000000000
--- a/driver/battery/smart.c
+++ /dev/null
@@ -1,695 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery driver.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "console.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr);
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-#define BATTERY_NO_RESPONSE_TIMEOUT	(1000*MSEC)
-
-static int fake_state_of_charge = -1;
-static int fake_temperature = -1;
-
-static int battery_supports_pec(void)
-{
-	static int supports_pec = -1;
-
-	if (!IS_ENABLED(CONFIG_SMBUS_PEC))
-		return 0;
-
-	if (supports_pec < 0) {
-		int spec_info;
-		int rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				    SB_SPECIFICATION_INFO, &spec_info);
-		/* failed, assuming not support and try again later */
-		if (rv)
-			return 0;
-
-		supports_pec = (BATTERY_SPEC_VERSION(spec_info) ==
-				BATTERY_SPEC_VER_1_1_WITH_PEC);
-		CPRINTS("battery supports pec: %d", supports_pec);
-	}
-	return supports_pec;
-}
-
-test_mockable int sb_read(int cmd, int *param)
-{
-	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-	/*
-	 * Some batteries would wake up after cut-off if we talk to it.
-	 */
-	if (battery_is_cut_off())
-		return EC_RES_ACCESS_DENIED;
-#endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
-
-	return i2c_read16(I2C_PORT_BATTERY, addr_flags, cmd, param);
-}
-
-test_mockable int sb_write(int cmd, int param)
-{
-	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-	/*
-	 * Some batteries would wake up after cut-off if we talk to it.
-	 */
-	if (battery_is_cut_off())
-		return EC_RES_ACCESS_DENIED;
-#endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
-
-	return i2c_write16(I2C_PORT_BATTERY, addr_flags, cmd, param);
-}
-
-int sb_read_string(int offset, uint8_t *data, int len)
-{
-	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-	/*
-	 * Some batteries would wake up after cut-off if we talk to it.
-	 */
-	if (battery_is_cut_off())
-		return EC_RES_ACCESS_DENIED;
-#endif
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
-
-	return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data, len);
-}
-
-int sb_read_mfgacc(int cmd, int block, uint8_t *data, int len)
-{
-	int rv;
-
-	/*
-	 * First two bytes returned from read are command sent hence read
-	 * doesn't yield anything if the length is less than 3 bytes.
-	 */
-	if (len < 3)
-		return EC_ERROR_INVAL;
-
-	/* Send manufacturer access command */
-	rv = sb_write(SB_MANUFACTURER_ACCESS, cmd);
-	if (rv)
-		return rv;
-
-	/*
-	 * Read data on the register block.
-	 * First two bytes returned are command sent,
-	 * rest are actual data LSB to MSB.
-	 */
-	rv = sb_read_string(block, data, len);
-	if (rv)
-		return rv;
-	if ((data[0] | data[1] << 8) != cmd)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-int sb_write_block(int reg, const uint8_t *val, int len)
-{
-	uint16_t addr_flags = BATTERY_ADDR_FLAGS;
-
-#ifdef CONFIG_BATTERY_CUT_OFF
-	/*
-	 * Some batteries would wake up after cut-off if we talk to it.
-	 */
-	if (battery_is_cut_off())
-		return EC_RES_ACCESS_DENIED;
-#endif
-
-	if (battery_supports_pec())
-		addr_flags |= I2C_FLAG_PEC;
-
-	/* TODO: implement smbus_write_block. */
-	return i2c_write_block(I2C_PORT_BATTERY, addr_flags, reg, val, len);
-}
-
-int battery_get_mode(int *mode)
-{
-	return sb_read(SB_BATTERY_MODE, mode);
-}
-
-/**
- * Force battery to mAh mode (instead of 10mW mode) for reporting capacity.
- *
- * @return non-zero if error.
- */
-
-static int battery_force_mah_mode(void)
-{
-	int val, rv;
-	rv = battery_get_mode(&val);
-	if (rv)
-		return rv;
-
-	if (val & MODE_CAPACITY)
-		rv = sb_write(SB_BATTERY_MODE, val & ~MODE_CAPACITY);
-
-	return rv;
-}
-
-int battery_state_of_charge_abs(int *percent)
-{
-	return sb_read(SB_ABSOLUTE_STATE_OF_CHARGE, percent);
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	int rv = battery_force_mah_mode();
-	if (rv)
-		return rv;
-
-	return sb_read(SB_REMAINING_CAPACITY, capacity);
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	int rv = battery_force_mah_mode();
-	if (rv)
-		return rv;
-
-	return sb_read(SB_FULL_CHARGE_CAPACITY, capacity);
-}
-
-int battery_time_to_empty(int *minutes)
-{
-	return sb_read(SB_AVERAGE_TIME_TO_EMPTY, minutes);
-}
-
-int battery_run_time_to_empty(int *minutes)
-{
-	return sb_read(SB_RUN_TIME_TO_EMPTY, minutes);
-}
-
-int battery_time_to_full(int *minutes)
-{
-	return sb_read(SB_AVERAGE_TIME_TO_FULL, minutes);
-}
-
-/* Read battery status */
-int battery_status(int *status)
-{
-	return sb_read(SB_BATTERY_STATUS, status);
-}
-
-/* Battery charge cycle count */
-int battery_cycle_count(int *count)
-{
-	return sb_read(SB_CYCLE_COUNT, count);
-}
-
-int battery_design_capacity(int *capacity)
-{
-	int rv = battery_force_mah_mode();
-	if (rv)
-		return rv;
-
-	return sb_read(SB_DESIGN_CAPACITY, capacity);
-}
-
-/* Designed battery output voltage
- * unit: mV
- */
-int battery_design_voltage(int *voltage)
-{
-	return sb_read(SB_DESIGN_VOLTAGE, voltage);
-}
-
-/* Read serial number */
-int battery_serial_number(int *serial)
-{
-	return sb_read(SB_SERIAL_NUMBER, serial);
-}
-
-test_mockable int battery_time_at_rate(int rate, int *minutes)
-{
-	int rv;
-	int ok, time;
-	int loop, cmd, output_sign;
-
-	if (rate == 0) {
-		*minutes = 0;
-		return EC_ERROR_INVAL;
-	}
-
-	rv = sb_write(SB_AT_RATE, rate);
-	if (rv)
-		return rv;
-	loop = 5;
-	while (loop--) {
-		rv = sb_read(SB_AT_RATE_OK, &ok);
-		if (rv)
-			return rv;
-		if (ok) {
-			if (rate > 0) {
-				cmd = SB_AT_RATE_TIME_TO_FULL;
-				output_sign = -1;
-			} else {
-				cmd = SB_AT_RATE_TIME_TO_EMPTY;
-				output_sign = 1;
-			}
-			rv = sb_read(cmd, &time);
-			if (rv)
-				return rv;
-
-			*minutes = (time == 0xffff) ? 0 : output_sign * time;
-			return EC_SUCCESS;
-		} else {
-			/* wait 10ms for AT_RATE_OK */
-			msleep(10);
-		}
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-test_mockable int battery_manufacture_date(int *year, int *month, int *day)
-{
-	int rv;
-	int ymd;
-
-	rv = sb_read(SB_MANUFACTURE_DATE, &ymd);
-	if (rv)
-		return rv;
-
-	/* battery date format:
-	 * ymd = day + month * 32 + (year - 1980) * 512
-	 */
-	*year  = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >>
-		  MANUFACTURE_DATE_YEAR_SHIFT) + MANUFACTURE_DATE_YEAR_OFFSET;
-	*month = (ymd & MANUFACTURE_DATE_MONTH_MASK) >>
-		 MANUFACTURE_DATE_MONTH_SHIFT;
-	*day   = (ymd & MANUFACTURE_DATE_DAY_MASK) >>
-		 MANUFACTURE_DATE_DAY_SHIFT;
-
-	return EC_SUCCESS;
-}
-
-int get_battery_manufacturer_name(char *dest, int size)
-{
-	return sb_read_string(SB_MANUFACTURER_NAME, dest, size);
-}
-
-/* Read device name */
-test_mockable int battery_device_name(char *dest, int size)
-{
-	return sb_read_string(SB_DEVICE_NAME, dest, size);
-}
-
-/* Read battery type/chemistry */
-test_mockable int battery_device_chemistry(char *dest, int size)
-{
-	return sb_read_string(SB_DEVICE_CHEMISTRY, dest, size);
-}
-
-int battery_get_avg_current(void)
-{
-	int current;
-
-	/* This is a signed 16-bit value. */
-	sb_read(SB_AVERAGE_CURRENT, &current);
-	return (int16_t)current;
-}
-
-#ifdef CONFIG_CMD_PWR_AVG
-/*
- * Technically returns only the instantaneous reading, but tests showed that
- * for the majority of charge states above 3% this varies by less than 40mV
- * every minute, so we accept the inaccuracy here.
- */
-int battery_get_avg_voltage(void)
-{
-	int voltage = -EC_ERROR_UNKNOWN;
-
-	sb_read(SB_VOLTAGE, &voltage);
-	return voltage;
-}
-#endif /* CONFIG_CMD_PWR_AVG */
-
-static void apply_fake_state_of_charge(struct batt_params *batt)
-{
-	int full;
-
-	if (fake_state_of_charge < 0)
-		return;
-
-	if (batt->flags & BATT_FLAG_BAD_FULL_CAPACITY)
-		battery_design_capacity(&full);
-	else
-		full = batt->full_capacity;
-
-	batt->state_of_charge = fake_state_of_charge;
-	batt->remaining_capacity = full * fake_state_of_charge / 100;
-	battery_compensate_params(batt);
-	batt->flags &= ~BATT_FLAG_BAD_STATE_OF_CHARGE;
-	batt->flags &= ~BATT_FLAG_BAD_REMAINING_CAPACITY;
-}
-
-void battery_get_params(struct batt_params *batt)
-{
-	struct batt_params batt_new = {0};
-	int v;
-
-	if (sb_read(SB_TEMPERATURE, &batt_new.temperature)
-			&& fake_temperature < 0)
-		batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE;
-
-	/* If temperature is faked, override with faked data */
-	if (fake_temperature >= 0)
-		batt_new.temperature = fake_temperature;
-
-	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge)
-	    && fake_state_of_charge < 0)
-		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
-
-	if (sb_read(SB_VOLTAGE, &batt_new.voltage))
-		batt_new.flags |= BATT_FLAG_BAD_VOLTAGE;
-
-	/* This is a signed 16-bit value. */
-	if (sb_read(SB_CURRENT, &v))
-		batt_new.flags |= BATT_FLAG_BAD_CURRENT;
-	else
-		batt_new.current = (int16_t)v;
-
-	if (sb_read(SB_AVERAGE_CURRENT, &v))
-		batt_new.flags |= BATT_FLAG_BAD_AVERAGE_CURRENT;
-	if (sb_read(SB_CHARGING_VOLTAGE, &batt_new.desired_voltage))
-		batt_new.flags |= BATT_FLAG_BAD_DESIRED_VOLTAGE;
-
-	if (sb_read(SB_CHARGING_CURRENT, &batt_new.desired_current))
-		batt_new.flags |= BATT_FLAG_BAD_DESIRED_CURRENT;
-
-	if (battery_remaining_capacity(&batt_new.remaining_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_REMAINING_CAPACITY;
-
-	if (battery_full_charge_capacity(&batt_new.full_capacity))
-		batt_new.flags |= BATT_FLAG_BAD_FULL_CAPACITY;
-
-	if (battery_status(&batt_new.status))
-		batt_new.flags |= BATT_FLAG_BAD_STATUS;
-
-	/* If any of those reads worked, the battery is responsive */
-	if ((batt_new.flags & BATT_FLAG_BAD_ANY) != BATT_FLAG_BAD_ANY)
-		batt_new.flags |= BATT_FLAG_RESPONSIVE;
-
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-	if (battery_imbalance_mv() > CONFIG_BATTERY_MAX_IMBALANCE_MV)
-		batt_new.flags |= BATT_FLAG_IMBALANCED_CELL;
-#endif
-
-#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	defined(CONFIG_BATTERY_PRESENT_GPIO)
-	/* Hardware can tell us for certain */
-	batt_new.is_present = battery_is_present();
-#else
-	/* No hardware test, so we only know it's there if it responds */
-	if (batt_new.flags & BATT_FLAG_RESPONSIVE)
-		batt_new.is_present = BP_YES;
-	else
-		batt_new.is_present = BP_NOT_SURE;
-#endif
-
-	/*
-	 * Charging allowed if both desired voltage and current are nonzero
-	 * and battery isn't full (and we read them all correctly).
-	 */
-	if (!(batt_new.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT |
-				BATT_FLAG_BAD_STATE_OF_CHARGE)) &&
-#ifdef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-		/*
-		 * TODO (crosbug.com/p/29467): remove this workaround
-		 * for dead battery that requests no voltage/current
-		 */
-		((batt_new.desired_voltage &&
-			batt_new.desired_current &&
-			batt_new.state_of_charge < BATTERY_LEVEL_FULL) ||
-		(batt_new.desired_voltage == 0 &&
-			batt_new.desired_current == 0 &&
-			batt_new.state_of_charge == 0)))
-#else
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
-	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
-#endif
-		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
-	else
-		/* Force both to zero */
-		batt_new.desired_voltage = batt_new.desired_current = 0;
-
-#ifdef HAS_TASK_HOSTCMD
-	/* if there is no host, we don't care about compensation */
-	battery_compensate_params(&batt_new);
-	board_battery_compensate_params(&batt_new);
-#endif
-
-	if (IS_ENABLED(CONFIG_CMD_BATTFAKE))
-		apply_fake_state_of_charge(&batt_new);
-
-	/* Update visible battery parameters */
-	memcpy(batt, &batt_new, sizeof(*batt));
-}
-
-/* Wait until battery is totally stable */
-int battery_wait_for_stable(void)
-{
-	int status;
-	uint64_t wait_timeout = get_time().val + BATTERY_NO_RESPONSE_TIMEOUT;
-
-	CPRINTS("Wait for battery stabilized during %d",
-			 BATTERY_NO_RESPONSE_TIMEOUT);
-	while (get_time().val < wait_timeout) {
-		/* Starting pinging battery */
-		if (battery_status(&status) == EC_SUCCESS) {
-			/* Battery is stable */
-			CPRINTS("battery responded with status %x", status);
-			return EC_SUCCESS;
-		}
-		msleep(25); /* clock stretching could hold 25ms */
-	}
-	CPRINTS("battery not responding");
-	return EC_ERROR_NOT_POWERED;
-}
-
-#if defined(CONFIG_CMD_BATTFAKE)
-static int command_battfake(int argc, char **argv)
-{
-	char *e;
-	int v;
-
-	if (argc == 2) {
-		v = strtoi(argv[1], &e, 0);
-		if (*e || v < -1 || v > 100)
-			return EC_ERROR_PARAM1;
-
-		fake_state_of_charge = v;
-	}
-
-	if (fake_state_of_charge >= 0)
-		ccprintf("Fake batt %d%%\n", fake_state_of_charge);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(battfake, command_battfake,
-			"percent (-1 = use real level)",
-			"Set fake battery level");
-
-static int command_batttempfake(int argc, char **argv)
-{
-	char *e;
-	int t;
-
-	if (argc == 2) {
-		t = strtoi(argv[1], &e, 0);
-		if (*e || t < -1 || t > 5000)
-			return EC_ERROR_PARAM1;
-
-		fake_temperature = t;
-	}
-
-	if (fake_temperature >= 0)
-		ccprintf("Fake batt temperature %d.%d K\n",
-			 fake_temperature / 10, fake_temperature % 10);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(batttempfake, command_batttempfake,
-			"temperature (-1 = use real temperature)",
-			"Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)");
-#endif
-
-#ifdef CONFIG_CMD_BATT_MFG_ACCESS
-static int command_batt_mfg_access_read(int argc, char **argv)
-{
-	char *e;
-	uint8_t data[32];
-	int cmd, block, len = 6;
-	int rv;
-
-	if (argc < 3 || argc > 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	cmd = strtoi(argv[1], &e, 0);
-	if (*e || cmd < 0)
-		return EC_ERROR_PARAM1;
-
-	block = strtoi(argv[2], &e, 0);
-	if (*e || block < 0)
-		return EC_ERROR_PARAM2;
-
-	if (argc > 3) {
-		len = strtoi(argv[3], &e, 0);
-		len += 2;
-		if (*e || len < 3 || len > sizeof(data))
-			return EC_ERROR_PARAM3;
-	}
-
-	rv = sb_read_mfgacc(cmd, block, data, len);
-	if (rv)
-		return rv;
-
-	ccprintf("data[MSB->LSB]=0x");
-	do {
-		len--;
-		ccprintf("%02x ", data[len]);
-	} while (len > 2);
-	ccprintf("\n");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(battmfgacc, command_batt_mfg_access_read,
-			"cmd block | len",
-			"Read battery manufacture access data");
-#endif /* CONFIG_CMD_BATT_MFG_ACCESS */
-
-/*****************************************************************************/
-/* Smart battery pass-through
- */
-#ifdef CONFIG_SB_PASSTHROUGH
-static enum ec_status
-host_command_sb_read_word(struct host_cmd_handler_args *args)
-{
-	int rv;
-	int val;
-	const struct ec_params_sb_rd *p = args->params;
-	struct ec_response_sb_rd_word *r = args->response;
-
-	if (p->reg > 0x1c)
-		return EC_RES_INVALID_PARAM;
-	rv = sb_read(p->reg, &val);
-	if (rv)
-		return EC_RES_ERROR;
-
-	r->value = val;
-	args->response_size = sizeof(struct ec_response_sb_rd_word);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD,
-		     host_command_sb_read_word,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_write_word(struct host_cmd_handler_args *args)
-{
-	int rv;
-	const struct ec_params_sb_wr_word *p = args->params;
-
-	if (p->reg > 0x1c)
-		return EC_RES_INVALID_PARAM;
-	rv = sb_write(p->reg, p->value);
-	if (rv)
-		return EC_RES_ERROR;
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD,
-		     host_command_sb_write_word,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_read_block(struct host_cmd_handler_args *args)
-{
-	int rv;
-	const struct ec_params_sb_rd *p = args->params;
-	struct ec_response_sb_rd_block *r = args->response;
-
-	if ((p->reg != SB_MANUFACTURER_NAME) &&
-	    (p->reg != SB_DEVICE_NAME) &&
-	    (p->reg != SB_DEVICE_CHEMISTRY) &&
-	    (p->reg != SB_MANUFACTURER_DATA))
-		return EC_RES_INVALID_PARAM;
-	rv = sb_read_string(p->reg, r->data, 32);
-	if (rv)
-		return EC_RES_ERROR;
-
-	args->response_size = sizeof(struct ec_response_sb_rd_block);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK,
-		     host_command_sb_read_block,
-		     EC_VER_MASK(0));
-
-static enum ec_status
-host_command_sb_write_block(struct host_cmd_handler_args *args)
-{
-	/* Not implemented */
-	return EC_RES_INVALID_COMMAND;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK,
-		     host_command_sb_write_block,
-		     EC_VER_MASK(0));
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-test_mockable int sb_i2c_test_read(int cmd, int *param)
-{
-	char chemistry[sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY) + 1];
-	int rv;
-
-	if (cmd == SB_DEVICE_CHEMISTRY) {
-		rv = battery_device_chemistry(chemistry,
-			sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY));
-		if (rv)
-			return rv;
-		if (strcasecmp(chemistry, CONFIG_BATTERY_DEVICE_CHEMISTRY))
-			return EC_ERROR_UNKNOWN;
-
-		*param = EC_SUCCESS;
-		return EC_SUCCESS;
-	}
-
-
-	return sb_read(cmd, param);
-}
-
-struct i2c_stress_test_dev battery_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = SB_DEVICE_CHEMISTRY,
-		.read_val = EC_SUCCESS,
-		.write_reg = SB_AT_RATE,
-	},
-	.i2c_read_dev = &sb_i2c_test_read,
-	.i2c_write_dev = &sb_write,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_BATTERY */
diff --git a/driver/bc12/max14637.c b/driver/bc12/max14637.c
deleted file mode 100644
index b2e734e1c0..0000000000
--- a/driver/bc12/max14637.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * MAX14637 USB BC 1.2 Charger Detector driver.
- *
- * NOTE: The driver assumes that CHG_AL_N and SW_OPEN are not connected,
- * therefore the value of CHG_DET indicates whether the source is NOT a
- * low-power standard downstream port (SDP).  In order to use higher currents,
- * the system will have to charge ramp.
- */
-
-#include "max14637.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "power/cannonlake.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-/**
- * Returns true if the charger detect pin is activated.
- *
- * @parm cfg driver for chip to read the charger detect pin for.
- * @return 1 if charger detect is activated (high when active high or
- *	low with active low), otherwise 0.
- */
-static int is_chg_det_activated(const struct max14637_config_t * const cfg)
-{
-	return !!gpio_get_level(cfg->chg_det_pin) ^
-		!!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW);
-}
-#endif
-
-/**
- * Activates the Chip Enable GPIO based on the enabled value.
- *
- * @param cfg driver for chip that will set chip enable gpio.
- * @param enable 1 to activate gpio (high for active high and low for active
- *	low).
- */
-static void activate_chip_enable(
-	const struct max14637_config_t * const cfg, const int enable)
-{
-	gpio_set_level(
-		cfg->chip_enable_pin,
-		!!enable ^ !!(cfg->flags & MAX14637_FLAGS_ENABLE_ACTIVE_LOW));
-}
-
-/**
- * Update BC1.2 detected status to charge manager.
- *
- * @param port: The Type-C port where VBUS is present.
- */
-static void update_bc12_status_to_charger_manager(const int port)
-{
-	const struct max14637_config_t * const cfg = &max14637_config[port];
-	struct charge_port_info new_chg;
-
-	new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	/*
-	 * The driver assumes that CHG_AL_N and SW_OPEN are not connected,
-	 * therefore an activated CHG_DET indicates whether the source is NOT a
-	 * low-power standard downstream port (SDP). The system will have to
-	 * ramp the current to determine the limit.  The Type-C spec prohibits
-	 * proprietary methods now, therefore 1500mA is the max.
-	 */
-	new_chg.current = is_chg_det_activated(cfg) ? USB_CHARGER_MAX_CURR_MA :
-						      500;
-#else
-	/*
-	 * If the board doesn't support charge ramping, then assume the lowest
-	 * denominator; that is assume the charger detected is a weak dedicated
-	 * charging port (DCP) which can only supply 500mA.
-	 */
-	new_chg.current = 500;
-#endif /* !defined(CONFIG_CHARGE_RAMP_SW && CONFIG_CHARGE_RAMP_HW) */
-
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, &new_chg);
-}
-
-/**
- * Perform BC1.2 detection.
- *
- * @param port: The Type-C port where VBUS is present.
- */
-static void bc12_detect(const int port)
-{
-	const struct max14637_config_t * const cfg = &max14637_config[port];
-
-	/*
-	 * Enable the IC to begin detection and connect switches if
-	 * necessary. This is only necessary if the port power role is a
-	 * sink. If the power role is a source then just keep the max14637
-	 * powered on so that data switches are close. Note that the gpio enable
-	 * for this chip is active by default. In order to trigger bc1.2
-	 * detection, the chip enable must be driven low, then high again so the
-	 * chip will start bc1.2 client side detection. Add a 100 msec delay to
-	 * avoid collision with a device that might be doing bc1.2 client side
-	 * detection.
-	 */
-	msleep(100);
-	activate_chip_enable(cfg, 0);
-	msleep(CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS);
-	activate_chip_enable(cfg, 1);
-
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	/*
-	 * Apple or TomTom charger detection can take as long as 600ms.  Wait a
-	 * little bit longer for margin.
-	 */
-	msleep(630);
-#endif /* !defined(CONFIG_CHARGE_RAMP_SW && CONFIG_CHARGE_RAMP_HW) */
-}
-
-/**
- * If VBUS is present and port power role is sink, then trigger bc1.2 client
- * detection. If VBUS is not present then update charge manager. Note that both
- * chip_enable and VBUS must be active for the IC to be powered up. Chip enable
- * is kept enabled by default so that bc1.2 client detection is not triggered
- * when the port power role is source.
- *
- * @param port: Which USB Type-C port to examine.
- */
-static void detect_or_power_down_ic(const int port)
-{
-	int vbus_present;
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	vbus_present = tcpm_check_vbus_level(port, VBUS_PRESENT);
-#else
-	vbus_present = pd_snk_is_vbus_provided(port);
-#endif /* !defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) */
-
-	if (vbus_present) {
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
-		/* Turn on the 5V rail to allow the chip to be powered. */
-		power_5v_enable(task_get_current(), 1);
-#endif
-		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			bc12_detect(port);
-			update_bc12_status_to_charger_manager(port);
-		}
-	} else {
-		/* Let charge manager know there's no more charge available. */
-		charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, NULL);
-		/*
-		 * If latest attached charger is PD Adapter then it would be
-		 * detected as DCP and data switch of USB2.0 would be open which
-		 * prevents USB 2.0 data path from working later. As a result,
-		 * bc12_detect() is called again here and SCP would be detected
-		 * due to D+/D- are NC (open) if nothing is attached then data
-		 * switch of USB2.0 can be kept close from now on.
-		 */
-		bc12_detect(port);
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
-		/* Issue a request to turn off the rail. */
-		power_5v_enable(task_get_current(), 0);
-#endif
-	}
-}
-
-static void max14637_usb_charger_task(const int port)
-{
-	uint32_t evt;
-	const struct max14637_config_t * const cfg = &max14637_config[port];
-
-	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	/*
-	 * Have chip enable active as default state so data switches are closed
-	 * and bc1.2 client side detection is not activated when the port power
-	 * role is a source.
-	 */
-	activate_chip_enable(cfg, 1);
-	/* Check whether bc1.2 client mode detection needs to be triggered */
-	detect_or_power_down_ic(port);
-
-	while (1) {
-		evt = task_wait_event(-1);
-
-		if (evt & USB_CHG_EVENT_VBUS)
-			detect_or_power_down_ic(port);
-	}
-}
-
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-static int max14637_ramp_allowed(int supplier)
-{
-	/*
-	 * Due to the limitations in the application of the MAX14637, we
-	 * don't quite know exactly what we're plugged into.  Therefore,
-	 * the supplier type will be CHARGE_SUPPLIER_OTHER.
-	 */
-	return supplier == CHARGE_SUPPLIER_OTHER;
-}
-
-static int max14637_ramp_max(int supplier, int sup_curr)
-{
-	/* Use the current limit that was decided by the MAX14637. */
-	if (supplier == CHARGE_SUPPLIER_OTHER)
-		return sup_curr;
-	else
-		return 500;
-}
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-
-/* Called on AP S5 -> S3  and S3/S0iX -> S0 transition */
-static void bc12_chipset_startup(void)
-{
-	int port;
-
-	/*
-	 * For each port, trigger a new USB_CHG_EVENT_VBUS event to handle cases
-	 * where there was no change in VBUS following an AP resume/startup
-	 * event. If a legacy charger is connected to the port, then VBUS will
-	 * not drop even during the USB PD hard reset.
-	 */
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_VBUS);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bc12_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, bc12_chipset_startup, HOOK_PRIO_DEFAULT);
-
-const struct bc12_drv max14637_drv = {
-	.usb_charger_task = max14637_usb_charger_task,
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	.ramp_allowed = max14637_ramp_allowed,
-	.ramp_max = max14637_ramp_max,
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &max14637_drv,
-	},
-};
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h
deleted file mode 100644
index 2b18bc222b..0000000000
--- a/driver/bc12/max14637.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX14637 USB BC 1.2 Charger Detector driver definitions */
-
-#include "gpio.h"
-
-#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW		BIT(0)
-#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW		BIT(1)
-
-struct max14637_config_t {
-	/*
-	 * Enable signal to BC 1.2. Can be active high or low depending on
-	 * MAX14637_FLAGS_ENABLE_ACTIVE_LOW flag bit.
-	 */
-	enum gpio_signal chip_enable_pin;
-	/*
-	 * Charger detect signal from BC 1.2 chip. Can be active high or low
-	 * depending on MAX14637_FLAGS_CHG_DET_ACTIVE_LOW flag bit.
-	 */
-	enum gpio_signal chg_det_pin;
-	/* Configuration flags with prefix MAX14637_FLAGS. */
-	int flags;
-};
-
-/*
- * Array that contains boards-specific configuration for BC 1.2 charging chips.
- */
-extern const struct max14637_config_t
-				max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-extern const struct bc12_drv max14637_drv;
diff --git a/driver/bc12/mt6360.c b/driver/bc12/mt6360.c
deleted file mode 100644
index 50aa4d0e45..0000000000
--- a/driver/bc12/mt6360.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charger.h"
-#include "charge_manager.h"
-#include "console.h"
-#include "crc8.h"
-#include "mt6360.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) \
-	cprints(CC_USBCHARGE, "%s " format, "MT6360", ## args)
-
-static enum ec_error_list mt6360_read8(int reg, int *val)
-{
-	return i2c_read8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
-}
-
-static enum ec_error_list mt6360_write8(int reg, int val)
-{
-	return i2c_write8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
-}
-
-static int mt6360_update_bits(int reg, int mask, int val)
-{
-	int rv;
-	int reg_val;
-
-	rv = mt6360_read8(reg, &reg_val);
-	if (rv)
-		return rv;
-	reg_val &= ~mask;
-	reg_val |= (mask & val);
-	rv = mt6360_write8(reg, reg_val);
-	return rv;
-}
-
-static inline int mt6360_set_bit(int reg, int mask)
-{
-	return mt6360_update_bits(reg, mask, mask);
-}
-
-static inline int mt6360_clr_bit(int reg, int mask)
-{
-	return mt6360_update_bits(reg, mask, 0x00);
-}
-
-static int mt6360_get_bc12_device_type(void)
-{
-	int reg;
-
-	if (mt6360_read8(MT6360_REG_USB_STATUS_1, &reg))
-		return CHARGE_SUPPLIER_NONE;
-
-	switch (reg & MT6360_MASK_USB_STATUS) {
-	case MT6360_MASK_SDP:
-		CPRINTS("BC12 SDP");
-		return CHARGE_SUPPLIER_BC12_SDP;
-	case MT6360_MASK_CDP:
-		CPRINTS("BC12 CDP");
-		return CHARGE_SUPPLIER_BC12_CDP;
-	case MT6360_MASK_DCP:
-		CPRINTS("BC12 DCP");
-		return CHARGE_SUPPLIER_BC12_DCP;
-	default:
-		CPRINTS("BC12 NONE");
-		return CHARGE_SUPPLIER_NONE;
-	}
-}
-
-static int mt6360_get_bc12_ilim(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-	case CHARGE_SUPPLIER_BC12_CDP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_SDP:
-	default:
-		return USB_CHARGER_MIN_CURR_MA;
-	}
-}
-
-static int mt6360_enable_bc12_detection(int en)
-{
-	int rv;
-
-	if (en) {
-#ifdef CONFIG_MT6360_BC12_GPIO
-		gpio_set_level(GPIO_BC12_DET_EN, 1);
-#endif
-		return mt6360_set_bit(MT6360_REG_DEVICE_TYPE,
-				      MT6360_MASK_USBCHGEN);
-	}
-
-	rv = mt6360_clr_bit(MT6360_REG_DEVICE_TYPE, MT6360_MASK_USBCHGEN);
-#ifdef CONFIG_MT6360_BC12_GPIO
-	gpio_set_level(GPIO_BC12_DET_EN, 0);
-#endif
-	return rv;
-}
-
-static void mt6360_update_charge_manager(int port,
-					 enum charge_supplier new_bc12_type)
-{
-	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
-
-	if (new_bc12_type != current_bc12_type) {
-		if (current_bc12_type >= 0)
-			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
-
-		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
-			struct charge_port_info chg = {
-				.current = mt6360_get_bc12_ilim(new_bc12_type),
-				.voltage = USB_CHARGER_VOLTAGE_MV,
-			};
-
-			charge_manager_update_charge(new_bc12_type, port, &chg);
-		}
-
-		current_bc12_type = new_bc12_type;
-	}
-}
-
-static void mt6360_handle_bc12_irq(int port)
-{
-	int reg;
-
-	mt6360_read8(MT6360_REG_DPDMIRQ, &reg);
-
-	if (reg & MT6360_MASK_DPDMIRQ_ATTACH) {
-		/* Check vbus again to avoid timing issue */
-		if (pd_snk_is_vbus_provided(port))
-			mt6360_update_charge_manager(
-					port, mt6360_get_bc12_device_type());
-		else
-			mt6360_update_charge_manager(
-					0, CHARGE_SUPPLIER_NONE);
-	}
-
-	/* write clear */
-	mt6360_write8(MT6360_REG_DPDMIRQ, reg);
-}
-
-static void mt6360_usb_charger_task(const int port)
-{
-	mt6360_clr_bit(MT6360_REG_DPDM_MASK1,
-		       MT6360_REG_DPDM_MASK1_CHGDET_DONEI_M);
-	mt6360_enable_bc12_detection(0);
-
-	while (1) {
-		uint32_t evt = task_wait_event(-1);
-
-		/* vbus change, start bc12 detection */
-		if (evt & USB_CHG_EVENT_VBUS) {
-			if (pd_snk_is_vbus_provided(port))
-				mt6360_enable_bc12_detection(1);
-			else
-				mt6360_update_charge_manager(
-						0, CHARGE_SUPPLIER_NONE);
-		}
-
-		/* detection done, update charge_manager and stop detection */
-		if (evt & USB_CHG_EVENT_BC12) {
-			mt6360_handle_bc12_irq(port);
-			mt6360_enable_bc12_detection(0);
-		}
-	}
-}
-
-/* Regulator: LDO & BUCK */
-static int mt6360_regulator_write8(uint8_t addr, int reg, int val)
-{
-	/*
-	 * Note: The checksum from I2C_FLAG_PEC happens to be correct because
-	 * length == 1 -> the high 3 bits of the offset byte is 0.
-	 */
-	return i2c_write8(mt6360_config.i2c_port,
-			  addr | I2C_FLAG_PEC, reg, val);
-}
-
-static int mt6360_regulator_read8(int addr, int reg, int *val)
-{
-	int rv;
-	uint8_t crc = 0, real_crc;
-	uint8_t out[3] = {(addr << 1) | 1, reg};
-
-	rv = i2c_read16(mt6360_config.i2c_port, addr, reg, val);
-	if (rv)
-		return rv;
-
-	real_crc = (*val >> 8) & 0xFF;
-	*val &= 0xFF;
-	out[2] = *val;
-	crc = cros_crc8(out, ARRAY_SIZE(out));
-
-	if (crc != real_crc)
-		return EC_ERROR_CRC;
-
-	return EC_SUCCESS;
-}
-
-static int mt6360_regulator_update_bits(int addr, int reg, int mask, int val)
-{
-	int rv;
-	int reg_val = 0;
-
-	rv = mt6360_regulator_read8(addr, reg, &reg_val);
-	if (rv)
-		return rv;
-	reg_val &= ~mask;
-	reg_val |= (mask & val);
-	rv = mt6360_regulator_write8(addr, reg, reg_val);
-	return rv;
-}
-
-struct mt6360_regulator_data {
-	const char *name;
-	const uint16_t *ldo_vosel_table;
-	uint16_t ldo_vosel_table_len;
-	uint8_t addr;
-	uint8_t reg_en_ctrl2;
-	uint8_t reg_ctrl3;
-	uint8_t mask_vosel;
-	uint8_t shift_vosel;
-	uint8_t mask_vocal;
-};
-
-static const uint16_t MT6360_LDO3_VOSEL_TABLE[16] = {
-	[0x4] = 1800,
-	[0xA] = 2900,
-	[0xB] = 3000,
-	[0xD] = 3300,
-};
-
-static const uint16_t MT6360_LDO5_VOSEL_TABLE[8] = {
-	[0x2] = 2900,
-	[0x3] = 3000,
-	[0x5] = 3300,
-};
-
-static const uint16_t MT6360_LDO6_VOSEL_TABLE[16] = {
-	[0x0] = 500,
-	[0x1] = 600,
-	[0x2] = 700,
-	[0x3] = 800,
-	[0x4] = 900,
-	[0x5] = 1000,
-	[0x6] = 1100,
-	[0x7] = 1200,
-	[0x8] = 1300,
-	[0x9] = 1400,
-	[0xA] = 1500,
-	[0xB] = 1600,
-	[0xC] = 1700,
-	[0xD] = 1800,
-	[0xE] = 1900,
-	[0xF] = 2000,
-};
-
-/* LDO7 VOSEL table is the same as LDO6's. */
-static const uint16_t *const MT6360_LDO7_VOSEL_TABLE = MT6360_LDO6_VOSEL_TABLE;
-static const uint16_t MT6360_LDO7_VOSEL_TABLE_SIZE =
-	ARRAY_SIZE(MT6360_LDO6_VOSEL_TABLE);
-
-static const
-struct mt6360_regulator_data regulator_data[MT6360_REGULATOR_COUNT] = {
-	[MT6360_LDO3] = {
-		.name = "mt6360_ldo3",
-		.ldo_vosel_table = MT6360_LDO3_VOSEL_TABLE,
-		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO3_VOSEL_TABLE),
-		.addr = MT6360_LDO_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_LDO3_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_LDO3_CTRL3,
-		.mask_vosel = MT6360_MASK_LDO3_VOSEL,
-		.shift_vosel = MT6360_MASK_LDO3_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_LDO3_VOCAL,
-	},
-	[MT6360_LDO5] = {
-		.name = "mt6360_ldo5",
-		.ldo_vosel_table = MT6360_LDO5_VOSEL_TABLE,
-		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO5_VOSEL_TABLE),
-		.addr = MT6360_LDO_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_LDO5_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_LDO5_CTRL3,
-		.mask_vosel = MT6360_MASK_LDO5_VOSEL,
-		.shift_vosel = MT6360_MASK_LDO5_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_LDO5_VOCAL,
-	},
-	[MT6360_LDO6] = {
-		.name = "mt6360_ldo6",
-		.ldo_vosel_table = MT6360_LDO6_VOSEL_TABLE,
-		.ldo_vosel_table_len = ARRAY_SIZE(MT6360_LDO6_VOSEL_TABLE),
-		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_LDO6_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_LDO6_CTRL3,
-		.mask_vosel = MT6360_MASK_LDO6_VOSEL,
-		.shift_vosel = MT6360_MASK_LDO6_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_LDO6_VOCAL,
-	},
-	[MT6360_LDO7] = {
-		.name = "mt6360_ldo7",
-		.ldo_vosel_table = MT6360_LDO7_VOSEL_TABLE,
-		.ldo_vosel_table_len = MT6360_LDO7_VOSEL_TABLE_SIZE,
-		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_LDO7_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_LDO7_CTRL3,
-		.mask_vosel = MT6360_MASK_LDO7_VOSEL,
-		.shift_vosel = MT6360_MASK_LDO7_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_LDO7_VOCAL,
-	},
-	[MT6360_BUCK1] = {
-		.name = "mt6360_buck1",
-		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_BUCK1_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_BUCK1_VOSEL,
-		.mask_vosel = MT6360_MASK_BUCK1_VOSEL,
-		.shift_vosel = MT6360_MASK_BUCK1_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_BUCK1_VOCAL,
-	},
-	[MT6360_BUCK2] = {
-		.name = "mt6360_buck2",
-		.addr = MT6360_PMIC_I2C_ADDR_FLAGS,
-		.reg_en_ctrl2 = MT6360_REG_BUCK2_EN_CTRL2,
-		.reg_ctrl3 = MT6360_REG_BUCK2_VOSEL,
-		.mask_vosel = MT6360_MASK_BUCK2_VOSEL,
-		.shift_vosel = MT6360_MASK_BUCK2_VOSEL_SHIFT,
-		.mask_vocal = MT6360_MASK_BUCK2_VOCAL,
-	},
-};
-
-static bool is_buck_regulator(const struct mt6360_regulator_data *data)
-{
-	/* There's no ldo_vosel_table, it's a buck. */
-	return !(data->ldo_vosel_table);
-}
-
-int mt6360_regulator_get_info(enum mt6360_regulator_id id, char *name,
-			      uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	int i;
-	int cnt = 0;
-	const struct mt6360_regulator_data *data;
-
-	if (id >= MT6360_REGULATOR_COUNT)
-		return EC_ERROR_INVAL;
-	data = &regulator_data[id];
-
-	strzcpy(name, data->name, EC_REGULATOR_NAME_MAX_LEN);
-
-	if (is_buck_regulator(data)) {
-		for (i = 0; i < MT6360_BUCK_VOSEL_MAX_STEP; ++i) {
-			int mv = MT6360_BUCK_VOSEL_MIN +
-				 i * MT6360_BUCK_VOSEL_STEP_MV;
-
-			if (cnt < EC_REGULATOR_VOLTAGE_MAX_COUNT)
-				voltages_mv[cnt++] = mv;
-			else
-				CPRINTS("%s voltage info overflow: %d-%d",
-					data->name, mv, MT6360_BUCK_VOSEL_MAX);
-		}
-	} else {
-		/* It's a LDO */
-		for (i = 0; i < data->ldo_vosel_table_len; i++) {
-			int mv = data->ldo_vosel_table[i];
-
-			if (!mv)
-				continue;
-			if (cnt < EC_REGULATOR_VOLTAGE_MAX_COUNT)
-				voltages_mv[cnt++] = mv;
-			else
-				CPRINTS("%s voltage info overflow: %d",
-					data->name, mv);
-		}
-	}
-
-	*num_voltages = cnt;
-	return EC_SUCCESS;
-}
-
-int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable)
-{
-	const struct mt6360_regulator_data *data;
-
-	if (id >= MT6360_REGULATOR_COUNT)
-		return EC_ERROR_INVAL;
-	data = &regulator_data[id];
-
-	if (enable)
-		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
-			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
-			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN);
-	else
-		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
-			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
-			MT6360_MASK_RGL_SW_OP_EN);
-}
-
-int mt6360_regulator_is_enabled(enum mt6360_regulator_id id, uint8_t *enabled)
-{
-	int rv;
-	int value;
-	const struct mt6360_regulator_data *data;
-
-	if (id >= MT6360_REGULATOR_COUNT)
-		return EC_ERROR_INVAL;
-	data = &regulator_data[id];
-
-	rv = mt6360_regulator_read8(data->addr, data->reg_en_ctrl2, &value);
-	if (rv) {
-		CPRINTS("Error reading %s enabled: %d", data->name, rv);
-		return rv;
-	}
-	*enabled = !!(value & MT6360_MASK_RGL_SW_EN);
-	return EC_SUCCESS;
-}
-
-int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
-				 int max_mv)
-{
-	int i;
-	const struct mt6360_regulator_data *data;
-
-	if (id >= MT6360_REGULATOR_COUNT)
-		return EC_ERROR_INVAL;
-	data = &regulator_data[id];
-
-	if (is_buck_regulator(data)) {
-		int mv;
-		int step;
-
-		if (max_mv < MT6360_BUCK_VOSEL_MIN)
-			goto error;
-
-		if (min_mv > MT6360_BUCK_VOSEL_MAX)
-			goto error;
-
-		mv = DIV_ROUND_UP((min_mv + max_mv) / 2,
-				  MT6360_BUCK_VOSEL_STEP_MV) *
-		     MT6360_BUCK_VOSEL_STEP_MV;
-		mv = MIN(MAX(mv, MT6360_BUCK_VOSEL_MIN), MT6360_BUCK_VOSEL_MAX);
-
-		step = (mv - MT6360_BUCK_VOSEL_MIN) / MT6360_BUCK_VOSEL_STEP_MV;
-
-		return mt6360_regulator_update_bits(data->addr,
-						    data->reg_ctrl3,
-						    data->mask_vosel, step);
-	}
-
-	/* It's a LDO. */
-	for (i = 0; i < data->ldo_vosel_table_len; i++) {
-		int mv = data->ldo_vosel_table[i];
-		int step = 0;
-
-		if (!mv)
-			continue;
-		if (mv + MT6360_LDO_VOCAL_STEP_MV * MT6360_LDO_VOCAL_MAX_STEP <
-		    min_mv)
-			continue;
-		if (mv < min_mv)
-			step = DIV_ROUND_UP(min_mv - mv,
-					    MT6360_LDO_VOCAL_STEP_MV);
-		if (mv + step * MT6360_LDO_VOCAL_STEP_MV > max_mv)
-			continue;
-		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_ctrl3,
-			data->mask_vosel | data->mask_vocal,
-			(i << data->shift_vosel) | step);
-	}
-
-error:
-	CPRINTS("%s voltage %d - %d out of range", data->name, min_mv, max_mv);
-	return EC_ERROR_INVAL;
-}
-
-int mt6360_regulator_get_voltage(enum mt6360_regulator_id id, int *voltage_mv)
-{
-	int value;
-	int rv;
-	const struct mt6360_regulator_data *data;
-
-	if (id >= MT6360_REGULATOR_COUNT)
-		return EC_ERROR_INVAL;
-	data = &regulator_data[id];
-
-	rv = mt6360_regulator_read8(data->addr, data->reg_ctrl3, &value);
-	if (rv) {
-		CPRINTS("Error reading %s ctrl3: %d", data->name, rv);
-		return rv;
-	}
-
-	/* BUCK */
-	if (is_buck_regulator(data)) {
-		*voltage_mv = MT6360_BUCK_VOSEL_MIN +
-			      value * MT6360_BUCK_VOSEL_STEP_MV;
-		return EC_SUCCESS;
-	}
-
-	/* LDO */
-	*voltage_mv = data->ldo_vosel_table[(value & data->mask_vosel) >>
-					    data->shift_vosel];
-	if (*voltage_mv == 0) {
-		CPRINTS("Unknown %s voltage value: %d", data->name, value);
-		return EC_ERROR_INVAL;
-	}
-	*voltage_mv +=
-		MIN(MT6360_LDO_VOCAL_MAX_STEP, value & data->mask_vocal) *
-		MT6360_LDO_VOCAL_STEP_MV;
-	return EC_SUCCESS;
-}
-
-/* RGB LED */
-void mt6360_led_init(void)
-{
-	/* Enable LED1 software mode */
-	mt6360_set_bit(MT6360_REG_RGB_EN, MT6360_ISINK1_CHRIND_EN_SEL);
-}
-DECLARE_HOOK(HOOK_INIT, mt6360_led_init, HOOK_PRIO_DEFAULT);
-
-int mt6360_led_enable(enum mt6360_led_id led_id, int enable)
-{
-	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT))
-		return EC_ERROR_INVAL;
-
-	if (enable)
-		return mt6360_set_bit(MT6360_REG_RGB_EN,
-				      MT6360_MASK_ISINK_EN(led_id));
-	return mt6360_clr_bit(MT6360_REG_RGB_EN, MT6360_MASK_ISINK_EN(led_id));
-}
-
-int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness)
-{
-	int val;
-
-	if (!IN_RANGE(led_id, 0, MT6360_LED_COUNT))
-		return EC_ERROR_INVAL;
-	if (!IN_RANGE(brightness, 0, 16))
-		return EC_ERROR_INVAL;
-
-	RETURN_ERROR(mt6360_read8(MT6360_REG_RGB_ISINK(led_id), &val));
-	val &= ~MT6360_MASK_CUR_SEL;
-	val |= brightness;
-
-	return mt6360_write8(MT6360_REG_RGB_ISINK(led_id), val);
-}
-
-const struct bc12_drv mt6360_drv = {
-	.usb_charger_task = mt6360_usb_charger_task,
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &mt6360_drv,
-	},
-};
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/mt6360.h b/driver/bc12/mt6360.h
deleted file mode 100644
index e23a2623ed..0000000000
--- a/driver/bc12/mt6360.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MT6360_H
-
-#include "bc12/mt6360_public.h"
-
-#define MT6360_IRQ_MASK 0x0C
-
-#define MT6360_REG_DEVICE_TYPE 0x22
-#define MT6360_MASK_USBCHGEN BIT(7)
-
-#define MT6360_REG_USB_STATUS_1 0x27
-#define MT6360_MASK_USB_STATUS 0x70
-#define MT6360_MASK_SDP 0x20
-#define MT6360_MASK_DCP 0x40
-#define MT6360_MASK_CDP 0x50
-
-#define MT6360_REG_RGB_EN 0x80
-#define MT6360_MASK_ISINK_EN(x) BIT(7 - (x))
-#define MT6360_ISINK1_CHRIND_EN_SEL BIT(3)
-
-#define MT6360_REG_RGB_ISINK(x) (0x81 + (x))
-#define MT6360_MASK_CUR_SEL 0xF
-
-#define MT6360_REG_DPDMIRQ 0xD6
-#define MT6360_MASK_DPDMIRQ_ATTACH BIT(0)
-#define MT6360_MASK_DPDMIRQ_DETACH BIT(1)
-
-#define MT6360_REG_DPDM_MASK1 0xF6
-#define MT6360_REG_DPDM_MASK1_CHGDET_DONEI_M BIT(0)
-
-#define MT6360_REG_LDO3_EN_CTRL2 0x05
-
-#define MT6360_REG_LDO3_CTRL3 0x09
-#define MT6360_MASK_LDO3_VOSEL 0xF0
-#define MT6360_MASK_LDO3_VOSEL_SHIFT 4
-#define MT6360_MASK_LDO3_VOCAL 0x0F
-
-#define MT6360_REG_LDO5_EN_CTRL2 0x0B
-
-#define MT6360_REG_LDO5_CTRL3 0x0F
-#define MT6360_MASK_LDO5_VOSEL 0x70
-#define MT6360_MASK_LDO5_VOSEL_SHIFT 4
-#define MT6360_MASK_LDO5_VOCAL 0x0F
-
-#define MT6360_REG_LDO6_EN_CTRL2 0x37
-
-#define MT6360_REG_LDO6_CTRL3 0x3B
-#define MT6360_MASK_LDO6_VOSEL 0xF0
-#define MT6360_MASK_LDO6_VOSEL_SHIFT 4
-#define MT6360_MASK_LDO6_VOCAL 0x0F
-
-#define MT6360_REG_LDO7_EN_CTRL2 0x31
-
-#define MT6360_REG_LDO7_CTRL3 0x35
-#define MT6360_MASK_LDO7_VOSEL 0xF0
-#define MT6360_MASK_LDO7_VOSEL_SHIFT 4
-#define MT6360_MASK_LDO7_VOCAL 0x0F
-
-#define MT6360_REG_BUCK1_EN_CTRL2 0x17
-
-#define MT6360_REG_BUCK1_VOSEL 0x10
-#define MT6360_MASK_BUCK1_VOSEL 0xFF
-#define MT6360_MASK_BUCK1_VOSEL_SHIFT 0
-#define MT6360_MASK_BUCK1_VOCAL 0x0
-
-#define MT6360_REG_BUCK2_EN_CTRL2 0x26
-
-#define MT6360_REG_BUCK2_VOSEL 0x20
-#define MT6360_MASK_BUCK2_VOSEL 0xFF
-#define MT6360_MASK_BUCK2_VOSEL_SHIFT 0
-#define MT6360_MASK_BUCK2_VOCAL 0x0
-
-/* This is same for LDO{1,2,3,5,6,7}_EN_CTRL2, BUCK{1,2}_EN_CTRL2 */
-#define MT6360_MASK_RGL_SW_OP_EN BIT(7)
-#define MT6360_MASK_RGL_SW_EN BIT(6)
-
-#define MT6360_LDO_VOCAL_STEP_MV 10
-#define MT6360_LDO_VOCAL_MAX_STEP 10
-
-#define MT6360_BUCK_VOSEL_STEP_MV 5
-#define MT6360_BUCK_VOSEL_MAX_STEP 200
-#define MT6360_BUCK_VOSEL_MIN 300
-#define MT6360_BUCK_VOSEL_MAX    \
-	(MT6360_BUCK_VOSEL_MIN + \
-	 MT6360_BUCK_VOSEL_STEP_MV * MT6360_BUCK_VOSEL_MAX_STEP)
-
-#endif /* __CROS_EC_MT6360_H */
diff --git a/driver/bc12/pi3usb9201.c b/driver/bc12/pi3usb9201.c
deleted file mode 100644
index 2a9986f823..0000000000
--- a/driver/bc12/pi3usb9201.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PI3USB9201 USB BC 1.2 Charger Detector driver. */
-
-#include "pi3usb9201.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-enum pi3usb9201_client_sts {
-	CHG_OTHER = 0,
-	CHG_2_4A,
-	CHG_2_0A,
-	CHG_1_0A,
-	CHG_RESERVED,
-	CHG_CDP,
-	CHG_SDP,
-	CHG_DCP,
-};
-
-struct bc12_status {
-	enum charge_supplier supplier;
-	int current_limit;
-};
-
-/* Used to store last BC1.2 detection result */
-static enum charge_supplier bc12_supplier[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * The USB Type-C specification limits the maximum amount of current from BC 1.2
- * suppliers to 1.5A.  Technically, proprietary methods are not allowed, but we
- * will continue to allow those.
- */
-static const struct bc12_status bc12_chg_limits[] = {
-	[CHG_OTHER] = {CHARGE_SUPPLIER_OTHER, 500},
-	[CHG_2_4A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_2_0A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_1_0A] = {CHARGE_SUPPLIER_PROPRIETARY, 1000},
-	[CHG_RESERVED] = {CHARGE_SUPPLIER_NONE, 0},
-	[CHG_CDP] = {CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA},
-	[CHG_SDP] = {CHARGE_SUPPLIER_BC12_SDP, 500},
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	/*
-	 * If ramping is supported, then for DCP set the current limit to be the
-	 * max supported for the port by the board or 1.5A (whichever is lower).
-	 * Although, the BC 1.2 specification allows DCP suppliers to ramp to
-	 * much higher currents, the USB Type-C specification limits the
-	 * maximum current allowed for BC 1.2 suppliers to 1.5A.
-	 */
-	[CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA},
-#else
-	[CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, 500},
-#endif
-};
-
-static inline int raw_read8(int port, int offset, int *value)
-{
-	return i2c_read8(pi3usb9201_bc12_chips[port].i2c_port,
-			 pi3usb9201_bc12_chips[port].i2c_addr_flags,
-			 offset, value);
-}
-
-static int pi3usb9201_raw(int port, int reg, int mask, int val)
-{
-	/* Clear mask and then set val in i2c reg value */
-	return i2c_field_update8(pi3usb9201_bc12_chips[port].i2c_port,
-				 pi3usb9201_bc12_chips[port].i2c_addr_flags,
-				 reg, mask, val);
-}
-
-static int pi3usb9201_interrupt_mask(int port, int enable)
-{
-	return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_1,
-			  PI3USB9201_REG_CTRL_1_INT_MASK,
-			  enable);
-}
-
-static int pi3usb9201_bc12_detect_ctrl(int port, int enable)
-{
-	return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_2,
-			      PI3USB9201_REG_CTRL_2_START_DET,
-			      enable ? PI3USB9201_REG_CTRL_2_START_DET : 0);
-}
-
-static int pi3usb9201_set_mode(int port, int desired_mode)
-{
-	return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_1,
-			      PI3USB9201_REG_CTRL_1_MODE_MASK,
-			      desired_mode << PI3USB9201_REG_CTRL_1_MODE_SHIFT);
-}
-
-static int pi3usb9201_get_mode(int port, int *mode)
-{
-	int rv;
-
-	rv = raw_read8(port, PI3USB9201_REG_CTRL_1, mode);
-	if (rv)
-		return rv;
-
-	*mode &= PI3USB9201_REG_CTRL_1_MODE_MASK;
-	*mode >>= PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-
-	return EC_SUCCESS;
-}
-
-static int pi3usb9201_get_status(int port, int *client, int *host)
-{
-	int rv;
-	int status;
-
-	rv = raw_read8(port, PI3USB9201_REG_CLIENT_STS, &status);
-	if (client)
-		*client = status;
-	rv |= raw_read8(port, PI3USB9201_REG_HOST_STS, &status);
-	if (host)
-		*host = status;
-
-	return rv;
-}
-
-static void bc12_update_supplier(enum charge_supplier supplier, int port,
-			  struct charge_port_info *new_chg)
-{
-	/*
-	 * If most recent supplier type is not CHARGE_SUPPLIER_NONE, then the
-	 * charge manager table entry for that supplier type needs to be cleared
-	 * out.
-	 */
-	if (bc12_supplier[port] != CHARGE_SUPPLIER_NONE)
-		charge_manager_update_charge(bc12_supplier[port], port, NULL);
-	/* Now update the current supplier type */
-	bc12_supplier[port] = supplier;
-	/* If new supplier type != NONE, then notify charge manager */
-	if (supplier != CHARGE_SUPPLIER_NONE)
-		charge_manager_update_charge(supplier, port, new_chg);
-}
-
-static void bc12_update_charge_manager(int port, int client_status)
-{
-	struct charge_port_info new_chg;
-	enum charge_supplier supplier;
-	int bit_pos;
-
-	/* Set charge voltage to 5V */
-	new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
-
-	/*
-	 * Find set bit position. Note that this funciton is only called if a
-	 * bit was set in client_status, so bit_pos won't be negative.
-	 */
-	bit_pos = __builtin_ffs(client_status) - 1;
-
-	new_chg.current = bc12_chg_limits[bit_pos].current_limit;
-	supplier = bc12_chg_limits[bit_pos].supplier;
-
-	CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d",
-		port, client_status, new_chg.current, supplier);
-	/* bc1.2 is complete and start bit does not auto clear */
-	pi3usb9201_bc12_detect_ctrl(port, 0);
-	/* Inform charge manager of new supplier type and current limit */
-	bc12_update_supplier(supplier, port, &new_chg);
-}
-
-static int bc12_detect_start(int port)
-{
-	int rv;
-
-	/*
-	 * Read both status registers to ensure that all interrupt indications
-	 * are cleared prior to starting bc1.2 detection.
-	 */
-	pi3usb9201_get_status(port, NULL, NULL);
-
-	/* Put pi3usb9201 into client mode */
-	rv = pi3usb9201_set_mode(port, PI3USB9201_CLIENT_MODE);
-	if (rv)
-		return rv;
-	/* Have pi3usb9201 start bc1.2 detection */
-	rv = pi3usb9201_bc12_detect_ctrl(port, 1);
-	if (rv)
-		return rv;
-	/* Unmask interrupt to wake task when detection completes */
-	return pi3usb9201_interrupt_mask(port, 0);
-}
-
-static void bc12_power_down(int port)
-{
-	/* Put pi3usb9201 into its power down mode */
-	pi3usb9201_set_mode(port, PI3USB9201_POWER_DOWN);
-	/* The start bc1.2 bit does not auto clear */
-	pi3usb9201_bc12_detect_ctrl(port, 0);
-	/* Mask interrupts unitl next bc1.2 detection event */
-	pi3usb9201_interrupt_mask(port, 1);
-	/*
-	 * Let charge manager know there's no more charge available for the
-	 * supplier type that was most recently detected.
-	 */
-	bc12_update_supplier(CHARGE_SUPPLIER_NONE, port, NULL);
-
-	/* There's nothing else to do if the part is always powered. */
-	if (pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED)
-		return;
-
-#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET)
-	/* Indicate PP5000_A rail is not required by USB_CHG task. */
-	power_5v_enable(task_get_current(), 0);
-#endif
-}
-
-static void bc12_power_up(int port)
-{
-	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL) &&
-	    IS_ENABLED(HAS_TASK_CHIPSET) &&
-	    !(pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED)) {
-		/* Turn on the 5V rail to allow the chip to be powered. */
-		power_5v_enable(task_get_current(), 1);
-		/*
-		 * Give the pi3usb9201 time so it's ready to receive i2c
-		 * messages
-		 */
-		msleep(1);
-	}
-
-	pi3usb9201_interrupt_mask(port, 1);
-}
-
-static void pi3usb9201_usb_charger_task(const int port)
-{
-	uint32_t evt;
-	int i;
-
-	/*
-	 * Set most recent bc1.2 detection supplier result to
-	 * CHARGE_SUPPLIER_NONE for all ports.
-	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		bc12_supplier[port] = CHARGE_SUPPLIER_NONE;
-
-	/*
-	 * The is no specific initialization required for the pi3usb9201 other
-	 * than enabling the interrupt mask.
-	 */
-	pi3usb9201_interrupt_mask(port, 1);
-
-	while (1) {
-		/* Wait for interrupt */
-		evt = task_wait_event(-1);
-
-		/* Interrupt from the Pericom chip, determine charger type */
-		if (evt & USB_CHG_EVENT_BC12) {
-			int client;
-			int host;
-			int rv;
-
-			rv = pi3usb9201_get_status(port, &client, &host);
-			if (!rv && client)
-				/*
-				 * Any bit set in client status register
-				 * indicates that BC1.2 detection has
-				 * completed.
-				 */
-				bc12_update_charge_manager(port, client);
-			if (!rv && host) {
-				/*
-				 * Switch to SDP after device is plugged in to
-				 * avoid noise (pulse on D-) causing USB
-				 * disconnect (b/156014140).
-				 */
-				if (host & PI3USB9201_REG_HOST_STS_DEV_PLUG)
-					pi3usb9201_set_mode(port,
-						PI3USB9201_SDP_HOST_MODE);
-				/*
-				 * Switch to CDP after device is unplugged so
-				 * we advertise higher power available for next
-				 * device.
-				 */
-				if (host & PI3USB9201_REG_HOST_STS_DEV_UNPLUG)
-					pi3usb9201_set_mode(port,
-						PI3USB9201_CDP_HOST_MODE);
-			}
-			/*
-			 * TODO(b/124061702): Use host status to allocate power
-			 * more intelligently.
-			 */
-		}
-
-#ifndef CONFIG_USB_PD_VBUS_DETECT_TCPC
-		if (evt & USB_CHG_EVENT_VBUS)
-			CPRINTS("VBUS p%d %d", port,
-				pd_snk_is_vbus_provided(port));
-#endif
-
-		if (evt & USB_CHG_EVENT_DR_UFP) {
-			bc12_power_up(port);
-			if (bc12_detect_start(port)) {
-				struct charge_port_info new_chg;
-
-				/*
-				 * VBUS is present, but starting bc1.2 detection
-				 * failed for some reason. So limit charge
-				 * current to default 500 mA for this case.
-				 */
-
-				new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
-				new_chg.current = USB_CHARGER_MIN_CURR_MA;
-				/* Save supplier type and notify chg manager */
-				bc12_update_supplier(CHARGE_SUPPLIER_OTHER,
-						     port, &new_chg);
-				CPRINTS("pi3usb9201[p%d]: bc1.2 failed use "
-					"defaults", port);
-			}
-		}
-
-		if (evt & USB_CHG_EVENT_DR_DFP) {
-			int mode;
-			int rv;
-
-			/*
-			 * Update the charge manager if bc1.2 client mode is
-			 * currently active.
-			 */
-			bc12_update_supplier(CHARGE_SUPPLIER_NONE, port, NULL);
-			/*
-			 * If the port is in DFP mode, then need to set mode to
-			 * CDP_HOST which will auto close D+/D- switches.
-			 */
-			bc12_power_up(port);
-			rv = pi3usb9201_get_mode(port, &mode);
-			if (!rv && (mode != PI3USB9201_CDP_HOST_MODE)) {
-				CPRINTS("pi3usb9201[p%d]: CDP_HOST mode", port);
-				/*
-				 * Read both status registers to ensure that all
-				 * interrupt indications are cleared prior to
-				 * starting DFP CDP host mode.
-				 */
-				pi3usb9201_get_status(port, NULL, NULL);
-				pi3usb9201_set_mode(port,
-						    PI3USB9201_CDP_HOST_MODE);
-				/*
-				 * Unmask interrupt to wake task when host
-				 * status changes.
-				 */
-				pi3usb9201_interrupt_mask(port, 0);
-			}
-		}
-
-		if (evt & USB_CHG_EVENT_CC_OPEN)
-			bc12_power_down(port);
-	}
-}
-
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-static int pi3usb9201_ramp_allowed(int supplier)
-{
-	/* Don't allow ramp if charge supplier is OTHER, SDP, or NONE */
-	return !(supplier == CHARGE_SUPPLIER_OTHER ||
-		 supplier == CHARGE_SUPPLIER_BC12_SDP ||
-		 supplier == CHARGE_SUPPLIER_NONE);
-}
-
-static int pi3usb9201_ramp_max(int supplier, int sup_curr)
-{
-	/*
-	 * Use the level from the bc12_chg_limits table above except for
-	 * proprietary or CDP and in those cases the charge current from the
-	 * charge manager is already set at the max determined by bc1.2
-	 * detection.
-	 */
-	switch (supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_CDP:
-	case CHARGE_SUPPLIER_PROPRIETARY:
-		return sup_curr;
-	case CHARGE_SUPPLIER_BC12_SDP:
-	default:
-		return 500;
-	}
-}
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-
-const struct bc12_drv pi3usb9201_drv = {
-	.usb_charger_task = pi3usb9201_usb_charger_task,
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	.ramp_allowed = pi3usb9201_ramp_allowed,
-	.ramp_max = pi3usb9201_ramp_max,
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &pi3usb9201_drv,
-	}
-};
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h
deleted file mode 100644
index 3163a3eebc..0000000000
--- a/driver/bc12/pi3usb9201.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PI3USB9201 USB BC 1.2 Charger Detector driver definitions */
-
-#ifndef __CROS_EC_DRIVER_BC12_PI3USB9201_H
-#define __CROS_EC_DRIVER_BC12_PI3USB9201_H
-
-#include "driver/bc12/pi3usb9201_public.h"
-
-#define PI3USB9201_REG_CTRL_1 0x0
-#define PI3USB9201_REG_CTRL_2 0x1
-#define PI3USB9201_REG_CLIENT_STS 0x2
-#define PI3USB9201_REG_HOST_STS 0x3
-
-/* Flags */
-#define PI3USB9201_ALWAYS_POWERED BIT(0)
-
-/* Control_1 regiter bit definitions */
-#define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
-#define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
-#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \
-					 PI3USB9201_REG_CTRL_1_MODE_SHIFT)
-
-/* Control_2 regiter bit definitions */
-#define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
-#define PI3USB9201_REG_CTRL_2_START_DET BIT(3)
-
-/* Host status register bit definitions */
-#define PI3USB9201_REG_HOST_STS_BC12_DET BIT(0)
-#define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1)
-#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2)
-
-enum pi3usb9201_mode {
-	PI3USB9201_POWER_DOWN,
-	PI3USB9201_SDP_HOST_MODE,
-	PI3USB9201_DCP_HOST_MODE,
-	PI3USB9201_CDP_HOST_MODE,
-	PI3USB9201_CLIENT_MODE,
-	PI3USB9201_RESERVED_1,
-	PI3USB9201_RESERVED_2,
-	PI3USB9201_USB_PATH_ON,
-};
-
-#endif /* __CROS_EC_DRIVER_BC12_PI3USB9201_H */
diff --git a/driver/bc12/pi3usb9281.c b/driver/bc12/pi3usb9281.c
deleted file mode 100644
index 9fc32e942b..0000000000
--- a/driver/bc12/pi3usb9281.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Pericom PI3USB3281 USB port switch driver.
- */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "pi3usb9281.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-
- /* Console output macros */
-#define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* I2C address */
-#define PI3USB9281_I2C_ADDR_FLAGS 0x25
-
-/* Delay values */
-#define PI3USB9281_SW_RESET_DELAY 20
-
-/* Wait after a charger is detected to debounce pin contact order */
-#define PI3USB9281_DETECT_DEBOUNCE_MS			1000
-#define PI3USB9281_RESET_DEBOUNCE_MS			100
-#define PI3USB9281_RESET_STARTUP_DELAY			(200 * MSEC)
-#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS	40
-
-/* Store the state of our USB data switches so that they can be restored. */
-static int usb_switch_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int pi3usb9281_reset(int port);
-static int pi3usb9281_get_interrupts(int port);
-
-static void select_chip(int port)
-{
-	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
-	ASSERT(port < CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
-
-	if (chip->mux_lock) {
-		mutex_lock(chip->mux_lock);
-		gpio_set_level(chip->mux_gpio, chip->mux_gpio_level);
-	}
-}
-
-static void unselect_chip(int port)
-{
-	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
-
-	if (chip->mux_lock)
-		/* Just release the mutex, no need to change the mux gpio */
-		mutex_unlock(chip->mux_lock);
-}
-
-static uint8_t pi3usb9281_do_read(int port, uint8_t reg, int with_lock)
-{
-	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
-	int res, val;
-
-	if (with_lock)
-		select_chip(port);
-
-	res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			reg, &val);
-
-	if (with_lock)
-		unselect_chip(port);
-
-	if (res)
-		return 0xee;
-
-	return val;
-}
-
-static uint8_t pi3usb9281_read_u(int port, uint8_t reg)
-{
-	return pi3usb9281_do_read(port, reg, 0);
-}
-
-static uint8_t pi3usb9281_read(int port, uint8_t reg)
-{
-	return pi3usb9281_do_read(port, reg, 1);
-}
-
-static int pi3usb9281_do_write(
-	int port, uint8_t reg, uint8_t val, int with_lock)
-{
-	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
-	int res;
-
-	if (with_lock)
-		select_chip(port);
-
-	res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			 reg, val);
-
-	if (with_lock)
-		unselect_chip(port);
-
-	if (res)
-		CPRINTS("PI3USB9281 I2C write failed");
-	return res;
-}
-
-static int pi3usb9281_write(int port, uint8_t reg, uint8_t val)
-{
-	return pi3usb9281_do_write(port, reg, val, 1);
-}
-
-/* Write control register, taking care to correctly set reserved bits. */
-static int pi3usb9281_do_write_ctrl(int port, uint8_t ctrl, int with_lock)
-{
-	return pi3usb9281_do_write(port, PI3USB9281_REG_CONTROL,
-				(ctrl & PI3USB9281_CTRL_MASK) |
-				PI3USB9281_CTRL_RSVD_1, with_lock);
-}
-
-static int pi3usb9281_write_ctrl(int port, uint8_t ctrl)
-{
-	return pi3usb9281_do_write_ctrl(port, ctrl, 1);
-}
-
-static int pi3usb9281_write_ctrl_u(int port, uint8_t ctrl)
-{
-	return pi3usb9281_do_write_ctrl(port, ctrl, 0);
-}
-
-/*
- * Mask particular interrupts (e.g. attach, detach, ovp, ocp).
- * 1: UnMask (enable). 0: Mask (disable)
- */
-static int pi3usb9281_set_interrupt_mask(int port, uint8_t mask)
-{
-	return pi3usb9281_write(port, PI3USB9281_REG_INT_MASK, ~mask);
-}
-
-static void pi3usb9281_init(int port)
-{
-	uint8_t dev_id;
-
-	dev_id = pi3usb9281_read(port, PI3USB9281_REG_DEV_ID);
-
-	if (dev_id != PI3USB9281_DEV_ID && dev_id != PI3USB9281_DEV_ID_A)
-		CPRINTS("PI3USB9281 invalid ID 0x%02x", dev_id);
-
-	pi3usb9281_reset(port);
-	pi3usb9281_enable_interrupts(port);
-}
-
-
-int pi3usb9281_enable_interrupts(int port)
-{
-	uint8_t ctrl;
-	pi3usb9281_set_interrupt_mask(port, PI3USB9281_INT_ATTACH_DETACH);
-	ctrl = pi3usb9281_read(port, PI3USB9281_REG_CONTROL);
-	if (ctrl == 0xee)
-		return EC_ERROR_UNKNOWN;
-
-	return pi3usb9281_write_ctrl(port, ctrl & ~PI3USB9281_CTRL_INT_DIS);
-}
-
-static int pi3usb9281_disable_interrupts(int port)
-{
-	uint8_t ctrl = pi3usb9281_read(port, PI3USB9281_REG_CONTROL);
-	int rv;
-
-	if (ctrl == 0xee)
-		return EC_ERROR_UNKNOWN;
-
-	rv = pi3usb9281_write_ctrl(port, ctrl | PI3USB9281_CTRL_INT_DIS);
-	pi3usb9281_get_interrupts(port);
-	return rv;
-}
-
-static int pi3usb9281_get_interrupts(int port)
-{
-	return pi3usb9281_read(port, PI3USB9281_REG_INT);
-}
-
-int pi3usb9281_get_device_type(int port)
-{
-	return pi3usb9281_read(port, PI3USB9281_REG_DEV_TYPE) & 0x77;
-}
-
-static int pi3usb9281_get_charger_status(int port)
-{
-	return pi3usb9281_read(port, PI3USB9281_REG_CHG_STATUS) & 0x1f;
-}
-
-static int pi3usb9281_get_ilim(int device_type, int charger_status)
-{
-	/* Limit USB port current. 500mA for not listed types. */
-	int current_limit_ma = 500;
-
-	/*
-	 * The USB Type-C specification limits the maximum amount of current
-	 * from BC 1.2 suppliers to 1.5A.  Technically, proprietary methods are
-	 * not allowed, but we will continue to allow those.
-	 */
-	if (charger_status & PI3USB9281_CHG_CAR_TYPE1 ||
-	    charger_status & PI3USB9281_CHG_CAR_TYPE2)
-		current_limit_ma = USB_CHARGER_MAX_CURR_MA;
-	else if (charger_status & PI3USB9281_CHG_APPLE_1A)
-		current_limit_ma = 1000;
-	else if (charger_status & PI3USB9281_CHG_APPLE_2A)
-		current_limit_ma = USB_CHARGER_MAX_CURR_MA;
-	else if (charger_status & PI3USB9281_CHG_APPLE_2_4A)
-		current_limit_ma = USB_CHARGER_MAX_CURR_MA;
-	else if (device_type & PI3USB9281_TYPE_CDP)
-		current_limit_ma = USB_CHARGER_MAX_CURR_MA;
-	else if (device_type & PI3USB9281_TYPE_DCP)
-		current_limit_ma = 500;
-
-	return current_limit_ma;
-}
-
-static int pi3usb9281_reset(int port)
-{
-	int rv = pi3usb9281_write(port, PI3USB9281_REG_RESET, 0x1);
-
-	if (!rv)
-		/* Reset takes ~15ms. Wait for 20ms to be safe. */
-		msleep(PI3USB9281_SW_RESET_DELAY);
-
-	return rv;
-}
-
-static int pi3usb9281_set_switch_manual(int port, int val)
-{
-	int res = EC_ERROR_UNKNOWN;
-	uint8_t ctrl;
-
-	select_chip(port);
-	ctrl = pi3usb9281_read_u(port, PI3USB9281_REG_CONTROL);
-
-	if (ctrl != 0xee) {
-		if (val)
-			ctrl &= ~PI3USB9281_CTRL_AUTO;
-		else
-			ctrl |= PI3USB9281_CTRL_AUTO;
-		res = pi3usb9281_write_ctrl_u(port, ctrl);
-	}
-
-	unselect_chip(port);
-	return res;
-}
-
-static int pi3usb9281_set_pins(int port, uint8_t val)
-{
-	return pi3usb9281_write(port, PI3USB9281_REG_MANUAL, val);
-}
-
-static int pi3usb9281_set_switches_impl(int port, int open)
-{
-	int res = EC_ERROR_UNKNOWN;
-	uint8_t ctrl;
-
-	select_chip(port);
-	ctrl = pi3usb9281_read_u(port, PI3USB9281_REG_CONTROL);
-
-	if (ctrl != 0xee) {
-		if (open)
-			ctrl &= ~PI3USB9281_CTRL_SWITCH_AUTO;
-		else
-			ctrl |= PI3USB9281_CTRL_SWITCH_AUTO;
-		res = pi3usb9281_write_ctrl_u(port, ctrl);
-	}
-
-	unselect_chip(port);
-	return res;
-}
-
-static void pi3usb9281_set_switches(int port, enum usb_switch setting)
-{
-	/* If switch is not changing then return */
-	if (setting == usb_switch_state[port])
-		return;
-	if (setting != USB_SWITCH_RESTORE)
-		usb_switch_state[port] = setting;
-	CPRINTS("USB MUX %d", usb_switch_state[port]);
-	task_set_event(TASK_ID_USB_CHG_P0 + port, USB_CHG_EVENT_MUX);
-}
-
-static int pc3usb9281_read_interrupt(int port)
-{
-	timestamp_t timeout;
-	timeout.val = get_time().val + PI3USB9281_RESET_STARTUP_DELAY;
-	do {
-		/* Read (& clear) possible attach & detach interrupt */
-		if (pi3usb9281_get_interrupts(port) &
-				PI3USB9281_INT_ATTACH_DETACH)
-			return EC_SUCCESS;
-		msleep(PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS);
-	} while (get_time().val < timeout.val);
-	return EC_ERROR_TIMEOUT;
-}
-
-/*
- * Handle BC 1.2 attach & detach event
- *
- * On attach, it resets pi3usb9281 for debounce. This reset should immediately
- * trigger another attach or detach interrupt. If other (unexpected) event is
- * observed, it forwards the event so that the caller can handle it.
- */
-static uint32_t bc12_detect(int port)
-{
-	int device_type, chg_status;
-	uint32_t evt = 0;
-
-	if (usb_charger_port_is_sourcing_vbus(port)) {
-		/* If we're sourcing VBUS then we're not charging */
-		device_type = PI3USB9281_TYPE_NONE;
-		chg_status = PI3USB9281_CHG_NONE;
-	} else {
-		/* Set device type */
-		device_type = pi3usb9281_get_device_type(port);
-		chg_status = pi3usb9281_get_charger_status(port);
-	}
-
-	/* Debounce pin plug order if we detect a charger */
-	if (device_type || PI3USB9281_CHG_STATUS_ANY(chg_status)) {
-		/* next operation might trigger a detach interrupt */
-		pi3usb9281_disable_interrupts(port);
-		/*
-		 * Ensure D+/D- are open before resetting
-		 * Note: we can't simply call pi3usb9281_set_switches() because
-		 * another task might override it and set the switches closed.
-		 */
-		pi3usb9281_set_switch_manual(port, 1);
-		pi3usb9281_set_pins(port, 0);
-
-		/* Delay to debounce pin attach order */
-		msleep(PI3USB9281_DETECT_DEBOUNCE_MS);
-
-		/*
-		 * Reset PI3USB9281 to refresh detection registers. After reset,
-		 * - Interrupt is globally disabled
-		 * - All interrupts are unmasked (=enabled)
-		 *
-		 * WARNING: This reset is acceptable for samus_pd,
-		 * but may not be acceptable for devices that have
-		 * an OTG / device mode, as we may be interrupting
-		 * the connection.
-		 */
-		pi3usb9281_reset(port);
-
-		/*
-		 * Restore data switch settings - switches return to
-		 * closed on reset until restored.
-		 */
-		pi3usb9281_set_switches(port, USB_SWITCH_RESTORE);
-
-		/*
-		 * Wait after reset, before re-enabling interrupt, so that
-		 * spurious interrupts from this port are ignored.
-		 */
-		msleep(PI3USB9281_RESET_DEBOUNCE_MS);
-
-		/* Re-enable interrupts */
-		pi3usb9281_enable_interrupts(port);
-
-		/*
-		 * Consume interrupt (expectedly) triggered by the reset.
-		 * If it's other event (e.g. VBUS), return immediately.
-		 */
-		evt = task_wait_event(PI3USB9281_RESET_DEBOUNCE_MS * MSEC);
-		if (evt & USB_CHG_EVENT_BC12)
-			evt &= ~USB_CHG_EVENT_BC12;
-		else if (evt & USB_CHG_EVENT_INTR)
-			evt &= ~USB_CHG_EVENT_INTR;
-		else
-			return evt;
-
-		/* Debounce is done. Registers should have trustworthy values */
-		device_type = PI3USB9281_TYPE_NONE;
-		chg_status = PI3USB9281_CHG_NONE;
-		if (pc3usb9281_read_interrupt(port) == EC_SUCCESS) {
-			device_type = pi3usb9281_get_device_type(port);
-			chg_status = pi3usb9281_get_charger_status(port);
-		}
-	}
-
-	/* Attachment: decode + update available charge */
-	if (device_type || PI3USB9281_CHG_STATUS_ANY(chg_status)) {
-		struct charge_port_info chg;
-		int type;
-
-		if (PI3USB9281_CHG_STATUS_ANY(chg_status))
-			type = CHARGE_SUPPLIER_PROPRIETARY;
-		else if (device_type & PI3USB9281_TYPE_CDP)
-			type = CHARGE_SUPPLIER_BC12_CDP;
-		else if (device_type & PI3USB9281_TYPE_DCP)
-			type = CHARGE_SUPPLIER_BC12_DCP;
-		else if (device_type & PI3USB9281_TYPE_SDP)
-			type = CHARGE_SUPPLIER_BC12_SDP;
-		else
-			type = CHARGE_SUPPLIER_OTHER;
-
-		chg.voltage = USB_CHARGER_VOLTAGE_MV;
-		chg.current = pi3usb9281_get_ilim(device_type, chg_status);
-		charge_manager_update_charge(type, port, &chg);
-	} else {
-		/* Detachment: update available charge to 0 */
-		usb_charger_reset_charge(port);
-	}
-
-	return evt;
-}
-
-static void pi3usb9281_usb_charger_task(const int port)
-{
-	uint32_t evt;
-
-	/* Initialize chip and enable interrupts */
-	pi3usb9281_init(port);
-
-	evt = bc12_detect(port);
-
-	while (1) {
-		/* Interrupt from the Pericom chip, determine charger type */
-		if (evt & USB_CHG_EVENT_BC12) {
-			/* Read interrupt register to clear on chip */
-			pi3usb9281_get_interrupts(port);
-			evt = bc12_detect(port);
-		} else if (evt & USB_CHG_EVENT_INTR) {
-			/* USB_CHG_EVENT_INTR & _BC12 are mutually exclusive */
-			/* Check the interrupt register, and clear on chip */
-			if (pi3usb9281_get_interrupts(port) &
-					PI3USB9281_INT_ATTACH_DETACH)
-				evt = bc12_detect(port);
-		}
-
-		if (evt & USB_CHG_EVENT_MUX)
-			pi3usb9281_set_switches_impl(
-					port, usb_switch_state[port]);
-
-		/*
-		 * Re-enable interrupts on pericom charger detector since the
-		 * chip may periodically reset itself, and come back up with
-		 * registers in default state. TODO(crosbug.com/p/33823): Fix
-		 * these unwanted resets.
-		 */
-		if (evt & USB_CHG_EVENT_VBUS) {
-			pi3usb9281_enable_interrupts(port);
-#ifndef CONFIG_USB_PD_VBUS_DETECT_TCPC
-			CPRINTS("VBUS p%d %d", port,
-				pd_snk_is_vbus_provided(port));
-#endif
-		}
-
-		evt = task_wait_event(-1);
-	}
-}
-
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-static int pi3usb9281_ramp_allowed(int supplier)
-{
-	return supplier == CHARGE_SUPPLIER_BC12_DCP ||
-	       supplier == CHARGE_SUPPLIER_BC12_SDP ||
-	       supplier == CHARGE_SUPPLIER_BC12_CDP ||
-	       supplier == CHARGE_SUPPLIER_PROPRIETARY;
-}
-
-static int pi3usb9281_ramp_max(int supplier, int sup_curr)
-{
-	switch (supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_SDP:
-		return 500;
-	case CHARGE_SUPPLIER_BC12_CDP:
-	case CHARGE_SUPPLIER_PROPRIETARY:
-		return sup_curr;
-	default:
-		return 500;
-	}
-}
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-
-const struct bc12_drv pi3usb9281_drv = {
-	.usb_charger_task = pi3usb9281_usb_charger_task,
-	.set_switches = pi3usb9281_set_switches,
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	.ramp_allowed = pi3usb9281_ramp_allowed,
-	.ramp_max = pi3usb9281_ramp_max,
-#endif /* CONFIG_CHARGE_RAMP_SW || CONFIG_CHARGE_RAMP_HW */
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &pi3usb9281_drv,
-	},
-};
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/pi3usb9281.h b/driver/bc12/pi3usb9281.h
deleted file mode 100644
index ca1828f49c..0000000000
--- a/driver/bc12/pi3usb9281.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Pericom PI3USB9281 USB port switch.
- */
-
-#ifndef __CROS_EC_PI3USB9281_H
-#define __CROS_EC_PI3USB9281_H
-
-#define PI3USB9281_REG_DEV_ID       0x01
-#define PI3USB9281_REG_CONTROL      0x02
-#define PI3USB9281_REG_INT          0x03
-#define PI3USB9281_REG_INT_MASK     0x05
-#define PI3USB9281_REG_DEV_TYPE     0x0a
-#define PI3USB9281_REG_CHG_STATUS   0x0e
-#define PI3USB9281_REG_MANUAL       0x13
-#define PI3USB9281_REG_RESET        0x1b
-#define PI3USB9281_REG_VBUS         0x1d
-
-#define PI3USB9281_DEV_ID           0x10
-#define PI3USB9281_DEV_ID_A         0x18
-
-#define PI3USB9281_CTRL_INT_DIS     BIT(0)
-#define PI3USB9281_CTRL_AUTO        BIT(2)
-#define PI3USB9281_CTRL_SWITCH_AUTO BIT(4)
-/* Bits 5 thru 7 are read X, write 0 */
-#define PI3USB9281_CTRL_MASK        0x1f
-/* Bits 1 and 3 are read 1, write 1 */
-#define PI3USB9281_CTRL_RSVD_1      0x0a
-
-#define PI3USB9281_PIN_MANUAL_VBUS  (3 << 0)
-#define PI3USB9281_PIN_MANUAL_DP    BIT(2)
-#define PI3USB9281_PIN_MANUAL_DM    BIT(5)
-
-#define PI3USB9281_INT_ATTACH       BIT(0)
-#define PI3USB9281_INT_DETACH       BIT(1)
-#define PI3USB9281_INT_OVP          BIT(5)
-#define PI3USB9281_INT_OCP          BIT(6)
-#define PI3USB9281_INT_OVP_OC       BIT(7)
-#define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \
-				      PI3USB9281_INT_DETACH)
-
-#define PI3USB9281_TYPE_NONE        0
-#define PI3USB9281_TYPE_MHL         BIT(0)
-#define PI3USB9281_TYPE_OTG         BIT(1)
-#define PI3USB9281_TYPE_SDP         BIT(2)
-#define PI3USB9281_TYPE_CAR         BIT(4)
-#define PI3USB9281_TYPE_CDP         BIT(5)
-#define PI3USB9281_TYPE_DCP         BIT(6)
-
-#define PI3USB9281_CHG_NONE         0
-#define PI3USB9281_CHG_CAR_TYPE1    BIT(1)
-#define PI3USB9281_CHG_CAR_TYPE2    (3 << 0)
-#define PI3USB9281_CHG_APPLE_1A     BIT(2)
-#define PI3USB9281_CHG_APPLE_2A     BIT(3)
-#define PI3USB9281_CHG_APPLE_2_4A   BIT(4)
-/* Check if charge status has any connection */
-#define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1)
-
-/* Define configuration of one pi3usb9281 part */
-struct pi3usb9281_config {
-	/* i2c port that chip resides on */
-	int i2c_port;
-	/* GPIO for chip selection in muxed configuration */
-	enum gpio_signal mux_gpio;
-	/* Logic level of mux_gpio to select chip */
-	int mux_gpio_level;
-	/* Mutex to lock access to mux gpio or NULL if no mux exists */
-	struct mutex *mux_lock;
-};
-
-/* Configuration struct defined at board level */
-extern struct pi3usb9281_config pi3usb9281_chips[];
-
-/* Enable interrupts. */
-int pi3usb9281_enable_interrupts(int port);
-
-/* Get the device type */
-int pi3usb9281_get_device_type(int port);
-
-extern const struct bc12_drv pi3usb9281_drv;
-#endif /* __CROS_EC_PI3USB9281_H */
diff --git a/driver/build.mk b/driver/build.mk
index 4ff201c5ce..4941ba3baa 100644
--- a/driver/build.mk
+++ b/driver/build.mk
@@ -80,9 +80,6 @@ driver-$(CONFIG_CHARGER_SM5803)+=charger/sm5803.o
 # DP Redrivers
 driver-$(CONFIG_DP_REDRIVER_TDP142)+=retimer/tdp142.o
 
-# Fingerprint Sensors
-include $(_driver_cur_dir)fingerprint/build.mk
-
 # I/O expander
 driver-$(CONFIG_IO_EXPANDER_CCGXXF)+=ioexpander/ccgxxf.o
 driver-$(CONFIG_IO_EXPANDER_IT8801)+=ioexpander/it8801.o
diff --git a/driver/charger/bd9995x.c b/driver/charger/bd9995x.c
deleted file mode 100644
index 6fd79b8d8f..0000000000
--- a/driver/charger/bd9995x.c
+++ /dev/null
@@ -1,1775 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ROHM BD9995X battery charger driver.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bd9995x.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "time.h"
-#include "util.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-
-#define OTPROM_LOAD_WAIT_RETRY	3
-
-#define BD9995X_CHARGE_PORT_COUNT 2
-
-/*
- * BC1.2 detection starts 100ms after VBUS/VCC attach and typically
- * completes 312ms after VBUS/VCC attach.
- */
-#define BC12_DETECT_US (312*MSEC)
-#define BD9995X_VSYS_PRECHARGE_OFFSET_MV 200
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-#ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-/*
- * Used in a check to determine if VBUS is within the
- * range of some VOLTAGE +/- VBUS_DELTA, where voltage
- * is measured in mV.
- */
-#define VBUS_DELTA 1000
-
-/* VBUS is debounced if it's stable for this length of time */
-#define VBUS_MSEC (100*MSEC)
-
-/* VBUS debouncing sample interval */
-#define VBUS_CHECK_MSEC (10*MSEC)
-
-/* Time to wait before VBUS debouncing begins */
-#define STABLE_TIMEOUT (500*MSEC)
-
-/* Maximum time to wait until VBUS is debounced */
-#define DEBOUNCE_TIMEOUT (500*MSEC)
-
-enum vstate {START, STABLE, DEBOUNCE};
-static enum vstate vbus_state;
-
-static int vbus_voltage;
-static uint64_t debounce_time;
-static uint64_t vbus_timeout;
-static int port_update;
-static int select_update;
-static int select_input_port_update;
-#endif
-
-/* Charger parameters */
-#define CHARGER_NAME    BD9995X_CHARGER_NAME
-#define CHARGE_V_MAX    19200
-#define CHARGE_V_MIN    3072
-#define CHARGE_V_STEP   16
-#define CHARGE_I_MAX    16320
-#define CHARGE_I_MIN    128
-#define CHARGE_I_OFF    0
-#define CHARGE_I_STEP   64
-#define INPUT_I_MAX     16352
-#define INPUT_I_MIN     512
-#define INPUT_I_STEP    32
-
-/* Charger parameters */
-static const struct charger_info bd9995x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
-	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
-	.input_current_step = INPUT_I_STEP,
-};
-
-/* Charge command code map */
-static enum bd9995x_command charger_map_cmd = BD9995X_INVALID_COMMAND;
-
-/* Mutex for active register set control. */
-static struct mutex bd9995x_map_mutex;
-
-/* Tracks the state of VSYS_PRIORITY */
-static int vsys_priority;
-/* Mutex for VIN_CTRL_SET register */
-static struct mutex bd9995x_vin_mutex;
-
-#ifdef HAS_TASK_USB_CHG
-/* USB switch */
-static enum usb_switch usb_switch_state[BD9995X_CHARGE_PORT_COUNT] = {
-	USB_SWITCH_DISCONNECT,
-	USB_SWITCH_DISCONNECT,
-};
-
-static enum ec_error_list bd9995x_set_current(int chgnum, int current);
-static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage);
-
-/*
- * The USB Type-C specification limits the maximum amount of current from BC 1.2
- * suppliers to 1.5A.  Technically, proprietary methods are not allowed, but we
- * will continue to allow those.
- */
-static int bd9995x_get_bc12_ilim(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_BC12_CDP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_DCP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_SDP:
-		return 900;
-	case CHARGE_SUPPLIER_OTHER:
-#ifdef CONFIG_CHARGE_RAMP_SW
-		return USB_CHARGER_MAX_CURR_MA;
-#else
-		/*
-		 * Setting the higher limit of current may result in an
-		 * anti-collapse hence limiting the current to 1A.
-		 */
-		return 1000;
-#endif
-	default:
-		return 500;
-	}
-}
-#endif /* HAS_TASK_USB_CHG */
-
-static inline enum ec_error_list ch_raw_read16(int chgnum, int cmd, int *param,
-					       enum bd9995x_command map_cmd)
-{
-	int rv;
-
-	/* Map the Charge command code to appropriate region */
-	mutex_lock(&bd9995x_map_mutex);
-	if (charger_map_cmd != map_cmd) {
-		rv = i2c_write16(chg_chips[chgnum].i2c_port,
-				 chg_chips[chgnum].i2c_addr_flags,
-				 BD9995X_CMD_MAP_SET, map_cmd);
-		if (rv) {
-			charger_map_cmd = BD9995X_INVALID_COMMAND;
-			goto bd9995x_read_cleanup;
-		}
-
-		charger_map_cmd = map_cmd;
-	}
-
-	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			cmd, param);
-
-bd9995x_read_cleanup:
-	mutex_unlock(&bd9995x_map_mutex);
-
-	return rv;
-}
-
-static inline enum ec_error_list ch_raw_write16(int chgnum, int cmd, int param,
-						enum bd9995x_command map_cmd)
-{
-	int rv;
-
-	/* Map the Charge command code to appropriate region */
-	mutex_lock(&bd9995x_map_mutex);
-	if (charger_map_cmd != map_cmd) {
-		rv = i2c_write16(chg_chips[chgnum].i2c_port,
-				 chg_chips[chgnum].i2c_addr_flags,
-				 BD9995X_CMD_MAP_SET, map_cmd);
-		if (rv) {
-			charger_map_cmd = BD9995X_INVALID_COMMAND;
-			goto bd9995x_write_cleanup;
-		}
-
-		charger_map_cmd = map_cmd;
-	}
-
-	rv = i2c_write16(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 cmd, param);
-
-bd9995x_write_cleanup:
-	mutex_unlock(&bd9995x_map_mutex);
-
-	return rv;
-}
-
-/* BD9995X local interfaces */
-
-static int bd9995x_set_vfastchg(int chgnum, int voltage)
-{
-
-	int rv;
-
-	/* Fast Charge Voltage Regulation Settings for fast charging. */
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET1,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-#ifndef CONFIG_CHARGER_BATTERY_TSENSE
-	/*
-	 * If TSENSE is not connected set all the VFASTCHG_REG_SETx
-	 * to same voltage.
-	 */
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET2,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET3,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
-#endif
-
-	return rv;
-}
-
-static int bd9995x_set_vsysreg(int chgnum, int voltage)
-{
-	/* VSYS Regulation voltage is in 64mV steps. */
-	voltage &= ~0x3F;
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_VSYSREG_SET, voltage,
-			      BD9995X_EXTENDED_COMMAND);
-}
-
-static int bd9995x_is_discharging_on_ac(int chgnum)
-{
-	int reg;
-
-	if (ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND))
-		return 0;
-
-	return !!(reg & BD9995X_CMD_CHGOP_SET2_BATT_LEARN);
-}
-
-static int bd9995x_charger_enable(int chgnum, int enable)
-{
-	int rv, reg;
-	static int prev_chg_enable = -1;
-	const struct battery_info *bi = battery_get_info();
-
-#ifdef CONFIG_CHARGER_BD9995X_CHGEN
-	/*
-	 * If the battery is not yet initialized, dont turn-off the BGATE so
-	 * that voltage from the AC is applied to the battery PACK.
-	 */
-	if (!enable && !board_battery_initialized())
-		return EC_SUCCESS;
-#endif
-
-	/* Nothing to change */
-	if (enable == prev_chg_enable)
-		return EC_SUCCESS;
-
-	prev_chg_enable = enable;
-
-	if (enable) {
-		/*
-		 * BGATE capacitor max : 0.1uF + 20%
-		 * Charge MOSFET threshold max : 2.8V
-		 * BGATE charge pump current min : 3uA
-		 * T = C * V / I so, Tmax = 112ms
-		 */
-		msleep(115);
-
-		/*
-		 * Set VSYSREG_SET <= VBAT so that the charger is in Fast-Charge
-		 * state when charging.
-		 */
-		rv = bd9995x_set_vsysreg(chgnum, bi->voltage_min);
-	} else {
-		/*
-		 * Set VSYSREG_SET > VBAT so that the charger is in Pre-Charge
-		 * state when not charging or discharging.
-		 */
-		rv = bd9995x_set_vsysreg(chgnum, bi->voltage_max +
-					 BD9995X_VSYS_PRECHARGE_OFFSET_MV);
-
-		/*
-		 * Allow charger in pre-charge state for 50ms before disabling
-		 * the charger which prevents inrush current while moving from
-		 * fast-charge state to pre-charge state.
-		 */
-		msleep(50);
-	}
-	if (rv)
-		return rv;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	if (enable)
-		reg |= BD9995X_CMD_CHGOP_SET2_CHG_EN;
-	else
-		reg &= ~BD9995X_CMD_CHGOP_SET2_CHG_EN;
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
-}
-
-static int bd9995x_por_reset(int chgnum)
-{
-	int rv;
-	int reg;
-	int i;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET,
-			BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD |
-			BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* Wait until OTPROM loading is finished */
-	for (i = 0; i < OTPROM_LOAD_WAIT_RETRY; i++) {
-		msleep(10);
-		rv = ch_raw_read16(chgnum, BD9995X_CMD_SYSTEM_STATUS, &reg,
-				BD9995X_EXTENDED_COMMAND);
-
-		if (!rv && (reg & BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE) &&
-			(reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE))
-			break;
-	}
-
-	if (rv)
-		return rv;
-	if (i == OTPROM_LOAD_WAIT_RETRY)
-		return EC_ERROR_TIMEOUT;
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET, 0,
-				BD9995X_EXTENDED_COMMAND);
-}
-
-static int bd9995x_reset_to_zero(int chgnum)
-{
-	int rv;
-
-	rv = bd9995x_set_current(chgnum, 0);
-	if (rv)
-		return rv;
-
-	return bd9995x_set_voltage(chgnum, 0);
-}
-
-static int bd9995x_get_charger_op_status(int chgnum, int *status)
-{
-	return ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_STATUS, status,
-				BD9995X_EXTENDED_COMMAND);
-}
-
-#ifdef HAS_TASK_USB_CHG
-static int bc12_detected_type[CONFIG_USB_PD_PORT_MAX_COUNT];
-/* Mutex for UCD_SET registers, lock before read / mask / write. */
-static struct mutex ucd_set_mutex[BD9995X_CHARGE_PORT_COUNT];
-
-static int bd9995x_get_bc12_device_type(int chgnum, int port)
-{
-	int rv;
-	int reg;
-
-	rv = ch_raw_read16(chgnum, (port == BD9995X_CHARGE_PORT_VBUS) ?
-				BD9995X_CMD_VBUS_UCD_STATUS :
-				BD9995X_CMD_VCC_UCD_STATUS,
-				&reg, BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return CHARGE_SUPPLIER_NONE;
-
-	switch (reg & BD9995X_TYPE_MASK) {
-	case BD9995X_TYPE_CDP:
-		return CHARGE_SUPPLIER_BC12_CDP;
-	case BD9995X_TYPE_DCP:
-		return CHARGE_SUPPLIER_BC12_DCP;
-	case BD9995X_TYPE_SDP:
-		return CHARGE_SUPPLIER_BC12_SDP;
-	case BD9995X_TYPE_PUP_PORT:
-	case BD9995X_TYPE_OTHER:
-		return CHARGE_SUPPLIER_OTHER;
-	case BD9995X_TYPE_OPEN_PORT:
-	case BD9995X_TYPE_VBUS_OPEN:
-	default:
-		return CHARGE_SUPPLIER_NONE;
-	}
-}
-
-/*
- * Do safe read / mask / write of BD9995X_CMD_*_UCD_SET register.
- * The USB charger task owns all bits of this register, except for bit 0
- * (BD9995X_CMD_UCD_SET_USB_SW), which is controlled by
- * usb_charger_set_switches().
- */
-static int bd9995x_update_ucd_set_reg(int chgnum, int port, uint16_t mask,
-				      int set)
-{
-	int rv;
-	int reg;
-	int port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_UCD_SET : BD9995X_CMD_VCC_UCD_SET;
-
-	mutex_lock(&ucd_set_mutex[port]);
-	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
-	if (!rv) {
-		if (set)
-			reg |= mask;
-		else
-			reg &= ~mask;
-
-		rv = ch_raw_write16(chgnum, port_reg, reg,
-				    BD9995X_EXTENDED_COMMAND);
-	}
-
-	mutex_unlock(&ucd_set_mutex[port]);
-	return rv;
-}
-
-static int bd9995x_bc12_check_type(int chgnum, int port)
-{
-	int bc12_type;
-	struct charge_port_info charge;
-	int vbus_provided = bd9995x_is_vbus_provided(port) &&
-			    !usb_charger_port_is_sourcing_vbus(port);
-
-	/*
-	 * If vbus is no longer provided, then no need to continue. Return 0 so
-	 * that a wait event is not scheduled.
-	 */
-	if (!vbus_provided)
-		return 0;
-
-	/* get device type */
-	bc12_type = bd9995x_get_bc12_device_type(chgnum, port);
-	if (bc12_type == CHARGE_SUPPLIER_NONE)
-		/*
-		 * Device type is not available, return non-zero so new wait
-		 * will be scheduled before putting the task to sleep.
-		 */
-		return 1;
-
-	bc12_detected_type[port] = bc12_type;
-	/* Update charge manager */
-	charge.voltage = USB_CHARGER_VOLTAGE_MV;
-	charge.current = bd9995x_get_bc12_ilim(bc12_type);
-	charge_manager_update_charge(bc12_type, port, &charge);
-
-	return 0;
-}
-
-static void bd9995x_bc12_detach(int chgnum, int port, int type)
-{
-	/* Update charge manager */
-	charge_manager_update_charge(type, port, NULL);
-
-	/* Disable charging trigger by BC1.2 detection */
-	bd9995x_bc12_enable_charging(port, 0);
-}
-
-static int bd9995x_enable_vbus_detect_interrupts(int chgnum, int port,
-						 int enable)
-{
-	int reg;
-	int rv;
-	int port_reg;
-	int mask_val;
-
-	/* 1st Level Interrupt Setting */
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_INT0_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	mask_val = ((port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT0_SET_INT1_EN :
-			BD9995X_CMD_INT0_SET_INT2_EN) |
-			BD9995X_CMD_INT0_SET_INT0_EN;
-	if (enable)
-		reg |= mask_val;
-	else
-		reg &= ~mask_val;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_INT0_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* 2nd Level Interrupt Setting */
-	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_SET : BD9995X_CMD_INT2_SET;
-	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* Enable threshold interrupts if we need to control discharge */
-#ifdef CONFIG_USB_PD_DISCHARGE
-	mask_val = BD9995X_CMD_INT_VBUS_DET | BD9995X_CMD_INT_VBUS_TH;
-#else
-	mask_val = BD9995X_CMD_INT_VBUS_DET;
-#endif
-	if (enable)
-		reg |= mask_val;
-	else
-		reg &= ~mask_val;
-
-	return ch_raw_write16(chgnum, port_reg, reg, BD9995X_EXTENDED_COMMAND);
-}
-
-/* Read + clear active interrupt bits for a given port */
-static int bd9995x_get_interrupts(int chgnum, int port)
-{
-	int rv;
-	int reg;
-	int port_reg;
-
-	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_STATUS : BD9995X_CMD_INT2_STATUS;
-
-	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
-
-	if (rv)
-		return 0;
-
-	/* Clear the interrupt status bits we just read */
-	ch_raw_write16(chgnum, port_reg, reg, BD9995X_EXTENDED_COMMAND);
-
-	return reg;
-}
-
-/*
- * Set or clear registers necessary to do one-time BC1.2 detection.
- * Pass enable = 1 to trigger BC1.2 detection, and enable = 0 once
- * BC1.2 detection has completed.
- */
-static int bd9995x_bc12_detect(int chgnum, int port, int enable)
-{
-	return bd9995x_update_ucd_set_reg(chgnum, port,
-					  BD9995X_CMD_UCD_SET_BCSRETRY |
-					  BD9995X_CMD_UCD_SET_USBDETEN |
-					  BD9995X_CMD_UCD_SET_USB_SW_EN,
-					  enable);
-}
-
-static int usb_charger_process(int chgnum, int port)
-{
-	int vbus_provided = bd9995x_is_vbus_provided(port) &&
-			    !usb_charger_port_is_sourcing_vbus(port);
-
-	/* Inform other modules about VBUS level */
-	usb_charger_vbus_change(port, vbus_provided);
-
-	/*
-	 * Do BC1.2 detection, if we have VBUS and our port is not known
-	 * to speak PD.
-	 */
-	if (vbus_provided && !pd_capable(port)) {
-		bd9995x_bc12_detect(chgnum, port, 1);
-		/*
-		 * Need to give the charger time (~312 mSec) before the
-		 * bc12_type is available. The main task loop will schedule a
-		 * task wait event which will then call bd9995x_bc12_get_type.
-		 */
-		return 1;
-	}
-
-	/* Reset BC1.2 regs so we don't do auto-detection. */
-	bd9995x_bc12_detect(chgnum, port, 0);
-
-	/*
-	 * VBUS is no longer being provided, if the bc12_type had been
-	 * previously determined, then need to detach.
-	 */
-	if (bc12_detected_type[port] != CHARGE_SUPPLIER_NONE) {
-		/* Charger/sink detached */
-		bd9995x_bc12_detach(chgnum, port, bc12_detected_type[port]);
-		bc12_detected_type[port] = CHARGE_SUPPLIER_NONE;
-	}
-	/* No need for the task to schedule a wait event */
-	return 0;
-}
-
-#ifdef CONFIG_CHARGE_RAMP_SW
-static int bd9995x_ramp_allowed(int supplier)
-{
-	return supplier == CHARGE_SUPPLIER_BC12_DCP ||
-	       supplier == CHARGE_SUPPLIER_BC12_SDP ||
-	       supplier == CHARGE_SUPPLIER_BC12_CDP ||
-	       supplier == CHARGE_SUPPLIER_OTHER;
-}
-
-static int bd9995x_ramp_max(int supplier, int sup_curr)
-{
-	return bd9995x_get_bc12_ilim(supplier);
-}
-#endif /* CONFIG_CHARGE_RAMP_SW */
-#endif /* HAS_TASK_USB_CHG */
-
-/* chip specific interfaces */
-
-static enum ec_error_list bd9995x_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-	int rv;
-
-	/* Input current step 32 mA */
-	input_current &= ~0x1F;
-
-	if (input_current < bd9995x_charger_info.input_current_min)
-		input_current = bd9995x_charger_info.input_current_min;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_IBUS_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
-	if (rv)
-		return rv;
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_ICC_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
-}
-
-static enum ec_error_list bd9995x_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	return ch_raw_read16(chgnum, BD9995X_CMD_CUR_ILIM_VAL, input_current,
-			     BD9995X_EXTENDED_COMMAND);
-}
-
-static enum ec_error_list bd9995x_manufacturer_id(int chgnum, int *id)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static enum ec_error_list bd9995x_device_id(int chgnum, int *id)
-{
-	return ch_raw_read16(chgnum, BD9995X_CMD_CHIP_ID, id,
-			     BD9995X_EXTENDED_COMMAND);
-}
-
-static enum ec_error_list bd9995x_get_option(int chgnum, int *option)
-{
-	int rv;
-	int reg;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET1, option,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	*option |= reg << 16;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bd9995x_set_option(int chgnum, int option)
-{
-	int rv;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET1, option & 0xFFFF,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2,
-			      (option >> 16) & 0xFFFF,
-			      BD9995X_EXTENDED_COMMAND);
-}
-
-/* Charger interfaces */
-
-static const struct charger_info *bd9995x_get_info(int chgnum)
-{
-	return &bd9995x_charger_info;
-}
-
-static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
-{
-	int rv;
-	int reg;
-	int ch_status;
-
-	/* charger level */
-	*status = CHARGER_LEVEL_2;
-
-	/* charger enable/inhibit */
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	if (!(reg & BD9995X_CMD_CHGOP_SET2_CHG_EN))
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	/* charger alarm enable/inhibit */
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_PROCHOT_CTRL_SET, &reg,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	if (!(reg & (BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0)))
-		*status |= CHARGER_ALARM_INHIBITED;
-
-	rv = bd9995x_get_charger_op_status(chgnum, &reg);
-	if (rv)
-		return rv;
-
-	/* power fail */
-	if (!(reg & BD9995X_CMD_CHGOP_STATUS_RBOOST_UV))
-		*status |= CHARGER_POWER_FAIL;
-
-	/* Safety signal ranges & battery presence */
-	ch_status = (reg & BD9995X_BATTTEMP_MASK) >> 8;
-
-	*status |= CHARGER_BATTERY_PRESENT;
-
-	switch (ch_status) {
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1:
-		*status |= CHARGER_RES_COLD;
-		break;
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2:
-		*status |= CHARGER_RES_COLD;
-		*status |= CHARGER_RES_UR;
-		break;
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1:
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2:
-		*status |= CHARGER_RES_HOT;
-		break;
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3:
-		*status |= CHARGER_RES_HOT;
-		*status |= CHARGER_RES_OR;
-		break;
-	case BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN:
-		*status &= ~CHARGER_BATTERY_PRESENT;
-	default:
-		break;
-	}
-
-	/* source of power */
-	if (bd9995x_is_vbus_provided(BD9995X_CHARGE_PORT_BOTH))
-		*status |= CHARGER_AC_PRESENT;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bd9995x_set_mode(int chgnum, int mode)
-{
-	int rv;
-
-	if (mode & CHARGE_FLAG_POR_RESET) {
-		rv = bd9995x_por_reset(chgnum);
-		if (rv)
-			return rv;
-	}
-
-	if (mode & CHARGE_FLAG_RESET_TO_ZERO) {
-		rv = bd9995x_reset_to_zero(chgnum);
-		if (rv)
-			return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bd9995x_get_current(int chgnum, int *current)
-{
-	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-				BD9995X_BAT_CHG_COMMAND);
-}
-
-static enum ec_error_list bd9995x_set_current(int chgnum, int current)
-{
-	int rv;
-	int chg_enable = 1;
-
-	/* Charge current step 64 mA */
-	current &= ~0x3F;
-
-	if (current < BD9995X_NO_BATTERY_CHARGE_I_MIN &&
-	    (battery_is_present() != BP_YES || battery_is_cut_off()))
-		current = BD9995X_NO_BATTERY_CHARGE_I_MIN;
-
-	/*
-	 * Disable charger before setting charge current to 0 or when
-	 * discharging on AC.
-	 * If charging current is set to 0mA during charging, reference of
-	 * the charge current feedback amp (VREF_CHG) is set to 0V. Hence
-	 * the DCDC stops switching (because of the EA offset).
-	 */
-	if (!current || bd9995x_is_discharging_on_ac(chgnum)) {
-		chg_enable = 0;
-		rv = bd9995x_charger_enable(chgnum, 0);
-		if (rv)
-			return rv;
-	}
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_IPRECH_SET,
-			    MIN(current, BD9995X_IPRECH_MAX),
-			    BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-			      BD9995X_BAT_CHG_COMMAND);
-	if (rv)
-		return rv;
-
-	/*
-	 * Enable charger if charge current is non-zero or not discharging
-	 * on AC.
-	 */
-	return chg_enable ? bd9995x_charger_enable(chgnum, 1) : EC_SUCCESS;
-}
-
-static enum ec_error_list bd9995x_get_voltage(int chgnum, int *voltage)
-{
-	if (vsys_priority) {
-		int batt_volt_measured;
-		int reg;
-		int rv;
-
-		/* Get battery voltage as reported by charger */
-		batt_volt_measured = bd9995x_get_battery_voltage();
-		if (batt_volt_measured > (battery_get_info()->voltage_min +
-					  BD9995X_VSYS_PRECHARGE_OFFSET_MV)) {
-			/*
-			 * Battery is not deeply discharged. Clear the
-			 * VSYS_PRIORITY bit to ensure that input current limit
-			 * is always active.
-			 */
-			mutex_lock(&bd9995x_vin_mutex);
-			if (!ch_raw_read16(chgnum, BD9995X_CMD_VIN_CTRL_SET,
-					   &reg, BD9995X_EXTENDED_COMMAND)) {
-				reg &= ~BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY;
-				rv = ch_raw_write16(chgnum,
-						    BD9995X_CMD_VIN_CTRL_SET,
-						    reg,
-						    BD9995X_EXTENDED_COMMAND);
-
-				/* Mirror the state of this bit */
-				if (!rv)
-					vsys_priority = 0;
-			}
-			mutex_unlock(&bd9995x_vin_mutex);
-		}
-	}
-
-	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_VOLTAGE, voltage,
-				BD9995X_BAT_CHG_COMMAND);
-}
-
-static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage)
-{
-	const int battery_voltage_max = battery_get_info()->voltage_max;
-
-	/*
-	 * Regulate the system voltage to battery max if the battery
-	 * is not present or the battery is discharging on AC.
-	 */
-	if (voltage == 0 ||
-		bd9995x_is_discharging_on_ac(chgnum) ||
-		battery_is_present() != BP_YES ||
-		battery_is_cut_off() ||
-		voltage > battery_voltage_max)
-		voltage = battery_voltage_max;
-
-	/* Charge voltage step 16 mV */
-	voltage &= ~0x0F;
-
-	/* Assumes charger's voltage_min < battery's voltage_max */
-	if (voltage < bd9995x_charger_info.voltage_min)
-		voltage = bd9995x_charger_info.voltage_min;
-
-	return bd9995x_set_vfastchg(chgnum, voltage);
-}
-
-static void bd9995x_battery_charging_profile_settings(int chgnum)
-{
-	const struct battery_info *bi = battery_get_info();
-
-	/* Input Current Limit Setting */
-	bd9995x_set_input_current_limit(chgnum, CONFIG_CHARGER_INPUT_CURRENT);
-
-	/* Charge Termination Current Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_ITERM_SET, 0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Trickle-charge Current Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_ITRICH_SET,
-		       bi->precharge_current & 0x07C0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	bd9995x_set_vfastchg(chgnum, bi->voltage_max);
-
-	/* Set Pre-charge Voltage Threshold for trickle charging. */
-	ch_raw_write16(chgnum, BD9995X_CMD_VPRECHG_TH_SET,
-		       (bi->voltage_min - 1000) & 0x7FC0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Re-charge Battery Voltage Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET,
-		       bi->voltage_max & 0x7FF0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Set battery OVP to 500 + maximum battery voltage */
-	ch_raw_write16(chgnum, BD9995X_CMD_VBATOVP_SET,
-		       (bi->voltage_max + 500) & 0x7ff0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Reverse buck boost voltage Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_VRBOOST_SET, 0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Disable fast/pre-charging watchdog */
-	ch_raw_write16(chgnum, BD9995X_CMD_CHGWDT_SET, 0,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* TODO(crosbug.com/p/55626): Set  VSYSVAL_THH/THL appropriately */
-}
-
-/*
- * Note: opting not to use charger driver init here due to the different
- * priority (other drivers use HOOK_PRIO_INIT_I2C + 1)
- */
-static void bd9995x_init(void)
-{
-	int reg;
-
-	/*
-	 * Disable charging trigger by BC1.2 on VCC & VBUS and
-	 * automatic limitation of the input current.
-	 */
-	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, &reg,
-			  BD9995X_EXTENDED_COMMAND))
-		return;
-	reg |= (BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN |
-		BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
-		BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN |
-		BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN |
-		BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN |
-		BD9995X_CMD_CHGOP_SET1_SDP_500_SEL |
-		BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL);
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, reg,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/*
-	 * OTP setting for this register is 6.08V. Set VSYS to above battery max
-	 * (as is done when charger is disabled) to ensure VSYSREG_SET > VBAT so
-	 * that the charger is in Pre-Charge state and that the input current
-	 * disable setting below will be active.
-	 */
-	bd9995x_set_vsysreg(CHARGER_SOLO, battery_get_info()->voltage_max +
-			    BD9995X_VSYS_PRECHARGE_OFFSET_MV);
-
-	/* Enable BC1.2 USB charging and DC/DC converter @ 1200KHz */
-	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET2, &reg,
-			  BD9995X_EXTENDED_COMMAND))
-		return;
-	reg &= ~(BD9995X_CMD_CHGOP_SET2_USB_SUS |
-		 BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL);
-	reg |= BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200;
-#ifdef CONFIG_CHARGER_BD9995X_CHGEN
-	reg |= BD9995X_CMD_CHGOP_SET2_CHG_EN;
-#endif
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET2, reg,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/*
-	 * We disable IADP (here before setting IBUS_LIM_SET and ICC_LIM_SET)
-	 * to prevent voltage on IADP/RESET pin from affecting SEL_ILIM_VAL.
-	 */
-	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VM_CTRL_SET, &reg,
-			  BD9995X_EXTENDED_COMMAND))
-		return;
-	reg &= ~BD9995X_CMD_VM_CTRL_SET_EXTIADPEN;
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VM_CTRL_SET, reg,
-		       BD9995X_EXTENDED_COMMAND);
-	/*
-	 * Disable the input current limit when VBAT is < VSYSREG_SET. This
-	 * needs to be done before calling
-	 * bd9995x_battery_charging_profile_settings() as in that function the
-	 * input current limit is set to CONFIG_CHARGER_INPUT_CURRENT which is
-	 * 512 mA. In deeply discharged battery cases, setting the input current
-	 * limit this low can cause VSYS to collapse, which in turn can cause
-	 * the EC's brownout detector to reset the EC.
-	 */
-	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, &reg,
-			  BD9995X_EXTENDED_COMMAND))
-		return;
-	reg |= BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY;
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, reg,
-		       BD9995X_EXTENDED_COMMAND);
-	/* Mirror the state of this bit */
-	vsys_priority = 1;
-
-	/* Define battery charging profile */
-	bd9995x_battery_charging_profile_settings(CHARGER_SOLO);
-
-	/* Power save mode when VBUS/VCC is removed. */
-#ifdef CONFIG_BD9995X_POWER_SAVE_MODE
-	bd9995x_set_power_save_mode(CONFIG_BD9995X_POWER_SAVE_MODE);
-#else
-	bd9995x_set_power_save_mode(BD9995X_PWR_SAVE_OFF);
-#endif
-
-#ifdef CONFIG_USB_PD_DISCHARGE
-	/* Set VBUS / VCC detection threshold for discharge enable */
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VBUS_TH_SET,
-		       BD9995X_VBUS_DISCHARGE_TH, BD9995X_EXTENDED_COMMAND);
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VCC_TH_SET,
-		       BD9995X_VBUS_DISCHARGE_TH, BD9995X_EXTENDED_COMMAND);
-#endif
-
-	/* Unlock debug regs */
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_PROTECT_SET, 0x3c,
-		       BD9995X_EXTENDED_COMMAND);
-
-	/* Undocumented - reverse current threshold = -50mV */
-	ch_raw_write16(CHARGER_SOLO, 0x14, 0x0202, BD9995X_DEBUG_COMMAND);
-	/* Undocumented - internal gain = 2x */
-	ch_raw_write16(CHARGER_SOLO, 0x1a, 0x80, BD9995X_DEBUG_COMMAND);
-
-	/* Re-lock debug regs */
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_PROTECT_SET, 0x0,
-		       BD9995X_EXTENDED_COMMAND);
-}
-DECLARE_HOOK(HOOK_INIT, bd9995x_init, HOOK_PRIO_INIT_EXTPOWER);
-
-static enum ec_error_list bd9995x_post_init(int chgnum)
-{
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable)
-{
-	int rv;
-	int reg;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/*
-	 * Suspend USB charging and DC/DC converter so that BATT_LEARN mode
-	 * doesn't auto exit if VBAT < VSYSVAL_THL_SET and also it helps to
-	 * discharge VBUS quickly when charging is not allowed and the AC
-	 * is removed.
-	 */
-	if (enable)
-		reg |= BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS;
-	else
-		reg &= ~(BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS);
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
-}
-
-static enum ec_error_list bd9995x_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
-{
-	uint8_t read_reg;
-
-	read_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_VBUS_VAL :
-							BD9995X_CMD_VCC_VAL;
-
-	return ch_raw_read16(chgnum, read_reg, voltage,
-			     BD9995X_EXTENDED_COMMAND);
-}
-
-/*** Non-standard interface functions ***/
-
-int bd9995x_is_vbus_provided(enum bd9995x_charge_port port)
-{
-	int reg;
-
-	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VBUS_VCC_STATUS, &reg,
-			  BD9995X_EXTENDED_COMMAND))
-		return 0;
-
-	if (port == BD9995X_CHARGE_PORT_VBUS)
-		reg &= BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT;
-	else if (port == BD9995X_CHARGE_PORT_VCC)
-		reg &= BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT;
-	else if (port == BD9995X_CHARGE_PORT_BOTH) {
-		/* Check VBUS on either port */
-		reg &= (BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT |
-			BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT);
-	} else
-		reg = 0;
-
-	return !!reg;
-}
-
-#ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-static int bd9995x_select_input_port_private(enum bd9995x_charge_port port,
-					     int select)
-#else
-int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
-#endif
-{
-	int rv;
-	int reg;
-
-	mutex_lock(&bd9995x_vin_mutex);
-	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, &reg,
-			   BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		goto select_input_port_exit;
-
-	if (select) {
-		if (port == BD9995X_CHARGE_PORT_VBUS) {
-			reg |= BD9995X_CMD_VIN_CTRL_SET_VBUS_EN;
-			reg &= ~BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
-		} else if (port == BD9995X_CHARGE_PORT_VCC) {
-			reg |= BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
-			reg &= ~BD9995X_CMD_VIN_CTRL_SET_VBUS_EN;
-		} else if (port == BD9995X_CHARGE_PORT_BOTH) {
-			/* Enable both the ports for PG3 */
-			reg |= BD9995X_CMD_VIN_CTRL_SET_VBUS_EN |
-				BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
-		} else {
-			/* Invalid charge port */
-			panic("Invalid charge port");
-		}
-	} else {
-		if (port == BD9995X_CHARGE_PORT_VBUS)
-			reg &= ~BD9995X_CMD_VIN_CTRL_SET_VBUS_EN;
-		else if (port == BD9995X_CHARGE_PORT_VCC)
-			reg &= ~BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
-		else if (port == BD9995X_CHARGE_PORT_BOTH)
-			reg &= ~(BD9995X_CMD_VIN_CTRL_SET_VBUS_EN |
-				 BD9995X_CMD_VIN_CTRL_SET_VCC_EN);
-		else
-			panic("Invalid charge port");
-	}
-
-	rv = ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, reg,
-			      BD9995X_EXTENDED_COMMAND);
-select_input_port_exit:
-	mutex_unlock(&bd9995x_vin_mutex);
-	return rv;
-}
-
-#ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
-{
-	port_update = port;
-	select_update = select;
-	vbus_state = START;
-	select_input_port_update = 1;
-	task_wake(TASK_ID_USB_CHG);
-
-	return EC_SUCCESS;
-}
-
-static inline int bd9995x_vbus_test(int value, int limit)
-{
-	uint32_t hi_value = limit + VBUS_DELTA;
-	uint32_t lo_value = limit - VBUS_DELTA;
-
-	return ((value > lo_value) && (value < hi_value));
-}
-
-static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port)
-{
-	int vbus_reg;
-	int voltage;
-
-	vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_VAL : BD9995X_CMD_VCC_VAL;
-	if (ch_raw_read16(chgnum, vbus_reg, &voltage, BD9995X_EXTENDED_COMMAND))
-		voltage = 0;
-
-	if (!bd9995x_vbus_test(voltage, vbus_voltage)) {
-		vbus_voltage = voltage;
-		debounce_time = get_time().val + VBUS_MSEC;
-	} else {
-		if (get_time().val >= debounce_time)
-			return 1;
-	}
-
-	return 0;
-}
-#endif
-
-
-#ifdef CONFIG_CHARGER_BATTERY_TSENSE
-int bd9995x_get_battery_temp(int *temp_ptr)
-{
-	int rv;
-
-	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_THERM_VAL, temp_ptr,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* Degrees C = 200 - THERM_VAL, range is -55C-200C, 1C steps */
-	*temp_ptr = 200 - *temp_ptr;
-	return EC_SUCCESS;
-}
-#endif
-
-void bd9995x_set_power_save_mode(int mode)
-{
-	ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_SMBREG, mode,
-		       BD9995X_EXTENDED_COMMAND);
-}
-
-int bd9995x_get_battery_voltage(void)
-{
-	int vbat_val, rv;
-
-	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VBAT_VAL, &vbat_val,
-			BD9995X_EXTENDED_COMMAND);
-
-	return rv ? 0 : vbat_val;
-}
-
-#ifdef HAS_TASK_USB_CHG
-int bd9995x_bc12_enable_charging(int port, int enable)
-{
-	int rv;
-	int reg;
-	int mask_val;
-
-	/*
-	 * For BC1.2, enable VBUS/VCC_BC_DISEN charging trigger by BC1.2
-	 * detection and disable SDP_CHG_TRIG, SDP_CHG_TRIG_EN. Vice versa
-	 * for USB-C.
-	 */
-	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, &reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	mask_val = (BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN |
-		BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
-		((port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN :
-		BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN));
-
-	if (enable)
-		reg &= ~mask_val;
-	else
-		reg |= mask_val;
-
-	return ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, reg,
-			BD9995X_EXTENDED_COMMAND);
-}
-
-static void bd9995x_set_switches(int port, enum usb_switch setting)
-{
-	/* If switch is not changing then return */
-	if (setting == usb_switch_state[port])
-		return;
-
-	if (setting != USB_SWITCH_RESTORE)
-		usb_switch_state[port] = setting;
-
-	/* ensure we disable power saving when we are using DP/DN */
-#ifdef CONFIG_BD9995X_POWER_SAVE_MODE
-	bd9995x_set_power_save_mode(
-		(usb_switch_state[0] == USB_SWITCH_DISCONNECT &&
-		usb_switch_state[1] == USB_SWITCH_DISCONNECT)
-		? CONFIG_BD9995X_POWER_SAVE_MODE : BD9995X_PWR_SAVE_OFF);
-#endif
-
-	bd9995x_update_ucd_set_reg(CHARGER_SOLO, port,
-				   BD9995X_CMD_UCD_SET_USB_SW,
-				usb_switch_state[port] == USB_SWITCH_CONNECT);
-}
-
-void bd9995x_vbus_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_USB_CHG);
-}
-
-static void bd9995x_usb_charger_task(const int unused)
-{
-	static int initialized;
-	int changed, port, interrupts;
-	int sleep_usec;
-	uint64_t bc12_det_mark[CONFIG_USB_PD_PORT_MAX_COUNT];
-#ifdef CONFIG_USB_PD_DISCHARGE
-	int vbus_reg, voltage;
-#endif
-
-#ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-	select_input_port_update = 0;
-	vbus_voltage = 0;
-#endif
-
-	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		bc12_detected_type[port] = CHARGE_SUPPLIER_NONE;
-		bd9995x_enable_vbus_detect_interrupts(CHARGER_SOLO, port, 1);
-		bc12_det_mark[port] = 0;
-	}
-
-	while (1) {
-		sleep_usec = -1;
-		changed = 0;
-		for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-			/* Get port interrupts */
-			interrupts = bd9995x_get_interrupts(CHARGER_SOLO, port);
-			if (interrupts & BD9995X_CMD_INT_VBUS_DET ||
-			    !initialized) {
-				/*
-				 * Detect based on current state of VBUS. If
-				 * VBUS is provided, then need to wait for
-				 * bc12_type to be available. If VBUS is not
-				 * provided, then disable wait for this port.
-				 */
-				bc12_det_mark[port] =
-					usb_charger_process(CHARGER_SOLO, port)
-					? get_time().val + BC12_DETECT_US : 0;
-				changed = 1;
-			}
-#ifdef CONFIG_USB_PD_DISCHARGE
-			if (interrupts & BD9995X_CMD_INT_VBUS_TH ||
-			    !initialized) {
-				/* Get VBUS voltage */
-				vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-					   BD9995X_CMD_VBUS_VAL :
-					   BD9995X_CMD_VCC_VAL;
-				if (ch_raw_read16(CHARGER_SOLO, vbus_reg,
-						  &voltage,
-						  BD9995X_EXTENDED_COMMAND))
-					voltage = 0;
-
-				/* Set discharge accordingly */
-				pd_set_vbus_discharge(port,
-					voltage < BD9995X_VBUS_DISCHARGE_TH);
-				changed = 1;
-			}
-#endif
-			if (bc12_det_mark[port] && (get_time().val >
-						    bc12_det_mark[port])) {
-				/*
-				 * bc12_type result should be available. If not
-				 * available still, then function will return
-				 * 1. Set up additional 100 msec wait. Note that
-				 * if VBUS is no longer provided when this call
-				 * happens the function will return 0.
-				 */
-				bc12_det_mark[port] =
-					bd9995x_bc12_check_type(CHARGER_SOLO,
-								port) ?
-					get_time().val + 100 * MSEC : 0;
-				/* Reset BC1.2 regs to skip auto-detection. */
-				bd9995x_bc12_detect(CHARGER_SOLO, port, 0);
-			}
-
-			/*
-			 * Determine if a wait for reading bc12_type needs to be
-			 * scheduled. Use the scheduled wait for this port if
-			 * it's less than the wait needed for a previous
-			 * port. If previous port(s) don't need a wait, then
-			 * sleep_usec will be -1.
-			 */
-			if (bc12_det_mark[port]) {
-				int bc12_wait_usec;
-
-				bc12_wait_usec = bc12_det_mark[port]
-					- get_time().val;
-				if ((sleep_usec < 0) ||
-				    (sleep_usec > bc12_wait_usec))
-					sleep_usec = bc12_wait_usec;
-			}
-		}
-
-		initialized = 1;
-#ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-/*
- * When a charge port is selected and VBUS is 5V, the inrush current on some
- * devices causes VBUS to droop, which could signal a sink disconnection.
- *
- * To mitigate the problem, charge port selection is delayed until VBUS
- * is stable or one second has passed. Hopefully PD has negotiated a VBUS
- * voltage of at least 9V before the one second timeout.
- */
-	if (select_input_port_update) {
-		sleep_usec = VBUS_CHECK_MSEC;
-		changed = 0;
-
-		switch (vbus_state) {
-		case START:
-			vbus_timeout = get_time().val + STABLE_TIMEOUT;
-			vbus_state = STABLE;
-			break;
-		case STABLE:
-			if (get_time().val > vbus_timeout) {
-				vbus_state = DEBOUNCE;
-				vbus_timeout = get_time().val +
-							DEBOUNCE_TIMEOUT;
-			}
-			break;
-		case DEBOUNCE:
-			if (bd9995x_vbus_debounce(CHARGER_SOLO, port_update) ||
-					get_time().val > vbus_timeout) {
-				select_input_port_update = 0;
-				bd9995x_select_input_port_private(
-						port_update, select_update);
-			}
-			break;
-		}
-	}
-#endif
-
-		/*
-		 * Re-read interrupt registers immediately if we got an
-		 * interrupt. We're dealing with multiple independent
-		 * interrupt sources and the interrupt pin may have
-		 * never deasserted if both sources were not in clear
-		 * state simultaneously.
-		 */
-		if (!changed)
-			task_wait_event(sleep_usec);
-	}
-}
-#endif /* HAS_TASK_USB_CHG */
-
-
-/*** Console commands ***/
-#ifdef CONFIG_CMD_CHARGER_DUMP
-static int read_bat(int chgnum, uint8_t cmd)
-{
-	int read = 0;
-
-	ch_raw_read16(chgnum, cmd, &read, BD9995X_BAT_CHG_COMMAND);
-	return read;
-}
-
-static int read_ext(int chgnum, uint8_t cmd)
-{
-	int read = 0;
-
-	ch_raw_read16(chgnum, cmd, &read, BD9995X_EXTENDED_COMMAND);
-	return read;
-}
-
-/* Dump all readable registers on bd9995x */
-static int console_bd9995x_dump_regs(int argc, char **argv)
-{
-	int i;
-	uint8_t regs[] = { 0x14, 0x15, 0x3c, 0x3d, 0x3e, 0x3f };
-
-	/* Battery group registers */
-	for (i = 0; i < ARRAY_SIZE(regs); ++i)
-		ccprintf("BAT REG %4x:  %4x\n", regs[i], read_bat(CHARGER_SOLO,
-								  regs[i]));
-
-	/* Extended group registers */
-	for (i = 0; i < 0x7f; ++i) {
-		ccprintf("EXT REG %4x:  %4x\n", i, read_ext(CHARGER_SOLO, i));
-		cflush();
-	}
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(charger_dump, console_bd9995x_dump_regs,
-			NULL,
-			"Dump all charger registers");
-#endif /* CONFIG_CMD_CHARGER_DUMP */
-
-#ifdef CONFIG_CMD_CHARGER
-static int console_command_bd9995x(int argc, char **argv)
-{
-	int rv, reg, data, val;
-	char rw, *e;
-	enum bd9995x_command cmd;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	rw = argv[1][0];
-	if (rw == 'w' && argc < 5)
-		return EC_ERROR_PARAM_COUNT;
-	else if (rw != 'w' && rw != 'r')
-		return EC_ERROR_PARAM1;
-
-	reg = strtoi(argv[2], &e, 16);
-	if (*e || reg < 0)
-		return EC_ERROR_PARAM2;
-
-	cmd = strtoi(argv[3], &e, 0);
-	if (*e || cmd < 0)
-		return EC_ERROR_PARAM3;
-
-	if (rw == 'r')
-		rv = ch_raw_read16(CHARGER_SOLO, reg, &data, cmd);
-	else {
-		val = strtoi(argv[4], &e, 16);
-		if (*e || val < 0)
-			return EC_ERROR_PARAM4;
-
-		rv = ch_raw_write16(CHARGER_SOLO, reg, val, cmd);
-		if (rv == EC_SUCCESS)
-			rv = ch_raw_read16(CHARGER_SOLO, reg, &data, cmd);
-	}
-
-	if (rv == EC_SUCCESS)
-		CPRINTS("register 0x%x [%d] = 0x%x [%d]", reg, reg, data, data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(bd9995x, console_command_bd9995x,
-			"bd9995x <r/w> <reg_hex> <cmd_type> | <val_hex>",
-			"Read or write a charger register");
-#endif /* CONFIG_CMD_CHARGER */
-
-#ifdef CONFIG_CHARGER_PSYS_READ
-static int bd9995x_psys_charger_adc(int chgnum)
-{
-	int i;
-	int reg;
-	uint64_t ipmon = 0;
-
-	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
-		if (ch_raw_read16(chgnum, BD9995X_CMD_PMON_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND))
-			return 0;
-
-		/* Conversion Interval is 200us */
-		usleep(200);
-		ipmon += reg;
-	}
-
-	/*
-	 * Calculate power in mW
-	 * PSYS = VACP×IACP+VBAT×IBAT = IPMON / GPMON
-	 */
-	return (int) ((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
-		BD9995X_PMON_IOUT_ADC_READ_COUNT));
-}
-
-static int bd9995x_enable_psys(int chgnum)
-{
-	int rv;
-	int reg;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* Enable PSYS & Select PSYS Gain */
-	reg &= ~BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK;
-	reg |= (BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL |
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN |
-		BD9995X_PSYS_GAIN_SELECT);
-
-	return ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
-}
-
-/**
- * Get system power.
- *
- * TODO(b:71520677): Implement charger_get_system_power, disable psys readout
- * when not needed (the code below leaves it enabled after the first access),
- * update "psys" console command to use charger_get_system_power and move it
- * to some common code.
- */
-static int console_command_psys(int argc, char **argv)
-{
-	int rv;
-
-	rv = bd9995x_enable_psys(CHARGER_SOLO);
-	if (rv)
-		return rv;
-
-	CPRINTS("PSYS from chg_adc: %d mW",
-			bd9995x_psys_charger_adc(CHARGER_SOLO));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
-			"Get the system power in mW");
-#endif /* CONFIG_CHARGER_PSYS_READ */
-
-#ifdef CONFIG_CMD_CHARGER_ADC_AMON_BMON
-static int bd9995x_amon_bmon_chg_adc(int chgnum)
-{
-	int i;
-	int reg;
-	int iout = 0;
-
-	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
-		ch_raw_read16(chgnum, BD9995X_CMD_IOUT_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND);
-		iout += reg;
-
-		/* Conversion Interval is 200us */
-		usleep(200);
-	}
-
-	/*
-	 * Discharge current in mA
-	 * IDCHG = iout * GIDCHG
-	 * IADP = iout * GIADP
-	 *
-	 * VIDCHG = GIDCHG * (VSRN- VSRP) = GIDCHG * IDCHG / IDCHG_RES
-	 * VIADP = GIADP * (VACP- VACN) = GIADP * IADP / IADP_RES
-	 */
-	return (iout * (5 << BD9995X_IOUT_GAIN_SELECT)) /
-		(10 * BD9995X_PMON_IOUT_ADC_READ_COUNT);
-}
-
-static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
-{
-	int rv;
-	int reg;
-	int imon;
-	int sns_res;
-
-	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	/* Enable monitor */
-	reg &= ~BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK;
-	reg |= (BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL |
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN |
-		(BD9995X_IOUT_GAIN_SELECT << 4));
-
-	if (amon_bmon) {
-		reg |= BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL;
-		sns_res = CONFIG_CHARGER_SENSE_RESISTOR_AC;
-	} else {
-		reg &= ~BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL;
-		sns_res = CONFIG_CHARGER_SENSE_RESISTOR;
-	}
-
-	rv = ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
-	if (rv)
-		return rv;
-
-	imon = bd9995x_amon_bmon_chg_adc(chgnum);
-
-	CPRINTS("%cMON from chg_adc: %d uV, %d mA]",
-		amon_bmon ? 'A' : 'B',
-		imon * sns_res,
-		imon);
-
-	return EC_SUCCESS;
-}
-
-/**
- * Get charger AMON and BMON current.
- */
-static int console_command_amon_bmon(int argc, char **argv)
-{
-	int rv = EC_ERROR_PARAM1;
-
-	/* Switch to AMON */
-	if (argc == 1 || (argc >= 2 && argv[1][0] == 'a'))
-		rv = bd9995x_amon_bmon(CHARGER_SOLO, 1);
-
-	/* Switch to BMON */
-	if (argc == 1 || (argc >= 2 && argv[1][0] == 'b'))
-		rv = bd9995x_amon_bmon(CHARGER_SOLO, 0);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon,
-			"amonbmon [a|b]",
-			"Get charger AMON/BMON voltage diff, current");
-#endif /* CONFIG_CMD_CHARGER_ADC_AMON_BMON */
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-static int bd9995x_i2c_read(const int reg, int *data)
-{
-	return ch_raw_read16(CHARGER_SOLO, reg, data, BD9995X_EXTENDED_COMMAND);
-}
-
-static int bd9995x_i2c_write(const int reg, int data)
-{
-	return ch_raw_write16(CHARGER_SOLO, reg, data,
-			      BD9995X_EXTENDED_COMMAND);
-}
-
-/* BD9995X_CMD_CHIP_ID register value may vary by chip. */
-struct i2c_stress_test_dev bd9995x_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = BD9995X_CMD_CHIP_ID,
-		.read_val = BD99956_CHIP_ID,
-		.write_reg = BD9995X_CMD_ITRICH_SET,
-	},
-	.i2c_read_dev = &bd9995x_i2c_read,
-	.i2c_write_dev = &bd9995x_i2c_write,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_CHARGER */
-
-const struct charger_drv bd9995x_drv = {
-	.post_init = &bd9995x_post_init,
-	.get_info = &bd9995x_get_info,
-	.get_status = &bd9995x_get_status,
-	.set_mode = &bd9995x_set_mode,
-	.get_current = &bd9995x_get_current,
-	.set_current = &bd9995x_set_current,
-	.get_voltage = &bd9995x_get_voltage,
-	.set_voltage = &bd9995x_set_voltage,
-	.discharge_on_ac = &bd9995x_discharge_on_ac,
-	.get_vbus_voltage = &bd9995x_get_vbus_voltage,
-	.set_input_current_limit = &bd9995x_set_input_current_limit,
-	.get_input_current_limit = &bd9995x_get_input_current_limit,
-	.manufacturer_id = &bd9995x_manufacturer_id,
-	.device_id = &bd9995x_device_id,
-	.get_option = &bd9995x_get_option,
-	.set_option = &bd9995x_set_option,
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[BD9995X_CHARGE_PORT_COUNT] = {
-	{
-		.drv = &(const struct bc12_drv) {
-			.usb_charger_task = bd9995x_usb_charger_task,
-			.set_switches = bd9995x_set_switches,
-#if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
-#endif /* CONFIG_CHARGE_RAMP_SW */
-		},
-	},
-	{
-		.drv = &(const struct bc12_drv) {
-			/* bd9995x uses a single task thread for both ports */
-			.usb_charger_task = NULL,
-			.set_switches = bd9995x_set_switches,
-#if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
-#endif /* CONFIG_CHARGE_RAMP_SW */
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bc12_ports) == CHARGE_PORT_COUNT);
-#else
-/*
- * TODO:
- * This driver assumes its two ports is always on number 0 and 1.
- * Prohibit multiple driver for safety.
- */
-#error config not supported
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h
deleted file mode 100644
index a1f1bdb64f..0000000000
--- a/driver/charger/bd9995x.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ROHM BD9995X battery charger driver.
- */
-
-#ifndef __CROS_EC_BD9995X_H
-#define __CROS_EC_BD9995X_H
-
-#define BD9995X_ADDR_FLAGS	0x09
-
-#define BD9995X_CHARGER_NAME	"bd9995x"
-#define BD99955_CHIP_ID		0x221
-#define BD99956_CHIP_ID		0x331
-
-/* BD9995X commands to change the command code map */
-enum bd9995x_command {
-	BD9995X_BAT_CHG_COMMAND,
-	BD9995X_EXTENDED_COMMAND,
-	BD9995X_DEBUG_COMMAND,
-	BD9995X_INVALID_COMMAND
-};
-
-/*
- * BD9995X has two external VBUS inputs (named VBUS and VCC) and two sets
- * of registers / bits for control. This entire driver is written under the
- * assumption that the physical VBUS port corresponds to PD port 0, and the
- * physical VCC port corresponds to PD port 1.
- */
-enum bd9995x_charge_port {
-	BD9995X_CHARGE_PORT_VBUS,
-	BD9995X_CHARGE_PORT_VCC,
-	BD9995X_CHARGE_PORT_BOTH,
-};
-
-/* Min. charge current w/ no battery to prevent collapse */
-#define BD9995X_NO_BATTERY_CHARGE_I_MIN	512
-
-/*
- * BC1.2 minimum voltage threshold.
- * BC1.2 charging port output voltage range is 4.75V to 5.25V,
- * BD9995X Anti-Collapse Threshold Voltage Accuracy is -100mV to +100mV,
- * and Delta of 50mV.
- */
-#define BD9995X_BC12_MIN_VOLTAGE	4600
-
-/* Battery Charger Commands */
-#define BD9995X_CMD_CHG_CURRENT		0x14
-#define BD9995X_CMD_CHG_VOLTAGE		0x15
-#define BD9995X_CMD_IBUS_LIM_SET	0x3C
-#define BD9995X_CMD_ICC_LIM_SET		0x3D
-#define BD9995X_CMD_PROTECT_SET		0x3E
-#define BD9995X_CMD_MAP_SET		0x3F
-
-/* Extended commands */
-#define BD9995X_CMD_CHGSTM_STATUS	0x00
-#define BD9995X_CMD_VBAT_VSYS_STATUS	0x01
-#define BD9995X_CMD_VBUS_VCC_STATUS	0x02
-#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT  BIT(8)
-#define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0)
-
-#define BD9995X_CMD_CHGOP_STATUS	0x03
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2	BIT(10)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1	BIT(9)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0	BIT(8)
-#define BD9995X_BATTTEMP_MASK			0x700
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP	0
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1		1
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2		2
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3		3
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1		4
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2		5
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE	6
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN	7
-#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV	BIT(1)
-
-#define BD9995X_CMD_WDT_STATUS		0x04
-#define BD9995X_CMD_CUR_ILIM_VAL	0x05
-#define BD9995X_CMD_SEL_ILIM_VAL	0x06
-#define BD9995X_CMD_EXT_IBUS_LIM_SET	0x07
-#define BD9995X_CMD_EXT_ICC_LIM_SET	0x08
-#define BD9995X_CMD_IOTG_LIM_SET	0x09
-#define BD9995X_CMD_VIN_CTRL_SET	0x0A
-#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY	BIT(4)
-
-#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU  BIT(11)
-#define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7)
-#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN       BIT(6)
-#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN        BIT(5)
-
-#define BD9995X_CMD_CHGOP_SET1		0x0B
-#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL    BIT(15)
-#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL     BIT(14)
-#define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13)
-#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN    BIT(11)
-#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN   BIT(10)
-#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9)
-#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG    BIT(8)
-
-#define BD9995X_CMD_CHGOP_SET2		0x0C
-#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN	 BIT(8)
-#define BD9995X_CMD_CHGOP_SET2_CHG_EN		 BIT(7)
-#define BD9995X_CMD_CHGOP_SET2_USB_SUS		 BIT(6)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL      (3 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600  (0 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857  BIT(2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2)
-
-#define BD9995X_CMD_VBUSCLPS_TH_SET	0x0D
-#define BD9995X_CMD_VCCCLPS_TH_SET	0x0E
-#define BD9995X_CMD_CHGWDT_SET		0x0F
-#define BD9995X_CMD_BATTWDT_SET		0x10
-#define BD9995X_CMD_VSYSREG_SET		0x11
-#define BD9995X_CMD_VSYSVAL_THH_SET	0x12
-#define BD9995X_CMD_VSYSVAL_THL_SET	0x13
-#define BD9995X_CMD_ITRICH_SET		0x14
-
-#define BD9995X_CMD_IPRECH_SET		0x15
-#define BD9995X_IPRECH_MAX		1024
-
-#define BD9995X_CMD_ICHG_SET		0x16
-#define BD9995X_CMD_ITERM_SET		0x17
-#define BD9995X_CMD_VPRECHG_TH_SET	0x18
-#define BD9995X_CMD_VRBOOST_SET		0x19
-#define BD9995X_CMD_VFASTCHG_REG_SET1	0x1A
-#define BD9995X_CMD_VFASTCHG_REG_SET2	0x1B
-#define BD9995X_CMD_VFASTCHG_REG_SET3	0x1C
-#define BD9995X_CMD_VRECHG_SET		0x1D
-#define BD9995X_CMD_VBATOVP_SET		0x1E
-#define BD9995X_CMD_IBATSHORT_SET	0x1F
-#define BD9995X_CMD_PROCHOT_CTRL_SET	0x20
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4	BIT(4)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3	BIT(3)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2	BIT(2)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1	BIT(1)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0	BIT(0)
-
-#define BD9995X_CMD_PROCHOT_ICRIT_SET	0x21
-#define BD9995X_CMD_PROCHOT_INORM_SET	0x22
-#define BD9995X_CMD_PROCHOT_IDCHG_SET	0x23
-#define BD9995X_CMD_PROCHOT_VSYS_SET	0x24
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET	0x25
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL	BIT(9)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL	BIT(8)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN	BIT(7)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL	BIT(6)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK	0x30
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V	0x00
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN	BIT(3)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK	0x07
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW	0x06
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW	0x05
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW	0x04
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW	0x00
-#define BD9995X_PMON_IOUT_ADC_READ_COUNT	128
-
-#define BD9995X_CMD_PMON_DACIN_VAL	0x26
-#define BD9995X_CMD_IOUT_DACIN_VAL	0x27
-#define BD9995X_CMD_VCC_UCD_SET		0x28
-/* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */
-/*  Retry BC1.2 detection on set */
-#define BD9995X_CMD_UCD_SET_BCSRETRY	BIT(12)
-/* Enable BC1.2 detection, will automatically occur on VBUS detect */
-#define BD9995X_CMD_UCD_SET_USBDETEN	BIT(7)
-/* USB switch state auto-control */
-#define BD9995X_CMD_UCD_SET_USB_SW_EN	BIT(1)
-/* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */
-#define BD9995X_CMD_UCD_SET_USB_SW	BIT(0)
-
-#define BD9995X_CMD_VCC_UCD_STATUS	0x29
-/* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */
-#define BD9995X_CMD_UCD_STATUS_DCDFAIL	BIT(15)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT1	BIT(13)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT0	BIT(12)
-#define BD9995X_CMD_UCD_STATUS_PUPDET	BIT(11)
-#define BD9995X_CMD_UCD_STATUS_CHGDET	BIT(6)
-#define BD9995X_TYPE_MASK		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-
-/* BC1.2 chargers */
-#define BD9995X_TYPE_CDP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_DCP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_SDP		(BD9995X_CMD_UCD_STATUS_CHGPORT0)
-/* non-standard BC1.2 chargers */
-#define BD9995X_TYPE_OTHER		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_PUP_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET)
-/* Open ports */
-#define BD9995X_TYPE_OPEN_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0)
-#define BD9995X_TYPE_VBUS_OPEN		0
-
-#define BD9995X_CMD_VCC_IDD_STATUS	0x2A
-#define BD9995X_CMD_VCC_UCD_FCTRL_SET	0x2B
-#define BD9995X_CMD_VCC_UCD_FCTRL_EN	0x2C
-#define BD9995X_CMD_VBUS_UCD_SET	0x30
-#define BD9995X_CMD_VBUS_UCD_STATUS	0x31
-#define BD9995X_CMD_VBUS_IDD_STATUS	0x32
-#define BD9995X_CMD_VBUS_UCD_FCTRL_SET	0x33
-#define BD9995X_CMD_VBUS_UCD_FCTRL_EN	0x34
-#define BD9995X_CMD_CHIP_ID		0x38
-#define BD9995X_CMD_CHIP_REV		0x39
-#define BD9995X_CMD_IC_SET1		0x3A
-#define BD9995X_CMD_IC_SET2		0x3B
-#define BD9995X_CMD_SYSTEM_STATUS	0x3C
-#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE	BIT(1)
-#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE	BIT(0)
-
-#define BD9995X_CMD_SYSTEM_CTRL_SET	0x3D
-#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD	BIT(1)
-#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST	BIT(0)
-
-#define BD9995X_CMD_EXT_PROTECT_SET	0x3E
-#define BD9995X_CMD_EXT_MAP_SET		0x3F
-#define BD9995X_CMD_VM_CTRL_SET		0x40
-#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN	BIT(9)
-#define BD9995X_CMD_THERM_WINDOW_SET1	0x41
-#define BD9995X_CMD_THERM_WINDOW_SET2	0x42
-#define BD9995X_CMD_THERM_WINDOW_SET3	0x43
-#define BD9995X_CMD_THERM_WINDOW_SET4	0x44
-#define BD9995X_CMD_THERM_WINDOW_SET5	0x45
-#define BD9995X_CMD_IBATP_TH_SET	0x46
-#define BD9995X_CMD_IBATM_TH_SET	0x47
-#define BD9995X_CMD_VBAT_TH_SET		0x48
-#define BD9995X_CMD_THERM_TH_SET	0x49
-#define BD9995X_CMD_IACP_TH_SET		0x4A
-#define BD9995X_CMD_VACP_TH_SET		0x4B
-
-/* Enable discharge when VBUS falls below BD9995X_VBUS_DISCHARGE_TH */
-#define BD9995X_VBUS_DISCHARGE_TH	3900
-#define BD9995X_CMD_VBUS_TH_SET		0x4C
-#define BD9995X_CMD_VCC_TH_SET		0x4D
-
-#define BD9995X_CMD_VSYS_TH_SET		0x4E
-#define BD9995X_CMD_EXTIADP_TH_SET	0x4F
-#define BD9995X_CMD_IBATP_VAL		0x50
-#define BD9995X_CMD_IBATP_AVE_VAL	0x51
-#define BD9995X_CMD_IBATM_VAL		0x52
-#define BD9995X_CMD_IBATM_AVE_VAL	0x53
-#define BD9995X_CMD_VBAT_VAL		0x54
-#define BD9995X_CMD_VBAT_AVE_VAL	0x55
-#define BD9995X_CMD_THERM_VAL		0x56
-#define BD9995X_CMD_VTH_VAL		0x57
-#define BD9995X_CMD_IACP_VAL		0x58
-#define BD9995X_CMD_IACP_AVE_VAL	0x59
-#define BD9995X_CMD_VACP_VAL		0x5A
-#define BD9995X_CMD_VACP_AVE_VAL	0x5B
-#define BD9995X_CMD_VBUS_VAL		0x5C
-#define BD9995X_CMD_VBUS_AVE_VAL	0x5D
-#define BD9995X_CMD_VCC_VAL		0x5E
-#define BD9995X_CMD_VCC_AVE_VAL		0x5F
-#define BD9995X_CMD_VSYS_VAL		0x60
-#define BD9995X_CMD_VSYS_AVE_VAL	0x61
-#define BD9995X_CMD_EXTIADP_VAL		0x62
-#define BD9995X_CMD_EXTIADP_AVE_VAL	0x63
-#define BD9995X_CMD_VACPCLPS_TH_SET	0x64
-#define BD9995X_CMD_INT0_SET		0x68
-#define BD9995X_CMD_INT0_SET_INT2_EN	BIT(2)
-#define BD9995X_CMD_INT0_SET_INT1_EN	BIT(1)
-#define BD9995X_CMD_INT0_SET_INT0_EN	BIT(0)
-
-#define BD9995X_CMD_INT1_SET		0x69
-/* Bits for both INT1 & INT2 reg */
-#define BD9995X_CMD_INT_SET_TH_DET	BIT(9)
-#define BD9995X_CMD_INT_SET_TH_RES	BIT(8)
-#define BD9995X_CMD_INT_SET_DET		BIT(1)
-#define BD9995X_CMD_INT_SET_RES		BIT(0)
-#define BD9995X_CMD_INT_VBUS_DET	(BD9995X_CMD_INT_SET_RES | \
-					 BD9995X_CMD_INT_SET_DET)
-#define BD9995X_CMD_INT_VBUS_TH         (BD9995X_CMD_INT_SET_TH_RES | \
-					 BD9995X_CMD_INT_SET_TH_DET)
-
-#define BD9995X_CMD_INT2_SET		0x6A
-#define BD9995X_CMD_INT3_SET		0x6B
-#define BD9995X_CMD_INT4_SET		0x6C
-#define BD9995X_CMD_INT5_SET		0x6D
-#define BD9995X_CMD_INT6_SET		0x6E
-#define BD9995X_CMD_INT7_SET		0x6F
-#define BD9995X_CMD_INT0_STATUS		0x70
-#define BD9995X_CMD_INT1_STATUS		0x71
-/* Bits for both INT1_STATUS & INT2_STATUS reg */
-#define BD9995X_CMD_INT_STATUS_DET	BIT(1)
-#define BD9995X_CMD_INT_STATUS_RES	BIT(0)
-
-#define BD9995X_CMD_INT2_STATUS		0x72
-#define BD9995X_CMD_INT3_STATUS		0x73
-#define BD9995X_CMD_INT4_STATUS		0x74
-#define BD9995X_CMD_INT5_STATUS		0x75
-#define BD9995X_CMD_INT6_STATUS		0x76
-#define BD9995X_CMD_INT7_STATUS		0x77
-#define BD9995X_CMD_REG0		0x78
-#define BD9995X_CMD_REG1		0x79
-#define BD9995X_CMD_OTPREG0		0x7A
-#define BD9995X_CMD_OTPREG1		0x7B
-#define BD9995X_CMD_SMBREG		0x7C
-/* Normal functionality - power save mode disabled. */
-#define BD9995X_PWR_SAVE_OFF		0
-/* BGATE ON w/ PROCHOT# monitored only system voltage. */
-#define BD9995X_PWR_SAVE_LOW		0x1
-/* BGATE ON w/ PROCHOT# monitored only system voltage every 1ms. */
-#define BD9995X_PWR_SAVE_MED		0x2
-/* BGATE ON w/o PROCHOT# monitoring. */
-#define BD9995X_PWR_SAVE_HIGH		0x5
-/* BGATE OFF */
-#define BD9995X_PWR_SAVE_MAX		0x6
-#define BD9995X_CMD_DEBUG_MODE_SET	0x7F
-
-/*
- * Non-standard interface functions - bd9995x integrates additional
- * functionality not part of the standard charger interface.
- */
-
-/* Is VBUS provided or external power present */
-int bd9995x_is_vbus_provided(enum bd9995x_charge_port port);
-/* Select or deselect input port from {VCC, VBUS, VCC&VBUS}. */
-int bd9995x_select_input_port(enum bd9995x_charge_port port, int select);
-/* Enable/Disable charging triggered by BC1.2 */
-int bd9995x_bc12_enable_charging(int port, int enable);
-/* Interrupt handler for USB charger VBUS */
-void bd9995x_vbus_interrupt(enum gpio_signal signal);
-/* Read temperature measurement value (in Celsius) */
-int bd9995x_get_battery_temp(int *temp_ptr);
-/* Set power save mode */
-void bd9995x_set_power_save_mode(int mode);
-/* Get Battery Voltage Measurement Value */
-int bd9995x_get_battery_voltage(void);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-extern struct i2c_stress_test_dev bd9995x_i2c_stress_test_dev;
-#endif
-
-extern const struct charger_drv bd9995x_drv;
-
-#endif /* __CROS_EC_BD9995X_H */
diff --git a/driver/charger/bq24715.c b/driver/charger/bq24715.c
deleted file mode 100644
index d2eb0e432a..0000000000
--- a/driver/charger/bq24715.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq24715 battery charger driver.
- */
-
-#include "battery_smart.h"
-#include "bq24715.h"
-#include "charger.h"
-#include "console.h"
-#include "common.h"
-#include "i2c.h"
-#include "util.h"
-
-/* Sense resistor configurations and macros */
-#define DEFAULT_SENSE_RESISTOR 10
-#define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
-#define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
-
-/* Note: it is assumed that the sense resistors are 10mOhm. */
-
-static const struct charger_info bq24715_charger_info = {
-	.name         = "bq24715",
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
-	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
-	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
-};
-
-static inline enum ec_error_list sbc_read(int chgnum, int cmd, int *param)
-{
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  cmd, param);
-}
-
-static inline enum ec_error_list sbc_write(int chgnum, int cmd, int param)
-{
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   cmd, param);
-}
-
-static enum ec_error_list bq24715_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-	return sbc_write(chgnum, BQ24715_INPUT_CURRENT,
-			 CURRENT_TO_REG(input_current, R_AC));
-}
-
-static enum ec_error_list bq24715_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	int rv;
-	int reg;
-
-	rv = sbc_read(chgnum, BQ24715_INPUT_CURRENT, &reg);
-	if (rv)
-		return rv;
-
-	*input_current = REG_TO_CURRENT(reg, R_AC);
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq24715_manufacturer_id(int chgnum, int *id)
-{
-	return sbc_read(chgnum, BQ24715_MANUFACTURER_ID, id);
-}
-
-static enum ec_error_list bq24715_device_id(int chgnum, int *id)
-{
-	return sbc_read(chgnum, BQ24715_DEVICE_ID, id);
-}
-
-static enum ec_error_list bq24715_get_option(int chgnum, int *option)
-{
-	return sbc_read(chgnum, BQ24715_CHARGE_OPTION, option);
-}
-
-static enum ec_error_list bq24715_set_option(int chgnum, int option)
-{
-	return sbc_write(chgnum, BQ24715_CHARGE_OPTION, option);
-}
-
-/* Charger interfaces */
-
-static const struct charger_info *bq24715_get_info(int chgnum)
-{
-	return &bq24715_charger_info;
-}
-
-static enum ec_error_list bq24715_get_status(int chgnum, int *status)
-{
-	int rv;
-	int option;
-
-	rv = bq24715_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	/* Default status */
-	*status = CHARGER_LEVEL_2;
-
-	if ((option & OPT_CHARGE_INHIBIT_MASK) == OPT_CHARGE_DISABLE)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq24715_set_mode(int chgnum, int mode)
-{
-	int rv;
-	int option;
-
-	rv = bq24715_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	option &= ~OPT_CHARGE_INHIBIT_MASK;
-	if (mode & CHARGE_FLAG_INHIBIT_CHARGE)
-		option |= OPT_CHARGE_DISABLE;
-	else
-		option |= OPT_CHARGE_ENABLE;
-	return bq24715_set_option(chgnum, option);
-}
-
-static enum ec_error_list bq24715_get_current(int chgnum, int *current)
-{
-	int rv;
-	int reg;
-
-	rv = sbc_read(chgnum, SB_CHARGING_CURRENT, &reg);
-	if (rv)
-		return rv;
-
-	*current = REG_TO_CURRENT(reg, R_SNS);
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq24715_set_current(int chgnum, int current)
-{
-	current = charger_closest_current(current);
-
-	return sbc_write(chgnum, SB_CHARGING_CURRENT,
-			 CURRENT_TO_REG(current, R_SNS));
-}
-
-/* The voltage setting needs to be cached to work with the current
- * charging infrastructure and state machine. The reason is that
- * the state machine expects to be able to set a 0V charging voltage.
- * The bq24715 does not allow this in the hardware register. Therefore
- * 0V is handled specially to appease the state machine. */
-static int cached_voltage;
-
-static enum ec_error_list bq24715_get_voltage(int chgnum, int *voltage)
-{
-	int ret;
-
-	if (cached_voltage == 0) {
-		*voltage = cached_voltage;
-		return EC_SUCCESS;
-	}
-
-	ret = sbc_read(chgnum, SB_CHARGING_VOLTAGE, &cached_voltage);
-
-	if (ret == EC_SUCCESS)
-		*voltage = cached_voltage;
-
-	return ret;
-}
-
-static enum ec_error_list bq24715_set_voltage(int chgnum, int voltage)
-{
-	cached_voltage = voltage;
-	return sbc_write(chgnum, SB_CHARGING_VOLTAGE, voltage);
-}
-
-/* Charging power state initialization */
-static enum ec_error_list bq24715_post_init(int chgnum)
-{
-	int rv;
-	int option;
-
-	rv = bq24715_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	/* Don't be noisy */
-	option |= OPT_AUDIO_FREQ_40KHZ_LIMIT;
-
-	/* Always monitor adapter current (40X multiplier). */
-	option |= OPT_FIX_IOUT_ALWAYS;
-	option &= ~OPT_IOUT_MASK;
-	option &= ~OPT_LEARN_MASK;
-
-	/* Enable dynamic power management */
-	option |= OPT_IDPM_ENABLE;
-
-	rv = bq24715_set_option(chgnum, option);
-	if (rv)
-		return rv;
-
-	rv = bq24715_set_input_current_limit(chgnum,
-					     CONFIG_CHARGER_INPUT_CURRENT);
-	return rv;
-}
-
-static enum ec_error_list bq24715_discharge_on_ac(int chgnum, int enable)
-{
-	int rv;
-	int option;
-
-	rv = bq24715_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	option &= ~OPT_LEARN_MASK;
-	if (enable)
-		option |= OPT_LEARN_ENABLE;
-	else
-		option |= OPT_LEARN_DISABLE;
-	rv = bq24715_set_option(chgnum, option);
-
-	return rv;
-}
-
-const struct charger_drv bq24715_drv = {
-	.post_init = &bq24715_post_init,
-	.get_info = &bq24715_get_info,
-	.get_status = &bq24715_get_status,
-	.set_mode = &bq24715_set_mode,
-	.get_current = &bq24715_get_current,
-	.set_current = &bq24715_set_current,
-	.get_voltage = &bq24715_get_voltage,
-	.set_voltage = &bq24715_set_voltage,
-	.discharge_on_ac = &bq24715_discharge_on_ac,
-	.set_input_current_limit = &bq24715_set_input_current_limit,
-	.get_input_current_limit = &bq24715_get_input_current_limit,
-	.manufacturer_id = &bq24715_manufacturer_id,
-	.device_id = &bq24715_device_id,
-	.get_option = &bq24715_get_option,
-	.set_option = &bq24715_set_option,
-};
diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h
deleted file mode 100644
index 644f995f2e..0000000000
--- a/driver/charger/bq24715.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq24715 battery charger driver.
- */
-
-#ifndef __CROS_EC_BQ24715_H
-#define __CROS_EC_BQ24715_H
-
-/* NOTES:
- * If battery is not present keep charge current register (0x14) at 0.
- * Max charge voltage (0x15) needs to be programmed before 0x14.
- */
-
-/* Chip specific registers */
-#define BQ24715_CHARGE_OPTION           0x12
-#define BQ24715_CHARGE_CURRENT          0x14
-#define BQ24715_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24715_MIN_SYSTEM_VOLTAGE      0x3e
-#define BQ24715_INPUT_CURRENT           0x3f
-#define BQ24715_MANUFACTURER_ID         0xfe
-#define BQ24715_DEVICE_ID               0xff
-
-/* ChargeOption Register - 0x12 */
-#define OPT_LOWPOWER_MASK               BIT(15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_ON    (0 << 15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_OFF   BIT(15)
-#define OPT_WATCHDOG_MASK               (3 << 13)
-#define   OPT_WATCHDOG_DISABLE            (0 << 13)
-#define   OPT_WATCHDOG_44SEC              BIT(13)
-#define   OPT_WATCHDOG_88SEC              (2 << 13)
-#define   OPT_WATCHDOG_175SEC             (3 << 13)
-#define OPT_SYSOVP_MASK                 BIT(12)
-#define   OPT_SYSOVP_15P1_3SEC_10P1_2SEC  (0 << 12)
-#define   OPT_SYSOVP_17P0_3SEC_11P3_2SEC  BIT(12)
-#define OPT_SYSOVP_STATUS_MASK          BIT(11)
-#define   OPT_SYSOVP_STATUS               BIT(11)
-#define OPT_AUDIO_FREQ_LIMIT_MASK       BIT(10)
-#define   OPT_AUDIO_FREQ_NO_LIMIT         (0 << 10)
-#define   OPT_AUDIO_FREQ_40KHZ_LIMIT      BIT(10)
-#define OPT_SWITCH_FREQ_MASK            (3 << 8)
-#define   OPT_SWITCH_FREQ_600KHZ          (0 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ          BIT(8)
-#define   OPT_SWITCH_FREQ_1MHZ            (2 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ_DUP      (3 << 8)
-#define OPT_ACOC_MASK                   BIT(7)
-#define   OPT_ACOC_DISABLED               (0 << 7)
-#define   OPT_ACOC_333PCT_IPDM            BIT(7)
-#define OPT_LSFET_OCP_MASK              BIT(6)
-#define   OPT_LSFET_OCP_250MV             (0 << 6)
-#define   OPT_LSFET_OCP_350MV             BIT(6)
-#define OPT_LEARN_MASK                  BIT(5)
-#define   OPT_LEARN_DISABLE               (0 << 5)
-#define   OPT_LEARN_ENABLE                BIT(5)
-#define OPT_IOUT_MASK                   BIT(4)
-#define   OPT_IOUT_40X                    (0 << 4)
-#define   OPT_IOUT_16X                    BIT(4)
-#define OPT_FIX_IOUT_MASK               BIT(3)
-#define   OPT_FIX_IOUT_IDPM_EN            (0 << 3)
-#define   OPT_FIX_IOUT_ALWAYS             BIT(3)
-#define OPT_LDO_MODE_MASK               BIT(2)
-#define   OPT_LDO_DISABLE                 (0 << 2)
-#define   OPT_LDO_ENABLE                  BIT(2)
-#define OPT_IDPM_MASK                   BIT(1)
-#define   OPT_IDPM_DISABLE                (0 << 1)
-#define   OPT_IDPM_ENABLE                 BIT(1)
-#define OPT_CHARGE_INHIBIT_MASK         BIT(0)
-#define   OPT_CHARGE_ENABLE               (0 << 0)
-#define   OPT_CHARGE_DISABLE              BIT(0)
-
-
-/* ChargeCurrent Register - 0x14
- * The ChargeCurrent register controls a DAC. Therefore
- * the below definitions are cummulative. */
-#define CHARGE_I_64MA                   BIT(6)
-#define CHARGE_I_128MA                  BIT(7)
-#define CHARGE_I_256MA                  BIT(8)
-#define CHARGE_I_512MA                  BIT(9)
-#define CHARGE_I_1024MA                 BIT(10)
-#define CHARGE_I_2048MA                 BIT(11)
-#define CHARGE_I_4096MA                 BIT(12)
-#define CHARGE_I_OFF                    (0)
-#define CHARGE_I_MIN                    (128)
-#define CHARGE_I_MAX                    (8128)
-#define CHARGE_I_STEP                   (64)
-
-/* MaxChargeVoltage Register - 0x15
- * The MaxChargeVoltage register controls a DAC. Therefore
- * the below definitions are cummulative. */
-#define CHARGE_V_16MV                   BIT(4)
-#define CHARGE_V_32MV                   BIT(5)
-#define CHARGE_V_64MV                   BIT(6)
-#define CHARGE_V_128MV                  BIT(7)
-#define CHARGE_V_256MV                  BIT(8)
-#define CHARGE_V_512MV                  BIT(9)
-#define CHARGE_V_1024MV                 BIT(10)
-#define CHARGE_V_2048MV                 BIT(11)
-#define CHARGE_V_4096MV                 BIT(12)
-#define CHARGE_V_8192MV                 BIT(13)
-#define CHARGE_V_MIN                    (4096)
-#define CHARGE_V_MAX                    (0x3ff0)
-#define CHARGE_V_STEP                   (16)
-
-/* MinSystemVoltage Register - 0x3e
- * The MinSystemVoltage register controls a DAC. Therefore
- * the below definitions are cummulative. */
-#define MIN_SYS_V_256MV                 BIT(8)
-#define MIN_SYS_V_512MV                 BIT(9)
-#define MIN_SYS_V_1024MV                BIT(10)
-#define MIN_SYS_V_2048MV                BIT(11)
-#define MIN_SYS_V_4096MV                BIT(12)
-#define MIN_SYS_V_8192MV                BIT(13)
-#define MIN_SYS_V_MIN                   (4096)
-
-/* InputCurrent Register - 0x3f
- * The InputCurrent register controls a DAC. Therefore
- * the below definitions are cummulative. */
-#define INPUT_I_64MA                   BIT(6)
-#define INPUT_I_128MA                  BIT(7)
-#define INPUT_I_256MA                  BIT(8)
-#define INPUT_I_512MA                  BIT(9)
-#define INPUT_I_1024MA                 BIT(10)
-#define INPUT_I_2048MA                 BIT(11)
-#define INPUT_I_4096MA                 BIT(12)
-#define INPUT_I_MIN                    (128)
-#define INPUT_I_MAX                    (8064)
-#define INPUT_I_STEP                   (64)
-
-extern const struct charger_drv bq24715_drv;
-
-#endif /* __CROS_EC_BQ24715_H */
diff --git a/driver/charger/bq24773.c b/driver/charger/bq24773.c
deleted file mode 100644
index d242f105c6..0000000000
--- a/driver/charger/bq24773.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq24773 battery charger driver.
- */
-
-#include "battery_smart.h"
-#include "bq24773.h"
-#include "charger.h"
-#include "console.h"
-#include "common.h"
-#include "util.h"
-
-/*
- * on the I2C version of the charger,
- * some registers are 8-bit only (eg input current)
- * and they are shifted by 6 bits compared to the SMBUS version (bq24770).
- */
-#define REG8_SHIFT 6
-#define R8 (1 << (REG8_SHIFT))
-/* Sense resistor configurations and macros */
-#define DEFAULT_SENSE_RESISTOR 10
-#define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  (CONFIG_CHARGER_SENSE_RESISTOR_AC)
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
-#define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
-#define REG8_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS) * R8)
-#define CURRENT_TO_REG8(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR / R8)
-
-/* ChargeCurrent Register - 0x14 (mA) */
-#define CHARGE_I_OFF                    0
-#define CHARGE_I_MIN                    128
-#define CHARGE_I_MAX                    8128
-#define CHARGE_I_STEP                   64
-
-/* MaxChargeVoltage Register - 0x15 (mV) */
-#define CHARGE_V_MIN                    1024
-#define CHARGE_V_MAX                    19200
-#define CHARGE_V_STEP                   16
-
-/* InputCurrent Register - 0x3f (mA) */
-#define INPUT_I_MIN                    128
-#define INPUT_I_MAX                    8128
-#define INPUT_I_STEP                   64
-
-/* Charger parameters */
-static const struct charger_info bq2477x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
-	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
-	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
-};
-
-#ifdef CONFIG_CHARGER_BQ24773
-static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
-}
-
-static inline enum ec_error_list raw_write8(int chgnum, int offset, int value)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-#endif
-
-static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
-{
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-
-static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
-{
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
-}
-
-
-/* chip specific interfaces */
-
-static enum ec_error_list bq2477x_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-#ifdef CONFIG_CHARGER_BQ24770
-	return raw_write16(chgnum, REG_INPUT_CURRENT,
-			   CURRENT_TO_REG(input_current, R_AC));
-#elif defined(CONFIG_CHARGER_BQ24773)
-	return raw_write8(chgnum, REG_INPUT_CURRENT,
-			  CURRENT_TO_REG8(input_current, R_AC));
-#endif
-}
-
-static enum ec_error_list bq2477x_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	int rv;
-	int reg;
-
-#ifdef CONFIG_CHARGER_BQ24770
-	rv = raw_read16(chgnum, REG_INPUT_CURRENT, &reg);
-#elif defined(CONFIG_CHARGER_BQ24773)
-	rv = raw_read8(chgnum, REG_INPUT_CURRENT, &reg);
-#endif
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_CHARGER_BQ24770
-	*input_current = REG_TO_CURRENT(reg, R_AC);
-#elif defined(CONFIG_CHARGER_BQ24773)
-	*input_current = REG8_TO_CURRENT(reg, R_AC);
-#endif
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq2477x_manufacturer_id(int chgnum, int *id)
-{
-#ifdef CONFIG_CHARGER_BQ24770
-	return raw_read16(chgnum, REG_MANUFACTURE_ID, id);
-#elif defined(CONFIG_CHARGER_BQ24773)
-	*id = 0x40; /* TI */
-	return EC_SUCCESS;
-#endif
-}
-
-static enum ec_error_list bq2477x_device_id(int chgnum, int *id)
-{
-#ifdef CONFIG_CHARGER_BQ24770
-	return raw_read16(chgnum, REG_DEVICE_ADDRESS, id);
-#elif defined(CONFIG_CHARGER_BQ24773)
-	return raw_read8(chgnum, REG_DEVICE_ADDRESS, id);
-#endif
-}
-
-static enum ec_error_list bq2477x_get_option(int chgnum, int *option)
-{
-	return raw_read16(chgnum, REG_CHARGE_OPTION0, option);
-}
-
-static enum ec_error_list bq2477x_set_option(int chgnum, int option)
-{
-	return raw_write16(chgnum, REG_CHARGE_OPTION0, option);
-}
-
-/* Charger interfaces */
-
-static const struct charger_info *bq2477x_get_info(int chgnum)
-{
-	return &bq2477x_charger_info;
-}
-
-static enum ec_error_list bq2477x_get_status(int chgnum, int *status)
-{
-	int rv;
-	int option;
-
-	rv = bq2477x_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	/* Default status */
-	*status = CHARGER_LEVEL_2;
-
-	if (option & OPTION0_CHARGE_INHIBIT)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq2477x_set_mode(int chgnum, int mode)
-{
-	int rv;
-	int option;
-
-	rv = bq2477x_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	if (mode & CHARGE_FLAG_INHIBIT_CHARGE)
-		option |= OPTION0_CHARGE_INHIBIT;
-	else
-		option &= ~OPTION0_CHARGE_INHIBIT;
-	return bq2477x_set_option(chgnum, option);
-}
-
-static enum ec_error_list bq2477x_get_current(int chgnum, int *current)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, REG_CHARGE_CURRENT, &reg);
-
-	if (rv)
-		return rv;
-
-	*current = REG_TO_CURRENT(reg, R_SNS);
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq2477x_set_current(int chgnum, int current)
-{
-	current = charger_closest_current(current);
-	return raw_write16(chgnum, REG_CHARGE_CURRENT,
-			   CURRENT_TO_REG(current, R_SNS));
-}
-
-static enum ec_error_list bq2477x_get_voltage(int chgnum, int *voltage)
-{
-	return raw_read16(chgnum, REG_MAX_CHARGE_VOLTAGE, voltage);
-}
-
-static enum ec_error_list bq2477x_set_voltage(int chgnum, int voltage)
-{
-	voltage = charger_closest_voltage(voltage);
-	return raw_write16(chgnum, REG_MAX_CHARGE_VOLTAGE, voltage);
-}
-
-/* Charging power state initialization */
-static enum ec_error_list bq2477x_post_init(int chgnum)
-{
-	int rv, option;
-#ifdef CONFIG_CHARGER_ILIM_PIN_DISABLED
-	int option2;
-#endif
-
-	rv = bq2477x_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	option &= ~OPTION0_LEARN_ENABLE;
-	rv = bq2477x_set_option(chgnum, option);
-	if (rv)
-		return rv;
-
-	/* Turn off PROCHOT warning */
-	rv = raw_read16(chgnum, REG_PROCHOT_OPTION1, &option);
-	if (rv)
-		return rv;
-
-	option &= ~PROCHOT_OPTION1_SELECTOR_MASK;
-	rv = raw_write16(chgnum, REG_PROCHOT_OPTION1, option);
-
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_CHARGER_ILIM_PIN_DISABLED
-	/* Read the external ILIM pin enabled flag. */
-	rv = raw_read16(chgnum, REG_CHARGE_OPTION2, &option2);
-	if (rv)
-		return rv;
-
-	/* Set ILIM pin disabled if it is currently enabled. */
-	if (option2 & OPTION2_EN_EXTILIM) {
-		option2 &= ~OPTION2_EN_EXTILIM;
-		rv = raw_write16(chgnum, REG_CHARGE_OPTION2, option2);
-	}
-	return rv;
-#else
-	return EC_SUCCESS;
-#endif
-}
-
-static enum ec_error_list bq2477x_discharge_on_ac(int chgnum, int enable)
-{
-	int rv;
-	int option;
-
-	rv = bq2477x_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	if (enable)
-		rv = bq2477x_set_option(chgnum, option | OPTION0_LEARN_ENABLE);
-	else
-		rv = bq2477x_set_option(chgnum, option & ~OPTION0_LEARN_ENABLE);
-
-	return rv;
-}
-
-const struct charger_drv bq2477x_drv = {
-	.post_init = &bq2477x_post_init,
-	.get_info = &bq2477x_get_info,
-	.get_status = &bq2477x_get_status,
-	.set_mode = &bq2477x_set_mode,
-	.get_current = &bq2477x_get_current,
-	.set_current = &bq2477x_set_current,
-	.get_voltage = &bq2477x_get_voltage,
-	.set_voltage = &bq2477x_set_voltage,
-	.discharge_on_ac = &bq2477x_discharge_on_ac,
-	.set_input_current_limit = &bq2477x_set_input_current_limit,
-	.get_input_current_limit = &bq2477x_get_input_current_limit,
-	.manufacturer_id = &bq2477x_manufacturer_id,
-	.device_id = &bq2477x_device_id,
-	.get_option = &bq2477x_get_option,
-	.set_option = &bq2477x_set_option,
-};
diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h
deleted file mode 100644
index 46f8939036..0000000000
--- a/driver/charger/bq24773.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq24773 battery charger driver.
- */
-
-#ifndef __CROS_EC_BQ24773_H
-#define __CROS_EC_BQ24773_H
-
-/* for i2c_read and i2c_write functions. */
-#include "i2c.h"
-
-/* I2C address */
-#define BQ24770_ADDR_FLAGS	0x09
-#define BQ24773_ADDR_FLAGS	0x6a
-
-/* Chip specific commands */
-#define BQ24770_CHARGE_OPTION0          0x12
-#define BQ24770_CHARGE_OPTION1          0x3B
-#define BQ24770_CHARGE_OPTION2          0x38
-#define BQ24770_PROCHOT_OPTION0         0x3C
-#define BQ24770_PROCHOT_OPTION1         0x3D
-#define BQ24770_CHARGE_CURRENT          0x14
-#define BQ24770_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24770_MIN_SYSTEM_VOLTAGE      0x3E
-#define BQ24770_INPUT_CURRENT           0x3F
-#define BQ24770_MANUFACTURE_ID          0xFE
-#define BQ24770_DEVICE_ADDRESS          0xFF
-
-#define BQ24773_CHARGE_OPTION0          0x00
-#define BQ24773_CHARGE_OPTION1          0x02
-#define BQ24773_PROCHOT_OPTION0         0x04
-#define BQ24773_PROCHOT_OPTION1         0x06
-#define BQ24773_PROCHOT_STATUS          0x08
-#define BQ24773_DEVICE_ADDRESS          0x09
-#define BQ24773_CHARGE_CURRENT          0x0A
-#define BQ24773_MAX_CHARGE_VOLTAGE      0x0C
-#define BQ24773_MIN_SYSTEM_VOLTAGE      0x0E
-#define BQ24773_INPUT_CURRENT           0x0F
-#define BQ24773_CHARGE_OPTION2          0x10
-
-/* Option bits */
-#define OPTION0_CHARGE_INHIBIT          BIT(0)
-#define OPTION0_LEARN_ENABLE            BIT(5)
-#define OPTION0_SWITCHING_FREQ_MASK     (3 << 8)
-#define OPTION0_SWITCHING_FREQ_600KHZ   (0 << 8)
-#define OPTION0_SWITCHING_FREQ_800KHZ   BIT(8)
-#define OPTION0_SWITCHING_FREQ_1000KHZ  (2 << 8)
-#define OPTION0_SWITCHING_FREQ_1200KHZ  (3 << 8)
-
-#define OPTION2_EN_EXTILIM              BIT(7)
-
-/* Prochot Option bits */
-#define PROCHOT_OPTION1_SELECTOR_MASK   0x7f /* [6:0] PROCHOT SELECTOR */
-
-#ifdef CONFIG_CHARGER_BQ24770
-	#define CHARGER_NAME		"bq24770"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24770_ADDR_FLAGS
-
-	#define REG_CHARGE_OPTION0	BQ24770_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24770_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24770_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24770_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24770_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24770_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24770_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24770_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24770_INPUT_CURRENT
-	#define REG_MANUFACTURE_ID	BQ24770_MANUFACTURE_ID
-	#define REG_DEVICE_ADDRESS	BQ24770_DEVICE_ADDRESS
-
-#elif defined(CONFIG_CHARGER_BQ24773)
-	#define CHARGER_NAME		"bq24773"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24773_ADDR_FLAGS
-
-	#define REG_CHARGE_OPTION0	BQ24773_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24773_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24773_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24773_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24773_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24773_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24773_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24773_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24773_INPUT_CURRENT
-	#define REG_DEVICE_ADDRESS	BQ24773_DEVICE_ADDRESS
-#endif
-
-extern const struct charger_drv bq2477x_drv;
-
-#endif /* __CROS_EC_BQ24773_H */
diff --git a/driver/charger/bq25710.c b/driver/charger/bq25710.c
deleted file mode 100644
index df898467be..0000000000
--- a/driver/charger/bq25710.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq25710 battery charger driver.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "bq25710.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-#ifndef CONFIG_CHARGER_NARROW_VDC
-#error "BQ25710 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
-#endif
-
-/*
- * Delay required from taking the bq25710 out of low power mode and having the
- * correct value in register 0x3E for VSYS_MIN voltage. The length of the delay
- * was determined by experiment. Less than 12 msec was not enough of delay, so
- * the value here is set to 20 msec to have plenty of margin.
- */
-#define BQ25710_VDDA_STARTUP_DELAY_MSEC 20
-
-/* Sense resistor configurations and macros */
-#define DEFAULT_SENSE_RESISTOR 10
-
-#ifdef CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710
-	#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
-		CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710
-#endif
-
-
-#define INPUT_RESISTOR_RATIO \
-	((CONFIG_CHARGER_SENSE_RESISTOR_AC) / DEFAULT_SENSE_RESISTOR)
-
-#define CHARGING_RESISTOR_RATIO \
-	((CONFIG_CHARGER_SENSE_RESISTOR) / DEFAULT_SENSE_RESISTOR)
-#define REG_TO_CHARGING_CURRENT(REG) ((REG) / CHARGING_RESISTOR_RATIO)
-#define CHARGING_CURRENT_TO_REG(CUR) ((CUR) * CHARGING_RESISTOR_RATIO)
-#ifdef CONFIG_CHARGER_BQ25720
-#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV) - 32)
-#endif
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-/*
- * If this config option is defined, then the bq25710 needs to remain in
- * performance mode when the AP is in S0. Performance mode is active whenever AC
- * power is connected or when the EN_LWPWR bit in ChargeOption0 is clear.
- */
-static uint32_t bq25710_perf_mode_req;
-static struct mutex bq25710_perf_mode_mutex;
-#endif
-
-/* Charger parameters */
-static const struct charger_info bq25710_charger_info = {
-	.name         = "bq25710",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
-	.voltage_step = 8,
-	.current_max  = 8128 / CHARGING_RESISTOR_RATIO,
-	.current_min  = 64 / CHARGING_RESISTOR_RATIO,
-	.current_step = 64 / CHARGING_RESISTOR_RATIO,
-	.input_current_max  = 6400 / INPUT_RESISTOR_RATIO,
-	.input_current_min  = 50 / INPUT_RESISTOR_RATIO,
-	.input_current_step = 50 / INPUT_RESISTOR_RATIO,
-};
-
-static enum ec_error_list bq25710_get_option(int chgnum, int *option);
-static enum ec_error_list bq25710_set_option(int chgnum, int option);
-
-static inline int iin_dpm_reg_to_current(int reg)
-{
-	return (reg + 1) * BQ25710_IIN_DPM_CURRENT_STEP_MA /
-		INPUT_RESISTOR_RATIO;
-}
-
-static inline int iin_host_current_to_reg(int current)
-{
-	return (current * INPUT_RESISTOR_RATIO /
-		BQ25710_IIN_HOST_CURRENT_STEP_MA) - 1;
-}
-
-static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
-{
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-
-static inline int min_system_voltage_to_reg(int voltage_mv)
-{
-	return (voltage_mv / BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV) <<
-			BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT;
-}
-
-static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
-{
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
-}
-
-#if defined(CONFIG_CHARGE_RAMP_HW) || \
-	defined(CONFIG_USB_PD_VBUS_MEASURE_CHARGER)
-static int bq25710_get_low_power_mode(int chgnum, int *mode)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_0, &reg);
-	if (rv)
-		return rv;
-
-	*mode = !!(reg & BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE);
-
-	return EC_SUCCESS;
-}
-
-static int bq25710_set_low_power_mode(int chgnum, int enable)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_0, &reg);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-	mutex_lock(&bq25710_perf_mode_mutex);
-	/*
-	 * Performance mode means not in low power mode. The bit that controls
-	 * this is EN_LWPWR in ChargeOption0. The 'enable' param in this
-	 * function is refeerring to low power mode, so enabling low power mode
-	 * means disabling performance mode and vice versa.
-	 */
-	if (enable)
-		bq25710_perf_mode_req &= ~(1 << task_get_current());
-	else
-		bq25710_perf_mode_req |= (1 << task_get_current());
-	enable = !bq25710_perf_mode_req;
-#endif
-
-	if (enable)
-		reg |= BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE;
-	else
-		reg &= ~BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE;
-
-	rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_0, reg);
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-	mutex_unlock(&bq25710_perf_mode_mutex);
-#endif
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-static int bq25710_adc_start(int chgnum, int adc_en_mask)
-{
-	int reg;
-	int mode;
-	int tries_left = BQ25710_ADC_OPTION_ADC_CONV_MS;
-
-	/* Save current mode to restore same state after ADC read */
-	if (bq25710_get_low_power_mode(chgnum, &mode))
-		return EC_ERROR_UNKNOWN;
-
-	/* Exit low power mode so ADC conversion takes typical time */
-	if (bq25710_set_low_power_mode(chgnum, 0))
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Turn on the ADC for one reading. Note that adc_en_mask
-	 * maps to bit[7:0] in ADCOption register.
-	 */
-	reg = (adc_en_mask & BQ25710_ADC_OPTION_EN_ADC_ALL) |
-	      BQ25710_ADC_OPTION_ADC_START;
-	if (raw_write16(chgnum, BQ25710_REG_ADC_OPTION, reg))
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Wait until the ADC operation completes. The spec says typical
-	 * conversion time is 10 msec (25 msec on bq25720). If low power
-	 * mode isn't exited first, then the conversion time jumps to
-	 * ~60 msec.
-	 */
-	do {
-		/* sleep 2 ms so we time out after 2x the expected time */
-		msleep(2);
-		raw_read16(chgnum, BQ25710_REG_ADC_OPTION, &reg);
-	} while (--tries_left && (reg & BQ25710_ADC_OPTION_ADC_START));
-
-	/* ADC reading attempt complete, go back to low power mode */
-	if (bq25710_set_low_power_mode(chgnum, mode))
-		return EC_ERROR_UNKNOWN;
-
-	/* Could not complete read */
-	if (reg & BQ25710_ADC_OPTION_ADC_START)
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-#endif
-
-static void bq25710_init(int chgnum)
-{
-	int reg;
-	int vsys;
-	int rv;
-
-	/*
-	 * Reset registers to their default settings. There is no reset pin for
-	 * this chip so without a full power cycle, some registers may not be at
-	 * their default values. Note, need to save the POR value of
-	 * MIN_SYSTEM_VOLTAGE register prior to setting the reset so that the
-	 * correct value is preserved. In order to have the correct value read,
-	 * the bq25710 must not be in low power mode, otherwise the VDDA rail
-	 * may not be powered if AC is not connected. Note, this reset is only
-	 * required when running out of RO and not following sysjump to RW.
-	 */
-	if (!system_jumped_late()) {
-		rv = bq25710_set_low_power_mode(chgnum, 0);
-		/* Allow enough time for VDDA to be powered */
-		msleep(BQ25710_VDDA_STARTUP_DELAY_MSEC);
-		rv |= raw_read16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys);
-		rv |= raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, &reg);
-		if (!rv) {
-			reg |= BQ25710_CHARGE_OPTION_3_RESET_REG;
-			/* Set all registers to default values */
-			raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_3, reg);
-			/* Restore VSYS_MIN voltage to POR reset value */
-			raw_write16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE,
-				    vsys);
-		}
-		/* Reenable low power mode */
-		bq25710_set_low_power_mode(chgnum, 1);
-	}
-
-	if (!raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, &reg)) {
-		/* Disable VDPM prochot profile at initialization */
-		reg &= ~BQ25710_PROCHOT_PROFILE_VDPM;
-		/*
-		 * Enable PROCHOT to be asserted with VSYS min detection. Note
-		 * that when no battery is present, then VSYS will be set to the
-		 * value in register 0x3E (MinSysVoltage) which means that when
-		 * no battery is present prochot will continuosly be asserted.
-		 */
-		reg |= BQ25710_PROCHOT_PROFILE_VSYS;
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-		/*
-		 * Set the IDCHG limit who's value is defined in the config
-		 * option in mA. Also, enable IDCHG trigger for prochot.
-		 */
-		reg &= ~BQ25710_PROCHOT_IDCHG_VTH_MASK;
-		/*
-		 * IDCHG limit is in 512 mA steps. Note there is a 128 mA offset
-		 * so the actual IDCHG limit will be the value stored in bits
-		 * 15:10 + 128 mA.
-		 */
-		reg |= ((CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA << 1) &
-			BQ25710_PROCHOT_IDCHG_VTH_MASK);
-		reg |= BQ25710_PROCHOT_PROFILE_IDCHG;
-#endif
-		raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_1, reg);
-#ifdef CONFIG_CHARGER_BQ25720_VSYS_TH2_DV
-		/*
-		 * The default VSYS_TH2 is 5.9v for a 2S config. Boards
-		 * may need to increase this for stability. PROCHOT is
-		 * asserted when the threshold is reached.
-		 */
-		if (!raw_read16(chgnum, BQ25720_REG_VMIN_ACTIVE_PROTECTION,
-				&reg)) {
-			reg &= ~BQ25720_VMIN_AP_VSYS_TH2_MASK;
-			reg |= VMIN_AP_VSYS_TH2_TO_REG(
-				CONFIG_CHARGER_BQ25720_VSYS_TH2_DV) <<
-				BQ25720_VMIN_AP_VSYS_TH2_SHIFT;
-			raw_write16(chgnum, BQ25720_REG_VMIN_ACTIVE_PROTECTION,
-				    reg);
-		}
-#endif
-	}
-
-	/* Reduce ILIM from default of 150% to 105% */
-	if (!raw_read16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, &reg)) {
-		reg &= ~BQ25710_PROCHOT0_ILIM_VTH_MASK;
-		raw_write16(chgnum, BQ25710_REG_PROCHOT_OPTION_0, reg);
-	}
-
-	/*
-	 * Reduce peak power mode overload and relax cycle time from default 20
-	 * msec to the minimum of 5 msec.
-	 */
-	if (!raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_2, &reg)) {
-		reg &= ~BQ25710_CHARGE_OPTION_2_TMAX_MASK;
-		raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, reg);
-	}
-}
-
-/* Charger interfaces */
-static const struct charger_info *bq25710_get_info(int chgnum)
-{
-	return &bq25710_charger_info;
-}
-
-static enum ec_error_list bq25710_post_init(int chgnum)
-{
-	/*
-	 * Note: bq25710 power on reset state is:
-	 *	watch dog timer     = 175 sec
-	 *	input current limit = ~1/2 maximum setting
-	 *	charging voltage    = 0 mV
-	 *	charging current    = 0 mA
-	 *	discharge on AC     = disabled
-	 */
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq25710_get_status(int chgnum, int *status)
-{
-	int rv;
-	int option;
-
-	rv = bq25710_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	/* Default status */
-	*status = CHARGER_LEVEL_2;
-
-	if (option & BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list bq25710_set_mode(int chgnum, int mode)
-{
-	int rv;
-	int option;
-
-	rv = bq25710_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	if (mode & CHARGER_CHARGE_INHIBITED)
-		option |= BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT;
-	else
-		option &= ~BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT;
-
-	return bq25710_set_option(chgnum, option);
-}
-
-static enum ec_error_list bq25710_enable_otg_power(int chgnum, int enabled)
-{
-	/* This is controlled with the EN_OTG pin. Support not added yet. */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static enum ec_error_list bq25710_set_otg_current_voltage(int chgum,
-							  int output_current,
-							  int output_voltage)
-{
-	/* Add when needed. */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static enum ec_error_list bq25710_get_current(int chgnum, int *current)
-{
-	int rv, reg;
-
-	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_CURRENT, &reg);
-	if (!rv)
-		*current = REG_TO_CHARGING_CURRENT(reg);
-
-	return rv;
-}
-
-static enum ec_error_list bq25710_set_current(int chgnum, int current)
-{
-	return raw_write16(chgnum, BQ25710_REG_CHARGE_CURRENT,
-		CHARGING_CURRENT_TO_REG(current));
-}
-
-/* Get/set charge voltage limit in mV */
-static enum ec_error_list bq25710_get_voltage(int chgnum, int *voltage)
-{
-	return raw_read16(chgnum, BQ25710_REG_MAX_CHARGE_VOLTAGE, voltage);
-}
-
-static enum ec_error_list bq25710_set_voltage(int chgnum, int voltage)
-{
-	return raw_write16(chgnum, BQ25710_REG_MAX_CHARGE_VOLTAGE, voltage);
-}
-
-/* Discharge battery when on AC power. */
-static enum ec_error_list bq25710_discharge_on_ac(int chgnum, int enable)
-{
-	int rv, option;
-
-	rv = bq25710_get_option(chgnum, &option);
-	if (rv)
-		return rv;
-
-	if (enable)
-		option |= BQ25710_CHARGE_OPTION_0_EN_LEARN;
-	else
-		option &= ~BQ25710_CHARGE_OPTION_0_EN_LEARN;
-
-	return bq25710_set_option(chgnum, option);
-}
-
-static enum ec_error_list bq25710_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-	int num_steps = iin_host_current_to_reg(input_current);
-
-	return raw_write16(chgnum, BQ25710_REG_IIN_HOST,
-			   num_steps << BQ25710_IIN_HOST_CURRENT_SHIFT);
-}
-
-static enum ec_error_list bq25710_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	int rv, reg;
-
-	/*
-	 * IIN_DPM register reflects the actual input current limit programmed
-	 * in the register, either from host or from ICO. After ICO, the
-	 * current limit used by DPM regulation may differ from the IIN_HOST
-	 * register settings.
-	 */
-	rv = raw_read16(chgnum, BQ25710_REG_IIN_DPM, &reg);
-	if (!rv)
-		*input_current =
-			iin_dpm_reg_to_current(reg >>
-					       BQ25710_IIN_DPM_CURRENT_SHIFT);
-
-	return rv;
-}
-
-static enum ec_error_list bq25710_manufacturer_id(int chgnum, int *id)
-{
-	return raw_read16(chgnum, BQ25710_REG_MANUFACTURER_ID, id);
-}
-
-static enum ec_error_list bq25710_device_id(int chgnum, int *id)
-{
-	return raw_read16(chgnum, BQ25710_REG_DEVICE_ADDRESS, id);
-}
-
-#ifdef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
-
-#if defined(CONFIG_CHARGER_BQ25720)
-
-static int reg_adc_vbus_to_mv(int reg)
-{
-	/*
-	 * LSB => 96mV, no DC offset.
-	 */
-	return reg * BQ25720_ADC_VBUS_STEP_MV;
-}
-
-#elif defined(CONFIG_CHARGER_BQ25710)
-
-static int reg_adc_vbus_to_mv(int reg)
-{
-	/*
-	 * LSB => 64mV.
-	 * Return 0 when VBUS <= 3.2V as ADC can't measure it.
-	 */
-	return reg ?
-		(reg * BQ25710_ADC_VBUS_STEP_MV + BQ25710_ADC_VBUS_BASE_MV) : 0;
-}
-
-#else
-#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
-#endif
-
-static enum ec_error_list bq25710_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
-{
-	int reg, rv;
-
-	rv = bq25710_adc_start(chgnum, BQ25710_ADC_OPTION_EN_ADC_VBUS);
-	if (rv)
-		goto error;
-
-	/* Read ADC value */
-	rv = raw_read16(chgnum, BQ25710_REG_ADC_VBUS_PSYS, &reg);
-	if (rv)
-		goto error;
-
-	reg >>= BQ25710_ADC_VBUS_STEP_BIT_OFFSET;
-	*voltage = reg_adc_vbus_to_mv(reg);
-
-error:
-	if (rv)
-		CPRINTF("Could not read VBUS ADC! Error: %d\n", rv);
-	return rv;
-}
-#endif
-
-static enum ec_error_list bq25710_get_option(int chgnum, int *option)
-{
-	/* There are 4 option registers, but we only need the first for now. */
-	return raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_0, option);
-}
-
-static enum ec_error_list bq25710_set_option(int chgnum, int option)
-{
-	/* There are 4 option registers, but we only need the first for now. */
-	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_0, option);
-}
-
-int bq25710_set_min_system_voltage(int chgnum, int mv)
-{
-	int reg;
-
-	reg = min_system_voltage_to_reg(mv);
-	return raw_write16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE, reg);
-}
-
-#ifdef CONFIG_CHARGE_RAMP_HW
-
-static void bq25710_chg_ramp_handle(void)
-{
-	int ramp_curr;
-	int chgnum = 0;
-
-	if (IS_ENABLED(CONFIG_OCPC))
-		chgnum = charge_get_active_chg_chip();
-
-	/*
-	 * Once the charge ramp is stable write back the stable ramp
-	 * current to the host input current limit register
-	 */
-	ramp_curr = chg_ramp_get_current_limit();
-	if (chg_ramp_is_stable()) {
-		if (ramp_curr &&
-		    !charger_set_input_current_limit(chgnum, ramp_curr))
-			CPRINTF("bq25710: stable ramp current=%d\n", ramp_curr);
-	} else {
-		CPRINTF("bq25710: ICO stall, ramp current=%d\n", ramp_curr);
-	}
-	/*
-	 * Disable ICO mode. When ICO mode is active the input current limit is
-	 * given by the value in register IIN_DPM (0x22)
-	 */
-	charger_set_hw_ramp(0);
-}
-DECLARE_DEFERRED(bq25710_chg_ramp_handle);
-
-static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable)
-{
-	int option3_reg, option2_reg, rv;
-
-	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, &option3_reg);
-	if (rv)
-		return rv;
-	rv = raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_2, &option2_reg);
-	if (rv)
-		return rv;
-
-	if (enable) {
-		/*
-		 * ICO mode can only be used when a battery is present. If there
-		 * is no battery, or if the battery has not recovered yet from
-		 * cutoff, then enabling ICO mode will lead to VSYS
-		 * dropping out.
-		 */
-		if (!battery_is_present() || (battery_get_disconnect_state() !=
-					      BATTERY_NOT_DISCONNECTED)) {
-			CPRINTF("bq25710: no battery, skip ICO enable\n");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* Set InputVoltage register to BC1.2 minimum ramp voltage */
-		rv = raw_write16(chgnum, BQ25710_REG_INPUT_VOLTAGE,
-			BQ25710_BC12_MIN_VOLTAGE_MV);
-		if (rv)
-			return rv;
-
-		/*  Enable ICO algorithm */
-		option3_reg |= BQ25710_CHARGE_OPTION_3_EN_ICO_MODE;
-
-		/* 0b: Input current limit is set by BQ25710_REG_IIN_HOST */
-		option2_reg &= ~BQ25710_CHARGE_OPTION_2_EN_EXTILIM;
-
-		/* Charge ramp may take up to 2s to settle down */
-		hook_call_deferred(&bq25710_chg_ramp_handle_data, (4 * SECOND));
-	} else {
-		/*  Disable ICO algorithm */
-		option3_reg &= ~BQ25710_CHARGE_OPTION_3_EN_ICO_MODE;
-
-		/*
-		 * 1b: Input current limit is set by the lower value of
-		 * ILIM_HIZ pin and BQ25710_REG_IIN_HOST
-		 */
-		option2_reg |= BQ25710_CHARGE_OPTION_2_EN_EXTILIM;
-	}
-
-	rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, option2_reg);
-	if (rv)
-		return rv;
-	return raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_3, option3_reg);
-}
-
-static int bq25710_ramp_is_stable(int chgnum)
-{
-	int reg;
-
-	if (raw_read16(chgnum, BQ25710_REG_CHARGER_STATUS, &reg))
-		return 0;
-
-	return reg & BQ25710_CHARGE_STATUS_ICO_DONE;
-}
-
-static int bq25710_ramp_get_current_limit(int chgnum)
-{
-	int reg, rv;
-
-	rv = raw_read16(chgnum, BQ25710_REG_IIN_DPM, &reg);
-	if (rv) {
-		CPRINTF("Could not read iin_dpm current limit! Error: %d\n",
-			rv);
-		return 0;
-	}
-
-	return iin_dpm_reg_to_current(reg >> BQ25710_IIN_DPM_CURRENT_SHIFT);
-}
-#endif /* CONFIG_CHARGE_RAMP_HW */
-
-#ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-/* Called on AP S5 -> S3  and S3/S0iX -> S0 transition */
-static void bq25710_chipset_startup(void)
-{
-	bq25710_set_low_power_mode(CHARGER_SOLO, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
-
-
-/* Called on AP S0 -> S0iX/S3 or S3 -> S5 transition */
-static void bq25710_chipset_suspend(void)
-{
-	bq25710_set_low_power_mode(CHARGER_SOLO, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, bq25710_chipset_suspend, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, bq25710_chipset_suspend, HOOK_PRIO_DEFAULT);
-#endif
-
-#ifdef CONFIG_CMD_CHARGER_DUMP
-static int console_bq25710_dump_regs(int argc, char **argv)
-{
-	int i;
-	int val;
-	int chgnum = 0;
-	char *e;
-
-	/* Dump all readable registers on bq25710. */
-	static const uint8_t regs[] = {
-		BQ25710_REG_CHARGE_OPTION_0,
-		BQ25710_REG_CHARGE_CURRENT,
-		BQ25710_REG_MAX_CHARGE_VOLTAGE,
-		BQ25710_REG_CHARGER_STATUS,
-		BQ25710_REG_PROCHOT_STATUS,
-		BQ25710_REG_IIN_DPM,
-		BQ25710_REG_ADC_VBUS_PSYS,
-		BQ25710_REG_ADC_IBAT,
-		BQ25710_REG_ADC_CMPIN_IIN,
-		BQ25710_REG_ADC_VSYS_VBAT,
-		BQ25710_REG_CHARGE_OPTION_1,
-		BQ25710_REG_CHARGE_OPTION_2,
-		BQ25710_REG_CHARGE_OPTION_3,
-		BQ25710_REG_PROCHOT_OPTION_0,
-		BQ25710_REG_PROCHOT_OPTION_1,
-		BQ25710_REG_ADC_OPTION,
-#ifdef CONFIG_CHARGER_BQ25720
-		BQ25720_REG_CHARGE_OPTION_4,
-		BQ25720_REG_VMIN_ACTIVE_PROTECTION,
-#endif
-		BQ25710_REG_OTG_VOLTAGE,
-		BQ25710_REG_OTG_CURRENT,
-		BQ25710_REG_INPUT_VOLTAGE,
-		BQ25710_REG_MIN_SYSTEM_VOLTAGE,
-		BQ25710_REG_IIN_HOST,
-		BQ25710_REG_MANUFACTURER_ID,
-		BQ25710_REG_DEVICE_ADDRESS,
-	};
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(regs); ++i) {
-		if (raw_read16(chgnum, regs[i], &val))
-			continue;
-		ccprintf("BQ25710 REG 0x%02x:  0x%04x\n", regs[i], val);
-	}
-
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(charger_dump, console_bq25710_dump_regs,
-			"charger_dump <chgnum>",
-			"Dump all charger registers");
-
-#endif /* CONFIG_CMD_CHARGER_DUMP */
-
-const struct charger_drv bq25710_drv = {
-	.init = &bq25710_init,
-	.post_init = &bq25710_post_init,
-	.get_info = &bq25710_get_info,
-	.get_status = &bq25710_get_status,
-	.set_mode = &bq25710_set_mode,
-	.enable_otg_power = &bq25710_enable_otg_power,
-	.set_otg_current_voltage = &bq25710_set_otg_current_voltage,
-	.get_current = &bq25710_get_current,
-	.set_current = &bq25710_set_current,
-	.get_voltage = &bq25710_get_voltage,
-	.set_voltage = &bq25710_set_voltage,
-	.discharge_on_ac = &bq25710_discharge_on_ac,
-	.get_vbus_voltage = &bq25710_get_vbus_voltage,
-	.set_input_current_limit = &bq25710_set_input_current_limit,
-	.get_input_current_limit = &bq25710_get_input_current_limit,
-	.manufacturer_id = &bq25710_manufacturer_id,
-	.device_id = &bq25710_device_id,
-	.get_option = &bq25710_get_option,
-	.set_option = &bq25710_set_option,
-#ifdef CONFIG_CHARGE_RAMP_HW
-	.set_hw_ramp = &bq25710_set_hw_ramp,
-	.ramp_is_stable = &bq25710_ramp_is_stable,
-	.ramp_get_current_limit = &bq25710_ramp_get_current_limit,
-#endif /* CONFIG_CHARGE_RAMP_HW */
-};
diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h
deleted file mode 100644
index 68c7619ceb..0000000000
--- a/driver/charger/bq25710.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI bq25710 battery charger driver.
- */
-
-#ifndef __CROS_EC_BQ25710_H
-#define __CROS_EC_BQ25710_H
-
-/* SMBUS Interface */
-#define BQ25710_SMBUS_ADDR1_FLAGS 0x09
-
-#define BQ25710_BC12_MIN_VOLTAGE_MV	1408
-
-/* Registers */
-#define BQ25710_REG_CHARGE_OPTION_0		0x12
-#define BQ25710_REG_CHARGE_CURRENT		0x14
-#define BQ25710_REG_MAX_CHARGE_VOLTAGE		0x15
-#define BQ25710_REG_CHARGER_STATUS		0x20
-#define BQ25710_REG_PROCHOT_STATUS		0x21
-#define BQ25710_REG_IIN_DPM			0x22
-#define BQ25710_REG_ADC_VBUS_PSYS		0x23
-#define BQ25710_REG_ADC_IBAT			0x24
-#define BQ25710_REG_ADC_CMPIN_IIN		0x25
-#define BQ25710_REG_ADC_VSYS_VBAT		0x26
-#define BQ25710_REG_CHARGE_OPTION_1		0x30
-#define BQ25710_REG_CHARGE_OPTION_2		0x31
-#define BQ25710_REG_CHARGE_OPTION_3		0x32
-#define BQ25710_REG_PROCHOT_OPTION_0		0x33
-#define BQ25710_REG_PROCHOT_OPTION_1		0x34
-#define BQ25710_REG_ADC_OPTION			0x35
-#ifdef CONFIG_CHARGER_BQ25720
-#define BQ25720_REG_CHARGE_OPTION_4		0x36
-#define BQ25720_REG_VMIN_ACTIVE_PROTECTION	0x37
-#endif
-#define BQ25710_REG_OTG_VOLTAGE			0x3B
-#define BQ25710_REG_OTG_CURRENT			0x3C
-#define BQ25710_REG_INPUT_VOLTAGE		0x3D
-#define BQ25710_REG_MIN_SYSTEM_VOLTAGE		0x3E
-#define BQ25710_REG_IIN_HOST			0x3F
-#define BQ25710_REG_MANUFACTURER_ID		0xFE
-#define BQ25710_REG_DEVICE_ADDRESS		0xFF
-
-/* ChargeOption0 Register */
-#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE	BIT(15)
-#define BQ25710_CHARGE_OPTION_0_IDPM_AUTO_DIS	BIT(12)
-#define BQ25710_CHARGE_OPTION_0_EN_LEARN	BIT(5)
-#define BQ25710_CHARGE_OPTION_0_IADP_GAIN	BIT(4)
-#define BQ25710_CHARGE_OPTION_0_EN_IDPM		BIT(1)
-#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT	BIT(0)
-
-/* ChargeOption2 Register */
-#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM	BIT(7)
-#define BQ25710_CHARGE_OPTION_2_TMAX_SHIFT	8
-#define BQ25710_CHARGE_OPTION_2_TMAX_MASK (0x3 << \
-					   BQ25710_CHARGE_OPTION_2_TMAX_SHIFT)
-
-/* ChargeOption3 Register */
-#define BQ25710_CHARGE_OPTION_3_RESET_REG	BIT(14)
-#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE	BIT(11)
-
-/* ChargeStatus Register */
-#define BQ25710_CHARGE_STATUS_ICO_DONE		BIT(14)
-
-/* IIN_DPM Register */
-#define BQ25710_IIN_DPM_CURRENT_SHIFT		8
-#define BQ25710_IIN_DPM_CURRENT_STEP_MA		50
-
-/* ADCOption Register */
-#define BQ25710_ADC_OPTION_ADC_START		BIT(14)
-#define BQ25710_ADC_OPTION_EN_ADC_VBUS		BIT(6)
-#define BQ25710_ADC_OPTION_EN_ADC_IIN		BIT(4)
-#define BQ25710_ADC_OPTION_EN_ADC_ALL		0xFF
-
-/* ADC conversion time ins ms */
-#if defined(CONFIG_CHARGER_BQ25720)
-#define BQ25710_ADC_OPTION_ADC_CONV_MS		25
-#elif defined(CONFIG_CHARGER_BQ25710)
-#define BQ25710_ADC_OPTION_ADC_CONV_MS		10
-#else
-#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
-#endif
-
-/* ADCVBUS/PSYS Register */
-#if defined(CONFIG_CHARGER_BQ25720)
-#define BQ25720_ADC_VBUS_STEP_MV		96
-#elif defined(CONFIG_CHARGER_BQ25710)
-#define BQ25710_ADC_VBUS_STEP_MV		64
-#define BQ25710_ADC_VBUS_BASE_MV		3200
-#else
-#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
-#endif
-#define BQ25710_ADC_VBUS_STEP_BIT_OFFSET	8
-
-/* ADCIIN Register */
-#define BQ25710_ADC_IIN_STEP_MA			50
-#define BQ25710_ADC_IIN_STEP_BIT_OFFSET		8
-
-/* ProchotOption0 Register */
-#define BQ25710_PROCHOT0_ILIM_VTH_SHIFT 11
-#define BQ25710_PROCHOT0_ILIM_VTH_MASK	(0x1f << \
-					 BQ25710_PROCHOT0_ILIM_VTH_SHIFT)
-
-/* ProchotOption1 Register */
-#define BQ25710_PROCHOT_PROFILE_VDPM		BIT(7)
-#define BQ25710_PROCHOT_PROFILE_IDCHG		BIT(3)
-#define BQ25710_PROCHOT_PROFILE_VSYS		BIT(2)
-#define BQ25710_PROCHOT_IDCHG_VTH_MASK		0xFC00
-
-/* IIN_HOST Register */
-#define BQ25710_IIN_HOST_CURRENT_SHIFT		8
-#define BQ25710_IIN_HOST_CURRENT_STEP_MA	50
-
-#if defined(CONFIG_CHARGER_BQ25720)
-/* Vmin Active Protection Register */
-#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT		2
-#define BQ25720_VMIN_AP_VSYS_TH2_MASK	GENMASK(7, \
-						BQ25720_VMIN_AP_VSYS_TH2_SHIFT)
-#endif
-
-/* Min System Voltage Register */
-#if defined(CONFIG_CHARGER_BQ25720)
-#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV	100
-#elif defined(CONFIG_CHARGER_BQ25710)
-#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV	256
-#else
-#error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
-#endif
-#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT	8
-
-extern const struct charger_drv bq25710_drv;
-
-/**
- * Set VSYS_MIN
- *
- * @param chgnum: Index into charger chips
- * @param mv: min system voltage in mV
- * @return EC_SUCCESS or error
- */
-int bq25710_set_min_system_voltage(int chgnum, int mv);
-
-#endif /* __CROS_EC_BQ25710_H */
diff --git a/driver/charger/isl923x.c b/driver/charger/isl923x.c
deleted file mode 100644
index 9e3284c29f..0000000000
--- a/driver/charger/isl923x.c
+++ /dev/null
@@ -1,1471 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Intersil ISL-9237/8 battery charger driver.
- */
-
-#include "adc.h"
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "common.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "isl923x.h"
-#include "ocpc.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#ifndef CONFIG_CHARGER_NARROW_VDC
-#error "ISL9237/8 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
-#endif
-
-#if defined(CONFIG_CHARGER_ISL9238) || defined(CONFIG_CHARGER_ISL9238C)
-#define CHARGER_ISL9238X
-#endif
-
-#ifdef CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
-	#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
-		CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
-#endif
-
-
-#define DEFAULT_R_AC 20
-#define DEFAULT_R_SNS 10
-#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS)
-#define CURRENT_TO_REG(CUR) ((CUR) * R_SNS / DEFAULT_R_SNS)
-#define AC_REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_AC / R_AC)
-#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC)
-
-#if defined(CONFIG_CHARGER_ISL9237)
-#define CHARGER_NAME  "isl9237"
-#define CHARGE_V_MAX  ISL9237_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_ISL9238)
-#define CHARGER_NAME  "isl9238"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_ISL9238C)
-#define CHARGER_NAME  "isl9238c"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#elif defined(CONFIG_CHARGER_RAA489000)
-#define CHARGER_NAME  "raa489000"
-#define CHARGE_V_MAX  RAA489000_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  RAA489000_SYS_VOLTAGE_REG_MIN
-#define CHARGE_V_STEP 8
-#endif
-
-#ifdef CONFIG_CHARGER_RAA489000
-#define CHARGE_I_MAX  RAA489000_CURRENT_REG_MAX
-#else
-#define CHARGE_I_MAX  ISL923X_CURRENT_REG_MAX
-#endif /* CONFIG_CHARGER_RAA489000 */
-#define CHARGE_I_MIN  4
-#define CHARGE_I_OFF  0
-#define CHARGE_I_STEP 4
-#ifdef CONFIG_CHARGER_RAA489000
-#define INPUT_I_MAX   RAA489000_CURRENT_REG_MAX
-#else
-#define INPUT_I_MAX   ISL923X_CURRENT_REG_MAX
-#endif /* CONFIG_CHARGER_RAA489000 */
-#define INPUT_I_MIN   4
-#define INPUT_I_STEP  4
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-enum isl923x_amon_bmon { AMON, BMON };
-enum isl923x_mon_dir { MON_CHARGE = 0, MON_DISCHARGE = 1 };
-
-static int learn_mode;
-
-/* Mutex for CONTROL1 register, that can be updated from multiple tasks. */
-K_MUTEX_DEFINE(control1_mutex);
-
-static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable);
-
-/* Charger parameters */
-static const struct charger_info isl9237_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN),
-	.current_step = REG_TO_CURRENT(CHARGE_I_STEP),
-	.input_current_max  = AC_REG_TO_CURRENT(INPUT_I_MAX),
-	.input_current_min  = AC_REG_TO_CURRENT(INPUT_I_MIN),
-	.input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP),
-};
-
-static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
-}
-
-static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
-{
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-
-static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
-{
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
-}
-
-static inline enum ec_error_list raw_update16(int chgnum, int offset, int mask,
-					      enum mask_update_action action)
-{
-	return i2c_update16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, mask, action);
-}
-
-static enum ec_error_list isl9237_set_current(int chgnum, uint16_t current)
-{
-	return raw_write16(chgnum, ISL923X_REG_CHG_CURRENT,
-			   CURRENT_TO_REG(current));
-}
-
-static enum ec_error_list isl9237_set_voltage(int chgnum, uint16_t voltage)
-{
-	return raw_write16(chgnum, ISL923X_REG_SYS_VOLTAGE_MAX, voltage);
-}
-
-/* chip specific interfaces */
-
-static enum ec_error_list isl923x_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-	int rv;
-	uint16_t reg = AC_CURRENT_TO_REG(input_current);
-
-	rv = raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT1, reg);
-	if (rv)
-		return rv;
-
-	return raw_write16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT2, reg);
-}
-
-#ifdef CONFIG_CMD_CHARGER_ADC_AMON_BMON
-static int get_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
-			 enum isl923x_mon_dir direction, int *adc)
-{
-	int reg, ret;
-
-	if (IS_ENABLED(CHARGER_ISL9238X)) {
-		ret = raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg);
-		if (ret)
-			return ret;
-
-		/* Switch direction */
-		if (direction)
-			reg |= ISL9238_C3_AMON_BMON_DIRECTION;
-		else
-			reg &= ~ISL9238_C3_AMON_BMON_DIRECTION;
-		ret = raw_write16(chgnum, ISL9238_REG_CONTROL3, reg);
-		if (ret)
-			return ret;
-	}
-
-	mutex_lock(&control1_mutex);
-
-	ret = raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg);
-	if (!ret) {
-		/* Switch between AMON/BMON */
-		if (amon == AMON)
-			reg &= ~ISL923X_C1_SELECT_BMON;
-		else
-			reg |= ISL923X_C1_SELECT_BMON;
-
-		/* Enable monitor */
-		reg &= ~ISL923X_C1_DISABLE_MON;
-		ret = raw_write16(chgnum, ISL923X_REG_CONTROL1, reg);
-	}
-
-	mutex_unlock(&control1_mutex);
-
-	if (ret)
-		return ret;
-
-	*adc = adc_read_channel(ADC_AMON_BMON);
-
-	return ret;
-}
-#endif
-
-static enum ec_error_list isl923x_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	int rv;
-	int regval;
-
-	rv = raw_read16(chgnum, ISL923X_REG_ADAPTER_CURRENT_LIMIT1, &regval);
-	if (rv)
-		return rv;
-
-	*input_current = AC_REG_TO_CURRENT(regval);
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CHARGER_RAA489000
-static enum ec_error_list raa489000_get_input_current(int chgnum,
-						    int *input_current)
-{
-	int rv;
-	int regval;
-	int reg;
-
-	reg = RAA489000_REG_ADC_INPUT_CURRENT;
-
-	rv = raw_read16(chgnum, reg, &regval);
-	if (rv)
-		return rv;
-
-	/* The value is in 22.2mA increments. */
-	regval *= 222;
-	regval /= 10;
-
-	*input_current = AC_REG_TO_CURRENT(regval);
-	return EC_SUCCESS;
-}
-#elif defined(CONFIG_CMD_CHARGER_ADC_AMON_BMON)
-static enum ec_error_list isl923x_get_input_current(int chgnum,
-						    int *input_current)
-{
-	int rv, adc;
-
-	rv = get_amon_bmon(chgnum, AMON, MON_CHARGE, &adc);
-	if (rv)
-		return rv;
-
-	*input_current = adc / CONFIG_CHARGER_SENSE_RESISTOR_AC;
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_CHARGER_RAA489000 */
-
-#if defined(CONFIG_CHARGER_OTG) && defined(CHARGER_ISL9238X)
-static enum ec_error_list isl923x_enable_otg_power(int chgnum, int enabled)
-{
-	int rv, control1;
-
-	mutex_lock(&control1_mutex);
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &control1);
-	if (rv)
-		goto out;
-
-	if (enabled)
-		control1 |= ISL923X_C1_OTG;
-	else
-		control1 &= ~ISL923X_C1_OTG;
-
-	rv = raw_write16(chgnum, ISL923X_REG_CONTROL1, control1);
-
-out:
-	mutex_unlock(&control1_mutex);
-
-	return rv;
-}
-
-/*
- * TODO(b:67920792): OTG is not implemented for ISL9237 that has different
- * register scale and range.
- */
-static enum ec_error_list isl923x_set_otg_current_voltage(int chgnum,
-							  int output_current,
-							  int output_voltage)
-{
-	int rv;
-	uint16_t volt_reg = (output_voltage / ISL9238_OTG_VOLTAGE_STEP)
-			<< ISL9238_OTG_VOLTAGE_SHIFT;
-	uint16_t current_reg =
-		DIV_ROUND_UP(output_current, ISL923X_OTG_CURRENT_STEP)
-			<< ISL923X_OTG_CURRENT_SHIFT;
-
-	if (output_current < 0 || output_current > ISL923X_OTG_CURRENT_MAX ||
-			output_voltage > ISL9238_OTG_VOLTAGE_MAX)
-		return EC_ERROR_INVAL;
-
-	/* Set voltage. */
-	rv = raw_write16(chgnum, ISL923X_REG_OTG_VOLTAGE, volt_reg);
-	if (rv)
-		return rv;
-
-	/* Set current. */
-	return raw_write16(chgnum, ISL923X_REG_OTG_CURRENT, current_reg);
-}
-#endif /* CONFIG_CHARGER_OTG && CHARGER_ISL9238X */
-
-static enum ec_error_list isl923x_manufacturer_id(int chgnum, int *id)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_MANUFACTURER_ID, &reg);
-	if (rv)
-		return rv;
-
-	*id = reg;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl923x_device_id(int chgnum, int *id)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_DEVICE_ID, &reg);
-	if (rv)
-		return rv;
-
-	*id = reg;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl923x_get_option(int chgnum, int *option)
-{
-	int rv;
-	uint32_t controls;
-	int reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg);
-	if (rv)
-		return rv;
-
-	controls = reg;
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg);
-	if (rv)
-		return rv;
-
-	controls |= reg << 16;
-	*option = controls;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl923x_set_option(int chgnum, int option)
-{
-	int rv;
-	uint16_t reg;
-
-	reg = option & 0xffff;
-	rv = raw_write16(chgnum, ISL923X_REG_CONTROL0, reg);
-
-	if (rv)
-		return rv;
-
-	reg = (option >> 16) & 0xffff;
-	return raw_write16(chgnum, ISL923X_REG_CONTROL1, reg);
-}
-
-/* Charger interfaces */
-
-static const struct charger_info *isl923x_get_info(int chgnum)
-{
-	return &isl9237_charger_info;
-}
-
-static enum ec_error_list isl923x_get_status(int chgnum, int *status)
-{
-	*status = CHARGER_LEVEL_2;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl923x_set_mode(int chgnum, int mode)
-{
-	int rv = EC_SUCCESS;
-
-	/*
-	 * See crosbug.com/p/51196.  Always disable learn mode unless it was set
-	 * explicitly.
-	 */
-	if (!learn_mode)
-		rv = isl923x_discharge_on_ac(chgnum, 0);
-
-	/* ISL923X does not support inhibit mode setting. */
-	return rv;
-}
-
-#ifdef CONFIG_CHARGER_RAA489000
-static enum ec_error_list raa489000_get_actual_current(int chgnum, int *current)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, RAA489000_REG_ADC_CHARGE_CURRENT, &reg);
-	/* The value is in 22.2mA increments. */
-	reg *= 222;
-	reg /= 10;
-
-	*current = REG_TO_CURRENT(reg);
-	return rv;
-}
-#endif /* CONFIG_CHARGER_RAA489000 */
-
-static enum ec_error_list isl923x_get_current(int chgnum, int *current)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_CHG_CURRENT, &reg);
-	if (rv)
-		return rv;
-
-	*current = REG_TO_CURRENT(reg);
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl923x_set_current(int chgnum, int current)
-{
-	return isl9237_set_current(chgnum, current);
-}
-
-#ifdef CONFIG_CHARGER_RAA489000
-static enum ec_error_list raa489000_get_actual_voltage(int chgnum, int *voltage)
-{
-	int rv;
-	int reg;
-
-	rv = raw_read16(chgnum, RAA489000_REG_ADC_VSYS, &reg);
-	if (rv)
-		return rv;
-
-	/* The voltage is returned in bits 13:6. LSB is 96mV. */
-	reg &= GENMASK(13, 6);
-	reg >>= 6;
-	reg *= 96;
-
-	*voltage = reg;
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_CHARGER_RAA489000 */
-
-static enum ec_error_list isl923x_get_voltage(int chgnum, int *voltage)
-{
-	return raw_read16(chgnum, ISL923X_REG_SYS_VOLTAGE_MAX, voltage);
-}
-
-static enum ec_error_list isl923x_set_voltage(int chgnum, int voltage)
-{
-	/* The ISL923X will drop voltage to as low as requested. As the
-	 * charger state machine will pass in 0 voltage, protect the system
-	 * voltage by capping to the minimum. The reason is that the ISL923X
-	 * only can regulate the system voltage which will kill the board's
-	 * power if below 0. */
-	if (voltage == 0) {
-		const struct battery_info *bi = battery_get_info();
-		voltage = bi->voltage_min;
-	}
-
-	return isl9237_set_voltage(chgnum, voltage);
-}
-
-static enum ec_error_list isl923x_post_init(int chgnum)
-{
-	/*
-	 * charger_post_init() is called every time AC becomes present in the
-	 * system.  It's called this frequently because there are some charger
-	 * ICs which become unpowered when AC is not present.  Therefore, upon
-	 * AC becoming present again, the chargers need to be reinitialized.
-	 * The ISL9237/8 can be powered from VSYS and therefore do not need to
-	 * be reinitialized everytime.  This is why isl923x_init() is called
-	 * once at HOOK_INIT time.
-	 */
-	return EC_SUCCESS;
-}
-
-int isl923x_set_ac_prochot(int chgnum, uint16_t ma)
-{
-	int rv;
-
-	if (ma > ISL923X_AC_PROCHOT_CURRENT_MAX) {
-		CPRINTS("%s: invalid current (%d mA)", CHARGER_NAME, ma);
-		return EC_ERROR_INVAL;
-	}
-
-	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_AC, AC_CURRENT_TO_REG(ma));
-	if (rv)
-		CPRINTS("%s set_ac_prochot failed (%d)", CHARGER_NAME, rv);
-	return rv;
-}
-
-int isl923x_set_dc_prochot(int chgnum, uint16_t ma)
-{
-	int rv;
-
-	if (ma > ISL923X_DC_PROCHOT_CURRENT_MAX) {
-		CPRINTS("%s: invalid current (%d mA)", CHARGER_NAME, ma);
-		return EC_ERROR_INVAL;
-	}
-
-	rv = raw_write16(chgnum, ISL923X_REG_PROCHOT_DC, CURRENT_TO_REG(ma));
-	if (rv)
-		CPRINTS("%s set_dc_prochot failed (%d)", CHARGER_NAME, rv);
-	return rv;
-}
-
-int isl923x_set_comparator_inversion(int chgnum, int invert)
-{
-	int rv;
-	int regval;
-
-	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			ISL923X_REG_CONTROL2, &regval);
-	if (invert)
-		regval |= ISL923X_C2_INVERT_CMOUT;
-	else
-		regval &= ~ISL923X_C2_INVERT_CMOUT;
-
-	if (!rv)
-		rv |= i2c_write16(chg_chips[chgnum].i2c_port,
-				  chg_chips[chgnum].i2c_addr_flags,
-				  ISL923X_REG_CONTROL2, regval);
-
-	if (rv)
-		CPRINTS("%s (%d) set_comparator_inversion failed (rv: %d)",
-			CHARGER_NAME, chgnum, rv);
-
-	return rv;
-}
-
-static void isl923x_init(int chgnum)
-{
-	int reg;
-	const struct battery_info *bi = battery_get_info();
-	int precharge_voltage = bi->precharge_voltage ?
-		bi->precharge_voltage : bi->voltage_min;
-
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		if (CONFIG_CHARGER_SENSE_RESISTOR ==
-		    CONFIG_CHARGER_SENSE_RESISTOR_AC) {
-			/*
-			 * A 1:1 ratio for Rs1:Rs2 is allowed, but Control4
-			 * register Bit<11> must be set.
-			 */
-			if (raw_read16(chgnum, ISL9238_REG_CONTROL4, &reg))
-				goto init_fail;
-
-			if (raw_write16(chgnum, ISL9238_REG_CONTROL4,
-					reg |
-					RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1))
-				goto init_fail;
-		}
-
-		/*
-		 * Enable hysteresis for CCM/DCM boundary to help with ripple.
-		 */
-		if (raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg))
-			goto init_fail;
-
-		if (raw_write16(chgnum, ISL9238_REG_CONTROL3,
-				reg |
-				RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE))
-			goto init_fail;
-
-		/* Set switching frequency to 600KHz to help with ripple. */
-		if (raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg))
-			goto init_fail;
-
-		reg &= ~ISL923X_C1_SWITCH_FREQ_MASK;
-
-		if (raw_write16(chgnum, ISL923X_REG_CONTROL1,
-				reg |
-				ISL9237_C1_SWITCH_FREQ_599K))
-			goto init_fail;
-	}
-
-	if (IS_ENABLED(CONFIG_TRICKLE_CHARGING))
-		if (raw_write16(chgnum, ISL923X_REG_SYS_VOLTAGE_MIN,
-				precharge_voltage))
-			goto init_fail;
-
-	/*
-	 * [10:9]: Prochot# Debounce time
-	 *         11b: 1ms
-	 */
-	if (raw_read16(chgnum, ISL923X_REG_CONTROL2, &reg))
-		goto init_fail;
-
-	if (!IS_ENABLED(CONFIG_CHARGER_RAA489000))
-		reg |= ISL923X_C2_OTG_DEBOUNCE_150;
-
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
-		reg |= ISL923X_C2_PROCHOT_DEBOUNCE_500;
-	else
-		reg |= ISL923X_C2_PROCHOT_DEBOUNCE_1000;
-
-	if (raw_write16(chgnum, ISL923X_REG_CONTROL2,
-			reg |
-			ISL923X_C2_ADAPTER_DEBOUNCE_150))
-		goto init_fail;
-
-	if (IS_ENABLED(CONFIG_CHARGE_RAMP_HW)) {
-		if (IS_ENABLED(CONFIG_CHARGER_ISL9237)) {
-			if (raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg))
-				goto init_fail;
-
-			/*
-			 * Set input voltage regulation reference voltage for
-			 * charge ramp.
-			 */
-			reg &= ~ISL9237_C0_VREG_REF_MASK;
-			reg |= ISL9237_C0_VREG_REF_4200;
-
-			if (raw_write16(chgnum, ISL923X_REG_CONTROL0, reg))
-				goto init_fail;
-		} else {
-			/*
-			 * For the ISL9238, set the input voltage regulation to
-			 * 4.439V.  Note, the voltage is set in 341.3 mV steps.
-			 *
-			 * For the RAA489000, set the input voltage regulation
-			 * to 4.437V.  Note, that the voltage is set in 85.33 mV
-			 * steps.
-			 */
-			if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
-				reg = (4437 / RAA489000_INPUT_VOLTAGE_REF_STEP)
-					<< RAA489000_INPUT_VOLTAGE_REF_SHIFT;
-			else
-				reg = (4439 / ISL9238_INPUT_VOLTAGE_REF_STEP)
-					<< ISL9238_INPUT_VOLTAGE_REF_SHIFT;
-
-			if (raw_write16(chgnum, ISL9238_REG_INPUT_VOLTAGE, reg))
-				goto init_fail;
-		}
-	} else {
-		if (raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg))
-			goto init_fail;
-
-		/* Disable voltage regulation loop to disable charge ramp */
-		reg |= ISL923X_C0_DISABLE_VREG;
-
-		if (raw_write16(chgnum, ISL923X_REG_CONTROL0, reg))
-			goto init_fail;
-	}
-
-	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C)) {
-		/* b/155366741: enable slew rate control */
-		if (raw_read16(chgnum, ISL9238C_REG_CONTROL6, &reg))
-			goto init_fail;
-
-		reg |= ISL9238C_C6_SLEW_RATE_CONTROL;
-
-		if (raw_write16(chgnum, ISL9238C_REG_CONTROL6, reg))
-			goto init_fail;
-	}
-
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		/*
-		 * Return the BFET to normal operation as it may have been
-		 * turned off when entering hibernate.
-		 */
-		if (raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg))
-			goto init_fail;
-		reg &= ~RAA489000_C1_BGATE_FORCE_OFF;
-		if (raw_write16(chgnum, ISL923X_REG_CONTROL1, reg))
-			goto init_fail;
-	}
-
-	/* Revert all changes done by isl9238c_hibernate(). */
-	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C) && isl9238c_resume(chgnum))
-		goto init_fail;
-
-	if (IS_ENABLED(CHARGER_ISL9238X) ||
-	    IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		/*
-		 * Don't reread the prog pin and don't reload the ILIM on ACIN.
-		 * For the RAA489000, just don't reload ACLIM.
-		 */
-		if (raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg))
-			goto init_fail;
-		reg |= ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN;
-		if (!IS_ENABLED(CONFIG_CHARGER_RAA489000))
-			reg |= ISL9238_C3_NO_REREAD_PROG_PIN;
-
-		/*
-		 * Disable autonomous charging initially since 1) it causes boot
-		 * loop issues with 2S batteries, and 2) it will automatically
-		 * get disabled as soon as we manually set the current limit
-		 * anyway.
-		 *
-		 * Note: This bit is inverted on the RAA489000.
-		 */
-		if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
-			reg &= ~ISL9238_C3_DISABLE_AUTO_CHARING;
-		else
-			reg |= ISL9238_C3_DISABLE_AUTO_CHARING;
-		if (raw_write16(chgnum, ISL9238_REG_CONTROL3, reg))
-			goto init_fail;
-
-		/*
-		 * No need to proceed with the rest of init if we sysjump'd to
-		 * this image as the input current limit has already been set.
-		 */
-		if (system_jumped_late())
-			return;
-
-		/*
-		 * Initialize the input current limit to the board's default.
-		 */
-		if (isl923x_set_input_current_limit(
-				chgnum, CONFIG_CHARGER_INPUT_CURRENT))
-			goto init_fail;
-	}
-
-#ifdef CONFIG_OCPC
-	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
-		/*
-		 * Ignore BATGONE on auxiliary charger ICs as it's not connected
-		 * there.
-		 * Clear DISABLE_GP_CMP & MCU_LDO_BAT_STATE_DISABLE to
-		 * enable ALERT_B with control the power of sub-board
-		 */
-		if (chgnum != CHARGER_PRIMARY) {
-			if (raw_read16(chgnum, ISL9238_REG_CONTROL4, &reg))
-				goto init_fail;
-
-			reg |= RAA489000_C4_BATGONE_DISABLE;
-			reg &= ~RAA489000_C4_DISABLE_GP_CMP;
-
-			if (raw_write16(chgnum, ISL9238_REG_CONTROL4, reg))
-				goto init_fail;
-
-			if (raw_read16(chgnum, RAA489000_REG_CONTROL8, &reg))
-				goto init_fail;
-
-			reg &= ~RAA489000_C8_MCU_LDO_BAT_STATE_DISABLE;
-
-			if (raw_write16(chgnum, RAA489000_REG_CONTROL8, reg))
-				goto init_fail;
-		}
-	}
-#endif /* CONFIG_OCPC */
-
-	return;
-init_fail:
-	CPRINTS("%s init failed!", CHARGER_NAME);
-}
-
-static enum ec_error_list isl923x_discharge_on_ac(int chgnum, int enable)
-{
-	int rv;
-	int control1;
-
-	mutex_lock(&control1_mutex);
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &control1);
-	if (rv)
-		goto out;
-
-	control1 &= ~ISL923X_C1_LEARN_MODE_AUTOEXIT;
-	if (enable)
-		control1 |= ISL923X_C1_LEARN_MODE_ENABLE;
-	else
-		control1 &= ~ISL923X_C1_LEARN_MODE_ENABLE;
-
-	rv = raw_write16(chgnum, ISL923X_REG_CONTROL1, control1);
-
-	learn_mode = !rv && enable;
-
-out:
-	mutex_unlock(&control1_mutex);
-	return rv;
-}
-
-#ifdef CONFIG_CHARGER_RAA489000
-enum ec_error_list raa489000_is_acok(int chgnum, bool *acok)
-{
-	int regval, rv;
-
-	if ((chgnum < 0) || (chgnum > board_get_charger_chip_count())) {
-		CPRINTS("%s: Invalid chgnum! (%d)", __func__, chgnum);
-		return EC_ERROR_INVAL;
-	}
-
-	rv = raw_read16(chgnum, ISL9238_REG_INFO2, &regval);
-	if (rv != EC_SUCCESS)
-		return rv;
-	*acok = (regval & RAA489000_INFO2_ACOK);
-
-	return EC_SUCCESS;
-}
-
-int raa489000_enable_asgate(int chgnum, bool enable)
-{
-	enum mask_update_action action = enable ? MASK_SET : MASK_CLR;
-
-	return raw_update16(chgnum, RAA489000_REG_CONTROL8,
-			    RAA489000_C8_ASGATE_ON_READY, action);
-}
-
-void raa489000_hibernate(int chgnum, bool disable_adc)
-{
-	int rv, regval;
-
-	if ((chgnum < 0) || (chgnum > board_get_charger_chip_count())) {
-		CPRINTS("%s: Invalid chgnum! (%d)", __func__, chgnum);
-		return;
-	}
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL0, &regval);
-	if (!rv) {
-		/* set BGATE to normal operation */
-		regval &= ~RAA489000_C0_BGATE_FORCE_ON;
-
-		/* set normal charge pump operation */
-		regval &= ~RAA489000_C0_EN_CHG_PUMPS_TO_100PCT;
-
-		rv = raw_write16(chgnum, ISL923X_REG_CONTROL0, regval);
-	}
-	if (rv)
-		CPRINTS("%s(%d): Failed to set Control0!", __func__, chgnum);
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL1, &regval);
-	if (!rv) {
-		/* Disable Supplemental support */
-		regval &= ~RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE;
-
-		/*
-		 * Force BGATE off.  For devices that utilize the Z-state, the
-		 * LDO will be powered through the BFET's body diode.
-		 */
-		regval |= RAA489000_C1_BGATE_FORCE_OFF;
-
-		/* Disable AMON/BMON */
-		regval |= ISL923X_C1_DISABLE_MON;
-
-		/* Disable PSYS */
-		regval &= ~ISL923X_C1_ENABLE_PSYS;
-
-		rv = raw_write16(chgnum, ISL923X_REG_CONTROL1, regval);
-	}
-	if (rv)
-		CPRINTS("%s(%d): Failed to set Control1!", __func__, chgnum);
-
-	rv = raw_read16(chgnum, ISL9238_REG_CONTROL3, &regval);
-	if (!rv) {
-		if (disable_adc)
-			/* ADC is active only when adapter plugged in */
-			regval &= ~RAA489000_ENABLE_ADC;
-		else
-			regval |= RAA489000_ENABLE_ADC;
-
-		rv = raw_write16(chgnum, ISL9238_REG_CONTROL3, regval);
-	}
-	if (rv)
-		CPRINTS("%s(%d): Failed to set Control3!", __func__, chgnum);
-
-	rv = raw_read16(chgnum, ISL9238_REG_CONTROL4, &regval);
-	if (!rv) {
-		/* Disable GP comparator for battery only mode */
-		regval |= RAA489000_C4_DISABLE_GP_CMP;
-
-		rv = raw_write16(chgnum, ISL9238_REG_CONTROL4, regval);
-	}
-	if (rv)
-		CPRINTS("%s(%d):Failed to set Control4!", __func__, chgnum);
-
-#ifdef CONFIG_OCPC
-	/* The LDO is needed in the Z-state on the primary charger */
-	if (chgnum != CHARGER_PRIMARY) {
-		rv = raw_read16(chgnum, RAA489000_REG_CONTROL8, &regval);
-		if (!rv) {
-			/* Disable MCU LDO in battery state */
-			regval |= RAA489000_C8_MCU_LDO_BAT_STATE_DISABLE;
-
-			rv = raw_write16(chgnum, RAA489000_REG_CONTROL8,
-					 regval);
-		}
-		if (rv)
-			CPRINTS("%s(%d):Failed to set Control8!", __func__,
-				chgnum);
-	}
-
-	/* Disable DVC on the main charger to reduce power consumption. */
-	if (chgnum == CHARGER_PRIMARY) {
-		rv = raw_write16(chgnum, RAA489000_REG_CONTROL10, 0);
-		if (rv)
-			CPRINTS("%s(%d):Failed to set Control10!", __func__,
-				chgnum);
-	}
-#endif
-
-	cflush();
-}
-#endif /* CONFIG_CHARGER_RAA489000 */
-
-#ifdef CONFIG_CHARGER_ISL9238C
-enum ec_error_list isl9238c_hibernate(int chgnum)
-{
-	/* Disable IMON */
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_DISABLE_MON, MASK_SET));
-
-	/* Disable PSYS */
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_CLR));
-
-	/* Disable GP comparator */
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_SET));
-
-	/* Force BGATE off */
-	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_SET));
-
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list isl9238c_resume(int chgnum)
-{
-	/* Revert everything in isl9238c_hibernate() */
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_DISABLE_MON, MASK_CLR));
-
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_SET));
-
-	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_CLR));
-
-	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_CLR));
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_CHARGER_ISL9238C */
-
-
-/*****************************************************************************/
-/* Hardware current ramping */
-
-#ifdef CONFIG_CHARGE_RAMP_HW
-static enum ec_error_list isl923x_set_hw_ramp(int chgnum, int enable)
-{
-	int rv, reg;
-
-	rv = raw_read16(chgnum, ISL923X_REG_CONTROL0, &reg);
-	if (rv)
-		return rv;
-
-	/* HW ramp is controlled by input voltage regulation reference bits */
-	if (enable)
-		reg &= ~ISL923X_C0_DISABLE_VREG;
-	else
-		reg |= ISL923X_C0_DISABLE_VREG;
-
-	return raw_write16(chgnum, ISL923X_REG_CONTROL0, reg);
-}
-
-static int isl923x_ramp_is_stable(int chgnum)
-{
-	/*
-	 * Since ISL cannot read the current limit that the ramp has settled
-	 * on, then we can never consider the ramp stable, because we never
-	 * know what the stable limit is.
-	 */
-	return 0;
-}
-
-static int isl923x_ramp_is_detected(int chgnum)
-{
-	return 1;
-}
-
-static int isl923x_ramp_get_current_limit(int chgnum)
-{
-	/*
-	 * ISL doesn't have a way to get this info, so return the nominal
-	 * current limit as an estimate.
-	 */
-	int input_current;
-
-	if (isl923x_get_input_current_limit(chgnum, &input_current))
-		return 0;
-	return input_current;
-}
-#endif /* CONFIG_CHARGE_RAMP_HW */
-
-
-#ifdef CONFIG_CHARGER_PSYS
-static int psys_enabled;
-/*
- * TODO(b/147440290): Set to appropriate charger with multiple charger support,
- * hardcode to 0 for now
- */
-static void charger_enable_psys(void)
-{
-	int val;
-
-	mutex_lock(&control1_mutex);
-
-	/*
-	 * enable system power monitor PSYS function
-	 */
-	if (raw_read16(CHARGER_SOLO, ISL923X_REG_CONTROL1, &val))
-		goto out;
-
-	val |= ISL923X_C1_ENABLE_PSYS;
-
-	if (raw_write16(CHARGER_SOLO, ISL923X_REG_CONTROL1, val))
-		goto out;
-
-	psys_enabled = 1;
-
-out:
-	mutex_unlock(&control1_mutex);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, charger_enable_psys, HOOK_PRIO_DEFAULT);
-
-static void charger_disable_psys(void)
-{
-	int val;
-
-	mutex_lock(&control1_mutex);
-
-	/*
-	 * disable system power monitor PSYS function
-	 */
-	if (raw_read16(CHARGER_SOLO, ISL923X_REG_CONTROL1, &val))
-		goto out;
-
-	val &= ~ISL923X_C1_ENABLE_PSYS;
-
-	if (raw_write16(CHARGER_SOLO, ISL923X_REG_CONTROL1, val))
-		goto out;
-
-	psys_enabled = 0;
-
-out:
-	mutex_unlock(&control1_mutex);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, charger_disable_psys, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CHARGER_PSYS_READ
-int charger_get_system_power(void)
-{
-	int adc;
-
-	/*
-	 * If PSYS is not enabled, AP is probably off, and the value is usually
-	 * too small to be measured acurately anyway.
-	 */
-	if (!psys_enabled)
-		return -1;
-
-	/*
-	 * We assume that the output gain is always left to the default
-	 * 1.44 uA/W, and that the ADC scaling values are setup accordingly in
-	 * board file, so that the value is indicated in uW.
-	 */
-	adc = adc_read_channel(ADC_PSYS);
-
-	return adc;
-}
-
-static int console_command_psys(int argc, char **argv)
-{
-	ccprintf("PSYS = %d uW\n", charger_get_system_power());
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
-			"Get the system power in mW");
-#endif /* CONFIG_CHARGER_PSYS_READ */
-#endif /* CONFIG_CHARGER_PSYS */
-
-#ifdef CONFIG_CMD_CHARGER_ADC_AMON_BMON
-static int print_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
-			   enum isl923x_mon_dir direction, int resistor)
-{
-	int ret, adc, curr;
-
-	ret = get_amon_bmon(chgnum, amon, direction, &adc);
-	if (ret)
-		return ret;
-
-	curr = adc / resistor;
-	ccprintf("%cMON(%sharging): %d uV, %d mA\n", amon == AMON ? 'A' : 'B',
-		direction == MON_DISCHARGE ? "Disc" : "C", adc, curr);
-
-	return ret;
-}
-
-/**
- * Get charger AMON and BMON current.
- */
-static int console_command_amon_bmon(int argc, char **argv)
-{
-	int ret = EC_SUCCESS;
-	int print_ac = 1;
-	int print_battery = 1;
-	int print_charge = 1;
-	int print_discharge = 1;
-	int chgnum = 0;
-	char *e;
-
-	if (argc >= 2) {
-		print_ac = (argv[1][0] == 'a');
-		print_battery = (argv[1][0] == 'b');
-		if (IS_ENABLED(CHARGER_ISL9238X) && argv[1][1] != '\0') {
-			print_charge = (argv[1][1] == 'c');
-			print_discharge = (argv[1][1] == 'd');
-		}
-		if (argc >= 3) {
-			chgnum = strtoi(argv[2], &e, 10);
-			if (*e)
-				return EC_ERROR_PARAM2;
-		}
-	}
-
-	if (print_ac) {
-		if (print_charge)
-			ret |= print_amon_bmon(chgnum, AMON, MON_CHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
-		if (IS_ENABLED(CHARGER_ISL9238X) && print_discharge)
-			ret |= print_amon_bmon(chgnum, AMON, MON_DISCHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
-	}
-
-	if (print_battery) {
-		if (IS_ENABLED(CHARGER_ISL9238X) && print_charge)
-			ret |= print_amon_bmon(chgnum, BMON, MON_CHARGE,
-					/*
-					 * charging current monitor has
-					 * 2x amplification factor
-					 */
-					2 * CONFIG_CHARGER_SENSE_RESISTOR);
-		if (print_discharge)
-			ret |= print_amon_bmon(chgnum, BMON, MON_DISCHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR);
-	}
-
-	return ret;
-}
-DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon,
-#ifdef CONFIG_CHARGER_ISL9237
-			"amonbmon [a|b] <chgnum>",
-#else
-			"amonbmon [a[c|d]|b[c|d]] <chgnum>",
-#endif
-			"Get charger AMON/BMON voltage diff, current");
-#endif /* CONFIG_CMD_CHARGER_ADC_AMON_BMON */
-
-#ifdef CONFIG_CMD_CHARGER_DUMP
-static void dump_reg_range(int chgnum, int low, int high)
-{
-	int reg;
-	int regval;
-	int rv;
-
-	for (reg = low; reg <= high; reg++) {
-		CPRINTF("[%Xh] = ", reg);
-		rv = i2c_read16(chg_chips[chgnum].i2c_port,
-				chg_chips[chgnum].i2c_addr_flags,
-				reg, &regval);
-		if (!rv)
-			CPRINTF("0x%04x\n", regval);
-		else
-			CPRINTF("ERR (%d)\n", rv);
-		cflush();
-	}
-}
-
-static int command_isl923x_dump(int argc, char **argv)
-{
-	int chgnum = 0;
-	char *e;
-
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	dump_reg_range(chgnum, 0x14, 0x15);
-	if (IS_ENABLED(CONFIG_CHARGER_ISL9238C))
-		dump_reg_range(chgnum, 0x37, 0x37);
-	dump_reg_range(chgnum, 0x38, 0x3F);
-	dump_reg_range(chgnum, 0x47, 0x4A);
-	if (IS_ENABLED(CHARGER_ISL9238X) ||
-	    IS_ENABLED(CONFIG_CHARGER_RAA489000))
-		dump_reg_range(chgnum, 0x4B, 0x4E);
-	dump_reg_range(chgnum, 0xFE, 0xFF);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(charger_dump, command_isl923x_dump,
-			"charger_dump <chgnum>", "Dumps ISL923x registers");
-#endif /* CONFIG_CMD_CHARGER_DUMP */
-
-static enum ec_error_list isl923x_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
-{
-	int val;
-	int rv;
-
-	rv = raw_read16(chgnum, RAA489000_REG_ADC_VBUS, &val);
-	if (rv)
-		return rv;
-
-	/* The VBUS voltage is returned in bits 13:6. The LSB is 96mV. */
-	val &= GENMASK(13, 6);
-	val = val >> 6;
-	val *= 96;
-	*voltage = val;
-
-	return EC_SUCCESS;
-}
-
-#if defined(CONFIG_CHARGER_RAA489000) && defined(CONFIG_OCPC)
-static enum ec_error_list raa489000_enable_linear_charge(int chgnum,
-							 bool enable)
-{
-	const struct battery_info *batt_info;
-	int trickle_regval;
-	int precharge_current;
-	int regval;
-	enum ec_error_list rv;
-	int act_chg = charge_get_active_chg_chip();
-
-	batt_info = battery_get_info();
-
-	if (enable) {
-		/* Set the auxiliary max VSYS to 300mV + min VSYS. */
-		rv = isl9237_set_voltage(act_chg, batt_info->voltage_min + 300);
-
-		/* Disable charge current loop for the aux charger. */
-		rv |= raw_update16(act_chg, RAA489000_REG_CONTROL10,
-				   RAA489000_C10_DISABLE_DVC_CC_LOOP,
-				   MASK_SET);
-
-		/*
-		 * Set primary charger charge current to the desired precharge
-		 * current.
-		 */
-		rv |= isl9237_set_current(CHARGER_PRIMARY,
-				    batt_info->precharge_current);
-
-		/*
-		 * Set primary charger max VSYS to the max of the battery.
-		 */
-		rv |= isl9237_set_voltage(CHARGER_PRIMARY,
-					  batt_info->voltage_max);
-
-		/*
-		 * Set trickle charging level.
-		 *
-		 * 64mA is the minimum current level we must set.
-		 */
-		precharge_current = MAX(64, batt_info->precharge_current);
-		trickle_regval = precharge_current / 32;
-		trickle_regval--; /* convert to 0-based field */
-		rv |= raw_read16(CHARGER_PRIMARY, ISL923X_REG_CONTROL2,
-				 &regval);
-		regval &= ~(GENMASK(15, 13));
-		regval |= trickle_regval << 13;
-		rv |= raw_write16(CHARGER_PRIMARY, ISL923X_REG_CONTROL2,
-				  regval);
-
-		/* Enable DVC trickle charge and DVC charge mode. */
-		rv |= raw_update16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
-				   RAA489000_C10_ENABLE_DVC_MODE |
-				   RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
-				   MASK_SET);
-
-		if (rv)
-			return EC_ERROR_UNKNOWN;
-
-	} else {
-		/* Disable DVC trickle charge. */
-		rv = raw_update16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
-				  RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
-				  MASK_CLR);
-	}
-
-	return rv;
-}
-
-static enum ec_error_list raa489000_set_vsys_compensation(int chgnum,
-							  struct ocpc_data *o,
-							  int current_ma,
-							  int voltage_mv)
-{
-	int device_id = 0;
-	int rv;
-	int rp1;
-	int rp2;
-	int regval;
-
-	/* This should never be called against the primary charger. */
-	ASSERT(chgnum != CHARGER_PRIMARY);
-
-	/* Only B0+ silicon supports VSYS compensation. */
-	rv = isl923x_device_id(chgnum, &device_id);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Note: this makes the assumption that this charger IC is used on the
-	 * primary port as well.
-	 */
-
-	if (device_id < RAA489000_DEV_ID_B0)
-		return EC_ERROR_UNIMPLEMENTED;
-
-	/*
-	 * Need to set board resistance values: Rp1 and Rp2.  These are expected
-	 * to be fairly constant once we are able to calculate their values.
-	 *
-	 * Rp1 is the total resistance from the right-hand side of the
-	 * auxiliary sense resistor to the actual VSYS node.  It should include:
-	 * a.     resistance of sub board sense resistor
-	 * b.     connector/cable resistance
-	 * c.     sub board PCB resistance to the actual VSYS node
-	 *
-	 * Rp2 is the total resistance from the actual VSYS node to the battery.
-	 * It should include:
-	 * a.     resistance of primary charger sense resistor (battery side)
-	 * b.     Rds(on) of BGATE FET
-	 * c.     main board PCB resistance to the battery
-	 * d.     battery internal resistance
-	 */
-
-	/*
-	 * Rp1 is set between 36-156mOhms in 4mOhm increments.  This must be
-	 * non-zero in order for compensation to work.
-	 *
-	 * To get Rp1, we need to look at the delta between VSYS measured by the
-	 * auxiliary charger IC and the primary charger IC where the actual VSYS
-	 * node is as well as the current provided by the auxiliary charger IC.
-	 * The system keeps track of combined resistance; therefore, Rp2 is the
-	 * difference between the combined resistance and Rp1 that we calculate.
-	 * If Rp1 is less than 36mOhms, then the compensation is disabled.
-	 */
-
-	rp1 = MIN(o->rsys_mo, RAA489000_RP1_MAX);
-	rp1 -= RAA489000_RP1_MIN;
-	if (rp1 < 0) {
-		if (o->last_vsys == OCPC_UNINIT)
-			CPRINTS("RAA489000(%d): Disabling DVC (Rp1 < 36mOhms)",
-				chgnum);
-		rp1 = 0;
-	} else {
-		rp1 /= 4;
-		rp1++; /* Rp1 min starts at register value 1 */
-	}
-
-	/* Rp2 is set between 0-124mOhms in 4mOhm increments. */
-	rp2 = o->rbatt_mo;
-	rp2 = CLAMP(rp2, RAA489000_RP2_MIN, RAA489000_RP2_MAX);
-	rp2 /= 4;
-
-	rv |= raw_read16(chgnum, RAA489000_REG_CONTROL10, &regval);
-	if (!rv) {
-		/* Set Rp1 and Rp2 */
-		regval &= ~RAA489000_C10_RP1_MASK;
-		regval &= ~RAA489000_C10_RP2_MASK;
-		regval |= rp2;
-		regval |= (rp1 << RAA489000_C10_RP1_SHIFT);
-
-		/* Enable DVC mode */
-		regval |= RAA489000_C10_ENABLE_DVC_MODE;
-
-		/* Disable charge current loop */
-		regval |= RAA489000_C10_DISABLE_DVC_CC_LOOP;
-
-		rv |= raw_write16(chgnum, RAA489000_REG_CONTROL10, regval);
-	}
-
-	if (rv) {
-		CPRINTS("%s(%d) Failed to enable DVC!", __func__, chgnum);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Lastly, enable DVC fast charge mode for the primary charger IC. */
-	rv = raw_read16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10, &regval);
-	regval |= RAA489000_C10_ENABLE_DVC_CHARGE_MODE;
-	rv |= raw_write16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10, regval);
-	if (rv) {
-		CPRINTS("%s Failed to enable DVC on primary charger!",
-			__func__);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/*
-	 * We'll need to use the PID loop in order to properly set VSYS such
-	 * such that we get the desired charge current.
-	 */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-#endif /* CONFIG_CHARGER_RAA489000 && CONFIG_OCPC */
-
-const struct charger_drv isl923x_drv = {
-	.init = &isl923x_init,
-	.post_init = &isl923x_post_init,
-	.get_info = &isl923x_get_info,
-	.get_status = &isl923x_get_status,
-	.set_mode = &isl923x_set_mode,
-#if defined(CONFIG_CHARGER_OTG) && defined(CHARGER_ISL9238X)
-	.enable_otg_power = &isl923x_enable_otg_power,
-	.set_otg_current_voltage = &isl923x_set_otg_current_voltage,
-#endif
-#ifdef CONFIG_CHARGER_RAA489000
-	.get_actual_current = &raa489000_get_actual_current,
-#endif
-	.get_current = &isl923x_get_current,
-	.set_current = &isl923x_set_current,
-#ifdef CONFIG_CHARGER_RAA489000
-	.get_actual_voltage = &raa489000_get_actual_voltage,
-#endif
-	.get_voltage = &isl923x_get_voltage,
-	.set_voltage = &isl923x_set_voltage,
-	.discharge_on_ac = &isl923x_discharge_on_ac,
-	.get_vbus_voltage = &isl923x_get_vbus_voltage,
-	.set_input_current_limit = &isl923x_set_input_current_limit,
-	.get_input_current_limit = &isl923x_get_input_current_limit,
-#ifdef CONFIG_CHARGER_RAA489000
-	.get_input_current = &raa489000_get_input_current,
-#elif defined(CONFIG_CMD_CHARGER_ADC_AMON_BMON)
-	.get_input_current = &isl923x_get_input_current,
-#endif
-	.manufacturer_id = &isl923x_manufacturer_id,
-	.device_id = &isl923x_device_id,
-	.get_option = &isl923x_get_option,
-	.set_option = &isl923x_set_option,
-#ifdef CONFIG_CHARGE_RAMP_HW
-	.set_hw_ramp = &isl923x_set_hw_ramp,
-	.ramp_is_stable = &isl923x_ramp_is_stable,
-	.ramp_is_detected = &isl923x_ramp_is_detected,
-	.ramp_get_current_limit = &isl923x_ramp_get_current_limit,
-#endif
-#if defined(CONFIG_CHARGER_RAA489000) && defined(CONFIG_OCPC)
-	.enable_linear_charge = &raa489000_enable_linear_charge,
-	.set_vsys_compensation = &raa489000_set_vsys_compensation,
-#endif
-};
diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h
deleted file mode 100644
index 558c17f971..0000000000
--- a/driver/charger/isl923x.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Intersil ISL-9237/8 battery charger driver.
- * Also supports Renesas RAA489000 battery charger.
- */
-
-#ifndef __CROS_EC_ISL923X_H
-#define __CROS_EC_ISL923X_H
-
-#include "driver/charger/isl923x_public.h"
-
-/* Registers */
-#define ISL923X_REG_CHG_CURRENT            0x14
-#define ISL923X_REG_ADAPTER_CURRENT_LIMIT1 0x3f
-#define ISL923X_REG_ADAPTER_CURRENT_LIMIT2 0x3b
-#define ISL923X_REG_SYS_VOLTAGE_MAX        0x15
-#define ISL923X_REG_SYS_VOLTAGE_MIN        0x3e
-#define ISL923X_REG_PROCHOT_AC             0x47
-#define ISL923X_REG_PROCHOT_DC             0x48
-#define ISL923X_REG_T1_T2                  0x38
-#define ISL923X_REG_CONTROL0               0x39
-#define ISL923X_REG_CONTROL1               0x3c
-#define ISL923X_REG_CONTROL2               0x3d
-#define ISL9238_REG_CONTROL3               0x4c
-#define ISL9238_REG_CONTROL4               0x4e
-#define ISL9238C_REG_CONTROL6              0x37
-#define ISL923X_REG_INFO                   0x3a
-#define ISL9238_REG_INFO2                  0x4d
-#define ISL923X_REG_OTG_VOLTAGE            0x49
-#define ISL923X_REG_OTG_CURRENT            0x4a
-#define ISL9238_REG_INPUT_VOLTAGE          0x4b
-#define ISL923X_REG_MANUFACTURER_ID        0xfe
-#define ISL923X_REG_DEVICE_ID              0xff
-#define RAA489000_REG_CONTROL8             0x37
-#define RAA489000_REG_CONTROL10            0x35
-
-/* Sense resistor default values in mOhm */
-#define ISL923X_DEFAULT_SENSE_RESISTOR_AC 20
-#define ISL923X_DEFAULT_SENSE_RESISTOR 10
-
-/* Maximum charging current register value */
-#define ISL923X_CURRENT_REG_MAX 0x17c0 /* bit<12:2> 10111110000 */
-#define RAA489000_CURRENT_REG_MAX 0x1ffc
-
-/* 2-level adpater current limit duration T1 & T2 in micro seconds */
-#define ISL923X_T1_10000 0x00
-#define ISL923X_T1_20000 0x01
-#define ISL923X_T1_15000 0x02
-#define ISL923X_T1_5000  0x03
-#define ISL923X_T1_1000  0x04
-#define ISL923X_T1_500   0x05
-#define ISL923X_T1_100   0x06
-#define ISL923X_T1_0     0x07
-#define ISL923X_T2_10    (0x00 << 8)
-#define ISL923X_T2_100   (0x01 << 8)
-#define ISL923X_T2_500   (0x02 << 8)
-#define ISL923X_T2_1000  (0x03 << 8)
-#define ISL923X_T2_300   (0x04 << 8)
-#define ISL923X_T2_750   (0x05 << 8)
-#define ISL923X_T2_2000  (0x06 << 8)
-#define ISL923X_T2_10000 (0x07 << 8)
-
-#define ISL9237_SYS_VOLTAGE_REG_MAX 13824
-#define ISL9238_SYS_VOLTAGE_REG_MAX 18304
-#define ISL923X_SYS_VOLTAGE_REG_MIN 2048
-#define RAA489000_SYS_VOLTAGE_REG_MAX 18304
-#define RAA489000_SYS_VOLTAGE_REG_MIN 64
-
-/* PROCHOT# debounce time and duration time in micro seconds */
-#define ISL923X_PROCHOT_DURATION_10000  (0 << 6)
-#define ISL923X_PROCHOT_DURATION_20000  BIT(6)
-#define ISL923X_PROCHOT_DURATION_15000  (2 << 6)
-#define ISL923X_PROCHOT_DURATION_5000   (3 << 6)
-#define ISL923X_PROCHOT_DURATION_1000   (4 << 6)
-#define ISL923X_PROCHOT_DURATION_500    (5 << 6)
-#define ISL923X_PROCHOT_DURATION_100000 (6 << 6)
-#define ISL923X_PROCHOT_DURATION_0      (7 << 6)
-#define ISL923X_PROCHOT_DURATION_MASK   (7 << 6)
-
-#define ISL923X_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_PROCHOT_DEBOUNCE_500  (2 << 9)
-#define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9)
-#define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9)
-
-/* Maximum PROCHOT register value */
-#define ISL923X_PROCHOT_AC_REG_MAX 6400
-#define ISL923X_PROCHOT_DC_REG_MAX 12800
-
-/* Control0: adapter voltage regulation reference */
-#define ISL9237_C0_VREG_REF_3900 0
-#define ISL9237_C0_VREG_REF_4200 1
-#define ISL9237_C0_VREG_REF_4500 2
-#define ISL9237_C0_VREG_REF_4800 3
-#define ISL9237_C0_VREG_REF_MASK 0x03
-
-/* Control0: disable adapter voltaqe regulation */
-#define ISL923X_C0_DISABLE_VREG BIT(2)
-
-/* Control0: battery DCHOT reference for RS2 == 20mOhm */
-#define ISL923X_C0_DCHOT_6A   (0 << 3)
-#define ISL923X_C0_DCHOT_5A   BIT(3)
-#define ISL923X_C0_DCHOT_4A   (2 << 3)
-#define ISL923X_C0_DCHOT_3A   (3 << 3)
-#define ISL923X_C0_DCHOT_MASK (3 << 3)
-
-/* Control0: BGATE force on */
-#define RAA489000_C0_BGATE_FORCE_ON BIT(10)
-#define RAA489000_C0_EN_CHG_PUMPS_TO_100PCT BIT(6)
-
-/* Control1: general purpose comparator debounce time in micro second */
-#define ISL923X_C1_GP_DEBOUNCE_2       (0 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_12      BIT(14)
-#define ISL923X_C1_GP_DEBOUNCE_2000    (2 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_MASK    (3 << 14)
-
-/* Control1: learn mode */
-#define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13)
-#define ISL923X_C1_LEARN_MODE_ENABLE   BIT(12)
-
-/* Control1: OTG enable */
-#define ISL923X_C1_OTG BIT(11)
-
-/* Control1: audio filter */
-#define ISL923X_C1_AUDIO_FILTER BIT(10)
-
-/* Control1: switch frequency, ISL9238 defines bit 7 as unused */
-#define ISL923X_C1_SWITCH_FREQ_PROG (0 << 7) /* 1000kHz or PROG */
-#define ISL9237_C1_SWITCH_FREQ_913K BIT(7)
-#define ISL923X_C1_SWITCH_FREQ_839K (2 << 7)
-#define ISL9237_C1_SWITCH_FREQ_777K (3 << 7)
-#define ISL923X_C1_SWITCH_FREQ_723K (4 << 7)
-#define ISL9237_C1_SWITCH_FREQ_676K (5 << 7)
-#define ISL923X_C1_SWITCH_FREQ_635K (6 << 7)
-#define ISL9237_C1_SWITCH_FREQ_599K (7 << 7)
-#define ISL923X_C1_SWITCH_FREQ_MASK (7 << 7)
-
-/* Control1: turbo mode */
-#define ISL923X_C1_TURBO_MODE BIT(6)
-
-/* Control1: AMON & BMON */
-#define ISL923X_C1_DISABLE_MON BIT(5)
-#define ISL923X_C1_SELECT_BMON BIT(4)
-
-/* Control1: PSYS, VSYS, VSYSLO */
-#define ISL923X_C1_ENABLE_PSYS BIT(3)
-#define ISL923X_C1_ENABLE_VSYS BIT(2)
-#define ISL923X_C1_VSYSLO_REF_6000 0
-#define ISL923X_C1_VSYSLO_REF_6300 1
-#define ISL923X_C1_VSYSLO_REF_6600 2
-#define ISL923X_C1_VSYSLO_REF_6900 3
-#define ISL923X_C1_VSYSLO_REF_MASK 3
-
-/* Control1: Supplemental mode support */
-#define RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE BIT(10)
-
-/* Control1: BGATE Force Off */
-#define RAA489000_C1_BGATE_FORCE_OFF BIT(6)
-
-/* Control2: trickle charging current in mA */
-#define ISL923X_C2_TRICKLE_256  (0 << 14)
-#define ISL923X_C2_TRICKLE_128  BIT(14)
-#define ISL923X_C2_TRICKLE_64   (2 << 14)
-#define ISL923X_C2_TRICKLE_512  (3 << 14)
-#define ISL923X_C2_TRICKLE_MASK (3 << 14)
-
-/* Control2: OTGEN debounce time in ms */
-#define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13)
-#define ISL923X_C2_OTG_DEBOUNCE_150  BIT(13)
-#define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13)
-
-/* Control2: 2-level adapter over current */
-#define ISL923X_C2_2LVL_OVERCURRENT BIT(12)
-
-/* Control2: adapter insertion debounce time in ms */
-#define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11)
-#define ISL923X_C2_ADAPTER_DEBOUNCE_150  BIT(11)
-#define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11)
-
-/* Control2: PROCHOT debounce time in uS */
-#define ISL9238_C2_PROCHOT_DEBOUNCE_7    (0 << 9)
-#define ISL9237_C2_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_500  (2 << 9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9)
-
-/* Control2: min PROCHOT duration in uS */
-#define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6)
-#define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_5000  (3 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_1000  (4 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_500   (5 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_100   (6 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_0     (7 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_MASK  (7 << 6)
-
-/* Control2: turn off ASGATE in OTG mode */
-#define ISL923X_C2_ASGATE_OFF BIT(5)
-
-/* Control2: CMIN, general purpose comparator reference in mV */
-#define ISL923X_C2_CMIN_2000 (0 << 4)
-#define ISL923X_C2_CMIN_1200 BIT(4)
-
-/* Control2: general purpose comparator enable */
-#define ISL923X_C2_COMPARATOR BIT(3)
-
-/* Control2: invert CMOUT, general purpose comparator output, polarity */
-#define ISL923X_C2_INVERT_CMOUT BIT(2)
-
-/* Control2: disable WOC, way over current */
-#define ISL923X_C2_WOC_OFF BIT(1)
-
-/* Control2: PSYS gain in uA/W (ISL9237 only) */
-#define ISL9237_C2_PSYS_GAIN BIT(0)
-
-/* Control3: Enable ADC for all modes */
-#define RAA489000_ENABLE_ADC BIT(0)
-
-/*
- * Control3: Buck-Boost switching period
- * 0: x1 frequency, 1: half frequency.
- */
-#define ISL9238_C3_BB_SWITCHING_PERIOD BIT(1)
-
-/*
- * Control3: AMON/BMON direction.
- * 0: adapter/charging, 1:OTG/discharging (ISL9238 only)
- */
-#define ISL9238_C3_AMON_BMON_DIRECTION BIT(3)
-
-/*
- * Control3: Disables Autonomous Charing
- *
- * Note: This is disabled automatically when ever we set the current limit
- * manually (which we always do).
- */
-#define ISL9238_C3_DISABLE_AUTO_CHARING BIT(7)
-
-/* Control3: PSYS gain in uA/W (ISL9238 only) */
-#define ISL9238_C3_PSYS_GAIN BIT(9)
-
-/* Control3: Enables or disables Battery Ship mode */
-#define ISL9238_C3_BGATE_OFF BIT(10)
-
-/* Control3: Enable or disable DCM/CCM Hysteresis */
-#define RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE BIT(10)
-
-/* Control3: Don't reload ACLIM on ACIN. */
-#define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN BIT(14)
-
-/* Control3: Don't reread PROG pin. */
-#define ISL9238_C3_NO_REREAD_PROG_PIN BIT(15)
-
-/* Control4: PSYS Rsense ratio. */
-#define RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1 BIT(11)
-
-/* Control4: GP comparator control bit */
-#define RAA489000_C4_DISABLE_GP_CMP BIT(12)
-
-/* Control4: Ignores BATGONE input */
-#define RAA489000_C4_BATGONE_DISABLE BIT(15)
-
-/* Control6: charger current and maximum system voltage slew rate control. */
-#define ISL9238C_C6_SLEW_RATE_CONTROL BIT(6)
-
-/* Control8: MCU_LDO - BAT state disable */
-#define RAA489000_C8_MCU_LDO_BAT_STATE_DISABLE BIT(14)
-#define RAA489000_C8_ASGATE_ON_READY BIT(13)
-
-/* OTG voltage limit in mV, current limit in mA */
-#define ISL9237_OTG_VOLTAGE_MIN 4864
-#define ISL9237_OTG_VOLTAGE_MAX 5376
-#define ISL9238_OTG_VOLTAGE_MAX 27456
-#define ISL923X_OTG_CURRENT_MAX 4096
-
-#define ISL9238_OTG_VOLTAGE_STEP 12
-#define ISL9238_OTG_VOLTAGE_SHIFT 3
-#define ISL923X_OTG_CURRENT_STEP 128
-#define ISL923X_OTG_CURRENT_SHIFT 7
-
-/* Input voltage regulation voltage reference */
-#define ISL9238_INPUT_VOLTAGE_REF_STEP 341
-#define ISL9238_INPUT_VOLTAGE_REF_SHIFT 8
-#define RAA489000_INPUT_VOLTAGE_REF_STEP 85
-#define RAA489000_INPUT_VOLTAGE_REF_SHIFT 6
-
-/* Info register fields */
-#define ISL9237_INFO_PROG_RESISTOR_MASK 0xf
-#define ISL923X_INFO_TRICKLE_ACTIVE_MASK BIT(4)
-#define ISL9237_INFO_PSTATE_SHIFT 5
-#define ISL9237_INFO_PSTATE_MASK 3
-#define RAA489000_INFO2_ACOK BIT(14)
-
-/* ADC registers */
-#define RAA489000_REG_ADC_INPUT_CURRENT 0x83
-#define RAA489000_REG_ADC_CHARGE_CURRENT 0x85
-#define RAA489000_REG_ADC_VSYS 0x86
-#define RAA489000_REG_ADC_VBUS 0x89
-
-enum isl9237_power_stage {
-	BUCK_MODE,
-	BOOST_MODE,
-	BUCK_BOOST_MODE,
-	REVERSE_BUCK_MODE
-};
-
-#define ISL9237_INFO_FSM_STATE_SHIFT 7
-#define ISL9237_INFO_FSM_STATE_MASK 7
-
-enum isl9237_fsm_state {
-	FSM_OFF,
-	FSM_BAT,
-	FSM_ADPT,
-	FSM_ACOK,
-	FSM_VSYS,
-	FSM_CHRG,
-	FSM_ENTOG,
-	FSM_OTG
-};
-
-#define ISL923X_INFO_VSYSLO BIT(10)
-#define ISL923X_INFO_DCHOT BIT(11)
-#define ISL9237_INFO_ACHOT BIT(12)
-
-#define RAA489000_DEV_ID_B0 0x11
-
-/* DVC - Dynamic Voltage Compensation */
-#define RAA489000_RP1_MAX 156
-#define RAA489000_RP1_MIN 36
-#define RAA489000_RP2_MAX 124
-#define RAA489000_RP2_MIN 0
-
-#define RAA489000_C10_RP2_MASK GENMASK(4, 0)
-#define RAA489000_C10_DISABLE_DVC_AUTO_ZERO BIT(5)
-#define RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE BIT(6)
-#define RAA489000_C10_DISABLE_DVC_CC_LOOP BIT(8)
-#define RAA489000_C10_ENABLE_DVC_CHARGE_MODE BIT(9)
-#define RAA489000_C10_RP1_MASK GENMASK(14, 10)
-#define RAA489000_C10_RP1_SHIFT 10
-#define RAA489000_C10_ENABLE_DVC_MODE BIT(15)
-
-#define I2C_ADDR_CHARGER_FLAGS ISL923X_ADDR_FLAGS
-
-#define ISL923X_AC_PROCHOT_CURRENT_MAX	6400	/* mA */
-#define ISL923X_DC_PROCHOT_CURRENT_MAX	12800	/* mA */
-
-#endif /* __CROS_EC_ISL923X_H */
diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c
deleted file mode 100644
index 794ea0b342..0000000000
--- a/driver/charger/isl9241.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Renesas (Intersil) ISL-9241 battery charger driver.
- */
-
-/* TODO(b/175881324) */
-#ifndef CONFIG_ZEPHYR
-#include "adc.h"
-#endif
-#include "battery.h"
-#include "battery_smart.h"
-#include "charger.h"
-#include "charge_state.h"
-#include "console.h"
-#include "common.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "isl9241.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#ifndef CONFIG_CHARGER_NARROW_VDC
-#error "ISL9241 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
-#endif
-
-/* Sense resistor default values in milli Ohm */
-#define ISL9241_DEFAULT_RS1 20	/* Input current sense resistor */
-#define ISL9241_DEFAULT_RS2 10	/* Battery charge current sense resistor */
-
-#define BOARD_RS1 CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define BOARD_RS2 CONFIG_CHARGER_SENSE_RESISTOR
-
-#define BC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS2) / BOARD_RS2)
-#define BC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS2) / ISL9241_DEFAULT_RS2)
-
-#define AC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS1) / BOARD_RS1)
-#define AC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS1) / ISL9241_DEFAULT_RS1)
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-
-static int learn_mode;
-
-/* Mutex for CONTROL1 register, that can be updated from multiple tasks. */
-K_MUTEX_DEFINE(control1_mutex);
-
-/* Charger parameters */
-static const struct charger_info isl9241_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
-	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
-	.input_current_step = INPUT_I_STEP,
-};
-
-static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable);
-
-static inline enum ec_error_list isl9241_read(int chgnum, int offset,
-					      int *value)
-{
-	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-
-static inline enum ec_error_list isl9241_write(int chgnum, int offset,
-					       int value)
-{
-	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
-}
-
-static inline enum ec_error_list isl9241_update(int chgnum, int offset,
-						uint16_t mask,
-						enum mask_update_action action)
-{
-	return i2c_update16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, mask, action);
-}
-
-/* chip specific interfaces */
-
-/*****************************************************************************/
-/* Charger interfaces */
-static enum ec_error_list isl9241_set_input_current_limit(int chgnum,
-							  int input_current)
-{
-	int rv;
-	uint16_t reg = AC_CURRENT_TO_REG(input_current);
-
-	rv = isl9241_write(chgnum, ISL9241_REG_ADAPTER_CUR_LIMIT1, reg);
-	if (rv)
-		return rv;
-
-	return isl9241_write(chgnum, ISL9241_REG_ADAPTER_CUR_LIMIT2, reg);
-}
-
-static enum ec_error_list isl9241_get_input_current_limit(int chgnum,
-							  int *input_current)
-{
-	int rv;
-
-	rv = isl9241_read(chgnum, ISL9241_REG_ADAPTER_CUR_LIMIT1,
-			  input_current);
-	if (rv)
-		return rv;
-
-	*input_current = AC_REG_TO_CURRENT(*input_current);
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl9241_manufacturer_id(int chgnum, int *id)
-{
-	return isl9241_read(chgnum, ISL9241_REG_MANUFACTURER_ID, id);
-}
-
-static enum ec_error_list isl9241_device_id(int chgnum, int *id)
-{
-	return isl9241_read(chgnum, ISL9241_REG_DEVICE_ID, id);
-}
-
-static enum ec_error_list isl9241_get_option(int chgnum, int *option)
-{
-	int rv;
-	uint32_t controls;
-	int reg;
-
-	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
-	if (rv)
-		return rv;
-
-	controls = reg;
-	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL1, &reg);
-	if (rv)
-		return rv;
-
-	controls |= reg << 16;
-	*option = controls;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl9241_set_option(int chgnum, int option)
-{
-	int rv;
-
-	rv = isl9241_write(chgnum, ISL9241_REG_CONTROL0, option & 0xFFFF);
-	if (rv)
-		return rv;
-
-	return isl9241_write(chgnum, ISL9241_REG_CONTROL1,
-			     (option >> 16) & 0xFFFF);
-}
-
-static const struct charger_info *isl9241_get_info(int chgnum)
-{
-	return &isl9241_charger_info;
-}
-
-static enum ec_error_list isl9241_get_status(int chgnum, int *status)
-{
-	int rv;
-	int reg;
-
-	/* Level 2 charger */
-	*status = CHARGER_LEVEL_2;
-
-	/* Charge inhibit status */
-	rv = isl9241_read(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, &reg);
-	if (rv)
-		return rv;
-	if (!reg)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	/* Battery present & AC present status */
-	rv = isl9241_read(chgnum, ISL9241_REG_INFORMATION2, &reg);
-	if (rv)
-		return rv;
-	if (!(reg & ISL9241_INFORMATION2_BATGONE_PIN))
-		*status |= CHARGER_BATTERY_PRESENT;
-	if (reg & ISL9241_INFORMATION2_ACOK_PIN)
-		*status |= CHARGER_AC_PRESENT;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl9241_set_mode(int chgnum, int mode)
-{
-	int rv;
-
-	/*
-	 * See crosbug.com/p/51196. Always disable learn mode unless it was set
-	 * explicitly.
-	 */
-	if (!learn_mode) {
-		rv = isl9241_discharge_on_ac(chgnum, 0);
-		if (rv)
-			return rv;
-	}
-
-	/*
-	 * Charger inhibit
-	 * MinSystemVoltage 0x00h = disables all battery charging
-	 */
-	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE,
-		mode & CHARGE_FLAG_INHIBIT_CHARGE ?
-		0 : battery_get_info()->voltage_min);
-	if (rv)
-		return rv;
-
-	/* POR reset */
-	if (mode & CHARGE_FLAG_POR_RESET) {
-		rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3,
-			ISL9241_CONTROL3_DIGITAL_RESET);
-	}
-
-	return rv;
-}
-
-static enum ec_error_list isl9241_get_current(int chgnum, int *current)
-{
-	int rv;
-
-	rv = isl9241_read(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, current);
-	if (rv)
-		return rv;
-
-	*current = BC_REG_TO_CURRENT(*current);
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl9241_set_current(int chgnum, int current)
-{
-	return isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT,
-				BC_CURRENT_TO_REG(current));
-}
-
-static enum ec_error_list isl9241_get_voltage(int chgnum, int *voltage)
-{
-	return isl9241_read(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage);
-}
-
-static enum ec_error_list isl9241_set_voltage(int chgnum, int voltage)
-{
-	return isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage);
-}
-
-static enum ec_error_list isl9241_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
-{
-	int adc_val = 0;
-	int ctl3_val;
-	int rv;
-
-	/* Get current Control3 value */
-	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL3, &ctl3_val);
-	if (rv)
-		goto error;
-
-	/* Enable ADC */
-	if (!(ctl3_val & ISL9241_CONTROL3_ENABLE_ADC)) {
-		rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3,
-				   ctl3_val | ISL9241_CONTROL3_ENABLE_ADC);
-		if (rv)
-			goto error;
-	}
-
-	/* Read voltage ADC value */
-	rv = isl9241_read(chgnum, ISL9241_REG_VIN_ADC_RESULTS, &adc_val);
-	if (rv)
-		goto error_restore_ctl3;
-
-	/*
-	 * Adjust adc_val
-	 *
-	 * raw adc_val has VIN_ADC in bits [13:6], so shift this down
-	 * this puts adc_val in the range of 0..255, which maps to 0..24.48V
-	 * each step in adc_val is 96mv
-	 */
-	adc_val >>= ISL9241_VIN_ADC_BIT_OFFSET;
-	adc_val *= ISL9241_VIN_ADC_STEP_MV;
-	*voltage = adc_val;
-
-error_restore_ctl3:
-	/* Restore Control3 value */
-	if (!(ctl3_val & ISL9241_CONTROL3_ENABLE_ADC))
-		(void)isl9241_write(chgnum, ISL9241_REG_CONTROL3, ctl3_val);
-
-error:
-	if (rv)
-		CPRINTF("Could not read VBUS ADC! Error: %d\n", rv);
-
-	return rv;
-}
-
-static enum ec_error_list isl9241_post_init(int chgnum)
-{
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable)
-{
-	int rv;
-
-	mutex_lock(&control1_mutex);
-
-	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-			    ISL9241_CONTROL1_LEARN_MODE,
-			    (enable) ? MASK_SET : MASK_CLR);
-	if (!rv)
-		learn_mode = enable;
-
-	mutex_unlock(&control1_mutex);
-	return rv;
-}
-
-int isl9241_set_ac_prochot(int chgnum, int ma)
-{
-	int rv;
-	uint16_t reg;
-
-	/*
-	 * The register reserves bits [6:0] and bits [15:13].
-	 * This routine should ensure these bits are not set
-	 * before writing the register.
-	 */
-	if (ma > AC_REG_TO_CURRENT(ISL9241_AC_PROCHOT_CURRENT_MAX))
-		reg = ISL9241_AC_PROCHOT_CURRENT_MAX;
-	else if (ma < AC_REG_TO_CURRENT(ISL9241_AC_PROCHOT_CURRENT_MIN))
-		reg = ISL9241_AC_PROCHOT_CURRENT_MIN;
-	else
-		reg = AC_CURRENT_TO_REG(ma);
-
-	rv = isl9241_write(chgnum, ISL9241_REG_AC_PROCHOT, reg);
-	if (rv)
-		CPRINTF("set_ac_prochot failed (%d)\n", rv);
-
-	return rv;
-}
-
-int isl9241_set_dc_prochot(int chgnum, int ma)
-{
-	int rv;
-
-	/*
-	 * The register reserves bits [7:0] and bits [15:14].
-	 * This routine should ensure these bits are not set
-	 * before writing the register.
-	 */
-	if (ma > ISL9241_DC_PROCHOT_CURRENT_MAX)
-		ma = ISL9241_DC_PROCHOT_CURRENT_MAX;
-	else if (ma < ISL9241_DC_PROCHOT_CURRENT_MIN)
-		ma = ISL9241_DC_PROCHOT_CURRENT_MIN;
-
-	rv = isl9241_write(chgnum, ISL9241_REG_DC_PROCHOT, ma);
-	if (rv)
-		CPRINTF("set_dc_prochot failed (%d)\n", rv);
-
-	return rv;
-}
-
-/*****************************************************************************/
-/* ISL-9241 initialization */
-static void isl9241_init(int chgnum)
-{
-#ifdef CONFIG_ISL9241_SWITCHING_FREQ
-	int ctl_val;
-#endif
-
-	const struct battery_info *bi = battery_get_info();
-
-	/*
-	 * Set the MaxSystemVoltage to battery maximum,
-	 * 0x00=disables switching charger states
-	 */
-	if (isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
-			  bi->voltage_max))
-		goto init_fail;
-
-	/*
-	 * Set the MinSystemVoltage to battery minimum,
-	 * 0x00=disables all battery charging
-	 */
-	if (isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE,
-			  bi->voltage_min))
-		goto init_fail;
-
-	/*
-	 * Set control2 register to
-	 * [15:13]: Trickle Charging Current (battery pre-charge current)
-	 * [10:9] : Prochot# Debounce time (1000us)
-	 */
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL2,
-			   (ISL9241_CONTROL2_TRICKLE_CHG_CURR(
-				bi->precharge_current) |
-			    ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000),
-			   MASK_SET))
-		goto init_fail;
-
-	/*
-	 * Set control3 register to
-	 * [14]: ACLIM Reload (Do not reload)
-	 */
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL3,
-			   ISL9241_CONTROL3_ACLIM_RELOAD,
-			   MASK_SET))
-		goto init_fail;
-
-	/*
-	 * Set control4 register to
-	 * [13]: Slew rate control enable (sets VSYS ramp to 8mV/us)
-	 */
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL4,
-			   ISL9241_CONTROL4_SLEW_RATE_CTRL,
-			   MASK_SET))
-		goto init_fail;
-
-#ifndef CONFIG_CHARGE_RAMP_HW
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-			   ISL9241_CONTROL0_INPUT_VTG_REGULATION,
-			   MASK_SET))
-		goto init_fail;
-#endif
-
-#ifdef CONFIG_ISL9241_SWITCHING_FREQ
-	if (isl9241_read(chgnum, ISL9241_REG_CONTROL1, &ctl_val))
-		goto init_fail;
-	ctl_val &= ~ISL9241_CONTROL1_SWITCHING_FREQ_MASK;
-	ctl_val |= ((CONFIG_ISL9241_SWITCHING_FREQ << 7) &
-		     ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
-	if (isl9241_write(chgnum, ISL9241_REG_CONTROL1, ctl_val))
-		goto init_fail;
-#endif
-
-	/*
-	 * No need to proceed with the rest of init if we sysjump'd to this
-	 * image as the input current limit has already been set.
-	 */
-	if (system_jumped_late())
-		return;
-
-	/* Initialize the input current limit to the board's default. */
-	if (isl9241_set_input_current_limit(chgnum,
-					    CONFIG_CHARGER_INPUT_CURRENT))
-		goto init_fail;
-
-	return;
-
-init_fail:
-	CPRINTF("ISL9241_init failed!\n");
-}
-
-/*****************************************************************************/
-/* Hardware current ramping */
-
-#ifdef CONFIG_CHARGE_RAMP_HW
-static enum ec_error_list isl9241_set_hw_ramp(int chgnum, int enable)
-{
-	/* HW ramp is controlled by input voltage regulation reference bits */
-	return isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-			      ISL9241_CONTROL0_INPUT_VTG_REGULATION,
-			      (enable) ? MASK_CLR : MASK_SET);
-}
-
-static int isl9241_ramp_is_stable(int chgnum)
-{
-	/*
-	 * Since ISL cannot read the current limit that the ramp has settled
-	 * on, then we can never consider the ramp stable, because we never
-	 * know what the stable limit is.
-	 */
-	return 0;
-}
-
-static int isl9241_ramp_is_detected(int chgnum)
-{
-	return 1;
-}
-
-static int isl9241_ramp_get_current_limit(int chgnum)
-{
-	int reg;
-
-	if (isl9241_read(chgnum, ISL9241_REG_IADP_ADC_RESULTS, &reg))
-		return 0;
-
-	/* LSB value of register = 22.2mA */
-	return (reg * 222) / 10;
-}
-#endif /* CONFIG_CHARGE_RAMP_HW */
-
-/*
- * When fully charged in a low-power state, the ISL9241 may get stuck
- * in CCM. Toggle learning mode for 50 ms to enter DCM and save power.
- * This is a workaround provided by Renesas. See b/183771327.
- * Note: the charger_get_state() returns the last known charge value,
- * so need to check the battery is not disconnected when the system
- * comes from the battery cutoff.
- */
-static void isl9241_restart_charge_voltage_when_full(void)
-{
-	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-	    && charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL
-	    && battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
-		charger_discharge_on_ac(1);
-		msleep(50);
-		charger_discharge_on_ac(0);
-	}
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     isl9241_restart_charge_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
-	     isl9241_restart_charge_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     isl9241_restart_charge_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-#ifdef CONFIG_CMD_CHARGER_DUMP
-static void dump_reg_range(int chgnum, int low, int high)
-{
-	int reg;
-	int regval;
-	int rv;
-
-	for (reg = low; reg <= high; reg++) {
-		CPRINTF("[%Xh] = ", reg);
-		rv = isl9241_read(chgnum, reg, &regval);
-		if (!rv)
-			CPRINTF("0x%04x\n", regval);
-		else
-			CPRINTF("ERR (%d)\n", rv);
-		cflush();
-	}
-}
-
-static int command_isl9241_dump(int argc, char **argv)
-{
-	char *e;
-	int chgnum = 0;
-
-	if (argc >= 2) {
-		chgnum = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	dump_reg_range(chgnum, 0x14, 0x15);
-	dump_reg_range(chgnum, 0x38, 0x40);
-	dump_reg_range(chgnum, 0x43, 0x43);
-	dump_reg_range(chgnum, 0x47, 0x4F);
-	dump_reg_range(chgnum, 0x80, 0x87);
-	dump_reg_range(chgnum, 0x90, 0x91);
-	dump_reg_range(chgnum, 0xFE, 0xFF);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(charger_dump, command_isl9241_dump,
-			"charger_dump <chgnum>",
-			"Dumps ISL9241 registers");
-#endif /* CONFIG_CMD_CHARGER_DUMP */
-
-const struct charger_drv isl9241_drv = {
-	.init = &isl9241_init,
-	.post_init = &isl9241_post_init,
-	.get_info = &isl9241_get_info,
-	.get_status = &isl9241_get_status,
-	.set_mode = &isl9241_set_mode,
-	.get_current = &isl9241_get_current,
-	.set_current = &isl9241_set_current,
-	.get_voltage = &isl9241_get_voltage,
-	.set_voltage = &isl9241_set_voltage,
-	.discharge_on_ac = &isl9241_discharge_on_ac,
-	.get_vbus_voltage = &isl9241_get_vbus_voltage,
-	.set_input_current_limit = &isl9241_set_input_current_limit,
-	.get_input_current_limit = &isl9241_get_input_current_limit,
-	.manufacturer_id = &isl9241_manufacturer_id,
-	.device_id = &isl9241_device_id,
-	.get_option = &isl9241_get_option,
-	.set_option = &isl9241_set_option,
-#ifdef CONFIG_CHARGE_RAMP_HW
-	.set_hw_ramp = &isl9241_set_hw_ramp,
-	.ramp_is_stable = &isl9241_ramp_is_stable,
-	.ramp_is_detected = &isl9241_ramp_is_detected,
-	.ramp_get_current_limit = &isl9241_ramp_get_current_limit,
-#endif
-};
diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h
deleted file mode 100644
index 0e5acd09df..0000000000
--- a/driver/charger/isl9241.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Renesas (Intersil) ISL-9241 battery charger driver header.
- */
-
-#ifndef __CROS_EC_ISL9241_H
-#define __CROS_EC_ISL9241_H
-
-#include "driver/charger/isl9241_public.h"
-
-#define CHARGER_NAME	"ISL9241"
-#define CHARGE_V_MAX	18304
-#define CHARGE_V_MIN	64
-#define CHARGE_V_STEP	8
-#define CHARGE_I_MAX	6140
-#define CHARGE_I_MIN	4
-#define CHARGE_I_STEP	4
-#define INPUT_I_MAX	6140
-#define INPUT_I_MIN	4
-#define	INPUT_I_STEP	4
-
-/* Registers */
-
-/*
- * ChargeCurrentLimit [12:2] 11-bit (0x0000h = disables fast charging,
- * trickle charging is allowed)
- */
-#define ISL9241_REG_CHG_CURRENT_LIMIT	0x14
-
-/* MaxSystemVoltage [14:3] 12-bit, (0x0000h = disables switching) */
-#define ISL9241_REG_MAX_SYSTEM_VOLTAGE	0x15
-
-#define ISL9241_REG_CONTROL7		0x38
-
-/* Configures various charger options */
-#define ISL9241_REG_CONTROL0		0x39
-/* 2: Input Voltage Regulation (0 = Enable (default), 1 = Disable) */
-#define ISL9241_CONTROL0_INPUT_VTG_REGULATION	BIT(2)
-
-
-#define ISL9241_REG_INFORMATION1	0x3A
-#define ISL9241_REG_ADAPTER_CUR_LIMIT2	0x3B
-
-/* Configures various charger options */
-#define ISL9241_REG_CONTROL1		0x3C
-#define ISL9241_CONTROL1_PSYS		BIT(3)
-#define ISL9241_CONTROL1_LEARN_MODE	BIT(12)
-/*
- * 9:7 - Switching Frequency
- */
-#define ISL9241_CONTROL1_SWITCHING_FREQ_MASK 0x380
-#define ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ 0
-#define ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ 1
-#define ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ 2
-#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ  3
-#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ  4
-#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ  5
-#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ  6
-#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ  7
-
-/* Configures various charger options */
-#define ISL9241_REG_CONTROL2		0x3D
-/*
- * 15:13 - Trickle Charging Current
- *         <000> 32mA (do not use)
- *         <001> 64mA
- *         <010> 96mA
- *         <011> 128mA (default)
- *         <100> 160mA
- *         <101> 192mA
- *         <110> 224mA
- *         <111> 256mA
- */
-#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr)	((((curr) >> 5) - 1) << 13)
-/* 12 - Two-Level Adapter Current Limit */
-#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR	BIT(12)
-/* 10:9 PROCHOT# debounce time in uS */
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK  GENMASK(10, 9)
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500	(2 << 9)
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000	(3 << 9)
-
-/* MinSystemVoltage [13:6] 8-bit (0x0000h = disables all battery charging) */
-#define ISL9241_REG_MIN_SYSTEM_VOLTAGE	0x3E
-
-#define ISL9241_REG_ADAPTER_CUR_LIMIT1	0x3F
-#define ISL9241_REG_ACOK_REFERENCE	0x40
-#define ISL9241_REG_CONTROL6		0x43
-#define ISL9241_REG_AC_PROCHOT		0x47
-#define ISL9241_REG_DC_PROCHOT		0x48
-#define ISL9241_REG_OTG_VOLTAGE		0x49
-#define ISL9241_REG_OTG_CURRENT		0x4A
-
-/* VIN Voltage (ADP Min Voltage) (default 4.096V) */
-#define ISL9241_REG_VIN_VOLTAGE		0x4B
-
-/* Configures various charger options */
-#define ISL9241_REG_CONTROL3		0x4C
-/* 14: ACLIM Reload (0 - reload, 1 - Do not reload */
-#define ISL9241_CONTROL3_ACLIM_RELOAD	BIT(14)
-/* 2: Digital Reset (0 - Idle, 1 - Reset */
-#define ISL9241_CONTROL3_DIGITAL_RESET	BIT(2)
-/* 0: Enable ADC (0 - Active when charging, 1 - Active always) */
-#define ISL9241_CONTROL3_ENABLE_ADC	BIT(0)
-
-/* Indicates various charger status */
-#define ISL9241_REG_INFORMATION2	0x4D
-/* 12: BATGONE pin status (0 = Battery is present, 1 = No battery) */
-#define ISL9241_INFORMATION2_BATGONE_PIN	BIT(12)
-/* 14: ACOK pin status (0 = No adapter, 1 = Adapter is present) */
-#define ISL9241_INFORMATION2_ACOK_PIN		BIT(14)
-
-#define ISL9241_REG_CONTROL4		0x4E
-/* 11: Rsense (Rs1:Rs2) ratio for PSYS (0 - 2:1, 1 - 1:1) */
-#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO  BIT(11)
-/* 13: Enable VSYS slew rate control (0 - disable, 1 - enable) */
-#define ISL9241_CONTROL4_SLEW_RATE_CTRL     BIT(13)
-
-#define ISL9241_REG_CONTROL5		0x4F
-#define ISL9241_REG_NTC_ADC_RESULTS	0x80
-#define ISL9241_REG_VBAT_ADC_RESULTS	0x81
-#define ISL9241_REG_TJ_ADC_RESULTS	0x82
-
-/* ADC result for adapter current measurements, LSB = 22.2mA */
-#define ISL9241_REG_IADP_ADC_RESULTS	0x83
-
-#define ISL9241_REG_DC_ADC_RESULTS	0x84
-#define ISL9241_REG_CC_ADC_RESULTS	0x85
-#define ISL9241_REG_VSYS_ADC_RESULTS	0x86
-#define ISL9241_REG_VIN_ADC_RESULTS	0x87
-#define ISL9241_REG_INFORMATION3	0x90
-#define ISL9241_REG_INFORMATION4	0x91
-#define ISL9241_REG_MANUFACTURER_ID	0xFE
-#define ISL9241_REG_DEVICE_ID		0xFF
-
-#define ISL9241_VIN_ADC_BIT_OFFSET	6
-#define ISL9241_VIN_ADC_STEP_MV		96
-
-#endif /* __CROS_EC_ISL9241_H */
diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c
deleted file mode 100644
index a4cfa5d2eb..0000000000
--- a/driver/charger/rt946x.c
+++ /dev/null
@@ -1,1927 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Richtek rt946x, Mediatek mt6370 battery charger driver.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "charger.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "config.h"
-#include "console.h"
-#include "extpower.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "printf.h"
-#include "driver/wpc/p9221.h"
-#include "rt946x.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) \
-	cprints(CC_CHARGER, "%s " format, "RT946X", ## args)
-
-/* Charger parameters */
-#define CHARGER_NAME    RT946X_CHARGER_NAME
-#define CHARGE_V_MAX    4710
-#define CHARGE_V_MIN    3900
-#define CHARGE_V_STEP   10
-#define CHARGE_I_MAX    5000
-#define CHARGE_I_MIN    100
-#define CHARGE_I_OFF    0
-#define CHARGE_I_STEP   100
-#define INPUT_I_MAX     3250
-#define INPUT_I_MIN     100
-#define INPUT_I_STEP    50
-
-/* Charger parameters */
-static const struct charger_info rt946x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
-	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
-	.input_current_step = INPUT_I_STEP,
-};
-
-static const struct rt946x_init_setting default_init_setting = {
-	.eoc_current = 400,
-	.mivr = 4000,
-	.ircmp_vclamp = 32,
-	.ircmp_res = 25,
-	.boost_voltage = 5050,
-	.boost_current = 1500,
-};
-
-__attribute__((weak))
-const struct rt946x_init_setting *board_rt946x_init_setting(void)
-{
-	return &default_init_setting;
-}
-
-enum rt946x_ilmtsel {
-	RT946X_ILMTSEL_PSEL_OTG,
-	RT946X_ILMTSEL_AICR = 2,
-	RT946X_ILMTSEL_LOWER_LEVEL, /* lower of above two */
-};
-
-enum rt946x_chg_stat {
-	RT946X_CHGSTAT_READY = 0,
-	RT946X_CHGSTAT_IN_PROGRESS,
-	RT946X_CHGSTAT_DONE,
-	RT946X_CHGSTAT_FAULT,
-};
-
-static struct mutex adc_access_lock;
-
-#ifdef CONFIG_CHARGER_MT6370
-/*
- * Unit for each ADC parameter
- * 0 stands for reserved
- */
-static const int mt6370_adc_unit[MT6370_ADC_MAX] = {
-	0,
-	MT6370_ADC_UNIT_VBUS_DIV5,
-	MT6370_ADC_UNIT_VBUS_DIV2,
-	MT6370_ADC_UNIT_VSYS,
-	MT6370_ADC_UNIT_VBAT,
-	0,
-	MT6370_ADC_UNIT_TS_BAT,
-	0,
-	MT6370_ADC_UNIT_IBUS,
-	MT6370_ADC_UNIT_IBAT,
-	0,
-	MT6370_ADC_UNIT_CHG_VDDP,
-	MT6370_ADC_UNIT_TEMP_JC,
-};
-
-static const int mt6370_adc_offset[MT6370_ADC_MAX] = {
-	0,
-	MT6370_ADC_OFFSET_VBUS_DIV5,
-	MT6370_ADC_OFFSET_VBUS_DIV2,
-	MT6370_ADC_OFFSET_VSYS,
-	MT6370_ADC_OFFSET_VBAT,
-	0,
-	MT6370_ADC_OFFSET_TS_BAT,
-	0,
-	MT6370_ADC_OFFSET_IBUS,
-	MT6370_ADC_OFFSET_IBAT,
-	0,
-	MT6370_ADC_OFFSET_CHG_VDDP,
-	MT6370_ADC_OFFSET_TEMP_JC,
-};
-
-static int hidden_mode_cnt = 0;
-static struct mutex hidden_mode_lock;
-static const unsigned char mt6370_reg_en_hidden_mode[] = {
-	MT6370_REG_HIDDENPASCODE1,
-	MT6370_REG_HIDDENPASCODE2,
-	MT6370_REG_HIDDENPASCODE3,
-	MT6370_REG_HIDDENPASCODE4,
-};
-
-static const unsigned char mt6370_val_en_hidden_mode[] = {
-	0x96, 0x69, 0xC3, 0x3C,
-};
-
-static const unsigned char mt6370_val_en_test_mode[] = {
-	0x69, 0x96, 0x63, 0x70,
-};
-#endif /* CONFIG_CHARGER_MT6370 */
-
-#if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-enum rt946x_irq {
-	RT946X_IRQ_CHGSTATC = 0,
-	RT946X_IRQ_CHGFAULT,
-	RT946X_IRQ_TSSTATC,
-	RT946X_IRQ_CHGIRQ1,
-	RT946X_IRQ_CHGIRQ2,
-	RT946X_IRQ_CHGIRQ3,
-#ifdef CONFIG_CHARGER_RT9467
-	RT946X_IRQ_DPDMIRQ,
-#endif
-	RT946X_IRQ_COUNT,
-};
-
-static uint8_t rt946x_irqmask[RT946X_IRQ_COUNT] = {
-	0xF0, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
-#ifdef CONFIG_CHARGER_RT9467
-	0xFC,
-#endif
-};
-
-static const uint8_t rt946x_irq_maskall[RT946X_IRQ_COUNT] = {
-	0xF0, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
-#ifdef CONFIG_CHARGER_RT9467
-	0xFF,
-#endif
-};
-#elif defined(CONFIG_CHARGER_MT6370)
-enum rt946x_irq {
-	MT6370_IRQ_CHGSTAT1 = 0,
-	MT6370_IRQ_CHGSTAT2,
-	MT6370_IRQ_CHGSTAT3,
-	MT6370_IRQ_CHGSTAT4,
-	MT6370_IRQ_CHGSTAT5,
-	MT6370_IRQ_CHGSTAT6,
-	MT6370_IRQ_DPDMSTAT,
-	MT6370_IRQ_DICHGSTAT,
-	MT6370_IRQ_OVPCTRLSTAT,
-	MT6370_IRQ_FLEDSTAT1,
-	MT6370_IRQ_FLEDSTAT2,
-	MT6370_IRQ_BASESTAT,
-	MT6370_IRQ_LDOSTAT,
-	MT6370_IRQ_RGBSTAT,
-	MT6370_IRQ_BLSTAT,
-	MT6370_IRQ_DBSTAT,
-	RT946X_IRQ_COUNT,
-};
-
-static uint8_t rt946x_irqmask[RT946X_IRQ_COUNT] = {
-	0xBF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFC, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
-};
-
-static const uint8_t rt946x_irq_maskall[RT946X_IRQ_COUNT] = {
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
-};
-#endif
-
-static enum ec_error_list rt946x_set_current(int chgnum, int current);
-static enum ec_error_list rt946x_get_current(int chgnum, int *current);
-static enum ec_error_list rt946x_set_voltage(int chgnum, int voltage);
-static enum ec_error_list rt946x_enable_otg_power(int chgnum, int enabled);
-static const struct charger_info *rt946x_get_info(int chgnum);
-
-/* Must be in ascending order */
-static const uint16_t rt946x_boost_current[] = {
-	500, 700, 1100, 1300, 1800, 2100, 2400,
-};
-
-static enum ec_error_list rt946x_read8(int chgnum, int reg, int *val)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags, reg, val);
-}
-
-static enum ec_error_list rt946x_write8(int chgnum, int reg, int val)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags, reg, val);
-}
-
-static enum ec_error_list rt946x_block_write(int chgnum, int reg,
-					     const uint8_t *val, int len)
-{
-	return i2c_write_block(chg_chips[chgnum].i2c_port,
-			       chg_chips[chgnum].i2c_addr_flags,
-			       reg, val, len);
-}
-
-static int rt946x_update_bits(int chgnum, int reg, int mask, int val)
-{
-	int rv;
-	int reg_val = 0;
-
-	rv = rt946x_read8(chgnum, reg, &reg_val);
-	if (rv)
-		return rv;
-	reg_val &= ~mask;
-	reg_val |= (mask & val);
-	rv = rt946x_write8(chgnum, reg, reg_val);
-	return rv;
-}
-
-static inline int rt946x_set_bit(int chgnum, int reg, int mask)
-{
-	return rt946x_update_bits(chgnum, reg, mask, mask);
-}
-
-static inline int rt946x_clr_bit(int chgnum, int reg, int mask)
-{
-	return rt946x_update_bits(chgnum, reg, mask, 0x00);
-}
-
-static inline int mt6370_pmu_reg_test_bit(int chgnum, int cmd, int shift,
-					  int *is_one)
-{
-	int rv, data;
-
-	rv = rt946x_read8(chgnum, cmd, &data);
-	if (rv) {
-		*is_one = 0;
-		return rv;
-	}
-
-	*is_one = !!(data & BIT(shift));
-	return rv;
-}
-
-static inline uint8_t rt946x_closest_reg(uint16_t min, uint16_t max,
-					 uint16_t step, uint16_t target)
-{
-	if (target < min)
-		return 0;
-	if (target >= max)
-		return ((max - min) / step);
-	return (target - min) / step;
-}
-
-static int rt946x_get_ieoc(int chgnum, uint32_t *ieoc)
-{
-	int ret, reg_ieoc;
-
-	ret = rt946x_read8(chgnum, RT946X_REG_CHGCTRL9, &reg_ieoc);
-	if (ret)
-		return ret;
-
-	*ieoc = RT946X_IEOC_MIN +
-		RT946X_IEOC_STEP *
-			((reg_ieoc & RT946X_MASK_IEOC) >> RT946X_SHIFT_IEOC);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CHARGER_MT6370
-static int mt6370_enable_hidden_mode(int chgnum, int en)
-{
-	int rv = 0;
-
-	if (in_interrupt_context()) {
-		CPRINTS("Err: use hidden mode in IRQ");
-		return EC_ERROR_INVAL;
-        }
-
-	mutex_lock(&hidden_mode_lock);
-	if (en) {
-		if (hidden_mode_cnt == 0) {
-			rv = rt946x_block_write(chgnum,
-				mt6370_reg_en_hidden_mode[0],
-				mt6370_val_en_hidden_mode,
-				ARRAY_SIZE(mt6370_val_en_hidden_mode));
-			if (rv)
-				goto out;
-		}
-		hidden_mode_cnt++;
-	} else {
-		if (hidden_mode_cnt == 1) /* last one */
-			rv = rt946x_write8(chgnum, mt6370_reg_en_hidden_mode[0],
-					   0x00);
-		hidden_mode_cnt--;
-		if (rv)
-			goto out;
-	}
-
-out:
-	mutex_unlock(&hidden_mode_lock);
-	return rv;
-}
-
-/*
- * Vsys short protection:
- * When the system is charging at 500mA, and if Isys > 3600mA, the
- * power path will be turned off and cause the system shutdown.
- * When Ichg < 400mA, then power path is roughly 1/8 of the original.
- * When Isys > 3600mA, this cause the voltage between Vbat and Vsys too
- * huge (Vbat - Vsys > Vsys short portection) and turns off the power
- * path.
- * To workaround this,
- * 1. disable Vsys short protection when Ichg is set below 900mA
- * 2. forbids Ichg <= 400mA (this is done natually on mt6370, since mt6370's
- *    minimum current is 512)
- */
-static int mt6370_ichg_workaround(int chgnum, int new_ichg)
-{
-	int rv = EC_SUCCESS;
-	int curr_ichg;
-
-	/*
-	 * TODO(b:144532905): The workaround should be applied to rt9466 as
-	 * well. But this needs rt9466's hidden register datasheet. Enable
-	 * this if we need it in the future.
-	 */
-	if (!IS_ENABLED(CONFIG_CHARGER_MT6370))
-		return EC_SUCCESS;
-
-	rv = rt946x_get_current(chgnum, &curr_ichg);
-	if (rv)
-		return rv;
-
-	mt6370_enable_hidden_mode(chgnum, 1);
-
-	/* disable Vsys protect if if the new ichg is below 900mA */
-	if (curr_ichg >= 900 && new_ichg < 900)
-		rv = rt946x_update_bits(chgnum, RT946X_REG_CHGHIDDENCTRL7,
-					RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT,
-					0);
-	/* enable Vsys protect if the new ichg is above 900mA */
-	else if (new_ichg >= 900 && curr_ichg < 900)
-		rv = rt946x_update_bits(chgnum, RT946X_REG_CHGHIDDENCTRL7,
-					RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT,
-					RT946X_ENABLE_VSYS_PROTECT);
-
-	mt6370_enable_hidden_mode(chgnum, 0);
-	return rv;
-}
-#endif /* CONFIG_CHARGER_MT6370 */
-
-static inline int rt946x_enable_wdt(int chgnum, int en)
-{
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN);
-}
-
-/* Enable high-impedance mode */
-static inline int rt946x_enable_hz(int chgnum, int en)
-{
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN);
-}
-
-int rt946x_por_reset(void)
-{
-	int rv, val;
-
-#ifdef CONFIG_CHARGER_MT6370
-	/* Soft reset. It takes only 1ns for resetting. b/116682788 */
-	val = RT946X_MASK_SOFT_RST;
-	/*
-	 * MT6370 has to set passcodes before resetting all the registers and
-	 * logics.
-	 */
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_REG_RSTPASCODE1,
-			   MT6370_MASK_RSTPASCODE1);
-	rv |= rt946x_write8(CHARGER_SOLO, MT6370_REG_RSTPASCODE2,
-			    MT6370_MASK_RSTPASCODE2);
-#else
-	/* Hard reset, may take several milliseconds. */
-	val = RT946X_MASK_RST;
-	rv = rt946x_enable_hz(CHARGER_SOLO, 0);
-#endif
-	if (rv)
-		return rv;
-
-	return rt946x_set_bit(CHARGER_SOLO, RT946X_REG_CORECTRL_RST, val);
-}
-
-static int rt946x_reset_to_zero(int chgnum)
-{
-	int rv;
-
-	rv = rt946x_set_current(chgnum, 0);
-	if (rv)
-		return rv;
-
-	rv = rt946x_set_voltage(chgnum, 0);
-	if (rv)
-		return rv;
-
-	return rt946x_enable_hz(chgnum, 1);
-}
-
-static int rt946x_enable_bc12_detection(int chgnum, int en)
-{
-#if defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370)
-	int rv;
-
-	if (en) {
-#ifdef CONFIG_CHARGER_MT6370_BC12_GPIO
-		gpio_set_level(GPIO_BC12_DET_EN, 1);
-#endif /* CONFIG_CHARGER_MT6370_BC12_GPIO */
-		return rt946x_set_bit(chgnum, RT946X_REG_DPDM1,
-				      RT946X_MASK_USBCHGEN);
-	}
-
-	rv = rt946x_clr_bit(chgnum, RT946X_REG_DPDM1, RT946X_MASK_USBCHGEN);
-#ifdef CONFIG_CHARGER_MT6370_BC12_GPIO
-	gpio_set_level(GPIO_BC12_DET_EN, 0);
-#endif /* CONFIG_CHARGER_MT6370_BC12_GPIO */
-	return rv;
-#endif
-	return 0;
-}
-
-static int rt946x_set_ieoc(int chgnum, unsigned int ieoc)
-{
-	uint8_t reg_ieoc;
-
-	reg_ieoc = rt946x_closest_reg(RT946X_IEOC_MIN, RT946X_IEOC_MAX,
-				      RT946X_IEOC_STEP, ieoc);
-
-	CPRINTS("ieoc=%d", ieoc);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL9, RT946X_MASK_IEOC,
-				reg_ieoc << RT946X_SHIFT_IEOC);
-}
-
-static int rt946x_set_mivr(int chgnum, unsigned int mivr)
-{
-	uint8_t reg_mivr = 0;
-
-	reg_mivr = rt946x_closest_reg(RT946X_MIVR_MIN, RT946X_MIVR_MAX,
-		RT946X_MIVR_STEP, mivr);
-
-	CPRINTS("mivr=%d", mivr);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL6, RT946X_MASK_MIVR,
-		reg_mivr << RT946X_SHIFT_MIVR);
-}
-
-static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage)
-{
-	uint8_t reg_voltage = 0;
-
-	reg_voltage = rt946x_closest_reg(RT946X_BOOST_VOLTAGE_MIN,
-		RT946X_BOOST_VOLTAGE_MAX, RT946X_BOOST_VOLTAGE_STEP, voltage);
-
-	CPRINTS("voltage=%d", voltage);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL5,
-		RT946X_MASK_BOOST_VOLTAGE,
-		reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE);
-}
-
-static int rt946x_set_boost_current(int chgnum, unsigned int current)
-{
-	int i;
-
-	/*
-	 * Find the smallest output current threshold which can support
-	 * our requested output current. Use the greatest achievable
-	 * boost current (2.4A) if requested current is too large.
-	 */
-	for (i = 0; i < ARRAY_SIZE(rt946x_boost_current) - 1; i++) {
-		if (current < rt946x_boost_current[i])
-			break;
-	}
-
-	CPRINTS("current=%d", current);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL10,
-		RT946X_MASK_BOOST_CURRENT,
-		i << RT946X_SHIFT_BOOST_CURRENT);
-}
-
-static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp)
-{
-	uint8_t reg_vclamp = 0;
-
-	reg_vclamp = rt946x_closest_reg(RT946X_IRCMP_VCLAMP_MIN,
-		RT946X_IRCMP_VCLAMP_MAX, RT946X_IRCMP_VCLAMP_STEP, vclamp);
-
-	CPRINTS("vclamp=%d", vclamp);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL18,
-		RT946X_MASK_IRCMP_VCLAMP,
-		reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP);
-}
-
-static int rt946x_set_ircmp_res(int chgnum, unsigned int res)
-{
-	uint8_t reg_res = 0;
-
-	reg_res = rt946x_closest_reg(RT946X_IRCMP_RES_MIN, RT946X_IRCMP_RES_MAX,
-		RT946X_IRCMP_RES_STEP, res);
-
-	CPRINTS("res=%d", res);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL18,
-				  RT946X_MASK_IRCMP_RES,
-				  reg_res << RT946X_SHIFT_IRCMP_RES);
-}
-
-static int rt946x_set_vprec(int chgnum, unsigned int vprec)
-{
-	uint8_t reg_vprec = 0;
-
-	reg_vprec = rt946x_closest_reg(RT946X_VPREC_MIN, RT946X_VPREC_MAX,
-		RT946X_VPREC_STEP, vprec);
-
-	CPRINTS("vprec=%d", vprec);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL8,
-				  RT946X_MASK_VPREC,
-				  reg_vprec << RT946X_SHIFT_VPREC);
-}
-
-static int rt946x_set_iprec(int chgnum, unsigned int iprec)
-{
-	uint8_t reg_iprec = 0;
-
-	reg_iprec = rt946x_closest_reg(RT946X_IPREC_MIN, RT946X_IPREC_MAX,
-		RT946X_IPREC_STEP, iprec);
-
-	CPRINTS("iprec=%d", iprec);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL8,
-				  RT946X_MASK_IPREC,
-				  reg_iprec << RT946X_SHIFT_IPREC);
-}
-
-static int rt946x_init_irq(int chgnum)
-{
-	int rv = 0;
-	int unused;
-	int i;
-
-	/* Mask all interrupts */
-	rv = rt946x_block_write(chgnum, RT946X_REG_CHGSTATCCTRL,
-				rt946x_irq_maskall, RT946X_IRQ_COUNT);
-	if (rv)
-		return rv;
-
-	/* Clear all interrupt flags */
-	for (i = 0; i < RT946X_IRQ_COUNT; i++) {
-		rv = rt946x_read8(chgnum, RT946X_REG_CHGSTATC + i, &unused);
-		if (rv)
-			return rv;
-	}
-
-	/* Init interrupt */
-	return rt946x_block_write(chgnum, RT946X_REG_CHGSTATCCTRL,
-				  rt946x_irqmask, ARRAY_SIZE(rt946x_irqmask));
-}
-
-static int rt946x_init_setting(int chgnum)
-{
-	int rv = 0;
-	const struct battery_info *batt_info = battery_get_info();
-	const struct rt946x_init_setting *setting = board_rt946x_init_setting();
-
-#ifdef CONFIG_BATTERY_SMART
-	/* Disable EOC */
-	rv = rt946x_enable_charge_eoc(0);
-	if (rv)
-		return rv;
-#endif
-
-#ifdef CONFIG_CHARGER_OTG
-	/*  Disable boost-mode output voltage */
-	rv = rt946x_enable_otg_power(chgnum, 0);
-	if (rv)
-		return rv;
-#endif
-	/* Disable BC 1.2 detection by default. It will be enabled on demand */
-	rv = rt946x_enable_bc12_detection(chgnum, 0);
-	if (rv)
-		return rv;
-	/* Disable WDT */
-	rv = rt946x_enable_wdt(chgnum, 0);
-	if (rv)
-		return rv;
-	/* Disable battery thermal protection */
-	rv = rt946x_clr_bit(chgnum, RT946X_REG_CHGCTRL16, RT946X_MASK_JEITA_EN);
-	if (rv)
-		return rv;
-	/* Disable charge timer */
-	rv = rt946x_clr_bit(chgnum, RT946X_REG_CHGCTRL12, RT946X_MASK_TMR_EN);
-	if (rv)
-		return rv;
-	rv = rt946x_set_mivr(chgnum, setting->mivr);
-	if (rv)
-		return rv;
-	rv = rt946x_set_ieoc(chgnum, setting->eoc_current);
-	if (rv)
-		return rv;
-	rv = rt946x_set_boost_voltage(chgnum,
-		setting->boost_voltage);
-	if (rv)
-		return rv;
-	rv = rt946x_set_boost_current(chgnum,
-		setting->boost_current);
-	if (rv)
-		return rv;
-	rv = rt946x_set_ircmp_vclamp(chgnum, setting->ircmp_vclamp);
-	if (rv)
-		return rv;
-	rv = rt946x_set_ircmp_res(chgnum, setting->ircmp_res);
-	if (rv)
-		return rv;
-	rv = rt946x_set_vprec(chgnum, batt_info->precharge_voltage ?
-			batt_info->precharge_voltage : batt_info->voltage_min);
-	if (rv)
-		return rv;
-	rv = rt946x_set_iprec(chgnum, batt_info->precharge_current);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_CHARGER_MT6370_BACKLIGHT
-	rt946x_write8(chgnum, MT6370_BACKLIGHT_BLEN,
-		      MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN |
-			MT6370_MASK_BLED_1CH_EN | MT6370_MASK_BLED_2CH_EN |
-			MT6370_MASK_BLED_3CH_EN | MT6370_MASK_BLED_4CH_EN |
-			MT6370_BLED_CODE_LINEAR);
-	rt946x_update_bits(chgnum, MT6370_BACKLIGHT_BLPWM,
-			   MT6370_MASK_BLPWM_BLED_PWM,
-			   BIT(MT6370_SHIFT_BLPWM_BLED_PWM));
-#endif
-
-	return rt946x_init_irq(chgnum);
-}
-
-#ifdef CONFIG_CHARGER_OTG
-static enum ec_error_list rt946x_enable_otg_power(int chgnum, int enabled)
-{
-	return (enabled ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE);
-}
-
-static int rt946x_is_sourcing_otg_power(int chgnum, int port)
-{
-	int val;
-
-	if (rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGCTRL1, &val))
-		return 0;
-
-	return !!(val & RT946X_MASK_OPA_MODE);
-}
-#endif
-
-static enum ec_error_list rt946x_set_input_current_limit(int chgnum,
-							 int input_current)
-{
-	uint8_t reg_iin = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
-
-	reg_iin = rt946x_closest_reg(info->input_current_min,
-		info->input_current_max, info->input_current_step,
-		input_current);
-
-	CPRINTS("iin=%d", input_current);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_AICR,
-		reg_iin << RT946X_SHIFT_AICR);
-}
-
-static enum ec_error_list rt946x_get_input_current_limit(int chgnum,
-							 int *input_current)
-{
-	int rv;
-	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL3, &val);
-	if (rv)
-		return rv;
-
-	val = (val & RT946X_MASK_AICR) >> RT946X_SHIFT_AICR;
-	*input_current = val * info->input_current_step
-		+ info->input_current_min;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_manufacturer_id(int chgnum, int *id)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static enum ec_error_list rt946x_device_id(int chgnum, int *id)
-{
-	int rv;
-
-	rv = rt946x_read8(chgnum, RT946X_REG_DEVICEID, id);
-	if (rv == EC_SUCCESS)
-		*id &= RT946X_MASK_VENDOR_ID;
-	return rv;
-}
-
-static enum ec_error_list rt946x_get_option(int chgnum, int *option)
-{
-	/* Ignored: does not exist */
-	*option = 0;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_set_option(int chgnum, int option)
-{
-	/* Ignored: does not exist */
-	return EC_SUCCESS;
-}
-
-static const struct charger_info *rt946x_get_info(int chgnum)
-{
-	return &rt946x_charger_info;
-}
-
-static enum ec_error_list rt946x_get_status(int chgnum, int *status)
-{
-	int rv;
-	int val = 0;
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL2, &val);
-	if (rv)
-		return rv;
-	val = (val & RT946X_MASK_CHG_EN) >> RT946X_SHIFT_CHG_EN;
-	if (!val)
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGFAULT, &val);
-	if (rv)
-		return rv;
-	if (val & RT946X_MASK_CHG_VBATOV)
-		*status |= CHARGER_VOLTAGE_OR;
-
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGNTC, &val);
-	if (rv)
-		return rv;
-	val = (val & RT946X_MASK_BATNTC_FAULT) >> RT946X_SHIFT_BATNTC_FAULT;
-
-	switch (val) {
-	case RT946X_BATTEMP_WARM:
-		*status |= CHARGER_RES_HOT;
-		break;
-	case RT946X_BATTEMP_COOL:
-		*status |= CHARGER_RES_COLD;
-		break;
-	case RT946X_BATTEMP_COLD:
-		*status |= CHARGER_RES_COLD;
-		*status |= CHARGER_RES_UR;
-		break;
-	case RT946X_BATTEMP_HOT:
-		*status |= CHARGER_RES_HOT;
-		*status |= CHARGER_RES_OR;
-		break;
-	default:
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_set_mode(int chgnum, int mode)
-{
-	int rv;
-
-	if (mode & CHARGE_FLAG_POR_RESET) {
-		rv = rt946x_por_reset();
-		if (rv)
-			return rv;
-	}
-
-	if (mode & CHARGE_FLAG_RESET_TO_ZERO) {
-		rv = rt946x_reset_to_zero(chgnum);
-		if (rv)
-			return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_get_current(int chgnum, int *current)
-{
-	int rv;
-	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL7, &val);
-	if (rv)
-		return rv;
-
-	val = (val & RT946X_MASK_ICHG) >> RT946X_SHIFT_ICHG;
-	*current = val * info->current_step + info->current_min;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_set_current(int chgnum, int current)
-{
-	int rv;
-	uint8_t reg_icc;
-	static int workaround;
-	const struct charger_info *const info = rt946x_get_info(chgnum);
-
-	/*
-	 * mt6370's minimum regulated current is 500mA REG17[7:2] 0b100,
-	 * values below 0b100 are preserved.
-	 */
-	if (IS_ENABLED(CONFIG_CHARGER_MT6370))
-		current = MAX(500, current);
-
-#ifdef CONFIG_CHARGER_MT6370
-	rv = mt6370_ichg_workaround(chgnum, current);
-	if (rv)
-		return rv;
-#endif
-
-	reg_icc = rt946x_closest_reg(info->current_min, info->current_max,
-				     info->current_step, current);
-
-	rv = rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL7, RT946X_MASK_ICHG,
-				reg_icc << RT946X_SHIFT_ICHG);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_CHARGER_RT9466) ||
-	    IS_ENABLED(CONFIG_CHARGER_MT6370)) {
-		uint32_t curr_ieoc;
-
-		/*
-		 * workaround to make IEOC accurate:
-		 * witht normal charging (ICC >= 900mA), the power path is fully
-		 * turned on. But at low charging current state (ICC < 900mA),
-		 * the power path will only be partially turned on. So under
-		 * such situation, the IEOC is inaccurate.
-		 */
-		rv = rt946x_get_ieoc(chgnum, &curr_ieoc);
-		if (rv)
-			return rv;
-
-		if (current < 900 && !workaround) {
-			/* raise IEOC if charge current is under 900 */
-			rv = rt946x_set_ieoc(chgnum, curr_ieoc + 100);
-			workaround = 1;
-		} else if (current >= 900 && workaround) {
-			/* reset IEOC if charge current is above 900 */
-			workaround = 0;
-			rv = rt946x_set_ieoc(chgnum, curr_ieoc - 100);
-		}
-	}
-
-	return rv;
-}
-
-static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage)
-{
-	int rv;
-	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL4, &val);
-	if (rv)
-		return rv;
-
-	val = (val & RT946X_MASK_CV) >> RT946X_SHIFT_CV;
-	*voltage = val * info->voltage_step + info->voltage_min;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list rt946x_set_voltage(int chgnum, int voltage)
-{
-	uint8_t reg_cv = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
-
-	reg_cv = rt946x_closest_reg(info->voltage_min, info->voltage_max,
-		info->voltage_step, voltage);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL4, RT946X_MASK_CV,
-		reg_cv << RT946X_SHIFT_CV);
-}
-
-static enum ec_error_list rt946x_discharge_on_ac(int chgnum, int enable)
-{
-	return rt946x_enable_hz(chgnum, enable);
-}
-
-/* Setup sourcing current to prevent overload */
-#ifdef CONFIG_CHARGER_ILIM_PIN_DISABLED
-static int rt946x_enable_ilim_pin(int chgnum, int en)
-{
-	int ret;
-
-	ret = (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN);
-
-	return ret;
-}
-
-static int rt946x_select_ilmt(int chgnum, enum rt946x_ilmtsel sel)
-{
-	int ret;
-
-	ret = rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL2,
-				 RT946X_MASK_ILMTSEL,
-				 sel << RT946X_SHIFT_ILMTSEL);
-
-	return ret;
-}
-#endif /* CONFIG_CHARGER_ILIM_PIN_DISABLED */
-
-/* Charging power state initialization */
-static enum ec_error_list rt946x_post_init(int chgnum)
-{
-#ifdef CONFIG_CHARGER_ILIM_PIN_DISABLED
-	int rv;
-
-	rv = rt946x_select_ilmt(chgnum, RT946X_ILMTSEL_AICR);
-	if (rv)
-		return rv;
-
-	/* Need 5ms to ramp after choose current limit source */
-	msleep(5);
-
-	/* Disable ILIM pin */
-	rv = rt946x_enable_ilim_pin(chgnum, 0);
-	if (rv)
-		return rv;
-#endif
-	return EC_SUCCESS;
-}
-
-/* Hardware current ramping (aka AICL: Average Input Current Level) */
-#ifdef CONFIG_CHARGE_RAMP_HW
-static int rt946x_get_mivr(int chgnum, int *mivr)
-{
-	int rv;
-	int val = 0;
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL6, &val);
-	if (rv)
-		return rv;
-
-	val = (val & RT946X_MASK_MIVR) >> RT946X_SHIFT_MIVR;
-	*mivr = val * RT946X_MIVR_STEP + RT946X_MIVR_MIN;
-
-	return EC_SUCCESS;
-}
-
-static int rt946x_set_aicl_vth(int chgnum, uint8_t aicl_vth)
-{
-	uint8_t reg_aicl_vth = 0;
-
-	reg_aicl_vth = rt946x_closest_reg(RT946X_AICLVTH_MIN,
-		RT946X_AICLVTH_MAX, RT946X_AICLVTH_STEP, aicl_vth);
-
-	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL14,
-				  RT946X_MASK_AICLVTH,
-				  reg_aicl_vth << RT946X_SHIFT_AICLVTH);
-}
-
-static enum ec_error_list rt946x_set_hw_ramp(int chgnum, int enable)
-{
-	int rv;
-	unsigned int mivr = 0;
-
-	if (!enable) {
-		rv = rt946x_clr_bit(chgnum, RT946X_REG_CHGCTRL14,
-				    RT946X_MASK_AICLMEAS);
-		return rv;
-	}
-
-	rv = rt946x_get_mivr(chgnum, &mivr);
-	if (rv < 0)
-		return rv;
-
-	/*
-	 * Check if there's a suitable AICL_VTH.
-	 * The vendor suggests setting AICL_VTH as (MIVR + 200mV).
-	 */
-	if ((mivr + 200) > RT946X_AICLVTH_MAX) {
-		CPRINTS("mivr(%d) too high", mivr);
-		return EC_ERROR_INVAL;
-	}
-
-	rv = rt946x_set_aicl_vth(chgnum, mivr + 200);
-	if (rv < 0)
-		return rv;
-
-	return rt946x_set_bit(chgnum, RT946X_REG_CHGCTRL14,
-			      RT946X_MASK_AICLMEAS);
-}
-
-static int rt946x_ramp_is_stable(int chgnum)
-{
-	int rv;
-	int val = 0;
-
-	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL14, &val);
-	val = (val & RT946X_MASK_AICLMEAS) >> RT946X_SHIFT_AICLMEAS;
-
-	return (!rv && !val);
-}
-
-static int rt946x_ramp_is_detected(int chgnum)
-{
-	return 1;
-}
-
-static int rt946x_ramp_get_current_limit(int chgnum)
-{
-	int rv;
-	int input_current = 0;
-
-	rv = rt946x_get_input_current_limit(chgnum, &input_current);
-
-	return rv ? -1 : input_current;
-}
-#endif /* CONFIG_CHARGE_RAMP_HW */
-
-static void rt946x_init(int chgnum)
-{
-	int ret = rt946x_init_setting(chgnum);
-
-	CPRINTS("init%d %s(%d)", chgnum, ret ? "fail" : "good", ret);
-}
-
-#ifdef HAS_TASK_USB_CHG
-#ifdef CONFIG_CHARGER_MT6370
-static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat)
-{
-	int ret, reg;
-	int chg_type =
-		(usb_stat & MT6370_MASK_USB_STATUS) >> MT6370_SHIFT_USB_STATUS;
-	int dp_2_3v, dm_2_3v;
-
-	/* Only SDP/CDP/DCP could possibly be Apple/Samsung TA */
-	if (chg_type != MT6370_CHG_TYPE_SDPNSTD &&
-	    chg_type != MT6370_CHG_TYPE_CDP &&
-	    chg_type != MT6370_CHG_TYPE_DCP)
-		return chg_type;
-
-	if (chg_type == MT6370_CHG_TYPE_SDPNSTD ||
-	    chg_type == MT6370_CHG_TYPE_CDP)
-		if (!(usb_stat & MT6370_MASK_DCD_TIMEOUT))
-			return chg_type;
-
-	/* Check D+ > 0.9V */
-	ret = rt946x_update_bits(chgnum, MT6370_REG_QCSTATUS2,
-				 MT6360_MASK_CHECK_DPDM,
-				 MT6370_MASK_APP_SS_EN | MT6370_MASK_APP_SS_PL);
-	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
-
-	if (ret)
-		return chg_type;
-
-	/* Normal port (D+ < 0.9V) */
-	if (!(reg & MT6370_MASK_SS_OUT))
-		return chg_type;
-
-	/* Samsung charger (D+ < 1.5V) */
-	if (!(reg & MT6370_MASK_APP_OUT))
-		return MT6370_CHG_TYPE_SAMSUNG_CHARGER;
-
-	/* Check D+ > 2.3 V */
-	ret = rt946x_update_bits(chgnum, MT6370_REG_QCSTATUS2,
-				 MT6360_MASK_CHECK_DPDM,
-				 MT6370_MASK_APP_REF | MT6370_MASK_APP_SS_PL |
-				 MT6370_MASK_APP_SS_EN);
-	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
-	dp_2_3v = reg & MT6370_MASK_APP_OUT;
-
-	/* Check D- > 2.3 V */
-	ret |= rt946x_update_bits(chgnum,
-		MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM,
-		MT6370_MASK_APP_REF | MT6370_MASK_APP_DPDM_IN |
-			MT6370_MASK_APP_SS_PL | MT6370_MASK_APP_SS_EN);
-	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
-	dm_2_3v = reg & MT6370_MASK_APP_OUT;
-
-	if (ret)
-		return chg_type;
-
-	/* Apple charger */
-	if (!dp_2_3v && !dm_2_3v)
-		/* Apple 2.5W charger */
-		return MT6370_CHG_TYPE_APPLE_0_5A_CHARGER;
-	else if (!dp_2_3v && dm_2_3v)
-		/* Apple 5W charger */
-		return MT6370_CHG_TYPE_APPLE_1_0A_CHARGER;
-	else if (dp_2_3v && !dm_2_3v)
-		/* Apple 10W charger */
-		return MT6370_CHG_TYPE_APPLE_2_1A_CHARGER;
-	else
-		/* Apple 12W charger */
-		return MT6370_CHG_TYPE_APPLE_2_4A_CHARGER;
-}
-#endif
-
-static int mt6370_get_bc12_device_type(int charger_type)
-{
-	switch (charger_type) {
-	case MT6370_CHG_TYPE_SDP:
-	case MT6370_CHG_TYPE_SDPNSTD:
-		return CHARGE_SUPPLIER_BC12_SDP;
-	case MT6370_CHG_TYPE_CDP:
-		return CHARGE_SUPPLIER_BC12_CDP;
-	case MT6370_CHG_TYPE_DCP:
-	case MT6370_CHG_TYPE_SAMSUNG_CHARGER:
-	case MT6370_CHG_TYPE_APPLE_0_5A_CHARGER:
-	case MT6370_CHG_TYPE_APPLE_1_0A_CHARGER:
-	case MT6370_CHG_TYPE_APPLE_2_1A_CHARGER:
-	case MT6370_CHG_TYPE_APPLE_2_4A_CHARGER:
-		return CHARGE_SUPPLIER_BC12_DCP;
-	default:
-		return CHARGE_SUPPLIER_NONE;
-	}
-}
-
-/* Returns a mt6370 charger_type. */
-static int mt6370_get_charger_type(int chgnum)
-{
-#ifdef CONFIG_CHARGER_MT6370
-	int reg;
-
-	if (rt946x_read8(chgnum, MT6370_REG_USBSTATUS1, &reg))
-		return CHARGE_SUPPLIER_NONE;
-	return mt6370_detect_apple_samsung_ta(chgnum, reg);
-#else
-	return CHARGE_SUPPLIER_NONE;
-#endif
-}
-
-/*
- * The USB Type-C specification limits the maximum amount of current from BC 1.2
- * suppliers to 1.5A.  Technically, proprietary methods are not allowed, but we
- * will continue to allow those.
- */
-static int mt6370_get_bc12_ilim(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case MT6370_CHG_TYPE_APPLE_0_5A_CHARGER:
-		return 500;
-	case MT6370_CHG_TYPE_APPLE_1_0A_CHARGER:
-		return 1000;
-	case MT6370_CHG_TYPE_APPLE_2_1A_CHARGER:
-	case MT6370_CHG_TYPE_APPLE_2_4A_CHARGER:
-	case MT6370_CHG_TYPE_DCP:
-	case MT6370_CHG_TYPE_CDP:
-	case MT6370_CHG_TYPE_SAMSUNG_CHARGER:
-		return USB_CHARGER_MAX_CURR_MA;
-	case MT6370_CHG_TYPE_SDP:
-	default:
-		return USB_CHARGER_MIN_CURR_MA;
-	}
-}
-
-static int rt946x_get_bc12_device_type(int chgnum, int charger_type)
-{
-	int reg;
-
-	if (rt946x_read8(chgnum, RT946X_REG_DPDM1, &reg))
-		return CHARGE_SUPPLIER_NONE;
-
-	switch (reg & RT946X_MASK_BC12_TYPE) {
-	case RT946X_MASK_SDP:
-		return CHARGE_SUPPLIER_BC12_SDP;
-	case RT946X_MASK_CDP:
-		return CHARGE_SUPPLIER_BC12_CDP;
-	case RT946X_MASK_DCP:
-		return CHARGE_SUPPLIER_BC12_DCP;
-	default:
-		return CHARGE_SUPPLIER_NONE;
-	}
-}
-
-static int rt946x_get_bc12_ilim(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-		if (IS_ENABLED(CONFIG_CHARGE_RAMP_SW) ||
-		    IS_ENABLED(CONFIG_CHARGE_RAMP_HW))
-			/* A conservative value to prevent a bad charger. */
-			return RT946X_AICR_TYP2MAX(USB_CHARGER_MAX_CURR_MA);
-		/* fallback */
-	case CHARGE_SUPPLIER_BC12_CDP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_SDP:
-	default:
-		return USB_CHARGER_MIN_CURR_MA;
-	}
-}
-
-static void check_ac_state(void)
-{
-	static uint8_t ac;
-
-	if (ac != extpower_is_present()) {
-		ac = !ac;
-		hook_notify(HOOK_AC_CHANGE);
-	}
-}
-DECLARE_DEFERRED(check_ac_state);
-
-void rt946x_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_USB_CHG);
-	/*
-	 * Generally, VBUS detection can be done immediately when the port
-	 * plug/unplug happens. But if it's a PD plug(and will generate an
-	 * interrupt), then it will take a few milliseconds to raise VBUS
-	 * by PD negotiation.
-	 */
-	hook_call_deferred(&check_ac_state_data, 100 * MSEC);
-}
-
-int rt946x_toggle_bc12_detection(void)
-{
-	int rv;
-	rv = rt946x_enable_bc12_detection(CHARGER_SOLO, 0);
-	if (rv)
-		return rv;
-	/* mt6370 requires 40us delay to toggle RT946X_MASK_USBCHGEN */
-	udelay(40);
-	return rt946x_enable_bc12_detection(CHARGER_SOLO, 1);
-}
-
-static void check_pd_capable(void)
-{
-	const int port = TASK_ID_TO_USB_CHG_PORT(TASK_ID_USB_CHG);
-
-	if (!pd_capable(port)) {
-		enum tcpc_cc_voltage_status cc1, cc2;
-
-		tcpm_get_cc(port, &cc1, &cc2);
-		/* if CC is not changed. */
-		if (cc_is_rp(cc1) || cc_is_rp(cc2))
-			rt946x_toggle_bc12_detection();
-	}
-}
-DECLARE_DEFERRED(check_pd_capable);
-
-static void rt946x_usb_connect(void)
-{
-	const int port = TASK_ID_TO_USB_CHG_PORT(TASK_ID_USB_CHG);
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	tcpm_get_cc(port, &cc1, &cc2);
-
-	/*
-	 * Only detect BC1.2 device when USB-C device recognition is
-	 * finished to prevent a potential race condition with USB enumeration.
-	 * If CC exists RP, then it might be a BC12 or a PD capable device.
-	 * Check this later to ensure it's not PD capable.
-	 */
-	if (cc_is_rp(cc1) || cc_is_rp(cc2))
-		/* delay extra 50 ms to ensure SrcCap received */
-		hook_call_deferred(&check_pd_capable_data,
-				   PD_T_SINK_WAIT_CAP + 50 * MSEC);
-	hook_call_deferred(&check_ac_state_data, 0);
-}
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, rt946x_usb_connect, HOOK_PRIO_DEFAULT);
-
-static void rt946x_pd_disconnect(void)
-{
-	/* Type-C disconnected, disable deferred check. */
-	hook_call_deferred(&check_pd_capable_data, -1);
-	hook_call_deferred(&check_ac_state_data, 0);
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, rt946x_pd_disconnect, HOOK_PRIO_DEFAULT);
-
-int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
-{
-	int rv, i, adc_start, adc_result = 0;
-	int adc_data_h, adc_data_l, aicr;
-	const int max_wait_times = 6;
-
-	if (in_interrupt_context()) {
-		CPRINTS("Err: use ADC in IRQ");
-		return EC_ERROR_INVAL;
-        }
-	mutex_lock(&adc_access_lock);
-#ifdef CONFIG_CHARGER_MT6370
-	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
-#endif
-
-	/* Select ADC to desired channel */
-	rv = rt946x_update_bits(CHARGER_SOLO, RT946X_REG_CHGADC,
-				RT946X_MASK_ADC_IN_SEL,
-				adc_sel << RT946X_SHIFT_ADC_IN_SEL);
-	if (rv)
-		goto out;
-
-	if (adc_sel == MT6370_ADC_IBUS) {
-		rv = charger_get_input_current_limit(CHARGER_SOLO, &aicr);
-		if (rv)
-			goto out;
-	}
-
-	/* Start ADC conversation */
-	rv = rt946x_set_bit(CHARGER_SOLO, RT946X_REG_CHGADC,
-			    RT946X_MASK_ADC_START);
-	if (rv)
-		goto out;
-
-	for (i = 0; i < max_wait_times; i++) {
-		msleep(35);
-		rv = mt6370_pmu_reg_test_bit(CHARGER_SOLO, RT946X_REG_CHGADC,
-					      RT946X_SHIFT_ADC_START,
-					      &adc_start);
-		if (!adc_start && rv == 0)
-			break;
-	}
-	if (i == max_wait_times)
-		CPRINTS("conversion fail sel=%d", adc_sel);
-
-	/* Read ADC data */
-	rv = rt946x_read8(CHARGER_SOLO, RT946X_REG_ADCDATAH, &adc_data_h);
-	rv = rt946x_read8(CHARGER_SOLO, RT946X_REG_ADCDATAL, &adc_data_l);
-	if (rv)
-		goto out;
-
-#if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-	if (adc_sel == RT946X_ADC_VBUS_DIV5)
-		adc_result = ((adc_data_h << 8) | adc_data_l) * 25;
-	else
-		CPRINTS("unsupported channel %d", adc_sel);
-	*adc_val = adc_result;
-#elif defined(CONFIG_CHARGER_MT6370)
-	/* Calculate ADC value */
-	adc_result = (adc_data_h * 256 + adc_data_l)
-			* mt6370_adc_unit[adc_sel] + mt6370_adc_offset[adc_sel];
-
-	/* For TS_BAT/TS_BUS, the real unit is 0.25, here we use 25(unit) */
-	if (adc_sel == MT6370_ADC_TS_BAT)
-		adc_result /= 100;
-#endif
-
-out:
-#ifdef CONFIG_CHARGER_MT6370
-	if (adc_sel == MT6370_ADC_IBUS) {
-		if (aicr < 400) /* 400mA */
-			adc_result = adc_result * 67 / 100;
-	}
-
-	if (adc_sel != MT6370_ADC_TS_BAT && adc_sel != MT6370_ADC_TEMP_JC)
-		*adc_val = adc_result / 1000;
-	else
-		*adc_val = adc_result;
-	mt6370_enable_hidden_mode(CHARGER_SOLO, 0);
-#endif
-	mutex_unlock(&adc_access_lock);
-	return rv;
-}
-
-static enum ec_error_list rt946x_get_vbus_voltage(int chgnum, int port,
-						  int *voltage)
-{
-	int vbus_mv;
-	int rv;
-
-	rv = rt946x_get_adc(RT946X_ADC_VBUS_DIV5, &vbus_mv);
-	*voltage = vbus_mv;
-
-	return rv;
-}
-
-#ifdef CONFIG_CHARGER_MT6370
-static int mt6370_toggle_cfo(void)
-{
-	int rv, data;
-
-	rv = rt946x_read8(CHARGER_SOLO, MT6370_REG_FLEDEN, &data);
-	if (rv)
-		return rv;
-
-	if (data & MT6370_STROBE_EN_MASK)
-		return rv;
-
-	/* read data */
-	rv = rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGCTRL2, &data);
-	if (rv)
-		return rv;
-
-	/* cfo off */
-	data &= ~RT946X_MASK_CFO_EN;
-	rv = rt946x_write8(CHARGER_SOLO, RT946X_REG_CHGCTRL2, data);
-	if (rv)
-		return rv;
-
-	/* cfo on */
-	data |= RT946X_MASK_CFO_EN;
-	return rt946x_write8(CHARGER_SOLO, RT946X_REG_CHGCTRL2, data);
-}
-
-static int mt6370_pmu_chg_mivr_irq_handler(int chgnum)
-{
-	int rv, ibus = 0, mivr_stat;
-
-	rv = mt6370_pmu_reg_test_bit(chgnum, MT6370_REG_CHGSTAT1,
-				MT6370_SHIFT_MIVR_STAT, &mivr_stat);
-	if (rv)
-		return rv;
-
-	if (!mivr_stat) {
-		CPRINTS("no mivr stat");
-		return rv;
-	}
-
-	rv = rt946x_get_adc(MT6370_ADC_IBUS, &ibus);
-	if (rv)
-		return rv;
-
-	if (ibus < 100) /* 100mA */
-		rv = mt6370_toggle_cfo();
-
-	return rv;
-}
-
-static int mt6370_irq_handler(int chgnum)
-{
-	int data, mask, ret, reg_val;
-	int stat_chg, valid_chg, stat_old, stat_new;
-
-	ret = rt946x_write8(chgnum, MT6370_REG_IRQMASK, MT6370_IRQ_MASK_ALL);
-	if (ret)
-		return ret;
-
-	ret = rt946x_read8(chgnum, MT6370_REG_IRQIND, &reg_val);
-	if (ret)
-		return ret;
-
-	/* read stat before reading irq evt */
-	ret = rt946x_read8(chgnum, MT6370_REG_CHGSTAT1, &stat_old);
-	if (ret)
-		return ret;
-
-	/* workaround for irq, divided irq event into upper and lower */
-	ret = rt946x_read8(chgnum, MT6370_REG_CHGIRQ1, &data);
-	if (ret)
-		return ret;
-
-	/* read stat after reading irq evt */
-	ret = rt946x_read8(chgnum, MT6370_REG_CHGSTAT1, &stat_new);
-	if (ret)
-		return ret;
-
-	ret = rt946x_read8(chgnum, MT6370_REG_CHGMASK1, &mask);
-	if (ret)
-		return ret;
-
-	ret = rt946x_write8(chgnum, MT6370_REG_IRQMASK, 0x00);
-	if (ret)
-		return ret;
-
-	stat_chg = stat_old ^ stat_new;
-	valid_chg = (stat_new & 0xF1) | (~stat_new & 0xF1);
-	data |= (stat_chg & valid_chg);
-	data &= ~mask;
-	if (data)
-		ret = mt6370_pmu_chg_mivr_irq_handler(chgnum);
-	return ret;
-}
-#endif /* CONFIG_CHARGER_MT6370 */
-
-static void rt946x_bc12_workaround(void)
-{
-	/*
-	 * There is a parasitic capacitance on D+,
-	 * which results in pulling D+ up too slow while detecting BC1.2.
-	 * So we try to fix this in two steps:
-	 * 1. Pull D+ up to a voltage under 0.6V
-	 * 2. re-toggling and pull D+ up to 0.6V (again)
-	 * and then detect the voltage of D-.
-	 */
-	rt946x_toggle_bc12_detection();
-	msleep(10);
-	rt946x_toggle_bc12_detection();
-}
-DECLARE_DEFERRED(rt946x_bc12_workaround);
-
-static void rt946x_usb_charger_task(const int unused)
-{
-	struct charge_port_info chg;
-	int bc12_type = CHARGE_SUPPLIER_NONE;
-	int chg_type;
-	int reg = 0;
-	int bc12_cnt = 0;
-	const int max_bc12_cnt = 3;
-	int voltage;
-
-	chg.voltage = USB_CHARGER_VOLTAGE_MV;
-	while (1) {
-#ifdef CONFIG_CHARGER_MT6370
-		mt6370_irq_handler(CHARGER_SOLO);
-#endif /* CONFIG_CHARGER_MT6370 */
-
-		rt946x_read8(CHARGER_SOLO, RT946X_REG_DPDMIRQ, &reg);
-
-		/* VBUS attach event */
-		if (reg & RT946X_MASK_DPDMIRQ_ATTACH) {
-			charger_get_vbus_voltage(0, &voltage);
-			CPRINTS("VBUS attached: %dmV", voltage);
-			if (IS_ENABLED(CONFIG_CHARGER_MT6370)) {
-				chg_type =
-					mt6370_get_charger_type(CHARGER_SOLO);
-				bc12_type =
-					mt6370_get_bc12_device_type(chg_type);
-				chg.current = mt6370_get_bc12_ilim(bc12_type);
-			} else {
-				bc12_type =
-				    rt946x_get_bc12_device_type(CHARGER_SOLO,
-								    chg_type);
-				chg.current = rt946x_get_bc12_ilim(bc12_type);
-			}
-			CPRINTS("BC12 type %d", bc12_type);
-			if (bc12_type == CHARGE_SUPPLIER_NONE)
-				goto bc12_none;
-			if (IS_ENABLED(CONFIG_WIRELESS_CHARGER_P9221_R7) &&
-			    bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
-			    wpc_chip_is_online()) {
-					p9221_notify_vbus_change(1);
-					CPRINTS("WPC ON");
-			}
-			if (bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
-			    ++bc12_cnt < max_bc12_cnt) {
-				/*
-				 * defer the workaround and awaiting for
-				 * waken up by the interrupt.
-				 */
-				hook_call_deferred(
-					&rt946x_bc12_workaround_data, 5);
-				goto wait_event;
-			}
-
-			charge_manager_update_charge(bc12_type, 0, &chg);
-bc12_none:
-			rt946x_enable_bc12_detection(CHARGER_SOLO, 0);
-		}
-
-		/* VBUS detach event */
-		if (reg & RT946X_MASK_DPDMIRQ_DETACH &&
-		    bc12_type != CHARGE_SUPPLIER_NONE) {
-			CPRINTS("VBUS detached");
-			bc12_cnt = 0;
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			p9221_notify_vbus_change(0);
-#endif
-			charge_manager_update_charge(bc12_type, 0, NULL);
-		}
-
-wait_event:
-		task_wait_event(-1);
-	}
-}
-
-static int rt946x_ramp_allowed(int supplier)
-{
-	return supplier == CHARGE_SUPPLIER_BC12_DCP;
-}
-
-static int rt946x_ramp_max(int supplier, int sup_curr)
-{
-	return rt946x_get_bc12_ilim(supplier);
-}
-#endif /* HAS_TASK_USB_CHG */
-
-/* Non-standard interface functions */
-
-int rt946x_enable_charger_boost(int en)
-{
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN);
-}
-
-/*
- * rt946x reports VBUS ready after VBUS is up for ~500ms.
- * Check if this works for the use case before calling this function.
- */
-int rt946x_is_vbus_ready(void)
-{
-	int val = 0;
-
-	return rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGSTATC, &val) ?
-	       0 : !!(val & RT946X_MASK_PWR_RDY);
-}
-
-int rt946x_is_charge_done(void)
-{
-	int val = 0;
-
-	if (rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGSTAT, &val))
-		return 0;
-
-	val = (val & RT946X_MASK_CHG_STAT) >> RT946X_SHIFT_CHG_STAT;
-
-	return val == RT946X_CHGSTAT_DONE;
-}
-
-int rt946x_cutoff_battery(void)
-{
-#ifdef CONFIG_CHARGER_MT6370
-/*
- * We should lock ADC usage to prevent from using ADC while
- * cut-off. Or this might cause the ADC power not turning off.
- */
-
-	int rv;
-
-	mutex_lock(&adc_access_lock);
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_REG_RSTPASCODE1,
-			   MT6370_MASK_RSTPASCODE1);
-	if (rv)
-		goto out;
-
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_REG_RSTPASCODE2,
-			   MT6370_MASK_RSTPASCODE2);
-	if (rv)
-		goto out;
-
-	/* reset all chg/fled/ldo/rgb/bl/db reg and logic */
-	rv = rt946x_write8(CHARGER_SOLO, RT946X_REG_CORECTRL2, 0x7F);
-	if (rv)
-		goto out;
-
-	/* disable chg auto sensing */
-	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
-	rv = rt946x_clr_bit(CHARGER_SOLO, MT6370_REG_CHGHIDDENCTRL15,
-				MT6370_MASK_ADC_TS_AUTO);
-	mt6370_enable_hidden_mode(CHARGER_SOLO, 0);
-	if (rv)
-		goto out;
-	msleep(50);
-	/* enter shipping mode */
-	rv = rt946x_set_bit(CHARGER_SOLO, RT946X_REG_CHGCTRL2,
-			    RT946X_MASK_SHIP_MODE);
-
-out:
-	mutex_unlock(&adc_access_lock);
-	return rv;
-#endif
-	/* enter shipping mode */
-	return rt946x_set_bit(CHARGER_SOLO, RT946X_REG_CHGCTRL2,
-			      RT946X_MASK_SHIP_MODE);
-}
-
-int rt946x_enable_charge_termination(int en)
-{
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE);
-}
-
-int rt946x_enable_charge_eoc(int en)
-{
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC);
-}
-
-#ifdef CONFIG_CHARGER_MT6370
-/* MT6370 LDO */
-
-int mt6370_set_ldo_voltage(int mv)
-{
-	int rv;
-	int vout_val;
-	const int vout_mask = MT6370_MASK_LDOVOUT_EN | MT6370_MASK_LDOVOUT_VOUT;
-
-	/* LDO output-off mode to floating. */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_REG_LDOCFG,
-				MT6370_MASK_LDOCFG_OMS, 0);
-	if (rv)
-		return rv;
-
-	/* Disable LDO if voltage is zero. */
-	if (mv == 0)
-		return rt946x_clr_bit(CHARGER_SOLO, MT6370_REG_LDOVOUT,
-				      MT6370_MASK_LDOVOUT_EN);
-
-	vout_val = 1 << MT6370_SHIFT_LDOVOUT_EN;
-	vout_val |= rt946x_closest_reg(MT6370_LDO_MIN, MT6370_LDO_MAX,
-				       MT6370_LDO_STEP, mv);
-	return rt946x_update_bits(CHARGER_SOLO, MT6370_REG_LDOVOUT, vout_mask,
-				  vout_val);
-}
-
-/* MT6370 Display bias */
-int mt6370_db_external_control(int en)
-{
-	return rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBCTRL1,
-				  MT6370_MASK_DB_EXT_EN,
-				  en << MT6370_SHIFT_DB_EXT_EN);
-}
-
-int mt6370_db_set_voltages(int vbst, int vpos, int vneg)
-{
-	int rv;
-
-	/* set display bias VBST */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVBST,
-				MT6370_MASK_DB_VBST,
-				rt946x_closest_reg(MT6370_DB_VBST_MIN,
-						   MT6370_DB_VBST_MAX,
-						   MT6370_DB_VBST_STEP, vbst));
-
-	/* set display bias VPOS */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVPOS,
-				 MT6370_MASK_DB_VPOS,
-				 rt946x_closest_reg(MT6370_DB_VPOS_MIN,
-						    MT6370_DB_VPOS_MAX,
-						    MT6370_DB_VPOS_STEP, vpos));
-
-	/* set display bias VNEG */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVNEG,
-				 MT6370_MASK_DB_VNEG,
-				 rt946x_closest_reg(MT6370_DB_VNEG_MIN,
-						    MT6370_DB_VNEG_MAX,
-						    MT6370_DB_VNEG_STEP, vneg));
-
-	/* Enable VNEG/VPOS discharge when VNEG/VPOS rails disabled. */
-	rv |= rt946x_update_bits(CHARGER_SOLO,
-		MT6370_REG_DBCTRL2,
-		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC,
-		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC);
-
-	return rv;
-}
-
-/* MT6370 BACKLIGHT LED */
-
-int mt6370_backlight_set_dim(uint16_t dim)
-{
-	int rv;
-
-	/* datasheet suggests that update BLDIM2 first then BLDIM */
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_BACKLIGHT_BLDIM2,
-			   dim & MT6370_MASK_BLDIM2);
-
-	if (rv)
-		return rv;
-
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_BACKLIGHT_BLDIM,
-			   (dim >> MT6370_SHIFT_BLDIM_MSB) & MT6370_MASK_BLDIM);
-
-	return rv;
-}
-
-/* MT6370 RGB LED */
-
-int mt6370_led_set_dim_mode(enum mt6370_led_index index,
-			    enum mt6370_led_dim_mode mode)
-{
-	if (index <= MT6370_LED_ID_OFF || index >= MT6370_LED_ID_COUNT)
-		return EC_ERROR_INVAL;
-
-	rt946x_update_bits(CHARGER_SOLO, MT6370_REG_RGBDIM_BASE + index,
-			   MT6370_MASK_RGB_DIMMODE,
-			   mode << MT6370_SHIFT_RGB_DIMMODE);
-	return EC_SUCCESS;
-}
-
-int mt6370_led_set_color(uint8_t mask)
-{
-	return rt946x_update_bits(CHARGER_SOLO, MT6370_REG_RGBEN,
-				  MT6370_MASK_RGB_ISNK_ALL_EN, mask);
-}
-
-int mt6370_led_set_brightness(enum mt6370_led_index index, uint8_t brightness)
-{
-	if (index >= MT6370_LED_ID_COUNT || index <= MT6370_LED_ID_OFF)
-		return EC_ERROR_INVAL;
-
-	rt946x_update_bits(CHARGER_SOLO, MT6370_REG_RGBISNK_BASE + index,
-			   MT6370_MASK_RGBISNK_CURSEL,
-			   brightness << MT6370_SHIFT_RGBISNK_CURSEL);
-	return EC_SUCCESS;
-}
-
-int mt6370_led_set_pwm_dim_duty(enum mt6370_led_index index, uint8_t dim_duty)
-{
-	if (index >= MT6370_LED_ID_COUNT || index <= MT6370_LED_ID_OFF)
-		return EC_ERROR_INVAL;
-
-	rt946x_update_bits(CHARGER_SOLO, MT6370_REG_RGBDIM_BASE + index,
-			   MT6370_MASK_RGB_DIMDUTY,
-			   dim_duty << MT6370_SHIFT_RGB_DIMDUTY);
-	return EC_SUCCESS;
-}
-
-int mt6370_led_set_pwm_frequency(enum mt6370_led_index index,
-				 enum mt6370_led_pwm_freq freq)
-{
-	if (index >= MT6370_LED_ID_COUNT || index <= MT6370_LED_ID_OFF)
-		return EC_ERROR_INVAL;
-
-	rt946x_update_bits(CHARGER_SOLO, MT6370_REG_RGBISNK_BASE + index,
-			   MT6370_MASK_RGBISNK_DIMFSEL,
-			   freq << MT6370_SHIFT_RGBISNK_DIMFSEL);
-	return EC_SUCCESS;
-}
-
-int mt6370_reduce_db_bl_driving(void)
-{
-	int rv;
-
-	/* Enter test mode */
-	rv = rt946x_block_write(CHARGER_SOLO, MT6370_REG_TM_PAS_CODE1,
-				mt6370_val_en_test_mode,
-				ARRAY_SIZE(mt6370_val_en_test_mode));
-	if (rv)
-		return rv;
-	msleep(1);
-	rv = rt946x_write8(CHARGER_SOLO, MT6370_REG_BANK, MT6370_MASK_REG_TM);
-	if (rv)
-		return rv;
-	msleep(1);
-	/* reduce bl driving */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_TM_REG_BL3,
-				MT6370_TM_MASK_BL3_SL, MT6370_TM_REDUCE_BL3_SL);
-	if (rv)
-		return rv;
-	msleep(1);
-	/* reduce db driving */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_TM_REG_DSV1,
-				MT6370_TM_MASK_DSV1_SL,
-				MT6370_TM_REDUCE_DSV1_SL);
-	if (rv)
-		return rv;
-	msleep(1);
-	/* Leave test mode */
-	return rt946x_write8(CHARGER_SOLO, MT6370_REG_TM_PAS_CODE1,
-			     MT6370_LEAVE_TM);
-}
-#endif /* CONFIG_CHARGER_MT6370 */
-
-const struct charger_drv rt946x_drv = {
-	.init = &rt946x_init,
-	.post_init = &rt946x_post_init,
-	.get_info = &rt946x_get_info,
-	.get_status = &rt946x_get_status,
-	.set_mode = &rt946x_set_mode,
-	.enable_otg_power = &rt946x_enable_otg_power,
-	.is_sourcing_otg_power = &rt946x_is_sourcing_otg_power,
-	.get_current = &rt946x_get_current,
-	.set_current = &rt946x_set_current,
-	.get_voltage = &rt946x_get_voltage,
-	.set_voltage = &rt946x_set_voltage,
-	.discharge_on_ac = &rt946x_discharge_on_ac,
-	.get_vbus_voltage = &rt946x_get_vbus_voltage,
-	.set_input_current_limit = &rt946x_set_input_current_limit,
-	.get_input_current_limit = &rt946x_get_input_current_limit,
-	.manufacturer_id = &rt946x_manufacturer_id,
-	.device_id = &rt946x_device_id,
-	.get_option = &rt946x_get_option,
-	.set_option = &rt946x_set_option,
-#ifdef CONFIG_CHARGE_RAMP_HW
-	.set_hw_ramp = &rt946x_set_hw_ramp,
-	.ramp_is_stable = &rt946x_ramp_is_stable,
-	.ramp_is_detected = &rt946x_ramp_is_detected,
-	.ramp_get_current_limit = &rt946x_ramp_get_current_limit,
-#endif
-};
-
-#ifdef HAS_TASK_USB_CHG
-const struct bc12_drv rt946x_bc12_drv = {
-	.usb_charger_task = rt946x_usb_charger_task,
-	.ramp_allowed = rt946x_ramp_allowed,
-	.ramp_max = rt946x_ramp_max,
-};
-
-#ifdef CONFIG_BC12_SINGLE_DRIVER
-/* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &rt946x_bc12_drv,
-	},
-};
-#endif /* CONFIG_BC12_SINGLE_DRIVER */
-#endif
diff --git a/driver/charger/rt946x.h b/driver/charger/rt946x.h
deleted file mode 100644
index 5e6f9e0223..0000000000
--- a/driver/charger/rt946x.h
+++ /dev/null
@@ -1,853 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Richtek rt9466/rt9467, Mediatek mt6370 battery charger driver.
- */
-
-#ifndef __CROS_EC_RT946X_H
-#define __CROS_EC_RT946X_H
-
-/* Registers for rt9466, rt9467 */
-#if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_REG_CORECTRL0		0x00
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL0
-#define RT946X_REG_CHGCTRL1		0x01
-#define RT946X_REG_CHGCTRL2		0x02
-#define RT946X_REG_CHGCTRL3		0x03
-#define RT946X_REG_CHGCTRL4		0x04
-#define RT946X_REG_CHGCTRL5		0x05
-#define RT946X_REG_CHGCTRL6		0x06
-#define RT946X_REG_CHGCTRL7		0x07
-#define RT946X_REG_CHGCTRL8		0x08
-#define RT946X_REG_CHGCTRL9		0x09
-#define RT946X_REG_CHGCTRL10		0x0A
-#define RT946X_REG_CHGCTRL11		0x0B
-#define RT946X_REG_CHGCTRL12		0x0C
-#define RT946X_REG_CHGCTRL13		0x0D
-#define RT946X_REG_CHGCTRL14		0x0E
-#define RT946X_REG_CHGCTRL15		0x0F
-#define RT946X_REG_CHGCTRL16		0x10
-#define RT946X_REG_CHGADC		0x11
-
-#ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDM1		0x12
-#define RT946X_REG_DPDM2		0x13
-#define RT946X_REG_DPDM3		0x14
-#endif
-
-#define RT946X_REG_CHGCTRL19		0x18
-#define RT946X_REG_CHGCTRL17		0x19
-#define RT946X_REG_CHGCTRL18		0x1A
-#define RT946X_REG_CHGHIDDENCTRL2	0x21
-#define RT946X_REG_CHGHIDDENCTRL4	0x23
-#define RT946X_REG_CHGHIDDENCTRL6	0x25
-#define RT946X_REG_CHGHIDDENCTRL7	0x26
-#define RT946X_REG_CHGHIDDENCTRL8	0x27
-#define RT946X_REG_CHGHIDDENCTRL9	0x28
-#define RT946X_REG_CHGHIDDENCTRL15	0x2E
-#define RT946X_REG_DEVICEID		0x40
-#define RT946X_REG_CHGSTAT		0x42
-#define RT946X_REG_CHGNTC		0x43
-#define RT946X_REG_ADCDATAH		0x44
-#define RT946X_REG_ADCDATAL		0x45
-#define RT946X_REG_CHGSTATC		0x50
-#define RT946X_REG_CHGFAULT		0x51
-#define RT946X_REG_TSSTATC		0x52
-#define RT946X_REG_CHGIRQ1		0x53
-#define RT946X_REG_CHGIRQ2		0x54
-#define RT946X_REG_CHGIRQ3		0x55
-
-#ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQ		0x56
-#endif
-
-#define RT946X_REG_CHGSTATCCTRL		0x60
-#define RT946X_REG_CHGFAULTCTRL		0x61
-#define RT946X_REG_TSSTATCCTRL		0x62
-#define RT946X_REG_CHGIRQ1CTRL		0x63
-#define RT946X_REG_CHGIRQ2CTRL		0x64
-#define RT946X_REG_CHGIRQ3CTRL		0x65
-
-#ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQCTRL		0x66
-#endif
-
-#elif defined(CONFIG_CHARGER_MT6370)
-/* Registers for mt6370 */
-#define RT946X_REG_DEVICEID		0x00
-#define RT946X_REG_CORECTRL1		0x01
-#define RT946X_REG_CORECTRL2		0x02
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL2
-#define MT6370_REG_RSTPASCODE1		0x03
-#define MT6370_REG_RSTPASCODE2		0x04
-#define MT6370_REG_HIDDENPASCODE1	0x07
-#define MT6370_REG_HIDDENPASCODE2	0x08
-#define MT6370_REG_HIDDENPASCODE3	0x09
-#define MT6370_REG_HIDDENPASCODE4	0x0A
-#define MT6370_REG_IRQIND		0x0B
-#define MT6370_REG_IRQMASK		0x0C
-#define MT6370_REG_OSCCTRL		0x10
-#define RT946X_REG_CHGCTRL1		0x11
-#define RT946X_REG_CHGCTRL2		0x12
-#define RT946X_REG_CHGCTRL3		0x13
-#define RT946X_REG_CHGCTRL4		0x14
-#define RT946X_REG_CHGCTRL5		0x15
-#define RT946X_REG_CHGCTRL6		0x16
-#define RT946X_REG_CHGCTRL7		0x17
-#define RT946X_REG_CHGCTRL8		0x18
-#define RT946X_REG_CHGCTRL9		0x19
-#define RT946X_REG_CHGCTRL10		0x1A
-#define RT946X_REG_CHGCTRL11		0x1B
-#define RT946X_REG_CHGCTRL12		0x1C
-#define RT946X_REG_CHGCTRL13		0x1D
-#define RT946X_REG_CHGCTRL14		0x1E
-#define RT946X_REG_CHGCTRL15		0x1F
-#define RT946X_REG_CHGCTRL16		0x20
-#define RT946X_REG_CHGADC		0x21
-#define MT6370_REG_DEVICETYPE		0x22
-#define RT946X_REG_DPDM1		MT6370_REG_DEVICETYPE
-#define MT6370_REG_USBSTATUS1		0x27
-#define MT6370_REG_QCSTATUS2		0x29
-#define RT946X_REG_CHGCTRL17		0X2B
-#define RT946X_REG_CHGCTRL18		0X2C
-#define RT946X_REG_CHGHIDDENCTRL7	0x36
-#define MT6370_REG_CHGHIDDENCTRL15	0x3E
-#define RT946X_REG_CHGSTAT		0X4A
-#define RT946X_REG_CHGNTC		0X4B
-#define RT946X_REG_ADCDATAH		0X4C
-#define RT946X_REG_ADCDATAL		0X4D
-/* FLED */
-#define MT6370_REG_FLEDEN		0x7E
-/* LDO */
-#define MT6370_REG_LDOCFG		0X80
-#define MT6370_REG_LDOVOUT		0X81
-/* RGB led */
-#define MT6370_REG_RGBDIM_BASE		0x81
-#define MT6370_REG_RGB1DIM		0x82
-#define MT6370_REG_RGB2DIM		0x83
-#define MT6370_REG_RGB3DIM		0x84
-#define MT6370_REG_RGBEN		0x85
-#define MT6370_REG_RGBISNK_BASE		0x85
-#define MT6370_REG_RGB1ISNK		0x86
-#define MT6370_REG_RGB2ISNK		0x87
-#define MT6370_REG_RGB3ISNK		0x88
-#define MT6370_REG_RGBCHRINDDIM		0x92
-#define MT6370_REG_RGBCHRINDCTRL	0x93
-
-/* backlight */
-#define MT6370_BACKLIGHT_BLEN		0xA0
-#define MT6370_BACKLIGHT_BLPWM		0xA2
-#define MT6370_BACKLIGHT_BLDIM2		0xA4
-#define MT6370_BACKLIGHT_BLDIM		0xA5
-
-/* Display bias */
-#define MT6370_REG_DBCTRL1		0XB0
-#define MT6370_REG_DBCTRL2		0XB1
-#define MT6370_REG_DBVBST		0XB2
-#define MT6370_REG_DBVPOS		0XB3
-#define MT6370_REG_DBVNEG		0XB4
-#define MT6370_REG_CHGIRQ1		0xC0
-#define RT946X_REG_DPDMIRQ		0xC6
-
-/* status event */
-#define MT6370_REG_CHGSTAT1		0xD0
-#define RT946X_REG_CHGSTATC		MT6370_REG_CHGSTAT1
-#define MT6370_REG_CHGSTAT2		0xD1
-#define RT946X_REG_CHGFAULT		MT6370_REG_CHGSTAT2
-#define MT6370_REG_CHGSTAT3		0xD2
-#define MT6370_REG_CHGSTAT4		0xD3
-#define MT6370_REG_CHGSTAT5		0xD4
-#define MT6370_REG_CHGSTAT6		0xD5
-#define MT6370_REG_DPDMSTAT		0xD6
-#define MT6370_REG_DICHGSTAT		0xD7
-#define MT6370_REG_OVPCTRLSTAT		0xD8
-#define MT6370_REG_FLEDSTAT1		0xD9
-#define MT6370_REG_FLEDSTAT2		0xDA
-#define MT6370_REG_BASESTAT		0xDB
-#define MT6370_REG_LDOSTAT		0xDC
-#define MT6370_REG_RGBSTAT		0xDD
-#define MT6370_REG_BLSTAT		0xDE
-#define MT6370_REG_DBSTAT		0xDF
-/* irq mask */
-#define MT6370_REG_CHGMASK1		0xE0
-#define RT946X_REG_CHGSTATCCTRL		MT6370_REG_CHGMASK1
-#define MT6370_REG_CHGMASK2		0xE1
-#define MT6370_REG_CHGMASK3		0xE2
-#define MT6370_REG_CHGMASK4		0xE3
-#define MT6370_REG_CHGMASK5		0xE4
-#define MT6370_REG_CHGMASK6		0xE5
-#define MT6370_REG_DPDMMASK1		0xE6
-#define MT6370_REG_DICHGMASK		0xE7
-#define MT6370_REG_OVPCTRLMASK		0xE8
-#define MT6370_REG_FLEDMASK1		0xE9
-#define MT6370_REG_FLEDMASK2		0xEA
-#define MT6370_REG_BASEMASK		0xEB
-#define MT6370_REG_LDOMASK		0xEC
-#define MT6370_REG_RGBMASK		0xED
-#define MT6370_REG_BLMASK		0xEE
-#define MT6370_REG_DBMASK		0xEF
-#define MT6370_REG_TM_PAS_CODE1		0xF0
-#define MT6370_REG_BANK			0xFF
-/* TM REGISTER */
-#define MT6370_TM_REG_BL3		0x34
-#define MT6370_TM_REG_DSV1		0x37
-#else
-#error "No suitable charger option defined"
-#endif
-
-/* EOC current */
-#define RT946X_IEOC_MIN		100
-#define RT946X_IEOC_MAX		850
-#define RT946X_IEOC_STEP	50
-
-/* Minimum Input Voltage Regulator */
-#define RT946X_MIVR_MIN		3900
-#define RT946X_MIVR_MAX		13400
-#define RT946X_MIVR_STEP	100
-
-/* Boost voltage */
-#define RT946X_BOOST_VOLTAGE_MIN	4425
-#define RT946X_BOOST_VOLTAGE_MAX	5825
-#define RT946X_BOOST_VOLTAGE_STEP	25
-
-/* IR compensation resistor */
-#define RT946X_IRCMP_RES_MIN	0
-#define RT946X_IRCMP_RES_MAX	175
-#define RT946X_IRCMP_RES_STEP	25
-
-/* IR compensation voltage clamp */
-#define RT946X_IRCMP_VCLAMP_MIN		0
-#define RT946X_IRCMP_VCLAMP_MAX		224
-#define RT946X_IRCMP_VCLAMP_STEP	32
-
-/* Pre-charge mode threshold voltage */
-#define RT946X_VPREC_MIN		2000
-#define RT946X_VPREC_MAX		3500
-#define RT946X_VPREC_STEP		100
-
-/* Pre-charge current */
-#define RT946X_IPREC_MIN		100
-#define RT946X_IPREC_MAX		850
-#define RT946X_IPREC_STEP		50
-
-/* AICLVTH */
-#define RT946X_AICLVTH_MIN	4100
-#define RT946X_AICLVTH_MAX	4800
-#define RT946X_AICLVTH_STEP	100
-
-/* NTC */
-#define RT946X_BATTEMP_NORMAL	0x00
-#define RT946X_BATTEMP_WARM	0x02
-#define RT946X_BATTEMP_COOL	0x03
-#define RT946X_BATTEMP_COLD	0x05
-#define RT946X_BATTEMP_HOT	0x06
-
-/* LDO voltage */
-#define MT6370_LDO_MIN		1600
-#define MT6370_LDO_MAX		4000
-#define MT6370_LDO_STEP		200
-
-/* ========== CORECTRL0 0x00 ============ */
-#define RT946X_SHIFT_RST	7
-#define RT946X_SHIFT_CHG_RST	6
-#define RT946X_SHIFT_FLED_RST	5
-#define RT946X_SHIFT_LDO_RST	4
-#define RT946X_SHIFT_RGB_RST	3
-#define RT946X_SHIFT_BL_RST	2
-#define RT946X_SHIFT_DB_RST	1
-#define RT946X_SHIFT_REG_RST	0
-
-#define RT946X_MASK_RST		BIT(RT946X_SHIFT_RST)
-#define RT946X_MASK_CHG_RST	BIT(RT946X_SHIFT_CHG_RST)
-#define RT946X_MASK_FLED_RST	BIT(RT946X_SHIFT_FLED_RST)
-#define RT946X_MASK_LDO_RST	BIT(RT946X_SHIFT_LDO_RST)
-#define RT946X_MASK_RGB_RST	BIT(RT946X_SHIFT_RGB_RST)
-#define RT946X_MASK_BL_RST	BIT(RT946X_SHIFT_BL_RST)
-#define RT946X_MASK_DB_RST	BIT(RT946X_SHIFT_DB_RST)
-#define RT946X_MASK_REG_RST	BIT(RT946X_SHIFT_REG_RST)
-#define RT946X_MASK_SOFT_RST                                                   \
-	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST |    \
-	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |       \
-	 RT946X_MASK_REG_RST)
-
-/* ========== CHGCTRL1 0x01 ============ */
-#define RT946X_SHIFT_OPA_MODE   0
-#define RT946X_SHIFT_HZ_EN      2
-#define RT946X_SHIFT_STAT_EN	4
-
-#define RT946X_MASK_OPA_MODE	BIT(RT946X_SHIFT_OPA_MODE)
-#define RT946X_MASK_HZ_EN	BIT(RT946X_SHIFT_HZ_EN)
-#define RT946X_MASK_STAT_EN	BIT(RT946X_SHIFT_STAT_EN)
-
-/* ========== CHGCTRL2 0x02 ============ */
-#define RT946X_SHIFT_SHIP_MODE	7
-#define RT946X_SHIFT_TE		4
-#define RT946X_SHIFT_ILMTSEL	2
-#define RT946X_SHIFT_CFO_EN	1
-#define RT946X_SHIFT_CHG_EN	0
-
-#define RT946X_MASK_SHIP_MODE	BIT(RT946X_SHIFT_SHIP_MODE)
-#define RT946X_MASK_TE		BIT(RT946X_SHIFT_TE)
-#define RT946X_MASK_ILMTSEL	(0x3 << RT946X_SHIFT_ILMTSEL)
-#define RT946X_MASK_CFO_EN	BIT(RT946X_SHIFT_CFO_EN)
-#define RT946X_MASK_CHG_EN	BIT(RT946X_SHIFT_CHG_EN)
-
-/* ========== RSTPASCODE1 0x03 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE1	0xA9
-
-/* ========== CHGCTRL3 0x03 ============ */
-#define RT946X_SHIFT_AICR	2
-#define RT946X_SHIFT_ILIMEN	0
-
-#define RT946X_MASK_AICR	(0x3F << RT946X_SHIFT_AICR)
-#define RT946X_MASK_ILIMEN	BIT(RT946X_SHIFT_ILIMEN)
-
-/*
- * The accuracy of AICR is 7%.  So if AICR = 2150,
- * then Max=2150, Typ=2000, Min=1860. And plus 25 since the AICR
- * is 50ma a step.
- */
-#define RT946X_AICR_TYP2MAX(x)	((x) * 107 / 100 + 25)
-
-/* ========== RSTPASCODE2 0x04 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE2	0x96
-
-/* ========== CHGCTRL4 0x04 ============ */
-#define RT946X_SHIFT_CV	1
-
-#define RT946X_MASK_CV	0xFE
-
-/* ========== CHGCTRL5 0x05 ============ */
-#define RT946X_SHIFT_BOOST_VOLTAGE	2
-
-#define RT946X_MASK_BOOST_VOLTAGE	0xFC
-
-/* ========== CHGCTRL6 0x06 ============ */
-#define RT946X_SHIFT_MIVR	1
-
-#define RT946X_MASK_MIVR	(0x7F << RT946X_SHIFT_MIVR)
-
-/* ========== CHGCTRL7 0x07 ============ */
-#define RT946X_SHIFT_ICHG	2
-
-#define RT946X_MASK_ICHG	(0x3F << RT946X_SHIFT_ICHG)
-
-/* ========== CHGCTRL8 0x08 ============ */
-#define RT946X_SHIFT_VPREC	4
-#define RT946X_SHIFT_IPREC	0
-
-#define RT946X_MASK_VPREC	(0xF << RT946X_SHIFT_VPREC)
-#define RT946X_MASK_IPREC	(0xF << RT946X_SHIFT_IPREC)
-
-/* ========== CHGCTRL9 0x09 ============ */
-#define RT946X_SHIFT_EOC	3
-#define RT946X_SHIFT_IEOC	4
-
-#define RT946X_MASK_EOC		BIT(RT946X_SHIFT_EOC)
-#define RT946X_MASK_IEOC	(0xF << RT946X_SHIFT_IEOC)
-
-/* ========== CHGCTRL10 0x0A ============ */
-#define RT946X_SHIFT_BOOST_CURRENT	0
-
-#define RT946X_MASK_BOOST_CURRENT	0x07
-
-/* ========== CHGCTRL12 0x0C ============ */
-#define RT946X_SHIFT_TMR_EN	1
-#define MT6370_IRQ_MASK_ALL	0xFE
-
-#define RT946X_MASK_TMR_EN	BIT(RT946X_SHIFT_TMR_EN)
-
-/* ========== CHGCTRL13 0x0D ============ */
-#define RT946X_SHIFT_WDT_EN	7
-
-#define RT946X_MASK_WDT_EN	BIT(RT946X_SHIFT_WDT_EN)
-
-/* ========== CHGCTRL14 0x0E ============ */
-#define RT946X_SHIFT_AICLMEAS	7
-#define RT946X_SHIFT_AICLVTH	0
-
-#define RT946X_MASK_AICLMEAS	BIT(RT946X_SHIFT_AICLMEAS)
-#define RT946X_MASK_AICLVTH	0x07
-
-/* ========== CHGCTRL16 0x10 ============ */
-#define RT946X_SHIFT_JEITA_EN	4
-
-#define RT946X_MASK_JEITA_EN	BIT(RT946X_SHIFT_JEITA_EN)
-
-/* ========== CHGADC 0x11 ============ */
-#define RT946X_SHIFT_ADC_IN_SEL	4
-#define RT946X_SHIFT_ADC_START	0
-
-#define RT946X_MASK_ADC_IN_SEL	(0xF << RT946X_SHIFT_ADC_IN_SEL)
-#define RT946X_MASK_ADC_START	BIT(RT946X_SHIFT_ADC_START)
-
-/* ========== CHGDPDM1 0x12 (rt946x) DEVICETYPE 0x22 (mt6370) ============ */
-#define RT946X_SHIFT_USBCHGEN	7
-#define RT946X_SHIFT_DCDTIMEOUT	6
-#define RT946X_SHIFT_DCP	2
-#define RT946X_SHIFT_CDP	1
-#define RT946X_SHIFT_SDP	0
-
-#define RT946X_MASK_USBCHGEN	BIT(RT946X_SHIFT_USBCHGEN)
-#define RT946X_MASK_DCDTIMEOUT	BIT(RT946X_SHIFT_DCDTIMEOUT)
-#define RT946X_MASK_DCP		BIT(RT946X_SHIFT_DCP)
-#define RT946X_MASK_CDP		BIT(RT946X_SHIFT_CDP)
-#define RT946X_MASK_SDP		BIT(RT946X_SHIFT_SDP)
-
-#define RT946X_MASK_BC12_TYPE	(RT946X_MASK_DCP | \
-				 RT946X_MASK_CDP | \
-				 RT946X_MASK_SDP)
-
-/* ========== USBSTATUS1 0x27 (mt6370) ============ */
-#define MT6370_SHIFT_DCD_TIMEOUT 	2
-#define MT6370_SHIFT_USB_STATUS		4
-
-#define MT6370_MASK_USB_STATUS	0x70
-
-#define MT6370_CHG_TYPE_NOVBUS			0
-#define MT6370_CHG_TYPE_BUSY			1
-#define MT6370_CHG_TYPE_SDP			2
-#define MT6370_CHG_TYPE_SDPNSTD			3
-#define MT6370_CHG_TYPE_DCP			4
-#define MT6370_CHG_TYPE_CDP			5
-#define MT6370_CHG_TYPE_SAMSUNG_CHARGER		6
-#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER	7
-#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER	8
-#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER	9
-#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER	10
-
-#define MT6370_MASK_DCD_TIMEOUT		BIT(MT6370_SHIFT_DCD_TIMEOUT)
-
-/* ========== QCSTATUS2 0x29 (mt6370) ============ */
-#define MT6370_SHIFT_APP_OUT		5
-#define MT6370_SHIFT_SS_OUT		4
-#define MT6370_SHIFT_APP_REF		3
-#define MT6370_SHIFT_APP_DPDM_IN	2
-#define MT6370_SHIFT_APP_SS_PL		1
-#define MT6370_SHIFT_APP_SS_EN		0
-
-#define MT6370_MASK_APP_OUT	BIT(MT6370_SHIFT_APP_OUT)
-#define MT6370_MASK_SS_OUT	BIT(MT6370_SHIFT_SS_OUT)
-#define MT6370_MASK_APP_REF	BIT(MT6370_SHIFT_APP_REF)
-#define MT6370_MASK_APP_DPDM_IN	BIT(MT6370_SHIFT_APP_DPDM_IN)
-#define MT6370_MASK_APP_SS_PL	BIT(MT6370_SHIFT_APP_SS_PL)
-#define MT6370_MASK_APP_SS_EN	BIT(MT6370_SHIFT_APP_SS_EN)
-
-#define MT6360_MASK_CHECK_DPDM	(MT6370_MASK_APP_SS_EN | \
-				MT6370_MASK_APP_SS_PL | \
-				MT6370_MASK_APP_DPDM_IN | \
-				MT6370_MASK_APP_REF)
-
-/* ========= CHGHIDDENCTRL7 0x36 (mt6370) ======== */
-#define RT946X_ENABLE_VSYS_PROTECT		0x40
-
-#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT	5
-#define RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT \
-	(0x3 << RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT)
-
-/* ========== CHGCTRL18 0x1A ============ */
-#define RT946X_SHIFT_IRCMP_RES		3
-#define RT946X_SHIFT_IRCMP_VCLAMP	0
-
-#define RT946X_MASK_IRCMP_RES		(0x7 << RT946X_SHIFT_IRCMP_RES)
-#define RT946X_MASK_IRCMP_VCLAMP	(0x7 << RT946X_SHIFT_IRCMP_VCLAMP)
-
-/* ========== HIDDEN CTRL15 0x3E ============ */
-#define MT6370_SHIFT_ADC_TS_AUTO	0
-#define MT6370_MASK_ADC_TS_AUTO		BIT(MT6370_SHIFT_ADC_TS_AUTO)
-
-/* ========== DEVICE_ID 0x40 ============ */
-#define RT946X_MASK_VENDOR_ID	0xF0
-#define RT946X_MASK_CHIP_REV	0x0F
-
-/* ========== CHGSTAT 0x42 ============ */
-#define RT946X_SHIFT_CHG_STAT	6
-#define RT946X_SHIFT_ADC_STAT	0
-
-#define RT946X_MASK_CHG_STAT	(0x3 << RT946X_SHIFT_CHG_STAT)
-#define RT946X_MASK_ADC_STAT	BIT(RT946X_SHIFT_ADC_STAT)
-
-/* ========== CHGNTC 0x43 ============ */
-#define RT946X_SHIFT_BATNTC_FAULT	4
-
-#define RT946X_MASK_BATNTC_FAULT	0x70
-
-/* ========== CHGSTATC 0x50 (rt946x) ============ */
-#define RT946X_SHIFT_PWR_RDY    7
-
-#define RT946X_MASK_PWR_RDY     BIT(RT946X_SHIFT_PWR_RDY)
-
-/* ========== CHGFAULT 0x51 (rt946x) ============ */
-#if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_SHIFT_CHG_VSYSUV	4
-#define RT946X_SHIFT_CHG_VSYSOV	5
-#define RT946X_SHIFT_CHG_VBATOV	6
-#define RT946X_SHIFT_CHG_VBUSOV	7
-
-#define RT946X_MASK_CHG_VSYSUV	BIT(RT946X_SHIFT_CHG_VSYSUV)
-#define RT946X_MASK_CHG_VSYSOV	BIT(RT946X_SHIFT_CHG_VSYSOV)
-#define RT946X_MASK_CHG_VBATOV	BIT(RT946X_SHIFT_CHG_VBATOV)
-#define RT946X_MASK_CHG_VBUSOV	BIT(RT946X_SHIFT_CHG_VBUSOV)
-#endif
-
-/* ========== DPDMIRQ 0x56 ============ */
-#if defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370)
-#define RT946X_SHIFT_DPDMIRQ_DETACH	1
-#define RT946X_SHIFT_DPDMIRQ_ATTACH	0
-
-#define RT946X_MASK_DPDMIRQ_DETACH	BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
-#define RT946X_MASK_DPDMIRQ_ATTACH	BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
-#endif
-
-/* ========== FLED EN 0x7E (mt6370) ============ */
-#define MT6370_STROBE_EN_MASK		0x04
-
-/* ========== LDOCFG 0x80 (mt6370) ============ */
-#define MT6370_SHIFT_LDOCFG_OMS	6
-
-#define MT6370_MASK_LDOCFG_OMS		BIT(MT6370_SHIFT_LDOCFG_OMS)
-
-/* ========== LDOVOUT 0x81 (mt6370) ============ */
-#define MT6370_SHIFT_LDOVOUT_EN		7
-#define MT6370_SHIFT_LDOVOUT_VOUT	0
-
-#define MT6370_MASK_LDOVOUT_EN		BIT(MT6370_SHIFT_LDOVOUT_EN)
-#define MT6370_MASK_LDOVOUT_VOUT	(0xf << MT6370_SHIFT_LDOVOUT_VOUT)
-
-/* ========== RGBDIM 0x82/0x83/0x84 (mt6370) ============ */
-#define MT6370_LED_PWM_DIMDUTY_MIN	0x00
-#define MT6370_LED_PWM_DIMDUTY_MAX	0x1f
-
-#define MT6370_SHIFT_RGB_DIMMODE	5
-#define MT6370_SHIFT_RGB_DIMDUTY	0
-
-#define MT6370_MASK_RGB_DIMMODE		(3 << MT6370_SHIFT_RGB_DIMMODE)
-#define MT6370_MASK_RGB_DIMDUTY		(0x1f << MT6370_SHIFT_RGB_DIMDUTY)
-
-/* ========== RGBEN 0x85 (mt6370) ============ */
-#define MT6370_SHIFT_RGB_ISNK1DIM	7
-#define MT6370_SHIFT_RGB_ISNK2DIM	6
-#define MT6370_SHIFT_RGB_ISNK3DIM	5
-#define MT6370_SHIFT_RGB_ISNKDIM_BASE	8
-
-#define MT6370_MASK_RGB_ISNK1DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK1DIM)
-#define MT6370_MASK_RGB_ISNK2DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK2DIM)
-#define MT6370_MASK_RGB_ISNK3DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK3DIM)
-#define MT6370_MASK_RGB_ISNK_ALL_EN	(MT6370_MASK_RGB_ISNK1DIM_EN | \
-					 MT6370_MASK_RGB_ISNK2DIM_EN | \
-					 MT6370_MASK_RGB_ISNK3DIM_EN)
-
-/* ========== RGB_ISNK 0x86/0x87/0x88 (mt6370) ============ */
-#define MT6370_LED_BRIGHTNESS_MIN 0
-#define MT6370_LED_BRIGHTNESS_MAX 7
-
-#define MT6370_SHIFT_RGBISNK_CURSEL	0
-#define MT6370_SHIFT_RGBISNK_DIMFSEL	3
-#define MT6370_MASK_RGBISNK_CURSEL	(0x7 << MT6370_SHIFT_RGBISNK_CURSEL)
-#define MT6370_MASK_RGBISNK_DIMFSEL	(0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL)
-
-/* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_SHIFT_DB_EXT_EN		0
-#define MT6370_SHIFT_DB_PERIODIC_FIX	4
-#define MT6370_SHIFT_DB_SINGLE_PIN	5
-#define MT6370_SHIFT_DB_FREQ_PM		6
-#define MT6370_SHIFT_DB_PERIODIC_MODE	7
-
-#define MT6370_MASK_DB_EXT_EN		1
-#define MT6370_MASK_DB_PERIODIC_FIX	1
-#define MT6370_MASK_DB_SINGLE_PIN	1
-#define MT6370_MASK_DB_FREQ_PM		1
-#define MT6370_MASK_DB_PERIODIC_MODE	1
-
-/* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_MASK_DB_VNEG_DISC	BIT(2)
-#define MT6370_MASK_DB_VPOS_DISC	BIT(5)
-
-/* ========== DBVBST (mt6370) ============ */
-#define MT6370_SHIFT_DB_VBST		0
-
-#define MT6370_MASK_DB_VBST		0x3f
-
-#define MT6370_DB_VBST_MAX		6200
-#define MT6370_DB_VBST_MIN		4000
-#define MT6370_DB_VBST_STEP		50
-
-/* ========== DBVPOS (mt6370) ============ */
-#define MT6370_SHIFT_DB_VPOS		0
-
-#define MT6370_MASK_DB_VPOS		0x3f
-
-#define MT6370_DB_VPOS_MAX		6000
-#define MT6370_DB_VPOS_MIN		4000
-#define MT6370_DB_VPOS_STEP		50
-
-/* ========== DBVNEG (mt6370) ============ */
-#define MT6370_SHIFT_DB_VNEG		0
-
-#define MT6370_MASK_DB_VNEG		0x3f
-
-#define MT6370_DB_VNEG_MAX		6000
-#define MT6370_DB_VNEG_MIN		4000
-#define MT6370_DB_VNEG_STEP		50
-
-/* ========== BLEN 0xA0 (mt6370) ============ */
-#define MT6370_SHIFT_BLED_EXT_EN	7
-#define MT6370_SHIFT_BLED_EN		6
-#define MT6370_SHIFT_BLED_1CH_EN	5
-#define MT6370_SHIFT_BLED_2CH_EN	4
-#define MT6370_SHIFT_BLED_3CH_EN	3
-#define MT6370_SHIFT_BLED_4CH_EN	2
-#define MT6370_SHIFT_BLED_CODE		1
-#define MT6370_SHIFT_BLED_CONFIG	0
-
-#define MT6370_MASK_BLED_EXT_EN		BIT(MT6370_SHIFT_BLED_EXT_EN)
-#define MT6370_MASK_BLED_EN		BIT(MT6370_SHIFT_BLED_EN)
-#define MT6370_MASK_BLED_1CH_EN		BIT(MT6370_SHIFT_BLED_1CH_EN)
-#define MT6370_MASK_BLED_2CH_EN		BIT(MT6370_SHIFT_BLED_2CH_EN)
-#define MT6370_MASK_BLED_3CH_EN		BIT(MT6370_SHIFT_BLED_3CH_EN)
-#define MT6370_MASK_BLED_4CH_EN		BIT(MT6370_SHIFT_BLED_4CH_EN)
-
-#define MT6370_BLED_CODE_LINEAR		BIT(MT6370_SHIFT_BLED_CODE)
-#define MT6370_BLED_CODE_EXP		0
-
-#define MT6370_BLED_CONFIG_ACTIVE_HIGH	BIT(MT6370_SHIFT_BLED_CONFIG)
-#define MT6370_BLED_CONFIG_ACTIVE_LOW	0
-
-/* ========== BLPWM 0xA2 (mt6370) ============ */
-#define MT6370_SHIFT_BLPWM_BLED_PWM	7
-
-#define MT6370_MASK_BLPWM_BLED_PWM	BIT(MT6370_SHIFT_BLPWM_BLED_PWM)
-
-/* ========== BLDIM2 0xA4 (mt6370) ============ */
-#define MT6370_MASK_BLDIM2		0x7
-
-/* ========== BLDIM 0xA5 (mt6370) ============ */
-#define MT6370_SHIFT_BLDIM_MSB		3
-#define MT6370_MASK_BLDIM		0xff
-
-#define MT6370_BLDIM_DEFAULT		0x7ff
-
-/* ========== CHG_IRQ1 0xC0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_EVT		6
-#define MT6370_MASK_MIVR_EVT		BIT(MT6370_SHIFT_MIVR_EVT)
-
-/* ========== CHGSTAT2 0xD0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_STAT		6
-
-/* ========== CHGSTAT2 0xD1 (mt6370) ============ */
-#ifdef CONFIG_CHARGER_MT6370
-#define MT6370_SHIFT_CHG_VBUSOV_STAT	7
-#define MT6370_SHIFT_CHG_VBATOV_STAT	6
-
-#define RT946X_MASK_CHG_VBATOV		MT6370_SHIFT_CHG_VBATOV_STAT
-
-#define MT6370_MASK_CHG_VBUSOV_STAT	BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
-#define MT6370_MASK_CHG_VBATOV_STAT	BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
-#endif
-
-/* ========== TM PAS CODE1 0xF0 (mt6370) ============ */
-#define MT6370_LEAVE_TM			0x00
-
-/* ========== BANK REG 0xFF (mt6370) ============ */
-#define MT6370_MASK_REG_TM		0x69
-
-/* ========== TM REG 0x34 (mt6370) ============ */
-#define MT6370_TM_MASK_BL3_SL		0xC0
-#define MT6370_TM_REDUCE_BL3_SL		0xC0
-
-/* ========== TM REG 0x37 (mt6370) ============ */
-#define MT6370_TM_MASK_DSV1_SL		0xC0
-#define MT6370_TM_REDUCE_DSV1_SL	0x00
-
-/* ADC unit/offset */
-#define MT6370_ADC_UNIT_VBUS_DIV5	25000	/* uV */
-#define MT6370_ADC_UNIT_VBUS_DIV2	10000	/* uV */
-#define MT6370_ADC_UNIT_VSYS		5000	/* uV */
-#define MT6370_ADC_UNIT_VBAT		5000	/* uV */
-#define MT6370_ADC_UNIT_TS_BAT		25	/* 0.01% */
-#define MT6370_ADC_UNIT_IBUS		50000	/* uA */
-#define MT6370_ADC_UNIT_IBAT		50000	/* uA */
-#define MT6370_ADC_UNIT_CHG_VDDP	5000	/* uV */
-#define MT6370_ADC_UNIT_TEMP_JC		2	/* degree */
-
-#define MT6370_ADC_OFFSET_VBUS_DIV5	0	/* mV */
-#define MT6370_ADC_OFFSET_VBUS_DIV2	0	/* mV */
-#define MT6370_ADC_OFFSET_VSYS		0	/* mV */
-#define MT6370_ADC_OFFSET_VBAT		0	/* mV */
-#define MT6370_ADC_OFFSET_TS_BAT	0	/* % */
-#define MT6370_ADC_OFFSET_IBUS		0	/* mA */
-#define MT6370_ADC_OFFSET_IBAT		0	/* mA */
-#define MT6370_ADC_OFFSET_CHG_VDDP	0	/* mV */
-#define MT6370_ADC_OFFSET_TEMP_JC	(-40)	/* degree */
-
-/* ========== Variant-specific configuration ============ */
-#if defined(CONFIG_CHARGER_RT9466)
-	#define RT946X_CHARGER_NAME	"rt9466"
-	#define RT946X_VENDOR_ID	0x80
-	#define RT946X_ADDR_FLAGS	0x53
-#elif defined(CONFIG_CHARGER_RT9467)
-	#define RT946X_CHARGER_NAME	"rt9467"
-	#define RT946X_VENDOR_ID	0x90
-	#define RT946X_ADDR_FLAGS	0x5B
-#elif defined(CONFIG_CHARGER_MT6370)
-	#define RT946X_CHARGER_NAME	"mt6370"
-	#define RT946X_VENDOR_ID	0xE0
-	#define RT946X_ADDR_FLAGS	0x34
-#else
-	#error "No suitable charger option defined"
-#endif
-
-/* RT946x specific interface functions */
-
-/* Power on reset */
-int rt946x_por_reset(void);
-
-/* Interrupt handler for rt946x */
-void rt946x_interrupt(enum gpio_signal signal);
-
-/* Enable/Disable rt946x (in charger or boost mode) */
-int rt946x_enable_charger_boost(int en);
-
-/*
- * Return 1 if VBUS is ready, which means
- * UVLO < VBUS < VOVP && VBUS > BATS + VSLP
- */
-int rt946x_is_vbus_ready(void);
-
-/* Return 1 if rt946x triggers charge termination due to full charge. */
-int rt946x_is_charge_done(void);
-
-/*
- * Cut off the battery (force BATFET to turn off).
- * Return 0 if it succeeds.
- */
-int rt946x_cutoff_battery(void);
-
-/* Enable/Disable charge temination */
-int rt946x_enable_charge_termination(int en);
-
-/* Enable/Disable charge EOC */
-int rt946x_enable_charge_eoc(int en);
-
-enum rt946x_adc_in_sel {
-	RT946X_ADC_VBUS_DIV5 = 1,
-	RT946X_ADC_VBUS_DIV2,
-	MT6370_ADC_TS_BAT = 6,
-	MT6370_ADC_IBUS = 8,
-	MT6370_ADC_TEMP_JC = 12,
-	MT6370_ADC_MAX,
-};
-
-/**
- * Read ADC channels
- *
- * @param adc_sel The ADC channel
- * @param adc_val The read value
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val);
-
-/**
- * Toggle BC12 detection
- *
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int rt946x_toggle_bc12_detection(void);
-
-struct rt946x_init_setting {
-	uint16_t eoc_current;
-	uint16_t mivr;
-	uint16_t ircmp_vclamp;
-	uint16_t ircmp_res;
-	uint16_t boost_voltage;
-	uint16_t boost_current;
-};
-
-#ifdef CONFIG_CHARGER_MT6370
-
-/*
- * Set LDO voltage.
- * Disable LDO if voltage is zero.
- */
-int mt6370_set_ldo_voltage(int mv);
-
-enum mt6370_led_index {
-	MT6370_LED_ID_OFF = 0,
-	MT6370_LED_ID1 = 1,
-	MT6370_LED_ID2 = 2,
-	MT6370_LED_ID3 = 3,
-	MT6370_LED_ID_COUNT, /* The bound of the ID indexes. */
-};
-
-enum mt6370_led_dim_mode {
-	MT6370_LED_DIM_MODE_PWM = 0,
-	MT6370_LED_DIM_MODE_BREATH = 1,
-	MT6370_LED_DIM_MODE_REGISTER = 3
-};
-
-enum mt6370_led_pwm_freq {
-	MT6370_LED_PWM_FREQ01 = 0, /* 0.1 Hz */
-	MT6370_LED_PWM_FREQ02 = 1, /* 0.2 Hz */
-	MT6370_LED_PWM_FREQ05 = 2, /* 0.5 Hz */
-	MT6370_LED_PWM_FREQ1 = 3, /* 1 Hz */
-	MT6370_LED_PWM_FREQ2 = 4, /* 2 Hz */
-	MT6370_LED_PWM_FREQ5 = 5, /* 5 Hz */
-	MT6370_LED_PWM_FREQ200 = 6, /* 200 Hz */
-	MT6370_LED_PWM_FREQ1000 = 7 /* 1000 Hz */
-};
-
-/* Enable display bias external pin control. */
-int mt6370_db_external_control(int en);
-
-/**
- * Set backlight LED dim.
- *
- * dim: A value from 0 to 2047.
- * return: EC_SUCCESS on success, and EC_ERROR_* otherwise.
- */
-int mt6370_backlight_set_dim(uint16_t dim);
-
-/**
- * MT6370 display bias voltage settings.
- *
- * Set disaply bias voltages for the panel.
- *
- * vbst: VBST config in mv.
- * vpos: VPOS config in mv.
- * vneg: VNEG config in mv.
- * return: EC_SUCCESS on succes, and EC_ERROR_* otherwise.
- */
-int mt6370_db_set_voltages(int vbst, int vpos, int vneg);
-
-/* Set LED brightness */
-int mt6370_led_set_brightness(enum mt6370_led_index index, uint8_t brightness);
-
-/**
- * Set LED Color
- *
- * mask: Bitmap indicating 1=on 0=off for each LED. 000 = all off.
- *       Combination of MT6370_MASK_RGB_ISNK1/2/3DIM_EN.
- * return: EC_SUCCESS or EC_ERROR_* on error.
- */
-int mt6370_led_set_color(uint8_t mask);
-
-/* Set LED dim mode, available modes: REGISTER, PWM, BREATH. */
-int mt6370_led_set_dim_mode(enum mt6370_led_index index,
-			    enum mt6370_led_dim_mode mode);
-
-/* Set LED PWM mode duty */
-int mt6370_led_set_pwm_dim_duty(enum mt6370_led_index index, uint8_t dim_duty);
-
-/* Set LED PWM mode frequency */
-int mt6370_led_set_pwm_frequency(enum mt6370_led_index index,
-				 enum mt6370_led_pwm_freq freq);
-
-/* Reduce mt6370 DB and BL driving capacity */
-int mt6370_reduce_db_bl_driving(void);
-#endif
-
-extern const struct charger_drv rt946x_drv;
-extern const struct bc12_drv rt946x_bc12_drv;
-
-#endif /* __CROS_EC_RT946X_H */
diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c
deleted file mode 100644
index 460dcf4093..0000000000
--- a/driver/charger/sm5803.c
+++ /dev/null
@@ -1,1933 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Silicon Mitus SM5803 Buck-Boost Charger
- */
-#include "atomic.h"
-#include "battery.h"
-#include "battery_smart.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "sm5803.h"
-#include "system.h"
-#include "stdbool.h"
-#include "throttle_ap.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usbc_ocp.h"
-#include "util.h"
-#include "watchdog.h"
-
-#ifndef CONFIG_CHARGER_NARROW_VDC
-#error "SM5803 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
-#endif
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-#define UNKNOWN_DEV_ID -1
-static int dev_id = UNKNOWN_DEV_ID;
-
-static const struct charger_info sm5803_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
-	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
-	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
-	.input_current_step = INPUT_I_STEP,
-};
-
-static uint32_t irq_pending; /* Bitmask of chips with interrupts pending */
-
-static struct mutex flow1_access_lock[CHARGER_NUM];
-static struct mutex flow2_access_lock[CHARGER_NUM];
-
-static int charger_vbus[CHARGER_NUM];
-
-/* Tracker for charging failures per port */
-struct {
-	int count;
-	timestamp_t time;
-} failure_tracker[CHARGER_NUM] = {};
-
-/* Port to restart charging on */
-static int active_restart_port = CHARGE_PORT_NONE;
-
-/*
- * If powered from the sub board port, we need to attempt to enable the BFET
- * before proceeding with charging.
- */
-static int attempt_bfet_enable;
-
-/*
- * Note if auto fast charge for the primary port is disabled due to a
- * disconnected battery, at re-enable auto fast charge later when the battery
- * has connected.
- */
-static bool fast_charge_disabled;
-
-
-#define CHARGING_FAILURE_MAX_COUNT	5
-#define CHARGING_FAILURE_INTERVAL	MINUTE
-
-static int sm5803_is_sourcing_otg_power(int chgnum, int port);
-static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id);
-static enum ec_error_list sm5803_set_current(int chgnum, int current);
-
-static inline enum ec_error_list chg_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
-}
-
-static inline enum ec_error_list chg_write8(int chgnum, int offset, int value)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
-}
-
-static inline enum ec_error_list meas_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
-			 offset, value);
-}
-
-static inline enum ec_error_list meas_write8(int chgnum, int offset, int value)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
-			 offset, value);
-}
-
-static inline enum ec_error_list main_read8(int chgnum, int offset, int *value)
-{
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
-			 offset, value);
-}
-
-static inline enum ec_error_list main_write8(int chgnum, int offset, int value)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
-			 offset, value);
-}
-
-static inline enum ec_error_list test_write8(int chgnum, int offset, int value)
-{
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_TEST_FLAGS,
-			 offset, value);
-}
-
-static inline enum ec_error_list test_update8(int chgnum, const int offset,
-					      const uint8_t mask,
-					const enum mask_update_action action)
-{
-	return i2c_update8(chg_chips[chgnum].i2c_port,
-			   SM5803_ADDR_TEST_FLAGS, offset, mask, action);
-}
-
-static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
-{
-	int rv;
-
-	/* Safety checks done, onto the actual register update */
-	mutex_lock(&flow1_access_lock[chgnum]);
-
-	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW1,
-			 mask, action);
-
-	mutex_unlock(&flow1_access_lock[chgnum]);
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_flow2_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
-{
-	int rv;
-
-	mutex_lock(&flow2_access_lock[chgnum]);
-
-	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW2,
-			 mask, action);
-
-	mutex_unlock(&flow2_access_lock[chgnum]);
-
-	return rv;
-}
-
-static bool is_platform_id_2s(uint32_t platform_id)
-{
-	return platform_id >= 0x06 && platform_id <= 0x0D;
-}
-
-static bool is_platform_id_3s(uint32_t platform_id)
-{
-	return platform_id >= 0x0E && platform_id <= 0x16;
-}
-
-int sm5803_is_vbus_present(int chgnum)
-{
-	return charger_vbus[chgnum];
-}
-
-enum ec_error_list sm5803_configure_gpio0(int chgnum,
-					  enum sm5803_gpio0_modes mode, int od)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_GPIO0_CTRL, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~SM5803_GPIO0_MODE_MASK;
-	reg |= mode << 1;
-
-	if (od)
-		reg |= SM5803_GPIO0_OPEN_DRAIN_EN;
-	else
-		reg &= ~SM5803_GPIO0_OPEN_DRAIN_EN;
-
-	rv = main_write8(chgnum, SM5803_REG_GPIO0_CTRL, reg);
-	return rv;
-}
-
-enum ec_error_list sm5803_set_gpio0_level(int chgnum, int level)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_GPIO0_CTRL, &reg);
-	if (rv)
-		return rv;
-
-	if (level)
-		reg |= SM5803_GPIO0_VAL;
-	else
-		reg &= ~SM5803_GPIO0_VAL;
-
-	rv = main_write8(chgnum, SM5803_REG_GPIO0_CTRL, reg);
-	return rv;
-}
-
-enum ec_error_list sm5803_configure_chg_det_od(int chgnum, int enable)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_GPIO0_CTRL, &reg);
-	if (rv)
-		return rv;
-
-	if (enable)
-		reg |= SM5803_CHG_DET_OPEN_DRAIN_EN;
-	else
-		reg &= ~SM5803_CHG_DET_OPEN_DRAIN_EN;
-
-	rv = main_write8(chgnum, SM5803_REG_GPIO0_CTRL, reg);
-	return rv;
-}
-
-enum ec_error_list sm5803_get_chg_det(int chgnum, int *chg_det)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_STATUS1, &reg);
-	if (rv)
-		return rv;
-
-	*chg_det = (reg & SM5803_STATUS1_CHG_DET) != 0;
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list sm5803_set_vbus_disch(int chgnum, int enable)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_PORTS_CTRL, &reg);
-	if (rv)
-		return rv;
-
-	if (enable)
-		reg |= SM5803_PORTS_VBUS_DISCH;
-	else
-		reg &= ~SM5803_PORTS_VBUS_DISCH;
-
-	rv = main_write8(chgnum, SM5803_REG_PORTS_CTRL, reg);
-	return rv;
-}
-
-enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
-{
-	enum ec_error_list rv;
-	int regval;
-
-	rv = sm5803_get_dev_id(chgnum, &dev_id);
-	if (rv)
-		return rv;
-
-	if (enable) {
-		if (chgnum == CHARGER_PRIMARY) {
-			/* Magic for new silicon */
-			if (dev_id >= 3) {
-				rv |= main_write8(chgnum, 0x1F, 0x1);
-				rv |= test_write8(chgnum, 0x44, 0x2);
-				rv |= main_write8(chgnum, 0x1F, 0);
-			}
-			/*
-			 * Only enable auto fast charge when a battery is
-			 * connected and out of cutoff.
-			 */
-			if (battery_get_disconnect_state() ==
-			    BATTERY_NOT_DISCONNECTED) {
-				rv = sm5803_flow2_update(chgnum,
-						 SM5803_FLOW2_AUTO_ENABLED,
-						 MASK_SET);
-				fast_charge_disabled = false;
-			} else {
-				rv = sm5803_flow2_update(chgnum,
-						SM5803_FLOW2_AUTO_TRKL_EN |
-						SM5803_FLOW2_AUTO_PRECHG_EN,
-						MASK_SET);
-				fast_charge_disabled = true;
-			}
-		} else {
-			if (dev_id >= 3) {
-				/* Touch of magic on the primary charger */
-				rv |= main_write8(CHARGER_PRIMARY, 0x1F, 0x1);
-				rv |= test_write8(CHARGER_PRIMARY, 0x44, 0x20);
-				rv |= main_write8(CHARGER_PRIMARY, 0x1F, 0x0);
-
-				/*
-				 * Disable linear, pre-charge, and linear fast
-				 * charge for primary charger.
-				 */
-				rv = chg_read8(CHARGER_PRIMARY,
-					       SM5803_REG_FLOW3, &regval);
-				regval &= ~(BIT(6) | BIT(5) | BIT(4));
-
-				rv |= chg_write8(CHARGER_PRIMARY,
-						 SM5803_REG_FLOW3, regval);
-			}
-		}
-
-		/* Last but not least, enable sinking */
-		rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK, MASK_SET);
-	} else {
-		if (chgnum == CHARGER_PRIMARY)
-			rv |= sm5803_flow2_update(chgnum,
-						  SM5803_FLOW2_AUTO_ENABLED,
-						  MASK_CLR);
-
-		if (chgnum == CHARGER_SECONDARY) {
-			rv |= sm5803_flow1_update(CHARGER_PRIMARY,
-						  SM5803_FLOW1_LINEAR_CHARGE_EN,
-						  MASK_CLR);
-
-			rv = chg_read8(CHARGER_PRIMARY, SM5803_REG_FLOW3,
-				       &regval);
-			regval &= ~(BIT(6) | BIT(5) | BIT(4));
-			rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FLOW3,
-					 regval);
-		}
-
-
-		/* Disable sink mode, unless currently sourcing out */
-		if (!sm5803_is_sourcing_otg_power(chgnum, chgnum))
-			rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK,
-						  MASK_CLR);
-	}
-
-	return rv;
-
-}
-
-/*
- * Track and store whether we've initialized the charger chips already on this
- * boot.  This should prevent us from re-running inits after sysjumps.
- */
-static bool chip_inited[CHARGER_NUM];
-#define SM5803_SYSJUMP_TAG	0x534D /* SM */
-#define SM5803_HOOK_VERSION	1
-
-static void init_status_preserve(void)
-{
-	system_add_jump_tag(SM5803_SYSJUMP_TAG, SM5803_HOOK_VERSION,
-			    sizeof(chip_inited), &chip_inited);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, init_status_preserve, HOOK_PRIO_DEFAULT);
-
-static void init_status_retrieve(void)
-{
-	const uint8_t *tag_contents;
-	int version, size;
-
-	tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG,
-						  &version, &size);
-	if (tag_contents && (version == SM5803_HOOK_VERSION) &&
-					(size == sizeof(chip_inited)))
-		/* Valid init status found, restore before charger chip init */
-		memcpy(&chip_inited, tag_contents, size);
-}
-DECLARE_HOOK(HOOK_INIT, init_status_retrieve, HOOK_PRIO_FIRST);
-
-static void sm5803_init(int chgnum)
-{
-	enum ec_error_list rv;
-	int reg;
-	int vbus_mv;
-	const struct battery_info *batt_info;
-	int pre_term;
-	int cells;
-
-	/*
-	 * If a charger is not currently present, disable switching per OCPC
-	 * requirements
-	 */
-	rv = charger_get_vbus_voltage(chgnum, &vbus_mv);
-	if (rv == EC_SUCCESS) {
-		if (vbus_mv < 4000) {
-			/*
-			 * No charger connected, disable CHG_EN
-			 * (note other bits default to 0)
-			 */
-			rv = chg_write8(chgnum, SM5803_REG_FLOW1, 0);
-		} else if (!sm5803_is_sourcing_otg_power(chgnum, chgnum)) {
-			charger_vbus[chgnum] = 1;
-		}
-	} else {
-		CPRINTS("%s %d: Failed to read VBUS voltage during init",
-			CHARGER_NAME, chgnum);
-		return;
-	}
-
-	/*
-	 * A previous boot already ran inits, safe to return now that we've
-	 * checked i2c communication to the chip and cached Vbus presence
-	 */
-	if (chip_inited[chgnum]) {
-		CPRINTS("%s %d: Already initialized", CHARGER_NAME, chgnum);
-		return;
-	}
-
-	rv |= charger_device_id(&reg);
-	if (reg == 0x02) {
-		/* --- Special register init ---
-		 * For early silicon (ID 2) with 3S batteries
-		 */
-		rv |= main_write8(chgnum, 0x20, 0x08);
-		rv |= main_write8(chgnum, 0x30, 0xC0);
-		rv |= main_write8(chgnum, 0x80, 0x01);
-
-		rv |= meas_write8(chgnum, 0x08, 0xC2);
-
-		rv |= chg_write8(chgnum, 0x1D, 0x40);
-		rv |= chg_write8(chgnum, 0x1F, 0x09);
-
-		rv |= chg_write8(chgnum, 0x22, 0xB3);
-		rv |= chg_write8(chgnum, 0x23, 0x81);
-		rv |= chg_write8(chgnum, 0x28, 0xB7);
-
-		rv |= chg_write8(chgnum, 0x4A, 0x82);
-		rv |= chg_write8(chgnum, 0x4B, 0xA3);
-		rv |= chg_write8(chgnum, 0x4C, 0xA8);
-		rv |= chg_write8(chgnum, 0x4D, 0xCA);
-		rv |= chg_write8(chgnum, 0x4E, 0x07);
-		rv |= chg_write8(chgnum, 0x4F, 0xFF);
-
-		rv |= chg_write8(chgnum, 0x50, 0x98);
-		rv |= chg_write8(chgnum, 0x51, 0x00);
-		rv |= chg_write8(chgnum, 0x52, 0x77);
-		rv |= chg_write8(chgnum, 0x53, 0xD2);
-		rv |= chg_write8(chgnum, 0x54, 0x02);
-		rv |= chg_write8(chgnum, 0x55, 0xD1);
-		rv |= chg_write8(chgnum, 0x56, 0x7F);
-		rv |= chg_write8(chgnum, 0x57, 0x02);
-		rv |= chg_write8(chgnum, 0x58, 0xD1);
-		rv |= chg_write8(chgnum, 0x59, 0x7F);
-		rv |= chg_write8(chgnum, 0x5A, 0x13);
-		rv |= chg_write8(chgnum, 0x5B, 0x50);
-		rv |= chg_write8(chgnum, 0x5C, 0x5B);
-		rv |= chg_write8(chgnum, 0x5D, 0xB0);
-		rv |= chg_write8(chgnum, 0x5E, 0x3C);
-		rv |= chg_write8(chgnum, 0x5F, 0x3C);
-
-		rv |= chg_write8(chgnum, 0x60, 0x44);
-		rv |= chg_write8(chgnum, 0x61, 0x20);
-		rv |= chg_write8(chgnum, 0x65, 0x35);
-		rv |= chg_write8(chgnum, 0x66, 0x29);
-		rv |= chg_write8(chgnum, 0x67, 0x64);
-		rv |= chg_write8(chgnum, 0x68, 0x88);
-		rv |= chg_write8(chgnum, 0x69, 0xC7);
-
-		/* Inits to access page 0x37 and enable trickle charging */
-		rv |= main_write8(chgnum, 0x1F, 0x01);
-		rv |= test_update8(chgnum, 0x8E, BIT(5), MASK_SET);
-		rv |= main_write8(chgnum, 0x1F, 0x00);
-	} else if (reg == 0x03) {
-		uint32_t platform_id;
-
-		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
-		if (rv) {
-			CPRINTS("%s %d: Failed to read platform during init",
-							CHARGER_NAME, chgnum);
-			return;
-		}
-		platform_id &= SM5803_PLATFORM_ID;
-
-		if (is_platform_id_3s(platform_id)) {
-			/* 3S Battery inits */
-			/* set 13.3V VBAT_SNSP TH GPADC THRESHOLD*/
-			rv |= meas_write8(chgnum, 0x26,
-				SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
-			/* OV_VBAT HW second level (14.1V) */
-			rv |= chg_write8(chgnum, 0x21,
-				SM5803_VBAT_PWR_MINTH_3S_LEVEL);
-			rv |= main_write8(chgnum, 0x30, 0xC0);
-			rv |= main_write8(chgnum, 0x80, 0x01);
-			rv |= main_write8(chgnum, 0x1A, 0x08);
-
-			rv |= meas_write8(chgnum, 0x08, 0xC2);
-
-			rv |= chg_write8(chgnum, 0x1D, 0x40);
-
-			rv |= chg_write8(chgnum, 0x22, 0xB3);
-
-			rv |= chg_write8(chgnum, 0x3E, 0x3C);
-
-			rv |= chg_write8(chgnum, 0x4B, 0xA6);
-			rv |= chg_write8(chgnum, 0x4F, 0xBF);
-
-			rv |= chg_write8(chgnum, 0x52, 0x77);
-			rv |= chg_write8(chgnum, 0x53, 0xD2);
-			rv |= chg_write8(chgnum, 0x54, 0x02);
-			rv |= chg_write8(chgnum, 0x55, 0xD1);
-			rv |= chg_write8(chgnum, 0x56, 0x7F);
-			rv |= chg_write8(chgnum, 0x57, 0x01);
-			rv |= chg_write8(chgnum, 0x58, 0x50);
-			rv |= chg_write8(chgnum, 0x59, 0x7F);
-			rv |= chg_write8(chgnum, 0x5A, 0x13);
-			rv |= chg_write8(chgnum, 0x5B, 0x50);
-			rv |= chg_write8(chgnum, 0x5D, 0xB0);
-
-			rv |= chg_write8(chgnum, 0x60, 0x44);
-			rv |= chg_write8(chgnum, 0x65, 0x35);
-			rv |= chg_write8(chgnum, 0x66, 0x29);
-
-			rv |= chg_write8(chgnum, 0x7D, 0x67);
-			rv |= chg_write8(chgnum, 0x7E, 0x04);
-
-			rv |= chg_write8(chgnum, 0x33, 0x3C);
-
-			rv |= chg_write8(chgnum, 0x5C, 0x7A);
-		} else if (is_platform_id_2s(platform_id)) {
-			/* 2S Battery inits */
-
-			/*
-			 * Set 9V as higher threshold for VBATSNSP_MAX_TH GPADC
-			 * threshold for interrupt generation.
-			 */
-			rv |= meas_write8(chgnum, 0x26,
-				SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
-
-			/* Set OV_VBAT HW second level threshold as 9.4V */
-			rv |= chg_write8(chgnum, 0x21,
-				SM5803_VBAT_PWR_MINTH_2S_LEVEL);
-
-			rv |= main_write8(chgnum, 0x30, 0xC0);
-			rv |= main_write8(chgnum, 0x80, 0x01);
-			rv |= main_write8(chgnum, 0x1A, 0x08);
-
-			rv |= meas_write8(chgnum, 0x08, 0xC2);
-
-			rv |= chg_write8(chgnum, 0x1D, 0x40);
-
-			rv |= chg_write8(chgnum, 0x22, 0xB3);
-
-			rv |= chg_write8(chgnum, 0x3E, 0x3C);
-
-			rv |= chg_write8(chgnum, 0x4F, 0xBF);
-
-			rv |= chg_write8(chgnum, 0x52, 0x77);
-			rv |= chg_write8(chgnum, 0x53, 0xD2);
-			rv |= chg_write8(chgnum, 0x54, 0x02);
-			rv |= chg_write8(chgnum, 0x55, 0xD1);
-			rv |= chg_write8(chgnum, 0x56, 0x7F);
-			rv |= chg_write8(chgnum, 0x57, 0x01);
-			rv |= chg_write8(chgnum, 0x58, 0x50);
-			rv |= chg_write8(chgnum, 0x59, 0x7F);
-			rv |= chg_write8(chgnum, 0x5A, 0x13);
-			rv |= chg_write8(chgnum, 0x5B, 0x52);
-			rv |= chg_write8(chgnum, 0x5D, 0xD0);
-
-			rv |= chg_write8(chgnum, 0x60, 0x44);
-			rv |= chg_write8(chgnum, 0x65, 0x35);
-			rv |= chg_write8(chgnum, 0x66, 0x29);
-
-			rv |= chg_write8(chgnum, 0x7D, 0x97);
-			rv |= chg_write8(chgnum, 0x7E, 0x07);
-
-			rv |= chg_write8(chgnum, 0x33, 0x3C);
-
-			rv |= chg_write8(chgnum, 0x5C, 0x7A);
-		}
-
-		rv |= chg_write8(chgnum, 0x73, 0x22);
-		rv |= chg_write8(chgnum, 0x50, 0x88);
-		rv |= chg_read8(chgnum, 0x34, &reg);
-		reg |= BIT(7);
-		rv |= chg_write8(chgnum, 0x34, reg);
-		rv |= main_write8(chgnum, 0x1F, 0x1);
-		rv |= test_write8(chgnum, 0x43, 0x10);
-		rv |= test_write8(chgnum, 0x47, 0x10);
-		rv |= test_write8(chgnum, 0x48, 0x04);
-		rv |= main_write8(chgnum, 0x1F, 0x0);
-	}
-
-	/* Enable LDO bits */
-	rv |= main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	reg &= ~(BIT(0) | BIT(1));
-	rv |= main_write8(chgnum, SM5803_REG_REFERENCE, reg);
-
-	/* Set a higher clock speed in case it was lowered for z-state */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/*
-	 * Turn on GPADCs to default.  Enable the IBAT_CHG ADC in order to
-	 * measure battery current and calculate system resistance.
-	 */
-	reg = SM5803_GPADCC1_TINT_EN     |
-	      SM5803_GPADCC1_VSYS_EN     |
-	      SM5803_GPADCC1_VCHGPWR_EN  |
-	      SM5803_GPADCC1_VBUS_EN     |
-	      SM5803_GPADCC1_IBAT_CHG_EN |
-	      SM5803_GPADCC1_IBAT_DIS_EN |
-	      SM5803_GPADCC1_VBATSNSP_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, reg);
-
-	/* Enable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
-	reg |= SM5803_PSYS1_DAC_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
-
-	/* Enable ADC sigma delta */
-	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
-	reg |= SM5803_CC_CONFIG1_SD_PWRUP;
-	rv |= chg_write8(chgnum, SM5803_REG_CC_CONFIG1, reg);
-
-	/* Enable PROCHOT comparators except Ibus */
-	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
-	reg |= SM5803_PHOT1_COMPARATOR_EN;
-	reg &= ~SM5803_PHOT1_IBUS_PHOT_COMP_EN;
-	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
-
-	/* Set DPM Voltage to 4200 mv, see b:172173517 */
-	reg = SM5803_VOLTAGE_TO_REG(4200);
-	rv = chg_write8(chgnum, SM5803_REG_DPM_VL_SET_MSB, (reg >> 3));
-	rv |= chg_write8(chgnum, SM5803_REG_DPM_VL_SET_LSB, (reg & 0x7));
-
-	/* Set default input current */
-	reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT)
-		& SM5803_CHG_ILIM_RAW;
-	rv |= chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg);
-
-	/* Configure charger insertion interrupts */
-	rv |= main_write8(chgnum, SM5803_REG_INT1_EN, SM5803_INT1_CHG);
-	/* Enable end of charge interrupts for logging */
-	rv |= main_write8(chgnum, SM5803_REG_INT4_EN, SM5803_INT4_CHG_FAIL |
-						      SM5803_INT4_CHG_DONE |
-						      SM5803_INT4_OTG_FAIL);
-
-	/* Set TINT interrupts for higher threshold 360 K */
-	rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-						SM5803_TINT_HIGH_LEVEL);
-	/*
-	 * Set TINT interrupts for lower threshold to 0 when not
-	 * throttled to prevent trigger interrupts continually
-	 */
-	rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-						SM5803_TINT_MIN_LEVEL);
-
-	/*
-	 * Configure VBAT_SNSP high interrupt to fire after thresholds are set.
-	 */
-	rv |= main_read8(chgnum, SM5803_REG_INT2_EN, &reg);
-	reg |= SM5803_INT2_VBATSNSP;
-	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, reg);
-
-
-	/* Configure TINT interrupts to fire after thresholds are set */
-	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, SM5803_INT2_TINT);
-
-	/*
-	 * Configure CHG_ENABLE to only be set through I2C by setting
-	 * HOST_MODE_EN bit (all other register bits are 0 by default)
-	 */
-	rv |= chg_write8(chgnum, SM5803_REG_FLOW2, SM5803_FLOW2_HOST_MODE_EN);
-
-	if (chgnum == CHARGER_PRIMARY) {
-		int ibat_eoc_ma;
-
-		/* Set end of fast charge threshold */
-		batt_info = battery_get_info();
-		ibat_eoc_ma = batt_info->precharge_current - 50;
-		ibat_eoc_ma /= 100;
-		ibat_eoc_ma = CLAMP(ibat_eoc_ma, 0, SM5803_CONF5_IBAT_EOC_TH);
-		rv |= chg_read8(chgnum, SM5803_REG_FAST_CONF5, &reg);
-		reg &= ~SM5803_CONF5_IBAT_EOC_TH;
-		reg |= ibat_eoc_ma;
-		rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FAST_CONF5, reg);
-
-		/* Setup the proper precharge thresholds. */
-		cells = batt_info->voltage_max / 4;
-		pre_term = batt_info->voltage_min / cells;
-		pre_term /= 100; /* Convert to decivolts. */
-		pre_term = CLAMP(pre_term, SM5803_VBAT_PRE_TERM_MIN_DV,
-				 SM5803_VBAT_PRE_TERM_MAX_DV);
-		pre_term -= SM5803_VBAT_PRE_TERM_MIN_DV; /* Convert to regval */
-
-		rv |= chg_read8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, &reg);
-		reg &= ~SM5803_VBAT_PRE_TERM;
-		reg |= pre_term << SM5803_VBAT_PRE_TERM_SHIFT;
-		rv |= chg_write8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, reg);
-
-		/*
-		 * Set up precharge current
-		 * Note it is preferred to under-shoot the precharge current
-		 * requested. Upper bits of this register are read/write 1 to
-		 * clear
-		 */
-		reg = SM5803_CURRENT_TO_REG(batt_info->precharge_current);
-		reg = MIN(reg, SM5803_PRECHG_ICHG_PRE_SET);
-		rv |= chg_write8(chgnum, SM5803_REG_PRECHG, reg);
-
-		/*
-		 * Set up BFET alerts
-		 *
-		 * We'll set the soft limit at 1.5W and the hard limit at 6W.
-		 *
-		 * The register is 29.2 mW per bit.
-		 */
-		reg = (1500 * 10) / 292;
-		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_MAX_TH, reg);
-		reg = (6000 * 10) / 292;
-		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_HWSAFE_MAX_TH,
-				 reg);
-		rv |= main_read8(chgnum, SM5803_REG_INT3_EN, &reg);
-		reg |= SM5803_INT3_BFET_PWR_LIMIT |
-		       SM5803_INT3_BFET_PWR_HWSAFE_LIMIT;
-		rv |= main_write8(chgnum, SM5803_REG_INT3_EN, reg);
-
-		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &reg);
-		reg &= ~SM5803_FLOW3_SWITCH_BCK_BST;
-		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, reg);
-
-		rv |= chg_read8(chgnum, SM5803_REG_SWITCHER_CONF, &reg);
-		reg |= SM5803_SW_BCK_BST_CONF_AUTO;
-		rv |= chg_write8(chgnum, SM5803_REG_SWITCHER_CONF, reg);
-	}
-
-	if (rv)
-		CPRINTS("%s %d: Failed initialization", CHARGER_NAME, chgnum);
-	else
-		chip_inited[chgnum] = true;
-}
-
-static enum ec_error_list sm5803_post_init(int chgnum)
-{
-	/* Nothing to do, charger is always powered */
-	return EC_SUCCESS;
-}
-
-void sm5803_hibernate(int chgnum)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read REFERENCE reg", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-
-	/* Disable LDO bits - note the primary LDO should not be disabled */
-	if (chgnum != CHARGER_PRIMARY) {
-		reg |= (BIT(0) | BIT(1));
-		rv |= main_write8(chgnum, SM5803_REG_REFERENCE, reg);
-	}
-
-	/* Slow the clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg |= SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/* Turn off GPADCs */
-	rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, 0);
-	rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG2, 0);
-
-	/* Disable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
-	reg &= ~SM5803_PSYS1_DAC_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
-
-	/* Disable ADC sigma delta */
-	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
-	reg &= ~SM5803_CC_CONFIG1_SD_PWRUP;
-	rv |= chg_write8(chgnum, SM5803_REG_CC_CONFIG1, reg);
-
-	/* Disable PROCHOT comparators */
-	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
-	reg &= ~SM5803_PHOT1_COMPARATOR_EN;
-	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
-
-	if (rv)
-		CPRINTS("%s %d: Failed to set hibernate", CHARGER_NAME, chgnum);
-}
-
-static void sm5803_disable_runtime_low_power_mode(void)
-{
-	enum ec_error_list rv;
-	int reg;
-	int chgnum = TASK_ID_TO_PD_PORT(task_get_current());
-
-	CPRINTS("%s %d: disable runtime low power mode", CHARGER_NAME, chgnum);
-	rv = main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read REFERENCE reg", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-	/* Set a higher clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/* Enable ADC sigma delta */
-	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
-	reg |= SM5803_CC_CONFIG1_SD_PWRUP;
-	rv |= chg_write8(chgnum, SM5803_REG_CC_CONFIG1, reg);
-
-	if (rv)
-		CPRINTS("%s %d: Failed to set in disable runtime LPM",
-			CHARGER_NAME, chgnum);
-}
-DECLARE_HOOK(HOOK_USB_PD_CONNECT,
-		sm5803_disable_runtime_low_power_mode,
-		HOOK_PRIO_FIRST);
-
-static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable)
-{
-	int rv;
-	int regval;
-	const struct battery_info *batt_info;
-
-	if (enable) {
-		/*
-		 * We need to wait for the BFET enable attempt to complete,
-		 * otherwise we may end up disabling linear charge.
-		 */
-		if (!attempt_bfet_enable)
-			return EC_ERROR_TRY_AGAIN;
-		rv = main_write8(chgnum, 0x1F, 0x1);
-		rv |= test_write8(chgnum, 0x44, 0x20);
-		rv |= main_write8(chgnum, 0x1F, 0);
-
-		/*
-		 * Precharge thresholds have already been set up as a part of
-		 * init, however set fast charge current equal to the precharge
-		 * current in case the battery moves beyond that threshold.
-		 */
-		batt_info = battery_get_info();
-		rv |= sm5803_set_current(CHARGER_PRIMARY,
-					 batt_info->precharge_current);
-
-		/* Enable linear charge mode. */
-		rv |= sm5803_flow1_update(chgnum,
-					  SM5803_FLOW1_LINEAR_CHARGE_EN,
-					 MASK_SET);
-		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
-		regval |= BIT(6) | BIT(5) | BIT(4);
-		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval);
-	} else {
-		rv = sm5803_flow1_update(chgnum,
-					 SM5803_FLOW1_LINEAR_CHARGE_EN,
-					 MASK_CLR);
-		rv |= sm5803_flow2_update(chgnum,
-					  SM5803_FLOW2_AUTO_ENABLED,
-					  MASK_CLR);
-		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
-		regval &= ~(BIT(6) | BIT(5) | BIT(4) |
-			    SM5803_FLOW3_SWITCH_BCK_BST);
-		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval);
-		rv |= chg_read8(chgnum, SM5803_REG_SWITCHER_CONF, &regval);
-		regval |= SM5803_SW_BCK_BST_CONF_AUTO;
-		rv |= chg_write8(chgnum, SM5803_REG_SWITCHER_CONF, regval);
-	}
-
-	return rv;
-}
-
-static void sm5803_enable_runtime_low_power_mode(void)
-{
-	enum ec_error_list rv;
-	int reg;
-	int chgnum = TASK_ID_TO_PD_PORT(task_get_current());
-
-	CPRINTS("%s %d: enable runtime low power mode", CHARGER_NAME, chgnum);
-	rv = main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read REFERENCE reg", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-	/* Slow the clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg |= SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/* Disable ADC sigma delta */
-	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
-	reg &= ~SM5803_CC_CONFIG1_SD_PWRUP;
-	rv |= chg_write8(chgnum, SM5803_REG_CC_CONFIG1, reg);
-
-	/* If the system is off, all PROCHOT comparators may be turned off */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_ANY_SUSPEND)) {
-		rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
-		reg &= ~SM5803_PHOT1_COMPARATOR_EN;
-		rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
-	}
-
-	if (rv)
-		CPRINTS("%s %d: Failed to set in enable runtime LPM",
-			CHARGER_NAME, chgnum);
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT,
-		sm5803_enable_runtime_low_power_mode,
-		HOOK_PRIO_LAST);
-
-void sm5803_disable_low_power_mode(int chgnum)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	CPRINTS("%s %d: disable low power mode", CHARGER_NAME, chgnum);
-	rv = main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read REFERENCE reg", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-	/* Enable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
-	reg |= SM5803_PSYS1_DAC_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
-
-	/* Enable PROCHOT comparators except Ibus */
-	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
-	reg |= SM5803_PHOT1_COMPARATOR_EN;
-	reg &= ~SM5803_PHOT1_IBUS_PHOT_COMP_EN;
-	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
-
-	if (rv)
-		CPRINTS("%s %d: Failed to set in disable low power mode",
-			CHARGER_NAME, chgnum);
-}
-
-void sm5803_enable_low_power_mode(int chgnum)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	CPRINTS("%s %d: enable low power mode", CHARGER_NAME, chgnum);
-	rv = main_read8(chgnum, SM5803_REG_REFERENCE, &reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read REFERENCE reg", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-	/* Disable Psys DAC */
-	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
-	reg &= ~SM5803_PSYS1_DAC_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_PSYS1, reg);
-
-	/*
-	 * Disable all PROCHOT comparators only if port is inactive.  Vbus
-	 * sourcing requires that the Vbus comparator be enabled, and it
-	 * cannot be enabled from HOOK_USB_PD_CONNECT since that is
-	 * called after Vbus has turned on.
-	 */
-	rv |= chg_read8(chgnum, SM5803_REG_PHOT1, &reg);
-	reg &= ~SM5803_PHOT1_COMPARATOR_EN;
-	if (pd_is_connected(chgnum))
-		reg |= SM5803_PHOT1_VBUS_MON_EN;
-	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
-
-
-	if (rv)
-		CPRINTS("%s %d: Failed to set in enable low power mode",
-			CHARGER_NAME, chgnum);
-}
-
-/*
- * Restart charging on the active port, if it's still active and it hasn't
- * exceeded our maximum number of restarts.
- */
-void sm5803_restart_charging(void)
-{
-	int act_chg = charge_manager_get_active_charge_port();
-	timestamp_t now = get_time();
-
-	if (act_chg == active_restart_port) {
-		if (timestamp_expired(failure_tracker[act_chg].time, &now)) {
-			/*
-			 * Enough time has passed since our last failure,
-			 * restart the timing and count from now.
-			 */
-			failure_tracker[act_chg].time.val = now.val +
-						CHARGING_FAILURE_INTERVAL;
-			failure_tracker[act_chg].count = 1;
-
-			sm5803_vbus_sink_enable(act_chg, 1);
-		} else if (++failure_tracker[act_chg].count >
-			   CHARGING_FAILURE_MAX_COUNT) {
-			CPRINTS("%s %d: Exceeded charging failure retries",
-				CHARGER_NAME, act_chg);
-		} else {
-			sm5803_vbus_sink_enable(act_chg, 1);
-		}
-	}
-
-	active_restart_port = CHARGE_PORT_NONE;
-}
-DECLARE_DEFERRED(sm5803_restart_charging);
-
-/*
- * Process interrupt registers and report any Vbus changes.  Alert the AP if the
- * charger has become too hot.
- */
-void sm5803_handle_interrupt(int chgnum)
-{
-	enum ec_error_list rv;
-	int int_reg, meas_reg;
-	static bool throttled;
-	struct batt_params bp;
-	int act_chg, val;
-
-	/* Note: Interrupt registers are clear on read */
-	rv = main_read8(chgnum, SM5803_REG_INT1_REQ, &int_reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed read int1 register", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-
-	if (int_reg & SM5803_INT1_CHG) {
-		rv = main_read8(chgnum, SM5803_REG_STATUS1, &meas_reg);
-		if (!(meas_reg & SM5803_STATUS1_CHG_DET)) {
-			charger_vbus[chgnum] = 0;
-			if (IS_ENABLED(CONFIG_USB_CHARGER))
-				usb_charger_vbus_change(chgnum, 0);
-		} else {
-			charger_vbus[chgnum] = 1;
-			if (IS_ENABLED(CONFIG_USB_CHARGER))
-				usb_charger_vbus_change(chgnum, 1);
-		}
-		board_check_extpower();
-	}
-
-	rv = main_read8(chgnum, SM5803_REG_INT2_REQ, &int_reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed read int2 register", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-
-	if (int_reg & SM5803_INT2_TINT) {
-		rv = meas_read8(chgnum, SM5803_REG_TINT_MEAS_MSB, &meas_reg);
-		if ((meas_reg <= SM5803_TINT_LOW_LEVEL) && throttled) {
-			throttled = false;
-			throttle_ap(THROTTLE_OFF, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
-			/*
-			 * Set back higher threshold to 360 K and set lower
-			 * threshold to 0.
-			 */
-			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-							SM5803_TINT_MIN_LEVEL);
-			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-							SM5803_TINT_HIGH_LEVEL);
-		} else if (meas_reg >= SM5803_TINT_HIGH_LEVEL) {
-			throttled = true;
-			throttle_ap(THROTTLE_ON, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
-			/*
-			 * Set back lower threshold to 330 K and set higher
-			 * threshold to maximum.
-			 */
-			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-							SM5803_TINT_MAX_LEVEL);
-			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-							SM5803_TINT_LOW_LEVEL);
-		}
-		/*
-		 * If the interrupt came in and we're not currently throttling
-		 * or the level is below the upper threshold, it can likely be
-		 * ignored.
-		 */
-	}
-
-	if (int_reg & SM5803_INT2_VBATSNSP) {
-		int meas_volt;
-		uint32_t platform_id;
-
-		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
-		if (rv) {
-			CPRINTS("%s %d: Failed to read platform in interrupt",
-							CHARGER_NAME, chgnum);
-			return;
-		}
-		platform_id &= SM5803_PLATFORM_ID;
-		act_chg = charge_manager_get_active_charge_port();
-		rv = meas_read8(CHARGER_PRIMARY,
-					SM5803_REG_VBATSNSP_MEAS_MSB,
-					&meas_reg);
-		if (rv)
-			return;
-		meas_volt = meas_reg << 2;
-		rv = meas_read8(CHARGER_PRIMARY,
-					SM5803_REG_VBATSNSP_MEAS_LSB,
-					&meas_reg);
-		if (rv)
-			return;
-		meas_volt |= meas_reg & 0x03;
-		rv = meas_read8(CHARGER_PRIMARY,
-			SM5803_REG_VBATSNSP_MAX_TH, &meas_reg);
-		if (rv)
-			return;
-
-		if (is_platform_id_2s(platform_id)) {
-			/* 2S Battery */
-			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! - "
-				"VBAT %d mV",
-				CHARGER_NAME, CHARGER_PRIMARY,
-				meas_reg * 408/10,
-				meas_volt * 102/10);
-		}
-
-		if (is_platform_id_3s(platform_id)) {
-			/* 3S Battery */
-			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! "
-				"- VBAT %d mV",
-				CHARGER_NAME, CHARGER_PRIMARY,
-				meas_reg * 616/10,
-				meas_volt * 154/10);
-		}
-
-		/* Set Vbat Threshold to Max value to re-arm the interrupt */
-		rv = meas_write8(CHARGER_PRIMARY,
-			SM5803_REG_VBATSNSP_MAX_TH, 0xFF);
-
-		/* Disable battery charge */
-		rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_DISABLED,
-			MASK_CLR);
-		if (is_platform_id_2s(platform_id)) {
-			/* 2S battery: set VBAT_SENSP TH 9V */
-			rv |= meas_write8(CHARGER_PRIMARY,
-				SM5803_REG_VBATSNSP_MAX_TH,
-				SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
-		}
-		if (is_platform_id_3s(platform_id)) {
-			/* 3S battery: set VBAT_SENSP TH 13.3V */
-			rv |= meas_write8(CHARGER_PRIMARY,
-				SM5803_REG_VBATSNSP_MAX_TH,
-				SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
-		}
-
-		active_restart_port = act_chg;
-		hook_call_deferred(&sm5803_restart_charging_data, 1 * SECOND);
-	}
-
-	/* TODO(b/159376384): Take action on fatal BFET power alert. */
-	rv = main_read8(chgnum, SM5803_REG_INT3_REQ, &int_reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read int3 register", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-
-	if ((int_reg & SM5803_INT3_BFET_PWR_LIMIT) ||
-	    (int_reg & SM5803_INT3_BFET_PWR_HWSAFE_LIMIT)) {
-		battery_get_params(&bp);
-		act_chg = charge_manager_get_active_charge_port();
-		CPRINTS("%s BFET power limit reached! (%s)", CHARGER_NAME,
-			(int_reg & SM5803_INT3_BFET_PWR_LIMIT) ? "warn" :
-			"FATAL");
-		CPRINTS("\tVbat: %dmV", bp.voltage);
-		CPRINTS("\tIbat: %dmA", bp.current);
-		charger_get_voltage(act_chg, &val);
-		CPRINTS("\tVsys(aux): %dmV", val);
-		charger_get_current(act_chg, &val);
-		CPRINTS("\tIsys: %dmA", val);
-		cflush();
-	}
-
-	rv = main_read8(chgnum, SM5803_REG_INT4_REQ, &int_reg);
-	if (rv) {
-		CPRINTS("%s %d: Failed to read int4 register", CHARGER_NAME,
-			chgnum);
-		return;
-	}
-
-	if (int_reg & SM5803_INT4_CHG_FAIL) {
-		int status_reg;
-
-		act_chg = charge_manager_get_active_charge_port();
-		chg_read8(chgnum, SM5803_REG_STATUS_CHG_REG, &status_reg);
-		CPRINTS("%s %d: CHG_FAIL_INT fired.  Status 0x%02x",
-			CHARGER_NAME, chgnum, status_reg);
-
-		/* Write 1 to clear status interrupts */
-		chg_write8(chgnum, SM5803_REG_STATUS_CHG_REG, status_reg);
-
-		/*
-		 * If a survivable fault happened, re-start sinking on the
-		 * active charger after an appropriate delay.
-		 */
-		if (status_reg & SM5803_STATUS_CHG_OV_ITEMP) {
-			active_restart_port = act_chg;
-			hook_call_deferred(&sm5803_restart_charging_data,
-					   30 * SECOND);
-		} else if ((status_reg & SM5803_STATUS_CHG_OV_VBAT) &&
-						act_chg == CHARGER_PRIMARY) {
-			active_restart_port = act_chg;
-			hook_call_deferred(&sm5803_restart_charging_data,
-					   1 * SECOND);
-		}
-	}
-
-	if (int_reg & SM5803_INT4_CHG_DONE)
-		CPRINTS("%s %d: CHG_DONE_INT fired!!!", CHARGER_NAME, chgnum);
-
-	if (int_reg & SM5803_INT4_OTG_FAIL) {
-		int status_reg;
-
-		/*
-		 * Gather status to detect if this was overcurrent
-		 *
-		 * Note: a status of 0 with this interrupt also indicates an
-		 * overcurrent (see b/170517117)
-		 */
-		chg_read8(chgnum, SM5803_REG_STATUS_DISCHG, &status_reg);
-		CPRINTS("%s %d: OTG_FAIL_INT fired. Status 0x%02x",
-			CHARGER_NAME, chgnum, status_reg);
-		if ((status_reg == 0) ||
-		    (status_reg == SM5803_STATUS_DISCHG_VBUS_SHORT)) {
-			pd_handle_overcurrent(chgnum);
-		}
-
-		/*
-		 * Clear source mode here when status is 0, since OTG disable
-		 * will detect us as sinking in this failure case.
-		 */
-		if (status_reg == 0)
-			rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-						 MASK_CLR);
-	}
-
-}
-
-static void sm5803_irq_deferred(void)
-{
-	int i;
-	uint32_t pending = atomic_clear(&irq_pending);
-
-	for (i = 0; i < CHARGER_NUM; i++)
-		if (BIT(i) & pending)
-			sm5803_handle_interrupt(i);
-}
-DECLARE_DEFERRED(sm5803_irq_deferred);
-
-void sm5803_interrupt(int chgnum)
-{
-	atomic_or(&irq_pending, BIT(chgnum));
-	hook_call_deferred(&sm5803_irq_deferred_data, 0);
-}
-
-static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id)
-{
-	int rv = EC_SUCCESS;
-
-	if (dev_id == UNKNOWN_DEV_ID)
-		rv = main_read8(chgnum, SM5803_REG_CHIP_ID, &dev_id);
-
-	if (!rv)
-		*id = dev_id;
-
-	return rv;
-
-}
-
-static const struct charger_info *sm5803_get_info(int chgnum)
-{
-	return &sm5803_charger_info;
-}
-
-static enum ec_error_list sm5803_get_status(int chgnum, int *status)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	/* Charger obeys smart battery requests - making it level 2 */
-	*status = CHARGER_LEVEL_2;
-
-	rv = chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
-	if (rv)
-		return rv;
-
-
-	if ((reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED &&
-	    !(reg & SM5803_FLOW1_LINEAR_CHARGE_EN))
-		*status |= CHARGER_CHARGE_INHIBITED;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_set_mode(int chgnum, int mode)
-{
-	enum ec_error_list rv = EC_SUCCESS;
-
-	if (mode & CHARGE_FLAG_INHIBIT_CHARGE) {
-		rv = sm5803_flow1_update(chgnum, 0xFF, MASK_CLR);
-		rv |= sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED,
-					  MASK_CLR);
-	}
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_get_actual_current(int chgnum, int *current)
-{
-	enum ec_error_list rv;
-	int reg;
-	int curr;
-
-	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_AVG_MEAS_MSB, &reg);
-	if (rv)
-		return rv;
-	curr = reg << 2;
-
-	rv = meas_read8(chgnum, SM5803_REG_IBAT_CHG_AVG_MEAS_LSB, &reg);
-	if (rv)
-		return rv;
-	curr |= reg & SM5803_IBAT_CHG_MEAS_LSB;
-
-	/* The LSB is 7.32mA */
-	*current = curr * 732 / 100;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_get_current(int chgnum, int *current)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_FAST_CONF4, &reg);
-	if (rv)
-		return rv;
-
-	reg &= SM5803_CONF4_ICHG_FAST;
-	*current = SM5803_REG_TO_CURRENT(reg);
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_set_current(int chgnum, int current)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_FAST_CONF4, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~SM5803_CONF4_ICHG_FAST;
-	reg |= SM5803_CURRENT_TO_REG(current);
-
-	rv = chg_write8(chgnum, SM5803_REG_FAST_CONF4, reg);
-	return rv;
-}
-
-static enum ec_error_list sm5803_get_actual_voltage(int chgnum, int *voltage)
-{
-	enum ec_error_list rv;
-	int reg;
-	int volt_bits;
-
-	rv = meas_read8(chgnum, SM5803_REG_VSYS_AVG_MEAS_MSB, &reg);
-	if (rv)
-		return rv;
-	volt_bits = reg << 2;
-
-	rv = meas_read8(chgnum, SM5803_REG_VSYS_AVG_MEAS_LSB, &reg);
-	if (rv)
-		return rv;
-	volt_bits |= reg & 0x3;
-
-	/* The LSB is 23.4mV */
-	*voltage = volt_bits * 234 / 10;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_get_voltage(int chgnum, int *voltage)
-{
-	enum ec_error_list rv;
-	int regval;
-	int v;
-
-	rv = chg_read8(chgnum, SM5803_REG_VBAT_FAST_MSB, &regval);
-	v = regval << 3;
-	rv |= chg_read8(chgnum, SM5803_REG_VBAT_FAST_LSB, &regval);
-	v |= (regval & 0x3);
-
-	*voltage = SM5803_REG_TO_VOLTAGE(v);
-
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage)
-{
-	enum ec_error_list rv;
-	int regval;
-
-	regval = SM5803_VOLTAGE_TO_REG(voltage);
-
-	/*
-	 * Note: Set both voltages on both chargers.  Vbat will only be used on
-	 * primary, which enables charging.
-	 */
-	rv = chg_write8(chgnum, SM5803_REG_VSYS_PREREG_MSB, (regval >> 3));
-	rv |= chg_write8(chgnum, SM5803_REG_VSYS_PREREG_LSB, (regval & 0x7));
-	rv |= chg_write8(chgnum, SM5803_REG_VBAT_FAST_MSB, (regval >> 3));
-	rv |= chg_write8(chgnum, SM5803_REG_VBAT_FAST_LSB, (regval & 0x7));
-
-	/* Once battery is connected, set up fast charge enable */
-	if (fast_charge_disabled && chgnum == CHARGER_PRIMARY &&
-	    battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
-		rv = sm5803_flow2_update(chgnum,
-					 SM5803_FLOW2_AUTO_ENABLED,
-					 MASK_SET);
-		fast_charge_disabled = false;
-	}
-
-	if (IS_ENABLED(CONFIG_OCPC) && chgnum != CHARGER_PRIMARY) {
-		/*
-		 * Check to see if the BFET is enabled.  If not, enable it by
-		 * toggling linear mode on the primary charger.  The BFET can be
-		 * disabled if the system is powered up from an auxiliary charge
-		 * port and the battery is dead.
-		 */
-		rv |= chg_read8(CHARGER_PRIMARY, SM5803_REG_LOG1, &regval);
-		if (!(regval & SM5803_BATFET_ON) && !attempt_bfet_enable) {
-			CPRINTS("SM5803: Attempting to turn on BFET");
-			cflush();
-			rv |= sm5803_flow1_update(CHARGER_PRIMARY,
-						  SM5803_FLOW1_LINEAR_CHARGE_EN,
-						  MASK_SET);
-			rv |= sm5803_flow1_update(CHARGER_PRIMARY,
-						  SM5803_FLOW1_LINEAR_CHARGE_EN,
-						  MASK_CLR);
-			attempt_bfet_enable = 1;
-			sm5803_vbus_sink_enable(chgnum, 1);
-		}
-		/* There's no need to attempt it if the BFET's already on. */
-		if (regval & SM5803_BATFET_ON)
-			attempt_bfet_enable = 1;
-	}
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_discharge_on_ac(int chgnum, int enable)
-{
-	enum ec_error_list rv = EC_SUCCESS;
-
-	if (enable) {
-		rv = sm5803_vbus_sink_enable(chgnum, 0);
-	} else {
-		if (chgnum == charge_manager_get_active_charge_port())
-			rv = sm5803_vbus_sink_enable(chgnum, 1);
-	}
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
-{
-	enum ec_error_list rv;
-	int reg;
-	int volt_bits;
-
-	rv = meas_read8(chgnum, SM5803_REG_VBUS_MEAS_MSB, &reg);
-	if (rv)
-		return rv;
-
-	volt_bits = reg << 2;
-
-	rv = meas_read8(chgnum, SM5803_REG_VBUS_MEAS_LSB, &reg);
-
-	volt_bits |= reg & SM5803_VBUS_MEAS_LSB;
-
-	/* Vbus ADC is in 23.4 mV steps */
-	*voltage = (volt_bits * 234) / 10;
-	return rv;
-}
-
-static enum ec_error_list sm5803_set_input_current_limit(int chgnum,
-							 int input_current)
-{
-	int reg;
-
-	reg = SM5803_CURRENT_TO_REG(input_current) & SM5803_CHG_ILIM_RAW;
-
-	return chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg);
-}
-
-static enum ec_error_list sm5803_get_input_current_limit(int chgnum,
-							 int *input_current)
-{
-	int rv;
-	int val;
-
-	rv = chg_read8(chgnum, SM5803_REG_CHG_ILIM, &val);
-	if (rv)
-		return rv;
-
-	*input_current = SM5803_REG_TO_CURRENT(val & SM5803_CHG_ILIM_RAW);
-	return rv;
-}
-
-static enum ec_error_list sm5803_get_input_current(int chgnum,
-						   int *input_current)
-{
-	enum ec_error_list rv;
-	int reg;
-	int curr;
-
-	rv = meas_read8(chgnum, SM5803_REG_IBUS_CHG_MEAS_MSB, &reg);
-	if (rv)
-		return rv;
-	curr = reg << 2;
-
-	rv = meas_read8(chgnum, SM5803_REG_IBUS_CHG_MEAS_LSB, &reg);
-	if (rv)
-		return rv;
-	curr |= reg & 0x3;
-
-	/* The LSB is 7.32mA */
-	*input_current = curr * 732 / 100;
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_get_option(int chgnum, int *option)
-{
-	enum ec_error_list rv;
-	uint32_t control;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
-	control = reg;
-
-	rv |= chg_read8(chgnum, SM5803_REG_FLOW2, &reg);
-	control |= reg << 8;
-
-	rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &reg);
-	control |= reg << 16;
-
-	return rv;
-}
-
-enum ec_error_list sm5803_is_acok(int chgnum, bool *acok)
-{
-	int rv;
-	int reg, vbus_mv;
-
-	rv = main_read8(chgnum, SM5803_REG_STATUS1, &reg);
-
-	if (rv)
-		return rv;
-
-	/* If we're not sinking, then AC can't be OK. */
-	if (!(reg & SM5803_STATUS1_CHG_DET)) {
-		*acok = false;
-		return EC_SUCCESS;
-	}
-
-	/*
-	 * Okay, we're sinking. Check that VBUS has some voltage. This
-	 * should indicate that the path is good.
-	 */
-	rv = charger_get_vbus_voltage(chgnum, &vbus_mv);
-
-	if (rv)
-		return rv;
-
-	/* Assume that ACOK would be asserted if VBUS is higher than ~4V. */
-	*acok = vbus_mv >= 4000;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_is_input_current_limit_reached(int chgnum,
-								bool *reached)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_LOG2, &reg);
-	if (rv)
-		return rv;
-
-	*reached = (reg & SM5803_ISOLOOP_ON) ? true : false;
-
-	return EC_SUCCESS;
-}
-
-static enum ec_error_list sm5803_set_option(int chgnum, int option)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	mutex_lock(&flow1_access_lock[chgnum]);
-
-	reg = option & 0xFF;
-	rv = chg_write8(chgnum, SM5803_REG_FLOW1, reg);
-
-	mutex_unlock(&flow1_access_lock[chgnum]);
-	if (rv)
-		return rv;
-
-	reg = (option >> 8) & 0xFF;
-	rv = chg_write8(chgnum, SM5803_REG_FLOW2, reg);
-	if (rv)
-		return rv;
-
-	reg = (option >> 16) & 0xFF;
-	rv = chg_write8(chgnum, SM5803_REG_FLOW3, reg);
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_set_otg_current_voltage(int chgnum,
-							 int output_current,
-							 int output_voltage)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_DISCH_CONF5, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~SM5803_DISCH_CONF5_CLS_LIMIT;
-	reg |= MIN((output_current / SM5803_CLS_CURRENT_STEP),
-						SM5803_DISCH_CONF5_CLS_LIMIT);
-	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF5, reg);
-
-	reg = SM5803_VOLTAGE_TO_REG(output_voltage);
-	rv = chg_write8(chgnum, SM5803_REG_VPWR_MSB, (reg >> 3));
-	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF2,
-					reg & SM5803_DISCH_CONF5_VPWR_LSB);
-
-	return rv;
-}
-
-static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
-{
-	enum ec_error_list rv;
-	int reg, status;
-
-	if (enabled) {
-		int selected_current;
-
-		rv = chg_read8(chgnum, SM5803_REG_ANA_EN1, &reg);
-		if (rv)
-			return rv;
-
-		/* Enable current limit */
-		reg &= ~SM5803_ANA_EN1_CLS_DISABLE;
-		rv = chg_write8(chgnum, SM5803_REG_ANA_EN1, reg);
-
-		/* Disable ramps on current set in discharge */
-		rv |= chg_read8(chgnum, SM5803_REG_DISCH_CONF6, &reg);
-		reg |= SM5803_DISCH_CONF6_RAMPS_DIS;
-		rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF6, reg);
-
-		/*
-		 * In order to ensure the Vbus output doesn't overshoot too
-		 * much, turn the starting voltage down to 4.8 V and ramp up
-		 * after 4 ms
-		 */
-		rv = chg_read8(chgnum, SM5803_REG_DISCH_CONF5, &reg);
-		if (rv)
-			return rv;
-
-		selected_current = (reg & SM5803_DISCH_CONF5_CLS_LIMIT) *
-			SM5803_CLS_CURRENT_STEP;
-		sm5803_set_otg_current_voltage(chgnum, selected_current, 4800);
-
-		/*
-		 * Enable: SOURCE_MODE - enable sourcing out
-		 *	   DIRECTCHG_SOURCE_EN - enable current loop
-		 *	   (for designs with no external Vbus FET)
-		 */
-		rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-					 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-					 MASK_SET);
-		usleep(4000);
-
-		sm5803_set_otg_current_voltage(chgnum, selected_current, 5000);
-	} else {
-		/* Always clear out discharge status before clearing FLOW1 */
-		rv = chg_read8(chgnum, SM5803_REG_STATUS_DISCHG, &status);
-		if (rv)
-			return rv;
-
-		if (status)
-			CPRINTS("%s %d: Discharge failure 0x%02x", CHARGER_NAME,
-				chgnum, status);
-
-		rv |= chg_write8(chgnum, SM5803_REG_STATUS_DISCHG, status);
-
-		/* Re-enable ramps on current set in discharge */
-		rv |= chg_read8(chgnum, SM5803_REG_DISCH_CONF6, &reg);
-		reg &= ~SM5803_DISCH_CONF6_RAMPS_DIS;
-		rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF6, reg);
-
-		/*
-		 * PD tasks will always turn off previous sourcing on init.
-		 * Protect ourselves from brown out on init by checking if we're
-		 * sinking right now.  The init process should only leave sink
-		 * mode enabled if a charger is plugged in; otherwise it's
-		 * expected to be 0.
-		 *
-		 * Always clear out sourcing if the previous source-out failed.
-		 */
-		rv |= chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
-		if (rv)
-			return rv;
-
-		if ((reg & SM5803_FLOW1_MODE) != CHARGER_MODE_SINK || status)
-			rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-						 MASK_CLR);
-	}
-
-	return rv;
-}
-
-static int sm5803_is_sourcing_otg_power(int chgnum, int port)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
-	if (rv)
-		return 0;
-
-	/*
-	 * Note: In linear mode, MB charger will read a reserved mode when
-	 * sourcing, so bit 1 is the most reliable way to detect sourcing.
-	 */
-	return (reg & BIT(1));
-}
-
-static enum ec_error_list sm5803_set_vsys_compensation(int chgnum,
-						       struct ocpc_data *ocpc,
-						       int current_ma,
-						       int voltage_mv)
-{
-
-	int rv;
-	int regval;
-	int r;
-
-	/* Set IR drop compensation */
-	r = ocpc->combined_rsys_rbatt_mo * 100 / 167; /* 1.67mOhm steps */
-	r = MAX(0, r);
-	rv = chg_write8(chgnum, SM5803_REG_IR_COMP2, r & 0x7F);
-	rv |= chg_read8(chgnum, SM5803_REG_IR_COMP1, &regval);
-	regval &= ~SM5803_IR_COMP_RES_SET_MSB;
-	r = r >> 8; /* Bits 9:8 */
-	regval |= (r & 0x3) << SM5803_IR_COMP_RES_SET_MSB_SHIFT;
-	regval |= SM5803_IR_COMP_EN;
-	rv |= chg_write8(chgnum, SM5803_REG_IR_COMP1, regval);
-
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-/* Hardware current ramping (aka DPM: Dynamic Power Management) */
-
-#ifdef CONFIG_CHARGE_RAMP_HW
-static enum ec_error_list sm5803_set_hw_ramp(int chgnum, int enable)
-{
-	enum ec_error_list rv;
-	int reg;
-
-	rv = chg_read8(chgnum, SM5803_REG_CHG_MON_REG, &reg);
-
-	if (enable)
-		reg |= SM5803_DPM_LOOP_EN;
-	else
-		reg &= ~SM5803_DPM_LOOP_EN;
-
-	rv |= chg_write8(chgnum, SM5803_REG_CHG_MON_REG, reg);
-
-	return rv;
-}
-
-static int sm5803_ramp_is_stable(int chgnum)
-{
-	/*
-	 * There is no way to read current limit that the ramp has
-	 * settled on with sm5803, so we don't consider the ramp stable,
-	 * because we never know what the stable limit is.
-	 */
-	return 0;
-}
-
-static int sm5803_ramp_is_detected(int chgnum)
-{
-	return 1;
-}
-
-static int sm5803_ramp_get_current_limit(int chgnum)
-{
-	int rv;
-	int input_current = 0;
-
-	rv = sm5803_get_input_current_limit(chgnum, &input_current);
-
-	return rv ? -1 : input_current;
-}
-#endif /* CONFIG_CHARGE_RAMP_HW */
-
-#ifdef CONFIG_CMD_CHARGER_DUMP
-static int command_sm5803_dump(int argc, char **argv)
-{
-	int reg;
-	int regval;
-	int chgnum = 0;
-
-	if (argc > 1)
-		chgnum = atoi(argv[1]);
-
-	/* Dump base regs */
-	ccprintf("BASE regs\n");
-	for (reg = 0x01; reg <= 0x30; reg++) {
-		if (!main_read8(chgnum, reg, &regval))
-			ccprintf("[0x%02X] = 0x%02x\n", reg, regval);
-		if (reg & 0xf) {
-			cflush(); /* Flush periodically */
-			watchdog_reload();
-		}
-	}
-
-	/* Dump measure regs */
-	ccprintf("MEAS regs\n");
-	for (reg = 0x01; reg <= 0xED; reg++) {
-		if (!meas_read8(chgnum, reg, &regval))
-			ccprintf("[0x%02X] = 0x%02x\n", reg, regval);
-		if (reg & 0xf) {
-			cflush(); /* Flush periodically */
-			watchdog_reload();
-		}
-	}
-
-	/* Dump Charger regs from 0x1C to 0x7F */
-	ccprintf("CHG regs\n");
-	for (reg = 0x1C; reg <= 0x7F; reg++) {
-		if (!chg_read8(chgnum, reg, &regval))
-			ccprintf("[0x%02X] = 0x%02x\n", reg, regval);
-		if (reg & 0xf) {
-			cflush(); /* Flush periodically */
-			watchdog_reload();
-		}
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(charger_dump, command_sm5803_dump,
-			"charger_dump [chgnum]", "Dumps SM5803 registers");
-#endif /* CONFIG_CMD_CHARGER_DUMP */
-
-const struct charger_drv sm5803_drv = {
-	.init = &sm5803_init,
-	.post_init = &sm5803_post_init,
-	.get_info = &sm5803_get_info,
-	.get_status = &sm5803_get_status,
-	.set_mode = &sm5803_set_mode,
-	.get_actual_current = &sm5803_get_actual_current,
-	.get_current = &sm5803_get_current,
-	.set_current = &sm5803_set_current,
-	.get_actual_voltage = &sm5803_get_actual_voltage,
-	.get_voltage = &sm5803_get_voltage,
-	.set_voltage = &sm5803_set_voltage,
-	.discharge_on_ac = &sm5803_discharge_on_ac,
-	.get_vbus_voltage = &sm5803_get_vbus_voltage,
-	.set_input_current_limit = &sm5803_set_input_current_limit,
-	.get_input_current_limit = &sm5803_get_input_current_limit,
-	.get_input_current = &sm5803_get_input_current,
-	.device_id = &sm5803_get_dev_id,
-	.get_option = &sm5803_get_option,
-	.set_option = &sm5803_set_option,
-	.set_otg_current_voltage = &sm5803_set_otg_current_voltage,
-	.enable_otg_power = &sm5803_enable_otg_power,
-	.is_sourcing_otg_power = &sm5803_is_sourcing_otg_power,
-	.set_vsys_compensation = &sm5803_set_vsys_compensation,
-	.is_icl_reached = &sm5803_is_input_current_limit_reached,
-	.enable_linear_charge = &sm5803_enable_linear_charge,
-#ifdef CONFIG_CHARGE_RAMP_HW
-	.set_hw_ramp = &sm5803_set_hw_ramp,
-	.ramp_is_stable = &sm5803_ramp_is_stable,
-	.ramp_is_detected = &sm5803_ramp_is_detected,
-	.ramp_get_current_limit = &sm5803_ramp_get_current_limit,
-#endif
-};
diff --git a/driver/charger/sm5803.h b/driver/charger/sm5803.h
deleted file mode 100644
index b7638411e4..0000000000
--- a/driver/charger/sm5803.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Silicon Mitus SM5803 Buck-Boost Charger
- */
-
-#ifndef __CROS_EC_SM5803_H
-#define __CROS_EC_SM5803_H
-
-#include "common.h"
-
-/* Note: configure charger struct with CHARGER_FLAGS */
-#define SM5803_ADDR_MAIN_FLAGS		0x30
-#define SM5803_ADDR_MEAS_FLAGS		0x31
-#define SM5803_ADDR_CHARGER_FLAGS	0x32
-#define SM5803_ADDR_TEST_FLAGS		0x37
-
-/* Main registers (address 0x30) */
-
-#define SM5803_REG_CHIP_ID		0x00
-
-#define SM5803_REG_STATUS1		0x01
-#define SM5803_STATUS1_VSYS_OK		BIT(0)
-#define SM5803_STATUS1_VPWR_OK		BIT(1)
-#define SM5803_STATUS1_VBUS_UVL		BIT(3)
-#define SM5803_STATUS1_VBUS_SHORT	BIT(4)
-#define SM5803_STATUS1_VBUS_OVH		BIT(5)
-#define SM5803_STATUS1_CHG_DET		BIT(6)
-#define SM5803_STATUS1_BAT_DET		BIT(7)
-
-#define SM5803_REG_STATUS2		0x02
-#define SM5803_STATUS2_BAT_DET_FG	BIT(1)
-#define SM5803_STATUS2_VBAT_SHORT	BIT(0)
-
-#define SM5803_REG_INT1_REQ			0x05
-#define SM5803_REG_INT1_EN			0x0A
-#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT	BIT(0)
-#define SM5803_INT1_CHG				BIT(2)
-#define SM5803_INT1_BAT				BIT(3)
-#define SM5803_INT1_CLS_OC			BIT(4)
-#define SM5803_INT1_SLV_DET			BIT(5)
-#define SM5803_INT1_SWL_DISCH			BIT(6)
-#define SM5803_INT1_PREREG			BIT(7)
-
-#define SM5803_REG_INT2_REQ		0x06
-#define SM5803_REG_INT2_EN		0x0B
-#define SM5803_INT2_VBATSNSP		BIT(0)
-#define SM5803_INT2_IBAT_DISCHG		BIT(1)
-#define SM5803_INT2_IBAT_CHG		BIT(2)
-#define SM5803_INT2_IBUS		BIT(3)
-#define SM5803_INT2_VBUS		BIT(4)
-#define SM5803_INT2_VCHGPWR		BIT(5)
-#define SM5803_INT2_VSYS		BIT(6)
-#define SM5803_INT2_TINT		BIT(7)
-
-#define SM5803_REG_INT3_REQ			0x07
-#define SM5803_REG_INT3_EN			0x0C
-#define SM5803_INT3_GPADC0			BIT(0)
-#define SM5803_INT3_BFET_PWR_LIMIT		BIT(1)
-#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT	BIT(2)
-#define SM5803_INT3_SPARE			BIT(3)
-#define SM5803_INT3_VBUS_PWR_LIMIT		BIT(4)
-#define SM5803_INT3_IBAT			BIT(5)
-
-#define SM5803_REG_INT4_REQ		0x08
-#define SM5803_REG_INT4_EN		0x0D
-#define SM5803_INT4_CHG_FAIL		BIT(0)
-#define SM5803_INT4_CHG_DONE		BIT(1)
-#define SM5803_INT4_CHG_START		BIT(2)
-#define SM5803_INT4_SLP_EXIT		BIT(3)
-#define SM5803_INT4_OTG_FAIL		BIT(4)
-#define SM5803_INT4_CHG_ILIM		BIT(5)
-#define SM5803_INT4_IBAT_CC		BIT(6)
-#define SM5803_INT4_CC			BIT(7)
-
-#define SM5803_REG_MISC_CONFIG		0x15
-#define SM5803_MISC_INV_INT		BIT(0)
-#define SM5803_INT_CLEAR_MODE		BIT(1)
-#define SM5803_INT_MASK_MODE		BIT(2)
-
-#define SM5803_REG_PLATFORM		0x18
-#define SM5803_PLATFORM_ID		GENMASK(4, 0)
-
-#define SM5803_REG_REFERENCE		0x20
-#define SM5803_REFERENCE_LDO3P3_PGOOD	BIT(4)
-#define SM5803_REFERENCE_LDO5_PGOOD	BIT(5)
-
-#define SM5803_REG_CLOCK_SEL		0x2A
-#define SM5803_CLOCK_SEL_LOW		BIT(0)
-
-#define SM5803_REG_GPIO0_CTRL		0x30
-#define SM5803_GPIO0_VAL		BIT(0)
-#define SM5803_GPIO0_MODE_MASK		GENMASK(2, 1)
-#define SM5803_GPIO0_OPEN_DRAIN_EN	BIT(6)
-#define SM5803_CHG_DET_OPEN_DRAIN_EN	BIT(7)
-
-#define SM5803_REG_VBATSNSP_MEAS_MSB	0x40
-#define SM5803_REG_VBATSNSP_MEAS_LSB	0x41
-
-enum sm5803_gpio0_modes {
-	GPIO0_MODE_PROCHOT,
-	GPIO0_MODE_OUTPUT,
-	GPIO0_MODE_INPUT
-};
-
-#define SM5803_REG_BFET_PWR_MAX_TH		0x35
-#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH	0x36
-
-#define SM5803_REG_PORTS_CTRL		0x40
-#define SM5803_PORTS_VBUS_DISCH		BIT(0)
-#define SM5803_PORTS_VBUS_PULLDOWN	BIT(1)
-#define SM5803_PORTS_VBUS_SNS_DISCH	BIT(2)
-#define SM5803_PORTS_VBUS_SNS_PULLDOWN	BIT(3)
-
-/* ADC Registers (address 0x31) */
-
-/*
- * Note: Some register bits must be enabled for the DC-DC converter to properly
- * handle transitions.
- */
-#define SM5803_REG_GPADC_CONFIG1	0x01
-#define SM5803_GPADCC1_VBATSNSP_EN	BIT(0)
-#define SM5803_GPADCC1_IBAT_DIS_EN	BIT(1)
-#define SM5803_GPADCC1_IBAT_CHG_EN	BIT(2)
-#define SM5803_GPADCC1_IBUS_EN		BIT(3)
-#define SM5803_GPADCC1_VBUS_EN		BIT(4)
-#define SM5803_GPADCC1_VCHGPWR_EN	BIT(5)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_VSYS_EN		BIT(6)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_TINT_EN		BIT(7)
-
-#define SM5803_REG_GPADC_CONFIG2	0x02
-
-#define SM5803_REG_PSYS1		0x04
-#define SM5803_PSYS1_DAC_EN		BIT(0)
-
-/* Note: Threshold registers all assume lower 2 bits are 0 */
-#define SM5803_REG_VBUS_LOW_TH		0x1A
-#define SM5803_REG_VBATSNSP_MAX_TH  0x26
-#define SM5803_REG_VBUS_HIGH_TH		0x2A
-#define SM5803_REG_VCHG_PWR_LOW_TH	0x1B
-#define SM5803_REG_VCHG_PWR_HIGH_TH	0x2B
-#define SM5803_REG_TINT_LOW_TH		0x1D
-#define SM5803_REG_TINT_HIGH_TH		0x2D
-
-/*
- * Vbus levels increment in 23.4 mV, set thresholds to below 3.5V and above 4.0V
- * to mirror what TCPCI uses for Vbus present indication
- */
-#define SM5803_VBUS_LOW_LEVEL		0x25
-#define SM5803_VBUS_HIGH_LEVEL		0x2C
-
-
-
-/*
- * TINT thresholds.  TINT steps are in 0.43 K with the upper threshold set to
- * 360 K and lower threshold to de-assert PROCHOT at 330 K.
- */
-#define SM5803_TINT_LOW_LEVEL		0xBF
-#define SM5803_TINT_HIGH_LEVEL		0xD1
-
-#define SM5803_TINT_MAX_LEVEL		0xFF
-#define SM5803_TINT_MIN_LEVEL		0x00
-
-/*
- * Set minimum thresholds for VBUS_PWR_LOW_TH interrupt generation
- * 2S battery 9.4v
- * 3S battery 14.1V VBUS_PWR MIN TH
- */
-#define SM5803_VBAT_PWR_MINTH_3S_LEVEL 0x9B
-#define SM5803_VBAT_PWR_MINTH_2S_LEVEL 0x9B
-
-/*
- * Set thresholds for VBATSNSP_MAX_TH GPADC interrupt generation
- * 2S battery 9v
- * 3S battery 13.3V
- */
-#define SM5803_VBAT_SNSP_MAXTH_3S_LEVEL 0xD8
-#define SM5803_VBAT_SNSP_MAXTH_2S_LEVEL 0xDC
-
-/* IBAT levels - The IBAT levels increment in 7.32mA */
-#define SM5803_REG_IBAT_CHG_MEAS_MSB		0x44
-#define SM5803_REG_IBAT_CHG_MEAS_LSB		0x45
-#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB	0xC4
-#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB	0xC5
-#define SM5803_IBAT_CHG_MEAS_LSB	GENMASK(1, 0)
-
-/* IBUS levels - The IBUS levels increment in 7.32mA */
-#define SM5803_REG_IBUS_CHG_MEAS_MSB	0x46
-#define SM5803_REG_IBUS_CHG_MEAS_LSB	0x47
-#define SM5803_IBUS_CHG_MEAS_LSB	GENMASK(1, 0)
-
-#define SM5803_REG_VBUS_MEAS_MSB	0x48
-#define SM5803_REG_VBUS_MEAS_LSB	0x49
-#define SM5803_VBUS_MEAS_LSB		GENMASK(1, 0)
-#define SM5803_VBUS_MEAS_BAT_DET	BIT(2)
-#define SM5803_VBUS_MEAS_VBUS_SHORT	BIT(4)
-#define SM5803_VBUS_MEAS_OV_TEMP	BIT(5)
-#define SM5803_VBUS_MEAS_CHG_DET	BIT(6)
-
-/* VCHGPWR levels - The VCHGPWR levels increment in 23.4mV steps. */
-#define SM5803_REG_VCHG_PWR_MSB		0x4A
-
-#define SM5803_REG_TINT_MEAS_MSB	0x4E
-
-/* VSYS levels - The VSYS levels increment in  23.4mV steps. */
-#define SM5803_REG_VSYS_MEAS_MSB	0x4C
-#define SM5803_REG_VSYS_MEAS_LSB	0x4D
-#define SM5803_REG_VSYS_AVG_MEAS_MSB	0xCC
-#define SM5803_REG_VSYS_AVG_MEAS_LSB	0xCD
-#define SM5803_VSYS_MEAS_LSB		GENMASK(1, 0)
-
-/* Charger registers (address 0x32) */
-
-#define SM5803_REG_CC_CONFIG1		0x01
-#define SM5803_CC_CONFIG1_SD_PWRUP	BIT(3)
-
-#define SM5803_REG_FLOW1		0x1C
-#define SM5803_FLOW1_MODE		GENMASK(1, 0)
-#define SM5803_FLOW1_DIRECTCHG_SRC_EN	BIT(2)
-#define SM5803_FLOW1_LINEAR_CHARGE_EN	BIT(3)
-#define SM5803_FLOW1_USB_SUSP		BIT(7)
-
-enum sm5803_charger_modes {
-	CHARGER_MODE_DISABLED,
-	CHARGER_MODE_SINK,
-	CHARGER_MODE_RESERVED,
-	CHARGER_MODE_SOURCE,
-};
-
-#define SM5803_REG_FLOW2		0x1D
-#define SM5803_FLOW2_AUTO_TRKL_EN	BIT(0)
-#define SM5803_FLOW2_AUTO_PRECHG_EN	BIT(1)
-#define SM5803_FLOW2_AUTO_FASTCHG_EN	BIT(2)
-#define SM5803_FLOW2_AUTO_ENABLED	GENMASK(2, 0)
-#define SM5803_FLOW2_FW_TRKL_CMD	BIT(3)
-#define SM5803_FLOW2_FW_PRECHG_CMD	BIT(4)
-#define SM5803_FLOW2_FW_FASTCHG_CMD	BIT(5)
-#define SM5803_FLOW2_HOST_MODE_EN	BIT(6)
-#define SM5803_FLOW2_AUTO_CHGEN_SET	BIT(7)
-
-#define SM5803_REG_FLOW3		0x1E
-#define SM5803_FLOW3_SWITCH_BCK_BST	BIT(0)
-#define SM5803_FLOW3_FW_SWITCH_RESUME	BIT(1)
-#define SM5803_FLOW3_FW_SWITCH_PAUSE	BIT(2)
-#define SM5803_FLOW3_SOFT_DISABLE_EN	BIT(3)
-
-#define SM5803_REG_SWITCHER_CONF	0x1F
-#define SM5803_SW_BCK_BST_CONF_AUTO	BIT(0)
-
-#define SM5803_REG_ANA_EN1		0x21
-#define SM5803_ANA_EN1_CLS_DISABLE	BIT(7)
-
-/*
- * Input current limit is CHG_ILIM_RAW *100 mA
- */
-#define SM5803_REG_CHG_ILIM		0x24
-#define SM5803_CHG_ILIM_RAW		GENMASK(4, 0)
-#define SM5803_CURRENT_STEP		100
-#define SM5803_REG_TO_CURRENT(r)	((r) * SM5803_CURRENT_STEP)
-#define SM5803_CURRENT_TO_REG(c)	((c) / SM5803_CURRENT_STEP)
-
-/*
- * DPM Voltage loop regulation contains the 8 bits with MSB register
- * and the lower 3 bits with LSB register.
- * The regulation value is 2.72 V + DPM_VL_SET * 10mV
- */
-#define SM5803_REG_DPM_VL_SET_MSB		0x26
-#define SM5803_REG_DPM_VL_SET_LSB		0x27
-
-/*
- * Output voltage uses the same equation as Vsys
- * Lower saturation value is 3 V, upper 20.5 V
- */
-#define SM5803_REG_VPWR_MSB		0x30
-#define SM5803_REG_DISCH_CONF2		0x31
-#define SM5803_DISCH_CONF5_VPWR_LSB	GENMASK(2, 0)
-
-/*
- * Output current limit is CLS_LIMIT * 50 mA and saturates to 3.2 A
- */
-#define SM5803_REG_DISCH_CONF5		0x34
-#define SM5803_DISCH_CONF5_CLS_LIMIT	GENMASK(6, 0)
-#define SM5803_CLS_CURRENT_STEP		50
-
-#define SM5803_REG_DISCH_CONF6		0x35
-#define SM5803_DISCH_CONF6_RAMPS_DIS	BIT(0)
-#define SM5803_DISCH_CONF6_SMOOTH_DIS	BIT(1)
-
-/*
- * Vsys is 11 bits, with the lower 3 bits in the LSB register.
- * The pre-regulation value is 2.72 V + Vsys_prereg * 10 mV
- * Lower saturation value is 3V, upper is 20V
- */
-#define SM5803_REG_VSYS_PREREG_MSB	0x36
-#define SM5803_REG_VSYS_PREREG_LSB	0x37
-#define SM5803_VOLTAGE_STEP		10
-#define SM5803_VOLTAGE_SHIFT		2720
-#define SM5803_REG_TO_VOLTAGE(r)	(SM5803_VOLTAGE_SHIFT + \
-					 (r) * SM5803_VOLTAGE_STEP)
-#define SM5803_VOLTAGE_TO_REG(v)	(((v) - SM5803_VOLTAGE_SHIFT) \
-					 / SM5803_VOLTAGE_STEP)
-
-/*
- * Precharge Termination threshold.
- */
-#define SM5803_REG_PRE_FAST_CONF_REG1	0x39
-#define SM5803_VBAT_PRE_TERM_MIN_DV	23
-/* 3.8V+ gets rounded to 4V */
-#define SM5803_VBAT_PRE_TERM_MAX_DV	38
-#define SM5803_VBAT_PRE_TERM		GENMASK(7, 4)
-#define SM5803_VBAT_PRE_TERM_SHIFT	4
-
-/*
- * Vbat for fast charge uses the same equation as Vsys
- * Lower saturation value is 3V, upper is dependent on number of cells
- */
-#define SM5803_REG_VBAT_FAST_MSB	0x3A
-#define SM5803_REG_VBAT_FAST_LSB	0x3B
-
-/*
- * Fast charge current limit is ICHG_FAST * 100 mA
- * Value read back may be adjusted if tempearture limits are exceeded
- */
-#define SM5803_REG_FAST_CONF4		0x3C
-#define SM5803_CONF4_ICHG_FAST		GENMASK(5, 0)
-
-/* Fast charge Termination */
-#define SM5803_REG_FAST_CONF5		0x3D
-#define SM5803_CONF5_IBAT_EOC_TH	GENMASK(3, 0)
-
-/* IR drop compensation */
-#define SM5803_REG_IR_COMP1		0x3F
-#define SM5803_IR_COMP_RES_SET_MSB	GENMASK(7, 6)
-#define SM5803_IR_COMP_RES_SET_MSB_SHIFT 6
-#define SM5803_IR_COMP_EN		BIT(5)
-
-/* LSB is in 1.67mOhm steps. */
-#define SM5803_REG_IR_COMP2		0x40
-
-/* Precharge current limit is also intervals of 100 mA */
-#define SM5803_REG_PRECHG		0x41
-#define SM5803_PRECHG_ICHG_PRE_SET	GENMASK(5, 0)
-
-#define SM5803_REG_LOG1			0x42
-#define SM5803_BATFET_ON		BIT(2)
-
-#define SM5803_REG_LOG2			0x43
-#define SM5803_ISOLOOP_ON		BIT(1)
-
-#define SM5803_REG_STATUS_CHG_REG	0x48
-#define SM5803_STATUS_CHG_BATT_REMOVAL	BIT(0)
-#define SM5803_STATUS_CHG_CHG_REMOVAL	BIT(1)
-#define SM5803_STATUS_CHG_BATTEMP_NOK	BIT(2)
-#define SM5803_STATUS_CHG_CHGWDG_EXP	BIT(3)
-#define SM5803_STATUS_CHG_VBUS_OC	BIT(4)
-#define SM5803_STATUS_CHG_OV_VBAT	BIT(5)
-#define SM5803_STATUS_CHG_TIMEOUT	BIT(6)
-#define SM5803_STATUS_CHG_OV_ITEMP	BIT(7)
-
-#define SM5803_REG_STATUS_DISCHG	0x49
-#define SM5803_STATUS_DISCHG_BATT_REM	BIT(0)
-#define SM5803_STATUS_DISCHG_UV_VBAT	BIT(1)
-#define SM5803_STATUS_DISCHG_VBUS_OC	BIT(2)
-#define SM5803_STATUS_DISCHG_VBUS_PWR	GENMASK(4, 3)
-#define SM5803_STATUS_DISCHG_ISO_CURR	BIT(5)
-#define SM5803_STATUS_DISCHG_VBUS_SHORT	BIT(6)
-#define SM5803_STATUS_DISCHG_OV_ITEMP	BIT(7)
-
-#define SM5803_REG_CHG_MON_REG		0x5C
-#define SM5803_DPM_LOOP_EN		BIT(0)
-
-#define SM5803_REG_PHOT1		0x72
-#define SM5803_PHOT1_IBAT_PHOT_COMP_EN	BIT(0)
-#define SM5803_PHOT1_IBUS_PHOT_COMP_EN	BIT(1)
-#define SM5803_PHOT1_VSYS_MON_EN	BIT(2)
-#define SM5803_PHOT1_VBUS_MON_EN	BIT(3)
-#define SM5803_PHOT1_COMPARATOR_EN	GENMASK(3, 0)
-#define SM5803_PHOT1_DURATION		GENMASK(6, 4)
-#define SM5803_PHOT1_DURATION_SHIFT	4
-#define SM5803_PHOT1_IRQ_MODE		BIT(7)
-
-#define CHARGER_NAME "sm5803"
-
-#define CHARGE_V_MAX 20000
-#define CHARGE_V_MIN SM5803_VOLTAGE_SHIFT
-#define CHARGE_V_STEP SM5803_VOLTAGE_STEP
-
-#define CHARGE_I_MAX 6300
-#define CHARGE_I_MIN 0
-#define CHARGE_I_STEP SM5803_CURRENT_STEP
-
-#define INPUT_I_MAX 3100
-#define INPUT_I_MIN 0
-#define INPUT_I_STEP SM5803_CURRENT_STEP
-
-/* Expose cached Vbus presence */
-int sm5803_is_vbus_present(int chgnum);
-
-/* Expose functions to control charger's GPIO and CHG_DET configuration */
-enum ec_error_list sm5803_configure_gpio0(int chgnum,
-					  enum sm5803_gpio0_modes mode, int od);
-enum ec_error_list sm5803_set_gpio0_level(int chgnum, int level);
-enum ec_error_list sm5803_configure_chg_det_od(int chgnum, int enable);
-enum ec_error_list sm5803_get_chg_det(int chgnum, int *chg_det);
-
-/* Expose Vbus discharge function */
-enum ec_error_list sm5803_set_vbus_disch(int chgnum, int enable);
-enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable);
-
-void sm5803_hibernate(int chgnum);
-void sm5803_interrupt(int chgnum);
-
-/**
- * Return whether ACOK is high or low.
- *
- * @param chgnum index into chg_chips table.
- * @param acok will be set to true if ACOK is asserted, otherwise false.
- * @return EC_SUCCESS, error otherwise.
- */
-enum ec_error_list sm5803_is_acok(int chgnum, bool *acok);
-
-/* Expose low power mode functions */
-void sm5803_disable_low_power_mode(int chgnum);
-void sm5803_enable_low_power_mode(int chgnum);
-
-extern const struct charger_drv sm5803_drv;
-
-/* Expose interrupt handler for processing in PD_INT task when needed */
-void sm5803_handle_interrupt(int chgnum);
-
-#endif
diff --git a/driver/charger/sy21612.c b/driver/charger/sy21612.c
deleted file mode 100644
index 7bc6caa4ea..0000000000
--- a/driver/charger/sy21612.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SILERGY SY21612 buck-boost converter driver.
- */
-
-
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "sy21612.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-static int sy21612_clear_set_reg(int reg, int clear, int set)
-{
-	int val, old_val, rv;
-
-	rv = i2c_read8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, reg, &old_val);
-	if (rv)
-		return rv;
-
-	val = old_val;
-	val &= ~clear;
-	val |= set;
-
-	if (val != old_val || clear || set)
-		rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS,
-				reg, val);
-
-	return rv;
-}
-
-static int sy21612_read(int reg, int *val)
-{
-	return i2c_read8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, reg, val);
-}
-
-int sy21612_enable_regulator(int enable)
-{
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_REG_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_REG_EN, 0);
-}
-
-int sy21612_enable_adc(int enable)
-{
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_ADC_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_ADC_EN, 0);
-}
-
-int sy21612_set_adc_mode(int auto_mode)
-{
-	return auto_mode ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_ADC_AUTO_MODE) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_ADC_AUTO_MODE, 0);
-}
-
-int sy21612_set_vbus_discharge(int auto_discharge)
-{
-	return auto_discharge ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_VBUS_NDISCHG, 0) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_VBUS_NDISCHG);
-}
-
-int sy21612_set_switching_freq(enum sy21612_switching_freq freq)
-{
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_FREQ_MASK,
-				     freq << SY21612_CTRL2_FREQ_SHIFT);
-}
-
-int sy21612_set_vbus_volt(enum sy21612_vbus_volt volt)
-{
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_MASK,
-				     volt << SY21612_CTRL2_VBUS_SHIFT);
-}
-
-int sy21612_set_vbus_adj(enum sy21612_vbus_adj adj)
-{
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_ADJ_MASK,
-				     adj << SY21612_CTRL2_VBUS_ADJ_SHIFT);
-}
-
-int sy21612_set_sink_mode(int sink_mode)
-{
-	return sink_mode ?
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      0, SY21612_PROT2_SINK_MODE) :
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      SY21612_PROT2_SINK_MODE, 0);
-}
-
-int sy21612_is_power_good(void)
-{
-	int reg;
-
-	if (sy21612_read(SY21612_STATE, &reg))
-		return 0;
-
-	return reg & SY21612_STATE_POWER_GOOD;
-}
-
-int sy21612_read_clear_int(void)
-{
-	int reg;
-
-	if (sy21612_read(SY21612_INT, &reg))
-		return 0;
-
-	return reg;
-}
-
-int sy21612_get_vbat_voltage(void)
-{
-	int reg;
-
-	if (sy21612_read(SY21612_VBAT_VOLT, &reg))
-		return 0;
-
-	return reg * 25000 / 255;
-}
-
-int sy21612_get_vbus_voltage(void)
-{
-	int reg;
-
-	if (sy21612_read(SY21612_VBUS_VOLT, &reg))
-		return 0;
-
-	return reg * 25000 / 255;
-}
-
-int sy21612_get_vbus_current(void)
-{
-	int reg;
-
-	if (sy21612_read(SY21612_VBUS_CURRENT, &reg))
-		return 0;
-
-	/*
-	 * delta V in range 0 ~ 67mV
-	 * sense resistor 10 mOhm
-	 */
-	return reg * 6700 / 255;
-}
-
-void sy21612_int(enum gpio_signal signal)
-{
-#ifdef HAS_TASK_SY21612
-	task_wake(TASK_ID_SY21612);
-#endif
-}
-
-#ifdef HAS_TASK_SY21612
-void sy21612_task(void *u)
-{
-	int flags;
-
-	while (1) {
-		task_wait_event(-1);
-		if (sy21612_read(SY21612_INT, &flags))
-			continue;
-		/* TODO: notify the error condition and enable regulator */
-		if (flags & SY21612_INT_VBUS_OCP)
-			CPUTS("buck-boost VBUS OCP\n");
-		if (flags & SY21612_INT_INDUCTOR_OCP)
-			CPUTS("buck-boost inductor OCP\n");
-		if (flags & SY21612_INT_UVP)
-			CPUTS("buck-boost UVP\n");
-		if (flags & SY21612_INT_OTP)
-			CPUTS("buck-boost OTP\n");
-	}
-}
-#endif
-
-#ifdef CONFIG_CMD_CHARGER
-static int command_sy21612(int argc, char **argv)
-{
-	int i, val, rv;
-
-	ccputs("sy21612 regs:\n");
-	for (i = 0; i < 9; i++) {
-		ccprintf("[%02x] ", i);
-		rv = sy21612_read(i, &val);
-		if (rv)
-			ccprintf(" x (%d)\n", rv);
-		else
-			ccprintf("%02x - %pb\n", val, BINARY_VALUE(val, 8));
-	}
-
-	ccprintf("vbat voltage: %d mV\n", sy21612_get_vbat_voltage());
-	ccprintf("vbus voltage: %d mV\n", sy21612_get_vbus_voltage());
-	ccprintf("vbus current: %d mA\n", sy21612_get_vbus_current());
-
-	return 0;
-}
-DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612,
-			NULL, NULL);
-#endif
diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h
deleted file mode 100644
index befb8e6a35..0000000000
--- a/driver/charger/sy21612.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SILERGY SY21612 buck-boost converter driver.
- */
-
-#ifndef __CROS_EC_SY21612_H
-#define __CROS_EC_SY21612_H
-
-#include "gpio.h"
-
-#ifndef SY21612_ADDR_FLAGS
-#define SY21612_ADDR_FLAGS		0x71
-#endif
-
-enum sy21612_switching_freq {
-	SY21612_FREQ_250KHZ = 0,
-	SY21612_FREQ_500KHZ,
-	SY21612_FREQ_750KHZ,
-	SY21612_FREQ_1MHZ
-};
-
-enum sy21612_vbus_volt {
-	SY21612_VBUS_5V = 2,
-	SY21612_VBUS_7V,
-	SY21612_VBUS_9V,
-	SY21612_VBUS_12V,
-	SY21612_VBUS_15V,
-	SY21612_VBUS_20V,
-};
-
-enum sy21612_vbus_adj {
-	SY21612_VBUS_M2_5 = 0,
-	SY21612_VBUS_M1_25,
-	SY21612_VBUS_0,
-	SY21612_VBUS_1_25,
-	SY21612_VBUS_2_5,
-	SY21612_VBUS_3_75,
-	SY21612_VBUS_5,
-};
-
-#define SY21612_CTRL1        0x00
-#define SY21612_CTRL1_REG_EN         BIT(7)
-#define SY21612_CTRL1_LOW_BAT_MASK   (7 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_2V  (0 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_7V  BIT(4)
-#define SY21612_CTRL1_LOW_BAT_11_2V  (2 << 4)
-#define SY21612_CTRL1_LOW_BAT_11_7V  (3 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_0V  (4 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_5V  (5 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_0V  (6 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_5V  (7 << 4)
-#define SY21612_CTRL1_ADC_EN         BIT(3)
-#define SY21612_CTRL1_ADC_AUTO_MODE  BIT(2)
-#define SY21612_CTRL1_VBUS_NDISCHG   BIT(1)
-
-#define SY21612_CTRL2        0x01
-#define SY21612_CTRL2_FREQ_MASK      (3 << 6)
-#define SY21612_CTRL2_FREQ_SHIFT     6
-#define SY21612_CTRL2_FREQ_250K      (0 << 6)
-#define SY21612_CTRL2_FREQ_500K      BIT(6)
-#define SY21612_CTRL2_FREQ_750K      (2 << 6)
-#define SY21612_CTRL2_FREQ_1M        (3 << 6)
-#define SY21612_CTRL2_VBUS_MASK      (7 << 3)
-#define SY21612_CTRL2_VBUS_SHIFT     3
-#define SY21612_CTRL2_VBUS_5V        (2 << 3)
-#define SY21612_CTRL2_VBUS_7V        (3 << 3)
-#define SY21612_CTRL2_VBUS_9V        (4 << 3)
-#define SY21612_CTRL2_VBUS_12V       (5 << 3)
-#define SY21612_CTRL2_VBUS_15V       (6 << 3)
-#define SY21612_CTRL2_VBUS_20V       (7 << 3)
-#define SY21612_CTRL2_VBUS_ADJ_MASK  7
-#define SY21612_CTRL2_VBUS_ADJ_SHIFT 0
-#define SY21612_CTRL2_VBUS_ADJ_M2_5  0
-#define SY21612_CTRL2_VBUS_ADJ_M1_25 1
-#define SY21612_CTRL2_VBUS_ADJ_0     2
-#define SY21612_CTRL2_VBUS_ADJ_1_25  3
-#define SY21612_CTRL2_VBUS_ADJ_2_5   4
-#define SY21612_CTRL2_VBUS_ADJ_3_75  5
-#define SY21612_CTRL2_VBUS_ADJ_5     6
-
-#define SY21612_PROT1        0x02
-#define SY21612_PROT1_I_THRESH_MASK   (7 << 5)
-#define SY21612_PROT1_I_THRESH_18MV   (0 << 5)
-#define SY21612_PROT1_I_THRESH_22MV   BIT(5)
-#define SY21612_PROT1_I_THRESH_27MV   (2 << 5)
-#define SY21612_PROT1_I_THRESH_31MV   (3 << 5)
-#define SY21612_PROT1_I_THRESH_36MV   (4 << 5)
-#define SY21612_PROT1_I_THRESH_45MV   (5 << 5)
-#define SY21612_PROT1_I_THRESH_54MV   (6 << 5)
-#define SY21612_PROT1_I_THRESH_64MV   (7 << 5)
-#define SY21612_PROT1_OVP_THRESH_MASK (3 << 3)
-#define SY21612_PROT1_OVP_THRESH_110  (0 << 3)
-#define SY21612_PROT1_OVP_THRESH_115  BIT(3)
-#define SY21612_PROT1_OVP_THRESH_120  (2 << 3)
-#define SY21612_PROT1_OVP_THRESH_125  (3 << 3)
-#define SY21612_PROT1_UVP_THRESH_MASK (3 << 1)
-#define SY21612_PROT1_UVP_THRESH_50   (0 << 1)
-#define SY21612_PROT1_UVP_THRESH_60   BIT(1)
-#define SY21612_PROT1_UVP_THRESH_70   (2 << 1)
-#define SY21612_PROT1_UVP_THRESH_80   (3 << 1)
-
-#define SY21612_PROT2        0x03
-#define SY21612_PROT2_I_LIMIT_MASK    (3 << 6)
-#define SY21612_PROT2_I_LIMIT_6A      (0 << 6)
-#define SY21612_PROT2_I_LIMIT_8A      (2 << 6)
-#define SY21612_PROT2_I_LIMIT_10A     (3 << 6)
-#define SY21612_PROT2_OCP_AUTORECOVER BIT(5)
-#define SY21612_PROT2_UVP_AUTORECOVER BIT(4)
-#define SY21612_PROT2_OTP_AUTORECOVER BIT(3)
-#define SY21612_PROT2_SINK_MODE       BIT(2)
-
-#define SY21612_STATE        0x04
-#define SY21612_STATE_POWER_GOOD      BIT(7)
-#define SY21612_STATE_VBAT_LT_VBUS    BIT(6)
-#define SY21612_STATE_VBAT_LOW        BIT(5)
-
-#define SY21612_INT          0x05
-#define SY21612_INT_ADC_READY         BIT(7)
-#define SY21612_INT_VBUS_OCP          BIT(6)
-#define SY21612_INT_INDUCTOR_OCP      BIT(5)
-#define SY21612_INT_UVP               BIT(4)
-#define SY21612_INT_OTP               BIT(3)
-
-/* Battery voltage range: 0 ~ 25V */
-#define SY21612_VBAT_VOLT    0x06
-
-/* VBUS voltage range: 0 ~ 25V */
-#define SY21612_VBUS_VOLT    0x07
-
-/* Output current sense voltage range 0 ~ 67mV */
-#define SY21612_VBUS_CURRENT 0x08
-
-/* Enable or disable the regulator */
-int sy21612_enable_regulator(int enable);
-/* Enable internal adc */
-int sy21612_enable_adc(int enable);
-/* Set ADC mode to single or auto */
-int sy21612_set_adc_mode(int auto_mode);
-/* Enable VBUS auto discharge when regulator is disabled */
-int sy21612_set_vbus_discharge(int auto_discharge);
-/* Set buck-boost switching frequency */
-int sy21612_set_switching_freq(enum sy21612_switching_freq freq);
-/* Set VBUS output voltage */
-int sy21612_set_vbus_volt(enum sy21612_vbus_volt volt);
-/* Adjust VBUS output voltage */
-int sy21612_set_vbus_adj(enum sy21612_vbus_adj adj);
-/* Set bidirection mode */
-int sy21612_set_sink_mode(int sink_mode);
-/* Get power good status */
-int sy21612_is_power_good(void);
-/* Read and clear interrupt flags */
-int sy21612_read_clear_int(void);
-/* Get VBUS voltage in mV */
-int sy21612_get_vbat_voltage(void);
-/* Get VBUS voltage in mV */
-int sy21612_get_vbus_voltage(void);
-/* Get VBUS current in mA */
-int sy21612_get_vbus_current(void);
-/* Interrupt handler */
-void sy21612_int(enum gpio_signal signal);
-
-#endif /* __CROS_EC_SY21612_H */
diff --git a/driver/fingerprint/OWNERS b/driver/fingerprint/OWNERS
deleted file mode 100644
index ba92c193e0..0000000000
--- a/driver/fingerprint/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../common/fpsensor/OWNERS
diff --git a/driver/fingerprint/build.mk b/driver/fingerprint/build.mk
deleted file mode 100644
index 6cb9dc7adb..0000000000
--- a/driver/fingerprint/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Build fingerprint drivers
-
-# Note that this variable includes the trailing "/"
-_fingerprint_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-include $(_fingerprint_cur_dir)elan/build.mk
-include $(_fingerprint_cur_dir)fpc/build.mk
diff --git a/driver/fingerprint/elan/build.mk b/driver/fingerprint/elan/build.mk
deleted file mode 100644
index 2e4ad2d46f..0000000000
--- a/driver/fingerprint/elan/build.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Build for ELAN fingerprint drivers
-
-# Note that this variable includes the trailing "/"
-_elan_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-ifneq (,$(filter rw,$(CONFIG_FP_SENSOR_ELAN80) $(CONFIG_FP_SENSOR_ELAN515)))
-
-# Make sure output directory is created (in build directory)
-dirs-y+="$(_elan_cur_dir)"
-
-include $(_elan_cur_dir)../../../private/fingerprint/elan/build.mk
-
-all-obj-rw+=$(_elan_cur_dir)elan_private.o
-all-obj-rw+=$(_elan_cur_dir)elan_sensor_pal.o
-
-endif
diff --git a/driver/fingerprint/elan/elan_private.c b/driver/fingerprint/elan/elan_private.c
deleted file mode 100644
index 555ad14ba0..0000000000
--- a/driver/fingerprint/elan/elan_private.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include "common.h"
-#include "console.h"
-#include "endian.h"
-#include "gpio.h"
-#include "link_defs.h"
-#include "spi.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "shared_mem.h"
-#include "math_util.h"
-#include "fpsensor.h"
-#include "cryptoc/util.h"
-
-#include "elan_sensor.h"
-#include "elan_setting.h"
-#include "elan_sensor_pal.h"
-
-static uint16_t errors;
-
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
-
-/* Sensor description */
-static struct ec_response_fp_info ec_fp_sensor_info = {
-	/* Sensor identification */
-	.vendor_id = VID,
-	.product_id = PID,
-	.model_id = MID,
-	.version = VERSION,
-	/* Image frame characteristics */
-	.frame_size = FP_SENSOR_RES_X * FP_SENSOR_RES_Y,
-	.pixel_format = V4L2_PIX_FMT_GREY,
-	.width = FP_SENSOR_RES_X,
-	.height = FP_SENSOR_RES_Y,
-	.bpp = FP_SENSOR_RES_BPP,
-};
-
-/**
- * set fingerprint sensor into power saving mode
- */
-void fp_sensor_low_power(void)
-{
-	elan_woe_mode();
-}
-
-/**
- * Reset and initialize the sensor IC
- */
-int fp_sensor_init(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-
-	errors = 0;
-	elan_execute_reset();
-	algorithm_parameter_setting();
-	if (elan_execute_calibration() < 0)
-		errors |= FP_ERROR_INIT_FAIL;
-	if (elan_woe_mode() != 0)
-		errors |= FP_ERROR_SPI_COMM;
-
-	return EC_SUCCESS;
-}
-
-/**
- * Deinitialize the sensor IC
- */
-int fp_sensor_deinit(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_fp_deinit();
-}
-
-/**
- * Fill the 'ec_response_fp_info' buffer with the sensor information
- *
- * @param[out] resp      retrieve the version, sensor and template information
- *
- * @return EC_SUCCESS on success otherwise error.
- */
-int fp_sensor_get_info(struct ec_response_fp_info *resp)
-{
-	int ret = 0;
-
-	CPRINTF("========%s=======\n", __func__);
-	memcpy(resp, &ec_fp_sensor_info, sizeof(struct ec_response_fp_info));
-	elan_sensor_get_alg_info(resp);
-	resp->errors |= errors;
-	CPRINTF("##%s## FrameSize=%d, errors=0x%04x\n", __func__,
-		resp->frame_size, resp->errors);
-
-	return ret;
-}
-
-/**
- * Compares given finger image against enrolled templates.
- *
- * @param[in]  templ            a pointer to the array of template buffers.
- * @param[in]  templ_count      the number of buffers in the array of templates.
- * @param[in]  image            the buffer containing the finger image
- * @param[out] match_index      index of the matched finger in the template
- *                              array if any.
- * @param[out] update_bitmap    contains one bit per template, the bit is set if
- *                              the match has updated the given template.
- *
- * @return negative value on error, else one of the following code :
- * - EC_MKBP_FP_ERR_MATCH_NO on non-match
- * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
- *   new data
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
- * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
- *   to low image quality
- * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
- *   due to finger covering too little area of the sensor
- */
-int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
-		    int32_t *match_index, uint32_t *update_bitmap)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_match(templ, templ_count, image, match_index,
-			  update_bitmap);
-}
-
-/**
- * start a finger enrollment session and initialize enrollment data
- *
- * @return 0 on success.
- *
- */
-int fp_enrollment_begin(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_enrollment_begin();
-}
-
-/**
- * Generate a template from the finger whose enrollment has just being
- * completed.
- *
- * @param templ the buffer which will receive the template.
- *              templ can be set to NULL to abort the current enrollment
- *              process.
- *
- * @return 0 on success or a negative error code.
- */
-int fp_enrollment_finish(void *templ)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_enrollment_finish(templ);
-}
-
-/**
- * Adds fingerprint image to the current enrollment session.
- *
- * @param[in]  image             fingerprint image data
- * @param[out] completion        retrieve percentage of current enrollment
- *
- * @return a negative value on error or one of the following codes:
- * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
- * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
- *   advised to move finger
- * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to
- *   low image quality
- * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
- *   finger covering too little area of the sensor
- */
-int fp_finger_enroll(uint8_t *image, int *completion)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_enroll(image, completion);
-}
-
-/**
- * Put the sensor in its lowest power state.
- *
- * fp_sensor_configure_detect needs to be called to restore finger detection
- * functionality.
- */
-void fp_sensor_configure_detect(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-	elan_woe_mode();
-}
-
-/**
- * Acquires a fingerprint image with specific capture mode.
- *
- * @param[out] image_data    Memory buffer to retrieve fingerprint image data
- *                          Image_data is allocated by the caller and the size
- *                          is FP_SENSOR_IMAGE_SIZE.
- * @param[in]  mode         one of the FP_CAPTURE_ constants to get a specific
- *                          image type
- * - FP_CAPTURE_VENDOR_FORMAT: Full blown vendor-defined capture
- * - FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture
- * - FP_CAPTURE_PATTERN0: Self test pattern
- * - FP_CAPTURE_PATTERN1: Self test pattern
- * - FP_CAPTURE_QUALITY_TEST
- * - FP_CAPTURE_RESET_TEST
- * - FP_CAPTURE_TYPE_MAX
- *
- * @return
- * - 0 on success
- * - negative value on error
- * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
- * - FP_SENSOR_TOO_FAST on finger removed before image was captured
- * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
- */
-int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_sensor_acquire_image_with_mode(image_data, mode);
-}
-
-/**
- * Returns the status of the finger on the sensor.
- *
- * @return one of the following codes:
- * - FINGER_NONE
- * - FINGER_PARTIAL
- * - FINGER_PRESENT
- */
-enum finger_state fp_sensor_finger_status(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_sensor_finger_status();
-}
-
-/**
- * Runs a test for defective pixels.
- *
- * Should be triggered periodically by the client. The maintenance command can
- * take several hundred milliseconds to run.
- *
- * @return EC_ERROR_HW_INTERNAL on error (such as finger on sensor)
- * @return EC_SUCCESS on success
- */
-int fp_maintenance(void)
-{
-	CPRINTF("========%s=======\n", __func__);
-	return elan_fp_maintenance(&errors);
-}
diff --git a/driver/fingerprint/elan/elan_sensor.h b/driver/fingerprint/elan/elan_sensor.h
deleted file mode 100644
index 490b1acf16..0000000000
--- a/driver/fingerprint/elan/elan_sensor.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef CROS_EC_DRIVER_FINGERPRINT_ELAN_ELAN_SENSOR_H
-#define CROS_EC_DRIVER_FINGERPRINT_ELAN_ELAN_SENSOR_H
-#include "common.h"
-
-/* Sensor pixel resolution */
-#if defined(CONFIG_FP_SENSOR_ELAN80)
-#define FP_SENSOR_IMAGE_SIZE (80 * 80)
-#define FP_SENSOR_RES_X 80
-#define FP_SENSOR_RES_Y 80
-#if defined(CHIP_FAMILY_STM32F4)
-#define FP_ALGORITHM_TEMPLATE_SIZE 15000
-#elif defined(CHIP_FAMILY_STM32H7)
-#define FP_ALGORITHM_TEMPLATE_SIZE 40960
-#endif
-#define FP_MAX_FINGER_COUNT 3
-#elif defined(CONFIG_FP_SENSOR_ELAN515)
-#define FP_SENSOR_IMAGE_SIZE (52 * 150)
-#define FP_SENSOR_RES_X 52
-#define FP_SENSOR_RES_Y 150
-#if defined(CHIP_FAMILY_STM32F4)
-#define FP_ALGORITHM_TEMPLATE_SIZE 15000
-#elif defined(CHIP_FAMILY_STM32H7)
-#define FP_ALGORITHM_TEMPLATE_SIZE 67000
-#endif
-#define FP_MAX_FINGER_COUNT 3
-#endif
-#define FP_SENSOR_RES_BPP (8)
-
-/**
- * Set ELAN fingerprint sensor into finger touch detects and power saving mode
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_woe_mode(void);
-
-/**
- * Set ELAN fingerprint sensor into the image sensing mode
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_sensing_mode(void);
-
-/**
- * To initialize parameters of the ELAN matching algorithm
- *
- */
-void algorithm_parameter_setting(void);
-
-/**
- * Compares given finger image against enrolled templates.
- *
- * @param[in]  templ            a pointer to the array of template buffers.
- * @param[in]  templ_count      the number of buffers in the array of templates.
- * @param[in]  image            the buffer containing the finger image
- * @param[out] match_index      index of the matched finger in the template
- *                              array if any.
- * @param[out] update_bitmap    contains one bit per template, the bit is set if
- *                              the match has updated the given template.
- *
- * @return negative value on error, else one of the following code :
- * - EC_MKBP_FP_ERR_MATCH_NO on non-match
- * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
- *   new data
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
- * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
- *   to low image quality
- * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
- *   due to finger covering too little area of the sensor
- */
-int elan_match(void *templ, uint32_t templ_count, uint8_t *image,
-	       int32_t *match_index, uint32_t *update_bitmap);
-
-/**
- * start a finger enrollment session and initialize enrollment data
- *
- * @return 0 on success.
- *
- */
-int elan_enrollment_begin(void);
-
-/**
- * Adds fingerprint image to the current enrollment session.
- *
- * @param[in]  image        fingerprint image data
- * @param[out] completion   retrieve percentage of current enrollment
- *
- * @return a negative value on error or one of the following codes:
- * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
- * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
-     advised to move finger
- * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to
- *   low image quality
- * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
- *   finger covering too little area of the sensor
- */
-int elan_enroll(uint8_t *image, int *completion);
-
-/**
- * Acquires a fingerprint image with specific capture mode.
- *
- * @param[out] image_data   Memory buffer to retrieve fingerprint image data
- *                          Image_data is allocated by the caller and the size
- *                          is FP_SENSOR_IMAGE_SIZE.
- * @param[in]  mode         one of the FP_CAPTURE_ constants to get a
- *                          specific image type
- * - FP_CAPTURE_VENDOR_FORMAT: Full blown vendor-defined capture
- * - FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture
- * - FP_CAPTURE_PATTERN0: Self test pattern
- * - FP_CAPTURE_PATTERN1: Self test pattern
- * - FP_CAPTURE_QUALITY_TEST
- * - FP_CAPTURE_RESET_TEST
- * - FP_CAPTURE_TYPE_MAX
- *
- * @return
- * - 0 on success
- * - negative value on error
- * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
- * - FP_SENSOR_TOO_FAST on finger removed before image was captured
- * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
- */
-int elan_sensor_acquire_image_with_mode(uint8_t *image_data, int mode);
-
-/**
- * Returns the status of the finger on the sensor.
- *
- * @return one of the following codes:
- * - FINGER_NONE
- * - FINGER_PARTIAL
- * - FINGER_PRESENT
- */
-enum finger_state elan_sensor_finger_status(void);
-
-/**
- * Generate a template from the finger whose enrollment has just being
- * completed.
- *
- * @param templ the buffer which will receive the template.
- *              templ can be set to NULL to abort the current enrollment
- *              process.
- *
- * @return 0 on success or a negative error code.
- */
-int elan_enrollment_finish(void *templ);
-
-/**
- * Fill the 'ec_response_fp_alg_info' buffer with the sensor alg information
- *
- * @param[out] resp      retrieve the algorithm information
- *
- * @return EC_SUCCESS on success otherwise error.
- */
-int elan_sensor_get_alg_info(struct ec_response_fp_info *resp);
-
-/**
- * Runs a test for defective pixels.
- *
- * Should be triggered periodically by the client. The maintenance command can
- * take several hundred milliseconds to run.
- *
- * @return EC_ERROR_HW_INTERNAL on error (such as finger on sensor)
- * @return EC_SUCCESS on success
- */
-int elan_fp_maintenance(uint16_t *error_state);
-
-/**
- * Deinitialize the sensor IC.
- *
- * @return EC_SUCCESS on success otherwise error.
- */
-int elan_fp_deinit(void);
-#endif
diff --git a/driver/fingerprint/elan/elan_sensor_pal.c b/driver/fingerprint/elan/elan_sensor_pal.c
deleted file mode 100644
index b59368b835..0000000000
--- a/driver/fingerprint/elan/elan_sensor_pal.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ELAN Platform Abstraction Layer callbacks */
-
-#include <stddef.h>
-#include "common.h"
-#include "console.h"
-#include "endian.h"
-#include "fpsensor.h"
-#include "gpio.h"
-#include "link_defs.h"
-#include "spi.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "shared_mem.h"
-#include "math_util.h"
-#include "cryptoc/util.h"
-
-#include "elan_setting.h"
-#include "elan_sensor.h"
-#include "elan_sensor_pal.h"
-
-static uint8_t tx_buf[CONFIG_SPI_TX_BUF_SIZE] __uncached;
-static uint8_t rx_buf[CONFIG_SPI_RX_BUF_SIZE] __uncached;
-
-int elan_write_cmd(uint8_t fp_cmd)
-{
-	int rc = 0;
-
-	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-
-	tx_buf[0] = fp_cmd;
-	rc = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
-			     SPI_READBACK_ALL);
-	return rc;
-}
-
-int elan_read_cmd(uint8_t fp_cmd, uint8_t *regdata)
-{
-	int ret = 0;
-
-	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-
-	tx_buf[0] = fp_cmd; /* one byte data read */
-	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
-			      SPI_READBACK_ALL);
-	*regdata = rx_buf[1];
-
-	return ret;
-}
-
-int elan_spi_transaction(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len)
-{
-	int ret = 0;
-
-	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-
-	memcpy(tx_buf, tx, tx_len);
-	ret = spi_transaction(&spi_devices[0], tx_buf, tx_len, rx_buf, rx_len);
-	memcpy(rx, rx_buf, rx_len);
-
-	return ret;
-}
-
-int elan_write_register(uint8_t regaddr, uint8_t regdata)
-{
-	int ret = 0;
-
-	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-
-	tx_buf[0] = WRITE_REG_HEAD + regaddr; /* one byte data write */
-	tx_buf[1] = regdata;
-	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
-			      SPI_READBACK_ALL);
-	return ret;
-}
-
-int elan_write_page(uint8_t page)
-{
-	int ret = 0;
-
-	memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-	memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-
-	tx_buf[0] = PAGE_SEL;
-	tx_buf[1] = page;
-	ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
-			      SPI_READBACK_ALL);
-
-	return ret;
-}
-
-int elan_write_reg_vector(const uint8_t *reg_table, int length)
-{
-	int ret = 0;
-	int i = 0;
-	uint8_t write_regaddr;
-	uint8_t write_regdata;
-
-	for (i = 0; i < length; i = i + 2) {
-		write_regaddr = reg_table[i];
-		write_regdata = reg_table[i + 1];
-		ret = elan_write_register(write_regaddr, write_regdata);
-		if (ret < 0)
-			break;
-	}
-	return ret;
-}
-
-int raw_capture(uint16_t *short_raw)
-{
-	int ret = 0, i = 0, image_index = 0, index = 0;
-	int cnt_timer = 0;
-	int dma_loop = 0, dma_len = 0;
-	uint8_t regdata[4] = { 0 };
-	char *img_buf;
-
-	memset(short_raw, 0, sizeof(uint16_t) * IMAGE_TOTAL_PIXEL);
-
-	ret = shared_mem_acquire(sizeof(uint8_t) * IMG_BUF_SIZE, &img_buf);
-	if (ret) {
-		LOGE_SA("%s Can't get shared mem\n", __func__);
-		return ret;
-	}
-	memset(img_buf, 0, sizeof(uint8_t) * IMG_BUF_SIZE);
-
-	/* Write start scans command to fp sensor */
-	if (elan_write_cmd(START_SCAN) < 0) {
-		ret = ELAN_ERROR_SPI;
-		LOGE_SA("%s SPISendCommand( SSP2, START_SCAN ) fail ret = %d",
-			__func__, ret);
-		goto exit;
-	}
-
-	/* Polling scan status */
-	cnt_timer = 0;
-	while (1) {
-		usleep(1000);
-		cnt_timer++;
-		regdata[0] = SENSOR_STATUS;
-		elan_spi_transaction(regdata, 2, regdata, 2);
-		if (regdata[0] & 0x04)
-			break;
-
-		if (cnt_timer > POLLING_SCAN_TIMER) {
-			ret = ELAN_ERROR_SCAN;
-			LOGE_SA("%s regdata = 0x%x, fail ret = %d", __func__,
-				regdata[0], ret);
-			goto exit;
-		}
-	}
-
-	/* Read the image from fp sensor */
-	dma_loop = 4;
-	dma_len = IMG_BUF_SIZE / dma_loop;
-
-	for (i = 0; i < dma_loop; i++) {
-		memset(tx_buf, 0, CONFIG_SPI_TX_BUF_SIZE);
-		memset(rx_buf, 0, CONFIG_SPI_RX_BUF_SIZE);
-		tx_buf[0] = START_READ_IMAGE;
-		ret = spi_transaction(&spi_devices[0], tx_buf, 2, rx_buf,
-				      dma_len);
-		memcpy(&img_buf[dma_len * i], rx_buf, dma_len);
-	}
-
-	/* Remove dummy byte */
-	for (image_index = 1; image_index < IMAGE_WIDTH; image_index++)
-		memcpy(&img_buf[RAW_PIXEL_SIZE * image_index],
-		       &img_buf[RAW_DATA_SIZE * image_index], RAW_PIXEL_SIZE);
-
-	for (index = 0; index < IMAGE_TOTAL_PIXEL; index++)
-		short_raw[index] =
-			(img_buf[index * 2] << 8) + img_buf[index * 2 + 1];
-
-exit:
-	if (img_buf != NULL) {
-		always_memset(img_buf, 0, sizeof(uint8_t) * IMG_BUF_SIZE);
-		shared_mem_release(img_buf);
-	}
-
-	if (ret != 0)
-		LOGE_SA("%s error = %d", __func__, ret);
-
-	return ret;
-}
-
-int elan_execute_calibration(void)
-{
-	int retry_time = 0;
-	int ret = 0;
-
-	while (retry_time < REK_TIMES) {
-		elan_write_cmd(SRST);
-		elan_write_cmd(FUSE_LOAD);
-		register_initialization();
-		elan_sensing_mode();
-
-		ret = calibration();
-		if (ret == 0)
-			break;
-
-		retry_time++;
-	}
-
-	return ret;
-}
-
-int elan_fp_maintenance(uint16_t *error_state)
-{
-	int rv;
-	fp_sensor_info_t sensor_info;
-	timestamp_t start = get_time();
-
-	if (error_state == NULL)
-		return EC_ERROR_INVAL;
-
-	/* Initial status */
-	*error_state &= 0xFC00;
-	sensor_info.num_defective_pixels = 0;
-	sensor_info.sensor_error_code = 0;
-	rv = fp_sensor_maintenance(&sensor_info);
-	LOGE_SA("Maintenance took %d ms", time_since32(start) / MSEC);
-
-	if (rv != 0) {
-		/*
-		 * Failure can occur if any of the fingerprint detection zones
-		 * are covered (i.e., finger is on sensor).
-		 */
-		LOGE_SA("Failed to run maintenance: %d", rv);
-		return EC_ERROR_HW_INTERNAL;
-	}
-	if (sensor_info.num_defective_pixels >= FP_ERROR_DEAD_PIXELS_UNKNOWN)
-		*error_state = FP_ERROR_DEAD_PIXELS_UNKNOWN;
-	else
-		*error_state |=
-			FP_ERROR_DEAD_PIXELS(sensor_info.num_defective_pixels);
-	LOGE_SA("num_defective_pixels: %d", sensor_info.num_defective_pixels);
-	LOGE_SA("sensor_error_code: %d", sensor_info.sensor_error_code);
-
-	return EC_SUCCESS;
-}
-
-void __unused elan_sensor_set_rst(bool state)
-{
-	gpio_set_level(GPIO_FP_RST_ODL, state ? 0 : 1);
-}
diff --git a/driver/fingerprint/elan/elan_sensor_pal.h b/driver/fingerprint/elan/elan_sensor_pal.h
deleted file mode 100644
index 067b693245..0000000000
--- a/driver/fingerprint/elan/elan_sensor_pal.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* ELAN Platform Abstraction Layer callbacks */
-
-#ifndef ELAN_SENSOR_PAL_H_
-#define ELAN_SENSOR_PAL_H_
-
-/* ELAN error codes */
-enum elan_error_code {
-	ELAN_ERROR_NONE = 0,
-	ELAN_ERROR_SPI = 1,
-	ELAN_ERROR_SCAN = 2,
-	ELAN_ERROR_CAL = 3,
-	ELAN_ERROR_DEFECT_NUM = 4,
-	ELAN_ERROR_DEFECT_X = 5,
-	ELAN_ERROR_DEFECT_Y = 6
-};
-
-/* ELAN error info */
-typedef struct {
-	uint32_t num_defective_pixels;
-	uint16_t sensor_error_code;
-} fp_sensor_info_t;
-
-/**
- * @brief Write fp command to the sensor
- *
- * @param[in] fp_cmd     One byte fp command to write
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_write_cmd(uint8_t fp_cmd);
-
-/**
- * @brief Read fp register data from the sensor
- *
- * @param[in]   fp_cmd   One byte fp command to read
- * @param[out]  regdata  One byte data where register's data will be stored
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_read_cmd(uint8_t fp_cmd, uint8_t *regdata);
-
-/**
- * @brief Transfers and receives SPI data.
- *
- * @param[in]   tx              The buffer to transfer
- * @param[in]   tx_len          The length to transfer
- * @param[out]  rx              The buffer where read data will be stored
- * @param[in]   rx_len          The length to receive
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_spi_transaction(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len);
-
-/**
- * @brief Write fp register data to sensor
- *
- * @param[in]    regaddr  One byte register address to write
- * @param[in]    regdata  Data to write to register
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_write_register(uint8_t regaddr, uint8_t regdata);
-
-/**
- * @brief Select sensor RAM page of register
- *
- * @param[in]   page    The number of RAM page control registers
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_write_page(uint8_t page);
-
-/**
- * @brief Write register table to fp sensor
- *
- * Using a table to write data to sensor register.
- * This table contains multiple pairs of address and data to
- * be written.
- *
- * @param[in]    reg_table       The register address to write
- * @param[in]    length          The data to write to register
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_write_reg_vector(const uint8_t *reg_table, int length);
-
-/**
- * Get 14bits raw image data from ELAN fingerprint sensor
- *
- * @param[out] short_raw    The memory buffer to receive fingerprint image
- *                          raw data, buffer length is:
- *                          (IMAGE_WIDTH*IMAGE_HEIGHT)*sizeof(uint16_t)
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int raw_capture(uint16_t *short_raw);
-
-/**
- * Execute calibrate ELAN fingerprint sensor flow.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int elan_execute_calibration(void);
-
-/**
- * Execute reset ELAN fingerprint sensor flow.
- */
-void elan_execute_reset(void);
-
-/**
- * Runs a test for defective pixels.
- *
- * @param[out] fp_sensor_info  Structure containing output data.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fp_sensor_maintenance(fp_sensor_info_t *fp_sensor_info);
-
-/**
- * @brief Set sensor reset state.
- *
- * Set sensor reset state.
- *
- * @param[in] state Reset state.
- *                  true  => reset sensor, i.e. low GPIO state
- *                  false => normal operation, i.e. high GPIO state
- */
-void __unused elan_sensor_set_rst(bool state);
-#endif
diff --git a/driver/fingerprint/elan/elan_setting.h b/driver/fingerprint/elan/elan_setting.h
deleted file mode 100644
index feaf5e1550..0000000000
--- a/driver/fingerprint/elan/elan_setting.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ELAN_SETTING_H
-#define ELAN_SETTING_H
-
-#include <stdint.h>
-
-/* The hardware ID information and FW version */
-#define VID 0x04F3
-#define PID 0x0903
-#define MID 0x01
-#define VERSION 0x100B
-
-/* SPI tx and rx buffer size */
-#define CONFIG_SPI_TX_BUF_SIZE 1024
-#define CONFIG_SPI_RX_BUF_SIZE 5120
-
-/**
- * Elan sensor operation is controlled by sending commands and receiving
- * through the SPI interface. There are several SPI command codes for
- * controlling FP sensor:
- *
- * - START_SCAN            Start scan
- * - START_READ_IMAGE      Start read the image
- * - SRST                  Software reset
- * - FUSE_LOAD             Load OTP trims data to control registers
- * - READ_REG_HEAD         Register single read
- * - WRITE_REG_HEAD        Register burst write
- * - READ_SERIER_REG_HEAD  Register burst read
- * - PAGE_SEL              Register page selection
- * - SENSOR_STATUS         Read sensor status
- */
-#define START_SCAN 0x01
-#define START_READ_IMAGE 0x10
-#define SRST 0x31
-#define FUSE_LOAD 0x04
-#define READ_REG_HEAD 0x40
-#define WRITE_REG_HEAD 0x80
-#define READ_SERIER_REG_HEAD 0xC0
-#define PAGE_SEL 0x07
-#define SENSOR_STATUS 0x03
-
-/* Sensor type name */
-#define EFSA515 1
-#define EFSA80SC 2
-#if defined(CONFIG_FP_SENSOR_ELAN80)
-#define IC_SELECTION EFSA80SC
-#elif defined(CONFIG_FP_SENSOR_ELAN515)
-#define IC_SELECTION EFSA515
-#endif
-
-/* Sensor pixel resolution */
-#if (IC_SELECTION == EFSA80SC)
-#define IMAGE_WIDTH 80
-#define IMAGE_HEIGHT 80
-#elif (IC_SELECTION == EFSA515)
-#define IMAGE_WIDTH 150
-#define IMAGE_HEIGHT 52
-#endif
-
-/**
- * Sensor real image size:
- * ((IMAGE_HEIGHT * ONE_PIXEL_BYTE) + FP_DUMMY_BYTE) * IMAGE_WIDTH
- */
-#define FP_DUMMY_BYTE 2
-#define ONE_PIXEL_BYTE 2
-#define IMAGE_TOTAL_PIXEL (IMAGE_WIDTH * IMAGE_HEIGHT)
-#define RAW_PIXEL_SIZE (IMAGE_HEIGHT * ONE_PIXEL_BYTE)
-#define RAW_DATA_SIZE (RAW_PIXEL_SIZE + FP_DUMMY_BYTE)
-#define IMG_BUF_SIZE (RAW_DATA_SIZE * IMAGE_WIDTH)
-
-/* Polling scan status counter */
-#define POLLING_SCAN_TIMER 10000
-
-/* Re-calibration timer */
-#define REK_TIMES 3
-
-/* Console output macros */
-#define LOGE_SA(format, args...) cprints(CC_FP, format, ##args)
-
-/**
- * Set ELAN fingerprint sensor register initialization
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int register_initialization(void);
-
-/**
- * To calibrate ELAN fingerprint sensor and keep the calibration results
- * for correcting fingerprint image data
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int calibration(void);
-
-#endif /* _ELAN_SETTING_H */
diff --git a/driver/fingerprint/fpc/bep/build.mk b/driver/fingerprint/fpc/bep/build.mk
deleted file mode 100644
index ac7f05fb60..0000000000
--- a/driver/fingerprint/fpc/bep/build.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# FPC BEP source files build
-
-# Note that this variable includes the trailing "/"
-_bep_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-# Make sure output directory is created (in build directory)
-dirs-y+="$(_bep_cur_dir)"
-
-# Only build for these objects for the RW image
-all-obj-rw+=$(_bep_cur_dir)fpc_misc.o \
-	$(_bep_cur_dir)fpc_private.o \
-	$(_bep_cur_dir)fpc_sensor_spi.o \
-	$(_bep_cur_dir)fpc_timebase.o
diff --git a/driver/fingerprint/fpc/bep/fpc1025_private.h b/driver/fingerprint/fpc/bep/fpc1025_private.h
deleted file mode 100644
index 2da127741f..0000000000
--- a/driver/fingerprint/fpc/bep/fpc1025_private.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC1025_PRIVATE_H
-#define __CROS_EC_FPC1025_PRIVATE_H
-
-/* The 16-bit hardware ID is 0x021y */
-#define FP_SENSOR_HWID 0x021
-
-/* Sensor type name */
-#define FP_SENSOR_NAME "FPC1025"
-
-/* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (160) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (160) /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
-
-/*
- * Sensor image size
- *
- * Value from fpc_bep_image_get_buffer_size(): (160*160)+660
- */
-#define FP_SENSOR_IMAGE_SIZE        (26260)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
-/* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
-
-/*
- * Constant value for the enrollment data size
- *
- * Size of private fp_bio_enrollment_t
- */
-#define FP_ALGORITHM_ENROLLMENT_SIZE (4)
-
-/*
- * Constant value corresponding to the maximum template size
- * for FPC1025 sensor. Client template memory allocation must
- * have this size. This includes extra memory for template update.
- *
- * Template size + alignment padding + size of template size variable
- */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (5088 + 0 + 4)
-
-/* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
-
-#endif /* __CROS_EC_FPC1025_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc1035_private.h b/driver/fingerprint/fpc/bep/fpc1035_private.h
deleted file mode 100644
index 695228898b..0000000000
--- a/driver/fingerprint/fpc/bep/fpc1035_private.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC1035_PRIVATE_H
-#define __CROS_EC_FPC1035_PRIVATE_H
-
-/* The 16-bit hardware ID is 0x011y */
-#define FP_SENSOR_HWID 0x011
-
-/* Sensor type name */
-#define FP_SENSOR_NAME "FPC1035"
-
-/* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (112) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (88)  /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
-
-/*
- * Sensor image size
- *
- * Value from fpc_bep_image_get_buffer_size(): (112*88)+660
- */
-#define FP_SENSOR_IMAGE_SIZE        (10516)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
-/* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
-
-/*
- * Constant value for the enrollment data size
- *
- * Size of private fp_bio_enrollment_t
- */
-#define FP_ALGORITHM_ENROLLMENT_SIZE (4)
-
-/*
- * Constant value corresponding to the maximum template size
- * for FPC1035 sensor. Client template memory allocation must
- * have this size. This includes extra memory for template update.
- *
- * Template size + alignment padding + size of template size variable
- */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (14373 + 3 + 4)
-
-/* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
-
-#endif /* __CROS_EC_FPC1035_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
deleted file mode 100644
index 1bf598a3ee..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC_BIO_ALGORITHM_H
-#define __CROS_EC_FPC_BIO_ALGORITHM_H
-
-#include <stdint.h>
-
-/*
- * An opaque pointer representing an image (scan).
- */
-typedef void *bio_image_t;
-/*
- * An opaque pointer representing/uniquely identifying an (serialized) enrolled
- * template.
- */
-typedef void *bio_template_t;
-/*
- * An opaque pointer representing/uniquely identifying enrollment attempt.
- */
-typedef void *bio_enrollment_t;
-/*
- * An opaque struct representing algorithm.
- */
-typedef struct fpc_bep_algorithm fpc_bep_algorithm_t;
-/*
- * Struct with biometric algorithm information.
- */
-typedef struct {
-	const fpc_bep_algorithm_t *algorithm;
-	uint32_t template_size;
-} fpc_bio_info_t;
-/*
- * Initializes biometric algorithm library. Should be the very first function
- * to be invoked by the biometric daemon.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_algorithm_init(void);
-/*
- * Instructs the biometric library to release all resources in preparation
- * for the process termination (or unloading the library). Regardless of
- * the returned error code the action is considered unrecoverable.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_algorithm_exit(void);
-/*
- * Compares given biometric image against a list of enrolled template(s).
- * In case the image match a template the match_index will indicate which
- * template in the list that matched.
- * The algorithm library can update templates with additional biometric data
- * from the image, if it chooses to do so. The updated template(s) will be
- * indicated by the out parameter 'updated_templates', a bit-field where
- * updated template(s) indicated by the corresponding bit being set
- * Returns:
- * - negative value on error
- * - BIO_TEMPLATE_NO_MATCH on non-match
- * - BIO_TEMPLATE_MATCH for match when template was not updated with new data
- * - BIO_TEMPLATE_MATCH_UPDATED for match when template was updated
- * - BIO_TEMPLATE_MATCH_UPDATE_FAILED match, but update failed (do not save)
- * - BIO_TEMPLATE_LOW_QUALITY when matching could not be performed due to low
- *   image quality
- * - BIO_TEMPLATE_LOW_COVERAGE when matching could not be performed due to
- *   finger covering too little area of the sensor
- */
-#define BIO_TEMPLATE_NO_MATCH            0
-#define BIO_TEMPLATE_MATCH               1
-#define BIO_TEMPLATE_MATCH_UPDATED       3
-#define BIO_TEMPLATE_MATCH_UPDATE_FAILED 5
-#define BIO_TEMPLATE_LOW_QUALITY         2
-#define BIO_TEMPLATE_LOW_COVERAGE        4
-
-int bio_template_image_match_list(bio_template_t templ, uint32_t num_templ,
-				  bio_image_t image, int32_t *match_index,
-				  uint32_t *updated_templ);
-/*
- * Initiates biometric data enrollment process. Algorithm library returns
- * 'enrollment handle' that is used for all subsequent enrollment operations.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_enrollment_begin(bio_enrollment_t *enrollment);
-/*
- * Adds fingerprint image to an enrollment.
- *
- * The library should expect to copy any relevant data from the “image�
- * as it is likely to be destroyed (via bio_image_destroy() call) shortly after
- * this call completes.
- *
- * Returns:
- * - negative value on error
- * - BIO_ENROLLMENT_OK when image was successfully enrolled
- * - BIO_ENROLLMENT_LOW_QUALITY when image could not be used due to low
- *   image quality
- * - BIO_ENROLLMENT_IMMOBILE when image added, but user should be advised
- *   to move finger
- * - BIO_ENROLLMENT_LOW_COVERAGE when image could not be used due to
- *   finger covering too little area of the sensor
- * - BIO_ENROLLMENT_INTERNAL_ERROR when an internal error occurred
- */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
-#define BIO_ENROLLMENT_INTERNAL_ERROR   5
-
-/* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
-int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
-/*
- * Returns percent of coverage accumulated during enrollment process.
- * Optional method. Regardless of value returned by this call user should call
- * bio_enrollment_is_complete() to check if algorithm library accumulated enough
- * data to create a template.
- *
- * Returns value in the range 0..100, or negative error (such as -EINVAL);
- */
-int bio_enrollment_get_percent_complete(bio_enrollment_t enrollment);
-/*
- * Indicates that given enrollment process is complete, and algorithm library
- * should generate an active template that can be used in subsequent calls
- * to bio_image_match() and bio_template_serialize() from enrollment data.
- * After the template is created the library should release all resources
- * associated with this enrollment.
- *
- * Argument 'templ' is optional and can be set to NULL if caller wishes to
- * abort enrollment process.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_enrollment_finish(bio_enrollment_t enrollment, bio_template_t *templ);
-
-#endif /* __CROS_EC_FPC_BIO_ALGORITHM_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_misc.c b/driver/fingerprint/fpc/bep/fpc_misc.c
deleted file mode 100644
index c4c779b702..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_misc.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* FPC Platform Abstraction Layer */
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "shared_mem.h"
-#include "uart.h"
-
-void __unused *fpc_malloc(uint32_t size)
-{
-	char *data;
-	int rc;
-
-	rc = shared_mem_acquire(size, (char **)&data);
-
-	if (rc == 0)
-		return data;
-	else
-		return NULL;
-}
-
-void __unused fpc_free(void *data)
-{
-	shared_mem_release(data);
-}
-
-/* Not in release */
-void __unused fpc_assert_fail(const char *file, uint32_t line, const char *func,
-			      const char *expr)
-{
-}
-
-void __unused fpc_log_var(const char *source, uint8_t level, const char *format,
-			  ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	uart_vprintf(format, args);
-	va_end(args);
-}
-
-uint32_t abs(int32_t a)
-{
-	return (a < 0) ? (uint32_t)(-a) : (uint32_t)a;
-}
diff --git a/driver/fingerprint/fpc/bep/fpc_private.c b/driver/fingerprint/fpc/bep/fpc_private.c
deleted file mode 100644
index a94ba2ab06..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_private.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "fpc_bio_algorithm.h"
-#include "fpsensor.h"
-#include "gpio.h"
-#include "spi.h"
-#include "system.h"
-#include "util.h"
-
-#include "driver/fingerprint/fpc/fpc_sensor.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
-static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4) = {0};
-
-/* Recorded error flags */
-static uint16_t errors;
-
-/* FPC specific initialization and de-initialization functions */
-int fp_sensor_open(void);
-int fp_sensor_close(void);
-
-/* Get FPC library version code.*/
-const char *fp_sensor_get_version(void);
-
-/* Get FPC library build info.*/
-const char *fp_sensor_get_build_info(void);
-
-/* Sensor description */
-static struct ec_response_fp_info ec_fp_sensor_info = {
-	/* Sensor identification */
-	.vendor_id = FOURCC('F', 'P', 'C', ' '),
-	.product_id = 9,
-	.model_id = 1,
-	.version = 1,
-	/* Image frame characteristics */
-	.frame_size = FP_SENSOR_IMAGE_SIZE,
-	.pixel_format = V4L2_PIX_FMT_GREY,
-	.width = FP_SENSOR_RES_X,
-	.height = FP_SENSOR_RES_Y,
-	.bpp = FP_SENSOR_RES_BPP,
-};
-
-typedef struct fpc_bep_sensor fpc_bep_sensor_t;
-
-typedef struct {
-	const fpc_bep_sensor_t *sensor;
-	uint32_t image_buffer_size;
-} fpc_sensor_info_t;
-
-#if defined(CONFIG_FP_SENSOR_FPC1025)
-
-extern const fpc_bep_sensor_t fpc_bep_sensor_1025;
-extern const fpc_bep_algorithm_t fpc_bep_algorithm_pfe_1025;
-
-const fpc_sensor_info_t fpc_sensor_info = {
-	.sensor = &fpc_bep_sensor_1025,
-	.image_buffer_size = FP_SENSOR_IMAGE_SIZE,
-};
-
-const fpc_bio_info_t fpc_bio_info = {
-	.algorithm = &fpc_bep_algorithm_pfe_1025,
-	.template_size = FP_ALGORITHM_TEMPLATE_SIZE,
-};
-
-#elif defined(CONFIG_FP_SENSOR_FPC1035)
-
-extern const fpc_bep_sensor_t fpc_bep_sensor_1035;
-extern const fpc_bep_algorithm_t fpc_bep_algorithm_pfe_1035;
-
-const fpc_sensor_info_t fpc_sensor_info = {
-	.sensor = &fpc_bep_sensor_1035,
-	.image_buffer_size = FP_SENSOR_IMAGE_SIZE,
-};
-
-const fpc_bio_info_t fpc_bio_info = {
-	.algorithm = &fpc_bep_algorithm_pfe_1035,
-	.template_size = FP_ALGORITHM_TEMPLATE_SIZE,
-};
-#else
-#error "Sensor type not defined!"
-#endif
-
-/* Sensor IC commands */
-enum fpc_cmd {
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_HW_ID             = 0xFC,
-};
-
-/* Maximum size of a sensor command SPI transfer */
-#define MAX_CMD_SPI_TRANSFER_SIZE 3
-
-/* Memory for the SPI transfer buffer */
-static uint8_t spi_buf[MAX_CMD_SPI_TRANSFER_SIZE];
-
-static int fpc_send_cmd(const uint8_t cmd)
-{
-	spi_buf[0] = cmd;
-
-	return spi_transaction(SPI_FP_DEVICE, spi_buf, 1, spi_buf,
-			       SPI_READBACK_ALL);
-}
-
-void fp_sensor_low_power(void)
-{
-	fpc_send_cmd(FPC_CMD_DEEPSLEEP);
-}
-
-int fpc_check_hwid(void)
-{
-	uint16_t id;
-	int rc;
-
-	spi_buf[0] = FPC_CMD_HW_ID;
-
-	rc = spi_transaction(SPI_FP_DEVICE, spi_buf, 3, spi_buf,
-			     SPI_READBACK_ALL);
-	if (rc) {
-		CPRINTS("FPC HW ID read failed %d", rc);
-		return FP_ERROR_SPI_COMM;
-	}
-
-	id = (spi_buf[1] << 8) | spi_buf[2];
-	if ((id >> 4) != FP_SENSOR_HWID) {
-		CPRINTS("FPC unknown silicon 0x%04x", id);
-		return FP_ERROR_BAD_HWID;
-	}
-	CPRINTS(FP_SENSOR_NAME " id 0x%04x", id);
-
-	return EC_SUCCESS;
-}
-
-/* Reset and initialize the sensor IC */
-int fp_sensor_init(void)
-{
-	int rc;
-
-	/* Print the binary libfpbep.a library version */
-	CPRINTS("FPC libfpbep.a %s", fp_sensor_get_version());
-
-	/* Print the BEP version and build time of the library */
-	CPRINTS("Build information - %s", fp_sensor_get_build_info());
-
-	errors = FP_ERROR_DEAD_PIXELS_UNKNOWN;
-
-	rc = fp_sensor_open();
-	if (rc) {
-		errors |= FP_ERROR_INIT_FAIL;
-		CPRINTS("Error: fp_sensor_open() failed, result=%d", rc);
-	}
-
-	errors |= fpc_check_hwid();
-
-	rc = bio_algorithm_init();
-	if (rc < 0) {
-		errors |= FP_ERROR_INIT_FAIL;
-		CPRINTS("Error: bio_algorithm_init() failed, result=%d", rc);
-	}
-
-	/* Go back to low power */
-	fp_sensor_low_power();
-
-	return EC_SUCCESS;
-}
-
-/* Deinitialize the sensor IC */
-int fp_sensor_deinit(void)
-{
-	int rc;
-
-	rc = bio_algorithm_exit();
-	if (rc < 0)
-		CPRINTS("Error: bio_algorithm_exit() failed, result=%d", rc);
-
-	rc = fp_sensor_close();
-	if (rc < 0)
-		CPRINTS("Error: fp_sensor_close() failed, result=%d", rc);
-
-	return rc;
-}
-
-int fp_sensor_get_info(struct ec_response_fp_info *resp)
-{
-	int rc;
-
-	spi_buf[0] = FPC_CMD_HW_ID;
-
-	memcpy(resp, &ec_fp_sensor_info, sizeof(struct ec_response_fp_info));
-
-	rc = spi_transaction(SPI_FP_DEVICE, spi_buf, 3, spi_buf,
-			     SPI_READBACK_ALL);
-	if (rc)
-		return EC_RES_ERROR;
-
-	resp->model_id = (spi_buf[1] << 8) | spi_buf[2];
-	resp->errors = errors;
-
-	return EC_SUCCESS;
-}
-
-int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
-		    int32_t *match_index, uint32_t *update_bitmap)
-{
-	int rc;
-
-	rc = bio_template_image_match_list(templ, templ_count, image,
-					   match_index, update_bitmap);
-	if (rc < 0)
-		CPRINTS("Error: bio_template_image_match_list() failed, result=%d",
-			rc);
-
-	return rc;
-}
-
-int fp_enrollment_begin(void)
-{
-	int rc;
-	bio_enrollment_t bio_enroll = enroll_ctx;
-
-	rc = bio_enrollment_begin(&bio_enroll);
-	if (rc < 0)
-		CPRINTS("Error: bio_enrollment_begin() failed, result=%d", rc);
-
-	return rc;
-}
-
-int fp_enrollment_finish(void *templ)
-{
-	int rc;
-	bio_enrollment_t bio_enroll = enroll_ctx;
-	bio_template_t bio_templ = templ;
-
-	rc = bio_enrollment_finish(bio_enroll, templ ? &bio_templ : NULL);
-	if (rc < 0)
-		CPRINTS("Error: bio_enrollment_finish() failed, result=%d", rc);
-
-	return rc;
-}
-
-int fp_finger_enroll(uint8_t *image, int *completion)
-{
-	int rc;
-	bio_enrollment_t bio_enroll = enroll_ctx;
-
-	rc = bio_enrollment_add_image(bio_enroll, image);
-	if (rc < 0) {
-		CPRINTS("Error: bio_enrollment_add_image() failed, result=%d",
-			rc);
-		return rc;
-	}
-
-	*completion = bio_enrollment_get_percent_complete(bio_enroll);
-
-	return rc;
-}
-
-int fp_maintenance(void)
-{
-	return fpc_fp_maintenance(&errors);
-}
diff --git a/driver/fingerprint/fpc/bep/fpc_private.h b/driver/fingerprint/fpc/bep/fpc_private.h
deleted file mode 100644
index 9a9acfd42a..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_private.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Private sensor interface */
-
-#ifndef __CROS_EC_FPC_PRIVATE_H
-#define __CROS_EC_FPC_PRIVATE_H
-
-#include <stdint.h>
-
-typedef struct {
-	uint32_t num_defective_pixels;
-} fp_sensor_info_t;
-
-/**
- * fp_sensor_maintenance runs a test for defective pixels and should
- * be triggered periodically by the client. Internally, a defective
- * pixel list is maintained and the algorithm will compensate for
- * any defect pixels when matching towards a template.
- *
- * The defective pixel update will abort and return an error if any of
- * the finger detect zones are covered. A client can call
- * fp_sensor_finger_status to determine the current status.
- *
- * @param[in]  image_data      pointer to FP_SENSOR_IMAGE_SIZE bytes of memory
- * @param[out] fp_sensor_info  Structure containing output data.
- *
- * @return
- * - 0 on success
- * - negative value on error
- */
-int fp_sensor_maintenance(uint8_t *image_data,
-			  fp_sensor_info_t *fp_sensor_info);
-
-/* Read the HWID from the sensor. */
-int fpc_check_hwid(void);
-
-#endif  /* __CROS_EC_FPC_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
deleted file mode 100644
index 225752bdb6..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* FPC Platform Abstraction Layer */
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
-#include "console.h"
-#include "fpsensor.h"
-#include "fpc_sensor_spi.h"
-#include "gpio.h"
-#include "spi.h"
-#include "util.h"
-
-#include "driver/fingerprint/fpc/fpc_sensor.h"
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
-
-#define SPI_BUF_SIZE              (1024)
-
-#define FPC_RESULT_OK                (0)
-#define FPC_RESULT_IO_ERROR         (-8)
-
-static uint8_t spi_buf[SPI_BUF_SIZE] FP_FRAME_SECTION __aligned(4);
-
-int __unused fpc_sensor_spi_write_read(uint8_t *write, uint8_t *read,
-				       size_t size, bool leave_cs_asserted)
-{
-	int rc = 0;
-
-	if (size == FP_SENSOR_REAL_IMAGE_SIZE) {
-		rc |= spi_transaction(SPI_FP_DEVICE, write, size, read,
-				      SPI_READBACK_ALL);
-		spi_transaction_flush(SPI_FP_DEVICE);
-	} else if (size <= SPI_BUF_SIZE) {
-		memcpy(spi_buf, write, size);
-		rc |= spi_transaction_async(SPI_FP_DEVICE, spi_buf, size,
-					    spi_buf, SPI_READBACK_ALL);
-
-		/* De-asserting the sensor chip-select will clear the sensor
-		 * internal command state. To run multiple sensor transactions
-		 * in the same command state (typically image capture), leave
-		 * chip-select asserted. Make sure chip-select is de-asserted
-		 * when all transactions are finished.
-		 */
-		if (!leave_cs_asserted)
-			spi_transaction_flush(SPI_FP_DEVICE);
-		else
-			spi_transaction_wait(SPI_FP_DEVICE);
-
-		memcpy(read, spi_buf, size);
-	} else {
-		rc = -1;
-	}
-
-	if (rc == 0) {
-		return FPC_RESULT_OK;
-	} else {
-		CPRINTS("Error: spi_transaction()/spi_transaction_async() failed, result=%d",
-			rc);
-		return FPC_RESULT_IO_ERROR;
-	}
-}
-
-bool __unused fpc_sensor_spi_check_irq(void)
-{
-	return (gpio_get_level(GPIO_FPS_INT) == 1);
-}
-
-bool __unused fpc_sensor_spi_read_irq(void)
-{
-	return (gpio_get_level(GPIO_FPS_INT) == 1);
-}
-
-void __unused fpc_sensor_spi_reset(bool state)
-{
-	gpio_set_level(GPIO_FP_RST_ODL, state ? 0 : 1);
-}
-
-void __unused fpc_sensor_spi_init(uint32_t speed_hz)
-{
-}
-
-int __unused fpc_sensor_wfi(uint16_t timeout_ms, fpc_wfi_check_t enter_wfi,
-			    bool enter_wfi_mode)
-{
-	return FPC_RESULT_OK;
-}
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h b/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
deleted file mode 100644
index 25d29d77a3..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC_SENSOR_SPI_H
-#define __CROS_EC_FPC_SENSOR_SPI_H
-
-/**
- * @file    fpc_sensor_spi.h
- * @brief   Driver for SPI controller.
- *
- * Driver for SPI controller. Intended for communication with
- * fingerprint sensor.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool (*fpc_wfi_check_t)(void);
-
-/**
- * @brief Writes and reads SPI data.
- *
- * Writes data to SPI interface and reads data from SPI interface, with chip
- * select control. The caller is blocked until the operation is complete. By use
- * of the chip select control parameter a single SPI transaction can be split in
- * several calls.
- *
- * @param[in]     write Data to write. Must not be NULL if size > 0.
- * @param[in,out] read  Receive data buffer. The caller is responsible for
- *                      allocating buffer. NULL => response is thrown away.
- * @param[in]     size  Number of bytes to write (same as bytes received).
- *                      0 => Only chip select control.
- * @param[in]     leave_cs_asserted True  => chip select is left in asserted
- *                                           state.
- *                                  False => chip select is de-asserted before
- *                                           return.
- * @return ::fpc_bep_result_t
- */
-int __unused fpc_sensor_spi_write_read(uint8_t *write, uint8_t *read,
-				       size_t size, bool leave_cs_asserted);
-
-/**
- * @brief Read sensor IRQ status.
- *
- * Returns status of the sensor IRQ.
- *
- * @return true if the sensor IRQ is currently active, otherwise false.
- */
-bool __unused fpc_sensor_spi_check_irq(void);
-
-/**
- * @brief Read sensor IRQ status and then set status to false.
- *
- * Returns status of the sensor IRQ and sets the status to false.
- *
- * @return true if the sensor IRQ has been active, otherwise false.
- */
-bool __unused fpc_sensor_spi_read_irq(void);
-
-/**
- * @brief Set sensor reset state.
- *
- * Set sensor reset state.
- *
- * @param[in] state Reset state.
- *                  true  => reset sensor, i.e. low GPIO state
- *                  false => normal operation, i.e. high GPIO state
- */
-void __unused fpc_sensor_spi_reset(bool state);
-
-/**
- * @brief Initializes SPI controller.
- *
- * @param[in] speed_hz  Maximum SPI clock speed according to sensor HW spec
- *                      (unit Hz).
- *
- */
-void __unused fpc_sensor_spi_init(uint32_t speed_hz);
-
-/**
- * @brief Set system in WFI mode while waiting sensor IRQ.
- *
- * @note This mode only requires the system to be able to wake up from Sensor
- * IRQ pin, all other peripheral can be turned off.
- *
- * @note The system time must be adjusted upon WFI return.
- *
- * @param[in] timeout_ms Time in ms before waking up, 0 if no timeout.
- * @param[in] enter_wfi Function pointer to check WFI entry.
- * @param[in] enter_wfi_mode Bool that is used when comparing the value returned
- *                           by enter_wfi.
- * @return FPC_RESULT_OK, FPC_RESULT_TIMEOUT
- */
-int __unused fpc_sensor_wfi(uint16_t timeout_ms, fpc_wfi_check_t enter_wfi,
-			    bool enter_wfi_mode);
-
-#endif /* __CROS_EC_FPC_SENSOR_SPI_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.c b/driver/fingerprint/fpc/bep/fpc_timebase.c
deleted file mode 100644
index 113e150ed9..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_timebase.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* FPC Platform Abstraction Layer */
-
-#include <stdint.h>
-
-#include "fpc_timebase.h"
-#include "timer.h"
-
-uint32_t __unused fpc_timebase_get_tick(void)
-{
-	clock_t time;
-
-	time = clock();
-
-	return (uint32_t)time;
-}
-
-void __unused fpc_timebase_busy_wait(uint32_t ms)
-{
-	udelay(ms * 1000);
-}
-
-void __unused fpc_timebase_init(void)
-{
-}
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.h b/driver/fingerprint/fpc/bep/fpc_timebase.h
deleted file mode 100644
index 388d13293e..0000000000
--- a/driver/fingerprint/fpc/bep/fpc_timebase.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC_TIMEBASE_H
-#define __CROS_EC_FPC_TIMEBASE_H
-
-/**
- * @file    fpc_timebase.h
- * @brief   Timebase based on a system tick.
- *
- * Supplies tick counter and wait operation(s).
- */
-
-#include <stdint.h>
-
-#include "common.h"
-
-/**
- * @brief Reads the system tick counter.
- *
- * @details To handle tick counter wrap around when checking for timeout, make
- *          sure to do the calculation in the following manner:
- *          "if ((current_tick - old_tick) > timeout) {"
- *          Example: current time (uint32_t) = 10 ticks
- *                   old time (uint32_t) = 30 ticks before overflow of uint32_t
- *          current_time - old_time = 10 - (2**32 - 30) -> wraps around to 40
- *
- * @return Tick count since fpc_timebase_init() call. [ms]
- */
-uint32_t __unused fpc_timebase_get_tick(void);
-
-/**
- * @brief Busy wait.
- *
- * @param[in] ms  Time to wait [ms].
- * 0 => return immediately
- * 1 => wait at least 1ms etc.
- */
-void __unused fpc_timebase_busy_wait(uint32_t ms);
-
-/**
- * @brief Initializes timebase. Starts system tick counter.
- */
-void __unused fpc_timebase_init(void);
-
-#endif /* __CROS_EC_FPC_TIMEBASE_H */
diff --git a/driver/fingerprint/fpc/build.mk b/driver/fingerprint/fpc/build.mk
deleted file mode 100644
index 5c18a1f096..0000000000
--- a/driver/fingerprint/fpc/build.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Build for FPC fingerprint drivers
-
-# Note that this variable includes the trailing "/"
-_fpc_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-# Only build if FPC sensor is configured.
-ifneq (,$(filter rw,$(CONFIG_FP_SENSOR_FPC1145) $(CONFIG_FP_SENSOR_FPC1025) \
-	$(CONFIG_FP_SENSOR_FPC1035)))
-
-ifeq ($(CONFIG_FP_SENSOR_FPC1145),rw)
-include $(_fpc_cur_dir)libfp/build.mk
-else ifeq ($(CONFIG_FP_SENSOR_FPC1025),rw)
-include $(_fpc_cur_dir)bep/build.mk
-else ifeq ($(CONFIG_FP_SENSOR_FPC1035),rw)
-include $(_fpc_cur_dir)bep/build.mk
-endif
-
-ifneq ($(CONFIG_FINGERPRINT_MCU),)
-# Make sure output directory is created (in build directory)
-dirs-rw+="$(_fpc_cur_dir)"
-
-# Only build these objects for the RW image
-all-obj-rw+=$(_fpc_cur_dir)fpc_sensor.o
-endif
-
-endif
diff --git a/driver/fingerprint/fpc/fpc_sensor.c b/driver/fingerprint/fpc/fpc_sensor.c
deleted file mode 100644
index a15502521f..0000000000
--- a/driver/fingerprint/fpc/fpc_sensor.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include <include/fpsensor.h>
-#include <include/fpsensor_state.h>
-#include <common/fpsensor/fpsensor_private.h>
-#if defined(CONFIG_FP_SENSOR_FPC1025) || defined(CONFIG_FP_SENSOR_FPC1035)
-#include "bep/fpc_private.h"
-#elif defined(CONFIG_FP_SENSOR_FPC1145)
-#include "libfp/fpc_private.h"
-#else
-#error "Sensor type not defined!"
-#endif
-
-/*
- * TODO(b/164174822): We cannot include fpc_sensor.h here, since
- * the parent fpsensor.h header conditionally excludes fpc_sensor.h
- * and replaces its content with default macros.
- * Fix this header discrepancy.
- *
- * #include "fpc_sensor.h"
- */
-
-int fpc_fp_maintenance(uint16_t *error_state)
-{
-	int rv;
-	fp_sensor_info_t sensor_info;
-	timestamp_t start = get_time();
-
-	if (error_state == NULL)
-		return EC_ERROR_INVAL;
-
-	rv = fp_sensor_maintenance(fp_buffer, &sensor_info);
-	CPRINTS("Maintenance took %d ms", time_since32(start) / MSEC);
-
-	if (rv != 0) {
-		/*
-		 * Failure can occur if any of the fingerprint detection zones
-		 * are covered (i.e., finger is on sensor).
-		 */
-		CPRINTS("Failed to run maintenance: %d", rv);
-		return EC_ERROR_HW_INTERNAL;
-	}
-
-	*error_state |= FP_ERROR_DEAD_PIXELS(sensor_info.num_defective_pixels);
-	CPRINTS("num_defective_pixels: %d", sensor_info.num_defective_pixels);
-
-	return EC_SUCCESS;
-}
diff --git a/driver/fingerprint/fpc/fpc_sensor.h b/driver/fingerprint/fpc/fpc_sensor.h
deleted file mode 100644
index 2ab9248eeb..0000000000
--- a/driver/fingerprint/fpc/fpc_sensor.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_FINGERPRINT_FPC_FPC_SENSOR_H_
-#define __CROS_EC_DRIVER_FINGERPRINT_FPC_FPC_SENSOR_H_
-
-#include "common.h"
-
-#if defined(CONFIG_FP_SENSOR_FPC1025)
-#include "bep/fpc1025_private.h"
-#elif defined(CONFIG_FP_SENSOR_FPC1035)
-#include "bep/fpc1035_private.h"
-#elif defined(CONFIG_FP_SENSOR_FPC1145)
-#include "libfp/fpc1145_private.h"
-#else
-#error "Sensor type not defined!"
-#endif
-
-int fpc_fp_maintenance(uint16_t *error_state);
-
-#endif /* __CROS_EC_DRIVER_FINGERPRINT_FPC_FPC_SENSOR_H_ */
diff --git a/driver/fingerprint/fpc/libfp/build.mk b/driver/fingerprint/fpc/libfp/build.mk
deleted file mode 100644
index 3fabab38e9..0000000000
--- a/driver/fingerprint/fpc/libfp/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# FPC libfp source files build
-
-# Note that this variable includes the trailing "/"
-libfp_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
-
-# Make sure output directory is created (in build directory)
-dirs-y+="$(libfp_cur_dir)"
-
-# Only build for these objects for the RW image
-all-obj-rw+=$(libfp_cur_dir)fpc_sensor_pal.o \
-			$(libfp_cur_dir)fpc_private.o
diff --git a/driver/fingerprint/fpc/libfp/fpc1145_private.h b/driver/fingerprint/fpc/libfp/fpc1145_private.h
deleted file mode 100644
index 399c75118b..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc1145_private.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPC1145_PRIVATE_H
-#define __CROS_EC_FPC1145_PRIVATE_H
-
-#include <stdint.h>
-
-/**
- * The hardware ID is 16-bits. All 114x FPC sensors (including FPC1145) are
- * detected with the pattern 0x1400 and mask 0xFFF0. All supported variants of
- * the 1145 (0x140B, 0x140C, and 0x1401) should be detected as part of the FPC
- * 1140 family with identical functionality.
- * See http://b/150407388 for additional details.
- */
-#define FP_SENSOR_HWID 0x140
-
-/* Sensor type name */
-#define FP_SENSOR_NAME "FPC1145"
-
-/* Sensor pixel resolution */
-#define FP_SENSOR_RES_Y        192
-#define FP_SENSOR_RES_X        56
-#define FP_SENSOR_RES_BPP      8
-
-/* Acquired finger frame definitions */
-#define FP_SENSOR_IMAGE_SIZE_MODE_VENDOR (35460)
-#define FP_SENSOR_IMAGE_SIZE_MODE_SIMPLE (13356)
-/*
- * Size of the captured image in MQT mode. If you this is modified the
- * corresponding value in the MQT tool fputils.py must be changed too.
- * See b/111443750 for context.
- */
-#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL   (24408)
-
-#define FP_SENSOR_IMAGE_SIZE   FP_SENSOR_IMAGE_SIZE_MODE_VENDOR
-#define FP_SENSOR_IMAGE_OFFSET 2340
-
-/* Opaque FPC context */
-#define FP_SENSOR_CONTEXT_SIZE 4944
-
-/* Algorithm buffer sizes */
-#define FP_ALGORITHM_ENROLLMENT_SIZE    28
-#define FP_ALGORITHM_TEMPLATE_SIZE   47552
-
-/* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT 5
-
-#endif /* __CROS_EC_FPC1145_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
deleted file mode 100644
index 9c00b14640..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef BIOD_BIO_ALGORITHM_H_
-#define BIOD_BIO_ALGORITHM_H_
-
-#include <stdint.h>
-
-enum bio_algorithm_type {
-	BIO_ALGORITHM_FINGERPRINT,
-	BIO_ALGORITHM_IRIS,
-};
-/*
- * An opaque pointer representing/uniquely identifying a sensor.
- */
-typedef void *bio_sensor_t;
-/*
- * An opaque pointer representing an image (scan).
- */
-typedef void *bio_image_t;
-/*
- * An opaque pointer representing/uniquely identifying an (serialized) enrolled
- * template.
- */
-typedef void *bio_template_t;
-/*
- * An opaque pointer representing/uniquely identifying enrollment attempt.
- */
-typedef void *bio_enrollment_t;
-/*
- * Initializes biometric algorithm library. Should be the very first function
- * to be invoked by the biometric daemon.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_algorithm_init(void);
-/*
- * Instructs the biometric library to release all resources in preparation
- * for the process termination (or unloading the library). Regardless of
- * the returned error code the action is considered unrecoverable.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_algorithm_exit(void);
-/*
- * Used to retrieve type of the algorithm library. Might be used by
- * configuration processor module to match sensors and algorithm libraries.
- */
-enum bio_algorithm_type bio_algorithm_get_type(void);
-/*
- * Used to retrieve name of the algorithm library, to be used in diagnostics.
- * Also might be used by configuration processor module to match sensors and
- * algorithm libraries.
- */
-const char *bio_algorithm_get_name(void);
-/*
- * Used to retrieve version of the algorithm library, to be used in diagnostics.
- */
-const char *bio_algorithm_get_version(void);
-/*
- * Used to retrieve additional information from the algorithm library, to be
- * used in diagnostics.
- */
-const char *bio_algorithm_get_banner(void);
-/*
- * Initializes a new sensor structure and returns its handle that will be used
- * in other calls to identify the sensor involved in the operation.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_sensor_create(bio_sensor_t *sensor);
-/*
- * Releases all resources held by the library in conjunction with given sensor.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_sensor_destroy(bio_sensor_t sensor);
-/*
- * Communicates particulars of a given sensor so that algorithm library can
- * adjust its behavior as needed.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_sensor_set_model(bio_sensor_t sensor, uint32_t vendor_id,
-			 uint32_t product_id, uint32_t model_id,
-			 uint32_t version);
-/*
- * Communicates format of data used by given sensor to the algorithm library.
- * This is a fourcc value defined by V4L2 API.
- * Could be a new define for biometric sensors or V4L2_PIX_FMT_GREY.
- * Algorithm library will return error if it can not work with given format.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_sensor_set_format(bio_sensor_t sensor, uint32_t pixel_format);
-/*
- * Communicates dimensions of given sensor to the algorithm library.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_sensor_set_size(bio_sensor_t sensor, uint32_t width, uint32_t height);
-/*
- * Instructs the algorithm library to initialize a new structure to hold
- * biometric image of given dimensions acquired from given sensor.
- * It will return image handle that will be used in other calls to identify
- * the image involved in the operation.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_image_create(bio_sensor_t sensor, uint32_t width, uint32_t height,
-		     bio_image_t *image);
-/*
- * Communicates dimensions of image to the algorithm library.
- * Can be used if image is less than full sensor resolution.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_image_set_size(bio_image_t image, uint32_t width, uint32_t height);
-/*
- * Attaches data from biometric sensor to image structure. The caller must
- * ensure that there is enough of data for given image dimensions for given
- * format used by the sensor.
- *
- * It is assumes that the data pointer stays valid until bio_image_destroy()
- * is called.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_image_set_data(bio_image_t image, const uint8_t *data, size_t size);
-/*
- * Releases all resources held by the library in conjunction with given image.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_image_destroy(bio_image_t image);
-
-/*
- * Compares given biometric image against a list of enrolled template(s).
- * In case the image match a template the match_index will indicate which
- * template in the list that matched.
- * The algorithm library can update templates with additional biometric data
- * from the image, if it chooses to do so. The updated template(s) will be
- * indicated by the out parameter 'updated_templates', a bit-field where
- * updated template(s) indicated by the corresponding bit being set
- * Returns:
- * - negative value on error
- * - BIO_TEMPLATE_NO_MATCH on non-match
- * - BIO_TEMPLATE_MATCH for match when template was not updated with new data
- * - BIO_TEMPLATE_MATCH_UPDATED for match when template was updated
- * - BIO_TEMPLATE_MATCH_UPDATE_FAILED match, but update failed (do not save)
- * - BIO_TEMPLATE_LOW_QUALITY when matching could not be performed due to low
- *   image quality
- * - BIO_TEMPLATE_LOW_COVERAGE when matching could not be performed due to
- *   finger covering too little area of the sensor
- */
-int bio_template_image_match_list(bio_template_t tmpl, uint32_t num_templates,
-				  bio_image_t image, int32_t *match_index,
-				  uint32_t *updated_templates);
-int bio_template_image_match(bio_template_t tmpl, bio_image_t image);
-/*
- * Returns size of template data in serialized form.
- *
- * Returns negative error code (such as -EINVAL) on failure, or size of the
- * serialized form in bytes.
- */
-ssize_t bio_template_get_serialized_size(bio_template_t tmpl);
-/*
- * Releases all resources held by the library in conjunction with given
- * template.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_template_destroy(bio_template_t tmpl);
-/*
- * Initiates biometric data enrollment process. Algorithm library returns
- * 'enrollment handle' that is used for all subsequent enrollment operations.
- *
- * Returns 0 on success, negative error code (such as -ENOMEM) on failure.
- */
-int bio_enrollment_begin(bio_sensor_t sensor, bio_enrollment_t *enrollment);
-/*
- * Adds fingerprint image to an enrollment.
- *
- * The library should expect to copy any relevant data from the “image�
- * as it is likely to be destroyed (via bio_image_destroy() call) shortly after
- * this call completes.
- *
- * Returns:
- * - negative value on error
- * - BIO_ENROLLMENT_OK when image was successfully enrolled
- * - BIO_ENROLLMENT_IMMOBILE when image added, but user should be advised
- *   to move finger
- * - BIO_ENROLLMENT_LOW_QUALITY when image could not be used due to low
- *   image quality
- * - BIO_ENROLLMENT_LOW_COVERAGE when image could not be used  due to
- *   finger covering too little area of the sensor
- */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
-/* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
-int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
-/*
- * Indicates whether there is enough data in the enrollment for it to be
- * converted into a template to be used for identification.
- *
- * Returns 0 for if enrollment does not have enough data yet, 1 if enrollment
- * is complete, or negative error code (such as -EINVAL) on failure.
- *
- */
-int bio_enrollment_is_complete(bio_enrollment_t enrollment);
-/*
- * Returns percent of coverage accumulated during enrollment process.
- * Optional method. Regardless of value returned by this call user should call
- * bio_enrollment_is_complete() to check if algorithm library accumulated enough
- * data to create a template.
- *
- * Returns value in the range 0..100, or negative error (such as -EINVAL);
- */
-int bio_enrollment_get_percent_complete(bio_enrollment_t enrollment);
-/*
- * Indicates that given enrollment process is complete, and algorithm library
- * should generate an active template that can be used in subsequent calls
- * to bio_image_match() and bio_template_serialize() from enrollment data.
- * After the template is created the library should release all resources
- * associated with this enrollment.
- *
- * Argument 'tmpl' is optional and can be set to NULL if caller wishes to
- * abort enrollment process.
- *
- * Returns 0 on success, negative error code (such as -EINVAL) on failure.
- */
-int bio_enrollment_finish(bio_enrollment_t enrollment, bio_template_t *tmpl);
-
-typedef struct {
-	int32_t coverage;     /* Sensor coverage in range [0..100]        */
-	int32_t quality;      /* Image quality in range [0..100]          */
-	int32_t min_coverage; /* Minimum coverage accepted by enroll      */
-	int32_t min_quality;  /* Minimum image quality accepted by enroll */
-} bio_image_status_t;
-
-/*
- * Get the image quality and threshold values for a bio_image_t
- *
- * @param[in]  image         Image data as acquired by
- *                           fp_sensor_acquire_image_with_mode
- * @param[out] image_status  Populated structure with quality/coverage values
- *                           and corresponding threshold values
- *
- * @note This function will alter the internal states of the bio algorithm
- *       library and must not be used during an enroll sequence. The typical
- *       use case for this function is to qualify images during image
- *       collection.
- *
- * @return negative on error.
- * @return 0 if the quality and coverage threshold values aren't reached.
- * @return 1 if the quality and coverage threshold values are reached.
- */
-int bio_sensor_get_image_status(bio_image_t image,
-				bio_image_status_t *image_status);
-
-#endif /* BIOD_BIO_ALGORITHM_H_ */
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c
deleted file mode 100644
index 34fc61f66c..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc_private.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include "common.h"
-#include "console.h"
-#include "endian.h"
-#include "fpc_bio_algorithm.h"
-#include "fpc_private.h"
-#include "fpsensor.h"
-#include "gpio.h"
-#include "link_defs.h"
-#include "spi.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-
-#include "driver/fingerprint/fpc/fpc_sensor.h"
-
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
-/* Minimum reset duration */
-#define FP_SENSOR_RESET_DURATION_US (10 * MSEC)
-/* Maximum delay for the interrupt to be asserted after the sensor is reset */
-#define FP_SENSOR_IRQ_MAX_DELAY_US (5 * MSEC)
-/* Maximum number of attempts to initialise the sensor */
-#define FP_SENSOR_MAX_INIT_ATTEMPTS 10
-/* Delay between failed attempts of fp_sensor_open() */
-#define FP_SENSOR_OPEN_DELAY_US (500 * MSEC)
-
-/* Decode internal error codes from FPC's sensor library */
-#define FPC_GET_INTERNAL_CODE(res) (((res) & 0x000fc000) >> 14)
-/* There was a finger on the sensor when calibrating finger detect */
-#define FPC_INTERNAL_FINGER_DFD FPC_ERROR_INTERNAL_38
-
-/*
- * The sensor context is uncached as it contains the SPI buffers,
- * the binary library assumes that it is aligned.
- */
-static uint8_t ctx[FP_SENSOR_CONTEXT_SIZE] __uncached __aligned(4);
-static bio_sensor_t bio_sensor;
-static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4);
-
-/* recorded error flags */
-static uint16_t errors;
-
-/* Sensor description */
-static struct ec_response_fp_info fpc1145_info = {
-	/* Sensor identification */
-	.vendor_id = FOURCC('F', 'P', 'C', ' '),
-	.product_id = 9,
-	.model_id = 1,
-	.version = 1,
-	/* Image frame characteristics */
-	.frame_size = FP_SENSOR_IMAGE_SIZE,
-	.pixel_format = V4L2_PIX_FMT_GREY,
-	.width = FP_SENSOR_RES_X,
-	.height = FP_SENSOR_RES_Y,
-	.bpp = FP_SENSOR_RES_BPP,
-};
-
-/* Sensor IC commands */
-enum fpc_cmd {
-	FPC_CMD_STATUS            = 0x14,
-	FPC_CMD_INT_STS           = 0x18,
-	FPC_CMD_INT_CLR           = 0x1C,
-	FPC_CMD_FINGER_QUERY      = 0x20,
-	FPC_CMD_SLEEP             = 0x28,
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_SOFT_RESET        = 0xF8,
-	FPC_CMD_HW_ID             = 0xFC,
-};
-
-/* Maximum size of a sensor command SPI transfer */
-#define MAX_CMD_SPI_TRANSFER_SIZE 3
-
-/* Uncached memory for the SPI transfer buffer */
-static uint8_t spi_buf[MAX_CMD_SPI_TRANSFER_SIZE] __uncached;
-
-static int fpc_send_cmd(const uint8_t cmd)
-{
-	spi_buf[0] = cmd;
-	return spi_transaction(SPI_FP_DEVICE, spi_buf, 1, spi_buf,
-			       SPI_READBACK_ALL);
-}
-
-void fp_sensor_low_power(void)
-{
-	/*
-	 * TODO(b/117620462): verify that sleep mode is WAI (no increased
-	 * latency, expected power consumption).
-	 */
-	if (0)
-		fpc_send_cmd(FPC_CMD_SLEEP);
-}
-
-int fpc_check_hwid(void)
-{
-	uint16_t id;
-	int rc;
-
-	/* Clear previous occurences of relevant |errors| flags. */
-	errors &= (~FP_ERROR_SPI_COMM & ~FP_ERROR_BAD_HWID);
-
-	spi_buf[0] = FPC_CMD_HW_ID;
-	rc = spi_transaction(SPI_FP_DEVICE, spi_buf, 3, spi_buf,
-			     SPI_READBACK_ALL);
-	if (rc) {
-		CPRINTS("FPC ID read failed %d", rc);
-		errors |= FP_ERROR_SPI_COMM;
-		return EC_ERROR_HW_INTERNAL;
-	}
-	id = (spi_buf[1] << 8) | spi_buf[2];
-	if ((id >> 4) != FP_SENSOR_HWID) {
-		CPRINTS("FPC unknown silicon 0x%04x", id);
-		errors |= FP_ERROR_BAD_HWID;
-		return EC_ERROR_HW_INTERNAL;
-	}
-	CPRINTS(FP_SENSOR_NAME " id 0x%04x", id);
-
-	return EC_SUCCESS;
-}
-
-static uint8_t fpc_read_clear_int(void)
-{
-	spi_buf[0] = FPC_CMD_INT_CLR;
-	spi_buf[1] = 0xff;
-	if (spi_transaction(SPI_FP_DEVICE, spi_buf, 2, spi_buf,
-			    SPI_READBACK_ALL))
-		return 0xff;
-	return spi_buf[1];
-}
-
-/*
- * Toggle the h/w reset pins and clear any pending IRQs before initializing the
- * sensor contexts.
- * Returns:
- * - EC_SUCCESS on success.
- * - EC_ERROR_HW_INTERNAL on failure (and |errors| variable is updated where
- *   appropriate).
- */
-static int fpc_pulse_hw_reset(void)
-{
-	int ret;
-	int rc = EC_SUCCESS;
-	/* Clear previous occurrence of possible error flags. */
-	errors &= ~FP_ERROR_NO_IRQ;
-
-	/* Ensure we pulse reset low to initiate the startup */
-	gpio_set_level(GPIO_FP_RST_ODL, 0);
-	usleep(FP_SENSOR_RESET_DURATION_US);
-	gpio_set_level(GPIO_FP_RST_ODL, 1);
-	/* the IRQ line should be set high by the sensor */
-	usleep(FP_SENSOR_IRQ_MAX_DELAY_US);
-	if (!gpio_get_level(GPIO_FPS_INT)) {
-		CPRINTS("Sensor IRQ not ready");
-		errors |= FP_ERROR_NO_IRQ;
-		rc = EC_ERROR_HW_INTERNAL;
-	}
-
-	/* Check the Hardware ID */
-	ret = fpc_check_hwid();
-	if (ret != EC_SUCCESS) {
-		CPRINTS("Failed to verify HW ID");
-		rc = EC_ERROR_HW_INTERNAL;
-	}
-
-	/* clear the pending 'ready' IRQ before enabling interrupts */
-	fpc_read_clear_int();
-
-	return rc;
-}
-
-/* Reset and initialize the sensor IC */
-int fp_sensor_init(void)
-{
-	int res;
-	int attempt;
-
-	errors = FP_ERROR_DEAD_PIXELS_UNKNOWN;
-
-	/* Release any previously held resources from earlier iterations */
-	res = bio_sensor_destroy(bio_sensor);
-	if (res)
-		CPRINTS("FPC Sensor resources release failed: %d", res);
-	bio_sensor = NULL;
-
-	res = bio_algorithm_exit();
-	if (res)
-		CPRINTS("FPC Algorithm resources release failed: %d", res);
-
-	/* Print the binary libfpsensor.a library version */
-	CPRINTF("FPC libfpsensor.a v%s\n", fp_sensor_get_version());
-	cflush();
-
-	attempt = 0;
-	do {
-		attempt++;
-
-		res = fpc_pulse_hw_reset();
-		if (res != EC_SUCCESS) {
-			/* In case of failure, retry after a delay. */
-			CPRINTS("H/W sensor reset failed, error flags: 0x%x",
-				errors);
-			cflush();
-			usleep(FP_SENSOR_OPEN_DELAY_US);
-			continue;
-		}
-
-		/*
-		 * Ensure that any previous context data is obliterated in case
-		 * of a sensor reset.
-		 */
-		memset(ctx, 0, FP_SENSOR_CONTEXT_SIZE);
-
-		res = fp_sensor_open(ctx, FP_SENSOR_CONTEXT_SIZE);
-		/* Flush messages from the PAL if any */
-		cflush();
-		CPRINTS("Sensor init (attempt %d): 0x%x", attempt, res);
-		/*
-		 * Retry on failure. This typically happens if the user has left
-		 * their finger on the sensor after powering up the device, DFD
-		 * will fail in that case. We've seen other error modes in the
-		 * field, retry in all cases to be more resilient.
-		 */
-		if (!res)
-			break;
-		usleep(FP_SENSOR_OPEN_DELAY_US);
-	} while (attempt < FP_SENSOR_MAX_INIT_ATTEMPTS);
-	if (res)
-		errors |= FP_ERROR_INIT_FAIL;
-
-	res = bio_algorithm_init();
-	/* the PAL might have spewed a lot of traces, ensure they are visible */
-	cflush();
-	CPRINTS("Algorithm init: 0x%x", res);
-	if (res < 0)
-		errors |= FP_ERROR_INIT_FAIL;
-	res = bio_sensor_create(&bio_sensor);
-	CPRINTS("Sensor create: 0x%x", res);
-	if (res < 0)
-		errors |= FP_ERROR_INIT_FAIL;
-
-	/* Go back to low power */
-	fp_sensor_low_power();
-
-	return EC_SUCCESS;
-}
-
-/* Deinitialize the sensor IC */
-int fp_sensor_deinit(void)
-{
-	/*
-	 * TODO(tomhughes): libfp doesn't have fp_sensor_close like BEP does.
-	 * We'll need FPC to either add it or verify that we don't have the same
-	 * problem with the libfp library as described in:
-	 * b/124773209#comment46
-	 */
-	return EC_SUCCESS;
-}
-
-int fp_sensor_get_info(struct ec_response_fp_info *resp)
-{
-	int rc;
-
-	memcpy(resp, &fpc1145_info, sizeof(*resp));
-
-	spi_buf[0] = FPC_CMD_HW_ID;
-	rc = spi_transaction(SPI_FP_DEVICE, spi_buf, 3, spi_buf,
-			     SPI_READBACK_ALL);
-	if (rc)
-		return EC_RES_ERROR;
-	resp->model_id = (spi_buf[1] << 8) | spi_buf[2];
-	resp->errors = errors;
-
-	return EC_SUCCESS;
-}
-
-int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
-		    int32_t *match_index, uint32_t *update_bitmap)
-{
-	return bio_template_image_match_list(templ, templ_count, image,
-					     match_index, update_bitmap);
-}
-
-int fp_enrollment_begin(void)
-{
-	int rc;
-	bio_enrollment_t p = enroll_ctx;
-
-	rc = bio_enrollment_begin(bio_sensor, &p);
-	if (rc < 0)
-		CPRINTS("begin failed %d", rc);
-	return rc;
-}
-
-int fp_enrollment_finish(void *templ)
-{
-	bio_template_t pt = templ;
-
-	return bio_enrollment_finish(enroll_ctx, templ ? &pt : NULL);
-}
-
-int fp_finger_enroll(uint8_t *image, int *completion)
-{
-	int rc = bio_enrollment_add_image(enroll_ctx, image);
-
-	if (rc < 0)
-		return rc;
-	*completion = bio_enrollment_get_percent_complete(enroll_ctx);
-	return rc;
-}
-
-int fp_maintenance(void)
-{
-	return fpc_fp_maintenance(&errors);
-}
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.h b/driver/fingerprint/fpc/libfp/fpc_private.h
deleted file mode 100644
index 95313726f6..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc_private.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Private sensor interface */
-
-#ifndef __CROS_EC_FPC_PRIVATE_H
-#define __CROS_EC_FPC_PRIVATE_H
-
-/* External error codes from FPC's sensor library */
-enum fpc_error_code_external {
-	FPC_ERROR_NONE                        = 0,
-	FPC_ERROR_NOT_FOUND                   = 1,
-	FPC_ERROR_CAN_BE_USED_2               = 2,
-	FPC_ERROR_CAN_BE_USED_3               = 3,
-	FPC_ERROR_CAN_BE_USED_4               = 4,
-	FPC_ERROR_PAL                         = 5,
-	FPC_ERROR_IO                          = 6,
-	FPC_ERROR_CANCELLED                   = 7,
-	FPC_ERROR_UNKNOWN                     = 8,
-	FPC_ERROR_MEMORY                      = 9,
-	FPC_ERROR_PARAMETER                   = 10,
-	FPC_ERROR_TEST_FAILED                 = 11,
-	FPC_ERROR_TIMEDOUT                    = 12,
-	FPC_ERROR_SENSOR                      = 13,
-	FPC_ERROR_SPI                         = 14,
-	FPC_ERROR_NOT_SUPPORTED               = 15,
-	FPC_ERROR_OTP                         = 16,
-	FPC_ERROR_STATE                       = 17,
-	FPC_ERROR_PN                          = 18,
-	FPC_ERROR_DEAD_PIXELS                 = 19,
-	FPC_ERROR_TEMPLATE_CORRUPTED          = 20,
-	FPC_ERROR_CRC                         = 21,
-	FPC_ERROR_STORAGE                     = 22, /**< Errors related to storage                  **/
-	FPC_ERROR_MAXIMUM_REACHED             = 23, /**< The allowed maximum has been reached       **/
-	FPC_ERROR_MINIMUM_NOT_REACHED         = 24, /**< The required minimum was not reached       **/
-	FPC_ERROR_SENSOR_LOW_COVERAGE         = 25, /**< Minimum sensor coverage was not reached    **/
-	FPC_ERROR_SENSOR_LOW_QUALITY          = 26, /**< Sensor image is considered low quality     **/
-	FPC_ERROR_SENSOR_FINGER_NOT_STABLE    = 27, /**< Finger was not stable during image capture **/
-};
-
-/* Internal error codes from FPC's sensor library */
-enum fpc_error_code_internal {
-	FPC_ERROR_INTERNAL_0  = 0,  /* Indicates that no internal code was set.                         */
-	FPC_ERROR_INTERNAL_1  = 1,  /* Not supported by sensor.                                         */
-	FPC_ERROR_INTERNAL_2  = 2,  /* Sensor got a NULL response (from other module).                  */
-	FPC_ERROR_INTERNAL_3  = 3,  /* Runtime config not supported by firmware.                        */
-	FPC_ERROR_INTERNAL_4  = 4,  /* CAC has not been created.                                        */
-	FPC_ERROR_INTERNAL_5  = 5,  /* CAC returned an error to the sensor.                             */
-	FPC_ERROR_INTERNAL_6  = 6,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_7  = 7,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_8  = 8,  /* CAC Simple image capture failed.                                 */
-	FPC_ERROR_INTERNAL_9  = 9,  /* CAC custom image capture failed.                                 */
-	FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed.                                    */
-	FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed.                                     */
-	FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid.                                          */
-	FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid.                                     */
-	FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid.                                */
-	FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid.                                 */
-	FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid.                               */
-	FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid.                             */
-	FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be extracted.                   */
-	FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component.                                  */
-	FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed.                                           */
-	FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed.                                     */
-	FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be extracted.                */
-	FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be extracted.                  */
-	FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid.                                     */
-	FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read.                                  */
-	FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs rrs.                     */
-	FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed.                                     */
-	FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp calibration.                 */
-	FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image.                             */
-	FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration.                         */
-	FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid.                          */
-	FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed.                                   */
-	FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete.                              */
-	FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after calibration.                   */
-	FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size.                                                  */
-	FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when calibrating finger detect. */
-	FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is larger than max.             */
-	FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows                                */
-	FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a too high or low value   */
-	FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL configuration                 */
-	FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw descriptor                  */
-	FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test                            */
-};
-
-/* FPC specific initialization function to fill their context */
-int fp_sensor_open(void *ctx, uint32_t ctx_size);
-
-/*
- * Get library version code.
- * version code contains three digits. x.y.z
- *   x - major version
- *   y - minor version
- *   z - build index
- */
-const char *fp_sensor_get_version(void);
-
-typedef struct {
-	uint32_t num_defective_pixels;
-} fp_sensor_info_t;
-
-/**
- * fp_sensor_maintenance runs a test for defective pixels and should
- * be triggered periodically by the client. Internally, a defective
- * pixel list is maintained and the algorithm will compensate for
- * any defect pixels when matching towards a template.
- *
- * The defective pixel update will abort and return an error if any of
- * the finger detect zones are covered. A client can call
- * fp_sensor_finger_status to determine the current status.
- *
- * @param[in]  image_data      pointer to FP_SENSOR_IMAGE_SIZE bytes of memory
- * @param[out] fp_sensor_info  Structure containing output data.
- *
- * @return
- * - 0 on success
- * - negative value on error
- */
-int fp_sensor_maintenance(uint8_t *image_data,
-			  fp_sensor_info_t *fp_sensor_info);
-
-/* Read the HWID from the sensor. */
-int fpc_check_hwid(void);
-
-#endif /* __CROS_EC_FPC_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
deleted file mode 100644
index 35c07b464a..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* FPC Platform Abstraction Layer callbacks */
-
-#include "common.h"
-#include "console.h"
-#include "fpsensor.h"
-#include "fpc_sensor_pal.h"
-#include "shared_mem.h"
-#include "spi.h"
-#include "timer.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
-
-void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	uart_puts(tag);
-	uart_vprintf(format, args);
-	va_end(args);
-}
-
-int fpc_pal_delay_us(uint64_t us)
-{
-	if (us > 250)
-		usleep(us);
-	else
-		udelay(us);
-	return 0;
-}
-
-int fpc_pal_spi_writeread(fpc_device_t device, uint8_t *tx_buf, uint8_t *rx_buf,
-			  uint32_t size)
-{
-	return spi_transaction(SPI_FP_DEVICE, tx_buf, size, rx_buf,
-			       SPI_READBACK_ALL);
-}
-
-int fpc_pal_wait_irq(fpc_device_t device, fpc_pal_irq_t irq_type)
-{
-	/* TODO: b/72360575 */
-	return EC_SUCCESS; /* just lie about it, libfpsensor prefers... */
-}
-
-int32_t FpcMalloc(void **data, size_t size)
-{
-	return shared_mem_acquire(size, (char **)data);
-}
-
-void FpcFree(void **data)
-{
-	shared_mem_release(*data);
-}
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
deleted file mode 100644
index 78376863f1..0000000000
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef FPC_PAL_SENSOR_H_
-#define FPC_PAL_SENSOR_H_
-
-#include <stdint.h>
-
-typedef void *fpc_device_t;
-
-/**
- * @brief Used to describe an interrupt
- */
-typedef enum {
-    IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast interrupt)                   **/
-    IRQ_EXT_TRIG = 0x02  /**< Externally triggered by event outside sensor (may take long time) **/
-} fpc_pal_irq_t;
-
-/**
- * @brief Write sensor access buffer to SPI interface
- *
- * @param[in] device             Client's device handle.
- * @param[in] access_buffer      Buffer holding data to write.
- * @param[in] access_buffer_size Size of the access buffer.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_spi_write(fpc_device_t device, uint8_t *access_buffer,
-		      uint32_t access_buffer_size);
-
-/**
- * @brief Write and read sensor access buffer to SPI interface
- *
- * SPI transfers always write the same number of bytes as they read,
- * hence the size of tx_buffer and rx_buffer must be the same.
- *
- * @param[in] device    Client's device handle.
- * @param[in] tx_buffer Buffer holding data to write.
- * @param[in] rx_buffer Buffer where read data will be stored.
- * @param[in] size      Size of tx and rx buffer.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_spi_writeread(fpc_device_t device, uint8_t *tx_buffer,
-			  uint8_t *rx_buffer, uint32_t size);
-
-/**
- * @brief Wait for IRQ
- *
- * @param[in] device   Client's device handle.
- * @param[in] irq_type The expected IRQ type.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_wait_irq(fpc_device_t device, fpc_pal_irq_t irq_type);
-
-/**
- * @brief Get time
- *
- * @param[out] time_us Timestamp in microseconds.
- *
- * Not all platforms have microsecond resolution. These should
- * return time in terms of hole milliseconds.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_get_time(uint64_t *time_us);
-
-/**
- * @brief Delay function
- *
- * @param[in] us Delay in microseconds.
- *
- * Not all platforms have microsecond resolution. These should
- * delay in terms of hole milliseconds.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_delay_us(uint64_t us);
-
-/**
- * @brief Get platform SPI clock frequency
- *
- * @param[in]  device   Client's device handle.
- * @param[out] speed_hz SPI frequency in hertz.
- *
- * Required by platform for adaptive SPI calculations.
- *
- * @return 0 on success.
- *         negative value on error.
- */
-int fpc_pal_spi_get_speed_hz(fpc_device_t device, uint32_t *speed_hz);
-
-/**
- * @brief Print SDK log strings
- *
- * @param[in] tag sensor sdk log prefix
- * @param[in] log_level  FPC_SENSOR_SDK_LOG_LEVEL_DEBUG - debug print
- *                       FPC_SENSOR_SDK_LOG_LEVEL_INFO  - information print
- *                       FPC_SENSOR_SDK_LOG_LEVEL_ERROR - error print
- * @param[in] format     the format specifier.
- * @param[in] ...        additional arguments.
- *
- */
-#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG    (1)
-#define FPC_SENSOR_SDK_LOG_LEVEL_INFO     (2)
-#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR    (3)
-#define FPC_SENSOR_SDK_LOG_LEVEL_DISABLED (4)
-void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...);
-
-#endif // FPC_PAL_SENSOR_H_
diff --git a/driver/fingerprint/fpsensor.h b/driver/fingerprint/fpsensor.h
deleted file mode 100644
index ac7e31fb6a..0000000000
--- a/driver/fingerprint/fpsensor.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_
-#define __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_
-
-#if defined(HAVE_PRIVATE) && !defined(EMU_BUILD)
-#define HAVE_FP_PRIVATE_DRIVER
-#if defined(CONFIG_FP_SENSOR_ELAN80) || defined(CONFIG_FP_SENSOR_ELAN515)
-#include "elan/elan_sensor.h"
-#else
-#include "fpc/fpc_sensor.h"
-#endif
-#else
-/* These values are used by the host (emulator) tests. */
-#define FP_SENSOR_IMAGE_SIZE 0
-#define FP_SENSOR_RES_X 0
-#define FP_SENSOR_RES_Y 0
-#define FP_ALGORITHM_TEMPLATE_SIZE 0
-#define FP_MAX_FINGER_COUNT 5
-#endif
-
-#if defined(HAVE_PRIVATE) && defined(TEST_BUILD)
-/*
- * For unittest in a private build, enable driver-related code in
- * common/fpsensor/ so that they can be tested (with fp_sensor_mock).
- */
-#define HAVE_FP_PRIVATE_DRIVER
-#endif
-
-#endif /* __CROS_EC_DRIVER_FINGERPRINT_FPSENSOR_H_ */
diff --git a/driver/gl3590.c b/driver/gl3590.c
deleted file mode 100644
index cb8d914d8c..0000000000
--- a/driver/gl3590.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "util.h"
-#include "pwr_defs.h"
-
-#include "gl3590.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-/* GL3590 is unique in terms of i2c_read, since it doesn't support repeated
- * start sequence. One need to issue two separate transactions - first is write
- * with a register offset, then after a delay second transaction is actual read.
- */
-int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count)
-{
-	int rv;
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       &reg, 1,
-			       NULL, 0,
-			       I2C_XFER_SINGLE);
-	i2c_lock(uhub_p->i2c_host_port, 0);
-
-	if (rv)
-		return rv;
-
-	/* GL3590 requires at least 1ms between consecutive i2c transactions */
-	udelay(MSEC);
-
-	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       NULL, 0,
-			       data, count,
-			       I2C_XFER_SINGLE);
-	i2c_lock(uhub_p->i2c_host_port, 0);
-
-	/*
-	 * GL3590 requires at least 1ms between consecutive i2c transactions.
-	 * Make sure that we are safe across API calls.
-	 */
-	udelay(MSEC);
-
-	return rv;
-};
-
-int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count)
-{
-	int rv;
-	uint8_t buf[5];
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	/* GL3590 registers accept 4 bytes at max */
-	if (count > (sizeof(buf) - 1)) {
-		ccprintf("Too many bytes to write");
-		return EC_ERROR_INVAL;
-	}
-
-	buf[0] = reg;
-	memcpy(&buf[1], data, count);
-
-	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       buf, count + 1,
-			       NULL, 0,
-			       I2C_XFER_SINGLE);
-	i2c_lock(uhub_p->i2c_host_port, 0);
-
-	/*
-	 * GL3590 requires at least 1ms between consecutive i2c transactions.
-	 * Make sure that we are safe across API calls.
-	 */
-	udelay(MSEC);
-
-	return rv;
-}
-
-/*
- * Basic initialization of GL3590 I2C interface.
- *
- * Please note, that I2C interface is online not earlier than ~50ms after
- * RESETJ# is deasserted. Platform should check that PGREEN_A_SMD pin is
- * asserted. This init function shouldn't be invoked until that time.
- */
-void gl3590_init(int hub)
-{
-	uint8_t tmp;
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	if (uhub_p->initialized)
-		return;
-
-	if (gl3590_read(hub, GL3590_HUB_MODE_REG, &tmp, 1)) {
-		CPRINTF("GL3590: Cannot read HUB_MODE register");
-		return;
-	}
-	if ((tmp & GL3590_HUB_MODE_I2C_READY) == 0)
-		CPRINTF("GL3590 interface isn't ready, consider deferring "
-			"this init\n");
-
-	/* Deassert INTR# signal */
-	tmp = GL3590_INT_CLEAR;
-	if (gl3590_write(hub, GL3590_INT_REG, &tmp, 1)) {
-		CPRINTF("GL3590: Cannot write to INT register");
-		return;
-	};
-
-	uhub_p->initialized = 1;
-}
-
-/*
- * GL3590 chip may drive I2C_SDA and I2C_SCL lines for 200ms (max) after it is
- * released from reset (through gpio de-assertion in main()). In order to avoid
- * broken I2C transactions, we need to add an extra delay before any activity on
- * the I2C bus in the system.
- */
-static void gl3590_delay_on_init(void)
-{
-	CPRINTS("Applying 200ms delay for GL3590 to release I2C lines");
-	udelay(200 * MSEC);
-}
-DECLARE_HOOK(HOOK_INIT, gl3590_delay_on_init, HOOK_PRIO_INIT_I2C - 1);
-
-void gl3590_irq_handler(int hub)
-{
-	uint8_t buf = 0;
-	uint8_t res_reg[2];
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	if (!uhub_p->initialized)
-		return;
-
-	/* Verify that irq is pending */
-	if (gl3590_read(hub, GL3590_INT_REG, &buf, sizeof(buf))) {
-		ccprintf("Cannot read from the host hub i2c\n");
-		goto exit;
-	}
-
-	if ((buf & GL3590_INT_PENDING) == 0) {
-		ccprintf("Invalid hub event\n");
-		goto exit;
-	}
-
-	/* Get the hub event reason */
-	if (gl3590_read(hub, GL3590_RESPONSE_REG, res_reg, sizeof(res_reg))) {
-		ccprintf("Cannot read from the host hub i2c\n");
-		goto exit;
-	}
-
-	if ((res_reg[0] & GL3590_RESPONSE_REG_SYNC_MASK) == 0)
-		ccprintf("Host hub response: ");
-	else
-		ccprintf("Host hub event! ");
-
-	switch(res_reg[0]) {
-	case 0x0:
-		ccprintf("No response");
-		break;
-	case 0x1:
-		ccprintf("Successful");
-		break;
-	case 0x2:
-		ccprintf("Invalid command");
-		break;
-	case 0x3:
-		ccprintf("Invalid arguments");
-		break;
-	case 0x4:
-		ccprintf("Invalid port: %d", res_reg[1]);
-		break;
-	case 0x5:
-		ccprintf("Command not completed");
-		break;
-	case 0x80:
-		ccprintf("Reset complete");
-		break;
-	case 0x81:
-		ccprintf("Power operation mode change");
-		break;
-	case 0x82:
-		ccprintf("Connect change");
-		break;
-	case 0x83:
-		ccprintf("Error on the specific port");
-		break;
-	case 0x84:
-		ccprintf("Hub state change");
-		break;
-	case 0x85:
-		ccprintf("SetFeature PORT_POWER failure");
-		break;
-	default:
-		ccprintf("Unknown value: 0x%0x", res_reg[0]);
-	}
-	ccprintf("\n");
-
-	if (res_reg[1])
-		ccprintf("Affected port %d\n", res_reg[1]);
-
-exit:
-	/* Try to clear interrupt */
-	buf = GL3590_INT_CLEAR;
-	gl3590_write(hub, GL3590_INT_REG, &buf, sizeof(buf));
-}
-
-enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr)
-{
-	uint8_t hub_sts, hub_mode;
-	int rv = 0;
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	if (!uhub_p->initialized)
-		return EC_ERROR_HW_INTERNAL;
-
-	if (gl3590_read(hub, GL3590_HUB_STS_REG, &hub_sts, sizeof(hub_sts))) {
-		CPRINTF("Error reading HUB_STS %d\n", rv);
-		return EC_ERROR_BUSY;
-	}
-
-	pwr->volts = 5;
-
-	switch ((hub_sts & GL3590_HUB_STS_HOST_PWR_MASK) >>
-		GL3590_HUB_STS_HOST_PWR_SHIFT) {
-	case GL3590_DEFAULT_HOST_PWR_SRC:
-		if (gl3590_read(hub, GL3590_HUB_MODE_REG, &hub_mode,
-				sizeof(hub_mode))) {
-			CPRINTF("Error reading HUB_MODE %d\n", rv);
-			return EC_ERROR_BUSY;
-		}
-		if (hub_mode & GL3590_HUB_MODE_USB3_EN) {
-			pwr->milli_amps = 900;
-			return EC_SUCCESS;
-		} else if (hub_mode & GL3590_HUB_MODE_USB2_EN) {
-			pwr->milli_amps = 500;
-			return EC_SUCCESS;
-		} else {
-			CPRINTF("GL3590: Neither USB3 nor USB2 hubs "
-				 "configured\n");
-			return EC_ERROR_HW_INTERNAL;
-		}
-	case GL3590_1_5_A_HOST_PWR_SRC:
-		pwr->milli_amps = 1500;
-		return EC_SUCCESS;
-	case GL3590_3_0_A_HOST_PWR_SRC:
-		pwr->milli_amps = 3000;
-		return EC_SUCCESS;
-	default:
-		CPRINTF("GL3590: Unkown host power source %d\n", hub_sts);
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-#define GL3590_EN_PORT_MAX_RETRY_COUNT	10
-
-int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable)
-{
-	uint8_t buf[4] = {0};
-	uint8_t en_mask = 0;
-	uint8_t tmp;
-	int rv, i;
-	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
-
-	if (!uhub_p->initialized)
-		return EC_ERROR_HW_INTERNAL;
-
-	if (!enable)
-		en_mask = port_mask;
-
-	buf[0] = en_mask;
-	buf[2] = port_mask;
-
-	for (i = 1; i <= GL3590_EN_PORT_MAX_RETRY_COUNT; i++) {
-		rv = gl3590_write(hub, GL3590_PORT_DISABLED_REG, buf,
-				  sizeof(buf));
-		if (rv)
-			return rv;
-
-		usleep(200 * MSEC);
-
-		/* Verify whether port is enabled/disabled */
-		rv = gl3590_read(hub, GL3590_PORT_EN_STS_REG, &tmp, 1);
-		if (rv)
-			return rv;
-
-		if (enable && ((tmp & port_mask) == port_mask))
-			break;
-		if (!enable && ((tmp & port_mask) == 0))
-			break;
-
-		if (i > GL3590_EN_PORT_MAX_RETRY_COUNT) {
-			CPRINTF("GL3590: Failed to %s port 0x%x\n",
-				enable ? "enable" : "disable", port_mask);
-			return EC_ERROR_HW_INTERNAL;
-		}
-
-		CPRINTF("GL3590: Port %s retrying.. %d/%d\n"
-			"Port status is 0x%x\n", enable ? "enable" : "disable",
-			i, GL3590_EN_PORT_MAX_RETRY_COUNT, tmp);
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_GL3590
-static int command_gl3590(int argc, char **argv)
-{
-	char *e;
-	int port;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[2], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM2;
-
-	if (strcasecmp(argv[1], "enable") == 0) {
-		if (!gl3590_enable_ports(0, port, 1))
-			return EC_SUCCESS;
-		else
-			return EC_ERROR_HW_INTERNAL;
-	} else if (strcasecmp(argv[1], "disable") == 0) {
-		if (!gl3590_enable_ports(0, port, 0))
-			return EC_SUCCESS;
-		else
-			return EC_ERROR_HW_INTERNAL;
-	}
-
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(gl3590, command_gl3590,
-			"<enable | disable> <port_bitmask>",
-			"Manage GL3590 USB3.1 hub and its ports");
-#endif /* CONFIG_CMD_GL3590 */
diff --git a/driver/gl3590.h b/driver/gl3590.h
deleted file mode 100644
index 931035d95e..0000000000
--- a/driver/gl3590.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "pwr_defs.h"
-#include "stdbool.h"
-
-/* Registers definitions */
-#define GL3590_HUB_MODE_REG		0x0
-#define GL3590_HUB_MODE_I2C_READY	0x1
-#define GL3590_HUB_MODE_USB2_EN		0x2
-#define GL3590_HUB_MODE_USB3_EN		0x4
-#define GL3590_INT_REG			0x1
-#define GL3590_INT_PENDING		0x1
-#define GL3590_INT_CLEAR		0x1
-#define GL3590_RESPONSE_REG		0x2
-#define GL3590_RESPONSE_REG_SYNC_MASK	0x80
-#define GL3590_PORT_DISABLED_REG	0x4
-#define GL3590_PORT_EN_STS_REG		0x8
-#define GL3590_HUB_STS_REG 		0xA
-#define GL3590_HUB_STS_HOST_PWR_MASK	0x30
-#define GL3590_HUB_STS_HOST_PWR_SHIFT	4
-#define GL3590_DEFAULT_HOST_PWR_SRC	0x0
-#define GL3590_1_5_A_HOST_PWR_SRC	0x1
-#define GL3590_3_0_A_HOST_PWR_SRC	0x2
-
-#define GL3590_I2C_ADDR0 0x50
-
-/* Read GL3590 I2C register */
-int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count);
-
-/* Write to GL3590 I2C register */
-int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count);
-
-/* Initialize GL3590 I2C interface */
-void gl3590_init(int hub);
-
-/* Generic handler for GL3590 IRQ, can be registered/invoked by platform */
-void gl3590_irq_handler(int hub);
-
-/* Get power capabilities of UFP host connection */
-enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr);
-
-#define GL3590_DFP1	BIT(0)
-#define GL3590_DFP2	BIT(1)
-#define GL3590_DFP3	BIT(2)
-#define GL3590_DFP4	BIT(3)
-#define GL3590_DFP5	BIT(4)
-#define GL3590_DFP6	BIT(5)
-#define GL3590_DFP7	BIT(6)
-#define GL3590_DFP8	BIT(7)
-
-/* Enable/disable power to particular downstream facing ports */
-int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable);
-
-/* Generic USB HUB I2C interface */
-struct uhub_i2c_iface_t {
-	int i2c_host_port;
-	int i2c_addr;
-	int initialized;
-};
-extern struct uhub_i2c_iface_t uhub_config[];
diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c
deleted file mode 100644
index 77dd888542..0000000000
--- a/driver/gyro_l3gd20h.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * L3GD20H gyro module for Chrome EC 3D digital gyroscope.
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/gyro_l3gd20h.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-/*
- * Struct for pairing an engineering value with the register value for a
- * parameter.
- */
-struct gyro_param_pair {
-	int val; /* Value in engineering units. */
-	int reg_val; /* Corresponding register value. */
-};
-
-/*
- * List of angular rate range values in +/-dps's
- * and their associated register values.
- */
-const struct gyro_param_pair dps_ranges[] = {
-	{245, L3GD20_DPS_SEL_245},
-	{500, L3GD20_DPS_SEL_500},
-	{2000, L3GD20_DPS_SEL_2000_0},
-	{2000, L3GD20_DPS_SEL_2000_1}
-};
-
-static inline const struct gyro_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
-{
-	if (psize)
-		*psize = ARRAY_SIZE(dps_ranges);
-	return dps_ranges;
-}
-
-/* List of ODR values in mHz and their associated register values. */
-const struct gyro_param_pair gyro_odr[] = {
-	{0,      L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK},
-	{12500,  L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{25000,  L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK},
-	{200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK},
-	{400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK},
-	{800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK},
-};
-
-static inline const struct gyro_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
-{
-	if (psize)
-		*psize = ARRAY_SIZE(gyro_odr);
-	return gyro_odr;
-}
-
-static inline int get_ctrl_reg(enum motionsensor_type type)
-{
-	return L3GD20_CTRL_REG1;
-}
-
-static inline int get_xyz_reg(enum motionsensor_type type)
-{
-	return L3GD20_OUT_X_L | BIT(7);
-}
-
-/**
- * @return reg value that matches the given engineering value passed in.
- * The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid reg value. If the request is
- * outside the range of values, it returns the closest valid reg value.
- */
-static int get_reg_val(const int eng_val, const int round_up,
-		const struct gyro_param_pair *pairs, const int size)
-{
-	int i;
-	for (i = 0; i < size - 1; i++) {
-		if (eng_val <= pairs[i].val)
-			break;
-
-		if (eng_val < pairs[i+1].val) {
-			if (round_up)
-				i += 1;
-			break;
-		}
-	}
-	return pairs[i].reg_val;
-}
-
-/**
- * @return engineering value that matches the given reg val
- */
-static int get_engineering_val(const int reg_val,
-		const struct gyro_param_pair *pairs, const int size)
-{
-	int i;
-	for (i = 0; i < size; i++) {
-		if (reg_val == pairs[i].reg_val)
-			break;
-	}
-	return pairs[i].val;
-}
-
-/**
- * Read register from Gyrometer.
- */
-static inline int raw_read8(const int port, const int addr, const int reg,
-							int *data_ptr)
-{
-	return i2c_read8(port, addr, reg, data_ptr);
-}
-
-/**
- * Write register from Gyrometer.
- */
-static inline int raw_write8(const int port, const int addr, const int reg,
-							 int data)
-{
-	return i2c_write8(port, addr, reg, data);
-}
-
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
-{
-	int ret, ctrl_val, range_tbl_size;
-	uint8_t ctrl_reg, reg_val;
-	const struct gyro_param_pair *ranges;
-
-	ctrl_reg = L3GD20_CTRL_REG4;
-	ranges = get_range_table(s->type, &range_tbl_size);
-
-	reg_val = get_reg_val(range, rnd, ranges, range_tbl_size);
-
-	/*
-	 * Lock Gyro resource to prevent another task from attempting
-	 * to write Gyro parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = raw_read8(s->port, s->addr, ctrl_reg, &ctrl_val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	ctrl_val = (ctrl_val & ~L3GD20_RANGE_MASK) | reg_val;
-	ret = raw_write8(s->port, s->addr, ctrl_reg, ctrl_val);
-
-	/* Now that we have set the range, update the driver's value. */
-	if (ret == EC_SUCCESS)
-		s->current_range = get_engineering_val(reg_val, ranges,
-						       range_tbl_size);
-
-gyro_cleanup:
-	mutex_unlock(s->mutex);
-	return EC_SUCCESS;
-}
-
-static int get_resolution(const struct motion_sensor_t *s)
-{
-	return L3GD20_RESOLUTION;
-}
-
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
-{
-	int ret, val, odr_tbl_size;
-	uint8_t ctrl_reg, reg_val;
-	const struct gyro_param_pair *data_rates;
-	struct l3gd20_data *data = s->drv_data;
-
-	ctrl_reg = get_ctrl_reg(s->type);
-	data_rates = get_odr_table(s->type, &odr_tbl_size);
-	reg_val = get_reg_val(rate, rnd, data_rates, odr_tbl_size);
-
-	/*
-	 * Lock gyro resource to prevent another task from attempting
-	 * to write gyro parameters until we are done.
-	 */
-	mutex_lock(s->mutex);
-
-	ret = raw_read8(s->port, s->addr, ctrl_reg, &val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	val = (val & ~(L3GD20_ODR_MASK | L3GD20_ODR_PD_MASK)) |
-		(reg_val & ~L3GD20_LOW_ODR_MASK);
-	ret = raw_write8(s->port, s->addr, ctrl_reg, val);
-
-	/* Now that we have set the odr, update the driver's value. */
-	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
-
-	ret = raw_read8(s->port, s->addr, L3GD20_LOW_ODR, &val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	/* We need to clear low_ODR bit for higher data rates */
-	if (reg_val & L3GD20_LOW_ODR_MASK)
-		val |= 1;
-	else
-		val &= ~1;
-
-	ret = raw_write8(s->port, s->addr, L3GD20_LOW_ODR, val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	/* CTRL_REG5 24h
-	 * [7] low-power mode = 0;
-	 * [6] fifo disabled = 0;
-	 * [5] Stop on fth = 0;
-	 * [4] High pass filter enable = 1;
-	 * [3:2] int1_sel = 0;
-	 * [1:0] out_sel = 1;
-	 */
-	ret = raw_read8(s->port, s->addr, L3GD20_CTRL_REG5, &val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	val |= BIT(4); /* high-pass filter enabled */
-	val |= BIT(0); /* data in data reg are high-pass filtered */
-	ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG5, val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	ret = raw_read8(s->port, s->addr, L3GD20_CTRL_REG2, &val);
-	if (ret != EC_SUCCESS)
-		goto gyro_cleanup;
-
-	/*
-	 * Table 25. High pass filter mode configuration
-	 * Table 26. High pass filter cut off frequency configuration
-	 */
-	val &= 0xf0;
-	val |= 0x04;
-	ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG2, val);
-
-gyro_cleanup:
-	mutex_unlock(s->mutex);
-	return ret;
-}
-
-static int get_data_rate(const struct motion_sensor_t *s)
-{
-	struct l3gd20_data *data = (struct l3gd20_data *)s->drv_data;
-
-	return data->base.odr;
-}
-
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
-{
-	/* temperature is ignored */
-	struct l3gd20_data *data = s->drv_data;
-	data->offset[X] = offset[X];
-	data->offset[Y] = offset[Y];
-	data->offset[Z] = offset[Z];
-	return EC_SUCCESS;
-}
-
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
-{
-	struct l3gd20_data *data = s->drv_data;
-	offset[X] = data->offset[X];
-	offset[Y] = data->offset[Y];
-	offset[Z] = data->offset[Z];
-	*temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-	return EC_SUCCESS;
-}
-
-static int is_data_ready(const struct motion_sensor_t *s, int *ready)
-{
-	int ret, tmp;
-
-	ret = raw_read8(s->port, s->addr, L3GD20_STATUS_REG, &tmp);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
-		return ret;
-	}
-
-	*ready = (tmp & L3GD20_STS_ZYXDA_MASK) ? 1 : 0;
-
-	return EC_SUCCESS;
-}
-
-static int read(const struct motion_sensor_t *s, intv3_t v)
-{
-	uint8_t raw[6];
-	uint8_t xyz_reg;
-	int ret, range, i, tmp = 0;
-	struct l3gd20_data *data = s->drv_data;
-
-	ret = is_data_ready(s, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/*
-	 * If sensor data is not ready, return the previous read data.
-	 * Note: return success so that motion senor task can read again
-	 * to get the latest updated sensor data quickly.
-	 */
-	if (!tmp) {
-		if (v != s->raw_xyz)
-			memcpy(v, s->raw_xyz, sizeof(s->raw_xyz));
-		return EC_SUCCESS;
-	}
-
-	xyz_reg = get_xyz_reg(s->type);
-
-	/* Read 6 bytes starting at xyz_reg */
-	i2c_block_read(s->port, s->addr, xyz_reg, raw, 6);
-
-	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
-		return ret;
-	}
-
-	for (i = X; i <= Z; i++)
-		v[i] = ((int16_t)((raw[i * 2 + 1] << 8) | raw[i * 2]));
-
-	rotate(v, *s->rot_standard_ref, v);
-
-	/* apply offset in the device coordinates */
-	range = s->current_range;
-	for (i = X; i <= Z; i++)
-		v[i] += (data->offset[i] << 5) / range;
-
-	return EC_SUCCESS;
-}
-
-static int init(struct motion_sensor_t *s)
-{
-	int ret = 0, tmp;
-
-	ret = raw_read8(s->port, s->addr, L3GD20_WHO_AM_I_REG, &tmp);
-	if (ret)
-		return ret;
-
-	if (tmp != L3GD20_WHO_AM_I)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* All axes are enabled */
-	ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG1, 0x0f);
-	if (ret)
-		return ret;
-
-	mutex_lock(s->mutex);
-	ret = raw_read8(s->port, s->addr, L3GD20_CTRL_REG4, &tmp);
-	if (ret) {
-		mutex_unlock(s->mutex);
-		return ret;
-	}
-
-	tmp |= L3GD20_BDU_ENABLE;
-	ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG4, tmp);
-	mutex_unlock(s->mutex);
-	if (ret)
-		return ret;
-
-	return sensor_init_done(s);
-}
-
-const struct accelgyro_drv l3gd20h_drv = {
-	.init = init,
-	.read = read,
-	.set_range = set_range,
-	.get_resolution = get_resolution,
-	.set_data_rate = set_data_rate,
-	.get_data_rate = get_data_rate,
-	.set_offset = set_offset,
-	.get_offset = get_offset,
-};
diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h
deleted file mode 100644
index 7a7ed6b7da..0000000000
--- a/driver/gyro_l3gd20h.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* L3GD20H gyro module for Chrome EC */
-
-#ifndef __CROS_EC_GYRO_L3GD20H_H
-#define __CROS_EC_GYRO_L3GD20H_H
-
-#include "accelgyro.h"
-#include "task.h"
-
-/*
- * 7-bit address is 110101Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define L3GD20_ADDR0_FLAGS       0x6a
-#define L3GD20_ADDR1_FLAGS       0x6b
-
-/* who am I  */
-#define L3GD20_WHO_AM_I          0xd7
-
-/* Chip specific registers. */
-#define L3GD20_WHO_AM_I_REG      0x0f
-#define L3GD20_CTRL_REG1         0x20
-#define L3GD20_CTRL_REG2         0x21
-#define L3GD20_CTRL_REG3         0x22
-#define L3GD20_CTRL_REG4         0x23
-#define L3GD20_CTRL_REG5         0x24
-#define L3GD20_CTRL_REFERENCE    0x25
-#define L3GD20_OUT_TEMP          0x26
-#define L3GD20_STATUS_REG        0x27
-#define L3GD20_OUT_X_L           0x28
-#define L3GD20_OUT_X_H           0x29
-#define L3GD20_OUT_Y_L           0x2a
-#define L3GD20_OUT_Y_H           0x2b
-#define L3GD20_OUT_Z_L           0x2c
-#define L3GD20_OUT_Z_H           0x2d
-#define L3GD20_FIFO_CTRL_REG     0x2e
-#define L3GD20_FIFO_SRC_REG      0x2f
-#define L3GD20_INT1_CFG          0x30
-#define L3GD20_INT1_SRC          0x31
-#define L3GD20_INT1_TSH_XH       0x32
-#define L3GD20_INT1_TSH_XL       0x33
-#define L3GD20_INT1_TSH_YH       0x34
-#define L3GD20_INT1_TSH_YL       0x35
-#define L3GD20_INT1_TSH_ZH       0x36
-#define L3GD20_INT1_TSH_ZL       0x37
-#define L3GD20_INT1_DURATION     0x38
-#define L3GD20_LOW_ODR           0x39
-
-#define L3GD20_DPS_SEL_245       (0 << 4)
-#define L3GD20_DPS_SEL_500       BIT(4)
-#define L3GD20_DPS_SEL_2000_0    (2 << 4)
-#define L3GD20_DPS_SEL_2000_1    (3 << 4)
-
-#define L3GD20_ODR_PD            (0 << 3)
-#define L3GD20_ODR_12_5HZ        (0 << 6)
-#define L3GD20_ODR_25HZ          BIT(6)
-#define L3GD20_ODR_50HZ_0        (2 << 6)
-#define L3GD20_ODR_50HZ_1        (3 << 6)
-#define L3GD20_ODR_100HZ         (0 << 6)
-#define L3GD20_ODR_200HZ         BIT(6)
-#define L3GD20_ODR_400HZ         (2 << 6)
-#define L3GD20_ODR_800HZ         (3 << 6)
-
-#define L3GD20_ODR_MASK          (3 << 6)
-#define L3GD20_STS_ZYXDA_MASK    BIT(3)
-#define L3GD20_RANGE_MASK        (3 << 4)
-#define L3GD20_LOW_ODR_MASK      BIT(0)
-#define L3GD20_ODR_PD_MASK       BIT(3)
-
-/* Min and Max sampling frequency in mHz */
-#define L3GD20_GYRO_MIN_FREQ     12500
-#define L3GD20_GYRO_MAX_FREQ     \
-	MOTION_MAX_SENSOR_FREQUENCY(800000, L3GD20_GYRO_MIN_FREQ)
-
-/*
- * Register      : STATUS_REG
- * Address       : 0X27
- */
-enum l3gd20_status {
-	L3GD20_STS_DOWN          = 0x00,
-	L3GD20_STS_ZYXDA_UP      = 0x08,
-};
-
-/*
- * Register      : CTRL_REG4
- * Address       : 0X23
- * Bit Group Name: BDU
- */
-enum l3gd20_bdu {
-	L3GD20_BDU_DISABLE       = 0x00,
-	L3GD20_BDU_ENABLE        = 0x80,
-};
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define L3GD20_RESOLUTION        16
-
-extern const struct accelgyro_drv l3gd20h_drv;
-struct l3gd20_data {
-	struct accelgyro_saved_data_t base;
-	int16_t offset[3];
-};
-
-#endif /* __CROS_EC_GYRO_L3GD20H_H */
diff --git a/driver/ina2xx.c b/driver/ina2xx.c
deleted file mode 100644
index cf4389ba49..0000000000
--- a/driver/ina2xx.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI INA219/231 Current/Power monitor driver.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "ina2xx.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-
-/* I2C base address */
-#define INA2XX_I2C_ADDR_FLAGS 0x40
-
-uint16_t ina2xx_read(uint8_t idx, uint8_t reg)
-{
-	int res;
-	int val;
-
-	res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			 reg, &val);
-	if (res) {
-		CPRINTS("INA2XX I2C read failed");
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-int ina2xx_write(uint8_t idx, uint8_t reg, uint16_t val)
-{
-	int res;
-	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
-
-	res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			  reg, be_val);
-	if (res)
-		CPRINTS("INA2XX I2C write failed");
-	return res;
-}
-
-int ina2xx_init(uint8_t idx, uint16_t config, uint16_t calib)
-{
-	int res;
-
-	res = ina2xx_write(idx, INA2XX_REG_CONFIG, config);
-	/* TODO(crosbug.com/p/29730): assume 1mA/LSB, revisit later */
-	res |= ina2xx_write(idx, INA2XX_REG_CALIB, calib);
-
-	return res;
-}
-
-int ina2xx_get_voltage(uint8_t idx)
-{
-	uint16_t bv = ina2xx_read(idx, INA2XX_REG_BUS_VOLT);
-	return INA2XX_BUS_MV((int)bv);
-}
-
-int ina2xx_get_current(uint8_t idx)
-{
-	int16_t curr = ina2xx_read(idx, INA2XX_REG_CURRENT);
-	/* Current calibration: LSB = 1mA/bit */
-	return (int)curr;
-}
-
-int ina2xx_get_power(uint8_t idx)
-{
-	uint16_t pow = ina2xx_read(idx, INA2XX_REG_POWER);
-	return INA2XX_POW_MW((int)pow);
-}
-
-int ina2xx_get_mask(uint8_t idx)
-{
-	return ina2xx_read(idx, INA2XX_REG_MASK);
-}
-
-int ina2xx_set_mask(uint8_t idx, uint16_t mask)
-{
-	return ina2xx_write(idx, INA2XX_REG_MASK, mask);
-}
-
-int ina2xx_get_alert(uint8_t idx)
-{
-	return ina2xx_read(idx, INA2XX_REG_ALERT);
-}
-
-int ina2xx_set_alert(uint8_t idx, uint16_t alert)
-{
-	return ina2xx_write(idx, INA2XX_REG_ALERT, alert);
-}
-
-#ifdef CONFIG_CMD_INA
-static void ina2xx_dump(uint8_t idx)
-{
-	uint16_t cfg = ina2xx_read(idx, INA2XX_REG_CONFIG);
-	int16_t sv = ina2xx_read(idx, INA2XX_REG_SHUNT_VOLT);
-	uint16_t bv = ina2xx_read(idx, INA2XX_REG_BUS_VOLT);
-	uint16_t pow = ina2xx_read(idx, INA2XX_REG_POWER);
-	int16_t curr = ina2xx_read(idx, INA2XX_REG_CURRENT);
-	uint16_t calib = ina2xx_read(idx, INA2XX_REG_CALIB);
-	uint16_t mask = ina2xx_read(idx, INA2XX_REG_MASK);
-	uint16_t alert = ina2xx_read(idx, INA2XX_REG_ALERT);
-
-	ccprintf("Configuration: %04x\n", cfg);
-	ccprintf("Shunt voltage: %04x => %d uV\n", sv,
-						   INA2XX_SHUNT_UV((int)sv));
-	ccprintf("Bus voltage  : %04x => %d mV\n", bv,
-						   INA2XX_BUS_MV((int)bv));
-	ccprintf("Power        : %04x => %d mW\n", pow,
-						   INA2XX_POW_MW((int)pow));
-	ccprintf("Current      : %04x => %d mA\n", curr, curr);
-	ccprintf("Calibration  : %04x\n", calib);
-	ccprintf("Mask/Enable  : %04x\n", mask);
-	ccprintf("Alert limit  : %04x\n", alert);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_ina(int argc, char **argv)
-{
-	char *e;
-	int idx;
-	uint16_t val;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	idx = strtoi(argv[1], &e, 10);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	if (2 == argc) { /* dump all registers */
-		ina2xx_dump(idx);
-		return EC_SUCCESS;
-	} else if (4 == argc) {
-		val = strtoi(argv[3], &e, 16);
-		if (*e)
-			return EC_ERROR_PARAM3;
-
-		if (!strcasecmp(argv[2], "config")) {
-			ina2xx_write(idx, INA2XX_REG_CONFIG, val);
-		} else if (!strcasecmp(argv[2], "calib")) {
-			ina2xx_write(idx, INA2XX_REG_CALIB, val);
-		} else if (!strcasecmp(argv[2], "mask")) {
-			ina2xx_write(idx, INA2XX_REG_MASK, val);
-		} else if (!strcasecmp(argv[2], "alert")) {
-			ina2xx_write(idx, INA2XX_REG_ALERT, val);
-		} else { /* read one register */
-			ccprintf("Invalid register: %s\n", argv[1]);
-			return EC_ERROR_INVAL;
-		}
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(ina, command_ina,
-			"<index> [config|calib|mask|alert <val>]",
-			"INA2XX power/current sensing");
-#endif
diff --git a/driver/ina2xx.h b/driver/ina2xx.h
deleted file mode 100644
index ec1e1ed92f..0000000000
--- a/driver/ina2xx.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI INA219/231 Current/Power monitor driver.
- */
-
-#ifndef __CROS_EC_INA2XX_H
-#define __CROS_EC_INA2XX_H
-
-#define INA2XX_REG_CONFIG     0x00
-#define INA2XX_REG_SHUNT_VOLT 0x01
-#define INA2XX_REG_BUS_VOLT   0x02
-#define INA2XX_REG_POWER      0x03
-#define INA2XX_REG_CURRENT    0x04
-#define INA2XX_REG_CALIB      0x05
-#define INA2XX_REG_MASK       0x06
-#define INA2XX_REG_ALERT      0x07
-
-#define INA2XX_CONFIG_MODE_MASK     (7 << 0)
-#define INA2XX_CONFIG_MODE_PWRDWN   (0 << 0)
-#define INA2XX_CONFIG_MODE_SHUNT    BIT(0)
-#define INA2XX_CONFIG_MODE_BUS      BIT(1)
-#define INA2XX_CONFIG_MODE_TRG      (0 << 2)
-#define INA2XX_CONFIG_MODE_CONT     BIT(2)
-
-/* Conversion time for bus and shunt in micro-seconds */
-enum ina2xx_conv_time {
-	INA2XX_CONV_TIME_140  = 0x00,
-	INA2XX_CONV_TIME_204  = 0x01,
-	INA2XX_CONV_TIME_332  = 0x02,
-	INA2XX_CONV_TIME_588  = 0x03,
-	INA2XX_CONV_TIME_1100 = 0x04,
-	INA2XX_CONV_TIME_2116 = 0x05,
-	INA2XX_CONV_TIME_4156 = 0x06,
-	INA2XX_CONV_TIME_8244 = 0x07,
-};
-#define INA2XX_CONV_TIME_MASK 0x7
-#define INA2XX_CONFIG_SHUNT_CONV_TIME(t) ((t) << 3)
-#define INA2XX_CONFIG_BUS_CONV_TIME(t)   ((t) << 6)
-
-#define INA2XX_CONFIG_AVG_1        (0 << 9)
-#define INA2XX_CONFIG_AVG_4        BIT(9)
-#define INA2XX_CONFIG_AVG_16       (2 << 9)
-#define INA2XX_CONFIG_AVG_64       (3 << 9)
-#define INA2XX_CONFIG_AVG_128      (4 << 9)
-#define INA2XX_CONFIG_AVG_256      (5 << 9)
-#define INA2XX_CONFIG_AVG_512      (6 << 9)
-#define INA2XX_CONFIG_AVG_1024     (7 << 9)
-
-#define INA2XX_MASK_EN_LEN         BIT(0)
-#define INA2XX_MASK_EN_APOL        BIT(1)
-#define INA2XX_MASK_EN_OVF         BIT(2)
-#define INA2XX_MASK_EN_CVRF        BIT(3)
-#define INA2XX_MASK_EN_AFF         BIT(4)
-#define INA2XX_MASK_EN_CNVR        BIT(10)
-#define INA2XX_MASK_EN_POL         BIT(11)
-#define INA2XX_MASK_EN_BUL         BIT(12)
-#define INA2XX_MASK_EN_BOL         BIT(13)
-#define INA2XX_MASK_EN_SUL         BIT(14)
-#define INA2XX_MASK_EN_SOL        BIT(15)
-
-
-#if defined(CONFIG_INA231) && defined(CONFIG_INA219)
-#error CONFIG_INA231 and CONFIG_INA219 must not be both defined.
-#endif
-
-#ifdef CONFIG_INA231
-
-/* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (5120/(rsense_mohm))
-/* Bus voltage: mV per LSB */
-#define INA2XX_BUS_MV(reg) ((reg) * 125 / 100)
-/* Shunt voltage: uV per LSB */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 25 / 10)
-/* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 25 * 1/*Current mA/LSB*/)
-
-#else /* CONFIG_INA219 */
-
-/* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (40960/(rsense_mohm))
-/* Bus voltage: mV per LSB */
-#define INA2XX_BUS_MV(reg) ((reg) / 2)
-/* Shunt voltage: uV */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 10)
-/* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 20 * 1/*Current mA/LSB*/)
-
-#endif
-
-
-/* Read INA2XX register. */
-uint16_t ina2xx_read(uint8_t idx, uint8_t reg);
-
-/* Write INA2XX register. */
-int ina2xx_write(uint8_t idx, uint8_t reg, uint16_t val);
-
-/* Set measurement parameters */
-int ina2xx_init(uint8_t idx, uint16_t config, uint16_t calib);
-
-/* Return bus voltage in milliVolts */
-int ina2xx_get_voltage(uint8_t idx);
-
-/* Return current in milliAmps */
-int ina2xx_get_current(uint8_t idx);
-
-/* Return power in milliWatts */
-int ina2xx_get_power(uint8_t idx);
-
-/* Return content of mask register */
-int ina2xx_get_mask(uint8_t idx);
-
-/* Set mask register to desired value */
-int ina2xx_set_mask(uint8_t idx, uint16_t mask);
-
-/* Return alert register value */
-int ina2xx_get_alert(uint8_t idx);
-
-/* Set alert register to desired value */
-int ina2xx_set_alert(uint8_t idx, uint16_t alert);
-
-#endif /* __CROS_EC_INA2XX_H */
diff --git a/driver/ina3221.c b/driver/ina3221.c
deleted file mode 100644
index 5b89f9694e..0000000000
--- a/driver/ina3221.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI INA3221 Power monitor driver.
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "ina3221.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-const static uint8_t ina3221_reg_map[INA3221_CHAN_COUNT][INA3221_MAX_REG] = {
-{ 1, 2,  7,  8 }, /* Chan 1 */
-{ 3, 4,  9, 10 }, /* Chan 2 */
-{ 5, 6, 11, 12 }  /* Chan 3 */
-};
-
-static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
-{
-	int res;
-	int val;
-
-	res = i2c_read16(ina3221[unit].port, ina3221[unit].address,
-			 reg, &val);
-	if (res) {
-		CPRINTS("INA3221 I2C read failed");
-		return 0x0bad;
-	}
-	return (val >> 8) | ((val & 0xff) << 8);
-}
-
-static uint16_t ina3221_chan_read(unsigned int unit, enum ina3221_channel chan,
-			   enum ina3221_register reg)
-{
-	if (chan >= INA3221_CHAN_COUNT || reg >= INA3221_MAX_REG) {
-		CPRINTS("INA3221 Bad channel or register value");
-		return 0x0bad;
-	}
-	return ina3221_read(unit, ina3221_reg_map[chan][reg]);
-}
-
-static int ina3221_write(unsigned int unit, uint8_t reg, uint16_t val)
-{
-	int res;
-	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
-
-	res = i2c_write16(ina3221[unit].port, ina3221[unit].address,
-			  reg, be_val);
-	if (res)
-		CPRINTS("INA3221 I2C write failed");
-	return res;
-}
-
-static void ina3221_init(void)
-{
-	unsigned int unit;
-
-	for (unit = 0; unit < ina3221_count; unit++) {
-		uint16_t conf = INA3221_CONFIG_BASE;
-		int chan;
-
-		for (chan = 0; chan < INA3221_CHAN_COUNT; chan++) {
-			/* Only initialise if channel is used */
-			if (ina3221[unit].name[chan] != NULL)
-				conf |= 0x4000 >> chan;
-		}
-		ina3221_write(unit, INA3221_REG_CONFIG, conf);
-	}
-}
-
-DECLARE_HOOK(HOOK_INIT, ina3221_init, HOOK_PRIO_INIT_EXTPOWER + 1);
-
-#ifdef CONFIG_CMD_INA
-static void ina3221_dump(unsigned int unit)
-{
-	uint16_t cfg;
-	int16_t sv[INA3221_CHAN_COUNT];
-	uint16_t bv[INA3221_CHAN_COUNT];
-	uint16_t crit[INA3221_CHAN_COUNT];
-	uint16_t warn[INA3221_CHAN_COUNT];
-	uint16_t mask;
-	int chan;
-
-	cfg = ina3221_read(unit, INA3221_REG_CONFIG);
-	for (chan = 0; chan < INA3221_CHAN_COUNT; chan++) {
-		if (ina3221[unit].name[chan] != NULL) {
-			sv[chan] = ina3221_chan_read(unit, chan,
-						     INA3221_SHUNT_VOLT);
-			bv[chan] = ina3221_chan_read(unit, chan,
-						     INA3221_BUS_VOLT);
-			crit[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_CRITICAL);
-			warn[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_WARNING);
-		}
-	}
-	mask = ina3221_read(unit, INA3221_REG_MASK);
-
-	ccprintf("Unit %d, address: %04x\n", unit, ina3221[unit].address);
-	ccprintf("Configuration   : %04x\n", cfg);
-	for (chan = 0; chan < INA3221_CHAN_COUNT; chan++) {
-		if (ina3221[unit].name[chan] != NULL) {
-			ccprintf("%d: %s:\n", chan, ina3221[unit].name[chan]);
-			ccprintf("      Shunt voltage: %04x => %d uV\n",
-				sv[chan], INA3221_SHUNT_UV((int)sv[chan]));
-			ccprintf("      Bus voltage  : %04x => %d mV\n",
-				bv[chan], INA3221_BUS_MV((int)bv[chan]));
-			ccprintf("      Warning      : %04x\n", warn[chan]);
-			ccprintf("      Critical     : %04x\n", crit[chan]);
-		}
-	}
-	ccprintf("Mask/Enable  : %04x\n", mask);
-}
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_ina(int argc, char **argv)
-{
-	char *e;
-	unsigned int unit;
-	uint16_t val;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	unit = strtoi(argv[1], &e, 10);
-	if (*e || unit >= ina3221_count)
-		return EC_ERROR_PARAM1;
-
-	if (argc == 2) { /* dump all registers */
-		ina3221_dump(unit);
-		return EC_SUCCESS;
-	} else if (argc == 4) {
-		val = strtoi(argv[3], &e, 16);
-		if (*e)
-			return EC_ERROR_PARAM3;
-
-		if (!strcasecmp(argv[2], "config")) {
-			ina3221_write(unit, INA3221_REG_CONFIG, val);
-		} else if (!strcasecmp(argv[2], "mask")) {
-			ina3221_write(unit, INA3221_REG_MASK, val);
-		} else {
-			ccprintf("Invalid register: %s\n", argv[1]);
-			return EC_ERROR_INVAL;
-		}
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(ina, command_ina,
-			"<index> [config|mask <val>]",
-			"INA3221 voltage sensing");
-#endif
diff --git a/driver/ina3221.h b/driver/ina3221.h
deleted file mode 100644
index 4d8c8211b4..0000000000
--- a/driver/ina3221.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI INA3221 Current/Power monitor driver.
- */
-
-#ifndef __CROS_EC_INA3221_H
-#define __CROS_EC_INA3221_H
-
-#define INA3221_REG_CONFIG	0x00
-#define INA3221_REG_MASK	0x0F
-
-/*
- * Common bits are:
- * Reset
- * average = 1
- * conversion time = 1.1 ms
- * mode = shunt and bus, continuous.
- */
-#define INA3221_CONFIG_BASE	0x8127
-
-/* Bus voltage: lower 3 bits clear, LSB = 8 mV */
-#define INA3221_BUS_MV(reg) (reg)
-/* Shunt voltage: lower 3 bits clear, LSB = 40 uV */
-#define INA3221_SHUNT_UV(reg) ((reg) * (40/8))
-
-enum ina3221_channel {
-	INA3221_CHAN_1 = 0,
-	INA3221_CHAN_2 = 1,
-	INA3221_CHAN_3 = 2,
-	INA3221_CHAN_COUNT = 3
-};
-
-/* Registers for each channel */
-enum ina3221_register {
-	INA3221_SHUNT_VOLT = 0,
-	INA3221_BUS_VOLT = 1,
-	INA3221_CRITICAL = 2,
-	INA3221_WARNING = 3,
-	INA3221_MAX_REG = 4
-};
-
-/* Configuration table - defined in board file. */
-struct ina3221_t {
-	int port;             /* I2C port index */
-	uint8_t address;      /* I2C address */
-	const char *name[INA3221_CHAN_COUNT];  /* Channel names */
-};
-
-/* External config in board file */
-extern const struct ina3221_t ina3221[];
-extern const unsigned int ina3221_count;
-
-#endif /* __CROS_EC_INA3221_H */
diff --git a/driver/ioexpander/ccgxxf.c b/driver/ioexpander/ccgxxf.c
deleted file mode 100644
index ac079d7b2f..0000000000
--- a/driver/ioexpander/ccgxxf.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cypress CCGXXF I/O Port expander (built inside PD chip) driver source
- */
-
-#include "console.h"
-#include "i2c.h"
-#include "ioexpander.h"
-
-/* Add after all include files */
-#include "ccgxxf.h"
-
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-static inline int ccgxxf_read8(int ioex, int reg, int *data)
-{
-	return i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
-}
-
-static inline int ccgxxf_update8(int ioex, int reg, uint8_t mask,
-				enum mask_update_action action)
-{
-	return i2c_update8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, mask, action);
-}
-
-static inline int ccgxxf_write16(int ioex, uint16_t reg, uint16_t data)
-{
-	return i2c_write16(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
-}
-
-static int ccgxxf_get_level(int ioex, int port, int mask, int *val)
-{
-	int rv;
-
-	rv = ccgxxf_read8(ioex, CCGXXF_REG_GPIO_STATUS(port), val);
-	if (!rv)
-		*val = !!(*val & mask);
-
-	return rv;
-}
-
-static int ccgxxf_set_level(int ioex, int port, int mask, int val)
-{
-	return ccgxxf_update8(ioex, CCGXXF_REG_GPIO_CONTROL(port), mask, val);
-}
-
-/*
- * Following type of pins are supported
- * - Output pins are supported with open-drain & pull-up
- * - Input pins are supported with pull-up & pull-down
- * - Analog pins
- * - 1.8V level GPIOs are supported per port and outputs can only be
- *   open-drain pins
- */
-static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
-{
-	uint16_t pin_mode;
-	int rv;
-
-	/* Push-pull output can't be configured for 1.8V level */
-	if ((flags & GPIO_OUTPUT) && (flags & GPIO_SEL_1P8V) &&
-		!(flags & GPIO_OPEN_DRAIN)) {
-		CPRINTS("Invalid flags: ioex=%d, port=%d, mask=%d, flags=0x%x",
-				ioex, port, mask, flags);
-
-		return EC_ERROR_INVAL;
-	}
-
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_OPEN_DRAIN) {
-			if (flags & GPIO_PULL_UP)
-				pin_mode = CCGXXF_GPIO_MODE_RES_UP;
-			else
-				pin_mode = CCGXXF_GPIO_MODE_OD_LOW;
-		} else {
-			pin_mode = CCGXXF_GPIO_MODE_STRONG;
-		}
-	} else if (flags & GPIO_INPUT) {
-		if (flags & GPIO_PULL_UP) {
-			pin_mode = CCGXXF_GPIO_MODE_RES_UP;
-			flags |= GPIO_HIGH;
-		} else if (flags & GPIO_PULL_DOWN) {
-			pin_mode = CCGXXF_GPIO_MODE_RES_DWN;
-			flags |= GPIO_LOW;
-		} else {
-			pin_mode = CCGXXF_GPIO_MODE_HIZ_DIGITAL;
-		}
-	} else if (flags & GPIO_ANALOG) {
-		pin_mode = CCGXXF_GPIO_MODE_HIZ_ANALOG;
-	} else {
-		return EC_ERROR_INVAL;
-	}
-
-	pin_mode = port | (pin_mode << CCGXXF_GPIO_PIN_MODE_SHIFT) |
-			(mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
-
-	/* Note: once set the 1.8V level affect whole GPIO port */
-	if (flags & GPIO_SEL_1P8V)
-		pin_mode |= CCGXXF_GPIO_1P8V_SEL;
-
-	/*
-	 * Before setting the GPIO mode, initilaize the pins to default value
-	 * to avoid spike on pins.
-	 */
-	if (flags & (GPIO_HIGH | GPIO_LOW)) {
-		rv = ccgxxf_set_level(ioex, port, mask,
-					flags & GPIO_HIGH ? 1 : 0);
-		if (rv)
-			return rv;
-	}
-
-	return	ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
-}
-
-static int ccgxxf_get_flags_by_mask(int ioex, int port, int mask, int *flags)
-{
-	 /* TODO: Add it after implementing in the CCGXXF firmware. */
-	return EC_SUCCESS;
-}
-
-static int ccgxxf_enable_interrupt(int ioex, int port, int mask, int enable)
-{
-	/* CCGXXF doesn't have interrupt capability on I/O expnader pins */
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int ccgxxf_init(int ioex)
-{
-	/* TCPC init of CCGXXF should handle initialization */
-	return EC_SUCCESS;
-}
-
-const struct ioexpander_drv ccgxxf_ioexpander_drv = {
-	.init			= &ccgxxf_init,
-	.get_level		= &ccgxxf_get_level,
-	.set_level		= &ccgxxf_set_level,
-	.get_flags_by_mask	= &ccgxxf_get_flags_by_mask,
-	.set_flags_by_mask	= &ccgxxf_set_flags_by_mask,
-	.enable_interrupt	= &ccgxxf_enable_interrupt,
-};
diff --git a/driver/ioexpander/ioexpander_nct38xx.c b/driver/ioexpander/ioexpander_nct38xx.c
deleted file mode 100644
index 8c87a33d24..0000000000
--- a/driver/ioexpander/ioexpander_nct38xx.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPIO expander for Nuvoton NCT38XX. */
-
-#include "console.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "nct38xx.h"
-#include "tcpm/tcpci.h"
-
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Store the GPIO_ALERT_MASK_0/1 and chip ID registers locally. In this way,
- * we don't have to read it via I2C transaction everytime.
- */
-struct nct38xx_chip_data {
-	uint8_t int_mask[2];
-	int chip_id;
-};
-
-static struct nct38xx_chip_data chip_data[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	 [0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  { {0, 0}, -1 }
-};
-
-static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask)
-{
-	if (chip_data[ioex].chip_id == NCT38XX_VARIANT_3808) {
-		if (port == 1) {
-			CPRINTF("Port 1 is not support in NCT3808\n");
-			return EC_ERROR_INVAL;
-		}
-		if (mask & ~NCT38XXX_3808_VALID_GPIO_MASK) {
-
-			CPRINTF("GPIO%02d is not support in NCT3808\n",
-							__fls(mask));
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int nct38xx_ioex_init(int ioex)
-{
-	int rv, val;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	/*
-	 * Check the NCT38xx part number in the register DEVICE_ID[4:2]:
-	 *  000: NCT3807
-	 *  010: NCT3808
-	 */
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			TCPC_REG_BCD_DEV, &val);
-
-	if (rv != EC_SUCCESS) {
-		CPRINTF("Failed to read NCT38XX DEV ID for IOexpander %d\n",
-					ioex);
-		return rv;
-	}
-
-	chip_data[ioex].chip_id = ((uint8_t)val & NCT38XX_VARIANT_MASK) >> 2;
-
-	/*
-	 * NCT38XX uses the Vendor Define bit in the ALERT event to indicate
-	 * that an IOEX IO's interrupt is triggered.
-	 * Normally, The ALERT MASK for Vendor Define event should be set by
-	 * the NCT38XX TCPCI driver's init function.
-	 * However, it should be also set here if we want to test the interrupt
-	 * function of IOEX when the NCT38XX TCPCI driver is not included.
-	 */
-	if (!IS_ENABLED(CONFIG_USB_PD_TCPM_NCT38XX)) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_addr_flags, TCPC_REG_ALERT_MASK,
-				TCPC_REG_ALERT_VENDOR_DEF);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-	return EC_SUCCESS;
-}
-
-static int nct38xx_ioex_get_level(int ioex, int port, int mask, int *val)
-{
-	int rv, reg;
-
-	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg = NCT38XX_REG_GPIO_DATA_IN(port);
-	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	*val = !!(*val & mask);
-
-	return EC_SUCCESS;
-}
-
-static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value)
-{
-	int rv, reg, val;
-
-	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg = NCT38XX_REG_GPIO_DATA_OUT(port);
-
-	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (value)
-		val |= mask;
-	else
-		val &= ~mask;
-
-	return i2c_write8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, val);
-}
-
-static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
-{
-	int rv, reg, val, i2c_port, i2c_addr;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	i2c_port = ioex_p->i2c_host_port;
-	i2c_addr = ioex_p->i2c_addr_flags;
-
-	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg = NCT38XX_REG_GPIO_DIR(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask)
-		*flags |= GPIO_OUTPUT;
-	else
-		*flags |= GPIO_INPUT;
-
-	reg = NCT38XX_REG_GPIO_DATA_IN(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask)
-		*flags |= GPIO_HIGH;
-	else
-		*flags |= GPIO_LOW;
-
-	reg = NCT38XX_REG_GPIO_OD_SEL(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask)
-		*flags |= GPIO_OPEN_DRAIN;
-
-	return EC_SUCCESS;
-}
-
-static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
-					int mask, int flags)
-{
-	int rv;
-	int reg_rising, reg_falling;
-	int rising, falling;
-
-	reg_rising = NCT38XX_REG_GPIO_ALERT_RISE(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg_rising, &rising);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg_falling = NCT38XX_REG_GPIO_ALERT_FALL(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg_falling, &falling);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Handle interrupt for level trigger */
-	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) {
-		int reg_level, level;
-
-		reg_level = NCT38XX_REG_GPIO_ALERT_LEVEL(port);
-		rv = i2c_read8(i2c_port, i2c_addr, reg_level, &level);
-		if (rv != EC_SUCCESS)
-			return rv;
-		/*
-		 * For "level" triggered interrupt, the related bit in
-		 * ALERT_RISE and ALERT_FALL registers must be 0
-		 */
-		rising &= ~mask;
-		falling &= ~mask;
-		if (flags & GPIO_INT_F_HIGH)
-			level |= mask;
-		else
-			level &= ~mask;
-
-		rv = i2c_write8(i2c_port, i2c_addr, reg_rising, rising);
-		if (rv != EC_SUCCESS)
-			return rv;
-		rv = i2c_write8(i2c_port, i2c_addr, reg_falling, falling);
-		if (rv != EC_SUCCESS)
-			return rv;
-		rv = i2c_write8(i2c_port, i2c_addr, reg_level, level);
-		if (rv != EC_SUCCESS)
-			return rv;
-	} else if ((flags & GPIO_INT_F_RISING) ||
-				(flags & GPIO_INT_F_FALLING)) {
-		if (flags & GPIO_INT_F_RISING)
-			rising |= mask;
-		else
-			rising &= ~mask;
-		if (flags & GPIO_INT_F_FALLING)
-			falling |= mask;
-		else
-			falling &= ~mask;
-		rv = i2c_write8(i2c_port, i2c_addr, reg_rising, rising);
-		if (rv != EC_SUCCESS)
-			return rv;
-		rv = i2c_write8(i2c_port, i2c_addr, reg_falling, falling);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-	return EC_SUCCESS;
-}
-
-static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
-{
-	int rv, reg, val, i2c_port, i2c_addr;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	i2c_port = ioex_p->i2c_host_port;
-	i2c_addr = ioex_p->i2c_addr_flags;
-
-	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/*
-	 * GPIO port 0 muxs with alternative function. Disable the alternative
-	 * function before setting flags.
-	 */
-	if (port == 0) {
-		/* GPIO03 in NCT3807 is not muxed with other function. */
-		if (!(chip_data[ioex].chip_id ==
-					NCT38XX_VARIANT_3807 && mask & 0x08)) {
-			reg = NCT38XX_REG_MUX_CONTROL;
-			rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-			if (rv != EC_SUCCESS)
-				return rv;
-
-			val = (val | mask);
-			rv = i2c_write8(i2c_port, i2c_addr, reg, val);
-			if (rv != EC_SUCCESS)
-				return rv;
-		}
-	}
-
-	val = flags & ~NCT38XX_SUPPORT_GPIO_FLAGS;
-	if (val) {
-		CPRINTF("Flag 0x%08x is not supported\n", val);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Select open drain 0:push-pull 1:open-drain */
-	reg = NCT38XX_REG_GPIO_OD_SEL(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= mask;
-	else
-		val &= ~mask;
-	rv = i2c_write8(i2c_port, i2c_addr, reg, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	nct38xx_ioex_sel_int_type(i2c_port, i2c_addr, port, mask, flags);
-
-	/* Configure the output level */
-	reg = NCT38XX_REG_GPIO_DATA_OUT(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (flags & GPIO_HIGH)
-		val |= mask;
-	else if (flags & GPIO_LOW)
-		val &= ~mask;
-	rv = i2c_write8(i2c_port, i2c_addr, reg, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg = NCT38XX_REG_GPIO_DIR(port);
-	rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (flags & GPIO_OUTPUT)
-		val |= mask;
-	else
-		val &= ~mask;
-
-	return  i2c_write8(i2c_port, i2c_addr, reg, val);
-}
-
-/*
- * The following functions are used for IO's interrupt support.
- *
- * please note that if the system needs to use an IO on NCT38XX to support
- * the interrupt, the following two consideration should be taken into account.
- * 1. Interrupt latency:
- *    Because it requires to access the registers of NCT38XX via I2C
- *    transaction to know the interrupt event, there is some added latency
- *    for the interrupt handling. If the interrupt requires short latency,
- *    we do not recommend to connect such a signal to the NCT38XX.
- *
- * 2. Shared ALERT pin:
- *    Because the ALERT pin is shared also with the TCPC ALERT, we do not
- *    recommend to connect any signal that may generate a high rate of
- *    interrupts so it will not interfere with the normal work of the
- *    TCPC.
- */
-static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
-{
-	int rv, reg, val;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	rv = nct38xx_ioex_check_is_valid(ioex, port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Clear the pending bit */
-	reg = NCT38XX_REG_GPIO_ALERT_STAT(port);
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	val |= mask;
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg = NCT38XX_REG_GPIO_ALERT_MASK(port);
-	if (enable) {
-		/* Enable the alert mask */
-		chip_data[ioex].int_mask[port] |= mask;
-		val = chip_data[ioex].int_mask[port];
-	} else {
-		/* Disable the alert mask */
-		chip_data[ioex].int_mask[port] &= ~mask;
-		val = chip_data[ioex].int_mask[port];
-	}
-
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, val);
-}
-
-int nct38xx_ioex_event_handler(int ioex)
-{
-	int reg, int_status, int_mask;
-	int i, j, total_port;
-	const struct ioex_info *g;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	int rv = 0;
-
-	int_mask = chip_data[ioex].int_mask[0] | (
-				chip_data[ioex].int_mask[1] << 8);
-	reg = NCT38XX_REG_GPIO_ALERT_STAT(0);
-	/*
-	 * Read ALERT_STAT_0 and ALERT_STAT_1 register in a single I2C
-	 * transaction to increase efficiency
-	 */
-	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, &int_status);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	int_status = int_status & int_mask;
-	/*
-	 * Clear the changed status bits in ALERT_STAT_0 and ALERT_STAT_1
-	 * register in a single I2C transaction to increase efficiency
-	 */
-	rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, int_status);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* For NCT3808, only check one port */
-	total_port = (chip_data[ioex].chip_id == NCT38XX_VARIANT_3808) ?
-		NCT38XX_NCT3808_MAX_IO_PORT :
-		NCT38XX_NCT3807_MAX_IO_PORT;
-	for (i = 0; i < total_port; i++) {
-		uint8_t pending;
-
-		pending = int_status >> (i * 8);
-
-		if (!pending)
-			continue;
-
-		for (j = 0, g = ioex_list; j < ioex_ih_count; j++, g++) {
-
-			if (ioex == g->ioex && i == g->port &&
-						(pending & g->mask)) {
-				ioex_irq_handlers[j](j + IOEX_SIGNAL_START);
-				pending &= ~g->mask;
-				if (!pending)
-					break;
-			}
-
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Normally, the ALERT MASK for Vendor Define event should be checked by
- * the NCT38XX TCPCI driver's tcpc_alert function.
- * However, it should be checked here if we want to test the interrupt
- * function of IOEX when the NCT38XX TCPCI driver is not included.
- */
-void nct38xx_ioex_handle_alert(int ioex)
-{
-	int rv, status;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			TCPC_REG_ALERT, &status);
-	if (rv != EC_SUCCESS)
-		CPRINTF("fail to read ALERT register\n");
-
-	if (status & TCPC_REG_ALERT_VENDOR_DEF) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_addr_flags, TCPC_REG_ALERT,
-				TCPC_REG_ALERT_VENDOR_DEF);
-		if (rv != EC_SUCCESS) {
-			CPRINTF("Fail to clear Vendor Define mask\n");
-			return;
-		}
-		nct38xx_ioex_event_handler(ioex);
-	}
-}
-
-const struct ioexpander_drv nct38xx_ioexpander_drv = {
-	.init              = &nct38xx_ioex_init,
-	.get_level         = &nct38xx_ioex_get_level,
-	.set_level         = &nct38xx_ioex_set_level,
-	.get_flags_by_mask = &nct38xx_ioex_get_flags,
-	.set_flags_by_mask = &nct38xx_ioex_set_flags_by_mask,
-	.enable_interrupt  = &nct38xx_ioex_enable_interrupt,
-};
diff --git a/driver/ioexpander/it8300.h b/driver/ioexpander/it8300.h
deleted file mode 100644
index 2b47e7f3e1..0000000000
--- a/driver/ioexpander/it8300.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ITE IT8300 I/O Port expander driver header
- */
-
-#ifndef __CROS_EC_IOEXPANDER_IT8300_H
-#define __CROS_EC_IOEXPANDER_IT8300_H
-
-#include "i2c.h"
-
-/* Gather Interrupt Status Register */
-#define IT8300_GISR		0x0
-
-/* Interrupt Status Registers */
-#define IT8300_ISR_A		0x6
-#define IT8300_ISR_B		0x7
-#define IT8300_ISR_C		0x28
-#define IT8300_ISR_D		0x2E
-#define IT8300_ISR_E		0x2F
-
-/* Port Data Register Groups */
-#define IT8300_PDGR_A		0x1
-#define IT8300_PDGR_B		0x2
-#define IT8300_PDGR_C		0x3
-#define IT8300_PDGR_D		0x4
-#define IT8300_PDGR_E		0x5
-
-/* GPIO Port Control n Registers */
-#define IT8300_GPCR_A0		0x10
-#define IT8300_GPCR_A1		0x11
-#define IT8300_GPCR_A2		0x12
-#define IT8300_GPCR_A3		0x13
-#define IT8300_GPCR_A4		0x14
-#define IT8300_GPCR_A5		0x15
-#define IT8300_GPCR_A6		0x16
-#define IT8300_GPCR_A7		0x17
-
-#define IT8300_GPCR_B0		0x18
-#define IT8300_GPCR_B1		0x19
-#define IT8300_GPCR_B2		0x1A
-#define IT8300_GPCR_B3		0x1B
-#define IT8300_GPCR_B4		0x1C
-#define IT8300_GPCR_B5		0x1D
-#define IT8300_GPCR_B6		0x1E
-
-#define IT8300_GPCR_C0		0x20
-#define IT8300_GPCR_C1		0x21
-#define IT8300_GPCR_C2		0x22
-#define IT8300_GPCR_C3		0x23
-#define IT8300_GPCR_C4		0x24
-#define IT8300_GPCR_C5		0x25
-#define IT8300_GPCR_C6		0x26
-
-#define IT8300_GPCR_D0		0x08
-#define IT8300_GPCR_D1		0x09
-#define IT8300_GPCR_D2		0x0A
-#define IT8300_GPCR_D3		0x0B
-#define IT8300_GPCR_D4		0x0C
-#define IT8300_GPCR_D5		0x0D
-
-#define IT8300_GPCR_E0		0x32
-
-#define IT8300_GPCR_E2		0x34
-#define IT8300_GPCR_E3		0x35
-#define IT8300_GPCR_E4		0x36
-#define IT8300_GPCR_E5		0x37
-#define IT8300_GPCR_E6		0x38
-
-#define IT8300_GPCR_GPI_MODE	BIT(7)
-#define IT8300_GPCR_GP0_MODE	BIT(6)
-#define IT8300_GPCR_PULL_UP_EN	BIT(2)
-#define IT8300_GPCR_PULL_DN_EN	BIT(1)
-
-/* EXGPIO Clear Alert */
-#define IT8300_ECA		0x30
-
-/* EXGPIO Alert Enable */
-#define IT8300_EAE		0x31
-
-/* Port Data Mirror Registers */
-#define IT8300_PDMRA_A		0x29
-#define IT8300_PDMRA_B		0x2A
-#define IT8300_PDMRA_C		0x2B
-#define IT8300_PDMRA_D		0x2C
-#define IT8300_PDMRA_E		0x2D
-
-/* Output Open-Drain Enable Registers */
-#define IT8300_OODER_A		0x39
-#define IT8300_OODER_B		0x3A
-#define IT8300_OODER_C		0x3B
-#define IT8300_OODER_D		0x3C
-#define IT8300_OODER_E		0x3D
-
-/* IT83200 Port GPIOs */
-#define IT8300_GPX_0		BIT(0)
-#define IT8300_GPX_1		BIT(1)
-#define IT8300_GPX_2		BIT(2)
-#define IT8300_GPX_3		BIT(3)
-#define IT8300_GPX_4		BIT(4)
-#define IT8300_GPX_5		BIT(5)
-#define IT8300_GPX_6		BIT(6)
-#define IT8300_GPX_7		BIT(7)
-
-#endif /* __CROS_EC_IOEXPANDER_IT8300_H */
diff --git a/driver/ioexpander/it8801.c b/driver/ioexpander/it8801.c
deleted file mode 100644
index 96070074fb..0000000000
--- a/driver/ioexpander/it8801.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "it8801.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "keyboard_backlight.h"
-
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
-
-static int it8801_ioex_set_level(int ioex, int port, int mask, int value);
-static void it8801_ioex_event_handler(void);
-DECLARE_DEFERRED(it8801_ioex_event_handler);
-
-static int it8801_read(int reg, int *data)
-{
-	return i2c_read8(IT8801_KEYBOARD_PWM_I2C_PORT,
-		IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS, reg, data);
-}
-
-__maybe_unused static int it8801_write(int reg, int data)
-{
-	return i2c_write8(IT8801_KEYBOARD_PWM_I2C_PORT,
-		IT8801_KEYBOARD_PWM_I2C_ADDR_FLAGS, reg, data);
-}
-
-struct it8801_vendor_id_t {
-	uint8_t chip_id;
-	uint8_t reg;
-};
-
-static const struct it8801_vendor_id_t it8801_vendor_id_verify[] = {
-	{ 0x12, IT8801_REG_HBVIDR},
-	{ 0x83, IT8801_REG_LBVIDR},
-};
-
-static int it8801_check_vendor_id(void)
-{
-	int i, ret, val;
-
-	/*  Verify vendor ID registers(16-bits). */
-	for (i = 0; i < ARRAY_SIZE(it8801_vendor_id_verify); i++) {
-		ret = it8801_read(it8801_vendor_id_verify[i].reg, &val);
-
-		if (ret != EC_SUCCESS)
-			return ret;
-
-		if (val != it8801_vendor_id_verify[i].chip_id)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Keyboard and GPIO interrupts are muxed inside the IT8801 chip.
- * Interrupt enable register controls the individual pins from
- * triggering this global interrupt hence it is okay that this
- * pin is enabled all the time.
- */
-static void it8801_muxed_kbd_gpio_intr_enable(void)
-{
-	static bool intr_enabled;
-
-	/*
-	 * Allow enabling this pin either by Keyboard enable code or
-	 * IOEX init code whichever gets called first.
-	 */
-	if (!intr_enabled) {
-		gpio_clear_pending_interrupt(GPIO_IT8801_SMB_INT);
-		gpio_enable_interrupt(GPIO_IT8801_SMB_INT);
-		intr_enabled = true;
-	}
-}
-
-#ifdef CONFIG_KEYBOARD_NOT_RAW
-void keyboard_raw_init(void)
-{
-	int ret;
-
-	/*  Verify Vendor ID registers. */
-	ret = it8801_check_vendor_id();
-	if (ret) {
-		CPRINTS("Failed to read IT8801 vendor id %x", ret);
-		return;
-	}
-
-	/* KSO alternate function switching(KSO[21:20, 18]). */
-	it8801_write(IT8801_REG_GPIO01_KSO18, IT8801_REG_MASK_GPIOAFS_FUNC2);
-	it8801_write(IT8801_REG_GPIO22_KSO21, IT8801_REG_MASK_GPIOAFS_FUNC2);
-	it8801_write(IT8801_REG_GPIO23_KSO20, IT8801_REG_MASK_GPIOAFS_FUNC2);
-
-	/* Start with KEYBOARD_COLUMN_ALL, KSO[22:11, 6:0] output low. */
-	it8801_write(IT8801_REG_KSOMCR, IT8801_REG_MASK_AKSOSC);
-
-	if (IS_ENABLED(CONFIG_KEYBOARD_COL2_INVERTED)) {
-		/*
-		 * Since most of the KSO pins can't drive up, we'll must use
-		 * a pin capable of being a GPIO instead and use the GPIO
-		 * feature to do the required inverted push pull.
-		 */
-		it8801_write(IT8801_REG_GPIO23_KSO20, IT8801_REG_MASK_GPIODIR);
-
-		/* Start with KEYBOARD_COLUMN_ALL, output high(so selected). */
-		it8801_ioex_set_level(0, 2, IT8801_REG_GPIO23SOV, 1);
-	}
-
-	/* Keyboard scan in interrupt enable register */
-	it8801_write(IT8801_REG_KSIIER, 0xff);
-	/* Gather KSI interrupt enable */
-	it8801_write(IT8801_REG_GIECR, IT8801_REG_MASK_GKSIIE);
-	/* Alert response enable */
-	it8801_write(IT8801_REG_SMBCR, IT8801_REG_MASK_ARE);
-
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	keyboard_raw_enable_interrupt(1);
-}
-
-__overridable const uint8_t it8801_kso_mapping[] = {
-	0, 1, 20, 3, 4, 5, 6, 17, 18, 16, 15, 11, 12,
-#ifdef CONFIG_KEYBOARD_KEYPAD
-	13, 14
-#endif
-};
-BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX);
-
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	int kso_val;
-
-	/* Tri-state all outputs */
-	if (col == KEYBOARD_COLUMN_NONE) {
-		/* KSO[22:11, 6:0] output high */
-		kso_val = IT8801_REG_MASK_KSOSDIC | IT8801_REG_MASK_AKSOSC;
-
-		if (IS_ENABLED(CONFIG_KEYBOARD_COL2_INVERTED)) {
-			/* Output low(so not selected). */
-			it8801_ioex_set_level(0, 2, IT8801_REG_GPIO23SOV, 0);
-		}
-	}
-	/* Assert all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL) {
-		/* KSO[22:11, 6:0] output low */
-		kso_val = IT8801_REG_MASK_AKSOSC;
-
-		if (IS_ENABLED(CONFIG_KEYBOARD_COL2_INVERTED)) {
-			/* Output high(so selected). */
-			it8801_ioex_set_level(0, 2, IT8801_REG_GPIO23SOV, 1);
-		}
-	} else {
-		/* To check if column is valid or not. */
-		if (col >= KEYBOARD_COLS_MAX)
-			return;
-		/*
-		 * Selected KSO[20, 18:11, 6:3, 1:0] output low,
-		 * all others KSO output high.
-		 */
-		kso_val = it8801_kso_mapping[col];
-
-		if (IS_ENABLED(CONFIG_KEYBOARD_COL2_INVERTED)) {
-			/* GPIO23 is inverted. */
-			if (col == IT8801_REG_MASK_SELKSO2) {
-				/* Output high(so selected). */
-				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 1);
-			} else {
-				/* Output low(so not selected). */
-				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 0);
-			}
-		}
-	}
-
-	it8801_write(IT8801_REG_KSOMCR, kso_val);
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int data = 0;
-	int ksieer = 0;
-
-	it8801_read(IT8801_REG_KSIDR, &data);
-
-	/* This register needs to write clear after reading data */
-	it8801_read(IT8801_REG_KSIEER, &ksieer);
-	it8801_write(IT8801_REG_KSIEER, ksieer);
-
-	/* Bits are active-low, so invert returned levels */
-	return (~data) & 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/* Clear pending iterrupts */
-		it8801_write(IT8801_REG_KSIEER, 0xff);
-
-		/* Enable muxed Keyboard & GPIO interrupt */
-		it8801_muxed_kbd_gpio_intr_enable();
-	}
-
-	it8801_write(IT8801_REG_KSIIER, enable ? 0xff : 0x00);
-}
-#endif /* CONFIG_KEYBOARD_NOT_RAW */
-
-void io_expander_it8801_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&it8801_ioex_event_handler_data, 0);
-}
-
-static int it8801_ioex_read(int ioex, int reg, int *data)
-{
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			 reg, data);
-}
-
-static int it8801_ioex_write(int ioex, int reg, int data)
-{
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			  reg, data);
-}
-
-static int it8801_ioex_update(int ioex, int reg, int data,
-				enum mask_update_action action)
-{
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			  reg, data, action);
-}
-
-static const int it8801_valid_gpio_group[] = {
-	IT8801_VALID_GPIO_G0_MASK,
-	IT8801_VALID_GPIO_G1_MASK,
-	IT8801_VALID_GPIO_G2_MASK,
-};
-
-/* Mutexes */
-static struct mutex ioex_mutex;
-
-static uint8_t it8801_gpio_sov[ARRAY_SIZE(it8801_valid_gpio_group)];
-
-/*
- * Initialize the general purpose I/O port(GPIO)
- */
-static int it8801_ioex_init(int ioex)
-{
-	int ret, port, val = 0;
-
-	/*  Verify Vendor ID registers. */
-	ret = it8801_check_vendor_id();
-	if (ret) {
-		CPRINTS("Failed to read IT8801 vendor id %x", ret);
-		return ret;
-	}
-
-	/*
-	 * We will read the value of SOVR and write it to the
-	 * cache(it8801_gpio_sov[port]) to avoid causing cache
-	 * to reset when EC is reset.
-	 */
-	for (port = 0; port < ARRAY_SIZE(it8801_valid_gpio_group); port++) {
-		it8801_ioex_read(ioex, IT8801_REG_GPIO_SOVR(port), &val);
-		it8801_gpio_sov[port] = val;
-	}
-
-	/* Enable muxed Keyboard & GPIO interrupt */
-	it8801_muxed_kbd_gpio_intr_enable();
-
-	return EC_SUCCESS;
-}
-
-static int ioex_check_is_not_valid(int port, int mask)
-{
-	if (port >= ARRAY_SIZE(it8801_valid_gpio_group)) {
-		CPRINTS("Port%d is not support in IT8801", port);
-		return EC_ERROR_INVAL;
-	}
-
-	if (mask & ~it8801_valid_gpio_group[port]) {
-		CPRINTS("GPIO%d-%d is not support in IT8801", port,
-			__fls(mask & ~it8801_valid_gpio_group[port]));
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it8801_ioex_get_level(int ioex, int port, int mask, int *val)
-{
-	int rv;
-
-	if (ioex_check_is_not_valid(port, mask))
-		return EC_ERROR_INVAL;
-
-	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_IPSR(port), val);
-
-	*val = !!(*val & mask);
-
-	return rv;
-}
-
-static int it8801_ioex_set_level(int ioex, int port, int mask, int value)
-{
-	int rv = EC_SUCCESS;
-
-	if (ioex_check_is_not_valid(port, mask))
-		return EC_ERROR_INVAL;
-
-	mutex_lock(&ioex_mutex);
-	/*
-	 * The bit of output value in SOV is different than
-	 * the one we were about to set it to.
-	 */
-	if (!!(it8801_gpio_sov[port] & mask) ^ value) {
-		if (value)
-			it8801_gpio_sov[port] |= mask;
-		else
-			it8801_gpio_sov[port] &= ~mask;
-
-		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
-	}
-	mutex_unlock(&ioex_mutex);
-
-	return rv;
-}
-
-static int it8801_ioex_get_flags_by_mask(int ioex, int port,
-		int mask, int *flags)
-{
-	int rv, val;
-
-	if (ioex_check_is_not_valid(port, mask))
-		return EC_ERROR_INVAL;
-
-	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_CR(port, mask), &val);
-	if (rv)
-		return rv;
-
-	*flags = 0;
-
-	/* Get GPIO direction */
-	*flags |= (val & IT8801_GPIODIR) ? GPIO_OUTPUT : GPIO_INPUT;
-
-	/* Get GPIO type, 0:push-pull 1:open-drain */
-	if (val & IT8801_GPIOIOT)
-		*flags |= GPIO_OPEN_DRAIN;
-
-	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_IPSR(port), &val);
-	if (rv)
-		return rv;
-
-	/* Get GPIO output level */
-	*flags |= (val & mask) ? GPIO_HIGH : GPIO_LOW;
-
-	return EC_SUCCESS;
-}
-
-static int it8801_ioex_set_flags_by_mask(int ioex, int port,
-		int mask, int flags)
-{
-	int rv, val;
-
-	if (ioex_check_is_not_valid(port, mask))
-		return EC_ERROR_INVAL;
-
-	if (flags & ~IT8801_SUPPORT_GPIO_FLAGS) {
-		CPRINTS("Flag 0x%08x is not supported at port %d, mask %d",
-					flags, port, mask);
-		return EC_ERROR_INVAL;
-	}
-
-	/* GPIO alternate function switching(GPIO[00, 12:15, 20:23]). */
-	rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask),
-					IT8801_REG_MASK_GPIOAFS_FUNC1);
-	if (rv)
-		return rv;
-
-	mutex_lock(&ioex_mutex);
-	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_CR(port, mask), &val);
-	if (rv)
-		goto unlock_mutex;
-
-	/* Select open drain 0:push-pull 1:open-drain */
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= IT8801_GPIOIOT;
-	else
-		val &= ~IT8801_GPIOIOT;
-
-	/* Select GPIO direction */
-	if (flags & GPIO_OUTPUT) {
-		/* Configure the output level */
-		if (flags & GPIO_HIGH)
-			it8801_gpio_sov[port] |= mask;
-		else
-			it8801_gpio_sov[port] &= ~mask;
-
-		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
-		if (rv)
-			goto unlock_mutex;
-
-		val |= IT8801_GPIODIR;
-	} else {
-		val &= ~IT8801_GPIODIR;
-	}
-
-	/* Set Interrupt Type */
-	if (flags & GPIO_INT_RISING)
-		val |= IT8801_GPIOIOT_INT_RISING;
-	if (flags & GPIO_INT_FALLING)
-		val |= IT8801_GPIOIOT_INT_FALLING;
-
-	rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask), val);
-
-unlock_mutex:
-	mutex_unlock(&ioex_mutex);
-
-	return rv;
-}
-
-/* Enable the individual GPIO interrupt pins based on the board requirement. */
-static int it8801_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
-{
-	int rv;
-
-	if (ioex_check_is_not_valid(port, mask))
-		return EC_ERROR_INVAL;
-
-	/* Clear pending interrupt */
-	rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port),
-				mask, MASK_SET);
-	if (rv)
-		return rv;
-
-	return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port),
-				mask, enable ? MASK_SET : MASK_CLR);
-}
-
-static void it8801_ioex_irq(int ioex, int port)
-{
-	int rv, data, i;
-	const struct ioex_info *g;
-
-	rv = it8801_ioex_read(ioex, IT8801_REG_GPIO_ISR(port), &data);
-	if (rv || !data)
-		return;
-
-	/* Trigger the intended interrupt from the IOEX IRQ pins */
-	for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) {
-		if (ioex == g->ioex && port == g->port && data & g->mask) {
-			ioex_irq_handlers[i](i + IOEX_SIGNAL_START);
-			data &= ~g->mask;
-
-			/* Clear pending interrupt */
-			it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port),
-					g->mask, MASK_SET);
-
-			if (!data)
-				break;
-		}
-	}
-}
-
-static void it8801_ioex_event_handler(void)
-{
-	int data, i;
-
-	/* Gather KSI interrupt status register */
-	if (it8801_read(IT8801_REG_GISR, &data))
-		return;
-
-	/* Wake the keyboard scan task if KSI interrupts are triggered */
-	if (IS_ENABLED(CONFIG_KEYBOARD_NOT_RAW) &&
-		data & IT8801_REG_MASK_GISR_GKSIIS)
-		task_wake(TASK_ID_KEYSCAN);
-
-	/*
-	 * Trigger the GPIO callback functions if the GPIO interrupts are
-	 * triggered.
-	 */
-	if (data & (IT8801_REG_MASK_GISR_GGPIOGXIS)) {
-		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) {
-			if (ioex_config[i].drv == &it8801_ioexpander_drv) {
-				/* Interrupt from GPIO port 0 is triggered */
-				if (data & IT8801_REG_MASK_GISR_GGPIOG0IS)
-					it8801_ioex_irq(i, 0);
-				/* Interrupt from GPIO port 1 is triggered */
-				if (data & IT8801_REG_MASK_GISR_GGPIOG1IS)
-					it8801_ioex_irq(i, 1);
-				/* Interrupt from GPIO port 2 is triggered */
-				if (data & IT8801_REG_MASK_GISR_GGPIOG2IS)
-					it8801_ioex_irq(i, 2);
-			}
-		}
-	}
-}
-
-const struct ioexpander_drv it8801_ioexpander_drv = {
-	.init              = &it8801_ioex_init,
-	.get_level         = &it8801_ioex_get_level,
-	.set_level         = &it8801_ioex_set_level,
-	.get_flags_by_mask = &it8801_ioex_get_flags_by_mask,
-	.set_flags_by_mask = &it8801_ioex_set_flags_by_mask,
-	.enable_interrupt  = &it8801_ioex_enable_interrupt,
-};
-
-static void dump_register(int reg)
-{
-	int rv;
-	int data;
-
-	ccprintf("[%Xh] = ", reg);
-
-	rv = it8801_read(reg, &data);
-
-	if (!rv)
-		ccprintf("0x%02x\n", data);
-	else
-		ccprintf("ERR (%d)\n", rv);
-}
-
-static int it8801_dump(int argc, char **argv)
-{
-	dump_register(IT8801_REG_KSIIER);
-	dump_register(IT8801_REG_KSIEER);
-	dump_register(IT8801_REG_KSIDR);
-	dump_register(IT8801_REG_KSOMCR);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(it8801_dump, it8801_dump, "NULL",
-			"Dumps IT8801 registers");
-
-#ifdef CONFIG_IO_EXPANDER_IT8801_PWM
-
-struct it8801_pwm_gpio_map {
-	int port;
-	int mask;
-	int pushpull_en;
-};
-
-const static struct it8801_pwm_gpio_map it8801_pwm_gpio_map[] = {
-	[1] = {.port = 1, .mask = BIT(2), .pushpull_en = BIT(0)},
-	[2] = {.port = 1, .mask = BIT(3), .pushpull_en = BIT(1)},
-	[3] = {.port = 1, .mask = BIT(4), .pushpull_en = BIT(2)},
-	[4] = {.port = 1, .mask = BIT(5), .pushpull_en = BIT(3)},
-	[7] = {.port = 2, .mask = BIT(0), .pushpull_en = BIT(4)},
-	[8] = {.port = 2, .mask = BIT(3), .pushpull_en = BIT(5)},
-	[9] = {.port = 2, .mask = BIT(2), .pushpull_en = BIT(6)},
-};
-
-void it8801_pwm_enable(enum pwm_channel ch, int enabled)
-{
-	int port, mask, val, index;
-
-	index = it8801_pwm_channels[ch].index;
-	if (index < 0 || index >= ARRAY_SIZE(it8801_pwm_gpio_map))
-		return;
-	port = it8801_pwm_gpio_map[index].port;
-	mask = it8801_pwm_gpio_map[index].mask;
-	if (port == 0 && mask == 0)
-		return;
-
-	/*
-	 * PWM1~4,7: alt func 1
-	 * PWM8,9: alt func 2
-	 */
-	if (it8801_pwm_channels[ch].index <= 7)
-		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x1 << IT8801_GPIOAFS_SHIFT);
-	else
-		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x2 << IT8801_GPIOAFS_SHIFT);
-
-	it8801_read(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), &val);
-	val &= (~IT8801_PWMMCR_MCR_MASK);
-	if (enabled)
-		val |= IT8801_PWMMCR_MCR_BLINKING;
-	it8801_write(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), val);
-
-	/*
-	 * 1: enable push pull function
-	 */
-	it8801_read(IT8801_REG_PWMODDSR, &val);
-	val &= ~it8801_pwm_gpio_map[index].pushpull_en;
-	if (enabled)
-		val |= it8801_pwm_gpio_map[index].pushpull_en;
-	it8801_write(IT8801_REG_PWMODDSR, val);
-
-}
-
-int it8801_pwm_get_enabled(enum pwm_channel ch)
-{
-	int val;
-
-	if (it8801_read(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), &val))
-		return 0;
-	return (val & IT8801_PWMMCR_MCR_MASK) == IT8801_PWMMCR_MCR_BLINKING;
-}
-
-void it8801_pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
-{
-	duty = MIN(duty, 255);
-	duty = MAX(duty, 0);
-	it8801_write(IT8801_REG_PWMDCR(it8801_pwm_channels[ch].index), duty);
-}
-
-uint16_t it8801_pwm_get_raw_duty(enum pwm_channel ch)
-{
-	int val;
-
-	if (it8801_read(IT8801_REG_PWMDCR(it8801_pwm_channels[ch].index), &val))
-		return 0;
-	return val;
-}
-
-void it8801_pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	return it8801_pwm_set_raw_duty(ch, percent * 255 / 100);
-}
-
-int it8801_pwm_get_duty(enum pwm_channel ch)
-{
-	return it8801_pwm_get_raw_duty(ch) * 100 / 255;
-}
-
-#ifdef CONFIG_KEYBOARD_BACKLIGHT
-const enum pwm_channel it8801_kblight_pwm_ch = IT8801_PWM_CH_KBLIGHT;
-
-static int it8801_kblight_enable(int enable)
-{
-	it8801_pwm_enable(it8801_kblight_pwm_ch, enable);
-	return EC_SUCCESS;
-}
-
-static int it8801_kblight_set_brightness(int percent)
-{
-	it8801_pwm_set_duty(it8801_kblight_pwm_ch, percent);
-	return EC_SUCCESS;
-}
-
-static int it8801_kblight_get_brightness(void)
-{
-	return it8801_pwm_get_duty(it8801_kblight_pwm_ch);
-}
-
-static int it8801_kblight_init(void)
-{
-	it8801_pwm_set_duty(it8801_kblight_pwm_ch, 0);
-	it8801_pwm_enable(it8801_kblight_pwm_ch, 1);
-	return EC_SUCCESS;
-}
-
-const struct kblight_drv kblight_it8801 = {
-	.init = it8801_kblight_init,
-	.set = it8801_kblight_set_brightness,
-	.get = it8801_kblight_get_brightness,
-	.enable = it8801_kblight_enable,
-};
-#endif
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
diff --git a/driver/ioexpander/it8801.h b/driver/ioexpander/it8801.h
deleted file mode 100644
index 05a17acf78..0000000000
--- a/driver/ioexpander/it8801.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IT8801 is an I/O expander with the keyboard matrix controller.
- *
- */
-
-#ifndef __CROS_EC_IO_EXPANDER_IT8801_H
-#define __CROS_EC_IO_EXPANDER_IT8801_H
-
-/* I2C address flags (7-bit without R/W) */
-#define IT8801_I2C_ADDR1 0x38
-#define IT8801_I2C_ADDR2 0x39
-
-/* Keyboard Matrix Scan control (KBS) */
-#define IT8801_REG_KSOMCR               0x40
-#define IT8801_REG_MASK_KSOSDIC         BIT(7)
-#define IT8801_REG_MASK_KSE             BIT(6)
-#define IT8801_REG_MASK_AKSOSC          BIT(5)
-#define IT8801_REG_KSIDR                0x41
-#define IT8801_REG_KSIEER               0x42
-#define IT8801_REG_KSIIER               0x43
-#define IT8801_REG_SMBCR                0xfa
-#define IT8801_REG_MASK_ARE             BIT(4)
-#define IT8801_REG_GIECR                0xfb
-#define IT8801_REG_MASK_GKSIIE          BIT(3)
-#define IT8801_REG_GPIO10               0x12
-#define IT8801_REG_GPIO00_KSO19         0x0a
-#define IT8801_REG_GPIO01_KSO18         0x0b
-#define IT8801_REG_GPIO22_KSO21         0x1c
-#define IT8801_REG_GPIO23_KSO20         0x1d
-#define IT8801_REG_MASK_GPIOAFS_PULLUP  BIT(7)
-#define IT8801_REG_MASK_GPIOAFS_FUNC2   BIT(6)
-#define IT8801_REG_MASK_GPIODIR         BIT(5)
-#define IT8801_REG_MASK_GPIOPUE         BIT(0)
-#define IT8801_REG_GPIO23SOV            BIT(3)
-#define IT8801_REG_MASK_SELKSO2         0x02
-#define IT8801_REG_GISR                 0xF9
-#define IT8801_REG_MASK_GISR_GKSIIS     BIT(6)
-#define IT8801_REG_MASK_GISR_GGPIOG2IS  BIT(2)
-#define IT8801_REG_MASK_GISR_GGPIOG1IS  BIT(1)
-#define IT8801_REG_MASK_GISR_GGPIOG0IS  BIT(0)
-#define IT8801_REG_MASK_GISR_GGPIOGXIS  (IT8801_REG_MASK_GISR_GGPIOG2IS | \
-		IT8801_REG_MASK_GISR_GGPIOG1IS | IT8801_REG_MASK_GISR_GGPIOG0IS)
-#define IT8801_REG_LBVIDR               0xFE
-#define IT8801_REG_HBVIDR               0xFF
-#define IT8801_KSO_COUNT                18
-
-/* General Purpose I/O Port (GPIO) */
-#define IT8801_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_ANY)
-
-#define IT8801_REG_MASK_GPIOAFS_FUNC1   (0x00 << 7)
-
-/* IT8801 only supports GPIO 0/1/2 */
-#define IT8801_VALID_GPIO_G0_MASK       0xD9
-#define IT8801_VALID_GPIO_G1_MASK       0x3F
-#define IT8801_VALID_GPIO_G2_MASK       0x0F
-
-extern __override_proto const uint8_t it8801_kso_mapping[];
-extern const struct ioexpander_drv it8801_ioexpander_drv;
-
-/* GPIO Register map */
-/* Input pin status register */
-#define IT8801_REG_GPIO_IPSR(port)      (0x00 + (port))
-/* Set output value register */
-#define IT8801_REG_GPIO_SOVR(port)      (0x05 + (port))
-/* Control register */
-#define IT8801_REG_GPIO_CR(port, mask)  \
-	(0x0A + (port) * 8 + GPIO_MASK_TO_NUM(mask))
-/* Interrupt status register */
-#define IT8801_REG_GPIO_ISR(port)       (0x32 + (port))
-/* Interrupt enable register */
-#define IT8801_REG_GPIO_IER(port)       (0x37 + (port))
-
-/* Control register values */
-#define IT8801_GPIOAFS_SHIFT            6  /* bit 6~7 */
-
-#define IT8801_GPIODIR                  BIT(5)  /* direction, output=1 */
-/* input pin */
-#define IT8801_GPIOIOT_INT_RISING       BIT(3)
-#define IT8801_GPIOIOT_INT_FALLING      BIT(4)
-
-#define IT8801_GPIODIR                  BIT(5)
-#define IT8801_GPIOIOT                  BIT(4)
-#define IT8801_GPIOPOL                  BIT(2)  /* polarity */
-#define IT8801_GPIOPDE                  BIT(1)  /* pull-down enable */
-#define IT8801_GPIOPUE                  BIT(0)  /* pull-up enable */
-
-/* ISR for IT8801's SMB_INT# */
-void io_expander_it8801_interrupt(enum gpio_signal signal);
-
-#ifdef CONFIG_IO_EXPANDER_IT8801_PWM
-
-/* Mapping PWM_CH_LED_* to it8801 channel */
-struct it8801_pwm_t {
-	int index;
-};
-
-extern const struct it8801_pwm_t it8801_pwm_channels[];
-extern const struct kblight_drv kblight_it8801;
-
-/* standard pwm interface as defined in pwm.h */
-void it8801_pwm_enable(enum pwm_channel ch, int enabled);
-int it8801_pwm_get_enabled(enum pwm_channel ch);
-void it8801_pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty);
-uint16_t it8801_pwm_get_raw_duty(enum pwm_channel ch);
-void it8801_pwm_set_duty(enum pwm_channel ch, int percent);
-int it8801_pwm_get_duty(enum pwm_channel ch);
-
-#define IT8801_REG_PWMODDSR                            0x5F
-#define IT8801_REG_PWMMCR(n)            (0x60 + ((n) - 1) * 8)
-#define IT8801_REG_PWMDCR(n)            (0x64 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSL(n)           (0x66 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSM(n)           (0x67 + ((n) - 1) * 8)
-
-#define IT8801_PWMMCR_MCR_MASK          0x3
-#define IT8801_PWMMCR_MCR_OFF           0
-#define IT8801_PWMMCR_MCR_BLINKING      1
-#define IT8801_PWMMCR_MCR_BREATHING     2
-#define IT8801_PWMMCR_MCR_ON            3
-
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
-
-#endif /* __CROS_EC_KBEXPANDER_IT8801_H */
diff --git a/driver/ioexpander/pca9534.c b/driver/ioexpander/pca9534.c
deleted file mode 100644
index d56eb864cb..0000000000
--- a/driver/ioexpander/pca9534.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA9534 I/O expander
- */
-
-#include "i2c.h"
-#include "pca9534.h"
-
-static int pca9534_pin_read(const int port, const uint16_t addr_flags,
-			    int reg, int pin, int *val)
-{
-	int ret;
-	ret = i2c_read8(port, addr_flags, reg, val);
-	*val = (*val & BIT(pin)) ? 1 : 0;
-	return ret;
-}
-
-static int pca9534_pin_write(const int port, const uint16_t addr_flags,
-			     int reg, int pin, int val)
-{
-	int ret, v;
-	ret = i2c_read8(port, addr_flags, reg, &v);
-	if (ret != EC_SUCCESS)
-		return ret;
-	v &= ~BIT(pin);
-	if (val)
-		v |= 1 << pin;
-	return i2c_write8(port, addr_flags, reg, v);
-}
-
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level)
-{
-	return pca9534_pin_read(port, addr_flags,
-				PCA9534_REG_INPUT, pin, level);
-}
-
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level)
-{
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_OUTPUT, pin, level);
-}
-
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input)
-{
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_CONFIG, pin, is_input);
-}
diff --git a/driver/ioexpander/pca9534.h b/driver/ioexpander/pca9534.h
deleted file mode 100644
index 0fec577576..0000000000
--- a/driver/ioexpander/pca9534.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA9534 I/O expander
- */
-
-#ifndef __CROS_EC_IOEXPANDER_PCA9534_H
-#define __CROS_EC_IOEXPANDER_PCA9534_H
-
-#define PCA9534_REG_INPUT  0x0
-#define PCA9534_REG_OUTPUT 0x1
-#define PCA9534_REG_CONFIG 0x3
-
-#define PCA9534_OUTPUT 0
-#define PCA9534_INPUT  1
-
-/*
- * Get input level. Note that this reflects the actual level on the
- * pin, even if the pin is configured as output.
- *
- * @param port  The I2C port of PCA9534.
- * @param addr  The address of PCA9534.
- * @param pin   The index of the pin to read.
- * @param level The pointer to where the read level is stored.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level);
-
-/*
- * Set output level. This function has no effect if the pin is
- * configured as input.
- *
- * @param port  The I2C port of PCA9534.
- * @param addr  The address of PCA9534.
- * @param pin   The index of the pin to set.
- * @param level The level to set.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level);
-
-/*
- * Config a pin as input or output.
- *
- * @param port     The I2C port of PCA9534.
- * @param addr     The address of PCA9534.
- * @param pin      The index of the pin to set.
- * @param is_input PCA9534_INPUT or PCA9534_OUTPUT.
- *
- * @return EC_SUCCESS, or EC_ERROR_* on error.
- */
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input);
-
-#endif  /* __CROS_EC_IOEXPANDER_PCA9534_H */
diff --git a/driver/ioexpander/pca9555.h b/driver/ioexpander/pca9555.h
deleted file mode 100644
index 273f898821..0000000000
--- a/driver/ioexpander/pca9555.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA9555 I/O Port expander driver header
- */
-
-#ifndef __CROS_EC_IOEXPANDER_PCA9555_H
-#define __CROS_EC_IOEXPANDER_PCA9555_H
-
-#include "i2c.h"
-
-#define PCA9555_CMD_INPUT_PORT_0		0
-#define PCA9555_CMD_INPUT_PORT_1		1
-#define PCA9555_CMD_OUTPUT_PORT_0		2
-#define PCA9555_CMD_OUTPUT_PORT_1		3
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_0	4
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_1	5
-#define PCA9555_CMD_CONFIGURATION_PORT_0	6
-#define PCA9555_CMD_CONFIGURATION_PORT_1	7
-
-#define PCA9555_IO_0	BIT(0)
-#define PCA9555_IO_1	BIT(1)
-#define PCA9555_IO_2	BIT(2)
-#define PCA9555_IO_3	BIT(3)
-#define PCA9555_IO_4	BIT(4)
-#define PCA9555_IO_5	BIT(5)
-#define PCA9555_IO_6	BIT(6)
-#define PCA9555_IO_7	BIT(7)
-
-static inline int pca9555_read(const int port,
-			       const uint16_t i2c_addr_flags,
-			       int reg, int *data_ptr)
-{
-	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
-}
-
-static inline int pca9555_write(const int port,
-				const uint16_t i2c_addr_flags,
-				int reg, int data)
-{
-	return i2c_write8(port, i2c_addr_flags, reg, data);
-}
-
-#endif /* __CROS_EC_IOEXPANDER_PCA9555_H */
diff --git a/driver/ioexpander/pca9675.c b/driver/ioexpander/pca9675.c
deleted file mode 100644
index 3fe3bfa0c4..0000000000
--- a/driver/ioexpander/pca9675.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA9675PW I/O Port expander driver source
- */
-
-#include "i2c.h"
-#include "ioexpander.h"
-#include "pca9675.h"
-
-struct pca9675_ioexpander {
-	/* I/O port direction (1 = input, 0 = output) */
-	uint16_t io_direction;
-	uint16_t cache_out_pins;
-};
-
-static struct pca9675_ioexpander pca9675_iox[CONFIG_IO_EXPANDER_PORT_COUNT];
-
-static int pca9675_read16(int ioex, uint16_t *data)
-{
-	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags,
-			NULL, 0, (uint8_t *)data, 2);
-}
-
-static int pca9675_write16(int ioex, uint16_t data)
-{
-	/*
-	 * PCA9675 is Quasi-bidirectional I/O architecture hence
-	 * append the direction (1 = input, 0 = output) to prevent
-	 * overwriting I/O pins inadvertently.
-	 */
-	data |= pca9675_iox[ioex].io_direction;
-
-	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags,
-			(uint8_t *)&data, 2, NULL, 0);
-}
-
-static int pca9675_reset(int ioex)
-{
-	uint8_t reset = PCA9675_RESET_SEQ_DATA;
-
-	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			0, &reset, 1, NULL, 0);
-}
-
-static int pca9675_get_flags_by_mask(int ioex, int port, int mask, int *flags)
-{
-	*flags = mask & pca9675_iox[ioex].io_direction ?
-				GPIO_INPUT : GPIO_OUTPUT;
-
-	return EC_SUCCESS;
-}
-
-static int pca9675_get_level(int ioex, int port, int mask, int *val)
-{
-	int rv = EC_SUCCESS;
-	uint16_t data_read;
-
-	/* Read from IO-expander only if the pin is input */
-	if (pca9675_iox[ioex].io_direction & mask) {
-		rv = pca9675_read16(ioex, &data_read);
-		if (!rv)
-			*val = !!(data_read & mask);
-	} else {
-		*val = !!(pca9675_iox[ioex].cache_out_pins & mask);
-	}
-
-	return rv;
-}
-
-static int pca9675_set_level(int ioex, int port, int mask, int val)
-{
-	/* Update the output pins */
-	if (val)
-		pca9675_iox[ioex].cache_out_pins |= mask;
-	else
-		pca9675_iox[ioex].cache_out_pins &= ~mask;
-
-	return pca9675_write16(ioex, pca9675_iox[ioex].cache_out_pins);
-}
-
-static int pca9675_set_flags_by_mask(int ioex, int port, int mask, int flags)
-{
-	int rv = EC_SUCCESS;
-
-	/* Initialize the I/O directions */
-	if (flags & GPIO_INPUT) {
-		pca9675_iox[ioex].io_direction |= mask;
-	} else {
-		pca9675_iox[ioex].io_direction &= ~mask;
-
-		/* Initialize the pin */
-		rv = pca9675_set_level(ioex, port, mask, flags & GPIO_HIGH);
-	}
-
-	return rv;
-}
-
-static int pca9675_enable_interrupt(int ioex, int port, int mask, int enable)
-{
-	/*
-	 * Nothing to do as an interrupt is generated by any rising or
-	 * falling edge of the port inputs.
-	 */
-	return EC_SUCCESS;
-}
-
-int pca9675_init(int ioex)
-{
-	pca9675_iox[ioex].io_direction = PCA9675_DEFAULT_IO_DIRECTION;
-	pca9675_iox[ioex].cache_out_pins = 0;
-
-	/* Set pca9675 to Power-on reset */
-	return pca9675_reset(ioex);
-}
-
-const struct ioexpander_drv pca9675_ioexpander_drv = {
-	.init			= &pca9675_init,
-	.get_level		= &pca9675_get_level,
-	.set_level		= &pca9675_set_level,
-	.get_flags_by_mask	= &pca9675_get_flags_by_mask,
-	.set_flags_by_mask	= &pca9675_set_flags_by_mask,
-	.enable_interrupt	= &pca9675_enable_interrupt,
-};
diff --git a/driver/ioexpander/pca9675.h b/driver/ioexpander/pca9675.h
deleted file mode 100644
index 59f36918a4..0000000000
--- a/driver/ioexpander/pca9675.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA9675PW I/O Port expander driver header
- */
-
-#ifndef __CROS_EC_IOEXPANDER_PCA9675_H
-#define __CROS_EC_IOEXPANDER_PCA9675_H
-
-/* PCA9675 IO pins that can be referenced in gpio.inc */
-enum pca9675_io_pins {
-	PCA9675_IO_P00,
-	PCA9675_IO_P01,
-	PCA9675_IO_P02,
-	PCA9675_IO_P03,
-	PCA9675_IO_P04,
-	PCA9675_IO_P05,
-	PCA9675_IO_P06,
-	PCA9675_IO_P07,
-	PCA9675_IO_P10,
-	PCA9675_IO_P11,
-	PCA9675_IO_P12,
-	PCA9675_IO_P13,
-	PCA9675_IO_P14,
-	PCA9675_IO_P15,
-	PCA9675_IO_P16,
-	PCA9675_IO_P17,
-};
-
-/* Write 06 to address 00 to reset the PCA9675 to back to power up state */
-#define PCA9675_RESET_SEQ_DATA 0x06
-
-/* Default I/O directons of PCA9675 is input */
-#define PCA9675_DEFAULT_IO_DIRECTION 0xffff
-
-extern const struct ioexpander_drv pca9675_ioexpander_drv;
-
-#endif /* __CROS_EC_IOEXPANDER_PCA9675_H */
diff --git a/driver/ioexpander/pcal6408.c b/driver/ioexpander/pcal6408.c
deleted file mode 100644
index 287e0506d0..0000000000
--- a/driver/ioexpander/pcal6408.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA(L)6408 I/O expander
- */
-#include "common.h"
-#include "console.h"
-#include "math_util.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "pcal6408.h"
-
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
-
-/*
- * Store interrupt mask registers locally. In this way,
- * we don't have to read it via i2c transaction every time.
- * Default value of interrupt mask register is 0xff.
- */
-uint8_t pcal6408_int_mask[] = {
-	[0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  0xff };
-
-
-static int pcal6408_read(int ioex, int reg, int *data)
-{
-	int rv;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			reg, data);
-
-	return rv;
-}
-
-static int pcal6408_write(int ioex, int reg, int data)
-{
-	int rv;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			reg, data);
-
-	return rv;
-}
-
-static int pcal6408_ioex_check_is_valid(int port, int mask)
-{
-	if (port != 0)
-		return EC_ERROR_INVAL;
-
-	if (mask & ~PCAL6408_VALID_GPIO_MASK) {
-		CPRINTF("GPIO%02d is not support in PCAL6408\n",
-						__fls(mask));
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int pcal6408_ioex_init(int ioex)
-{
-	/* It seems that we have nothing to do here.
-	 * This chip has not a chip id to be identified.
-	 */
-	return EC_SUCCESS;
-}
-
-static int pcal6408_ioex_get_level(int ioex, int port, int mask, int *val)
-{
-	int rv;
-
-	rv = pcal6408_ioex_check_is_valid(port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_INPUT, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	*val = !!(*val & mask);
-
-	return EC_SUCCESS;
-}
-
-static int pcal6408_ioex_set_level(int ioex, int port, int mask, int value)
-{
-	int rv, val;
-
-	rv = pcal6408_ioex_check_is_valid(port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_OUTPUT, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (value)
-		val |= mask;
-	else
-		val &= ~mask;
-
-	return pcal6408_write(ioex, PCAL6408_REG_OUTPUT, val);
-}
-
-static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask,
-					int *flags)
-{
-	int rv, val;
-
-	rv = pcal6408_ioex_check_is_valid(port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	*flags = GPIO_FLAG_NONE;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_CONFIG, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask)
-		*flags |= GPIO_INPUT;
-	else
-		*flags |= GPIO_OUTPUT;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_INPUT, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask)
-		*flags |= GPIO_HIGH;
-	else
-		*flags |= GPIO_LOW;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_OUT_CONFIG, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & PCAL6408_OUT_CONFIG_OPEN_DRAIN)
-		*flags |= GPIO_OPEN_DRAIN;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_PULL_ENABLE, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (val & mask) {
-		rv = pcal6408_read(ioex, PCAL6408_REG_PULL_UP_DOWN, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		if (val & mask)
-			*flags |= GPIO_PULL_UP;
-		else
-			*flags |= GPIO_PULL_DOWN;
-	}
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_INT_MASK, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if ((!!(val & mask) == 0) && ((*flags) & GPIO_INPUT))
-		*flags |= GPIO_INT_BOTH;
-
-	return rv;
-}
-
-static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
-{
-	int rv, val;
-
-	rv = pcal6408_ioex_check_is_valid(port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (((flags & GPIO_INT_BOTH) == GPIO_INT_RISING) ||
-		((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) {
-		CPRINTF("PCAL6408 only support GPIO_INT_BOTH.\n");
-		return EC_ERROR_INVAL;
-	}
-
-
-	if ((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) &&
-		!(flags & GPIO_INPUT)) {
-		CPRINTF("Interrupt pin must be GPIO_INPUT.\n");
-		return EC_ERROR_INVAL;
-	}
-
-	/* All output gpios share GPIO_OPEN_DRAIN, should be consistent */
-	if (flags & GPIO_OPEN_DRAIN)
-		val = PCAL6408_OUT_CONFIG_OPEN_DRAIN;
-	else
-		val = 0;
-
-	rv = pcal6408_write(ioex, PCAL6408_REG_OUT_CONFIG, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rv = pcal6408_read(ioex, PCAL6408_REG_CONFIG, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (flags & GPIO_INPUT)
-		val |= mask;
-	if (flags & GPIO_OUTPUT)
-		val &= ~mask;
-
-	rv = pcal6408_write(ioex, PCAL6408_REG_CONFIG, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (flags & GPIO_OUTPUT) {
-		rv = pcal6408_read(ioex, PCAL6408_REG_OUTPUT, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		if (flags & GPIO_HIGH)
-			val |= mask;
-		else if (flags & GPIO_LOW)
-			val &= ~mask;
-
-		rv = pcal6408_write(ioex, PCAL6408_REG_OUTPUT, val);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	if (!(flags & (GPIO_PULL_UP | GPIO_PULL_DOWN))) {
-		rv = pcal6408_read(ioex, PCAL6408_REG_PULL_ENABLE, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		val &= ~mask;
-
-		rv = pcal6408_write(ioex, PCAL6408_REG_PULL_ENABLE, val);
-		if (rv != EC_SUCCESS)
-			return rv;
-	} else {
-		rv = pcal6408_read(ioex, PCAL6408_REG_PULL_ENABLE, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		val |= mask;
-
-		rv = pcal6408_write(ioex, PCAL6408_REG_PULL_ENABLE, val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		rv = pcal6408_read(ioex, PCAL6408_REG_PULL_UP_DOWN, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		if (flags & GPIO_PULL_UP)
-			val |= mask;
-		else if (flags & GPIO_PULL_DOWN)
-			val &= ~mask;
-
-		rv = pcal6408_write(ioex, PCAL6408_REG_PULL_UP_DOWN, val);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return rv;
-}
-
-static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
-{
-	int rv, val;
-
-	rv = pcal6408_ioex_check_is_valid(port, mask);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Interrupt should be latched */
-	rv = pcal6408_read(ioex, PCAL6408_REG_INPUT_LATCH, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (enable)
-		val |= mask;
-	else
-		val &= ~mask;
-
-	rv = pcal6408_write(ioex, PCAL6408_REG_INPUT_LATCH, val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/*
-	 * Enable or disable interrupt.
-	 * In PCAL6408_REG_INT_MASK, 0 = enable interrupt,
-	 *                           1 = disable interrupt.
-	 */
-	if (enable)
-		pcal6408_int_mask[ioex] &= ~mask;
-	else
-		pcal6408_int_mask[ioex] |= mask;
-
-	rv = pcal6408_write(ioex, PCAL6408_REG_INT_MASK,
-			pcal6408_int_mask[ioex]);
-
-	return rv;
-}
-
-int pcal6408_ioex_event_handler(int ioex)
-{
-	int int_status, int_mask;
-	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	int i, rv = 0;
-	const struct ioex_info *g;
-
-	int_mask = pcal6408_int_mask[ioex];
-
-	/*
-	 * Read input port register will clear the interrupt,
-	 * read status register will not.
-	 */
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-				PCAL6408_REG_INT_STATUS, &int_status);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/*
-	 * In pcal6408_int_mask[x], 0 = enable interrupt,
-	 *                          1 = disable interrupt.
-	 */
-	int_status = int_status & ~int_mask;
-
-	if (!int_status)
-		return EC_SUCCESS;
-
-	for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) {
-
-		if (ioex == g->ioex && 0 == g->port &&
-					(int_status & g->mask)) {
-			ioex_irq_handlers[i](i + IOEX_SIGNAL_START);
-			int_status &= ~g->mask;
-			if (!int_status)
-				break;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-const struct ioexpander_drv pcal6408_ioexpander_drv = {
-	.init			= &pcal6408_ioex_init,
-	.get_level		= &pcal6408_ioex_get_level,
-	.set_level		= &pcal6408_ioex_set_level,
-	.get_flags_by_mask	= &pcal6408_ioex_get_flags_by_mask,
-	.set_flags_by_mask	= &pcal6408_ioex_set_flags_by_mask,
-	.enable_interrupt	= &pcal6408_ioex_enable_interrupt,
-};
diff --git a/driver/ioexpander/pcal6408.h b/driver/ioexpander/pcal6408.h
deleted file mode 100644
index fc9969aab1..0000000000
--- a/driver/ioexpander/pcal6408.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NXP PCA(L)6408 I/O expander
- */
-
-#ifndef __CROS_EC_IOEXPANDER_PCAL6408_H
-#define __CROS_EC_IOEXPANDER_PCAL6408_H
-
-#define PCAL6408_I2C_ADDR0		0x20
-#define PCAL6408_I2C_ADDR1		0x21
-
-#define PCAL6408_REG_INPUT		0x00
-#define PCAL6408_REG_OUTPUT		0x01
-#define PCAL6408_REG_POLARITY_INVERSION	0x02
-#define PCAL6408_REG_CONFIG		0x03
-#define PCAL6408_REG_OUT_STRENGTH0	0x40
-#define PCAL6408_REG_OUT_STRENGTH1	0x41
-#define PCAL6408_REG_INPUT_LATCH	0x42
-#define PCAL6408_REG_PULL_ENABLE	0x43
-#define PCAL6408_REG_PULL_UP_DOWN	0x44
-#define PCAL6408_REG_INT_MASK		0x45
-#define PCAL6408_REG_INT_STATUS		0x46
-#define PCAL6408_REG_OUT_CONFIG		0x4f
-
-#define PCAL6408_VALID_GPIO_MASK	0xff
-
-#define PCAL6408_OUTPUT			0
-#define PCAL6408_INPUT			1
-
-#define PCAL6408_OUT_CONFIG_OPEN_DRAIN	0x01
-
-/*
- * Check which IO's interrupt event is triggered. If any, call its
- * registered interrupt handler.
- */
-int pcal6408_ioex_event_handler(int ioex);
-
-extern const struct ioexpander_drv pcal6408_ioexpander_drv;
-
-#endif  /* __CROS_EC_IOEXPANDER_PCAL6408_H */
diff --git a/driver/ioexpander/tca64xxa.c b/driver/ioexpander/tca64xxa.c
deleted file mode 100644
index 9a70ceec11..0000000000
--- a/driver/ioexpander/tca64xxa.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "tca64xxa.h"
-
-/*
- * This chip series contain registers in the same order.
- * Difference between models is only amount of registers and
- * value of which you must multiply to access specific register.
- * For 16 bit series, registers are 2 byte away, so to access TCA64XXA_REG_CONF
- * you must multiply it by 2. For 24 bit, they are away by 4 bytes so you
- * must multiply them by 4. Flags value contains information which version
- * of chip is used.
- */
-#define TCA64XXA_PORT_ID(port, reg, flags) \
-	((((flags) & TCA64XXA_FLAG_VER_MASK) \
-	>> TCA64XXA_FLAG_VER_OFFSET) * (reg) + (port))
-
-static int tca64xxa_write_byte(int ioex, int port, int reg, uint8_t val)
-{
-	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	const int reg_addr = TCA64XXA_PORT_ID(port, reg, ioex_p->flags);
-
-	return i2c_write8(ioex_p->i2c_host_port,
-			  ioex_p->i2c_addr_flags,
-			  reg_addr,
-			  val);
-}
-
-static int tca64xxa_read_byte(int ioex, int port, int reg, int *val)
-{
-	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	const int reg_addr = TCA64XXA_PORT_ID(port, reg, ioex_p->flags);
-
-	return i2c_read8(ioex_p->i2c_host_port,
-			 ioex_p->i2c_addr_flags,
-			 reg_addr,
-			 val);
-}
-
-/* Restore default values in registers */
-static int tca64xxa_reset(int ioex, int portsCount)
-{
-	int port;
-	int ret;
-
-	/*
-	 * On servo_v4p1, reset pin is pulled up and it results in values
-	 * not being restored to default ones after software reboot.
-	 * This loop sets default values (from specification) to all registers.
-	 */
-	for (port = 0; port < portsCount; port++) {
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_OUTPUT,
-					  TCA64XXA_DEFAULT_OUTPUT);
-		if (ret)
-			return ret;
-
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_POLARITY_INV,
-					  TCA64XXA_DEFAULT_POLARITY_INV);
-		if (ret)
-			return ret;
-
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_CONF,
-					  TCA64XXA_DEFAULT_CONF);
-		if (ret)
-			return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Initialize IO expander chip/driver */
-static int tca64xxa_init(int ioex)
-{
-	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	int portsCount;
-
-	if (ioex_p->flags & TCA64XXA_FLAG_VER_TCA6416A)
-		portsCount = 2;
-	else if (ioex_p->flags & TCA64XXA_FLAG_VER_TCA6424A)
-		portsCount = 3;
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-
-	if (!system_jumped_late())
-		return tca64xxa_reset(ioex, portsCount);
-
-	return EC_SUCCESS;
-}
-
-/* Get the current level of the IOEX pin */
-static int tca64xxa_get_level(int ioex, int port, int mask, int *val)
-{
-	int buf;
-	int ret;
-
-	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_INPUT, &buf);
-	*val = !!(buf & mask);
-
-	return ret;
-}
-
-/* Set the level of the IOEX pin */
-static int tca64xxa_set_level(int ioex, int port, int mask, int val)
-{
-	int ret;
-	int v;
-
-	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
-	if (ret)
-		return ret;
-
-	if (val)
-		v |= mask;
-	else
-		v &= ~mask;
-
-	return tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT, v);
-}
-
-/* Get flags for the IOEX pin */
-static int tca64xxa_get_flags_by_mask(int ioex, int port, int mask, int *flags)
-{
-	int ret;
-	int v;
-
-	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v);
-	if (ret)
-		return ret;
-
-	*flags = 0;
-	if (v & mask) {
-		*flags |= GPIO_INPUT;
-	} else {
-		*flags |= GPIO_OUTPUT;
-
-		ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
-		if(ret)
-			return ret;
-
-		if (v & mask)
-			*flags |= GPIO_HIGH;
-		else
-			*flags |= GPIO_LOW;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Set flags for the IOEX pin */
-static int tca64xxa_set_flags_by_mask(int ioex, int port, int mask, int flags)
-{
-	int ret;
-	int v;
-
-	/* Output value */
-	if (flags & GPIO_OUTPUT) {
-		ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
-		if (ret)
-			return ret;
-
-		if (flags & GPIO_LOW)
-			v &= ~mask;
-		else if (flags & GPIO_HIGH)
-			v |= mask;
-		else
-			return EC_ERROR_INVAL;
-
-		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT, v);
-		if (ret)
-			return ret;
-	}
-
-	/* Configuration */
-	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v);
-	if(ret)
-		return ret;
-
-	if (flags & GPIO_INPUT)
-		v |= mask;
-	else if (flags & GPIO_OUTPUT)
-		v &= ~mask;
-	else
-		return EC_ERROR_INVAL;
-
-	ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_CONF, v);
-	if (ret)
-		return ret;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-
-/* Read levels for whole IO expander port */
-static int tca64xxa_get_port(int ioex, int port, int *val)
-{
-	return tca64xxa_read_byte(ioex, port, TCA64XXA_REG_INPUT, val);
-}
-
-#endif
-
-/* Driver structure */
-const struct ioexpander_drv tca64xxa_ioexpander_drv = {
-	.init 			= tca64xxa_init,
-	.get_level 		= tca64xxa_get_level,
-	.set_level 		= tca64xxa_set_level,
-	.get_flags_by_mask 	= tca64xxa_get_flags_by_mask,
-	.set_flags_by_mask 	= tca64xxa_set_flags_by_mask,
-	.enable_interrupt 	= NULL,
-#ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port		= tca64xxa_get_port,
-#endif
-};
diff --git a/driver/ioexpander/tca64xxa.h b/driver/ioexpander/tca64xxa.h
deleted file mode 100644
index 8c3448f804..0000000000
--- a/driver/ioexpander/tca64xxa.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_
-#define __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_
-
-#define TCA64XXA_FLAG_VER_TCA6416A	2
-#define TCA64XXA_FLAG_VER_TCA6424A	4
-#define TCA64XXA_FLAG_VER_MASK		GENMASK(2, 1)
-#define TCA64XXA_FLAG_VER_OFFSET	0
-
-#define TCA64XXA_REG_INPUT		0
-#define TCA64XXA_REG_OUTPUT		1
-#define TCA64XXA_REG_POLARITY_INV	2
-#define TCA64XXA_REG_CONF		3
-
-#define TCA64XXA_DEFAULT_OUTPUT		0xFF
-#define TCA64XXA_DEFAULT_POLARITY_INV	0x00
-#define TCA64XXA_DEFAULT_CONF		0xFF
-
-extern const struct ioexpander_drv tca64xxa_ioexpander_drv;
-
-#endif /* __CROS_EC_DRIVER_IOEXPANDER_TCA64XXA_H_ */
diff --git a/driver/led/ds2413.c b/driver/led/ds2413.c
deleted file mode 100644
index b856d85671..0000000000
--- a/driver/led/ds2413.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power LED control for Chrome EC */
-
-#include "charge_state.h"
-#include "console.h"
-#include "hooks.h"
-#include "onewire.h"
-#include "timer.h"
-#include "util.h"
-
-#define ONEWIRE_RETRIES 10
-
-enum led_color {
-	LED_OFF = 0,
-	LED_RED,
-	LED_YELLOW,
-	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static const uint8_t led_masks[LED_COLOR_COUNT] = {0xff, 0xfe, 0xfc, 0xfd};
-static const char * const color_names[LED_COLOR_COUNT] = {
-	"off", "red", "yellow", "green"};
-
-/**
- * Set the onewire LED GPIO controller outputs
- *
- * @param mask		Mask of outputs to enable
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-static int led_set_mask(int mask)
-{
-	int rv;
-
-	/* Reset the 1-wire bus */
-	rv = onewire_reset();
-	if (rv)
-		return rv;
-
-	/* Skip ROM, since only one device */
-	onewire_write(0xcc);
-
-	/* Write and turn on the LEDs */
-	onewire_write(0x5a);
-	onewire_write(mask);
-	onewire_write(~mask);  /* Repeat inverted */
-
-	rv = onewire_read();   /* Confirmation byte */
-	if (rv != 0xaa)
-		return EC_ERROR_UNKNOWN;
-
-	/* The next byte is a read-back of the chip status.  Since we're only
-	 * using lines as outputs, we can ignore it. */
-	return EC_SUCCESS;
-}
-
-static int led_set(enum led_color color)
-{
-	int rv = EC_SUCCESS;
-	int i;
-
-	/*
-	 * 1-wire communication can fail for timing reasons in the current
-	 * system.  We have a limited timing window to send/receive bits, but
-	 * we can't disable interrupts for the rest of the system to guarantee
-	 * we hit that window.  Instead, simply retry the low-level command a
-	 * few times.
-	 */
-	for (i = 0; i < ONEWIRE_RETRIES; i++) {
-		rv = led_set_mask(led_masks[color]);
-		if (rv == EC_SUCCESS)
-			break;
-
-		/*
-		 * Sleep for a bit between tries.  This gives the 1-wire GPIO
-		 * chip time to recover from the failed attempt, and allows
-		 * lower-priority tasks a chance to run.
-		 */
-		usleep(100);
-	}
-
-	return rv;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void onewire_led_tick(void)
-{
-	static enum led_color current_color = LED_COLOR_COUNT;
-	static int tick_count;
-
-	enum led_color new_color = LED_OFF;
-	uint32_t chflags = charge_get_flags();
-
-	tick_count++;
-
-	if (!(chflags & CHARGE_FLAG_EXTERNAL_POWER)) {
-		/* AC isn't present, so the power LED on the AC plug is off */
-		current_color = LED_OFF;
-		return;
-	}
-
-	/* Translate charge state to LED color */
-	switch (charge_get_state()) {
-	case PWR_STATE_IDLE:
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			new_color = (tick_count & 1) ? LED_GREEN : LED_OFF;
-		else
-			new_color = LED_GREEN;
-		break;
-	case PWR_STATE_CHARGE:
-		new_color = LED_YELLOW;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		new_color = LED_GREEN;
-		break;
-	case PWR_STATE_ERROR:
-		new_color = LED_RED;
-		break;
-	default:
-		/* Other states don't change LED color */
-		break;
-	}
-
-	/*
-	 * The power adapter on link can partially unplug and lose its LED
-	 * state.  There's no way to detect this, so just assume it forgets its
-	 * state every 10 seconds.
-	 */
-	if (!(tick_count % 10))
-		current_color = LED_COLOR_COUNT;
-
-	/* If current color is still correct, leave now */
-	if (new_color == current_color)
-		return;
-
-	/* Update LED */
-	if (!led_set(new_color))
-		current_color = new_color;
-}
-DECLARE_HOOK(HOOK_SECOND, onewire_led_tick, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console commands */
-#define CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
-{
-	int i;
-
-	/* Pick a color, any color... */
-	for (i = 0; i < LED_COLOR_COUNT; i++) {
-		if (!strcasecmp(argv[1], color_names[i]))
-			return led_set(i);
-	}
-	return EC_ERROR_PARAM1;
-}
-DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-			"<off | red | yellow | green>",
-			"Set power LED color");
-#endif
diff --git a/driver/led/lm3509.c b/driver/led/lm3509.c
deleted file mode 100644
index 7c20c43ac2..0000000000
--- a/driver/led/lm3509.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LM3509 LED driver.
- */
-
-#include "compile_time_macros.h"
-#include "i2c.h"
-#include "keyboard_backlight.h"
-#include "lm3509.h"
-
-static inline int lm3509_write(uint8_t reg, uint8_t val)
-{
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			  reg, val);
-}
-
-static inline int lm3509_read(uint8_t reg, int *val)
-{
-	return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			 reg, val);
-}
-
-/* Brightness level (0.0 to 100.0%) to brightness register conversion table */
-static const uint16_t lm3509_brightness[32] = {
-	  0,   1,   6,  10,  11,  13,  16,  20,
-	 24,  28,  31,  37,  43,  52,  62,  75,
-	 87, 100, 125, 150, 168, 187, 225, 262,
-	312, 375, 437, 525, 612, 700, 875, 1000
-};
-
-static int brightness_to_bmain(int percent)
-{
-	int i;
-	int b = percent * 10;
-
-	for (i = 1; i < sizeof(lm3509_brightness); i++) {
-		int low = lm3509_brightness[i - 1];
-		int high = lm3509_brightness[i];
-		if (high < b)
-			continue;
-		/* rounding to the nearest */
-		return (b - low < high - b) ? i - 1 : i;
-	}
-	/* Brightness is out of range. Return the highest value. */
-	return i - 1;
-}
-
-static int lm3509_power(int enable)
-{
-	/* Enable both MAIN and SUB in unison mode.
-	 * Don't alter brightness here. It's not driver's business. */
-	return lm3509_write(LM3509_REG_GP, enable ? 0x7 : 0);
-}
-
-static int lm3509_set_brightness(int percent)
-{
-	/* We don't need to read/mask/write BMAIN because bit6 and 7 are non
-	 * functional read only bits.
-	 */
-	return lm3509_write(LM3509_REG_BMAIN, brightness_to_bmain(percent));
-}
-
-static int lm3509_get_brightness(void)
-{
-	int rv, val;
-	rv = lm3509_read(LM3509_REG_BMAIN, &val);
-	if (rv)
-		return -1;
-	val &= LM3509_BMAIN_MASK;
-	return lm3509_brightness[val] / 10;
-}
-
-static int lm3509_init(void)
-{
-	return EC_SUCCESS;
-}
-
-const struct kblight_drv kblight_lm3509 = {
-	.init = lm3509_init,
-	.set = lm3509_set_brightness,
-	.get = lm3509_get_brightness,
-	.enable = lm3509_power,
-};
diff --git a/driver/led/lm3509.h b/driver/led/lm3509.h
deleted file mode 100644
index a7defe1fb7..0000000000
--- a/driver/led/lm3509.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LM3509 LED driver.
- */
-
-#ifndef __CROS_EC_LM3509_H
-#define __CROS_EC_LM3509_H
-
-#define LM3509_I2C_ADDR_FLAGS	0x36
-
-/*
- * General purpose register
- *
- * [2]= set both main and secondary current same
- *      both control by BMAIN.
- * [1]= enable secondary current sink.
- * [0]= enable main current sink.
- */
-#define LM3509_REG_GP		0x10
-
-/*
- * Brightness register
- *
- * 0x00: 0%
- * 0x1F: 100%
- * Power-on-value: 0% (0xE0)
- */
-#define LM3509_REG_BMAIN	0xA0
-#define LM3509_REG_BSUB		0xB0
-
-#define LM3509_BMAIN_MASK	0x1F
-
-extern const struct kblight_drv kblight_lm3509;
-
-#endif /* __CROS_EC_LM3509_H */
diff --git a/driver/led/lm3630a.c b/driver/led/lm3630a.c
deleted file mode 100644
index a2c4aaa74c..0000000000
--- a/driver/led/lm3630a.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LM3630A LED driver.
- */
-
-#include "hooks.h"
-#include "i2c.h"
-#include "lm3630a.h"
-#include "timer.h"
-
-
-/* I2C address */
-#define LM3630A_I2C_ADDR_FLAGS 0x36
-
-static inline int lm3630a_write(uint8_t reg, uint8_t val)
-{
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS,
-			  reg, val);
-}
-
-static inline int lm3630a_read(uint8_t reg, int *val)
-{
-	return i2c_read8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS,
-			 reg, val);
-}
-
-static void deferred_lm3630a_poweron(void)
-{
-	/*
-	 * Set full brightness so that PWM will control. This needs to happen
-	 * after setting the control register, because enabling the banks
-	 * resets the value to 0.
-	 */
-	lm3630a_write(LM3630A_REG_A_BRIGHTNESS, 0xff);
-}
-DECLARE_DEFERRED(deferred_lm3630a_poweron);
-
-int lm3630a_poweron(void)
-{
-	int ret = 0;
-
-	/*
-	 * LM3630A will NAK I2C transactions for 1ms (tWAIT in the datasheet)
-	 * after HWEN asserted or after SW reset.
-	 */
-	msleep(1);
-
-	/* Sample PWM every 8 periods. */
-	ret |= lm3630a_write(LM3630A_REG_FILTER_STRENGTH, 0x3);
-
-	/* Enable feedback and PWM for banks A. */
-	ret |= lm3630a_write(LM3630A_REG_CONFIG,
-				LM3630A_CFG_BIT_FB_EN_A |
-				LM3630A_CFG_BIT_PWM_EN_A);
-
-	/* 24V, 800mA overcurrent protection, 500kHz boost frequency. */
-	ret |= lm3630a_write(LM3630A_REG_BOOST_CONTROL,
-				LM3630A_BOOST_OVP_24V |
-				LM3630A_BOOST_OCP_800MA |
-				LM3630A_FMODE_500KHZ);
-
-	/* Limit current to 24.5mA */
-	ret |= lm3630a_write(LM3630A_REG_A_CURRENT, 0x1a);
-
-	/* Enable bank A, put in linear mode, and connect LED2 to bank A. */
-	ret |= lm3630a_write(LM3630A_REG_CONTROL,
-				LM3630A_CTRL_BIT_LINEAR_A |
-				LM3630A_CTRL_BIT_LED_EN_A |
-				LM3630A_CTRL_BIT_LED2_ON_A);
-
-	/*
-	 * Only set the brightness after ~100 ms. Without this, LED may blink
-	 * for a short duration, as the PWM sampler sometimes appears to be
-	 * confused, and slowly dim from a large initial PWM input value.
-	 */
-	hook_call_deferred(&deferred_lm3630a_poweron_data, 100 * MSEC);
-
-	return ret;
-}
-
-int lm3630a_poweroff(void)
-{
-	return lm3630a_write(LM3630A_REG_CONTROL, LM3630A_CTRL_BIT_SLEEP_CMD);
-}
diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h
deleted file mode 100644
index d43304b66e..0000000000
--- a/driver/led/lm3630a.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LM3630A LED driver.
- */
-
-#ifndef __CROS_EC_LM3630A_H
-#define __CROS_EC_LM3630A_H
-
-#define LM3630A_REG_CONTROL		0x00
-#define LM3630A_REG_CONFIG		0x01
-#define LM3630A_REG_BOOST_CONTROL	0x02
-#define LM3630A_REG_A_BRIGHTNESS	0x03
-#define LM3630A_REG_B_BRIGHTNESS	0x04
-#define LM3630A_REG_A_CURRENT		0x05
-#define LM3630A_REG_B_CURRENT		0x06
-#define LM3630A_REG_ONOFF_RAMP		0x07
-#define LM3630A_REG_RUN_RAMP		0x08
-#define LM3630A_REG_INT_STATUS		0x09
-#define LM3630A_REG_INT_ENABLE		0x0a
-#define LM3630A_REG_FAULT_STATUS	0x0b
-#define LM3630A_REG_SW_RESET		0x0f
-#define LM3630A_REG_PWM_OUT_LOW		0x12
-#define LM3630A_REG_PWM_OUT_HIGH	0x13
-#define LM3630A_REG_REVISION		0x1f
-#define LM3630A_REG_FILTER_STRENGTH	0x50
-
-/* Control register bits */
-#define LM3630A_CTRL_BIT_SLEEP_CMD	BIT(7)
-#define LM3630A_CTRL_BIT_SLEEP_STAT	BIT(6)
-#define LM3630A_CTRL_BIT_LINEAR_A	BIT(4)
-#define LM3630A_CTRL_BIT_LINEAR_B	BIT(3)
-#define LM3630A_CTRL_BIT_LED_EN_A	BIT(2)
-#define LM3630A_CTRL_BIT_LED_EN_B	BIT(1)
-#define LM3630A_CTRL_BIT_LED2_ON_A	BIT(0)
-
-/* Config register bits */
-#define LM3630A_CFG_BIT_FB_EN_B		BIT(4)
-#define LM3630A_CFG_BIT_FB_EN_A		BIT(3)
-#define LM3630A_CFG_BIT_PWM_LOW		BIT(2)
-#define LM3630A_CFG_BIT_PWM_EN_B	BIT(1)
-#define LM3630A_CFG_BIT_PWM_EN_A	BIT(0)
-
-/* Boost control register bits */
-#define LM3630A_BOOST_OVP_16V		(0 << 5)
-#define LM3630A_BOOST_OVP_24V		BIT(5)
-#define LM3630A_BOOST_OVP_32V		(2 << 5)
-#define LM3630A_BOOST_OVP_40V		(3 << 5)
-#define LM3630A_BOOST_OCP_600MA		(0 << 3)
-#define LM3630A_BOOST_OCP_800MA		BIT(3)
-#define LM3630A_BOOST_OCP_1000MA	(2 << 3)
-#define LM3630A_BOOST_OCP_1200MA	(3 << 3)
-#define LM3630A_BOOST_SLOW_START	BIT(2)
-#define LM3630A_SHIFT_500KHZ		(0 << 1)  /* FMODE=0 */
-#define LM3630A_SHIFT_560KHZ		BIT(1)  /* FMODE=0 */
-#define LM3630A_SHIFT_1000KHZ		(0 << 1)  /* FMODE=1 */
-#define LM3630A_SHIFT_1120KHZ		BIT(1)  /* FMODE=1 */
-#define LM3630A_FMODE_500KHZ		(0 << 0)
-#define LM3630A_FMODE_1000KHZ		BIT(0)
-
-/* Power on and initialize LM3630A. */
-int lm3630a_poweron(void);
-
-/* Power off LM3630A. */
-int lm3630a_poweroff(void);
-
-#endif /* __CROS_EC_LM3630A_H */
diff --git a/driver/led/lp5562.c b/driver/led/lp5562.c
deleted file mode 100644
index e0758a8b91..0000000000
--- a/driver/led/lp5562.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LP5562 driver.
- */
-
-#include "console.h"
-#include "i2c.h"
-#include "lp5562.h"
-#include "timer.h"
-#include "util.h"
-
-/* I2C address */
-#define LP5562_I2C_ADDR_FLAGS 0x30
-
-inline int lp5562_write(uint8_t reg, uint8_t val)
-{
-	return i2c_write8(I2C_PORT_MASTER, LP5562_I2C_ADDR_FLAGS, reg, val);
-}
-
-inline int lp5562_read(uint8_t reg, int *val)
-{
-	return i2c_read8(I2C_PORT_MASTER, LP5562_I2C_ADDR_FLAGS, reg, val);
-}
-
-int lp5562_set_color(uint32_t rgb)
-{
-	int ret = 0;
-
-	ret |= lp5562_write(LP5562_REG_B_PWM, rgb & 0xff);
-	ret |= lp5562_write(LP5562_REG_G_PWM, (rgb >> 8) & 0xff);
-	ret |= lp5562_write(LP5562_REG_R_PWM, (rgb >> 16) & 0xff);
-
-	return ret;
-}
-
-int lp5562_set_engine(uint8_t r, uint8_t g, uint8_t b)
-{
-	return lp5562_write(LP5562_REG_LED_MAP, (r << 4) | (g << 2) | b);
-}
-
-int lp5562_engine_load(int engine, const uint8_t *program, int size)
-{
-	int prog_addr = LP5562_REG_ENG_PROG(engine);
-	int i, ret, val;
-	int shift = 6 - engine * 2;
-
-	ret = lp5562_read(LP5562_REG_OP_MODE, &val);
-	if (ret)
-		return ret;
-	val &= ~(0x3 << shift);
-	val |= 0x1 << shift;
-	ret = lp5562_write(LP5562_REG_OP_MODE, val);
-	if (ret)
-		return ret;
-
-	for (i = 0; i < size; ++i) {
-		ret = lp5562_write(prog_addr + i, program[i]);
-		if (ret)
-			return ret;
-	}
-
-	val &= ~(0x3 << shift);
-	val |= 0x2 << shift;
-	ret = lp5562_write(LP5562_REG_OP_MODE, val);
-
-	return ret;
-}
-
-int lp5562_engine_control(int eng1, int eng2, int eng3)
-{
-	int ret, val;
-
-	ret = lp5562_read(LP5562_REG_ENABLE, &val);
-	if (ret)
-		return ret;
-	val &= 0xc0;
-	val |= (eng1 << 4) | (eng2 << 2) | eng3;
-	return lp5562_write(LP5562_REG_ENABLE, val);
-}
-
-int lp5562_get_engine_state(int engine)
-{
-	int val;
-
-	if (lp5562_read(LP5562_REG_ENABLE, &val))
-		return 0xee;
-	return (val >> (6 - engine * 2)) & 0x3;
-}
-
-int lp5562_poweron(void)
-{
-	int ret = 0;
-
-	ret |= lp5562_write(LP5562_REG_ENABLE, 0x40);
-	udelay(500); /* start-up delay */
-
-	ret |= lp5562_write(LP5562_REG_CONFIG, 0x1);
-	ret |= lp5562_write(LP5562_REG_LED_MAP, 0x0);
-
-	return ret;
-}
-
-int lp5562_poweroff(void)
-{
-	return lp5562_write(LP5562_REG_ENABLE, 0x0);
-}
-
-int lp5562_get_pc(int engine)
-{
-	int ret;
-	if (lp5562_read(LP5562_REG_ENG1_PC + engine - 1, &ret))
-		return 0xee;
-	return ret;
-}
-
-int lp5562_set_pc(int engine, int val)
-{
-	return lp5562_write(LP5562_REG_ENG1_PC + engine - 1, val);
-}
-
-/*****************************************************************************/
-/* Console commands */
-#ifdef CONFIG_CMD_POWERLED
-static int command_lp5562(int argc, char **argv)
-{
-	if (argc == 4) {
-		char *e;
-		uint8_t red, green, blue;
-
-		red = strtoi(argv[1], &e, 0);
-		if (e && *e)
-			return EC_ERROR_PARAM1;
-		green = strtoi(argv[2], &e, 0);
-		if (e && *e)
-			return EC_ERROR_PARAM2;
-		blue = strtoi(argv[3], &e, 0);
-		if (e && *e)
-			return EC_ERROR_PARAM3;
-
-		return lp5562_set_color((red << 16) | (green << 8) | blue);
-	} else if (argc == 2) {
-		int v;
-
-		if (!parse_bool(argv[1], &v))
-			return EC_ERROR_PARAM1;
-
-		if (v)
-			return lp5562_poweron();
-		else
-			return lp5562_poweroff();
-	}
-
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(lp5562, command_lp5562,
-			"on | off | <red> <green> <blue>",
-			"Set the color of the LED");
-#endif
diff --git a/driver/led/lp5562.h b/driver/led/lp5562.h
deleted file mode 100644
index 75e820aab7..0000000000
--- a/driver/led/lp5562.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI LP5562 LED driver.
- */
-
-#ifndef __CROS_EC_LP5562_H
-#define __CROS_EC_LP5562_H
-
-#define LP5562_REG_ENABLE	0x00
-#define LP5562_REG_OP_MODE	0x01
-#define LP5562_REG_B_PWM	0x02
-#define LP5562_REG_G_PWM	0x03
-#define LP5562_REG_R_PWM	0x04
-#define LP5562_REG_B_CURRENT	0x05
-#define LP5562_REG_G_CURRENT	0x06
-#define LP5562_REG_R_CURRENT	0x07
-#define LP5562_REG_CONFIG	0x08
-#define LP5562_REG_ENG1_PC	0x09
-#define LP5562_REG_ENG2_PC	0x0a
-#define LP5562_REG_ENG3_PC	0x0b
-#define LP5562_REG_STATUS	0x0c
-#define LP5562_REG_RESET	0x0d
-#define LP5562_REG_W_PWM	0x0e
-#define LP5562_REG_W_CURRENT	0x0f
-#define LP5562_REG_LED_MAP	0x70
-
-#define LP5562_REG_ENG_PROG(n)	(0x10 + ((n)-1) * 0x20)
-
-/* Brightness range: 0x00 - 0xff */
-#define LP5562_COLOR_NONE	0x000000
-#define LP5562_COLOR_RED(b)	(0x010000 * (b))
-#define LP5562_COLOR_GREEN(b)	(0x000100 * (b))
-#define LP5562_COLOR_BLUE(b)	(0x000001 * (b))
-
-#define LP5562_ENG_SEL_NONE	0x0
-#define LP5562_ENG_SEL_1	0x1
-#define LP5562_ENG_SEL_2	0x2
-#define LP5562_ENG_SEL_3	0x3
-
-#define LP5562_ENG_HOLD		0x0
-#define LP5562_ENG_STEP		0x1
-#define LP5562_ENG_RUN		0x2
-
-/* Power on and initialize LP5562. */
-int lp5562_poweron(void);
-
-/* Power off LP5562. */
-int lp5562_poweroff(void);
-
-/*
- * Set LED color.
- * The parameter 'rgb' is in the format 0x00RRGGBB.
- */
-int lp5562_set_color(uint32_t rgb);
-
-/* Set lighting engine used by each color */
-int lp5562_set_engine(uint8_t r, uint8_t g, uint8_t b);
-
-/* Load lighting engine program */
-int lp5562_engine_load(int engine, const uint8_t *program, int size);
-
-/* Control lighting engine execution state */
-int lp5562_engine_control(int eng1, int eng2, int eng3);
-
-/* Get engine execution state. Return 0xee on error. */
-int lp5562_get_engine_state(int engine);
-
-/* Get current program counter. Return 0xee on error. */
-int lp5562_get_pc(int engine);
-
-/* Set program counter */
-int lp5562_set_pc(int engine, int val);
-
-#endif /* __CROS_EC_LP5562_H */
diff --git a/driver/led/max695x.c b/driver/led/max695x.c
deleted file mode 100644
index 6f0e1b8e84..0000000000
--- a/driver/led/max695x.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MAX6958/MAX6959 7-Segment LED Display Driver
- */
-
-#include "common.h"
-#include "console.h"
-#include "display_7seg.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "max695x.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static inline int max695x_i2c_write8(uint8_t offset, uint8_t data)
-{
-	return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, (int)data);
-}
-
-static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len)
-{
-	/*
-	 * The address pointer stored in the MAX695x increments after
-	 * each data byte is written unless the address equals 01111111
-	 */
-	return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, data, len);
-}
-
-int display_7seg_write(enum seven_seg_module_display module, uint16_t data)
-{
-	uint8_t buf[4];
-
-	/*
-	 * Convert the data into binary coded hexadecimal value i.e.
-	 * in hexadecimal code-decode mode, the decoder prints 1 byte
-	 * on two segments. It checks the lower nibble of the data in
-	 * the digit register (D3–D0), disregarding bits D7–D4. Hence,
-	 * preparing the hexadecimal buffer to be sent.
-	 *
-	 * Segment 3-2 : Module name
-	 *	  0xEC : EC
-	 *	  0x80 : PORT80
-	 * Segment 1-0 : Data
-	 * For console Command segment 3-0 : Data
-	 */
-	switch (module) {
-	case SEVEN_SEG_CONSOLE_DISPLAY:
-		/* Segment - 3 */
-		buf[0] = (data >> 12) & 0x0F;
-		/* Segment - 2 */
-		buf[1] = (data >> 8) & 0x0F;
-		break;
-	case SEVEN_SEG_EC_DISPLAY:
-		/* Segment - 3 */
-		buf[0] = 0x0E;
-		/* Segment - 2 */
-		buf[1] = 0x0C;
-		break;
-	case SEVEN_SEG_PORT80_DISPLAY:
-		/* Segment - 3 */
-		buf[0] = 0x08;
-		/* Segment - 2 */
-		buf[1] = 0x00;
-		break;
-	default:
-		CPRINTS("Unknown Module");
-		return EC_ERROR_UNKNOWN;
-	}
-	/* Segment - 1 */
-	buf[2] = (data >> 4) & 0x0F;
-	/* Segment - 0 */
-	buf[3] = data & 0x0F;
-
-	return max695x_i2c_write(MAX695X_DIGIT0_ADDR, buf, ARRAY_SIZE(buf));
-}
-
-/**
- * Initialise MAX656x 7-segment display.
- */
-static void max695x_init(void)
-{
-	uint8_t buf[4] = {
-		[0] = MAX695X_DECODE_MODE_HEX_DECODE,
-		[1] = MAX695X_INTENSITY_MEDIUM,
-		[2] = MAX695X_SCAN_LIMIT_4,
-		[3] = MAX695X_CONFIG_OPR_NORMAL
-	};
-	max695x_i2c_write(MAX695X_REG_DECODE_MODE, buf, ARRAY_SIZE(buf));
-}
-DECLARE_HOOK(HOOK_INIT, max695x_init, HOOK_PRIO_DEFAULT);
-
-static void max695x_shutdown(void)
-{
-	max695x_i2c_write8(MAX695X_REG_CONFIG,
-			   MAX695X_CONFIG_OPR_SHUTDOWN);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, max695x_shutdown, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CMD_SEVEN_SEG_DISPLAY
-static int console_command_max695x_write(int argc, char **argv)
-{
-	char *e;
-	int val;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Get value to be written to the seven segment display*/
-	val = strtoi(argv[1], &e, 0);
-	if (*e || val < 0 || val > UINT16_MAX)
-		return EC_ERROR_PARAM1;
-
-	return display_7seg_write(SEVEN_SEG_CONSOLE_DISPLAY, val);
-}
-DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write,
-			"<val>",
-			"Write to 7 segment display in hex");
-#endif
diff --git a/driver/led/max695x.h b/driver/led/max695x.h
deleted file mode 100644
index 5ed5d91e2f..0000000000
--- a/driver/led/max695x.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MAX6958/MAX6959 7-Segment LED Display Driver header
- */
-
-#ifndef __CROS_EC_MAX656X_H
-#define __CROS_EC_MAX656X_H
-
-/* I2C interface */
-#define MAX695X_I2C_ADDR1_FLAGS	0x38
-#define MAX695X_I2C_ADDR2_FLAGS	0x39
-
-/* Decode mode register */
-#define MAX695X_REG_DECODE_MODE		0x01
-/* Hexadecimal decode for digits 3–0 */
-#define MAX695X_DECODE_MODE_HEX_DECODE	0x0f
-
-/* Intensity register */
-#define MAX695X_REG_INTENSITY		0x02
-/* Setting meduim intensity */
-#define MAX695X_INTENSITY_MEDIUM	0x20
-
-/* Scan limit register value */
-#define MAX695X_REG_SCAN_LIMIT		0x03
-
-/* Scanning digits 0-3 */
-#define MAX695X_SCAN_LIMIT_4		0x03
-
-/* Configuration register */
-#define MAX695X_REG_CONFIG		0x04
-/* Shutdown seven segment display */
-#define MAX695X_CONFIG_OPR_SHUTDOWN	0x00
-/* Start seven segment display */
-#define MAX695X_CONFIG_OPR_NORMAL	0x01
-
-/* Digit addresses */
-#define MAX695X_DIGIT0_ADDR	0x20
-#define MAX695X_DIGIT1_ADDR	0x21
-#define MAX695X_DIGIT2_ADDR	0x22
-#define MAX695X_DIGIT3_ADDR	0x23
-
-#endif /* __CROS_EC_MAX656X_H */
diff --git a/driver/led/oz554.c b/driver/led/oz554.c
deleted file mode 100644
index 504ac55e90..0000000000
--- a/driver/led/oz554.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * O2 Micro OZ554 LED driver.
- */
-
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "oz554.h"
-#include "task.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-
-#define I2C_ADDR_OZ554_FLAGS	0x31
-
-struct oz554_value {
-	uint8_t offset;
-	uint8_t data;
-};
-
-/*
- * OZ554ALN asserts the interrupt when it's ready for writing settings, which
- * are cleared when it's turned off. We enable the interrupt on HOOK_INIT and
- * keep it enabled in S0/S3/S5.
- *
- * It's assumed the device doesn't have a lid and OZ554ALN is powered only in
- * S0. For clamshell devices, different interrupt & power control scheme may be
- * needed.
- */
-
-/* This ordering is suggested by vendor. */
-static struct oz554_value oz554_conf[] = {
-	/*
-	 * Reigster 0x01: Operation frequency control
-	 * Frequency selection: 300(KHz)
-	 * Short circuit protection: 8(V)
-	 */
-	{.offset = 1, .data = 0x43},
-	/*
-	 * Reigster 0x02: LED current amplitude control
-	 * ISET Resistor: 10.2(Kohm)
-	 * Maximum LED current: 1636/10.2 = 160.4(mA)
-	 * Setting LED current: 65(mA)
-	 */
-	{.offset = 2, .data = 0x65},
-	/*
-	 * Reigster 0x03: LED backlight Status
-	 * Status function: Read only
-	 */
-	{.offset = 3, .data = 0x00},
-	/*
-	 * Reigster 0x04: LED current control with SMBus
-	 * SMBus PWM function: None Use
-	 */
-	{.offset = 4, .data = 0x00},
-	/*
-	 * Reigster 0x05: OVP, OCP control
-	 * Over Current Protection: 0.5(V)
-	 * Panel LED Voltage(Max): 47.8(V)
-	 * OVP setting: 54(V)
-	 */
-	{.offset = 5, .data = 0x97},
-	/*
-	 * Reigster 0x00: Dimming mode and string ON/OFF control
-	 * String Selection: 4(Number)
-	 * Interface Selection: 1
-	 * Brightness mode: 3
-	 */
-	{.offset = 0, .data = 0xF2},
-};
-static const int oz554_conf_size = ARRAY_SIZE(oz554_conf);
-
-static void set_oz554_reg(void)
-{
-	int i;
-
-	for (i = 0; i < oz554_conf_size; ++i) {
-		int rv = i2c_write8(I2C_PORT_BACKLIGHT,
-				    I2C_ADDR_OZ554_FLAGS,
-				    oz554_conf[i].offset, oz554_conf[i].data);
-		if (rv) {
-			CPRINTS("Write OZ554 register %d failed rv=%d" , i, rv);
-			return;
-		}
-	}
-	CPRINTS("Wrote OZ554 settings");
-}
-
-static void backlight_enable_deferred(void)
-{
-	if (gpio_get_level(GPIO_PANEL_BACKLIGHT_EN))
-		set_oz554_reg();
-}
-DECLARE_DEFERRED(backlight_enable_deferred);
-
-void backlight_enable_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * 1. Spec says backlight should be turned on after 500ms
-	 *    after eDP signals are ready.
-	 *
-	 * 2. There's no way to get exact eDP ready time, therefore,
-	 *    give one second delay.
-	 *
-	 * power up  __/----------------
-	 * eDP       ______/------------
-	 * backlight _____________/-----
-	 *                 |- t1 -| : >=500 ms
-	 *             |-   t2   -| : 1 second is enough
-	 */
-	hook_call_deferred(&backlight_enable_deferred_data,
-                           OZ554_POWER_BACKLIGHT_DELAY);
-}
-
-int oz554_set_config(int offset, int data)
-{
-	int i;
-	for (i = 0; i < oz554_conf_size; i++) {
-		if (oz554_conf[i].offset == offset)
-			break;
-	}
-	if (i >= oz554_conf_size) {
-		/* Matching offset not found */
-		CPRINTS("oz554: offset %d not found", i);
-		return EC_ERROR_INVAL;
-	}
-	oz554_conf[i].data = data;
-	return EC_SUCCESS;
-}
-
-static void init_oz554(void)
-{
-	oz554_board_init();
-
-	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
-}
-DECLARE_HOOK(HOOK_INIT, init_oz554, HOOK_PRIO_DEFAULT);
-
-
-__overridable void oz554_board_init(void)
-{
-}
diff --git a/driver/led/oz554.h b/driver/led/oz554.h
deleted file mode 100644
index d1d9d9656e..0000000000
--- a/driver/led/oz554.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * O2 Micro OZ554 LED driver.
- */
-
-#ifndef __CROS_EC_OZ554_H
-#define __CROS_EC_OZ554_H
-
-#include "gpio.h"
-#include "common.h"
-
-/*
- * Overridable board initialization.  Should be overridden by a board
- * specific function if the default is not appropriate
- */
-__override_proto void oz554_board_init(void);
-
-/**
- * Update oz554 configuration array (oz554_conf).
- *
- * @param offset: Offset of the register to be set.
- * @param data:   Value to be set.
- * @return EC_SUCCESS or EC_ERROR_* for errors.
- */
-int oz554_set_config(int offset, int data);
-
-#ifndef OZ554_POWER_BACKLIGHT_DELAY
-#define OZ554_POWER_BACKLIGHT_DELAY SECOND
-#endif
-
-void backlight_enable_interrupt(enum gpio_signal signal);
-
-#endif
diff --git a/driver/ln9310.c b/driver/ln9310.c
deleted file mode 100644
index 3464cf46a2..0000000000
--- a/driver/ln9310.c
+++ /dev/null
@@ -1,573 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LION Semiconductor LN-9310 switched capacitor converter.
- */
-
-#include "common.h"
-#include "console.h"
-#include "driver/ln9310.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "util.h"
-#include "timer.h"
-
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-static int power_good;
-static int startup_workaround_required;
-
-int ln9310_power_good(void)
-{
-	return power_good;
-}
-
-static inline int raw_read8(int offset, int *value)
-{
-	return i2c_read8(ln9310_config.i2c_port,
-			 ln9310_config.i2c_addr_flags,
-			 offset,
-			 value);
-}
-
-static inline int field_update8(int offset, int mask, int value)
-{
-	/* Clear mask and then set value in i2c reg value */
-	return i2c_field_update8(ln9310_config.i2c_port,
-				 ln9310_config.i2c_addr_flags,
-				 offset,
-				 mask,
-				 value);
-}
-
-static void ln9310_irq_deferred(void)
-{
-	int status, val, pg_2to1, pg_3to1;
-
-	status = raw_read8(LN9310_REG_INT1, &val);
-	if (status) {
-		CPRINTS("LN9310 reading INT1 failed");
-		return;
-	}
-
-	CPRINTS("LN9310 received interrupt: 0x%x", val);
-	/* Don't care other interrupts except mode change */
-	if (!(val & LN9310_INT1_MODE))
-		return;
-
-	/* Check if the device is active in 2:1 or 3:1 switching mode */
-	status = raw_read8(LN9310_REG_SYS_STS, &val);
-	if (status) {
-		CPRINTS("LN9310 reading SYS_STS failed");
-		return;
-	}
-	CPRINTS("LN9310 system status: 0x%x", val);
-
-	/* Either 2:1 or 3:1 mode active is treated as PGOOD */
-	pg_2to1 = !!(val & LN9310_SYS_SWITCHING21_ACTIVE);
-	pg_3to1 = !!(val & LN9310_SYS_SWITCHING31_ACTIVE);
-	power_good = pg_2to1 || pg_3to1;
-}
-DECLARE_DEFERRED(ln9310_irq_deferred);
-
-void ln9310_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&ln9310_irq_deferred_data, 0);
-}
-
-static int is_battery_gt_10v(bool *out)
-{
-	int status, val;
-
-	CPRINTS("LN9310 checking input voltage, threshold=10V");
-	/*
-	 * Turn on INFET_OUT_SWITCH_OK comparator;
-	 * configure INFET_OUT_SWITCH_OK to 10V.
-	 */
-	status = field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V);
-	if (status != EC_SUCCESS)
-		return status;
-
-	/* Read INFET_OUT_SWITCH_OK comparator */
-	status = raw_read8(LN9310_REG_BC_STS_B, &val);
-	if (status != EC_SUCCESS) {
-		CPRINTS("LN9310 reading BC_STS_B failed");
-		return status;
-	}
-	CPRINTS("LN9310 BC_STS_B: 0x%x", val);
-
-	/*
-	 * If INFET_OUT_SWITCH_OK=0, VIN < 10V
-	 * If INFET_OUT_SWITCH_OK=1, VIN > 10V
-	 */
-	*out = !!(val & LN9310_BC_STS_B_INFET_OUT_SWITCH_OK);
-	CPRINTS("LN9310 battery %s 10V", (*out) ? ">" : "<");
-
-	/* Turn off INFET_OUT_SWITCH_OK comparator */
-	status = field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF);
-
-	return status;
-}
-
-static int ln9310_reset_detected(void)
-{
-	/*
-	 * Check LN9310_REG_LION_CTRL to see if it has been reset to 0x0.
-	 * ln9310_init() and all other functions will set this register
-	 * to a non-zero value so it should only become 0 again if LN9310
-	 * is reset.
-	 */
-	int val, status, reset_detected;
-
-	status = raw_read8(LN9310_REG_LION_CTRL, &val);
-	if (status) {
-		CPRINTS("LN9310 reading LN9310_REG_LION_CTRL failed");
-		/* If read fails, safest to assume reset has occurred */
-		return 1;
-	}
-	reset_detected = (val == 0x0);
-	if (reset_detected) {
-		CPRINTS("LN9310 was reset (possibly in error)");
-	}
-	return reset_detected;
-}
-
-static int ln9310_update_startup_seq(void)
-{
-	int rc;
-
-	CPRINTS("LN9310 update startup sequence");
-
-	/*
-	 * Startup sequence instruction swap to hold Cfly
-	 * bottom plate low during startup
-	 */
-	rc = field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
-			   LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
-
-	rc |= field_update8(LN9310_REG_SWAP_CTRL_0, 0xff, 0x52);
-
-	rc |= field_update8(LN9310_REG_SWAP_CTRL_1, 0xff, 0x54);
-
-	rc |= field_update8(LN9310_REG_SWAP_CTRL_2, 0xff, 0xCC);
-
-	rc |= field_update8(LN9310_REG_SWAP_CTRL_3, 0xff, 0x02);
-
-	/* Startup sequence settings */
-	rc |= field_update8(
-		LN9310_REG_CFG_4,
-		LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK |
-			LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK |
-			LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK,
-		LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON |
-			LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF |
-			LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST);
-
-	/* SW4 before BSTH_BSTL */
-	rc |= field_update8(LN9310_REG_SPARE_0,
-			    LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK,
-			    LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON);
-
-	rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
-			    LN9310_LION_CTRL_LOCK);
-
-	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-static int ln9310_init_3to1(void)
-{
-	int rc;
-
-	CPRINTS("LN9310 init (3:1 operation)");
-
-	/* Enable track protection and SC_OUT configs for 3:1 switching */
-	rc = field_update8(LN9310_REG_MODE_CHANGE_CFG,
-			   LN9310_MODE_TM_TRACK_MASK |
-				   LN9310_MODE_TM_SC_OUT_PRECHG_MASK |
-				   LN9310_MODE_TM_VIN_OV_CFG_MASK,
-			   LN9310_MODE_TM_TRACK_SWITCH31 |
-				   LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 |
-				   LN9310_MODE_TM_VIN_OV_CFG_3S);
-
-	/* Enable 3:1 operation mode */
-	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK,
-			    LN9310_PWR_OP_MODE_SWITCH31);
-
-	/* 3S lower bound delta configurations */
-	rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK,
-			    LN9310_LB_DELTA_3S);
-
-	/*
-	 * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value
-	 * accidentally. Override it to 0. This may not need.
-	 */
-	rc |= field_update8(LN9310_REG_SYS_CTRL, 0xff, 0);
-
-	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-static int ln9310_init_2to1(void)
-{
-	int rc;
-	bool battery_gt_10v;
-
-	CPRINTS("LN9310 init (2:1 operation)");
-
-	rc = is_battery_gt_10v(&battery_gt_10v);
-	if (rc != EC_SUCCESS || battery_gt_10v) {
-		CPRINTS("LN9310 init stop. Input voltage is too high.");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable track protection and SC_OUT configs for 2:1 switching */
-	rc = field_update8(LN9310_REG_MODE_CHANGE_CFG,
-			   LN9310_MODE_TM_TRACK_MASK |
-				   LN9310_MODE_TM_SC_OUT_PRECHG_MASK,
-			   LN9310_MODE_TM_TRACK_SWITCH21 |
-				   LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21);
-
-	/* Enable 2:1 operation mode */
-	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK,
-			   LN9310_PWR_OP_MODE_SWITCH21);
-
-	/* 2S lower bound delta configurations */
-	rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK,
-			   LN9310_LB_DELTA_2S);
-
-	/*
-	 * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value
-	 * accidentally. Override it to 0. This may not need.
-	 */
-	rc |= field_update8(LN9310_REG_SYS_CTRL, 0xff, 0);
-
-	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-static int ln9310_update_infet(void)
-{
-	int rc;
-
-	CPRINTS("LN9310 update infet configuration");
-
-	rc = field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
-			   LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
-
-	/* Update Infet register settings */
-	rc |= field_update8(LN9310_REG_CFG_5, LN9310_CFG_5_INGATE_PD_EN_MASK,
-			   LN9310_CFG_5_INGATE_PD_EN_OFF);
-
-	rc |= field_update8(LN9310_REG_CFG_5,
-			   LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK,
-			   LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST);
-
-	/* enable automatic infet control */
-	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_INFET_AUTO_MODE_MASK,
-			   LN9310_PWR_INFET_AUTO_MODE_ON);
-
-	/* disable LS_HELPER during IDLE by setting MSK bit high  */
-	rc |= field_update8(LN9310_REG_CFG_0,
-			   LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK,
-			   LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON);
-
-	rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
-			   LN9310_LION_CTRL_LOCK);
-
-	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-static int ln9310_precharge_cfly(uint64_t *precharge_timeout)
-{
-	int status = 0;
-	CPRINTS("LN9310 precharge cfly");
-
-	/* Unlock registers and enable test mode */
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
-
-	/* disable test mode overrides */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
-
-	/* Configure test mode target values for precharge ckts.  */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON);
-
-	/* Force SCOUT precharge/predischarge overrides */
-	status |= field_update8(LN9310_REG_TEST_MODE_CTRL,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON |
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON);
-
-	/* Force enable CFLY precharge overrides */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON);
-
-	/* delay long enough to ensure CFLY has time to fully precharge */
-	usleep(LN9310_CFLY_PRECHARGE_DELAY);
-
-	/* locking and leaving test mode will stop CFLY precharge */
-	*precharge_timeout = get_time().val + LN9310_CFLY_PRECHARGE_TIMEOUT;
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_LOCK);
-
-	return status;
-}
-
-static int ln9310_precharge_cfly_reset(void)
-{
-	int status = 0;
-	CPRINTS("LN9310 precharge cfly reset");
-
-	/* set known initial state for config bits related to cfly precharge */
-	status |= field_update8(LN9310_REG_LION_CTRL,
-		LN9310_LION_CTRL_MASK,
-		LN9310_LION_CTRL_UNLOCK);
-
-	/* Force off SCOUT precharge/predischarge overrides */
-	status |= field_update8(LN9310_REG_TEST_MODE_CTRL,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF |
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF);
-
-	/* disable test mode overrides */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
-
-	/* disable CFLY and SC_OUT precharge control  */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF);
-
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_LOCK);
-
-	return status;
-}
-
-int ln9310_init(void)
-{
-	int status, val, chip_revision;
-	enum battery_cell_type batt;
-
-	/* Make sure initial state of LN9310 is STANDBY (i.e. output is off)  */
-	field_update8(LN9310_REG_STARTUP_CTRL,
-				LN9310_STARTUP_STANDBY_EN,
-				1);
-
-	/*
-	 * LN9310 software startup is only required for earlier silicon revs.
-	 * LN9310 hardware revisions after LN9310_BC_STS_C_CHIP_REV_FIXED
-	 * should not use the software startup sequence.
-	 */
-	status = raw_read8(LN9310_REG_BC_STS_C, &val);
-	if (status != EC_SUCCESS) {
-		CPRINTS("LN9310 reading BC_STS_C failed: %d", status);
-		return status;
-	}
-	chip_revision = val & LN9310_BC_STS_C_CHIP_REV_MASK;
-	startup_workaround_required = chip_revision < LN9310_BC_STS_C_CHIP_REV_FIXED;
-
-	/* Update INFET configuration  */
-	status = ln9310_update_infet();
-
-	if (status != EC_SUCCESS)
-		return status;
-
-	/*
-	 * Set OPERATION_MODE update method
-	 *   - OP_MODE_MANUAL_UPDATE = 0
-	 *   - OP_MODE_SELF_SYNC_EN  = 1
-	 */
-	field_update8(LN9310_REG_PWR_CTRL,
-		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK,
-		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF);
-
-	field_update8(LN9310_REG_TIMER_CTRL,
-		      LN9310_TIMER_OP_SELF_SYNC_EN_MASK,
-		      LN9310_TIMER_OP_SELF_SYNC_EN_ON);
-
-	/*
-	 * Use VIN for VDR, not EXT_5V. The following usleep will give
-	 * circuit time to settle.
-	 */
-	field_update8(LN9310_REG_STARTUP_CTRL,
-		      LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR,
-		      0);
-
-	field_update8(LN9310_REG_LB_CTRL,
-		      LN9310_LB_MIN_FREQ_EN,
-		      LN9310_LB_MIN_FREQ_EN);
-
-	/* Set minimum switching frequency to 25 kHz */
-	field_update8(LN9310_REG_SPARE_0,
-		      LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK,
-		      LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON);
-
-	usleep(LN9310_CDC_DELAY);
-	CPRINTS("LN9310 OP_MODE Update method: Self-sync");
-
-	if (startup_workaround_required) {
-		/* Update Startup sequence */
-		status = ln9310_update_startup_seq();
-		if (status != EC_SUCCESS)
-			return status;
-	}
-
-	batt = board_get_battery_cell_type();
-	if (batt == BATTERY_CELL_TYPE_3S) {
-		status = ln9310_init_3to1();
-	} else if (batt == BATTERY_CELL_TYPE_2S) {
-		status = ln9310_init_2to1();
-	} else {
-		CPRINTS("LN9310 not supported battery type: %d", batt);
-		return EC_ERROR_INVAL;
-	}
-
-	if (status != EC_SUCCESS)
-		return status;
-
-	/* Unmask the MODE change interrupt */
-	field_update8(LN9310_REG_INT1_MSK,
-			LN9310_INT1_MODE,
-			0);
-	return EC_SUCCESS;
-}
-
-void ln9310_software_enable(int enable)
-{
-	int status, val, retry_count;
-	uint64_t precharge_timeout;
-	bool ln9310_init_completed = false;
-
-	/*
-	 * LN9310 startup requires (nEN=0 AND STANDBY_EN=0) where nEN is a pin
-	 * and STANDBY_EN is a register bit. Previous EC firmware set
-	 * STANDBY_EN=1 in ln9310_init and toggled nEN to startup/shutdown. This
-	 * function implements an alternate software (i.e. controlled by EC
-	 * through I2C commands) startup sequence so one option is to set nEN=1
-	 * and just used ln9310_software_enable to startup/shutdown.
-	 * ln9310_software_enable can also be used in conjunction w/ the nEN pin
-	 * (in case nEN pin is desired as visible signal ) as follows:
-	 *
-	 * Initial battery insertion:
-	 * nEN=1
-	 * ln9310_init() - initial condition is STANDBY_EN=1
-	 *
-	 * Power up LN9310:
-	 * nEN=0 - STANDBY_EN should be 1 so this doesn't trigger startup
-	 * ln9310_software_enable(1) - triggers alternate software-based startup
-	 *
-	 * Power down LN9310:
-	 * nEN=1 - shutdown LN9310 (shutdown seq. does not require modification)
-	 * ln9310_software_enable(0) - reset LN9310 register to state necessary
-	 *                             for subsequent startups
-	 */
-	if (ln9310_reset_detected())
-		ln9310_init();
-
-	/* Dummy clear all interrupts */
-	status = raw_read8(LN9310_REG_INT1, &val);
-	if (status) {
-		CPRINTS("LN9310 reading INT1 failed");
-		return;
-	}
-	CPRINTS("LN9310 cleared interrupts: 0x%x", val);
-
-	if (startup_workaround_required) {
-		if (enable) {
-			/*
-			* Software modification of LN9310 startup sequence w/ retry
-			* loop.
-			*
-			* (1) Clear interrupts
-			* (2) Precharge Cfly w/ overrides of internal LN9310 signals
-			* (3) disable overrides -> stop precharging Cfly
-			* (4.1) if < 100 ms elapsed since (2) -> trigger LN9310 internal
-			*                                        startup seq. 
-			* (4.2) else -> abort and optionally retry from step 2
-			*/
-			retry_count = 0;
-			while (!ln9310_init_completed && retry_count < LN9310_INIT_RETRY_COUNT) {
-				/* Precharge CFLY before starting up */
-				status = ln9310_precharge_cfly(&precharge_timeout);
-				if (status != EC_SUCCESS) {
-					CPRINTS("LN9310 failed to run Cfly precharge sequence");
-					status = ln9310_precharge_cfly_reset();
-					retry_count++;
-					continue;
-				}
-
-				/*
-				* Only start the SC if the cfly precharge
-				* hasn't timed out (i.e. ended too long ago)
-				*/
-				if (get_time().val < precharge_timeout) {
-					/* Clear the STANDBY_EN bit to enable the SC */
-					field_update8(LN9310_REG_STARTUP_CTRL,
-							LN9310_STARTUP_STANDBY_EN,
-							0);
-					if (get_time().val > precharge_timeout ) {
-						/*
-						* if timed out during previous I2C command, abort 
-						* startup attempt
-						*/
-						field_update8(LN9310_REG_STARTUP_CTRL,
-							LN9310_STARTUP_STANDBY_EN,
-							1);
-					} else {
-						/* all other paths should reattempt startup  */
-						ln9310_init_completed = true;
-					}
-				}
-				/* Reset to known state for config bits related to cfly precharge */
-				ln9310_precharge_cfly_reset();
-				retry_count++;
-			}
-
-			if (!ln9310_init_completed) {
-				CPRINTS("LN9310 failed to start after %d retry attempts",
-						retry_count);
-			}
-		} else {
-			/*
-			* Internal LN9310 shutdown sequence is ok as is, so just reset
-			* the state to prepare for subsequent startup sequences.
-			*
-			* (1) set STANDBY_EN=1 to be sure the part turns off even if nEN=0
-			* (2) reset cfly precharge related registers to known initial state
-			*/
-			field_update8(LN9310_REG_STARTUP_CTRL,
-					LN9310_STARTUP_STANDBY_EN,
-					1);
-
-			ln9310_precharge_cfly_reset();
-		}
-	} else {
-		/*
-		* for newer LN9310 revsisions, the startup workaround is not required
-		* so the STANDBY_EN bit can just be set directly
-		*/
-		field_update8(LN9310_REG_STARTUP_CTRL,
-					LN9310_STARTUP_STANDBY_EN,
-					!enable);
-	}
-	return;
-}
\ No newline at end of file
diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c
deleted file mode 100644
index ad1eba7ad0..0000000000
--- a/driver/mag_bmm150.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * BMM150 compass behind a BMI160
- */
-
-#include "accelgyro.h"
-#include "common.h"
-#include "console.h"
-#include "driver/mag_bmm150.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#ifdef CONFIG_MAG_BMI_BMM150
-#include "driver/accelgyro_bmi_common.h"
-#define raw_mag_read8 bmi160_sec_raw_read8
-#define raw_mag_write8 bmi160_sec_raw_write8
-#else
-#error "Not implemented"
-#endif
-
-
-#define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
-
-/****************************************************************************
-* Copyright (C) 2011 - 2014 Bosch Sensortec GmbH
-*
-****************************************************************************/
-/***************************************************************************
-* License:
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-*/
-
-#define BMI150_READ_16BIT_COM_REG(store_, addr_) do { \
-	int val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \
-	store_ = val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1, &val); \
-	store_ |= (val << 8); \
-} while (0)
-
-
-int bmm150_init(struct motion_sensor_t *s)
-{
-	int ret;
-	int val;
-	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
-	struct mag_cal_t             *moc = BMM150_CAL(s);
-
-	/* Set the compass from Suspend to Sleep */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_PWR_CTRL, BMM150_PWR_ON);
-	msleep(4);
-	/* Now we can read the device id */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_CHIP_ID, &val);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	if (val != BMM150_CHIP_ID_MAJOR)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Read the private registers for compensation */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REGA_DIG_X1, &val);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-	regs->dig1[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y1, &val);
-	regs->dig1[Y] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_X2, &val);
-	regs->dig2[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y2, &val);
-	regs->dig2[Y] = val;
-
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY1, &val);
-	regs->dig_xy1 = val;
-
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY2, &val);
-	regs->dig_xy2 = val;
-
-	BMI150_READ_16BIT_COM_REG(regs->dig_z1, BMM150_REGA_DIG_Z1_LSB);
-	BMI150_READ_16BIT_COM_REG(regs->dig_z2, BMM150_REGA_DIG_Z2_LSB);
-	BMI150_READ_16BIT_COM_REG(regs->dig_z3, BMM150_REGA_DIG_Z3_LSB);
-	BMI150_READ_16BIT_COM_REG(regs->dig_z4, BMM150_REGA_DIG_Z4_LSB);
-	BMI150_READ_16BIT_COM_REG(regs->dig_xyz1, BMM150_REGA_DIG_XYZ1_LSB);
-
-
-	/* Set the repetition in "Regular Preset" */
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPXY, BMM150_REP(SPECIAL, XY));
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPZ, BMM150_REP(SPECIAL, Z));
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPXY, &val);
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPZ, &val);
-	/*
-	 * Set the compass forced mode, to sleep after each measure.
-	 */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_OP_CTRL,
-			     BMM150_OP_MODE_FORCED << BMM150_OP_MODE_OFFSET);
-
-	init_mag_cal(moc);
-	moc->radius = 0.0f;
-	return ret;
-}
-
-void bmm150_temp_compensate_xy(const struct motion_sensor_t *s,
-			       intv3_t raw,
-			       intv3_t comp,
-			       int r)
-{
-	int inter, axis;
-	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
-	if (r == 0)
-		inter = 0;
-	else
-		inter = ((int)regs->dig_xyz1 << 14) / r - BIT(14);
-
-	for (axis = X; axis <= Y; axis++) {
-		if (raw[axis] == BMM150_FLIP_OVERFLOW_ADCVAL) {
-			comp[axis] = BMM150_OVERFLOW_OUTPUT;
-			continue;
-		}
-		/*
-		 * The formula is, using 4 LSB for precision:
-		 * (mdata_x * ((((dig_xy2 * i^2 / 268435456) +
-		 *              i * dig_xy1) / 16384) + 256) *
-		 *  (dig2 + 160)) / 8192 + dig1 * 8.0f
-		 * To prevent precision loss, we calculate at << 12:
-		 * 1 / 268435456 = 1 >> 28 = 1 >> (7 + 9 + 12)
-		 * 1 / 16384 = 1 >> (-7 + 9 + 12)
-		 * 256 = 1 << (20 - 12)
-		 */
-		comp[axis] = (int)regs->dig_xy2 * ((inter * inter) >> 7);
-		comp[axis] += inter * ((int)regs->dig_xy1 << 7);
-		comp[axis] >>= 9;
-		comp[axis] += 1 << (8 + 12);
-		comp[axis] *= (int)regs->dig2[axis] + 160;
-		comp[axis] >>= 12;
-		comp[axis] *= raw[axis];
-		comp[axis] >>= 13;
-		comp[axis] += (int)regs->dig1[axis] << 3;
-	}
-}
-
-void bmm150_temp_compensate_z(const struct motion_sensor_t *s,
-			      intv3_t raw,
-			      intv3_t comp,
-			      int r)
-{
-	int dividend, divisor;
-	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
-
-	if (raw[Z] == BMM150_HALL_OVERFLOW_ADCVAL) {
-		comp[Z] = BMM150_OVERFLOW_OUTPUT;
-		return;
-	}
-	/*
-	 * The formula is
-	 * ((z - dig_z4) * 131072 - dig_z3 * (r - dig_xyz1)) /
-	 * ((dig_z2 + dig_z1 * r / 32768) * 4);
-	 *
-	 * We spread 4 so we multiply by 131072 / 4 == BIT(15) only.
-	 */
-	dividend = (raw[Z] - (int)regs->dig_z4) << 15;
-	dividend -= (regs->dig_z3 * (r - (int)regs->dig_xyz1)) >> 2;
-	/* add BIT(15) to round to next integer. */
-	divisor = (int)regs->dig_z1 * (r << 1) + BIT(15);
-	divisor >>= 16;
-	divisor += (int)regs->dig_z2;
-	comp[Z] = dividend / divisor;
-	if (comp[Z] > BIT(15) || comp[Z] < -(BIT(15)))
-		comp[Z] = BMM150_OVERFLOW_OUTPUT;
-}
-
-void bmm150_normalize(const struct motion_sensor_t *s,
-		      intv3_t v,
-		      uint8_t *data)
-{
-	uint16_t r;
-	intv3_t raw;
-	struct mag_cal_t *cal = BMM150_CAL(s);
-
-	/* X and Y are two's complement 13 bits vectors */
-	raw[X] = ((int16_t)(data[0] | (data[1] << 8))) >> 3;
-	raw[Y] = ((int16_t)(data[2] | (data[3] << 8))) >> 3;
-	/* Z are two's complement 15 bits vectors */
-	raw[Z] = ((int16_t)(data[4] | (data[5] << 8))) >> 1;
-
-	/* RHALL value to compensate with - unsigned 14 bits */
-	r = (data[6] | (data[7] << 8)) >> 2;
-
-	bmm150_temp_compensate_xy(s, raw, v, r);
-	bmm150_temp_compensate_z(s, raw, v, r);
-	mag_cal_update(cal, v);
-
-	v[X] += cal->bias[X];
-	v[Y] += cal->bias[Y];
-	v[Z] += cal->bias[Z];
-}
-
-int bmm150_set_offset(const struct motion_sensor_t *s,
-		      const intv3_t offset)
-{
-	struct mag_cal_t *cal = BMM150_CAL(s);
-	cal->bias[X] = offset[X];
-	cal->bias[Y] = offset[Y];
-	cal->bias[Z] = offset[Z];
-	return EC_SUCCESS;
-}
-
-int bmm150_get_offset(const struct motion_sensor_t *s,
-		      intv3_t offset)
-{
-	struct mag_cal_t *cal = BMM150_CAL(s);
-	offset[X] = cal->bias[X];
-	offset[Y] = cal->bias[Y];
-	offset[Z] = cal->bias[Z];
-	return EC_SUCCESS;
-}
diff --git a/driver/mcdp28x0.c b/driver/mcdp28x0.c
deleted file mode 100644
index bf44a6eaf8..0000000000
--- a/driver/mcdp28x0.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Megachips DisplayPort to HDMI protocol converter / level shifter driver.
- */
-
-#include "config.h"
-#include "console.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "mcdp28x0.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "timer.h"
-#include "usart-stm32f0.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-static uint8_t mcdp_inbuf[MCDP_INBUF_MAX];
-
-#undef MCDP_DEBUG
-
-#ifdef MCDP_DEBUG
-static inline void print_buffer(uint8_t *buf, int cnt)
-{
-	int i;
-	CPRINTF("buf:");
-	for (i = 0; i < cnt; i++) {
-		if (i && !(i % 4))
-			CPRINTF("\n    ");
-		CPRINTF("[%02d]0x%02x ", i, buf[i]);
-	}
-	CPRINTF("\n");
-}
-#else
-static inline void print_buffer(uint8_t *buf, int cnt) {}
-#endif
-
-static struct usart_config const usart_mcdp;
-
-struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(MCDP_INBUF_MAX,
-						      uint8_t,
-						      usart_mcdp.producer,
-						      null_consumer);
-struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(MCDP_OUTBUF_MAX,
-						      uint8_t,
-						      null_producer,
-						      usart_mcdp.consumer);
-
-static struct usart_config const usart_mcdp = USART_CONFIG(CONFIG_MCDP28X0,
-							   usart_rx_interrupt,
-							   usart_tx_interrupt,
-							   115200,
-							   0,
-							   usart_mcdp_rx_queue,
-							   usart_mcdp_tx_queue);
-
-/**
- * Compute checksum.
- *
- * @seed initial value of checksum.
- * @msg message bytes to compute checksum on.
- * @cnt count of message bytes.
- * @return partial checksum.
- */
-static uint8_t compute_checksum(uint8_t seed, const uint8_t *msg, int cnt)
-{
-	int i;
-	uint8_t chksum = seed;
-
-	for (i = 0; i < cnt; i++)
-		chksum += msg[i];
-	return ~chksum + 1;
-}
-
-/**
- * transmit message over serial
- *
- * Packet consists of:
- *   msg[0]     == length of entire packet
- *   msg[1]     == 1st message byte (typically command)
- *   msg[cnt+1] == last message byte
- *   msg[cnt+2] == checksum
- *
- * @msg message bytes
- * @cnt count of message bytes
- * @return zero if success, error code otherwise
- */
-static int tx_serial(const uint8_t *msg, int cnt)
-{
-	uint8_t out = cnt + 2;
-	/* 1st byte (not in msg) is always cnt + 2, so seed chksum with that */
-	uint8_t chksum = compute_checksum(cnt + 2, msg, cnt);
-
-	if (queue_add_unit(&usart_mcdp_tx_queue, &out) != 1)
-		return MCDP_ERROR_TX_CNT;
-
-	if (queue_add_units(&usart_mcdp_tx_queue, msg, cnt) != cnt)
-		return MCDP_ERROR_TX_BODY;
-
-	print_buffer((uint8_t *)msg, cnt);
-
-	if (queue_add_unit(&usart_mcdp_tx_queue, &chksum) != 1)
-		return MCDP_ERROR_TX_CHKSUM;
-
-	return MCDP_SUCCESS;
-}
-
-/**
- * receive message over serial
- *
- * While definitive documentation is lacking its believed the following receive
- * packet is always true.
- *
- * Packet consists of:
- *   msg[0]     == length of entire packet
- *   msg[1]     == 1st message byte (typically command)
- *   msg[cnt+2] == last message byte
- *   msg[cnt+3] == checksum
- *
- * @msg pointer to buffer to read message into
- * @cnt count of message bytes
- * @return zero if success, error code otherwise
- */
-static int rx_serial(uint8_t *msg, int cnt)
-{
-	size_t read;
-	int retry = 2;
-
-	read = queue_remove_units(&usart_mcdp_rx_queue, msg, cnt);
-	while ((read < cnt) && retry) {
-		usleep(100*MSEC);
-		read += queue_remove_units(&usart_mcdp_rx_queue, msg + read,
-					   cnt - read);
-		retry--;
-	}
-
-	print_buffer(msg, cnt);
-
-	/* Some response sizes are dynamic so shrink cnt accordingly. */
-	if (cnt > msg[0])
-		cnt = msg[0];
-
-	if (msg[cnt-1] != compute_checksum(0, msg, cnt-1))
-		return MCDP_ERROR_CHKSUM;
-
-	if (read != cnt) {
-		CPRINTF("rx_serial: read bytes %d != %d cnt\n", read, cnt);
-		return MCDP_ERROR_RX_BYTES;
-	}
-
-	return MCDP_SUCCESS;
-}
-
-static int rx_serial_ack(void)
-{
-	int rv = rx_serial(mcdp_inbuf, 3);
-	if (rv)
-		return rv;
-
-	if (mcdp_inbuf[1] != MCDP_CMD_ACK)
-		return MCDP_ERROR_RX_ACK;
-
-	return rv;
-}
-
-void mcdp_enable(void)
-{
-	usart_init(&usart_mcdp);
-}
-
-void mcdp_disable(void)
-{
-	usart_shutdown(&usart_mcdp);
-}
-
-int mcdp_get_info(struct mcdp_info  *info)
-{
-	const uint8_t msg[2] = {MCDP_CMD_APPSTEST, 0x28};
-	int rv = tx_serial(msg, sizeof(msg));
-
-	if (rv)
-		return rv;
-
-	rv = rx_serial_ack();
-	if (rv)
-		return rv;
-
-	/* chksum is unreliable ... don't check */
-	rx_serial(mcdp_inbuf, MCDP_RSP_LEN(MCDP_LEN_GETINFO));
-
-	memcpy(info, &mcdp_inbuf[2], MCDP_LEN_GETINFO);
-
-	return rv;
-}
-
-#ifdef CONFIG_CMD_MCDP
-static int mcdp_get_dev_id(char *dev, uint8_t dev_id, int dev_cnt)
-{
-	uint8_t msg[2];
-	int rv;
-	msg[0] = MCDP_CMD_GETDEVID;
-	msg[1] = dev_id;
-
-	rv = tx_serial(msg, sizeof(msg));
-	if (rv)
-		return rv;
-
-	rv = rx_serial(mcdp_inbuf, sizeof(mcdp_inbuf));
-	if (rv)
-		return rv;
-
-	memcpy(dev, &mcdp_inbuf[2], mcdp_inbuf[0] - 3);
-	dev[mcdp_inbuf[0] - 3] = '\0';
-	return EC_SUCCESS;
-}
-
-static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv)
-{
-	uint8_t msg[6];
-	char *e;
-	int i;
-	int rv = MCDP_SUCCESS;
-
-	/* setup any appstest params */
-	msg[0] = MCDP_CMD_APPSTESTPARAM;
-	for (i = 0; i < paramc; i++) {
-		uint32_t param = strtoi(paramv[i], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-		msg[1] = i + 1;
-		msg[2] = (param >> 24) & 0xff;
-		msg[3] = (param >> 16) & 0xff;
-		msg[4] = (param >>  8) & 0xff;
-		msg[5] = (param >>  0) & 0xff;
-		rv = tx_serial(msg, sizeof(msg));
-		if (rv)
-			return rv;
-
-		rv = rx_serial_ack();
-		if (rv)
-			return rv;
-	}
-
-	msg[0] = MCDP_CMD_APPSTEST;
-	msg[1] = cmd;
-	rv = tx_serial(msg, 2);
-	if (rv)
-		return rv;
-
-	rv = rx_serial_ack();
-	if (rv)
-		return rv;
-
-	/* magic */
-	rx_serial(mcdp_inbuf, sizeof(mcdp_inbuf));
-	rx_serial(mcdp_inbuf, sizeof(mcdp_inbuf));
-
-	return EC_SUCCESS;
-}
-
-int command_mcdp(int argc, char **argv)
-{
-	int rv = EC_SUCCESS;
-	char *e;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	mcdp_enable();
-	if (!strncasecmp(argv[1], "info", 4)) {
-		struct mcdp_info info;
-		rv = mcdp_get_info(&info);
-		if (!rv)
-			ccprintf("family:%04x chipid:%04x irom:%d.%d.%d "
-				 "fw:%d.%d.%d\n",
-				 MCDP_FAMILY(info.family),
-				 MCDP_CHIPID(info.chipid),
-				 info.irom.major, info.irom.minor,
-				 info.irom.build,
-				 info.fw.major, info.fw.minor, info.fw.build);
-	} else if (!strncasecmp(argv[1], "devid", 4)) {
-		uint8_t dev_id = strtoi(argv[2], &e, 10);
-		char dev[32];
-		if (*e)
-			return EC_ERROR_PARAM2;
-		else
-			rv = mcdp_get_dev_id(dev, dev_id, 32);
-		if (!rv)
-			ccprintf("devid[%d] = %s\n", dev_id, dev);
-	} else if (!strncasecmp(argv[1], "appstest", 4)) {
-		uint8_t cmd = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		else
-			rv = mcdp_appstest(cmd, argc - 3, &argv[3]);
-		if (!rv)
-			ccprintf("appstest[%d] completed\n", cmd);
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	mcdp_disable();
-	if (rv)
-		ccprintf("mcdp_error:%d\n", rv);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(mcdp, command_mcdp,
-			"info|devid <id>|appstest <cmd> [<params>]",
-			"USB PD");
-#endif /* CONFIG_CMD_MCDP */
diff --git a/driver/mcdp28x0.h b/driver/mcdp28x0.h
deleted file mode 100644
index 4352a3899e..0000000000
--- a/driver/mcdp28x0.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Megachips DisplayPort to HDMI protocol converter / level shifter driver.
- */
-
-#ifndef __CROS_EC_MCDP28X0_H
-#define __CROS_EC_MCDP28X0_H
-
-#define MCDP_OUTBUF_MAX 16
-#define MCDP_INBUF_MAX 16
-
-#define MCDP_CMD_GETINFO       0x40
-#define MCDP_CMD_GETDEVID      0x30
-#define MCDP_CMD_APPSTEST      0x12
-#define MCDP_CMD_APPSTESTPARAM 0x11
-#define MCDP_CMD_ACK           0x0c
-
-/* packet header (2 bytes: length + cmd) + data + footer (1byte: checksum) */
-#define MCDP_RSP_LEN(len) (len + 3)
-#define MCDP_LEN_GETINFO 12
-
-/* List of common error codes that can be returned */
-enum mcdp_error_list {
-	MCDP_SUCCESS = 0,
-	MCDP_ERROR_TX_CNT,
-	MCDP_ERROR_TX_BODY,
-	MCDP_ERROR_TX_CHKSUM,
-	MCDP_ERROR_CHKSUM,
-	MCDP_ERROR_RX_BYTES,
-	MCDP_ERROR_RX_ACK,
-};
-
-/**
- * Enable mcdp driver.
- */
-void mcdp_enable(void);
-
-/**
- * Disable mcdp driver.
- */
-void mcdp_disable(void);
-
-/**
- * get get information command from mcdp.
- *
- * @info pointer to mcdp_info structure
- * @return zero if success, error code otherwise.
- */
-int mcdp_get_info(struct mcdp_info  *info);
-
-#endif
diff --git a/driver/mp2964.c b/driver/mp2964.c
deleted file mode 100644
index 21a23a8f4c..0000000000
--- a/driver/mp2964.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Driver for tuning the MP2964 IMVP8 - IMVP9.1 parameters */
-
-#include "console.h"
-#include "i2c.h"
-#include "mp2964.h"
-#include "timer.h"
-#include "util.h"
-
-#define MP2964_STARTUP_WAIT_US		(50 * MSEC)
-#define MP2964_STORE_WAIT_US		(300 * MSEC)
-#define MP2964_RESTORE_WAIT_US		(2 * MSEC)
-
-enum reg_page {
-	REG_PAGE_0,
-	REG_PAGE_1,
-	REG_PAGE_COUNT
-};
-
-static int mp2964_write8(uint8_t reg, uint8_t value)
-{
-	const uint8_t tx[2] = { reg, value };
-
-	return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				 tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
-}
-
-static void mp2964_read16(uint8_t reg, uint16_t *value)
-{
-	const uint8_t tx[1] = { reg };
-	uint8_t rx[2];
-
-	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-			  tx, sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE);
-	*value = (rx[1] << 8) | rx[0];
-}
-
-static void mp2964_write16(uint8_t reg, uint16_t value)
-{
-	const uint8_t tx[3] = { reg, value & 0xff, value >> 8 };
-
-	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-			  tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
-}
-
-static int mp2964_select_page(enum reg_page page)
-{
-	int status;
-
-	if (page >= REG_PAGE_COUNT)
-		return EC_ERROR_INVAL;
-
-	status = mp2964_write8(MP2964_PAGE, page);
-	if (status != EC_SUCCESS) {
-		ccprintf("%s: could not select page 0x%02x, error %d\n",
-			 __func__, page, status);
-	}
-	return status;
-}
-
-static void mp2964_write_vec16(const struct mp2964_reg_val *init_list,
-			       int count, int *delta)
-{
-	const struct mp2964_reg_val *reg_val;
-	uint16_t outval;
-	int i;
-
-	reg_val = init_list;
-	for (i = 0; i < count; ++i, ++reg_val) {
-		mp2964_read16(reg_val->reg, &outval);
-		if (outval == reg_val->val) {
-			ccprintf("mp2964: reg 0x%02x already 0x%04x\n",
-				 reg_val->reg, outval);
-			continue;
-		}
-		ccprintf("mp2964: tuning reg 0x%02x from 0x%04x to 0x%04x\n",
-			 reg_val->reg, outval, reg_val->val);
-		mp2964_write16(reg_val->reg, reg_val->val);
-		*delta += 1;
-	}
-}
-
-static int mp2964_store_user_all(void)
-{
-	const uint8_t wr = MP2964_STORE_USER_ALL;
-	const uint8_t rd = MP2964_RESTORE_USER_ALL;
-	int status;
-
-	ccprintf("%s: updating persistent settings\n", __func__);
-
-	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				   &wr, sizeof(wr), NULL, 0, I2C_XFER_SINGLE);
-	if (status != EC_SUCCESS)
-		return status;
-
-	usleep(MP2964_STORE_WAIT_US);
-
-	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				   &rd, sizeof(rd), NULL, 0, I2C_XFER_SINGLE);
-	if (status != EC_SUCCESS)
-		return status;
-
-	usleep(MP2964_RESTORE_WAIT_US);
-
-	return EC_SUCCESS;
-}
-
-static void mp2964_patch_rail(enum reg_page page,
-			      const struct mp2964_reg_val *page_vals,
-			      int count,
-			      int *delta)
-{
-	if (mp2964_select_page(page) != EC_SUCCESS)
-		return;
-	mp2964_write_vec16(page_vals, count, delta);
-}
-
-int mp2964_tune(const struct mp2964_reg_val *rail_a, int count_a,
-		const struct mp2964_reg_val *rail_b, int count_b)
-{
-	int tries = 2;
-	int delta;
-
-	udelay(MP2964_STARTUP_WAIT_US);
-
-	i2c_lock(I2C_PORT_MP2964, 1);
-
-	do {
-		int status;
-
-		delta = 0;
-		mp2964_patch_rail(REG_PAGE_0, rail_a, count_a, &delta);
-		mp2964_patch_rail(REG_PAGE_1, rail_b, count_b, &delta);
-		if (delta == 0)
-			break;
-
-		status = mp2964_store_user_all();
-		if (status != EC_SUCCESS)
-			ccprintf("%s: STORE_USER_ALL failed\n", __func__);
-	} while (--tries > 0);
-
-	i2c_lock(I2C_PORT_MP2964, 0);
-
-	if (delta)
-		return EC_ERROR_UNKNOWN;
-	else
-		return EC_SUCCESS;
-}
diff --git a/driver/mp2964.h b/driver/mp2964.h
deleted file mode 100644
index 8c0339c06e..0000000000
--- a/driver/mp2964.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PMIC_MP2964_H
-#define __CROS_EC_PMIC_MP2964_H
-
-#define MP2964_PAGE			0x00
-#define MP2964_STORE_USER_ALL		0x15
-#define MP2964_RESTORE_USER_ALL		0x16
-#define MP2964_MFR_ALT_SET		0x3f
-
-struct mp2964_reg_val {
-	uint8_t reg;
-	uint16_t val;
-};
-
-int mp2964_tune(const struct mp2964_reg_val *page0, int count0,
-		const struct mp2964_reg_val *page1, int count1);
-
-#endif /* __CROS_EC_PMIC_MP2964_H */
diff --git a/driver/mp4245.c b/driver/mp4245.c
deleted file mode 100644
index 2b38e5c9e9..0000000000
--- a/driver/mp4245.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MPS MP4245 Buck-Boost converter driver. */
-
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "mp4245.h"
-#include "util.h"
-
-
-static int mp4245_reg16_write(int offset, int data)
-{
-	return i2c_write16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, offset,
-			   data);
-}
-
-int mp4245_set_voltage_out(int desired_mv)
-{
-	int vout;
-
-	/*
-	 * For a desired voltage output Vdes, Vout = Vdes * 1024. This means
-	 * there are 10 fractional and 6 integer bits. Vdes is stored in in mV
-	 * so this scaling to mV must also be accounted for.
-	 *
-	 * VOUT_COMMAND = (Vdes (mV) * 1024 / 1000) / 1024
-	 */
-	vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1))
-		/ MP4245_VOUT_1V;
-
-	return mp4245_reg16_write(MP4245_CMD_VOUT_COMMAND, vout);
-}
-
-int mp4245_set_current_lim(int desired_ma)
-{
-	int limit;
-
-	/* Current limit is stored as number of 50 mA steps */
-	limit = (desired_ma + (MP4245_ILIM_STEP_MA / 2)) / MP4245_ILIM_STEP_MA;
-
-	return mp4245_reg16_write(MP4245_CMD_MFR_CURRENT_LIM, limit);
-}
-
-int mp4245_votlage_out_enable(int enable)
-{
-	int cmd_val = enable ? MP4245_CMD_OPERATION_ON : 0;
-
-	return i2c_write8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-			MP4245_CMD_OPERATION, cmd_val);
-}
-
-int mp3245_get_vbus(int *mv, int *ma)
-{
-	int vbus = 0;
-	int ibus = 0;
-	int rv;
-
-	/* Get Vbus/Ibus raw measurements */
-	rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_READ_VOUT, &vbus);
-	rv |= i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_READ_IOUT, &ibus);
-
-	if (rv == EC_SUCCESS) {
-		/* Convert Vbus/Ibus to mV/mA */
-		vbus = MP4245_VOUT_TO_MV(vbus);
-		ibus = MP4245_IOUT_TO_MA(ibus);
-	}
-
-	*mv = vbus;
-	*ma = ibus;
-
-	return rv;
-}
-
-struct mp4245_info {
-	uint8_t cmd;
-	uint8_t len;
-};
-
-static struct mp4245_info  mp4245_cmds[] = {
-	{MP4245_CMD_OPERATION,          1},
-	{MP4245_CMD_CLEAR_FAULTS,       1},
-	{MP4245_CMD_WRITE_PROTECT,      1},
-	{MP4245_CMD_STORE_USER_ALL,     1},
-	{MP4245_CMD_RESTORE_USER_ALL,   1},
-	{MP4245_CMD_VOUT_MODE,          1},
-	{MP4245_CMD_VOUT_COMMAND,       2},
-	{MP4245_CMD_VOUT_SCALE_LOOP,    2},
-	{MP4245_CMD_STATUS_BYTE,        1},
-	{MP4245_CMD_STATUS_WORD,        2},
-	{MP4245_CMD_STATUS_VOUT,        1},
-	{MP4245_CMD_STATUS_INPUT,       1},
-	{MP4245_CMD_STATUS_TEMP,        1},
-	{MP4245_CMD_STATUS_CML,         1},
-	{MP4245_CMD_READ_VIN,           2},
-	{MP4245_CMD_READ_VOUT,          2},
-	{MP4245_CMD_READ_IOUT,          2},
-	{MP4245_CMD_READ_TEMP,          2},
-	{MP4245_CMD_MFR_MODE_CTRL,      1},
-	{MP4245_CMD_MFR_CURRENT_LIM,    1},
-	{MP4245_CMD_MFR_LINE_DROP,      1},
-	{MP4245_CMD_MFR_OT_FAULT_LIM,   1},
-	{MP4245_CMD_MFR_OT_WARN_LIM,    1},
-	{MP4245_CMD_MFR_CRC_ERROR,      1},
-	{MP4245_CMD_MFF_MTP_CFG_CODE,   1},
-	{MP4245_CMD_MFR_MTP_REV_NUM,    1},
-	{MP4245_CMD_MFR_STATUS_MASK,    1},
-};
-
-static void mp4245_dump_reg(void)
-{
-	int i;
-	int val;
-	int rv;
-
-	for (i = 0; i < ARRAY_SIZE(mp4245_cmds); i++) {
-		if (mp4245_cmds[i].len == 1) {
-			rv = i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-				       mp4245_cmds[i].cmd, &val);
-		} else {
-			rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-				       mp4245_cmds[i].cmd, &val);
-		}
-
-		if (!rv)
-			ccprintf("[%02x]:\t%04x\n", mp4245_cmds[i].cmd, val);
-	}
-}
-
-void mp4245_get_status(void)
-{
-	int status;
-	int on;
-	int vbus;
-	int ibus;
-	int ilim;
-	int vout;
-
-	/* Get Operation register */
-	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_OPERATION, &on);
-	/* Vbus on/off is bit 7 */
-	on >>= 7;
-
-	/* Get status word */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_STATUS_WORD, &status);
-
-	/* Get Vbus measurement */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_READ_VOUT, &vbus);
-	vbus = MP4245_VOUT_TO_MV(vbus);
-
-	/* Get Ibus measurement */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_READ_IOUT, &ibus);
-	ibus = MP4245_IOUT_TO_MA(ibus);
-
-	/* Get Vout command (sets Vbus level) */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_VOUT_COMMAND, &vout);
-	vout = MP4245_VOUT_TO_MV(vout);
-
-	/* Get Input current limit */
-	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_MFR_CURRENT_LIM, &ilim);
-	ilim *= MP4245_ILIM_STEP_MA;
-
-	ccprintf("mp4245 Vbus %s:\n", on ? "On" : "Off");
-	ccprintf("\tstatus = 0x%04x\n", status);
-	ccprintf("\tVout   = %d mV, Vbus = %d mV\n", vout, vbus);
-	ccprintf("\tIlim   = %d mA, Ibus = %d mA\n", ilim, ibus);
-}
-
-static int command_mp4245(int argc, char **argv)
-{
-	char *e;
-	int val;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (!strcasecmp(argv[1], "info")) {
-		mp4245_get_status();
-	} else if (!strcasecmp(argv[1], "dump")) {
-		mp4245_dump_reg();
-	} else if (!strcasecmp(argv[1], "vbus")) {
-		if (argc < 3)
-			return EC_ERROR_PARAM_COUNT;
-		val = strtoi(argv[2], &e, 10);
-		/* If value out of bounds, turn off */
-		if (val < 0 || val > 20) {
-			return EC_ERROR_PARAM2;
-		}
-		if (val == 0) {
-			mp4245_votlage_out_enable(0);
-		} else {
-			mp4245_set_voltage_out(val * 1000);
-			mp4245_votlage_out_enable(1);
-		}
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245,
-			"<info|dump|vbus|ilim>",
-			"Turn on/off|set vbus.");
-
diff --git a/driver/mp4245.h b/driver/mp4245.h
deleted file mode 100644
index b453ad2076..0000000000
--- a/driver/mp4245.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* MPS MP4245 Buck-Boost converter driver definitions */
-
-/* I2C addresses */
-#define MP4245_I2C_ADDR_0_FLAGS 0x61  /* R1 -> GND */
-#define MP4245_I2C_ADDR_1_FLAGS 0x62  /* R1 -> 15.0k */
-#define MP4245_I2C_ADDR_2_FLAGS 0x63  /* R1 -> 25.5k */
-#define MP4245_I2C_ADDR_3_FLAGS 0x64  /* R1 -> 35.7k */
-#define MP4245_I2C_ADDR_4_FLAGS 0x65  /* R1 -> 45.3k */
-#define MP4245_I2C_ADDR_5_FLAGS 0x66  /* R1 -> 56.0k */
-#define MP4245_I2C_ADDR_6_FLAGS 0x67  /* R1 -> VCC */
-
-
-/* MP4245 CMD Offsets */
-#define MP4245_CMD_OPERATION         0x01
-#define MP4245_CMD_CLEAR_FAULTS      0x03
-#define MP4245_CMD_WRITE_PROTECT     0x10
-#define MP4245_CMD_STORE_USER_ALL    0x15
-#define MP4245_CMD_RESTORE_USER_ALL  0x16
-#define MP4245_CMD_VOUT_MODE         0x20
-#define MP4245_CMD_VOUT_COMMAND      0x21
-#define MP4245_CMD_VOUT_SCALE_LOOP   0x29
-#define MP4245_CMD_STATUS_BYTE       0x78
-#define MP4245_CMD_STATUS_WORD       0x79
-#define MP4245_CMD_STATUS_VOUT       0x7A
-#define MP4245_CMD_STATUS_INPUT      0x7C
-#define MP4245_CMD_STATUS_TEMP       0x7D
-#define MP4245_CMD_STATUS_CML        0x7E
-#define MP4245_CMD_READ_VIN          0x88
-#define MP4245_CMD_READ_VOUT         0x8B
-#define MP4245_CMD_READ_IOUT         0x8C
-#define MP4245_CMD_READ_TEMP         0x8D
-#define MP4245_CMD_MFR_MODE_CTRL     0xD0
-#define MP4245_CMD_MFR_CURRENT_LIM   0xD1
-#define MP4245_CMD_MFR_LINE_DROP     0xD2
-#define MP4245_CMD_MFR_OT_FAULT_LIM  0xD3
-#define MP4245_CMD_MFR_OT_WARN_LIM   0xD4
-#define MP4245_CMD_MFR_CRC_ERROR     0xD5
-#define MP4245_CMD_MFF_MTP_CFG_CODE  0xD6
-#define MP4245_CMD_MFR_MTP_REV_NUM   0xD7
-#define MP4245_CMD_MFR_STATUS_MASK   0xD8
-
-#define MP4245_CMD_OPERATION_ON      BIT(7)
-
-#define MP4245_VOUT_1V               BIT(10)
-#define MP4245_VOUT_FROM_MV          (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000)
-#define MP4245_VOUT_TO_MV(v)         ((v * 1000) / MP4245_VOUT_1V)
-#define MP4245_IOUT_TO_MA(i)         (((i & 0x7ff) * 1000) / BIT(6))
-#define MP4245_ILIM_STEP_MA          50
-#define MP4245_VOUT_5V_DELAY_MS      10
-
-
-#define MP4245_MFR_STATUS_MASK_VOUT        BIT(7)
-#define MP4245_MFR_STATUS_MASK_IOUT        BIT(6)
-#define MP4245_MFR_STATUS_MASK_INPUT       BIT(5)
-#define MP4245_MFR_STATUS_MASK_TEMP        BIT(4)
-#define MP4245_MFR_STATUS_MASK_PG_STATUS   BIT(3)
-#define MP4245_MFR_STATUS_MASK_PG_ALT_EDGE BIT(2)
-#define MP4245_MFR_STATUS_MASK_OTHER       BIT(1)
-#define MP4245_MFR_STATUS_MASK_UNKNOWN     BIT(0)
-
-/**
- * MP4245 set output voltage level
- *
- * @param desired_mv -> voltage level in mV
- * @return i2c write result
- */
-int mp4245_set_voltage_out(int desired_mv);
-
-/**
- * MP4245 set output current limit
- *
- * @param desired_ma -> current limit in mA
- * @return i2c write result
- */
-int mp4245_set_current_lim(int desired_ma);
-
-/**
- * MP4245 set output current limit
- *
- * @param enable -> 0 = off, else on
- * @return i2c write result
- */
-int mp4245_votlage_out_enable(int enable);
-
-/**
- * MP4245 get Vbus voltage/current values
- *
- * @param *mv -> vbus voltage in mV
- * @param *ma -> vbus current in mA
- * @return i2c read results
- */
-int mp3245_get_vbus(int *mv, int *ma);
diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c
deleted file mode 100644
index 6f711c509e..0000000000
--- a/driver/nfc/ctn730.c
+++ /dev/null
@@ -1,711 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "ctn730.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "peripheral_charger.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Configuration
- */
-
-/* Print additional data */
-#define CTN730_DEBUG
-
-/*
- * When ctn730 is asleep, I2C is ignored but can wake it up. I2C will be resent
- * after this delay.
- */
-static const int _wake_up_delay_ms = 10;
-
-/* Device detection interval */
-static const int _detection_interval_ms = 500;
-
-/* Buffer size for i2c read & write */
-#define CTN730_MESSAGE_BUFFER_SIZE	0x20
-
-/* This driver isn't compatible with big endian. */
-BUILD_ASSERT(__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__);
-
-#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CTN730: " fmt, ##args)
-
-static const char *_text_instruction(uint8_t instruction)
-{
-	/* TODO: For normal build, use %pb and BINARY_VALUE(res->inst, 6) */
-	switch (instruction) {
-	case WLC_HOST_CTRL_RESET:
-		return "RESET";
-	case WLC_HOST_CTRL_DL_OPEN_SESSION:
-		return "DL_OPEN";
-	case WLC_HOST_CTRL_DL_COMMIT_SESSION:
-		return "DL_COMMIT";
-	case WLC_HOST_CTRL_DL_WRITE_FLASH:
-		return "DL_WRITE";
-	case WLC_HOST_CTRL_DUMP_STATUS:
-		return "DUMP_STATUS";
-	case WLC_HOST_CTRL_GENERIC_ERROR:
-		return "GENERIC_ERROR";
-	case WLC_HOST_CTRL_BIST:
-		return "BIST";
-	case WLC_CHG_CTRL_ENABLE:
-		return "ENABLE";
-	case WLC_CHG_CTRL_DISABLE:
-		return "DISABLE";
-	case WLC_CHG_CTRL_DEVICE_STATE:
-		return "DEVICE_STATE";
-	case WLC_CHG_CTRL_CHARGING_STATE:
-		return "CHARGING_STATE";
-	case WLC_CHG_CTRL_CHARGING_INFO:
-		return "CHARGING_INFO";
-	default:
-		return "UNDEF";
-	}
-}
-
-static const char *_text_message_type(uint8_t type)
-{
-	switch (type) {
-	case CTN730_MESSAGE_TYPE_COMMAND:
-		return "CMD";
-	case CTN730_MESSAGE_TYPE_RESPONSE:
-		return "RSP";
-	case CTN730_MESSAGE_TYPE_EVENT:
-		return "EVT";
-	default:
-		return "BAD";
-	}
-}
-
-static const char *_text_status_code(uint8_t code)
-{
-	switch (code) {
-	case WLC_HOST_STATUS_OK:
-		return "OK";
-	case WLC_HOST_STATUS_PARAMETER_ERROR:
-		return "PARAMETER_ERR";
-	case WLC_HOST_STATUS_STATE_ERROR:
-		return "STATE_ERR";
-	case WLC_HOST_STATUS_VALUE_ERROR:
-		return "VALUE_ERR";
-	case WLC_HOST_STATUS_REJECTED:
-		return "REJECTED";
-	case WLC_HOST_STATUS_RESOURCE_ERROR:
-		return "RESOURCE_ERR";
-	case WLC_HOST_STATUS_TXLDO_ERROR:
-		return "TXLDO_ERR";
-	case WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR:
-		return "ANTENNA_SELECTION_ERR";
-	case WLC_HOST_STATUS_BIST_FAILED:
-		return "BIST_FAILED";
-	case WLC_HOST_STATUS_BIST_NO_WLC_CAP:
-		return "BIST_NO_WLC_CAP";
-	case WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW:
-		return "BIST_TXLDO_CURRENT_OVERFLOW";
-	case WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW:
-		return "BIST_TXLDO_CURRENT_UNDERFLOW";
-	case WLC_HOST_STATUS_FW_VERSION_ERROR:
-		return "FW_VERSION_ERR";
-	case WLC_HOST_STATUS_FW_VERIFICATION_ERROR:
-		return "FW_VERIFICATION_ERR";
-	case WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR:
-		return "NTAG_BLOCK_PARAMETER_ERR";
-	case WLC_HOST_STATUS_NTAG_READ_ERROR:
-		return "NTAG_READ_ERR";
-	default:
-		return "UNDEF";
-	}
-}
-
-static const char *_text_reset_reason(uint8_t code)
-{
-	switch (code) {
-	case WLC_HOST_CTRL_RESET_REASON_INTENDED:
-		return "intended";
-	case WLC_HOST_CTRL_RESET_REASON_CORRUPTED:
-		return "corrupted";
-	case WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE:
-		return "unrecoverable";
-	default:
-		return "unknown";
-	}
-}
-
-static int _i2c_read(int i2c_port, uint8_t *in, int in_len)
-{
-	int rv;
-
-	memset(in, 0, in_len);
-
-	rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, NULL, 0, in, in_len);
-	if (rv) {
-		msleep(_wake_up_delay_ms);
-		rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, NULL, 0, in, in_len);
-	}
-	if (rv)
-		CPRINTS("Failed to read: %d", rv);
-
-	return rv;
-}
-
-static void _print_header(const struct ctn730_msg *msg)
-{
-	CPRINTS("%s_%s",
-		_text_instruction(msg->instruction),
-		_text_message_type(msg->message_type));
-}
-
-static int _send_command(struct pchg *ctx, const struct ctn730_msg *cmd)
-{
-	int i2c_port = ctx->cfg->i2c_port;
-	int rv;
-
-	_print_header(cmd);
-
-	rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, (void *)cmd,
-		      sizeof(*cmd) + cmd->length, NULL, 0);
-
-	if (rv) {
-		msleep(_wake_up_delay_ms);
-		rv = i2c_xfer(i2c_port, CTN730_I2C_ADDR, (void *)cmd,
-			      sizeof(*cmd) + cmd->length, NULL, 0);
-	}
-	if (rv)
-		CPRINTS("Failed to write: %d", rv);
-
-	return rv;
-}
-
-static int ctn730_reset(struct pchg *ctx)
-{
-	gpio_set_level(GPIO_WLC_NRST_CONN, 0);
-	/*
-	 * Datasheet says minimum is 10 us. This is better not to be a sleep
-	 * especially if it's long (e.g. ~1 ms) since the PCHG state machine
-	 * may try to access the I2C bus, which is held low by ctn730.
-	 */
-	udelay(15);
-	gpio_set_level(GPIO_WLC_NRST_CONN, 1);
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int ctn730_init(struct pchg *ctx)
-{
-	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	int rv;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	cmd->instruction = WLC_HOST_CTRL_RESET;
-	cmd->length = WLC_HOST_CTRL_RESET_CMD_SIZE;
-	cmd->payload[0] = ctx->mode == PCHG_MODE_NORMAL
-			? WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL
-			: WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD;
-
-	/* TODO: Run 1 sec timeout timer. */
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		return rv;
-
-	/* WLC-host should send EVT_HOST_CTRL_RESET_EVT shortly. */
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int ctn730_enable(struct pchg *ctx, bool enable)
-{
-	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	uint16_t *interval = (void *)cmd->payload;
-	int rv;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	if (enable) {
-		cmd->instruction = WLC_CHG_CTRL_ENABLE;
-		cmd->length = WLC_CHG_CTRL_ENABLE_CMD_SIZE;
-		/* Assume core is little endian. Use htole16 for portability. */
-		*interval = _detection_interval_ms;
-	} else {
-		cmd->instruction = WLC_CHG_CTRL_DISABLE;
-		cmd->length = WLC_CHG_CTRL_DISABLE_CMD_SIZE;
-	}
-
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int _process_payload_response(struct pchg *ctx, struct ctn730_msg *res)
-{
-	uint8_t len = res->length;
-	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
-
-	if (sizeof(buf) < len) {
-		CPRINTS("Response size (%d) exceeds buffer", len);
-		return EC_ERROR_OVERFLOW;
-	}
-
-	if (len > 0) {
-		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
-		if (rv)
-			return rv;
-		if (IS_ENABLED(CTN730_DEBUG))
-			CPRINTS("Payload: %ph", HEX_BUF(buf, len));
-	}
-
-	ctx->event = PCHG_EVENT_NONE;
-
-	/*
-	 * Messages with no payload (<len> == 0) is allowed in the spec. So,
-	 * make sure <len> is checked before reading buf[0].
-	 */
-	switch (res->instruction) {
-	case WLC_HOST_CTRL_RESET:
-		if (len != WLC_HOST_CTRL_RESET_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK)
-			ctx->event = PCHG_EVENT_OTHER_ERROR;
-		break;
-	case WLC_HOST_CTRL_DL_OPEN_SESSION:
-		if (len != WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK) {
-			CPRINTS("FW open session failed for %s",
-				_text_status_code(buf[0]));
-			ctx->event = PCHG_EVENT_UPDATE_ERROR;
-			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_FW_VERSION);
-		} else {
-			ctx->event = PCHG_EVENT_UPDATE_OPENED;
-		}
-		break;
-	case WLC_HOST_CTRL_DL_COMMIT_SESSION:
-		if (len != WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK) {
-			CPRINTS("FW commit failed for %s",
-				_text_status_code(buf[0]));
-			ctx->event = PCHG_EVENT_UPDATE_ERROR;
-			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_INVALID_FW);
-		} else {
-			ctx->event = PCHG_EVENT_UPDATE_CLOSED;
-		}
-		break;
-	case WLC_HOST_CTRL_DL_WRITE_FLASH:
-		if (len != WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK) {
-			CPRINTS("FW write failed for %s",
-				_text_status_code(buf[0]));
-			ctx->event = PCHG_EVENT_UPDATE_ERROR;
-			ctx->error |= PCHG_ERROR_MASK(PCHG_ERROR_WRITE_FLASH);
-		} else {
-			ctx->event = PCHG_EVENT_UPDATE_WRITTEN;
-		}
-		break;
-	case WLC_CHG_CTRL_ENABLE:
-		if (len != WLC_CHG_CTRL_ENABLE_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK)
-			ctx->event = PCHG_EVENT_OTHER_ERROR;
-		else
-			ctx->event = PCHG_EVENT_ENABLED;
-		break;
-	case WLC_CHG_CTRL_DISABLE:
-		if (len != WLC_CHG_CTRL_DISABLE_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK)
-			ctx->event = PCHG_EVENT_OTHER_ERROR;
-		else
-			ctx->event = PCHG_EVENT_DISABLED;
-		break;
-	case WLC_CHG_CTRL_CHARGING_INFO:
-		if (len != WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE)
-			return EC_ERROR_UNKNOWN;
-		if (buf[0] != WLC_HOST_STATUS_OK) {
-			ctx->event = PCHG_EVENT_OTHER_ERROR;
-		} else {
-			ctx->battery_percent = buf[1];
-			ctx->event = PCHG_EVENT_CHARGE_UPDATE;
-		}
-		break;
-	default:
-		CPRINTS("Received unknown response (%d)", res->instruction);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int _process_payload_event(struct pchg *ctx, struct ctn730_msg *res)
-{
-	uint8_t len = res->length;
-	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
-
-	if (sizeof(buf) < len) {
-		CPRINTS("Response size (%d) exceeds buffer", len);
-		return EC_ERROR_OVERFLOW;
-	}
-
-	if (len > 0) {
-		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
-		if (rv)
-			return rv;
-		if (IS_ENABLED(CTN730_DEBUG))
-			CPRINTS("Payload: %ph", HEX_BUF(buf, len));
-	}
-
-	ctx->event = PCHG_EVENT_NONE;
-
-	/*
-	 * Messages with no payload (<len> == 0) is allowed in the spec. So,
-	 * make sure <len> is checked before reading buf[0].
-	 */
-	switch (res->instruction) {
-	case WLC_HOST_CTRL_RESET:
-		if (len < WLC_HOST_CTRL_RESET_EVT_MIN_SIZE)
-			return EC_ERROR_INVAL;
-		if (buf[0] == WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE) {
-			if (len != WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE)
-				return EC_ERROR_INVAL;
-			ctx->event = PCHG_EVENT_IN_NORMAL;
-			ctx->fw_version = (uint16_t)buf[1] << 8 | buf[2];
-			CPRINTS("Normal Mode (FW=0x%02x.%02x)", buf[1], buf[2]);
-			/*
-			 * ctn730 isn't immediately ready for i2c write after
-			 * normal mode initialization (b:178096436).
-			 */
-			msleep(5);
-		} else if (buf[0] == WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE) {
-			if (len != WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE)
-				return EC_ERROR_INVAL;
-			CPRINTS("Download Mode (%s)",
-				_text_reset_reason(buf[1]));
-			ctx->event = PCHG_EVENT_RESET;
-		} else {
-			return EC_ERROR_INVAL;
-		}
-		break;
-	case WLC_HOST_CTRL_GENERIC_ERROR:
-		break;
-	case WLC_CHG_CTRL_DISABLE:
-		if (len != WLC_CHG_CTRL_DISABLE_EVT_SIZE)
-			return EC_ERROR_INVAL;
-		ctx->event = PCHG_EVENT_DISABLED;
-		break;
-	case WLC_CHG_CTRL_DEVICE_STATE:
-		if (len < WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
-			return EC_ERROR_INVAL;
-		switch (buf[0]) {
-		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED:
-			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
-				return EC_ERROR_INVAL;
-			ctx->event = PCHG_EVENT_DEVICE_DETECTED;
-			break;
-		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED:
-			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED)
-				return EC_ERROR_INVAL;
-			ctx->event = PCHG_EVENT_DEVICE_CONNECTED;
-			break;
-		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST:
-		case WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED:
-			if (len != WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE)
-				return EC_ERROR_INVAL;
-			ctx->event = PCHG_EVENT_DEVICE_LOST;
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-		break;
-	case WLC_CHG_CTRL_CHARGING_STATE:
-		if (len != WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE)
-			return EC_ERROR_INVAL;
-		switch (buf[0]) {
-		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED:
-			ctx->event = PCHG_EVENT_CHARGE_STARTED;
-			break;
-		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED:
-			ctx->event = PCHG_EVENT_CHARGE_ENDED;
-			break;
-		case WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED:
-			/* Includes over temp., DISABLE_CMD, device removal. */
-			ctx->event = PCHG_EVENT_CHARGE_STOPPED;
-			break;
-		default:
-			return EC_ERROR_INVAL;
-		}
-		break;
-	case WLC_CHG_CTRL_CHARGING_INFO:
-		if (len != WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE || buf[0] > 100)
-			return EC_ERROR_INVAL;
-		ctx->event = PCHG_EVENT_CHARGE_UPDATE;
-		ctx->battery_percent = buf[0];
-		break;
-	default:
-		CPRINTS("Received unknown event (%d)", res->instruction);
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int ctn730_get_event(struct pchg *ctx)
-{
-	struct ctn730_msg res;
-	int i2c_port = ctx->cfg->i2c_port;
-	int rv;
-
-	/* Read message header */
-	rv = _i2c_read(i2c_port, (uint8_t *)&res, sizeof(res));
-	if (rv)
-		return rv;
-
-	_print_header(&res);
-
-	if (res.message_type == CTN730_MESSAGE_TYPE_RESPONSE) {
-		/* TODO: Check 1 sec timeout. */
-		return _process_payload_response(ctx, &res);
-	} else if (res.message_type == CTN730_MESSAGE_TYPE_EVENT) {
-		return _process_payload_event(ctx, &res);
-	}
-
-	CPRINTS("Invalid message type (%d)", res.message_type);
-	return EC_ERROR_UNKNOWN;
-}
-
-static int ctn730_get_soc(struct pchg *ctx)
-{
-	struct ctn730_msg cmd;
-	int rv;
-
-	cmd.message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	cmd.instruction = WLC_CHG_CTRL_CHARGING_INFO;
-	cmd.length = WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE;
-
-	rv = _send_command(ctx, &cmd);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int ctn730_update_open(struct pchg *ctx)
-{
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	uint32_t version = ctx->update.version;
-	int rv;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	cmd->instruction = WLC_HOST_CTRL_DL_OPEN_SESSION;
-	cmd->length = WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE;
-	cmd->payload[0] = (version >> 8) & 0xff;
-	cmd->payload[1] = version & 0xff;
-
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int ctn730_update_write(struct pchg *ctx)
-{
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	uint32_t *a = (void *)cmd->payload;
-	uint8_t *d = (void *)&cmd->payload[CTN730_FLASH_ADDR_SIZE];
-	int rv;
-
-	/* Address is 3 bytes. FW size must be a multiple of 128 bytes. */
-	if (ctx->update.addr & GENMASK(31, 24)
-		|| ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
-		return EC_ERROR_INVAL;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	cmd->instruction = WLC_HOST_CTRL_DL_WRITE_FLASH;
-	cmd->length = WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE;
-
-	/* 4th byte will be overwritten by memcpy below. */
-	*a = ctx->update.addr;
-
-	/* Store data in payload with 0-padding for short blocks. */
-	memset(d, 0, WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE);
-	memcpy(d, ctx->update.data, ctx->update.size);
-
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-static int ctn730_update_close(struct pchg *ctx)
-{
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	uint32_t *crc32 = (void *)cmd->payload;
-	int rv;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-	cmd->instruction = WLC_HOST_CTRL_DL_COMMIT_SESSION;
-	cmd->length = WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE;
-	*crc32 = ctx->update.crc32;
-
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS_IN_PROGRESS;
-}
-
-/**
- * Send command in blocking loop
- *
- * @param ctx     PCHG port context
- * @param buf     [IN] Command header and payload to send.
- *                [OUT] Response header and payload received.
- * @param buf_len Size of <buf>
- * @return        enum ec_error_list
- */
-static int _send_command_blocking(struct pchg *ctx, uint8_t *buf, int buf_len)
-{
-	int i2c_port = ctx->cfg->i2c_port;
-	int irq_pin = ctx->cfg->irq_pin;
-	struct ctn730_msg *cmd = (void *)buf;
-	struct ctn730_msg *res = (void *)buf;
-	timestamp_t deadline;
-	int rv;
-
-	gpio_disable_interrupt(irq_pin);
-
-	rv = _send_command(ctx, cmd);
-	if (rv)
-		goto exit;
-
-	deadline.val = get_time().val + CTN730_COMMAND_TIME_OUT;
-
-	/* Busy loop */
-	while (gpio_get_level(irq_pin) == 0 && !rv) {
-		udelay(1 * MSEC);
-		rv = timestamp_expired(deadline, NULL);
-		watchdog_reload();
-	}
-
-	if (rv) {
-		ccprintf("Response timeout\n");
-		rv = EC_ERROR_TIMEOUT;
-		goto exit;
-	}
-
-	rv = _i2c_read(i2c_port, buf, sizeof(*res));
-	if (rv)
-		goto exit;
-
-	_print_header(res);
-
-	if (sizeof(*res) + res->length > buf_len) {
-		ccprintf("RSP size exceeds buffer\n");
-		rv = EC_ERROR_OVERFLOW;
-		goto exit;
-	}
-
-	rv = _i2c_read(i2c_port, res->payload, res->length);
-	if (rv)
-		goto exit;
-
-exit:
-	gpio_clear_pending_interrupt(irq_pin);
-	gpio_enable_interrupt(irq_pin);
-
-	return rv;
-}
-
-const struct pchg_drv ctn730_drv = {
-	.reset = ctn730_reset,
-	.init = ctn730_init,
-	.enable = ctn730_enable,
-	.get_event = ctn730_get_event,
-	.get_soc = ctn730_get_soc,
-	.update_open = ctn730_update_open,
-	.update_write = ctn730_update_write,
-	.update_close = ctn730_update_close,
-};
-
-static int cc_ctn730(int argc, char **argv)
-{
-	int port;
-	char *end;
-	uint8_t buf[CTN730_MESSAGE_BUFFER_SIZE];
-	struct ctn730_msg *cmd = (void *)buf;
-	struct ctn730_msg *res = (void *)buf;
-	int rv;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &end, 0);
-	if (*end || port < 0 || pchg_count <= port)
-		return EC_ERROR_PARAM2;
-
-	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
-
-	if (!strcasecmp(argv[2], "dump")) {
-		int tag = strtoi(argv[3], &end, 0);
-
-		if (*end || tag < 0 || 0x07 < tag)
-			return EC_ERROR_PARAM3;
-
-		cmd->instruction = WLC_HOST_CTRL_DUMP_STATUS;
-		cmd->length = WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE;
-		cmd->payload[0] = tag;
-	} else if (!strcasecmp(argv[2], "bist")) {
-		int id = strtoi(argv[3], &end, 0);
-
-		if (*end || id < 0)
-			return EC_ERROR_PARAM3;
-
-		cmd->instruction = WLC_HOST_CTRL_BIST;
-		cmd->payload[0] = id;
-
-		switch (id) {
-		case 0x01:
-			/* Switch on RF field. Tx driver conf not implemented */
-			cmd->length = 1;
-			break;
-		case 0x04:
-			/* WLC device activation test */
-			cmd->length = 1;
-			break;
-		default:
-			return EC_ERROR_PARAM3;
-		}
-	} else {
-		return EC_ERROR_PARAM2;
-	}
-
-	rv = _send_command_blocking(&pchgs[port], buf, sizeof(buf));
-	if (rv)
-		return rv;
-
-	ccprintf("STATUS_%s\n", _text_status_code(res->payload[0]));
-	hexdump(res->payload, res->length);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ctn730, cc_ctn730,
-			"<port> dump/bist <tag/id>"
-			"\n\t<port> dump <tag>"
-			"\n\t<port> bist <test_id>",
-			"Control ctn730");
diff --git a/driver/nfc/ctn730.h b/driver/nfc/ctn730.h
deleted file mode 100644
index 0195b36a6d..0000000000
--- a/driver/nfc/ctn730.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CTN730_H
-#define __CROS_EC_CTN730_H
-
-#define CTN730_I2C_ADDR			0x28
-
-/* Size of flash address space in bytes */
-#define CTN730_FLASH_ADDR_SIZE		3
-
-/* All commands are guaranteed to finish within 1 second. */
-#define CTN730_COMMAND_TIME_OUT		(1 * SECOND)
-
-/* Message Types */
-#define CTN730_MESSAGE_TYPE_COMMAND	0b00
-#define CTN730_MESSAGE_TYPE_RESPONSE	0b01
-#define CTN730_MESSAGE_TYPE_EVENT	0b10
-
-/* Instruction Codes */
-#define WLC_HOST_CTRL_RESET			0b000000
-#define WLC_HOST_CTRL_DL_OPEN_SESSION		0b000011
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION		0b000100
-#define WLC_HOST_CTRL_DL_WRITE_FLASH		0b000101
-#define WLC_HOST_CTRL_DUMP_STATUS		0b001100
-#define WLC_HOST_CTRL_GENERIC_ERROR		0b001111
-#define WLC_HOST_CTRL_BIST			0b000110
-#define WLC_CHG_CTRL_ENABLE			0b010000
-#define WLC_CHG_CTRL_DISABLE			0b010001
-#define WLC_CHG_CTRL_DEVICE_STATE		0b010010
-#define WLC_CHG_CTRL_CHARGING_STATE		0b010100
-#define WLC_CHG_CTRL_CHARGING_INFO		0b010101
-
-/* WLC_HOST_CTRL_RESET constants */
-#define WLC_HOST_CTRL_RESET_CMD_SIZE			1
-#define WLC_HOST_CTRL_RESET_RSP_SIZE			1
-#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE		0x00
-#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE	3
-#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE		0x01
-#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE	2
-#define WLC_HOST_CTRL_RESET_REASON_INTENDED		0x00
-#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED		0x01
-#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE	0x02
-#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL		0x00
-#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD		0x01
-#define WLC_HOST_CTRL_RESET_EVT_MIN_SIZE \
-	WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE
-
-/* WLC_HOST_CTRL_DL_* constants */
-#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE		2
-#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE		1
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE		128
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE		\
-	(CTN730_FLASH_ADDR_SIZE + WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE		1
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE	4
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE	1
-
-/* WLC_CHG_CTRL_ENABLE constants */
-#define WLC_CHG_CTRL_ENABLE_CMD_SIZE		2
-#define WLC_CHG_CTRL_ENABLE_RSP_SIZE		1
-
-/* WLC_CHG_CTRL_DISABLE constants */
-#define WLC_CHG_CTRL_DISABLE_CMD_SIZE		0
-#define WLC_CHG_CTRL_DISABLE_RSP_SIZE		1
-#define WLC_CHG_CTRL_DISABLE_EVT_SIZE		1
-
-/* WLC_CHG_CTRL_DEVICE_STATE constants */
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED		0x00
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED		0x01
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST		0x02
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION	0x03
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED			0x04
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED		0x05
-#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED		8
-#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE			1
-
-/* WLC_CHG_CTRL_CHARGING_STATE constants */
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED		0x00
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED		0x01
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED		0x02
-#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE			1
-
-/* WLC_HOST_CTRL_DUMP_STATUS constants */
-#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE	1
-
-/* WLC_CHG_CTRL_CHARGING_INFO constants */
-#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE	0
-#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE	2
-#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE	5
-
-/* Status Codes */
-enum wlc_host_status {
-	WLC_HOST_STATUS_OK				= 0x00,
-	WLC_HOST_STATUS_PARAMETER_ERROR			= 0x01,
-	WLC_HOST_STATUS_STATE_ERROR			= 0x02,
-	WLC_HOST_STATUS_VALUE_ERROR			= 0x03,
-	WLC_HOST_STATUS_REJECTED			= 0x04,
-	WLC_HOST_STATUS_RESOURCE_ERROR			= 0x10,
-	WLC_HOST_STATUS_TXLDO_ERROR			= 0x11,
-	WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR		= 0x12,
-	WLC_HOST_STATUS_BIST_FAILED			= 0x20,
-	WLC_HOST_STATUS_BIST_NO_WLC_CAP			= 0x21,
-	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW	= 0x22,
-	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW	= 0x23,
-	WLC_HOST_STATUS_FW_VERSION_ERROR		= 0x30,
-	WLC_HOST_STATUS_FW_VERIFICATION_ERROR		= 0x31,
-	WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR	= 0x32,
-	WLC_HOST_STATUS_NTAG_READ_ERROR			= 0x33,
-};
-
-struct ctn730_msg {
-	uint8_t instruction : 6;
-	uint8_t message_type : 2;
-	uint8_t length;
-	uint8_t payload[];
-} __packed;
-
-#endif  /* __CROS_EC_CTN730_H */
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h
deleted file mode 100644
index e00ea1d252..0000000000
--- a/driver/pmic_bd99992gw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ROHM BD99992GW PMIC register map.
- */
-
-#ifndef __CROS_EC_PMIC_BD99992GW_H
-#define __CROS_EC_PMIC_BD99992GW_H
-
-#include "temp_sensor/bd99992gw.h"
-
-#define BD99992GW_REG_PWRSRCINT		0x04
-#define BD99992GW_REG_RESETIRQ1		0x08
-#define BD99992GW_REG_PBCONFIG		0x14
-#define BD99992GW_REG_PWRSTAT1		0x16
-#define BD99992GW_REG_PWRSTAT2		0x17
-#define BD99992GW_REG_VCCIOCNT		0x30
-#define BD99992GW_REG_V5ADS3CNT		0x31
-#define BD99992GW_REG_V18ACNT		0x34
-#define BD99992GW_REG_V100ACNT		0x37
-#define BD99992GW_REG_V085ACNT		0x38
-#define BD99992GW_REG_VRMODECTRL	0x3b
-#define BD99992GW_REG_DISCHGCNT1	0x3c
-#define BD99992GW_REG_DISCHGCNT2	0x3d
-#define BD99992GW_REG_DISCHGCNT3	0x3e
-#define BD99992GW_REG_DISCHGCNT4	0x3f
-#define BD99992GW_REG_SDWNCTRL		0x49
-#define BD99992GW_SDWNCTRL_SWDN		BIT(0) /* SWDN mask */
-
-#endif  /* __CROS_EC_PMIC_BD99992GW_H */
diff --git a/driver/pmic_tps650x30.h b/driver/pmic_tps650x30.h
deleted file mode 100644
index f03bef5f05..0000000000
--- a/driver/pmic_tps650x30.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI TPS650x30 PMIC register map.
- */
-
-#ifndef __CROS_EC_PMIC_TPS650X30_H
-#define __CROS_EC_PMIC_TPS650X30_H
-
-/* I2C interface */
-#define TPS650X30_I2C_ADDR1_FLAGS	0x30
-#define TPS650X30_I2C_ADDR2_FLAGS	0x32
-#define TPS650X30_I2C_ADDR3_FLAGS	0x34
-
-/* TPS650X30 registers */
-#define TPS650X30_REG_VENDORID		0x00
-#define TPS650X30_REG_PBCONFIG		0x14
-#define TPS650X30_REG_PGMASK1		0x18
-#define TPS650X30_REG_VCCIOCNT		0x30
-#define TPS650X30_REG_V5ADS3CNT		0x31
-#define TPS650X30_REG_V33ADSWCNT	0x32
-#define TPS650X30_REG_V18ACNT		0x34
-#define TPS650X30_REG_V1P2UCNT		0x36
-#define TPS650X30_REG_V100ACNT		0x37
-#define TPS650X30_REG_VRMODECTRL	0x3B
-#define TPS650X30_REG_DISCHCNT1		0x3C
-#define TPS650X30_REG_DISCHCNT2		0x3D
-#define TPS650X30_REG_DISCHCNT3		0x3E
-#define TPS650X30_REG_DISCHCNT4		0x3F
-#define TPS650X30_REG_PWFAULT_MASK1	0xE5
-#define TPS650X30_REG_PWFAULT_MASK2	0xE6
-
-/* TPS650X30 register values */
-#define TPS650X30_VENDOR_ID		0x22
-
-#endif	/* __CROS_EC_PMIC_TPS650X30_H */
diff --git a/driver/ppc/aoz1380.c b/driver/ppc/aoz1380.c
deleted file mode 100644
index 4e2188c60d..0000000000
--- a/driver/ppc/aoz1380.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * AOZ1380 USB-C Power Path Controller
- *
- * This is a basic TCPM controlled PPC driver.  It could easily be
- * renamed and repurposed to be generic, if there are other TCPM
- * controlled PPC chips that are similar to the AOZ1380
- */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "aoz1380.h"
-#include "hooks.h"
-#include "system.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpc.h"
-#include "usbc_ppc.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
-
-#define AOZ1380_FLAGS_SOURCE_ENABLED    BIT(0)
-#define AOZ1380_FLAGS_SINK_ENABLED      BIT(1)
-#define AOZ1380_FLAGS_INT_ON_DISCONNECT BIT(2)
-static uint32_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define AOZ1380_SET_FLAG(port, flag) atomic_or(&flags[port], (flag))
-#define AOZ1380_CLR_FLAG(port, flag) atomic_clear_bits(&flags[port], (flag))
-
-static int aoz1380_init(int port)
-{
-	flags[port] = 0;
-
-	if (tcpm_get_snk_ctrl(port))
-		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SINK_ENABLED);
-
-	if (tcpm_get_src_ctrl(port))
-		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SOURCE_ENABLED);
-
-	return EC_SUCCESS;
-}
-
-static int aoz1380_vbus_sink_enable(int port, int enable)
-{
-	int rv;
-
-	rv = tcpm_set_snk_ctrl(port, enable);
-	if (rv)
-		return rv;
-
-	/*
-	 * On enable, we want to indicate connection as a SINK.
-	 * On disable, clear SINK and that we have interrupted.
-	 */
-	if (enable)
-		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SINK_ENABLED);
-	else
-		AOZ1380_CLR_FLAG(port, (AOZ1380_FLAGS_SINK_ENABLED |
-					AOZ1380_FLAGS_INT_ON_DISCONNECT));
-
-	return EC_SUCCESS;
-}
-
-static int aoz1380_vbus_source_enable(int port, int enable)
-{
-	int rv;
-
-	rv = tcpm_set_src_ctrl(port, enable);
-	if (rv)
-		return rv;
-
-	/*
-	 * On enable, we want to indicate connection as a SOURCE.
-	 * On disable, clear SOURCE and that we have interrupted.
-	 */
-	if (enable)
-		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_SOURCE_ENABLED);
-	else
-		AOZ1380_CLR_FLAG(port, (AOZ1380_FLAGS_SOURCE_ENABLED |
-					AOZ1380_FLAGS_INT_ON_DISCONNECT));
-
-	return EC_SUCCESS;
-}
-
-static int aoz1380_is_sourcing_vbus(int port)
-{
-	return flags[port] & AOZ1380_FLAGS_SOURCE_ENABLED;
-}
-
-static int aoz1380_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
-{
-	return board_aoz1380_set_vbus_source_current_limit(port, rp);
-}
-
-/*
- * AOZ1380 Interrupt Handler
- *
- * This device only has a single over current/temperature interrupt.
- * TODO(b/141939343) Determine how to clear the interrupt
- * TODO(b/142076004) Test this to verify we shut off vbus current
- * TODO(b/147359722) Verify correct fault functionality
- */
-static void aoz1380_handle_interrupt(int port)
-{
-	/*
-	 * We can get a false positive on disconnect that we
-	 * had an over current/temperature event when we are no
-	 * longer connected as sink or source.  Ignore it if
-	 * that is the case.
-	 */
-	if (flags[port] != 0) {
-		/*
-		 * This is a over current/temperature condition
-		 */
-		ppc_prints("Vbus overcurrent/temperature", port);
-		pd_handle_overcurrent(port);
-	} else {
-		/*
-		 * Just in case there is a condition that we will
-		 * continue an interrupt storm, track that we have
-		 * already been here once and will take the other
-		 * path if we do this again before setting the
-		 * sink/source as enabled or disabled again.
-		 */
-		AOZ1380_SET_FLAG(port, AOZ1380_FLAGS_INT_ON_DISCONNECT);
-	}
-}
-
-static void aoz1380_irq_deferred(void)
-{
-	int i;
-	uint32_t pending = atomic_clear(&irq_pending);
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		if (BIT(i) & pending)
-			aoz1380_handle_interrupt(i);
-}
-DECLARE_DEFERRED(aoz1380_irq_deferred);
-
-void aoz1380_interrupt(int port)
-{
-	atomic_or(&irq_pending, BIT(port));
-	hook_call_deferred(&aoz1380_irq_deferred_data, 0);
-}
-
-const struct ppc_drv aoz1380_drv = {
-	.init = &aoz1380_init,
-	.is_sourcing_vbus = &aoz1380_is_sourcing_vbus,
-	.vbus_sink_enable = &aoz1380_vbus_sink_enable,
-	.vbus_source_enable = &aoz1380_vbus_source_enable,
-	.set_vbus_source_current_limit =
-		&aoz1380_set_vbus_source_current_limit,
-};
diff --git a/driver/ppc/aoz1380.h b/driver/ppc/aoz1380.h
deleted file mode 100644
index 94f2b804b7..0000000000
--- a/driver/ppc/aoz1380.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * AOZ1380 USB-C Power Path Controller
- *
- * This is a basic TCPM controlled PPC driver.  It could easily be
- * renamed and repurposed to be generic, if there are other TCPM
- * controlled PPC chips that are similar to the AOZ1380
- */
-
-#ifndef __CROS_EC_AOZ1380_H
-#define __CROS_EC_AOZ1380_H
-
-#include "usb_pd_tcpm.h"
-
-struct ppc_drv;
-extern const struct ppc_drv aoz1380_drv;
-
-/**
- * AOZ1380 Set VBus Source Current Limit.
- *
- * Using this driver requires a board_aoz1380_set_vbus_source_limit
- * function due to the lack of programability of this device and
- * requirement for hardware specific code to handle setting this limit.
- *
- * @param port The Type-C port
- * @param rp The Type-C RP value
- * @return EC_SUCCESS for success, otherwise error
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp);
-
-
-/**
- * Interrupt Handler for the AOZ1380.
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void aoz1380_interrupt(int port);
-
-#endif /* defined(__CROS_EC_AOZ1380_H) */
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c
deleted file mode 100644
index a5136bbf23..0000000000
--- a/driver/ppc/nx20p348x.c
+++ /dev/null
@@ -1,566 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NX20P348x USB-C Power Path Controller */
-
-#include "common.h"
-#include "console.h"
-#include "nx20p348x.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "tcpm/tcpm.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
-
-#define NX20P348X_DB_EXIT_FAIL_THRESHOLD 10
-static int db_exit_fail_count[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define NX20P348X_FLAGS_SOURCE_ENABLED BIT(0)
-static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#if !defined(CONFIG_USBC_PPC_NX20P3481) && !defined(CONFIG_USBC_PPC_NX20P3483)
-#error "Either the NX20P3481 or NX20P3483 must be selected"
-#endif
-
-static int read_reg(uint8_t port, int reg, int *regval)
-{
-	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
-}
-
-static int write_reg(uint8_t port, int reg, int regval)
-{
-	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
-}
-
-static int nx20p348x_set_ovp_limit(int port)
-{
-	int rv;
-	int reg;
-
-	/* Set VBUS over voltage threshold (OVLO) */
-	rv = read_reg(port, NX20P348X_OVLO_THRESHOLD_REG, &reg);
-	if (rv)
-		return rv;
-	/* OVLO threshold is 3 bit field */
-	reg &= ~NX20P348X_OVLO_THRESHOLD_MASK;
-	/* Set SNK OVP to 23.0 V */
-	reg |= NX20P348X_OVLO_23_0;
-	rv = write_reg(port, NX20P348X_OVLO_THRESHOLD_REG, reg);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-static int nx20p348x_is_sourcing_vbus(int port)
-{
-	return flags[port] & NX20P348X_FLAGS_SOURCE_ENABLED;
-}
-
-static int nx20p348x_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
-{
-	int regval;
-	int status;
-
-	status = read_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, &regval);
-	if (status)
-		return status;
-
-	regval &= ~NX20P348X_ILIM_MASK;
-
-	/* We need buffer room for all current values. */
-	switch (rp) {
-	case TYPEC_RP_3A0:
-		regval |= NX20P348X_ILIM_3_200;
-		break;
-
-	case TYPEC_RP_1A5:
-		regval |= NX20P348X_ILIM_1_600;
-		break;
-
-	case TYPEC_RP_USB:
-	default:
-		regval |= NX20P348X_ILIM_0_600;
-		break;
-	};
-
-
-	return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval);
-}
-
-static int nx20p348x_discharge_vbus(int port, int enable)
-{
-	int regval;
-	int newval;
-	int status;
-
-	status = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &regval);
-	if (status)
-		return status;
-
-	if (enable)
-		newval = regval | NX20P348X_CTRL_VBUSDIS_EN;
-	else
-		newval = regval & ~NX20P348X_CTRL_VBUSDIS_EN;
-
-	if (newval == regval)
-		return EC_SUCCESS;
-
-	status = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, newval);
-	if (status) {
-		CPRINTS("Failed to %s VBUS discharge",
-			enable ? "enable" : "disable");
-		return status;
-	}
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int nx20p3481_vbus_sink_enable(int port, int enable)
-{
-	int status;
-	int rv;
-	int control = enable ? NX20P3481_SWITCH_CONTROL_HVSNK : 0;
-
-	if (enable) {
-		/*
-		 * VBUS Discharge must be off in sink mode.
-		 */
-		rv = nx20p348x_discharge_vbus(port, 0);
-		if (rv)
-			return rv;
-	}
-
-	rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
-	if (rv)
-		return rv;
-
-	/*
-	 * Read switch status register. The bit definitions for switch control
-	 * and switch status resister are identical, so the control value can be
-	 * compared against the status value. The control switch has a debounce
-	 * (15 msec) before the status will reflect the control command.
-	 */
-	msleep(NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC);
-	rv = read_reg(port, NX20P348X_SWITCH_STATUS_REG, &status);
-	if (rv)
-		return rv;
-
-	return (status & NX20P348X_SWITCH_STATUS_HVSNK) == control ?
-		EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-__maybe_unused static int nx20p3481_vbus_source_enable(int port, int enable)
-{
-	int status;
-	int rv;
-	uint8_t previous_flags = flags[port];
-	int control = enable ? NX20P3481_SWITCH_CONTROL_5VSRC : 0;
-
-	rv = write_reg(port, NX20P348X_SWITCH_CONTROL_REG, control);
-	if (rv)
-		return rv;
-
-	/* Cache the anticipated Vbus state */
-	if (enable)
-		flags[port] |= NX20P348X_FLAGS_SOURCE_ENABLED;
-	else
-		flags[port] &= ~NX20P348X_FLAGS_SOURCE_ENABLED;
-
-	/*
-	 * Read switch status register. The bit definitions for switch control
-	 * and switch status resister are identical, so the control value can be
-	 * compared against the status value. The control switch has a debounce
-	 * (15 msec) before the status will reflect the control command.
-	 */
-	msleep(NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481)) {
-		rv = read_reg(port, NX20P348X_SWITCH_STATUS_REG, &status);
-		if (rv) {
-			flags[port] = previous_flags;
-			return rv;
-		}
-		if ((status & NX20P348X_SWITCH_STATUS_MASK) != control) {
-			flags[port] = previous_flags;
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int nx20p3483_vbus_sink_enable(int port, int enable)
-{
-	int rv;
-
-	enable = !!enable;
-
-	if (enable) {
-		/*
-		 * VBUS Discharge must be off in sink mode.
-		 */
-		rv = nx20p348x_discharge_vbus(port, 0);
-		if (rv)
-			return rv;
-	}
-
-	/*
-	 * We cannot use an EC GPIO for EN_SNK since an EC reset
-	 * will float the GPIO thus browning out the board (without
-	 * a battery).
-	 */
-	rv = tcpm_set_snk_ctrl(port, enable);
-	if (rv)
-		return rv;
-
-	for (int i = 0; i < NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC; ++i) {
-		int ds;
-		bool is_sink;
-
-		rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &ds);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		is_sink = (ds & NX20P3483_DEVICE_MODE_MASK) ==
-			NX20P3483_MODE_HV_SNK;
-		if (enable == is_sink)
-			return EC_SUCCESS;
-
-		msleep(1);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-__maybe_unused static int nx20p3483_vbus_source_enable(int port, int enable)
-{
-	int rv;
-
-	enable = !!enable;
-
-	/*
-	 * For parity's sake, we should not use an EC GPIO for
-	 * EN_SRC since we cannot use it for EN_SNK (for brown
-	 * out reason listed above).
-	 */
-	rv = tcpm_set_src_ctrl(port, enable);
-	if (rv)
-		return rv;
-
-	/*
-	 * Wait up to NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC for the status
-	 * to reflect the control command.
-	 */
-
-	for (int i = 0; i < NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC; ++i) {
-		int s;
-
-		rv = read_reg(port, NX20P348X_SWITCH_STATUS_REG, &s);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		if (!!(s & (NX20P348X_SWITCH_STATUS_5VSRC |
-			    NX20P348X_SWITCH_STATUS_HVSRC)) == enable) {
-			if (enable)
-				flags[port] |= NX20P348X_FLAGS_SOURCE_ENABLED;
-			else
-				flags[port] &= ~NX20P348X_FLAGS_SOURCE_ENABLED;
-			return EC_SUCCESS;
-		}
-		msleep(1);
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-static int nx20p348x_init(int port)
-{
-	int reg;
-	int mask;
-	int mode;
-	int rv;
-	enum tcpc_rp_value initial_current_limit;
-
-	/* Mask interrupts for interrupt 2 register */
-	mask = ~NX20P348X_INT2_EN_ERR;
-	rv = write_reg(port, NX20P348X_INTERRUPT2_MASK_REG, mask);
-	if (rv)
-		return rv;
-
-	/* Mask interrupts for interrupt 1 register */
-	mask = ~(NX20P348X_INT1_OC_5VSRC | NX20P348X_INT1_SC_5VSRC |
-		 NX20P348X_INT1_RCP_5VSRC | NX20P348X_INT1_DBEXIT_ERR);
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481)) {
-		/* Unmask Fast Role Swap detect interrupt */
-		mask &= ~NX20P3481_INT1_FRS_DET;
-	}
-	rv = write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask);
-	if (rv)
-		return rv;
-
-	/* Clear any pending interrupts by reading interrupt registers */
-	read_reg(port, NX20P348X_INTERRUPT1_REG, &reg);
-	read_reg(port, NX20P348X_INTERRUPT2_REG, &reg);
-
-	/* Get device  mode */
-	rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &mode);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481))
-		mode &= NX20P3481_DEVICE_MODE_MASK;
-	else if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3483))
-		mode &= NX20P3483_DEVICE_MODE_MASK;
-
-	/* Check if dead battery mode is active. */
-	if (mode == NX20P348X_MODE_DEAD_BATTERY) {
-		/*
-		 * If in dead battery mode, must enable HV SNK mode prior to
-		 * exiting dead battery mode or VBUS path will get cut off and
-		 * system will lose power. Before DB mode is exited, the device
-		 * mode will not reflect the correct value and therefore the
-		 * return value isn't useful here.
-		 */
-		nx20p348x_drv.vbus_sink_enable(port, 1);
-
-		/* Exit dead battery mode. */
-		rv = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &reg);
-		if (rv)
-			return rv;
-		reg |= NX20P348X_CTRL_DB_EXIT;
-		rv = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, reg);
-		if (rv)
-			return rv;
-	}
-
-	/*
-	 * Set VBUS over voltage threshold (OVLO). Note that while the PPC is in
-	 * dead battery mode, OVLO is forced to 6.8V, so this setting must be
-	 * done after dead battery mode is exited.
-	 */
-	nx20p348x_set_ovp_limit(port);
-
-	/* Set the Vbus current limit after dead battery mode exit */
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	initial_current_limit = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
-#else
-	initial_current_limit = TYPEC_RP_1A5;
-#endif
-	nx20p348x_set_vbus_source_current_limit(port, initial_current_limit);
-
-	/* Restore power-on reset value */
-	rv = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, 0);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-static void nx20p348x_handle_interrupt(int port)
-{
-	int reg;
-	int control_reg;
-
-	/*
-	 * Read interrupt 1 status register. Note, interrupt register is
-	 * automatically cleared by reading.
-	 */
-	read_reg(port, NX20P348X_INTERRUPT1_REG, &reg);
-
-	/* Check for DBEXIT error */
-	if (reg & NX20P348X_INT1_DBEXIT_ERR) {
-		int mask_reg;
-
-		/*
-		 * This failure is not expected. If for some reason, this
-		 * keeps happening, then log an error and mask the interrupt to
-		 * prevent interrupt floods.
-		 */
-		if (++db_exit_fail_count[port] >=
-		    NX20P348X_DB_EXIT_FAIL_THRESHOLD) {
-			ppc_prints("failed to exit DB mode", port);
-			if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
-				    &mask_reg)) {
-				mask_reg |= NX20P348X_INT1_DBEXIT_ERR;
-				write_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
-					  mask_reg);
-			}
-		}
-		read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &control_reg);
-		control_reg |= NX20P348X_CTRL_DB_EXIT;
-		write_reg(port, NX20P348X_DEVICE_CONTROL_REG, control_reg);
-		/*
-		 * If DB exit mode failed, then the OVP limit setting done in
-		 * the init routine will not be successful. Set the OVP limit
-		 * again here.
-		 */
-		nx20p348x_set_ovp_limit(port);
-	}
-
-	/* Check for 5V OC interrupt */
-	if (reg & NX20P348X_INT1_OC_5VSRC) {
-		ppc_prints("detected Vbus overcurrent!", port);
-		pd_handle_overcurrent(port);
-	}
-
-	/* Check for Vbus reverse current protection */
-	if (reg & NX20P348X_INT1_RCP_5VSRC)
-		ppc_prints("detected Vbus reverse current!", port);
-
-	/* Check for Vbus short protection */
-	if (reg & NX20P348X_INT1_SC_5VSRC)
-		ppc_prints("Vbus short detected!", port);
-
-	/* Check for FRS detection */
-	if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481) &&
-	    (reg & NX20P3481_INT1_FRS_DET)) {
-		/*
-		 * TODO(b/113069469): Need to check for CC status and verifiy
-		 * that a sink is attached to continue with FRS. If a sink is
-		 * not attached, then this FRS detect is a false detect which is
-		 * triggered when removing an external charger. If FRS was
-		 * detected by the PPC, then it has automatically  enabled the
-		 * 5V SRC mode and this must be undone for a proper detach.
-		 */
-		/* Check CC status */
-
-		/*
-		 * False detect, disable SRC mode which was enabled by
-		 * NX20P3481.
-		 */
-		ppc_prints("FRS false detect, disabling SRC mode!", port);
-		nx20p3481_vbus_source_enable(port, 0);
-	}
-
-	/*
-	 * Read interrupt 2 status register. Note, interrupt register is
-	 * automatically cleared by reading.
-	 */
-	/*
-	 * TODO (b/75272421): Not sure if any of these interrupts
-	 * will be used. Might want to use EN_ERR which tracks when both
-	 * SNK_EN and SRC_EN are set. However, since for the Analogix TCPC
-	 * these values aren't controlled by the EC directly, not sure what
-	 * action if any can be taken.
-	 */
-	read_reg(port, NX20P348X_INTERRUPT2_REG, &reg);
-}
-
-static void nx20p348x_irq_deferred(void)
-{
-	int i;
-	uint32_t pending = atomic_clear(&irq_pending);
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		if (BIT(i) & pending)
-			nx20p348x_handle_interrupt(i);
-}
-DECLARE_DEFERRED(nx20p348x_irq_deferred);
-
-void nx20p348x_interrupt(int port)
-{
-	atomic_or(&irq_pending, BIT(port));
-	hook_call_deferred(&nx20p348x_irq_deferred_data, 0);
-}
-
-#ifdef CONFIG_CMD_PPC_DUMP
-static int nx20p348x_dump(int port)
-{
-	int reg_addr;
-	int reg;
-	int rv;
-
-	ccprintf("Port %d NX20P348X registers\n", port);
-	for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <=
-		     NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
-		rv = read_reg(port, reg_addr, &reg);
-		if (rv) {
-			ccprintf("nx20p: Failed to read register 0x%x\n",
-				 reg_addr);
-			return rv;
-		}
-		ccprintf("[0x%02x]: 0x%02x\n", reg_addr, reg);
-
-		/* Flush every call otherwise buffer may get full */
-		cflush();
-	}
-
-	return EC_SUCCESS;
-}
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-/*
- * TODO (b/112697473): The NX20P348x PPCs do not support vbus detection or vconn
- * generation. However, if a different PPC does support these features and needs
- * these config options, then these functions do need to exist. The
- * configuration for what each PPC supports should be converted to bits within
- * a flags variable that is part of the ppc_config_t struct.
- */
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-static int nx20p348x_is_vbus_present(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-static int nx20p348x_set_polarity(int port, int polarity)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-#endif
-
-#ifdef CONFIG_USBC_PPC_VCONN
-static int nx20p348x_set_vconn(int port, int enable)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-#endif
-
-const struct ppc_drv nx20p348x_drv = {
-	.init = &nx20p348x_init,
-	.is_sourcing_vbus = &nx20p348x_is_sourcing_vbus,
-#ifdef CONFIG_USBC_PPC_NX20P3481
-	.vbus_sink_enable = &nx20p3481_vbus_sink_enable,
-	.vbus_source_enable = &nx20p3481_vbus_source_enable,
-#endif /* CONFIG_USBC_PPC_NX20P3481 */
-#ifdef CONFIG_USBC_PPC_NX20P3483
-	.vbus_sink_enable = &nx20p3483_vbus_sink_enable,
-	.vbus_source_enable = &nx20p3483_vbus_source_enable,
-#endif /* CONFIG_USBC_PPC_NX20P3483 */
-#ifdef CONFIG_CMD_PPC_DUMP
-	.reg_dump = &nx20p348x_dump,
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-	.set_vbus_source_current_limit =
-		&nx20p348x_set_vbus_source_current_limit,
-	.discharge_vbus = &nx20p348x_discharge_vbus,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-	.is_vbus_present = &nx20p348x_is_vbus_present,
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-#ifdef CONFIG_USBC_PPC_POLARITY
-	.set_polarity = &nx20p348x_set_polarity,
-#endif /* defined(CONFIG_USBC_PPC_POLARITY) */
-#ifdef CONFIG_USBC_PPC_VCONN
-	.set_vconn = &nx20p348x_set_vconn,
-#endif /* defined(CONFIG_USBC_PPC_VCONN) */
-};
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h
deleted file mode 100644
index 54c6dc40b5..0000000000
--- a/driver/ppc/nx20p348x.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NX20P348x Type-C Power Path Controller */
-
-#ifndef __CROS_EC_NX20P348X_H
-#define __CROS_EC_NX20P348X_H
-
-#define NX20P3483_ADDR0_FLAGS 0x70
-#define NX20P3483_ADDR1_FLAGS 0x71
-#define NX20P3483_ADDR2_FLAGS 0x72
-#define NX20P3483_ADDR3_FLAGS 0x73
-
-#define NX20P3481_ADDR0_FLAGS 0x74
-#define NX20P3481_ADDR1_FLAGS 0x75
-#define NX20P3481_ADDR2_FLAGS 0x76
-#define NX20P3481_ADDR3_FLAGS 0x77
-
-/*
- * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
- * mode. If we ever are every going to drop the PD rail, we need to first ensure
- * that Vbus is negotiated to below 6.8V otherwise we can lock out Vbus.
- */
-#define NX20P348X_SAFE_RESET_VBUS_MV 5000
-
-/* NX20P348x register addresses */
-#define NX20P348X_DEVICE_ID_REG			0x00
-#define NX20P348X_DEVICE_STATUS_REG		0x01
-#define NX20P348X_SWITCH_CONTROL_REG		0x02
-#define NX20P348X_SWITCH_STATUS_REG		0x03
-#define NX20P348X_INTERRUPT1_REG		0x04
-#define NX20P348X_INTERRUPT2_REG		0x05
-#define NX20P348X_INTERRUPT1_MASK_REG		0x06
-#define NX20P348X_INTERRUPT2_MASK_REG		0x07
-#define NX20P348X_OVLO_THRESHOLD_REG		0x08
-#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG	0x09
-#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG	0x0A
-#define NX20P348X_DEVICE_CONTROL_REG		0x0B
-
-/* Device Control Register (0x0B) */
-#define NX20P3483_CTRL_FRS_AT		BIT(3)
-#define NX20P348X_CTRL_DB_EXIT		BIT(2)
-#define NX20P348X_CTRL_VBUSDIS_EN	BIT(1)
-#define NX20P348X_CTRL_LDO_SD		BIT(0)
-
-/* Device Status Modes (0x01) */
-#define NX20P3481_DEVICE_MODE_MASK	0x3
-#define NX20P3483_DEVICE_MODE_MASK	0x7
-#define NX20P348X_MODE_DEAD_BATTERY	0
-/* After dead battery, mode values are different between 3481 and 3483 */
-#define NX20P3481_MODE_NORMAL		1
-#define NX20P3481_MODE_FRS		2
-#define NX20P3481_MODE_STANDBY		3
-
-#define NX20P3483_MODE_HV_SNK		1
-#define NX20P3483_MODE_5V_SRC		2
-#define NX20P3483_MODE_HV_SRC		3
-#define NX20P3483_MODE_STANDBY		4
-
-/* Switch Control Register (0x02) */
-#define NX20P3481_SWITCH_CONTROL_5VSRC	BIT(2)
-#define NX20P3481_SWITCH_CONTROL_HVSRC	BIT(1)
-#define NX20P3481_SWITCH_CONTROL_HVSNK	BIT(0)
-
-/* Switch Status Register (0x03) */
-#define NX20P348X_SWITCH_STATUS_5VSRC	BIT(2)
-#define NX20P348X_SWITCH_STATUS_HVSRC	BIT(1)
-#define NX20P348X_SWITCH_STATUS_HVSNK	BIT(0)
-#define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25
-#define NX20P348X_SWITCH_STATUS_MASK	0x7
-
-/* Internal 5V VBUS Switch Current Limit Settings (min) */
-#define NX20P348X_ILIM_MASK 0xF
-#define NX20P348X_ILIM_0_400  0
-#define NX20P348X_ILIM_0_600  1
-#define NX20P348X_ILIM_0_800  2
-#define NX20P348X_ILIM_1_000  3
-#define NX20P348X_ILIM_1_200  4
-#define NX20P348X_ILIM_1_400  5
-#define NX20P348X_ILIM_1_600  6
-#define NX20P348X_ILIM_1_800  7
-#define NX20P348X_ILIM_2_000  8
-#define NX20P348X_ILIM_2_200  9
-#define NX20P348X_ILIM_2_400 10
-#define NX20P348X_ILIM_2_600 11
-#define NX20P348X_ILIM_2_800 12
-#define NX20P348X_ILIM_3_000 13
-#define NX20P348X_ILIM_3_200 14
-#define NX20P348X_ILIM_3_400 15
-
-/* HV VBUS over voltage threshold settings V_mV*/
-#define NX20P348X_OVLO_THRESHOLD_MASK 0x7
-#define NX20P348X_OVLO_06_0 0
-#define NX20P348X_OVLO_06_8 1
-#define NX20P348X_OVLO_10_0 2
-#define NX20P348X_OVLO_11_5 3
-#define NX20P348X_OVLO_14_0 4
-#define NX20P348X_OVLO_17_0 5
-#define NX20P348X_OVLO_23_0 6
-
-/* Interrupt 1 Register Bits (0x04) */
-#define NX20P348X_INT1_DBEXIT_ERR	BIT(7)
-#define NX20P3481_INT1_FRS_DET		BIT(6)
-#define NX20P348X_INT1_OV_5VSRC		BIT(4)
-#define NX20P348X_INT1_RCP_5VSRC	BIT(3)
-#define NX20P348X_INT1_SC_5VSRC		BIT(2)
-#define NX20P348X_INT1_OC_5VSRC		BIT(1)
-#define NX20P348X_INT1_OTP		BIT(0)
-
-/* Interrupt 2 Register Bits (0x05) */
-#define NX20P348X_INT2_EN_ERR		BIT(7)
-#define NX20P348X_INT2_RCP_HVSNK	BIT(6)
-#define NX20P348X_INT2_SC_HVSNK		BIT(5)
-#define NX20P348X_INT2_OV_HVSNK		BIT(4)
-#define NX20P348X_INT2_RCP_HVSRC	BIT(3)
-#define NX20P348X_INT2_SC_HVSRC		BIT(2)
-#define NX20P348X_INT2_OC_HVSRC		BIT(1)
-#define NX20P348X_INT2_OV_HVSRC		BIT(0)
-
-struct ppc_drv;
-extern const struct ppc_drv nx20p348x_drv;
-
-/**
- * Interrupt Handler for the NX20P348x.
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void nx20p348x_interrupt(int port);
-
-#endif /* defined(__CROS_EC_NX20P348X_H) */
diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c
deleted file mode 100644
index 96cb789cd0..0000000000
--- a/driver/ppc/rt1718s.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Richtek RT1718S USB-C Power Path Controller */
-#include "atomic.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "driver/ppc/rt1718s.h"
-#include "driver/tcpm/tcpci.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-
-#define RT1718S_FLAGS_SOURCE_ENABLED BIT(0)
-static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static int read_reg(uint8_t port, int reg, int *val)
-{
-	if (reg > 0xFF) {
-		return i2c_read_offset16(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val, 1);
-	} else {
-		return i2c_read8(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val);
-	}
-}
-
-static int write_reg(uint8_t port, int reg, int val)
-{
-	if (reg > 0xFF) {
-		return i2c_write_offset16(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val, 1);
-	} else {
-		return i2c_write8(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val);
-	}
-}
-
-static int update_bits(int port, int reg, int mask, int val)
-{
-	int reg_val;
-
-	if (mask == 0xFF)
-		return write_reg(port, reg, val);
-
-	RETURN_ERROR(read_reg(port, reg, &reg_val));
-
-	reg_val &= (~mask);
-	reg_val |= (mask & val);
-	return write_reg(port, reg, reg_val);
-}
-
-static int rt1718s_is_sourcing_vbus(int port)
-{
-	return (flags[port] & RT1718S_FLAGS_SOURCE_ENABLED);
-}
-
-static int rt1718s_vbus_source_enable(int port, int enable)
-{
-	atomic_t prev_flag;
-
-	if (enable)
-		prev_flag = atomic_or(&flags[port],
-				RT1718S_FLAGS_SOURCE_ENABLED);
-	else
-		prev_flag = atomic_clear_bits(&flags[port],
-				RT1718S_FLAGS_SOURCE_ENABLED);
-
-	/* Return if status doesn't change */
-	if (!!(prev_flag & RT1718S_FLAGS_SOURCE_ENABLED) == !!enable)
-		return EC_SUCCESS;
-
-	RETURN_ERROR(tcpm_set_src_ctrl(port, enable));
-
-#if defined(CONFIG_USB_CHARGER) && defined(CONFIG_USB_PD_VBUS_DETECT_PPC)
-	/*
-	 * Since the VBUS state could be changing here, need to wake the
-	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
-	 */
-	usb_charger_vbus_change(port, enable);
-#endif
-
-	return EC_SUCCESS;
-}
-
-static int rt1718s_vbus_sink_enable(int port, int enable)
-{
-	return tcpm_set_snk_ctrl(port, enable);
-}
-
-static int rt1718s_discharge_vbus(int port, int enable)
-{
-	return update_bits(port,
-		TCPC_REG_POWER_CTRL,
-		TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
-		enable ? 0xFF : 0x00);
-}
-
-#ifdef CONFIG_CMD_PPC_DUMP
-static int rt1718s_dump(int port)
-{
-	for (int i = 0; i <= 0xEF; i++) {
-		int val = 0;
-		int rt = read_reg(port, i, &val);
-
-		if (i % 16 == 0)
-			CPRINTF("%02X: ", i);
-		if (rt)
-			CPRINTF("-- ");
-		else
-			CPRINTF("%02X ", val);
-		if (i % 16 == 15)
-			CPRINTF("\n");
-	}
-	for (int i = 0xF200; i <= 0xF2CF; i++) {
-		int val = 0;
-		int rt = read_reg(port, i, &val);
-
-		if (i % 16 == 0)
-			CPRINTF("%04X: ", i);
-		if (rt)
-			CPRINTF("-- ");
-		else
-			CPRINTF("%02X ", val);
-		if (i % 16 == 15)
-			CPRINTF("\n");
-	}
-
-	return EC_SUCCESS;
-}
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-static int rt1718s_is_vbus_present(int port)
-{
-	__maybe_unused static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT];
-	int status, vbus;
-
-	if (read_reg(port, TCPC_REG_POWER_STATUS, &status))
-		return 0;
-
-	vbus = !!(status & TCPC_REG_POWER_STATUS_VBUS_PRES);
-
-#ifdef CONFIG_USB_CHARGER
-	if (!!(vbus_prev[port] != vbus))
-		usb_charger_vbus_change(port, vbus);
-
-	if (vbus)
-		atomic_or(&vbus_prev[port], 1);
-	else
-		atomic_clear(&vbus_prev[port]);
-#endif
-
-	return vbus;
-}
-#endif
-
-static int rt1718s_init(int port)
-{
-	atomic_clear(&flags[port]);
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
-		/* Set Rx frs unmasked */
-		RETURN_ERROR(update_bits(port, RT1718S_RT_MASK1,
-					RT1718S_RT_MASK1_M_RX_FRS,
-					0xFF));
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-static int rt1718s_set_polarity(int port, int polarity)
-{
-	return tcpci_tcpm_set_polarity(port, polarity);
-}
-#endif
-
-#ifdef CONFIG_USB_PD_FRS_PPC
-static int rt1718s_set_frs_enable(int port, int enable)
-{
-	/*
-	 * Use write instead of update to save 2 i2c read.
-	 * Assume other bits are at their reset value.
-	 */
-	int frs_ctrl2 = 0x10, vbus_ctrl_en = 0x3F;
-
-	if (enable) {
-		frs_ctrl2 |= RT1718S_FRS_CTRL2_RX_FRS_EN;
-		frs_ctrl2 |= RT1718S_FRS_CTRL2_VBUS_FRS_EN;
-
-		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN;
-		vbus_ctrl_en |= RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN;
-	}
-
-	RETURN_ERROR(write_reg(port, RT1718S_FRS_CTRL2, frs_ctrl2));
-	RETURN_ERROR(write_reg(port, RT1718S_VBUS_CTRL_EN, vbus_ctrl_en));
-	return EC_SUCCESS;
-}
-#endif
-
-const struct ppc_drv rt1718s_ppc_drv = {
-	.init = &rt1718s_init,
-	.is_sourcing_vbus = &rt1718s_is_sourcing_vbus,
-	.vbus_sink_enable = &rt1718s_vbus_sink_enable,
-	.vbus_source_enable = &rt1718s_vbus_source_enable,
-#ifdef CONFIG_CMD_PPC_DUMP
-	.reg_dump = &rt1718s_dump,
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-	.is_vbus_present = &rt1718s_is_vbus_present,
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-	.discharge_vbus = &rt1718s_discharge_vbus,
-#ifdef CONFIG_USBC_PPC_POLARITY
-	.set_polarity = &rt1718s_set_polarity,
-#endif
-#ifdef CONFIG_USBC_PPC_VCONN
-	.set_vconn = &tcpci_tcpm_set_vconn,
-#endif
-#ifdef CONFIG_USB_PD_FRS_PPC
-	.set_frs_enable = rt1718s_set_frs_enable,
-#endif
-};
diff --git a/driver/ppc/rt1718s.h b/driver/ppc/rt1718s.h
deleted file mode 100644
index f692bf3dd4..0000000000
--- a/driver/ppc/rt1718s.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Richtek RT1718S Type-C Power Path Controller */
-
-#ifndef __CROS_EC_PPC_RT1718S_H
-#define __CROS_EC_PPC_RT1718S_H
-
-#include "driver/tcpm/rt1718s.h"
-#include "usbc_ppc.h"
-
-extern const struct ppc_drv rt1718s_ppc_drv;
-
-#endif /* defined(__CROS_EC_PPC_RT1718S_H) */
-
diff --git a/driver/ppc/sn5s330.c b/driver/ppc/sn5s330.c
deleted file mode 100644
index 4abf85cf50..0000000000
--- a/driver/ppc/sn5s330.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TI SN5S330 USB-C Power Path Controller */
-
-/*
- * PP1 : Sourcing power path.
- * PP2 : Sinking power path.
- */
-
-#include "common.h"
-#include "console.h"
-#include "sn5s330.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
-static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int read_reg(uint8_t port, int reg, int *regval)
-{
-	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
-}
-
-static int write_reg(uint8_t port, int reg, int regval)
-{
-	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
-}
-
-static int set_flags(const int port, const int addr, const int flags_to_set)
-{
-	int val, rv;
-
-	rv = read_reg(port, addr, &val);
-	if (rv)
-		return rv;
-
-	val |= flags_to_set;
-
-	return write_reg(port, addr, val);
-}
-
-
-static int clr_flags(const int port, const int addr, const int flags_to_clear)
-{
-	int val, rv;
-
-	rv = read_reg(port, addr, &val);
-	if (rv)
-		return rv;
-
-	val &= ~flags_to_clear;
-
-	return write_reg(port, addr, val);
-}
-
-#ifdef CONFIG_CMD_PPC_DUMP
-static int sn5s330_dump(int port)
-{
-	int i;
-	int data;
-	const int i2c_port = ppc_chips[port].i2c_port;
-	const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
-
-	/* Flush after every set otherwise console buffer may get full. */
-
-	for (i = SN5S330_FUNC_SET1; i <= SN5S330_FUNC_SET12; i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("FUNC_SET%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_FUNC_SET1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	for (i = SN5S330_INT_STATUS_REG1; i <= SN5S330_INT_STATUS_REG4; i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("INT_STATUS_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_STATUS_REG1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	for (i = SN5S330_INT_TRIP_RISE_REG1; i <= SN5S330_INT_TRIP_RISE_REG3;
-	     i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("INT_TRIP_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_RISE_REG1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	for (i = SN5S330_INT_TRIP_FALL_REG1; i <= SN5S330_INT_TRIP_FALL_REG3;
-	     i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("INT_TRIP_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_FALL_REG1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	for (i = SN5S330_INT_MASK_RISE_REG1; i <= SN5S330_INT_MASK_RISE_REG3;
-	     i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("INT_MASK_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_RISE_REG1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	for (i = SN5S330_INT_MASK_FALL_REG1; i <= SN5S330_INT_MASK_FALL_REG3;
-	     i++) {
-		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
-		ccprintf("INT_MASK_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_FALL_REG1 + 1,
-			 i,
-			 data);
-	}
-
-	cflush();
-
-	return EC_SUCCESS;
-}
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-static int sn5s330_pp_fet_enable(uint8_t port, enum sn5s330_pp_idx pp,
-				 int enable)
-{
-	int status;
-	int pp_bit;
-
-	if (pp == SN5S330_PP1)
-		pp_bit = SN5S330_PP1_EN;
-	else if (pp == SN5S330_PP2)
-		pp_bit = SN5S330_PP2_EN;
-	else
-		return EC_ERROR_INVAL;
-
-	status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit)
-			: clr_flags(port, SN5S330_FUNC_SET3, pp_bit);
-
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET3!", port);
-		return status;
-	}
-
-	if (pp == SN5S330_PP1)
-		source_enabled[port] = enable;
-
-	return EC_SUCCESS;
-}
-
-static int sn5s330_init(int port)
-{
-	int regval;
-	int status;
-	int retries;
-	int reg;
-	const int i2c_port  = ppc_chips[port].i2c_port;
-	const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Set the sourcing current limit value. */
-	switch (CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) {
-	case TYPEC_RP_3A0:
-		/* Set current limit to ~3A. */
-		regval = SN5S330_ILIM_3_06;
-		break;
-
-	case TYPEC_RP_1A5:
-	default:
-		/* Set current limit to ~1.5A. */
-		regval = SN5S330_ILIM_1_62;
-		break;
-	}
-#else /* !defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-	/* Default SRC current limit to ~1.5A. */
-	regval = SN5S330_ILIM_1_62;
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/*
-	 * It seems that sometimes setting the FUNC_SET1 register fails
-	 * initially.  Therefore, we'll retry a couple of times.
-	 */
-	retries = 0;
-	do {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    SN5S330_FUNC_SET1, regval);
-		if (status) {
-			ppc_prints("Failed to set FUNC_SET1! Retrying..",
-				port);
-			retries++;
-			msleep(1);
-		} else {
-			break;
-		}
-	} while (retries < 10);
-
-	/* Set Vbus OVP threshold to ~22.325V. */
-	regval = 0x37;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET5, regval);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET5!", port);
-		return status;
-	}
-
-	/* Set Vbus UVP threshold to ~2.75V. */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET6, &regval);
-	if (status) {
-		ppc_prints("Failed to read FUNC_SET6!", port);
-		return status;
-	}
-	regval &= ~0x3F;
-	regval |= 1;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET6, regval);
-	if (status) {
-		ppc_prints("Failed to write FUNC_SET6!", port);
-		return status;
-	}
-
-	/* Enable SBU Fets and set PP2 current limit to ~3A. */
-	regval = SN5S330_SBU_EN | 0x8;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET2, regval);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET2!", port);
-		return status;
-	}
-
-	/*
-	 * Indicate we are using PP2 configuration 2 and enable OVP comparator
-	 * for CC lines.
-	 *
-	 * Also, turn off under-voltage protection for incoming Vbus as it would
-	 * prevent us from enabling SNK path before we hibernate the ec. We
-	 * need to enable the SNK path so USB power will assert ACOK and wake
-	 * the EC up went inserting USB power. We always turn off under-voltage
-	 * protection because the battery charger will boost the voltage up
-	 * to the needed battery voltage either way (and it will have its own
-	 * low voltage protection).
-	 */
-	regval = SN5S330_OVP_EN_CC | SN5S330_PP2_CONFIG | SN5S330_CONFIG_UVP;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET9, regval);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET9!", port);
-		return status;
-	}
-
-	/*
-	 * Set analog current limit delay to 200 us for PP1,
-	 * set 1000 us for PP2 for compatibility.
-	 */
-	regval = (PPX_ILIM_DEGLITCH_0_US_200 << 3) |
-		  PPX_ILIM_DEGLITCH_0_US_1000;
-	status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET11,
-			    regval);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET11", port);
-		return status;
-	}
-
-#ifdef CONFIG_USBC_PPC_VCONN
-	/*
-	 * Set the deglitch timeout on the Vconn current limit to 640us.  This
-	 * improves compatibility with some USB C -> HDMI devices versus the
-	 * reset default (20 us).
-	 */
-	regval = 0;
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET8, &regval);
-	if (status) {
-		ppc_prints("Failed to read FUNC_SET8!", port);
-		return status;
-	}
-	regval &= ~SN5S330_VCONN_DEGLITCH_MASK;
-	regval |= SN5S330_VCONN_DEGLITCH_640_US;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET8, regval);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET8!", port);
-		return status;
-	}
-#endif /* CONFIG_USBC_PPC_VCONN */
-
-	/*
-	 * Turn off dead battery resistors, turn on CC FETs, and set the higher
-	 * of the two VCONN current limits (min 0.6A).  Many VCONN accessories
-	 * trip the default current limit of min 0.35A.
-	 */
-	status = set_flags(port, SN5S330_FUNC_SET4,
-			   SN5S330_CC_EN | SN5S330_VCONN_ILIM_SEL);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET4!", port);
-		return status;
-	}
-
-	/* Set ideal diode mode for both PP1 and PP2. */
-	status = set_flags(port, SN5S330_FUNC_SET3,
-			   SN5S330_SET_RCP_MODE_PP1 | SN5S330_SET_RCP_MODE_PP2);
-	if (status) {
-		ppc_prints("Failed to set FUNC_SET3!", port);
-		return status;
-	}
-
-	/* Turn off PP1 FET. */
-	status = sn5s330_pp_fet_enable(port, SN5S330_PP1, 0);
-	if (status) {
-		ppc_prints("Failed to turn off PP1 FET!", port);
-	}
-
-	/*
-	 * Don't proceed with the rest of initialization if we're sysjumping.
-	 * We would have already done this before.
-	 */
-	if (system_jumped_late())
-		return EC_SUCCESS;
-
-	/*
-	 * Clear the digital reset bit, and mask off and clear vSafe0V
-	 * interrupts. Leave the dead battery mode bit unchanged since it
-	 * is checked below.
-	 */
-	regval = SN5S330_DIG_RES | SN5S330_VSAFE0V_MASK;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_STATUS_REG4, regval);
-	if (status) {
-		ppc_prints("Failed to write INT_STATUS_REG4!", port);
-		return status;
-	}
-
-	/*
-	 * Before turning on the PP2 FET, mask off all unwanted interrupts and
-	 * then clear all pending interrupts.
-	 *
-	 * TODO(aaboagye): Unmask fast-role swap events once fast-role swap is
-	 * implemented in the PD stack.
-	 */
-
-	/* Enable PP1 overcurrent interrupts. */
-	regval = ~SN5S330_ILIM_PP1_MASK;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_RISE_REG1, regval);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_RISE1!", port);
-		return status;
-	}
-
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_FALL_REG1, 0xFF);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_FALL1!", port);
-		return status;
-	}
-
-	/* Enable VCONN overcurrent and CC1/CC2 overvoltage interrupts. */
-	regval = ~(SN5S330_VCONN_ILIM | SN5S330_CC1_CON | SN5S330_CC2_CON);
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_RISE_REG2, regval);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_RISE2!", port);
-		return status;
-	}
-
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_FALL_REG2, 0xFF);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_FALL2!", port);
-		return status;
-	}
-
-#if defined(CONFIG_USB_PD_VBUS_DETECT_PPC) && defined(CONFIG_USB_CHARGER)
-	/* If PPC is being used to detect VBUS, enable VBUS interrupts. */
-	regval = ~SN5S330_VBUS_GOOD_MASK;
-#else
-	regval = 0xFF;
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
-
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_RISE_REG3, regval);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_RISE3!", port);
-		return status;
-	}
-
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_MASK_FALL_REG3, regval);
-	if (status) {
-		ppc_prints("Failed to write INT_MASK_FALL3!", port);
-		return status;
-	}
-
-	/* Now clear any pending interrupts. */
-	for (reg = SN5S330_INT_TRIP_RISE_REG1;
-	     reg <= SN5S330_INT_TRIP_FALL_REG3;
-	     reg++) {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    reg, 0xFF);
-		if (status) {
-			CPRINTS("ppc p%d: Failed to write reg 0x%2x!",
-				port, reg);
-			return status;
-		}
-	}
-
-
-	/*
-	 * For PP2, check to see if we booted in dead battery mode.  If we
-	 * booted in dead battery mode, the PP2 FET will already be enabled.
-	 */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, &regval);
-	if (status) {
-		ppc_prints("Failed to read INT_STATUS_REG4!", port);
-		return status;
-	}
-
-	if (regval & SN5S330_DB_BOOT) {
-		/*
-		 * Clear the bit by writing 1 and keep vSafe0V_MASK
-		 * unchanged.
-		 */
-		i2c_write8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, regval);
-
-		/* Turn on PP2 FET. */
-		status = sn5s330_pp_fet_enable(port, SN5S330_PP2, 1);
-		if (status) {
-			ppc_prints("Failed to turn on PP2 FET!", port);
-			return status;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-static int sn5s330_is_vbus_present(int port)
-{
-	int regval;
-	int rv;
-
-	rv = read_reg(port, SN5S330_INT_STATUS_REG3, &regval);
-	if (rv) {
-		ppc_err_prints("VBUS present error", port, rv);
-		return 0;
-	}
-
-	return !!(regval & SN5S330_VBUS_GOOD);
-}
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-
-static int sn5s330_is_sourcing_vbus(int port)
-{
-	return source_enabled[port];
-}
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-static int sn5s330_set_polarity(int port, int polarity)
-{
-	if (polarity)
-		/* CC2 active. */
-		return set_flags(port, SN5S330_FUNC_SET4, SN5S330_CC_POLARITY);
-	else
-		/* CC1 active. */
-		return clr_flags(port, SN5S330_FUNC_SET4, SN5S330_CC_POLARITY);
-}
-#endif
-
-static int sn5s330_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
-{
-	int regval;
-	int status;
-
-	status = read_reg(port, SN5S330_FUNC_SET1, &regval);
-	if (status)
-		return status;
-
-	/*
-	 * Note that we chose the lowest current limit setting that is just
-	 * above indicated Rp value.  This is because these are minimum values
-	 * and we must be able to provide the current that we advertise.
-	 */
-	regval &= ~0x1F; /* The current limit settings are 4:0. */
-	switch (rp) {
-	case TYPEC_RP_3A0:
-		regval |= SN5S330_ILIM_3_06;
-		break;
-
-	case TYPEC_RP_1A5:
-		regval |= SN5S330_ILIM_1_62;
-		break;
-
-	case TYPEC_RP_USB:
-	default:
-		regval |= SN5S330_ILIM_0_63;
-		break;
-	};
-
-	status = write_reg(port, SN5S330_FUNC_SET1, regval);
-
-	return status;
-}
-
-static int sn5s330_discharge_vbus(int port, int enable)
-{
-	int status = enable ? set_flags(port, SN5S330_FUNC_SET3,
-					SN5S330_VBUS_DISCH_EN)
-			    : clr_flags(port, SN5S330_FUNC_SET3,
-					SN5S330_VBUS_DISCH_EN);
-
-	if (status) {
-		CPRINTS("ppc p%d: Failed to %s vbus discharge",
-			port, enable ? "enable" : "disable");
-		return status;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int sn5s330_enter_low_power_mode(int port)
-{
-	int rv;
-
-	/* Turn off both SRC and SNK FETs */
-	rv = clr_flags(port, SN5S330_FUNC_SET3,
-		       SN5S330_PP1_EN | SN5S330_PP2_EN);
-
-	if (rv) {
-		ppc_err_prints("Could not disable both FETS", port, rv);
-		return rv;
-	}
-
-	/* Turn off Vconn power */
-	rv = clr_flags(port, SN5S330_FUNC_SET4, SN5S330_VCONN_EN);
-
-	if (rv) {
-		ppc_err_prints("Could not disable Vconn", port, rv);
-		return rv;
-	}
-
-	/* Turn off SBU path */
-	rv = clr_flags(port, SN5S330_FUNC_SET2, SN5S330_SBU_EN);
-
-	if (rv) {
-		ppc_err_prints("Could not disable SBU path", port, rv);
-		return rv;
-	}
-
-	/*
-	 * Turn off the Over Voltage Protection circuits. Needs to happen after
-	 * FETs are disabled, otherwise OVP can automatically turned back on.
-	 * Since FETs are off, any over voltage does not make it to the board
-	 * side of the PPC.
-	 */
-	rv = clr_flags(port, SN5S330_FUNC_SET9,
-		       SN5S330_FORCE_OVP_EN_SBU | SN5S330_FORCE_ON_VBUS_OVP |
-			       SN5S330_FORCE_ON_VBUS_UVP);
-
-	if (rv) {
-		ppc_err_prints("Could not disable OVP circuit", port, rv);
-		return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USBC_PPC_VCONN
-static int sn5s330_set_vconn(int port, int enable)
-{
-	int regval;
-	int status;
-
-	status = read_reg(port, SN5S330_FUNC_SET4, &regval);
-	if (status)
-		return status;
-
-	if (enable)
-		regval |= SN5S330_VCONN_EN;
-	else
-		regval &= ~SN5S330_VCONN_EN;
-
-	return write_reg(port, SN5S330_FUNC_SET4, regval);
-}
-#endif
-
-static int sn5s330_vbus_sink_enable(int port, int enable)
-{
-	return sn5s330_pp_fet_enable(port, SN5S330_PP2, !!enable);
-}
-
-static int sn5s330_vbus_source_enable(int port, int enable)
-{
-	return sn5s330_pp_fet_enable(port, SN5S330_PP1, !!enable);
-}
-
-#ifdef CONFIG_USBC_PPC_SBU
-static int sn5s330_set_sbu(int port, int enable)
-{
-	int rv;
-
-	if (enable)
-		rv = set_flags(port, SN5S330_FUNC_SET2, SN5S330_SBU_EN);
-	else
-		rv = clr_flags(port, SN5S330_FUNC_SET2, SN5S330_SBU_EN);
-
-	return rv;
-}
-#endif /* CONFIG_USBC_PPC_SBU */
-
-static void sn5s330_handle_interrupt(int port)
-{
-	int attempt = 0;
-
-	/*
-	 * SN5S330's /INT pin is level, so process interrupts until it
-	 * deasserts if the chip has a dedicated interrupt pin.
-	 */
-#ifdef CONFIG_USBC_PPC_DEDICATED_INT
-	while (ppc_get_alert_status(port))
-#endif
-	{
-		int rise = 0;
-		int fall = 0;
-
-		attempt++;
-
-		if (attempt > 1)
-			ppc_prints("Could not clear interrupts on first "
-				"try, retrying", port);
-
-		read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise);
-		read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall);
-
-		/* Notify the system about the overcurrent event. */
-		if (rise & SN5S330_ILIM_PP1_MASK)
-			pd_handle_overcurrent(port);
-
-		/* Clear the interrupt sources. */
-		write_reg(port, SN5S330_INT_TRIP_RISE_REG1, rise);
-		write_reg(port, SN5S330_INT_TRIP_FALL_REG1, fall);
-
-		read_reg(port, SN5S330_INT_TRIP_RISE_REG2, &rise);
-		read_reg(port, SN5S330_INT_TRIP_FALL_REG2, &fall);
-
-		/*
-		 * VCONN may be latched off due to an overcurrent.  Indicate
-		 * when the VCONN overcurrent happens.
-		 */
-		if (rise & SN5S330_VCONN_ILIM)
-			ppc_prints("VCONN OC!", port);
-
-		/* Notify the system about the CC overvoltage event. */
-		if (rise & SN5S330_CC1_CON || rise & SN5S330_CC2_CON) {
-			ppc_prints("CC OV!", port);
-			pd_handle_cc_overvoltage(port);
-		}
-
-		/* Clear the interrupt sources. */
-		write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise);
-		write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall);
-
-#if defined(CONFIG_USB_PD_VBUS_DETECT_PPC) && defined(CONFIG_USB_CHARGER)
-		read_reg(port, SN5S330_INT_TRIP_RISE_REG3, &rise);
-		read_reg(port, SN5S330_INT_TRIP_FALL_REG3, &fall);
-
-		/* Inform other modules about VBUS level */
-		if (rise & SN5S330_VBUS_GOOD_MASK
-		    || fall & SN5S330_VBUS_GOOD_MASK)
-			usb_charger_vbus_change(port,
-						sn5s330_is_vbus_present(port));
-
-		/* Clear the interrupt sources. */
-		write_reg(port, SN5S330_INT_TRIP_RISE_REG3, rise);
-		write_reg(port, SN5S330_INT_TRIP_FALL_REG3, fall);
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
-
-	}
-}
-
-static void sn5s330_irq_deferred(void)
-{
-	int i;
-	uint32_t pending = atomic_clear(&irq_pending);
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		if (BIT(i) & pending)
-			sn5s330_handle_interrupt(i);
-}
-DECLARE_DEFERRED(sn5s330_irq_deferred);
-
-void sn5s330_interrupt(int port)
-{
-	atomic_or(&irq_pending, BIT(port));
-	hook_call_deferred(&sn5s330_irq_deferred_data, 0);
-}
-
-const struct ppc_drv sn5s330_drv = {
-	.init = &sn5s330_init,
-	.is_sourcing_vbus = &sn5s330_is_sourcing_vbus,
-	.vbus_sink_enable = &sn5s330_vbus_sink_enable,
-	.vbus_source_enable = &sn5s330_vbus_source_enable,
-	.set_vbus_source_current_limit = &sn5s330_set_vbus_source_current_limit,
-	.discharge_vbus = &sn5s330_discharge_vbus,
-	.enter_low_power_mode = &sn5s330_enter_low_power_mode,
-#ifdef CONFIG_CMD_PPC_DUMP
-	.reg_dump = &sn5s330_dump,
-#endif
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-	.is_vbus_present = &sn5s330_is_vbus_present,
-#endif
-#ifdef CONFIG_USBC_PPC_POLARITY
-	.set_polarity = &sn5s330_set_polarity,
-#endif
-#ifdef CONFIG_USBC_PPC_SBU
-	.set_sbu = &sn5s330_set_sbu,
-#endif /* defined(CONFIG_USBC_PPC_SBU) */
-#ifdef CONFIG_USBC_PPC_VCONN
-	.set_vconn = &sn5s330_set_vconn,
-#endif
-};
diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h
deleted file mode 100644
index f94a3e8e10..0000000000
--- a/driver/ppc/sn5s330.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TI SN5S330 Type-C Power Path Controller */
-
-#ifndef __CROS_EC_SN5S330_H
-#define __CROS_EC_SN5S330_H
-
-#include "common.h"
-
-#include "driver/ppc/sn5s330_public.h"
-
-struct sn5s330_config {
-	uint8_t i2c_port;
-	uint8_t i2c_addr_flags;
-};
-
-extern const struct sn5s330_config sn5s330_chips[];
-extern const unsigned int sn5s330_cnt;
-
-/* Power Path Indices */
-enum sn5s330_pp_idx {
-	SN5S330_PP1,
-	SN5S330_PP2,
-	SN5S330_PP_COUNT,
-};
-
-#define SN5S330_FUNC_SET1  0x50
-#define SN5S330_FUNC_SET2  0x51
-#define SN5S330_FUNC_SET3  0x52
-#define SN5S330_FUNC_SET4  0x53
-#define SN5S330_FUNC_SET5  0x54
-#define SN5S330_FUNC_SET6  0x55
-#define SN5S330_FUNC_SET7  0x56
-#define SN5S330_FUNC_SET8  0x57
-#define SN5S330_FUNC_SET9  0x58
-#define SN5S330_FUNC_SET10 0x59
-#define SN5S330_FUNC_SET11 0x5A
-#define SN5S330_FUNC_SET12 0x5B
-
-#define SN5S330_INT_STATUS_REG1 0x2F
-#define SN5S330_INT_STATUS_REG2 0x30
-#define SN5S330_INT_STATUS_REG3 0x31
-#define SN5S330_INT_STATUS_REG4 0x32
-
-#define SN5S330_INT_TRIP_RISE_REG1 0x20
-#define SN5S330_INT_TRIP_RISE_REG2 0x21
-#define SN5S330_INT_TRIP_RISE_REG3 0x22
-#define SN5S330_INT_TRIP_FALL_REG1 0x23
-#define SN5S330_INT_TRIP_FALL_REG2 0x24
-#define SN5S330_INT_TRIP_FALL_REG3 0x25
-
-#define SN5S330_INT_MASK_RISE_REG1 0x26
-#define SN5S330_INT_MASK_RISE_REG2 0x27
-#define SN5S330_INT_MASK_RISE_REG3 0x28
-#define SN5S330_INT_MASK_FALL_REG1 0x29
-#define SN5S330_INT_MASK_FALL_REG2 0x2A
-#define SN5S330_INT_MASK_FALL_REG3 0x2B
-
-#define PPX_ILIM_DEGLITCH_0_US_20     0x1
-#define PPX_ILIM_DEGLITCH_0_US_50     0x2
-#define PPX_ILIM_DEGLITCH_0_US_100    0x3
-#define PPX_ILIM_DEGLITCH_0_US_200    0x4
-#define PPX_ILIM_DEGLITCH_0_US_1000   0x5
-#define PPX_ILIM_DEGLITCH_0_US_2000   0x6
-#define PPX_ILIM_DEGLITCH_0_US_10000  0x7
-
-/* Internal VBUS Switch Current Limit Settings (min) */
-#define SN5S330_ILIM_0_35  0
-#define SN5S330_ILIM_0_63  1
-#define SN5S330_ILIM_0_90  2
-#define SN5S330_ILIM_1_14  3
-#define SN5S330_ILIM_1_38  4
-#define SN5S330_ILIM_1_62  5
-#define SN5S330_ILIM_1_86  6
-#define SN5S330_ILIM_2_10  7
-#define SN5S330_ILIM_2_34  8
-#define SN5S330_ILIM_2_58  9
-#define SN5S330_ILIM_2_82  10
-#define SN5S330_ILIM_3_06  11
-#define SN5S330_ILIM_3_30  12
-
-/* FUNC_SET_2 */
-#define SN5S330_SBU_EN			BIT(4)
-
-/* FUNC_SET_3 */
-#define SN5S330_PP1_EN			BIT(0)
-#define SN5S330_PP2_EN			BIT(1)
-#define SN5S330_VBUS_DISCH_EN		BIT(2)
-#define SN5S330_SET_RCP_MODE_PP1	BIT(5)
-#define SN5S330_SET_RCP_MODE_PP2	BIT(6)
-
-/* FUNC_SET_4 */
-#define SN5S330_VCONN_EN		BIT(0)
-#define SN5S330_CC_POLARITY		BIT(1)
-#define SN5S330_CC_EN			BIT(4)
-#define SN5S330_VCONN_ILIM_SEL		BIT(5)
-
-/* FUNC_SET_8 */
-#define SN5S330_VCONN_DEGLITCH_MASK	(3 << 6)
-#define SN5S330_VCONN_DEGLITCH_63_US	(0 << 6)
-#define SN5S330_VCONN_DEGLITCH_125_US	BIT(6)
-#define SN5S330_VCONN_DEGLITCH_640_US	(2 << 6)
-#define SN5S330_VCONN_DEGLITCH_1280_US	(3 << 6)
-
-/* FUNC_SET_9 */
-#define SN5S330_FORCE_OVP_EN_SBU	BIT(1)
-#define SN5S330_PP2_CONFIG		BIT(2)
-#define SN5S330_OVP_EN_CC		BIT(4)
-#define SN5S330_CONFIG_UVP		BIT(5)
-#define SN5S330_FORCE_ON_VBUS_OVP	BIT(6)
-#define SN5S330_FORCE_ON_VBUS_UVP	BIT(7)
-
-/* INT_STATUS_REG3 */
-#define SN5S330_VBUS_GOOD		BIT(0)
-
-/* INT_STATUS_REG4 */
-#define SN5S330_DIG_RES			BIT(0)
-#define SN5S330_DB_BOOT			BIT(1)
-#define SN5S330_VSAFE0V_STAT		BIT(2)
-#define SN5S330_VSAFE0V_MASK		BIT(3)
-
-/*
- * INT_MASK_RISE/FALL_EDGE_1
- *
- * The ILIM_PP1 bit indicates an overcurrent condition when sourcing on power
- * path 1.  For rising edge registers, this indicates an overcurrent has
- * occured; similarly for falling edge, it means the overcurrent condition is no
- * longer present.
- */
-#define SN5S330_ILIM_PP1_MASK BIT(4)
-
-/*
- * INT_MASK_RISE/FALL_EDGE2
- *
- * The VCONN_ILIM bit indicates an overcurrent condition on VCONN.  By default,
- * VCONN will be latched off.
- */
-#define SN5S330_VCONN_ILIM (1 << 1)
-
-/*
- * INT_MASK_RISE/FALL_EDGE2
- *
- * The OV_CC1_CON/OV_CC2_CON bit indicates an over-voltage occurred on
- * C_CC1/C_CC2.
- */
-#define SN5S330_CC1_CON (1 << 2)
-#define SN5S330_CC2_CON (1 << 3)
-
-/*
- * INT_MASK_RISE/FALL_EDGE_3
- *
- * The VBUS_GOOD bit indicates VBUS has increased beyond a 4.0V threshold.
- * For rising edge registers, this indicates VBUS has risen above 4.0V.
- * For falling edge registers, this indicates VBUS has fallen below 4.0V.
- */
-#define SN5S330_VBUS_GOOD_MASK BIT(0)
-
-#endif /* defined(__CROS_EC_SN5S330_H) */
diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c
deleted file mode 100644
index 0e49abdf6a..0000000000
--- a/driver/ppc/syv682x.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Silergy SYV682x USB-C Power Path Controller */
-#include "atomic.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "syv682x.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define SYV682X_FLAGS_SOURCE_ENABLED	BIT(0)
-#define SYV682X_FLAGS_SINK_ENABLED	BIT(1)
-/* 0 -> CC1, 1 -> CC2 */
-#define SYV682X_FLAGS_CC_POLARITY	BIT(2)
-#define SYV682X_FLAGS_VBUS_PRESENT	BIT(3)
-#define SYV682X_FLAGS_TSD		BIT(4)
-#define SYV682X_FLAGS_OVP		BIT(5)
-#define SYV682X_FLAGS_5V_OC		BIT(6)
-#define SYV682X_FLAGS_FRS		BIT(7)
-#define SYV682X_FLAGS_VCONN_OCP		BIT(8)
-
-static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
-static uint32_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-/* Running count of sink ocp events */
-static uint32_t sink_ocp_count[CONFIG_USB_PD_PORT_MAX_COUNT];
-static timestamp_t vbus_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
-static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define SYV682X_VBUS_DET_THRESH_MV		4000
-/* Longest time that can be programmed in DSG_TIME field */
-#define SYV682X_MAX_VBUS_DISCHARGE_TIME_MS 400
-/*
- * Delay between checks when polling the interrupt registers. Must be longer
- * than the HW deglitch on OC (10ms)
- */
-#define INTERRUPT_DELAY_MS 15
-/* Deglitch in ms of sourcing overcurrent detection */
-#define SOURCE_OC_DEGLITCH_MS 100
-#define VCONN_OC_DEGLITCH_MS 100
-/* Max. number of OC events allowed before disabling port */
-#define OCP_COUNT_LIMIT 3
-
-#if INTERRUPT_DELAY_MS <= SYV682X_HW_OC_DEGLITCH_MS
-#error "INTERRUPT_DELAY_MS should be greater than SYV682X_HW_OC_DEGLITCH_MS"
-#endif
-
-#if SOURCE_OC_DEGLITCH_MS < INTERRUPT_DELAY_MS
-#error "SOURCE_OC_DEGLITCH_MS should be at least INTERRUPT_DELAY_MS"
-#endif
-
-/* When FRS is enabled, the VCONN line isn't passed through to the TCPC */
-#if defined(CONFIG_USB_PD_FRS_PPC) && defined(CONFIG_USBC_VCONN) && \
-	!defined(CONFIG_USBC_PPC_VCONN)
-#error "if FRS is enabled on the SYV682X, VCONN must be supplied by the PPC "
-"instead of the TCPC"
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static int syv682x_vbus_sink_enable(int port, int enable);
-
-static int syv682x_init(int port);
-
-static void syv682x_interrupt_delayed(int port, int delay);
-
-static int read_reg(uint8_t port, int reg, int *regval)
-{
-	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
-}
-
-#ifdef CONFIG_USBC_PPC_SYV682C
-__overridable int syv682x_board_is_syv682c(int port)
-{
-	return true;
-}
-#endif
-
-/*
- * During channel transition or discharge, the SYV682X silently ignores I2C
- * writes. Poll the BUSY bit until the SYV682A is ready.
- */
-static int syv682x_wait_for_ready(int port, int reg)
-{
-	int regval;
-	int rv;
-	timestamp_t deadline;
-
-#ifdef CONFIG_USBC_PPC_SYV682C
-	/* On SYV682C, busy bit is not applied to CONTROL_4 */
-	if (syv682x_board_is_syv682c(port) && reg == SYV682X_CONTROL_4_REG)
-		return EC_SUCCESS;
-#endif
-
-	deadline.val = get_time().val
-			+ (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC);
-
-	do {
-		rv = read_reg(port, SYV682X_CONTROL_3_REG, &regval);
-		if (rv)
-			return rv;
-
-		if (!(regval & SYV682X_BUSY))
-			break;
-
-		if (timestamp_expired(deadline, NULL)) {
-			ppc_prints("busy timeout", port);
-			return EC_ERROR_TIMEOUT;
-		}
-
-		msleep(1);
-	} while (1);
-
-	return EC_SUCCESS;
-}
-
-static int write_reg(uint8_t port, int reg, int regval)
-{
-	int rv;
-
-	rv = syv682x_wait_for_ready(port, reg);
-	if (rv)
-		return rv;
-
-	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
-}
-
-static int syv682x_is_sourcing_vbus(int port)
-{
-	return !!(flags[port] & SYV682X_FLAGS_SOURCE_ENABLED);
-}
-
-static int syv682x_discharge_vbus(int port, int enable)
-{
-#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-	int regval;
-	int rv;
-
-	rv = read_reg(port, SYV682X_CONTROL_2_REG, &regval);
-	if (rv)
-		return rv;
-
-	if (enable)
-		regval |= SYV682X_CONTROL_2_FDSG;
-	else
-		regval &= ~SYV682X_CONTROL_2_FDSG;
-
-	return write_reg(port, SYV682X_CONTROL_2_REG, regval);
-#else
-	/*
-	 * Smart discharge mode is enabled, nothing to do
-	 */
-	return EC_SUCCESS;
-#endif
-}
-
-static int syv682x_vbus_source_enable(int port, int enable)
-{
-	int regval;
-	int rv;
-	/*
-	 * For source mode need to make sure 5V power path is connected
-	 * and source mode is selected.
-	 */
-	rv = read_reg(port, SYV682X_CONTROL_1_REG, &regval);
-	if (rv)
-		return rv;
-
-	if (enable) {
-		/* Select 5V path and turn on channel */
-		regval &= ~(SYV682X_CONTROL_1_CH_SEL |
-			    SYV682X_CONTROL_1_PWR_ENB);
-		/* Disable HV Sink path */
-		regval |= SYV682X_CONTROL_1_HV_DR;
-	} else if (flags[port] & SYV682X_FLAGS_SOURCE_ENABLED) {
-		/*
-		 * For the disable case, make sure that VBUS was being sourced
-		 * prior to disabling the source path. Because the source/sink
-		 * paths can't be independently disabled, and this function will
-		 * get called as part of USB PD initialization, setting the
-		 * PWR_ENB always can lead to broken dead battery behavior.
-		 *
-		 * No need to change the voltage path or channel direction. But,
-		 * turn both paths off.
-		 *
-		 * De-assert the FRS GPIO, which will be asserted if we got to
-		 * be a source via an FRS.
-		 */
-		regval |= SYV682X_CONTROL_1_PWR_ENB;
-		if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
-			gpio_set_level(ppc_chips[port].frs_en, 0);
-	}
-
-	rv = write_reg(port, SYV682X_CONTROL_1_REG, regval);
-	if (rv)
-		return rv;
-
-	if (enable) {
-		atomic_or(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
-	} else {
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
-	}
-
-#if defined(CONFIG_USB_CHARGER) && defined(CONFIG_USB_PD_VBUS_DETECT_PPC)
-	/*
-	 * Since the VBUS state could be changing here, need to wake the
-	 * USB_CHG_N task so that BC 1.2 detection will be triggered.
-	 */
-	usb_charger_vbus_change(port, enable);
-#endif
-
-	return EC_SUCCESS;
-}
-
-/* Filter interrupts with rising edge trigger */
-static bool syv682x_interrupt_filter(int port, int regval, int regmask,
-				     int flagmask)
-{
-	if (regval & regmask) {
-		if (!(flags[port] & flagmask)) {
-			atomic_or(&flags[port], flagmask);
-			return true;
-		}
-	} else {
-		atomic_clear_bits(&flags[port], flagmask);
-	}
-	return false;
-}
-
-/*
- * Two status registers can trigger the ALERT_L pin, STATUS and CONTROL_4
- * These registers are clear on read if the condition has been cleared.
- * The ALERT_L pin will not de-assert if the alert condition has not been
- * cleared. Since they are clear on read, we should check the alerts whenever we
- * read these registers to avoid race conditions.
- */
-static void syv682x_handle_status_interrupt(int port, int regval)
-{
-	/*
-	 * An FRS will automatically disable sinking immediately, and enable the
-	 * source path if VBUS is <5V. The FRS GPIO must remain asserted until
-	 * VBUS falls below 5V. SYV682X_FLAGS_FRS signals that the SRC state was
-	 * entered via an FRS.
-	 *
-	 * Note the FRS Alert will remain asserted until VBUS has fallen below
-	 * 5V or the frs_en gpio is de-asserted. So use the rising edge trigger.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC)) {
-		if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_FRS,
-					     SYV682X_FLAGS_FRS)) {
-			atomic_or(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
-			atomic_clear_bits(&flags[port],
-					  SYV682X_FLAGS_SINK_ENABLED);
-			if (!IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
-				pd_got_frs_signal(port);
-		}
-	}
-
-	/*
-	 * 5V OC is actually notifying that it is current limiting
-	 * to 3.3A. If this happens for a long time, we will trip TSD
-	 * which will disable the channel. We should disable the sourcing path
-	 * before that happens for safety reasons.
-	 *
-	 * On first check, set the flag and set the timer. This also clears the
-	 * flag if the OC is gone.
-	 */
-	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_OC_5V,
-				     SYV682X_FLAGS_5V_OC)) {
-		vbus_oc_timer[port].val =
-			get_time().val + SOURCE_OC_DEGLITCH_MS * MSEC;
-	} else if ((regval & SYV682X_STATUS_OC_5V) &&
-		   (get_time().val > vbus_oc_timer[port].val)) {
-		vbus_oc_timer[port].val = UINT64_MAX;
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_5V_OC);
-		syv682x_vbus_source_enable(port, 0);
-		pd_handle_overcurrent(port);
-	}
-
-	/*
-	 * No PD handling for VBUS OVP or TSD events.
-	 * For TSD, this means we are in danger of burning the device so turn
-	 *   everything off and leave it off. The power paths will be
-	 *   automatically disabled.
-	 * In the case of OVP, the channels will be
-	 *   disabled but don't unset the sink flag, since a sink OCP can
-	 *   inadvertently cause an OVP, and we'd want to re-enable the sink
-	 *   path in that situation.
-	 */
-	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_TSD,
-				     SYV682X_FLAGS_TSD)) {
-		ppc_prints("TSD!", port);
-		atomic_clear_bits(&flags[port],
-				  SYV682X_FLAGS_SOURCE_ENABLED |
-					  SYV682X_FLAGS_SINK_ENABLED);
-	}
-	if (syv682x_interrupt_filter(port, regval, SYV682X_STATUS_OVP,
-				     SYV682X_FLAGS_OVP)) {
-		ppc_prints("VBUS OVP!", port);
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
-	}
-
-	/*
-	 * HV OC is a hard limit that will disable the sink path (automatically
-	 * removing this alert condition), so try re-enabling if we hit an OCP.
-	 * If we get multiple OCPs, don't re-enable. The OCP counter is reset on
-	 * the sink path being explicitly disabled or on a PPC init.
-	 */
-	if (regval & SYV682X_STATUS_OC_HV) {
-		ppc_prints("Sink OCP!", port);
-		atomic_add(&sink_ocp_count[port], 1);
-		if ((sink_ocp_count[port] < OCP_COUNT_LIMIT) &&
-		    (flags[port] & SYV682X_FLAGS_SINK_ENABLED)) {
-			syv682x_vbus_sink_enable(port, 1);
-		} else {
-			ppc_prints("Disable sink", port);
-			atomic_clear_bits(&flags[port],
-					  SYV682X_FLAGS_SINK_ENABLED);
-		}
-	}
-}
-
-static int syv682x_handle_control_4_interrupt(int port, int regval)
-{
-	/*
-	 * VCONN OC is actually notifying that it is current limiting
-	 * to 600mA. If this happens for a long time, we will trip TSD
-	 * which will disable the channel. We should disable the sourcing path
-	 * before that happens for safety reasons.
-	 *
-	 * On first check, set the flag and set the timer. This also clears the
-	 * flag if the OC is gone.
-	 */
-	if (syv682x_interrupt_filter(port, regval, SYV682X_CONTROL_4_VCONN_OCP,
-				     SYV682X_FLAGS_VCONN_OCP)) {
-		vconn_oc_timer[port].val =
-			get_time().val + VCONN_OC_DEGLITCH_MS * MSEC;
-	} else if ((regval & SYV682X_CONTROL_4_VCONN_OCP) &&
-		   (get_time().val > vconn_oc_timer[port].val)) {
-		vconn_oc_timer[port].val = UINT64_MAX;
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_VCONN_OCP);
-
-		/* Disable VCONN */
-		regval &=
-			~(SYV682X_CONTROL_4_VCONN2 | SYV682X_CONTROL_4_VCONN1);
-		write_reg(port, SYV682X_CONTROL_4_REG, regval);
-
-		ppc_prints("VCONN OC!", port);
-	}
-
-	/*
-	 * On VBAT OVP, CC/VCONN are cut. Re-enable before sending the hard
-	 * reset using a PPC re-init. We could reconfigure CC based on flags,
-	 * but these will be updated anyway due to a hard reset so just re-init
-	 * for simplicity. If this happens return an error since this isn't
-	 * recoverable.
-	 */
-	if (regval & SYV682X_CONTROL_4_VBAT_OVP) {
-		ppc_prints("VBAT or CC OVP!", port);
-		syv682x_init(port);
-		pd_handle_cc_overvoltage(port);
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int syv682x_vbus_sink_enable(int port, int enable)
-{
-	int regval;
-	int rv;
-
-	if (!enable) {
-		atomic_clear(&sink_ocp_count[port]);
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
-		/*
-		 * We're currently a source, so nothing more to do
-		 */
-		if (syv682x_is_sourcing_vbus(port))
-			return EC_SUCCESS;
-	} else if (sink_ocp_count[port] > OCP_COUNT_LIMIT) {
-		/*
-		 * Don't re-enable the channel until an explicit sink disable
-		 * resets the ocp counter.
-		 */
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/*
-	 * For sink mode need to make sure high voltage power path is connected
-	 * and sink mode is selected.
-	 */
-	rv = read_reg(port, SYV682X_CONTROL_1_REG, &regval);
-	if (rv)
-		return rv;
-
-	if (enable) {
-		/* Select high voltage path */
-		regval |= SYV682X_CONTROL_1_CH_SEL;
-		/* Select Sink mode and turn on the channel */
-		regval &= ~(SYV682X_CONTROL_1_HV_DR |
-			    SYV682X_CONTROL_1_PWR_ENB);
-		/* Set sink current limit to the configured value */
-		regval |= CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT;
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
-		atomic_or(&flags[port], SYV682X_FLAGS_SINK_ENABLED);
-	} else {
-		/*
-		 * No need to change the voltage path or channel direction. But,
-		 * turn both paths off because we are currently a sink.
-		 */
-		regval |= SYV682X_CONTROL_1_PWR_ENB;
-	}
-
-	return write_reg(port, SYV682X_CONTROL_1_REG, regval);
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-static int syv682x_is_vbus_present(int port)
-{
-	int val;
-	int vbus = 0;
-
-	if (read_reg(port, SYV682X_STATUS_REG, &val))
-		return vbus;
-	/*
-	 * The status register interrupt bits are clear on read, check
-	 * register value to see if there are interrupts to avoid race
-	 * conditions with the interrupt handler
-	 */
-	syv682x_handle_status_interrupt(port, val);
-
-	/*
-	 * VBUS is considered present if VSafe5V is detected or neither VSafe5V
-	 * or VSafe0V is detected, which implies VBUS > 5V.
-	 */
-	if ((val & SYV682X_STATUS_VSAFE_5V) ||
-	    !(val & (SYV682X_STATUS_VSAFE_5V | SYV682X_STATUS_VSAFE_0V)))
-		vbus = 1;
-#ifdef CONFIG_USB_CHARGER
-	if (!!(flags[port] & SYV682X_FLAGS_VBUS_PRESENT) != vbus)
-		usb_charger_vbus_change(port, vbus);
-
-	if (vbus)
-		atomic_or(&flags[port], SYV682X_FLAGS_VBUS_PRESENT);
-	else
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_VBUS_PRESENT);
-#endif
-
-	return vbus;
-}
-#endif
-
-static int syv682x_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
-{
-	int rv;
-	int limit;
-	int regval;
-
-	rv = read_reg(port, SYV682X_CONTROL_1_REG, &regval);
-	if (rv)
-		return rv;
-
-	/* We need buffer room for all current values. */
-	switch (rp) {
-	case TYPEC_RP_3A0:
-		limit = SYV682X_5V_ILIM_3_30;
-		break;
-
-	case TYPEC_RP_1A5:
-		limit = SYV682X_5V_ILIM_1_75;
-		break;
-
-	case TYPEC_RP_USB:
-	default:
-		/* 1.25 A is lowest current limit setting for SVY682 */
-		limit = SYV682X_5V_ILIM_1_25;
-		break;
-	};
-
-	regval &= ~SYV682X_5V_ILIM_MASK;
-	regval |= (limit << SYV682X_5V_ILIM_BIT_SHIFT);
-	return write_reg(port, SYV682X_CONTROL_1_REG, regval);
-}
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-static int syv682x_set_polarity(int port, int polarity)
-{
-	/*
-	 * The SYV682x does not explicitly set CC polarity. However, if VCONN is
-	 * being used then the polarity is required to connect 5V to the correct
-	 * CC line. So this function saves the CC polarity as a bit in the flags
-	 * variable so VCONN is connected the correct CC line. The flag bit
-	 * being set means polarity = CC2, the flag bit clear means
-	 * polarity = CC1.
-	 */
-	if (polarity)
-		atomic_or(&flags[port], SYV682X_FLAGS_CC_POLARITY);
-	else
-		atomic_clear_bits(&flags[port], SYV682X_FLAGS_CC_POLARITY);
-
-	return EC_SUCCESS;
-}
-#endif
-
-#ifdef CONFIG_USBC_PPC_VCONN
-static int syv682x_set_vconn(int port, int enable)
-{
-	int regval;
-	int rv;
-
-	rv = read_reg(port, SYV682X_CONTROL_4_REG, &regval);
-	if (rv)
-		return rv;
-	/*
-	 * The control4 register interrupt bits are clear on read, check
-	 * register value to see if there are interrupts to avoid race
-	 * conditions with the interrupt handler
-	 */
-	rv = syv682x_handle_control_4_interrupt(port, regval);
-	if (rv)
-		return rv;
-
-	regval &= ~(SYV682X_CONTROL_4_VCONN2 | SYV682X_CONTROL_4_VCONN1);
-	if (enable) {
-		regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ?
-				  SYV682X_CONTROL_4_VCONN1 :
-				  SYV682X_CONTROL_4_VCONN2;
-	}
-
-	return write_reg(port, SYV682X_CONTROL_4_REG, regval);
-}
-#endif
-
-#ifdef CONFIG_CMD_PPC_DUMP
-static int syv682x_dump(int port)
-{
-	int reg_addr;
-	int data;
-	int rv;
-	const int i2c_port = ppc_chips[port].i2c_port;
-	const int i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
-
-	for (reg_addr = SYV682X_STATUS_REG; reg_addr <= SYV682X_CONTROL_4_REG;
-	     reg_addr++) {
-		rv = i2c_read8(i2c_port, i2c_addr_flags, reg_addr, &data);
-		if (rv)
-			ccprintf("ppc_syv682[p%d]: Failed to read reg 0x%02x\n",
-				 port, reg_addr);
-		else
-			ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n",
-				 port, reg_addr, data);
-	}
-
-	cflush();
-
-	return EC_SUCCESS;
-}
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-static void syv682x_handle_interrupt(int port)
-{
-	int control4;
-	int status;
-
-	/* Both interrupt registers are clear on read */
-	read_reg(port, SYV682X_CONTROL_4_REG, &control4);
-	syv682x_handle_control_4_interrupt(port, control4);
-
-	read_reg(port, SYV682X_STATUS_REG, &status);
-	syv682x_handle_status_interrupt(port, status);
-
-	/*
-	 * Since ALERT_L is level-triggered, check the alert status and repeat
-	 * until all interrupts are cleared. The SYV682B and later have a 10ms
-	 * deglitch on OC, so make sure not to check the status register again
-	 * for at least 10ms to give it time to re-trigger. This will not spam
-	 * indefinitely on OCP, but may on OVP, RVS, or TSD.
-	 */
-
-	if (status & SYV682X_STATUS_INT_MASK ||
-	    control4 & SYV682X_CONTROL_4_INT_MASK) {
-		syv682x_interrupt_delayed(port, INTERRUPT_DELAY_MS);
-	}
-}
-
-static void syv682x_irq_deferred(void)
-{
-	int i;
-	uint32_t pending = atomic_clear(&irq_pending);
-
-	for (i = 0; i < board_get_usb_pd_port_count(); i++)
-		if (BIT(i) & pending)
-			syv682x_handle_interrupt(i);
-}
-DECLARE_DEFERRED(syv682x_irq_deferred);
-
-static void syv682x_interrupt_delayed(int port, int delay)
-{
-	atomic_or(&irq_pending, BIT(port));
-	hook_call_deferred(&syv682x_irq_deferred_data, delay * MSEC);
-}
-
-void syv682x_interrupt(int port)
-{
-	/* FRS timings require <15ms response to an FRS event */
-	syv682x_interrupt_delayed(port, 0);
-}
-
-/*
- * The frs_en signal can be driven from the TCPC as well (preferred).
- * In that case, no PPC configuration needs to be done to enable FRS
- */
-#ifdef CONFIG_USB_PD_FRS_PPC
-static int syv682x_set_frs_enable(int port, int enable)
-{
-	int regval;
-
-	read_reg(port, SYV682X_CONTROL_4_REG, &regval);
-	syv682x_handle_control_4_interrupt(port, regval);
-
-	if (enable) {
-		/*
-		 * The CC line is the FRS trigger, and VCONN should
-		 * be ignored. The SYV682 uses the CCx_BPS fields to
-		 * determine if CC1 or CC2 is CC and should be used for
-		 * FRS. This CCx is also connected through to the TCPC.
-		 * The other CCx signal (VCONN) is isolated from the
-		 * TCPC with this write (VCONN must be provided by PPC).
-		 *
-		 * It is not a valid state to have both or neither
-		 * CC_BPS bits set and the CC_FRS enabled, exactly 1
-		 * should be set.
-		 */
-		regval &= ~(SYV682X_CONTROL_4_CC1_BPS |
-				SYV682X_CONTROL_4_CC2_BPS);
-		regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ?
-					SYV682X_CONTROL_4_CC2_BPS :
-					SYV682X_CONTROL_4_CC1_BPS;
-		/* set GPIO after configuring */
-		write_reg(port, SYV682X_CONTROL_4_REG, regval);
-		gpio_set_level(ppc_chips[port].frs_en, 1);
-	} else {
-		/*
-		 * Reconnect CC lines to TCPC. Since the FRS GPIO needs to be
-		 * asserted until VBUS falls below 5V during an FRS, if
-		 * SYV682X_FLAGS_FRS is set then don't deassert it, instead
-		 * disable when sourcing is disabled.
-		 */
-		regval |= SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS;
-		write_reg(port, SYV682X_CONTROL_4_REG, regval);
-		if (!(flags[port] & SYV682X_FLAGS_FRS))
-			gpio_set_level(ppc_chips[port].frs_en, 0);
-	}
-	return EC_SUCCESS;
-}
-#endif /*CONFIG_USB_PD_FRS_PPC*/
-
-#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-static int syv682x_dev_is_connected(int port, enum ppc_device_role dev)
-{
-	/*
-	 * (b:160548079) We disable the smart discharge(SDSG), so we should
-	 * turn off the discharge FET if a source is connected.
-	 */
-	if (dev == PPC_DEV_SRC)
-		return syv682x_discharge_vbus(port, 0);
-	else if (dev == PPC_DEV_DISCONNECTED)
-		return syv682x_discharge_vbus(port, 1);
-
-	return EC_SUCCESS;
-}
-#endif
-
-static bool syv682x_is_sink(uint8_t control_1)
-{
-	/*
-	 * The SYV682 integrates power paths: 5V and HV (high voltage).
-	 * The SYV682 can source either 5V or HV, but only sinks on the HV path.
-	 *
-	 * PD analyzer without a device connected confirms the SYV682 acts as
-	 * a source under these conditions:
-	 *	HV_DR && !CH_SEL:	source 5V
-	 *	HV_DR && CH_SEL:	source 15V
-	 *	!HV_DR && !CH_SEL:	source 5V
-	 *
-	 * The SYV682 is only a sink when !HV_DR && CH_SEL
-	 */
-	if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB)
-		&& !(control_1 & SYV682X_CONTROL_1_HV_DR)
-		&& (control_1 & SYV682X_CONTROL_1_CH_SEL))
-		return true;
-
-	return false;
-}
-
-static int syv682x_init(int port)
-{
-	int rv;
-	int regval;
-	int status, control_1;
-	enum tcpc_rp_value initial_current_limit;
-
-	rv = read_reg(port, SYV682X_STATUS_REG, &status);
-	if (rv)
-		return rv;
-
-	rv = read_reg(port, SYV682X_CONTROL_1_REG, &control_1);
-	if (rv)
-		return rv;
-	atomic_clear(&sink_ocp_count[port]);
-
-	/*
-	 * Disable FRS prior to configuring the power paths
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
-		gpio_set_level(ppc_chips[port].frs_en, 0);
-
-	if (!syv682x_is_sink(control_1)
-		|| (status & SYV682X_STATUS_VSAFE_0V)) {
-		/*
-		 * Disable both power paths,
-		 * set HV_ILIM to 3.3A,
-		 * set 5V_ILIM to 3.3A,
-		 * set HV direction to sink,
-		 * select HV channel.
-		 */
-		regval = SYV682X_CONTROL_1_PWR_ENB |
-			(CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) |
-			/* !SYV682X_CONTROL_1_HV_DR */
-			SYV682X_CONTROL_1_CH_SEL;
-		rv = write_reg(port, SYV682X_CONTROL_1_REG, regval);
-		if (rv)
-			return rv;
-	} else {
-		/* Dead battery mode, or an existing PD contract is in place */
-		rv = syv682x_vbus_sink_enable(port, 1);
-		if (rv)
-			return rv;
-	}
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	initial_current_limit = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
-#else
-	initial_current_limit = CONFIG_USB_PD_PULLUP;
-#endif
-	rv = syv682x_set_vbus_source_current_limit(port, initial_current_limit);
-	if (rv)
-		return rv;
-
-	/*
-	 * Set Control Reg 2 to defaults except 50ms smart discharge time.
-	 * Note: On SYV682A/B, enable smart discharge would block i2c
-	 * transactions for 50ms (discharge time) and this
-	 * prevents us from disabling Vconn when stop sourcing Vbus and has
-	 * tVconnOff (35ms) timeout.
-	 * On SYV682C, we are allowed to access CONTROL4 while the i2c busy.
-	 */
-	regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT)
-		| (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT)
-		| (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT);
-
-	if (IS_ENABLED(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE))
-		regval |= SYV682X_CONTROL_2_SDSG;
-
-	rv = write_reg(port, SYV682X_CONTROL_2_REG, regval);
-	if (rv)
-		return rv;
-
-	/*
-	 * Always set the over voltage setting to the maximum to support
-	 * sinking from a 20V PD charger. The common PPC code doesn't provide
-	 * any hooks for indicating what the currently negotiated voltage is.
-	 *
-	 * Mask Alerts due to Reverse Voltage.
-	 */
-	regval = (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) | SYV682X_RVS_MASK;
-	rv = write_reg(port, SYV682X_CONTROL_3_REG, regval);
-	if (rv)
-		return rv;
-
-	/*
-	 * Remove Rd and connect CC1/CC2 lines to TCPC
-	 * Disable Vconn
-	 * Enable CC detection of Fast Role Swap (FRS)
-	 */
-	regval = SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS;
-	rv = write_reg(port, SYV682X_CONTROL_4_REG, regval);
-	if (rv)
-		return rv;
-
-	return EC_SUCCESS;
-}
-
-const struct ppc_drv syv682x_drv = {
-	.init = &syv682x_init,
-	.is_sourcing_vbus = &syv682x_is_sourcing_vbus,
-	.vbus_sink_enable = &syv682x_vbus_sink_enable,
-	.vbus_source_enable = &syv682x_vbus_source_enable,
-#ifdef CONFIG_CMD_PPC_DUMP
-	.reg_dump = &syv682x_dump,
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-#ifdef CONFIG_USB_PD_FRS_PPC
-	.set_frs_enable = &syv682x_set_frs_enable,
-#endif
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-	.is_vbus_present = &syv682x_is_vbus_present,
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-	.set_vbus_source_current_limit = &syv682x_set_vbus_source_current_limit,
-	.discharge_vbus = &syv682x_discharge_vbus,
-#ifndef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-	.dev_is_connected = &syv682x_dev_is_connected,
-#endif /* defined(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE) */
-#ifdef CONFIG_USBC_PPC_POLARITY
-	.set_polarity = &syv682x_set_polarity,
-#endif
-#ifdef CONFIG_USBC_PPC_VCONN
-	.set_vconn = &syv682x_set_vconn,
-#endif
-};
diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h
deleted file mode 100644
index d9416f47f1..0000000000
--- a/driver/ppc/syv682x.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Silergy SYV682x Type-C Power Path Controller */
-
-#ifndef __CROS_EC_SYV682X_H
-#define __CROS_EC_SYV682X_H
-
-#include "common.h"
-#include "driver/ppc/syv682x_public.h"
-
-/* Source OC deglitch implemented in HW for SYV682B */
-#define SYV682X_HW_OC_DEGLITCH_MS	10
-
-/* SYV682x register addresses */
-#define SYV682X_STATUS_REG		0x00
-#define SYV682X_CONTROL_1_REG		0x01
-#define SYV682X_CONTROL_2_REG		0x02
-#define SYV682X_CONTROL_3_REG		0x03
-#define SYV682X_CONTROL_4_REG		0x04
-
-/* Status Register */
-#define SYV682X_STATUS_OC_HV		BIT(7)
-#define SYV682X_STATUS_RVS		BIT(6)
-#define SYV682X_STATUS_OC_5V		BIT(5)
-#define SYV682X_STATUS_OVP		BIT(4)
-#define SYV682X_STATUS_FRS		BIT(3)
-#define SYV682X_STATUS_TSD		BIT(2)
-#define SYV682X_STATUS_VSAFE_5V		BIT(1)
-#define SYV682X_STATUS_VSAFE_0V		BIT(0)
-#define SYV682X_STATUS_INT_MASK		0xfc
-
-/* Control Register 1 */
-#define SYV682X_CONTROL_1_CH_SEL	BIT(1)
-#define SYV682X_CONTROL_1_HV_DR		BIT(2)
-#define SYV682X_CONTROL_1_PWR_ENB	BIT(7)
-
-#define SYV682X_5V_ILIM_MASK		0x18
-#define SYV682X_5V_ILIM_BIT_SHIFT	3
-#define SYV682X_5V_ILIM_1_25		0
-#define SYV682X_5V_ILIM_1_75		1
-#define SYV682X_5V_ILIM_2_25		2
-#define SYV682X_5V_ILIM_3_30		3
-
-#define SYV682X_HV_ILIM_MASK		0x60
-#define SYV682X_HV_ILIM_BIT_SHIFT	5
-#define SYV682X_HV_ILIM_1_25		0
-#define SYV682X_HV_ILIM_1_75		1
-#define SYV682X_HV_ILIM_3_30		2
-#define SYV682X_HV_ILIM_5_50		3
-
-/* Control Register 2 */
-#define SYV682X_OC_DELAY_MASK		GENMASK(7, 6)
-#define SYV682X_OC_DELAY_SHIFT		6
-#define SYV682X_OC_DELAY_1MS		0
-#define SYV682X_OC_DELAY_10MS		1
-#define SYV682X_OC_DELAY_50MS		2
-#define SYV682X_OC_DELAY_100MS		3
-#define SYV682X_DSG_TIME_MASK		GENMASK(5, 4)
-#define SYV682X_DSG_TIME_SHIFT		4
-#define SYV682X_DSG_TIME_50MS		0
-#define SYV682X_DSG_TIME_100MS		1
-#define SYV682X_DSG_TIME_200MS		2
-#define SYV682X_DSG_TIME_400MS		3
-#define SYV682X_DSG_RON_MASK		GENMASK(3, 2)
-#define SYV682X_DSG_RON_SHIFT		2
-#define SYV682X_DSG_RON_200_OHM		0
-#define SYV682X_DSG_RON_400_OHM		1
-#define SYV682X_DSG_RON_800_OHM		2
-#define SYV682X_DSG_RON_1600_OHM	3
-#define SYV682X_CONTROL_2_SDSG		BIT(1)
-#define SYV682X_CONTROL_2_FDSG		BIT(0)
-
-/* Control Register 3 */
-#define SYV682X_BUSY			BIT(7)
-#define SYV682X_RVS_MASK		BIT(3)
-#define SYV682X_RST_REG			BIT(0)
-#define SYV682X_OVP_MASK		0x70
-#define SYV682X_OVP_BIT_SHIFT		4
-#define SYV682X_OVP_06_0		0
-#define SYV682X_OVP_08_0		1
-#define SYV682X_OVP_11_1		2
-#define SYV682X_OVP_12_1		3
-#define SYV682X_OVP_14_2		4
-#define SYV682X_OVP_17_9		5
-#define SYV682X_OVP_21_6		6
-#define SYV682X_OVP_23_7		7
-
-/* Control Register 4 */
-#define SYV682X_CONTROL_4_CC1_BPS	BIT(7)
-#define SYV682X_CONTROL_4_CC2_BPS	BIT(6)
-#define SYV682X_CONTROL_4_VCONN1	BIT(5)
-#define SYV682X_CONTROL_4_VCONN2	BIT(4)
-#define SYV682X_CONTROL_4_VBAT_OVP	BIT(3)
-#define SYV682X_CONTROL_4_VCONN_OCP	BIT(2)
-#define SYV682X_CONTROL_4_CC_FRS	BIT(1)
-#define SYV682X_CONTROL_4_INT_MASK	0x0c
-
-/*
- * syv682x_board_is_syv682c
- *
- * b:160548079 This is a function to workaround that some board revisions
- * might have different SYV682 sub-version.
- *
- * @param port the query port
- * @return 1 if the PPC is SYV682C else 0
- */
-__override_proto int syv682x_board_is_syv682c(int port);
-
-#endif /* defined(__CROS_EC_SYV682X_H) */
diff --git a/driver/regulator_ir357x.c b/driver/regulator_ir357x.c
deleted file mode 100644
index 4721146367..0000000000
--- a/driver/regulator_ir357x.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * IR357x driver.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* I2C address */
-#define IR357x_I2C_ADDR_FLAGS 0x08
-
-struct ir_setting {
-	uint8_t reg;
-	uint8_t value;
-};
-
-static struct ir_setting ir3570_settings[] = {
-	{0x10, 0x22}, {0x11, 0x22}, {0x12, 0x88}, {0x13, 0x10},
-	{0x14, 0x0d}, {0x15, 0x21}, {0x16, 0x21}, {0x17, 0x00},
-	{0x18, 0x00}, {0x19, 0x00}, {0x1a, 0x00}, {0x1b, 0x00},
-	{0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00}, {0x1f, 0x00},
-	{0x20, 0x00}, {0x21, 0x00}, {0x22, 0x60}, {0x23, 0x60},
-	{0x24, 0x74}, {0x25, 0x4e}, {0x26, 0xff}, {0x27, 0x80},
-	{0x28, 0x00}, {0x29, 0x20}, {0x2a, 0x15}, {0x2b, 0x26},
-	{0x2c, 0xb6}, {0x2d, 0x21}, {0x2e, 0x11}, {0x2f, 0x20},
-	{0x30, 0xab}, {0x31, 0x14}, {0x32, 0x90}, {0x33, 0x4d},
-	{0x34, 0x75}, {0x35, 0x64}, {0x36, 0x64}, {0x37, 0x09},
-	{0x38, 0xc4}, {0x39, 0x20}, {0x3a, 0x80}, {0x3b, 0x00},
-	{0x3c, 0x00}, {0x3d, 0xaa}, {0x3e, 0x00}, {0x3f, 0x05},
-	{0x40, 0x50}, {0x41, 0x40}, {0x42, 0x00}, {0x43, 0x00},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x00},
-	{0x48, 0x1c}, {0x49, 0x0c}, {0x4a, 0x0f}, {0x4b, 0x40},
-	{0x4c, 0x80}, {0x4d, 0x40}, {0x4e, 0x80},
-	{0x51, 0x00}, {0x52, 0x45}, {0x53, 0x59},
-	{0x54, 0x23}, {0x55, 0xae}, {0x56, 0x68}, {0x57, 0x24},
-	{0x58, 0x62}, {0x59, 0x42}, {0x5a, 0x34}, {0x5b, 0x00},
-	{0x5c, 0x30}, {0x5d, 0x05}, {0x5e, 0x02}, {0x5f, 0x35},
-	{0x60, 0x30}, {0x61, 0x00}, {0x62, 0xd8}, {0x63, 0x00},
-	{0x64, 0x52}, {0x65, 0x28}, {0x66, 0x14}, {0x67, 0x87},
-	{0x68, 0x80}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0xff}, {0x6e, 0x06}, {0x6f, 0xff},
-	{0x70, 0xff}, {0x71, 0x20}, {0x72, 0x00}, {0x73, 0x01},
-	{0x74, 0x00}, {0x75, 0x00}, {0x76, 0x00}, {0x77, 0x00},
-	{0x78, 0x00}, {0x79, 0x00}, {0x7a, 0x00}, {0x7b, 0x00},
-	{0x7c, 0x15}, {0x7d, 0x15}, {0x7e, 0x00}, {0x7f, 0x00},
-	{0x80, 0x00}, {0x81, 0x00}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x88}, {0x89, 0x88}, {0x8a, 0x01}, {0x8b, 0x42},
-	{0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x1f},
-	{0, 0}
-};
-
-static struct ir_setting ir3571_settings[] = {
-	{0x18, 0x22}, {0x19, 0x22}, {0x1a, 0x08}, {0x1b, 0x10},
-	{0x1c, 0x06}, {0x1d, 0x21}, {0x1e, 0x21}, {0x1f, 0x83},
-	{0x20, 0x83}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
-	{0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x34},
-	{0x28, 0x34}, {0x29, 0x74}, {0x2a, 0x4e}, {0x2b, 0xff},
-	{0x2c, 0x00}, {0x2d, 0x1d}, {0x2e, 0x14}, {0x2f, 0x1f},
-	{0x30, 0x88}, {0x31, 0x9a}, {0x32, 0x1e}, {0x33, 0x19},
-	{0x34, 0xe9}, {0x35, 0x40}, {0x36, 0x90}, {0x37, 0x6d},
-	{0x38, 0x75}, {0x39, 0xa0}, {0x3a, 0x84}, {0x3b, 0x08},
-	{0x3c, 0xc5}, {0x3d, 0xa0}, {0x3e, 0x80}, {0x3f, 0xaa},
-	{0x40, 0x50}, {0x41, 0x4b}, {0x42, 0x02}, {0x43, 0x04},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x78},
-	{0x48, 0x56}, {0x49, 0x18}, {0x4a, 0x88}, {0x4b, 0x00},
-	{0x4c, 0x80}, {0x4d, 0x60}, {0x4e, 0x60}, {0x4f, 0xff},
-	{0x50, 0xff}, {0x51, 0x00}, {0x52, 0x9b}, {0x53, 0xaa},
-	{0x54, 0xd8}, {0x55, 0x56}, {0x56, 0x31}, {0x57, 0x1a},
-	{0x58, 0x12}, {0x59, 0x63}, {0x5a, 0x00}, {0x5b, 0x09},
-	{0x5c, 0x02}, {0x5d, 0x00}, {0x5e, 0xea}, {0x5f, 0x00},
-	{0x60, 0xb0}, {0x61, 0x1e}, {0x62, 0x00}, {0x63, 0x56},
-	{0x64, 0x00}, {0x65, 0x00}, {0x66, 0x00}, {0x67, 0x00},
-	{0x68, 0x28}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0x00}, {0x6e, 0x00}, {0x6f, 0x00},
-	{0x70, 0x80}, {0x71, 0x00}, {0x72, 0x00}, {0x73, 0x00},
-	{0x74, 0x00}, {0x75, 0xbf}, {0x76, 0x06}, {0x77, 0xff},
-	{0x78, 0xff}, {0x79, 0x04}, {0x7a, 0x00}, {0x7b, 0x1d},
-	{0x7c, 0xa0}, {0x7d, 0x10}, {0x7e, 0x00}, {0x7f, 0x8a},
-	{0x80, 0x1b}, {0x81, 0x11}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x00}, {0x89, 0x00}, {0x8a, 0x00}, {0x8b, 0x00},
-	{0x8c, 0x00}, {0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x00},
-	{0, 0}
-};
-
-static uint8_t ir357x_read(uint8_t reg)
-{
-	int res;
-	int val;
-
-	res = i2c_read8(I2C_PORT_REGULATOR, IR357x_I2C_ADDR, reg, &val);
-	if (res)
-		return 0xee;
-
-	return val;
-}
-
-static void ir357x_write(uint8_t reg, uint8_t val)
-{
-	int res;
-
-	res = i2c_write8(I2C_PORT_REGULATOR, IR357x_I2C_ADDR, reg, val);
-	if (res)
-		CPRINTF("IR I2C write failed\n");
-}
-
-static int ir357x_get_version(void)
-{
-	/* IR3571 on Link EVT */
-	if ((ir357x_read(0xfc) == 'I') && (ir357x_read(0xfd) == 'R') &&
-	    ((ir357x_read(0x0a) & 0xe) == 0))
-		return 3571;
-
-	/* IR3570A on Link Proto 0/1 and Link DVT */
-	if ((ir357x_read(0x92) == 'C') && (ir357x_read(0xcd) == 0x24))
-		return 3570;
-
-	/* Unknown and unsupported chip */
-	return -1;
-}
-
-struct ir_setting *ir357x_get_settings(void)
-{
-	int version = ir357x_get_version();
-
-	if (version == 3570)
-		return ir3570_settings;
-	else if (version == 3571)
-		return ir3571_settings;
-	else
-		return NULL;
-}
-
-static void ir357x_prog(void)
-{
-	struct ir_setting *settings = ir357x_get_settings();
-
-	if (settings) {
-		for (; settings->reg; settings++)
-			ir357x_write(settings->reg, settings->value);
-	} else {
-		CPRINTF("IR%d chip unsupported. Skip writing settings!\n",
-			ir357x_get_version());
-		return;
-	}
-
-	CPRINTF("IR%d registers UPDATED\n", ir357x_get_version());
-}
-
-static void ir357x_dump(void)
-{
-	int i;
-
-	for (i = 0; i < 256; i++) {
-		if (!(i & 0xf)) {
-			ccprintf("\n%02x: ", i);
-			cflush();
-		}
-		ccprintf("%02x ", ir357x_read(i));
-	}
-	ccprintf("\n");
-}
-
-static int ir357x_check(void)
-{
-	uint8_t val;
-	int diff = 0;
-	struct ir_setting *settings = ir357x_get_settings();
-
-	if (!settings) {
-		ccprintf("no setting for chip IR%d !\n", ir357x_get_version());
-		return 1;
-	}
-
-	for (; settings->reg; settings++) {
-		val = ir357x_read(settings->reg);
-		if (val != settings->value) {
-			ccprintf("DIFF reg 0x%02x %02x->%02x\n",
-				 settings->reg, settings->value, val);
-			cflush();
-			diff++;
-		}
-	}
-	return !!diff;
-}
-
-#ifdef CONFIG_CMD_REGULATOR
-static int command_ir357x(int argc, char **argv)
-{
-	int reg, val;
-	char *rem;
-
-	if (1 == argc) { /* dump all registers */
-		ir357x_dump();
-		return EC_SUCCESS;
-	} else if (2 == argc) {
-		if (!strcasecmp(argv[1], "check")) {
-			ir357x_check();
-		} else { /* read one register */
-			reg = strtoi(argv[1], &rem, 16);
-			if (*rem) {
-				ccprintf("Invalid register: %s\n", argv[1]);
-				return EC_ERROR_INVAL;
-			}
-			ccprintf("reg 0x%02x = 0x%02x\n", reg,
-				 ir357x_read(reg));
-		}
-		return EC_SUCCESS;
-	} else if (3 == argc) { /* write one register */
-		reg = strtoi(argv[1], &rem, 16);
-		if (*rem) {
-			ccprintf("Invalid register: %s\n", argv[1]);
-			return EC_ERROR_INVAL;
-		}
-		val = strtoi(argv[2], &rem, 16);
-		if (*rem) {
-			ccprintf("Invalid value: %s\n", argv[2]);
-			return EC_ERROR_INVAL;
-		}
-		ir357x_write(reg, val);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x,
-			"[check|write]",
-			"IR357x core regulator control");
-#endif
-
-static void ir357x_hot_settings(void)
-{
-	/* dynamically apply settings to workaround issue */
-	ir357x_prog();
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, ir357x_hot_settings, HOOK_PRIO_DEFAULT);
diff --git a/driver/retimer/anx7491.h b/driver/retimer/anx7491.h
deleted file mode 100644
index 045cf9f411..0000000000
--- a/driver/retimer/anx7491.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ANX7491:10G USB 3.2 Re-timer (1-Port)
- */
-
-#ifndef __CROS_EC_USB_RETIMER_ANX7491_H
-#define __CROS_EC_USB_RETIMER_ANX7491_H
-
-/* I2C interface addresses */
-#define ANX7491_I2C_ADDR0_FLAGS		0x10
-#define ANX7491_I2C_ADDR1_FLAGS		0x14
-#define ANX7491_I2C_ADDR2_FLAGS		0x16
-#define ANX7491_I2C_ADDR3_FLAGS		0x11
-
-#endif /* __CROS_EC_USB_RETIMER_ANX7491_H */
diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c
deleted file mode 100644
index bf3da60b32..0000000000
--- a/driver/retimer/bb_retimer.c
+++ /dev/null
@@ -1,623 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Driver for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
- */
-
-#include "driver/retimer/bb_retimer.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define BB_RETIMER_REG_SIZE	4
-#define BB_RETIMER_READ_SIZE	(BB_RETIMER_REG_SIZE + 1)
-#define BB_RETIMER_WRITE_SIZE	(BB_RETIMER_REG_SIZE + 2)
-#define BB_RETIMER_MUX_DATA_PRESENT (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_SAFE_MODE \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
-
-#define BB_RETIMER_MUX_USB_ALT_MODE (USB_PD_MUX_USB_ENABLED\
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
-
-#define BB_RETIMER_MUX_USB_DP_MODE (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define BB_RETIMER_I2C_RETRY	5
-
-/**
- * Utility functions
- */
-static int bb_retimer_read(const struct usb_mux *me,
-			   const uint8_t offset, uint32_t *data)
-{
-	int rv, retry = 0;
-	uint8_t buf[BB_RETIMER_READ_SIZE];
-
-	/*
-	 * This I2C message will trigger retimer's internal read sequence
-	 * if its a NAK, sleep and resend same I2C
-	 */
-	while (1) {
-		/*
-		 * Read sequence
-		 * Addr flags (w) - Reg offset - repeated start - Addr flags(r)
-		 * byte[0]   : Read size
-		 * byte[1:4] : Data [LSB -> MSB]
-		 * Stop
-		 */
-		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      &offset, 1, buf, BB_RETIMER_READ_SIZE);
-
-		if (rv == EC_SUCCESS)
-			break;
-
-		if (++retry >= BB_RETIMER_I2C_RETRY) {
-			CPRINTS("C%d: Retimer I2C read err=%d",
-				me->usb_port, rv);
-			return rv;
-		}
-		msleep(10);
-	}
-
-	if (buf[0] != BB_RETIMER_REG_SIZE)
-		return EC_ERROR_UNKNOWN;
-
-	*data = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24);
-
-	return EC_SUCCESS;
-}
-
-static int bb_retimer_write(const struct usb_mux *me,
-			    const uint8_t offset, uint32_t data)
-{
-	int rv, retry = 0;
-	uint8_t buf[BB_RETIMER_WRITE_SIZE];
-
-	/*
-	 * Write sequence
-	 * Addr flags(w)
-	 * byte[0]   : Reg offset
-	 * byte[1]   : Write Size
-	 * byte[2:5] : Data [LSB -> MSB]
-	 * stop
-	 */
-	buf[0] = offset;
-	buf[1] = BB_RETIMER_REG_SIZE;
-	buf[2] = data & 0xFF;
-	buf[3] = (data >> 8) & 0xFF;
-	buf[4] = (data >> 16) & 0xFF;
-	buf[5] = (data >> 24) & 0xFF;
-
-	/*
-	 * This I2C message will trigger retimer's internal write sequence
-	 * if its a NAK, sleep and resend same I2C
-	 */
-	while (1) {
-		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf,
-			     BB_RETIMER_WRITE_SIZE, NULL, 0);
-
-		if (rv == EC_SUCCESS)
-			break;
-
-		if (++retry >= BB_RETIMER_I2C_RETRY) {
-			CPRINTS("C%d: Retimer I2C write err=%d",
-				me->usb_port, rv);
-			break;
-		}
-		msleep(10);
-	}
-	return rv;
-}
-
-__overridable int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	const struct bb_usb_control *control = &bb_controls[me->usb_port];
-
-	/* handle retimer's power domain */
-
-	if (enable) {
-		gpio_set_level(control->usb_ls_en_gpio, 1);
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		msleep(1);
-		gpio_set_level(control->retimer_rst_gpio, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		gpio_set_level(control->retimer_rst_gpio, 0);
-		msleep(1);
-		gpio_set_level(control->usb_ls_en_gpio, 0);
-	}
-	return EC_SUCCESS;
-}
-
-static void retimer_set_state_dfp(int port, mux_state_t mux_state,
-				  uint32_t *set_retimer_con)
-{
-	union tbt_mode_resp_cable cable_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
-	union tbt_mode_resp_device dev_resp;
-	enum idh_ptype cable_type = get_usb_pd_cable_type(port);
-
-	/*
-	 * Bit 2: RE_TIMER_DRIVER
-	 * 0 - Re-driver
-	 * 1 - Re-timer
-	 *
-	 * If Alternate mode is USB/DP/USB4, RE_TIMER_DRIVER is
-	 * set according to SOP' VDO2 response Bit 9.
-	 *
-	 */
-	if (is_active_cable_element_retimer(port) &&
-	   (mux_state & BB_RETIMER_MUX_USB_DP_MODE))
-		*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
-
-	/*
-	 * Bit 22: ACTIVE/PASSIVE
-	 * 0 - Passive cable
-	 * 1 - Active cable
-	 *
-	 * If the mode is USB/DP/Thunderbolt_compat/USB4, ACTIVE/PASIVE is
-	 * set according to Discover mode SOP' response.
-	 */
-	if ((mux_state & BB_RETIMER_MUX_USB_ALT_MODE) &&
-	    ((cable_type == IDH_PTYPE_ACABLE) ||
-	      cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE))
-		*set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE;
-
-	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ||
-	    mux_state & USB_PD_MUX_USB4_ENABLED) {
-		dev_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
-
-		/*
-		 * Bit 2: RE_TIMER_DRIVER
-		 * 0 - Re-driver
-		 * 1 - Re-timer
-		 *
-		 * If Alternate mode is Thunderbolt-Compat, RE_TIMER_DRIVER is
-		 * set according to Discover Mode SOP' response,
-		 * Bit 22: Retimer Type.
-		 */
-		if (cable_resp.retimer_type == USB_RETIMER)
-			*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
-
-		/*
-		 * Bit 17: TBT_TYPE
-		 * 0 - Type-C to Type-C Cable
-		 * 1 - Type-C Legacy TBT Adapter
-		 */
-		if (dev_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY)
-			*set_retimer_con |= BB_RETIMER_TBT_TYPE;
-
-		/*
-		 * Bit 18: CABLE_TYPE
-		 * 0 - Electrical cable
-		 * 1 - Optical cable
-		 */
-		if (cable_resp.tbt_cable == TBT_CABLE_OPTICAL)
-			*set_retimer_con |= BB_RETIMER_TBT_CABLE_TYPE;
-
-		/*
-		 * Bit 19: VPO_DOCK_DETECTED_OR_DP_OVERDRIVE
-		 * 0 - No vPro Dock.No DP Overdrive
-		 *     detected
-		 * 1 - vPro Dock or DP Overdrive
-		 *     detected
-		 */
-		if (dev_resp.intel_spec_b0 == VENDOR_SPECIFIC_SUPPORTED ||
-		    dev_resp.vendor_spec_b1 == VENDOR_SPECIFIC_SUPPORTED)
-			*set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
-
-		/*
-		 * Bit 20: TBT_ACTIVE_LINK_TRAINING
-		 * 0 - Active with bi-directional LSRX communication
-		 * 1 - Active with uni-directional LSRX communication
-		 * Set to "0" when passive cable plug
-		 */
-		if ((cable_type == IDH_PTYPE_ACABLE ||
-		     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) &&
-		     cable_resp.lsrx_comm == UNIDIR_LSRX_COMM)
-			*set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING;
-
-		/*
-		 * Bit 27-25: USB4/TBT Cable speed
-		 * 000b - No functionality
-		 * 001b - USB3.1 Gen1 Cable
-		 * 010b - 10Gb/s
-		 * 011b - 10Gb/s and 20Gb/s
-		 * 10..11b - Reserved
-		 */
-		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-				    mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ?
-				    get_tbt_cable_speed(port) :
-				    get_usb4_cable_speed(port));
-
-		/*
-		 * Bits 29-28: TBT_GEN_SUPPORT
-		 * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s)
-		 * 01b - 4th generation TBT (10.00005Gb/s, 10.3125Gb/s,
-		 *                           20.0625Gb/s, 20.000Gb/s)
-		 * 10..11b - Reserved
-		 */
-		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
-				       cable_resp.tbt_rounded);
-	}
-}
-
-static void retimer_set_state_ufp(int port, mux_state_t mux_state,
-				  uint32_t *set_retimer_con)
-{
-	/*
-	 * Bit 7: USB_DATA_ROLE for the Burnside Bridge side of
-	 * connection.
-	 * 0 - DFP
-	 * 1 - UFP
-	 */
-	*set_retimer_con |= BB_RETIMER_USB_DATA_ROLE;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_UFP))
-		return;
-
-	/* TODO:b/168890624: Set USB4 retimer config for UFP */
-	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
-		union tbt_dev_mode_enter_cmd ufp_tbt_enter_mode = {
-			.raw_value = pd_ufp_get_enter_mode(port)};
-		/*
-		 * Bit 2: RE_TIMER_DRIVER
-		 * 0 - Re-driver
-		 * 1 - Re-timer
-		 *
-		 * Set according to TBT3 Enter Mode bit 22.
-		 */
-		if (ufp_tbt_enter_mode.retimer_type == USB_RETIMER)
-			*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
-
-		/*
-		 * Bit 18: CABLE_TYPE
-		 * 0 - Electrical cable
-		 * 1 - Optical cable
-		 *
-		 * Set according to TBT3 Enter Mode bit 21.
-		 */
-		if (ufp_tbt_enter_mode.tbt_cable == TBT_CABLE_OPTICAL)
-			*set_retimer_con |= BB_RETIMER_TBT_CABLE_TYPE;
-
-		/*
-		 * Bit 19: VPO_DOCK_DETECTED_OR_DP_OVERDRIVE
-		 * 0 - No vPro Dock.No DP Overdrive
-		 *     detected
-		 * 1 - vPro Dock or DP Overdrive
-		 *     detected
-		 *
-		 * Set according to TBT3 Enter Mode bit 26 or bit 31
-		 */
-		if (ufp_tbt_enter_mode.intel_spec_b0 ==
-					VENDOR_SPECIFIC_SUPPORTED ||
-		    ufp_tbt_enter_mode.vendor_spec_b1 ==
-					VENDOR_SPECIFIC_SUPPORTED)
-			*set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
-
-		/*
-		 * Bit 20: TBT_ACTIVE_LINK_TRAINING
-		 * 0 - Active with bi-directional LSRX communication
-		 * 1 - Active with uni-directional LSRX communication
-		 *
-		 * Set according to TBT3 Enter Mode bit 23
-		 */
-		if (ufp_tbt_enter_mode.lsrx_comm == UNIDIR_LSRX_COMM)
-			*set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING;
-
-		/*
-		 * Bit 22: ACTIVE/PASSIVE
-		 * 0 - Passive cable
-		 * 1 - Active cable
-		 *
-		 * Set according to TBT3 Enter Mode bit 24
-		 */
-		if (ufp_tbt_enter_mode.cable == TBT_ENTER_ACTIVE_CABLE)
-			*set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE;
-
-		/*
-		 * Bit 27-25: TBT Cable speed
-		 * 000b - No functionality
-		 * 001b - USB3.1 Gen1 Cable
-		 * 010b - 10Gb/s
-		 * 011b - 10Gb/s and 20Gb/s
-		 * 10..11b - Reserved
-		 *
-		 * Set according to TBT3 Enter Mode bit 18:16
-		 */
-		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-					ufp_tbt_enter_mode.tbt_cable_speed);
-		/*
-		 * Bits 29-28: TBT_GEN_SUPPORT
-		 * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s)
-		 * 01b - 4th generation TBT (10.00005Gb/s, 10.3125Gb/s,
-		 *                           20.0625Gb/s, 20.000Gb/s)
-		 * 10..11b - Reserved
-		 *
-		 * Set according to TBT3 Enter Mode bit 20:19
-		 */
-		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
-				       ufp_tbt_enter_mode.tbt_rounded);
-	}
-}
-
-/**
- * Driver interface functions
- */
-static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
-			     bool *ack_required)
-{
-	uint32_t set_retimer_con = 0;
-	uint8_t dp_pin_mode;
-	int port = me->usb_port;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/*
-	 * Bit 0: DATA_CONNECTION_PRESENT
-	 * 0 - No connection present
-	 * 1 - Connection present
-	 */
-	if (mux_state & BB_RETIMER_MUX_DATA_PRESENT)
-		set_retimer_con |= BB_RETIMER_DATA_CONNECTION_PRESENT;
-
-	/*
-	 * Bit 1: CONNECTION_ORIENTATION
-	 * 0 - Normal
-	 * 1 - reversed
-	 */
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		set_retimer_con |= BB_RETIMER_CONNECTION_ORIENTATION;
-
-	/*
-	 * Bit 5: USB_3_CONNECTION
-	 * 0 - No USB3.1 Connection
-	 * 1 - USB3.1 connection
-	 */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		set_retimer_con |= BB_RETIMER_USB_3_CONNECTION;
-
-		/*
-		 * Bit 6: USB3_Speed
-		 * 0 – USB3 is limited to Gen1
-		 * 1 – USB3 Gen1/Gen2 supported
-		 */
-		if (is_cable_speed_gen2_capable(port))
-			set_retimer_con |= BB_RETIMER_USB_3_SPEED;
-	}
-
-	/*
-	 * Bit 8: DP_CONNECTION
-	 * 0 – No DP connection
-	 * 1 – DP connected
-	 */
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		set_retimer_con |= BB_RETIMER_DP_CONNECTION;
-
-		/*
-		 * Bit 11-10: DP_PIN_ASSIGNMENT (ignored if BIT8 = 0)
-		 * 00 – Pin assignments E/E’
-		 * 01 – Pin assignments C/C’/D/D’1,2
-		 * 10, 11 - reserved
-		 */
-		dp_pin_mode = get_dp_pin_mode(port);
-		if (dp_pin_mode == MODE_DP_PIN_C ||
-			dp_pin_mode == MODE_DP_PIN_D)
-			set_retimer_con |= BB_RETIMER_DP_PIN_ASSIGNMENT;
-
-		/*
-		 * Bit 14: IRQ_HPD (ignored if BIT8 = 0)
-		 * 0 - No IRQ_HPD
-		 * 1 - IRQ_HPD received
-		 */
-		if (mux_state & USB_PD_MUX_HPD_IRQ)
-			set_retimer_con |= BB_RETIMER_IRQ_HPD;
-
-		/*
-		 * Bit 15: HPD_LVL (ignored if BIT8 = 0)
-		 * 0 - HPD_State Low
-		 * 1 - HPD_State High
-		 */
-		if (mux_state & USB_PD_MUX_HPD_LVL)
-			set_retimer_con |= BB_RETIMER_HPD_LVL;
-	}
-
-	/*
-	 * Bit 16: TBT_CONNECTION
-	 * 0 - TBT not configured
-	 * 1 - TBT configured
-	 */
-	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED)
-		set_retimer_con |= BB_RETIMER_TBT_CONNECTION;
-
-	/*
-	 * Bit 23: USB4_CONNECTION
-	 * 0 - USB4 not configured
-	 * 1 - USB4 Configured
-	 */
-	if (mux_state & USB_PD_MUX_USB4_ENABLED)
-		set_retimer_con |= BB_RETIMER_USB4_ENABLED;
-
-	if (pd_get_data_role(port) == PD_ROLE_DFP)
-		retimer_set_state_dfp(port, mux_state, &set_retimer_con);
-	else
-		retimer_set_state_ufp(port, mux_state, &set_retimer_con);
-
-	/* Writing the register4 */
-	return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE,
-			set_retimer_con);
-}
-
-void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state)
-{
-	uint32_t retimer_con_reg = 0;
-
-	if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE,
-			    &retimer_con_reg) != EC_SUCCESS)
-		return;
-
-	/*
-	 * Bit 14: IRQ_HPD (ignored if BIT8 = 0)
-	 * 0 - No IRQ_HPD
-	 * 1 - IRQ_HPD received
-	 */
-	if (mux_state & USB_PD_MUX_HPD_IRQ)
-		retimer_con_reg |= BB_RETIMER_IRQ_HPD;
-	else
-		retimer_con_reg &= ~BB_RETIMER_IRQ_HPD;
-
-	/*
-	 * Bit 15: HPD_LVL (ignored if BIT8 = 0)
-	 * 0 - HPD_State Low
-	 * 1 - HPD_State High
-	 */
-	if (mux_state & USB_PD_MUX_HPD_LVL)
-		retimer_con_reg |= BB_RETIMER_HPD_LVL;
-	else
-		retimer_con_reg &= ~BB_RETIMER_HPD_LVL;
-
-	/* Writing the register4 */
-	bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg);
-}
-
-static int retimer_low_power_mode(const struct usb_mux *me)
-{
-	return bb_retimer_power_enable(me, false);
-}
-
-static bool is_retimer_fw_update_capable(void)
-{
-	return true;
-}
-
-static int retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	uint32_t data;
-
-	/* Burnside Bridge is powered by main AP rail */
-	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
-		/* Ensure reset is asserted while chip is not powered */
-		bb_retimer_power_enable(me, false);
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	rv = bb_retimer_power_enable(me, true);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data);
-	if (rv != EC_SUCCESS)
-		return rv;
-	if ((data != BB_RETIMER_VENDOR_ID_1) &&
-			data != BB_RETIMER_VENDOR_ID_2)
-		return EC_ERROR_INVAL;
-
-	rv = bb_retimer_read(me, BB_RETIMER_REG_DEVICE_ID, &data);
-	if (rv != EC_SUCCESS)
-		return rv;
-	if (data != BB_RETIMER_DEVICE_ID)
-		return EC_ERROR_INVAL;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver bb_usb_retimer = {
-	.init = retimer_init,
-	.set = retimer_set_state,
-	.enter_low_power_mode = retimer_low_power_mode,
-	.is_retimer_fw_update_capable = is_retimer_fw_update_capable,
-};
-
-#ifdef CONFIG_CMD_RETIMER
-static int console_command_bb_retimer(int argc, char **argv)
-{
-	char rw, *e;
-	int port, reg, data, val = 0;
-	int rv = EC_SUCCESS;
-	const struct usb_mux *mux;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Get port number */
-	port = strtoi(argv[1], &e, 0);
-	if (*e || !board_is_usb_pd_port_present(port))
-		return EC_ERROR_PARAM1;
-
-	mux = &usb_muxes[port];
-	while (mux) {
-		if (mux->driver == &bb_usb_retimer)
-			break;
-		mux = mux->next_mux;
-	}
-
-	if (!mux)
-		return EC_ERROR_PARAM1;
-
-	/* Validate r/w selection */
-	rw = argv[2][0];
-	if (rw != 'w' && rw != 'r')
-		return EC_ERROR_PARAM2;
-
-	/* Get register address */
-	reg = strtoi(argv[3], &e, 0);
-	if (*e || reg < 0)
-		return EC_ERROR_PARAM3;
-
-	/* Get value to be written */
-	if (rw == 'w') {
-		val = strtoi(argv[4], &e, 0);
-		if (*e || val < 0)
-			return EC_ERROR_PARAM4;
-	}
-
-	for (; mux != NULL; mux = mux->next_mux) {
-		if (mux->driver == &bb_usb_retimer) {
-			if (rw == 'r')
-				rv = bb_retimer_read(mux, reg, &data);
-			else {
-				rv = bb_retimer_write(mux, reg, val);
-				if (rv == EC_SUCCESS) {
-					rv = bb_retimer_read(
-						mux, reg, &data);
-				if (rv == EC_SUCCESS && data != val)
-					rv = EC_ERROR_UNKNOWN;
-				}
-			}
-			if (rv == EC_SUCCESS)
-				CPRINTS("Addr 0x%x register %d = 0x%x",
-					mux->i2c_addr_flags, reg, data);
-		}
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(bb, console_command_bb_retimer,
-			"<port> <r/w> <reg> | <val>",
-			"Read or write to BB retimer register");
-#endif /* CONFIG_CMD_RETIMER */
diff --git a/driver/retimer/kb800x.c b/driver/retimer/kb800x.c
deleted file mode 100644
index 48e47404c2..0000000000
--- a/driver/retimer/kb800x.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Driver for Kandou KB800x USB-C 40 Gb/s multiprotocol switch.
- */
-
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "kb800x.h"
-#include "time.h"
-
-/* Time between load switch enable and the reset being de-asserted */
-#define KB800X_POWER_ON_DELAY_MS 20
-
-static mux_state_t cached_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int kb800x_write(const struct usb_mux *me, uint16_t address,
-			uint8_t data)
-{
-	uint8_t kb800x_config[3] = { 0x00, 0x00, 0x00 };
-
-	kb800x_config[0] = (address >> 8) & 0xff;
-	kb800x_config[1] = address & 0xff;
-	kb800x_config[2] = data;
-	return i2c_xfer(me->i2c_port, me->i2c_addr_flags, kb800x_config,
-			sizeof(kb800x_config), NULL, 0);
-}
-
-static int kb800x_read(const struct usb_mux *me, uint16_t address,
-		       uint8_t *data)
-{
-	uint8_t kb800x_config[2] = { 0x00, 0x00 };
-
-	kb800x_config[0] = (address >> 8) & 0xff;
-	kb800x_config[1] = address & 0xff;
-	return i2c_xfer(me->i2c_port, me->i2c_addr_flags, kb800x_config,
-			sizeof(kb800x_config), data, 1);
-}
-
-#ifdef CONFIG_KB800X_CUSTOM_XBAR
-
-/* These lookup tables are derived from the KB8001 EVB GUI register map */
-
-/* Map elastic buffer (EB) to register field for TX configuration. */
-static const uint8_t tx_eb_to_field_ab[] = {
-	[KB800X_EB1] = 4, [KB800X_EB2] = 0, [KB800X_EB3] = 0,
-	[KB800X_EB4] = 1, [KB800X_EB5] = 2, [KB800X_EB6] = 3
-};
-static const uint8_t tx_eb_to_field_cd[] = {
-	[KB800X_EB1] = 1, [KB800X_EB2] = 2, [KB800X_EB3] = 3,
-	[KB800X_EB4] = 4, [KB800X_EB5] = 0, [KB800X_EB6] = 0
-};
-/* Map phy lane to register field for RX configuration */
-static const uint8_t rx_phy_lane_to_field[] = {
-	[KB800X_A0] = 1, [KB800X_A1] = 2, [KB800X_B0] = 5, [KB800X_B1] = 6,
-	[KB800X_C0] = 1, [KB800X_C1] = 2, [KB800X_D0] = 5, [KB800X_D1] = 6
-};
-/* Map EB to address for RX configuration */
-static const uint16_t rx_eb_to_address[] = {
-	[KB800X_EB1] = KB800X_REG_XBAR_EB1SEL,
-	[KB800X_EB2] = KB800X_REG_XBAR_EB23SEL,
-	[KB800X_EB3] = KB800X_REG_XBAR_EB23SEL,
-	[KB800X_EB4] = KB800X_REG_XBAR_EB4SEL,
-	[KB800X_EB5] = KB800X_REG_XBAR_EB56SEL,
-	[KB800X_EB6] = KB800X_REG_XBAR_EB56SEL
-};
-/* Map SS lane to EB for DP or USB/CIO protocols */
-static const uint8_t dp_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4,
-					    [KB800X_TX1] = KB800X_EB5,
-					    [KB800X_RX0] = KB800X_EB6,
-					    [KB800X_RX1] = KB800X_EB1 };
-static const uint8_t usb_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4,
-					     [KB800X_TX1] = KB800X_EB5,
-					     [KB800X_RX0] = KB800X_EB1,
-					     [KB800X_RX1] = KB800X_EB2 };
-
-/* Assign a phy TX to an elastic buffer */
-static int kb800x_assign_tx_to_eb(const struct usb_mux *me,
-			  enum kb800x_phy_lane phy_lane, enum kb800x_eb eb)
-{
-	uint8_t field_value = 0;
-	uint8_t regval;
-	int rv;
-
-	field_value = KB800X_PHY_IS_AB(phy_lane) ? tx_eb_to_field_ab[eb] :
-						    tx_eb_to_field_cd[eb];
-
-	/* For lane1 of each PHY, shift by 3 bits */
-	field_value <<= 3 * KB800X_LANE_NUMBER_FROM_PHY(phy_lane);
-
-	rv = kb800x_read(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane), &regval);
-	if (rv)
-		return rv;
-	return kb800x_write(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane),
-		     regval | field_value);
-}
-
-
-/* Assign a phy RX to an elastic buffer */
-static int kb800x_assign_rx_to_eb(const struct usb_mux *me,
-			  enum kb800x_phy_lane phy_lane, enum kb800x_eb eb)
-{
-	uint16_t address = 0;
-	uint8_t field_value = 0;
-	uint8_t regval = 0;
-	int rv;
-
-
-	field_value = rx_phy_lane_to_field[phy_lane];
-	address = rx_eb_to_address[eb];
-
-	/*
-	 * need to shift by 4 for reverse EB or 3rd EB in set based on the
-	 * register definition from the KB8001 EVB register map
-	 */
-	switch (eb) {
-	case KB800X_EB1:
-		if (!KB800X_PHY_IS_AB(phy_lane))
-			field_value <<= 4;
-		break;
-	case KB800X_EB4:
-		if (KB800X_PHY_IS_AB(phy_lane))
-			field_value <<= 4;
-		break;
-	case KB800X_EB3:
-	case KB800X_EB6:
-		field_value <<= 4;
-		break;
-	default:
-		break;
-	}
-
-	rv = kb800x_read(me, address, &regval);
-	if (rv)
-		return rv;
-	return kb800x_write(me, address, regval | field_value);
-}
-
-static bool kb800x_in_dpmf(const struct usb_mux *me)
-{
-	if ((cached_mux_state[me->usb_port] & USB_PD_MUX_DP_ENABLED) &&
-	    (cached_mux_state[me->usb_port] & USB_PD_MUX_USB_ENABLED))
-		return true;
-	else
-		return false;
-}
-
-static bool kb800x_is_dp_lane(const struct usb_mux *me,
-			      enum kb800x_ss_lane ss_lane)
-{
-	if (cached_mux_state[me->usb_port] & USB_PD_MUX_DP_ENABLED) {
-		/* DP ALT mode */
-		if (kb800x_in_dpmf(me)) {
-			/* DPMF pin configuration */
-			if ((ss_lane == KB800X_TX1) ||
-			    (ss_lane == KB800X_RX1)) {
-				return true; /* ML0 or ML1 */
-			}
-		} else {
-			/* Pure, 4-lane DP mode */
-			return true;
-		}
-	}
-	/* Not a DP mode or ML2/3 while in DPMF */
-	return false;
-}
-
-/* Assigning this PHY to this SS lane means it should be RX */
-static bool kb800x_phy_ss_lane_is_rx(enum kb800x_phy_lane phy_lane,
-				     enum kb800x_ss_lane ss_lane)
-{
-	bool rx;
-
-	switch (ss_lane) {
-	case KB800X_TX0:
-	case KB800X_TX1:
-		rx = false;
-		break;
-	case KB800X_RX0:
-	case KB800X_RX1:
-		rx = true;
-		break;
-	}
-	/* invert for C/D (host side), since it is receiving the TX signal*/
-	if (!KB800X_PHY_IS_AB(phy_lane))
-		return !rx;
-	return rx;
-}
-
-/* Assign SS lane to PHY. Assumes A/B is connector-side, and C/D is host-side */
-static int kb800x_assign_lane(const struct usb_mux *me,
-			      enum kb800x_phy_lane phy_lane,
-			      enum kb800x_ss_lane ss_lane)
-{
-	enum kb800x_eb eb = 0;
-
-	/*
-	 * Easiest way to handle flipping is to just swap lane 1/0. This assumes
-	 * lanes are flipped in the AP. If they are not, they shouldn't be
-	 * flipped for the AP-side lanes, but should for connector-side
-	 */
-	if (cached_mux_state[me->usb_port] & USB_PD_MUX_POLARITY_INVERTED)
-		ss_lane = KB800X_FLIP_SS_LANE(ss_lane);
-
-	if (kb800x_is_dp_lane(me, ss_lane)) {
-		if (kb800x_in_dpmf(me)) {
-			/* Route USB3 RX/TX to EB1/4, and ML0/1 to EB5/6 */
-			switch (ss_lane) {
-			case KB800X_TX1: /* ML1 */
-				eb = KB800X_EB6;
-				break;
-			case KB800X_RX1: /* ML0 */
-				eb = KB800X_EB5;
-				break;
-			default:
-				break;
-			}
-		} else {
-			/* Route ML0/1/2/3 through EB1/5/4/6 */
-			eb = dp_ss_lane_to_eb[ss_lane];
-		}
-
-		/* For DP lanes, always DFP so A/B is TX, C/D is RX */
-		if (KB800X_PHY_IS_AB(phy_lane))
-			return kb800x_assign_tx_to_eb(me, phy_lane, eb);
-		else
-			return kb800x_assign_rx_to_eb(me, phy_lane, eb);
-	}
-
-	/* Lane is either USB3 or CIO */
-	if (kb800x_phy_ss_lane_is_rx(phy_lane, ss_lane))
-		return kb800x_assign_rx_to_eb(me, phy_lane,
-					      usb_ss_lane_to_eb[ss_lane]);
-	else
-		return kb800x_assign_tx_to_eb(me, phy_lane,
-					      usb_ss_lane_to_eb[ss_lane]);
-}
-
-static int kb800x_xbar_override(const struct usb_mux *me)
-{
-	int rv;
-	int i;
-
-	for (i = KB800X_A0; i < KB800X_PHY_LANE_COUNT; ++i) {
-		rv = kb800x_assign_lane(
-			me, i,
-			kb800x_control[me->usb_port].ss_lanes[i]);
-		if (rv)
-			return rv;
-	}
-	return kb800x_write(me, KB800X_REG_XBAR_OVR,
-				KB800X_XBAR_OVR_EN);
-}
-#endif /* CONFIG_KB800X_CUSTOM_XBAR */
-
-/*
- * The initialization writes for each protocol can be found in the KB8001/KB8002
- * Programming Guidelines
- */
-static const uint16_t global_init_addresses[] = {
-	0x5058, 0x5059, 0xFF63, 0xF021, 0xF022, 0xF057, 0xF058,
-	0x8194, 0xF0C9, 0xF0CA, 0xF0CB, 0xF0CC, 0xF0CD, 0xF0CE,
-	0xF0DF, 0xF0E0, 0xF0E1, 0x8198, 0x8191
-};
-static const uint8_t global_init_values[] = { 0x12, 0x12, 0x3C, 0x02, 0x02,
-					      0x02, 0x02, 0x37, 0x0C, 0x0B,
-					      0x0A, 0x09, 0x08, 0x07, 0x57,
-					      0x66, 0x66, 0x33, 0x00 };
-static const uint16_t usb3_init_addresses[] = { 0xF020, 0xF056 };
-static const uint8_t usb3_init_values[] = { 0x2f, 0x2f };
-static const uint16_t dp_init_addresses[] = { 0xF2CB, 0x0011 };
-static const uint8_t dp_init_values[] = { 0x30, 0x00 };
-/*
- * The first 2 CIO writes apply an SBRX pullup to the host side (C/D)
- * This is required when the CPU doesn't apply a pullup.
- */
-static const uint16_t cio_init_addresses[] = { 0x81fd, 0x81fe, 0xF26B, 0xF26E };
-static const uint8_t cio_init_values[] = { 0x08, 0x80, 0x01, 0x19 };
-
-static int kb800x_bulk_write(const struct usb_mux *me,
-			     const uint16_t *addresses, const uint8_t *values,
-			     const uint8_t size)
-{
-	int i;
-	int rv;
-
-	for (i = 0; i < size; ++i) {
-		rv = kb800x_write(me, addresses[i], values[i]);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int kb800x_global_init(const struct usb_mux *me)
-{
-	return kb800x_bulk_write(me, global_init_addresses, global_init_values,
-				 sizeof(global_init_values));
-}
-
-static int kb800x_dp_init(const struct usb_mux *me, mux_state_t mux_state)
-{
-	int rv;
-
-	rv = kb800x_bulk_write(me, dp_init_addresses, dp_init_values,
-			       sizeof(dp_init_values));
-	if (rv)
-		return rv;
-	return kb800x_write(
-		me, KB800X_REG_ORIENTATION,
-		KB800X_ORIENTATION_DP_DFP |
-			((mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
-				       KB800X_ORIENTATION_POLARITY :
-				       0x0));
-}
-
-static int kb800x_usb3_init(const struct usb_mux *me, mux_state_t mux_state)
-{
-	int rv;
-
-	rv = kb800x_bulk_write(me, usb3_init_addresses, usb3_init_values,
-			       sizeof(usb3_init_values));
-	if (rv)
-		return rv;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		/* This will be overwritten in the DPMF case */
-		return kb800x_write(me, KB800X_REG_ORIENTATION,
-				    KB800X_ORIENTATION_POLARITY);
-	return EC_SUCCESS;
-}
-
-static int kb800x_cio_init(const struct usb_mux *me, mux_state_t mux_state)
-{
-	uint8_t orientation = 0x0;
-	int rv;
-
-	enum idh_ptype cable_type = get_usb_pd_cable_type(me->usb_port);
-	union tbt_mode_resp_cable cable_resp = {
-		.raw_value =
-			pd_get_tbt_mode_vdo(me->usb_port, TCPCI_MSG_SOP_PRIME)
-	};
-
-	rv = kb800x_bulk_write(me, cio_init_addresses, cio_init_values,
-			       sizeof(cio_init_values));
-	if (rv)
-		return rv;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		orientation = KB800X_ORIENTATION_CIO_LANE_SWAP |
-			      KB800X_ORIENTATION_POLARITY;
-
-	if (!(mux_state & USB_PD_MUX_USB4_ENABLED)) {
-		/* Special configuration only for legacy mode */
-		if (cable_type == IDH_PTYPE_ACABLE ||
-		     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
-			/* Active cable */
-			if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) {
-				orientation |=
-					KB800X_ORIENTATION_CIO_LEGACY_UNIDIR;
-			} else {
-				/* 'Pre-Coding on a TBT3-Compatible Link' ECN */
-				rv = kb800x_write(me, 0x8194, 0x31);
-				if (rv)
-					return rv;
-				orientation |=
-					KB800X_ORIENTATION_CIO_LEGACY_BIDIR;
-			}
-		} else {
-			/* Passive Cable */
-			orientation |= KB800X_ORIENTATION_CIO_LEGACY_PASSIVE;
-		}
-	}
-	return kb800x_write(me, KB800X_REG_ORIENTATION, orientation);
-}
-
-static int kb800x_set_state(const struct usb_mux *me, mux_state_t mux_state,
-			    bool *ack_required)
-{
-	int rv;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	cached_mux_state[me->usb_port] = mux_state;
-	rv = kb800x_write(me, KB800X_REG_RESET, KB800X_RESET_MASK);
-	if (rv)
-		return rv;
-	/* Release memory map reset */
-	rv = kb800x_write(me, KB800X_REG_RESET,
-		     KB800X_RESET_MASK & ~KB800X_RESET_MM);
-	if (rv)
-		return rv;
-
-	/* Already in reset, nothing to do */
-	if ((mux_state == USB_PD_MUX_NONE) ||
-	    (mux_state & USB_PD_MUX_SAFE_MODE))
-		return EC_SUCCESS;
-
-	rv = kb800x_global_init(me);
-	if (rv)
-		return rv;
-
-	/* CIO mode (USB4/TBT) */
-	if (mux_state &
-	    (USB_PD_MUX_USB4_ENABLED | USB_PD_MUX_TBT_COMPAT_ENABLED)) {
-		rv = kb800x_cio_init(me, mux_state);
-		if (rv)
-			return rv;
-		rv = kb800x_write(me, KB800X_REG_PROTOCOL, KB800X_PROTOCOL_CIO);
-	} else {
-		/* USB3 enabled (USB3-only or DPMF) */
-		if (mux_state & USB_PD_MUX_USB_ENABLED) {
-			rv = kb800x_usb3_init(me, mux_state);
-			if (rv)
-				return rv;
-			/* USB3-only is the default KB800X_REG_PROTOCOL value */
-		}
-
-		/* DP alt modes (DP-only or DPMF) */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			rv = kb800x_dp_init(me, mux_state);
-			if (rv)
-				return rv;
-			if (mux_state & USB_PD_MUX_USB_ENABLED)
-				rv = kb800x_write(me, KB800X_REG_PROTOCOL,
-						  KB800X_PROTOCOL_DPMF);
-			else
-				rv = kb800x_write(me, KB800X_REG_PROTOCOL,
-						  KB800X_PROTOCOL_DP);
-		}
-	}
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_KB800X_CUSTOM_XBAR
-	rv = kb800x_xbar_override(me);
-	if (rv)
-		return rv;
-#endif /* CONFIG_KB800X_CUSTOM_XBAR */
-
-	return kb800x_write(me, KB800X_REG_RESET, 0x00);
-}
-
-static int kb800x_init(const struct usb_mux *me)
-{
-	gpio_set_level(kb800x_control[me->usb_port].usb_ls_en_gpio, 1);
-	gpio_set_level(kb800x_control[me->usb_port].retimer_rst_gpio, 1);
-
-	/*
-	 * Delay after enabling power and releasing the reset to allow the power
-	 * to come up and the reset to be released by the power sequencing
-	 * logic. If after the delay, the reset is still held low - return an
-	 * error.
-	 */
-	msleep(KB800X_POWER_ON_DELAY_MS);
-	if (!gpio_get_level(kb800x_control[me->usb_port].retimer_rst_gpio))
-		return EC_ERROR_NOT_POWERED;
-
-	return kb800x_set_state(me, USB_PD_MUX_NONE);
-}
-
-static int kb800x_enter_low_power_mode(const struct usb_mux *me)
-{
-	gpio_set_level(kb800x_control[me->usb_port].retimer_rst_gpio, 0);
-	/* Power-down sequencing must be handled in HW */
-	gpio_set_level(kb800x_control[me->usb_port].usb_ls_en_gpio, 0);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_RETIMER
-
-static int console_command_kb800x_xfer(int argc, char **argv)
-{
-	char rw, *e;
-	int rv, port, reg, val;
-	uint8_t data;
-	const struct usb_mux *mux;
-
-	if (argc < 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Get port number */
-	port = strtoi(argv[1], &e, 0);
-	if (*e || !board_is_usb_pd_port_present(port))
-		return EC_ERROR_PARAM1;
-
-	mux = &usb_muxes[port];
-	while (mux) {
-		if (mux->driver == &kb800x_usb_mux_driver)
-			break;
-		mux = mux->next_mux;
-	}
-
-	if (!mux)
-		return EC_ERROR_PARAM1;
-
-	/* Validate r/w selection */
-	rw = argv[2][0];
-	if (rw != 'w' && rw != 'r')
-		return EC_ERROR_PARAM2;
-
-	/* Get register address */
-	reg = strtoi(argv[3], &e, 0);
-	if (*e || reg < 0)
-		return EC_ERROR_PARAM3;
-	rv = EC_SUCCESS;
-	if (rw == 'r')
-		rv = kb800x_read(mux, reg, &data);
-	else {
-		if (argc < 5)
-			return EC_ERROR_PARAM_COUNT;
-		/* Get value to be written */
-		val = strtoi(argv[4], &e, 0);
-		if (*e || val < 0)
-			return EC_ERROR_PARAM4;
-		rv = kb800x_write(mux, reg, val);
-		if (rv == EC_SUCCESS) {
-			rv = kb800x_read(mux, reg, &data);
-			if (rv == EC_SUCCESS && data != val)
-				rv = EC_ERROR_UNKNOWN;
-		}
-	}
-
-	if (rv == EC_SUCCESS)
-		ccprintf("register 0x%x [%d] = 0x%x [%d]\n", reg, reg, data,
-			 data);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(kbxfer, console_command_kb800x_xfer,
-			"<port> <r/w> <reg> | <val>",
-			"Read or write to KB retimer register");
-#endif /* CONFIG_CMD_RETIMER */
-
-const struct usb_mux_driver kb800x_usb_mux_driver = {
-	.init = kb800x_init,
-	.set = kb800x_set_state,
-	.enter_low_power_mode = kb800x_enter_low_power_mode,
-};
diff --git a/driver/retimer/kb800x.h b/driver/retimer/kb800x.h
deleted file mode 100644
index 5f8cf2810d..0000000000
--- a/driver/retimer/kb800x.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Driver for Kandou KB8001 USB-C 40 Gb/s multiprotocol switch.
- */
-
-#ifndef __CROS_EC_KB800X_H
-#define __CROS_EC_KB800X_H
-
-#include "compile_time_macros.h"
-#include "gpio_signal.h"
-#include "usb_mux.h"
-
-#define KB800X_I2C_ADDR0_FLAGS	0x08
-#define KB800X_I2C_ADDR1_FLAGS	0x0C
-
-extern const struct usb_mux_driver kb800x_usb_mux_driver;
-
-/* Set the protocol */
-#define KB800X_REG_PROTOCOL			0x0001
-#define KB800X_PROTOCOL_USB3			0x0
-#define KB800X_PROTOCOL_DPMF			0x1
-#define KB800X_PROTOCOL_DP			0x2
-#define KB800X_PROTOCOL_CIO			0x3
-
-/* Configure the lane orientaitons */
-#define KB800X_REG_ORIENTATION			0x0002
-#define KB800X_ORIENTATION_POLARITY		0x1
-#define KB800X_ORIENTATION_DP_UFP		0x4
-#define KB800X_ORIENTATION_DP_DFP		0x6
-#define KB800X_ORIENTATION_CIO_LANE_SWAP	0x8
-/* Select one, 0x0 for non-legacy */
-#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE	(0x1 << 4)
-#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR	(0x2 << 4)
-#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR	(0x3 << 4)
-
-#define KB800X_REG_RESET			0x0006
-#define KB800X_RESET_FSM			BIT(0)
-#define KB800X_RESET_MM				BIT(1)
-#define KB800X_RESET_SERDES			BIT(2)
-#define KB800X_RESET_COM			BIT(3)
-#define KB800X_RESET_MASK			GENMASK(3, 0)
-
-#define KB800X_REG_XBAR_OVR			0x5040
-#define KB800X_XBAR_OVR_EN			BIT(6)
-
-/* Registers to configure the elastic buffer input connection */
-#define KB800X_REG_XBAR_EB1SEL			0x5044
-#define KB800X_REG_XBAR_EB23SEL			0x5045
-#define KB800X_REG_XBAR_EB4SEL			0x5046
-#define KB800X_REG_XBAR_EB56SEL			0x5047
-
-/* Registers to configure the elastic buffer output connection (x=0-7) */
-#define KB800X_REG_TXSEL_FROM_PHY(x)		(0x5048+((x)/2))
-
-enum kb800x_ss_lane {
-	KB800X_TX0 = 0,
-	KB800X_TX1,
-	KB800X_RX0,
-	KB800X_RX1
-};
-
-enum kb800x_phy_lane {
-	KB800X_A0 = 0,
-	KB800X_A1,
-	KB800X_B0,
-	KB800X_B1,
-	KB800X_C0,
-	KB800X_C1,
-	KB800X_D0,
-	KB800X_D1,
-	KB800X_PHY_LANE_COUNT
-};
-
-enum kb800x_eb {
-	KB800X_EB1 = 0,
-	KB800X_EB2,
-	KB800X_EB3,
-	KB800X_EB4,
-	KB800X_EB5,
-	KB800X_EB6
-};
-
-#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2*((x) & 0x1))
-#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x) & 0x1)
-#define KB800X_PHY_IS_AB(x) ((x) <= KB800X_B1)
-
-struct kb800x_control_t {
-	enum gpio_signal retimer_rst_gpio;
-	enum gpio_signal usb_ls_en_gpio;
-#ifdef CONFIG_KB800X_CUSTOM_XBAR
-	enum kb800x_ss_lane ss_lanes[KB800X_PHY_LANE_COUNT];
-#endif /* CONFIG_KB800X_CUSTOM_XBAR */
-};
-
-/*
- * Default 'example' lane mapping. With this mapping, CONFIG_KB800X_CUSTOM_XBAR
- * can be undefined, since a custom xbar mapping is not needed.
- * ss_lanes = {
- * [KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0,
- * [KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1,
- * [KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0,
- * [KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1,}
- */
-
-extern struct kb800x_control_t kb800x_control[];
-
-
-#endif /* __CROS_EC_KB800X_H  */
diff --git a/driver/retimer/nb7v904m.c b/driver/retimer/nb7v904m.c
deleted file mode 100644
index 94e96230b2..0000000000
--- a/driver/retimer/nb7v904m.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ON Semiconductor NB7V904M USB Type-C DisplayPort Alt Mode Redriver
- */
-#include <stdbool.h>
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "nb7v904m.h"
-#include "usb_mux.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
-int nb7v904m_lpm_disable = 0;
-#endif
-
-static int nb7v904m_write(const struct usb_mux *me, int offset, int data)
-{
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
-
-}
-
-static int nb7v904m_read(const struct usb_mux *me, int offset, int *regval)
-{
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, regval);
-
-}
-
-static int set_low_power_mode(const struct usb_mux *me, bool enable)
-{
-	int regval;
-	int rv;
-
-	rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, &regval);
-	if (rv)
-		return rv;
-#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
-	if (nb7v904m_lpm_disable)
-		enable = 0;
-#endif
-
-	if (enable)
-		regval &= ~NB7V904M_CHIP_EN;
-	else
-		regval |= NB7V904M_CHIP_EN;
-
-	return nb7v904m_write(me, NB7V904M_REG_GEN_DEV_SETTINGS, regval);
-}
-
-static int nb7v904m_enter_low_power_mode(const struct usb_mux *me)
-{
-	int rv = set_low_power_mode(me, 1);
-
-	if (rv)
-		CPRINTS("C%d: NB7V904M: Failed to enter low power mode!",
-			me->usb_port);
-	return rv;
-}
-
-/* Tune USB Eq All: This must be called on board_init context */
-int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
-			uint8_t eq_b, uint8_t eq_c, uint8_t eq_d)
-{
-	int rv = EC_SUCCESS;
-
-	if (eq_a != NB7V904M_CH_ALL_SKIP_EQ)
-		rv = nb7v904m_write(me, NB7V904M_REG_CH_A_EQ_SETTINGS, eq_a);
-
-	if (eq_b != NB7V904M_CH_ALL_SKIP_EQ)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_EQ_SETTINGS, eq_b);
-
-	if (eq_c != NB7V904M_CH_ALL_SKIP_EQ)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_EQ_SETTINGS, eq_c);
-
-	if (eq_d != NB7V904M_CH_ALL_SKIP_EQ)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_EQ_SETTINGS, eq_d);
-
-	return rv;
-}
-
-/* Tune USB Flat Gain: This must be called on board_init context */
-int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
-			uint8_t gain_b, uint8_t gain_c, uint8_t gain_d)
-{
-	int rv = EC_SUCCESS;
-
-	if (gain_a != NB7V904M_CH_ALL_SKIP_GAIN)
-		rv = nb7v904m_write(me, NB7V904M_REG_CH_A_FLAT_GAIN, gain_a);
-
-	if (gain_b != NB7V904M_CH_ALL_SKIP_GAIN)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_FLAT_GAIN, gain_b);
-
-	if (gain_c != NB7V904M_CH_ALL_SKIP_GAIN)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_FLAT_GAIN, gain_c);
-
-	if (gain_d != NB7V904M_CH_ALL_SKIP_GAIN)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_FLAT_GAIN, gain_d);
-
-	return rv;
-}
-
-/* Set Loss Profile Matching : This must be called on board_init context */
-int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
-			uint8_t loss_b, uint8_t loss_c, uint8_t loss_d)
-{
-	int rv = EC_SUCCESS;
-
-	if (loss_a != NB7V904M_CH_ALL_SKIP_LOSS)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_A_LOSS_CTRL, loss_a);
-
-	if (loss_b != NB7V904M_CH_ALL_SKIP_LOSS)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_B_LOSS_CTRL, loss_b);
-
-	if (loss_c != NB7V904M_CH_ALL_SKIP_LOSS)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_C_LOSS_CTRL, loss_c);
-
-	if (loss_d != NB7V904M_CH_ALL_SKIP_LOSS)
-		rv |= nb7v904m_write(me, NB7V904M_REG_CH_D_LOSS_CTRL, loss_d);
-
-	return rv;
-}
-
-/* Set AUX control switch */
-int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch)
-{
-	int rv = EC_SUCCESS;
-
-	rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, aux_ch);
-	return rv;
-}
-
-static int nb7v904m_init(const struct usb_mux *me)
-{
-	int rv = set_low_power_mode(me, 0);
-
-	if (rv)
-		CPRINTS("C%d: NB7V904M: init failed!", me->usb_port);
-	return rv;
-}
-
-static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			    bool *ack_required)
-{
-	int rv = EC_SUCCESS;
-	int regval;
-	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/* Turn off redriver if it's not needed at all. */
-	if (mux_state == USB_PD_MUX_NONE)
-		return nb7v904m_enter_low_power_mode(me);
-
-	rv = nb7v904m_init(me);
-	if (rv)
-		return rv;
-
-	/* Clear operation mode field */
-	rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, &regval);
-	if (rv) {
-		CPRINTS("C%d %s: Failed to obtain dev settings!",
-			me->usb_port, __func__);
-		return rv;
-	}
-	regval &= ~NB7V904M_OP_MODE_MASK;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			if (flipped)
-				regval |= NB7V904M_USB_DP_FLIPPED;
-			else
-				regval |= NB7V904M_USB_DP_NORMAL;
-		} else {
-			/* USB only */
-			regval |= NB7V904M_USB_ONLY;
-		}
-
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* 4 lanes DP */
-		regval |= NB7V904M_DP_ONLY;
-	}
-
-	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Connect AUX */
-		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, flipped ?
-				    NB7V904M_AUX_CH_FLIPPED :
-				    NB7V904M_AUX_CH_NORMAL);
-		/* Enable all channels for DP */
-		regval |= NB7V904M_CH_EN_MASK;
-	} else {
-		/* Disconnect AUX since it's not being used. */
-		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL,
-				    NB7V904M_AUX_CH_HI_Z);
-
-		/* Disable the unused channels to save power */
-		regval &= ~NB7V904M_CH_EN_MASK;
-		if (flipped) {
-			/* Only enable channels A & B */
-			regval |= NB7V904M_CH_A_EN | NB7V904M_CH_B_EN;
-		} else {
-			/* Only enable channels C & D */
-			regval |= NB7V904M_CH_C_EN | NB7V904M_CH_D_EN;
-		}
-	}
-
-	rv |= nb7v904m_write(me, NB7V904M_REG_GEN_DEV_SETTINGS, regval);
-	if (rv)
-		CPRINTS("C%d: %s failed!", me->usb_port, __func__);
-
-	return rv;
-}
-
-const struct usb_mux_driver nb7v904m_usb_redriver_drv = {
-	.enter_low_power_mode = &nb7v904m_enter_low_power_mode,
-	.init = &nb7v904m_init,
-	.set = &nb7v904m_set_mux,
-};
diff --git a/driver/retimer/nb7v904m.h b/driver/retimer/nb7v904m.h
deleted file mode 100644
index d19602153c..0000000000
--- a/driver/retimer/nb7v904m.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ON Semiconductor NB7V904M USB Type-C DisplayPort Alt Mode Redriver
- */
-
-#ifndef __CROS_EC_USB_REDRIVER_NB7V904M_H
-#define __CROS_EC_USB_REDRIVER_NB7V904M_H
-
-#include "compile_time_macros.h"
-#include "usb_mux.h"
-
-#define NB7V904M_I2C_ADDR0 0x19
-#define NB7V904M_I2C_ADDR1 0x1A
-#define NB7V904M_I2C_ADDR2 0x1C
-
-/* Registers */
-#define NB7V904M_REG_GEN_DEV_SETTINGS	0x00
-#define NB7V904M_REG_CH_A_EQ_SETTINGS	0x01
-#define NB7V904M_REG_CH_B_EQ_SETTINGS	0x03
-#define NB7V904M_REG_CH_C_EQ_SETTINGS	0x05
-#define NB7V904M_REG_CH_D_EQ_SETTINGS	0x07
-#define NB7V904M_REG_AUX_CH_CTRL        0x09
-#define NB7V904M_REG_CH_A_FLAT_GAIN		0x18
-#define NB7V904M_REG_CH_A_LOSS_CTRL		0x19
-#define NB7V904M_REG_CH_B_FLAT_GAIN		0x1a
-#define NB7V904M_REG_CH_B_LOSS_CTRL		0x1b
-#define NB7V904M_REG_CH_C_FLAT_GAIN		0x1c
-#define NB7V904M_REG_CH_C_LOSS_CTRL		0x1d
-#define NB7V904M_REG_CH_D_FLAT_GAIN		0x1e
-#define NB7V904M_REG_CH_D_LOSS_CTRL		0x1f
-
-/* 0x00 - General Device Settings */
-#define NB7V904M_CHIP_EN        BIT(0)
-#define NB7V904M_USB_DP_NORMAL  BIT(1)
-#define NB7V904M_USB_DP_FLIPPED 0
-#define NB7V904M_DP_ONLY        BIT(2)
-#define NB7V904M_USB_ONLY       (BIT(3) | BIT(1))
-#define NB7V904M_OP_MODE_MASK   GENMASK(3, 1)
-#define NB7V904M_CH_A_EN        BIT(4)
-#define NB7V904M_CH_B_EN        BIT(5)
-#define NB7V904M_CH_C_EN        BIT(6)
-#define NB7V904M_CH_D_EN        BIT(7)
-#define NB7V904M_CH_EN_MASK     GENMASK(7, 4)
-
-/* 0x01 - Channel A Equalization Settings */
-#define NB7V904M_CH_A_EQ_0_DB	0x0a
-#define NB7V904M_CH_A_EQ_2_DB	0x08
-#define NB7V904M_CH_A_EQ_4_DB	0x0e
-#define NB7V904M_CH_A_EQ_6_DB	0x0c
-#define NB7V904M_CH_A_EQ_8_DB	0x02
-#define NB7V904M_CH_A_EQ_10_DB	0x00
-
-/* 0x03 - Channel B Equalization Settings */
-#define NB7V904M_CH_B_EQ_0_DB	0x0e
-#define NB7V904M_CH_B_EQ_2_DB	0x0c
-#define NB7V904M_CH_B_EQ_4_DB	0x0a
-#define NB7V904M_CH_B_EQ_6_DB	0x08
-#define NB7V904M_CH_B_EQ_8_DB	0x06
-#define NB7V904M_CH_B_EQ_10_DB	0x00
-
-/* 0x05 - Channel C Equalization Settings */
-#define NB7V904M_CH_C_EQ_0_DB	0x0e
-#define NB7V904M_CH_C_EQ_2_DB	0x0c
-#define NB7V904M_CH_C_EQ_4_DB	0x0a
-#define NB7V904M_CH_C_EQ_6_DB	0x08
-#define NB7V904M_CH_C_EQ_8_DB	0x06
-#define NB7V904M_CH_C_EQ_10_DB	0x00
-
-/* 0x07 - Channel D Equalization Settings */
-#define NB7V904M_CH_D_EQ_0_DB	0x0a
-#define NB7V904M_CH_D_EQ_2_DB	0x08
-#define NB7V904M_CH_D_EQ_4_DB	0x0e
-#define NB7V904M_CH_D_EQ_6_DB	0x0c
-#define NB7V904M_CH_D_EQ_8_DB	0x02
-#define NB7V904M_CH_D_EQ_10_DB	0x00
-
-/* 0x09 - Auxiliary Channel Control */
-#define NB7V904M_AUX_CH_NORMAL   0
-#define NB7V904M_AUX_CH_FLIPPED  BIT(0)
-#define NB7V904M_AUX_CH_HI_Z     BIT(1)
-
-/* 0x18 - Channel A Flag Gain */
-#define NB7V904M_CH_A_GAIN_0_DB		0x00
-#define NB7V904M_CH_A_GAIN_1P5_DB	0x02
-#define NB7V904M_CH_A_GAIN_3P5_DB	0x03
-
-/* 0x1a - Channel B Flag Gain */
-#define NB7V904M_CH_B_GAIN_0_DB		0x03
-#define NB7V904M_CH_B_GAIN_1P5_DB	0x01
-#define NB7V904M_CH_B_GAIN_3P5_DB	0x00
-
-/* 0x1c - Channel C Flag Gain */
-#define NB7V904M_CH_C_GAIN_0_DB		0x03
-#define NB7V904M_CH_C_GAIN_1P5_DB	0x01
-#define NB7V904M_CH_C_GAIN_3P5_DB	0x00
-
-/* 0x1e - Channel D Flag Gain */
-#define NB7V904M_CH_D_GAIN_0_DB		0x00
-#define NB7V904M_CH_D_GAIN_1P5_DB	0x02
-#define NB7V904M_CH_D_GAIN_3P5_DB	0x03
-
-/* 0x19 - Channel A Loss Profile Matching Control */
-/* 0x1b - Channel B Loss Profile Matching Control */
-/* 0x1d - Channel C Loss Profile Matching Control */
-/* 0x1f - Channel D Loss Profile Matching Control */
-#define NB7V904M_LOSS_PROFILE_A		0x00
-#define NB7V904M_LOSS_PROFILE_B		0x01
-#define NB7V904M_LOSS_PROFILE_C		0x02
-#define NB7V904M_LOSS_PROFILE_D		0x03
-
-extern const struct usb_mux_driver nb7v904m_usb_redriver_drv;
-#ifdef CONFIG_NB7V904M_LPM_OVERRIDE
-extern int nb7v904m_lpm_disable;
-#endif
-
-/* Use this value if tuning eq wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_EQ	0xff
-int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
-			uint8_t eq_b, uint8_t eq_c, uint8_t eq_d);
-/* Use this value if tuning gain wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_GAIN	0xff
-int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
-			uint8_t gain_b, uint8_t gain_c, uint8_t gain_d);
-/* Use this value if loss profile control  wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_LOSS	0xff
-/* Control channel Loss Profile Matching */
-int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
-			uint8_t loss_b, uint8_t loss_c, uint8_t loss_d);
-/* Control mapping between AUX and SBU */
-int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch);
-#endif /* __CROS_EC_USB_REDRIVER_NB7V904M_H */
diff --git a/driver/retimer/pi3dpx1207.c b/driver/retimer/pi3dpx1207.c
deleted file mode 100644
index 8829c508a1..0000000000
--- a/driver/retimer/pi3dpx1207.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PI3DPX1207 retimer.
- */
-
-#include "pi3dpx1207.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "usb_mux.h"
-
-#define I2C_MAX_RETRIES 2
-
-/* Stack space is limited, so put the buffer somewhere else */
-static uint8_t buf[PI3DPX1207_NUM_REGISTERS];
-
-/**
- * Local utility functions
- */
-static int pi3dpx1207_i2c_write(const struct usb_mux *me,
-				uint8_t offset,
-				uint8_t val)
-{
-	int rv = EC_SUCCESS;
-	int attempt;
-
-	if (offset >= PI3DPX1207_NUM_REGISTERS)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * PI3DPX1207 does not support device register offset in
-	 * the typical I2C sense. Have to read the values starting
-	 * from 0, modify the byte and then write the block.
-	 *
-	 * NOTE: The device may not respond correctly if it was
-	 * just powered or has gone to sleep.  Allow for retries
-	 * in case this happens.
-	 */
-	if (offset > 0) {
-		attempt = 0;
-		do {
-			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      NULL, 0, buf, offset);
-		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
-	}
-
-	if (rv == EC_SUCCESS) {
-		buf[offset] = val;
-
-		attempt = 0;
-		do {
-			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      buf, offset + 1, NULL, 0);
-		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
-	}
-	return rv;
-}
-
-static void pi3dpx1207_shutoff_power(const struct usb_mux *me)
-{
-	const int port = me->usb_port;
-	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
-	const int gpio_dp_enable = pi3dpx1207_controls[port].dp_enable_gpio;
-
-	gpio_or_ioex_set_level(gpio_enable, 0);
-	gpio_or_ioex_set_level(gpio_dp_enable, 0);
-}
-
-/**
- * Driver interface code
- */
-static int pi3dpx1207_init(const struct usb_mux *me)
-{
-	const int port = me->usb_port;
-	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
-
-	gpio_or_ioex_set_level(gpio_enable, 1);
-	return EC_SUCCESS;
-}
-
-static int pi3dpx1207_enter_low_power_mode(const struct usb_mux *me)
-{
-	pi3dpx1207_shutoff_power(me);
-	return EC_SUCCESS;
-}
-
-static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	int rv = EC_SUCCESS;
-	uint8_t mode_val = PI3DPX1207_MODE_WATCHDOG_EN;
-	const int port = me->usb_port;
-	const int gpio_enable = pi3dpx1207_controls[port].enable_gpio;
-	const int gpio_dp_enable = pi3dpx1207_controls[port].dp_enable_gpio;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/* USB */
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		gpio_or_ioex_set_level(gpio_enable, 1);
-		/* USB with DP */
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			gpio_or_ioex_set_level(gpio_dp_enable, 1);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_DP_FLIP
-					: PI3DPX1207_MODE_CONF_USB_DP;
-		}
-		/* USB without DP */
-		else {
-			gpio_or_ioex_set_level(gpio_dp_enable, 0);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_FLIP
-					: PI3DPX1207_MODE_CONF_USB;
-		}
-	}
-	/* DP without USB */
-	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		gpio_or_ioex_set_level(gpio_enable, 1);
-		gpio_or_ioex_set_level(gpio_dp_enable, 1);
-		mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? PI3DPX1207_MODE_CONF_DP_FLIP
-				: PI3DPX1207_MODE_CONF_DP;
-	}
-	/* Nothing enabled, power down the retimer */
-	else {
-		pi3dpx1207_shutoff_power(me);
-		return EC_SUCCESS;
-	}
-
-	/* Write the retimer config byte */
-	rv = pi3dpx1207_i2c_write(me, PI3DPX1207_MODE_OFFSET, mode_val);
-	return rv;
-}
-
-const struct usb_mux_driver pi3dpx1207_usb_retimer = {
-	.init = pi3dpx1207_init,
-	.set = pi3dpx1207_set_mux,
-	.enter_low_power_mode = pi3dpx1207_enter_low_power_mode,
-};
diff --git a/driver/retimer/pi3dpx1207.h b/driver/retimer/pi3dpx1207.h
deleted file mode 100644
index 2e3405d1aa..0000000000
--- a/driver/retimer/pi3dpx1207.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PI3DPX1207 retimer.
- */
-#include "gpio.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PI3PDX1207_H
-#define __CROS_EC_USB_RETIMER_PI3PDX1207_H
-
-#define PI3DPX1207_I2C_ADDR_FLAGS	0x57
-#define PI3DPX1207_NUM_REGISTERS	32
-
-/* Register Offset 0 - Revision and Vendor ID */
-#define PI3DPX1207_VID_OFFSET		0
-
-#define PI3DPX1207B_VID				0x03
-#define PI3DPX1207C_VID				0x13
-
-/* Register Offset 1 - Device Type/ID */
-#define PI3DPX1207_DID_OFFSET		1
-
-#define PI3DPX1207_DID_ACTIVE_MUX		0x11
-
-/* Register Offset 3 - Mode Control */
-#define PI3DPX1207_MODE_OFFSET		3
-
-#define PI3DPX1207_MODE_WATCHDOG_EN		0x02
-
-#define PI3DPX1207B_MODE_GEN_APP_EN		0x08
-
-#define PI3DPX1207_MODE_CONF_SAFE		0x00
-#define PI3DPX1207_MODE_CONF_DP			0x20
-#define PI3DPX1207_MODE_CONF_DP_FLIP		0x30
-#define PI3DPX1207_MODE_CONF_USB		0x40
-#define PI3DPX1207_MODE_CONF_USB_FLIP		0x50
-#define PI3DPX1207_MODE_CONF_USB_DP		0x60
-#define PI3DPX1207_MODE_CONF_USB_DP_FLIP	0x70
-#define PI3DPX1207_MODE_CONF_USB_SUPER		0xC0
-
-/* Supported USB retimer drivers */
-extern const struct usb_mux_driver pi3dpx1207_usb_retimer;
-
-/* Retimer driver hardware specific controls */
-struct pi3dpx1207_usb_control {
-	/* Retimer enable */
-	const enum gpio_signal enable_gpio;
-	/* DP Mode enable */
-	const enum gpio_signal dp_enable_gpio;
-};
-extern const struct pi3dpx1207_usb_control pi3dpx1207_controls[];
-
-#endif /* __CROS_EC_USB_RETIMER_PI3PDX1207_H */
diff --git a/driver/retimer/pi3hdx1204.c b/driver/retimer/pi3hdx1204.c
deleted file mode 100644
index 3b0d80609f..0000000000
--- a/driver/retimer/pi3hdx1204.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PI3HDX1204 retimer.
- */
-
-#include "i2c.h"
-#include "pi3hdx1204.h"
-
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
-		      const int enable)
-{
-	const uint8_t buf[PI3HDX1204_DE_OFFSET + 1] = {
-		[PI3HDX1204_ACTIVITY_OFFSET] = 0, /* Read Only */
-		[PI3HDX1204_NOT_USED_OFFSET] = 0, /* Read Only */
-		[PI3HDX1204_ENABLE_OFFSET] =
-			enable ? PI3HDX1204_ENABLE_ALL_CHANNELS : 0,
-		[PI3HDX1204_EQ_CH0_CH1_OFFSET] =
-			pi3hdx1204_tuning.eq_ch0_ch1_offset,
-		[PI3HDX1204_EQ_CH2_CH3_OFFSET] =
-			pi3hdx1204_tuning.eq_ch2_ch3_offset,
-		[PI3HDX1204_VOD_OFFSET] = pi3hdx1204_tuning.vod_offset,
-		[PI3HDX1204_DE_OFFSET] = pi3hdx1204_tuning.de_offset,
-	};
-	int rv;
-
-	rv = i2c_xfer(i2c_port, i2c_addr_flags,
-		      buf, PI3HDX1204_DE_OFFSET + 1,
-		      NULL, 0);
-
-	if (rv)
-		ccprints("pi3hdx1204 enable failed: %d", rv);
-
-	return rv;
-}
diff --git a/driver/retimer/pi3hdx1204.h b/driver/retimer/pi3hdx1204.h
deleted file mode 100644
index 825f502602..0000000000
--- a/driver/retimer/pi3hdx1204.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PI3HDX1204 retimer.
- */
-
-#ifndef __CROS_EC_USB_RETIMER_PI3HDX1204_H
-#define __CROS_EC_USB_RETIMER_PI3HDX1204_H
-
-#define PI3HDX1204_I2C_ADDR_FLAGS	0x60
-
-/* Register Offset 0 - Activity */
-#define PI3HDX1204_ACTIVITY_OFFSET	0
-
-/* Register Offset 1 - Not Used */
-#define PI3HDX1204_NOT_USED_OFFSET	1
-
-/* Register Offset 2 - Enable */
-#define PI3HDX1204_ENABLE_OFFSET	2
-#define PI3HDX1204_ENABLE_ALL_CHANNELS	0xF0
-
-/* Register Offset 3 - EQ setting BIT7-4:CH1, BIT3-0:CH0 */
-#define PI3HDX1204_EQ_CH0_CH1_OFFSET	3
-
-/* Register Offset 4 - EQ setting BIT7-4:CH3, BIT3-0:CH2 */
-#define PI3HDX1204_EQ_CH2_CH3_OFFSET	4
-
-/* EQ setting for two channel */
-#define PI3HDX1204_EQ_DB25	0x00
-#define PI3HDX1204_EQ_DB80	0x11
-#define PI3HDX1204_EQ_DB110	0x22
-#define PI3HDX1204_EQ_DB220	0x33
-#define PI3HDX1204_EQ_DB410	0x44
-#define PI3HDX1204_EQ_DB710	0x55
-#define PI3HDX1204_EQ_DB900	0x66
-#define PI3HDX1204_EQ_DB1030	0x77
-#define PI3HDX1204_EQ_DB1180	0x88
-#define PI3HDX1204_EQ_DB1390	0x99
-#define PI3HDX1204_EQ_DB1530	0xAA
-#define PI3HDX1204_EQ_DB1690	0xBB
-#define PI3HDX1204_EQ_DB1790	0xCC
-#define PI3HDX1204_EQ_DB1920	0xDD
-#define PI3HDX1204_EQ_DB2050	0xEE
-#define PI3HDX1204_EQ_DB2220	0xFF
-
-/* Register Offset 5 - Output Voltage Swing Setting */
-#define PI3HDX1204_VOD_OFFSET	5
-#define PI3HDX1204_VOD_80_ALL_CHANNELS	0x00
-#define PI3HDX1204_VOD_95_ALL_CHANNELS	0x55
-#define PI3HDX1204_VOD_115_ALL_CHANNELS	0xAA
-#define PI3HDX1204_VOD_130_ALL_CHANNELS	0xFF
-
-/* Register Offset 6 - Output De-emphasis Setting */
-#define PI3HDX1204_DE_OFFSET	6
-#define PI3HDX1204_DE_DB_0		0x00
-#define PI3HDX1204_DE_DB_MINUS5		0x55
-#define PI3HDX1204_DE_DB_MINUS7		0xAA
-#define PI3HDX1204_DE_DB_MINUS10	0xFF
-
-/* Delay for I2C to be ready after power on. */
-#define PI3HDX1204_POWER_ON_DELAY_MS 2
-
-/* Enable or disable the PI3HDX1204. */
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
-		      const int enable);
-
-struct pi3hdx1204_tuning {
-	uint8_t eq_ch0_ch1_offset;
-	uint8_t eq_ch2_ch3_offset;
-	uint8_t vod_offset;
-	uint8_t de_offset;
-};
-extern const struct pi3hdx1204_tuning pi3hdx1204_tuning;
-
-#endif /* __CROS_EC_USB_RETIMER_PI3HDX1204_H */
diff --git a/driver/retimer/ps8802.c b/driver/retimer/ps8802.c
deleted file mode 100644
index 9738123ace..0000000000
--- a/driver/retimer/ps8802.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8802 retimer.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "ps8802.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-#define PS8802_DEBUG 0
-#define PS8802_I2C_WAKE_DELAY 500
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
-{
-	int rv;
-
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
-
-	if (PS8802_DEBUG)
-		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
-
-	return rv;
-}
-
-int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
-
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
-
-	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-		       int data)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
-
-	rv = i2c_write16(me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data);
-
-	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%04X) "
-			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
-			     uint8_t field_mask, uint8_t set_value)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &pre_val);
-
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
-
-	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
-			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
-
-	rv = i2c_field_update16(me->i2c_port,
-				me->i2c_addr_flags + page,
-				offset,
-				field_mask,
-				set_value);
-
-	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%04X) "
-			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-/*
- * If PS8802 is in I2C standby mode, wake it up by reading PS8802_REG_MODE.
- * From Application Note: 1) Activate by reading any Page 2 register. 2) Wait
- * 500 microseconds. 3) After 5 seconds idle, PS8802 will return to standby.
- */
-int ps8802_i2c_wake(const struct usb_mux *me)
-{
-	int data;
-	int rv = EC_ERROR_UNKNOWN;
-
-	/* If in standby, first read will fail, second should succeed. */
-	for (int i = 0; i < 2; i++) {
-		rv = ps8802_i2c_read(me,
-				     PS8802_REG_PAGE2,
-				     PS8802_REG2_MODE,
-				     &data);
-		if (rv == EC_SUCCESS)
-			return rv;
-
-		usleep(PS8802_I2C_WAKE_DELAY);
-	}
-
-	return rv;
-}
-
-/*
- * Setting operation mode to standby mode
- */
-static int ps8802_enter_low_power_mode(const struct usb_mux *me)
-{
-	int rv;
-
-	rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE,
-		  PS8802_MODE_STANDBY_MODE);
-
-	if (rv)
-		CPRINTS("C%d: PS8802: Failed to enter low power mode!",
-			me->usb_port);
-
-	return rv;
-}
-
-static int ps8802_init(const struct usb_mux *me)
-{
-	ps8802_enter_low_power_mode(me);
-	return EC_SUCCESS;
-}
-
-static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	int val;
-	int rv;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
-
-	/* Make sure the PS8802 is awake */
-	rv = ps8802_i2c_wake(me);
-	if (rv)
-		return rv;
-
-	if (PS8802_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
-
-	/* Set the mode and flip */
-	val = (PS8802_MODE_DP_REG_CONTROL |
-	       PS8802_MODE_USB_REG_CONTROL |
-	       PS8802_MODE_FLIP_REG_CONTROL |
-	       PS8802_MODE_IN_HPD_REG_CONTROL);
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val |= PS8802_MODE_USB_ENABLE;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val |= PS8802_MODE_DP_ENABLE | PS8802_MODE_IN_HPD_ENABLE;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		val |= PS8802_MODE_FLIP_ENABLE;
-
-	rv = ps8802_i2c_write(me,
-			      PS8802_REG_PAGE2,
-			      PS8802_REG2_MODE,
-			      val);
-
-	return rv;
-}
-
-static int ps8802_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int rv;
-	int val;
-
-	*mux_state = USB_PD_MUX_NONE;
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	rv = ps8802_i2c_wake(me);
-	if (rv)
-		return rv;
-
-	rv = ps8802_i2c_read(me,
-			     PS8802_REG_PAGE2,
-			     PS8802_REG2_MODE,
-			     &val);
-	if (rv)
-		return rv;
-
-	if (val & PS8802_MODE_USB_ENABLE)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (val & PS8802_MODE_DP_ENABLE)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (val & PS8802_MODE_FLIP_ENABLE)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return rv;
-}
-
-const struct usb_mux_driver ps8802_usb_mux_driver = {
-	.init = ps8802_init,
-	.set = ps8802_set_mux,
-	.get = ps8802_get_mux,
-	.enter_low_power_mode = &ps8802_enter_low_power_mode,
-};
-
-/*
- * If PS8802 I2c address was conflicted, change
- * the I2c address in page 0x0A, offset 0xB0
- * switch to 0x50 8-bit address
- */
-int ps8802_chg_i2c_addr(int i2c_port)
-{
-	int rv;
-
-	rv = i2c_write8(i2c_port,
-			PS8802_P1_ADDR, PS8802_ADDR_CFG,
-			PS8802_I2C_ADDR_FLAGS_ALT);
-
-	return rv;
-}
diff --git a/driver/retimer/ps8802.h b/driver/retimer/ps8802.h
deleted file mode 100644
index 858b83bfc7..0000000000
--- a/driver/retimer/ps8802.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8802 retimer.
- */
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PS8802_H
-#define __CROS_EC_USB_RETIMER_PS8802_H
-
-/*
- * PS8802 uses 7-bit I2C addresses 0x08 to 0x17 (ADDR=L).
- * Page 0 = 0x08, Page 1 = 0x09, Page 2 = 0x0A.
- */
-#define PS8802_I2C_ADDR_FLAGS	0x08
-
-/*
- * PS8802 uses 7-bit I2C addresses 0x28 to 0x37.
- * Page 0 = 0x028, Page 1 = 0x29, Page 2 = 0x2A.
- */
-#define PS8802_I2C_ADDR_FLAGS_CUSTOM	0x28
-
-/*
- * PAGE 0 Register Definitions
- */
-#define PS8802_REG_PAGE0	0x00
-
-#define PS8802_REG0_TX_STATUS		0x72
-#define PS8802_REG0_RX_STATUS		0x76
-#define PS8802_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8802_STATUS_10_GBPS			BIT(5)
-
-/*
- * PAGE 1 Register Definitions
- */
-#define PS8802_REG_PAGE1	0x01
-
-#define PS8802_800MV_LEVEL_TUNING	0x8A
-#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT	0X00
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1	0X01
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2	0X02
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3	0X03
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4	0X04
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1	0X05
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2	0X06
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3	0X07
-#define PS8802_EXTRA_SWING_LEVEL_P0_MASK	0X07
-
-/*
- * PAGE 2 Register Definitions
- */
-#define PS8802_REG_PAGE2	0x02
-
-#define PS8802_REG2_USB_SSEQ_LEVEL	0x02
-#define PS8802_REG2_USB_CEQ_LEVEL	0x04
-#define PS8802_USBEQ_LEVEL_UP_12DB		(0x0000 | 0x0003)
-#define PS8802_USBEQ_LEVEL_UP_13DB		(0x0400 | 0x0007)
-#define PS8802_USBEQ_LEVEL_UP_16DB		(0x0C00 | 0x000F)
-#define PS8802_USBEQ_LEVEL_UP_17DB		(0x1C00 | 0x001F)
-#define PS8802_USBEQ_LEVEL_UP_18DB		(0x3C00 | 0x003F)
-#define PS8802_USBEQ_LEVEL_UP_19DB		(0x7C00 | 0x007F)
-#define PS8802_USBEQ_LEVEL_UP_20DB		(0xFC00 | 0x00FF)
-#define PS8802_USBEQ_LEVEL_UP_23DB		(0xFD00 | 0x01FF)
-#define PS8802_USBEQ_LEVEL_UP_MASK		0xFDFF
-
-#define PS8802_REG2_MODE		0x06
-#define PS8802_MODE_DP_REG_CONTROL		BIT(7)
-#define PS8802_MODE_DP_ENABLE			BIT(6)
-#define PS8802_MODE_USB_REG_CONTROL		BIT(5)
-#define PS8802_MODE_USB_ENABLE			BIT(4)
-#define PS8802_MODE_FLIP_REG_CONTROL		BIT(3)
-#define PS8802_MODE_FLIP_ENABLE			BIT(2)
-#define PS8802_MODE_IN_HPD_REG_CONTROL		BIT(1)
-#define PS8802_MODE_IN_HPD_ENABLE		BIT(0)
-
-/*
- * Support power saving mode, Bit7 Disable
- * CE_DP, Bit5 Disable CE_USB, Bit3 Disable
- * FLIP pin, Bit1 Display IN_HPD pin, [Bit6 Bit4]
- * 00: I2C standy by mode.
- */
-#define PS8802_MODE_STANDBY_MODE		0xAA
-
-#define PS8802_REG2_DPEQ_LEVEL		0x07
-#define PS8802_DPEQ_LEVEL_UP_9DB		0x00
-#define PS8802_DPEQ_LEVEL_UP_11DB		0x01
-#define PS8802_DPEQ_LEVEL_UP_12DB		0x02
-#define PS8802_DPEQ_LEVEL_UP_14DB		0x03
-#define PS8802_DPEQ_LEVEL_UP_17DB		0x04
-#define PS8802_DPEQ_LEVEL_UP_18DB		0x05
-#define PS8802_DPEQ_LEVEL_UP_19DB		0x06
-#define PS8802_DPEQ_LEVEL_UP_20DB		0x07
-#define PS8802_DPEQ_LEVEL_UP_21DB		0x08
-#define PS8802_DPEQ_LEVEL_UP_MASK		0x0F
-
-#define PS8802_P1_ADDR			0x0A
-#define PS8802_ADDR_CFG			0xB0
-#define PS8802_I2C_ADDR_FLAGS_ALT	0x50
-
-extern const struct usb_mux_driver ps8802_usb_mux_driver;
-
-int ps8802_i2c_wake(const struct usb_mux *me);
-int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
-int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data);
-int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-			int data);
-int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
-			     uint8_t field_mask, uint8_t set_value);
-int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value);
-int ps8802_chg_i2c_addr(int i2c_port);
-
-#endif /* __CROS_EC_USB_RETIMER_PS8802_H */
diff --git a/driver/retimer/ps8811.c b/driver/retimer/ps8811.c
deleted file mode 100644
index 6a66248d38..0000000000
--- a/driver/retimer/ps8811.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8811 retimer.
- */
-
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "ps8811.h"
-#include "usb_mux.h"
-
-int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
-{
-	int rv;
-
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
-
-	return rv;
-}
-
-int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data)
-{
-	int rv;
-
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
-
-	return rv;
-}
-
-int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset,
-			     uint8_t field_mask, uint8_t set_value)
-{
-	int rv;
-
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
-
-	return rv;
-}
diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h
deleted file mode 100644
index c3a98c1660..0000000000
--- a/driver/retimer/ps8811.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8811 retimer.
- */
-
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PS8811_H
-#define __CROS_EC_USB_RETIMER_PS8811_H
-
-/*
- * PS8811 uses 7-bit I2C addresses 0x28 to 0x29 (ADDR=LL).
- * Page 0 = 0x28, Page 1 = 0x29.
- * PS8811 uses 7-bit I2C addresses 0x2A to 0x2B (ADDR=LH).
- * Page 0 = 0x2A, Page 1 = 0x2B.
- * PS8811 uses 7-bit I2C addresses 0x70 to 0x71 (ADDR=HL).
- * Page 0 = 0x70, Page 1 = 0x71.
- * PS8811 uses 7-bit I2C addresses 0x72 to 0x73 (ADDR=HH).
- * Page 0 = 0x72, Page 1 = 0x73.
- */
-#define PS8811_I2C_ADDR_FLAGS0	0x28
-#define PS8811_I2C_ADDR_FLAGS1	0x2A
-#define PS8811_I2C_ADDR_FLAGS2	0x70
-#define PS8811_I2C_ADDR_FLAGS3	0x72
-
-/*
- * PAGE 1 Register Definitions
- */
-#define PS8811_REG_PAGE1			0x01
-
-#define PS8811_REG1_USB_BEQ_LEVEL		0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_PIN_LEVEL_UP_10_5DB		0x01
-#define PS8811_BEQ_PIN_LEVEL_UP_12DB		0x02
-#define PS8811_BEQ_PIN_LEVEL_UP_13DB		0x03
-#define PS8811_BEQ_PIN_LEVEL_UP_16DB		0x04
-#define PS8811_BEQ_PIN_LEVEL_UP_17DB		0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_18DB		0x06
-#define PS8811_BEQ_PIN_LEVEL_UP_19DB		0x07
-#define PS8811_BEQ_PIN_LEVEL_UP_20DB		0x08
-#define PS8811_BEQ_PIN_LEVEL_UP_21DB		0x09
-#define PS8811_BEQ_PIN_LEVEL_UP_23DB		0x0A
-#define PS8811_BEQ_I2C_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_I2C_LEVEL_UP_10_5DB		0x10
-#define PS8811_BEQ_I2C_LEVEL_UP_12DB		0x20
-#define PS8811_BEQ_I2C_LEVEL_UP_13DB		0x30
-#define PS8811_BEQ_I2C_LEVEL_UP_16DB		0x40
-#define PS8811_BEQ_I2C_LEVEL_UP_17DB		0x50
-#define PS8811_BEQ_I2C_LEVEL_UP_18DB		0x60
-#define PS8811_BEQ_I2C_LEVEL_UP_19DB		0x70
-#define PS8811_BEQ_I2C_LEVEL_UP_20DB		0x80
-#define PS8811_BEQ_I2C_LEVEL_UP_21DB		0x90
-#define PS8811_BEQ_I2C_LEVEL_UP_23DB		0xA0
-
-#define PS8811_REG1_USB_BEQ_CONFIG		0x06
-#define PS8811_BEQ_CONFIG_REG_ENABLE		BIT(0)
-
-#define PS8811_REG1_USB_CHAN_A_SWING		0x66
-#define PS8811_CHAN_A_SWING_MASK		GENMASK(6, 4)
-#define PS8811_CHAN_A_SWING_SHIFT		4
-
-#define PS8811_REG1_USB_CHAN_B_SWING		0xA4
-#define PS8811_CHAN_B_SWING_MASK		GENMASK(2, 0)
-#define PS8811_CHAN_B_SWING_SHIFT		0
-
-/* De-emphasis -2.2 dB, Pre-shoot 1.2 dB */
-#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB		0x1
-#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB		0x13
-
-/* De-emphasis -3.5 dB, Pre-shoot 0 dB */
-#define PS8811_CHAN_B_DE_3_5_PS_0_LSB		0x0
-#define PS8811_CHAN_B_DE_3_5_PS_0_MSB		0x5
-
-/* De-emphasis -4.5 dB, Pre-shoot 0 dB */
-#define PS8811_CHAN_B_DE_4_5_PS_0_LSB		0x0
-#define PS8811_CHAN_B_DE_4_5_PS_0_MSB		0x6
-
-/* De-emphasis -6 dB, Pre-shoot 1.5 dB */
-#define PS8811_CHAN_B_DE_6_PS_1_5_LSB		0x2
-#define PS8811_CHAN_B_DE_6_PS_1_5_MSB		0x16
-
-/* De-emphasis -6 dB, Pre-shoot 3 dB */
-#define PS8811_CHAN_B_DE_6_PS_3_LSB		0x4
-#define PS8811_CHAN_B_DE_6_PS_3_MSB		0x16
-
-#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB	0xA5
-#define PS8811_CHAN_B_DE_PS_LSB_MASK		GENMASK(2, 0)
-
-#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB	0xA6
-#define PS8811_CHAN_B_DE_PS_MSB_MASK		GENMASK(5, 0)
-
-int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
-int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data);
-int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset,
-			    uint8_t field_mask, uint8_t set_value);
-
-#endif /* __CROS_EC_USB_RETIMER_PS8802_H */
diff --git a/driver/retimer/ps8818.c b/driver/retimer/ps8818.c
deleted file mode 100644
index 2f8e353099..0000000000
--- a/driver/retimer/ps8818.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8818 retimer.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "ps8818.h"
-#include "usb_mux.h"
-
-#define PS8818_DEBUG 0
-
-int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
-{
-	int rv;
-
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
-
-	if (PS8818_DEBUG)
-		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
-
-	return rv;
-}
-
-int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
-
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
-
-	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset,
-			     uint8_t field_mask, uint8_t set_value)
-{
-	int rv;
-	int pre_val, post_val;
-
-	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
-
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
-
-	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
-
-		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
-			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
-	}
-
-	return rv;
-}
-
-static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	int rv;
-	int val = 0;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
-
-	if (PS8818_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
-
-	/* Set the mode */
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val |= PS8818_MODE_USB_ENABLE;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val |= PS8818_MODE_DP_ENABLE;
-
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_MODE,
-				PS8818_MODE_NON_RESERVED_MASK,
-				val);
-	if (rv)
-		return rv;
-
-	/* Set the flip */
-	val = 0;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		val |= PS8818_FLIP_CONFIG;
-
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_FLIP,
-				PS8818_FLIP_NON_RESERVED_MASK,
-				val);
-	if (rv)
-		return rv;
-
-	/* Set the IN_HPD */
-	val = PS8818_DPHPD_CONFIG_INHPD_DISABLE;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val |= PS8818_DPHPD_PLUGGED;
-
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_DPHPD_CONFIG,
-				PS8818_DPHPD_NON_RESERVED_MASK,
-				val);
-
-	return rv;
-}
-
-const struct usb_mux_driver ps8818_usb_retimer_driver = {
-	.set = ps8818_set_mux,
-};
diff --git a/driver/retimer/ps8818.h b/driver/retimer/ps8818.h
deleted file mode 100644
index b56df4b411..0000000000
--- a/driver/retimer/ps8818.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8818 retimer.
- */
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PS8818_H
-#define __CROS_EC_USB_RETIMER_PS8818_H
-
-#define PS8818_I2C_ADDR_FLAGS	0x28
-
-/*
- * PAGE 0 Register Definitions
- */
-#define PS8818_REG_PAGE0	0x00
-
-#define PS8818_REG0_FLIP		0x00
-#define PS8818_FLIP_CONFIG			BIT(7)
-#define PS8818_FLIP_NON_RESERVED_MASK		0xE0
-
-#define PS8818_REG0_MODE		0x01
-#define PS8818_MODE_DP_ENABLE			BIT(7)
-#define PS8818_MODE_USB_ENABLE			BIT(6)
-#define PS8818_MODE_NON_RESERVED_MASK		0xC0
-
-#define PS8818_REG0_DPHPD_CONFIG	0x02
-#define PS8818_DPHPD_CONFIG_INHPD_DISABLE	BIT(7)
-#define PS8818_DPHPD_PLUGGED			BIT(6)
-#define PS8818_DPHPD_NON_RESERVED_MASK		0xFC
-
-/*
- * PAGE 1 Register Definitions
- */
-#define PS8818_REG_PAGE1	0x01
-
-#define PS8818_REG1_APTX1EQ_10G_LEVEL	0x00
-#define PS8818_REG1_APTX2EQ_10G_LEVEL	0x02
-#define PS8818_REG1_CRX1EQ_10G_LEVEL	0x08
-#define PS8818_REG1_CRX2EQ_10G_LEVEL	0x0A
-#define PS8818_REG1_APRX1_DE_LEVEL	0x0C
-#define PS8818_REG1_APTX1EQ_5G_LEVEL	0x70
-#define PS8818_REG1_APTX2EQ_5G_LEVEL	0x72
-#define PS8818_REG1_CRX1EQ_5G_LEVEL	0x78
-#define PS8818_REG1_CRX2EQ_5G_LEVEL	0x7A
-#define PS8818_EQ_LEVEL_UP_9DB			(0)
-#define PS8818_EQ_LEVEL_UP_10DB			(1)
-#define PS8818_EQ_LEVEL_UP_12DB			(2)
-#define PS8818_EQ_LEVEL_UP_13DB			(3)
-#define PS8818_EQ_LEVEL_UP_16DB			(4)
-#define PS8818_EQ_LEVEL_UP_17DB			(5)
-#define PS8818_EQ_LEVEL_UP_18DB			(6)
-#define PS8818_EQ_LEVEL_UP_19DB			(7)
-#define PS8818_EQ_LEVEL_UP_20DB			(8)
-#define PS8818_EQ_LEVEL_UP_21DB			(9)
-#define PS8818_EQ_LEVEL_UP_MASK			(0x0F)
-
-#define PS8818_REG1_RX_PHY		0x6D
-#define PS8818_RX_INPUT_TERM_112_OHM		(0 << 6)
-#define PS8818_RX_INPUT_TERM_104_OHM		(1 << 6)
-#define PS8818_RX_INPUT_TERM_96_OHM		(2 << 6)
-#define PS8818_RX_INPUT_TERM_85_OHM		(3 << 6)
-#define PS8818_RX_INPUT_TERM_MASK		(3 << 6)
-
-#define PS8818_REG1_DPEQ_LEVEL		0xB6
-#define PS8818_DPEQ_LEVEL_UP_9DB		(0 << 3)
-#define PS8818_DPEQ_LEVEL_UP_10DB		(1 << 3)
-#define PS8818_DPEQ_LEVEL_UP_12DB		(2 << 3)
-#define PS8818_DPEQ_LEVEL_UP_13DB		(3 << 3)
-#define PS8818_DPEQ_LEVEL_UP_16DB		(4 << 3)
-#define PS8818_DPEQ_LEVEL_UP_17DB		(5 << 3)
-#define PS8818_DPEQ_LEVEL_UP_18DB		(6 << 3)
-#define PS8818_DPEQ_LEVEL_UP_19DB		(7 << 3)
-#define PS8818_DPEQ_LEVEL_UP_20DB		(8 << 3)
-#define PS8818_DPEQ_LEVEL_UP_21DB		(9 << 3)
-#define PS8818_DPEQ_LEVEL_UP_MASK		(0x0F << 3)
-
-/*
- * PAGE 2 Register Definitions
- */
-#define PS8818_REG_PAGE2	0x02
-
-#define PS8818_REG2_TX_STATUS		0x42
-#define PS8818_REG2_RX_STATUS		0x46
-#define PS8818_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8818_STATUS_10_GBPS			BIT(5)
-
-extern const struct usb_mux_driver ps8818_usb_retimer_driver;
-
-int ps8818_i2c_read(const struct usb_mux *me,
-		    int page, int offset, int *data);
-int ps8818_i2c_write(const struct usb_mux *me,
-		     int page, int offset, int data);
-int ps8818_i2c_field_update8(const struct usb_mux *me,
-			     int page, int offset,
-			     uint8_t field_mask, uint8_t set_value);
-
-#endif /* __CROS_EC_USB_RETIMER_PS8818_H */
diff --git a/driver/retimer/tdp142.c b/driver/retimer/tdp142.c
deleted file mode 100644
index e1632150d0..0000000000
--- a/driver/retimer/tdp142.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Texas Instruments TDP142 DisplayPort Linear Redriver
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "tdp142.h"
-
-static enum ec_error_list tdp142_write(int offset, int data)
-{
-	return i2c_write8(TDP142_I2C_PORT,
-			  TDP142_I2C_ADDR,
-			  offset, data);
-
-}
-
-static enum ec_error_list tdp142_read(int offset, int *regval)
-{
-	return i2c_read8(TDP142_I2C_PORT,
-			 TDP142_I2C_ADDR,
-			 offset, regval);
-
-}
-
-enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection)
-{
-	int regval;
-	enum ec_error_list rv;
-
-	rv = tdp142_read(TDP142_REG_GENERAL, &regval);
-	if (rv)
-		return rv;
-
-	regval &= ~TDP142_GENERAL_CTLSEL;
-	regval |= selection;
-
-	return tdp142_write(TDP142_REG_GENERAL, regval);
-}
diff --git a/driver/retimer/tdp142.h b/driver/retimer/tdp142.h
deleted file mode 100644
index 8346a233a5..0000000000
--- a/driver/retimer/tdp142.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Texas Instruments TDP142 DisplayPort Linear Redriver
- */
-
-#ifndef __CROS_EC_REDRIVER_TDP142_H
-#define __CROS_EC_REDRIVER_TDP142_H
-
-#include "compile_time_macros.h"
-
-/*
- * Note: Since DP redrivers do not have a standard EC structure, define a
- * TDP142_I2C_PORT and TDP142_I2C_ADDR in board.h
- */
-#define TDP142_I2C_ADDR0 0x44
-#define TDP142_I2C_ADDR1 0x47
-#define TDP142_I2C_ADDR2 0x0C
-#define TDP142_I2C_ADDR3 0x0F
-
-/* Registers */
-#define TDP142_REG_GENERAL		0x0A
-#define TDP142_GENERAL_CTLSEL		GENMASK(1, 0)
-#define TDP142_GENERAL_HPDIN_OVRRIDE	BIT(3)
-#define TDP142_GENERAL_EQ_OVERRIDE	BIT(4)
-#define TDP142_GENERAL_SWAP_HPDIN	BIT(5)
-
-enum tdp142_ctlsel {
-	TDP142_CTLSEL_SHUTDOWN,
-	TDP142_CTLSEL_DISABLED,
-	TDP142_CTLSEL_ENABLED,
-};
-
-/* Control redriver enable */
-enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection);
-
-#endif /* __CROS_EC_REDRIVER_TDP142_H */
diff --git a/driver/retimer/tusb544.c b/driver/retimer/tusb544.c
deleted file mode 100644
index 9de543fd42..0000000000
--- a/driver/retimer/tusb544.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI TUSB544 USB Type-C Multi-Protocol Linear Redriver
- */
-#include "i2c.h"
-#include "tusb544.h"
-#include "usb_mux.h"
-
-static int tusb544_write(const struct usb_mux *me, int offset, int data)
-{
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
-}
-
-static int tusb544_read(const struct usb_mux *me, int offset, int *data)
-{
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, data);
-}
-
-int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
-			     uint8_t field_mask, uint8_t set_value)
-{
-	int rv;
-
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags,
-			       offset,
-			       field_mask,
-			       set_value);
-
-	return rv;
-}
-
-static int tusb544_enter_low_power_mode(const struct usb_mux *me)
-{
-	int reg;
-	int rv;
-
-	rv = tusb544_read(me, TUSB544_REG_GENERAL4, &reg);
-	if (rv)
-		return rv;
-
-	/* Setting CTL_SEL[0,1] to 0 powers down, per Table 5 */
-	reg &= ~TUSB544_GEN4_CTL_SEL;
-	/* Clear HPD */
-	reg &= ~TUSB544_GEN4_HPDIN;
-
-	return tusb544_write(me, TUSB544_REG_GENERAL4, reg);
-}
-
-static int tusb544_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int reg;
-	int rv;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state == USB_PD_MUX_NONE)
-		return tusb544_enter_low_power_mode(me);
-
-	rv = tusb544_read(me, TUSB544_REG_GENERAL4, &reg);
-	if (rv)
-		return rv;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= TUSB544_GEN4_FLIP_SEL;
-	else
-		reg &= ~TUSB544_GEN4_FLIP_SEL;
-
-	reg &= ~TUSB544_GEN4_CTL_SEL;
-
-	if (IS_ENABLED(CONFIG_TUSB544_EQ_BY_REGISTER))
-		reg |= TUSB544_GEN4_EQ_OVRD;
-
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
-	    (mux_state & USB_PD_MUX_DP_ENABLED)) {
-		reg |= TUSB544_CTL_SEL_DP_USB;
-		reg |= TUSB544_GEN4_HPDIN;
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		reg |= TUSB544_CTL_SEL_DP_ONLY;
-		reg |= TUSB544_GEN4_HPDIN;
-	} else if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= TUSB544_CTL_SEL_USB_ONLY;
-
-	rv = tusb544_write(me, TUSB544_REG_GENERAL4, reg);
-	if (rv)
-		return rv;
-
-	rv = tusb544_read(me, TUSB544_REG_GENERAL6, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~TUSB544_GEN6_DIR_SEL;
-	/* All chromebooks are DP SRC */
-	reg |= TUSB544_DIR_SEL_USB_DP_SRC;
-
-	return tusb544_write(me, TUSB544_REG_GENERAL6, reg);
-}
-
-const struct usb_mux_driver tusb544_drv = {
-	.enter_low_power_mode = &tusb544_enter_low_power_mode,
-	.init = &tusb544_init,
-	.set = &tusb544_set_mux,
-};
diff --git a/driver/retimer/tusb544.h b/driver/retimer/tusb544.h
deleted file mode 100644
index e1599c78ca..0000000000
--- a/driver/retimer/tusb544.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TI TUSB544 USB Type-C Multi-Protocol Linear Redriver
- */
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_REDRIVER_TUSB544_H
-#define __CROS_EC_USB_REDRIVER_TUSB544_H
-
-
-#define TUSB544_I2C_ADDR_FLAGS0 0x44
-
-#define TUSB544_REG_GENERAL4	0x0A
-#define TUSB544_GEN4_CTL_SEL		GENMASK(1, 0)
-#define TUSB544_GEN4_FLIP_SEL		BIT(2)
-#define TUSB544_GEN4_HPDIN		BIT(3)
-#define TUSB544_GEN4_EQ_OVRD		BIT(4)
-#define TUSB544_GEN4_SWAP_SEL		BIT(5)
-
-#define TUSB544_REG_DISPLAYPORT_1	0x10
-#define TUSB544_REG_DISPLAYPORT_2	0x11
-#define TUSB544_REG_USB3_1_1	0x20
-#define TUSB544_REG_USB3_1_2	0x21
-#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33		(0)
-#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15		(1)
-#define TUSB544_EQ_RX_DFP_17_UFP_0		(2)
-#define TUSB544_EQ_RX_DFP_32_UFP_14		(3)
-#define TUSB544_EQ_RX_DFP_41_UFP_24		(4)
-#define TUSB544_EQ_RX_DFP_52_UFP_35		(5)
-#define TUSB544_EQ_RX_DFP_61_UFP_43		(6)
-#define TUSB544_EQ_RX_DFP_69_UFP_52		(7)
-#define TUSB544_EQ_RX_DFP_77_UFP_60		(8)
-#define TUSB544_EQ_RX_DFP_83_UFP_66		(9)
-#define TUSB544_EQ_RX_DFP_88_UFP_72		(10)
-#define TUSB544_EQ_RX_DFP_94_UFP_77		(11)
-#define TUSB544_EQ_RX_DFP_98_UFP_81		(12)
-#define TUSB544_EQ_RX_DFP_103_UFP_86		(13)
-#define TUSB544_EQ_RX_DFP_106_UFP_90		(14)
-#define TUSB544_EQ_RX_DFP_110_UFP_94		(15)
-#define TUSB544_EQ_RX_MASK		(0x0F)
-
-#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33		(0 << 4)
-#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15		(1 << 4)
-#define TUSB544_EQ_TX_DFP_17_UFP_0		(2 << 4)
-#define TUSB544_EQ_TX_DFP_32_UFP_14		(3 << 4)
-#define TUSB544_EQ_TX_DFP_41_UFP_24		(4 << 4)
-#define TUSB544_EQ_TX_DFP_52_UFP_35		(5 << 4)
-#define TUSB544_EQ_TX_DFP_61_UFP_43		(6 << 4)
-#define TUSB544_EQ_TX_DFP_69_UFP_52		(7 << 4)
-#define TUSB544_EQ_TX_DFP_77_UFP_60		(8 << 4)
-#define TUSB544_EQ_TX_DFP_83_UFP_66		(9 << 4)
-#define TUSB544_EQ_TX_DFP_88_UFP_72		(10 << 4)
-#define TUSB544_EQ_TX_DFP_94_UFP_77		(11 << 4)
-#define TUSB544_EQ_TX_DFP_98_UFP_81		(12 << 4)
-#define TUSB544_EQ_TX_DFP_103_UFP_86		(13 << 4)
-#define TUSB544_EQ_TX_DFP_106_UFP_90		(14 << 4)
-#define TUSB544_EQ_TX_DFP_110_UFP_94		(15 << 4)
-#define TUSB544_EQ_TX_MASK		(0xF0)
-
-enum tusb544_ct_sel {
-	TUSB544_CTL_SEL_DISABLED,
-	TUSB544_CTL_SEL_USB_ONLY,
-	TUSB544_CTL_SEL_DP_ONLY,
-	TUSB544_CTL_SEL_DP_USB,
-};
-
-#define TUSB544_REG_GENERAL6	0x0C
-#define TUSB544_GEN6_DIR_SEL	GENMASK(1, 0)
-#define TUSB544_VOD_DCGAIN_SEL	GENMASK(5, 2)
-#define TUSB544_VOD_DCGAIN_OVERRIDE  BIT(6)
-
-enum tusb544_dir_sel {
-	TUSB544_DIR_SEL_USB_DP_SRC,
-	TUSB544_DIR_SEL_USB_DP_SNK,
-	TUSB544_DIR_SEL_CUSTOM_SRC,
-	TUSB544_DIS_SEL_CUSTOM_SNK,
-};
-
-enum tusb544_vod_dcgain_sel {
-	TUSB544_VOD_DCGAIN_SETTING_1,
-	TUSB544_VOD_DCGAIN_SETTING_2,
-	TUSB544_VOD_DCGAIN_SETTING_3,
-	TUSB544_VOD_DCGAIN_SETTING_4,
-	TUSB544_VOD_DCGAIN_SETTING_5,
-	TUSB544_VOD_DCGAIN_SETTING_6,
-	TUSB544_VOD_DCGAIN_SETTING_7,
-	TUSB544_VOD_DCGAIN_SETTING_8,
-};
-
-/*
- * Note: TUSB544 automatically snoops DP lanes to enable, but may be manually
- * directed which lanes to turn on when snoop is disabled
- */
-#define TUSB544_REG_DP4			0x13
-#define TUSB544_DP4_DP0_DISABLE		BIT(0)
-#define TUSB544_DP4_DP1_DISABLE		BIT(1)
-#define TUSB544_DP4_DP2_DISABLE		BIT(2)
-#define TUSB544_DP4_DP3_DISABLE		BIT(3)
-#define TUSB544_DP4_AUX_SBU_OVR		GENMASK(5, 4)
-#define TUSB544_DP4_AUX_SNOOP_DISABLE	BIT(7)
-
-extern const struct usb_mux_driver tusb544_drv;
-
-int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
-			     uint8_t field_mask, uint8_t set_value);
-
-#endif
diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c
deleted file mode 100644
index fbcbd990ff..0000000000
--- a/driver/sb_rmi.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AMD SB-RMI (Side-band Remote Management Interface) Driver */
-
-#include "common.h"
-#include "chipset.h"
-#include "i2c.h"
-#include "sb_rmi.h"
-#include "stdbool.h"
-#include "time.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#define SB_RMI_MAILBOX_TIMEOUT_MS 10
-#define SB_RMI_MAILBOX_RETRY_DELAY_US 200
-
-/**
- * Write an SB-RMI register
- */
-static int sb_rmi_write(const int reg, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL_AP, SB_RMI_I2C_ADDR_FLAGS0, reg,
-			  data);
-}
-
-/**
- * Read an SB-RMI register
- */
-static int sb_rmi_read(const int reg, int *data)
-{
-	return i2c_read8(I2C_PORT_THERMAL_AP, SB_RMI_I2C_ADDR_FLAGS0, reg,
-			 data);
-}
-
-/**
- * Set SB-RMI software interrupt
- */
-static int sb_rmi_assert_interrupt(bool assert)
-{
-	return sb_rmi_write(SB_RMI_SW_INTR_REG, assert ? 0x1 : 0x0);
-}
-
-
-/**
- * Execute a SB-RMI mailbox transaction
- *
- * cmd:
- *	See "SB-RMI Soft Mailbox Message" table in PPR for command id
- * msg_in:
- *	Message In buffer
- * msg_out:
- *	Message Out buffer
- */
-int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr)
-{
-       /**
-	* The sequence is as follows:
-	* 1. The initiator (BMC) indicates that command is to be serviced by
-	*    firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F). This
-	*    register must be set to 0x80 after reset.
-	* 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0
-	*    (SBRMI_x38).
-	* 3. For write operations or read operations which require additional
-	*    addressing information as shown in the table above, the initiator
-	*    (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
-	*    {SBRMI_x3C(MSB):SBRMI_x39(LSB)}.
-	* 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to
-	*    notify firmware to perform the requested read or write command.
-	* 5. Firmware reads the message and performs the defined action.
-	* 6. Firmware writes the original command to outbound message register
-	*    SBRMI::OutBndMsg_inst0 (SBRMI_x30).
-	* 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an
-	*    ALERT (if enabled) to initiator (BMC) to indicate completion of the
-	*    requested command. Firmware must (if applicable) put the message
-	*    data into the message registers SBRMI::OutBndMsg_inst[4:1]
-	*    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
-	* 8. For a read operation, the initiator (BMC) reads the firmware
-	*    response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
-	*    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
-	* 9. Firmware clears the interrupt on SBRMI::SoftwareInterrupt.
-	* 10. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
-	*     ALERT to initiator (BMC). It is recommended to clear the ALERT
-	*     upon completion of the current mailbox command.
-	*/
-	int val;
-	bool alerted;
-	timestamp_t start;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	/**
-	 * Step 1: writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F) to
-	 *         indicate that command is to be serviced and to make sure
-	 *         SBRMIx40[Software Interrupt] is cleared
-	 */
-	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG7_REG, 0x80));
-	RETURN_ERROR(sb_rmi_assert_interrupt(0));
-
-	/* Step 2: writes the command to SBRMI::InBndMsg_inst0 (SBRMI_x38) */
-	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG0_REG, cmd));
-	/* Step 3: msgIn to {SBRMI_x3C(MSB):SBRMI_x39(LSB)} */
-	RETURN_ERROR(sb_rmi_write(SB_RMI_IN_BND_MSG1_REG, msg_in & 0xFF));
-	RETURN_ERROR(
-		sb_rmi_write(SB_RMI_IN_BND_MSG2_REG, (msg_in >> 8) & 0xFF));
-	RETURN_ERROR(
-		sb_rmi_write(SB_RMI_IN_BND_MSG3_REG, (msg_in >> 16) & 0xFF));
-	RETURN_ERROR(
-		sb_rmi_write(SB_RMI_IN_BND_MSG4_REG, (msg_in >> 24) & 0xFF));
-
-	/**
-	 * Step 4: writes 0x01 to SBRMIx40[Software Interrupt] to notify
-	 *         firmware to start service.
-	 */
-	RETURN_ERROR(sb_rmi_assert_interrupt(1));
-
-	/**
-	 * Step 5: SoC do the service
-	 * Step 6: The original command will be copied to SBRMI::OutBndMsg_inst0
-	 *         (SBRMI_x30)
-	 * Step 7: wait SBRMIx02[SwAlertSts] to 1 which indicate the completion
-	 *         of a mailbox operation
-	 */
-	alerted = false;
-	start = get_time();
-	do {
-		if (sb_rmi_read(SB_RMI_STATUS_REG, &val))
-			break;
-		if (val & 0x02) {
-			alerted = true;
-			break;
-		}
-		msleep(1);
-	} while (time_since32(start) < SB_RMI_MAILBOX_TIMEOUT_MS * MSEC);
-
-	if (!alerted) {
-		CPRINTS("SB-SMI: Mailbox transfer timeout");
-		/* Clear interrupt */
-		sb_rmi_assert_interrupt(0);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG0_REG, &val));
-	if (val != cmd) {
-		CPRINTS("RMI: Unexpected command value in out bound message");
-		sb_rmi_assert_interrupt(0);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Step 8: read msgOut from {SBRMI_x34(MSB):SBRMI_x31(LSB)} */
-	*msg_out_ptr = 0;
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG1_REG, &val));
-	*msg_out_ptr |= val;
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG2_REG, &val));
-	*msg_out_ptr |= val << 8;
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG3_REG, &val));
-	*msg_out_ptr |= val << 16;
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG4_REG, &val));
-	*msg_out_ptr |= val << 24;
-
-	/* Step 9: clear SBRMIx40[Software Interrupt] */
-	RETURN_ERROR(sb_rmi_assert_interrupt(0));
-
-	/**
-	 * Step 10: BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear
-	 *          the ALERT to initiator (BMC). It is recommended to clear the
-	 *          ALERT upon completion of the current mailbox command.
-	 */
-	RETURN_ERROR(sb_rmi_write(SB_RMI_STATUS_REG, 0x2));
-
-	/* Step 11: read the return code from OutBndMsg_inst7 (SBRMI_x37) */
-	RETURN_ERROR(sb_rmi_read(SB_RMI_OUT_BND_MSG7_REG, &val));
-
-	switch (val) {
-	case SB_RMI_MAILBOX_SUCCESS:
-		return EC_SUCCESS;
-	case SB_RMI_MAILBOX_ERROR_ABORTED:
-		return EC_ERROR_UNKNOWN;
-	case SB_RMI_MAILBOX_ERROR_UNKNOWN_CMD:
-		return EC_ERROR_INVAL;
-	case SB_RMI_MAILBOX_ERROR_INVALID_CORE:
-		return EC_ERROR_PARAM1;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-}
diff --git a/driver/sb_rmi.h b/driver/sb_rmi.h
deleted file mode 100644
index 132af0e70a..0000000000
--- a/driver/sb_rmi.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AMD SB-RMI (Side-band Remote Management Interface) Driver */
-
-#ifndef __CROS_EC_SB_RMI_H
-#define __CROS_EC_SB_RMI_H
-
-#include "common.h"
-
-#define SB_RMI_OUT_BND_MSG0_REG 0x30
-#define SB_RMI_OUT_BND_MSG1_REG 0x31
-#define SB_RMI_OUT_BND_MSG2_REG 0x32
-#define SB_RMI_OUT_BND_MSG3_REG 0x33
-#define SB_RMI_OUT_BND_MSG4_REG 0x34
-#define SB_RMI_OUT_BND_MSG5_REG 0x35
-#define SB_RMI_OUT_BND_MSG6_REG 0x36
-#define SB_RMI_OUT_BND_MSG7_REG 0x37
-
-#define SB_RMI_IN_BND_MSG0_REG 0x38
-#define SB_RMI_IN_BND_MSG1_REG 0x39
-#define SB_RMI_IN_BND_MSG2_REG 0x3a
-#define SB_RMI_IN_BND_MSG3_REG 0x3b
-#define SB_RMI_IN_BND_MSG4_REG 0x3c
-#define SB_RMI_IN_BND_MSG5_REG 0x3d
-#define SB_RMI_IN_BND_MSG6_REG 0x3e
-#define SB_RMI_IN_BND_MSG7_REG 0x3f
-
-#define SB_RMI_SW_INTR_REG 0x40
-#define SB_RMI_STATUS_REG 0x02
-
-#define SB_RMI_WRITE_STT_SENSOR_CMD 0x3A
-
-#define SB_RMI_MAILBOX_SUCCESS 0x0
-#define SB_RMI_MAILBOX_ERROR_ABORTED 0x1
-#define SB_RMI_MAILBOX_ERROR_UNKNOWN_CMD 0x2
-#define SB_RMI_MAILBOX_ERROR_INVALID_CORE 0x3
-
-/* Socket ID 0 */
-#define SB_RMI_I2C_ADDR_FLAGS0 0x3c
-/* Socket ID 1 */
-#define SB_RMI_I2C_ADDR_FLAGS1 0x30
-
-/**
- * Execute a SB-RMI mailbox transaction
- *
- * cmd:
- *	See "SB-RMI Soft Mailbox Message" table in PPR for command id
- * msg_in:
- *	Message In buffer
- * msg_out:
- *	Message Out buffer
- */
-int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr);
-
-#endif /* __CROS_EC_SB_RMI_H */
diff --git a/driver/sensorhub_lsm6dsm.c b/driver/sensorhub_lsm6dsm.c
deleted file mode 100644
index 371d8474f6..0000000000
--- a/driver/sensorhub_lsm6dsm.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Sensor Hub Driver for LSM6DSM acce/gyro module to enable connecting
- * external sensors like magnetometer
- */
-
-#include "console.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/sensorhub_lsm6dsm.h"
-#include "driver/stm_mems_common.h"
-
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-
-static int set_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
-{
-	int tmp;
-	int ret;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, reg, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	tmp |= bit_field;
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, tmp);
-}
-
-static int clear_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
-{
-	int tmp;
-	int ret;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, reg, &tmp);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	tmp &= ~(bit_field);
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, tmp);
-}
-
-static inline int enable_sensorhub_func(const struct motion_sensor_t *s)
-{
-	return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
-}
-
-static inline int disable_sensorhub_func(const struct motion_sensor_t *s)
-{
-	return clear_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
-}
-
-/*
- * Sensor hub includes embedded register banks associated with external
- * sensors. 4 external sensor slaves can be attached to the sensor hub
- * and hence 4 such register banks exist. The access to them are disabled
- * by default. Below 2 helper functions help enable/disable access to those
- * register banks.
- */
-static inline int enable_ereg_bank_acc(const struct motion_sensor_t *s)
-{
-	return set_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
-}
-
-static inline int disable_ereg_bank_acc(const struct motion_sensor_t *s)
-{
-	return clear_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
-}
-
-static inline int enable_aux_i2c_master(const struct motion_sensor_t *s)
-{
-	return set_reg_bit_field(s, LSM6DSM_MASTER_CFG_ADDR,
-							LSM6DSM_I2C_MASTER_ON);
-}
-
-static inline int disable_aux_i2c_master(const struct motion_sensor_t *s)
-{
-	return clear_reg_bit_field(s, LSM6DSM_MASTER_CFG_ADDR,
-							LSM6DSM_I2C_MASTER_ON);
-}
-
-static inline int restore_master_cfg(const struct motion_sensor_t *s,
-								int cache)
-{
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_MASTER_CFG_ADDR, cache);
-}
-
-static int enable_i2c_pass_through(const struct motion_sensor_t *s,
-							int *cache)
-{
-	int ret;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_MASTER_CFG_ADDR, cache);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCR error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	/*
-	 * Fake set sensor hub to external trigger event and wait for 10ms.
-	 * Wait is for any pending bus activity(probably read) to settle down
-	 * so that there is no bus contention.
-	 */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_MASTER_CFG_ADDR,
-			    *cache | LSM6DSM_EXT_TRIGGER_EN);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-	msleep(10);
-
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_MASTER_CFG_ADDR,
-				 *cache & ~(LSM6DSM_EXT_TRIGGER_EN
-					    | LSM6DSM_I2C_MASTER_ON));
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCC error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		restore_master_cfg(s, *cache);
-		return ret;
-	}
-
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			LSM6DSM_MASTER_CFG_ADDR, LSM6DSM_I2C_PASS_THRU_MODE);
-}
-
-static inline int power_down_accel(const struct motion_sensor_t *s,
-						int *cache)
-{
-	int ret;
-
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_CTRL1_ADDR, cache);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR,
-			     *cache & ~LSM6DSM_XL_ODR_MASK);
-}
-
-static inline int restore_ctrl1(const struct motion_sensor_t *s, int cache)
-{
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR, cache);
-}
-
-static int config_slv0_read(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint16_t reg, uint8_t len)
-{
-	int ret;
-	uint16_t addr_8bit = I2C_STRIP_FLAGS(slv_addr_flags) << 1;
-
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_SLV0_ADD_ADDR,
-			    (addr_8bit | LSM6DSM_SLV0_RD_BIT));
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SA error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_SLV0_SUBADD_ADDR, reg);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x RA error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	/*
-	 * No decimation for external sensor 0,
-	 * Number of sensors connected to external sensor hub 1
-	 */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_SLV0_CONFIG_ADDR,
-			    (len & LSM6DSM_SLV0_NUM_OPS_MASK));
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CFG error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
-			     const uint16_t slv_addr_flags,
-			     uint8_t reg, uint8_t val)
-{
-	int ret;
-	int tmp;
-
-	ret = enable_i2c_pass_through(s, &tmp);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	ret = st_raw_write8(s->port, slv_addr_flags, reg, val);
-	restore_master_cfg(s, tmp);
-	return ret;
-}
-
-int sensorhub_config_slv0_read(const struct motion_sensor_t *s,
-			       uint16_t slv_addr_flags, uint8_t reg, int len)
-{
-	int tmp_xl_cfg;
-	int ret;
-
-	if (len <= 0 || len > OUT_XYZ_SIZE) {
-		CPRINTF("%s: %s type:0x%x Invalid length: %d\n",
-			__func__, s->name, s->type, len);
-		return EC_ERROR_INVAL;
-	}
-
-	ret = power_down_accel(s, &tmp_xl_cfg);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	ret = enable_ereg_bank_acc(s);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		goto out_restore_ctrl1;
-	}
-
-	ret = config_slv0_read(s, slv_addr_flags, reg, len);
-	disable_ereg_bank_acc(s);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		goto out_restore_ctrl1;
-	}
-
-	ret = enable_sensorhub_func(s);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		goto out_restore_ctrl1;
-	}
-
-	ret = enable_aux_i2c_master(s);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		disable_sensorhub_func(s);
-	}
-out_restore_ctrl1:
-	restore_ctrl1(s, tmp_xl_cfg);
-	return ret;
-}
-
-int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw)
-{
-	int ret;
-
-	/*
-	 * Accel/Gyro is already reading slave 0 data into the sensorhub1
-	 * register as soon as the accel is in power-up mode. So return the
-	 * contents of that register.
-	 */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LSM6DSM_SENSORHUB1_REG,
-				  raw, OUT_XYZ_SIZE);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-	return EC_SUCCESS;
-}
-
-int sensorhub_check_and_rst(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint8_t whoami_reg, uint8_t whoami_val,
-			    uint8_t rst_reg, uint8_t rst_val)
-{
-	int ret, tmp;
-	int tmp_master_cfg;
-
-	ret = enable_i2c_pass_through(s, &tmp_master_cfg);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		return ret;
-	}
-
-	ret = st_raw_read8(s->port, slv_addr_flags, whoami_reg, &tmp);
-	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		goto err_restore_master_cfg;
-	}
-
-	if (tmp != whoami_val) {
-		CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n",
-			__func__, s->name, s->type, ret);
-		ret = EC_ERROR_UNKNOWN;
-		goto err_restore_master_cfg;
-	}
-
-	ret = st_raw_write8(s->port, slv_addr_flags, rst_reg, rst_val);
-err_restore_master_cfg:
-	restore_master_cfg(s, tmp_master_cfg);
-	return ret;
-}
diff --git a/driver/sync.c b/driver/sync.c
deleted file mode 100644
index c9a2752d63..0000000000
--- a/driver/sync.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Sync event driver.
- * Useful for recording the exact time a gpio interrupt happened in the
- * context of sensors. Originally created for a camera vsync signal.
- */
-
-#include "accelgyro.h"
-#include "config.h"
-#include "console.h"
-#include "driver/sync.h"
-#include "hwtimer.h"
-#include "motion_sense_fifo.h"
-#include "queue.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
-
-#ifndef CONFIG_ACCEL_FIFO
-#error This driver needs CONFIG_ACCEL_FIFO
-#endif
-
-#ifndef CONFIG_ACCEL_INTERRUPTS
-#error This driver needs CONFIG_ACCEL_INTERRUPTS
-#endif
-
-struct sync_event_t {
-	uint32_t timestamp;
-	int counter;
-};
-
-static struct queue const sync_event_queue =
-	QUEUE_NULL(CONFIG_SYNC_QUEUE_SIZE, struct sync_event_t);
-
-struct sync_event_t next_event;
-struct ec_response_motion_sensor_data vector = {
-	.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO,
-	.data = {0, 0, 0}
-};
-
-int sync_enabled;
-
-static int sync_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	v[0] = next_event.counter;
-	return EC_SUCCESS;
-}
-
-/*
- * Since there's no such thing as data rate for this sensor, but the framework
- * still depends on being able to set this to 0 to disable it, we'll just use
- * non 0 rate values as an enable boolean.
- */
-static int sync_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
-{
-	sync_enabled = !!rate;
-	CPRINTF("sync event driver enabling=%d\n", sync_enabled);
-	return EC_SUCCESS;
-}
-
-static int sync_get_data_rate(const struct motion_sensor_t *s)
-{
-	return sync_enabled;
-}
-
-/* Upper half of the irq handler */
-void sync_interrupt(enum gpio_signal signal)
-{
-	next_event.timestamp = __hw_clock_source_read();
-
-	if (!sync_enabled)
-		return;
-
-	next_event.counter++;
-	queue_add_unit(&sync_event_queue, &next_event);
-
-	task_set_event(TASK_ID_MOTIONSENSE, CONFIG_SYNC_INT_EVENT);
-}
-
-/* Bottom half of the irq handler */
-static int motion_irq_handler(struct motion_sensor_t *s, uint32_t *event)
-{
-	struct sync_event_t sync_event;
-
-	if (!(*event & CONFIG_SYNC_INT_EVENT))
-		return EC_ERROR_NOT_HANDLED;
-
-	while (queue_remove_unit(&sync_event_queue, &sync_event)) {
-		vector.data[X] = sync_event.counter;
-		motion_sense_fifo_stage_data(
-			&vector, s, 1, sync_event.timestamp);
-	}
-	motion_sense_fifo_commit_data();
-
-	return EC_SUCCESS;
-}
-
-static int sync_init(struct motion_sensor_t *s)
-{
-	vector.sensor_num = s - motion_sensors;
-	sync_enabled = 0;
-	next_event.counter = 0;
-	queue_init(&sync_event_queue);
-	return 0;
-}
-
-#ifdef CONFIG_SYNC_COMMAND
-static int command_sync(int argc, char **argv)
-{
-	int count = 1, i;
-
-	if (argc > 1)
-		count = strtoi(argv[1], 0, 0);
-
-	for (i = 0; i < count; i++)
-		sync_interrupt(GPIO_SYNC_INT);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sync, command_sync,
-	"[count]",
-	"Simulates sync events");
-#endif
-
-const struct accelgyro_drv sync_drv = {
-	.init = sync_init,
-	.read = sync_read,
-	.set_data_rate = sync_set_data_rate,
-	.get_data_rate = sync_get_data_rate,
-	.irq_handler = motion_irq_handler,
-};
-
diff --git a/driver/sync.h b/driver/sync.h
deleted file mode 100644
index 1f6115a086..0000000000
--- a/driver/sync.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Sync event driver.
- * Useful for recording the exact time a gpio interrupt happened in the
- * context of sensors. Originally created for a camera vsync signal.
- */
-
-#ifndef __CROS_EC_VSYNC_H
-#define __CROS_EC_VSYNC_H
-
-extern const struct accelgyro_drv sync_drv;
-
-void sync_interrupt(enum gpio_signal signal);
-
-#endif	/* __CROS_EC_VSYNC_H */
-
diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c
deleted file mode 100644
index 9a9a3c7971..0000000000
--- a/driver/tcpm/anx7447.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ANX7447 port manager */
-
-#include "common.h"
-#include "anx7447.h"
-#include "console.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define vsafe5v_min (3800/25)
-#define vsafe0v_max (800/25)
-/*
- * These interface are workable while ADC is enabled, before
- * calling them should make sure ec driver finished chip initilization.
- */
-#define is_equal_greater_safe5v(port) \
-		(((anx7447_get_vbus_voltage(port))) > vsafe5v_min)
-#define is_equal_greater_safe0v(port) \
-		(((anx7447_get_vbus_voltage(port))) > vsafe0v_max)
-
-struct anx_state {
-	uint16_t i2c_addr_flags;
-};
-
-struct anx_usb_mux {
-	int state;
-};
-
-static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required);
-
-static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
-static struct anx_usb_mux mux[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * ANX7447 has two co-existence I2C addresses, TCPC address and
- * SPI address. The registers of TCPC address are partly compliant
- * with standard USB TCPC specification, and the registers in SPI
- * address controls the other functions (ex, hpd_level, mux_switch, and
- * so on). It can't use tcpc_read() and tcpc_write() to access SPI
- * address because its address has been set as TCPC in the structure
- * tcpc_config_t.
- * anx7447_reg_write() and anx7447_reg_read() are implemented here to access
- * ANX7447 SPI address.
- */
-const struct anx7447_i2c_addr anx7447_i2c_addrs_flags[] = {
-	{AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS},
-	{AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS},
-	{AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS},
-	{AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS}
-};
-
-static inline int anx7447_reg_write(int port, int reg, int val)
-{
-	int rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			    anx[port].i2c_addr_flags,
-			    reg, val);
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	pd_device_accessed(port);
-#endif
-	return rv;
-}
-
-static inline int anx7447_reg_read(int port, int reg, int *val)
-{
-	int rv = i2c_read8(tcpc_config[port].i2c_info.port,
-			   anx[port].i2c_addr_flags,
-			   reg, val);
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	pd_device_accessed(port);
-#endif
-	return rv;
-}
-
-void anx7447_hpd_mode_init(int port)
-{
-	int reg, rv;
-
-	rv = anx7447_reg_read(port, ANX7447_REG_HPD_CTRL_0, &reg);
-	if (rv)
-		return;
-
-	/*
-	 * Set ANX7447_REG_HPD_MODE bit as 0, then the TCPC will generate the
-	 * HPD pulse from internal timer (by using ANX7447_REG_HPD_IRQ0)
-	 * instead of using the ANX7447_REG_HPD_OUT to set the HPD IRQ signal.
-	 */
-	reg &= ~(ANX7447_REG_HPD_MODE | ANX7447_REG_HPD_PLUG |
-		 ANX7447_REG_HPD_UNPLUG);
-	anx7447_reg_write(port, ANX7447_REG_HPD_CTRL_0, reg);
-}
-
-void anx7447_hpd_output_en(int port)
-{
-	int reg, rv;
-
-	rv = anx7447_reg_read(port, ANX7447_REG_HPD_DEGLITCH_H, &reg);
-	if (rv)
-		return;
-
-	reg |= ANX7447_REG_HPD_OEN;
-	anx7447_reg_write(port, ANX7447_REG_HPD_DEGLITCH_H, reg);
-}
-
-void anx7447_set_hpd_level(int port, int hpd_lvl)
-{
-	int reg, rv;
-
-	rv = anx7447_reg_read(port, ANX7447_REG_HPD_CTRL_0, &reg);
-	if (rv)
-		return;
-
-	/*
-	 * When ANX7447_REG_HPD_MODE is 1, use ANX7447_REG_HPD_OUT
-	 * to generate HPD event, otherwise use ANX7447_REG_HPD_UNPLUG
-	 * and ANX7447_REG_HPD_PLUG.
-	 */
-	if (hpd_lvl) {
-		reg &= ~ANX7447_REG_HPD_UNPLUG;
-		reg |= ANX7447_REG_HPD_PLUG;
-	} else {
-		reg &= ~ANX7447_REG_HPD_PLUG;
-		reg |= ANX7447_REG_HPD_UNPLUG;
-	}
-	anx7447_reg_write(port, ANX7447_REG_HPD_CTRL_0, reg);
-}
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
-static inline void anx7447_reg_write_and(int port, int reg, int v_and)
-{
-	int val;
-
-	if (!anx7447_reg_read(port, reg, &val))
-		anx7447_reg_write(port, reg, (val & v_and));
-}
-
-static inline void anx7447_reg_write_or(int port, int reg, int v_or)
-{
-	int val;
-
-	if (!anx7447_reg_read(port, reg, &val))
-		anx7447_reg_write(port, reg, (val | v_or));
-}
-
-#define ANX7447_FLASH_DONE_TIMEOUT_US	(100 * MSEC)
-
-static int anx7447_wait_for_flash_done(int port)
-{
-	timestamp_t deadline;
-	int rv;
-	int r;
-
-	deadline.val = get_time().val + ANX7447_FLASH_DONE_TIMEOUT_US;
-	do {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-		rv = anx7447_reg_read(port, ANX7447_REG_R_RAM_CTRL, &r);
-		if (rv)
-			return rv;
-	} while (!(r & ANX7447_R_RAM_CTRL_FLASH_DONE));
-
-	return EC_SUCCESS;
-}
-
-static int anx7447_flash_write_en(int port)
-{
-	anx7447_reg_write(port, ANX7447_REG_FLASH_INST_TYPE,
-			  ANX7447_FLASH_INST_TYPE_WRITEENABLE);
-	anx7447_reg_write_or(port, ANX7447_REG_R_FLASH_RW_CTRL,
-			     ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN);
-	return anx7447_wait_for_flash_done(port);
-}
-
-static int anx7447_flash_op_init(int port)
-{
-	int rv;
-
-	anx7447_reg_write_or(port, ANX7447_REG_OCM_CTRL_0,
-			     ANX7447_OCM_CTRL_OCM_RESET);
-	anx7447_reg_write_or(port, ANX7447_REG_ADDR_GPIO_CTRL_0,
-			     ANX7447_ADDR_GPIO_CTRL_0_SPI_WP);
-
-	rv = anx7447_flash_write_en(port);
-	if (rv)
-		return rv;
-
-	anx7447_reg_write_and(port, ANX7447_REG_R_FLASH_STATUS_0,
-			      ANX7447_FLASH_STATUS_SPI_STATUS_0);
-	anx7447_reg_write_or(port, ANX7447_REG_R_FLASH_RW_CTRL,
-			     ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN);
-
-	return anx7447_wait_for_flash_done(port);
-}
-
-static int anx7447_flash_is_empty(int port)
-{
-	int r;
-
-	anx7447_reg_read(port, ANX7447_REG_OCM_VERSION, &r);
-
-	return ((r == 0) ? 1 : 0);
-}
-
-static int anx7447_flash_erase_internal(int port, int write_console_if_empty)
-{
-	int rv;
-	int r;
-
-	tcpc_read(port, TCPC_REG_COMMAND, &r);
-	usleep(ANX7447_DELAY_IN_US);
-
-	if (anx7447_flash_is_empty(port) == 1) {
-		if (write_console_if_empty)
-			CPRINTS("C%d: Nothing to erase!", port);
-		return EC_SUCCESS;
-	}
-	CPRINTS("C%d: Erasing OCM flash...", port);
-
-	rv = anx7447_flash_op_init(port);
-	if (rv)
-		return rv;
-
-	usleep(ANX7447_DELAY_IN_US);
-
-	rv = anx7447_flash_write_en(port);
-	if (rv)
-		return rv;
-
-	anx7447_reg_write(port, ANX7447_REG_FLASH_ERASE_TYPE,
-			  ANX7447_FLASH_ERASE_TYPE_CHIPERASE);
-	anx7447_reg_write_or(port, ANX7447_REG_R_FLASH_RW_CTRL,
-			     ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN);
-
-	return anx7447_wait_for_flash_done(port);
-}
-
-int anx7447_flash_erase(int port)
-{
-	return anx7447_flash_erase_internal(port,
-					    0 /* suppress console if empty */);
-}
-
-/* Add console command to erase OCM flash if needed. */
-static int command_anx_ocm(int argc, char **argv)
-{
-	char *e = NULL;
-	int port;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* Get port number from first parameter */
-	port = strtoi(argv[1], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM1;
-
-	if (argc > 2) {
-		int rv;
-		if (strcasecmp(argv[2], "erase"))
-			return EC_ERROR_PARAM2;
-		rv = anx7447_flash_erase_internal(
-			port, 1 /* write to console if empty */);
-		if (rv)
-			ccprintf("C%d: Failed to erase OCM flash (%d)\n",
-				 port, rv);
-	}
-
-	ccprintf("C%d: OCM flash is %sempty.\n",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm,
-			"port [erase]",
-			"Print OCM status or erases OCM for a given port.");
-#endif
-
-static int anx7447_init(int port)
-{
-	int rv, reg, i;
-	const struct usb_mux *me = &usb_muxes[port];
-	bool unused;
-
-	ASSERT(port < CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	memset(&anx[port], 0, sizeof(struct anx_state));
-
-	/*
-	 * find corresponding anx7447 SPI address according to
-	 * specified TCPC address
-	 */
-	for (i = 0; i < ARRAY_SIZE(anx7447_i2c_addrs_flags); i++) {
-		if (I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags) ==
-		    I2C_STRIP_FLAGS(
-			    anx7447_i2c_addrs_flags[i].tcpc_addr_flags)) {
-			anx[port].i2c_addr_flags =
-				anx7447_i2c_addrs_flags[i].spi_addr_flags;
-			break;
-		}
-	}
-	if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) {
-		ccprintf("TCPC I2C addr 0x%x is invalid for ANX7447\n",
-			 I2C_STRIP_FLAGS(tcpc_config[port]
-				      .i2c_info.addr_flags));
-		return EC_ERROR_UNKNOWN;
-	}
-
-
-	rv = tcpci_tcpm_init(port);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
-	/* Check and print OCM status to console. */
-	CPRINTS("C%d: OCM flash is %sempty",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
-#endif
-
-	/*
-	 * 7447 has a physical pin to detect the presence of VBUS, VBUS_SENSE
-	 * , and 7447 has a VBUS current protection mechanism through another
-	 * pin input VBUS_OCP. To enable VBUS OCP, OVP protection, driver needs
-	 * to set the threshold to the registers VBUS_VOLTAGE_ALARM_HI_CFG
-	 * (0x76 & 0x77) and VBUS_OCP_HI_THRESHOLD (0xDD &0xDE). These values
-	 * could be customized based on different platform design.
-	 * Disable VBUS protection here since the default values of
-	 * VBUS_VOLTAGE_ALARM_HI_CFG and VBUS_OCP_HI_THRESHOLD are zero.
-	 */
-	rv = tcpc_read(port, ANX7447_REG_TCPC_CTRL_2, &reg);
-	if (rv)
-		return rv;
-	reg &= ~ANX7447_REG_ENABLE_VBUS_PROTECT;
-	rv = tcpc_write(port, ANX7447_REG_TCPC_CTRL_2, reg);
-	if (rv)
-		return rv;
-
-	/*
-	 * Specifically disable voltage alarms, as VBUS_VOLTAGE_ALARM_HI may
-	 * trigger repeatedly despite being masked (b/153989733)
-	 */
-	rv = tcpc_update16(port, TCPC_REG_POWER_CTRL,
-			   TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS, MASK_SET);
-	if (rv)
-		return rv;
-
-	/* ADC enable, use to monitor VBUS voltage */
-	rv = tcpc_read(port, ANX7447_REG_ADC_CTRL_1, &reg);
-	if (rv)
-		return rv;
-	reg |= ANX7447_REG_ADCFSM_EN;
-	rv = tcpc_write(port, ANX7447_REG_ADC_CTRL_1, reg);
-	if (rv)
-		return rv;
-
-	/* Set VCONN OCP(Over Current Protection) threshold */
-	rv = tcpc_read(port, ANX7447_REG_ANALOG_CTRL_8, &reg);
-	if (rv)
-		return rv;
-	reg &= ~ANX7447_REG_VCONN_OCP_MASK;
-	reg |= ANX7447_REG_VCONN_OCP_440mA;
-	rv = tcpc_write(port, ANX7447_REG_ANALOG_CTRL_8, reg);
-
-	/* Vconn SW protection time of inrush current */
-	rv = tcpc_read(port, ANX7447_REG_ANALOG_CTRL_10, &reg);
-	if (rv)
-		return rv;
-	reg &= ~ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK;
-	reg |= ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US;
-	rv = tcpc_write(port, ANX7447_REG_ANALOG_CTRL_10, reg);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-	/*
-	 * Run mux_set() here for considering CCD(Case-Closed Debugging) case
-	 * If this TCPC is not also the MUX then don't initialize to NONE
-	 */
-	while ((me != NULL) && (me->driver != &anx7447_usb_mux_driver))
-		me = me->next_mux;
-
-	/*
-	 * Note that bypassing the usb_mux API is okay for internal driver calls
-	 * since the task calling init already holds this port's mux lock.
-	 */
-	if (me != NULL &&
-	    !(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		rv = anx7447_mux_set(me, USB_PD_MUX_NONE, &unused);
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
-	return rv;
-}
-
-static int anx7447_release(int port)
-{
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-static int anx7447_get_vbus_voltage(int port)
-{
-	int vbus_volt = 0;
-
-	tcpc_read16(port, TCPC_REG_VBUS_VOLTAGE, &vbus_volt);
-
-	return vbus_volt;
-}
-
-int anx7447_set_power_supply_ready(int port)
-{
-	int count = 0;
-
-	while (is_equal_greater_safe0v(port)) {
-		if (count >= 10)
-			break;
-		msleep(100);
-		count++;
-	}
-
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x77);
-}
-#endif /* CONFIG_USB_PD_VBUS_DETECT_TCPC */
-
-int anx7447_power_supply_reset(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x66);
-}
-
-int anx7447_board_charging_enable(int port, int enable)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, enable ? 0x55 : 0x44);
-}
-
-static void anx7447_tcpc_alert(int port)
-{
-	/* process and clear alert status */
-	tcpci_tcpc_alert(port);
-}
-
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.
- */
-static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int reg = 0;
-	int port = me->usb_port;
-	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
-	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-
-	/*
-	 * All calls within this method need to update to a mux_read/write calls
-	 * that use the secondary address. This is a non-trival change and no
-	 * one is using the anx7447 as a mux only (and probably never will since
-	 * it doesn't have a re-driver). If that changes, we need to update this
-	 * code.
-	 */
-	ASSERT(!(me->flags & USB_MUX_FLAG_NOT_TCPC));
-
-	anx7447_set_hpd_level(port, hpd_lvl);
-
-	if (hpd_irq) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < hpd_deadline[port])
-			usleep(hpd_deadline[port] - now);
-
-		/*
-		 * For generate hardware HPD IRQ, need clear bit
-		 * ANX7447_REG_HPD_IRQ0 first, then set it. This bit is not
-		 * write clear.
-		 */
-		anx7447_reg_read(port, ANX7447_REG_HPD_CTRL_0, &reg);
-		reg &= ~ANX7447_REG_HPD_IRQ0;
-		anx7447_reg_write(port, ANX7447_REG_HPD_CTRL_0, reg);
-		reg |= ANX7447_REG_HPD_IRQ0;
-		anx7447_reg_write(port, ANX7447_REG_HPD_CTRL_0, reg);
-	}
-	/* enforce 2-ms delay between HPD pulses */
-	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-}
-
-void anx7447_tcpc_clear_hpd_status(int port)
-{
-	anx7447_hpd_output_en(port);
-	anx7447_set_hpd_level(port, 0);
-}
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-static int anx7447_mux_init(const struct usb_mux *me)
-{
-	int port = me->usb_port;
-	bool unused;
-
-	ASSERT(port < CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	memset(&mux[port], 0, sizeof(struct anx_usb_mux));
-
-	/* init hpd status */
-	anx7447_hpd_mode_init(port);
-	anx7447_set_hpd_level(port, 0);
-	anx7447_hpd_output_en(port);
-
-	/*
-	 * ANX initializes its muxes to (USB_PD_MUX_USB_ENABLED |
-	 * USB_PD_MUX_DP_ENABLED) when reinitialized, we need to force
-	 * initialize it to USB_PD_MUX_NONE
-	 */
-	return anx7447_mux_set(me, USB_PD_MUX_NONE, &unused);
-}
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-static void anx7447_mux_safemode(const struct usb_mux *me, int on_off)
-{
-	int reg;
-
-	mux_read(me, ANX7447_REG_ANALOG_CTRL_9, &reg);
-
-	if (on_off)
-		reg |= ANX7447_REG_SAFE_MODE;
-	else
-		reg &= ~(ANX7447_REG_SAFE_MODE);
-
-	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
-	CPRINTS("C%d set mux to safemode %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
-}
-
-static inline void anx7447_configure_aux_src(const struct usb_mux *me,
-					     int on_off)
-{
-	int reg;
-
-	mux_read(me, ANX7447_REG_ANALOG_CTRL_9, &reg);
-
-	if (on_off)
-		reg |= ANX7447_REG_R_AUX_RES_PULL_SRC;
-	else
-		reg &= ~(ANX7447_REG_R_AUX_RES_PULL_SRC);
-
-	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
-
-	CPRINTS("C%d set aux_src to %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
-}
-#endif
-
-/*
- * Set mux.
- *
- * sstx and ssrx are the USB superspeed transmit and receive pairs. ml is the
- * DisplayPort Main Link. There are four lanes total. For example, DP cases
- * connect them all and dock cases connect 2 DP and USB.
- *
- * a2, a3, a10, a11, b2, b3, b10, b11 are pins on the USB-C connector.
- */
-static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int cc_direction;
-	mux_state_t mux_type;
-	int sw_sel = 0x00, aux_sw = 0x00;
-	int rv;
-	int port = me->usb_port;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	cc_direction = mux_state & USB_PD_MUX_POLARITY_INVERTED;
-	mux_type = mux_state & USB_PD_MUX_DOCK;
-	CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x",
-		port, mux_state, mux_type);
-	if (cc_direction == 0) {
-		/* cc1 connection */
-		if (mux_type == USB_PD_MUX_DOCK) {
-			/* ml0-a10/11, ml1-b2/b3, sstx-a2/a3, ssrx-b10/11 */
-			sw_sel = 0x21;
-			/* aux+ <-> sbu1, aux- <-> sbu2 */
-			aux_sw = 0x03;
-		} else if (mux_type == USB_PD_MUX_DP_ENABLED) {
-			/* ml0-a10/11, ml1-b2/b3, ml2-a2/a3, ml3-b10/11 */
-			sw_sel = 0x09;
-			/* aux+ <-> sbu1, aux- <-> sbu2 */
-			aux_sw = 0x03;
-		} else if (mux_type == USB_PD_MUX_USB_ENABLED) {
-			/* ssrxp<->b11, ssrxn<->b10, sstxp<->a2, sstxn<->a3 */
-			sw_sel = 0x20;
-		}
-	} else {
-		/* cc2 connection */
-		if (mux_type == USB_PD_MUX_DOCK) {
-			/* ml0-b10/11, ml1-a2/b3, sstx-b2/a3, ssrx-a10/11 */
-			sw_sel = 0x12;
-			/* aux+ <-> sbu2, aux- <-> sbu1 */
-			aux_sw = 0x0C;
-		} else if (mux_type == USB_PD_MUX_DP_ENABLED) {
-			/* ml0-b10/11, ml1-a2/b3, ml2-b2/a3, ml3-a10/11 */
-			sw_sel = 0x06;
-			/* aux+ <-> sbu2, aux- <-> sbu1 */
-			aux_sw = 0x0C;
-		} else if (mux_type == USB_PD_MUX_USB_ENABLED) {
-			/* ssrxp<->a11, ssrxn<->a10, sstxp<->b2, sstxn<->b3 */
-			sw_sel = 0x10;
-		}
-	}
-
-	/*
-	 * Once need to configure the Mux, should set the mux to safe mode
-	 * first. After the  mux configured, should set mux to normal mode.
-	 */
-#ifdef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-	anx7447_mux_safemode(me, 1);
-#endif
-	rv = mux_write(me, ANX7447_REG_TCPC_SWITCH_0, sw_sel);
-	rv |= mux_write(me, ANX7447_REG_TCPC_SWITCH_1, sw_sel);
-	rv |= mux_write(me, ANX7447_REG_TCPC_AUX_SWITCH, aux_sw);
-
-	mux[port].state = mux_state;
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-	/*
-	 * DP and Dock mode: after configured the Mux, change the Mux to
-	 * normal mode, otherwise: keep safe mode.
-	 */
-	if (mux_type != USB_PD_MUX_NONE) {
-		anx7447_configure_aux_src(me, 1);
-		anx7447_mux_safemode(me, 0);
-	} else
-		anx7447_configure_aux_src(me, 0);
-#endif
-
-	return rv;
-}
-
-/* current mux state */
-static int anx7447_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int port = me->usb_port;
-
-	*mux_state = mux[port].state;
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-static int anx7447_tcpc_drp_toggle(int port)
-{
-	int rv, reg;
-
-	rv = tcpc_read(port, ANX7447_REG_ANALOG_CTRL_10, &reg);
-	if (rv)
-		return rv;
-	/*
-	 * When using Look4Connection command to toggle CC under normal mode
-	 * the CABLE_DET_DIG shall be clear first.
-	 */
-	if (reg & ANX7447_REG_CABLE_DET_DIG) {
-		reg &= ~ANX7447_REG_CABLE_DET_DIG;
-		rv = tcpc_write(port, ANX7447_REG_ANALOG_CTRL_10, reg);
-		if (rv)
-			return rv;
-	}
-
-	return tcpci_tcpc_drp_toggle(port);
-}
-#endif
-
-/* Override for tcpci_tcpm_set_cc */
-static int anx7447_set_cc(int port, int pull)
-{
-	int rp, reg;
-
-	rp = tcpc_read(port, ANX7447_REG_ANALOG_CTRL_10, &reg);
-	if (rp)
-		return rp;
-	/*
-	 * When setting CC status, should be confirm that the CC toggling
-	 * process is stopped, the CABLE_DET_DIG shall be set to one.
-	 */
-	if ((reg & ANX7447_REG_CABLE_DET_DIG) == 0) {
-		reg |= ANX7447_REG_CABLE_DET_DIG;
-		rp = tcpc_write(port, ANX7447_REG_ANALOG_CTRL_10, reg);
-		if (rp)
-			return rp;
-	}
-
-	rp = tcpci_get_cached_rp(port);
-
-	/* Set manual control, and set both CC lines to the same pull */
-	return tcpc_write(port, TCPC_REG_ROLE_CTRL,
-			  TCPC_REG_ROLE_CTRL_SET(0, rp, pull, pull));
-}
-
-/* Override for tcpci_tcpm_set_polarity */
-static int anx7447_set_polarity(int port,
-				enum tcpc_cc_polarity polarity)
-{
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
-}
-
-#ifdef CONFIG_CMD_TCPC_DUMP
-static const struct tcpc_reg_dump_map anx7447_regs[] = {
-	{
-		.addr = ANX7447_REG_TCPC_SWITCH_0,
-		.name = "SWITCH_0",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_TCPC_SWITCH_1,
-		.name = "SWITCH_1",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_TCPC_AUX_SWITCH,
-		.name = "AUX_SWITCH",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_ADC_CTRL_1,
-		.name = "ADC_CTRL_1",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_ANALOG_CTRL_8,
-		.name = "ANALOG_CTRL_8",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_ANALOG_CTRL_10,
-		.name = "ANALOG_CTRL_10",
-		.size = 1,
-	},
-	{
-		.addr = ANX7447_REG_TCPC_CTRL_2,
-		.name = "TCPC_CTRL_2",
-		.size = 1,
-	},
-};
-
-const struct {
-	const char *name;
-	uint8_t addr;
-} anx7447_alt_regs[] = {
-	{
-		.name = "HPD_CTRL_0",
-		.addr = ANX7447_REG_HPD_CTRL_0,
-	},
-	{
-		.name = "HPD_DEGLITCH_H",
-		.addr = ANX7447_REG_HPD_DEGLITCH_H,
-	},
-	{
-		.name = "INTP_SOURCE_0",
-		.addr = ANX7447_REG_INTP_SOURCE_0,
-	},
-	{
-		.name = "INTP_MASK_0",
-		.addr = ANX7447_REG_INTP_MASK_0,
-	},
-	{
-		.name = "INTP_CTRL_0",
-		.addr = ANX7447_REG_INTP_CTRL_0,
-	},
-	{
-		.name = "PAD_INTP_CTRL",
-		.addr = ANX7447_REG_PAD_INTP_CTRL,
-	},
-};
-
-/*
- * Dump registers for debug command.
- */
-static void anx7447_dump_registers(int port)
-{
-	int i, val;
-
-	tcpc_dump_std_registers(port);
-	tcpc_dump_registers(port, anx7447_regs, ARRAY_SIZE(anx7447_regs));
-	for (i = 0; i < ARRAY_SIZE(anx7447_alt_regs); i++) {
-		anx7447_reg_read(port, anx7447_alt_regs[i].addr, &val);
-		ccprintf("  %-26s(ALT/0x%02x) =   0x%02x\n",
-				anx7447_alt_regs[i].name,
-				anx7447_alt_regs[i].addr, (uint8_t)val);
-		cflush();
-	}
-}
-#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
-
-/*
- * ANX7447 is a TCPCI compatible port controller, with some caveats.
- * It seems to require both CC lines to be set always, instead of just
- * one at a time, according to TCPCI spec.  Thus, now that the TCPCI
- * driver more closely follows the spec, this driver requires
- * overrides for set_cc and set_polarity.
- */
-const struct tcpm_drv anx7447_tcpm_drv = {
-	.init			= &anx7447_init,
-	.release		= &anx7447_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &anx7447_set_cc,
-	.set_polarity		= &anx7447_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7447_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= anx7447_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-#ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &anx7447_dump_registers,
-#endif
-};
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-const struct usb_mux_driver anx7447_usb_mux_driver = {
-	.init = anx7447_mux_init,
-	.set = anx7447_mux_set,
-	.get = anx7447_mux_get,
-};
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h
deleted file mode 100644
index 75982e6b91..0000000000
--- a/driver/tcpm/anx7447.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "usb_mux.h"
-
-/* USB Power delivery port management */
-
-#ifndef __CROS_EC_USB_PD_TCPM_ANX7447_H
-#define __CROS_EC_USB_PD_TCPM_ANX7447_H
-
-/* Registers: TCPC address used */
-#define ANX7447_REG_TCPC_SWITCH_0	0xB4
-#define ANX7447_REG_TCPC_SWITCH_1	0xB5
-#define ANX7447_REG_TCPC_AUX_SWITCH	0xB6
-
-#define ANX7447_REG_INTR_ALERT_MASK_0	0xC9
-
-#define ANX7447_REG_TCPC_CTRL_2		0xCD
-#define ANX7447_REG_ENABLE_VBUS_PROTECT	0x20
-
-#define ANX7447_REG_ADC_CTRL_1		0xBF
-#define ANX7447_REG_ADCFSM_EN		0x20
-
-/* Registers: SPI address used */
-#define ANX7447_REG_INTP_SOURCE_0	0x67
-
-#define ANX7447_REG_HPD_CTRL_0		0x7E
-#define ANX7447_REG_HPD_MODE		0x01
-#define ANX7447_REG_HPD_OUT		0x02
-#define ANX7447_REG_HPD_IRQ0		0x04
-#define ANX7447_REG_HPD_PLUG		0x08
-#define ANX7447_REG_HPD_UNPLUG		0x10
-
-#define ANX7447_REG_HPD_DEGLITCH_H	0x80
-#define ANX7447_REG_HPD_DETECT		0x80
-#define ANX7447_REG_HPD_OEN		0x40
-
-#define ANX7447_REG_PAD_INTP_CTRL	0x85
-
-#define ANX7447_REG_INTP_MASK_0		0x86
-
-#define ANX7447_REG_INTP_CTRL_0		0x9E
-
-#define ANX7447_REG_ANALOG_CTRL_8	0xA8
-#define ANX7447_REG_VCONN_OCP_MASK	0x0C
-#define ANX7447_REG_VCONN_OCP_240mA	0x00
-#define ANX7447_REG_VCONN_OCP_310mA	0x04
-#define ANX7447_REG_VCONN_OCP_370mA	0x08
-#define ANX7447_REG_VCONN_OCP_440mA	0x0C
-
-#define ANX7447_REG_ANALOG_CTRL_10	0xAA
-#define ANX7447_REG_CABLE_DET_DIG	0x40
-
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK	0x38
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US	0x00
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US	0x08
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US    0x10
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US   0x18
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US   0x20
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US	0x28
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US	0x30
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US	0x38
-
-#define ANX7447_REG_ANALOG_CTRL_9	0xA9
-#define ANX7447_REG_SAFE_MODE		0x80
-#define ANX7447_REG_R_AUX_RES_PULL_SRC	0x20
-
-/*
- * This section of defines are only required to support the config option
- * CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND.
- */
-/* SPI registers used for OCM flash operations */
-#define ANX7447_DELAY_IN_US		(20*1000)
-
-#define ANX7447_REG_R_RAM_CTRL			0x05
-#define ANX7447_REG_R_FLASH_RW_CTRL		0x30
-#define ANX7447_REG_R_FLASH_STATUS_0		0x31
-#define ANX7447_REG_FLASH_INST_TYPE		0x33
-#define ANX7447_REG_FLASH_ERASE_TYPE		0x34
-#define ANX7447_REG_OCM_CTRL_0			0x6E
-#define ANX7447_REG_ADDR_GPIO_CTRL_0		0x88
-#define ANX7447_REG_OCM_VERSION			0xB4
-
-/* R_RAM_CTRL bit definitions */
-#define ANX7447_R_RAM_CTRL_FLASH_DONE			(1<<7)
-
-/* R_FLASH_RW_CTRL bit definitions */
-#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN		(1<<6)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN		(1<<5)
-#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN		(1<<2)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ		(1<<1)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE		(1<<0)
-
-/* R_FLASH_STATUS_0 definitions */
-#define ANX7447_FLASH_STATUS_SPI_STATUS_0		0x43
-
-/* FLASH_ERASE_TYPE bit definitions */
-#define ANX7447_FLASH_INST_TYPE_WRITEENABLE		0x06
-#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE		0x60
-
-/* OCM_CTRL_0 bit definitions */
-#define ANX7447_OCM_CTRL_OCM_RESET			(1<<6)
-
-/* ADDR_GPIO_CTRL_0 bit definitions */
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP			(1<<7)
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE		(1<<6)
-/* End of defines used for CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND */
-
-struct anx7447_i2c_addr {
-	uint16_t	tcpc_addr_flags;
-	uint16_t	spi_addr_flags;
-};
-
-#define AN7447_TCPC0_I2C_ADDR_FLAGS	0x2C
-#define AN7447_TCPC1_I2C_ADDR_FLAGS	0x2B
-#define AN7447_TCPC2_I2C_ADDR_FLAGS	0x2A
-#define AN7447_TCPC3_I2C_ADDR_FLAGS	0x29
-
-#define AN7447_SPI0_I2C_ADDR_FLAGS	0x3F
-#define AN7447_SPI1_I2C_ADDR_FLAGS	0x37
-#define AN7447_SPI2_I2C_ADDR_FLAGS	0x32
-#define AN7447_SPI3_I2C_ADDR_FLAGS	0x31
-
-/*
- * Time TEST_R must be held high for a reset
- */
-#define ANX74XX_RESET_HOLD_MS	1
-/*
- * Time after TEST_R reset to wait for eFuse loading
- */
-#define ANX74XX_RESET_FINISH_MS	2
-
-int anx7447_set_power_supply_ready(int port);
-int anx7447_power_supply_reset(int port);
-int anx7447_board_charging_enable(int port, int enable);
-
-void anx7447_hpd_mode_en(int port);
-void anx7447_hpd_output_en(int port);
-
-extern const struct tcpm_drv anx7447_tcpm_drv;
-extern const struct usb_mux_driver anx7447_usb_mux_driver;
-void anx7447_tcpc_clear_hpd_status(int port);
-void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state);
-
-/**
- * Erase OCM flash if it's not empty
- *
- * @param port: USB-C port number
- * @return: EC_SUCCESS or EC_ERROR_*
- */
-int anx7447_flash_erase(int port);
-
-#endif /* __CROS_EC_USB_PD_TCPM_ANX7688_H */
diff --git a/driver/tcpm/anx74xx.c b/driver/tcpm/anx74xx.c
deleted file mode 100644
index 567005920e..0000000000
--- a/driver/tcpm/anx74xx.c
+++ /dev/null
@@ -1,1210 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Author : Analogix Semiconductor.
- */
-
-/* Type-C port manager for Analogix's anx74xx chips */
-
-#include "console.h"
-#include "anx74xx.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#if !defined(CONFIG_USB_PD_TCPM_TCPCI)
-#error "ANX74xx is using part of standard TCPCI control"
-#error "Please upgrade your board configuration"
-#endif
-
-#if defined(CONFIG_USB_PD_REV30)
-#error "ANX74xx chips were developed before PD 3.0 and aren't PD 3.0 compliant"
-#error "Please undefine PD 3.0.  See b/159253723 for details"
-#endif
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-struct anx_state {
-	int	polarity;
-	int	vconn_en;
-	int	mux_state;
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	int	prev_mode;
-#endif
-};
-#define clear_recvd_msg_int(port) do {\
-		int reg, rv; \
-		rv = tcpc_read(port, ANX74XX_REG_RECVD_MSG_INT, &reg); \
-		if (!rv) \
-			tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, \
-			reg | 0x01); \
-	} while (0)
-
-static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-/* Save the message address */
-static int msg_sop[CONFIG_USB_PD_PORT_MAX_COUNT];
-#endif
-
-static int anx74xx_tcpm_init(int port);
-
-static void anx74xx_tcpm_set_auto_good_crc(int port, int enable)
-{
-	int reply_sop_en = 0;
-
-	if (enable) {
-		reply_sop_en = ANX74XX_REG_REPLY_SOP_EN;
-#ifdef CONFIG_USB_PD_DECODE_SOP
-		/*
-		 * Only the VCONN Source is allowed to communicate
-		 * with the Cable Plugs.
-		 */
-		if (anx[port].vconn_en) {
-			reply_sop_en |= ANX74XX_REG_REPLY_SOP_1_EN |
-					ANX74XX_REG_REPLY_SOP_2_EN;
-		}
-#endif
-	}
-
-	tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_2, reply_sop_en);
-}
-
-static void anx74xx_update_cable_det(int port, int mode)
-{
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	int reg;
-
-	if (anx[port].prev_mode == mode)
-		return;
-
-	/* Update power mode */
-	anx[port].prev_mode = mode;
-
-	/* Get ANALOG_CTRL_0 for cable det bit */
-	if (tcpc_read(port, ANX74XX_REG_ANALOG_CTRL_0, &reg))
-		return;
-
-	if (mode == ANX74XX_STANDBY_MODE) {
-		int cc_reg;
-
-		/*
-		 * The ANX4329 enters standby mode by setting PWR_EN signal
-		 * low. In addition, RESET_L must be set low to keep the ANX3429
-		 * in standby mode.
-		 *
-		 * Clearing bit 7 of ANX74XX_REG_ANALOG_CTRL_0 will cause the
-		 * ANX3429 to clear the cable_det signal that goes from the
-		 * ANX3429 to the EC. If this bit is cleared when a cable is
-		 * attached then cable_det will go high once standby is entered.
-		 *
-		 * In some cases, such as when the chipset power state is
-		 * S3/S5/G3 and a sink only adapter is connected to the port,
-		 * this behavior is undesirable. The constant toggling between
-		 * standby and normal mode means that effectively the ANX3429 is
-		 * not in standby mode only consumes ~1 mW less than just
-		 * remaining in normal mode. However when an E mark cable is
-		 * connected, clearing bit 7 is required so that while the E
-		 * mark cable configuration happens, the USB PD state machine
-		 * will continue to wake up until the USB PD attach event can be
-		 * regtistered.
-		 *
-		 * Therefore, the decision to clear bit 7 is based on the
-		 * current CC status of the port. If the CC status is open for
-		 * both CC lines OR if either CC line is showing Ra, then clear
-		 * bit 7. Not clearing bit 7 has no impact for normal cables and
-		 * prevents the constant toggle of standby<->normal when an
-		 * adapter is connected that isn't allowed to attach. Clearing
-		 * bit 7 when CC status reads Ra for either CC line allows the
-		 * USB PD state machine to be woken until the attach event can
-		 * happen. Note that in the case an E mark cable is connected
-		 * and can't attach (i.e. sink only port <- Emark cable -> sink
-		 * only adapter), then the ANX3429 will toggle indefinitely,
-		 * until either the cable is removed, or the port drp status
-		 * changes so the attach event can occur.
-		 * .
-		 */
-
-		/* Read CC status to see if cable_det bit should be cleared */
-		if (tcpc_read(port, ANX74XX_REG_CC_STATUS, &cc_reg))
-			return;
-		/* If open or either CC line is Ra, then clear cable_det */
-		if (!cc_reg || (cc_reg & ANX74XX_CC_RA_MASK &&
-				!(cc_reg & ANX74XX_CC_RD_MASK)))
-			reg &= ~ANX74XX_REG_R_PIN_CABLE_DET;
-	} else {
-		reg |= ANX74XX_REG_R_PIN_CABLE_DET;
-	}
-
-	tcpc_write(port, ANX74XX_REG_ANALOG_CTRL_0, reg);
-#endif
-}
-
-static void anx74xx_set_power_mode(int port, int mode)
-{
-	/*
-	 * Update PWR_EN and RESET_N signals to the correct level. High for
-	 * Normal mode and low for Standby mode. When transitioning from standby
-	 * to normal mode, must set the PWR_EN and RESET_N before attempting to
-	 * modify cable_det bit of analog_ctrl_0. If going from Normal to
-	 * Standby, updating analog_ctrl_0 must happen before setting PWR_EN and
-	 * RESET_N low.
-	 */
-	if (mode == ANX74XX_NORMAL_MODE) {
-		/* Take chip out of standby mode */
-		board_set_tcpc_power_mode(port, mode);
-		/* Update the cable det signal */
-		anx74xx_update_cable_det(port, mode);
-	} else {
-		/* Update cable cable det signal */
-		anx74xx_update_cable_det(port, mode);
-		/*
-		 * Delay between setting cable_det low and setting RESET_L low
-		 * as recommended the ANX3429 datasheet.
-		 */
-		msleep(1);
-		/* Put chip into standby mode */
-		board_set_tcpc_power_mode(port, mode);
-	}
-}
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-
-static int anx74xx_tcpc_drp_toggle(int port)
-{
-	/*
-	 * The ANX3429 always auto-toggles when in low power mode. Since this is
-	 * not configurable, there is nothing to do here. DRP auto-toggle will
-	 * happen once low power mode is set via anx74xx_enter_low_power_mode().
-	 * Note: this means the ANX3429 auto-toggles in PD_DRP_FORCE_SINK mode,
-	 * which is undesirable (b/72007056).
-	 */
-	return EC_SUCCESS;
-}
-
-static int anx74xx_enter_low_power_mode(int port)
-{
-	anx74xx_set_power_mode(port, ANX74XX_STANDBY_MODE);
-	return EC_SUCCESS;
-}
-
-#endif
-
-void anx74xx_tcpc_set_vbus(int port, int enable)
-{
-	int reg;
-
-	tcpc_read(port, ANX74XX_REG_GPIO_CTRL_4_5, &reg);
-	if (enable)
-		reg |= ANX74XX_REG_SET_VBUS;
-	else
-		reg &= ~ANX74XX_REG_SET_VBUS;
-	tcpc_write(port, ANX74XX_REG_GPIO_CTRL_4_5, reg);
-}
-
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-static void anx74xx_tcpc_discharge_vbus(int port, int enable)
-{
-	int reg;
-
-	tcpc_read(port, ANX74XX_REG_HPD_CTRL_0, &reg);
-	if (enable)
-		reg |= ANX74XX_REG_DISCHARGE_CTRL;
-	else
-		reg &= ~ANX74XX_REG_DISCHARGE_CTRL;
-	tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, reg);
-}
-#endif
-
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.
- */
-static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state)
-{
-	int reg;
-	int port = me->usb_port;
-	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
-	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-
-	mux_read(me, ANX74XX_REG_HPD_CTRL_0, &reg);
-	if (hpd_lvl)
-		reg |= ANX74XX_REG_HPD_OUT_DATA;
-	else
-		reg &= ~ANX74XX_REG_HPD_OUT_DATA;
-	mux_write(me, ANX74XX_REG_HPD_CTRL_0, reg);
-
-	if (hpd_irq) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < hpd_deadline[port])
-			usleep(hpd_deadline[port] - now);
-
-		mux_read(me, ANX74XX_REG_HPD_CTRL_0, &reg);
-		reg &= ~ANX74XX_REG_HPD_OUT_DATA;
-		mux_write(me, ANX74XX_REG_HPD_CTRL_0, reg);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		reg |= ANX74XX_REG_HPD_OUT_DATA;
-		mux_write(me, ANX74XX_REG_HPD_CTRL_0, reg);
-	}
-	/* enforce 2-ms delay between HPD pulses */
-	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-}
-
-void anx74xx_tcpc_clear_hpd_status(int port)
-{
-	int reg;
-
-	tcpc_read(port, ANX74XX_REG_HPD_CTRL_0, &reg);
-	reg &= 0xcf;
-	tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, reg);
-}
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-static int anx74xx_tcpm_mux_init(const struct usb_mux *me)
-{
-	/* Nothing to do here, ANX initializes its muxes
-	 * as (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
-	 */
-	anx[me->usb_port].mux_state = USB_PD_MUX_USB_ENABLED |
-				      USB_PD_MUX_DP_ENABLED;
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_tcpm_mux_enter_safe_mode(int port)
-{
-	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
-
-	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
-		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg |
-		       ANX74XX_REG_MODE_TRANS))
-		return EC_ERROR_UNKNOWN;
-
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_tcpm_mux_exit_safe_mode(int port)
-{
-	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
-
-	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
-		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg &
-		       ~ANX74XX_REG_MODE_TRANS))
-		return EC_ERROR_UNKNOWN;
-
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_tcpm_mux_exit(int port)
-{
-	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
-
-	/*
-	 * Safe mode must be entered before any changes are made to the mux
-	 * settings used to enable ALT_DP mode. This function is called either
-	 * from anx74xx_tcpm_mux_set when USB_PD_MUX_NONE is selected as the
-	 * new mux state, or when both cc lines are determined to be
-	 * TYPEC_CC_VOLT_OPEN. Therefore, safe mode must be entered and exited
-	 * here so that both entry paths are handled.
-	 */
-	if (anx74xx_tcpm_mux_enter_safe_mode(port))
-		return EC_ERROR_UNKNOWN;
-
-	/* Disconnect aux from sbu */
-	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
-		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg & 0xf))
-		return EC_ERROR_UNKNOWN;
-
-	/* Clear Bit[7:0] R_SWITCH */
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_1, 0x0))
-		return EC_ERROR_UNKNOWN;
-	/* Clear Bit[7:4] R_SWITCH_H */
-	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_5, &reg))
-		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_5, reg & 0x0f))
-		return EC_ERROR_UNKNOWN;
-
-	/* Exit safe mode */
-	if (anx74xx_tcpm_mux_exit_safe_mode(port))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-
-static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled)
-{
-	int reg;
-	const int aux_mask = ANX74XX_REG_AUX_SWAP_SET_CC2 |
-		ANX74XX_REG_AUX_SWAP_SET_CC1;
-	const struct usb_mux *me = &usb_muxes[port];
-
-	/*
-	 * Get the current value of analog_ctrl_2 register. Note, that safe mode
-	 * is enabled and exited by the calling function, so only have to worry
-	 * about setting the correct value for the upper 4 bits of analog_ctrl_2
-	 * here.
-	 */
-	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
-		return EC_ERROR_UNKNOWN;
-
-	/* Assume aux_p/n lines are not connected */
-	reg &= ~aux_mask;
-
-	if (enabled) {
-		/* If enabled, connect aux to sbu based on desired  polarity */
-		if (polarity)
-			reg |= ANX74XX_REG_AUX_SWAP_SET_CC2;
-		else
-			reg |= ANX74XX_REG_AUX_SWAP_SET_CC1;
-	}
-	/* Write new aux <-> sbu settings */
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg))
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state,
-				bool *ack_required)
-{
-	int ctrl5;
-	int ctrl1 = 0;
-	int rv;
-	int port = me->usb_port;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (!(mux_state & ~USB_PD_MUX_POLARITY_INVERTED)) {
-		anx[port].mux_state = mux_state;
-		return anx74xx_tcpm_mux_exit(port);
-	}
-
-	rv = mux_read(me, ANX74XX_REG_ANALOG_CTRL_5, &ctrl5);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	ctrl5 &= 0x0f;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-		/* Connect USB SS switches */
-		if (mux_state & USB_PD_MUX_POLARITY_INVERTED) {
-			ctrl1 = ANX74XX_REG_MUX_SSRX_RX2;
-			ctrl5 |= ANX74XX_REG_MUX_SSTX_TX2;
-		} else {
-			ctrl1 = ANX74XX_REG_MUX_SSRX_RX1;
-			ctrl5 |= ANX74XX_REG_MUX_SSTX_TX1;
-		}
-		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			/* Set pin assignment D */
-			if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				ctrl1 |= (ANX74XX_REG_MUX_ML0_RX1 |
-					  ANX74XX_REG_MUX_ML1_TX1);
-			else
-				ctrl1 |= (ANX74XX_REG_MUX_ML0_RX2 |
-					  ANX74XX_REG_MUX_ML1_TX2);
-		}
-		/* Keep ML0/ML1 unconnected if DP is not enabled */
-	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		/* Set pin assignment C */
-		if (mux_state & USB_PD_MUX_POLARITY_INVERTED) {
-			ctrl1 = (ANX74XX_REG_MUX_ML0_RX1 |
-				 ANX74XX_REG_MUX_ML1_TX1 |
-				 ANX74XX_REG_MUX_ML3_RX2);
-			ctrl5 |= ANX74XX_REG_MUX_ML2_TX2;
-		} else {
-			ctrl1 = (ANX74XX_REG_MUX_ML0_RX2 |
-				 ANX74XX_REG_MUX_ML1_TX2 |
-				 ANX74XX_REG_MUX_ML3_RX1);
-			ctrl5 |= ANX74XX_REG_MUX_ML2_TX1;
-		}
-	} else if (!mux_state) {
-		return anx74xx_tcpm_mux_exit(port);
-	} else {
-		return  EC_ERROR_UNIMPLEMENTED;
-	}
-
-	/*
-	 * Safe mode must be entererd prior to any changes to the mux related to
-	 * ALT_DP mode. Therefore, first enable safe mode prior to updating the
-	 * values for analog_ctrl_1, analog_ctrl_5, and analog_ctrl_2.
-	 */
-	if (anx74xx_tcpm_mux_enter_safe_mode(port))
-		return EC_ERROR_UNKNOWN;
-
-	/* Write updated pin assignment */
-	rv = mux_write(me, ANX74XX_REG_ANALOG_CTRL_1, ctrl1);
-	/* Write Rswitch config bits */
-	rv |= mux_write(me, ANX74XX_REG_ANALOG_CTRL_5, ctrl5);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* Configure DP aux to sbu settings */
-	if (anx74xx_mux_aux_to_sbu(port,
-				   mux_state & USB_PD_MUX_POLARITY_INVERTED,
-				   mux_state & USB_PD_MUX_DP_ENABLED))
-		return EC_ERROR_UNKNOWN;
-
-	/* Exit safe mode */
-	if (anx74xx_tcpm_mux_exit_safe_mode(port))
-		return EC_ERROR_UNKNOWN;
-
-	anx[port].mux_state = mux_state;
-
-	return EC_SUCCESS;
-}
-
-/* current mux state  */
-static int anx74xx_tcpm_mux_get(const struct usb_mux *me,
-				mux_state_t *mux_state)
-{
-	*mux_state = anx[me->usb_port].mux_state;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver = {
-	.init = &anx74xx_tcpm_mux_init,
-	.set = &anx74xx_tcpm_mux_set,
-	.get = &anx74xx_tcpm_mux_get,
-};
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
-static int anx74xx_init_analog(int port)
-{
-	int reg, rv = EC_SUCCESS;
-
-	/* Analog settings for chip */
-	rv |= tcpc_write(port, ANX74XX_REG_HPD_CONTROL,
-			 ANX74XX_REG_HPD_OP_MODE);
-	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0,
-			 ANX74XX_REG_HPD_DEFAULT);
-	if (rv)
-		return rv;
-	rv = tcpc_read(port, ANX74XX_REG_GPIO_CTRL_4_5, &reg);
-	if (rv)
-		return rv;
-	reg &= ANX74XX_REG_VBUS_GPIO_MODE;
-	reg |= ANX74XX_REG_VBUS_OP_ENABLE;
-	rv = tcpc_write(port, ANX74XX_REG_GPIO_CTRL_4_5, reg);
-	if (rv)
-		return rv;
-	rv = tcpc_read(port, ANX74XX_REG_CC_SOFTWARE_CTRL, &reg);
-	if (rv)
-		return rv;
-	reg |= ANX74XX_REG_TX_MODE_ENABLE;
-	rv = tcpc_write(port, ANX74XX_REG_CC_SOFTWARE_CTRL, reg);
-
-	return rv;
-}
-
-static int anx74xx_send_message(int port, uint16_t header,
-				const uint32_t *payload,
-				int type,
-				uint8_t len)
-{
-	int reg, rv = EC_SUCCESS;
-	uint8_t *buf = NULL;
-	int num_retry = 0, i = 0;
-	/* If sending Soft_reset, clear received message */
-	/* Soft Reset Message type = 1101 and Number of Data Object = 0 */
-	if ((header & 0x700f) == 0x000d) {
-		/*
-		* When sending soft reset,
-		* the Rx buffer of ANX3429 shall be clear
-		*/
-		rv = tcpc_read(port, ANX74XX_REG_CTRL_FW, &reg);
-		rv |= tcpc_write(
-			port, ANX74XX_REG_CTRL_FW, reg | CLEAR_RX_BUFFER);
-		if (rv)
-			return EC_ERROR_UNKNOWN;
-		tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, 0xFF);
-	}
-	/* Inform chip about message length and TX type
-	 * type->bit-0..2, len->bit-3..7
-	 */
-	reg = (len << 3) & 0xf8;
-	reg |= type & 0x07;
-	rv |= tcpc_write(port, ANX74XX_REG_TX_CTRL_2, reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* Enqueue Header */
-	rv = tcpc_write(port, ANX74XX_REG_TX_HEADER_L, (header & 0xff));
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	rv = tcpc_write(port, ANX74XX_REG_TX_HEADER_H, (header >> 8));
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	/* Enqueue payload */
-	if (len > 2) {
-		len -= 2;
-		buf = (uint8_t *)payload;
-		while (1) {
-			if (i < 18)
-				rv = tcpc_write(port,
-						ANX74XX_REG_TX_START_ADDR_0 + i,
-						*buf);
-			else
-				rv = tcpc_write(port,
-					ANX74XX_REG_TX_START_ADDR_1 + i - 18,
-						*buf);
-			if (rv) {
-				num_retry++;
-			} else {
-				buf++;
-				len--;
-				num_retry = 0;
-				i++;
-			}
-			if (len == 0 || num_retry >= 3)
-				break;
-		}
-		/* If enqueue failed, do not request anx to transmit
-		 * messages, FIFO will get cleared in next call
-		 * before enqueue.
-		 * num_retry = 0, refer to success
-		 */
-		if (num_retry)
-			return EC_ERROR_UNKNOWN;
-	}
-	/* Request a data transmission
-	 * This bit will be cleared by ANX after TX success
-	 */
-	rv = tcpc_read(port, ANX74XX_REG_CTRL_COMMAND, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	reg |= ANX74XX_REG_TX_SEND_DATA_REQ;
-	rv |= tcpc_write(port, ANX74XX_REG_CTRL_COMMAND, reg);
-
-	return rv;
-}
-
-static int anx74xx_read_pd_obj(int port,
-				uint8_t *buf,
-				int plen)
-{
-	int rv = EC_SUCCESS, i;
-	int reg, addr = ANX74XX_REG_PD_RX_DATA_OBJ;
-
-	/* Read PD data objects from ANX */
-	for (i = 0; i < plen ; i++) {
-		/* Register sequence changes for last two bytes, if
-		 * plen is greater than 26
-		 */
-		if (i == 26)
-			addr = ANX74XX_REG_PD_RX_DATA_OBJ_M;
-		rv = tcpc_read(port, addr + i, &reg);
-		if (rv)
-			break;
-		buf[i] = reg;
-	}
-	clear_recvd_msg_int(port);
-	return rv;
-}
-
-static int anx74xx_check_cc_type(int cc_reg)
-{
-	int cc;
-
-	switch (cc_reg & ANX74XX_REG_CC_STATUS_MASK) {
-	case BIT_VALUE_OF_SRC_CC_RD:
-		cc = TYPEC_CC_VOLT_RD;
-		break;
-
-	case BIT_VALUE_OF_SRC_CC_RA:
-		cc = TYPEC_CC_VOLT_RA;
-		break;
-
-	case BIT_VALUE_OF_SNK_CC_DEFAULT:
-		cc = TYPEC_CC_VOLT_RP_DEF;
-		break;
-
-	case BIT_VALUE_OF_SNK_CC_1_P_5:
-		cc = TYPEC_CC_VOLT_RP_1_5;
-		break;
-
-	case BIT_VALUE_OF_SNK_CC_3_P_0:
-		cc = TYPEC_CC_VOLT_RP_3_0;
-		break;
-
-	default:
-		/* If no bits are set, then nothing is attached */
-		cc = TYPEC_CC_VOLT_OPEN;
-	}
-
-	return cc;
-}
-
-static int anx74xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int rv = EC_SUCCESS;
-	int reg = 0;
-
-	/* Read tcpc cc status register */
-	rv |= tcpc_read(port, ANX74XX_REG_CC_STATUS, &reg);
-	/* Check for cc1 type */
-	*cc1 = anx74xx_check_cc_type(reg);
-	/*
-	 * Check for cc2 type (note cc2 bits are upper 4 of cc status
-	 * register.
-	 */
-	*cc2 = anx74xx_check_cc_type(reg >> 4);
-
-	/* clear HPD status*/
-	if (!(*cc1) && !(*cc2)) {
-		anx74xx_tcpc_clear_hpd_status(port);
-#ifdef CONFIG_USB_PD_TCPM_MUX
-		anx74xx_tcpm_mux_exit(port);
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_rp_control(int port, int rp)
-{
-	int reg;
-	int rv;
-
-	rv = tcpc_read(port, ANX74XX_REG_ANALOG_CTRL_6, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* clear Bit[0,1] R_RP to default Rp's value */
-	reg &= ~0x03;
-
-	switch (rp) {
-	case TYPEC_RP_1A5:
-		/* Set Rp strength to 12K for presenting 1.5A */
-		reg |= ANX74XX_REG_CC_PULL_RP_12K;
-		break;
-	case TYPEC_RP_3A0:
-		/* Set Rp strength to 4K for presenting 3A */
-		reg |= ANX74XX_REG_CC_PULL_RP_4K;
-		break;
-	case TYPEC_RP_USB:
-	default:
-		/* default: Set Rp strength to 36K */
-		break;
-	}
-
-	return tcpc_write(port, ANX74XX_REG_ANALOG_CTRL_6, reg);
-}
-
-static int anx74xx_tcpm_select_rp_value(int port, int rp)
-{
-	/* Keep track of current RP value */
-	tcpci_set_cached_rp(port, rp);
-
-	/* For ANX3429 cannot get cc correctly when Rp != USB_Default */
-	return EC_SUCCESS;
-}
-
-
-static int anx74xx_cc_software_ctrl(int port, int enable)
-{
-	int rv;
-	int reg;
-
-	rv = tcpc_read(port, ANX74XX_REG_CC_SOFTWARE_CTRL, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	if (enable)
-		reg |= ANX74XX_REG_CC_SW_CTRL_ENABLE;
-	else
-		reg &= ~ANX74XX_REG_CC_SW_CTRL_ENABLE;
-
-	rv |= tcpc_write(port, ANX74XX_REG_CC_SOFTWARE_CTRL, reg);
-	return rv;
-}
-
-static int anx74xx_tcpm_set_cc(int port, int pull)
-{
-	int rv = EC_SUCCESS;
-	int reg;
-
-	/* Enable CC software Control */
-	rv = anx74xx_cc_software_ctrl(port, 1);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	switch (pull) {
-	case TYPEC_CC_RP:
-	/* Enable Rp */
-		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
-		if (rv)
-			return EC_ERROR_UNKNOWN;
-		reg |= ANX74XX_REG_CC_PULL_RP;
-		rv |= tcpc_write(port, ANX74XX_REG_ANALOG_STATUS, reg);
-		break;
-	case TYPEC_CC_RD:
-	/* Enable Rd */
-		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
-		if (rv)
-			return EC_ERROR_UNKNOWN;
-		reg &= ANX74XX_REG_CC_PULL_RD;
-		rv |= tcpc_write(port, ANX74XX_REG_ANALOG_STATUS, reg);
-		break;
-	default:
-		rv = EC_ERROR_UNKNOWN;
-		break;
-	}
-
-	return rv;
-}
-
-static int anx74xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	int reg, mux_state, rv = EC_SUCCESS;
-	const struct usb_mux *me = &usb_muxes[port];
-	bool unused;
-
-	rv |= tcpc_read(port, ANX74XX_REG_CC_SOFTWARE_CTRL, &reg);
-	if (polarity_rm_dts(polarity)) /* Inform ANX to use CC2 */
-		reg &= ~ANX74XX_REG_SELECT_CC1;
-	else /* Inform ANX to use CC1 */
-		reg |= ANX74XX_REG_SELECT_CC1;
-	rv |= tcpc_write(port, ANX74XX_REG_CC_SOFTWARE_CTRL, reg);
-
-	anx[port].polarity = polarity;
-
-	/* Update mux polarity */
-#ifdef CONFIG_USB_PD_TCPM_MUX
-	mux_state = anx[port].mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
-	if (polarity_rm_dts(polarity))
-		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-	anx74xx_tcpm_mux_set(me, mux_state, &unused);
-#endif
-	return rv;
-}
-
-static int anx74xx_tcpm_set_vconn(int port, int enable)
-{
-	int reg, rv = EC_SUCCESS;
-
-	/* switch VCONN to Non CC line */
-	rv |= tcpc_read(port, ANX74XX_REG_INTP_VCONN_CTRL, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	if (enable) {
-		if (anx[port].polarity)
-			reg |= ANX74XX_REG_VCONN_1_ENABLE;
-		else
-			reg |= ANX74XX_REG_VCONN_2_ENABLE;
-	} else {
-		reg &= ANX74XX_REG_VCONN_DISABLE;
-	}
-	rv |= tcpc_write(port, ANX74XX_REG_INTP_VCONN_CTRL, reg);
-	anx[port].vconn_en = enable;
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	rv |= tcpc_read(port, ANX74XX_REG_TX_AUTO_GOODCRC_2, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	if (reg & ANX74XX_REG_REPLY_SOP_EN) {
-		if (enable) {
-			reg |= ANX74XX_REG_REPLY_SOP_1_EN |
-				ANX74XX_REG_REPLY_SOP_2_EN;
-		} else {
-			reg &= ~(ANX74XX_REG_REPLY_SOP_1_EN |
-				 ANX74XX_REG_REPLY_SOP_2_EN);
-		}
-
-		tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_2, reg);
-	}
-#endif
-	return rv;
-}
-
-static int anx74xx_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_1,
-		  ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role, !!power_role));
-}
-
-static int anx74xx_tcpm_set_rx_enable(int port, int enable)
-{
-	int reg, rv;
-
-	rv = tcpc_read(port, ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK, &reg);
-	if (rv)
-		return rv;
-	if (enable) {
-		reg &= ~(ANX74XX_REG_IRQ_CC_MSG_INT);
-		anx74xx_tcpm_set_auto_good_crc(port, 1);
-		anx74xx_rp_control(port, tcpci_get_cached_rp(port));
-	} else {
-		/* Disable RX message by masking interrupt */
-		reg |= (ANX74XX_REG_IRQ_CC_MSG_INT);
-		anx74xx_tcpm_set_auto_good_crc(port, 0);
-		anx74xx_rp_control(port, TYPEC_RP_USB);
-	}
-	/*When this function was call, the interrupt status shall be cleared*/
-	tcpc_write(port, ANX74XX_REG_IRQ_SOURCE_RECV_MSG, 0);
-
-	return tcpc_write(port, ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK, reg);
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-static bool anx74xx_tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	int reg = 0;
-
-	tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
-	if (level == VBUS_PRESENT)
-		return ((reg & ANX74XX_REG_VBUS_STATUS) ? 1 : 0);
-	else
-		return ((reg & ANX74XX_REG_VBUS_STATUS) ? 0 : 1);
-}
-#endif
-
-static int anx74xx_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	int reg;
-	int len;
-
-	/* Fetch the header */
-	if (tcpc_read16(port, ANX74XX_REG_PD_HEADER, &reg)) {
-		clear_recvd_msg_int(port);
-		return EC_ERROR_UNKNOWN;
-	}
-	*head = reg;
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	*head |= PD_HEADER_SOP(msg_sop[port]);
-#endif
-
-	len = PD_HEADER_CNT(*head) * 4;
-	if (!len) {
-		clear_recvd_msg_int(port);
-		return EC_SUCCESS;
-	}
-
-	/* Receive message : assuming payload have enough
-	 * memory allocated
-	 */
-	return anx74xx_read_pd_obj(port, (uint8_t *)payload, len);
-}
-
-static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type,
-		  uint16_t header,
-		  const uint32_t *data)
-{
-	uint8_t len = 0;
-	int ret = 0, reg = 0;
-
-	switch (type) {
-	/* ANX is aware of type */
-	case TCPCI_MSG_SOP:
-	case TCPCI_MSG_SOP_PRIME:
-	case TCPCI_MSG_SOP_PRIME_PRIME:
-		len = PD_HEADER_CNT(header) * 4 + 2;
-		ret = anx74xx_send_message(port, header,
-						  data, type, len);
-		break;
-	case TCPCI_MSG_TX_HARD_RESET:
-	/* Request HARD RESET */
-		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
-		reg |= ANX74XX_REG_TX_HARD_RESET_REQ;
-		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
-	/*After Hard Reset, TCPM shall disable goodCRC*/
-		anx74xx_tcpm_set_auto_good_crc(port, 0);
-		break;
-	case TCPCI_MSG_CABLE_RESET:
-	/* Request CABLE RESET */
-		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
-		reg |= ANX74XX_REG_TX_CABLE_RESET_REQ;
-		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
-		break;
-	case TCPCI_MSG_TX_BIST_MODE_2:
-	/* Request BIST MODE 2 */
-		reg = ANX74XX_REG_TX_BIST_START
-				| ANX74XX_REG_TX_BIXT_FOREVER | (0x02 << 4);
-		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, reg);
-		msleep(1);
-		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_ENABLE);
-		msleep(30);
-		tcpc_read(port, ANX74XX_REG_TX_BIST_CTRL, &reg);
-		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_STOP);
-		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg & (~ANX74XX_REG_TX_BIST_STOP));
-		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, 0);
-		break;
-	default:
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return ret;
-}
-
-/*
- * Don't let the TCPC try to pull from the RX buffer forever. We typical only
- * have 1 or 2 messages waiting.
- */
-#define MAX_ALLOW_FAILED_RX_READS 10
-
-void anx74xx_tcpc_alert(int port)
-{
-	int reg;
-	int failed_attempts;
-
-	/* Clear soft irq bit */
-	tcpc_write(port, ANX74XX_REG_IRQ_EXT_SOURCE_3,
-		   ANX74XX_REG_CLEAR_SOFT_IRQ);
-
-	/* Read main alert register for pending alerts */
-	reg = 0;
-	tcpc_read(port, ANX74XX_REG_IRQ_SOURCE_RECV_MSG, &reg);
-
-	/* Prioritize TX completion because PD state machine is waiting */
-	if (reg & ANX74XX_REG_IRQ_GOOD_CRC_INT)
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
-
-	if (reg & ANX74XX_REG_IRQ_TX_FAIL_INT)
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_FAILED);
-
-	/* Pull all RX messages from TCPC into EC memory */
-	failed_attempts = 0;
-	while (reg & ANX74XX_REG_IRQ_CC_MSG_INT) {
-		if (tcpm_enqueue_message(port))
-			++failed_attempts;
-		if (tcpc_read(port, ANX74XX_REG_IRQ_SOURCE_RECV_MSG, &reg))
-			++failed_attempts;
-
-		/* Ensure we don't loop endlessly */
-		if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) {
-			CPRINTF("C%d Cannot consume RX buffer after %d failed "
-				"attempts!", port, failed_attempts);
-			/*
-			 * The port is in a bad state, we don't want to consume
-			 * all EC resources so suspend the port for a little
-			 * while.
-			 */
-			pd_set_suspend(port, 1);
-			pd_deferred_resume(port);
-			return;
-		}
-	}
-
-	/* Clear all pending alerts */
-	tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, reg);
-
-	if (reg & ANX74XX_REG_IRQ_CC_STATUS_INT)
-		/* CC status changed, wake task */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-
-	/* Read and clear extended alert register 1 */
-	reg = 0;
-	tcpc_read(port, ANX74XX_REG_IRQ_EXT_SOURCE_1, &reg);
-	tcpc_write(port, ANX74XX_REG_IRQ_EXT_SOURCE_1, reg);
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	if (reg & ANX74XX_REG_EXT_SOP)
-		msg_sop[port] = TCPCI_MSG_SOP;
-	else if (reg & ANX74XX_REG_EXT_SOP_PRIME)
-		msg_sop[port] = TCPCI_MSG_SOP_PRIME;
-#endif
-
-	/* Check for Hard Reset done bit */
-	if (reg & ANX74XX_REG_ALERT_TX_HARD_RESETOK)
-		/* ANX hardware clears the request bit */
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
-
-	/* Read and clear TCPC extended alert register 2 */
-	reg = 0;
-	tcpc_read(port, ANX74XX_REG_IRQ_EXT_SOURCE_2, &reg);
-	tcpc_write(port, ANX74XX_REG_IRQ_EXT_SOURCE_2, reg);
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	if (reg & ANX74XX_REG_EXT_SOP_PRIME_PRIME)
-		msg_sop[port] = TCPCI_MSG_SOP_PRIME_PRIME;
-#endif
-
-	if (reg & ANX74XX_REG_EXT_HARD_RST) {
-		/* hard reset received */
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_RX_HARD_RESET);
-	}
-}
-
-static int anx74xx_tcpm_init(int port)
-{
-	int rv = 0, reg;
-
-	memset(&anx[port], 0, sizeof(struct anx_state));
-	/* Bring chip in normal mode to work */
-	anx74xx_set_power_mode(port, ANX74XX_NORMAL_MODE);
-
-	/* Initialize analog section of ANX */
-	rv |= anx74xx_init_analog(port);
-
-	/* disable all interrupts */
-	rv |= tcpc_write(port, ANX74XX_REG_IRQ_EXT_MASK_1,
-			 ANX74XX_REG_CLEAR_SET_BITS);
-
-	/* Initialize interrupt open-drain */
-	rv |= tcpc_read(port, ANX74XX_REG_INTP_VCONN_CTRL, &reg);
-	if (tcpc_config[port].flags & TCPC_FLAGS_ALERT_OD)
-		reg |= ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN;
-	else
-		reg &= ~ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN;
-	rv |= tcpc_write(port, ANX74XX_REG_INTP_VCONN_CTRL, reg);
-
-	/* Initialize interrupt polarity */
-	reg = tcpc_config[port].flags & TCPC_FLAGS_ALERT_ACTIVE_HIGH ?
-		ANX74XX_REG_IRQ_POL_HIGH : ANX74XX_REG_IRQ_POL_LOW;
-	rv |= tcpc_write(port, ANX74XX_REG_IRQ_STATUS, reg);
-
-	/* unmask interrupts */
-	rv |= tcpc_read(port, ANX74XX_REG_IRQ_EXT_MASK_1, &reg);
-	reg &= (~ANX74XX_REG_ALERT_TX_MSG_ERROR);
-	reg &= (~ANX74XX_REG_ALERT_TX_CABLE_RESETOK);
-	reg &= (~ANX74XX_REG_ALERT_TX_HARD_RESETOK);
-	rv |= tcpc_write(port, ANX74XX_REG_IRQ_EXT_MASK_1, reg);
-
-	rv |= tcpc_read(port, ANX74XX_REG_IRQ_EXT_MASK_2, &reg);
-	reg &= (~ANX74XX_REG_EXT_HARD_RST);
-	rv |= tcpc_write(port, ANX74XX_REG_IRQ_EXT_MASK_2, reg);
-
-	/*  HPD pin output enable*/
-	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, ANX74XX_REG_HPD_DEFAULT);
-
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* Set AVDD10_BMC to 1.08 */
-	rv |= tcpc_read(port, ANX74XX_REG_ANALOG_CTRL_5, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	rv = tcpc_write(port, ANX74XX_REG_ANALOG_CTRL_5, (reg & 0xf3));
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* Decrease BMC TX lowest swing voltage */
-	rv |= tcpc_read(port, ANX74XX_REG_ANALOG_CTRL_11, &reg);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-	rv = tcpc_write(port, ANX74XX_REG_ANALOG_CTRL_11, (reg & 0x3f) | 0x40);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	/* Set BMC TX cap slew rate to 400ns */
-	rv = tcpc_write(port, ANX74XX_REG_ANALOG_CTRL_12, 0x4);
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	tcpm_get_chip_info(port, 1, NULL);
-
-	return EC_SUCCESS;
-}
-
-static int anx74xx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	int rv = tcpci_get_chip_info(port, live, chip_info);
-	int val;
-
-	if (rv)
-		return rv;
-
-	if (chip_info->fw_version_number == 0 ||
-	    chip_info->fw_version_number == -1 || live) {
-		rv = tcpc_read(port, ANX74XX_REG_FW_VERSION, &val);
-
-		if (rv)
-			return rv;
-
-		chip_info->fw_version_number = val;
-	}
-
-#ifdef CONFIG_USB_PD_TCPM_ANX3429
-	/*
-	 * Min firmware version of ANX3429 to ensure that false SOP' detection
-	 * doesn't occur for e-marked cables. See b/116255749#comment8 and
-	 * b/64752060#comment11
-	 */
-	chip_info->min_req_fw_version_number = 0x16;
-#endif
-
-	return rv;
-}
-
-/*
- * Dissociate from the TCPC.
- */
-
-static int anx74xx_tcpm_release(int port)
-{
-	return EC_SUCCESS;
-}
-
-const struct tcpm_drv anx74xx_tcpm_drv = {
-	.init			= &anx74xx_tcpm_init,
-	.release		= &anx74xx_tcpm_release,
-	.get_cc			= &anx74xx_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx74xx_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &anx74xx_tcpm_select_rp_value,
-	.set_cc			= &anx74xx_tcpm_set_cc,
-	.set_polarity		= &anx74xx_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &anx74xx_tcpm_set_vconn,
-	.set_msg_header		= &anx74xx_tcpm_set_msg_header,
-	.set_rx_enable		= &anx74xx_tcpm_set_rx_enable,
-	.get_message_raw	= &anx74xx_tcpm_get_message_raw,
-	.transmit		= &anx74xx_tcpm_transmit,
-	.tcpc_alert		= &anx74xx_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &anx74xx_tcpc_discharge_vbus,
-#endif
-	.get_chip_info		= &anx74xx_get_chip_info,
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-		defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-	.drp_toggle		= &anx74xx_tcpc_drp_toggle,
-	.enter_low_power_mode	= &anx74xx_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-struct i2c_stress_test_dev anx74xx_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = ANX74XX_REG_VENDOR_ID_L,
-		.read_val = ANX74XX_VENDOR_ID & 0xFF,
-		.write_reg = ANX74XX_REG_CC_SOFTWARE_CTRL,
-	},
-	.i2c_read = &tcpc_i2c_read,
-	.i2c_write = &tcpc_i2c_write,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_TCPC */
diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h
deleted file mode 100644
index 8d700d4d86..0000000000
--- a/driver/tcpm/anx74xx.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Author : Analogix Semiconductor.
- */
-
-#include "usb_mux.h"
-
-/* USB Power delivery port management */
-
-#ifndef __CROS_EC_USB_PD_TCPM_ANX74XX_H
-#define __CROS_EC_USB_PD_TCPM_ANX74XX_H
-
-/* I2C interface */
-#define ANX74XX_I2C_ADDR1_FLAGS 0x28
-#define ANX74XX_I2C_ADDR2_FLAGS 0x39
-#define ANX74XX_I2C_ADDR3_FLAGS 0x3E
-#define ANX74XX_I2C_ADDR4_FLAGS 0x40
-
-#define ANX74XX_REG_IRQ_POL_LOW		0x00
-#define ANX74XX_REG_IRQ_POL_HIGH		0x02
-
-#define ANX74XX_REG_VENDOR_ID_L         0x00
-#define ANX74XX_REG_VENDOR_ID_H         0x01
-#define ANX74XX_VENDOR_ID               0xAAAA
-
-/* ANX F/W version：0x50:0x44 which contains otp firmware version */
-#define ANX74XX_REG_FW_VERSION          0x44
-
-#define ANX74XX_REG_IRQ_STATUS		0x53
-
-#define ANX74XX_REG_INTP_VCONN_CTRL	0x33
-#define ANX74XX_REG_VCONN_DISABLE		0x0f
-#define ANX74XX_REG_VCONN_1_ENABLE		BIT(4)
-#define ANX74XX_REG_VCONN_2_ENABLE		BIT(5)
-#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN	BIT(2)
-
-#define ANX74XX_STANDBY_MODE		(0)
-#define ANX74XX_NORMAL_MODE		(1)
-
-#define ANX74XX_REG_TX_CTRL_1		0x81
-#define ANX74XX_REG_TX_HARD_RESET_REQ	BIT(1)
-#define ANX74XX_REG_TX_CABLE_RESET_REQ	BIT(2)
-
-#define ANX74XX_REG_TX_CTRL_2		0x82
-#define ANX74XX_REG_TX_WR_FIFO		0x83
-#define ANX74XX_REG_TX_FIFO_CTRL		0x9a
-#define ANX74XX_REG_TX_HEADER_L		0x2c
-#define ANX74XX_REG_TX_HEADER_H		0x2d
-#define ANX74XX_REG_TX_START_ADDR_0		0x6d
-#define ANX74XX_REG_TX_START_ADDR_1		0xd0
-
-#define ANX74XX_REG_CTRL_COMMAND		0xdb
-#define ANX74XX_REG_TX_SEND_DATA_REQ	BIT(0)
-#define ANX74XX_REG_TX_HARD_RST_REQ	BIT(1)
-
-#define ANX74XX_REG_TX_BIST_CTRL 0x9D
-#define ANX74XX_REG_TX_BIST_MODE BIT(4)
-#define ANX74XX_REG_TX_BIST_STOP BIT(3)
-#define ANX74XX_REG_TX_BIXT_FOREVER BIT(2)
-#define ANX74XX_REG_TX_BIST_ENABLE BIT(1)
-#define ANX74XX_REG_TX_BIST_START BIT(0)
-
-#define ANX74XX_REG_PD_HEADER		0x69
-#define ANX74XX_REG_PD_RX_DATA_OBJ		0x11
-#define ANX74XX_REG_PD_RX_DATA_OBJ_M	0x4d
-
-#define ANX74XX_REG_ANALOG_STATUS		0x40
-#define ANX74XX_REG_VBUS_STATUS		BIT(4)
-#define ANX74XX_REG_CC_PULL_RD		0xfd
-#define ANX74XX_REG_CC_PULL_RP		0x02
-
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_2	0x94
-#define ANX74XX_REG_REPLY_SOP_EN        BIT(3)
-#define ANX74XX_REG_REPLY_SOP_1_EN      BIT(4)
-#define ANX74XX_REG_REPLY_SOP_2_EN      BIT(5)
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_1	0x9c
-#define ANX74XX_REG_SPEC_REV_BIT_POS	(3)
-#define ANX74XX_REG_DATA_ROLE_BIT_POS	(2)
-#define ANX74XX_REG_PWR_ROLE_BIT_POS	(1)
-#define ANX74XX_REG_AUTO_GOODCRC_EN	BIT(0)
-#define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole)    \
-	((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \
-	((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS)  | \
-	((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS)   | \
-	ANX74XX_REG_AUTO_GOODCRC_EN)
-
-
-#define ANX74XX_REG_ANALOG_CTRL_0		0x41
-#define ANX74XX_REG_R_PIN_CABLE_DET		BIT(7)
-
-#define ANX74XX_REG_ANALOG_CTRL_1		0x42
-#define ANX74XX_REG_ANALOG_CTRL_5		0x46
-#define ANX74XX_REG_ANALOG_CTRL_6		0x47
-#define ANX74XX_REG_CC_PULL_RP_36K	0x00
-#define ANX74XX_REG_CC_PULL_RP_12K	0x01
-#define ANX74XX_REG_CC_PULL_RP_4K	0x02
-
-#define ANX74XX_REG_R_SWITCH_CC_CLR	0x0f
-#define ANX74XX_REG_R_SWITCH_CC2_SET	0x10
-#define ANX74XX_REG_R_SWITCH_CC1_SET	0x20
-#define ANX74XX_REG_AUX_SWAP_SET_CC1	0x30
-#define ANX74XX_REG_AUX_SWAP_SET_CC2	0xc0
-
-#define ANX74XX_REG_ANALOG_CTRL_11		0x4c
-#define ANX74XX_REG_ANALOG_CTRL_12		0x4d
-
-#define ANX74XX_REG_MUX_ML0_RX2		BIT(0)
-#define ANX74XX_REG_MUX_ML0_RX1		BIT(1)
-#define ANX74XX_REG_MUX_ML3_RX2		BIT(2)
-#define ANX74XX_REG_MUX_ML3_RX1		BIT(3)
-#define ANX74XX_REG_MUX_SSRX_RX2	BIT(4)
-#define ANX74XX_REG_MUX_SSRX_RX1	BIT(5)
-#define ANX74XX_REG_MUX_ML1_TX2		BIT(6)
-#define ANX74XX_REG_MUX_ML1_TX1		BIT(7)
-
-#define ANX74XX_REG_MUX_ML2_TX2		BIT(4)
-#define ANX74XX_REG_MUX_ML2_TX1		BIT(5)
-#define ANX74XX_REG_MUX_SSTX_TX2	BIT(6)
-#define ANX74XX_REG_MUX_SSTX_TX1	BIT(7)
-
-#define ANX74XX_REG_CC_SOFTWARE_CTRL	0x4a
-#define ANX74XX_REG_CC_SW_CTRL_ENABLE	0x01
-#define ANX74XX_REG_TX_MODE_ENABLE		0x04
-
-#define ANX74XX_REG_SELECT_CC1		0x02
-
-#define ANX74XX_REG_GPIO_CTRL_4_5		0x3f
-#define ANX74XX_REG_VBUS_OP_ENABLE		0x04
-#define ANX74XX_REG_VBUS_GPIO_MODE		0xfe
-
-#define ANX74XX_REG_IRQ_EXT_MASK_1		0x3b
-#define ANX74XX_REG_IRQ_EXT_MASK_2		0x3c
-#define ANX74XX_REG_IRQ_EXT_SOURCE_1	0x3e
-#define ANX74XX_REG_EXT_SOP                     BIT(6)
-#define ANX74XX_REG_EXT_SOP_PRIME               BIT(7)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_2	0x4e
-#define ANX74XX_REG_EXT_SOP_PRIME_PRIME         BIT(0)
-#define ANX74XX_REG_EXT_HARD_RST		BIT(2)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_3	0x4f
-#define ANX74XX_REG_CLEAR_SOFT_IRQ		BIT(2)
-
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG	0x6b
-#define ANX74XX_REG_IRQ_CC_MSG_INT		BIT(0)
-#define ANX74XX_REG_IRQ_CC_STATUS_INT	BIT(1)
-#define ANX74XX_REG_IRQ_GOOD_CRC_INT	BIT(2)
-#define ANX74XX_REG_IRQ_TX_FAIL_INT	BIT(3)
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK	0x6c
-
-#define ANX74XX_REG_CLEAR_SET_BITS		0xff
-#define ANX74XX_REG_ALERT_HARD_RST_RECV		BIT(6)
-#define ANX74XX_REG_ALERT_MSG_RECV		BIT(5)
-#define ANX74XX_REG_ALERT_TX_MSG_ERROR	BIT(4)
-#define ANX74XX_REG_ALERT_TX_ACK_RECV	BIT(3)
-#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK	BIT(2)
-#define ANX74XX_REG_ALERT_TX_HARD_RESETOK	BIT(1)
-#define ANX74XX_REG_ALERT_CC_CHANGE	BIT(0)
-
-#define ANX74XX_REG_ANALOG_CTRL_2		0x43
-#define ANX74XX_REG_MODE_TRANS		0x01
-
-#define ANX74XX_REG_SET_VBUS		0x20
-
-#define ANX74XX_REG_ANALOG_CTRL_7		0x48
-#define ANX74XX_REG_STATUS_CC_RD		0x01
-#define ANX74XX_REG_STATUS_CC_RA		0x03
-#define ANX74XX_REG_STATUS_CC1(reg)	((reg & 0x0C) >> 2)
-#define ANX74XX_REG_STATUS_CC2(reg)	((reg & 0x03) >> 0)
-
-#define ANX74XX_REG_HPD_CONTROL		0xfd
-
-#define ANX74XX_REG_HPD_CTRL_0		0x36
-#define ANX74XX_REG_DISCHARGE_CTRL     0x80
-#define ANX74XX_REG_HPD_OP_MODE		0x08
-#define ANX74XX_REG_HPD_DEFAULT		0x00
-#define ANX74XX_REG_HPD_OUT_DATA		0x10
-
-#define ANX74XX_REG_RECVD_MSG_INT 0x98
-#define ANX74XX_REG_CC_STATUS     0x99
-#define ANX74XX_REG_CTRL_FW  0x2E
-#define CLEAR_RX_BUFFER (1)
-#define ANX74XX_REG_POWER_DOWN_CTRL	0x0d
-#define ANX74XX_REG_STATUS_CC1_VRD_USB	BIT(7)
-#define ANX74XX_REG_STATUS_CC1_VRD_1P5	BIT(6)
-#define ANX74XX_REG_STATUS_CC1_VRD_3P0	BIT(5)
-#define ANX74XX_REG_STATUS_CC2_VRD_USB	BIT(4)
-#define ANX74XX_REG_STATUS_CC2_VRD_1P5	BIT(3)
-#define ANX74XX_REG_STATUS_CC2_VRD_3P0	BIT(2)
-
-/* defined in the inter-bock Spec: 4.2.10 CC Detect Status */
-#define ANX74XX_REG_CC_STATUS_MASK  0xf
-#define BIT_VALUE_OF_SRC_CC_RD      0x01
-#define BIT_VALUE_OF_SRC_CC_RA      0x02
-#define BIT_VALUE_OF_SNK_CC_DEFAULT 0x04
-#define BIT_VALUE_OF_SNK_CC_1_P_5   0x08
-#define BIT_VALUE_OF_SNK_CC_3_P_0   0x0C
-#define ANX74XX_CC_RA_MASK (BIT_VALUE_OF_SRC_CC_RA | \
-			    (BIT_VALUE_OF_SRC_CC_RA << 4))
-#define ANX74XX_CC_RD_MASK (BIT_VALUE_OF_SRC_CC_RD | \
-			    (BIT_VALUE_OF_SRC_CC_RD << 4))
-
-/*
- * RESETN low to PWR_EN low delay
- */
-#define ANX74XX_RST_L_PWR_L_DELAY_MS	1
-/*
- * minimum power off-to-on delay to reset chip
- */
-#define ANX74XX_PWR_L_PWR_H_DELAY_MS	10
-/*
- * parameter T4: PWR_EN high to RESETN high delay
- */
-#define ANX74XX_PWR_H_RST_H_DELAY_MS	10
-
-extern const struct tcpm_drv anx74xx_tcpm_drv;
-extern const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver;
-void anx74xx_tcpc_set_vbus(int port, int enable);
-void anx74xx_tcpc_clear_hpd_status(int port);
-void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-extern struct i2c_stress_test_dev anx74xx_i2c_stress_test_dev;
-#endif
-
-#endif /* __CROS_EC_USB_PD_TCPM_ANX74XX_H */
diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c
deleted file mode 100644
index 5e37352bc5..0000000000
--- a/driver/tcpm/anx7688.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ANX7688 port manager */
-
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of anx7688 PD driver"
-#endif
-
-#define ANX7688_VENDOR_ALERT    BIT(15)
-
-#define ANX7688_REG_STATUS      0x82
-#define ANX7688_REG_STATUS_LINK BIT(0)
-
-#define ANX7688_REG_HPD         0x83
-#define ANX7688_REG_HPD_HIGH    BIT(0)
-#define ANX7688_REG_HPD_IRQ     BIT(1)
-#define ANX7688_REG_HPD_ENABLE  BIT(2)
-
-#define ANX7688_USBC_ADDR_FLAGS		0x28
-#define ANX7688_REG_RAMCTRL		0xe7
-#define ANX7688_REG_RAMCTRL_BOOT_DONE	BIT(6)
-
-static int anx7688_init(int port)
-{
-	int rv = 0;
-	int mask = 0;
-
-	/*
-	 * 7688 POWER_STATUS[6] is not reliable for tcpci_tcpm_init() to poll
-	 * due to it is default 0 in HW, and we cannot write TCPC until it is
-	 * ready, or something goes wrong. (Issue 52772)
-	 * Instead we poll TCPC 0x50:0xe7 bit6 here to make sure bootdone is
-	 * ready(50ms). Then PD main flow can process cc debounce in 50ms ~
-	 * 100ms to follow cts.
-	 */
-	while (1) {
-		rv = i2c_read8(I2C_PORT_TCPC, ANX7688_USBC_ADDR_FLAGS,
-			       ANX7688_REG_RAMCTRL, &mask);
-
-		if (rv == EC_SUCCESS && (mask & ANX7688_REG_RAMCTRL_BOOT_DONE))
-			break;
-		msleep(10);
-	}
-
-	rv = tcpci_tcpm_drv.init(port);
-	if (rv)
-		return rv;
-
-	rv = tcpc_read16(port, TCPC_REG_ALERT_MASK, &mask);
-	if (rv)
-		return rv;
-
-	/* enable vendor specific alert */
-	mask |= ANX7688_VENDOR_ALERT;
-	rv = tcpc_write16(port, TCPC_REG_ALERT_MASK, mask);
-	return rv;
-}
-
-static int anx7688_release(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static void anx7688_update_hpd_enable(int port)
-{
-	int status, reg, rv;
-
-	rv = tcpc_read(port, ANX7688_REG_STATUS, &status);
-	rv |= tcpc_read(port, ANX7688_REG_HPD, &reg);
-	if (rv)
-		return;
-
-	if (!(reg & ANX7688_REG_HPD_ENABLE) ||
-	    !(status & ANX7688_REG_STATUS_LINK)) {
-		reg &= ~ANX7688_REG_HPD_IRQ;
-		tcpc_write(port, ANX7688_REG_HPD,
-			   (status & ANX7688_REG_STATUS_LINK)
-			   ? reg | ANX7688_REG_HPD_ENABLE
-			   : reg & ~ANX7688_REG_HPD_ENABLE);
-	}
-}
-
-int anx7688_hpd_disable(int port)
-{
-	return tcpc_write(port, ANX7688_REG_HPD, 0);
-}
-
-int anx7688_update_hpd(int port, int level, int irq)
-{
-	int reg, rv;
-
-	rv = tcpc_read(port, ANX7688_REG_HPD, &reg);
-	if (rv)
-		return rv;
-
-	if (level)
-		reg |= ANX7688_REG_HPD_HIGH;
-	else
-		reg &= ~ANX7688_REG_HPD_HIGH;
-
-	if (irq)
-		reg |= ANX7688_REG_HPD_IRQ;
-	else
-		reg &= ~ANX7688_REG_HPD_IRQ;
-
-	return tcpc_write(port, ANX7688_REG_HPD, reg);
-}
-
-int anx7688_enable_cable_detection(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, 0xff);
-}
-
-int anx7688_set_power_supply_ready(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x77);
-}
-
-int anx7688_power_supply_reset(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x66);
-}
-
-static void anx7688_tcpc_alert(int port)
-{
-	int alert, rv;
-
-	rv = tcpc_read16(port, TCPC_REG_ALERT, &alert);
-	/* process and clear alert status */
-	tcpci_tcpc_alert(port);
-
-	if (!rv && (alert & ANX7688_VENDOR_ALERT))
-		anx7688_update_hpd_enable(port);
-}
-
-static int anx7688_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int reg = 0;
-	int rv, polarity;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg &= ~TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK;
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP;
-
-	/* ANX7688 needs to set bit0 */
-	rv = mux_read(me, TCPC_REG_TCPC_CTRL, &polarity);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* copy the polarity from TCPC_CTRL[0], take care clear then set */
-	reg &= ~TCPC_REG_TCPC_CTRL_POLARITY(1);
-	reg |= TCPC_REG_TCPC_CTRL_POLARITY(polarity);
-	return mux_write(me, TCPC_REG_CONFIG_STD_OUTPUT, reg);
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-static bool anx7688_tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	int reg = 0;
-
-	/* On ANX7688, POWER_STATUS.VBusPresent (bit 2) is averaged 16 times, so
-	 * its value may not be set to 1 quickly enough during power role swap.
-	 * Therefore, we use a proprietary register to read the unfiltered VBus
-	 * value. See crosbug.com/p/55221 .
-	 */
-	i2c_read8(I2C_PORT_TCPC, 0x28, 0x40, &reg);
-
-	if (level == VBUS_PRESENT)
-		return ((reg & 0x10) ? 1 : 0);
-	else
-		return ((reg & 0x10) ? 0 : 1);
-}
-#endif
-
-/* ANX7688 is a TCPCI compatible port controller */
-const struct tcpm_drv anx7688_tcpm_drv = {
-	.init			= &anx7688_init,
-	.release		= &anx7688_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx7688_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7688_tcpc_alert,
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-};
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-const struct usb_mux_driver anx7688_usb_mux_driver = {
-	.init = tcpci_tcpm_mux_init,
-	.set = anx7688_mux_set,
-	.get = tcpci_tcpm_mux_get,
-};
-#endif /* CONFIG_USB_PD_TCPM_MUX */
diff --git a/driver/tcpm/anx7688.h b/driver/tcpm/anx7688.h
deleted file mode 100644
index 534e4155b1..0000000000
--- a/driver/tcpm/anx7688.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-
-#ifndef __CROS_EC_USB_PD_TCPM_ANX7688_H
-#define __CROS_EC_USB_PD_TCPM_ANX7688_H
-
-int anx7688_update_hpd(int port, int level, int irq);
-int anx7688_set_dp_pin_mode(int port, int pin_mode);
-int anx7688_enable_cable_detection(int port);
-int anx7688_set_power_supply_ready(int port);
-int anx7688_power_supply_reset(int port);
-int anx7688_hpd_disable(int port);
-
-extern struct tcpm_drv anx7688_tcpm_drv;
-extern struct usb_mux_driver anx7688_usb_mux_driver;
-
-#endif /* __CROS_EC_USB_PD_TCPM_ANX7688_H */
diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h
deleted file mode 100644
index f4b3deb355..0000000000
--- a/driver/tcpm/ccgxxf.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * USB Power delivery port management For Cypress EZ-PD CCG6DF, CCG6SF
- * CCGXXF FW is designed to adapt standard TCPM driver procedures.
- */
-#ifndef __CROS_EC_DRIVER_TCPM_CCGXXF_H
-#define __CROS_EC_DRIVER_TCPM_CCGXXF_H
-
-#define CCGXXF_I2C_ADDR1_FLAGS	0x0B
-#define CCGXXF_I2C_ADDR2_FLAGS	0x1B
-
-/* CCGXXF built in I/O expander definitions */
-#ifdef CONFIG_IO_EXPANDER_CCGXXF
-
-/* CCGXXF I/O ports that can be referenced in gpio.inc */
-enum ccgxxf_io_ports {
-	CCGXXF_PORT_0,
-	CCGXXF_PORT_1,
-	CCGXXF_PORT_2,
-	CCGXXF_PORT_3
-};
-
-/* CCGXXF I/O pins that can be referenced in gpio.inc */
-enum ccgxxf_io_pins {
-	CCGXXF_IO_0,
-	CCGXXF_IO_1,
-	CCGXXF_IO_2,
-	CCGXXF_IO_3,
-	CCGXXF_IO_4,
-	CCGXXF_IO_5,
-	CCGXXF_IO_6,
-	CCGXXF_IO_7
-};
-
-#define CCGXXF_REG_GPIO_CONTROL(port)	((port) + 0x80)
-#define CCGXXF_REG_GPIO_STATUS(port)	((port) + 0x84)
-
-#define CCGXXF_REG_GPIO_MODE		0x88
-#define CCGXXF_GPIO_PIN_MASK_SHIFT	8
-#define CCGXXF_GPIO_PIN_MODE_SHIFT	2
-#define CCGXXF_GPIO_1P8V_SEL		BIT(7)
-
-enum ccgxxf_gpio_mode {
-	CCGXXF_GPIO_MODE_HIZ_ANALOG,
-	CCGXXF_GPIO_MODE_HIZ_DIGITAL,
-	CCGXXF_GPIO_MODE_RES_UP,
-	CCGXXF_GPIO_MODE_RES_DWN,
-	CCGXXF_GPIO_MODE_OD_LOW,
-	CCGXXF_GPIO_MODE_OD_HIGH,
-	CCGXXF_GPIO_MODE_STRONG,
-	CCGXXF_GPIO_MODE_RES_UPDOWN
-};
-
-extern const struct ioexpander_drv ccgxxf_ioexpander_drv;
-
-#endif /* CONFIG_IO_EXPANDER_CCGXXF */
-
-#endif /* __CROS_EC_DRIVER_TCPM_CCGXXF_H */
diff --git a/driver/tcpm/fusb302.c b/driver/tcpm/fusb302.c
deleted file mode 100644
index 0098906d32..0000000000
--- a/driver/tcpm/fusb302.c
+++ /dev/null
@@ -1,1205 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Author: Gabe Noblesmith
- */
-
-/* Type-C port manager for Fairchild's FUSB302 */
-
-#include "console.h"
-#include "fusb302.h"
-#include "task.h"
-#include "hooks.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of fusb302 PD driver"
-#endif
-
-#define PACKET_IS_GOOD_CRC(head) (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && \
-				 PD_HEADER_CNT(head) == 0)
-
-static struct fusb302_chip_state {
-	int cc_polarity;
-	int vconn_enabled;
-	/* 1 = pulling up (DFP) 0 = pulling down (UFP) */
-	int pulling_up;
-	int rx_enable;
-	uint8_t mdac_vnc;
-	uint8_t mdac_rd;
-} state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static struct mutex measure_lock;
-
-/*
- * Bring the FUSB302 out of reset after Hard Reset signaling. This will
- * automatically flush both the Rx and Tx FIFOs.
- */
-static void fusb302_pd_reset(int port)
-{
-	tcpc_write(port, TCPC_REG_RESET, TCPC_REG_RESET_PD_RESET);
-}
-
-/*
- * Flush our Rx FIFO. To prevent packet framing issues, this function should
- * only be called when Rx is disabled.
- */
-static void fusb302_flush_rx_fifo(int port)
-{
-	/*
-	 * other bits in the register _should_ be 0
-	 * until the day we support other SOP* types...
-	 * then we'll have to keep a shadow of what this register
-	 * value should be so we don't clobber it here!
-	 */
-	tcpc_write(port, TCPC_REG_CONTROL1, TCPC_REG_CONTROL1_RX_FLUSH);
-}
-
-static void fusb302_flush_tx_fifo(int port)
-{
-	int reg;
-
-	tcpc_read(port, TCPC_REG_CONTROL0, &reg);
-	reg |= TCPC_REG_CONTROL0_TX_FLUSH;
-	tcpc_write(port, TCPC_REG_CONTROL0, reg);
-}
-
-static void fusb302_auto_goodcrc_enable(int port, int enable)
-{
-	int reg;
-
-	tcpc_read(port,	TCPC_REG_SWITCHES1, &reg);
-
-	if (enable)
-		reg |= TCPC_REG_SWITCHES1_AUTO_GCRC;
-	else
-		reg &= ~TCPC_REG_SWITCHES1_AUTO_GCRC;
-
-	tcpc_write(port, TCPC_REG_SWITCHES1, reg);
-}
-
-/* Convert BC LVL values (in FUSB302) to Type-C CC Voltage Status */
-static int convert_bc_lvl(int port, int bc_lvl)
-{
-	/* assume OPEN unless one of the following conditions is true... */
-	int ret = TYPEC_CC_VOLT_OPEN;
-
-	if (state[port].pulling_up) {
-		if (bc_lvl == 0x00)
-			ret = TYPEC_CC_VOLT_RA;
-		else if (bc_lvl < 0x3)
-			ret = TYPEC_CC_VOLT_RD;
-	} else {
-		if (bc_lvl == 0x1)
-			ret = TYPEC_CC_VOLT_RP_DEF;
-		else if (bc_lvl == 0x2)
-			ret = TYPEC_CC_VOLT_RP_1_5;
-		else if (bc_lvl == 0x3)
-			ret = TYPEC_CC_VOLT_RP_3_0;
-	}
-
-	return ret;
-}
-
-static int measure_cc_pin_source(int port, int cc_measure)
-{
-	int switches0_reg;
-	int reg;
-	int cc_lvl;
-
-	mutex_lock(&measure_lock);
-
-	/* Read status register */
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-	/* Save current value */
-	switches0_reg = reg;
-	/* Clear pull-up register settings and measure bits */
-	reg &= ~(TCPC_REG_SWITCHES0_MEAS_CC1 | TCPC_REG_SWITCHES0_MEAS_CC2);
-	/* Set desired pullup register bit */
-	if (cc_measure == TCPC_REG_SWITCHES0_MEAS_CC1)
-		reg |= TCPC_REG_SWITCHES0_CC1_PU_EN;
-	else
-		reg |= TCPC_REG_SWITCHES0_CC2_PU_EN;
-	/* Set CC measure bit */
-	reg |= cc_measure;
-
-	/* Set measurement switch */
-	tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-	/* Set MDAC for Open vs Rd/Ra comparison */
-	tcpc_write(port, TCPC_REG_MEASURE, state[port].mdac_vnc);
-
-	/* Wait on measurement */
-	usleep(250);
-
-	/* Read status register */
-	tcpc_read(port, TCPC_REG_STATUS0, &reg);
-
-	/* Assume open */
-	cc_lvl = TYPEC_CC_VOLT_OPEN;
-
-	/* CC level is below the 'no connect' threshold (vOpen) */
-	if ((reg & TCPC_REG_STATUS0_COMP) == 0) {
-		/* Set MDAC for Rd vs Ra comparison */
-		tcpc_write(port, TCPC_REG_MEASURE, state[port].mdac_rd);
-
-		/* Wait on measurement */
-		usleep(250);
-
-		/* Read status register */
-		tcpc_read(port, TCPC_REG_STATUS0, &reg);
-
-		cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD
-						       : TYPEC_CC_VOLT_RA;
-	}
-
-	/* Restore SWITCHES0 register to its value prior */
-	tcpc_write(port, TCPC_REG_SWITCHES0, switches0_reg);
-
-	mutex_unlock(&measure_lock);
-
-	return cc_lvl;
-}
-
-/* Determine cc pin state for source when in manual detect mode */
-static void detect_cc_pin_source_manual(int port,
-	enum tcpc_cc_voltage_status *cc1_lvl,
-	enum tcpc_cc_voltage_status *cc2_lvl)
-{
-	int cc1_measure = TCPC_REG_SWITCHES0_MEAS_CC1;
-	int cc2_measure = TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	if (state[port].vconn_enabled) {
-		/* If VCONN enabled, measure cc_pin that matches polarity */
-		if (state[port].cc_polarity)
-			*cc2_lvl = measure_cc_pin_source(port, cc2_measure);
-		else
-			*cc1_lvl = measure_cc_pin_source(port, cc1_measure);
-	} else {
-		/* If VCONN not enabled, measure both cc1 and cc2 */
-		*cc1_lvl = measure_cc_pin_source(port, cc1_measure);
-		*cc2_lvl = measure_cc_pin_source(port, cc2_measure);
-	}
-
-}
-
-/* Determine cc pin state for sink */
-static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int reg;
-	int orig_meas_cc1;
-	int orig_meas_cc2;
-	int bc_lvl_cc1;
-	int bc_lvl_cc2;
-
-	mutex_lock(&measure_lock);
-
-	/*
-	 * Measure CC1 first.
-	 */
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-	/* save original state to be returned to later... */
-	if (reg & TCPC_REG_SWITCHES0_MEAS_CC1)
-		orig_meas_cc1 = 1;
-	else
-		orig_meas_cc1 = 0;
-
-	if (reg & TCPC_REG_SWITCHES0_MEAS_CC2)
-		orig_meas_cc2 = 1;
-	else
-		orig_meas_cc2 = 0;
-
-
-	/* Disable CC2 measurement switch, enable CC1 measurement switch */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-
-	tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-	/* CC1 is now being measured by FUSB302. */
-
-	/* Wait on measurement */
-	usleep(250);
-
-	tcpc_read(port, TCPC_REG_STATUS0, &bc_lvl_cc1);
-
-	/* mask away unwanted bits */
-	bc_lvl_cc1 &= (TCPC_REG_STATUS0_BC_LVL0 | TCPC_REG_STATUS0_BC_LVL1);
-
-	/*
-	 * Measure CC2 next.
-	 */
-
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-	/* Disable CC1 measurement switch, enable CC2 measurement switch */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-	/* CC2 is now being measured by FUSB302. */
-
-	/* Wait on measurement */
-	usleep(250);
-
-	tcpc_read(port, TCPC_REG_STATUS0, &bc_lvl_cc2);
-
-	/* mask away unwanted bits */
-	bc_lvl_cc2 &= (TCPC_REG_STATUS0_BC_LVL0 | TCPC_REG_STATUS0_BC_LVL1);
-
-	*cc1 = convert_bc_lvl(port, bc_lvl_cc1);
-	*cc2 = convert_bc_lvl(port, bc_lvl_cc2);
-
-	/* return MEAS_CC1/2 switches to original state */
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-	if (orig_meas_cc1)
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-	else
-		reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	if (orig_meas_cc2)
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-	else
-		reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-	mutex_unlock(&measure_lock);
-}
-
-/* Parse header bytes for the size of packet */
-static int get_num_bytes(uint16_t header)
-{
-	int rv;
-
-	/* Grab the Number of Data Objects field.*/
-	rv = PD_HEADER_CNT(header);
-
-	/* Multiply by four to go from 32-bit words -> bytes */
-	rv *= 4;
-
-	/* Plus 2 for header */
-	rv += 2;
-
-	return rv;
-}
-
-static int fusb302_send_message(int port, uint16_t header, const uint32_t *data,
-				 uint8_t *buf, int buf_pos)
-{
-	int rv;
-	int reg;
-	int len;
-
-	len = get_num_bytes(header);
-
-	/*
-	 * packsym tells the TXFIFO that the next X bytes are payload,
-	 * and should not be interpreted as special tokens.
-	 * The 5 LSBs represent X, the number of bytes.
-	 */
-	reg = FUSB302_TKN_PACKSYM;
-	reg |= (len & 0x1F);
-
-	buf[buf_pos++] = reg;
-
-	/* write in the header */
-	reg = header;
-	buf[buf_pos++] = reg & 0xFF;
-
-	reg >>= 8;
-	buf[buf_pos++] = reg & 0xFF;
-
-	/* header is done, subtract from length to make this for-loop simpler */
-	len -= 2;
-
-	/* write data objects, if present */
-	memcpy(&buf[buf_pos], data, len);
-	buf_pos += len;
-
-	/* put in the CRC */
-	buf[buf_pos++] = FUSB302_TKN_JAMCRC;
-
-	/* put in EOP */
-	buf[buf_pos++] = FUSB302_TKN_EOP;
-
-	/* Turn transmitter off after sending message */
-	buf[buf_pos++] = FUSB302_TKN_TXOFF;
-
-	/* Start transmission */
-	reg = FUSB302_TKN_TXON;
-	buf[buf_pos++] = FUSB302_TKN_TXON;
-
-	/* burst write for speed! */
-	rv = tcpc_xfer(port, buf, buf_pos, 0, 0);
-
-	return rv;
-}
-
-static int fusb302_tcpm_select_rp_value(int port, int rp)
-{
-	int reg;
-	int rv;
-	uint8_t vnc, rd;
-
-	/* Keep track of current RP value */
-	tcpci_set_cached_rp(port, rp);
-
-	rv = tcpc_read(port, TCPC_REG_CONTROL0, &reg);
-	if (rv)
-		return rv;
-
-	/* Set the current source for Rp value */
-	reg &= ~TCPC_REG_CONTROL0_HOST_CUR_MASK;
-	switch (rp) {
-	case TYPEC_RP_1A5:
-		reg |= TCPC_REG_CONTROL0_HOST_CUR_1A5;
-		vnc = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_1_5_VNC_MV);
-		rd = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_1_5_RD_THRESH_MV);
-		break;
-	case TYPEC_RP_3A0:
-		reg |= TCPC_REG_CONTROL0_HOST_CUR_3A0;
-		vnc = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_3_0_VNC_MV);
-		rd = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_3_0_RD_THRESH_MV);
-		break;
-	case TYPEC_RP_USB:
-	default:
-		reg |= TCPC_REG_CONTROL0_HOST_CUR_USB;
-		vnc = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_DEF_VNC_MV);
-		rd = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_DEF_RD_THRESH_MV);
-	}
-	state[port].mdac_vnc = vnc;
-	state[port].mdac_rd = rd;
-	return tcpc_write(port, TCPC_REG_CONTROL0, reg);
-}
-
-static int fusb302_tcpm_init(int port)
-{
-	int reg;
-
-	/* set default */
-	state[port].cc_polarity = -1;
-
-	/* set the voltage threshold for no connect detection (vOpen) */
-	state[port].mdac_vnc = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_DEF_VNC_MV);
-	/* set the voltage threshold for Rd vs Ra detection */
-	state[port].mdac_rd = TCPC_REG_MEASURE_MDAC_MV(PD_SRC_DEF_RD_THRESH_MV);
-
-	/* all other variables assumed to default to 0 */
-
-	/* Restore default settings */
-	tcpc_write(port, TCPC_REG_RESET, TCPC_REG_RESET_SW_RESET);
-
-	/* Turn on retries and set number of retries */
-	tcpc_read(port, TCPC_REG_CONTROL3, &reg);
-	reg |= TCPC_REG_CONTROL3_AUTO_RETRY;
-	reg |= (CONFIG_PD_RETRY_COUNT & 0x3) << TCPC_REG_CONTROL3_N_RETRIES_POS;
-	tcpc_write(port, TCPC_REG_CONTROL3, reg);
-
-	/* Create interrupt masks */
-	reg = 0xFF;
-	/* CC level changes */
-	reg &= ~TCPC_REG_MASK_BC_LVL;
-	/* collisions */
-	reg &= ~TCPC_REG_MASK_COLLISION;
-	/* misc alert */
-	reg &= ~TCPC_REG_MASK_ALERT;
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	/* TODO(crbug.com/791109): Clean up VBUS notification. */
-
-	/* VBUS threshold crossed (~4.0V) */
-	reg &= ~TCPC_REG_MASK_VBUSOK;
-#endif
-	tcpc_write(port, TCPC_REG_MASK, reg);
-
-	reg = 0xFF;
-	/* when all pd message retries fail... */
-	reg &= ~TCPC_REG_MASKA_RETRYFAIL;
-	/* when fusb302 send a hard reset. */
-	reg &= ~TCPC_REG_MASKA_HARDSENT;
-	/* when fusb302 receives GoodCRC ack for a pd message */
-	reg &= ~TCPC_REG_MASKA_TX_SUCCESS;
-	/* when fusb302 receives a hard reset */
-	reg &= ~TCPC_REG_MASKA_HARDRESET;
-	tcpc_write(port, TCPC_REG_MASKA, reg);
-
-	reg = 0xFF;
-	/* when fusb302 sends GoodCRC to ack a pd message */
-	reg &= ~TCPC_REG_MASKB_GCRCSENT;
-	tcpc_write(port, TCPC_REG_MASKB, reg);
-
-	/* Interrupt Enable */
-	tcpc_read(port, TCPC_REG_CONTROL0, &reg);
-	reg &= ~TCPC_REG_CONTROL0_INT_MASK;
-	tcpc_write(port, TCPC_REG_CONTROL0, reg);
-
-	/* Set VCONN switch defaults */
-	tcpm_set_polarity(port, 0);
-	tcpm_set_vconn(port, 0);
-
-	/* TODO: Reduce power consumption */
-	tcpc_write(port, TCPC_REG_POWER, TCPC_REG_POWER_PWR_ALL);
-
-#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) && defined(CONFIG_USB_CHARGER)
-	/* Wait for the reference voltage to stablize */
-	usleep(250);
-	/*
-	 * Initialize VBUS supplier when VBUS is already present before
-	 * init (e.g. Cold reboot with charger plugged).
-	 */
-	tcpc_read(port, TCPC_REG_STATUS0, &reg);
-	if (reg & TCPC_REG_STATUS0_VBUSOK)
-		usb_charger_vbus_change(port, 1);
-#endif
-
-	return 0;
-}
-
-static int fusb302_tcpm_release(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static int fusb302_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	if (state[port].pulling_up) {
-		/* Source mode? */
-		detect_cc_pin_source_manual(port, cc1, cc2);
-	} else {
-		/* Sink mode? */
-		detect_cc_pin_sink(port, cc1, cc2);
-	}
-
-	return 0;
-}
-
-static int fusb302_tcpm_set_cc(int port, int pull)
-{
-	int reg;
-
-	/* NOTE: FUSB302 toggles a single pull-up between CC1 and CC2 */
-	/* NOTE: FUSB302 Does not support Ra. */
-	switch (pull) {
-	case TYPEC_CC_RP:
-		/* enable the pull-up we know to be necessary */
-		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-		reg &= ~(TCPC_REG_SWITCHES0_CC2_PU_EN |
-			 TCPC_REG_SWITCHES0_CC1_PU_EN |
-			 TCPC_REG_SWITCHES0_CC1_PD_EN |
-			 TCPC_REG_SWITCHES0_CC2_PD_EN |
-			 TCPC_REG_SWITCHES0_VCONN_CC1 |
-			 TCPC_REG_SWITCHES0_VCONN_CC2);
-
-		reg |= TCPC_REG_SWITCHES0_CC1_PU_EN |
-			TCPC_REG_SWITCHES0_CC2_PU_EN;
-
-		if (state[port].vconn_enabled)
-			reg |= state[port].cc_polarity ?
-			       TCPC_REG_SWITCHES0_VCONN_CC1 :
-			       TCPC_REG_SWITCHES0_VCONN_CC2;
-
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		state[port].pulling_up = 1;
-		break;
-	case TYPEC_CC_RD:
-		/* Enable UFP Mode */
-
-		/* turn off toggle */
-		tcpc_read(port, TCPC_REG_CONTROL2, &reg);
-		reg &= ~TCPC_REG_CONTROL2_TOGGLE;
-		tcpc_write(port, TCPC_REG_CONTROL2, reg);
-
-		/* enable pull-downs, disable pullups */
-		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-		reg &= ~(TCPC_REG_SWITCHES0_CC2_PU_EN);
-		reg &= ~(TCPC_REG_SWITCHES0_CC1_PU_EN);
-		reg |= (TCPC_REG_SWITCHES0_CC1_PD_EN);
-		reg |= (TCPC_REG_SWITCHES0_CC2_PD_EN);
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		state[port].pulling_up = 0;
-		break;
-	case TYPEC_CC_OPEN:
-		/* Disable toggling */
-		tcpc_read(port, TCPC_REG_CONTROL2, &reg);
-		reg &= ~TCPC_REG_CONTROL2_TOGGLE;
-		tcpc_write(port, TCPC_REG_CONTROL2, reg);
-
-		/* Ensure manual switches are opened */
-		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-		reg &= ~TCPC_REG_SWITCHES0_CC1_PU_EN;
-		reg &= ~TCPC_REG_SWITCHES0_CC2_PU_EN;
-		reg &= ~TCPC_REG_SWITCHES0_CC1_PD_EN;
-		reg &= ~TCPC_REG_SWITCHES0_CC2_PD_EN;
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		state[port].pulling_up = 0;
-		break;
-	default:
-		/* Unsupported... */
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-	return 0;
-}
-
-static int fusb302_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	/* Port polarity : 0 => CC1 is CC line, 1 => CC2 is CC line */
-	int reg;
-
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-	/* clear VCONN switch bits */
-	reg &= ~TCPC_REG_SWITCHES0_VCONN_CC1;
-	reg &= ~TCPC_REG_SWITCHES0_VCONN_CC2;
-
-	if (state[port].vconn_enabled) {
-		/* set VCONN switch to be non-CC line */
-		if (polarity_rm_dts(polarity))
-			reg |= TCPC_REG_SWITCHES0_VCONN_CC1;
-		else
-			reg |= TCPC_REG_SWITCHES0_VCONN_CC2;
-	}
-
-	/* clear meas_cc bits (RX line select) */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	/* set rx polarity */
-	if (polarity_rm_dts(polarity))
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-	else
-		reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-
-	tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-	tcpc_read(port, TCPC_REG_SWITCHES1, &reg);
-
-	/* clear tx_cc bits */
-	reg &= ~TCPC_REG_SWITCHES1_TXCC1_EN;
-	reg &= ~TCPC_REG_SWITCHES1_TXCC2_EN;
-
-	/* set tx polarity */
-	if (polarity_rm_dts(polarity))
-		reg |= TCPC_REG_SWITCHES1_TXCC2_EN;
-	else
-		reg |= TCPC_REG_SWITCHES1_TXCC1_EN;
-
-	tcpc_write(port, TCPC_REG_SWITCHES1, reg);
-
-	/* Save the polarity for later */
-	state[port].cc_polarity = polarity;
-
-	return 0;
-}
-
-__maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port,
-								bool enable)
-{
-	int reg;
-
-	if (tcpc_read(port, TCPC_REG_CONTROL1, &reg))
-		return EC_ERROR_UNKNOWN;
-
-	if (enable)
-		reg |= (TCPC_REG_CONTROL1_ENSOP1 |
-				TCPC_REG_CONTROL1_ENSOP2);
-	else
-		reg &= ~(TCPC_REG_CONTROL1_ENSOP1 |
-			TCPC_REG_CONTROL1_ENSOP2);
-
-	return tcpc_write(port, TCPC_REG_CONTROL1, reg);
-}
-
-static int fusb302_tcpm_set_vconn(int port, int enable)
-{
-	/*
-	 * FUSB302 does not have dedicated VCONN Enable switch.
-	 * We'll get through this by disabling both of the
-	 * VCONN - CC* switches to disable, and enabling the
-	 * saved polarity when enabling.
-	 * Therefore at startup, tcpm_set_polarity should be called first,
-	 * or else live with the default put into tcpm_init.
-	 */
-	int reg;
-
-	/* save enable state for later use */
-	state[port].vconn_enabled = enable;
-
-	if (enable) {
-		/* set to saved polarity */
-		tcpm_set_polarity(port, state[port].cc_polarity);
-
-		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-			if (state[port].rx_enable) {
-				if (fusb302_tcpm_decode_sop_prime_enable(port,
-									true))
-					return EC_ERROR_UNKNOWN;
-			}
-		}
-	} else {
-
-		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-		/* clear VCONN switch bits */
-		reg &= ~TCPC_REG_SWITCHES0_VCONN_CC1;
-		reg &= ~TCPC_REG_SWITCHES0_VCONN_CC2;
-
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-			if (state[port].rx_enable) {
-				if (fusb302_tcpm_decode_sop_prime_enable(port,
-									false))
-					return EC_ERROR_UNKNOWN;
-			}
-		}
-	}
-
-	return 0;
-}
-
-static int fusb302_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	int reg;
-
-	tcpc_read(port, TCPC_REG_SWITCHES1, &reg);
-
-	reg &= ~TCPC_REG_SWITCHES1_POWERROLE;
-	reg &= ~TCPC_REG_SWITCHES1_DATAROLE;
-
-	if (power_role)
-		reg |= TCPC_REG_SWITCHES1_POWERROLE;
-	if (data_role)
-		reg |= TCPC_REG_SWITCHES1_DATAROLE;
-
-	tcpc_write(port, TCPC_REG_SWITCHES1, reg);
-
-	return 0;
-}
-
-static int fusb302_tcpm_set_rx_enable(int port, int enable)
-{
-	int reg;
-
-	state[port].rx_enable = enable;
-
-	/* Get current switch state */
-	tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
-
-	/* Clear CC1/CC2 measure bits */
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC1;
-	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
-
-	if (enable) {
-		switch (state[port].cc_polarity) {
-		/* if CC polarity hasnt been determined, can't enable */
-		case -1:
-			return EC_ERROR_UNKNOWN;
-		case 0:
-			reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
-			break;
-		case 1:
-			reg |= TCPC_REG_SWITCHES0_MEAS_CC2;
-			break;
-		default:
-			/* "shouldn't get here" */
-			return EC_ERROR_UNKNOWN;
-		}
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		/* Disable BC_LVL interrupt when enabling PD comm */
-		if (!tcpc_read(port, TCPC_REG_MASK, &reg))
-			tcpc_write(port, TCPC_REG_MASK,
-				   reg | TCPC_REG_MASK_BC_LVL);
-
-		/* flush rx fifo in case messages have been coming our way */
-		fusb302_flush_rx_fifo(port);
-
-
-	} else {
-		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
-
-		/* Enable BC_LVL interrupt when disabling PD comm */
-		if (!tcpc_read(port, TCPC_REG_MASK, &reg))
-			tcpc_write(port, TCPC_REG_MASK,
-				   reg & ~TCPC_REG_MASK_BC_LVL);
-	}
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	/*
-	 * Only the VCONN Source is allowed to communicate
-	 * with the Cable Plugs.
-	 */
-	if (state[port].vconn_enabled) {
-		if (tcpc_read(port, TCPC_REG_CONTROL1, &reg))
-			return EC_ERROR_UNKNOWN;
-
-		reg |= (TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2);
-		tcpc_write(port, TCPC_REG_CONTROL1, reg);
-	}
-#endif
-
-	fusb302_auto_goodcrc_enable(port, enable);
-
-	return 0;
-}
-
-/* Return true if our Rx FIFO is empty */
-static int fusb302_rx_fifo_is_empty(int port)
-{
-	int reg;
-
-	return (!tcpc_read(port, TCPC_REG_STATUS1, &reg)) &&
-	       (reg & TCPC_REG_STATUS1_RX_EMPTY);
-}
-
-static int fusb302_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	/*
-	 * This is the buffer that will get the burst-read data
-	 * from the fusb302.
-	 *
-	 * It's re-used in a couple different spots, the worst of which
-	 * is the PD packet (not header) and CRC.
-	 * maximum size necessary = 28 + 4 = 32
-	 */
-	uint8_t buf[32];
-	int rv, len;
-
-	/* Read until we have a non-GoodCRC packet or an empty FIFO */
-	do {
-		buf[0] = TCPC_REG_FIFOS;
-		tcpc_lock(port, 1);
-
-		/*
-		 * PART 1 OF BURST READ: Write in register address.
-		 * Issue a START, no STOP.
-		 */
-		rv = tcpc_xfer_unlocked(port, buf, 1, 0, 0, I2C_XFER_START);
-
-		/*
-		 * PART 2 OF BURST READ: Read up to the header.
-		 * Issue a repeated START, no STOP.
-		 * only grab three bytes so we can get the header
-		 * and determine how many more bytes we need to read.
-		 * TODO: Check token to ensure valid packet.
-		 */
-		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, 3, I2C_XFER_START);
-
-		/* Grab the header */
-		*head = (buf[1] & 0xFF);
-		*head |= ((buf[2] << 8) & 0xFF00);
-
-		/* figure out packet length, subtract header bytes */
-		len = get_num_bytes(*head) - 2;
-
-		/*
-		 * PART 3 OF BURST READ: Read everything else.
-		 * No START, but do issue a STOP at the end.
-		 * add 4 to len to read CRC out
-		 */
-		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len+4, I2C_XFER_STOP);
-
-		tcpc_lock(port, 0);
-	} while (!rv && PACKET_IS_GOOD_CRC(*head) &&
-		 !fusb302_rx_fifo_is_empty(port));
-
-	if (!rv) {
-		/* Discard GoodCRC packets */
-		if (PACKET_IS_GOOD_CRC(*head))
-			rv = EC_ERROR_UNKNOWN;
-		else
-			memcpy(payload, buf, len);
-	}
-
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	{
-		int reg;
-
-		if (tcpc_read(port, TCPC_REG_STATUS1, &reg))
-			return EC_ERROR_UNKNOWN;
-
-		if (reg & TCPC_REG_STATUS1_RXSOP1)
-			*head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME);
-		else if (reg & TCPC_REG_STATUS1_RXSOP2)
-			*head |= PD_HEADER_SOP(TCPCI_MSG_SOP_PRIME_PRIME);
-	}
-#endif
-
-	return rv;
-}
-
-static int fusb302_tcpm_transmit(int port, enum tcpci_msg_type type,
-				 uint16_t header, const uint32_t *data)
-{
-	/*
-	 * this is the buffer that will be burst-written into the fusb302
-	 * maximum size necessary =
-	 * 1: FIFO register address
-	 * 4: SOP* tokens
-	 * 1: Token that signifies "next X bytes are not tokens"
-	 * 30: 2 for header and up to 7*4 = 28 for rest of message
-	 * 1: "Insert CRC" Token
-	 * 1: EOP Token
-	 * 1: "Turn transmitter off" token
-	 * 1: "Star Transmission" Command
-	 * -
-	 * 40: 40 bytes worst-case
-	 */
-	uint8_t buf[40];
-	int buf_pos = 0;
-
-	int reg;
-
-	/* Flush the TXFIFO */
-	fusb302_flush_tx_fifo(port);
-
-	switch (type) {
-	case TCPCI_MSG_SOP:
-
-		/* put register address first for of burst tcpc write */
-		buf[buf_pos++] = TCPC_REG_FIFOS;
-
-		/* Write the SOP Ordered Set into TX FIFO */
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC2;
-
-		return fusb302_send_message(port, header, data, buf, buf_pos);
-	case TCPCI_MSG_SOP_PRIME:
-
-		/* put register address first for of burst tcpc write */
-		buf[buf_pos++] = TCPC_REG_FIFOS;
-
-		/* Write the SOP' Ordered Set into TX FIFO */
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC3;
-		buf[buf_pos++] = FUSB302_TKN_SYNC3;
-
-		return fusb302_send_message(port, header, data, buf, buf_pos);
-	case TCPCI_MSG_SOP_PRIME_PRIME:
-
-		/* put register address first for of burst tcpc write */
-		buf[buf_pos++] = TCPC_REG_FIFOS;
-
-		/* Write the SOP'' Ordered Set into TX FIFO */
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC3;
-		buf[buf_pos++] = FUSB302_TKN_SYNC1;
-		buf[buf_pos++] = FUSB302_TKN_SYNC3;
-
-		return fusb302_send_message(port, header, data, buf, buf_pos);
-	case TCPCI_MSG_TX_HARD_RESET:
-		/* Simply hit the SEND_HARD_RESET bit */
-		tcpc_read(port, TCPC_REG_CONTROL3, &reg);
-		reg |= TCPC_REG_CONTROL3_SEND_HARDRESET;
-		tcpc_write(port, TCPC_REG_CONTROL3, reg);
-
-		break;
-	case TCPCI_MSG_TX_BIST_MODE_2:
-		/* Hit the BIST_MODE2 bit and start TX */
-		tcpc_read(port, TCPC_REG_CONTROL1, &reg);
-		reg |= TCPC_REG_CONTROL1_BIST_MODE2;
-		tcpc_write(port, TCPC_REG_CONTROL1, reg);
-
-		tcpc_read(port, TCPC_REG_CONTROL0, &reg);
-		reg |= TCPC_REG_CONTROL0_TX_START;
-		tcpc_write(port, TCPC_REG_CONTROL0, reg);
-
-		task_wait_event(PD_T_BIST_TRANSMIT);
-
-		/* Clear BIST mode bit, TX_START is self-clearing */
-		tcpc_read(port, TCPC_REG_CONTROL1, &reg);
-		reg &= ~TCPC_REG_CONTROL1_BIST_MODE2;
-		tcpc_write(port, TCPC_REG_CONTROL1, reg);
-
-		break;
-	default:
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-static bool fusb302_tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	int reg;
-
-	/* Read status register */
-	tcpc_read(port, TCPC_REG_STATUS0, &reg);
-
-	if (level == VBUS_PRESENT)
-		return (reg & TCPC_REG_STATUS0_VBUSOK) ? 1 : 0;
-	else
-		return (reg & TCPC_REG_STATUS0_VBUSOK) ? 0 : 1;
-}
-#endif
-
-void fusb302_tcpc_alert(int port)
-{
-	/* interrupt has been received */
-	int interrupt;
-	int interrupta;
-	int interruptb;
-
-	/* reading interrupt registers clears them */
-
-	tcpc_read(port, TCPC_REG_INTERRUPT, &interrupt);
-	tcpc_read(port, TCPC_REG_INTERRUPTA, &interrupta);
-	tcpc_read(port, TCPC_REG_INTERRUPTB, &interruptb);
-
-	/*
-	 * Ignore BC_LVL changes when transmitting / receiving PD,
-	 * since CC level will constantly change.
-	 */
-	if (state[port].rx_enable)
-		interrupt &= ~TCPC_REG_INTERRUPT_BC_LVL;
-
-	if (interrupt & TCPC_REG_INTERRUPT_BC_LVL) {
-		/* CC Status change */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-	}
-
-	if (interrupt & TCPC_REG_INTERRUPT_COLLISION) {
-		/* packet sending collided */
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_FAILED);
-	}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	if (interrupt & TCPC_REG_INTERRUPT_VBUSOK) {
-		/* VBUS crossed threshold */
-#ifdef CONFIG_USB_CHARGER
-		usb_charger_vbus_change(port,
-					fusb302_tcpm_check_vbus_level(port,
-							VBUS_PRESENT));
-#else
-		if (!fusb302_tcpm_check_vbus_level(port, VBUS_PRESENT))
-			pd_vbus_low(port);
-#endif
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		hook_notify(HOOK_AC_CHANGE);
-	}
-#endif
-
-	/* GoodCRC was received, our FIFO is now non-empty */
-	if (interrupta & TCPC_REG_INTERRUPTA_TX_SUCCESS) {
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
-	}
-
-	if (interrupta & TCPC_REG_INTERRUPTA_RETRYFAIL) {
-		/* all retries have failed to get a GoodCRC */
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_FAILED);
-	}
-
-	if (interrupta & TCPC_REG_INTERRUPTA_HARDSENT) {
-		/* hard reset has been sent */
-
-		/* bring FUSB302 out of reset */
-		fusb302_pd_reset(port);
-
-		pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
-	}
-
-	if (interrupta & TCPC_REG_INTERRUPTA_HARDRESET) {
-		/* hard reset has been received */
-
-		/* bring FUSB302 out of reset */
-		fusb302_pd_reset(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_RX_HARD_RESET);
-	}
-
-	if (interruptb & TCPC_REG_INTERRUPTB_GCRCSENT) {
-		/* Packet received and GoodCRC sent */
-		/* (this interrupt fires after the GoodCRC finishes) */
-		if (state[port].rx_enable) {
-			/* Pull all RX messages from TCPC into EC memory */
-			while (!fusb302_rx_fifo_is_empty(port))
-				tcpm_enqueue_message(port);
-		} else {
-			/* flush rx fifo if rx isn't enabled */
-			fusb302_flush_rx_fifo(port);
-		}
-	}
-
-}
-
-/* For BIST receiving */
-void tcpm_set_bist_test_data(int port)
-{
-	int reg;
-
-	/* Read control3 register */
-	tcpc_read(port, TCPC_REG_CONTROL3, &reg);
-
-	/* Set the BIST_TMODE bit (Clears on Hard Reset) */
-	reg |= TCPC_REG_CONTROL3_BIST_TMODE;
-
-	/* Write the updated value */
-	tcpc_write(port, TCPC_REG_CONTROL3, reg);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int fusb302_set_toggle_mode(int port, int mode)
-{
-	int reg, rv;
-
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~TCPC_REG_CONTROL2_MODE_MASK;
-	reg |= mode << TCPC_REG_CONTROL2_MODE_POS;
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
-}
-
-static int fusb302_tcpm_enter_low_power_mode(int port)
-{
-	int reg, rv, mode = TCPC_REG_CONTROL2_MODE_DRP;
-
-	/**
-	 * vendor's suggested LPM flow:
-	 * - enable low power mode and set up other things
-	 * - sleep 250 us
-	 * - start toggling
-	 */
-	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			  tcpc_config[port].i2c_info.addr_flags,
-			  TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW);
-	if (rv)
-		return rv;
-
-	switch (pd_get_dual_role(port)) {
-	case PD_DRP_TOGGLE_ON:
-		mode = TCPC_REG_CONTROL2_MODE_DRP;
-		break;
-	case PD_DRP_TOGGLE_OFF:
-		mode = TCPC_REG_CONTROL2_MODE_UFP;
-		break;
-	case PD_DRP_FREEZE:
-		mode = pd_get_power_role(port) == PD_ROLE_SINK ?
-			TCPC_REG_CONTROL2_MODE_UFP :
-			TCPC_REG_CONTROL2_MODE_DFP;
-		break;
-	case PD_DRP_FORCE_SINK:
-		mode = TCPC_REG_CONTROL2_MODE_UFP;
-		break;
-	case PD_DRP_FORCE_SOURCE:
-		mode = TCPC_REG_CONTROL2_MODE_DFP;
-		break;
-	}
-	rv = fusb302_set_toggle_mode(port, mode);
-	if (rv)
-		return rv;
-
-	usleep(250);
-
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
-	if (rv)
-		return rv;
-	reg |= TCPC_REG_CONTROL2_TOGGLE;
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
-}
-#endif
-
-/*
- * Compare VBUS voltage with given mdac reference voltage.
- * returns non-zero if VBUS voltage >= (mdac + 1) * 420 mV
- */
-static int fusb302_compare_mdac(int port, int mdac)
-{
-	int orig_reg, status0;
-
-	mutex_lock(&measure_lock);
-
-	/* backup REG_MEASURE */
-	tcpc_read(port, TCPC_REG_MEASURE, &orig_reg);
-	/* set reg_measure bit 0~5 to mdac, and bit6 to 1(measure vbus) */
-	tcpc_write(port, TCPC_REG_MEASURE,
-		(mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS);
-
-	/* Wait on measurement */
-	usleep(350);
-
-	/*
-	 * Read status register, if STATUS0_COMP=1 then vbus is higher than
-	 * (mdac + 1) * 0.42V
-	 */
-	tcpc_read(port, TCPC_REG_STATUS0, &status0);
-	/* write back original value */
-	tcpc_write(port, TCPC_REG_MEASURE, orig_reg);
-
-	mutex_unlock(&measure_lock);
-
-	return status0 & TCPC_REG_STATUS0_COMP;
-}
-
-int tcpc_get_vbus_voltage(int port)
-{
-	int mdac = 0, i;
-
-	/*
-	 * Implement by comparing VBUS with MDAC reference voltage, and binary
-	 * search the value of MDAC.
-	 *
-	 * MDAC register has 6 bits, so we can simply search 1 bit per
-	 * iteration, from MSB to LSB.
-	 */
-	for (i = 5; i >= 0; i--) {
-		if (fusb302_compare_mdac(port, mdac | BIT(i)))
-			mdac |= BIT(i);
-	}
-
-	return (mdac + 1) * 420;
-}
-
-const struct tcpm_drv fusb302_tcpm_drv = {
-	.init			= &fusb302_tcpm_init,
-	.release		= &fusb302_tcpm_release,
-	.get_cc			= &fusb302_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &fusb302_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &fusb302_tcpm_select_rp_value,
-	.set_cc			= &fusb302_tcpm_set_cc,
-	.set_polarity		= &fusb302_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &fusb302_tcpm_decode_sop_prime_enable,
-#endif
-	.set_vconn		= &fusb302_tcpm_set_vconn,
-	.set_msg_header		= &fusb302_tcpm_set_msg_header,
-	.set_rx_enable		= &fusb302_tcpm_set_rx_enable,
-	.get_message_raw	= &fusb302_tcpm_get_message_raw,
-	.transmit		= &fusb302_tcpm_transmit,
-	.tcpc_alert		= &fusb302_tcpc_alert,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &fusb302_tcpm_enter_low_power_mode,
-#endif
-};
diff --git a/driver/tcpm/fusb302.h b/driver/tcpm/fusb302.h
deleted file mode 100644
index 717b28df18..0000000000
--- a/driver/tcpm/fusb302.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Author: Gabe Noblesmith
- */
-
-/* USB Power delivery port management */
-/* For Fairchild FUSB302 */
-#ifndef __CROS_EC_DRIVER_TCPM_FUSB302_H
-#define __CROS_EC_DRIVER_TCPM_FUSB302_H
-
-/* Chip Device ID - 302A or 302B */
-#define FUSB302_DEVID_302A 0x08
-#define FUSB302_DEVID_302B 0x09
-
-/* I2C address varies by part number */
-/* FUSB302BUCX / FUSB302BMPX */
-#define FUSB302_I2C_ADDR_FLAGS 0x22
-/* FUSB302B01MPX */
-#define FUSB302_I2C_ADDR_B01_FLAGS 0x23
-/* FUSB302B10MPX */
-#define FUSB302_I2C_ADDR_B10_FLAGS 0x24
-/* FUSB302B11MPX */
-#define FUSB302_I2C_ADDR_B11_FLAGS 0x25
-
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
-/*
- * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
- * maximum error, which also matches suggested thresholds in datasheet
- * (Table 3. Host Interrupt Summary).
- */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
-/* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
-/* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
-/* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
-
-/* Tokens defined for the FUSB302 TX FIFO */
-enum fusb302_txfifo_tokens {
-	FUSB302_TKN_TXON = 0xA1,
-	FUSB302_TKN_SYNC1 = 0x12,
-	FUSB302_TKN_SYNC2 = 0x13,
-	FUSB302_TKN_SYNC3 = 0x1B,
-	FUSB302_TKN_RST1 = 0x15,
-	FUSB302_TKN_RST2 = 0x16,
-	FUSB302_TKN_PACKSYM = 0x80,
-	FUSB302_TKN_JAMCRC = 0xFF,
-	FUSB302_TKN_EOP = 0x14,
-	FUSB302_TKN_TXOFF = 0xFE,
-};
-
-extern const struct tcpm_drv fusb302_tcpm_drv;
-
-#endif /* __CROS_EC_DRIVER_TCPM_FUSB302_H */
diff --git a/driver/tcpm/fusb307.c b/driver/tcpm/fusb307.c
deleted file mode 100644
index e8804a2661..0000000000
--- a/driver/tcpm/fusb307.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Type-C port manager for Fairchild's FUSB307 */
-
-#include "console.h"
-#include "fusb307.h"
-#include "hooks.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int fusb307_power_supply_reset(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, 0x66);
-}
-
-static int fusb307_tcpm_init(int port)
-{
-	int rv;
-
-	rv = tcpci_tcpm_init(port);
-
-	rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, TYPEC_CC_RD);
-	pd_set_dual_role(port, PD_DRP_TOGGLE_ON);
-
-	return rv;
-}
-
-int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	int rv;
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	rv = tcpci_tcpm_set_polarity(port, polarity);
-
-	tcpm_get_cc(port, &cc1, &cc2);
-	if (cc1) {
-		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RD, TYPEC_CC_OPEN);
-
-			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RP, TYPEC_CC_OPEN);
-
-			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-		}
-	} else if (cc2) {
-		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RD);
-
-			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RP);
-
-			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-		}
-	} else {
-		if (pd_get_power_role(port) == PD_ROLE_SINK)
-			tcpci_tcpm_set_cc(port, TYPEC_CC_RD);
-		else
-			tcpci_tcpm_set_cc(port, TYPEC_CC_RP);
-	}
-
-	return rv;
-}
-
-const struct tcpm_drv fusb307_tcpm_drv = {
-	.init			= &fusb307_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &fusb307_tcpm_set_polarity,
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
-	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.get_chip_info		= &tcpci_get_chip_info,
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-};
-
diff --git a/driver/tcpm/fusb307.h b/driver/tcpm/fusb307.h
deleted file mode 100644
index 3f1f12901d..0000000000
--- a/driver/tcpm/fusb307.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-/* For Fairchild FUSB307 */
-#ifndef __CROS_EC_FUSB307_H
-#define __CROS_EC_FUSB307_H
-
-#include "usb_pd.h"
-
-#define FUSB307_I2C_ADDR_FLAGS 0x50
-
-#define TCPC_REG_RESET		0xA2
-#define TCPC_REG_RESET_PD_RESET	BIT(1)
-#define TCPC_REG_RESET_SW_RESET	BIT(0)
-
-#define TCPC_REG_GPIO1_CFG		0xA4
-#define TCPC_REG_GPIO1_CFG_GPO1_VAL	BIT(2)
-#define TCPC_REG_GPIO1_CFG_GPI1_EN	BIT(1)
-#define TCPC_REG_GPIO1_CFG_GPO1_EN	BIT(0)
-
-int fusb307_power_supply_reset(int port);
-
-extern const struct tcpm_drv fusb307_tcpm_drv;
-
-#endif /* __CROS_EC_FUSB307_H */
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c
deleted file mode 100644
index 7bd2913bd7..0000000000
--- a/driver/tcpm/it83xx.c
+++ /dev/null
@@ -1,910 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TCPM for MCU also running TCPC */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "it83xx_pd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "hooks.h"
-
-#ifdef CONFIG_USB_PD_TCPMV1
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT83xx PD driver"
-#endif
-#endif
-
-#ifdef CONFIG_USB_PD_TCPMV2
-#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT83xx PD driver"
-#endif
-#endif
-
-int rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
-STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
-
-const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
-};
-BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == IT83XX_USBPD_PHY_PORT_COUNT);
-
-static int it83xx_tcpm_set_rx_enable(int port, int enable);
-static int it83xx_tcpm_set_vconn(int port, int enable);
-
-/*
- * Disable cc analog and pd digital module, but only left Rd_5.1K (Not
- * Dead Battery) analog module alive to assert Rd on CCs. EC reset or
- * calling _init() are able to re-active cc and pd.
- */
-void it83xx_Rd_5_1K_only_for_hibernate(int port)
-{
-	/* This only apply to active PD port */
-	if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG &&
-		*usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
-		/* Disable PD PHY */
-		IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4));
-		/*
-		 * Disable CCs voltage detector, and
-		 * connect CCs analog module (ex.UP/RD/DET/TX/RX), and
-		 * connect CCs 5.1K to GND
-		 */
-		IT83XX_USBPD_CCCSR(port) = 0x22;
-		/* Disconnect CCs 5V tolerant */
-		IT83XX_USBPD_CCPSR(port) |=
-			(USBPD_REG_MASK_DISCONNECT_POWER_CC2 |
-			 USBPD_REG_MASK_DISCONNECT_POWER_CC1);
-		/*
-		 * Select Rp reserved value for not current leakage, and
-		 * CCs assert Rd, and
-		 * enable CCs analog module
-		 */
-		IT83XX_USBPD_BMCSR(port) &= ~0x08;
-		IT83XX_USBPD_CCGCR(port) &= ~0x1f;
-	}
-}
-
-static enum tcpc_cc_voltage_status it83xx_get_cc(
-	enum usbpd_port port,
-	enum usbpd_cc_pin cc_pin)
-{
-	enum usbpd_ufp_volt_status ufp_volt;
-	enum usbpd_dfp_volt_status dfp_volt;
-	enum tcpc_cc_voltage_status cc_state = TYPEC_CC_VOLT_OPEN;
-	int pull;
-
-	pull = (cc_pin == USBPD_CC_PIN_1) ?
-		USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) :
-		USBPD_GET_CC2_PULL_REGISTER_SELECTION(port);
-
-	/* select Rp */
-	if (pull)
-		CLEAR_MASK(cc_state, BIT(2));
-	/* select Rd */
-	else
-		SET_MASK(cc_state, BIT(2));
-
-	/* sink */
-	if (USBPD_GET_POWER_ROLE(port) == USBPD_POWER_ROLE_CONSUMER) {
-		if (cc_pin == USBPD_CC_PIN_1)
-			ufp_volt = IT83XX_USBPD_UFPVDR(port) & 0x7;
-		else
-			ufp_volt = (IT83XX_USBPD_UFPVDR(port) >> 4) & 0x7;
-
-		switch (ufp_volt) {
-		case USBPD_UFP_STATE_SNK_DEF:
-			cc_state |= (TYPEC_CC_VOLT_RP_DEF & 3);
-			break;
-		case USBPD_UFP_STATE_SNK_1_5:
-			cc_state |= (TYPEC_CC_VOLT_RP_1_5 & 3);
-			break;
-		case USBPD_UFP_STATE_SNK_3_0:
-			cc_state |= (TYPEC_CC_VOLT_RP_3_0 & 3);
-			break;
-		case USBPD_UFP_STATE_SNK_OPEN:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		default:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		}
-	/* source */
-	} else {
-		if (cc_pin == USBPD_CC_PIN_1)
-			dfp_volt = IT83XX_USBPD_DFPVDR(port) & 0xf;
-		else
-			dfp_volt = (IT83XX_USBPD_DFPVDR(port) >> 4) & 0xf;
-
-		switch (dfp_volt) {
-		case USBPD_DFP_STATE_SRC_RA:
-			cc_state |= TYPEC_CC_VOLT_RA;
-			break;
-		case USBPD_DFP_STATE_SRC_RD:
-			cc_state |= TYPEC_CC_VOLT_RD;
-			break;
-		case USBPD_DFP_STATE_SRC_OPEN:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		default:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		}
-	}
-
-	return cc_state;
-}
-
-static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
-{
-	int cnt = PD_HEADER_CNT(IT83XX_USBPD_RMH(port));
-
-	if (!USBPD_IS_RX_DONE(port))
-		return EC_ERROR_UNKNOWN;
-
-	/* store header */
-	*head = IT83XX_USBPD_RMH(port);
-	/* check data message */
-	if (cnt)
-		memcpy(buf, (uint32_t *)&IT83XX_USBPD_RDO0(port), cnt * 4);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		int type = USBPD_REG_GET_SOP_TYPE_RX(IT83XX_USBPD_MRSR(port));
-		*head |= PD_HEADER_SOP(type);
-	}
-	/*
-	 * Note: clear RX done interrupt after get the data.
-	 * If clear this bit, USBPD receives next packet
-	 */
-	IT83XX_USBPD_MRSR(port) = USBPD_REG_MASK_RX_MSG_VALID;
-
-	return EC_SUCCESS;
-}
-
-static enum tcpc_transmit_complete it83xx_tx_data(
-	enum usbpd_port port,
-	enum tcpci_msg_type type,
-	uint16_t header,
-	const uint32_t *buf)
-{
-	int r;
-	uint32_t evt;
-	uint8_t length = PD_HEADER_CNT(header);
-
-	/* set message header */
-	IT83XX_USBPD_TMHLR(port) = (uint8_t)header;
-	IT83XX_USBPD_TMHHR(port) = (header >> 8);
-
-	/*
-	 * SOP type bit[6~4]:
-	 * on bx version and before:
-	 * x00b=SOP, x01b=SOP', x10b=SOP", bit[6] is reserved.
-	 * on dx version:
-	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
-	 */
-	IT83XX_USBPD_MTSR1(port) =
-		(IT83XX_USBPD_MTSR1(port) & ~0x70) | ((type & 0x7) << 4);
-	/* bit7: transmit message is send to cable or not */
-	if (type == TCPCI_MSG_SOP)
-		IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE;
-	else
-		IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE;
-	/* clear msg length */
-	IT83XX_USBPD_MTSR1(port) &= (~0x7);
-	/* Limited by PD_HEADER_CNT() */
-	ASSERT(length <= 0x7);
-
-	if (length) {
-		/* set data bit */
-		IT83XX_USBPD_MTSR0(port) |= BIT(4);
-		/* set data length setting */
-		IT83XX_USBPD_MTSR1(port) |= length;
-		/* set data */
-		memcpy((uint32_t *)&IT83XX_USBPD_TDO(port), buf, length * 4);
-	}
-
-	for (r = 0; r <= CONFIG_PD_RETRY_COUNT; r++) {
-		/* Start TX */
-		USBPD_KICK_TX_START(port);
-		evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE,
-					PD_T_TCPC_TX_TIMEOUT);
-		/* check TX status */
-		if (USBPD_IS_TX_ERR(port) || (evt & TASK_EVENT_TIMER)) {
-			/*
-			 * If discard, means HW doesn't send the msg and resend.
-			 */
-			if (USBPD_IS_TX_DISCARD(port))
-				continue;
-			/*
-			 * Or port partner doesn't respond GoodCRC
-			 */
-			else
-				return TCPC_TX_COMPLETE_FAILED;
-		} else {
-			break;
-		}
-	}
-
-	if (r > CONFIG_PD_RETRY_COUNT)
-		return TCPC_TX_COMPLETE_DISCARDED;
-
-	return TCPC_TX_COMPLETE_SUCCESS;
-}
-
-static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port,
-				enum tcpci_msg_type reset_type)
-{
-	if (reset_type == TCPCI_MSG_CABLE_RESET)
-		IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE;
-	else
-		IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE;
-
-	/* send hard reset */
-	USBPD_SEND_HARD_RESET(port);
-	usleep(MSEC);
-
-	if (USBPD_IS_HARD_CABLE_RESET_TX_DONE(port)) {
-		IT83XX_USBPD_ISR(port) =
-			USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE;
-		return TCPC_TX_COMPLETE_SUCCESS;
-	}
-
-	return TCPC_TX_COMPLETE_FAILED;
-}
-
-static void it83xx_send_bist_mode2_pattern(enum usbpd_port port)
-{
-	USBPD_ENABLE_SEND_BIST_MODE_2(port);
-	usleep(PD_T_BIST_TRANSMIT);
-	USBPD_DISABLE_SEND_BIST_MODE_2(port);
-}
-
-static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
-{
-	enum usbpd_cc_pin cc_pin;
-
-	if (USBPD_GET_PULL_CC_SELECTION(port))
-		cc_pin = USBPD_CC_PIN_1;
-	else
-		cc_pin = USBPD_CC_PIN_2;
-
-	if (enabled) {
-		/* Disable unused CC to become VCONN */
-		if (cc_pin == USBPD_CC_PIN_1) {
-			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
-		} else {
-			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
-		}
-	} else {
-		/* Enable cc1 and cc2 */
-		IT83XX_USBPD_CCCSR(port) &= ~0xaa;
-		IT83XX_USBPD_CCPSR(port) |=
-			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
-	}
-}
-
-static void it83xx_enable_cc(enum usbpd_port port, int enable)
-{
-	if (enable)
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(4));
-	else
-		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(4));
-}
-
-static void it83xx_set_power_role(enum usbpd_port port, int power_role)
-{
-	/* PD_ROLE_SINK 0, PD_ROLE_SOURCE 1 */
-	if (power_role == PD_ROLE_SOURCE) {
-		/*
-		 * bit[2,3] BMC Rx threshold setting
-		 * 00b: power neutral
-		 * 01b: sinking power =>
-		 *      High to low Y3Rx threshold = 0.38,
-		 *      Low to high Y3Rx threshold = 0.54.
-		 * 10b: sourcing power =>
-		 *      High to low Y3Rx threshold = 0.64,
-		 *      Low to high Y3Rx threshold = 0.79.
-		 */
-		IT83XX_USBPD_CCADCR(port) = 0x08;
-		/* bit0: source */
-		SET_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
-		/* bit1: CC1 select Rp */
-		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(1));
-		/* bit3: CC2 select Rp */
-		SET_MASK(IT83XX_USBPD_BMCSR(port), BIT(3));
-	} else {
-		/*
-		 * bit[2,3] BMC Rx threshold setting
-		 * 00b: power neutral
-		 * 01b: sinking power =>
-		 *      High to low Y3Rx threshold = 0.38,
-		 *      Low to high Y3Rx threshold = 0.54
-		 * 10b: sourcing power =>
-		 *      High to low Y3Rx threshold = 0.64,
-		 *      Low to high Y3Rx threshold = 0.79
-		 */
-		IT83XX_USBPD_CCADCR(port) = 0x04;
-		/* bit0: sink */
-		CLEAR_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
-		/* bit1: CC1 select Rd */
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(1));
-		/* bit3: CC2 select Rd */
-		CLEAR_MASK(IT83XX_USBPD_BMCSR(port), BIT(3));
-	}
-}
-
-static void it83xx_set_data_role(enum usbpd_port port, int pd_role)
-{
-	/* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */
-	IT83XX_USBPD_PDMSR(port) =
-		(IT83XX_USBPD_PDMSR(port) & ~0xc) | ((pd_role & 0x1) << 2);
-}
-
-#ifdef CONFIG_USB_PD_FRS_TCPC
-static int it83xx_tcpm_set_frs_enable(int port, int enable)
-{
-	uint8_t mask = (USBPD_REG_FAST_SWAP_REQUEST_ENABLE |
-			USBPD_REG_FAST_SWAP_DETECT_ENABLE);
-
-	if (enable) {
-		/*
-		 * Disable HW auto turn off FRS requestion and detection
-		 * when we receive soft or hard reset.
-		 */
-		IT83XX_USBPD_PDPSR(port) &= ~USBPD_REG_MASK_AUTO_FRS_DISABLE;
-		/* W/C status */
-		IT83XX_USBPD_PD30IR(port) = 0x3f;
-		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) &= ~(USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
-		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDQSCR(port) = (IT83XX_USBPD_PDQSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
-	} else {
-		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) |= (USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
-		/* Disable FRS detection and requestion */
-		IT83XX_USBPD_PDQSCR(port) &= ~mask;
-	}
-
-	return EC_SUCCESS;
-}
-#endif
-
-static void it83xx_init(enum usbpd_port port, int role)
-{
-#ifdef IT83XX_USBPD_CC_PARAMETER_RELOAD
-	/* bit7: Reload CC parameter setting. */
-	IT83XX_USBPD_CCPSR0(port) |= BIT(7);
-#endif
-	/* reset and disable HW auto generate message header */
-	IT83XX_USBPD_GCR(port) = BIT(5);
-	USBPD_SW_RESET(port);
-	/*
-	 * According PD version set the total number of HW attempts
-	 * (= retry count + 1)
-	 */
-	IT83XX_USBPD_BMCSR(port) = (IT83XX_USBPD_BMCSR(port) & ~0x70) |
-					((CONFIG_PD_RETRY_COUNT + 1) << 4);
-	/* Disable Rx decode */
-	it83xx_tcpm_set_rx_enable(port, 0);
-	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) {
-		uint8_t flags = 0;
-		/*
-		 * If explicit contract is set in bbram when EC boot up, then
-		 * TCPMv1 set soft reset as first state instead of
-		 * unattached.SNK, so we need to enable BMC PHY for tx module.
-		 *
-		 * NOTE: If the platform is without battery and connects to
-		 * adapter, then cold reset EC, our Rd is always asserted on cc,
-		 * so adapter keeps providing 5v and data in BBRAM are still
-		 * alive.
-		 */
-		if ((pd_get_saved_port_flags(port, &flags) == EC_SUCCESS) &&
-		    (flags & PD_BBRMFLG_EXPLICIT_CONTRACT))
-			USBPD_ENABLE_BMC_PHY(port);
-	}
-	/* W/C status */
-	IT83XX_USBPD_ISR(port) = 0xff;
-	/* enable cc, select cc1 and Rd. */
-	IT83XX_USBPD_CCGCR(port) = 0xd;
-	/* change data role as the same power role */
-	it83xx_set_data_role(port, role);
-	/* set power role */
-	it83xx_set_power_role(port, role);
-	/* disable all interrupts */
-	IT83XX_USBPD_IMR(port) = 0xff;
-	/* enable tx done and reset detect interrupt */
-	IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE |
-					USBPD_REG_MASK_HARD_RESET_DETECT);
-#ifdef IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-	/*
-	 * when tcpc detect type-c plug in (cc lines voltage change), it will
-	 * interrupt fw to wake pd task, so task can react immediately.
-	 *
-	 * w/c status and unmask TCDCR (detect type-c plug in interrupt default
-	 * is enable).
-	 */
-	IT83XX_USBPD_TCDCR(port) = USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
-#endif
-	/* cc connect */
-	IT83XX_USBPD_CCCSR(port) = 0;
-	/* disable vconn */
-	it83xx_tcpm_set_vconn(port, 0);
-	/* TX start from high */
-	IT83XX_USBPD_CCADCR(port) |= BIT(6);
-	/* enable cc1/cc2 */
-	*usbpd_ctrl_regs[port].cc1 = IT83XX_USBPD_CC_PIN_CONFIG;
-	*usbpd_ctrl_regs[port].cc2 = IT83XX_USBPD_CC_PIN_CONFIG;
-	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
-	task_enable_irq(usbpd_ctrl_regs[port].irq);
-	USBPD_START(port);
-	/*
-	 * Disconnect CCs Rd_DB from GND
-	 * NOTE: CCs assert both Rd_5.1k and Rd_DB from USBPD_START() to
-	 *       disconnect Rd_DB about 1.5us.
-	 */
-	IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB |
-				     USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
-}
-
-static void it83xx_select_polarity(enum usbpd_port port,
-					enum usbpd_cc_pin cc_pin)
-{
-	/* cc1/cc2 selection */
-	if (cc_pin == USBPD_CC_PIN_1)
-		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(0));
-	else
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(0));
-}
-
-static int it83xx_set_cc(enum usbpd_port port, int pull)
-{
-	int enable_cc = 1;
-
-	switch (pull) {
-	case TYPEC_CC_RD:
-		it83xx_set_power_role(port, PD_ROLE_SINK);
-		break;
-	case TYPEC_CC_RP:
-		it83xx_set_power_role(port, PD_ROLE_SOURCE);
-		break;
-	case TYPEC_CC_OPEN:
-		/* Power-down CC1 & CC2 to remove Rp/Rd */
-		enable_cc = 0;
-		break;
-	default:
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	it83xx_enable_cc(port, enable_cc);
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_init(int port)
-{
-	/* Initialize physical layer */
-	it83xx_init(port, PD_ROLE_DEFAULT(port));
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_release(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static int it83xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	*cc2 = it83xx_get_cc(port, USBPD_CC_PIN_2);
-	*cc1 = it83xx_get_cc(port, USBPD_CC_PIN_1);
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_select_rp_value(int port, int rp_sel)
-{
-	uint8_t rp;
-
-	/* Keep track of current RP value */
-	tcpci_set_cached_rp(port, rp_sel);
-
-	/*
-	 * bit[3-2]: CC output current (when Rp selected)
-	 *       00: reserved
-	 *       01: 330uA outpt (3.0A)
-	 *       10: 180uA outpt (1.5A)
-	 *       11: 80uA outpt  (USB default)
-	 */
-	switch (rp_sel) {
-	case TYPEC_RP_1A5:
-		rp = 2 << 2;
-		break;
-	case TYPEC_RP_3A0:
-		rp = BIT(2);
-		break;
-	case TYPEC_RP_USB:
-	default:
-		rp = 3 << 2;
-		break;
-	}
-	IT83XX_USBPD_CCGCR(port) = (IT83XX_USBPD_CCGCR(port) & ~(3 << 2)) | rp;
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_set_cc(int port, int pull)
-{
-	return it83xx_set_cc(port, pull);
-}
-
-static int it83xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	enum usbpd_cc_pin cc_pin =
-		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
-
-	it83xx_select_polarity(port, cc_pin);
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int it83xx_tcpm_decode_sop_prime_enable(int port,
-							      bool enable)
-{
-	/* Save SOP'/SOP'' enable state */
-	sop_prime_en[port] = enable;
-
-	if (rx_en[port]) {
-		if (enable)
-			IT83XX_USBPD_PDMSR(port) |=
-				(USBPD_REG_MASK_SOPP_ENABLE |
-				 USBPD_REG_MASK_SOPPP_ENABLE);
-		else
-			IT83XX_USBPD_PDMSR(port) &=
-				~(USBPD_REG_MASK_SOPP_ENABLE |
-				  USBPD_REG_MASK_SOPPP_ENABLE);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_set_vconn(int port, int enable)
-{
-	/*
-	 * IT83XX doesn't have integrated circuit to source CC lines for VCONN.
-	 * An external device like PPC or Power Switch has to source the VCONN.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
-		if (enable) {
-			/*
-			 * Unused cc will become Vconn SRC, disable cc analog
-			 * module (ex.UP/RD/DET/Tx/Rx) and enable 5v tolerant.
-			 */
-			it83xx_enable_vconn(port, enable);
-			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Enable tcpc receive SOP' and SOP'' packet */
-				it83xx_tcpm_decode_sop_prime_enable(port, true);
-			/* Turn on Vconn power switch. */
-			board_pd_vconn_ctrl(port,
-					    USBPD_GET_PULL_CC_SELECTION(port) ?
-					    USBPD_CC_PIN_2 : USBPD_CC_PIN_1,
-					    enable);
-		} else {
-			/*
-			 * If the pd port has previous connection and supplies
-			 * Vconn, then RO jumping to RW reset the system,
-			 * we never know which cc is the previous Vconn pin,
-			 * so we always turn both cc pins off when disable
-			 * Vconn power switch.
-			 */
-			board_pd_vconn_ctrl(port, USBPD_CC_PIN_1, enable);
-			board_pd_vconn_ctrl(port, USBPD_CC_PIN_2, enable);
-			/* Disable tcpc receive SOP' and SOP'' packet */
-			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				it83xx_tcpm_decode_sop_prime_enable(port,
-								    false);
-			/*
-			 * Before disabling cc 5v tolerant, we need to make
-			 * sure cc voltage detector is enabled and Vconn is
-			 * dropped below 3.3v (>500us) to avoid the potential
-			 * risk of voltage fed back into Vcore.
-			 */
-			usleep(IT83XX_USBPD_T_VCONN_BELOW_3_3V);
-			/*
-			 * Since our cc are not Vconn SRC, enable cc analog
-			 * module (ex.UP/RD/DET/Tx/Rx) and disable 5v tolerant.
-			 */
-			it83xx_enable_vconn(port, enable);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	/* PD_ROLE_SINK 0, PD_ROLE_SOURCE 1 */
-	if (power_role == PD_ROLE_SOURCE)
-		/* bit0: source */
-		SET_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
-	else
-		/* bit0: sink */
-		CLEAR_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
-
-	it83xx_set_data_role(port, data_role);
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_set_rx_enable(int port, int enable)
-{
-	/* Save rx_on */
-	rx_en[port] = enable;
-
-	if (enable) {
-		IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE;
-		IT83XX_USBPD_PDMSR(port) |= USBPD_REG_MASK_SOP_ENABLE;
-		IT83XX_USBPD_VDMMCSR(port) |= USBPD_REG_MASK_HARD_RESET_DECODE;
-		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-			it83xx_tcpm_decode_sop_prime_enable(port,
-							    sop_prime_en[port]);
-	} else {
-		IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
-		IT83XX_USBPD_PDMSR(port) &= ~(USBPD_REG_MASK_SOP_ENABLE |
-					      USBPD_REG_MASK_SOPP_ENABLE |
-					      USBPD_REG_MASK_SOPPP_ENABLE);
-		IT83XX_USBPD_VDMMCSR(port) &= ~USBPD_REG_MASK_HARD_RESET_DECODE;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			const uint32_t *data)
-{
-	int status = TCPC_TX_COMPLETE_FAILED;
-
-	switch (type) {
-	case TCPCI_MSG_SOP:
-	case TCPCI_MSG_SOP_PRIME:
-	case TCPCI_MSG_SOP_PRIME_PRIME:
-	case TCPCI_MSG_SOP_DEBUG_PRIME:
-	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
-		status = it83xx_tx_data(port,
-					type,
-					header,
-					data);
-		break;
-	case TCPCI_MSG_TX_BIST_MODE_2:
-		it83xx_send_bist_mode2_pattern(port);
-		status = TCPC_TX_COMPLETE_SUCCESS;
-		break;
-	case TCPCI_MSG_TX_HARD_RESET:
-	case TCPCI_MSG_CABLE_RESET:
-		status = it83xx_send_hw_reset(port, type);
-		break;
-	default:
-		status = TCPC_TX_COMPLETE_FAILED;
-		break;
-	}
-	pd_transmit_complete(port, status);
-
-	return EC_SUCCESS;
-}
-
-static int it83xx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
-	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
-	chip_info->fw_version_number = 0xEC;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int it83xx_tcpm_enter_low_power_mode(int port)
-{
-	/*
-	 * ITE embedded TCPC SLEEP_MASK_USB_PD flag is only controlled by
-	 * it83xx driver in set_pd_sleep_mask(), and do low power mode in
-	 * idle_task().
-	 * In deep sleep mode, ITE TCPC clock is turned off, and the
-	 * timer every 5ms to exit the mode and wakeup PD task to run
-	 * (ex. change the CC lines termination).
-	 */
-	return EC_SUCCESS;
-}
-#endif
-
-static void it83xx_tcpm_switch_plug_out_type(int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	/* Check what do we and partner cc assert */
-	it83xx_tcpm_get_cc(port, &cc1, &cc2);
-
-	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
-	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
-		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
-	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
-		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
-	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
-		/*
-		 * We're sink, disable detect interrupt, so messages on cc line
-		 * won't trigger interrupt.
-		 * NOTE: Plug out is detected by TCPM polling Vbus.
-		 */
-		IT83XX_USBPD_TCDCR(port) |=
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE;
-	/*
-	 * If not above cases, plug in interrupt will fire again,
-	 * and call switch_plug_out_type() to set the right state.
-	 */
-}
-
-void switch_plug_out_type(enum usbpd_port port)
-{
-	it83xx_tcpm_switch_plug_out_type(port);
-}
-
-void set_pd_sleep_mask(int port)
-{
-	int i;
-	bool prevent_deep_sleep = false;
-
-	/*
-	 * Set SLEEP_MASK_USB_PD for deep sleep mode:
-	 * 1.Enable deep sleep mode, when all ITE ports are in Unattach.SRC/SNK
-	 *   state (HOOK_DISCONNECT called) and other ports aren't pd_capable().
-	 * 2.Disable deep sleep mode, when one of ITE port is in Attach.SRC/SNK
-	 *   state (HOOK_CONNECT called) or one of other ports is pd_capable().
-	 */
-	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
-		if (IT83XX_USBPD_GCR(i) & USBPD_REG_MASK_BMC_PHY) {
-			prevent_deep_sleep = true;
-			break;
-		}
-	}
-
-	/*
-	 * Check if any other ports have a PD port partner connected.  Deep
-	 * sleep is forbidden if any PD port partner is connected.  Above, we
-	 * only checked for the ITE ports.
-	 */
-	if (!prevent_deep_sleep) {
-		for (; i < board_get_usb_pd_port_count(); i++)
-			if (pd_capable(i))
-				prevent_deep_sleep = true;
-	}
-
-	if (prevent_deep_sleep)
-		disable_sleep(SLEEP_MASK_USB_PD);
-	else
-		enable_sleep(SLEEP_MASK_USB_PD);
-}
-
-static void it83xx_tcpm_hook_connect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-#ifdef CONFIG_USB_PD_TCPMV2
-	/*
-	 * There are five cases that hook_connect() be called by TCPMv2:
-	 * 1)AttachWait.SNK -> Attached.SNK: disable detect interrupt.
-	 * 2)AttachWait.SRC -> Attached.SRC: enable detect plug out.
-	 * 3)AttachWait.SNK -> Try.SRC -> TryWait.SNK -> Attached.SNK: we do
-	 *   Try.SRC fail, disable detect interrupt.
-	 * 4)AttachWait.SNK -> Try.SRC -> Attached.SRC: we do Try.SRC
-	 *   successfully, need to switch to detect plug out.
-	 * 5)Attached.SRC -> TryWait.SNK -> Attached.SNK: partner do Try.SRC
-	 *   successfully, disable detect interrupt.
-	 *
-	 * NOTE: Try.SRC and TryWait.SNK are embedded respectively in
-	 * SRC_DISCONNECT and SNK_DISCONNECT in TCPMv1. Every time we go to
-	 * Try.SRC/TryWait.SNK state, the plug in interrupt will be enabled and
-	 * fire for 3), 4), 5) cases, then set correctly for the SRC detect plug
-	 * out or the SNK disable detect, so TCPMv1 needn't this.
-	 */
-	it83xx_tcpm_switch_plug_out_type(port);
-#endif
-	/* Enable PD PHY Tx and Rx module since type-c has connected. */
-	USBPD_ENABLE_BMC_PHY(port);
-	set_pd_sleep_mask(port);
-}
-
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, it83xx_tcpm_hook_connect, HOOK_PRIO_DEFAULT);
-
-static void it83xx_tcpm_hook_disconnect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT))
-		/*
-		 * Switch to detect plug in and enable detect plug in interrupt,
-		 * since pd task has detected a type-c physical disconnected.
-		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
-
-	/* exit BIST test data mode */
-	USBPD_SW_RESET(port);
-
-	/*
-	 * Init rx status and disable PD PHY Tx and Rx module for better power
-	 * consumption since type-c has disconnected.
-	 */
-	rx_en[port] = 0;
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		sop_prime_en[port] = 0;
-	USBPD_DISABLE_BMC_PHY(port);
-	set_pd_sleep_mask(port);
-}
-
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_hook_disconnect,
-	     HOOK_PRIO_DEFAULT);
-
-const struct tcpm_drv it83xx_tcpm_drv = {
-	.init			= &it83xx_tcpm_init,
-	.release		= &it83xx_tcpm_release,
-	.get_cc			= &it83xx_tcpm_get_cc,
-	.select_rp_value	= &it83xx_tcpm_select_rp_value,
-	.set_cc			= &it83xx_tcpm_set_cc,
-	.set_polarity		= &it83xx_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &it83xx_tcpm_decode_sop_prime_enable,
-#endif
-	.set_vconn		= &it83xx_tcpm_set_vconn,
-	.set_msg_header		= &it83xx_tcpm_set_msg_header,
-	.set_rx_enable		= &it83xx_tcpm_set_rx_enable,
-	.get_message_raw	= &it83xx_tcpm_get_message_raw,
-	.transmit		= &it83xx_tcpm_transmit,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
-#endif
-	.get_chip_info		= &it83xx_tcpm_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it83xx_tcpm_enter_low_power_mode,
-#endif
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it83xx_tcpm_set_frs_enable,
-#endif
-};
diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h
deleted file mode 100644
index ff7c231f23..0000000000
--- a/driver/tcpm/it83xx_pd.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-#ifndef __CROS_EC_DRIVER_TCPM_IT83XX_H
-#define __CROS_EC_DRIVER_TCPM_IT83XX_H
-
-#include "driver/tcpm/it8xxx2_pd_public.h"
-
-/* USBPD Controller */
-#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define IT83XX_USBPD_BASE(port)   (0x00F03700 + (0x100 * (port)))
-
-#define IT83XX_USBPD_GCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_TYPE_C_DETECT_RESET        BIT(6)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(4)
-#define USBPD_REG_MASK_AUTO_SEND_SW_RESET         BIT(3)
-#define USBPD_REG_MASK_AUTO_SEND_HW_RESET         BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_GLOBAL_ENABLE              BIT(0)
-#define IT83XX_USBPD_PDMSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define USBPD_REG_MASK_SOPPP_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SOPP_ENABLE                BIT(6)
-#define USBPD_REG_MASK_SOP_ENABLE                 BIT(5)
-#define IT83XX_USBPD_CCGCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(4)
-#define IT83XX_USBPD_CCCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
-#define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
-#define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
-#ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    (BIT(5) | BIT(1))
-#else
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(1)
-#endif
-#define IT83XX_USBPD_CCPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_DFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define IT83XX_USBPD_UFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define IT83XX_USBPD_PDPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x0B)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(7)
-#define IT83XX_USBPD_CCADCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define IT83XX_USBPD_ISR(p)       REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_TYPE_C_DETECT              BIT(7)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE    BIT(3)
-#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE   BIT(2)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(1)
-#define USBPD_REG_MASK_TIMER_TIMEOUT              BIT(0)
-#define IT83XX_USBPD_IMR(p)       REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_SW_RESET_TX_STAT           BIT(3)
-#define USBPD_REG_MASK_TX_BUSY_STAT               BIT(2)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(2)
-#ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(5)
-#else
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(1)
-#endif
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)     REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define USBPD_REG_MASK_CABLE_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(6)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(5)
-#define IT83XX_USBPD_MTSR1(p)     REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define IT83XX_USBPD_VDMMCSR(p)   REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define USBPD_REG_MASK_HARD_RESET_DECODE          BIT(0)
-#define IT83XX_USBPD_MRSR(p)      REG8(IT83XX_USBPD_BASE(p)+0x1C)
-#define USBPD_REG_GET_SOP_TYPE_RX(mrsr)           (((mrsr) >> 4) & 0x7)
-#define USBPD_REG_MASK_RX_MSG_VALID               BIT(0)
-#define IT83XX_USBPD_PEFSMR(p)    REG8(IT83XX_USBPD_BASE(p)+0x1D)
-#define IT83XX_USBPD_PES0R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1E)
-#define IT83XX_USBPD_PES1R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1F)
-#define IT83XX_USBPD_TDO(p)       REG32(IT83XX_USBPD_BASE(p)+0x20)
-#define IT83XX_USBPD_AGTMHLR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3C)
-#define IT83XX_USBPD_AGTMHHR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3D)
-#define IT83XX_USBPD_TMHLR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3E)
-#define IT83XX_USBPD_TMHHR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3F)
-#define IT83XX_USBPD_RDO0(p)      REG32(IT83XX_USBPD_BASE(p)+0x40)
-#define IT83XX_USBPD_RMH(p)       REG16(IT83XX_USBPD_BASE(p)+0x5E)
-#define IT83XX_USBPD_CCPSR0(p)    REG8(IT83XX_USBPD_BASE(p)+0x60)
-#define IT83XX_USBPD_BMCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x64)
-#define IT83XX_USBPD_PDMHSR(p)    REG8(IT83XX_USBPD_BASE(p)+0x65)
-#define IT83XX_USBPD_TCDCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR      BIT(4)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_PDQSCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x70)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE     BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE      BIT(0)
-#define IT83XX_USBPD_PD30IR(p)    REG8(IT83XX_USBPD_BASE(p)+0x78)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT        BIT(4)
-#define IT83XX_USBPD_MPD30IR(p)   REG8(IT83XX_USBPD_BASE(p)+0x7A)
-#define USBPD_REG_MASK_PD30_ISR                BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR    BIT(4)
-
-#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define IT83XX_USBPD_BASE(port)     (0x00F03700 + (0x100 * (port) * (port)))
-
-#define IT83XX_USBPD_PDGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR       BIT(6)
-#define USBPD_REG_MASK_BIST_DATA_MODE             BIT(4)
-#define USBPD_REG_MASK_AUTO_BIST_RESPONSE         BIT(3)
-#define USBPD_REG_MASK_TX_MESSAGE_ENABLE          BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(0)
-#define IT83XX_USBPD_PDCSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define IT83XX_USBPD_PDMSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x02)
-#define USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER BIT(7)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(6)
-#define IT83XX_USBPD_PDCSR1(p)      REG8(IT83XX_USBPD_BASE(p)+0x03)
-#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE      BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE       BIT(5)
-#define USBPD_REG_MASK_SOPPP_RX_ENABLE            BIT(2)
-#define USBPD_REG_MASK_SOPP_RX_ENABLE             BIT(1)
-#define USBPD_REG_MASK_SOP_RX_ENABLE              BIT(0)
-#define IT83XX_USBPD_CCGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(7)
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(6)
-#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED      (BIT(3) | BIT(2) | BIT(1))
-#define USBPD_REG_MASK_CC_SELECT_RP_DEF           (BIT(3) | BIT(2))
-#define USBPD_REG_MASK_CC_SELECT_RP_1A5           BIT(3)
-#define USBPD_REG_MASK_CC_SELECT_RP_3A0           BIT(2)
-#define USBPD_REG_MASK_CC1_CC2_SELECTION          BIT(0)
-#define IT83XX_USBPD_CCCSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
-#define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
-#define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
-#ifdef IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       (BIT(1) | BIT(5))
-#else
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       BIT(1)
-#endif
-#define IT83XX_USBPD_CCPSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_SRCVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H     BIT(5)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H     BIT(1)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_SNKVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H     BIT(6)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M     BIT(5)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H     BIT(2)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M     BIT(1)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_PDFSCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE        BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE         BIT(0)
-#define IT83XX_USBPD_IFS(p)         REG8(IT83XX_USBPD_BASE(p)+0x12)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT           BIT(4)
-#define IT83XX_USBPD_MIFS(p)        REG8(IT83XX_USBPD_BASE(p)+0x13)
-#define USBPD_REG_MASK_FAST_SWAP_ISR              BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR       BIT(4)
-#define IT83XX_USBPD_ISR(p)         REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_TX_ERROR_STAT              BIT(3)
-#define USBPD_REG_MASK_CABLE_RESET_TX_DONE        BIT(2)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE         BIT(1)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(0)
-#define IT83XX_USBPD_IMR(p)         REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)        REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(7)
-#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT        BIT(6)
-#define USBPD_REG_MASK_TX_NOT_EN_STAT             BIT(5)
-#define USBPD_REG_MASK_CABLE_RESET                BIT(3)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(2)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(1)
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define IT83XX_USBPD_MHSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE         BIT(5)
-#define IT83XX_USBPD_MHSR1(p)       REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE        BIT(0)
-#define IT83XX_USBPD_TDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x22)
-#define IT83XX_USBPD_RMH(p)         REG16(IT83XX_USBPD_BASE(p)+0x42)
-#define IT83XX_USBPD_RDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x44)
-#define IT83XX_USBPD_BMCDR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x61)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC       BIT(5)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK       BIT(1)
-#define IT83XX_USBPD_TCDCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(6)
-#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE         BIT(5)
-#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE         BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_CCPSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x70)
-#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p)+0x73)
-#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p)+0x74)
-#endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
-
-/*
- * Dedicated setting for CC pin.
- * This setting will connect CC pin to internal PD module directly without
- * applying any GPIO/ALT configuration.
- */
-#define IT83XX_USBPD_CC_PIN_CONFIG  0x86
-#define IT83XX_USBPD_CC_PIN_CONFIG2 0x06
-
-/*
- * Before disabling cc 5v tolerant, we need to make sure cc voltage
- * detector is enabled and Vconn is dropped below 3.3v (>500us) to avoid
- * the potential risk of voltage fed back into Vcore.
- */
-#define IT83XX_USBPD_T_VCONN_BELOW_3_3V       500  /* us */
-
-#ifndef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   0
-#endif
-
-#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM_BIT(PD_EVENT_FIRST_FREE_BIT)
-
-#define SET_MASK(reg, bit_mask)      ((reg) |= (bit_mask))
-#define CLEAR_MASK(reg, bit_mask)    ((reg) &= (~(bit_mask)))
-#define IS_MASK_SET(reg, bit_mask)   (((reg) & (bit_mask)) != 0)
-#define IS_MASK_CLEAR(reg, bit_mask) (((reg) & (bit_mask)) == 0)
-
-#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-/* macros for set */
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_GCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTSR0(port), \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
-	(IT83XX_USBPD_PD30IR(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
-
-/* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_PDMSR(port) & 1)
-#define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_CCGCR(port) & BIT(1))
-#define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_BMCSR(port) & BIT(3))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & 1)
-
-/* macros for check */
-#define USBPD_IS_TX_ERR(port)       \
-	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_ERR_STAT)
-#define USBPD_IS_TX_DISCARD(port)   \
-	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_DISCARD_STAT)
-
-#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-/* macros for set */
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_PDGCR(port), \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SEND_CABLE_RESET(port)         \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_CABLE_RESET)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTCR(port),  \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
-	(IT83XX_USBPD_IFS(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
-	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
-
-/* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_MHSR1(port) & BIT(0))
-#define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_CCCSR(port) & BIT(1))
-#define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_CCCSR(port) & BIT(1))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & BIT(0))
-#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SNKVCRR(port) &               \
-		(USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SNKVCRR(port) &              \
-		(USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> 4)
-#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SRCVCRR(port) &               \
-		(USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SRCVCRR(port) &              \
-		(USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> 4)
-
-/* macros for check */
-#define USBPD_IS_TX_ERR(port)           \
-	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_TX_ERROR_STAT)
-#endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
-
-/* macros for PD ISR */
-#define USBPD_IS_HARD_RESET_DETECT(port) \
-	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT)
-#define USBPD_IS_HARD_CABLE_RESET_TX_DONE(port) \
-	IS_MASK_SET(IT83XX_USBPD_ISR(port),     \
-		USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE)
-#define USBPD_IS_TX_DONE(port)           \
-	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE)
-#define USBPD_IS_RX_DONE(port)           \
-	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_RX_DONE)
-#define USBPD_IS_PLUG_IN_OUT_DETECT(port)\
-	IS_MASK_SET(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_IN_OUT_DETECT_STAT)
-#define USBPD_IS_PLUG_IN(port)           \
-	IS_MASK_CLEAR(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_OUT_SELECT)
-#if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
-	IS_MASK_SET(IT83XX_USBPD_PD30IR(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
-#elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
-	IS_MASK_SET(IT83XX_USBPD_IFS(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
-#endif
-
-#if defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP) && defined(CONFIG_ZEPHYR)
-/* Use the Zephyr names here. When upstreaming we can update this */
-#include <dt-bindings/interrupt-controller/ite-intc.h>
-
-#define IT83XX_GPIO_GPCRF4	GPCRF4
-#define IT83XX_GPIO_GPCRF5	GPCRF5
-#define IT83XX_GPIO_GPCRH1	GPCRH1
-#define IT83XX_GPIO_GPCRH2	GPCRH2
-#define IT83XX_GPIO_GPCRP0	IT8XXX2_GPIO_GPCRP0
-#define IT83XX_GPIO_GPCRP1	IT8XXX2_GPIO_GPCRP1
-#define IT83XX_IRQ_USBPD0	IT8XXX2_IRQ_USBPD0
-#define IT83XX_IRQ_USBPD1	IT8XXX2_IRQ_USBPD1
-#define IT83XX_IRQ_USBPD2	IT8XXX2_IRQ_USBPD2
-#define USB_VID_ITE		0x048d
-
-/* ITE chip supports PD features */
-#define IT83XX_INTC_FAST_SWAP_SUPPORT
-#define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-#endif
-
-enum usbpd_port {
-	USBPD_PORT_A,
-	USBPD_PORT_B,
-	USBPD_PORT_C,
-};
-
-enum usbpd_ufp_volt_status {
-	USBPD_UFP_STATE_SNK_OPEN = 0,
-	USBPD_UFP_STATE_SNK_DEF  = 1,
-	USBPD_UFP_STATE_SNK_1_5  = 3,
-	USBPD_UFP_STATE_SNK_3_0  = 7,
-};
-
-enum usbpd_dfp_volt_status {
-	USBPD_DFP_STATE_SRC_RA   = 0,
-	USBPD_DFP_STATE_SRC_RD   = 1,
-	USBPD_DFP_STATE_SRC_OPEN = 3,
-};
-
-enum usbpd_power_role {
-	USBPD_POWER_ROLE_CONSUMER,
-	USBPD_POWER_ROLE_PROVIDER,
-	USBPD_POWER_ROLE_CONSUMER_PROVIDER,
-	USBPD_POWER_ROLE_PROVIDER_CONSUMER,
-};
-
-enum tuning_unit {
-	IT83XX_TX_PRE_DRIVING_TIME_DEFAULT,
-	IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-	IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-	IT83XX_TX_PRE_DRIVING_TIME_3_UNIT,
-};
-
-struct usbpd_ctrl_t {
-	volatile uint8_t *cc1;
-	volatile uint8_t *cc2;
-	uint8_t irq;
-};
-
-/* Data structure for board to adjust pd port rising and falling time */
-struct cc_para_t {
-	enum tuning_unit rising_time;
-	enum tuning_unit falling_time;
-};
-
-extern const struct usbpd_ctrl_t usbpd_ctrl_regs[];
-void it8xxx2_clear_tx_error_status(enum usbpd_port port);
-void it8xxx2_get_tx_error_status(enum usbpd_port port);
-void it83xx_Rd_5_1K_only_for_hibernate(int port);
-void switch_plug_out_type(enum usbpd_port port);
-/*
- * Board-level callback function to get cc tuning parameters
- * NOTE: board must define CONFIG_IT83XX_TUNE_CC_PHY
- */
-const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port);
-
-#endif /* __CROS_EC_DRIVER_TCPM_IT83XX_H */
diff --git a/driver/tcpm/it8xxx2.c b/driver/tcpm/it8xxx2.c
deleted file mode 100644
index dd5d1231fc..0000000000
--- a/driver/tcpm/it8xxx2.c
+++ /dev/null
@@ -1,968 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TCPM on ITE chip it8xxx2 with embedded TCPC */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "it83xx_pd.h"
-#include "ite_pd_intc.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_common.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "hooks.h"
-
-#ifdef CONFIG_USB_PD_TCPMV1
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT8xxx2 PD driver"
-#endif
-#endif
-
-#ifdef CONFIG_USB_PD_TCPMV2
-#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "Unsupported config options of IT8xxx2 PD driver"
-#endif
-#endif
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
-STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
-static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0};
-
-const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
-	{&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2},
-};
-BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);
-
-/*
- * Disable cc analog and pd digital module, but only left Rd_5.1K (Not
- * Rd_DB) analog module alive to assert Rd on CCs. EC reset or calling
- * _init() are able to re-active cc and pd.
- */
-void it83xx_Rd_5_1K_only_for_hibernate(int port)
-{
-	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
-
-	/* This only apply to active PD port */
-	if (*usbpd_ctrl_regs[port].cc1 == cc_config &&
-	    *usbpd_ctrl_regs[port].cc2 == cc_config) {
-		/* Disable PD Tx and Rx PHY */
-		IT83XX_USBPD_PDGCR(port) &= ~USBPD_REG_MASK_BMC_PHY;
-		/* Disable CCs voltage detector */
-		IT83XX_USBPD_CCGCR(port) |=
-			USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-		/* Select Rp reserved value for not current leakage */
-		IT83XX_USBPD_CCGCR(port) |=
-			USBPD_REG_MASK_CC_SELECT_RP_RESERVED;
-		/*
-		 * Connect CCs analog module (ex.UP/RD/DET/TX/RX), and
-		 * connect CCs 5.1K to GND, and
-		 * CCs assert Rd
-		 */
-		IT83XX_USBPD_CCCSR(port) &=
-			~(USBPD_REG_MASK_CC2_DISCONNECT |
-			  USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND |
-			  USBPD_REG_MASK_CC1_DISCONNECT |
-			  USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND |
-			  USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT);
-		/* Disconnect CCs 5V tolerant */
-		IT83XX_USBPD_CCPSR(port) |=
-			(USBPD_REG_MASK_DISCONNECT_POWER_CC2 |
-			 USBPD_REG_MASK_DISCONNECT_POWER_CC1);
-		/* Enable CCs analog module */
-		IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_DISABLE_CC;
-	}
-}
-
-static enum tcpc_cc_voltage_status it8xxx2_get_cc(enum usbpd_port port,
-						  enum usbpd_cc_pin cc_pin)
-{
-	enum usbpd_ufp_volt_status ufp_volt;
-	enum usbpd_dfp_volt_status dfp_volt;
-	enum tcpc_cc_voltage_status cc_state = TYPEC_CC_VOLT_OPEN;
-
-	/*
-	 * Because the message header bit(8) field has different definition
-	 * between SOP and SOP'/SOP'', in order to not happen misjudgement
-	 * when we receive SOP or SOP'/SOP'', the getting power role synchronize
-	 * with pd[port].power_role (also synchronization with tcpm_set_cc)
-	 * instead of message header.
-	 */
-	/* Sink */
-	if (pd_get_power_role(port) == PD_ROLE_SINK) {
-		if (cc_pin == USBPD_CC_PIN_1)
-			ufp_volt = USBPD_GET_SNK_COMPARE_CC1_VOLT(port);
-		else
-			ufp_volt = USBPD_GET_SNK_COMPARE_CC2_VOLT(port);
-
-		switch (ufp_volt) {
-		case USBPD_UFP_STATE_SNK_DEF:
-			cc_state = TYPEC_CC_VOLT_RP_DEF;
-			break;
-		case USBPD_UFP_STATE_SNK_1_5:
-			cc_state = TYPEC_CC_VOLT_RP_1_5;
-			break;
-		case USBPD_UFP_STATE_SNK_3_0:
-			cc_state = TYPEC_CC_VOLT_RP_3_0;
-			break;
-		case USBPD_UFP_STATE_SNK_OPEN:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		default:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		}
-	/* Source */
-	} else {
-		if (cc_pin == USBPD_CC_PIN_1)
-			dfp_volt = USBPD_GET_SRC_COMPARE_CC1_VOLT(port);
-		else
-			dfp_volt = USBPD_GET_SRC_COMPARE_CC2_VOLT(port);
-
-		switch (dfp_volt) {
-		case USBPD_DFP_STATE_SRC_RA:
-			cc_state = TYPEC_CC_VOLT_RA;
-			break;
-		case USBPD_DFP_STATE_SRC_RD:
-			cc_state = TYPEC_CC_VOLT_RD;
-			break;
-		case USBPD_DFP_STATE_SRC_OPEN:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		default:
-			cc_state = TYPEC_CC_VOLT_OPEN;
-			break;
-		}
-	}
-
-	return cc_state;
-}
-
-static int it8xxx2_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
-{
-	int cnt = PD_HEADER_CNT(IT83XX_USBPD_RMH(port));
-
-	if (!USBPD_IS_RX_DONE(port))
-		return EC_ERROR_UNKNOWN;
-
-	/* Store header */
-	*head = IT83XX_USBPD_RMH(port);
-
-	/*
-	 * BIT[6:4] SOP type of Rx message
-	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP"
-	 * 101b=HRDRST, 110b=CBLRST
-	 * 000b~100b is aligned to enum tcpci_msg_type.
-	 *
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		*head |= PD_HEADER_SOP((IT83XX_USBPD_MTSR0(port) >> 4) & 0x7);
-
-	/* Check data message */
-	if (cnt)
-		memcpy(buf, (uint32_t *)&IT83XX_USBPD_RDO(port), cnt * 4);
-
-	return EC_SUCCESS;
-}
-
-void it8xxx2_clear_tx_error_status(enum usbpd_port port)
-{
-	tx_error_status[port] = 0;
-}
-
-void it8xxx2_get_tx_error_status(enum usbpd_port port)
-{
-	tx_error_status[port] = IT83XX_USBPD_MTCR(port) &
-				(USBPD_REG_MASK_TX_NOT_EN_STAT |
-				 USBPD_REG_MASK_TX_DISCARD_STAT |
-				 USBPD_REG_MASK_TX_NO_RESPONSE_STAT);
-}
-
-static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port,
-						   enum tcpci_msg_type type,
-						   uint16_t header,
-						   const uint32_t *buf)
-{
-	int r;
-	uint32_t evt;
-	uint8_t length = PD_HEADER_CNT(header);
-
-	/* Set message header */
-	IT83XX_USBPD_MHSR0(port) = (uint8_t)header;
-	IT83XX_USBPD_MHSR1(port) = (header >> 8);
-
-	/*
-	 * Bit[2:0] Tx message type
-	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
-	 */
-	IT83XX_USBPD_MTSR0(port) =
-		(IT83XX_USBPD_MTSR0(port) & ~0x7) | (type & 0x7);
-
-	/* Limited by PD_HEADER_CNT() */
-	ASSERT(length <= 0x7);
-
-	if (length)
-		/* Set data */
-		memcpy((uint32_t *)&IT83XX_USBPD_TDO(port), buf, length * 4);
-
-	for (r = 0; r <= CONFIG_PD_RETRY_COUNT; r++) {
-		/* Start Tx */
-		USBPD_KICK_TX_START(port);
-		evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE,
-					   PD_T_TCPC_TX_TIMEOUT);
-
-		/*
-		 * Check Tx error status (TCPC won't set multi tx errors at one
-		 * time transmission):
-		 * 1) If we doesn't enable Tx.
-		 * 2) If discard, means HW doesn't send the msg and resend.
-		 * 3) If port partner doesn't respond GoodCRC.
-		 * 4) If Tx timeout.
-		 */
-		if (tx_error_status[port] || (evt & TASK_EVENT_TIMER)) {
-			if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NOT_EN_STAT) {
-				CPRINTS("p%d TxErr: Tx EN and resend", port);
-				tx_error_status[port] &=
-					~USBPD_REG_MASK_TX_NOT_EN_STAT;
-				IT83XX_USBPD_PDGCR(port) |=
-					USBPD_REG_MASK_TX_MESSAGE_ENABLE;
-				continue;
-			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_DISCARD_STAT) {
-				CPRINTS("p%d TxErr: Discard and resend", port);
-				tx_error_status[port] &=
-					~USBPD_REG_MASK_TX_DISCARD_STAT;
-				continue;
-			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NO_RESPONSE_STAT) {
-				/* HW had automatically resent message twice */
-				tx_error_status[port] &=
-					~USBPD_REG_MASK_TX_NO_RESPONSE_STAT;
-				return TCPC_TX_COMPLETE_FAILED;
-			} else if (evt & TASK_EVENT_TIMER) {
-				CPRINTS("p%d TxErr: Timeout", port);
-				return TCPC_TX_UNSET;
-			}
-		} else
-			break;
-	}
-
-	if (r > CONFIG_PD_RETRY_COUNT)
-		return TCPC_TX_COMPLETE_DISCARDED;
-
-	return TCPC_TX_COMPLETE_SUCCESS;
-}
-
-static enum tcpc_transmit_complete it8xxx2_send_hw_reset(enum usbpd_port port)
-{
-	/* Send hard reset */
-	USBPD_SEND_HARD_RESET(port);
-	usleep(MSEC);
-
-	if (!(IT83XX_USBPD_ISR(port) & USBPD_REG_MASK_HARD_RESET_TX_DONE))
-		return TCPC_TX_COMPLETE_FAILED;
-	IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_TX_DONE;
-
-	return TCPC_TX_COMPLETE_SUCCESS;
-}
-
-static enum tcpc_transmit_complete it8xxx2_send_cable_reset(
-						enum usbpd_port port)
-{
-	/* Send cable reset */
-	USBPD_SEND_CABLE_RESET(port);
-	usleep(MSEC);
-
-	if (!(IT83XX_USBPD_ISR(port) & USBPD_REG_MASK_CABLE_RESET_TX_DONE))
-		return TCPC_TX_COMPLETE_FAILED;
-	IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_CABLE_RESET_TX_DONE;
-
-	return TCPC_TX_COMPLETE_SUCCESS;
-}
-
-static void it8xxx2_send_bist_mode2_pattern(enum usbpd_port port)
-{
-	USBPD_ENABLE_SEND_BIST_MODE_2(port);
-	usleep(PD_T_BIST_TRANSMIT);
-	USBPD_DISABLE_SEND_BIST_MODE_2(port);
-}
-
-static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled)
-{
-	enum usbpd_cc_pin cc_pin;
-
-	if (USBPD_GET_PULL_CC_SELECTION(port))
-		cc_pin = USBPD_CC_PIN_1;
-	else
-		cc_pin = USBPD_CC_PIN_2;
-
-	if (enabled) {
-		/* Disable unused CC to become VCONN */
-		if (cc_pin == USBPD_CC_PIN_1) {
-			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
-		} else {
-			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
-		}
-	} else {
-		/* Connect cc analog module (ex.UP/RD/DET/TX/RX) */
-		IT83XX_USBPD_CCCSR(port) &= ~(USBPD_REG_MASK_CC2_DISCONNECT |
-					      USBPD_REG_MASK_CC1_DISCONNECT);
-		/* Disable cc 5v tolerant */
-		IT83XX_USBPD_CCPSR(port) |=
-			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
-	}
-}
-
-static void it8xxx2_enable_cc(enum usbpd_port port, int enable)
-{
-	if (enable)
-		IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_DISABLE_CC;
-	else
-		IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_DISABLE_CC;
-}
-
-static void it8xxx2_set_power_role(enum usbpd_port port, int power_role)
-{
-	/* 0: PD_ROLE_SINK, 1: PD_ROLE_SOURCE */
-	if (power_role == PD_ROLE_SOURCE) {
-		/*
-		 * Bit[0:6] BMC Rx threshold setting
-		 * 000 1000b: power neutral
-		 * 010 0000b: sinking power =>
-		 *      High to low Y3Rx threshold = 0.38,
-		 *      Low to high Y3Rx threshold = 0.54.
-		 * 000 0010b: sourcing power =>
-		 *      High to low Y3Rx threshold = 0.64,
-		 *      Low to high Y3Rx threshold = 0.79.
-		 */
-		IT83XX_USBPD_BMCDR0(port) = USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC;
-		/* Bit0: source */
-		IT83XX_USBPD_MHSR1(port) |= USBPD_REG_MASK_SOP_PORT_POWER_ROLE;
-		/* Bit1: CC1 and CC2 select Rp */
-		IT83XX_USBPD_CCCSR(port) |= USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT;
-	} else {
-		/*
-		 * Bit[0:6] BMC Rx threshold setting
-		 * 000 1000b: power neutral
-		 * 010 0000b: sinking power =>
-		 *      High to low Y3Rx threshold = 0.38,
-		 *      Low to high Y3Rx threshold = 0.54.
-		 * 000 0010b: sourcing power =>
-		 *      High to low Y3Rx threshold = 0.64,
-		 *      Low to high Y3Rx threshold = 0.79.
-		 */
-		IT83XX_USBPD_BMCDR0(port) = USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK;
-		/* Bit0: sink */
-		IT83XX_USBPD_MHSR1(port) &= ~USBPD_REG_MASK_SOP_PORT_POWER_ROLE;
-		/* Bit1: CC1 and CC2 select Rd */
-		IT83XX_USBPD_CCCSR(port) &=
-			~USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT;
-	}
-}
-
-static void it8xxx2_set_data_role(enum usbpd_port port, int data_role)
-{
-	/* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */
-	if (data_role == PD_ROLE_DFP)
-		/* Bit5: DFP */
-		IT83XX_USBPD_MHSR0(port) |= USBPD_REG_MASK_SOP_PORT_DATA_ROLE;
-	else
-		/* Bit5: UFP */
-		IT83XX_USBPD_MHSR0(port) &= ~USBPD_REG_MASK_SOP_PORT_DATA_ROLE;
-}
-
-static void it8xxx2_select_polarity(enum usbpd_port port,
-				    enum usbpd_cc_pin cc_pin)
-{
-	/* CC1/CC2 selection */
-	if (cc_pin == USBPD_CC_PIN_1)
-		IT83XX_USBPD_CCGCR(port) |= USBPD_REG_MASK_CC1_CC2_SELECTION;
-	else
-		IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_CC1_CC2_SELECTION;
-}
-
-static int it8xxx2_set_cc(enum usbpd_port port, int pull)
-{
-	int enable_cc = 1;
-
-	switch (pull) {
-	case TYPEC_CC_RD:
-		it8xxx2_set_power_role(port, PD_ROLE_SINK);
-		break;
-	case TYPEC_CC_RP:
-		it8xxx2_set_power_role(port, PD_ROLE_SOURCE);
-		break;
-	case TYPEC_CC_OPEN:
-		/* Power-down CC1 & CC2 to remove Rp/Rd */
-		enable_cc = 0;
-		break;
-	default:
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	it8xxx2_enable_cc(port, enable_cc);
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_release(int port)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static int it8xxx2_tcpm_get_cc(int port,
-			       enum tcpc_cc_voltage_status *cc1,
-			       enum tcpc_cc_voltage_status *cc2)
-{
-	*cc2 = it8xxx2_get_cc(port, USBPD_CC_PIN_2);
-	*cc1 = it8xxx2_get_cc(port, USBPD_CC_PIN_1);
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_select_rp_value(int port, int rp_sel)
-{
-	uint8_t rp;
-
-	/*
-	 * Bit[3-1]: CC output current (effective when Rp assert in 05h Bit[1])
-	 *       111: reserved
-	 *       010: 330uA outpt (3.0A)
-	 *       100: 180uA outpt (1.5A)
-	 *       110: 80uA outpt  (USB default)
-	 */
-	switch (rp_sel) {
-	case TYPEC_RP_1A5:
-		rp = USBPD_REG_MASK_CC_SELECT_RP_1A5;
-		break;
-	case TYPEC_RP_3A0:
-		rp = USBPD_REG_MASK_CC_SELECT_RP_3A0;
-		break;
-	case TYPEC_RP_USB:
-	default:
-		rp = USBPD_REG_MASK_CC_SELECT_RP_DEF;
-		break;
-	}
-	IT83XX_USBPD_CCGCR(port) = (IT83XX_USBPD_CCGCR(port) & ~(7 << 1)) | rp;
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_set_cc(int port, int pull)
-{
-	return it8xxx2_set_cc(port, pull);
-}
-
-static int it8xxx2_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	enum usbpd_cc_pin cc_pin =
-		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
-
-	it8xxx2_select_polarity(port, cc_pin);
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int it8xxx2_tcpm_decode_sop_prime_enable(int port,
-							       bool enable)
-{
-	/* Save SOP'/SOP'' enable state */
-	sop_prime_en[port] = enable;
-
-	if (!rx_en[port])
-		return EC_SUCCESS;
-
-	if (enable)
-		IT83XX_USBPD_PDCSR1(port) |=
-			(USBPD_REG_MASK_SOPP_RX_ENABLE |
-			 USBPD_REG_MASK_SOPPP_RX_ENABLE);
-	else
-		IT83XX_USBPD_PDCSR1(port) &=
-			~(USBPD_REG_MASK_SOPP_RX_ENABLE |
-			  USBPD_REG_MASK_SOPPP_RX_ENABLE);
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_set_vconn(int port, int enable)
-{
-	/*
-	 * IT8xxx2 doesn't have integrated circuit to source CC lines for VCONN.
-	 * An external device like PPC or Power Switch has to source the VCONN.
-	 */
-	if (IS_ENABLED(CONFIG_USBC_VCONN)) {
-		if (enable) {
-			/*
-			 * Unused cc will become Vconn SRC, disable cc analog
-			 * module (ex.UP/RD/DET/Tx/Rx) and enable 5v tolerant.
-			 */
-			it8xxx2_enable_vconn(port, enable);
-			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Enable tcpc receive SOP' and SOP'' packet */
-				it8xxx2_tcpm_decode_sop_prime_enable(port,
-								     true);
-			/* Turn on Vconn power switch. */
-			board_pd_vconn_ctrl(port,
-					    USBPD_GET_PULL_CC_SELECTION(port) ?
-					    USBPD_CC_PIN_2 : USBPD_CC_PIN_1,
-					    enable);
-		} else {
-			/*
-			 * If the pd port has previous connection and supplies
-			 * Vconn, then RO jumping to RW reset the system,
-			 * we never know which cc is the previous Vconn pin,
-			 * so we always turn both cc pins off when disable
-			 * Vconn power switch.
-			 */
-			board_pd_vconn_ctrl(port, USBPD_CC_PIN_1, enable);
-			board_pd_vconn_ctrl(port, USBPD_CC_PIN_2, enable);
-			if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-				/* Disable tcpc receive SOP' and SOP'' packet */
-				it8xxx2_tcpm_decode_sop_prime_enable(port,
-								     false);
-			/*
-			 * Before disabling cc 5v tolerant, we need to make
-			 * sure cc voltage detector is enabled and Vconn is
-			 * dropped below 3.3v (>500us) to avoid the potential
-			 * risk of voltage fed back into Vcore.
-			 */
-			usleep(IT83XX_USBPD_T_VCONN_BELOW_3_3V);
-			/*
-			 * Since our cc are not Vconn SRC, enable cc analog
-			 * module (ex.UP/RD/DET/Tx/Rx) and disable 5v tolerant.
-			 */
-			it8xxx2_enable_vconn(port, enable);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	/* 0: PD_ROLE_SINK, 1: PD_ROLE_SOURCE */
-	if (power_role == PD_ROLE_SOURCE)
-		/* Bit0: source */
-		IT83XX_USBPD_MHSR1(port) |= USBPD_REG_MASK_SOP_PORT_POWER_ROLE;
-	else
-		/* Bit0: sink */
-		IT83XX_USBPD_MHSR1(port) &= ~USBPD_REG_MASK_SOP_PORT_POWER_ROLE;
-
-	it8xxx2_set_data_role(port, data_role);
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_set_rx_enable(int port, int enable)
-{
-	/* Save rx_on */
-	rx_en[port] = !!enable;
-
-	if (enable) {
-		IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE;
-		IT83XX_USBPD_PDCSR1(port) |=
-				(USBPD_REG_MASK_SOP_RX_ENABLE |
-				 USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
-		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-			it8xxx2_tcpm_decode_sop_prime_enable(port,
-							sop_prime_en[port]);
-	} else {
-		IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
-		IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOP_RX_ENABLE |
-					USBPD_REG_MASK_SOPP_RX_ENABLE |
-					USBPD_REG_MASK_SOPPP_RX_ENABLE |
-					USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_transmit(int port,
-				 enum tcpci_msg_type type,
-				 uint16_t header,
-				 const uint32_t *data)
-{
-	int status = TCPC_TX_COMPLETE_FAILED;
-
-	switch (type) {
-	case TCPCI_MSG_SOP:
-	case TCPCI_MSG_SOP_PRIME:
-	case TCPCI_MSG_SOP_PRIME_PRIME:
-	case TCPCI_MSG_SOP_DEBUG_PRIME:
-	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
-		status = it8xxx2_tx_data(port,
-					 type,
-					 header,
-					 data);
-		break;
-	case TCPCI_MSG_TX_BIST_MODE_2:
-		it8xxx2_send_bist_mode2_pattern(port);
-		status = TCPC_TX_COMPLETE_SUCCESS;
-		break;
-	case TCPCI_MSG_TX_HARD_RESET:
-		status = it8xxx2_send_hw_reset(port);
-		break;
-	case TCPCI_MSG_CABLE_RESET:
-		status = it8xxx2_send_cable_reset(port);
-		break;
-	default:
-		status = TCPC_TX_COMPLETE_FAILED;
-		break;
-	}
-	pd_transmit_complete(port, status);
-
-	return EC_SUCCESS;
-}
-
-static int it8xxx2_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
-	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
-	chip_info->fw_version_number = 0xEC;
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int it8xxx2_tcpm_enter_low_power_mode(int port)
-{
-	/*
-	 * ITE embedded TCPC SLEEP_MASK_USB_PD flag is only controlled by
-	 * it8xxx2 driver in it8xxx2_set_pd_sleep_mask(), and do low power
-	 * mode in idle_task().
-	 * In deep sleep mode, ITE TCPC clock is turned off, and the
-	 * timer every 5ms to exit the mode and wakeup PD task to run
-	 * (ex. change the CC lines termination).
-	 */
-	return EC_SUCCESS;
-}
-#endif
-
-#ifdef CONFIG_USB_PD_FRS_TCPC
-static int it8xxx2_tcpm_set_frs_enable(int port, int enable)
-{
-	uint8_t mask = (USBPD_REG_FAST_SWAP_REQUEST_ENABLE |
-			USBPD_REG_FAST_SWAP_DETECT_ENABLE);
-
-	if (enable) {
-		/*
-		 * Disable HW auto turn off FRS requestion and detection
-		 * when we receive soft or hard reset.
-		 */
-		IT83XX_USBPD_PDMSR(port) &= ~USBPD_REG_MASK_AUTO_FRS_DISABLE;
-		/* W/C status */
-		IT83XX_USBPD_IFS(port) = 0x33;
-		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) &= ~(USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
-		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDFSCR(port)  = (IT83XX_USBPD_PDFSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
-		/*
-		 * TODO(b/160210457): Enable HW auto trigger
-		 * GPH3(port0)/GPH4(port1) output H/L after we detect FRS cc
-		 * low signal.
-		 */
-	} else {
-		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) |= (USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
-		/* Disable FRS detection and requestion */
-		IT83XX_USBPD_PDFSCR(port) &= ~mask;
-		/*
-		 * TODO(b/160210457): Disable HW auto trigger
-		 * GPH3(port0)/GPH4(port1) output H/L after we detect FRS cc
-		 * low signal.
-		 */
-	}
-
-	return EC_SUCCESS;
-}
-#endif
-
-static void it8xxx2_tcpm_switch_plug_out_type(int port)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	/* Check what do we and partner cc assert */
-	it8xxx2_tcpm_get_cc(port, &cc1, &cc2);
-
-	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
-	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
-		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
-	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
-		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
-	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
-		/*
-		 * We're sink, disable detect interrupt, so messages on cc line
-		 * won't trigger interrupt.
-		 * NOTE: Plug out is detected by TCPM polling Vbus.
-		 */
-		IT83XX_USBPD_TCDCR(port) |=
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE;
-	/*
-	 * If not above cases, plug in interrupt will fire again,
-	 * and call switch_plug_out_type() to set the right state.
-	 */
-}
-
-void switch_plug_out_type(enum usbpd_port port)
-{
-	it8xxx2_tcpm_switch_plug_out_type(port);
-}
-
-static void it8xxx2_init(enum usbpd_port port, int role)
-{
-	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
-
-	if (IS_ENABLED(CONFIG_IT83XX_TUNE_CC_PHY)) {
-		/* Tune cc Tx pre-driving time */
-		const struct cc_para_t *ptr =
-			board_get_cc_tuning_parameter(port);
-
-		IT83XX_USBPD_CCPSR3_RISE(port) = ptr->rising_time;
-		IT83XX_USBPD_CCPSR4_FALL(port) = ptr->falling_time;
-	}
-	/* Reset and disable HW auto generate message header */
-	IT83XX_USBPD_PDMSR(port) &= ~USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER;
-	USBPD_SW_RESET(port);
-	/* According PD version set HW auto retry count */
-	IT83XX_USBPD_PDCSR0(port) = (IT83XX_USBPD_PDCSR0(port) & ~0xC0) |
-					(CONFIG_PD_RETRY_COUNT << 6);
-	/* Disable Rx decode */
-	it8xxx2_tcpm_set_rx_enable(port, 0);
-	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) {
-		uint8_t flags = 0;
-		/*
-		 * If explicit contract is set in bbram when EC boot up, then
-		 * TCPMv1 set soft reset as first state instead of
-		 * unattached.SNK, so we need to enable BMC PHY for tx module.
-		 *
-		 * NOTE: If the platform is without battery and connects to
-		 * adapter, then cold reset EC, our Rd is always asserted on cc,
-		 * so adapter keeps providing 5v and data in BBRAM are still
-		 * alive.
-		 */
-		if ((pd_get_saved_port_flags(port, &flags) == EC_SUCCESS) &&
-		    (flags & PD_BBRMFLG_EXPLICIT_CONTRACT))
-			USBPD_ENABLE_BMC_PHY(port);
-	}
-	/* Disable all interrupts */
-	IT83XX_USBPD_IMR(port) = 0xff;
-	/* W/C status */
-	IT83XX_USBPD_ISR(port) = 0xff;
-	/* Enable cc voltage detector */
-	IT83XX_USBPD_CCGCR(port) &= ~USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR;
-	/* Select Rp value USB-DEFAULT (Rd value default connect with 5.1k) */
-	it8xxx2_tcpm_select_rp_value(port, TYPEC_RP_USB);
-	/* Which cc pin connect in attached state. Default to cc1  */
-	it8xxx2_select_polarity(port, USBPD_CC_PIN_1);
-	/* Change data role as the same power role */
-	it8xxx2_set_data_role(port, role);
-	/* Set default power role and assert Rp/Rd */
-	it8xxx2_set_power_role(port, role);
-	/* Disable vconn: connect cc analog module, disable cc 5v tolerant */
-	it8xxx2_tcpm_set_vconn(port, 0);
-	/* Enable tx done and hard reset detect interrupt */
-	IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE |
-				    USBPD_REG_MASK_HARD_RESET_DETECT);
-#ifdef IT83XX_INTC_PLUG_IN_OUT_SUPPORT
-	/*
-	 * When tcpc detect type-c plug in (cc lines voltage change), it will
-	 * interrupt fw to wake pd task, so task can react immediately.
-	 *
-	 * W/C status and enable type-c plug-in detect interrupt.
-	 */
-	IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				    ~(USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE |
-				      USBPD_REG_PLUG_OUT_SELECT)) |
-				    USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
-#endif
-	/* Set cc1/cc2 pins alternate mode */
-	*usbpd_ctrl_regs[port].cc1 = cc_config;
-	*usbpd_ctrl_regs[port].cc2 = cc_config;
-	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
-#ifdef CONFIG_ZEPHYR
-	irq_connect_dynamic(usbpd_ctrl_regs[port].irq, 0,
-			(void (*)(const void *))chip_pd_irq, (void *)port, 0);
-#endif
-	task_enable_irq(usbpd_ctrl_regs[port].irq);
-	USBPD_START(port);
-	/*
-	 * Disconnect CCs Rd_DB from GND
-	 * NOTE: CCs assert both Rd_5.1k and Rd_DB from USBPD_START() to
-	 *       disconnect Rd_DB about 1.5us.
-	 */
-	IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB |
-				     USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB);
-}
-
-static int it8xxx2_tcpm_init(int port)
-{
-	/* Initialize physical layer */
-	it8xxx2_init(port, PD_ROLE_DEFAULT(port));
-
-	return EC_SUCCESS;
-}
-
-static void it8xxx2_set_pd_sleep_mask(int port)
-{
-	int i;
-	bool prevent_deep_sleep = false;
-
-	/*
-	 * Set SLEEP_MASK_USB_PD for deep sleep mode:
-	 * 1.Enable deep sleep mode, when all ITE ports are in Unattach.SRC/SNK
-	 *   state (HOOK_DISCONNECT called) and other ports aren't pd_capable().
-	 * 2.Disable deep sleep mode, when one of ITE port is in Attach.SRC/SNK
-	 *   state (HOOK_CONNECT called) or one of other ports is pd_capable().
-	 */
-	for (i = 0; i < CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT; ++i) {
-		if (IT83XX_USBPD_PDGCR(i) & USBPD_REG_MASK_BMC_PHY) {
-			prevent_deep_sleep = true;
-			break;
-		}
-	}
-
-	/*
-	 * Check if any other ports have a PD port partner connected.  Deep
-	 * sleep is forbidden if any PD port partner is connected.  Above, we
-	 * only checked for the ITE ports.
-	 */
-	if (!prevent_deep_sleep) {
-		for (; i < board_get_usb_pd_port_count(); i++)
-			if (pd_capable(i))
-				prevent_deep_sleep = true;
-	}
-
-	if (prevent_deep_sleep)
-		disable_sleep(SLEEP_MASK_USB_PD);
-	else
-		enable_sleep(SLEEP_MASK_USB_PD);
-}
-
-static void it8xxx2_tcpm_hook_connect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-#ifdef CONFIG_USB_PD_TCPMV2
-	/*
-	 * There are five cases that hook_connect() be called by TCPMv2:
-	 * 1)AttachWait.SNK -> Attached.SNK: disable detect interrupt.
-	 * 2)AttachWait.SRC -> Attached.SRC: enable detect plug out.
-	 * 3)AttachWait.SNK -> Try.SRC -> TryWait.SNK -> Attached.SNK: we do
-	 *   Try.SRC fail, disable detect interrupt.
-	 * 4)AttachWait.SNK -> Try.SRC -> Attached.SRC: we do Try.SRC
-	 *   successfully, need to switch to detect plug out.
-	 * 5)Attached.SRC -> TryWait.SNK -> Attached.SNK: partner do Try.SRC
-	 *   successfully, disable detect interrupt.
-	 *
-	 * NOTE: Try.SRC and TryWait.SNK are embedded respectively in
-	 * SRC_DISCONNECT and SNK_DISCONNECT in TCPMv1. Every time we go to
-	 * Try.SRC/TryWait.SNK state, the plug in interrupt will be enabled and
-	 * fire for 3), 4), 5) cases, then set correctly for the SRC detect plug
-	 * out or the SNK disable detect, so TCPMv1 needn't this.
-	 */
-	it8xxx2_tcpm_switch_plug_out_type(port);
-#endif
-	/* Enable PD PHY Tx and Rx module since type-c has connected. */
-	USBPD_ENABLE_BMC_PHY(port);
-	it8xxx2_set_pd_sleep_mask(port);
-}
-
-DECLARE_HOOK(HOOK_USB_PD_CONNECT, it8xxx2_tcpm_hook_connect, HOOK_PRIO_DEFAULT);
-
-static void it8xxx2_tcpm_hook_disconnect(void)
-{
-	int port = TASK_ID_TO_PD_PORT(task_get_current());
-
-	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT))
-		/*
-		 * Switch to detect plug in and enable detect plug in interrupt,
-		 * since pd task has detected a type-c physical disconnected.
-		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
-
-	/* Exit BIST test data mode */
-	USBPD_SW_RESET(port);
-
-	/*
-	 * Init rx status and disable PD PHY Tx and Rx module for better power
-	 * consumption since type-c has disconnected.
-	 */
-	rx_en[port] = 0;
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		sop_prime_en[port] = 0;
-	USBPD_DISABLE_BMC_PHY(port);
-	it8xxx2_set_pd_sleep_mask(port);
-}
-
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it8xxx2_tcpm_hook_disconnect,
-	     HOOK_PRIO_DEFAULT);
-
-const struct tcpm_drv it8xxx2_tcpm_drv = {
-	.init			= &it8xxx2_tcpm_init,
-	.release		= &it8xxx2_tcpm_release,
-	.get_cc			= &it8xxx2_tcpm_get_cc,
-	.select_rp_value	= &it8xxx2_tcpm_select_rp_value,
-	.set_cc			= &it8xxx2_tcpm_set_cc,
-	.set_polarity		= &it8xxx2_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &it8xxx2_tcpm_decode_sop_prime_enable,
-#endif
-	.set_vconn		= &it8xxx2_tcpm_set_vconn,
-	.set_msg_header		= &it8xxx2_tcpm_set_msg_header,
-	.set_rx_enable		= &it8xxx2_tcpm_set_rx_enable,
-	.get_message_raw	= &it8xxx2_tcpm_get_message_raw,
-	.transmit		= &it8xxx2_tcpm_transmit,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
-#endif
-	.get_chip_info		= &it8xxx2_tcpm_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it8xxx2_tcpm_enter_low_power_mode,
-#endif
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it8xxx2_tcpm_set_frs_enable,
-#endif
-};
diff --git a/driver/tcpm/ite_pd_intc.c b/driver/tcpm/ite_pd_intc.c
deleted file mode 100644
index 2b5a391dfe..0000000000
--- a/driver/tcpm/ite_pd_intc.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "it83xx_pd.h"
-#include "ite_pd_intc.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-
-void chip_pd_irq(enum usbpd_port port)
-{
-	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
-
-	/* check status */
-	if (IS_ENABLED(IT83XX_INTC_FAST_SWAP_SUPPORT) &&
-		IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
-		IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		/*
-		 * FRS detection must handle first, because we need to short
-		 * the interrupt -> board_frs_handler latency-critical time.
-		 */
-		if (USBPD_IS_FAST_SWAP_DETECT(port)) {
-			/* clear detect FRS signal (cc to GND) status */
-			USBPD_CLEAR_FRS_DETECT_STATUS(port);
-			if (board_frs_handler)
-				board_frs_handler(port);
-			/* inform TCPMv2 to change state */
-			pd_got_frs_signal(port);
-		}
-	}
-
-	if (USBPD_IS_HARD_RESET_DETECT(port)) {
-		/* clear interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_DETECT;
-		USBPD_SW_RESET(port);
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_RX_HARD_RESET);
-	}
-
-	if (USBPD_IS_RX_DONE(port)) {
-		tcpm_enqueue_message(port);
-		/* clear RX done interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_RX_DONE;
-	}
-
-	if (USBPD_IS_TX_DONE(port)) {
-#ifdef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-		it8xxx2_clear_tx_error_status(port);
-		/* check TX status, clear by TX_DONE status too */
-		if (USBPD_IS_TX_ERR(port))
-			it8xxx2_get_tx_error_status(port);
-#endif
-		/* clear TX done interrupt */
-		IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_TX_DONE;
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       TASK_EVENT_PHY_TX_DONE);
-	}
-
-	if (IS_ENABLED(IT83XX_INTC_PLUG_IN_OUT_SUPPORT)) {
-		if (USBPD_IS_PLUG_IN_OUT_DETECT(port)) {
-			if (USBPD_IS_PLUG_IN(port))
-				/*
-				 * When tcpc detect type-c plug in:
-				 * 1)If we are sink, disable detect interrupt,
-				 * messages on cc line won't trigger interrupt.
-				 * 2)If we are source, then set plug out
-				 * detection.
-				 */
-				switch_plug_out_type(port);
-			else
-				/*
-				 * When tcpc detect type-c plug out:
-				 * switch to detect plug in.
-				 */
-				IT83XX_USBPD_TCDCR(port) &=
-					~USBPD_REG_PLUG_OUT_SELECT;
-
-			/* clear type-c device plug in/out detect interrupt */
-			IT83XX_USBPD_TCDCR(port) |=
-				USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
-			task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-		}
-	}
-}
diff --git a/driver/tcpm/ite_pd_intc.h b/driver/tcpm/ite_pd_intc.h
deleted file mode 100644
index 8123e1a233..0000000000
--- a/driver/tcpm/ite_pd_intc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ITE PD INTC control module */
-
-#ifndef __CROS_EC_ITE_PD_INTC_H
-#define __CROS_EC_ITE_PD_INTC_H
-
-/**
- * ITE embedded PD interrupt routine
- *
- * NOTE: Enable ITE embedded PD that it requires CONFIG_USB_PD_TCPM_ITE_ON_CHIP
- *
- * @param port Type-C port number
- *
- * @return none
- */
-void chip_pd_irq(enum usbpd_port port);
-
-#endif /* __CROS_EC_ITE_PD_INTC_H */
diff --git a/driver/tcpm/mt6370.c b/driver/tcpm/mt6370.c
deleted file mode 100644
index 100a4d9eeb..0000000000
--- a/driver/tcpm/mt6370.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MT6370 TCPC Driver
- */
-
-#include "console.h"
-#include "hooks.h"
-#include "mt6370.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static int mt6370_polarity;
-
-/* i2c_write function which won't wake TCPC from low power mode. */
-static int mt6370_i2c_write8(int port, int reg, int val)
-{
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-			  tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static int mt6370_init(int port)
-{
-	int rv, val;
-
-	rv = tcpc_read(port, MT6370_REG_IDLE_CTRL, &val);
-
-	/* Only do soft-reset in shipping mode. (b:122017882) */
-	if (!(val & MT6370_REG_SHIPPING_OFF)) {
-
-		/* Software reset. */
-		rv = tcpc_write(port, MT6370_REG_SWRESET, 1);
-		if (rv)
-			return rv;
-
-		/* Need 1 ms for software reset. */
-		msleep(1);
-	}
-
-	/* The earliest point that we can do generic init. */
-	rv = tcpci_tcpm_init(port);
-
-	if (rv)
-		return rv;
-
-	/*
-	 * AUTO IDLE off, shipping off, select CK_300K from BICIO_320K,
-	 * PD3.0 ext-msg on.
-	 */
-	rv = tcpc_write(port, MT6370_REG_IDLE_CTRL,
-			MT6370_REG_IDLE_SET(0, 1, 0, 0));
-	/* CC Detect Debounce 5 */
-	rv |= tcpc_write(port, MT6370_REG_TTCPC_FILTER, 5);
-	/* DRP Duty */
-	rv |= tcpc_write(port, MT6370_REG_DRP_TOGGLE_CYCLE, 4);
-	rv |= tcpc_write16(port, MT6370_REG_DRP_DUTY_CTRL, 400);
-	/* Vconn OC on */
-	rv |= tcpc_write(port, MT6370_REG_VCONN_CLIMITEN, 1);
-	/* PHY control */
-	rv |= tcpc_write(port, MT6370_REG_PHY_CTRL1,
-			 MT6370_REG_PHY_CTRL1_SET(0, 7, 0, 1));
-	rv |= tcpc_write(port, MT6370_REG_PHY_CTRL3, 0x82);
-
-	return rv;
-}
-
-static inline int mt6370_init_cc_params(int port, int cc_res)
-{
-	int rv, en, sel;
-
-	if (cc_res == TYPEC_CC_VOLT_RP_DEF) { /* RXCC threshold : 0.55V */
-		en = 1;
-		sel = MT6370_OCCTRL_600MA | MT6370_MASK_BMCIO_RXDZSEL;
-	} else { /* RD threshold : 0.4V & RP threshold : 0.7V */
-		en = 0;
-		sel = MT6370_OCCTRL_600MA;
-	}
-	rv = tcpc_write(port, MT6370_REG_BMCIO_RXDZEN, en);
-	if (!rv)
-		rv = tcpc_write(port, MT6370_REG_BMCIO_RXDZSEL, sel);
-	return rv;
-}
-
-static int mt6370_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int status;
-	int rv;
-	int role, is_snk;
-
-	rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status);
-
-	/* If tcpc read fails, return error and CC as open */
-	if (rv) {
-		*cc1 = TYPEC_CC_VOLT_OPEN;
-		*cc2 = TYPEC_CC_VOLT_OPEN;
-		return rv;
-	}
-
-	*cc1 = TCPC_REG_CC_STATUS_CC1(status);
-	*cc2 = TCPC_REG_CC_STATUS_CC2(status);
-
-	/*
-	 * If status is not open, then OR in termination to convert to
-	 * enum tcpc_cc_voltage_status.
-	 *
-	 * MT6370 TCPC follows USB PD 1.0 protocol. When DRP not auto-toggling,
-	 * it will not update the DRP_RESULT bits in TCPC_REG_CC_STATUS,
-	 * instead, we should check CC1/CC2 bits in TCPC_REG_ROLE_CTRL.
-	 */
-	rv = tcpc_read(port, TCPC_REG_ROLE_CTRL, &role);
-
-	if (TCPC_REG_ROLE_CTRL_DRP(role))
-		is_snk = TCPC_REG_CC_STATUS_TERM(status);
-	else
-		/* CC1/CC2 states are the same, checking one-side is enough. */
-		is_snk = TCPC_REG_CC_STATUS_CC1(role) == TYPEC_CC_RD;
-
-	if (is_snk) {
-		if (*cc1 != TYPEC_CC_VOLT_OPEN)
-			*cc1 |= 0x04;
-		if (*cc2 != TYPEC_CC_VOLT_OPEN)
-			*cc2 |= 0x04;
-	}
-
-	rv = mt6370_init_cc_params(port, (int)mt6370_polarity ? *cc1 : *cc2);
-	return rv;
-}
-
-static int mt6370_set_cc(int port, int pull)
-{
-	if (pull == TYPEC_CC_RD)
-		mt6370_init_cc_params(port, TYPEC_CC_VOLT_RP_DEF);
-	return tcpci_tcpm_set_cc(port, pull);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int mt6370_enter_low_power_mode(int port)
-{
-	int rv;
-
-	/* VBUS_DET_EN for detecting charger plug. */
-	rv = tcpc_write(port, MT6370_REG_BMC_CTRL,
-			MT6370_REG_BMCIO_LPEN | MT6370_REG_VBUS_DET_EN);
-
-	if (rv)
-		return rv;
-
-	return tcpci_enter_low_power_mode(port);
-}
-#endif
-
-static int mt6370_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	mt6370_polarity = polarity;
-	mt6370_get_cc(port, &cc1, &cc2);
-	return tcpci_tcpm_set_polarity(port, polarity);
-}
-
-int mt6370_vconn_discharge(int port)
-{
-	/*
-	 * Write to mt6370 in low-power mode may return fail, but it is
-	 * actually written. So we just ignore its return value.
-	 */
-	mt6370_i2c_write8(port, MT6370_REG_OVP_FLAG_SEL,
-			  MT6370_REG_DISCHARGE_LVL);
-	/* Set MT6370_REG_DISCHARGE_EN bit and also the rest default value. */
-	mt6370_i2c_write8(port, MT6370_REG_BMC_CTRL,
-			  MT6370_REG_DISCHARGE_EN |
-				  MT6370_REG_BMC_CTRL_DEFAULT);
-
-	return EC_SUCCESS;
-}
-
-/* MT6370 is a TCPCI compatible port controller */
-const struct tcpm_drv mt6370_tcpm_drv = {
-	.init			= &mt6370_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &mt6370_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &mt6370_set_cc,
-	.set_polarity		= &mt6370_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &mt6370_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-};
diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h
deleted file mode 100644
index cdc3112a3e..0000000000
--- a/driver/tcpm/mt6370.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MT6370 TCPC Driver
- */
-
-#ifndef __CROS_EC_USB_PD_TCPM_MT6370_H
-#define __CROS_EC_USB_PD_TCPM_MT6370_H
-
-/* MT6370 Private RegMap */
-
-#define MT6370_REG_PHY_CTRL1			0x80
-#define MT6370_REG_PHY_CTRL2			0x81
-#define MT6370_REG_PHY_CTRL3			0x82
-#define MT6370_REG_PHY_CTRL6			0x85
-
-#define MT6370_REG_CLK_CTRL2			0x87
-#define MT6370_REG_CLK_CTRL3			0x88
-
-#define MT6370_REG_RUST_STATUS			0x8A
-#define MT6370_REG_RUST_INT_EVENT		0x8B
-#define MT6370_REG_RUST_MASK			0x8C
-#define MT6370_REG_BMC_CTRL			0x90
-#define MT6370_REG_BMCIO_RXDZSEL		0x93
-#define MT6370_REG_VCONN_CLIMITEN		0x95
-
-#define MT6370_REG_OVP_FLAG_SEL			0x96
-
-#define MT6370_REG_RT_STATUS			0x97
-#define MT6370_REG_RT_INT			0x98
-#define MT6370_REG_RT_MASK			0x99
-#define RT5081_REG_BMCIO_RXDZEN			0x9A
-#define MT6370_REG_IDLE_CTRL			0x9B
-#define MT6370_REG_INTRST_CTRL			0x9C
-#define MT6370_REG_WATCHDOG_CTRL		0x9D
-#define MT6370_REG_I2CRST_CTRL			0X9E
-
-#define MT6370_REG_SWRESET			0xA0
-#define MT6370_REG_TTCPC_FILTER			0xA1
-#define MT6370_REG_DRP_TOGGLE_CYCLE		0xA2
-#define MT6370_REG_DRP_DUTY_CTRL		0xA3
-#define MT6370_REG_RUST_DETECTION		0xAD
-#define MT6370_REG_RUST_CONTROL			0xAE
-#define MT6370_REG_BMCIO_RXDZEN			0xAF
-#define MT6370_REG_DRP_RUST			0xB9
-
-#define MT6370_REG_UNLOCK_PW2			0xF0
-#define MT6370_REG_UNLOCK_PW1			0xF1
-
-#define MT6370_TCPC_I2C_ADDR_FLAGS		0x4E
-
-/*
- * MT6370_REG_PHY_CTRL1				0x80
- */
-
-#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt,      \
-				 rx_filter)                                    \
-	((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) |      \
-	 (rx_filter & 0x03))
-
-/*
- * MT6370_REG_CLK_CTRL2				0x87
- */
-
-#define MT6370_REG_CLK_DIV_600K_EN		BIT(7)
-#define MT6370_REG_CLK_BCLK2_EN			BIT(6)
-#define MT6370_REG_CLK_BCLK2_TG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_300K_EN		BIT(3)
-#define MT6370_REG_CLK_CK_300K_EN		BIT(2)
-#define MT6370_REG_CLK_BCLK_EN			BIT(1)
-#define MT6370_REG_CLK_BCLK_TH_EN		BIT(0)
-
-/*
- * MT6370_REG_CLK_CTRL3				0x88
- */
-
-#define MT6370_REG_CLK_OSCMUX_RG_EN		BIT(7)
-#define MT6370_REG_CLK_CK_24M_EN		BIT(6)
-#define MT6370_REG_CLK_OSC_RG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_2P4M_EN		BIT(4)
-#define MT6370_REG_CLK_CK_2P4M_EN		BIT(3)
-#define MT6370_REG_CLK_PCLK_EN			BIT(2)
-#define MT6370_REG_CLK_PCLK_RG_EN		BIT(1)
-#define MT6370_REG_CLK_PCLK_TG_EN		BIT(0)
-
-/*
- * MT6370_REG_RX_TX_DBG				0x8b
- */
-
-#define MT6370_REG_RX_TX_DBG_RX_BUSY		BIT(7)
-#define MT6370_REG_RX_TX_DBG_TX_BUSY		BIT(6)
-
-/*
- * MT6370_REG_BMC_CTRL				0x90
- */
-
-#define MT6370_REG_IDLE_EN			BIT(6)
-#define MT6370_REG_DISCHARGE_EN			BIT(5)
-#define MT6370_REG_BMCIO_LPRPRD			BIT(4)
-#define MT6370_REG_BMCIO_LPEN			BIT(3)
-#define MT6370_REG_BMCIO_BG_EN			BIT(2)
-#define MT6370_REG_VBUS_DET_EN			BIT(1)
-#define MT6370_REG_BMCIO_OSC_EN			BIT(0)
-#define MT6370_REG_BMC_CTRL_DEFAULT                                            \
-	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN |                     \
-	 MT6370_REG_BMCIO_OSC_EN)
-
-/*
- * MT6370_REG_BMCIO_RXDZSEL			0x93
- */
-
-#define MT6370_MASK_OCCTRL_SEL			0xE0
-#define MT6370_OCCTRL_600MA			0x80
-#define MT6370_MASK_BMCIO_RXDZSEL		BIT(0)
-
-/*
- * MT6370_REG_OVP_FLAG_SEL			0x96
- */
-
-#define MT6370_MASK_DISCHARGE_LVL		0x03
-#define MT6370_REG_DISCHARGE_LVL		BIT(0)
-
-/*
- * MT6370_REG_RT_STATUS				0x97
- */
-
-#define MT6370_REG_RA_DETACH			BIT(5)
-#define MT6370_REG_VBUS_80			BIT(1)
-
-/*
- * MT6370_REG_RT_INT				0x98
- */
-
-#define MT6370_REG_INT_RA_DETACH		BIT(5)
-#define MT6370_REG_INT_WATCHDOG			BIT(2)
-#define MT6370_REG_INT_VBUS_80			BIT(1)
-#define MT6370_REG_INT_WAKEUP			BIT(0)
-
-/*
- * MT6370_REG_RT_MASK				0x99
- */
-
-#define MT6370_REG_M_RA_DETACH			BIT(5)
-#define MT6370_REG_M_WATCHDOG			BIT(2)
-#define MT6370_REG_M_VBUS_80			BIT(1)
-#define MT6370_REG_M_WAKEUP			BIT(0)
-
-/*
- * MT6370_REG_IDLE_CTRL				0x9B
- */
-
-#define MT6370_REG_CK_300K_SEL			BIT(7)
-#define MT6370_REG_SHIPPING_OFF			BIT(5)
-#define MT6370_REG_ENEXTMSG			BIT(4)
-#define MT6370_REG_AUTOIDLE_EN			BIT(3)
-
-/* timeout = (tout*2+1) * 6.4ms */
-#ifdef CONFIG_USB_PD_REV30
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
-	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) |   \
-	 MT6370_REG_ENEXTMSG)
-#else
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
-	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07))
-#endif
-
-/*
- * MT6370_REG_INTRST_CTRL			0x9C
- */
-
-#define MT6370_REG_INTRST_EN			BIT(7)
-
-/* timeout = (tout+1) * 0.2sec */
-#define MT6370_REG_INTRST_SET(en, tout)		((en << 7) | (tout & 0x03))
-
-/*
- * MT6370_REG_WATCHDOG_CTRL			0x9D
- */
-
-#define MT6370_REG_WATCHDOG_EN			BIT(7)
-
-/* timeout = (tout+1) * 0.4sec */
-#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout)	((en << 7) | (tout & 0x07))
-
-/*
- * MT6370_REG_I2CRST_CTRL			0x9E
- */
-
-#define MT6370_REG_I2CRST_EN			BIT(7)
-
-/* timeout = (tout+1) * 12.5ms */
-#define MT6370_REG_I2CRST_SET(en, tout)		((en << 7) | (tout & 0x0f))
-
-extern const struct tcpm_drv mt6370_tcpm_drv;
-
-/* Enable VCONN discharge. */
-int mt6370_vconn_discharge(int port);
-
-#endif /* __CROS_EC_USB_PD_TCPM_MT6370_H */
diff --git a/driver/tcpm/nct38xx.c b/driver/tcpm/nct38xx.c
deleted file mode 100644
index 00240516e5..0000000000
--- a/driver/tcpm/nct38xx.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Type-C port manager for Nuvoton NCT38XX. */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "nct38xx.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "usb_common.h"
-
-#if !defined(CONFIG_USB_PD_TCPM_TCPCI)
-#error "NCT38XX is using part of standard TCPCI control"
-#error "Please upgrade your board configuration"
-#endif
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static enum nct38xx_boot_type boot_type[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-enum nct38xx_boot_type nct38xx_get_boot_type(int port)
-{
-	return boot_type[port];
-}
-
-void nct38xx_reset_notify(int port)
-{
-	/* A full reset also resets the chip's dead battery boot status */
-	boot_type[port] = NCT38XX_BOOT_UNKNOWN;
-}
-
-static int nct38xx_init(int port)
-{
-	int rv;
-	int reg;
-
-	/*
-	 * Detect dead battery boot by the default role control value of 0x0A
-	 * once per EC run
-	 */
-	if (boot_type[port] == NCT38XX_BOOT_UNKNOWN) {
-		RETURN_ERROR(tcpc_read(port, TCPC_REG_ROLE_CTRL, &reg));
-
-		if (reg == NCT38XX_ROLE_CTRL_DEAD_BATTERY)
-			boot_type[port] = NCT38XX_BOOT_DEAD_BATTERY;
-		else
-			boot_type[port] = NCT38XX_BOOT_NORMAL;
-	}
-
-	RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &reg));
-
-	/*
-	 * Set TCPC_CONTROL.DebugAccessoryControl = 1 to control by TCPM,
-	 * not TCPC in most cases.  This must be left alone if we're on a
-	 * dead battery boot with a debug accessory.  CC line detection will
-	 * be delayed if we have booted from a dead battery with a debug
-	 * accessory and change this bit (see b/186799392).
-	 */
-	if ((boot_type[port] == NCT38XX_BOOT_DEAD_BATTERY) &&
-				(reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON))
-		CPRINTS("C%d: Booted in dead battery mode, not changing debug"
-			" control", port);
-	else if (tcpc_config[port].flags & TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)
-		CPRINTS("C%d: NO_DEBUG_ACC_CONTROL", port);
-	else
-		RETURN_ERROR(tcpc_update8(port, TCPC_REG_TCPC_CTRL,
-					  TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL,
-					  MASK_SET));
-
-	/*
-	 * Write to the CONTROL_OUT_EN register to enable:
-	 * [6] - CONNDIREN : Connector direction indication output enable
-	 * [2] - SNKEN     : VBUS sink enable output enable
-	 * [0] - SRCEN     : VBUS source voltage enable output enable
-	 */
-	reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN |
-	      NCT38XX_REG_CTRL_OUT_EN_SNKEN |
-	      NCT38XX_REG_CTRL_OUT_EN_CONNDIREN;
-
-	rv = tcpc_write(port, NCT38XX_REG_CTRL_OUT_EN, reg);
-	if (rv)
-		return rv;
-
-	/* Disable OVP */
-	rv = tcpc_update8(port,
-			  TCPC_REG_FAULT_CTRL,
-			  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-			  MASK_SET);
-	if (rv)
-		return rv;
-
-	/* Enable VBus monitor and Disable FRS */
-	rv = tcpc_update8(port,
-			  TCPC_REG_POWER_CTRL,
-			  (TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
-			   TCPC_REG_POWER_CTRL_FRS_ENABLE),
-			  MASK_CLR);
-	if (rv)
-		return rv;
-
-	/* Set FRS direction for SNK detect, if FRS is enabled */
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
-		reg = TCPC_REG_DEV_CAP_2_SNK_FR_SWAP;
-		rv = tcpc_write(port, TCPC_REG_DEV_CAP_2, reg);
-		if (rv)
-			return rv;
-
-		reg = TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR;
-		rv = tcpc_write(port, TCPC_REG_CONFIG_EXT_1, reg);
-		if (rv)
-			return rv;
-	}
-
-	/* Start VBus monitor */
-	rv = tcpc_write(port, TCPC_REG_COMMAND,
-			TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
-	if (rv)
-		return rv;
-
-	/**
-	 * Set driver specific ALERT mask bits
-	 *
-	 * Wake up on faults
-	 */
-	reg = TCPC_REG_ALERT_FAULT;
-
-	/*
-	 * Enable the Vendor Define alert event only when the IO expander
-	 * feature is defined
-	 */
-	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX))
-		reg |= TCPC_REG_ALERT_VENDOR_DEF;
-
-	rv = tcpc_update16(port,
-			   TCPC_REG_ALERT_MASK,
-			   reg,
-			   MASK_SET);
-
-	if (rv)
-		return rv;
-
-	/* Enable full VCONN protection (Over-Current and Short-Circuit) */
-	reg = NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN |
-	      NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN |
-	      NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF;
-
-	rv = tcpc_update8(port,
-			  NCT38XX_REG_VBC_FAULT_CTL,
-			  reg,
-			  MASK_SET);
-
-	return rv;
-}
-
-static int nct38xx_tcpm_init(int port)
-{
-	int rv;
-
-	rv = tcpci_tcpm_init(port);
-	if (rv)
-		return rv;
-
-	return nct38xx_init(port);
-}
-
-static int nct38xx_tcpm_set_cc(int port, int pull)
-{
-	/*
-	 * Setting the CC lines to open/open requires that the NCT CTRL_OUT
-	 * register has sink disabled. Otherwise, when no battery is connected:
-	 *
-	 * 1. You set CC lines to Open/Open. This is physically happening on
-	 *    the CC line.
-	 * 2. Since CC is now Open/Open, the internal TCPC HW state machine
-	 *    is no longer in Attached.Snk and therefore our TCPC HW
-	 *    automatically opens the sink switch (de-assert the VBSNK_EN pin)
-	 * 3. Since sink switch is open, the TCPC VCC voltage starts to drop.
-	 * 4. When TCPC VCC gets below ~2.7V the TCPC will reset and therefore
-	 *    it will present Rd/Rd on the CC lines. Also the VBSNK_EN pin
-	 *    after reset is Hi-Z, so the sink switch will get closed again.
-	 *
-	 * Disabling SNKEN makes the VBSNK_EN pin Hi-Z, so
-	 * USB_Cx_TCPC_VBSNK_EN_L will be asserted by external
-	 * pull-down, so only do so if already sinking, otherwise
-	 * both source and sink switches can be closed, which should
-	 * never happen (b/166850036).
-	 *
-	 * SNKEN will be re-enabled in nct38xx_init above (from tcpm_init), or
-	 * when CC lines are set again, or when sinking is disabled.
-	 */
-	int rv;
-	enum mask_update_action action =
-			pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ?
-				MASK_CLR : MASK_SET;
-
-	rv = tcpc_update8(port,
-			  NCT38XX_REG_CTRL_OUT_EN,
-			  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-			  action);
-	if (rv)
-		return rv;
-
-	return tcpci_tcpm_set_cc(port, pull);
-}
-
-#ifdef CONFIG_USB_PD_PPC
-static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
-{
-	int rv;
-
-	/*
-	 * To disable sinking, SNKEN must be enabled so that
-	 * USB_Cx_TCPC_VBSNK_EN_L will be driven high.
-	 */
-	if (!enable) {
-		rv = tcpc_update8(port,
-				  NCT38XX_REG_CTRL_OUT_EN,
-				  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-				  MASK_SET);
-		if (rv)
-			return rv;
-	}
-
-	return tcpci_tcpm_set_snk_ctrl(port, enable);
-}
-#endif
-
-static inline int tcpc_read_alert_no_lpm_exit(int port, int *val)
-{
-	return tcpc_addr_read16_no_lpm_exit(port,
-					tcpc_config[port].i2c_info.addr_flags,
-					TCPC_REG_ALERT, val);
-}
-
-/* Map Type-C port to IOEX port */
-__overridable int board_map_nct38xx_tcpc_port_to_ioex(int port)
-{
-	return port;
-}
-
-static void nct38xx_tcpc_alert(int port)
-{
-	int alert, rv;
-
-	/*
-	 * The nct3808 is a dual port chip with a shared ALERT
-	 * pin. Avoid taking a port out of LPM if it is not alerting.
-	 *
-	 * The nct38xx exits Idle mode when ALERT is signaled, so there
-	 * is no need to run the TCPM LPM exit code to check the ALERT
-	 * register bits (Ref. NCT38n7/8 Datasheet S 2.3.4 "Setting the
-	 * I2C to * Idle"). In fact, running the TCPM LPM exit code
-	 * causes a new CC Status ALERT which has the effect of creating
-	 * a new ALERT as a side-effect of handing an ALERT.
-	 */
-	rv = tcpc_read_alert_no_lpm_exit(port, &alert);
-	if (rv == EC_SUCCESS && alert == TCPC_REG_ALERT_NONE) {
-		/* No ALERT on this port, return early. */
-		return;
-	}
-
-	/* Process normal TCPC ALERT event and clear status. */
-	tcpci_tcpc_alert(port);
-
-	/*
-	 * If the IO expander feature is enabled, use the ALERT register
-	 * value read before it was cleared by calling
-	 * tcpci_tcpc_alert().  Check the Vendor Defined Alert bit to
-	 * handle the IOEX IO's interrupt event.
-	 */
-	if (IS_ENABLED(CONFIG_IO_EXPANDER_NCT38XX) &&
-		rv == EC_SUCCESS && (alert & TCPC_REG_ALERT_VENDOR_DEF)) {
-		int ioexport;
-
-		ioexport = board_map_nct38xx_tcpc_port_to_ioex(port);
-		nct38xx_ioex_event_handler(ioexport);
-	}
-}
-
-static int nct3807_handle_fault(int port, int fault)
-{
-	int rv = EC_SUCCESS;
-
-	/* Registers are set to default, initialize for our use */
-	if (fault & TCPC_REG_FAULT_STATUS_ALL_REGS_RESET) {
-		rv = nct38xx_init(port);
-	} else {
-		/* We don't use TCPC OVP, so just disable it */
-		if (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE) {
-			/* Disable OVP */
-			rv = tcpc_update8(port,
-				  TCPC_REG_FAULT_CTRL,
-				  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-				  MASK_SET);
-			if (rv)
-				return rv;
-		}
-		/* Failing AutoDischargeDisconnect should disable it */
-		if (fault & TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL)
-			tcpm_enable_auto_discharge_disconnect(port, 0);
-	}
-	return rv;
-}
-
-__maybe_unused static int nct38xx_set_frs_enable(int port, int enable)
-{
-	/*
-	 * From b/192012189: Enabling FRS for this chip should:
-	 *
-	 * 1.  Make sure that the sink will not disconnect if Vbus will drop
-	 * due to the Fast Role Swap by setting VBUS_SINK_DISCONNECT_THRESHOLD
-	 * to 0
-	 * 2. Enable the FRS interrupt (already done in TCPCI alert init)
-	 * 3. Set POWER_CONTORL.FastRoleSwapEnable to 1
-	 */
-	RETURN_ERROR(tcpc_write16(port,
-				TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
-				enable ? 0x0000 :
-				TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT));
-
-	return tcpc_update8(port,
-			    TCPC_REG_POWER_CTRL,
-			    TCPC_REG_POWER_CTRL_FRS_ENABLE,
-			    enable ? MASK_SET : MASK_CLR);
-}
-
-const struct tcpm_drv nct38xx_tcpm_drv = {
-	.init			= &nct38xx_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &nct38xx_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &nct38xx_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.debug_accessory	= &tcpci_tcpc_debug_accessory,
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USB_PD_PPC
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &nct38xx_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable         = &nct38xx_set_frs_enable,
-#endif
-	.handle_fault		= &nct3807_handle_fault,
-};
diff --git a/driver/tcpm/nct38xx.h b/driver/tcpm/nct38xx.h
deleted file mode 100644
index a63a9f0808..0000000000
--- a/driver/tcpm/nct38xx.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Nuvoton Type-C port controller */
-
-#ifndef __CROS_EC_USB_PD_TCPM_NCT38XX_H
-#define __CROS_EC_USB_PD_TCPM_NCT38XX_H
-
-/* Chip variant ID (Part number)  */
-#define NCT38XX_VARIANT_MASK               0x1C
-#define NCT38XX_VARIANT_3807               0x0
-#define NCT38XX_VARIANT_3808               0x2
-
-/* There are two IO ports in NCT3807 */
-#define NCT38XX_NCT3807_MAX_IO_PORT        2
-/* There is only one IO port in NCT3808 */
-#define NCT38XX_NCT3808_MAX_IO_PORT        1
-
-#define NCT38XX_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_F_RISING | \
-		GPIO_INT_F_FALLING | GPIO_INT_F_HIGH | GPIO_INT_F_LOW)
-
-/* I2C interface */
-#define NCT38XX_I2C_ADDR1_1_FLAGS          0x70
-#define NCT38XX_I2C_ADDR1_2_FLAGS          0x71
-#define NCT38XX_I2C_ADDR1_3_FLAGS          0x72
-#define NCT38XX_I2C_ADDR1_4_FLAGS          0x73
-
-#define NCT38XX_I2C_ADDR2_1_FLAGS          0x74
-#define NCT38XX_I2C_ADDR2_2_FLAGS          0x75
-#define NCT38XX_I2C_ADDR2_3_FLAGS          0x76
-#define NCT38XX_I2C_ADDR2_4_FLAGS          0x77
-
-#define NCT38XX_REG_VENDOR_ID_L            0x00
-#define NCT38XX_REG_VENDOR_ID_H            0x01
-#define NCT38XX_VENDOR_ID                  0x0416
-
-#define NCT38XX_PRODUCT_ID                 0xC301
-
-/*
- * Default value from the ROLE_CTRL register on first boot will depend on
- * whether we're coming from a dead battery state.
- */
-#define NCT38XX_ROLE_CTRL_DEAD_BATTERY	   0x0A
-#define NCT39XX_ROLE_CTRL_GOOD_BATTERY	   0x4A
-
-#define NCT38XX_REG_GPIO_DATA_IN(n)       (0xC0 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DATA_OUT(n)      (0xC1 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DIR(n)           (0xC2 + ((n) * 8))
-#define NCT38XX_REG_GPIO_OD_SEL(n)        (0xC3 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_RISE(n)    (0xC4 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_FALL(n)    (0xC5 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_LEVEL(n)   (0xC6 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_MASK(n)    (0xC7 + ((n) * 8))
-#define NCT38XX_REG_MUX_CONTROL            0xD0
-#define NCT38XX_REG_GPIO_ALERT_STAT(n)    (0xD4 + (n))
-
-/* NCT3808 only supports GPIO 2/3/4/6/7 */
-#define NCT38XXX_3808_VALID_GPIO_MASK            0xDC
-
-#define NCT38XX_REG_CTRL_OUT_EN            0xD2
-#define NCT38XX_REG_CTRL_OUT_EN_SRCEN      (1 << 0)
-#define NCT38XX_REG_CTRL_OUT_EN_FASTEN     (1 << 1)
-#define NCT38XX_REG_CTRL_OUT_EN_SNKEN      (1 << 2)
-#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN  (1 << 6)
-
-#define NCT38XX_REG_VBC_FAULT_CTL          0xD7
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN	(1 << 0)
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN	(1 << 1)
-#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF	(1 << 3)
-#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF	(1 << 4)
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF	(1 << 5)
-
-#define NCT38XX_RESET_HOLD_DELAY_MS	1
-
-/*
- * From the datasheet (section 4.4.2 Reset Timing) as following:
- *                       |  Min  |  Max  |
- * ----------------------+-------+-------+
- * NCT3807 (single port) |   x   | 1.5ms |
- * ----------------------+-------+-------+
- * NCT3808 (dual port)   |   x   |   3ms |
- * ----------------------+-------+-------+
- */
-#define NCT3807_RESET_POST_DELAY_MS	2
-#define NCT3808_RESET_POST_DELAY_MS	3
-
-extern const struct tcpm_drv nct38xx_tcpm_drv;
-
-/*
- * The interrupt handler to handle Vendor Define ALERT event from IOEX chip.
- *
- * Normally, the Vendor Define event should be checked by the NCT38XX TCPCI
- * driver's tcpc_alert function.
- * This function is only included when NCT38XX TCPC driver is not included.
- * (i.e. CONFIG_USB_PD_TCPM_NCT38XX is not defined)
- */
-void nct38xx_ioex_handle_alert(int ioex);
-
-/*
- * Check which IO's interrupt event is triggered. If any, call its
- * registered interrupt handler.
- *
- * @param ioex	I/O expander number
- * @return EC_SUCCESS on success else error
- */
-int nct38xx_ioex_event_handler(int ioex);
-
-/*
- * Board level function to map USB-C port to IOEX port
- *
- * Default function assumes USB-C port number to be same as the
- * I/O expander port number. If this logic differs, add an
- * overridable function at the board level.
- *
- * @param port	USB-C port number
- * @return IOEX port number
- */
-__override_proto int board_map_nct38xx_tcpc_port_to_ioex(int port);
-
-enum nct38xx_boot_type {
-	NCT38XX_BOOT_UNKNOWN,
-	NCT38XX_BOOT_DEAD_BATTERY,
-	NCT38XX_BOOT_NORMAL,
-};
-
-/**
- * Collect our boot type from the driver
- *
- * @param port	USB-C port number
- * @return	Returns the boot type detected for this chip
- */
-enum nct38xx_boot_type nct38xx_get_boot_type(int port);
-
-/**
- * Notify the driver that the TCPC has been reset, and any stored state from
- * the chip should therefore be gathered again.  This should be called when
- * board_reset_pd_mcu is called after init time.
- *
- * @param port	USB-C port number which has been reset
- */
-void nct38xx_reset_notify(int port);
-
-extern const struct ioexpander_drv nct38xx_ioexpander_drv;
-
-#endif /* defined(__CROS_EC_USB_PD_TCPM_NCT38XX_H) */
diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c
deleted file mode 100644
index 4643c669c0..0000000000
--- a/driver/tcpm/ps8xxx.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Type-C port manager for Parade PS8XXX with integrated superspeed muxes.
- *
- * Supported TCPCs:
- * - PS8705
- * - PS8751
- * - PS8755
- * - PS8805
- * - PS8815
- */
-
-#include "common.h"
-#include "console.h"
-#include "ps8xxx.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-
-#if !defined(CONFIG_USB_PD_TCPM_PS8705) && \
-	!defined(CONFIG_USB_PD_TCPM_PS8751) && \
-	!defined(CONFIG_USB_PD_TCPM_PS8755) && \
-	!defined(CONFIG_USB_PD_TCPM_PS8805) && \
-	!defined(CONFIG_USB_PD_TCPM_PS8815)
-#error "Unsupported PS8xxx TCPC."
-#endif
-
-#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || \
-	!defined(CONFIG_USB_PD_TCPM_MUX) || \
-	!defined(CONFIG_USBC_SS_MUX)
-
-#error "PS8XXX is using a standard TCPCI interface with integrated mux control"
-#error "Please upgrade your board configuration"
-
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_PS8751
-/* PS8751 cannot run with PD 3.0 (see b/148554997 for details) */
-#if defined(CONFIG_USB_PD_REV30)
-#error "PS8751 cannot run with PD 3.0.  Fall back to using PD 2.0"
-#endif
-
-#endif /* CONFIG_USB_PD_TCPM_PS8751 */
-
-#ifdef CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
-#if !defined(CONFIG_USB_PD_TCPM_PS8751)
-#error "Custom MUX driver is available only for PS8751"
-#endif
-
-#endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#define PS8XXX_I2C_RECOVERY_DELAY_MS	10
-
-/*
- * The product_id per ports here is expected to be set in callback function -
- * .init of tcpm_drv by calling board_get_ps8xxx_product_id().
- *
- * In case of CONFIG_USB_PD_TCPM_MULTI_PS8XXX enabled, board code should
- * override the board_get_ps8xxx_product_id() for getting the correct id.
- */
-static uint16_t product_id[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * Revisions A1 and A0 of the PS8815 can corrupt the transmit buffer when
- * updating the transmit buffer within 1ms of writing the ROLE_CONTROL
- * register. When this version of silicon is detected, add a 1ms delay before
- * all writes to the transmit buffer.
- *
- * See b/171430855 for details.
- */
-static uint8_t ps8xxx_role_control_delay_ms[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * b/178664884, on PS8815, firmware revision 0x10 and older can report an
- * incorrect value on the the CC lines. This flag controls when to apply
- * the workaround.
- */
-static bool ps8815_disable_rp_detect[CONFIG_USB_PD_PORT_MAX_COUNT];
-static bool ps8815_disconnected[CONFIG_USB_PD_PORT_MAX_COUNT];
-/*
- * timestamp of the next possible toggle to ensure the 2-ms spacing
- * between IRQ_HPD.
- */
-static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void ps8xxx_wake_from_standby(const struct usb_mux *me);
-
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
-	defined(CONFIG_USB_PD_TCPM_PS8751) || \
-	defined(CONFIG_USB_PD_TCPM_PS8755) || \
-	defined(CONFIG_USB_PD_TCPM_PS8805)
-/*
- * DCI is enabled by default and burns about 40 mW when the port is in
- * USB2 mode or when a C-to-A dongle is attached, so force it off.
- */
-
-static int ps8xxx_addr_dci_disable(int port, int i2c_addr, int i2c_reg)
-{
-	int status;
-	int dci;
-
-	status = tcpc_addr_read(port, i2c_addr, i2c_reg, &dci);
-	if (status != EC_SUCCESS)
-		return status;
-	if ((dci & PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK) !=
-	    PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF) {
-		dci &= ~PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK;
-		dci |= PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF;
-		if (tcpc_addr_write(port, i2c_addr, i2c_reg, dci) != EC_SUCCESS)
-			return status;
-	}
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_USB_PD_TCPM_PS875[15] || CONFIG_USB_PD_TCPM_PS8[78]05 */
-
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
-	defined(CONFIG_USB_PD_TCPM_PS8755) || \
-	defined(CONFIG_USB_PD_TCPM_PS8805)
-static int ps8705_dci_disable(int port)
-{
-	int p1_addr;
-	int p3_addr;
-	int regval;
-	int rv;
-
-	/* Enable access to debug pages. */
-	p3_addr = tcpc_config[port].i2c_info.addr_flags;
-	rv = tcpc_addr_read(port, p3_addr, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
-			    &regval);
-	if (rv)
-		return rv;
-
-	rv = tcpc_addr_write(port, p3_addr, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
-			     PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON);
-
-	/* Disable Auto DCI */
-	p1_addr = PS8751_P3_TO_P1_FLAGS(p3_addr);
-	rv = ps8xxx_addr_dci_disable(port, p1_addr,
-				     PS8XXX_P1_REG_MUX_USB_DCI_CFG);
-
-	/*
-	 * PS8705/PS8755/PS8805 will automatically re-assert bit:0 on the
-	 * PS8XXX_REG_I2C_DEBUGGING_ENABLE register.
-	 */
-	return rv;
-}
-#endif /* CONFIG_USB_PD_TCPM_PS8755 || CONFIG_USB_PD_TCPM_PS8[78]05 */
-
-#ifdef CONFIG_USB_PD_TCPM_PS8751
-static int ps8751_dci_disable(int port)
-{
-	int p3_addr;
-
-	p3_addr = tcpc_config[port].i2c_info.addr_flags;
-	return ps8xxx_addr_dci_disable(port, p3_addr,
-				       PS8751_REG_MUX_USB_DCI_CFG);
-}
-#endif /* CONFIG_USB_PD_TCPM_PS8751 */
-
-#ifdef CONFIG_USB_PD_TCPM_PS8815
-static int ps8815_dci_disable(int port)
-{
-	/* DCI is disabled on the ps8815 */
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_USB_PD_TCPM_PS8815 */
-
-#ifdef CONFIG_USB_PD_TCPM_PS8805
-static int ps8805_gpio_mask[] = {
-	PS8805_REG_GPIO_0,
-	PS8805_REG_GPIO_1,
-	PS8805_REG_GPIO_2,
-};
-
-int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level)
-{
-	int rv;
-	int regval;
-	int mask;
-
-	if (signal >= PS8805_GPIO_NUM)
-		return EC_ERROR_INVAL;
-
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, &regval);
-	if (rv)
-		return rv;
-
-	mask = ps8805_gpio_mask[signal];
-	if (level)
-		regval |= mask;
-	else
-		regval &= ~mask;
-
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, regval);
-}
-
-int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level)
-{
-	int regval;
-	int rv;
-
-	if (signal >= PS8805_GPIO_NUM)
-		return EC_ERROR_INVAL;
-
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, &regval);
-	if (rv)
-		return rv;
-	*level = !!(regval & ps8805_gpio_mask[signal]);
-
-	return EC_SUCCESS;
-}
-#endif /* CONFIG_USB_PD_TCPM_PS8805 */
-
-enum ps8xxx_variant_regs {
-	REG_FIRST_INDEX = 0,
-	/* NOTE: The rev will read as 0x00 if the FW has malfunctioned. */
-	REG_FW_VER = REG_FIRST_INDEX,
-	REG_MAX_COUNT,
-};
-
-struct ps8xxx_variant_map {
-	int product_id;
-	int (*dci_disable_ptr)(int port);
-	int reg_map[REG_MAX_COUNT];
-};
-
-/*
- * variant_map here is leveraged to lookup from ps8xxx_variant_regs to i2c
- * register and corresponding dci_disable function based on product_id.
- */
-static struct ps8xxx_variant_map variant_map[] = {
-#ifdef CONFIG_USB_PD_TCPM_PS8705
-	{
-		PS8705_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-		 [REG_FW_VER] = 0x82,
-		}
-	},
-#endif
-#ifdef CONFIG_USB_PD_TCPM_PS8751
-	{
-		PS8751_PRODUCT_ID,
-		ps8751_dci_disable,
-		{
-			[REG_FW_VER] = 0x90,
-		}
-	},
-#endif
-#ifdef CONFIG_USB_PD_TCPM_PS8755
-	{
-		PS8755_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
-#endif
-#ifdef CONFIG_USB_PD_TCPM_PS8805
-	{
-		PS8805_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
-#endif
-#ifdef CONFIG_USB_PD_TCPM_PS8815
-	{
-		PS8815_PRODUCT_ID,
-		ps8815_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
-#endif
-};
-
-static int get_reg_by_product(const int port,
-			      const enum ps8xxx_variant_regs reg)
-{
-	int i;
-
-	if (reg < REG_FIRST_INDEX || reg >= REG_MAX_COUNT)
-		return INT32_MAX;
-
-	for (i = 0; i < ARRAY_SIZE(variant_map); i++) {
-		if (product_id[port] ==
-		      variant_map[i].product_id) {
-			return variant_map[i].reg_map[reg];
-		}
-	}
-
-	CPRINTS("%s: failed to get register number by product_id.", __func__);
-	return INT32_MAX;
-}
-
-static int dp_set_hpd(const struct usb_mux *me, int enable)
-{
-	int reg;
-	int rv;
-
-	rv = mux_read(me, MUX_IN_HPD_ASSERTION_REG, &reg);
-	if (rv)
-		return rv;
-	if (enable)
-		reg |= IN_HPD;
-	else
-		reg &= ~IN_HPD;
-	return mux_write(me, MUX_IN_HPD_ASSERTION_REG, reg);
-}
-
-static int dp_set_irq(const struct usb_mux *me, int enable)
-{
-	int reg;
-	int rv;
-
-	rv = mux_read(me, MUX_IN_HPD_ASSERTION_REG, &reg);
-	if (rv)
-		return rv;
-	if (enable)
-		reg |= HPD_IRQ;
-	else
-		reg &= ~HPD_IRQ;
-	return mux_write(me, MUX_IN_HPD_ASSERTION_REG, reg);
-}
-
-__overridable
-uint16_t board_get_ps8xxx_product_id(int port)
-{
-	/* Board supporting multiple chip sources in ps8xxx.c MUST override this
-	 * function to judge the real chip source for this board. For example,
-	 * SKU ID / strappings / provisioning in the factory can be the ways.
-	 */
-
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_MULTI_PS8XXX)) {
-		CPRINTS("%s: board should override this function.", __func__);
-		return 0;
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8705)) {
-		return PS8705_PRODUCT_ID;
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751)) {
-		return PS8751_PRODUCT_ID;
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8755)) {
-		return PS8755_PRODUCT_ID;
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8805)) {
-		return PS8805_PRODUCT_ID;
-	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) {
-		return PS8815_PRODUCT_ID;
-	}
-
-	CPRINTS("%s: Any new product id is not defined here?", __func__);
-	return 0;
-}
-
-bool check_ps8755_chip(int port)
-{
-	int val;
-	int p0_addr;
-	int status;
-	bool is_ps8755 = false;
-
-	p0_addr = PS8751_P3_TO_P0_FLAGS(tcpc_config[port].i2c_info.addr_flags);
-	status = tcpc_addr_read(port, p0_addr, PS8755_P0_REG_SM, &val);
-	if (status == EC_SUCCESS && val == PS8755_P0_REG_SM_VALUE)
-		is_ps8755 = true;
-
-	return is_ps8755;
-}
-
-void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   mux_state_t mux_state)
-{
-	int port = me->usb_port;
-	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
-	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER) &&
-	    product_id[me->usb_port] == PS8751_PRODUCT_ID &&
-	    me->flags & USB_MUX_FLAG_NOT_TCPC)
-		ps8xxx_wake_from_standby(me);
-
-	dp_set_hpd(me, hpd_lvl);
-
-	if (hpd_irq) {
-		uint64_t now = get_time().val;
-		/* wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < hpd_deadline[port])
-			usleep(hpd_deadline[port] - now);
-
-		dp_set_irq(me, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		dp_set_irq(me, hpd_irq);
-	}
-	/* enforce 2-ms delay between HPD pulses */
-	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-}
-
-static int ps8xxx_tcpc_bist_mode_2(int port)
-{
-	int rv;
-
-	/* Generate BIST for 50ms. */
-	rv = tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE0, PS8751_BIST_COUNTER_BYTE0);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE1, PS8751_BIST_COUNTER_BYTE1);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE2, PS8751_BIST_COUNTER_BYTE2);
-
-	/* Auto stop */
-	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
-
-	/* Start BIST MODE 2 */
-	rv |= tcpc_write(port, TCPC_REG_TRANSMIT, TCPCI_MSG_TX_BIST_MODE_2);
-
-	return rv;
-}
-
-static int ps8xxx_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data)
-{
-	if (type == TCPCI_MSG_TX_BIST_MODE_2)
-		return ps8xxx_tcpc_bist_mode_2(port);
-	else
-		return tcpci_tcpm_transmit(port, type, header, data);
-}
-
-static int ps8xxx_tcpm_release(int port)
-{
-	int version;
-	int status;
-	int reg = get_reg_by_product(port, REG_FW_VER);
-
-	status = tcpc_read(port, reg, &version);
-	if (status != 0) {
-		/* wait for chip to wake up */
-		msleep(10);
-	}
-
-	return tcpci_tcpm_release(port);
-}
-
-static void ps8xxx_role_control_delay(int port)
-{
-	int delay;
-
-	delay = ps8xxx_role_control_delay_ms[port];
-	if (delay)
-		msleep(delay);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-static int ps8xxx_set_role_ctrl(int port, enum tcpc_drp drp,
-	enum tcpc_rp_value rp, enum tcpc_cc_pull pull)
-{
-	int rv;
-
-	rv = tcpci_set_role_ctrl(port, drp, rp, pull);
-
-	/*
-	 * b/171430855 delay 1 ms after ROLE_CONTROL updates to prevent
-	 * transmit buffer corruption
-	 */
-	ps8xxx_role_control_delay(port);
-
-	return rv;
-}
-
-static int ps8xxx_tcpc_drp_toggle(int port)
-{
-	int rv;
-	int status;
-	int opposite_pull;
-
-	/*
-	 * Workaround for PS8805/PS8815, which can't restart Connection
-	 * Detection if the partner already presents pull. Now starts with
-	 * the opposite pull. Check b/149570002.
-	 */
-	if (product_id[port] == PS8805_PRODUCT_ID ||
-	    product_id[port] == PS8815_PRODUCT_ID) {
-		if (ps8815_disable_rp_detect[port]) {
-			CPRINTS("TCPC%d: rearm Rp disable detect on connect",
-				port);
-			ps8815_disconnected[port] = true;
-		}
-
-		/* Check CC_STATUS for the current pull */
-		rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status);
-		if (status & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) {
-			/* Current pull: Rd */
-			opposite_pull = TYPEC_CC_RP;
-		} else {
-			/* Current pull: Rp */
-			opposite_pull = TYPEC_CC_RD;
-		}
-
-		/* Set auto drp toggle, starting with the opposite pull */
-		rv |= ps8xxx_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB,
-			opposite_pull);
-
-		/* Set Look4Connection command */
-		rv |= tcpc_write(port, TCPC_REG_COMMAND,
-				 TCPC_REG_COMMAND_LOOK4CONNECTION);
-
-		return rv;
-	} else {
-		return tcpci_tcpc_drp_toggle(port);
-	}
-}
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-static int ps8805_make_device_id(int port, int *id)
-{
-	int p0_addr;
-	int val;
-	int status;
-
-	p0_addr = PS8751_P3_TO_P0_FLAGS(tcpc_config[port].i2c_info.addr_flags);
-
-	status = tcpc_addr_read(port, p0_addr, PS8805_P0_REG_CHIP_REVISION,
-				&val);
-	if (status != EC_SUCCESS)
-		return status;
-	switch (val & 0xF0) {
-	case 0x00: /* A2 chip */
-		*id = 1;
-		break;
-	case 0xa0: /* A3 chip */
-		*id = 2;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-/*
- * Early ps8815 A1 firmware reports 0x0001 in the TCPCI Device ID
- * registers which makes it indistinguishable from A0. This
- * overrides the Device ID based if vendor specific registers
- * identify the chip as A1.
- *
- * See b/159289062.
- *
- * The ps8815 A2 reports device ID 0x0001 instead of 0x0003 when the
- * firmware is bad (mis-programmed).
- */
-static int ps8815_make_device_id(int port, int *id)
-{
-	int p1_addr;
-	int val;
-	int status;
-
-	/* P1 registers are always accessible on PS8815 */
-	p1_addr = PS8751_P3_TO_P1_FLAGS(tcpc_config[port].i2c_info.addr_flags);
-
-	status = tcpc_addr_read16(port, p1_addr, PS8815_P1_REG_HW_REVISION,
-				  &val);
-	if (status != EC_SUCCESS)
-		return status;
-
-	switch (val) {
-	case 0x0a00:
-		*id = 1;
-		break;
-	case 0x0a01:
-		*id = 2;
-		break;
-	case 0x0a02:
-		*id = 3;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-#endif
-
-/*
- * The ps8815 can take up to 50ms (FW_INIT_DELAY_MS) to fully wake up
- * from sleep/low power mode - specially when it contains an application
- * block firmware update. When the chip is asleep, the 1st I2C
- * transaction will fail but the chip will begin to wake up within 10ms
- * (I2C_RECOVERY_DELAY_MS). After this delay, I2C transactions succeed,
- * but the firmware is still not fully operational. The way to check if
- * the firmware is ready, is to poll the firmware register for a
- * non-zero value. This logic applies to all ps8xxx family members
- * supported by this driver.
- */
-
-static int ps8xxx_lpm_recovery_delay(int port)
-{
-	int val;
-	int status;
-	int fw_reg;
-	timestamp_t deadline;
-
-	fw_reg = get_reg_by_product(port, REG_FW_VER);
-
-	deadline = get_time();
-	deadline.val += PS8815_FW_INIT_DELAY_MS * 1000;
-
-	val = 0;
-	for (;;) {
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-
-		status = tcpc_read(port, fw_reg, &val);
-		if (status != EC_SUCCESS) {
-			/* wait for chip to wake up */
-			msleep(PS8XXX_I2C_RECOVERY_DELAY_MS);
-			continue;
-		}
-		if (val != 0)
-			break;
-		msleep(1);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int ps8xxx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	int val;
-	int reg;
-	int rv = tcpci_get_chip_info(port, live, chip_info);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (chip_info == NULL)
-		return EC_SUCCESS;
-
-	if (!live) {
-		uint16_t pid;
-
-		pid = board_get_ps8xxx_product_id(port);
-		if (pid == 0)
-			return EC_ERROR_UNKNOWN;
-		product_id[port] = pid;
-		chip_info->vendor_id = PS8XXX_VENDOR_ID;
-		chip_info->product_id = product_id[port];
-	}
-
-#ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-	if (chip_info->product_id == PS8805_PRODUCT_ID &&
-	    chip_info->device_id == 0x0001) {
-		rv = ps8805_make_device_id(port, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-		chip_info->device_id = val;
-	}
-#endif
-#ifdef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-	if (chip_info->product_id == PS8815_PRODUCT_ID &&
-	    chip_info->device_id == 0x0001) {
-		rv = ps8815_make_device_id(port, &val);
-		if (rv != EC_SUCCESS)
-			return rv;
-		chip_info->device_id = val;
-	}
-#endif
-	reg = get_reg_by_product(port, REG_FW_VER);
-	rv = tcpc_read(port, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	chip_info->fw_version_number = val;
-
-	/* Treat unexpected values as error (FW not initiated from reset) */
-	if (live && (
-	    chip_info->vendor_id != PS8XXX_VENDOR_ID ||
-	    chip_info->product_id != board_get_ps8xxx_product_id(port) ||
-	    chip_info->fw_version_number == 0))
-		return EC_ERROR_UNKNOWN;
-
-#if defined(CONFIG_USB_PD_TCPM_PS8751) && \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC)
-	/*
-	 * Min firmware version of PS8751 to ensure that it can detect Vbus
-	 * properly. See b/109769787#comment7
-	 */
-	chip_info->min_req_fw_version_number = 0x39;
-#endif
-
-	return rv;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int ps8xxx_enter_low_power_mode(int port)
-{
-	/*
-	 * PS8751 has the auto sleep function that enters low power mode on
-	 * its own in ~2 seconds. Other chips don't have it. Stub it out for
-	 * PS8751.
-	 */
-	if (product_id[port] == PS8751_PRODUCT_ID)
-		return EC_SUCCESS;
-
-	return tcpci_enter_low_power_mode(port);
-}
-#endif
-
-static int ps8xxx_dci_disable(int port)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(variant_map); i++) {
-		if (product_id[port] == variant_map[i].product_id)
-			return variant_map[i].dci_disable_ptr(port);
-	}
-
-	CPRINTS("%s: failed to get dci_disable function pointers.", __func__);
-	return EC_ERROR_INVAL;
-}
-
-__maybe_unused static int ps8815_transmit_buffer_workaround_check(int port)
-{
-	int p1_addr;
-	int val;
-	int status;
-
-	if (product_id[port] != PS8815_PRODUCT_ID)
-		return EC_SUCCESS;
-
-	/* P1 registers are always accessible on PS8815 */
-	p1_addr = PS8751_P3_TO_P1_FLAGS(tcpc_config[port].i2c_info.addr_flags);
-
-	status = tcpc_addr_read16(port, p1_addr, PS8815_P1_REG_HW_REVISION,
-				  &val);
-	if (status != EC_SUCCESS)
-		return status;
-
-	switch (val) {
-	case 0x0a00:
-	case 0x0a01:
-		ps8xxx_role_control_delay_ms[port] = 1;
-		break;
-	default:
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int ps8815_disable_rp_detect_workaround_check(int port)
-{
-	int val;
-	int rv;
-	int reg;
-
-	ps8815_disable_rp_detect[port] = false;
-	ps8815_disconnected[port] = true;
-
-	reg = get_reg_by_product(port, REG_FW_VER);
-	rv = tcpc_read(port, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/*
-	 * RP detect is a problem in firmware version 0x10 and older.
-	 */
-	if (val <= 0x10)
-		ps8815_disable_rp_detect[port] = true;
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_ps8xxx_tcpc_init(int port)
-{}
-
-static int ps8xxx_tcpm_init(int port)
-{
-	int status;
-
-	product_id[port] = board_get_ps8xxx_product_id(port);
-
-	status = ps8xxx_lpm_recovery_delay(port);
-	if (status != EC_SUCCESS) {
-		CPRINTS("C%d: init: LPM recovery failed", port);
-		return status;
-	}
-
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) {
-		status = ps8815_transmit_buffer_workaround_check(port);
-		if (status != EC_SUCCESS)
-			return status;
-		status = ps8815_disable_rp_detect_workaround_check(port);
-		if (status != EC_SUCCESS)
-			return status;
-	}
-
-	board_ps8xxx_tcpc_init(port);
-
-	status = tcpci_tcpm_init(port);
-	if (status != EC_SUCCESS)
-		return status;
-
-	return ps8xxx_dci_disable(port);
-}
-
-#ifdef CONFIG_USB_PD_TCPM_PS8751
-/*
- * TODO(twawrzynczak): Remove this workaround when no
- * longer needed.  See: https://issuetracker.google.com/147684491
- *
- * This is a workaround for what appears to be a bug in PS8751 firmware
- * version 0x44.  (Does the bug exist in other PS8751 firmware versions?
- * Should this workaround be limited to only 0x44?)
- *
- * With nothing connected to the port, sometimes after DRP is disabled,
- * the CC_STATUS register reads the CC state incorrectly (reading it
- * as though a port partner is detected), which ends up confusing
- * our TCPM.  The workaround for this seems to be a short sleep and
- * then re-reading the CC state.  In other words, the issue shows up
- * as a short glitch or transient, which an extra read and then a short
- * delay will allow the transient to disappear.
- */
-static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
-{
-	int rv;
-	int status;
-	rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status);
-	if (rv)
-		return rv;
-
-	/* Derived empirically */
-	usleep(300);
-
-	return tcpci_tcpm_get_cc(port, cc1, cc2);
-}
-#endif
-
-static int ps8xxx_tcpm_set_cc(int port, int pull)
-{
-	int rv;
-
-	/*
-	 * b/178664884: Before presenting Rp on initial connect, disable
-	 * internal function that checks Rp value. This is a workaround
-	 * in the PS8815 firmware that reports an incorrect value on the CC
-	 * lines.
-	 *
-	 * The PS8815 self-clears these bits.
-	 */
-	if (ps8815_disable_rp_detect[port] && ps8815_disconnected[port] &&
-	    pull == TYPEC_CC_RP) {
-		CPRINTS("TCPC%d: disable chip based Rp detect on connection",
-			port);
-		tcpc_write(port, PS8XXX_REG_RP_DETECT_CONTROL,
-			   RP_DETECT_DISABLE);
-		ps8815_disconnected[port] = false;
-	}
-
-	rv = tcpci_tcpm_set_cc(port, pull);
-
-	/*
-	 * b/171430855 delay 1 ms after ROLE_CONTROL updates to prevent
-	 * transmit buffer corruption
-	 */
-	ps8xxx_role_control_delay(port);
-
-	return rv;
-}
-
-static int ps8xxx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
-{
-#ifdef CONFIG_USB_PD_TCPM_PS8751
-	if (product_id[port] == PS8751_PRODUCT_ID)
-		return ps8751_get_gcc(port, cc1, cc2);
-#endif
-
-	return tcpci_tcpm_get_cc(port, cc1, cc2);
-}
-
-const struct tcpm_drv ps8xxx_tcpm_drv = {
-	.init			= ps8xxx_tcpm_init,
-	.release		= ps8xxx_tcpm_release,
-	.get_cc			= ps8xxx_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= tcpci_tcpm_select_rp_value,
-	.set_cc			= ps8xxx_tcpm_set_cc,
-	.set_polarity		= tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= tcpci_tcpm_set_vconn,
-	.set_msg_header		= tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= tcpci_tcpm_get_message_raw,
-	.transmit		= ps8xxx_tcpm_transmit,
-	.tcpc_alert		= tcpci_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= tcpci_tcpc_discharge_vbus,
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= ps8xxx_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl		= tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info		= ps8xxx_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= ps8xxx_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= tcpci_set_bist_test_mode,
-};
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev = {
-	.reg_info = {
-		.read_reg = PS8XXX_REG_VENDOR_ID_L,
-		.read_val = PS8XXX_VENDOR_ID & 0xFF,
-		.write_reg = MUX_IN_HPD_ASSERTION_REG,
-	},
-	.i2c_read = tcpc_i2c_read,
-	.i2c_write = tcpc_i2c_write,
-};
-#endif /* CONFIG_CMD_I2C_STRESS_TEST_TCPC */
-
-#ifdef CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
-
-static int ps8xxx_mux_init(const struct usb_mux *me)
-{
-	RETURN_ERROR(tcpci_tcpm_mux_init(me));
-
-	/* If this MUX is also the TCPC, then skip init */
-	if (!(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		return EC_SUCCESS;
-
-	product_id[me->usb_port] = board_get_ps8xxx_product_id(me->usb_port);
-
-	return EC_SUCCESS;
-}
-
-/*
- * PS8751 goes to standby mode automatically when both CC lines are set to RP.
- * In standby mode it doesn't respond to first I2C access, but next
- * transactions are working fine (until it goes to sleep again).
- *
- * To wake device documentation recommends read content of 0xA0 register.
- */
-void ps8xxx_wake_from_standby(const struct usb_mux *me)
-{
-	int reg;
-
-	/* Since we are waking up device, this call will most likely fail */
-	mux_read(me, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &reg);
-	msleep(10);
-}
-
-static int ps8xxx_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
-	    me->flags & USB_MUX_FLAG_NOT_TCPC) {
-		ps8xxx_wake_from_standby(me);
-
-		/*
-		 * To operate properly, when working as mux only, PS8751 CC
-		 * lines needs to be RD all the time. Changing to RP after
-		 * setting mux breaks SuperSpeed connection.
-		 */
-		if (mux_state != USB_PD_MUX_NONE)
-			RETURN_ERROR(mux_write(me, TCPC_REG_ROLE_CTRL,
-					TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP,
-							       TYPEC_RP_USB,
-							       TYPEC_CC_RD,
-							       TYPEC_CC_RD)));
-	}
-
-	return tcpci_tcpm_mux_set(me, mux_state, ack_required);
-}
-
-static int ps8xxx_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
-	    me->flags & USB_MUX_FLAG_NOT_TCPC)
-		ps8xxx_wake_from_standby(me);
-
-	return tcpci_tcpm_mux_get(me, mux_state);
-}
-
-static int ps8xxx_mux_enter_low_power(const struct usb_mux *me)
-{
-	/*
-	 * Set PS8751 lines to RP. This allows device to standby
-	 * automatically after ~2 seconds
-	 */
-	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
-	    me->flags & USB_MUX_FLAG_NOT_TCPC) {
-		/*
-		 * It may happen that this write will fail, but
-		 * RP seems to be set correctly
-		 */
-		mux_write(me, TCPC_REG_ROLE_CTRL,
-			  TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, TYPEC_RP_USB,
-						 TYPEC_CC_RP, TYPEC_CC_RP));
-		return EC_SUCCESS;
-	}
-
-	return tcpci_tcpm_mux_enter_low_power(me);
-}
-
-const struct usb_mux_driver ps8xxx_usb_mux_driver = {
-	.init = ps8xxx_mux_init,
-	.set = ps8xxx_mux_set,
-	.get = ps8xxx_mux_get,
-	.enter_low_power_mode = ps8xxx_mux_enter_low_power,
-};
-
-#endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h
deleted file mode 100644
index 8458dbb7e5..0000000000
--- a/driver/tcpm/ps8xxx.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "usb_mux.h"
-
-#include "driver/tcpm/ps8xxx_public.h"
-
-/* Parade Tech Type-C port controller */
-
-#ifndef __CROS_EC_USB_PD_TCPM_PS8XXX_H
-#define __CROS_EC_USB_PD_TCPM_PS8XXX_H
-
-#define PS8751_P3_TO_P0_FLAGS(p3_flags)	((p3_flags) - 3)
-#define PS8751_P3_TO_P1_FLAGS(p3_flags)	((p3_flags) - 2)
-
-#define PS8751_BIST_TIMER_FREQ  15000000
-#define PS8751_BIST_DELAY_MS    50
-
-#define PS8751_BIST_COUNTER (PS8751_BIST_TIMER_FREQ / MSEC \
-				* PS8751_BIST_DELAY_MS)
-
-#define PS8751_BIST_COUNTER_BYTE0 (PS8751_BIST_COUNTER & 0xff)
-#define PS8751_BIST_COUNTER_BYTE1 ((PS8751_BIST_COUNTER >> 8) & 0xff)
-#define PS8751_BIST_COUNTER_BYTE2 ((PS8751_BIST_COUNTER >> 16) & 0xff)
-
-#define PS8XXX_REG_RP_DETECT_CONTROL            0x9B
-#define RP_DETECT_DISABLE			0x30
-
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE         0xA0
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON      0x30
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF     0x31    /* default */
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE0         0xBC
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE1         0xBD
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE2         0xBE
-#define PS8XXX_REG_BIST_CONT_MODE_CTR           0xBF
-#define PS8XXX_REG_DET_CTRL0                    0x08
-
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK    0xC0
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF     0x80
-
-#define MUX_IN_HPD_ASSERTION_REG                0xD0
-#define IN_HPD  BIT(0)
-#define HPD_IRQ BIT(1)
-
-#define PS8XXX_P1_REG_MUX_USB_DCI_CFG           0x4B
-
-#define PS8755_P0_REG_SM			0x06
-#define PS8755_P0_REG_SM_VALUE			0x80
-
-#if defined(CONFIG_USB_PD_TCPM_PS8751)
-/* Vendor defined registers */
-#define PS8XXX_REG_VENDOR_ID_L                  0x00
-#define PS8XXX_REG_VENDOR_ID_H                  0x01
-#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION      0xD3
-#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION  0xD4
-#define PS8XXX_REG_MUX_USB_C2SS_EQ              0xE7
-#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD    0xE8
-#define PS8751_REG_MUX_USB_DCI_CFG              0xED
-#endif
-
-/* Vendor defined registers */
-#define PS8815_P1_REG_HW_REVISION		0xF0
-
-/*
- * Below register is defined from Parade PS8815 Register Table,
- * See b:189587527 for more detail.
- */
-
-/* Displayport related settings */
-#define PS8815_REG_DP_EQ_SETTING		0xF8
-#define PS8815_AUTO_EQ_DISABLE			BIT(7)
-#define PS8815_DPEQ_LOSS_UP_21DB		0x09
-#define PS8815_DPEQ_LOSS_UP_20DB		0x08
-#define PS8815_DPEQ_LOSS_UP_19DB		0x07
-#define PS8815_DPEQ_LOSS_UP_18DB		0x06
-#define PS8815_DPEQ_LOSS_UP_17DB		0x05
-#define PS8815_DPEQ_LOSS_UP_16DB		0x04
-#define PS8815_DPEQ_LOSS_UP_13DB		0x03
-#define PS8815_DPEQ_LOSS_UP_12DB		0x02
-#define PS8815_DPEQ_LOSS_UP_10DB		0x01
-#define PS8815_DPEQ_LOSS_UP_9DB			0x00
-#define PS8815_REG_DP_EQ_COMP_SHIFT		3
-#define PS8815_AUX_INTERCEPTION_DISABLE		BIT(1)
-
-/*
- * PS8805 register to distinguish chip revision
- * bit 7-4: 1010b is A3 chip, 0000b is A2 chip
- */
-#define PS8805_P0_REG_CHIP_REVISION		0x62
-
-/*
- * PS8805 GPIO control register. Note the device I2C address of 0x1A is
- * independent of the ADDR pin on the chip, and not the same address being used
- * for TCPCI functions.
- */
-#define PS8805_VENDOR_DEFINED_I2C_ADDR		0x1A
-#define PS8805_REG_GPIO_CONTROL		0x21
-#define PS8805_REG_GPIO_0			BIT(7)
-#define PS8805_REG_GPIO_1			BIT(5)
-#define PS8805_REG_GPIO_2			BIT(6)
-
-enum ps8805_gpio {
-	PS8805_GPIO_0,
-	PS8805_GPIO_1,
-	PS8805_GPIO_2,
-	PS8805_GPIO_NUM,
-};
-
-/**
- * Set PS8805 gpio signal to desired level
- *
- * @param port: The Type-C port number.
- * @param signal PS8805 gpio number (0, 1, or 2)
- * @param level desired level
- * @return EC_SUCCESS if I2C accesses are successful
- */
-int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level);
-
-/**
- * Get PS8805 gpio signal value
- *
- * @param port: The Type-C port number.
- * @param signal PS8805 gpio number (0, 1, or 2)
- * @param pointer location to store gpio level
- * @return EC_SUCCESS if I2C accesses are successful
- */
-int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level);
-
-/**
- * Check if the chip is PS8755
- *
- * @param port: The Type-C port number.
- * @return true if hidden register sm is 0x80
- */
-bool check_ps8755_chip(int port);
-
-/*
- * Allow boards to customize for PS8XXX initial if board has
- * specific settings.
- *
- * @param port: The Type-C port number.
- */
-__override_proto void board_ps8xxx_tcpc_init(int port);
-
-#endif /* defined(__CROS_EC_USB_PD_TCPM_PS8XXX_H) */
diff --git a/driver/tcpm/raa489000.c b/driver/tcpm/raa489000.c
deleted file mode 100644
index c4976bab4e..0000000000
--- a/driver/tcpm/raa489000.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Renesas RAA489000 TCPC driver
- */
-
-#include "charge_manager.h"
-#include "charger.h"
-#include "common.h"
-#include "console.h"
-#include "driver/charger/isl923x.h"
-#include "i2c.h"
-#include "raa489000.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-
-#define DEFAULT_R_AC 20
-#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC)
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-static int dev_id[CONFIG_USB_PD_PORT_MAX_COUNT] = { -1 };
-
-static int raa489000_enter_low_power_mode(int port)
-{
-	int rv;
-
-	rv = tcpc_write16(port, RAA489000_PD_PHYSICAL_SETTING1, 0);
-	if (rv)
-		CPRINTS("RAA489000(%d): Failed to set PD PHY setting1!", port);
-
-	rv = tcpc_write16(port, RAA489000_TCPC_SETTING1, 0);
-	if (rv)
-		CPRINTS("RAA489000(%d): Failed to set TCPC setting1!", port);
-
-	return tcpci_enter_low_power_mode(port);
-}
-
-/* Configure output current in the TCPC because it is controlling Vbus */
-int raa489000_set_output_current(int port, enum tcpc_rp_value rp)
-{
-	int regval;
-	int selected_cur = rp == TYPEC_RP_3A0 ?
-				RAA489000_VBUS_CURRENT_TARGET_3A :
-				RAA489000_VBUS_CURRENT_TARGET_1_5A;
-
-	regval = AC_CURRENT_TO_REG(selected_cur) +
-				selected_cur % (DEFAULT_R_AC/R_AC);
-
-	return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET,
-				regval);
-}
-
-int raa489000_init(int port)
-{
-	int rv;
-	int regval;
-	int device_id;
-	int i2c_port;
-	struct charge_port_info chg = { 0 };
-	int vbus_mv = 0;
-
-	/* Perform unlock sequence */
-	rv = tcpc_write16(port, 0xAA, 0xDAA0);
-	if (rv)
-		CPRINTS("c%d: failed unlock step1", port);
-	rv = tcpc_write16(port, 0xAA, 0xACE0);
-	if (rv)
-		CPRINTS("c%d: failed unlock step2", port);
-	rv = tcpc_write16(port, 0xAA, 0x0D0B);
-	if (rv)
-		CPRINTS("c%d: failed unlock step3", port);
-
-	device_id = -1;
-	rv = tcpc_read16(port, TCPC_REG_BCD_DEV, &device_id);
-	if (rv)
-		CPRINTS("C%d: Failed to read DEV_ID", port);
-	CPRINTS("%s(%d): DEVICE_ID=%d", __func__, port, device_id);
-	dev_id[port] = device_id;
-
-	/* Enable the ADC */
-	/*
-	 * TODO(b:147316511) Since this register can be accessed by multiple
-	 * tasks, we should add a mutex when modifying this register.
-	 *
-	 * See(b:178981107,b:178728138) When the battery does not exist,
-	 * we must enable ADC function so that charger_get_vbus_voltage
-	 * can get the correct voltage.
-	 */
-	i2c_port = tcpc_config[port].i2c_info.port;
-	rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_CONTROL3, &regval);
-	regval |= RAA489000_ENABLE_ADC;
-	rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_CONTROL3, regval);
-	if (rv)
-		CPRINTS("c%d: failed to enable ADCs", port);
-
-	/* Enable Vbus detection */
-	rv = tcpc_write(port, TCPC_REG_COMMAND,
-			TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
-	if (rv)
-		CPRINTS("c%d: failed to enable vbus detect cmd", port);
-
-
-	/*
-	 * If VBUS is present, start sinking from it if we haven't already
-	 * chosen a charge port and no battery is connected.  This is
-	 * *kinda hacky* doing it here, but we must start sinking VBUS now,
-	 * otherwise the board may die (See b/150702984, b/178728138).  This
-	 * works as this part is a combined charger IC and TCPC.
-	 */
-	usleep(853);
-	charger_get_vbus_voltage(port, &vbus_mv);
-
-	/*
-	 * Disable the ADC
-	 *
-	 * See(b:178356507)  9mW is reduced on S0iX power consumption
-	 * by clearing 'Enable ADC' bit.
-	 */
-	if (IS_ENABLED(CONFIG_OCPC) && (port != 0)) {
-		i2c_port = tcpc_config[port].i2c_info.port;
-		rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS,
-				ISL9238_REG_CONTROL3, &regval);
-		regval &= ~RAA489000_ENABLE_ADC;
-		rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS,
-				ISL9238_REG_CONTROL3, regval);
-		if (rv)
-			CPRINTS("c%d: failed to disable ADCs", port);
-	}
-
-	if ((vbus_mv > 3900) &&
-	    charge_manager_get_active_charge_port() == CHARGE_PORT_NONE &&
-	    !pd_is_battery_capable()) {
-		chg.current = 500;
-		chg.voltage = 5000;
-		charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, port, &chg);
-		board_set_active_charge_port(port);
-	}
-
-	if (device_id > 1) {
-		/*
-		 * A1 silicon has a DEVICE_ID of 1.  For B0 and newer, we need
-		 * allow the TCPC to control VBUS in order to start VBUS ADC
-		 * sampling.  This is a requirement to clear the TCPC
-		 * initialization status but in POWER_STATUS.  Otherwise, the
-		 * common TCPCI init will fail. (See b/154191301)
-		 */
-		rv = tcpc_read16(port, RAA489000_TCPC_SETTING1, &regval);
-		regval |= RAA489000_TCPC_PWR_CNTRL;
-		rv = tcpc_write16(port, RAA489000_TCPC_SETTING1, regval);
-		if (rv)
-			CPRINTS("C%d: failed to set TCPC power control", port);
-	}
-
-	/* Note: registers may not be ready until TCPCI init succeeds */
-	rv = tcpci_tcpm_init(port);
-	if (rv)
-		return rv;
-
-	/*
-	 * Set some vendor defined registers to enable the CC comparators and
-	 * remove the dead battery resistors.  This only needs to be done on
-	 * early silicon versions.
-	 */
-	if (device_id <= 1) {
-		rv = tcpc_write16(port, RAA489000_TYPEC_SETTING1,
-			     RAA489000_SETTING1_RDOE |
-			     RAA489000_SETTING1_CC2_CMP3_EN |
-			     RAA489000_SETTING1_CC2_CMP2_EN |
-			     RAA489000_SETTING1_CC2_CMP1_EN |
-			     RAA489000_SETTING1_CC1_CMP3_EN |
-			     RAA489000_SETTING1_CC1_CMP2_EN |
-			     RAA489000_SETTING1_CC1_CMP1_EN |
-			     RAA489000_SETTING1_CC_DB_EN);
-		if (rv)
-			CPRINTS("c%d: failed to enable CC comparators", port);
-	}
-
-	/* Set Rx enable for receiver comparator */
-	rv = tcpc_read16(port, RAA489000_PD_PHYSICAL_SETTING1, &regval);
-	regval |= RAA489000_PD_PHY_SETTING1_RECEIVER_EN |
-		RAA489000_PD_PHY_SETTING1_SQUELCH_EN |
-		RAA489000_PD_PHY_SETTING1_TX_LDO11_EN;
-	rv |= tcpc_write16(port, RAA489000_PD_PHYSICAL_SETTING1, regval);
-	if (rv)
-		CPRINTS("c%d: failed to set PD PHY setting1", port);
-
-	/*
-	 * Disable VBUS auto discharge, we'll turn it on later as its needed to
-	 * goodcrc.
-	 */
-	rv = tcpc_read(port, TCPC_REG_POWER_CTRL, &regval);
-	regval &= ~TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT;
-	rv |= tcpc_write(port, TCPC_REG_POWER_CTRL, regval);
-	if (rv)
-		CPRINTS("c%d: failed to set auto discharge", port);
-
-	if (device_id <= 1) {
-		/* The vendor says to set this setting. */
-		rv = tcpc_write16(port, RAA489000_PD_PHYSICAL_PARAMETER1,
-				  0x6C07);
-		if (rv)
-			CPRINTS("c%d: failed to set PD PHY PARAM1", port);
-	}
-
-	/* Enable the correct TCPCI interface version */
-	rv = tcpc_read16(port, RAA489000_TCPC_SETTING1, &regval);
-	if (!(tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0))
-		regval |= RAA489000_TCPCV1_0_EN;
-	else
-		regval &= ~RAA489000_TCPCV1_0_EN;
-
-	if (device_id <= 1) {
-		/* Allow the TCPC to control VBUS. */
-		regval |= RAA489000_TCPC_PWR_CNTRL;
-	}
-
-	rv = tcpc_write16(port, RAA489000_TCPC_SETTING1, regval);
-	if (rv)
-		CPRINTS("c%d: failed to set TCPCIv1.0 mode", port);
-
-	/*
-	 * Set Vbus OCP UV here, PD tasks will set target current
-	 */
-	rv = tcpc_write16(port, RAA489000_VBUS_OCP_UV_THRESHOLD,
-				RAA489000_OCP_THRESHOLD_VALUE);
-	if (rv)
-		CPRINTS("c%d: failed to set OCP threshold", port);
-
-	/* Set Vbus Target Voltage */
-	rv = tcpc_write16(port, RAA489000_VBUS_VOLTAGE_TARGET,
-				RAA489000_VBUS_VOLTAGE_TARGET_5160MV);
-	if (rv)
-		CPRINTS("c%d: failed to set Vbus Target Voltage", port);
-
-	return rv;
-}
-
-int raa489000_tcpm_set_cc(int port, int pull)
-{
-	int rv;
-
-	rv = tcpci_tcpm_set_cc(port, pull);
-	if (dev_id[port] > 1 || rv)
-		return rv;
-
-	/* Older silicon needs the TCPM to set RDOE to 1 after setting Rp */
-	if (pull == TYPEC_CC_RP)
-		rv = tcpc_update16(port, RAA489000_TYPEC_SETTING1,
-				   RAA489000_SETTING1_RDOE, MASK_SET);
-
-	return rv;
-}
-
-int raa489000_debug_detach(int port)
-{
-	int rv;
-	int power_status;
-
-	/*
-	 * Force RAA489000 to see debug detach by running:
-	 *
-	 * 1. Set POWER_CONTROL. AutoDischargeDisconnect=1
-	 * 2. Set ROLE_CONTROL=0x0F(OPEN,OPEN)
-	 * 3. Set POWER_CONTROL. AutoDischargeDisconnect=0
-	 *
-	 * Only if we have sufficient battery or are not sinking.  Otherwise,
-	 * we would risk brown-out during the CC open set.
-	 */
-	RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &power_status));
-
-	if (!pd_is_battery_capable() &&
-			(power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS))
-		return EC_SUCCESS;
-
-	tcpci_tcpc_enable_auto_discharge_disconnect(port, 1);
-
-	rv = tcpci_tcpm_set_cc(port, TYPEC_CC_OPEN);
-
-	tcpci_tcpc_enable_auto_discharge_disconnect(port, 0);
-
-	return rv;
-}
-
-/* RAA489000 is a TCPCI compatible port controller */
-const struct tcpm_drv raa489000_tcpm_drv = {
-	.init                   = &raa489000_init,
-	.release                = &tcpci_tcpm_release,
-	.get_cc                 = &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value        = &tcpci_tcpm_select_rp_value,
-	.set_cc                 = &raa489000_tcpm_set_cc,
-	.set_polarity           = &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn              = &tcpci_tcpm_set_vconn,
-	.set_msg_header         = &tcpci_tcpm_set_msg_header,
-	.set_rx_enable          = &tcpci_tcpm_set_rx_enable,
-	.get_message_raw        = &tcpci_tcpm_get_message_raw,
-	.transmit               = &tcpci_tcpm_transmit,
-	.tcpc_alert             = &tcpci_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus    = &tcpci_tcpc_discharge_vbus,
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle             = &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info          = &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &raa489000_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-	.tcpc_enable_auto_discharge_disconnect =
-		&tcpci_tcpc_enable_auto_discharge_disconnect,
-	.debug_detach		= &raa489000_debug_detach,
-};
diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h
deleted file mode 100644
index 2a4c7c6b3d..0000000000
--- a/driver/tcpm/raa489000.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * TCPC driver for Renesas RAA489000 Buck-boost charger with TCPC
- */
-
-#include "compile_time_macros.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef __CROS_EC_USB_PD_TCPM_RAA489000_H
-#define __CROS_EC_USB_PD_TCPM_RAA489000_H
-
-#define RAA489000_TCPC0_I2C_FLAGS 0x22
-#define RAA489000_TCPC1_I2C_FLAGS 0x23
-#define RAA489000_TCPC2_I2C_FLAGS 0x24
-#define RAA489000_TCPC3_I2C_FLAGS 0x25
-
-/* Vendor registers */
-#define RAA489000_TCPC_SETTING1			0x80
-#define RAA489000_VBUS_VOLTAGE_TARGET		0x90
-#define RAA489000_VBUS_CURRENT_TARGET		0x92
-#define RAA489000_VBUS_OCP_UV_THRESHOLD		0x94
-#define RAA489000_TYPEC_SETTING1		0xC0
-#define RAA489000_PD_PHYSICAL_SETTING1		0xE0
-#define RAA489000_PD_PHYSICAL_PARAMETER1	0xE8
-
-/* TCPC_SETTING_1 */
-#define RAA489000_TCPCV1_0_EN		BIT(0)
-#define RAA489000_TCPC_PWR_CNTRL	BIT(4)
-
-/* VBUS_CURRENT_TARGET */
-#define RAA489000_VBUS_CURRENT_TARGET_3A	0x66 /* 3.0A + iOvershoot */
-#define RAA489000_VBUS_CURRENT_TARGET_1_5A	0x38 /* 1.5A + iOvershoot */
-
-/* VBUS_VOLTAGE_TARGET */
-#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV	0x102 /* 5.16V */
-#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV	0x105 /* 5.22V */
-
-/* VBUS_OCP_UV_THRESHOLD */
-/* Detect voltage level of overcurrent protection during Sourcing VBUS */
-#define RAA489000_OCP_THRESHOLD_VALUE 0x00BE /* 4.75V */
-
-/* TYPEC_SETTING1 - only older silicon */
-/* Enables for reverse current protection */
-#define RAA489000_SETTING1_IP2_EN	BIT(9)
-#define RAA489000_SETTING1_IP1_EN	BIT(8)
-
-/* Switches from dead-battery Rd */
-#define RAA489000_SETTING1_RDOE		BIT(7)
-
-/* CC comparator enables */
-#define RAA489000_SETTING1_CC2_CMP3_EN	BIT(6)
-#define RAA489000_SETTING1_CC2_CMP2_EN	BIT(5)
-#define RAA489000_SETTING1_CC2_CMP1_EN	BIT(4)
-#define RAA489000_SETTING1_CC1_CMP3_EN	BIT(3)
-#define RAA489000_SETTING1_CC1_CMP2_EN	BIT(2)
-#define RAA489000_SETTING1_CC1_CMP1_EN	BIT(1)
-
-/* CC debounce enable */
-#define RAA489000_SETTING1_CC_DB_EN	BIT(0)
-
-/* PD_PHYSICAL_SETTING_1 */
-#define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9)
-#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN  BIT(8)
-#define RAA489000_PD_PHY_SETTING1_TX_LDO11_EN BIT(0)
-
-/* PD_PHYSICAL_PARMETER_1 */
-#define PD_PHY_PARAM1_NOISE_FILTER_CNT_MASK (GENMASK(4, 0))
-
-/**
- *
- * Set output current limit on the TCPC.  Note, this chip also offers an OTG
- * current level register in the charger i2c page but we must use the TCPC
- * current limit because the TCPC is controlling Vbus.
- *
- * @param port	USB-C port number
- * @param rp	Rp value for current limit (either 1.5A or 3A)
- *
- * @return	Zero if the current limit set was successful, non-zero otherwise
- */
-int raa489000_set_output_current(int port, enum tcpc_rp_value rp);
-
-extern const struct tcpm_drv raa489000_tcpm_drv;
-
-#endif
diff --git a/driver/tcpm/rt1715.c b/driver/tcpm/rt1715.c
deleted file mode 100644
index ed3d283bc9..0000000000
--- a/driver/tcpm/rt1715.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Richtek RT1715 Type-C port controller */
-
-#include "common.h"
-#include "rt1715.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#ifndef CONFIG_USB_PD_TCPM_TCPCI
-#error "RT1715 is using a standard TCPCI interface"
-#error "Please upgrade your board configuration"
-#endif
-
-static int rt1715_polarity[CONFIG_USB_PD_PORT_MAX_COUNT];
-static bool rt1715_initialized[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-
-static int rt1715_enable_ext_messages(int port, int enable)
-{
-	return tcpc_update8(port, RT1715_REG_VENDOR_5,
-		  RT1715_REG_VENDOR_5_ENEXTMSG,
-		  enable ? MASK_SET : MASK_CLR);
-}
-
-static int rt1715_tcpci_tcpm_init(int port)
-{
-	int rv;
-	/*
-	 * Do not fully reinitialize the registers when leaving low-power mode.
-	 * TODO(b/179234089): Generalize this concept in the tcpm_drv API.
-	 */
-
-	/* Only do soft-reset on first init. */
-	if (!(rt1715_initialized[port])) {
-		/* RT1715 has a vendor-defined register reset */
-		rv = tcpc_update8(port, RT1715_REG_VENDOR_7,
-			RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
-		if (rv)
-			return rv;
-		rt1715_initialized[port] = true;
-		msleep(10);
-	}
-
-	rv = tcpc_update8(port, RT1715_REG_VENDOR_5,
-		  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		rt1715_enable_ext_messages(port, 1);
-
-	rv = tcpc_write(port, RT1715_REG_I2CRST_CTRL,
-		  (RT1715_REG_I2CRST_CTRL_EN |
-		  RT1715_REG_I2CRST_CTRL_TOUT_200MS));
-	if (rv)
-		return rv;
-
-	/* Unmask interrupt for LPM wakeup */
-	rv = tcpc_write(port, RT1715_REG_RT_MASK, RT1715_REG_RT_MASK_M_WAKEUP);
-	if (rv)
-		return rv;
-
-	/*
-	 * Set tTCPCFilter (CC debounce time) to 400 us
-	 * (min 250 us, max 500 us).
-	 */
-	rv = tcpc_write(port, RT1715_REG_TTCPC_FILTER,
-		  RT1715_REG_TTCPC_FILTER_400US);
-	if (rv)
-		return rv;
-
-	rv = tcpc_write(port, RT1715_REG_DRP_TOGGLE_CYCLE,
-		  RT1715_REG_DRP_TOGGLE_CYCLE_76MS);
-	if (rv)
-		return rv;
-
-	/* PHY control */
-	/* Set PHY control registers to Richtek recommended values */
-	rv = tcpc_write(port, RT1715_REG_PHY_CTRL1,
-		  (RT1715_REG_PHY_CTRL1_ENRETRY |
-		  RT1715_REG_PHY_CTRL1_TRANSCNT_7 |
-		  RT1715_REG_PHY_CTRL1_TRXFILTER_125NS));
-	if (rv)
-		return rv;
-
-	/* Set PHY control registers to Richtek recommended values */
-	rv = tcpc_write(port, RT1715_REG_PHY_CTRL2,
-		  RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US);
-	if (rv)
-		return rv;
-
-	return tcpci_tcpm_init(port);
-}
-
-/*
- * Selects the CC PHY noise filter voltage level according to the current
- * CC voltage level.
- *
- * @param cc_level The CC voltage level for the port's current role
- * @return EC_SUCCESS if writes succeed; failure code otherwise
- */
-static inline int rt1715_init_cc_params(int port, int cc_level)
-{
-	int rv, en, sel;
-
-	if (cc_level == TYPEC_CC_VOLT_RP_DEF) {
-		/* RXCC threshold : 0.55V */
-		en = RT1715_REG_BMCIO_RXDZEN_DISABLE;
-
-		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
-		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
-	} else {
-		/* RD threshold : 0.35V & RP threshold : 0.75V */
-		en = RT1715_REG_BMCIO_RXDZEN_ENABLE;
-
-		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
-		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
-	}
-
-	rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZEN, en);
-	if (!rv)
-		rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZSEL, sel);
-
-	return rv;
-}
-
-static int rt1715_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int rv;
-
-	rv = tcpci_tcpm_get_cc(port, cc1, cc2);
-	if (rv)
-		return rv;
-
-	return rt1715_init_cc_params(port, rt1715_polarity[port] ? *cc2 : *cc1);
-}
-
-/*
- * See b/179256608#comment26 for explanation.
- * Disable 24MHz oscillator and enable LPM. Upon exit from LPM, the LPEN will be
- * reset to 0.
- *
- * The exit condition for LPM is CC status change, and the wakeup interrupt will
- * be set.
- */
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int rt1715_enter_low_power_mode(int port)
-{
-	int regval;
-	int rv;
-
-	rv = tcpc_read(port, RT1715_REG_PWR, &regval);
-	if (rv)
-		return rv;
-
-	regval |= RT1715_REG_PWR_BMCIO_LPEN;
-	regval &= ~RT1715_REG_PWR_BMCIO_OSCEN;
-	rv = tcpc_write(port, RT1715_REG_PWR, regval);
-	if (rv)
-		return rv;
-
-	return tcpci_enter_low_power_mode(port);
-}
-#endif
-
-static int rt1715_set_vconn(int port, int enable)
-{
-	int rv;
-	int regval;
-
-	/*
-	 * Auto-idle cannot be used while sourcing Vconn.
-	 * See b/179256608#comment26 for explanation.
-	 */
-	rv = tcpc_read(port, RT1715_REG_VENDOR_5, &regval);
-	if (rv)
-		return rv;
-
-	if (enable)
-		regval &= ~RT1715_REG_VENDOR_5_AUTOIDLE_EN;
-	else
-		regval |= RT1715_REG_VENDOR_5_AUTOIDLE_EN;
-
-	rv = tcpc_write(port, RT1715_REG_VENDOR_5, regval);
-	if (rv)
-		return rv;
-
-	return tcpci_tcpm_set_vconn(port, enable);
-}
-
-static int rt1715_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	int rv;
-	enum tcpc_cc_voltage_status cc1, cc2;
-
-	rt1715_polarity[port] = polarity;
-
-	rv = tcpci_tcpm_get_cc(port, &cc1, &cc2);
-	if (rv)
-		return rv;
-
-	rv = rt1715_init_cc_params(port, polarity ? cc2 : cc1);
-	if (rv)
-		return rv;
-
-	return tcpci_tcpm_set_polarity(port, polarity);
-}
-
-static void rt1715_alert(int port)
-{
-	/*
-	 * Make sure the wakeup interrupt is cleared. This bit is set on wakeup
-	 * from LPM. See b/179256608#comment16 for explanation.
-	 */
-	tcpc_write(port, RT1715_REG_RT_INT, RT1715_REG_RT_INT_WAKEUP);
-
-	tcpci_tcpc_alert(port);
-}
-
-const struct tcpm_drv rt1715_tcpm_drv = {
-	.init = &rt1715_tcpci_tcpm_init,
-	.release = &tcpci_tcpm_release,
-	.get_cc = &rt1715_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value = &tcpci_tcpm_select_rp_value,
-	.set_cc = &tcpci_tcpm_set_cc,
-	.set_polarity = &rt1715_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable   = &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn = &rt1715_set_vconn,
-	.set_msg_header = &tcpci_tcpm_set_msg_header,
-	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
-	.get_message_raw = &tcpci_tcpm_get_message_raw,
-	.transmit = &tcpci_tcpm_transmit,
-	.tcpc_alert = &rt1715_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
-#endif
-	.tcpc_enable_auto_discharge_disconnect =
-		&tcpci_tcpc_enable_auto_discharge_disconnect,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle = &tcpci_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info = &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode = &rt1715_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-};
diff --git a/driver/tcpm/rt1715.h b/driver/tcpm/rt1715.h
deleted file mode 100644
index dcf2aa28d4..0000000000
--- a/driver/tcpm/rt1715.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Richtek RT1715 Type-C port controller */
-#ifndef __CROS_EC_USB_PD_TCPM_RT1715_H
-#define __CROS_EC_USB_PD_TCPM_RT1715_H
-
-/* I2C interface */
-#define RT1715_I2C_ADDR_FLAGS			0x4E
-
-#define RT1715_VENDOR_ID			0x29CF
-
-#define RT1715_REG_VENDOR_7			0xA0
-#define RT1715_REG_VENDOR_7_SOFT_RESET		BIT(0)
-
-#define RT1715_REG_PHY_CTRL1			0x80
-/* Wait for tReceive before retrying transmit in response to a bad GoodCRC */
-#define RT1715_REG_PHY_CTRL1_ENRETRY		BIT(7)
-/*
- * Bit 6:4 <TRANSCNT>: Consider CC to be idle if there are 7 or fewer BMC
- * transients observed in <46.67us>
- */
-#define RT1715_REG_PHY_CTRL1_TRANSCNT_7		0x70
-/*
- * Bit 1:0 <TRXFilter>: RX filter to make sure the stable received PD message.
- * default value is 01b
- * The debounce time is (register value + 2) * 41.67ns
- */
-#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS	0x01
-#define RT1715_REG_PHY_CTRL2			0x81
-/*
- * Decrease the time that the PHY will wait for a second transition to detect
- * a BMC-encoded 1 bit from 2.67 us to 2.25 us.
- * Timeout = register value * .04167 us.
- */
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US	54
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US	60
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US	62
-
-#define RT1715_REG_PWR				0x90
-#define RT1715_REG_PWR_BMCIO_LPEN		BIT(3)
-#define RT1715_REG_PWR_VBUS_DETEN		BIT(1)
-#define RT1715_REG_PWR_BMCIO_OSCEN		BIT(0)
-
-#define RT1715_REG_BMCIO_RXDZSEL		0x93
-#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA	BIT(7)
-#define RT1715_REG_BMCIO_RXDZSEL_SEL		BIT(0)
-
-#define RT1715_REG_RT_INT			0x98
-#define RT1715_REG_RT_INT_WAKEUP		BIT(0)
-
-#define RT1715_REG_RT_MASK			0x99
-#define RT1715_REG_RT_MASK_M_WAKEUP		BIT(0)
-
-#define RT1715_REG_VENDOR_5			0x9B
-#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF	BIT(5)
-#define RT1715_REG_VENDOR_5_ENEXTMSG		BIT(4)
-#define RT1715_REG_VENDOR_5_AUTOIDLE_EN		BIT(3)
-
-#define RT1715_REG_I2CRST_CTRL			0x9E
-/* I2C reset : (val + 1) * 12.5ms */
-#define RT1715_REG_I2CRST_CTRL_TOUT_200MS	0x0F
-#define RT1715_REG_I2CRST_CTRL_TOUT_150MS	0x0B
-#define RT1715_REG_I2CRST_CTRL_TOUT_100MS	0x07
-#define RT1715_REG_I2CRST_CTRL_EN		BIT(7)
-
-
-#define RT1715_REG_TTCPC_FILTER			0xA1
-#define RT1715_REG_TTCPC_FILTER_400US		0x0F
-
-#define RT1715_REG_DRP_TOGGLE_CYCLE		0xA2
-/* DRP Duty : (51.2 + 6.4 * val) ms */
-#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS	0x04
-
-#define RT1715_REG_DRP_DUTY_CTRL		0xA3
-#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT	400
-
-#define RT1715_REG_BMCIO_RXDZEN			0xAF
-#define RT1715_REG_BMCIO_RXDZEN_ENABLE		0x01
-#define RT1715_REG_BMCIO_RXDZEN_DISABLE		0x00
-
-extern const struct tcpm_drv rt1715_tcpm_drv;
-
-#endif /* defined(__CROS_EC_USB_PD_TCPM_RT1715_H) */
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c
deleted file mode 100644
index 9d5a8895ad..0000000000
--- a/driver/tcpm/rt1718s.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * RT1718S TCPC Driver
- */
-
-#include "console.h"
-#include "driver/tcpm/rt1718s.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "stdint.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#define RT1718S_SW_RESET_DELAY_MS 2
-
-/* i2c_write function which won't wake TCPC from low power mode. */
-static int rt1718s_write(int port, int reg, int val, int len)
-{
-	if (reg > 0xFF) {
-		return i2c_write_offset16(
-			tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			reg, val, len);
-	} else if (len == 1) {
-		return tcpc_write(port, reg, val);
-	} else {
-		return tcpc_write16(port, reg, val);
-	}
-}
-
-static int rt1718s_read(int port, int reg, int *val, int len)
-{
-	if (reg > 0xFF) {
-		return i2c_read_offset16(
-			tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			reg, val, len);
-	} else if (len == 1) {
-		return tcpc_read(port, reg, val);
-	} else {
-		return tcpc_read16(port, reg, val);
-	}
-}
-
-int rt1718s_write8(int port, int reg, int val)
-{
-	return rt1718s_write(port, reg, val, 1);
-}
-
-int rt1718s_read8(int port, int reg, int *val)
-{
-	return rt1718s_read(port, reg, val, 1);
-}
-
-int rt1718s_update_bits8(int port, int reg, int mask, int val)
-{
-	int reg_val;
-
-	if (mask == 0xFF)
-		return rt1718s_write8(port, reg, val);
-
-	RETURN_ERROR(rt1718s_read8(port, reg, &reg_val));
-
-	reg_val &= (~mask);
-	reg_val |= (mask & val);
-	return rt1718s_write8(port, reg, reg_val);
-}
-
-int rt1718s_write16(int port, int reg, int val)
-{
-	return rt1718s_write(port, reg, val, 2);
-}
-
-int rt1718s_read16(int port, int reg, int *val)
-{
-	return rt1718s_read(port, reg, val, 2);
-}
-
-
-static int rt1718s_sw_reset(int port)
-{
-	int rv;
-
-	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3,
-		RT1718S_SWRESET_MASK, 0xFF);
-
-	msleep(RT1718S_SW_RESET_DELAY_MS);
-
-	return rv;
-}
-
-/* enable bc 1.2 sink function  */
-static int rt1718s_enable_bc12_sink(int port, bool en)
-{
-	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN,
-			en ? 0xFF : 0);
-}
-
-static int rt1718s_set_bc12_sink_spec_ta(int port, bool en)
-{
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN, en ? 0xFF : 0);
-}
-
-static int rt1718s_set_bc12_sink_dcdt_sel(int port, uint8_t dcdt_sel)
-{
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK, dcdt_sel);
-}
-
-static int rt1718s_set_bc12_sink_vlgc_option(int port, bool en)
-{
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT, en ? 0xFF : 0);
-}
-
-static int rt1718s_set_bc12_sink_vport_sel(int port, uint8_t sel)
-{
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel);
-}
-
-static int rt1718s_set_bc12_sink_wait_vbus(int port, bool en)
-{
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS,
-			en ? 0xFF : 0);
-}
-
-/*
- * rt1718s BC12 function initial
- */
-static int rt1718s_bc12_init(int port)
-{
-	/* Enable vendor defined BC12 function */
-	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT_MASK6,
-			RT1718S_RT_MASK6_M_BC12_SNK_DONE |
-			RT1718S_RT_MASK6_M_BC12_TA_CHG));
-
-	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01,
-			RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN |
-			RT1718S_RT2_SBU_CTRL_01_DM_SWEN |
-			RT1718S_RT2_SBU_CTRL_01_DP_SWEN));
-
-	/* Disable 2.7v mode */
-	RETURN_ERROR(rt1718s_set_bc12_sink_spec_ta(port, false));
-
-	/* DCDT select 600ms timeout */
-	RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel(port,
-			RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS));
-
-	/* Disable vlgc option */
-	RETURN_ERROR(rt1718s_set_bc12_sink_vlgc_option(port, false));
-
-	/* DPDM voltage selection */
-	RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel(port,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V));
-
-	/* Disable sink wait vbus */
-	RETURN_ERROR(rt1718s_set_bc12_sink_wait_vbus(port, false));
-
-	return EC_SUCCESS;
-}
-
-static int rt1718s_workaround(int port)
-{
-	int device_id;
-
-	RETURN_ERROR(tcpc_read16(port, RT1718S_DEVICE_ID, &device_id));
-
-	switch (device_id) {
-	case RT1718S_DEVICE_ID_ES1:
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3,
-					RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG,
-					0xFF));
-		/* fallthrough */
-	case RT1718S_DEVICE_ID_ES2:
-		RETURN_ERROR(rt1718s_update_bits8(port, TCPC_REG_FAULT_CTRL,
-					TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS,
-					0xFF));
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4,
-					RT1718S_VCON_CTRL4_UVP_CP_EN |
-					RT1718S_VCON_CTRL4_OVP_CP_EN,
-					0));
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_2,
-					RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 |
-					RT1718S_VCONN_CONTROL_2_OVP_EN_CC2,
-					0xFF));
-		break;
-	default:
-		/* do nothing */
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int rt1718s_init(int port)
-{
-	static bool need_sw_reset = true;
-
-	if (!system_jumped_late() && need_sw_reset) {
-		RETURN_ERROR(rt1718s_sw_reset(port));
-		need_sw_reset = false;
-	}
-
-	RETURN_ERROR(rt1718s_bc12_init(port));
-
-	/* Set VBUS_VOL_SEL to 20V */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_VBUS_VOL_CTRL,
-				RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL,
-				RT1718S_VBUS_VOL_TO_REG(20)));
-
-	/* Disable FOD function */
-	RETURN_ERROR(rt1718s_update_bits8(port, 0xCF, 0x40, 0x00));
-
-	/* Tcpc connect invalid disabled. Exit shipping mode */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1,
-				RT1718S_SYS_CTRL1_TCPC_CONN_INVALID, 0x00));
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1,
-				RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF));
-
-	/* Clear alert and fault */
-	RETURN_ERROR(rt1718s_write8(port, TCPC_REG_FAULT_STATUS, 0xFF));
-	RETURN_ERROR(tcpc_write16(port, TCPC_REG_ALERT, 0xFFFF));
-
-	RETURN_ERROR(tcpci_tcpm_init(port));
-
-	RETURN_ERROR(rt1718s_workaround(port));
-	/*
-	 * Set vendor defined alert unmasked, this must be done after
-	 * tcpci_tcpm_init.
-	 */
-	RETURN_ERROR(tcpc_update16(port, TCPC_REG_ALERT_MASK,
-				TCPC_REG_ALERT_MASK_VENDOR_DEF,
-				MASK_SET));
-
-	RETURN_ERROR(board_rt1718s_init(port));
-
-	return EC_SUCCESS;
-}
-
-__overridable int board_rt1718s_init(int port)
-{
-	return EC_SUCCESS;
-}
-
-static enum charge_supplier rt1718s_get_bc12_type(int port)
-{
-	int data;
-
-	if (rt1718s_read8(port, RT1718S_RT2_BC12_STAT, &data))
-		return CHARGE_SUPPLIER_OTHER;
-
-	switch (data & RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK) {
-	case RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE:
-		return CHARGE_SUPPLIER_NONE;
-	case RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP:
-		return CHARGE_SUPPLIER_BC12_SDP;
-	case RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP:
-		return CHARGE_SUPPLIER_BC12_CDP;
-	case RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP:
-		return CHARGE_SUPPLIER_BC12_DCP;
-	}
-
-	return CHARGE_SUPPLIER_OTHER;
-}
-
-static int rt1718s_get_bc12_ilim(enum charge_supplier supplier)
-{
-	switch (supplier) {
-	case CHARGE_SUPPLIER_BC12_DCP:
-	case CHARGE_SUPPLIER_BC12_CDP:
-		return USB_CHARGER_MAX_CURR_MA;
-	case CHARGE_SUPPLIER_BC12_SDP:
-	default:
-		return USB_CHARGER_MIN_CURR_MA;
-	}
-}
-
-static void rt1718s_update_charge_manager(int port,
-					  enum charge_supplier new_bc12_type)
-{
-	static enum charge_supplier current_bc12_type = CHARGE_SUPPLIER_NONE;
-
-	if (new_bc12_type != current_bc12_type) {
-		if (current_bc12_type != CHARGE_SUPPLIER_NONE)
-			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
-
-		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
-			struct charge_port_info chg = {
-				.current = rt1718s_get_bc12_ilim(new_bc12_type),
-				.voltage = USB_CHARGER_VOLTAGE_MV,
-			};
-
-			charge_manager_update_charge(new_bc12_type, port, &chg);
-		}
-
-		current_bc12_type = new_bc12_type;
-	}
-}
-
-static void rt1718s_bc12_usb_charger_task(const int port)
-{
-	rt1718s_enable_bc12_sink(port, false);
-
-	while (1) {
-		uint32_t evt = task_wait_event(-1);
-
-		if (evt & USB_CHG_EVENT_VBUS) {
-			if (pd_snk_is_vbus_provided(port))
-				rt1718s_enable_bc12_sink(port, true);
-			else
-				rt1718s_update_charge_manager(
-						port, CHARGE_SUPPLIER_NONE);
-		}
-
-		/* detection done, update charge_manager and stop detection */
-		if (evt & USB_CHG_EVENT_BC12) {
-			int type = rt1718s_get_bc12_type(port);
-
-			rt1718s_update_charge_manager(
-					port, type);
-			rt1718s_enable_bc12_sink(port, false);
-		}
-	}
-}
-
-void rt1718s_vendor_defined_alert(int port)
-{
-	int rv, value;
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC) &&
-	    IS_ENABLED(CONFIG_USBC_PPC_RT1718S)) {
-		int int1;
-
-		rv = rt1718s_read8(port, RT1718S_RT_INT1, &int1);
-		if (rv)
-			return;
-		rv = rt1718s_write8(port, RT1718S_RT_INT1, int1);
-		if (rv)
-			return;
-
-		if ((int1 & RT1718S_RT_INT1_INT_RX_FRS)) {
-			pd_got_frs_signal(port);
-
-			tcpc_write16(port, TCPC_REG_ALERT,
-					TCPC_REG_ALERT_VENDOR_DEF);
-			/* ignore other interrupts for faster frs handling */
-			return;
-		}
-	}
-
-	/* Process BC12 alert */
-	rv = rt1718s_read8(port, RT1718S_RT_INT6, &value);
-	if (rv)
-		return;
-
-	/* clear BC12 alert */
-	rv = rt1718s_write8(port, RT1718S_RT_INT6, value);
-	if (rv)
-		return;
-
-	/* check snk done */
-	if (value & RT1718S_RT_INT6_INT_BC12_SNK_DONE)
-		task_set_event(USB_CHG_PORT_TO_TASK_ID(port),
-			       USB_CHG_EVENT_BC12);
-
-	/* clear the alerts from rt1718s_workaround() */
-	rv = rt1718s_write8(port, RT1718S_RT_INT2, 0xFF);
-	if (rv)
-		return;
-	/* ES1 workaround: disable Vconn discharge */
-	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
-			RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN,
-			0);
-	if (rv)
-		return;
-
-	tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF);
-}
-
-static void rt1718s_alert(int port)
-{
-	int alert;
-
-	tcpc_read16(port, TCPC_REG_ALERT, &alert);
-	if (alert & TCPC_REG_ALERT_VENDOR_DEF)
-		rt1718s_vendor_defined_alert(port);
-
-	if (alert & ~TCPC_REG_ALERT_VENDOR_DEF)
-		tcpci_tcpc_alert(port);
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static int rt1718s_enter_low_power_mode(int port)
-{
-	/* enter low power mode */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
-					  RT1718S_SYS_CTRL2_LPWR_EN, 0xFF));
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
-					  RT1718S_SYS_CTRL2_BMCIO_OSC_EN, 0));
-
-	/* disable DP/DM/SBU swtiches */
-	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01, 0));
-
-	return tcpci_enter_low_power_mode(port);
-}
-#endif
-
-int rt1718s_get_adc(int port, enum rt1718s_adc_channel channel, int *adc_val)
-{
-	static struct mutex adc_lock;
-	int rv;
-	const int max_wait_times = 30;
-
-	if (in_interrupt_context()) {
-		CPRINTS("Err: use ADC in IRQ");
-		return EC_ERROR_INVAL;
-	}
-
-	mutex_lock(&adc_lock);
-
-	/* Start ADC conversation */
-	rv = rt1718s_write16(port, RT1718S_ADC_CTRL_01, BIT(channel));
-	if (rv)
-		goto out;
-
-	/*
-	 * The expected conversion time is 85.3us * number of enabled channels.
-	 * Polling for 3ms should be long enough.
-	 */
-	for (int i = 0; i < max_wait_times; i++) {
-		int adc_done;
-
-		usleep(100);
-		rv = rt1718s_read8(port, RT1718S_RT_INT6, &adc_done);
-		if (rv)
-			goto out;
-		if (adc_done & RT1718S_RT_INT6_INT_ADC_DONE)
-			break;
-		if (i == max_wait_times - 1) {
-			CPRINTS("conversion fail channel=%d", channel);
-			rv = EC_ERROR_TIMEOUT;
-			goto out;
-		}
-	}
-
-	/* Read ADC data */
-	rv = rt1718s_read16(port, RT1718S_ADC_CHX_VOL_L(channel), adc_val);
-	if (rv)
-		goto out;
-
-	/*
-	 * The resolution of VBUS1 ADC is 12.5mV,
-	 * other channels are 4mV.
-	 */
-	if (channel == RT1718S_ADC_VBUS1)
-		*adc_val = *adc_val * 125 / 10;
-	else
-		*adc_val *= 4;
-
-out:
-	/* Cleanup: disable adc and clear interrupt. Error ignored. */
-	rt1718s_write16(port, RT1718S_ADC_CTRL_01, 0);
-	rt1718s_write8(port, RT1718S_RT_INT6, RT1718S_RT_INT6_INT_ADC_DONE);
-
-	mutex_unlock(&adc_lock);
-	return rv;
-}
-
-void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags)
-{
-	int val = 0;
-
-	if (!(flags & GPIO_OPEN_DRAIN))
-		val |= RT1718S_GPIO_CTRL_OD_N;
-	if (flags & GPIO_PULL_UP)
-		val |= RT1718S_GPIO_CTRL_PU;
-	if (flags & GPIO_PULL_DOWN)
-		val |= RT1718S_GPIO_CTRL_PD;
-	if (flags & GPIO_HIGH)
-		val |= RT1718S_GPIO_CTRL_O;
-	if (flags & GPIO_OUTPUT)
-		val |= RT1718S_GPIO_CTRL_OE;
-
-	rt1718s_write8(port, RT1718S_GPIO_CTRL(signal), val);
-}
-
-void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value)
-{
-	rt1718s_update_bits8(port, RT1718S_GPIO_CTRL(signal),
-			RT1718S_GPIO_CTRL_O,
-			value ? 0xFF : 0);
-}
-
-int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal)
-{
-	int val;
-
-	rt1718s_read8(port, RT1718S_GPIO_CTRL(signal), &val);
-	return !!(val & RT1718S_GPIO_CTRL_I);
-}
-
-/* RT1718S is a TCPCI compatible port controller */
-const struct tcpm_drv rt1718s_tcpm_drv = {
-	.init			= &rt1718s_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &rt1718s_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &rt1718s_enter_low_power_mode,
-#endif
-};
-
-const struct bc12_drv rt1718s_bc12_drv = {
-	.usb_charger_task = rt1718s_bc12_usb_charger_task,
-};
diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h
deleted file mode 100644
index 07c3ed3f82..0000000000
--- a/driver/tcpm/rt1718s.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_PD_TCPM_RT1718S_H
-#define __CROS_EC_USB_PD_TCPM_RT1718S_H
-
-#include "util.h"
-#include "usb_charge.h"
-#include "usb_pd_tcpm.h"
-
-/* RT1718S Private RegMap */
-#define RT1718S_I2C_ADDR_FLAGS				0x43
-
-#define RT1718S_VID					0x29CF
-#define RT1718S_PID					0x1718
-
-#define RT1718S_DEVICE_ID				0x04
-#define RT1718S_DEVICE_ID_ES1				0x4511
-#define RT1718S_DEVICE_ID_ES2				0x4513
-
-#define RT1718S_PHYCTRL1				0x80
-#define RT1718S_PHYCTRL2				0x81
-#define RT1718S_PHYCTRL3				0x82
-#define RT1718S_PHYCTRL7				0x86
-#define RT1718S_VCON_CTRL1				0x8A
-#define RT1718S_VCON_CTRL3				0x8C
-#define RT1718S_SYS_CTRL1				0x8F
-#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID		BIT(6)
-#define RT1718S_SYS_CTRL1_SHIPPING_OFF			BIT(5)
-#define RT1718S_SYS_CTRL2				0x90
-#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN			BIT(0)
-#define RT1718S_SYS_CTRL2_LPWR_EN			BIT(3)
-
-#define RT1718S_VCONN_CONTROL_2				0x8B
-#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1		BIT(7)
-#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2		BIT(6)
-#define RT1718S_VCONN_CONTROL_3				0x8C
-#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG		BIT(1)
-
-#define RT1718S_SYS_CTRL2				0x90
-#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN		BIT(5)
-
-#define RT1718S_RT_MASK1				0x91
-#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW			BIT(7)
-#define RT1718S_RT_MASK1_M_RX_FRS			BIT(6)
-#define RT1718S_RT_MASK2				0x92
-#define RT1718S_RT_MASK3				0x93
-#define RT1718S_RT_MASK4				0x94
-#define RT1718S_RT_MASK5				0x95
-#define RT1718S_RT_MASK6				0x96
-#define RT1718S_RT_MASK6_M_BC12_SNK_DONE		BIT(7)
-#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE		BIT(6)
-#define RT1718S_RT_MASK6_M_BC12_TA_CHG			BIT(5)
-#define RT1718S_RT_MASK7				0x97
-
-#define RT1718S_RT_INT1					0x98
-#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW		BIT(7)
-#define RT1718S_RT_INT1_INT_RX_FRS			BIT(6)
-#define RT1718S_RT_INT2					0x99
-#define RT1718S_RT_INT6					0x9D
-#define RT1718S_RT_INT6_INT_BC12_SNK_DONE		BIT(7)
-#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE		BIT(6)
-#define RT1718S_RT_INT6_INT_BC12_TA_CHG			BIT(5)
-#define RT1718S_RT_INT6_INT_ADC_DONE			BIT(0)
-
-#define RT1718S_RT_ST6					0xA4
-#define RT1718S_RT_ST6_BC12_SNK_DONE			BIT(7)
-#define RT1718S_RT_ST6_HVDCP_CHK_DONE			BIT(6)
-#define RT1718S_RT_ST6_BC12_TA_CHG			BIT(5)
-
-#define RT1718S_PHYCTRL9				0xAC
-
-#define RT1718S_SYS_CTRL3				0xB0
-#define RT1718S_TCPC_CTRL1				0xB1
-#define RT1718S_TCPC_CTRL2				0xB2
-#define RT1718S_TCPC_CTRL3				0xB3
-#define RT1718S_SWRESET_MASK				BIT(0)
-#define RT1718S_TCPC_CTRL4				0xB4
-#define RT1718S_SYS_CTRL4				0xB8
-#define RT1718S_WATCHDOG_CTRL				0xBE
-#define RT1718S_I2C_RST_CTRL				0xBF
-
-#define RT1718S_HILO_CTRL9				0xC8
-#define RT1718S_SHILED_CTRL1				0xCA
-#define RT1718S_FRS_CTRL1				0xCB
-#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK			0xF0
-#define RT1718S_FRS_CTRL2				0xCC
-#define RT1718S_FRS_CTRL2_RX_FRS_EN			BIT(6)
-#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT		BIT(4)
-#define RT1718S_FRS_CTRL2_VBUS_FRS_EN			BIT(3)
-#define RT1718S_FRS_CTRL3				0xCE
-#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2		BIT(3)
-#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1		BIT(2)
-
-#define RT1718S_DIS_SRC_VBUS_CTRL			0xE0
-#define RT1718S_ENA_SRC_VBUS_CTRL			0xE1
-#define RT1718S_FAULT_OC1_VBUS_CTRL			0xE3
-#define RT1718S_GPIO1_VBUS_CTRL				0xEA
-#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
-#define RT1718S_GPIO2_VBUS_CTRL				0xEB
-#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
-#define RT1718S_VBUS_CTRL_EN				0xEC
-#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN		BIT(7)
-#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN		BIT(6)
-
-#define RT1718S_GPIO_CTRL(n)				(0xED + (n))
-#define RT1718S_GPIO_CTRL_PU				BIT(5)
-#define RT1718S_GPIO_CTRL_PD				BIT(4)
-#define RT1718S_GPIO_CTRL_OD_N				BIT(3)
-#define RT1718S_GPIO_CTRL_OE				BIT(2)
-#define RT1718S_GPIO_CTRL_O				BIT(1)
-#define RT1718S_GPIO_CTRL_I				BIT(0)
-
-#define RT1718S_UNLOCK_PW_2				0xF0
-#define RT1718S_UNLOCK_PW_1				0xF1
-
-#define RT1718S_RT2_SYS_CTRL5				0xF210
-
-#define RT1718S_VBUS_VOL_TO_REG(_vol)			(CLAMP(_vol, 5, 20) - 5)
-#define RT1718S_VBUS_PCT_TO_REG(_pct)			(CLAMP(_pct, 5, 20) \
-							/ 5 - 1)
-#define RT1718S_RT2_VBUS_VOL_CTRL			0xF213
-#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL		(BIT(5) | BIT(4))
-#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL		0x0F
-
-#define RT1718S_VCON_CTRL4				0xF211
-#define RT1718S_VCON_CTRL4_UVP_CP_EN			BIT(5)
-#define RT1718S_VCON_CTRL4_OVP_CP_EN			BIT(4)
-
-#define RT1718S_RT2_VBUS_OCRC_EN			0xF214
-#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN		BIT(0)
-#define RT1718S_RT2_VBUS_OCP_CTRL1			0xF216
-#define RT1718S_RT2_VBUS_OCP_CTRL4			0xF219
-
-#define RT1718S_RT2_SBU_CTRL_01				0xF23A
-#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN		BIT(7)
-#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN		BIT(6)
-#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN		BIT(3)
-#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN		BIT(2)
-#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN			BIT(1)
-#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN			BIT(0)
-
-#define RT1718S_RT2_BC12_SNK_FUNC			0xF260
-#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN		BIT(7)
-#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN		BIT(6)
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK		0x30
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE	0x00
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS	0x10
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS	0x20
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA	0x30
-#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT		BIT(3)
-#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL		BIT(2)
-#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS	BIT(1)
-
-#define RT1718S_RT2_BC12_STAT				0xF261
-#define RT1718S_RT2_BC12_STAT_DCDT			BIT(4)
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK		0x0F
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE		0x00
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP		0x0D
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP		0x0E
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP		0x0F
-
-
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET			0xF263
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK	0x03
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V	0x00
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V	0x01
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V	0x02
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V	0x03
-
-#define RT1718S_RT2_BC12_SRC_FUNC			0xF26D
-#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN		BIT(7)
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK	0x70
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP	0x00
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP	0x10
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP	0x20
-#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON		BIT(0)
-
-#define RT1718S_ADC_CTRL_01				0xF2A0
-#define RT1718S_ADC_CTRL_02				0xF2A1
-#define RT1718S_ADC_CHX_VOL_L(ch)			(0xF2A6 + (ch) * 2)
-#define RT1718S_ADC_CHX_VOL_H(ch)			(0xF2A7 + (ch) * 2)
-
-extern const struct tcpm_drv rt1718s_tcpm_drv;
-extern const struct bc12_drv rt1718s_bc12_drv;
-
-int rt1718s_write8(int port, int reg, int val);
-int rt1718s_read8(int port, int reg, int *val);
-int rt1718s_update_bits8(int port, int reg, int mask, int val);
-int rt1718s_write16(int port, int reg, int val);
-int rt1718s_read16(int port, int reg, int *val);
-__override_proto int board_rt1718s_init(int port);
-
-enum rt1718s_adc_channel {
-	RT1718S_ADC_VBUS1 = 0,
-	RT1718S_ADC_VBUS2,
-	RT1718S_ADC_VDC,
-	RT1718S_ADC_VBUS_CURRENT,
-	RT1718S_ADC_CC1,
-	RT1718S_ADC_CC2,
-	RT1718S_ADC_SBU1,
-	RT1718S_ADC_SBU2,
-	RT1718S_ADC_DP,
-	RT1718S_ADC_DM,
-	RT1718S_ADC_CH10,
-	RT1718S_ADC_CH11,
-};
-
-int rt1718s_get_adc(int port, enum rt1718s_adc_channel channel, int *adc_val);
-
-enum rt1718s_gpio {
-	RT1718S_GPIO1 = 0,
-	RT1718S_GPIO2,
-	RT1718S_GPIO3,
-};
-
-/**
- * Set flags for GPIO
- *
- * @param port		rt1718s I2C port
- * @param signal	gpio pin name in enum rt1718s_gpio
- * @param flags		GPIO_* flags defined in include/gpio.h
- */
-void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags);
-
-/**
- * Set the value of a signal
- *
- * @param port		rt1718s I2C port
- * @param signal	gpio pin name in enum rt1718s_gpio
- * @param value		New value for signal (0 = low, non-zero = high)
- */
-void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value);
-
-/**
- * Get the current value of a signal.
- *
- * @param port		rt1718s I2C port
- * @param signal	gpio pin name in enum rt1718s_gpio
- * @return 0 if low, 1 if high.
- */
-int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal);
-
-#endif /* __CROS_EC_USB_PD_TCPM_MT6370_H */
diff --git a/driver/tcpm/stm32gx.c b/driver/tcpm/stm32gx.c
deleted file mode 100644
index 359c7c1108..0000000000
--- a/driver/tcpm/stm32gx.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TCPM for STM32Gx UCPD module */
-
-#include "chip/stm32/ucpd-stm32gx.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "registers.h"
-#include "stm32gx.h"
-#include "system.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "hooks.h"
-
-/*
- * STM32G4 UCPD peripheral does not have the ability to detect VBUS, but
- * CONFIG_USB_PD_VBUS_DETECT_TCPC maybe still be defined for another port on the
- * same board which uses a TCPC that does have this feature. Therefore, this
- * config option is not considered an error.
- */
-#if defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-#error "Unsupported config options of Stm32gx PD driver"
-#endif
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-/* Wait time for vconn power switch to turn off. */
-#ifndef PD_STM32GX_VCONN_TURN_OFF_DELAY_US
-#define PD_STM32GX_VCONN_TURN_OFF_DELAY_US 500
-#endif
-
-static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-
-static int stm32gx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
-{
-	return stm32gx_ucpd_get_message_raw(port, buf, head);
-}
-
-static int stm32gx_tcpm_init(int port)
-{
-	return stm32gx_ucpd_init(port);
-}
-
-static int stm32gx_tcpm_release(int port)
-{
-	return stm32gx_ucpd_release(port);
-}
-
-static int stm32gx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	/* Get cc_state value for each CC line */
-	stm32gx_ucpd_get_cc(port, cc1, cc2);
-
-	return EC_SUCCESS;
-}
-
-static int stm32gx_tcpm_select_rp_value(int port, int rp_sel)
-{
-	cached_rp[port] = rp_sel;
-
-	return EC_SUCCESS;
-}
-
-static int stm32gx_tcpm_set_cc(int port, int pull)
-{
-	return stm32gx_ucpd_set_cc(port, pull, cached_rp[port]);
-}
-
-static int stm32gx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return stm32gx_ucpd_set_polarity(port, polarity);
-}
-
-static int stm32gx_tcpm_set_vconn(int port, int enable)
-{
-	stm32gx_ucpd_vconn_disc_rp(port, enable);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		stm32gx_ucpd_sop_prime_enable(port, enable);
-
-	return EC_SUCCESS;
-}
-
-static int stm32gx_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return stm32gx_ucpd_set_msg_header(port, power_role, data_role);
-}
-
-static int stm32gx_tcpm_set_rx_enable(int port, int enable)
-{
-	return stm32gx_ucpd_set_rx_enable(port, enable);
-}
-
-static int stm32gx_tcpm_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			const uint32_t *data)
-{
-	return stm32gx_ucpd_transmit(port, type, header, data);
-}
-
-static int stm32gx_tcpm_sop_prime_enable(int port, bool enable)
-{
-	return stm32gx_ucpd_sop_prime_enable(port, enable);
-}
-
-
-static int stm32gx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	return stm32gx_ucpd_get_chip_info(port, live, chip_info);
-}
-
-static void stm32gx_tcpm_sw_reset(void)
-{
-	/*
-	 * TODO(b/167601672): Not sure if this hook is required for UCPD as
-	 * opposed to TCPCI compliant TCPC. Leaving this a placeholder so I
-	 * don't forget to pull this back in, if required.
-	 */
-}
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, stm32gx_tcpm_sw_reset, HOOK_PRIO_DEFAULT);
-
-static int stm32gx_tcpm_reset_bist_type_2(int port)
-{
-	/*
-	 * The UCPD peripheral must be disabled, then enabled, to recover from
-	 * starting BIST type-2 mode. Call the init method to accomplish
-	 * this. Then, need to send a hard reset to port partner.
-	 */
-	stm32gx_ucpd_init(port);
-	pd_execute_hard_reset(port);
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list stm32gx_tcpm_set_bist_test_mode(const int port,
-		const bool enable)
-{
-	return stm32gx_ucpd_set_bist_test_mode(port, enable);
-}
-
-bool stm32gx_tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	/*
-	 * UCPD peripheral can't detect VBUS, so always return 0. Any port which
-	 * uses the stm32g4 UCPD peripheral for its TCPC would also have a PPC
-	 * that will handle VBUS detection. However, there may be products which
-	 * don't have a PPC on some ports that will rely on a TCPC to do VBUS
-	 * detection.
-	 */
-	return 0;
-}
-
-const struct tcpm_drv stm32gx_tcpm_drv = {
-	.init			= &stm32gx_tcpm_init,
-	.release		= &stm32gx_tcpm_release,
-	.get_cc			= &stm32gx_tcpm_get_cc,
-	.check_vbus_level	= &stm32gx_tcpm_check_vbus_level,
-	.select_rp_value	= &stm32gx_tcpm_select_rp_value,
-	.set_cc			= &stm32gx_tcpm_set_cc,
-	.set_polarity		= &stm32gx_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable      = &stm32gx_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &stm32gx_tcpm_set_vconn,
-	.set_msg_header		= &stm32gx_tcpm_set_msg_header,
-	.set_rx_enable		= &stm32gx_tcpm_set_rx_enable,
-	.get_message_raw	= &stm32gx_tcpm_get_message_raw,
-	.transmit		= &stm32gx_tcpm_transmit,
-	.get_chip_info		= &stm32gx_tcpm_get_chip_info,
-	.reset_bist_type_2	= &stm32gx_tcpm_reset_bist_type_2,
-	.set_bist_test_mode	= &stm32gx_tcpm_set_bist_test_mode,
-};
diff --git a/driver/tcpm/stm32gx.h b/driver/tcpm/stm32gx.h
deleted file mode 100644
index de6a803d52..0000000000
--- a/driver/tcpm/stm32gx.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-#ifndef __CROS_EC_DRIVER_TCPM_STM32GX_H
-#define __CROS_EC_DRIVER_TCPM_STM32GX_H
-
-
-extern const struct tcpm_drv stm32gx_tcpm_drv;
-
-
-#endif /* __CROS_EC_DRIVER_TCPM_STM32GX_H */
diff --git a/driver/tcpm/stub.c b/driver/tcpm/stub.c
deleted file mode 100644
index 863a88c044..0000000000
--- a/driver/tcpm/stub.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TCPM for MCU also running TCPC */
-
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-
-static int init_alert_mask(int port)
-{
-	uint16_t mask;
-	int rv;
-
-	/*
-	 * Create mask of alert events that will cause the TCPC to
-	 * signal the TCPM via the Alert# gpio line.
-	 */
-	mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-		TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-		TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
-	/* Set the alert mask in TCPC */
-	rv = tcpc_alert_mask_set(port, mask);
-
-	return rv;
-}
-
-static int init_power_status_mask(int port)
-{
-	return tcpc_set_power_status_mask(port, 0);
-}
-
-int tcpm_init(int port)
-{
-	int rv;
-
-	tcpc_init(port);
-	rv = init_alert_mask(port);
-	if (rv)
-		return rv;
-
-	return init_power_status_mask(port);
-}
-
-int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	return tcpc_get_cc(port, cc1, cc2);
-}
-
-int tcpm_select_rp_value(int port, int rp)
-{
-	return tcpc_select_rp_value(port, rp);
-}
-
-int tcpm_set_cc(int port, int pull)
-{
-	return tcpc_set_cc(port, pull);
-}
-
-int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return tcpc_set_polarity(port, polarity_rm_dts(polarity));
-}
-
-int tcpm_set_vconn(int port, int enable)
-{
-	return tcpc_set_vconn(port, enable);
-}
-
-int tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return tcpc_set_msg_header(port, power_role, data_role);
-}
-
-static int tcpm_alert_status(int port, int *alert)
-{
-	/* Read TCPC Alert register */
-	return tcpc_alert_status(port, alert);
-}
-
-int tcpm_set_rx_enable(int port, int enable)
-{
-	return tcpc_set_rx_enable(port, enable);
-}
-
-void tcpm_enable_auto_discharge_disconnect(int port, int enable)
-{
-}
-
-int tcpm_has_pending_message(int port)
-{
-	return !rx_buf_is_empty(port);
-}
-
-int tcpm_dequeue_message(int port, uint32_t *payload, int *head)
-{
-	int ret = tcpc_get_message(port, payload, head);
-
-	/* Read complete, clear RX status alert bit */
-	tcpc_alert_status_clear(port, TCPC_REG_ALERT_RX_STATUS);
-
-	return ret;
-}
-
-void tcpm_clear_pending_messages(int port)
-{
-	rx_buf_clear(port);
-}
-
-int tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
-		  const uint32_t *data)
-{
-	return tcpc_transmit(port, type, header, data);
-}
-
-void tcpc_alert(int port)
-{
-	int status;
-
-	/* Read the Alert register from the TCPC */
-	tcpm_alert_status(port, &status);
-
-	/*
-	 * Clear alert status for everything except RX_STATUS, which shouldn't
-	 * be cleared until we have successfully retrieved message.
-	 */
-	if (status & ~TCPC_REG_ALERT_RX_STATUS)
-		tcpc_alert_status_clear(port,
-					status & ~TCPC_REG_ALERT_RX_STATUS);
-
-	if (status & TCPC_REG_ALERT_CC_STATUS) {
-		/* CC status changed, wake task */
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-	}
-	if (status & TCPC_REG_ALERT_RX_STATUS) {
-		/*
-		 * message received. since TCPC is compiled in, we
-		 * already woke the PD task up from the phy layer via
-		 * pd_rx_event(), so we don't need to wake it again.
-		 */
-	}
-	if (status & TCPC_REG_ALERT_RX_HARD_RST) {
-		/* hard reset received */
-		task_set_event(PD_PORT_TO_TASK_ID(port),
-			       PD_EVENT_RX_HARD_RESET);
-	}
-	if (status & TCPC_REG_ALERT_TX_COMPLETE) {
-		/* transmit complete */
-		pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
-	}
-}
diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c
deleted file mode 100644
index 1e08e0967d..0000000000
--- a/driver/tcpm/tcpci.c
+++ /dev/null
@@ -1,1838 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Type-C port manager */
-
-#include "atomic.h"
-#include "anx74xx.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ps8xxx.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_common.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_flags.h"
-#include "usb_pd_tcpc.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#define TCPC_FLAGS_VSAFE0V(_flags) \
-	((_flags & TCPC_FLAGS_TCPCI_REV2_0) && \
-		!(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V))
-
-/****************************************************************************
- * TCPCI DEBUG Helpers
- */
-
-/* TCPCI FAULT-0x01 is an invalid I2C operation was performed.  This tends
- * to have to do with the state of registers and the last write operation.
- * Defining DEBUG_I2C_FAULT_LAST_WRITE_OP will track the write operations,
- * excluding XFER and BlockWrites, in an attempt to give clues as to what
- * was written to the TCPCI that caused the issue.
- */
-#undef DEBUG_I2C_FAULT_LAST_WRITE_OP
-
-struct i2c_wrt_op {
-	int addr;
-	int reg;
-	int val;
-	int mask;
-};
-STATIC_IF(DEBUG_I2C_FAULT_LAST_WRITE_OP)
-	struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * AutoDischargeDisconnect has caused a number of issues with the
- * feature not being correctly enabled/disabled.  Defining
- * DEBUG_AUTO_DISCHARGE_DISCONNECT will output a line for each enable
- * and disable to help better understand any AutoDischargeDisconnect
- * issues.
- */
-#undef DEBUG_AUTO_DISCHARGE_DISCONNECT
-
-/*
- * ForcedDischarge debug to help coordinate with AutoDischarge.
- * Defining DEBUG_FORCED_DISCHARGE will output a line for each enable
- * and disable to help better understand any Discharge issues.
- */
-#undef DEBUG_FORCED_DISCHARGE
-
-/*
- * Seeing the CC Status and ROLE Control registers as well as the
- * CC that is being determined from this information can be
- * helpful.  Defining DEBUG_GET_CC will output a line that gives
- * this useful information
- */
-#undef DEBUG_GET_CC
-
-struct get_cc_values {
-	int cc1;
-	int cc2;
-	int cc_sts;
-	int role;
-};
-STATIC_IF(DEBUG_GET_CC)
-	struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/*
- * Seeing RoleCtrl updates can help determine why GetCC is not
- * working as it should be.
- */
-#undef DEBUG_ROLE_CTRL_UPDATES
-
-/****************************************************************************/
-
-/*
- * Last reported VBus Level
- *
- * BIT(VBUS_SAFE0V) will indicate if in SAFE0V
- * BIT(VBUS_PRESENT) will indicate if in PRESENT in the TCPCI POWER_STATUS
- *
- * Note that VBUS_REMOVED cannot be distinguished from !VBUS_PRESENT with
- * this interface, but the trigger thresholds for Vbus Present should allow the
- * same bit to be used safely for both.
- *
- * TODO(b/149530538): Some TCPCs may be able to implement
- * VBUS_SINK_DISCONNECT_THRESHOLD to support vSinkDisconnectPD
- */
-static int tcpc_vbus[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Cached RP role values */
-static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Cache our Device Capabilities at init for later reference */
-static int dev_cap_1[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
-		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFF;
-		last_write_op[port].mask = 0;
-	}
-
-	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
-		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFFFF;
-		last_write_op[port].mask = 0;
-	}
-
-	rv = i2c_write16(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       i2c_addr, reg, val);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
-{
-	pd_wait_exit_low_power(port);
-
-	return tcpc_addr_read16_no_lpm_exit(port, i2c_addr, reg, val);
-}
-
-int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val)
-{
-	int rv;
-
-	rv = i2c_read16(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_read_block(int port, int reg, uint8_t *in, int size)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	rv = i2c_read_block(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, in, size);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_write_block(int port, int reg, const uint8_t *out, int size)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	rv = i2c_write_block(tcpc_config[port].i2c_info.port,
-			     tcpc_config[port].i2c_info.addr_flags,
-			     reg, out, size);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-			uint8_t *in, int in_size)
-{
-	int rv;
-	/* Dispatching to tcpc_xfer_unlocked reduces code size growth. */
-	tcpc_lock(port, 1);
-	rv = tcpc_xfer_unlocked(port, out, out_size, in, in_size,
-				I2C_XFER_SINGLE);
-	tcpc_lock(port, 0);
-	return rv;
-}
-
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
-{
-	int rv;
-
-	pd_wait_exit_low_power(port);
-
-	rv = i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       out, out_size, in, in_size, flags);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_update8(int port, int reg,
-		 uint8_t mask,
-		 enum mask_update_action action)
-{
-	int rv;
-	const int i2c_addr = tcpc_config[port].i2c_info.addr_flags;
-
-	pd_wait_exit_low_power(port);
-
-	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
-		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
-		last_write_op[port].mask = (mask & 0xFF) | (action << 16);
-	}
-
-	rv = i2c_update8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, mask, action);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-int tcpc_update16(int port, int reg,
-		  uint16_t mask,
-		  enum mask_update_action action)
-{
-	int rv;
-	const int i2c_addr = tcpc_config[port].i2c_info.addr_flags;
-
-	pd_wait_exit_low_power(port);
-
-	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
-		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
-		last_write_op[port].mask = (mask & 0xFFFF) | (action << 16);
-	}
-
-	rv = i2c_update16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, mask, action);
-
-	pd_device_accessed(port);
-	return rv;
-}
-
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-/*
- * TCPCI maintains and uses cached values for the RP and
- * last used PULL values.  Since TCPC drivers are allowed
- * to use some of the TCPCI functionality, these global
- * cached values need to be maintained in case part of the
- * used TCPCI functionality relies on these values
- */
-void tcpci_set_cached_rp(int port, int rp)
-{
-	cached_rp[port] = rp;
-}
-
-int tcpci_get_cached_rp(int port)
-{
-	return cached_rp[port];
-}
-
-static int init_alert_mask(int port)
-{
-	int rv;
-	uint16_t mask;
-
-	/*
-	 * Create mask of alert events that will cause the TCPC to
-	 * signal the TCPM via the Alert# gpio line.
-	 */
-	if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) {
-		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-			TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
-			TCPC_REG_ALERT_FAULT
-			| TCPC_REG_ALERT_POWER_STATUS
-			;
-	} else {
-		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-			TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
-			TCPC_REG_ALERT_FAULT
-			;
-	}
-
-	/* TCPCI Rev2 includes SAFE0V alerts */
-	if (TCPC_FLAGS_VSAFE0V(tcpc_config[port].flags))
-		mask |= TCPC_REG_ALERT_EXT_STATUS;
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
-		mask |= TCPC_REG_ALERT_ALERT_EXT;
-
-	/* Set the alert mask in TCPC */
-	rv = tcpc_write16(port, TCPC_REG_ALERT_MASK, mask);
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
-		if (rv)
-			return rv;
-
-		/* Sink FRS allowed */
-		mask = TCPC_REG_ALERT_EXT_SNK_FRS;
-		rv = tcpc_write(port, TCPC_REG_ALERT_EXTENDED_MASK, mask);
-	}
-	return rv;
-}
-
-static int clear_alert_mask(int port)
-{
-	return tcpc_write16(port, TCPC_REG_ALERT_MASK, 0);
-}
-
-static int init_power_status_mask(int port)
-{
-	uint8_t mask;
-	int rv;
-
-	if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)
-		mask = TCPC_REG_POWER_STATUS_VBUS_PRES;
-	else
-		mask = 0;
-
-	rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK , mask);
-
-	return rv;
-}
-
-static int clear_power_status_mask(int port)
-{
-	return tcpc_write(port, TCPC_REG_POWER_STATUS_MASK, 0);
-}
-
-static int tcpci_tcpm_get_power_status(int port, int *status)
-{
-	return tcpc_read(port, TCPC_REG_POWER_STATUS, status);
-}
-
-int tcpci_tcpm_select_rp_value(int port, int rp)
-{
-	/* Keep track of current RP value */
-	tcpci_set_cached_rp(port, rp);
-
-	return EC_SUCCESS;
-}
-
-void tcpci_tcpc_discharge_vbus(int port, int enable)
-{
-	if (IS_ENABLED(DEBUG_FORCED_DISCHARGE))
-		CPRINTS("C%d: ForceDischarge %sABLED",
-			port, enable ? "EN" : "DIS");
-
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
-		     TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
-		     (enable) ? MASK_SET : MASK_CLR);
-}
-
-/*
- * Auto Discharge Disconnect is supposed to be enabled when we
- * are connected and disabled after we are disconnected and
- * VBus is at SafeV0
- */
-void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable)
-{
-	if (IS_ENABLED(DEBUG_AUTO_DISCHARGE_DISCONNECT))
-		CPRINTS("C%d: AutoDischargeDisconnect %sABLED",
-			port, enable ? "EN" : "DIS");
-
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
-		     TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT,
-		     (enable) ? MASK_SET : MASK_CLR);
-}
-
-int tcpci_tcpc_debug_accessory(int port, bool enable)
-{
-	return tcpc_update8(port, TCPC_REG_CONFIG_STD_OUTPUT,
-			    TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N,
-			    enable ? MASK_CLR : MASK_SET);
-}
-
-int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	int role;
-	int status;
-	int cc1_present_rd, cc2_present_rd;
-	int rv;
-
-	/* errors will return CC as open */
-	*cc1 = TYPEC_CC_VOLT_OPEN;
-	*cc2 = TYPEC_CC_VOLT_OPEN;
-
-	/* Get the ROLE CONTROL and CC STATUS values */
-	rv = tcpc_read(port, TCPC_REG_ROLE_CTRL, &role);
-	if (rv)
-		return rv;
-
-	rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status);
-	if (rv)
-		return rv;
-
-	/* Get the current CC values from the CC STATUS */
-	*cc1 = TCPC_REG_CC_STATUS_CC1(status);
-	*cc2 = TCPC_REG_CC_STATUS_CC2(status);
-
-	/* Determine if we are presenting Rd */
-	cc1_present_rd = 0;
-	cc2_present_rd = 0;
-	if (role & TCPC_REG_ROLE_CTRL_DRP_MASK) {
-		/*
-		 * We are doing DRP.  We will use the CC STATUS
-		 * ConnectResult to determine if we are presenting
-		 * Rd or Rp.
-		 */
-		int term;
-
-		term = TCPC_REG_CC_STATUS_TERM(status);
-
-		if (*cc1 != TYPEC_CC_VOLT_OPEN)
-			cc1_present_rd = term;
-		if (*cc2 != TYPEC_CC_VOLT_OPEN)
-			cc2_present_rd = term;
-	} else {
-		/*
-		 * We are not doing DRP.  We will use the ROLE CONTROL
-		 * CC values to determine if we are presenting Rd or Rp.
-		 */
-		int role_cc1, role_cc2;
-
-		role_cc1 = TCPC_REG_ROLE_CTRL_CC1(role);
-		role_cc2 = TCPC_REG_ROLE_CTRL_CC2(role);
-
-		if (*cc1 != TYPEC_CC_VOLT_OPEN)
-			cc1_present_rd = !!(role_cc1 == TYPEC_CC_RD);
-		if (*cc2 != TYPEC_CC_VOLT_OPEN)
-			cc2_present_rd = !!(role_cc2 == TYPEC_CC_RD);
-	}
-	*cc1 |= cc1_present_rd << 2;
-	*cc2 |= cc2_present_rd << 2;
-
-	if (IS_ENABLED(DEBUG_GET_CC) &&
-	    (last_get_cc[port].cc1 != *cc1 ||
-	     last_get_cc[port].cc2 != *cc2 ||
-	     last_get_cc[port].cc_sts != status ||
-	     last_get_cc[port].role != role)) {
-
-		CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X",
-			port, *cc1, *cc2, status, role);
-
-		last_get_cc[port].cc1 = *cc1;
-		last_get_cc[port].cc2 = *cc2;
-		last_get_cc[port].cc_sts = status;
-		last_get_cc[port].role = role;
-	}
-	return rv;
-}
-
-int tcpci_tcpm_set_cc(int port, int pull)
-{
-	int role = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP,
-					  tcpci_get_cached_rp(port),
-					  pull, pull);
-
-	if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES))
-		CPRINTS("C%d: SET_CC pull=%d role=0x%X", port, pull, role);
-
-	return tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull pull)
-{
-	int role = TCPC_REG_ROLE_CTRL_SET(drp, rp, pull, pull);
-
-	if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES))
-		CPRINTS("C%d: SET_ROLE_CTRL drp=%d rp=%d pull=%d role=0x%X",
-			port, drp, rp, pull, role);
-
-	return tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
-}
-
-int tcpci_tcpc_drp_toggle(int port)
-{
-	int rv;
-	enum tcpc_cc_pull pull;
-
-	/*
-	 * Set auto drp toggle
-	 *
-	 *     Set RC.DRP=1b (DRP)
-	 *     Set RC.RpValue=00b (smallest Rp to save power)
-	 *     Set RC.CC1=(Rp) or (Rd)
-	 *     Set RC.CC2=(Rp) or (Rd)
-	 *
-	 * TCPCI r1 wants both lines to be set to Rd
-	 * TCPCI r2 wants both lines to be set to Rp
-	 *
-	 * Set the Rp Value to be the minimal to save power
-	 */
-	pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0)
-			? TYPEC_CC_RP : TYPEC_CC_RD;
-
-	rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, pull);
-	if (rv)
-		return rv;
-
-	/* Set up to catch LOOK4CONNECTION alerts */
-	rv = tcpc_update8(port,
-			  TCPC_REG_TCPC_CTRL,
-			  TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT,
-			  MASK_SET);
-	if (rv)
-		return rv;
-
-	/* Set Look4Connection command */
-	rv = tcpc_write(port, TCPC_REG_COMMAND,
-			TCPC_REG_COMMAND_LOOK4CONNECTION);
-
-	return rv;
-}
-#endif
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-int tcpci_enter_low_power_mode(int port)
-{
-	return tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
-}
-#endif
-
-int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
-}
-
-#ifdef CONFIG_USB_PD_PPC
-bool tcpci_tcpm_get_snk_ctrl(int port)
-{
-	int rv;
-	int pwr_sts;
-
-	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
-
-	return rv == EC_SUCCESS &&
-		pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS;
-}
-
-int tcpci_tcpm_set_snk_ctrl(int port, int enable)
-{
-	int cmd = enable ? TCPC_REG_COMMAND_SNK_CTRL_HIGH :
-		TCPC_REG_COMMAND_SNK_CTRL_LOW;
-
-	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
-}
-
-bool tcpci_tcpm_get_src_ctrl(int port)
-{
-	int rv;
-	int pwr_sts;
-
-	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
-
-	return rv == EC_SUCCESS &&
-		pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
-}
-
-int tcpci_tcpm_set_src_ctrl(int port, int enable)
-{
-	int cmd = enable ? TCPC_REG_COMMAND_SRC_CTRL_HIGH :
-		TCPC_REG_COMMAND_SRC_CTRL_LOW;
-
-	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
-}
-#endif
-
-__maybe_unused int tcpci_tcpm_sop_prime_enable(int port, bool enable)
-{
-	/* save SOP'/SOP'' enable state */
-	sop_prime_en[port] = enable;
-
-	if (rx_en[port]) {
-		int detect_sop_en = TCPC_REG_RX_DETECT_SOP_HRST_MASK;
-
-		if (enable) {
-			detect_sop_en =
-				TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK;
-		}
-
-		return tcpc_write(port, TCPC_REG_RX_DETECT, detect_sop_en);
-	}
-
-	return EC_SUCCESS;
-}
-
-int tcpci_tcpm_set_vconn(int port, int enable)
-{
-	int reg, rv;
-
-	rv = tcpc_read(port, TCPC_REG_POWER_CTRL, &reg);
-	if (rv)
-		return rv;
-
-	reg &= ~TCPC_REG_POWER_CTRL_VCONN(1);
-	reg |= TCPC_REG_POWER_CTRL_VCONN(enable);
-
-	/*
-	 * Add delay of writing TCPC_REG_POWER_CTRL makes
-	 * CC status being judged correctly when disable VCONN.
-	 * This may be a PS8XXX firmware issue, Parade is still trying.
-	 * https://partnerissuetracker.corp.google.com/issues/185202064
-	 */
-	if (!enable)
-		msleep(PS8XXX_VCONN_TURN_OFF_DELAY_US);
-
-	return tcpc_write(port, TCPC_REG_POWER_CTRL, reg);
-}
-
-int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return tcpc_write(port, TCPC_REG_MSG_HDR_INFO,
-			  TCPC_REG_MSG_HDR_INFO_SET(data_role, power_role));
-}
-
-static int tcpm_alert_status(int port, int *alert)
-{
-	/* Read TCPC Alert register */
-	return tcpc_read16(port, TCPC_REG_ALERT, alert);
-}
-
-static int tcpm_alert_ext_status(int port, int *alert_ext)
-{
-	/* Read TCPC Extended Alert register */
-	return tcpc_read(port, TCPC_REG_ALERT_EXT, alert_ext);
-}
-
-static int tcpm_ext_status(int port, int *ext_status)
-{
-	/* Read TCPC Extended Status register */
-	return tcpc_read(port, TCPC_REG_EXT_STATUS, ext_status);
-}
-
-int tcpci_tcpm_set_rx_enable(int port, int enable)
-{
-	int detect_sop_en = 0;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		/* save rx_on */
-		rx_en[port] = enable;
-	}
-
-
-	if (enable) {
-		detect_sop_en = TCPC_REG_RX_DETECT_SOP_HRST_MASK;
-
-		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) &&
-			sop_prime_en[port]) {
-			/*
-			 * Only the VCONN Source is allowed to communicate
-			 * with the Cable Plugs.
-			 */
-			detect_sop_en =
-				TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK;
-		}
-	}
-
-	/* If enable, then set RX detect for SOP and HRST */
-	return tcpc_write(port, TCPC_REG_RX_DETECT, detect_sop_en);
-}
-
-#ifdef CONFIG_USB_PD_FRS_TCPC
-int tcpci_tcpc_fast_role_swap_enable(int port, int enable)
-{
-	return tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
-		     TCPC_REG_POWER_CTRL_FRS_ENABLE,
-		     (enable) ? MASK_SET : MASK_CLR);
-}
-#endif
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	if (level == VBUS_SAFE0V)
-		return !!(tcpc_vbus[port] & BIT(VBUS_SAFE0V));
-	else if (level == VBUS_PRESENT)
-		return !!(tcpc_vbus[port] & BIT(VBUS_PRESENT));
-	else
-		return !(tcpc_vbus[port] & BIT(VBUS_PRESENT));
-}
-#endif
-
-struct cached_tcpm_message {
-	uint32_t header;
-	uint32_t payload[7];
-};
-
-static int tcpci_rev2_0_tcpm_get_message_raw(int port, uint32_t *payload,
-					     int *head)
-{
-	int rv = 0, cnt, reg = TCPC_REG_RX_BUFFER;
-	int frm;
-	uint8_t tmp[2];
-	/*
-	 * Register 0x30 is Readable Byte Count, Buffer frame type, and RX buf
-	 * byte X.
-	 */
-	tcpc_lock(port, 1);
-	rv = tcpc_xfer_unlocked(port, (uint8_t *)&reg, 1, tmp, 2,
-				I2C_XFER_START);
-	if (rv) {
-		rv = EC_ERROR_UNKNOWN;
-		goto clear;
-	}
-	cnt = tmp[0];
-	frm = tmp[1];
-
-	/*
-	 * READABLE_BYTE_COUNT includes 3 bytes for frame type and header, and
-	 * may be 0 if the TCPC saw a disconnect before the message read
-	 */
-	cnt -= 3;
-	if ((cnt < 0) ||
-	    (cnt > member_size(struct cached_tcpm_message, payload))) {
-		/* Continue to send the stop bit with the header read */
-		rv = EC_ERROR_UNKNOWN;
-		cnt = 0;
-	}
-
-	/* The next two bytes are the header */
-	rv |= tcpc_xfer_unlocked(port, NULL, 0, (uint8_t *)head, 2,
-				cnt ? 0 : I2C_XFER_STOP);
-
-	/* Encode message address in bits 31 to 28 */
-	*head &= 0x0000ffff;
-	*head |= PD_HEADER_SOP(frm);
-
-	/* Execute read and I2C_XFER_STOP, even if header read failed */
-	if (cnt > 0) {
-		tcpc_xfer_unlocked(port, NULL, 0, (uint8_t *)payload, cnt,
-				   I2C_XFER_STOP);
-	}
-
-clear:
-	tcpc_lock(port, 0);
-	/* Read complete, clear RX status alert bit */
-	tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_RX_STATUS);
-
-	if (rv)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static int tcpci_rev1_0_tcpm_get_message_raw(int port, uint32_t *payload,
-					     int *head)
-{
-	int rv, cnt, reg = TCPC_REG_RX_DATA;
-	int frm;
-
-	rv = tcpc_read(port, TCPC_REG_RX_BYTE_CNT, &cnt);
-
-	/* RX_BYTE_CNT includes 3 bytes for frame type and header */
-	if (rv != EC_SUCCESS || cnt < 3) {
-		rv = EC_ERROR_UNKNOWN;
-		goto clear;
-	}
-	cnt -= 3;
-	if (cnt > member_size(struct cached_tcpm_message, payload)) {
-		rv = EC_ERROR_UNKNOWN;
-		goto clear;
-	}
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		rv = tcpc_read(port, TCPC_REG_RX_BUF_FRAME_TYPE, &frm);
-		if (rv != EC_SUCCESS) {
-			rv = EC_ERROR_UNKNOWN;
-			goto clear;
-		}
-	}
-
-	rv = tcpc_read16(port, TCPC_REG_RX_HDR, (int *)head);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
-		/* Encode message address in bits 31 to 28 */
-		*head &= 0x0000ffff;
-		*head |= PD_HEADER_SOP(frm);
-	}
-
-	if (rv == EC_SUCCESS && cnt > 0) {
-		tcpc_read_block(port, reg, (uint8_t *)payload, cnt);
-	}
-
-clear:
-	/* Read complete, clear RX status alert bit */
-	tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_RX_STATUS);
-
-	return rv;
-}
-
-int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
-{
-	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0)
-		return tcpci_rev2_0_tcpm_get_message_raw(port, payload, head);
-
-	return tcpci_rev1_0_tcpm_get_message_raw(port, payload, head);
-}
-
-/* Cache depth needs to be power of 2 */
-/* TODO: Keep track of the high water mark */
-#define CACHE_DEPTH BIT(3)
-#define CACHE_DEPTH_MASK (CACHE_DEPTH - 1)
-
-struct queue {
-	/*
-	 * Head points to the index of the first empty slot to put a new RX
-	 * message. Must be masked before used in lookup.
-	 */
-	uint32_t head;
-	/*
-	 * Tail points to the index of the first message for the PD task to
-	 * consume. Must be masked before used in lookup.
-	 */
-	uint32_t tail;
-	struct cached_tcpm_message buffer[CACHE_DEPTH];
-};
-static struct queue cached_messages[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Note this method can be called from an interrupt context. */
-int tcpm_enqueue_message(const int port)
-{
-	int rv;
-	struct queue *const q = &cached_messages[port];
-	struct cached_tcpm_message *const head =
-		&q->buffer[q->head & CACHE_DEPTH_MASK];
-
-	if (q->head - q->tail == CACHE_DEPTH) {
-		CPRINTS("C%d RX EC Buffer full!", port);
-		return EC_ERROR_OVERFLOW;
-	}
-
-	/* Blank any old message, just in case. */
-	memset(head, 0, sizeof(*head));
-	/* Call the raw driver without caching */
-	rv = tcpc_config[port].drv->get_message_raw(port, head->payload,
-						    &head->header);
-	if (rv) {
-		CPRINTS("C%d: Could not retrieve RX message (%d)", port, rv);
-		return rv;
-	}
-
-	/* Increment atomically to ensure get_message_raw happens-before */
-	atomic_add(&q->head, 1);
-
-	/* Wake PD task up so it can process incoming RX messages */
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-
-	return EC_SUCCESS;
-}
-
-int tcpm_has_pending_message(const int port)
-{
-	const struct queue *const q = &cached_messages[port];
-
-	return q->head != q->tail;
-}
-
-int tcpm_dequeue_message(const int port, uint32_t *const payload,
-			 int *const header)
-{
-	struct queue *const q = &cached_messages[port];
-	struct cached_tcpm_message *const tail =
-		&q->buffer[q->tail & CACHE_DEPTH_MASK];
-
-	if (!tcpm_has_pending_message(port)) {
-		CPRINTS("C%d No message in RX buffer!", port);
-		return EC_ERROR_BUSY;
-	}
-
-	/* Copy cache data in to parameters */
-	*header = tail->header;
-	memcpy(payload, tail->payload, sizeof(tail->payload));
-
-	/* Increment atomically to ensure memcpy happens-before */
-	atomic_add(&q->tail, 1);
-
-	return EC_SUCCESS;
-}
-
-void tcpm_clear_pending_messages(int port)
-{
-	struct queue *const q = &cached_messages[port];
-
-	q->tail = q->head;
-}
-
-int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data)
-{
-	int reg = TCPC_REG_TX_DATA;
-	int rv, cnt = 4*PD_HEADER_CNT(header);
-
-	/* If not SOP* transmission, just write to the transmit register */
-	if (type >= NUM_SOP_STAR_TYPES) {
-		/*
-		 * Per TCPCI spec, do not specify retry (although the TCPC
-		 * should ignore retry field for these 3 types).
-		 */
-		return tcpc_write(port, TCPC_REG_TRANSMIT,
-			TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type));
-	}
-
-	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
-		/*
-		 * In TCPCI Rev 2.0, TX_BYTE_CNT and TX_BUF_BYTE_X are the same
-		 * register.
-		 */
-		reg = TCPC_REG_TX_BUFFER;
-		/* TX_BYTE_CNT includes extra bytes for message header */
-		cnt += sizeof(header);
-		tcpc_lock(port, 1);
-		rv = tcpc_xfer_unlocked(port, (uint8_t *)&reg, 1, NULL, 0,
-					I2C_XFER_START);
-		rv |= tcpc_xfer_unlocked(port, (uint8_t *)&cnt, 1, NULL, 0, 0);
-		if (cnt > sizeof(header)) {
-			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					 sizeof(header), NULL, 0, 0);
-			rv |= tcpc_xfer_unlocked(port, (uint8_t *)data,
-					 cnt-sizeof(header), NULL, 0,
-					 I2C_XFER_STOP);
-		} else {
-			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					sizeof(header), NULL, 0, I2C_XFER_STOP);
-		}
-		tcpc_lock(port, 0);
-
-		/* If tcpc write fails, return error */
-		if (rv)
-			return rv;
-	} else {
-		/* TX_BYTE_CNT includes extra bytes for message header */
-		rv = tcpc_write(port, TCPC_REG_TX_BYTE_CNT,
-				cnt + sizeof(header));
-
-		rv |= tcpc_write16(port, TCPC_REG_TX_HDR, header);
-
-		/* If tcpc write fails, return error */
-		if (rv)
-			return rv;
-
-		if (cnt > 0) {
-			rv = tcpc_write_block(port, reg, (const uint8_t *)data,
-					      cnt);
-
-			/* If tcpc write fails, return error */
-			if (rv)
-				return rv;
-		}
-	}
-
-	/*
-	 * We always retry in TCPC hardware since the TCPM is too slow to
-	 * respond within tRetry (~195 usec).
-	 *
-	 * The retry count used is dependent on the maximum PD revision
-	 * supported at build time.
-	 */
-	return tcpc_write(port, TCPC_REG_TRANSMIT,
-			  TCPC_REG_TRANSMIT_SET_WITH_RETRY(
-				  pd_get_retry_count(port, type), type));
-}
-
-/*
- * Returns true if TCPC has reset based on reading mask registers.
- */
-static int register_mask_reset(int port)
-{
-	int mask;
-
-	mask = 0;
-	tcpc_read16(port, TCPC_REG_ALERT_MASK, &mask);
-	if (mask == TCPC_REG_ALERT_MASK_ALL)
-		return 1;
-
-	mask = 0;
-	tcpc_read(port, TCPC_REG_POWER_STATUS_MASK, &mask);
-	if (mask == TCPC_REG_POWER_STATUS_MASK_ALL)
-		return 1;
-
-	return 0;
-}
-
-static int tcpci_get_fault(int port, int *fault)
-{
-	return tcpc_read(port, TCPC_REG_FAULT_STATUS, fault);
-}
-
-static int tcpci_handle_fault(int port, int fault)
-{
-	int rv = EC_SUCCESS;
-
-	CPRINTS("C%d FAULT 0x%02X detected", port, fault);
-
-	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP) &&
-	    fault & TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR) {
-		if (last_write_op[port].mask == 0)
-			CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X",
-				port,
-				last_write_op[port].addr,
-				last_write_op[port].reg,
-				last_write_op[port].val);
-		else
-			CPRINTS("C%d I2C UP 0x%02X 0x%02X op=%d mask=0x%X",
-				port,
-				last_write_op[port].addr,
-				last_write_op[port].reg,
-				last_write_op[port].mask >> 16,
-				last_write_op[port].mask & 0xFFFF);
-	}
-
-	/* Report overcurrent to the OCP module if enabled */
-	if ((dev_cap_1[port] & TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING) &&
-			IS_ENABLED(CONFIG_USBC_OCP) &&
-			(fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT))
-		pd_handle_overcurrent(port);
-
-	if (tcpc_config[port].drv->handle_fault)
-		rv = tcpc_config[port].drv->handle_fault(port, fault);
-
-	return rv;
-}
-
-enum ec_error_list tcpci_set_bist_test_mode(const int port,
-		const bool enable)
-{
-	int rv;
-
-	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
-			TCPC_REG_TCPC_CTRL_BIST_TEST_MODE,
-			enable ? MASK_SET : MASK_CLR);
-	rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK,
-			TCPC_REG_ALERT_RX_STATUS, enable ? MASK_CLR : MASK_SET);
-	return rv;
-}
-
-static int tcpci_clear_fault(int port, int fault)
-{
-	int rv;
-
-	rv = tcpc_write(port, TCPC_REG_FAULT_STATUS, fault);
-	if (rv)
-		return rv;
-
-	return tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_FAULT);
-}
-
-static void tcpci_check_vbus_changed(int port, int alert, uint32_t *pd_event)
-{
-	/*
-	 * Check for VBus change
-	 */
-	/* TCPCI Rev2 includes Safe0V detection */
-	if (TCPC_FLAGS_VSAFE0V(tcpc_config[port].flags) &&
-	    (alert & TCPC_REG_ALERT_EXT_STATUS)) {
-		int ext_status = 0;
-
-		/* Determine if Safe0V was detected */
-		tcpm_ext_status(port, &ext_status);
-		if (ext_status & TCPC_REG_EXT_STATUS_SAFE0V)
-			/* Safe0V=1 and Present=0 */
-			tcpc_vbus[port] = BIT(VBUS_SAFE0V);
-	}
-
-	if (alert & TCPC_REG_ALERT_POWER_STATUS) {
-		int pwr_status = 0;
-
-		/* Determine reason for power status change */
-		tcpci_tcpm_get_power_status(port, &pwr_status);
-		if (pwr_status & TCPC_REG_POWER_STATUS_VBUS_PRES)
-			/* Safe0V=0 and Present=1 */
-			tcpc_vbus[port] = BIT(VBUS_PRESENT);
-		else if (TCPC_FLAGS_VSAFE0V(tcpc_config[port].flags))
-			/* TCPCI Rev2 detects Safe0V, so Present=0 */
-			tcpc_vbus[port] &= ~BIT(VBUS_PRESENT);
-		else {
-			/*
-			 * TCPCI Rev1 can not detect Safe0V, so treat this
-			 * like a Safe0V detection.
-			 *
-			 * Safe0V=1 and Present=0
-			 */
-			tcpc_vbus[port] = BIT(VBUS_SAFE0V);
-		}
-
-		if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) &&
-		    IS_ENABLED(CONFIG_USB_CHARGER)) {
-			/* Update charge manager with new VBUS state */
-			usb_charger_vbus_change(port,
-				!!(tcpc_vbus[port] & BIT(VBUS_PRESENT)));
-
-			if (pd_event)
-				*pd_event |= TASK_EVENT_WAKE;
-		}
-	}
-}
-
-/*
- * Don't let the TCPC try to pull from the RX buffer forever. We typical only
- * have 1 or 2 messages waiting.
- */
-#define MAX_ALLOW_FAILED_RX_READS 10
-
-void tcpci_tcpc_alert(int port)
-{
-	int alert = 0;
-	int alert_ext = 0;
-	int failed_attempts;
-	uint32_t pd_event = 0;
-	int retval = 0;
-
-	/* Read the Alert register from the TCPC */
-	if (tcpm_alert_status(port, &alert)) {
-		CPRINTS("C%d: Failed to read alert register", port);
-		return;
-	}
-
-	/* Get Extended Alert register if needed */
-	if (alert & TCPC_REG_ALERT_ALERT_EXT)
-		tcpm_alert_ext_status(port, &alert_ext);
-
-	/* Clear any pending faults */
-	if (alert & TCPC_REG_ALERT_FAULT) {
-		int fault;
-
-		if (tcpci_get_fault(port, &fault) == EC_SUCCESS &&
-		    fault != 0 &&
-		    tcpci_handle_fault(port, fault) == EC_SUCCESS &&
-		    tcpci_clear_fault(port, fault) == EC_SUCCESS)
-			CPRINTS("C%d FAULT 0x%02X handled", port, fault);
-	}
-
-	/*
-	 * Check for TX complete first b/c PD state machine waits on TX
-	 * completion events. This will send an event to the PD tasks
-	 * immediately
-	 */
-	if (alert & TCPC_REG_ALERT_TX_COMPLETE)
-		pd_transmit_complete(port, alert & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
-
-	/* Pull all RX messages from TCPC into EC memory */
-	failed_attempts = 0;
-	while (alert & TCPC_REG_ALERT_RX_STATUS) {
-		retval = tcpm_enqueue_message(port);
-		if (retval)
-			++failed_attempts;
-		if (tcpm_alert_status(port, &alert))
-			++failed_attempts;
-
-
-		/*
-		 * EC RX FIFO is full. Deassert ALERT# line to exit interrupt
-		 * handler by discarding pending message from TCPC RX FIFO.
-		 */
-		if (retval == EC_ERROR_OVERFLOW) {
-			CPRINTS("C%d: PD RX OVF!", port);
-			tcpc_write16(port, TCPC_REG_ALERT,
-				TCPC_REG_ALERT_RX_STATUS |
-				TCPC_REG_ALERT_RX_BUF_OVF);
-		}
-
-		/* Ensure we don't loop endlessly */
-		if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) {
-			CPRINTS("C%d Cannot consume RX buffer after %d failed attempts!",
-				port, failed_attempts);
-			/*
-			 * The port is in a bad state, we don't want to consume
-			 * all EC resources so suspend the port for a little
-			 * while.
-			 */
-			pd_set_suspend(port, 1);
-			pd_deferred_resume(port);
-			return;
-		}
-	}
-
-	/*
-	 * Clear all pending alert bits. Ext first because ALERT.AlertExtended
-	 * is set if any bit of ALERT_EXTENDED is set.
-	 */
-	if (alert_ext)
-		tcpc_write(port, TCPC_REG_ALERT_EXT, alert_ext);
-	if (alert)
-		tcpc_write16(port, TCPC_REG_ALERT, alert);
-
-	if (alert & TCPC_REG_ALERT_CC_STATUS) {
-		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)) {
-			enum tcpc_cc_voltage_status cc1;
-			enum tcpc_cc_voltage_status cc2;
-
-			/*
-			 * Some TCPCs generate CC Alerts when
-			 * drp auto toggle is active and nothing
-			 * is connected to the port. So, get the
-			 * CC line status and only generate a
-			 * PD_EVENT_CC if something is connected.
-			 */
-			tcpci_tcpm_get_cc(port, &cc1, &cc2);
-			if (cc1 != TYPEC_CC_VOLT_OPEN ||
-			    cc2 != TYPEC_CC_VOLT_OPEN)
-				/* CC status cchanged, wake task */
-				pd_event |= PD_EVENT_CC;
-		} else {
-			/* CC status changed, wake task */
-			pd_event |= PD_EVENT_CC;
-		}
-	}
-
-	tcpci_check_vbus_changed(port, alert, &pd_event);
-
-	/* Check for Hard Reset received */
-	if (alert & TCPC_REG_ALERT_RX_HARD_RST) {
-		/* hard reset received */
-		CPRINTS("C%d Hard Reset received", port);
-		pd_event |= PD_EVENT_RX_HARD_RESET;
-	}
-
-	/* USB TCPCI Spec R2 V1.1 Section 4.7.3 Step 2
-	 *
-	 * The TCPC asserts both ALERT.TransmitSOP*MessageSuccessful and
-	 * ALERT.TransmitSOP*MessageFailed regardless of the outcome of the
-	 * transmission and asserts the Alert# pin.
-	 */
-	if (alert & TCPC_REG_ALERT_TX_SUCCESS &&
-	    alert & TCPC_REG_ALERT_TX_FAILED)
-		CPRINTS("C%d Hard Reset sent", port);
-
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)
-	    && (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS))
-		pd_got_frs_signal(port);
-
-	/*
-	 * Check registers to see if we can tell that the TCPC has reset. If
-	 * so, perform a tcpc_init.
-	 */
-	if (register_mask_reset(port))
-		pd_event |= PD_EVENT_TCPC_RESET;
-
-	/*
-	 * Wait until all possible TCPC accesses in this function are complete
-	 * prior to setting events and/or waking the pd task. When the PD
-	 * task is woken and runs (which will happen during I2C transactions in
-	 * this function), the pd task may put the TCPC into low power mode and
-	 * the next I2C transaction to the TCPC will cause it to wake again.
-	 */
-	if (pd_event)
-		task_set_event(PD_PORT_TO_TASK_ID(port), pd_event);
-}
-
-/*
- * This call will wake up the TCPC if it is in low power mode upon accessing the
- * i2c bus (but the pd state machine should put it back into low power mode).
- *
- * Once it's called, the chip info will be stored in cache, which can be
- * accessed by tcpm_get_chip_info without worrying about chip states.
- */
-int tcpci_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
-{
-	static struct ec_response_pd_chip_info_v1
-		cached_info[CONFIG_USB_PD_PORT_MAX_COUNT];
-	struct ec_response_pd_chip_info_v1 *i;
-	int error;
-	int val;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	i = &cached_info[port];
-
-
-	/* If already cached && live data is not asked, return cached value */
-	if (i->vendor_id && !live) {
-		/*
-		 * If chip_info is NULL, chip info will be stored in cache and
-		 * can be read later by another call.
-		 */
-		if (chip_info)
-			memcpy(chip_info, i, sizeof(*i));
-
-		return EC_SUCCESS;
-	}
-
-	error = tcpc_read16(port, TCPC_REG_VENDOR_ID, &val);
-	if (error)
-		return error;
-	i->vendor_id = val;
-
-	error = tcpc_read16(port, TCPC_REG_PRODUCT_ID, &val);
-	if (error)
-		return error;
-	i->product_id = val;
-
-	error = tcpc_read16(port, TCPC_REG_BCD_DEV, &val);
-	if (error)
-		return error;
-	i->device_id = val;
-
-	/*
-	 * This varies chip to chip; more specific driver code is expected to
-	 * override this value if it can.
-	 */
-	i->fw_version_number = -1;
-
-	/* Copy the cached value to return if chip_info is not NULL */
-	if (chip_info)
-		memcpy(chip_info, i, sizeof(*i));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Dissociate from the TCPC.
- */
-
-int tcpci_tcpm_release(int port)
-{
-	int error;
-
-	error = clear_alert_mask(port);
-	if (error)
-		return error;
-	error = clear_power_status_mask(port);
-	if (error)
-		return error;
-	/* Clear pending interrupts */
-	error = tcpc_write16(port, TCPC_REG_ALERT, 0xffff);
-	if (error)
-		return error;
-
-	return EC_SUCCESS;
-}
-
-/*
- * On TCPC i2c failure, make 30 tries (at least 300ms) before giving up
- * in order to allow the TCPC time to boot / reset.
- */
-#define TCPM_INIT_TRIES 30
-
-int tcpci_tcpm_init(int port)
-{
-	int error;
-	int power_status;
-	int tries = TCPM_INIT_TRIES;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_ERROR_INVAL;
-
-	while (1) {
-		error = tcpci_tcpm_get_power_status(port, &power_status);
-		/*
-		 * If read succeeds and the uninitialized bit is clear, then
-		 * initialization is complete, clear all alert bits and write
-		 * the initial alert mask.
-		 */
-		if (!error && !(power_status & TCPC_REG_POWER_STATUS_UNINIT))
-			break;
-		if (--tries <= 0)
-			return error ? error : EC_ERROR_TIMEOUT;
-		msleep(10);
-	}
-
-	/*
-	 * For TCPCI Rev 2.0, unless the TCPM sets
-	 * TCPC_CONTROL.EnableLooking4ConnectionAlert bit, TCPC by default masks
-	 * Alert assertion when CC_STATUS.Looking4Connection changes state.
-	 */
-	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
-		error = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
-				TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT,
-				MASK_SET);
-		if (error)
-			CPRINTS("C%d: Failed to init TCPC_CTRL!", port);
-	}
-
-	/*
-	 * Handle and clear any alerts, since we might be coming out of low
-	 * power mode in response to an alert interrupt from the TCPC.
-	 */
-	tcpc_alert(port);
-	/* Initialize power_status_mask */
-	init_power_status_mask(port);
-
-	if (TCPC_FLAGS_VSAFE0V(tcpc_config[port].flags)) {
-		int ext_status = 0;
-
-		/* Read Extended Status register */
-		tcpm_ext_status(port, &ext_status);
-		/* Initial level, set appropriately */
-		if (power_status & TCPC_REG_POWER_STATUS_VBUS_PRES)
-			tcpc_vbus[port] = BIT(VBUS_PRESENT);
-		else if (ext_status & TCPC_REG_EXT_STATUS_SAFE0V)
-			tcpc_vbus[port] = BIT(VBUS_SAFE0V);
-		else
-			tcpc_vbus[port] = 0;
-	} else {
-		/* Initial level, set appropriately */
-		tcpc_vbus[port] = (power_status &
-				   TCPC_REG_POWER_STATUS_VBUS_PRES)
-					? BIT(VBUS_PRESENT)
-					: BIT(VBUS_SAFE0V);
-	}
-
-	/*
-	 * Force an update to the VBUS status in case the TCPC doesn't send a
-	 * power status changed interrupt later.
-	 */
-	tcpci_check_vbus_changed(port,
-		TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS,
-		NULL);
-
-	error = init_alert_mask(port);
-	if (error)
-		return error;
-
-	/* Read chip info here when we know the chip is awake. */
-	tcpm_get_chip_info(port, 1, NULL);
-
-	/* Cache our device capabilities for future reference */
-	tcpc_read16(port, TCPC_REG_DEV_CAP_1, &dev_cap_1[port]);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPM_MUX
-
-/*
- * When the TCPC/MUX device is only used for the MUX, we need to initialize it
- * via mux init because tcpc_init won't run for the device. This is borrowed
- * from tcpc_init.
- */
-int tcpci_tcpm_mux_init(const struct usb_mux *me)
-{
-	int error;
-	int power_status;
-	int tries = TCPM_INIT_TRIES;
-
-	/* If this MUX is also the TCPC, then skip init */
-	if (!(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		return EC_SUCCESS;
-
-	/* Wait for the device to exit low power state */
-	while (1) {
-		error = mux_read(me, TCPC_REG_POWER_STATUS, &power_status);
-		/*
-		 * If read succeeds and the uninitialized bit is clear, then
-		 * initialization is complete.
-		 */
-		if (!error && !(power_status & TCPC_REG_POWER_STATUS_UNINIT))
-			break;
-		if (--tries <= 0)
-			return error ? error : EC_ERROR_TIMEOUT;
-		msleep(10);
-	}
-
-	/* Turn off all alerts and acknowledge any pending IRQ */
-	error = mux_write16(me, TCPC_REG_ALERT_MASK, 0);
-	error |= mux_write16(me, TCPC_REG_ALERT, 0xffff);
-
-	return error ? EC_ERROR_UNKNOWN : EC_SUCCESS;
-}
-
-int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me)
-{
-	/* If this MUX is also the TCPC, then skip low power */
-	if (!(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		return EC_SUCCESS;
-
-	return mux_write(me, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
-}
-
-int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-		       bool *ack_required)
-{
-	int rv;
-	int reg = 0;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/* Parameter is port only */
-	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	reg &= ~(TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK |
-		 TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED);
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
-
-	/* Parameter is port only */
-	return mux_write(me, TCPC_REG_CONFIG_STD_OUTPUT, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-int tcpci_tcpm_mux_get(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int rv;
-	int reg = 0;
-
-	*mux_state = 0;
-
-	/* Parameter is port only */
-	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	if (reg & TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver tcpci_tcpm_usb_mux_driver = {
-	.init = &tcpci_tcpm_mux_init,
-	.set = &tcpci_tcpm_mux_set,
-	.get = &tcpci_tcpm_mux_get,
-	.enter_low_power_mode = &tcpci_tcpm_mux_enter_low_power,
-};
-
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
-#ifdef CONFIG_CMD_TCPC_DUMP
-static const struct tcpc_reg_dump_map tcpc_regs[] = {
-	{
-		.addr = TCPC_REG_VENDOR_ID,
-		.name = "VENDOR_ID",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_PRODUCT_ID,
-		.name = "PRODUCT_ID",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_BCD_DEV,
-		.name = "BCD_DEV",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_TC_REV,
-		.name = "TC_REV",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_PD_REV,
-		.name = "PD_REV",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_PD_INT_REV,
-		.name = "PD_INT_REV",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_ALERT,
-		.name = "ALERT",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_ALERT_MASK,
-		.name = "ALERT_MASK",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_POWER_STATUS_MASK,
-		.name = "POWER_STATUS_MASK",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_FAULT_STATUS_MASK,
-		.name = "FAULT_STATUS_MASK",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_EXT_STATUS_MASK,
-		.name = "EXT_STATUS_MASK",
-		.size = 1
-	},
-	{
-		.addr = TCPC_REG_ALERT_EXTENDED_MASK,
-		.name = "ALERT_EXTENDED_MASK",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_CONFIG_STD_OUTPUT,
-		.name = "CONFIG_STD_OUTPUT",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_TCPC_CTRL,
-		.name = "TCPC_CTRL",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_ROLE_CTRL,
-		.name = "ROLE_CTRL",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_FAULT_CTRL,
-		.name = "FAULT_CTRL",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_POWER_CTRL,
-		.name = "POWER_CTRL",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_CC_STATUS,
-		.name = "CC_STATUS",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_POWER_STATUS,
-		.name = "POWER_STATUS",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_FAULT_STATUS,
-		.name = "FAULT_STATUS",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_EXT_STATUS,
-		.name = "EXT_STATUS",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_ALERT_EXT,
-		.name = "ALERT_EXT",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_DEV_CAP_1,
-		.name = "DEV_CAP_1",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_DEV_CAP_2,
-		.name = "DEV_CAP_2",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_STD_INPUT_CAP,
-		.name = "STD_INPUT_CAP",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_STD_OUTPUT_CAP,
-		.name = "STD_OUTPUT_CAP",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_CONFIG_EXT_1,
-		.name = "CONFIG_EXT_1",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_MSG_HDR_INFO,
-		.name = "MSG_HDR_INFO",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_RX_DETECT,
-		.name = "RX_DETECT",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_RX_BYTE_CNT,
-		.name = "RX_BYTE_CNT",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_RX_BUF_FRAME_TYPE,
-		.name = "RX_BUF_FRAME_TYPE",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_TRANSMIT,
-		.name = "TRANSMIT",
-		.size = 1,
-	},
-	{
-		.addr = TCPC_REG_VBUS_VOLTAGE,
-		.name = "VBUS_VOLTAGE",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
-		.name = "VBUS_SINK_DISCONNECT_THRESH",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_VBUS_STOP_DISCHARGE_THRESH,
-		.name = "VBUS_STOP_DISCHARGE_THRESH",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG,
-		.name = "VBUS_VOLTAGE_ALARM_HI_CFG",
-		.size = 2,
-	},
-	{
-		.addr = TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG,
-		.name = "VBUS_VOLTAGE_ALARM_LO_CFG",
-		.size = 2,
-	},
-};
-
-/*
- * Dump standard TCPC registers.
- */
-void tcpc_dump_std_registers(int port)
-{
-	tcpc_dump_registers(port, tcpc_regs, ARRAY_SIZE(tcpc_regs));
-}
-#endif
-
-const struct tcpm_drv tcpci_tcpm_drv = {
-	.init			= &tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-	.tcpc_enable_auto_discharge_disconnect =
-		&tcpci_tcpc_enable_auto_discharge_disconnect,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_PPC
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-#ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &tcpc_dump_std_registers,
-#endif
-};
diff --git a/driver/tcpm/tusb422.c b/driver/tcpm/tusb422.c
deleted file mode 100644
index f2a4ec2fb3..0000000000
--- a/driver/tcpm/tusb422.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Type-C port manager for TI TUSB422 Port Controller */
-
-#include "common.h"
-#include "tusb422.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_pd.h"
-
-#ifndef CONFIG_USB_PD_TCPM_TCPCI
-#error "TUSB422 is using a standard TCPCI interface"
-#error "Please upgrade your board configuration"
-
-#endif
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-	!defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-#error "TUSB422 driver requires CONFIG_USB_PD_TCPC_LOW_POWER if " \
-		"CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE is enabled"
-#endif
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
-#error "TUSB422 must disable TCPC discharge to support enabling Auto " \
-		"Discharge Disconnect all the time."
-#endif
-
-enum tusb422_reg_addr {
-	TUSB422_REG_VBUS_AND_VCONN_CONTROL = 0x98,
-};
-
-enum vbus_and_vconn_control_mask {
-	INT_VCONNDIS_DISABLE = BIT(1),
-	INT_VBUSDIS_DISABLE  = BIT(2),
-};
-
-/* The TUSB422 cannot drive an FRS GPIO, but can detect FRS */
-static int tusb422_set_frs_enable(int port, int enable)
-{
-	return tcpc_update8(port, TUSB422_REG_PHY_BMC_RX_CTRL,
-			    TUSB422_REG_PHY_BMC_RX_CTRL_FRS_RX_EN,
-			    enable ? MASK_SET : MASK_CLR);
-}
-
-static int tusb422_tcpci_tcpm_init(int port)
-{
-	int rv;
-
-	/*
-	 * Do not perform TCPC soft reset while waking from Low Power Mode,
-	 * because it makes DRP incapable of looking for connection correctly
-	 * (see b/176986511) and probably breaks firmware_PDTrySrc test
-	 * (see b/179234089).
-	 *
-	 * TODO(b/179234089): Consider implementing function that performs
-	 * only necessary things when leaving Low Power Mode, so we can perform
-	 * TCPC soft reset here.
-	 */
-
-	rv = tcpci_tcpm_init(port);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)) {
-		/*
-		 * When dual role auto toggle is enabled, the TUSB422 needs
-		 * auto discharge disconnect enabled so that the CC state
-		 * is detected correctly.
-		 * Without this, the CC lines get stuck in the SRC.Open state
-		 * after updating the ROLE Control register on a device connect.
-		 */
-		tusb422_tcpm_drv.tcpc_enable_auto_discharge_disconnect(port, 1);
-
-		/*
-		 * Disable internal VBUS discharge. AutoDischargeDisconnect must
-		 * generally remain enabled to keep TUSB422 in active mode.
-		 * However, this will interfere with FRS by default by
-		 * discharging at inappropriate times. Mitigate this by
-		 * disabling internal VBUS discharge. The TUSB422 must rely on
-		 * external VBUS discharge. See TUSB422 datasheet, 7.4.2 Active
-		 * Mode.
-		 */
-		tcpc_write(port, TUSB422_REG_VBUS_AND_VCONN_CONTROL,
-				INT_VBUSDIS_DISABLE);
-	}
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
-		/* Disable FRS detection, and enable the FRS detection alert */
-		tusb422_set_frs_enable(port, 0);
-		tcpc_update16(port, TCPC_REG_ALERT_MASK,
-			      TCPC_REG_ALERT_MASK_VENDOR_DEF, MASK_SET);
-		tcpc_update8(port, TUSB422_REG_VENDOR_INTERRUPTS_MASK,
-			     TUSB422_REG_VENDOR_INTERRUPTS_MASK_FRS_RX,
-			     MASK_SET);
-	}
-	/*
-	 * VBUS detection is supposed to be enabled by default, however the
-	 * TUSB422 has this disabled following reset.
-	 */
-	/* Enable VBUS detection */
-	return tcpc_write16(port, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
-}
-
-static int tusb422_tcpm_set_cc(int port, int pull)
-{
-	/*
-	 * Enable AutoDischargeDisconnect to keep TUSB422 in active mode through
-	 * this transition. Note that the configuration keeps the TCPC from
-	 * actually discharging VBUS in this case.
-	 */
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE))
-		tusb422_tcpm_drv.tcpc_enable_auto_discharge_disconnect(port, 1);
-
-	return tcpci_tcpm_set_cc(port, pull);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-static int tusb422_tcpc_drp_toggle(int port)
-{
-	/*
-	 * The TUSB422 requires auto discharge disconnect to be enabled for
-	 * active mode (not unattached) operation. Make sure it is disabled
-	 * before enabling DRP toggling.
-	 *
-	 * USB Type-C Port Controller Interface Specification revision 2.0,
-	 * Figure 4-21 Source Disconnect and Figure 4-22 Sink Disconnect
-	 */
-	tusb422_tcpm_drv.tcpc_enable_auto_discharge_disconnect(port, 0);
-
-	return tcpci_tcpc_drp_toggle(port);
-}
-#endif
-
-static void tusb422_tcpci_tcpc_alert(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
-		int regval;
-
-		/* FRS detection is a vendor defined alert */
-		tcpc_read(port, TUSB422_REG_VENDOR_INTERRUPTS_STATUS, &regval);
-		if (regval & TUSB422_REG_VENDOR_INTERRUPTS_STATUS_FRS_RX) {
-			tusb422_set_frs_enable(port, 0);
-			tcpc_write(port, TUSB422_REG_VENDOR_INTERRUPTS_STATUS,
-				   regval);
-			pd_got_frs_signal(port);
-		}
-	}
-	tcpci_tcpc_alert(port);
-}
-
-const struct tcpm_drv tusb422_tcpm_drv = {
-	.init			= &tusb422_tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
-#endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tusb422_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
-#endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tusb422_tcpci_tcpc_alert,
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
-#endif
-	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tusb422_tcpc_drp_toggle,
-#endif
-#ifdef CONFIG_USB_PD_PPC
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-#endif
-	.get_chip_info		= &tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
-#endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
-#ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable         = &tusb422_set_frs_enable,
-#endif
-};
diff --git a/driver/tcpm/tusb422.h b/driver/tcpm/tusb422.h
deleted file mode 100644
index f39939b184..0000000000
--- a/driver/tcpm/tusb422.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TI TUSB422 Type-C port controller */
-
-#ifndef __CROS_EC_USB_PD_TCPM_TUSB422_H
-#define __CROS_EC_USB_PD_TCPM_TUSB422_H
-
-#include "driver/tcpm/tusb422_public.h"
-
-#define TUSB422_REG_VENDOR_INTERRUPTS_STATUS 0x90
-#define TUSB422_REG_VENDOR_INTERRUPTS_STATUS_FRS_RX BIT(0)
-
-#define TUSB422_REG_VENDOR_INTERRUPTS_MASK 0x92
-#define TUSB422_REG_VENDOR_INTERRUPTS_MASK_FRS_RX BIT(0)
-
-#define TUSB422_REG_PHY_BMC_RX_CTRL 0x96
-#define TUSB422_REG_PHY_BMC_RX_CTRL_FRS_RX_EN BIT(3)
-
-#endif /* defined(__CROS_EC_USB_PD_TCPM_TUSB422_H) */
diff --git a/driver/temp_sensor/adt7481.c b/driver/temp_sensor/adt7481.c
deleted file mode 100644
index cbd32e5cd5..0000000000
--- a/driver/temp_sensor/adt7481.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ADT7481 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "adt7481.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_local;
-static int temp_val_remote1;
-static int temp_val_remote2;
-static uint8_t is_sensor_shutdown;
-
-/**
- * Determine whether the sensor is powered.
- *
- * @return non-zero the adt7481 sensor is powered.
- */
-static int has_power(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return !is_sensor_shutdown;
-#endif
-}
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
-}
-
-static int raw_write8(const int offset, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			  offset, data);
-}
-
-static int get_temp(const int offset, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv < 0)
-		return rv;
-
-	*temp_ptr = (int)(int8_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int adt7481_set_temp(const int offset, int temp)
-{
-	if (temp < -127 || temp > 127)
-		return EC_ERROR_INVAL;
-
-	return raw_write8(offset, (uint8_t)temp);
-}
-#endif
-
-int adt7481_get_val(int idx, int *temp_ptr)
-{
-	if (!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	switch (idx) {
-	case ADT7481_IDX_LOCAL:
-		*temp_ptr = temp_val_local;
-		break;
-	case ADT7481_IDX_REMOTE1:
-		*temp_ptr = temp_val_remote1;
-		break;
-	case ADT7481_IDX_REMOTE2:
-		*temp_ptr = temp_val_remote2;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int adt7481_shutdown(uint8_t want_shutdown)
-{
-	int ret, value;
-
-	if (want_shutdown == is_sensor_shutdown)
-		return EC_SUCCESS;
-
-	ret = raw_read8(ADT7481_CONFIGURATION1_R, &value);
-	if (ret < 0) {
-		ccprintf("ERROR: Temp sensor I2C read8 error.\n");
-		return ret;
-	}
-
-	if (want_shutdown && !(value & ADT7481_CONFIG1_RUN_L)) {
-		/* adt7481 is running, and want it to shutdown */
-		/* CONFIG REG1 BIT6: 0=Run, 1=Shutdown */
-		/* shut it down */
-		value |= ADT7481_CONFIG1_RUN_L;
-		ret = raw_write8(ADT7481_CONFIGURATION1_R, value);
-	} else if (!want_shutdown && (value & ADT7481_CONFIG1_RUN_L)) {
-		/* adt7481 is shutdown, and want turn it on */
-		value &= ~ADT7481_CONFIG1_RUN_L;
-		ret = raw_write8(ADT7481_CONFIGURATION1_R, value);
-	}
-	/* else, the current setting is exactly what you want */
-
-	is_sensor_shutdown = want_shutdown;
-	return ret;
-}
-
-static int adt7481_set_therm_mode(void)
-{
-	int ret = 0;
-	int data = 0;
-
-	ret = raw_read8(ADT7481_CONFIGURATION1_R, &data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	data |= ADT7481_CONFIG1_MODE;
-	ret = raw_write8(ADT7481_CONFIGURATION1_W, data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-int adt7481_set_therm_limit(int channel, int limit_c, int hysteresis)
-{
-	int ret = 0;
-	int reg = 0;
-
-	if (channel >= ADT7481_CHANNEL_COUNT)
-		return EC_ERROR_INVAL;
-
-	if (hysteresis > ADT7481_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT)
-		return EC_ERROR_INVAL;
-
-	/* hysteresis must be less than high limit */
-	if (hysteresis > limit_c)
-		return EC_ERROR_INVAL;
-
-	if (adt7481_set_therm_mode() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	switch (channel) {
-	case ADT7481_CHANNEL_LOCAL:
-		reg = ADT7481_LOCAL_HIGH_LIMIT_W;
-		break;
-	case ADT7481_CHANNEL_REMOTE1:
-		reg = ADT7481_REMOTE1_HIGH_LIMIT_W;
-		break;
-	case ADT7481_CHANNEL_REMOTE2:
-		reg = ADT7481_REMOTE2_HIGH_LIMIT;
-		break;
-	}
-
-	ret = raw_write8(reg, limit_c);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	ret = raw_write8(ADT7481_THERM_HYSTERESIS, hysteresis);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static void adt7481_temp_sensor_poll(void)
-{
-	int temp_c;
-
-	if (!has_power())
-		return;
-
-	if (get_temp(ADT7481_LOCAL, &temp_c) == EC_SUCCESS)
-		temp_val_local = C_TO_K(temp_c);
-
-	if (get_temp(ADT7481_REMOTE1, &temp_c) == EC_SUCCESS)
-		temp_val_remote1 = C_TO_K(temp_c);
-
-	if (get_temp(ADT7481_REMOTE2, &temp_c) == EC_SUCCESS)
-		temp_val_remote2 = C_TO_K(temp_c);
-}
-DECLARE_HOOK(HOOK_SECOND, adt7481_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int adt7481_temp_reg,
-		const int adt7481_therm_limit_reg,
-		const int adt7481_high_limit_reg,
-		const int adt7481_low_limit_reg)
-{
-	int value;
-
-	if (!has_power()) {
-		ccprintf("  ADT7481 is shutdown\n");
-		return;
-	}
-
-	ccprintf("%s:\n", name);
-
-	if (get_temp(adt7481_temp_reg, &value) == EC_SUCCESS)
-		ccprintf("  Temp       %3dC\n", value);
-
-	if (get_temp(adt7481_therm_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Therm Trip %3dC\n", value);
-
-	if (get_temp(adt7481_high_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  High Alarm %3dC\n", value);
-
-	if (get_temp(adt7481_low_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Low Alarm  %3dC\n", value);
-}
-
-static int print_status(void)
-{
-	int value;
-
-	print_temps("Local", ADT7481_LOCAL,
-		    ADT7481_LOCAL_THERM_LIMIT,
-		    ADT7481_LOCAL_HIGH_LIMIT_R,
-		    ADT7481_LOCAL_LOW_LIMIT_R);
-
-	print_temps("Remote1", ADT7481_REMOTE1,
-		    ADT7481_REMOTE1_THERM_LIMIT,
-		    ADT7481_REMOTE1_HIGH_LIMIT_R,
-		    ADT7481_REMOTE1_LOW_LIMIT_R);
-
-	print_temps("Remote2", ADT7481_REMOTE2,
-		    ADT7481_REMOTE2_THERM_LIMIT,
-		    ADT7481_REMOTE2_HIGH_LIMIT,
-		    ADT7481_REMOTE2_LOW_LIMIT);
-
-	ccprintf("\n");
-
-	if (raw_read8(ADT7481_STATUS1_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS1:  %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(ADT7481_STATUS2_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS2:  %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(ADT7481_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(ADT7481_CONFIGURATION2, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
-
-	return EC_SUCCESS;
-}
-
-static int command_adt7481(int argc, char **argv)
-{
-	char *command;
-	char *e;
-	char *power;
-	int data;
-	int offset;
-	int rv;
-
-	/* handle "power" command before checking the power status. */
-	if ((argc == 3) && !strcasecmp(argv[1], "power")) {
-		power = argv[2];
-		if (!strncasecmp(power, "on", sizeof("on"))) {
-			rv = adt7481_set_power(ADT7481_POWER_ON);
-			if (!rv)
-				print_status();
-		} else if (!strncasecmp(power, "off", sizeof("off")))
-			rv = adt7481_set_power(ADT7481_POWER_OFF);
-		else
-			return EC_ERROR_PARAM2;
-		ccprintf("Set ADT7481 %s\n", power);
-		return rv;
-	}
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	/* If no args just print status */
-	if (argc == 1)
-		return print_status();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = argv[1];
-	offset = strtoi(argv[2], &e, 0);
-	if (*e || offset < 0 || offset > 255)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(command, "getbyte")) {
-		rv = raw_read8(offset, &data);
-		if (rv < 0)
-			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
-		return rv;
-	}
-
-	/* Remaining commands are "adt7481 set-command offset data" */
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	data = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(command, "settemp")) {
-		ccprintf("Setting 0x%02x to %dC\n", offset, data);
-		rv = adt7481_set_temp(offset, data);
-	} else if (!strcasecmp(command, "setbyte")) {
-		ccprintf("Setting 0x%02x to 0x%02x\n", offset, data);
-		rv = raw_write8(offset, data);
-	} else
-		return EC_ERROR_PARAM1;
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(adt7481, command_adt7481,
-	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
-	"[power <on|off>]. "
-	"Temps in Celsius.",
-	"Print tmp432 temp sensor status or set parameters.");
-#endif
-
-int adt7481_set_power(enum adt7481_power_state power_on)
-{
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
-	uint8_t shutdown = (power_on == ADT7481_POWER_OFF) ? 1 : 0;
-
-	return adt7481_shutdown(shutdown);
-#else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
-	return EC_SUCCESS;
-#endif
-}
-
diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h
deleted file mode 100644
index 78541a0a3b..0000000000
--- a/driver/temp_sensor/adt7481.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ADT7481 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_ADT7481_H
-#define __CROS_EC_ADT7481_H
-
-#define ADT7481_I2C_ADDR_FLAGS		0x4B
-
-#define ADT7481_IDX_LOCAL	0
-#define ADT7481_IDX_REMOTE1	1
-#define ADT7481_IDX_REMOTE2	2
-
-/* Chip-specific registers */
-#define ADT7481_LOCAL			0x00
-#define ADT7481_REMOTE1			0x01
-#define ADT7481_STATUS1_R		0x02
-#define ADT7481_CONFIGURATION1_R	0x03
-#define ADT7481_CONVERSION_RATE_R	0x04
-#define ADT7481_LOCAL_HIGH_LIMIT_R	0x05
-#define ADT7481_LOCAL_LOW_LIMIT_R	0x06
-#define ADT7481_REMOTE1_HIGH_LIMIT_R	0x07
-#define ADT7481_REMOTE1_LOW_LIMIT_R	0x08
-#define ADT7481_CONFIGURATION1_W	0x09
-#define ADT7481_CONVERSION_RATE_W	0x0a
-#define ADT7481_LOCAL_HIGH_LIMIT_W	0x0b
-#define ADT7481_LOCAL_LOW_LIMIT_W	0x0c
-#define ADT7481_REMOTE1_HIGH_LIMIT_W	0x0d
-#define ADT7481_REMOTE1_LOW_LIMIT_W	0x0e
-#define ADT7481_ONESHOT_W		0x0f
-#define ADT7481_REMOTE1_EXTD_R		0x10
-#define ADT7481_REMOTE1_OFFSET		0x11
-#define ADT7481_REMOTE1_OFFSET_EXTD	0x12
-#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define ADT7481_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define ADT7481_REMOTE1_THERM_LIMIT	0x19
-#define ADT7481_LOCAL_THERM_LIMIT	0x20
-#define ADT7481_THERM_HYSTERESIS	0x21
-#define ADT7481_CONSECUTIVE_ALERT	0x22
-#define ADT7481_STATUS2_R		0x23
-#define ADT7481_CONFIGURATION2		0x24
-#define ADT7481_REMOTE2			0x30
-#define ADT7481_REMOTE2_HIGH_LIMIT	0x31
-#define ADT7481_REMOTE2_LOW_LIMIT	0x32
-#define ADT7481_REMOTE2_EXTD_R		0x33
-#define ADT7481_REMOTE2_OFFSET		0x34
-#define ADT7481_REMOTE2_OFFSET_EXTD	0x35
-#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD	0x36
-#define ADT7481_REMOTE2_LOW_LIMIT_EXTD	0x37
-#define ADT7481_REMOTE2_THERM_LIMIT	0x39
-#define ADT7481_DEVICE_ID		0x3d
-#define ADT7481_MANUFACTURER_ID		0x3e
-
-/* Config1 register bits */
-#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK	BIT(0)
-#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK	BIT(1)
-#define ADT7481_CONFIG1_TEMP_RANGE		BIT(2)
-#define ADT7481_CONFIG1_SEL_REMOTE2		BIT(3)
-/* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */
-#define ADT7481_CONFIG1_MODE			BIT(5)
-#define ADT7481_CONFIG1_RUN_L			BIT(6)
-/* mask all alerts on ALERT# pin */
-#define ADT7481_CONFIG1_ALERT_MASK_L		BIT(7)
-
-/* Config2 register bits */
-#define ADT7481_CONFIG2_LOCK			BIT(7)
-
-/* Conversion Rate/Channel Select Register */
-#define ADT7481_CONV_RATE_MASK		(0x0f)
-#define ADT7481_CONV_RATE_16S		(0x00)
-#define ADT7481_CONV_RATE_8S		(0x01)
-#define ADT7481_CONV_RATE_4S		(0x02)
-#define ADT7481_CONV_RATE_2S		(0x03)
-#define ADT7481_CONV_RATE_1S		(0x04)
-#define ADT7481_CONV_RATE_500MS		(0x05)
-#define ADT7481_CONV_RATE_250MS		(0x06)
-#define ADT7481_CONV_RATE_125MS		(0x07)
-#define ADT7481_CONV_RATE_62500US	(0x08)
-#define ADT7481_CONV_RATE_31250US	(0x09)
-#define ADT7481_CONV_RATE_15500US	(0x0a)
-/* continuous mode 73 ms averaging */
-#define ADT7481_CONV_RATE_73MS_AVE	(0x0b)
-#define ADT7481_CONV_CHAN_SELECT_MASK	(0x30)
-#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN	(0 << 4)
-#define ADT7481_CONV_CHAN_SEL_LOCAL		BIT(4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE1		(2 << 4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE2		(3 << 4)
-#define ADT7481_CONV_AVERAGING_L	BIT(7)
-
-
-/* Status1 register bits */
-#define ADT7481_STATUS1_LOCAL_THERM_ALARM	BIT(0)
-#define ADT7481_STATUS1_REMOTE1_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS1_REMOTE1_OPEN		BIT(2)
-#define ADT7481_STATUS1_REMOTE1_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM	BIT(4)
-#define ADT7481_STATUS1_LOCAL_LOW_ALARM		BIT(5)
-#define ADT7481_STATUS1_LOCAL_HIGH_ALARM	BIT(6)
-#define ADT7481_STATUS1_BUSY			BIT(7)
-
-/* Status2 register bits */
-#define ADT7481_STATUS2_ALERT			BIT(0)
-#define ADT7481_STATUS2_REMOTE2_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS2_REMOTE2_OPEN		BIT(2)
-#define ADT7481_STATUS2_REMOTE2_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM	BIT(4)
-
-/* Consecutive Alert register */
-#define ADT7481_CONSEC_MASK		(0xf)
-#define ADT7481_CONSEC_1		(0x0)
-#define ADT7481_CONSEC_2		(0x2)
-#define ADT7481_CONSEC_3		(0x6)
-#define ADT7481_CONSEC_4		(0xe)
-#define ADT7481_CONSEC_EN_SCL_TIMEOUT	BIT(5)
-#define ADT7481_CONSEC_EN_SDA_TIMEOUT	BIT(6)
-#define ADT7481_CONSEC_MASK_LOCAL_ALERT	BIT(7)
-
-
-/* Limits */
-#define ADT7481_HYSTERESIS_HIGH_LIMIT	255
-#define ADT7481_HYSTERESIS_LOW_LIMIT	0
-
-enum adt7481_power_state {
-	ADT7481_POWER_OFF = 0,
-	ADT7481_POWER_ON,
-	ADT7481_POWER_COUNT
-};
-
-enum adt7481_channel_id {
-	ADT7481_CHANNEL_LOCAL,
-	ADT7481_CHANNEL_REMOTE1,
-	ADT7481_CHANNEL_REMOTE2,
-
-	ADT7481_CHANNEL_COUNT
-};
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int adt7481_get_val(int idx, int *temp_ptr);
-
-/**
- * Power control function of ADT7481 temperature sensor.
- *
- * @param power_on	ADT7481_POWER_ON: turn ADT7481 sensor on.
- *			ADT7481_POWER_OFF: shut ADT7481 sensor down.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int adt7481_set_power(enum adt7481_power_state power_on);
-
-/*
- * Set ADT7481 ALERT#/THERM2# pin to THERM mode, and give a limit
- * for a specific channel.
- *
- * @param channel	specific a channel
- *
- * @param limit_c	High limit temperature, default: 85C
- *
- * @param hysteresis	Hysteresis temperature, default: 10C
- *			All channels share the same hysteresis
- *
- * In THERM mode, ALERT# pin will trigger(Low) by itself when any
- * channel's temperature is greater( >= )than channel's limit_c,
- * and release(High) by itself when channel's temperature is lower
- * than (limit_c - hysteresis)
- */
-int adt7481_set_therm_limit(int channel, int limit_c, int hysteresis);
-#endif /* __CROS_EC_ADT7481_H */
diff --git a/driver/temp_sensor/amd_r19me4070.c b/driver/temp_sensor/amd_r19me4070.c
deleted file mode 100644
index b331a1a3eb..0000000000
--- a/driver/temp_sensor/amd_r19me4070.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* R19ME4070 temperature sensor module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "amd_r19me4070.h"
-#include "power.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* GPU I2C address */
-#define GPU_ADDR_FLAGS                  0x0041
-
-#define GPU_INIT_OFFSET                 0x01
-#define GPU_TEMPERATURE_OFFSET          0x03
-
-static int initialized;
-/*
- * Tell SMBus we want to read 4 Byte from register offset(0x01665A)
- */
-static const uint8_t gpu_init_write_value[5] = {
-	0x04, 0x0F, 0x01, 0x66, 0x5A,
-};
-
-static void gpu_init_temp_sensor(void)
-{
-	int rv;
-	rv = i2c_write_block(I2C_PORT_GPU, GPU_ADDR_FLAGS, GPU_INIT_OFFSET,
-			  gpu_init_write_value,
-			  ARRAY_SIZE(gpu_init_write_value));
-	if (rv == EC_SUCCESS) {
-		initialized = 1;
-		return;
-	}
-	CPRINTS("init GPU fail");
-}
-
-/* INIT GPU first before read the GPU's die tmeperature. */
-int get_temp_R19ME4070(int idx, int *temp_ptr)
-{
-	uint8_t reg[5];
-	int rv;
-
-	/*
-	 * We shouldn't read the GPU temperature when the state
-	 * is not in S0, because GPU is enabled in S0.
-	 */
-	if ((power_get_state()) != POWER_S0) {
-		*temp_ptr = C_TO_K(0);
-		return EC_ERROR_BUSY;
-	}
-	/* if no INIT GPU, must init it first and wait 1 sec. */
-	if (!initialized) {
-		gpu_init_temp_sensor();
-		*temp_ptr = C_TO_K(0);
-		return EC_ERROR_BUSY;
-	}
-	rv = i2c_read_block(I2C_PORT_GPU, GPU_ADDR_FLAGS,
-			GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
-	if (rv) {
-		CPRINTS("read GPU Temperature fail");
-		*temp_ptr = C_TO_K(0);
-		return rv;
-	}
-	/*
-	 * The register is four bytes, bit[17:9] represents the GPU temperature.
-	 * 0x000 : 0	ﾟC
-	 * 0x001 : 1	ﾟC
-	 * 0x002 : 2	ﾟC
-	 * ...
-	 * 0x1FF : 511	ﾟC
-	 * -------------------------------
-	 * reg[4] = bit0  - bit7
-	 * reg[3] = bit8  - bit15
-	 * reg[2] = bit16 - bit23
-	 * reg[1] = bit24 - bit31
-	 * reg[0] = 0x04
-	 */
-	*temp_ptr = C_TO_K(reg[3] >> 1);
-
-	return EC_SUCCESS;
-}
diff --git a/driver/temp_sensor/amd_r19me4070.h b/driver/temp_sensor/amd_r19me4070.h
deleted file mode 100644
index d3c7977ba5..0000000000
--- a/driver/temp_sensor/amd_r19me4070.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GPU R19ME4070 configuration */
-
-#ifndef __CROS_EC_R19ME4070_H
-#define __CROS_EC_R19ME4070_H
-
-/* GPU features */
-#define R19ME4070_LOCAL                 0
-
-/*
- * get GPU temperature value and move to *tem_ptr
- * One second trigger ,Use I2C read GPU's Die temperature.
- */
-int get_temp_R19ME4070(int idx, int *temp_ptr);
-
-#endif /* __CROS_EC_AMD_R19ME4070_H */
diff --git a/driver/temp_sensor/bd99992gw.c b/driver/temp_sensor/bd99992gw.c
deleted file mode 100644
index e66642224c..0000000000
--- a/driver/temp_sensor/bd99992gw.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * BD99992GW PMIC temperature sensor module for Chrome EC.
- * Note that ADC / temperature sensor registers are only active while
- * the PMIC is in S0.
- */
-
-#include "bd99992gw.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-/* List of active channels, ordered by pointer register */
-static enum bd99992gw_adc_channel
-	active_channels[BD99992GW_ADC_POINTER_REG_COUNT];
-
-/*
- * Use 27ms as the period between ADC conversions, as we will typically be
- * sampling temperature sensors every second, and 27ms is the longest
- * supported period.
- */
-#define ADC_LOOP_PERIOD BD99992GW_ADC1CNTL1_SLP27MS
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	int ret;
-	ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			offset, data_ptr);
-	if (ret != EC_SUCCESS)
-		CPRINTS("bd99992gw read fail %d", ret);
-	return ret;
-}
-
-static int raw_write8(const int offset, int data)
-{
-	int ret;
-	ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			 offset, data);
-	if (ret != EC_SUCCESS)
-		CPRINTS("bd99992gw write fail %d", ret);
-	return ret;
-}
-
-static void bd99992gw_init(void)
-{
-	int i;
-	int active_channel_count = 0;
-	uint8_t pointer_reg = BD99992GW_REG_ADC1ADDR0;
-
-	/* Mark active channels from the board temp sensor table */
-	for (i = 0; i < TEMP_SENSOR_COUNT; ++i)
-		if (temp_sensors[i].read == bd99992gw_get_val)
-			active_channels[active_channel_count++] =
-				temp_sensors[i].idx;
-
-	/* Make sure we don't have too many active channels. */
-	ASSERT(active_channel_count <= ARRAY_SIZE(active_channels));
-
-	/* Mark the first unused channel so we know where to stop searching */
-	if (active_channel_count != ARRAY_SIZE(active_channels))
-		active_channels[active_channel_count] =
-			BD99992GW_ADC_CHANNEL_NONE;
-
-	/* Now write pointer regs with channel to monitor */
-	for (i = 0; i < active_channel_count; ++i)
-		/* Write stop bit on last channel */
-		if (raw_write8(pointer_reg + i, active_channels[i] |
-			  ((i == active_channel_count - 1) ?
-			  BD99992GW_ADC1ADDR_STOP : 0)))
-			return;
-
-	/* Enable ADC interrupts */
-	if (raw_write8(BD99992GW_REG_MADC1INT, 0xf & ~BD99992GW_MADC1INT_RND))
-		return;
-	if (raw_write8(BD99992GW_REG_IRQLVL1MSK, BD99992GW_IRQLVL1MSK_MADC))
-		return;
-
-	/* Enable ADC sequencing */
-	if (raw_write8(BD99992GW_REG_ADC1CNTL2, BD99992GW_ADC1CNTL2_ADCTHERM))
-		return;
-
-	/* Start round-robin conversions at 27ms period */
-	raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
-}
-/*
- * Some regs only work in S0, so we must initialize on AP startup in
- * addition to INIT.
- */
-DECLARE_HOOK(HOOK_INIT, bd99992gw_init, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, bd99992gw_init, HOOK_PRIO_DEFAULT);
-
-/* Convert ADC result to temperature in celsius */
-static int bd99992gw_get_temp(uint16_t adc)
-{
-#ifdef CONFIG_THERMISTOR_NCP15WB
-	return ncp15wb_calculate_temp(adc);
-#else
-#error "Unknown thermistor for bd99992gw"
-	return 0;
-#endif
-}
-
-/* Get temperature from requested sensor */
-int bd99992gw_get_val(int idx, int *temp_ptr)
-{
-	uint16_t adc;
-	int i, read, ret;
-	enum bd99992gw_adc_channel channel;
-
-	/* ADC unit is only functional in S0 */
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Find requested channel */
-	for (i = 0; i < ARRAY_SIZE(active_channels); ++i) {
-		channel = active_channels[i];
-		if (channel == idx ||
-		    channel == BD99992GW_ADC_CHANNEL_NONE)
-			break;
-	}
-
-	/* Make sure we found it */
-	if (i == ARRAY_SIZE(active_channels) ||
-	    active_channels[i] != idx) {
-		CPRINTS("Bad ADC channel %d", idx);
-		return EC_ERROR_INVAL;
-	}
-
-	/* Pause conversions */
-	ret = raw_write8(0x80,
-			 ADC_LOOP_PERIOD |
-			 BD99992GW_ADC1CNTL1_ADEN |
-			 BD99992GW_ADC1CNTL1_ADSTRT |
-			 BD99992GW_ADC1CNTL1_ADPAUSE);
-	if (ret)
-		return ret;
-
-	/* Read 10-bit ADC result */
-	ret = raw_read8(BD99992GW_REG_ADC1DATA0L + 2 * i, &read);
-	if (ret)
-		return ret;
-	adc = read;
-	ret = raw_read8(BD99992GW_REG_ADC1DATA0H + 2 * i, &read);
-	if (ret)
-		return ret;
-	adc |= read << 2;
-
-	/* Convert temperature to C / K */
-	*temp_ptr = C_TO_K(bd99992gw_get_temp(adc));
-
-	/* Clear interrupts */
-	ret = raw_write8(BD99992GW_REG_ADC1INT, BD99992GW_ADC1INT_RND);
-	if (ret)
-		return ret;
-	ret = raw_write8(BD99992GW_REG_IRQLVL1, BD99992GW_IRQLVL1_ADC);
-	if (ret)
-		return ret;
-
-	/* Resume conversions */
-	ret = raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
-	if (ret)
-		return ret;
-
-	return EC_SUCCESS;
-}
diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h
deleted file mode 100644
index c461012c45..0000000000
--- a/driver/temp_sensor/bd99992gw.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* G781 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TEMP_SENSOR_BD99992GW_H
-#define __CROS_EC_TEMP_SENSOR_BD99992GW_H
-
-#define BD99992GW_I2C_ADDR_FLAGS	0x30
-
-/* ADC channels */
-enum bd99992gw_adc_channel {
-	BD99992GW_ADC_CHANNEL_NONE      = -1,
-	BD99992GW_ADC_CHANNEL_BATTERY   = 0,
-	BD99992GW_ADC_CHANNEL_AC        = 1,
-	BD99992GW_ADC_CHANNEL_SYSTHERM0 = 2,
-	BD99992GW_ADC_CHANNEL_SYSTHERM1 = 3,
-	BD99992GW_ADC_CHANNEL_SYSTHERM2 = 4,
-	BD99992GW_ADC_CHANNEL_SYSTHERM3 = 5,
-	BD99992GW_ADC_CHANNEL_DIE_TEMP  = 6,
-	BD99992GW_ADC_CHANNEL_VDC       = 7,
-	BD99992GW_ADC_CHANNEL_COUNT     = 8,
-};
-
-/* Registers */
-#define BD99992GW_REG_IRQLVL1		0x02
-#define BD99992GW_IRQLVL1_ADC		 BIT(1) /* ADC IRQ asserted */
-
-#define BD99992GW_REG_ADC1INT		0x03
-#define BD99992GW_ADC1INT_RND		 BIT(0) /* RR cycle completed */
-
-#define BD99992GW_REG_MADC1INT		0x0a
-#define BD99992GW_MADC1INT_RND		 BIT(0) /* RR cycle mask */
-
-#define BD99992GW_REG_IRQLVL1MSK	0x13
-#define BD99992GW_IRQLVL1MSK_MADC	 BIT(1) /* ADC IRQ mask */
-
-#define BD99992GW_REG_ADC1CNTL1		0x80
-#define BD99992GW_ADC1CNTL1_SLP27MS	 (0x6 << 3) /* 27ms between pass */
-#define BD99992GW_ADC1CNTL1_NOLOOP	 (0x7 << 3) /* Single loop pass only */
-#define BD99992GW_ADC1CNTL1_ADPAUSE	 BIT(2)   /* ADC pause */
-#define BD99992GW_ADC1CNTL1_ADSTRT	 BIT(1)   /* ADC start */
-#define BD99992GW_ADC1CNTL1_ADEN	 BIT(0)   /* ADC enable */
-
-#define BD99992GW_REG_ADC1CNTL2		0x81
-#define BD99992GW_ADC1CNTL2_ADCTHERM	 BIT(0) /* Enable ADC sequencing */
-
- /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
-#define BD99992GW_ADC_POINTER_REG_COUNT	8
-#define BD99992GW_REG_ADC1ADDR0		0x82
-#define BD99992GW_REG_ADC1ADDR1		0x83
-#define BD99992GW_REG_ADC1ADDR2		0x84
-#define BD99992GW_REG_ADC1ADDR3		0x85
-#define BD99992GW_REG_ADC1ADDR4		0x86
-#define BD99992GW_REG_ADC1ADDR5		0x87
-#define BD99992GW_REG_ADC1ADDR6		0x88
-#define BD99992GW_REG_ADC1ADDR7		0x89
-#define BD99992GW_ADC1ADDR_STOP		 BIT(3) /* Last conversion channel */
-
-/* Result registers */
-#define BD99992GW_REG_ADC1DATA0L	0x95
-#define BD99992GW_REG_ADC1DATA0H	0x96
-#define BD99992GW_REG_ADC1DATA1L	0x97
-#define BD99992GW_REG_ADC1DATA1H	0x98
-#define BD99992GW_REG_ADC1DATA2L	0x99
-#define BD99992GW_REG_ADC1DATA2H	0x9a
-#define BD99992GW_REG_ADC1DATA3L	0x9b
-#define BD99992GW_REG_ADC1DATA3H	0x9c
-#define BD99992GW_REG_ADC1DATA4L	0x9d
-#define BD99992GW_REG_ADC1DATA4H	0x9e
-#define BD99992GW_REG_ADC1DATA5L	0x9f
-#define BD99992GW_REG_ADC1DATA5H	0xa0
-#define BD99992GW_REG_ADC1DATA6L	0xa1
-#define BD99992GW_REG_ADC1DATA6H	0xa2
-#define BD99992GW_REG_ADC1DATA7L	0xa3
-#define BD99992GW_REG_ADC1DATA7H	0xa4
-
-/**
- * Get the latest value from the sensor.
- *
- * @param idx		ADC channel to read.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int bd99992gw_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
diff --git a/driver/temp_sensor/ec_adc.c b/driver/temp_sensor/ec_adc.c
deleted file mode 100644
index 196d191e47..0000000000
--- a/driver/temp_sensor/ec_adc.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* EC_ADC driver for Chrome EC */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "ec_adc.h"
-#include "temp_sensor/thermistor.h"
-#include "util.h"
-
-/* Get temperature from requested sensor */
-static int get_temp(int idx, int *temp_ptr)
-{
-	int temp_raw = 0;
-
-	/* Read 10-bit ADC result */
-	temp_raw = adc_read_channel(idx);
-
-	if (temp_raw == ADC_READ_ERROR)
-		return EC_ERROR_UNKNOWN;
-
-	/* TODO : Need modification here if the result is not 10-bit */
-
-	/* If there is no thermistor calculation function.
-	 *  1. Add adjusting function like thermistor_ncp15wb.c
-	 *  2. Place function here with ifdef
-	 *  3. define it on board.h
-	 */
-#ifdef CONFIG_THERMISTOR_NCP15WB
-	*temp_ptr = ncp15wb_calculate_temp((uint16_t) temp_raw);
-#else
-#error "Unknown thermistor for ec_adc"
-	return EC_ERROR_UNKNOWN;
-#endif
-
-	return EC_SUCCESS;
-}
-
-int ec_adc_get_val(int idx, int *temp_ptr)
-{
-	int ret;
-	int temp_c;
-
-	if(idx < 0 || idx >= ADC_CH_COUNT)
-		return EC_ERROR_INVAL;
-
-	ret = get_temp(idx, &temp_c);
-	if (ret == EC_SUCCESS)
-		*temp_ptr = C_TO_K(temp_c);
-
-	return ret;
-}
diff --git a/driver/temp_sensor/ec_adc.h b/driver/temp_sensor/ec_adc.h
deleted file mode 100644
index 8ff213e95d..0000000000
--- a/driver/temp_sensor/ec_adc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ec_adc which uses adc and thermistors module for Chrome EC
- * Some EC has it's own ADC modules, define here EC's max ADC channels.
- * We can consider every channel as a thermal sensor.
- */
-
-#ifndef __CROS_EC_TEMP_SENSOR_EC_ADC_H
-#define __CROS_EC_TEMP_SENSOR_EC_ADC_H
-
-/**
- * Get the latest value from the sensor.
- *
- * @param idx		ADC channel to read.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int ec_adc_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */
diff --git a/driver/temp_sensor/f75303.c b/driver/temp_sensor/f75303.c
deleted file mode 100644
index 6b8895a252..0000000000
--- a/driver/temp_sensor/f75303.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* F75303 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "f75303.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-#include "console.h"
-
-static int temps[F75303_IDX_COUNT];
-static int8_t fake_temp[F75303_IDX_COUNT] = {-1, -1, -1};
-
-/**
- * Read 8 bits register from temp sensor.
- */
-static int raw_read8(const int offset, int *data)
-{
-	return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS,
-			 offset, data);
-}
-
-static int get_temp(const int offset, int *temp)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv != 0)
-		return rv;
-
-	*temp = C_TO_K(temp_raw);
-	return EC_SUCCESS;
-}
-
-int f75303_get_val(int idx, int *temp)
-{
-	if (idx < 0 || F75303_IDX_COUNT <= idx)
-		return EC_ERROR_INVAL;
-
-	if (fake_temp[idx] != -1) {
-		*temp = C_TO_K(fake_temp[idx]);
-		return EC_SUCCESS;
-	}
-
-	*temp = temps[idx];
-	return EC_SUCCESS;
-}
-
-static void f75303_sensor_poll(void)
-{
-	get_temp(F75303_TEMP_LOCAL, &temps[F75303_IDX_LOCAL]);
-	get_temp(F75303_TEMP_REMOTE1, &temps[F75303_IDX_REMOTE1]);
-	get_temp(F75303_TEMP_REMOTE2, &temps[F75303_IDX_REMOTE2]);
-}
-DECLARE_HOOK(HOOK_SECOND, f75303_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-static int f75303_set_fake_temp(int argc, char **argv)
-{
-	int index;
-	int value;
-	char *e;
-
-	if (argc != 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	index = strtoi(argv[1], &e, 0);
-	if ((*e) || (index < 0) || (index >= F75303_IDX_COUNT))
-		return EC_ERROR_PARAM1;
-
-	if (!strcasecmp(argv[2], "off")) {
-		fake_temp[index] = -1;
-		ccprintf("Turn off fake temp mode for sensor %u.\n", index);
-		return EC_SUCCESS;
-	}
-
-	value = strtoi(argv[2], &e, 0);
-
-	if ((*e) || (value < 0) || (value > 100))
-		return EC_ERROR_PARAM2;
-
-	fake_temp[index] = value;
-	ccprintf("Force sensor %u = %uC.\n", index, value);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp,
-		"<index> <value>|off",
-		"Set fake temperature of sensor f75303.");
diff --git a/driver/temp_sensor/f75303.h b/driver/temp_sensor/f75303.h
deleted file mode 100644
index bdfd2624f0..0000000000
--- a/driver/temp_sensor/f75303.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* F75303 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_F75303_H
-#define __CROS_EC_F75303_H
-
-#ifdef BOARD_MUSHU
-#define F75303_I2C_ADDR_FLAGS		0x4D
-#else
-#define F75303_I2C_ADDR_FLAGS		0x4C
-#endif
-
-enum f75303_index {
-	F75303_IDX_LOCAL = 0,
-	F75303_IDX_REMOTE1,
-	F75303_IDX_REMOTE2,
-	F75303_IDX_COUNT,
-};
-
-/* F75303 register */
-#define F75303_TEMP_LOCAL		0x00
-#define F75303_TEMP_REMOTE1		0x01
-#define F75303_TEMP_REMOTE2		0x23
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx	Index to read. Idx indicates whether to read die
- *		temperature or external temperature.
- * @param temp	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int f75303_get_val(int idx, int *temp);
-
-#endif  /* __CROS_EC_F75303_H */
diff --git a/driver/temp_sensor/g753.c b/driver/temp_sensor/g753.c
deleted file mode 100644
index 857263c161..0000000000
--- a/driver/temp_sensor/g753.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* G753 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "g753.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_local;
-
-/**
- * Determine whether the sensor is powered.
- *
- * @return non-zero the g753 sensor is powered.
- */
-static int has_power(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return 1;
-#endif
-}
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int raw_write8(const int offset, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			  offset, data);
-}
-#endif
-
-static int get_temp(const int offset, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv < 0)
-		return rv;
-
-	*temp_ptr = (int)(int8_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int set_temp(const int offset, int temp)
-{
-	if (temp < -127 || temp > 127)
-		return EC_ERROR_INVAL;
-
-	return raw_write8(offset, (uint8_t)temp);
-}
-#endif
-
-int g753_get_val(int idx, int *temp_ptr)
-{
-	if (!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	switch (idx) {
-	case G753_IDX_INTERNAL:
-		*temp_ptr = temp_val_local;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void temp_sensor_poll(void)
-{
-	if (!has_power())
-		return;
-
-	get_temp(G753_TEMP_LOCAL, &temp_val_local);
-	temp_val_local = C_TO_K(temp_val_local);
-}
-DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
-			const int high_limit_reg)
-{
-	int value;
-
-	ccprintf("%s:\n", name);
-
-	if (get_temp(temp_reg, &value) == EC_SUCCESS)
-		ccprintf("  Temp:       %3dC\n", value);
-
-	if (get_temp(high_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  High Alarm: %3dC\n", value);
-
-}
-
-static int print_status(void)
-{
-	int value;
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	print_temps("Local", G753_TEMP_LOCAL,
-		    G753_LOCAL_TEMP_HIGH_LIMIT_R);
-
-	ccprintf("\n");
-
-	if (raw_read8(G753_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(G753_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
-
-	return EC_SUCCESS;
-}
-
-static int command_g753(int argc, char **argv)
-{
-	char *command;
-	char *e;
-	int data;
-	int offset;
-	int rv;
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	/* If no args just print status */
-	if (argc == 1)
-		return print_status();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = argv[1];
-	offset = strtoi(argv[2], &e, 0);
-	if (*e || offset < 0 || offset > 255)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(command, "getbyte")) {
-		rv = raw_read8(offset, &data);
-		if (rv < 0)
-			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
-		return rv;
-	}
-
-	/* Remaining commands are of the form "g753 set-command offset data" */
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	data = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(command, "settemp")) {
-		ccprintf("Setting 0x%02x to %dC\n", offset, data);
-		rv = set_temp(offset, data);
-	} else if (!strcasecmp(command, "setbyte")) {
-		ccprintf("Setting 0x%02x to 0x%02x\n", offset, data);
-		rv = raw_write8(offset, data);
-	} else
-		return EC_ERROR_PARAM1;
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(g753, command_g753,
-	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
-	"Temps in Celsius.",
-	"Print g753 temp sensor status or set parameters.");
-#endif
diff --git a/driver/temp_sensor/g753.h b/driver/temp_sensor/g753.h
deleted file mode 100644
index 04c412bfbb..0000000000
--- a/driver/temp_sensor/g753.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* G753 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_G753_H
-#define __CROS_EC_G753_H
-
-
-#define G753_I2C_ADDR_FLAGS			0x48
-
-#define G753_IDX_INTERNAL	0
-
-/* G753 register */
-#define G753_TEMP_LOCAL				0x00
-#define G753_STATUS				0x02
-#define G753_CONFIGURATION_R			0x03
-#define G753_CONVERSION_RATE_R			0x04
-#define G753_LOCAL_TEMP_HIGH_LIMIT_R		0x05
-#define G753_CONFIGURATION_W			0x09
-#define G753_CONVERSION_RATE_W			0x0A
-#define G753_LOCAL_TEMP_HIGH_LIMIT_W		0x0B
-#define G753_ONESHOT				0x0F
-#define G753_Customer_Data_Log_Register_1	0x2D
-#define G753_Customer_Data_Log_Register_2	0x2E
-#define G753_Customer_Data_Log_Register_3	0x2F
-#define G753_ALERT_MODE				0xBF
-#define G753_CHIP_ID				0xFD
-#define G753_VENDOR_ID				0xFE
-#define G753_DEVICE_ID				0xFF
-
-/* Config register bits */
-#define G753_CONFIGURATION_STANDBY		BIT(6)
-#define G753_CONFIGURATION_ALERT_MASK		BIT(7)
-
-/* Status register bits */
-#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G753_STATUS_BUSY			BIT(7)
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int g753_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_G753_H */
diff --git a/driver/temp_sensor/g78x.c b/driver/temp_sensor/g78x.c
deleted file mode 100644
index aef13d3d68..0000000000
--- a/driver/temp_sensor/g78x.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* G781/G782 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "g78x.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_local;
-static int temp_val_remote1;
-#ifdef CONFIG_TEMP_SENSOR_G782
-static int temp_val_remote2;
-#endif
-
-/**
- * Determine whether the sensor is powered.
- *
- * @return non-zero the g781/g782 sensor is powered.
- */
-static int has_power(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return 1;
-#endif
-}
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int raw_write8(const int offset, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			  offset, data);
-}
-#endif
-
-static int get_temp(const int offset, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv < 0)
-		return rv;
-
-	*temp_ptr = (int)(int8_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int set_temp(const int offset, int temp)
-{
-	if (temp < -127 || temp > 127)
-		return EC_ERROR_INVAL;
-
-	return raw_write8(offset, (uint8_t)temp);
-}
-#endif
-
-int g78x_get_val(int idx, int *temp_ptr)
-{
-	if (!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	switch (idx) {
-	case G78X_IDX_INTERNAL:
-		*temp_ptr = temp_val_local;
-		break;
-	case G78X_IDX_EXTERNAL1:
-		*temp_ptr = temp_val_remote1;
-		break;
-#ifdef CONFIG_TEMP_SENSOR_G782
-	case G78X_IDX_EXTERNAL2:
-		*temp_ptr = temp_val_remote2;
-		break;
-#endif
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void temp_sensor_poll(void)
-{
-	if (!has_power())
-		return;
-
-	get_temp(G78X_TEMP_LOCAL, &temp_val_local);
-	temp_val_local = C_TO_K(temp_val_local);
-
-	get_temp(G78X_TEMP_REMOTE1, &temp_val_remote1);
-	temp_val_remote1 = C_TO_K(temp_val_remote1);
-
-#ifdef CONFIG_TEMP_SENSOR_G782
-	get_temp(G78X_TEMP_REMOTE2, &temp_val_remote2);
-	temp_val_remote2 = C_TO_K(temp_val_remote2);
-#endif
-}
-DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
-			const int therm_limit_reg,
-			const int high_limit_reg,
-			const int low_limit_reg)
-{
-	int value;
-
-	ccprintf("%s:\n", name);
-
-	if (get_temp(temp_reg, &value) == EC_SUCCESS)
-		ccprintf("  Temp:       %3dC\n", value);
-
-	if (get_temp(therm_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Therm Trip: %3dC\n", value);
-
-	if (get_temp(high_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  High Alarm: %3dC\n", value);
-
-	if (get_temp(low_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Low Alarm:  %3dC\n", value);
-}
-
-static int print_status(void)
-{
-	int value;
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	print_temps("Local", G78X_TEMP_LOCAL,
-		    G78X_LOCAL_TEMP_THERM_LIMIT,
-		    G78X_LOCAL_TEMP_HIGH_LIMIT_R,
-		    G78X_LOCAL_TEMP_LOW_LIMIT_R);
-
-	print_temps("Remote1", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE1_TEMP_THERM_LIMIT,
-		    G78X_REMOTE1_TEMP_HIGH_LIMIT_R,
-		    G78X_REMOTE1_TEMP_LOW_LIMIT_R);
-
-#ifdef CONFIG_TEMP_SENSOR_G782
-	print_temps("Remote2", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE2_TEMP_THERM_LIMIT,
-		    G78X_REMOTE2_TEMP_HIGH_LIMIT_R,
-		    G78X_REMOTE2_TEMP_LOW_LIMIT_R);
-#endif
-
-	ccprintf("\n");
-
-	if (raw_read8(G78X_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
-
-#ifdef CONFIG_TEMP_SENSOR_G782
-	if (raw_read8(G78X_STATUS1, &value) == EC_SUCCESS)
-		ccprintf("STATUS1: %pb\n", BINARY_VALUE(value, 8));
-#endif
-
-	if (raw_read8(G78X_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
-
-	return EC_SUCCESS;
-}
-
-static int command_g78x(int argc, char **argv)
-{
-	char *command;
-	char *e;
-	int data;
-	int offset;
-	int rv;
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	/* If no args just print status */
-	if (argc == 1)
-		return print_status();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = argv[1];
-	offset = strtoi(argv[2], &e, 0);
-	if (*e || offset < 0 || offset > 255)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(command, "getbyte")) {
-		rv = raw_read8(offset, &data);
-		if (rv < 0)
-			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
-		return rv;
-	}
-
-	/* Remaining commands are of the form "g78x set-command offset data" */
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	data = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(command, "settemp")) {
-		ccprintf("Setting 0x%02x to %dC\n", offset, data);
-		rv = set_temp(offset, data);
-	} else if (!strcasecmp(command, "setbyte")) {
-		ccprintf("Setting 0x%02x to 0x%02x\n", offset, data);
-		rv = raw_write8(offset, data);
-	} else
-		return EC_ERROR_PARAM1;
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(g78x, command_g78x,
-	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
-	"Temps in Celsius.",
-	"Print g781/g782 temp sensor status or set parameters.");
-#endif
diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h
deleted file mode 100644
index fdd987fcbd..0000000000
--- a/driver/temp_sensor/g78x.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* G781/G782 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_G78X_H
-#define __CROS_EC_G78X_H
-
-#if defined(CONFIG_TEMP_SENSOR_G781) && defined(CONFIG_TEMP_SENSOR_G782)
-#error Cannot support both G781 and G782 together!
-#endif
-
-#define G78X_I2C_ADDR_FLAGS		0x4C
-
-#define G78X_IDX_INTERNAL	0
-#define G78X_IDX_EXTERNAL1	1
-#define G78X_IDX_EXTERNAL2	2
-
-#if defined(CONFIG_TEMP_SENSOR_G781)
-/* G781 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_STATUS			0x02
-#define G78X_CONFIGURATION_R		0x03
-#define G78X_CONVERSION_RATE_R		0x04
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x05
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x06
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x07
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x08
-#define G78X_CONFIGURATION_W		0x09
-#define G78X_CONVERSION_RATE_W		0x0a
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x0b
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x0c
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x0d
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x0e
-#define G78X_ONESHOT			0x0f
-#define G78X_REMOTE1_TEMP_EXTENDED	0x10
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x11
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x12
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x13
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x14
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
-
-/* Config register bits */
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
-
-/* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(0)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(1)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(2)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(4)
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
-
-#elif defined(CONFIG_TEMP_SENSOR_G782)
-/* G782 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_TEMP_REMOTE2		0x02
-#define G78X_STATUS			0x03
-#define G78X_CONFIGURATION_R		0x04
-#define G78X_CONFIGURATION_W		0x04
-#define G78X_CONVERSION_RATE_R		0x05
-#define G78X_CONVERSION_RATE_W		0x05
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x06
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x06
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x07
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x07
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x08
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x08
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x09
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x09
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R	0x0a
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W	0x0a
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_R	0x0b
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_W	0x0b
-#define G78X_ONESHOT			0x0c
-#define G78X_REMOTE1_TEMP_EXTENDED	0x0d
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x0e
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x0f
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x10
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x11
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x12
-#define G78X_REMOTE2_TEMP_EXTENDED	0x13
-#define G78X_REMOTE2_TEMP_OFFSET_HIGH	0x14
-#define G78X_REMOTE2_TEMP_OFFSET_EXTD	0x15
-#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD	0x16
-#define G78X_REMOTE2_T_LOW_LIMIT_EXTD	0x17
-#define G78X_REMOTE2_TEMP_THERM_LIMIT	0x18
-#define G78X_STATUS1			0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
-
-/* Config register bits */
-#define G78X_CONFIGURATION_REMOTE2_DIS	BIT(5)
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
-
-/* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(0)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(1)
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(2)
-#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_FAULT		BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
-
-/* Status1 register bits */
-#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM	BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(6)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(7)
-#endif
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int g78x_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_G78X_H */
diff --git a/driver/temp_sensor/oti502.c b/driver/temp_sensor/oti502.c
deleted file mode 100644
index 8a420363e8..0000000000
--- a/driver/temp_sensor/oti502.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* OTI502 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "oti502.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_ambient;	/* Ambient is chip temperature*/
-static int temp_val_object;		/* Object is IR temperature */
-
-static int oti502_read_block(const int offset, uint8_t *data, int len)
-{
-	return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS,
-			 offset, data, len);
-}
-
-int oti502_get_val(int idx, int *temp_ptr)
-{
-	switch (idx) {
-	case OTI502_IDX_AMBIENT:
-		*temp_ptr = temp_val_ambient;
-		break;
-	case OTI502_IDX_OBJECT:
-		*temp_ptr = temp_val_object;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static void temp_sensor_poll(void)
-{
-	uint8_t temp_val[6];
-
-	memset(temp_val, 0, sizeof(temp_val));
-
-	oti502_read_block(0x80, temp_val, sizeof(temp_val));
-
-	if (temp_val[2] >= 0x80) {
-		/* Treat temperature as 0 degree C if temperature is negative*/
-		temp_val_ambient = 0;
-		ccprintf("Temperature ambient is negative !\n");
-	} else {
-		temp_val_ambient = ((temp_val[1] << 8) + temp_val[0]) / 200;
-		temp_val_ambient = C_TO_K(temp_val_ambient);
-	}
-
-	if (temp_val[5] >= 0x80) {
-		/* Treat temperature as 0 degree C if temperature is negative*/
-		temp_val_object = 0;
-		ccprintf("Temperature object is negative !\n");
-	} else {
-		temp_val_object = ((temp_val[4] << 8) + temp_val[5]) / 200;
-		temp_val_object = C_TO_K(temp_val_object);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
diff --git a/driver/temp_sensor/oti502.h b/driver/temp_sensor/oti502.h
deleted file mode 100644
index 4e846282c1..0000000000
--- a/driver/temp_sensor/oti502.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* OTI502 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_OTI502_H
-#define __CROS_EC_OTI502_H
-
-#define OTI502_I2C_ADDR_FLAGS		0x10
-
-#define OTI502_IDX_AMBIENT	0
-#define OTI502_IDX_OBJECT	1
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int oti502_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_OTI502_H */
diff --git a/driver/temp_sensor/sb_tsi.c b/driver/temp_sensor/sb_tsi.c
deleted file mode 100644
index ba47bcb727..0000000000
--- a/driver/temp_sensor/sb_tsi.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SB-TSI: SB Temperature Sensor Interface.
- * This is an I2C temp sensor on the AMD Stony Ridge FT4 SOC.
- */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "sb_tsi.h"
-#include "util.h"
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
-}
-
-int sb_tsi_get_val(int idx, int *temp_ptr)
-{
-	int ret;
-	/* There is only one temp sensor on the FT4 */
-	if (idx != 0)
-		return EC_ERROR_PARAM1;
-	/* FT4 SB-TSI sensor only powered in S0 */
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_ERROR_NOT_POWERED;
-	/* Read the value over I2C */
-	ret = raw_read8(SB_TSI_TEMP_H, temp_ptr);
-	if (ret)
-		return ret;
-	*temp_ptr = C_TO_K(*temp_ptr);
-	return EC_SUCCESS;
-}
diff --git a/driver/temp_sensor/sb_tsi.h b/driver/temp_sensor/sb_tsi.h
deleted file mode 100644
index b7113dbc70..0000000000
--- a/driver/temp_sensor/sb_tsi.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SB-TSI: SB Temperature Sensor Interface.
- * This is an I2C temp sensor on the AMD Stony Ridge FT4 SOC.
- */
-
-#ifndef __CROS_EC_SB_TSI_H
-#define __CROS_EC_SB_TSI_H
-
-#define SB_TSI_I2C_ADDR_FLAGS		0x4C
-
-/* G781 register */
-#define SB_TSI_TEMP_H			0x01
-#define SB_TSI_STATUS			0x02
-#define SB_TSI_CONFIG_1			0x03
-#define SB_TSI_UPDATE_RATE		0x04
-#define SB_TSI_HIGH_TEMP_THRESHOLD_H	0x07
-#define SB_TSI_LOW_TEMP_THRESHOLD_H	0x08
-#define SB_TSI_CONFIG_2			0x09
-#define SB_TSI_TEMP_L			0x10
-#define SB_TSI_TEMP_OFFSET_H		0x11
-#define SB_TSI_TEMP_OFFSET_L		0x12
-#define SB_TSI_HIGH_TEMP_THRESHOLD_L	0x13
-#define SB_TSI_LOW_TEMP_THRESHOLD_L	0x14
-#define SB_TSI_TIMEOUT_CONFIG		0x22
-#define SB_TSI_PSTATE_LIMIT_CONFIG	0x2F
-#define SB_TSI_ALERT_THRESHOLD		0x32
-#define SB_TSI_ALERT_CONFIG		0xBF
-#define SB_TSI_MANUFACTURE_ID		0xFE
-#define SB_TSI_REVISION			0xFF
-
-/**
- * Get the value of a sensor in K.
- *
- * @param idx		Index to read. Only 0 is valid for sb_tsi.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int sb_tsi_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_SB_TSI_H */
diff --git a/driver/temp_sensor/thermistor.c b/driver/temp_sensor/thermistor.c
deleted file mode 100644
index ffa780cb07..0000000000
--- a/driver/temp_sensor/thermistor.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Common thermistor code for Chrome EC. See ./thermistor.md for table of
- * resistance of a 47kΩ B4050 thermistor
- */
-
-#include "adc.h"
-#include "common.h"
-#include "gpio.h"
-#include "temp_sensor/thermistor.h"
-#include "util.h"
-
-int thermistor_linear_interpolate(uint16_t mv,
-		const struct thermistor_info *info)
-{
-	const struct thermistor_data_pair *data = info->data;
-	int v_high = 0, v_low = 0, t_low, t_high, num_steps;
-	int head, tail, mid = 0;
-
-	/* We need at least two points to form a line. */
-	ASSERT(info->num_pairs >= 2);
-
-	/*
-	 * If input value is out of bounds return the lowest or highest
-	 * value in the data sets provided.
-	 */
-	if (mv > data[0].mv * info->scaling_factor)
-		return data[0].temp;
-	else if (mv < data[info->num_pairs - 1].mv * info->scaling_factor)
-		return data[info->num_pairs - 1].temp;
-
-	head = 0;
-	tail = info->num_pairs - 1;
-	while (head != tail) {
-		mid = (head + tail) / 2;
-		v_high = data[mid].mv * info->scaling_factor;
-		v_low = data[mid + 1].mv * info->scaling_factor;
-
-		if ((mv <= v_high) && (mv >= v_low))
-			break;
-		else if (mv > v_high)
-			tail = mid;
-		else if (mv < v_low)
-			head = mid + 1;
-	}
-
-	t_low = data[mid].temp;
-	t_high = data[mid + 1].temp;
-
-	/*
-	 * The obvious way of doing this is to figure out how many mV per
-	 * degree are in between the two points (mv_per_deg_c), and then how
-	 * many of those exist between the input voltage and voltage of
-	 * lower temperature :
-	 *   1. mv_per_deg_c = (v_high - v_low) / (t_high - t_low)
-	 *   2. num_steps = (v_high - mv) / mv_per_deg_c
-	 *   3. result = t_low + num_steps
-	 *
-	 * Combine #1 and #2 to mitigate precision loss due to integer division.
-	 */
-	num_steps = ((v_high - mv) * (t_high - t_low)) / (v_high - v_low);
-	return t_low + num_steps;
-}
-
-#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) || \
-	defined(CONFIG_STEINHART_HART_3V3_13K7_47K_4050B) || \
-	defined(CONFIG_STEINHART_HART_6V0_51K1_47K_4050B) || \
-	defined(CONFIG_STEINHART_HART_3V0_22K6_47K_4050B) || \
-	defined(CONFIG_STEINHART_HART_3V3_30K9_47K_4050B) || \
-	defined(CONFIG_ZEPHYR)
-int thermistor_get_temperature(int idx_adc, int *temp_ptr,
-			       const struct thermistor_info *info)
-{
-	int mv;
-
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	/*
-	 * If the power rail for the thermistor circuit is not enabled, then
-	 * need to ignore any ADC measurments.
-	 */
-	if (!gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO))
-		return EC_ERROR_NOT_POWERED;
-#endif /* CONFIG_TEMP_SENSOR_POWER_GPIO */
-	mv = adc_read_channel(idx_adc);
-	if (mv < 0)
-		return EC_ERROR_UNKNOWN;
-
-	*temp_ptr = thermistor_linear_interpolate(mv, info);
-	*temp_ptr = C_TO_K(*temp_ptr);
-	return EC_SUCCESS;
-}
-#endif
-
-#ifdef CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-/*
- * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=3300mV, R = 51.1Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
- * resistance (R0) = 47Kohm).
- */
-#define THERMISTOR_SCALING_FACTOR_51_47 11
-static const struct thermistor_data_pair thermistor_data_51_47[] = {
-	{ 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0   },
-	{ 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10  },
-	{ 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20  },
-	{ 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30  },
-	{ 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40  },
-	{  802 / THERMISTOR_SCALING_FACTOR_51_47, 50  },
-	{  593 / THERMISTOR_SCALING_FACTOR_51_47, 60  },
-	{  436 / THERMISTOR_SCALING_FACTOR_51_47, 70  },
-	{  321 / THERMISTOR_SCALING_FACTOR_51_47, 80  },
-	{  276 / THERMISTOR_SCALING_FACTOR_51_47, 85  },
-	{  237 / THERMISTOR_SCALING_FACTOR_51_47, 90  },
-	{  204 / THERMISTOR_SCALING_FACTOR_51_47, 95  },
-	{  177 / THERMISTOR_SCALING_FACTOR_51_47, 100 },
-};
-
-static const struct thermistor_info thermistor_info_51_47 = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR_51_47,
-	.num_pairs = ARRAY_SIZE(thermistor_data_51_47),
-	.data = thermistor_data_51_47,
-};
-
-int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr)
-{
-	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_51_47);
-}
-#endif /* CONFIG_STEINHART_HART_3V3_51K1_47K_4050B */
-
-#ifdef CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-/*
- * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=3300mV, R = 13.7Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
- * resistance (R0) = 47Kohm).
- */
-#define THERMISTOR_SCALING_FACTOR_13_47 13
-static const struct thermistor_data_pair thermistor_data_13_47[] = {
-	{ 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0   },
-	{ 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10  },
-	{ 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20  },
-	{ 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30  },
-	{ 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40  },
-	{ 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50  },
-	{ 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60  },
-	{ 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70  },
-	{  947 / THERMISTOR_SCALING_FACTOR_13_47, 80  },
-	{  839 / THERMISTOR_SCALING_FACTOR_13_47, 85  },
-	{  741 / THERMISTOR_SCALING_FACTOR_13_47, 90  },
-	{  653 / THERMISTOR_SCALING_FACTOR_13_47, 95  },
-	{  576 / THERMISTOR_SCALING_FACTOR_13_47, 100 },
-};
-
-static const struct thermistor_info thermistor_info_13_47 = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR_13_47,
-	.num_pairs = ARRAY_SIZE(thermistor_data_13_47),
-	.data = thermistor_data_13_47,
-};
-
-int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr)
-{
-	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_13_47);
-}
-#endif /* CONFIG_STEINHART_HART_3V3_13K7_47K_4050B */
-
-#ifdef CONFIG_STEINHART_HART_6V0_51K1_47K_4050B
-/*
- * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=6000mV, R = 51.1Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
- * resistance (R0) = 47Kohm).
- */
-#define THERMISTOR_SCALING_FACTOR_6V0_51_47 18
-static const struct thermistor_data_pair thermistor_data_6v0_51_47[] = {
-	{ 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0   },
-	{ 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10  },
-	{ 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20  },
-	{ 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30  },
-	{ 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40  },
-	{ 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50  },
-	{ 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60  },
-	{  794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70  },
-	{  584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80  },
-	{  502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85  },
-	{  432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90  },
-	{  372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95  },
-	{  322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 },
-};
-
-static const struct thermistor_info thermistor_info_6v0_51_47 = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR_6V0_51_47,
-	.num_pairs = ARRAY_SIZE(thermistor_data_6v0_51_47),
-	.data = thermistor_data_6v0_51_47,
-};
-
-int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr)
-{
-	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_6v0_51_47);
-}
-#endif /* CONFIG_STEINHART_HART_6V0_51K1_47K_4050B */
-
-#ifdef CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-/*
- * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=3000mV, R = 22.6Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
- * resistance (R0) = 47Kohm).
- */
-#define THERMISTOR_SCALING_FACTOR_22_47 11
-static const struct thermistor_data_pair thermistor_data_22_47[] = {
-	{ 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0   },
-	{ 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10  },
-	{ 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20  },
-	{ 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30  },
-	{ 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40  },
-	{ 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50  },
-	{  994 / THERMISTOR_SCALING_FACTOR_22_47, 60  },
-	{  769 / THERMISTOR_SCALING_FACTOR_22_47, 70  },
-	{  588 / THERMISTOR_SCALING_FACTOR_22_47, 80  },
-	{  513 / THERMISTOR_SCALING_FACTOR_22_47, 85  },
-	{  448 / THERMISTOR_SCALING_FACTOR_22_47, 90  },
-	{  390 / THERMISTOR_SCALING_FACTOR_22_47, 95  },
-	{  340 / THERMISTOR_SCALING_FACTOR_22_47, 100 },
-};
-
-static const struct thermistor_info thermistor_info_22_47 = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR_22_47,
-	.num_pairs = ARRAY_SIZE(thermistor_data_22_47),
-	.data = thermistor_data_22_47,
-};
-
-int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr)
-{
-	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_22_47);
-}
-#endif /* CONFIG_STEINHART_HART_3V0_22K6_47K_4050B */
-
-#ifdef CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-/*
- * Data derived from Steinhart-Hart equation in a resistor divider circuit with
- * Vdd=3300mV, R = 30.9Kohm, and thermistor (B = 4050, T0 = 298.15 K, nominal
- * resistance (R0) = 47Kohm).
- */
-#define THERMISTOR_SCALING_FACTOR_31_47 11
-static const struct thermistor_data_pair thermistor_data_31_47[] = {
-	{ 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0   },
-	{ 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10  },
-	{ 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20  },
-	{ 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30  },
-	{ 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50  },
-	{  878 / THERMISTOR_SCALING_FACTOR_31_47, 60  },
-	{  665 / THERMISTOR_SCALING_FACTOR_31_47, 70  },
-	{  500 / THERMISTOR_SCALING_FACTOR_31_47, 80  },
-	{  375 / THERMISTOR_SCALING_FACTOR_31_47, 90  },
-	{  282 / THERMISTOR_SCALING_FACTOR_31_47, 100 },
-};
-
-static const struct thermistor_info thermistor_info_31_47 = {
-	.scaling_factor = THERMISTOR_SCALING_FACTOR_31_47,
-	.num_pairs = ARRAY_SIZE(thermistor_data_31_47),
-	.data = thermistor_data_31_47,
-};
-
-int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr)
-{
-	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_31_47);
-}
-#endif /* CONFIG_STEINHART_HART_3V3_30K9_47K_4050B */
diff --git a/driver/temp_sensor/thermistor.md b/driver/temp_sensor/thermistor.md
deleted file mode 100644
index bb9faa04ef..0000000000
--- a/driver/temp_sensor/thermistor.md
+++ /dev/null
@@ -1,106 +0,0 @@
-We used the following resistance table for a 47kΩ B4050 thermistor in the
-[thermistor.c](./thermistor.c) tables.
-
-C°   | kΩ
---- | -----
-0   | 155.7
-1   | 147.9
-2   | 140.6
-3   | 133.7
-4   | 127.2
-5   | 121.0
-6   | 115.1
-7   | 109.6
-8   | 104.3
-9   | 99.31
-10  | 94.6
-11  | 90.13
-12  | 85.89
-13  | 81.87
-14  | 78.07
-15  | 74.45
-16  | 71.02
-17  | 67.77
-18  | 64.68
-19  | 61.75
-20  | 58.97
-21  | 56.32
-22  | 53.81
-23  | 51.43
-24  | 49.16
-25  | 47.0
-26  | 44.95
-27  | 42.99
-28  | 41.13
-29  | 39.36
-30  | 37.68
-31  | 36.07
-32  | 34.54
-33  | 33.08
-34  | 31.69
-35  | 30.36
-36  | 29.1
-37  | 27.9
-38  | 26.75
-39  | 25.65
-40  | 24.61
-41  | 23.61
-42  | 22.66
-43  | 21.75
-44  | 20.88
-45  | 20.05
-46  | 19.26
-47  | 18.5
-48  | 17.78
-49  | 17.09
-50  | 16.43
-51  | 15.8
-52  | 15.2
-53  | 14.62
-54  | 14.07
-55  | 13.54
-56  | 13.03
-57  | 12.55
-58  | 12.09
-59  | 11.64
-60  | 11.21
-61  | 10.8
-62  | 10.41
-63  | 10.04
-64  | 9.676
-65  | 9.331
-66  | 8.999
-67  | 8.68
-68  | 8.374
-69  | 8.081
-70  | 7.799
-71  | 7.528
-72  | 7.268
-73  | 7.018
-74  | 6.777
-75  | 6.546
-76  | 6.324
-77  | 6.111
-78  | 5.906
-79  | 5.708
-80  | 5.518
-81  | 5.335
-82  | 5.16
-83  | 4.99
-84  | 4.827
-85  | 4.671
-86  | 4.519
-87  | 4.374
-88  | 4.233
-89  | 4.098
-90  | 3.968
-91  | 3.842
-92  | 3.721
-93  | 3.605
-94  | 3.492
-95  | 3.384
-96  | 3.279
-97  | 3.179
-98  | 3.082
-99  | 2.988
-100 | 2.898
diff --git a/driver/temp_sensor/thermistor_ncp15wb.c b/driver/temp_sensor/thermistor_ncp15wb.c
deleted file mode 100644
index dba06ee326..0000000000
--- a/driver/temp_sensor/thermistor_ncp15wb.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NCP15WB thermistor module for Chrome EC */
-
-#include "common.h"
-#include "temp_sensor/thermistor.h"
-#include "util.h"
-
-/*
- * ADC-to-temp conversion assumes recommended thermistor / resistor
- * configuration (NCP15WB* / 24.9K) with a 10-bit ADC.
- * For 50C through 100C, use linear interpolation from discreet points
- * in table below. For temps < 50C, use a simplified linear function.
- */
-#define ADC_DISCREET_RANGE_START_TEMP	50
-/* 10 bit ADC result corresponding to START_TEMP */
-#define ADC_DISCREET_RANGE_START_RESULT	407
-
-#define ADC_DISCREET_RANGE_LIMIT_TEMP	100
-/* 10 bit ADC result corresponding to LIMIT_TEMP */
-#define ADC_DISCREET_RANGE_LIMIT_RESULT	107
-
-/* Table entries in steppings of 5C */
-#define ADC_DISCREET_RANGE_STEP		5
-
-/* Discreet range ADC results (9 bit) per temperature, in 5 degree steps */
-static const uint8_t adc_result[] = {
-	203,	/* 50 C */
-	178,	/* 55 C */
-	157,	/* 60 C */
-	138,	/* 65 C */
-	121,	/* 70 C */
-	106,	/* 75 C */
-	93,	/* 80 C */
-	81,	/* 85 C */
-	70,	/* 90 C */
-	61,	/* 95 C */
-	53,	/* 100 C */
-};
-
-/*
- * From 20C (reasonable lower limit of temperatures we care about accuracy)
- * to 50C, the temperature curve is roughly linear, so we don't need to include
- * data points in our table.
- */
-#define adc_to_temp(result) (ADC_DISCREET_RANGE_START_TEMP - \
-	(((result) - ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32)
-
-/* Convert ADC result (10 bit) to temperature in celsius */
-int ncp15wb_calculate_temp(uint16_t adc)
-{
-	int temp;
-	int head, tail, mid;
-	uint8_t delta, step;
-
-	/* Is ADC result in linear range? */
-	if (adc >= ADC_DISCREET_RANGE_START_RESULT)
-		temp = adc_to_temp(adc);
-	/* Hotter than our discreet range limit? */
-	else if (adc <= ADC_DISCREET_RANGE_LIMIT_RESULT)
-		temp = ADC_DISCREET_RANGE_LIMIT_TEMP;
-	/* We're in the discreet range */
-	else {
-		/* Table uses 9 bit ADC values */
-		adc /= 2;
-
-		/* Binary search to find proper table entry */
-		head = 0;
-		tail = ARRAY_SIZE(adc_result) - 1;
-		while (head != tail) {
-			mid = (head + tail) / 2;
-			if (adc_result[mid] >= adc &&
-			    adc_result[mid+1] < adc)
-				break;
-			if (adc_result[mid] > adc)
-				head = mid + 1;
-			else
-				tail = mid;
-		}
-
-		/* Now fit between table entries using linear interpolation. */
-		if (head != tail) {
-			delta = adc_result[mid] - adc_result[mid + 1];
-			step = ((adc_result[mid] - adc) *
-				ADC_DISCREET_RANGE_STEP + delta / 2) / delta;
-		} else {
-			/* Edge case where adc = max */
-			mid = head;
-			step = 0;
-		}
-
-		temp = ADC_DISCREET_RANGE_START_TEMP +
-		       ADC_DISCREET_RANGE_STEP * mid + step;
-	}
-
-	return temp;
-}
diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c
deleted file mode 100644
index e4794ccc4a..0000000000
--- a/driver/temp_sensor/tmp006.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP006 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "i2c.h"
-#include "math.h"
-#include "task.h"
-#include "temp_sensor.h"
-#include "tmp006.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-/*
- * Alg 0 was what's in the TMP006 User's Guide.  Alg 1 is Alg 0, but with
- * some filters applied to the Tdie input and Tobj output (see
- * crosbug.com/p/32260).
- */
-#define ALGORITHM_NUM 1
-#define ALGORITHM_PARAMS 12
-
-/* Flags for tdata->fail */
-#define FAIL_INIT        BIT(0)  /* Just initialized */
-#define FAIL_POWER       BIT(1)  /* Sensor not powered */
-#define FAIL_I2C         BIT(2)  /* I2C communication error */
-#define FAIL_NOT_READY   BIT(3)  /* Data not ready */
-
-/* State and conversion factors to track for each sensor */
-struct tmp006_data_t {
-	/* chip info */
-	int16_t v_raw;		 /* TMP006_REG_VOBJ */
-	int16_t t_raw0;		 /* TMP006_REG_TDIE */
-	int fail;		 /* Fail flags; non-zero if last read failed */
-	/* calibration params */
-	float s0, a1, a2;	 /* Sensitivity factors */
-	float b0, b1, b2;	 /* Self-heating correction */
-	float c2;		 /* Seebeck effect */
-	float d0, d1, ds;	 /* Tdie filter and slope adjustment */
-	float e0, e1;		 /* Tobj output filter */
-	/* FIR filter stages */
-	float tdie1, tobj1;
-};
-static struct tmp006_data_t tmp006_data[TMP006_COUNT];
-
-/* Default state and conversion factors */
-static const struct tmp006_data_t tmp006_data_default = {
-	.fail = FAIL_INIT,
-
-	/* Alg 0 params from User's Guide */
-	.s0 = 0.0f,				/* zero == "uncalibrated" */
-	.a1 = 1.75e-3f,
-	.a2 = -1.678e-5f,
-	.b0 = -2.94e-5f,
-	.b1 = -5.7e-7f,
-	.b2 = 4.63e-9f,
-	.c2 = 13.4f,
-
-	/* Additional Alg 1 filter params */
-	.d0 = 0.2f,
-	.d1 = 0.8f,
-	.ds = 1.48e-4,
-	.e0 = 0.1f,
-	.e1 = 0.9f,
-};
-
-static int tmp006_has_power(int idx)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return 1;
-#endif
-}
-
-static void tmp006_poll_sensor(int sensor_id)
-{
-	struct tmp006_data_t *tdata = tmp006_data + sensor_id;
-	int t, v, rv;
-	int addr_flags = tmp006_sensors[sensor_id].addr_flags;
-
-	/* Invalidate the filter history if there is any error */
-	if (tdata->fail) {
-		tdata->tdie1 = 0.0f;
-		tdata->tobj1 = 0.0;
-	}
-
-	if (!tmp006_has_power(sensor_id)) {
-		tdata->fail |= FAIL_POWER;
-		return;
-	}
-
-	/*
-	 * If sensor has just initialized and/or has lost power, wait for
-	 * data ready; otherwise, we read garbage data.
-	 */
-	if (tdata->fail & (FAIL_POWER | FAIL_INIT)) {
-		rv = i2c_read16(TMP006_PORT(addr_flags),
-				TMP006_REG(addr_flags),
-				TMP006_REG_CONFIG, &v);
-		if (rv) {
-			tdata->fail |= FAIL_I2C;
-			return;
-		} else if (!(v & 0x80)) {
-			/* Bit 7 is the Data Ready bit */
-			tdata->fail |= FAIL_NOT_READY;
-			return;
-		}
-	}
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_TDIE, &t);
-	if (rv) {
-		tdata->fail |= FAIL_I2C;
-		return;
-	}
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_VOBJ, &v);
-	if (rv) {
-		tdata->fail |= FAIL_I2C;
-		return;
-	}
-
-	tdata->t_raw0 = t;
-	tdata->v_raw = v;
-
-	tdata->fail = 0;
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void tmp006_init(void)
-{
-	int i;
-
-	for (i = 0; i < TMP006_COUNT; ++i)
-		tmp006_data[i] = tmp006_data_default;
-}
-DECLARE_HOOK(HOOK_INIT, tmp006_init, HOOK_PRIO_DEFAULT);
-
-static void tmp006_poll(void)
-{
-	int i;
-
-	for (i = 0; i < TMP006_COUNT; ++i)
-		tmp006_poll_sensor(i);
-}
-DECLARE_HOOK(HOOK_SECOND, tmp006_poll, HOOK_PRIO_TEMP_SENSOR);
-
-/*****************************************************************************/
-/* Interface to the rest of the EC */
-
-/* This just returns Tdie */
-static int tmp006_read_die_temp_k(const struct tmp006_data_t *tdata,
-				  int *temp_ptr)
-{
-	if (tdata->fail)
-		return EC_ERROR_UNKNOWN;
-
-	/* Tdie reg is signed 1/128 degrees C, resolution 1/32 degrees */
-	*temp_ptr = (int)tdata->t_raw0 / 128 + 273;
-	return EC_SUCCESS;
-}
-
-/*
- * This uses Tdie and Vobj and a bunch of magic parameters to calculate the
- * object temperature, Tobj.
- */
-static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata,
-				     int *temp_ptr)
-{
-	float tdie, vobj;
-	float tx, s, vos, vx, fv, tobj, t4;
-	float tdie_filtered, tdie_slope, tobj_filtered;
-
-	if (tdata->fail)
-		return EC_ERROR_UNKNOWN;
-
-	if (!tdata->s0)
-		return EC_ERROR_NOT_CALIBRATED;
-
-	/* Tdie reg is signed 1/128 degrees C, resolution 1/32 degrees
-	 * We need degrees K */
-	tdie = (float)tdata->t_raw0 / 128.0f + 273.15f;
-	/* Vobj reg is signed int, LSB = 156.25 nV
-	 * We need volts */
-	vobj = (float)tdata->v_raw / 156.25f * 1e-9f;
-
-	/* Alg1: apply filter to tdie. If tdie1 is 0K, initialize it. */
-	if (tdata->tdie1 == 0.0f)
-		tdata->tdie1 = tdie;
-	tdie_filtered = tdata->d0 * tdie + tdata->d1 * tdata->tdie1;
-	tdie_slope = tdie - tdie_filtered;
-	/* Remember the current Tdie for next time */
-	tdata->tdie1 = tdie;
-
-	/* Calculate according to TMP006 users guide. */
-	tx = tdie - 298.15f;
-	/* s is the sensitivity */
-	s = tdata->s0 * (1.0f + tdata->a1 * tx + tdata->a2 * tx * tx);
-	/* vos is the offset voltage */
-	vos = tdata->b0 + tdata->b1 * tx + tdata->b2 * tx * tx;
-	/* Alg1: use Tdie FIR here */
-	vx = vobj - vos + tdie_slope * tdata->ds;
-	/* fv is Seebeck coefficient f(vobj) */
-	fv = vx + tdata->c2 * vx * vx;
-
-	t4 = tdie * tdie * tdie * tdie + fv / s;
-	tobj = sqrtf(sqrtf(t4));
-
-	/* Alg1: apply another filter on the calculated tobj. */
-	if (tdata->tobj1 == 0.0f)
-		tdata->tobj1 = tobj;
-
-	tobj_filtered = tdata->e0 * tobj + tdata->e1 * tdata->tobj1;
-	tdata->tobj1 = tobj;
-
-	/* return integer degrees K */
-	*temp_ptr = tobj_filtered;
-
-	return EC_SUCCESS;
-}
-
-int tmp006_get_val(int idx, int *temp_ptr)
-{
-	/*
-	 * Note: idx is a thermal sensor index, where the top N-1 bits are the
-	 * TMP006 index and the bottom bit is (0=die, 1=remote).
-	 */
-	int tidx = idx >> 1;
-	struct tmp006_data_t *tdata = tmp006_data + tidx;
-
-	if (tdata->fail & FAIL_POWER) {
-		/*
-		 * Sensor isn't powered, or hasn't successfully provided data
-		 * since being powered.  Keep reporting not-powered until
-		 * we get good data (which will clear FAIL_POWER) or there is
-		 * an I2C error.
-		 */
-		return (tdata->fail & FAIL_I2C) ? EC_ERROR_UNKNOWN :
-			EC_ERROR_NOT_POWERED;
-	}
-
-	/* Check the low bit to determine which temperature to read. */
-	if ((idx & 0x1) == 0)
-		return tmp006_read_die_temp_k(tdata, temp_ptr);
-	else
-		return tmp006_read_object_temp_k(tdata, temp_ptr);
-}
-
-/*****************************************************************************/
-/* Host commands */
-
-enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_tmp006_get_calibration *p = args->params;
-	struct ec_response_tmp006_get_calibration_v1 *r1 = args->response;
-	const struct tmp006_data_t *tdata;
-
-	if (p->index >= TMP006_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	tdata = tmp006_data + p->index;
-
-	r1->algorithm = ALGORITHM_NUM;
-	r1->num_params = ALGORITHM_PARAMS;
-	r1->val[0]  = tdata->s0;
-	r1->val[1]  = tdata->a1;
-	r1->val[2]  = tdata->a2;
-	r1->val[3]  = tdata->b0;
-	r1->val[4]  = tdata->b1;
-	r1->val[5]  = tdata->b2;
-	r1->val[6]  = tdata->c2;
-	r1->val[7]  = tdata->d0;
-	r1->val[8]  = tdata->d1;
-	r1->val[9]  = tdata->ds;
-	r1->val[10] = tdata->e0;
-	r1->val[11] = tdata->e1;
-
-	args->response_size = sizeof(*r1) +
-		r1->num_params * sizeof(r1->val[0]);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION,
-		     tmp006_get_calibration,
-		     EC_VER_MASK(1));
-
-enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_tmp006_set_calibration_v1 *p1 = args->params;
-	struct tmp006_data_t *tdata;
-
-	if (p1->index >= TMP006_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	/* We only have one algorithm today */
-	if (p1->algorithm != ALGORITHM_NUM ||
-	    p1->num_params != ALGORITHM_PARAMS)
-		return EC_RES_INVALID_PARAM;
-
-	tdata = tmp006_data + p1->index;
-
-	tdata->s0 = p1->val[0];
-	tdata->a1 = p1->val[1];
-	tdata->a2 = p1->val[2];
-	tdata->b0 = p1->val[3];
-	tdata->b1 = p1->val[4];
-	tdata->b2 = p1->val[5];
-	tdata->c2 = p1->val[6];
-	tdata->d0 = p1->val[7];
-	tdata->d1 = p1->val[8];
-	tdata->ds = p1->val[9];
-	tdata->e0 = p1->val[10];
-	tdata->e1 = p1->val[11];
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION,
-		     tmp006_set_calibration,
-		     EC_VER_MASK(1));
-
-enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_tmp006_get_raw *p = args->params;
-	struct ec_response_tmp006_get_raw *r = args->response;
-	const struct tmp006_data_t *tdata;
-
-	if (p->index >= TMP006_COUNT)
-		return EC_RES_INVALID_PARAM;
-
-	tdata = tmp006_data + p->index;
-
-	/* Vobj reg is signed int, LSB = 156.25 nV
-	 * response units are nV */
-	r->v = ((int)tdata->v_raw * 15625) / 100;
-
-	/* Tdie reg is signed 1/128 degrees C, resolution 1/32 degrees
-	 * response units are 1/100 degrees K */
-	r->t = ((int)tdata->t_raw0 * 100) / 128 + 27315;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW,
-		     tmp006_get_raw,
-		     EC_VER_MASK(0));
-
-/*****************************************************************************/
-/* Console commands */
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-/**
- * Print temperature info for a sensor; used by console command.
- */
-static int tmp006_print(int idx)
-{
-	int vraw, v;
-	int traw, t;
-	int rv;
-	int d;
-	int addr_flags = tmp006_sensors[idx].addr_flags;
-
-
-	ccprintf("Debug data from %s:\n", tmp006_sensors[idx].name);
-
-	if (!tmp006_has_power(idx)) {
-		ccputs("Sensor powered off.\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_MANUFACTURER_ID, &d);
-	if (rv)
-		return rv;
-	ccprintf("  Manufacturer ID: 0x%04x\n", d);
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_DEVICE_ID, &d);
-	ccprintf("  Device ID:       0x%04x\n", d);
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_CONFIG, &d);
-	ccprintf("  Config:          0x%04x\n", d);
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_VOBJ, &vraw);
-
-	v = ((int)vraw * 15625) / 100;
-	ccprintf("  Voltage:         0x%04x = %d nV\n", vraw, v);
-
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
-			TMP006_REG_TDIE, &traw);
-	t = (int)traw;
-	ccprintf("  Temperature:     0x%04x = %d.%02d C\n",
-		 traw, t / 128, t > 0 ? t % 128 : 128 - (t % 128));
-
-	return EC_SUCCESS;
-}
-
-static int command_sensor_info(int argc, char **argv)
-{
-	int i;
-	int rv, rv1;
-	int a = 0, b = TMP006_COUNT;
-
-	if (argc > 1) {
-		char *e = 0;
-		i = strtoi(argv[1], &e, 0);
-		if (*e || i < 0 || i >= TMP006_COUNT)
-			return EC_ERROR_PARAM1;
-		a = i;
-		b = i + 1;
-	}
-
-	rv1 = EC_SUCCESS;
-	for (i = a; i < b; i++) {
-		rv = tmp006_print(i);
-		if (rv != EC_SUCCESS)
-			rv1 = rv;
-		cflush();
-	}
-
-	return rv1;
-}
-DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info,
-			"[ <index> ]",
-			"Print TMP006 sensors");
-#endif
-
-/* Disable the t6cal command until/unless we have FP support in printf */
-#if 0
-static int command_t6cal(int argc, char **argv)
-{
-	struct tmp006_data_t *tdata;
-	char *e;
-	int v;
-	int i;
-
-	if (argc < 2) {
-		ccprintf("# Name            S0          b0"
-			 "         b1          b2\n");
-		for (i = 0; i < TMP006_COUNT; i++) {
-			tdata = tmp006_data + i;
-			ccprintf("%d %-11s"
-				 "%7de-17 %7de-8 %7de-10 %7de-12\n",
-				 i, tmp006_sensors[i].name,
-				 (int)(tdata->s0 * 1e17f),
-				 (int)(tdata->b0 * 1e8f),
-				 (int)(tdata->b1 * 1e10f),
-				 (int)(tdata->b2 * 1e12f));
-		}
-
-		return EC_SUCCESS;
-	}
-
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	i = strtoi(argv[1], &e, 0);
-	if (*e || i < 0 || i >= TMP006_COUNT)
-		return EC_ERROR_PARAM1;
-	tdata = tmp006_data + i;
-
-	v = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(argv[2], "s0"))
-		tdata->s0 = (float)v * 1e-17f;
-	else if (!strcasecmp(argv[2], "b0"))
-		tdata->b0 = (float)v * 1e-8f;
-	else if (!strcasecmp(argv[2], "b1"))
-		tdata->b1 = (float)v * 1e-10f;
-	else if (!strcasecmp(argv[2], "b2"))
-		tdata->b2 = (float)v * 1e-12f;
-	else
-		return EC_ERROR_PARAM2;
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(t6cal, command_t6cal,
-			"[<index> <coeff_name> <radix>]",
-			"Set/print TMP006 calibration");
-#endif
diff --git a/driver/temp_sensor/tmp006.h b/driver/temp_sensor/tmp006.h
deleted file mode 100644
index 594dbc711a..0000000000
--- a/driver/temp_sensor/tmp006.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP006 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TMP006_H
-#define __CROS_EC_TMP006_H
-
-/* Registers within the TMP006 chip */
-#define TMP006_REG_VOBJ            0x00
-#define TMP006_REG_TDIE            0x01
-#define TMP006_REG_CONFIG          0x02
-#define TMP006_REG_MANUFACTURER_ID 0xfe
-#define TMP006_REG_DEVICE_ID       0xff
-
-/* I2C address components */
-#define TMP006_ADDR(PORT, REG) ((PORT << 16) + REG)
-#define TMP006_PORT(ADDR) (ADDR >> 16)
-#define TMP006_REG(ADDR) (ADDR & 0xffff)
-
-struct tmp006_t {
-	const char *name;
-	int addr_flags;	/* I2C address formed by TMP006_ADDR macro. */
-};
-
-/* Names and addresses of the sensors we have */
-extern const struct tmp006_t tmp006_sensors[];
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read.  The low bit in idx indicates whether
- *			to read die temperature or object temperature.  The
- *			other bits serve as internal index to tmp006 module.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp006_get_val(int idx, int *temp_ptr);
-
-#endif  /* __CROS_EC_TMP006_H */
diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c
deleted file mode 100644
index 4da5c4e0e8..0000000000
--- a/driver/temp_sensor/tmp112.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP112 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "tmp112.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "math_util.h"
-#include "util.h"
-
-#define TMP112_RESOLUTION 12
-#define TMP112_SHIFT1 (16 - TMP112_RESOLUTION)
-#define TMP112_SHIFT2 (TMP112_RESOLUTION - 8)
-
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-static int temp_mk_local[TMP112_COUNT];
-
-static int raw_read16(int sensor, const int offset, int *data_ptr)
-{
-#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-	/*
-	 * Don't try to read if the port is unpowered
-	 */
-	if (!board_is_i2c_port_powered(tmp112_sensors[sensor].i2c_port))
-		return EC_ERROR_NOT_POWERED;
-#endif
-	return i2c_read16(tmp112_sensors[sensor].i2c_port,
-			  tmp112_sensors[sensor].i2c_addr_flags,
-			  offset, data_ptr);
-}
-
-static int raw_write16(int sensor, const int offset, int data)
-{
-#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-	/*
-	 * Don't try to write if the port is unpowered
-	 */
-	if (!board_is_i2c_port_powered(tmp112_sensors[sensor].i2c_port))
-		return EC_ERROR_NOT_POWERED;
-#endif
-	return i2c_write16(tmp112_sensors[sensor].i2c_port,
-			   tmp112_sensors[sensor].i2c_addr_flags,
-			   offset, data);
-}
-
-static int get_reg_temp(int sensor, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read16(sensor, TMP112_REG_TEMP, &temp_raw);
-	if (rv)
-		return rv;
-
-	*temp_ptr = (int)(int16_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-static inline int tmp112_reg_to_mk(int16_t reg)
-{
-	int temp_mc;
-
-	temp_mc = (((reg >> TMP112_SHIFT1) * 1000) >> TMP112_SHIFT2);
-
-	return MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc);
-}
-
-int tmp112_get_val_k(int idx, int *temp_k_ptr)
-{
-	if (idx >= TMP112_COUNT)
-		return EC_ERROR_INVAL;
-
-	*temp_k_ptr = MILLI_KELVIN_TO_KELVIN(temp_mk_local[idx]);
-	return EC_SUCCESS;
-}
-
-int tmp112_get_val_mk(int idx, int *temp_mk_ptr)
-{
-	if (idx >= TMP112_COUNT)
-		return EC_ERROR_INVAL;
-
-	*temp_mk_ptr = temp_mk_local[idx];
-	return EC_SUCCESS;
-}
-
-static void tmp112_poll(void)
-{
-	int s;
-	int temp_reg = 0;
-
-	for (s = 0; s < TMP112_COUNT; s++) {
-		if (get_reg_temp(s, &temp_reg) == EC_SUCCESS)
-			temp_mk_local[s] = tmp112_reg_to_mk(temp_reg);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, tmp112_poll, HOOK_PRIO_TEMP_SENSOR);
-
-void tmp112_init(void)
-{
-	int tmp, s, rv;
-	int set_mask, clr_mask;
-
-	/* 12 bit mode */
-	set_mask = (3 << 5);
-
-	/* not oneshot mode */
-	clr_mask = BIT(7);
-
-	for (s = 0; s < TMP112_COUNT; s++) {
-		rv = raw_read16(s, TMP112_REG_CONF, &tmp);
-		if (rv != EC_SUCCESS) {
-			CPRINTS("TMP112-%d: Failed to init (rv %d)", s, rv);
-			continue;
-		}
-		raw_write16(s, TMP112_REG_CONF, (tmp & ~clr_mask) | set_mask);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, tmp112_init, HOOK_PRIO_DEFAULT);
diff --git a/driver/temp_sensor/tmp112.h b/driver/temp_sensor/tmp112.h
deleted file mode 100644
index d1b97b138c..0000000000
--- a/driver/temp_sensor/tmp112.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TMP112_H
-#define __CROS_EC_TMP112_H
-
-#include "i2c.h"
-
-#define TMP112_I2C_ADDR_FLAGS0 (0x48 | I2C_FLAG_BIG_ENDIAN)
-#define TMP112_I2C_ADDR_FLAGS1 (0x49 | I2C_FLAG_BIG_ENDIAN)
-#define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN)
-#define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN)
-
-#define TMP112_REG_TEMP	0x00
-#define TMP112_REG_CONF	0x01
-#define TMP112_REG_HYST	0x02
-#define TMP112_REG_MAX	0x03
-
-/*
- * I2C port and address information for all the board TMP112 sensors should be
- * defined in an array of the following structures, with an enum tmp112_sensor
- * indexing the array.  The enum tmp112_sensor shall end with a TMP112_COUNT
- * defining the maximum number of sensors for the board.
- */
-
-struct tmp112_sensor_t {
-	int i2c_port;
-	int i2c_addr_flags;
-};
-
-extern const struct tmp112_sensor_t tmp112_sensors[];
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read, from board's enum tmp112_sensor
- *			definition
- *
- * @param temp_k_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp112_get_val_k(int idx, int *temp_k_ptr);
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read, from board's enum tmp112_sensor
- *			definition
- *
- * @param temp_mk_ptr	Destination for temperature in mK.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp112_get_val_mk(int idx, int *temp_mk_ptr);
-
-/**
- * Init the sensors.  Note, this will run automatically on HOOK_INIT, but is
- * made available for boards which may not always power the sensor in all
- * states.
- */
-void tmp112_init(void);
-
-#endif /* __CROS_EC_TMP112_H */
diff --git a/driver/temp_sensor/tmp411.c b/driver/temp_sensor/tmp411.c
deleted file mode 100644
index ef22052da8..0000000000
--- a/driver/temp_sensor/tmp411.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP411 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "tmp411.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_local;
-static int temp_val_remote1;
-static uint8_t is_sensor_shutdown;
-
-/**
- * Determine whether the sensor is powered.
- *
- * @return non-zero the tmp411 sensor is powered.
- */
-static int has_power(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return !is_sensor_shutdown;
-#endif
-}
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL, TMP411_I2C_ADDR, offset, data_ptr);
-}
-
-static int raw_write8(const int offset, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL, TMP411_I2C_ADDR, offset, data);
-}
-
-static int get_temp(const int offset, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv < 0)
-		return rv;
-
-	*temp_ptr = (int)(int8_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int tmp411_set_temp(const int offset, int temp)
-{
-	if (temp < -127 || temp > 127)
-		return EC_ERROR_INVAL;
-
-	return raw_write8(offset, (uint8_t)temp);
-}
-#endif
-
-int tmp411_get_val(int idx, int *temp_ptr)
-{
-	if (!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	switch (idx) {
-	case TMP411_IDX_LOCAL:
-		*temp_ptr = temp_val_local;
-		break;
-	case TMP411_IDX_REMOTE1:
-		*temp_ptr = temp_val_remote1;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int tmp411_shutdown(uint8_t want_shutdown)
-{
-	int ret, value;
-
-	if (want_shutdown == is_sensor_shutdown)
-		return EC_SUCCESS;
-
-	ret = raw_read8(TMP411_CONFIGURATION1_R, &value);
-	if (ret < 0) {
-		ccprintf("ERROR: Temp sensor I2C read8 error.\n");
-		return ret;
-	}
-
-	if (want_shutdown && !(value & TMP411_CONFIG1_RUN_L)) {
-		/* tmp411 is running, and want it to shutdown */
-		/* CONFIG REG1 BIT6: 0=Run, 1=Shutdown */
-		/* shut it down */
-		value |= TMP411_CONFIG1_RUN_L;
-		ret = raw_write8(TMP411_CONFIGURATION1_R, value);
-	} else if (!want_shutdown && (value & TMP411_CONFIG1_RUN_L)) {
-		/* tmp411 is shutdown, and want turn it on */
-		value &= ~TMP411_CONFIG1_RUN_L;
-		ret = raw_write8(TMP411_CONFIGURATION1_R, value);
-	}
-	/* else, the current setting is exactly what you want */
-
-	is_sensor_shutdown = want_shutdown;
-	return ret;
-}
-
-static int tmp411_set_therm_mode(void)
-{
-	int ret = 0;
-	int data = 0;
-
-	ret = raw_read8(TMP411_CONFIGURATION1_R, &data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	data |= TMP411_CONFIG1_MODE;
-	ret = raw_write8(TMP411_CONFIGURATION1_W, data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-int tmp411_set_therm_limit(int channel, int limit_c, int hysteresis)
-{
-	int ret = 0;
-	int reg = 0;
-
-	if (channel >= TMP411_CHANNEL_COUNT)
-		return EC_ERROR_INVAL;
-
-	if (hysteresis > TMP411_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP411_HYSTERESIS_LOW_LIMIT)
-		return EC_ERROR_INVAL;
-
-	/* hysteresis must be less than high limit */
-	if (hysteresis > limit_c)
-		return EC_ERROR_INVAL;
-
-	if (tmp411_set_therm_mode() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	switch (channel) {
-	case TMP411_CHANNEL_LOCAL:
-		reg = TMP411_LOCAL_HIGH_LIMIT_W;
-		break;
-	case TMP411_CHANNEL_REMOTE1:
-		reg = TMP411_REMOTE1_HIGH_LIMIT_W;
-		break;
-	}
-
-	ret = raw_write8(reg, limit_c);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	ret = raw_write8(TMP411_THERM_HYSTERESIS, hysteresis);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static void tmp411_temp_sensor_poll(void)
-{
-	int temp_c;
-
-	if (!has_power())
-		return;
-
-	if (get_temp(TMP411_LOCAL, &temp_c) == EC_SUCCESS)
-		temp_val_local = C_TO_K(temp_c);
-
-	if (get_temp(TMP411_REMOTE1, &temp_c) == EC_SUCCESS)
-		temp_val_remote1 = C_TO_K(temp_c);
-
-}
-DECLARE_HOOK(HOOK_SECOND, tmp411_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int tmp411_temp_reg,
-		const int tmp411_therm_limit_reg,
-		const int tmp411_high_limit_reg,
-		const int tmp411_low_limit_reg)
-{
-	int value;
-
-	if (!has_power()) {
-		ccprintf("  TMP411 is shutdown\n");
-		return;
-	}
-
-	ccprintf("%s:\n", name);
-
-	if (get_temp(tmp411_temp_reg, &value) == EC_SUCCESS)
-		ccprintf("  Temp       %3dC\n", value);
-
-	if (get_temp(tmp411_therm_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Therm Trip %3dC\n", value);
-
-	if (get_temp(tmp411_high_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  High Alarm %3dC\n", value);
-
-	if (get_temp(tmp411_low_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Low Alarm  %3dC\n", value);
-}
-
-static int print_status(void)
-{
-	int value;
-
-	print_temps("Local", TMP411_LOCAL,
-		    TMP411_LOCAL_THERM_LIMIT,
-		    TMP411_LOCAL_HIGH_LIMIT_R,
-		    TMP411_LOCAL_LOW_LIMIT_R);
-
-	print_temps("Remote1", TMP411_REMOTE1,
-		    TMP411_REMOTE1_THERM_LIMIT,
-		    TMP411_REMOTE1_HIGH_LIMIT_R,
-		    TMP411_REMOTE1_LOW_LIMIT_R);
-
-	ccprintf("\n");
-
-	if (raw_read8(TMP411_STATUS_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(TMP411_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
-
-	return EC_SUCCESS;
-}
-
-static int command_tmp411(int argc, char **argv)
-{
-	char *command;
-	char *e;
-	char *power;
-	int data;
-	int offset;
-	int rv;
-
-	/* handle "power" command before checking the power status. */
-	if ((argc == 3) && !strcasecmp(argv[1], "power")) {
-		power = argv[2];
-		if (!strncasecmp(power, "on", sizeof("on"))) {
-			rv = tmp411_set_power(TMP411_POWER_ON);
-			if (!rv)
-				print_status();
-		} else if (!strncasecmp(power, "off", sizeof("off")))
-			rv = tmp411_set_power(TMP411_POWER_OFF);
-		else
-			return EC_ERROR_PARAM2;
-		ccprintf("Set TMP411 %s\n", power);
-		return rv;
-	}
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	/* If no args just print status */
-	if (argc == 1)
-		return print_status();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = argv[1];
-	offset = strtoi(argv[2], &e, 0);
-	if (*e || offset < 0 || offset > 255)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(command, "getbyte")) {
-		rv = raw_read8(offset, &data);
-		if (rv < 0)
-			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
-		return rv;
-	}
-
-	/* Remaining commands are "tmp411 set-command offset data" */
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	data = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(command, "settemp")) {
-		ccprintf("Setting 0x%02x to %dC\n", offset, data);
-		rv = tmp411_set_temp(offset, data);
-	} else if (!strcasecmp(command, "setbyte")) {
-		ccprintf("Setting 0x%02x to 0x%02x\n", offset, data);
-		rv = raw_write8(offset, data);
-	} else
-		return EC_ERROR_PARAM1;
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(tmp411, command_tmp411,
-	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
-	"[power <on|off>]. "
-	"Temps in Celsius.",
-	"Print tmp411 temp sensor status or set parameters.");
-#endif
-
-int tmp411_set_power(enum tmp411_power_state power_on)
-{
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
-	uint8_t shutdown = (power_on == TMP411_POWER_OFF) ? 1 : 0;
-
-	return tmp411_shutdown(shutdown);
-#else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
-	return EC_SUCCESS;
-#endif
-}
-
diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h
deleted file mode 100644
index ef1b23278c..0000000000
--- a/driver/temp_sensor/tmp411.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP411 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TMP411_H
-#define __CROS_EC_TMP411_H
-
-#define TMP411_I2C_ADDR_FLAGS		0x4C
-
-#define TMP411_IDX_LOCAL	0
-#define TMP411_IDX_REMOTE1	1
-#define TMP411_IDX_REMOTE2	2
-
-/* Chip-specific registers */
-#define TMP411_LOCAL			0x00
-#define TMP411_REMOTE1			0x01
-#define TMP411_STATUS_R			0x02
-#define TMP411_CONFIGURATION1_R		0x03
-#define TMP411_CONVERSION_RATE_R	0x04
-#define TMP411_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP411_LOCAL_LOW_LIMIT_R	0x06
-#define TMP411_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP411_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP411_CONFIGURATION1_W		0x09
-#define TMP411_CONVERSION_RATE_W	0x0a
-#define TMP411_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP411_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP411_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP411_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP411_ONESHOT			0x0f
-#define TMP411_REMOTE1_EXTD		0x10
-#define TMP411_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP411_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP411_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP411_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP411_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP411_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP411_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP411_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP411_REMOTE1_THERM_LIMIT	0x19
-#define TMP411_REMOTE2_THERM_LIMIT	0x1a
-#define TMP411_STATUS_FAULT		0x1b
-#define TMP411_CHANNEL_MASK		0x1f
-#define TMP411_LOCAL_THERM_LIMIT	0x20
-#define TMP411_THERM_HYSTERESIS		0x21
-#define TMP411_CONSECUTIVE_ALERT	0x22
-#define TMP411_REMOTE2			0x23
-#define TMP411_REMOTE2_EXTD		0x24
-#define TMP411_BETA_RANGE_CH1		0x25
-#define TMP411_BETA_RANGE_CH2		0x26
-#define TMP411_NFACTOR_REMOTE1		0x27
-#define TMP411_NFACTOR_REMOTE2		0x28
-#define TMP411_LOCAL_EXTD		0x29
-#define TMP411_STATUS_LIMIT_HIGH	0x35
-#define TMP411_STATUS_LIMIT_LOW		0x36
-#define TMP411_STATUS_THERM		0x37
-#define TMP411_RESET_W			0xfc
-#define TMP411_MANUFACTURER_ID		0xfe
-#define TMP411_DEVICE_ID		0xff
-
-#define TMP411A_DEVICE_ID_VAL		0x12
-#define TMP411B_DEVICE_ID_VAL		0x13
-#define TMP411C_DEVICE_ID_VAL		0x10
-#define TMP411d_DEVICE_ID_VAL		0x12
-
-/* Config register bits */
-#define TMP411_CONFIG1_TEMP_RANGE	BIT(2)
-/* TMP411_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP411_CONFIG1_MODE		BIT(5)
-#define TMP411_CONFIG1_RUN_L		BIT(6)
-#define TMP411_CONFIG1_ALERT_MASK_L	BIT(7)
-
-/* Status register bits */
-#define TMP411_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP411_STATUS_OPEN		BIT(2)
-#define TMP411_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP411_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define TMP411_STATUS_BUSY		BIT(7)
-
-/* Limits */
-#define TMP411_HYSTERESIS_HIGH_LIMIT	255
-#define TMP411_HYSTERESIS_LOW_LIMIT	0
-
-enum tmp411_power_state {
-	TMP411_POWER_OFF = 0,
-	TMP411_POWER_ON,
-	TMP411_POWER_COUNT
-};
-
-enum tmp411_channel_id {
-	TMP411_CHANNEL_LOCAL,
-	TMP411_CHANNEL_REMOTE1,
-
-	TMP411_CHANNEL_COUNT
-};
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp411_get_val(int idx, int *temp_ptr);
-
-/**
- * Power control function of tmp411 temperature sensor.
- *
- * @param power_on	TMP411_POWER_ON: turn tmp411 sensor on.
- *			TMP411_POWER_OFF: shut tmp411 sensor down.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp411_set_power(enum tmp411_power_state power_on);
-
-/*
- * Set TMP411 ALERT#/THERM2# pin to THERM mode, and give a limit
- * for a specific channel.
- *
- * @param channel	specific a channel
- *
- * @param limit_c	High limit temperature, default: 85C
- *
- * @param hysteresis	Hysteresis temperature, default: 10C
- *			All channels share the same hysteresis
- *
- * In THERM mode, ALERT# pin will trigger(Low) by itself when any
- * channel's temperature is greater( >= )than channel's limit_c,
- * and release(High) by itself when channel's temperature is lower
- * than (limit_c - hysteresis)
- */
-int tmp411_set_therm_limit(int channel, int limit_c, int hysteresis);
-#endif /* __CROS_EC_TMP411_H */
diff --git a/driver/temp_sensor/tmp432.c b/driver/temp_sensor/tmp432.c
deleted file mode 100644
index 6260678dcd..0000000000
--- a/driver/temp_sensor/tmp432.c
+++ /dev/null
@@ -1,399 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP432 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "tmp432.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-static int temp_val_local;
-static int temp_val_remote1;
-static int temp_val_remote2;
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
-static uint8_t is_sensor_shutdown;
-#endif
-static int fake_temp[TMP432_IDX_COUNT] = {-1, -1, -1};
-
-/**
- * Determine whether the sensor is powered.
- *
- * @return non-zero the tmp432 sensor is powered.
- */
-static int has_power(void)
-{
-#ifdef CONFIG_TEMP_SENSOR_POWER_GPIO
-	return gpio_get_level(CONFIG_TEMP_SENSOR_POWER_GPIO);
-#else
-	return !is_sensor_shutdown;
-#endif
-}
-
-static int raw_read8(const int offset, int *data_ptr)
-{
-	return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
-}
-
-static int raw_write8(const int offset, int data)
-{
-	return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			  offset, data);
-}
-
-static int get_temp(const int offset, int *temp_ptr)
-{
-	int rv;
-	int temp_raw = 0;
-
-	rv = raw_read8(offset, &temp_raw);
-	if (rv < 0)
-		return rv;
-
-	*temp_ptr = (int)(int8_t)temp_raw;
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int tmp432_set_temp(const int offset, int temp)
-{
-	if (temp < -127 || temp > 127)
-		return EC_ERROR_INVAL;
-
-	return raw_write8(offset, (uint8_t)temp);
-}
-#endif
-
-int tmp432_get_val(int idx, int *temp_ptr)
-{
-	if (!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	switch (idx) {
-	case TMP432_IDX_LOCAL:
-		*temp_ptr = temp_val_local;
-		break;
-	case TMP432_IDX_REMOTE1:
-		*temp_ptr = temp_val_remote1;
-		break;
-	case TMP432_IDX_REMOTE2:
-		*temp_ptr = temp_val_remote2;
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
-static int tmp432_shutdown(uint8_t want_shutdown)
-{
-	int ret, value;
-
-	if (want_shutdown == is_sensor_shutdown)
-		return EC_SUCCESS;
-
-	ret = raw_read8(TMP432_CONFIGURATION1_R, &value);
-	if (ret < 0) {
-		ccprintf("ERROR: Temp sensor I2C read8 error.\n");
-		return ret;
-	}
-
-	if (want_shutdown && !(value & TMP432_CONFIG1_RUN_L)) {
-		/* tmp432 is running, and want it to shutdown */
-		/* CONFIG REG1 BIT6: 0=Run, 1=Shutdown */
-		/* shut it down */
-		value |= TMP432_CONFIG1_RUN_L;
-		ret = raw_write8(TMP432_CONFIGURATION1_R, value);
-	} else if (!want_shutdown && (value & TMP432_CONFIG1_RUN_L)) {
-		/* tmp432 is shutdown, and want turn it on */
-		value &= ~TMP432_CONFIG1_RUN_L;
-		ret = raw_write8(TMP432_CONFIGURATION1_R, value);
-	}
-	/* else, the current setting is exactly what you want */
-
-	is_sensor_shutdown = want_shutdown;
-	return ret;
-}
-#endif
-
-static int tmp432_set_therm_mode(void)
-{
-	int ret = 0;
-	int data = 0;
-
-	ret = raw_read8(TMP432_CONFIGURATION1_R, &data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	data |= TMP432_CONFIG1_MODE;
-	ret = raw_write8(TMP432_CONFIGURATION1_W, data);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-int tmp432_set_therm_limit(int channel, int limit_c, int hysteresis)
-{
-	int ret = 0;
-	int reg = 0;
-
-	if (channel >= TMP432_CHANNEL_COUNT)
-		return EC_ERROR_INVAL;
-
-	if (hysteresis > TMP432_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP432_HYSTERESIS_LOW_LIMIT)
-		return EC_ERROR_INVAL;
-
-	/* hysteresis must be less than high limit */
-	if (hysteresis > limit_c)
-		return EC_ERROR_INVAL;
-
-	if (tmp432_set_therm_mode() != EC_SUCCESS)
-		return EC_ERROR_UNKNOWN;
-
-	switch (channel) {
-	case TMP432_CHANNEL_LOCAL:
-		reg = TMP432_LOCAL_HIGH_LIMIT_W;
-		break;
-	case TMP432_CHANNEL_REMOTE1:
-		reg = TMP432_REMOTE1_HIGH_LIMIT_W;
-		break;
-	case TMP432_CHANNEL_REMOTE2:
-		reg = TMP432_REMOTE2_HIGH_LIMIT_W;
-		break;
-	}
-
-	ret = raw_write8(reg, limit_c);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	ret = raw_write8(TMP432_THERM_HYSTERESIS, hysteresis);
-	if (ret)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static void temp_sensor_poll(void)
-{
-	int temp_c;
-
-	if (!has_power())
-		return;
-
-	if (fake_temp[TMP432_IDX_LOCAL] != -1) {
-		temp_val_local = C_TO_K(fake_temp[TMP432_IDX_LOCAL]);
-	} else {
-		if (get_temp(TMP432_LOCAL, &temp_c) == EC_SUCCESS)
-			temp_val_local = C_TO_K(temp_c);
-		/* else: Keep previous value when it fails */
-	}
-
-	if (fake_temp[TMP432_IDX_REMOTE1] != -1) {
-		temp_val_remote1 = C_TO_K(fake_temp[TMP432_IDX_REMOTE1]);
-	} else {
-		if (get_temp(TMP432_REMOTE1, &temp_c) == EC_SUCCESS)
-			temp_val_remote1 = C_TO_K(temp_c);
-		/* else: Keep previous value when it fails */
-	}
-
-	if (fake_temp[TMP432_IDX_REMOTE2] != -1) {
-		temp_val_remote2 = C_TO_K(fake_temp[TMP432_IDX_REMOTE2]);
-	} else {
-		if (get_temp(TMP432_REMOTE2, &temp_c) == EC_SUCCESS)
-			temp_val_remote2 = C_TO_K(temp_c);
-		/* else: Keep previous value when it fails */
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-#ifdef CONFIG_CMD_TEMP_SENSOR
-static int tmp432_set_fake_temp(int index, int degree_c)
-{
-	if ((index < 0) || (index >= TMP432_IDX_COUNT))
-		return EC_ERROR_INVAL;
-
-	fake_temp[index] = degree_c;
-	ccprintf("New degree will be updated 1 sec later\n\n");
-
-	return EC_SUCCESS;
-}
-
-static void print_temps(
-		const char *name,
-		const int tmp432_temp_reg,
-		const int tmp432_therm_limit_reg,
-		const int tmp432_high_limit_reg,
-		const int tmp432_low_limit_reg)
-{
-	int value;
-
-	if (!has_power()) {
-		ccprintf("  TMP432 is shutdown\n");
-		return;
-	}
-
-	ccprintf("%s:\n", name);
-
-	if (get_temp(tmp432_temp_reg, &value) == EC_SUCCESS)
-		ccprintf("  Temp       %3dC\n", value);
-
-	if (get_temp(tmp432_therm_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Therm Trip %3dC\n", value);
-
-	if (get_temp(tmp432_high_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  High Alarm %3dC\n", value);
-
-	if (get_temp(tmp432_low_limit_reg, &value) == EC_SUCCESS)
-		ccprintf("  Low Alarm  %3dC\n", value);
-}
-
-static int print_status(void)
-{
-	int value, i;
-
-	print_temps("Local", TMP432_LOCAL,
-		    TMP432_LOCAL_THERM_LIMIT,
-		    TMP432_LOCAL_HIGH_LIMIT_R,
-		    TMP432_LOCAL_LOW_LIMIT_R);
-
-	print_temps("Remote1", TMP432_REMOTE1,
-		    TMP432_REMOTE1_THERM_LIMIT,
-		    TMP432_REMOTE1_HIGH_LIMIT_R,
-		    TMP432_REMOTE1_LOW_LIMIT_R);
-
-	print_temps("Remote2", TMP432_REMOTE2,
-		    TMP432_REMOTE2_THERM_LIMIT,
-		    TMP432_REMOTE2_HIGH_LIMIT_R,
-		    TMP432_REMOTE2_LOW_LIMIT_R);
-
-	ccprintf("\n");
-
-	for (i = 0; i < TMP432_IDX_COUNT; ++i) {
-		ccprintf("fake temperature[%d]= ", i);
-		if (fake_temp[i] == -1) {
-			ccprintf("Not overridden\n");
-			continue;
-		}
-
-		if (tmp432_get_val(i, &value) == EC_SUCCESS)
-			ccprintf("%d C or %d K\n", (value - 273), value);
-		else
-			ccprintf("Access error\n");
-	}
-
-	ccprintf("\n");
-
-	if (raw_read8(TMP432_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(TMP432_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
-
-	if (raw_read8(TMP432_CONFIGURATION2_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
-
-	return EC_SUCCESS;
-}
-
-static int command_tmp432(int argc, char **argv)
-{
-	char *command;
-	char *e;
-	char *power;
-	int data;
-	int offset;
-	int rv;
-
-	/* handle "power" command before checking the power status. */
-	if ((argc == 3) && !strcasecmp(argv[1], "power")) {
-		power = argv[2];
-		if (!strncasecmp(power, "on", sizeof("on"))) {
-			rv = tmp432_set_power(TMP432_POWER_ON);
-			if (!rv)
-				print_status();
-		}
-		else if (!strncasecmp(power, "off", sizeof("off")))
-			rv = tmp432_set_power(TMP432_POWER_OFF);
-		else
-			return EC_ERROR_PARAM2;
-		ccprintf("Set TMP432 %s\n", power);
-		return rv;
-	}
-
-	if (!has_power()) {
-		ccprintf("ERROR: Temp sensor not powered.\n");
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	/* If no args just print status */
-	if (argc == 1)
-		return print_status();
-
-	if (argc < 3)
-		return EC_ERROR_PARAM_COUNT;
-
-	command = argv[1];
-	offset = strtoi(argv[2], &e, 0);
-	if (*e || offset < 0 || offset > 255)
-		return EC_ERROR_PARAM2;
-
-	if (!strcasecmp(command, "getbyte")) {
-		rv = raw_read8(offset, &data);
-		if (rv < 0)
-			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
-		return rv;
-	}
-
-	/* Remaining commands are "tmp432 set-command offset data" */
-	if (argc != 4)
-		return EC_ERROR_PARAM_COUNT;
-
-	data = strtoi(argv[3], &e, 0);
-	if (*e)
-		return EC_ERROR_PARAM3;
-
-	if (!strcasecmp(command, "settemp")) {
-		ccprintf("Setting 0x%02x to %dC\n", offset, data);
-		rv = tmp432_set_temp(offset, data);
-	} else if (!strcasecmp(command, "setbyte")) {
-		ccprintf("Setting 0x%02x to 0x%02x\n", offset, data);
-		rv = raw_write8(offset, data);
-	} else if (!strcasecmp(command, "fake")) {
-		ccprintf("Hook temperature\n");
-		rv = tmp432_set_fake_temp(offset, data);
-		print_status();
-	} else
-		return EC_ERROR_PARAM1;
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(tmp432, command_tmp432,
-	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
-	"[fake <index> <value>] or [power <on|off>]. "
-	"Temps in Celsius.",
-	"Print tmp432 temp sensor status or set parameters.");
-#endif
-
-int tmp432_set_power(enum tmp432_power_state power_on)
-{
-#ifndef CONFIG_TEMP_SENSOR_POWER_GPIO
-	uint8_t shutdown = (power_on == TMP432_POWER_OFF) ? 1 : 0;
-	return tmp432_shutdown(shutdown);
-#else
-	gpio_set_level(CONFIG_TEMP_SENSOR_POWER_GPIO, power_on);
-	return EC_SUCCESS;
-#endif
-}
-
diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h
deleted file mode 100644
index e58e39a4a0..0000000000
--- a/driver/temp_sensor/tmp432.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP432 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TMP432_H
-#define __CROS_EC_TMP432_H
-
-#define TMP432_I2C_ADDR_FLAGS		0x4C
-
-#define TMP432_IDX_LOCAL	0
-#define TMP432_IDX_REMOTE1	1
-#define TMP432_IDX_REMOTE2	2
-#define TMP432_IDX_COUNT	3
-
-/* Chip-specific registers */
-#define TMP432_LOCAL			0x00
-#define TMP432_REMOTE1			0x01
-#define TMP432_STATUS			0x02
-#define TMP432_CONFIGURATION1_R		0x03
-#define TMP432_CONVERSION_RATE_R	0x04
-#define TMP432_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP432_LOCAL_LOW_LIMIT_R	0x06
-#define TMP432_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP432_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP432_CONFIGURATION1_W		0x09
-#define TMP432_CONVERSION_RATE_W	0x0a
-#define TMP432_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP432_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP432_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP432_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP432_ONESHOT			0x0f
-#define TMP432_REMOTE1_EXTD		0x10
-#define TMP432_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP432_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP432_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP432_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP432_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP432_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP432_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP432_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP432_REMOTE1_THERM_LIMIT	0x19
-#define TMP432_REMOTE2_THERM_LIMIT	0x1a
-#define TMP432_STATUS_FAULT		0x1b
-#define TMP432_CHANNEL_MASK		0x1f
-#define TMP432_LOCAL_THERM_LIMIT	0x20
-#define TMP432_THERM_HYSTERESIS		0x21
-#define TMP432_CONSECUTIVE_ALERT	0x22
-#define TMP432_REMOTE2			0x23
-#define TMP432_REMOTE2_EXTD		0x24
-#define TMP432_BETA_RANGE_CH1		0x25
-#define TMP432_BETA_RANGE_CH2		0x26
-#define TMP432_NFACTOR_REMOTE1		0x27
-#define TMP432_NFACTOR_REMOTE2		0x28
-#define TMP432_LOCAL_EXTD		0x29
-#define TMP432_STATUS_LIMIT_HIGH	0x35
-#define TMP432_STATUS_LIMIT_LOW		0x36
-#define TMP432_STATUS_THERM		0x37
-#define TMP432_LOCAL_HIGH_LIMIT_EXTD	0x3d
-#define TMP432_LOCAL_LOW_LIMIT_EXTD	0x3e
-#define TMP432_CONFIGURATION2_R		0x3f
-#define TMP432_CONFIGURATION2_W		0x3f
-#define TMP432_RESET_W			0xfc
-#define TMP432_DEVICE_ID		0xfd
-#define TMP432_MANUFACTURER_ID		0xfe
-
-/* Config register bits */
-#define TMP432_CONFIG1_TEMP_RANGE	BIT(2)
-/* TMP432_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP432_CONFIG1_MODE		BIT(5)
-#define TMP432_CONFIG1_RUN_L		BIT(6)
-#define TMP432_CONFIG1_ALERT_MASK_L	BIT(7)
-#define TMP432_CONFIG2_RESISTANCE_CORRECTION	BIT(2)
-#define TMP432_CONFIG2_LOCAL_ENABLE	BIT(3)
-#define TMP432_CONFIG2_REMOTE1_ENABLE	BIT(4)
-#define TMP432_CONFIG2_REMOTE2_ENABLE	BIT(5)
-
-/* Status register bits */
-#define TMP432_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP432_STATUS_OPEN		BIT(2)
-#define TMP432_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP432_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP432_STATUS_BUSY		BIT(7)
-
-/* Limintaions */
-#define TMP432_HYSTERESIS_HIGH_LIMIT	255
-#define TMP432_HYSTERESIS_LOW_LIMIT	0
-
-enum tmp432_power_state {
-	TMP432_POWER_OFF = 0,
-	TMP432_POWER_ON,
-	TMP432_POWER_COUNT
-};
-
-enum tmp432_channel_id {
-	TMP432_CHANNEL_LOCAL,
-	TMP432_CHANNEL_REMOTE1,
-	TMP432_CHANNEL_REMOTE2,
-
-	TMP432_CHANNEL_COUNT
-};
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp432_get_val(int idx, int *temp_ptr);
-
-/**
- * Power control function of tmp432 temperature sensor.
- *
- * @param power_on	TMP432_POWER_ON: turn tmp432 sensor on.
- *			TMP432_POWER_OFF: shut tmp432 sensor down.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp432_set_power(enum tmp432_power_state power_on);
-
-/*
- * Set TMP432 ALERT#/THERM2# pin to THERM mode, and give a limit
- * for a specific channel.
- *
- * @param channel	specific a channel
- *
- * @param limit_c	High limit temperature, default: 85C
- *
- * @param hysteresis	Hysteresis temperature, default: 10C
- *			All channels share the same hysteresis
- *
- * In THERM mode, ALERT# pin will trigger(Low) by itself when any
- * channel's temperature is greater( >= )than channel's limit_c,
- * and release(High) by itself when channel's temperature is lower
- * than (limit_c - hysteresis)
- */
-int tmp432_set_therm_limit(int channel, int limit_c, int hysteresis);
-#endif /* __CROS_EC_TMP432_H */
diff --git a/driver/temp_sensor/tmp468.c b/driver/temp_sensor/tmp468.c
deleted file mode 100644
index 46e77ca696..0000000000
--- a/driver/temp_sensor/tmp468.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP468 temperature sensor module for Chrome EC */
-
-#include "common.h"
-#include "console.h"
-#include "tmp432.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "hooks.h"
-#include "util.h"
-
-#include "tmp468.h"
-
-
-static int fake_temp[TMP468_CHANNEL_COUNT] = {-1, -1, -1, -1, -1, -1, -1 , -1, -1};
-static int temp_val[TMP468_CHANNEL_COUNT]  = {0, 0, 0, 0, 0, 0, 0 , 0, 0};
-static uint8_t is_sensor_shutdown;
-
-static int has_power(void)
-{
-	return !is_sensor_shutdown;
-}
-
-static int raw_read16(const int offset, int *data_ptr)
-{
-	return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			  offset, data_ptr);
-}
-
-static int raw_write16(const int offset, int data_ptr)
-{
-	return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			   offset, data_ptr);
-}
-
-static int tmp468_shutdown(uint8_t want_shutdown)
-{
-	int ret, value;
-
-	if (want_shutdown == is_sensor_shutdown)
-		return EC_SUCCESS;
-
-	ret = raw_read16(TMP468_CONFIGURATION, &value);
-	if (ret < 0) {
-		ccprintf("ERROR: Temp sensor I2C read16 error.\n");
-		return ret;
-	}
-
-	if (want_shutdown)
-		value |= TMP468_SHUTDOWN;
-	else
-		value &= ~TMP468_SHUTDOWN;
-
-	ret = raw_write16(TMP468_CONFIGURATION, value);
-	if (ret == EC_SUCCESS)
-		is_sensor_shutdown = want_shutdown;
-
-	return EC_SUCCESS;
-}
-
-int tmp468_get_val(int idx, int *temp_ptr)
-{
-	if(!has_power())
-		return EC_ERROR_NOT_POWERED;
-
-	if (idx < TMP468_CHANNEL_COUNT) {
-		*temp_ptr = C_TO_K(temp_val[idx]);
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_INVAL;
-}
-
-static void temp_sensor_poll(void)
-{
-	int i, ret;
-
-	if (!has_power())
-		return;
-
-	for (i = 0; i < TMP468_CHANNEL_COUNT; i++)
-		if (fake_temp[i] != -1) {
-			temp_val[i] = fake_temp[i];
-		} else {
-			ret = raw_read16(TMP468_LOCAL + i, &temp_val[i]);
-			if (ret < 0)
-				return;
-			temp_val[i] >>= TMP468_SHIFT1;
-		}
-}
-DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
-
-int tmp468_set_power(enum tmp468_power_state power_on)
-{
-	uint8_t shutdown = (power_on == TMP468_POWER_OFF) ? 1 : 0;
-	return tmp468_shutdown(shutdown);
-}
diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h
deleted file mode 100644
index 59fbd20477..0000000000
--- a/driver/temp_sensor/tmp468.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TMP468 temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TMP468_H
-#define __CROS_EC_TMP468_H
-
-#define TMP468_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
-#define TMP468_SHIFT1 7
-
-#define TMP468_LOCAL			0x00
-#define TMP468_REMOTE1			0x01
-#define TMP468_REMOTE2			0x02
-#define TMP468_REMOTE3			0x03
-#define TMP468_REMOTE4			0x04
-#define TMP468_REMOTE5			0x05
-#define TMP468_REMOTE6			0x06
-#define TMP468_REMOTE7			0x07
-#define TMP468_REMOTE8			0x08
-
-#define TMP468_SRST			0x20
-#define TMP468_THERM			0x21
-#define TMP468_THERM2			0x22
-#define TMP468_ROPEN			0x23
-
-#define TMP468_CONFIGURATION		0x30
-#define TMP468_THERM_HYST		0x38
-
-#define TMP468_LOCAL_LOW_LIMIT		0x39
-#define TMP468_LOCAL_HIGH_LIMT		0x3a
-
-#define TMP468_REMOTE1_OFFSET		0x40
-#define TMP468_REMOTE1_NFACTOR		0x41
-#define TMP468_REMOTE1_LOW_LIMIT	0x41
-#define TMP468_REMOTE1_HIGH_LIMIT	0x42
-
-#define TMP468_REMOTE2_OFFSET		0x48
-#define TMP468_REMOTE2_NFACTOR		0x49
-#define TMP468_REMOTE2_LOW_LIMIT	0x4a
-#define TMP468_REMOTE2_HIGH_LIMIT	0x4b
-
-#define TMP468_REMOTE3_OFFSET		0x50
-#define TMP468_REMOTE3_NFACTOR		0x51
-#define TMP468_REMOTE3_LOW_LIMIT	0x52
-#define TMP468_REMOTE3_HIGH_LIMIT	0x53
-
-#define TMP468_REMOTE4_OFFSET		0x58
-#define TMP468_REMOTE4_NFACTOR		0x59
-#define TMP468_REMOTE4_LOW_LIMIT	0x59
-#define TMP468_REMOTE4_HIGH_LIMIT	0x5a
-
-#define TMP468_REMOTE5_OFFSET		0x60
-#define TMP468_REMOTE5_NFACTOR		0x61
-#define TMP468_REMOTE5_LOW_LIMIT	0x62
-#define TMP468_REMOTE5_HIGH_LIMIT	0x63
-
-#define TMP468_REMOTE6_OFFSET		0x68
-#define TMP468_REMOTE6_NFACTOR		0x69
-#define TMP468_REMOTE6_LOW_LIMIT	0x6a
-#define TMP468_REMOTE6_HIGH_LIMIT	0x6b
-
-#define TMP468_REMOTE7_OFFSET		0x70
-#define TMP468_REMOTE7_NFACTOR		0x71
-#define TMP468_REMOTE7_LOW_LIMIT	0x72
-#define TMP468_REMOTE7_HIGH_LIMIT	0x73
-
-#define TMP468_REMOTE8_OFFSET		0x78
-#define TMP468_REMOTE8_NFACTOR		0x79
-#define TMP468_REMOTE8_LOW_LIMIT	0x7a
-#define TMP468_REMOTE8_HIGH_LIMIT	0x7b
-
-#define TMP468_LOCK			0xc4
-
-#define TMP468_DEVICE_ID		0xfd
-#define TMP468_MANUFACTURER_ID		0xfe
-
-#define TMP468_SHUTDOWN			BIT(5)
-
-enum tmp468_channel_id {
-	TMP468_CHANNEL_LOCAL,
-
-	TMP468_CHANNEL_REMOTE1,
-	TMP468_CHANNEL_REMOTE2,
-	TMP468_CHANNEL_REMOTE3,
-	TMP468_CHANNEL_REMOTE4,
-	TMP468_CHANNEL_REMOTE5,
-	TMP468_CHANNEL_REMOTE6,
-	TMP468_CHANNEL_REMOTE7,
-	TMP468_CHANNEL_REMOTE8,
-
-	TMP468_CHANNEL_COUNT
-};
-
-enum tmp468_power_state {
-	TMP468_POWER_OFF = 0,
-	TMP468_POWER_ON,
-
-	TMP468_POWER_COUNT
-};
-
-
-/**
- * Get the last polled value of a sensor.
- *
- * @param idx		Index to read. Idx indicates whether to read die
- *			temperature or external temperature.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp468_get_val(int idx, int *temp_ptr);
-
-/**
- * Power control function of tmp432 temperature sensor.
- *
- * @param power_on	TMP468_POWER_ON: turn tmp468 sensor on.
- *			TMP468_POWER_OFF: shut tmp468 sensor down.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int tmp468_set_power(enum tmp468_power_state power_on);
-
-#endif /* __CROS_EC_TMP468_H */
diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c
deleted file mode 100644
index 6df4f0f7de..0000000000
--- a/driver/touchpad_elan.c
+++ /dev/null
@@ -1,847 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "byteorder.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "math_util.h"
-#include "sha256.h"
-#include "shared_mem.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "touchpad.h"
-#include "update_fw.h"
-#include "util.h"
-#include "usb_api.h"
-#include "usb_hid_touchpad.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
-
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
-
-/******************************************************************************/
-/* How to talk to the controller */
-/******************************************************************************/
-
-#define ELAN_VENDOR_ID			0x04f3
-
-#define ETP_I2C_RESET			0x0100
-#define ETP_I2C_WAKE_UP			0x0800
-#define ETP_I2C_SLEEP			0x0801
-
-#define ETP_I2C_STAND_CMD		0x0005
-#define ETP_I2C_UNIQUEID_CMD		0x0101
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
-#define ETP_I2C_XY_TRACENUM_CMD		0x0105
-#define ETP_I2C_MAX_X_AXIS_CMD		0x0106
-#define ETP_I2C_MAX_Y_AXIS_CMD		0x0107
-#define ETP_I2C_RESOLUTION_CMD		0x0108
-#define ETP_I2C_IAP_VERSION_CMD		0x0110
-#define ETP_I2C_PRESSURE_CMD		0x010A
-#define ETP_I2C_SET_CMD			0x0300
-#define ETP_I2C_IAP_TYPE_CMD		0x0304
-#define ETP_I2C_POWER_CMD		0x0307
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
-
-#define ETP_ENABLE_ABS		0x0001
-
-#define ETP_DISABLE_POWER	0x0001
-
-#define ETP_I2C_REPORT_LEN	34
-
-#define ETP_MAX_FINGERS		5
-#define ETP_FINGER_DATA_LEN	5
-
-#define ETP_PRESSURE_OFFSET	25
-#define ETP_FWIDTH_REDUCE	90
-
-#define ETP_REPORT_ID		0x5D
-#define ETP_REPORT_ID_OFFSET	2
-#define ETP_TOUCH_INFO_OFFSET	3
-#define ETP_FINGER_DATA_OFFSET	4
-#define ETP_HOVER_INFO_OFFSET	30
-#define ETP_MAX_REPORT_LEN	34
-
-#define ETP_IAP_START_ADDR		0x0083
-
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		BIT(9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
-
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
-
-#define ETP_FW_IAP_PAGE_ERR		BIT(5)
-#define ETP_FW_IAP_INTF_ERR		BIT(4)
-
-#ifdef CONFIG_USB_UPDATE
-/* The actual FW_SIZE depends on IC. */
-#define FW_SIZE			CONFIG_TOUCHPAD_VIRTUAL_SIZE
-#endif
-
-struct {
-	/* Max X/Y position */
-	uint16_t max_x;
-	uint16_t max_y;
-	/* Scaling factor for finger width/height */
-	uint16_t width_x;
-	uint16_t width_y;
-	/* Pressure adjustment */
-	uint8_t pressure_adj;
-	uint16_t ic_type;
-	uint16_t page_count;
-	uint16_t page_size;
-	uint16_t iap_version;
-} elan_tp_params;
-
-/*
- * Report a more reasonable pressure value, so that no adjustment is necessary
- * on Chrome OS side. 3216/1024 ~= 3.1416.
- */
-const int pressure_mult = 3216;
-const int pressure_div = 1024;
-
-static int elan_tp_read_cmd(uint16_t reg, uint16_t *val)
-{
-	uint8_t buf[2];
-
-	buf[0] = reg;
-	buf[1] = reg >> 8;
-
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), (uint8_t *)val, sizeof(*val));
-}
-
-static int elan_tp_write_cmd(uint16_t reg, uint16_t val)
-{
-	uint8_t buf[4];
-
-	buf[0] = reg;
-	buf[1] = reg >> 8;
-	buf[2] = val;
-	buf[3] = val >> 8;
-
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), NULL, 0);
-}
-
-/* Power is on by default. */
-static int elan_tp_power = 1;
-
-static int elan_tp_set_power(int enable)
-{
-	int rv;
-	uint16_t val;
-
-	if ((enable && elan_tp_power) || (!enable && !elan_tp_power))
-		return EC_SUCCESS;
-
-	CPRINTS("elan TP power %s", enable ? "on" : "off");
-
-	rv = elan_tp_read_cmd(ETP_I2C_POWER_CMD, &val);
-	if (rv)
-		goto out;
-
-	if (enable)
-		val &= ~ETP_DISABLE_POWER;
-	else
-		val |= ETP_DISABLE_POWER;
-
-	rv = elan_tp_write_cmd(ETP_I2C_POWER_CMD, val);
-
-	elan_tp_power = enable;
-out:
-	return rv;
-}
-
-static int finger_status[ETP_MAX_FINGERS] = {0};
-
-/*
- * Timestamp of last interrupt (32 bits are enough as we divide the value by 100
- * and then put it in a 16-bit field).
- */
-static uint32_t irq_ts;
-
-/*
- * Read touchpad report.
- * Returns 0 on success, positive (EC_RES_*) value on I2C error, and a negative
- * value if the I2C transaction is successful but the data is invalid (fairly
- * common).
- */
-static int elan_tp_read_report(void)
-{
-	int rv;
-	uint8_t tp_buf[ETP_I2C_REPORT_LEN];
-	int i, ri;
-	uint8_t touch_info;
-	uint8_t hover_info;
-	uint8_t *finger = tp_buf+ETP_FINGER_DATA_OFFSET;
-	struct usb_hid_touchpad_report report;
-	uint16_t timestamp;
-
-	/* Compute and save timestamp early in case another interrupt comes. */
-	timestamp = irq_ts / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-		      NULL, 0, tp_buf, ETP_I2C_REPORT_LEN);
-
-	if (rv) {
-		CPRINTS("read report error (%d)", rv);
-		return rv;
-	}
-
-	if (tp_buf[ETP_REPORT_ID_OFFSET] != ETP_REPORT_ID) {
-		CPRINTS("Invalid report id (%x)", tp_buf[ETP_REPORT_ID_OFFSET]);
-		return -1;
-	}
-
-	memset(&report, 0, sizeof(report));
-	report.id = 0x01;
-	ri = 0; /* Next finger index in HID report */
-
-	touch_info = tp_buf[ETP_TOUCH_INFO_OFFSET];
-	hover_info = tp_buf[ETP_HOVER_INFO_OFFSET];
-
-	for (i = 0; i < ETP_MAX_FINGERS; i++) {
-		int valid = touch_info & (1 << (3+i));
-
-		if (valid) {
-			int width = finger[3] & 0x0f;
-			int height = (finger[3] & 0xf0) >> 4;
-			int pressure = finger[4] + elan_tp_params.pressure_adj;
-			pressure = DIV_ROUND_NEAREST(pressure * pressure_mult,
-						pressure_div);
-
-			width = MIN(4095, width * elan_tp_params.width_x);
-			height = MIN(4095, height * elan_tp_params.width_y);
-			pressure = MIN(1023, pressure);
-
-			report.finger[ri].confidence = 1;
-			report.finger[ri].tip = 1;
-			report.finger[ri].inrange = 1;
-			report.finger[ri].id = i;
-			report.finger[ri].width = width;
-			report.finger[ri].height = height;
-			report.finger[ri].x =
-				((finger[0] & 0xf0) << 4) | finger[1];
-			report.finger[ri].y =
-				elan_tp_params.max_y -
-				(((finger[0] & 0x0f) << 8) | finger[2]);
-			report.finger[ri].pressure = pressure;
-			finger += ETP_FINGER_DATA_LEN;
-			ri++;
-			finger_status[i] = 1;
-		} else if (finger_status[i]) {
-			report.finger[ri].id = i;
-			/* When a finger is leaving, it's not a plam */
-			report.finger[ri].confidence = 1;
-			ri++;
-			finger_status[i] = 0;
-		}
-	}
-
-	report.count = ri;
-	report.timestamp = timestamp;
-
-	if (touch_info & 0x01) {
-		/* Do not report zero-finger click events */
-		if (report.count > 0)
-			report.button = 1;
-	}
-
-	if (hover_info & 0x40) {
-		/* TODO(b/35582031): Report hover event */
-		CPRINTF("[TP] hover!\n");
-	}
-
-	set_touchpad_report(&report);
-
-	return 0;
-}
-
-static void elan_get_fwinfo(void)
-{
-	uint16_t ic_type = elan_tp_params.ic_type;
-	uint16_t iap_version = elan_tp_params.iap_version;
-
-	switch (ic_type) {
-	case 0x09:
-		elan_tp_params.page_count = 768;
-		break;
-	case 0x0D:
-		elan_tp_params.page_count = 896;
-		break;
-	case 0x00:
-	case 0x10:
-	case 0x14:
-	case 0x15:
-		elan_tp_params.page_count = 1024;
-		break;
-	default:
-		elan_tp_params.page_count = -1;
-		CPRINTS("unknown ic_type: %d", ic_type);
-	}
-
-	if ((ic_type == 0x14 || ic_type == 0x15) && iap_version >= 2) {
-		elan_tp_params.page_count /= 8;
-		elan_tp_params.page_size = 512;
-	} else if (ic_type >= 0x0D && iap_version >= 1) {
-		elan_tp_params.page_count /= 2;
-		elan_tp_params.page_size = 128;
-	} else {
-		elan_tp_params.page_size = 64;
-	}
-}
-
-/*
- * - dpi == logical dimension / physical dimension (inches)
- *   (254 tenths of mm per inch)
- */
-__maybe_unused static int calc_physical_dimension(int dpi, int logical_dim)
-{
-	return round_divide(254 * logical_dim, dpi);
-}
-
-/* Initialize the controller ICs after reset */
-static void elan_tp_init(void)
-{
-	int rv;
-	uint8_t val[2];
-	int dpi_x, dpi_y;
-
-	CPRINTS("%s", __func__);
-
-	elan_tp_write_cmd(ETP_I2C_STAND_CMD, ETP_I2C_RESET);
-	msleep(100);
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-		      NULL, 0, val, sizeof(val));
-
-	CPRINTS("reset rv %d buf=%04x", rv, *((uint16_t *)val));
-	if (rv)
-		goto out;
-
-	/* Read IC type, IAP version */
-	rv = elan_tp_read_cmd(ETP_I2C_OSM_VERSION_CMD, &elan_tp_params.ic_type);
-	CPRINTS("%s: ic_type:%04X.", __func__, elan_tp_params.ic_type);
-	elan_tp_params.ic_type >>= 8;
-	if (rv)
-		goto out;
-
-	rv = elan_tp_read_cmd(ETP_I2C_IAP_VERSION_CMD,
-			&elan_tp_params.iap_version);
-	CPRINTS("%s: iap_version:%04X.", __func__, elan_tp_params.iap_version);
-	elan_tp_params.iap_version >>= 8;
-	if (rv)
-		goto out;
-
-	elan_get_fwinfo();
-
-	/* Read min/max */
-	rv = elan_tp_read_cmd(ETP_I2C_MAX_X_AXIS_CMD, &elan_tp_params.max_x);
-	if (rv)
-		goto out;
-	rv = elan_tp_read_cmd(ETP_I2C_MAX_Y_AXIS_CMD, &elan_tp_params.max_y);
-	if (rv)
-		goto out;
-
-	/* Read min/max */
-	rv = elan_tp_read_cmd(ETP_I2C_XY_TRACENUM_CMD, (uint16_t *)val);
-	if (rv)
-		goto out;
-	if (val[0] == 0 || val[1] == 0) {
-		CPRINTS("Invalid XY_TRACENUM");
-		goto out;
-	}
-
-	/* ETP_FWIDTH_REDUCE reduces the apparent width to avoid treating large
-	 * finger as palm. Multiply value by 2 as HID multitouch divides it.
-	 */
-	elan_tp_params.width_x =
-		2 * ((elan_tp_params.max_x / val[0]) - ETP_FWIDTH_REDUCE);
-	elan_tp_params.width_y =
-		2 * ((elan_tp_params.max_y / val[1]) - ETP_FWIDTH_REDUCE);
-
-	rv = elan_tp_read_cmd(ETP_I2C_PRESSURE_CMD, (uint16_t *)val);
-	if (rv)
-		goto out;
-	elan_tp_params.pressure_adj = (val[0] & 0x10) ? 0 : ETP_PRESSURE_OFFSET;
-
-	rv = elan_tp_read_cmd(ETP_I2C_RESOLUTION_CMD, (uint16_t *)val);
-	if (rv)
-		goto out;
-
-	dpi_x = 10*val[0] + 790;
-	dpi_y = 10*val[1] + 790;
-
-	CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d",
-		elan_tp_params.max_x, elan_tp_params.max_y,
-		elan_tp_params.width_x, elan_tp_params.width_y,
-		elan_tp_params.pressure_adj, dpi_x, dpi_y);
-
-#ifdef CONFIG_USB_HID_TOUCHPAD
-	/* Validity check dimensions provided at build time. */
-	if (elan_tp_params.max_x != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X ||
-	    elan_tp_params.max_y != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y ||
-	    calc_physical_dimension(dpi_x, elan_tp_params.max_x) !=
-			CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X ||
-	    calc_physical_dimension(dpi_y, elan_tp_params.max_y) !=
-			CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) {
-		CPRINTS("*** TP mismatch!");
-	}
-#endif
-
-	/* Switch to absolute mode */
-	rv = elan_tp_write_cmd(ETP_I2C_SET_CMD, ETP_ENABLE_ABS);
-	if (rv)
-		goto out;
-
-	/* Sleep control off */
-	rv = elan_tp_write_cmd(ETP_I2C_STAND_CMD, ETP_I2C_WAKE_UP);
-
-	/* Enable interrupt to fetch reports */
-	gpio_enable_interrupt(GPIO_TOUCHPAD_INT);
-
-out:
-	CPRINTS("%s:%d", __func__, rv);
-
-	return;
-}
-DECLARE_DEFERRED(elan_tp_init);
-
-#ifdef CONFIG_USB_UPDATE
-int touchpad_get_info(struct touchpad_info *tp)
-{
-	int rv;
-	uint16_t val;
-
-	tp->status = EC_RES_SUCCESS;
-	tp->vendor = ELAN_VENDOR_ID;
-
-	/* Get unique ID, FW, SM version. */
-	rv = elan_tp_read_cmd(ETP_I2C_UNIQUEID_CMD, &val);
-	if (rv)
-		return -1;
-	tp->elan.id = val;
-
-	rv = elan_tp_read_cmd(ETP_I2C_FW_VERSION_CMD, &val);
-	if (rv)
-		return -1;
-	tp->elan.fw_version = val & 0xff;
-
-	rv = elan_tp_read_cmd(ETP_I2C_FW_CHECKSUM_CMD, &val);
-	if (rv)
-		return -1;
-	tp->elan.fw_checksum = val;
-
-	return sizeof(*tp);
-}
-
-static int elan_in_main_mode(void)
-{
-	uint16_t val;
-
-	elan_tp_read_cmd(ETP_I2C_IAP_CTRL_CMD, &val);
-	return val & ETP_I2C_MAIN_MODE_ON;
-}
-
-static int elan_read_write_iap_type(void)
-{
-	for (int retry = 0; retry < 3; ++retry) {
-		uint16_t val;
-
-		if (elan_tp_write_cmd(ETP_I2C_IAP_TYPE_CMD,
-					elan_tp_params.page_size / 2))
-			return EC_ERROR_UNKNOWN;
-
-		if (elan_tp_read_cmd(ETP_I2C_IAP_TYPE_CMD, &val))
-			return EC_ERROR_UNKNOWN;
-
-		if (val == elan_tp_params.page_size / 2)
-			return EC_SUCCESS;
-
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-static int elan_prepare_for_update(void)
-{
-	uint16_t rx_buf;
-	int initial_mode;
-
-	initial_mode = elan_in_main_mode();
-	if (!initial_mode) {
-		CPRINTS("%s: In IAP mode, reset IC.", __func__);
-		elan_tp_write_cmd(ETP_I2C_IAP_RESET_CMD, ETP_I2C_IAP_RESET);
-		msleep(30);
-	}
-	/* Send the passphrase */
-	elan_tp_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
-	msleep(initial_mode ? 100 : 30);
-
-	/* We should be in the IAP mode now */
-	if (elan_in_main_mode()) {
-		CPRINTS("%s: Failure to enter IAP mode.", __func__);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (elan_tp_params.ic_type >= 0x0D && elan_tp_params.iap_version >= 1) {
-		if (elan_read_write_iap_type())
-			return EC_ERROR_UNKNOWN;
-	}
-
-	/* Send the passphrase again */
-	elan_tp_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
-	msleep(30);
-
-	/* Verify the password */
-	if (elan_tp_read_cmd(ETP_I2C_IAP_CMD, &rx_buf)) {
-		CPRINTS("%s: Cannot read IAP password.", __func__);
-		return EC_ERROR_UNKNOWN;
-	}
-	if (rx_buf != ETP_I2C_IAP_PASSWORD) {
-		CPRINTS("%s: Got an unexpected IAP password %0x4x.", __func__,
-			rx_buf);
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-static int touchpad_update_page(const uint8_t *data)
-{
-	const uint8_t cmd[2] = {ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H};
-	uint16_t checksum = 0;
-	uint16_t rx_buf;
-	int i, rv;
-
-	for (i = 0; i < elan_tp_params.page_size; i += 2)
-		checksum += ((uint16_t)(data[i + 1]) << 8) | (data[i]);
-	checksum = htole16(checksum);
-
-	i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 1);
-
-	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
-			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			       cmd, sizeof(cmd), NULL, 0, I2C_XFER_START);
-	if (rv)
-		goto fail;
-	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
-			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			       data, elan_tp_params.page_size, NULL, 0, 0);
-	if (rv)
-		goto fail;
-	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
-			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			       (uint8_t *)&checksum, sizeof(checksum), NULL, 0,
-			       I2C_XFER_STOP);
-	if (rv)
-		goto fail;
-
-fail:
-	i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 0);
-	if (rv)
-		return rv;
-	msleep(elan_tp_params.page_size >= 512 ? 50 : 35);
-
-	rv = elan_tp_read_cmd(ETP_I2C_IAP_CTRL_CMD, &rx_buf);
-
-	if (rv || (rx_buf & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR))) {
-		CPRINTS("%s: IAP reports failed write : %x.",
-			__func__, rx_buf);
-		return EC_ERROR_UNKNOWN;
-	}
-	return 0;
-}
-
-int touchpad_update_write(int offset, int size, const uint8_t *data)
-{
-	static int iap_addr = -1;
-	int addr, rv;
-
-	CPRINTS("%s %08x %d", __func__, offset, size);
-
-	if (offset == 0) {
-		/* Verify the IC type is aligned with defined firmware size */
-		if (elan_tp_params.page_size * elan_tp_params.page_count
-				!= FW_SIZE) {
-			CPRINTS("%s: IC(%d*%d) size and FW_SIZE(%d) mismatch",
-				__func__, elan_tp_params.page_count,
-				elan_tp_params.page_size, FW_SIZE);
-			return EC_ERROR_UNKNOWN;
-		}
-
-		gpio_disable_interrupt(GPIO_TOUCHPAD_INT);
-		CPRINTS("%s: prepare fw update.", __func__);
-		rv = elan_prepare_for_update();
-		if (rv)
-			return rv;
-		iap_addr = 0;
-	}
-
-	if (offset <= (ETP_IAP_START_ADDR * 2) &&
-	    (ETP_IAP_START_ADDR * 2) < (offset + size)) {
-		iap_addr = ((data[ETP_IAP_START_ADDR * 2 - offset + 1] << 8) |
-			data[ETP_IAP_START_ADDR * 2 - offset]) << 1;
-		CPRINTS("%s: payload starts from 0x%x.", __func__, iap_addr);
-	}
-
-	/* Data that comes in must align with page_size */
-	if (offset % elan_tp_params.page_size)
-		return EC_ERROR_INVAL;
-
-	for (addr = offset; addr < (offset + size);
-			addr += elan_tp_params.page_size) {
-		if (iap_addr > addr) /* Skip chunk */
-			continue;
-		rv = touchpad_update_page(data + addr - offset);
-		if (rv)
-			return rv;
-		CPRINTF("/p%d", addr / elan_tp_params.page_size);
-		watchdog_reload();
-	}
-	CPRINTF("\n");
-
-	if (offset + size == FW_SIZE) {
-		CPRINTS("%s: End update, wait for reset.", __func__);
-		hook_call_deferred(&elan_tp_init_data, 600 * MSEC);
-	}
-	return EC_SUCCESS;
-}
-
-/* Debugging mode. */
-
-/* Allowed debug commands. We only store a hash of the allowed commands. */
-#define TOUCHPAD_ELAN_DEBUG_CMD_LENGTH 50
-#define TOUCHPAD_ELAN_DEBUG_NUM_CMD 2
-
-static const uint8_t
-allowed_command_hashes[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = {
-	{
-		0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c,
-		0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3,
-		0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b,
-		0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48
-	},
-	{
-		0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76,
-		0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9,
-		0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d,
-		0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74
-	},
-};
-
-/* Debugging commands need to allocate a <=1k buffer. */
-SHARED_MEM_CHECK_SIZE(1024);
-
-int touchpad_debug(const uint8_t *param, unsigned int param_size,
-		   uint8_t **data, unsigned int *data_size)
-{
-	static uint8_t *buffer;
-	static unsigned int buffer_size;
-	unsigned int offset;
-
-	/* Offset parameter is 1 byte. */
-	if (param_size < 1)
-		return EC_RES_INVALID_PARAM;
-
-	/*
-	 * Debug command, compute SHA-256, check that it matches allowed hashes,
-	 * and execute I2C command.
-	 *
-	 * param[0] must be 0xff
-	 * param[1] is the offset of the command in the data
-	 * param[2] is the command length
-	 * param[3-4] is the read-back length (MSB first), can be 0
-	 * param[5-49] is verified using SHA-256 hash.
-	 */
-	if (param[0] == 0xff && param_size == TOUCHPAD_ELAN_DEBUG_CMD_LENGTH) {
-		struct sha256_ctx ctx;
-		uint8_t *command_hash;
-		unsigned int offset = param[1];
-		unsigned int write_length = param[2];
-		unsigned int read_length =
-			((unsigned int)param[3] << 8) | param[4];
-		int i;
-		int match;
-		int rv;
-
-		if (offset < 5 || write_length == 0 ||
-		    (offset + write_length) >= TOUCHPAD_ELAN_DEBUG_CMD_LENGTH)
-			return EC_RES_INVALID_PARAM;
-
-		SHA256_init(&ctx);
-		SHA256_update(&ctx, param+5, TOUCHPAD_ELAN_DEBUG_CMD_LENGTH-5);
-		command_hash = SHA256_final(&ctx);
-
-		match = 0;
-		for (i = 0; i < TOUCHPAD_ELAN_DEBUG_NUM_CMD; i++) {
-			if (!memcmp(command_hash, allowed_command_hashes[i],
-					sizeof(allowed_command_hashes[i]))) {
-				match = 1;
-				break;
-			}
-		}
-
-		if (!match)
-			return EC_RES_INVALID_PARAM;
-
-		if (buffer) {
-			shared_mem_release(buffer);
-			buffer = NULL;
-		}
-
-		buffer_size = read_length;
-
-		if (read_length > 0) {
-			if (shared_mem_acquire(buffer_size,
-				    (char **)&buffer) != EC_SUCCESS) {
-				buffer = NULL;
-				buffer_size = 0;
-				return EC_RES_BUSY;
-			}
-
-			memset(buffer, 0, buffer_size);
-		}
-
-		rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			      &param[offset], write_length,
-			      buffer, read_length);
-
-		if (rv)
-			return EC_RES_BUS_ERROR;
-
-		return EC_RES_SUCCESS;
-	}
-
-	/*
-	 * Data request: Retrieve previously read data from buffer, in blocks of
-	 * 64 bytes.
-	 */
-	offset = param[0] * 64;
-
-	if (!buffer)
-		return EC_RES_UNAVAILABLE;
-
-	if (offset >= buffer_size) {
-		shared_mem_release(buffer);
-		buffer = NULL;
-		*data = NULL;
-		*data_size = 0;
-		return EC_RES_OVERFLOW;
-	}
-
-	*data = buffer + offset;
-	*data_size = MIN(64, buffer_size - offset);
-
-	return EC_RES_SUCCESS;
-}
-#endif
-
-/*
- * Try to read touchpad report up to 3 times, reset the touchpad if we still
- * fail.
- */
-void elan_tp_read_report_retry(void)
-{
-	int ret;
-	int retry = 3;
-
-	while (retry--) {
-		ret = elan_tp_read_report();
-
-		if (ret <= 0)
-			return;
-
-		/* Try again */
-		msleep(1);
-	}
-
-	/* Failed to read data, reset the touchpad. */
-	CPRINTF("Resetting TP.\n");
-	board_touchpad_reset();
-	elan_tp_init();
-}
-
-void touchpad_interrupt(enum gpio_signal signal)
-{
-	irq_ts = __hw_clock_source_read();
-
-	task_wake(TASK_ID_TOUCHPAD);
-}
-
-/* Make a decision on touchpad power, based on USB and tablet mode status. */
-static void touchpad_power_control(void)
-{
-	static int enabled = 1;
-	int enable = 1;
-
-#ifdef CONFIG_USB_SUSPEND
-	enable = enable &&
-		(!usb_is_suspended() || usb_is_remote_wakeup_enabled());
-#endif
-
-#ifdef CONFIG_TABLET_MODE
-	enable = enable && !tablet_get_mode();
-#endif
-
-	if (enabled == enable)
-		return;
-
-	elan_tp_set_power(enable);
-
-	enabled = enable;
-}
-
-void touchpad_task(void *u)
-{
-	uint32_t event;
-
-	elan_tp_init();
-	touchpad_power_control();
-
-	while (1) {
-		event = task_wait_event(-1);
-
-		if (event & TASK_EVENT_WAKE)
-			elan_tp_read_report_retry();
-
-		if (event & TASK_EVENT_POWER)
-			touchpad_power_control();
-	}
-}
-
-/*
- * When USB PM status changes, or tablet mode changes, call in the main task to
- * decide whether to turn touchpad on or off.
- */
-#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_TABLET_MODE)
-static void touchpad_power_change(void)
-{
-	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER);
-}
-#endif
-#ifdef CONFIG_USB_SUSPEND
-DECLARE_HOOK(HOOK_USB_PM_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
-#endif
-#ifdef CONFIG_TABLET_MODE
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
-#endif
diff --git a/driver/touchpad_gt7288.c b/driver/touchpad_gt7288.c
deleted file mode 100644
index ac05b88323..0000000000
--- a/driver/touchpad_gt7288.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "task.h"
-#include "touchpad_gt7288.h"
-#include "util.h"
-
-/* Define this to enable various warning messages during report parsing. */
-#undef DEBUG_CHECKS
-
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
-
-#define GT7288_I2C_ADDR_FLAGS 0x14
-
-#define GT7288_REPORT_ID_PTP 0x04
-
-#define GT7288_BUTTON_STATE_UP 0x80
-#define GT7288_BUTTON_STATE_DOWN 0x81
-
-#define GT7288_REG_HID_DESCRIPTOR 0x0001
-#define GT7288_REG_REPORT_DESCRIPTOR 0x0002
-
-#define GT7288_HID_DESCRIPTOR_LENGTH 0x1E
-#define GT7288_REPORT_DESCRIPTOR_LENGTH 0x1AE
-#define GT7288_REPORT_LENGTH 16
-
-/**
- * Reads a descriptor using the Conventional Read Mode.
- *
- * @param[in]  register_id The register containing the descriptor to read.
- * @param[out] data The data that is read.
- * @param[in]  max_length The maximum length of data.
- *
- * @return EC_SUCCESS or an error code.
- */
-static int gt7288_read_desc(uint16_t register_id, uint8_t *data,
-			    size_t max_length)
-{
-	uint8_t reg_bytes[] = {
-		register_id & 0xFF, (register_id & 0xFF00) >> 8
-	};
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS,
-			reg_bytes, sizeof(reg_bytes), data, max_length);
-}
-
-int gt7288_get_version_info(struct gt7288_version_info *info)
-{
-	uint8_t data[GT7288_HID_DESCRIPTOR_LENGTH];
-
-	RETURN_ERROR(gt7288_read_desc(GT7288_REG_HID_DESCRIPTOR, data,
-				      sizeof(data)));
-	info->product_id = UINT16_FROM_BYTE_ARRAY_LE(data, 22);
-	info->version_id = UINT16_FROM_BYTE_ARRAY_LE(data, 24);
-	return EC_SUCCESS;
-}
-
-static void gt7288_translate_contact(const uint8_t *data,
-				     struct gt7288_contact *contact)
-{
-	if (IS_ENABLED(DEBUG_CHECKS)) {
-		uint8_t report_id = data[2];
-
-		if (report_id != GT7288_REPORT_ID_PTP) {
-			CPRINTS("WARNING: unexpected report ID 0x%02X (expected 0x%02X).",
-				report_id, GT7288_REPORT_ID_PTP);
-		}
-	}
-
-	contact->id = data[3] >> 4;
-	/* Note: these bits appear to be in the wrong order in the programming
-	 * guide, verified by experimentation.
-	 */
-	contact->tip = (data[3] & BIT(1)) >> 1;
-	contact->confidence = data[3] & BIT(0);
-	contact->x = UINT16_FROM_BYTE_ARRAY_LE(data, 4);
-	contact->y = UINT16_FROM_BYTE_ARRAY_LE(data, 6);
-	contact->width = data[12];
-	contact->height = data[13];
-}
-
-static int gt7288_read(uint8_t *data, size_t max_length)
-{
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS,
-			NULL, 0, data, max_length);
-}
-
-int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
-{
-	size_t i;
-	uint8_t data[GT7288_REPORT_LENGTH];
-
-	RETURN_ERROR(gt7288_read(data, sizeof(data)));
-	report->timestamp = UINT16_FROM_BYTE_ARRAY_LE(data, 8);
-
-	if (data[10] > GT7288_MAX_CONTACTS) {
-		if (IS_ENABLED(DEBUG_CHECKS))
-			CPRINTS("ERROR: too many contacts (%d > %d).",
-				data[10], GT7288_MAX_CONTACTS);
-		return EC_ERROR_HW_INTERNAL;
-	}
-	report->num_contacts = data[10];
-
-	if (IS_ENABLED(DEBUG_CHECKS) && data[11] != GT7288_BUTTON_STATE_UP &&
-	    data[11] != GT7288_BUTTON_STATE_DOWN) {
-		CPRINTS("WARNING: unexpected button state 0x%02X (expected 0x%02X or 0x%02X).",
-			data[11], GT7288_BUTTON_STATE_UP,
-			GT7288_BUTTON_STATE_DOWN);
-	}
-	report->button_down = data[11] == GT7288_BUTTON_STATE_DOWN;
-
-	gt7288_translate_contact(data, &report->contacts[0]);
-
-	for (i = 1; i < report->num_contacts; i++) {
-		RETURN_ERROR(gt7288_read(data, sizeof(data)));
-		gt7288_translate_contact(data, &report->contacts[i]);
-	}
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_CMD_GT7288
-static int command_gt7288_read_desc(int argc, char **argv)
-{
-	uint16_t register_id;
-	long parsed_arg;
-	char *end;
-	int i;
-	uint8_t data[GT7288_HID_DESCRIPTOR_LENGTH];
-
-	if (argc != 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	parsed_arg = strtoi(argv[1], &end, 0);
-	if (parsed_arg < 0 || parsed_arg > UINT16_MAX || end == argv[1])
-		return EC_ERROR_PARAM1;
-	register_id = parsed_arg;
-
-	RETURN_ERROR(gt7288_read_desc(register_id, data, sizeof(data)));
-
-	ccprintf("Data: ");
-	for (i = 0; i < sizeof(data); i++)
-		ccprintf("%02X ", data[i]);
-	ccprintf("\n");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc,
-			"register",
-			"Read a descriptor on the GT7288");
-
-static int command_gt7288_read_report_descriptor(int argc, char **argv)
-{
-	int i;
-	uint8_t data[64];
-	size_t bytes_read = 0;
-
-	if (argc != 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	/* The report descriptor is bigger than the Maxim I2C code can handle in
-	 * one go, so we have to split it into chunks.
-	 */
-	RETURN_ERROR(gt7288_read_desc(GT7288_REG_REPORT_DESCRIPTOR, NULL, 0));
-	ccprintf("Report descriptor: ");
-	while (bytes_read < GT7288_REPORT_DESCRIPTOR_LENGTH) {
-		size_t bytes_to_read =
-			MIN(GT7288_REPORT_DESCRIPTOR_LENGTH - bytes_read,
-			    sizeof(data));
-		RETURN_ERROR(gt7288_read(data, bytes_to_read));
-
-		for (i = 0; i < sizeof(data); i++)
-			ccprintf("%02X ", data[i]);
-
-		bytes_read += bytes_to_read;
-	}
-	ccprintf("\n");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gt7288_repdesc, command_gt7288_read_report_descriptor,
-			"", "Read the report descriptor on the GT7288");
-
-static int command_gt7288_ver(int argc, char **argv)
-{
-	struct gt7288_version_info info;
-
-	if (argc != 1)
-		return EC_ERROR_PARAM_COUNT;
-
-	RETURN_ERROR(gt7288_get_version_info(&info));
-	ccprintf("Product ID: 0x%04X\n", info.product_id);
-	ccprintf("Version ID: 0x%04X\n", info.version_id);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gt7288_ver, command_gt7288_ver, "",
-			"Read version information from the GT7288");
-
-static int command_gt7288_report(int argc, char **argv)
-{
-	int i;
-	struct gt7288_ptp_report report;
-
-	RETURN_ERROR(gt7288_read_ptp_report(&report));
-	ccprintf("Timestamp %d, button %s, %d contacts\n", report.timestamp,
-		 report.button_down ? "down" : "up", report.num_contacts);
-	if (report.num_contacts == 0)
-		return EC_SUCCESS;
-
-	ccprintf("ID,    X,    Y, width, height, tip, confidence\n");
-	for (i = 0; i < report.num_contacts; i++) {
-		struct gt7288_contact *contact = &report.contacts[i];
-
-		ccprintf("%2d, %4d, %4d, %5d, %6d, %3d, %10d\n", contact->id,
-			 contact->x, contact->y, contact->width,
-			 contact->height, contact->tip, contact->confidence);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(gt7288_rep, command_gt7288_report, "",
-			"Read a report from the GT7288.");
-#endif /* CONFIG_CMD_GT7288 */
diff --git a/driver/touchpad_gt7288.h b/driver/touchpad_gt7288.h
deleted file mode 100644
index c89c586784..0000000000
--- a/driver/touchpad_gt7288.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Driver for the Goodix GT7288 touch controller. */
-
-#ifndef __CROS_EC_TOUCHPAD_GT7288_H
-#define __CROS_EC_TOUCHPAD_GT7288_H
-
-#include <stdbool.h>
-#include <stddef.h>
-
-/* The maximum number of contacts that can be reported at once. */
-#define GT7288_MAX_CONTACTS 5
-
-/**
- * Version information for the chip.
- */
-struct gt7288_version_info {
-	/** HID product ID (0x01F0 for touchpads, 0x01F1 for touchscreens). */
-	uint16_t product_id;
-	/**
-	 * The firmware version. For touchpads equipped with a fingerprint
-	 * sensor, the MSB will be 1.
-	 */
-	uint16_t version_id;
-};
-
-/**
- * Reads version information from the GT7288.
- *
- * @param[out] info The version information.
- *
- * @return EC_SUCCESS or an error code.
- */
-int gt7288_get_version_info(struct gt7288_version_info *info);
-
-/**
- * Data describing a single contact.
- */
-struct gt7288_contact {
-	/**
-	 * A 4-bit ID that uniquely identifies the contact during its lifecycle.
-	 */
-	uint8_t id;
-	/** The absolute X coordinate. */
-	uint16_t x;
-	/** The absolute Y coordinate. */
-	uint16_t y;
-	/** The width of the contact (with firmware version 4 or greater). */
-	uint8_t width;
-	/** The height of the contact (with firmware version 4 or greater). */
-	uint8_t height;
-	/** Whether the finger is touching the pad. (Currently always true.) */
-	bool tip;
-	/** Whether the touch is a finger (true) or palm (false). */
-	bool confidence;
-};
-
-/**
- * Data from a complete report in PTP mode.
- */
-struct gt7288_ptp_report {
-	/** A relative timestamp, in units of 100µs. */
-	uint16_t timestamp;
-	/** The number of contacts on the pad. */
-	size_t num_contacts;
-	/** Whether the button is pressed. */
-	bool button_down;
-	/** An array of structs describing the individual contacts. */
-	struct gt7288_contact contacts[GT7288_MAX_CONTACTS];
-};
-
-/**
- * Reads a complete report, when the GT7288 is in PTP mode.
- *
- * @param[out] report The report that is read.
- *
- * @return EC_SUCCESS or an error code.
- */
-int gt7288_read_ptp_report(struct gt7288_ptp_report *report);
-
-#endif /* __CROS_EC_TOUCHPAD_GT7288_H */
diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c
deleted file mode 100644
index 56633bad16..0000000000
--- a/driver/touchpad_st.c
+++ /dev/null
@@ -1,1895 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "atomic.h"
-#include "board.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hwtimer.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "tablet_mode.h"
-#include "timer.h"
-#include "touchpad.h"
-#include "touchpad_st.h"
-#include "update_fw.h"
-#include "usb_api.h"
-#include "usb_hid_touchpad.h"
-#include "usb_isochronous.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Console output macros */
-#define CC_TOUCHPAD CC_USB
-#define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
-
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_TP_UPDATED  TASK_EVENT_CUSTOM_BIT(1)
-
-#define SPI (&(spi_devices[SPI_ST_TP_DEVICE_ID]))
-
-BUILD_ASSERT(sizeof(struct st_tp_event_t) == 8);
-BUILD_ASSERT(BYTES_PER_PIXEL == 1);
-
-/* Function prototypes */
-static int st_tp_panel_init(int full);
-static int st_tp_read_all_events(int show_error);
-static int st_tp_read_host_buffer_header(void);
-static int st_tp_send_ack(void);
-static int st_tp_start_scan(void);
-static int st_tp_stop_scan(void);
-static int st_tp_update_system_state(int new_state, int mask);
-static void touchpad_power_control(void);
-
-/* Global variables */
-/*
- * Current system state, meaning of each bit is defined below.
- */
-static int system_state;
-
-#define SYSTEM_STATE_DEBUG_MODE		BIT(0)
-#define SYSTEM_STATE_ENABLE_HEAT_MAP	BIT(1)
-#define SYSTEM_STATE_ENABLE_DOME_SWITCH	BIT(2)
-#define SYSTEM_STATE_ACTIVE_MODE	BIT(3)
-#define SYSTEM_STATE_DOME_SWITCH_LEVEL	BIT(4)
-#define SYSTEM_STATE_READY		BIT(5)
-
-/*
- * Pending action for touchpad.
- */
-static int tp_control;
-
-#define TP_CONTROL_SHALL_HALT		BIT(0)
-#define TP_CONTROL_SHALL_RESET		BIT(1)
-#define TP_CONTROL_SHALL_INIT		BIT(2)
-#define TP_CONTROL_SHALL_INIT_FULL	BIT(3)
-#define TP_CONTROL_SHALL_DUMP_ERROR	BIT(4)
-#define TP_CONTROL_RESETTING		BIT(5)
-#define TP_CONTROL_INIT			BIT(6)
-#define TP_CONTROL_INIT_FULL		BIT(7)
-
-/*
- * Number of times we have reset the touchpad because of errors.
- */
-static int tp_reset_retry_count;
-
-#define MAX_TP_RESET_RETRY_COUNT 3
-
-static int dump_memory_on_error;
-
-/*
- * Bitmap to track if a finger exists.
- */
-static int touch_slot;
-
-/*
- * Timestamp of last interrupt (32 bits are enough as we divide the value by 100
- * and then put it in a 16-bit field).
- */
-static uint32_t irq_ts;
-
-/*
- * Cached system info.
- */
-static struct st_tp_system_info_t system_info;
-
-static struct {
-#if ST_TP_EXTRA_BYTE == 1
-	uint8_t extra_byte;
-#endif
-	union {
-		uint8_t bytes[512];
-		struct st_tp_host_buffer_header_t buffer_header;
-		struct st_tp_host_buffer_heat_map_t heat_map;
-		struct st_tp_host_data_header_t data_header;
-		struct st_tp_event_t events[32];
-		uint32_t dump_info[32];
-	} /* anonymous */;
-} __packed rx_buf;
-
-
-#ifdef CONFIG_USB_ISOCHRONOUS
-#define USB_ISO_PACKET_SIZE 256
-/*
- * Header of each USB pacaket.
- */
-struct packet_header_t {
-	uint8_t index;
-
-#define HEADER_FLAGS_NEW_FRAME	BIT(0)
-	uint8_t flags;
-} __packed;
-BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE);
-
-static struct packet_header_t packet_header;
-
-/* What will be sent to USB interface. */
-struct st_tp_usb_packet_t {
-#define USB_FRAME_FLAGS_BUTTON	BIT(0)
-	/*
-	 * This will be true if user clicked on touchpad.
-	 * TODO(b/70482333): add corresponding code for button signal.
-	 */
-	uint8_t flags;
-
-	/*
-	 * This will be `st_tp_host_buffer_heat_map_t.frame` but each pixel
-	 * will be scaled to 8 bits value.
-	 */
-	uint8_t frame[ST_TOUCH_ROWS * ST_TOUCH_COLS];
-} __packed;
-
-/* Next buffer index SPI will write to. */
-static volatile uint32_t spi_buffer_index;
-/* Next buffer index USB will read from. */
-static volatile uint32_t usb_buffer_index;
-static struct st_tp_usb_packet_t usb_packet[2]; /* double buffering */
-/* How many bytes we have transmitted. */
-static size_t transmit_report_offset;
-
-/* Function prototypes */
-static int get_heat_map_addr(void);
-static void print_frame(void);
-static void st_tp_disable_heat_map(void);
-static void st_tp_enable_heat_map(void);
-static int st_tp_read_frame(void);
-static void st_tp_interrupt_send(void);
-DECLARE_DEFERRED(st_tp_interrupt_send);
-#endif
-
-
-/* Function implementations */
-
-static void set_bits(int *lvalue, int rvalue, int mask)
-{
-	*lvalue &= ~mask;
-	*lvalue |= rvalue & mask;
-}
-
-/*
- * Parse a finger report from ST event and save it to (report)->finger.
- *
- * @param report: pointer to a USB HID touchpad report.
- * @param event: a pointer event from ST.
- * @param i: array index for next finger.
- *
- * @return array index of next finger (i.e. (i + 1) if a finger is added).
- */
-static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
-			      struct st_tp_event_t *event,
-			      int i)
-{
-	const int id = event->finger.touch_id;
-
-	/* This is not a finger */
-	if (event->finger.touch_type == ST_TP_TOUCH_TYPE_INVALID)
-		return i;
-
-	if (event->evt_id ==  ST_TP_EVENT_ID_ENTER_POINTER)
-		touch_slot |= 1 << id;
-	else if (event->evt_id ==  ST_TP_EVENT_ID_LEAVE_POINTER)
-		touch_slot &= ~BIT(id);
-
-	/* We cannot report more fingers */
-	if (i >= ARRAY_SIZE(report->finger)) {
-		CPRINTS("WARN: ST reports more than %d fingers", i);
-		return i;
-	}
-
-	switch (event->evt_id) {
-	case ST_TP_EVENT_ID_ENTER_POINTER:
-	case ST_TP_EVENT_ID_MOTION_POINTER:
-		/* Pressure == 255 is a palm. */
-		report->finger[i].confidence = (event->finger.z < 255);
-		report->finger[i].tip = 1;
-		report->finger[i].inrange = 1;
-		report->finger[i].id = id;
-		report->finger[i].pressure = event->finger.z;
-		report->finger[i].width = (event->finger.minor |
-					   (event->minor_high << 4)) << 5;
-		report->finger[i].height = (event->finger.major |
-					    (event->major_high << 4)) << 5;
-
-		report->finger[i].x = (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X -
-				       event->finger.x);
-		report->finger[i].y = (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y -
-				       event->finger.y);
-		break;
-	case ST_TP_EVENT_ID_LEAVE_POINTER:
-		report->finger[i].id = id;
-		/* When a finger is leaving, it's not a palm */
-		report->finger[i].confidence = 1;
-		break;
-	}
-	return i + 1;
-}
-
-/*
- * Read domeswitch level from touchpad, and save in `system_state`.
- *
- * After calling this function, use
- *	`system_state & SYSTEM_STATE_DOME_SWITCH_LEVEL`
- * to get current value.
- *
- * @return error code on failure.
- */
-static int st_tp_check_domeswitch_state(void)
-{
-	int ret = st_tp_read_host_buffer_header();
-
-	if (ret)
-		return ret;
-
-	ret = rx_buf.buffer_header.flags & ST_TP_BUFFER_HEADER_DOMESWITCH_LVL;
-	/*
-	 * Domeswitch level from device is inverted.
-	 * That is, 0 => pressed, 1 => released.
-	 */
-	set_bits(&system_state,
-		 ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL,
-		 SYSTEM_STATE_DOME_SWITCH_LEVEL);
-	return 0;
-}
-
-static int st_tp_write_hid_report(void)
-{
-	int ret, i, num_finger, num_events;
-	const int old_system_state = system_state;
-	int domeswitch_changed;
-	struct usb_hid_touchpad_report report;
-
-	ret = st_tp_check_domeswitch_state();
-	if (ret)
-		return ret;
-
-	domeswitch_changed = ((old_system_state ^ system_state) &
-			      SYSTEM_STATE_DOME_SWITCH_LEVEL);
-
-	num_events = st_tp_read_all_events(1);
-	if (tp_control)
-		return 1;
-
-	memset(&report, 0, sizeof(report));
-	report.id = REPORT_ID_TOUCHPAD;
-	num_finger = 0;
-
-	for (i = 0; i < num_events; i++) {
-		struct st_tp_event_t *e = &rx_buf.events[i];
-
-		switch (e->evt_id) {
-		case ST_TP_EVENT_ID_ENTER_POINTER:
-		case ST_TP_EVENT_ID_MOTION_POINTER:
-		case ST_TP_EVENT_ID_LEAVE_POINTER:
-			num_finger = st_tp_parse_finger(&report, e, num_finger);
-			break;
-		default:
-			break;
-		}
-	}
-
-	if (!num_finger && !domeswitch_changed)  /* nothing changed */
-		return 0;
-
-	/* Don't report 0 finger click. */
-	if (num_finger && (system_state & SYSTEM_STATE_DOME_SWITCH_LEVEL))
-		report.button = 1;
-	report.count = num_finger;
-	report.timestamp = irq_ts / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
-
-	set_touchpad_report(&report);
-	return 0;
-}
-
-static int st_tp_read_report(void)
-{
-	if (system_state & SYSTEM_STATE_ENABLE_HEAT_MAP) {
-#ifdef CONFIG_USB_ISOCHRONOUS
-		/*
-		 * Because we are using double buffering, so, if
-		 * usb_buffer_index = N
-		 *
-		 * 1. spi_buffer_index == N      => ok, both slots are empty
-		 * 2. spi_buffer_index == N + 1  => ok, second slot is empty
-		 * 3. spi_buffer_index == N + 2  => not ok, need to wait for USB
-		 */
-		if (spi_buffer_index - usb_buffer_index <= 1) {
-			if (st_tp_read_frame() == EC_SUCCESS) {
-				spi_buffer_index++;
-				if (system_state & SYSTEM_STATE_DEBUG_MODE) {
-					print_frame();
-					usb_buffer_index++;
-				}
-			}
-		}
-		if (spi_buffer_index > usb_buffer_index)
-			hook_call_deferred(&st_tp_interrupt_send_data, 0);
-#endif
-	} else {
-		st_tp_write_hid_report();
-	}
-	return st_tp_send_ack();
-}
-
-static int st_tp_read_host_buffer_header(void)
-{
-	const uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, 0x00, 0x00 };
-	int rx_len = ST_TP_EXTRA_BYTE + sizeof(rx_buf.buffer_header);
-
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			       (uint8_t *)&rx_buf, rx_len);
-}
-
-static int st_tp_send_ack(void)
-{
-	uint8_t tx_buf[] = { ST_TP_CMD_SPI_HOST_BUFFER_ACK };
-
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-}
-
-static int st_tp_update_system_state(int new_state, int mask)
-{
-	int ret = EC_SUCCESS;
-	int need_locked_scan_mode = 0;
-
-	/* copy reserved bits */
-	set_bits(&new_state, system_state, ~mask);
-
-	mask = SYSTEM_STATE_DEBUG_MODE;
-	if ((new_state & mask) != (system_state & mask))
-		set_bits(&system_state, new_state, mask);
-
-	mask = SYSTEM_STATE_ENABLE_HEAT_MAP | SYSTEM_STATE_ENABLE_DOME_SWITCH;
-	if ((new_state & mask) != (system_state & mask)) {
-		uint8_t tx_buf[] = {
-			ST_TP_CMD_WRITE_FEATURE_SELECT,
-			0x05,
-			0
-		};
-		if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) {
-			CPRINTS("Heatmap enabled");
-			tx_buf[2] |= BIT(0);
-			need_locked_scan_mode = 1;
-		} else {
-			CPRINTS("Heatmap disabled");
-		}
-
-		if (new_state & SYSTEM_STATE_ENABLE_DOME_SWITCH)
-			tx_buf[2] |= BIT(1);
-		ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-		if (ret)
-			return ret;
-		set_bits(&system_state, new_state, mask);
-	}
-
-	mask = SYSTEM_STATE_ACTIVE_MODE;
-	if ((new_state & mask) != (system_state & mask)) {
-		uint8_t tx_buf[] = {
-			ST_TP_CMD_WRITE_SCAN_MODE_SELECT,
-			ST_TP_SCAN_MODE_ACTIVE,
-			!!(new_state & SYSTEM_STATE_ACTIVE_MODE),
-		};
-		CPRINTS("Enable Multi-Touch: %d", tx_buf[2]);
-		ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-		if (ret)
-			return ret;
-		set_bits(&system_state, new_state, mask);
-	}
-
-	/*
-	 * We need to lock scan mode to prevent scan rate drop when heat map
-	 * mode is enabled.
-	 */
-	if (need_locked_scan_mode) {
-		uint8_t tx_buf[] = {
-			ST_TP_CMD_WRITE_SCAN_MODE_SELECT,
-			ST_TP_SCAN_MODE_LOCKED,
-			0x0,
-		};
-
-		ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-		if (ret)
-			return ret;
-	}
-	return ret;
-}
-
-static void st_tp_enable_interrupt(int enable)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01, enable ? 1 : 0};
-	if (enable)
-		gpio_enable_interrupt(GPIO_TOUCHPAD_INT);
-	spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-	if (!enable)
-		gpio_disable_interrupt(GPIO_TOUCHPAD_INT);
-}
-
-static int st_tp_start_scan(void)
-{
-	int new_state = (SYSTEM_STATE_ACTIVE_MODE |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH);
-	int mask = new_state;
-	int ret;
-
-	CPRINTS("ST: Start scanning");
-	ret = st_tp_update_system_state(new_state, mask);
-	if (ret)
-		return ret;
-	st_tp_send_ack();
-	st_tp_enable_interrupt(1);
-
-	return ret;
-}
-
-static int st_tp_read_host_data_memory(uint16_t addr, void *rx_buf, int len)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8, addr & 0xFF
-	};
-
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), rx_buf, len);
-}
-
-static int st_tp_stop_scan(void)
-{
-	int new_state = 0;
-	int mask = SYSTEM_STATE_ACTIVE_MODE;
-	int ret;
-
-	CPRINTS("ST: Stop scanning");
-	ret = st_tp_update_system_state(new_state, mask);
-	st_tp_enable_interrupt(0);
-
-	return ret;
-}
-
-static int st_tp_load_host_data(uint8_t mem_id)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id
-	};
-	int retry, ret;
-	uint16_t count;
-	struct st_tp_host_data_header_t *header = &rx_buf.data_header;
-	int rx_len = sizeof(*header) + ST_TP_EXTRA_BYTE;
-
-	st_tp_read_host_data_memory(0x0000, &rx_buf, rx_len);
-	if (header->host_data_mem_id == mem_id)
-		return EC_SUCCESS; /* already loaded no need to reload */
-
-	count = header->count;
-
-	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-	if (ret)
-		return ret;
-
-	ret = EC_ERROR_TIMEOUT;
-	retry = 5;
-	while (retry--) {
-		st_tp_read_host_data_memory(0x0000, &rx_buf, rx_len);
-		if (header->magic == ST_TP_HEADER_MAGIC &&
-		    header->host_data_mem_id == mem_id &&
-		    header->count != count) {
-			ret = EC_SUCCESS;
-			break;
-		}
-		msleep(10);
-	}
-	return ret;
-}
-
-/*
- * Read System Info from Host Data Memory.
- *
- * @param reload: true to force reloading system info into host data memory
- *                before reading.
- */
-static int st_tp_read_system_info(int reload)
-{
-	int ret = EC_SUCCESS;
-	int rx_len = ST_TP_EXTRA_BYTE + ST_TP_SYSTEM_INFO_LEN;
-	uint8_t *ptr = rx_buf.bytes;
-
-	if (reload)
-		ret = st_tp_load_host_data(ST_TP_MEM_ID_SYSTEM_INFO);
-	if (ret)
-		return ret;
-	ret = st_tp_read_host_data_memory(0x0000, &rx_buf, rx_len);
-	if (ret)
-		return ret;
-
-	/* Parse the content */
-	memcpy(&system_info, ptr, ST_TP_SYSTEM_INFO_PART_1_SIZE);
-
-	/* Check header */
-	if (system_info.header.magic != ST_TP_HEADER_MAGIC ||
-	    system_info.header.host_data_mem_id != ST_TP_MEM_ID_SYSTEM_INFO)
-		return EC_ERROR_UNKNOWN;
-
-	ptr += ST_TP_SYSTEM_INFO_PART_1_SIZE;
-	ptr += ST_TP_SYSTEM_INFO_PART_1_RESERVED;
-	memcpy(&system_info.scr_res_x, ptr, ST_TP_SYSTEM_INFO_PART_2_SIZE);
-
-#define ST_TP_SHOW(attr) CPRINTS(#attr ": %04x", system_info.attr)
-	ST_TP_SHOW(chip0_id[0]);
-	ST_TP_SHOW(chip0_id[1]);
-	ST_TP_SHOW(chip0_ver);
-	ST_TP_SHOW(scr_tx_len);
-	ST_TP_SHOW(scr_rx_len);
-#define ST_TP_SHOW64(attr) CPRINTS(#attr ": %04llx", system_info.attr)
-	ST_TP_SHOW64(release_info);
-#undef ST_TP_SHOW
-#undef ST_TP_SHOW64
-	return ret;
-}
-
-/*
- * Enable / disable deep sleep on memory and bus.
- *
- * Before calling dump_error() and dump_error(), deep sleep should be disabled,
- * otherwise response data might be garbage.
- */
-static void enable_deep_sleep(int enable)
-{
-	uint8_t cmd[] = {0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08};
-
-	spi_transaction(SPI, cmd, sizeof(cmd), NULL, 0);
-}
-
-static void dump_error(void)
-{
-	uint8_t tx_buf[] = {0xFB, 0x20, 0x01, 0xEF, 0x80};
-	int rx_len = sizeof(rx_buf.dump_info) + ST_TP_EXTRA_BYTE;
-	int i;
-
-	spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			(uint8_t *)&rx_buf, rx_len);
-
-	for (i = 0; i < ARRAY_SIZE(rx_buf.dump_info); i += 4)
-		CPRINTS("%08x %08x %08x %08x",
-			rx_buf.dump_info[i + 0], rx_buf.dump_info[i + 1],
-			rx_buf.dump_info[i + 2], rx_buf.dump_info[i + 3]);
-	msleep(8);
-}
-
-/*
- * Dump entire 64K memory on touchpad.
- *
- * This is very time consuming.  For now, let's disable this in production
- * build.
- */
-static void dump_memory(void)
-{
-	uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE;
-	uint32_t offset, i;
-	uint8_t cmd[] = {0xFB, 0x00, 0x10, 0x00, 0x00};
-
-	if (!dump_memory_on_error)
-		return;
-
-	for (offset = 0; offset < size; offset += 512) {
-		cmd[3] = (offset >> 8) & 0xFF;
-		cmd[4] = (offset >> 0) & 0xFF;
-		spi_transaction(SPI, cmd, sizeof(cmd),
-				(uint8_t *)&rx_buf, rx_len);
-
-		for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) {
-			CPRINTF("%ph %ph %ph %ph "
-				"%ph %ph %ph %ph\n",
-				HEX_BUF(rx_buf.bytes + i + 4 * 0, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 1, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 2, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 3, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 4, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 5, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 6, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 7, 4));
-			msleep(8);
-		}
-	}
-	CPRINTF("===============================\n");
-	msleep(8);
-}
-
-/*
- * Set `tp_control` if there are any actions should be taken.
- */
-static void st_tp_handle_error(uint8_t error_type)
-{
-	tp_control |= TP_CONTROL_SHALL_DUMP_ERROR;
-
-	/*
-	 * Suggest action: memory dump and power cycle.
-	 */
-	if (error_type <= 0x06 ||
-	    error_type == 0xF1 ||
-	    error_type == 0xF2 ||
-	    error_type == 0xF3 ||
-	    (error_type >= 0x47 && error_type <= 0x4E)) {
-		tp_control |= TP_CONTROL_SHALL_RESET;
-		return;
-	}
-
-	/*
-	 * Suggest action: FW shall halt, consult ST.
-	 */
-	if ((error_type >= 0x20 && error_type <= 0x23) ||
-	    error_type == 0x25 ||
-	    (error_type >= 0x2E && error_type <= 0x46)) {
-		CPRINTS("tp shall halt");
-		tp_control |= TP_CONTROL_SHALL_HALT;
-		return;
-	}
-
-	/*
-	 * Corrupted panel configuration, a panel init should fix it.
-	 */
-	if (error_type >= 0x28 && error_type <= 0x29) {
-		tp_control |= TP_CONTROL_SHALL_INIT;
-		return;
-	}
-
-	/*
-	 * Corrupted CX section, a full panel init should fix it.
-	 */
-	if (error_type >= 0xA0 && error_type <= 0xA6) {
-		tp_control |= TP_CONTROL_SHALL_INIT_FULL;
-		return;
-	}
-
-	/*
-	 * When 0xFF is received, it's very likely ST touchpad is down.
-	 * Try if touchpad can be recovered by reset.
-	 */
-	if (error_type == 0xFF) {
-		if (tp_reset_retry_count < MAX_TP_RESET_RETRY_COUNT) {
-			tp_control |= TP_CONTROL_SHALL_RESET;
-			tp_reset_retry_count++;
-		} else {
-			tp_control |= TP_CONTROL_SHALL_HALT;
-		}
-		return;
-	}
-}
-
-/*
- * Handles error reports.
- */
-static void st_tp_handle_error_report(struct st_tp_event_t *e)
-{
-	uint8_t error_type = e->report.report_type;
-
-	CPRINTS("Touchpad error: %x %x", error_type,
-		((e->report.info[0] << 0) | (e->report.info[1] << 8) |
-		 (e->report.info[2] << 16) | (e->report.info[3] << 24)));
-
-	st_tp_handle_error(error_type);
-}
-
-static void st_tp_handle_status_report(struct st_tp_event_t *e)
-{
-	static uint32_t prev_idle_count;
-	uint32_t info = ((e->report.info[0] << 0) |
-			 (e->report.info[1] << 8) |
-			 (e->report.info[2] << 16) |
-			 (e->report.info[3] << 24));
-
-	if (e->report.report_type == ST_TP_STATUS_FCAL ||
-	    e->report.report_type == ST_TP_STATUS_FRAME_DROP)
-		CPRINTS("TP STATUS REPORT: %02x %08x",
-			e->report.report_type, info);
-
-	/*
-	 * Idle count might not change if ST FW is busy (for example, when the
-	 * user puts a big palm on touchpad).  Therefore if idle count doesn't
-	 * change, we need to double check with touch count.
-	 *
-	 * If touch count is 0, and idle count doesn't change, it means that:
-	 *
-	 *   1) ST doesn't think there are any fingers.
-	 *   2) ST is busy on something, can't get into idle mode, and this
-	 *      might cause (1).
-	 *
-	 * Resetting touchpad should be the correct action.
-	 */
-	if (e->report.report_type == ST_TP_STATUS_BEACON) {
-#if 0
-		const uint8_t touch_count = e->report.reserved;
-
-		CPRINTS("BEACON: idle count=%08x", info);
-		CPRINTS("  touch count=%d  touch slot=%04x",
-			touch_count, touch_slot);
-#endif
-		if (prev_idle_count == info && touch_slot == 0) {
-			CPRINTS("  idle count=%08x not changed", info);
-			tp_control |= TP_CONTROL_SHALL_RESET;
-			return;
-		}
-		prev_idle_count = info;
-	}
-}
-
-/*
- * Read all events, and handle errors.
- *
- * When there are error events, suggested action will be saved in `tp_control`.
- *
- * @param show_error: whether EC should read and dump error or not.
- *   ***If this is true, rx_buf.events[] will be cleared.***
- *
- * @return number of events available
- */
-static int st_tp_read_all_events(int show_error)
-{
-	uint8_t cmd = ST_TP_CMD_READ_ALL_EVENTS;
-	int rx_len = sizeof(rx_buf.events) + ST_TP_EXTRA_BYTE;
-	int i;
-
-	if (spi_transaction(SPI, &cmd, 1, (uint8_t *)&rx_buf, rx_len))
-		return 0;
-
-	for (i = 0; i < ARRAY_SIZE(rx_buf.events); i++) {
-		struct st_tp_event_t *e = &rx_buf.events[i];
-
-		if (e->magic != ST_TP_EVENT_MAGIC)
-			break;
-
-		switch (e->evt_id) {
-		case ST_TP_EVENT_ID_ERROR_REPORT:
-			st_tp_handle_error_report(e);
-			break;
-		case ST_TP_EVENT_ID_STATUS_REPORT:
-			st_tp_handle_status_report(e);
-			break;
-		}
-	}
-
-	if (show_error && (tp_control & TP_CONTROL_SHALL_DUMP_ERROR)) {
-		enable_deep_sleep(0);
-		dump_error();
-		dump_memory();
-		enable_deep_sleep(1);
-		/* rx_buf.events[] is invalid now */
-		i = 0;
-	}
-	tp_control &= ~TP_CONTROL_SHALL_DUMP_ERROR;
-
-	return i;
-}
-
-/*
- * Reset touchpad.  This function will wait for "controller ready" event after
- * the touchpad is reset.
- */
-static int st_tp_reset(void)
-{
-	int i, num_events, retry = 100;
-
-	board_touchpad_reset();
-
-	while (retry--) {
-		num_events = st_tp_read_all_events(0);
-
-		/*
-		 * We are not doing full panel initialization, and error code
-		 * suggest us to reset or halt.
-		 */
-		if (!(tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) &&
-		    (tp_control & (TP_CONTROL_SHALL_HALT |
-				   TP_CONTROL_SHALL_RESET)))
-			break;
-
-		for (i = 0; i < num_events; i++) {
-			struct st_tp_event_t *e = &rx_buf.events[i];
-
-			if (e->evt_id == ST_TP_EVENT_ID_CONTROLLER_READY) {
-				CPRINTS("Touchpad ready");
-				tp_reset_retry_count = 0;
-				return 0;
-			}
-		}
-
-		msleep(10);
-	}
-	CPRINTS("Timeout waiting for controller ready.");
-	return EC_ERROR_TIMEOUT;
-}
-
-/* Initialize the controller ICs after reset */
-static void st_tp_init(void)
-{
-	tp_control = 0;
-	system_state = 0;
-
-	if (st_tp_reset())
-		return;
-
-	if (tp_control) {
-		CPRINTS("tp_control = %x", tp_control);
-		return;
-	}
-	/*
-	 * On boot, ST firmware will load system info to host data memory,
-	 * So we don't need to reload it.
-	 */
-	st_tp_read_system_info(0);
-
-	system_state = SYSTEM_STATE_READY;
-	touch_slot = 0;
-
-	touchpad_power_control();
-}
-DECLARE_DEFERRED(st_tp_init);
-
-#ifdef CONFIG_USB_UPDATE
-int touchpad_get_info(struct touchpad_info *tp)
-{
-	if (st_tp_read_system_info(1)) {
-		tp->status = EC_RES_SUCCESS;
-		tp->vendor = ST_VENDOR_ID;
-		/*
-		 * failed to get system info, FW corrupted, return some default
-		 * values.
-		 */
-		tp->st.id = 0x3936;
-		tp->st.fw_version = 0;
-		tp->st.fw_checksum = 0;
-		return sizeof(*tp);
-	}
-
-	tp->status = EC_RES_SUCCESS;
-	tp->vendor = ST_VENDOR_ID;
-	tp->st.id = (system_info.chip0_id[0] << 8) | system_info.chip0_id[1];
-	tp->st.fw_version = system_info.release_info;
-	tp->st.fw_checksum = system_info.fw_crc;
-
-	return sizeof(*tp);
-}
-
-/*
- * Helper functions for firmware update
- *
- * There is no documentation about ST_TP_CMD_WRITE_HW_REG (0xFA).
- * All implementations below are based on sample code from ST.
- */
-static int write_hwreg_cmd32(uint32_t address, uint32_t data)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		(data >> 24) & 0xFF,
-		(data >> 16) & 0xFF,
-		(data >> 8) & 0xFF,
-		(data >> 0) & 0xFF,
-	};
-
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-}
-
-static int write_hwreg_cmd8(uint32_t address, uint8_t data)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		data,
-	};
-
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-}
-
-static int wait_for_flash_ready(uint8_t type)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HW_REG,
-		0x20, 0x00, 0x00, type,
-	};
-	int ret = EC_SUCCESS, retry = 200;
-
-	while (retry--) {
-		ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-				      (uint8_t *)&rx_buf, 1 + ST_TP_EXTRA_BYTE);
-		if (ret == EC_SUCCESS && !(rx_buf.bytes[0] & 0x80))
-			break;
-		msleep(50);
-	}
-	return retry >= 0 ? ret : EC_ERROR_TIMEOUT;
-}
-
-static int erase_flash(int full_init_required)
-{
-	int ret;
-
-	if (full_init_required)
-		ret = write_hwreg_cmd32(0x20000128, 0xFFFFFFFF);
-	else
-		/* Erase everything, except CX */
-		ret = write_hwreg_cmd32(0x20000128, 0xFFFFFF83);
-	if (ret)
-		return ret;
-	ret = write_hwreg_cmd8(0x2000006B, 0x00);
-	if (ret)
-		return ret;
-	ret = write_hwreg_cmd8(0x2000006A, 0xA0);
-	if (ret)
-		return ret;
-	return wait_for_flash_ready(0x6A);
-}
-
-static int st_tp_prepare_for_update(int full_init_required)
-{
-	/* hold m3 */
-	write_hwreg_cmd8(0x20000024, 0x01);
-	/* unlock flash */
-	write_hwreg_cmd8(0x20000025, 0x20);
-	/* unlock flash erase */
-	write_hwreg_cmd8(0x200000DE, 0x03);
-	erase_flash(full_init_required);
-
-	return EC_SUCCESS;
-}
-
-static int st_tp_start_flash_dma(void)
-{
-	int ret;
-
-	ret = write_hwreg_cmd8(0x20000071, 0xC0);
-	if (ret)
-		return ret;
-	ret = wait_for_flash_ready(0x71);
-	return ret;
-}
-
-static int st_tp_write_one_chunk(const uint8_t *head,
-				 uint32_t addr, uint32_t chunk_size)
-{
-	uint8_t tx_buf[ST_TP_DMA_CHUNK_SIZE + 5];
-	uint32_t index = 0;
-	int ret;
-
-	index = 0;
-
-	tx_buf[index++] = ST_TP_CMD_WRITE_HW_REG;
-	tx_buf[index++] = (addr >> 24) & 0xFF;
-	tx_buf[index++] = (addr >> 16) & 0xFF;
-	tx_buf[index++] = (addr >> 8) & 0xFF;
-	tx_buf[index++] = (addr >> 0) & 0xFF;
-	memcpy(tx_buf + index, head, chunk_size);
-	ret = spi_transaction(SPI, tx_buf, chunk_size + 5, NULL, 0);
-
-	return ret;
-}
-
-/*
- * @param offset: offset in memory to copy the data (in bytes).
- * @param size: length of data (in bytes).
- * @param data: pointer to data bytes.
- */
-static int st_tp_write_flash(int offset, int size, const uint8_t *data)
-{
-	uint8_t tx_buf[12] = {0};
-	const uint8_t *head = data, *tail = data + size;
-	uint32_t addr, index, chunk_size;
-	uint32_t flash_buffer_size;
-	int ret;
-
-	offset >>= 2;  /* offset should be count in words */
-	/*
-	 * To write to flash, the data has to be separated into several chunks.
-	 * Each chunk will be no more than `ST_TP_DMA_CHUNK_SIZE` bytes.
-	 * The chunks will first be saved into a buffer, the buffer can only
-	 * holds `ST_TP_FLASH_BUFFER_SIZE` bytes.  We have to flush the buffer
-	 * when the capacity is reached.
-	 */
-	while (head < tail) {
-		addr = 0x00100000;
-		flash_buffer_size = 0;
-		while (flash_buffer_size < ST_TP_FLASH_BUFFER_SIZE) {
-			chunk_size = MIN(ST_TP_DMA_CHUNK_SIZE, tail - head);
-			ret = st_tp_write_one_chunk(head, addr, chunk_size);
-			if (ret)
-				return ret;
-
-			flash_buffer_size += chunk_size;
-			addr += chunk_size;
-			head += chunk_size;
-
-			if (head >= tail)
-				break;
-		}
-
-		/* configuring the DMA */
-		flash_buffer_size = flash_buffer_size / 4 - 1;
-		index = 0;
-
-		tx_buf[index++] = ST_TP_CMD_WRITE_HW_REG;
-		tx_buf[index++] = 0x20;
-		tx_buf[index++] = 0x00;
-		tx_buf[index++] = 0x00;
-		tx_buf[index++] = 0x72;  /* flash DMA config */
-		tx_buf[index++] = 0x00;
-		tx_buf[index++] = 0x00;
-
-		tx_buf[index++] = offset & 0xFF;
-		tx_buf[index++] = (offset >> 8) & 0xFF;
-		tx_buf[index++] = flash_buffer_size & 0xFF;
-		tx_buf[index++] = (flash_buffer_size >> 8) & 0xFF;
-		tx_buf[index++] = 0x00;
-
-		ret = spi_transaction(SPI, tx_buf, index, NULL, 0);
-		if (ret)
-			return ret;
-		ret = st_tp_start_flash_dma();
-		if (ret)
-			return ret;
-
-		offset += ST_TP_FLASH_BUFFER_SIZE / 4;
-	}
-	return EC_SUCCESS;
-}
-
-static int st_tp_check_command_echo(const uint8_t *cmd, const size_t len)
-{
-	int num_events, i;
-	num_events = st_tp_read_all_events(0);
-
-	for (i = 0; i < num_events; i++) {
-		struct st_tp_event_t *e = &rx_buf.events[i];
-
-		if (e->evt_id == ST_TP_EVENT_ID_STATUS_REPORT &&
-		    e->report.report_type == ST_TP_STATUS_CMD_ECHO &&
-		    memcmp(e->report.info, cmd, MIN(4, len)) == 0)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_BUSY;
-}
-
-static uint8_t get_cx_version(uint8_t tp_version)
-{
-	/*
-	 * CX version is tracked by ST release note: go/whiskers-st-release-note
-	 */
-
-	if (tp_version >= 32)
-		return 3;
-
-	if (tp_version >= 20)
-		return 2;
-
-	if (tp_version >= 18)
-		return 1;
-	return 0;
-}
-
-/*
- * Perform panel initialization.
- *
- * This function will wait until the initialization is done, or 10 second
- * timeout is reached.
- *
- * @param full: 1 => force "full" panel initialization.  Otherwise, tp_control
- *              will be checked to decide if full panel initialization is
- *              required.
- *
- * @return EC_SUCCESS or error code.
- */
-static int st_tp_panel_init(int full)
-{
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02
-	};
-	int ret, retry;
-
-	if (tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL))
-		return EC_ERROR_BUSY;
-
-	st_tp_stop_scan();
-	ret = st_tp_reset();
-	/*
-	 * TODO(b:118312397): Figure out how to handle st_tp_reset errors (if
-	 * needed at all).
-	 */
-	CPRINTS("st_tp_reset ret=%d", ret);
-
-	full |= tp_control & TP_CONTROL_SHALL_INIT_FULL;
-	if (full) {
-		/* should perform full panel initialization */
-		tx_buf[2] = 0x3;
-		tp_control = TP_CONTROL_INIT_FULL;
-	} else {
-		tp_control = TP_CONTROL_INIT;
-	}
-
-	CPRINTS("Start panel initialization (full=%d)", full);
-	spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
-
-	retry = 100;
-	while (retry--) {
-		watchdog_reload();
-		msleep(100);
-
-		ret = st_tp_check_command_echo(tx_buf, sizeof(tx_buf));
-		if (ret == EC_SUCCESS) {
-			CPRINTS("Panel initialization completed.");
-			tp_control &= ~(TP_CONTROL_INIT | TP_CONTROL_INIT_FULL);
-			st_tp_init();
-			return EC_SUCCESS;
-		} else if (ret == EC_ERROR_BUSY) {
-			CPRINTS("Panel initialization on going...");
-		} else if (tp_control & ~(TP_CONTROL_INIT |
-					  TP_CONTROL_INIT_FULL)) {
-			/* there are other kind of errors. */
-			CPRINTS("Panel initialization failed, tp_control: %x",
-				tp_control);
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-	return EC_ERROR_TIMEOUT;
-}
-
-/*
- * @param offset: should be address between 0 to 1M, aligned with
- *	ST_TP_DMA_CHUNK_SIZE.
- * @param size: length of `data` array.
- * @param data: content of new touchpad firmware.
- */
-int touchpad_update_write(int offset, int size, const uint8_t *data)
-{
-	static int full_init_required;
-	int ret, flash_offset;
-
-	CPRINTS("%s %08x %d", __func__, offset, size);
-	if (offset == 0) {
-		const struct st_tp_fw_header_t *header;
-		uint8_t old_cx_version;
-		uint8_t new_cx_version;
-		int retry;
-
-		header = (const struct st_tp_fw_header_t *)data;
-		if (header->signature != 0xAA55AA55)
-			return EC_ERROR_INVAL;
-
-		for (retry = 50; retry > 0; retry--) {
-			watchdog_reload();
-			if (system_state & SYSTEM_STATE_READY)
-				break;
-			if (retry % 10 == 0)
-				CPRINTS("TP not ready for update, "
-					"will check again");
-			msleep(100);
-		}
-
-		old_cx_version = get_cx_version(system_info.release_info);
-		new_cx_version = get_cx_version(header->release_info);
-
-		full_init_required = old_cx_version != new_cx_version;
-
-		/* stop scanning, interrupt, etc... */
-		st_tp_stop_scan();
-
-		ret = st_tp_prepare_for_update(full_init_required);
-		if (ret)
-			return ret;
-		return EC_SUCCESS;
-	}
-
-	flash_offset = offset - CONFIG_UPDATE_PDU_SIZE;
-	if (flash_offset % ST_TP_DMA_CHUNK_SIZE)
-		return EC_ERROR_INVAL;
-
-	if (flash_offset >= ST_TP_FLASH_OFFSET_PANEL_CFG &&
-	    flash_offset < ST_TP_FLASH_OFFSET_CONFIG)
-		/* don't update CX section && panel config section */
-		return EC_SUCCESS;
-
-	ret = st_tp_write_flash(flash_offset, size, data);
-	if (ret)
-		return ret;
-
-	if (offset + size == CONFIG_TOUCHPAD_VIRTUAL_SIZE) {
-		CPRINTS("%s: End update, wait for reset.", __func__);
-
-		ret = st_tp_panel_init(full_init_required);
-		task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_TP_UPDATED);
-		return ret;
-	}
-
-	return EC_SUCCESS;
-}
-
-int touchpad_debug(const uint8_t *param, unsigned int param_size,
-		   uint8_t **data, unsigned int *data_size)
-{
-	static uint8_t buf[8];
-	int num_events;
-
-	if (param_size != 1)
-		return EC_RES_INVALID_PARAM;
-
-	switch (*param) {
-	case ST_TP_DEBUG_CMD_RESET_TOUCHPAD:
-		*data = NULL;
-		*data_size = 0;
-		st_tp_stop_scan();
-		hook_call_deferred(&st_tp_init_data, 100 * MSEC);
-		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_CALIBRATE:
-		/* no return value */
-		*data = NULL;
-		*data_size = 0;
-		st_tp_panel_init(1);
-		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_START_SCAN:
-		*data = NULL;
-		*data_size = 0;
-		st_tp_start_scan();
-		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_STOP_SCAN:
-		*data = NULL;
-		*data_size = 0;
-		st_tp_stop_scan();
-		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_READ_BUF_HEADER:
-		*data = buf;
-		*data_size = 8;
-		st_tp_read_host_buffer_header();
-		memcpy(buf, rx_buf.bytes, *data_size);
-		CPRINTS("header: %ph", HEX_BUF(buf, *data_size));
-		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_READ_EVENTS:
-		num_events = st_tp_read_all_events(0);
-		if (num_events) {
-			int i;
-
-			for (i = 0; i < num_events; i++) {
-				CPRINTS("event[%d]: id=%d, type=%d",
-					i, rx_buf.events[i].evt_id,
-					rx_buf.events[i].report.report_type);
-			}
-		}
-		*data = buf;
-		*data_size = 1;
-		*data[0] = num_events;
-		st_tp_send_ack();
-		return EC_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-#endif
-
-void touchpad_interrupt(enum gpio_signal signal)
-{
-	irq_ts = __hw_clock_source_read();
-
-	task_wake(TASK_ID_TOUCHPAD);
-}
-
-static int touchpad_should_enable(void)
-{
-	/* touchpad is not ready. */
-	if (tp_control)
-		return 0;
-
-#ifdef CONFIG_USB_SUSPEND
-	if (usb_is_suspended() && !usb_is_remote_wakeup_enabled())
-		return 0;
-#endif
-
-#ifdef CONFIG_TABLET_MODE
-	if (tablet_get_mode())
-		return 0;
-#endif
-	return 1;
-}
-
-/* Make a decision on touchpad power, based on USB and tablet mode status. */
-static void touchpad_power_control(void)
-{
-	const int enabled = !!(system_state & SYSTEM_STATE_ACTIVE_MODE);
-	int enable = touchpad_should_enable();
-
-	if (enabled == enable)
-		return;
-
-	if (enable)
-		st_tp_start_scan();
-	else
-		st_tp_stop_scan();
-}
-
-static void touchpad_read_idle_count(void)
-{
-	static uint32_t prev_count;
-	uint32_t count;
-	int ret;
-	int rx_len = 2 + ST_TP_EXTRA_BYTE;
-	uint8_t cmd_read_counter[] = {
-		0xFB, 0x00, 0x10, 0xff, 0xff
-	};
-
-	/* Find address of idle count. */
-	ret = st_tp_load_host_data(ST_TP_MEM_ID_SYSTEM_INFO);
-	if (ret)
-		return;
-	st_tp_read_host_data_memory(0x0082, &rx_buf, rx_len);
-
-	/* Fill in address of idle count, the byte order is reversed. */
-	cmd_read_counter[3] = rx_buf.bytes[1];
-	cmd_read_counter[4] = rx_buf.bytes[0];
-
-	/* Read idle count */
-	spi_transaction(SPI, cmd_read_counter, sizeof(cmd_read_counter),
-			(uint8_t *)&rx_buf, 4 + ST_TP_EXTRA_BYTE);
-
-	count = rx_buf.dump_info[0];
-
-	CPRINTS("idle_count = %08x", count);
-	if (count == prev_count)
-		CPRINTS("counter doesn't change...");
-	else
-		prev_count = count;
-}
-
-/*
- * Try to collect symptoms of type B error.
- *
- * There are three possible symptoms:
- *   1. error dump section is corrupted / contains error.
- *   2. memory stack is corrupted (not 0xCC).
- *   3. idle count is not changing.
- */
-static void touchpad_collect_error(void)
-{
-	const uint8_t tx_dump_error[] = {
-		0xFB, 0x20, 0x01, 0xEF, 0x80
-	};
-	uint32_t dump_info[2];
-	const uint8_t tx_dump_memory[] = {
-		0xFB, 0x00, 0x10, 0x00, 0x00
-	};
-	uint32_t dump_memory[16];
-	int i;
-
-	enable_deep_sleep(0);
-	spi_transaction(SPI, tx_dump_error, sizeof(tx_dump_error),
-			(uint8_t *)&rx_buf,
-			sizeof(dump_info) + ST_TP_EXTRA_BYTE);
-	memcpy(dump_info, rx_buf.bytes, sizeof(dump_info));
-
-	spi_transaction(SPI, tx_dump_memory, sizeof(tx_dump_memory),
-			(uint8_t *)&rx_buf,
-			sizeof(dump_memory) + ST_TP_EXTRA_BYTE);
-	memcpy(dump_memory, rx_buf.bytes, sizeof(dump_memory));
-
-	CPRINTS("check error dump: %08x %08x", dump_info[0], dump_info[1]);
-	CPRINTS("check memory dump:");
-	for (i = 0; i < ARRAY_SIZE(dump_memory); i += 8) {
-		CPRINTF("%08x %08x %08x %08x %08x %08x %08x %08x\n",
-			dump_memory[i + 0],
-			dump_memory[i + 1],
-			dump_memory[i + 2],
-			dump_memory[i + 3],
-			dump_memory[i + 4],
-			dump_memory[i + 5],
-			dump_memory[i + 6],
-			dump_memory[i + 7]);
-	}
-
-	for (i = 0; i < 3; i++)
-		touchpad_read_idle_count();
-	enable_deep_sleep(1);
-
-	tp_control |= TP_CONTROL_SHALL_RESET;
-}
-
-void touchpad_task(void *u)
-{
-	uint32_t event;
-
-	while (1) {
-		uint32_t retry;
-
-		for (retry = 0; retry < 3; retry++) {
-			CPRINTS("st_tp_init: trial %d", retry + 1);
-			st_tp_init();
-
-			if (system_state & SYSTEM_STATE_READY)
-				break;
-			/*
-			 * React on touchpad errors.
-			 */
-			if (tp_control & TP_CONTROL_SHALL_INIT_FULL) {
-				/* suppress other handlers */
-				tp_control = TP_CONTROL_SHALL_INIT_FULL;
-				st_tp_panel_init(1);
-			} else if (tp_control & TP_CONTROL_SHALL_INIT) {
-				/* suppress other handlers */
-				tp_control = TP_CONTROL_SHALL_INIT;
-				st_tp_panel_init(0);
-			} else if (tp_control & TP_CONTROL_SHALL_RESET) {
-				/* suppress other handlers */
-				tp_control = TP_CONTROL_SHALL_RESET;
-			} else if (tp_control & TP_CONTROL_SHALL_HALT) {
-				CPRINTS("shall halt");
-				tp_control = 0;
-				break;
-			}
-		}
-
-		if (system_state & SYSTEM_STATE_READY)
-			break;
-
-		/* failed to init, mark it as ready to allow upgrade */
-		system_state = SYSTEM_STATE_READY;
-		/* wait for upgrade complete */
-		task_wait_event_mask(TASK_EVENT_TP_UPDATED, -1);
-	}
-	touchpad_power_control();
-
-	while (1) {
-		/* wait for at most 3 seconds */
-		event = task_wait_event(3 * 1000 * 1000);
-
-		if ((event & TASK_EVENT_TIMER) &&
-		    (system_state & SYSTEM_STATE_ACTIVE_MODE))
-			/*
-			 * Haven't received anything for 3 seconds, and we are
-			 * supposed to be in active mode.  This is not normal,
-			 * check for errors and reset.
-			 */
-			touchpad_collect_error();
-
-		if (event & TASK_EVENT_WAKE)
-			while (!tp_control &&
-			       !gpio_get_level(GPIO_TOUCHPAD_INT))
-				st_tp_read_report();
-
-		/*
-		 * React on touchpad errors.
-		 */
-		if (tp_control & TP_CONTROL_SHALL_INIT_FULL) {
-			/* suppress other handlers */
-			tp_control = TP_CONTROL_SHALL_INIT_FULL;
-			st_tp_panel_init(1);
-		} else if (tp_control & TP_CONTROL_SHALL_INIT) {
-			/* suppress other handlers */
-			tp_control = TP_CONTROL_SHALL_INIT;
-			st_tp_panel_init(0);
-		} else if (tp_control & TP_CONTROL_SHALL_RESET) {
-			/* suppress other handlers */
-			tp_control = TP_CONTROL_SHALL_RESET;
-			st_tp_init();
-		} else if (tp_control & TP_CONTROL_SHALL_HALT) {
-			tp_control = 0;
-			st_tp_stop_scan();
-		}
-
-		if (event & TASK_EVENT_POWER)
-			touchpad_power_control();
-	}
-}
-
-/*
- * When USB PM status changes, or tablet mode changes, call in the main task to
- * decide whether to turn touchpad on or off.
- */
-#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_TABLET_MODE)
-static void touchpad_power_change(void)
-{
-	task_set_event(TASK_ID_TOUCHPAD, TASK_EVENT_POWER);
-}
-#endif
-#ifdef CONFIG_USB_SUSPEND
-DECLARE_HOOK(HOOK_USB_PM_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
-#endif
-#ifdef CONFIG_TABLET_MODE
-DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
-#endif
-
-#ifdef CONFIG_USB_ISOCHRONOUS
-static void st_tp_enable_heat_map(void)
-{
-	int new_state = (SYSTEM_STATE_ENABLE_HEAT_MAP |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH |
-			 SYSTEM_STATE_ACTIVE_MODE);
-	int mask = new_state;
-
-	st_tp_update_system_state(new_state, mask);
-}
-DECLARE_DEFERRED(st_tp_enable_heat_map);
-
-static void st_tp_disable_heat_map(void)
-{
-	int new_state = 0;
-	int mask = SYSTEM_STATE_ENABLE_HEAT_MAP;
-
-	st_tp_update_system_state(new_state, mask);
-}
-DECLARE_DEFERRED(st_tp_disable_heat_map);
-
-static void print_frame(void)
-{
-	char debug_line[ST_TOUCH_COLS + 5];
-	int i, j, index;
-	int v;
-	struct st_tp_usb_packet_t *packet = &usb_packet[usb_buffer_index & 1];
-
-	if (usb_buffer_index == spi_buffer_index)
-		/* buffer is empty. */
-		return;
-
-	/* We will have ~150 FPS, let's print ~4 frames per second */
-	if (usb_buffer_index % 37 == 0) {
-		/* move cursor back to top left corner */
-		CPRINTF("\x1b[H");
-		CPUTS("==============\n");
-		for (i = 0; i < ST_TOUCH_ROWS; i++) {
-			for (j = 0; j < ST_TOUCH_COLS; j++) {
-				index = i * ST_TOUCH_COLS;
-				index += (ST_TOUCH_COLS - j - 1); // flip X
-				v = packet->frame[index];
-
-				if (v > 0)
-					debug_line[j] = '0' + v * 10 / 256;
-				else
-					debug_line[j] = ' ';
-			}
-			debug_line[j++] = '\n';
-			debug_line[j++] = '\0';
-			CPRINTF(debug_line);
-		}
-		CPUTS("==============\n");
-	}
-}
-
-static int st_tp_read_frame(void)
-{
-	int ret = EC_SUCCESS;
-	int rx_len = ST_TOUCH_FRAME_SIZE + ST_TP_EXTRA_BYTE;
-	int heat_map_addr = get_heat_map_addr();
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_SPI_HOST_BUFFER,
-		(heat_map_addr >> 8) & 0xFF,
-		(heat_map_addr >> 0) & 0xFF,
-	};
-
-	/*
-	 * Since usb_packet.frame is already ane uint8_t byte array, we can just
-	 * make it the RX buffer for SPI transaction.
-	 *
-	 * When there is a extra byte, since we know that flags is a one byte
-	 * value, and we will override it later, it's okay for SPI transaction
-	 * to write the extra byte to flags address.
-	 */
-#if ST_TP_EXTRA_BYTE == 1
-	BUILD_ASSERT(sizeof(usb_packet[0].flags) == 1);
-	uint8_t *rx_buf = &usb_packet[spi_buffer_index & 1].flags;
-#else
-	uint8_t *rx_buf = usb_packet[spi_buffer_index & 1].frame;
-#endif
-
-	st_tp_read_all_events(1);
-	if (tp_control) {
-		ret = EC_ERROR_UNKNOWN;
-		goto failed;
-	}
-
-	if (heat_map_addr < 0)
-		goto failed;
-
-	ret = st_tp_check_domeswitch_state();
-	if (ret)
-		goto failed;
-
-	/*
-	 * Theoretically, we should read host buffer header to check if data is
-	 * valid, but the data should always be ready when interrupt pin is low.
-	 * Let's skip this check for now.
-	 */
-	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			      (uint8_t *)rx_buf, rx_len);
-	if (ret == EC_SUCCESS) {
-		int i;
-		uint8_t *dest = usb_packet[spi_buffer_index & 1].frame;
-		uint8_t max_value = 0;
-
-		for (i = 0; i < ST_TOUCH_COLS * ST_TOUCH_ROWS; i++)
-			max_value |= dest[i];
-		if (max_value == 0) // empty frame
-			return -1;
-
-		usb_packet[spi_buffer_index & 1].flags = 0;
-		if (system_state & SYSTEM_STATE_DOME_SWITCH_LEVEL)
-			usb_packet[spi_buffer_index & 1].flags |=
-				USB_FRAME_FLAGS_BUTTON;
-	}
-failed:
-	return ret;
-}
-
-/* Define USB interface for heat_map */
-
-/* function prototypes */
-static int st_tp_usb_set_interface(usb_uint alternate_setting,
-				   usb_uint interface);
-static int heatmap_send_packet(struct usb_isochronous_config const *config);
-static void st_tp_usb_tx_callback(struct usb_isochronous_config const *config);
-
-/* USB descriptors */
-USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config,
-			    USB_IFACE_ST_TOUCHPAD,
-			    USB_CLASS_VENDOR_SPEC,
-			    USB_SUBCLASS_GOOGLE_HEATMAP,
-			    USB_PROTOCOL_GOOGLE_HEATMAP,
-			    USB_STR_HEATMAP_NAME,  /* interface name */
-			    USB_EP_ST_TOUCHPAD,
-			    USB_ISO_PACKET_SIZE,
-			    st_tp_usb_tx_callback,
-			    st_tp_usb_set_interface,
-			    1 /* 1 extra EP for interrupts */)
-
-/* ***This function will be executed in interrupt context*** */
-void st_tp_usb_tx_callback(struct usb_isochronous_config const *config)
-{
-	task_wake(TASK_ID_HEATMAP);
-}
-
-void heatmap_task(void *unused)
-{
-	struct usb_isochronous_config const *config;
-
-	config = &usb_st_tp_heatmap_config;
-
-	while (1) {
-		/* waiting st_tp_usb_tx_callback() */
-		task_wait_event(-1);
-
-		if (system_state & SYSTEM_STATE_DEBUG_MODE)
-			continue;
-
-		if (usb_buffer_index == spi_buffer_index)
-			/* buffer is empty */
-			continue;
-
-		while (heatmap_send_packet(config))
-			/* We failed to write a packet, try again later. */
-			task_wait_event(100);
-	}
-}
-
-/* USB interface has completed TX, it's asking for more data */
-static int heatmap_send_packet(struct usb_isochronous_config const *config)
-{
-	size_t num_byte_available;
-	size_t offset = 0;
-	int ret, buffer_id = -1;
-	struct st_tp_usb_packet_t *packet = &usb_packet[usb_buffer_index & 1];
-
-	packet_header.flags = 0;
-	num_byte_available = sizeof(*packet) - transmit_report_offset;
-	if (num_byte_available > 0) {
-		if (transmit_report_offset == 0)
-			packet_header.flags |= HEADER_FLAGS_NEW_FRAME;
-		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)&packet_header,
-				sizeof(packet_header),
-				offset,
-				&buffer_id,
-				0);
-		/*
-		 * Since USB_ISO_PACKET_SIZE > sizeof(packet_header), this must
-		 * be true.
-		 */
-		if (ret != sizeof(packet_header))
-			return -1;
-
-		offset += ret;
-		packet_header.index++;
-
-		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)packet + transmit_report_offset,
-				num_byte_available,
-				offset,
-				&buffer_id,
-				1);
-		if (ret < 0) {
-			/*
-			 * TODO(b/70482333): handle this error, it might be:
-			 *   1. timeout (buffer_id changed)
-			 *   2. invalid offset
-			 *
-			 * For now, let's just return an error and try again.
-			 */
-			CPRINTS("%s %d: %d", __func__, __LINE__, -ret);
-			return ret;
-		}
-
-		/* We should have sent some bytes, update offset */
-		transmit_report_offset += ret;
-		if (transmit_report_offset == sizeof(*packet)) {
-			transmit_report_offset = 0;
-			usb_buffer_index++;
-		}
-	}
-	return 0;
-}
-
-static int st_tp_usb_set_interface(usb_uint alternate_setting,
-				   usb_uint interface)
-{
-	if (alternate_setting == 1) {
-		if ((system_info.release_info & 0xFF) <
-		    ST_TP_MIN_HEATMAP_VERSION) {
-			CPRINTS("release version %04llx doesn't support heatmap",
-				system_info.release_info);
-			/* Heatmap mode is not supported in this version. */
-			return -1;
-		}
-
-		hook_call_deferred(&st_tp_enable_heat_map_data, 0);
-		return 0;
-	} else if (alternate_setting == 0) {
-		hook_call_deferred(&st_tp_disable_heat_map_data, 0);
-		return 0;
-	} else  /* we only have two settings. */
-		return -1;
-}
-
-static int get_heat_map_addr(void)
-{
-	/*
-	 * TODO(stimim): drop this when we are sure all trackpads are having the
-	 * same config (e.g. after EVT).
-	 */
-	if (system_info.release_info >= 0x3)
-		return 0x0120;
-	else if (system_info.release_info == 0x1)
-		return 0x20;
-	else
-		return -1; /* Unknown version */
-}
-
-struct st_tp_interrupt_t {
-#define ST_TP_INT_FRAME_AVAILABLE	BIT(0)
-	uint8_t flags;
-} __packed;
-
-static usb_uint st_tp_usb_int_buffer[
-	DIV_ROUND_UP(sizeof(struct st_tp_interrupt_t), 2)] __usb_ram;
-
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_ST_TOUCHPAD, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_ST_TOUCHPAD_INT,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = sizeof(struct st_tp_interrupt_t),
-	.bInterval = 1 /* ms */,
-};
-
-static void st_tp_interrupt_send(void)
-{
-	struct st_tp_interrupt_t report;
-
-	memset(&report, 0, sizeof(report));
-
-	if (usb_buffer_index < spi_buffer_index)
-		report.flags |= ST_TP_INT_FRAME_AVAILABLE;
-	memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer),
-			 &report, sizeof(report));
-	/* enable TX */
-	STM32_TOGGLE_EP(USB_EP_ST_TOUCHPAD_INT, EP_TX_MASK, EP_TX_VALID, 0);
-	usb_wake();
-}
-
-static void st_tp_interrupt_tx(void)
-{
-	STM32_USB_EP(USB_EP_ST_TOUCHPAD_INT) &= EP_MASK;
-
-	if (usb_buffer_index < spi_buffer_index)
-		/* pending frames */
-		hook_call_deferred(&st_tp_interrupt_send_data, 0);
-}
-
-static void st_tp_interrupt_event(enum usb_ep_event evt)
-{
-	int ep = USB_EP_ST_TOUCHPAD_INT;
-
-	if (evt == USB_EVENT_RESET) {
-		btable_ep[ep].tx_addr = usb_sram_addr(st_tp_usb_int_buffer);
-		btable_ep[ep].tx_count = sizeof(struct st_tp_interrupt_t);
-
-		STM32_USB_EP(ep) = ((ep << 0) |
-				    EP_TX_VALID |
-				    (3 << 9) /* interrupt EP */ |
-				    EP_RX_DISAB);
-	}
-}
-
-USB_DECLARE_EP(USB_EP_ST_TOUCHPAD_INT, st_tp_interrupt_tx, st_tp_interrupt_tx,
-	       st_tp_interrupt_event);
-
-#endif
-
-/* Debugging commands */
-static int command_touchpad_st(int argc, char **argv)
-{
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-	if (strcasecmp(argv[1], "version") == 0) {
-		st_tp_read_system_info(1);
-		return EC_SUCCESS;
-	} else if (strcasecmp(argv[1], "calibrate") == 0) {
-		st_tp_panel_init(1);
-		return EC_SUCCESS;
-	} else if (strcasecmp(argv[1], "enable") == 0) {
-#ifdef CONFIG_USB_ISOCHRONOUS
-		set_bits(&system_state, SYSTEM_STATE_DEBUG_MODE,
-			 SYSTEM_STATE_DEBUG_MODE);
-		hook_call_deferred(&st_tp_enable_heat_map_data, 0);
-		return 0;
-#else
-		return EC_ERROR_NOT_HANDLED;
-#endif
-	} else if (strcasecmp(argv[1], "disable") == 0) {
-#ifdef CONFIG_USB_ISOCHRONOUS
-		set_bits(&system_state, 0, SYSTEM_STATE_DEBUG_MODE);
-		hook_call_deferred(&st_tp_disable_heat_map_data, 0);
-		return 0;
-#else
-		return EC_ERROR_NOT_HANDLED;
-#endif
-	} else if (strcasecmp(argv[1], "dump") == 0) {
-		enable_deep_sleep(0);
-		dump_error();
-		dump_memory();
-		enable_deep_sleep(1);
-		return EC_SUCCESS;
-	} else if (strcasecmp(argv[1], "memory_dump") == 0) {
-		if (argc == 3 && !parse_bool(argv[2], &dump_memory_on_error))
-			return EC_ERROR_PARAM2;
-
-		ccprintf("memory_dump: %d\n", dump_memory_on_error);
-		return EC_SUCCESS;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-}
-DECLARE_CONSOLE_COMMAND(touchpad_st, command_touchpad_st,
-			"<enable | disable | version | calibrate | dump | "
-			"memory_dump <enable|disable>>",
-			"Read write spi. id is spi_devices array index");
diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h
deleted file mode 100644
index a6534f278f..0000000000
--- a/driver/touchpad_st.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TOUCHPAD_ST_H
-#define __CROS_EC_TOUCHPAD_ST_H
-
-#include <stdint.h>
-
-#include "common.h"
-
-#define ST_VENDOR_ID		0x0483
-
-#define ST_TP_EXTRA_BYTE	1
-
-#define ST_TP_CMD_READ_ALL_EVENTS		0x87
-#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT	0xA0
-#define ST_TP_CMD_WRITE_FEATURE_SELECT		0xA2
-#define ST_TP_CMD_WRITE_SYSTEM_COMMAND		0xA4
-#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY	0xA6
-#define ST_TP_CMD_READ_HOST_DATA_MEMORY		0xA7
-#define ST_TP_CMD_WRITE_FW_CONFIG		0xA8
-#define ST_TP_CMD_READ_FW_CONFIG		0xA9
-#define ST_TP_CMD_SPI_HOST_BUFFER_ACK		0xC0
-#define ST_TP_CMD_READ_SPI_HOST_BUFFER		0xC1
-
-#define ST_TP_CMD_WRITE_HW_REG			0xFA
-#define ST_TP_CMD_READ_HW_REG			0xFB
-
-/* Max number of bytes that the DMA can burn on the flash in one shot in FTI */
-#define ST_TP_FLASH_BUFFER_SIZE		(64 * 1024)
-/* Max number of bytes that can be written in I2C to the DMA */
-#define ST_TP_DMA_CHUNK_SIZE		32
-
-#define ST_HOST_BUFFER_DATA_VALID	BIT(0)
-#define ST_HOST_BUFFER_MT_READY		BIT(3)
-#define ST_HOST_BUFFER_SF_READY		BIT(4)
-#define ST_HOST_BUFFER_SS_READY		BIT(5)
-
-#define ST_TP_SCAN_MODE_ACTIVE		0x00
-#define ST_TP_SCAN_MODE_LOW_POWER	0x01
-#define ST_TP_SCAN_MODE_TUNING_WIZARD	0x02
-#define ST_TP_SCAN_MODE_LOCKED		0x03
-
-#define ST_TOUCH_ROWS		(18)  /* force len */
-#define ST_TOUCH_COLS		(25)  /* sense len */
-
-#define ST_TOUCH_HEADER_SIZE	32
-
-#define BYTES_PER_PIXEL		1
-/* Number of bits per pixel, this value is decided by experiments. */
-#define BITS_PER_PIXEL		8
-
-#define ST_TOUCH_FRAME_SIZE	(ST_TOUCH_ROWS * ST_TOUCH_COLS * \
-				 BYTES_PER_PIXEL)
-#define ST_TOUCH_FORCE_SIZE	(ST_TOUCH_ROWS * BYTES_PER_PIXEL)
-#define ST_TOUCH_SENSE_SIZE	(ST_TOUCH_COLS * BYTES_PER_PIXEL)
-
-#define ST_TP_MEM_ID_SYSTEM_INFO	0x01
-
-#define ST_TP_FLASH_OFFSET_CODE		(0x0000 << 2)
-#define ST_TP_FLASH_OFFSET_PANEL_CFG	(0x6800 << 2)
-#define ST_TP_FLASH_OFFSET_CX		(0x7000 << 2)
-#define ST_TP_FLASH_OFFSET_CONFIG	(0x7C00 << 2)
-
-
-struct st_tp_host_data_header_t {
-#define ST_TP_HEADER_MAGIC	0xA5
-	uint8_t magic;  /* this should always be ST_TP_HEADER_MAGIC */
-	uint8_t host_data_mem_id;
-	uint16_t count;
-} __packed;
-
-/* Compute offset of end of a member in given type */
-#define endof(type, member) (offsetof(type, member) + \
-			     sizeof(((type *)NULL)->member))
-
-struct st_tp_system_info_t {
-	/* Part 1, basic info */
-	struct st_tp_host_data_header_t header;
-	uint16_t api_ver_rev;
-	uint8_t api_ver_minor;
-	uint8_t api_ver_major;
-	uint16_t chip0_ver;
-	uint8_t chip0_id[2];  /* should be 0x3936 */
-	uint16_t chip1_ver;
-	uint16_t chip1_id;
-	uint16_t fw_ver;
-	uint16_t svn_rev;
-	uint16_t cfg_ver;
-	uint16_t cfg_project_id;
-	uint16_t cx_ver;
-	uint16_t cx_project_id;
-	uint8_t cfg_afe_ver;
-	uint8_t cx_afe_ver;
-	uint8_t panel_cfg_afe_ver;
-	uint8_t protocol;
-	uint8_t die_id[16];
-	uint64_t release_info; /* unsigned little endian 64 bit integer */
-	uint32_t fw_crc;
-	uint32_t cfg_crc;
-#define ST_TP_SYSTEM_INFO_PART_1_SIZE endof(struct st_tp_system_info_t, cfg_crc)
-#define ST_TP_SYSTEM_INFO_PART_1_RESERVED	16
-
-	uint16_t scr_res_x;
-	uint16_t scr_res_y;
-	uint8_t scr_tx_len;
-	uint8_t scr_rx_len;
-	uint8_t key_len;
-	uint8_t frc_len;
-#define ST_TP_SYSTEM_INFO_PART_2_SIZE (endof(struct st_tp_system_info_t, \
-					     frc_len) - \
-				       offsetof(struct st_tp_system_info_t, \
-						scr_res_x))
-#define ST_TP_SYSTEM_INFO_PART_2_RESERVED	40
-
-#if 0  /* the following parts are defined in spec, but not currently used. */
-
-	uint16_t dbg_frame_addr;
-#define ST_TP_SYSTEM_INFO_PART_3_SIZE (endof(struct st_tp_system_info_t, \
-					     dbg_frame_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						dbg_frame_addr))
-#define ST_TP_SYSTEM_INFO_PART_3_RESERVED	6
-
-	uint16_t ms_scr_raw_addr;
-	uint16_t ms_scr_filter_addr;
-	uint16_t ms_scr_str_addr;
-	uint16_t ms_scr_bl_addr;
-	uint16_t ss_tch_tx_raw_addr;
-	uint16_t ss_tch_tx_filter_addr;
-	uint16_t ss_tch_tx_str_addr;
-	uint16_t ss_tch_tx_bl_addr;
-	uint16_t ss_tch_rx_raw_addr;
-	uint16_t ss_tch_rx_filter_addr;
-	uint16_t ss_tch_rx_str_addr;
-	uint16_t ss_tch_rx_bl_addr;
-	uint16_t key_raw_addr;
-	uint16_t key_filter_addr;
-	uint16_t key_str_addr;
-	uint16_t key_bl_addr;
-	uint16_t frc_raw_addr;
-	uint16_t frc_filter_addr;
-	uint16_t frc_str_addr;
-	uint16_t frc_bl_addr;
-	uint16_t ss_hvr_tx_raw_addr;
-	uint16_t ss_hvr_tx_filter_addr;
-	uint16_t ss_hvr_tx_str_addr;
-	uint16_t ss_hvr_tx_bl_addr;
-	uint16_t ss_hvr_rx_raw_addr;
-	uint16_t ss_hvr_rx_filter_addr;
-	uint16_t ss_hvr_rx_str_addr;
-	uint16_t ss_hvr_rx_bl_addr;
-	uint16_t ss_prx_tx_raw_addr;
-	uint16_t ss_prx_tx_filter_addr;
-	uint16_t ss_prx_tx_str_addr;
-	uint16_t ss_prx_tx_bl_addr;
-	uint16_t ss_prx_rx_raw_addr;
-	uint16_t ss_prx_rx_filter_addr;
-	uint16_t ss_prx_rx_str_addr;
-	uint16_t ss_prx_rx_bl_addr;
-#define ST_TP_SYSTEM_INFO_PART_4_SIZE (endof(struct st_tp_system_info_t, \
-					     ss_prx_rx_bl_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						ms_scr_raw_addr))
-#endif  /* if 0 */
-} __packed;
-
-#define ST_TP_SYSTEM_INFO_LEN	(sizeof(struct st_tp_system_info_t) + \
-				 ST_TP_SYSTEM_INFO_PART_1_RESERVED)
-
-struct st_tp_host_buffer_header_t {
-#define ST_TP_BUFFER_HEADER_DATA_VALID		BIT(0)
-#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY	BIT(1)
-#define ST_TP_BUFFER_HEADER_SYS_FAULT		BIT(2)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY	BIT(3)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY	BIT(4)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY	BIT(5)
-#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL	BIT(6)
-	uint8_t flags;
-	uint8_t reserved[3];
-	uint8_t heatmap_miss_count;
-	uint8_t event_count;
-	uint8_t event_miss_count;
-} __packed;
-
-struct st_tp_host_buffer_heat_map_t {
-	uint8_t frame[ST_TOUCH_FRAME_SIZE];
-#if 0  /* we are not using these now */
-	uint8_t force[ST_TOUCH_FORCE_SIZE];
-	uint8_t sense[ST_TOUCH_SENSE_SIZE];
-#endif
-} __packed;
-
-struct st_tp_event_t {
-#define ST_TP_EVENT_MAGIC		0x3
-	unsigned magic:2;  /* should always be 0x3 */
-	unsigned major_high:2;
-#define ST_TP_EVENT_ID_CONTROLLER_READY	0x0
-#define ST_TP_EVENT_ID_ENTER_POINTER	0x1
-#define ST_TP_EVENT_ID_MOTION_POINTER	0x2
-#define ST_TP_EVENT_ID_LEAVE_POINTER	0x3
-#define ST_TP_EVENT_ID_STATUS_REPORT	0x4
-#define ST_TP_EVENT_ID_USER_REPORT	0x5
-#define ST_TP_EVENT_ID_DEBUG_REPORT	0xe
-#define ST_TP_EVENT_ID_ERROR_REPORT	0xf
-	unsigned evt_id:4;
-
-	union {
-		struct {
-#define ST_TP_TOUCH_TYPE_INVALID	0x0
-#define ST_TP_TOUCH_TYPE_FINGER		0x1
-#define ST_TP_TOUCH_TYPE_GLOVE		0x2
-#define ST_TP_TOUCH_TYPE_STYLUS		0x3
-#define ST_TP_TOUCH_TYPE_PALM		0x4
-			unsigned touch_type:4;
-			unsigned touch_id:4;
-			unsigned y:12;
-			unsigned x:12;
-			uint8_t z;
-			uint8_t minor:4;  // need to be concat with minor_high
-			uint8_t major:4;  // need to be concat with major_high
-		} __packed finger;
-
-		struct {
-#define ST_TP_STATUS_CMD_ECHO	0x1
-#define ST_TP_STATUS_FRAME_DROP	0x3
-#define ST_TP_STATUS_FCAL	0x5
-#define ST_TP_STATUS_BEACON	0x9
-			uint8_t report_type;
-			uint8_t info[4];
-			uint8_t reserved;
-		} __packed report;
-	} __packed ; /* anonymous */
-
-	unsigned minor_high:2;
-	unsigned reserved:1;
-	unsigned evt_left:5;
-} __packed;
-
-struct st_tp_fw_header_t {
-	uint32_t signature;
-	uint32_t ftb_ver;
-	uint32_t chip_id;
-	uint32_t svn_ver;
-	uint32_t fw_ver;
-	uint32_t config_id;
-	uint32_t config_ver;
-	uint8_t reserved[8];
-	uint64_t release_info;
-	uint32_t sec_size[4];
-	uint32_t crc;
-} __packed;
-
-enum ST_TP_MODE {
-	X_Y_MODE = 0,
-	HEAT_MAP_MODE,
-};
-
-#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD		0x00
-#define ST_TP_DEBUG_CMD_CALIBRATE		0x01
-#define ST_TP_DEBUG_CMD_START_SCAN		0x02
-#define ST_TP_DEBUG_CMD_STOP_SCAN		0x03
-#define ST_TP_DEBUG_CMD_READ_BUF_HEADER		0x04
-#define ST_TP_DEBUG_CMD_READ_EVENTS		0x05
-
-#define ST_TP_HEAT_MAP_THRESHOLD 10
-
-/* A minimum version that supports heatmap mode. */
-#define ST_TP_MIN_HEATMAP_VERSION 0x12
-
-#endif /* __CROS_EC_TOUCHPAD_ST_H */
-
diff --git a/driver/usb_mux/amd_fp5.c b/driver/usb_mux/amd_fp5.c
deleted file mode 100644
index b77edf2826..0000000000
--- a/driver/usb_mux/amd_fp5.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMD FP5 USB/DP Mux.
- */
-
-#include "amd_fp5.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "queue.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-static mux_state_t saved_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val)
-{
-	uint8_t buf[3] = { 0 };
-	int rv;
-
-	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      NULL, 0, buf, 3);
-	if (rv)
-		return rv;
-
-	*val = buf[me->usb_port + 1];
-
-	return EC_SUCCESS;
-}
-
-static inline int amd_fp5_mux_write(const struct usb_mux *me, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  me->usb_port, val);
-}
-
-static int amd_fp5_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	uint8_t val = 0;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	saved_mux_state[me->usb_port] = mux_state;
-
-	/*
-	 * This MUX is on the FP5 SoC.  If that device is not powered then
-	 * we either have to complain that it is not powered or if we were
-	 * setting the state to OFF, then go ahead and report that we did
-	 * it because a powered down MUX is off.
-	 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE)
-			? EC_SUCCESS
-			: EC_ERROR_NOT_POWERED;
-
-	if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
-		(mux_state & USB_PD_MUX_DP_ENABLED))
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DOCK_INVERTED : AMD_FP5_MUX_DOCK;
-	else if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_USB_INVERTED : AMD_FP5_MUX_USB;
-	else if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DP_INVERTED : AMD_FP5_MUX_DP;
-
-	return amd_fp5_mux_write(me, val);
-}
-
-static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	uint8_t val = AMD_FP5_MUX_SAFE;
-
-	/*
-	 * This MUX is on the FP5 SoC.  Only access the device if we
-	 * have power.  If that device is not powered then claim the
-	 * state to be NONE, which is SAFE.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
-		int rv;
-
-		rv = amd_fp5_mux_read(me, &val);
-		if (rv)
-			return rv;
-	}
-
-	switch (val) {
-	case AMD_FP5_MUX_USB:
-		*mux_state = USB_PD_MUX_USB_ENABLED;
-		break;
-	case AMD_FP5_MUX_USB_INVERTED:
-		*mux_state = USB_PD_MUX_USB_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
-		break;
-	case AMD_FP5_MUX_DOCK:
-		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED;
-		break;
-	case AMD_FP5_MUX_DOCK_INVERTED:
-		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED
-			     | USB_PD_MUX_POLARITY_INVERTED;
-		break;
-	case AMD_FP5_MUX_DP:
-		*mux_state = USB_PD_MUX_DP_ENABLED;
-		break;
-	case AMD_FP5_MUX_DP_INVERTED:
-		*mux_state = USB_PD_MUX_DP_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
-		break;
-	case AMD_FP5_MUX_SAFE:
-	default:
-		*mux_state = USB_PD_MUX_NONE;
-		break;
-	}
-
-	return EC_SUCCESS;
-}
-
-static struct queue const chipset_reset_queue
-	= QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *);
-
-static void amd_fp5_chipset_reset_delay(void)
-{
-	struct usb_mux *me;
-	int rv;
-	bool unused;
-
-	while (queue_remove_unit(&chipset_reset_queue, &me)) {
-		rv = amd_fp5_set_mux(me, saved_mux_state[me->usb_port],
-				     &unused);
-		if (rv)
-			ccprints("C%d restore mux rv:%d", me->usb_port, rv);
-	}
-}
-DECLARE_DEFERRED(amd_fp5_chipset_reset_delay);
-
-/*
- * The AP's internal USB-C mux is reset when AP resets, so wait for
- * it to be ready and then restore the previous setting.
- */
-static int amd_fp5_chipset_reset(const struct usb_mux *me)
-{
-	queue_add_unit(&chipset_reset_queue, &me);
-	hook_call_deferred(&amd_fp5_chipset_reset_delay_data, 200 * MSEC);
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver amd_fp5_usb_mux_driver = {
-	.init = &amd_fp5_init,
-	.set = &amd_fp5_set_mux,
-	.get = &amd_fp5_get_mux,
-	.chipset_reset = &amd_fp5_chipset_reset,
-};
diff --git a/driver/usb_mux/amd_fp5.h b/driver/usb_mux/amd_fp5.h
deleted file mode 100644
index 7534ea0d8a..0000000000
--- a/driver/usb_mux/amd_fp5.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMD FP5 USB/DP Mux.
- */
-
-#ifndef __CROS_EC_USB_MUX_AMD_FP5_H
-#define __CROS_EC_USB_MUX_AMD_FP5_H
-
-#define AMD_FP5_MUX_I2C_ADDR_FLAGS	0x5C
-
-#define AMD_FP5_MUX_SAFE		0x00
-#define AMD_FP5_MUX_USB			0x02
-#define AMD_FP5_MUX_USB_INVERTED	0x11
-#define AMD_FP5_MUX_DOCK		0x06
-#define AMD_FP5_MUX_DOCK_INVERTED	0x19
-#define AMD_FP5_MUX_DP			0x0C
-#define AMD_FP5_MUX_DP_INVERTED		0x1C
-
-#endif /* __CROS_EC_USB_MUX_AMD_FP5_H */
diff --git a/driver/usb_mux/amd_fp6.c b/driver/usb_mux/amd_fp6.c
deleted file mode 100644
index b2d5ae1fb4..0000000000
--- a/driver/usb_mux/amd_fp6.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMD FP6 USB/DP Mux.
- */
-
-#include "amd_fp6.h"
-#include "chipset.h"
-#include "common.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "queue.h"
-#include "timer.h"
-#include "usb_mux.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/*
- * The recommendation from "3.3.2 Command Timeout" is 250ms,
- * however empirical testing found that a 100ms timeout is sufficient.
- */
-#define WRITE_CMD_TIMEOUT_MS 100
-
-/* Command retry interval */
-#define CMD_RETRY_INTERVAL_MS 1000
-
-/*
- * Local data structure for saving mux state so it can be restored after
- * an AP reset.
- */
-static struct {
-	const struct usb_mux *mux;
-	uint8_t val;
-	bool write_pending;
-} saved_mux_state[USBC_PORT_COUNT];
-
-static int amd_fp6_mux_port0_read(const struct usb_mux *me, uint8_t *val)
-{
-	uint8_t payload[3] = { 0 };
-	bool mux_ready;
-
-	RETURN_ERROR(i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0,
-			      payload, 3));
-
-	/*
-	 * payload[0]: Status/ID
-	 * payload[1]: Port 0 Control/Status
-	 * payload[2]: Port 1 Control/Status (unused on FP6)
-	 */
-	mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET)
-						& AMD_FP6_MUX_PD_STATUS_READY);
-
-	if (!mux_ready)
-		return EC_ERROR_BUSY;
-	*val = payload[1];
-
-	return EC_SUCCESS;
-}
-
-static int amd_fp6_mux_port0_write(const struct usb_mux *me, uint8_t write_val)
-{
-	uint8_t read_val;
-	uint8_t port_status;
-	timestamp_t start;
-
-	/* Check if mux is ready */
-	RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val));
-
-	/* Write control register */
-	RETURN_ERROR(
-		i2c_write8(me->i2c_port, me->i2c_addr_flags, 0, write_val));
-
-	/*
-	 * Read status until write command finishes or times out.
-	 * The mux has an internal opaque timeout, which we wrap with our own
-	 * timeout to be safe.
-	 */
-	start = get_time();
-	while (time_since32(start) < WRITE_CMD_TIMEOUT_MS * MSEC) {
-
-		RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val));
-		port_status = read_val >> AMD_FP6_MUX_PORT_STATUS_OFFSET;
-
-		if (port_status == AMD_FP6_MUX_PORT_CMD_COMPLETE)
-			return EC_SUCCESS;
-		else if (port_status == AMD_FP6_MUX_PORT_CMD_TIMEOUT)
-			return EC_ERROR_TIMEOUT;
-		else if (port_status == AMD_FP6_MUX_PORT_CMD_BUSY)
-			msleep(5);
-		else
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_ERROR_TIMEOUT;
-}
-
-/*
- * Keep trying to write the saved mux state until successful or SOC leaves
- * S0 power state.
- */
-static void amd_fp6_set_mux_retry(void);
-DECLARE_DEFERRED(amd_fp6_set_mux_retry);
-static void amd_fp6_set_mux_retry(void)
-{
-	int rv;
-	bool try_again = false;
-
-	/*
-	 * Mux can only be written in S0, stop trying.
-	 * Will try again on chipset_resume.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return;
-
-	for (int i = 0; i < ARRAY_SIZE(saved_mux_state); i++) {
-		/* Make sure mux_state is initialized */
-		if (saved_mux_state[i].mux == NULL ||
-		    !saved_mux_state[i].write_pending)
-			continue;
-
-		rv = amd_fp6_mux_port0_write(saved_mux_state[i].mux,
-					     saved_mux_state[i].val);
-
-		if (rv)
-			try_again = true;
-		else
-			saved_mux_state[i].write_pending = false;
-	}
-	if (try_again)
-		hook_call_deferred(&amd_fp6_set_mux_retry_data,
-				   CMD_RETRY_INTERVAL_MS * MSEC);
-}
-
-
-static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	uint8_t val;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state == USB_PD_MUX_NONE)
-		/*
-		 * LOW_POWER must be set when connection mode is
-		 * set to 00b (safe state)
-		 */
-		val = AMD_FP6_MUX_MODE_SAFE | AMD_FP6_MUX_LOW_POWER;
-	else if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
-		 (mux_state & USB_PD_MUX_DP_ENABLED))
-		val = AMD_FP6_MUX_MODE_DOCK;
-	else if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val = AMD_FP6_MUX_MODE_USB;
-	else if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val = AMD_FP6_MUX_MODE_DP;
-	else {
-		CPRINTSUSB("C%d: unhandled mux_state %x\n", me->usb_port,
-			   mux_state);
-		return EC_ERROR_INVAL;
-	}
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		val |= AMD_FP6_MUX_ORIENTATION;
-
-	saved_mux_state[me->usb_port].mux = me;
-	saved_mux_state[me->usb_port].val = val;
-
-	/* Mux is not powered in Z1 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
-
-	saved_mux_state[me->usb_port].write_pending = true;
-	amd_fp6_set_mux_retry();
-
-	return EC_SUCCESS;
-}
-
-static int amd_fp6_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	uint8_t val;
-	bool inverted;
-	uint8_t mode;
-
-	/* Mux is not powered in Z1 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return USB_PD_MUX_NONE;
-
-	RETURN_ERROR(amd_fp6_mux_port0_read(me, &val));
-
-	mode = (val & AMD_FP6_MUX_MODE_MASK);
-	inverted = !!(val & AMD_FP6_MUX_ORIENTATION);
-
-	if (mode == AMD_FP6_MUX_MODE_USB)
-		*mux_state = USB_PD_MUX_USB_ENABLED;
-	else if (mode == AMD_FP6_MUX_MODE_DP)
-		*mux_state = USB_PD_MUX_DP_ENABLED;
-	else if (mode == AMD_FP6_MUX_MODE_DOCK)
-		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED;
-	else /* AMD_FP6_MUX_MODE_SAFE */
-		*mux_state = USB_PD_MUX_NONE;
-
-	if (inverted)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-/*
- * The FP6 USB Mux will not be ready for writing until *sometime* after S0.
- */
-static void amd_fp6_chipset_resume(void)
-{
-	for (int i = 0; i < ARRAY_SIZE(saved_mux_state); i++)
-		saved_mux_state[i].write_pending = true;
-	hook_call_deferred(&amd_fp6_set_mux_retry_data,
-			   CMD_RETRY_INTERVAL_MS * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, amd_fp6_chipset_resume, HOOK_PRIO_DEFAULT);
-
-static int amd_fp6_chipset_reset(const struct usb_mux *me)
-{
-	amd_fp6_chipset_resume();
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver amd_fp6_usb_mux_driver = {
-	.set = &amd_fp6_set_mux,
-	.get = &amd_fp6_get_mux,
-	.chipset_reset = &amd_fp6_chipset_reset
-};
diff --git a/driver/usb_mux/amd_fp6.h b/driver/usb_mux/amd_fp6.h
deleted file mode 100644
index 913903e4c4..0000000000
--- a/driver/usb_mux/amd_fp6.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMD FP6 USB/DP Mux.
- */
-
-#ifndef __CROS_EC_USB_MUX_AMD_FP6_H
-#define __CROS_EC_USB_MUX_AMD_FP6_H
-
-#define AMD_FP6_C0_MUX_I2C_ADDR		0x5C
-#define AMD_FP6_C4_MUX_I2C_ADDR		0x52
-
-#define AMD_FP6_MUX_MODE_SAFE		0x0
-#define AMD_FP6_MUX_MODE_USB		0x1
-#define AMD_FP6_MUX_MODE_DP		0x2
-#define AMD_FP6_MUX_MODE_DOCK		0x3
-#define AMD_FP6_MUX_MODE_MASK		GENMASK(1, 0)
-
-#define AMD_FP6_MUX_ORIENTATION		BIT(4)
-#define AMD_FP6_MUX_LOW_POWER		BIT(5)
-
-#define AMD_FP6_MUX_PORT_STATUS_OFFSET	6
-#define AMD_FP6_MUX_PORT_CMD_BUSY	0x0
-#define AMD_FP6_MUX_PORT_CMD_COMPLETE	0x1
-#define AMD_FP6_MUX_PORT_CMD_TIMEOUT	0x2
-
-#define AMD_FP6_MUX_PD_STATUS_READY	BIT(5)
-#define AMD_FP6_MUX_PD_STATUS_OFFSET	1
-
-#endif /* __CROS_EC_USB_MUX_AMD_FP6_H */
diff --git a/driver/usb_mux/anx3443.c b/driver/usb_mux/anx3443.c
deleted file mode 100644
index 2e57f4d30c..0000000000
--- a/driver/usb_mux/anx3443.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ANX3443: 10G Active Mux (6x4) with
- * Integrated Re-timers for USB3.2/DisplayPort
- */
-
-#include "anx3443.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "time.h"
-#include "usb_mux.h"
-#include "util.h"
-
-/*
- * Empirical testing found it takes ~12ms to wake mux.
- * Setting timeout to 20ms for some buffer.
- */
-#define ANX3443_I2C_WAKE_TIMEOUT_MS 20
-#define ANX3443_I2C_WAKE_RETRY_DELAY_US 500
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static inline int anx3443_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static inline int anx3443_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static int anx3443_power_off(const struct usb_mux *me)
-{
-	/*
-	 * The mux will not send an acknowledgment when powered off, so ignore
-	 * response and always return success.
-	 */
-	anx3443_write(me, ANX3443_REG_POWER_CNTRL, ANX3443_POWER_CNTRL_OFF);
-	return EC_SUCCESS;
-}
-
-static int anx3443_wake_up(const struct usb_mux *me)
-{
-	timestamp_t start;
-	int rv;
-	int val;
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Keep reading top register until mux wakes up or timesout */
-	start = get_time();
-	do {
-		rv = anx3443_read(me, 0x0, &val);
-		if (!rv)
-			break;
-		usleep(ANX3443_I2C_WAKE_RETRY_DELAY_US);
-	} while (time_since32(start) < ANX3443_I2C_WAKE_TIMEOUT_MS * MSEC);
-	if (rv) {
-		CPRINTS("ANX3443: Failed to wake mux rv:%d", rv);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	/* ULTRA_LOW_POWER must always be disabled (Fig 2-2) */
-	RETURN_ERROR(anx3443_write(me, ANX3443_REG_ULTRA_LOW_POWER,
-				   ANX3443_ULTRA_LOW_POWER_DIS));
-
-	return EC_SUCCESS;
-}
-
-static int anx3443_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int reg;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/* Mux is not powered in Z1 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
-
-	/* To disable both DP and USB the mux must be powered off. */
-	if (!(mux_state & (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)))
-		return anx3443_power_off(me);
-
-	RETURN_ERROR(anx3443_wake_up(me));
-
-	/* ULP_CFG_MODE_EN overrides pin control. Always set it */
-	reg = ANX3443_ULP_CFG_MODE_EN;
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= ANX3443_ULP_CFG_MODE_USB_EN;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= ANX3443_ULP_CFG_MODE_DP_EN;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= ANX3443_ULP_CFG_MODE_FLIP;
-
-	return anx3443_write(me, ANX3443_REG_ULP_CFG_MODE, reg);
-}
-
-static int anx3443_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg;
-
-	/* Mux is not powered in Z1 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return USB_PD_MUX_NONE;
-
-	RETURN_ERROR(anx3443_wake_up(me));
-
-	*mux_state = 0;
-	RETURN_ERROR(anx3443_read(me, ANX3443_REG_ULP_CFG_MODE, &reg));
-
-	if (reg & ANX3443_ULP_CFG_MODE_USB_EN)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & ANX3443_ULP_CFG_MODE_DP_EN)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & ANX3443_ULP_CFG_MODE_FLIP)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-static int anx3443_init(const struct usb_mux *me)
-{
-	uint64_t now;
-	bool unused;
-
-	/*
-	 * ANX3443 requires 30ms to power on. EC and ANX3443 are on the same
-	 * power rail, so just wait 30ms since EC boot.
-	 */
-	now = get_time().val;
-	if (now < ANX3443_I2C_READY_DELAY)
-		usleep(ANX3443_I2C_READY_DELAY - now);
-
-	RETURN_ERROR(anx3443_wake_up(me));
-
-	/*
-	 * Note that bypassing the usb_mux API is okay for internal driver calls
-	 * since the task calling init already holds this port's mux lock.
-	 */
-	/* Default to USB mode */
-	RETURN_ERROR(anx3443_set_mux(me, USB_PD_MUX_USB_ENABLED, &unused));
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver anx3443_usb_mux_driver = {
-	.init = anx3443_init,
-	.set = anx3443_set_mux,
-	.get = anx3443_get_mux,
-};
diff --git a/driver/usb_mux/anx3443.h b/driver/usb_mux/anx3443.h
deleted file mode 100644
index b505f993ea..0000000000
--- a/driver/usb_mux/anx3443.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ANX3443: 10G Active Mux (6x4) with
- * Integrated Re-timers for USB3.2/DisplayPort
- */
-
-#ifndef __CROS_EC_USB_MUX_ANX3443_H
-#define __CROS_EC_USB_MUX_ANX3443_H
-
-#define ANX3443_I2C_READY_DELAY		(30 * MSEC)
-
-/* I2C interface addresses */
-#define ANX3443_I2C_ADDR0_FLAGS		0x10
-#define ANX3443_I2C_ADDR1_FLAGS		0x14
-#define ANX3443_I2C_ADDR2_FLAGS		0x16
-#define ANX3443_I2C_ADDR3_FLAGS		0x11
-
-/* This register is not documented in datasheet. */
-#define ANX3443_REG_POWER_CNTRL		0x2B
-#define ANX3443_POWER_CNTRL_OFF		0xFF
-
-
-/* Ultra low power control register  */
-#define ANX3443_REG_ULTRA_LOW_POWER	0xE6
-#define ANX3443_ULTRA_LOW_POWER_EN	0x06
-#define ANX3443_ULTRA_LOW_POWER_DIS	0x00
-
-/* Mux control register  */
-#define ANX3443_REG_ULP_CFG_MODE	0xF8
-#define ANX3443_ULP_CFG_MODE_EN		BIT(4)
-#define ANX3443_ULP_CFG_MODE_SWAP	BIT(3)
-#define ANX3443_ULP_CFG_MODE_FLIP	BIT(2)
-#define ANX3443_ULP_CFG_MODE_DP_EN	BIT(1)
-#define ANX3443_ULP_CFG_MODE_USB_EN	BIT(0)
-
-extern const struct usb_mux_driver anx3443_usb_mux_driver;
-
-#endif /* __CROS_EC_USB_MUX_ANX3443_H */
diff --git a/driver/usb_mux/anx7440.c b/driver/usb_mux/anx7440.c
deleted file mode 100644
index 89e593217d..0000000000
--- a/driver/usb_mux/anx7440.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Analogix ANX7440 USB Type-C Active mux with
- * Integrated Re-timers for USB3.1/DisplayPort.
- */
-
-#include "anx7440.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "usb_mux.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static inline int anx7440_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static inline int anx7440_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-struct anx7440_id_t {
-	uint8_t val;
-	uint8_t reg;
-};
-
-static const struct anx7440_id_t anx7440_device_ids[] = {
-	{ ANX7440_VENDOR_ID_L, ANX7440_REG_VENDOR_ID_L },
-	{ ANX7440_VENDOR_ID_H, ANX7440_REG_VENDOR_ID_H },
-	{ ANX7440_DEVICE_ID_L, ANX7440_REG_DEVICE_ID_L },
-	{ ANX7440_DEVICE_ID_H, ANX7440_REG_DEVICE_ID_H },
-	{ ANX7440_DEVICE_VERSION, ANX7440_REG_DEVICE_VERSION },
-};
-
-static int anx7440_init(const struct usb_mux *me)
-{
-	int i;
-	int val;
-	int res;
-
-	/* Verify device id / version registers */
-	for (i = 0; i < ARRAY_SIZE(anx7440_device_ids); i++) {
-		res = anx7440_read(me, anx7440_device_ids[i].reg, &val);
-		if (res)
-			return res;
-
-		if (val != anx7440_device_ids[i].val)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/* Writes control register to set switch mode */
-static int anx7440_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int reg, res;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	res = anx7440_read(me, ANX7440_REG_CHIP_CTRL, &reg);
-	if (res)
-		return res;
-
-	reg &= ~ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR;
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= ANX7440_CHIP_CTRL_SW_OP_MODE_USB;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= ANX7440_CHIP_CTRL_SW_OP_MODE_DP;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= ANX7440_CHIP_CTRL_SW_FLIP;
-
-	return anx7440_write(me, ANX7440_REG_CHIP_CTRL, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int anx7440_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg, res;
-
-	*mux_state = 0;
-	res = anx7440_read(me, ANX7440_REG_CHIP_CTRL, &reg);
-	if (res)
-		return res;
-
-	if (reg & ANX7440_CHIP_CTRL_OP_MODE_FINAL_USB)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & ANX7440_CHIP_CTRL_FINAL_FLIP)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver anx7440_usb_mux_driver = {
-	.init = anx7440_init,
-	.set = anx7440_set_mux,
-	.get = anx7440_get_mux,
-	/* TODO(b/146683781): add low power mode */
-};
diff --git a/driver/usb_mux/anx7440.h b/driver/usb_mux/anx7440.h
deleted file mode 100644
index 2147e3146a..0000000000
--- a/driver/usb_mux/anx7440.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Analogix ANX7440 USB Type-C Active mux with
- * Integrated Re-timers for USB3.1/DisplayPort.
- */
-
-#ifndef __CROS_EC_USB_MUX_ANX7440_H
-#define __CROS_EC_USB_MUX_ANX7440_H
-
-/* I2C interface address */
-#define ANX7440_I2C_ADDR1_FLAGS 0x10
-#define ANX7440_I2C_ADDR2_FLAGS 0x12
-#define I2C_ADDR_USB_MUX0_FLAGS ANX7440_I2C_ADDR1_FLAGS
-#define I2C_ADDR_USB_MUX1_FLAGS ANX7440_I2C_ADDR2_FLAGS
-
-/* Vendor / Device Id registers and expected fused values */
-#define ANX7440_REG_VENDOR_ID_L    0x00
-#define ANX7440_VENDOR_ID_L        0xaa
-#define ANX7440_REG_VENDOR_ID_H    0x01
-#define ANX7440_VENDOR_ID_H        0xaa
-#define ANX7440_REG_DEVICE_ID_L    0x02
-#define ANX7440_DEVICE_ID_L        0x40
-#define ANX7440_REG_DEVICE_ID_H    0x03
-#define ANX7440_DEVICE_ID_H        0x74
-#define ANX7440_REG_DEVICE_VERSION 0x04
-#define ANX7440_DEVICE_VERSION     0xCB
-
-/* Chip control register for checking mux state */
-#define ANX7440_REG_CHIP_CTRL               0x05
-#define ANX7440_CHIP_CTRL_FINAL_FLIP        BIT(6)
-#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP  BIT(5)
-#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_USB BIT(4)
-#define ANX7440_CHIP_CTRL_SW_FLIP           BIT(2)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP     BIT(1)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB    BIT(0)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR  0x7
-
-#endif /* __CROS_EC_USB_MUX_ANX7440_H */
diff --git a/driver/usb_mux/anx7451.c b/driver/usb_mux/anx7451.c
deleted file mode 100644
index 42fdb1f078..0000000000
--- a/driver/usb_mux/anx7451.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ANX7451: 10G Active Mux (4x4) with
- * Integrated Re-timers for USB3.2/DisplayPort
- */
-
-#include "anx7451.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "time.h"
-#include "usb_mux.h"
-#include "util.h"
-
-/*
- * Empirical testing found it takes ~12ms to wake mux.
- * Setting timeout to 20ms for some buffer.
- */
-#define ANX7451_I2C_WAKE_TIMEOUT_MS 20
-#define ANX7451_I2C_WAKE_RETRY_DELAY_US 500
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static inline int anx7451_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static inline int anx7451_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static int anx7451_power_off(const struct usb_mux *me)
-{
-	/*
-	 * The mux will not send an acknowledgment when powered off, so ignore
-	 * response and always return success.
-	 */
-	anx7451_write(me, ANX7451_REG_POWER_CNTRL, ANX7451_POWER_CNTRL_OFF);
-	return EC_SUCCESS;
-}
-
-static int anx7451_wake_up(const struct usb_mux *me)
-{
-	timestamp_t start;
-	int rv;
-	int val;
-	uint16_t usb_i2c_addr = board_anx7451_get_usb_i2c_addr(me);
-
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* Keep reading top register until mux wakes up or timesout */
-	start = get_time();
-	do {
-		rv = anx7451_read(me, 0x0, &val);
-		if (!rv)
-			break;
-		usleep(ANX7451_I2C_WAKE_RETRY_DELAY_US);
-	} while (time_since32(start) < ANX7451_I2C_WAKE_TIMEOUT_MS * MSEC);
-	if (rv) {
-		CPRINTS("ANX7451: Failed to wake mux rv:%d", rv);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	/* ULTRA_LOW_POWER must always be disabled (Fig 2-2) */
-	RETURN_ERROR(anx7451_write(me, ANX7451_REG_ULTRA_LOW_POWER,
-				   ANX7451_ULTRA_LOW_POWER_DIS));
-
-	/*
-	 * Configure ANX7451 USB I2C address.
-	 * Shift 1 bit to make 7 bit address an 8 bit address.
-	 */
-	RETURN_ERROR(
-		anx7451_write(me, ANX7451_REG_USB_I2C_ADDR, usb_i2c_addr << 1));
-
-	/* b/185276137: Fix ANX7451 upstream AUX FLIP */
-	RETURN_ERROR(i2c_write8(me->i2c_port, usb_i2c_addr,
-				ANX7451_REG_USB_AUX_FLIP_CTRL,
-				ANX7451_USB_AUX_FLIP_EN));
-
-	return EC_SUCCESS;
-}
-
-static int anx7451_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int reg;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	/*
-	 * Mux is not powered in Z1, and will start up in USB mode.  Ensure any
-	 * mux sets when off get run again so we don't leave the retimer on with
-	 * the None mode set
-	 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return EC_ERROR_NOT_POWERED;
-
-	/* To disable both DP and USB the mux must be powered off. */
-	if (!(mux_state & (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)))
-		return anx7451_power_off(me);
-
-	RETURN_ERROR(anx7451_wake_up(me));
-
-	/* ULP_CFG_MODE_EN overrides pin control. Always set it */
-	reg = ANX7451_ULP_CFG_MODE_EN;
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= ANX7451_ULP_CFG_MODE_USB_EN;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= ANX7451_ULP_CFG_MODE_DP_EN;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= ANX7451_ULP_CFG_MODE_FLIP;
-
-	return anx7451_write(me, ANX7451_REG_ULP_CFG_MODE, reg);
-}
-
-static int anx7451_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg;
-
-	/* Mux is not powered in Z1 */
-	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return USB_PD_MUX_NONE;
-
-	RETURN_ERROR(anx7451_wake_up(me));
-
-	*mux_state = 0;
-	RETURN_ERROR(anx7451_read(me, ANX7451_REG_ULP_CFG_MODE, &reg));
-
-	if (reg & ANX7451_ULP_CFG_MODE_USB_EN)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & ANX7451_ULP_CFG_MODE_DP_EN)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & ANX7451_ULP_CFG_MODE_FLIP)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver anx7451_usb_mux_driver = {
-	.set = anx7451_set_mux,
-	.get = anx7451_get_mux,
-	/* Low power mode is not supported on ANX7451 */
-};
diff --git a/driver/usb_mux/anx7451.h b/driver/usb_mux/anx7451.h
deleted file mode 100644
index 7eefb6e79e..0000000000
--- a/driver/usb_mux/anx7451.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ANX7451: 10G Active Mux (4x4) with
- * Integrated Re-timers for USB3.2/DisplayPort
- */
-
-#ifndef __CROS_EC_USB_MUX_ANX7451_H
-#define __CROS_EC_USB_MUX_ANX7451_H
-
-#include "usb_mux.h"
-
-/* I2C interface addresses */
-#define ANX7451_I2C_ADDR0_FLAGS		0x10
-#define ANX7451_I2C_ADDR1_FLAGS		0x14
-#define ANX7451_I2C_ADDR2_FLAGS		0x16
-#define ANX7451_I2C_ADDR3_FLAGS		0x11
-
-/* This register is not documented in datasheet. */
-#define ANX7451_REG_POWER_CNTRL		0x2B
-#define ANX7451_POWER_CNTRL_OFF		0xFF
-
-/*
- * Ultra low power control register.
- * On ANX7451, this register should always be 0 (disabled).
- * See figure 2-2 in family programming guide.
- */
-#define ANX7451_REG_ULTRA_LOW_POWER	0xE6
-/* #define ANX7451_ULTRA_LOW_POWER_EN	0x06 */
-#define ANX7451_ULTRA_LOW_POWER_DIS	0x00
-
-/* Mux control register  */
-#define ANX7451_REG_ULP_CFG_MODE	0xF8
-#define ANX7451_ULP_CFG_MODE_EN		BIT(4)
-#define ANX7451_ULP_CFG_MODE_SWAP	BIT(3)
-#define ANX7451_ULP_CFG_MODE_FLIP	BIT(2)
-#define ANX7451_ULP_CFG_MODE_DP_EN	BIT(1)
-#define ANX7451_ULP_CFG_MODE_USB_EN	BIT(0)
-
-/* Register to set USB I2C address, defaults to 0x29 (7-bit) */
-#define ANX7451_REG_USB_I2C_ADDR	0x38
-
-/* ANX7451 AUX FLIP control */
-#define ANX7451_REG_USB_AUX_FLIP_CTRL	0xA4
-#define ANX7451_USB_AUX_FLIP_EN		0x20
-
-extern const struct usb_mux_driver anx7451_usb_mux_driver;
-
-/*
- * ANX7451 uses a separate i2c address for USB configuration registers.
- * This address is not controlled by address straps and defaults to 0x29.
- * This address may conflict with other ANX74* parts. Implement
- * board_anx7451_get_usb_i2c_addr to set a non-conflicting 7-bit address.
- */
-uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me);
-
-#endif /* __CROS_EC_USB_MUX_ANX7451_H */
diff --git a/driver/usb_mux/it5205.c b/driver/usb_mux/it5205.c
deleted file mode 100644
index 0cfecdeda0..0000000000
--- a/driver/usb_mux/it5205.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ITE IT5205 Type-C USB alternate mode mux.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "it5205.h"
-#include "util.h"
-
-#define MUX_STATE_DP_USB_MASK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
-
-static int it5205_read(const struct usb_mux *me, uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static int it5205_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
-}
-
-static int it5205h_sbu_update(const struct usb_mux *me, uint8_t reg,
-			      uint8_t mask, enum mask_update_action action)
-{
-	return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-			   reg, mask, action);
-}
-
-static int it5205h_sbu_field_update(const struct usb_mux *me, uint8_t reg,
-				    uint8_t field_mask, uint8_t set_value)
-{
-	return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-				 reg, field_mask, set_value);
-}
-
-struct mux_chip_id_t {
-	uint8_t chip_id;
-	uint8_t reg;
-};
-
-static const struct mux_chip_id_t mux_chip_id_verify[] = {
-	{ '5', IT5205_REG_CHIP_ID3},
-	{ '2', IT5205_REG_CHIP_ID2},
-	{ '0', IT5205_REG_CHIP_ID1},
-	{ '5', IT5205_REG_CHIP_ID0},
-};
-
-static int it5205_init(const struct usb_mux *me)
-{
-	int i, val, ret;
-
-	/* bit[0]: mux power on, bit[7-1]: reserved. */
-	ret = it5205_write(me, IT5205_REG_MUXPDR, 0);
-	if (ret)
-		return ret;
-	/*  Verify chip ID registers. */
-	for (i = 0; i < ARRAY_SIZE(mux_chip_id_verify); i++) {
-		ret = it5205_read(me, mux_chip_id_verify[i].reg, &val);
-		if (ret)
-			return ret;
-
-		if (val != mux_chip_id_verify[i].chip_id)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	if (IS_ENABLED(CONFIG_USB_MUX_IT5205H_SBU_OVP)) {
-		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_VSR,
-				IT5205H_VREF_SELECT_MASK,
-				IT5205H_VREF_SELECT_3_3V));
-
-		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_CSBUOVPSR,
-				IT5205H_OVP_SELECT_MASK,
-				IT5205H_OVP_3_68V));
-
-		RETURN_ERROR(it5205h_sbu_update(me, IT5205H_REG_ISR,
-				IT5205H_ISR_CSBU_MASK, MASK_CLR));
-
-		RETURN_ERROR(it5205h_enable_csbu_switch(me, true));
-	}
-
-	return EC_SUCCESS;
-}
-
-enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me, bool en)
-{
-	return it5205h_sbu_update(me, IT5205H_REG_CSBUSR,
-			IT5205H_CSBUSR_SWITCH, en ? MASK_SET : MASK_CLR);
-}
-
-/* Writes control register to set switch mode */
-static int it5205_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	uint8_t reg;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	switch (mux_state & MUX_STATE_DP_USB_MASK) {
-	case USB_PD_MUX_USB_ENABLED:
-		reg = IT5205_USB;
-		break;
-	case USB_PD_MUX_DP_ENABLED:
-		reg = IT5205_DP;
-		break;
-	case MUX_STATE_DP_USB_MASK:
-		reg = IT5205_DP_USB;
-		break;
-	default:
-		reg = 0;
-		break;
-	}
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= IT5205_POLARITY_INVERTED;
-
-	return it5205_write(me, IT5205_REG_MUXCR, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int it5205_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg, ret;
-
-	ret = it5205_read(me, IT5205_REG_MUXCR, &reg);
-	if (ret)
-		return ret;
-
-	switch (reg & IT5205_DP_USB_CTRL_MASK) {
-	case IT5205_USB:
-		*mux_state = USB_PD_MUX_USB_ENABLED;
-		break;
-	case IT5205_DP:
-		*mux_state = USB_PD_MUX_DP_ENABLED;
-		break;
-	case IT5205_DP_USB:
-		*mux_state = MUX_STATE_DP_USB_MASK;
-		break;
-	default:
-		*mux_state = 0;
-		break;
-	}
-
-	if (reg & IT5205_POLARITY_INVERTED)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-static int it5205_enter_low_power_mode(const struct usb_mux *me)
-{
-	int rv;
-
-	/* Turn off all switches */
-	rv = it5205_write(me, IT5205_REG_MUXCR, 0);
-
-	if (rv)
-		return rv;
-
-	/* Power down mux */
-	return it5205_write(me, IT5205_REG_MUXPDR, IT5205_MUX_POWER_DOWN);
-}
-
-const struct usb_mux_driver it5205_usb_mux_driver = {
-	.init = &it5205_init,
-	.set = &it5205_set_mux,
-	.get = &it5205_get_mux,
-	.enter_low_power_mode = &it5205_enter_low_power_mode,
-};
diff --git a/driver/usb_mux/it5205.h b/driver/usb_mux/it5205.h
deleted file mode 100644
index 0fb9f009f6..0000000000
--- a/driver/usb_mux/it5205.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ITE IT5205 Type-C USB alternate mode mux.
- */
-
-#ifndef __CROS_EC_IT5205_H
-#define __CROS_EC_IT5205_H
-
-#include "stdbool.h"
-#include "usb_mux.h"
-#include "usb_mux/it5205_public.h"
-
-/* Chip ID registers */
-#define IT5205_REG_CHIP_ID3 0x4
-#define IT5205_REG_CHIP_ID2 0x5
-#define IT5205_REG_CHIP_ID1 0x6
-#define IT5205_REG_CHIP_ID0 0x7
-
-/* MUX power down register */
-#define IT5205_REG_MUXPDR        0x10
-#define IT5205_MUX_POWER_DOWN    BIT(0)
-
-/* MUX control register */
-#define IT5205_REG_MUXCR         0x11
-#define IT5205_POLARITY_INVERTED BIT(4)
-
-#define IT5205_DP_USB_CTRL_MASK  0x0f
-#define IT5205_DP                0x0f
-#define IT5205_DP_USB            0x03
-#define IT5205_USB               0x07
-
-
-/* IT5205-H SBU module */
-
-/* I2C address for SBU switch control */
-#define IT5205H_SBU_I2C_ADDR_FLAGS 0x6a
-
-/* Vref Select Register */
-#define IT5205H_REG_VSR            0x10
-#define IT5205H_VREF_SELECT_MASK   0x30
-#define IT5205H_VREF_SELECT_3_3V   0x00
-#define IT5205H_VREF_SELECT_OFF    0x20
-
-/* CSBU OVP Select Register */
-#define IT5205H_REG_CSBUOVPSR      0x1e
-#define IT5205H_OVP_SELECT_MASK    0x30
-#define IT5205H_OVP_3_90V          0x00
-#define IT5205H_OVP_3_68V          0x10
-#define IT5205H_OVP_3_62V          0x20
-#define IT5205H_OVP_3_57V          0x30
-
-/* CSBU Switch Register */
-#define IT5205H_REG_CSBUSR         0x22
-#define IT5205H_CSBUSR_SWITCH      BIT(0)
-
-/* Interrupt Switch Register */
-#define IT5205H_REG_ISR            0x25
-#define IT5205H_ISR_CSBU_MASK      BIT(4)
-#define IT5205H_ISR_CSBU_OVP       BIT(0)
-
-enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me,
-					      bool en);
-
-#endif /* __CROS_EC_IT5205_H */
diff --git a/driver/usb_mux/pi3usb3x532.c b/driver/usb_mux/pi3usb3x532.c
deleted file mode 100644
index 2435157967..0000000000
--- a/driver/usb_mux/pi3usb3x532.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Pericom PI3USB3X532 USB port switch driver.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "pi3usb3x532.h"
-#include "usb_mux.h"
-#include "util.h"
-
-static int pi3usb3x532_read(const struct usb_mux *me,
-			    uint8_t reg, uint8_t *val)
-{
-	int read, res;
-
-	/*
-	 * First byte read will be i2c address (ignored).
-	 * Second byte read will be vendor ID.
-	 * Third byte read will be selection control.
-	 */
-	res = i2c_read16(me->i2c_port, me->i2c_addr_flags, 0, &read);
-	if (res)
-		return res;
-
-	if (reg == PI3USB3X532_REG_VENDOR)
-		*val = read & 0xff;
-	else /* reg == PI3USB3X532_REG_CONTROL */
-		*val = (read >> 8) & 0xff;
-
-	return EC_SUCCESS;
-}
-
-static int pi3usb3x532_write(const struct usb_mux *me,
-			     uint8_t reg, uint8_t val)
-{
-	if (reg != PI3USB3X532_REG_CONTROL)
-		return EC_ERROR_UNKNOWN;
-
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags, 0, val);
-}
-
-int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val)
-{
-	int res;
-	uint8_t read;
-
-	res = pi3usb3x532_read(me, PI3USB3X532_REG_VENDOR, &read);
-	if (res)
-		return res;
-
-	*val = read;
-
-	return EC_SUCCESS;
-}
-
-static int pi3usb3x532_reset(const struct usb_mux *me)
-{
-	return pi3usb3x532_write(
-		me,
-		PI3USB3X532_REG_CONTROL,
-		(PI3USB3X532_MODE_POWERDOWN & PI3USB3X532_CTRL_MASK) |
-		PI3USB3X532_CTRL_RSVD);
-}
-
-static int pi3usb3x532_init(const struct usb_mux *me)
-{
-	uint8_t val;
-	int res;
-
-	res = pi3usb3x532_reset(me);
-	if (res)
-		return res;
-	res = pi3usb3x532_read(me, PI3USB3X532_REG_VENDOR, &val);
-	if (res)
-		return res;
-	if (val != PI3USB3X532_VENDOR_ID)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Writes control register to set switch mode */
-static int pi3usb3x532_set_mux(const struct usb_mux *me,
-			       mux_state_t mux_state,
-			       bool *ack_required)
-{
-	uint8_t reg = 0;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= PI3USB3X532_MODE_USB;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= PI3USB3X532_MODE_DP;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= PI3USB3X532_BIT_SWAP;
-
-	return pi3usb3x532_write(me, PI3USB3X532_REG_CONTROL,
-				 reg | PI3USB3X532_CTRL_RSVD);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int pi3usb3x532_get_mux(const struct usb_mux *me,
-			       mux_state_t *mux_state)
-{
-	uint8_t reg = 0;
-	uint8_t res;
-
-	*mux_state = 0;
-	res = pi3usb3x532_read(me, PI3USB3X532_REG_CONTROL, &reg);
-	if (res)
-		return res;
-
-	if (reg & PI3USB3X532_MODE_USB)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & PI3USB3X532_MODE_DP)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & PI3USB3X532_BIT_SWAP)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver pi3usb3x532_usb_mux_driver = {
-	.init = pi3usb3x532_init,
-	.set = pi3usb3x532_set_mux,
-	.get = pi3usb3x532_get_mux,
-};
diff --git a/driver/usb_mux/pi3usb3x532.h b/driver/usb_mux/pi3usb3x532.h
deleted file mode 100644
index 6b398fdace..0000000000
--- a/driver/usb_mux/pi3usb3x532.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Pericom PI3USB3X532 USB port switch driver.
- *
- * Supported switches:
- * - PI3USB30532
- * - PI3USB31532
- */
-
-#ifndef __CROS_EC_PI3USB3X532_H
-#define __CROS_EC_PI3USB3X532_H
-
-#include "usb_pd.h"
-#include "usb_mux.h"
-
-/* I2C Addresses */
-#define PI3USB3X532_I2C_ADDR0 0x54
-#define PI3USB3X532_I2C_ADDR1 0x55
-#define PI3USB3X532_I2C_ADDR2 0x56
-#define PI3USB3X532_I2C_ADDR3 0x57
-
-/* USB switch registers */
-#define PI3USB3X532_REG_ADDR 0x00
-#define PI3USB3X532_REG_VENDOR 0x01
-#define PI3USB3X532_REG_CONTROL 0x02
-/* Control register field */
-#define PI3USB3X532_CTRL_MASK 0x7
-#define PI3USB3X532_CTRL_RSVD 0
-/* Switch vendor ID  */
-#define PI3USB3X532_VENDOR_ID 0
-
-/* PI3USB3X532 control flags */
-#define PI3USB3X532_BIT_SWAP BIT(0)
-#define PI3USB3X532_BIT_DP BIT(1)
-#define PI3USB3X532_BIT_USB BIT(2)
-
-/* PI3USB3X532 modes */
-/* Power down, switch open */
-#define PI3USB3X532_MODE_POWERDOWN 0
-/* Keep power on, switch open */
-#define PI3USB3X532_MODE_POWERON 1
-/* 4-lane DP 1.2
- * dp0~3 : rx2, tx2, tx1, rx1
- * hpd+/-: rfu1, rfu2
- */
-#define PI3USB3X532_MODE_DP PI3USB3X532_BIT_DP
-/* 4-lane DP 1.2 swap
- * dp0~3 : rx1, tx1, tx2, rx2
- * hpd+/-: rfu2, rfu1
- */
-#define PI3USB3X532_MODE_DP_SWAP (PI3USB3X532_MODE_DP | PI3USB3X532_BIT_SWAP)
-/* USB3
- * tx/rx : tx1, rx1
- */
-#define PI3USB3X532_MODE_USB PI3USB3X532_BIT_USB
-/* USB3 swap
- * tx/rx : tx2, rx2
- */
-#define PI3USB3X532_MODE_USB_SWAP (PI3USB3X532_MODE_USB | PI3USB3X532_BIT_SWAP)
-/* 2-lane DP 1.2 + USB3
- * tx/rx : tx1, rx1
- * dp0~1 : rx2, tx2
- * hpd+/-: rfu1, rfu2
- */
-#define PI3USB3X532_MODE_DP_USB (PI3USB3X532_BIT_DP | PI3USB3X532_BIT_USB)
-/* 2-lane DP 1.2 + USB3, swap
- * tx/rx : tx2, rx2
- * dp0-1 : rx1, tx1
- * hpd+/-: rfu2, rfu1
- */
-#define PI3USB3X532_MODE_DP_USB_SWAP (PI3USB3X532_MODE_DP_USB | \
-				      PI3USB3X532_BIT_SWAP)
-
-/* Get Vendor ID */
-int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val);
-#endif /* __CROS_EC_PI3USB3X532_H */
diff --git a/driver/usb_mux/ps8740.c b/driver/usb_mux/ps8740.c
deleted file mode 100644
index 618c74cd65..0000000000
--- a/driver/usb_mux/ps8740.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8740 (and PS8742)
- * USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "ps8740.h"
-#include "usb_mux.h"
-#include "util.h"
-
-int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
-}
-
-int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
-}
-
-static int ps8740_init(const struct usb_mux *me)
-{
-	int id1;
-	int id2;
-	int res;
-
-	/* Reset chip back to power-on state */
-	res = ps8740_write(me, PS8740_REG_MODE, PS8740_MODE_POWER_DOWN);
-	if (res)
-		return res;
-
-	/*
-	 * Verify chip ID registers.
-	 */
-	res = ps8740_read(me, PS8740_REG_CHIP_ID1, &id1);
-	if (res)
-		return res;
-
-	res  = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2);
-	if (res)
-		return res;
-
-	if (id1 != PS8740_CHIP_ID1 || id2 != PS8740_CHIP_ID2)
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Verify revision ID registers.
-	 */
-	res = ps8740_read(me, PS8740_REG_REVISION_ID1, &id1);
-	if (res)
-		return res;
-
-	res = ps8740_read(me, PS8740_REG_REVISION_ID2, &id2);
-	if (res)
-		return res;
-
-	if (id1 != PS8740_REVISION_ID1)
-		return EC_ERROR_UNKNOWN;
-	/* PS8740 may have REVISION_ID2 as 0xa or 0xb */
-	if (id2 != PS8740_REVISION_ID2_0 && id2 != PS8740_REVISION_ID2_1)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Writes control register to set switch mode */
-static int ps8740_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	uint8_t reg = 0;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= PS8740_MODE_USB_ENABLED;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= PS8740_MODE_DP_ENABLED;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= PS8740_MODE_POLARITY_INVERTED;
-
-	return ps8740_write(me, PS8740_REG_MODE, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int ps8740_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg;
-	int res;
-
-	res = ps8740_read(me, PS8740_REG_STATUS, &reg);
-	if (res)
-		return res;
-
-	*mux_state = 0;
-	if (reg & PS8740_STATUS_USB_ENABLED)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & PS8740_STATUS_DP_ENABLED)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & PS8740_STATUS_POLARITY_INVERTED)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-/* Tune USB Tx/Rx Equalization */
-int ps8740_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx)
-{
-	int ret;
-
-	ret = ps8740_write(me, PS8740_REG_USB_EQ_TX, tx);
-	ret |= ps8740_write(me, PS8740_REG_USB_EQ_RX, rx);
-
-	return ret;
-}
-
-const struct usb_mux_driver ps8740_usb_mux_driver = {
-	.init = ps8740_init,
-	.set = ps8740_set_mux,
-	.get = ps8740_get_mux,
-};
diff --git a/driver/usb_mux/ps8740.h b/driver/usb_mux/ps8740.h
deleted file mode 100644
index 3a669b5ad9..0000000000
--- a/driver/usb_mux/ps8740.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8740 (and PS8742)
- * USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#ifndef __CROS_EC_PS8740_H
-#define __CROS_EC_PS8740_H
-
-#include "usb_mux.h"
-
-#define PS8740_I2C_ADDR0_FLAG    0x10
-#define PS8740_I2C_ADDR1_FLAG    0x11
-#define PS8740_I2C_ADDR2_FLAG    0x19
-#define PS8740_I2C_ADDR3_FLAG    0x1a
-
-/* Mode register for setting mux */
-#define PS8740_REG_MODE 0x00
-#define PS8740_MODE_POLARITY_INVERTED BIT(4)
-#define PS8740_MODE_USB_ENABLED       BIT(5)
-#define PS8740_MODE_DP_ENABLED        BIT(6)
-#ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_MODE_POWER_DOWN        BIT(7)
-#elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_MODE_CE_DP_ENABLED     BIT(7)
-	/* To reset the state machine to default */
-	#define PS8740_MODE_POWER_DOWN        0
-#endif
-
-/* Status register for checking mux state */
-#define PS8740_REG_STATUS 0x09
-#define PS8740_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8740_STATUS_USB_ENABLED       BIT(3)
-#define PS8740_STATUS_DP_ENABLED        BIT(4)
-#define PS8740_STATUS_HPD_ASSERTED      BIT(7)
-
-/* Chip ID / revision registers and expected fused values */
-#define PS8740_REG_REVISION_ID1 0xf0
-#define PS8740_REG_REVISION_ID2 0xf1
-#define PS8740_REG_CHIP_ID1     0xf2
-#define PS8740_REG_CHIP_ID2     0xf3
-#ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_REVISION_ID1   0x00
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0b
-	#define PS8740_CHIP_ID1       0x40
-#elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_REVISION_ID1   0x01
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0a
-	#define PS8740_CHIP_ID1       0x42
-#endif
-#define PS8740_CHIP_ID2         0x87
-
-/* USB equalization settings for Host to Mux */
-#define PS8740_REG_USB_EQ_TX     0x32
-#define PS8740_USB_EQ_TX_10_1_DB 0x00
-#define PS8740_USB_EQ_TX_14_3_DB 0x20
-#define PS8740_USB_EQ_TX_8_5_DB  0x40
-#define PS8740_USB_EQ_TX_6_5_DB  0x60
-#define PS8740_USB_EQ_TX_11_5_DB 0x80
-#define PS8740_USB_EQ_TX_9_5_DB  0xc0
-#define PS8740_USB_EQ_TX_7_5_DB  0xe0
-#define PS8740_USB_EQ_TERM_100_OHM (0 << 2)
-#define PS8740_USB_EQ_TERM_85_OHM  BIT(2)
-
-/* USB equalization settings for Connector to Mux */
-#define PS8740_REG_USB_EQ_RX     0x3b
-#define PS8740_USB_EQ_RX_4_4_DB  0x00
-#define PS8740_USB_EQ_RX_7_0_DB  0x10
-#define PS8740_USB_EQ_RX_8_2_DB  0x20
-#define PS8740_USB_EQ_RX_9_4_DB  0x30
-#define PS8740_USB_EQ_RX_10_2_DB 0x40
-#define PS8740_USB_EQ_RX_11_4_DB 0x50
-#define PS8740_USB_EQ_RX_14_3_DB 0x60
-#define PS8740_USB_EQ_RX_14_8_DB 0x70
-#define PS8740_USB_EQ_RX_15_2_DB 0x80
-#define PS8740_USB_EQ_RX_15_5_DB 0x90
-#define PS8740_USB_EQ_RX_16_2_DB 0xa0
-#define PS8740_USB_EQ_RX_17_3_DB 0xb0
-#define PS8740_USB_EQ_RX_18_4_DB 0xc0
-#define PS8740_USB_EQ_RX_20_1_DB 0xd0
-#define PS8740_USB_EQ_RX_21_3_DB 0xe0
-
-int ps8740_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx);
-int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
-int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val);
-
-#endif /* __CROS_EC_PS8740_H */
diff --git a/driver/usb_mux/ps8743.c b/driver/usb_mux/ps8743.c
deleted file mode 100644
index f618bb009f..0000000000
--- a/driver/usb_mux/ps8743.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "ps8743.h"
-#include "usb_mux.h"
-#include "util.h"
-
-int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
-}
-
-int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
-}
-
-int ps8743_check_chip_id(const struct usb_mux *me, int *val)
-{
-	int id1;
-	int id2;
-	int res;
-
-	/*
-	 * Verify chip ID registers.
-	 */
-	res = ps8743_read(me, PS8743_REG_CHIP_ID1, &id1);
-	if (res)
-		return res;
-
-	res  = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
-	if (res)
-		return res;
-
-	*val = (id2 << 8) + id1;
-
-	return EC_SUCCESS;
-}
-
-static int ps8743_init(const struct usb_mux *me)
-{
-	int id1;
-	int id2;
-	int res;
-
-	/* Reset chip back to power-on state */
-	res = ps8743_write(me, PS8743_REG_MODE, PS8743_MODE_POWER_DOWN);
-	if (res)
-		return res;
-
-	/*
-	 * Verify chip ID registers.
-	 */
-	res = ps8743_read(me, PS8743_REG_CHIP_ID1, &id1);
-	if (res)
-		return res;
-
-	res  = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
-	if (res)
-		return res;
-
-	if (id1 != PS8743_CHIP_ID1 || id2 != PS8743_CHIP_ID2)
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Verify revision ID registers.
-	 */
-	res = ps8743_read(me, PS8743_REG_REVISION_ID1, &id1);
-	if (res)
-		return res;
-
-	res = ps8743_read(me, PS8743_REG_REVISION_ID2, &id2);
-	if (res)
-		return res;
-
-	/*
-	 * From Parade: PS8743 may have REVISION_ID1 as 0 or 1
-	 * Rev 1 is derived from Rev 0 and have same functionality.
-	 */
-	if (id1 != PS8743_REVISION_ID1_0 && id1 != PS8743_REVISION_ID1_1)
-		return EC_ERROR_UNKNOWN;
-	if (id2 != PS8743_REVISION_ID2)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Writes control register to set switch mode */
-static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	/*
-	 * For CE_DP, CE_USB, and FLIP, disable pin control and enable I2C
-	 * control.
-	 */
-	uint8_t reg = (PS8743_MODE_IN_HPD_CONTROL |
-		       PS8743_MODE_DP_REG_CONTROL |
-		       PS8743_MODE_USB_REG_CONTROL |
-		       PS8743_MODE_FLIP_REG_CONTROL);
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= PS8743_MODE_USB_ENABLE;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= PS8743_MODE_DP_ENABLE | PS8743_MODE_IN_HPD_ASSERT;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= PS8743_MODE_FLIP_ENABLE;
-
-	return ps8743_write(me, PS8743_REG_MODE, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int ps8743_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg;
-	int res;
-
-	res = ps8743_read(me, PS8743_REG_STATUS, &reg);
-	if (res)
-		return res;
-
-	*mux_state = 0;
-	if (reg & PS8743_STATUS_USB_ENABLED)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & PS8743_STATUS_DP_ENABLED)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & PS8743_STATUS_POLARITY_INVERTED)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-/* Tune USB Tx/Rx Equalization */
-int ps8743_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx)
-{
-	int ret;
-
-	ret = ps8743_write(me, PS8743_REG_USB_EQ_TX, tx);
-	ret |= ps8743_write(me, PS8743_REG_USB_EQ_RX, rx);
-
-	return ret;
-}
-
-const struct usb_mux_driver ps8743_usb_mux_driver = {
-	.init = ps8743_init,
-	.set = ps8743_set_mux,
-	.get = ps8743_get_mux,
-};
diff --git a/driver/usb_mux/ps8743.h b/driver/usb_mux/ps8743.h
deleted file mode 100644
index 741b93e98a..0000000000
--- a/driver/usb_mux/ps8743.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#ifndef __CROS_EC_PS8743_H
-#define __CROS_EC_PS8743_H
-
-#include "usb_mux.h"
-#include "usb_mux/ps8743_public.h"
-
-/* Status register for checking mux state */
-#define PS8743_REG_STATUS 0x09
-#define PS8743_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8743_STATUS_USB_ENABLED       BIT(3)
-#define PS8743_STATUS_DP_ENABLED        BIT(4)
-#define PS8743_STATUS_HPD_ASSERTED      BIT(7)
-
-/* Chip ID / revision registers and expected fused values */
-#define PS8743_REG_REVISION_ID1 0xf0
-#define PS8743_REG_REVISION_ID2 0xf1
-#define PS8743_REG_CHIP_ID1     0xf2
-#define PS8743_REG_CHIP_ID2     0xf3
-#define PS8743_REVISION_ID1_0   0x00
-#define PS8743_REVISION_ID1_1   0x01
-#define PS8743_REVISION_ID2     0x0b
-#define PS8743_CHIP_ID1         0x41
-#define PS8743_CHIP_ID2         0x87
-
-#endif /* __CROS_EC_PS8743_H */
diff --git a/driver/usb_mux/ps8822.c b/driver/usb_mux/ps8822.c
deleted file mode 100644
index 7f25db37f4..0000000000
--- a/driver/usb_mux/ps8822.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8822
- * USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#include "common.h"
-#include "i2c.h"
-#include "ps8822.h"
-#include "usb_mux.h"
-#include "util.h"
-
-static int ps8822_read(const struct usb_mux *me, int page, uint8_t reg,
-		       int *val)
-{
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags + page,
-			 reg, val);
-}
-
-static int ps8822_write(const struct usb_mux *me, int page, uint8_t reg,
-			int val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags + page,
-			reg, val);
-}
-
-int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db)
-{
-	int dpeq_reg;
-	int rv;
-
-	/* Read DP EQ register */
-	rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ,
-			 &dpeq_reg);
-	if (rv)
-		return rv;
-
-	if (db < PS8822_DPEQ_LEVEL_UP_9DB || db > PS8822_DPEQ_LEVEL_UP_21DB)
-		return EC_ERROR_INVAL;
-
-	/* Disable auto eq */
-	dpeq_reg &= ~PS8822_DP_EQ_AUTO_EN;
-
-	/* Set gain to the requested value */
-	dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK <<
-		      PS8822_REG_DP_EQ_SHIFT);
-	dpeq_reg |= (db << PS8822_REG_DP_EQ_SHIFT);
-
-	/* Apply new EQ setting */
-	return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ,
-			  dpeq_reg);
-}
-
-static int ps8822_init(const struct usb_mux *me)
-{
-	char id[PS8822_ID_LEN + 1];
-	int reg;
-	int i;
-	int rv = 0;
-
-	/* Read ID registers */
-	for (i = 0; i < PS8822_ID_LEN; i++) {
-		rv |= ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_DEV_ID1 + i,
-				  &reg);
-		if (!rv)
-			id[i] = reg;
-	}
-
-	if (!rv) {
-		id[PS8822_ID_LEN] = '\0';
-		/* Set mode register to default value */
-		rv = ps8822_write(me, PS8822_REG_PAGE0, PS8822_REG_MODE, 0);
-		rv |= strcasecmp("PS8822", id);
-	}
-
-	return rv;
-}
-
-/* Writes control register to set switch mode */
-static int ps8822_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			  bool *ack_required)
-{
-	int reg;
-	int rv;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	rv = ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_MODE, &reg);
-	if (rv)
-		return rv;
-
-	/* Assume standby, preserve PIN_E config bit */
-	reg &= ~(PS8822_MODE_ALT_DP_EN | PS8822_MODE_USB_EN | PS8822_MODE_FLIP);
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= PS8822_MODE_USB_EN;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= PS8822_MODE_ALT_DP_EN;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= PS8822_MODE_FLIP;
-
-	return ps8822_write(me, PS8822_REG_PAGE0, PS8822_REG_MODE, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int ps8822_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int reg;
-	int res;
-
-	res = ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_MODE, &reg);
-	if (res)
-		return res;
-
-	*mux_state = 0;
-	if (reg & PS8822_MODE_USB_EN)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & PS8822_MODE_ALT_DP_EN)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & PS8822_MODE_FLIP)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-
-const struct usb_mux_driver ps8822_usb_mux_driver = {
-	.init = ps8822_init,
-	.set = ps8822_set_mux,
-	.get = ps8822_get_mux,
-};
diff --git a/driver/usb_mux/ps8822.h b/driver/usb_mux/ps8822.h
deleted file mode 100644
index 86b911db70..0000000000
--- a/driver/usb_mux/ps8822.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8822
- * USB Type-C Retiming Switch for USB Device / DisplayPort Sink
- */
-
-#ifndef __CROS_EC_PS8822_H
-#define __CROS_EC_PS8822_H
-
-#include "usb_mux.h"
-
-#define PS8822_I2C_ADDR0_FLAG    0x10
-#define PS8822_I2C_ADDR1_FLAG    0x18
-#define PS8822_I2C_ADDR2_FLAG    0x58
-#define PS8822_I2C_ADDR3_FLAG    0x60
-
-#define PS8822_REG_PAGE0	0x00
-
-/* Mode register for setting mux */
-#define PS8822_REG_MODE         0x01
-#define PS8822_MODE_ALT_DP_EN   BIT(7)
-#define PS8822_MODE_USB_EN      BIT(6)
-#define PS8822_MODE_FLIP        BIT(5)
-#define PS8822_MODE_PIN_E       BIT(4)
-
-#define PS8822_REG_CONFIG       0x02
-#define PS8822_CONFIG_HPD_IN_DIS BIT(7)
-#define PS8822_CONFIG_DP_PLUG    BIT(6)
-
-#define PS8822_REG_DEV_ID1      0x06
-#define PS8822_REG_DEV_ID2      0x07
-#define PS8822_REG_DEV_ID3      0x08
-#define PS8822_REG_DEV_ID4      0x09
-#define PS8822_REG_DEV_ID5      0x0A
-#define PS8822_REG_DEV_ID6      0x0B
-
-#define PS8822_ID_LEN 6
-
-#define PS8822_REG_PAGE1        0x01
-#define PS8822_REG_DP_EQ        0xB6
-#define PS8822_DP_EQ_AUTO_EN    BIT(7)
-
-#define PS8822_DPEQ_LEVEL_UP_9DB    0x00
-#define PS8822_DPEQ_LEVEL_UP_11DB   0x01
-#define PS8822_DPEQ_LEVEL_UP_12DB   0x02
-#define PS8822_DPEQ_LEVEL_UP_14DB   0x03
-#define PS8822_DPEQ_LEVEL_UP_17DB   0x04
-#define PS8822_DPEQ_LEVEL_UP_18DB   0x05
-#define PS8822_DPEQ_LEVEL_UP_19DB   0x06
-#define PS8822_DPEQ_LEVEL_UP_20DB   0x07
-#define PS8822_DPEQ_LEVEL_UP_21DB   0x08
-#define PS8822_DPEQ_LEVEL_UP_MASK   0x0F
-#define PS8822_REG_DP_EQ_SHIFT      3
-
-/**
- * Set DP Rx Equalization value
- *
- * @param *me pointer to usb_mux descriptor
- * @param db requested gain setting for DP Rx path
- * @return EC_SUCCESS if db param is valid and I2C is successful
- */
-int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db);
-
-#endif /* __CROS_EC_PS8822_H */
diff --git a/driver/usb_mux/tusb1064.c b/driver/usb_mux/tusb1064.c
deleted file mode 100644
index 1c0f0e4701..0000000000
--- a/driver/usb_mux/tusb1064.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c.h"
-#include "tusb1064.h"
-#include "usb_mux.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/*
- * configuration bits which never change in the General Register
- * e.g. REG_GENERAL_DP_EN_CTRL or REG_GENERAL_EQ_OVERRIDE
- */
-#define REG_GENERAL_STATIC_BITS REG_GENERAL_EQ_OVERRIDE
-
-static int tusb1064_read(const struct usb_mux *me, uint8_t reg, uint8_t *val)
-{
-	int buffer = 0xee;
-	int res = i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			    (int)reg, &buffer);
-	*val = buffer;
-	return res;
-}
-
-static int tusb1064_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
-{
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  (int)reg, (int)val);
-}
-
-/* Writes control register to set switch mode */
-static int tusb1064_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			    bool *ack_required)
-{
-	int reg = REG_GENERAL_STATIC_BITS;
-
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_USB_ENABLED)
-		reg |= REG_GENERAL_CTLSEL_USB3;
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		reg |= REG_GENERAL_CTLSEL_ANYDP;
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		reg |= REG_GENERAL_FLIPSEL;
-
-	return tusb1064_write(me, TUSB1064_REG_GENERAL, reg);
-}
-
-/* Reads control register and updates mux_state accordingly */
-static int tusb1064_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	uint8_t reg;
-	int res;
-
-	res = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
-	if (res)
-		return EC_ERROR_INVAL;
-
-	*mux_state = 0;
-	if (reg & REG_GENERAL_CTLSEL_USB3)
-		*mux_state |= USB_PD_MUX_USB_ENABLED;
-	if (reg & REG_GENERAL_CTLSEL_ANYDP)
-		*mux_state |= USB_PD_MUX_DP_ENABLED;
-	if (reg & REG_GENERAL_FLIPSEL)
-		*mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	return EC_SUCCESS;
-}
-
-/* Generic driver init function */
-static int tusb1064_init(const struct usb_mux *me)
-{
-	int res;
-	uint8_t reg;
-	bool unused;
-
-	/* Default to "Floating Pin" DP Equalization */
-	reg = TUSB1064_DP1EQ(TUSB1064_DP_EQ_RX_10_0_DB) |
-		TUSB1064_DP3EQ(TUSB1064_DP_EQ_RX_10_0_DB);
-	res = tusb1064_write(me, TUSB1064_REG_DP1DP3EQ_SEL, reg);
-	if (res)
-		return res;
-
-	reg = TUSB1064_DP0EQ(TUSB1064_DP_EQ_RX_10_0_DB) |
-		TUSB1064_DP2EQ(TUSB1064_DP_EQ_RX_10_0_DB);
-	res = tusb1064_write(me, TUSB1064_REG_DP0DP2EQ_SEL, reg);
-	if (res)
-		return res;
-
-	/*
-	 * Note that bypassing the usb_mux API is okay for internal driver calls
-	 * since the task calling init already holds this port's mux lock.
-	 */
-	/* Disconnect USB3.1 and DP */
-	res = tusb1064_set_mux(me, USB_PD_MUX_NONE, &unused);
-	if (res)
-		return res;
-
-	/* Disable AUX mux override */
-	res = tusb1064_write(me, TUSB1064_REG_AUXDPCTRL, 0);
-	if (res)
-		return res;
-
-	return EC_SUCCESS;
-}
-
-const struct usb_mux_driver tusb1064_usb_mux_driver = {
-	/* CAUTION: This is an UFP/RX/SINK redriver mux */
-	.init = tusb1064_init,
-	.set = tusb1064_set_mux,
-	.get = tusb1064_get_mux,
-};
diff --git a/driver/usb_mux/tusb1064.h b/driver/usb_mux/tusb1064.h
deleted file mode 100644
index e860cc539a..0000000000
--- a/driver/usb_mux/tusb1064.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TUSB1064_H
-#define __CROS_EC_TUSB1064_H
-
-#include <stdint.h>
-#include "usb_mux.h"
-
-/*
- * TUSB1064 Has 16 possible device addresses which are selected by A1|A0 lines
- * using 4 level inputs.
- *    0 -> tied directly to GND
- *    R -> tied to GND via a 20k pulldown
- *    F -> floating
- *    1 -> tied to VCC
- */
-#define TUSB1064_I2C_ADDR0_FLAGS     0x44
-#define TUSB1064_I2C_ADDR1_FLAGS     0x45
-#define TUSB1064_I2C_ADDR2_FLAGS     0x46
-#define TUSB1064_I2C_ADDR3_FLAGS     0x47
-#define TUSB1064_I2C_ADDR4_FLAGS     0x20
-#define TUSB1064_I2C_ADDR5_FLAGS     0x21
-#define TUSB1064_I2C_ADDR6_FLAGS     0x22
-#define TUSB1064_I2C_ADDR7_FLAGS     0x23
-#define TUSB1064_I2C_ADDR8_FLAGS     0x10
-#define TUSB1064_I2C_ADDR9_FLAGS     0x11
-#define TUSB1064_I2C_ADDR10_FLAGS    0x12
-#define TUSB1064_I2C_ADDR11_FLAGS    0x13
-#define TUSB1064_I2C_ADDR12_FLAGS    0x0C
-#define TUSB1064_I2C_ADDR13_FLAGS    0x0D
-#define TUSB1064_I2C_ADDR14_FLAGS    0x0E
-#define TUSB1064_I2C_ADDR15_FLAGS    0x0F
-
-/* TUSB1064 General Register */
-#define TUSB1064_REG_GENERAL            0x0a
-#define REG_GENERAL_CTLSEL_USB3         BIT(0)
-#define REG_GENERAL_CTLSEL_ANYDP        BIT(1)
-#define REG_GENERAL_FLIPSEL             BIT(2)
-#define REG_GENERAL_DP_EN_CTRL          BIT(3)
-#define REG_GENERAL_EQ_OVERRIDE         BIT(4)
-
-/* AUX and DP Lane Control Register */
-#define TUSB1064_REG_AUXDPCTRL          0x13
-#define TUSB1064_AUXDPCTRL_AUX_SNOOP_DISABLE BIT(7)
-#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR  0x30
-#define TUSB1064_AUXDPCTRL_DP3_DISABLE  BIT(3)
-#define TUSB1064_AUXDPCTRL_DP2_DISABLE  BIT(2)
-#define TUSB1064_AUXDPCTRL_DP1_DISABLE  BIT(1)
-#define TUSB1064_AUXDPCTRL_DP0_DISABLE  BIT(0)
-
-/* Receiver Equalization GPIO Control */
-#define TUSB1064_REG_DP1DP3EQ_SEL 0x10
-#define TUSB1064_REG_DP0DP2EQ_SEL 0x11
-
-/* DP Receiver equalization settings */
-#define TUSB1064_DP_EQ_RX_NEG_0_3_DB 0x0
-#define TUSB1064_DP_EQ_RX_1_6_DB 0x1
-#define TUSB1064_DP_EQ_RX_3_0_DB 0x2
-#define TUSB1064_DP_EQ_RX_4_4_DB 0x3
-#define TUSB1064_DP_EQ_RX_5_4_DB 0x4
-#define TUSB1064_DP_EQ_RX_6_5_DB 0x5
-#define TUSB1064_DP_EQ_RX_7_3_DB 0x6
-#define TUSB1064_DP_EQ_RX_8_1_DB 0x7
-#define TUSB1064_DP_EQ_RX_8_9_DB 0x8
-#define TUSB1064_DP_EQ_RX_9_5_DB 0x9
-#define TUSB1064_DP_EQ_RX_10_0_DB 0xA
-#define TUSB1064_DP_EQ_RX_10_6_DB 0xB
-#define TUSB1064_DP_EQ_RX_11_0_DB 0xC
-#define TUSB1064_DP_EQ_RX_11_4_DB 0xD
-#define TUSB1064_DP_EQ_RX_11_8_DB 0xE
-#define TUSB1064_DP_EQ_RX_12_1_DB 0xF
-
-#ifndef TUSB1064_DP1EQ
-#define TUSB1064_DP1EQ(nr)         ((nr) << 4)
-#endif
-#ifndef TUSB1064_DP3EQ
-#define TUSB1064_DP3EQ(nr)         ((nr) << 0)
-#endif
-#ifndef TUSB1064_DP0EQ
-#define TUSB1064_DP0EQ(nr)         ((nr) << 4)
-#endif
-#ifndef TUSB1064_DP2EQ
-#define TUSB1064_DP2EQ(nr)         ((nr) << 0)
-#endif
-
-
-/* TUSB1064 Receiver Equalization GPIO Control */
-#define TUSB1064_REG_SSRX2RX1EQ_SEL 0x20
-#define TUSB1064_REG_SSTXEQ_SEL 0x21
-
-/* USB equalization settings for Mux DFP (TX) */
-#define TUSB1064_USB_EQ_DFP_NEG_3_0_DB 0x0
-#define TUSB1064_USB_EQ_DFP_NEG_0_8_DB 0x1
-#define TUSB1064_USB_EQ_DFP_NEG_0_7_DB 0x2
-#define TUSB1064_USB_EQ_DFP_2_2_DB 0x3
-#define TUSB1064_USB_EQ_DFP_3_3_DB 0x4
-#define TUSB1064_USB_EQ_DFP_4_3_DB 0x5
-#define TUSB1064_USB_EQ_DFP_5_1_DB 0x6
-#define TUSB1064_USB_EQ_DFP_6_0_DB 0x7
-#define TUSB1064_USB_EQ_DFP_6_7_DB 0x8
-#define TUSB1064_USB_EQ_DFP_7_3_DB 0x9
-#define TUSB1064_USB_EQ_DFP_7_8_DB 0xA
-#define TUSB1064_USB_EQ_DFP_8_3_DB 0xB
-#define TUSB1064_USB_EQ_DFP_8_6_DB 0xC
-#define TUSB1064_USB_EQ_DFP_9_0_DB 0xD
-#define TUSB1064_USB_EQ_DFP_9_3_DB 0xE
-#define TUSB1064_USB_EQ_DFP_9_7_DB 0xF
-
-/* USB equalization settings for Mux UFP (RX) */
-#define TUSB1064_USB_EQ_UFP_NEG_1_5_DB 0x0
-#define TUSB1064_USB_EQ_UFP_0_7_DB 0x1
-#define TUSB1064_USB_EQ_UFP_2_2_DB 0x2
-#define TUSB1064_USB_EQ_UFP_3_7_DB 0x3
-#define TUSB1064_USB_EQ_UFP_4_7_DB 0x4
-#define TUSB1064_USB_EQ_UFP_5_8_DB 0x5
-#define TUSB1064_USB_EQ_UFP_6_6_DB 0x6
-#define TUSB1064_USB_EQ_UFP_7_4_DB 0x7
-#define TUSB1064_USB_EQ_UFP_8_1_DB 0x8
-#define TUSB1064_USB_EQ_UFP_8_7_DB 0x9
-#define TUSB1064_USB_EQ_UFP_9_2_DB 0xA
-#define TUSB1064_USB_EQ_UFP_9_7_DB 0xB
-#define TUSB1064_USB_EQ_UFP_10_0_DB 0xC
-#define TUSB1064_USB_EQ_UFP_10_4_DB 0xD
-#define TUSB1064_USB_EQ_UFP_10_7_DB 0xE
-#define TUSB1064_USB_EQ_UFP_11_1_DB 0xF
-
-#endif /* __CROS_EC_TUSB1064_H */
diff --git a/driver/usb_mux/usb_mux.c b/driver/usb_mux/usb_mux.c
deleted file mode 100644
index 155ba8fb3e..0000000000
--- a/driver/usb_mux/usb_mux.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB mux high-level driver. */
-
-#include "atomic.h"
-#include "common.h"
-#include "console.h"
-#include "chipset.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-#else
-#define CPRINTS(format, args...)
-#define CPRINTF(format, args...)
-#endif
-
-static int enable_debug_prints;
-
-/*
- * Flags will reset to 0 after sysjump; This works for current flags as LPM will
- * get reset in the init method which is called during PD task startup.
- */
-static uint32_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Device is in low power mode. */
-#define USB_MUX_FLAG_IN_LPM		BIT(0)
-
-/* Device initialized at least once */
-#define USB_MUX_FLAG_INIT		BIT(1)
-
-/* Coordinate mux accesses by-port among the tasks */
-static mutex_t mux_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Coordinate which task requires an ACK event */
-static task_id_t ack_task[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID };
-
-enum mux_config_type {
-	USB_MUX_INIT,
-	USB_MUX_LOW_POWER,
-	USB_MUX_SET_MODE,
-	USB_MUX_GET_MODE,
-	USB_MUX_CHIPSET_RESET,
-	USB_MUX_HPD_UPDATE,
-};
-
-#ifdef CONFIG_ZEPHYR
-static int init_mux_mutex(const struct device *dev)
-{
-	int port;
-
-	ARG_UNUSED(dev);
-	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-		k_mutex_init(&mux_lock[port]);
-	return 0;
-}
-SYS_INIT(init_mux_mutex, POST_KERNEL, 50);
-#endif /* CONFIG_ZEPHYR */
-
-/* Configure the MUX */
-static int configure_mux(int port,
-			 enum mux_config_type config,
-			 mux_state_t *mux_state)
-{
-	int rv = EC_SUCCESS;
-	const struct usb_mux *mux_ptr;
-
-	if (config == USB_MUX_SET_MODE ||
-	    config == USB_MUX_GET_MODE) {
-		if (mux_state == NULL)
-			return EC_ERROR_INVAL;
-
-		if (config == USB_MUX_GET_MODE)
-			*mux_state = USB_PD_MUX_NONE;
-	}
-
-	/*
-	 * a MUX for a particular port can be a linked list chain of
-	 * MUXes.  So when we change one, we traverse the whole list
-	 * to make sure they are all updated appropriately.
-	 */
-	for (mux_ptr = &usb_muxes[port];
-	     rv == EC_SUCCESS && mux_ptr != NULL;
-	     mux_ptr = mux_ptr->next_mux) {
-		mux_state_t lcl_state;
-		const struct usb_mux_driver *drv = mux_ptr->driver;
-		bool ack_required = false;
-
-		/* Action time!  Lock this mux */
-		mutex_lock(&mux_lock[port]);
-
-		switch (config) {
-		case USB_MUX_INIT:
-			if (drv && drv->init) {
-				rv = drv->init(mux_ptr);
-				if (rv)
-					break;
-			}
-
-			/* Apply board specific initialization */
-			if (mux_ptr->board_init)
-				rv = mux_ptr->board_init(mux_ptr);
-
-			break;
-
-		case USB_MUX_LOW_POWER:
-			if (drv && drv->enter_low_power_mode)
-				rv = drv->enter_low_power_mode(mux_ptr);
-
-			break;
-
-		case USB_MUX_CHIPSET_RESET:
-			if (drv && drv->chipset_reset)
-				rv = drv->chipset_reset(mux_ptr);
-
-			break;
-
-		case USB_MUX_SET_MODE:
-			lcl_state = *mux_state;
-
-			if (mux_ptr->flags & USB_MUX_FLAG_SET_WITHOUT_FLIP)
-				lcl_state &= ~USB_PD_MUX_POLARITY_INVERTED;
-
-			if (drv && drv->set) {
-				rv = drv->set(mux_ptr, lcl_state,
-					      &ack_required);
-				if (rv)
-					break;
-			}
-
-			if (ack_required)
-				ack_task[port] = task_get_current();
-
-			/* Apply board specific setting */
-			if (mux_ptr->board_set)
-				rv = mux_ptr->board_set(mux_ptr, lcl_state);
-
-			break;
-
-		case USB_MUX_GET_MODE:
-			/*
-			 * This is doing a GET_CC on all of the MUXes in the
-			 * chain and ORing them together. This will make sure
-			 * if one of the MUX values has FLIP turned off that
-			 * we will end up with the correct value in the end.
-			 */
-			if (drv && drv->get) {
-				rv = drv->get(mux_ptr, &lcl_state);
-				if (rv)
-					break;
-				*mux_state |= lcl_state;
-			}
-			break;
-
-		case USB_MUX_HPD_UPDATE:
-			if (mux_ptr->hpd_update)
-				mux_ptr->hpd_update(mux_ptr, *mux_state);
-
-		}
-
-		/* Unlock before any host command waits */
-		mutex_unlock(&mux_lock[port]);
-
-		if (ack_required) {
-			/* This should only be called from the PD task */
-			assert(port == TASK_ID_TO_PD_PORT(task_get_current()));
-
-			/*
-			 * Note: This task event could be generalized for more
-			 * purposes beyond host command ACKs.  For now, these
-			 * wait times are tuned for the purposes of the TCSS
-			 * mux, but could be made configurable for other
-			 * purposes.
-			 */
-			task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100*MSEC);
-			ack_task[port] = TASK_ID_INVALID;
-
-			usleep(12.5 * MSEC);
-		}
-	}
-
-	if (rv)
-		CPRINTS("mux config:%d, port:%d, rv:%d",
-			config, port, rv);
-
-	return rv;
-}
-
-static void enter_low_power_mode(int port)
-{
-	/*
-	 * Set LPM flag regardless of method presence or method failure. We
-	 * want know know that we tried to put the device in low power mode
-	 * so we can re-initialize the device on the next access.
-	 */
-	atomic_or(&flags[port], USB_MUX_FLAG_IN_LPM);
-
-	/* Apply any low power customization if present */
-	configure_mux(port, USB_MUX_LOW_POWER, NULL);
-}
-
-static int exit_low_power_mode(int port)
-{
-	/* If we are in low power, initialize device (which clears LPM flag) */
-	if (flags[port] & USB_MUX_FLAG_IN_LPM)
-		usb_mux_init(port);
-
-	if (!(flags[port] & USB_MUX_FLAG_INIT)) {
-		CPRINTS("C%d: USB_MUX_FLAG_INIT not set", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	if (flags[port] & USB_MUX_FLAG_IN_LPM) {
-		CPRINTS("C%d: USB_MUX_FLAG_IN_LPM not cleared", port);
-		return EC_ERROR_NOT_POWERED;
-	}
-
-	return EC_SUCCESS;
-}
-
-void usb_mux_init(int port)
-{
-	int rv;
-
-	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
-
-	if (port >= board_get_usb_pd_port_count()) {
-		return;
-	}
-
-	rv = configure_mux(port, USB_MUX_INIT, NULL);
-
-	if (rv == EC_SUCCESS)
-		atomic_or(&flags[port], USB_MUX_FLAG_INIT);
-
-	/*
-	 * Mux may fail initialization if it's not powered. Mark this port
-	 * as in LPM mode to try initialization again.
-	 */
-	if (rv == EC_ERROR_NOT_POWERED)
-		atomic_or(&flags[port], USB_MUX_FLAG_IN_LPM);
-	else
-		atomic_clear_bits(&flags[port], USB_MUX_FLAG_IN_LPM);
-}
-
-/*
- * TODO(crbug.com/505480): Setting muxes often involves I2C transcations,
- * which can block. Consider implementing an asynchronous task.
- */
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
-{
-	mux_state_t mux_state;
-	const int should_enter_low_power_mode =
-		(mux_mode == USB_PD_MUX_NONE &&
-		usb_mode == USB_SWITCH_DISCONNECT);
-
-	if (port >= board_get_usb_pd_port_count()) {
-		return;
-	}
-
-	/* Perform initialization if not initialized yet */
-	if (!(flags[port] & USB_MUX_FLAG_INIT))
-		usb_mux_init(port);
-
-	/* Configure USB2.0 */
-	if (IS_ENABLED(CONFIG_USB_CHARGER))
-		usb_charger_set_switches(port, usb_mode);
-
-	/*
-	 * Don't wake device up just to put it back to sleep. Low power mode
-	 * flag is only set if the mux set() operation succeeded previously for
-	 * the same disconnected state.
-	 */
-	if (should_enter_low_power_mode && (flags[port] & USB_MUX_FLAG_IN_LPM))
-		return;
-
-	if (exit_low_power_mode(port) != EC_SUCCESS)
-		return;
-
-	/* Configure superspeed lanes */
-	mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity)
-			? mux_mode | USB_PD_MUX_POLARITY_INVERTED
-			: mux_mode;
-
-	if (configure_mux(port, USB_MUX_SET_MODE, &mux_state))
-		return;
-
-	if (enable_debug_prints)
-		CPRINTS(
-		     "usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)",
-		     port, mux_mode, usb_mode, polarity);
-
-	/*
-	 * If we are completely disconnecting the mux, then we should put it in
-	 * its lowest power state.
-	 */
-	if (should_enter_low_power_mode)
-		enter_low_power_mode(port);
-}
-
-mux_state_t usb_mux_get(int port)
-{
-	mux_state_t mux_state;
-	int rv;
-
-	if (port >= board_get_usb_pd_port_count()) {
-		return USB_PD_MUX_NONE;
-	}
-
-	/* Perform initialization if not initialized yet */
-	if (!(flags[port] & USB_MUX_FLAG_INIT))
-		usb_mux_init(port);
-
-	if (flags[port] & USB_MUX_FLAG_IN_LPM)
-		return USB_PD_MUX_NONE;
-
-	rv = configure_mux(port, USB_MUX_GET_MODE, &mux_state);
-
-	return rv ? USB_PD_MUX_NONE : mux_state;
-}
-
-void usb_mux_flip(int port)
-{
-	mux_state_t mux_state;
-
-	if (port >= board_get_usb_pd_port_count()) {
-		return;
-	}
-
-	/* Perform initialization if not initialized yet */
-	if (!(flags[port] & USB_MUX_FLAG_INIT))
-		usb_mux_init(port);
-
-	if (exit_low_power_mode(port) != EC_SUCCESS)
-		return;
-
-	if (configure_mux(port, USB_MUX_GET_MODE, &mux_state))
-		return;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		mux_state &= ~USB_PD_MUX_POLARITY_INVERTED;
-	else
-		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-
-	configure_mux(port, USB_MUX_SET_MODE, &mux_state);
-}
-
-void usb_mux_hpd_update(int port, mux_state_t hpd_state)
-{
-	if (port >= board_get_usb_pd_port_count()) {
-		return;
-	}
-
-	/* Perform initialization if not initialized yet */
-	if (!(flags[port] & USB_MUX_FLAG_INIT))
-		usb_mux_init(port);
-
-	if (exit_low_power_mode(port) != EC_SUCCESS)
-		return;
-
-	configure_mux(port, USB_MUX_HPD_UPDATE, &hpd_state);
-}
-
-int usb_mux_retimer_fw_update_port_info(void)
-{
-	int i;
-	int port_info = 0;
-	const struct usb_mux *mux_ptr;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		mux_ptr = &usb_muxes[i];
-		while (mux_ptr) {
-			if (mux_ptr->driver &&
-				mux_ptr->driver->is_retimer_fw_update_capable &&
-				mux_ptr->driver->is_retimer_fw_update_capable())
-				port_info |= BIT(i);
-			mux_ptr = mux_ptr->next_mux;
-		}
-	}
-	return port_info;
-}
-
-static void mux_chipset_reset(void)
-{
-	int port;
-
-	for (port = 0; port < board_get_usb_pd_port_count(); ++port)
-		configure_mux(port, USB_MUX_CHIPSET_RESET, NULL);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, mux_chipset_reset, HOOK_PRIO_DEFAULT);
-
-/*
- * For muxes which have powered off in G3, clear any cached INIT and LPM flags
- * since the chip will need reset.
- */
-static void usb_mux_reset_in_g3(void)
-{
-	int port;
-	const struct usb_mux *mux_ptr;
-
-	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		mux_ptr = &usb_muxes[port];
-
-		while (mux_ptr) {
-			if (mux_ptr->flags & USB_MUX_FLAG_RESETS_IN_G3) {
-				atomic_clear_bits(&flags[port],
-						  USB_MUX_FLAG_INIT |
-						  USB_MUX_FLAG_IN_LPM);
-			}
-			mux_ptr = mux_ptr->next_mux;
-		}
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, usb_mux_reset_in_g3, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_CMD_TYPEC
-static int command_typec(int argc, char **argv)
-{
-	const char * const mux_name[] = {"none", "usb", "dp", "dock"};
-	char *e;
-	int port;
-	mux_state_t mux = USB_PD_MUX_NONE;
-	int i;
-
-	if (argc == 2 && !strcasecmp(argv[1], "debug")) {
-		enable_debug_prints = 1;
-		return EC_SUCCESS;
-	}
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	port = strtoi(argv[1], &e, 10);
-	if (*e || port >= board_get_usb_pd_port_count())
-		return EC_ERROR_PARAM1;
-
-	if (argc < 3) {
-		mux_state_t mux_state;
-
-		mux_state = usb_mux_get(port);
-		ccprintf("Port %d: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d "
-			"HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n", port,
-			!!(mux_state & USB_PD_MUX_USB_ENABLED),
-			!!(mux_state & USB_PD_MUX_DP_ENABLED),
-			mux_state & USB_PD_MUX_POLARITY_INVERTED ?
-				"INVERTED" : "NORMAL",
-			!!(mux_state & USB_PD_MUX_HPD_IRQ),
-			!!(mux_state & USB_PD_MUX_HPD_LVL),
-			!!(mux_state & USB_PD_MUX_SAFE_MODE),
-			!!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
-			!!(mux_state & USB_PD_MUX_USB4_ENABLED));
-
-		return EC_SUCCESS;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(mux_name); i++)
-		if (!strcasecmp(argv[2], mux_name[i]))
-			mux = i;
-	usb_mux_set(port, mux, mux == USB_PD_MUX_NONE ?
-				      USB_SWITCH_DISCONNECT :
-				      USB_SWITCH_CONNECT,
-			  polarity_rm_dts(pd_get_polarity(port)));
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(typec, command_typec,
-			"[port|debug] [none|usb|dp|dock]",
-			"Control type-C connector muxing");
-#endif
-
-static enum ec_status hc_usb_pd_mux_info(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_usb_pd_mux_info *p = args->params;
-	struct ec_response_usb_pd_mux_info *r = args->response;
-	int port = p->port;
-	mux_state_t mux_state;
-
-	if (port >= board_get_usb_pd_port_count())
-		return EC_RES_INVALID_PARAM;
-
-	if (configure_mux(port, USB_MUX_GET_MODE, &mux_state))
-		return EC_RES_ERROR;
-
-	r->flags = mux_state;
-
-	/* Clear HPD IRQ event since we're about to inform host of it. */
-	if (IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) &&
-	    (r->flags & USB_PD_MUX_HPD_IRQ)) {
-		usb_mux_hpd_update(port, r->flags & USB_PD_MUX_HPD_LVL);
-	}
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO,
-		     hc_usb_pd_mux_info,
-		     EC_VER_MASK(0));
-
-static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args)
-{
-	__maybe_unused const struct ec_params_usb_pd_mux_ack *p = args->params;
-
-	if (!IS_ENABLED(CONFIG_USB_MUX_AP_ACK_REQUEST))
-		return EC_RES_INVALID_COMMAND;
-
-	if (ack_task[p->port] != TASK_ID_INVALID)
-		task_set_event(ack_task[p->port], PD_EVENT_AP_MUX_DONE);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK,
-		     hc_usb_pd_mux_ack,
-		     EC_VER_MASK(0));
diff --git a/driver/usb_mux/virtual.c b/driver/usb_mux/virtual.c
deleted file mode 100644
index dbece4faf9..0000000000
--- a/driver/usb_mux/virtual.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Virtual USB mux driver for host-controlled USB muxes.
- */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "util.h"
-
-/*
- * USB PD protocol configures the USB & DP mux state and USB PD policy
- * configures the HPD mux state. Both states are independent of each other
- * may differ when the PD role changes when in dock mode.
- */
-#define USB_PD_MUX_HPD_STATE	(USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
-#define USB_PD_MUX_USB_DP_STATE	(USB_PD_MUX_USB_ENABLED | \
-			USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED | \
-			USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
-			USB_PD_MUX_USB4_ENABLED)
-
-static mux_state_t virtual_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static inline void virtual_mux_update_state(int port, mux_state_t mux_state,
-					    bool *ack_required)
-{
-	mux_state_t previous_mux_state = virtual_mux_state[port];
-
-	virtual_mux_state[port] = mux_state;
-
-	/*
-	 * Initialize ack_required to false to start, and set on necessary
-	 * conditions
-	 */
-	*ack_required = false;
-
-	if (!IS_ENABLED(CONFIG_HOSTCMD_EVENTS))
-		return;
-
-	host_set_single_event(EC_HOST_EVENT_USB_MUX);
-
-	if (!IS_ENABLED(CONFIG_USB_MUX_AP_ACK_REQUEST))
-		return;
-
-	/*
-	 * EC waits for the ACK from kernel indicating that TCSS Mux
-	 * configuration is completed. This mechanism is implemented for
-	 * entering, exiting the safe mode and entering the disconnect mode
-	 * This is needed to remove timing senstivity between BB retimer and
-	 * TCSS Mux to allow better synchronization between them and thereby
-	 * remain in the same state for achieving proper safe state
-	 * terminations.
-	 */
-
-	/* TODO(b/186777984): Wait for an ACK for all mux state change */
-
-	if ((!(previous_mux_state & USB_PD_MUX_SAFE_MODE) &&
-	     (mux_state & USB_PD_MUX_SAFE_MODE)) ||
-	   ((previous_mux_state & USB_PD_MUX_SAFE_MODE) &&
-	    !(mux_state & USB_PD_MUX_SAFE_MODE)) ||
-	   ((previous_mux_state != USB_PD_MUX_NONE) &&
-	    (mux_state == USB_PD_MUX_NONE)))
-		*ack_required = true;
-}
-
-static int virtual_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-/*
- * Set the state of our 'virtual' mux. The EC does not actually control this
- * mux, so update the desired state, then notify the host of the update.
- */
-static int virtual_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			   bool *ack_required)
-{
-	int port = me->usb_port;
-
-	/* Current USB & DP mux status + existing HPD related mux status */
-	mux_state_t new_mux_state = (mux_state & ~USB_PD_MUX_HPD_STATE) |
-		(virtual_mux_state[port] & USB_PD_MUX_HPD_STATE);
-
-	virtual_mux_update_state(port, new_mux_state, ack_required);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Get the state of our 'virtual' mux. Since we the EC does not actually
- * control this mux, and the EC has no way of knowing its actual status,
- * we return the desired state here.
- */
-static int virtual_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
-{
-	int port = me->usb_port;
-
-	*mux_state = virtual_mux_state[port];
-
-	return EC_SUCCESS;
-}
-
-void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state)
-{
-	int port = me->usb_port;
-	bool unused;
-
-	/* Current HPD related mux status + existing USB & DP mux status */
-	mux_state_t new_mux_state = mux_state |
-			(virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE);
-
-	/* HPD ACK isn't required for the EC to continue with its tasks */
-	virtual_mux_update_state(port, new_mux_state, &unused);
-}
-
-const struct usb_mux_driver virtual_usb_mux_driver = {
-	.init = virtual_init,
-	.set = virtual_set_mux,
-	.get = virtual_get_mux,
-};
diff --git a/driver/wpc/p9221.c b/driver/wpc/p9221.c
deleted file mode 100644
index 973d991240..0000000000
--- a/driver/wpc/p9221.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * IDT P9221-R7 Wireless Power Receiver driver.
- */
-
-#include "p9221.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-#include <stdbool.h>
-#include "printf.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ## args)
-
-#define P9221_TX_TIMEOUT_MS		(20 * 1000*1000)
-#define P9221_DCIN_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_VRECT_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_NOTIFIER_DELAY_MS		(80*1000)
-#define P9221R7_ILIM_MAX_UA		(1600 * 1000)
-#define P9221R7_OVER_CHECK_NUM		3
-
-#define OVC_LIMIT			1
-#define OVC_THRESHOLD			1400000
-#define OVC_BACKOFF_LIMIT		900000
-#define OVC_BACKOFF_AMOUNT		100000
-
-/* P9221  parameters */
-static struct wpc_charger_info p9221_charger_info = {
-	.online = false,
-	.i2c_port = I2C_PORT_WPC,
-	.pp_buf_valid = false,
-};
-
-static struct wpc_charger_info *wpc = &p9221_charger_info;
-
-static void p9221_set_offline(void);
-
-static const uint32_t p9221_ov_set_lut[] = {
-	17000000, 20000000, 15000000, 13000000,
-	11000000, 11000000, 11000000, 11000000
-};
-
-static int p9221_reg_is_8_bit(uint16_t reg)
-{
-	switch (reg) {
-	case P9221_CHIP_REVISION_REG:
-	case P9221R7_VOUT_SET_REG:
-	case P9221R7_ILIM_SET_REG:
-	case P9221R7_CHARGE_STAT_REG:
-	case P9221R7_EPT_REG:
-	case P9221R7_SYSTEM_MODE_REG:
-	case P9221R7_COM_CHAN_RESET_REG:
-	case P9221R7_COM_CHAN_SEND_SIZE_REG:
-	case P9221R7_COM_CHAN_SEND_IDX_REG:
-	case P9221R7_COM_CHAN_RECV_SIZE_REG:
-	case P9221R7_COM_CHAN_RECV_IDX_REG:
-	case P9221R7_DEBUG_REG:
-	case P9221R7_EPP_Q_FACTOR_REG:
-	case P9221R7_EPP_TX_GUARANTEED_POWER_REG:
-	case P9221R7_EPP_TX_POTENTIAL_POWER_REG:
-	case P9221R7_EPP_TX_CAPABILITY_FLAGS_REG:
-	case P9221R7_EPP_RENEGOTIATION_REG:
-	case P9221R7_EPP_CUR_RPP_HEADER_REG:
-	case P9221R7_EPP_CUR_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_CUR_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_CUR_FSK_MODULATION_REG:
-	case P9221R7_EPP_REQ_RPP_HEADER_REG:
-	case P9221R7_EPP_REQ_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_REQ_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_REQ_FSK_MODULATION_REG:
-	case P9221R7_VRECT_TARGET_REG:
-	case P9221R7_VRECT_KNEE_REG:
-	case P9221R7_FOD_SECTION_REG:
-	case P9221R7_VRECT_ADJ_REG:
-	case P9221R7_ALIGN_X_ADC_REG:
-	case P9221R7_ALIGN_Y_ADC_REG:
-	case P9221R7_ASK_MODULATION_DEPTH_REG:
-	case P9221R7_OVSET_REG:
-	case P9221R7_EPP_TX_SPEC_REV_REG:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static int p9221_read8(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 1);
-}
-
-static int p9221_write8(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 1);
-}
-
-static int p9221_read16(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 2);
-}
-
-static int p9221_write16(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 2);
-}
-
-static int p9221_block_read(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				       reg, data, len);
-}
-
-static int p9221_block_write(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-					reg, data, len);
-}
-
-static int p9221_set_cmd_reg(uint8_t cmd)
-{
-	int cur_cmd;
-	int retry;
-	int ret;
-
-	for (retry = 0; retry < P9221_COM_CHAN_RETRIES; retry++) {
-		ret = p9221_read8(P9221_COM_REG, &cur_cmd);
-		if (ret == EC_SUCCESS && cur_cmd == 0)
-			break;
-		msleep(25);
-	}
-
-	if (retry >= P9221_COM_CHAN_RETRIES) {
-		CPRINTS("Failed to wait for cmd free %02x", cur_cmd);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	ret = p9221_write8(P9221_COM_REG, cmd);
-	if (ret)
-		CPRINTS("Failed to set cmd reg %02x: %d", cmd, ret);
-
-	return ret;
-}
-
-/* Convert a register value to uV, Hz, or uA */
-static int p9221_convert_reg_r7(uint16_t reg, uint16_t raw_data, uint32_t *val)
-{
-	switch (reg) {
-	case P9221R7_ALIGN_X_ADC_REG:	/* raw */
-	case P9221R7_ALIGN_Y_ADC_REG:	/* raw */
-		*val = raw_data;
-		break;
-	case P9221R7_VOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_IOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_DIE_TEMP_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_EXT_TEMP_REG:
-		*val = raw_data & 0xFFF;
-		break;
-	case P9221R7_VOUT_SET_REG:	/* 0.1V -> uV */
-		*val = raw_data * 100 * 1000;
-		break;
-	case P9221R7_IOUT_REG:		/* mA -> uA */
-	case P9221R7_VRECT_REG:		/* mV -> uV */
-	case P9221R7_VOUT_REG:		/* mV -> uV */
-	case P9221R7_OP_FREQ_REG:	/* kHz -> Hz */
-	case P9221R7_TX_PINGFREQ_REG:	/* kHz -> Hz */
-		*val = raw_data * 1000;
-		break;
-	case P9221R7_ILIM_SET_REG:	/* 100mA -> uA, 200mA offset */
-		*val = ((raw_data * 100) + 200) * 1000;
-		break;
-	case P9221R7_OVSET_REG:		/* uV */
-		raw_data &= P9221R7_OVSET_MASK;
-		*val = p9221_ov_set_lut[raw_data];
-		break;
-	default:
-		return -2;
-	}
-
-	return 0;
-}
-
-static int p9221_reg_read_converted(uint16_t reg, uint32_t *val)
-{
-	int ret;
-	int data;
-
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_read8(reg, &data);
-	else
-		ret = p9221_read16(reg, &data);
-
-	if (ret)
-		return ret;
-
-	return p9221_convert_reg_r7(reg, data, val);
-}
-
-static int p9221_is_online(void)
-{
-	int chip_id;
-
-	if (p9221_read16(P9221_CHIP_ID_REG, &chip_id)
-			|| chip_id != P9221_CHIP_ID)
-		return false;
-	else
-		return true;
-}
-
-int wpc_chip_is_online(void)
-{
-	return p9221_is_online();
-}
-
-
-void p9221_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_WPC);
-}
-
-static int p9221r7_clear_interrupts(uint16_t mask)
-{
-	int ret;
-
-	ret = p9221_write16(P9221R7_INT_CLEAR_REG, mask);
-	if (ret) {
-		CPRINTS("Failed to clear INT reg: %d", ret);
-		return ret;
-	}
-
-	ret = p9221_set_cmd_reg(P9221_COM_CLEAR_INT_MASK);
-	if (ret)
-		CPRINTS("Failed to reset INT: %d", ret);
-
-	return ret;
-}
-
-/*
- * Enable interrupts on the P9221 R7, note we don't really need to disable
- * interrupts since when the device goes out of field, the P9221 is reset.
- */
-static int p9221_enable_interrupts_r7(void)
-{
-	uint16_t mask = 0;
-	int ret;
-
-	CPRINTS("Enable interrupts");
-
-	mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK
-		| P9221_STAT_VRECT;
-
-	p9221r7_clear_interrupts(mask);
-
-	ret = p9221_write8(P9221_INT_ENABLE_REG, mask);
-	if (ret)
-		CPRINTS("Failed to enable INTs: %d", ret);
-	return ret;
-}
-
-static int p9221_send_csp(uint8_t status)
-{
-	int ret;
-
-	CPRINTS("Send CSP=%d", status);
-	mutex_lock(&wpc->cmd_lock);
-
-	ret = p9221_write8(P9221R7_CHARGE_STAT_REG, status);
-	if (ret == EC_SUCCESS)
-		ret = p9221_set_cmd_reg(P9221R7_COM_SENDCSP);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return ret;
-}
-
-static int p9221_send_eop(uint8_t reason)
-{
-	int rv;
-
-	CPRINTS("Send EOP reason=%d", reason);
-	mutex_lock(&wpc->cmd_lock);
-
-	rv = p9221_write8(P9221R7_EPT_REG, reason);
-	if (rv == EC_SUCCESS)
-		rv = p9221_set_cmd_reg(P9221R7_COM_SENDEPT);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return rv;
-}
-
-static void print_current_samples(uint32_t *iout_val, int count)
-{
-	int i;
-	char temp[P9221R7_OVER_CHECK_NUM * 9 + 1] = { 0 };
-
-	for (i = 0; i < count ; i++)
-		snprintf(temp + i * 9, sizeof(temp) - i * 9,
-			  "%08x ", iout_val[i]);
-	CPRINTS("OVER IOUT_SAMPLES: %s", temp);
-}
-
-
-/*
- * Number of times to poll the status to see if the current limit condition
- * was transient or not.
- */
-static void p9221_limit_handler_r7(uint16_t orign_irq_src)
-{
-	uint8_t reason;
-	int i;
-	int ret;
-	int ovc_count = 0;
-	uint32_t iout_val[P9221R7_OVER_CHECK_NUM] = { 0 };
-	int irq_src = (int)orign_irq_src;
-
-	CPRINTS("OVER INT: %02x", irq_src);
-
-	if (irq_src & P9221R7_STAT_OVV) {
-		reason = P9221_EOP_OVER_VOLT;
-		goto send_eop;
-	}
-
-	if (irq_src & P9221R7_STAT_OVT) {
-		reason = P9221_EOP_OVER_TEMP;
-		goto send_eop;
-	}
-
-	if ((irq_src & P9221R7_STAT_UV) && !(irq_src & P9221R7_STAT_OVC))
-		return;
-
-	reason = P9221_EOP_OVER_CURRENT;
-	for (i = 0; i < P9221R7_OVER_CHECK_NUM; i++) {
-		ret = p9221r7_clear_interrupts(
-				irq_src & P9221R7_STAT_LIMIT_MASK);
-		msleep(50);
-		if (ret)
-			continue;
-
-		ret = p9221_reg_read_converted(P9221R7_IOUT_REG, &iout_val[i]);
-		if (ret) {
-			CPRINTS("Failed to read IOUT[%d]: %d", i, ret);
-			continue;
-		} else if (iout_val[i] > OVC_THRESHOLD) {
-			ovc_count++;
-		}
-
-		ret = p9221_read16(P9221_STATUS_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read status: %d", ret);
-			continue;
-		}
-
-		if ((irq_src & P9221R7_STAT_OVC) == 0) {
-			print_current_samples(iout_val, i + 1);
-			CPRINTS("OVER condition %04x cleared after %d tries",
-				irq_src, i);
-			return;
-		}
-
-		CPRINTS("OVER status is still %04x, retry", irq_src);
-	}
-
-	if (ovc_count < OVC_LIMIT) {
-		print_current_samples(iout_val, P9221R7_OVER_CHECK_NUM);
-		CPRINTS("ovc_threshold=%d, ovc_count=%d, ovc_limit=%d",
-			OVC_THRESHOLD, ovc_count, OVC_LIMIT);
-		return;
-	}
-
-send_eop:
-	CPRINTS("OVER is %04x, sending EOP %d", irq_src, reason);
-
-	ret = p9221_send_eop(reason);
-	if (ret)
-		CPRINTS("Failed to send EOP %d: %d", reason, ret);
-}
-
-static void p9221_abort_transfers(void)
-{
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = true;
-	wpc->rx_len = 0;
-}
-
-/* Handler for r7 and R7 chips */
-static void p9221r7_irq_handler(uint16_t irq_src)
-{
-	int res;
-
-	if (irq_src & P9221R7_STAT_LIMIT_MASK)
-		p9221_limit_handler_r7(irq_src);
-
-	/* Receive complete */
-	if (irq_src & P9221R7_STAT_CCDATARCVD) {
-		int rxlen = 0;
-
-		res = p9221_read8(P9221R7_COM_CHAN_RECV_SIZE_REG, &rxlen);
-		if (res)
-			CPRINTS("Failed to read len: %d", res);
-
-		if (rxlen) {
-			res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-					       wpc->rx_buf, rxlen);
-			if (res) {
-				CPRINTS("Failed to read CC data: %d", res);
-				rxlen = 0;
-			}
-
-			wpc->rx_len = rxlen;
-			wpc->rx_done = true;
-		}
-	}
-
-	/* Send complete */
-	if (irq_src & P9221R7_STAT_CCSENDBUSY) {
-		wpc->tx_busy = false;
-		wpc->tx_done = true;
-	}
-
-	/* Proprietary packet */
-	if (irq_src & P9221R7_STAT_PPRCVD) {
-		res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-				       wpc->pp_buf, sizeof(wpc->pp_buf));
-		if (res) {
-			CPRINTS("Failed to read PP: %d", res);
-			wpc->pp_buf_valid = false;
-			return;
-		}
-
-		/* We only care about PP which come with 0x4F header */
-		wpc->pp_buf_valid = (wpc->pp_buf[0] == 0x4F);
-
-		hexdump(wpc->pp_buf, sizeof(wpc->pp_buf));
-	}
-
-	/* CC Reset complete */
-	if (irq_src & P9221R7_STAT_CCRESET)
-		p9221_abort_transfers();
-}
-
-static int p9221_is_epp(void)
-{
-	int ret, reg;
-	uint32_t vout_uv;
-
-	if (p9221_read8(P9221R7_SYSTEM_MODE_REG, &reg) == EC_SUCCESS)
-		return reg & P9221R7_SYSTEM_MODE_EXTENDED_MASK;
-
-	/* Check based on power supply voltage */
-	ret = p9221_reg_read_converted(P9221R7_VOUT_ADC_REG, &vout_uv);
-	if (ret) {
-		CPRINTS("Failed to read VOUT_ADC: %d", ret);
-		return false;
-	}
-
-	CPRINTS("Voltage is %duV", vout_uv);
-	if (vout_uv > P9221_EPP_THRESHOLD_UV)
-		return true;
-
-	return false;
-}
-
-static void p9221_config_fod(void)
-{
-
-	int epp;
-	uint8_t *fod;
-	int fod_len;
-	int ret;
-	int retries = 3;
-
-	CPRINTS("Config FOD");
-
-	epp = p9221_is_epp();
-	fod_len = epp ? board_get_epp_fod(&fod) : board_get_fod(&fod);
-	if (!fod_len || !fod) {
-		CPRINTS("FOD data not found");
-		return;
-	}
-
-	while (retries) {
-		uint8_t fod_read[fod_len];
-
-		CPRINTS("Writing %s FOD (n=%d try=%d)",
-			epp ? "EPP" : "BPP", fod_len, retries);
-
-		ret = p9221_block_write(P9221R7_FOD_REG, fod, fod_len);
-		if (ret)
-			goto no_fod;
-
-		/* Verify the FOD has been written properly */
-		ret = p9221_block_read(P9221R7_FOD_REG, fod_read, fod_len);
-		if (ret)
-			goto no_fod;
-
-		if (memcmp(fod, fod_read, fod_len) == 0)
-			return;
-
-		hexdump(fod_read, fod_len);
-
-		retries--;
-		msleep(100);
-	}
-
-no_fod:
-	CPRINTS("Failed to set FOD. retries:%d ret:%d", retries, ret);
-}
-
-static void p9221_set_online(void)
-{
-	int ret;
-
-	CPRINTS("Set online");
-
-	wpc->online = true;
-
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = false;
-	wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-
-	ret = p9221_enable_interrupts_r7();
-	if (ret)
-		CPRINTS("Failed to enable INT: %d", ret);
-
-	/* NOTE: depends on _is_epp() which is not valid until DC_IN */
-	p9221_config_fod();
-}
-
-static void p9221_vbus_check_timeout(void)
-{
-	CPRINTS("Timeout VBUS, online=%d", wpc->online);
-	if (wpc->online)
-		p9221_set_offline();
-
-}
-DECLARE_DEFERRED(p9221_vbus_check_timeout);
-
-static void p9221_set_offline(void)
-{
-	CPRINTS("Set offline");
-
-	wpc->online = false;
-	/* Reset PP buf so we can get a new serial number next time around */
-	wpc->pp_buf_valid = false;
-
-	p9221_abort_transfers();
-
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-}
-
-/* P9221_NOTIFIER_DELAY_MS from VRECTON */
-static int p9221_notifier_check_det(void)
-{
-	if (wpc->online)
-		goto done;
-
-	/* send out a FOD but is_epp() is still invalid */
-	p9221_set_online();
-
-	/* Give the vbus 2 seconds to come up. */
-	CPRINTS("Waiting VBUS");
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-	hook_call_deferred(&p9221_vbus_check_timeout_data,
-			   P9221_DCIN_TIMEOUT_MS);
-
-done:
-	wpc->p9221_check_det = false;
-	return 0;
-}
-
-static int p9221_get_charge_supplier(void)
-{
-	if (!wpc->online)
-		return EC_ERROR_UNKNOWN;
-
-	if (p9221_is_epp()) {
-		uint32_t tx_id;
-		int txmf_id;
-		int ret;
-
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_EPP;
-
-		ret = p9221_read16(P9221R7_EPP_TX_MFG_CODE_REG, &txmf_id);
-		if (ret || txmf_id != P9221_GPP_TX_MF_ID)
-			return ret;
-
-		ret = p9221_block_read(P9221R7_PROP_TX_ID_REG,
-				       (uint8_t *) &tx_id,
-				       P9221R7_PROP_TX_ID_SIZE);
-		if (ret)
-			return ret;
-
-		if (tx_id & P9221R7_PROP_TX_ID_GPP_MASK)
-			wpc->charge_supplier = CHARGE_SUPPLIER_WPC_GPP;
-
-		CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d",
-			txmf_id, tx_id, wpc->charge_supplier);
-	} else {
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-		CPRINTS("supplier=%d", wpc->charge_supplier);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int p9221_get_icl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_ICL_EPP_MA;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_ICL_BPP_MA;
-	}
-}
-
-static int p9221_get_ivl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_IVL_EPP_MV;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_IVL_BPP_MV;
-	}
-}
-
-static void p9221_update_charger(int type, struct charge_port_info *chg)
-{
-	if (!chg)
-		charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	else
-		charge_manager_update_dualrole(0, CAP_DEDICATED);
-
-	charge_manager_update_charge(type, 0, chg);
-}
-
-static int p9221_reg_write_converted_r7(uint16_t reg, uint32_t val)
-{
-	int ret = 0;
-	uint16_t data;
-	int i;
-	/* Do the appropriate conversion */
-	switch (reg) {
-	case P9221R7_ILIM_SET_REG:
-		/* uA -> 0.1A, offset 0.2A */
-		if ((val < 200000) || (val > 1600000))
-			return -EC_ERROR_INVAL;
-		data = (val / (100 * 1000)) - 2;
-		break;
-	case P9221R7_VOUT_SET_REG:
-		/* uV -> 0.1V */
-		val /= 1000;
-		if (val < 3500 || val > 9000)
-			return -EC_ERROR_INVAL;
-		data = val / 100;
-		break;
-	case P9221R7_OVSET_REG:
-		/* uV */
-		for (i = 0; i < ARRAY_SIZE(p9221_ov_set_lut); i++) {
-			if (val == p9221_ov_set_lut[i])
-				break;
-		}
-		if (i == ARRAY_SIZE(p9221_ov_set_lut))
-			return -EC_ERROR_INVAL;
-		data = i;
-		break;
-	default:
-		return -EC_ERROR_INVAL;
-	}
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_write8(reg, data);
-	else
-		ret = p9221_write16(reg, data);
-	return ret;
-}
-
-static int p9221_set_dc_icl(void)
-{
-	/* Increase the IOUT limit */
-	if (p9221_reg_write_converted_r7(P9221R7_ILIM_SET_REG,
-					 P9221R7_ILIM_MAX_UA))
-		CPRINTS("%s set rx_iout limit fail.", __func__);
-
-	return EC_SUCCESS;
-}
-
-
-static void p9221_notifier_check_vbus(void)
-{
-	struct charge_port_info chg;
-
-	wpc->p9221_check_vbus = false;
-
-	CPRINTS("%s online:%d vbus:%d", __func__, wpc->online,
-		wpc->vbus_status);
-
-	/*
-	 * We now have confirmation from DC_IN, kill the timer, p9221_online
-	 * will be set by this function.
-	 */
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-
-	if (wpc->vbus_status) {
-		/* WPC VBUS on ,Always write FOD, check dc_icl, send CSP */
-		p9221_set_dc_icl();
-		p9221_config_fod();
-
-		p9221_send_csp(1);
-
-		/* when wpc vbus attached after 2s, set wpc online */
-		if (!wpc->online)
-			p9221_set_online();
-
-		/* WPC VBUS on , update charge voltage and current */
-		p9221_get_charge_supplier();
-		chg.voltage = p9221_get_ivl(wpc->charge_supplier);
-		chg.current = p9221_get_icl(wpc->charge_supplier);
-
-		p9221_update_charger(wpc->charge_supplier, &chg);
-	} else {
-		/*
-		 * Vbus detached, set wpc offline and update wpc charge voltage
-		 * and current to zero.
-		 */
-		if (wpc->online) {
-			p9221_set_offline();
-			p9221_update_charger(wpc->charge_supplier, NULL);
-		}
-	}
-
-	CPRINTS("check_vbus changed on:%d vbus:%d", wpc->online,
-		wpc->vbus_status);
-
-}
-
-static void p9221_detect_work(void)
-{
-
-	CPRINTS("%s online:%d check_vbus:%d check_det:%d vbus:%d", __func__,
-		wpc->online, wpc->p9221_check_vbus, wpc->p9221_check_det,
-		wpc->vbus_status);
-
-	/* Step 1 */
-	if (wpc->p9221_check_det)
-		p9221_notifier_check_det();
-
-	/* Step 2 */
-	if (wpc->p9221_check_vbus)
-		p9221_notifier_check_vbus();
-
-}
-DECLARE_DEFERRED(p9221_detect_work);
-
-void p9221_notify_vbus_change(int vbus)
-{
-	wpc->p9221_check_vbus = true;
-	wpc->vbus_status = vbus;
-	hook_call_deferred(&p9221_detect_work_data, P9221_NOTIFIER_DELAY_MS);
-}
-
-void wireless_power_charger_task(void *u)
-{
-	while (1) {
-		int ret, irq_src;
-		task_wait_event(-1);
-
-		ret = p9221_read16(P9221_INT_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read INT REG");
-			continue;
-		}
-
-		CPRINTS("INT SRC 0x%04x", irq_src);
-
-		if (p9221r7_clear_interrupts(irq_src))
-			continue;
-
-		if (irq_src & P9221_STAT_VRECT) {
-			CPRINTS("VRECTON, online=%d", wpc->online);
-			if (!wpc->online) {
-				wpc->p9221_check_det = true;
-				hook_call_deferred(&p9221_detect_work_data,
-						   P9221_NOTIFIER_DELAY_MS);
-			}
-		}
-
-		p9221r7_irq_handler(irq_src);
-	}
-}
diff --git a/driver/wpc/p9221.h b/driver/wpc/p9221.h
deleted file mode 100644
index 0bb0571b38..0000000000
--- a/driver/wpc/p9221.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-
-/*
- * IDT P9221-R7 Wireless Power Receiver driver definitions.
- */
-
-#ifndef __P9221_R7_H
-#define __P9221_R7_H
-
-#include "common.h"
-#include "gpio.h"
-#include "charge_manager.h"
-#include "task.h"
-
-
-/* ========== Variant-specific configuration ============ */
-
-#define P9221_R7_ADDR_FLAGS			0x61
-
-/*
- * P9221 common registers
- */
-#define P9221_CHIP_ID_REG			0x00
-#define P9221_CHIP_ID				0x9220
-#define P9221_CHIP_REVISION_REG			0x02
-#define P9221_CUSTOMER_ID_REG			0x03
-#define P9221R7_CUSTOMER_ID_VAL			0x05
-#define P9221_OTP_FW_MAJOR_REV_REG		0x04
-#define P9221_OTP_FW_MINOR_REV_REG		0x06
-#define P9221_OTP_FW_DATE_REG			0x08
-#define P9221_OTP_FW_DATE_SIZE			12
-#define P9221_OTP_FW_TIME_REG			0x14
-#define P9221_OTP_FW_TIME_SIZE			8
-#define P9221_SRAM_FW_MAJOR_REV_REG		0x1C
-#define P9221_SRAM_FW_MINOR_REV_REG		0x1E
-#define P9221_SRAM_FW_DATE_REG			0x20
-#define P9221_SRAM_FW_DATE_SIZE			12
-#define P9221_SRAM_FW_TIME_REG			0x2C
-#define P9221_SRAM_FW_TIME_SIZE			8
-#define P9221_STATUS_REG			0x34
-#define P9221_INT_REG				0x36
-#define P9221_INT_MASK				0xF7
-#define P9221_INT_ENABLE_REG			0x38
-#define P9221_GPP_TX_MF_ID			0x0072
-
-/*
- * P9221 Rx registers (x != 5)
- */
-#define P9221_CHARGE_STAT_REG			0x3A
-#define P9221_EPT_REG				0x3B
-#define P9221_VOUT_ADC_REG			0x3C
-#define P9221_VOUT_ADC_MASK			0x0FFF
-#define P9221_VOUT_SET_REG			0x3E
-#define P9221_MAX_VOUT_SET_MV_DEFAULT		9000
-#define P9221_VRECT_ADC_REG			0x40
-#define P9221_VRECT_ADC_MASK			0x0FFF
-#define P9221_OVSET_REG				0x42
-#define P9221_OVSET_MASK			0x70
-#define P9221_OVSET_SHIFT			4
-#define P9221_RX_IOUT_REG			0x44
-#define P9221_DIE_TEMP_ADC_REG			0x46
-#define P9221_DIE_TEMP_ADC_MASK			0x0FFF
-#define P9221_OP_FREQ_REG			0x48
-#define P9221_ILIM_SET_REG			0x4A
-#define P9221_ALIGN_X_ADC_REG			0x4B
-#define P9221_ALIGN_Y_ADC_REG			0x4C
-#define P9221_OP_MODE_REG			0x4D
-#define P9221_COM_REG				0x4E
-#define P9221_FW_SWITCH_KEY_REG			0x4F
-#define P9221_INT_CLEAR_REG			0x56
-#define P9221_RXID_REG				0x5C
-#define P9221_RXID_LEN				6
-#define P9221_MPREQ_REG				0x5C
-#define P9221_MPREQ_LEN				6
-#define P9221_FOD_REG				0x68
-#define P9221_NUM_FOD				16
-#define P9221_RX_RAWIOUT_REG			0x7A
-#define P9221_RX_RAWIOUT_MASK			0xFFF
-#define P9221_PMA_AD_REG			0x7C
-#define P9221_RX_PINGFREQ_REG			0xFC
-#define P9221_RX_PINGFREQ_MASK			0xFFF
-#define P9221_LAST_REG				0xFF
-
-/*
- * P9221R7 unique registers
- */
-#define P9221R7_INT_CLEAR_REG			0x3A
-#define P9221R7_VOUT_SET_REG			0x3C
-#define P9221R7_ILIM_SET_REG			0x3D
-#define P9221R7_ILIM_SET_MAX			0x0E	/* 0x0E = 1.6A */
-#define P9221R7_CHARGE_STAT_REG			0x3E
-#define P9221R7_EPT_REG				0x3F
-#define P9221R7_VRECT_REG			0x40
-#define P9221R7_VOUT_REG			0x42
-#define P9221R7_IOUT_REG			0x44
-#define P9221R7_OP_FREQ_REG			0x48
-#define P9221R7_SYSTEM_MODE_REG			0x4C
-#define P9221R7_COM_CHAN_RESET_REG		0x50
-#define P9221R7_COM_CHAN_SEND_SIZE_REG		0x58
-#define P9221R7_COM_CHAN_SEND_IDX_REG		0x59
-#define P9221R7_COM_CHAN_RECV_SIZE_REG		0x5A
-#define P9221R7_COM_CHAN_RECV_IDX_REG		0x5B
-#define P9221R7_VRECT_ADC_REG			0x60
-#define P9221R7_VOUT_ADC_REG			0x62
-#define P9221R7_VOUT_ADC_MASK			0xFFF
-#define P9221R7_IOUT_ADC_REG			0x64
-#define P9221R7_IOUT_ADC_MASK			0xFFF
-#define P9221R7_DIE_TEMP_ADC_REG		0x66
-#define P9221R7_DIE_TEMP_ADC_MASK		0xFFF
-#define P9221R7_AC_PERIOD_REG			0x68
-#define P9221R7_TX_PINGFREQ_REG			0x6A
-#define P9221R7_EXT_TEMP_REG			0x6C
-#define P9221R7_EXT_TEMP_MASK			0xFFF
-#define P9221R7_FOD_REG				0x70
-#define P9221R7_NUM_FOD				16
-#define P9221R7_DEBUG_REG			0x80
-#define P9221R7_EPP_Q_FACTOR_REG		0x83
-#define P9221R7_EPP_TX_GUARANTEED_POWER_REG	0x84
-#define P9221R7_EPP_TX_POTENTIAL_POWER_REG	0x85
-#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG	0x86
-#define P9221R7_EPP_RENEGOTIATION_REG		0x87
-#define P9221R7_EPP_CUR_RPP_HEADER_REG		0x88
-#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG	0x89
-#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG	0x8A
-#define P9221R7_EPP_CUR_FSK_MODULATION_REG	0x8B
-#define P9221R7_EPP_REQ_RPP_HEADER_REG		0x8C
-#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG	0x8D
-#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG	0x8E
-#define P9221R7_EPP_REQ_FSK_MODULATION_REG	0x8F
-#define P9221R7_VRECT_TARGET_REG		0x90
-#define P9221R7_VRECT_KNEE_REG			0x92
-#define P9221R7_VRECT_CORRECTION_FACTOR_REG	0x93
-#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG	0x94
-#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG	0x96
-#define P9221R7_FOD_SECTION_REG			0x99
-#define P9221R7_VRECT_ADJ_REG			0x9E
-#define P9221R7_ALIGN_X_ADC_REG			0xA0
-#define P9221R7_ALIGN_Y_ADC_REG			0xA1
-#define P9221R7_ASK_MODULATION_DEPTH_REG	0xA2
-#define P9221R7_OVSET_REG			0xA3
-#define P9221R7_OVSET_MASK			0x7
-#define P9221R7_EPP_TX_SPEC_REV_REG		0xA9
-#define P9221R7_EPP_TX_MFG_CODE_REG		0xAA
-#define P9221R7_GP0_RESET_VOLT_REG		0xAC
-#define P9221R7_GP1_RESET_VOLT_REG		0xAE
-#define P9221R7_GP2_RESET_VOLT_REG		0xB0
-#define P9221R7_GP3_RESET_VOLT_REG		0xB2
-#define P9221R7_PROP_TX_ID_REG			0xB4
-#define P9221R7_PROP_TX_ID_SIZE			4
-#define P9221R7_DATA_SEND_BUF_START		0x100
-#define P9221R7_DATA_SEND_BUF_SIZE		0x80
-#define P9221R7_DATA_RECV_BUF_START		0x180
-#define P9221R7_DATA_RECV_BUF_SIZE		0x80
-#define P9221R7_MAX_PP_BUF_SIZE			16
-#define P9221R7_LAST_REG			0x1FF
-
-/*
- * System Mode Mask (r7+/0x4C)
- */
-#define P9221R7_SYSTEM_MODE_EXTENDED_MASK	(1 << 3)
-
-/*
- * TX ID GPP Mask (r7+/0xB4->0xB7)
- */
-#define P9221R7_PROP_TX_ID_GPP_MASK		(1 << 29)
-
-/*
- * Com Channel Commands
- */
-#define P9221R7_COM_CHAN_CCRESET		BIT(7)
-#define P9221_COM_CHAN_RETRIES			5
-
-/*
- * End of Power packet types
- */
-#define P9221_EOP_UNKNOWN			0x00
-#define P9221_EOP_EOC				0x01
-#define P9221_EOP_INTERNAL_FAULT		0x02
-#define P9221_EOP_OVER_TEMP			0x03
-#define P9221_EOP_OVER_VOLT			0x04
-#define P9221_EOP_OVER_CURRENT			0x05
-#define P9221_EOP_BATT_FAIL			0x06
-#define P9221_EOP_RECONFIG			0x07
-#define P9221_EOP_NO_RESPONSE			0x08
-#define P9221_EOP_NEGOTIATION_FAIL		0x0A
-#define P9221_EOP_RESTART_POWER			0x0B
-
-/*
- * Command flags
- */
-#define P9221R7_COM_RENEGOTIATE			P9221_COM_RENEGOTIATE
-#define P9221R7_COM_SWITCH2RAM			P9221_COM_SWITCH_TO_RAM_MASK
-#define P9221R7_COM_CLRINT			P9221_COM_CLEAR_INT_MASK
-#define P9221R7_COM_SENDCSP			P9221_COM_SEND_CHG_STAT_MASK
-#define P9221R7_COM_SENDEPT			P9221_COM_SEND_EOP_MASK
-#define P9221R7_COM_LDOTGL			P9221_COM_LDO_TOGGLE
-#define P9221R7_COM_CCACTIVATE			BIT(0)
-
-#define P9221_COM_RENEGOTIATE			BIT(7)
-#define P9221_COM_SWITCH_TO_RAM_MASK		BIT(6)
-#define P9221_COM_CLEAR_INT_MASK		BIT(5)
-#define P9221_COM_SEND_CHG_STAT_MASK		BIT(4)
-#define P9221_COM_SEND_EOP_MASK			BIT(3)
-#define P9221_COM_LDO_TOGGLE			BIT(1)
-
-/*
- * Interrupt/Status flags for P9221
- */
-#define P9221_STAT_VOUT				BIT(7)
-#define P9221_STAT_VRECT			BIT(6)
-#define P9221_STAT_ACMISSING			BIT(5)
-#define P9221_STAT_OV_TEMP			BIT(2)
-#define P9221_STAT_OV_VOLT			BIT(1)
-#define P9221_STAT_OV_CURRENT			BIT(0)
-#define P9221_STAT_LIMIT_MASK			(P9221_STAT_OV_TEMP | \
-						 P9221_STAT_OV_VOLT | \
-						 P9221_STAT_OV_CURRENT)
-/*
- * Interrupt/Status flags for P9221R7
- */
-#define P9221R7_STAT_CCRESET			BIT(12)
-#define P9221R7_STAT_CCERROR			BIT(11)
-#define P9221R7_STAT_PPRCVD			BIT(10)
-#define P9221R7_STAT_CCDATARCVD			BIT(9)
-#define P9221R7_STAT_CCSENDBUSY			BIT(8)
-#define P9221R7_STAT_VOUTCHANGED		BIT(7)
-#define P9221R7_STAT_VRECTON			BIT(6)
-#define P9221R7_STAT_MODECHANGED		BIT(5)
-#define P9221R7_STAT_UV				BIT(3)
-#define P9221R7_STAT_OVT			BIT(2)
-#define P9221R7_STAT_OVV			BIT(1)
-#define P9221R7_STAT_OVC			BIT(0)
-#define P9221R7_STAT_MASK			0x1FFF
-#define P9221R7_STAT_CC_MASK			(P9221R7_STAT_CCRESET | \
-						 P9221R7_STAT_PPRCVD | \
-						 P9221R7_STAT_CCERROR | \
-						 P9221R7_STAT_CCDATARCVD | \
-						 P9221R7_STAT_CCSENDBUSY)
-#define P9221R7_STAT_LIMIT_MASK			(P9221R7_STAT_UV | \
-						 P9221R7_STAT_OVV | \
-						 P9221R7_STAT_OVT | \
-						 P9221R7_STAT_OVC)
-
-#define P9221_DC_ICL_BPP_MA			1000
-#define P9221_DC_ICL_EPP_MA			1100
-#define P9221_DC_IVL_BPP_MV			5000
-#define P9221_DC_IVL_EPP_MV			9000
-#define P9221_EPP_THRESHOLD_UV			7000000
-
-#define true    1
-#define false   0
-
-struct wpc_charger_info {
-	uint8_t online;				 /* wpc is online */
-	uint8_t cust_id;			 /* customer id */
-	uint8_t i2c_port;			 /* i2c port */
-	/* Proprietary Packets receive buffer, to get Proprietary data from TX*/
-	uint8_t pp_buf[P9221R7_MAX_PP_BUF_SIZE];
-	uint8_t pp_buf_valid;
-	/* Common message Packets receive buffer, for get data from TX */
-	uint8_t rx_buf[P9221R7_DATA_RECV_BUF_SIZE];
-	uint8_t rx_len;
-	uint8_t rx_done;
-	/* Message packets send buffer, used when send messages from RX to TX*/
-	uint8_t tx_buf[P9221R7_DATA_SEND_BUF_SIZE];
-	uint8_t tx_id;				/* TX device id */
-	uint8_t tx_len;	 /* The data size need send to TX */
-	uint8_t tx_done; /* TX data send has done */
-	uint8_t tx_busy; /* when tx_busy=1, can't transfer data from RX to TX */
-	/* p9221_check_vbus=1 when VBUS has changed, need update charge state */
-	uint8_t p9221_check_vbus;
-	/* p9221_check_det=1 when TX device has detected */
-	uint8_t p9221_check_det;
-	/* vbus_status is 1 when VBUS attached and is 0 when VBUS detached*/
-	uint8_t vbus_status;
-	/* supplier type of wireless charger */
-	uint8_t charge_supplier;
-	/* lock of send command to p9221 */
-	struct mutex cmd_lock;
-};
-
-/* Interrupt handler for p9221 */
-void p9221_interrupt(enum gpio_signal signal);
-
-/**
- * notify p9221 detect update charger status when VBUS changed
- *
- * @param vbus: new status of VBUS, 1 if VBUS on, 0 if VBUS off.
- */
-void p9221_notify_vbus_change(int vbus);
-
-/**
- * get the fod (foreign-object detection) parameters for bpp charger type
- *
- * @param fod: return the real value of fod paramerters,
- *             return NULL if fod paramerters not set.
- *
- * @return the count bytes of fod paramerters.
- */
-int board_get_fod(uint8_t **fod);
-
-/**
- * get the fod (foreign-object detection) parameters for epp chager type
- *
- * @param fod: return the real value of fod paramerters,
- *             return NULL if fod paramerters not set.
- *
- * @return the count bytes of fod paramerters.
- */
-int board_get_epp_fod(uint8_t **fod);
-
-/**
- * return the wireless charge online status
- *
- * @return true if online, false if offline.
- */
-int wpc_chip_is_online(void);
-
-#endif
diff --git a/extra/README b/extra/README
deleted file mode 100644
index 874a7b1b32..0000000000
--- a/extra/README
+++ /dev/null
@@ -1,5 +0,0 @@
-
-This directory is for experiments only. It is not built automatically,
-required, supported, guaranteed to work, or necessarily well-documented.
-
-The contents may change without warning at any time.
diff --git a/extra/cr50_rma_open/cr50_rma_open.py b/extra/cr50_rma_open/cr50_rma_open.py
deleted file mode 100755
index 42ddbbac2d..0000000000
--- a/extra/cr50_rma_open/cr50_rma_open.py
+++ /dev/null
@@ -1,665 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Used to access the cr50 console and handle RMA Open
-"""Open cr50 using RMA authentication.
-
-Run RMA Open to enable CCD on Cr50. The utility can be used to get a
-url that will generate an authcode to open cr50. It can also be used to
-try opening cr50 with the generated authcode.
-
-The last challenge is the only valid one, so don't generate a challenge
-10 times and then use the first URL. You can only use the last one.
-
-For RMA Open:
-Connect suzyq to the dut and your workstation.
-
-Check the basic setup with
-    sudo python cr50_rma_open.py -c
-
-If the setup is broken. Follow the debug print statements to try to fix
-the error. Rerun until the script says Cr50 setup ok.
-
-After the setup is verified, run the following command to generate the
-challenge url
-    sudo python cr50_rma_open.py -g -i $HWID
-
-Go to the URL from by that command to generate an authcode. Once you have
-the authcode, you can use it to open cr50.
-    sudo python cr50_rma_open.py -a $AUTHCODE
-
-If for some reason hardware write protect doesn't get disabled during rma
-open or gets enabled at some point the script can be used to disable
-write protect.
-    sudo python cr50_rma_open.py -w
-
-When prepping devices for the testlab, you need to enable testlab mode.
-Prod cr50 images can't enable testlab mode. If the device is running a
-prod image, you can skip this step.
-    sudo python cr50_rma_open.py -t
-"""
-
-import argparse
-import glob
-import logging
-import re
-import subprocess
-import sys
-import time
-
-import serial
-
-SCRIPT_VERSION = 5
-CCD_IS_UNRESTRICTED = 1 << 0
-WP_IS_DISABLED = 1 << 1
-TESTLAB_IS_ENABLED = 1 << 2
-RMA_OPENED = CCD_IS_UNRESTRICTED | WP_IS_DISABLED
-URL = ('https://www.google.com/chromeos/partner/console/cr50reset?'
-       'challenge=%s&hwid=%s')
-RMA_SUPPORT_PROD = '0.3.3'
-RMA_SUPPORT_PREPVT = '0.4.5'
-DEV_MODE_OPEN_PROD = '0.3.9'
-DEV_MODE_OPEN_PREPVT = '0.4.7'
-TESTLAB_PROD = '0.3.10'
-CR50_USB = '18d1:5014'
-CR50_LSUSB_CMD = ['lsusb', '-vd', CR50_USB]
-ERASED_BID = 'ffffffff'
-
-DEBUG_MISSING_USB = """
-Unable to find Cr50 Device 18d1:5014
-
-DEBUG MISSING USB:
-    - Make sure suzyq is plugged into the correct DUT port
-    - Try flipping the cable
-    - unplug the cable for 5s then plug it back in
-"""
-
-DEBUG_DEVICE = """
-DEBUG DEVICE COMMUNICATION:
-Issues communicating with %s
-
-A 18d1:5014 device exists, so make sure you have selected the correct
-/dev/ttyUSB
-"""
-
-DEBUG_SERIALNAME = """
-DEBUG SERIALNAME:
-Found the USB device, but can't match the usb serialname. Check the
-serialname you passed into cr50_rma_open or try running without a
-serialname.
-"""
-
-DEBUG_CONNECTION = """
-DEBUG CONNECTION:
-Found the USB device but cant communicate with any of the consoles.
-
-Try Running cr50_rma_open again. If it still fails unplug the ccd cable
-for 5 seconds and plug it back in.
-"""
-
-DEBUG_TOO_MANY_USB_DEVICES = """
-DEBUG SELECT USB:
-More than one cr50 usb device was found. Disconnect all but one device
-or use the -s option with the correct usb serialname.
-"""
-
-DEBUG_ERASED_BOARD_ID = """
-DEBUG ERASED BOARD ID:
-If you are using a prePVT device run
-/usr/share/cros/cr50-set-board-id.sh proto
-
-If you are running a MP device, please talk to someone.
-"""
-
-DEBUG_AUTHCODE_MISMATCH = """
-DEBUG AUTHCODE MISMATCH:
-    - Check the URL matches the one generated by the last cr50_rma_open
-      run.
-    - Check you used the correct authcode.
-    - Make sure the cr50 version is greater than 3.3.
-    - try generating another URL by rerunning the generate command and
-      rerunning the process.
-"""
-
-DEBUG_DUT_CONTROL_OSERROR = """
-Run from chroot if you are trying to use a /dev/pts ccd servo console
-"""
-
-class RMAOpen(object):
-    """Used to find the cr50 console and run RMA open"""
-
-    ENABLE_TESTLAB_CMD = 'ccd testlab enabled\n'
-
-    def __init__(self, device=None, usb_serial=None, servo_port=None, ip=None):
-        self.servo_port = servo_port if servo_port else '9999'
-        self.ip = ip
-        if device:
-            self.set_cr50_device(device)
-        elif servo_port:
-            self.find_cr50_servo_uart()
-        else:
-            self.find_cr50_device(usb_serial)
-        logging.info('DEVICE: %s', self.device)
-        self.check_version()
-        self.print_platform_info()
-        logging.info('Cr50 setup ok')
-        self.update_ccd_state()
-        self.using_ccd = self.device_is_running_with_servo_ccd()
-
-    def _dut_control(self, control):
-        """Run dut-control and return the response"""
-        try:
-            cmd = ['dut-control', '-p', self.servo_port, control]
-            return subprocess.check_output(cmd, encoding='utf-8').strip()
-        except OSError:
-            logging.warning(DEBUG_DUT_CONTROL_OSERROR)
-            raise
-
-    def find_cr50_servo_uart(self):
-        """Save the device used for the console.
-
-        Find the console and configure it, so it can be used with this script.
-        """
-        self._dut_control('cr50_uart_timestamp:off')
-        self.device = self._dut_control('cr50_uart_pty').split(':')[-1]
-
-    def set_cr50_device(self, device):
-        """Save the device used for the console"""
-        self.device = device
-
-    def send_cmd_get_output(self, cmd, nbytes=0):
-        """Send a cr50 command and get the output
-
-        Args:
-            cmd: The cr50 command string
-            nbytes: The number of bytes to read from the console. If 0 read all
-                    of the console output.
-        Returns:
-            The command output
-        """
-        try:
-            ser = serial.Serial(self.device, timeout=1)
-        except OSError:
-            logging.warning('Permission denied %s', self.device)
-            logging.warning('Try running cr50_rma_open with sudo')
-            raise
-        write_cmd = cmd + '\n\n'
-        ser.write(write_cmd.encode('utf-8'))
-        if nbytes:
-            output = ser.read(nbytes)
-        else:
-            output = ser.readall()
-        ser.close()
-
-        output = output.decode('utf-8').strip() if output else ''
-        # Return only the command output
-        split_cmd = cmd + '\r'
-        if cmd and split_cmd in output:
-            return ''.join(output.rpartition(split_cmd)[1::]).split('>')[0]
-        return output
-
-    def device_is_running_with_servo_ccd(self):
-        """Return True if the device is a servod ccd console"""
-        # servod uses /dev/pts consoles. Non-servod uses /dev/ttyUSBX
-        if '/dev/pts' not in self.device:
-            return False
-        # If cr50 doesn't show rdd is connected, cr50 the device must not be
-        # a ccd device
-        if 'Rdd:     connected' not in self.send_cmd_get_output('ccdstate'):
-            return False
-        # Check if the servod is running with ccd. This requires the script
-        # is run in the chroot, so run it last.
-        if 'ccd_cr50' not in self._dut_control('servo_type'):
-            return False
-        logging.info('running through servod ccd')
-        return True
-
-    def get_rma_challenge(self):
-        """Get the rma_auth challenge
-
-        There are two challenge formats
-
-        "
-        ABEQ8 UGA4F AVEQP SHCKV
-        DGGPR N8JHG V8PNC LCHR2
-        T27VF PRGBS N3ZXF RCCT2
-        UBMKP ACM7E WUZUA A4GTN
-        "
-        and
-        "
-        generated challenge:
-
-        CBYRYBEMH2Y75TC...rest of challenge
-        "
-        support extracting the challenge from both.
-
-        Returns:
-            The RMA challenge with all whitespace removed.
-        """
-        output = self.send_cmd_get_output('rma_auth').strip()
-        logging.info('rma_auth output:\n%s', output)
-        # Extract the challenge from the console output
-        if 'generated challenge:' in output:
-            return output.split('generated challenge:')[-1].strip()
-        challenge = ''.join(re.findall(r' \S{5}' * 4, output))
-        # Remove all whitespace
-        return re.sub(r'\s', '', challenge)
-
-    def generate_challenge_url(self, hwid):
-        """Get the rma_auth challenge
-
-        Returns:
-            The RMA challenge with all whitespace removed.
-        """
-
-        challenge = self.get_rma_challenge()
-        self.print_platform_info()
-        logging.info('CHALLENGE: %s', challenge)
-        logging.info('HWID: %s', hwid)
-        url = URL % (challenge, hwid)
-        logging.info('GOTO:\n %s', url)
-        logging.info('If the server fails to debug the challenge make sure the '
-                     'RLZ is allowlisted')
-
-    def try_authcode(self, authcode):
-        """Try opening cr50 with the authcode
-
-        Raises:
-            ValueError if there was no authcode match and ccd isn't open
-        """
-        # rma_auth may cause the system to reboot. Don't wait to read all that
-        # output. Read the first 300 bytes and call it a day.
-        output = self.send_cmd_get_output('rma_auth ' + authcode, nbytes=300)
-        logging.info('CR50 RESPONSE: %s', output)
-        logging.info('waiting for cr50 reboot')
-        # Cr50 may be rebooting. Wait a bit
-        time.sleep(5)
-        if self.using_ccd:
-            # After reboot, reset the ccd endpoints
-            self._dut_control('power_state:ccd_reset')
-        # Update the ccd state after the authcode attempt
-        self.update_ccd_state()
-
-        authcode_match = 'process_response: success!' in output
-        if not self.check(CCD_IS_UNRESTRICTED):
-            if not authcode_match:
-                logging.warning(DEBUG_AUTHCODE_MISMATCH)
-                message = 'Authcode mismatch. Check args and url'
-            else:
-                message = 'Could not set all capability privileges to Always'
-            raise ValueError(message)
-
-    def wp_is_force_disabled(self):
-        """Returns True if write protect is forced disabled"""
-        output = self.send_cmd_get_output('wp')
-        wp_state = output.split('Flash WP:', 1)[-1].split('\n', 1)[0].strip()
-        logging.info('wp: %s', wp_state)
-        return wp_state == 'forced disabled'
-
-    def testlab_is_enabled(self):
-        """Returns True if testlab mode is enabled"""
-        output = self.send_cmd_get_output('ccd testlab')
-        testlab_state = output.split('mode')[-1].strip().lower()
-        logging.info('testlab: %s', testlab_state)
-        return testlab_state == 'enabled'
-
-    def ccd_is_restricted(self):
-        """Returns True if any of the capabilities are still restricted"""
-        output = self.send_cmd_get_output('ccd')
-        if 'Capabilities' not in output:
-            raise ValueError('Could not get ccd output')
-        logging.debug('CURRENT CCD SETTINGS:\n%s', output)
-        restricted = 'IfOpened' in output or 'IfUnlocked' in output
-        logging.info('ccd: %srestricted', '' if restricted else 'Un')
-        return restricted
-
-    def update_ccd_state(self):
-        """Get the wp and ccd state from cr50. Save it in _ccd_state"""
-        self._ccd_state = 0
-        if not self.ccd_is_restricted():
-            self._ccd_state |= CCD_IS_UNRESTRICTED
-        if self.wp_is_force_disabled():
-            self._ccd_state |= WP_IS_DISABLED
-        if self.testlab_is_enabled():
-            self._ccd_state |= TESTLAB_IS_ENABLED
-
-    def check(self, setting):
-        """Returns true if the all of the 1s in setting are 1 in _ccd_state"""
-        return self._ccd_state & setting == setting
-
-    def _has_testlab_support(self):
-        """Return True if you can enable testlab mode"""
-        # all prepvt images can enable testlab
-        if self.is_prepvt:
-            return True
-        return not self._running_version_is_older(DEV_MODE_OPEN_PROD)
-
-    def _capabilities_allow_open_from_console(self):
-        """Return True if ccd open is Always allowed from usb"""
-        output = self.send_cmd_get_output('ccd')
-        return (re.search('OpenNoDevMode.*Always', output) and
-                re.search('OpenFromUSB.*Always', output))
-
-    def _requires_dev_mode_open(self):
-        """Return True if the image requires dev mode to open"""
-        if self._capabilities_allow_open_from_console():
-            return False
-        # All prod images that support 'open' require dev mode
-        if not self.is_prepvt:
-            return True
-        return not self._running_version_is_older(DEV_MODE_OPEN_PREPVT)
-
-    def _run_on_dut(self, command):
-        """Run the command on the DUT."""
-        return subprocess.check_output(['ssh', self.ip, command],
-                                       encoding='utf-8')
-
-    def _open_in_dev_mode(self):
-        """Open Cr50 when it's in dev mode"""
-        output = self.send_cmd_get_output('ccd')
-        # If the device is already open, nothing needs to be done.
-        if 'State: Open' not in output:
-            # Verify the device is in devmode before trying to run open.
-            if 'dev_mode' not in output:
-                logging.warning('Enter dev mode to open ccd or update to %s',
-                                TESTLAB_PROD)
-                raise ValueError('DUT not in dev mode')
-            if not self.ip:
-                logging.warning("If your DUT doesn't have ssh support, run "
-                                "'gsctool -a -o' from the AP")
-                raise ValueError('Cannot run ccd open without dut ip')
-            self._run_on_dut('gsctool -a -o')
-            # Wait >1 second for cr50 to update ccd state
-            time.sleep(3)
-            output = self.send_cmd_get_output('ccd')
-            if 'State: Open' not in output:
-                raise ValueError('Could not open cr50')
-        logging.info('ccd is open')
-
-    def enable_testlab(self):
-        """Disable write protect"""
-        if not self._has_testlab_support():
-            logging.warning('Testlab mode is not supported in prod iamges')
-            return
-        # Some cr50 images need to be in dev mode before they can be opened.
-        if self._requires_dev_mode_open():
-            self._open_in_dev_mode()
-        else:
-            self.send_cmd_get_output('ccd open')
-        logging.info('Enabling testlab mode reqires pressing the power button.')
-        logging.info('Once the process starts keep tapping the power button '
-                     'for 10 seconds.')
-        input("Press Enter when you're ready to start...")
-        end_time = time.time() + 15
-
-        ser = serial.Serial(self.device, timeout=1)
-        printed_lines = ''
-        output = ''
-        # start ccd testlab enable
-        ser.write(self.ENABLE_TESTLAB_CMD.encode('utf-8'))
-        logging.info('start pressing the power button\n\n')
-        # Print all of the cr50 output as we get it, so the user will have more
-        # information about pressing the power button. Tapping the power button
-        # a couple of times should do it, but this will give us more confidence
-        # the process is still running/worked.
-        try:
-            while time.time() < end_time:
-                output += ser.read(100).decode('utf-8')
-                full_lines = output.rsplit('\n', 1)[0]
-                new_lines = full_lines
-                if printed_lines:
-                    new_lines = full_lines.split(printed_lines, 1)[-1].strip()
-                logging.info('\n%s', new_lines)
-                printed_lines = full_lines
-
-                # Make sure the process hasn't ended. If it has, print the last
-                # of the output and exit.
-                new_lines = output.split(printed_lines, 1)[-1]
-                if 'CCD test lab mode enabled' in output:
-                    # print the last of the ou
-                    logging.info(new_lines)
-                    break
-                elif 'Physical presence check timeout' in output:
-                    logging.info(new_lines)
-                    logging.warning('Did not detect power button press in time')
-                    raise ValueError('Could not enable testlab mode try again')
-        finally:
-            ser.close()
-        # Wait for the ccd hook to update things
-        time.sleep(3)
-        # Update the state after attempting to disable write protect
-        self.update_ccd_state()
-        if not self.check(TESTLAB_IS_ENABLED):
-            raise ValueError('Could not enable testlab mode try again')
-
-    def wp_disable(self):
-        """Disable write protect"""
-        logging.info('Disabling write protect')
-        self.send_cmd_get_output('wp disable')
-        # Update the state after attempting to disable write protect
-        self.update_ccd_state()
-        if not self.check(WP_IS_DISABLED):
-            raise ValueError('Could not disable write protect')
-
-    def check_version(self):
-        """Make sure cr50 is running a version that supports RMA Open"""
-        output = self.send_cmd_get_output('version')
-        if not output.strip():
-            logging.warning(DEBUG_DEVICE, self.device)
-            raise ValueError('Could not communicate with %s' % self.device)
-
-        version = re.search(r'RW.*\* ([\d\.]+)/', output).group(1)
-        logging.info('Running Cr50 Version: %s', version)
-        self.running_ver_fields = [int(field) for field in version.split('.')]
-
-        # prePVT images have even major versions. Prod have odd
-        self.is_prepvt = self.running_ver_fields[1] % 2 == 0
-        rma_support = RMA_SUPPORT_PREPVT if self.is_prepvt else RMA_SUPPORT_PROD
-
-        logging.info('%s RMA support added in: %s',
-                     'prePVT' if self.is_prepvt else 'prod', rma_support)
-        if not self.is_prepvt and self._running_version_is_older(TESTLAB_PROD):
-            raise ValueError('Update cr50. No testlab support in old prod '
-                             'images.')
-        if self._running_version_is_older(rma_support):
-            raise ValueError('%s does not have RMA support. Update to at '
-                             'least %s' % (version, rma_support))
-
-    def _running_version_is_older(self, target_ver):
-        """Returns True if running version is older than target_ver."""
-        target_ver_fields = [int(field) for field in target_ver.split('.')]
-        for i, field in enumerate(self.running_ver_fields):
-            if field > int(target_ver_fields[i]):
-                return False
-        return True
-
-    def device_matches_devid(self, devid, device):
-        """Return True if the device matches devid.
-
-        Use the sysinfo output from device to determine if it matches devid
-
-        Returns:
-            True if sysinfo from device shows the given devid. False if there
-            is no output or sysinfo doesn't contain the devid.
-        """
-        self.set_cr50_device(device)
-        sysinfo = self.send_cmd_get_output('sysinfo')
-        # Make sure there is some output, and it shows it's from Cr50
-        if not sysinfo or 'cr50' not in sysinfo:
-            return False
-        logging.debug('Sysinfo output: %s', sysinfo)
-        # The cr50 device id should be in the sysinfo output, if we found
-        # the right console. Make sure it is
-        return devid in sysinfo
-
-    def find_cr50_device(self, usb_serial):
-        """Find the cr50 console device
-
-        The Cr50 usb serialname matches the cr50 devid. Convert the serialname
-        to devid. Use that to check all of the consoles and find cr50's.
-
-        Args:
-            usb_serial: an optional string. The serialname of the cr50 usb
-                        device
-        Raises:
-            ValueError if the console can't be found with the given serialname
-        """
-        usb_serial = self.find_cr50_usb(usb_serial)
-        logging.info('SERIALNAME: %s', usb_serial)
-        devid = '0x' + ' 0x'.join(usb_serial.lower().split('-'))
-        logging.info('DEVID: %s', devid)
-
-        # Get all the usb devices
-        devices = glob.glob('/dev/ttyUSB*')
-        # Typically Cr50 has the lowest number. Sort the devices, so we're more
-        # likely to try the cr50 console first.
-        devices.sort()
-
-        # Find the one that is the cr50 console
-        for device in devices:
-            logging.info('testing %s', device)
-            if self.device_matches_devid(devid, device):
-                logging.info('found device: %s', device)
-                return
-        logging.warning(DEBUG_CONNECTION)
-        raise ValueError('Found USB device, but could not communicate with '
-                         'cr50 console')
-
-    def print_platform_info(self):
-        """Print the cr50 BID RLZ code"""
-        bid_output = self.send_cmd_get_output('bid')
-        bid = re.search(r'Board ID: (\S+?)[:,]', bid_output).group(1)
-        if bid == ERASED_BID:
-            logging.warning(DEBUG_ERASED_BOARD_ID)
-            raise ValueError('Cannot run RMA Open when board id is erased')
-        bid = int(bid, 16)
-        chrs = [chr((bid >> (8 * i)) & 0xff) for i in range(4)]
-        logging.info('RLZ: %s', ''.join(chrs[::-1]))
-
-    @staticmethod
-    def find_cr50_usb(usb_serial):
-        """Make sure the Cr50 USB device exists"""
-        try:
-            output = subprocess.check_output(CR50_LSUSB_CMD, encoding='utf-8')
-        except:
-            logging.warning(DEBUG_MISSING_USB)
-            raise ValueError('Could not find Cr50 USB device')
-        serialnames = re.findall(r'iSerial +\d+ (\S+)\s', output)
-        if usb_serial:
-            if usb_serial not in serialnames:
-                logging.warning(DEBUG_SERIALNAME)
-                raise ValueError('Could not find usb device "%s"' % usb_serial)
-            return usb_serial
-        if len(serialnames) > 1:
-            logging.info('Found Cr50 device serialnames %s',
-                         ', '.join(serialnames))
-            logging.warning(DEBUG_TOO_MANY_USB_DEVICES)
-            raise ValueError('Too many cr50 usb devices')
-        return serialnames[0]
-
-    def print_dut_state(self):
-        """Print CCD RMA and testlab mode state."""
-        if not self.check(CCD_IS_UNRESTRICTED):
-            logging.info('CCD is still restricted.')
-            logging.info('Run cr50_rma_open.py -g -i $HWID to generate a url')
-            logging.info('Run cr50_rma_open.py -a $AUTHCODE to open cr50 with '
-                         'an authcode')
-        elif not self.check(WP_IS_DISABLED):
-            logging.info('WP is still enabled.')
-            logging.info('Run cr50_rma_open.py -w to disable write protect')
-        if self.check(RMA_OPENED):
-            logging.info('RMA Open complete')
-
-        if not self.check(TESTLAB_IS_ENABLED) and self.is_prepvt:
-            logging.info('testlab mode is disabled.')
-            logging.info('If you are prepping a device for the testlab, you '
-                         'should enable testlab mode.')
-            logging.info('Run cr50_rma_open.py -t to enable testlab mode')
-
-
-def parse_args(argv):
-    """Get cr50_rma_open args."""
-    parser = argparse.ArgumentParser(
-        description=__doc__, formatter_class=argparse.RawTextHelpFormatter)
-    parser.add_argument('-g', '--generate_challenge', action='store_true',
-                        help='Generate Cr50 challenge. Must be used with -i')
-    parser.add_argument('-t', '--enable_testlab', action='store_true',
-                        help='enable testlab mode')
-    parser.add_argument('-w', '--wp_disable', action='store_true',
-                        help='Disable write protect')
-    parser.add_argument('-c', '--check_connection', action='store_true',
-                        help='Check cr50 console connection works')
-    parser.add_argument('-s', '--serialname', type=str, default='',
-                        help='The cr50 usb serialname')
-    parser.add_argument('-D', '--debug', action='store_true',
-                        help='print debug messages')
-    parser.add_argument('-d', '--device', type=str, default='',
-                        help='cr50 console device ex /dev/ttyUSB0')
-    parser.add_argument('-i', '--hwid', type=str, default='',
-                        help='The board hwid. Needed to generate a challenge')
-    parser.add_argument('-a', '--authcode', type=str, default='',
-                        help='The authcode string from the challenge url')
-    parser.add_argument('-P', '--servo_port', type=str, default='',
-                        help='the servo port')
-    parser.add_argument('-I', '--ip', type=str, default='',
-                        help='The DUT IP. Necessary to do ccd open')
-    return parser.parse_args(argv)
-
-
-def main(argv):
-    """Run cr50 rma open."""
-    opts = parse_args(argv)
-
-    loglevel = logging.INFO
-    log_format = '%(levelname)7s'
-    if opts.debug:
-        loglevel = logging.DEBUG
-        log_format += ' - %(lineno)3d:%(funcName)-15s'
-    log_format += ' - %(message)s'
-    logging.basicConfig(level=loglevel, format=log_format)
-
-    tried_authcode = False
-    logging.info('Running cr50_rma_open version %s', SCRIPT_VERSION)
-
-    cr50_rma_open = RMAOpen(opts.device, opts.serialname, opts.servo_port,
-                            opts.ip)
-    if opts.check_connection:
-        sys.exit(0)
-
-    if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-        if opts.generate_challenge:
-            if not opts.hwid:
-                logging.warning('--hwid necessary to generate challenge url')
-                sys.exit(0)
-            cr50_rma_open.generate_challenge_url(opts.hwid)
-            sys.exit(0)
-        elif opts.authcode:
-            logging.info('Using authcode: %s', opts.authcode)
-            cr50_rma_open.try_authcode(opts.authcode)
-            tried_authcode = True
-
-    if not cr50_rma_open.check(WP_IS_DISABLED) and (tried_authcode or
-                                                    opts.wp_disable):
-        if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't disable write protect unless ccd is "
-                             "open. Run through the rma open process first")
-        if tried_authcode:
-            logging.warning('RMA Open did not disable write protect. File a '
-                            'bug')
-            logging.warning('Trying to disable it manually')
-        cr50_rma_open.wp_disable()
-
-    if not cr50_rma_open.check(TESTLAB_IS_ENABLED) and opts.enable_testlab:
-        if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't enable testlab mode unless ccd is open."
-                             "Run through the rma open process first")
-        cr50_rma_open.enable_testlab()
-
-    cr50_rma_open.print_dut_state()
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/extra/ftdi_hostcmd/.gitignore b/extra/ftdi_hostcmd/.gitignore
deleted file mode 100644
index 9831af29be..0000000000
--- a/extra/ftdi_hostcmd/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-test_cmds
diff --git a/extra/ftdi_hostcmd/Makefile b/extra/ftdi_hostcmd/Makefile
deleted file mode 100644
index d46b4b1c72..0000000000
--- a/extra/ftdi_hostcmd/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Use your own libmpsse if you want, but we're going to use the files
-# that are part of the Chromium OS trunks_client program.
-PLATFORM2 = ../../../../platform2
-MPSSE_DIR = $(PLATFORM2)/trunks/ftdi
-
-PROG = test_cmds
-SRCS = test_cmds.c $(MPSSE_DIR)/mpsse.c $(MPSSE_DIR)/support.c
-
-CFLAGS = \
-	-std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-CFLAGS += -I../../include -I${MPSSE_DIR} -I${PLATFORM2}
-
-CFLAGS += $(shell pkg-config --cflags libusb-1.0 libftdi1)
-LIBS   += $(shell pkg-config --libs   libusb-1.0 libftdi1)
-
-$(PROG): $(SRCS) Makefile
-	gcc $(CFLAGS) $(SRCS) $(LDFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-clean:
-	rm -rf $(PROG)
diff --git a/extra/ftdi_hostcmd/README b/extra/ftdi_hostcmd/README
deleted file mode 100644
index 4de2f45fb3..0000000000
--- a/extra/ftdi_hostcmd/README
+++ /dev/null
@@ -1,6 +0,0 @@
-
-Ubuntu Trusty uses an ancient version of libftdi.
-
-You'll probably want to grab the latest libftdi1-1.2.tar.bz2 from
-http://www.intra2net.com/en/developer/libftdi/ and install it into /usr
-instead.
diff --git a/extra/ftdi_hostcmd/test_cmds.c b/extra/ftdi_hostcmd/test_cmds.c
deleted file mode 100644
index 4552476d0f..0000000000
--- a/extra/ftdi_hostcmd/test_cmds.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "mpsse.h"
-
-#include "ec_commands.h"
-
-static int opt_verbose;
-
-/* Communication handle */
-static struct mpsse_context *mpsse;
-
-/* enum ec_status meaning */
-static const char *ec_strerr(enum ec_status r)
-{
-	static const char * const strs[] = {
-		"SUCCESS",
-		"INVALID_COMMAND",
-		"ERROR",
-		"INVALID_PARAM",
-		"ACCESS_DENIED",
-		"INVALID_RESPONSE",
-		"INVALID_VERSION",
-		"INVALID_CHECKSUM",
-		"IN_PROGRESS",
-		"UNAVAILABLE",
-		"TIMEOUT",
-		"OVERFLOW",
-		"INVALID_HEADER",
-		"REQUEST_TRUNCATED",
-		"RESPONSE_TOO_BIG",
-		"BUS_ERROR",
-		"BUSY",
-	};
-	if (r >= EC_RES_SUCCESS && r <= EC_RES_BUSY)
-		return strs[r];
-
-	return "<undefined result>";
-};
-
-
-/****************************************************************************
- * Debugging output
- */
-
-#define LINELEN 16
-
-static void showline(uint8_t *buf, int len)
-{
-	int i;
-	printf("  ");
-	for (i = 0; i < len; i++)
-		printf(" %02x", buf[i]);
-	for (i = len; i < LINELEN; i++)
-		printf("   ");
-	printf("    ");
-	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
-	printf("\n");
-}
-
-static void show(const char *fmt, uint8_t *buf, int len)
-{
-	int i, m, n;
-
-	if (!opt_verbose)
-		return;
-
-	printf(fmt, len);
-
-	m = len / LINELEN;
-	n = len % LINELEN;
-
-	for (i = 0; i < m; i++)
-		showline(buf + i * LINELEN, LINELEN);
-	if (n)
-		showline(buf + m * LINELEN, n);
-}
-
-/****************************************************************************
- * Send command & receive result
- */
-
-/*
- * With proto v3, the kernel driver asks the EC for the max param size
- * (EC_CMD_GET_PROTOCOL_INFO) at probe time, because it can vary depending on
- * the bus and/or the supported commands.
- *
- * FIXME: For now we'll just hard-code a size.
- */
-static uint8_t txbuf[128];
-
-/*
- * Load the output buffer with a proto v3 request (header, then data, with
- * checksum correct in header).
- */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
-{
-	struct ec_host_request *request;
-	size_t i, total_len;
-	uint8_t csum = 0;
-
-	total_len = sizeof(*request) + data_len;
-	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
-		return -1;
-	}
-
-	/* Header first */
-	request = (struct ec_host_request *)txbuf;
-	request->struct_version = EC_HOST_REQUEST_VERSION;
-	request->checksum = 0;
-	request->command = cmd;
-	request->command_version = version;
-	request->reserved = 0;
-	request->data_len = data_len;
-
-	/* Then data */
-	memcpy(txbuf + sizeof(*request), data, data_len);
-
-	/* Update checksum */
-	for (i = 0; i < total_len; i++)
-		csum += txbuf[i];
-	request->checksum = -csum;
-
-	return total_len;
-}
-
-/*
- * Sends prepared proto v3 command using the SPI protocol
- *
- * Returns zero if command was sent, nonzero otherwise.
- */
-static int send_request(uint8_t *txbuf, size_t len)
-{
-	uint8_t *tptr;
-	size_t i;
-	int ret = 0;
-
-	show("Transfer(%d) =>\n", txbuf, len);
-	tptr = Transfer(mpsse, txbuf, len);
-
-	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
-		return -1;
-	}
-
-	show("Transfer(%d) <=\n", tptr, len);
-
-	/* Make sure the EC was listening */
-	for (i = 0; i < len; i++) {
-		switch (tptr[i]) {
-		case EC_SPI_PAST_END:
-		case EC_SPI_RX_BAD_DATA:
-		case EC_SPI_NOT_READY:
-			ret = tptr[i];
-			/* FALLTHROUGH */
-		default:
-			break;
-		}
-		if (ret)
-			break;
-	}
-	free(tptr);
-	return ret;
-}
-
-
-/* Timeout flag, so we don't wait forever */
-static int timedout;
-static void alarm_handler(int sig)
-{
-	timedout = 1;
-}
-
-/*
- * Read proto v3 response from SPI bus
- *
- * The response header and data are copied into the provided locations.
- *
- * Return value:
- *   0   = response received (check hdr for EC result and body size)
- *   -1  = problems
- */
-static int get_response(struct ec_host_response *hdr,
-			uint8_t *bodydest, size_t bodylen)
-{
-	uint8_t *hptr = 0, *bptr = 0;
-	uint8_t sum = 0;
-	int ret = -1;
-	size_t i;
-
-	/* Give up eventually */
-	timedout = 0;
-	if (SIG_ERR == signal(SIGALRM, alarm_handler)) {
-		perror("Problem with signal handler");
-		goto out;
-	}
-	alarm(3);
-
-	/* Read a byte at a time until we see the start of the frame.
-	 * This is slow, but still faster than the EC. */
-	while (1) {
-		uint8_t *ptr = Read(mpsse, 1);
-		if (!ptr) {
-			fprintf(stderr, "Read failed: %s\n",
-				ErrorString(mpsse));
-			alarm(0);
-			goto out;
-		}
-		if (*ptr == EC_SPI_FRAME_START) {
-			free(ptr);
-			break;
-		}
-		free(ptr);
-
-		if (timedout) {
-			fprintf(stderr, "timed out\n");
-			goto out;
-		}
-	}
-	alarm(0);
-
-	/* Now read the response header */
-	hptr = Read(mpsse, sizeof(*hdr));
-	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
-		goto out;
-	}
-	show("Header(%d):\n", hptr, sizeof(*hdr));
-	memcpy(hdr, hptr, sizeof(*hdr));
-
-	/* Check the header */
-	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
-		printf("response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
-		goto out;
-	}
-
-	if (hdr->data_len > bodylen) {
-		printf("response data_len %d is > %zd\n",
-		       hdr->data_len,
-		       bodylen);
-		goto out;
-	}
-
-	/* Read the data */
-	if (hdr->data_len) {
-		bptr = Read(mpsse, hdr->data_len);
-		if (!bptr) {
-			fprintf(stderr, "Read failed: %s\n",
-				ErrorString(mpsse));
-			goto out;
-		}
-		show("Body(%d):\n", bptr, hdr->data_len);
-		memcpy(bodydest, bptr, hdr->data_len);
-	}
-
-	/* Verify the checksum */
-	for (i = 0; i < sizeof(hdr); i++)
-		sum += hptr[i];
-	for (i = 0; i < hdr->data_len; i++)
-		sum += bptr[i];
-	if (sum)
-
-		printf("Checksum invalid\n");
-	else
-		ret = 0;
-
-out:
-	if (hptr)
-		free(hptr);
-	if (bptr)
-		free(bptr);
-	return ret;
-}
-
-
-/*
- * Send command, wait for result. Return zero if communication succeeded; check
- * response to see if the EC liked the command.
- */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *resp,
-		    void *inbuf,
-		    size_t insize)
-{
-
-	size_t len;
-	int ret = -1;
-
-	/* Load up the txbuf with the stuff to send */
-	len = prepare_request(cmd, version, outbuf, outsize);
-	if (len < 0)
-		return -1;
-
-	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
-		return -1;
-	}
-
-	if (0 == send_request(txbuf, len) &&
-	    0 == get_response(resp, inbuf, insize))
-		ret = 0;
-
-	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
-		return -1;
-	}
-
-	return ret;
-}
-
-
-/****************************************************************************
- * Probe for basic protocol info
- */
-
-/**
- * Try to talk to the attached(?) device.
- *
- * @return  zero on success
- */
-static int probe_v3(void)
-{
-	struct ec_host_response resp;
-	struct ec_response_get_protocol_info info;
-	int i, ret;
-
-	memset(&resp, 0, sizeof(resp));
-	memset(&info, 0, sizeof(info));
-
-	if (opt_verbose)
-		printf("Trying EC_CMD_GET_PROTOCOL_INFO...\n");
-
-	ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0,
-		       0, 0,
-		       &resp,
-		       &info, sizeof(info));
-
-	if (ret) {
-		printf("EC_CMD_GET_PROTOCOL_INFO failed\n");
-		return -1;
-	}
-
-	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
-		return -1;
-	}
-
-	printf("EC_CMD_GET_PROTOCOL_INFO Success!\n");
-	printf("  protocol_versions:         ");
-	for (i = 0; i < 32; i++)
-		if (info.protocol_versions & (1 << i))
-			printf(" %d", i);
-	printf("\n");
-	printf("  max_request_packet_size:    %d\n",
-	       info.max_request_packet_size);
-	printf("  max_response_packet_size:   %d\n",
-	       info.max_response_packet_size);
-	printf("  flags:                      0x%x\n",
-	       info.flags);
-
-	return 0;
-}
-
-/****************************************************************************
- * Pretty-print the host commands that the device admits to having
- */
-
-struct lookup {
-	uint16_t cmd;
-	const char * const desc;
-};
-
-static struct lookup cmd_table[] = {
-	{0x00, "EC_CMD_PROTO_VERSION"},
-	{0x01, "EC_CMD_HELLO"},
-	{0x02, "EC_CMD_GET_VERSION"},
-	{0x03, "EC_CMD_READ_TEST"},
-	{0x04, "EC_CMD_GET_BUILD_INFO"},
-	{0x05, "EC_CMD_GET_CHIP_INFO"},
-	{0x06, "EC_CMD_GET_BOARD_VERSION"},
-	{0x07, "EC_CMD_READ_MEMMAP"},
-	{0x08, "EC_CMD_GET_CMD_VERSIONS"},
-	{0x09, "EC_CMD_GET_COMMS_STATUS"},
-	{0x0a, "EC_CMD_TEST_PROTOCOL"},
-	{0x0b, "EC_CMD_GET_PROTOCOL_INFO"},
-	{0x0c, "EC_CMD_GSV_PAUSE_IN_S5"},
-	{0x0d, "EC_CMD_GET_FEATURES"},
-	{0x10, "EC_CMD_FLASH_INFO"},
-	{0x11, "EC_CMD_FLASH_READ"},
-	{0x12, "EC_CMD_FLASH_WRITE"},
-	{0x13, "EC_CMD_FLASH_ERASE"},
-	{0x15, "EC_CMD_FLASH_PROTECT"},
-	{0x16, "EC_CMD_FLASH_REGION_INFO"},
-	{0x17, "EC_CMD_VBNV_CONTEXT"},
-	{0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM"},
-	{0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM"},
-	{0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT"},
-	{0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT"},
-	{0x24, "EC_CMD_PWM_SET_FAN_DUTY"},
-	{0x28, "EC_CMD_LIGHTBAR_CMD"},
-	{0x29, "EC_CMD_LED_CONTROL"},
-	{0x2a, "EC_CMD_VBOOT_HASH"},
-	{0x2b, "EC_CMD_MOTION_SENSE_CMD"},
-	{0x2c, "EC_CMD_FORCE_LID_OPEN"},
-	{0x30, "EC_CMD_USB_CHARGE_SET_MODE"},
-	{0x40, "EC_CMD_PSTORE_INFO"},
-	{0x41, "EC_CMD_PSTORE_READ"},
-	{0x42, "EC_CMD_PSTORE_WRITE"},
-	{0x44, "EC_CMD_RTC_GET_VALUE"},
-	{0x45, "EC_CMD_RTC_GET_ALARM"},
-	{0x46, "EC_CMD_RTC_SET_VALUE"},
-	{0x47, "EC_CMD_RTC_SET_ALARM"},
-	{0x48, "EC_CMD_PORT80_LAST_BOOT"},
-	{0x48, "EC_CMD_PORT80_READ"},
-	{0x50, "EC_CMD_THERMAL_SET_THRESHOLD"},
-	{0x51, "EC_CMD_THERMAL_GET_THRESHOLD"},
-	{0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL"},
-	{0x53, "EC_CMD_TMP006_GET_CALIBRATION"},
-	{0x54, "EC_CMD_TMP006_SET_CALIBRATION"},
-	{0x55, "EC_CMD_TMP006_GET_RAW"},
-	{0x60, "EC_CMD_MKBP_STATE"},
-	{0x61, "EC_CMD_MKBP_INFO"},
-	{0x62, "EC_CMD_MKBP_SIMULATE_KEY"},
-	{0x64, "EC_CMD_MKBP_SET_CONFIG"},
-	{0x65, "EC_CMD_MKBP_GET_CONFIG"},
-	{0x66, "EC_CMD_KEYSCAN_SEQ_CTRL"},
-	{0x67, "EC_CMD_GET_NEXT_EVENT"},
-	{0x70, "EC_CMD_TEMP_SENSOR_GET_INFO"},
-	{0x87, "EC_CMD_HOST_EVENT_GET_B"},
-	{0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK"},
-	{0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK"},
-	{0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK"},
-	{0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK"},
-	{0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK"},
-	{0x8c, "EC_CMD_HOST_EVENT_CLEAR"},
-	{0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK"},
-	{0x8f, "EC_CMD_HOST_EVENT_CLEAR_B"},
-	{0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT"},
-	{0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS"},
-	{0x92, "EC_CMD_GPIO_SET"},
-	{0x93, "EC_CMD_GPIO_GET"},
-	{0x94, "EC_CMD_I2C_READ"},
-	{0x95, "EC_CMD_I2C_WRITE"},
-	{0x96, "EC_CMD_CHARGE_CONTROL"},
-	{0x97, "EC_CMD_CONSOLE_SNAPSHOT"},
-	{0x98, "EC_CMD_CONSOLE_READ"},
-	{0x99, "EC_CMD_BATTERY_CUT_OFF"},
-	{0x9a, "EC_CMD_USB_MUX"},
-	{0x9b, "EC_CMD_LDO_SET"},
-	{0x9c, "EC_CMD_LDO_GET"},
-	{0x9d, "EC_CMD_POWER_INFO"},
-	{0x9e, "EC_CMD_I2C_PASSTHRU"},
-	{0x9f, "EC_CMD_HANG_DETECT"},
-	{0xa0, "EC_CMD_CHARGE_STATE"},
-	{0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT"},
-	{0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT"},
-	{0xb0, "EC_CMD_SB_READ_WORD"},
-	{0xb1, "EC_CMD_SB_WRITE_WORD"},
-	{0xb2, "EC_CMD_SB_READ_BLOCK"},
-	{0xb3, "EC_CMD_SB_WRITE_BLOCK"},
-	{0xb4, "EC_CMD_BATTERY_VENDOR_PARAM"},
-	{0xb5, "EC_CMD_SB_FW_UPDATE"},
-	{0xd2, "EC_CMD_REBOOT_EC"},
-	{0xd3, "EC_CMD_GET_PANIC_INFO"},
-	{0xd1, "EC_CMD_REBOOT"},
-	{0xdb, "EC_CMD_RESEND_RESPONSE"},
-	{0xdc, "EC_CMD_VERSION0"},
-	{0x100, "EC_CMD_PD_EXCHANGE_STATUS"},
-	{0x104, "EC_CMD_PD_HOST_EVENT_STATUS"},
-	{0x101, "EC_CMD_USB_PD_CONTROL"},
-	{0x102, "EC_CMD_USB_PD_PORTS"},
-	{0x103, "EC_CMD_USB_PD_POWER_INFO"},
-	{0x110, "EC_CMD_USB_PD_FW_UPDATE"},
-	{0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY"},
-	{0x112, "EC_CMD_USB_PD_DEV_INFO"},
-	{0x113, "EC_CMD_USB_PD_DISCOVERY"},
-	{0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE"},
-	{0x115, "EC_CMD_PD_GET_LOG_ENTRY"},
-	{0x116, "EC_CMD_USB_PD_GET_AMODE"},
-	{0x117, "EC_CMD_USB_PD_SET_AMODE"},
-	{0x118, "EC_CMD_PD_WRITE_LOG_ENTRY"},
-	{0x200, "EC_CMD_BLOB"},
-};
-
-#define ARRAY_SIZE(A) (sizeof(A) / sizeof(A[0]))
-
-static void show_command(uint16_t c)
-{
-	unsigned int i;
-	const char *desc = "<unknown>";
-
-	for (i = 0; i < ARRAY_SIZE(cmd_table); i++)
-		if (cmd_table[i].cmd == c) {
-			desc = cmd_table[i].desc;
-			break;
-		}
-
-	printf("  %02x  %s\n", c, desc);
-}
-
-static void scan_commands(uint16_t start, uint16_t stop)
-{
-	struct ec_params_get_cmd_versions_v1 q_vers;
-	struct ec_response_get_cmd_versions r_vers;
-	struct ec_host_response ec_resp;
-	uint16_t i;
-
-	memset(&ec_resp, 0, sizeof(ec_resp));
-
-	printf("Supported host commands:\n");
-	for (i = start; i <= stop; i++) {
-
-		if (opt_verbose)
-			printf("Querying CMD %02x\n", i);
-
-		q_vers.cmd = i;
-		if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1,
-				  &q_vers, sizeof(q_vers),
-				  &ec_resp,
-				  &r_vers, sizeof(r_vers))) {
-			printf("query failed on cmd %02x - aborting\n", i);
-			return;
-		}
-
-		switch (ec_resp.result) {
-		case EC_RES_SUCCESS:
-			if (opt_verbose)
-				printf("Yes: ");
-			show_command(i);
-			break;
-		case EC_RES_INVALID_PARAM:
-			if (opt_verbose)
-				printf("No\n");
-			break;
-		default:
-			printf("lookup of cmd %02x returned %d %s\n", i,
-			       ec_resp.result,
-			       ec_strerr(ec_resp.result));
-		}
-	}
-}
-
-/****************************************************************************/
-
-static void usage(char *progname)
-{
-	printf("Usage: %s [-v] [start [stop]]\n", progname);
-}
-
-int main(int argc, char *argv[])
-{
-	int retval = 1;
-	int errorcnt = 0;
-	int i;
-	uint16_t start = cmd_table[0].cmd;
-	uint16_t stop = cmd_table[ARRAY_SIZE(cmd_table) - 1].cmd;
-
-	while ((i = getopt(argc, argv, ":v")) != -1) {
-		switch (i) {
-		case 'v':
-			opt_verbose++;
-			break;
-		case '?':
-			printf("unrecognized option: -%c\n", optopt);
-			errorcnt++;
-			break;
-		}
-	}
-	if (errorcnt) {
-		usage(argv[0]);
-		return 1;
-	}
-
-	/* Range (no error checking) */
-	if (optind < argc)
-		start = (uint16_t)strtoull(argv[optind++], 0, 0);
-	if (optind < argc)
-		stop = (uint16_t)strtoull(argv[optind++], 0, 0);
-
-	/* Find something to talk to */
-	mpsse = MPSSE(SPI0, 1000000, 0);
-	if (!mpsse) {
-		printf("Can't find a device to open\n");
-		return 1;
-	}
-
-	if (0 != probe_v3())
-		goto out;
-
-	scan_commands(start, stop);
-
-	retval = 0;
-out:
-	Close(mpsse);
-	mpsse = 0;
-	return retval;
-}
diff --git a/extra/i2c_pseudo/.gitignore b/extra/i2c_pseudo/.gitignore
deleted file mode 100644
index 98ec2e970f..0000000000
--- a/extra/i2c_pseudo/.gitignore
+++ /dev/null
@@ -1,10 +0,0 @@
-.i2c-pseudo.ko.cmd
-.i2c-pseudo.mod.o.cmd
-.i2c-pseudo.o.cmd
-.tmp_versions/
-Module.symvers
-i2c-pseudo.ko
-i2c-pseudo.mod.c
-i2c-pseudo.mod.o
-i2c-pseudo.o
-modules.order
diff --git a/extra/i2c_pseudo/50-i2c-pseudo.rules b/extra/i2c_pseudo/50-i2c-pseudo.rules
deleted file mode 100644
index 22a4c8daf0..0000000000
--- a/extra/i2c_pseudo/50-i2c-pseudo.rules
+++ /dev/null
@@ -1 +0,0 @@
-DEVPATH=="/devices/virtual/i2c-pseudo/*", GROUP="plugdev", MODE="0660"
diff --git a/extra/i2c_pseudo/Documentation.txt b/extra/i2c_pseudo/Documentation.txt
deleted file mode 100644
index 77de99574b..0000000000
--- a/extra/i2c_pseudo/Documentation.txt
+++ /dev/null
@@ -1,291 +0,0 @@
-----Introduction----
-
-Usually I2C adapters are implemented in a kernel driver.  It is also possible to
-implement an adapter in userspace, through the /dev/i2c-pseudo-controller
-interface.  Load module i2c-pseudo for this.
-
-Use cases for this module include:
-
-[A] Using local I2C device drivers, particularly i2c-dev, with I2C busses on
-remote systems.  For example, interacting with a Device Under Test (DUT)
-connected to a Linux host through a debug interface, or interacting with a
-remote host over a network.
-
-[B] Support I2C device driver tests that are too complex for the i2c-stub
-module.  For example, when simulating an I2C device where its driver might
-issue a sequence of reads and writes without interruption, and the value a
-certain address must change during the sequence.
-
-Any possible use case could of course be implemented as a kernel driver.
-However, it can be much faster and easier to implement such things in userspace,
-thanks to the far greater code reuse possibilities (libraries), the plethora of
-programming language options for rapid iteration, and not needing to understand
-how to implement Linux kernel drivers.
-
-This is not intended to replace kernel drivers for actual I2C busses on the
-local host machine.
-
-
-
-----Details----
-
-Each time /dev/i2c-pseudo-controller is opened, and the correct initialization
-command is written to it (ADAPTER_START), a new I2C adapter is created.  The
-adapter will live until its file descriptor is closed.  Multiple pseudo adapters
-can co-exist simultaneously, controlled by the same or different userspace
-processes.  When an I2C device driver sends an I2C message to a pseudo adapter,
-the message becomes readable from its file descriptor.  If a reply is written
-before the adapter timeout expires, that reply will be sent back to the I2C
-device driver.
-
-Reads and writes are buffered inside i2c-pseudo such that userspace controllers
-may split them up into arbitrarily small chunks.  Multiple commands, or portions
-of multiple commands, may be read or written together.
-
-Blocking I/O is the default.  Non-blocking I/O is supported as well, enabled by
-O_NONBLOCK.  Polling is supported, with or without non-blocking I/O.  A special
-command (ADAPTER_SHUTDOWN) is available to unblock any pollers or blocked
-reads or writes, as a convenience for a multi-threaded or multi-process program
-that wants to exit.
-
-It is safe to access a single controller fd from multiple threads or processes
-concurrently, though it is up to the controller to ensure proper ordering, and
-to ensure that writes for different commands do not get interleaved.  However,
-it is recommended (not required) that controller implementations have only one
-reader thread and one writer thread, which may or may not be the same thread.
-Avoiding multiple readers and multiple writers greatly simplifies controller
-implementation, and there is likely no performance benefit to be gained from
-concurrent reads or concurrent writes due to how i2c-pseudo serializes them
-internally.  After all, on a real I2C bus only one I2C message can be active at
-a time.
-
-Commands are newline-terminated, both those read from the controller device, and
-those written to it.
-
-
-
-----Read Commands----
-
-The commands that may be read from a pseudo controller device are:
-
-
-Read Command: I2C_ADAPTER_NUM <num>
-Example: "I2C_ADAPTER_NUM 5\n"
-
-Details: This is read in response to the GET_ADAPTER_NUM command being written.
-The number is the I2C adapter number in decimal.  This can only occur after
-ADAPTER_START, because before that the number is not known and cannot be
-predicted reliably.
-
-
-Read Command: I2C_PSEUDO_ID <num>
-Example: "I2C_PSEUDO_ID 98\n"
-
-Details: This is read in response to the GET_PSEUDO_ID command being written.
-The number is the pseudo ID in decimal.
-
-
-Read Command: I2C_BEGIN_XFER
-Example: "I2C_BEGIN_XFER\n"
-
-Details: This indicates the start of an I2C transaction request, in other words
-the start of the I2C messages from a single invocation of the I2C adapter's
-master_xfer() callback.  This can only occur after ADAPTER_START.
-
-
-Read Command: I2C_XFER_REQ <xfer_id> <msg_id> <addr> <flags> <data_len> [<write_byte>[:...]]
-Example: "I2C_XFER_REQ 3 0 0x0070 0x0000 2 AB:9F\n"
-Example: "I2C_XFER_REQ 3 1 0x0070 0x0001 4\n"
-
-Details: This is a single I2C message that a device driver requested be sent on
-the bus, in other words a single struct i2c_msg from master_xfer() msgs arg.
-
-The xfer_id is a number representing the whole I2C transaction, thus all
-I2C_XFER_REQ between a I2C_BEGIN_XFER + I2C_COMMIT_XFER pair share an xfer_id.
-The purpose is to ensure replies from the userspace controller are always
-properly matched to the intended master_xfer() request.  The first transaction
-has xfer_id 0, and it increases by 1 with each transaction, however it will
-eventually wrap back to 0 if enough transactions happen during the lifetime of a
-pseudo adapter.  It is guaranteed to have a large enough maximum value such that
-there can never be multiple outstanding transactions with the same ID, due to an
-internal limit in i2c-pseudo that will block master_xfer() calls when the
-controller is falling behind in its replies.
-
-The msg_id is a decimal number representing the index of the I2C message within
-its transaction, in other words the index in master_xfer() *msgs array arg.
-This starts at 0 after each I2C_BEGIN_XFER.  This is guaranteed to not wrap.
-
-The addr is the hexadecimal I2C address for this I2C message.  The address is
-right-aligned without any read/write bit.
-
-The flags are the same bitmask flags used in struct i2c_msg, in hexadecimal
-form.  Of particular importance to any pseudo controller is the read bit, which
-is guaranteed to be 0x1 per Linux I2C documentation.
-
-The data_len is the decimal number of either how many bytes to write that will
-follow, or how many bytes to read and reply with if this is a read request.
-
-If this is a read, data_len will be the final field in this command.  If this is
-a write, data_len will be followed by the given number of colon-separated
-hexadecimal byte values, in the format shown in the example above.
-
-
-Read Command: I2C_COMMIT_XFER
-Example: "I2C_COMMIT_XFER\n"
-
-Details: This indicates the end of an I2C transaction request, in other words
-the end of the I2C messages from a single invocation of the I2C adapter's
-master_xfer() callback.  This should be read exactly once after each
-I2C_BEGIN_XFER, with a varying number of I2C_XFER_REQ between them.
-
-
-
-----Write Commands----
-
-The commands that may be written to a pseudo controller device are:
-
-
-Write Command: SET_ADAPTER_NAME_SUFFIX <suffix>
-Example: "SET_ADAPTER_NAME_SUFFIX My Adapter\n"
-
-Details: Sets a suffix to append to the auto-generated I2C adapter name.  Only
-valid before ADAPTER_START.  A space or other separator character will be placed
-between the auto-generated name and the suffix, so there is no need to include a
-leading separator in the suffix.  If the resulting name is too long for the I2C
-adapter name field, it will be quietly truncated.
-
-
-Write Command: SET_ADAPTER_TIMEOUT_MS <ms>
-Example: "SET_ADAPTER_TIMEOUT_MS 2000\n"
-
-Details: Sets the timeout in milliseconds for each I2C transaction, in other
-words for each master_xfer() reply.  Only valid before ADAPTER_START.  The I2C
-subsystem will automatically time out transactions based on this setting.  Set
-to 0 to use the I2C subsystem default timeout.  The default timeout for new
-pseudo adapters where this command has not been used is configurable at
-i2c-pseudo module load time, and itself has a default independent from the I2C
-subsystem default.  (Though if the i2c-pseudo module level default is set to 0,
-that has the same meaning as here.)
-
-
-Write Command: ADAPTER_START
-Example: "ADAPTER_START\n"
-
-Details: Tells i2c-pseudo to actually create the I2C adapter.  Only valid once
-per open controller fd.
-
-
-Write Command: GET_ADAPTER_NUM
-Example: "GET_ADAPTER_NUM\n"
-
-Details: Asks i2c-pseudo for the number assigned to this I2C adapter by the I2C
-subsystem.  Only valid after ADAPTER_START, because before that the number
-is not known and cannot be predicted reliably.
-
-
-Write Command: GET_PSEUDO_ID
-Example: "GET_PSEUDO_ID\n"
-
-Details: Asks i2c-pseudo for the pseudo ID of this I2C adapter.  The pseudo ID
-will not be reused for the lifetime of the i2c-pseudo module, unless an internal
-counter wraps.  I2C clients can use this to track specific instances of pseudo
-adapters, even when adapter numbers have been reused.
-
-
-Write Command: I2C_XFER_REPLY <xfer_id> <msg_id> <addr> <flags> <errno> [<read_byte>[:...]]
-Example: "I2C_XFER_REPLY 3 0 0x0070 0x0000 0\n"
-Example: "I2C_XFER_REPLY 3 1 0x0070 0x0001 0 0B:29:02:D9\n"
-
-Details: This is how a pseudo controller can reply to I2C_XFER_REQ.  Only valid
-after I2C_XFER_REQ.  A pseudo controller should write one of these for each
-I2C_XFER_REQ it reads, including for failures, so that I2C device drivers need
-not wait for the adapter timeout upon failure (if failure is known sooner).
-
-The fields in common with I2C_XFER_REQ have their same meanings, and their
-values are expected to exactly match what was read in the I2C_XFER_REQ command
-that this is in reply to.
-
-The errno field is how the pseudo controller indicates success or failure for
-this I2C message.  A 0 value indicates success.  A non-zero value indicates a
-failure.  Pseudo controllers are encouraged to use errno values to encode some
-meaning in a failure response, but that is not a requirement, and the I2C
-adapter interface does not provide a way to pass per-message errno values to a
-device driver anyways.
-
-Pseudo controllers are encouraged to reply in the same order as messages were
-received, however i2c-pseudo will properly match up out-of-order replies with
-their original requests.
-
-
-Write Command: ADAPTER_SHUTDOWN
-Example: "ADAPTER_SHUTDOWN\n"
-
-Details: This tells i2c-pseudo that the pseudo controller wants to shutdown and
-intends to close the controller device fd soon.  Use of this is OPTIONAL, it is
-perfectly valid to close the controller device fd without ever using this
-command.
-
-This commands unblocks any blocked controller I/O (reads, writes, or polls), and
-that is its main purpose.
-
-Any I2C transactions attempted by a device driver after this command will fail,
-and will not be passed on to the userspace controller.
-
-This DOES NOT delete the I2C adapter.  Only closing the fd will do that.  That
-MAY CHANGE in the future, such that this does delete the I2C adapter.  (However
-this will never be required, it will always be okay to simply close the fd.)
-
-
-
-----Example userspace controller code----
-
-In C, a simple exchange between i2c-pseudo and userspace might look like the
-example below.  Note that for brevity this lacks any error checking and
-handling, which a real pseudo controller implementation should have.
-
-int fd;
-char buf[1<<12];
-
-fd = open("/dev/i2c-pseudo-controller", O_RDWR);
-/* Create the I2C adapter. */
-dprintf(fd, "ADAPTER_START\n");
-
-/*
- * Pretend this I2C adapter number is 5, and the first I2C xfer sent to it was
- * from this command (using its i2c-dev interface):
- * $ i2cset -y 5 0x70 0xC2
- *
- * Then this read would place the following into *buf:
- * "I2C_BEGIN_XFER\n"
- * "I2C_XFER_REQ 0 0 0x0070 0x0000 1 C2\n"
- * "I2C_COMMIT_XFER\n"
- */
-read(fd, buf, sizeof(buf));
-
-/* This reply would allow the i2cset command above to exit successfully. */
-dprintf(fd, "I2C_XFER_REPLY 0 0 0x0070 0x0000 0\n");
-
-/*
- * Now pretend the next I2C xfer sent to this adapter was from:
- * $ i2cget -y 5 0x70 0xAB
- *
- * Then this read would place the following into *buf:
- * "I2C_BEGIN_XFER\n"
- * "I2C_XFER_REQ 1 0 0x0070 0x0000 1 AB\n"
- * "I2C_XFER_REQ 1 1 0x0070 0x0001 1\n'"
- * "I2C_COMMIT_XFER\n"
- */
-read(fd, buf, sizeof(buf));
-
-/*
- * These replies would allow the i2cget command above to print the following to
- * stdout and exit successfully:
- * 0x0b
- *
- * Note that it is also valid to write these together in one write().
- */
-dprintf(fd, "I2C_XFER_REPLY 1 0 0x0070 0x0000 0\n");
-dprintf(fd, "I2C_XFER_REPLY 1 1 0x0070 0x0001 0 0B\n");
-
-/* Destroy the I2C adapter. */
-close(fd);
diff --git a/extra/i2c_pseudo/Makefile b/extra/i2c_pseudo/Makefile
deleted file mode 100644
index f7fda6e2de..0000000000
--- a/extra/i2c_pseudo/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Makefile for i2c-pseudo module.  Typical usage:
-#   $ make
-#   $ sudo make modules_install
-#   $ make clean
-
-obj-m := i2c-pseudo.o
-
-.PHONY: all
-
-all: modules
-
-CFLAGS_i2c-pseudo.o += "-DHAVE_STREAM_OPEN=$(shell "$M"/check_stream_open.sh)"
-
-.DEFAULT:
-	$(MAKE) -C /lib/modules/$(shell uname -r)/build \
-		M=$(shell pwd) \
-		$(MAKECMDGOALS)
diff --git a/extra/i2c_pseudo/README b/extra/i2c_pseudo/README
deleted file mode 100644
index 96efa062b1..0000000000
--- a/extra/i2c_pseudo/README
+++ /dev/null
@@ -1,20 +0,0 @@
-This directory contains the i2c-pseudo Linux kernel module.
-
-The i2c-pseudo module was written with the intention of being submitted upstream
-in the Linux kernel.  This copy exists because of as 2019-03 this module is not
-yet in the upstream kernel, and even if/when this is included, it may take years
-before making its way to the prepackaged Linux distribution kernels typically
-used by CrOS developers.
-
-See Documentation.txt for more information about the module itself.  That file
-is Documentation/i2c/pseudo-controller-interface in the upstream patch.
-
-When servod starts, if the i2c-pseudo module is loaded servod will automatically
-create an I2C pseudo adapter for the Servo I2C bus.  That I2C adapter may then
-be used in userspace through i2c-dev (/dev/i2c-<N>).  The i2c-tools package
-provides command line utilities for interfacing with i2c-dev devices, and some
-CrOS software can work directly with i2c-dev devices as well, such as iteflash
-which is used by flash_ec when reflashing an ITE EC through a Servo.
-
-Automated installation:
-$ ./install
diff --git a/extra/i2c_pseudo/check_stream_open.sh b/extra/i2c_pseudo/check_stream_open.sh
deleted file mode 100755
index da802cb282..0000000000
--- a/extra/i2c_pseudo/check_stream_open.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/sh
-#
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# This checks whether stream_open symbol is available from the target kernel.
-#
-# Output meanings:
-#   -1 : stream_open is not available
-#    0 : unknown whether or not stream_open is available
-#    1 : stream_open is available
-
-symbols="$(< "/lib/modules/$(uname -r)/build/Module.symvers" \
-           awk '{print $2}' | grep -E '^(nonseekable_open|stream_open)$')"
-
-if echo "${symbols}" | grep -q '^stream_open$'; then
-	echo 1
-elif echo "${symbols}" | grep -q '^nonseekable_open$'; then
-	echo -1
-else
-	echo 0
-fi
diff --git a/extra/i2c_pseudo/i2c-pseudo.c b/extra/i2c_pseudo/i2c-pseudo.c
deleted file mode 100644
index e4f1852cd8..0000000000
--- a/extra/i2c_pseudo/i2c-pseudo.c
+++ /dev/null
@@ -1,3212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This Linux kernel module implements pseudo I2C adapters that can be backed
- * by userspace programs.  This allows for implementing an I2C bus from
- * userspace, which can tunnel the I2C commands through another communication
- * channel to a remote I2C bus.
- */
-
-#include <linux/build_bug.h>
-#include <linux/cdev.h>
-#include <linux/completion.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/jiffies.h>
-#include <linux/kernel.h>
-#include <linux/kobject.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/poll.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/time64.h>
-#include <linux/types.h>
-#include <linux/uaccess.h>
-#include <linux/wait.h>
-#include <stdarg.h>
-
-/* Minimum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MIN	0
-/* Maximum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MAX	256
-/* Default i2cp_limit module parameter value. */
-#define I2CP_DEFAULT_LIMIT	8
-/* Value for alloc_chrdev_region() baseminor arg. */
-#define I2CP_CDEV_BASEMINOR	0
-#define I2CP_TIMEOUT_MS_MIN	0
-#define I2CP_TIMEOUT_MS_MAX	(60 * MSEC_PER_SEC)
-#define I2CP_DEFAULT_TIMEOUT_MS	(3 * MSEC_PER_SEC)
-
-/* Used in struct device.kobj.name field. */
-#define I2CP_DEVICE_NAME	"i2c-pseudo-controller"
-/* Value for alloc_chrdev_region() name arg. */
-#define I2CP_CHRDEV_NAME	"i2c_pseudo"
-/* Value for class_create() name arg. */
-#define I2CP_CLASS_NAME		"i2c-pseudo"
-/* Value for alloc_chrdev_region() count arg.  Should always be 1. */
-#define I2CP_CDEV_COUNT		1
-
-#define I2CP_ADAP_START_CMD		"ADAPTER_START"
-#define I2CP_ADAP_SHUTDOWN_CMD		"ADAPTER_SHUTDOWN"
-#define I2CP_GET_NUMBER_CMD		"GET_ADAPTER_NUM"
-#define I2CP_NUMBER_REPLY_CMD		"I2C_ADAPTER_NUM"
-#define I2CP_GET_PSEUDO_ID_CMD		"GET_PSEUDO_ID"
-#define I2CP_PSEUDO_ID_REPLY_CMD	"I2C_PSEUDO_ID"
-#define I2CP_SET_NAME_SUFFIX_CMD	"SET_ADAPTER_NAME_SUFFIX"
-#define I2CP_SET_TIMEOUT_CMD		"SET_ADAPTER_TIMEOUT_MS"
-#define I2CP_BEGIN_MXFER_REQ_CMD	"I2C_BEGIN_XFER"
-#define I2CP_COMMIT_MXFER_REQ_CMD	"I2C_COMMIT_XFER"
-#define I2CP_MXFER_REQ_CMD		"I2C_XFER_REQ"
-#define I2CP_MXFER_REPLY_CMD		"I2C_XFER_REPLY"
-
-/* Maximum size of a controller command. */
-#define I2CP_CTRLR_CMD_LIMIT		255
-/* Maximum number of controller read responses to allow enqueued at once. */
-#define I2CP_CTRLR_RSP_QUEUE_LIMIT	256
-/* The maximum size of a single controller read response. */
-#define I2CP_MAX_MSG_BUF_SIZE		16384
-/* Maximum size of a controller read or write. */
-#define I2CP_RW_SIZE_LIMIT		1048576
-
-/*
- * Marks the end of a controller command or read response.
- *
- * Fundamentally, controller commands and read responses could use different end
- * marker characters, but for validity they should be the same.
- *
- * This must be a variable, not a macro, because it is passed to copy_to_user()
- * by address.  Taking the address of a character literal causes a compiler
- * error.  Making these C strings instead of characters would allow for that
- * (with other implications), but then copy_to_user() itself refuses to compile,
- * because of an assertion that the copy size (1) must match the size of the
- * string literal (2 with its trailing null).
- */
-static const char i2cp_ctrlr_end_char		= '\n';
-/* Separator between I2C message header fields in the controller bytestream. */
-static const char i2cp_ctrlr_header_sep_char	= ' ';
-/* Separator between I2C message data bytes in the controller bytestream. */
-static const char i2cp_ctrlr_data_sep_char	= ':';
-
-/*
- * This used instead of strcmp(in_str, other_str) because in_str may have null
- * characters within its in_size boundaries, which could cause an unintended
- * match.
- */
-#define STRING_NEQ(in_str, in_size, other_str) \
-	(in_size != strlen(other_str) || memcmp(other_str, in_str, in_size))
-
-#define STR_HELPER(num)		#num
-#define STR(num)		STR_HELPER(num)
-
-#define CONST_STRLEN(str)	(sizeof(str) - 1)
-
-/*
- * The number of pseudo I2C adapters permitted.  This default value can be
- * overridden at module load time.  Must be in the range
- * [I2CP_ADAPTERS_MIN, I2CP_ADAPTERS_MAX].
- *
- * As currently used, this MUST NOT be changed during or after module
- * initialization.  If the ability to change this at runtime is desired, an
- * audit of the uses of this variable will be necessary.
- */
-static unsigned int i2cp_limit = I2CP_DEFAULT_LIMIT;
-module_param(i2cp_limit, uint, 0444);
-
-/*
- * The default I2C pseudo adapter timeout, in milliseconds.
- * 0 means use Linux I2C adapter default.
- * Can be changed per adapter by the controller.
- */
-static unsigned int i2cp_default_timeout_ms = I2CP_DEFAULT_TIMEOUT_MS;
-module_param(i2cp_default_timeout_ms, uint, 0444);
-
-struct i2cp_controller;
-
-/* This tracks all I2C pseudo adapters. */
-struct i2cp_counters {
-	/* This must be held while accessing any fields. */
-	struct mutex lock;
-	unsigned int count;
-	/*
-	 * This is used to make a strong attempt at avoiding ID reuse,
-	 * especially during the lifetime of a userspace i2c-dev client.  This
-	 * can wrap by design, and thus makes no perfect guarantees.
-	 */
-	/* Same type as struct i2cp_controller.id field. */
-	unsigned int next_ctrlr_id;
-	struct i2cp_controller **all_controllers;
-};
-
-static struct class *i2cp_class;
-static dev_t i2cp_dev_num;
-
-struct i2cp_device {
-	struct i2cp_counters counters;
-	struct cdev cdev;
-	struct device device;
-};
-
-static struct i2cp_device *i2cp_device;
-
-/*
- * An instance of this struct in i2cp_cmds[] array defines a command that a
- * controller process may write to the I2C pseudo character device, hereafter a
- * "write command."
- *
- * A write command consists of one or more header fields, followed optionally by
- * data.  Each header field is fully buffered before being sent to
- * header_receiver().  Data is not fully buffered, it is chunked in fixed
- * increments set by the return value of the final header_receiver() call.
- *
- * Every write command begins with its name.  The name is used both to map the
- * command to an instance of this struct, and as the first header field.
- *
- * A header field ends at either i2cp_ctrlr_end_char or
- * i2cp_ctrlr_header_sep_char, neither of which is ever included in header field
- * values passed to a callback.
- *
- * A command always ends at i2cp_ctrlr_end_char.  Anything written after that by
- * the controller is treated as a new command.
- *
- * After i2cp_ctrlr_header_sep_char the return value of header_receiver() from
- * the previous header field is used to determine whether subsequent input is
- * another header field, or data.
- *
- * Once header_receiver() has indicated that data is expected, all input until
- * i2cp_ctrlr_end_char will be handled as data, and header_receiver() will not
- * be called again for the command.
- *
- * For a given I2C pseudo controller instance there will never be more than one
- * write command in flight at once, and there will never be more than one of
- * these callbacks executing at once.  These callbacks need not do any
- * cross-thread synchronization among themselves.
- *
- * Note: Data may contain i2cp_ctrlr_header_sep_char.
- *
- * Note: There are no restrictions on the use of the null char ('\0') in either
- * header fields or data.  (If either i2cp_ctrlr_header_sep_char or
- * i2cp_ctrlr_end_char is null then the respective restrictions around those
- * characters apply as usual, of course.)  Write command implementations need
- * not use or expect null, but they must at least handle it gracefully and fail
- * without bad side effects, same as with any unexpected input.
- */
-struct i2cp_cmd {
-	/*
-	 * Set these to the command name.
-	 *
-	 * The command name must not contain i2cp_ctrlr_header_sep_char or
-	 * i2cp_ctrlr_end_char.  The behavior otherwise is undefined; such a
-	 * command would be uncallable, and could become either a build-time or
-	 * runtime error.
-	 *
-	 * The command name must be unique in the i2cp_cmds[] array.  The
-	 * behavior with duplicate command names is undefined, subject to
-	 * change, and subject to become either a build-time or runtime error.
-	 */
-	char *cmd_string;  /* Must be non-NULL. */
-	size_t cmd_size;  /* Must be non-zero. */
-
-	/*
-	 * This is called once for each I2C pseudo controller to initialize
-	 * *data, prior to that pointer being passed to any other callbacks.
-	 *
-	 * This will only be called before the I2C adapter device is added.
-	 *
-	 * *data will be set to NULL before this is called.
-	 *
-	 * This callback may be NULL, in which case *data will remain NULL upon
-	 * initialization.
-	 *
-	 * This should return -errno upon failure, 0 upon success.  All
-	 * non-negative return values are currently treated as success but
-	 * positive values are reserved for potential future use.
-	 *
-	 * Initialization failure will cause the whole I2C pseudo controller to
-	 * fail to initialize or function, thus *data will not be passed to any
-	 * other callbacks.
-	 */
-	int (*data_creator)(void **data);
-	/*
-	 * This is called once when shutdown of an I2C pseudo controller is
-	 * imminent, and no further I2C replies can be processed.
-	 *
-	 * This callback may be NULL.
-	 */
-	void (*data_shutdown)(void *data);
-	/*
-	 * This is called once upon termination of each I2C pseudo controller to
-	 * free any resources held by @data.
-	 *
-	 * This will never be called while the I2C adapter device is active.
-	 * Normally that means this is called after the I2C adapter device has
-	 * been deleted, but it is also possible for this to be called during
-	 * I2C pseudo controller initialization if a subsequent initialization
-	 * step failed, as part of failure handling cleanup.
-	 *
-	 * This will only be called after a successful return value from
-	 * data_creator().
-	 *
-	 * This will be passed the same *data pointer that data_creator() placed
-	 * in its **data output arg.
-	 *
-	 * The *data pointer will not be used again by the write command system
-	 * after the start of this function call.
-	 *
-	 * This callback may be NULL.
-	 */
-	void (*data_destroyer)(void *data);
-	/*
-	 * This is called to process write command header fields, including the
-	 * command name itself as the first header field in every command.
-	 *
-	 * This is called once for each header field, in order, including the
-	 * initial command name.
-	 *
-	 * @data is the value of *data from data_creator().  (Thus NULL if
-	 * data_creator field is NULL.)
-	 *
-	 * @in and @in_size are the header value.  It will never contain
-	 * i2cp_ctrlr_header_sep_char or i2cp_ctrlr_end_char.
-	 *
-	 * in[in_size] is guaranteed to be null.  There may be null characters
-	 * inside the buffer boundary indicated by @in_size as well though!
-	 *
-	 * @non_blocking indicates whether O_NONBLOCK is set on the controller
-	 * file descriptor.  This is not expected to be relevant to most write
-	 * command callback implementations, however it should be respected if
-	 * relevant.  In other words, if this is true do not block indefinitely,
-	 * instead return EAGAIN or EWOULDBLOCK.  If this is false never return
-	 * EAGAIN or EWOULDBLOCK.
-	 *
-	 * Return -errno to indicate a failure.  After a failure the next and
-	 * final callback invocation for the command will be cmd_completer().
-	 *
-	 * Return 0 to indicate success _and_ that another header field is
-	 * expected next.  The next header field will be fully buffered before
-	 * being sent to this callback, just as the current one was.
-	 *
-	 * Return a positive value to indicate success _and_ that data is
-	 * expected next.  The exact positive value sets the chunk size used to
-	 * buffer the data and pass it to data_receiver.  All invocations of
-	 * data_receiver are guaranteed to receive data in a _multiple_ of the
-	 * chunk size, except the final invocation, because
-	 * i2cp_ctrlr_end_char could be received on a non-chunk-size boundary.
-	 * The return value should be less than I2CP_CTRLR_CMD_LIMIT, as that
-	 * minus one is the maximum that will ever be buffered at once, and thus
-	 * the maximum that will ever be sent to a single invocation of
-	 * data_receiver.
-	 *
-	 * If the command is expected to end after a header field without any
-	 * data, it is encouraged to return 1 here and have data_receiver
-	 * indicate a failure if it is called.  That avoids having the
-	 * unexpected input buffered unnecessarily.
-	 *
-	 * This callback MUST NOT be NULL.
-	 */
-	int (*header_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
-	/*
-	 * This is called to process write command data, when requested by the
-	 * header_receiver() return value.
-	 *
-	 * This may be invoked multiple times for each data field, with the data
-	 * broken up into sequential non-overlapping chunks.
-	 *
-	 * @in and @in_size are data.  The data will never contain
-	 * i2cp_ctrlr_end_char.
-	 *
-	 * in[in_size] is guaranteed to be null.  There may be null characters
-	 * inside the buffer boundary indicated by @in_size as well though!
-	 *
-	 * @in_size is guaranteed to be a multiple of the chunk size as
-	 * specified by the last return value from header_receiver(), unless
-	 * either the chunk size is >= I2CP_CTRLR_CMD_LIMIT, or
-	 * i2cp_ctrlr_end_char was reached on a non-chunk-sized boundary.
-	 *
-	 * @in_size is guaranteed to be greater than zero, and less than
-	 * I2CP_CTRLR_CMD_LIMIT.
-	 *
-	 * @non_blocking indicates whether O_NONBLOCK is set on the controller
-	 * file descriptor.  This is not expected to be relevant to most write
-	 * command callback implementations, however it should be respected if
-	 * relevant.  In other words, if this is true do not block indefinitely,
-	 * instead return EAGAIN or EWOULDBLOCK.  If this is false never return
-	 * EAGAIN or EWOULDBLOCK.
-	 *
-	 * This should return -errno upon failure, 0 upon success.  All
-	 * non-negative return values are currently treated as success but
-	 * positive values are reserved for potential future use.  After a
-	 * failure the next and final callback invocation for the command will
-	 * be cmd_completer().
-	 *
-	 * If header_receiver() never returns a positive number, this callback
-	 * should be NULL.  Otherwise, this callback MUST NOT be NULL.
-	 */
-	int (*data_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
-	/*
-	 * This is called to complete processing of a command, after it has been
-	 * received in its entirety.
-	 *
-	 * If @receive_status is positive, it is an error code from the invoking
-	 * routines themselves, e.g. if the controller process wrote a header
-	 * field >= I2CP_CTRLR_CMD_LIMIT.
-	 *
-	 * If @receive_status is zero, it means all invocations of
-	 * header_receiver and data_receiver returned successful values and the
-	 * entire write command was received successfully.
-	 *
-	 * If @receive_status is negative, it is the value returned by the last
-	 * header_receiver or data_receiver invocation.
-	 *
-	 * @non_blocking indicates whether O_NONBLOCK is set on the controller
-	 * file descriptor.  This is not expected to be relevant to most write
-	 * command callback implementations, however it should be respected if
-	 * relevant.  In other words, if this is true do not block indefinitely,
-	 * instead return EAGAIN or EWOULDBLOCK.  If this is false never return
-	 * EAGAIN or EWOULDBLOCK.
-	 *
-	 * This is called exactly once for each write command.  This is true
-	 * regardless of the value of @non_blocking and regardless of the return
-	 * value of this function, so it is imperative that this function
-	 * perform any necessary cleanup tasks related to @data, even if
-	 * non_blocking=true and blocking is required!
-	 *
-	 * Thus, even with non_blocking=true, it would only ever make sense to
-	 * return -EAGAIN from this function if the struct i2cp_cmd
-	 * implementation is able to perform the would-be blocked cmd_completer
-	 * operation later, e.g. upon invocation of a callback for the next
-	 * write command, or by way of a background thread.
-	 *
-	 * This should return -errno upon failure, 0 upon success.  All
-	 * non-negative return values are currently treated as success but
-	 * positive values are reserved for potential future use.
-	 *
-	 * An error should be returned only to indicate a new error that
-	 * happened during the execution of this callback.  Any error from
-	 * @receive_status should *not* be copied to the return value of this
-	 * callback.
-	 *
-	 * This callback may be NULL.
-	 */
-	int (*cmd_completer)(void *data, struct i2cp_controller *pdata,
-		int receive_status, bool non_blocking);
-};
-
-/*
- * These are indexes of i2cp_cmds[].  Every element in that array should have a
- * corresponding value in this enum, and the enum value should be used in the
- * i2cp_cmds[] initializer.
- *
- * Command names are matched in this order, so sort by expected frequency.
- */
-enum {
-	I2CP_CMD_MXFER_REPLY_IDX = 0,
-	I2CP_CMD_ADAP_START_IDX,
-	I2CP_CMD_ADAP_SHUTDOWN_IDX,
-	I2CP_CMD_GET_NUMBER_IDX,
-	I2CP_CMD_GET_PSEUDO_ID_IDX,
-	I2CP_CMD_SET_NAME_SUFFIX_IDX,
-	I2CP_CMD_SET_TIMEOUT_IDX,
-	/* Keep this at the end! This must equal ARRAY_SIZE(i2cp_cmds). */
-	I2CP_NUM_WRITE_CMDS,
-};
-
-/*
- * All values must be >= 0.  This should not contain any error values.
- *
- * The state for a new controller must have a zero value, so that
- * zero-initialized memory results in the correct default value.
- */
-enum i2cp_ctrlr_state {
-	/*
-	 * i2c_add_adapter() has not been called yet, or has only returned
-	 * failure.
-	 */
-	I2CP_CTRLR_STATE_NEW = 0,
-	/*
-	 * i2c_add_adapter() has return success, and the controller has not
-	 * requested shutdown yet.
-	 */
-	I2CP_CTRLR_STATE_RUNNING,
-	/*
-	 * i2c_add_adapter() has returned success, and the controller has
-	 * requested shutdown.
-	 *
-	 * Note that it is perfectly acceptable for a pseudo controller fd to be
-	 * closed and released without shutdown having been requested
-	 * beforehand.  Thus, this state is purely optional in the lifetime of a
-	 * controller.
-	 */
-	I2CP_CTRLR_STATE_SHUTDN_REQ,
-};
-
-/*
- * Avoid allocating this struct on the stack, it contains a large buffer as a
- * direct member.
- *
- * To avoid deadlocks, never attempt to hold more than one of the locks in this
- * structure at once, with the following exceptions:
- *   - It is permissible to acquire read_rsp_queue_lock while holding cmd_lock.
- *   - It is permissible to acquire read_rsp_queue_lock while holding rsp_lock.
- */
-struct i2cp_controller {
-	unsigned int index;
-	/*
-	 * Never modify the ID after initialization.
-	 *
-	 * This should be an unsigned integer type large enough to hold
-	 * I2CP_ADAPTERS_MAX.
-	 */
-	unsigned int id;
-	/*
-	 * Only i2cp_cdev_open() and i2cp_cdev_release() may access this field.
-	 * Other functions called by them, or called by the I2C subsystem, may
-	 * of course take a reference to this same struct i2c_adapter.  However
-	 * no other functions besides the aforementioned two may access the
-	 * i2c_adapter field of struct i2cp_controller.
-	 */
-	struct i2c_adapter i2c_adapter;
-
-	struct mutex startstop_lock;
-	enum i2cp_ctrlr_state startstop_state;
-
-	wait_queue_head_t poll_wait_queue;
-
-	/* This must be held while read or writing cmd_* fields. */
-	struct mutex cmd_lock;
-	/*
-	 * This becomes the @receive_status arg to struct i2cp_cmd.cmd_completer
-	 * callback.
-	 *
-	 * A negative value is an error number from
-	 * struct i2cp_cmd.header_receiver or struct i2cp_cmd.data_receiver.
-	 *
-	 * A zero value means no error has occurred so far in processing the
-	 * current write reply command.
-	 *
-	 * A positive value is an error number from a non-command-specific part
-	 * of write command processing, e.g. from the
-	 * struct file_operations.write callback itself, or function further up
-	 * its call stack that is not specific to any particular write command.
-	 */
-	int cmd_receive_status;
-	/*
-	 * Index of i2cp_cmds[] and .cmd_data[] plus one, i.e. value of 1 means
-	 * 0 index.  Value of 0 (zero) means the controller is waiting for a new
-	 * command.
-	 */
-	int cmd_idx_plus_one;
-	int cmd_data_increment;
-	size_t cmd_size;
-	/* Add one for trailing null character. */
-	char cmd_buf[I2CP_CTRLR_CMD_LIMIT + 1];
-	void *cmd_data[I2CP_NUM_WRITE_CMDS];
-
-	struct completion read_rsp_queued;
-	/* This must be held while read or writing read_rsp_queue_* fields. */
-	struct mutex read_rsp_queue_lock;
-	/*
-	 * This is a FIFO queue of struct i2cp_rsp.queue .
-	 *
-	 * This MUST be strictly used as FIFO.  Only consume or pop the first
-	 * item.  Only append to the end.  Users of this queue assume this FIFO
-	 * behavior is strictly followed, and their uses of read_rsp_queue_lock
-	 * would not be safe otherwise.
-	 */
-	struct list_head read_rsp_queue_head;
-	unsigned int read_rsp_queue_length;
-
-	/* This must be held while reading or writing rsp_* fields. */
-	struct mutex rsp_lock;
-	bool rsp_invalidated;
-	/*
-	 * Holds formatted string from most recently popped item of
-	 * read_rsp_queue_head if it was not wholly consumed by the last
-	 * controller read.
-	 */
-	char *rsp_buf_start;
-	char *rsp_buf_pos;
-	ssize_t rsp_buf_remaining;
-};
-
-struct i2cp_cmd_mxfer_reply {
-	/*
-	 * This lock MUST be held while reading or modifying any part of this
-	 * struct i2cp_cmd_mxfer_reply, unless you can guarantee that nothing
-	 * else can access this struct concurrently, such as during
-	 * initialization.
-	 *
-	 * The struct i2cp_cmd_mxfer_reply_data.reply_queue_lock of the
-	 * struct i2cp_cmd_mxfer_reply_data.reply_queue_head list which contains
-	 * this struct i2cp_cmd_mxfer_reply.reply_queue_item MUST be held when
-	 * attempting to acquire this lock.
-	 *
-	 * It is NOT required to keep
-	 * struct i2cp_cmd_mxfer_reply_data.reply_queue_lock held after
-	 * acquisition of this lock (unless also manipulating
-	 * struct i2cp_cmd_mxfer_reply_data.reply_queue_* of course).
-	 */
-	struct mutex lock;
-
-	/*
-	 * Never modify the ID after initialization.
-	 *
-	 * This should be an unsigned integer type large enough to hold
-	 * I2CP_CTRLR_RSP_QUEUE_LIMIT.  If changing this type, audit for printf
-	 * format strings that need updating!
-	 */
-	unsigned int id;
-	/* Number of I2C messages successfully processed, or negative error. */
-	int ret;
-	/* Same type as struct i2c_algorithm.master_xfer @num arg. */
-	int num_msgs;
-	/* Same type as struct i2c_algorithm.master_xfer @msgs arg. */
-	struct i2c_msg *msgs;
-	/* Same length (not size) as *msgs array. */
-	bool *completed;
-	/* Number of completed[] array entries with true value. */
-	int num_completed_true;
-
-	/*
-	 * This is for use in struct i2cp_cmd_mxfer_reply_data.reply_queue_head
-	 * FIFO queue.
-	 *
-	 * Any time this is deleted from its containing
-	 * struct i2cp_cmd_mxfer_reply_data.reply_queue_head list, either
-	 * list_del_init() MUST be used (not list_del()), OR this whole
-	 * struct i2cp_cmd_mxfer_reply MUST be freed.
-	 *
-	 * That way, if this struct is not immediately freed, the code which
-	 * eventually frees it can test whether it still needs to be deleted
-	 * from struct i2cp_cmd_mxfer_reply_data.reply_queue_head by using
-	 * list_empty() on reply_queue_item.  (Calling list_del() on an
-	 * already-deleted list item is unsafe.)
-	 */
-	struct list_head reply_queue_item;
-	struct completion data_filled;
-};
-
-/*
- * The state for receiving the first field must have a zero value, so that
- * zero-initialized memory results in the correct default value.
- */
-enum i2cp_cmd_mxfer_reply_state {
-	I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT = 0,
-	I2CP_CMD_MXFER_REPLY_STATE_ID_NEXT,
-	I2CP_CMD_MXFER_REPLY_STATE_INDEX_NEXT,
-	I2CP_CMD_MXFER_REPLY_STATE_ADDR_NEXT,
-	I2CP_CMD_MXFER_REPLY_STATE_FLAGS_NEXT,
-	I2CP_CMD_MXFER_REPLY_STATE_ERRNO_NEXT,
-	I2CP_CMD_MXFER_REPLY_STATE_DATA_NEXT,
-	/*
-	 * This is used to tell subsequent callback invocations that the write
-	 * command currently being received is invalid, when the receiver wants
-	 * to quietly discard the write command instead of loudly returning an
-	 * error.
-	 */
-	I2CP_CMD_MXFER_REPLY_STATE_INVALID,
-};
-
-struct i2cp_cmd_mxfer_reply_data {
-	/* This must be held while read or writing reply_queue_* fields. */
-	struct mutex reply_queue_lock;
-	/*
-	 * This is used to make a strong attempt at avoiding ID reuse,
-	 * especially for overlapping master_xfer() calls.
-	 *
-	 * This can wrap by design, and thus makes no perfect guarantees over
-	 * the lifetime of an I2C pseudo adapter.
-	 *
-	 * No code should assume uniqueness, not even for master_xfer() calls of
-	 * overlapping lifetimes.  When the controller writes a master_xfer()
-	 * reply command, assume that it is for the oldest outstanding instance
-	 * of the ID number specified.
-	 */
-	/* Same type as struct i2cp_cmd_mxfer_reply.id field. */
-	unsigned int next_mxfer_id;
-	/*
-	 * This is a FIFO queue of struct i2cp_cmd_mxfer_reply.reply_queue_item.
-	 *
-	 * This MUST be strictly used as FIFO.  Only consume or pop the first
-	 * item.  Only append to the end.  Users of this queue assume this FIFO
-	 * behavior is strictly followed, and their uses of reply_queue_lock may
-	 * not be safe otherwise.
-	 */
-	struct list_head reply_queue_head;
-	unsigned int reply_queue_length;
-	struct i2cp_cmd_mxfer_reply *reply_queue_current_item;
-
-	enum i2cp_cmd_mxfer_reply_state state;
-
-	/* Same type as struct i2cp_cmd_mxfer_reply.id field. */
-	unsigned int current_id;
-	/* Same type as struct i2c_msg.addr field. */
-	u16 current_addr;
-	/* Same type as struct i2c_msg.flags field. */
-	u16 current_flags;
-	/* Same type as struct i2c_algorithm.master_xfer @num arg. */
-	int current_msg_idx;
-	/* Same type as struct i2c_msg.len field. */
-	u16 current_buf_idx;
-};
-
-struct i2cp_cmd_set_name_suffix_data {
-	char name_suffix[sizeof_field(struct i2c_adapter, name)];
-	size_t name_suffix_len;
-};
-
-struct i2cp_cmd_set_timeout_data {
-	int field_pos;
-	unsigned int timeout_ms;
-};
-
-struct i2cp_rsp {
-	/*
-	 * This callback is invoked to format its associated data for passing to
-	 * the userspace controller process when it read()s the I2C pseudo
-	 * controller character device.
-	 *
-	 * @data will be the data pointer from this struct instance.
-	 *
-	 * @out is an output argument.  Upon positive return value, *out must be
-	 * set to a buffer which the caller will take ownership of, and which
-	 * can be freed with kfree().
-	 *
-	 * Upon positive return value, @data must NOT be freed.
-	 *
-	 * The formatter will be called repeatedly for the same data until it
-	 * returns non-positive.
-	 *
-	 * Upon non-positive return value, *out should not be modified.
-	 *
-	 * Upon non-positive return value, the formatter should have freed data
-	 * with kfree().  Implicitly this means any allocations owned by *data
-	 * should have been freed by the formatter as well.
-	 *
-	 * A negative return value indicates an error occurred and the data
-	 * cannot be formatted successfully.  The error code may or may not
-	 * eventually be propagated back to the I2C pseudo adapter controller.
-	 *
-	 * A positive return value is the number of characters/bytes to use from
-	 * the *out buffer, always starting from index 0.  It should NOT include
-	 * a trailing NULL character unless that character should be propagated
-	 * to the I2C pseudo adapter controller!  It therefore does NOT need to
-	 * be the full size of the allocated *out buffer, instead it can be
-	 * less.  (The size is not needed by kfree().)
-	 *
-	 * The formatter owns the memory pointed to by data.  The invoking code
-	 * will never mutate or free data.  Thus, upon non-positive return value
-	 * from the formatter, the formatter must have already performed any
-	 * reference counting decrement or memory freeing necessary to ensure
-	 * data does not live beyond its final use.
-	 *
-	 * There will never be more than one formatter callback in flight at
-	 * once for a given I2C pseudo controller.  This is true even in the
-	 * face of concurrent reads by the controller.
-	 *
-	 * The formatter must NOT use i2cp_ctrlr_end_char in anywhere in *out
-	 * (within the size range indicated by the return value; past that does
-	 * not matter).  The i2cp_ctrlr_end_char will be added automatically by
-	 * the caller after a zero return value (successful completion) from the
-	 * formatter.
-	 *
-	 * The formatter must never create or return a buffer larger than
-	 * I2CP_MAX_MSG_BUF_SIZE.  The formatter is encouraged to avoid that by
-	 * generating and returning the output in chunks, taking advantage of
-	 * the guarantee that it will be called repeatedly until  exhaustion
-	 * (zero return value) or failure (negative return value).  If the
-	 * formatter expects its formatted output or natural subsets of it to
-	 * always fit within I2CP_MAX_MSG_BUF_SIZE, and it is called with input
-	 * data not meeting that expectation, the formatter should return
-	 * -ERANGE to indicate this condition.
-	 */
-	ssize_t (*formatter)(void *data, char **out);
-	void *data;
-
-	struct list_head queue;
-};
-
-struct i2cp_rsp_buffer {
-	char *buf;
-	ssize_t size;
-};
-
-struct i2cp_rsp_master_xfer {
-	/* Never modify the ID after initialization. */
-	/* Same type as struct i2cp_cmd_mxfer_reply.id field. */
-	unsigned int id;
-
-	/* These types match those of struct i2c_algorithm.master_xfer args. */
-	struct i2c_msg *msgs;
-	int num;
-
-	/*
-	 * Always initialize fields below here to zero.  They are for internal
-	 * use by i2cp_rsp_master_xfer_formatter().
-	 */
-	int num_msgs_done;  /* type of @num field */
-	size_t buf_start_plus_one;
-};
-
-/* vanprintf - See anprintf() documentation. */
-static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, va_list ap)
-{
-	int ret;
-	ssize_t buf_size;
-	char *buf = NULL;
-	va_list args1;
-
-	va_copy(args1, ap);
-	ret = vsnprintf(NULL, 0, fmt, ap);
-	if (ret < 0)
-		goto fail_before_args1;
-	if (max_size >= 0 && ret > max_size) {
-		ret = -ERANGE;
-		goto fail_before_args1;
-	}
-
-	buf_size = ret + 1;
-	buf = kmalloc(buf_size, gfp);
-	if (buf == NULL) {
-		ret = -ENOMEM;
-		goto fail_before_args1;
-	}
-
-	ret = vsnprintf(buf, buf_size, fmt, args1);
-	va_end(args1);
-	if (ret < 0)
-		goto fail_after_args1;
-	if (ret + 1 != buf_size) {
-		ret = -ENOTRECOVERABLE;
-		goto fail_after_args1;
-	}
-
-	*out = buf;
-	return ret;
-
- fail_before_args1:
-	va_end(args1);
- fail_after_args1:
-	kfree(buf);
-	if (ret >= 0)
-		ret = -ENOTRECOVERABLE;
-	return ret;
-}
-
-/*
- * anprintf - Format a string and place it into a newly allocated buffer.
- * @out: Address of the pointer to place the buffer address into.  Will only be
- *     written to with a successful positive return value.
- * @max_size: If non-negative, the maximum buffer size that this function will
- *     attempt to allocate.  If the formatted string including trailing null
- *     character would not fit, no buffer will be allocated, and an error will
- *     be returned.  (Thus max_size of 0 will always result in an error.)
- * @gfp: GFP flags for kmalloc().
- * @fmt: The format string to use.
- * @...: Arguments for the format string.
- *
- * Return value meanings:
- *
- *   >=0: A buffer of this size was allocated and its address written to *out.
- *        The caller now owns the buffer and is responsible for freeing it with
- *        kfree().  The final character in the buffer, not counted in this
- *        return value, is the trailing null.  This is the same return value
- *        meaning as snprintf(3).
- *
- *    <0: An error occurred.  Negate the return value for the error number.
- *        @out will not have been written to.  Errors that might come from
- *        snprintf(3) may come from this function as well.  Additionally, the
- *        following errors may occur from this function:
- *
- *        ERANGE: A buffer larger than @max_size would be needed to fit the
- *        formatted string including its trailing null character.
- *
- *        ENOMEM: Allocation of the output buffer failed.
- *
- *        ENOTRECOVERABLE: An unexpected condition occurred.  This may indicate
- *        a bug.
- */
-static ssize_t anprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, ...)
-{
-	ssize_t ret;
-	va_list args;
-
-	va_start(args, fmt);
-	ret = vanprintf(out, max_size, gfp, fmt, args);
-	va_end(args);
-	return ret;
-}
-
-static ssize_t i2cp_rsp_buffer_formatter(void *data, char **out)
-{
-	struct i2cp_rsp_buffer *rsp_buf;
-
-	rsp_buf = data;
-	if (rsp_buf->buf) {
-		if (rsp_buf->size > 0) {
-			*out = rsp_buf->buf;
-			rsp_buf->buf = NULL;
-			return rsp_buf->size;
-		}
-		kfree(rsp_buf->buf);
-	}
-	kfree(rsp_buf);
-	return 0;
-}
-
-static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
-{
-	ssize_t ret;
-	size_t i, buf_size, byte_start, byte_limit;
-	char *buf_start, *buf_pos;
-	struct i2cp_rsp_master_xfer *mxfer_rsp;
-	struct i2c_msg *i2c_msg;
-
-	mxfer_rsp = data;
-
-	/*
-	 * This condition is set by a previous call to this function with the
-	 * same data, when it returned an error but was not consuming the final
-	 * i2c_msg.
-	 */
-	if (!mxfer_rsp->msgs) {
-		++mxfer_rsp->num_msgs_done;
-		ret = 0;
-		goto maybe_free;
-	}
-
-	i2c_msg = &mxfer_rsp->msgs[mxfer_rsp->num_msgs_done];
-
-	/*
-	 * If this is a read, or if this is a write and we've finished writing
-	 * the data buffer, we are done with this i2c_msg.
-	 */
-	if (mxfer_rsp->buf_start_plus_one >= 1 &&
-	    (i2c_msg->flags & I2C_M_RD ||
-	     mxfer_rsp->buf_start_plus_one >= (size_t)i2c_msg->len + 1)) {
-		++mxfer_rsp->num_msgs_done;
-		mxfer_rsp->buf_start_plus_one = 0;
-		ret = 0;
-		goto maybe_free;
-	}
-
-	if (mxfer_rsp->buf_start_plus_one <= 0) {
-		/*
-		 * The length is not strictly necessary with the explicit
-		 * end-of-message marker (i2cp_ctrlr_end_char), however it
-		 * serves as a useful validity check for controllers to verify
-		 * that no bytes were lost in kernel->userspace transmission.
-		 */
-		ret = anprintf(&buf_start, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-			"%*s%c%u%c%d%c0x%04X%c0x%04X%c%u",
-			(int)strlen(I2CP_MXFER_REQ_CMD), I2CP_MXFER_REQ_CMD,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->id,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->num_msgs_done,
-			i2cp_ctrlr_header_sep_char, i2c_msg->addr,
-			i2cp_ctrlr_header_sep_char, i2c_msg->flags,
-			i2cp_ctrlr_header_sep_char, i2c_msg->len);
-		if (ret > 0) {
-			*out = buf_start;
-			mxfer_rsp->buf_start_plus_one = 1;
-		/*
-		 * If we have a zero return value, it means the output buffer
-		 * was allocated as size one, containing only a terminating null
-		 * character.  This would be a bug given the requested format
-		 * string above.  Also, formatter functions must not mutate *out
-		 * when returning zero.  So if this matches, free the useless
-		 * buffer and return an error.
-		 */
-		} else if (ret == 0) {
-			ret = -EINVAL;
-			kfree(buf_start);
-		}
-		goto maybe_free;
-	}
-
-	byte_start = mxfer_rsp->buf_start_plus_one - 1;
-	byte_limit = min_t(size_t, i2c_msg->len - byte_start,
-		I2CP_MAX_MSG_BUF_SIZE / 3);
-	/* 3 chars per byte == 2 chars for hex + 1 char for separator */
-	buf_size = byte_limit * 3;
-
-	buf_start = kzalloc(buf_size, GFP_KERNEL);
-	if (!buf_start) {
-		ret = -ENOMEM;
-		goto maybe_free;
-	}
-
-	for (buf_pos = buf_start, i = 0; i < byte_limit; ++i) {
-		*buf_pos++ = (i || byte_start) ?
-			i2cp_ctrlr_data_sep_char : i2cp_ctrlr_header_sep_char;
-		buf_pos = hex_byte_pack_upper(
-			buf_pos, i2c_msg->buf[byte_start + i]);
-	}
-	*out = buf_start;
-	ret = buf_size;
-	mxfer_rsp->buf_start_plus_one += i;
-
- maybe_free:
-	if (ret <= 0) {
-		if (mxfer_rsp->num_msgs_done >= mxfer_rsp->num) {
-			kfree(mxfer_rsp->msgs);
-			kfree(mxfer_rsp);
-		/*
-		 * If we are returning an error but have not consumed all of
-		 * mxfer_rsp yet, we must not attempt to output any more I2C
-		 * messages from the same mxfer_rsp.  Setting mxfer_rsp->msgs to
-		 * NULL tells the remaining invocations with this mxfer_rsp to
-		 * output nothing.
-		 *
-		 * There can be more invocations with the same mxfer_rsp even
-		 * after returning an error here because
-		 * i2cp_adapter_master_xfer() reuses a single
-		 * struct i2cp_rsp_master_xfer (mxfer_rsp) across multiple
-		 * struct i2cp_rsp (rsp_wrappers), one for each struct i2c_msg
-		 * within the mxfer_rsp.
-		 */
-		} else if (ret < 0) {
-			kfree(mxfer_rsp->msgs);
-			mxfer_rsp->msgs = NULL;
-		}
-	}
-	return ret;
-}
-
-static ssize_t i2cp_id_show(struct device *dev, struct device_attribute *attr,
-	char *buf)
-{
-	int ret;
-	struct i2c_adapter *adap;
-	struct i2cp_controller *pdata;
-
-	adap = container_of(dev, struct i2c_adapter, dev);
-	pdata = container_of(adap, struct i2cp_controller, i2c_adapter);
-	ret = snprintf(buf, PAGE_SIZE, "%u\n", pdata->id);
-	if (ret >= PAGE_SIZE)
-		return -ERANGE;
-	return ret;
-}
-
-static const struct device_attribute i2cp_id_dev_attr = {
-	.attr = {
-		.name = "i2c-pseudo-id",
-		.mode = 0444,
-	},
-	.show = i2cp_id_show,
-};
-
-static enum i2cp_ctrlr_state i2cp_adap_get_state(struct i2cp_controller *pdata)
-{
-	enum i2cp_ctrlr_state ret;
-
-	mutex_lock(&pdata->startstop_lock);
-	ret = pdata->startstop_state;
-	mutex_unlock(&pdata->startstop_lock);
-	return ret;
-}
-
-static int i2cp_cmd_mxfer_reply_data_creator(void **data)
-{
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-
-	cmd_data = kzalloc(sizeof(*cmd_data), GFP_KERNEL);
-	if (!cmd_data)
-		return -ENOMEM;
-	mutex_init(&cmd_data->reply_queue_lock);
-	INIT_LIST_HEAD(&cmd_data->reply_queue_head);
-	*data = cmd_data;
-	return 0;
-}
-
-/*
- * Notify pending I2C requests of the shutdown.  There is no possibility of
- * further I2C replies at this point.  This stops the I2C requests from waiting
- * for the adapter timeout, which could have been set arbitrarily long by the
- * userspace controller.
- */
-static void i2cp_cmd_mxfer_reply_data_shutdown(void *data)
-{
-	struct list_head *list_ptr;
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-	struct i2cp_cmd_mxfer_reply *mxfer_reply;
-
-	cmd_data = data;
-	mutex_lock(&cmd_data->reply_queue_lock);
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
-		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
-		mutex_lock(&mxfer_reply->lock);
-		complete_all(&mxfer_reply->data_filled);
-		mutex_unlock(&mxfer_reply->lock);
-	}
-	mutex_unlock(&cmd_data->reply_queue_lock);
-}
-
-static void i2cp_cmd_mxfer_reply_data_destroyer(void *data)
-{
-	/*
-	 * We do not have to worry about racing with in-flight I2C messages
-	 * because data_destroyer callbacks are guaranteed to never be called
-	 * while the I2C adapter device is active.
-	 */
-	kfree(data);
-}
-
-static inline bool i2cp_mxfer_reply_is_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data,
-	struct i2cp_cmd_mxfer_reply *mxfer_reply)
-{
-	int i;
-
-	i = cmd_data->current_msg_idx;
-	return cmd_data->current_id == mxfer_reply->id &&
-		i >= 0 && i < mxfer_reply->num_msgs &&
-		cmd_data->current_addr == mxfer_reply->msgs[i].addr &&
-		cmd_data->current_flags == mxfer_reply->msgs[i].flags;
-}
-
-/* cmd_data->reply_queue_lock must be held. */
-static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
-{
-	struct list_head *list_ptr;
-	struct i2cp_cmd_mxfer_reply *mxfer_reply;
-
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
-		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
-		if (i2cp_mxfer_reply_is_current(cmd_data, mxfer_reply))
-			return mxfer_reply;
-	}
-	return NULL;
-}
-
-/* cmd_data->reply_queue_lock must NOT already be held. */
-static inline void i2cp_mxfer_reply_update_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
-{
-	mutex_lock(&cmd_data->reply_queue_lock);
-	cmd_data->reply_queue_current_item = i2cp_mxfer_reply_find_current(
-		cmd_data);
-	mutex_unlock(&cmd_data->reply_queue_lock);
-}
-
-static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	int ret, reply_errno = 0;
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-
-	cmd_data = data;
-
-	switch (cmd_data->state) {
-	case I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT:
-		/* Expect the msg/reply ID header field next. */
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_ID_NEXT;
-		return 0;
-	case I2CP_CMD_MXFER_REPLY_STATE_ID_NEXT:
-	case I2CP_CMD_MXFER_REPLY_STATE_INDEX_NEXT:
-	case I2CP_CMD_MXFER_REPLY_STATE_ADDR_NEXT:
-	case I2CP_CMD_MXFER_REPLY_STATE_FLAGS_NEXT:
-	case I2CP_CMD_MXFER_REPLY_STATE_ERRNO_NEXT:
-		break;
-	default:
-		/* Reaching here is a bug. */
-		/*
-		 * Testing this before checking for null characters ensures the
-		 * correct error is indicated.
-		 */
-		return -EINVAL;
-	}
-
-	/*
-	 * The command name is logically outside the control of this function,
-	 * and may contain null characters, even if that would be nonsensical.
-	 * Thus it is handled above, followed by this check, and below here
-	 * the rest of the header fields are handled.  Some of them use
-	 * functions that could mishandle input which contains nulls.  An actual
-	 * error would be okay, however if the input were consumed incorrectly
-	 * without an error, that could lead to subtle bugs.
-	 */
-	if (memchr(in, '\0', in_size))
-		return -EPROTO;
-
-	switch (cmd_data->state) {
-	case I2CP_CMD_MXFER_REPLY_STATE_ID_NEXT:
-		ret = kstrtouint(in, 0, &cmd_data->current_id);
-		if (ret < 0)
-			return ret;
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_INDEX_NEXT;
-		return 0;
-	case I2CP_CMD_MXFER_REPLY_STATE_INDEX_NEXT:
-		ret = kstrtoint(in, 0, &cmd_data->current_msg_idx);
-		if (ret < 0)
-			return ret;
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_ADDR_NEXT;
-		return 0;
-	case I2CP_CMD_MXFER_REPLY_STATE_ADDR_NEXT:
-		ret = kstrtou16(in, 0, &cmd_data->current_addr);
-		if (ret < 0)
-			return ret;
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_FLAGS_NEXT;
-		return 0;
-	case I2CP_CMD_MXFER_REPLY_STATE_FLAGS_NEXT:
-		ret = kstrtou16(in, 0, &cmd_data->current_flags);
-		if (ret < 0)
-			return ret;
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_ERRNO_NEXT;
-		return 0;
-	case I2CP_CMD_MXFER_REPLY_STATE_ERRNO_NEXT:
-		ret = kstrtoint(in, 0, &reply_errno);
-		if (ret < 0)
-			return ret;
-		break;
-	default:
-		/* Reaching here is a bug. */
-		return -EINVAL;
-	}
-
-	/*
-	 * Only I2CP_CMD_MXFER_REPLY_STATE_ERRNO_NEXT can reach this point.
-	 * Now that we've received all of the headers, find the matching
-	 * mxfer_reply.
-	 */
-	i2cp_mxfer_reply_update_current(cmd_data);
-
-	if (reply_errno || !cmd_data->reply_queue_current_item) {
-		/*
-		 * reply_errno:
-		 * Drop the specific errno for now.  The Linux I2C API
-		 * does not provide a way to return an errno for a
-		 * specific message within a master_xfer() call.  The
-		 * cmd_completer callback will indicate this
-		 * controller-reported failure by not incrementing
-		 * mxfer_reply->ret for this I2C msg reply.
-		 *
-		 * cmd_data->reply_queue_current_item == NULL:
-		 * No matching mxfer_reply was found.  Discard any
-		 * further input in this command.  The cmd_completer
-		 * callback will indicate this failure to the
-		 * controller.
-		 */
-		cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_INVALID;
-		/*
-		 * Ask for data bytes in multiples of 1, i.e. no
-		 * boundary requirements, because the we're just going
-		 * to discard it.  The next field could even be a header
-		 * instead of data, but it doesn't matter, we're going
-		 * to continue discarding the write input until the end
-		 * of this write command.
-		 */
-		return 1;
-	}
-
-	cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_DATA_NEXT;
-	/*
-	 * Ask for data bytes in multiples of 3.  Expected format is
-	 * hexadecimal NN:NN:... e.g. "3C:05:F1:01" is a possible 4 byte
-	 * data value.
-	 */
-	return 3;
-}
-
-static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	int ret;
-	char u8_hex[3] = {0};
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-	struct i2cp_cmd_mxfer_reply *mxfer_reply;
-	struct i2c_msg *i2c_msg;
-
-	cmd_data = data;
-
-	if (cmd_data->state == I2CP_CMD_MXFER_REPLY_STATE_INVALID)
-		return 0;
-	if (cmd_data->state != I2CP_CMD_MXFER_REPLY_STATE_DATA_NEXT)
-		/* Reaching here is a bug. */
-		return -EINVAL;
-
-	mutex_lock(&cmd_data->reply_queue_lock);
-	mxfer_reply = cmd_data->reply_queue_current_item;
-	if (!mxfer_reply) {
-		/* Reaching here is a bug. */
-		mutex_unlock(&cmd_data->reply_queue_lock);
-		return -EINVAL;
-	}
-	mutex_lock(&mxfer_reply->lock);
-	mutex_unlock(&cmd_data->reply_queue_lock);
-
-	if (cmd_data->current_msg_idx < 0 ||
-	    cmd_data->current_msg_idx >= mxfer_reply->num_msgs) {
-		/* Reaching here is a bug. */
-		ret = -EINVAL;
-		goto unlock;
-	}
-
-	i2c_msg = &mxfer_reply->msgs[cmd_data->current_msg_idx];
-
-	if (!(i2c_msg->flags & I2C_M_RD)) {
-		/* The controller responded to a write with data. */
-		ret = -EIO;
-		goto unlock;
-	}
-
-	if (i2c_msg->flags & I2C_M_RECV_LEN) {
-		/*
-		 * When I2C_M_RECV_LEN is set, struct i2c_algorithm.master_xfer
-		 * is expected to increment struct i2c_msg.len by the actual
-		 * amount of bytes read.
-		 *
-		 * Given the above, an initial struct i2c_msg.len value of 0
-		 * would be reasonable, since it will be incremented for each
-		 * byte read.
-		 *
-		 * An initial value of 1 representing the expected size byte
-		 * also makes sense, and appears to be common practice.
-		 *
-		 * We consider a larger initial value to indicate a bug in the
-		 * I2C/SMBus client, because it's difficult to reconcile such a
-		 * value with the documented requirement that struct i2c_msg.len
-		 * be "incremented by the number of block data bytes received."
-		 * Besides returning an error, our only options would be to
-		 * ignore and blow away a value that was potentially meaningful
-		 * to the client (e.g. if it indicates the maximum buffer size),
-		 * assume the value is the buffer size or expected read size
-		 * (which would conflict with the documentation), or just
-		 * blindly increment it, leaving it at a value greater than the
-		 * actual number of bytes we wrote to the buffer, and likely
-		 * indicating a size larger than the actual buffer allocation.
-		 */
-		if (cmd_data->current_buf_idx == 0) {
-			if (i2c_msg->len > 1) {
-				ret = -EPROTO;
-				goto unlock;
-			}
-			/*
-			 * Subtract the read size byte because the in_size
-			 * increment in the loop below will re-add it.
-			 */
-			i2c_msg->len = 0;
-		}
-	}
-
-	while (in_size > 0 && cmd_data->current_buf_idx < i2c_msg->len) {
-		if (in_size < 2 ||
-		    (in_size > 2 && in[2] != i2cp_ctrlr_data_sep_char) ||
-		    memchr(in, '\0', 2)) {
-			/*
-			 * Reaching here is a bug in the userspace I2C pseudo
-			 * adapter controller.  (Or possibly a bug in this
-			 * module itself, of course.)
-			 */
-			ret = -EIO;
-			goto unlock;
-		}
-		/*
-		 * When using I2C_M_RECV_LEN, the buffer is required to be able
-		 * to hold:
-		 *
-		 * I2C_SMBUS_BLOCK_MAX
-		 * +1 byte for the read size (first byte)
-		 * +1 byte for the optional PEC byte (last byte if present).
-		 *
-		 * If reading the next byte would exceed that, return EPROTO
-		 * error per Documentation/i2c/fault-codes .
-		 */
-		if (i2c_msg->flags & I2C_M_RECV_LEN &&
-		    i2c_msg->len >= I2C_SMBUS_BLOCK_MAX + 2) {
-			ret = -EPROTO;
-			goto unlock;
-		}
-		/* Use u8_hex to get a terminating null byte for kstrtou8(). */
-		memcpy(u8_hex, in, 2);
-		/*
-		 * TODO: Do we need to do anything different based on the
-		 * I2C_M_DMA_SAFE bit? Do we ever need to use copy_to_user()?
-		 */
-		ret = kstrtou8(u8_hex, 16,
-			&i2c_msg->buf[cmd_data->current_buf_idx]);
-		if (ret < 0)
-			goto unlock;
-		if (i2c_msg->flags & I2C_M_RECV_LEN)
-			++i2c_msg->len;
-		++cmd_data->current_buf_idx;
-		in += min_t(size_t, 3, in_size);
-		in_size -= min_t(size_t, 3, in_size);
-	}
-
-	/* Quietly ignore any bytes beyond the buffer size. */
-	ret = 0;
-
- unlock:
-	mutex_unlock(&mxfer_reply->lock);
-	return ret;
-}
-
-static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	int ret;
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-	struct i2cp_cmd_mxfer_reply *mxfer_reply;
-	struct i2c_msg *i2c_msg;
-
-	cmd_data = data;
-	mutex_lock(&cmd_data->reply_queue_lock);
-
-	mxfer_reply = cmd_data->reply_queue_current_item;
-	if (!mxfer_reply) {
-		mutex_unlock(&cmd_data->reply_queue_lock);
-		ret = -EIO;
-		goto reset_cmd_data;
-	}
-
-	mutex_lock(&mxfer_reply->lock);
-
-	if (mxfer_reply->completed[cmd_data->current_msg_idx]) {
-		/* We already received a reply for this msg. */
-		mutex_unlock(&cmd_data->reply_queue_lock);
-		mutex_unlock(&mxfer_reply->lock);
-		ret = -EIO;
-		goto reset_cmd_data;
-	}
-
-	mxfer_reply->completed[cmd_data->current_msg_idx] = true;
-	if (++mxfer_reply->num_completed_true >= mxfer_reply->num_msgs) {
-		list_del_init(&mxfer_reply->reply_queue_item);
-		--cmd_data->reply_queue_length;
-		cmd_data->reply_queue_current_item = NULL;
-		complete_all(&mxfer_reply->data_filled);
-	}
-
-	mutex_unlock(&cmd_data->reply_queue_lock);
-	i2c_msg = &mxfer_reply->msgs[cmd_data->current_msg_idx];
-
-	if (!receive_status &&
-	    cmd_data->state == I2CP_CMD_MXFER_REPLY_STATE_DATA_NEXT &&
-	    (!(i2c_msg->flags & I2C_M_RD) ||
-	     cmd_data->current_buf_idx >= i2c_msg->len))
-		++mxfer_reply->ret;
-
-	mutex_unlock(&mxfer_reply->lock);
-	ret = 0;
-
- reset_cmd_data:
-	cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT;
-	cmd_data->current_id = 0;
-	cmd_data->current_addr = 0;
-	cmd_data->current_flags = 0;
-	cmd_data->current_msg_idx = 0;
-	cmd_data->current_buf_idx = 0;
-	return ret;
-}
-
-static int i2cp_cmd_adap_start_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * No more header fields or data are expected.  This directs any further
-	 * input in this command to the data_receiver, which for this write
-	 * command will unconditionally indicate a controller error.
-	 */
-	return 1;
-}
-
-static int i2cp_cmd_adap_start_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * Reaching here means the controller wrote extra data in the command
-	 * line after the initial command name.  That is unexpected and
-	 * indicates a controller bug.
-	 */
-	return -EPROTO;
-}
-
-static int i2cp_cmd_adap_start_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	int ret;
-
-	/* Refuse to start if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	/*
-	 * Acquire pdata->startstop_lock manually instead of using
-	 * i2cp_adap_get_state() in order to keep the lock while calling
-	 * i2c_add_adapter().
-	 */
-	mutex_lock(&pdata->startstop_lock);
-
-	if (pdata->startstop_state != I2CP_CTRLR_STATE_NEW) {
-		ret = -EISCONN;
-		goto unlock;
-	}
-
-	/* Add the I2C adapter. */
-	ret = i2c_add_adapter(&pdata->i2c_adapter);
-	if (ret < 0)
-		goto unlock;
-
-	pdata->startstop_state = I2CP_CTRLR_STATE_RUNNING;
-
-	/* Add the I2C pseudo controller ID sysfs file. */
-	ret = device_create_file(&pdata->i2c_adapter.dev, &i2cp_id_dev_attr);
-	if (ret < 0)
-		goto unlock;
-
-	ret = 0;
-
- unlock:
-	mutex_unlock(&pdata->startstop_lock);
-	return ret;
-}
-
-static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * No more header fields or data are expected.  This directs any further
-	 * input in this command to the data_receiver, which for this write
-	 * command will unconditionally indicate a controller error.
-	 */
-	return 1;
-}
-
-static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * Reaching here means the controller wrote extra data in the command
-	 * line after the initial command name.  That is unexpected and
-	 * indicates a controller bug.
-	 */
-	return -EPROTO;
-}
-
-static int i2cp_cmd_adap_shutdown_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	/* Refuse to shutdown if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	mutex_lock(&pdata->startstop_lock);
-	pdata->startstop_state = I2CP_CTRLR_STATE_SHUTDN_REQ;
-	mutex_unlock(&pdata->startstop_lock);
-
-	/* Wake up blocked controller readers. */
-	complete_all(&pdata->read_rsp_queued);
-	/* Wake up blocked controller pollers. */
-	wake_up_interruptible_all(&pdata->poll_wait_queue);
-	return 0;
-}
-
-static int i2cp_cmd_get_number_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * No more header fields or data are expected.  This directs any further
-	 * input in this command to the data_receiver, which for this write
-	 * command will unconditionally indicate a controller error.
-	 */
-	return 1;
-}
-
-static int i2cp_cmd_get_number_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * Reaching here means the controller wrote extra data in the command
-	 * line after the initial command name.  That is unexpected and
-	 * indicates a controller bug.
-	 */
-	return -EPROTO;
-}
-
-static int i2cp_cmd_get_number_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	ssize_t ret;
-	int i2c_adap_nr;
-	struct i2cp_rsp_buffer *rsp_buf;
-	struct i2cp_rsp *rsp_wrapper;
-
-	/* Abort if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	/*
-	 * Check the pseudo controller startstop_state.  If it's running, get
-	 * the I2C adapter number.
-	 *
-	 * Acquire pdata->startstop_lock manually instead of using
-	 * i2cp_adap_get_state() in order to keep the lock while retrieving the
-	 * I2C adapter number.
-	 */
-	mutex_lock(&pdata->startstop_lock);
-	if (pdata->startstop_state != I2CP_CTRLR_STATE_RUNNING) {
-		mutex_unlock(&pdata->startstop_lock);
-		return -ENOTCONN;
-	}
-	i2c_adap_nr = pdata->i2c_adapter.nr;
-	mutex_unlock(&pdata->startstop_lock);
-
-	rsp_wrapper = kzalloc(sizeof(*rsp_wrapper), GFP_KERNEL);
-	if (!rsp_wrapper)
-		return -ENOMEM;
-
-	rsp_buf = kzalloc(sizeof(*rsp_buf), GFP_KERNEL);
-	if (!rsp_buf) {
-		ret = -ENOMEM;
-		goto fail_after_rsp_wrapper_alloc;
-	}
-
-	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%d",
-		(int)strlen(I2CP_NUMBER_REPLY_CMD), I2CP_NUMBER_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, i2c_adap_nr);
-	if (ret < 0) {
-		goto fail_after_rsp_buf_alloc;
-	} else if (ret == 0) {
-		ret = -EINVAL;
-		goto fail_after_buf_alloc;
-	}
-	rsp_buf->size = ret;
-
-	rsp_wrapper->data = rsp_buf;
-	rsp_wrapper->formatter = i2cp_rsp_buffer_formatter;
-
-	mutex_lock(&pdata->read_rsp_queue_lock);
-	if (pdata->read_rsp_queue_length >= I2CP_CTRLR_RSP_QUEUE_LIMIT) {
-		ret = -ENOBUFS;
-		mutex_unlock(&pdata->read_rsp_queue_lock);
-		goto fail_after_buf_alloc;
-	}
-
-	list_add_tail(&rsp_wrapper->queue, &pdata->read_rsp_queue_head);
-	++pdata->read_rsp_queue_length;
-	complete(&pdata->read_rsp_queued);
-
-	mutex_unlock(&pdata->read_rsp_queue_lock);
-	return 0;
-
- fail_after_buf_alloc:
-	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
-	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
-	kfree(rsp_wrapper);
-	return ret;
-}
-
-static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * No more header fields or data are expected.  This directs any further
-	 * input in this command to the data_receiver, which for this write
-	 * command will unconditionally indicate a controller error.
-	 */
-	return 1;
-}
-
-static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * Reaching here means the controller wrote extra data in the command
-	 * line after the initial command name.  That is unexpected and
-	 * indicates a controller bug.
-	 */
-	return -EPROTO;
-}
-
-static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	ssize_t ret;
-	struct i2cp_rsp_buffer *rsp_buf;
-	struct i2cp_rsp *rsp_wrapper;
-
-	/* Abort if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	rsp_wrapper = kzalloc(sizeof(*rsp_wrapper), GFP_KERNEL);
-	if (!rsp_wrapper)
-		return -ENOMEM;
-
-	rsp_buf = kzalloc(sizeof(*rsp_buf), GFP_KERNEL);
-	if (!rsp_buf) {
-		ret = -ENOMEM;
-		goto fail_after_rsp_wrapper_alloc;
-	}
-
-	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%u",
-		(int)strlen(I2CP_PSEUDO_ID_REPLY_CMD), I2CP_PSEUDO_ID_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, pdata->id);
-	if (ret < 0) {
-		goto fail_after_rsp_buf_alloc;
-	} else if (ret == 0) {
-		ret = -EINVAL;
-		goto fail_after_buf_alloc;
-	}
-	rsp_buf->size = ret;
-
-	rsp_wrapper->data = rsp_buf;
-	rsp_wrapper->formatter = i2cp_rsp_buffer_formatter;
-
-	mutex_lock(&pdata->read_rsp_queue_lock);
-	if (pdata->read_rsp_queue_length >= I2CP_CTRLR_RSP_QUEUE_LIMIT) {
-		ret = -ENOBUFS;
-		mutex_unlock(&pdata->read_rsp_queue_lock);
-		goto fail_after_buf_alloc;
-	}
-
-	list_add_tail(&rsp_wrapper->queue, &pdata->read_rsp_queue_head);
-	++pdata->read_rsp_queue_length;
-	complete(&pdata->read_rsp_queued);
-
-	mutex_unlock(&pdata->read_rsp_queue_lock);
-	return 0;
-
- fail_after_buf_alloc:
-	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
-	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
-	kfree(rsp_wrapper);
-	return ret;
-}
-
-static int i2cp_cmd_set_name_suffix_data_creator(void **data)
-{
-	struct i2cp_cmd_set_name_suffix_data *cmd_data;
-
-	cmd_data = kzalloc(sizeof(*cmd_data), GFP_KERNEL);
-	if (!cmd_data)
-		return -ENOMEM;
-	*data = cmd_data;
-	return 0;
-}
-
-static void i2cp_cmd_set_name_suffix_data_destroyer(void *data)
-{
-	kfree(data);
-}
-
-static int i2cp_cmd_set_name_suffix_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	return 1;
-}
-
-static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	size_t remaining;
-	struct i2cp_cmd_set_name_suffix_data *cmd_data;
-
-	cmd_data = data;
-	remaining = sizeof(cmd_data->name_suffix) - cmd_data->name_suffix_len;
-	/* Quietly truncate the suffix if necessary. */
-	/* The suffix may need to be further truncated later. */
-	if (in_size > remaining)
-		in_size = remaining;
-	memcpy(&cmd_data->name_suffix[cmd_data->name_suffix_len], in, in_size);
-	cmd_data->name_suffix_len += in_size;
-	return 0;
-}
-
-static int i2cp_cmd_set_name_suffix_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	int ret;
-	struct i2cp_cmd_set_name_suffix_data *cmd_data;
-
-	/* Abort if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	/*
-	 * Acquire pdata->startstop_lock manually instead of using
-	 * i2cp_adap_get_state() in order to keep the lock while
-	 * setting the I2C adapter name.
-	 */
-	mutex_lock(&pdata->startstop_lock);
-
-	if (pdata->startstop_state != I2CP_CTRLR_STATE_NEW) {
-		ret = -EISCONN;
-		goto unlock;
-	}
-
-	cmd_data = data;
-	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u %*s", pdata->id,
-		(int)cmd_data->name_suffix_len, cmd_data->name_suffix);
-	if (ret < 0)
-		goto unlock;
-
-	ret = 0;
-
- unlock:
-	mutex_unlock(&pdata->startstop_lock);
-	return ret;
-}
-
-static int i2cp_cmd_set_timeout_data_creator(void **data)
-{
-	struct i2cp_cmd_set_timeout_data *cmd_data;
-
-	cmd_data = kzalloc(sizeof(*cmd_data), GFP_KERNEL);
-	if (!cmd_data)
-		return -ENOMEM;
-	*data = cmd_data;
-	return 0;
-}
-
-static void i2cp_cmd_set_timeout_data_destroyer(void *data)
-{
-	kfree(data);
-}
-
-static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	int ret;
-	struct i2cp_cmd_set_timeout_data *cmd_data;
-
-	cmd_data = data;
-	switch (cmd_data->field_pos++) {
-	case 0:
-		return 0;
-	case 1:
-		ret = kstrtouint(in, 0, &cmd_data->timeout_ms);
-		if (ret < 0)
-			return ret;
-		return 1;
-	}
-	/* Reaching here is a bug. */
-	return -EINVAL;
-}
-
-static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
-{
-	/*
-	 * Reaching here means the controller wrote extra data in the command
-	 * line.  That is unexpected and indicates a controller bug.
-	 */
-	return -EPROTO;
-}
-
-static int i2cp_cmd_set_timeout_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
-{
-	int ret;
-	struct i2cp_cmd_set_timeout_data *cmd_data;
-
-	/* Abort if there were errors processing this command. */
-	if (receive_status)
-		return 0;
-
-	/*
-	 * Acquire pdata->startstop_lock manually instead of using
-	 * i2cp_adap_get_state() in order to keep the lock while setting the
-	 * I2C adapter name.
-	 */
-	mutex_lock(&pdata->startstop_lock);
-
-	if (pdata->startstop_state != I2CP_CTRLR_STATE_NEW) {
-		ret = -EISCONN;
-		goto unlock;
-	}
-
-	cmd_data = data;
-	if (cmd_data->timeout_ms < I2CP_TIMEOUT_MS_MIN ||
-		cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) {
-		ret = -ERANGE;
-		goto unlock;
-	}
-
-	pdata->i2c_adapter.timeout = msecs_to_jiffies(cmd_data->timeout_ms);
-	ret = 0;
-
- unlock:
-	mutex_unlock(&pdata->startstop_lock);
-	return ret;
-}
-
-/* Command names are matched in this order, so sort by expected frequency. */
-/* All elements should be initialized in their I2CP_CMD_*_IDX position. */
-static const struct i2cp_cmd i2cp_cmds[] = {
-	[I2CP_CMD_MXFER_REPLY_IDX] = {
-		.cmd_string = I2CP_MXFER_REPLY_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_MXFER_REPLY_CMD),
-		.data_creator = i2cp_cmd_mxfer_reply_data_creator,
-		.data_shutdown = i2cp_cmd_mxfer_reply_data_shutdown,
-		.data_destroyer = i2cp_cmd_mxfer_reply_data_destroyer,
-		.header_receiver = i2cp_cmd_mxfer_reply_header_receiver,
-		.data_receiver = i2cp_cmd_mxfer_reply_data_receiver,
-		.cmd_completer = i2cp_cmd_mxfer_reply_cmd_completer,
-	},
-	[I2CP_CMD_ADAP_START_IDX] = {
-		.cmd_string = I2CP_ADAP_START_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_ADAP_START_CMD),
-		.header_receiver = i2cp_cmd_adap_start_header_receiver,
-		.data_receiver = i2cp_cmd_adap_start_data_receiver,
-		.cmd_completer = i2cp_cmd_adap_start_cmd_completer,
-	},
-	[I2CP_CMD_ADAP_SHUTDOWN_IDX] = {
-		.cmd_string = I2CP_ADAP_SHUTDOWN_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_ADAP_SHUTDOWN_CMD),
-		.header_receiver = i2cp_cmd_adap_shutdown_header_receiver,
-		.data_receiver = i2cp_cmd_adap_shutdown_data_receiver,
-		.cmd_completer = i2cp_cmd_adap_shutdown_cmd_completer,
-	},
-	[I2CP_CMD_GET_NUMBER_IDX] = {
-		.cmd_string = I2CP_GET_NUMBER_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_GET_NUMBER_CMD),
-		.header_receiver = i2cp_cmd_get_number_header_receiver,
-		.data_receiver = i2cp_cmd_get_number_data_receiver,
-		.cmd_completer = i2cp_cmd_get_number_cmd_completer,
-	},
-	[I2CP_CMD_GET_PSEUDO_ID_IDX] = {
-		.cmd_string = I2CP_GET_PSEUDO_ID_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_GET_PSEUDO_ID_CMD),
-		.header_receiver = i2cp_cmd_get_pseudo_id_header_receiver,
-		.data_receiver = i2cp_cmd_get_pseudo_id_data_receiver,
-		.cmd_completer = i2cp_cmd_get_pseudo_id_cmd_completer,
-	},
-	[I2CP_CMD_SET_NAME_SUFFIX_IDX] = {
-		.cmd_string = I2CP_SET_NAME_SUFFIX_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_SET_NAME_SUFFIX_CMD),
-		.data_creator = i2cp_cmd_set_name_suffix_data_creator,
-		.data_destroyer = i2cp_cmd_set_name_suffix_data_destroyer,
-		.header_receiver = i2cp_cmd_set_name_suffix_header_receiver,
-		.data_receiver = i2cp_cmd_set_name_suffix_data_receiver,
-		.cmd_completer = i2cp_cmd_set_name_suffix_cmd_completer,
-	},
-	[I2CP_CMD_SET_TIMEOUT_IDX] = {
-		.cmd_string = I2CP_SET_TIMEOUT_CMD,
-		.cmd_size = CONST_STRLEN(I2CP_SET_TIMEOUT_CMD),
-		.data_creator = i2cp_cmd_set_timeout_data_creator,
-		.data_destroyer = i2cp_cmd_set_timeout_data_destroyer,
-		.header_receiver = i2cp_cmd_set_timeout_header_receiver,
-		.data_receiver = i2cp_cmd_set_timeout_data_receiver,
-		.cmd_completer = i2cp_cmd_set_timeout_cmd_completer,
-	},
-};
-
-/* Returns whether or not there is response queue data to read. */
-/* Must be called with pdata->rsp_lock held. */
-static inline bool i2cp_poll_in(struct i2cp_controller *pdata)
-{
-	return pdata->rsp_invalidated || pdata->rsp_buf_remaining != 0 ||
-		!list_empty(&pdata->read_rsp_queue_head);
-}
-
-static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper,
-	struct i2cp_rsp_buffer *rsp_buf, char *contents, size_t size)
-{
-	rsp_buf->buf = kmemdup(contents, size, GFP_KERNEL);
-	if (!rsp_buf->buf)
-		return -ENOMEM;
-	rsp_buf->size = size;
-	rsp_wrapper->data = rsp_buf;
-	rsp_wrapper->formatter = i2cp_rsp_buffer_formatter;
-	return 0;
-}
-
-#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal)\
-	i2cp_fill_rsp_buf(\
-		rsp_wrapper, rsp_buf, str_literal, strlen(str_literal))
-
-static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
-	struct i2c_msg *msgs, int num)
-{
-	int i, ret = 0;
-	long wait_ret;
-	size_t wrappers_length, wrapper_idx = 0, rsp_bufs_idx = 0;
-	struct i2cp_controller *pdata;
-	struct i2cp_rsp **rsp_wrappers;
-	struct i2cp_rsp_buffer *rsp_bufs[2] = {0};
-	struct i2cp_rsp_master_xfer *mxfer_rsp;
-	struct i2cp_cmd_mxfer_reply_data *cmd_data;
-	struct i2cp_cmd_mxfer_reply *mxfer_reply;
-
-	if (num <= 0) {
-		if (num < 0)
-			return -EINVAL;
-		return ret;
-	}
-
-	pdata = adap->algo_data;
-	cmd_data = pdata->cmd_data[I2CP_CMD_MXFER_REPLY_IDX];
-
-	switch (i2cp_adap_get_state(pdata)) {
-	case I2CP_CTRLR_STATE_RUNNING:
-		break;
-	case I2CP_CTRLR_STATE_SHUTDN_REQ:
-		return ret;
-	default:
-		/* Reaching here is a bug, even with a valid enum value. */
-		return -EINVAL;
-	}
-
-	wrappers_length = (size_t)num + ARRAY_SIZE(rsp_bufs);
-	rsp_wrappers = kcalloc(wrappers_length, sizeof(*rsp_wrappers),
-		GFP_KERNEL);
-	if (!rsp_wrappers)
-		return -ENOMEM;
-
-	mxfer_reply = kzalloc(sizeof(*mxfer_reply), GFP_KERNEL);
-	if (!mxfer_reply) {
-		ret = -ENOMEM;
-		goto return_after_rsp_wrappers_ptrs_alloc;
-	}
-
-	mxfer_reply->num_msgs = num;
-	init_completion(&mxfer_reply->data_filled);
-	mutex_init(&mxfer_reply->lock);
-
-	mxfer_reply->msgs = kcalloc(num, sizeof(*mxfer_reply->msgs),
-		GFP_KERNEL);
-	if (!mxfer_reply->msgs) {
-		ret = -ENOMEM;
-		goto return_after_mxfer_reply_alloc;
-	}
-
-	mxfer_reply->completed = kcalloc(num, sizeof(*mxfer_reply->completed),
-		GFP_KERNEL);
-	if (!mxfer_reply->completed) {
-		ret = -ENOMEM;
-		goto return_after_reply_msgs_alloc;
-	}
-
-	for (i = 0; i < num; ++i) {
-		mxfer_reply->msgs[i].addr = msgs[i].addr;
-		mxfer_reply->msgs[i].flags = msgs[i].flags;
-		mxfer_reply->msgs[i].len = msgs[i].len;
-		if (msgs[i].flags & I2C_M_RD)
-			/* Copy the address, not the data. */
-			mxfer_reply->msgs[i].buf = msgs[i].buf;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(rsp_bufs); ++i) {
-		rsp_bufs[i] = kzalloc(sizeof(*rsp_bufs[i]), GFP_KERNEL);
-		if (!rsp_bufs[i]) {
-			ret = -ENOMEM;
-			goto return_after_reply_completed_alloc;
-		}
-	}
-
-	mxfer_rsp = kzalloc(sizeof(*mxfer_rsp), GFP_KERNEL);
-	if (!mxfer_rsp) {
-		ret = -ENOMEM;
-		goto fail_after_individual_rsp_bufs_alloc;
-	}
-
-	mxfer_rsp->id = cmd_data->next_mxfer_id++;
-	mxfer_rsp->num = num;
-
-	mxfer_rsp->msgs = kcalloc(num, sizeof(*mxfer_rsp->msgs), GFP_KERNEL);
-	if (!mxfer_rsp->msgs) {
-		ret = -ENOMEM;
-		goto fail_after_mxfer_rsp_alloc;
-	}
-
-	for (i = 0; i < num; ++i) {
-		mxfer_rsp->msgs[i].addr = msgs[i].addr;
-		mxfer_rsp->msgs[i].flags = msgs[i].flags;
-		mxfer_rsp->msgs[i].len = msgs[i].len;
-		if (msgs[i].flags & I2C_M_RD)
-			continue;
-		/* Copy the data, not the address. */
-		mxfer_rsp->msgs[i].buf = kmemdup(msgs[i].buf, msgs[i].len,
-			GFP_KERNEL);
-		if (!mxfer_rsp->msgs[i].buf) {
-			ret = -ENOMEM;
-			goto fail_after_rsp_msgs_alloc;
-		}
-	}
-
-	for (i = 0; i < wrappers_length; ++i) {
-		rsp_wrappers[i] = kzalloc(sizeof(*rsp_wrappers[i]), GFP_KERNEL);
-		if (!rsp_wrappers[i]) {
-			ret = -ENOMEM;
-			goto fail_after_individual_rsp_wrappers_alloc;
-		}
-	}
-
-	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_BEGIN_MXFER_REQ_CMD);
-	if (ret < 0)
-		goto fail_after_individual_rsp_wrappers_alloc;
-
-	for (i = 0; i < num; ++i) {
-		rsp_wrappers[wrapper_idx]->data = mxfer_rsp;
-		rsp_wrappers[wrapper_idx++]->formatter =
-			i2cp_rsp_master_xfer_formatter;
-	}
-
-	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_COMMIT_MXFER_REQ_CMD);
-	if (ret < 0)
-		goto fail_after_individual_rsp_wrappers_alloc;
-
-	BUILD_BUG_ON(rsp_bufs_idx != ARRAY_SIZE(rsp_bufs));
-
-	mutex_lock(&pdata->read_rsp_queue_lock);
-	if (pdata->read_rsp_queue_length >= I2CP_CTRLR_RSP_QUEUE_LIMIT) {
-		ret = -ENOBUFS;
-		goto fail_with_read_rsp_queue_lock;
-	}
-
-	mutex_lock(&cmd_data->reply_queue_lock);
-	if (cmd_data->reply_queue_length >= I2CP_CTRLR_RSP_QUEUE_LIMIT) {
-		ret = -ENOBUFS;
-		goto fail_with_reply_queue_lock;
-	}
-
-	mxfer_reply->id = mxfer_rsp->id;
-	list_add_tail(&mxfer_reply->reply_queue_item,
-		&cmd_data->reply_queue_head);
-	++cmd_data->reply_queue_length;
-
-	for (i = 0; i < wrappers_length; ++i) {
-		list_add_tail(&rsp_wrappers[i]->queue,
-			&pdata->read_rsp_queue_head);
-		complete(&pdata->read_rsp_queued);
-	}
-	pdata->read_rsp_queue_length += wrappers_length;
-
-	mutex_unlock(&cmd_data->reply_queue_lock);
-	mutex_unlock(&pdata->read_rsp_queue_lock);
-
-	/* Wake up the userspace controller if it was polling. */
-	wake_up_interruptible(&pdata->poll_wait_queue);
-	/* Wait for a response from the userspace controller. */
-	wait_ret = wait_for_completion_killable_timeout(
-		&mxfer_reply->data_filled, adap->timeout);
-
-	mutex_lock(&cmd_data->reply_queue_lock);
-	/*
-	 * Ensure mxfer_reply is not in use before dequeuing and freeing it.
-	 * This depends on the requirement that mxfer_reply->lock only be
-	 * acquired while holding cmd_data->reply_queue_lock.
-	 */
-	mutex_lock(&mxfer_reply->lock);
-
-	if (wait_ret == -ERESTARTSYS)
-		ret = -EINTR;
-	else if (wait_ret < 0)
-		ret = wait_ret;
-	else
-		ret = mxfer_reply->ret;
-
-	/*
-	 * This depends on other functions that might delete
-	 * mxfer_reply->reply_queue_item from cmd_data->reply_queue_head using
-	 * list_del_init(), never list_del().
-	 */
-	if (!list_empty(&mxfer_reply->reply_queue_item)) {
-		list_del(&mxfer_reply->reply_queue_item);
-		--cmd_data->reply_queue_length;
-		if (mxfer_reply == cmd_data->reply_queue_current_item)
-			cmd_data->reply_queue_current_item = NULL;
-	}
-
-	mutex_unlock(&mxfer_reply->lock);
-	mutex_unlock(&cmd_data->reply_queue_lock);
-	goto return_after_reply_msgs_alloc;
-
- fail_with_reply_queue_lock:
-	mutex_unlock(&cmd_data->reply_queue_lock);
- fail_with_read_rsp_queue_lock:
-	mutex_unlock(&pdata->read_rsp_queue_lock);
- fail_after_individual_rsp_wrappers_alloc:
-	for (i = 0; i < wrappers_length; ++i)
-		kfree(rsp_wrappers[i]);
- fail_after_rsp_msgs_alloc:
-	for (i = 0; i < num; ++i)
-		kfree(mxfer_rsp->msgs[i].buf);
-	kfree(mxfer_rsp->msgs);
- fail_after_mxfer_rsp_alloc:
-	kfree(mxfer_rsp);
- fail_after_individual_rsp_bufs_alloc:
-	for (i = 0; i < ARRAY_SIZE(rsp_bufs); ++i) {
-		kfree(rsp_bufs[i]->buf);
-		kfree(rsp_bufs[i]);
-	}
- return_after_reply_completed_alloc:
-	kfree(mxfer_reply->completed);
- return_after_reply_msgs_alloc:
-	kfree(mxfer_reply->msgs);
- return_after_mxfer_reply_alloc:
-	kfree(mxfer_reply);
- return_after_rsp_wrappers_ptrs_alloc:
-	kfree(rsp_wrappers);
-	return ret;
-}
-
-/*
- * If more functionality than this needs to be supported, add a write command
- * for the controller to specify its additional functionality prior to
- * ADAPTER_START.  Basic I2C functionality should remain implied and required.
- *
- * These functionalities in particular could be worth supporting:
- * I2C_FUNC_10BIT_ADDR
- * I2C_FUNC_NOSTART
- * I2C_FUNC_PROTOCOL_MANGLING
- */
-static u32 i2cp_adapter_functionality(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm i2cp_algorithm = {
-	.master_xfer = i2cp_adapter_master_xfer,
-	.functionality = i2cp_adapter_functionality,
-};
-
-/* this_pseudo->counters.lock must _not_ be held when calling this. */
-static void i2cp_remove_from_counters(struct i2cp_controller *pdata,
-	struct i2cp_device *this_pseudo)
-{
-
-	mutex_lock(&this_pseudo->counters.lock);
-	this_pseudo->counters.all_controllers[pdata->index] = NULL;
-	--this_pseudo->counters.count;
-	mutex_unlock(&this_pseudo->counters.lock);
-}
-
-static int i2cp_cdev_open(struct inode *inodep, struct file *filep)
-{
-	int ret = 0;
-	unsigned int i, num_cmd_data_created = 0;
-	unsigned int ctrlr_id;
-	struct i2cp_controller *pdata;
-	struct i2cp_device *this_pseudo;
-
-	/* Is there any way to find this through @inodep? */
-	this_pseudo = i2cp_device;
-
-	/*
-	 * HAVE_STREAM_OPEN value meanings:
-	 *   -1 : stream_open() is not available
-	 *    0 : unknown if stream_open() is or is not available
-	 *    1 : stream_open() is available
-	 */
-#if HAVE_STREAM_OPEN >= 0
-	/* I2C pseudo adapter controllers are non-seekable pure I/O streams. */
-	stream_open(inodep, filep);
-#else
-	/* I2C pseudo adapter controllers are not seekable. */
-	nonseekable_open(inodep, filep);
-#endif
-	/* Refuse fsnotify events.  Modeled after /dev/ptmx implementation. */
-	filep->f_mode |= FMODE_NONOTIFY;
-
-	/* Allocate the I2C adapter. */
-	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-	if (!pdata)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&pdata->read_rsp_queue_head);
-	init_waitqueue_head(&pdata->poll_wait_queue);
-	init_completion(&pdata->read_rsp_queued);
-	mutex_init(&pdata->startstop_lock);
-	mutex_init(&pdata->cmd_lock);
-	mutex_init(&pdata->rsp_lock);
-	mutex_init(&pdata->read_rsp_queue_lock);
-
-	for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i) {
-		if (!i2cp_cmds[i].data_creator)
-			continue;
-		ret = i2cp_cmds[i].data_creator(&pdata->cmd_data[i]);
-		if (ret < 0)
-			break;
-	}
-	num_cmd_data_created = i;
-	if (ret < 0)
-		goto fail_after_cmd_data_created;
-
-	mutex_lock(&this_pseudo->counters.lock);
-
-	for (i = 0; i < i2cp_limit; ++i)
-		if (!this_pseudo->counters.all_controllers[i])
-			break;
-	if (i >= i2cp_limit) {
-		mutex_unlock(&this_pseudo->counters.lock);
-		ret = -ENOSPC;
-		goto fail_after_cmd_data_created;
-	}
-	pdata->index = i;
-
-	for (ctrlr_id = this_pseudo->counters.next_ctrlr_id;;) {
-		/* Determine whether ctrlr_id is already in use. */
-		for (i = 0; i < i2cp_limit; ++i) {
-			if (this_pseudo->counters.all_controllers[i] &&
-			    (this_pseudo->counters.all_controllers[i]->id ==
-			     ctrlr_id))
-				break;
-		}
-		/* If ctrlr_id is available, use it. */
-		if (i >= i2cp_limit) {
-			pdata->id = ctrlr_id;
-			this_pseudo->counters.next_ctrlr_id = ctrlr_id + 1;
-			++this_pseudo->counters.count;
-			this_pseudo->counters.all_controllers[pdata->index] =
-				pdata;
-			break;
-		}
-		/* Increment ctrlr_id, and check for wrapping. */
-		if (++ctrlr_id == this_pseudo->counters.next_ctrlr_id) {
-			mutex_unlock(&this_pseudo->counters.lock);
-			ret = -ENOSPC;
-			goto fail_after_cmd_data_created;
-		}
-	}
-
-	mutex_unlock(&this_pseudo->counters.lock);
-
-	/* Initialize the I2C adapter. */
-	pdata->i2c_adapter.owner = THIS_MODULE;
-	pdata->i2c_adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
-	pdata->i2c_adapter.algo = &i2cp_algorithm;
-	pdata->i2c_adapter.algo_data = pdata;
-	pdata->i2c_adapter.timeout = msecs_to_jiffies(i2cp_default_timeout_ms);
-	pdata->i2c_adapter.dev.parent = &this_pseudo->device;
-	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u", pdata->id);
-	if (ret < 0)
-		goto fail_after_counters_update;
-
-	/* Return success. */
-	filep->private_data = pdata;
-	return 0;
-
- fail_after_counters_update:
-	i2cp_remove_from_counters(pdata, this_pseudo);
- fail_after_cmd_data_created:
-	for (i = 0; i < num_cmd_data_created; ++i)
-		if (i2cp_cmds[i].data_destroyer)
-			i2cp_cmds[i].data_destroyer(pdata->cmd_data[i]);
-	kfree(pdata);
-	return ret;
-}
-
-static int i2cp_cdev_release(struct inode *inodep, struct file *filep)
-{
-	int i;
-	bool adapter_was_added = false;
-	struct i2cp_controller *pdata;
-	struct i2cp_device *this_pseudo;
-
-	pdata = filep->private_data;
-	this_pseudo = container_of(pdata->i2c_adapter.dev.parent,
-		struct i2cp_device, device);
-
-	/*
-	 * The select(2) man page makes it clear that the behavior of pending
-	 * select()/poll()/epoll_wait() on a fd that gets closed while waiting
-	 * is undefined and should never be relied on.  However since we are
-	 * about to free pdata and therefore free pdata->poll_wait_queue, safest
-	 * to wake up anyone waiting on it in an attempt to not leave them in a
-	 * completely undefined state.
-	 */
-	wake_up_interruptible_all(&pdata->poll_wait_queue);
-	/*
-	 * Linux guarantees there are no outstanding reads or writes when a
-	 * struct file is released, so no further synchronization with the other
-	 * struct file_operations callbacks should be needed.
-	 */
-	filep->private_data = NULL;
-
-	mutex_lock(&pdata->startstop_lock);
-	if (pdata->startstop_state != I2CP_CTRLR_STATE_NEW) {
-		/*
-		 * Defer deleting the adapter until after releasing
-		 * pdata->startstop_state.  This avoids deadlocking with any
-		 * overlapping i2cp_adapter_master_xfer() calls, which also
-		 * acquire the lock in order to check the state.
-		 */
-		adapter_was_added = true;
-		/*
-		 * Instruct any overlapping i2cp_adapter_master_xfer() calls to
-		 * return immediately.
-		 */
-		pdata->startstop_state = I2CP_CTRLR_STATE_SHUTDN_REQ;
-	}
-	mutex_unlock(&pdata->startstop_lock);
-
-	/*
-	 * Wake up blocked I2C requests.  This is an optimization so that they
-	 * don't need to wait for the I2C adapter timeout, since there is no
-	 * possibility of any further I2C replies.
-	 */
-	for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i)
-		if (i2cp_cmds[i].data_shutdown)
-			i2cp_cmds[i].data_shutdown(pdata->cmd_data[i]);
-
-	if (adapter_was_added)
-		i2c_del_adapter(&pdata->i2c_adapter);
-
-	for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i) {
-		if (i2cp_cmds[i].data_destroyer)
-			i2cp_cmds[i].data_destroyer(pdata->cmd_data[i]);
-		pdata->cmd_data[i] = NULL;
-	}
-
-	i2cp_remove_from_counters(pdata, this_pseudo);
-	kfree(pdata);
-	return 0;
-}
-
-/* The caller must hold pdata->rsp_lock. */
-/* Return value is whether or not to continue in calling loop. */
-static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
-	ssize_t *ret, bool non_blocking, struct i2cp_controller *pdata)
-{
-	long wait_ret;
-	ssize_t copy_size;
-	unsigned long copy_ret;
-	struct i2cp_rsp *rsp_wrapper = NULL;
-
-	/*
-	 * If a previous read response buffer has been exhausted, free
-	 * it.
-	 *
-	 * This is done at the beginning of the while(count>0) loop
-	 * because...?
-	 */
-	if (pdata->rsp_buf_start && !pdata->rsp_buf_remaining) {
-		kfree(pdata->rsp_buf_start);
-		pdata->rsp_buf_start = NULL;
-		pdata->rsp_buf_pos = NULL;
-	}
-
-	/*
-	 * If we have no formatter callback output queued (neither
-	 * successful output nor error), go through the FIFO queue of
-	 * read responses until a formatter returns non-zero (successful
-	 * output or failure).
-	 */
-	while (pdata->rsp_buf_remaining == 0) {
-		/*
-		 * If pdata->rsp_invalidated is true, it means the
-		 * previous read() returned an error.  Now that the
-		 * error has already been propagated to userspace, we
-		 * can write the end character for the invalidated read
-		 * response.
-		 */
-		if (pdata->rsp_invalidated) {
-			pdata->rsp_invalidated = false;
-			goto write_end_char;
-		}
-
-		/* If we have already read some bytes successfully, even
-		 * if less than requested, we should return as much as
-		 * we can without blocking further.  Same if we have an
-		 * error to return.
-		 */
-		if (non_blocking || *ret != 0) {
-			if (!try_wait_for_completion(&pdata->read_rsp_queued)) {
-				if (*ret == 0)
-					*ret = -EAGAIN;
-				/*
-				 * If we are out of read responses,
-				 * return whatever we have written to
-				 * the userspace buffer so far, even if
-				 * it's nothing.
-				 */
-				return false;
-			}
-		} else {
-			wait_ret = wait_for_completion_killable(
-				&pdata->read_rsp_queued);
-			if (wait_ret == -ERESTARTSYS) {
-				if (*ret == 0)
-					*ret = -EINTR;
-				return false;
-			} else if (wait_ret < 0) {
-				if (*ret == 0)
-					*ret = wait_ret;
-				return false;
-			}
-		}
-
-		mutex_lock(&pdata->read_rsp_queue_lock);
-		if (!list_empty(&pdata->read_rsp_queue_head))
-			rsp_wrapper = list_first_entry(
-				&pdata->read_rsp_queue_head,
-				struct i2cp_rsp, queue);
-		/*
-		 * Avoid holding pdata->read_rsp_queue_lock while
-		 * executing a formatter, allocating memory, or doing
-		 * anything else that might block or take non-trivial
-		 * time.  This avoids blocking the enqueuing of new read
-		 * responses for any significant time, even during large
-		 * controller reads.
-		 */
-		mutex_unlock(&pdata->read_rsp_queue_lock);
-
-		if (!rsp_wrapper) {
-			/* This should only happen if shutdown was requested. */
-			if (i2cp_adap_get_state(pdata) !=
-			    I2CP_CTRLR_STATE_SHUTDN_REQ)
-				*ret = -EINVAL;
-			return false;
-		}
-
-		pdata->rsp_buf_remaining = rsp_wrapper->formatter(
-			rsp_wrapper->data, &pdata->rsp_buf_start);
-
-		if (pdata->rsp_buf_remaining > 0) {
-			pdata->rsp_buf_pos = pdata->rsp_buf_start;
-			/*
-			 * We consumed a completion for this rsp_wrapper
-			 * but we are leaving it in
-			 * pdata->read_rsp_queue_head.  Re-add a
-			 * completion for it.
-			 *
-			 * Since overlapping reads are effectively
-			 * serialized via use of pdata->rsp_lock, we
-			 * could take shortcuts in how
-			 * pdata->read_rsp_queued is used to avoid the
-			 * need for re-incrementing it here.  However by
-			 * maintaining the invariant of consuming a
-			 * completion each time an item from
-			 * pdata->read_rsp_queue_head is consumed
-			 * (whether or not it ends up being removed from
-			 * the queue in that iteration), the completion
-			 * logic is simpler to follow, and more easily
-			 * lends itself to a future refactor of this
-			 * read operation to not hold pdata->rsp_lock
-			 * continuously.
-			 */
-			complete(&pdata->read_rsp_queued);
-			break;
-		}
-
-		/*
-		 * The formatter should not mutate pdata->rsp_buf_start
-		 * if it returned non-positive.  Just in case, we handle
-		 * such a bug gracefully here.
-		 */
-		kfree(pdata->rsp_buf_start);
-		pdata->rsp_buf_start = NULL;
-
-		mutex_lock(&pdata->read_rsp_queue_lock);
-		list_del(&rsp_wrapper->queue);
-		--pdata->read_rsp_queue_length;
-		mutex_unlock(&pdata->read_rsp_queue_lock);
-
-		kfree(rsp_wrapper);
-		rsp_wrapper = NULL;
-
-		/* Check if the formatter callback returned an error.
-		 *
-		 * If we have _not_ written any bytes to the userspace
-		 * buffer yet, return now with the error code from the
-		 * formatter.
-		 *
-		 * If we _have_ written bytes already, return now with
-		 * the number of bytes written, and leave the error code
-		 * from the formatter in pdata->rsp_buf_remaining so it
-		 * can be returned on the next read, before any bytes
-		 * are written.
-		 *
-		 * In either case, we deliberately return the error
-		 * before writing the end character for the invalidated
-		 * read response, so that the userspace controller knows
-		 * to discard the response.
-		 */
-		if (pdata->rsp_buf_remaining < 0) {
-			if (*ret == 0) {
-				*ret = pdata->rsp_buf_remaining;
-				pdata->rsp_buf_remaining = 0;
-			}
-			pdata->rsp_invalidated = true;
-			return false;
-		}
-
- write_end_char:
-		copy_size = sizeof(i2cp_ctrlr_end_char);
-		/*
-		 * This assertion is just in case someone changes
-		 * i2cp_ctrlr_end_char to a string.  Such a change would require
-		 * handling it like a read response buffer, including ensuring
-		 * that we not write more than *count.  So long as it's a single
-		 * character, we can avoid an extra check of *count in this code
-		 * block, we already know it's greater than zero.
-		 */
-		BUILD_BUG_ON(copy_size != 1);
-		copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char,
-			copy_size);
-		copy_size -= copy_ret;
-		/*
-		 * After writing to the userspace buffer, we need to
-		 * update various counters including the return value,
-		 * then continue from the start of the outer while loop
-		 * because it's possible *count has reached zero.
-		 *
-		 * Those exact same steps must be done after copying
-		 * from a read response buffer to the userspace buffer,
-		 * so jump to that code instead of duplicating it.
-		 */
-		goto after_copy_to_user;
-	}
-
-	copy_size = max_t(ssize_t, 0,
-		min_t(ssize_t, *count, pdata->rsp_buf_remaining));
-	copy_ret = copy_to_user(*buf, pdata->rsp_buf_pos, copy_size);
-	copy_size -= copy_ret;
-	pdata->rsp_buf_remaining -= copy_size;
-
-	if (pdata->rsp_buf_remaining > 0) {
-		pdata->rsp_buf_pos += copy_size;
-	} else {
-		kfree(pdata->rsp_buf_start);
-		pdata->rsp_buf_start = NULL;
-		pdata->rsp_buf_pos = NULL;
-	}
-
- /*
-  * When jumping here, the following variables should be set:
-  *   copy_ret: Return value from copy_to_user() (bytes not copied).
-  *   copy_size: The number of bytes successfully copied by copy_to_user().  In
-  *       other words, this should be the size arg to copy_to_user() minus its
-  *       return value (bytes not copied).
-  */
- after_copy_to_user:
-	*ret += copy_size;
-	*count -= copy_size;
-	*buf += copy_size;
-
-	return !copy_ret;
-}
-
-static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf,
-		size_t count, loff_t *f_ps)
-{
-	ssize_t ret = 0;
-	bool non_blocking;
-	struct i2cp_controller *pdata;
-
-	/*
-	 * Just in case this could change out from under us, best to keep a
-	 * consistent view for the duration of this syscall.
-	 */
-	non_blocking = !!(filep->f_flags & O_NONBLOCK);
-	pdata = filep->private_data;
-
-	if (count > (size_t)I2CP_RW_SIZE_LIMIT)
-		count = I2CP_RW_SIZE_LIMIT;
-
-	/*
-	 * Since read() calls are effectively serialized by way of
-	 * pdata->rsp_lock, we MUST NOT block on obtaining that lock if in
-	 * non-blocking mode, because it might be held by a blocking read().
-	 */
-	if (!non_blocking)
-		mutex_lock(&pdata->rsp_lock);
-	else if (!mutex_trylock(&pdata->rsp_lock))
-		return -EAGAIN;
-
-	/*
-	 * Check if a formatter callback returned an error that hasn't yet been
-	 * returned to the controller.  Do this before the while(count>0) loop
-	 * because read(2) with zero count is allowed to report errors.
-	 */
-	if (pdata->rsp_buf_remaining < 0) {
-		BUILD_BUG_ON(ret != 0);
-		ret = pdata->rsp_buf_remaining;
-		pdata->rsp_buf_remaining = 0;
-		goto unlock;
-	}
-
-	while (count > 0 && i2cp_cdev_read_iteration(
-		&buf, &count, &ret, non_blocking, pdata))
-		;
-
- unlock:
-	mutex_unlock(&pdata->rsp_lock);
-	return ret;
-}
-
-/* Must be called with pdata->cmd_lock held. */
-/* Must never consume past first i2cp_ctrlr_end_char in @start. */
-static ssize_t i2cp_receive_ctrlr_cmd_header(
-	struct i2cp_controller *pdata, char *start, size_t remaining,
-	bool non_blocking)
-{
-	int found_deliminator_char = 0;
-	int i, cmd_idx;
-	ssize_t copy_size, ret = 0, stop, buf_remaining;
-
-	buf_remaining = I2CP_CTRLR_CMD_LIMIT - pdata->cmd_size;
-	stop = min_t(ssize_t, remaining, buf_remaining + 1);
-
-	for (i = 0; i < stop; ++i)
-		if (start[i] == i2cp_ctrlr_end_char ||
-		    start[i] == i2cp_ctrlr_header_sep_char) {
-			found_deliminator_char = 1;
-			break;
-	}
-
-	if (i <= buf_remaining) {
-		copy_size = i;
-	} else {
-		copy_size = buf_remaining;
-		if (!pdata->cmd_receive_status)
-			/*
-			 * Exceeded max size of I2C pseudo controller command
-			 * buffer.  The command currently being written will be
-			 * ignored.
-			 *
-			 * Positive error number is deliberate here.
-			 */
-			pdata->cmd_receive_status = ENOBUFS;
-	}
-
-	memcpy(&pdata->cmd_buf[pdata->cmd_size], start, copy_size);
-	pdata->cmd_size += copy_size;
-
-	if (!found_deliminator_char || pdata->cmd_size <= 0)
-		return copy_size + found_deliminator_char;
-
-	/* This may be negative. */
-	cmd_idx = pdata->cmd_idx_plus_one - 1;
-
-	if (cmd_idx < 0) {
-		for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i)
-			if (i2cp_cmds[i].cmd_size == pdata->cmd_size &&
-			    !memcmp(i2cp_cmds[i].cmd_string, pdata->cmd_buf,
-					pdata->cmd_size))
-				break;
-		if (i >= ARRAY_SIZE(i2cp_cmds)) {
-			/* unrecognized command */
-			ret = -EIO;
-			goto clear_buffer;
-		}
-		cmd_idx = i;
-		pdata->cmd_idx_plus_one = cmd_idx + 1;
-	}
-
-	/*
-	 * If we have write bytes queued and we encountered i2cp_ctrlr_end_char
-	 * or i2cp_ctrlr_header_sep_char, invoke the header_receiver callback.
-	 */
-	if (!pdata->cmd_receive_status) {
-		ret = i2cp_cmds[cmd_idx].header_receiver(
-			pdata->cmd_data[cmd_idx], pdata->cmd_buf,
-			pdata->cmd_size, non_blocking);
-		if (ret > 0) {
-			if (ret > I2CP_CTRLR_CMD_LIMIT) {
-				ret = -EINVAL;
-				goto clear_buffer;
-			}
-			pdata->cmd_data_increment = ret;
-		} else if (ret < 0) {
-			pdata->cmd_receive_status = ret;
-		}
-	}
-
- clear_buffer:
-	pdata->cmd_size = 0;
-	/*
-	 * Ensure a trailing null character for the next header_receiver() or
-	 * data_receiver() invocation.
-	 */
-	memset(pdata->cmd_buf, 0, sizeof(pdata->cmd_buf));
-
-	if (ret < 0) {
-		if (pdata->cmd_idx_plus_one >= 1 && !pdata->cmd_receive_status)
-			/* Negate to get a positive error number. */
-			pdata->cmd_receive_status = -ret;
-		return ret;
-	}
-	return copy_size + found_deliminator_char;
-}
-
-/* Must be called with pdata->cmd_lock held. */
-/* Must never consume past first i2cp_ctrlr_end_char in @start. */
-static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
-	char *start, size_t remaining, bool non_blocking)
-{
-	ssize_t i, ret, size_holder;
-	int cmd_idx;
-
-	/* If cmd_idx ends up negative here, it is a bug. */
-	cmd_idx = pdata->cmd_idx_plus_one - 1;
-	if (cmd_idx < 0)
-		return -EINVAL;
-
-	size_holder = min_t(size_t,
-		(I2CP_CTRLR_CMD_LIMIT -
-		 (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)) -
-		pdata->cmd_size,
-		(((pdata->cmd_size + remaining) /
-		  pdata->cmd_data_increment) *
-		 pdata->cmd_data_increment) - pdata->cmd_size);
-
-	/* Size of current buffer plus all remaining write bytes. */
-	size_holder = pdata->cmd_size + remaining;
-	/*
-	 * Avoid rounding down to zero.  If there are insufficient write
-	 * bytes remaining to grow the buffer to 1x of the requested
-	 * data byte increment, we'll copy what is available to the
-	 * buffer, and just leave it queued without any further command
-	 * handler invocations in this write() (unless i2cp_ctrlr_end_char is
-	 * found, in which case we will always invoke the data_receiver for any
-	 * remaining data bytes, and will always invoke the cmd_completer).
-	 */
-	if (size_holder > pdata->cmd_data_increment)
-		/*
-		 * Round down to the nearest multiple of the requested
-		 * data byte increment.
-		 */
-		size_holder -= size_holder % pdata->cmd_data_increment;
-	/*
-	 * Take the smaller of:
-	 *
-	 * [A] 2nd min_t() arg: The number of bytes that we would want the
-	 * buffer to end up with if it had unlimited space (computed
-	 * above).
-	 *
-	 * [B] 3rd min_t() arg: The number of bytes that we would want the
-	 * buffer to end up with if there were unlimited write bytes
-	 * remaining (computed in-line below).
-	 */
-	size_holder = min_t(ssize_t, size_holder, (I2CP_CTRLR_CMD_LIMIT - (
-		I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)));
-	/*
-	 * Subtract the existing buffer size to get the number of bytes we
-	 * actually want to copy from the remaining write bytes in this loop
-	 * iteration, assuming no i2cp_ctrlr_end_char.
-	 */
-	size_holder -= pdata->cmd_size;
-
-	/*
-	 * Look for i2cp_ctrlr_end_char.  If we find it, we will copy up to but
-	 * *not* including its position.
-	 */
-	for (i = 0; i < size_holder; ++i)
-		if (start[i] == i2cp_ctrlr_end_char)
-			break;
-
-	/* Copy from the remaining write bytes to the command buffer. */
-	memcpy(&pdata->cmd_buf[pdata->cmd_size], start, i);
-	pdata->cmd_size += i;
-
-	/*
-	 * If we have write bytes queued and *either* we encountered
-	 * i2cp_ctrlr_end_char *or* we have a multiple of
-	 * pdata->cmd_data_increment, invoke the data_receiver callback.
-	 */
-	if (pdata->cmd_size > 0 &&
-	    (i < size_holder ||
-	     pdata->cmd_size % pdata->cmd_data_increment == 0)) {
-		if (!pdata->cmd_receive_status) {
-			ret = i2cp_cmds[cmd_idx].data_receiver(
-				pdata->cmd_data[cmd_idx], pdata->cmd_buf,
-				pdata->cmd_size, non_blocking);
-			if (ret < 0)
-				pdata->cmd_receive_status = ret;
-		}
-		pdata->cmd_size = 0;
-		/*
-		 * Ensure a trailing null character for the next
-		 * header_receiver() or data_receiver() invocation.
-		 */
-		memset(pdata->cmd_buf, 0, sizeof(pdata->cmd_buf));
-	}
-
-	/* If i2cp_ctrlr_end_char was found, skip past it. */
-	if (i < size_holder)
-		++i;
-	return i;
-}
-
-/* Must be called with pdata->cmd_lock held. */
-static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
-	bool non_blocking)
-{
-	int ret = 0, cmd_idx;
-
-	/* This may be negative. */
-	cmd_idx = pdata->cmd_idx_plus_one - 1;
-
-	if (cmd_idx >= 0 && i2cp_cmds[cmd_idx].cmd_completer) {
-		ret = i2cp_cmds[cmd_idx].cmd_completer(pdata->cmd_data[cmd_idx],
-			pdata, pdata->cmd_receive_status, non_blocking);
-		if (ret > 0)
-			ret = 0;
-	}
-
-	pdata->cmd_idx_plus_one = 0;
-	pdata->cmd_receive_status = 0;
-	pdata->cmd_data_increment = 0;
-
-	pdata->cmd_size = 0;
-	/*
-	 * Ensure a trailing null character for the next header_receiver() or
-	 * data_receiver() invocation.
-	 */
-	memset(pdata->cmd_buf, 0, sizeof(pdata->cmd_buf));
-
-	return ret;
-}
-
-static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
-		size_t count, loff_t *f_ps)
-{
-	ssize_t ret = 0;
-	bool non_blocking;
-	size_t remaining;
-	char *kbuf, *start;
-	struct i2cp_controller *pdata;
-
-	/*
-	 * Just in case this could change out from under us, best to keep a
-	 * consistent view for the duration of this syscall.
-	 *
-	 * Write command implementations, i.e. struct i2cp_cmd implementations,
-	 * do NOT have to support blocking writes.  For example, if a write of
-	 * an I2C message reply is received for a message that the pseudo
-	 * adapter never requested or expected, it makes more sense to indicate
-	 * an error than to block until possibly receiving a master_xfer request
-	 * for that I2C message, even if blocking is permitted.
-	 *
-	 * Furthermore, controller writes MUST NEVER block indefinitely, even
-	 * when non_blocking is false.  E.g. while non_blocking may be used to
-	 * select between mutex_trylock and mutex_lock*, even in the
-	 * latter case the lock should never be blocked on I/O, on userspace, or
-	 * on anything else outside the control of this driver.  It IS
-	 * permissable for the lock to be blocked on processing of previous or
-	 * concurrent write input, so long as that processing does not violate
-	 * these rules.
-	 */
-	non_blocking = !!(filep->f_flags & O_NONBLOCK);
-	pdata = filep->private_data;
-
-	if (count > (size_t)I2CP_RW_SIZE_LIMIT)
-		count = I2CP_RW_SIZE_LIMIT;
-
-	kbuf = kzalloc(count, GFP_KERNEL);
-	if (!kbuf) {
-		ret = -ENOMEM;
-		goto free_kbuf;
-	}
-	if (copy_from_user(kbuf, buf, count)) {
-		ret = -EFAULT;
-		goto free_kbuf;
-	}
-
-	start = kbuf;
-	remaining = count;
-
-	/*
-	 * Since write() calls are effectively serialized by way of
-	 * pdata->cmd_lock, we MUST NOT block on obtaining that lock if in
-	 * non-blocking mode, because it might be held by a blocking write().
-	 */
-	if (!non_blocking) {
-		mutex_lock(&pdata->cmd_lock);
-	} else if (!mutex_trylock(&pdata->cmd_lock)) {
-		ret = -EAGAIN;
-		goto free_kbuf;
-	}
-
-	while (remaining) {
-		if (pdata->cmd_data_increment <= 0)
-			ret = i2cp_receive_ctrlr_cmd_header(
-				pdata, start, remaining, non_blocking);
-		else
-			ret = i2cp_receive_ctrlr_cmd_data(
-				pdata, start, remaining, non_blocking);
-		if (ret < 0)
-			break;
-		if (ret == 0 || ret > remaining) {
-			ret = -EINVAL;
-			break;
-		}
-
-		remaining -= ret;
-		start += ret;
-
-		if (ret > 0 && start[-1] == i2cp_ctrlr_end_char) {
-			ret = i2cp_receive_ctrlr_cmd_complete(
-				pdata, non_blocking);
-			if (ret < 0)
-				break;
-		}
-	}
-
-	mutex_unlock(&pdata->cmd_lock);
-	wake_up_interruptible_sync(&pdata->poll_wait_queue);
-
-	if (ret >= 0)
-		/* If successful the whole write is always consumed. */
-		ret = count;
-
- free_kbuf:
-	kfree(kbuf);
-	return ret;
-}
-
-/*
- * The select/poll/epoll implementation in this module is designed around these
- * controller behavior assumptions:
- *
- * - If any reader of a given controller makes use of polling, all will.
- *
- * - Upon notification of available data to read, a reader will fully consume it
- *   in a read() loop until receiving EAGAIN, EWOULDBLOCK, or EOF.
- *
- * - Only one reader need be woken upon newly available data, however it is okay
- *   if more than one are sometimes woken.
- *
- * - If more than one reader is woken, or otherwise acts in parallel, it is the
- *   responsibility of the readers to either ensure that only one at a time
- *   consumes all input until EAGAIN/EWOULDBLOCK, or that they properly
- *   recombine any data that was split among them.
- *
- * - All of the above applies to writers as well.
- *
- * Notes:
- *
- * - If a reader does not read all available data until EAGAIN/EWOULDBLOCK after
- *   being woken from poll, there may be no wake event for the remaining
- *   available data, causing it to remain unread until further data becomes
- *   available and triggers another wake event.  The same applies to writers -
- *   they are only guaranteed to be woken /once/ per blocked->unblocked
- *   transition, so after being woken they should continue writing until either
- *   the controller is out of data or EAGAIN/EWOULDBLOCK is encountered.
- *
- * - It is strongly suggested that controller implementations have only one
- *   reader (thread) and one writer (thread), which may or may not be the same
- *   thread.  After all only one message can be active on an I2C bus at a time,
- *   and this driver implementation reflects that.  Avoiding multiple readers
- *   and multiple writers greatly simplifies controller implementation, and
- *   there is likely nothing to be gained from performing any of their work in
- *   parallel.
- *
- * - Implementation detail: Reads are effectively serialized by a per controller
- *   read lock.  From the perspective of other readers, the controller device
- *   will appear blocked, with appropriate behavior based on the O_NONBLOCK bit.
- *   THIS IS SUBJECT TO CHANGE!
- *
- * - Implementation detail: Writes are effectively serialized by a per
- *   controller write lock.  From the perspective of other writers, the
- *   controller device will appear blocked, with appropriate behavior based on
- *   the O_NONBLOCK bit.  THIS IS SUBJECT TO CHANGE!
- *
- * - Implementation detail: In the initial implementation, the only scenario
- *   where a controller will appear blocked for writes is if another write is in
- *   progress.  Thus, a single writer should never see the device blocked.  THIS
- *   IS SUBJECT TO CHANGE!  When using O_NONBLOCK, a controller should correctly
- *   handle EAGAIN/EWOULDBLOCK even if it has only one writer.
- */
-static __poll_t i2cp_cdev_poll(struct file *filep, poll_table *ptp)
-{
-	__poll_t poll_ret = 0;
-	struct i2cp_controller *pdata;
-
-	pdata = filep->private_data;
-
-	poll_wait(filep, &pdata->poll_wait_queue, ptp);
-
-	if (mutex_trylock(&pdata->rsp_lock)) {
-		if (i2cp_poll_in(pdata))
-			poll_ret |= POLLIN | POLLRDNORM;
-		mutex_unlock(&pdata->rsp_lock);
-	}
-
-	if (!mutex_is_locked(&pdata->cmd_lock))
-		poll_ret |= POLLOUT | POLLWRNORM;
-
-	if (i2cp_adap_get_state(pdata) == I2CP_CTRLR_STATE_SHUTDN_REQ)
-		poll_ret |= POLLHUP;
-
-	return poll_ret;
-}
-
-static const struct file_operations i2cp_fileops = {
-	.owner = THIS_MODULE,
-	.open = i2cp_cdev_open,
-	.release = i2cp_cdev_release,
-	.read = i2cp_cdev_read,
-	.write = i2cp_cdev_write,
-	.poll = i2cp_cdev_poll,
-	.llseek = no_llseek,
-};
-
-static ssize_t i2cp_limit_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	int ret;
-
-	ret = snprintf(buf, PAGE_SIZE, "%u\n", i2cp_limit);
-	if (ret >= PAGE_SIZE)
-		return -ERANGE;
-	return ret;
-}
-
-static struct device_attribute i2cp_limit_dev_attr = {
-	.attr = {
-		.name = "limit",
-		.mode = 0444,
-	},
-	.show = i2cp_limit_show,
-};
-
-static ssize_t i2cp_count_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	int count, ret;
-	struct i2cp_device *this_pseudo;
-
-	this_pseudo = container_of(dev, struct i2cp_device, device);
-
-	mutex_lock(&this_pseudo->counters.lock);
-	count = this_pseudo->counters.count;
-	mutex_unlock(&this_pseudo->counters.lock);
-
-	ret = snprintf(buf, PAGE_SIZE, "%u\n", count);
-	if (ret >= PAGE_SIZE)
-		return -ERANGE;
-	return ret;
-}
-
-static struct device_attribute i2cp_count_dev_attr = {
-	.attr = {
-		.name = "count",
-		.mode = 0444,
-	},
-	.show = i2cp_count_show,
-};
-
-static struct attribute *i2cp_device_sysfs_attrs[] = {
-	&i2cp_limit_dev_attr.attr,
-	&i2cp_count_dev_attr.attr,
-	NULL,
-};
-
-static const struct attribute_group i2cp_device_sysfs_group = {
-	.attrs = i2cp_device_sysfs_attrs,
-};
-
-static const struct attribute_group *i2cp_device_sysfs_groups[] = {
-	&i2cp_device_sysfs_group,
-	NULL,
-};
-
-static void i2c_p_device_release(struct device *dev)
-{
-	struct i2cp_device *this_pseudo;
-
-	this_pseudo = container_of(dev, struct i2cp_device, device);
-	kfree(this_pseudo->counters.all_controllers);
-	kfree(this_pseudo);
-}
-
-static inline void i2c_p_class_destroy(void)
-{
-	struct class *class;
-
-	class = i2cp_class;
-	i2cp_class = NULL;
-	class_destroy(class);
-}
-
-static int __init i2cp_init(void)
-{
-	int ret = -1;
-
-	if (i2cp_limit < I2CP_ADAPTERS_MIN || i2cp_limit > I2CP_ADAPTERS_MAX) {
-		pr_err("%s: i2cp_limit=%u, must be in range ["
-			STR(I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX)
-			"]\n", __func__, i2cp_limit);
-		return -EINVAL;
-	}
-
-	i2cp_class = class_create(THIS_MODULE, I2CP_CLASS_NAME);
-	if (IS_ERR(i2cp_class))
-		return PTR_ERR(i2cp_class);
-
-	i2cp_class->dev_groups = i2cp_device_sysfs_groups;
-
-	ret = alloc_chrdev_region(&i2cp_dev_num, I2CP_CDEV_BASEMINOR,
-		I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME);
-	if (ret < 0)
-		goto fail_after_class_create;
-
-	i2cp_device = kzalloc(sizeof(*i2cp_device), GFP_KERNEL);
-	if (!i2cp_device) {
-		ret = -ENOMEM;
-		goto fail_after_chrdev_register;
-	}
-
-	i2cp_device->device.devt = i2cp_dev_num;
-	i2cp_device->device.class = i2cp_class;
-	i2cp_device->device.release = i2c_p_device_release;
-	device_initialize(&i2cp_device->device);
-
-	ret = dev_set_name(&i2cp_device->device, "%s", I2CP_DEVICE_NAME);
-	if (ret < 0)
-		goto fail_after_device_init;
-
-	mutex_init(&i2cp_device->counters.lock);
-	i2cp_device->counters.all_controllers = kcalloc(i2cp_limit,
-		sizeof(*i2cp_device->counters.all_controllers), GFP_KERNEL);
-	if (!i2cp_device->counters.all_controllers) {
-		ret = -ENOMEM;
-		goto fail_after_device_init;
-	}
-
-	cdev_init(&i2cp_device->cdev, &i2cp_fileops);
-	i2cp_device->cdev.owner = THIS_MODULE;
-
-	ret = cdev_device_add(&i2cp_device->cdev, &i2cp_device->device);
-	if (ret < 0)
-		goto fail_after_device_init;
-
-	return 0;
-
- fail_after_device_init:
-	put_device(&i2cp_device->device);
- fail_after_chrdev_register:
-	unregister_chrdev_region(i2cp_dev_num, I2CP_CDEV_COUNT);
- fail_after_class_create:
-	i2c_p_class_destroy();
-	return ret;
-}
-
-static void __exit i2cp_exit(void)
-{
-	cdev_device_del(&i2cp_device->cdev, &i2cp_device->device);
-	put_device(&i2cp_device->device);
-	unregister_chrdev_region(i2cp_dev_num, I2CP_CDEV_COUNT);
-	i2c_p_class_destroy();
-}
-
-MODULE_AUTHOR("Matthew Blecker <matthewb@ihavethememo.net");
-MODULE_DESCRIPTION("Driver for userspace I2C adapter implementations.");
-MODULE_LICENSE("GPL");
-
-module_init(i2cp_init);
-module_exit(i2cp_exit);
diff --git a/extra/i2c_pseudo/install b/extra/i2c_pseudo/install
deleted file mode 100755
index e66dcbd719..0000000000
--- a/extra/i2c_pseudo/install
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/sh
-#
-# This attempts to build and install the i2c-pseudo Linux kernel module.
-# Installs a udev rule making i2c-pseudo devices read-write by users in plugdev.
-
-set -e
-cd "$(dirname "$0")"
-
-make clean
-make
-ret=0
-sudo make modules_install || ret="$?"
-
-# Only install udev rule if plugdev group exists.
-if getent group plugdev > /dev/null; then
-  sudo cp -iv 50-i2c-pseudo.rules /etc/udev/rules.d/ \
-    || echo 1>&2 "NOTICE: Failed to copy udev rules file."
-fi
-
-if [ "$ret" -eq 0 ]; then
-  make clean
-  sudo depmod -a
-  sudo modprobe i2c-pseudo
-  echo "SUCCESS: installed and loaded i2c-pseudo module"
-else
-  echo 1>&2 "WARNING: make modules_install failed with exit status $ret."
-  echo 1>&2 "The module has not been installed for future reuse."
-  echo 1>&2 "Will still attempt to load the module, using insmod instead of "\
-"modprobe."
-  ret=0
-  sudo insmod i2c-pseudo.ko || ret="$?"
-  if [ "$ret" -ne 0 ]; then
-    make clean
-    exit "$ret"
-  fi
-  echo "PARTIAL SUCCESS: loaded i2c-pseudo module (not installed)"
-  make clean
-fi
diff --git a/extra/lightbar/.gitignore b/extra/lightbar/.gitignore
deleted file mode 100644
index 964154302a..0000000000
--- a/extra/lightbar/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-lightbar
diff --git a/extra/lightbar/Makefile b/extra/lightbar/Makefile
deleted file mode 100644
index ce84428869..0000000000
--- a/extra/lightbar/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-PROG= lightbar
-HEADERS= simulation.h
-SRCS= main.c windows.c input.c ../../common/lightbar.c
-
-# comment this out if you don't have libreadline installed
-HAS_GNU_READLINE=1
-
-INCLUDE= -I. -I../../include
-CFLAGS= -g -Wall -Werror -pthread ${INCLUDE} -DLIGHTBAR_SIMULATION
-LDFLAGS = -lX11 -lxcb -lrt
-
-ifneq ($(HAS_GNU_READLINE),)
-CFLAGS += -DHAS_GNU_READLINE
-LDFLAGS += -lreadline
-endif
-
-all: ${PROG}
-
-${PROG} : ${SRCS} ${HEADERS} Makefile
-	gcc ${CFLAGS} ${SRCS} ${LDFLAGS} -o ${PROG}
-
-.PHONY: clean
-clean:
-	rm -f ${PROG}
diff --git a/extra/lightbar/README b/extra/lightbar/README
deleted file mode 100644
index 1862f922e4..0000000000
--- a/extra/lightbar/README
+++ /dev/null
@@ -1,39 +0,0 @@
-Lightbar simulator
-------------------------------------------------------------------------------
-
-Build with "make lightbar". The executable is "./lightbar".
-
-You may need to install libxcb1-dev or similar.
-
-This provides a simulation environment for the lightbar task, compiling
-common/lightbar.c from the EC source, but faking the rest of the EC.
-
-The EC console is on stdin/stdout, delivering all input to the lightbar's
-console command handler (so it prefixes any input with "lightbar"). The
-lightbar itself is displayed in an X window. You can click in that window to
-emulate changes to the battery level, AC connection, and brightness, all of
-which are normally outside the lightbar task's direct control.
-
-The initial sequence is "S5". Try issuing the command "seq s3s0" to see
-something more familiar.
-
-
-Note: the Pixel lightbar circuitry has three modes of operation:
-
-Unpowered
-
-  When the host CPU is off (S5/G3), all power to the lightbar and its
-  controller circuitry is lost.
-
-On
-
-  When the host CPU is on (S0) or suspended (S3), the lightbar is powered
-  again. After every power loss, it will need to be reinitialized by calling
-  lb_init() before it can be used.
-
-Standby
-
-  The lightbar controller ICs can turn off all the LED outputs to conserve
-  power. This is the initial state when power is applied. You can turn the
-  LEDs off manually by calling lb_off(). When suspended, the controller will
-  respond to commands, but the LEDs aren't lit. Turn them on with lb_on().
diff --git a/extra/lightbar/input.c b/extra/lightbar/input.c
deleted file mode 100644
index e6c5485e39..0000000000
--- a/extra/lightbar/input.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-
-#include "simulation.h"
-
-#ifdef HAS_GNU_READLINE
-#include <readline/readline.h>
-#include <readline/history.h>
-
-char *get_input(const char *prompt)
-{
-	static char *line;
-
-	if (line) {
-		free(line);
-		line = 0;
-	}
-
-	line = readline(prompt);
-
-	if (line && *line)
-		add_history(line);
-
-	return line;
-}
-
-#else  /* no readline */
-
-char *get_input(const char *prompt)
-{
-	static char mybuf[80];
-	char *got;
-	printf("%s", prompt);
-	got = fgets(mybuf, sizeof(mybuf), stdin);
-	return got;
-}
-
-#endif /* HAS_GNU_READLINE */
-
-void *entry_input(void *ptr)
-{
-	char *got, buf[80];
-	char *str, *word, *saveptr;
-	int argc;
-	char *argv[40];
-	int ret;
-
-	do {
-		got = get_input("lightbar% ");
-		if (got) {
-			strcpy(buf, got);
-			argc = 0;
-			argv[argc++] = "lightbar";
-			word = str = buf;
-			while (word && argc < ARRAY_SIZE(argv)) {
-				word = strtok_r(str, " \t\r\n", &saveptr);
-				if (word)
-					argv[argc++] = word;
-				str = 0;
-			}
-			argv[argc] = 0;
-			ret = fake_consolecmd_lightbar(argc, argv);
-			if (ret)
-				printf("ERROR %d\n", ret);
-		}
-
-	} while (got);
-
-	exit(0);
-
-	return 0;
-}
diff --git a/extra/lightbar/main.c b/extra/lightbar/main.c
deleted file mode 100644
index 5acf3d427a..0000000000
--- a/extra/lightbar/main.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <assert.h>
-#include <errno.h>
-#include <inttypes.h>
-#include <pthread.h>
-#include <stdint.h>
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <time.h>
-
-#include "simulation.h"
-
-static void *(*thread_fns[])(void *) = {
-	entry_windows,
-	entry_lightbar,
-	entry_input,
-};
-
-int main(int argc, char *argv[])
-{
-	int i;
-	pthread_t thread[ARRAY_SIZE(thread_fns)];
-
-	printf("\nLook at the README file.\n");
-	printf("Click in the window.\n");
-	printf("Type \"help\" for commands.\n\n");
-	fflush(stdout);
-
-	init_windows();
-
-	for (i = 0; i < ARRAY_SIZE(thread_fns); i++)
-		assert(0 == pthread_create(&thread[i], NULL, thread_fns[i], 0));
-
-	for (i = 0; i < ARRAY_SIZE(thread_fns); i++)
-		pthread_join(thread[i], NULL);
-
-	return 0;
-}
-
-void *entry_lightbar(void *ptr)
-{
-	lightbar_task();
-	return 0;
-}
-
-/****************************************************************************/
-/* Fake functions. We only have to implement enough for lightbar.c */
-
-/* timespec uses nanoseconds */
-#define TS_USEC 1000L
-#define TS_MSEC 1000000L
-#define TS_SEC  1000000000L
-
-static void timespec_incr(struct timespec *v, time_t secs, long nsecs)
-{
-	v->tv_sec += secs;
-	/* The nanosecond sum won't overflow, but might have a carry. */
-	v->tv_nsec += nsecs;
-	v->tv_sec += v->tv_nsec / TS_SEC;
-	v->tv_nsec %= TS_SEC;
-}
-
-
-static pthread_mutex_t task_mutex = PTHREAD_MUTEX_INITIALIZER;
-static pthread_cond_t task_cond = PTHREAD_COND_INITIALIZER;
-static uint32_t task_event;
-
-uint32_t task_wait_event(int timeout_us)
-{
-	struct timespec t;
-	uint32_t event;
-
-	pthread_mutex_lock(&task_mutex);
-
-	if (timeout_us > 0) {
-		clock_gettime(CLOCK_REALTIME, &t);
-		timespec_incr(&t, timeout_us / SECOND, timeout_us * TS_USEC);
-
-		if (ETIMEDOUT == pthread_cond_timedwait(&task_cond,
-							&task_mutex, &t))
-			task_event |= TASK_EVENT_TIMER;
-	} else {
-		pthread_cond_wait(&task_cond, &task_mutex);
-	}
-
-	pthread_mutex_unlock(&task_mutex);
-	event = task_event;
-	task_event = 0;
-	return event;
-}
-
-uint32_t task_set_event(task_id_t tskid, /* always LIGHTBAR */
-			uint32_t event)
-{
-	pthread_mutex_lock(&task_mutex);
-	task_event = event;
-	pthread_cond_signal(&task_cond);
-	pthread_mutex_unlock(&task_mutex);
-	return 0;
-}
-
-
-
-/* Stubbed functions */
-
-void cprintf(int zero, const char *fmt, ...)
-{
-	va_list ap;
-	char *s;
-	char *newfmt = strdup(fmt);
-
-	for (s = newfmt; *s; s++)
-		if (*s == '%' && s[1] == 'T')
-			*s = 'T';
-
-	va_start(ap, fmt);
-	vprintf(newfmt, ap);
-	va_end(ap);
-
-	free(newfmt);
-}
-
-void cprints(int zero, const char *fmt, ...)
-{
-	va_list ap;
-
-	printf("[TT ");
-	va_start(ap, fmt);
-	vprintf(fmt, ap);
-	va_end(ap);
-	printf("]\n");
-}
-
-timestamp_t get_time(void)
-{
-	static struct timespec t_start;
-	struct timespec t;
-	timestamp_t ret;
-
-	if (!t_start.tv_sec)
-		clock_gettime(CLOCK_REALTIME, &t_start);
-	clock_gettime(CLOCK_REALTIME, &t);
-	ret.val = (t.tv_sec - t_start.tv_sec) * SECOND +
-		(t.tv_nsec - t_start.tv_nsec) / TS_USEC;
-	return ret;
-}
-
-/* We could implement these if we wanted to test their usage. */
-int system_add_jump_tag(uint16_t tag, int version, int size, const void *data)
-{
-	return 0;
-}
-
-uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
-{
-	return 0;
-}
-
-/* Copied from util/ectool.c */
-int lb_read_params_from_file(const char *filename,
-			     struct lightbar_params_v1 *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-
-	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
-	READ(3);
-	p->tap_idx[0] = val[0];
-	p->tap_idx[1] = val[1];
-	p->tap_idx[2] = val[2];
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-int lb_load_program(const char *filename, struct lightbar_program *prog)
-{
-	FILE *fp;
-	size_t got;
-	int rc;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	rc = fseek(fp, 0, SEEK_END);
-	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
-		fclose(fp);
-		return 1;
-	}
-	rc = (int) ftell(fp);
-	if (rc > EC_LB_PROG_LEN) {
-		fprintf(stderr, "File %s is too long, aborting\n", filename);
-		fclose(fp);
-		return 1;
-	}
-	rewind(fp);
-
-	memset(prog->data, 0, EC_LB_PROG_LEN);
-	got = fread(prog->data, 1, EC_LB_PROG_LEN, fp);
-	if (rc != got)
-		fprintf(stderr, "Warning: did not read entire file\n");
-	prog->size = got;
-	fclose(fp);
-	return 0;
-}
diff --git a/extra/lightbar/programs/bad-decode-32.bin b/extra/lightbar/programs/bad-decode-32.bin
deleted file mode 100644
index 1d5d0c6c75..0000000000
--- a/extra/lightbar/programs/bad-decode-32.bin
+++ /dev/null
@@ -1 +0,0 @@
-UUU
\ No newline at end of file
diff --git a/extra/lightbar/programs/bad-decode-8.bin b/extra/lightbar/programs/bad-decode-8.bin
deleted file mode 100644
index 8352675d67..0000000000
--- a/extra/lightbar/programs/bad-decode-8.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/bad-jump.bin b/extra/lightbar/programs/bad-jump.bin
deleted file mode 100644
index b2c29a0bbf..0000000000
--- a/extra/lightbar/programs/bad-jump.bin
+++ /dev/null
@@ -1 +0,0 @@
-?
\ No newline at end of file
diff --git a/extra/lightbar/programs/bad-opcode.bin b/extra/lightbar/programs/bad-opcode.bin
deleted file mode 100644
index 6b10f95843..0000000000
--- a/extra/lightbar/programs/bad-opcode.bin
+++ /dev/null
@@ -1 +0,0 @@
-Ã
\ No newline at end of file
diff --git a/extra/lightbar/programs/green-pulse.bin b/extra/lightbar/programs/green-pulse.bin
deleted file mode 100644
index 0fdab712e9..0000000000
--- a/extra/lightbar/programs/green-pulse.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/green-pulse.lbs b/extra/lightbar/programs/green-pulse.lbs
deleted file mode 100644
index bccf3e5c9a..0000000000
--- a/extra/lightbar/programs/green-pulse.lbs
+++ /dev/null
@@ -1,8 +0,0 @@
-	set.1 {0,1,2,3}.end.g 0xff
-	delay.r 7813
-	delay.w 2000000
-L0001:	on
-	cycle.1
-	off
-	wait
-	jump L0001
diff --git a/extra/lightbar/programs/infinite-jump.bin b/extra/lightbar/programs/infinite-jump.bin
deleted file mode 100644
index 5407bf3ddf..0000000000
--- a/extra/lightbar/programs/infinite-jump.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/infinite-jump.lbs b/extra/lightbar/programs/infinite-jump.lbs
deleted file mode 100644
index 6174d7ffd4..0000000000
--- a/extra/lightbar/programs/infinite-jump.lbs
+++ /dev/null
@@ -1 +0,0 @@
-L0001:	jump L0001
diff --git a/extra/lightbar/programs/konami.bin b/extra/lightbar/programs/konami.bin
deleted file mode 100644
index f7abfdc4ee..0000000000
--- a/extra/lightbar/programs/konami.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/konami.lbs b/extra/lightbar/programs/konami.lbs
deleted file mode 100644
index c9fa8d697a..0000000000
--- a/extra/lightbar/programs/konami.lbs
+++ /dev/null
@@ -1,89 +0,0 @@
-# Konami code easter egg
-	delay.w 100000
-	set.rgb {1,2}.end 0xff 0xff 0x00
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.rgb {1,2}.end 0x00 0x00 0x00
-	set.1 {0,3}.end.b 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.1 {0,3}.end.b 0x00
-	set.1 {0,1}.end.r 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.1 {0,1}.end.r 0x00
-	set.1 {2,3}.end.g 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.1 {2,3}.end.g 0x00
-	set.1 {0,1}.end.r 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.1 {0,1}.end.r 0x00
-	set.1 {2,3}.end.g 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	set.1 {2,3}.end.g 0x00
-	set.rgb {0,2}.end 0x00 0xff 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	delay.w 50000
-	wait
-	set.rgb {0,2}.end 0x00 0x00 0x00
-	set.rgb {1,3}.end 0xff 0x00 0xff
-	ramp.1
-	wait
-	wait
-	cycle.1
-	wait
-	delay.w 100000
-	wait
-	wait
-	set.rgb {0,1,2,3}.end 0xff 0xff 0xff
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	halt
diff --git a/extra/lightbar/programs/rainbow-shift.bin b/extra/lightbar/programs/rainbow-shift.bin
deleted file mode 100644
index a72c5b16d6..0000000000
--- a/extra/lightbar/programs/rainbow-shift.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/rainbow-shift.lbs b/extra/lightbar/programs/rainbow-shift.lbs
deleted file mode 100644
index e1cbcddc83..0000000000
--- a/extra/lightbar/programs/rainbow-shift.lbs
+++ /dev/null
@@ -1,8 +0,0 @@
-# The rainbow cycle program.
-	set.rgb {0,1,2,3}.end 0xff 0xff 0xff
-	set.rgb {0}.phase 0x00 0x55 0xaa
-	set.rgb {1}.phase 0x40 0x95 0xea
-	set.rgb {2}.phase 0x80 0xd5 0x2a
-	set.rgb {3}.phase 0xc0 0x15 0x6a
-	delay.r 7813
-	cycle
diff --git a/extra/lightbar/programs/red-green-blink.bin b/extra/lightbar/programs/red-green-blink.bin
deleted file mode 100644
index 6bece444dd..0000000000
--- a/extra/lightbar/programs/red-green-blink.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/red-green-blink.lbs b/extra/lightbar/programs/red-green-blink.lbs
deleted file mode 100644
index d520b739bb..0000000000
--- a/extra/lightbar/programs/red-green-blink.lbs
+++ /dev/null
@@ -1,14 +0,0 @@
-# Blinks red and green with 1 second pauses.
-	set.rgb {0,1,2,3}.beg 0xff 0x00 0x00
-	set.rgb {0,1,2,3}.end 0x00 0xff 0x00
-	delay.w 250000
-	delay.r 0
-	cycle.1
-	wait
-	ramp.1
-	wait
-	cycle.1
-	wait
-	ramp.1
-	wait
-	halt
diff --git a/extra/lightbar/programs/s0.bin b/extra/lightbar/programs/s0.bin
deleted file mode 100644
index b20cecd8ee..0000000000
--- a/extra/lightbar/programs/s0.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/s0.lbs b/extra/lightbar/programs/s0.lbs
deleted file mode 100644
index 364c3d595c..0000000000
--- a/extra/lightbar/programs/s0.lbs
+++ /dev/null
@@ -1,22 +0,0 @@
-# S0 sequence: Google colors, unless battery is low.
-	set.rgb {0}.end 0x33 0x69 0xe8
-	set.rgb {1}.end 0xd5 0x0f 0x25
-	set.rgb {2}.end 0xee 0xb2 0x11
-	set.rgb {3}.end 0x00 0x99 0x25
-	delay.r 1250
-	ramp.1
-	set.1 {0,1,2,3}.beg.r 0xff
-	delay.r 2500
-	delay.w 1000000
-	wait
-	jump L0003
-L0001:	swap
-	ramp.1
-L0002:	wait
-L0003:	jbat L0004 L0002
-	jump L0002
-L0004:	swap
-	ramp.1
-L0005:	wait
-	jbat L0005 L0001
-	jump L0001
diff --git a/extra/lightbar/programs/s0s3.bin b/extra/lightbar/programs/s0s3.bin
deleted file mode 100644
index d1cb8a4af1..0000000000
--- a/extra/lightbar/programs/s0s3.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/s0s3.lbs b/extra/lightbar/programs/s0s3.lbs
deleted file mode 100644
index ba141f338d..0000000000
--- a/extra/lightbar/programs/s0s3.lbs
+++ /dev/null
@@ -1,16 +0,0 @@
-# S0S3 sequence: Fade out, Google color ramp up/down.
-	get
-	delay.r 2000
-	ramp.1
-	swap
-	set.rgb {0}.end 0x33 0x69 0xe8
-	set.rgb {1}.end 0xd5 0x0f 0x25
-	set.rgb {2}.end 0xee 0xb2 0x11
-	set.rgb {3}.end 0x00 0x99 0x25
-	delay.r 1250
-	ramp.1
-	swap
-	delay.r 10000
-	ramp.1
-	off
-	halt
diff --git a/extra/lightbar/programs/s3.bin b/extra/lightbar/programs/s3.bin
deleted file mode 100644
index 7e487bb8c9..0000000000
--- a/extra/lightbar/programs/s3.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/s3.lbs b/extra/lightbar/programs/s3.lbs
deleted file mode 100644
index e8803a06bb..0000000000
--- a/extra/lightbar/programs/s3.lbs
+++ /dev/null
@@ -1,17 +0,0 @@
-# S3 sequence: Pulse red on low battery.
-	set.rgb {0,1,2,3}.end 0xff 0x00 0x00
-	cycle.1
-	delay.w 5000000
-L0001:	off
-	wait
-	jcharge L0001
-	jbat L0002 L0001
-	jump L0001
-L0002:	on
-	delay.r 1250
-	ramp.1
-	swap
-	delay.r 10000
-	ramp.1
-	swap
-	jump L0001
diff --git a/extra/lightbar/programs/s3s0.bin b/extra/lightbar/programs/s3s0.bin
deleted file mode 100644
index b277752d25..0000000000
--- a/extra/lightbar/programs/s3s0.bin
+++ /dev/null
diff --git a/extra/lightbar/programs/s3s0.lbs b/extra/lightbar/programs/s3s0.lbs
deleted file mode 100644
index 0cac96f208..0000000000
--- a/extra/lightbar/programs/s3s0.lbs
+++ /dev/null
@@ -1,11 +0,0 @@
-# S3S0 sequence: Google color ramp up/down.
-	set.rgb {0}.end 0x33 0x69 0xe8
-	set.rgb {1}.end 0xd5 0x0f 0x25
-	set.rgb {2}.end 0xee 0xb2 0x11
-	set.rgb {3}.end 0x00 0x99 0x25
-	delay.r 1250
-	ramp.1
-	swap
-	delay.r 10000
-	ramp.1
-	halt
diff --git a/extra/lightbar/simulation.h b/extra/lightbar/simulation.h
deleted file mode 100644
index 4df7b69411..0000000000
--- a/extra/lightbar/simulation.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EXTRA_SIMULATION_H
-#define __EXTRA_SIMULATION_H
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "lb_common.h"
-#include "lightbar.h"
-
-/* Functions specific to our simulation environment */
-void *entry_windows(void *);
-void *entry_input(void *);
-void *entry_lightbar(void *);
-void init_windows(void);
-int lb_read_params_from_file(const char *filename,
-			     struct lightbar_params_v1 *p);
-int lb_load_program(const char *filename, struct lightbar_program *prog);
-/* Interfaces to the EC code that we're encapsulating */
-void lightbar_task(void);
-int fake_consolecmd_lightbar(int argc, char *argv[]);
-
-/* EC-specific configuration */
-#undef DEMO_MODE_DEFAULT
-#define DEMO_MODE_DEFAULT 1
-#ifndef CONFIG_CONSOLE_CMDHELP
-#define CONFIG_CONSOLE_CMDHELP
-#endif
-#ifndef CONFIG_LIGHTBAR_POWER_RAILS
-#define CONFIG_LIGHTBAR_POWER_RAILS
-#endif
-
-
-/* Stuff that's too interleaved with the rest of the EC to just include */
-
-/* Test an important condition at compile time, not run time */
-#define _BA1_(cond, line) \
-	extern int __build_assertion_ ## line[1 - 2*!(cond)]	\
-	__attribute__ ((unused))
-#define _BA0_(c, x) _BA1_(c, x)
-#define BUILD_ASSERT(cond) _BA0_(cond, __LINE__)
-
-#define BUILD_CHECK_INLINE(value, cond_true) ((value) / (!!(cond_true)))
-
-/* Number of elements in an array */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-/* Non-standard standard library functions */
-void cprintf(int zero, const char *fmt, ...);
-void cprints(int zero, const char *fmt, ...);
-#define ccprintf(fmt...) cprintf(0, fmt)
-#define strtoi strtol
-
-/* Task events */
-#define TASK_EVENT_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0x0fffffff)
-#define TASK_EVENT_I2C_IDLE      0x10000000
-#define TASK_EVENT_WAKE          0x20000000
-#define TASK_EVENT_MUTEX         0x40000000
-#define TASK_EVENT_TIMER         0x80000000
-
-/* Time units in usecs */
-#define MSEC         1000
-#define SECOND    1000000
-
-#define TASK_ID_LIGHTBAR 0
-#define CC_LIGHTBAR 0
-
-/* Other definitions and structs */
-#define EC_SUCCESS 0
-#define EC_ERROR_INVAL 5
-#define EC_ERROR_PARAM1 11
-#define EC_ERROR_PARAM2 12
-
-typedef int task_id_t;
-
-typedef union {
-	uint64_t val;
-	struct {
-		uint32_t lo;
-		uint32_t hi;
-	} le /* little endian words */;
-} timestamp_t;
-
-struct host_cmd_handler_args {
-	const void *params;
-	void *response;
-	int response_size;
-};
-
-/* EC functions that we have to provide */
-uint32_t task_wait_event(int timeout_us);
-uint32_t task_set_event(task_id_t tskid, uint32_t event);
-timestamp_t get_time(void);
-int system_add_jump_tag(uint16_t tag, int version, int size, const void *data);
-uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size);
-
-/* Export unused static functions to avoid compiler warnings. */
-#define DECLARE_HOOK(X, fn, Y) \
-	void fake_hook_##fn(void) { fn(); }
-
-#define DECLARE_HOST_COMMAND(X, fn, Y) \
-	enum ec_status fake_hostcmd_##fn(struct host_cmd_handler_args *args) \
-	{ return fn(args); }
-
-#define DECLARE_CONSOLE_COMMAND(X, fn, Y...) \
-	int fake_consolecmd_##X(int argc, char *argv[]) \
-	{ return fn(argc, argv); }
-
-#endif	/* __EXTRA_SIMULATION_H */
diff --git a/extra/lightbar/windows.c b/extra/lightbar/windows.c
deleted file mode 100644
index 115074363c..0000000000
--- a/extra/lightbar/windows.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <assert.h>
-#include <pthread.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <xcb/xcb.h>
-
-#include "simulation.h"
-
-/*****************************************************************************/
-/* Window drawing stuff */
-
-/* Dimensions - may change */
-static int win_w = 1024;
-static int win_h = 32;
-
-static xcb_connection_t *c;
-static xcb_screen_t *screen;
-static xcb_drawable_t win;
-static xcb_gcontext_t foreground;
-static xcb_colormap_t colormap_id;
-
-static int fake_power;
-
-void init_windows(void)
-{
-	uint32_t mask = 0;
-	uint32_t values[2];
-
-	/* Open the connection to the X server */
-	c = xcb_connect(NULL, NULL);
-
-	/* Get the first screen */
-	screen = xcb_setup_roots_iterator(xcb_get_setup(c)).data;
-
-	/* Get a colormap */
-	colormap_id = xcb_generate_id(c);
-	xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE,
-			    colormap_id, screen->root, screen->root_visual);
-
-	/* Create foreground GC */
-	foreground = xcb_generate_id(c);
-	mask = XCB_GC_FOREGROUND | XCB_GC_GRAPHICS_EXPOSURES;
-	values[0] = screen->white_pixel;
-	values[1] = 0;
-	xcb_create_gc(c, foreground, screen->root, mask, values);
-
-	/* Create the window */
-	win = xcb_generate_id(c);
-	mask = XCB_CW_BACK_PIXEL | XCB_CW_EVENT_MASK;
-	values[0] = screen->black_pixel;
-	values[1] = XCB_EVENT_MASK_EXPOSURE | XCB_EVENT_MASK_BUTTON_PRESS;
-	xcb_create_window(c,				 /* Connection */
-			  XCB_COPY_FROM_PARENT,		 /* depth */
-			  win,				 /* window Id */
-			  screen->root,			 /* parent window */
-			  0, 0,				 /* x, y */
-			  win_w, win_h,			 /* width, height */
-			  10,				 /* border_width */
-			  XCB_WINDOW_CLASS_INPUT_OUTPUT, /* class */
-			  screen->root_visual,		 /* visual */
-			  mask, values);		 /* masks */
-
-	/* Map the window on the screen */
-	xcb_map_window(c, win);
-
-	/* We flush the request */
-	xcb_flush(c);
-}
-
-void cleanup(void)
-{
-	xcb_destroy_window(c, win);
-	xcb_free_gc(c, foreground);
-	xcb_free_colormap(c, colormap_id);
-	xcb_disconnect(c);
-}
-
-/*****************************************************************************/
-/* Draw the lightbar elements */
-
-/* xcb likes 16-bit colors */
-uint16_t leds[NUM_LEDS][3] = {
-	{0xffff, 0x0000, 0x0000},
-	{0x0000, 0xffff, 0x0000},
-	{0x0000, 0x0000, 0xffff},
-	{0xffff, 0xffff, 0x0000},
-};
-pthread_mutex_t leds_mutex = PTHREAD_MUTEX_INITIALIZER;
-
-void change_gc_color(uint16_t red, uint16_t green, uint16_t blue)
-{
-	uint32_t mask = 0;
-	uint32_t values[2];
-	xcb_alloc_color_reply_t *reply;
-
-	reply = xcb_alloc_color_reply(c,
-				      xcb_alloc_color(c, colormap_id,
-						      red, green, blue),
-				      NULL);
-	assert(reply);
-
-	mask = XCB_GC_FOREGROUND;
-	values[0] = reply->pixel;
-	xcb_change_gc(c, foreground, mask, values);
-	free(reply);
-}
-
-void update_window(void)
-{
-	xcb_segment_t segments[] = {
-		{0, 0, win_w, win_h},
-		{0, win_h, win_w, 0},
-	};
-	xcb_rectangle_t rect;
-	int w = win_w / NUM_LEDS;
-	int i;
-	uint16_t copyleds[NUM_LEDS][3];
-
-	if (fake_power) {
-		pthread_mutex_lock(&leds_mutex);
-		memcpy(copyleds, leds, sizeof(leds));
-		pthread_mutex_unlock(&leds_mutex);
-
-		for (i = 0; i < NUM_LEDS; i++) {
-			rect.x = i * w;
-			rect.y = 0;
-			rect.width = w;
-			rect.height = win_h;
-
-			change_gc_color(copyleds[i][0],
-					copyleds[i][1],
-					copyleds[i][2]);
-
-			xcb_poly_fill_rectangle(c, win, foreground, 1, &rect);
-		}
-	} else {
-		rect.x = 0;
-		rect.y = 0;
-		rect.width = win_w;
-		rect.height = win_h;
-
-		change_gc_color(0, 0, 0);
-		xcb_poly_fill_rectangle(c, win, foreground, 1, &rect);
-
-		change_gc_color(0x8080, 0, 0);
-
-		for (i = 0; i < NUM_LEDS; i++) {
-			segments[0].x1 = i * w;
-			segments[0].y1 = 0;
-			segments[0].x2 = segments[0].x1 + w;
-			segments[0].y2 = win_h;
-			segments[1].x1 = segments[0].x1;
-			segments[1].y1 = win_h;
-			segments[1].x2 = segments[0].x2;
-			segments[1].y2 = 0;
-			xcb_poly_segment(c, win, foreground, 2, segments);
-		}
-	}
-
-	xcb_flush(c);
-}
-
-void setrgb(int led, int red, int green, int blue)
-{
-	led %= NUM_LEDS;
-
-	pthread_mutex_lock(&leds_mutex);
-	leds[led][0] = red << 8 | red;
-	leds[led][1] = green << 8 | green;
-	leds[led][2] = blue << 8 | blue;
-	pthread_mutex_unlock(&leds_mutex);
-
-	update_window();
-}
-
-/*****************************************************************************/
-/* lb_common stubs */
-
-
-
-/* Brightness serves no purpose here. It's automatic on the Chromebook. */
-static int brightness = 0xc0;
-void lb_set_brightness(unsigned int newval)
-{
-	brightness = newval;
-}
-uint8_t lb_get_brightness(void)
-{
-	return brightness;
-}
-
-void lb_set_rgb(unsigned int led, int red, int green, int blue)
-{
-	int i;
-	if (led >= NUM_LEDS)
-		for (i = 0; i < NUM_LEDS; i++)
-			setrgb(i, red, green, blue);
-	else
-		setrgb(led, red, green, blue);
-}
-
-int lb_get_rgb(unsigned int led, uint8_t *red, uint8_t *green, uint8_t *blue)
-{
-	led %= NUM_LEDS;
-	pthread_mutex_lock(&leds_mutex);
-	*red = leds[led][0];
-	*green = leds[led][1];
-	*blue = leds[led][2];
-	pthread_mutex_unlock(&leds_mutex);
-	return 0;
-}
-
-void lb_init(void)
-{
-	if (fake_power)
-		lb_set_rgb(NUM_LEDS, 0, 0, 0);
-};
-void lb_off(void)
-{
-	fake_power = 0;
-	update_window();
-};
-void lb_on(void)
-{
-	fake_power = 1;
-	update_window();
-};
-void lb_hc_cmd_dump(struct ec_response_lightbar *out)
-{
-	printf("lightbar is %s\n", fake_power ? "on" : "off");
-	memset(out, fake_power, sizeof(*out));
-};
-void lb_hc_cmd_reg(const struct ec_params_lightbar *in) { };
-
-int lb_power(int enabled)
-{
-	return fake_power;
-}
-
-
-/*****************************************************************************/
-/* Event handling stuff */
-
-void *entry_windows(void *ptr)
-{
-	xcb_generic_event_t *e;
-	xcb_expose_event_t *ev;
-	xcb_button_press_event_t *bv;
-	int chg = 1;
-
-	while ((e = xcb_wait_for_event(c))) {
-
-		switch (e->response_type & ~0x80) {
-		case XCB_EXPOSE:
-			ev = (xcb_expose_event_t *)e;
-			if (win_w != ev->width || win_h != ev->height) {
-				win_w = ev->width;
-				win_h = ev->height;
-			}
-			update_window();
-			break;
-		case XCB_BUTTON_PRESS:
-			bv = (xcb_button_press_event_t *)e;
-			switch (bv->detail) {
-			case 1:
-				demo_battery_level(-1);
-				break;
-			case 3:
-				demo_battery_level(+1);
-				break;
-			case 2:
-				chg = !chg;
-				demo_is_charging(chg);
-				break;
-			}
-			break;
-		}
-
-		free(e);
-	}
-
-	cleanup();
-	exit(0);
-	return 0;
-}
diff --git a/extra/rma_reset/.gitignore b/extra/rma_reset/.gitignore
deleted file mode 100644
index ae297b7dc0..0000000000
--- a/extra/rma_reset/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-base32.o
-curve25519-generic.o
-curve25519.o
-rma_reset
-sha256.o
diff --git a/extra/rma_reset/Makefile b/extra/rma_reset/Makefile
deleted file mode 100644
index 4a640c5b4c..0000000000
--- a/extra/rma_reset/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CC ?= gcc
-PROGRAM := rma_reset
-SOURCE  := $(PROGRAM).c
-OBJS    := curve25519.o curve25519-generic.o sha256.o base32.o
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-ifeq ($(DEBUG),1)
-CFLAGS += -g -O0
-else
-CFLAGS += -O3
-endif
-#
-# Add libusb-1.0 required flags
-#
-INCLUDE=-I. -I../../ -I../../fuzz -I../../test -I../../include -I../../chip/host
-LIBS    += -lcrypto -lssl
-CFLAGS  += ${INCLUDE}
-STANDALONE_FLAGS=${INCLUDE} -ffreestanding -fno-builtin \
-                        -Ibuiltin/ -D"__keep= "
-
-$(PROGRAM): $(SOURCE) $(OBJS) Makefile
-	$(CC) $(CFLAGS) $(SOURCE) $(LFLAGS) $(LIBS) $(OBJS) -o $@
-
-curve25519-generic.o: ../../common/curve25519-generic.c
-	$(CC) $(STANDALONE_FLAGS) -c -o curve25519-generic.o \
-				../../common/curve25519-generic.c
-
-curve25519.o: ../../common/curve25519.c
-	$(CC) $(STANDALONE_FLAGS) -c -o curve25519.o ../../common/curve25519.c
-
-sha256.o: ../../common/sha256.c
-	$(CC) $(STANDALONE_FLAGS) -c -o sha256.o ../../common/sha256.c
-
-base32.o: ../../common/base32.c
-	$(CC) $(STANDALONE_FLAGS) -c -o base32.o ../../common/base32.c
-
-.PHONY: clean
-
-clean:
-	rm -rf *.o $(PROGRAM) *~
diff --git a/extra/rma_reset/board.h b/extra/rma_reset/board.h
deleted file mode 100644
index f969ad0c56..0000000000
--- a/extra/rma_reset/board.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_RNG
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/extra/rma_reset/rma_reset.c b/extra/rma_reset/rma_reset.c
deleted file mode 100644
index fe1eb5e909..0000000000
--- a/extra/rma_reset/rma_reset.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <endian.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include <openssl/bn.h>
-#include <openssl/ec.h>
-#include <openssl/obj_mac.h>
-#include <openssl/rand.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "rma_auth.h"
-#include "curve25519.h"
-#include "sha256.h"
-#include "base32.h"
-
-#define EC_COORDINATE_SZ 32
-#define EC_PRIV_KEY_SZ 32
-#define EC_P256_UNCOMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ * 2 + 1)
-#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ  + 1)
-
-#define SERVER_ADDRESS \
-	"https://www.google.com/chromeos/partner/console/cr50reset/request"
-
-/* Test server keys for x25519 and p256 curves. */
-static const uint8_t rma_test_server_x25519_public_key[] = {
-	0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73,
-	0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,
-	0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,
-	0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f
-};
-
-static const uint8_t rma_test_server_x25519_private_key[] = {
-	0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77,
-	0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,
-	0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,
-	0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad
-};
-
-#define RMA_TEST_SERVER_X25519_KEY_ID 0x10
-#define RMA_PROD_SERVER_X25519_KEY_ID 0
-
-/*
- * P256 curve keys, generated using openssl as follows:
- *
- * openssl ecparam -name prime256v1 -genkey -out key.pem
- * openssl ec -in key.pem -text -noout
- */
-static const uint8_t rma_test_server_p256_private_key[] = {
-	0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a,
-	0xa7, 0x6b, 0xea, 0x8f, 0x30, 0xcc, 0xf7, 0x3d,
-	0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec, 0x7d, 0xe9,
-	0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81
-};
-
-/*
- * P256 public key in full form, x and y coordinates with a single byte
- * prefix, 65 bytes total.
- */
-static const uint8_t rma_test_server_p256_public_key[] = {
-	0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc,
-	0x68, 0xf4, 0x8c, 0x56, 0x65, 0x5a, 0xcb, 0xf8,
-	0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b, 0xae, 0xd6,
-	0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b,
-	0x0a, 0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19,
-	0x81, 0x76, 0x84, 0x92, 0x7f, 0x8d, 0xb2, 0xbe,
-	0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00, 0x67,
-	0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4,
-	0x35
-};
-
-#define RMA_TEST_SERVER_P256_KEY_ID 0x20
-#define RMA_PROD_SERVER_P256_KEY_ID 0x01
-
-/* Default values which can change based on command line arguments. */
-static uint8_t server_key_id = RMA_TEST_SERVER_X25519_KEY_ID;
-static uint8_t board_id[4] = {'Z', 'Z', 'C', 'R'};
-static uint8_t device_id[8] = {'T', 'H', 'X', 1, 1, 3, 8, 0xfe};
-static uint8_t hw_id[20] = "TESTSAMUS1234";
-
-static char challenge[RMA_CHALLENGE_BUF_SIZE];
-static char authcode[RMA_AUTHCODE_BUF_SIZE];
-
-static char *progname;
-static char *short_opts = "a:b:c:d:hpk:tw:";
-static const struct option long_opts[] = {
-	/* name    hasarg *flag val */
-	{"auth_code",  1,   NULL, 'a'},
-	{"board_id",   1,   NULL, 'b'},
-	{"challenge",  1,   NULL, 'c'},
-	{"device_id",  1,   NULL, 'd'},
-	{"help",       0,   NULL, 'h'},
-	{"hw_id",      1,   NULL, 'w'},
-	{"key_id",     1,   NULL, 'k'},
-	{"p256",       0,   NULL, 'p'},
-	{"test",       0,   NULL, 't'},
-	{},
-};
-
-void panic_assert_fail(const char *fname, int linenum);
-void rand_bytes(void *buffer, size_t len);
-int safe_memcmp(const void *s1, const void *s2, size_t size);
-
-void panic_assert_fail(const char *fname, int linenum)
-{
-	printf("\nASSERTION FAILURE at %s:%d\n", fname, linenum);
-}
-
-int safe_memcmp(const void *s1, const void *s2, size_t size)
-{
-	const uint8_t *us1 = s1;
-	const uint8_t *us2 = s2;
-	int result = 0;
-
-	if (size == 0)
-		return 0;
-
-	while (size--)
-		result |= *us1++ ^ *us2++;
-
-	return result != 0;
-}
-
-void rand_bytes(void *buffer, size_t len)
-{
-	RAND_bytes(buffer, len);
-}
-
-/*
- * Generate a p256 key pair and calculate the shared secret based on our
- * private key and the server public key.
- *
- * Return the X coordinate of the generated public key and the shared secret.
- *
- * @pub_key - the compressed public key without the prefix; by convention
- *	      between RMA client and server the generated pubic key would
- *	      always have prefix of 0x03, (the Y coordinate value is odd), so
- *	      it is omitted from the key blob, which allows to keep the blob
- *	      size at 32 bytes.
- * @secret_seed - the product of multiplying of the server point by our
- *	      private key, only the 32 bytes of X coordinate are returned.
- */
-static void p256_key_and_secret_seed(uint8_t pub_key[32],
-				     uint8_t secret_seed[32])
-{
-	const EC_GROUP *group;
-	EC_KEY *key;
-	EC_POINT *pub;
-	EC_POINT *secret_point;
-	uint8_t buf[EC_P256_UNCOMPRESSED_PUB_KEY_SZ];
-
-	/* Prepare structures to operate on. */
-	key = EC_KEY_new_by_curve_name(NID_X9_62_prime256v1);
-	group = EC_KEY_get0_group(key);
-	pub = EC_POINT_new(group);
-
-	/*
-	 * We might have to try multiple times, until the Y coordinate is an
-	 * odd value as required by convention.
-	 */
-	do {
-		EC_KEY_generate_key(key);
-
-		/* Extract public key into an octal array. */
-		EC_POINT_point2oct(group, EC_KEY_get0_public_key(key),
-				   POINT_CONVERSION_UNCOMPRESSED,
-				   buf, sizeof(buf), NULL);
-
-		/* If Y coordinate is an odd value, we are done. */
-	} while (!(buf[sizeof(buf) - 1] & 1));
-
-	/* Copy X coordinate out. */
-	memcpy(pub_key, buf + 1, 32);
-
-	/*
-	 * We have our private key and the server's point coordinates (aka
-	 * server public key). Let's multiply the coordinates by our private
-	 * key to get the shared secret.
-	 */
-
-	/* Load raw public key into the point structure. */
-	EC_POINT_oct2point(group, pub, rma_test_server_p256_public_key,
-			   sizeof(rma_test_server_p256_public_key), NULL);
-
-	secret_point = EC_POINT_new(group);
-
-	/* Multiply server public key by our private key. */
-	EC_POINT_mul(group, secret_point, 0, pub,
-		     EC_KEY_get0_private_key(key), 0);
-
-	/* Pull the result back into the octal buffer. */
-	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
-			   buf, sizeof(buf), NULL);
-
-	/*
-	 * Copy X coordinate into the output to use as the shared secret
-	 * seed.
-	 */
-	memcpy(secret_seed, buf + 1, 32);
-
-	/* release resources */
-	EC_KEY_free(key);
-	EC_POINT_free(pub);
-	EC_POINT_free(secret_point);
-}
-
-/*
- * When imitating server side, calculate the secret value given the client's
- * compressed public key (X coordinate only with 0x03 prefix implied) and
- * knowing our (server) private key.
- *
- * @secret - array to return the X coordinate of the calculated point.
- * @raw_pub_key - X coordinate of the point calculated by the client, 0x03
- *		  prefix implied.
- */
-static void p256_calculate_secret(uint8_t secret[32],
-				  const uint8_t raw_pub_key[32])
-{
-	uint8_t raw_pub_key_x[EC_P256_COMPRESSED_PUB_KEY_SZ];
-	EC_KEY *key;
-	const uint8_t *kp = raw_pub_key_x;
-	EC_POINT *secret_point;
-	const EC_GROUP *group;
-	BIGNUM *priv;
-	uint8_t buf[EC_P256_UNCOMPRESSED_PUB_KEY_SZ];
-
-	/* Express server private key as a BN. */
-	priv = BN_new();
-	BN_bin2bn(rma_test_server_p256_private_key, EC_PRIV_KEY_SZ, priv);
-
-	/*
-	 * Populate a p256 key structure based on the compressed
-	 * representation of the client's public key.
-	 */
-	raw_pub_key_x[0] = 3; /* Implied by convention. */
-	memcpy(raw_pub_key_x + 1, raw_pub_key, sizeof(raw_pub_key_x) - 1);
-	key = EC_KEY_new_by_curve_name(NID_X9_62_prime256v1);
-	group = EC_KEY_get0_group(key);
-	key = o2i_ECPublicKey(&key, &kp, sizeof(raw_pub_key_x));
-
-	/* This is where the multiplication result will go. */
-	secret_point = EC_POINT_new(group);
-
-	/* Multiply client's point by our private key. */
-	EC_POINT_mul(group, secret_point, 0,
-		     EC_KEY_get0_public_key(key),
-		     priv, 0);
-
-	/* Pull the result back into the octal buffer. */
-	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
-			   buf, sizeof(buf), NULL);
-
-	/* Copy X coordinate into the output to use as the shared secret. */
-	memcpy(secret, buf + 1, 32);
-}
-
-static int rma_server_side(const char *generated_challenge)
-{
-	int key_id, version;
-	uint8_t secret[32];
-	uint8_t hmac[32];
-	struct rma_challenge c;
-	uint8_t *cptr = (uint8_t *)&c;
-
-	/* Convert the challenge back into binary */
-	if (base32_decode(cptr, 8 * sizeof(c), generated_challenge, 9) !=
-		8 * sizeof(c)) {
-		printf("Error decoding challenge\n");
-		return -1;
-	}
-
-	version = RMA_CHALLENGE_GET_VERSION(c.version_key_id);
-	key_id = RMA_CHALLENGE_GET_KEY_ID(c.version_key_id);
-	printf("Challenge:    %s\n", generated_challenge);
-	printf("Version:      %d\n", version);
-	printf("Server KeyID: %d\n", key_id);
-
-	if (version != RMA_CHALLENGE_VERSION)
-		printf("Unsupported challenge version %d\n", version);
-
-	/* Calculate the shared secret, use curve based on the key ID. */
-	switch (key_id) {
-	case RMA_PROD_SERVER_X25519_KEY_ID:
-		printf("Unsupported Prod KeyID %d\n", key_id);
-	case RMA_TEST_SERVER_X25519_KEY_ID:
-		X25519(secret, rma_test_server_x25519_private_key,
-		       c.device_pub_key);
-		break;
-	case RMA_PROD_SERVER_P256_KEY_ID:
-		printf("Unsupported Prod KeyID %d\n", key_id);
-	case RMA_TEST_SERVER_P256_KEY_ID:
-		p256_calculate_secret(secret, c.device_pub_key);
-		break;
-	default:
-		printf("Unknown KeyID %d\n", key_id);
-		return 1;
-	}
-
-	/*
-	 * Auth code is a truncated HMAC of the ephemeral public key, BoardID,
-	 * and DeviceID.
-	 */
-	hmac_SHA256(hmac, secret, sizeof(secret), cptr + 1, sizeof(c) - 1);
-	if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE,
-			  hmac, RMA_AUTHCODE_CHARS * 5, 0)) {
-		printf("Error encoding auth code\n");
-		return -1;
-	}
-	printf("Authcode:     %s\n", authcode);
-
-	return 0;
-};
-
-static int rma_create_test_challenge(int p256_mode)
-{
-	uint8_t temp[32];   /* Private key or HMAC */
-	uint8_t secret_seed[32];
-	struct rma_challenge c;
-	uint8_t *cptr = (uint8_t *)&c;
-	uint32_t bid;
-
-	/* Clear the current challenge and authcode, if any */
-	memset(challenge, 0, sizeof(challenge));
-	memset(authcode, 0, sizeof(authcode));
-
-	memset(&c, 0, sizeof(c));
-	c.version_key_id = RMA_CHALLENGE_VKID_BYTE(
-		RMA_CHALLENGE_VERSION, server_key_id);
-
-	memcpy(&bid, board_id, sizeof(bid));
-	bid = be32toh(bid);
-	memcpy(c.board_id, &bid, sizeof(c.board_id));
-
-	memcpy(c.device_id, device_id, sizeof(c.device_id));
-
-	if (p256_mode) {
-		p256_key_and_secret_seed(c.device_pub_key, secret_seed);
-	} else {
-		/* Calculate a new ephemeral key pair */
-		X25519_keypair(c.device_pub_key, temp);
-		/* Calculate the shared secret seed. */
-		X25519(secret_seed, temp, rma_test_server_x25519_public_key);
-	}
-
-	/* Encode the challenge */
-	if (base32_encode(challenge, sizeof(challenge), cptr, 8 * sizeof(c), 9))
-		return 1;
-
-	/*
-	 * Auth code is a truncated HMAC of the ephemeral public key, BoardID,
-	 * and DeviceID.  Those are all in the right order in the challenge
-	 * struct, after the version/key id byte.
-	 */
-	hmac_SHA256(temp, secret_seed, sizeof(secret_seed),
-		    cptr + 1, sizeof(c) - 1);
-	if (base32_encode(authcode, sizeof(authcode), temp,
-			  RMA_AUTHCODE_CHARS * 5, 0))
-		return 1;
-
-	return 0;
-}
-
-int rma_try_authcode(const char *code)
-{
-	return safe_memcmp(authcode, code, RMA_AUTHCODE_CHARS);
-}
-
-static void dump_key(const char *title, const uint8_t *key, size_t key_size)
-{
-	size_t i;
-	const int bytes_per_line = 8;
-
-	printf("\n\n\%s\n", title);
-	for (i = 0; i < key_size; i++)
-		printf("%02x%c", key[i], ((i + 1) % bytes_per_line) ? ' ':'\n');
-
-	if (i % bytes_per_line)
-		printf("\n");
-}
-
-static void print_params(int p_flag)
-{
-	int i;
-	const uint8_t *priv_key;
-	const uint8_t *pub_key;
-	int key_id;
-	size_t pub_key_size;
-
-	printf("\nBoard Id:\n");
-	for (i = 0; i < 4; i++)
-		printf("%c ", board_id[i]);
-
-	printf("\n\nDevice Id:\n");
-	for (i = 0; i < 3; i++)
-		printf("%c ", device_id[i]);
-	for (i = 3; i < 8; i++)
-		printf("%02x ", device_id[i]);
-
-	if (p_flag) {
-		priv_key = rma_test_server_p256_private_key;
-		pub_key = rma_test_server_p256_public_key;
-		pub_key_size = sizeof(rma_test_server_p256_public_key);
-		key_id = RMA_TEST_SERVER_P256_KEY_ID;
-	} else {
-		priv_key = rma_test_server_x25519_private_key;
-		pub_key = rma_test_server_x25519_public_key;
-		pub_key_size = sizeof(rma_test_server_x25519_public_key);
-		key_id = RMA_TEST_SERVER_X25519_KEY_ID;
-	}
-
-	printf("\n\nServer Key Id:\n");
-	printf("%02x", key_id);
-
-	/* Both private keys are of the same size */
-	dump_key("Server Private Key:", priv_key, EC_PRIV_KEY_SZ);
-	dump_key("Server Public Key:", pub_key, pub_key_size);
-
-	printf("\nChallenge:\n");
-	for (i = 0; i < RMA_CHALLENGE_CHARS; i++) {
-		printf("%c", challenge[i]);
-		if (((i + 1) % 5) == 0)
-			printf(" ");
-		if (((i + 1) % 40) == 0)
-			printf("\n");
-	}
-
-	printf("\nAuthorization Code:\n");
-	for (i = 0; i < RMA_AUTHCODE_BUF_SIZE; i++)
-		printf("%c", authcode[i]);
-
-	printf("\n\nChallenge String:\n");
-	printf("%s?challenge=", SERVER_ADDRESS);
-	for (i = 0; i < RMA_CHALLENGE_CHARS; i++)
-		printf("%c", challenge[i]);
-	printf("&hwid=%s\n", hw_id);
-
-	printf("\n");
-}
-
-static void usage(void)
-{
-	printf("\nUsage: %s  [--p256] --key_id <arg> --board_id <arg> "
-	       "--device_id <arg> --hw_id <arg> |\n"
-	       "                           --auth_code <arg> |\n"
-	       "                           --challenge <arg>\n"
-		"\n"
-		"This is used to generate the cr50 or server responses for rma "
-		"open.\n"
-		"The cr50 side can be used to generate a challenge response "
-		"and sends authoriztion code to reset device.\n"
-		"The server side can generate an authcode from cr50's "
-		"rma challenge.\n"
-		"\n"
-		"  -c,--challenge    The challenge generated by cr50\n"
-		"  -k,--key_id       Index of the server private key\n"
-		"  -b,--board_id     BoardID type field\n"
-		"  -d,--device_id    Device-unique identifier\n"
-		"  -a,--auth_code    Reset authorization code\n"
-		"  -w,--hw_id        Hardware id\n"
-		"  -h,--help         Show this message\n"
-		"  -p,--p256         Use prime256v1 curve instead of x25519\n"
-		"  -t,--test         "
-			"Generate challenge using default test inputs\n"
-	       "\n", progname);
-}
-
-static int atoh(char *v)
-{
-	char hn;
-	char ln;
-
-	hn = toupper(*v);
-	ln = toupper(*(v + 1));
-
-	hn -= (isdigit(hn) ? '0' : '7');
-	ln -= (isdigit(ln) ? '0' : '7');
-
-	if ((hn < 0 || hn > 0xf) || (ln < 0 || ln > 0xf))
-		return 0;
-
-	return (hn << 4) | ln;
-}
-
-static int set_server_key_id(char *id)
-{
-	/* verify length */
-	if (strlen(id) != 2)
-		return 1;
-
-	/* verify digits */
-	if (!isxdigit(*id) || !isxdigit(*(id+1)))
-		return 1;
-
-	server_key_id = atoh(id);
-
-	return 0;
-}
-
-static int set_board_id(char *id)
-{
-	int i;
-
-	/* verify length */
-	if (strlen(id) != 8)
-		return 1;
-
-	/* verify digits */
-	for (i = 0; i < 8; i++)
-		if (!isxdigit(*(id + i)))
-			return 1;
-
-	for (i = 0; i < 4; i++)
-		board_id[i] = atoh((id + (i*2)));
-
-	return 0;
-}
-
-static int set_device_id(char *id)
-{
-	int i;
-
-	/* verify length */
-	if (strlen(id) != 16)
-		return 1;
-
-	for (i = 0; i < 16; i++)
-		if (!isxdigit(*(id + i)))
-			return 1;
-
-	for (i = 0; i < 8; i++)
-		device_id[i] = atoh((id + (i*2)));
-
-	return 0;
-}
-
-static int set_hw_id(char *id)
-{
-	int i;
-	int len;
-
-	len = strlen(id);
-	if (len > 20)
-		len = 20;
-
-	for (i = 0; i < 20; i++)
-		hw_id[i] = *(id + i);
-
-	return 0;
-}
-
-static int set_auth_code(char *code)
-{
-	int i;
-
-	if (strlen(code) != 8)
-		return 1;
-
-	for (i = 0; i < 8; i++)
-		authcode[i] = *(code + i);
-	authcode[i] = 0;
-
-	return 0;
-}
-
-int main(int argc, char **argv)
-{
-	int a_flag = 0;
-	int b_flag = 0;
-	int d_flag = 0;
-	int k_flag = 0;
-	int p_flag = 0;
-	int t_flag = 0;
-	int w_flag = 0;
-	int i;
-
-	progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;
-	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
-		switch (i) {
-		case 't':
-			t_flag = 1;
-			break;
-		case 'c':
-			return rma_server_side(optarg);
-		case 'k':
-			if (set_server_key_id(optarg)) {
-				printf("Malformed key id\n");
-				return 1;
-			}
-			k_flag = 1;
-			break;
-		case 'b':
-			if (set_board_id(optarg)) {
-				printf("Malformed board id\n");
-				return 1;
-			}
-			b_flag = 1;
-			break;
-		case 'd':
-			if (set_device_id(optarg)) {
-				printf("Malformed device id\n");
-				return 1;
-			}
-			d_flag = 1;
-			break;
-		case 'a':
-			if (set_auth_code(optarg)) {
-				printf("Malformed authorization code\n");
-				return 1;
-			}
-			a_flag = 1;
-			break;
-		case 'w':
-			if (set_hw_id(optarg)) {
-				printf("Malformed hardware id\n");
-				return 1;
-			}
-			w_flag = 1;
-			break;
-		case 'h':
-			usage();
-			return 0;
-		case 0:                         /* auto-handled option */
-			break;
-		case '?':
-			if (optopt)
-				printf("Unrecognized option: -%c\n", optopt);
-			else
-				printf("Unrecognized option: %s\n",
-							argv[optind - 1]);
-			break;
-		case ':':
-			printf("Missing argument to %s\n", argv[optind - 1]);
-			break;
-		case 'p':
-			p_flag = 1;
-			server_key_id = RMA_TEST_SERVER_P256_KEY_ID;
-			break;
-		default:
-			printf("Internal error at %s:%d\n", __FILE__, __LINE__);
-			return 1;
-		}
-	}
-
-	if (a_flag) {
-		FILE *acode;
-		char verify_authcode[RMA_AUTHCODE_BUF_SIZE];
-		int rv;
-
-		acode = fopen("/tmp/authcode", "r");
-		if (acode == NULL) {
-			printf("Please generate challenge\n");
-			return 1;
-		}
-
-		rv = fread(verify_authcode, 1, RMA_AUTHCODE_BUF_SIZE, acode);
-		if (rv != RMA_AUTHCODE_BUF_SIZE) {
-			printf("Error reading saved authcode\n");
-			return 1;
-		}
-		if (strcmp(verify_authcode, authcode) == 0)
-			printf("Code Accepted\n");
-		else
-			printf("Invalid Code\n");
-
-	} else {
-		if (!t_flag) { /* Use default values */
-			if (!k_flag || !b_flag || !d_flag || !w_flag) {
-				printf("server-side: Flag -c is mandatory\n");
-				printf("cr50-side: Flags -k, -b, -d, and -w "
-					"are mandatory\n");
-				return 1;
-			}
-		}
-
-		rma_create_test_challenge(p_flag);
-
-		{
-			FILE *acode;
-
-			acode = fopen("/tmp/authcode", "w");
-			if (acode < 0)
-				return 1;
-			fwrite(authcode, 1, RMA_AUTHCODE_BUF_SIZE, acode);
-			fclose(acode);
-		}
-
-		print_params(p_flag);
-	}
-
-	return 0;
-}
diff --git a/extra/sps_errs/.gitignore b/extra/sps_errs/.gitignore
deleted file mode 100644
index ea17491321..0000000000
--- a/extra/sps_errs/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-prog
diff --git a/extra/sps_errs/Makefile b/extra/sps_errs/Makefile
deleted file mode 100644
index 12224ad803..0000000000
--- a/extra/sps_errs/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Use your own libmpsse if you want, but we're going to use the files
-# that are part of the Chromium OS trunks_client program.
-PLATFORM2 = ../../../../platform2
-MPSSE_DIR = $(PLATFORM2)/trunks/ftdi
-
-PROG = prog
-SRCS = prog.c $(MPSSE_DIR)/mpsse.c $(MPSSE_DIR)/support.c
-
-CFLAGS = \
-	-std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-CFLAGS += -I../../include -I${MPSSE_DIR} -I${PLATFORM2}
-
-CFLAGS += $(shell pkg-config --cflags libusb-1.0 libftdi1)
-LIBS   += $(shell pkg-config --libs   libusb-1.0 libftdi1)
-
-$(PROG): $(SRCS) Makefile
-	gcc $(CFLAGS) $(SRCS) $(LDFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-clean:
-	rm -rf $(PROG)
diff --git a/extra/sps_errs/README b/extra/sps_errs/README
deleted file mode 100644
index d1fbb6b43f..0000000000
--- a/extra/sps_errs/README
+++ /dev/null
@@ -1,28 +0,0 @@
-SETUP:
-
-  Attach an EC to the build host using an FTDI USB-to-SPI adapter.
-
-BUILD:
-
-  make
-  ./prog
-
-
-USAGE:
-
-  Usage: ./prog [-v] [-c BYTES]
-
-  This sends a EC_CMD_HELLO host command. The -c option can
-  be used to truncate the exchange early, to see how the EC
-  deals with the interruption.
-
-NOTE:
-
-  Ubuntu Trusty uses an ancient version of libftdi.
-
-  If building outside of the Chromium chroot, you'll probably want to grab the
-  latest libftdi1-1.2.tar.bz2 from
-
-    http://www.intra2net.com/en/developer/libftdi/
-
-  and install it into /usr instead.
diff --git a/extra/sps_errs/prog.c b/extra/sps_errs/prog.c
deleted file mode 100644
index b649199068..0000000000
--- a/extra/sps_errs/prog.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "mpsse.h"
-
-#include "ec_commands.h"
-
-static int opt_verbose;
-static size_t stop_after = -1;
-
-/* Communication handle */
-static struct mpsse_context *mpsse;
-
-/* enum ec_status meaning */
-static const char *ec_strerr(enum ec_status r)
-{
-	static const char * const strs[] = {
-		"SUCCESS",
-		"INVALID_COMMAND",
-		"ERROR",
-		"INVALID_PARAM",
-		"ACCESS_DENIED",
-		"INVALID_RESPONSE",
-		"INVALID_VERSION",
-		"INVALID_CHECKSUM",
-		"IN_PROGRESS",
-		"UNAVAILABLE",
-		"TIMEOUT",
-		"OVERFLOW",
-		"INVALID_HEADER",
-		"REQUEST_TRUNCATED",
-		"RESPONSE_TOO_BIG",
-		"BUS_ERROR",
-		"BUSY",
-	};
-	if (r >= EC_RES_SUCCESS && r <= EC_RES_BUSY)
-		return strs[r];
-
-	return "<undefined result>";
-};
-
-
-/****************************************************************************
- * Debugging output
- */
-
-#define LINELEN 16
-
-static void showline(uint8_t *buf, int len)
-{
-	int i;
-	printf("  ");
-	for (i = 0; i < len; i++)
-		printf(" %02x", buf[i]);
-	for (i = len; i < LINELEN; i++)
-		printf("   ");
-	printf("    ");
-	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
-	printf("\n");
-}
-
-static void show(const char *fmt, uint8_t *buf, int len)
-{
-	int i, m, n;
-
-	if (!opt_verbose)
-		return;
-
-	printf(fmt, len);
-
-	m = len / LINELEN;
-	n = len % LINELEN;
-
-	for (i = 0; i < m; i++)
-		showline(buf + i * LINELEN, LINELEN);
-	if (n)
-		showline(buf + m * LINELEN, n);
-}
-
-/****************************************************************************
- * Send command & receive result
- */
-
-/*
- * With proto v3, the kernel driver asks the EC for the max param size
- * (EC_CMD_GET_PROTOCOL_INFO) at probe time, because it can vary depending on
- * the bus and/or the supported commands.
- *
- * FIXME: For now we'll just hard-code a size.
- */
-static uint8_t txbuf[128];
-
-/*
- * Load the output buffer with a proto v3 request (header, then data, with
- * checksum correct in header).
- */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
-{
-	struct ec_host_request *request;
-	size_t i, total_len;
-	uint8_t csum = 0;
-
-	total_len = sizeof(*request) + data_len;
-	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
-		return -1;
-	}
-
-	/* Header first */
-	request = (struct ec_host_request *)txbuf;
-	request->struct_version = EC_HOST_REQUEST_VERSION;
-	request->checksum = 0;
-	request->command = cmd;
-	request->command_version = version;
-	request->reserved = 0;
-	request->data_len = data_len;
-
-	/* Then data */
-	memcpy(txbuf + sizeof(*request), data, data_len);
-
-	/* Update checksum */
-	for (i = 0; i < total_len; i++)
-		csum += txbuf[i];
-	request->checksum = -csum;
-
-	return total_len;
-}
-
-
-/* Timeout flag, so we don't wait forever */
-static int timedout;
-static void alarm_handler(int sig)
-{
-	timedout = 1;
-}
-
-/*
- * Send command, wait for result. Return zero if communication succeeded; check
- * response to see if the EC liked the command.
- */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *hdr,
-		    void *bodydest,
-		    size_t bodylen)
-{
-	uint8_t *tptr, *hptr = 0, *bptr = 0;
-	size_t len, i;
-	uint8_t sum = 0;
-	int lastone = 0x1111;
-	int ret = 0;
-	size_t bytes_left = stop_after;
-	size_t bytes_sent = 0;
-
-
-	/* Load up the txbuf with the stuff to send */
-	len = prepare_request(cmd, version, outbuf, outsize);
-	if (len < 0)
-		return -1;
-
-	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
-		return -1;
-	}
-
-	/* Send the command request */
-	if (len > bytes_left) {
-		printf("len %zd => %zd\n", len, bytes_left);
-		len = bytes_left;
-	}
-
-	show("Transfer(%d) =>\n", txbuf, len);
-	tptr = Transfer(mpsse, txbuf, len);
-	bytes_left -= len;
-	bytes_sent += len;
-	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
-		goto out;
-	}
-
-	show("Transfer(%d) <=\n", tptr, len);
-
-	/* Make sure the EC was listening */
-	for (i = 0; i < len; i++) {
-		switch (tptr[i]) {
-		case EC_SPI_PAST_END:
-		case EC_SPI_RX_BAD_DATA:
-		case EC_SPI_NOT_READY:
-			ret = tptr[i];
-			/* FALLTHROUGH */
-		default:
-			break;
-		}
-		if (ret)
-			break;
-	}
-	free(tptr);
-	if (ret) {
-		printf("HEY: EC no good (0x%02x)\n", ret);
-		goto out;
-	}
-
-	if (!bytes_left)
-		goto out;
-
-	/* Read until we see the response come along */
-
-	/* Give up eventually */
-	timedout = 0;
-	if (SIG_ERR == signal(SIGALRM, alarm_handler)) {
-		perror("Problem with signal handler");
-		goto out;
-	}
-	alarm(1);
-
-	if (opt_verbose)
-		printf("Wait:");
-
-	/* Read a byte at a time until we see the start of the frame.
-	 * This is slow, but still faster than the EC. */
-	while (bytes_left) {
-		uint8_t *ptr = Read(mpsse, 1);
-		bytes_left--;
-		bytes_sent++;
-		if (!ptr) {
-			fprintf(stderr, "Read failed: %s\n",
-				ErrorString(mpsse));
-			alarm(0);
-			goto out;
-		}
-		if (opt_verbose && lastone != *ptr) {
-			printf(" %02x", *ptr);
-			lastone = *ptr;
-		}
-		if (*ptr == EC_SPI_FRAME_START) {
-			free(ptr);
-			break;
-		}
-		free(ptr);
-
-		if (timedout) {
-			fprintf(stderr, "timed out\n");
-			goto out;
-		}
-	}
-	alarm(0);
-
-	if (opt_verbose)
-		printf("\n");
-
-	if (!bytes_left)
-		goto out;
-
-	/* Now read the response header */
-	len = sizeof(*hdr);
-	if (len > bytes_left) {
-		printf("len %zd => %zd\n", len, bytes_left);
-		len = bytes_left;
-	}
-
-	hptr = Read(mpsse, len);
-	bytes_left -= len;
-	bytes_sent += len;
-	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
-		goto out;
-	}
-	show("Header(%d):\n", hptr, sizeof(*hdr));
-	memcpy(hdr, hptr, sizeof(*hdr));
-
-	/* Check the header */
-	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
-		printf("HEY: response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
-		goto out;
-	}
-
-	if (hdr->data_len > bodylen) {
-		printf("HEY: response data_len %d is > %zd\n",
-		       hdr->data_len,
-		       bodylen);
-		goto out;
-	}
-
-	if (!bytes_left)
-		goto out;
-
-	len = hdr->data_len;
-	if (len > bytes_left) {
-		printf("len %zd => %zd\n", len, bytes_left);
-		len = bytes_left;
-	}
-
-	/* Read the data */
-	if (len) {
-		bptr = Read(mpsse, len);
-		bytes_left -= len;
-		bytes_sent += len;
-		if (!bptr) {
-			fprintf(stderr, "Read failed: %s\n",
-				ErrorString(mpsse));
-			goto out;
-		}
-		show("Body(%d):\n", bptr, hdr->data_len);
-		memcpy(bodydest, bptr, hdr->data_len);
-	}
-
-	/* Verify the checksum */
-	for (i = 0; i < sizeof(hdr); i++)
-		sum += hptr[i];
-	for (i = 0; i < hdr->data_len; i++)
-		sum += bptr[i];
-	if (sum)
-		printf("HEY: Checksum invalid\n");
-
-out:
-	printf("sent %zd bytes\n", bytes_sent);
-	if (!bytes_left)
-		printf("hit byte limit\n");
-	if (hptr)
-		free(hptr);
-	if (bptr)
-		free(bptr);
-
-	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
-		return -1;
-	}
-
-	return 0;
-}
-
-
-/****************************************************************************/
-
-/**
- * Try it.
- *
- * @return  zero on success
- */
-static int hello(void)
-{
-	struct ec_params_hello p;
-	struct ec_host_response resp;
-	struct ec_response_hello r;
-	uint32_t expected;
-	int retval;
-
-	memset(&p, 0, sizeof(p));
-	memset(&resp, 0, sizeof(resp));
-	memset(&r, 0, sizeof(r));
-
-	p.in_data = 0xa5a5a5a5;
-	expected = p.in_data + 0x01020304;
-
-	retval = send_cmd(EC_CMD_HELLO, 0,
-			  &p, sizeof(p),
-			  &resp,
-			  &r, sizeof(r));
-
-	if (retval) {
-		printf("Transmission error\n");
-		return -1;
-	}
-
-	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
-		return -1;
-	}
-
-	printf("sent %08x, expected %08x, got %08x => %s\n",
-	       p.in_data, expected, r.out_data,
-	       expected == r.out_data ? "yay" : "boo");
-
-	return !(expected == r.out_data);
-}
-
-static void usage(char *progname)
-{
-	printf("\nUsage: %s [-v] [-c BYTES]\n\n", progname);
-	printf("This sends a EC_CMD_HELLO host command. The -c option can\n");
-	printf("be used to truncate the exchange early, to see how the EC\n");
-	printf("deals with the interruption.\n\n");
-}
-
-int main(int argc, char *argv[])
-{
-	int retval = 1;
-	int errorcnt = 0;
-	int i;
-
-	while ((i = getopt(argc, argv, ":vc:")) != -1) {
-		switch (i) {
-		case 'c':
-			stop_after = atoi(optarg);
-			printf("stopping after %zd bytes\n", stop_after);
-			break;
-		case 'v':
-			opt_verbose++;
-			break;
-		case '?':
-			printf("unrecognized option: -%c\n", optopt);
-			errorcnt++;
-			break;
-		}
-	}
-	if (errorcnt) {
-		usage(argv[0]);
-		return 1;
-	}
-
-	/* Find something to talk to */
-	mpsse = MPSSE(SPI0, 2000000, 0);
-	if (!mpsse) {
-		printf("Can't find a device to open\n");
-		return 1;
-	}
-
-	if (0 != hello())
-		goto out;
-
-	retval = 0;
-out:
-	Close(mpsse);
-	mpsse = 0;
-	return retval;
-}
diff --git a/extra/stack_analyzer/README.md b/extra/stack_analyzer/README.md
deleted file mode 100644
index d1c77b57d2..0000000000
--- a/extra/stack_analyzer/README.md
+++ /dev/null
@@ -1,105 +0,0 @@
-# Stack Size Analysis Tool for EC Firmware
-
-This tool does static analysis on EC firmwares to get the maximum stack usage of
-each function and task. The maximum stack usage of a function includes the stack
-used by itself and the functions it calls.
-
-## Usage
-
-Make sure the firmware of your target board has been built.
-
-In `src/platform/ec`, run `make BOARD=${BOARD} SECTION=${SECTION}
-ANNOTATION=${ANNOTATION} analyzestack` The `${SECTION}` can be `RO` or `RW`. The
-`${ANNOTATION}` is a optional annotation file, see the example_annotation.yaml,
-by default, board/$BOARD/analyzestack.yaml is used.
-
-## Output
-
-For each task, it will output the result like below,
-
-```
-Task: PD_C1, Max size: 1156 (932 + 224), Allocated size: 640
-Call Trace:
-    pd_task (160) [common/usb_pd_protocol.c:1644] 1008a6e8
-        -> pd_task[common/usb_pd_protocol.c:1808] 1008ac8a
-           - handle_request[common/usb_pd_protocol.c:1191]
-             - handle_data_request[common/usb_pd_protocol.c:798]
-        -> pd_task[common/usb_pd_protocol.c:2672] 1008c222
-        -> [annotation]
-    pd_send_request_msg.lto_priv.263 (56) [common/usb_pd_protocol.c:653] 1009a0b4
-        -> pd_send_request_msg.lto_priv.263[common/usb_pd_protocol.c:712] 1009a22e0
-```
-
-The `pd_task` uses 160 bytes on the stack and calls
-`pd_send_request_msg.lto_priv.263`.
-
-The callsites to the next function will be shown like below,
-
-```
--> pd_task[common/usb_pd_protocol.c:1808] 1008ac8a
-   - handle_request[common/usb_pd_protocol.c:1191]
-     - handle_data_request[common/usb_pd_protocol.c:798]
--> pd_task[common/usb_pd_protocol.c:2672] 1008c222
--> [annotation]
-```
-
-This means one callsite to the next function is at `usb_pd_protocol.c:798`, but
-it is inlined to the current function and you can follow the trace:
-`usb_pd_protocol.c:1808 -> usb_pd_protocol.c:1191 -> usb_pd_protocol.c:798` to
-find the callsite. The second callsite is at `usb_pd_protocol.c:2672`. And the
-third one is added by annotation.
-
-The unresolved indirect callsites have the similar format to the above.
-
-## Annotating Indirect Call
-
-To annotate an indirect call like this,
-
-```
-Unresolved indirect callsites:
-    pd_transmit
-        -> pd_transmit[common/usb_pd_protocol.c:407] 802c9c8
-           - tcpm_transmit[driver/tcpm/tcpm.h:142]
-```
-
-It is an indirect call in the `tcpm_transmit`, which is inlined to the
-`pd_transmit`.
-
-You can add a annotation like the below to eliminate it.
-
-```
-add:
-  tcpm_transmit[driver/tcpm/tcpm.h:142]:
-  - anx74xx_tcpm_transmit
-```
-
-The source `tcpm_transmit[driver/tcpm/tcpm.h:142]` must be a full signature
-(function_name[path:line number]). So the resolver can know which indirect call
-you want to annotate and eliminate (even if it is inlined).
-
-## Annotating arrays (hooks, console commands, host commands)
-
-When a callsite calls a number of functions based on values from an constant
-array (in `.rodata` section), one can use the following syntax:
-
-```
-  hook_task[common/hooks.c:197]:
-    - { name: __deferred_funcs, stride: 4, offset: 0 }
-    - { name: __hooks_second, stride: 8, offset: 0 }
-    - { name: __hooks_tick, stride: 8, offset: 0 }
-```
-
-Where `name` is the symbol name for the start of the array (the end of the array
-is `<name>_end`), stride is the array element size, and offset is the offset of
-the function pointer in the structure. For example, above, `__deferred_funcs` is
-a simple array of function pointers, while `__hooks_tick` is an array of `struct
-hook_data` (size 8, pointer at offset 0):
-
-```
-struct hook_data {
-        /* Hook processing routine. */
-        void (*routine)(void);
-        /* Priority; low numbers = higher priority. */
-        int priority;
-};
-```
diff --git a/extra/stack_analyzer/example_annotation.yaml b/extra/stack_analyzer/example_annotation.yaml
deleted file mode 100644
index 084fabc2d1..0000000000
--- a/extra/stack_analyzer/example_annotation.yaml
+++ /dev/null
@@ -1,44 +0,0 @@
-# Size of extra stack frame needed by exception context switch.
-exception_frame_size: 64
-
-# Add some missing calls.
-add:
-  # console_task also calls command_display_accel_info and command_accel_init.
-  console_task:
-  - command_display_accel_info
-  - command_accel_init
-
-  # Function name can be followed by [source code path] to indicate where is it
-  # declared (there may be several functions with the same name).
-  motion_lid_calc[common/motion_lid.c]:
-  - get_range[driver/accel_kionix.c]
-
-  # The full signature (function name[path:line number]) can be used to
-  # eliminate the indirect call (see README.md).
-  tcpm_transmit[driver/tcpm/tcpm.h:142]:
-  - anx74xx_tcpm_transmit
-
-# Remove some call paths.
-remove:
-# Remove all callsites pointing to panic_assert_fail.
-- panic_assert_fail
-- panic
-- [software_panic]
-# Remove some invalid paths.
-- [pd_send_request_msg, set_state, pd_power_supply_reset]
-- [__tx_char, __tx_char]
-- [set_state, set_state, set_state]
-
-# Remove two invalid paths with the common prefix.
-- [pd_execute_hard_reset, set_state, [charge_manager_update_dualrole, pd_dfp_exit_mode]]
-# It is equivalent to the following two lines,
-# - [pd_execute_hard_reset, set_state, charge_manager_update_dualrole]
-# - [pd_execute_hard_reset, set_state, pd_dfp_exit_mode]
-
-# Remove four invalid paths with the common segment.
-- [[pd_send_request_msg, pd_request_vconn_swap], set_state, [usb_mux_set, pd_power_supply_reset]]
-# It is equivalent to the following four lines,
-# - [pd_send_request_msg, set_state, usb_mux_set]
-# - [pd_send_request_msg, set_state, pd_power_supply_reset]
-# - [pd_request_vconn_swap, set_state, usb_mux_set]
-# - [pd_request_vconn_swap, set_state, pd_power_supply_reset]
diff --git a/extra/stack_analyzer/run_tests.sh b/extra/stack_analyzer/run_tests.sh
deleted file mode 100755
index 5662f60b8b..0000000000
--- a/extra/stack_analyzer/run_tests.sh
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Discover all the unit tests in extra/stack_analyzer directory and run them.
-python3 -m unittest discover -b -s extra/stack_analyzer -p "*_unittest.py"  \
-    && touch extra/stack_analyzer/.tests-passed
diff --git a/extra/stack_analyzer/stack_analyzer.py b/extra/stack_analyzer/stack_analyzer.py
deleted file mode 100755
index 77d16d5450..0000000000
--- a/extra/stack_analyzer/stack_analyzer.py
+++ /dev/null
@@ -1,1872 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Statically analyze stack usage of EC firmware.
-
-  Example:
-    extra/stack_analyzer/stack_analyzer.py \
-        --export_taskinfo ./build/elm/util/export_taskinfo.so \
-        --section RW \
-        ./build/elm/RW/ec.RW.elf
-
-"""
-
-from __future__ import print_function
-
-import argparse
-import collections
-import ctypes
-import os
-import re
-import subprocess
-import yaml
-
-
-SECTION_RO = 'RO'
-SECTION_RW = 'RW'
-# Default size of extra stack frame needed by exception context switch.
-# This value is for cortex-m with FPU enabled.
-DEFAULT_EXCEPTION_FRAME_SIZE = 224
-
-
-class StackAnalyzerError(Exception):
-  """Exception class for stack analyzer utility."""
-
-
-class TaskInfo(ctypes.Structure):
-  """Taskinfo ctypes structure.
-
-  The structure definition is corresponding to the "struct taskinfo"
-  in "util/export_taskinfo.so.c".
-  """
-  _fields_ = [('name', ctypes.c_char_p),
-              ('routine', ctypes.c_char_p),
-              ('stack_size', ctypes.c_uint32)]
-
-
-class Task(object):
-  """Task information.
-
-  Attributes:
-    name: Task name.
-    routine_name: Routine function name.
-    stack_max_size: Max stack size.
-    routine_address: Resolved routine address. None if it hasn't been resolved.
-  """
-
-  def __init__(self, name, routine_name, stack_max_size, routine_address=None):
-    """Constructor.
-
-    Args:
-      name: Task name.
-      routine_name: Routine function name.
-      stack_max_size: Max stack size.
-      routine_address: Resolved routine address.
-    """
-    self.name = name
-    self.routine_name = routine_name
-    self.stack_max_size = stack_max_size
-    self.routine_address = routine_address
-
-  def __eq__(self, other):
-    """Task equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Task):
-      return False
-
-    return (self.name == other.name and
-            self.routine_name == other.routine_name and
-            self.stack_max_size == other.stack_max_size and
-            self.routine_address == other.routine_address)
-
-
-class Symbol(object):
-  """Symbol information.
-
-  Attributes:
-    address: Symbol address.
-    symtype: Symbol type, 'O' (data, object) or 'F' (function).
-    size: Symbol size.
-    name: Symbol name.
-  """
-
-  def __init__(self, address, symtype, size, name):
-    """Constructor.
-
-    Args:
-      address: Symbol address.
-      symtype: Symbol type.
-      size: Symbol size.
-      name: Symbol name.
-    """
-    assert symtype in ['O', 'F']
-    self.address = address
-    self.symtype = symtype
-    self.size = size
-    self.name = name
-
-  def __eq__(self, other):
-    """Symbol equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Symbol):
-      return False
-
-    return (self.address == other.address and
-            self.symtype == other.symtype and
-            self.size == other.size and
-            self.name == other.name)
-
-
-class Callsite(object):
-  """Function callsite.
-
-  Attributes:
-    address: Address of callsite location. None if it is unknown.
-    target: Callee address. None if it is unknown.
-    is_tail: A bool indicates that it is a tailing call.
-    callee: Resolved callee function. None if it hasn't been resolved.
-  """
-
-  def __init__(self, address, target, is_tail, callee=None):
-    """Constructor.
-
-    Args:
-      address: Address of callsite location. None if it is unknown.
-      target: Callee address. None if it is unknown.
-      is_tail: A bool indicates that it is a tailing call. (function jump to
-               another function without restoring the stack frame)
-      callee: Resolved callee function.
-    """
-    # It makes no sense that both address and target are unknown.
-    assert not (address is None and target is None)
-    self.address = address
-    self.target = target
-    self.is_tail = is_tail
-    self.callee = callee
-
-  def __eq__(self, other):
-    """Callsite equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Callsite):
-      return False
-
-    if not (self.address == other.address and
-            self.target == other.target and
-            self.is_tail == other.is_tail):
-      return False
-
-    if self.callee is None:
-      return other.callee is None
-    elif other.callee is None:
-      return False
-
-    # Assume the addresses of functions are unique.
-    return self.callee.address == other.callee.address
-
-
-class Function(object):
-  """Function.
-
-  Attributes:
-    address: Address of function.
-    name: Name of function from its symbol.
-    stack_frame: Size of stack frame.
-    callsites: Callsite list.
-    stack_max_usage: Max stack usage. None if it hasn't been analyzed.
-    stack_max_path: Max stack usage path. None if it hasn't been analyzed.
-  """
-
-  def __init__(self, address, name, stack_frame, callsites):
-    """Constructor.
-
-    Args:
-      address: Address of function.
-      name: Name of function from its symbol.
-      stack_frame: Size of stack frame.
-      callsites: Callsite list.
-    """
-    self.address = address
-    self.name = name
-    self.stack_frame = stack_frame
-    self.callsites = callsites
-    self.stack_max_usage = None
-    self.stack_max_path = None
-
-  def __eq__(self, other):
-    """Function equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Function):
-      return False
-
-    if not (self.address == other.address and
-            self.name == other.name and
-            self.stack_frame == other.stack_frame and
-            self.callsites == other.callsites and
-            self.stack_max_usage == other.stack_max_usage):
-      return False
-
-    if self.stack_max_path is None:
-      return other.stack_max_path is None
-    elif other.stack_max_path is None:
-      return False
-
-    if len(self.stack_max_path) != len(other.stack_max_path):
-      return False
-
-    for self_func, other_func in zip(self.stack_max_path, other.stack_max_path):
-      # Assume the addresses of functions are unique.
-      if self_func.address != other_func.address:
-        return False
-
-    return True
-
-  def __hash__(self):
-    return id(self)
-
-class AndesAnalyzer(object):
-  """Disassembly analyzer for Andes architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = [ 'eq', 'eqz', 'gez', 'gtz', 'lez', 'ltz', 'ne', 'nez',
-                      'eqc', 'nec', 'nezs', 'nes', 'eqs']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$' \
-                  .format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile \
-                  (r'^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$')
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lp register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile \
-                  (r'^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$')
-  # TODO: Handle other kinds of store instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push(\d{1,})$')
-  PUSH_OPERAND_RE = re.compile(r'^\$r\d{1,}, \#\d{1,}    \! \{([^\]]+)\}')
-  SMW_OPCODE_RE = re.compile(r'^smw(\.\w\w|\.\w\w\w)$')
-  SMW_OPERAND_RE = re.compile(r'^(\$r\d{1,}|\$\wp), \[\$\wp\], '
-                   r'(\$r\d{1,}|\$\wp), \#\d\w\d    \! \{([^\]]+)\}')
-  OPERANDGROUP_RE = re.compile(r'^\$r\d{1,}\~\$r\d{1,}')
-
-  LWI_OPCODE_RE = re.compile(r'^lwi(\.\w\w)$')
-  LWI_PC_OPERAND_RE = re.compile(r'^\$pc, \[([^\]]+)\]')
-  # Example: "34280:  3f c8 0f ec   addi.gp $fp, #0xfec"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+'
-                    r'(?P<words>[0-9A-Fa-f ]+)'
-                    r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
-
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, words, opcode, operand_text): The instruction address, words,
-                                        opcode, and the text of operands.
-                                        None if it isn't an instruction line.
-    """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    words = result.group('words')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, words, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-
-    stack_frame = 0
-    callsites = []
-    for address, words, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-
-      if is_jump_opcode or is_call_opcode:
-        is_tail = is_jump_opcode
-
-        result = self.CALL_OPERAND_RE.match(operand_text)
-
-        if result is None:
-          if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
-        else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LWI_OPCODE_RE.match(opcode) is not None:
-        result = self.LWI_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "lwi $pc, [$sp], xx" because it's usually a return.
-          if result.group(1) != '$sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: fc 20    push25 $r8, #0    ! {$r6~$r8, $fp, $gp, $lp}
-        if self.PUSH_OPERAND_RE.match(operand_text) is not None:
-          # capture fc 20
-          imm5u = int(words.split(' ')[1], 16)
-          # sp = sp - (imm5u << 3)
-          imm8u = (imm5u<<3) & 0xff
-          stack_frame += imm8u
-
-          result = self.PUSH_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(1)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-      elif self.SMW_OPCODE_RE.match(opcode) is not None:
-        # Example: smw.adm $r6, [$sp], $r10, #0x2    ! {$r6~$r10, $lp}
-        if self.SMW_OPERAND_RE.match(operand_text) is not None:
-          result = self.SMW_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(3)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-    return (stack_frame, callsites)
-
-class ArmAnalyzer(object):
-  """Disassembly analyzer for ARM architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = ['', 'eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl', 'vs',
-                     'vc', 'hi', 'ls', 'ge', 'lt', 'gt', 'le']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-  # Assume there is no function name containing ">".
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-
-  # Fuzzy regular expressions for instruction and operand parsing.
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(
-      r'^(b{0}|bx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile(
-      r'^(bl{0}|blx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  CBZ_CBNZ_OPCODE_RE = re.compile(r'^(cbz|cbnz)(\.\w)?$')
-  # Example: "r0, 1009bcbe <host_cmd_motion_sense+0x1d2>"
-  CBZ_CBNZ_OPERAND_RE = re.compile(r'^[^,]+,\s+{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lr register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile(r'^r\d+|sb|sl|fp|ip|sp|pc$')
-  # TODO(cheyuw): Handle conditional versions of following
-  #               instructions.
-  # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc).
-  LDR_OPCODE_RE = re.compile(r'^ldr(\.\w)?$')
-  # Example: "pc, [sp], #4"
-  LDR_PC_OPERAND_RE = re.compile(r'^pc, \[([^\]]+)\]')
-  # TODO(cheyuw): Handle other kinds of stm instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push$')
-  STM_OPCODE_RE = re.compile(r'^stmdb$')
-  # Stack subtraction instructions.
-  SUB_OPCODE_RE = re.compile(r'^sub(s|w)?(\.\w)?$')
-  SUB_OPERAND_RE = re.compile(r'^sp[^#]+#(\d+)')
-  # Example: "44d94:  f893 0068   ldrb.w  r0, [r3, #104]  ; 0x68"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+'
-                               r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
-
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, opcode, operand_text): The instruction address, opcode,
-                                       and the text of operands. None if it
-                                       isn't an instruction line.
-    """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-    """Analyze function, resolve the size of stack frame and callsites.
-
-    Args:
-      function_symbol: Function symbol.
-      instructions: Instruction list.
-
-    Returns:
-      (stack_frame, callsites): Size of stack frame, callsite list.
-    """
-    stack_frame = 0
-    callsites = []
-    for address, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-      is_cbz_cbnz_opcode = self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None
-      if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode:
-        is_tail = is_jump_opcode or is_cbz_cbnz_opcode
-
-        if is_cbz_cbnz_opcode:
-          result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text)
-        else:
-          result = self.CALL_OPERAND_RE.match(operand_text)
-
-        if result is None:
-          # Failed to match immediate address, maybe it is an indirect call.
-          # CBZ and CBNZ can't be indirect calls.
-          if (not is_cbz_cbnz_opcode and
-              self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
-        else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LDR_OPCODE_RE.match(opcode) is not None:
-        result = self.LDR_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "ldr pc, [sp], xx" because it's usually a return.
-          if result.group(1) != 'sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: "{r4, r5, r6, r7, lr}"
-        stack_frame += (len(operand_text.split(',')) *
-                        self.GENERAL_PURPOSE_REGISTER_SIZE)
-      elif self.SUB_OPCODE_RE.match(opcode) is not None:
-        result = self.SUB_OPERAND_RE.match(operand_text)
-        if result is not None:
-          stack_frame += int(result.group(1))
-        else:
-          # Unhandled stack register subtraction.
-          assert not operand_text.startswith('sp')
-
-      elif self.STM_OPCODE_RE.match(opcode) is not None:
-        if operand_text.startswith('sp!'):
-          # Subtract and writeback to stack register.
-          # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}"
-          # Get the text of pushed register list.
-          unused_sp, unused_sep, parameter_text = operand_text.partition(',')
-          stack_frame += (len(parameter_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-    return (stack_frame, callsites)
-
-class RiscvAnalyzer(object):
-  """Disassembly analyzer for RISC-V architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = [ 'eqz', 'nez', 'lez', 'gez', 'ltz', 'gtz', 'gt', 'le',
-                      'gtu', 'leu', 'eq', 'ne', 'ge', 'lt', 'ltu', 'geu']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr)$'.format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile(r'^(jal|jalr)$')
-  # Example: "j		8009b318 <set_state_prl_hr>" or
-  #          "jal	ra,800a4394 <power_get_signals>" or
-  #          "bltu	t0,t1,80080300 <data_loop>"
-  JUMP_ADDRESS_RE = r'((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>'
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(JUMP_ADDRESS_RE))
-  # Capture address, Example:  800a4394
-  CAPTURE_ADDRESS = re.compile(r'[0-9A-Fa-f]{8}')
-  # Indirect jump, Example: jalr	a5
-  INDIRECT_CALL_OPERAND_RE = re.compile(r'^t\d+|s\d+|a\d+$')
-  # Example:  addi
-  ADDI_OPCODE_RE = re.compile(r'^addi$')
-  # Allocate stack instructions.
-  ADDI_OPERAND_RE = re.compile(r'^(sp,sp,-\d+)$')
-  # Example: "800804b6:	1101                	addi	sp,sp,-32"
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+'
-                               r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
-
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, opcode, operand_text):  The instruction address, opcode,
-                                        and the text of operands. None if it
-                                        isn't an instruction line.
-    """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-
-    stack_frame = 0
-    callsites = []
-    for address, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-
-      if is_jump_opcode or is_call_opcode:
-        is_tail = is_jump_opcode
-
-        result = self.CALL_OPERAND_RE.match(operand_text)
-        if result is None:
-          if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
-        else:
-          # Capture address form operand_text and then convert to string
-          address_str = "".join(self.CAPTURE_ADDRESS.findall(operand_text))
-          # String to integer
-          target_address = int(address_str, 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.ADDI_OPCODE_RE.match(opcode) is not None:
-      	# Example: sp,sp,-32
-        if self.ADDI_OPERAND_RE.match(operand_text) is not None:
-            stack_frame += abs(int(operand_text.split(",")[2]))
-
-    return (stack_frame, callsites)
-
-class StackAnalyzer(object):
-  """Class to analyze stack usage.
-
-  Public Methods:
-    Analyze: Run the stack analysis.
-  """
-
-  C_FUNCTION_NAME = r'_A-Za-z0-9'
-
-  # Assume there is no ":" in the path.
-  # Example: "driver/accel_kionix.c:321 (discriminator 3)"
-  ADDRTOLINE_RE = re.compile(
-      r'^(?P<path>[^:]+):(?P<linenum>\d+)(\s+\(discriminator\s+\d+\))?$')
-  # To eliminate the suffix appended by compilers, try to extract the
-  # C function name from the prefix of symbol name.
-  # Example: "SHA256_transform.constprop.28"
-  FUNCTION_PREFIX_NAME_RE = re.compile(
-      r'^(?P<name>[{0}]+)([^{0}].*)?$'.format(C_FUNCTION_NAME))
-
-  # Errors of annotation resolving.
-  ANNOTATION_ERROR_INVALID = 'invalid signature'
-  ANNOTATION_ERROR_NOTFOUND = 'function is not found'
-  ANNOTATION_ERROR_AMBIGUOUS = 'signature is ambiguous'
-
-  def __init__(self, options, symbols, rodata, tasklist, annotation):
-    """Constructor.
-
-    Args:
-      options: Namespace from argparse.parse_args().
-      symbols: Symbol list.
-      rodata: Content of .rodata section (offset, data)
-      tasklist: Task list.
-      annotation: Annotation config.
-    """
-    self.options = options
-    self.symbols = symbols
-    self.rodata_offset = rodata[0]
-    self.rodata = rodata[1]
-    self.tasklist = tasklist
-    self.annotation = annotation
-    self.address_to_line_cache = {}
-
-  def AddressToLine(self, address, resolve_inline=False):
-    """Convert address to line.
-
-    Args:
-      address: Target address.
-      resolve_inline: Output the stack of inlining.
-
-    Returns:
-      lines: List of the corresponding lines.
-
-    Raises:
-      StackAnalyzerError: If addr2line is failed.
-    """
-    cache_key = (address, resolve_inline)
-    if cache_key in self.address_to_line_cache:
-      return self.address_to_line_cache[cache_key]
-
-    try:
-      args = [self.options.addr2line,
-              '-f',
-              '-e',
-              self.options.elf_path,
-              '{:x}'.format(address)]
-      if resolve_inline:
-        args.append('-i')
-
-      line_text = subprocess.check_output(args, encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('addr2line failed to resolve lines.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run addr2line.')
-
-    lines = [line.strip() for line in line_text.splitlines()]
-    # Assume the output has at least one pair like "function\nlocation\n", and
-    # they always show up in pairs.
-    # Example: "handle_request\n
-    #           common/usb_pd_protocol.c:1191\n"
-    assert len(lines) >= 2 and len(lines) % 2 == 0
-
-    line_infos = []
-    for index in range(0, len(lines), 2):
-      (function_name, line_text) = lines[index:index + 2]
-      if line_text in ['??:0', ':?']:
-        line_infos.append(None)
-      else:
-        result = self.ADDRTOLINE_RE.match(line_text)
-        # Assume the output is always well-formed.
-        assert result is not None
-        line_infos.append((function_name.strip(),
-                           os.path.realpath(result.group('path').strip()),
-                           int(result.group('linenum'))))
-
-    self.address_to_line_cache[cache_key] = line_infos
-    return line_infos
-
-  def AnalyzeDisassembly(self, disasm_text):
-    """Parse the disassembly text, analyze, and build a map of all functions.
-
-    Args:
-      disasm_text: Disassembly text.
-
-    Returns:
-      function_map: Dict of functions.
-    """
-    disasm_lines = [line.strip() for line in disasm_text.splitlines()]
-
-    if 'nds' in disasm_lines[1]:
-      analyzer = AndesAnalyzer()
-    elif 'arm' in disasm_lines[1]:
-      analyzer = ArmAnalyzer()
-    elif 'riscv' in disasm_lines[1]:
-      analyzer = RiscvAnalyzer()
-    else:
-      raise StackAnalyzerError('Unsupported architecture.')
-
-    # Example: "08028c8c <motion_lid_calc>:"
-    function_signature_regex = re.compile(
-        r'^(?P<address>[0-9A-Fa-f]+)\s+<(?P<name>[^>]+)>:$')
-
-    def DetectFunctionHead(line):
-      """Check if the line is a function head.
-
-      Args:
-        line: Text of disassembly.
-
-      Returns:
-        symbol: Function symbol. None if it isn't a function head.
-      """
-      result = function_signature_regex.match(line)
-      if result is None:
-        return None
-
-      address = int(result.group('address'), 16)
-      symbol = symbol_map.get(address)
-
-      # Check if the function exists and matches.
-      if symbol is None or symbol.symtype != 'F':
-        return None
-
-      return symbol
-
-    # Build symbol map, indexed by symbol address.
-    symbol_map = {}
-    for symbol in self.symbols:
-      # If there are multiple symbols with same address, keeping any of them is
-      # good enough.
-      symbol_map[symbol.address] = symbol
-
-    # Parse the disassembly text. We update the variable "line" to next line
-    # when needed. There are two steps of parser:
-    #
-    # Step 1: Searching for the function head. Once reach the function head,
-    # move to the next line, which is the first line of function body.
-    #
-    # Step 2: Parsing each instruction line of function body. Once reach a
-    # non-instruction line, stop parsing and analyze the parsed instructions.
-    #
-    # Finally turn back to the step 1 without updating the line, because the
-    # current non-instruction line can be another function head.
-    function_map = {}
-    # The following three variables are the states of the parsing processing.
-    # They will be initialized properly during the state changes.
-    function_symbol = None
-    function_end = None
-    instructions = []
-
-    # Remove heading and tailing spaces for each line.
-    line_index = 0
-    while line_index < len(disasm_lines):
-      # Get the current line.
-      line = disasm_lines[line_index]
-
-      if function_symbol is None:
-        # Step 1: Search for the function head.
-
-        function_symbol = DetectFunctionHead(line)
-        if function_symbol is not None:
-          # Assume there is no empty function. If the function head is followed
-          # by EOF, it is an empty function.
-          assert line_index + 1 < len(disasm_lines)
-
-          # Found the function head, initialize and turn to the step 2.
-          instructions = []
-          # If symbol size exists, use it as a hint of function size.
-          if function_symbol.size > 0:
-            function_end = function_symbol.address + function_symbol.size
-          else:
-            function_end = None
-
-      else:
-        # Step 2: Parse the function body.
-
-        instruction = analyzer.ParseInstruction(line, function_end)
-        if instruction is not None:
-          instructions.append(instruction)
-
-        if instruction is None or line_index + 1 == len(disasm_lines):
-          # Either the invalid instruction or EOF indicates the end of the
-          # function, finalize the function analysis.
-
-          # Assume there is no empty function.
-          assert len(instructions) > 0
-
-          (stack_frame, callsites) = analyzer.AnalyzeFunction(function_symbol,
-                                                              instructions)
-          # Assume the function addresses are unique in the disassembly.
-          assert function_symbol.address not in function_map
-          function_map[function_symbol.address] = Function(
-              function_symbol.address,
-              function_symbol.name,
-              stack_frame,
-              callsites)
-
-          # Initialize and turn back to the step 1.
-          function_symbol = None
-
-          # If the current line isn't an instruction, it can be another function
-          # head, skip moving to the next line.
-          if instruction is None:
-            continue
-
-      # Move to the next line.
-      line_index += 1
-
-    # Resolve callees of functions.
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          # Remain the callee as None if we can't resolve it.
-          callsite.callee = function_map.get(callsite.target)
-
-    return function_map
-
-  def MapAnnotation(self, function_map, signature_set):
-    """Map annotation signatures to functions.
-
-    Args:
-      function_map: Function map.
-      signature_set: Set of annotation signatures.
-
-    Returns:
-      Map of signatures to functions, map of signatures which can't be resolved.
-    """
-    # Build the symbol map indexed by symbol name. If there are multiple symbols
-    # with the same name, add them into a set. (e.g. symbols of static function
-    # with the same name)
-    symbol_map = collections.defaultdict(set)
-    for symbol in self.symbols:
-      if symbol.symtype == 'F':
-        # Function symbol.
-        result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-        if result is not None:
-          function = function_map.get(symbol.address)
-          # Ignore the symbol not in disassembly.
-          if function is not None:
-            # If there are multiple symbol with the same name and point to the
-            # same function, the set will deduplicate them.
-            symbol_map[result.group('name').strip()].add(function)
-
-    # Build the signature map indexed by annotation signature.
-    signature_map = {}
-    sig_error_map = {}
-    symbol_path_map = {}
-    for sig in signature_set:
-      (name, path, _) = sig
-
-      functions = symbol_map.get(name)
-      if functions is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
-
-      if name not in symbol_path_map:
-        # Lazy symbol path resolving. Since the addr2line isn't fast, only
-        # resolve needed symbol paths.
-        group_map = collections.defaultdict(list)
-        for function in functions:
-          line_info = self.AddressToLine(function.address)[0]
-          if line_info is None:
-            continue
-
-          (_, symbol_path, _) = line_info
-
-          # Group the functions with the same symbol signature (symbol name +
-          # symbol path). Assume they are the same copies and do the same
-          # annotation operations of them because we don't know which copy is
-          # indicated by the users.
-          group_map[symbol_path].append(function)
-
-        symbol_path_map[name] = group_map
-
-      # Symbol matching.
-      function_group = None
-      group_map = symbol_path_map[name]
-      if len(group_map) > 0:
-        if path is None:
-          if len(group_map) > 1:
-            # There is ambiguity but the path isn't specified.
-            sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS
-            continue
-
-          # No path signature but all symbol signatures of functions are same.
-          # Assume they are the same functions, so there is no ambiguity.
-          (function_group,) = group_map.values()
-        else:
-          function_group = group_map.get(path)
-
-      if function_group is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
-
-      # The function_group is a list of all the same functions (according to
-      # our assumption) which should be annotated together.
-      signature_map[sig] = function_group
-
-    return (signature_map, sig_error_map)
-
-  def LoadAnnotation(self):
-    """Load annotation rules.
-
-    Returns:
-      Map of add rules, set of remove rules, set of text signatures which can't
-      be parsed.
-    """
-    # Assume there is no ":" in the path.
-    # Example: "get_range.lto.2501[driver/accel_kionix.c:327]"
-    annotation_signature_regex = re.compile(
-        r'^(?P<name>[^\[]+)(\[(?P<path>[^:]+)(:(?P<linenum>\d+))?\])?$')
-
-    def NormalizeSignature(signature_text):
-      """Parse and normalize the annotation signature.
-
-      Args:
-        signature_text: Text of the annotation signature.
-
-      Returns:
-        (function name, path, line number) of the signature. The path and line
-        number can be None if not exist. None if failed to parse.
-      """
-      result = annotation_signature_regex.match(signature_text.strip())
-      if result is None:
-        return None
-
-      name_result = self.FUNCTION_PREFIX_NAME_RE.match(
-          result.group('name').strip())
-      if name_result is None:
-        return None
-
-      path = result.group('path')
-      if path is not None:
-        path = os.path.realpath(path.strip())
-
-      linenum = result.group('linenum')
-      if linenum is not None:
-        linenum = int(linenum.strip())
-
-      return (name_result.group('name').strip(), path, linenum)
-
-    def ExpandArray(dic):
-      """Parse and expand a symbol array
-
-      Args:
-        dic: Dictionary for the array annotation
-
-      Returns:
-        array of (symbol name, None, None).
-      """
-      # TODO(drinkcat): This function is quite inefficient, as it goes through
-      # the symbol table multiple times.
-
-      begin_name = dic['name']
-      end_name = dic['name'] + "_end"
-      offset = dic['offset'] if 'offset' in dic else 0
-      stride = dic['stride']
-
-      begin_address = None
-      end_address = None
-
-      for symbol in self.symbols:
-        if (symbol.name == begin_name):
-          begin_address = symbol.address
-        if (symbol.name == end_name):
-          end_address = symbol.address
-
-      if (not begin_address or not end_address):
-        return None
-
-      output = []
-      # TODO(drinkcat): This is inefficient as we go from address to symbol
-      # object then to symbol name, and later on we'll go back from symbol name
-      # to symbol object.
-      for addr in range(begin_address+offset, end_address, stride):
-        # TODO(drinkcat): Not all architectures need to drop the first bit.
-        val = self.rodata[(addr-self.rodata_offset) // 4] & 0xfffffffe
-        name = None
-        for symbol in self.symbols:
-          if (symbol.address == val):
-            result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-            name = result.group('name')
-            break
-
-        if not name:
-          raise StackAnalyzerError('Cannot find function for address %s.',
-                                   hex(val))
-
-        output.append((name, None, None))
-
-      return output
-
-    add_rules = collections.defaultdict(set)
-    remove_rules = list()
-    invalid_sigtxts = set()
-
-    if 'add' in self.annotation and self.annotation['add'] is not None:
-      for src_sigtxt, dst_sigtxts in self.annotation['add'].items():
-        src_sig = NormalizeSignature(src_sigtxt)
-        if src_sig is None:
-          invalid_sigtxts.add(src_sigtxt)
-          continue
-
-        for dst_sigtxt in dst_sigtxts:
-          if isinstance(dst_sigtxt, dict):
-            dst_sig = ExpandArray(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(str(dst_sigtxt))
-            else:
-              add_rules[src_sig].update(dst_sig)
-          else:
-            dst_sig = NormalizeSignature(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(dst_sigtxt)
-            else:
-              add_rules[src_sig].add(dst_sig)
-
-    if 'remove' in self.annotation and self.annotation['remove'] is not None:
-      for sigtxt_path in self.annotation['remove']:
-        if isinstance(sigtxt_path, str):
-          # The path has only one vertex.
-          sigtxt_path = [sigtxt_path]
-
-        if len(sigtxt_path) == 0:
-          continue
-
-        # Generate multiple remove paths from all the combinations of the
-        # signatures of each vertex.
-        sig_paths = [[]]
-        broken_flag = False
-        for sigtxt_node in sigtxt_path:
-          if isinstance(sigtxt_node, str):
-            # The vertex has only one signature.
-            sigtxt_set = {sigtxt_node}
-          elif isinstance(sigtxt_node, list):
-            # The vertex has multiple signatures.
-            sigtxt_set = set(sigtxt_node)
-          else:
-            # Assume the format of annotation is verified. There should be no
-            # invalid case.
-            assert False
-
-          sig_set = set()
-          for sigtxt in sigtxt_set:
-            sig = NormalizeSignature(sigtxt)
-            if sig is None:
-              invalid_sigtxts.add(sigtxt)
-              broken_flag = True
-            elif not broken_flag:
-              sig_set.add(sig)
-
-          if broken_flag:
-            continue
-
-          # Append each signature of the current node to the all previous
-          # remove paths.
-          sig_paths = [path + [sig] for path in sig_paths for sig in sig_set]
-
-        if not broken_flag:
-          # All signatures are normalized. The remove path has no error.
-          remove_rules.extend(sig_paths)
-
-    return (add_rules, remove_rules, invalid_sigtxts)
-
-  def ResolveAnnotation(self, function_map):
-    """Resolve annotation.
-
-    Args:
-      function_map: Function map.
-
-    Returns:
-      Set of added call edges, list of remove paths, set of eliminated
-      callsite addresses, set of annotation signatures which can't be resolved.
-    """
-    def StringifySignature(signature):
-      """Stringify the tupled signature.
-
-      Args:
-        signature: Tupled signature.
-
-      Returns:
-        Signature string.
-      """
-      (name, path, linenum) = signature
-      bracket_text = ''
-      if path is not None:
-        path = os.path.relpath(path)
-        if linenum is None:
-          bracket_text = '[{}]'.format(path)
-        else:
-          bracket_text = '[{}:{}]'.format(path, linenum)
-
-      return name + bracket_text
-
-    (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation()
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    # Map signatures to functions.
-    (signature_map, sig_error_map) = self.MapAnnotation(function_map,
-                                                        signature_set)
-
-    # Build the indirect callsite map indexed by callsite signature.
-    indirect_map = collections.defaultdict(set)
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          continue
-
-        # Found an indirect callsite.
-        line_info = self.AddressToLine(callsite.address)[0]
-        if line_info is None:
-          continue
-
-        (name, path, linenum) = line_info
-        result = self.FUNCTION_PREFIX_NAME_RE.match(name)
-        if result is None:
-          continue
-
-        indirect_map[(result.group('name').strip(), path, linenum)].add(
-            (function, callsite.address))
-
-    # Generate the annotation sets.
-    add_set = set()
-    remove_list = list()
-    eliminated_addrs = set()
-
-    for src_sig, dst_sigs in add_rules.items():
-      src_funcs = set(signature_map.get(src_sig, []))
-      # Try to match the source signature to the indirect callsites. Even if it
-      # can't be found in disassembly.
-      indirect_calls = indirect_map.get(src_sig)
-      if indirect_calls is not None:
-        for function, callsite_address in indirect_calls:
-          # Add the caller of the indirect callsite to the source functions.
-          src_funcs.add(function)
-          # Assume each callsite can be represented by a unique address.
-          eliminated_addrs.add(callsite_address)
-
-        if src_sig in sig_error_map:
-          # Assume the error is always the not found error. Since the signature
-          # found in indirect callsite map must be a full signature, it can't
-          # happen the ambiguous error.
-          assert sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND
-          # Found in inline stack, remove the not found error.
-          del sig_error_map[src_sig]
-
-      for dst_sig in dst_sigs:
-        dst_funcs = signature_map.get(dst_sig)
-        if dst_funcs is None:
-          continue
-
-        # Duplicate the call edge for all the same source and destination
-        # functions.
-        for src_func in src_funcs:
-          for dst_func in dst_funcs:
-            add_set.add((src_func, dst_func))
-
-    for remove_sigs in remove_rules:
-      # Since each signature can be mapped to multiple functions, generate
-      # multiple remove paths from all the combinations of these functions.
-      remove_paths = [[]]
-      skip_flag = False
-      for remove_sig in remove_sigs:
-        # Transform each signature to the corresponding functions.
-        remove_funcs = signature_map.get(remove_sig)
-        if remove_funcs is None:
-          # There is an unresolved signature in the remove path. Ignore the
-          # whole broken remove path.
-          skip_flag = True
-          break
-        else:
-          # Append each function of the current signature to the all previous
-          # remove paths.
-          remove_paths = [p + [f] for p in remove_paths for f in remove_funcs]
-
-      if skip_flag:
-        # Ignore the broken remove path.
-        continue
-
-      for remove_path in remove_paths:
-        # Deduplicate the remove paths.
-        if remove_path not in remove_list:
-          remove_list.append(remove_path)
-
-    # Format the error messages.
-    failed_sigtxts = set()
-    for sigtxt in invalid_sigtxts:
-      failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID))
-
-    for sig, error in sig_error_map.items():
-      failed_sigtxts.add((StringifySignature(sig), error))
-
-    return (add_set, remove_list, eliminated_addrs, failed_sigtxts)
-
-  def PreprocessAnnotation(self, function_map, add_set, remove_list,
-                           eliminated_addrs):
-    """Preprocess the annotation and callgraph.
-
-    Add the missing call edges, and delete simple remove paths (the paths have
-    one or two vertices) from the function_map.
-
-    Eliminate the annotated indirect callsites.
-
-    Return the remaining remove list.
-
-    Args:
-      function_map: Function map.
-      add_set: Set of missing call edges.
-      remove_list: List of remove paths.
-      eliminated_addrs: Set of eliminated callsite addresses.
-
-    Returns:
-      List of remaining remove paths.
-    """
-    def CheckEdge(path):
-      """Check if all edges of the path are on the callgraph.
-
-      Args:
-        path: Path.
-
-      Returns:
-        True or False.
-      """
-      for index in range(len(path) - 1):
-        if (path[index], path[index + 1]) not in edge_set:
-          return False
-
-      return True
-
-    for src_func, dst_func in add_set:
-      # TODO(cheyuw): Support tailing call annotation.
-      src_func.callsites.append(
-          Callsite(None, dst_func.address, False, dst_func))
-
-    # Delete simple remove paths.
-    remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2)
-    edge_set = set()
-    for function in function_map.values():
-      cleaned_callsites = []
-      for callsite in function.callsites:
-        if ((callsite.callee,) in remove_simple or
-            (function, callsite.callee) in remove_simple):
-          continue
-
-        if callsite.target is None and callsite.address in eliminated_addrs:
-          continue
-
-        cleaned_callsites.append(callsite)
-        if callsite.callee is not None:
-          edge_set.add((function, callsite.callee))
-
-      function.callsites = cleaned_callsites
-
-    return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)]
-
-  def AnalyzeCallGraph(self, function_map, remove_list):
-    """Analyze callgraph.
-
-    It will update the max stack size and path for each function.
-
-    Args:
-      function_map: Function map.
-      remove_list: List of remove paths.
-
-    Returns:
-      List of function cycles.
-    """
-    def Traverse(curr_state):
-      """Traverse the callgraph and calculate the max stack usages of functions.
-
-      Args:
-        curr_state: Current state.
-
-      Returns:
-        SCC lowest link.
-      """
-      scc_index = scc_index_counter[0]
-      scc_index_counter[0] += 1
-      scc_index_map[curr_state] = scc_index
-      scc_lowlink = scc_index
-      scc_stack.append(curr_state)
-      # Push the current state in the stack. We can use a set to maintain this
-      # because the stacked states are unique; otherwise we will find a cycle
-      # first.
-      stacked_states.add(curr_state)
-
-      (curr_address, curr_positions) = curr_state
-      curr_func = function_map[curr_address]
-
-      invalid_flag = False
-      new_positions = list(curr_positions)
-      for index, position in enumerate(curr_positions):
-        remove_path = remove_list[index]
-
-        # The position of each remove path in the state is the length of the
-        # longest matching path between the prefix of the remove path and the
-        # suffix of the current traversing path. We maintain this length when
-        # appending the next callee to the traversing path. And it can be used
-        # to check if the remove path appears in the traversing path.
-
-        # TODO(cheyuw): Implement KMP algorithm to match remove paths
-        #               efficiently.
-        if remove_path[position] is curr_func:
-          # Matches the current function, extend the length.
-          new_positions[index] = position + 1
-          if new_positions[index] == len(remove_path):
-            # The length of the longest matching path is equal to the length of
-            # the remove path, which means the suffix of the current traversing
-            # path matches the remove path.
-            invalid_flag = True
-            break
-
-        else:
-          # We can't get the new longest matching path by extending the previous
-          # one directly. Fallback to search the new longest matching path.
-
-          # If we can't find any matching path in the following search, reset
-          # the matching length to 0.
-          new_positions[index] = 0
-
-          # We want to find the new longest matching prefix of remove path with
-          # the suffix of the current traversing path. Because the new longest
-          # matching path won't be longer than the prevous one now, and part of
-          # the suffix matches the prefix of remove path, we can get the needed
-          # suffix from the previous matching prefix of the invalid path.
-          suffix = remove_path[:position] + [curr_func]
-          for offset in range(1, len(suffix)):
-            length = position - offset
-            if remove_path[:length] == suffix[offset:]:
-              new_positions[index] = length
-              break
-
-      new_positions = tuple(new_positions)
-
-      # If the current suffix is invalid, set the max stack usage to 0.
-      max_stack_usage = 0
-      max_callee_state = None
-      self_loop = False
-
-      if not invalid_flag:
-        # Max stack usage is at least equal to the stack frame.
-        max_stack_usage = curr_func.stack_frame
-        for callsite in curr_func.callsites:
-          callee = callsite.callee
-          if callee is None:
-            continue
-
-          callee_state = (callee.address, new_positions)
-          if callee_state not in scc_index_map:
-            # Unvisited state.
-            scc_lowlink = min(scc_lowlink, Traverse(callee_state))
-          elif callee_state in stacked_states:
-            # The state is shown in the stack. There is a cycle.
-            sub_stack_usage = 0
-            scc_lowlink = min(scc_lowlink, scc_index_map[callee_state])
-            if callee_state == curr_state:
-              self_loop = True
-
-          done_result = done_states.get(callee_state)
-          if done_result is not None:
-            # Already done this state and use its result. If the state reaches a
-            # cycle, reusing the result will cause inaccuracy (the stack usage
-            # of cycle depends on where the entrance is). But it's fine since we
-            # can't get accurate stack usage under this situation, and we rely
-            # on user-provided annotations to break the cycle, after which the
-            # result will be accurate again.
-            (sub_stack_usage, _) = done_result
-
-            if callsite.is_tail:
-              # For tailing call, since the callee reuses the stack frame of the
-              # caller, choose the larger one directly.
-              stack_usage = max(curr_func.stack_frame, sub_stack_usage)
-            else:
-              stack_usage = curr_func.stack_frame + sub_stack_usage
-
-            if stack_usage > max_stack_usage:
-              max_stack_usage = stack_usage
-              max_callee_state = callee_state
-
-      if scc_lowlink == scc_index:
-        group = []
-        while scc_stack[-1] != curr_state:
-          scc_state = scc_stack.pop()
-          stacked_states.remove(scc_state)
-          group.append(scc_state)
-
-        scc_stack.pop()
-        stacked_states.remove(curr_state)
-
-        # If the cycle is not empty, record it.
-        if len(group) > 0 or self_loop:
-          group.append(curr_state)
-          cycle_groups.append(group)
-
-      # Store the done result.
-      done_states[curr_state] = (max_stack_usage, max_callee_state)
-
-      if curr_positions == initial_positions:
-        # If the current state is initial state, we traversed the callgraph by
-        # using the current function as start point. Update the stack usage of
-        # the function.
-        # If the function matches a single vertex remove path, this will set its
-        # max stack usage to 0, which is not expected (we still calculate its
-        # max stack usage, but prevent any function from calling it). However,
-        # all the single vertex remove paths have been preprocessed and removed.
-        curr_func.stack_max_usage = max_stack_usage
-
-        # Reconstruct the max stack path by traversing the state transitions.
-        max_stack_path = [curr_func]
-        callee_state = max_callee_state
-        while callee_state is not None:
-          # The first element of state tuple is function address.
-          max_stack_path.append(function_map[callee_state[0]])
-          done_result = done_states.get(callee_state)
-          # All of the descendants should be done.
-          assert done_result is not None
-          (_, callee_state) = done_result
-
-        curr_func.stack_max_path = max_stack_path
-
-      return scc_lowlink
-
-    # The state is the concatenation of the current function address and the
-    # state of matching position.
-    initial_positions = (0,) * len(remove_list)
-    done_states = {}
-    stacked_states = set()
-    scc_index_counter = [0]
-    scc_index_map = {}
-    scc_stack = []
-    cycle_groups = []
-    for function in function_map.values():
-      if function.stack_max_usage is None:
-        Traverse((function.address, initial_positions))
-
-    cycle_functions = []
-    for group in cycle_groups:
-      cycle = set(function_map[state[0]] for state in group)
-      if cycle not in cycle_functions:
-        cycle_functions.append(cycle)
-
-    return cycle_functions
-
-  def Analyze(self):
-    """Run the stack analysis.
-
-    Raises:
-      StackAnalyzerError: If disassembly fails.
-    """
-    def OutputInlineStack(address, prefix=''):
-      """Output beautiful inline stack.
-
-      Args:
-        address: Address.
-        prefix: Prefix of each line.
-
-      Returns:
-        Key for sorting, output text
-      """
-      line_infos = self.AddressToLine(address, True)
-
-      if line_infos[0] is None:
-        order_key = (None, None)
-      else:
-        (_, path, linenum) = line_infos[0]
-        order_key = (linenum, path)
-
-      line_texts = []
-      for line_info in reversed(line_infos):
-        if line_info is None:
-          (function_name, path, linenum) = ('??', '??', 0)
-        else:
-          (function_name, path, linenum) = line_info
-
-        line_texts.append('{}[{}:{}]'.format(function_name,
-                                             os.path.relpath(path),
-                                             linenum))
-
-      output = '{}-> {} {:x}\n'.format(prefix, line_texts[0], address)
-      for depth, line_text in enumerate(line_texts[1:]):
-        output += '{}   {}- {}\n'.format(prefix, '  ' * depth, line_text)
-
-      # Remove the last newline character.
-      return (order_key, output.rstrip('\n'))
-
-    # Analyze disassembly.
-    try:
-      disasm_text = subprocess.check_output([self.options.objdump,
-                                             '-d',
-                                             self.options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to disassemble.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    function_map = self.AnalyzeDisassembly(disasm_text)
-    result = self.ResolveAnnotation(function_map)
-    (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result
-    remove_list = self.PreprocessAnnotation(function_map,
-                                            add_set,
-                                            remove_list,
-                                            eliminated_addrs)
-    cycle_functions = self.AnalyzeCallGraph(function_map, remove_list)
-
-    # Print the results of task-aware stack analysis.
-    extra_stack_frame = self.annotation.get('exception_frame_size',
-                                            DEFAULT_EXCEPTION_FRAME_SIZE)
-    for task in self.tasklist:
-      routine_func = function_map[task.routine_address]
-      print('Task: {}, Max size: {} ({} + {}), Allocated size: {}'.format(
-          task.name,
-          routine_func.stack_max_usage + extra_stack_frame,
-          routine_func.stack_max_usage,
-          extra_stack_frame,
-          task.stack_max_size))
-
-      print('Call Trace:')
-      max_stack_path = routine_func.stack_max_path
-      # Assume the routine function is resolved.
-      assert max_stack_path is not None
-      for depth, curr_func in enumerate(max_stack_path):
-        line_info = self.AddressToLine(curr_func.address)[0]
-        if line_info is None:
-          (path, linenum) = ('??', 0)
-        else:
-          (_, path, linenum) = line_info
-
-        print('    {} ({}) [{}:{}] {:x}'.format(curr_func.name,
-                                                curr_func.stack_frame,
-                                                os.path.relpath(path),
-                                                linenum,
-                                                curr_func.address))
-
-        if depth + 1 < len(max_stack_path):
-          succ_func = max_stack_path[depth + 1]
-          text_list = []
-          for callsite in curr_func.callsites:
-            if callsite.callee is succ_func:
-              indent_prefix = '        '
-              if callsite.address is None:
-                order_text = (None, '{}-> [annotation]'.format(indent_prefix))
-              else:
-                order_text = OutputInlineStack(callsite.address, indent_prefix)
-
-              text_list.append(order_text)
-
-          for _, text in sorted(text_list, key=lambda item: item[0]):
-            print(text)
-
-    print('Unresolved indirect callsites:')
-    for function in function_map.values():
-      indirect_callsites = []
-      for callsite in function.callsites:
-        if callsite.target is None:
-          indirect_callsites.append(callsite.address)
-
-      if len(indirect_callsites) > 0:
-        print('    In function {}:'.format(function.name))
-        text_list = []
-        for address in indirect_callsites:
-          text_list.append(OutputInlineStack(address, '        '))
-
-        for _, text in sorted(text_list, key=lambda item: item[0]):
-          print(text)
-
-    print('Unresolved annotation signatures:')
-    for sigtxt, error in failed_sigtxts:
-      print('    {}: {}'.format(sigtxt, error))
-
-    if len(cycle_functions) > 0:
-      print('There are cycles in the following function sets:')
-      for functions in cycle_functions:
-        print('[{}]'.format(', '.join(function.name for function in functions)))
-
-
-def ParseArgs():
-  """Parse commandline arguments.
-
-  Returns:
-    options: Namespace from argparse.parse_args().
-  """
-  parser = argparse.ArgumentParser(description="EC firmware stack analyzer.")
-  parser.add_argument('elf_path', help="the path of EC firmware ELF")
-  parser.add_argument('--export_taskinfo', required=True,
-                      help="the path of export_taskinfo.so utility")
-  parser.add_argument('--section', required=True, help='the section.',
-                      choices=[SECTION_RO, SECTION_RW])
-  parser.add_argument('--objdump', default='objdump',
-                      help='the path of objdump')
-  parser.add_argument('--addr2line', default='addr2line',
-                      help='the path of addr2line')
-  parser.add_argument('--annotation', default=None,
-                      help='the path of annotation file')
-
-  # TODO(cheyuw): Add an option for dumping stack usage of all functions.
-
-  return parser.parse_args()
-
-
-def ParseSymbolText(symbol_text):
-  """Parse the content of the symbol text.
-
-  Args:
-    symbol_text: Text of the symbols.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Example: "10093064 g     F .text  0000015c .hidden hook_task"
-  symbol_regex = re.compile(r'^(?P<address>[0-9A-Fa-f]+)\s+[lwg]\s+'
-                            r'((?P<type>[OF])\s+)?\S+\s+'
-                            r'(?P<size>[0-9A-Fa-f]+)\s+'
-                            r'(\S+\s+)?(?P<name>\S+)$')
-
-  symbols = []
-  for line in symbol_text.splitlines():
-    line = line.strip()
-    result = symbol_regex.match(line)
-    if result is not None:
-      address = int(result.group('address'), 16)
-      symtype = result.group('type')
-      if symtype is None:
-        symtype = 'O'
-
-      size = int(result.group('size'), 16)
-      name = result.group('name')
-      symbols.append(Symbol(address, symtype, size, name))
-
-  return symbols
-
-
-def ParseRoDataText(rodata_text):
-  """Parse the content of rodata
-
-  Args:
-    symbol_text: Text of the rodata dump.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108  ...H........K...
-  #           100a7294 00000000 00000000 01000000           ............
-
-  base_offset = None
-  offset = None
-  rodata = []
-  for line in rodata_text.splitlines():
-    line = line.strip()
-    space = line.find(' ')
-    if space < 0:
-        continue
-    try:
-      address = int(line[0:space], 16)
-    except ValueError:
-      continue
-
-    if not base_offset:
-      base_offset = address
-      offset = address
-    elif address != offset:
-      raise StackAnalyzerError('objdump of rodata not contiguous.')
-
-    for i in range(0, 4):
-      num = line[(space + 1 + i*9):(space + 9 + i*9)]
-      if len(num.strip()) > 0:
-        val = int(num, 16)
-      else:
-        val = 0
-      # TODO(drinkcat): Not all platforms are necessarily big-endian
-      rodata.append((val & 0x000000ff) << 24 |
-                    (val & 0x0000ff00) << 8 |
-                    (val & 0x00ff0000) >> 8 |
-                    (val & 0xff000000) >> 24)
-
-    offset = offset + 4*4
-
-  return (base_offset, rodata)
-
-
-def LoadTasklist(section, export_taskinfo, symbols):
-  """Load the task information.
-
-  Args:
-    section: Section (RO | RW).
-    export_taskinfo: Handle of export_taskinfo.so.
-    symbols: Symbol list.
-
-  Returns:
-    tasklist: Task list.
-  """
-
-  TaskInfoPointer = ctypes.POINTER(TaskInfo)
-  taskinfos = TaskInfoPointer()
-  if section == SECTION_RO:
-    get_taskinfos_func = export_taskinfo.get_ro_taskinfos
-  else:
-    get_taskinfos_func = export_taskinfo.get_rw_taskinfos
-
-  taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos))
-
-  tasklist = []
-  for index in range(taskinfo_num):
-    taskinfo = taskinfos[index]
-    tasklist.append(Task(taskinfo.name.decode('utf-8'),
-                         taskinfo.routine.decode('utf-8'),
-                         taskinfo.stack_size))
-
-  # Resolve routine address for each task. It's more efficient to resolve all
-  # routine addresses of tasks together.
-  routine_map = dict((task.routine_name, None) for task in tasklist)
-
-  for symbol in symbols:
-    # Resolve task routine address.
-    if symbol.name in routine_map:
-      # Assume the symbol of routine is unique.
-      assert routine_map[symbol.name] is None
-      routine_map[symbol.name] = symbol.address
-
-  for task in tasklist:
-    address = routine_map[task.routine_name]
-    # Assume we have resolved all routine addresses.
-    assert address is not None
-    task.routine_address = address
-
-  return tasklist
-
-
-def main():
-  """Main function."""
-  try:
-    options = ParseArgs()
-
-    # Load annotation config.
-    if options.annotation is None:
-      annotation = {}
-    elif not os.path.exists(options.annotation):
-      print('Warning: Annotation file {} does not exist.'
-            .format(options.annotation))
-      annotation = {}
-    else:
-      try:
-        with open(options.annotation, 'r') as annotation_file:
-          annotation = yaml.safe_load(annotation_file)
-
-      except yaml.YAMLError:
-        raise StackAnalyzerError('Failed to parse annotation file {}.'
-                                 .format(options.annotation))
-      except IOError:
-        raise StackAnalyzerError('Failed to open annotation file {}.'
-                                 .format(options.annotation))
-
-      # TODO(cheyuw): Do complete annotation format verification.
-      if not isinstance(annotation, dict):
-        raise StackAnalyzerError('Invalid annotation file {}.'
-                                 .format(options.annotation))
-
-    # Generate and parse the symbols.
-    try:
-      symbol_text = subprocess.check_output([options.objdump,
-                                             '-t',
-                                             options.elf_path],
-                                            encoding='utf-8')
-      rodata_text = subprocess.check_output([options.objdump,
-                                             '-s',
-                                             '-j', '.rodata',
-                                             options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to dump symbol table or rodata.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    symbols = ParseSymbolText(symbol_text)
-    rodata = ParseRoDataText(rodata_text)
-
-    # Load the tasklist.
-    try:
-      export_taskinfo = ctypes.CDLL(options.export_taskinfo)
-    except OSError:
-      raise StackAnalyzerError('Failed to load export_taskinfo.')
-
-    tasklist = LoadTasklist(options.section, export_taskinfo, symbols)
-
-    analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation)
-    analyzer.Analyze()
-  except StackAnalyzerError as e:
-    print('Error: {}'.format(e))
-
-
-if __name__ == '__main__':
-  main()
diff --git a/extra/stack_analyzer/stack_analyzer_unittest.py b/extra/stack_analyzer/stack_analyzer_unittest.py
deleted file mode 100755
index c36fa9da45..0000000000
--- a/extra/stack_analyzer/stack_analyzer_unittest.py
+++ /dev/null
@@ -1,830 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Tests for Stack Analyzer classes and functions."""
-
-from __future__ import print_function
-
-import mock
-import os
-import subprocess
-import unittest
-
-import stack_analyzer as sa
-
-
-class ObjectTest(unittest.TestCase):
-  """Tests for classes of basic objects."""
-
-  def testTask(self):
-    task_a = sa.Task('a', 'a_task', 1234)
-    task_b = sa.Task('b', 'b_task', 5678, 0x1000)
-    self.assertEqual(task_a, task_a)
-    self.assertNotEqual(task_a, task_b)
-    self.assertNotEqual(task_a, None)
-
-  def testSymbol(self):
-    symbol_a = sa.Symbol(0x1234, 'F', 32, 'a')
-    symbol_b = sa.Symbol(0x234, 'O', 42, 'b')
-    self.assertEqual(symbol_a, symbol_a)
-    self.assertNotEqual(symbol_a, symbol_b)
-    self.assertNotEqual(symbol_a, None)
-
-  def testCallsite(self):
-    callsite_a = sa.Callsite(0x1002, 0x3000, False)
-    callsite_b = sa.Callsite(0x1002, 0x3000, True)
-    self.assertEqual(callsite_a, callsite_a)
-    self.assertNotEqual(callsite_a, callsite_b)
-    self.assertNotEqual(callsite_a, None)
-
-  def testFunction(self):
-    func_a = sa.Function(0x100, 'a', 0, [])
-    func_b = sa.Function(0x200, 'b', 0, [])
-    self.assertEqual(func_a, func_a)
-    self.assertNotEqual(func_a, func_b)
-    self.assertNotEqual(func_a, None)
-
-
-class ArmAnalyzerTest(unittest.TestCase):
-  """Tests for class ArmAnalyzer."""
-
-  def AppendConditionCode(self, opcodes):
-    rets = []
-    for opcode in opcodes:
-      rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES)
-
-    return rets
-
-  def testInstructionMatching(self):
-    jump_list = self.AppendConditionCode(['b', 'bx'])
-    jump_list += (list(opcode + '.n' for opcode in jump_list) +
-                  list(opcode + '.w' for opcode in jump_list))
-    for opcode in jump_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('bl'))
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('blx'))
-
-    cbz_list = ['cbz', 'cbnz', 'cbz.n', 'cbnz.n', 'cbz.w', 'cbnz.w']
-    for opcode in cbz_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match('cbn'))
-
-    call_list = self.AppendConditionCode(['bl', 'blx'])
-    call_list += list(opcode + '.n' for opcode in call_list)
-    for opcode in call_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match('ble'))
-
-    result = sa.ArmAnalyzer.CALL_OPERAND_RE.match('53f90 <get_time+0x18>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get_time+0x18')
-
-    result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match('r6, 53f90 <get+0x0>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get+0x0')
-
-    self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('push'))
-    self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('pushal'))
-    self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('stmdb'))
-    self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('lstm'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subw'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub.w'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs.w'))
-
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, sp, #1668   ; 0x684')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, #1668')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match('sl, #1668'))
-
-  def testAnalyzeFunction(self):
-    analyzer = sa.ArmAnalyzer()
-    symbol = sa.Symbol(0x10, 'F', 0x100, 'foo')
-    instructions = [
-        (0x10, 'push', '{r4, r5, r6, r7, lr}'),
-        (0x12, 'subw', 'sp, sp, #16	; 0x10'),
-        (0x16, 'movs', 'lr, r1'),
-        (0x18, 'beq.n', '26 <foo+0x26>'),
-        (0x1a, 'bl', '30 <foo+0x30>'),
-        (0x1e, 'bl', 'deadbeef <bar>'),
-        (0x22, 'blx', '0 <woo>'),
-        (0x26, 'push', '{r1}'),
-        (0x28, 'stmdb', 'sp!, {r4, r5, r6, r7, r8, r9, lr}'),
-        (0x2c, 'stmdb', 'sp!, {r4}'),
-        (0x30, 'stmdb', 'sp, {r4}'),
-        (0x34, 'bx.n', '10 <foo>'),
-        (0x36, 'bx.n', 'r3'),
-        (0x38, 'ldr', 'pc, [r10]'),
-    ]
-    (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions)
-    self.assertEqual(size, 72)
-    expect_callsites = [sa.Callsite(0x1e, 0xdeadbeef, False),
-                        sa.Callsite(0x22, 0x0, False),
-                        sa.Callsite(0x34, 0x10, True),
-                        sa.Callsite(0x36, None, True),
-                        sa.Callsite(0x38, None, True)]
-    self.assertEqual(callsites, expect_callsites)
-
-
-class StackAnalyzerTest(unittest.TestCase):
-  """Tests for class StackAnalyzer."""
-
-  def setUp(self):
-    symbols = [sa.Symbol(0x1000, 'F', 0x15C, 'hook_task'),
-               sa.Symbol(0x2000, 'F', 0x51C, 'console_task'),
-               sa.Symbol(0x3200, 'O', 0x124, '__just_data'),
-               sa.Symbol(0x4000, 'F', 0x11C, 'touchpad_calc'),
-               sa.Symbol(0x5000, 'F', 0x12C, 'touchpad_calc.constprop.42'),
-               sa.Symbol(0x12000, 'F', 0x13C, 'trackpad_range'),
-               sa.Symbol(0x13000, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul_alias'),
-               sa.Symbol(0x20000, 'O', 0x0, '__array'),
-               sa.Symbol(0x20010, 'O', 0x0, '__array_end'),
-    ]
-    tasklist = [sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-                sa.Task('CONSOLE', 'console_task', 460, 0x2000)]
-    # Array at 0x20000 that contains pointers to hook_task and console_task,
-    # with stride=8, offset=4
-    rodata = (0x20000, [ 0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000 ])
-    options = mock.MagicMock(elf_path='./ec.RW.elf',
-                             export_taskinfo='fake',
-                             section='RW',
-                             objdump='objdump',
-                             addr2line='addr2line',
-                             annotation=None)
-    self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {})
-
-  def testParseSymbolText(self):
-    symbol_text = (
-        '0 g     F .text  e8 Foo\n'
-        '0000dead  w    F .text  000000e8 .hidden Bar\n'
-        'deadbeef l     O .bss   00000004 .hidden Woooo\n'
-        'deadbee g     O .rodata        00000008 __Hooo_ooo\n'
-        'deadbee g       .rodata        00000000 __foo_doo_coo_end\n'
-    )
-    symbols = sa.ParseSymbolText(symbol_text)
-    expect_symbols = [sa.Symbol(0x0, 'F', 0xe8, 'Foo'),
-                      sa.Symbol(0xdead, 'F', 0xe8, 'Bar'),
-                      sa.Symbol(0xdeadbeef, 'O', 0x4, 'Woooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x8, '__Hooo_ooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x0, '__foo_doo_coo_end')]
-    self.assertEqual(symbols, expect_symbols)
-
-  def testParseRoData(self):
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-    rodata = sa.ParseRoDataText(rodata_text)
-    expect_rodata = (0x20000,
-                     [ 0x0010adde, 0x00001000, 0x0020adde, 0x00002000 ])
-    self.assertEqual(rodata, expect_rodata)
-
-  def testLoadTasklist(self):
-    def tasklist_to_taskinfos(pointer, tasklist):
-      taskinfos = []
-      for task in tasklist:
-        taskinfos.append(sa.TaskInfo(name=task.name.encode('utf-8'),
-                                     routine=task.routine_name.encode('utf-8'),
-                                     stack_size=task.stack_max_size))
-
-      TaskInfoArray = sa.TaskInfo * len(taskinfos)
-      pointer.contents.contents = TaskInfoArray(*taskinfos)
-      return len(taskinfos)
-
-    def ro_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_ro_tasklist)
-
-    def rw_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_rw_tasklist)
-
-    expect_ro_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-    ]
-
-    expect_rw_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-        sa.Task('WOOKS', 'hook_task', 4096, 0x1000),
-        sa.Task('CONSOLE', 'console_task', 460, 0x2000),
-    ]
-
-    export_taskinfo = mock.MagicMock(
-        get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos),
-        get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos))
-
-    tasklist = sa.LoadTasklist('RO', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_ro_tasklist)
-    tasklist = sa.LoadTasklist('RW', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_rw_tasklist)
-
-  def testResolveAnnotation(self):
-    self.analyzer.annotation = {}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {'add': None, 'remove': None}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {
-        'add': None,
-        'remove': [
-            [['a', 'b'], ['0', '[', '2'], 'x'],
-            [['a', 'b[x:3]'], ['0', '1', '2'], 'x'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(list.sort(remove_rules), list.sort([
-        [('a', None, None), ('1', None, None), ('x', None, None)],
-        [('a', None, None), ('0', None, None), ('x', None, None)],
-        [('a', None, None), ('2', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('1', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('0', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('2', None, None), ('x', None, None)],
-    ]))
-    self.assertEqual(invalid_sigtxts, {'['})
-
-    self.analyzer.annotation = {
-        'add': {
-          'touchpad_calc': [ dict(name='__array', stride=8, offset=4) ],
-        }
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {
-      ('touchpad_calc', None, None):
-        set([('console_task', None, None), ('hook_task', None, None)])})
-
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-        0x5000: sa.Function(0x5000, 'touchpad_calc.constprop.42', 0, []),
-        0x13000: sa.Function(0x13000, 'inlined_mul', 0, []),
-        0x13100: sa.Function(0x13100, 'inlined_mul', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, None, False, None)]
-    # Set address_to_line_cache to fake the results of addr2line.
-    self.analyzer.address_to_line_cache = {
-        (0x1000, False): [('hook_task', os.path.abspath('a.c'), 10)],
-        (0x1002, False): [('toot_calc', os.path.abspath('t.c'), 1234)],
-        (0x2000, False): [('console_task', os.path.abspath('b.c'), 20)],
-        (0x4000, False): [('toudhpad_calc', os.path.abspath('a.c'), 20)],
-        (0x5000, False): [
-            ('touchpad_calc.constprop.42', os.path.abspath('b.c'), 40)],
-        (0x12000, False): [('trackpad_range', os.path.abspath('t.c'), 10)],
-        (0x13000, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-        (0x13100, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-    }
-    self.analyzer.annotation = {
-        'add': {
-            'hook_task.lto.573': ['touchpad_calc.lto.2501[a.c]'],
-            'console_task': ['touchpad_calc[b.c]', 'inlined_mul_alias'],
-            'hook_task[q.c]': ['hook_task'],
-            'inlined_mul[x.c]': ['inlined_mul'],
-            'toot_calc[t.c:1234]': ['hook_task'],
-        },
-        'remove': [
-            ['touchpad?calc['],
-            'touchpad_calc',
-            ['touchpad_calc[a.c]'],
-            ['task_unk[a.c]'],
-            ['touchpad_calc[x/a.c]'],
-            ['trackpad_range'],
-            ['inlined_mul'],
-            ['inlined_mul', 'console_task', 'touchpad_calc[a.c]'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(invalid_sigtxts, {'touchpad?calc['})
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    (signature_map, failed_sigs) = self.analyzer.MapAnnotation(funcs,
-                                                               signature_set)
-    result = self.analyzer.ResolveAnnotation(funcs)
-    (add_set, remove_list, eliminated_addrs, failed_sigs) = result
-
-    expect_signature_map = {
-        ('hook_task', None, None): {funcs[0x1000]},
-        ('touchpad_calc', os.path.abspath('a.c'), None): {funcs[0x4000]},
-        ('touchpad_calc', os.path.abspath('b.c'), None): {funcs[0x5000]},
-        ('console_task', None, None): {funcs[0x2000]},
-        ('inlined_mul_alias', None, None): {funcs[0x13100]},
-        ('inlined_mul', os.path.abspath('x.c'), None): {funcs[0x13000],
-                                                        funcs[0x13100]},
-        ('inlined_mul', None, None): {funcs[0x13000], funcs[0x13100]},
-    }
-    self.assertEqual(len(signature_map), len(expect_signature_map))
-    for sig, funclist in signature_map.items():
-      self.assertEqual(set(funclist), expect_signature_map[sig])
-
-    self.assertEqual(add_set, {
-        (funcs[0x1000], funcs[0x4000]),
-        (funcs[0x1000], funcs[0x1000]),
-        (funcs[0x2000], funcs[0x5000]),
-        (funcs[0x2000], funcs[0x13100]),
-        (funcs[0x13000], funcs[0x13000]),
-        (funcs[0x13000], funcs[0x13100]),
-        (funcs[0x13100], funcs[0x13000]),
-        (funcs[0x13100], funcs[0x13100]),
-    })
-    expect_remove_list = [
-        [funcs[0x4000]],
-        [funcs[0x13000]],
-        [funcs[0x13100]],
-        [funcs[0x13000], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13100], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13000], funcs[0x13100], funcs[0x2000]],
-        [funcs[0x13100], funcs[0x13100], funcs[0x2000]],
-    ]
-    self.assertEqual(len(remove_list), len(expect_remove_list))
-    for remove_path in remove_list:
-      self.assertTrue(remove_path in expect_remove_list)
-
-    self.assertEqual(eliminated_addrs, {0x1002})
-    self.assertEqual(failed_sigs, {
-        ('touchpad?calc[', sa.StackAnalyzer.ANNOTATION_ERROR_INVALID),
-        ('touchpad_calc', sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS),
-        ('hook_task[q.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('task_unk[a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('touchpad_calc[x/a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('trackpad_range', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-    })
-
-  def testPreprocessAnnotation(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]),
-        sa.Callsite(0x2006, None, True, None),
-    ]
-    add_set = {
-        (funcs[0x2000], funcs[0x2000]),
-        (funcs[0x2000], funcs[0x4000]),
-        (funcs[0x4000], funcs[0x1000]),
-        (funcs[0x4000], funcs[0x2000]),
-    }
-    remove_list = [
-        [funcs[0x1000]],
-        [funcs[0x2000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000]],
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000], funcs[0x4000]],
-    ]
-    eliminated_addrs = {0x2006}
-
-    remaining_remove_list = self.analyzer.PreprocessAnnotation(funcs,
-                                                               add_set,
-                                                               remove_list,
-                                                               eliminated_addrs)
-
-    expect_funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    expect_funcs[0x2000].callsites = [
-        sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])]
-    expect_funcs[0x4000].callsites = [
-        sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])]
-    self.assertEqual(funcs, expect_funcs)
-    self.assertEqual(remaining_remove_list, [
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-    ])
-
-  def testAndesAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 42\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1004:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   b1 13\tbnezs8 100929de <flash_command_write>\n'
-        '   1008:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   de ad be ef\tswi.gp $r0, [ + #-11036]\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:   47 70\t\tmovi55 $r0, #1\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 48, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 16,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testArmAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	dead beef\tfake\n'
-        '   1004:	4770\t\tbx	lr\n'
-        '   1006:	b113\tcbz	r3, 100929de <flash_command_write>\n'
-        '   1008:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr} ; malformed comments,; r0, r1 \n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	dead beef\tfake\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:	4770\t\tbx	lr\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 0, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 8,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testAnalyzeCallGraph(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 8, []),
-        0x3000: sa.Function(0x3000, 'task_a', 12, []),
-        0x4000: sa.Function(0x4000, 'task_b', 96, []),
-        0x5000: sa.Function(0x5000, 'task_c', 32, []),
-        0x6000: sa.Function(0x6000, 'task_d', 100, []),
-        0x7000: sa.Function(0x7000, 'task_e', 24, []),
-        0x8000: sa.Function(0x8000, 'task_f', 20, []),
-        0x9000: sa.Function(0x9000, 'task_g', 20, []),
-        0x10000: sa.Function(0x10000, 'task_x', 16, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]),
-        sa.Callsite(0x1006, 0x4000, False, funcs[0x4000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]),
-        sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]),
-        sa.Callsite(0x200a, 0x10000, False, funcs[0x10000])]
-    funcs[0x3000].callsites = [
-        sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]),
-        sa.Callsite(0x3006, 0x1000, False, funcs[0x1000])]
-    funcs[0x4000].callsites = [
-        sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]),
-        sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]),
-        sa.Callsite(0x400a, 0x8000, False, funcs[0x8000])]
-    funcs[0x5000].callsites = [
-        sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])]
-    funcs[0x7000].callsites = [
-        sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])]
-    funcs[0x8000].callsites = [
-        sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])]
-    funcs[0x9000].callsites = [
-        sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])]
-    funcs[0x10000].callsites = [
-        sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])]
-
-    cycles = self.analyzer.AnalyzeCallGraph(funcs, [
-        [funcs[0x2000]] * 2,
-        [funcs[0x10000], funcs[0x2000]] * 3,
-        [funcs[0x1000], funcs[0x3000], funcs[0x1000]]
-    ])
-
-    expect_func_stack = {
-        0x1000: (268, [funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x2000: (208, [funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x5000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x3000: (280, [funcs[0x3000],
-                       funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x4000: (120, [funcs[0x4000], funcs[0x7000]]),
-        0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]),
-        0x6000: (100, [funcs[0x6000]]),
-        0x7000: (24, [funcs[0x7000]]),
-        0x8000: (160, [funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]),
-        0x10000: (200, [funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x5000],
-                        funcs[0x4000],
-                        funcs[0x7000]]),
-    }
-    expect_cycles = [
-        {funcs[0x4000], funcs[0x8000], funcs[0x9000]},
-        {funcs[0x7000]},
-    ]
-    for func in funcs.values():
-      (stack_max_usage, stack_max_path) = expect_func_stack[func.address]
-      self.assertEqual(func.stack_max_usage, stack_max_usage)
-      self.assertEqual(func.stack_max_path, stack_max_path)
-
-    self.assertEqual(len(cycles), len(expect_cycles))
-    for cycle in cycles:
-      self.assertTrue(cycle in expect_cycles)
-
-  @mock.patch('subprocess.check_output')
-  def testAddressToLine(self, checkoutput_mock):
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/a.c:1\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234, True),
-                     [('fake_func', '/a.c', 1), ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234', '-i'],
-        encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1 (discriminator 128)'
-    self.assertEqual(self.analyzer.AddressToLine(0x12345),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '12345'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = '??\n:?\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x123456),
-                     [None, ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '123456'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'addr2line failed to resolve lines.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.AddressToLine(0x5678)
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run addr2line.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.AddressToLine(0x9012)
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 00\t\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1002:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   12 34 56 78\tjral5 $r0\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (16) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testArmAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	b508\t\tpush	{r3, lr}\n'
-        '   1002:	4770\t\tbx	lr\n'
-        '   1006:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr}\n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	1234 5678\tb.w  sl\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (8) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.ParseArgs')
-  def testMain(self, parseargs_mock, checkoutput_mock):
-    symbol_text = ('1000 g     F .text  0000015c .hidden hook_task\n'
-                   '2000 g     F .text  0000051c .hidden console_task\n')
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-
-    args = mock.MagicMock(elf_path='./ec.RW.elf',
-                          export_taskinfo='fake',
-                          section='RW',
-                          objdump='objdump',
-                          addr2line='addr2line',
-                          annotation='fake')
-    parseargs_mock.return_value = args
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = False
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          sa.main()
-          print_mock.assert_any_call(
-              'Warning: Annotation file fake does not exist.')
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = True
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.side_effect = IOError()
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Failed to open annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.return_value.read.side_effect = ['{', '']
-          sa.main()
-          open_mock.assert_called_once_with('fake', 'r')
-          print_mock.assert_called_once_with(
-              'Error: Failed to parse annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open',
-                        mock.mock_open(read_data='')) as open_mock:
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Invalid annotation file fake.')
-
-    args.annotation = None
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = [symbol_text, rodata_text]
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: Failed to load export_taskinfo.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: objdump failed to dump symbol table or rodata.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = OSError()
-      sa.main()
-      print_mock.assert_called_once_with('Error: Failed to run objdump.')
-
-
-if __name__ == '__main__':
-  unittest.main()
diff --git a/extra/tigertool/README.md b/extra/tigertool/README.md
deleted file mode 100644
index 407a58a751..0000000000
--- a/extra/tigertool/README.md
+++ /dev/null
@@ -1,28 +0,0 @@
-# tigertool
-
-tigertool.py is a commandline utility to control the tigertail USB-C mux. It
-supports changing the mux status to port A, B, or off. You can set a serial
-number to use multiple tigertails at once.
-
-## Usage
-
-Typical usage to set the mux port
-
-```
-./tigertail.py -m [A|B|off] -s [serialno]
-```
-
-Reboot the tigertail<br>
-
-```
-./tigertail.py --reboot
-```
-
-Set the serial number, when only one tigertail is plugged
-
-```
-./tigertail.py --setserialno=[serialno]
-```
-
-Tigertail can support up to 20V 3A on the mux and passes through all USB-C lines
-except SBU.
diff --git a/extra/tigertool/ecusb/__init__.py b/extra/tigertool/ecusb/__init__.py
deleted file mode 100644
index fe4dbc6749..0000000000
--- a/extra/tigertool/ecusb/__init__.py
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-__all__ = ['tiny_servo_common', 'stm32usb', 'stm32uart', 'pty_driver']
diff --git a/extra/tigertool/ecusb/pty_driver.py b/extra/tigertool/ecusb/pty_driver.py
deleted file mode 100644
index 137cbc149b..0000000000
--- a/extra/tigertool/ecusb/pty_driver.py
+++ /dev/null
@@ -1,304 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""ptyDriver class
-
-This class takes a pty interface and can send commands and expect results
-as regex. This is useful for automating console based interfaces, such as
-the CrOS EC console commands.
-"""
-
-import ast
-import errno
-import fcntl
-import os
-import pexpect
-import time
-from pexpect import fdpexpect
-
-# Expecting a result in 3 seconds is plenty even for slow platforms.
-DEFAULT_UART_TIMEOUT = 3
-FLUSH_UART_TIMEOUT = 1
-
-
-class ptyError(Exception):
-  """Exception class for pty errors."""
-
-
-UART_PARAMS = {
-    'uart_cmd': None,
-    'uart_multicmd': None,
-    'uart_regexp': None,
-    'uart_timeout': DEFAULT_UART_TIMEOUT,
-}
-
-
-class ptyDriver(object):
-  """Automate interactive commands on a pty interface."""
-  def __init__(self, interface, params, fast=False):
-    """Init class variables."""
-    self._child = None
-    self._fd = None
-    self._interface = interface
-    self._pty_path = self._interface.get_pty()
-    self._dict = UART_PARAMS.copy()
-    self._fast = fast
-
-  def __del__(self):
-    self.close()
-
-  def close(self):
-    """Close any open files and interfaces."""
-    if self._fd:
-      self._close()
-    self._interface.close()
-
-  def _open(self):
-    """Connect to serial device and create pexpect interface."""
-    assert self._fd is None
-    self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK)
-    # Don't allow forked processes to access.
-    fcntl.fcntl(self._fd, fcntl.F_SETFD,
-                fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC)
-    self._child = fdpexpect.fdspawn(self._fd)
-    # pexpect defaults to a 100ms delay before sending characters, to
-    # work around race conditions in ssh. We don't need this feature
-    # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up.
-    if self._fast:
-      self._child.delaybeforesend = 0.001
-
-  def _close(self):
-    """Close serial device connection."""
-    os.close(self._fd)
-    self._fd = None
-    self._child = None
-
-  def _flush(self):
-    """Flush device output to prevent previous messages interfering."""
-    if self._child.sendline('') != 1:
-      raise ptyError('Failed to send newline.')
-    # Have a maximum timeout for the flush operation. We should have cleared
-    # all data from the buffer, but if data is regularly being generated, we
-    # can't guarantee it will ever stop.
-    flush_end_time = time.time() + FLUSH_UART_TIMEOUT
-    while time.time() <= flush_end_time:
-      try:
-        self._child.expect('.', timeout=0.01)
-      except (pexpect.TIMEOUT, pexpect.EOF):
-        break
-      except OSError as e:
-        # EAGAIN indicates no data available, maybe we didn't wait long enough.
-        if e.errno != errno.EAGAIN:
-          raise
-        break
-
-  def _send(self, cmds):
-    """Send command to EC.
-
-    This function always flushes serial device before sending, and is used as
-    a wrapper function to make sure the channel is always flushed before
-    sending commands.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-
-    Raises:
-      ptyError: Raised when writing to the device fails.
-    """
-    self._flush()
-    if not isinstance(cmds, list):
-      cmds = [cmds]
-    for cmd in cmds:
-      if self._child.sendline(cmd) != len(cmd) + 1:
-        raise ptyError('Failed to send command.')
-
-  def _issue_cmd(self, cmds):
-    """Send command to the device and do not wait for response.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-    """
-    self._issue_cmd_get_results(cmds, [])
-
-  def _issue_cmd_get_results(self, cmds,
-                             regex_list, timeout=DEFAULT_UART_TIMEOUT):
-    """Send command to the device and wait for response.
-
-    This function waits for response message matching a regular
-    expressions.
-
-    Args:
-      cmds: The commands issued, either a list or a string.
-      regex_list: List of Regular expressions used to match response message.
-        Note1, list must be ordered.
-        Note2, empty list sends and returns.
-      timeout: time to wait for matching results before failing.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-      For example:
-        response of the given command:
-          High temp: 37.2
-          Low temp: 36.4
-        regex_list:
-          ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)']
-        returns:
-          [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')]
-
-    Raises:
-      ptyError: If timed out waiting for a response
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmds)
-      for regex in regex_list:
-        self._child.expect(regex, timeout)
-        match = self._child.match
-        lastindex = match.lastindex if match and match.lastindex else 0
-        # Create a tuple which contains the entire matched string and all
-        # the subgroups of the match.
-        result = match.group(*range(lastindex + 1)) if match else None
-        if result:
-          result = tuple(res.decode('utf-8') for res in result)
-        result_list.append(result)
-    except pexpect.TIMEOUT:
-      raise ptyError('Timeout waiting for response.')
-    finally:
-      self._close()
-    return result_list
-
-  def _issue_cmd_get_multi_results(self, cmd, regex):
-    """Send command to the device and wait for multiple response.
-
-    This function waits for arbitrary number of response message
-    matching a regular expression.
-
-    Args:
-      cmd: The command issued.
-      regex: Regular expression used to match response message.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmd)
-      while True:
-        try:
-          self._child.expect(regex, timeout=0.1)
-          match = self._child.match
-          lastindex = match.lastindex if match and match.lastindex else 0
-          # Create a tuple which contains the entire matched string and all
-          # the subgroups of the match.
-          result = match.group(*range(lastindex + 1)) if match else None
-          if result:
-            result = tuple(res.decode('utf-8') for res in result)
-          result_list.append(result)
-        except pexpect.TIMEOUT:
-          break
-    finally:
-      self._close()
-    return result_list
-
-  def _Set_uart_timeout(self, timeout):
-    """Set timeout value for waiting for the device response.
-
-    Args:
-      timeout: Timeout value in second.
-    """
-    self._dict['uart_timeout'] = timeout
-
-  def _Get_uart_timeout(self):
-    """Get timeout value for waiting for the device response.
-
-    Returns:
-      Timeout value in second.
-    """
-    return self._dict['uart_timeout']
-
-  def _Set_uart_regexp(self, regexp):
-    """Set the list of regular expressions which matches the command response.
-
-    Args:
-      regexp: A string which contains a list of regular expressions.
-    """
-    if not isinstance(regexp, str):
-      raise ptyError('The argument regexp should be a string.')
-    self._dict['uart_regexp'] = ast.literal_eval(regexp)
-
-  def _Get_uart_regexp(self):
-    """Get the list of regular expressions which matches the command response.
-
-    Returns:
-      A string which contains a list of regular expressions.
-    """
-    return str(self._dict['uart_regexp'])
-
-  def _Set_uart_cmd(self, cmd):
-    """Set the UART command and send it to the device.
-
-    If ec_uart_regexp is 'None', the command is just sent and it doesn't care
-    about its response.
-
-    If ec_uart_regexp is not 'None', the command is send and its response,
-    which matches the regular expression of ec_uart_regexp, will be kept.
-    Use its getter to obtain this result. If no match after ec_uart_timeout
-    seconds, a timeout error will be raised.
-
-    Args:
-      cmd: A string of UART command.
-    """
-    if self._dict['uart_regexp']:
-      self._dict['uart_cmd'] = self._issue_cmd_get_results(
-          cmd, self._dict['uart_regexp'], self._dict['uart_timeout'])
-    else:
-      self._dict['uart_cmd'] = None
-      self._issue_cmd(cmd)
-
-  def _Set_uart_multicmd(self, cmds):
-    """Set multiple UART commands and send them to the device.
-
-    Note that ec_uart_regexp is not supported to match the results.
-
-    Args:
-      cmds: A semicolon-separated string of UART commands.
-    """
-    self._issue_cmd(cmds.split(';'))
-
-  def _Get_uart_cmd(self):
-    """Get the result of the latest UART command.
-
-    Returns:
-      A string which contains a list of tuples, each of which contains the
-      entire matched string and all the subgroups of the match. 'None' if
-      the ec_uart_regexp is 'None'.
-    """
-    return str(self._dict['uart_cmd'])
-
-  def _Set_uart_capture(self, cmd):
-    """Set UART capture mode (on or off).
-
-    Once capture is enabled, UART output could be collected periodically by
-    invoking _Get_uart_stream() below.
-
-    Args:
-      cmd: True for on, False for off
-    """
-    self._interface.set_capture_active(cmd)
-
-  def _Get_uart_capture(self):
-    """Get the UART capture mode (on or off)."""
-    return self._interface.get_capture_active()
-
-  def _Get_uart_stream(self):
-    """Get uart stream generated since last time."""
-    return self._interface.get_stream()
diff --git a/extra/tigertool/ecusb/stm32uart.py b/extra/tigertool/ecusb/stm32uart.py
deleted file mode 100644
index 95219455a9..0000000000
--- a/extra/tigertool/ecusb/stm32uart.py
+++ /dev/null
@@ -1,248 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Allow creation of uart/console interface via stm32 usb endpoint."""
-
-from __future__ import print_function
-
-import os
-import select
-import sys
-import termios
-import threading
-import time
-import tty
-import usb
-
-from . import stm32usb
-
-
-class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-
-class Suart(object):
-  """Provide interface to stm32 serial usb endpoint."""
-  def __init__(self, vendor=0x18d1, product=0x501a, interface=0,
-               serialname=None, debuglog=False):
-    """Suart contstructor.
-
-    Initializes stm32 USB stream interface.
-
-    Args:
-      vendor: usb vendor id of stm32 device
-      product: usb product id of stm32 device
-      interface: interface number of stm32 device to use
-      serialname: serial name to target. Defaults to None.
-      debuglog: chatty output. Defaults to False.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._ptym = None
-    self._ptys = None
-    self._ptyname = None
-    self._rx_thread = None
-    self._tx_thread = None
-    self._debuglog = debuglog
-    self._susb = stm32usb.Susb(vendor=vendor, product=product,
-                               interface=interface, serialname=serialname)
-    self._running = False
-
-  def __del__(self):
-    """Suart destructor."""
-    self.close()
-
-  def close(self):
-    """Stop all running threads."""
-    self._running = False
-    if self._rx_thread:
-      self._rx_thread.join(2)
-      self._rx_thread = None
-    if self._tx_thread:
-      self._tx_thread.join(2)
-      self._tx_thread = None
-    self._susb.close()
-
-  def run_rx_thread(self):
-    """Background loop to pass data from USB to pty."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              if self._debuglog:
-                print(''.join([chr(x) for x in r]), end='')
-              os.write(self._ptym, r)
-
-          # If we miss some characters on pty disconnect, that's fine.
-          # ep.read() also throws USBError on timeout, which we discard.
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run_tx_thread(self):
-    """Background loop to pass data from pty to USB."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = os.read(self._ptym, 64)
-            # TODO(crosbug.com/936182): Remove when the servo v4/micro console
-            # issues are fixed.
-            time.sleep(0.001)
-            if r:
-              self._susb._write_ep.write(r, self._susb.TIMEOUT_MS)
-
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run(self):
-    """Creates pthreads to poll stm32 & PTY for data."""
-    m, s = os.openpty()
-    self._ptyname = os.ttyname(s)
-
-    self._ptym = m
-    self._ptys = s
-
-    os.fchmod(s, 0o660)
-
-    # Change the owner and group of the PTY to the user who started servod.
-    try:
-      uid = int(os.environ.get('SUDO_UID', -1))
-    except TypeError:
-      uid = -1
-
-    try:
-      gid = int(os.environ.get('SUDO_GID', -1))
-    except TypeError:
-      gid = -1
-    os.fchown(s, uid, gid)
-
-    tty.setraw(self._ptym, termios.TCSADRAIN)
-
-    # Generate a HUP flag on pty slave fd.
-    os.fdopen(s).close()
-
-    self._running = True
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[])
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[])
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
-
-  def get_uart_props(self):
-    """Get the uart's properties.
-
-    Returns:
-      dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data Can be 5|6|7|8 inclusive
-        parity: integer, parity of 0-2 inclusive where:
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-    """
-    return {
-        'baudrate': 115200,
-        'bits': 8,
-        'parity': 0,
-        'sbits': 1,
-    }
-
-  def set_uart_props(self, line_props):
-    """Set the uart's properties.
-
-    Note that Suart cannot set properties
-    and will fail if the properties are not the default 115200,8n1.
-
-    Args:
-      line_props: dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data ( prior to stop bit)
-        parity: integer, parity of 0-2 inclusive where
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-
-    Raises:
-      SuartError: If requested line properties are not the default.
-    """
-    curr_props = self.get_uart_props()
-    for prop in line_props:
-      if line_props[prop] != curr_props[prop]:
-        raise SuartError('Line property %s cannot be set from %s to %s' % (
-            prop, curr_props[prop], line_props[prop]))
-    return True
-
-  def get_pty(self):
-    """Gets path to pty for communication to/from uart.
-
-    Returns:
-      String path to the pty connected to the uart
-    """
-    return self._ptyname
-
-
-def main():
-  """Run a suart test with the default parameters."""
-  try:
-    sobj = Suart()
-    sobj.run()
-
-    # run() is a thread so just busy wait to mimic server.
-    while True:
-      # Ours sleeps to eleven!
-      time.sleep(11)
-  except KeyboardInterrupt:
-    sys.exit(0)
-
-
-if __name__ == '__main__':
-  main()
diff --git a/extra/tigertool/ecusb/stm32usb.py b/extra/tigertool/ecusb/stm32usb.py
deleted file mode 100644
index bfd5fbb1fb..0000000000
--- a/extra/tigertool/ecusb/stm32usb.py
+++ /dev/null
@@ -1,119 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Allows creation of an interface via stm32 usb."""
-
-import usb
-
-
-class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-
-class Susb(object):
-  """Provide stm32 USB functionality.
-
-  Instance Variables:
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x5027, interface=1, serialname=None, logger=None):
-    """Susb constructor.
-
-    Discovers and connects to stm32 USB endpoints.
-
-    Args:
-      vendor: usb vendor id of stm32 device.
-      product: usb product id of stm32 device.
-      interface: interface number ( 1 - 4 ) of stm32 device to use.
-      serialname: string of device serialname.
-      logger: none
-
-    Raises:
-      SusbError: An error accessing Susb object
-    """
-    self._vendor = vendor
-    self._product = product
-    self._interface = interface
-    self._serialname = serialname
-    self._find_device()
-
-  def _find_device(self):
-    """Set up the usb endpoint"""
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=self._vendor, idProduct=self._product,
-                             find_all=True)
-    dev_list = list(dev_g)
-
-    if not dev_list:
-      raise SusbError('USB device not found')
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if self._serialname:
-      for d in dev_list:
-        dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == self._serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError('USB device(%s) not found' % self._serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except StopIteration:
-        raise SusbError('USB device %04x:%04x not found' % (
-            self._vendor, self._product))
-
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
-
-    self._dev = dev
-
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface)
-    self._intf = intf
-    if not intf:
-      raise SusbError('Interface %04x:%04x - 0x%x not found' % (
-          self._vendor, self._product, self._interface))
-
-    # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel
-    # module driver that produces a ttyUSB, or direct endpoint access, but
-    # can't do both at the same time.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
-      dev.detach_kernel_driver(intf.bInterfaceNumber)
-
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
-
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
-
-  def close(self):
-    usb.util.dispose_resources(self._dev)
diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py
deleted file mode 100644
index 152c238bdf..0000000000
--- a/extra/tigertool/ecusb/tiny_servo_common.py
+++ /dev/null
@@ -1,174 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Utilities for using lightweight console functions."""
-
-# Note: This is a py2/3 compatible file.
-
-import datetime
-import errno
-import os
-import re
-import subprocess
-import sys
-import time
-
-import six
-
-from . import pty_driver
-from . import stm32uart
-
-
-def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
-
-
-class TinyServoError(Exception):
-  """Exceptions."""
-
-
-def log(output):
-  """Print output to console, logfiles can be added here.
-
-  Args:
-    output: string to output.
-  """
-  sys.stdout.write(output)
-  sys.stdout.write('\n')
-  sys.stdout.flush()
-
-def check_usb(vidpid, serialname=None):
-  """Check if |vidpid| is present on the system's USB.
-
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specified.
-
-  Returns: True if found, False, otherwise.
-  """
-  if serialname:
-    output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                     **get_subprocess_args())
-    m = re.search(r'^\s*iSerial\s+\d+\s+%s$' % serialname, output, flags=re.M)
-    if m:
-      return True
-
-    return False
-  else:
-    if subprocess.call(['lsusb', '-d', vidpid], stdout=open('/dev/null', 'w')):
-      return False
-  return True
-
-def check_usb_sn(vidpid):
-  """Return the serial number
-
-  Return the serial number of the first USB device with VID:PID vidpid,
-  or None if no device is found. This will not work well with two of
-  the same device attached.
-
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-
-  Returns: string serial number if found, None otherwise.
-  """
-  output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                   **get_subprocess_args())
-  m = re.search(r'^\s*iSerial\s+(.*)$', output, flags=re.M)
-  if m:
-    return m.group(1)
-
-  return None
-
-def wait_for_usb_remove(vidpid, serialname=None, timeout=None):
-  """Wait for USB device with vidpid to be removed.
-
-  Wrapper for wait_for_usb below
-  """
-  wait_for_usb(vidpid, serialname=serialname,
-               timeout=timeout, desiredpresence=False)
-
-def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True):
-  """Wait for usb device with vidpid to be present/absent.
-
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specificed.
-    timeout: timeout in seconds, None for no timeout.
-    desiredpresence: True for present, False for not present.
-
-  Raises:
-    TinyServoError: on timeout.
-  """
-  if timeout:
-    finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout)
-  while check_usb(vidpid, serialname) != desiredpresence:
-    time.sleep(.1)
-    if timeout:
-      if datetime.datetime.now() > finish:
-        raise TinyServoError('Timeout', 'Timeout waiting for USB %s' % vidpid)
-
-def do_serialno(serialno, pty):
-  """Set serialnumber 'serialno' via ec console 'pty'.
-
-  Commands are:
-  # > serialno set 1234
-  # Saving serial number
-  # Serial number: 1234
-
-  Args:
-    serialno: string serial number to set.
-    pty: tinyservo console to send commands.
-
-  Raises:
-    TinyServoError: on failure to set.
-    ptyError: on command interface error.
-  """
-  cmd = 'serialno set %s' % serialno
-  regex = 'Serial number:\s+(\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  sn = results[1].strip().strip('\n\r')
-
-  if sn == serialno:
-    log('Success !')
-    log('Serial set to %s' % sn)
-  else:
-    log('Serial number set to %s but saved as %s.' % (serialno, sn))
-    raise TinyServoError(
-        'Serial Number',
-        'Serial number set to %s but saved as %s.' % (serialno, sn))
-
-def setup_tinyservod(vidpid, interface, serialname=None, debuglog=False):
-  """Set up a pty
-
-  Set up a pty to the ec console in order
-  to send commands. Returns a pty_driver object.
-
-  Args:
-    vidpid: string vidpid of device to access.
-    interface: not used.
-    serialname: string serial name of device requested, optional.
-    debuglog: chatty printout (boolean)
-
-  Returns: pty object
-
-  Raises:
-    UsbError, SusbError: on device not found
-  """
-  vidstr, pidstr = vidpid.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
-  suart = stm32uart.Suart(vendor=vid, product=pid,
-                          interface=interface, serialname=serialname,
-                          debuglog=debuglog)
-  suart.run()
-  pty = pty_driver.ptyDriver(suart, [])
-
-  return pty
diff --git a/extra/tigertool/ecusb/tiny_servod.py b/extra/tigertool/ecusb/tiny_servod.py
deleted file mode 100644
index 632d9c3a20..0000000000
--- a/extra/tigertool/ecusb/tiny_servod.py
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Helper class to facilitate communication to servo ec console."""
-
-from ecusb import pty_driver
-from ecusb import stm32uart
-
-
-class TinyServod(object):
-  """Helper class to wrap a pty_driver with interface."""
-
-  def __init__(self, vid, pid, interface, serialname=None, debug=False):
-    """Build the driver and interface.
-
-    Args:
-      vid: servo device vid
-      pid: servo device pid
-      interface: which usb interface the servo console is on
-      serialname: the servo device serial (if available)
-    """
-    self._vid = vid
-    self._pid = pid
-    self._interface = interface
-    self._serial = serialname
-    self._debug = debug
-    self._init()
-
-  def _init(self):
-    self.suart = stm32uart.Suart(vendor=self._vid,
-                                 product=self._pid,
-                                 interface=self._interface,
-                                 serialname=self._serial,
-                                 debuglog=self._debug)
-    self.suart.run()
-    self.pty = pty_driver.ptyDriver(self.suart, [])
-
-  def reinitialize(self):
-    """Reinitialize the connect after a reset/disconnect/etc."""
-    self.close()
-    self._init()
-
-  def close(self):
-    """Close out the connection and release resources.
-
-    Note: if another TinyServod process or servod itself needs the same device
-          it's necessary to call this to ensure the usb device is available.
-    """
-    self.suart.close()
diff --git a/extra/tigertool/flash_dfu.sh b/extra/tigertool/flash_dfu.sh
deleted file mode 100755
index 7aa6c24f09..0000000000
--- a/extra/tigertool/flash_dfu.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-FLAGS_timeout=600
-IMG=${1:-tigertail.bin}
-
-echo "Flashing ${IMG}"
-
-error() {
-	printf "%s\n" "$*" >&2
-}
-
-die() {
-	[[ "$#*" == "0" ]] || error "$@"
-	exit 1
-}
-
-flash_stm32_dfu() {
-	local DFU_DEVICE=0483:df11
-	local ADDR=0x08000000
-
-	[[ -e "${IMG}" ]] || die "File ${IMG} not found!"
-
-	# Check for a suitable local dfu-util
-	local LOCAL_DFU_UTIL=$(which dfu-util)
-	if [[ -n "${LOCAL_DFU_UTIL}" ]]; then
-		DFU_VERSION=$("${LOCAL_DFU_UTIL}" -V | head -n1 | cut -d' ' -f2)
-		if [[ "${DFU_VERSION}" < "0.7" ]]; then
-			LOCAL_DFU_UTIL=""
-		fi
-	fi
-	local DFU_UTIL=${LOCAL_DFU_UTIL:-'./dfu-util'}
-
-	which "${DFU_UTIL}" &> /dev/null || die \
-		"no dfu-util util found.  Did you 'sudo emerge dfu-util'."
-
-	local dev_cnt=$(lsusb -d "${DFU_DEVICE}" | wc -l)
-	if [ $dev_cnt -eq 0 ] ; then
-		die "unable to locate dfu device at ${DFU_DEVICE}."
-	elif [ $dev_cnt -ne 1 ] ; then
-		die "too many dfu devices (${dev_cnt}). Disconnect all but one."
-	fi
-
-	local SIZE=$(wc -c "${IMG}" | cut -d' ' -f1)
-	# Remove read protection.
-	sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-		${DFU_UTIL} -a 0 -s ${ADDR}:${SIZE}:force:unprotect -D "${IMG}"
-	# Wait for mass-erase and reboot after unprotection.
-	sleep 1
-	# Actual image flashing.
-	sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-		$DFU_UTIL -a 0 -s ${ADDR}:${SIZE} -D "${IMG}"
-}
-
-flash_stm32_dfu
diff --git a/extra/tigertool/make_pkg.sh b/extra/tigertool/make_pkg.sh
deleted file mode 100755
index d2860f64c1..0000000000
--- a/extra/tigertool/make_pkg.sh
+++ /dev/null
@@ -1,28 +0,0 @@
-#!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Make sure we are in the correct dir.
-cd "$( dirname "${BASH_SOURCE[0]}" )" || exit
-
-# Clean and previous cruft.
-rm -rf build
-
-DEST=build/tigertool
-DATE=$(date +"%Y%m%d")
-
-mkdir -p "${DEST}"
-cp ../usb_serial/console.py "${DEST}"
-cp ../../../../../chroot/usr/bin/dfu-util "${DEST}"
-cp flash_dfu.sh "${DEST}"
-cp tigertool.py "${DEST}"
-
-cp -r ecusb "${DEST}"
-cp -r ../../../../../chroot/usr/lib64/python2.7/site-packages/usb "${DEST}"
-find "${DEST}" -name "*.py[co]" -delete
-cp -r ../usb_serial "${DEST}"
-
-(cd build; tar -czf tigertool_${DATE}.tgz tigertool)
-
-echo "Done packaging tigertool_${DATE}.tgz"
diff --git a/extra/tigertool/tigertool.py b/extra/tigertool/tigertool.py
deleted file mode 100755
index 79aa30c3a4..0000000000
--- a/extra/tigertool/tigertool.py
+++ /dev/null
@@ -1,266 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Script to control tigertail USB-C Mux board."""
-
-# Note: This is a py2/3 compatible file.
-
-import argparse
-import sys
-import time
-
-import ecusb.tiny_servo_common as c
-
-STM_VIDPID = '18d1:5027'
-serialno = 'Uninitialized'
-
-def do_mux(mux, pty):
-  """Set mux via ec console 'pty'.
-
-  Args:
-    mux: mux to connect to DUT, 'A', 'B', or 'off'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > mux A
-  # TYPE-C mux is A
-  """
-  validmux = ['A', 'B', 'off']
-  if mux not in validmux:
-    c.log('Mux setting %s invalid, try one of %s' % (mux, validmux))
-    return False
-
-  cmd = '\r\nmux %s\r\n' % mux
-  regex = 'TYPE\-C mux is ([^\s\r\n]*)\r'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  result = results[1].strip().strip('\n\r')
-
-  if result != mux:
-    c.log('Mux set to %s but saved as %s.' % (mux, result))
-    return False
-  c.log('Mux set to %s' % result)
-  return True
-
-def do_version(pty):
-  """Check version via ec console 'pty'.
-
-  Args:
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > version
-  # Chip:    stm stm32f07x
-  # Board:   0
-  # RO:      tigertail_v1.1.6749-74d1a312e
-  # RW:      tigertail_v1.1.6749-74d1a312e
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  #          2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com
-
-  """
-  cmd = '\r\nversion\r\n'
-  regex = 'RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+' \
-          '(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Version is %s' % results[3])
-  c.log('RO:    %s' % results[1])
-  c.log('RW:    %s' % results[2])
-  c.log('Date:  %s' % results[4])
-  c.log('Src:   %s' % results[5])
-
-  return True
-
-def do_check_serial(pty):
-  """Check serial via ec console 'pty'.
-
-  Args:
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > serialno
-  # Serial number: number
-  """
-  cmd = '\r\nserialno\r\n'
-  regex = 'Serial number: ([^\n\r]+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Serial is %s' % results[1])
-
-  return True
-
-
-def do_power(count, bus, pty):
-  """Check power usage via ec console 'pty'.
-
-  Args:
-    count: number of samples to capture
-    bus: rail to monitor, 'vbus', 'cc1', or 'cc2'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > ina 0
-  # Configuration: 4127
-  # Shunt voltage: 02c4 => 1770 uV
-  # Bus voltage  : 1008 => 5130 mV
-  # Power        : 0019 => 625 mW
-  # Current      : 0082 => 130 mA
-  # Calibration  : 0155
-  # Mask/Enable  : 0008
-  # Alert limit  : 0000
-  """
-  if bus == 'vbus':
-    ina = 0
-  if bus == 'cc1':
-    ina = 4
-  if bus == 'cc2':
-    ina = 1
-
-  start = time.time()
-
-  c.log('time,\tmV,\tmW,\tmA')
-
-  cmd = '\r\nina %s\r\n' % ina
-  regex = 'Bus voltage  : \S+ \S+ (\d+) mV\s+' \
-          'Power        : \S+ \S+ (\d+) mW\s+' \
-          'Current      : \S+ \S+ (\d+) mA'
-
-  for i in range(0, count):
-    results = pty._issue_cmd_get_results(cmd, [regex])[0]
-    c.log('%.2f,\t%s,\t%s\t%s' % (time.time() - start,
-          results[1], results[2], results[3]))
-
-  return True
-
-def do_reboot(pty):
-  """Reboot via ec console pty
-
-  Args:
-    pty: a pty object connected to tigertail
-
-  Command is: reboot.
-  """
-  cmd = '\r\nreboot\r\n'
-  regex = 'Rebooting'
-
-  try:
-    results = pty._issue_cmd_get_results(cmd, [regex])[0]
-    time.sleep(1)
-    c.log(results)
-  except Exception as e:
-    c.log(e)
-    return False
-
-  return True
-
-def do_sysjump(region, pty):
-  """Set region via ec console 'pty'.
-
-  Args:
-    region: ec code region to execute, 'ro' or 'rw'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > sysjump rw
-  """
-  validregion = ['ro', 'rw']
-  if region not in validregion:
-    c.log('Region setting %s invalid, try one of %s' % (
-        region, validregion))
-    return False
-
-  cmd = '\r\nsysjump %s\r\n' % region
-  try:
-    pty._issue_cmd(cmd)
-    time.sleep(1)
-  except Exception as e:
-    c.log(e)
-    return False
-
-  c.log('Region requested %s' % region)
-  return True
-
-def get_parser():
-  parser = argparse.ArgumentParser(
-      description=__doc__)
-  parser.add_argument('-s', '--serialno', type=str, default=None,
-                      help='serial number of board to use')
-  parser.add_argument('-b', '--bus', type=str, default='vbus',
-                     help='Which rail to log: [vbus|cc1|cc2]')
-  group = parser.add_mutually_exclusive_group()
-  group.add_argument('--setserialno', type=str, default=None,
-                     help='serial number to set on the board.')
-  group.add_argument('--check_serial', action='store_true',
-                     help='check serial number set on the board.')
-  group.add_argument('-m', '--mux', type=str, default=None,
-                     help='mux selection')
-  group.add_argument('-p', '--power', action='store_true',
-                     help='check VBUS')
-  group.add_argument('-l', '--powerlog', type=int, default=None,
-                     help='log VBUS')
-  group.add_argument('-r', '--sysjump', type=str, default=None,
-                     help='region selection')
-  group.add_argument('--reboot', action='store_true',
-                     help='reboot tigertail')
-  group.add_argument('--check_version', action='store_true',
-                     help='check tigertail version')
-  return parser
-
-def main(argv):
-  parser = get_parser()
-  opts = parser.parse_args(argv)
-
-  result = True
-
-  # Let's make sure there's a tigertail
-  # If nothing found in 5 seconds, fail.
-  c.wait_for_usb(STM_VIDPID, timeout=5., serialname=opts.serialno)
-
-  pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno)
-
-  if opts.bus not in ('vbus', 'cc1', 'cc2'):
-    c.log('Try --bus [vbus|cc1|cc2]')
-    result = False
-
-  elif opts.setserialno:
-    try:
-      c.do_serialno(opts.setserialno, pty)
-    except Exception:
-      result = False
-
-  elif opts.mux:
-    result &= do_mux(opts.mux, pty)
-
-  elif opts.sysjump:
-    result &= do_sysjump(opts.sysjump, pty)
-
-  elif opts.reboot:
-    result &= do_reboot(pty)
-
-  elif opts.check_version:
-    result &= do_version(pty)
-
-  elif opts.check_serial:
-    result &= do_check_serial(pty)
-
-  elif opts.power:
-    result &= do_power(1, opts.bus, pty)
-
-  elif opts.powerlog:
-    result &= do_power(opts.powerlog, opts.bus, pty)
-
-  if result:
-    c.log('PASS')
-  else:
-    c.log('FAIL')
-    exit(-1)
-
-
-if __name__ == '__main__':
-  sys.exit(main(sys.argv[1:]))
diff --git a/extra/touchpad_updater/Makefile b/extra/touchpad_updater/Makefile
deleted file mode 100644
index ebf9c3212d..0000000000
--- a/extra/touchpad_updater/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CC ?= gcc
-PKG_CONFIG ?= pkg-config
-PROGRAM := touchpad_updater
-SOURCE  := $(PROGRAM).c
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-#
-# Add libusb-1.0 required flags
-#
-LIBS    += $(shell $(PKG_CONFIG) --libs   libusb-1.0)
-CFLAGS  += $(shell $(PKG_CONFIG) --cflags libusb-1.0)
-
-$(PROGRAM): $(SOURCE) Makefile
-	$(CC) $(CFLAGS) $(SOURCE) $(LFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-
-clean:
-	rm -rf $(PROGRAM) *~
diff --git a/extra/touchpad_updater/touchpad_updater.c b/extra/touchpad_updater/touchpad_updater.c
deleted file mode 100644
index 716ded00f5..0000000000
--- a/extra/touchpad_updater/touchpad_updater.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <getopt.h>
-#include <poll.h>
-#include <signal.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/select.h>
-#include <unistd.h>
-
-#include <libusb.h>
-
-/* Command line options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5022;			/* Hammer */
-static uint8_t ep_num = 4;			/* console endpoint */
-static uint8_t extended_i2c_exercise;		/* non-zero to exercise */
-static char *firmware_binary = "144.0_2.0.bin";	/* firmware blob */
-
-/* Firmware binary blob related */
-#define MAX_FW_PAGE_SIZE	512
-#define MAX_FW_PAGE_COUNT	1024
-#define MAX_FW_SIZE		(128 * 1024)
-
-static uint8_t fw_data[MAX_FW_SIZE];
-int fw_page_count;
-int fw_page_size;
-int fw_size;
-uint8_t ic_type;
-int iap_version;
-
-/* Utility functions */
-static int le_bytes_to_int(uint8_t *buf)
-{
-	return buf[0] + (int)(buf[1] << 8);
-}
-
-/* Command line parsing related */
-static char *progname;
-static char *short_opts = ":f:v:p:e:hd";
-static const struct option long_opts[] = {
-	/* name    hasarg *flag val */
-	{"file",     1,   NULL, 'f'},
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{"debug",    0,   NULL, 'd'},
-	{NULL,       0,   NULL, 0},
-};
-
-static void usage(int errs)
-{
-	printf("\nUsage: %s [options]\n"
-	       "\n"
-	       "Firmware updater over USB for trackpad under hammer\n"
-	       "\n"
-	       "Options:\n"
-	       "\n"
-	       "  -f,--file   STR         Firmware binary (default %s)\n"
-	       "  -v,--vid    HEXVAL      Vendor ID (default %04x)\n"
-	       "  -p,--pid    HEXVAL      Product ID (default %04x)\n"
-	       "  -e,--ep     NUM         Endpoint (default %d)\n"
-	       "  -d,--debug              Exercise extended read I2C over USB\n"
-	       "                          and print verbose debug messages.\n"
-	       "  -h,--help               Show this message\n"
-	       "\n", progname, firmware_binary, vid, pid, ep_num);
-
-	exit(!!errs);
-}
-
-static void parse_cmdline(int argc, char *argv[])
-{
-	char *e = 0;
-	int i, errorcnt = 0;
-
-	progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;				/* quiet, you */
-	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
-		switch (i) {
-		case 'f':
-			firmware_binary = optarg;
-			break;
-		case 'p':
-			pid = (uint16_t) strtoull(optarg, &e, 16);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'v':
-			vid = (uint16_t) strtoull(optarg, &e, 16);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'e':
-			ep_num = (uint8_t) strtoull(optarg, &e, 0);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'd':
-			extended_i2c_exercise = 1;
-			break;
-		case 'h':
-			usage(errorcnt);
-			break;
-		case 0:				/* auto-handled option */
-			break;
-		case '?':
-			if (optopt)
-				printf("Unrecognized option: -%c\n", optopt);
-			else
-				printf("Unrecognized option: %s\n",
-				       argv[optind - 1]);
-			errorcnt++;
-			break;
-		case ':':
-			printf("Missing argument to %s\n", argv[optind - 1]);
-			errorcnt++;
-			break;
-		default:
-			printf("Internal error at %s:%d\n", __FILE__, __LINE__);
-			exit(1);
-		}
-	}
-
-	if (errorcnt)
-		usage(errorcnt);
-
-}
-
-/* USB transfer related */
-static uint8_t rx_buf[1024];
-static uint8_t tx_buf[1024];
-
-static struct libusb_device_handle *devh;
-static struct libusb_transfer *rx_transfer;
-static struct libusb_transfer *tx_transfer;
-
-static int claimed_iface;
-static int iface_num = -1;
-static int do_exit;
-
-static void request_exit(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-	do_exit++;    /* Why need this ? */
-
-	if (tx_transfer)
-		libusb_free_transfer(tx_transfer);
-	if (rx_transfer)
-		libusb_free_transfer(rx_transfer);
-	if (devh) {
-		if (claimed_iface)
-			libusb_release_interface(devh, iface_num);
-		libusb_close(devh);
-	}
-	libusb_exit(NULL);
-	exit(1);
-}
-
-#define DIE(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
-
-static void sighandler(int signum)
-{
-	request_exit("caught signal %d: %s\n", signum, strsignal(signum));
-}
-
-static int find_interface_with_endpoint(int want_ep_num)
-{
-	int iface_num = -1;
-	int r, i, j, k;
-	struct libusb_device *dev;
-	struct libusb_config_descriptor *conf = 0;
-	const struct libusb_interface *iface0;
-	const struct libusb_interface_descriptor *iface;
-	const struct libusb_endpoint_descriptor *ep;
-
-	dev = libusb_get_device(devh);
-	r = libusb_get_active_config_descriptor(dev, &conf);
-	if (r < 0) {
-		DIE("get_active_config", r);
-		return -1;
-	}
-
-	for (i = 0; i < conf->bNumInterfaces; i++) {
-		iface0 = &conf->interface[i];
-		for (j = 0; j < iface0->num_altsetting; j++) {
-			iface = &iface0->altsetting[j];
-			for (k = 0; k < iface->bNumEndpoints; k++) {
-				ep = &iface->endpoint[k];
-				if (ep->bEndpointAddress == want_ep_num) {
-					iface_num = i;
-					break;
-				}
-			}
-		}
-	}
-
-	libusb_free_config_descriptor(conf);
-	return iface_num;
-}
-
-static void init_with_libusb(void)
-{
-	int r = 1;
-
-	printf("init usb interface\n");
-	r = libusb_init(NULL);
-	if (r < 0)
-		DIE("init", r);
-
-	printf("open_device %04x:%04x\n", vid, pid);
-	devh = libusb_open_device_with_vid_pid(NULL, vid, pid);
-	if (!devh)
-		request_exit("can't find device\n");
-
-	iface_num = find_interface_with_endpoint(ep_num);
-	if (iface_num < 0)
-		request_exit("can't find interface owning EP %d\n", ep_num);
-
-	printf("claim_interface %d to use endpoint %d\n", iface_num, ep_num);
-	r = libusb_claim_interface(devh, iface_num);
-	if (r < 0)
-		DIE("claim interface", r);
-	claimed_iface = 1;
-}
-
-static void register_sigaction(void)
-{
-	struct sigaction sigact;
-	sigact.sa_handler = sighandler;
-	sigemptyset(&sigact.sa_mask);
-	sigact.sa_flags = 0;
-	sigaction(SIGINT, &sigact, NULL);
-	sigaction(SIGTERM, &sigact, NULL);
-	sigaction(SIGQUIT, &sigact, NULL);
-}
-
-/* Transfer over libusb */
-#define I2C_PORT_ON_HAMMER		0x00
-#define I2C_ADDRESS_ON_HAMMER		0x15
-
-static int check_read_status(int r, int expected, int actual)
-{
-	int i;
-	if (r)
-		printf("Warning: libusb_bulk_transfer return error : %d\n", r);
-	if (actual != (expected + 4)) {
-		printf("Warning: Not reading back %d bytes.\n", expected);
-		r = 1;
-	}
-
-	/* Check transaction status as defined in usb_i2c.h */
-	for (i = 0; i < 4; ++i)
-		if (rx_buf[i] != 0)
-			break;
-
-	if (i != 4) {
-		r = le_bytes_to_int(rx_buf);
-		printf("Warning: Defined error code (%d) returned.\n", r);
-	}
-
-	if (r || extended_i2c_exercise) {
-		printf("\nDumping the receive buffer:\n");
-		printf("  Recv %d bytes from USB hosts.\n", actual);
-		for (i = 0; i < actual; ++i)
-			printf("    [%2d]bytes: 0x%0x\n", i, rx_buf[i]);
-	}
-	return r;
-}
-
-#define MAX_USB_PACKET_SIZE		64
-#define PRIMITIVE_READING_SIZE		60
-
-static int libusb_single_write_and_read(
-		const uint8_t *to_write, uint16_t write_length,
-		uint8_t *to_read, uint16_t read_length)
-{
-	int r;
-	int tx_ready;
-	int remains;
-	int sent_bytes = 0;
-	int actual_length = -1;
-	int offset = read_length > PRIMITIVE_READING_SIZE ? 6 : 4;
-	tx_transfer = rx_transfer = 0;
-
-	memmove(tx_buf + offset, to_write, write_length);
-	tx_buf[0] = I2C_PORT_ON_HAMMER | ((write_length >> 8) << 4);
-	tx_buf[1] = I2C_ADDRESS_ON_HAMMER;
-	tx_buf[2] = write_length & 0xff;
-	if (read_length > PRIMITIVE_READING_SIZE) {
-		tx_buf[3] = (read_length & 0x7f) | (1 << 7);
-		tx_buf[4] = read_length >> 7;
-		if (extended_i2c_exercise) {
-			printf("Triggering extended reading."
-				"rc:%0x, rc1:%0x\n",
-				tx_buf[3], tx_buf[4]);
-			printf("Expecting %d Bytes.\n",
-				(tx_buf[3] & 0x7f) | (tx_buf[4] << 7));
-		}
-	} else {
-		tx_buf[3] = read_length;
-	}
-
-	/*
-	 * TODO: This loop is probably not required as we write the whole block
-	 * in one transaction.
-	 */
-	while (sent_bytes < (offset + write_length)) {
-		tx_ready = remains = (offset + write_length) - sent_bytes;
-
-		r = libusb_bulk_transfer(devh,
-				(ep_num | LIBUSB_ENDPOINT_OUT),
-				tx_buf + sent_bytes, tx_ready,
-				&actual_length, 5000);
-		if (r == 0 && actual_length == tx_ready) {
-			r = libusb_bulk_transfer(devh,
-					(ep_num | LIBUSB_ENDPOINT_IN),
-					rx_buf, sizeof(rx_buf),
-					&actual_length, 5000);
-		}
-		r = check_read_status(
-				r, (remains == tx_ready) ? read_length : 0,
-				actual_length);
-		if (r)
-			break;
-		sent_bytes += tx_ready;
-	}
-	return r;
-}
-
-/* Control Elan trackpad I2C over USB */
-#define ETP_I2C_INF_LENGTH		2
-
-static int elan_write_and_read(
-		int reg, uint8_t *buf, int read_length,
-		int with_cmd, int cmd)
-{
-
-	tx_buf[0] = (reg >> 0) & 0xff;
-	tx_buf[1] = (reg >> 8) & 0xff;
-	if (with_cmd) {
-		tx_buf[2] = (cmd >> 0) & 0xff;
-		tx_buf[3] = (cmd >> 8) & 0xff;
-	}
-	return libusb_single_write_and_read(
-			tx_buf, with_cmd ? 4 : 2, rx_buf, read_length);
-}
-
-static int elan_read_block(int reg, uint8_t *buf, int read_length)
-{
-	return elan_write_and_read(reg, buf, read_length, 0, 0);
-}
-
-static int elan_read_cmd(int reg)
-{
-	return elan_read_block(reg, rx_buf, ETP_I2C_INF_LENGTH);
-}
-
-static int elan_write_cmd(int reg, int cmd)
-{
-	return elan_write_and_read(reg, rx_buf, 0, 1, cmd);
-}
-
-/* Elan trackpad firmware information related */
-#define ETP_I2C_IAP_VERSION_CMD		0x0110
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_IAP_CHECKSUM_CMD	0x0315
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
-
-static int elan_get_version(int is_iap)
-{
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_VERSION_CMD : ETP_I2C_FW_VERSION_CMD);
-	return le_bytes_to_int(rx_buf + 4);
-}
-
-static void elan_get_ic_page_count(void)
-{
-	elan_read_cmd(ETP_I2C_OSM_VERSION_CMD);
-
-	ic_type = rx_buf[5];
-	printf("ic_type: %02x\n", ic_type);
-
-	switch (ic_type) {
-	case 0x09:
-		fw_page_count = 768;
-		break;
-	case 0x0D:
-		fw_page_count = 896;
-		break;
-	case 0x00:
-	case 0x10:
-	case 0x14:
-		fw_page_count = 1024;
-		break;
-	default:
-		request_exit("The IC type is not supported.\n");
-	}
-
-	iap_version = elan_get_version(1);
-	if (ic_type == 0x14 && iap_version >= 2) {
-		fw_page_count /= 8;
-		fw_page_size = 512;
-	} else if (ic_type >= 0x0D && iap_version >= 1) {
-		fw_page_count /= 2;
-		fw_page_size = 128;
-	} else {
-		fw_page_size = 64;
-	}
-}
-
-static int elan_get_checksum(int is_iap)
-{
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_CHECKSUM_CMD : ETP_I2C_FW_CHECKSUM_CMD);
-	return le_bytes_to_int(rx_buf + 4);
-}
-
-static uint16_t elan_get_fw_info(void)
-{
-	int fw_version = -1;
-	uint16_t iap_checksum = 0xffff;
-	uint16_t fw_checksum = 0xffff;
-
-	printf("Querying device info...\n");
-	fw_checksum = elan_get_checksum(0);
-	iap_checksum = elan_get_checksum(1);
-	fw_version = elan_get_version(0);
-	iap_version = elan_get_version(1);
-	printf("IAP  version: %4x, FW  version: %4x\n",
-			iap_version, fw_version);
-	printf("IAP checksum: %4x, FW checksum: %4x\n",
-			iap_checksum, fw_checksum);
-	return fw_checksum;
-}
-
-/* Update preparation */
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		(1 << 9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
-#define ETP_I2C_IAP_TYPE_CMD		0x0304
-
-static int elan_in_main_mode(void)
-{
-	elan_read_cmd(ETP_I2C_IAP_CTRL_CMD);
-	return le_bytes_to_int(rx_buf + 4) & ETP_I2C_MAIN_MODE_ON;
-}
-
-static int elan_read_write_iap_type(void)
-{
-	for (int retry = 0; retry < 3; ++retry) {
-		uint16_t val;
-
-		if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD,
-				   fw_page_size / 2))
-			return -1;
-
-		if (elan_read_cmd(ETP_I2C_IAP_TYPE_CMD))
-			return -1;
-
-		val = le_bytes_to_int(rx_buf + 4);
-		if (val == fw_page_size / 2) {
-			printf("%s: OK\n", __func__);
-			return 0;
-		}
-
-	}
-	return -1;
-}
-
-static void elan_prepare_for_update(void)
-{
-	printf("%s\n", __func__);
-
-	int initial_mode = elan_in_main_mode();
-	if (!initial_mode) {
-		printf("In IAP mode, reset IC.\n");
-		elan_write_cmd(ETP_I2C_IAP_RESET_CMD, ETP_I2C_IAP_RESET);
-		usleep(30 * 1000);
-	}
-
-	/* Send the passphrase */
-	elan_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
-	usleep((initial_mode ? 100 : 30) * 1000);
-
-	/* We should be in the IAP mode now */
-	if (elan_in_main_mode())
-		request_exit("Failure to enter IAP mode, still in main mode\n");
-
-	if (ic_type >= 0x0D && iap_version >= 1) {
-		if (elan_read_write_iap_type())
-			request_exit("Failure to set IAP mode\n");
-	}
-
-	/* Send the passphrase again */
-	elan_write_cmd(ETP_I2C_IAP_CMD, ETP_I2C_IAP_PASSWORD);
-	usleep(30 * 1000);
-
-	/* Verify the password */
-	if (elan_read_cmd(ETP_I2C_IAP_CMD))
-		request_exit("cannot read iap password.\n");
-	if (le_bytes_to_int(rx_buf + 4) != ETP_I2C_IAP_PASSWORD)
-		request_exit("Got an unexpected IAP password %4x\n",
-			le_bytes_to_int(rx_buf + 4));
-}
-
-/* Firmware block update */
-#define ETP_IAP_START_ADDR		0x0083
-
-static uint16_t elan_calc_checksum(uint8_t *data, int length)
-{
-	uint16_t checksum = 0;
-	for (int i = 0; i < length; i += 2)
-		checksum += ((uint16_t)(data[i+1]) << 8) | (data[i]);
-	return checksum;
-}
-
-static int elan_get_iap_addr(void)
-{
-	return le_bytes_to_int(fw_data + ETP_IAP_START_ADDR * 2) * 2;
-}
-
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
-
-#define ETP_FW_IAP_PAGE_ERR		(1 << 5)
-#define ETP_FW_IAP_INTF_ERR		(1 << 4)
-
-static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
-{
-	uint8_t page_store[MAX_FW_PAGE_SIZE + 4];
-	int rv;
-
-	page_store[0] = ETP_I2C_IAP_REG_L;
-	page_store[1] = ETP_I2C_IAP_REG_H;
-	memcpy(page_store + 2, raw_data, fw_page_size);
-	page_store[fw_page_size + 2 + 0] = (checksum >> 0) & 0xff;
-	page_store[fw_page_size + 2 + 1] = (checksum >> 8) & 0xff;
-
-	rv = libusb_single_write_and_read(
-			page_store, fw_page_size + 4, rx_buf, 0);
-	if (rv)
-		return rv;
-	usleep((fw_page_size >= 512 ? 50 : 35) * 1000);
-	elan_read_cmd(ETP_I2C_IAP_CTRL_CMD);
-	rv = le_bytes_to_int(rx_buf + 4);
-	if (rv & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR)) {
-		printf("IAP reports failed write : %x\n", rv);
-		return rv;
-	}
-	return 0;
-}
-
-
-static uint16_t elan_update_firmware(void)
-{
-	uint16_t checksum = 0, block_checksum;
-	int rv;
-
-	printf("%s\n", __func__);
-
-	for (int i = elan_get_iap_addr(); i < fw_size; i += fw_page_size) {
-		printf("\rUpdating page %3d...", i / fw_page_size);
-		fflush(stdout);
-		block_checksum = elan_calc_checksum(fw_data + i, fw_page_size);
-		rv = elan_write_fw_block(fw_data + i, block_checksum);
-		if (rv)
-			request_exit("Failed to update.\n");
-		checksum += block_checksum;
-		printf(" Updated, checksum: %d", checksum);
-		fflush(stdout);
-	}
-	return checksum;
-}
-
-static void pretty_print_buffer(uint8_t *buf, int len)
-{
-	int i;
-
-	printf("Buffer = 0x");
-	for (i = 0; i < len; ++i)
-		printf("%02X", buf[i]);
-	printf("\n");
-}
-
-int main(int argc, char *argv[])
-{
-	uint16_t local_checksum;
-	uint16_t remote_checksum;
-
-	parse_cmdline(argc, argv);
-	init_with_libusb();
-	register_sigaction();
-
-	/*
-	 * Judge IC type  and get page count first.
-	 * Then check the FW file.
-	 */
-	elan_get_ic_page_count();
-	fw_size = fw_page_count * fw_page_size;
-	printf("FW has %d bytes x %d pages\n", fw_page_size, fw_page_count);
-
-	/* Read the FW file */
-	FILE *f = fopen(firmware_binary, "rb");
-	if (!f)
-		request_exit("Cannot find binary: %s\n", firmware_binary);
-	if (fread(fw_data, 1, fw_size, f) != (unsigned int)fw_size)
-		request_exit("binary size mismatch, expect %d\n", fw_size);
-
-	/*
-	 * It is possible that you are not able to get firmware info. This
-	 * might due to an incomplete update last time
-	 */
-	elan_get_fw_info();
-
-	/* Trigger an I2C transaction of expecting reading of 633 bytes. */
-	if (extended_i2c_exercise) {
-		tx_buf[0] = 0x05;
-		tx_buf[1] = 0x00;
-		tx_buf[2] = 0x3C;
-		tx_buf[3] = 0x02;
-		tx_buf[4] = 0x06;
-		tx_buf[5] = 0x00;
-		libusb_single_write_and_read(tx_buf, 6, rx_buf, 633);
-		pretty_print_buffer(rx_buf, 637);
-	}
-
-	/* Get the trackpad ready for receiving update */
-	elan_prepare_for_update();
-
-	local_checksum = elan_update_firmware();
-	/* Wait for a reset */
-	usleep(600 * 1000);
-	remote_checksum = elan_get_checksum(1);
-	if (remote_checksum != local_checksum)
-		printf("checksum diff local=[%04X], remote=[%04X]\n",
-				local_checksum, remote_checksum);
-
-	/* Print the updated firmware information */
-	elan_get_fw_info();
-	return 0;
-}
diff --git a/extra/usb_console/.gitignore b/extra/usb_console/.gitignore
deleted file mode 100644
index efee63e87e..0000000000
--- a/extra/usb_console/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-usb_console
diff --git a/extra/usb_console/Makefile b/extra/usb_console/Makefile
deleted file mode 100644
index bddca1d0a2..0000000000
--- a/extra/usb_console/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-PROGRAM := usb_console
-SOURCE  := $(PROGRAM).c
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-#
-# Add libusb-1.0 required flags
-#
-LIBS    += $(shell pkg-config --libs   libusb-1.0)
-CFLAGS  += $(shell pkg-config --cflags libusb-1.0)
-
-$(PROGRAM): $(SOURCE) Makefile
-	gcc $(CFLAGS) $(SOURCE) $(LFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-
-clean:
-	rm -rf $(PROGRAM) *~
diff --git a/extra/usb_console/usb_console.c b/extra/usb_console/usb_console.c
deleted file mode 100644
index e4f8ea504f..0000000000
--- a/extra/usb_console/usb_console.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <getopt.h>
-#include <poll.h>
-#include <signal.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/select.h>
-#include <unistd.h>
-
-#include <libusb.h>
-
-/* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x500f;			/* discovery-stm32f072 */
-static uint8_t ep_num = 4;			/* console endpoint */
-
-static unsigned char rx_buf[1024];		/* much too big */
-static unsigned char tx_buf[1024];		/* much too big */
-static const struct libusb_pollfd **usb_fds;
-static struct libusb_device_handle *devh;
-static struct libusb_transfer *rx_transfer;
-static struct libusb_transfer *tx_transfer;
-static int tx_ready;
-static int do_exit;
-
-static void request_exit(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-	do_exit++;
-}
-
-#define BOO(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
-
-static void sighandler(int signum)
-{
-	request_exit("caught signal %d: %s\n", signum, strsignal(signum));
-}
-
-#if 0
-static void show_xfer(const char *msg, struct libusb_transfer *t)
-{
-	printf("%s: f=%02x ep=%02x type=%d status=%d len=%d actlen=%d\n", msg,
-	       t->flags,
-	       t->endpoint, t->type, t->status, t->length, t->actual_length);
-}
-#endif
-
-static void LIBUSB_CALL cb_rx(struct libusb_transfer *transfer)
-{
-	int r;
-
-	if (transfer->actual_length) {
-		transfer->buffer[transfer->actual_length] = '\0';
-		fputs((char *)transfer->buffer, stdout);
-		fflush(stdout);
-	}
-
-	if (transfer->status == LIBUSB_TRANSFER_CANCELLED) {
-		printf("rx_transfer cancelled\n");
-		if (rx_transfer)
-			libusb_free_transfer(rx_transfer);
-		rx_transfer = NULL;
-		return;
-	}
-
-	/* Try again */
-	if (!do_exit) {
-		r = libusb_submit_transfer(rx_transfer);
-		if (r < 0)
-			BOO("resubmit rx_transfer failed", r);
-	}
-}
-
-static void LIBUSB_CALL cb_tx(struct libusb_transfer *transfer)
-{
-	if (transfer->status == LIBUSB_TRANSFER_CANCELLED) {
-		if (tx_transfer)
-			libusb_free_transfer(tx_transfer);
-		tx_transfer = NULL;
-		request_exit("tx_transfer cancelled\n");
-		return;
-	}
-
-	if (tx_ready != transfer->actual_length)
-		printf("%s: only sent %d/%d bytes\n", __func__,
-		       transfer->actual_length, tx_ready);
-
-	tx_ready = 0;
-}
-
-static void send_tx(int len)
-{
-	int r;
-
-	libusb_fill_bulk_transfer(tx_transfer, devh,
-				  ep_num, tx_buf, len, cb_tx, NULL, 0);
-
-	r = libusb_submit_transfer(tx_transfer);
-	if (r < 0)
-		BOO("submit tx_transfer failed", r);
-}
-
-static void handle_stdin(void)
-{
-	static unsigned int i;
-	int n;
-
-	for (; i < sizeof(tx_buf) - 1; i++) {
-		n = read(0, tx_buf + i, 1);
-		if (n == 0) {
-			request_exit("EOF on stdin\n");
-			return;
-		}
-		if (n < 0) {
-			request_exit("stdin: %s\n", strerror(errno));
-			return;
-		}
-
-		if (tx_buf[i] == '\n') {
-			i++;
-			tx_buf[i] = '\0';
-			break;
-		}
-	}
-
-	tx_ready = strlen((char *)tx_buf) + 1;
-	send_tx(tx_ready);
-	i = 0;
-}
-
-static void handle_libusb(void)
-{
-	struct timeval tv = { 0, 0 };
-	int r;
-
-	r = libusb_handle_events_timeout_completed(NULL, &tv, &do_exit);
-	if (r < 0)
-		BOO("libusb event problem", r);
-}
-
-static int wait_for_stuff_to_happen(void)
-{
-	int i, r, nfds = 0;
-	fd_set readset, writeset;
-	struct timeval tv = { 1, 0 };
-
-	if (!usb_fds) {
-		request_exit("No usb_fds to watch\n");
-		return -1;
-	}
-
-	FD_ZERO(&readset);
-	FD_ZERO(&writeset);
-	/* always watch stdin */
-	FD_SET(0, &readset);
-
-	for (i = 0; usb_fds[i]; i++) {
-		int fd = usb_fds[i]->fd;
-		short events = usb_fds[i]->events;
-		if (fd > nfds)
-			nfds = fd;
-
-		if (events & POLLIN)
-			FD_SET(fd, &readset);
-		if (events & POLLOUT)
-			FD_SET(fd, &writeset);
-	}
-
-	r = select(nfds + 1, &readset, &writeset, NULL, &tv);
-	if (r < 0) {
-		request_exit("select: %s\n", strerror(errno));
-		return -1;
-	}
-
-	if (r == 0)				/* timed out */
-		return 0;
-
-	/* Ignore stdin until we've finished sending the current line */
-	if (!tx_ready && FD_ISSET(0, &readset))
-		return 1;
-
-	/* libusb, then */
-	return 2;
-}
-
-static int find_interface_with_endpoint(int want_ep_num)
-{
-	int iface_num = -1;
-	int r, i, j, k;
-	struct libusb_device *dev;
-	struct libusb_config_descriptor *conf = 0;
-	const struct libusb_interface *iface0;
-	const struct libusb_interface_descriptor *iface;
-	const struct libusb_endpoint_descriptor *ep;
-
-	dev = libusb_get_device(devh);
-	r = libusb_get_active_config_descriptor(dev, &conf);
-	if (r < 0) {
-		BOO("get_active_config", r);
-		return -1;
-	}
-
-	for (i = 0; i < conf->bNumInterfaces; i++) {
-		iface0 = &conf->interface[i];
-		for (j = 0; j < iface0->num_altsetting; j++) {
-			iface = &iface0->altsetting[j];
-			for (k = 0; k < iface->bNumEndpoints; k++) {
-				ep = &iface->endpoint[k];
-				if (ep->bEndpointAddress == want_ep_num) {
-					iface_num = i;
-					break;
-				}
-			}
-		}
-	}
-
-	libusb_free_config_descriptor(conf);
-	return iface_num;
-}
-
-static char *progname;
-static char *short_opts = ":v:p:e:h";
-static const struct option long_opts[] = {
-	/* name    hasarg *flag val */
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{NULL,       0,   NULL, 0},
-};
-
-static void usage(int errs)
-{
-	printf("\nUsage: %s [options]\n"
-	       "\n"
-	       "A very simple serial console emulator\n"
-	       "\n"
-	       "Options:\n"
-	       "\n"
-	       "  -v,--vid    HEXVAL      Vendor ID (default %04x)\n"
-	       "  -p,--pid    HEXVAL      Product ID (default %04x)\n"
-	       "  -e,--ep     NUM         Endpoint (default %d)\n"
-	       "  -h,--help               Show this message\n"
-	       "\n", progname, vid, pid, ep_num);
-
-	exit(!!errs);
-}
-
-int main(int argc, char *argv[])
-{
-	struct sigaction sigact;
-	int iface_num;
-	int claimed_iface = 0;
-	int r = 1;
-	int errorcnt = 0;
-	char *e = 0;
-	int i;
-
-	progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;				/* quiet, you */
-	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
-		switch (i) {
-		case 'p':
-			pid = (uint16_t) strtoull(optarg, &e, 16);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'v':
-			vid = (uint16_t) strtoull(optarg, &e, 16);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'e':
-			ep_num = (uint8_t) strtoull(optarg, &e, 0);
-			if (!*optarg || (e && *e)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'h':
-			usage(errorcnt);
-			break;
-		case 0:				/* auto-handled option */
-			break;
-		case '?':
-			if (optopt)
-				printf("Unrecognized option: -%c\n", optopt);
-			else
-				printf("Unrecognized option: %s\n",
-				       argv[optind - 1]);
-			errorcnt++;
-			break;
-		case ':':
-			printf("Missing argument to %s\n", argv[optind - 1]);
-			errorcnt++;
-			break;
-		default:
-			printf("Internal error at %s:%d\n", __FILE__, __LINE__);
-			exit(1);
-		}
-	}
-
-	if (errorcnt)
-		usage(errorcnt);
-
-	printf("init\n");
-	r = libusb_init(NULL);
-	if (r < 0) {
-		BOO("init", r);
-		exit(1);
-	}
-
-	printf("open_device %04x:%04x\n", vid, pid);
-	devh = libusb_open_device_with_vid_pid(NULL, vid, pid);
-	if (!devh) {
-		printf("can't find device\n");
-		goto out;
-	}
-
-	iface_num = find_interface_with_endpoint(ep_num);
-	if (iface_num < 0) {
-		printf("can't find interface owning EP %d\n", ep_num);
-		goto out;
-	}
-	/* NOTE: The EP might be on an alternate interface. We should switch
-	 * to the correct one. */
-
-	printf("claim_interface %d to use endpoint %d\n", iface_num, ep_num);
-	r = libusb_claim_interface(devh, iface_num);
-	if (r < 0) {
-		BOO("claim interface", r);
-		goto out;
-	}
-	claimed_iface = 1;
-
-	sigact.sa_handler = sighandler;
-	sigemptyset(&sigact.sa_mask);
-	sigact.sa_flags = 0;
-	sigaction(SIGINT, &sigact, NULL);
-	sigaction(SIGTERM, &sigact, NULL);
-	sigaction(SIGQUIT, &sigact, NULL);
-
-	printf("alloc_transfers\n");
-	rx_transfer = libusb_alloc_transfer(0);
-	if (!rx_transfer) {
-		printf("can't alloc rx_transfer");
-		goto out;
-	}
-	libusb_fill_bulk_transfer(rx_transfer, devh,
-				  0x80 | ep_num,
-				  rx_buf, sizeof(rx_buf), cb_rx, NULL, 0);
-
-	tx_transfer = libusb_alloc_transfer(0);
-	if (!tx_transfer) {
-		printf("can't alloc tx_transfer");
-		goto out;
-	}
-
-	printf("get_pollfds\n");
-	usb_fds = libusb_get_pollfds(NULL);
-	if (!usb_fds) {
-		printf("can't get usb_fds\n");
-		goto out;
-	}
-
-	printf("submit rx_transfer\n");
-	r = libusb_submit_transfer(rx_transfer);
-	if (r < 0) {
-		BOO("submit rx_transfer", r);
-		goto out;
-	}
-
-	printf("READY\n-------\n");
-	while (!do_exit) {
-		r = wait_for_stuff_to_happen();
-		switch (r) {
-		case 0:	/* timed out */
-			/* printf("."); */
-			/* fflush(stdout); */
-			break;
-		case 1:	/* stdin ready */
-			handle_stdin();
-			break;
-		case 2:	/* libusb ready */
-			handle_libusb();
-			break;
-		}
-	}
-
-	printf("-------\nshutting down\n");
-
-	r = libusb_cancel_transfer(rx_transfer);
-	if (r < 0) {
-		BOO("cancel rx_transfer", r);
-		if (rx_transfer)
-			libusb_free_transfer(rx_transfer);
-		rx_transfer = 0;
-	}
-
-	if (tx_ready) {
-		r = libusb_cancel_transfer(tx_transfer);
-		if (r < 0) {
-			BOO("cancel tx_transfer", r);
-			if (tx_transfer)
-				libusb_free_transfer(tx_transfer);
-			tx_transfer = 0;
-		}
-	}
-
-	while (rx_transfer) {
-		printf("draining events...\n");
-		r = libusb_handle_events(NULL);
-		if (r < 0) {
-			printf("Huh: %s\n", libusb_error_name(r));
-			break;
-		}
-	}
-
-	printf("bye\n");
-	r = 0;
- out:
-	if (tx_transfer)
-		libusb_free_transfer(tx_transfer);
-	if (rx_transfer)
-		libusb_free_transfer(rx_transfer);
-
-	if (devh) {
-		if (claimed_iface)
-			libusb_release_interface(devh, iface_num);
-		libusb_close(devh);
-	}
-	libusb_exit(NULL);
-
-	return r;
-}
diff --git a/extra/usb_gpio/.gitignore b/extra/usb_gpio/.gitignore
deleted file mode 100644
index 239f1ed4d8..0000000000
--- a/extra/usb_gpio/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-usb_gpio
diff --git a/extra/usb_gpio/Makefile b/extra/usb_gpio/Makefile
deleted file mode 100644
index 644e3ee70f..0000000000
--- a/extra/usb_gpio/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-PROGRAM := usb_gpio
-SOURCE  := $(PROGRAM).c
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-#
-# Add libusb-1.0 required flags
-#
-LIBS    += $(shell pkg-config --libs   libusb-1.0)
-CFLAGS  += $(shell pkg-config --cflags libusb-1.0)
-
-$(PROGRAM): $(SOURCE) Makefile
-	gcc $(CFLAGS) $(SOURCE) $(LFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-
-clean:
-	rm -rf $(PROGRAM) *~
diff --git a/extra/usb_gpio/usb_gpio.c b/extra/usb_gpio/usb_gpio.c
deleted file mode 100644
index 8973f3d304..0000000000
--- a/extra/usb_gpio/usb_gpio.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <libusb.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#define CHECK(expression)					\
-	({							\
-		int error__ = (expression);			\
-								\
-		if (error__ != 0) {				\
-			fprintf(stderr,				\
-				"libusb error: %s:%d %s\n",	\
-				__FILE__,			\
-				__LINE__,			\
-				libusb_error_name(error__));	\
-			return error__;				\
-		}						\
-								\
-		error__;					\
-	})
-
-#define TRANSFER_TIMEOUT_MS 100
-
-static int gpio_write(libusb_device_handle *device,
-		      uint32_t set_mask,
-		      uint32_t clear_mask)
-{
-	uint8_t command[8];
-	int     transferred;
-
-	command[0] = (set_mask >>  0) & 0xff;
-	command[1] = (set_mask >>  8) & 0xff;
-	command[2] = (set_mask >> 16) & 0xff;
-	command[3] = (set_mask >> 24) & 0xff;
-
-	command[4] = (clear_mask >>  0) & 0xff;
-	command[5] = (clear_mask >>  8) & 0xff;
-	command[6] = (clear_mask >> 16) & 0xff;
-	command[7] = (clear_mask >> 24) & 0xff;
-
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_OUT | 2,
-				   command,
-				   sizeof(command),
-				   &transferred,
-				   TRANSFER_TIMEOUT_MS));
-
-	if (transferred != sizeof(command)) {
-		fprintf(stderr,
-			"Failed to transfer full command "
-			"(sent %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(command));
-		return LIBUSB_ERROR_OTHER;
-	}
-
-	return 0;
-}
-
-static int gpio_read(libusb_device_handle *device, uint32_t *mask)
-{
-	uint8_t response[4];
-	int     transferred;
-
-	/*
-	 * The first query does triggers the sampling of the GPIO values, the
-	 * second query reads them back.
-	 */
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
-				   TRANSFER_TIMEOUT_MS));
-
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
-				   TRANSFER_TIMEOUT_MS));
-
-	if (transferred != sizeof(response)) {
-		fprintf(stderr,
-			"Failed to transfer full response "
-			"(read %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(response));
-		return LIBUSB_ERROR_OTHER;
-	}
-
-	*mask = (response[0] <<  0 |
-		 response[1] <<  8 |
-		 response[2] << 16 |
-		 response[3] << 24);
-
-	return 0;
-}
-
-int main(int argc, char **argv)
-{
-	libusb_context       *context;
-	libusb_device_handle *device;
-	uint16_t              vendor_id  = 0x18d1; /* Google */
-	uint16_t              product_id = 0x500f; /* discovery-stm32f072 */
-	int                   interface = 1;	   /* gpio interface */
-
-	if (!(argc == 2 && strcmp(argv[1], "read")  == 0) &&
-	    !(argc == 4 && strcmp(argv[1], "write") == 0)) {
-		puts("Usage: usb_gpio read\n"
-		     "       usb_gpio write <set_mask> <clear_mask>\n");
-		return 1;
-	}
-
-	CHECK(libusb_init(&context));
-
-	device = libusb_open_device_with_vid_pid(context,
-						 vendor_id,
-						 product_id);
-
-	if (device == NULL) {
-		fprintf(stderr,
-			"Unable to find device 0x%04x:0x%04x\n",
-			vendor_id,
-			product_id);
-		return 1;
-	}
-
-	CHECK(libusb_set_auto_detach_kernel_driver(device, 1));
-	CHECK(libusb_claim_interface(device, interface));
-
-	if (argc == 2 && strcmp(argv[1], "read") == 0) {
-		uint32_t mask;
-
-		CHECK(gpio_read(device, &mask));
-
-		printf("GPIO mask: 0x%08x\n", mask);
-	}
-
-	if (argc == 4 && strcmp(argv[1], "write") == 0) {
-		uint32_t set_mask   = strtol(argv[2], NULL, 0);
-		uint32_t clear_mask = strtol(argv[3], NULL, 0);
-
-		CHECK(gpio_write(device, set_mask, clear_mask));
-	}
-
-	libusb_close(device);
-	libusb_exit(context);
-
-	return 0;
-}
diff --git a/extra/usb_power/__init__.py b/extra/usb_power/__init__.py
deleted file mode 100644
index e69de29bb2..0000000000
--- a/extra/usb_power/__init__.py
+++ /dev/null
diff --git a/extra/usb_power/board/kevin/kevin.board b/extra/usb_power/board/kevin/kevin.board
deleted file mode 100644
index 8ab59573c6..0000000000
--- a/extra/usb_power/board/kevin/kevin.board
+++ /dev/null
@@ -1,18 +0,0 @@
-[
-{"name": "pp5000", "rs": 0.01, "sweetberry": "A", "channel": 0},
-{"name": "ppvar_gpu", "rs": 0.01, "sweetberry": "A", "channel": 1},
-{"name": "pp3300_wifi_bt", "rs": 0.01, "sweetberry": "A", "channel": 2},
-{"name": "pp1500_ap_io", "rs": 0.01, "sweetberry": "A", "channel": 3},
-{"name": "pp3300_alw", "rs": 0.01, "sweetberry": "A", "channel": 4},
-{"name": "ppvar_litcpu", "rs": 0.01, "sweetberry": "A", "channel": 5},
-{"name": "pp1800_s0", "rs": 0.01, "sweetberry": "A", "channel": 6},
-{"name": "pp3300_haven", "rs": 0.1, "sweetberry": "A", "channel": 7},
-{"name": "ppvar_bigcpu", "rs": 0.01, "sweetberry": "A", "channel": 8},
-{"name": "pp900_ap", "rs": 0.01, "sweetberry": "A", "channel": 9},
-{"name": "pp1800_ec", "rs": 0.1, "sweetberry": "A", "channel": 10},
-{"name": "pp1800_sensor", "rs": 0.01, "sweetberry": "A", "channel": 11},
-{"name": "pp1800_alw", "rs": 0.01, "sweetberry": "A", "channel": 12},
-{"name": "pp1200_lpddr", "rs": 0.01, "sweetberry": "A", "channel": 13},
-{"name": "pp3300_ec", "rs": 0.1, "sweetberry": "A", "channel": 14},
-{"name": "pp3300_s0", "rs": 0.01, "sweetberry": "A", "channel": 15}
-]
diff --git a/extra/usb_power/board/kevin/kevin_all.scenario b/extra/usb_power/board/kevin/kevin_all.scenario
deleted file mode 100644
index dbc3953364..0000000000
--- a/extra/usb_power/board/kevin/kevin_all.scenario
+++ /dev/null
@@ -1,18 +0,0 @@
-[
-"pp5000",
-"ppvar_gpu",
-"pp3300_wifi_bt",
-"pp1500_ap_io",
-"pp3300_alw",
-"ppvar_litcpu",
-"pp1800_s0",
-"pp3300_haven",
-"ppvar_bigcpu",
-"pp900_ap",
-"pp1800_ec",
-"pp1800_sensor",
-"pp1800_alw",
-"pp1200_lpddr",
-"pp3300_ec",
-"pp3300_s0"
-]
diff --git a/extra/usb_power/board/marlin/marlin.board b/extra/usb_power/board/marlin/marlin.board
deleted file mode 100644
index dc4cdad258..0000000000
--- a/extra/usb_power/board/marlin/marlin.board
+++ /dev/null
@@ -1,74 +0,0 @@
-[
-{"name": "VBAT", "rs": 0.01, "sweetberry": "A", "net": "", "channel": 0},
-{"name": "VBAT_", "rs": 0.01, "sweetberry": "B", "net": "", "channel": 0},
-{"name": "VDD_MEM", "rs": 0.05, "sweetberry": "A", "net": "V_MEM_0V875", "channel": 1},
-{"name": "VDD_EBI_PHY", "rs": 0.1, "sweetberry": "A", "net": "V_EBI_0V875", "channel": 2},
-{"name": "VDD_PCIE_1P8", "rs": 0.5, "sweetberry": "A", "net": "V_USB_1V8", "channel": 3},
-{"name": "VDD_PCIE_CORE", "rs": 0.1, "sweetberry": "A", "net": "V_PCIE_0V925", "channel": 4},
-{"name": "VDD_MIPI_CSI", "rs": 0.1, "sweetberry": "A", "net": "V_CSI_DSI_1V25", "channel": 5},
-{"name": "VDD_A1", "rs": 0.1, "sweetberry": "A", "net": "V_MSMA1_1V225", "channel": 6},
-{"name": "VDD_A2", "rs": 1.0, "sweetberry": "A", "net": "V_MSMA2_1V8", "channel": 7},
-{"name": "VDD_P2", "rs": 0.02, "sweetberry": "A", "net": "V_IO_1V8", "channel": 8},
-{"name": "VDD_P3", "rs": 0.5, "sweetberry": "B", "net": "V_IO_1V8", "channel": 1},
-{"name": "VDD_P5", "rs": 0.5, "sweetberry": "A", "net": "V_RUIM1", "channel": 9},
-{"name": "VDD_P6", "rs": 0.02, "sweetberry": "A", "net": "V_IO_1V8", "channel": 46},
-{"name": "VDD_P10", "rs": 0.1, "sweetberry": "A", "net": "V_UFS_1V2", "channel": 10},
-{"name": "VDD_P12", "rs": 0.1, "sweetberry": "A", "net": "V_SRIO_1V8", "channel": 11},
-{"name": "VDD_USB_HS_3P1", "rs": 0.5, "sweetberry": "A", "net": "V_USB_3V075", "channel": 12},
-{"name": "VDD_CORE", "rs": 0.02, "sweetberry": "A", "net": "V_VDDCORE_0V8", "channel": 13},
-{"name": "VDD_GFX", "rs": 0.05, "sweetberry": "A", "net": "V_GFX_0V98", "channel": 14},
-{"name": "VDD_MODEM", "rs": 0.05, "sweetberry": "A", "net": "V_MODEM_1V0", "channel": 15},
-{"name": "VDD_APC", "rs": 0.01, "sweetberry": "A", "net": "V_APC_0V8", "channel": 16},
-{"name": "VDD_P1", "rs": 0.1, "sweetberry": "A", "net": "V_DDRCORE_1V1", "channel": 17},
-{"name": "VDD_DDR_CORE_1P8", "rs": 0.1, "sweetberry": "B", "net": "V_IO_1V8", "channel": 3},
-{"name": "VDD_SSC_CORE", "rs": 0.05, "sweetberry": "A", "net": "V_SSCCORE_0V8", "channel": 18},
-{"name": "VDD_SSC_MEM", "rs": 0.02, "sweetberry": "A", "net": "V_SSCMEM_0V875", "channel": 19},
-{"name": "V_EMMC_2V95", "rs": 0.1, "sweetberry": "A", "net": "V_EMMC_2V95", "channel": 20},
-{"name": "VCCQ2", "rs": 0.1, "sweetberry": "B", "net": "V_IO_1V8", "channel": 4},
-{"name": "VDD/VDDIO", "rs": 1.0, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 5},
-{"name": "V_LED_3V3", "rs": 0.1, "sweetberry": "A", "net": "V_LED_3V3", "channel": 21},
-{"name": "VDD/VIO", "rs": 1.0, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 6},
-{"name": "V_SRIO_1V8", "rs": 1.0, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 7},
-{"name": "V_SRIO_1V8_", "rs": 1.0, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 8},
-{"name": "VBAT/VDD/VDDA", "rs": 0.1, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 9},
-{"name": "V_SRIO_1V8__", "rs": 1.0, "sweetberry": "B", "net": "V_SRIO_1V8", "channel": 10},
-{"name": "V_SR_2V85", "rs": 0.1, "sweetberry": "A", "net": "V_SR_2V85", "channel": 22},
-{"name": "", "rs": 0.1, "sweetberry": "B", "net": "", "channel": 11},
-{"name": "V_USBSS_SW_1V8", "rs": 0.1, "sweetberry": "A", "net": "V_USBSS_SW_1V8", "channel": 23},
-{"name": "V_RF_2V7", "rs": 0.5, "sweetberry": "A", "net": "V_RF_2V7", "channel": 24},
-{"name": "V_TP_3V3", "rs": 0.5, "sweetberry": "A", "net": "V_TP_3V3", "channel": 25},
-{"name": "V_ELVDD", "rs": 0.1, "sweetberry": "B", "net": "V_ELVDD", "channel": 16},
-{"name": "V_AVDD", "rs": 1.0, "sweetberry": "B", "net": "V_AVDD", "channel": 17},
-{"name": "VCI_3V", "rs": 0.1, "sweetberry": "A", "net": "VCI_3V", "channel": 26},
-{"name": "VDD_1V8_PANEL", "rs": 0.5, "sweetberry": "A", "net": "VDD_1V8_PANEL", "channel": 27},
-{"name": "V_TP_1V8", "rs": 0.1, "sweetberry": "A", "net": "V_TP_1V8", "channel": 28},
-{"name": "V_CAM2_D1V2", "rs": 0.1, "sweetberry": "A", "net": "V_CAM2_D1V2", "channel": 31},
-{"name": "V_CAMIO_1V8", "rs": 0.1, "sweetberry": "A", "net": "V_CAMIO_1V8", "channel": 32},
-{"name": "V_CAM1_VCM2V85", "rs": 0.5, "sweetberry": "B", "net": "V_CAM1_VCM2V85", "channel": 18},
-{"name": "V_CAM1_A2V85", "rs": 1.0, "sweetberry": "B", "net": "V_CAM1_A2V85", "channel": 19},
-{"name": "V_CAM1_D1V0", "rs": 0.02, "sweetberry": "A", "net": "V_CAM1_D1V0", "channel": 33},
-{"name": "V_CAMIO_1V8_", "rs": 1.0, "sweetberry": "B", "net": "V_CAMIO_1V8", "channel": 20},
-{"name": "VBAT_ADC_IN", "rs": 0.01, "sweetberry": "A", "net": "V_DCIN", "channel": 34},
-{"name": "VDD_RX", "rs": 1.0, "sweetberry": "B", "net": "V_IO_1V8", "channel": 21},
-{"name": "VDD_MIC_BIAS", "rs": 0.01, "sweetberry": "A", "net": "V_BOOST_BYPASS", "channel": 35},
-{"name": "PVDD/VDD", "rs": 0.1, "sweetberry": "A", "net": "V_AUD_AMP_3V3", "channel": 36},
-{"name": "V_DCIN", "rs": 0.01, "sweetberry": "A", "net": "V_DCIN", "channel": 47},
-{"name": "V_AUDIO_2V15", "rs": 0.02, "sweetberry": "A", "net": "V_AUDIO_2V15", "channel": 38},
-{"name": "V_AUDIO_1V3", "rs": 0.02, "sweetberry": "A", "net": "V_AUDIO_1V3", "channel": 39},
-{"name": "PVIN/AVIN", "rs": 0.02, "sweetberry": "A", "net": "V_DCIN", "channel": 40},
-{"name": "VBATT", "rs": 0.5, "sweetberry": "B", "net": "VPA_BATT", "channel": 24},
-{"name": "VCC_GSM", "rs": 0.01, "sweetberry": "B", "net": "VPA_APT", "channel": 25},
-{"name": "VCC1_3G", "rs": 0.01, "sweetberry": "B", "net": "VPA", "channel": 26},
-{"name": "VAPT", "rs": 0.01, "sweetberry": "B", "net": "VPA_APT", "channel": 27},
-{"name": "VCC1", "rs": 0.01, "sweetberry": "B", "net": "VPA", "channel": 28},
-{"name": "VPA_BATT", "rs": 0.5, "sweetberry": "B", "net": "VPA_BATT", "channel": 29},
-{"name": "VDD_RF1_TVCO", "rs": 0.1, "sweetberry": "A", "net": "VREG_RF_1P0", "channel": 42},
-{"name": "V_GPS_1V8", "rs": 1.0, "sweetberry": "A", "net": "V_GPS_1V8", "channel": 43},
-{"name": "VDDIO_XTAL", "rs": 1.0, "sweetberry": "A", "net": "VDDIO_XTAL_1V8", "channel": 44},
-{"name": "VDD_FEM", "rs": 0.05, "sweetberry": "A", "net": "V_DCIN", "channel": 45},
-{"name": "VDD33", "rs": 0.1, "sweetberry": "B", "net": "V_VDDRF_3V2", "channel": 31},
-{"name": "DVDD11", "rs": 0.1, "sweetberry": "B", "net": "V_VDDRF_1V1", "channel": 32},
-{"name": "VDD(PAD)", "rs": 0.5, "sweetberry": "B", "net": "V_NFC_1V8", "channel": 33},
-{"name": "VBAT/VBAT2/VDD(UP)", "rs": 0.1, "sweetberry": "B", "net": "V_MBAT", "channel": 34},
-{"name": "NFC_5V_BOOST", "rs": 0.1, "sweetberry": "B", "net": "NFC_5V_BOOST", "channel": 35}
-]
diff --git a/extra/usb_power/board/marlin/marlin_all_A.scenario b/extra/usb_power/board/marlin/marlin_all_A.scenario
deleted file mode 100644
index a024b698d7..0000000000
--- a/extra/usb_power/board/marlin/marlin_all_A.scenario
+++ /dev/null
@@ -1,42 +0,0 @@
-[ "VBAT",
-"VDD_MEM",
-"VDD_EBI_PHY",
-"VDD_PCIE_1P8",
-"VDD_PCIE_CORE",
-"VDD_MIPI_CSI",
-"VDD_A1",
-"VDD_A2",
-"VDD_P2",
-"VDD_P5",
-"VDD_P6",
-"VDD_P10",
-"VDD_P12",
-"VDD_USB_HS_3P1",
-"VDD_CORE",
-"VDD_GFX",
-"VDD_MODEM",
-"VDD_APC",
-"VDD_P1",
-"VDD_SSC_CORE",
-"VDD_SSC_MEM",
-"V_EMMC_2V95",
-"V_LED_3V3",
-"V_SR_2V85",
-"V_USBSS_SW_1V8",
-"V_RF_2V7",
-"V_TP_3V3",
-"VCI_3V",
-"VDD_1V8_PANEL",
-"V_TP_1V8",
-"V_CAM2_D1V2",
-"V_CAMIO_1V8",
-"V_CAM1_D1V0",
-"VBAT_ADC_IN",
-"VDD_MIC_BIAS",
-"PVDD/VDD",
-"V_DCIN",
-"V_AUDIO_2V15",
-"V_AUDIO_1V3",
-"VDD_RF1_TVCO",
-"V_GPS_1V8",
-"VDD_FEM"]
diff --git a/extra/usb_power/board/marlin/marlin_all_B.scenario b/extra/usb_power/board/marlin/marlin_all_B.scenario
deleted file mode 100644
index 876d2dbfbd..0000000000
--- a/extra/usb_power/board/marlin/marlin_all_B.scenario
+++ /dev/null
@@ -1,28 +0,0 @@
-[ "VBAT_",
-"VDD_P3",
-"VDD_DDR_CORE_1P8",
-"VCCQ2",
-"VDD/VDDIO",
-"VDD/VIO",
-"V_SRIO_1V8",
-"V_SRIO_1V8_",
-"VBAT/VDD/VDDA",
-"V_SRIO_1V8__",
-"",
-"V_ELVDD",
-"V_AVDD",
-"V_CAM1_VCM2V85",
-"V_CAM1_A2V85",
-"V_CAMIO_1V8_",
-"VDD_RX",
-"VBATT",
-"VCC_GSM",
-"VCC1_3G",
-"VAPT",
-"VCC1",
-"VPA_BATT",
-"VDD33",
-"DVDD11",
-"VDD(PAD)",
-"VBAT/VBAT2/VDD(UP)",
-"NFC_5V_BOOST" ]
diff --git a/extra/usb_power/board/marlin/marlin_common.scenario b/extra/usb_power/board/marlin/marlin_common.scenario
deleted file mode 100644
index 7e20236c34..0000000000
--- a/extra/usb_power/board/marlin/marlin_common.scenario
+++ /dev/null
@@ -1 +0,0 @@
-["VBAT", "VDD_MEM", "VDD_EBI_PHY", "VDD_PCIE_1P8", "VDD_PCIE_CORE", "VDD_MIPI_CSI", "VDD_A1", "VDD_CORE", "VDD_GFX", "VDD_MODEM", "VDD_APC", "VDD_P1", "VDD_SSC_CORE", "VDD_SSC_MEM", "VDD_1V8_PANEL", "V_CAM2_D1V2", "VBAT_ADC_IN", "VDD_FEM"]
diff --git a/extra/usb_power/board/marlin/marlin_pvc.scenario b/extra/usb_power/board/marlin/marlin_pvc.scenario
deleted file mode 100644
index 426cd1479c..0000000000
--- a/extra/usb_power/board/marlin/marlin_pvc.scenario
+++ /dev/null
@@ -1 +0,0 @@
-["VBAT", ["VBAT", "BUSV"],  ["VBAT", "CURRENT"], ["VBAT", "SHUNTV"]]
diff --git a/extra/usb_power/board/marlin/marlin_short.scenario b/extra/usb_power/board/marlin/marlin_short.scenario
deleted file mode 100644
index 2cfc8b0f9a..0000000000
--- a/extra/usb_power/board/marlin/marlin_short.scenario
+++ /dev/null
@@ -1 +0,0 @@
-["VBAT", "VDD_MEM", "VDD_CORE", "VDD_GFX", "VDD_1V8_PANEL"]
diff --git a/extra/usb_power/board/marlin/marlin_vbat.scenario b/extra/usb_power/board/marlin/marlin_vbat.scenario
deleted file mode 100644
index f1c18ca202..0000000000
--- a/extra/usb_power/board/marlin/marlin_vbat.scenario
+++ /dev/null
@@ -1 +0,0 @@
-["VBAT"]
diff --git a/extra/usb_power/convert_power_log_board.py b/extra/usb_power/convert_power_log_board.py
deleted file mode 100644
index 8aab77ee4c..0000000000
--- a/extra/usb_power/convert_power_log_board.py
+++ /dev/null
@@ -1,92 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""
-Program to convert sweetberry config to servod config template.
-"""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import json
-import os
-import sys
-
-from powerlog import Spower
-
-
-def fetch_records(board_file):
-    """Import records from servo_ina file.
-
-    board files are json files, and have a list of tuples with
-    the INA data.
-    (name, rs, swetberry_num, net_name, channel)
-
-    Args:
-      board_file: board file
-
-    Returns:
-      list of tuples as described above.
-    """
-    data = None
-    with open(board_file) as f:
-        data = json.load(f)
-    return data
-
-
-def write_to_file(file, sweetberry, inas):
-    """Writes records of |sweetberry| to |file|
-    Args:
-      file: file to write to.
-      sweetberry: sweetberry type. A or B.
-      inas: list of inas read from board file.
-    """
-
-    with open(file, 'w') as pyfile:
-
-        pyfile.write('inas = [\n')
-
-        for rec in inas:
-            if rec['sweetberry'] != sweetberry:
-                continue
-
-            # EX : ('sweetberry', 0x40, 'SB_FW_CAM_2P8', 5.0, 1.000, 3, False),
-            channel, i2c_addr = Spower.CHMAP[rec['channel']]
-            record = ("    ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')"
-                      ",\n" % (i2c_addr, rec['name'], rec['rs'], channel))
-            pyfile.write(record)
-
-        pyfile.write(']\n')
-
-
-def main(argv):
-    if len(argv) != 2:
-        print("usage:")
-        print(" %s input.board" % argv[0])
-        return
-
-    inputf = argv[1]
-    basename = os.path.splitext(inputf)[0]
-
-    inas = fetch_records(inputf)
-
-    sweetberry = set(rec['sweetberry'] for rec in inas)
-
-    if len(sweetberry) == 2:
-        print("Converting %s to %s and %s" % (inputf, basename + '_a.py',
-                                              basename + '_b.py'))
-        write_to_file(basename + '_a.py', 'A', inas)
-        write_to_file(basename + '_b.py', 'B', inas)
-    else:
-        print("Converting %s to %s" % (inputf, basename + '.py'))
-        write_to_file(basename + '.py', sweetberry.pop(), inas)
-
-
-if __name__ == "__main__":
-    main(sys.argv)
diff --git a/extra/usb_power/convert_servo_ina.py b/extra/usb_power/convert_servo_ina.py
deleted file mode 100755
index 1c70f31aeb..0000000000
--- a/extra/usb_power/convert_servo_ina.py
+++ /dev/null
@@ -1,80 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Program to convert power logging config from a servo_ina device
-   to a sweetberry config.
-"""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import os
-import sys
-
-
-def fetch_records(basename):
-  """Import records from servo_ina file.
-
-  servo_ina files are python imports, and have a list of tuples with
-  the INA data.
-  (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True)
-
-  Args:
-    basename: python import name (filename -.py)
-
-  Returns:
-    list of tuples as described above.
-  """
-  ina_desc = __import__(basename)
-  return ina_desc.inas
-
-
-def main(argv):
-  if len(argv) != 2:
-    print("usage:")
-    print(" %s input.py" % argv[0])
-    return
-
-  inputf = argv[1]
-  basename = os.path.splitext(inputf)[0]
-  outputf = basename + '.board'
-  outputs = basename + '.scenario'
-
-  print("Converting %s to %s, %s" % (inputf, outputf, outputs))
-
-  inas = fetch_records(basename)
-
-
-  boardfile = open(outputf, 'w')
-  scenario = open(outputs, 'w')
-
-  boardfile.write('[\n')
-  scenario.write('[\n')
-  start = True
-
-  for rec in inas:
-    if start:
-      start = False
-    else:
-      boardfile.write(',\n')
-      scenario.write(',\n')
-
-    record = '  {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}' % (
-             rec[2], rec[4], rec[1] - 64)
-    boardfile.write(record)
-    scenario.write('"%s"' % rec[2])
-
-  boardfile.write('\n')
-  boardfile.write(']')
-
-  scenario.write('\n')
-  scenario.write(']')
-
-if __name__ == "__main__":
-  main(sys.argv)
diff --git a/extra/usb_power/marlin_v.scenario b/extra/usb_power/marlin_v.scenario
deleted file mode 100644
index 99c132cb27..0000000000
--- a/extra/usb_power/marlin_v.scenario
+++ /dev/null
@@ -1 +0,0 @@
-[["VBAT", "BUSV"], ["VDD_1V8_PANEL", "BUSV"], ["V_EMMC_2V95", "BUSV"], ["V_SR_2V85", "BUSV"], ["V_USBSS_SW_1V8",  "BUSV"], ["V_AUDIO_2V15",  "BUSV"]]
diff --git a/extra/usb_power/powerlog.README.md b/extra/usb_power/powerlog.README.md
deleted file mode 100644
index 105516330a..0000000000
--- a/extra/usb_power/powerlog.README.md
+++ /dev/null
@@ -1,210 +0,0 @@
-# Sweetberry USB power monitoring
-
-This tool allows high speed monitoring of power rails via a special USB
-endpoint. Currently this is implemented for the Sweetberry board.
-
-To use on a board, you'll need two config files, one describing the board, a
-`.board` file, and one describing the particular rails you want to monitor in
-this session, a `.scenario` file.
-
-## Converting from servo_ina configs
-
--   Method 1 (not limited to chroot)
-
-    Many configs can be found for the servo_ina_board in `hdctools/servo/data/`.
-    Sweetberry is plug compatible with servo_ina headers, and config files can
-    be converted with the following tool:
-
-    ```
-    ./convert_servo_ina.py <board>_r0_loc.py
-    ```
-
-    This will generate `<board>_r0_loc.board` and `<board>_r0_loc.scenario`
-    locally, which can be used with `powerlog.py`.
-
--   Method 2 (recommended for Chrome OS developers, requires chroot)
-
-    If you are using `powerlog.py` within the chroot, copy `<board>_r0_loc.py`
-    to `src/third_party/hdctools/servo/data`, then add this line to file:
-
-    ```python
-    config_type = 'sweetberry'
-    ```
-
-    And run command in chroot:
-
-    ```
-    (Anywhere in chroot, just ONCE) cros_workon --host start dev-util/hdctools
-    ```
-
-    Then every time you make a change to `<board>_r0_loc.py`, run:
-
-    ```
-    (Anywhere in chroot) sudo emerge dev-util/hdctools
-    ```
-
-    The command will install the corresponding `.board` and `.scenario` file in
-    the chroot. To use `powerlog.py` use the command:
-
-    ```
-    (Anywhere in chroot) powerlog -b <board>_r0_loc.board -c <board>_r0_loc.scenario
-    ```
-
-    There is no need to specify the absolute path to the `.board` and
-    `.scenario` file, once they are installed into the chroot. If there is any
-    changes to `<board>_r0_loc.py`, you need to `sudo emerge dev-util/hdctools`
-    again.
-
-## Board files
-
-Board files contain a list of rails, supporting 48 channels each on up to two
-Sweetberries. For each rail you must specify a name, sense resistor value, and
-channel number. You can optionally list expected voltage and net name. The
-format is as follows, in json:
-
-example.board:
-
-```json
-[
-{ "name": "railname",
-  "rs": <sense resistor value in ohms>,
-  "sweetberry": <"A" for main Sweetberry, "B" for a secondary Sweetberry>,
-  "channel": <0-47 according to board schematic>,
-  "v": <optional expected bus voltage in volts>,
-  "net": <optional schematic net name>
-},
-{...}
-]
-```
-
-## Scenario files
-
-Scenario files contain the set of rails to monitor in this session. The file
-format is simply a list of rail names from the board file.
-
-Optionally, you can specify the type of measurement, from the set of `"POWER"`,
-`"BUSV"`, `"CURRENT"`, `"SHUNTV"`. If not specified, the default is power.
-
-example.scenario:
-
-```json
-[
-"railname",
-"another_railname",
-["railname", "BUSV"],
-["railname", "CURRENT"],
-...
-]
-```
-
-## Output
-
-`powerlog.py` will output a csv formatted log to stdout, at timing intervals
-specified on the command line. Currently values below `-t 10000` do not work
-reliably but further updates should allow faster updating.
-
-An example run of:
-
-```
-./powerlog.py -b board/marlin/marlin.board -c board/marlin/marlin_short.scenario -t 100000
-```
-
-Will result in: `ts:32976us, VBAT uW, VDD_MEM uW, VDD_CORE uW, VDD_GFX uW,
-VDD_1V8_PANEL uW 0.033004, 12207.03, 4882.81, 9155.27, 2441.41, 0.00 0.066008,
-12207.03, 3662.11, 9155.27, 2441.41, 0.00 0.099012, 12207.03, 3662.11, 9155.27,
-2441.41, 0.00 ...`
-
-The output format is as follows:
-
--   `ts:32976us`
-
-    Timestamps either zero based or synced to system clock, in seconds. The
-    column header indicates the selected sampling interval. Since the INA231 has
-    specific hardware defines sampling options, this will be the closest
-    supported option lower than the requested `-t` value on the command line.
-
--   `VBAT uW`
-
-    Microwatt reading from this rail, generated on the INA by integrating the
-    voltage/amperage on the sense resistor over the sampling time, and
-    multiplying by the sampled bus voltage.
-
--   `... uW`
-
-    Further microwatt entry columns for each rail specified in your scenario
-    file.
-
--   `... xX`
-
-    Measurement in uW, mW, mV, uA, uV as per config.
-
-## Calculate stats and store data and stats
-
-When appropriate flag is set, powerlog.py is capable of calculating statistics
-and storing statistics and raw data.
-
--   Example 1
-
-    ```
-    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats [<directory>]
-    ```
-
-    If `<directory>` is specified, this will save stats as:
-    `<directory>/sweetberry<timestamp>/summary.txt`. If `<directory>` does not
-    exist, it will be created.
-
-    If `<directory>` is not specified but the flag is set, this will save stats
-    under the directory which `powerlog.py` is in: `<directory of
-    powerlog.py>/sweetberry<timestamp>/summary.txt`.
-
-    If `--save_stats` flag is not set, stats will not be saved.
-
--   Example 2
-
-    ```
-    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_raw_data [<directory>]
-    ```
-
-    If `<directory>` is specified, this will save raw data in:
-    `<directory>/sweetberry<timestamp>/raw_data/`. If `<directory>` does not
-    exist, it will be created.
-
-    If `<directory>` is not specified but the flag is set, this will save raw
-    data under the directory which `powerlog.py` is in: `<directory of
-    powerlog.py>/sweetberry<timestamp>/raw_data/`.
-
-    If `--save_raw_data` flag is not set, raw data will not be saved.
-
--   Example 3:
-
-    ```
-    ./powerlog.py -b board/eve_dvt2_loc/eve_dvt2_loc.board -c board/eve_dvt2_loc/eve_dvt2_loc.scenario --save_stats_json [<directory>]
-    ```
-
-    If `<directory>` is specified, this will save MEANS in json as:
-    `<directory>/sweetberry<timestamp>/summary.json`. If `<directory>` does not
-    exist, it will be created.
-
-    If `<directory>` is not specified but the flag is set, this will save MEANS
-    in json under the directory which `powerlog.py` is in: `<directory of
-    powerlog.py>/sweetberry<timestamp>/summary.json`.
-
-    If `--save_stats` flag is not set, stats will not be saved.
-
-    `--save_stats_json` is designed for `power_telemetry_logger` for easy
-    reading and writing.
-
-## Making developer changes to `powerlog.py`
-
-`powerlog.py` is installed in chroot, and the developer can import `powerlog` or
-use `powerlog` directly anywhere within chroot. Anytime the developer makes a
-change to `powerlog.py`, the developer needs to re-install `powerlog.py` so that
-anything that imports `powerlog` does not break. The following is how the
-developer installs `powerlog.py` during development.
-
-Run command in chroot:
-
-```
-(Anywhere in chroot, just ONCE) cros_workon --host start chromeos-base/ec-devutils
-(Anywhere in chroot, every time powerlog.py is changed) sudo emerge chromeos-base/ec-devutils
-```
diff --git a/extra/usb_power/powerlog.py b/extra/usb_power/powerlog.py
deleted file mode 100755
index 82cce3daed..0000000000
--- a/extra/usb_power/powerlog.py
+++ /dev/null
@@ -1,908 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Program to fetch power logging data from a sweetberry device
-   or other usb device that exports a USB power logging interface.
-"""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import argparse
-import array
-from distutils import sysconfig
-import json
-import logging
-import os
-import pprint
-import struct
-import sys
-import time
-import traceback
-
-import usb
-
-from stats_manager import StatsManager
-
-# Directory where hdctools installs configuration files into.
-LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), 'servo',
-                       'data')
-
-# Potential config file locations: current working directory, the same directory
-# as powerlog.py file or LIB_DIR.
-CONFIG_LOCATIONS = [os.getcwd(), os.path.dirname(os.path.realpath(__file__)),
-                    LIB_DIR]
-
-def logoutput(msg):
-  print(msg)
-  sys.stdout.flush()
-
-def process_filename(filename):
-  """Find the file path from the filename.
-
-  If filename is already the complete path, return that directly. If filename is
-  just the short name, look for the file in the current working directory, in
-  the directory of the current .py file, and then in the directory installed by
-  hdctools. If the file is found, return the complete path of the file.
-
-  Args:
-      filename: complete file path or short file name.
-
-  Returns:
-      a complete file path.
-
-  Raises:
-      IOError if filename does not exist.
-  """
-  # Check if filename is absolute path.
-  if os.path.isabs(filename) and os.path.isfile(filename):
-    return filename
-  # Check if filename is relative to a known config location.
-  for dirname in CONFIG_LOCATIONS:
-    file_at_dir = os.path.join(dirname, filename)
-    if os.path.isfile(file_at_dir):
-      return file_at_dir
-  raise IOError('No such file or directory: \'%s\'' % filename)
-
-
-class Spower(object):
-  """Power class to access devices on the bus.
-
-  Usage:
-    bus = Spower()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-
-  # INA interface type.
-  INA_POWER     = 1
-  INA_BUSV      = 2
-  INA_CURRENT   = 3
-  INA_SHUNTV    = 4
-  # INA_SUFFIX is used to differentiate multiple ina types for the same power
-  # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1
-  # (power, no suffix for backward compatibility).
-  INA_SUFFIX      = ['', '', '_busv', '_cur', '_shuntv']
-
-  # usb power commands
-  CMD_RESET   = 0x0000
-  CMD_STOP    = 0x0001
-  CMD_ADDINA  = 0x0002
-  CMD_START   = 0x0003
-  CMD_NEXT    = 0x0004
-  CMD_SETTIME = 0x0005
-
-  # Map between header channel number (0-47)
-  # and INA I2C bus/addr on sweetberry.
-  CHMAP = {
-	0: (3, 0x40),
-	1: (1, 0x40),
-	2: (2, 0x40),
-	3: (0, 0x40),
-	4: (3, 0x41),
-	5: (1, 0x41),
-	6: (2, 0x41),
-	7: (0, 0x41),
-	8: (3, 0x42),
-	9: (1, 0x42),
-	10: (2, 0x42),
-	11: (0, 0x42),
-	12: (3, 0x43),
-	13: (1, 0x43),
-	14: (2, 0x43),
-	15: (0, 0x43),
-	16: (3, 0x44),
-	17: (1, 0x44),
-	18: (2, 0x44),
-	19: (0, 0x44),
-	20: (3, 0x45),
-	21: (1, 0x45),
-	22: (2, 0x45),
-	23: (0, 0x45),
-	24: (3, 0x46),
-	25: (1, 0x46),
-	26: (2, 0x46),
-	27: (0, 0x46),
-	28: (3, 0x47),
-	29: (1, 0x47),
-	30: (2, 0x47),
-	31: (0, 0x47),
-	32: (3, 0x48),
-	33: (1, 0x48),
-	34: (2, 0x48),
-	35: (0, 0x48),
-	36: (3, 0x49),
-	37: (1, 0x49),
-	38: (2, 0x49),
-	39: (0, 0x49),
-	40: (3, 0x4a),
-	41: (1, 0x4a),
-	42: (2, 0x4a),
-	43: (0, 0x4a),
-	44: (3, 0x4b),
-	45: (1, 0x4b),
-	46: (2, 0x4b),
-	47: (0, 0x4b),
-  }
-
-  def __init__(self, board, vendor=0x18d1,
-               product=0x5020, interface=1, serialname=None):
-    self._logger = logging.getLogger(__name__)
-    self._board = board
-
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Power", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB dioesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except ValueError:
-          # Incompatible pyUsb version.
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise Exception("Power", "USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except TypeError:
-        # Incompatible pyUsb version.
-        dev = dev_list.next()
-
-    self._logger.debug("Found USB device: %04x:%04x", vendor, product)
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except usb.USBError:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==255 and i.bInterfaceSubClass==0x54)
-
-    self._intf = intf
-    self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress)
-
-    self.clear_ina_struct()
-
-    self._logger.debug("Found power logging USB endpoint.")
-
-  def clear_ina_struct(self):
-    """ Clear INA description struct."""
-    self._inas = []
-
-  def append_ina_struct(self, name, rs, port, addr,
-                        data=None, ina_type=INA_POWER):
-    """Add an INA descriptor into the list of active INAs.
-
-    Args:
-      name:	Readable name of this channel.
-      rs:	Sense resistor value in ohms, floating point.
-      port:	I2C channel this INA is connected to.
-      addr: 	I2C addr of this INA.
-      data:	Misc data for special handling, board specific.
-      ina_type: INA function to use, power, voltage, etc.
-    """
-    ina = {}
-    ina['name'] = name
-    ina['rs'] = rs
-    ina['port'] = port
-    ina['addr'] = addr
-    ina['type'] = ina_type
-    # Calculate INA231 Calibration register
-    # (see INA231 spec p.15)
-    # CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
-    # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000)
-    ina['uAscale'] = 80000000. / (rs * 0x8000);
-    ina['uWscale'] = 25. * ina['uAscale'];
-    ina['mVscale'] = 1.25
-    ina['uVscale'] = 2.5
-    ina['data'] = data
-    self._inas.append(ina)
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000):
-    """Write command to logger logic.
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-
-    Returns:
-      bytes read, or None on failure.
-    """
-    self._logger.debug("Spower.wr_command(write_list=[%s] (%d), read_count=%s)",
-                       list(bytearray(write_list)), len(write_list), read_count)
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-
-    self._logger.debug("RET: %s ", ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      self._logger.debug("BYTES: [%s]", bytesread)
-
-      if len(bytesread) != read_count:
-        pass
-
-      self._logger.debug("STATUS: 0x%02x", int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
-
-    return None
-
-  def clear(self):
-    """Clear pending reads on the stm32"""
-    try:
-      while True:
-        ret = self.wr_command(b"", read_count=512, rtimeout=100, wtimeout=50)
-        self._logger.debug("Try Clear: read %s",
-                           "success" if ret == 0 else "failure")
-    except:
-      pass
-
-  def send_reset(self):
-    """Reset the power interface on the stm32"""
-    cmd = struct.pack("<H", self.CMD_RESET)
-    ret = self.wr_command(cmd, rtimeout=50, wtimeout=50)
-    self._logger.debug("Command RESET: %s",
-                       "success" if ret == 0 else "failure")
-
-  def reset(self):
-    """Try resetting the USB interface until success.
-
-    Use linear back off strategy when encounter the error with 10ms increment.
-
-    Raises:
-      Exception on failure.
-    """
-    max_reset_retry = 100
-    for count in range(1, max_reset_retry + 1):
-      self.clear()
-      try:
-        self.send_reset()
-        return
-      except Exception as e:
-        self.clear()
-        self.clear()
-        self._logger.debug("TRY %d of %d: %s", count, max_reset_retry, e)
-        time.sleep(count * 0.01)
-    raise Exception("Power", "Failed to reset")
-
-  def stop(self):
-    """Stop any active data acquisition."""
-    cmd = struct.pack("<H", self.CMD_STOP)
-    ret = self.wr_command(cmd)
-    self._logger.debug("Command STOP: %s",
-                       "success" if ret == 0 else "failure")
-
-  def start(self, integration_us):
-    """Start data acquisition.
-
-    Args:
-      integration_us: int, how many us between samples, and
-                      how often the data block must be read.
-
-    Returns:
-      actual sampling interval in ms.
-    """
-    cmd = struct.pack("<HI", self.CMD_START, integration_us)
-    read = self.wr_command(cmd, read_count=5)
-    actual_us = 0
-    if len(read) == 5:
-      ret, actual_us = struct.unpack("<BI", read)
-      self._logger.debug("Command START: %s %dus",
-               "success" if ret == 0 else "failure", actual_us)
-    else:
-      self._logger.debug("Command START: FAIL")
-
-    return actual_us
-
-  def add_ina_name(self, name_tuple):
-    """Add INA from board config.
-
-    Args:
-      name_tuple:	name and type of power rail in board config.
-
-    Returns:
-      True if INA added, False if the INA is not on this board.
-
-    Raises:
-      Exception on unexpected failure.
-    """
-    name, ina_type = name_tuple
-
-    for datum in self._brdcfg:
-      if datum["name"] == name:
-        rs = int(float(datum["rs"]) * 1000.)
-        board = datum["sweetberry"]
-
-        if board == self._board:
-          if 'port' in datum and 'addr' in datum:
-            port = datum['port']
-            addr = datum['addr']
-          else:
-            channel = int(datum["channel"])
-            port, addr = self.CHMAP[channel]
-          self.add_ina(port, ina_type, addr, 0, rs, data=datum)
-          return True
-        else:
-          return False
-    raise Exception("Power", "Failed to find INA %s" % name)
-
-  def set_time(self, timestamp_us):
-    """Set sweetberry time to match host time.
-
-    Args:
-      timestamp_us: host timestmap in us.
-    """
-    # 0x0005 , 8 byte timestamp
-    cmd = struct.pack("<HQ", self.CMD_SETTIME, timestamp_us)
-    ret = self.wr_command(cmd)
-
-    self._logger.debug("Command SETTIME: %s",
-                       "success" if ret == 0 else "failure")
-
-  def add_ina(self, bus, ina_type, addr, extra, resistance, data=None):
-    """Add an INA to the data acquisition list.
-
-    Args:
-      bus: which i2c bus the INA is on. Same ordering as Si2c.
-      ina_type: Ina interface: INA_POWER/BUSV/etc.
-      addr: 7 bit i2c addr of this INA
-      extra: extra data for nonstandard configs.
-      resistance: int, shunt resistance in mOhm
-    """
-    # 0x0002, 1B: bus, 1B:INA type, 1B: INA addr, 1B: extra, 4B: Rs
-    cmd = struct.pack("<HBBBBI", self.CMD_ADDINA,
-                      bus, ina_type, addr, extra, resistance)
-    ret = self.wr_command(cmd)
-    if ret == 0:
-      if data:
-        name = data['name']
-      else:
-        name = "ina%d_%02x" % (bus, addr)
-      self.append_ina_struct(name, resistance, bus, addr,
-                             data=data, ina_type=ina_type)
-    self._logger.debug("Command ADD_INA: %s",
-                       "success" if ret == 0 else "failure")
-
-  def report_header_size(self):
-    """Helper function to calculate power record header size."""
-    result = 2
-    timestamp = 8
-    return result + timestamp
-
-  def report_size(self, ina_count):
-    """Helper function to calculate full power record size."""
-    record = 2
-
-    datasize = self.report_header_size() + ina_count * record
-    # Round to multiple of 4 bytes.
-    datasize = int(((datasize + 3) // 4) * 4)
-
-    return datasize
-
-  def read_line(self):
-    """Read a line of data from the setup INAs
-
-    Returns:
-      list of dicts of the values read by ina/type tuple, otherwise None.
-      [{ts:100, (vbat, power):450}, {ts:200, (vbat, power):440}]
-    """
-    try:
-      expected_bytes = self.report_size(len(self._inas))
-      cmd = struct.pack("<H", self.CMD_NEXT)
-      bytesread = self.wr_command(cmd, read_count=expected_bytes)
-    except usb.core.USBError as e:
-      self._logger.error("READ LINE FAILED %s", e)
-      return None
-
-    if len(bytesread) == 1:
-      if bytesread[0] != 0x6:
-        self._logger.debug("READ LINE FAILED bytes: %d ret: %02x",
-                           len(bytesread), bytesread[0])
-      return None
-
-    if len(bytesread) % expected_bytes != 0:
-      self._logger.debug("READ LINE WARNING: expected %d, got %d",
-          expected_bytes, len(bytesread))
-
-    packet_count = len(bytesread) // expected_bytes
-
-    values = []
-    for i in range(0, packet_count):
-      start = i * expected_bytes
-      end = (i + 1) * expected_bytes
-      record = self.interpret_line(bytesread[start:end])
-      values.append(record)
-
-    return values
-
-  def interpret_line(self, data):
-    """Interpret a power record from INAs
-
-    Args:
-      data: one single record of bytes.
-
-    Output:
-      stdout of the record in csv format.
-
-    Returns:
-      dict containing name, value of recorded data.
-    """
-    status, size = struct.unpack("<BB", data[0:2])
-    if len(data) != self.report_size(size):
-      self._logger.error("READ LINE FAILED st:%d size:%d expected:%d len:%d",
-                         status, size, self.report_size(size), len(data))
-    else:
-      pass
-
-    timestamp = struct.unpack("<Q", data[2:10])[0]
-    self._logger.debug("READ LINE: st:%d size:%d time:%dus", status, size,
-                       timestamp)
-    ftimestamp = float(timestamp) / 1000000.
-
-    record = {"ts": ftimestamp, "status": status, "berry":self._board}
-
-    for i in range(0, size):
-      idx = self.report_header_size() + 2*i
-      name = self._inas[i]['name']
-      name_tuple = (self._inas[i]['name'], self._inas[i]['type'])
-
-      raw_val = struct.unpack("<h", data[idx:idx+2])[0]
-
-      if self._inas[i]['type'] == Spower.INA_POWER:
-        val = raw_val * self._inas[i]['uWscale']
-      elif self._inas[i]['type'] == Spower.INA_BUSV:
-        val = raw_val * self._inas[i]['mVscale']
-      elif self._inas[i]['type'] == Spower.INA_CURRENT:
-        val = raw_val * self._inas[i]['uAscale']
-      elif self._inas[i]['type'] == Spower.INA_SHUNTV:
-        val = raw_val * self._inas[i]['uVscale']
-
-      self._logger.debug("READ %d %s: %fs: 0x%04x %f", i, name, ftimestamp,
-                         raw_val, val)
-      record[name_tuple] = val
-
-    return record
-
-  def load_board(self, brdfile):
-    """Load a board config.
-
-    Args:
-      brdfile:	Filename of a json file decribing the INA wiring of this board.
-    """
-    with open(process_filename(brdfile)) as data_file:
-        data = json.load(data_file)
-
-    #TODO: validate this.
-    self._brdcfg = data;
-    self._logger.debug(pprint.pformat(data))
-
-
-class powerlog(object):
-  """Power class to log aggregated power.
-
-  Usage:
-    obj = powerlog()
-
-  Instance Variables:
-    _data: a StatsManager object that records sweetberry readings and calculates
-           statistics.
-    _pwr[]: Spower objects for individual sweetberries.
-  """
-
-  def __init__(self, brdfile, cfgfile, serial_a=None, serial_b=None,
-               sync_date=False, use_ms=False, use_mW=False, print_stats=False,
-               stats_dir=None, stats_json_dir=None, print_raw_data=True,
-               raw_data_dir=None):
-    """Init the powerlog class and set the variables.
-
-    Args:
-      brdfile: string name of json file containing board layout.
-      cfgfile: string name of json containing list of rails to read.
-      serial_a: serial number of sweetberry A.
-      serial_b: serial number of sweetberry B.
-      sync_date: report timestamps synced with host datetime.
-      use_ms: report timestamps in ms rather than us.
-      use_mW: report power as milliwatts, otherwise default to microwatts.
-      print_stats: print statistics for sweetberry readings at the end.
-      stats_dir: directory to save sweetberry readings statistics; if None then
-                 do not save the statistics.
-      stats_json_dir: directory to save means of sweetberry readings in json
-                      format; if None then do not save the statistics.
-      print_raw_data: print sweetberry readings raw data in real time, default
-                      is to print.
-      raw_data_dir: directory to save sweetberry readings raw data; if None then
-                    do not save the raw data.
-    """
-    self._logger = logging.getLogger(__name__)
-    self._data = StatsManager()
-    self._pwr = {}
-    self._use_ms = use_ms
-    self._use_mW = use_mW
-    self._print_stats = print_stats
-    self._stats_dir = stats_dir
-    self._stats_json_dir = stats_json_dir
-    self._print_raw_data = print_raw_data
-    self._raw_data_dir = raw_data_dir
-
-    if not serial_a and not serial_b:
-      self._pwr['A'] = Spower('A')
-    if serial_a:
-      self._pwr['A'] = Spower('A', serialname=serial_a)
-    if serial_b:
-      self._pwr['B'] = Spower('B', serialname=serial_b)
-
-    with open(process_filename(cfgfile)) as data_file:
-      names = json.load(data_file)
-    self._names = self.process_scenario(names)
-
-    for key in self._pwr:
-      self._pwr[key].load_board(brdfile)
-      self._pwr[key].reset()
-
-    # Allocate the rails to the appropriate boards.
-    used_boards = []
-    for name in self._names:
-      success = False
-      for key in self._pwr.keys():
-        if self._pwr[key].add_ina_name(name):
-          success = True
-          if key not in used_boards:
-            used_boards.append(key)
-      if not success:
-        raise Exception("Failed to add %s (maybe missing "
-                        "sweetberry, or bad board file?)" % name)
-
-    # Evict unused boards.
-    for key in list(self._pwr.keys()):
-      if key not in used_boards:
-        self._pwr.pop(key)
-
-    for key in self._pwr.keys():
-      if sync_date:
-        self._pwr[key].set_time(time.time() * 1000000)
-      else:
-        self._pwr[key].set_time(0)
-
-  def process_scenario(self, name_list):
-    """Return list of tuples indicating name and type.
-
-    Args:
-      json originated list of names, or [name, type]
-    Returns:
-      list of tuples of (name, type) defaulting to type "POWER"
-    Raises: exception, invalid INA type.
-    """
-    names = []
-    for entry in name_list:
-      if isinstance(entry, list):
-        name = entry[0]
-        if entry[1] == "POWER":
-          type = Spower.INA_POWER
-        elif entry[1] == "BUSV":
-          type = Spower.INA_BUSV
-        elif entry[1] == "CURRENT":
-          type = Spower.INA_CURRENT
-        elif entry[1] == "SHUNTV":
-          type = Spower.INA_SHUNTV
-        else:
-          raise Exception("Invalid INA type", "Type of %s [%s] not recognized,"
-                    " try one of POWER, BUSV, CURRENT" % (entry[0], entry[1]))
-      else:
-        name = entry
-        type = Spower.INA_POWER
-
-      names.append((name, type))
-    return names
-
-  def start(self, integration_us_request, seconds, sync_speed=.8):
-    """Starts sampling.
-
-    Args:
-      integration_us_request: requested interval between sample values.
-      seconds: time until exit, or None to run until cancel.
-      sync_speed: A usb request is sent every [.8] * integration_us.
-    """
-    # We will get back the actual integration us.
-    # It should be the same for all devices.
-    integration_us = None
-    for key in self._pwr:
-      integration_us_new = self._pwr[key].start(integration_us_request)
-      if integration_us:
-        if integration_us != integration_us_new:
-          raise Exception("FAIL",
-              "Integration on A: %dus != integration on B %dus" % (
-              integration_us, integration_us_new))
-      integration_us = integration_us_new
-
-    # CSV header
-    title = "ts:%dus" % integration_us
-    for name_tuple in self._names:
-      name, ina_type = name_tuple
-
-      if ina_type == Spower.INA_POWER:
-        unit = "mW" if self._use_mW else "uW"
-      elif ina_type == Spower.INA_BUSV:
-        unit = "mV"
-      elif ina_type == Spower.INA_CURRENT:
-        unit = "uA"
-      elif ina_type == Spower.INA_SHUNTV:
-        unit = "uV"
-
-      title += ", %s %s" % (name, unit)
-      name_type = name + Spower.INA_SUFFIX[ina_type]
-      self._data.SetUnit(name_type, unit)
-    title += ", status"
-    if self._print_raw_data:
-      logoutput(title)
-
-    forever = False
-    if not seconds:
-      forever = True
-    end_time = time.time() + seconds
-    try:
-      pending_records = []
-      while forever or end_time > time.time():
-        if (integration_us > 5000):
-          time.sleep((integration_us / 1000000.) * sync_speed)
-        for key in self._pwr:
-          records = self._pwr[key].read_line()
-          if not records:
-            continue
-
-          for record in records:
-            pending_records.append(record)
-
-        pending_records.sort(key=lambda r: r['ts'])
-
-        aggregate_record = {"boards": set()}
-        for record in pending_records:
-          if record["berry"] not in aggregate_record["boards"]:
-            for rkey in record.keys():
-              aggregate_record[rkey] = record[rkey]
-            aggregate_record["boards"].add(record["berry"])
-          else:
-            self._logger.info("break %s, %s", record["berry"],
-                              aggregate_record["boards"])
-            break
-
-          if aggregate_record["boards"] == set(self._pwr.keys()):
-            csv = "%f" % aggregate_record["ts"]
-            for name in self._names:
-              if name in aggregate_record:
-                multiplier = 0.001 if (self._use_mW and
-                    name[1]==Spower.INA_POWER) else 1
-                value = aggregate_record[name] * multiplier
-                csv += ", %.2f" % value
-                name_type = name[0] + Spower.INA_SUFFIX[name[1]]
-                self._data.AddSample(name_type, value)
-              else:
-                csv += ", "
-            csv += ", %d" % aggregate_record["status"]
-            if self._print_raw_data:
-              logoutput(csv)
-
-            aggregate_record = {"boards": set()}
-            for r in range(0, len(self._pwr)):
-              pending_records.pop(0)
-
-    except KeyboardInterrupt:
-      self._logger.info('\nCTRL+C caught.')
-
-    finally:
-      for key in self._pwr:
-        self._pwr[key].stop()
-      self._data.CalculateStats()
-      if self._print_stats:
-        print(self._data.SummaryToString())
-      save_dir = 'sweetberry%s' % time.time()
-      if self._stats_dir:
-        stats_dir = os.path.join(self._stats_dir, save_dir)
-        self._data.SaveSummary(stats_dir)
-      if self._stats_json_dir:
-        stats_json_dir = os.path.join(self._stats_json_dir, save_dir)
-        self._data.SaveSummaryJSON(stats_json_dir)
-      if self._raw_data_dir:
-        raw_data_dir = os.path.join(self._raw_data_dir, save_dir)
-        self._data.SaveRawData(raw_data_dir)
-
-
-def main(argv=None):
-  if argv is None:
-    argv = sys.argv[1:]
-  # Command line argument description.
-  parser = argparse.ArgumentParser(
-      description="Gather CSV data from sweetberry")
-  parser.add_argument('-b', '--board', type=str,
-      help="Board configuration file, eg. my.board", default="")
-  parser.add_argument('-c', '--config', type=str,
-      help="Rail config to monitor, eg my.scenario", default="")
-  parser.add_argument('-A', '--serial', type=str,
-      help="Serial number of sweetberry A", default="")
-  parser.add_argument('-B', '--serial_b', type=str,
-      help="Serial number of sweetberry B", default="")
-  parser.add_argument('-t', '--integration_us', type=int,
-      help="Target integration time for samples", default=100000)
-  parser.add_argument('-s', '--seconds', type=float,
-      help="Seconds to run capture", default=0.)
-  parser.add_argument('--date', default=False,
-      help="Sync logged timestamp to host date", action="store_true")
-  parser.add_argument('--ms', default=False,
-      help="Print timestamp as milliseconds", action="store_true")
-  parser.add_argument('--mW', default=False,
-      help="Print power as milliwatts, otherwise default to microwatts",
-      action="store_true")
-  parser.add_argument('--slow', default=False,
-      help="Intentionally overflow", action="store_true")
-  parser.add_argument('--print_stats', default=False, action="store_true",
-      help="Print statistics for sweetberry readings at the end")
-  parser.add_argument('--save_stats', type=str, nargs='?',
-      dest='stats_dir', metavar='STATS_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save statistics for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--save_stats_json', type=str, nargs='?',
-      dest='stats_json_dir', metavar='STATS_JSON_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save means for sweetberry readings in json to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--no_print_raw_data',
-      dest='print_raw_data', default=True, action="store_false",
-      help="Not print raw sweetberry readings at real time, default is to "
-           "print")
-  parser.add_argument('--save_raw_data', type=str, nargs='?',
-      dest='raw_data_dir', metavar='RAW_DATA_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save raw data for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "raw data will be saved to where %(prog)s is located; if this flag "
-           "is not set, then do not save raw data")
-  parser.add_argument('-v', '--verbose', default=False,
-      help="Very chatty printout", action="store_true")
-
-  args = parser.parse_args(argv)
-
-  root_logger = logging.getLogger(__name__)
-  if args.verbose:
-    root_logger.setLevel(logging.DEBUG)
-  else:
-    root_logger.setLevel(logging.INFO)
-
-  # if powerlog is used through main, log to sys.stdout
-  if __name__ == "__main__":
-    stdout_handler = logging.StreamHandler(sys.stdout)
-    stdout_handler.setFormatter(logging.Formatter('%(levelname)s: %(message)s'))
-    root_logger.addHandler(stdout_handler)
-
-  integration_us_request = args.integration_us
-  if not args.board:
-    raise Exception("Power", "No board file selected, see board.README")
-  if not args.config:
-    raise Exception("Power", "No config file selected, see board.README")
-
-  brdfile = args.board
-  cfgfile = args.config
-  seconds = args.seconds
-  serial_a = args.serial
-  serial_b = args.serial_b
-  sync_date = args.date
-  use_ms = args.ms
-  use_mW = args.mW
-  print_stats = args.print_stats
-  stats_dir = args.stats_dir
-  stats_json_dir = args.stats_json_dir
-  print_raw_data = args.print_raw_data
-  raw_data_dir = args.raw_data_dir
-
-  boards = []
-
-  sync_speed = .8
-  if args.slow:
-    sync_speed = 1.2
-
-  # Set up logging interface.
-  powerlogger = powerlog(brdfile, cfgfile, serial_a=serial_a, serial_b=serial_b,
-      sync_date=sync_date, use_ms=use_ms, use_mW=use_mW,
-      print_stats=print_stats, stats_dir=stats_dir,
-      stats_json_dir=stats_json_dir,
-      print_raw_data=print_raw_data,raw_data_dir=raw_data_dir)
-
-  # Start logging.
-  powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed)
-
-
-if __name__ == "__main__":
-  main()
diff --git a/extra/usb_power/powerlog_unittest.py b/extra/usb_power/powerlog_unittest.py
deleted file mode 100644
index 1d0718530e..0000000000
--- a/extra/usb_power/powerlog_unittest.py
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Unit tests for powerlog."""
-
-import os
-import shutil
-import tempfile
-import unittest
-
-import powerlog
-
-class TestPowerlog(unittest.TestCase):
-  """Test to verify powerlog util methods work as expected."""
-
-  def setUp(self):
-    """Set up data and create a temporary directory to save data and stats."""
-    self.tempdir = tempfile.mkdtemp()
-    self.filename = 'testfile'
-    self.filepath = os.path.join(self.tempdir, self.filename)
-    with open(self.filepath, 'w') as f:
-      f.write('')
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_ProcessFilenameAbsoluteFilePath(self):
-    """Absolute file path is returned unchanged."""
-    processed_fname = powerlog.process_filename(self.filepath)
-    self.assertEqual(self.filepath, processed_fname)
-
-  def test_ProcessFilenameRelativeFilePath(self):
-    """Finds relative file path inside a known config location."""
-    original = powerlog.CONFIG_LOCATIONS
-    powerlog.CONFIG_LOCATIONS = [self.tempdir]
-    processed_fname = powerlog.process_filename(self.filename)
-    try:
-      self.assertEqual(self.filepath, processed_fname)
-    finally:
-      powerlog.CONFIG_LOCATIONS = original
-
-  def test_ProcessFilenameInvalid(self):
-    """IOError is raised when file cannot be found by any of the four ways."""
-    with self.assertRaises(IOError):
-      powerlog.process_filename(self.filename)
-
-if __name__ == '__main__':
-  unittest.main()
diff --git a/extra/usb_power/stats_manager.py b/extra/usb_power/stats_manager.py
deleted file mode 100644
index 0f8c3fcb15..0000000000
--- a/extra/usb_power/stats_manager.py
+++ /dev/null
@@ -1,401 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Calculates statistics for lists of data and pretty print them."""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import collections
-import json
-import logging
-import math
-import os
-
-import numpy
-
-STATS_PREFIX = '@@'
-NAN_TAG = '*'
-NAN_DESCRIPTION = '%s domains contain NaN samples' % NAN_TAG
-
-LONG_UNIT = {
-    '': 'N/A',
-    'mW': 'milliwatt',
-    'uW': 'microwatt',
-    'mV': 'millivolt',
-    'uA': 'microamp',
-    'uV': 'microvolt'
-}
-
-
-class StatsManagerError(Exception):
-  """Errors in StatsManager class."""
-  pass
-
-
-class StatsManager(object):
-  """Calculates statistics for several lists of data(float).
-
-  Example usage:
-
-    >>> stats = StatsManager(title='Title Banner')
-    >>> stats.AddSample(TIME_KEY, 50.0)
-    >>> stats.AddSample(TIME_KEY, 25.0)
-    >>> stats.AddSample(TIME_KEY, 40.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample('frobnicate', 11.5)
-    >>> stats.AddSample('frobnicate', 9.0)
-    >>> stats.AddSample('foobar', 11111.0)
-    >>> stats.AddSample('foobar', 22222.0)
-    >>> stats.CalculateStats()
-    >>> print(stats.SummaryToString())
-  ` @@--------------------------------------------------------------
-  ` @@                        Title Banner
-    @@--------------------------------------------------------------
-    @@            NAME  COUNT      MEAN   STDDEV       MAX       MIN
-    @@   sample_msecs      4     31.25    15.16     50.00     10.00
-    @@         foobar      2  16666.50  5555.50  22222.00  11111.00
-    @@     frobnicate      2     10.25     1.25     11.50      9.00
-  ` @@--------------------------------------------------------------
-
-  Attributes:
-    _data: dict of list of readings for each domain(key)
-    _unit: dict of unit for each domain(key)
-    _smid: id supplied to differentiate data output to other StatsManager
-           instances that potentially save to the same directory
-           if smid all output files will be named |smid|_|fname|
-    _title: title to add as banner to formatted summary. If no title,
-            no banner gets added
-    _order: list of formatting order for domains. Domains not listed are
-            displayed in sorted order
-    _hide_domains: collection of domains to hide when formatting summary string
-    _accept_nan: flag to indicate if NaN samples are acceptable
-    _nan_domains: set to keep track of which domains contain NaN samples
-    _summary: dict of stats per domain (key): min, max, count, mean, stddev
-    _logger = StatsManager logger
-
-  Note:
-    _summary is empty until CalculateStats() is called, and is updated when
-    CalculateStats() is called.
-  """
-
-  # pylint: disable=W0102
-  def __init__(self, smid='', title='', order=[], hide_domains=[],
-               accept_nan=True):
-    """Initialize infrastructure for data and their statistics."""
-    self._title = title
-    self._data = collections.defaultdict(list)
-    self._unit = collections.defaultdict(str)
-    self._smid = smid
-    self._order = order
-    self._hide_domains = hide_domains
-    self._accept_nan = accept_nan
-    self._nan_domains = set()
-    self._summary = {}
-    self._logger = logging.getLogger(type(self).__name__)
-
-  def AddSample(self, domain, sample):
-    """Add one sample for a domain.
-
-    Args:
-      domain: the domain name for the sample.
-      sample: one time sample for domain, expect type float.
-
-    Raises:
-      StatsManagerError: if trying to add NaN and |_accept_nan| is false
-    """
-    try:
-      sample = float(sample)
-    except ValueError:
-      # if we don't accept nan this will be caught below
-      self._logger.debug('sample %s for domain %s is not a number. Making NaN',
-                         sample, domain)
-      sample = float('NaN')
-    if not self._accept_nan and math.isnan(sample):
-      raise StatsManagerError('accept_nan is false. Cannot add NaN sample.')
-    self._data[domain].append(sample)
-    if math.isnan(sample):
-      self._nan_domains.add(domain)
-
-  def SetUnit(self, domain, unit):
-    """Set the unit for a domain.
-
-    There can be only one unit for each domain. Setting unit twice will
-    overwrite the original unit.
-
-    Args:
-      domain: the domain name.
-      unit: unit of the domain.
-    """
-    if domain in self._unit:
-      self._logger.warning('overwriting the unit of %s, old unit is %s, new '
-                           'unit is %s.', domain, self._unit[domain], unit)
-    self._unit[domain] = unit
-
-  def CalculateStats(self):
-    """Calculate stats for all domain-data pairs.
-
-    First erases all previous stats, then calculate stats for all data.
-    """
-    self._summary = {}
-    for domain, data in self._data.items():
-      data_np = numpy.array(data)
-      self._summary[domain] = {
-          'mean': numpy.nanmean(data_np),
-          'min': numpy.nanmin(data_np),
-          'max': numpy.nanmax(data_np),
-          'stddev': numpy.nanstd(data_np),
-          'count': data_np.size,
-      }
-
-  @property
-  def DomainsToDisplay(self):
-    """List of domains that the manager will output in summaries."""
-    return set(self._summary.keys()) - set(self._hide_domains)
-
-  @property
-  def NanInOutput(self):
-    """Return whether any of the domains to display have NaN values."""
-    return bool(len(set(self._nan_domains) & self.DomainsToDisplay))
-
-  def _SummaryTable(self):
-    """Generate the matrix to output as a summary.
-
-    Returns:
-      A 2d matrix of headers and their data for each domain
-      e.g.
-      [[NAME, COUNT, MEAN, STDDEV, MAX, MIN],
-       [pp5000_mw, 10, 50, 0, 50, 50]]
-    """
-    headers = ('NAME', 'COUNT', 'MEAN', 'STDDEV', 'MAX', 'MIN')
-    table = [headers]
-    # determine what domains to display & and the order
-    domains_to_display = self.DomainsToDisplay
-    display_order = [key for key in self._order if key in domains_to_display]
-    domains_to_display -= set(display_order)
-    display_order.extend(sorted(domains_to_display))
-    for domain in display_order:
-      stats = self._summary[domain]
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      if domain in self._nan_domains:
-        domain = '%s%s' % (domain, NAN_TAG)
-      row = [domain]
-      row.append(str(stats['count']))
-      for entry in headers[2:]:
-        row.append('%.2f' % stats[entry.lower()])
-      table.append(row)
-    return table
-
-  def SummaryToMarkdownString(self):
-    """Format the summary into a b/ compatible markdown table string.
-
-    This requires this sort of output format
-
-    | header1   | header2   | header3   | ...
-    | --------- | --------- | --------- | ...
-    | sample1h1 | sample1h2 | sample1h3 | ...
-    .
-    .
-    .
-
-    Returns:
-      formatted summary string.
-    """
-    # All we need to do before processing is insert a row of '-' between
-    # the headers, and the data
-    table = self._SummaryTable()
-    columns = len(table[0])
-    # Using '-:' to allow the numbers to be right aligned
-    sep_row = ['-'] + ['-:'] * (columns - 1)
-    table.insert(1, sep_row)
-    text_rows = ['|'.join(r) for r in table]
-    body = '\n'.join(['|%s|' % r for r in text_rows])
-    if self._title:
-      title_section = '**%s**  \n\n' % self._title
-      body = title_section + body
-    # Make sure that the body is terminated with a newline.
-    return body + '\n'
-
-  def SummaryToString(self, prefix=STATS_PREFIX):
-    """Format summary into a string, ready for pretty print.
-
-    See class description for format example.
-
-    Args:
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      formatted summary string.
-    """
-    table = self._SummaryTable()
-    max_col_width = []
-    for col_idx in range(len(table[0])):
-      col_item_widths = [len(row[col_idx]) for row in table]
-      max_col_width.append(max(col_item_widths))
-
-    formatted_lines = []
-    for row in table:
-      formatted_row = prefix + ' '
-      for i in range(len(row)):
-        formatted_row += row[i].rjust(max_col_width[i] + 2)
-      formatted_lines.append(formatted_row)
-    if self.NanInOutput:
-      formatted_lines.append('%s %s' % (prefix, NAN_DESCRIPTION))
-
-    if self._title:
-      line_length = len(formatted_lines[0])
-      dec_length = len(prefix)
-      # trim title to be at most as long as the longest line without the prefix
-      title = self._title[:(line_length - dec_length)]
-      # line is a seperator line consisting of -----
-      line = '%s%s' % (prefix, '-' * (line_length - dec_length))
-      # prepend the prefix to the centered title
-      padded_title = '%s%s' % (prefix, title.center(line_length)[dec_length:])
-      formatted_lines = [line, padded_title, line] + formatted_lines + [line]
-    formatted_output = '\n'.join(formatted_lines)
-    return formatted_output
-
-  def GetSummary(self):
-    """Getter for summary."""
-    return self._summary
-
-  def _MakeUniqueFName(self, fname):
-    """prepend |_smid| to fname & rotate fname to ensure uniqueness.
-
-    Before saving a file through the StatsManager, make sure that the filename
-    is unique, first by prepending the smid if any and otherwise by appending
-    increasing integer suffixes until the filename is unique.
-
-    If |smid| is defined /path/to/example/file.txt becomes
-    /path/to/example/{smid}_file.txt.
-
-    The rotation works by changing /path/to/example/somename.txt to
-    /path/to/example/somename1.txt if the first one already exists on the
-    system.
-
-    Note: this is not thread-safe. While it makes sense to use StatsManager
-    in a threaded data-collection, the data retrieval should happen in a
-    single threaded environment to ensure files don't get potentially clobbered.
-
-    Args:
-      fname: filename to ensure uniqueness.
-
-    Returns:
-      {smid_}fname{tag}.[b].ext
-      the smid portion gets prepended if |smid| is defined
-      the tag portion gets appended if necessary to ensure unique fname
-    """
-    fdir = os.path.dirname(fname)
-    base, ext = os.path.splitext(os.path.basename(fname))
-    if self._smid:
-      base = '%s_%s' % (self._smid, base)
-    unique_fname = os.path.join(fdir, '%s%s' % (base, ext))
-    tag = 0
-    while os.path.exists(unique_fname):
-      old_fname = unique_fname
-      unique_fname = os.path.join(fdir, '%s%d%s' % (base, tag, ext))
-      self._logger.warning('Attempted to store stats information at %s, but '
-                           'file already exists. Attempting to store at %s '
-                           'now.', old_fname, unique_fname)
-      tag += 1
-    return unique_fname
-
-  def SaveSummary(self, directory, fname='summary.txt', prefix=STATS_PREFIX):
-    """Save summary to file.
-
-    Args:
-      directory: directory to save the summary in.
-      fname: filename to save summary under.
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      full path of summary save location
-    """
-    summary_str = self.SummaryToString(prefix=prefix) + '\n'
-    return self._SaveSummary(summary_str, directory, fname)
-
-  def SaveSummaryJSON(self, directory, fname='summary.json'):
-    """Save summary (only MEAN) into a JSON file.
-
-    Args:
-      directory: directory to save the JSON summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    data = {}
-    for domain in self._summary:
-      unit = LONG_UNIT.get(self._unit[domain], self._unit[domain])
-      data_entry = {'mean': self._summary[domain]['mean'], 'unit': unit}
-      data[domain] = data_entry
-    summary_str = json.dumps(data, indent=2)
-    return self._SaveSummary(summary_str, directory, fname)
-
-  def SaveSummaryMD(self, directory, fname='summary.md'):
-    """Save summary into a MD file to paste into b/.
-
-    Args:
-      directory: directory to save the MD summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    summary_str = self.SummaryToMarkdownString()
-    return self._SaveSummary(summary_str, directory, fname)
-
-  def _SaveSummary(self, output_str, directory, fname):
-    """Wrote |output_str| to |fname|.
-
-    Args:
-      output_str: formatted output string
-      directory: directory to save the summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    fname = self._MakeUniqueFName(os.path.join(directory, fname))
-    with open(fname, 'w') as f:
-      f.write(output_str)
-    return fname
-
-  def GetRawData(self):
-    """Getter for all raw_data."""
-    return self._data
-
-  def SaveRawData(self, directory, dirname='raw_data'):
-    """Save raw data to file.
-
-    Args:
-      directory: directory to create the raw data folder in.
-      dirname: folder in which raw data live.
-
-    Returns:
-      list of full path of each domain's raw data save location
-    """
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    dirname = os.path.join(directory, dirname)
-    if not os.path.exists(dirname):
-      os.makedirs(dirname)
-    fnames = []
-    for domain, data in self._data.items():
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      fname = self._MakeUniqueFName(os.path.join(dirname, '%s.txt' % domain))
-      with open(fname, 'w') as f:
-        f.write('\n'.join('%.2f' % sample for sample in data) + '\n')
-      fnames.append(fname)
-    return fnames
diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py
deleted file mode 100644
index beb9984b93..0000000000
--- a/extra/usb_power/stats_manager_unittest.py
+++ /dev/null
@@ -1,315 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Unit tests for StatsManager."""
-
-from __future__ import print_function
-import json
-import os
-import re
-import shutil
-import tempfile
-import unittest
-
-import stats_manager
-
-
-class TestStatsManager(unittest.TestCase):
-  """Test to verify StatsManager methods work as expected.
-
-  StatsManager should collect raw data, calculate their statistics, and save
-  them in expected format.
-  """
-
-  def _populate_mock_stats(self):
-    """Create a populated & processed StatsManager to test data retrieval."""
-    self.data.AddSample('A', 99999.5)
-    self.data.AddSample('A', 100000.5)
-    self.data.SetUnit('A', 'uW')
-    self.data.SetUnit('A', 'mW')
-    self.data.AddSample('B', 1.5)
-    self.data.AddSample('B', 2.5)
-    self.data.AddSample('B', 3.5)
-    self.data.SetUnit('B', 'mV')
-    self.data.CalculateStats()
-
-  def _populate_mock_stats_no_unit(self):
-    self.data.AddSample('B', 1000)
-    self.data.AddSample('A', 200)
-    self.data.SetUnit('A', 'blue')
-
-  def setUp(self):
-    """Set up StatsManager and create a temporary directory for test."""
-    self.tempdir = tempfile.mkdtemp()
-    self.data = stats_manager.StatsManager()
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_AddSample(self):
-    """Adding a sample successfully adds a sample."""
-    self.data.AddSample('Test', 1000)
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_AddSampleNoFloatAcceptNaN(self):
-    """Adding a non-number adds 'NaN' and doesn't raise an exception."""
-    self.data.AddSample('Test', 10)
-    self.data.AddSample('Test', 20)
-    # adding a fake NaN: one that gets converted into NaN internally
-    self.data.AddSample('Test', 'fiesta')
-    # adding a real NaN
-    self.data.AddSample('Test', float('NaN'))
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    # assert that 'NaN' as added.
-    self.assertEqual(4, summary['Test']['count'])
-    # assert that mean, min, and max calculatings ignore the 'NaN'
-    self.assertEqual(10, summary['Test']['min'])
-    self.assertEqual(20, summary['Test']['max'])
-    self.assertEqual(15, summary['Test']['mean'])
-
-  def test_AddSampleNoFloatNotAcceptNaN(self):
-    """Adding a non-number raises a StatsManagerError if accept_nan is False."""
-    self.data = stats_manager.StatsManager(accept_nan=False)
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a fake NaN: one that gets converted into NaN internally
-      self.data.AddSample('Test', 'fiesta')
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a real NaN
-      self.data.AddSample('Test', float('NaN'))
-
-  def test_AddSampleNoUnit(self):
-    """Not adding a unit does not cause an exception on CalculateStats()."""
-    self.data.AddSample('Test', 17)
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_UnitSuffix(self):
-    """Unit gets appended as a suffix in the displayed summary."""
-    self.data.AddSample('test', 250)
-    self.data.SetUnit('test', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-
-  def test_DoubleUnitSuffix(self):
-    """If domain already ends in unit, verify that unit doesn't get appended."""
-    self.data.AddSample('test_mw', 250)
-    self.data.SetUnit('test_mw', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-    self.assertNotIn('test_mw_mw', summary_str)
-
-  def test_GetRawData(self):
-    """GetRawData returns exact same data as fed in."""
-    self._populate_mock_stats()
-    raw_data = self.data.GetRawData()
-    self.assertListEqual([99999.5, 100000.5], raw_data['A'])
-    self.assertListEqual([1.5, 2.5, 3.5], raw_data['B'])
-
-  def test_GetSummary(self):
-    """GetSummary returns expected stats about the data fed in."""
-    self._populate_mock_stats()
-    summary = self.data.GetSummary()
-    self.assertEqual(2, summary['A']['count'])
-    self.assertAlmostEqual(100000.5, summary['A']['max'])
-    self.assertAlmostEqual(99999.5, summary['A']['min'])
-    self.assertAlmostEqual(0.5, summary['A']['stddev'])
-    self.assertAlmostEqual(100000.0, summary['A']['mean'])
-    self.assertEqual(3, summary['B']['count'])
-    self.assertAlmostEqual(3.5, summary['B']['max'])
-    self.assertAlmostEqual(1.5, summary['B']['min'])
-    self.assertAlmostEqual(0.81649658092773, summary['B']['stddev'])
-    self.assertAlmostEqual(2.5, summary['B']['mean'])
-
-  def test_SaveRawData(self):
-    """SaveRawData stores same data as fed in."""
-    self._populate_mock_stats()
-    dirname = 'unittest_raw_data'
-    expected_files = set(['A_mW.txt', 'B_mV.txt'])
-    fnames = self.data.SaveRawData(self.tempdir, dirname)
-    files_returned = set([os.path.basename(f) for f in fnames])
-    # Assert that only the expected files got returned.
-    self.assertEqual(expected_files, files_returned)
-    # Assert that only the returned files are in the outdir.
-    self.assertEqual(set(os.listdir(os.path.join(self.tempdir, dirname))),
-                     files_returned)
-    for fname in fnames:
-      with open(fname, 'r') as f:
-        if 'A_mW' in fname:
-          self.assertEqual('99999.50', f.readline().strip())
-          self.assertEqual('100000.50', f.readline().strip())
-        if 'B_mV' in fname:
-          self.assertEqual('1.50', f.readline().strip())
-          self.assertEqual('2.50', f.readline().strip())
-          self.assertEqual('3.50', f.readline().strip())
-
-  def test_SaveRawDataNoUnit(self):
-    """SaveRawData appends no unit suffix if the unit is not specified."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    outdir = 'unittest_raw_data'
-    files = self.data.SaveRawData(self.tempdir, outdir)
-    files = [os.path.basename(f) for f in files]
-    # Verify nothing gets appended to domain for filename if no unit exists.
-    self.assertIn('B.txt', files)
-
-  def test_SaveRawDataSMID(self):
-    """SaveRawData uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    files = self.data.SaveRawData(self.tempdir)
-    for fname in files:
-      self.assertTrue(os.path.basename(fname).startswith(identifier))
-
-  def test_SummaryToStringNaNHelp(self):
-    """NaN containing row gets tagged with *, help banner gets added."""
-    help_banner_exp = '%s %s' % (stats_manager.STATS_PREFIX,
-                                 stats_manager.NAN_DESCRIPTION)
-    nan_domain = 'A-domain'
-    nan_domain_exp = '%s%s' % (nan_domain, stats_manager.NAN_TAG)
-    # NaN helper banner is added when a NaN domain is found & domain gets tagged
-    data = stats_manager.StatsManager()
-    data.AddSample(nan_domain, float('NaN'))
-    data.AddSample(nan_domain, 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertIn(help_banner_exp, summarystr)
-    self.assertIn(nan_domain_exp, summarystr)
-    # NaN helper banner is not added when no NaN domain output, no tagging
-    data = stats_manager.StatsManager()
-    # nan_domain in this scenario does not contain any NaN
-    data.AddSample(nan_domain, 19)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertNotIn(help_banner_exp, summarystr)
-    self.assertNotIn(nan_domain_exp, summarystr)
-
-  def test_SummaryToStringTitle(self):
-    """Title shows up in SummaryToString if title specified."""
-    title = 'titulo'
-    data = stats_manager.StatsManager(title=title)
-    self._populate_mock_stats()
-    summary_str = data.SummaryToString()
-    self.assertIn(title, summary_str)
-
-  def test_SummaryToStringHideDomains(self):
-    """Keys indicated in hide_domains are not printed in the summary."""
-    data = stats_manager.StatsManager(hide_domains=['A-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertIn('B-domain', summary_str)
-    self.assertNotIn('A-domain', summary_str)
-
-  def test_SummaryToStringOrder(self):
-    """Order passed into StatsManager is honoured when formatting summary."""
-    # StatsManager that should print D & B first, and the subsequent elements
-    # are sorted.
-    d_b_a_c_regexp = re.compile('D-domain.*B-domain.*A-domain.*C-domain',
-                                re.DOTALL)
-    data = stats_manager.StatsManager(order=['D-domain', 'B-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.AddSample('C-domain', 17)
-    data.AddSample('D-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertRegexpMatches(summary_str, d_b_a_c_regexp)
-
-  def test_MakeUniqueFName(self):
-    data = stats_manager.StatsManager()
-    testfile = os.path.join(self.tempdir, 'testfile.txt')
-    with open(testfile, 'w') as f:
-      f.write('')
-    expected_fname = os.path.join(self.tempdir, 'testfile0.txt')
-    self.assertEqual(expected_fname, data._MakeUniqueFName(testfile))
-
-  def test_SaveSummary(self):
-    """SaveSummary properly dumps the summary into a file."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.txt'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummary(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      self.assertEqual(
-          '@@   NAME  COUNT       MEAN  STDDEV        MAX       MIN\n',
-          f.readline())
-      self.assertEqual(
-          '@@   A_mW      2  100000.00    0.50  100000.50  99999.50\n',
-          f.readline())
-      self.assertEqual(
-          '@@   B_mV      3       2.50    0.82       3.50      1.50\n',
-          f.readline())
-
-  def test_SaveSummarySMID(self):
-    """SaveSummary uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummary(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSON(self):
-    """SaveSummaryJSON saves the added data properly in JSON format."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.json'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertAlmostEqual(100000.0, summary['A']['mean'])
-      self.assertEqual('milliwatt', summary['A']['unit'])
-      self.assertAlmostEqual(2.5, summary['B']['mean'])
-      self.assertEqual('millivolt', summary['B']['unit'])
-
-  def test_SaveSummaryJSONSMID(self):
-    """SaveSummaryJSON uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSONNoUnit(self):
-    """SaveSummaryJSON marks unknown units properly as N/A."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    fname = 'unittest_summary.json'
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertEqual('blue', summary['A']['unit'])
-      # if no unit is specified, JSON should save 'N/A' as the unit.
-      self.assertEqual('N/A', summary['B']['unit'])
-
-if __name__ == '__main__':
-  unittest.main()
diff --git a/extra/usb_serial/.gitignore b/extra/usb_serial/.gitignore
deleted file mode 100644
index 77fee262b1..0000000000
--- a/extra/usb_serial/.gitignore
+++ /dev/null
@@ -1,12 +0,0 @@
-.built-in.o.cmd
-.raiden.ko.cmd
-.raiden.mod.o.cmd
-.raiden.o.cmd
-.tmp_versions/
-Module.symvers
-built-in.o
-modules.order
-raiden.ko
-raiden.mod.c
-raiden.mod.o
-raiden.o
diff --git a/extra/usb_serial/51-google-serial-fallback.rules b/extra/usb_serial/51-google-serial-fallback.rules
deleted file mode 100644
index 5f43e58e30..0000000000
--- a/extra/usb_serial/51-google-serial-fallback.rules
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Add USB VID/PID for usb-serial compatible CCD devices.  This is a fallback
-# rule that can be used if the raiden module can't be built, or used for some
-# reason.
-#
-SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="18d1", ENV{ID_USB_INTERFACES}=="*:ff5001:*", RUN+="add_usb_serial_id $attr{idVendor} $attr{idProduct}"
diff --git a/extra/usb_serial/51-google-serial.rules b/extra/usb_serial/51-google-serial.rules
deleted file mode 100644
index 3dedac1b1f..0000000000
--- a/extra/usb_serial/51-google-serial.rules
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# Rules for Google Case Closed Debugging devices.
-#
-# The first rule matches the google VID and records the product name, USB bus
-# number and USB device path (the device path is the list of hub ports between
-# the root and the device).  This becomes a unique directory name under which
-# later rules can create symlinks.  If this rule doesn't match udev will skip
-# the rest of this files rules.
-#
-# This rule intentionally matches using SUBSYSTEMS and ATTRS instead of
-# SUBSYSTEM and ATTR so that the GOOGLE_CCD_NAME is available to all nodes
-# that descend from a Google USB device (this includes all USB interface nodes
-# as well as all of the TTY nodes derived from CCD USB interfaces).
-#
-SUBSYSTEMS=="usb", ATTRS{idVendor}=="18d1", ENV{GOOGLE_CCD_NAME}="$attr{product}-$attr{busnum}-$attr{devpath}"
-
-#
-# Force ModemManager to ignore all Google case closed debug devices.  It would
-# be better to just ignore the case closed debug serial console interfaces, but
-# ModemManager doesn't look at the usb_interface udev node, it looks at the
-# usb_device node, so you have to mark the entire device as incompatible with
-# ModemManager.
-#
-# This node could lose the match against the usb_device DEVTYPE and still work,
-# it would just add extraneous ID_MM_DEVICE_IGNORE tags to the TTY and USB
-# interface nodes.
-#
-SUBSYSTEM=="usb", ENV{GOOGLE_CCD_NAME}!="", ENV{DEVTYPE}=="usb_device", ENV{ID_USB_INTERFACES}=="*:ff5001:*", ENV{ID_MM_DEVICE_IGNORE}="1"
-
-#
-# Construct a symlink to a TTY generated from a CCD USB serial interface.
-#
-SUBSYSTEM=="tty", ENV{GOOGLE_CCD_NAME}!="", ATTRS{bInterfaceClass}=="ff", ATTRS{bInterfaceSubClass}=="50", ATTRS{bInterfaceProtocol}=="01", OPTIONS+="string_escape=replace", SYMLINK+="google/$env{GOOGLE_CCD_NAME}/serial/$attr{interface}"
diff --git a/extra/usb_serial/Makefile b/extra/usb_serial/Makefile
deleted file mode 100644
index 9c478050cc..0000000000
--- a/extra/usb_serial/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-obj-m := raiden.o
-
-.PHONY: all
-
-all: modules
-
-.DEFAULT:
-	$(MAKE) -C /lib/modules/$(shell uname -r)/build \
-		M=$(shell pwd) \
-		$(MAKECMDGOALS)
diff --git a/extra/usb_serial/README.md b/extra/usb_serial/README.md
deleted file mode 100644
index 7cc6030d0a..0000000000
--- a/extra/usb_serial/README.md
+++ /dev/null
@@ -1,5 +0,0 @@
-# Case Closed Debugging Serial Consoles over USB
-
-Please see the documentation in [case_closed_debugging doc][1]
-
-[1]:https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md
diff --git a/extra/usb_serial/add_usb_serial_id b/extra/usb_serial/add_usb_serial_id
deleted file mode 100755
index ef8336afdc..0000000000
--- a/extra/usb_serial/add_usb_serial_id
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/sh -e
-#
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Add a USB VID:PID device ID to the usbserial list of handled devices
-
-if [ $# -ne 2 ]; then
-    echo ""
-    echo "Usage: $0 <VID> <PID>"
-    echo ""
-    echo "Add a USB VID:PID device identification pair to the list of devices"
-    echo "that usbserial will recognize.  This script ensures that a device is"
-    echo "not added more than once."
-    echo ""
-    exit 1
-fi
-
-#
-# Firts ensure that the usbserial module is loaded.  This is required as there
-# may be no other USB serial adaptor connected yet.
-#
-modprobe usbserial
-
-device_id="$1 $2"
-file="/sys/bus/usb-serial/drivers/generic/new_id"
-
-#
-# Only add the device ID pair if it isn't already in the ID list.
-#
-grep -q "$device_id" $file || echo $device_id > $file
diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py
deleted file mode 100755
index 7b3bacd903..0000000000
--- a/extra/usb_serial/console.py
+++ /dev/null
@@ -1,298 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Allow creation of uart/console interface via usb google serial endpoint."""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import argparse
-import array
-import os
-import sys
-import termios
-import threading
-import time
-import traceback
-import tty
-try:
-  import usb
-except:
-  print("import usb failed")
-  print("try running these commands:")
-  print(" sudo apt-get install python-pip")
-  print(" sudo pip install --pre pyusb")
-  print()
-  sys.exit(-1)
-
-import six
-
-
-def GetBuffer(stream):
-  if six.PY3:
-    return stream.buffer
-  return stream
-
-
-"""Class Susb covers USB device discovery and initialization.
-
-  It can find a particular endpoint by vid:pid, serial number,
-  and interface number.
-"""
-
-class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-class Susb():
-  """Provide USB functionality.
-
-  Instance Variables:
-  _read_ep: pyUSB read endpoint for this interface
-  _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x500f, interface=1, serialname=None):
-    """Susb constructor.
-
-    Discovers and connects to USB endpoints.
-
-    Args:
-      vendor    : usb vendor id of device
-      product   : usb product id of device
-      interface : interface number ( 1 - 8 ) of device to use
-      serialname: string of device serialnumber.
-
-    Raises:
-      SusbError: An error accessing Susb object
-    """
-    # Find the device.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise SusbError("USB device not found")
-
-    # Check if we have multiple devices.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB doesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except:
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % (serialname,))
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        try:
-          dev = dev_list.next()
-        except:
-          raise SusbError("USB device %04x:%04x not found" % (vendor, product))
-
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
-
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface)
-    self._intf = intf
-
-    if not intf:
-      raise SusbError("Interface not found")
-
-    # Detach raiden.ko if it is loaded.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
-            dev.detach_kernel_driver(intf.bInterfaceNumber)
-
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
-
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
-
-
-"""Suart class implements a stream interface, to access Google's USB class.
-
-  This creates a send and receive thread that monitors USB and console input
-  and forwards them across. This particular class is hardcoded to stdin/out.
-"""
-
-class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-
-class Suart():
-  """Provide interface to serial usb endpoint."""
-
-  def __init__(self, vendor=0x18d1, product=0x501c, interface=0,
-               serialname=None):
-    """Suart contstructor.
-
-    Initializes USB stream interface.
-
-    Args:
-      vendor: usb vendor id of device
-      product: usb product id of device
-      interface: interface number of device to use
-      serialname: Defaults to None.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._done = threading.Event()
-    self._susb = Susb(vendor=vendor, product=product,
-        interface=interface, serialname=serialname)
-
-  def wait_until_done(self, timeout=None):
-    return self._done.wait(timeout=timeout)
-
-  def run_rx_thread(self):
-    try:
-      while True:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              GetBuffer(sys.stdout).write(r.tostring())
-              GetBuffer(sys.stdout).flush()
-
-          except Exception as e:
-            # If we miss some characters on pty disconnect, that's fine.
-            # ep.read() also throws USBError on timeout, which we discard.
-            if not isinstance(e, (OSError, usb.core.USBError)):
-              print("rx %s" % e)
-    finally:
-      self._done.set()
-
-  def run_tx_thread(self):
-    try:
-      while True:
-          try:
-            r = GetBuffer(sys.stdin).read(1)
-            if not r or r == b"\x03":
-              break
-            if r:
-              self._susb._write_ep.write(array.array('B', r),
-                                         self._susb.TIMEOUT_MS)
-          except Exception as e:
-            print("tx %s" % e)
-    finally:
-      self._done.set()
-
-  def run(self):
-    """Creates pthreads to poll USB & PTY for data.
-    """
-    self._exit = False
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread)
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread)
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
-
-
-
-"""Command line functionality
-
-  Allows specifying vid:pid, serialnumber, interface.
-  Ctrl-C exits.
-"""
-
-parser = argparse.ArgumentParser(description="Open a console to a USB device")
-parser.add_argument('-d', '--device', type=str,
-    help="vid:pid of target device", default="18d1:501c")
-parser.add_argument('-i', '--interface', type=int,
-    help="interface number of console", default=0)
-parser.add_argument('-s', '--serialno', type=str,
-    help="serial number of device", default="")
-parser.add_argument('-S', '--notty-exit-sleep', type=float, default=0.2,
-    help="When stdin is *not* a TTY, wait this many seconds after EOF from "
-    "stdin before exiting, to give time for receiving a reply from the USB "
-    "device.")
-
-
-def runconsole():
-  """Run the usb console code
-
-  Starts the pty thread, and idles until a ^C is caught.
-  """
-  args = parser.parse_args()
-
-  vidstr, pidstr = args.device.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
-
-  serialno = args.serialno
-  interface = args.interface
-
-  sobj = Suart(vendor=vid, product=pid, interface=interface,
-               serialname=serialno)
-  if sys.stdin.isatty():
-    tty.setraw(sys.stdin.fileno())
-  sobj.run()
-  sobj.wait_until_done()
-  if not sys.stdin.isatty() and args.notty_exit_sleep > 0:
-    time.sleep(args.notty_exit_sleep)
-
-
-def main():
-  stdin_isatty = sys.stdin.isatty()
-  if stdin_isatty:
-    fd = sys.stdin.fileno()
-    os.system("stty -echo")
-    old_settings = termios.tcgetattr(fd)
-
-  try:
-    runconsole()
-  finally:
-    if stdin_isatty:
-      termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
-      os.system("stty echo")
-    # Avoid having the user's shell prompt start mid-line after the final output
-    # from this program.
-    print()
-
-
-if __name__ == '__main__':
-  main()
diff --git a/extra/usb_serial/install b/extra/usb_serial/install
deleted file mode 100755
index eba1d2ac83..0000000000
--- a/extra/usb_serial/install
+++ /dev/null
@@ -1,88 +0,0 @@
-#!/bin/sh -e
-#
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Build and install raiden module and udev rules
-
-bold=$(tput bold)
-normal=$(tput sgr0)
-
-error() {
-    echo "${bold}Install failed${normal}"
-}
-
-trap "error $LINENO" ERR
-
-fallback=false
-
-if [ "$1" = "--fallback" ]; then
-    fallback=true
-    shift
-fi
-
-if [ $# -ne 0 ]; then
-    echo ""
-    echo "Usage: ${bold}$0${normal} [--fallback]"
-    echo ""
-    echo "Install Raiden kernel module and udev rules for working with Case"
-    echo "Closed Debug enabled devices."
-    echo ""
-    echo "${bold}--fallback${normal}"
-    echo "    Install udev rules to use usbserial directly without installing"
-    echo "    the raiden module.  This can be used when the raiden module fails"
-    echo "    to build, or can not be used for other reasons."
-    echo ""
-    echo "    The fallback solution will generate extra /dev/ttyUSB? entries"
-    echo "    for the SPI and possibly other CCD bridges.  These should be"
-    echo "    ignored by you.  Flashrom is smart enough to detach the kernel"
-    echo "    driver from the SPI bridge, so they will not interfere with"
-    echo "    flashing new firmware images over CCD."
-    echo ""
-    exit 1
-fi
-
-if [ "$fallback" = "false" ]; then
-    #
-    # The normal path builds and installs the raiden module
-    #
-    {
-	#
-	# Don't build the module as root so it's easier to clean up after
-	#
-	make modules &&
-
-	#
-	# Install the new module and update dependency and alias information
-	#
-	sudo make modules_install &&
-	sudo depmod -a
-    } || {
-	echo $bold
-	echo "Building and/or installing the raiden module failed, you may"
-	echo "want to use the --fallback option."
-	echo $normal
-	exit 1;
-    }
-else
-    #
-    # The fallback path installs the fallback udev rule and its helper script.
-    #
-    sudo install -m644 51-google-serial-fallback.rules /etc/udev/rules.d
-    sudo install add_usb_serial_id /lib/udev
-fi
-
-#
-# Install the udev rule for creating /dev/google symlinks.
-#
-sudo install -m644  51-google-serial.rules /etc/udev/rules.d
-
-#
-# Trigger udev to create the symlinks for any attached devices that have the
-# Google Vendor ID.  Limiting triggering like this prevents unwanted resetting
-# of some device state, even with the change action specified.
-#
-for syspath in $(dirname $(grep -rxl --include=idVendor 18d1 /sys/devices)); do
-    sudo udevadm trigger --action=change --parent-match=${syspath}
-done
diff --git a/extra/usb_serial/raiden.c b/extra/usb_serial/raiden.c
deleted file mode 100644
index e4720b4357..0000000000
--- a/extra/usb_serial/raiden.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * USB Serial module for Raiden USB debug serial console forwarding.
- * SubClass and Protocol allocated in go/usb-ids
- *
- * Copyright 2014 The Chromium OS Authors <chromium-os-dev@chromium.org>
- * Author: Anton Staaf <robotboy@chromium.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/usb.h>
-#include <linux/usb/serial.h>
-
-MODULE_LICENSE("GPL");
-
-#define USB_VENDOR_ID_GOOGLE		0x18d1
-#define USB_SUBCLASS_GOOGLE_SERIAL	0x50
-#define USB_PROTOCOL_GOOGLE_SERIAL	0x01
-
-static struct usb_device_id const ids[] = {
-	{ USB_VENDOR_AND_INTERFACE_INFO(USB_VENDOR_ID_GOOGLE,
-					USB_CLASS_VENDOR_SPEC,
-					USB_SUBCLASS_GOOGLE_SERIAL,
-					USB_PROTOCOL_GOOGLE_SERIAL) },
-        { 0 }
-};
-
-MODULE_DEVICE_TABLE(usb, ids);
-
-static struct usb_serial_driver device =
-{
-	.driver    = { .owner = THIS_MODULE,
-		       .name  = "Google" },
-	.id_table  = ids,
-	.num_ports = 1,
-};
-
-static struct usb_serial_driver * const drivers[] = { &device, NULL };
-
-module_usb_serial_driver(drivers, ids);
diff --git a/extra/usb_updater/.gitignore b/extra/usb_updater/.gitignore
deleted file mode 100644
index 37c3bd3808..0000000000
--- a/extra/usb_updater/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-generated_version.h
-gsctool
-usb_updater2
-*.d
-*.o
-dp
\ No newline at end of file
diff --git a/extra/usb_updater/Makefile b/extra/usb_updater/Makefile
deleted file mode 100644
index 1dfbc55645..0000000000
--- a/extra/usb_updater/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CC ?= gcc
-PKG_CONFIG ?= pkg-config
-PROGRAMS := usb_updater2
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-	-g \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-ifeq (DEBUG,)
-CFLAGS += -O3
-else
-CFLAGS += -O0
-endif
-
-#
-# Add libusb-1.0 required flags
-#
-LIBS    += $(shell $(PKG_CONFIG) --libs   libusb-1.0)
-CFLAGS  += $(shell $(PKG_CONFIG) --cflags libusb-1.0)
-CFLAGS  += -I../../include -I../../util -I../../fuzz -I../../test
-
-VPATH = ../../util
-
-LIBS_common  = -lfmap
-
-all: $(PROGRAMS)
-
-%.o: %.c
-	$(CC) $(CFLAGS) -c -MMD -MF $(basename $@).d -o $@ $<
-
-# common EC code USB updater
-usb_updater2: usb_updater2.c Makefile
-	$(CC) $(CFLAGS) $< $(LFLAGS) $(LIBS) $(LIBS_common) -o $@
-
-.PHONY: clean
-
-clean:
-	rm -rf $(PROGRAMS) *~ *.o *.d dp
-
-parser_debug: desc_parser.c
-	gcc -g -O0  -DTEST_PARSER desc_parser.c -o dp
-
diff --git a/extra/usb_updater/c2d2.json b/extra/usb_updater/c2d2.json
deleted file mode 100644
index 79fc6f0992..0000000000
--- a/extra/usb_updater/c2d2.json
+++ /dev/null
@@ -1,15 +0,0 @@
-{
-  "Comment": "This file describes the updateable sections of the flash.",
-  "board": "c2d2",
-  "vid": "0x18d1",
-  "pid": "0x5041",
-  "console": "3",
-  "Comment on flash": "This is the base address of writeable flash",
-  "flash": "0x8000000",
-  "Comment on region format": "name: [baseoffset, length]",
-  "regions": {
-    "RW": ["0x10000", "0x10000"],
-    "PSTATE": ["0xf000", "0x1000"],
-    "RO": ["0x0000", "0xf000"]
-  }
-}
diff --git a/extra/usb_updater/desc_parser.c b/extra/usb_updater/desc_parser.c
deleted file mode 100644
index 5bd996bdda..0000000000
--- a/extra/usb_updater/desc_parser.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <malloc.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/stat.h>
-
-#include "desc_parser.h"
-
-static FILE *hash_file_;
-static int line_count_;
-static int section_count_;
-
-/*
- * This is used to verify consistency of the description database, namely that
- * all hash sections include the same number of hash variants.
- */
-static size_t variant_count;
-
-/* Size of the retrieved string or negative OS error value. */
-static ssize_t get_next_line(char *next_line, size_t line_size)
-{
-	size_t index = 0;
-
-	while (fgets(next_line + index, line_size - index, hash_file_)) {
-		line_count_++;
-
-		if (next_line[index] == '#')
-			continue; /* Skip the comment */
-
-		if (next_line[index] == '\n') {
-			/*
-			 * This is an empty line, return all collected data,
-			 * pontintially an array of size zero if this is a
-			 * repeated empty line.
-			 */
-			next_line[index] = '\0';
-			return index;
-		}
-
-		/* Make sure next string overwrites this string's newline. */
-		index += strlen(next_line + index) - 1;
-
-		if (index >= (line_size - 1)) {
-			fprintf(stderr, "%s: Input overflow in line %d\n",
-				__func__, line_count_);
-			return -EOVERFLOW;
-		}
-	}
-
-	if (index) {
-		/*
-		 * This must be the last line in the file with no empty line
-		 * after it. Drop the closing newline, if it is there.
-		 */
-		if (next_line[index] == '\n')
-			next_line[index--] = '\0';
-
-		return index;
-	}
-	return errno ? -errno : -ENODATA;
-}
-
-static int get_next_token(char *input, size_t expected_size, char **output)
-{
-	char *next_colon;
-
-	next_colon = strchr(input, ':');
-	if (next_colon)
-		*next_colon = '\0';
-	if (!next_colon || (expected_size &&
-			    strlen(input) != expected_size)) {
-		fprintf(stderr, "Invalid entry in section %d\n",
-			section_count_);
-		return -EINVAL;
-	}
-
-	*output = next_colon + 1;
-	return 0;
-}
-
-static int get_hex_value(char *input, char **output)
-{
-	char *e;
-	long int value;
-
-	if (strchr(input, ':'))
-		get_next_token(input, 0, output);
-	else
-		*output = NULL;
-
-	value = strtol(input, &e, 16);
-	if ((e && *e) || (strlen(input) > 8)) {
-		fprintf(stderr, "Invalid hex value %s in section %d\n",
-			input, section_count_);
-		return -EINVAL;
-	}
-
-	return value;
-}
-
-static int parse_range(char *next_line,
-		       size_t line_len,
-		       struct addr_range *parsed_range)
-{
-	char *line_cursor;
-	char *next_token;
-	int is_a_hash_range;
-	struct result_node *node;
-	int value;
-
-	section_count_++;
-	line_cursor = next_line;
-
-	/* Range type. */
-	if (get_next_token(line_cursor, 1, &next_token))
-		return -EINVAL;
-
-	switch (*line_cursor) {
-	case 'a':
-		parsed_range->range_type = AP_RANGE;
-		break;
-	case 'e':
-		parsed_range->range_type = EC_RANGE;
-		break;
-	case 'g':
-		parsed_range->range_type = EC_GANG_RANGE;
-		break;
-	default:
-		fprintf(stderr, "Invalid range type %c in section %d\n",
-			*line_cursor, section_count_);
-		return -EINVAL;
-	}
-	line_cursor = next_token;
-
-	/* Hash or dump? */
-	if (get_next_token(line_cursor, 1, &next_token))
-		return -EINVAL;
-
-	switch (*line_cursor) {
-	case 'd':
-		is_a_hash_range = 0;
-		break;
-	case 'h':
-		is_a_hash_range = 1;
-		break;
-	default:
-		fprintf(stderr, "Invalid entry kind %c in section %d\n",
-			*line_cursor, section_count_);
-		return -EINVAL;
-	}
-	line_cursor = next_token;
-
-	/* Range base address. */
-	value = get_hex_value(line_cursor, &next_token);
-	if (value < 0)
-		return -EINVAL;
-	parsed_range->base_addr = value;
-
-	/* Range size. */
-	line_cursor = next_token;
-	value = get_hex_value(line_cursor, &next_token);
-	if (value < 0)
-		return -EINVAL;
-	parsed_range->range_size = value;
-
-	if (!next_token && is_a_hash_range) {
-		fprintf(stderr, "Missing hash in section %d\n", section_count_);
-		return -EINVAL;
-	}
-
-	if (next_token && !is_a_hash_range) {
-		fprintf(stderr, "Unexpected data in section %d\n",
-			section_count_);
-		return -EINVAL;
-	}
-
-	parsed_range->variant_count = 0;
-	if (!is_a_hash_range)
-		return 0; /* No more input for dump ranges. */
-
-	node = parsed_range->variants;
-	do { /* While line is not over. */
-		char c;
-		int i = 0;
-
-		line_cursor = next_token;
-		next_token = strchr(line_cursor, ':');
-		if (next_token)
-			*next_token++ = '\0';
-		if (strlen(line_cursor) != (2 * sizeof(*node))) {
-			fprintf(stderr,
-				"Invalid hash %zd size %zd in section %d\n",
-				parsed_range->variant_count + 1,
-				strlen(line_cursor), section_count_);
-			return -EINVAL;
-		}
-
-		while ((c = *line_cursor++) != 0) {
-			uint8_t nibble;
-
-			if (!isxdigit(c)) {
-				fprintf(stderr,
-					"Invalid hash %zd value in section %d\n",
-					parsed_range->variant_count + 1,
-					section_count_);
-				return -EINVAL;
-			}
-
-			if (c <= '9')
-				nibble = c - '0';
-			else if (c >= 'a')
-				nibble = c - 'a' + 10;
-			else
-				nibble = c - 'A' + 10;
-
-			if (i & 1)
-				node->expected_result[i / 2] |= nibble;
-			else
-				node->expected_result[i / 2] = nibble << 4;
-
-			i++;
-		}
-
-		node++;
-		parsed_range->variant_count++;
-
-	} while (next_token);
-
-	return 0;
-}
-
-int parser_get_next_range(struct addr_range **range)
-{
-	char next_line[1000]; /* Should be enough for the largest descriptor. */
-	ssize_t entry_size;
-	struct addr_range *new_range;
-	int rv;
-
-	/*
-	 * We come here after hash descriptor database file was opened and the
-	 * current board's section has been found. Just in case check if the
-	 * file has been opened.
-	 */
-	if (!hash_file_ || !range)
-		return -EIO;
-
-	*range = NULL;
-	do {
-		entry_size = get_next_line(next_line, sizeof(next_line));
-		if (entry_size < 0)
-			return entry_size;
-	} while (!entry_size); /* Skip empty lines. */
-
-	if (entry_size == 4) /* Next board's entry must have been reached. */
-		return -ENODATA;
-
-	/* This sure will be enough to fit parsed structure contents. */
-	new_range = malloc(sizeof(*new_range) + entry_size);
-	if (!new_range) {
-		fprintf(stderr, "Failed to allocate %zd bytes\n",
-			sizeof(*new_range) + entry_size);
-		return -ENOMEM;
-	}
-
-	/* This must be a new descriptor section, lets parse it. */
-	rv = parse_range(next_line, entry_size, new_range);
-
-	if (rv) {
-		free(new_range);
-		return rv;
-	}
-
-	if (new_range->variant_count) {
-		/*
-		 * A new range was found, if this is the first hash range we
-		 * encountered, save its dimensions for future reference.
-		 *
-		 * If this is not the first one - verify that it has the same
-		 * number of hash variants as all previous hash blocks.
-		 */
-		if (!variant_count) {
-			variant_count = new_range->variant_count;
-		} else if (variant_count != new_range->variant_count) {
-			fprintf(stderr,
-				"Unexpected number of variants in section %d\n",
-				section_count_);
-			free(new_range);
-			return -EINVAL;
-		}
-	}
-
-	*range = new_range;
-	return 0;
-
-}
-
-int parser_find_board(const char *hash_file_name, const char *board_id)
-{
-	char next_line[1000]; /* Should be enough for the largest descriptor. */
-	ssize_t id_len = strlen(board_id);
-
-	if (!hash_file_) {
-		hash_file_ = fopen(hash_file_name, "r");
-		if (!hash_file_) {
-			fprintf(stderr, "Error:%s can not open file '%s'\n",
-				strerror(errno), hash_file_name);
-			return errno;
-		}
-	}
-
-	while (1) {
-		ssize_t entry_size;
-
-		entry_size = get_next_line(next_line, sizeof(next_line));
-		if (entry_size < 0) {
-			return entry_size;
-		}
-
-		if ((entry_size == id_len) &&
-		    !memcmp(next_line, board_id, id_len)) {
-			variant_count = 0;
-			return 0;
-		}
-	}
-
-	return -ENODATA;
-}
-
-void parser_done(void)
-{
-	if (!hash_file_)
-		return;
-
-	fclose(hash_file_);
-	hash_file_ = NULL;
-}
-
-#ifdef TEST_PARSER
-int main(int argc, char **argv)
-{
-	const char *board_name = "QZUX";
-	char next_line[1000]; /* Should be enough for the largest descriptor. */
-	int rv;
-	int count;
-
-	if (argc < 2) {
-		fprintf(stderr, "Name of the file to parse is required.\n");
-		return -1;
-	}
-
-	if (parser_find_board(argv[1], board_name)) {
-		fprintf(stderr, "Board %s NOT found\n", board_name);
-		return -1;
-	}
-
-	count = 0;
-	do {
-		struct addr_range *range;
-
-		rv = parser_get_next_range(&range);
-		count++;
-		printf("Section %d, rv %d\n", count, rv);
-		free(range); /* Freeing NULL is OK. */
-
-	} while (rv != -ENODATA);
-
-	return 0;
-}
-#endif
diff --git a/extra/usb_updater/desc_parser.h b/extra/usb_updater/desc_parser.h
deleted file mode 100644
index faa80d1a63..0000000000
--- a/extra/usb_updater/desc_parser.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EXTRA_USB_UPDATER_DESC_PARSER_H
-#define __EXTRA_USB_UPDATER_DESC_PARSER_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-struct result_node {
-	uint8_t expected_result[32];
-};
-
-enum range_type_t {
-	NOT_A_RANGE,
-	AP_RANGE,
-	EC_RANGE,
-	EC_GANG_RANGE,
-};
-
-struct addr_range {
-	enum range_type_t range_type;
-	uint32_t base_addr;
-	uint32_t range_size;
-	size_t variant_count; /* Set to zero for dump ranges. */
-	struct result_node variants[0];
-};
-
-/* Board description retrieval API includes the following functions. */
-
-/*
- * In the given hash database file find board by its ID. Return zero on
- * success, or OS error of error. In particular ENODATA is returned if the
- * section for the required board ID is not found in the file.
- */
-int parser_find_board(const char *hash_file_name, const char board_id[4]);
-
-/*
- * Find next range for the previousely defined board, parse it into the
- * addr_range structure and return pointer to the parsed structure to the
- * caller, set pointer to NULL if no more entries are available or in case of
- * error.
- *
- * Caller of this function is responsible for returning memory allocated for
- * the entry.
- *
- * Return value set to zero on success, or to OS error if one occurs. EIO is
- * used if an attmept to get next range is made before hash database file was
- * opened and board entry in it was found.
- */
-int parser_get_next_range(struct addr_range **range);
-
-/* Close the hash database file. */
-void parser_done(void);
-
-#endif // __EXTRA_USB_UPDATER_DESC_PARSER_H
diff --git a/extra/usb_updater/ecusb b/extra/usb_updater/ecusb
deleted file mode 120000
index c06ee0f51b..0000000000
--- a/extra/usb_updater/ecusb
+++ /dev/null
@@ -1 +0,0 @@
-../tigertool/ecusb/
\ No newline at end of file
diff --git a/extra/usb_updater/fw_update.py b/extra/usb_updater/fw_update.py
deleted file mode 100755
index 0d7a570fc3..0000000000
--- a/extra/usb_updater/fw_update.py
+++ /dev/null
@@ -1,426 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# Upload firmware over USB
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import argparse
-import array
-import json
-import os
-import struct
-import sys
-import time
-from pprint import pprint
-import usb
-
-
-debug = False
-def debuglog(msg):
-  if debug:
-    print(msg)
-
-def log(msg):
-  print(msg)
-  sys.stdout.flush()
-
-
-"""Sends firmware update to CROS EC usb endpoint."""
-
-class Supdate(object):
-  """Class to access firmware update endpoints.
-
-  Usage:
-    d = Supdate()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  USB_SUBCLASS_GOOGLE_UPDATE = 0x53
-  USB_CLASS_VENDOR = 0xFF
-
-  def __init__(self):
-    pass
-
-
-  def connect_usb(self, serialname=None):
-    """Initial discovery and connection to USB endpoint.
-
-    This searches for a USB device matching the VID:PID specified
-    in the config file, optionally matching a specified serialname.
-
-    Args:
-      serialname: Find the device with this serial, in case multiple
-          devices are attached.
-
-    Returns:
-      True on success.
-    Raises:
-      Exception on error.
-    """
-    # Find the stm32.
-    vendor = self._brdcfg['vid']
-    product = self._brdcfg['pid']
-
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Update", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        if usb.util.get_string(d, d.iSerialNumber) == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        dev = dev_list.next()
-
-    debuglog("Found stm32: %04x:%04x" % (vendor, product))
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==self.USB_CLASS_VENDOR and \
-        i.bInterfaceSubClass==self.USB_SUBCLASS_GOOGLE_UPDATE)
-
-    self._intf = intf
-    debuglog("Interface: %s" % intf)
-    debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress)
-
-    return True
-
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000):
-    """Write command to logger logic..
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-      wtimeout: mS to wait for write success
-      rtimeout: mS to wait for read success
-
-    Returns:
-      status byte, if one byte is read,
-      byte list, if multiple bytes are read,
-      None, if no bytes are read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-    """
-    debuglog("wr_command(write_list=[%s] (%d), read_count=%s)" % (
-          list(bytearray(write_list)), len(write_list), read_count))
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-      debuglog("RET: %s " % ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      debuglog("BYTES: [%s]" % bytesread)
-
-      if len(bytesread) != read_count:
-        debuglog("Unexpected bytes read: %d, expected: %d" % (len(bytesread), read_count))
-        pass
-
-      debuglog("STATUS: 0x%02x" % int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
-
-    return None
-
-  def stop(self):
-    """Finalize system flash and exit."""
-    cmd = struct.pack(">I", 0xB007AB1E)
-    read = self.wr_command(cmd, read_count=4)
-
-    if len(read) == 4:
-      log("Finished flashing")
-      return
-
-    raise Exception("Update", "Stop failed [%s]" % read)
-
-
-  def write_file(self):
-    """Write the update region packet by packet to USB
-
-    This sends write packets of size 128B out, in 32B chunks.
-    Overall, this will write all data in the inactive code region.
-
-    Raises:
-      Exception if write failed or address out of bounds.
-    """
-    region = self._region
-    flash_base = self._brdcfg["flash"]
-    offset = self._base - flash_base
-    if offset != self._brdcfg['regions'][region][0]:
-      raise Exception("Update", "Region %s offset 0x%x != available offset 0x%x" % (
-          region, self._brdcfg['regions'][region][0], offset))
-
-    length = self._brdcfg['regions'][region][1]
-    log("Sending")
-
-    # Go to the correct region in the ec.bin file.
-    self._binfile.seek(offset)
-
-    # Send 32 bytes at a time. Must be less than the endpoint's max packet size.
-    maxpacket = 32
-
-    # While data is left, create update packets.
-    while length > 0:
-      # Update packets are 128B. We can use any number
-      # but the micro must malloc this memory.
-      pagesize = min(length, 128)
-
-      # Packet is:
-      #  packet size: page bytes transferred plus 3 x 32b values header.
-      #  cmd: n/a
-      #  base: flash address to write this packet.
-      #  data: 128B of data to write into flash_base
-      cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base)
-      read = self.wr_command(cmd, read_count=0)
-
-      # Push 'todo' bytes out the pipe.
-      todo = pagesize
-      while todo > 0:
-        packetsize = min(maxpacket, todo)
-        data = self._binfile.read(packetsize)
-        if len(data) != packetsize:
-          raise Exception("Update", "No more data from file")
-        for i in range(0, 10):
-          try:
-            self.wr_command(data, read_count=0)
-            break
-          except:
-            log("Timeout fail")
-        todo -= packetsize
-      # Done with this packet, move to the next one.
-      length -= pagesize
-      offset += pagesize
-
-      # Validate that the micro thinks it successfully wrote the data.
-      read = self.wr_command(''.encode(), read_count=4)
-      result = struct.unpack("<I", read)
-      result = result[0]
-      if result != 0:
-        raise Exception("Update", "Upload failed with rc: 0x%x" % result)
-
-
-  def start(self):
-    """Start a transaction and erase currently inactive region.
-
-    This function sends a start command, and receives the base of the
-    preferred inactive region. This could be RW, RW_B,
-    or RO (if there's no RW_B)
-
-    Note that the region is erased here, so you'd better program the RO if
-    you just erased it. TODO(nsanders): Modify the protocol to allow active
-    region select or query before erase.
-    """
-
-    # Size is 3 uint32 fields
-    # packet: [packetsize, cmd, base]
-    size = 4 + 4 + 4
-    # Return value is [status, base_addr]
-    expected = 4 + 4
-
-    cmd = struct.pack("<III", size, 0, 0)
-    read = self.wr_command(cmd, read_count=expected)
-
-    if len(read) == 4:
-      raise Exception("Update", "Protocol version 0 not supported")
-    elif len(read) == expected:
-      base, version = struct.unpack(">II", read)
-      log("Update protocol v. %d" % version)
-      log("Available flash region base: %x" % base)
-    else:
-      raise Exception("Update", "Start command returned %d bytes" % len(read))
-
-    if base < 256:
-      raise Exception("Update", "Start returned error code 0x%x" % base)
-
-    self._base = base
-    flash_base = self._brdcfg["flash"]
-    self._offset = self._base - flash_base
-
-    # Find our active region.
-    for region in self._brdcfg['regions']:
-      if (self._offset >= self._brdcfg['regions'][region][0]) and \
-         (self._offset < (self._brdcfg['regions'][region][0] + \
-          self._brdcfg['regions'][region][1])):
-        log("Active region: %s" % region)
-        self._region = region
-
-
-  def load_board(self, brdfile):
-    """Load firmware layout file.
-
-    example as follows:
-    {
-      "board": "servo micro",
-      "vid": 6353,
-      "pid": 20506,
-      "flash": 134217728,
-      "regions": {
-        "RW": [65536, 65536],
-        "PSTATE": [61440, 4096],
-        "RO": [0, 61440]
-      }
-    }
-
-    Args:
-      brdfile: path to board description file.
-    """
-    with open(brdfile) as data_file:
-        data = json.load(data_file)
-
-    # TODO(nsanders): validate this data before moving on.
-    self._brdcfg = data;
-    if debug:
-      pprint(data)
-
-    log("Board is %s" % self._brdcfg['board'])
-    # Cast hex strings to int.
-    self._brdcfg['flash'] = int(self._brdcfg['flash'], 0)
-    self._brdcfg['vid'] = int(self._brdcfg['vid'], 0)
-    self._brdcfg['pid'] = int(self._brdcfg['pid'], 0)
-
-    log("Flash Base is %x" % self._brdcfg['flash'])
-    self._flashsize = 0
-    for region in self._brdcfg['regions']:
-      base = int(self._brdcfg['regions'][region][0], 0)
-      length = int(self._brdcfg['regions'][region][1], 0)
-      log("region %s\tbase:0x%08x size:0x%08x" % (
-          region, base, length))
-      self._flashsize += length
-
-      # Convert these to int because json doesn't support hex.
-      self._brdcfg['regions'][region][0] = base
-      self._brdcfg['regions'][region][1] = length
-
-    log("Flash Size: 0x%x" % self._flashsize)
-
-  def load_file(self, binfile):
-    """Open and verify size of the target ec.bin file.
-
-    Args:
-      binfile: path to ec.bin
-
-    Raises:
-      Exception on file not found or filesize not matching.
-    """
-    self._filesize = os.path.getsize(binfile)
-    self._binfile = open(binfile, 'rb')
-
-    if self._filesize != self._flashsize:
-      raise Exception("Update", "Flash size 0x%x != file size 0x%x" % (self._flashsize, self._filesize))
-
-
-
-# Generate command line arguments
-parser = argparse.ArgumentParser(description="Update firmware over usb")
-parser.add_argument('-b', '--board', type=str, help="Board configuration json file", default="board.json")
-parser.add_argument('-f', '--file', type=str, help="Complete ec.bin file", default="ec.bin")
-parser.add_argument('-s', '--serial', type=str, help="Serial number", default="")
-parser.add_argument('-l', '--list', action="store_true", help="List regions")
-parser.add_argument('-v', '--verbose', action="store_true", help="Chatty output")
-
-def main():
-  global debug
-  args = parser.parse_args()
-
-
-  brdfile = args.board
-  serial = args.serial
-  binfile = args.file
-  if args.verbose:
-    debug = True
-
-  with open(brdfile) as data_file:
-    names = json.load(data_file)
-
-  p = Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serial)
-  p.load_file(binfile)
-
-  # List solely prints the config.
-  if (args.list):
-    return
-
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  log("Uploading %s" % binfile)
-  p.write_file()
-
-  # Finalize
-  log("Done. Finalizing.")
-  p.stop()
-
-if __name__ == "__main__":
-  main()
-
-
diff --git a/extra/usb_updater/sample_descriptor b/extra/usb_updater/sample_descriptor
deleted file mode 100644
index 1566e9e2e1..0000000000
--- a/extra/usb_updater/sample_descriptor
+++ /dev/null
@@ -1,87 +0,0 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Hash descriptor database file consists of sections for various Chrome OS
-# boards. Each board description section starts with a line of 4 characters
-# which is the board ID (the same as the board's RLZ code).
-#
-# Each board description section includes variable number of range
-# descriptor entries, each entry consisting of semicolon separated fields:
-#
-# {a|e|g}:{h|d}:base_addr:size[:value[:value[:value...]]]]
-#
-# Where
-#
-#  - the first sindgle character field defines the way the range is accessed:
-#     a - AP flash
-#     e - EC flash
-#     g - EC flash requiring gang programming mode
-#  - the second single character field defines the range type
-#     h - Cr50 returns the hash of the range
-#     d - Cr50 returns actual contents of the range (hex dump)
-#   - the third and and forth fields are base address and size of the range
-#   - ranges of type 'h' include one or more values for the hash of the range.
-#
-# Descriptor entries can be split along multiple lines. Each entry is
-# terminated by an empty line. Board description section is completed when
-# another board ID or end of file is encountered.
-#
-# All values are expressed in hex. Repeating empty lines and lines starting
-# with '#' are ignored.
-#
-
-QZUX
-
-# 1: Valid hash section.
-a:h:0:10000:
-756c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3503:
-336c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3503:
-446c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3503
-
-# 2: Valid dump section.
-a:d:10:10
-
-# 3: Valid hash section.
-e:h:0:100:
-55d262badc1116520a7ae1d3fda380c0382b4b87f0db10de6495053ba3aadb87:
-444442badc1116520a7ae1d3fda380c0382b4b87f0db10de6495053ba3aadb87:
-443322badc1116520a7ae1d3fda380c0382b4b87f0db10de6495053ba3aadb87
-
-# 4: Invalid dump section (includes hash)
-a:d:20:10:55d262badc1116520a7ae1d3fda380c0382b4b87f0db10de6495053ba3aadb87
-
-# 5: Invalid hash section (does not include hash)
-e:h:0:100:
-
-# 6: Another invalid hash section (does not include hash)
-e:h:0:100:
-
-# extra empty lines
-
-
-# 7: Invalid hash section (hash too short)
-e:h:0:100:
-55d262badc1116520a7ae1d3fda380c0382b4b87f0db10de6495053ba3aadb8
-
-# 8: Invalid hash section (hash too long)
-a:h:0:10000:
-756c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf35034:
-336c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3503
-
-# 9: Invalid hash section (hash includes non-hex value)
-a:h:0:10000:
-756c41b90ac9aa23a6c98ce13549dccd7xe0a83f8537eb834d9cfc3d12bf3503:
-336c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3505
-
-# 10: Invalid hash section (hash does not include 3 variants)
-a:h:0:10000:
-756c41b90ac9aa23a6c98ce13549dccd75e0a83f8537eb834d9cfc3d12bf3503:
-336c41b90ac9aa23a6c98ce13549dccd72e0a83f8537eb834d9cfc3d12bf3505
-
-# 11: Invalid dump section (size includes non hex character)
-a:d:10:10x
-
-ABCD
-
-a:d:10:10
diff --git a/extra/usb_updater/servo_micro.json b/extra/usb_updater/servo_micro.json
deleted file mode 100644
index 71b1fd25dc..0000000000
--- a/extra/usb_updater/servo_micro.json
+++ /dev/null
@@ -1,15 +0,0 @@
-{
-  "Comment": "This file describes the updateable sections of the flash.",
-  "board": "servo_micro",
-  "vid": "0x18d1",
-  "pid": "0x501a",
-  "console": "3",
-  "Comment on flash": "This is the base address of writeable flash",
-  "flash": "0x8000000",
-  "Comment on region format": "name: [baseoffset, length]",
-  "regions": {
-    "RW": ["0x10000", "0x10000"],
-    "PSTATE": ["0xf000", "0x1000"],
-    "RO": ["0x0000", "0xf000"]
-  }
-}
diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py
deleted file mode 100755
index 4dff264182..0000000000
--- a/extra/usb_updater/servo_updater.py
+++ /dev/null
@@ -1,456 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import argparse
-import errno
-import os
-import re
-import subprocess
-import time
-import tempfile
-
-import json
-
-import fw_update
-import ecusb.tiny_servo_common as c
-from ecusb import tiny_servod
-
-class ServoUpdaterException(Exception):
-  """Raised on exceptions generated by servo_updater."""
-
-BOARD_C2D2 = 'c2d2'
-BOARD_SERVO_MICRO = 'servo_micro'
-BOARD_SERVO_V4 = 'servo_v4'
-BOARD_SERVO_V4P1 = 'servo_v4p1'
-BOARD_SWEETBERRY = 'sweetberry'
-
-DEFAULT_BOARD = BOARD_SERVO_V4
-
-# These lists are to facilitate exposing choices in the command-line tool
-# below.
-BOARDS = [BOARD_C2D2, BOARD_SERVO_MICRO, BOARD_SERVO_V4, BOARD_SERVO_V4P1,
-          BOARD_SWEETBERRY]
-
-# Servo firmware bundles four channels of firmware. We need to make sure the
-# user does not request a non-existing channel, so keep the lists around to
-# guard on command-line usage.
-
-DEFAULT_CHANNEL = STABLE_CHANNEL = 'stable'
-
-PREV_CHANNEL = 'prev'
-
-# The ordering here matters. From left to right it's the channel that the user
-# is most likely to be running. This is used to inform and warn the user if
-# there are issues. e.g. if the all channels are the same, we want to let the
-# user know they are running the 'stable' version before letting them know they
-# are running 'dev' or even 'alpah' which (while true) might cause confusion.
-
-CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, 'dev', 'alpha']
-
-DEFAULT_BASE_PATH = '/usr/'
-TEST_IMAGE_BASE_PATH = '/usr/local/'
-
-COMMON_PATH = 'share/servo_updater'
-
-FIRMWARE_DIR = "firmware/"
-CONFIGS_DIR = "configs/"
-
-RETRIES_COUNT = 10
-RETRIES_DELAY = 1
-
-def do_with_retries(func, *args):
-  """
-  Call function passed as argument and check if no error happened.
-  If exception was raised by function,
-  it will be retried up to RETRIES_COUNT times.
-
-  Args:
-    func: function that will be called
-    args: arguments passed to 'func'
-
-  Returns:
-    If call to function was successful, its result will be returned.
-    If retries count was exceeded, exception will be raised.
-  """
-
-  retry = 0
-  while retry < RETRIES_COUNT:
-    try:
-      return func(*args)
-    except Exception as e:
-      print("Retrying function %s: %s" % (func.__name__, e))
-      retry = retry + 1
-      time.sleep(RETRIES_DELAY)
-      continue
-
-  raise Exception("'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT))
-
-def flash(brdfile, serialno, binfile):
-  """
-  Call fw_update to upload to updater USB endpoint.
-
-  Args:
-    brdfile:  path to board configuration file
-    serialno: device serial number
-    binfile:  firmware file
-  """
-
-  p = fw_update.Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serialno)
-  p.load_file(binfile)
-
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  print("Uploading %s" % binfile)
-  p.write_file()
-
-  # Finalize
-  print("Done. Finalizing.")
-  p.stop()
-
-def flash2(vidpid, serialno, binfile):
-  """
-  Call fw update via usb_updater2 commandline.
-
-  Args:
-    vidpid:   vendor id and product id of device
-    serialno: device serial number (optional)
-    binfile:  firmware file
-  """
-
-  tool = 'usb_updater2'
-  cmd = "%s -d %s" % (tool, vidpid)
-  if serialno:
-    cmd += " -S %s" % serialno
-  cmd += " -n"
-  cmd += " %s" % binfile
-
-  print(cmd)
-  help_cmd = '%s --help' % tool
-  with open('/dev/null') as devnull:
-    valid_check = subprocess.call(help_cmd.split(), stdout=devnull,
-                                  stderr=devnull)
-  if valid_check:
-    raise ServoUpdaterException('%s exit with res = %d. Make sure the tool '
-                                'is available on the device.' % (help_cmd,
-                                                                 valid_check))
-  res = subprocess.call(cmd.split())
-
-  if res in (0, 1, 2):
-    return res
-  else:
-    raise ServoUpdaterException("%s exit with res = %d" % (cmd, res))
-
-def select(tinys, region):
-  """
-  Ensure the servo is in the expected ro/rw region.
-  This function jumps to the required region and verify if jump was
-  successful by executing 'sysinfo' command and reading current region.
-  If response was not received or region is invalid, exception is raised.
-
-  Args:
-    tinys:  TinyServod object
-    region: region to jump to, only "rw" and "ro" is allowed
-  """
-
-  if region not in ["rw", "ro"]:
-    raise Exception("Region must be ro or rw")
-
-  if region is "ro":
-    cmd = "reboot"
-  else:
-    cmd = "sysjump %s" % region
-
-  tinys.pty._issue_cmd(cmd)
-
-  tinys.close()
-  time.sleep(2)
-  tinys.reinitialize()
-
-  res = tinys.pty._issue_cmd_get_results("sysinfo", ["Copy:[\s]+(RO|RW)"])
-  current_region = res[0][1].lower()
-  if current_region != region:
-    raise Exception("Invalid region: %s/%s" % (current_region, region))
-
-def do_version(tinys):
-  """Check version via ec console 'pty'.
-
-  Args:
-    tinys: TinyServod object
-
-  Returns:
-    detected version number
-
-  Commands are:
-  # > version
-  # ...
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  """
-  cmd = '\r\nversion\r\n'
-  regex = 'Build:\s+(\S+)[\r\n]+'
-
-  results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0]
-
-  return results[1].strip(' \t\r\n\0')
-
-def do_updater_version(tinys):
-  """Check whether this uses python updater or c++ updater
-
-  Args:
-    tinys: TinyServod object
-
-  Returns:
-    updater version number. 2 or 6.
-  """
-  vers = do_version(tinys)
-
-  # Servo versions below 58 are from servo-9040.B. Versions starting with _v2
-  # are newer than anything _v1, no need to check the exact number. Updater
-  # version is not directly queryable.
-  if re.search('_v[2-9]\.\d', vers):
-    return 6
-  m = re.search('_v1\.1\.(\d\d\d\d)', vers)
-  if m:
-    version_number = int(m.group(1))
-    if version_number < 5800:
-      return 2
-    else:
-      return 6
-  raise ServoUpdaterException(
-      "Can't determine updater target from vers: [%s]" % vers)
-
-def _extract_version(boardname, binfile):
-  """Find the version string from |binfile|.
-
-  Args:
-    boardname: the name of the board, eg. "servo_micro"
-    binfile: path to the binary to search
-
-  Returns:
-    the version string.
-  """
-  if boardname is None:
-    # cannot extract the version if the name is None
-    return None
-  rawstrings = subprocess.check_output(
-      ['cbfstool', binfile, 'read', '-r', 'RO_FRID', '-f', '/dev/stdout'],
-      **c.get_subprocess_args())
-  m = re.match(r'%s_v\S+' % boardname, rawstrings)
-  if m:
-    newvers = m.group(0).strip(' \t\r\n\0')
-  else:
-    raise ServoUpdaterException("Can't find version from file: %s." % binfile)
-
-  return newvers
-
-def get_firmware_channel(bname, version):
-  """Find out which channel |version| for |bname| came from.
-
-  Args:
-    bname: board name
-    version: current version string
-
-  Returns:
-    one of the channel names if |version| came from one of those, or None
-  """
-  for channel in CHANNELS:
-    # Pass |bname| as cname to find the board specific file, and pass None as
-    # fname to ensure the default directory is searched
-    _, _, vers = get_files_and_version(bname, None, channel=channel)
-    if version == vers:
-      return channel
-  # None of the channels matched. This firmware is currently unknown.
-  return None
-
-def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL):
-  """Select config and firmware binary files.
-
-  This checks default file names and paths.
-  In: /usr/share/servo_updater/[firmware|configs]
-  check for board.json, board.bin
-
-  Args:
-    cname: board name, or config name. eg. "servo_v4" or "servo_v4.json"
-    fname: firmware binary name. Can be None to try default.
-    channel: the channel requested for servo firmware. See |CHANNELS| above.
-
-  Returns:
-    cname, fname, version: validated filenames selected from the path.
-  """
-  for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH):
-    updater_path = os.path.join(p, COMMON_PATH)
-    if os.path.exists(updater_path):
-      break
-  else:
-    raise ServoUpdaterException('servo_updater/ dir not found in known spots.')
-
-  firmware_path = os.path.join(updater_path, FIRMWARE_DIR)
-  configs_path = os.path.join(updater_path, CONFIGS_DIR)
-
-  for p in (firmware_path, configs_path):
-    if not os.path.exists(p):
-      raise ServoUpdaterException('Could not find required path %r' % p)
-
-  if not os.path.isfile(cname):
-    # If not an existing file, try checking on the default path.
-    newname = os.path.join(configs_path, cname)
-    if os.path.isfile(newname):
-      cname = newname
-    else:
-      # Try appending ".json" to convert board name to config file.
-      cname = newname + ".json"
-    if not os.path.isfile(cname):
-      raise ServoUpdaterException("Can't find config file: %s." % cname)
-
-  # Always retrieve the boardname
-  with open(cname) as data_file:
-    data = json.load(data_file)
-  boardname = data['board']
-
-  if not fname:
-    # If no |fname| supplied, look for the default locations with the board
-    # and channel requested.
-    binary_file = '%s.%s.bin' % (boardname, channel)
-    newname = os.path.join(firmware_path, binary_file)
-    if os.path.isfile(newname):
-      fname = newname
-    else:
-      raise ServoUpdaterException("Can't find firmware binary: %s." %
-                                  binary_file)
-  elif not os.path.isfile(fname):
-    # If a name is specified but not found, try the default path.
-    newname = os.path.join(firmware_path, fname)
-    if os.path.isfile(newname):
-      fname = newname
-    else:
-      raise ServoUpdaterException("Can't find file: %s." % fname)
-
-  # Lastly, retrieve the version as well for decision making, debug, and
-  # informational purposes.
-  binvers = _extract_version(boardname, fname)
-
-  return cname, fname, binvers
-
-def main():
-  parser = argparse.ArgumentParser(description="Image a servo device")
-  parser.add_argument('-p', '--print', dest='print_only', action='store_true',
-                      default=False,
-                      help='only print available firmware for board/channel')
-  parser.add_argument('-s', '--serialno', type=str,
-                      help="serial number to program", default=None)
-  parser.add_argument('-b', '--board', type=str,
-                      help="Board configuration json file",
-                      default=DEFAULT_BOARD, choices=BOARDS)
-  parser.add_argument('-c', '--channel', type=str,
-                      help="Firmware channel to use",
-                      default=DEFAULT_CHANNEL, choices=CHANNELS)
-  parser.add_argument('-f', '--file', type=str,
-                      help="Complete ec.bin file", default=None)
-  parser.add_argument('--force', action="store_true",
-                      help="Update even if version match", default=False)
-  parser.add_argument('-v', '--verbose', action="store_true",
-                      help="Chatty output")
-  parser.add_argument('-r', '--reboot', action="store_true",
-                      help="Always reboot, even after probe.")
-
-  args = parser.parse_args()
-
-  brdfile, binfile, newvers = get_files_and_version(args.board, args.file,
-                                                    args.channel)
-
-  # If the user only cares about the information then just print it here,
-  # and exit.
-  if args.print_only:
-    output = ('board: %s\n'
-              'channel: %s\n'
-              'firmware: %s') % (args.board, args.channel, newvers)
-    print(output)
-    return
-
-  serialno = args.serialno
-
-  with open(brdfile) as data_file:
-      data = json.load(data_file)
-  vid, pid = int(data['vid'], 0), int(data['pid'], 0)
-  vidpid = "%04x:%04x" % (vid, pid)
-  iface = int(data['console'], 0)
-  boardname = data['board']
-
-  # Make sure device is up.
-  print("===== Waiting for USB device =====")
-  c.wait_for_usb(vidpid, serialname=serialno)
-  # We need a tiny_servod to query some information. Set it up first.
-  tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose)
-
-  if not args.force:
-    vers = do_version(tinys)
-    print("Current %s version is   %s" % (boardname, vers))
-    print("Available %s version is %s" % (boardname, newvers))
-
-    if newvers == vers:
-      print("No version update needed")
-      if args.reboot:
-        select(tinys, 'ro')
-      return
-    else:
-      print("Updating to recommended version.")
-
-  # Make sure the servo MCU is in RO
-  print("===== Jumping to RO =====")
-  do_with_retries(select, tinys, 'ro')
-
-  print("===== Flashing RW =====")
-  vers = do_with_retries(do_updater_version, tinys)
-  # To make sure that the tiny_servod here does not interfere with other
-  # processes, close it out.
-  tinys.close()
-
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    flash2(vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
-
-  # Make sure device is up.
-  c.wait_for_usb(vidpid, serialname=serialno)
-  # After we have made sure that it's back/available, reconnect the tiny servod.
-  tinys.reinitialize()
-
-  # Make sure the servo MCU is in RW
-  print("===== Jumping to RW =====")
-  do_with_retries(select, tinys, 'rw')
-
-  print("===== Flashing RO =====")
-  vers = do_with_retries(do_updater_version, tinys)
-
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    flash2(vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
-
-  # Make sure the servo MCU is in RO
-  print("===== Rebooting =====")
-  do_with_retries(select, tinys, 'ro')
-  # Perform additional reboot to free USB/UART resources, taken by tiny servod.
-  # See https://issuetracker.google.com/196021317 for background.
-  tinys.pty._issue_cmd("reboot")
-
-  print("===== Finished =====")
-
-if __name__ == "__main__":
-  main()
diff --git a/extra/usb_updater/servo_v4.json b/extra/usb_updater/servo_v4.json
deleted file mode 100644
index e041f56b68..0000000000
--- a/extra/usb_updater/servo_v4.json
+++ /dev/null
@@ -1,15 +0,0 @@
-{
-  "Comment": "This file describes the updateable sections of the flash.",
-  "board": "servo_v4",
-  "vid": "0x18d1",
-  "pid": "0x501b",
-  "console": "0",
-  "Comment on flash": "This is the base address of writeable flash",
-  "flash": "0x8000000",
-  "Comment on region format": "name: [baseoffset, length]",
-  "regions": {
-    "RW": ["0x10000", "0x10000"],
-    "PSTATE": ["0xf000", "0x1000"],
-    "RO": ["0x0000", "0xf000"]
-  }
-}
diff --git a/extra/usb_updater/servo_v4p1.json b/extra/usb_updater/servo_v4p1.json
deleted file mode 100644
index 46efbf24ad..0000000000
--- a/extra/usb_updater/servo_v4p1.json
+++ /dev/null
@@ -1,15 +0,0 @@
-{
-  "Comment": "This file describes the updateable sections of the flash.",
-  "board": "servo_v4p1",
-  "vid": "0x18d1",
-  "pid": "0x520d",
-  "console": "0",
-  "Comment on flash": "This is the base address of writeable flash",
-  "flash": "0x8000000",
-  "Comment on region format": "name: [baseoffset, length]",
-  "regions": {
-    "RW": ["0x10000", "0x10000"],
-    "PSTATE": ["0xf000", "0x1000"],
-    "RO": ["0x0000", "0xf000"]
-  }
-}
diff --git a/extra/usb_updater/sweetberry.json b/extra/usb_updater/sweetberry.json
deleted file mode 100644
index 6b70d19fad..0000000000
--- a/extra/usb_updater/sweetberry.json
+++ /dev/null
@@ -1,14 +0,0 @@
-{
-  "Comment": "This file describes the updateable sections of the flash.",
-  "board": "sweetberry",
-  "vid": "0x18d1",
-  "pid": "0x5020",
-  "console": "0",
-  "Comment on flash": "This is the base address of writeable flash",
-  "flash": "0x8000000",
-  "Comment on region format": "name: [baseoffset, length]",
-  "regions": {
-    "RW": ["0x40000", "0x40000"],
-    "RO": ["0x0000", "0x40000"]
-  }
-}
diff --git a/extra/usb_updater/usb_updater2.c b/extra/usb_updater/usb_updater2.c
deleted file mode 100644
index 12ee1615fc..0000000000
--- a/extra/usb_updater/usb_updater2.c
+++ /dev/null
@@ -1,1244 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <asm/byteorder.h>
-#include <endian.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include <libusb.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <time.h>
-#include <unistd.h>
-
-#include <fmap.h>
-
-#ifndef __packed
-#define __packed __attribute__((packed))
-#endif
-
-#include "compile_time_macros.h"
-#include "misc_util.h"
-#include "usb_descriptor.h"
-#include "update_fw.h"
-#include "vb21_struct.h"
-
-#ifdef DEBUG
-#define debug printf
-#else
-#define debug(fmt, args...)
-#endif
-
-/*
- * This file contains the source code of a Linux application used to update
- * EC device firmware (common code only, gsctool takes care of cr50).
- */
-
-#define VID USB_VID_GOOGLE
-#define PID 0x5022
-#define SUBCLASS USB_SUBCLASS_GOOGLE_UPDATE
-#define PROTOCOL USB_PROTOCOL_GOOGLE_UPDATE
-
-enum exit_values {
-	noop = 0,	  /* All up to date, no update needed. */
-	all_updated = 1,  /* Update completed, reboot required. */
-	rw_updated  = 2,  /* RO was not updated, reboot required. */
-	update_error = 3  /* Something went wrong. */
-};
-
-struct usb_endpoint {
-	struct libusb_device_handle *devh;
-	uint8_t ep_num;
-	int     chunk_len;
-};
-
-struct transfer_descriptor {
-	/*
-	 * offsets of section available for update (not currently active).
-	 */
-	uint32_t offset;
-
-	struct usb_endpoint uep;
-};
-
-/* Information about the target */
-static struct first_response_pdu targ;
-
-static uint16_t protocol_version;
-static uint16_t header_type;
-static char *progname;
-static char *short_opts = "bd:efg:hjlnp:rsS:tuw";
-static const struct option long_opts[] = {
-	/* name    hasarg *flag val */
-	{"binvers",	1,   NULL, 'b'},
-	{"device",	1,   NULL, 'd'},
-	{"entropy",	0,   NULL, 'e'},
-	{"fwver",	0,   NULL, 'f'},
-	{"tp_debug",	1,   NULL, 'g'},
-	{"help",	0,   NULL, 'h'},
-	{"jump_to_rw",	0,   NULL, 'j'},
-	{"follow_log",	0,   NULL, 'l'},
-	{"no_reset",	0,   NULL, 'n'},
-	{"tp_update",	1,   NULL, 'p'},
-	{"reboot",	0,   NULL, 'r'},
-	{"stay_in_ro",	0,   NULL, 's'},
-	{"serial",	1,   NULL, 'S'},
-	{"tp_info",	0,   NULL, 't'},
-	{"unlock_rollback",	0,   NULL, 'u'},
-	{"unlock_rw",	0,   NULL, 'w'},
-	{},
-};
-
-/* Release USB device and return error to the OS. */
-static void shut_down(struct usb_endpoint *uep)
-{
-	libusb_close(uep->devh);
-	libusb_exit(NULL);
-	exit(update_error);
-}
-
-static void usage(int errs)
-{
-	printf("\nUsage: %s [options] <binary image>\n"
-	       "\n"
-	       "This updates EC firmware over USB (common code EC, no cr50).\n"
-	       "The required argument is the full RO+RW image.\n"
-	       "\n"
-	       "Options:\n"
-	       "\n"
-	       "  -b,--binvers             Report versions of image's "
-				"RW and RO, do not update\n"
-	       "  -d,--device  VID:PID     USB device (default %04x:%04x)\n"
-	       "  -e,--entropy             Add entropy to device secret\n"
-	       "  -f,--fwver               Report running firmware versions.\n"
-	       "  -g,--tp_debug <hex data> Touchpad debug command\n"
-	       "  -h,--help                Show this message\n"
-	       "  -j,--jump_to_rw          Tell EC to jump to RW\n"
-	       "  -l,--follow_log          Get console log\n"
-	       "  -p,--tp_update file      Update touchpad FW\n"
-	       "  -r,--reboot              Tell EC to reboot\n"
-	       "  -s,--stay_in_ro          Tell EC to stay in RO\n"
-	       "  -S,--serial              Device serial number\n"
-	       "  -t,--tp_info             Get touchpad information\n"
-	       "  -u,--unlock_rollback     Tell EC to unlock the rollback region\n"
-	       "  -w,--unlock_rw           Tell EC to unlock the RW region\n"
-	       "\n", progname, VID, PID);
-
-	exit(errs ? update_error : noop);
-}
-
-static void str2hex(const char *str, uint8_t *data, int *len)
-{
-	int i;
-	int slen = strlen(str);
-
-	if (slen/2 > *len) {
-		fprintf(stderr, "Hex string too long.\n");
-		exit(update_error);
-	}
-
-	if (slen % 2 != 0) {
-		fprintf(stderr, "Hex string length not a multiple of 2.\n");
-		exit(update_error);
-	}
-
-	for (i = 0, *len = 0; i < slen; i += 2, (*len)++) {
-		char *end;
-		char tmp[3];
-
-		tmp[0] = str[i];
-		tmp[1] = str[i+1];
-		tmp[2] = 0;
-
-		data[*len] = strtol(tmp, &end, 16);
-
-		if (*end != 0) {
-			fprintf(stderr, "Invalid hex string.\n");
-			exit(update_error);
-		}
-	}
-}
-
-static void hexdump(const uint8_t *data, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		printf("%02x", data[i]);
-		if ((i % 16) == 15)
-			printf("\n");
-	}
-
-	if ((len % 16) != 0)
-		printf("\n");
-}
-
-static void dump_touchpad_info(const uint8_t *data, int len)
-{
-	const struct touchpad_info *info = (const struct touchpad_info *)data;
-
-	if (len != sizeof(struct touchpad_info)) {
-		fprintf(stderr, "Hex string length is not %zu",
-			sizeof(struct touchpad_info));
-		hexdump(data, len);
-		return;
-	}
-
-	printf("\n");
-	printf("status:         0x%02x\n", info->status);
-	printf("vendor:         0x%04x\n", info->vendor);
-	printf("fw_address:     0x%08x\n", info->fw_address);
-	printf("fw_size:        0x%08x\n", info->fw_size);
-
-	printf("allowed_fw_hash:\n");
-	hexdump(info->allowed_fw_hash, sizeof(info->allowed_fw_hash));
-
-	switch (info->vendor) {
-	case 0x04f3: /* ELAN */
-	case 0x0483: /* ST */
-		printf("id:             0x%04x\n", info->elan.id);
-		printf("fw_version:     0x%04x\n", info->elan.fw_version);
-		printf("fw_fw_checksum: 0x%04x\n", info->elan.fw_checksum);
-		break;
-	default:
-		fprintf(stderr, "Unknown vendor, vendor specific data:\n");
-		hexdump((const uint8_t *)&info->elan, sizeof(info->elan));
-		break;
-	}
-}
-
-/* Read file into buffer */
-static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr)
-{
-	FILE *fp;
-	struct stat st;
-	uint8_t *data;
-	size_t len;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		perror(filename);
-		exit(update_error);
-	}
-	if (fstat(fileno(fp), &st)) {
-		perror("stat");
-		exit(update_error);
-	}
-
-	len = st.st_size;
-
-	data = malloc(len);
-	if (!data) {
-		perror("malloc");
-		exit(update_error);
-	}
-
-	if (fread(data, st.st_size, 1, fp) != 1) {
-		perror("fread");
-		exit(update_error);
-	}
-
-	fclose(fp);
-
-	*len_ptr = len;
-	return data;
-}
-
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
-
-/*
- * Actual USB transfer function, the 'allow_less' flag indicates that the
- * valid response could be shortef than allotted memory, the 'rxed_count'
- * pointer, if provided along with 'allow_less' lets the caller know how mavy
- * bytes were received.
- */
-static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
-		    void *inbuf, int inlen, int allow_less,
-		    size_t *rxed_count)
-{
-
-	int r, actual;
-
-	/* Send data out */
-	if (outbuf && outlen) {
-		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
-					 &actual, 2000);
-		if (r < 0) {
-			USB_ERROR("libusb_bulk_transfer", r);
-			exit(update_error);
-		}
-		if (actual != outlen) {
-			fprintf(stderr, "%s:%d, only sent %d/%d bytes\n",
-				__FILE__, __LINE__, actual, outlen);
-			shut_down(uep);
-		}
-	}
-
-	/* Read reply back */
-	if (inbuf && inlen) {
-
-		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 5000);
-		if (r < 0) {
-			USB_ERROR("libusb_bulk_transfer", r);
-			exit(update_error);
-		}
-		if ((actual != inlen) && !allow_less) {
-			fprintf(stderr, "%s:%d, only received %d/%d bytes\n",
-				__FILE__, __LINE__, actual, inlen);
-			hexdump(inbuf, actual);
-			shut_down(uep);
-		}
-
-		if (rxed_count)
-			*rxed_count = actual;
-	}
-}
-
-static void xfer(struct usb_endpoint *uep, void *outbuf,
-		 size_t outlen, void *inbuf, size_t inlen, int allow_less)
-{
-	do_xfer(uep, outbuf, outlen, inbuf, inlen, allow_less, NULL);
-}
-
-/* Return 0 on error, since it's never gonna be EP 0 */
-static int find_endpoint(const struct libusb_interface_descriptor *iface,
-			 struct usb_endpoint *uep)
-{
-	const struct libusb_endpoint_descriptor *ep;
-
-	if (iface->bInterfaceClass == 255 &&
-	    iface->bInterfaceSubClass == SUBCLASS &&
-	    iface->bInterfaceProtocol == PROTOCOL &&
-	    iface->bNumEndpoints) {
-		ep = &iface->endpoint[0];
-		uep->ep_num = ep->bEndpointAddress & 0x7f;
-		uep->chunk_len = ep->wMaxPacketSize;
-		return 1;
-	}
-
-	return 0;
-}
-
-/* Return -1 on error */
-static int find_interface(struct usb_endpoint *uep)
-{
-	int iface_num = -1;
-	int r, i, j;
-	struct libusb_device *dev;
-	struct libusb_config_descriptor *conf = 0;
-	const struct libusb_interface *iface0;
-	const struct libusb_interface_descriptor *iface;
-
-	dev = libusb_get_device(uep->devh);
-	r = libusb_get_active_config_descriptor(dev, &conf);
-	if (r < 0) {
-		USB_ERROR("libusb_get_active_config_descriptor", r);
-		goto out;
-	}
-
-	for (i = 0; i < conf->bNumInterfaces; i++) {
-		iface0 = &conf->interface[i];
-		for (j = 0; j < iface0->num_altsetting; j++) {
-			iface = &iface0->altsetting[j];
-			if (find_endpoint(iface, uep)) {
-				iface_num = i;
-				goto out;
-			}
-		}
-	}
-
-out:
-	libusb_free_config_descriptor(conf);
-	return iface_num;
-}
-
-/* Returns true if parsed. */
-static int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr)
-{
-	char *copy, *s, *e = 0;
-
-	copy = strdup(input);
-
-	s = strchr(copy, ':');
-	if (!s)
-		return 0;
-	*s++ = '\0';
-
-	*vid_ptr = (uint16_t) strtoull(copy, &e, 16);
-	if (!*optarg || (e && *e))
-		return 0;
-
-	*pid_ptr = (uint16_t) strtoull(s, &e, 16);
-	if (!*optarg || (e && *e))
-		return 0;
-
-	return 1;
-}
-
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, char *serialno)
-{
-	struct libusb_device_descriptor desc;
-	libusb_device_handle *handle = NULL;
-	char sn[256];
-	int ret;
-	int match = 1;
-	int snvalid = 0;
-
-	ret = libusb_get_device_descriptor(dev, &desc);
-	if (ret < 0)
-		return NULL;
-
-	ret = libusb_open(dev, &handle);
-
-	if (ret != LIBUSB_SUCCESS)
-		return NULL;
-
-	if (desc.iSerialNumber) {
-		ret = libusb_get_string_descriptor_ascii(handle,
-			desc.iSerialNumber, (unsigned char *)sn, sizeof(sn));
-		if (ret > 0)
-			snvalid = 1;
-	}
-
-	if (vid != 0 && vid != desc.idVendor)
-		match = 0;
-	if (pid != 0 && pid != desc.idProduct)
-		match = 0;
-	if (serialno != NULL && (!snvalid || strstr(sn, serialno) == NULL))
-		match = 0;
-
-	if (match)
-		return handle;
-
-	libusb_close(handle);
-	return NULL;
-}
-
-static void usb_findit(uint16_t vid, uint16_t pid,
-		char *serialno, struct usb_endpoint *uep)
-{
-	int iface_num, r, i;
-	libusb_device **devs;
-	libusb_device_handle *devh = NULL;
-	ssize_t count;
-
-	memset(uep, 0, sizeof(*uep));
-
-	r = libusb_init(NULL);
-	if (r < 0) {
-		USB_ERROR("libusb_init", r);
-		exit(update_error);
-	}
-
-	count = libusb_get_device_list(NULL, &devs);
-	if (count < 0)
-		return;
-
-	for (i = 0; devs[i]; i++) {
-		devh = check_device(devs[i], vid, pid, serialno);
-		if (devh) {
-			printf("Found device.\n");
-			break;
-		}
-	}
-
-	libusb_free_device_list(devs, 1);
-
-	if (!devh) {
-		fprintf(stderr, "Can't find device\n");
-		exit(update_error);
-	}
-
-	uep->devh = devh;
-
-	iface_num = find_interface(uep);
-	if (iface_num < 0) {
-		fprintf(stderr, "USB FW update not supported by that device\n");
-		shut_down(uep);
-	}
-	if (!uep->chunk_len) {
-		fprintf(stderr, "wMaxPacketSize isn't valid\n");
-		shut_down(uep);
-	}
-
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
-
-	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
-	r = libusb_claim_interface(uep->devh, iface_num);
-	if (r < 0) {
-		USB_ERROR("libusb_claim_interface", r);
-		shut_down(uep);
-	}
-
-	printf("READY\n-------\n");
-}
-
-static int transfer_block(struct usb_endpoint *uep,
-			  struct update_frame_header *ufh,
-			  uint8_t *transfer_data_ptr, size_t payload_size)
-{
-	size_t transfer_size;
-	uint32_t reply;
-	int actual;
-	int r;
-
-	/* First send the header. */
-	xfer(uep, ufh, sizeof(*ufh), NULL, 0, 0);
-
-	/* Now send the block, chunk by chunk. */
-	for (transfer_size = 0; transfer_size < payload_size;) {
-		int chunk_size;
-
-		chunk_size = MIN(uep->chunk_len, payload_size - transfer_size);
-		xfer(uep, transfer_data_ptr, chunk_size, NULL, 0, 0);
-		transfer_data_ptr += chunk_size;
-		transfer_size += chunk_size;
-	}
-
-	/* Now get the reply. */
-	r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-				 (void *) &reply, sizeof(reply),
-				 &actual, 5000);
-	if (r) {
-		if (r == -7) {
-			fprintf(stderr, "Timeout!\n");
-			return r;
-		}
-		USB_ERROR("libusb_bulk_transfer", r);
-		shut_down(uep);
-	}
-
-	reply = *((uint8_t *)&reply);
-	if (reply) {
-		fprintf(stderr, "Error: status %#x\n", reply);
-		exit(update_error);
-	}
-
-	return 0;
-}
-
-/**
- * Transfer an image section (typically RW or RO).
- *
- * td           - transfer descriptor to use to communicate with the target
- * data_ptr     - pointer at the section base in the image
- * section_addr - address of the section in the target memory space
- * data_len     - section size
- * smart_update - non-zero to enable the smart trailing of 0xff.
- */
-static void transfer_section(struct transfer_descriptor *td,
-			     uint8_t *data_ptr,
-			     uint32_t section_addr,
-			     size_t data_len,
-			     uint8_t smart_update)
-{
-	/*
-	 * Actually, we can skip trailing chunks of 0xff, as the entire
-	 * section space must be erased before the update is attempted.
-	 *
-	 * FIXME: We can be smarter than this and skip blocks within the image.
-	 */
-	if (smart_update)
-		while (data_len && (data_ptr[data_len - 1] == 0xff))
-			data_len--;
-
-	printf("sending 0x%zx bytes to %#x\n", data_len, section_addr);
-	while (data_len) {
-		size_t payload_size;
-		uint32_t block_base;
-		int max_retries;
-
-		/* prepare the header to prepend to the block. */
-		payload_size = MIN(data_len, targ.common.maximum_pdu_size);
-
-		block_base = htobe32(section_addr);
-
-		struct update_frame_header ufh;
-
-		ufh.block_size = htobe32(payload_size +
-					sizeof(struct update_frame_header));
-		ufh.cmd.block_base = block_base;
-		ufh.cmd.block_digest = 0;
-		for (max_retries = 10; max_retries; max_retries--)
-			if (!transfer_block(&td->uep, &ufh,
-						data_ptr, payload_size))
-				break;
-
-		if (!max_retries) {
-			fprintf(stderr,
-				"Failed to transfer block, %zd to go\n",
-				data_len);
-			exit(update_error);
-		}
-		data_len -= payload_size;
-		data_ptr += payload_size;
-		section_addr += payload_size;
-	}
-}
-
-/*
- * Each RO or RW section of the new image can be in one of the following
- * states.
- */
-enum upgrade_status {
-	not_needed = 0,  /* Version below or equal that on the target. */
-	not_possible,    /*
-			  * RO is newer, but can't be transferred due to
-			  * target RW shortcomings.
-			  */
-	needed            /*
-			   * This section needs to be transferred to the
-			   * target.
-			   */
-};
-
-/* This array describes all sections of the new image. */
-static struct {
-	const char *name;
-	uint32_t    offset;
-	uint32_t    size;
-	enum upgrade_status  ustatus;
-	char version[32];
-	int32_t rollback;
-	uint32_t key_version;
-} sections[] = {
-	{"RO"},
-	{"RW"}
-};
-
-static const struct fmap_area *fmap_find_area_or_die(const struct fmap *fmap,
-						     const char *name)
-{
-	const struct fmap_area *fmaparea;
-
-	fmaparea = fmap_find_area(fmap, name);
-	if (!fmaparea) {
-		fprintf(stderr, "Cannot find FMAP area %s\n", name);
-		exit(update_error);
-	}
-
-	return fmaparea;
-}
-
-/*
- * Scan the new image and retrieve versions of all sections.
- */
-static void fetch_header_versions(const uint8_t *image, size_t len)
-{
-	const struct fmap *fmap;
-	const struct fmap_area *fmaparea;
-	long int offset;
-	size_t i;
-
-	offset = fmap_find(image, len);
-	if (offset < 0) {
-		fprintf(stderr, "Cannot find FMAP in image\n");
-		exit(update_error);
-	}
-	fmap = (const struct fmap *)(image+offset);
-
-	/* FIXME: validate fmap struct more than this? */
-	if (fmap->size != len) {
-		fprintf(stderr, "Mismatch between FMAP size and image size\n");
-		exit(update_error);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(sections); i++) {
-		const char *fmap_name;
-		const char *fmap_fwid_name;
-		const char *fmap_rollback_name = NULL;
-		const char *fmap_key_name = NULL;
-
-		if (!strcmp(sections[i].name, "RO")) {
-			fmap_name = "EC_RO";
-			fmap_fwid_name = "RO_FRID";
-		} else if (!strcmp(sections[i].name, "RW")) {
-			fmap_name = "EC_RW";
-			fmap_fwid_name = "RW_FWID";
-			fmap_rollback_name = "RW_RBVER";
-			/*
-			 * Key version comes from key RO (RW signature does not
-			 * contain the key version.
-			 */
-			fmap_key_name = "KEY_RO";
-		} else {
-			fprintf(stderr, "Invalid section name\n");
-			exit(update_error);
-		}
-
-		fmaparea = fmap_find_area_or_die(fmap, fmap_name);
-
-		/* FIXME: endianness? */
-		sections[i].offset = fmaparea->offset;
-		sections[i].size = fmaparea->size;
-
-		fmaparea = fmap_find_area_or_die(fmap, fmap_fwid_name);
-
-		if (fmaparea->size != sizeof(sections[i].version)) {
-			fprintf(stderr, "Invalid fwid size\n");
-			exit(update_error);
-		}
-		memcpy(sections[i].version, image+fmaparea->offset,
-			fmaparea->size);
-
-		sections[i].rollback = -1;
-		if (fmap_rollback_name) {
-			fmaparea = fmap_find_area(fmap, fmap_rollback_name);
-			if (fmaparea)
-				memcpy(&sections[i].rollback,
-				       image+fmaparea->offset,
-				       sizeof(sections[i].rollback));
-		}
-
-		sections[i].key_version = -1;
-		if (fmap_key_name) {
-			fmaparea = fmap_find_area(fmap, fmap_key_name);
-			if (fmaparea) {
-				const struct vb21_packed_key *key =
-					(const void *)(image+fmaparea->offset);
-				sections[i].key_version = key->key_version;
-			}
-		}
-	}
-}
-
-static int show_headers_versions(const void *image)
-{
-	size_t i;
-
-	for (i = 0; i < ARRAY_SIZE(sections); i++) {
-		printf("%s off=%08x/%08x v=%.32s rb=%d kv=%d\n",
-			sections[i].name, sections[i].offset, sections[i].size,
-			sections[i].version, sections[i].rollback,
-			sections[i].key_version);
-	}
-	return 0;
-}
-
-/*
- * Pick sections to transfer based on information retrieved from the target,
- * the new image, and the protocol version the target is running.
- */
-static void pick_sections(struct transfer_descriptor *td)
-{
-	size_t i;
-
-	for (i = 0; i < ARRAY_SIZE(sections); i++) {
-		uint32_t offset = sections[i].offset;
-
-		/* Skip currently active section. */
-		if (offset != td->offset)
-			continue;
-
-		sections[i].ustatus = needed;
-	}
-}
-
-static void setup_connection(struct transfer_descriptor *td)
-{
-	size_t rxed_size;
-	size_t i;
-	uint32_t error_code;
-
-	/*
-	 * Need to be backwards compatible, communicate with targets running
-	 * different protocol versions.
-	 */
-	union {
-		struct first_response_pdu rpdu;
-		uint32_t legacy_resp;
-	} start_resp;
-
-	/* Send start request. */
-	printf("start\n");
-
-	struct update_frame_header ufh;
-	uint8_t inbuf[td->uep.chunk_len];
-	int actual = 0;
-
-	/* Flush all data from endpoint to recover in case of error. */
-	while (!libusb_bulk_transfer(td->uep.devh,
-					td->uep.ep_num | 0x80,
-					(void *)&inbuf, td->uep.chunk_len,
-					&actual, 10)) {
-		printf("flush\n");
-	}
-
-	memset(&ufh, 0, sizeof(ufh));
-	ufh.block_size = htobe32(sizeof(ufh));
-	do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp,
-		sizeof(start_resp), 1, &rxed_size);
-
-	/* We got something. Check for errors in response */
-	if (rxed_size < 8) {
-		fprintf(stderr, "Unexpected response size %zd: ", rxed_size);
-		for (i = 0; i < rxed_size; i++)
-			fprintf(stderr, " %02x", ((uint8_t *)&start_resp)[i]);
-		fprintf(stderr, "\n");
-		exit(update_error);
-	}
-
-	protocol_version = be16toh(start_resp.rpdu.protocol_version);
-	if (protocol_version < 5 || protocol_version > 6) {
-		fprintf(stderr, "Unsupported protocol version %d\n",
-			protocol_version);
-		exit(update_error);
-	}
-
-	header_type = be16toh(start_resp.rpdu.header_type);
-
-	printf("target running protocol version %d (type %d)\n",
-		protocol_version, header_type);
-	if (header_type != UPDATE_HEADER_TYPE_COMMON) {
-		fprintf(stderr, "Unsupported header type %d\n",
-			header_type);
-		exit(update_error);
-	}
-
-	error_code = be32toh(start_resp.rpdu.return_value);
-
-	if (error_code) {
-		fprintf(stderr, "Target reporting error %d\n", error_code);
-		shut_down(&td->uep);
-		exit(update_error);
-	}
-
-	td->offset = be32toh(start_resp.rpdu.common.offset);
-	memcpy(targ.common.version, start_resp.rpdu.common.version,
-		sizeof(start_resp.rpdu.common.version));
-	targ.common.maximum_pdu_size =
-		be32toh(start_resp.rpdu.common.maximum_pdu_size);
-	targ.common.flash_protection =
-		be32toh(start_resp.rpdu.common.flash_protection);
-	targ.common.min_rollback = be32toh(start_resp.rpdu.common.min_rollback);
-	targ.common.key_version = be32toh(start_resp.rpdu.common.key_version);
-
-	printf("maximum PDU size: %d\n", targ.common.maximum_pdu_size);
-	printf("Flash protection status: %04x\n", targ.common.flash_protection);
-	printf("version: %32s\n", targ.common.version);
-	printf("key_version: %d\n", targ.common.key_version);
-	printf("min_rollback: %d\n", targ.common.min_rollback);
-	printf("offset: writable at %#x\n", td->offset);
-
-	pick_sections(td);
-}
-
-/*
- * Channel TPM extension/vendor command over USB. The payload of the USB frame
- * in this case consists of the 2 byte subcommand code concatenated with the
- * command body. The caller needs to indicate if a response is expected, and
- * if it is - of what maximum size.
- */
-static int ext_cmd_over_usb(struct usb_endpoint *uep, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    void *resp, size_t *resp_size,
-			    int allow_less)
-{
-	struct update_frame_header *ufh;
-	uint16_t *frame_ptr;
-	size_t usb_msg_size;
-
-	usb_msg_size = sizeof(struct update_frame_header) +
-		sizeof(subcommand) + body_size;
-
-	ufh = malloc(usb_msg_size);
-	if (!ufh) {
-		printf("%s: failed to allocate %zd bytes\n",
-		       __func__, usb_msg_size);
-		return -1;
-	}
-
-	ufh->block_size = htobe32(usb_msg_size);
-	ufh->cmd.block_digest = 0;
-	ufh->cmd.block_base = htobe32(UPDATE_EXTRA_CMD);
-	frame_ptr = (uint16_t *)(ufh + 1);
-	*frame_ptr = htobe16(subcommand);
-
-	if (body_size)
-		memcpy(frame_ptr + 1, cmd_body, body_size);
-
-	xfer(uep, ufh, usb_msg_size, resp, resp_size ? *resp_size : 0,
-	     allow_less);
-
-	free(ufh);
-	return 0;
-}
-
-/*
- * Indicate to the target that update image transfer has been completed. Upon
- * receiveing of this message the target state machine transitions into the
- * 'rx_idle' state. The host may send an extension command to reset the target
- * after this.
- */
-static void send_done(struct usb_endpoint *uep)
-{
-	uint32_t out;
-
-	/* Send stop request, ignoring reply. */
-	out = htobe32(UPDATE_DONE);
-	xfer(uep, &out, sizeof(out), &out, 1, 0);
-}
-
-static void send_subcommand(struct transfer_descriptor *td, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    uint8_t *response, size_t response_size)
-{
-	send_done(&td->uep);
-
-	ext_cmd_over_usb(&td->uep, subcommand,
-			cmd_body, body_size,
-			response, &response_size, 0);
-	printf("sent command %x, resp %x\n", subcommand, response[0]);
-}
-
-/* Returns number of successfully transmitted image sections. */
-static int transfer_image(struct transfer_descriptor *td,
-			       uint8_t *data, size_t data_len)
-{
-	size_t i;
-	int num_txed_sections = 0;
-
-	for (i = 0; i < ARRAY_SIZE(sections); i++)
-		if (sections[i].ustatus == needed) {
-			transfer_section(td,
-					 data + sections[i].offset,
-					 sections[i].offset,
-					 sections[i].size, 1);
-			num_txed_sections++;
-		}
-
-	/*
-	 * Move USB receiver sate machine to idle state so that vendor
-	 * commands can be processed later, if any.
-	 */
-	send_done(&td->uep);
-
-	if (!num_txed_sections)
-		printf("nothing to do\n");
-	else
-		printf("-------\nupdate complete\n");
-	return num_txed_sections;
-}
-
-static void generate_reset_request(struct transfer_descriptor *td)
-{
-	size_t response_size;
-	uint8_t response;
-	uint16_t subcommand;
-	uint8_t command_body[2]; /* Max command body size. */
-	size_t command_body_size;
-
-	if (protocol_version < 6) {
-		/*
-		 * Send a second stop request, which should reboot
-		 * without replying.
-		 */
-		send_done(&td->uep);
-		/* Nothing we can do over /dev/tpm0 running versions below 6. */
-		return;
-	}
-
-	/*
-	 * If the user explicitly wants it, request post reset instead of
-	 * immediate reset. In this case next time the target reboots, the h1
-	 * will reboot as well, and will consider running the uploaded code.
-	 *
-	 * In case target RW version is 19 or above, to reset the target the
-	 * host is supposed to send the command to enable the uploaded image
-	 * disabled by default.
-	 *
-	 * Otherwise the immediate reset command would suffice.
-	 */
-	/* Most common case. */
-	command_body_size = 0;
-	response_size = 1;
-	subcommand = UPDATE_EXTRA_CMD_IMMEDIATE_RESET;
-	ext_cmd_over_usb(&td->uep, subcommand,
-			command_body, command_body_size,
-			&response, &response_size, 0);
-
-	printf("reboot not triggered\n");
-}
-
-static void get_random(uint8_t *data, int len)
-{
-	FILE *fp;
-	int i = 0;
-
-	fp = fopen("/dev/random", "rb");
-	if (!fp) {
-		perror("Can't open /dev/random");
-		exit(update_error);
-	}
-
-	while (i < len) {
-		int ret = fread(data+i, len-i, 1, fp);
-
-		if (ret < 0) {
-			perror("fread");
-			exit(update_error);
-		}
-
-		i += ret;
-	}
-
-	fclose(fp);
-}
-
-static void read_console(struct transfer_descriptor *td)
-{
-	uint8_t payload[] = { 0x1 };
-	uint8_t response[64];
-	size_t response_size = 64;
-	struct timespec sleep_duration = {  /* 100 ms */
-		.tv_sec = 0,
-		.tv_nsec = 100l * 1000l * 1000l,
-	};
-
-	send_done(&td->uep);
-
-	printf("\n");
-	while (1) {
-		response_size = 1;
-		ext_cmd_over_usb(&td->uep,
-				 UPDATE_EXTRA_CMD_CONSOLE_READ_INIT,
-				 NULL, 0,
-				 response, &response_size, 0);
-
-		while (1) {
-			response_size = 64;
-			ext_cmd_over_usb(&td->uep,
-					 UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT,
-					 payload, sizeof(payload),
-					 response, &response_size, 1);
-			if (response[0] == 0)
-				break;
-			/* make sure it's null-terminated. */
-			response[response_size - 1] = 0;
-			printf("%s", (const char *)response);
-		}
-		nanosleep(&sleep_duration, NULL);
-	}
-}
-
-int main(int argc, char *argv[])
-{
-	struct transfer_descriptor td;
-	int errorcnt;
-	uint8_t *data = 0;
-	size_t data_len = 0;
-	uint16_t vid = VID, pid = PID;
-	char *serialno = NULL;
-	int i;
-	size_t j;
-	int transferred_sections = 0;
-	int binary_vers = 0;
-	int show_fw_ver = 0;
-	int no_reset_request = 0;
-	int touchpad_update = 0;
-	int extra_command = -1;
-	uint8_t extra_command_data[50];
-	int extra_command_data_len = 0;
-	uint8_t extra_command_answer[64];
-	int extra_command_answer_len = 1;
-
-	progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	/* Usb transfer - default mode. */
-	memset(&td, 0, sizeof(td));
-
-	errorcnt = 0;
-	opterr = 0;				/* quiet, you */
-	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
-		switch (i) {
-		case 'b':
-			binary_vers = 1;
-			break;
-		case 'd':
-			if (!parse_vidpid(optarg, &vid, &pid)) {
-				printf("Invalid argument: \"%s\"\n", optarg);
-				errorcnt++;
-			}
-			break;
-		case 'e':
-			get_random(extra_command_data, 32);
-			extra_command_data_len = 32;
-			extra_command = UPDATE_EXTRA_CMD_INJECT_ENTROPY;
-			break;
-		case 'f':
-			show_fw_ver = 1;
-			break;
-		case 'g':
-			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG;
-			/* Maximum length. */
-			extra_command_data_len = 50;
-			str2hex(optarg,
-				extra_command_data, &extra_command_data_len);
-			hexdump(extra_command_data, extra_command_data_len);
-			extra_command_answer_len = 64;
-			break;
-		case 'h':
-			usage(errorcnt);
-			break;
-		case 'j':
-			extra_command = UPDATE_EXTRA_CMD_JUMP_TO_RW;
-			break;
-		case 'l':
-			extra_command = UPDATE_EXTRA_CMD_CONSOLE_READ_INIT;
-			break;
-		case 'n':
-			no_reset_request = 1;
-			break;
-		case 'p':
-			touchpad_update = 1;
-
-			data = get_file_or_die(optarg, &data_len);
-			printf("read %zd(%#zx) bytes from %s\n",
-				data_len, data_len, argv[optind - 1]);
-
-			break;
-		case 'r':
-			extra_command = UPDATE_EXTRA_CMD_IMMEDIATE_RESET;
-			break;
-		case 's':
-			extra_command = UPDATE_EXTRA_CMD_STAY_IN_RO;
-			break;
-		case 'S':
-			serialno = optarg;
-			break;
-		case 't':
-			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_INFO;
-			extra_command_answer_len =
-				sizeof(struct touchpad_info);
-			break;
-		case 'u':
-			extra_command = UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK;
-			break;
-		case 'w':
-			extra_command = UPDATE_EXTRA_CMD_UNLOCK_RW;
-			break;
-		case 0:				/* auto-handled option */
-			break;
-		case '?':
-			if (optopt)
-				printf("Unrecognized option: -%c\n", optopt);
-			else
-				printf("Unrecognized option: %s\n",
-				       argv[optind - 1]);
-			errorcnt++;
-			break;
-		case ':':
-			printf("Missing argument to %s\n", argv[optind - 1]);
-			errorcnt++;
-			break;
-		default:
-			printf("Internal error at %s:%d\n", __FILE__, __LINE__);
-			exit(update_error);
-		}
-	}
-
-	if (errorcnt)
-		usage(errorcnt);
-
-	if (!show_fw_ver && extra_command == -1 && !touchpad_update) {
-		if (optind >= argc) {
-			fprintf(stderr,
-				"\nERROR: Missing required <binary image>\n\n");
-			usage(1);
-		}
-
-		data = get_file_or_die(argv[optind], &data_len);
-		printf("read %zd(%#zx) bytes from %s\n",
-		       data_len, data_len, argv[optind]);
-
-		fetch_header_versions(data, data_len);
-
-		if (binary_vers)
-			exit(show_headers_versions(data));
-	} else {
-		if (optind < argc)
-			printf("Ignoring binary image %s\n", argv[optind]);
-	}
-
-	usb_findit(vid, pid, serialno, &td.uep);
-
-	setup_connection(&td);
-
-	if (show_fw_ver) {
-		printf("Current versions:\n");
-		printf("Writable %32s\n", targ.common.version);
-	}
-
-	if (data) {
-		if (touchpad_update) {
-			transfer_section(&td,
-					data,
-					0x80000000,
-					data_len, 0);
-			free(data);
-
-			send_done(&td.uep);
-		} else {
-			transferred_sections = transfer_image(&td,
-							data, data_len);
-			free(data);
-
-			if (transferred_sections && !no_reset_request)
-				generate_reset_request(&td);
-		}
-	} else if (extra_command == UPDATE_EXTRA_CMD_CONSOLE_READ_INIT) {
-		read_console(&td);
-	} else if (extra_command > -1) {
-		send_subcommand(&td, extra_command,
-				extra_command_data, extra_command_data_len,
-				extra_command_answer, extra_command_answer_len);
-
-		switch (extra_command) {
-		case UPDATE_EXTRA_CMD_TOUCHPAD_INFO:
-			dump_touchpad_info(extra_command_answer,
-					   extra_command_answer_len);
-			break;
-		case  UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG:
-			hexdump(extra_command_answer, extra_command_answer_len);
-			break;
-		}
-	}
-
-	libusb_close(td.uep.devh);
-	libusb_exit(NULL);
-
-	if (!transferred_sections)
-		return noop;
-	/*
-	 * We should indicate if RO update was not done because of the
-	 * insufficient RW version.
-	 */
-	for (j = 0; j < ARRAY_SIZE(sections); j++)
-		if (sections[j].ustatus == not_possible) {
-			/* This will allow scripting repeat attempts. */
-			printf("Failed to update RO, run the command again\n");
-			return rw_updated;
-		}
-
-	printf("image updated\n");
-	return all_updated;
-}
diff --git a/firmware_builder.py b/firmware_builder.py
deleted file mode 100755
index d5a7e6ac8d..0000000000
--- a/firmware_builder.py
+++ /dev/null
@@ -1,250 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Build, bundle, or test all of the EC boards.
-
-This is the entry point for the custom firmware builder workflow recipe.  It
-gets invoked by chromite/api/controller/firmware.py.
-"""
-
-import argparse
-import multiprocessing
-import os
-import subprocess
-import sys
-
-# pylint: disable=import-error
-from google.protobuf import json_format
-# TODO(crbug/1181505): Code outside of chromite should not be importing from
-# chromite.api.gen.  Import json_format after that so we get the matching one.
-from chromite.api.gen.chromite.api import firmware_pb2
-
-
-DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles'
-DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata'
-
-# The the list of boards whose on-device unit tests we will verify compilation.
-# TODO(b/172501728) On-device unit tests should build for all boards, but
-# they've bit rotted, so we only build the ones that compile.
-BOARDS_UNIT_TEST = [
-    'bloonchipper',
-    'dartmonkey',
-]
-
-
-def build(opts):
-    """Builds all EC firmware targets
-
-    Note that when we are building unit tests for code coverage, we don't
-    need this step. It builds EC **firmware** targets, but unit tests with
-    code coverage are all host-based. So if the --code-coverage flag is set,
-    we don't need to build the firmware targets and we can return without
-    doing anything but creating the metrics file and giving an informational
-    message.
-    """
-    # TODO(b/169178847): Add appropriate metric information
-    metrics = firmware_pb2.FwBuildMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-
-    if opts.code_coverage:
-        print("When --code-coverage is selected, 'build' is a no-op. "
-              "Run 'test' with --code-coverage instead.")
-        return
-
-    cmd = ['make', 'buildall_only', '-j{}'.format(opts.cpus)]
-    print(f'# Running {" ".join(cmd)}.')
-    subprocess.run(cmd,
-                   cwd=os.path.dirname(__file__),
-                   check=True)
-
-
-def bundle(opts):
-    if opts.code_coverage:
-        bundle_coverage(opts)
-    else:
-        bundle_firmware(opts)
-
-
-def get_bundle_dir(opts):
-    """Get the directory for the bundle from opts or use the default.
-
-    Also create the directory if it doesn't exist.
-    """
-    bundle_dir = opts.output_dir if opts.output_dir else \
-        DEFAULT_BUNDLE_DIRECTORY
-    if not os.path.isdir(bundle_dir):
-        os.mkdir(bundle_dir)
-    return bundle_dir
-
-
-def write_metadata(opts, info):
-    """Write the metadata about the bundle."""
-    bundle_metadata_file = opts.metadata if opts.metadata else \
-        DEFAULT_BUNDLE_METADATA_FILE
-    with open(bundle_metadata_file, 'w') as f:
-        f.write(json_format.MessageToJson(info))
-
-
-def bundle_coverage(opts):
-    """Bundles the artifacts from code coverage into its own tarball."""
-    info = firmware_pb2.FirmwareArtifactInfo()
-    info.bcs_version_info.version_string = opts.bcs_version
-    bundle_dir = get_bundle_dir(opts)
-    ec_dir = os.path.dirname(__file__)
-    tarball_name = 'coverage.tbz2'
-    tarball_path = os.path.join(bundle_dir, tarball_name)
-    cmd = ['tar', 'cvfj', tarball_path, 'lcov.info']
-    subprocess.run(cmd, cwd=os.path.join(ec_dir, 'build/coverage'), check=True)
-    meta = info.objects.add()
-    meta.file_name = tarball_name
-    meta.lcov_info.type = (
-        firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV)
-
-    write_metadata(opts, info)
-
-
-def bundle_firmware(opts):
-    """Bundles the artifacts from each target into its own tarball."""
-    info = firmware_pb2.FirmwareArtifactInfo()
-    info.bcs_version_info.version_string = opts.bcs_version
-    bundle_dir = get_bundle_dir(opts)
-    ec_dir = os.path.dirname(__file__)
-    for build_target in sorted(os.listdir(os.path.join(ec_dir, 'build'))):
-        tarball_name = ''.join([build_target, '.firmware.tbz2'])
-        tarball_path = os.path.join(bundle_dir, tarball_name)
-        cmd = [
-            'tar', 'cvfj', tarball_path, '--exclude=*.o.d', '--exclude=*.o', '.'
-        ]
-        subprocess.run(
-            cmd, cwd=os.path.join(ec_dir, 'build', build_target), check=True)
-        meta = info.objects.add()
-        meta.file_name = tarball_name
-        meta.tarball_info.type = (
-            firmware_pb2.FirmwareArtifactInfo.TarballInfo.FirmwareType.EC)
-        # TODO(kmshelton): Populate the rest of metadata contents as it gets
-        # defined in infra/proto/src/chromite/api/firmware.proto.
-
-    write_metadata(opts, info)
-
-
-def test(opts):
-    """Runs all of the unit tests for EC firmware"""
-    # TODO(b/169178847): Add appropriate metric information
-    metrics = firmware_pb2.FwTestMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-
-    # If building for code coverage, build the 'coverage' target, which
-    # builds the posix-based unit tests for code coverage and assembles
-    # the LCOV information.
-    #
-    # Otherwise, build the 'runtests' target, which verifies all
-    # posix-based unit tests build and pass.
-    target = 'coverage' if opts.code_coverage else 'runtests'
-    cmd = ['make', target, '-j{}'.format(opts.cpus)]
-    print(f'# Running {" ".join(cmd)}.')
-    subprocess.run(cmd,
-                   cwd=os.path.dirname(__file__),
-                   check=True)
-
-    if not opts.code_coverage:
-        # Verify compilation of the on-device unit test binaries.
-        # TODO(b/172501728) These should build  for all boards, but they've bit
-        # rotted, so we only build the ones that compile.
-        cmd = ['make', '-j{}'.format(opts.cpus)]
-        cmd.extend(['tests-' + b for b in BOARDS_UNIT_TEST])
-        print(f'# Running {" ".join(cmd)}.')
-        subprocess.run(cmd,
-                       cwd=os.path.dirname(__file__),
-                       check=True)
-
-
-def main(args):
-    """Builds, bundles, or tests all of the EC targets.
-
-    Additionally, the tool reports build metrics.
-    """
-    opts = parse_args(args)
-
-    if not hasattr(opts, 'func'):
-        print('Must select a valid sub command!')
-        return -1
-
-    # Run selected sub command function
-    try:
-        opts.func(opts)
-    except subprocess.CalledProcessError:
-        return 1
-    else:
-        return 0
-
-
-def parse_args(args):
-    parser = argparse.ArgumentParser(description=__doc__)
-
-    parser.add_argument(
-        '--cpus',
-        default=multiprocessing.cpu_count(),
-        help='The number of cores to use.',
-    )
-
-    parser.add_argument(
-        '--metrics',
-        dest='metrics',
-        required=True,
-        help='File to write the json-encoded MetricsList proto message.',
-    )
-
-    parser.add_argument(
-        '--metadata',
-        required=False,
-        help='Full pathname for the file in which to write build artifact '
-        'metadata.',
-    )
-
-    parser.add_argument(
-        '--output-dir',
-        required=False,
-        help='Full pathanme for the directory in which to bundle build '
-        'artifacts.',
-    )
-
-    parser.add_argument(
-        '--code-coverage',
-        required=False,
-        action='store_true',
-        help='Build host-based unit tests for code coverage.',
-    )
-
-    parser.add_argument(
-        '--bcs-version',
-        dest='bcs_version',
-        default='',
-        required=False,
-        # TODO(b/180008931): make this required=True.
-        help='BCS version to include in metadata.',
-    )
-
-    # Would make this required=True, but not available until 3.7
-    sub_cmds = parser.add_subparsers()
-
-    build_cmd = sub_cmds.add_parser('build',
-                                    help='Builds all firmware targets')
-    build_cmd.set_defaults(func=build)
-
-    build_cmd = sub_cmds.add_parser('bundle',
-                                    help='Creates a tarball containing build '
-                                    'artifacts from all firmware targets')
-    build_cmd.set_defaults(func=bundle)
-
-    test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests')
-    test_cmd.set_defaults(func=test)
-
-    return parser.parse_args(args)
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/fuzz/build.mk b/fuzz/build.mk
deleted file mode 100644
index 3b5f117d20..0000000000
--- a/fuzz/build.mk
+++ /dev/null
@@ -1,34 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# fuzzer binaries
-#
-
-fuzz-test-list-host =
-# Fuzzers should only be built for architectures that support sanitizers.
-ifeq ($(ARCH),amd64)
-fuzz-test-list-host += host_command_fuzz usb_pd_fuzz usb_tcpm_v2_rev20_fuzz \
-	usb_tcpm_v2_rev30_fuzz pchg_fuzz
-endif
-
-# For fuzzing targets libec.a is built from the ro objects and hides functions
-# that collide with stdlib. The rw only objects are then linked against libec.a
-# with stdlib support. Therefore fuzzing targets that need to call this internal
-# functions should be marked "-y" or "-ro", and fuzzing targets that need stdlib
-# should be marked "-rw". In other words:
-#
-# Does your object file need to link against the Cr50 implementations of stdlib
-# functions?
-#   Yes -> use <obj_name>-y
-# Does your object file need to link against cstdlib?
-#   Yes -> use <obj_name>-rw
-# Otherwise use <obj_name>-y
-host_command_fuzz-y = host_command_fuzz.o
-usb_pd_fuzz-y = usb_pd_fuzz.o
-usb_tcpm_v2_rev30_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev30_fuzz.o \
-	../test/fake_battery.o
-usb_tcpm_v2_rev20_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev20_fuzz.o \
-	../test/fake_battery.o
-pchg_fuzz-y = pchg_fuzz.o
\ No newline at end of file
diff --git a/fuzz/fuzz_config.h b/fuzz/fuzz_config.h
deleted file mode 100644
index fb974ea727..0000000000
--- a/fuzz/fuzz_config.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fuzzer target config flags */
-
-#ifndef __FUZZ_FUZZ_CONFIG_H
-#define __FUZZ_FUZZ_CONFIG_H
-#ifdef TEST_FUZZ
-
-/* Disable hibernate: We never want to exit while fuzzing. */
-#undef CONFIG_HIBERNATE
-
-#ifdef TEST_HOST_COMMAND_FUZZ
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-
-/* Defining this makes fuzzing slower, but exercises additional code paths. */
-#define FUZZ_HOSTCMD_VERBOSE
-
-#ifdef FUZZ_HOSTCMD_VERBOSE
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_PARAMS
-#else
-#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
-#endif /* ! FUZZ_HOSTCMD_VERBOSE */
-
-/* The following are for fpsensor host commands. */
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-#define CONFIG_SHA256
-
-#endif /* TEST_HOST_COMMAND_FUZZ */
-
-#ifdef TEST_USB_PD_FUZZ
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#endif /* TEST_USB_PD_FUZZ */
-
-#ifdef TEST_USB_TCPM_V2_REV30_FUZZ
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PID 0x5555
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US 5000
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
-#endif /* TEST_USB_TCPM_V2_REV30_FUZZ */
-
-#ifdef TEST_USB_TCPM_V2_REV20_FUZZ
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PID 0x5555
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US 5000
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
-#endif /* TEST_USB_TCPM_V2_REV20_FUZZ */
-
-#ifdef TEST_PCHG_FUZZ
-#define CONFIG_CTN730
-#define CONFIG_DEVICE_EVENT
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PERIPHERAL_CHARGER
-#define I2C_PORT_WLC		0
-#define GPIO_WLC_IRQ_CONN	1
-#define GPIO_WLC_NRST_CONN	2
-#define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN
-#endif  /* TEST_PCHG_FUZZ */
-
-#endif  /* TEST_FUZZ */
-#endif  /* __FUZZ_FUZZ_CONFIG_H */
diff --git a/fuzz/host_command_fuzz.c b/fuzz/host_command_fuzz.c
deleted file mode 100644
index 4ca94ff616..0000000000
--- a/fuzz/host_command_fuzz.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Fuzz host command.
- */
-
-#include <pthread.h>
-#include <sys/time.h>
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "host_test.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-/* Only test requests with valid size and checksum (makes fuzzing faster) */
-#define VALID_REQUEST_ONLY
-
-#define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_HOSTCMD_DONE TASK_EVENT_CUSTOM_BIT(1)
-
-/* Request/response buffer size (and maximum command length) */
-#define BUFFER_SIZE 128
-
-struct host_packet pkt;
-static uint8_t resp_buf[BUFFER_SIZE];
-struct ec_host_response *resp = (struct ec_host_response *)resp_buf;
-static uint8_t req_buf[BUFFER_SIZE];
-static struct ec_host_request *req = (struct ec_host_request *)req_buf;
-
-static void hostcmd_respond(struct host_packet *pkt)
-{
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_HOSTCMD_DONE);
-}
-
-static char calculate_checksum(const char *buf, int size)
-{
-	int c = 0;
-	int i;
-
-	for (i = 0; i < size; ++i)
-		c += buf[i];
-
-	return -c;
-}
-
-struct chunk {
-	int start;
-	int size;
-};
-
-static int hostcmd_fill(const uint8_t *data, size_t size)
-{
-	static int first = 1;
-
-#ifdef VALID_REQUEST_ONLY
-	const int checksum_offset = offsetof(struct ec_host_request, checksum);
-	const int checksum_size = sizeof(req->checksum);
-	const int data_len_offset = offsetof(struct ec_host_request, data_len);
-	const int data_len_size = sizeof(req->data_len);
-
-	struct chunk chunks[3];
-
-	chunks[0].start = 0;
-	chunks[0].size = checksum_offset;
-	chunks[1].start = chunks[0].start + chunks[0].size + checksum_size;
-	chunks[1].size = data_len_offset - chunks[1].start;
-	chunks[2].start = chunks[1].start + chunks[1].size + data_len_size;
-	chunks[2].size = sizeof(req_buf) - chunks[2].start;
-#else
-	struct chunk chunks[1] = { {0, sizeof(req_buf)} };
-#endif
-
-	int ipos = 0;
-	int i;
-	int req_size = 0;
-
-	/*
-	 * TODO(chromium:854975): We should probably malloc req_buf with the
-	 * correct size, to make we do not read uninitialized req_buf data.
-	 */
-	memset(req_buf, 0, sizeof(req_buf));
-
-	/*
-	 * Fill in req_buf, according to chunks defined above (i.e. skipping
-	 * over checksum and data_len.
-	 */
-	for (i = 0; i < ARRAY_SIZE(chunks) && ipos < size; i++) {
-		int cp_size = MIN(chunks[i].size, size-ipos);
-
-		memcpy(req_buf + chunks[i].start, data + ipos, cp_size);
-
-		ipos += cp_size;
-
-		req_size = chunks[i].start + cp_size;
-	}
-
-	/* Not enough space in req_buf. */
-	if (ipos != size)
-		return -1;
-
-	pkt.request_size = req_size;
-	req->data_len = req_size - sizeof(*req);
-	req->checksum = calculate_checksum(req_buf, req_size);
-
-	/*
-	 * Print the full request on the first fuzzing attempt: useful to
-	 * report bugs, and write up commit messages when reproducing
-	 * issues.
-	 */
-	if (first) {
-		ccprintf("Request: cmd=%04x data=%ph\n",
-			req->command, HEX_BUF(req_buf, req_size));
-		first = 0;
-	}
-
-	pkt.send_response = hostcmd_respond;
-	pkt.request = (const void *)req_buf;
-	pkt.request_max = BUFFER_SIZE;
-	pkt.response = (void *)resp_buf;
-	pkt.response_max = BUFFER_SIZE;
-	pkt.driver_result = 0;
-
-	return 0;
-}
-
-static pthread_cond_t done_cond;
-static pthread_mutex_t lock;
-
-void run_test(int argc, char **argv)
-{
-	ccprints("Fuzzing task started");
-	wait_for_task_started();
-
-	while (1) {
-		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
-		/* Send the host command (pkt prepared by main thread). */
-		host_packet_receive(&pkt);
-		task_wait_event_mask(TASK_EVENT_HOSTCMD_DONE, -1);
-		pthread_cond_signal(&done_cond);
-	}
-}
-
-int test_fuzz_one_input(const uint8_t *data, unsigned int size)
-{
-	/* Fill in req_buf. */
-	if (hostcmd_fill(data, size) < 0)
-		return 0;
-
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ);
-	pthread_cond_wait(&done_cond, &lock);
-
-#ifdef VALID_REQUEST_ONLY
-	/*
-	 * We carefully crafted all our requests to have a valid checksum, so
-	 * we should never receive an invalid checksum error. (but ignore
-	 * EC_CMD_TEST_PROTOCOL, as it can lead to arbitrary result values).
-	 */
-	ASSERT(req->command == EC_CMD_TEST_PROTOCOL ||
-	       resp->result != EC_RES_INVALID_CHECKSUM);
-#endif
-
-	return 0;
-}
-
diff --git a/fuzz/host_command_fuzz.mocklist b/fuzz/host_command_fuzz.mocklist
deleted file mode 100644
index 4ffc786b32..0000000000
--- a/fuzz/host_command_fuzz.mocklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST \
-	MOCK(FP_SENSOR)        \
-	MOCK(FPSENSOR_DETECT)  \
-	MOCK(MKBP_EVENTS)      \
-	MOCK(ROLLBACK)
diff --git a/fuzz/host_command_fuzz.tasklist b/fuzz/host_command_fuzz.tasklist
deleted file mode 100644
index 2ff8a94d98..0000000000
--- a/fuzz/host_command_fuzz.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-        TASK_TEST(FPSENSOR, fp_task, NULL, TASK_STACK_SIZE)
diff --git a/fuzz/pchg_fuzz.c b/fuzz/pchg_fuzz.c
deleted file mode 100644
index 97dbca74c4..0000000000
--- a/fuzz/pchg_fuzz.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test peripheral device charger module.
- */
-
-#define HIDE_EC_STDLIB
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/nfc/ctn730.h"
-#include "peripheral_charger.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#include <pthread.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
-
-extern struct pchg_drv ctn730_drv;
-struct pchg pchgs[] = {
-	[0] = {
-		.cfg = &(const struct pchg_config) {
-			.drv = &ctn730_drv,
-			.i2c_port = I2C_PORT_WLC,
-			.irq_pin = GPIO_WLC_IRQ_CONN,
-			.full_percent = 96,
-			.block_size = 128,
-		},
-		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
-	},
-};
-const int pchg_count = ARRAY_SIZE(pchgs);
-
-static pthread_cond_t done_cond;
-static pthread_mutex_t lock;
-
-#define MAX_MESSAGES 8
-#define MAX_MESSAGE_SIZE (sizeof(struct ctn730_msg) \
-			  + member_size(struct ctn730_msg, length) * 256)
-static uint8_t input[MAX_MESSAGE_SIZE * MAX_MESSAGES];
-static uint8_t *head, *tail;
-static bool data_available;
-
-int pchg_i2c_xfer(int port, uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	if (port != I2C_PORT_WLC || addr_flags != CTN730_I2C_ADDR)
-		return EC_ERROR_INVAL;
-
-	if (in == NULL || in_size == 0)
-		return EC_SUCCESS;
-
-	if (head + in_size >= tail) {
-		data_available = false;
-		return EC_ERROR_OVERFLOW;
-	}
-
-	memcpy(in, head, in_size);
-	head += in_size;
-
-	return EC_SUCCESS;
-}
-DECLARE_TEST_I2C_XFER(pchg_i2c_xfer);
-
-/*
- * Task for generating IRQs. The task priority is lower than the PCHG task so
- * that it can yield the CPU to the PCHG task.
- */
-void irq_task(int argc, char **argv)
-{
-	ccprints("%s task started", __func__);
-	wait_for_task_started();
-
-	while (1) {
-		int i = 0;
-
-		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
-		test_chipset_on();
-
-		while (data_available && i++ < MAX_MESSAGES)
-			pchg_irq(pchgs[0].cfg->irq_pin);
-
-		test_chipset_off();
-
-		pthread_mutex_lock(&lock);
-		pthread_cond_signal(&done_cond);
-		pthread_mutex_unlock(&lock);
-	}
-
-}
-
-void run_test(int argc, char **argv)
-{
-	ccprints("Fuzzing task started");
-	task_wait_event(-1);
-}
-
-int test_fuzz_one_input(const uint8_t *data, unsigned int size)
-{
-	/* We're not interested in too small or too large input. */
-	if (size < sizeof(struct ctn730_msg) || sizeof(input) < size)
-		return 0;
-
-	pthread_mutex_init(&lock, NULL);
-	pthread_cond_init(&done_cond, NULL);
-
-	head = input;
-	tail = input + size;
-	memcpy(input, data, size);
-	data_available = true;
-
-	task_set_event(TASK_ID_IRQ, TASK_EVENT_FUZZ);
-
-	pthread_mutex_lock(&lock);
-	pthread_cond_wait(&done_cond, &lock);
-	pthread_mutex_unlock(&lock);
-
-	return 0;
-}
diff --git a/fuzz/pchg_fuzz.corpus b/fuzz/pchg_fuzz.corpus
deleted file mode 100644
index 0b069baf4f..0000000000
--- a/fuzz/pchg_fuzz.corpus
+++ /dev/null
@@ -1,26 +0,0 @@
-"\xae\x01"
-"\x18\x01\x00\x00"
-"\xff~"
-"\x01u"
-"\x80\x00\x00\x00"
-"Q\x00"
-"5\x00"
-"\xb7\x01\x00\x00"
-"\x01\x00\x00\x00\x01\x00\x00\x00"
-"\x00\x00\x00\x00\x00\x00\x00\x00"
-"\xff\xff\xff\x00n_\x0b\xc0"
-"\x92\x00"
-"\xff\xdc"
-"\xa6\x01"
-"\x85f\xfc$\x00\x00\x00\x00"
-"\xff\xff\xff\xff\xff\xff\xff\xff"
-"\xff\xff\xff\xff\x00\x00\x00\x00"
-"\xfff"
-"\x01\xcb"
-"\x8f\x00\x00\x00"
-"\xff\xff\xff\x0d"
-"=\x00\x00\x00"
-"\xbc\x00"
-"\x02\x91"
-"\xff\xff\xff\x00\x00\x00\x00\x00"
-"\x00y"
diff --git a/fuzz/pchg_fuzz.tasklist b/fuzz/pchg_fuzz.tasklist
deleted file mode 100644
index 5b30e09245..0000000000
--- a/fuzz/pchg_fuzz.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(IRQ, irq_task, NULL, TASK_STACK_SIZE) \
-	TASK_TEST(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/fuzz/span.h b/fuzz/span.h
deleted file mode 100644
index 531df832a3..0000000000
--- a/fuzz/span.h
+++ /dev/null
@@ -1,56 +0,0 @@
-// Copyright 2018 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE file.
-
-#ifndef __FUZZ_SPAN_H
-#define __FUZZ_SPAN_H
-
-#include <unistd.h>
-
-#include <algorithm>
-
-namespace fuzz {
-
-template <typename T>
-class span {
- public:
-  typedef T value_type;
-
-  constexpr span() : span<T>(nullptr, nullptr) {}
-  constexpr span(T* begin, size_t size) : begin_(begin), end_(begin + size) {}
-  constexpr span(T* begin, T* end) : begin_(begin), end_(end) {}
-
-  template <class Container>
-  constexpr span(Container& container)
-      : begin_(container.begin()), end_(container.end()){};
-
-  constexpr T* begin() const { return begin_; }
-  constexpr T* end() const { return end_; }
-
-  constexpr T* data() const { return begin_; }
-
-  constexpr bool empty() const { return begin_ == end_; }
-  constexpr size_t size() const { return end_ - begin_; }
-
- private:
-  T* begin_;
-  T* end_;
-};
-
-template <typename Source, typename Destination>
-size_t CopyWithPadding(Source source,
-                       Destination destination,
-                       typename Destination::value_type fill_value) {
-  if (source.size() >= destination.size()) {
-    std::copy(source.begin(), source.begin() + destination.size(),
-              destination.begin());
-    return destination.size();
-  }
-  std::copy(source.begin(), source.end(), destination.begin());
-  std::fill(destination.begin() + source.size(), destination.end(), fill_value);
-  return source.size();
-}
-
-}  // namespace fuzz
-
-#endif  // __FUZZ_SPAN_H
diff --git a/fuzz/usb_pd_fuzz.c b/fuzz/usb_pd_fuzz.c
deleted file mode 100644
index 64eb0913a6..0000000000
--- a/fuzz/usb_pd_fuzz.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PD module.
- */
-#define HIDE_EC_STDLIB
-#include "common.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#include <pthread.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
-
-#define PORT0	0
-
-static int mock_tcpm_init(int port) { return EC_SUCCESS; }
-static int mock_tcpm_release(int port) { return EC_SUCCESS; }
-
-static int mock_tcpm_select_rp_value(int port, int rp)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_tcpm_set_cc(int port, int pull) { return EC_SUCCESS; }
-static int mock_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return EC_SUCCESS;
-}
-
-static __maybe_unused int mock_tcpm_sop_prime_enable(int port, bool enable)
-{
-	return EC_SUCCESS;
-}
-
-static int mock_tcpm_set_vconn(int port, int enable) { return EC_SUCCESS; }
-static int mock_tcpm_set_msg_header(int port,
-			int power_role, int data_role) { return EC_SUCCESS; }
-static int mock_tcpm_set_rx_enable(int port, int enable) { return EC_SUCCESS; }
-static int mock_tcpm_transmit(int port, enum tcpci_msg_type type,
-		uint16_t header, const uint32_t *data)
-{ return EC_SUCCESS; }
-static void mock_tcpc_alert(int port) {}
-static int mock_tcpci_get_chip_info(int port, int live,
-		struct ec_response_pd_chip_info_v1 *info)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static __maybe_unused int mock_enter_low_power_mode(int port)
-{
-	return EC_SUCCESS;
-}
-
-#define MAX_TCPC_PAYLOAD 28
-
-struct message {
-	uint8_t cnt;
-	uint16_t header;
-	uint8_t payload[MAX_TCPC_PAYLOAD];
-} __packed;
-
-struct tcpc_state {
-	enum tcpc_cc_voltage_status cc1, cc2;
-	struct message message;
-};
-
-static struct tcpc_state mock_tcpc_state[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int mock_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	*cc1 = mock_tcpc_state[port].cc1;
-	*cc2 = mock_tcpc_state[port].cc2;
-
-	return EC_SUCCESS;
-}
-
-static int pending;
-
-int tcpm_has_pending_message(const int port)
-{
-	return pending;
-}
-
-int tcpm_dequeue_message(const int port, uint32_t *const payload,
-			 int *const header)
-{
-	struct message *m = &mock_tcpc_state[port].message;
-
-	ccprints("%s", __func__);
-
-	/* Force a segfault, if no message is actually pending. */
-	if (pending == 0)
-		m = NULL;
-
-	*header = m->header;
-
-	/*
-	 * This mirrors what tcpci.c:tcpm_dequeue_message does: always copy the
-	 * whole payload to destination.
-	 */
-	memcpy(payload, m->payload, sizeof(m->payload));
-
-	pending--;
-	return EC_SUCCESS;
-}
-
-/* Note this method can be called from an interrupt context. */
-int tcpm_enqueue_message(const int port)
-{
-	pending = 1;
-
-	/* Wake PD task up so it can process incoming RX messages */
-	task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE);
-
-	return EC_SUCCESS;
-}
-
-void tcpm_clear_pending_messages(int port) {}
-
-static const struct tcpm_drv mock_tcpm_drv = {
-	.init                   = &mock_tcpm_init,
-	.release                = &mock_tcpm_release,
-	.get_cc                 = &mock_tcpm_get_cc,
-#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &mock_tcpm_check_vbus_level,
-#endif
-	.select_rp_value        = &mock_tcpm_select_rp_value,
-	.set_cc                 = &mock_tcpm_set_cc,
-	.set_polarity           = &mock_tcpm_set_polarity,
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable		= &mock_tcpm_sop_prime_enable,
-#endif
-	.set_vconn              = &mock_tcpm_set_vconn,
-	.set_msg_header         = &mock_tcpm_set_msg_header,
-	.set_rx_enable          = &mock_tcpm_set_rx_enable,
-	/* The core calls tcpm_dequeue_message. */
-	.get_message_raw        = NULL,
-	.transmit               = &mock_tcpm_transmit,
-	.tcpc_alert             = &mock_tcpc_alert,
-	.get_chip_info          = &mock_tcpci_get_chip_info,
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &mock_enter_low_power_mode,
-#endif
-};
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpm_drv,
-	},
-	{
-		.drv = &mock_tcpm_drv,
-	}
-};
-
-static pthread_cond_t done_cond;
-static pthread_mutex_t lock;
-
-enum tcpc_cc_voltage_status next_cc1, next_cc2;
-#define MAX_MESSAGES 8
-static struct message messages[MAX_MESSAGES];
-
-void run_test(int argc, char **argv)
-{
-	uint8_t port = PORT0;
-	int i;
-
-	ccprints("Fuzzing task started");
-	wait_for_task_started();
-
-	while (1) {
-		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
-
-		memset(&mock_tcpc_state[port],
-			0, sizeof(mock_tcpc_state[port]));
-
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
-		task_wait_event(250 * MSEC);
-
-		mock_tcpc_state[port].cc1 = next_cc1;
-		mock_tcpc_state[port].cc2 = next_cc2;
-
-		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-		task_wait_event(50 * MSEC);
-
-		/* Fake RX messages, one by one. */
-		for (i = 0; i < MAX_MESSAGES && messages[i].cnt; i++) {
-			memcpy(&mock_tcpc_state[port].message, &messages[i],
-				sizeof(messages[i]));
-
-			tcpm_enqueue_message(port);
-			task_wait_event(50 * MSEC);
-		}
-
-		pthread_cond_signal(&done_cond);
-	}
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return 0;
-}
-
-int test_fuzz_one_input(const uint8_t *data, unsigned int size)
-{
-	int i;
-
-	if (size < 1)
-		return 0;
-
-	next_cc1 = data[0] & 0x0f;
-	next_cc2 = (data[0] & 0xf0) >> 4;
-	data++; size--;
-
-	memset(messages, 0, sizeof(messages));
-
-	for (i = 0; i < MAX_MESSAGES && size > 0; i++) {
-		int cnt = data[0];
-
-		if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD+3 || cnt > size) {
-			/* Invalid count, or out of bounds. */
-			return 0;
-		}
-
-		memcpy(&messages[i], data, cnt);
-
-		data += cnt; size -= cnt;
-	}
-
-	if (size != 0) {
-		/* Useless extra data in buffer, skip. */
-		return 0;
-	}
-
-	task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_FUZZ);
-	pthread_cond_wait(&done_cond, &lock);
-
-	return 0;
-}
diff --git a/fuzz/usb_pd_fuzz.tasklist b/fuzz/usb_pd_fuzz.tasklist
deleted file mode 100644
index 6edeac2f98..0000000000
--- a/fuzz/usb_pd_fuzz.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.c b/fuzz/usb_tcpm_v2_rev20_fuzz.c
deleted file mode 100644
index f5afb92ac1..0000000000
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Stubs needed for fuzz testing the USB TCPMv2 state machines.
- */
-
-#define HIDE_EC_STDLIB
-#include "charge_manager.h"
-#include "mock/usb_mux_mock.h"
-#include "usb_pd.h"
-
-const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-/* USB mux configuration */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	},
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-int pd_check_vconn_swap(int port)
-{
-	return 1;
-}
-
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist b/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
deleted file mode 100644
index 1b2c615371..0000000000
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST \
-	MOCK(USB_MUX)
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist b/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
deleted file mode 100644
index e3ad19e719..0000000000
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
-
diff --git a/fuzz/usb_tcpm_v2_rev30_fuzz.c b/fuzz/usb_tcpm_v2_rev30_fuzz.c
deleted file mode 120000
index e62b1786fd..0000000000
--- a/fuzz/usb_tcpm_v2_rev30_fuzz.c
+++ /dev/null
@@ -1 +0,0 @@
-usb_tcpm_v2_rev20_fuzz.c
\ No newline at end of file
diff --git a/fuzz/usb_tcpm_v2_rev30_fuzz.mocklist b/fuzz/usb_tcpm_v2_rev30_fuzz.mocklist
deleted file mode 120000
index 061e1ef826..0000000000
--- a/fuzz/usb_tcpm_v2_rev30_fuzz.mocklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_tcpm_v2_rev20_fuzz.mocklist
\ No newline at end of file
diff --git a/fuzz/usb_tcpm_v2_rev30_fuzz.tasklist b/fuzz/usb_tcpm_v2_rev30_fuzz.tasklist
deleted file mode 120000
index a01883297a..0000000000
--- a/fuzz/usb_tcpm_v2_rev30_fuzz.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_tcpm_v2_rev20_fuzz.tasklist
\ No newline at end of file
diff --git a/include/accel_cal.h b/include/accel_cal.h
deleted file mode 100644
index 80f0161a04..0000000000
--- a/include/accel_cal.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Online accelerometer calibration */
-
-#ifndef __CROS_EC_ACCEL_CAL_H
-#define __CROS_EC_ACCEL_CAL_H
-
-#include "common.h"
-#include "kasa.h"
-#include "newton_fit.h"
-#include "stdbool.h"
-#include "stillness_detector.h"
-
-struct accel_cal_algo {
-	struct kasa_fit kasa_fit;
-	struct newton_fit newton_fit;
-};
-
-struct accel_cal {
-	struct still_det still_det;
-	struct accel_cal_algo *algos;
-	uint8_t num_temp_windows;
-	fpv3_t bias;
-};
-
-/**
- * Reset the accelerometer calibration object. This should only be called
- * once. The struct will reset automatically in accel_cal_accumulate when
- * a new calibration is computed.
- *
- * @param cal Pointer to the accel_cal struct to reset.
- */
-void accel_cal_reset(struct accel_cal *cal);
-
-/**
- * Add new reading to the accelerometer calibration.
- *
- * @param cal Pointer to the accel_cal struct to update.
- * @param sample_time The timestamp when the sample was taken.
- * @param x X component of the new reading.
- * @param y Y component of the new reading.
- * @param z Z component of the new reading.
- * @param temp The sensor's internal temperature in degrees C.
- * @return True if a new bias is available.
- */
-bool accel_cal_accumulate(struct accel_cal *cal, uint32_t sample_time, fp_t x,
-			  fp_t y, fp_t z, fp_t temp);
-
-#endif /* __CROS_EC_ACCEL_CAL_H */
diff --git a/include/adc.h b/include/adc.h
deleted file mode 100644
index 8342bc1fb6..0000000000
--- a/include/adc.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* ADC interface for Chrome EC */
-
-#ifndef __CROS_EC_ADC_H
-#define __CROS_EC_ADC_H
-
-#include "adc_chip.h"
-#include "common.h"
-
-#define ADC_READ_ERROR -1  /* Value returned by adc_read_channel() on error */
-
-#ifdef CONFIG_ZEPHYR
-#include <zephyr_adc.h>
-#endif /* CONFIG_ZEPHYR */
-
-/*
- * Boards must provide this list of ADC channel definitions.  This must match
- * the enum adc_channel list provided by the board.
- */
-#ifndef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-extern const struct adc_t adc_channels[];
-#else
-extern struct adc_t adc_channels[];
-#endif
-
-/*
- * Boards which use the ADC interface must provide enum adc_channel in the
- * board.h file.  See chip/$CHIP/adc_chip.h for additional chip-specific
- * requirements.
- */
-
-/**
- * Read an ADC channel.
- *
- * @param ch		Channel to read
- *
- * @return The scaled ADC value, or ADC_READ_ERROR if error.
- */
-int adc_read_channel(enum adc_channel ch);
-
-/**
- * Enable ADC watchdog. Note that interrupts might come in repeatedly very
- * quickly when ADC output goes out of the accepted range.
- *
- * @param ain_id	The AIN to be watched by the watchdog.
- * @param high		The high threshold that the watchdog would trigger
- *			an interrupt when exceeded.
- * @param low		The low threshold.
- *
- * @return		EC_SUCCESS, or non-zero if any error.
- */
-int adc_enable_watchdog(int ain_id, int high, int low);
-
-/**
- * Disable ADC watchdog.
- *
- * @return		EC_SUCCESS, or non-zero if any error.
- */
-int adc_disable_watchdog(void);
-
-/**
- * Set the delay between ADC watchdog samples. This can be used as a trade-off
- * of power consumption and performance.
- *
- * @param delay_ms      The delay in milliseconds between two ADC watchdog
- *                      samples.
- *
- * @return              EC_SUCCESS, or non-zero if any error or not supported.
- */
-int adc_set_watchdog_delay(int delay_ms);
-
-#endif  /* __CROS_EC_ADC_H */
diff --git a/include/aes-gcm.h b/include/aes-gcm.h
deleted file mode 120000
index ba62939792..0000000000
--- a/include/aes-gcm.h
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/include/aes-gcm.h
\ No newline at end of file
diff --git a/include/aes.h b/include/aes.h
deleted file mode 120000
index b30c680a6a..0000000000
--- a/include/aes.h
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/include/aes.h
\ No newline at end of file
diff --git a/include/als.h b/include/als.h
deleted file mode 100644
index 4ff3fcdb4f..0000000000
--- a/include/als.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ALS_H
-#define __CROS_EC_ALS_H
-
-#include "common.h"
-
-/* Priority for ALS HOOK int */
-#define HOOK_PRIO_ALS_INIT (HOOK_PRIO_DEFAULT + 1)
-
-/* Defined in board.h */
-enum als_id;
-
-/* Initialized in board.c */
-struct als_t {
-	const char *const name;
-	int (*init)(void);
-	int (*read)(int *lux, int af);
-	int attenuation_factor;
-};
-
-extern struct als_t als[];
-
-/**
- * Read an ALS
- *
- * @param id		Which one?
- * @param lux	        Put value here
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int als_read(enum als_id id, int *lux);
-
-#endif  /* __CROS_EC_ALS_H */
diff --git a/include/audio_codec.h b/include/audio_codec.h
deleted file mode 100644
index b80d1c0f57..0000000000
--- a/include/audio_codec.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_AUDIO_CODEC_H
-#define __CROS_EC_AUDIO_CODEC_H
-
-#include "stdint.h"
-
-/*
- * Common abstract layer
- */
-
-/*
- * Checks capability of audio codec.
- *
- * @cap is an integer from enum ec_codec_cap.  Note that it represents a
- * bit field in a 32-bit integer.  The valid range is [0, 31].
- *
- * Returns:
- *   1 if audio codec capabilities include cap passed as parameter.
- *   0 if not capable.
- */
-int audio_codec_capable(uint8_t cap);
-
-/*
- * Registers shared memory (SHM).
- *
- * @shm_id is a SHM identifier from enum ec_codec_shm_id.
- * @cap is an integer from enum ec_codec_cap.
- * @addr is the address pointer to the SHM.
- * @len is the maximum length of the SHM.
- * @type is an integer from enum ec_codec_shm_type.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal errors.
- *   EC_ERROR_INVAL if invalid shm_id.
- *   EC_ERROR_INVAL if invalid cap.
- *   EC_ERROR_BUSY if the shm_id has been registered.
- */
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type);
-
-/*
- * Translates the physical address from AP to EC's memory space.  Required if
- * wants to use AP SHM.
- *
- * @ap_addr is physical address from AP.
- * @ec_addr is the translation destination.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal errors.
- *   EC_ERROR_UNIMPLEMENTED if no concrete implementation.
- */
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr);
-
-/*
- * Scales a S16_LE sample by multiplying scalar.
- */
-int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar);
-
-
-/*
- * DMIC abstract layer
- */
-
-/*
- * Gets the maximum possible gain value.  All channels share the same maximum
- * gain value [0, max].
- *
- * The gain has no unit and should fit in a scale to represent relative dB.
- *
- * For example, suppose maximum possible gain value is 4, one could define a
- * mapping:
- * - 0 => -10 dB
- * - 1 => -5 dB
- * - 2 => 0 dB
- * - 3 => 5 dB
- * - 4 => 10 dB
- *
- * @max_gain is the destination address to put the gain value.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- */
-int audio_codec_dmic_get_max_gain(uint8_t *max_gain);
-
-/*
- * Sets the microphone gain for the specified channel.
- *
- * @channel is an integer from enum ec_codec_dmic_channel.  The valid range
- * is [0, 7].
- * @gain is the target gain for the specified channel.  The valid range
- * is [0, max_gain].  See also audio_codec_dmic_get_max_gain.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_INVAL if channel does not look good.
- *   EC_ERROR_INVAL if gain does not look good.
- */
-int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain);
-
-/*
- * Gets the microphone gain of the specified channel.
- *
- * @channel is an integer from enum ec_codec_dmic_channel.  The valid range
- * is [0, 7].
- * @gain is the destination address to put the gain value of the channel.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_INVAL if channel does not look good.
- */
-int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain);
-
-
-/*
- * I2S RX abstract layer
- */
-
-/*
- * Enables I2S RX.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has enabled.
- */
-int audio_codec_i2s_rx_enable(void);
-
-/*
- * Disables I2S RX.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has not enabled.
- */
-int audio_codec_i2s_rx_disable(void);
-
-/*
- * Sets I2S RX sample depth.
- *
- * @depth is an integer from enum ec_codec_i2s_rx_sample_depth.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_INVAL if depth does not look good.
- */
-int audio_codec_i2s_rx_set_sample_depth(uint8_t depth);
-
-/*
- * Sets I2S RX DAI format.
- *
- * @daifmt is an integer from enum ec_codec_i2s_rx_daifmt.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_INVAL if daifmt does not look good.
- */
-int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt);
-
-/*
- * Sets I2S RX BCLK.
- *
- * @bclk is an integer to represent the bit clock rate.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_INVAL if bclk does not look good.
- */
-int audio_codec_i2s_rx_set_bclk(uint32_t bclk);
-
-
-/*
- * WoV abstract layer
- */
-
-/*
- * Enables WoV.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has enabled.
- */
-int audio_codec_wov_enable(void);
-
-/*
- * Disables WoV.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has not enabled.
- */
-int audio_codec_wov_disable(void);
-
-/*
- * Reads the WoV audio data from chip.
- *
- * @buf is the target pointer to put the data.
- * @count is the maximum number of bytes to read.
- *
- * Returns:
- *   -1 if any errors.
- *   0 if no data.
- *   >0 if success.  The returned value denotes number of bytes read.
- */
-int32_t audio_codec_wov_read(void *buf, uint32_t count);
-
-/*
- * Enables notification if WoV audio data is available.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has enabled.
- *   EC_ERROR_ACCESS_DENIED if the notifiee has not set.
- */
-int audio_codec_wov_enable_notifier(void);
-
-/*
- * Disables WoV data notification.
- *
- * Returns:
- *   EC_SUCCESS if success.
- *   EC_ERROR_UNKNOWN if internal error.
- *   EC_ERROR_BUSY if has not enabled.
- *   EC_ERROR_ACCESS_DENIED if the notifiee has not set.
- */
-int audio_codec_wov_disable_notifier(void);
-
-/*
- * Audio buffer for 2 seconds S16_LE, 16kHz, mono.
- */
-extern uintptr_t audio_codec_wov_audio_buf_addr;
-
-/*
- * Language model buffer for speech-micro.  At least 67KB.
- */
-extern uintptr_t audio_codec_wov_lang_buf_addr;
-
-/*
- * Task for running WoV.
- */
-void audio_codec_wov_task(void *arg);
-
-#endif
diff --git a/include/backlight.h b/include/backlight.h
deleted file mode 100644
index 1bfafbdd2c..0000000000
--- a/include/backlight.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Backlight API for Chrome EC */
-
-#ifndef __CROS_EC_BACKLIGHT_H
-#define __CROS_EC_BACKLIGHT_H
-
-#include "common.h"
-#include "gpio.h"
-
-/**
- * Interrupt handler for backlight.
- *
- * @param signal	Signal which triggered the interrupt.
- */
-#ifdef CONFIG_BACKLIGHT_REQ_GPIO
-void backlight_interrupt(enum gpio_signal signal);
-#else
-static inline void backlight_interrupt(enum gpio_signal signal) { }
-#endif /* !CONFIG_BACKLIGHT_REQ_GPIO */
-
-/**
- * Activate/Deactivate the backlight GPIO pin considering active high or low.
- */
-void enable_backlight(int enabled);
-
-#endif  /* __CROS_EC_BACKLIGHT_H */
diff --git a/include/base32.h b/include/base32.h
deleted file mode 100644
index ac04ce9c70..0000000000
--- a/include/base32.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Base-32 encoding/decoding, designed for manual operator entry. */
-
-#ifndef __CROS_EC_BASE32_H
-#define __CROS_EC_BASE32_H
-
-/* Symbol map for base32 encoding */
-extern const char base32_map[33];
-
-/**
- * CRC-5-USB Initially created for USB Token Packets. It uses
- * the generator polynomial X^5 + X^2 + X^0 and is 5-bits.
- *
- * @param sym		New symbol to update CRC with
- * @param previous_crc	Existing CRC value
- * @return The updated CRC.
- */
-uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc);
-
-/**
- * base32-encode data into a null-terminated string
- *
- * Uses A-Z0-9 encoding, skipping I,O,0,1 since they're easy to get mixed up.
- *
- * @param dest			Destination buffer; set to empty string on
- *				error
- * @param destlen_chars		Length of destination buffer in characters
- * @param src			Source binary data
- * @param srclen_bits		Length of source *in bits*.  If this is not a
- *				multiple of 8, the *most significant* bits of
- *				the last byte will be used.  If this is not a
- *				multiple of 5, the least significant bits of
- *				the last symbol will be padded with 0 bits.
- * @param add_crc_every		If non-zero, add a CRC symbol after each group
- *				of this many symbols.  There must be an exact
- *				number of groups; that is, ceil(srclen_bits/5)
- *				must be a multiple of add_crc_every.
- * @return EC_SUCCESS, or non-zero error code.
- */
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every);
-
-/**
- * base32-decode data from a null-terminated string
- *
- * Ignores whitespace and '-' dashes in the source string.
- *
- * If the destination is smaller than the decoded bitstream, only that many
- * bits will be decoded.  This is useful for decoding the first part of a
- * bitstream to look for a struct version.
- *
- * If the destination is larger than the decoded bitstream, check the return
- * value to determine how many bits were decoded from the source.  Note that if
- * padding was added by base32_encode (that is, the input length was not a
- * multiple of 5 bits), the padding will be included in the count.
- *
- * @param dest			Destination; must be at least
- *				ceil(destlen_bits/8) bytes.
- * @param destlen_bits		Length of destination *in bits*.
- * @param src			Source string (null-terminated)
- * @param crc_after_every	If non-zero, expect CRC symbol after every
- *				group of this many symbols.
- * @return Number of decoded *bits*, or -1 if error.
- */
-int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
-		  int crc_after_every);
-
-#endif
diff --git a/include/base_state.h b/include/base_state.h
deleted file mode 100644
index d8c72e5663..0000000000
--- a/include/base_state.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-
-/**
- * Return 1 if base attached, 0 otherwise.
- */
-int base_get_state(void);
-
-/**
- * Sets the current state of the base, with 0 meaning detached,
- * and non-zero meaning attached.
- */
-void base_set_state(int state);
-
-/**
- * Call board specific base_force_state function.
- * Force the current state of the base, with 0 meaning detached,
- * 1 meaning attached and 2 meaning reset to the original state.
- */
-void base_force_state(enum ec_set_base_state_cmd state);
diff --git a/include/battery_bq27621_g1.h b/include/battery_bq27621_g1.h
deleted file mode 100644
index 0c388d8a52..0000000000
--- a/include/battery_bq27621_g1.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery driver for BQ27621-G1
- */
-
-/* Sets percent to the battery life as a percentage (0-100)
- *
- * Returns EC_SUCCESS on success.
- */
-int bq27621_state_of_charge(int *percent);
-
-/* Initializes the fuel gauge with the constants for the battery.
- *
- * Returns EC_SUCCESS on success.
- */
-int bq27621_init(void);
-
diff --git a/include/battery_fuel_gauge.h b/include/battery_fuel_gauge.h
deleted file mode 100644
index eb54b64c53..0000000000
--- a/include/battery_fuel_gauge.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery fuel gauge parameters
- */
-
-#ifndef __CROS_EC_BATTERY_FUEL_GAUGE_H
-#define __CROS_EC_BATTERY_FUEL_GAUGE_H
-
-#include "battery.h"
-#include <stdbool.h>
-
-/* Number of writes needed to invoke battery cutoff command */
-#define SHIP_MODE_WRITES 2
-
-struct ship_mode_info {
-	/*
-	 * Write Block Support. If wb_support is true, then we use a i2c write
-	 * block command instead of a 16-bit write. The effective difference is
-	 * that the i2c transaction will prefix the length (2) when wb_support
-	 * is enabled.
-	 */
-	const uint8_t wb_support;
-	const uint8_t reg_addr;
-	const uint16_t reg_data[SHIP_MODE_WRITES];
-};
-
-struct sleep_mode_info {
-	const bool sleep_supported;
-	const uint8_t reg_addr;
-	const uint16_t reg_data;
-};
-
-struct fet_info {
-	const int mfgacc_support;
-	const uint8_t reg_addr;
-	const uint16_t reg_mask;
-	const uint16_t disconnect_val;
-	const uint16_t cfet_mask; /* CHG FET status mask */
-	const uint16_t cfet_off_val;
-};
-
-struct fuel_gauge_info {
-	const char *manuf_name;
-	const char *device_name;
-	const uint8_t override_nil;
-	const struct ship_mode_info ship_mode;
-	const struct sleep_mode_info sleep_mode;
-	const struct fet_info fet;
-
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-	/* See battery_*_imbalance_mv() for functions which are suitable. */
-	int (*imbalance_mv)(void);
-#endif
-};
-
-struct board_batt_params {
-	const struct fuel_gauge_info fuel_gauge;
-	const struct battery_info batt_info;
-};
-
-/* Forward declare board specific data used by common code */
-extern const struct board_batt_params board_battery_info[];
-extern const enum battery_type DEFAULT_BATTERY_TYPE;
-
-
-#ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
-/**
- * Report the absolute difference between the highest and lowest cell voltage in
- * the battery pack, in millivolts.  On error or unimplemented, returns '0'.
- */
-int battery_default_imbalance_mv(void);
-
-#ifdef CONFIG_BATTERY_BQ4050
-int battery_bq4050_imbalance_mv(void);
-#endif
-
-#endif
-
-/**
- * Return the board-specific default battery type.
- *
- * @return a value of `enum battery_type`.
- */
-__override_proto int board_get_default_battery_type(void);
-
-/**
- * Return 1 if CFET is disabled, 0 if enabled. -1 if an error was encountered.
- * If the CFET mask is not defined, it will return 0.
- */
-int battery_is_charge_fet_disabled(void);
-
-/**
- * Battery cut off command via SMBus write block.
- *
- * @param ship_mode		Battery ship mode information
- * @return non-zero if error
- */
-int cut_off_battery_block_write(const struct ship_mode_info *ship_mode);
-
-/**
- * Battery cut off command via SMBus write word.
- *
- * @param ship_mode		Battery ship mode information
- * @return non-zero if error
- */
-int cut_off_battery_sb_write(const struct ship_mode_info *ship_mode);
-
-/**
- * Send the fuel gauge sleep command through SMBus.
- *
- * @return	0 if successful, non-zero if error occurred
- */
-enum ec_error_list battery_sleep_fuel_gauge(void);
-
-#endif /* __CROS_EC_BATTERY_FUEL_GAUGE_H */
diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h
deleted file mode 100644
index 286653dda6..0000000000
--- a/include/bluetooth_le.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Bluetooth LE packet formats, etc. */
-
-/*
- * Since the fields are all little endian,
- *
- * uint16_t two_octets;
- *
- * is used in place of
- *
- * uint8_t two_single_octets[2];
- *
- * in many places.
- */
-
-#ifndef __CROS_EC_BLE_H
-#define __CROS_EC_BLE_H
-
-#include "common.h"
-#include "util.h"
-
-#define BLUETOOTH_ADDR_OCTETS                   6
-
-/*
- * GAP assigned numbers
- * https://www.bluetooth.org/en-us/specification/
- * assigned-numbers/generic-access-profile
- */
-#define GAP_FLAGS                               0x01
-#define GAP_INCOMP_16_BIT_UUID                  0x02
-#define GAP_COMP_16_BIT_UUID                    0x03
-#define GAP_INCOMP_32_BIT_UUID                  0x04
-#define GAP_COMP_32_BIT_UUID                    0x05
-#define GAP_INCOMP_128_BIT_UUID                 0x06
-#define GAP_COMP_128_BIT_UUID                   0x07
-#define GAP_SHORT_NAME                          0x08
-#define GAP_COMPLETE_NAME                       0x09
-#define GAP_TX_POWER_LEVEL                      0x0A
-#define GAP_CLASS_OF_DEVICE                     0x0D
-#define GAP_SIMPLE_PAIRING_HASH                 0x0E
-#define GAP_SIMPLE_PAIRING_HASH_192             0x0E
-#define GAP_SIMPLE_PAIRING_RAND                 0x0F
-#define GAP_SIMPLE_PAIRING_RAND_192             0x0F
-#define GAP_DEVICE_ID                           0x10
-#define GAP_SECURITY_MANAGER_TK                 0x10
-#define GAP_SECURITY_MANAGER_OOB_FLAGS          0x11
-#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE     0x12
-#define GAP_SERVICE_SOLICITATION_UUID_16        0x14
-#define GAP_SERVICE_SOLICITATION_UUID_32        0x1F
-#define GAP_SERVICE_SOLICITATION_UUID_128       0x15
-#define GAP_SERVICE_DATA                        0x16
-#define GAP_SERVICE_DATA_UUID_16                0x16
-#define GAP_SERVICE_DATA_UUID_32                0x20
-#define GAP_SERVICE_DATA_UUID_128               0x21
-#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION  0x22
-#define GAP_LE_SECURE_CONNECTIONS_RAND          0x23
-#define GAP_PUBLIC_TARGET_ADDRESS               0x17
-#define GAP_RANDOM_TARGET_ADDRESS               0x18
-#define GAP_APPEARANCE                          0x19
-#define GAP_ADVERTISING_INTERVAL                0x1A
-#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B
-#define GAP_LE_ROLE                             0x1C
-#define GAP_SIMPLE_PAIRING_HASH_256             0x1D
-#define GAP_SIMPLE_PAIRING_RAND_256             0x1E
-#define GAP_3D_INFORMATION_DATA                 0x3D
-#define GAP_MANUFACTURER_SPECIFIC_DATA          0xFF
-
-
-/* org.bluetooth.characteristic.gap.appearance.xml */
-#define GAP_APPEARANCE_HID_KEYBOARD             961
-
-/* org.bluetooth.service.human_interface_device.xml */
-#define GATT_SERVICE_HID_UUID                   0x1812
-
-/* Bluetooth Core Supplement v5 */
-
-/* Bluetooth Core Supplement v5 1.3 */
-#define GAP_FLAGS_LE_LIM_DISC   0x01
-#define GAP_FLAGS_LE_GEN_DISC   0x02
-#define GAP_FLAGS_LE_NO_BR_EDR  0x04
-
-/* Bluetooth Core Supplement v5 1.3 */
-
-
-/* BLE 4.1 Vol 6 section 2.3 pg 38+ */
-
-/* Advertising PDU Header
- * 16 Bits:
- *    4 bit type
- *    1 bit TxAddr
- *    1 bit RxAddr
- *    6 bit length (length of the payload in bytes)
- */
-
-struct ble_adv_header {
-	uint8_t type;
-	uint8_t txaddr;
-	uint8_t rxaddr;
-	uint8_t length;
-};
-
-#define BLE_ADV_HEADER_PDU_TYPE_SHIFT    0
-#define BLE_ADV_HEADER_TXADD_SHIFT       6
-#define BLE_ADV_HEADER_RXADD_SHIFT       7
-#define BLE_ADV_HEADER_LENGTH_SHIFT      8
-
-#define BLE_ADV_HEADER(type, tx, rx, length) \
-		((uint16_t) \
-		((((length) & 0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \
-		 (((rx) & 0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \
-		 (((tx) & 0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \
-		 (((type) & 0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT)))
-
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND         0
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND  1
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND 2
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ        3
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP        4
-#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ     5
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND    6
-
-#define BLE_ADV_HEADER_PUBLIC_ADDR    0
-#define BLE_ADV_HEADER_RANDOM_ADDR    1
-
-/* BLE 4.1 Vol 3 Part C 10.8 */
-#define BLE_RANDOM_ADDR_MSBS_PRIVATE             0x00
-#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE  0x40
-#define BLE_RANDOM_ADDR_MSBS_RFU                 0x80
-#define BLE_RANDOM_ADDR_MSBS_STATIC              0xC0
-
-#define BLE_ADV_ACCESS_ADDRESS 0x8E89BED6
-#define BLE_ADV_CRCINIT 0x555555
-
-#define BLE_MAX_ADV_PAYLOAD_OCTETS       37
-
-/* LL SCA Values.  They are shifted left 5 bits for Hop values */
-#define BLE_LL_SCA_251_PPM_TO_500_PPM    (0 << 5)
-#define BLE_LL_SCA_151_PPM_TO_250_PPM    BIT(5)
-#define BLE_LL_SCA_101_PPM_TO_150_PPM    (2 << 5)
-#define BLE_LL_SCA_076_PPM_TO_100_PPM    (3 << 5)
-#define BLE_LL_SCA_051_PPM_TO_075_PPM    (4 << 5)
-#define BLE_LL_SCA_031_PPM_TO_050_PPM    (5 << 5)
-#define BLE_LL_SCA_021_PPM_TO_030_PPM    (6 << 5)
-#define BLE_LL_SCA_000_PPM_TO_020_PPM    (7 << 5)
-
-/* BLE 4.1 Vol 6 section 2.4 pg 45 */
-
-/* Data PDU Header
- * 16 Bits:
- *    2 bit LLID   ( Control or Data )
- *    1 bit NESN   ( Next expected sequence number )
- *    1 bit SN     ( Sequence Number )
- *    1 bit MD     ( More Data )
- *    5 bit length ( length of the payload + MIC in bytes )
- *
- * This struct isn't packed, since it isn't sent to the radio.
- *
- */
-
-struct ble_data_header {
-	uint8_t llid;
-	uint8_t nesn;
-	uint8_t sn;
-	uint8_t md;
-	uint8_t length;
-};
-
-#define BLE_DATA_HEADER_LLID_SHIFT       0
-#define BLE_DATA_HEADER_NESN_SHIFT       2
-#define BLE_DATA_HEADER_SN_SHIFT         3
-#define BLE_DATA_HEADER_MD_SHIFT         4
-#define BLE_DATA_HEADER_LENGTH_SHIFT     8
-
-#define BLE_DATA_HEADER_LLID_DATANOSTART 1
-#define BLE_DATA_HEADER_LLID_DATASTART   2
-#define BLE_DATA_HEADER_LLID_CONTROL     3
-
-#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \
-		((uint16_t) \
-		((((length) & 0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \
-		 (((MD) & 0x1) << BLE_DATA_HEADER_MD_SHIFT) | \
-		 (((SN) & 0x1) << BLE_DATA_HEADER_SN_SHIFT) | \
-		 (((NESN) & 0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \
-		 (((llid) & 0x3) << BLE_DATA_HEADER_LLID_SHIFT)))
-
-#define BLE_MAX_DATA_PAYLOAD_OCTETS      31
-#define BLE_MAX_PAYLOAD_OCTETS           BLE_MAX_ADV_PAYLOAD_OCTETS
-
-union ble_header {
-	struct ble_adv_header adv;
-	struct ble_data_header data;
-};
-
-struct ble_pdu {
-	union ble_header header;
-	uint8_t header_type_adv;
-	uint8_t payload[BLE_MAX_PAYLOAD_OCTETS];
-	uint32_t mic; /* Only included in PDUs with encrypted payloads. */
-};
-
-struct ble_packet {
-	/* uint8_t preamble; */
-	uint32_t access_address;
-	struct ble_pdu pdu;
-	/* uint32_t crc; */
-};
-
-/* LL Control PDU Opcodes BLE 4.1 Vol 6 2.4.2 */
-#define BLE_LL_CONNECTION_UPDATE_REQ     0x00
-#define BLE_LL_CHANNEL_MAP_REQ           0x01
-#define BLE_LL_TERMINATE_IND             0x02
-#define BLE_LL_ENC_REQ                   0x03
-#define BLE_LL_ENC_RSP                   0x04
-#define BLE_LL_START_ENC_REQ             0x05
-#define BLE_LL_START_ENC_RSP             0x06
-#define BLE_LL_UNKNOWN_RSP               0x07
-#define BLE_LL_FEATURE_REQ               0x08
-#define BLE_LL_FEATURE_RSP               0x09
-#define BLE_LL_PAUSE_ENC_REQ             0x0A
-#define BLE_LL_PAUSE_ENC_RSP             0x0B
-#define BLE_LL_VERSION_IND               0x0C
-#define BLE_LL_REJECT_IND                0x0D
-#define BLE_LL_SLAVE_FEATURE_REQ         0x0E
-#define BLE_LL_CONNECTION_PARAM_REQ      0x0F
-#define BLE_LL_CONNECTION_PARAM_RSP      0x10
-#define BLE_LL_REJECT_IND_EXT            0x11
-#define BLE_LL_PING_REQ                  0x12
-#define BLE_LL_PING_RSP                  0x13
-#define BLE_LL_RFU                       0x14
-
-/* BLE 4.1 Vol 6 4.6 Table 4.3 */
-#define BLE_LL_FEATURE_LE_ENCRYPTION     0x00
-#define BLE_LL_FEATURE_CONN_PARAMS_REQ   0x01
-#define BLE_LL_FEATURE_EXT_REJ_IND       0x02
-#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG  0x03
-#define BLE_LL_FEATURE_LE_PING           0x04
-
-struct ble_ll_connection_update_req {
-	uint8_t win_size;
-	uint16_t win_offset;
-	uint16_t interval;
-	uint16_t latency;
-	uint16_t timeout;
-	uint16_t instant;
-} __packed;
-
-struct ble_ll_channel_map_req {
-	uint8_t map[5];
-	uint16_t instant;
-} __packed;
-
-/* ble_ll_terminate_ind: single-byte error code */
-
-struct ble_ll_enc_req {
-	uint8_t rand[8];
-	uint16_t ediv;
-	uint8_t skdm[8];
-	uint8_t ivm[4];
-} __packed;
-
-struct ble_ll_enc_rsp {
-	uint8_t skds[8];
-	uint8_t ivs[4];
-} __packed;
-
-/* ble_ll_start_enc_req has no CtrData field */
-
-/* ble_ll_start_enc_rsp has no CtrData field */
-
-/* ble_ll_unknown_rsp: single-byte error code */
-
-struct ble_ll_feature_req {
-	uint8_t feature_set[8];
-} __packed;
-
-struct ble_ll_feature_rsp {
-	uint8_t feature_set[8];
-} __packed;
-
-/* ble_ll_pause_enc_req has no CtrData field */
-
-/* ble_ll_pause_enc_rsp has no CtrData field */
-
-#define BLE_LL_VERS_NR_4_0     6
-#define BLE_LL_VERS_NR_4_1     7
-
-struct ble_ll_version_ind {
-	uint8_t vers_nr; /* Version Number */
-	uint16_t comp_id; /* Company ID */
-	uint16_t sub_vers_nr; /* Subversion Number */
-} __packed;
-
-/* ble_ll_reject_ind: single-byte error code */
-
-struct ble_ll_slave_feature_req {
-	uint8_t feature_set[8];
-} __packed;
-
-/* ble_ll_connection_param (req and rsp) */
-
-struct ble_ll_connection_param {
-	uint16_t interval_min; /* times 1.25 ms */
-	uint16_t interval_max; /* times 1.25 ms */
-	uint16_t latency; /* connection events */
-	uint16_t timeout; /* times 10 ms */
-	uint8_t preferred_periodicity; /* times 1.25 ms */
-	uint16_t reference_conn_event_count; /* base for offsets*/
-	uint16_t offset0; /* Anchor offset from reference (preferred) */
-	uint16_t offset1;
-	uint16_t offset2;
-	uint16_t offset3;
-	uint16_t offset4;
-	uint16_t offset5; /* least preferred */
-} __packed;
-
-struct ble_ll_reject_ind_ext {
-	uint8_t reject_opcode;
-	uint8_t error_code;
-} __packed;
-
-/* ble_ll_ping_req has no CtrData field */
-
-/* ble_ll_ping_rsp has no CtrData field */
-
-/* BLE 4.1 Vol 6 4.5.8 */
-struct remapping_table {
-	uint8_t remapping_index[37];
-	uint8_t map[5];
-	int num_used_channels;
-	int hop_increment;
-	int last_unmapped_channel;
-};
-
-/* BLE 4.1 Vol 6 4.5.9 */
-struct connection_data {
-	int transmit_seq_num;
-	int next_expected_seq_num;
-	struct remapping_table rt;
-	/* Add timing information */
-};
-
-/* BLE 4.1 Vol 6 1.4.1 */
-int chan2freq(int channel);
-
-/* BLE 4.1 Vol 6 2.3.3.1 */
-void fill_remapping_table(struct remapping_table *rt, uint8_t map[5],
-	int hop_increment);
-
-void ble_tx(struct ble_pdu *pdu);
-
-/**
- * Receive a packet into pdu if one comes before the timeout
- *
- * @param	pdu Where the received data is to be stored
- * @param	timeout Number of microseconds allowed before timeout
- * @param	adv Set to 1 if receiving in advertising state; else set to 0
- * @returns EC_SUCCESS on packet reception, else returns error
- */
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv);
-
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val);
-
-/*
- * Uses the algorithm defined in the BLE core specifcation
- * 4.1 Vol 6 4.5.8 to select the next data channel
- */
-uint8_t get_next_data_channel(struct remapping_table *rt);
-
-/* BLE 4.1 Vol 3 Part C 11 */
-uint8_t *pack_adv(uint8_t *dest, int length, int type, const uint8_t *data);
-uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data);
-uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr);
-
-const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type,
-		    const uint8_t **data);
-
-void dump_ble_addr(uint8_t *mem, char *name);
-
-void dump_ble_packet(struct ble_pdu *ble_p);
-
-/* Radio-specific allow list handling */
-int ble_radio_clear_allow_list(void);
-int ble_radio_read_allow_list_size(uint8_t *ret_size);
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t rand);
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t rand);
-
-#endif /* __CROS_EC_BLE_H */
diff --git a/include/bluetooth_le_ll.h b/include/bluetooth_le_ll.h
deleted file mode 100644
index 9f540102da..0000000000
--- a/include/bluetooth_le_ll.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "btle_hci_int.h"
-
-enum ll_state_t {
-	UNINITIALIZED,
-	STANDBY,
-	SCANNING,
-	ADVERTISING,
-	INITIATING,
-	CONNECTION,
-	TEST_RX,
-	TEST_TX,
-};
-
-#define LL_ADV_INTERVAL_UNIT_US       625
-#define LL_ADV_TIMEOUT_UNIT_US        1000000
-
-#define LL_ADV_DIRECT_INTERVAL_US     3750    /* 3.75 ms */
-#define LL_ADV_DIRECT_TIMEOUT_US      1280000 /* 1.28 s */
-
-#define LL_MAX_DATA_PACKET_LENGTH     27
-#define LL_MAX_DATA_PACKETS           4
-
-/* BTLE Spec 4.0: Vol 6, Part B, Section 4.5.3 */
-#define TRANSMIT_WINDOW_OFFSET_CONSTANT	1250
-
-#define LL_MAX_BUFFER_SIZE  (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS)
-
-#define LL_SUPPORTED_FEATURES (HCI_LE_FTR_ENCRYPTION | \
-	HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \
-	HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \
-	HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE)
-
-#define LL_SUPPORTED_STATES (HCI_LE_STATE_NONCON_ADV | \
-	HCI_LE_STATE_SCANNABLE_ADV | \
-	HCI_LE_STATE_CONNECTABLE_ADV | \
-	HCI_LE_STATE_DIRECT_ADV | \
-	HCI_LE_STATE_PASSIVE_SCAN | \
-	HCI_LE_STATE_ACTIVE_SCAN | \
-	HCI_LE_STATE_INITIATE | \
-	HCI_LE_STATE_SLAVE)
-
-/*
- * 4.6.1 LE Encryption
- * A controller that supports LE Encryption shall support the following sections
- * within this document:
- * - LL_ENC_REQ (Section 2.4.2.4)
- * - LL_ENC_RSP (Section 2.4.2.5)
- * - LL_START_ENC_REQ (Section 2.4.2.6)
- * - LL_START_ENC_RSP (Section 2.4.2.7)
- * - LL_PAUSE_ENC_REQ (Section 2.4.2.11)
- * - LL_PAUSE_ENC_RSP (Section 2.4.2.12)
- * - Encryption Start Procedure (Section 5.1.3.1)
- * - Encryption Pause Procedure (Section 5.1.3.2)
- */
-
-/*Link Layer Control PDU Opcodes */
-#define LL_CONNECTION_UPDATE_REQ  0x00
-#define LL_CHANNEL_MAP_REQ        0x01
-#define LL_TERMINATE_IND          0x02
-#define LL_ENC_REQ                0x03
-#define LL_ENC_RSP                0x04
-#define LL_START_ENC_REQ          0x05
-#define LL_START_ENC_RSP          0x06
-#define LL_UNKNOWN_RSP            0x07
-#define LL_FEATURE_REQ            0x08
-#define LL_FEATURE_RSP            0x09
-#define LL_PAUSE_ENC_REQ          0x0A
-#define LL_PAUSE_ENC_RSP          0x0B
-#define LL_VERSION_IND            0x0C
-#define LL_REJECT_IND             0x0D
-#define LL_SLAVE_FEATURE_REQ      0x0E
-#define LL_CONNECTION_PARAM_REQ   0x0F
-#define LL_CONNECTION_PARAM_RSP   0x10
-#define LL_REJECT_IND_EXT         0x11
-#define LL_PING_REQ               0x12
-#define LL_PING_RSP               0x13
-
-/* BLE 4.1 Vol 6 2.3.3.1 Connection information */
-#define CONNECT_REQ_INITA_LEN					6
-#define CONNECT_REQ_ADVA_LEN					6
-#define CONNECT_REQ_ACCESS_ADDR_LEN				4
-#define CONNECT_REQ_CRC_INIT_VAL_LEN				3
-#define CONNECT_REQ_WIN_SIZE_LEN				1
-#define CONNECT_REQ_WIN_OFFSET_LEN				2
-#define CONNECT_REQ_INTERVAL_LEN				2
-#define CONNECT_REQ_LATENCY_LEN					2
-#define CONNECT_REQ_TIMEOUT_LEN					2
-#define CONNECT_REQ_CHANNEL_MAP_LEN				5
-#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN			1
-struct ble_connection_params {
-	uint8_t		init_a[CONNECT_REQ_INITA_LEN];
-	uint8_t		adv_a[CONNECT_REQ_ADVA_LEN];
-	uint32_t	access_addr;
-	uint32_t	crc_init_val;
-	uint8_t		win_size;
-	uint16_t	win_offset;
-	uint16_t	interval;
-	uint16_t	latency;
-	uint16_t	timeout;
-	uint64_t	channel_map;
-	uint8_t		hop_increment;
-	uint8_t		sleep_clock_accuracy;
-	uint32_t	transmitWindowOffset;
-	uint32_t	transmitWindowSize;
-	uint32_t	connInterval;
-	uint16_t	connLatency;
-	uint32_t	connSupervisionTimeout;
-};
-
-uint8_t ll_reset(void);
-
-uint8_t ll_set_tx_power(uint8_t *params);
-
-
-/* LE Information */
-uint8_t ll_read_buffer_size(uint8_t *return_params);
-uint8_t ll_read_local_supported_features(uint8_t *return_params);
-uint8_t ll_read_supported_states(uint8_t *return_params);
-uint8_t ll_set_host_channel_classification(uint8_t *params);
-
-/* Advertising */
-uint8_t ll_set_advertising_params(uint8_t *params);
-uint8_t ll_read_tx_power(void);
-uint8_t ll_set_adv_data(uint8_t *params);
-uint8_t ll_set_scan_response_data(uint8_t *params);
-uint8_t ll_set_advertising_enable(uint8_t *params);
-
-uint8_t ll_set_random_address(uint8_t *params);
-
-/* Scanning */
-uint8_t ll_set_scan_enable(uint8_t *params);
-uint8_t ll_set_scan_params(uint8_t *params);
-
-/* Allow List */
-uint8_t ll_clear_allow_list(void);
-uint8_t ll_read_allow_list_size(uint8_t *return_params);
-uint8_t ll_add_device_to_allow_list(uint8_t *params);
-uint8_t ll_remove_device_from_allow_list(uint8_t *params);
-
-/* Connections */
-uint8_t ll_read_remote_used_features(uint8_t *params);
-
-/* RF Phy Testing */
-uint8_t ll_receiver_test(uint8_t *params);
-uint8_t ll_transmitter_test(uint8_t *params);
-uint8_t ll_test_end(uint8_t *return_params);
-
-void ll_ble_test_rx(void);
-void ll_ble_test_rx(void);
diff --git a/include/btle_hci2.h b/include/btle_hci2.h
deleted file mode 100644
index 0b30a0dc48..0000000000
--- a/include/btle_hci2.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Copied from NewBlue hci.c with permission from Dmitry Grinberg, the original
- * author.
- */
-
-#include "btle_hci_int.h"
-
-struct hciCmdHdr {
-	uint16_t opcode;
-	uint8_t paramLen;
-} __packed;
-#define CMD_MAKE_OPCODE(ogf, ocf) ((((uint16_t)((ogf) & 0x3f)) << 10) | ((ocf) & 0x03ff))
-#define CMD_GET_OGF(opcode)       (((opcode) >> 10) & 0x3f)
-#define CMD_GET_OCF(opcode)       ((opcode) & 0x03ff)
-
-
-struct hciAclHdr {
-	uint16_t hdr;
-	uint16_t len;
-} __packed;
-#define ACL_HDR_MASK_CONN_ID      0x0FFF
-#define ACL_HDR_MASK_PB           0x3000
-#define ACL_HDR_MASK_BC           0xC000
-#define ACL_HDR_PB_FIRST_NONAUTO  0x0000
-#define ACL_HDR_PB_CONTINUED      0x1000
-#define ACL_HDR_PB_FIRST_AUTO     0x2000
-#define ACL_HDR_PB_COMPLETE       0x3000
-
-struct hciScoHdr {
-	uint16_t hdr;
-	uint8_t len;
-} __packed;
-#define SCO_HDR_MASK_CONN_ID      0x0FFF
-#define SCO_HDR_MASK_STATUS       0x3000
-#define SCO_STATUS_ALL_OK         0x0000
-#define SCO_STATUS_UNKNOWN        0x1000
-#define SCO_STATUS_NO_DATA        0x2000
-#define SCO_STATUS_SOME_DATA      0x3000
-
-struct hciEvtHdr {
-	uint8_t code;
-	uint8_t len;
-} __packed;
-
-
-void hci_cmd(uint8_t *hciCmdbuf);
-void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len);
-void hci_acl_from_host(uint8_t *hciAclbuf);
-void hci_event(uint8_t event_code, uint8_t len, uint8_t *params);
-
diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h
deleted file mode 100644
index ba0b3e6041..0000000000
--- a/include/btle_hci_int.h
+++ /dev/null
@@ -1,3156 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Copied from NewBlue hci_int.h with permission from Dmitry Grinberg, the
- * original author.
- */
-
-
-#ifndef _HCI_INT_H_
-#define _HCI_INT_H_
-
-#include "util.h"
-#define HCI_DEV_NAME_LEN        248
-
-#define HCI_INQUIRY_LENGTH_UNIT                                  1280 /* msec */
-#define HCI_INQUIRY_LENGTH_MAX                                   48 /* units */
-
-#define HCI_LAP_Unlimited_Inquiry                                0x9E8B33
-#define HCI_LAP_Limited_Inquiry                                  0x9E8B00
-
-#define HCI_CLOCK_OFST_VALID                                     0x8000
-
-#define HCI_PKT_TYP_NO_2_DH1                                     0x0002 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH1                                     0x0004 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM1                                          0x0008 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH1                                          0x0010 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH3                                     0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH3                                     0x0200 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM3                                          0x0400 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH3                                          0x0800 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM5                                          0x4000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH5                                          0x8000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DEFAULT                                      0xCC18
-
-#define HCI_PKT_TYP_SCO_HV1                                      0x0001 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV2                                      0x0002 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV3                                      0x0004 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_EV3                                      0x0008 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV4                                      0x0010 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV5                                      0x0020 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV3                                 0x0040 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV3                                 0x0080 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV5                                 0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV5                                 0x0200 /* BT 2.1+ */
-
-#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES                     0x0000
-#define HCI_LINK_POLICY_ENABLE_ROLESWITCH                        0x0001
-#define HCI_LINK_POLICY_ENABLE_HOLD_MODE                         0x0002
-#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE                        0x0004
-#define HCI_LINK_POLICY_ENABLE_PARK_MODE                         0x0008
-
-#define HCI_FILTER_TYPE_CLEAR_ALL                                0x00 /* no subtypes, no data */
-#define HCI_FILTER_INQUIRY_RESULT                                0x01 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS                     0x00 /* no data */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS                    0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class) */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR                       0x02 /* uint8_t mac[6] */
-#define HCI_FILTER_CONNECTION_SETUP                              0x02 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS           0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 - yes w/ roleswitch */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS   0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class), auto_accept flag same as above */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR      0x02 /* uint8_t mac[6], auto_accept flag same as above */
-
-#define HCI_SCAN_ENABLE_INQUIRY                                  0x01 /* discoverable */
-#define HCI_SCAN_ENABLE_PAGE                                     0x02 /* connectable */
-
-#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN                          0x01
-#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN                       0x02
-#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES                 0x04
-
-#define HCI_TO_HOST_FLOW_CTRL_ACL                                0x01
-#define HCI_TO_HOST_FLOW_CTRL_SCO                                0x02
-
-#define HCI_INQ_MODE_STD                                         0 /* normal mode @ BT 1.1+ */
-#define HCI_INQ_MODE_RSSI                                        1 /* with RSSI   @ BT 1.2+ */
-#define HCI_INQ_MODE_EIR                                         2 /* with EIR    @ BT 2.1+ */
-
-#define HCI_SSP_KEY_ENTRY_STARTED                                0
-#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED                          1
-#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED                           2
-#define HCI_SSP_KEY_ENTRY_CLEARED                                3
-#define HCI_SSP_KEY_ENTRY_COMPLETED                              4
-
-#define HCI_LOCATION_DOMAIN_OPTION_NONE                          0x20 /* ' ' */
-#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY                 0x4F /* 'O' */
-#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY                  0x49 /* 'I' */
-#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY            0x58 /* 'X' */
-
-#define HCI_PERIOD_TYPE_DOWNLINK                                 0x00
-#define HCI_PERIOD_TYPE_UPLINK                                   0x01
-#define HCI_PERIOD_TYPE_BIDIRECTIONAL                            0x02
-#define HCI_PERIOD_TYPE_GUARD_PERIOD                             0x03
-
-#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX                        0x00
-#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED                         0x01
-#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED                         0x02
-#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED                      0x03
-#define HCI_MWS_INTERVAL_TYPE_FRAME                              0x04 /* type defined by Set External Frame Configuration command */
-
-#define HCI_CONNLESS_FRAG_TYPE_CONT                              0x00 /* continuation fragment */
-#define HCI_CONNLESS_FRAG_TYPE_START                             0x01 /* first fragment */
-#define HCI_CONNLESS_FRAG_TYPE_END                               0x02 /* last fragment */
-#define HCI_CONNLESS_FRAG_TYPE_COMPLETE                          0x03 /* complete fragment - no fragmentation */
-
-#define HCI_CUR_MODE_ACTIVE                                      0x00
-#define HCI_CUR_MODE_HOLD                                        0x01
-#define HCI_CUR_MODE_SNIFF                                       0x02
-#define HCI_CUR_MODE_PARK                                        0x03
-
-#define HCI_SCO_LINK_TYPE_SCO                                    0x00
-#define HCI_SCO_LINK_TYPE_ESCO                                   0x02
-
-#define HCI_SCO_AIR_MODE_MULAW                                   0x00
-#define HCI_SCO_AIR_MODE_ALAW                                    0x01
-#define HCI_SCO_AIR_MODE_CVSD                                    0x02
-#define HCI_SCO_AIR_MODE_TRANSPARENT                             0x03
-
-#define HCI_MCA_500_PPM                                          0x00
-#define HCI_MCA_250_PPM                                          0x01
-#define HCI_MCA_150_PPM                                          0x02
-#define HCI_MCA_100_PPM                                          0x03
-#define HCI_MCA_75_PPM                                           0x04
-#define HCI_MCA_50_PPM                                           0x05
-#define HCI_MCA_30_PPM                                           0x06
-#define HCI_MCA_20_PPM                                           0x07
-
-#define HCI_EDR_LINK_KEY_COMBO                                   0x00
-#define HCI_EDR_LINK_KEY_LOCAL                                   0x01
-#define HCI_EDR_LINK_KEY_REMOTE                                  0x02
-#define HCI_EDR_LINK_KEY_DEBUG                                   0x03
-#define HCI_EDR_LINK_KEY_UNAUTH_COMBO                            0x04
-#define HCI_EDR_LINK_KEY_AUTH_COMBO                              0x05
-#define HCI_EDR_LINK_KEY_CHANGED                                 0x06
-
-#define HCI_VERSION_1_0_B                                         0 /* BT 1.0b */
-#define HCI_VERSION_1_1                                           1 /* BT 1.1  */
-#define HCI_VERSION_1_2                                           2 /* BT 1.2  */
-#define HCI_VERSION_2_0                                           4 /* BT 2.0  */
-#define HCI_VERSION_2_1                                           3 /* BT 2.1  */
-#define HCI_VERSION_3_0                                           4 /* BT 3.0  */
-#define HCI_VERSION_4_0                                           6 /* BT 4.0  */
-#define HCI_VERSION_4_1                                           7 /* BT 4.1  */
-
-#define HCI_LE_STATE_NONCON_ADV                                  0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV                               0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV                             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV                                  0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN                                0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN                                 0x0000000000000020ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INITIATE                                    0x0000000000000040ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SLAVE                                       0x0000000000000080ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN                   0x0000000000000100ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN                0x0000000000000200ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN              0x0000000000000400ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN                   0x0000000000000800ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN                    0x0000000000001000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN                 0x0000000000002000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN               0x0000000000004000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN                    0x0000000000008000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_INITIATING                     0x0000000000010000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING                  0x0000000000020000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_MASTER                         0x0000000000040000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER                      0x0000000000080000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_SLAVE                          0x0000000000100000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE                       0x0000000000200000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING                   0x0000000000400000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING                    0x0000000000800000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER                       0x0000000001000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER                        0x0000000002000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE                        0x0000000004000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE                         0x0000000008000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INTIATING_w_MASTER                          0x0000000010000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV                   0x0000000020000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV    0x0000000040000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV     0x0000000080000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING                0x0000000100000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING                     0x0000000200000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING      0x0000000400000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER                    0x0000000800000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_MASTER                         0x0000001000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER          0x0000002000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE                     0x0000004000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE                          0x0000008000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE           0x0000010000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_INITIATING_w_SLAVE                          0x0000020000000000ULL /* BT 4.1+ */
-
-#define HCI_LMP_FTR_3_SLOT_PACKETS                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_5_SLOT_PACKETS                               0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_ENCRYPTION                                   0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SLOT_OFFSET                                  0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TIMING_ACCURACY                              0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SWITCH                                       0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HOLD_MODE                                    0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SNIFF_MODE                                   0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PARK_MODE                                    0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_RSSI                                         0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE             0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SCO_LINKS                                    0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV2_PACKETS                                  0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV3_PACKETS                                  0x0000000000002000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_MU_LAW                                       0x0000000000004000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_A_LAW                                        0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CVSD                                         0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PAGING_SCHEME                                0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_POWER_CONTROL                                0x0000000000040000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA                         0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0                          0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1                          0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2                          0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_BROADCAST_ENCRYPTION                         0x0000000000800000ULL /* BT 1.2+ */
-#define HCI_LMP_FTR_ACL_2MBPS                                    0x0000000002000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ACL_3MBPS                                    0x0000000004000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN                        0x0000000008000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN                      0x0000000010000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN                         0x0000000020000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS                    0x0000000040000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_SCO_LINK                            0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */
-#define HCI_LMP_FTR_EV4_PACKETS                                  0x0000000100000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EV5_PACKETS                                  0x0000000200000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE                            0x0000000800000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE                     0x0000001000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED                         0x0000002000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER                      0x0000004000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS                           0x0000008000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS                           0x0000010000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SNIFF_SUBRATING                              0x0000020000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_PAUSE_ENCRYPTION                             0x0000040000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_MASTER                           0x0000080000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER                    0x0000100000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_2MBPS                                   0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_3MBPS                                   0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_3_SLOT_ESCO                                  0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE                    0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SSP                                          0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENCAPSULATED_PDU                             0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING                     0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG           0x0040000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT       0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL              0x0200000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_FEATURES                            0x8000000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL                       0x0400000000000000ULL /* BT 3.0+ */
-#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER              0x0002000000000000ULL /* BT 4.0+ */
-
-#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT                      0x0000000000000001ULL /* BT 2.1+ */
-#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT                       0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT       0x0000000000000008ULL /* BT 4.1+ */
-
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER       0x0000000000000001ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE        0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN                 0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN                  0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT     0x0000000000000010ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN           0x0000000000000020ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT               0x0000000000000040ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER 0x0000000000000100ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_PING                                  0x0000000000000200ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING                         0x0000000000000800ULL /* BT 4.1+ */
-
-#define HCI_EVENT_INQUIRY_COMPLETE                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_EVENT_INQUIRY_RESULT                                 0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_COMPLETE                                  0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_REQUEST                                   0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_EVENT_DISCONNECTION_COMPLETE                         0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_EVENT_AUTH_COMPLETE                                  0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE                   0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_EVENT_ENCR_CHANGE                                    0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE                  0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE                       0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE        0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE              0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_SETUP_COMPLETE                             0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_EVENT_HARDWARE_ERROR                                 0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_EVENT_FLUSH_OCCURRED                                 0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_EVENT_ROLE_CHANGE                                    0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_EVENT_MODE_CHANGE                                    0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_EVENT_RETURN_LINK_KEYS                               0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_EVENT_PIN_CODE_REQUEST                               0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_REQUEST                               0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_NOTIFICATION                          0x0000000000800000ULL /* BT 1.1+ */
-#define HCI_EVENT_LOOPBACK_COMMAND                               0x0000000001000000ULL /* BT 1.1+ */
-#define HCI_EVENT_DATA_BUFFER_OVERFLOW                           0x0000000002000000ULL /* BT 1.1+ */
-#define HCI_EVENT_MAX_SLOTS_CHANGE                               0x0000000004000000ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE                     0x0000000008000000ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED                       0x0000000010000000ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_VIOLATION                                  0x0000000020000000ULL /* BT 1.1+ */
-#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE                          0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */
-#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE               0x0000000080000000ULL /* BT 1.1+ */
-#define HCI_EVENT_ALL_BT_1_1                                     0x00000000FFFFFFFFULL /* also the default for BT 1.1 */
-#define HCI_EVENT_FLOW_SPEC_COMPLETE                             0x0000000100000000ULL /* BT 1.2+ */
-#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI                       0x0000000200000000ULL /* BT 1.2+ */
-#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE         0x0000000400000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_COMPLETE                             0x0000080000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_CHANGED                              0x0000100000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_ALL_BT_1_2                                     0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */
-#define HCI_EVENT_SNIFF_SUBRATING                                0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_EXTENDED_INQUIRY_RESULT                        0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE                      0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST                          0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY                    0x0002000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_CONFIRMATION_REQUEST                      0x0004000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_REQUEST                           0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST                        0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE                        0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED                0x0080000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE                        0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_NOTIFICATION                      0x0400000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_KEYPRESS_NOTIFICATION                          0x0800000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES                 0x1000000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ALL_BT_2_1                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_3_0                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_LE_META                                        0x2000000000000000ULL /* BT 4.0+ */
-#define HCI_EVENT_ALL_BT_4_0                                     0x3DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_4_1                                     0x3DBFFFFFFFFFFFFFULL
-
-#define HCI_EVENT_P2_PHYS_LINK_COMPLETE                          0x0000000000000001ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_CHANNEL_SELECTED                            0x0000000000000002ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK                 0x0000000000000004ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING            0x0000000000000008ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY                      0x0000000000000010ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE                       0x0000000000000020ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE         0x0000000000000040ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE                   0x0000000000000080ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS             0x0000000000000100ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_START_TEST                              0x0000000000000200ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_TEST_END                                0x0000000000000400ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_RECEIVER_REPORT                         0x0000000000000800ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE            0x0000000000001000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_STATUS_CHANGE                           0x0000000000002000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_ALL_BT_3_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_ALL_BT_4_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE                     0x0000000000004000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE                        0x0000000000008000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED                        0x0000000000010000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED               0x0000000000020000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT            0x0000000000040000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE                     0x0000000000080000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT                 0x0000000000100000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE 0x0000000000200000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION               0x0000000000400000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED       0x0000000000800000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_ALL_BT_4_1                                  0x0000000000FFFFFFULL
-
-#define HCI_LE_EVENT_CONN_COMPLETE                               0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_ADV_REPORT                                  0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE                        0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE           0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_LTK_REQUEST                                 0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST         0x0000000000000020ULL /* BT 4.1+ */
-
-#define HCI_LE_FTR_ENCRYPTION                                    0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST                 0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION                    0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE             0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LE_FTR_LE_PING                                       0x0000000000000010ULL /* BT 4.1+ */
-
-
-
-
-
-#define HCI_OGF_Link_Control                                     1
-
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_CMD_Inquiry                                          0x0001 /* status */
-struct hciInquiry {
-	uint8_t lap[3];
-	uint8_t inqLen;
-	uint8_t numResp;
-} __packed;
-
-#define HCI_CMD_Inquiry_Cancel                                   0x0002 /* complete */
-struct hciCmplInquiryCancel {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Periodic_Inquiry_Mode                            0x0003 /* complete */
-struct hciPeriodicInquiryMode {
-	uint16_t maxPeriodLen;
-	uint16_t minPeriodLen;
-	uint8_t lap[3];
-	uint8_t inqLen;
-	uint8_t numResp;
-} __packed;
-struct hciCmplPeriodicInquiryMode {
-	uint8_t status;
-} __packed;
-
-
-#define HCI_CMD_Exit_Periodic_Inquiry_Mode                       0x0004 /* complete */
-
-#define HCI_CMD_Create_Connection                                0x0005 /* status */
-struct hciCreateConnection {
-	uint8_t mac[6];
-	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
-	uint8_t PSRM;
-	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
-	uint8_t allowRoleSwitch;
-} __packed;
-
-#define HCI_CMD_Disconnect                                       0x0006 /* status */
-struct hciDisconnect {
-	uint16_t conn;
-	uint8_t reason;
-} __packed;
-
-#define HCI_CMD_Add_SCO_Connection                               0x0007 /* status */ /* deprecated in BT 1.2+ */
-struct hciAddScoConnection {
-	uint16_t conn;
-	uint16_t packetTypes; /* HCI_PKT_TYP_SCO_* */
-} __packed;
-
-#define HCI_CMD_Create_Connection_Cancel                         0x0008 /* complete */
-struct hciCreateConnectionCancel {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplCreateConnectionCancel {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Accept_Connection_Request                        0x0009 /* status */
-struct hciAcceptConnection {
-	uint8_t mac[6];
-	uint8_t remainSlave;
-} __packed;
-
-#define HCI_CMD_Reject_Connection_Request                        0x000A /* status */
-struct hciRejectConnection {
-	uint8_t mac[6];
-	uint8_t reason;
-} __packed;
-
-#define HCI_CMD_Link_Key_Request_Reply                           0x000B /* complete */
-struct hciLinkKeyRequestReply {
-	uint8_t mac[6];
-	uint8_t key[16];
-} __packed;
-struct hciCmplLinkKeyRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Link_Key_Request_Negative_Reply                  0x000C /* complete */
-struct hciLinkKeyRequestNegativeReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplLinkKeyRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_PIN_Code_Request_Reply                           0x000D /* complete */
-struct hciPinCodeRequestReply {
-	uint8_t mac[6];
-	uint8_t pinCodeLen;
-	uint8_t pinCode[16];
-} __packed;
-struct hciCmplPinCodeRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_PIN_Code_Request_Negative_Reply                  0x000E /* complete */
-struct hciPinCodeRequestNegativeReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplPinCodeRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Change_Connection_Packet_Type                    0x000F /* status */
-struct hciChangeConnectionPacketType {
-	uint16_t conn;
-	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
-} __packed;
-
-#define HCI_CMD_Authentication_Requested                         0x0011 /* status */
-struct hciAuthRequested {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Set_Connection_Encryption                        0x0013 /* status */
-struct hciSetConnectionEncryption {
-	uint16_t conn;
-	uint8_t encrOn;
-} __packed;
-
-#define HCI_CMD_Change_Connection_Link_Key                       0x0015 /* status */
-struct hciChangeConnLinkKey {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Master_Link_Key                                  0x0017 /* status */
-struct hciMasterLinkKey {
-	uint8_t useTempKey;
-} __packed;
-
-#define HCI_CMD_Remote_Name_Request                              0x0019 /* status */
-struct hciRemoteNameRequest {
-	uint8_t mac[6];
-	uint8_t PSRM;
-	uint8_t PSM; /* deprecated, should be zero for BT 1.2+ */
-	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
-} __packed;
-
-#define HCI_CMD_Remote_Name_Request_Cancel                       0x001A /* complete */
-struct hciRemoteNameRequestCancel {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplRemoteNameRequestCancel {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Read_Remote_Supported_Features                   0x001B /* status */
-struct hciReadRemoteSupportedFeatures {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Remote_Version_Information                  0x001D /* status */
-struct hciReadRemoteVersionInfo {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Clock_Offset                                0x001F /* status */
-struct hciReadClockOffset {
-	uint16_t conn;
-} __packed;
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_CMD_Read_Remote_Extended_Features                    0x001C /* status */
-struct hciReadRemoteExtendedFeatures {
-	uint16_t conn;
-	uint8_t page; /* BT1.2 max: 0 */
-} __packed;
-
-#define HCI_CMD_Read_Lmp_Handle                                  0x0020 /* complete */
-struct hciReadLmpHandle {
-	uint16_t handle;
-} __packed;
-struct hciCmplReadLmpHandle {
-	uint8_t status;
-	uint16_t handle;
-	uint8_t lmpHandle;
-	uint32_t reserved;
-} __packed;
-
-#define HCI_CMD_Setup_Synchronous_Connection                     0x0028 /* status */
-struct hciSetupSyncConn {
-	uint16_t conn;
-	uint32_t txBandwidth;
-	uint32_t rxBandwidth;
-	uint16_t maxLatency;
-	uint16_t voiceSetting;
-	uint8_t retransmissionEffort;
-	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
-} __packed;
-
-#define HCI_CMD_Accept_Synchronous_Connection_Request            0x0029 /* status */
-struct hciAcceptSyncConn {
-	uint8_t mac[6];
-	uint32_t txBandwidth;
-	uint32_t rxBandwidth;
-	uint16_t maxLatency;
-	uint16_t contentFormat;
-	uint8_t retransmissionEffort;
-	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
-} __packed;
-
-#define HCI_CMD_Reject_Synchronous_Connection_Request            0x002A /* status */
-struct hciRejectSyncConn {
-	uint8_t mac[6];
-	uint8_t reason;
-} __packed;
-
-
-/* ==== BR 2.1 ==== */
-
-#define HCI_CMD_IO_Capability_Request_Reply                      0x002B /* complete */
-struct hciIoCapabilityRequestReply {
-	uint8_t mac[6];
-	uint8_t cap; /* HCI_DISPLAY_CAP_* */
-	uint8_t oobPresent;
-	uint8_t authReqments; /* HCI_AUTH_REQMENT_* */
-} __packed;
-struct hciCmplIoCapabilityRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_User_Confirmation_Request_Reply                  0x002C /* complete */
-struct hciUserConfRequestReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplUserConfRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_User_Confirmation_Request_Negative_Reply         0x002D /* complete */
-struct hciUserConfRequestNegativeReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplUserConfRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_User_Passkey_Request_Reply                       0x002E /* complete */
-struct hciUserPasskeyRequestReply {
-	uint8_t mac[6];
-	uint32_t num;
-} __packed;
-struct hciCmplUserPasskeyRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_User_Passkey_Request_Negative_Reply              0x002F /* complete */
-struct hciUserPasskeyRequestNegativeReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplUserPasskeyRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Remote_OOB_Data_Request_Reply                    0x0030 /* complete */
-struct hciRemoteOobDataRequestReply {
-	uint8_t mac[6];
-	uint8_t C[16];
-	uint8_t R[16];
-} __packed;
-struct hciCmplRemoteOobDataRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply           0x0033 /* complete */
-struct hciRemoteOobDataRequestNegativeReply {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplRemoteOobDataRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_IO_Capability_Request_Negative_Reply             0x0034 /* complete */
-struct hciIoCapabilityRequestNegativeReply {
-	uint8_t mac[6];
-	uint8_t reason;
-} __packed;
-struct hciCmplIoCapabilityRequestNegativeReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_CMD_Create_Physical_link                             0x0035 /* status */
-struct hciCreatePhysicalLink {
-	uint8_t physLinkHandle;
-	uint8_t dedicatedAmpKeyLength;
-	uint8_t dedicatedAmpKeyType;
-	uint8_t dedicatedAmpKey;
-} __packed;
-
-#define HCI_CMD_Accept_Physical_link                             0x0036 /* status */
-struct hciAcceptPhysicalLink {
-	uint8_t physLinkHandle;
-	uint8_t dedicatedAmpKeyLength;
-	uint8_t dedicatedAmpKeyType;
-	uint8_t dedicatedAmpKey;
-} __packed;
-
-#define HCI_CMD_Disconnect_Physical_link                         0x0037 /* status */
-struct hciDisconnectPhysicalLink {
-	uint8_t physLinkHandle;
-	uint8_t reason;
-} __packed;
-
-#define HCI_CMD_Create_Logical_link                              0x0038 /* status */
-struct hciCreateLogicalLink {
-	uint8_t physLinkHandle;
-	uint8_t txFlowSpec[16];
-	uint8_t rxFlowSpec[16];
-} __packed;
-
-#define HCI_CMD_Accept_Logical_Link                              0x0039 /* status */
-struct hciAcceptLogicalLink {
-	uint8_t physLinkHandle;
-	uint8_t txFlowSpec[16];
-	uint8_t rxFlowSpec[16];
-} __packed;
-
-#define HCI_CMD_Disconnect_Logical_link                          0x003A /* status */
-struct hciDisconnectLogicalLink {
-	uint8_t physLinkHandle;
-} __packed;
-
-#define HCI_CMD_Logical_Link_Cancel                              0x003B /* complete */
-struct hciLogicalLinkCancel {
-	uint8_t physLinkHandle;
-	uint8_t txFlowSpecID;
-} __packed;
-struct hciCmplLogicalLinkCancel {
-	uint8_t status;
-	uint8_t physLinkHandle;
-	uint8_t txFlowSpecID;
-} __packed;
-
-#define HCI_CMD_Flow_Spec_Modify                                 0x003C /* status */
-struct hciFlowSpecModify {
-	uint16_t handle;
-	uint8_t txFlowSpec[16];
-	uint8_t rxFlowSpec[16];
-} __packed;
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_CMD_Enhanced_Setup_Synchronous_Connection            0x003D /* status */
-struct hciEnhSetupSyncConn {
-	uint16_t conn;
-	uint32_t txBandwidth;
-	uint32_t rxBandwidth;
-	uint8_t txCodingFormat[5];
-	uint8_t rxCodingFormat[5];
-	uint16_t txCodecFrameSize;
-	uint16_t rxCodecFrameSize;
-	uint32_t inputBandwidth;
-	uint32_t outputBandwidth;
-	uint8_t inputCodingFormat[5];
-	uint8_t outputCodingFormat[5];
-	uint16_t inputCodedDataSize;
-	uint16_t outputCodedDataSize;
-	uint8_t inputPcmDataFormat;
-	uint8_t outputPcmDataFormat;
-	uint8_t inputPcmSamplePayloadMsbPosition;
-	uint8_t outputPcmSamplePayloadMsbPosition;
-	uint8_t inputDataPath;
-	uint8_t outputDataPath;
-	uint8_t inputTransportUnitSize;
-	uint8_t outputTransportUnitSize;
-	uint16_t maxLatency;
-	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
-	uint8_t retransmissionEffort;
-} __packed;
-
-#define HCI_CMD_Enhanced_Accept_Synchronous_Connection           0x003E /* status */
-struct hciEnhAcceptSyncConn {
-	uint8_t mac[6];
-	uint32_t txBandwidth;
-	uint32_t rxBandwidth;
-	uint8_t txCodingFormat[5];
-	uint8_t rxCodingFormat[5];
-	uint16_t txCodecFrameSize;
-	uint16_t rxCodecFrameSize;
-	uint32_t inputBandwidth;
-	uint32_t outputBandwidth;
-	uint8_t inputCodingFormat[5];
-	uint8_t outputCodingFormat[5];
-	uint16_t inputCodedDataSize;
-	uint16_t outputCodedDataSize;
-	uint8_t inputPcmDataFormat;
-	uint8_t outputPcmDataFormat;
-	uint8_t inputPcmSamplePayloadMsbPosition;
-	uint8_t outputPcmSamplePayloadMsbPosition;
-	uint8_t inputDataPath;
-	uint8_t outputDataPath;
-	uint8_t inputTransportUnitSize;
-	uint8_t outputTransportUnitSize;
-	uint16_t maxLatency;
-	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
-	uint8_t retransmissionEffort;
-} __packed;
-
-#define HCI_CMD_Truncated_Page                                   0x003F /* status */
-struct hciTruncatedPage {
-	uint8_t mac[6];
-	uint8_t PSRM;
-	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
-} __packed;
-
-#define HCI_CMD_Truncated_Page_Cancel                            0x0040 /* complete */
-struct hciTruncatedPageCancel {
-	uint8_t mac[6];
-} __packed;
-struct hciCmplTruncatedPageCancel {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast               0x0041 /* complete */
-struct hciSetConnectionlessSlaveBroadcast {
-	uint8_t enabled;
-	uint8_t ltAddr; /* 1..7 */
-	uint8_t lpoAllowed; /* can sleep? */
-	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
-	uint16_t intervalMin;
-	uint16_t intervalMax;
-	uint16_t supervisionTimeout;
-} __packed;
-struct hciCmplSetConnectionlessSlaveBroadcast {
-	uint8_t status;
-	uint8_t ltAddr; /* 1..7 */
-	uint16_t interval;
-} __packed;
-
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive       0x0042 /* complete */
-struct hciSetConnectionlessSlaveBroadcastReceive {
-	uint8_t enabled;
-	uint8_t mac[6]; /* add rof tranmitter */
-	uint8_t ltAddr; /* 1..7 */
-	uint16_t interval;
-	uint32_t clockOffset; /* lower 28 bits used */
-	uint32_t nextConnectionlessSlaveBroadcastClock; /* lower 28 bits used */
-	uint16_t supervisionTimeout;
-	uint8_t remoteTimingAccuracy;
-	uint8_t skip;
-	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
-	uint8_t afhChannelMap[10];
-} __packed;
-struct hciCmplSetConnectionlessSlaveBroadcastReceive {
-	uint8_t status;
-	uint8_t mac[6]; /* add rof tranmitter */
-	uint8_t ltAddr; /* 1..7 */
-} __packed;
-
-#define HCI_CMD_Start_Synchronisation_Train                      0x0043 /* status */
-
-#define HCI_CMD_Receive_Synchronisation_Train                    0x0044 /* status */
-struct hciReceiveSyncTrain {
-	uint8_t mac[6];
-	uint16_t syncScanTimeout;
-	uint16_t syncScanWindow;
-	uint16_t syncScanInterval;
-} __packed;
-
-#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply           0x0045 /* complete */
-struct hciRemoteOobExtendedDataRequestReply {
-	uint8_t mac[6];
-	uint8_t C_192[16];
-	uint8_t R_192[16];
-	uint8_t C_256[16];
-	uint8_t R_256[16];
-} __packed;
-struct hciCmplRemoteOobExtendedDataRequestReply {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-
-
-
-
-#define HCI_OGF_Link_Policy                                      2
-
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_CMD_Hold_Mode                                        0x0001 /* status */
-struct hciHoldMode {
-	uint16_t conn;
-	uint16_t holdModeMaxInt;
-	uint16_t holdModeMinInt;
-} __packed;
-
-#define HCI_CMD_Sniff_Mode                                       0x0003 /* status */
-struct hciSniffMode {
-	uint16_t conn;
-	uint16_t sniffMaxInt;
-	uint16_t sniffMinInt;
-	uint16_t sniffAttempt;
-	uint16_t sniffTimeout;
-} __packed;
-
-#define HCI_CMD_Exit_Sniff_Mode                                  0x0004 /* status */
-struct hciExitSniffMode {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Park_State                                       0x0005 /* status */
-struct hciParkState {
-	uint16_t conn;
-	uint16_t beaconMaxInt;
-	uint16_t beaconMinInt;
-} __packed;
-
-#define HCI_CMD_Exit_Park_State                                  0x0006 /* status */
-struct hciExitParkState {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_QoS_Setup                                        0x0007 /* status */
-struct hisQosSetup {
-	uint16_t conn;
-	uint8_t flags;
-	uint8_t serviceType;
-	uint32_t tokenRate;
-	uint32_t peakBandwidth;
-	uint32_t latency;
-	uint32_t delayVariation;
-} __packed;
-
-#define HCI_CMD_Role_Discovery                                   0x0009 /* complete */
-struct hciRoleDiscovery {
-	uint16_t conn;
-} __packed;
-struct hciCmplRoleDiscovery {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Switch_Role                                      0x000B /* status */
-struct hciSwitchRole {
-	uint8_t mac[6];
-	uint8_t becomeSlave;
-} __packed;
-
-#define HCI_CMD_Read_Link_Policy_Settings                        0x000C /* complete */
-struct hciReadLinkPolicySettings {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadLinkPolicySettings {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t policy; /* HCI_LINK_POLICY_* */
-} __packed;
-
-#define HCI_CMD_Write_Link_Policy_Settings                       0x000D /* complete */
-struct hciWriteLinkPolicySettings {
-	uint16_t conn;
-	uint16_t policy; /* HCI_LINK_POLICY_* */
-} __packed;
-struct hciCmplWriteLinkPolicySettings {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_CMD_Read_Default_Link_Policy_Settings                0x000E /* complete */
-struct hciCmplReadDefaultLinkPolicySettings {
-	uint8_t status;
-	uint16_t policy; /* HCI_LINK_POLICY_* */
-} __packed;
-
-#define HCI_CMD_Write_Default_Link_Policy_Settings               0x000F /* complete */
-struct hciWriteDefaultLinkPolicySettings {
-	uint16_t policy; /* HCI_LINK_POLICY_* */
-} __packed;
-struct hciCmplWriteDefaultLinkPolicySettings {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Flow_Specification                               0x0010 /* status */
-struct hisFlowSpecification {
-	uint16_t conn;
-	uint8_t flags;
-	uint8_t flowDirection;
-	uint8_t serviceType;
-	uint32_t tokenRate;
-	uint32_t tockenBucketSize;
-	uint32_t peakBandwidth;
-	uint32_t accessLatency;
-} __packed;
-
-
-/* ==== BT 2.1 ==== */
-
-#define HCI_CMD_Sniff_Subrating                                  0x0011 /* complete */
-struct hciSniffSubrating {
-	uint16_t conn;
-	uint16_t maxLatency;
-	uint16_t minRemoteTimeout;
-	uint16_t minLocalTimeout;
-} __packed;
-struct hciCmplSniffSubrating {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-
-
-
-
-#define HCI_OGF_Controller_and_Baseband                          3
-
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_CMD_Set_Event_Mask                                   0x0001 /* complete */
-struct hciSetEventMask {
-	uint64_t mask; /* bitmask of HCI_EVENT_* */
-} __packed;
-struct hciCmplSetEventMask {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Reset                                            0x0003 /* complete */
-struct hciCmplReset {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_Event_Filter                                 0x0005 /* complete */
-struct hciSetEventFilter {
-	uint8_t filterType; /* HCI_FILTER_TYPE_* */
-	/* more things are optional here */
-} __packed;
-struct hciCmplSetEventFiler {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Flush                                            0x0008 /* complete */
-struct hciFlush {
-	uint16_t conn;
-} __packed;
-struct hciCmplFlush {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_PIN_Type                                    0x0009 /* complete */
-struct hciCmplReadPinType {
-	uint8_t status;
-	uint8_t isFixed;
-} __packed;
-
-#define HCI_CMD_Write_PIN_Type                                   0x000A /* complete */
-struct hciWritePinType {
-	uint8_t isFixed;
-} __packed;
-struct hciCmplWritePinType {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Create_New_Unit_Key                              0x000B /* complete */
-struct hciCmplCreateNewUnitKey {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Stored_Link_Key                             0x000D /* complete */
-struct hciReadStoredLinkKey {
-	uint8_t mac[6];
-	uint8_t readAll;
-} __packed;
-struct hciCmplReadStoredLinkKey {
-	uint8_t status;
-	uint16_t maxNumKeys;
-	uint16_t numKeysRead;
-} __packed;
-
-#define HCI_CMD_Write_Stored_Link_Key                            0x0011 /* complete */
-struct hciWriteStoredLinkKeyItem {
-	uint8_t mac[6];
-	uint8_t key[16];
-} __packed;
-struct hciWriteStoredLinkKey {
-	uint8_t numKeys;
-	struct hciWriteStoredLinkKeyItem items[];
-} __packed;
-struct hciCmplWriteStoredLinkKey {
-	uint8_t status;
-	uint8_t numKeysWritten;
-} __packed;
-
-#define HCI_CMD_Delete_Stored_Link_Key                           0x0012 /* complete */
-struct hciDeleteStoredLinkKey {
-	uint8_t mac[6];
-	uint8_t deleteAll;
-} __packed;
-struct hciCmplDeleteStoredLinkKey {
-	uint8_t status;
-	uint8_t numKeysDeleted;
-} __packed;
-
-#define HCI_CMD_Write_Local_Name                                 0x0013 /* complete */
-struct hciWriteLocalName {
-	char name[HCI_DEV_NAME_LEN];
-} __packed;
-struct hciCmplWriteLocalName {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Local_Name                                  0x0014 /* complete */
-struct hciCmplReadLocalName {
-	uint8_t status;
-	char name[HCI_DEV_NAME_LEN];
-} __packed;
-
-#define HCI_CMD_Read_Connection_Accept_Timeout                   0x0015 /* complete */
-struct hciCmplReadConnAcceptTimeout {
-	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
-} __packed;
-
-#define HCI_CMD_Write_Connection_Accept_Timeout                  0x0016 /* complete */
-struct hciWriteConnAcceptTimeout {
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
-} __packed;
-struct hciCmplWriteConnAcceptTimeout {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Page_Timeout                                0x0017 /* complete */
-struct hciCmplReadPageTimeout {
-	uint8_t status;
-	uint16_t timeout;
-} __packed;
-
-#define HCI_CMD_Write_Page_Timeout                               0x0018 /* complete */
-struct hciWritePageTimeout {
-	uint16_t timeout;
-} __packed;
-struct hciCmplWritePageTimeout {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Scan_Enable                                 0x0019 /* complete */
-struct hciCmplReadScanEnable {
-	uint8_t status;
-	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
-} __packed;
-
-#define HCI_CMD_Write_Scan_Enable                                0x001A /* complete */
-struct hciWriteScanEnable {
-	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
-} __packed;
-struct hciCmplWriteScanEnable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Page_Scan_Activity                          0x001B /* complete */
-struct hciCmplReadPageScanActivity {
-	uint8_t status;
-	uint16_t scanInterval;
-	uint16_t scanWindow;
-} __packed;
-
-#define HCI_CMD_Write_Page_Scan_Activity                         0x001C /* complete */
-struct hciWritePageScanActivity {
-	uint16_t scanInterval;
-	uint16_t scanWindow;
-} __packed;
-struct hciCmplWritePageScanActivity {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Inquiry_Scan_Activity                       0x001D /* complete */
-struct hciCmplReadInquiryScanActivity {
-	uint8_t status;
-	uint16_t scanInterval;
-	uint16_t scanWindow;
-} __packed;
-
-#define HCI_CMD_Write_Inquiry_Scan_Activity                      0x001E /* complete */
-struct hciWriteInquiryScanActivity {
-	uint16_t scanInterval;
-	uint16_t scanWindow;
-} __packed;
-struct hciCmplWriteInquiryScanActivity {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Authentication_Enable                       0x001F /* complete */
-struct hciCmplReadAuthEnable {
-	uint8_t status;
-	uint8_t authRequired;
-} __packed;
-
-#define HCI_CMD_Write_Authentication_Enable                      0x0020 /* complete */
-struct hciWriteAuthEnable {
-	uint8_t authRequired;
-} __packed;
-struct hciCmplWriteAuthEnable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Encryption_Mode                             0x0021 /* complete *//* deprecated in BT 2.1+ */
-struct hciCmplReadEncryptionMode {
-	uint8_t status;
-	uint8_t encrRequired;
-} __packed;
-
-#define HCI_CMD_Write_Encryption_Mode                            0x0022 /* complete *//* deprecated in BT 2.1+ */
-struct hciWriteEncryptionMode {
-	uint8_t encrRequired;
-} __packed;
-struct hciCmplWriteEncryptionMode {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Class_Of_Device                             0x0023 /* complete */
-struct hciCmplReadClassOfDevice {
-	uint8_t status;
-	uint8_t cls[3];
-} __packed;
-
-#define HCI_CMD_Write_Class_Of_Device                            0x0024 /* complete */
-struct hciWriteClassOfDevice {
-	uint8_t cls[3];
-} __packed;
-struct hciCmplWriteClassOfDevice {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Voice_Setting                               0x0025 /* complete */
-struct hciCmplReadVoiceSetting {
-	uint8_t status;
-	uint16_t voiceSetting;
-} __packed;
-
-#define HCI_CMD_Write_Voice_Setting                              0x0026 /* complete */
-struct hciWriteVoiceSetting {
-	uint16_t voiceSetting;
-} __packed;
-struct hciCmplWriteVoiceSetting {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Automatic_Flush_Timeout                     0x0027 /* complete */
-struct hciReadAutoFlushTimeout {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadAutoFlushTimeout {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t timeout;
-} __packed;
-
-#define HCI_CMD_Write_Automatic_Flush_Timeout                    0x0028 /* complete */
-struct hciWriteAutoFlushTimeout {
-	uint16_t conn;
-	uint16_t timeout;
-} __packed;
-struct hciCmplWriteAutoFlushTimeout {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Num_Broadcast_Retransmissions               0x0029 /* complete */
-struct hciCmplReadNumBroadcastRetransmissions {
-	uint8_t status;
-	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
-} __packed;
-
-#define HCI_CMD_Write_Num_Broadcast_Retransmissions              0x002A /* complete */
-struct hciWriteNumBroadcastRetransmissions {
-	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
-} __packed;
-struct hciCmplWriteNumBroadcastRetransmissions {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Hold_Mode_Activity                          0x002B /* complete */
-struct hciCmplReadHoldModeActivity {
-	uint8_t status;
-	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
-} __packed;
-
-#define HCI_CMD_Write_Hold_Mode_Activity                         0x002C /* complete */
-struct hciWriteHoldModeActivity {
-	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
-} __packed;
-struct hciCmplWriteHoldModeActivity {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Transmit_Power_Level                        0x002D /* complete */
-struct hciReadTransmitPowerLevel {
-	uint16_t conn;
-	uint8_t max; /* else current */
-} __packed;
-struct hciCmplReadTransmitPowerLevel {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t txPower; /* actually an int8_t */
-} __packed;
-
-#define HCI_CMD_Read_SCO_Flow_Control_Enable                     0x002E /* complete */
-struct hciCmplReadSyncFlowCtrl {
-	uint8_t status;
-	uint8_t syncFlowCtrlOn;
-} __packed;
-
-#define HCI_CMD_Write_SCO_Flow_Control_Enable                    0x002F /* complete */
-struct hciWriteSyncFlowCtrlEnable {
-	uint8_t syncFlowCtrlOn;
-} __packed;
-struct hciCmplWriteSyncFlowCtrlEnable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_Controller_To_Host_Flow_Control              0x0031 /* complete */
-struct hciSetControllerToHostFlowControl {
-	uint8_t chipToHostFlowCtrl; /* bitmask of HCI_TO_HOST_FLOW_CTRL_* */
-} __packed;
-struct hciCmplSetControllerToHostFlowControl {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Host_Buffer_Size                                 0x0033 /* complete */
-struct hciHostBufferSize {
-	uint16_t maxAclPacket;
-	uint8_t maxScoPacket;
-	uint16_t numAclPackets;
-	uint16_t numScoPackets;
-} __packed;
-struct hciCmplHostBufferSize {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Host_Number_Of_Completed_Packets                 0x0035 /* special: can be sent anytime (not subj to cmd flow control), does not generate events unless error */
-struct hciHostNumberOfCompletedPacketsItem {
-	uint16_t conn;
-	uint16_t numCompletedPackets;
-} __packed;
-struct hciHostNumberOfCompletedPackets {
-	uint8_t numHandles;
-	struct hciHostNumberOfCompletedPacketsItem items[];
-} __packed;
-
-#define HCI_CMD_Read_Link_Supervision_Timeout                    0x0036 /* complete */
-struct hciReadLinkSupervisionTimeout {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadLinkSupervisionTimeout {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
-} __packed;
-
-#define HCI_CMD_Write_Link_Supervision_Timeout                   0x0037 /* complete */
-struct hciWriteLinkSupervisionTimeout {
-	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
-} __packed;
-struct hciCmplWriteLinkSupervisionTimeout {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Number_Of_Supported_IAC                     0x0038 /* complete */
-struct hciCmplReadNumberOfSupportedIac {
-	uint8_t status;
-	uint8_t numSupportedIac;
-} __packed;
-
-#define HCI_CMD_Read_Current_IAC_LAP                             0x0039 /* complete */
-struct hciCmplReadCurrentIacItem {
-	uint8_t iac_lap[3];
-} __packed;
-struct hciCmplReadCurrentIac {
-	uint8_t status;
-	uint8_t numCurrentIac;
-	struct hciCmplReadCurrentIacItem items[];
-} __packed;
-
-#define HCI_CMD_Write_Current_IAC_LAP                            0x003A /* complete */
-struct hciWriteCurrentIacLapItem {
-	uint8_t iacLap[3];
-} __packed;
-struct hciWriteCurrentIacLap {
-	uint8_t numCurrentIac;
-	struct hciWriteCurrentIacLapItem items[];
-} __packed;
-struct hciCmplWriteCurrentIacLap {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Page_Scan_Period_Mode                       0x003B /* complete */
-struct hciCmplReadPageScanPeriodMode {
-	uint8_t status;
-	uint8_t mode;
-} __packed;
-
-#define HCI_CMD_Write_Page_Scan_Period_Mode                      0x003C /* complete */
-struct hciWritePageScanPeriodMode {
-	uint8_t mode;
-} __packed;
-struct hciCmplWritePageScanPeriodMode {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Page_Scan_Mode                              0x003D  /* complete *//* deprecated in BT 1.2+ */
-struct hciCmplReadPageScanMode {
-	uint8_t status;
-	uint8_t pageScanMode; /* nonzero modes are optional */
-} __packed;
-
-#define HCI_CMD_Write_Page_Scan_Mode                             0x003E  /* complete *//* deprecated in BT 1.2+ */
-struct hciWritePageScanMode {
-	uint8_t pageScanMode; /* nonzero modes are optional */
-} __packed;
-struct hciCmplWritePageScanMode {
-	uint8_t status;
-} __packed;
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_CMD_Set_AFH_Host_Channel_Classification              0x003F /* complete */
-struct hciSetAfhHostChannelClassification {
-	uint8_t channels[10];
-} __packed;
-struct hciCmplSetAfhHostChannelClassification {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Inquiry_Scan_Type                           0x0042 /* complete */
-struct hciCmplReadInquiryScanType {
-	uint8_t status;
-	uint8_t interlaced; /* optional */
-} __packed;
-
-#define HCI_CMD_Write_Inquiry_Scan_Type                          0x0043 /* complete */
-struct hciWriteInquiryScanType {
-	uint8_t interlaced; /* optional */
-} __packed;
-struct hciCmplWriteInquiryScanType {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Inquiry_Mode                                0x0044 /* complete */
-struct hciCmplReadInquryMode {
-	uint8_t status;
-	uint8_t inqMode; /* HCI_INQ_MODE_* */
-} __packed;
-
-#define HCI_CMD_Write_Inquiry_Mode                               0x0045 /* complete */
-struct hciWriteInquiryMode {
-	uint8_t inqMode; /* HCI_INQ_MODE_* */
-} __packed;
-struct hciCmplWriteInquiryMode {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Page_Scan_Type                              0x0046 /* complete */
-struct hciCmplReadPageScanType {
-	uint8_t status;
-	uint8_t interlaced; /* optional */
-} __packed;
-
-#define HCI_CMD_Write_Page_Scan_Type                             0x0047 /* complete */
-struct hciWritePageScanType {
-	uint8_t interlaced; /* optional */
-} __packed;
-struct hciCmplWritePageScanType {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_AFH_Channel_Assessment_Mode                 0x0048 /* complete */
-struct hciCmplReadAfhChannelAssessment {
-	uint8_t status;
-	uint8_t channelAssessmentEnabled;
-} __packed;
-
-#define HCI_CMD_Write_AFH_Channel_Assessment_Mode                0x0049 /* complete */
-struct hciWriteAfhChannelAssessment {
-	uint8_t channelAssessmentEnabled;
-} __packed;
-struct hciCmplWriteAfhChannelAssessment {
-	uint8_t status;
-} __packed;
-
-
-/* ==== BT 2.1 ==== */
-
-#define HCI_CMD_Read_Extended_Inquiry_Response                   0x0051 /* complete */
-struct hciCmplReadEIR {
-	uint8_t status;
-	uint8_t useFec;
-	uint8_t data[240];
-} __packed;
-
-#define HCI_CMD_Write_Extended_Inquiry_Response                  0x0052 /* complete */
-struct hciWriteEIR {
-	uint8_t useFec;
-	uint8_t data[240];
-} __packed;
-struct hciCmplWriteEIR {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Refresh_Encryption_Key                           0x0052 /* status */
-struct hciRefreshEncryptionKey {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Simple_Pairing_Mode                         0x0055 /* complete */
-struct hciCmplReadSimplePairingMore {
-	uint8_t status;
-	uint8_t useSsp;
-} __packed;
-
-#define HCI_CMD_Write_Simple_Pairing_Mode                        0x0056 /* complete */
-struct hciWriteSimplePairingMode {
-	uint8_t useSsp;
-} __packed;
-struct hciCmplWriteSimplePairingMode {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Local_OOB_Data                              0x0057 /* complete */
-struct hciCmplReadLocalOobData {
-	uint8_t status;
-	uint8_t C[16];
-	uint8_t R[16];
-} __packed;
-
-#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level       0x0058 /* complete */
-struct hciCmplReadInquiryTransmitPowerLevel {
-	uint8_t status;
-	uint8_t power; /* actually an int8_t */
-} __packed;
-
-#define HCI_CMD_Write_Inquiry_Transmit_Power_Level               0x0059 /* complete */
-struct hciWriteInquiryTransmitPowerLevel {
-	uint8_t power; /* actually an int8_t */
-} __packed;
-struct hciCmplWriteInquiryTransmitPowerLevel {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Default_Erroneous_Data_Reporting            0x005A /* complete */
-struct hciCmplReadErroneousDataReporting {
-	uint8_t status;
-	uint8_t reportingEnabled;
-} __packed;
-
-#define HCI_CMD_Write_Default_Erroneous_Data_Reporting           0x005B /* complete */
-struct hciWriteErroneousDataReporting {
-	uint8_t reportingEnabled;
-} __packed;
-struct hciCmplWriteErroneousDataReporting {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Enhanced_Flush                                   0x005F /* status */
-struct hciEnhancedFlush {
-	uint16_t conn;
-	uint8_t which; /* 0 is the only value - flush auto-flushable packets only */
-} __packed;
-
-#define HCI_CMD_Send_Keypress_Notification                       0x0060 /* complete */
-struct hciSendKeypressNotification {
-	uint8_t mac[6];
-	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
-} __packed;
-struct hciCmplSendKeypressNotification {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_CMD_Read_Logical_Link_Accept_Timeout                 0x0061 /* complete */
-struct hciCmplReadLogicalLinkTimeout {
-	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
-} __packed;
-
-#define HCI_CMD_Write_Logical_Link_Accept_Timeout                0x0062 /* complete */
-struct hciWriteLogicalLinkTimeout {
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
-} __packed;
-struct hciCmplWriteLogicalLinkTimeout {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_Event_Mask_Page_2                            0x0063 /* complete */
-struct hciSetEventMaskPage2 {
-	uint64_t mask; /* bitmask of HCI_EVENT_P2_* */
-} __packed;
-struct hciCmplSetEventMaskPage2 {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Location_Data                               0x0064 /* complete */
-struct hciCmplReadLocationData {
-	uint8_t status;
-	uint8_t regulatoryDomainKnown;
-	uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */
-	uint8_t locationSuffix; /* HCI_LOCATION_DOMAIN_OPTION_* */
-	uint8_t mainsPowered;
-} __packed;
-
-#define HCI_CMD_Write_Location_Data                              0x0065 /* complete */
-struct hciWriteLocationData {
-	uint8_t regulatoryDomainKnown;
-	uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */
-	uint8_t locationSuffix; /* HCI_LOCATION_DOMAIN_OPTION_* */
-	uint8_t mainsPowered;
-} __packed;
-struct hciCmplWriteLocationData {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Flow_Control_Mode                           0x0066 /* complete */
-struct hciCmplReadFlowControlMode {
-	uint8_t status;
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
-} __packed;
-
-#define HCI_CMD_Write_Flow_Control_mode                          0x0067 /* complete */
-struct hciWriteFlowControlMode {
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
-} __packed;
-struct hciCmplWriteFlowcontrolMode {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Enhanced_Transmit_Power_Level               0x0068 /* complete */
-struct hciReadEnhancedTransmitPowerLevel {
-	uint16_t conn;
-	uint8_t max; /* else currurent is read */
-} __packed;
-struct hciCmplReadEnhancedTransmitPowerLevel {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t txLevelGFSK; /* actually an int8_t */
-	uint8_t txLevelDQPSK; /* actually an int8_t */
-	uint8_t txLevel8DPSK; /* actually an int8_t */
-} __packed;
-
-#define HCI_CMD_Read_Best_Effort_Flush_Timeout                   0x0069 /* complete */
-struct hciReadBestEffortFlushTimeout {
-	uint16_t logicalLinkHandle;
-} __packed;
-struct hciCmplReadBestEffortFlushTimeout {
-	uint8_t status;
-	uint32_t bestEffortFlushTimeout; /* in microseconds */
-} __packed;
-
-#define HCI_CMD_Write_Best_Effort_Flush_Timeout                  0x006A /* complete */
-struct hciWriteBestEffortFlushTimeout {
-	uint16_t logicalLinkHandle;
-	uint32_t bestEffortFlushTimeout; /* in microseconds */
-} __packed;
-struct hciCmplWriteBestEffortFlushTimeout {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Short_Range_Mode                                 0x006B /* status */
-struct hciShortRangeMode {
-	uint8_t physicalLinkHandle;
-	uint8_t shortRangeModeEnabled;
-} __packed;
-
-
-/* ==== BT 4.0 ==== */
-
-#define HCI_CMD_Read_LE_Host_Supported                           0x006C /* complete */
-struct hciCmplReadLeHostSupported {
-	uint8_t status;
-	uint8_t leSupportedHost;
-	uint8_t simultaneousLeHost;
-} __packed;
-
-#define HCI_CMD_Write_LE_Host_Supported                          0x006D /* complete */
-struct hciWriteLeHostSupported {
-	uint8_t leSupportedHost;
-	uint8_t simultaneousLeHost;
-} __packed;
-struct hciCmplWriteLeHostSupported {
-	uint8_t status;
-} __packed;
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_CMD_Set_MWS_Channel_Parameters                       0x006E /* complete */
-struct hciSetMwsChannelParams {
-	uint8_t mwsEnabled;
-	uint16_t mwsChannelRxCenterFreq; /* in MHz */
-	uint16_t mwsChannelTxCenterFreq; /* in MHz */
-	uint16_t mwsChannelRxBandwidth; /* in MHz */
-	uint16_t mwsChannelTxBandwidth; /* in MHz */
-	uint8_t mwsChannelType;
-} __packed;
-struct hciCmplSetMwsChannelParams {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_External_Frame_Configuration                 0x006F /* complete */
-struct hciSetExternalFrameConfigItem {
-	uint16_t periodDuration; /* in microseconds */
-	uint8_t periodType; /* HCI_PERIOD_TYPE_* */
-} __packed;
-struct hciSetExternalFrameConfig {
-	uint16_t extFrameDuration; /* in microseonds */
-	uint16_t extFrameSyncAssertOffset; /* in microseonds */
-	uint16_t extFrameSyncAssertJitter; /* in microseonds */
-	uint8_t extNumPeriods; /* 1 .. 32 */
-	struct hciSetExternalFrameConfigItem items[];
-} __packed;
-struct hciCmplSetExternalFrameConfig {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_MWS_Signalling                               0x0070 /* complete */
-struct hciSetMwsSignalling {
-	uint16_t mwsRxAssertOffset; /* all of these are in microseconds */
-	uint16_t mwsRxAssertJitter;
-	uint16_t mwsRxDeassertOffset;
-	uint16_t mwsRxDeassertJitter;
-	uint16_t mwsTxAssertOffset;
-	uint16_t mwsTxAssertJitter;
-	uint16_t mwsTxDeassertOffset;
-	uint16_t mwsTxDeassertJitter;
-	uint16_t mwsPatternAssertOffset;
-	uint16_t mwsPatternAssertJitter;
-	uint16_t mwsInactivityDurationAssertOffset;
-	uint16_t mwsInactivityDurationAssertJitter;
-	uint16_t mwsScanFrequencyAssertOffset;
-	uint16_t mwsScanFrequencyAssertJitter;
-	uint16_t mwsPriorityAssertOffsetRequest;
-} __packed;
-struct hciCmplSetMwsSignalling {
-	uint8_t status;
-	uint16_t bluetoothRxPriorityAssertOffset;
-	uint16_t bluetoothRxPriorityAssertJitter;
-	uint16_t bluetoothRxPriorityDeassertOffset;
-	uint16_t bluetoothRxPriorityDeassertJitter;
-	uint16_t _802RxPriorityAssertOffset;
-	uint16_t _802RxPriorityAssertJitter;
-	uint16_t _802RxPriorityDeassertOffset;
-	uint16_t _802RxPriorityDeassertJitter;
-	uint16_t bluetoothTxOnAssertOffset;
-	uint16_t bluetoothTxOnAssertJitter;
-	uint16_t bluetoothTxOnDeassertOffset;
-	uint16_t bluetoothTxOnDeassertJitter;
-	uint16_t _802TxOnAssertOffset;
-	uint16_t _802TxOnAssertJitter;
-	uint16_t _802TxOnDeassertOffset;
-	uint16_t _802TxOnDeassertJitter;
-} __packed;
-
-#define HCI_CMD_Set_MWS_Transport_Layer                          0x0071 /* complete */
-struct hciSetMwsTransportLayer {
-	uint8_t transportLayer;
-	uint32_t toMwsBaudRate; /* in byte/sec */
-	uint32_t fromMwsBaudRate; /* in byte/sec */
-} __packed;
-struct hciCmplSetMwsTransportLayer {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_MWS_Scan_Frequency_Table                     0x0072 /* complete */
-struct hciSetMwsScanFrequencyTableItem {
-	uint16_t scanFreqLow; /*in MHz */
-	uint16_t scanFreqHigh; /*in MHz */
-} __packed;
-struct hciSetMwsScanFrequencyTable {
-	uint8_t n;
-	struct hciSetMwsScanFrequencyTableItem items[];
-} __packed;
-struct hciCmplSetMwsScanFrequencyTable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_MWS_PATTERN_Configuration                    0x0073 /* complete */
-struct hciSetMwsPatternConfigItem {
-	uint16_t intervalDuration; /* in microseconds */
-	uint8_t intervalType; /* HCI_MWS_INTERVAL_TYPE_* */
-} __packed;
-struct hciSetMwsPatternConfig {
-	uint8_t mwsPatternIndex; /* 0 .. 2 */
-	uint8_t mwsPatternNumIntervals;
-	struct hciSetMwsPatternConfigItem items[];
-} __packed;
-struct hciCmplSetMwsPatternConfig {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Set_Reserved_LT_ADDR                             0x0074 /* complete */
-struct hciSetReservedLtAddr {
-	uint8_t ltAddr;
-} __packed;
-struct hciCmplSetReservedLtAddr {
-	uint8_t status;
-	uint8_t ltAddr;
-} __packed;
-
-#define HCI_CMD_Delete_Reserved_LT_ADDR                          0x0075 /* complete */
-struct hciDeleteReservedLtAddr {
-	uint8_t ltAddr;
-} __packed;
-struct hciCmplDeleteReservedLtAddr {
-	uint8_t status;
-	uint8_t ltAddr;
-} __packed;
-
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data          0x0076 /* complete */
-struct hciSetConnlessSlaveBroadcastData {
-	uint8_t ltAddr;
-	uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */
-	uint8_t dataLen;
-	uint8_t data[];
-} __packed;
-struct hciCmplSetConnlessSlaveBroadcastData {
-	uint8_t status;
-	uint8_t ltAddr;
-} __packed;
-
-#define HCI_CMD_Read_Synchronisation_Train_Parameters            0x0077 /* complete */
-struct hciCmplReadSyncTrainParams {
-	uint8_t status;
-	uint16_t interval;
-	uint32_t syncTrainTimeout;
-	uint8_t serviceData;
-} __packed;
-
-#define HCI_CMD_Write_Synchronisation_Train_Parameters           0x0078 /* complete */
-struct hciWriteSyncTrainParams {
-	uint16_t intMin;
-	uint16_t intMax;
-	uint32_t syncTrainTimeout;
-	uint8_t serviceData;
-} __packed;
-struct hciCmplWriteSyncTrainParams {
-	uint8_t status;
-	uint16_t interval;
-} __packed;
-
-#define HCI_CMD_Read_Secure_Connections_Host_Support             0x0079 /* complete */
-struct hciCmplReadSecureConnectionsHostSupport {
-	uint8_t status;
-	uint8_t secureConnectionsSupported;
-} __packed;
-
-#define HCI_CMD_Write_Secure_Connections_Host_Support            0x007A /* complete */
-struct hciWriteSecureConnectionsHostSupport {
-	uint8_t secureConnectionsSupported;
-} __packed;
-struct hciCmplWriteSecureConnectionsHostSupport {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Authenticated_Payload_Timeout               0x007B /* complete */
-struct hciReadAuthedPayloadTimeout {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadAuthedPayloadTimeout {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
-} __packed;
-
-#define HCI_CMD_Write_Authenticated_Payload_Timeout              0x007C /* complete */
-struct hciWriteAuthedPayloadTimeout {
-	uint16_t conn;
-	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
-} __packed;
-struct hciCmplWriteAuthedPayloadTimeout {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Local_OOB_Extended_Data                     0x007D /* complete */
-struct hciCmplReadLocalOobExtendedData {
-	uint8_t status;
-	uint8_t C_192[16];
-	uint8_t R_192[16];
-	uint8_t C_256[16];
-	uint8_t R_256[16];
-} __packed;
-
-#define HCI_CMD_Read_Extended_Page_Timeout                       0x007E /* complete */
-struct hciCmplReadExtendedPageTimeout {
-	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
-} __packed;
-
-#define HCI_CMD_Write_Extended_Page_Timeout                      0x007F /* complete */
-struct hciWriteExtendedPageTimeout {
-	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
-} __packed;
-struct hciCmplWriteExtendedPageTimeout {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_Read_Extended_Inquiry_Length                     0x0080 /* complete */
-struct hciCmplReadExtendedInquiryLength {
-	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
-} __packed;
-
-#define HCI_CMD_Write_Extended_Inquiry_Length                    0x0081 /* complete */
-struct hciWriteExtendedInquiryLength {
-	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
-} __packed;
-struct hciCmplWriteExtendedInquiryLength {
-	uint8_t status;
-} __packed;
-
-
-
-
-
-#define HCI_OGF_Informational                                    4
-
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_CMD_Read_Local_Version_Information                   0x0001 /* complete */
-struct hciCmplReadLocalVersion {
-	uint8_t status;
-	uint8_t hciVersion; /* HCI_VERSION_* */
-	uint16_t hciRevision;
-	uint8_t lmpVersion; /* HCI_VERSION_* */
-	uint16_t manufName;
-	uint16_t lmpSubversion;
-} __packed;
-
-#define HCI_CMD_Read_Local_Supported_Commands                    0x0002 /* complete */
-struct hciCmplReadLocalSupportedCommands {
-	uint8_t status;
-	uint64_t bitfield;
-} __packed;
-
-#define HCI_CMD_Read_Local_Supported_Features                    0x0003 /* complete */
-struct hciCmplReadLocalSupportedFeatures {
-	uint8_t status;
-	uint64_t features;  /* bitmask of HCI_LMP_FTR_* */
-} __packed;
-
-#define HCI_CMD_Read_Local_Extended_Features                     0x0004 /* complete */
-struct hciReadLocalExtendedFeatures {
-	uint8_t page;
-} __packed;
-struct hciCmplReadLocalExtendedFeatures {
-	uint8_t status;
-	uint8_t page;
-	uint8_t maxPage;
-	uint64_t features; /* bitmask of HCI_LMP_EXT_FTR_P* */
-} __packed;
-
-#define HCI_CMD_Read_Buffer_Size                                 0x0005 /* complete */
-struct hciCmplReadBufferSize {
-	uint8_t status;
-	uint16_t aclBufferLen;
-	uint8_t scoBufferLen;
-	uint16_t numAclBuffers;
-	uint16_t numScoBuffers;
-} __packed;
-
-#define HCI_CMD_Read_BD_ADDR                                     0x0009 /* complete */
-struct hciCmplReadBdAddr {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_CMD_Read_Data_Block_Size                             0x000A /* complete */
-struct hciCmplReadDataBlockSize {
-	uint8_t status;
-	uint16_t maxAclDataPacketLen;
-	uint16_t dataBlockLen;
-	uint16_t totalNumDataBlocks;
-} __packed;
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_CMD_Read_Local_Supported_Codecs                      0x000B /* complete */
-struct hciCmplReadLocalSupportedCodecs {
-	uint8_t status;
-	uint8_t numSupportedCodecs;
-	uint8_t codecs[];
-/* these follow, but due to var array cannot be declared here:
-	uint8_t numVendorCodecs;
-	uint32_t vendorCodecs[];
-*/
-} __packed;
-
-
-
-
-
-#define HCI_OGF_Status                                           5
-
-
-/* == BT 1.1 == */
-
-#define HCI_CMD_Read_Failed_Contact_Counter                      0x0001 /* complete */
-struct hciReadFailedContactCounter {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadFailedContactCounter {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t counter;
-} __packed;
-
-#define HCI_CMD_Reset_Failed_Contact_Counter                     0x0002 /* complete */
-struct hciResetFailedContactCounter {
-	uint16_t conn;
-} __packed;
-struct hciCmplResetFailedContactCounter {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_Read_Link_Quality                                0x0003 /* complete */
-struct hciReadLinkQuality {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadLinkQuality {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t quality;
-} __packed;
-
-#define HCI_CMD_Read_RSSI                                        0x0005 /* complete */
-struct hciReadRssi {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadRssi {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t RSSI; /* actually an int8_t */
-} __packed;
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_CMD_Read_AFH_Channel_Map                             0x0006 /* complete */
-struct hciReadAfhChannelMap {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadAfhChannelMap {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t map[10];
-} __packed;
-
-#define HCI_CMD_Read_Clock                                       0x0007 /* complete */
-struct hciReadClock {
-	uint16_t conn;
-	uint8_t readRemote; /* else reads local and ignores conn */
-} __packed;
-struct hciCmplReadClock {
-	uint8_t status;
-	uint16_t conn;
-	uint32_t clock;
-	uint16_t accuracy;
-} __packed;
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_CMD_Read_Encryption_Key_Size                         0x0008 /* complete */
-struct hciReadEncrKeySize {
-	uint16_t conn;
-} __packed;
-struct hciCmplReadEncrKeySize {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t keySize;
-} __packed;
-
-#define HCI_CMD_Read_Local_AMP_Info                              0x0009 /* complete */
-struct hciCmplReadLocalAmpInfo {
-	uint8_t status;
-	uint8_t ampStatus;
-	uint32_t totalBandwidth;
-	uint32_t maxGuaranteedBandwidth;
-	uint32_t minLatency;
-	uint16_t maxPduSize;
-	uint8_t controllerType;
-	uint16_t palCapabilities;
-	uint16_t maxAmpAssocLen;
-	uint32_t maxFlushTimeout;
-	uint32_t bestEffortFlushTimeout;
-} __packed;
-
-#define HCI_CMD_Read_Local_AMP_ASSOC                             0x000A /* complete */
-struct hciReadLocalAmpAssoc {
-	uint8_t physicalLinkHandle;
-	uint16_t lengthSoFar;
-	uint16_t ampAssocLen;
-} __packed;
-struct hciCmplReadLocalAmpAssoc {
-	uint8_t status;
-	uint8_t physicalLinkHandle;
-	uint16_t ampAssocRemainingLen; /* incl this fragment */
-	uint8_t ampAssocFragment[]; /* 1.. 248 byutes */
-} __packed;
-
-#define HCI_CMD_Write_Remote_AMP_ASSOC                           0x000B /* complete */
-struct hciWriteRemoteAmpAssoc {
-	uint8_t physicalLinkHandle;
-	uint16_t lengthSoFar;
-	uint16_t remaningLength;
-	uint8_t fragment[]; /* 248 bytes for all but last one */
-} __packed;
-struct hciCmplWriteRemoteAmpAssoc {
-	uint8_t status;
-	uint8_t physicalLinkHandle;
-} __packed;
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_CMD_Get_MWS_Transport_Layer_Configuration            0x000C /* complete */
-struct hciCmplGetMwsTransportLayerConfigItem {
-	uint8_t transportLayer;
-	uint8_t numBaudRates;
-} __packed;
-struct hciCmplGetMwsTransportLayerConfigBandwidthItem {
-	uint32_t toMwsBaudRate;
-	uint32_t fromMwsBaudRate;
-} __packed;
-struct hciCmplGetMwsTransportLayerConfig {
-	uint8_t status;
-	uint8_t numTransports;
-	struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports items */
-/* this follows:
-	struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // sum(items[].numbaudRates) items
-*/
-} __packed;
-
-#define HCI_CMD_Set_Triggered_Clock_Capture                      0x000D /* complete */
-struct hciSetTriggeredClockCapture {
-	uint16_t conn;
-	uint8_t enable;
-	uint8_t piconetClock; /* else local clock & "conn" is ignored */
-	uint8_t lpoAllowed; /* can sleep? */
-	uint8_t numClockCapturesToFilter;
-} __packed;
-struct hciCmplSetTriggeredClockCapture {
-	uint8_t status;
-} __packed;
-
-
-
-
-
-#define HCI_OGF_LE                                               8
-
-
-/* ==== BT 4.0 ==== */
-
-#define HCI_CMD_LE_Set_Event_Mask                                0x0001 /* complete */
-struct hciLeSetEventMask {
-	uint64_t events; /* bitmask of HCI_LE_EVENT_* */
-} __packed;
-struct hciCmplLeSetEventMask {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Read_Buffer_Size                              0x0002 /* complete */
-struct hciCmplLeReadBufferSize {
-	uint8_t status;
-	uint16_t leBufferSize;
-	uint8_t leNumBuffers;
-} __packed;
-
-#define HCI_CMD_LE_Read_Local_Supported_Features                 0x0003 /* complete */
-struct hciCmplLeReadLocalSupportedFeatures {
-	uint8_t status;
-	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
-} __packed;
-
-#define HCI_CMD_LE_Set_Random_Address                            0x0005 /* complete */
-struct hciLeSetRandomAddress{
-	uint8_t mac[6];
-} __packed;
-struct hciCmplLeSetRandomAddress{
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Set_Adv_Params                                0x0006 /* complete */
-struct hciLeSetAdvParams {
-	uint16_t advIntervalMin;
-	uint16_t advIntervalMax;
-	uint8_t advType;
-	uint8_t useRandomAddress;
-	uint8_t directRandomAddress;
-	uint8_t directAddr[6];
-	uint8_t advChannelMap;
-	uint8_t advFilterPolicy;
-} __packed;
-struct hciCmplLeSetAdvParams {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Read_Adv_Channel_TX_Power                     0x0007 /* complete */
-struct hciCmplLeReadAdvChannelTxPower {
-	uint8_t status;
-	uint8_t txPower; /* actually an int8_t */
-} __packed;
-
-#define HCI_CMD_LE_Set_Advertising_Data                          0x0008 /* complete */
-struct hciLeSetAdvData {
-	uint8_t advDataLen;
-	uint8_t advData[31];
-} __packed;
-struct hciCmplLeSetAdvData {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Set_Scan_Response_Data                        0x0009 /* complete */
-struct hciSetScanResponseData {
-	uint8_t scanRspDataLen;
-	uint8_t scanRspData[31];
-} __packed;
-struct hciCmplSetScanResponseData {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Set_Advertise_Enable                          0x000A /* complete */
-struct hciLeSetAdvEnable {
-	uint8_t advOn;
-} __packed;
-struct hciCmplLeSetAdvEnable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Set_Scan_Parameters                           0x000B /* complete */
-struct hciLeSetScanParams {
-	uint8_t activeScan;
-	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
-	uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */
-	uint8_t useOwnRandomAddr;
-	uint8_t onlyAllowlist;
-} __packed;
-struct hciCmplLeSetScanParams {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Set_Scan_Enable                               0x000C /* complete */
-struct hciLeSetScanEnable {
-	uint8_t scanOn;
-	uint8_t filterDuplicates;
-} __packed;
-struct hciCmplLeSetScanEnable {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Create_Connection                             0x000D /* status */
-struct hciLeCreateConnection {
-	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
-	uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */
-	uint8_t connectToAnyAllowlistedDevice; /* if so, ignore next 2 params */
-	uint8_t peerRandomAddr;
-	uint8_t peerMac[6];
-	uint8_t useOwnRandomAddr;
-	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x1F4 */
-	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-} __packed;
-
-#define HCI_CMD_LE_Create_Connection_Cancel                      0x000E /* complete */
-struct hciCmplLeCreateConnectionCancel {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Read_Allow_List_Size                          0x000F /* complete */
-struct hciCmplLeReadAllowListSize {
-	uint8_t status;
-	uint8_t allowlistSize;
-} __packed;
-
-#define HCI_CMD_LE_Clear_Allow_List                              0x0010 /* complete */
-struct hciCmplLeClearAllowList {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Add_Device_To_Allow_List                      0x0011 /* complete */
-struct hciLeAddDeviceToAllowList {
-	uint8_t randomAddr;
-	uint8_t mac[6];
-} __packed;
-struct hciCmplLeAddDeviceToAllowList {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Remove_Device_From_Allow_List                 0x0012 /* complete */
-struct hciLeRemoveDeviceFromAllowList {
-	uint8_t randomAddr;
-	uint8_t mac[6];
-} __packed;
-struct hciCmplLeRemoveDeviceFromAllowList {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Connection_Update                             0x0013 /* status */
-struct hciLeConnectionUpdate {
-	uint16_t conn;
-	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x1F4 */
-	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-} __packed;
-
-#define HCI_CMD_LE_Set_Host_Channel_Classification               0x0014 /* complete */
-struct hciLeSetHostChannelClassification {
-	uint8_t chMap[5];
-} __packed;
-struct hciCmplLeSetHostChannelClassification {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Read_Channel_Map                              0x0015 /* complete */
-struct hciLeReadChannelMap {
-	uint16_t conn;
-} __packed;
-struct hciCmplLeReadChannelMap {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t chMap[5];
-} __packed;
-
-#define HCI_CMD_LE_Read_Remote_Used_Features                     0x0016 /* status */
-struct hciLeReadRemoteUsedFeatures {
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_LE_Encrypt                                       0x0017 /* complete */
-struct hciLeEncrypt {
-	uint8_t key[16];
-	uint8_t plaintext[16];
-} __packed;
-struct hciCmplLeEncrypt {
-	uint8_t status;
-	uint8_t encryptedData[16];
-} __packed;
-
-#define HCI_CMD_LE_Rand                                          0x0018 /* complete */
-struct hciCmplLeRand {
-	uint8_t status;
-	uint64_t rand;
-} __packed;
-
-#define HCI_CMD_LE_Start_Encryption                              0x0019 /* status */
-struct hciLeStartEncryption {
-	uint16_t conn;
-	uint64_t rand;
-	uint16_t diversifier;
-	uint8_t LTK[16];
-} __packed;
-
-#define HCI_CMD_LE_LTK_Request_Reply                             0x001A /* complete */
-struct hciLeLtkRequestReply {
-	uint16_t conn;
-	uint8_t LTK[16];
-} __packed;
-struct hciCmplLeLtkRequestReply {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_LE_LTK_Request_Negative_Reply                    0x001B /* complete */
-struct hciLeLtkRequestNegativeReply {
-	uint16_t conn;
-} __packed;
-struct hciCmplLeLtkRequestNegativeReply {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_LE_Read_Supported_States                         0x001C /* complete */
-struct hciCmplLeReadSupportedStates {
-	uint8_t status;
-	uint64_t states; /* bitmask of HCI_LE_STATE_* */
-} __packed;
-
-#define HCI_CMD_LE_Receiver_Test                                 0x001D /* complete */
-struct hciLeReceiverTest {
-	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
-} __packed;
-struct hciCmplLeReceiverTest {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Transmitter_Test                              0x001E /* complete */
-struct hciLeTransmitterTest {
-	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
-	uint8_t lengthOfTestData;
-	uint8_t testPacketDataType;
-} __packed;
-struct hciCmplLeTransmitterTest {
-	uint8_t status;
-} __packed;
-
-#define HCI_CMD_LE_Test_End                                      0x001F /* complete */
-struct hciCmplLeTestEnd {
-	uint8_t status;
-	uint16_t numPackets;
-} __packed;
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply               0x0020 /* complete */
-struct hciLeRemoteConnParamRequestReply {
-	uint16_t conn;
-	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x1F4 */
-	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-} __packed;
-struct hciCmplLeRemoteConnParamRequestReply {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply      0x0021 /* complete */
-struct hciRemoteConnParamRequestNegativeReply {
-	uint16_t conn;
-	uint8_t reason;
-} __packed;
-struct hciCmplLeRemoteConnParamRequestNegativeReply {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-
-
-/* EVENTS */
-
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_EVT_Inquiry_Complete                                 0x01
-struct hciEvtInquiryComplete {
-	uint8_t status;
-} __packed;
-
-#define HCI_EVT_Inquiry_Result                                   0x02
-struct hciEvtInquiryResultItem {
-	uint8_t mac[6];
-	uint8_t PSRM;
-	uint8_t PSPM;
-	uint8_t PSM; /* obsoleted in BT 1.2+ */
-	uint8_t deviceClass[3];
-	uint16_t clockOffset;
-} __packed;
-struct hciEvtInquiryResult {
-	uint8_t numResponses;
-	struct hciEvtInquiryResultItem items[];
-} __packed;
-
-#define HCI_EVT_Connection_Complete                              0x03
-struct hciEvtConnComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t mac[6];
-	uint8_t isAclLink;
-	uint8_t encrypted;
-} __packed;
-
-#define HCI_EVT_Connection_Request                               0x04
-struct hciEvtConnRequest {
-	uint8_t mac[6];
-	uint8_t deviceClass[3];
-	uint8_t isAclLink;
-} __packed;
-
-#define HCI_EVT_Disconnection_Complete                           0x05
-struct hciEvtDiscComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t reason;
-} __packed;
-
-#define HCI_EVT_Authentication_Complete                          0x06
-struct hciEvtAuthComplete {
-	uint8_t status;
-	uint16_t handle;
-} __packed;
-
-#define HCI_EVT_Remote_Name_Request_Complete                     0x07
-struct hciEvtRemoteNameReqComplete {
-	uint8_t status;
-	uint8_t mac[6];
-	char name[HCI_DEV_NAME_LEN];
-} __packed;
-
-#define HCI_EVT_Encryption_Change                                0x08
-struct hciEvtEncrChange {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t encrOn;
-} __packed;
-
-#define HCI_EVT_Change_Connection_Link_Key_Complete              0x09
-struct hciEvtChangeConnLinkKeyComplete {
-	uint8_t status;
-	uint16_t handle;
-} __packed;
-
-#define HCI_EVT_Master_Link_Key_Complete                         0x0A
-struct hciEvtMasterLinkKeyComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t usingTempKey; /* else using semi-permanent key */
-} __packed;
-
-#define HCI_EVT_Read_Remote_Supported_Features_Complete          0x0B
-struct hciEvtReadRemoteSupportedFeaturesComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint64_t lmpFeatures; /* bitmask of HCI_LMP_FTR_* */
-} __packed;
-
-#define HCI_EVT_Read_Remote_Version_Complete                     0x0C
-struct hciEvtReadRemoteVersionComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t lmpVersion; /* HCI_VERSION_* */
-	uint16_t manufName;
-	uint16_t lmpSubversion;
-} __packed;
-
-#define HCI_EVT_QOS_Setup_Complete                               0x0D
-struct hciEvtQosSetupComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t flags;
-	uint8_t serviceType;
-	uint32_t tokenRate;
-	uint32_t peakBandwidth;
-	uint32_t latency;
-	uint32_t delayVariation;
-} __packed;
-
-#define HCI_EVT_Command_Complete                                 0x0E
-struct hciEvtCmdComplete {
-	uint8_t numCmdCredits;
-	uint16_t opcode;
-} __packed;
-
-#define HCI_EVT_Command_Status                                   0x0F
-struct hciEvtCmdStatus {
-	uint8_t status;
-	uint8_t numCmdCredits;
-	uint16_t opcode;
-} __packed;
-
-#define HCI_EVT_Hardware_Error                                   0x10
-struct hciEvtHwError {
-	uint8_t errCode;
-} __packed;
-
-#define HCI_EVT_Flush_Occurred                                   0x11
-struct hciEvtFlushOccurred {
-	uint16_t conn;
-} __packed;
-
-#define HCI_EVT_Role_Change                                      0x12
-struct hciEvtRoleChange {
-	uint8_t status;
-	uint8_t mac[6];
-	uint8_t amSlave;
-} __packed;
-
-#define HCI_EVT_Number_Of_Completed_Packets                      0x13
-struct hciEvtNumCompletedPacketsItem {
-	uint16_t conn;
-	uint16_t numPackets;
-} __packed;
-struct hciEvtNumCompletedPackets {
-	uint8_t numHandles;
-	struct hciEvtNumCompletedPacketsItem items[];
-} __packed;
-
-#define HCI_EVT_Mode_Change                                      0x14
-struct hciEvtModeChange {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t mode; /* HCI_CUR_MODE_* */
-	uint16_t interval; /* in units of 0.625ms 0..0xffff */
-} __packed;
-
-#define HCI_EVT_Return_Link_Keys                                 0x15
-struct hciEvtReturnLinkKeysItem {
-	uint8_t mac[6];
-	uint8_t key[16];
-} __packed;
-struct hciEvtReturnLinkKeys {
-	uint8_t numKeys;
-	struct hciEvtReturnLinkKeysItem items[];
-} __packed;
-
-#define HCI_EVT_PIN_Code_Request                                 0x16
-struct hciEvtPinCodeReq {
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Link_Key_Request                                 0x17
-struct hciEvtLinkKeyReq {
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Link_Key_Notification                            0x18
-struct hciEvtLinkKeyNotif {
-	uint8_t mac[6];
-	uint8_t key[16];
-	uint8_t keyType; /* HCI_KEY_TYPE_ */
-} __packed;
-
-#define HCI_EVT_Loopback_Command                                 0x19
-/* data is the sent command, up to 252 bytes of it */
-
-#define HCI_EVT_Data_Buffer_Overflow                             0x1A
-struct hciEvtDataBufferOverflow {
-	uint8_t aclLink;
-} __packed;
-
-#define HCI_EVT_Max_Slots_Change                                 0x1B
-struct hciEvtMaxSlotsChange {
-	uint16_t conn;
-	uint8_t lmpMaxSlots;
-} __packed;
-
-#define HCI_EVT_Read_Clock_Offset_Complete                       0x1C
-struct hciEvtReadClockOffsetComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t clockOffset;
-} __packed;
-
-#define HCI_EVT_Connection_Packet_Type_Changed                   0x1D
-struct hciEvtConnPacketTypeChanged {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t packetsAllowed; /* HCI_PKT_TYP_* */
-} __packed;
-
-#define HCI_EVT_QoS_Violation                                    0x1E
-struct hciEvtQosViolation {
-	uint16_t conn;
-} __packed;
-
-#define HCI_EVT_Page_Scan_Mode_Change                            0x1F /* deprecated in BT 1.2+ */
-struct hciEvtPsmChange {
-	uint8_t mac[6];
-	uint8_t PSM;
-} __packed;
-
-#define HCI_EVT_Page_Scan_Repetition_Mode_Change                 0x20
-struct hciEvtPrsmChange {
-	uint8_t mac[6];
-	uint8_t PSRM;
-} __packed;
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_EVT_Flow_Specification_Complete                      0x21
-struct hciEvtFlowSpecComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t flags;
-	uint8_t flowDirection;
-	uint8_t serviceType;
-	uint32_t tokenRate;
-	uint32_t peakBandwidth;
-	uint32_t latency;
-} __packed;
-
-#define HCI_EVT_Inquiry_Result_With_RSSI                         0x22
-struct hciEvtInquiryResultWithRssiItem {
-	uint8_t mac[6];
-	uint8_t PSRM;
-	uint8_t PSPM;
-	uint8_t deviceClass[3];
-	uint16_t clockOffset;
-	uint8_t RSSI; /* actually a int8_t */
-} __packed;
-struct hciEvtInquiryResultWithRssi {
-	uint8_t numResponses;
-	struct hciEvtInquiryResultWithRssiItem items[];
-} __packed;
-
-#define HCI_EVT_Read_Remote_Extended_Features_Complete           0x23
-struct hciEvtReadRemoteExtFeturesComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t pageNum;
-	uint8_t maxPageNum;
-	uint64_t extLmpFeatures; /* HCI_LMP_EXT_FTR_P* & HCI_LMP_FTR_* */
-} __packed;
-
-#define HCI_EVT_Synchronous_Connection_Complete                  0x2C
-struct hciEvtSyncConnComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t mac[6];
-	uint8_t linkType; /* HCI_SCO_LINK_TYPE_* */
-	uint8_t interval;
-	uint8_t retrWindow;
-	uint16_t rxPacketLen;
-	uint16_t txPacketLen;
-	uint8_t airMode; /* HCI_SCO_AIR_MODE_* */
-} __packed;
-
-#define HCI_EVT_Synchronous_Connection_Changed                   0x2D
-struct hciEvtSyncConnChanged {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t interval;
-	uint8_t retrWindow;
-	uint16_t rxPacketLen;
-	uint16_t txPacketLen;
-} __packed;
-
-
-/* ==== BT 2.1 ==== */
-
-#define HCI_EVT_Sniff_Subrating                                  0x2E
-struct hciEvtSniffSubrating {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t maxTxLatency;
-	uint16_t maxRxLatency;
-	uint16_t minRemoteTimeout;
-	uint16_t minLocalTimeout;
-} __packed;
-
-#define HCI_EVT_Extended_Inquiry_Result                          0x2F
-struct hciEvtExtendedInquiryResult {
-	uint8_t numResponses; /* must be 1 */
-	uint8_t mac[6];
-	uint8_t PSRM;
-	uint8_t reserved;
-	uint8_t deviceClass[3];
-	uint16_t clockOffset;
-	uint8_t RSSI; /* actually a int8_t */
-	uint8_t EIR[240];
-} __packed;
-
-#define HCI_EVT_Encryption_Key_Refresh_Complete                  0x30
-struct hciEvtEncrKeyRefreshComplete {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_EVT_IO_Capability_Request                            0x31
-struct hciEvtIoCapRequest {
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_IO_Capability_Response                           0x32
-struct hciEvtIoCapResponse {
-	uint8_t mac[6];
-	uint8_t ioCapability; /* HCI_DISPLAY_CAP_* */
-	uint8_t oobDataPresent;
-	uint8_t authReqments; /* HCI_AUTH_REQMENT_ */
-} __packed;
-
-#define HCI_EVT_User_Confirmation_Request                        0x33
-struct hciEvtUserConfRequest {
-	uint8_t mac[6];
-	uint32_t numericValue;
-} __packed;
-
-#define HCI_EVT_User_Passkey_Request                             0x34
-struct hciEvtUserPasskeyRequest {
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Remote_OOB_Data_Request                          0x35
-struct hciEvtRemoteOobRequest {
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Simple_Pairing_Complete                          0x36
-struct hciEvtSimplePairingComplete {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Link_Supervision_Timeout_Changed                 0x38
-struct hciEvtLinkSupervisionTimeoutChanged {
-	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625 ms 1..0xffff */
-} __packed;
-
-#define HCI_EVT_Enhanced_Flush_Complete                          0x39
-struct hciEvtEnahncedFlushComplete {
-	uint16_t conn;
-} __packed;
-
-#define HCI_EVT_User_Passkey_Notification                        0x3B
-struct hciEvtUserPasskeyNotif {
-	uint8_t mac[6];
-	uint32_t passkey;
-} __packed;
-
-#define HCI_EVT_Keypress_Notification                            0x3C
-struct hciEvtKeypressNotification {
-	uint8_t mac[6];
-	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
-} __packed;
-
-#define HCI_EVT_Remote_Host_Supported_Features_Notification      0x3D
-struct hciEvtRemoteHostSupportedFeatures {
-	uint8_t mac[6];
-	uint64_t hostSupportedFeatures; /* HCI_LMP_FTR_* */
-} __packed;
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_EVT_Physical_Link_Complete                           0x40
-struct hciEvtPhysLinkComplete {
-	uint8_t status;
-	uint8_t physLinkHandle;
-} __packed;
-
-#define HIC_EVT_Channel_Selected                                 0x41
-struct hciEvtChannelSelected {
-	uint8_t physLinkHandle;
-} __packed;
-
-#define HCI_EVT_Disconnection_Physical_Link_Complete             0x42
-struct hciEvtDiscPhysLinkComplete {
-	uint8_t status;
-	uint8_t physLinkHandle;
-	uint8_t reason;
-} __packed;
-
-#define HCI_EVT_Physical_Link_Loss_Early_Warning                 0x43
-struct hciEvtDiscPhysLinkLossEralyWarning {
-	uint8_t physLinkHandle;
-	uint8_t lossReason;
-} __packed;
-
-#define HCI_EVT_Physical_Link_Recovery                           0x44
-struct hciEvtDiscPhysLinkRecovery {
-	uint8_t physLinkHandle;
-} __packed;
-
-#define HCI_EVT_Logical_Link_Complete                            0x45
-struct hciEvtLogicalLinkComplete {
-	uint8_t status;
-	uint16_t logicalLinkHandle;
-	uint8_t physLinkHandle;
-	uint8_t txFlowSpecID;
-} __packed;
-
-#define HCI_EVT_Disconnection_Logical_Link_Complete              0x46
-struct hciEvtDiscLogicalLinkComplete {
-	uint8_t status;
-	uint16_t logicalLinkHandle;
-	uint8_t reason;
-} __packed;
-
-#define HCI_EVT_Flow_Spec_Modify_Complete                        0x47
-struct hciEvtFlowSpecModifyComplete {
-	uint8_t status;
-	uint16_t conn;
-} __packed;
-
-#define HCI_EVT_Number_Of_Completed_Data_Blocks                  0x48
-struct hciEvtNumCompletedDataBlocksItem {
-	uint16_t conn;
-	uint16_t numPackets;
-} __packed;
-struct hciEvtNumCompletedDataBlocks {
-	uint16_t totalNumBlocks;
-	uint8_t numberOfHandles;
-	struct hciEvtNumCompletedDataBlocksItem items[];
-} __packed;
-
-#define HCI_EVT_AMP_Start_Test                                   0x49
-struct hciEvtAmpStartTest {
-	uint8_t status;
-	uint8_t scenario;
-} __packed;
-
-#define HCI_EVT_AMP_Test_End                                     0x4A
-struct hciEvtAmpTestEnd {
-	uint8_t status;
-	uint8_t scenario;
-} __packed;
-
-#define HCI_EVT_AMP_Receiver_Report                              0x4B
-struct hciEvtampReceiverReport {
-	uint8_t controllerType;
-	uint8_t reason;
-	uint32_t eventType;
-	uint16_t numberOfFrames;
-	uint16_t numberOfErrorFrames;
-	uint32_t numberOfBits;
-	uint32_t numberOfErrorBits;
-} __packed;
-
-#define HCI_EVT_Short_Range_Mode_Change_Complete                 0x4C
-struct hciEvtshortRangeModeChangeComplete {
-	uint8_t status;
-	uint8_t physLinkHandle;
-	uint8_t shortRangeModeOn;
-} __packed;
-
-#define HCI_EVT_AMP_Status_Change                                0x4D
-struct hciEvtAmpStatusChange {
-	uint8_t status;
-	uint8_t ampStatus;
-} __packed;
-
-
-/* ==== BT 4.0 ==== */
-
-#define HCI_EVT_LE_Meta                                          0x3E
-struct hciEvtLeMeta {
-	uint8_t subevent;
-} __packed;
-
-#define HCI_EVTLE_Connection_Complete                            0x01
-struct hciEvtLeConnectionComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint8_t amSlave;
-	uint8_t peerAddrRandom;
-	uint8_t peerMac[6];
-	uint16_t connInterval; /* in units of 1.25 ms 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x01f3 */
-	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
-	uint8_t masterClockAccuracy; /* HCI_MCA_* */
-} __packed;
-
-#define HCI_EVTLE_Advertising_Report                             0x02
-struct hciEvtLeAdvReportItem {
-	uint8_t advType; /* HCI_ADV_TYPE_* */
-	uint8_t randomAddr;
-	uint8_t mac[6];
-	uint8_t dataLen;
-	uint8_t data[];
-/*  int8_t RSSI <-- this cannot be here due to variable data len, but in reality it is there */
-} __packed;
-struct hciEvtLeAdvReport {
-	uint8_t numReports;
-	/* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since data length is variable */
-} __packed;
-
-#define HCI_EVTLE_Connection_Update_Complete                     0x03
-struct hciEvtLeConnectionUpdateComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint16_t connInterval; /* in units of 1.25 ms 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x01f3 */
-	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
-} __packed;
-
-#define HCI_EVTLE_Read_Remote_Used_Features_Complete             0x04
-struct hciEvtLeReadRemoteFeaturesComplete {
-	uint8_t status;
-	uint16_t conn;
-	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
-} __packed;
-
-#define HCI_EVTLE_LTK_Request                                    0x05
-struct hciEvtLeLtkRequest {
-	uint16_t conn;
-	uint64_t randomNum;
-	uint16_t diversifier;
-} __packed;
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request       0x06
-struct hciEvtLeReadRemoteConnParamRequest {
-	uint16_t conn;
-	uint16_t connIntervalMin; /* in units of 1.25 ms 6..0x0C80 */
-	uint16_t connIntervalMax; /* in units of 1.25 ms 6..0x0C80 */
-	uint16_t connLatency; /* 0..0x01f3 */
-	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
-} __packed;
-
-#define HCI_EVT_Triggered_Clock_Capture                          0x4E
-struct hciEvtTriggeredClockCapture {
-	uint16_t conn;
-	uint8_t piconetClock;
-	uint32_t clock;
-	uint16_t slotOffset;
-} __packed;
-
-#define HCI_EVT_Synchronization_Train_Complete                   0x4F
-struct hciEvtSyncTrainComplete {
-	uint8_t status;
-} __packed;
-
-#define HCI_EVT_Synchronization_Train_Received                   0x50
-struct hciEvtSyncTrainReceived {
-	uint8_t status;
-	uint8_t mac[6];
-	uint32_t offset;
-	uint8_t afhChannelMap[10];
-	uint8_t ltAddr;
-	uint32_t nextBroadcastInstant;
-	uint16_t connectionlessSlaveBroadcastInterval;
-	uint8_t serviceData;
-} __packed;
-
-#define HCI_EVT_Connectionless_Slave_Broadcast_Receive           0x51
-struct hciEvtConnectionlessSlaveBroadcastReceive {
-	uint8_t mac[6];
-	uint8_t ltAddr;
-	uint32_t clk;
-	uint32_t offset;
-	uint8_t rxFailed;
-	uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */
-	uint8_t dataLen;
-	/* data */
-} __packed;
-
-#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout           0x52
-struct hciEvtConnectionlessSlaveBroadcastTimeout {
-	uint8_t mac[6];
-	uint8_t ltAddr;
-} __packed;
-
-#define HCI_EVT_Truncated_Page_Complete                          0x53
-struct hciEvtTruncatedPageComplete {
-	uint8_t status;
-	uint8_t mac[6];
-} __packed;
-
-#define HCI_EVT_Slave_Page_Response_Timeout                      0x54
-
-#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change      0x55
-struct hciEvtConnlessSlaveBroadcastChannelMapChange {
-	uint8_t map[10];
-} __packed;
-
-#define HCI_EVT_Inquiry_Response_Notification                    0x56
-struct hciEvtInquiryResponseNotif {
-	uint8_t lap[3];
-	uint8_t RSSI; /* actually an int8_t */
-} __packed;
-
-#define HCI_EVT_Authenticated_Payload_Timeout_Expired            0x57
-struct hciEvtAuthedPayloadTimeoutExpired {
-	uint16_t conn;
-} __packed;
-
-
-
-
-
-/* ERROR CODES */
-
-/* ==== BT 1.1 ==== */
-
-#define HCI_SUCCESS                                              0x00
-#define HCI_ERR_Unknown_HCI_Command                              0x01
-#define HCI_ERR_No_Connection                                    0x02
-#define HCI_ERR_Hardware_Failure                                 0x03
-#define HCI_ERR_Page_Timeout                                     0x04
-#define HCI_ERR_Authentication_Failure                           0x05
-#define HCI_ERR_Key_Missing                                      0x06
-#define HCI_ERR_Memory_Full                                      0x07
-#define HCI_ERR_Connection_Timeout                               0x08
-#define HCI_ERR_Max_Number_Of_Connections                        0x09
-#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device        0x0A
-#define HCI_ERR_ACL_Connection_Already_Exists                    0x0B
-#define HCI_ERR_Command_Disallowed                               0x0C
-#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources           0x0D
-#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons            0x0E
-#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device      0x0F
-#define HCI_ERR_Host_Timeout                                     0x10
-#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value           0x11
-#define HCI_ERR_Invalid_HCI_Command_Parameters                   0x12
-#define HCI_ERR_Other_End_Terminated_Connection_User_Requested   0x13
-#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources    0x14
-#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off   0x15
-#define HCI_ERR_Connection_Terminated_By_Local_Host              0x16
-#define HCI_ERR_Repeated_Attempts                                0x17
-#define HCI_ERR_Pairing_Not_Allowed                              0x18
-#define HCI_ERR_Unknown_LMP_PDU                                  0x19
-#define HCI_ERR_Unsupported_Remote_Feature                       0x1A
-#define HCI_ERR_SCO_Offset_Rejected                              0x1B
-#define HCI_ERR_SCO_Interval_Rejected                            0x1C
-#define HCI_ERR_SCO_Air_Mode_Rejected                            0x1D
-#define HCI_ERR_Invalid_LMP_Parameters                           0x1E
-#define HCI_ERR_Unspecified_Error                                0x1F
-#define HCI_ERR_Unsupported_LMP_Parameter                        0x20
-#define HCI_ERR_Role_Change_Not_Allowed                          0x21
-#define HCI_ERR_LMP_Response_Timeout                             0x22
-#define HCI_ERR_LMP_Error_Transaction_Collision                  0x23
-#define HCI_ERR_LMP_PDU_Not_Allowed                              0x24
-#define HCI_ERR_Encryption_Mode_Not_Acceptable                   0x25
-#define HCI_ERR_Unit_Key_Used                                    0x26
-#define HCI_ERR_QoS_Not_Supported                                0x27
-#define HCI_ERR_Instant_Passed                                   0x28
-#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported              0x29
-
-
-/* ==== BT 1.2 ==== */
-
-#define HCI_ERR_Different_Transaction_Collision                  0x2A
-#define HCI_ERR_QoS_Unacceptable_Parameter                       0x2C
-#define HCI_ERR_QoS_Rejected                                     0x2D
-#define HCI_ERR_Channel_Classification_Not_Supported             0x2E
-#define HCI_ERR_Insufficient_Security                            0x2F
-#define HCI_ERR_Parameter_Out_Of_Mandatory_Range                 0x30
-#define HCI_ERR_Role_Switch_Pending                              0x33
-#define HCI_ERR_Reserved_Slot_Violation                          0x34
-#define HIC_ERR_Role_Switch_Failed                               0x35
-
-
-/* ==== BT 2.1 ==== */
-
-#define HCI_ERR_EIR_Too_Large                                    0x36
-#define HCI_ERR_SSP_Not_Supported_By_Host                        0x37
-#define HCI_ERR_Host_Busy_Pairing                                0x38
-
-
-/* ==== BT 3.0 ==== */
-
-#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found    0x39
-#define HCI_ERR_Controller_Busy                                  0x3A
-
-
-/* ==== BT 4.0 ==== */
-
-#define HCI_ERR_Unacceptable_Connection_Interval                 0x3B
-#define HCI_ERR_Directed_Advertising_Timeout                     0x3C
-#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure         0x3D
-#define HCI_ERR_Connection_Failed_To_To_Established              0x3E
-#define HCI_ERR_MAC_Connection_Failed                            0x3F
-
-
-/* ==== BT 4.1 ==== */
-
-#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging    0x40
-
-
-
-#endif
-
diff --git a/include/byteorder.h b/include/byteorder.h
deleted file mode 100644
index 8cfd810e54..0000000000
--- a/include/byteorder.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_INCLUDE_BYTEORDER_H
-#define __EC_INCLUDE_BYTEORDER_H
-
-#include <endian.h>
-
-#endif  /* __EC_INCLUDE_BYTEORDER_H */
diff --git a/include/capsense.h b/include/capsense.h
deleted file mode 100644
index 2c0734aa4d..0000000000
--- a/include/capsense.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CAPSENSE_H
-#define __CROS_EC_CAPSENSE_H
-
-#include "common.h"
-#include "gpio.h"
-
-void capsense_interrupt(enum gpio_signal signal);
-
-#endif  /* __CROS_EC_CAPSENSE_H */
diff --git a/include/case_closed_debug.h b/include/case_closed_debug.h
deleted file mode 100644
index 53c8b1ed17..0000000000
--- a/include/case_closed_debug.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Case Closed Debug interface
- */
-#ifndef __CROS_EC_CASE_CLOSED_DEBUG_H
-#define __CROS_EC_CASE_CLOSED_DEBUG_H
-
-/**
- * Return non-zero if the CCD external interface is enabled.
- */
-int ccd_ext_is_enabled(void);
-
-#endif /* __CROS_EC_CASE_CLOSED_DEBUG_H */
diff --git a/include/cec.h b/include/cec.h
deleted file mode 100644
index b1ac6dbbb0..0000000000
--- a/include/cec.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ec_commands.h"
-
-/* Size of the buffer inside the rx queue */
-#define CEC_RX_BUFFER_SIZE 20
-#if CEC_RX_BUFFER_SIZE < MAX_CEC_MSG_LEN + 1
-#error "Buffer must fit at least a CEC message and a length byte"
-#endif
-#if CEC_RX_BUFFER_SIZE > 255
-#error "Buffer size must not exceed 255 since offsets are uint8_t"
-#endif
-
-/* CEC message during transfer */
-struct cec_msg_transfer {
-	/* Bit offset  */
-	uint8_t bit;
-	/* Byte offset */
-	uint8_t byte;
-	/* The CEC message */
-	uint8_t buf[MAX_CEC_MSG_LEN];
-};
-
-/*
- * Queue of completed incoming CEC messages
- * ready to be read out by AP
- */
-struct cec_rx_queue {
-	/*
-	 * Write offset. Updated from interrupt context when we
-	 * have received a complete message.
-	 */
-	uint8_t write_offset;
-	/* Read offset. Updated when AP sends CEC read command */
-	uint8_t read_offset;
-	/* Data buffer */
-	uint8_t buf[CEC_RX_BUFFER_SIZE];
-};
-
-/**
- * Get the current bit of a CEC message transfer
- *
- * @param queue		Queue to flush
- */
-int cec_transfer_get_bit(const struct cec_msg_transfer *transfer);
-
-/**
- * Set the current bit of a CEC message transfer
- *
- * @param transfer	Message transfer to set current bit of
- * @param val		New bit value
- */
-void cec_transfer_set_bit(struct cec_msg_transfer *transfer, int val);
-
-/**
- * Make the current bit the next bit in the transfer buffer
- *
- * @param transfer	Message transfer to change current bit of
- */
-void cec_transfer_inc_bit(struct cec_msg_transfer *transfer);
-
-/**
- * Check if current bit is an end-of-message bit and if it is set
- *
- * @param transfer	Message transfer to check for end-of-message
- */
-int cec_transfer_is_eom(const struct cec_msg_transfer *transfer, int len);
-
-/**
- * Flush all messages from a CEC receive queue
- *
- * @param queue		Queue to flush
- */
-void cec_rx_queue_flush(struct cec_rx_queue *queue);
-
-/**
- * Push a CEC message to a CEC receive queue
- *
- * @param queue		Queue to add message to
- */
-int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
-		      uint8_t msg_len);
-
-/**
- * Pop a CEC message from a CEC receive queue
- *
- * @param queue		Queue to retrieve message from
- * @param msg		Buffer to store retrieved message in
- * @param msg_len	Number of data bytes in msg
- */
-int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
-		     uint8_t *msg_len);
diff --git a/include/charge_ramp.h b/include/charge_ramp.h
deleted file mode 100644
index 0745f5ef98..0000000000
--- a/include/charge_ramp.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Charge input current limit ramp header for Chrome EC */
-
-#ifndef __CROS_EC_CHARGE_RAMP_H
-#define __CROS_EC_CHARGE_RAMP_H
-
-#include "timer.h"
-
-/* Charge ramp state used for checking VBUS */
-enum chg_ramp_vbus_state {
-	CHG_RAMP_VBUS_RAMPING,
-	CHG_RAMP_VBUS_STABLE
-};
-
-/**
- * Check if VBUS is too low
- *
- * @param port Charge ramp port
- * @param ramp_state Current ramp state
- *
- * @return VBUS is sagging low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state);
-
-/**
- * Check if ramping is allowed for given supplier
- *
- * @param port Charge ramp port
- * @supplier Supplier to check
- *
- * @return Ramping is allowed for given supplier
- */
-int chg_ramp_allowed(int port, int supplier);
-
-/**
- * Get the maximum current limit that we are allowed to ramp to
- *
- * @param port Charge ramp port
- * @supplier Active supplier type
- * @sup_curr Input current limit based on supplier
- *
- * @return Maximum current in mA
- */
-int chg_ramp_max(int port, int supplier, int sup_curr);
-
-/**
- * Get the input current limit set by ramp module
- *
- * Active input current limit (mA)
- */
-int chg_ramp_get_current_limit(void);
-
-/**
- * Return if charge ramping has reached stable state
- *
- * @return 1 if stable, 0 otherwise
- */
-int chg_ramp_is_stable(void);
-
-/**
- * Return if charge ramping has reached detected state
- *
- * @return 1 if detected, 0 otherwise
- */
-int chg_ramp_is_detected(void);
-
-#ifdef HAS_TASK_CHG_RAMP
-/**
- * Notify charge ramp module of supplier type change on a port. If port
- * is CHARGE_PORT_NONE, the call indicates the last charge supplier went
- * away.
- *
- * @port Active charging port
- * @supplier Active charging supplier
- * @current Minimum input current limit
- * @registration_time Timestamp of when the supplier is registered
- * @voltage Negotiated charge voltage.
- */
-void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-			     timestamp_t registration_time, int voltage);
-
-#else
-static inline void chg_ramp_charge_supplier_change(
-		int port, int supplier, timestamp_t registration_time) { }
-#endif
-
-#endif /* __CROS_EC_CHARGE_RAMP_H */
diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h
deleted file mode 100644
index 6bc8529a6e..0000000000
--- a/include/charge_state_v1.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "timer.h"
-
-#ifndef __CROS_EC_CHARGE_STATE_V1_H
-#define __CROS_EC_CHARGE_STATE_V1_H
-
-/* Update period to prevent charger watchdog timeout */
-#define CHARGER_UPDATE_PERIOD (SECOND * 10)
-
-/* Power state error flags */
-#define F_CHARGER_INIT        BIT(0) /* Charger initialization */
-#define F_CHARGER_VOLTAGE     BIT(1) /* Charger maximum output voltage */
-#define F_CHARGER_CURRENT     BIT(2) /* Charger maximum output current */
-#define F_BATTERY_VOLTAGE     BIT(3) /* Battery voltage */
-#define F_BATTERY_MODE        BIT(8) /* Battery mode */
-#define F_BATTERY_CAPACITY    BIT(9) /* Battery capacity */
-#define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */
-#define F_BATTERY_UNRESPONSIVE    BIT(11) /* Battery not responding */
-#define F_BATTERY_NOT_CONNECTED   BIT(12) /* Battery not connected */
-#define F_BATTERY_GET_PARAMS  BIT(13) /* Any battery parameter bad */
-
-#define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \
-			F_BATTERY_MODE | \
-			F_BATTERY_CAPACITY | F_BATTERY_STATE_OF_CHARGE | \
-			F_BATTERY_UNRESPONSIVE | F_BATTERY_NOT_CONNECTED | \
-			F_BATTERY_GET_PARAMS)
-#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | \
-			F_CHARGER_INIT)
-
-/* Power state data
- * Status collection of charging state machine.
- */
-struct charge_state_data {
-	int ac;
-	int charging_voltage;
-	int charging_current;
-	struct batt_params batt;
-	enum charge_state state;
-	uint32_t error;
-	timestamp_t ts;
-};
-
-/* State context
- * The shared context for state handler. The context contains current and
- * previous state.
- */
-struct charge_state_context {
-	struct charge_state_data curr;
-	struct charge_state_data prev;
-	timestamp_t charge_state_updated_time;
-	uint32_t *memmap_batt_volt;
-	uint32_t *memmap_batt_rate;
-	uint32_t *memmap_batt_cap;
-	uint8_t *memmap_batt_flags;
-	/* Charger and battery pack info */
-	const struct charger_info *charger;
-	const struct battery_info *battery;
-	/* Charging timestamps */
-	timestamp_t charger_update_time;
-	timestamp_t trickle_charging_time;
-	timestamp_t voltage_debounce_time;
-	timestamp_t shutdown_warning_time;
-	int battery_responsive;
-};
-
-#endif /* __CROS_EC_CHARGE_STATE_V1_H */
-
diff --git a/include/charger_detect.h b/include/charger_detect.h
deleted file mode 100644
index ae2001e418..0000000000
--- a/include/charger_detect.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Detect what adapter is connected */
-
-#ifndef __CROS_CHARGER_DETECT_H
-#define __CROS_CHARGER_DETECT_H
-
-/*
- * Get attached device type.
- *
- * @return CHARGE_SUPPLIER_BC12_* or 0 if the device type was not detected
- */
-int charger_detect_get_device_type(void);
-
-#endif /* __CROS_CHARGER_DETECT_H */
diff --git a/include/charger_profile_override.h b/include/charger_profile_override.h
deleted file mode 100644
index 091eb11946..0000000000
--- a/include/charger_profile_override.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Charger profile override for fast charging
- */
-
-#ifndef __CROS_EC_CHARGER_PROFILE_OVERRIDE_H
-#define __CROS_EC_CHARGER_PROFILE_OVERRIDE_H
-
-#include "charge_state_v2.h"
-
-#define TEMPC_TENTHS_OF_DEG(c) ((c) * 10)
-
-#define CHARGER_PROF_TEMP_C_LAST_RANGE 0xFFFF
-
-#define CHARGER_PROF_VOLTAGE_MV_LAST_RANGE 0xFFFF
-
-/* Charge profile override info */
-struct fast_charge_profile {
-	/* temperature in 10ths of a degree C */
-	const int temp_c;
-	/* charge current for respective battery voltage ranges in mA. */
-	const int current_mA[CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES];
-};
-
-/* Charge profile override parameters */
-struct fast_charge_params {
-	/* Total temperature ranges of the charge profile */
-	const int total_temp_ranges;
-	/* Default temperature range of the charge profile */
-	const int default_temp_range_profile;
-	/*
-	 * Battery voltage ranges in mV.
-	 * It is assumed that these values are added in ascending order in the
-	 * board battery file.
-	 */
-	const int voltage_mV[CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES];
-	const struct fast_charge_profile *chg_profile_info;
-};
-
-/**
- * Optional customization of charger profile override for fast charging.
- *
- * On input, the struct reflects the default behavior. The function can make
- * changes to the state, requested_voltage, or requested_current.
- *
- * @param curr Charge state machine data.
- *
- * @return
- *   >0    Desired time in usec for this poll period.
- *   0     Use the default poll period (which varies with the state).
- *  <0     An error occurred. The poll time will be shorter than usual.
- *         Too many errors in a row may trigger some corrective action.
- */
-int charger_profile_override(struct charge_state_data *curr);
-
-/**
- * Common code of charger profile override for fast charging.
- *
- * @param curr               Charge state machine data.
- * @param fast_chg_params    Fast charge profile parameters.
- * @param prev_chg_prof_info Previous charge profile info.
- * @param batt_vtg_max       Maximum battery voltage.
- *
- * @return
- *   >0    Desired time in usec for this poll period.
- *   0     Use the default poll period (which varies with the state).
- *  <0     An error occurred. The poll time will be shorter than usual.
- *         Too many errors in a row may trigger some corrective action.
- */
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max);
-
-/*
- * Access to custom profile params through host commands.
- * What this does is up to the implementation.
- */
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value);
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value);
-
-#endif /* __CROS_EC_CHARGER_PROFILE_OVERRIDE_H */
diff --git a/include/config.h b/include/config.h
index 2753cc715c..30224c9a95 100644
--- a/include/config.h
+++ b/include/config.h
@@ -6126,8 +6126,6 @@
  * override some of the config flags in non-standard ways to mock only parts of
  * the system.
  */
-#include "fuzz_config.h"
-#include "test_config.h"
 
 /*
  * Validity checks to make sure some of the configs above make sense.
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
deleted file mode 100644
index d272f5136c..0000000000
--- a/include/config_std_internal_flash.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
-#define __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
-
-/*
- * Standard memory-mapped flash layout:
- * - RO image starts at the beginning of flash.
- * - PSTATE immediately follows the RO image.
- * - RW image starts at the second half of flash.
- * - Protected region consists of the first half of flash (RO image + PSTATE).
- * - Unprotected region consists of second half of flash (RW image).
- *
- *                            PSTATE
- *                              |
- *                              v
- * |<-----Protected Region------>|<------Unprotected Region----->|
- * |<--------RO image--------->| |<----------RW image----------->|
- * 0                            N/2                              N
- *
- * This layout is used by several supported chips. Chips which do not use
- * this layout MUST NOT include this header file, and must instead define
- * the configs below in a chip-level header file (config_flash_layout.h).
- *
- * See the following page for additional image geometry discussion:
- *
- * https://www.chromium.org/chromium-os/ec-development/ec-image-geometry-spec
- *
- * TODO(crosbug.com/p/23796): Finish implementing the spec.
- */
-
-/*
- * Size of one firmware image in flash - half for RO, half for RW.
- * This is NOT a globally defined config, and is only used in this file
- * for convenience.
- */
-#define _IMAGE_SIZE		((CONFIG_FLASH_SIZE_BYTES - \
-				  CONFIG_SHAREDLIB_SIZE) / 2)
-
-/*
- * The EC uses the one bank of flash to emulate a SPI-like write protect
- * register with persistent state.
- */
-#define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE	CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF	(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-
-/*
- * By default, there is no shared objects library.  However, if configured, the
- * shared objects library will be placed after the RO image.
- */
-#define CONFIG_SHAREDLIB_MEM_OFF	(CONFIG_RO_MEM_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_STORAGE_OFF	(CONFIG_RO_STORAGE_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_SIZE	0
-
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF	(CONFIG_SHAREDLIB_MEM_OFF + \
-				 CONFIG_SHAREDLIB_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		_IMAGE_SIZE
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		(CONFIG_FLASH_SIZE_BYTES - \
-						 CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-#endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */
diff --git a/include/crc.h b/include/crc.h
deleted file mode 100644
index 04a82313d8..0000000000
--- a/include/crc.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CRC_H
-#define __CROS_EC_CRC_H
-/* CRC-32 implementation with USB constants */
-/* Note: it's a stateful CRC-32 to match the hardware block interface */
-
-#if defined(CONFIG_HW_CRC) && !defined(HOST_TOOLS_BUILD)
-#include "crc_hw.h"
-#else
-
-/* Use software implementation */
-
-/* Static context variant */
-
-void crc32_init(void);
-
-/**
- * Calculate CRC32 of data in arbitrary length.
- *
- * @param buf   Data for CRC32 to be calculated for.
- * @param size  Size of <buf> in bytes.
- */
-void crc32_hash(const void *buf, int size);
-
-void crc32_hash32(uint32_t val);
-
-void crc32_hash16(uint16_t val);
-
-uint32_t crc32_result(void);
-
-/* Provided context variant */
-
-void crc32_ctx_init(uint32_t *ctx);
-
-/**
- * Calculate CRC32 of data in arbitrary length using given context.
- *
- * @param crc   CRC32 context.
- * @param buf   Data for CRC32 to be calculated for.
- * @param size  Size of <buf> in bytes.
- */
-void crc32_ctx_hash(uint32_t *crc, const void *buf, int size);
-
-void crc32_ctx_hash32(uint32_t *ctx, uint32_t val);
-
-void crc32_ctx_hash16(uint32_t *ctx, uint16_t val);
-
-void crc32_ctx_hash8(uint32_t *ctx, uint8_t val);
-
-uint32_t crc32_ctx_result(uint32_t *ctx);
-
-#endif /* CONFIG_HW_CRC && !HOST_TOOLS_BUILD */
-
-#endif /* __CROS_EC_CRC_H */
diff --git a/include/crypto_api.h b/include/crypto_api.h
deleted file mode 100644
index 8a8ccacf99..0000000000
--- a/include/crypto_api.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __INCLUDE_CRYPTO_API_H
-#define __INCLUDE_CRYPTO_API_H
-
-#include "util.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Calculate hash of an arbitrary data
- *
- * Up to SHA_DIGEST_SIZE byte hash can be generated, if hash_len is
- * longer - it is padded with zeros.
- *
- * @param p_buf: pointer to beginning of data
- * @param num_bytes: length of data in bytes
- * @param p_hash: pointer to where computed hash will be stored
- * @param hash_len: length in bytes to use from sha computation. If this
- *		    value exceeds SHA1 size (20 bytes), the rest of the
- *		    hash is filled up with zeros.
- */
-void app_compute_hash(uint8_t *p_buf, size_t num_bytes,
-		      uint8_t *p_hash, size_t hash_len);
-
-#define CIPHER_SALT_SIZE 16
-
-/*
- * Encrypt/decrypt a flat blob.
- *
- * Encrypt or decrypt the input buffer, and write the correspondingly
- * ciphered output to out.  The number of bytes produced is equal to
- * the number of input bytes.
- *
- * This API is expected to be applied to a single contiguous region. WARNING:
- * Presently calling this function more than once with "in" pointing to
- * logically different buffers will result in using the same IV value
- * internally and as such reduce encryption efficiency.
- *
- * @param salt pointer to a unique value to be associated with this blob,
- *	       used for derivation of the proper IV, the size of this value
- *	       is as defined by CIPHER_SALT_SIZE above.
- *	       WARNING: a given salt/"in" pair must be unique (it is an ERROR
- *	       to use a given salt with more than one unique buffer).  For an
- *	       example, a good salt would be a digest of the plaintext input.
- * @param out Destination pointer where to write plaintext / ciphertext.
- * @param in  Source pointer where to read ciphertext / plaintext.
- * @param len Number of bytes to read from in / write to out.
- * @return non-zero on success, and zero otherwise.
- */
-int app_cipher(const void *salt, void *out, const void *in, size_t size);
-
-/*
- * Return a Boolean showing if crypto hardware is enabled.
- */
-int crypto_enabled(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __INCLUDE_CRYPTO_API_H */
diff --git a/include/curve25519.h b/include/curve25519.h
deleted file mode 120000
index b9943bd4ac..0000000000
--- a/include/curve25519.h
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/include/curve25519.h
\ No newline at end of file
diff --git a/include/device_event.h b/include/device_event.h
deleted file mode 100644
index 7a6403e51d..0000000000
--- a/include/device_event.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Device event module for Chrome EC */
-
-#ifndef __CROS_EC_DEVICE_EVENT_H
-#define __CROS_EC_DEVICE_EVENT_H
-
-#include "common.h"
-#include "ec_commands.h"
-
-/**
- * Return the raw device event state.
- */
-uint32_t device_get_events(void);
-
-/**
- * Set one or more device event bits.
- *
- * Call device_clear_events to unset event bits.
- *
- * @param mask          Event bits to set (use EC_DEVICE_EVENT_MASK()).
- */
-void device_set_events(uint32_t mask);
-
-/**
- * Clear one or more device event bits.
- *
- * @param mask          Event bits to clear (use EC_DEVICE_EVENT_MASK()).
- *                      Write 1 to a bit to clear it.
- */
-void device_clear_events(uint32_t mask);
-
-/**
- * Set a single device event.
- *
- * @param event         Event to set (EC_DEVICE_EVENT_*).
- */
-static inline void device_set_single_event(int event)
-{
-	device_set_events(EC_DEVICE_EVENT_MASK(event));
-}
-
-/**
- * Enable device event.
- *
- * @param event         Event to enable (EC_DEVICE_EVENT_*)
- */
-void device_enable_event(enum ec_device_event event);
-
-#endif  /* __CROS_EC_DEVICE_EVENT_H */
diff --git a/include/device_state.h b/include/device_state.h
deleted file mode 100644
index e7894ba998..0000000000
--- a/include/device_state.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_DEVICE_STATE_H
-#define __CROS_DEVICE_STATE_H
-
-enum gpio_signal;
-
-/* Device configuration */
-struct device_config {
-	/* Device name */
-	const char *name;
-
-	/* Current state */
-	enum device_state state;
-
-	/*
-	 * Last known state.  That is, the last state value passed to
-	 * device_set_state() which was DEVICE_STATE_OFF or DEVICE_STATE_ON.
-	 * Or DEVICE_STATE_UNKNOWN, if device_set_state() has not been called
-	 * for this device this boot.
-	 */
-	enum device_state last_known_state;
-
-	/*
-	 * Deferred handler to debounce state transitions. This is NOT used by
-	 * the device_state module; it's just here as a convenience for the
-	 * board.
-	 */
-	const struct deferred_data *deferred;
-
-	/*
-	 * GPIO used to detect the state.  This is NOT used by the device_state
-	 * module; it's just here as a convenience for the board.
-	 */
-	enum gpio_signal detect;
-};
-
-/*
- * board.h must supply an enumerated list of devices, ending in DEVICE_COUNT.
- */
-enum device_type;
-
-/*
- * board.c must provide this list of device configurations.  It must match enum
- * device_type, and must be DEVICE_COUNT entries long.
- */
-extern struct device_config device_states[];
-
-/**
- * Get the current state for the device.
- *
- * @param device	Device to check
- * @return The device state (current; NOT last known).
- */
-enum device_state device_get_state(enum device_type device);
-
-/**
- * Set the device state
- *
- * Updates the device's last known state if <state> is DEVICE_STATE_ON or
- * DEVICE_STATE_OFF, and that's different than the device's last known state.
- *
- * Note that this only changes the recorded state.  It does not notify anything
- * of these changes.  That must be done by the caller.
- *
- * @param device	Device to update
- * @param state		New device state
- * @return non-zero if this changed the device's last known state.
- */
-int device_set_state(enum device_type device, enum device_state state);
-
-/**
- * Update the device state based on the device gpios.
- *
- * The board must implement this.  It will be called for each device in the
- * context of HOOK_SECOND.  If the state has changed, the board is responsible
- * for doing any associated reconfiguration and then calling
- * device_set_state().
- *
- * @param device	Device to check.
- */
-void board_update_device_state(enum device_type device);
-
-#endif  /* __CROS_DEVICE_STATE_H */
diff --git a/include/display_7seg.h b/include/display_7seg.h
deleted file mode 100644
index cbaf33f458..0000000000
--- a/include/display_7seg.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Seven Segment Display module for Chrome EC */
-
-#ifndef __CROS_EC_DISPLAY_7SEG_H
-#define __CROS_EC_DISPLAY_7SEG_H
-
-enum seven_seg_module_display {
-	SEVEN_SEG_CONSOLE_DISPLAY,	/* Console data */
-	SEVEN_SEG_EC_DISPLAY,		/* power state */
-	SEVEN_SEG_PORT80_DISPLAY,	/* port80 data */
-};
-
-/**
- * Write register to MAX656x 7-segment display.
- *
- * @param module which is writing to the display
- * @param data to be displayed
- * @return EC_SUCCESS is write is successful
- */
-int display_7seg_write(enum seven_seg_module_display module, uint16_t data);
-
-#endif  /* __CROS_EC_DISPLAY_7SEG_H */
-
diff --git a/include/dps.h b/include/dps.h
deleted file mode 100644
index 151c6b3f09..0000000000
--- a/include/dps.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DPS__H
-#define __CROS_EC_DPS__H
-
-#include <stdbool.h>
-
-#include "common.h"
-
-/* Dynamic PDO Selection config. */
-struct dps_config_t {
-	/* (0, 100) coeff for transition to a lower power PDO*/
-	uint32_t k_less_pwr;
-	/* (0, 100) coeff for transition to a higher power PDO*/
-	uint32_t k_more_pwr;
-	/* Number for how many the same consecutive sample to transist */
-	uint32_t k_sample;
-	/* Number for moving average window for the power and the current. */
-	uint32_t k_window;
-	/* Power stabilized time after a new contract in us */
-	uint32_t t_stable;
-	/* Next power evaluation time interval in us */
-	uint32_t t_check;
-	/*
-	 * If the current voltage is more efficient than the previous voltage
-	 *
-	 * @param curr_mv: current PDO voltage
-	 * @param prev_mv: previous PDO voltage
-	 * @param batt_mv: battery desired voltage
-	 * @param batt_mw: current battery power
-	 * @param input_mw: current adapter input power
-	 * @return true is curr_mv is more efficient otherwise false
-	 */
-	bool (*is_more_efficient)(int curr_mv, int prev_mv, int batt_mv,
-				  int batt_mw, int input_mw);
-};
-
-/*
- * Get voltage in the current system load
- *
- * @return a voltage(mV) that the adapter supports to charge at the given port.
- */
-int dps_get_dynamic_voltage(void);
-
-/*
- * Get DPS charge port
- *
- * @return the DPS charge port, or CHARGE_PORT_NONE if unavailable.
- */
-int dps_get_charge_port(void);
-
-/*
- * Check if DPS is enabled.
- *
- * @return true if enabled, false otherwise.
- */
-bool dps_is_enabled(void);
-
-/*
- * Update DPS stablized timeout
- *
- * This is called at the exit of PE_SNK_TRANSITION_SINK
- *
- * @param port: the port for timer reset.
- */
-void dps_update_stabilized_time(int port);
-
-#endif /* __CROS_EC_DPS__H */
diff --git a/include/dptf.h b/include/dptf.h
deleted file mode 100644
index c34e8ea47a..0000000000
--- a/include/dptf.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions used to provide the Intel DPTF interface over ACPI */
-
-#ifndef __CROS_EC_DPTF_H
-#define __CROS_EC_DPTF_H
-
-/**
- * Set fan duty target.
- *
- * 0-100% sets fixed duty cycle, out of range means let the EC drive.
- */
-void dptf_set_fan_duty_target(int pct);
-
-/**
- * Return 0-100% if in duty mode. -1 if not.
- */
-int dptf_get_fan_duty_target(void);
-
-/* Thermal thresholds may be set for each temp sensor. */
-#define DPTF_THRESHOLDS_PER_SENSOR 2
-#define DPTF_THRESHOLD_HYSTERESIS 2
-
-/**
- * Set/enable the thresholds.
- */
-void dptf_set_temp_threshold(int sensor_id,	/* zero-based sensor index */
-			     int temp,		/* in degrees K */
-			     int idx,		/* which threshold (0 or 1) */
-			     int enable);	/* true = on, false = off */
-
-/**
- * Return the ID of a temp sensor that has crossed its threshold since the last
- * time we asked. -1 means none.
- */
-int dptf_query_next_sensor_event(void);
-
-/**
- * Set charging current limit, in mA.  -1 means no limit.
- */
-void dptf_set_charging_current_limit(int ma);
-
-/**
- * Get charging current limit, in mA, or -1 if not DPTF-limiting.
- */
-int dptf_get_charging_current_limit(void);
-
-#endif	/* __CROS_EC_DPTF_H */
diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h
deleted file mode 100644
index 3a46c7c050..0000000000
--- a/include/driver/accel_bma2x2.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMA2x2 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_ACCEL_BMA2x2_H
-#define __CROS_EC_ACCEL_BMA2x2_H
-
-#include "accel_bma2x2_public.h"
-
-/*** Chip-specific registers ***/
-/* REGISTER ADDRESS DEFINITIONS */
-#define BMA2x2_EEP_OFFSET			0x16
-#define BMA2x2_IMAGE_BASE			0x38
-#define BMA2x2_IMAGE_LEN			22
-#define BMA2x2_CHIP_ID_ADDR			0x00
-#define BMA255_CHIP_ID_MAJOR			0xfa
-
-/* DATA ADDRESS DEFINITIONS */
-#define BMA2x2_X_AXIS_LSB_ADDR			0x02
-#define BMA2x2_X_AXIS_MSB_ADDR			0x03
-#define BMA2x2_Y_AXIS_LSB_ADDR			0x04
-#define BMA2x2_Y_AXIS_MSB_ADDR			0x05
-#define BMA2x2_Z_AXIS_LSB_ADDR			0x06
-#define BMA2x2_Z_AXIS_MSB_ADDR			0x07
-#define BMA2x2_TEMP_ADDR			0x08
-
-#define BMA2x2_AXIS_LSB_NEW_DATA		0x01
-
-/* STATUS ADDRESS DEFINITIONS */
-#define BMA2x2_STAT1_ADDR			0x09
-#define BMA2x2_STAT2_ADDR			0x0A
-#define BMA2x2_STAT_TAP_SLOPE_ADDR		0x0B
-#define BMA2x2_STAT_ORIENT_HIGH_ADDR		0x0C
-#define BMA2x2_STAT_FIFO_ADDR			0x0E
-#define BMA2x2_RANGE_SELECT_ADDR		0x0F
-#define BMA2x2_RANGE_SELECT_MSK			0x0F
-#define BMA2x2_RANGE_2G				3
-#define BMA2x2_RANGE_4G				5
-#define BMA2x2_RANGE_8G				8
-#define BMA2x2_RANGE_16G			12
-
-#define BMA2x2_RANGE_TO_REG(_range) \
-	((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \
-			BMA2x2_RANGE_8G + ((_range) / 16) * 4)
-
-#define BMA2x2_REG_TO_RANGE(_reg) \
-	((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \
-				    8 + ((_reg) - BMA2x2_RANGE_8G) * 2)
-
-#define BMA2x2_BW_SELECT_ADDR			0x10
-#define BMA2x2_BW_MSK				0x1F
-#define BMA2x2_BW_7_81HZ			0x08 /* LowPass   7.8125HZ */
-#define BMA2x2_BW_15_63HZ			0x09 /* LowPass  15.625HZ */
-#define BMA2x2_BW_31_25HZ			0x0A /* LowPass  31.25HZ */
-#define BMA2x2_BW_62_50HZ			0x0B /* LowPass  62.50HZ */
-#define BMA2x2_BW_125HZ				0x0C /* LowPass 125HZ */
-#define BMA2x2_BW_250HZ				0x0D /* LowPass 250HZ */
-#define BMA2x2_BW_500HZ				0x0E /* LowPass 500HZ */
-#define BMA2x2_BW_1000HZ			0x0F /* LowPass 1000HZ */
-
-/* Do not use BW lower than 7813, because __fls cannot be call for 0 */
-#define BMA2x2_BW_TO_REG(_bw) \
-	((_bw) < 125000 ? \
-	 BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \
-	 BMA2x2_BW_125HZ + __fls((_bw) / 125000))
-
-#define  BMA2x2_REG_TO_BW(_reg) \
-	((_reg) < BMA2x2_BW_125HZ ? \
-	 (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \
-	 125000 << ((_reg) - BMA2x2_BW_125HZ))
-
-#define BMA2x2_MODE_CTRL_ADDR			0x11
-#define BMA2x2_LOW_NOISE_CTRL_ADDR		0x12
-#define BMA2x2_DATA_CTRL_ADDR			0x13
-#define BMA2x2_DATA_HIGH_BW			0x80
-#define BMA2x2_DATA_SHADOW_DIS			0x40
-#define BMA2x2_RST_ADDR				0x14
-#define BMA2x2_CMD_SOFT_RESET			0xb6
-
-/* INTERRUPT ADDRESS DEFINITIONS */
-#define BMA2x2_INTR_ENABLE1_ADDR		0x16
-#define BMA2x2_INTR_ENABLE2_ADDR		0x17
-#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR		0x18
-#define BMA2x2_INTR1_PAD_SELECT_ADDR		0x19
-#define BMA2x2_INTR_DATA_SELECT_ADDR		0x1A
-#define BMA2x2_INTR2_PAD_SELECT_ADDR		0x1B
-#define BMA2x2_INTR_SOURCE_ADDR			0x1E
-#define BMA2x2_INTR_SET_ADDR			0x20
-#define BMA2x2_INTR_CTRL_ADDR			0x21
-#define BMA2x2_INTR_CTRL_RST_INT		0x80
-
-/* FEATURE ADDRESS DEFINITIONS */
-#define BMA2x2_LOW_DURN_ADDR			0x22
-#define BMA2x2_LOW_THRES_ADDR			0x23
-#define BMA2x2_LOW_HIGH_HYST_ADDR		0x24
-#define BMA2x2_HIGH_DURN_ADDR			0x25
-#define BMA2x2_HIGH_THRES_ADDR			0x26
-#define BMA2x2_SLOPE_DURN_ADDR			0x27
-#define BMA2x2_SLOPE_THRES_ADDR			0x28
-#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR	0x29
-#define BMA2x2_TAP_PARAM_ADDR			0x2A
-#define BMA2x2_TAP_THRES_ADDR			0x2B
-#define BMA2x2_ORIENT_PARAM_ADDR		0x2C
-#define BMA2x2_THETA_BLOCK_ADDR			0x2D
-#define BMA2x2_THETA_FLAT_ADDR			0x2E
-#define BMA2x2_FLAT_HOLD_TIME_ADDR		0x2F
-#define BMA2x2_SELFTEST_ADDR			0x32
-#define BMA2x2_EEPROM_CTRL_ADDR			0x33
-#define BMA2x2_EEPROM_REMAIN_OFF		4
-#define BMA2x2_EEPROM_REMAIN_MSK		0xF0
-#define BMA2x2_EEPROM_LOAD			0x08
-#define BMA2x2_EEPROM_RDY			0x04
-#define BMA2x2_EEPROM_PROG			0x02
-#define BMA2x2_EEPROM_PROG_EN			0x01
-#define BMA2x2_SERIAL_CTRL_ADDR			0x34
-
-/* OFFSET ADDRESS DEFINITIONS */
-#define BMA2x2_OFFSET_CTRL_ADDR			0x36
-#define BMA2x2_OFFSET_RESET			0x80
-#define BMA2x2_OFFSET_TRIGGER_OFF		5
-#define BMA2x2_OFFSET_TRIGGER_MASK	(0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
-#define BMA2x2_OFFSET_CAL_READY			0x10
-#define BMA2x2_OFFSET_CAL_SLOW_X		0x04
-#define BMA2x2_OFFSET_CAL_SLOW_Y		0x02
-#define BMA2x2_OFFSET_CAL_SLOW_Z		0x01
-
-#define BMA2x2_OFC_SETTING_ADDR			0x37
-#define BMA2x2_OFC_TARGET_AXIS_OFF		1
-#define BMA2x2_OFC_TARGET_AXIS_LEN		2
-#define BMA2x2_OFC_TARGET_AXIS(_axis) \
-	(BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
-#define BMA2x2_OFC_TARGET_0G			0
-#define BMA2x2_OFC_TARGET_PLUS_1G		1
-#define BMA2x2_OFC_TARGET_MINUS_1G		2
-
-#define BMA2x2_OFFSET_X_AXIS_ADDR		0x38
-#define BMA2x2_OFFSET_Y_AXIS_ADDR		0x39
-#define BMA2x2_OFFSET_Z_AXIS_ADDR		0x3A
-
-/* GP ADDRESS DEFINITIONS */
-#define BMA2x2_GP0_ADDR				0x3B
-#define BMA2x2_GP1_ADDR				0x3C
-
-/* FIFO ADDRESS DEFINITIONS */
-#define BMA2x2_FIFO_MODE_ADDR			0x3E
-#define BMA2x2_FIFO_DATA_OUTPUT_ADDR		0x3F
-#define BMA2x2_FIFO_WML_TRIG			0x30
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMA2x2_RESOLUTION			12
-
-#endif /* __CROS_EC_ACCEL_BMA2x2_H */
diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h
deleted file mode 100644
index 6b3d366270..0000000000
--- a/include/driver/accel_bma2x2_public.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMA2x2 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H
-#define __CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H
-
-extern const struct accelgyro_drv bma2x2_accel_drv;
-
-/* I2C ADDRESS DEFINITIONS    */
-/* The following definition of I2C address is used for the following sensors
-* BMA253
-* BMA255
-* BMA355
-* BMA280
-* BMA282
-* BMA223
-* BMA254
-* BMA284
-* BMA250E
-* BMA222E
-*/
-#define BMA2x2_I2C_ADDR1_FLAGS              0x18
-#define BMA2x2_I2C_ADDR2_FLAGS              0x19
-
-/* The following definition of I2C address is used for the following sensors
-* BMC150
-* BMC056
-* BMC156
-*/
-#define BMA2x2_I2C_ADDR3_FLAGS              0x10
-#define BMA2x2_I2C_ADDR4_FLAGS              0x11
-
-/*
- * Min and Max sampling frequency in mHz.
- * Given BMA255 is polled, we limit max frequency to 125Hz.
- * If set to 250Hz, given we can read up to 3ms before the due time
- * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when
- * other sensors are active.
- */
-#define BMA255_ACCEL_MIN_FREQ           7810
-#define BMA255_ACCEL_MAX_FREQ \
-	MOTION_MAX_SENSOR_FREQUENCY(125000, 15625)
-
-#endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */
diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h
deleted file mode 100644
index 565376f319..0000000000
--- a/include/driver/accel_lis2dw12_public.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* LIS2DW12 gsensor module for Chrome EC */
-
-#ifndef __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H
-#define __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H
-
-#include "gpio.h"
-
-extern const struct accelgyro_drv lis2dw12_drv;
-
-/* I2C ADDRESS DEFINITIONS
- *
- * 7-bit address is 011000Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define LIS2DW12_ADDR0			0x18
-#define LIS2DW12_ADDR1			0x19
-
-#define LIS2DWL_ADDR0_FLAGS		0x18
-#define LIS2DWL_ADDR1_FLAGS		0x19
-
-#define LIS2DW12_EN_BIT			0x01
-#define LIS2DW12_DIS_BIT		0x00
-
-/* Absolute Acc rate. */
-#define LIS2DW12_ODR_MIN_VAL		12500
-#define LIS2DW12_ODR_MAX_VAL		\
-	MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL)
-
-void lis2dw12_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_DRIVER_ACCEL_LIS2DW12_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h
deleted file mode 100644
index c916576130..0000000000
--- a/include/driver/accelgyro_bmi160.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI160 accelerometer and gyro and BMM150 compass module for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI160_H
-#define __CROS_EC_ACCELGYRO_BMI160_H
-
-#include "accelgyro.h"
-#include "driver/accelgyro_bmi160_public.h"
-#include "mag_bmm150.h"
-
-#define BMI160_CHIP_ID           0x00
-#define BMI160_CHIP_ID_MAJOR     0xd1
-#define BMI168_CHIP_ID_MAJOR     0xd2
-
-#define BMI160_SPEC_ACC_STARTUP_TIME_MS     10
-#define BMI160_SPEC_GYR_STARTUP_TIME_MS     80
-#define BMI160_SPEC_MAG_STARTUP_TIME_MS     60
-
-
-#define BMI160_ERR_REG         0x02
-#define BMI160_PMU_STATUS      0x03
-#define BMI160_PMU_MAG_OFFSET               0
-#define BMI160_PMU_GYR_OFFSET               2
-#define BMI160_PMU_ACC_OFFSET               4
-#define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \
-	(((_val) >> (4 - 2 * (_sensor_type))) & 0x3)
-#define BMI160_PMU_SUSPEND                  0
-#define BMI160_PMU_NORMAL                   1
-#define BMI160_PMU_LOW_POWER                2
-#define BMI160_PMU_FAST_STARTUP             3
-
-#define BMI160_MAG_X_L_G       0x04
-#define BMI160_MAG_X_H_G       0x05
-#define BMI160_MAG_Y_L_G       0x06
-#define BMI160_MAG_Y_H_G       0x07
-#define BMI160_MAG_Z_L_G       0x08
-#define BMI160_MAG_Z_H_G       0x09
-#define BMI160_RHALL_L_G       0x0a
-#define BMI160_RHALL_H_G       0x0b
-#define BMI160_GYR_X_L_G       0x0c
-#define BMI160_GYR_X_H_G       0x0d
-#define BMI160_GYR_Y_L_G       0x0e
-#define BMI160_GYR_Y_H_G       0x0f
-#define BMI160_GYR_Z_L_G       0x10
-#define BMI160_GYR_Z_H_G       0x11
-#define BMI160_ACC_X_L_G       0x12
-#define BMI160_ACC_X_H_G       0x13
-#define BMI160_ACC_Y_L_G       0x14
-#define BMI160_ACC_Y_H_G       0x15
-#define BMI160_ACC_Z_L_G       0x16
-#define BMI160_ACC_Z_H_G       0x17
-
-#define BMI160_SENSORTIME_0    0x18
-#define BMI160_SENSORTIME_1    0x19
-#define BMI160_SENSORTIME_2    0x1a
-
-#define BMI160_STATUS          0x1b
-#define BMI160_POR_DETECTED        BIT(0)
-#define BMI160_GYR_SLF_TST         BIT(1)
-#define BMI160_MAG_MAN_OP          BIT(2)
-#define BMI160_FOC_RDY             BIT(3)
-#define BMI160_NVM_RDY             BIT(4)
-#define BMI160_DRDY_MAG            BIT(5)
-#define BMI160_DRDY_GYR            BIT(6)
-#define BMI160_DRDY_ACC            BIT(7)
-#define BMI160_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI160_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
-
-/* first 2 bytes are the interrupt reasons, next 2 some qualifier */
-#define BMI160_INT_STATUS_0    0x1c
-#define BMI160_STEP_INT            BIT(0)
-#define BMI160_SIGMOT_INT          BIT(1)
-#define BMI160_ANYM_INT            BIT(2)
-#define BMI160_PMU_TRIGGER_INT     BIT(3)
-#define BMI160_D_TAP_INT           BIT(4)
-#define BMI160_S_TAP_INT           BIT(5)
-#define BMI160_ORIENT_INT          BIT(6)
-#define BMI160_FLAT_INT            BIT(7)
-#define BMI160_ORIENT_XY_MASK	   0x30
-#define BMI160_ORIENT_PORTRAIT		(0 << 4)
-#define BMI160_ORIENT_PORTRAIT_INVERT	BIT(4)
-#define BMI160_ORIENT_LANDSCAPE		(2 << 4)
-#define BMI160_ORIENT_LANDSCAPE_INVERT	(3 << 4)
-
-
-#define BMI160_INT_STATUS_1    0x1d
-#define BMI160_HIGHG_INT           (1 << (2 + 8))
-#define BMI160_LOWG_INT            (1 << (3 + 8))
-#define BMI160_DRDY_INT            (1 << (4 + 8))
-#define BMI160_FFULL_INT           (1 << (5 + 8))
-#define BMI160_FWM_INT             (1 << (6 + 8))
-#define BMI160_NOMO_INT            (1 << (7 + 8))
-
-#define BMI160_INT_MASK            0xFFFF
-
-#define BMI160_INT_STATUS_2    0x1e
-#define BMI160_INT_STATUS_3    0x1f
-#define BMI160_FIRST_X             (1 << (0 + 16))
-#define BMI160_FIRST_Y             (1 << (1 + 16))
-#define BMI160_FIRST_Z             (1 << (2 + 16))
-#define BMI160_SIGN                (1 << (3 + 16))
-#define BMI160_ANYM_OFFSET         0
-#define BMI160_TAP_OFFSET          4
-#define BMI160_HIGH_OFFSET         8
-#define BMI160_INT_INFO(_type, _data) \
-(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET))
-
-#define BMI160_ORIENT_Z            (1 << (6 + 24))
-#define BMI160_FLAT                (1 << (7 + 24))
-
-#define BMI160_TEMPERATURE_0   0x20
-#define BMI160_TEMPERATURE_1   0x21
-
-
-#define BMI160_FIFO_LENGTH_0   0x22
-#define BMI160_FIFO_LENGTH_1   0x23
-#define BMI160_FIFO_LENGTH_MASK    (BIT(11) - 1)
-#define BMI160_FIFO_DATA       0x24
-
-#define BMI160_ACC_CONF        0x40
-#define BMI160_ACC_BW_OFFSET            4
-#define BMI160_ACC_BW_MASK     (0x7 << BMI160_ACC_BW_OFFSET)
-
-#define BMI160_ACC_RANGE       0x41
-#define BMI160_GSEL_2G         0x03
-#define BMI160_GSEL_4G         0x05
-#define BMI160_GSEL_8G         0x08
-#define BMI160_GSEL_16G        0x0c
-
-#define BMI160_GYR_CONF        0x42
-#define BMI160_GYR_BW_OFFSET   4
-#define BMI160_GYR_BW_MASK     (0x3 << BMI160_GYR_BW_OFFSET)
-
-#define BMI160_GYR_RANGE       0x43
-#define BMI160_DPS_SEL_2000    0x00
-#define BMI160_DPS_SEL_1000    0x01
-#define BMI160_DPS_SEL_500     0x02
-#define BMI160_DPS_SEL_250     0x03
-#define BMI160_DPS_SEL_125     0x04
-
-#define BMI160_MAG_CONF        0x44
-
-#define BMI160_FIFO_DOWNS      0x45
-#define BMI160_FIFO_CONFIG_0   0x46
-#define BMI160_FIFO_CONFIG_1   0x47
-#define BMI160_FIFO_TAG_TIME_EN    BIT(1)
-#define BMI160_FIFO_TAG_INT2_EN    BIT(2)
-#define BMI160_FIFO_TAG_INT1_EN    BIT(3)
-#define BMI160_FIFO_HEADER_EN      BIT(4)
-#define BMI160_FIFO_MAG_EN         BIT(5)
-#define BMI160_FIFO_ACC_EN         BIT(6)
-#define BMI160_FIFO_GYR_EN         BIT(7)
-#define BMI160_FIFO_TARG_INT(_i)  CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN)
-#define BMI160_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \
-	   BMI160_FIFO_MAG_EN))
-
-#define BMI160_MAG_IF_0        0x4b
-#define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0
-#define BMI160_MAG_IF_1        0x4c
-#define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1
-#define BMI160_MAG_READ_BURST_MASK 3
-#define BMI160_MAG_READ_BURST_1    0
-#define BMI160_MAG_READ_BURST_2    1
-#define BMI160_MAG_READ_BURST_6    2
-#define BMI160_MAG_READ_BURST_8    3
-#define BMI160_MAG_OFFSET_OFF      3
-#define BMI160_MAG_OFFSET_MASK     (0xf << BMI160_MAG_OFFSET_OFF)
-#define BMI160_MAG_MANUAL_EN       BIT(7)
-
-#define BMI160_MAG_IF_2        0x4d
-#define BMI160_MAG_I2C_READ_ADDR    BMI160_MAG_IF_2
-#define BMI160_MAG_IF_3        0x4e
-#define BMI160_MAG_I2C_WRITE_ADDR   BMI160_MAG_IF_3
-#define BMI160_MAG_IF_4        0x4f
-#define BMI160_MAG_I2C_WRITE_DATA   BMI160_MAG_IF_4
-#define BMI160_MAG_I2C_READ_DATA    BMI160_MAG_X_L_G
-
-#define BMI160_INT_EN_0        0x50
-#define BMI160_INT_ANYMO_X_EN      BIT(0)
-#define BMI160_INT_ANYMO_Y_EN      BIT(1)
-#define BMI160_INT_ANYMO_Z_EN      BIT(2)
-#define BMI160_INT_D_TAP_EN        BIT(4)
-#define BMI160_INT_S_TAP_EN        BIT(5)
-#define BMI160_INT_ORIENT_EN       BIT(6)
-#define BMI160_INT_FLAT_EN         BIT(7)
-#define BMI160_INT_EN_1        0x51
-#define BMI160_INT_HIGHG_X_EN      BIT(0)
-#define BMI160_INT_HIGHG_Y_EN      BIT(1)
-#define BMI160_INT_HIGHG_Z_EN      BIT(2)
-#define BMI160_INT_LOW_EN          BIT(3)
-#define BMI160_INT_DRDY_EN         BIT(4)
-#define BMI160_INT_FFUL_EN         BIT(5)
-#define BMI160_INT_FWM_EN          BIT(6)
-#define BMI160_INT_EN_2        0x52
-#define BMI160_INT_NOMOX_EN        BIT(0)
-#define BMI160_INT_NOMOY_EN        BIT(1)
-#define BMI160_INT_NOMOZ_EN        BIT(2)
-#define BMI160_INT_STEP_DET_EN     BIT(3)
-
-#define BMI160_INT_OUT_CTRL    0x53
-#define BMI160_INT_EDGE_CTRL       BIT(0)
-#define BMI160_INT_LVL_CTRL        BIT(1)
-#define BMI160_INT_OD              BIT(2)
-#define BMI160_INT_OUTPUT_EN       BIT(3)
-#define BMI160_INT1_CTRL_OFFSET     0
-#define BMI160_INT2_CTRL_OFFSET     4
-#define BMI160_INT_CTRL(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET))
-
-#define BMI160_INT_LATCH       0x54
-#define BMI160_INT1_INPUT_EN       BIT(4)
-#define BMI160_INT2_INPUT_EN       BIT(5)
-#define BMI160_LATCH_MASK          0xf
-#define BMI160_LATCH_NONE          0
-#define BMI160_LATCH_5MS           5
-#define BMI160_LATCH_FOREVER       0xf
-
-#define BMI160_INT_MAP_0       0x55
-#define BMI160_INT_LOWG_STEP       BIT(0)
-#define BMI160_INT_HIGHG           BIT(1)
-#define BMI160_INT_ANYMOTION       BIT(2)
-#define BMI160_INT_NOMOTION        BIT(3)
-#define BMI160_INT_D_TAP           BIT(4)
-#define BMI160_INT_S_TAP           BIT(5)
-#define BMI160_INT_ORIENT          BIT(6)
-#define BMI160_INT_FLAT            BIT(7)
-
-#define BMI160_INT_MAP_1       0x56
-#define BMI160_INT_PMU_TRIG        BIT(0)
-#define BMI160_INT_FFULL           BIT(1)
-#define BMI160_INT_FWM             BIT(2)
-#define BMI160_INT_DRDY            BIT(3)
-#define BMI160_INT1_MAP_OFFSET      4
-#define BMI160_INT2_MAP_OFFSET      0
-#define BMI160_INT_MAP(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET))
-#define BMI160_INT_FIFO_MAP    BMI160_INT_MAP_1
-
-#define BMI160_INT_MAP_2       0x57
-
-#define BMI160_INT_MAP_INT_1   BMI160_INT_MAP_0
-#define BMI160_INT_MAP_INT_2   BMI160_INT_MAP_2
-#define BMI160_INT_MAP_REG(_i)  CONCAT2(BMI160_INT_MAP_INT_, _i)
-
-#define BMI160_INT_DATA_0      0x58
-#define BMI160_INT_DATA_1      0x59
-
-#define BMI160_INT_LOW_HIGH_0  0x5a
-#define BMI160_INT_LOW_HIGH_1  0x5b
-#define BMI160_INT_LOW_HIGH_2  0x5c
-#define BMI160_INT_LOW_HIGH_3  0x5d
-#define BMI160_INT_LOW_HIGH_4  0x5e
-
-#define BMI160_INT_MOTION_0    0x5f
-#define BMI160_INT_MOTION_1    0x60
-/*
- * The formula is defined in 2.11.25 (any motion interrupt [1]).
- *
- * if we want threshold at a (in mg), the register should be x, where
- * x * 7.81mg = a, assuming a range of 4G, which is
- * x * 4 * 1.953 = a so
- * x = a * 1000 / range * 1953
- */
-#define BMI160_MOTION_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->current_range * 1953), 0xff))
-#define BMI160_INT_MOTION_2    0x61
-#define BMI160_INT_MOTION_3    0x62
-#define BMI160_MOTION_NO_MOT_SEL   BIT(0)
-#define BMI160_MOTION_SIG_MOT_SEL  BIT(1)
-#define BMI160_MOTION_SKIP_OFF 2
-#define BMI160_MOTION_SKIP_MASK 0x3
-#define BMI160_MOTION_SKIP_TIME(_ms) \
-	(MIN(__fls((_ms) / 1500), BMI160_MOTION_SKIP_MASK))
-#define BMI160_MOTION_PROOF_OFF 4
-#define BMI160_MOTION_PROOF_MASK 0x3
-#define BMI160_MOTION_PROOF_TIME(_ms) \
-	(MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK))
-
-#define BMI160_INT_TAP_0       0x63
-#define BMI160_TAP_DUR(_s, _ms) \
-	((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \
-	 (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \
-	 (_ms) < 700 ? 6 : 7)
-
-#define BMI160_INT_TAP_1       0x64
-#define BMI160_TAP_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->current_range * 31250), 0x1f))
-
-#define BMI160_INT_ORIENT_0				0x65
-
-/* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */
-#define BMI160_INT_ORIENT_0_INIT_VAL			0x48
-
-#define BMI160_INT_ORIENT_1				0x66
-
-/* no axes remap, no int on up/down, no blocking angle */
-#define BMI160_INT_ORIENT_1_INIT_VAL			0x00
-
-#define BMI160_INT_FLAT_0      0x67
-#define BMI160_INT_FLAT_1      0x68
-
-#define BMI160_FOC_CONF        0x69
-#define BMI160_FOC_GYRO_EN              BIT(6)
-#define BMI160_FOC_ACC_PLUS_1G          1
-#define BMI160_FOC_ACC_MINUS_1G         2
-#define BMI160_FOC_ACC_0G               3
-#define BMI160_FOC_ACC_Z_OFFSET         0
-#define BMI160_FOC_ACC_Y_OFFSET         2
-#define BMI160_FOC_ACC_X_OFFSET         4
-
-#define BMI160_CONF            0x6a
-#define BMI160_IF_CONF         0x6b
-#define BMI160_IF_MODE_OFF     4
-#define BMI160_IF_MODE_MASK    3
-#define BMI160_IF_MODE_AUTO_OFF 0
-#define BMI160_IF_MODE_I2C_IOS  1
-#define BMI160_IF_MODE_AUTO_I2C 2
-
-#define BMI160_PMU_TRIGGER     0x6c
-#define BMI160_SELF_TEST       0x6d
-
-#define BMI160_NV_CONF         0x70
-
-#define BMI160_OFFSET_ACC70        0x71
-#define BMI160_OFFSET_GYR70        0x74
-#define BMI160_OFFSET_EN_GYR98     0x77
-#define BMI160_OFFSET_ACC_EN            BIT(6)
-#define BMI160_OFFSET_GYRO_EN           BIT(7)
-
-#define BMI160_STEP_CNT_0          0x78
-#define BMI160_STEP_CNT_1          0x79
-#define BMI160_STEP_CONF_0         0x7a
-#define BMI160_STEP_CONF_1         0x7b
-
-#define BMI160_CMD_REG             0x7e
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_NOOP            0x00
-#define BMI160_CMD_START_FOC       0x03
-#define BMI160_CMD_ACC_MODE_OFFSET 0x10
-#define BMI160_CMD_ACC_MODE_SUSP   0x10
-#define BMI160_CMD_ACC_MODE_NORMAL 0x11
-#define BMI160_CMD_ACC_MODE_LOWPOWER 0x12
-#define BMI160_CMD_GYR_MODE_SUSP   0x14
-#define BMI160_CMD_GYR_MODE_NORMAL 0x15
-#define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17
-#define BMI160_CMD_MAG_MODE_SUSP   0x18
-#define BMI160_CMD_MAG_MODE_NORMAL 0x19
-#define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a
-#define BMI160_CMD_MODE_SUSPEND(_sensor_type) \
-	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_SUSPEND)
-#define BMI160_CMD_MODE_NORMAL(_sensor_type) \
-	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL)
-
-#define BMI160_CMD_FIFO_FLUSH      0xb0
-#define BMI160_CMD_INT_RESET       0xb1
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_EXT_MODE_EN_B0  0x37
-#define BMI160_CMD_EXT_MODE_EN_B1  0x9a
-#define BMI160_CMD_EXT_MODE_EN_B2  0xc0
-
-#define BMI160_CMD_EXT_MODE_ADDR   0x7f
-#define BMI160_CMD_PAGING_EN           BIT(7)
-#define BMI160_CMD_TARGET_PAGE         BIT(4)
-#define BMI160_COM_C_TRIM_ADDR 0x85
-#define BMI160_COM_C_TRIM              (3 << 4)
-
-#define BMI160_CMD_TGT_PAGE    0
-#define BMI160_CMD_TGT_PAGE_COM    1
-#define BMI160_CMD_TGT_PAGE_ACC    2
-#define BMI160_CMD_TGT_PAGE_GYR    3
-
-#define BMI160_FF_FRAME_LEN_TS          4
-#define BMI160_FF_DATA_LEN_ACC          6
-#define BMI160_FF_DATA_LEN_GYR          6
-#define BMI160_FF_DATA_LEN_MAG          8
-
-/* Root mean square noise of 100 Hz accelerometer, units: ug */
-#define BMI160_ACCEL_RMS_NOISE_100HZ    1300
-
-#ifdef CONFIG_BMI_SEC_I2C
-/* Functions to access the secondary device through the accel/gyro. */
-int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags,
-			 const uint8_t reg, int *data_ptr);
-int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags,
-			  const uint8_t reg, int data);
-#endif
-
-#endif /* __CROS_EC_ACCELGYRO_BMI160_H */
diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h
deleted file mode 100644
index 6a6890eb84..0000000000
--- a/include/driver/accelgyro_bmi160_public.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI160 accelerometer and gyro for Chrome EC */
-
-#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI160_PUBLIC_H
-#define __CROS_EC_DRIVER_ACCELGYRO_BMI160_PUBLIC_H
-
-/*
- * The addr field of motion_sensor support both SPI and I2C:
- * This is defined in include/i2c.h and is no longer an 8bit
- * address. The 7/10 bit address starts at bit 0 and leaves
- * room for a 10 bit address, although we don't currently
- * have any 10 bit peripherals. I2C or SPI is indicated by a
- * more significant bit
- */
-
-/* I2C addresses */
-#define BMI160_ADDR0_FLAGS      0x68
-
-extern const struct accelgyro_drv bmi160_drv;
-
-void bmi160_interrupt(enum gpio_signal signal);
-int bmi160_get_sensor_temp(int idx, int *temp_ptr);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev bmi160_i2c_stress_test_dev;
-#endif
-
-#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h
deleted file mode 100644
index 86c05a0697..0000000000
--- a/include/driver/accelgyro_bmi260.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI260 accelerometer and gyro for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI260_H
-#define __CROS_EC_ACCELGYRO_BMI260_H
-
-#include "accelgyro.h"
-#include "common.h"
-#include "mag_bmm150.h"
-#include "driver/accelgyro_bmi260_public.h"
-
-#define BMI260_CHIP_ID      0x00
-#define BMI260_CHIP_ID_MAJOR    0x27
-
-#define BMI260_ERR_REG          0x02
-
-#define BMI260_STATUS           0x03
-#define BMI260_AUX_BUSY             BIT(2)
-#define BMI260_CMD_RDY              BIT(4)
-#define BMI260_DRDY_AUX             BIT(5)
-#define BMI260_DRDY_GYR             BIT(6)
-#define BMI260_DRDY_ACC             BIT(7)
-#define BMI260_DRDY_OFF(_sensor)    (7 - (_sensor))
-#define BMI260_DRDY_MASK(_sensor)   (1 << BMI260_DRDY_OFF(_sensor))
-
-#define BMI260_AUX_X_L_G           0x04
-#define BMI260_AUX_X_H_G           0x05
-#define BMI260_AUX_Y_L_G           0x06
-#define BMI260_AUX_Y_H_G           0x07
-#define BMI260_AUX_Z_L_G           0x08
-#define BMI260_AUX_Z_H_G           0x09
-#define BMI260_AUX_R_L_G           0x0a
-#define BMI260_AUX_R_H_G           0x0b
-#define BMI260_ACC_X_L_G           0x0c
-#define BMI260_ACC_X_H_G           0x0d
-#define BMI260_ACC_Y_L_G           0x0e
-#define BMI260_ACC_Y_H_G           0x0f
-#define BMI260_ACC_Z_L_G           0x10
-#define BMI260_ACC_Z_H_G           0x11
-#define BMI260_GYR_X_L_G           0x12
-#define BMI260_GYR_X_H_G           0x13
-#define BMI260_GYR_Y_L_G           0x14
-#define BMI260_GYR_Y_H_G           0x15
-#define BMI260_GYR_Z_L_G           0x16
-#define BMI260_GYR_Z_H_G           0x17
-
-#define BMI260_SENSORTIME_0     0x18
-#define BMI260_SENSORTIME_1     0x19
-#define BMI260_SENSORTIME_2     0x1a
-
-#define BMI260_EVENT            0x1b
-
-/* 2 bytes interrupt reasons*/
-#define BMI260_INT_STATUS_0     0x1c
-#define BMI260_SIG_MOTION_OUT       BIT(0)
-#define BMI260_STEP_COUNTER_OUT     BIT(1)
-#define BMI260_HIGH_LOW_G_OUT       BIT(2)
-#define BMI260_TAP_OUT              BIT(3)
-#define BMI260_FLAT_OUT             BIT(4)
-#define BMI260_NO_MOTION_OUT        BIT(5)
-#define BMI260_ANY_MOTION_OUT       BIT(6)
-#define BMI260_ORIENTATION_OUT      BIT(7)
-
-#define BMI260_INT_STATUS_1     0x1d
-#define BMI260_FFULL_INT            BIT(0 + 8)
-#define BMI260_FWM_INT              BIT(1 + 8)
-#define BMI260_ERR_INT              BIT(2 + 8)
-#define BMI260_AUX_DRDY_INT         BIT(5 + 8)
-#define BMI260_GYR_DRDY_INT         BIT(6 + 8)
-#define BMI260_ACC_DRDY_INT         BIT(7 + 8)
-
-#define BMI260_INT_MASK             0xFFFF
-
-#define BMI260_SC_OUT_0         0x1e
-#define BMI260_SC_OUT_1         0x1f
-
-#define BMI260_ORIENT_ACT       0x20
-
-#define BMI260_INTERNAL_STATUS  0X21
-#define BMI260_MESSAGE_MASK         0xf
-#define BMI260_NOT_INIT             0x00
-#define BMI260_INIT_OK              0x01
-#define BMI260_INIT_ERR             0x02
-#define BMI260_DRV_ERR              0x03
-#define BMI260_SNS_STOP             0x04
-#define BMI260_NVM_ERROR            0x05
-#define BMI260_START_UP_ERROR       0x06
-#define BMI260_COMPAT_ERROR         0x07
-
-#define BMI260_TEMPERATURE_0    0x22
-#define BMI260_TEMPERATURE_1    0x23
-
-#define BMI260_FIFO_LENGTH_0    0x24
-#define BMI260_FIFO_LENGTH_1    0x25
-#define BMI260_FIFO_LENGTH_MASK     (BIT(14) - 1)
-#define BMI260_FIFO_DATA        0x26
-
-#define BMI260_FEAT_PAGE        0x2f
-/*
- * The register of feature page should be read/write as 16-bit register
- * Otherwise, there can be invalid data
- */
-/* Features page 0 */
-#define BMI260_ORIENT_OUT       0x36
-#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK   3
-#define BMI260_ORIENT_PORTRAIT                      0x0
-#define BMI260_ORIENT_LANDSCAPE                     0x1
-#define BMI260_ORIENT_PORTRAIT_INVERT               0x2
-#define BMI260_ORIENT_LANDSCAPE_INVERT              0x3
-
-/* Features page 1 */
-#define BMI260_GEN_SET_1        0x34
-#define BMI260_GYR_SELF_OFF         BIT(9)
-
-#define BMI260_TAP_1            0x3e
-#define BMI260_TAP_1_EN                     BIT(0)
-#define BMI260_TAP_1_SENSITIVITY_OFFSET     1
-#define BMI260_TAP_1_SENSITIVITY_MASK       \
-	(0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET)
-
-/* Features page 2 */
-#define BMI260_ORIENT_1         0x30
-#define BMI260_ORIENT_1_EN          BIT(0)
-#define BMI260_ORIENT_1_UD_EN       BIT(1)
-#define BMI260_ORIENT_1_MODE_OFFSET 2
-#define BMI260_ORIENT_1_MODE_MASK   (0x3 << BMI260_ORIENT_1_MODE_OFFSET)
-#define BMI260_ORIENT_1_BLOCK_OFFSET    4
-#define BMI260_ORIENT_1_BLOCK_MASK      (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET)
-#define BMI260_ORIENT_1_THETA_OFFSET     6
-#define BMI260_ORIENT_1_THETA_MASK      \
-	((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET)
-
-#define BMI260_ORIENT_2         0x32
-/* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */
-#define BMI260_ORIENT_2_HYSTERESIS_MASK     (BIT(11) - 1)
-
-#define BMI260_ACC_CONF         0x40
-#define BMI260_ACC_BW_OFFSET        4
-#define BMI260_ACC_BW_MASK          (0x7 << BMI260_ACC_BW_OFFSET)
-#define BMI260_FILTER_PERF          BIT(7)
-#define BMI260_ULP                  0x0
-#define BMI260_HP                   0x1
-
-#define BMI260_ACC_RANGE        0x41
-#define BMI260_GSEL_2G              0x00
-#define BMI260_GSEL_4G              0x01
-#define BMI260_GSEL_8G              0x02
-#define BMI260_GSEL_16G             0x03
-
-/* The max positvie value of accel data is 0x7FFF, equal to range(g) */
-/* So, in order to get +1g, divide the 0x7FFF by range */
-#define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
-#define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range))
-
-#define BMI260_GYR_CONF         0x42
-#define BMI260_GYR_BW_OFFSET        4
-#define BMI260_GYR_BW_MASK          (0x3 << BMI260_GYR_BW_OFFSET)
-#define BMI260_GYR_NOISE_PERF       BIT(6)
-
-#define BMI260_GYR_RANGE        0x43
-#define BMI260_DPS_SEL_2000         0x00
-#define BMI260_DPS_SEL_1000         0x01
-#define BMI260_DPS_SEL_500          0x02
-#define BMI260_DPS_SEL_250          0x03
-#define BMI260_DPS_SEL_125          0x04
-
-#define BMI260_AUX_CONF         0x44
-
-#define BMI260_FIFO_DOWNS       0x45
-
-#define BMI260_FIFO_WTM_0       0x46
-#define BMI260_FIFO_WTM_1       0x47
-
-#define BMI260_FIFO_CONFIG_0    0x48
-#define BMI260_FIFO_STOP_ON_FULL    BIT(0)
-#define BMI260_FIFO_TIME_EN     BIT(1)
-
-#define BMI260_FIFO_CONFIG_1    0x49
-#define BMI260_FIFO_TAG_INT1_EN_OFFSET  0
-#define BMI260_FIFO_TAG_INT1_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT2_EN_OFFSET  2
-#define BMI260_FIFO_TAG_INT2_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT_EDGE        0x0
-#define BMI260_FIFO_TAG_INT_LEVEL       0x1
-#define BMI260_FIFO_TAG_ACC_SAT         0x2
-#define BMI260_FIFO_TAG_GYR_SAT         0x3
-#define BMI260_FIFO_HEADER_EN           BIT(4)
-#define BMI260_FIFO_AUX_EN              BIT(5)
-#define BMI260_FIFO_ACC_EN              BIT(6)
-#define BMI260_FIFO_GYR_EN              BIT(7)
-#define BMI260_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \
-	   BMI260_FIFO_AUX_EN))
-
-#define BMI260_SATURATION       0x4a
-
-#define BMI260_AUX_DEV_ID       0x4b
-#define BMI260_AUX_I2C_ADDRESS          BMI260_AUX_DEV_ID
-
-#define BMI260_AUX_IF_CONF      0x4c
-#define BMI260_AUX_I2C_CONTROL          BMI260_AUX_IF_CONF
-#define BMI260_AUX_READ_BURST_MASK      3
-#define BMI260_AUX_MAN_READ_BURST_OFF   2
-#define BMI260_AUX_MAN_READ_BURST_MASK  (0x3 << BMI280_AUX_MAN_READ_BURST_OFF)
-#define BMI260_AUX_READ_BURST_1         0
-#define BMI260_AUX_READ_BURST_2         1
-#define BMI260_AUX_READ_BURST_6         2
-#define BMI260_AUX_READ_BURST_8         3
-#define BMI260_AUX_FCU_WRITE_EN         BIT(6)
-#define BMI260_AUX_MANUAL_EN            BIT(7)
-
-#define BMI260_AUX_RD_ADDR      0x4d
-#define BMI260_AUX_I2C_READ_ADDR    BMI260_AUX_RD_ADDR
-#define BMI260_AUX_WR_ADDR      0x4e
-#define BMI260_AUX_I2C_WRITE_ADDR   BMI260_AUX_WR_ADDR
-#define BMI260_AUX_WR_DATA      0x4f
-#define BMI260_AUX_I2C_WRITE_DATA   BMI260_AUX_WR_DATA
-#define BMI260_AUX_I2C_READ_DATA    BMI260_AUX_X_L_G
-
-#define BMI260_ERR_REG_MSK      0x52
-#define BMI260_FATAL_ERR            BIT(0)
-#define BMI260_INTERNAL_ERR_OFF     1
-#define BMI260_INTERNAL_ERR_MASK    (0xf << BMI260_INTERNAL_ERR_OFF)
-#define BMI260_FIFO_ERR             BIT(6)
-#define BMI260_AUX_ERR              BIT(7)
-
-#define BMI260_INT1_IO_CTRL     0x53
-#define BMI260_INT1_LVL             BIT(1)
-#define BMI260_INT1_OD              BIT(2)
-#define BMI260_INT1_OUTPUT_EN       BIT(3)
-#define BMI260_INT1_INPUT_EN        BIT(4)
-
-#define BMI260_INT2_IO_CTRL     0x54
-#define BMI260_INT2_LVL             BIT(1)
-#define BMI260_INT2_OD              BIT(2)
-#define BMI260_INT2_OUTPUT_EN       BIT(3)
-#define BMI260_INT2_INPUT_EN        BIT(4)
-
-#define BMI260_INT_LATCH        0x55
-#define BMI260_INT_LATCH_EN         BIT(0)
-
-#define BMI260_INT1_MAP_FEAT    0x56
-#define BMI260_INT2_MAP_FEAT    0x57
-#define BMI260_MAP_SIG_MOTION_OUT   BIT(0)
-#define BMI260_MAP_STEP_COUNTER_OUT BIT(1)
-#define BMI260_MAP_HIGH_LOW_G_OUT   BIT(2)
-#define BMI260_MAP_TAP_OUT          BIT(3)
-#define BMI260_MAP_FLAT_OUT         BIT(4)
-#define BMI260_MAP_NO_MOTION_OUT    BIT(5)
-#define BMI260_MAP_ANY_MOTION_OUT   BIT(6)
-#define BMI260_MAP_ORIENTAION_OUT   BIT(7)
-
-#define BMI260_INT_MAP_DATA     0x58
-#define BMI260_MAP_FFULL_INT        BIT(0)
-#define BMI260_MAP_FWM_INT          BIT(1)
-#define BMI260_MAP_DRDY_INT         BIT(2)
-#define BMI260_MAP_ERR_INT          BIT(3)
-#define BMI260_INT_MAP_DATA_INT1_OFFSET     0
-#define BMI260_INT_MAP_DATA_INT2_OFFSET     4
-#define BMI260_INT_MAP_DATA_REG(_i, _bit) \
-	(CONCAT3(BMI260_MAP_, _bit, _INT) << \
-	CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET))
-
-#define BMI260_INIT_CTRL        0x59
-#define BMI260_INIT_ADDR_0      0x5b
-#define BMI260_INIT_ADDR_1      0x5c
-#define BMI260_INIT_DATA        0x5e
-#define BMI260_INTERNAL_ERROR   0x5f
-#define BMI260_INT_ERR_1            BIT(1)
-#define BMI260_INT_ERR_2            BIT(2)
-#define BMI260_FEAT_ENG_DISABLED    BIT(4)
-
-#define BMI260_AUX_IF_TRIM      0x68
-#define BMI260_GYR_CRT_CONF     0x69
-
-#define BMI260_NVM_CONF         0x6a
-#define BMI260_NVM_PROG_EN          BIT(1)
-
-#define BMI260_IF_CONF          0x6b
-#define BMI260_IF_SPI3              BIT(0)
-#define BMI260_IF_SPI3_OIS          BIT(1)
-#define BMI260_IF_OIS_EN            BIT(4)
-#define BMI260_IF_AUX_EN            BIT(5)
-
-#define BMI260_DRV              0x6c
-#define BMI260_ACC_SELF_TEST    0x6d
-
-#define BMI260_GYR_SELF_TEST_AXES 0x6e
-
-#define BMI260_NV_CONF          0x70
-#define BMI260_ACC_OFFSET_EN        BIT(3)
-
-#define BMI260_OFFSET_ACC70     0x71
-#define BMI260_OFFSET_GYR70     0x74
-#define BMI260_OFFSET_EN_GYR98  0x77
-#define BMI260_OFFSET_GYRO_EN       BIT(6)
-#define BMI260_GYR_GAIN_EN          BIT(7)
-
-#define BMI260_PWR_CONF         0x7c
-#define BMI260_ADV_POWER_SAVE       BIT(0)
-#define BMI260_FIFO_SELF_WAKE_UP    BIT(1)
-#define BMI260_FUP_EN               BIT(2)
-
-#define BMI260_PWR_CTRL         0x7d
-#define BMI260_AUX_EN               BIT(0)
-#define BMI260_GYR_EN               BIT(1)
-#define BMI260_ACC_EN               BIT(2)
-#define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type)
-#define BMI260_TEMP_EN              BIT(3)
-
-#define BMI260_CMD_REG          0x7e
-#define BMI260_CMD_FIFO_FLUSH       0xb0
-#define BMI260_CMD_SOFT_RESET       0xb6
-
-#define BMI260_FF_FRAME_LEN_TS          4
-#define BMI260_FF_DATA_LEN_ACC          6
-#define BMI260_FF_DATA_LEN_GYR          6
-#define BMI260_FF_DATA_LEN_MAG          8
-
-/* Root mean square noise of 100Hz accelerometer, units: ug */
-#define BMI260_ACCEL_RMS_NOISE_100HZ    1060
-
-#endif /* __CROS_EC_ACCELGYRO_BMI260_H */
diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h
deleted file mode 100644
index 9b93ef65ae..0000000000
--- a/include/driver/accelgyro_bmi260_public.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* BMI260 accelerometer and gyro for Chrome EC */
-
-#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H
-#define __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H
-
-/*
- * The addr field of motion_sensor support both SPI and I2C:
- * This is defined in include/i2c.h and is no longer an 8bit
- * address. The 7/10 bit address starts at bit 0 and leaves
- * room for a 10 bit address, although we don't currently
- * have any 10 bit peripherals. I2C or SPI is indicated by a
- * more significant bit
- */
-
-/* I2C addresses */
-#define BMI260_ADDR0_FLAGS	0x68
-
-extern const struct accelgyro_drv bmi260_drv;
-
-void bmi260_interrupt(enum gpio_signal signal);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-extern struct i2c_stress_test_dev bmi260_i2c_stress_test_dev;
-#endif
-
-#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI260_PUBLIC_H */
diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h
deleted file mode 100644
index 6e1ed122b3..0000000000
--- a/include/driver/accelgyro_bmi_common.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* BMI accelerometer and gyro common definitions for Chrome EC */
-
-#ifndef __CROS_EC_ACCELGYRO_BMI_COMMON_H
-#define __CROS_EC_ACCELGYRO_BMI_COMMON_H
-
-#include "accelgyro.h"
-#include "accelgyro_bmi160.h"
-#include "accelgyro_bmi260.h"
-#include "mag_bmm150.h"
-#include "accelgyro_bmi_common_public.h"
-
-#if !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \
-	!defined(CONFIG_ACCELGYRO_BMI_COMM_I2C)
-#error "BMI must use either SPI or I2C communication"
-#endif
-
-#define BMI_CONF_REG(_sensor)      (0x40 + 2 * (_sensor))
-#define BMI_RANGE_REG(_sensor)     (0x41 + 2 * (_sensor))
-
-#define BMI_ODR_MASK         0x0F
-/* odr = 100 / (1 << (8 - reg)) , within limit */
-#define BMI_ODR_0_78HZ       0x01
-#define BMI_ODR_100HZ        0x08
-
-#define BMI_REG_TO_ODR(_regval) \
-	((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \
-					100000 * (1 << ((_regval) - 8)))
-#define BMI_ODR_TO_REG(_odr) \
-	((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \
-			   (39 - __builtin_clz((_odr) / 100000)))
-
-enum fifo_header {
-	BMI_FH_EMPTY = 0x80,
-	BMI_FH_SKIP = 0x40,
-	BMI_FH_TIME = 0x44,
-	BMI_FH_CONFIG = 0x48
-};
-
-#define BMI_FH_MODE_MASK     0xc0
-#define BMI_FH_PARM_OFFSET       2
-#define BMI_FH_PARM_MASK         (0x7 << BMI_FH_PARM_OFFSET)
-#define BMI_FH_EXT_MASK      0x03
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMI_RESOLUTION      16
-/* Min and Max sampling frequency in mHz */
-#define BMI_ACCEL_MIN_FREQ 12500
-#define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-#define BMI_GYRO_MIN_FREQ  25000
-#define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
-
-enum bmi_running_mode {
-	STANDARD_UI_9DOF_FIFO          = 0,
-	STANDARD_UI_IMU_FIFO           = 1,
-	STANDARD_UI_IMU                = 2,
-	STANDARD_UI_ADVANCEPOWERSAVE   = 3,
-	ACCEL_PEDOMETER                = 4,
-	APPLICATION_HEAD_TRACKING      = 5,
-	APPLICATION_NAVIGATION         = 6,
-	APPLICATION_REMOTE_CONTROL     = 7,
-	APPLICATION_INDOOR_NAVIGATION  = 8,
-};
-
-#define BMI_FLAG_SEC_I2C_ENABLED    BIT(0)
-#define BMI_FIFO_FLAG_OFFSET        4
-#define BMI_FIFO_ALL_MASK           7
-
-#define BMI_GET_DATA(_s) \
-	((struct bmi_drv_data_t *)(_s)->drv_data)
-#define BMI_GET_SAVED_DATA(_s) \
-	(&BMI_GET_DATA(_s)->saved_data[(_s)->type])
-
-#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \
-	(v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G))
-#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \
-	(v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G))
-#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \
-	(v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G))
-
-#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \
-	(v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0))
-#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \
-	(v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1))
-#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \
-	(v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor)))
-
-#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \
-	(v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0))
-#define BMI_INVALID_TEMP     0x8000
-
-#define BMI_STATUS(v) (BMI160_STATUS + \
-	(v) * (BMI260_STATUS - BMI160_STATUS))
-#define BMI_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
-
-#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \
-	(v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70))
-#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \
-	(v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70))
-/*
- * There is some bits in this register that differ between BMI160 and BMI260
- * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0).
- */
-#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \
-	(v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98))
-#define BMI_OFFSET_GYR98_MASK     (BIT(6) - 1)
-#define BMI_OFFSET_ACC_MULTI_MG   (3900 * 1024)
-#define BMI_OFFSET_ACC_DIV_MG     1000000
-#define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024)
-#define BMI_OFFSET_GYRO_DIV_MDS   1000
-
-#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \
-	(v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0))
-#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \
-	(v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK))
-#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \
-	(v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA))
-
-#define BMI_CMD_REG(v) (BMI160_CMD_REG + \
-	(v) * (BMI260_CMD_REG - BMI160_CMD_REG))
-#define BMI_CMD_FIFO_FLUSH 0xb0
-
-#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \
-	(v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ))
-#define BMI_ACCEL_100HZ 100
-
-/*
- * Struct for pairing an engineering value with the register value for a
- * parameter.
- */
-struct bmi_accel_param_pair {
-	int val; /* Value in engineering units. */
-	int reg_val; /* Corresponding register value. */
-};
-
-int bmi_get_xyz_reg(const struct motion_sensor_t *s);
-
-/**
- * @param type   Accel/Gyro
- * @param psize  Size of the table
- *
- * @return       Range table of the type.
- */
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize);
-
-/**
- * @return reg value that matches the given engineering value passed in.
- * The round_up flag is used to specify whether to round up or down.
- * Note, this function always returns a valid reg value. If the request is
- * outside the range of values, it returns the closest valid reg value.
- */
-int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size);
-
-/**
- * @return engineering value that matches the given reg val
- */
-int bmi_get_engineering_val(const int reg_val,
-			    const struct bmi_accel_param_pair *pairs,
-			    const int size);
-
-/**
- * Read 8bit register from accelerometer.
- */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr);
-
-/**
- * Write 8bit register from accelerometer.
- */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data);
-
-/**
- * Read 16bit register from accelerometer.
- */
-int bmi_read16(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr);
-
-/**
- * Write 16bit register from accelerometer.
- */
-int bmi_write16(const int port, const uint16_t i2c_spi_addr_flags,
-		const int reg, int data);
-
-/**
- * Read 32bit register from accelerometer.
- */
-int bmi_read32(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, int *data_ptr);
-
-/**
- * Read n bytes from accelerometer.
- */
-int bmi_read_n(const int port, const uint16_t i2c_spi_addr_flags,
-	       const uint8_t reg, uint8_t *data_ptr, const int len);
-
-/**
- * Write n bytes from accelerometer.
- */
-int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
-		const uint8_t reg, const uint8_t *data_ptr, const int len);
-
-/*
- * Enable/Disable specific bit set of a 8-bit reg.
- */
-int bmi_enable_reg8(const struct motion_sensor_t *s,
-		    int reg, uint8_t bits, int enable);
-
-/*
- * Set specific bit set to certain value of a 8-bit reg.
- */
-int bmi_set_reg8(const struct motion_sensor_t *s, int reg,
-		 uint8_t bits, int mask);
-
-/*
- * @s: base sensor.
- * @v: output vector.
- * @input: 6-bits array input.
- */
-void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input);
-
-/*
- * Decode the header from the fifo.
- * Return 0 if we need further processing.
- * Sensor mutex must be held during processing, to protect the fifos.
- *
- * @accel: base sensor
- * @hdr: the header to decode
- * @last_ts: the last timestamp of fifo interrupt.
- * @bp: current pointer in the buffer, updated when processing the header.
- * @ep: pointer to the end of the valid data in the buffer.
- */
-int bmi_decode_header(struct motion_sensor_t *accel,
-		      enum fifo_header hdr, uint32_t last_ts,
-		      uint8_t **bp, uint8_t *ep);
-/**
- * Retrieve hardware FIFO from sensor,
- * - put data in Sensor Hub fifo.
- * - update sensor raw_xyz vector with the last information.
- * We put raw data in hub fifo and process data from there.
- * @s: Pointer to sensor data.
- * @last_ts: The last timestamp of fifo interrupt.
- *
- * Read only up to  bmi_buffer. If more reads are needed, we will be called
- * again by the interrupt routine.
- *
- * NOTE: If a new driver supports this function, be sure to add a check
- * for spoof_mode in order to load the sensor stack with the spoofed
- * data.  See accelgyro_bmi260.c::load_fifo for an example.
- */
-int bmi_load_fifo(struct motion_sensor_t *s, uint32_t last_ts);
-
-int bmi_set_range(struct motion_sensor_t *s, int range, int rnd);
-
-int bmi_get_data_rate(const struct motion_sensor_t *s);
-
-
-int bmi_get_offset(const struct motion_sensor_t *s,
-		   int16_t *offset, int16_t *temp);
-
-int bmi_get_resolution(const struct motion_sensor_t *s);
-
-#ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s);
-#endif
-
-int bmi_set_scale(const struct motion_sensor_t *s,
-		  const uint16_t *scale, int16_t temp);
-
-int bmi_get_scale(const struct motion_sensor_t *s,
-		  uint16_t *scale, int16_t *temp);
-
-/* Start/Stop the FIFO collecting events */
-int bmi_enable_fifo(const struct motion_sensor_t *s, int enable);
-
-/* Read the xyz data of accel/gyro */
-int bmi_read(const struct motion_sensor_t *s, intv3_t v);
-
-/* Read temperature of sensor s */
-int bmi_read_temp(const struct motion_sensor_t *s, int *temp_ptr);
-
-/* Read temperature of sensor idx */
-int bmi_get_sensor_temp(int idx, int *temp_ptr);
-
-/*
- * Get the normalized rate according to input rate and input rnd
- * @rate: input rate
- * @rnd: round up
- * @normalized_rate_ptr: normalized rate pointer for output
- * @reg_val_ptr: pointer to the actual register value of normalized rate for
- *               output.
- */
-int bmi_get_normalized_rate(const struct motion_sensor_t *s, int rate, int rnd,
-			    int *normalized_rate_ptr, uint8_t *reg_val_ptr);
-
-/* Get the accelerometer offset */
-int bmi_accel_get_offset(const struct motion_sensor_t *accel, intv3_t v);
-
-/* Get the gyroscope offset */
-int bmi_gyro_get_offset(const struct motion_sensor_t *gyro, intv3_t v);
-
-/* Set the accelerometer offset */
-int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v);
-
-/* Set the gyroscope offset */
-int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr);
-
-int bmi_list_activities(const struct motion_sensor_t *s,
-			uint32_t *enabled,
-			uint32_t *disabled);
-#endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */
diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h
deleted file mode 100644
index 52814c71bf..0000000000
--- a/include/driver/accelgyro_bmi_common_public.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* BMI accelerometer and gyro common definitions for Chrome EC */
-
-#ifndef __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H
-#define __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H
-
-/* Min and Max sampling frequency in mHz */
-#define BMI_ACCEL_MIN_FREQ 12500
-#define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-#define BMI_GYRO_MIN_FREQ  25000
-#define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
-
-struct bmi_drv_data_t {
-	struct accelgyro_saved_data_t saved_data[3];
-	uint8_t              flags;
-	uint8_t              enabled_activities;
-	uint8_t              disabled_activities;
-#ifdef CONFIG_MAG_BMI_BMM150
-	struct bmm150_private_data compass;
-#endif
-#ifdef CONFIG_BMI_ORIENTATION_SENSOR
-	uint8_t raw_orientation;
-	enum motionsensor_orientation orientation;
-	enum motionsensor_orientation last_orientation;
-#endif
-
-};
-
-#endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */
diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h
deleted file mode 100644
index 0078b90442..0000000000
--- a/include/driver/als_tcs3400.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMS TCS3400 light sensor driver
- */
-
-#ifndef __CROS_EC_ALS_TCS3400_H
-#define __CROS_EC_ALS_TCS3400_H
-
-#include "driver/als_tcs3400_public.h"
-
-/* ID for TCS34001 and TCS34005 */
-#define TCS340015_DEVICE_ID	0x90
-
-/* ID for TCS34003 and TCS34007 */
-#define TCS340037_DEVICE_ID	0x93
-
-/* Register Map */
-#define TCS_I2C_ENABLE    0x80    /* R/W Enables states and interrupts */
-#define TCS_I2C_ATIME     0x81    /* R/W RGBC integration time */
-#define TCS_I2C_WTIME     0x83    /* R/W Wait time */
-#define TCS_I2C_AILTL     0x84    /* R/W Clear irq low threshold low byte */
-#define TCS_I2C_AILTH     0x85    /* R/W Clear irq low threshold high byte */
-#define TCS_I2C_AIHTL     0x86    /* R/W Clear irq high threshold low byte */
-#define TCS_I2C_AIHTH     0x87    /* R/W Clear irq high threshold high byte */
-#define TCS_I2C_PERS      0x8C    /* R/W Interrupt persistence filter */
-#define TCS_I2C_CONFIG    0x8D    /* R/W Configuration */
-#define TCS_I2C_CONTROL   0x8F    /* R/W Gain control register */
-#define TCS_I2C_AUX       0x90    /* R/W Auxiliary control register */
-#define TCS_I2C_REVID     0x91    /* R Revision ID */
-#define TCS_I2C_ID        0x92    /* R Device ID */
-#define TCS_I2C_STATUS    0x93    /* R Device status */
-#define TCS_I2C_CDATAL    0x94    /* R Clear / IR channel low data register */
-#define TCS_I2C_CDATAH    0x95    /* R Clear / IR channel high data register */
-#define TCS_I2C_RDATAL    0x96    /* R Red ADC low data register */
-#define TCS_I2C_RDATAH    0x97    /* R Red ADC high data register */
-#define TCS_I2C_GDATAL    0x98    /* R Green ADC low data register */
-#define TCS_I2C_GDATAH    0x99    /* R Green ADC high data register */
-#define TCS_I2C_BDATAL    0x9A    /* R Blue ADC low data register */
-#define TCS_I2C_BDATAH    0x9B    /* R Blue ADC high data register */
-#define TCS_I2C_IR        0xC0    /* R/W Access IR Channel */
-#define TCS_I2C_IFORCE    0xE4    /* W Force Interrupt */
-#define TCS_I2C_CICLEAR   0xE6    /* W Clear channel interrupt clear */
-#define TCS_I2C_AICLEAR   0xE7    /* W Clear all interrupts */
-
-#define TCS_I2C_ENABLE_POWER_ON             BIT(0)
-#define TCS_I2C_ENABLE_ADC_ENABLE           BIT(1)
-#define TCS_I2C_ENABLE_WAIT_ENABLE          BIT(3)
-#define TCS_I2C_ENABLE_INT_ENABLE           BIT(4)
-#define TCS_I2C_ENABLE_SLEEP_AFTER_INT      BIT(6)
-#define TCS_I2C_ENABLE_MASK                 (TCS_I2C_ENABLE_POWER_ON |    \
-					     TCS_I2C_ENABLE_ADC_ENABLE |  \
-					     TCS_I2C_ENABLE_WAIT_ENABLE | \
-					     TCS_I2C_ENABLE_INT_ENABLE |  \
-					     TCS_I2C_ENABLE_SLEEP_AFTER_INT)
-
-enum tcs3400_mode {
-	TCS3400_MODE_SUSPEND = 0,
-	TCS3400_MODE_IDLE =       (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE),
-	TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE |
-				   TCS_I2C_ENABLE_INT_ENABLE),
-};
-
-#define TCS_I2C_CONTROL_MASK                0x03
-#define TCS_I2C_STATUS_RGBC_VALID           BIT(0)
-#define TCS_I2C_STATUS_ALS_IRQ              BIT(4)
-#define TCS_I2C_STATUS_ALS_SATURATED        BIT(7)
-
-#define TCS_I2C_AUX_ASL_INT_ENABLE          BIT(5)
-
-/* Light data resides at 0x94 thru 0x98 */
-#define TCS_DATA_START_LOCATION             TCS_I2C_CDATAL
-#define TCS_CLEAR_DATA_SIZE                 2
-#define TCS_RGBC_DATA_SIZE                  8
-
-#define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data)
-#define TCS3400_RGB_DRV_DATA(_s) \
-	((struct tcs3400_rgb_drv_data_t *)(_s)->drv_data)
-
-/*
- * Factor to multiply light value by to determine if an increase in gain
- * would cause the next value to saturate.
- *
- * On the TCS3400, gain increases 4x each time again register setting is
- * incremented.  However, I see cases where values that are 24% of saturation
- * go into saturation after increasing gain, causing a back-and-forth cycle to
- * occur :
- *
- * [134.654994 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
- * [135.655064 tcs3400_adjust_sensor_for_saturation value=15750 24% Gain=1 ]
- * [136.655107 tcs3400_adjust_sensor_for_saturation value=65535 100% Gain=2 ]
- *
- * To avoid this, we require value to be <= 20% of saturation level
- * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased.
- */
-#define TCS_GAIN_ADJUST_FACTOR   5
-#define TCS_GAIN_SAT_LEVEL       (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR)
-#define TCS_UPSHIFT_FACTOR_N     25 /* upshift factor = 2.5 */
-#define TCS_UPSHIFT_FACTOR_D     10
-#define TCS_GAIN_UPSHIFT_LEVEL   (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \
-							/ TCS_UPSHIFT_FACTOR_N)
-
-/*
- * Percentage of saturation level that the auto-adjusting anti-saturation
- * method will drive towards.
- */
-#define TSC_SATURATION_LOW_BAND_PERCENT 90
-#define TSC_SATURATION_LOW_BAND_LEVEL   (TCS_SATURATION_LEVEL * \
-					 TSC_SATURATION_LOW_BAND_PERCENT / 100)
-
-enum crbg_index {
-	CLEAR_CRGB_IDX = 0,
-	RED_CRGB_IDX,
-	GREEN_CRGB_IDX,
-	BLUE_CRGB_IDX,
-	CRGB_COUNT,
-};
-
-#endif /* __CROS_EC_ALS_TCS3400_H */
diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h
deleted file mode 100644
index 812aeda8d3..0000000000
--- a/include/driver/als_tcs3400_public.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AMS TCS3400 light sensor driver
- */
-
-#ifndef __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H
-#define __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H
-
-#include "accelgyro.h"
-
-/* I2C Interface */
-#define TCS3400_I2C_ADDR_FLAGS	0x39
-
-/* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */
-#define TCS_MIN_ATIME           0x00            /* 712 ms */
-#define TCS_MAX_ATIME           0x70            /* 400 ms */
-#define TCS_ATIME_GRANULARITY   256             /* 256 atime settings */
-#define TCS_SATURATION_LEVEL    0xffff          /* for 0 < atime < 0x70 */
-#define TCS_DEFAULT_ATIME       TCS_MIN_ATIME   /* 712 ms */
-#define TCS_CALIBRATION_ATIME   TCS_MIN_ATIME
-#define TCS_GAIN_UPSHIFT_ATIME  TCS_MAX_ATIME
-
-/* Number of different ranges supported for atime adjustment support */
-#define TCS_MAX_ATIME_RANGES    13
-#define TCS_GAIN_TABLE_MAX_LUX  12999
-#define TCS_ATIME_GAIN_FACTOR   100     /* table values are 100x actual value */
-
-#define TCS_MIN_AGAIN           0x00            /* 1x gain */
-#define TCS_MAX_AGAIN           0x03            /* 64x gain */
-#define TCS_CALIBRATION_AGAIN   0x02            /* 16x gain */
-#define TCS_DEFAULT_AGAIN       TCS_CALIBRATION_AGAIN
-
-#define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */
-#define TCS_ATIME_DEC_STEP      5
-#define TCS_ATIME_INC_STEP      TCS_GAIN_UPSHIFT_ATIME
-
-/* Min and Max sampling frequency in mHz */
-#define TCS3400_LIGHT_MIN_FREQ              149
-#define TCS3400_LIGHT_MAX_FREQ              1000
-#if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ)
-#error "EC too slow for light sensor"
-#endif
-
-/* saturation auto-adjustment */
-struct tcs_saturation_t {
-	/*
-	 * Gain Scaling; must be value between 0 and 3
-	 *      0 - 1x scaling
-	 *      1 - 4x scaling
-	 *      2 - 16x scaling
-	 *      3 - 64x scaling
-	 */
-	uint8_t again;
-
-	/* Acquisition Time, controlled by the ATIME register */
-	uint8_t atime;             /* ATIME register setting */
-};
-
-/* tcs3400 rgb als driver data */
-struct tcs3400_rgb_drv_data_t {
-	uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */
-
-	struct rgb_calibration_t calibration;
-	struct tcs_saturation_t saturation;  /* saturation adjustment */
-};
-
-extern const struct accelgyro_drv tcs3400_drv;
-extern const struct accelgyro_drv tcs3400_rgb_drv;
-
-void tcs3400_interrupt(enum gpio_signal signal);
-int tcs3400_get_integration_time(int atime);
-
-#endif /* __CROS_EC_DRIVER_ALS_TCS3400_PUBLIC_H */
diff --git a/include/driver/amd_stt.h b/include/driver/amd_stt.h
deleted file mode 100644
index 3d382a6c0a..0000000000
--- a/include/driver/amd_stt.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AMD STT (Skin Temperature Tracking) Manager */
-
-#ifndef __CROS_EC_AMD_STT_H
-#define __CROS_EC_AMD_STT_H
-
-#define AMD_STT_WRITE_SENSOR_VALUE_CMD 0x3A
-
-enum amd_stt_pcb_sensor {
-	AMD_STT_PCB_SENSOR_APU = 0x0,
-	AMD_STT_PCB_SENSOR_REMOTE = 0x1,
-	AMD_STT_PCB_SENSOR_GPU = 0x2
-};
-
-/**
- * Boards must implement these callbacks for SOC and Ambient temperature.
- * Temperature must be returned in Milli Kelvin.
- * TODO(b/192391025): Replace with direct calls to temp_sensor_read_mk
- */
-int board_get_soc_temp_mk(int *temp_mk);
-int board_get_ambient_temp_mk(int *temp_mk);
-
-#endif /* __CROS_EC_AMD_STT_H */
diff --git a/include/driver/bc12/mt6360_public.h b/include/driver/bc12/mt6360_public.h
deleted file mode 100644
index d2b8499e1f..0000000000
--- a/include/driver/bc12/mt6360_public.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H
-#define __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H
-
-#include <inttypes.h>
-
-#define MT6360_PMU_I2C_ADDR_FLAGS 0x34
-#define MT6360_PMIC_I2C_ADDR_FLAGS 0x1a
-#define MT6360_LDO_I2C_ADDR_FLAGS 0x64
-#define MT6360_PD_I2C_ADDR_FLAGS 0x4e
-
-enum mt6360_regulator_id {
-	MT6360_LDO3,
-	MT6360_LDO5,
-	MT6360_LDO6,
-	MT6360_LDO7,
-	MT6360_BUCK1,
-	MT6360_BUCK2,
-
-	MT6360_REGULATOR_COUNT,
-};
-
-int mt6360_regulator_get_info(enum mt6360_regulator_id id, char *name,
-			      uint16_t *voltage_count, uint16_t *voltages_mv);
-
-int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable);
-
-int mt6360_regulator_is_enabled(enum mt6360_regulator_id id, uint8_t *enabled);
-
-int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
-				 int max_mv);
-
-int mt6360_regulator_get_voltage(enum mt6360_regulator_id id, int *voltage_mv);
-
-enum mt6360_led_id {
-	MT6360_LED_RGB1,
-	MT6360_LED_RGB2,
-	MT6360_LED_RGB3,
-	MT6360_LED_RGB_ML,
-
-	MT6360_LED_COUNT,
-};
-
-#define MT6360_LED_BRIGHTNESS_MAX 15
-
-int mt6360_led_enable(enum mt6360_led_id led_id, int enable);
-
-int mt6360_led_set_brightness(enum mt6360_led_id led_id, int brightness);
-
-extern const struct mt6360_config_t mt6360_config;
-
-struct mt6360_config_t {
-	int i2c_port;
-	int i2c_addr_flags;
-};
-extern const struct bc12_drv mt6360_drv;
-
-#endif /* __CROS_EC_DRIVER_BC12_MT6360_PUBLIC_H */
diff --git a/include/driver/bc12/pi3usb9201_public.h b/include/driver/bc12/pi3usb9201_public.h
deleted file mode 100644
index 643952ab4a..0000000000
--- a/include/driver/bc12/pi3usb9201_public.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PI3USB9201 USB BC 1.2 Charger Detector public definitions */
-
-#ifndef __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H
-#define __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H
-
-/* I2C address */
-#define PI3USB9201_I2C_ADDR_0_FLAGS 0x5C
-#define PI3USB9201_I2C_ADDR_1_FLAGS 0x5D
-#define PI3USB9201_I2C_ADDR_2_FLAGS 0x5E
-#define PI3USB9201_I2C_ADDR_3_FLAGS 0x5F
-
-struct pi3usb9201_config_t {
-	const int i2c_port;
-	const int i2c_addr_flags;
-	const int flags;
-};
-
-/* Configuration struct defined at board level */
-extern const struct pi3usb9201_config_t pi3usb9201_bc12_chips[];
-
-extern const struct bc12_drv pi3usb9201_drv;
-
-#endif /* __CROS_EC_DRIVER_BC12_PI3USB9201_PUBLIC_H */
diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h
deleted file mode 100644
index 2ee5f62cdb..0000000000
--- a/include/driver/charger/isl923x_public.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Renesas (Intersil) ISL-9237/38 battery charger public header
- */
-
-#ifndef __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H
-#define __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H
-
-#include "common.h"
-#include "stdbool.h"
-
-#define ISL923X_ADDR_FLAGS	(0x09)
-
-extern const struct charger_drv isl923x_drv;
-
-/**
- * Initialize AC & DC prochot threshold
- *
- * @param	chgnum: Index into charger chips
- * @param	AC Prochot threshold current in mA:
- *			multiple of 128 up to 6400 mA
- *			DC Prochot threshold current in mA:
- *			multiple of 128 up to 12800 mA
- *		Bits below 128mA are truncated (ignored).
- * @return enum ec_error_list
- */
-int isl923x_set_ac_prochot(int chgnum, uint16_t ma);
-int isl923x_set_dc_prochot(int chgnum, uint16_t ma);
-
-/**
- * Set the general comparator output polarity when asserted.
- *
- * @param chgnum: Index into charger chips
- * @param invert: Non-zero to invert polarity, zero to non-invert.
- * @return EC_SUCCESS, error otherwise.
- */
-int isl923x_set_comparator_inversion(int chgnum, int invert);
-
-/**
- * Return whether ACOK is high or low.
- *
- * @param chgnum index into chg_chips table.
- * @param acok will be set to true if ACOK is asserted, otherwise false.
- * @return EC_SUCCESS, error otherwise.
- */
-enum ec_error_list raa489000_is_acok(int chgnum, bool *acok);
-
-/**
- * Prepare the charger IC for battery ship mode.  Battery ship mode sets the
- * lowest power state for the IC. Battery ship mode can only be entered from
- * battery only mode.
- *
- * @param chgnum index into chg_chips table.
- */
-void raa489000_hibernate(int chgnum, bool disable_adc);
-
-/**
- * Enable or Disable the ASGATE in the READY state.
- *
- * @param chgnum: Index into charger chips
- * @param enable: whether to enable ASGATE
- */
-int raa489000_enable_asgate(int chgnum, bool enable);
-
-enum ec_error_list isl9238c_hibernate(int chgnum);
-enum ec_error_list isl9238c_resume(int chgnum);
-
-#endif /* __CROS_EC_DRIVER_CHARGER_ISL923X_PUBLIC_H */
diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h
deleted file mode 100644
index 342f627bd3..0000000000
--- a/include/driver/charger/isl9241_public.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Renesas (Intersil) ISL-9241 battery charger public header
- */
-
-#ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
-#define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
-
-#define ISL9241_ADDR_FLAGS	0x09
-
-/* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */
-#define ISL9241_BC12_MIN_VOLTAGE	4096
-
-extern const struct charger_drv isl9241_drv;
-
-/**
- * Set AC prochot threshold
- *
- * @param chgnum: Index into charger chips
- * @param ma: AC prochot threshold current in mA, multiple of 128mA
- * @return EC_SUCCESS or error
- */
-int isl9241_set_ac_prochot(int chgnum, int ma);
-
-/**
- * Set DC prochot threshold
- *
- * @param chgnum: Index into charger chips
- * @param ma: DC prochot threshold current in mA, multiple of 256mA
- * @return EC_SUCCESS or error
- */
-int isl9241_set_dc_prochot(int chgnum, int ma);
-
-#define ISL9241_AC_PROCHOT_CURRENT_MIN  128     /* mA */
-#define ISL9241_AC_PROCHOT_CURRENT_MAX  6400    /* mA */
-#define ISL9241_DC_PROCHOT_CURRENT_MIN  256     /* mA */
-#define ISL9241_DC_PROCHOT_CURRENT_MAX  12800   /* mA */
-
-#endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */
diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h
deleted file mode 100644
index 0ae7af4c4c..0000000000
--- a/include/driver/ln9310.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * LION Semiconductor LN-9310 switched capacitor converter.
- */
-
-#ifndef __CROS_EC_LN9310_H
-#define __CROS_EC_LN9310_H
-
-#include "gpio.h"
-
-/* I2C address */
-#define LN9310_I2C_ADDR_0_FLAGS		0x72
-#define LN9310_I2C_ADDR_1_FLAGS		0x73
-#define LN9310_I2C_ADDR_2_FLAGS		0x53
-#define LN9310_I2C_ADDR_3_FLAGS		0x54
-
-/* Registers */
-#define LN9310_REG_CHIP_ID		0x00
-#define LN9310_CHIP_ID			0x44
-#define LN9310_REG_INT1			0x01
-#define LN9310_REG_INT1_MSK		0x02
-#define LN9310_INT1_TIMER		BIT(0)
-#define LN9310_INT1_INFET		BIT(1)
-#define LN9310_INT1_TEMP		BIT(2)
-#define LN9310_INT1_REV_CURR		BIT(3)
-#define LN9310_INT1_MODE		BIT(4)
-#define LN9310_INT1_ALARM		BIT(5)
-#define LN9310_INT1_OK			BIT(6)
-#define LN9310_INT1_FAULT		BIT(7)
-
-#define LN9310_REG_SYSGPIO_MSK		0x03
-
-#define LN9310_REG_SYS_STS		0x04
-#define LN9310_SYS_STANDBY		BIT(0)
-#define LN9310_SYS_SWITCHING21_ACTIVE	BIT(1)
-#define LN9310_SYS_SWITCHING31_ACTIVE	BIT(2)
-#define LN9310_SYS_BYPASS_ACTIVE	BIT(3)
-#define LN9310_SYS_INFET_OK		BIT(4)
-#define LN9310_SYS_SC_OUT_SWITCH_OK	BIT(5)
-#define LN9310_SYS_INFET_OUT_SWITCH_OK	BIT(6)
-
-#define LN9310_REG_SAFETY_STS		0x05
-#define LN9310_REG_FAULT1_STS		0x06
-#define LN9310_REG_FAULT2_STS		0x07
-
-#define LN9310_REG_PWR_CTRL		0x1d
-#define LN9310_PWR_OP_MODE0		BIT(0)
-#define LN9310_PWR_OP_MODE1		BIT(1)
-#define LN9310_PWR_INFET_EN		BIT(2)
-#define LN9310_PWR_INFET_AUTO_MODE	BIT(3)
-#define LN9310_PWR_REVERSE_MODE		BIT(4)
-#define LN9310_PWR_VIN_OV_IGNORE	BIT(5)
-#define LN9310_PWR_OP_MANUAL_UPDATE	BIT(6)
-#define LN9310_PWR_FORCE_INSNS_EN	BIT(7)
-#define LN9310_PWR_OP_MODE_MASK		0x03
-#define LN9310_PWR_OP_MODE_DISABLED	0x00
-#define LN9310_PWR_OP_MODE_BYPASS	0x01
-#define LN9310_PWR_OP_MODE_SWITCH21	0x02
-#define LN9310_PWR_OP_MODE_SWITCH31	0x03
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK	0x40
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF	0x00
-#define LN9310_PWR_INFET_AUTO_MODE_MASK		0x08
-#define LN9310_PWR_INFET_AUTO_MODE_ON		0x08
-#define LN9310_PWR_INFET_AUTO_MODE_OFF		0x00
-
-#define LN9310_REG_SYS_CTRL		0x1e
-
-#define LN9310_REG_STARTUP_CTRL			0x1f
-#define LN9310_STARTUP_STANDBY_EN				BIT(0)
-#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR	BIT(3)
-
-#define LN9310_REG_IIN_CTRL		0x20
-#define LN9310_REG_VIN_CTRL		0x21
-
-#define LN9310_REG_TRACK_CTRL		0x22
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN			BIT(7)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2		BIT(6)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1		BIT(5)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0		BIT(4)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK	0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON		0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF		0x00
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK	0x70
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V	0x10
-
-#define LN9310_REG_OCP_CTRL		0x23
-
-#define LN9310_REG_TIMER_CTRL		0x24
-#define LN9310_TIMER_OP_SELF_SYNC_EN		BIT(3)
-#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK	0x08
-#define LN9310_TIMER_OP_SELF_SYNC_EN_ON		0x08
-
-#define LN9310_REG_RECOVERY_CTRL	0x25
-
-#define LN9310_REG_LB_CTRL		0x26
-#define LN9310_LB_MIN_FREQ_EN	BIT(2)
-#define LN9310_LB_DELTA_MASK	0x38
-#define LN9310_LB_DELTA_2S		0x20
-#define LN9310_LB_DELTA_3S		0x20
-
-#define LN9310_REG_SC_OUT_OV_CTRL	0x29
-#define LN9310_REG_STS_CTRL		0x2d
-
-#define LN9310_REG_MODE_CHANGE_CFG	0x2e
-#define LN9310_MODE_TM_VIN_OV_CFG0		BIT(0)
-#define LN9310_MODE_TM_VIN_OV_CFG1		BIT(1)
-#define LN9310_MODE_TM_VIN_OV_CFG2		BIT(2)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0	BIT(3)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1	BIT(4)
-#define LN9310_MODE_TM_TRACK_CFG0		BIT(5)
-#define LN9310_MODE_TM_TRACK_CFG1		BIT(6)
-#define LN9310_MODE_FORCE_MODE_CFG		BIT(7)
-#define LN9310_MODE_TM_TRACK_MASK		0x60
-#define LN9310_MODE_TM_TRACK_BYPASS		0x00
-#define LN9310_MODE_TM_TRACK_SWITCH21		0x20
-#define LN9310_MODE_TM_TRACK_SWITCH31		0x60
-#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK	0x18
-#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS	0x0
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21	0x08
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31	0x18
-#define LN9310_MODE_TM_VIN_OV_CFG_MASK		0x07
-#define LN9310_MODE_TM_VIN_OV_CFG_2S		0x0  /* 14V */
-#define LN9310_MODE_TM_VIN_OV_CFG_3S		0x2  /* 20V */
-
-#define LN9310_REG_SPARE_0	0x2A
-#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK	0x40
-#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON	0x40
-#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK	0x10
-#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON	0x10
-
-#define LN9310_REG_SC_DITHER_CTRL	0x2f
-
-#define LN9310_REG_LION_CTRL				0x30
-#define LN9310_LION_CTRL_MASK				0xFF
-#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM	0xAA
-#define LN9310_LION_CTRL_UNLOCK				0x5B
-/*
- * value changed to 0x22 to distinguish from reset value of 0x00
- * 0x22 and 0x00 are functionally equivalent within LN9310
- */
-#define LN9310_LION_CTRL_LOCK				0x22
-
-#define LN9310_REG_CFG_0	0x3C
-#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK	0x20
-#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON		0x20
-
-#define LN9310_REG_CFG_4	0x40
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG		BIT(2)
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK				BIT(3)
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 	0x04
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK			0x08
-#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK		0xC0
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 	0x04
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF			0x00
-#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST		0x00
-
-#define LN9310_REG_CFG_5	0x41
-#define LN9310_CFG_5_INGATE_PD_EN_MASK		0xC0
-#define LN9310_CFG_5_INGATE_PD_EN_OFF		0x00
-#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK		0x30
-#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST	0x00
-
-#define LN9310_REG_TEST_MODE_CTRL	0x46
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK		0x40
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON			0x40
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF		0x00
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK	0x20
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON		0x20
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF		0x00
-
-#define LN9310_REG_FORCE_SC21_CTRL_1	0x49
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK	0xFF
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON	0x59
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF	0x40
-
-#define LN9310_REG_FORCE_SC21_CTRL_2	0x4A
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK		0x80
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON		0x80
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF		0x00
-
-#define LN9310_REG_SWAP_CTRL_0	0x58
-#define LN9310_REG_SWAP_CTRL_1	0x59
-#define LN9310_REG_SWAP_CTRL_2	0x5A
-#define LN9310_REG_SWAP_CTRL_3	0x5B
-
-#define LN9310_REG_BC_STS_B		0x51
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK		BIT(5)
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK	0x20
-
-#define LN9310_REG_BC_STS_C				0x52
-#define LN9310_BC_STS_C_CHIP_REV_MASK	0xF0
-#define LN9310_BC_STS_C_CHIP_REV_FIXED	0x40
-
-/* LN9310 Timing definition */
-#define LN9310_CDC_DELAY 				120	/* 120us */
-#define LN9310_CFLY_PRECHARGE_DELAY 	(12*MSEC)
-#define LN9310_CFLY_PRECHARGE_TIMEOUT	(100*MSEC)
-
-/* LN9310 Driver Configuration */
-#define LN9310_INIT_RETRY_COUNT 3
-
-/* Define configuration of LN9310 part */
-struct ln9310_config_t {
-	const int i2c_port;
-	const int i2c_addr_flags;
-};
-
-/* Configuration struct defined at board level */
-extern const struct ln9310_config_t ln9310_config;
-
-/**
- * @brief Init the driver
- *
- * @return EC_SUCCESS when initialization was complete.
- */
-int ln9310_init(void);
-
-/* Enable/disable the ln9310 output */
-void ln9310_software_enable(int enable);
-
-/* Interrupt handler */
-void ln9310_interrupt(enum gpio_signal signal);
-
-/* Return the POWER_GOOD status */
-int ln9310_power_good(void);
-
-/* Battery cell type */
-enum battery_cell_type {
-	BATTERY_CELL_TYPE_UNKNOWN = 0,
-	BATTERY_CELL_TYPE_2S = 2,
-	BATTERY_CELL_TYPE_3S = 3
-};
-
-enum battery_cell_type board_get_battery_cell_type(void);
-
-#endif /* __CROS_EC_LN9310_H */
diff --git a/include/driver/ppc/sn5s330_public.h b/include/driver/ppc/sn5s330_public.h
deleted file mode 100644
index fdd60e54cb..0000000000
--- a/include/driver/ppc/sn5s330_public.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TI SN5S330 USB-C Power Path Controller */
-
-#ifndef __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H
-#define __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H
-
-#define SN5S330_ADDR0_FLAGS 0x40
-#define SN5S330_ADDR1_FLAGS 0x41
-#define SN5S330_ADDR2_FLAGS 0x42
-#define SN5S330_ADDR3_FLAGS 0x43
-
-extern const struct ppc_drv sn5s330_drv;
-
-/**
- * Interrupt Handler for the SN5S330.
- *
- * By default, the only interrupt sources that are unmasked are overcurrent
- * conditions for PP1, and VBUS_GOOD if PPC is being used to detect VBUS
- * (CONFIG_USB_PD_VBUS_DETECT_PPC).
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void sn5s330_interrupt(int port);
-
-#endif /* __CROS_EC_DRIVER_PPC_SN5S330_PUBLIC_H */
diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h
deleted file mode 100644
index f366da59b3..0000000000
--- a/include/driver/ppc/syv682x_public.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Silergy SYV682x Type-C Power Path Controller */
-
-#ifndef __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H
-#define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H
-
-/* I2C addresses */
-#define SYV682X_ADDR0_FLAGS		0x40
-#define SYV682X_ADDR1_FLAGS		0x41
-#define SYV682X_ADDR2_FLAGS		0x42
-#define SYV682x_ADDR3_FLAGS		0x43
-
-extern const struct ppc_drv syv682x_drv;
-
-void syv682x_interrupt(int port);
-
-#endif /* __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H */
diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h
deleted file mode 100644
index 35b2352704..0000000000
--- a/include/driver/retimer/bb_retimer.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Driver header for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
- */
-
-#ifndef __CROS_EC_BB_RETIMER_H
-#define __CROS_EC_BB_RETIMER_H
-
-#include "gpio.h"
-#include "usb_mux.h"
-#include "driver/retimer/bb_retimer_public.h"
-
-/* Burnside Bridge I2C Configuration Space */
-#define BB_RETIMER_REG_VENDOR_ID	0
-#define BB_RETIMER_VENDOR_ID_1          0x8086
-#define BB_RETIMER_VENDOR_ID_2          0x8087
-
-#define BB_RETIMER_REG_DEVICE_ID	1
-#define BB_RETIMER_DEVICE_ID		0x15EE
-
-/* Connection State Register Attributes */
-#define BB_RETIMER_REG_CONNECTION_STATE		4
-#define BB_RETIMER_DATA_CONNECTION_PRESENT	BIT(0)
-#define BB_RETIMER_CONNECTION_ORIENTATION	BIT(1)
-#define BB_RETIMER_RE_TIMER_DRIVER		BIT(2)
-#define BB_RETIMER_USB_2_CONNECTION		BIT(4)
-#define BB_RETIMER_USB_3_CONNECTION		BIT(5)
-#define BB_RETIMER_USB_3_SPEED			BIT(6)
-#define BB_RETIMER_USB_DATA_ROLE		BIT(7)
-#define BB_RETIMER_DP_CONNECTION		BIT(8)
-#define BB_RETIMER_DP_PIN_ASSIGNMENT		BIT(10)
-#define BB_RETIMER_IRQ_HPD			BIT(14)
-#define BB_RETIMER_HPD_LVL			BIT(15)
-#define BB_RETIMER_TBT_CONNECTION		BIT(16)
-#define BB_RETIMER_TBT_TYPE			BIT(17)
-#define BB_RETIMER_TBT_CABLE_TYPE		BIT(18)
-#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE	BIT(19)
-#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING	BIT(20)
-#define BB_RETIMER_ACTIVE_PASSIVE		BIT(22)
-#define BB_RETIMER_USB4_ENABLED			BIT(23)
-#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x)	(((x) & 0x7) << 25)
-#define BB_RETIMER_TBT_CABLE_GENERATION(x)		(((x) & 0x3) << 28)
-
-#define BB_RETIMER_REG_TBT_CONTROL		5
-#define BB_RETIMER_REG_EXT_CONNECTION_MODE	6
-
-#define BB_RETIMER_REG_COUNT			7
-
-#endif /* __CROS_EC_BB_RETIMER_H */
diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h
deleted file mode 100644
index f1a924f67e..0000000000
--- a/include/driver/retimer/bb_retimer_public.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Public header for Intel Burnside Bridge - Thunderbolt/USB/DisplayPort Retimer
- */
-
-#ifndef __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H
-#define __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H
-
-#include "usb_mux.h"
-
-struct usb_mux;
-
-/* Supported USB retimer drivers */
-extern const struct usb_mux_driver bb_usb_retimer;
-
-/* Retimer driver hardware specific controls */
-struct bb_usb_control {
-	/* Load switch enable */
-	enum gpio_signal usb_ls_en_gpio;
-	/* Retimer reset */
-	enum gpio_signal retimer_rst_gpio;
-};
-
-#ifndef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-extern const struct bb_usb_control bb_controls[];
-#else
-extern struct bb_usb_control bb_controls[];
-#endif
-
-/**
- * Enable/disable the power state of BB retimer
- *
- * Define override function at board level if the platform specific changes
- * are needed to enable/disable the power state of BB retimer.
- *
- * @param me     Pointer to USB mux
- * @param enable BB retimer power state to be changed
- *
- * @return EC_SUCCESS, or non-zero on error.
- */
-__override_proto int bb_retimer_power_enable(const struct usb_mux *me,
-					     bool enable);
-
-/**
- * Set HPD on the BB retimer
- *
- * Set the HPD related fields in the BB retimer
- *
- * @param me		Pointer to USB mux
- * @param mux_state	USB mux state containing HPD level and IRQ
- */
-void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state);
-
-#endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */
diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h
deleted file mode 100644
index 6ad11a9555..0000000000
--- a/include/driver/tcpm/it8xxx2_pd_public.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H
-#define __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H
-
-extern const struct tcpm_drv it83xx_tcpm_drv;
-extern const struct tcpm_drv it8xxx2_tcpm_drv;
-
-#endif /* __CROS_EC_DRIVER_TCPM_IT8XXX2_PD_PUBLIC_H */
diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h
deleted file mode 100644
index 0e200cb395..0000000000
--- a/include/driver/tcpm/ps8xxx_public.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Parade Tech Type-C port controller */
-
-#ifndef __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H
-#define __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H
-
-#include "usb_mux.h"
-
-struct usb_mux;
-
-/* I2C interface */
-#define PS8751_I2C_ADDR1_P1_FLAGS 0x09
-#define PS8751_I2C_ADDR1_P2_FLAGS 0x0A
-#define PS8751_I2C_ADDR1_FLAGS    0x0B	/* P3 */
-#define PS8751_I2C_ADDR2_FLAGS    0x1B
-#define PS8751_I2C_ADDR3_FLAGS    0x2B
-#define PS8751_I2C_ADDR4_FLAGS    0x4B
-
-#define PS8XXX_VENDOR_ID  0x1DA0
-
-/* Minimum Delay for reset assertion */
-#define PS8XXX_RESET_DELAY_MS 1
-
-/* Delay between releasing reset and the first I2C read */
-#define PS8805_FW_INIT_DELAY_MS 10
-
-/* Delay from power on to reset de-asserted */
-#define PS8815_PWR_H_RST_H_DELAY_MS 20
-
-/*
- * Add delay of writing TCPC_REG_POWER_CTRL makes
- * CC status being judged correctly when disable VCONN.
- * This may be a PS8XXX firmware issue, Parade is still trying.
- * https://partnerissuetracker.corp.google.com/issues/185202064
- */
-#define PS8XXX_VCONN_TURN_OFF_DELAY_US 10
-
-/*
- * Delay between releasing reset and the first I2C read
- *
- * If the delay is too short, I2C fails.
- * If the delay is marginal I2C reads return garbage.
- *
- * With firmware 0x03:
- *   10ms is too short
- *   20ms is marginal
- *   25ms is OK
- */
-#define PS8815_FW_INIT_DELAY_MS 50
-
-/* NOTE: The Product ID will read as 0x8803 if the firmware has malfunctioned in
- * 8705, 8755 and 8805.
- */
-#define PS8705_PRODUCT_ID 0x8705
-#define PS8751_PRODUCT_ID 0x8751
-#define PS8755_PRODUCT_ID 0x8755
-#define PS8805_PRODUCT_ID 0x8805
-#define PS8815_PRODUCT_ID 0x8815
-
-extern const struct tcpm_drv ps8xxx_tcpm_drv;
-
-/**
- * Board-specific callback to judge and provide which chip source of PS8XXX
- * series supported by this driver per specific port.
- *
- * If the board supports only one single source then there is no nencessary to
- * provide the __override version.
- *
- * If board supports two sources or above (with CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
- * then the __override version is mandatory.
- *
- * @param port	TCPC port number.
- */
-__override_proto
-uint16_t board_get_ps8xxx_product_id(int port);
-
-void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   mux_state_t mux_state);
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev;
-#endif /* defined(CONFIG_CMD_I2C_STRESS_TEST_TCPC) */
-
-/*
- * This driver was designed to use Low Power Mode on PS8751 TCPC/MUX chip
- * when running as MUX only (CC lines are not connected, eg. Ampton).
- * To achieve this RP on CC lines is set when device should enter LPM and
- * RD when mux should work.
- */
-extern const struct usb_mux_driver ps8xxx_usb_mux_driver;
-
-#endif /* __CROS_EC_DRIVER_TCPM_PS8XXX_PUBLIC_H */
diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h
deleted file mode 100644
index 14fa9495e8..0000000000
--- a/include/driver/tcpm/rt1715_public.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Richtek RT1715 Type-C port controller */
-
-#ifndef __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H
-#define __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H
-
-/* I2C interface */
-#define RT1715_I2C_ADDR_FLAGS 0x4E
-
-#define RT1715_VENDOR_ID 0x29CF
-
-extern const struct tcpm_drv rt1715_tcpm_drv;
-
-#endif /* __CROS_EC_DRIVER_TCPM_RT1715_PUBLIC_H */
diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h
deleted file mode 100644
index 53a6a4e65e..0000000000
--- a/include/driver/tcpm/tcpci.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management */
-
-#ifndef __CROS_EC_USB_PD_TCPM_TCPCI_H
-#define __CROS_EC_USB_PD_TCPM_TCPCI_H
-
-#include "config.h"
-#include "ec_commands.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-
-#define TCPC_REG_VENDOR_ID         0x0
-#define TCPC_REG_PRODUCT_ID        0x2
-#define TCPC_REG_BCD_DEV           0x4
-#define TCPC_REG_TC_REV            0x6
-#define TCPC_REG_PD_REV            0x8
-#define TCPC_REG_PD_INT_REV        0xa
-
-#define TCPC_REG_ALERT             0x10
-#define TCPC_REG_ALERT_NONE         0x0000
-#define TCPC_REG_ALERT_MASK_ALL     0xffff
-#define TCPC_REG_ALERT_VENDOR_DEF   BIT(15)
-#define TCPC_REG_ALERT_ALERT_EXT    BIT(14)
-#define TCPC_REG_ALERT_EXT_STATUS   BIT(13)
-#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
-#define TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)
-#define TCPC_REG_ALERT_FAULT        BIT(9)
-#define TCPC_REG_ALERT_V_ALARM_LO   BIT(8)
-#define TCPC_REG_ALERT_V_ALARM_HI   BIT(7)
-#define TCPC_REG_ALERT_TX_SUCCESS   BIT(6)
-#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
-#define TCPC_REG_ALERT_TX_FAILED    BIT(4)
-#define TCPC_REG_ALERT_RX_HARD_RST  BIT(3)
-#define TCPC_REG_ALERT_RX_STATUS    BIT(2)
-#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
-#define TCPC_REG_ALERT_CC_STATUS    BIT(0)
-#define TCPC_REG_ALERT_TX_COMPLETE  (TCPC_REG_ALERT_TX_SUCCESS | \
-				      TCPC_REG_ALERT_TX_DISCARDED | \
-				      TCPC_REG_ALERT_TX_FAILED)
-
-#define TCPC_REG_ALERT_MASK        0x12
-#define TCPC_REG_ALERT_MASK_VENDOR_DEF   BIT(15)
-
-#define TCPC_REG_POWER_STATUS_MASK 0x14
-#define TCPC_REG_FAULT_STATUS_MASK 0x15
-#define TCPC_REG_EXT_STATUS_MASK   0x16
-#define TCPC_REG_ALERT_EXTENDED_MASK 0x17
-
-#define TCPC_REG_CONFIG_STD_OUTPUT 0x18
-#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N    BIT(6)
-#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N      BIT(5)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK          (3 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE          (0 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           BIT(2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP            (2 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
-
-#define TCPC_REG_TCPC_CTRL         0x19
-#define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
-#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1)
-/*
- * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when
- * a connection is found.
- */
-#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT  BIT(6)
-#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL         BIT(4)
-#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE            BIT(1)
-
-#define TCPC_REG_ROLE_CTRL         0x1a
-#define TCPC_REG_ROLE_CTRL_DRP_MASK                    BIT(6)
-#define TCPC_REG_ROLE_CTRL_RP_MASK                     (BIT(5)|BIT(4))
-#define TCPC_REG_ROLE_CTRL_CC2_MASK                    (BIT(3)|BIT(2))
-#define TCPC_REG_ROLE_CTRL_CC1_MASK                    (BIT(1)|BIT(0))
-#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
-		((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
-		(((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \
-		(((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \
-		((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))
-#define TCPC_REG_ROLE_CTRL_DRP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
-#define TCPC_REG_ROLE_CTRL_RP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
-#define TCPC_REG_ROLE_CTRL_CC2(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
-#define TCPC_REG_ROLE_CTRL_CC1(reg) \
-		((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
-
-#define TCPC_REG_FAULT_CTRL        0x1b
-#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS         BIT(1)
-#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS         BIT(0)
-
-#define TCPC_REG_POWER_CTRL        0x1c
-#define TCPC_REG_POWER_CTRL_FRS_ENABLE                 BIT(7)
-#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS       BIT(6)
-#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS             BIT(5)
-#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT  BIT(4)
-#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE            BIT(2)
-#define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
-#define TCPC_REG_POWER_CTRL_VCONN(reg)    ((reg) & 0x1)
-
-#define TCPC_REG_CC_STATUS         0x1d
-#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK        BIT(5)
-#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK         BIT(4)
-#define TCPC_REG_CC_STATUS_CC2_STATE_MASK              (BIT(3)|BIT(2))
-#define TCPC_REG_CC_STATUS_CC1_STATE_MASK              (BIT(1)|BIT(0))
-#define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \
-		((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3))
-#define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \
-		((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
-#define TCPC_REG_CC_STATUS_TERM(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
-#define TCPC_REG_CC_STATUS_CC2(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
-#define TCPC_REG_CC_STATUS_CC1(reg) \
-		((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
-
-#define TCPC_REG_POWER_STATUS      0x1e
-#define TCPC_REG_POWER_STATUS_MASK_ALL  0xff
-#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
-#define TCPC_REG_POWER_STATUS_UNINIT    BIT(6)
-#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
-#define TCPC_REG_POWER_STATUS_VBUS_DET  BIT(3)
-#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
-#define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
-
-#define TCPC_REG_FAULT_STATUS      0x1f
-#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET            BIT(7)
-#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS            BIT(6)
-#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL       BIT(5)
-#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL      BIT(4)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT         BIT(3)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE         BIT(2)
-#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT        BIT(1)
-#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR         BIT(0)
-
-#define TCPC_REG_EXT_STATUS        0x20
-#define TCPC_REG_EXT_STATUS_SAFE0V   BIT(0)
-
-#define TCPC_REG_ALERT_EXT         0x21
-#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED        BIT(2)
-#define TCPC_REG_ALERT_EXT_SRC_FRS              BIT(1)
-#define TCPC_REG_ALERT_EXT_SNK_FRS              BIT(0)
-
-#define TCPC_REG_COMMAND           0x23
-#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT      0x33
-#define TCPC_REG_COMMAND_SNK_CTRL_LOW            0x44
-#define TCPC_REG_COMMAND_SNK_CTRL_HIGH           0x55
-#define TCPC_REG_COMMAND_SRC_CTRL_LOW            0x66
-#define TCPC_REG_COMMAND_SRC_CTRL_HIGH           0x77
-#define TCPC_REG_COMMAND_LOOK4CONNECTION         0x99
-#define TCPC_REG_COMMAND_I2CIDLE                 0xFF
-
-#define TCPC_REG_DEV_CAP_1         0x24
-#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET	BIT(15)
-#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING		BIT(14)
-#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING		BIT(13)
-#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE		BIT(12)
-#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE		BIT(11)
-#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE	BIT(10)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK		(BIT(8)|BIT(9))
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF		(0 << 8)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF	(1 << 8)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF	(2 << 8)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK			(BIT(5)|BIT(6)|BIT(7))
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK		(0 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC			(1 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK			(2 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC		(3 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP			(4 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL	(5 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP		(6 << 5)
-#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED	BIT(4)
-#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN			BIT(3)
-#define TCPC_REG_DEV_CAP_1_SINK_VBUS			BIT(2)
-#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS	BIT(1)
-#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS			BIT(0)
-
-#define TCPC_REG_DEV_CAP_2         0x26
-#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP           BIT(9)
-
-#define TCPC_REG_STD_INPUT_CAP     0x28
-#define TCPC_REG_STD_OUTPUT_CAP    0x29
-
-#define TCPC_REG_CONFIG_EXT_1      0x2A
-#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR	BIT(1)
-
-#define TCPC_REG_MSG_HDR_INFO      0x2e
-#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
-		((drole) << 3 | (PD_REV20 << 1) | (prole))
-#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
-#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
-
-#define TCPC_REG_RX_DETECT         0x2f
-#define TCPC_REG_RX_DETECT_SOP_HRST_MASK 0x21
-#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK 0x27
-
-/* TCPCI Rev 1.0 receive registers */
-#define TCPC_REG_RX_BYTE_CNT       0x30
-#define TCPC_REG_RX_BUF_FRAME_TYPE 0x31
-#define TCPC_REG_RX_HDR            0x32
-#define TCPC_REG_RX_DATA           0x34 /* through 0x4f */
-
-/*
- * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
- * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
- * only be accessed by reading at a common register address 30h.
- */
-#define TCPC_REG_RX_BUFFER         0x30
-
-#define TCPC_REG_TRANSMIT          0x50
-#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \
-		((retries) << 4 | (type))
-#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
-#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
-#define TCPC_REG_TRANSMIT_TYPE(reg)  ((reg) & 0x7)
-
-/* TCPCI Rev 1.0 transmit registers */
-#define TCPC_REG_TX_BYTE_CNT       0x51
-#define TCPC_REG_TX_HDR            0x52
-#define TCPC_REG_TX_DATA           0x54 /* through 0x6f */
-
-/*
- * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
- * portion of the SOP* USB PD message payload (including the header and/or the
- * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
- * is “hidden� and can only be accessed by writing to register address 51h
- */
-#define TCPC_REG_TX_BUFFER         0x51
-
-#define TCPC_REG_VBUS_VOLTAGE                0x70
-
-#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
-#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */
-
-#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH  0x74
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG   0x76
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG   0x78
-
-extern const struct tcpm_drv tcpci_tcpm_drv;
-extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver;
-
-void tcpci_set_cached_rp(int port, int rp);
-int tcpci_get_cached_rp(int port);
-void tcpci_set_cached_pull(int port, enum tcpc_cc_pull pull);
-enum tcpc_cc_pull tcpci_get_cached_pull(int port);
-
-void tcpci_tcpc_alert(int port);
-int tcpci_tcpm_init(int port);
-int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
-bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level);
-int tcpci_tcpm_select_rp_value(int port, int rp);
-int tcpci_tcpm_set_cc(int port, int pull);
-int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
-int tcpci_tcpm_sop_prime_enable(int port, bool enable);
-int tcpci_tcpm_set_vconn(int port, int enable);
-int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role);
-int tcpci_tcpm_set_rx_enable(int port, int enable);
-int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head);
-int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data);
-int tcpci_tcpm_release(int port);
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull pull);
-int tcpci_tcpc_drp_toggle(int port);
-#endif
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-int tcpci_enter_low_power_mode(int port);
-#endif
-enum ec_error_list tcpci_set_bist_test_mode(const int port,
-		const bool enable);
-#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-void tcpci_tcpc_discharge_vbus(int port, int enable);
-#endif
-void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable);
-int tcpci_tcpc_debug_accessory(int port, bool enable);
-
-int tcpci_tcpm_mux_init(const struct usb_mux *me);
-int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
-		       bool *ack_required);
-int tcpci_tcpm_mux_get(const struct usb_mux *me, mux_state_t *mux_state);
-int tcpci_tcpm_mux_enter_low_power(const struct usb_mux *me);
-int tcpci_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info);
-#ifdef CONFIG_USBC_PPC
-bool tcpci_tcpm_get_snk_ctrl(int port);
-int tcpci_tcpm_set_snk_ctrl(int port, int enable);
-bool tcpci_tcpm_get_src_ctrl(int port);
-int tcpci_tcpm_set_src_ctrl(int port, int enable);
-#endif
-
-int tcpci_tcpc_fast_role_swap_enable(int port, int enable);
-
-#endif /* __CROS_EC_USB_PD_TCPM_TCPCI_H */
diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h
deleted file mode 100644
index fb63e5504f..0000000000
--- a/include/driver/tcpm/tcpm.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port management - common header for TCPM drivers */
-
-#ifndef __CROS_EC_USB_PD_TCPM_TCPM_H
-#define __CROS_EC_USB_PD_TCPM_TCPM_H
-
-#include "common.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "usb_pd_tcpm.h"
-#include "util.h"
-
-#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-	!defined(CONFIG_USB_PD_DUAL_ROLE)
-#error "DRP auto toggle requires board to have DRP support"
-#error "Please upgrade your board configuration"
-#endif
-
-#ifndef CONFIG_USB_PD_TCPC
-
-/* I2C wrapper functions - get I2C port / peripheral addr from config struct. */
-#ifndef CONFIG_USB_PD_TCPC_LOW_POWER
-static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
-{
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
-{
-	return i2c_write16(tcpc_config[port].i2c_info.port,
-			   i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
-{
-	return i2c_read8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
-}
-
-static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
-{
-	return i2c_read16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
-}
-
-/*
- * The *_no_lpm_exit() routines are intende to be used where the TCPC
- * needs to be accessed without being being taken out of LPM. The main
- * use case is to check the alert register to determine if a TCPC is the
- * source of an interrupt in a shared interrupt implementation. If the
- * TCPC is taken out of LPM, it may generate a new alert which can lead
- * to successive unintended interrupts. The TCPC is placed back into the
- * idle state after the LPM timer expires similar to other tcpc_*()
- * routines.
- *
- * The caller must guarantee that the chip responds to I2C as expected:
- *  - some TCPCs wake up when they alert and do not need special handing
- *  - some TCPCs wake up on I2C and respond as expected
- *  - some TCPCs wake up on I2C and throw away the transaction - these
- *    need an explicit by the caller.
- */
-
-static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr,
-					       int reg, int *val)
-{
-	return tcpc_addr_read16(port, i2c_addr, reg, val);
-}
-
-static inline int tcpc_xfer(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size)
-{
-	return i2c_xfer(tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			out, out_size, in, in_size);
-}
-
-static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
-{
-	return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-				 tcpc_config[port].i2c_info.addr_flags,
-				 out, out_size, in, in_size, flags);
-}
-
-static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size)
-{
-	return i2c_read_block(tcpc_config[port].i2c_info.port,
-			      tcpc_config[port].i2c_info.addr_flags,
-			      reg, in, size);
-}
-
-static inline int tcpc_write_block(int port, int reg,
-		const uint8_t *out, int size)
-{
-	return i2c_write_block(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       reg, out, size);
-}
-
-static inline int tcpc_update8(int port, int reg,
-			       uint8_t mask,
-			       enum mask_update_action action)
-{
-	return i2c_update8(tcpc_config[port].i2c_info.port,
-			   tcpc_config[port].i2c_info.addr_flags,
-			   reg, mask, action);
-}
-
-static inline int tcpc_update16(int port, int reg,
-				uint16_t mask,
-				enum mask_update_action action)
-{
-	return i2c_update16(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, mask, action);
-}
-
-#else /* !CONFIG_USB_PD_TCPC_LOW_POWER */
-int tcpc_addr_write(int port, int i2c_addr, int reg, int val);
-int tcpc_addr_write16(int port, int i2c_addr, int reg, int val);
-int tcpc_addr_read(int port, int i2c_addr, int reg, int *val);
-int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val);
-int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val);
-int tcpc_read_block(int port, int reg, uint8_t *in, int size);
-int tcpc_write_block(int port, int reg, const uint8_t *out, int size);
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size);
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags);
-
-int tcpc_update8(int port, int reg,
-		 uint8_t mask, enum mask_update_action action);
-int tcpc_update16(int port, int reg,
-		  uint16_t mask, enum mask_update_action action);
-
-#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
-
-static inline int tcpc_write(int port, int reg, int val)
-{
-	return tcpc_addr_write(port,
-			       tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_write16(int port, int reg, int val)
-{
-	return tcpc_addr_write16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_read(int port, int reg, int *val)
-{
-	return tcpc_addr_read(port,
-			      tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline int tcpc_read16(int port, int reg, int *val)
-{
-	return tcpc_addr_read16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
-}
-
-static inline void tcpc_lock(int port, int lock)
-{
-	i2c_lock(tcpc_config[port].i2c_info.port, lock);
-}
-
-/* TCPM driver wrapper function */
-static inline int tcpm_init(int port)
-{
-	int rv;
-
-	rv = tcpc_config[port].drv->init(port);
-	if (rv)
-		return rv;
-
-	/* Board specific post TCPC init */
-	if (board_tcpc_post_init)
-		rv = board_tcpc_post_init(port);
-
-	return rv;
-}
-
-static inline int tcpm_release(int port)
-{
-	return tcpc_config[port].drv->release(port);
-}
-
-static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
-{
-	return tcpc_config[port].drv->get_cc(port, cc1, cc2);
-}
-
-static inline bool tcpm_check_vbus_level(int port, enum vbus_level level)
-{
-	return tcpc_config[port].drv->check_vbus_level(port, level);
-}
-
-static inline int tcpm_select_rp_value(int port, int rp)
-{
-	return tcpc_config[port].drv->select_rp_value(port, rp);
-}
-
-static inline int tcpm_set_cc(int port, int pull)
-{
-	return tcpc_config[port].drv->set_cc(port, pull);
-}
-
-static inline int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
-{
-	return tcpc_config[port].drv->set_polarity(port, polarity);
-}
-
-static inline int tcpm_sop_prime_enable(int port, bool enable)
-{
-#ifdef CONFIG_USB_PD_DECODE_SOP
-	return tcpc_config[port].drv->sop_prime_enable(port, enable);
-#else
-	return EC_SUCCESS;
-#endif
-}
-
-static inline int tcpm_set_vconn(int port, int enable)
-{
-#ifdef CONFIG_USB_PD_TCPC_VCONN
-	int rv;
-
-	rv = tcpc_config[port].drv->set_vconn(port, enable);
-	if (rv)
-		return rv;
-#endif
-
-	return tcpm_sop_prime_enable(port, enable);
-}
-
-static inline int tcpm_set_msg_header(int port, int power_role, int data_role)
-{
-	return tcpc_config[port].drv->set_msg_header(port, power_role,
-						     data_role);
-}
-
-static inline int tcpm_set_rx_enable(int port, int enable)
-{
-	return tcpc_config[port].drv->set_rx_enable(port, enable);
-}
-
-static inline void tcpm_enable_auto_discharge_disconnect(int port, int enable)
-{
-	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
-
-	if (tcpc->tcpc_enable_auto_discharge_disconnect)
-		tcpc->tcpc_enable_auto_discharge_disconnect(port, enable);
-}
-
-static inline int tcpm_reset_bist_type_2(int port)
-{
-	if (tcpc_config[port].drv->reset_bist_type_2 != NULL)
-		return tcpc_config[port].drv->reset_bist_type_2(port);
-	else
-		return EC_SUCCESS;
-}
-
-/**
- * Reads a message using get_message_raw driver method and puts it into EC's
- * cache.
- */
-int tcpm_enqueue_message(int port);
-
-static inline int tcpm_transmit(int port, enum tcpci_msg_type type,
-				uint16_t header, const uint32_t *data)
-{
-	return tcpc_config[port].drv->transmit(port, type, header, data);
-}
-
-#ifdef CONFIG_USB_PD_PPC
-static inline bool tcpm_get_snk_ctrl(int port)
-{
-	return tcpc_config[port].drv->get_snk_ctrl ?
-		tcpc_config[port].drv->get_snk_ctrl(port) : false;
-}
-static inline int tcpm_set_snk_ctrl(int port, int enable)
-{
-	if (tcpc_config[port].drv->set_snk_ctrl != NULL)
-		return tcpc_config[port].drv->set_snk_ctrl(port, enable);
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-}
-
-static inline bool tcpm_get_src_ctrl(int port)
-{
-
-	return tcpc_config[port].drv->get_src_ctrl ?
-		tcpc_config[port].drv->get_src_ctrl(port) : false;
-}
-static inline int tcpm_set_src_ctrl(int port, int enable)
-{
-	if (tcpc_config[port].drv->set_src_ctrl != NULL)
-		return tcpc_config[port].drv->set_src_ctrl(port, enable);
-	else
-		return EC_ERROR_UNIMPLEMENTED;
-}
-#endif
-
-static inline void tcpc_alert(int port)
-{
-	tcpc_config[port].drv->tcpc_alert(port);
-}
-
-static inline void tcpc_discharge_vbus(int port, int enable)
-{
-	tcpc_config[port].drv->tcpc_discharge_vbus(port, enable);
-}
-
-#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-static inline int tcpm_auto_toggle_supported(int port)
-{
-	return !!tcpc_config[port].drv->drp_toggle;
-}
-
-static inline int tcpm_enable_drp_toggle(int port)
-{
-	return tcpc_config[port].drv->drp_toggle(port);
-}
-#else
-static inline int tcpm_auto_toggle_supported(int port)
-{
-	return false;
-}
-int tcpm_enable_drp_toggle(int port);
-#endif
-
-static inline int tcpm_debug_accessory(int port, bool enable)
-{
-	if (tcpc_config[port].drv->debug_accessory)
-		return tcpc_config[port].drv->debug_accessory(port, enable);
-	return EC_SUCCESS;
-}
-
-static inline int tcpm_debug_detach(int port)
-{
-	if (tcpc_config[port].drv->debug_detach)
-		return tcpc_config[port].drv->debug_detach(port);
-
-	/* No special handling for debug disconnections?  Success! */
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-static inline int tcpm_enter_low_power_mode(int port)
-{
-	return tcpc_config[port].drv->enter_low_power_mode(port);
-}
-#else
-int tcpm_enter_low_power_mode(int port);
-#endif
-
-#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
-static inline int tcpc_i2c_read(const int port, const uint16_t addr_flags,
-				const int reg, int *data)
-{
-	return tcpc_read(port, reg, data);
-}
-
-static inline int tcpc_i2c_write(const int port, const uint16_t addr_flags,
-				 const int reg, int data)
-{
-	return tcpc_write(port, reg, data);
-}
-#endif
-
-static inline int tcpm_get_chip_info(int port, int live,
-				     struct ec_response_pd_chip_info_v1 *info)
-{
-	if (tcpc_config[port].drv->get_chip_info)
-		return tcpc_config[port].drv->get_chip_info(port, live, info);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable)
-{
-	const struct tcpm_drv *tcpc;
-	int rv = EC_SUCCESS;
-
-	tcpc = tcpc_config[port].drv;
-	if (tcpc->set_bist_test_mode)
-		rv = tcpc->set_bist_test_mode(port, enable);
-	return rv;
-}
-
-#ifdef CONFIG_USB_PD_FRS_TCPC
-static inline int tcpm_set_frs_enable(int port, int enable)
-{
-	const struct tcpm_drv *tcpc;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * set_frs_enable will be set to tcpci_tcp_fast_role_swap_enable
-	 * if it is handled by the tcpci for the tcpc chipset
-	 */
-	tcpc = tcpc_config[port].drv;
-	if (tcpc->set_frs_enable)
-		rv = tcpc->set_frs_enable(port, enable);
-	return rv;
-}
-#endif /* defined(CONFIG_USB_PD_FRS_TCPC) */
-
-#else /* CONFIG_USB_PD_TCPC */
-
-/**
- * Initialize TCPM driver and wait for TCPC readiness.
- *
- * @param port Type-C port number
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_init(int port);
-
-/**
- * Read the CC line status.
- *
- * @param port Type-C port number
- * @param cc1 pointer to CC status for CC1
- * @param cc2 pointer to CC status for CC2
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
-
-/**
- * Check VBUS level
- *
- * @param port Type-C port number
- * @param level safe level voltage to check against
- *
- * @return False => VBUS not at level, True => VBUS at level
- */
-bool tcpm_check_vbus_level(int port, enum vbus_level level);
-
-/**
- * Set the value of the CC pull-up used when we are a source.
- *
- * @param port Type-C port number
- * @param rp One of enum tcpc_rp_value
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_select_rp_value(int port, int rp);
-
-/**
- * Set the CC pull resistor. This sets our role as either source or sink.
- *
- * @param port Type-C port number
- * @param pull One of enum tcpc_cc_pull
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_cc(int port, int pull);
-
-/**
- * Set polarity
- *
- * @param port Type-C port number
- * @param polarity port polarity
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
-
-/**
- * Enable SOP' message transmit/receive.
- *
- * @param port Type-C port number
- * @param enable Enable/Disable SOP' and SOP'' messages
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_sop_prime_enable(int port, int enable);
-
-/**
- * Set Vconn.
- *
- * @param port Type-C port number
- * @param enable Enable/Disable Vconn
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_vconn(int port, int enable);
-
-/**
- * Set PD message header to use for goodCRC
- *
- * @param port Type-C port number
- * @param power_role Power role to use in header
- * @param data_role Data role to use in header
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_msg_header(int port, int power_role, int data_role);
-
-/**
- * Set RX enable flag
- *
- * @param port Type-C port number
- * @enable true for enable, false for disable
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_set_rx_enable(int port, int enable);
-
-/**
- * Enable Auto Discharge Disconnect
- *
- * @param port Type-C port number
- * @param enable true for enable, false for disable
- */
-void tcpm_enable_auto_discharge_disconnect(int port, int enable);
-
-/**
- * Transmit PD message
- *
- * @param port Type-C port number
- * @param type Transmit type
- * @param header Packet header
- * @param cnt Number of bytes in payload
- * @param data Payload
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
-		  const uint32_t *data);
-
-/**
- * TCPC is asserting alert
- *
- * @param port Type-C port number
- */
-void tcpc_alert(int port);
-
-#endif /* CONFIG_USB_PD_TCPC */
-
-/**
- * Gets the next waiting RX message.
- *
- * @param port Type-C port number
- * @param payload Pointer to location to copy payload of PD message
- * @param header The header of PD message
- *
- * @return EC_SUCCESS or error
- */
-int tcpm_dequeue_message(int port, uint32_t *payload, int *header);
-
-/**
- * Returns true if the tcpm has RX messages waiting to be consumed.
- */
-int tcpm_has_pending_message(int port);
-
-/**
- * Clear any pending messages in the RX queue.  This function must be
- * called from the same context as the caller of tcpm_dequeue_message to avoid
- * race conditions.
- */
-void tcpm_clear_pending_messages(int port);
-
-/**
- * Enable/Disable TCPC Fast Role Swap detection
- *
- * @param port Type-C port number
- * @param enable FRS enable (true) disable (false)
- * @return EC_SUCCESS on success, or an error
- */
-int tcpm_set_frs_enable(int port, int enable);
-
-#ifdef CONFIG_CMD_TCPC_DUMP
-static inline void tcpm_dump_registers(int port)
-{
-	const struct tcpm_drv *tcpc = tcpc_config[port].drv;
-
-	if (tcpc->dump_registers)
-		tcpc->dump_registers(port);
-	else
-		tcpc_dump_std_registers(port);
-}
-#endif /* defined(CONFIG_CMD_TCPC_DUMP) */
-
-/**
- * Disable BIST type-2 mode
- *
- * @param port Type-C port number
- * @return EC_SUCCESS on success, or an error
- */
-int tcpm_reset_bist_type_2(int port);
-
-#endif
diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h
deleted file mode 100644
index 8756d9b362..0000000000
--- a/include/driver/tcpm/tusb422_public.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TI TUSB422 Type-C port controller */
-
-#ifndef __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H
-#define __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H
-
-/* I2C interface */
-#define TUSB422_I2C_ADDR_FLAGS 0x20
-
-extern const struct tcpm_drv tusb422_tcpm_drv;
-
-#endif /* __CROS_EC_DRIVER_TCPM_TUSB422_PUBLIC_H */
diff --git a/include/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h
deleted file mode 100644
index adcd5c5be4..0000000000
--- a/include/driver/temp_sensor/thermistor.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Thermistor module for Chrome EC */
-
-#ifndef __CROS_EC_TEMP_SENSOR_THERMISTOR_H
-#define __CROS_EC_TEMP_SENSOR_THERMISTOR_H
-
-struct thermistor_data_pair {
-	uint8_t mv;	/* Scaled voltage level at ADC (in mV) */
-	uint8_t temp;	/* Temperature in Celsius */
-};
-
-struct thermistor_info {
-	uint8_t scaling_factor;	/* Scaling factor for voltage in data pair. */
-	uint8_t num_pairs;	/* Number of data pairs. */
-
-	/*
-	 * Values between given data pairs will be calculated as points on
-	 * a line. Pairs can be derived using the Steinhart-Hart equation.
-	 *
-	 * Guidelines for data sets:
-	 * - Must contain at least two pairs.
-	 * - First and last pairs are the max and min.
-	 * - Pairs must be sorted in descending order.
-	 * - 5 pairs should provide reasonable accuracy in most cases. Use
-	 *   points where the slope changes significantly or to recalibrate
-	 *   the algorithm if needed.
-	 */
-	const struct thermistor_data_pair *data;
-};
-
-/**
- * Calculate temperature using linear interpolation of data points.
- *
- * Given a set of datapoints, the algorithm will calculate the "step" in
- * between each one in order to interpolate missing entries.
- *
- * @param mv	Value read from ADC (in millivolts).
- * @param info	Reference data set and info.
- *
- * @return	temperature in C
- */
-int thermistor_linear_interpolate(uint16_t mv,
-				  const struct thermistor_info *info);
-
-#ifdef CONFIG_THERMISTOR_NCP15WB
-/**
- * ncp15wb temperature conversion routine.
- *
- * @param adc	10bit raw data on adc.
- *
- * @return	temperature in C.
- */
-int ncp15wb_calculate_temp(uint16_t adc);
-#endif /* CONFIG_THERMISTOR_NCP15WB */
-
-#ifdef CONFIG_STEINHART_HART_3V3_13K7_47K_4050B
-/**
- * Reads the specified ADC channel and uses a lookup table and interpolation to
- * return a temperature in degrees K.
- *
- * The lookup table is based off of a resistor divider circuit on 3.3V with a
- * 13.7K resistor in series with a thermistor with nominal value of 47K (at 25C)
- * and a B (25/100) value of 4050.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr);
-#endif
-
-#ifdef CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
-/**
- * Reads the specified ADC channel and uses a lookup table and interpolation to
- * return a temperature in degrees K.
- *
- * The lookup table is based off of a resistor divider circuit on 3.3V with a
- * 51.1K resistor in series with a thermistor with nominal value of 47K (at 25C)
- * and a B (25/100) value of 4050.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr);
-#endif
-
-#ifdef CONFIG_STEINHART_HART_6V0_51K1_47K_4050B
-/**
- * Reads the specified ADC channel and uses a lookup table and interpolation to
- * return a temperature in degrees K.
- *
- * The lookup table is based off of a resistor divider circuit on 6.0V with a
- * 51.1K resistor in series with a thermistor with nominal value of 47K (at 25C)
- * and a B (25/100) value of 4050.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr);
-#endif
-
-#ifdef CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-/**
- * Reads the specified ADC channel and uses a lookup table and interpolation to
- * return a temperature in degrees K.
- *
- * The lookup table is based off of a resistor divider circuit on 3V with a
- * 22.6K resistor in series with a thermistor with nominal value of 47K (at 25C)
- * and a B (25/100) value of 4050.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr);
-#endif
-
-#ifdef CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-/**
- * Reads the specified ADC channel and uses a lookup table and interpolation to
- * return a temperature in degrees K.
- *
- * The lookup table is based off of a resistor divider circuit on 3.3V with a
- * 30.9K resistor in series with a thermistor with nominal value of 47K (at 25C)
- * and a B (25/100) value of 4050.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr);
-#endif
-
-/**
- * Reads the sensor's ADC channel and uses a lookup table and interpolation to
- * argument thermistor_info for interpolation to return a temperature in degrees
- * K.
- *
- * @param idx_adc	The idx value from the temp_sensor_t struct, which is
- *			the ADC channel to read and convert to degrees K
- * @param temp_ptr	Destination for temperature (in degrees K)
- * @param info	Structure containing information about the underlying thermistor
- * that is necessary to interpolate temperature
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int thermistor_get_temperature(int idx_adc, int *temp_ptr,
-			       const struct thermistor_info *info);
-
-#endif /* __CROS_EC_TEMP_SENSOR_THERMISTOR_NCP15WB_H */
diff --git a/include/driver/usb_mux/it5205_public.h b/include/driver/usb_mux/it5205_public.h
deleted file mode 100644
index 81dc326049..0000000000
--- a/include/driver/usb_mux/it5205_public.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ITE IT5205 Type-C USB alternate mode mux public header
- */
-
-#ifndef __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H
-#define __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H
-
-/* I2C interface */
-#define IT5205_I2C_ADDR1_FLAGS 0x48
-#define IT5205_I2C_ADDR2_FLAGS 0x58
-
-#endif /* __CROS_EC_DRIVER_USB_MUX_IT5205_PUBLIC_H */
diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h
deleted file mode 100644
index b0a7ae2eda..0000000000
--- a/include/driver/usb_mux/ps8743_public.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Parade PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort.
- */
-
-#ifndef __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H
-#define __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H
-
-#include <inttypes.h>
-
-#define PS8743_I2C_ADDR0_FLAG    0x10
-#define PS8743_I2C_ADDR1_FLAG    0x11
-#define PS8743_I2C_ADDR2_FLAG    0x19
-#define PS8743_I2C_ADDR3_FLAG    0x1a
-
-/* Mode register for setting mux */
-#define PS8743_REG_MODE 0x00
-#define PS8743_MODE_IN_HPD_ASSERT    BIT(0)
-#define PS8743_MODE_IN_HPD_CONTROL   BIT(1)
-#define PS8743_MODE_FLIP_ENABLE      BIT(2)
-#define PS8743_MODE_FLIP_REG_CONTROL BIT(3)
-#define PS8743_MODE_USB_ENABLE       BIT(4)
-#define PS8743_MODE_USB_REG_CONTROL  BIT(5)
-#define PS8743_MODE_DP_ENABLE        BIT(6)
-#define PS8743_MODE_DP_REG_CONTROL   BIT(7)
-/* To reset the state machine to default */
-#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL |  \
-				PS8743_MODE_DP_REG_CONTROL)
-/* DP output setting */
-#define PS8743_REG_DP_SETTING    0x07
-#define PS8743_DP_SWG_ADJ_DFLT   0x00
-#define PS8743_DP_SWG_ADJ_N20P   0x40
-#define PS8743_DP_SWG_ADJ_N15P   0x80
-#define PS8743_DP_SWG_ADJ_P15P   0xc0
-#define PS8743_DP_OUT_SWG_400    0x00
-#define PS8743_DP_OUT_SWG_600    0x10
-#define PS8743_DP_OUT_SWG_800    0x20
-#define PS8743_DP_OUT_SWG_1000   0x30
-#define PS8743_DP_OUT_PRE_EM_0_DB   0x00
-#define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04
-#define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08
-#define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c
-#define PS8743_DP_POST_CUR2_0_DB       0x00
-#define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01
-#define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02
-#define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03
-
-/* USB equalization settings for Host to Mux */
-#define PS8743_REG_USB_EQ_TX     0x32
-#define PS8743_USB_EQ_TX_12_8_DB 0x00
-#define PS8743_USB_EQ_TX_17_DB   0x20
-#define PS8743_USB_EQ_TX_7_7_DB  0x40
-#define PS8743_USB_EQ_TX_3_6_DB  0x60
-#define PS8743_USB_EQ_TX_15_DB   0x80
-#define PS8743_USB_EQ_TX_10_9_DB 0xc0
-#define PS8743_USB_EQ_TX_4_5_DB  0xe0
-
-/* USB swing adjust for Mux to Type-C connector */
-#define PS8743_REG_USB_SWING     0x36
-#define PS8743_OUT_SWG_DEFAULT   0x00
-#define PS8743_OUT_SWG_NEG_20    0x40
-#define PS8743_OUT_SWG_NEG_15    0x80
-#define PS8743_OUT_SWG_POS_15    0xc0
-#define PS8743_LFPS_SWG_DEFAULT  0x00
-#define PS8743_LFPS_SWG_TD       0x08
-
-/* USB equalization settings for Connector to Mux */
-#define PS8743_REG_USB_EQ_RX     0x3b
-#define PS8743_USB_EQ_RX_2_4_DB  0x00
-#define PS8743_USB_EQ_RX_5_DB    0x10
-#define PS8743_USB_EQ_RX_6_5_DB  0x20
-#define PS8743_USB_EQ_RX_7_4_DB  0x30
-#define PS8743_USB_EQ_RX_8_7_DB  0x40
-#define PS8743_USB_EQ_RX_10_9_DB 0x50
-#define PS8743_USB_EQ_RX_12_8_DB 0x60
-#define PS8743_USB_EQ_RX_13_8_DB 0x70
-#define PS8743_USB_EQ_RX_14_8_DB 0x80
-#define PS8743_USB_EQ_RX_15_4_DB 0x90
-#define PS8743_USB_EQ_RX_16_0_DB 0xa0
-#define PS8743_USB_EQ_RX_16_7_DB 0xb0
-#define PS8743_USB_EQ_RX_18_8_DB 0xc0
-#define PS8743_USB_EQ_RX_21_3_DB 0xd0
-#define PS8743_USB_EQ_RX_22_2_DB 0xe0
-
-/* USB High Speed Signal Detector thershold adjustment */
-#define PS8743_REG_HS_DET_THRESHOLD  0x3c
-#define PS8743_USB_HS_THRESH_DEFAULT 0x00
-#define PS8743_USB_HS_THRESH_POS_10  0x20
-#define PS8743_USB_HS_THRESH_POS_33  0x40
-#define PS8743_USB_HS_THRESH_NEG_10  0x60
-#define PS8743_USB_HS_THRESH_NEG_25  0x80
-#define PS8743_USB_HS_THRESH_POS_25  0xa0
-#define PS8743_USB_HS_THRESH_NEG_45  0xc0
-#define PS8743_USB_HS_THRESH_NEG_35  0xe0
-
-int ps8743_tune_usb_eq(const struct usb_mux *me, uint8_t tx, uint8_t rx);
-int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
-int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val);
-int ps8743_check_chip_id(const struct usb_mux *me, int *val);
-
-#endif /* __CROS_EC_DRIVER_USB_MUX_PS8743_PUBLIC_H */
diff --git a/include/ec_ec_comm_server.h b/include/ec_ec_comm_server.h
deleted file mode 100644
index 1ed5588666..0000000000
--- a/include/ec_ec_comm_server.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC-EC communication, functions and definition for server.
- */
-
-#ifndef EC_EC_COMM_SERVER_H_
-#define EC_EC_COMM_SERVER_H_
-
-#include <stdint.h>
-#include "consumer.h"
-#include "queue.h"
-
-extern struct queue const ec_ec_comm_server_input;
-extern struct queue const ec_ec_comm_server_output;
-
-void ec_ec_comm_server_written(struct consumer const *consumer, size_t count);
-
-#endif /* EC_EC_COMM_SERVER_H_ */
diff --git a/include/espi.h b/include/espi.h
deleted file mode 100644
index d1b8af3425..0000000000
--- a/include/espi.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* eSPI module for Chrome EC */
-
-#ifndef __CROS_EC_ESPI_H
-#define __CROS_EC_ESPI_H
-
-#include "gpio_signal.h"
-
-/* Signal through VW */
-enum espi_vw_signal {
-	/* The first valid VW signal is 0x2000 */
-	VW_SIGNAL_START = IOEX_LIMIT + 1,
-	VW_SLP_S3_L = VW_SIGNAL_START,	/* index 02h (In)  */
-	VW_SLP_S4_L,
-	VW_SLP_S5_L,
-	VW_SUS_STAT_L,			/* index 03h (In)  */
-	VW_PLTRST_L,
-	VW_OOB_RST_WARN,
-	VW_OOB_RST_ACK,			/* index 04h (Out) */
-	VW_WAKE_L,
-	VW_PME_L,
-	VW_ERROR_FATAL,			/* index 05h (Out) */
-	VW_ERROR_NON_FATAL,
-	/* Merge bit 3/0 into one signal. Need to set them simultaneously */
-	VW_PERIPHERAL_BTLD_STATUS_DONE,
-	VW_SCI_L,			/* index 06h (Out) */
-	VW_SMI_L,
-	VW_RCIN_L,
-	VW_HOST_RST_ACK,
-	VW_HOST_RST_WARN,		/* index 07h (In)  */
-	VW_SUS_ACK,			/* index 40h (Out) */
-	VW_SUS_WARN_L,			/* index 41h (In)  */
-	VW_SUS_PWRDN_ACK_L,
-	VW_SLP_A_L,
-	VW_SLP_LAN,                     /* index 42h (In)  */
-	VW_SLP_WLAN,
-	VW_SIGNAL_END,
-	VW_LIMIT = 0x2FFF
-};
-BUILD_ASSERT(VW_SIGNAL_END < VW_LIMIT);
-
-#define VW_SIGNAL_COUNT (VW_SIGNAL_END - VW_SIGNAL_START)
-
-/**
- * Set eSPI Virtual-Wire signal to Host
- *
- * @param signal vw signal needs to set
- * @param level  level of vw signal
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level);
-
-/**
- * Get eSPI Virtual-Wire signal from host
- *
- * @param signal vw signal needs to get
- * @return      1: set by host, otherwise: no signal
- */
-int espi_vw_get_wire(enum espi_vw_signal signal);
-
-/**
- * Enable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to enable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_enable_wire_int(enum espi_vw_signal signal);
-
-/**
- * Disable VW interrupt of power sequence signal
- *
- * @param signal vw signal needs to disable interrupt
- * @return EC_SUCCESS, or non-zero if error.
- */
-int espi_vw_disable_wire_int(enum espi_vw_signal signal);
-
-/**
- * Return pointer to constant eSPI virtual wire signal name
- *
- * @param signal virtual wire enum
- * @return pointer to string or NULL if signal out of range
- */
-const char *espi_vw_get_wire_name(enum espi_vw_signal signal);
-
-/**
- * Check if signal is an eSPI virtual wire
- * @param signal is gpio_signal or espi_vw_signal enum casted to int
- * @return 1 if signal is virtual wire else returns 0.
- */
-int espi_signal_is_vw(int signal);
-
-
-#endif  /* __CROS_EC_ESPI_H */
diff --git a/include/event_log.h b/include/event_log.h
deleted file mode 100644
index 45b10a3a2d..0000000000
--- a/include/event_log.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_EVENT_LOG_H
-#define __CROS_EC_EVENT_LOG_H
-
-struct event_log_entry {
-	uint32_t timestamp; /* relative timestamp in milliseconds */
-	uint8_t type;       /* event type, caller-defined */
-	uint8_t size;       /* [7:5] caller-def'd [4:0] payload size in bytes */
-	uint16_t data;      /* type-defined data payload */
-	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
-} __packed;
-
-#define EVENT_LOG_SIZE_MASK  0x1f
-#define EVENT_LOG_SIZE(size) ((size) & EVENT_LOG_SIZE_MASK)
-
-/* The timestamp is the microsecond counter shifted to get about a ms. */
-#define EVENT_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
-/* Returned in the "type" field, when there is no entry available */
-#define EVENT_LOG_NO_ENTRY 0xff
-
-/* Add an entry to the event log. */
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-		   void *payload, uint32_t timestamp);
-
-/*
- * Remove and return an entry from the event log, if available.
- * Returns size of log entry *r.
- */
-int log_dequeue_event(struct event_log_entry *r);
-
-#endif /* __CROS_EC_EVENT_LOG_H */
diff --git a/include/fan.h b/include/fan.h
deleted file mode 100644
index bd92b97254..0000000000
--- a/include/fan.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fan control module for Chrome EC */
-
-#ifndef __CROS_EC_FAN_H
-#define __CROS_EC_FAN_H
-
-#ifdef CONFIG_ZEPHYR
-#ifdef CONFIG_PLATFORM_EC_FAN
-
-#include <devicetree.h>
-#define NODE_ID_AND_COMMA(node_id) node_id,
-enum fan_channel {
-#if DT_NODE_EXISTS(DT_INST(0, named_fans))
-	DT_FOREACH_CHILD(DT_INST(0, named_fans), NODE_ID_AND_COMMA)
-#endif /* named_fans */
-	FAN_CH_COUNT
-};
-
-#define CONFIG_FANS FAN_CH_COUNT
-
-#endif /* CONFIG_PLATFORM_EC_FAN */
-#endif /* CONFIG_ZEPHYR */
-
-struct fan_conf {
-	unsigned int flags;
-	/* Hardware channel number (the meaning is chip-specific) */
-	int ch;
-	/* Active-high power_good input GPIO, or -1 if none */
-	int pgood_gpio;
-	/* Active-high power_enable output GPIO, or -1 if none */
-	int enable_gpio;
-};
-
-struct fan_rpm {
-	/* rpm_min is to keep turning. rpm_start is to begin turning */
-	int rpm_min;
-	int rpm_start;
-	int rpm_max;
-};
-
-/* Characteristic of each physical fan */
-struct fan_t {
-	const struct fan_conf *conf;
-	const struct fan_rpm *rpm;
-};
-
-/* Values for .flags field */
-/*   Enable automatic RPM control using tach input */
-#define FAN_USE_RPM_MODE   BIT(0)
-/*   Require a higher duty cycle to start up than to keep running */
-#define FAN_USE_FAST_START BIT(1)
-
-/* The list of fans is instantiated in board.c. */
-#ifdef CONFIG_FAN_DYNAMIC
-extern struct fan_t fans[];
-#else
-extern const struct fan_t fans[];
-#endif
-
-/* For convenience */
-#define FAN_CH(fan)	fans[fan].conf->ch
-
-/**
- * Set the amount of active cooling needed. The thermal control task will call
- * this frequently, and the fan control logic will attempt to provide it.
- *
- * @param fan   Fan number (index into fans[])
- * @param pct   Percentage of cooling effort needed (0 - 100)
- */
-void fan_set_percent_needed(int fan, int pct);
-
-/**
- * This function translates the percentage of cooling needed into a target RPM.
- * The default implementation should be sufficient for most needs, but
- * individual boards may provide a custom version if needed (see config.h).
- *
- * @param fan   Fan number (index into fans[])
- * @param pct   Percentage of cooling effort needed (always in [0,100])
- * Return       Target RPM for fan
- */
-int fan_percent_to_rpm(int fan, int pct);
-
-
-/**
- * These functions require chip-specific implementations.
- */
-
-/* Enable/Disable the fan controller */
-void fan_set_enabled(int ch, int enabled);
-int fan_get_enabled(int ch);
-
-/* Fixed pwm duty cycle (0-100%) */
-void fan_set_duty(int ch, int percent);
-int fan_get_duty(int ch);
-
-/* Enable/Disable automatic RPM control using tach feedback */
-void fan_set_rpm_mode(int ch, int rpm_mode);
-int fan_get_rpm_mode(int ch);
-
-/* Set the target for the automatic RPM control */
-void fan_set_rpm_target(int ch, int rpm);
-int fan_get_rpm_actual(int ch);
-int fan_get_rpm_target(int ch);
-
-/* Is the fan stalled when it shouldn't be? */
-int fan_is_stalled(int ch);
-
-/**
- * STOPPED means not spinning.
- *
- * When setting fan rpm, some implementations in chip layer (npcx and it83xx)
- * is to adjust fan pwm duty steps by steps. In this period, fan_status will
- * be marked as CHANGING. After change is done, fan_status will become LOCKED.
- *
- * In the period of changing pwm duty, if it's trying to increase/decrease duty
- * even when duty is already in upper/lower bound. Then this action won't work,
- * and fan_status will be marked as FRUSTRATED.
- *
- * For other implementations in chip layer (mchp and mec1322), there is no
- * changing period. So they don't have CHANGING status.
- * Just return status as LOCKED in normal spinning case, return STOPPED when
- * not spinning, return FRUSTRATED when the related flags (which is read from
- * chip's register) is set.
- */
-enum fan_status {
-	FAN_STATUS_STOPPED = 0,
-	FAN_STATUS_CHANGING = 1,
-	FAN_STATUS_LOCKED = 2,
-	FAN_STATUS_FRUSTRATED = 3
-};
-enum fan_status fan_get_status(int ch);
-
-/* Initialize the HW according to the desired flags */
-void fan_channel_setup(int ch, unsigned int flags);
-
-int fan_get_count(void);
-
-void fan_set_count(int count);
-
-int is_thermal_control_enabled(int idx);
-
-#endif  /* __CROS_EC_FAN_H */
diff --git a/include/flash_log.h b/include/flash_log.h
deleted file mode 100644
index e504df6ee7..0000000000
--- a/include/flash_log.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_EVENT_LOG_H
-#define __CROS_EC_EVENT_LOG_H
-
-#include "config.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "stddef.h"
-
-enum flash_event_type {
-	FE_LOG_START = 0,
-	FE_LOG_CORRUPTED = 1,
-	FE_TPM_I2C_ERROR = 2,
-	FE_LOG_OVERFLOWS = 3, /* A single byte, overflow counter. */
-	FE_LOG_LOCKS = 4,     /* A single byte, lock failures counter. */
-	FE_LOG_NVMEM = 5,     /* NVMEM failure, variable structure. */
-	FE_LOG_TPM_WIPE_ERROR = 6,     /* Failed to wipe the TPM */
-	FE_LOG_TRNG_STALL = 7,     /* Stall while retrieving a random number. */
-	FE_LOG_DCRYPTO_FAILURE = 8, /* Dcrypto had to be reset. */
-
-	/*
-	 * Fixed padding value makes it easier to parse log space
-	 * snapshots.
-	 */
-	FE_LOG_PAD = 253,
-	/* A test event, the highest possible event type value. */
-	FE_LOG_TEST = 254,
-};
-struct flash_log_entry {
-	/*
-	 * Until real wall clock time is available this is a monotonically
-	 * increasing entry number.
-	 *
-	 * TODO(vbendeb): however unlikely, there could be multiple events
-	 *    logged within the same 1 second interval. There needs to be a
-	 *    way to handle this. Maybe storing incremental time, having only
-	 *    the very first entry in the log carry the real time. Maybe
-	 *    enhancing the log traversion function to allow multiple entries
-	 *    with the same timestamp value.
-	 */
-	uint32_t timestamp;
-	uint8_t size; /* [7:6] caller-def'd [5:0] payload size in bytes. */
-	uint8_t type; /* event type, caller-defined */
-	uint8_t crc;
-	uint8_t payload[0]; /* optional additional data payload: 0..63 bytes. */
-} __packed;
-
-/* Payloads for various log events. */
-/* NVMEM failures. */
-enum nvmem_failure_type {
-	NVMEMF_MALLOC = 0,
-	NVMEMF_PH_SIZE_MISMATCH = 1,
-	NVMEMF_READ_UNDERRUN = 2,
-	NVMEMF_INCONSISTENT_FLASH_CONTENTS = 3,
-	NVMEMF_MIGRATION_FAILURE = 4,
-	NVMEMF_LEGACY_ERASE_FAILURE = 5,
-	NVMEMF_EXCESS_DELETE_OBJECTS = 6,
-	NVMEMF_UNEXPECTED_LAST_OBJ = 7,
-	NVMEMF_MISSING_OBJECT = 8,
-	NVMEMF_SECTION_VERIFY = 9,
-	NVMEMF_PRE_ERASE_MISMATCH = 10,
-	NVMEMF_PAGE_LIST_OVERFLOW = 11,
-	NVMEMF_CIPHER_ERROR = 12,
-	NVMEMF_CORRUPTED_INIT = 13,
-	NVMEMF_CONTAINER_HASH_MISMATCH = 14,
-	NVMEMF_UNRECOVERABLE_INIT = 15,
-	NVMEMF_NVMEM_WIPE = 16,
-};
-
-/* Not all nvmem failures require payload. */
-struct nvmem_failure_payload {
-	uint8_t failure_type;
-	union {
-		uint16_t size; /* How much memory was requested. */
-		struct {
-			uint16_t ph_offset;
-			uint16_t expected;
-		} ph __packed;
-		uint16_t underrun_size; /* How many bytes short. */
-		uint8_t last_obj_type;
-	} __packed;
-} __packed;
-
-/* Returned in the "type" field, when there is no entry available */
-#define FLASH_LOG_NO_ENTRY 0xff
-#define MAX_FLASH_LOG_PAYLOAD_SIZE ((1 << 6) - 1)
-#define FLASH_LOG_PAYLOAD_SIZE_MASK (MAX_FLASH_LOG_PAYLOAD_SIZE)
-
-#define FLASH_LOG_PAYLOAD_SIZE(size) ((size)&FLASH_LOG_PAYLOAD_SIZE_MASK)
-/* Size of log entry for a specific payload size. */
-#define FLASH_LOG_ENTRY_SIZE(payload_sz)                                       \
-	((FLASH_LOG_PAYLOAD_SIZE(payload_sz) +                                 \
-	  sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) &      \
-	 ~(CONFIG_FLASH_WRITE_SIZE - 1))
-
-/*
- * Flash log implementation expects minimum flash write size not to exceed the
- * log header structure size.
- *
- * It will be easy to extend implementation to cover larger write sizes if
- * necessary.
- */
-BUILD_ASSERT(sizeof(struct flash_log_entry) >= CONFIG_FLASH_WRITE_SIZE);
-
-/* A helper structure to represent maximum size flash elog event entry. */
-union entry_u {
-	uint8_t entry[FLASH_LOG_ENTRY_SIZE(MAX_FLASH_LOG_PAYLOAD_SIZE)];
-	struct flash_log_entry r;
-};
-
-#define COMPACTION_SPACE_PRESERVE (CONFIG_FLASH_LOG_SPACE / 4)
-#define STARTUP_LOG_FULL_WATERMARK (CONFIG_FLASH_LOG_SPACE * 3 / 4)
-#define RUN_TIME_LOG_FULL_WATERMARK (CONFIG_FLASH_LOG_SPACE * 9 / 10)
-
-/*
- * Add an entry to the event log. No errors are reported, as there is little
- * we can do if logging attempt fails.
- */
-void flash_log_add_event(uint8_t type, uint8_t size, void *payload);
-
-/*
- * Report the next event after the passed in number.
- *
- * Return
- *  - positive integer - the size of the retrieved event
- *  - 0 if there is no more events
- *  - -EC_ERROR_BUSY if event logging is in progress
- *  - -EC_ERROR_MEMORY_ALLOCATION if event body does not fit into the buffer
- *  - -EC_ERROR_INVAL in case log storage is corrupted
- */
-int flash_log_dequeue_event(uint32_t event_after, void *buffer,
-			    size_t buffer_size);
-
-void flash_log_register_flash_control_callback(
-	void (*flash_control)(int enable));
-
-/*
- * Set log timestamp base. The argument is current epoch time in seconds.
- * Return value of EC_ERROR_INVAL indicates attempt to set the timestamp base
- * to a value below the latest log entry timestamp.
- */
-enum ec_error_list flash_log_set_tstamp(uint32_t tstamp);
-
-/* Get current log timestamp value. */
-uint32_t flash_log_get_tstamp(void);
-
-#if defined(TEST_BUILD)
-void flash_log_init(void);
-extern uint32_t last_used_timestamp;
-extern uint32_t lock_failures_count;
-extern uint8_t log_event_in_progress;
-#endif
-
-#endif /* __CROS_EC_EVENT_LOG_H */
diff --git a/include/fpsensor.h b/include/fpsensor.h
deleted file mode 100644
index 2c5baa2679..0000000000
--- a/include/fpsensor.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fingerprint sensor interface */
-
-#ifndef __CROS_EC_FPSENSOR_H
-#define __CROS_EC_FPSENSOR_H
-
-#include <stdint.h>
-#include "common.h"
-#include "ec_commands.h"
-
-#ifndef SPI_FP_DEVICE
-#define SPI_FP_DEVICE (&spi_devices[0])
-#endif
-
-/*  Four-character-code */
-#define FOURCC(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
-			   ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
-
-/* 8-bit greyscale pixel format as defined by V4L2 headers */
-#define V4L2_PIX_FMT_GREY FOURCC('G', 'R', 'E', 'Y')
-
-/* --- functions provided by the sensor-specific driver --- */
-
-/* Initialize the connected sensor hardware and put it in a low power mode. */
-int fp_sensor_init(void);
-
-/* De-initialize the sensor hardware. */
-int fp_sensor_deinit(void);
-
-/*
- * Fill the 'ec_response_fp_info' buffer with the sensor information
- * as required by the EC_CMD_FP_INFO host command.
- *
- * Put both the static information and the ones read from the sensor at runtime.
- */
-int fp_sensor_get_info(struct ec_response_fp_info *resp);
-
-/*
- * Put the sensor in its lowest power state.
- *
- * fp_sensor_configure_detect needs to be called to restore finger detection
- * functionality.
- */
-void fp_sensor_low_power(void);
-
-/*
- * Configure finger detection.
- *
- * Send the settings to the sensor, so it is properly configured to detect
- * the presence of a finger.
- */
-void fp_sensor_configure_detect(void);
-
-/*
- * Returns the status of the finger on the sensor.
- * (assumes fp_sensor_configure_detect was called before)
- */
-enum finger_state {
-	FINGER_NONE = 0,
-	FINGER_PARTIAL = 1,
-	FINGER_PRESENT = 2,
-};
-enum finger_state fp_sensor_finger_status(void);
-
-/*
- * Acquires a fingerprint image.
- *
- * This function is called once the finger has been detected and cover enough
- * area of the sensor (ie fp_sensor_finger_status returned FINGER_PRESENT).
- * It does the acquisition immediately.
- * The image_data parameter points to an image data buffer of size
- *
- * FP_SENSOR_IMAGE_SIZE allocated by the caller.
- * Returns:
- * - 0 on success
- * - negative value on error
- * - FP_SENSOR_LOW_IMAGE_QUALITY on image captured but quality is too low
- * - FP_SENSOR_TOO_FAST on finger removed before image was captured
- * - FP_SENSOR_LOW_SENSOR_COVERAGE on sensor not fully covered by finger
- */
-#define FP_SENSOR_LOW_IMAGE_QUALITY 1
-#define FP_SENSOR_TOO_FAST 2
-#define FP_SENSOR_LOW_SENSOR_COVERAGE 3
-int fp_sensor_acquire_image(uint8_t *image_data);
-
-/*
- * Acquires a fingerprint image with specific capture mode.
- *
- * Same as the fp_sensor_acquire_image function above,
- * excepted 'mode' can be set to one of the FP_CAPTURE_ constants
- * to get a specific image type (e.g. a pattern) rather than the default one.
- */
-int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode);
-
-/*
- * Compares given finger image against enrolled templates.
- *
- * The matching algorithm can update the template with additional biometric data
- * from the image, if it chooses to do so.
- *
- * @param templ a pointer to the array of template buffers.
- * @param templ_count the number of buffers in the array of templates.
- * @param image the buffer containing the finger image
- * @param match_index index of the matched finger in the template array if any.
- * @param update_bitmap contains one bit per template, the bit is set if the
- * match has updated the given template.
- * @return negative value on error, else one of the following code :
- * - EC_MKBP_FP_ERR_MATCH_NO on non-match
- * - EC_MKBP_FP_ERR_MATCH_YES for match when template was not updated with
- *   new data
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATED for match when template was updated
- * - EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED match, but update failed (not saved)
- * - EC_MKBP_FP_ERR_MATCH_LOW_QUALITY when matching could not be performed due
- *   to low image quality
- * - EC_MKBP_FP_ERR_MATCH_LOW_COVERAGE when matching could not be performed
- *   due to finger covering too little area of the sensor
- */
-int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
-		    int32_t *match_index, uint32_t *update_bitmap);
-
-/*
- * Start a finger enrollment session.
- *
- * @return 0 on success or a negative error code.
- */
-int fp_enrollment_begin(void);
-
-/*
- * Generate a template from the finger whose enrollment has just being
- * completed.
- *
- * @param templ the buffer which will receive the template.
- * templ can be set to NULL to abort the current enrollment process.
- *
- * @return 0 on success or a negative error code.
- */
-int fp_enrollment_finish(void *templ);
-
-/*
- * Adds fingerprint image to the current enrollment session.
- *
- * @return a negative value on error or one of the following codes:
- * - EC_MKBP_FP_ERR_ENROLL_OK when image was successfully enrolled
- * - EC_MKBP_FP_ERR_ENROLL_IMMOBILE when image added, but user should be
- *   advised to move finger
- * - EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY when image could not be used due to low
- *   image quality
- * - EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE when image could not be used due to
- *   finger covering too little area of the sensor
- */
-int fp_finger_enroll(uint8_t *image, int *completion);
-
-/**
- * Runs a test for defective pixels.
- *
- * Should be triggered periodically by the client. The maintenance command can
- * take several hundred milliseconds to run.
- *
- * @return EC_ERROR_HW_INTERNAL on error (such as finger on sensor)
- * @return EC_SUCCESS on success
- */
-int fp_maintenance(void);
-
-#endif /* __CROS_EC_FPSENSOR_H */
diff --git a/include/fpsensor_crypto.h b/include/fpsensor_crypto.h
deleted file mode 100644
index b6252b3fd2..0000000000
--- a/include/fpsensor_crypto.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fingerprint sensor crypto operations */
-
-#ifndef __CROS_EC_FPSENSOR_CRYPTO_H
-#define __CROS_EC_FPSENSOR_CRYPTO_H
-
-#include <stddef.h>
-
-#include "sha256.h"
-
-#define HKDF_MAX_INFO_SIZE 128
-#define HKDF_SHA256_MAX_BLOCK_COUNT 255
-
-/**
- * Expand hkdf pseudorandom key |prk| to length |out_key_size|.
- *
- * @param out_key the buffer to hold output key material.
- * @param out_key_size length of output key in bytes. Must be less than
- * or equal to HKDF_SHA256_MAX_BLOCK_COUNT * SHA256_DIGEST_SIZE bytes.
- * @param prk pseudorandom key.
- * @param prk_size length of |prk| in bytes.
- * @param info optional context.
- * @param info_size size of |info| in bytes, must be less than or equal to
- * HKDF_MAX_INFO_SIZE bytes.
- * @return EC_SUCCESS on success and error code otherwise.
- */
-int hkdf_expand(uint8_t *out_key, size_t out_key_size, const uint8_t *prk,
-		size_t prk_size, const uint8_t *info, size_t info_size);
-
-/**
- * Derive hardware encryption key from rollback secret and |salt|.
- *
- * @param outkey the pointer to buffer holding the output key.
- * @param salt the salt to use in HKDF.
- * @return EC_SUCCESS on success and error code otherwise.
- */
-int derive_encryption_key(uint8_t *out_key, const uint8_t *salt);
-
-/**
- * Derive positive match secret from |input_positive_match_salt| and
- * SBP_Src_Key.
- *
- * @param output buffer to store positive match secret, must be at least
- * FP_POSITIVE_MATCH_SECRET_BYTES in size.
- * @param input_positive_match_salt the salt for deriving secret, must be at
- * least FP_POSITIVE_MATCH_SALT_BYTES in size.
- * @return EC_SUCCESS on success and error code otherwise.
- */
-int derive_positive_match_secret(uint8_t *output,
-				 const uint8_t *input_positive_match_salt);
-
-/**
- * Encrypt |plaintext| using AES-GCM128.
- *
- * @param key the key to use in AES.
- * @param key_size the size of |key| in bytes.
- * @param plaintext the plain text to encrypt.
- * @param ciphertext buffer to hold encryption result.
- * @param text_size size of both |plaintext| and output ciphertext in bytes.
- * @param nonce the nonce value to use in GCM128.
- * @param nonce_size the size of |nonce| in bytes.
- * @param tag the tag to hold the authenticator after encryption.
- * @param tag_size the size of |tag|.
- * @return EC_SUCCESS on success and error code otherwise.
- */
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size);
-
-/**
- * Decrypt |plaintext| using AES-GCM128.
- *
- * @param key the key to use in AES.
- * @param key_size the size of |key| in bytes.
- * @param ciphertext the cipher text to decrypt.
- * @param plaintext buffer to hold decryption result.
- * @param text_size size of both |ciphertext| and output plaintext in bytes.
- * @param nonce the nonce value to use in GCM128.
- * @param nonce_size the size of |nonce| in bytes.
- * @param tag the tag to compare against when decryption finishes.
- * @param tag_size the length of tag to compare against.
- * @return EC_SUCCESS on success and error code otherwise.
- */
-int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
-		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size);
-
-#endif /* __CROS_EC_FPSENSOR_CRYPTO_H */
diff --git a/include/fpsensor_state.h b/include/fpsensor_state.h
deleted file mode 100644
index 6b752bc86d..0000000000
--- a/include/fpsensor_state.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Fingerprint sensor interface */
-
-#ifndef __CROS_EC_FPSENSOR_STATE_H
-#define __CROS_EC_FPSENSOR_STATE_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "common.h"
-#include "ec_commands.h"
-#include "link_defs.h"
-#include "timer.h"
-
-#include "driver/fingerprint/fpsensor.h"
-
-/* if no special memory regions are defined, fallback on regular SRAM */
-#ifndef FP_FRAME_SECTION
-#define FP_FRAME_SECTION
-#endif
-#ifndef FP_TEMPLATE_SECTION
-#define FP_TEMPLATE_SECTION
-#endif
-
-#define SBP_ENC_KEY_LEN 16
-#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \
-	(FP_ALGORITHM_TEMPLATE_SIZE + \
-		FP_POSITIVE_MATCH_SALT_BYTES + \
-		sizeof(struct ec_fp_template_encryption_metadata))
-
-/* Events for the FPSENSOR task */
-#define TASK_EVENT_SENSOR_IRQ     TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_UPDATE_CONFIG  TASK_EVENT_CUSTOM_BIT(1)
-
-#define FP_NO_SUCH_TEMPLATE -1
-
-/* --- Global variables defined in fpsensor_state.c --- */
-
-/* Last acquired frame (aligned as it is used by arbitrary binary libraries) */
-extern uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE];
-/* Fingers templates for the current user */
-extern uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE];
-/* Encryption/decryption buffer */
-/* TODO: On-the-fly encryption/decryption without a dedicated buffer */
-/*
- * Store the encryption metadata at the beginning of the buffer containing the
- * ciphered data.
- */
-extern uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE];
-/* Salt used in derivation of positive match secret. */
-extern uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
-/* Index of the last enrolled but not retrieved template. */
-extern int8_t template_newly_enrolled;
-/* Number of used templates */
-extern uint32_t templ_valid;
-/* Bitmap of the templates with local modifications */
-extern uint32_t templ_dirty;
-/* Current user ID */
-extern uint32_t user_id[FP_CONTEXT_USERID_WORDS];
-/* Part of the IKM used to derive encryption keys received from the TPM. */
-extern uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES];
-
-extern uint32_t fp_events;
-
-extern uint32_t sensor_mode;
-
-struct positive_match_secret_state {
-	/* Index of the most recently matched template. */
-	int8_t template_matched;
-	/* Flag indicating positive match secret can be read. */
-	bool readable;
-	/* Deadline to read positive match secret. */
-	timestamp_t deadline;
-};
-
-extern struct positive_match_secret_state positive_match_secret_state;
-
-/* Simulation for unit tests. */
-void fp_task_simulate(void);
-
-/*
- * Clear one fingerprint template.
- *
- * @param idx the index of the template to clear.
- */
-void fp_clear_finger_context(int idx);
-
-/**
- * Clear all fingerprint templates associated with the current user id and
- * reset the sensor.
- */
-void fp_reset_and_clear_context(void);
-
-/*
- * Get the next FP event.
- *
- * @param out the pointer to the output event.
- */
-int fp_get_next_event(uint8_t *out);
-
-/*
- * Check if FP TPM seed has been set.
- *
- * @return 1 if the seed has been set, 0 otherwise.
- */
-int fp_tpm_seed_is_set(void);
-
-/**
- * Change the sensor mode.
- *
- * @param mode          new mode to change to
- * @param mode_output   resulting mode
- * @return EC_RES_SUCCESS on success. Error code on failure.
- */
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
-
-/**
- * Allow reading positive match secret for |fgr| in the next 5 seconds.
- *
- * @param fgr the index of template to enable positive match secret.
- * @param state the state of positive match secret, e.g. readable or not.
- * @return EC_SUCCESS if the request is valid, error code otherwise.
- */
-int fp_enable_positive_match_secret(uint32_t fgr,
-	struct positive_match_secret_state *state);
-
-/**
- * Disallow positive match secret for any finger to be read.
- *
- * @param state the state of positive match secret, e.g. readable or not.
- */
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state);
-
-#endif /* __CROS_EC_FPSENSOR_STATE_H */
diff --git a/include/gyro_cal.h b/include/gyro_cal.h
deleted file mode 100644
index fb69464aec..0000000000
--- a/include/gyro_cal.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GYRO_CAL_H
-#define __CROS_EC_GYRO_CAL_H
-
-#include "common.h"
-#include "gyro_still_det.h"
-#include "math_util.h"
-#include "stdbool.h"
-#include "stddef.h"
-#include "vec3.h"
-
-struct temperature_mean_data {
-	int16_t temperature_min_kelvin;
-	int16_t temperature_max_kelvin;
-	int16_t latest_temperature_kelvin;
-	int mean_accumulator;
-	size_t num_points;
-};
-
-/** Data structure for tracking min/max window mean during device stillness. */
-struct min_max_window_mean_data {
-	fpv3_t gyro_winmean_min;
-	fpv3_t gyro_winmean_max;
-};
-
-struct gyro_cal {
-	/** Stillness detector for accelerometer. */
-	struct gyro_still_det accel_stillness_detect;
-	/** Stillness detector for magnetometer. */
-	struct gyro_still_det mag_stillness_detect;
-	/** Stillness detector for gyroscope. */
-	struct gyro_still_det gyro_stillness_detect;
-
-	/**
-	 * Data for tracking temperature mean during periods of device
-	 * stillness.
-	 */
-	struct temperature_mean_data temperature_mean_tracker;
-
-	/** Data for tracking gyro mean during periods of device stillness. */
-	struct min_max_window_mean_data window_mean_tracker;
-
-	/**
-	 * Aggregated sensor stillness threshold required for gyro bias
-	 * calibration.
-	 */
-	fp_t stillness_threshold;
-
-	/** Min and max durations for gyro bias calibration. */
-	uint32_t min_still_duration_us;
-	uint32_t max_still_duration_us;
-
-	/** Duration of the stillness processing windows. */
-	uint32_t window_time_duration_us;
-
-	/** Timestamp when device started a still period. */
-	uint64_t start_still_time_us;
-
-	/**
-	 * Gyro offset estimate, and the associated calibration temperature,
-	 * timestamp, and stillness confidence values.
-	 * [rad/sec]
-	 */
-	fp_t bias_x, bias_y, bias_z;
-	int bias_temperature_kelvin;
-	fp_t stillness_confidence;
-	uint32_t calibration_time_us;
-
-	/**
-	 * Current window end-time for all sensors. Used to assist in keeping
-	 * sensor data collection in sync. On initialization this will be set to
-	 * zero indicating that sensor data will be dropped until a valid
-	 * end-time is set from the first gyro timestamp received.
-	 */
-	uint32_t stillness_win_endtime_us;
-
-	/**
-	 * Watchdog timer to reset to a known good state when data capture
-	 * stalls.
-	 */
-	uint32_t gyro_window_start_us;
-	uint32_t gyro_window_timeout_duration_us;
-
-	/** Flag is "true" when the magnetometer is used. */
-	bool using_mag_sensor;
-
-	/** Flag set by user to control whether calibrations are used. */
-	bool gyro_calibration_enable;
-
-	/** Flag is 'true' when a new calibration update is ready. */
-	bool new_gyro_cal_available;
-
-	/** Flag to indicate if device was previously still. */
-	bool prev_still;
-
-	/**
-	 * Min and maximum stillness window mean. This is used to check the
-	 * stability of the mean values computed for the gyroscope (i.e.
-	 * provides further validation for stillness).
-	 */
-	fpv3_t gyro_winmean_min;
-	fpv3_t gyro_winmean_max;
-	fp_t stillness_mean_delta_limit;
-
-	/**
-	 * The mean temperature over the stillness period. The limit is used to
-	 * check for temperature stability and provide a gate for when
-	 * temperature is rapidly changing.
-	 */
-	fp_t temperature_mean_kelvin;
-	fp_t temperature_delta_limit_kelvin;
-};
-
-/**
- * Data structure used to configure the gyroscope calibration in individual
- * sensors.
- */
-struct gyro_cal_data {
-	/** The gyro_cal struct to use. */
-	struct gyro_cal gyro_cal;
-	/** The sensor ID of the accelerometer to use. */
-	uint8_t accel_sensor_id;
-	/**
-	 * The sensor ID of the accelerometer to use (use a number greater than
-	 * SENSOR_COUNT to skip).
-	 */
-	uint8_t mag_sensor_id;
-};
-
-/** Reset trackers. */
-void init_gyro_cal(struct gyro_cal *gyro_cal);
-
-/** Get the most recent bias calibration value. */
-void gyro_cal_get_bias(struct gyro_cal *gyro_cal, fpv3_t bias,
-		       int *temperature_kelvin, uint32_t *calibration_time_us);
-
-/** Set an initial bias calibration value. */
-void gyro_cal_set_bias(struct gyro_cal *gyro_cal, fpv3_t bias,
-		       int temperature_kelvin, uint32_t calibration_time_us);
-
-/** Remove gyro bias from the calibration [rad/sec]. */
-void gyro_cal_remove_bias(struct gyro_cal *gyro_cal, fpv3_t in, fpv3_t out);
-
-/** Returns true when a new gyro calibration is available. */
-bool gyro_cal_new_bias_available(struct gyro_cal *gyro_cal);
-
-/** Update the gyro calibration with gyro data [rad/sec]. */
-void gyro_cal_update_gyro(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			  fp_t x, fp_t y, fp_t z, int temperature_kelvin);
-
-/** Update the gyro calibration with mag data [micro Tesla]. */
-void gyro_cal_update_mag(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			 fp_t x, fp_t y, fp_t z);
-
-/** Update the gyro calibration with accel data [m/sec^2]. */
-void gyro_cal_update_accel(struct gyro_cal *gyro_cal, uint32_t sample_time_us,
-			   fp_t x, fp_t y, fp_t z);
-
-#endif /* __CROS_EC_GYRO_CAL_H */
diff --git a/include/gyro_still_det.h b/include/gyro_still_det.h
deleted file mode 100644
index a776da7ae7..0000000000
--- a/include/gyro_still_det.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GYRO_STILL_DET_H
-#define __CROS_EC_GYRO_STILL_DET_H
-
-#include "common.h"
-#include "math_util.h"
-#include "stdbool.h"
-#include "vec3.h"
-
-struct gyro_still_det {
-	/**
-	 * Variance threshold for the stillness confidence score.
-	 * [sensor units]^2
-	 */
-	fp_t var_threshold;
-
-	/**
-	 * Delta about the variance threshold for calculation of the stillness
-	 * confidence score [0,1]. [sensor units]^2
-	 */
-	fp_t confidence_delta;
-
-	/**
-	 * Flag to indicate when enough samples have been collected for
-	 * a complete stillness calculation.
-	 */
-	bool stillness_window_ready;
-
-	/**
-	 * Flag to signal the beginning of a new stillness detection window.
-	 * This is used to keep track of the window start time.
-	 */
-	bool start_new_window;
-
-	/** Starting time stamp for the current window. */
-	uint32_t window_start_time;
-
-	/**
-	 * Accumulator variables for tracking the sample mean during
-	 * the stillness period.
-	 */
-	uint32_t num_acc_samples;
-	fpv3_t mean;
-
-	/**
-	 * Accumulator variables for computing the window sample mean and
-	 * variance for the current window (used for stillness detection).
-	 */
-	uint32_t num_acc_win_samples;
-	fpv3_t win_mean;
-	fpv3_t assumed_mean;
-	fpv3_t acc_var;
-
-	/** Stillness period mean (used for look-ahead). */
-	fpv3_t prev_mean;
-
-	/** Latest computed variance. */
-	fpv3_t win_var;
-
-	/**
-	 * Stillness confidence score for current and previous sample
-	 * windows [0,1] (used for look-ahead).
-	 */
-	fp_t stillness_confidence;
-	fp_t prev_stillness_confidence;
-
-	/** Timestamp of last sample recorded. */
-	uint32_t last_sample_time;
-};
-
-/** Update the stillness detector with a new sample. */
-void gyro_still_det_update(struct gyro_still_det *gyro_still_det,
-			   uint32_t stillness_win_endtime, uint32_t sample_time,
-			   fp_t x, fp_t y, fp_t z);
-
-/** Calculates and returns the stillness confidence score [0,1]. */
-fp_t gyro_still_det_compute(struct gyro_still_det *gyro_still_det);
-
-/**
- * Resets the stillness detector and initiates a new detection window.
- *
- * @param reset_stats Determines whether the stillness statistics are reset.
- */
-void gyro_still_det_reset(struct gyro_still_det *gyro_still_det,
-			  bool reset_stats);
-
-#endif /* __CROS_EC_GYRO_STILL_DET_H */
diff --git a/include/hotword_dsp_api.h b/include/hotword_dsp_api.h
deleted file mode 100644
index 369af00ede..0000000000
--- a/include/hotword_dsp_api.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef SPEECH_MICRO_API_HOTWORD_DSP_API_H_
-#define SPEECH_MICRO_API_HOTWORD_DSP_API_H_
-
-/*
- * This API creates a global singleton behind the scenes. It's the caller's
- * responsibility to store the contents of the hotword_memmap model file into
- * aligned memory and pass its pointer to this library. Note that no additional
- * memory is allocated and hotword_memmap will contain both the model and the
- * scratch buffers.
- */
-
-/* Specifies the required alignment for the hotword_memmap. */
-extern const int kGoogleHotwordRequiredDataAlignment;
-
-/*
- * Called to set up the Google hotword algorithm. Returns 1 if successful, and 0
- * otherwise.
- */
-int GoogleHotwordDspInit(void *hotword_memmap);
-
-/*
- * Call with every frame of samples to process. If a hotword is detected, this
- * function returns 1 otherwise 0. The required preamble length will be set to
- * the number of milliseconds of buffered audio to be transferred to the AP.
- */
-int GoogleHotwordDspProcess(const void *samples, int num_samples,
-			    int *preamble_length_ms);
-
-/*
- * If there's a break in the audio stream (e.g. when Sound Activity Detection is
- * enabled), call this before any subsequent calls to GoogleHotwordDspProcess.
- */
-void GoogleHotwordDspReset(void);
-
-/* Returns the maximum possible audio preamble length in miliseconds. */
-int GoogleHotwordDspGetMaximumAudioPreambleMs(void);
-
-/* Returns an internal version number that this library was built at. */
-extern int GoogleHotwordVersion(void);
-
-#endif  /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */
diff --git a/include/i2c_hid.h b/include/i2c_hid.h
deleted file mode 100644
index 8568b42837..0000000000
--- a/include/i2c_hid.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * General definitions for I2C-HID
- *
- * For a complete reference, please see the following docs on
- * https://docs.microsoft.com/
- *
- * 1. hid-over-i2c-protocol-spec-v1-0.docx
- */
-#ifndef __CROS_EC_I2C_HID_H
-#define __CROS_EC_I2C_HID_H
-
-#include "common.h"
-#include "stdint.h"
-
-/*
- * I2C-HID registers
- *
- * Except for I2C_HID_HID_DESC_REGISTER, fields in this section can be chosen
- * freely so we just picked something that we are happy with.
- *
- * I2C_HID_HID_DESC_REGISTER is defined in the ACPI table so please make sure
- * you have put in the same value there.
- */
-#define I2C_HID_HID_DESC_REGISTER	0x0001
-#define I2C_HID_REPORT_DESC_REGISTER	0x1000
-#define I2C_HID_INPUT_REPORT_REGISTER	0x2000
-#define I2C_HID_COMMAND_REGISTER	0x3000
-#define I2C_HID_DATA_REGISTER		0x3000
-
-/* I2C-HID commands */
-#define I2C_HID_CMD_RESET		0x01
-#define I2C_HID_CMD_GET_REPORT		0x02
-#define I2C_HID_CMD_SET_REPORT		0x03
-#define I2C_HID_CMD_GET_IDLE		0x04
-#define I2C_HID_CMD_SET_IDLE		0x05
-#define I2C_HID_CMD_GET_PROTOCOL	0x06
-#define I2C_HID_CMD_SET_PROTOCOL	0x07
-#define I2C_HID_CMD_SET_POWER		0x08
-
-/* Common HID fields */
-#define I2C_HID_DESC_LENGTH		sizeof(struct i2c_hid_descriptor)
-#define I2C_HID_BCD_VERSION		0x0100
-
-/* I2C-HID HID descriptor */
-struct __packed i2c_hid_descriptor {
-	uint16_t wHIDDescLength;
-	uint16_t bcdVersion;
-	uint16_t wReportDescLength;
-	uint16_t wReportDescRegister;
-	uint16_t wInputRegister;
-	uint16_t wMaxInputLength;
-	uint16_t wOutputRegister;
-	uint16_t wMaxOutputLength;
-	uint16_t wCommandRegister;
-	uint16_t wDataRegister;
-	uint16_t wVendorID;
-	uint16_t wProductID;
-	uint16_t wVersionID;
-	uint32_t reserved;
-};
-
-#endif /* __CROS_EC_I2C_HID_H */
diff --git a/include/i2c_hid_touchpad.h b/include/i2c_hid_touchpad.h
deleted file mode 100644
index d5d728a488..0000000000
--- a/include/i2c_hid_touchpad.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Implementation of I2C HID for touchpads */
-#ifndef __CROS_EC_I2C_HID_TOUCHPAD_H
-#define __CROS_EC_I2C_HID_TOUCHPAD_H
-
-#include "common.h"
-#include "i2c_hid.h"
-#include "stdbool.h"
-#include "stdint.h"
-
-/* Max fingers to support */
-#define I2C_HID_TOUCHPAD_MAX_FINGERS	5
-
-/*
- * Struct holding a touchpad event
- *
- * The user should parse the original touchpad report, apply necessary
- * transformations and fill the result in this common struct. The touchpad is
- * assumed to implement the Linux HID MT-B protocol.
- */
-struct touchpad_event {
-	/* If hover is detected */
-	bool hover;
-	/* If button is clicked */
-	bool button;
-	/* Struct for contacts */
-	struct {
-		/* X & Y of the contact */
-		uint16_t x;
-		uint16_t y;
-		/* Pressure/contact area */
-		uint16_t pressure;
-		/* W & H of the contact */
-		uint16_t width;
-		uint16_t height;
-		/*
-		 * Orientation of the contact ellipse. Can be plain 0 if
-		 * unavailable.
-		 */
-		uint16_t orientation;
-		/*
-		 * If the touchpad believes it is a palm. Some touchpads report
-		 * it through the confidence field.
-		 */
-		bool is_palm;
-		/* If this slot contains valid contact (touching the surface) */
-		bool valid;
-	} __packed finger[I2C_HID_TOUCHPAD_MAX_FINGERS];
-} __packed;
-
-/* Initialize the I2C HID touchpad */
-void i2c_hid_touchpad_init(void);
-/*
- * Process an I2C-HID command from host.
- *
- * @param len		>= 0 - Input data length in bytes
- * @param buffer	Shared input/output buffer
- * @param send_response	Function to send the response to host
- * @param data		Extracted request content if there is any
- * @param reg		I2C HID register as defined in include/i2c-hid.h
- * @param cmd		I2C HID command as defined in common/i2c_hid_touchpad.c
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int i2c_hid_touchpad_process(unsigned int len, uint8_t *buffer,
-			     void (*send_response)(int len), uint8_t *data,
-			     int *reg, int *cmd);
-/**
- * Compile an (outgoing) HID input report for an (incoming) touchpad event
- *
- * The compiled report would be sent next time when the host requests one.
- *
- * @param touchpad_event	Touchpad event data
- */
-void i2c_hid_compile_report(struct touchpad_event *event);
-
-#endif /* __CROS_EC_I2C_HID_TOUCHPAD_H */
diff --git a/include/i2c_ite_flash_support.h b/include/i2c_ite_flash_support.h
deleted file mode 100644
index f70bec877a..0000000000
--- a/include/i2c_ite_flash_support.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* API for module that provides flash support for ITE-based ECs over i2c */
-
-#ifndef __CROS_EC_I2C_ITE_FLASH_SUPPORT_H
-#define __CROS_EC_I2C_ITE_FLASH_SUPPORT_H
-
-#include "gpio.h"
-#include "stdbool.h"
-
-struct ite_dfu_config_t {
-	/* I2C port to communicate on */
-	int i2c_port;
-	/* True if using OC1N instead of OC1 */
-	bool use_complement_timer_channel;
-	/*
-	 * Optional function that guards access to i2c port. If present, the
-	 * return value should return true if dfu access is allowed and false
-	 * otherwise.
-	 */
-	bool (*access_allow)(void);
-	/*
-	 * The gpio signals that moved between TIM16/17 (MODULE_I2C_TIMERS) and
-	 * I2C (MODULE_I2C).
-	 */
-	enum gpio_signal scl;
-	enum gpio_signal sda;
-};
-
-/* Provided by board implementation if CONFIG_ITE_FLASH_SUPPORT is used */
-const extern struct ite_dfu_config_t ite_dfu_config;
-
-#endif /* __CROS_EC_I2C_ITE_FLASH_SUPPORT_H */
diff --git a/include/i2c_peripheral.h b/include/i2c_peripheral.h
deleted file mode 100644
index 488e886b0e..0000000000
--- a/include/i2c_peripheral.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* I2C peripheral interface for Chrome EC */
-
-#ifndef __CROS_EC_I2C_PERIPHERAL_H
-#define __CROS_EC_I2C_PERIPHERAL_H
-
-/* Data structure to define I2C peripheral port configuration. */
-struct i2c_periph_port_t {
-	const char *name;     /* Port name */
-	int port;             /* Port */
-	uint8_t addr;         /* address(7-bit without R/W) */
-};
-
-extern const struct i2c_periph_port_t i2c_periph_ports[];
-extern const unsigned int i2c_periphs_used;
-
-#endif /* __CROS_EC_I2C_PERIPHERAL_H */
diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h
deleted file mode 100644
index 7e554fc03e..0000000000
--- a/include/i8042_protocol.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * i8042 keyboard protocol constants
- */
-
-#ifndef __CROS_EC_I8042_PROTOCOL_H
-#define __CROS_EC_I8042_PROTOCOL_H
-
-/* Some commands appear more than once.  Why? */
-
-/* port 0x60 */
-#define I8042_CMD_MOUSE_1_1     0xe6
-#define I8042_CMD_MOUSE_2_1     0xe7
-#define I8042_CMD_MOUSE_RES     0xe8
-#define I8042_CMD_OK_GETID      0xe8
-#define I8042_CMD_GET_MOUSE     0xe9
-#define I8042_CMD_EX_ENABLE     0xea
-#define I8042_CMD_EX_SETLEDS    0xeb
-#define I8042_CMD_SETLEDS       0xed
-#define I8042_CMD_DIAG_ECHO     0xee
-#define I8042_CMD_GSCANSET      0xf0
-#define I8042_CMD_SSCANSET      0xf0
-#define I8042_CMD_GETID         0xf2
-#define I8042_CMD_SETREP        0xf3
-#define I8042_CMD_ENABLE        0xf4
-#define I8042_CMD_RESET_DIS     0xf5
-#define I8042_CMD_RESET_DEF     0xf6
-#define I8042_CMD_ALL_TYPEM     0xf7
-#define I8042_CMD_SETALL_MB     0xf8
-#define I8042_CMD_SETALL_MBR    0xfa
-#define I8042_CMD_SET_A_KEY_T   0xfb
-#define I8042_CMD_SET_A_KEY_MR  0xfc
-#define I8042_CMD_SET_A_KEY_M   0xfd
-#define I8042_CMD_RESET         0xff
-#define I8042_CMD_RESEND        0xfe
-
-/* port 0x64 */
-#define I8042_READ_CMD_BYTE     0x20
-#define I8042_READ_CTL_RAM      0x21
-#define I8042_READ_CTL_RAM_END  0x3f
-#define I8042_WRITE_CMD_BYTE    0x60  /* expect a byte on port 0x60 */
-#define I8042_WRITE_CTL_RAM     0x61
-#define I8042_WRITE_CTL_RAM_END 0x7f
-#define I8042_ROUTE_AUX0        0x90
-#define I8042_ROUTE_AUX1        0x91
-#define I8042_ROUTE_AUX2        0x92
-#define I8042_ROUTE_AUX3        0x93
-#define I8042_ENA_PASSWORD      0xa6
-#define I8042_DIS_MOUSE         0xa7
-#define I8042_ENA_MOUSE         0xa8
-#define I8042_TEST_MOUSE        0xa9
-#define I8042_RESET_SELF_TEST   0xaa
-#define I8042_TEST_KB_PORT      0xab
-#define I8042_DIS_KB            0xad
-#define I8042_ENA_KB            0xae
-#define I8042_READ_OUTPUT_PORT  0xd0
-#define I8042_WRITE_OUTPUT_PORT 0xd1
-#define I8042_ECHO_MOUSE        0xd3  /* expect a byte on port 0x60 */
-#define I8042_SEND_TO_MOUSE     0xd4  /* expect a byte on port 0x60 */
-#define I8042_DISABLE_A20       0xdd
-#define I8042_ENABLE_A20        0xdf
-#define I8042_PULSE_START       0xf0
-#define I8042_SYSTEM_RESET      0xfe
-#define I8042_PULSE_END         0xff
-
-/* port 0x60 return value */
-#define I8042_RET_EMUL0         0xe0
-#define I8042_RET_EMUL1         0xe1
-#define I8042_RET_ECHO          0xee
-#define I8042_RET_RELEASE       0xf0
-#define I8042_RET_HANJA         0xf1
-#define I8042_RET_HANGEUL       0xf2
-#define I8042_RET_ACK           0xfa
-#define I8042_RET_TEST_FAIL     0xfc
-#define I8042_RET_INTERNAL_FAIL 0xfd
-#define I8042_RET_NAK           0xfe
-#define I8042_RET_ERR           0xff
-
-/* port 64 - command byte bits */
-#define I8042_XLATE             BIT(6)
-#define I8042_AUX_DIS           BIT(5)
-#define I8042_KBD_DIS           BIT(4)
-#define I8042_SYS_FLAG          BIT(2)
-#define I8042_ENIRQ12           BIT(1)
-#define I8042_ENIRQ1            BIT(0)
-
-/* Status Flags */
-#define I8042_AUX_DATA		BIT(5)
-
-#endif /* __CROS_EC_I8042_PROTOCOL_H */
diff --git a/include/inductive_charging.h b/include/inductive_charging.h
deleted file mode 100644
index 5c44e410aa..0000000000
--- a/include/inductive_charging.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Inductive charging control */
-
-#include "gpio.h"
-
-#ifndef __CROS_EC_INDUCTIVE_CHARGING_H
-#define __CROS_EC_INDUCTIVE_CHARGING_H
-
-/*
- * Interrupt handler for inductive charging signal.
- *
- * @param signal  Signal which triggered the interrupt.
- */
-void inductive_charging_interrupt(enum gpio_signal);
-
-#endif
diff --git a/include/init_rom.h b/include/init_rom.h
deleted file mode 100644
index 2c1ab33cd5..0000000000
--- a/include/init_rom.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Routines for accessing data objects store in the .init_rom region.
- * Enabled with the CONFIG_CHIP_INIT_ROM_REGION config option. Data
- * objects are placed into the .init_rom region using the __init_rom attribute.
- */
-
-#ifndef __CROS_EC_INIT_ROM_H
-#define __CROS_EC_INIT_ROM_H
-
-#include "stdbool.h"
-
-#ifdef CONFIG_CHIP_INIT_ROM_REGION
-/**
- * Get the memory mapped address of an .init_rom data object.
- *
- * @param offset	Address of the data object assigned by the linker.
- *			This is effectively a flash offset when
- *			CONFIG_CHIP_INIT_ROM_REGION is enabled, otherwise
- *			it is a regular address.
- * @param size	        Size of the data object.
- *
- * @return Pointer to data object in memory. Return NULL if the object
- * is not memory mapped.
- */
-const void *init_rom_map(const void *addr, int size);
-
-/**
- * Unmaps an .init_rom data object. Must be called when init_rom_map() is
- * successful.
- *
- * @param offset	Address of the data object assigned by the linker.
- * @param size	        Size of the data object.
- */
-void init_rom_unmap(const void *addr, int size);
-
-/**
- * Copy an .init_rom data object into a RAM location. This routine must be used
- * if init_rom_get_addr() returns NULL. This routine automatically handles
- * locking of the flash.
- *
- * @param offset	Flash offset of the data object.
- * @param size	        Size of the data object.
- * @param data		Destination buffer for data.
- *
- * @return 0 on success.
- */
-int init_rom_copy(int offset, int size, char *data);
-#else
-static inline const void *init_rom_map(const void *addr, int size)
-{
-	return addr;
-}
-
-static inline void init_rom_unmap(const void *addr, int size)
-{
-}
-
-static inline int init_rom_copy(int offset, int size, char *data)
-{
-	return 0;
-}
-#endif
-
-#endif /* __CROS_EC_INIT_ROM_H */
diff --git a/include/keyboard_8042.h b/include/keyboard_8042.h
deleted file mode 100644
index 6826eb98ac..0000000000
--- a/include/keyboard_8042.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * The functions implemented by keyboard component of EC core.
- */
-
-#ifndef __CROS_EC_KEYBOARD_8042_H
-#define __CROS_EC_KEYBOARD_8042_H
-
-#include "common.h"
-#include "button.h"
-
-/**
- * Called by power button handler and button interrupt handler.
- *
- * This function sends the corresponding make or break code to the host.
- */
-void button_state_changed(enum keyboard_button_type button, int is_pressed);
-
-/**
- * Notify the keyboard module when a byte is written by the host.
- *
- * Note: This is called in interrupt context by the LPC interrupt handler.
- *
- * @param data		Byte written by host
- * @param is_cmd        Is byte command (!=0) or data (0)
- */
-void keyboard_host_write(int data, int is_cmd);
-
-/*
- * Board specific callback function when a key state is changed.
- *
- * A board may watch key events and create some easter eggs, or apply dynamic
- * translation to the make code (i.e., remap keys).
- *
- * Returning EC_SUCCESS implies *make_code is still a valid make code to be
- * processed. Any other return value will abort processing of this make code.
- * If callback alters *make_code or aborts key processing when pressed=1, it is
- * responsible for also altering/aborting the matching pressed=0 call.
- *
- * @param make_code	Pointer to scan code (set 2) of key in action.
- * @param pressed	Is the key being pressed (1) or released (0).
- */
-enum ec_error_list keyboard_scancode_callback(uint16_t *make_code,
-					      int8_t pressed);
-
-/**
- * Send aux data to host from interrupt context.
- *
- * @param data	Aux response to send to host.
- */
-void send_aux_data_to_host_interrupt(uint8_t data);
-
-/**
- * Send aux data to device.
- *
- * @param data	Aux data to send to device.
- */
-void send_aux_data_to_device(uint8_t data);
-
-#endif  /* __CROS_EC_KEYBOARD_8042_H */
diff --git a/include/keyboard_8042_sharedlib.h b/include/keyboard_8042_sharedlib.h
deleted file mode 100644
index 6c2e37fbf4..0000000000
--- a/include/keyboard_8042_sharedlib.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * The functions implemented by keyboard component of EC core.
- */
-
-#ifndef __CROS_EC_KEYBOARD_8042_SHAREDLIB_H
-#define __CROS_EC_KEYBOARD_8042_SHAREDLIB_H
-
-#include "button.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-
-struct button_8042_t {
-	uint16_t scancode;
-	int repeat;
-};
-
-/**
- * Get the standard Chrome OS keyboard matrix set 2 scanset
- * @param row	Row number
- * @param col	Column number
- * @return	0 on error, scanset for the (row,col) if successful
- **/
-uint16_t get_scancode_set2(uint8_t row, uint8_t col);
-/**
- * Set the standard Chrome OS keyboard matrix set 2 scanset
- * @param row	Row number
- * @param col	Column number
- * @param val	Value to set
- **/
-void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val);
-
-/* Translation from scan code set 2 to set 1. */
-extern const uint8_t scancode_translate_table[];
-extern uint8_t scancode_translate_set2_to_1(uint8_t code);
-
-#ifdef CONFIG_KEYBOARD_DEBUG
-#define KEYCAP_LONG_LABEL_BIT   (0x80)
-#define KEYCAP_LONG_LABEL_INDEX_BITMASK		(~KEYCAP_LONG_LABEL_BIT)
-
-enum keycap_long_label_idx {
-	KLLI_UNKNO = 0x80,		/* UNKNOWN */
-	KLLI_F1    = 0x81,		/* F1 or PREVIOUS */
-	KLLI_F2    = 0x82,		/* F2 or NEXT */
-	KLLI_F3    = 0x83,		/* F3 or REFRESH */
-	KLLI_F4    = 0x84,		/* F4 or FULL_SCREEN */
-	KLLI_F5    = 0x85,		/* F5 or OVERVIEW */
-	KLLI_F6    = 0x86,		/* F6 or DIM */
-	KLLI_F7    = 0x87,		/* F7 or BRIGHT */
-	KLLI_F8    = 0x88,		/* F8 or MUTE */
-	KLLI_F9    = 0x89,		/* F9 or VOLUME DOWN */
-	KLLI_F10   = 0x8A,		/* F10 or VOLUME UP */
-	KLLI_F11   = 0x8B,		/* F11 or POWER */
-	KLLI_F12   = 0x8C,		/* F12 or DEV TOOLS */
-	KLLI_F13   = 0x8D,		/* F13 or GOOGLE ASSISTANT */
-	KLLI_F14   = 0x8E,		/* F14 */
-	KLLI_F15   = 0x8F,		/* F15 */
-	KLLI_L_ALT = 0x90,		/* LEFT ALT */
-	KLLI_R_ALT = 0x91,		/* RIGHT ALT */
-	KLLI_L_CTR = 0x92,		/* LEFT CONTROL */
-	KLLI_R_CTR = 0x93,		/* RIGHT CONTROL */
-	KLLI_L_SHT = 0x94,		/* LEFT SHIFT */
-	KLLI_R_SHT = 0x95,		/* RIGHT SHIFT */
-	KLLI_ENTER = 0x96,		/* ENTER */
-	KLLI_SPACE = 0x97,		/* SPACE */
-	KLLI_B_SPC = 0x98,		/* BACk SPACE*/
-	KLLI_TAB   = 0x99,		/* TAB */
-	KLLI_SEARC = 0x9A,		/* SEARCH */
-	KLLI_LEFT  = 0x9B,		/* LEFT ARROW */
-	KLLI_RIGHT = 0x9C,		/* RIGHT ARROW */
-	KLLI_DOWN  = 0x9D,		/* DOWN ARROW */
-	KLLI_UP    = 0x9E,		/* UP ARROW */
-	KLLI_ESC   = 0x9F,		/* ESCAPE */
-	KLLI_MAX
-};
-
-/**
- * Get the keycap "long version" label
- * @param idx	Index into keycap_long_label_idx[]
- * @return	"UNKNOWN" on error, long label for idx if successful
- */
-const char *get_keycap_long_label(uint8_t idx);
-
-/**
- * Get the keycap label
- * @param row	Row number
- * @param col	Column number
- * @return	KLLI_UNKNO on error, label for the (row,col) if successful
- */
-char get_keycap_label(uint8_t row, uint8_t col);
-/**
- * Set the keycap label
- * @param row	Row number
- * @param col	Column number
- * @param val	Value to set
- */
-void set_keycap_label(uint8_t row, uint8_t col, char val);
-#endif
-
-/* Button scancodes (Power, Volume Down, Volume Up, etc.) */
-extern const struct button_8042_t buttons_8042[KEYBOARD_BUTTON_COUNT];
-
-/* Scan code set 2 table. */
-enum scancode_values {
-	SCANCODE_1 = 0x0016,
-	SCANCODE_2 = 0x001e,
-	SCANCODE_3 = 0x0026,
-	SCANCODE_4 = 0x0025,
-	SCANCODE_5 = 0x002e,
-	SCANCODE_6 = 0x0036,
-	SCANCODE_7 = 0x003d,
-	SCANCODE_8 = 0x003e,
-
-	SCANCODE_A = 0x001c,
-	SCANCODE_B = 0x0032,
-	SCANCODE_T = 0x002c,
-
-	SCANCODE_F1 = 0x0005,	/* Translates to 3b in codeset 1 */
-	SCANCODE_F2 = 0x0006,	/* Translates to 3c in codeset 1 */
-	SCANCODE_F3 = 0x0004,	/* Translates to 3d in codeset 1 */
-	SCANCODE_F4 = 0x000c,	/* Translates to 3e in codeset 1 */
-	SCANCODE_F5 = 0x0003,	/* Translates to 3f in codeset 1 */
-	SCANCODE_F6 = 0x000b,	/* Translates to 40 in codeset 1 */
-	SCANCODE_F7 = 0x0083,	/* Translates to 41 in codeset 1 */
-	SCANCODE_F8 = 0x000a,	/* Translates to 42 in codeset 1 */
-	SCANCODE_F9 = 0x0001,	/* Translates to 43 in codeset 1 */
-	SCANCODE_F10 = 0x0009,	/* Translates to 44 in codeset 1 */
-	SCANCODE_F11 = 0x0078,	/* Translates to 57 in codeset 1 */
-	SCANCODE_F12 = 0x0007,	/* Translates to 58 in codeset 1 */
-	SCANCODE_F13 = 0x000f,	/* Translates to 59 in codeset 1 */
-	SCANCODE_F14 = 0x0017,	/* Translates to 5a in codeset 1 */
-	SCANCODE_F15 = 0x001f,	/* Translates to 5b in codeset 1 */
-
-	SCANCODE_BACK =	0xe038,			/* e06a in codeset 1 */
-	SCANCODE_REFRESH = 0xe020,		/* e067 in codeset 1 */
-	SCANCODE_FORWARD = 0xe030,		/* e069 in codeset 1 */
-	SCANCODE_FULLSCREEN = 0xe01d,		/* e011 in codeset 1 */
-	SCANCODE_OVERVIEW = 0xe024,		/* e012 in codeset 1 */
-	SCANCODE_SNAPSHOT = 0xe02d,		/* e013 in codeset 1 */
-	SCANCODE_BRIGHTNESS_DOWN = 0xe02c,	/* e014 in codeset 1 */
-	SCANCODE_BRIGHTNESS_UP = 0xe035,	/* e015 in codeset 1 */
-	SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c,	/* e016 in codeset 1 */
-	SCANCODE_VOLUME_MUTE = 0xe023,		/* e020 in codeset 1 */
-	SCANCODE_VOLUME_DOWN = 0xe021,		/* e02e in codeset 1 */
-	SCANCODE_VOLUME_UP = 0xe032,		/* e030 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_DOWN = 0xe043,	/* e017 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_UP = 0xe044,	/* e018 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c,	/* e01e in codeset 1 */
-	SCANCODE_NEXT_TRACK = 0xe04d,		/* e019 in codeset 1 */
-	SCANCODE_PREV_TRACK = 0xe015,		/* e010 in codeset 1 */
-	SCANCODE_PLAY_PAUSE = 0xe054,		/* e01a in codeset 1 */
-	SCANCODE_MICMUTE = 0xe05b,		/* e01b in codeset 1 */
-
-	SCANCODE_UP = 0xe075,
-	SCANCODE_DOWN = 0xe072,
-	SCANCODE_LEFT = 0xe06b,
-	SCANCODE_RIGHT = 0xe074,
-
-	SCANCODE_LEFT_CTRL = 0x0014,
-	SCANCODE_RIGHT_CTRL = 0xe014,
-	SCANCODE_LEFT_ALT = 0x0011,
-	SCANCODE_RIGHT_ALT = 0xe011,
-
-	SCANCODE_LEFT_WIN = 0xe01f,  /* Also known as GUI or Super key. */
-	SCANCODE_RIGHT_WIN = 0xe027,
-	SCANCODE_MENU = 0xe02f,
-
-	SCANCODE_POWER = 0xe037,
-
-	SCANCODE_NUMLOCK = 0x0077,
-	SCANCODE_CAPSLOCK = 0x0058,
-	SCANCODE_SCROLL_LOCK = 0x007e,
-
-	SCANCODE_CTRL_BREAK = 0xe07e,
-};
-
-#endif /* __CROS_EC_KEYBOARD_8042_SHAREDLIB_H */
diff --git a/include/keyboard_backlight.h b/include/keyboard_backlight.h
deleted file mode 100644
index e0a1f4d30e..0000000000
--- a/include/keyboard_backlight.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_KEYBOARD_BACKLIGHT_H
-#define __CROS_EC_KEYBOARD_BACKLIGHT_H
-
-/**
- * If GPIO_EN_KEYBOARD_BACKLIGHT is defined, this GPIO will be set when
- * the the keyboard backlight is enabled or disabled. This GPIO is used
- * to enable or disable the power to the keyboard backlight circuitry.
- * GPIO_EN_KEYBOARD_BACKLIGHT must be active high.
- */
-
-struct kblight_conf {
-	const struct kblight_drv *drv;
-};
-
-struct kblight_drv {
-	/**
-	 * Initialize the keyboard backlight controller
-	 * @return EC_SUCCESS or EC_ERROR_*
-	 */
-	int (*init)(void);
-
-	/**
-	 * Set the brightness
-	 * @param percent
-	 * @return EC_SUCCESS or EC_ERROR_*
-	 */
-	int (*set)(int percent);
-
-	/**
-	 * Get the current brightness
-	 * @return Brightness in percentage
-	 */
-	int (*get)(void);
-
-	/**
-	 * Enable or disable keyboard backlight
-	 * @param enable: 1=Enable, 0=Disable.
-	 * @return EC_SUCCESS or EC_ERROR_*
-	 */
-	int (*enable)(int enable);
-};
-
-/**
- * Initialize keyboard backlight per board
- */
-void board_kblight_init(void);
-
-/**
- * Set keyboard backlight brightness
- *
- * @param percent Brightness in percentage
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int kblight_set(int percent);
-
-/**
- * Get keyboard backlight brightness
- *
- * @return Brightness in percentage
- */
-int kblight_get(void);
-
-/**
- * Enable or disable keyboard backlight
- *
- * @param enable: 1=Enable, 0=Disable.
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int kblight_enable(int enable);
-
-/**
- * Register keyboard backlight controller
- *
- * @param drv: Driver of keyboard backlight controller
- * @return EC_SUCCESS or EC_ERROR_*
- */
-int kblight_register(const struct kblight_drv *drv);
-
-extern const struct kblight_drv kblight_pwm;
-
-#endif /* __CROS_EC_KEYBOARD_BACKLIGHT_H */
diff --git a/include/keyboard_mkbp.h b/include/keyboard_mkbp.h
deleted file mode 100644
index 3d153d63b5..0000000000
--- a/include/keyboard_mkbp.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * MKBP keyboard protocol
- */
-
-#ifndef __CROS_EC_KEYBOARD_MKBP_H
-#define __CROS_EC_KEYBOARD_MKBP_H
-
-#include "common.h"
-#include "keyboard_config.h"
-
-/**
- * Add keyboard state into FIFO
- *
- * @return EC_SUCCESS if entry added, EC_ERROR_OVERFLOW if FIFO is full
- */
-int mkbp_keyboard_add(const uint8_t *buffp);
-
-/**
- * Send KEY_BATTERY keystroke.
- */
-#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-void keyboard_send_battery_key(void);
-#else
-static inline void keyboard_send_battery_key(void) { }
-#endif
-
-#endif  /* __CROS_EC_KEYBOARD_MKBP_H */
diff --git a/include/keyboard_protocol.h b/include/keyboard_protocol.h
deleted file mode 100644
index 362364ced4..0000000000
--- a/include/keyboard_protocol.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Keyboard protocol interface
- */
-
-#ifndef __CROS_EC_KEYBOARD_PROTOCOL_H
-#define __CROS_EC_KEYBOARD_PROTOCOL_H
-
-#include "common.h"
-#include "button.h"
-
-/* Routines common to all protocols */
-
-/**
- * Clear the keyboard buffer to host.
- */
-void keyboard_clear_buffer(void);
-
-/*
- * Respond to button changes. Implemented by a host-specific
- * handler.
- *
- * @param button	The button that changed.
- * @param is_pressed	Whether the button is now pressed.
- */
-void keyboard_update_button(enum keyboard_button_type button, int is_pressed);
-
-/* Protocol-specific includes */
-
-#ifdef CONFIG_KEYBOARD_PROTOCOL_8042
-#include "keyboard_8042.h"
-#endif
-
-#ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
-#include "keyboard_mkbp.h"
-
-/* MKBP protocol takes the whole keyboard matrix, and does not care about
- * individual key presses.
- */
-static inline void keyboard_state_changed(int row, int col, int is_pressed) {}
-#else
-/**
- * Called by keyboard scan code once any key state change (after de-bounce),
- *
- * This function will look up matrix table and convert scancode host.
- */
-void keyboard_state_changed(int row, int col, int is_pressed);
-#endif
-
-/**
- * Returns true if keyboard backlight is present/detected.
- */
-int board_has_keyboard_backlight(void);
-
-/*
- * This function can help change the keyboard top row layout as presented to the
- * AP. If changing the position of the "Refresh" key from T3, you may also need
- * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on
- * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3)
- */
-__override_proto
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void);
-
-#endif  /* __CROS_EC_KEYBOARD_PROTOCOL_H */
diff --git a/include/keyboard_raw.h b/include/keyboard_raw.h
deleted file mode 100644
index 6c8ecc3b2a..0000000000
--- a/include/keyboard_raw.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw access to keyboard GPIOs.
- *
- * The keyboard matrix is read by driving output signals on the column lines
- * and reading the row lines.
- */
-
-#ifndef __CROS_EC_KEYBOARD_RAW_H
-#define __CROS_EC_KEYBOARD_RAW_H
-
-#include "assert.h"
-#include "common.h"
-#include "gpio.h"
-#include "keyboard_config.h"
-
-/* Column values for keyboard_raw_drive_column() */
-enum keyboard_column_index {
-	KEYBOARD_COLUMN_ALL = -2,  /* Drive all columns */
-	KEYBOARD_COLUMN_NONE = -1, /* Drive no columns (tri-state all) */
-	/* 0 ~ KEYBOARD_COLS_MAX-1 for the corresponding column */
-};
-
-/**
- * Initialize the raw keyboard interface.
- *
- * Must be called before any other functions in this interface.
- */
-void keyboard_raw_init(void);
-
-/**
- * Finish intitialization after task scheduling has started.
- *
- * Call from the keyboard scan task.
- */
-void keyboard_raw_task_start(void);
-
-/**
- * Drive the specified column low.
- *
- * Other columns are tristated.  See enum keyboard_column_index for special
- * values for <col>.
- */
-void keyboard_raw_drive_column(int col);
-
-/**
- * Read raw row state.
- *
- * Bits are 1 if signal is present, 0 if not present.
- */
-int keyboard_raw_read_rows(void);
-
-/**
- * Enable or disable keyboard interrupts.
- *
- * Enabling interrupts will clear any pending interrupt bits.  To avoid missing
- * any interrupts that occur between the end of scanning and then, you should
- * call keyboard_raw_read_rows() after this.  If it returns non-zero, disable
- * interrupts and go back to polling mode instead of waiting for an interrupt.
- */
-void keyboard_raw_enable_interrupt(int enable);
-
-#ifdef HAS_TASK_KEYSCAN
-
-/**
- * GPIO interrupt for raw keyboard input
- */
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal);
-
-#else
-static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) { }
-#endif /* !HAS_TASK_KEYSCAN */
-
-/**
- * Run keyboard factory test scanning.
- *
- * @return non-zero if keyboard pins are shorted.
- */
-int keyboard_factory_test_scan(void);
-
-/**
- * Return true if the current value of the given input GPIO port is zero
- *
- * @param port: GPIO port/bank number
- * @param id:   GPIO index in <port>
- * @return true:input is zero, false:otherwise
- */
-int keyboard_raw_is_input_low(int port, int id);
-
-static inline int keyboard_raw_get_cols(void) {
-	return keyboard_cols;
-}
-
-static inline void keyboard_raw_set_cols(int cols) {
-#ifdef CONFIG_KEYBOARD_LANGUAGE_ID
-	/* Keyboard ID is probably encoded right after the last column. Scanner
-	 * would read keyboard ID if the column size is decreased. */
-	assert(cols == KEYBOARD_COLS_MAX);
-#else
-	/* We can only decrease the column size. You have to assume a larger
-	 * grid (and reduce scanning size if the keyboard has no keypad). */
-	assert(cols <= KEYBOARD_COLS_MAX);
-#endif
-	keyboard_cols = cols;
-}
-
-#ifdef CONFIG_KEYBOARD_CUSTOMIZATION
-/* The board implements this function to control the of the keyboard column.
- * For example, use the gpio to drive 0 or 1 for the refresh key column.
- * @param col: If the value is greater than or equal to 0, the function drive
- *             the specific column.
- *             If the value is KEYBOARD_COLUMN_NONE, drive nothing.
- *             If the value is KEYBOARD_COLUMN_ALL, drive all columns.
- *             Otherwise, do nothing.
- */
-void board_keyboard_drive_col(int col);
-#endif
-
-#endif  /* __CROS_EC_KEYBOARD_RAW_H */
diff --git a/include/keyboard_test.h b/include/keyboard_test.h
deleted file mode 100644
index 142cff5e53..0000000000
--- a/include/keyboard_test.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Keyboard scanner test module for Chrome EC */
-
-#ifndef __CROS_EC_KEYBOARD_TEST_H
-#define __CROS_EC_KEYBOARD_TEST_H
-
-#include <timer.h>
-
-/*
- * Keyboard scan test item - contains a single scan to 'present' to key scan
- * logic.
- */
-struct keyscan_item {
-	timestamp_t abs_time;	/* absolute timestamp to present this item */
-	uint32_t time_us;	/* time for this item relative to test start */
-	uint8_t done;		/* 1 if we managed to present this */
-	uint8_t scan[KEYBOARD_COLS_MAX];
-};
-
-/**
- * Get the next key scan from the test sequence, if any
- *
- * @param column	Column to read (-1 to OR all columns together
- * @param scan		Raw scan data read from GPIOs
- * @return test scan, or just 'scan' if no test is active
- */
-uint8_t keyscan_seq_get_scan(int column, uint8_t scan);
-
-/**
- * Calculate the delay until the next key scan event needs to be presented
- *
- * @return number of microseconds from now until the next key scan event, or
- *	-1 if there is no future key scan event (e.g. testing is complete)
- */
-int keyscan_seq_next_event_delay(void);
-
-#endif
diff --git a/include/lb_common.h b/include/lb_common.h
deleted file mode 100644
index 327c810cad..0000000000
--- a/include/lb_common.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Lightbar IC interface */
-
-#ifndef __CROS_EC_LB_COMMON_H
-#define __CROS_EC_LB_COMMON_H
-
-#include "ec_commands.h"
-
-/* How many (logical) LEDs do we have? */
-#define NUM_LEDS 4
-
-/* Set the color of one LED (or all if the LED number is too large) */
-void lb_set_rgb(unsigned int led, int red, int green, int blue);
-/* Get the current color of one LED. Fails if the LED number is too large. */
-int lb_get_rgb(unsigned int led, uint8_t *red, uint8_t *green, uint8_t *blue);
-/* Set the overall brightness level. */
-void lb_set_brightness(unsigned int newval);
-/* Get the overall brighness level. */
-uint8_t lb_get_brightness(void);
-/* Initialize the IC controller registers to reasonable values. */
-void lb_init(int use_lock);
-/* Disable the LED current off (the IC stays on). */
-void lb_off(void);
-/* Enable the LED current. */
-void lb_on(void);
-/* Fill in the response fields for the LIGHTBAR_CMD_DUMP command. */
-void lb_hc_cmd_dump(struct ec_response_lightbar *out);
-/* Write the IC controller register given by the LIGHTBAR_CMD_REG command. */
-void lb_hc_cmd_reg(const struct ec_params_lightbar *in);
-/*
- * Optional (see config.h). Request that the lightbar power rails be on or off.
- * Returns true if a change to the rails was made, false if it wasn't.
- */
-int lb_power(int enabled);
-
-#endif  /* __CROS_EC_LB_COMMON_H */
diff --git a/include/led_common.h b/include/led_common.h
deleted file mode 100644
index a66455b008..0000000000
--- a/include/led_common.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for blinking LEDs.
- */
-
-#ifndef __CROS_EC_LED_COMMON_H
-#define __CROS_EC_LED_COMMON_H
-
-#include "ec_commands.h"
-
-/* Defined in led_<board>.c */
-extern const enum ec_led_id supported_led_ids[];
-
-/* Defined in led_<board>.c */
-extern const int supported_led_ids_count;
-
-/**
- * Enable or disable automatic control of an LED.
- *
- * @param led_id	ID of LED to enable or disable automatic control.
- * @param enable	1 to enable . 0 to disable
- *
- */
-void led_auto_control(enum ec_led_id led_id, int enable);
-
-/**
- * Whether an LED is under automatic control.
- *
- * @param led_id	ID of LED to query.
- *
- * @returns		1 if LED is under automatic control. 0 if it is not.
- *
- */
-int led_auto_control_is_enabled(enum ec_led_id led_id);
-
-/**
- * Query brightness per color channel for an LED.
- *
- * @param led_id		ID of LED to query.
- * @param brightness_range	Points to EC_LED_COLOR_COUNT element array
- *				where current brightness will be stored.
- *	Value per color channel:
- *		0 unsupported,
- *		1 on/off control,
- *		2 -> 255 max brightness under PWM control.
- *
- */
-void led_get_brightness_range(enum ec_led_id, uint8_t *brightness_range);
-
-/**
- * Set brightness per color channel for an LED.
- *
- * @param led_id	ID of LED to set.
- * @param brightness	Brightness per color channel to set.
- *
- * @returns		EC_SUCCESS or EC_ERROR_INVAL
- *
- */
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness);
-
-/**
- * Enable LED.
- *
- * @param enable	1 to enable LED. 0 to disable.
- *
- */
-void led_enable(int enable);
-
-enum ec_led_state {
-	LED_STATE_OFF   = 0,
-	LED_STATE_ON    = 1,
-	LED_STATE_RESET = 2,
-};
-
-/**
- * Control state of LED.
- *
- * @param led_id	ID of LED to control
- * @param state	0=off, 1=on, 2=reset to default
- *
- */
-void led_control(enum ec_led_id id, enum ec_led_state state);
-
-#endif /* __CROS_EC_LED_COMMON_H */
diff --git a/include/led_onoff_states.h b/include/led_onoff_states.h
deleted file mode 100644
index 63955e590a..0000000000
--- a/include/led_onoff_states.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common functions for stateful LEDs (charger and power)
- */
-
-#ifndef __CROS_EC_ONOFFSTATES_LED_H
-#define __CROS_EC_ONOFFSTATES_LED_H
-
-#include "ec_commands.h"
-
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
-
-/*
- * All LED states should have one phase defined,
- * and an additional phase can be defined for blinking
- */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
-
-/*
- * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
- * STATE_CHARGING_LVL_2 is when led_charge_level_1 <=
- * charge_percentage < led_charge_level_2.
- * STATE_CHARGING_FULL_CHARGE is when
- * led_charge_level_2 <= charge_percentage < 100.
- *
- * STATE_CHARGING_FULL_S5 is optional and state machine will fall back to
- *	FULL_CHARGE if not defined
- */
-enum led_states {
-	STATE_CHARGING_LVL_1,
-	STATE_CHARGING_LVL_2,
-	STATE_CHARGING_FULL_CHARGE,
-	STATE_CHARGING_FULL_S5,
-	STATE_DISCHARGE_S0,
-	STATE_DISCHARGE_S0_BAT_LOW,
-	STATE_DISCHARGE_S3,
-	STATE_DISCHARGE_S5,
-	STATE_BATTERY_ERROR,
-	STATE_FACTORY_TEST,
-	LED_NUM_STATES
-};
-
-struct led_descriptor {
-	enum ec_led_colors color;
-	uint8_t time;
-};
-
-extern const int led_charge_lvl_1;
-extern const int led_charge_lvl_2;
-
-enum pwr_led_states {
-	PWR_LED_STATE_ON,
-	PWR_LED_STATE_SUSPEND_AC,
-	PWR_LED_STATE_SUSPEND_NO_AC,
-	PWR_LED_STATE_OFF,
-	PWR_LED_STATE_OFF_LOW_POWER, /* Falls back to OFF if not defined */
-	PWR_LED_NUM_STATES
-};
-
-/**
- * Set battery LED color - defined in board's led.c if supported, along with:
- *	- led_bat_state_table
- *	- led_charge_lvl_1
- *	- led_charge_lvl_2
- *
- * @param color		Color to set on battery LED
- *
- */
-__override_proto void led_set_color_battery(enum ec_led_colors color);
-
-/**
- * Set power LED color - defined in board's led.c if supported, along with:
- *	- led_pwr_state_table
- */
-__override_proto void led_set_color_power(enum ec_led_colors color);
-
-__override_proto enum led_states
-board_get_led_state(enum led_states desired_state);
-
-#endif /* __CROS_EC_ONOFFSTATES_LED_H */
diff --git a/include/led_pwm.h b/include/led_pwm.h
deleted file mode 100644
index 0f8b270d19..0000000000
--- a/include/led_pwm.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_LED_PWM_H
-#define __CROS_EC_LED_PWM_H
-
-#include "ec_commands.h"
-
-#ifdef CONFIG_ZEPHYR
-#include "pwm/pwm.h"
-#endif
-
-#define PWM_LED_NO_CHANNEL -1
-
-struct pwm_led {
-	enum pwm_channel ch0;
-	enum pwm_channel ch1;
-	enum pwm_channel ch2;
-
-	void (*enable)(enum pwm_channel ch, int enabled);
-	void (*set_duty)(enum pwm_channel ch, int percent);
-};
-
-struct pwm_led_color_map {
-	uint8_t ch0;
-	uint8_t ch1;
-	uint8_t ch2;
-};
-
-enum pwm_led_id {
-	PWM_LED0 = 0,
-#if CONFIG_LED_PWM_COUNT >= 2
-	PWM_LED1,
-#endif /* CONFIG_LED_PWM_COUNT > 2 */
-};
-
-/*
- * A mapping of color to LED duty cycles per channel.
- *
- * This should be defined by the boards to declare what each color looks like.
- * There should be an entry for every enum ec_led_colors value.  For colors that
- * are impossible for a given board, they should define a duty cycle of 0 for
- * all applicable channels.  (e.g. A bi-color LED which has a red and green
- * channel should define all 0s for EC_LED_COLOR_BLUE and EC_LED_COLOR_WHITE.)
- */
-extern struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT];
-
-/*
- * A map of the PWM channels to logical PWM LEDs.
- *
- * A logical PWM LED would be considered as "per diffuser".  There may be 1-3
- * channels per diffuser and they should form a single entry in pwm_leds.  If a
- * channel is not used, simply define that channel as PWM_LED_NO_CHANNEL.
- */
-extern struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT];
-
-void set_pwm_led_color(enum pwm_led_id id, int color);
-
-#endif /* defined(__CROS_EC_LED_PWM_H) */
diff --git a/include/libsharedobjs.h b/include/libsharedobjs.h
deleted file mode 100644
index 3801ccaca0..0000000000
--- a/include/libsharedobjs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Helper macros for shared objects library.
- */
-#ifndef __CROS_EC_LIBSHAREDOBJS_H
-#define __CROS_EC_LIBSHAREDOBJS_H
-
-#include "common.h"
-
-#ifdef CONFIG_SHAREDLIB
-/*
- * The shared library currently only works with those platforms in which both
- * the RO and RW images are loaded simultaneously in some executable memory.
- *
- * NOTE: I know that this doesn't cover all possible cases, but it will catch
- *       an obvious case.
- */
-#if (CONFIG_RO_MEM_OFF ==  CONFIG_RW_MEM_OFF)
-#error "The shared library is NOT compatible with this EC."
-#endif
-
-/*
- * All of the objects in the shared library will be placed into the '.roshared'
- * section.  The SHAREDLIB() macro simply adds this attribute and prevents the
- * RW image from compiling them in.
- */
-#undef SHAREDLIB
-#ifdef SHAREDLIB_IMAGE
-#define SHAREDLIB(...) __attribute__ ((section(".roshared"))) __VA_ARGS__
-#else /* !defined(SHAREDLIB_IMAGE) */
-#define SHAREDLIB(...)
-#endif /* defined(SHAREDLIB_IMAGE) */
-#define SHAREDLIB_FUNC(...) \
-	extern __VA_ARGS__ __attribute__ ((section(".roshared.text")))
-
-#else /* !defined(CONFIG_SHAREDLIB) */
-
-/* By default, the SHAREDLIB() macro maps to its contents. */
-#define SHAREDLIB(...) __VA_ARGS__
-#define SHAREDLIB_FUNC(...) __VA_ARGS__
-#endif /* defined(CONFIG_SHAREDLIB) */
-#endif /* __CROS_EC_LIBSHAREDOBJS_H */
diff --git a/include/lightbar_opcode_list.h b/include/lightbar_opcode_list.h
deleted file mode 100644
index 5d75feb459..0000000000
--- a/include/lightbar_opcode_list.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * This defines a list of lightbar opcodes for programmable sequences.
- */
-
-/* 	   NAME			OPERAND BYTES	MNEMONIC*/
-#define LIGHTBAR_OPCODE_TABLE					\
-	OP(ON,			0,		"on"		)\
-	OP(OFF,			0,		"off"		)\
-	OP(JUMP,		1,		"jump"		)\
-	OP(JUMP_BATTERY,	2,		"jbat"		)\
-	OP(JUMP_IF_CHARGING,	1,		"jcharge"	)\
-	OP(SET_WAIT_DELAY,	4,		"delay.w"	)\
-	OP(SET_RAMP_DELAY,	4,		"delay.r"	)\
-	OP(WAIT,		0,		"wait"		)\
-	OP(SET_BRIGHTNESS,	1,		"bright"	)\
-	OP(SET_COLOR_SINGLE,	2,		"set.1"		)\
-	OP(SET_COLOR_RGB,	4,		"set.rgb"	)\
-	OP(GET_COLORS,		0,		"get"		)\
-	OP(SWAP_COLORS,		0,		"swap"		)\
-	OP(RAMP_ONCE,		0,		"ramp.1"	)\
-	OP(CYCLE_ONCE,		0,		"cycle.1"	)\
-	OP(CYCLE,		0,		"cycle"		)\
-	OP(HALT,		0,		"halt"		)
diff --git a/include/memory_commands.h b/include/memory_commands.h
deleted file mode 100644
index 91020d8920..0000000000
--- a/include/memory_commands.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Memory commands for Chrome EC */
-
-#ifndef __CROS_EC_MEMORY_COMMANDS_H
-#define __CROS_EC_MEMORY_COMMANDS_H
-
-#include "common.h"
-
-/* Initializes the module. */
-int memory_commands_init(void);
-
-#endif  /* __CROS_EC_MEMORY_COMMANDS_H */
diff --git a/include/mkbp_fifo.h b/include/mkbp_fifo.h
deleted file mode 100644
index 347f94e2a7..0000000000
--- a/include/mkbp_fifo.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* FIFO buffer of MKBP events for Chrome EC */
-
-#ifndef __CROS_EC_MKBP_FIFO_H
-#define __CROS_EC_MKBP_FIFO_H
-
-#include "common.h"
-#include "ec_commands.h"
-
-
-#define FIFO_DEPTH 16
-
-
-/**
- * Update the "soft" FIFO depth (size). The new depth should be less or
- * equal FIFO_DEPTH
- *
- * @param new_max_depth		New FIFO depth.
- */
-void mkbp_fifo_depth_update(uint8_t new_max_depth);
-
-/**
- * Clear all keyboard events from the MKBP common FIFO
- */
-void mkbp_fifo_clear_keyboard(void);
-
-/**
- * Clear the entire MKBP common FIFO.
- */
-void mkbp_clear_fifo(void);
-
-/**
- * Add an element to the common MKBP FIFO.
- *
- * @param event_type	The MKBP event type.
- * @param buffp		Pointer to the event data to enqueue.
- * @return EC_SUCCESS if entry added, EC_ERROR_OVERFLOW if FIFO is full.
- */
-test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp);
-
-/**
- * Remove an element from the common MKBP FIFO.
- *
- * @param out		Pointer to the event data to dequeue.
- * @param event_type	The MKBP event type.
- * @return size of the returned event, EC_ERROR_BUSY if type mismatch.
- */
-int mkbp_fifo_get_next_event(uint8_t *out, enum ec_mkbp_event evt);
-
-#endif /* __CROS_EC_MKBP_FIFO_H */
diff --git a/include/mkbp_input_devices.h b/include/mkbp_input_devices.h
deleted file mode 100644
index 2557aab3f2..0000000000
--- a/include/mkbp_input_devices.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Input devices using Matrix Keyboard Protocol [MKBP] events for Chrome EC */
-
-#ifndef __CROS_EC_MKBP_INPUT_DEVICES_H
-#define __CROS_EC_MKBP_INPUT_DEVICES_H
-
-#include "common.h"
-#include "ec_commands.h"
-
-/**
- * Update the state of the switches.
- *
- * @param sw		The switch that changed.
- * @param state		The state of the switch.
- */
-void mkbp_update_switches(uint32_t sw, int state);
-
-/**
- * Update the state of buttons
- *
- * @param button	The button that changed.
- * @param is_pressed	Whether the button is now pressed.
- */
-void mkbp_button_update(enum keyboard_button_type button, int is_pressed);
-
-/**
- * Retrieve state of buttons [Power, Volume up/down, etc]
- */
-uint32_t mkbp_get_button_state(void);
-
-/**
- * Retrieve state of switches [Lid open/closed, tablet mode switch, etc]
- */
-uint32_t mkbp_get_switch_state(void);
-
-#endif /* __CROS_EC_MKBP_INPUT_DEVICES_H */
diff --git a/include/mock/charge_manager_mock.h b/include/mock/charge_manager_mock.h
deleted file mode 100644
index 8a791f6121..0000000000
--- a/include/mock/charge_manager_mock.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Controls for the mock charge_manager
- */
-
-#ifndef __MOCK_CHARGE_MANAGER_MOCK_H
-#define __MOCK_CHARGE_MANAGER_MOCK_H
-
-struct mock_ctrl_charge_manager {
-	int vbus_voltage_mv;
-};
-
-#define MOCK_CTRL_DEFAULT_CHARGE_MANAGER    \
-	((struct mock_ctrl_charge_manager) { \
-		.vbus_voltage_mv = 0,       \
-	})
-
-extern struct mock_ctrl_charge_manager mock_ctrl_charge_manager;
-
-void mock_charge_manager_set_vbus_voltage(int voltage_mv);
-
-#endif /* __MOCK_CHARGE_MANAGER_MOCK_H */
diff --git a/include/mock/dp_alt_mode_mock.h b/include/mock/dp_alt_mode_mock.h
deleted file mode 100644
index 27811140c7..0000000000
--- a/include/mock/dp_alt_mode_mock.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock for DisplayPort alternate mode support */
-
-#ifndef __MOCK_DP_ALT_MODE_MOCK_H
-#define __MOCK_DP_ALT_MODE_MOCK_H
-
-#include "common.h"
-
-void mock_dp_alt_mode_reset(void);
-
-#endif /* __MOCK_DP_ALT_MODE_MOCK_H */
diff --git a/include/mock/fp_sensor_mock.h b/include/mock/fp_sensor_mock.h
deleted file mode 100644
index 432802348c..0000000000
--- a/include/mock/fp_sensor_mock.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Controls for the mock fpsensor private driver
- */
-
-#ifndef __MOCK_FP_SENSOR_MOCK_H
-#define __MOCK_FP_SENSOR_MOCK_H
-
-#include "common.h"
-#include "fpsensor.h"
-
-struct mock_ctrl_fp_sensor {
-	int fp_sensor_init_return;
-	int fp_sensor_deinit_return;
-	int fp_sensor_get_info_return;
-	enum finger_state fp_sensor_finger_status_return;
-	int fp_sensor_acquire_image_return;
-	int fp_sensor_acquire_image_with_mode_return;
-	int fp_finger_match_return;
-	int fp_enrollment_begin_return;
-	int fp_enrollment_finish_return;
-	int fp_finger_enroll_return;
-	int fp_maintenance_return;
-};
-
-#define MOCK_CTRL_DEFAULT_FP_SENSOR                                    \
-(struct mock_ctrl_fp_sensor) {                                         \
-	.fp_sensor_init_return                       = EC_SUCCESS,     \
-	.fp_sensor_deinit_return                     = EC_SUCCESS,     \
-	.fp_sensor_get_info_return                   = EC_SUCCESS,     \
-	.fp_sensor_finger_status_return              = FINGER_NONE,    \
-	.fp_sensor_acquire_image_return              = 0,              \
-	.fp_sensor_acquire_image_with_mode_return    = 0,              \
-	.fp_finger_match_return    = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \
-	.fp_enrollment_begin_return                  = 0,              \
-	.fp_enrollment_finish_return                 = 0,              \
-	.fp_finger_enroll_return   = EC_MKBP_FP_ERR_ENROLL_OK,         \
-	.fp_maintenance_return			     = EC_SUCCESS      \
-}
-
-extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor;
-
-#endif /* __MOCK_FP_SENSOR_MOCK_H */
diff --git a/include/mock/fpsensor_detect_mock.h b/include/mock/fpsensor_detect_mock.h
deleted file mode 100644
index da23dded96..0000000000
--- a/include/mock/fpsensor_detect_mock.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __MOCK_FPSENSOR_DETECT_MOCK_H
-#define __MOCK_FPSENSOR_DETECT_MOCK_H
-
-#include "fpsensor_detect.h"
-
-struct mock_ctrl_fpsensor_detect {
-	enum fp_sensor_type get_fp_sensor_type_return;
-	enum fp_transport_type get_fp_transport_type_return;
-	enum fp_sensor_spi_select get_fp_sensor_spi_select_return;
-};
-
-#define MOCK_CTRL_DEFAULT_FPSENSOR_DETECT                                  \
-	{                                                                  \
-		.get_fp_sensor_type_return = FP_SENSOR_TYPE_UNKNOWN,       \
-		.get_fp_transport_type_return = FP_TRANSPORT_TYPE_UNKNOWN, \
-		.get_fp_sensor_spi_select_return =                         \
-			FP_SENSOR_SPI_SELECT_UNKNOWN                       \
-	}
-
-extern struct mock_ctrl_fpsensor_detect mock_ctrl_fpsensor_detect;
-
-#endif /* __MOCK_FPSENSOR_DETECT_MOCK_H */
diff --git a/include/mock/fpsensor_state_mock.h b/include/mock/fpsensor_state_mock.h
deleted file mode 100644
index eafe01851c..0000000000
--- a/include/mock/fpsensor_state_mock.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __MOCK_FPSENSOR_STATE_MOCK_H
-#define __MOCK_FPSENSOR_STATE_MOCK_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "ec_commands.h"
-
-extern const uint8_t default_fake_tpm_seed[FP_CONTEXT_TPM_BYTES];
-
-int fpsensor_state_mock_set_tpm_seed(
-	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES]);
-
-#endif  /* __MOCK_FPSENSOR_STATE_MOCK_H */
diff --git a/include/mock/mkbp_events_mock.h b/include/mock/mkbp_events_mock.h
deleted file mode 100644
index 3d686e3618..0000000000
--- a/include/mock/mkbp_events_mock.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Controls for the mock MKBP keyboard protocol
- */
-
-#ifndef __MOCK_MKBP_EVENTS_MOCK_H
-#define __MOCK_MKBP_EVENTS_MOCK_H
-
-struct mock_ctrl_mkbp_events {
-	int mkbp_send_event_return;
-};
-
-#define MOCK_CTRL_DEFAULT_MKBP_EVENTS          \
-(struct mock_ctrl_mkbp_events) {               \
-	.mkbp_send_event_return = 1,           \
-}
-
-extern struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events;
-
-#endif /* __MOCK_MKBP_EVENTS_MOCK_H */
diff --git a/include/mock/rollback_mock.h b/include/mock/rollback_mock.h
deleted file mode 100644
index 576f87e6b9..0000000000
--- a/include/mock/rollback_mock.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Controls for the mock rollback block library
- */
-
-#ifndef __MOCK_ROLLBACK_MOCK_H
-#define __MOCK_ROLLBACK_MOCK_H
-
-#include <stdbool.h>
-
-struct mock_ctrl_rollback {
-	bool get_secret_fail;
-};
-
-#define MOCK_CTRL_DEFAULT_ROLLBACK             \
-(struct mock_ctrl_rollback) {                  \
-	.get_secret_fail = false,              \
-}
-
-extern struct mock_ctrl_rollback mock_ctrl_rollback;
-
-#endif  /* __MOCK_ROLLBACK_MOCK_H */
diff --git a/include/mock/tcpc_mock.h b/include/mock/tcpc_mock.h
deleted file mode 100644
index 9098fe1ba3..0000000000
--- a/include/mock/tcpc_mock.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
- /* Mock for the TCPC interface */
-
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-
-/* Controller for TCPC state */
-struct mock_tcpc_ctrl {
-	enum tcpc_cc_voltage_status cc1;
-	enum tcpc_cc_voltage_status cc2;
-	int vbus_level;
-	int num_calls_to_set_header;
-	bool should_print_call;
-	uint64_t first_call_to_enable_auto_toggle;
-
-	/* Set to function pointer if callback is needed for test code */
-	struct tcpm_drv callbacks;
-
-	/* Store the latest values that were set on TCPC API */
-	struct {
-		enum pd_power_role power_role;
-		enum pd_data_role data_role;
-		enum tcpc_cc_pull cc;
-		enum tcpc_rp_value rp;
-		enum tcpc_cc_polarity polarity;
-	} last;
-
-};
-
-/* Reset this TCPC mock */
-void mock_tcpc_reset(void);
-
-extern const struct tcpm_drv mock_tcpc_driver;
-extern struct mock_tcpc_ctrl mock_tcpc;
diff --git a/include/mock/tcpci_i2c_mock.h b/include/mock/tcpci_i2c_mock.h
deleted file mode 100644
index 1d4a986ebe..0000000000
--- a/include/mock/tcpci_i2c_mock.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-#define MOCK_TCPCI_I2C_ADDR_FLAGS 0x99
-
-void mock_tcpci_reset(void);
-
-void mock_tcpci_set_reg(int reg, uint16_t value);
-void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask);
-void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask);
-
-uint16_t mock_tcpci_get_reg(int reg_offset);
-
-int verify_tcpci_transmit(enum tcpci_msg_type tx_type,
-			  enum pd_ctrl_msg_type ctrl_msg,
-			  enum pd_data_msg_type data_msg);
-
-int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
-				enum pd_ctrl_msg_type ctrl_msg,
-				enum pd_data_msg_type data_msg,
-				int retry_count);
-
-int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
-			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout);
-
-int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
-			      enum pd_data_msg_type data_msg,
-			      uint8_t *data,
-			      int data_bytes,
-			      int *msg_len,
-			      int timeout);
-
-struct possible_tx {
-	enum tcpci_msg_type tx_type;
-	enum pd_ctrl_msg_type ctrl_msg;
-	enum pd_data_msg_type data_msg;
-};
-
-int verify_tcpci_possible_tx(struct possible_tx possible[],
-			     int possible_cnt,
-			     int *found_index,
-			     uint8_t *data,
-			     int data_bytes,
-			     int *msg_len,
-			     int timeout);
-
-void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
-			uint32_t *payload);
-
-void tcpci_register_dump(void);
diff --git a/include/mock/tcpm_mock.h b/include/mock/tcpm_mock.h
deleted file mode 100644
index 7fd89919f5..0000000000
--- a/include/mock/tcpm_mock.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
- /* Mock for the TCPM interface */
-
-#include "common.h"
-#include "tcpm/tcpm.h"
-
-/* Copied from usb_prl_sm.c, line 99. */
-#define MOCK_CHK_BUF_SIZE 7
-
-/* Define a struct to hold the data we need to control the mocks. */
-struct mock_tcpm_t {
-	uint32_t mock_rx_chk_buf[MOCK_CHK_BUF_SIZE];
-	uint32_t mock_header;
-	int mock_has_pending_message;
-};
-
-extern struct mock_tcpm_t mock_tcpm[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_tcpm_reset(void);
-void mock_tcpm_rx_msg(int port, uint16_t header, int cnt, const uint32_t *data);
diff --git a/include/mock/timer_mock.h b/include/mock/timer_mock.h
deleted file mode 100644
index 04dc01e9ab..0000000000
--- a/include/mock/timer_mock.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __MOCK_TIMER_MOCK_H
-#define __MOCK_TIMER_MOCK_H
-
-#include "timer.h"
-
-void set_time(timestamp_t now_);
-
-timestamp_t get_time(void);
-
-#endif  /* __MOCK_TIMER_MOCK_H */
diff --git a/include/mock/usb_mux_mock.h b/include/mock/usb_mux_mock.h
deleted file mode 100644
index 128286796b..0000000000
--- a/include/mock/usb_mux_mock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock USB Type-C mux */
-
-#include "usb_mux.h"
-
-/* Controller for mux state */
-struct mock_usb_mux_ctrl {
-	mux_state_t state;
-	int num_set_calls;
-};
-
-/* Resets the state of the mock */
-void mock_usb_mux_reset(void);
-
-extern const struct usb_mux_driver mock_usb_mux_driver;
-extern struct mock_usb_mux_ctrl mock_usb_mux;
diff --git a/include/mock/usb_pd_dpm_mock.h b/include/mock/usb_pd_dpm_mock.h
deleted file mode 100644
index c61594fd2b..0000000000
--- a/include/mock/usb_pd_dpm_mock.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock of Device Policy Manager implementation */
-
-#ifndef __MOCK_USB_PD_DPM_MOCK_H
-#define __MOCK_USB_PD_DPM_MOCK_H
-
-#include "common.h"
-#include "usb_pd_dpm.h"
-
-/* Defaults should all be 0 values. */
-struct mock_dpm_port_t {
-	bool mode_entry_done;
-	bool mode_exit_request;
-};
-
-extern struct mock_dpm_port_t dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_dpm_reset(void);
-
-#endif /* __MOCK_USB_PD_DPM_MOCK_H */
diff --git a/include/mock/usb_pe_sm_mock.h b/include/mock/usb_pe_sm_mock.h
deleted file mode 100644
index fcd6e268a0..0000000000
--- a/include/mock/usb_pe_sm_mock.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock USB PE state machine */
-
-#ifndef __MOCK_USB_PE_SM_MOCK_H
-#define __MOCK_USB_PE_SM_MOCK_H
-
-#include "common.h"
-#include "usb_pe_sm.h"
-#include "usb_pd_tcpm.h"
-
-struct mock_pe_port_t {
-	enum tcpci_msg_type sop;
-
-	int mock_pe_message_sent;
-	int mock_pe_error;
-	int mock_pe_hard_reset_sent;
-	int mock_pe_got_hard_reset;
-	int mock_pe_message_received;
-	int mock_got_soft_reset;
-	int mock_pe_message_discarded;
-};
-
-extern struct mock_pe_port_t mock_pe_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_pe_port_reset(void);
-
-#endif /* __MOCK_USB_PE_SM_MOCK_H */
diff --git a/include/mock/usb_prl_mock.h b/include/mock/usb_prl_mock.h
deleted file mode 100644
index ee37d6e6e2..0000000000
--- a/include/mock/usb_prl_mock.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock for USB protocol layer */
-
-#ifndef __MOCK_USB_PRL_MOCK_H
-#define __MOCK_USB_PRL_MOCK_H
-
-#include "common.h"
-#include "usb_emsg.h"
-#include "usb_pd_tcpm.h"
-
-void mock_prl_reset(void);
-
-int mock_prl_wait_for_tx_msg(int port,
-			     enum tcpci_msg_type tx_type,
-			     enum pd_ctrl_msg_type ctrl_msg,
-			     enum pd_data_msg_type data_msg,
-			     int timeout);
-
-enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port);
-
-enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port);
-
-
-void mock_prl_clear_last_sent_msg(int port);
-
-void mock_prl_message_sent(int port);
-
-void mock_prl_message_received(int port);
-
-void mock_prl_report_error(int port, enum pe_error e,
-			   enum tcpci_msg_type tx_type);
-
-#endif /* __MOCK_DP_ALT_MODE_MOCK_H */
diff --git a/include/mock/usb_tc_sm_mock.h b/include/mock/usb_tc_sm_mock.h
deleted file mode 100644
index ca16fb4d98..0000000000
--- a/include/mock/usb_tc_sm_mock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* Mock USB TC state machine*/
-
-#ifndef __MOCK_USB_TC_SM_MOCK_H
-#define __MOCK_USB_TC_SM_MOCK_H
-
-#include "common.h"
-#include "usb_tc_sm.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-struct mock_tc_port_t {
-	int rev;
-	int pd_enable;
-	int msg_tx_id;
-	int msg_rx_id;
-	enum tcpci_msg_type sop;
-	enum tcpc_rp_value lcl_rp;
-	int attached_snk;
-	int attached_src;
-	bool vconn_src;
-	enum pd_data_role data_role;
-	enum pd_power_role power_role;
-};
-
-extern struct mock_tc_port_t mock_tc_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-void mock_tc_port_reset(void);
-
-#endif /* __MOCK_USB_TC_SM_MOCK_H */
diff --git a/include/mock_filter.h b/include/mock_filter.h
deleted file mode 100644
index 113c227a3b..0000000000
--- a/include/mock_filter.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Filter mocklists for makefile relevant items.
- * A mocklist is the .mocklist file in test/ and fuzz/ directories.
- * See common/mock/README.md for more information.
- */
-
-#ifndef __CROS_EC_MOCK_FILTER_H
-#define __CROS_EC_MOCK_FILTER_H
-
-/* If included directly from Makefile, dump mock list. */
-#ifdef _MAKEFILE
-#define MOCK(n) n
-CONFIG_TEST_MOCK_LIST
-#endif
-
-
-#endif /*  __CROS_EC_MOCK_FILTER_H */
diff --git a/include/newton_fit.h b/include/newton_fit.h
deleted file mode 100644
index b4db64c814..0000000000
--- a/include/newton_fit.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Newton's method for sphere fit algorithm */
-
-#ifndef __CROS_EC_NEWTON_FIT_H
-#define __CROS_EC_NEWTON_FIT_H
-
-#include "queue.h"
-#include "vec3.h"
-#include "stdbool.h"
-
-struct newton_fit_orientation {
-	/** An orientations. */
-	fpv3_t orientation;
-
-	/** The number of samples of this orientation. */
-	uint8_t nsamples;
-};
-
-struct newton_fit {
-	/**
-	 * Threshold used to detect when two vectors are identical. Measured in
-	 * units^2.
-	 */
-	fp_t nearness_threshold;
-
-	/**
-	 * The weight to use for a new data point when computing the mean. When
-	 * a new point is considered the same as an existing orientation (via
-	 * the nearness_threshold) it will be averaged with the existing
-	 * orientation using this weight. Valid range is (0,1).
-	 */
-	fp_t new_pt_weight;
-
-	/**
-	 * The threshold used to determine whether or not to continue iterating
-	 * when performing the bias computation.
-	 */
-	fp_t error_threshold;
-
-	/**
-	 * The maximum number of orientations to use, changing this affects the
-	 * memory footprint of the algorithm as 3 floats are needed per
-	 * orientation.
-	 */
-	uint32_t max_orientations;
-
-	/**
-	 * The maximum number of iterations the algorithm is allowed to run.
-	 */
-	uint32_t max_iterations;
-
-	/**
-	 * The minimum number of samples per orientation to consider the
-	 * orientation ready for calculation
-	 */
-	uint8_t min_orientation_samples;
-
-	/**
-	 * Queue of newton_fit_orientation structs.
-	 */
-	struct queue *orientations;
-};
-
-#define NEWTON_FIT(SIZE, NSAMPLES, NEAR_THRES, NEW_PT_WEIGHT, ERROR_THRESHOLD, \
-		   MAX_ITERATIONS)                                             \
-	((struct newton_fit){                                                  \
-		.nearness_threshold = NEAR_THRES,                              \
-		.new_pt_weight = NEW_PT_WEIGHT,                                \
-		.error_threshold = ERROR_THRESHOLD,                            \
-		.max_orientations = SIZE,                                      \
-		.max_iterations = MAX_ITERATIONS,                              \
-		.min_orientation_samples = NSAMPLES,                           \
-		.orientations = (struct queue *)&QUEUE_NULL(                   \
-			SIZE, struct newton_fit_orientation),                  \
-	})
-
-/**
- * Reset the newton_fit struct's state.
- *
- * @param fit Pointer to the struct.
- */
-void newton_fit_reset(struct newton_fit *fit);
-
-/**
- * Add new vector to the struct. The behavior of this depends on the
- * configuration values used when the struct was created. For example:
- * - Samples that are within sqrt(NEAR_THRES) of an existing orientation will
- *   be averaged with the matching orientation entry.
- * - If the new sample isn't near an existing orientation it will only be added
- *   if state->num_orientations < config->num_orientations.
- *
- * @param fit Pointer to the struct.
- * @param x The new samples' X component.
- * @param y The new samples' Y component.
- * @param z The new samples' Z component.
- * @return True if orientations are full and the struct is ready to compute the
- *         bias.
- */
-bool newton_fit_accumulate(struct newton_fit *fit, fp_t x, fp_t y, fp_t z);
-
-/**
- * Compute the center/bias and optionally the radius represented by the current
- * struct.
- *
- * @param fit Pointer to the struct.
- * @param bias Pointer to the output bias (this is also the starting bias for
- *             the algorithm.
- * @param radius Optional pointer to write the computed radius into. If NULL,
- *               the calculation will be skipped.
- */
-void newton_fit_compute(struct newton_fit *fit, fpv3_t bias, fp_t *radius);
-
-#endif /* __CROS_EC_NEWTON_FIT_H */
diff --git a/include/onewire.h b/include/onewire.h
deleted file mode 100644
index 58899360a4..0000000000
--- a/include/onewire.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* 1-wire interface for Chrome EC */
-
-/*
- * Note that 1-wire communication is VERY latency-sensitive.  If these
- * functions are run at low priority, communication may be garbled.  However,
- * these functions are also slow enough (~1ms per call) that it's really not
- * desirable to put them at high priority.  So make sure you check the
- * confirmation code from the peripheral for any communication, and retry a few
- * times in case of failure.
- */
-
-#ifndef __CROS_EC_ONEWIRE_H
-#define __CROS_EC_ONEWIRE_H
-
-#include "common.h"
-
-/**
- * Reset the 1-wire bus.
- *
- * @return EC_SUCCESS, or non-zero if presence detect fails.
- */
-int onewire_reset(void);
-
-/**
- * Read a byte from the 1-wire bus.
- *
- * @return The byte value read.
- */
-int onewire_read(void);
-
-/**
- * Write a byte to the 1-wire bus.
- *
- * @param data		Byte to write
- */
-void onewire_write(int data);
-
-#endif  /* __CROS_EC_ONEWIRE_H */
diff --git a/include/overflow.h b/include/overflow.h
deleted file mode 100644
index 42eab6a094..0000000000
--- a/include/overflow.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_OVERFLOW_H
-#define __CROS_EC_OVERFLOW_H
-
-#include "compiler.h"
-
-/*
- * __builtin_add_overflow, __builtin_sub_overflow and __builtin_mul_overflow
- * were added in gcc 5.1: https://gcc.gnu.org/gcc-5/changes.html
- */
-#if GCC_VERSION > 50100
-#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
-#endif
-
-/*
- * __has_builtin available in
- * clang 10 and newer: https://clang.llvm.org/docs/LanguageExtensions.html
- */
-#ifdef __clang__
-#if __has_builtin(__builtin_add_overflow) &&     \
-	__has_builtin(__builtin_sub_overflow) && \
-	__has_builtin(__builtin_mul_overflow)
-#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
-#endif
-#endif  /* __clang__ */
-
-#include "third_party/linux/overflow.h"
-
-#endif /* __CROS_EC_OVERFLOW_H */
diff --git a/include/peci.h b/include/peci.h
deleted file mode 100644
index 993e7d637d..0000000000
--- a/include/peci.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* PECI module for Chrome EC */
-
-#ifndef __CROS_EC_PECI_H
-#define __CROS_EC_PECI_H
-
-#include "common.h"
-
-#define PECI_TARGET_ADDRESS         0x30
-#define PECI_WRITE_DATA_FIFO_SIZE   15
-#define PECI_READ_DATA_FIFO_SIZE    16
-
-#define PECI_GET_TEMP_READ_LENGTH   2
-#define PECI_GET_TEMP_WRITE_LENGTH  0
-#define PECI_GET_TEMP_TIMEOUT_US    200
-
-/* PECI Command Code */
-enum peci_command_code {
-	PECI_CMD_PING             = 0x00,
-	PECI_CMD_GET_DIB          = 0xF7,
-	PECI_CMD_GET_TEMP         = 0x01,
-	PECI_CMD_RD_PKG_CFG       = 0xA1,
-	PECI_CMD_WR_PKG_CFG       = 0xA5,
-	PECI_CMD_RD_IAMSR         = 0xB1,
-	PECI_CMD_WR_IAMSR         = 0xB5,
-	PECI_CMD_RD_PCI_CFG       = 0x61,
-	PECI_CMD_WR_PCI_CFG       = 0x65,
-	PECI_CMD_RD_PCI_CFG_LOCAL = 0xE1,
-	PECI_CMD_WR_PCI_CFG_LOCAL = 0xE5,
-};
-
-struct peci_data {
-	enum peci_command_code cmd_code; /* command code */
-	uint8_t addr;	/* client address */
-	uint8_t w_len;	/* write length */
-	uint8_t r_len;	/* read length */
-	uint8_t *w_buf;	/* buffer pointer of write data */
-	uint8_t *r_buf;	/* buffer pointer of read data */
-	int timeout_us;	/* transaction timeout unit:us */
-};
-
-/**
- * Get the last polled value of the PECI temp sensor.
- *
- * @param idx		Sensor index to read.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int peci_temp_sensor_get_val(int idx, int *temp_ptr);
-
-/**
- * Start a PECI transaction
- *
- * @param  peci transaction data
- *
- * @return zero if successful, non-zero if error
- */
-int peci_transaction(struct peci_data *peci);
-
-#endif  /* __CROS_EC_PECI_H */
diff --git a/include/peripheral_charger.h b/include/peripheral_charger.h
deleted file mode 100644
index b1f82bb1f3..0000000000
--- a/include/peripheral_charger.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PERIPHERAL_CHARGER_H
-#define __CROS_EC_PERIPHERAL_CHARGER_H
-
-#include "common.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "queue.h"
-#include "stdbool.h"
-#include "task.h"
-
-/*
- * Peripheral charge manager
- *
- * Peripheral charge manager (PCHG) is a state machine (SM), which manages
- * charge ports to charge peripheral devices. Events can be generated
- * externally (by a charger chip) or internally (by a host command or the SM
- * itself). Events are queued and handled first-come-first-serve basis.
- *
- * Peripheral charger drivers should implement struct pchg_drv. Each operation
- * can be synchronous or asynchronous depending on the chip. If a function
- * works synchronously, it should return EC_SUCCESS. That'll make the SM
- * immediately queue the next event (if applicable) and transition to the next
- * state. If a function works asynchronously, it should return
- * EC_SUCCESS_IN_PROGRESS. That'll make the SM stay in the same state. The SM
- * is expected to receive IRQ for further information about the operation,
- * which may or may not make the SM transition to the next state.
- *
- * Roughly speaking the SM looks as follows:
- *
- *                  +---------------+
- *                  |     RESET     |
- *                  +-------+-------+
- *                          |
- *                          | INITIALIZED
- *                          v
- *                  +---------------+
- *                  |  INITIALIZED  |<--------------+
- *                  +------+--------+               |
- *                         | ^                      |
- *                 ENABLED | | DISABLED             |
- *                         v |                      |
- *                  +--------+------+               |
- *   +------------->|    ENABLED    |               |
- *   |              +-----+-+-------+               |
- *   |                    | |                       |
- *   |   DEVICE_CONNECTED | | DEVICE_DOCKED         |
- *   |                    | v                       |
- *   | DEVICE_LOST  +---------------+               |
- *   +--------------+     DOCKED    +---------------+
- *   |              +-------+-------+               |
- *   |                    | |                       |
- *   |                    | | DEVICE_CONNECTED      |
- *   |                    v v                       |
- *   |              +---------------+               |
- *   +--------------+   CONNECTED   +---------------+
- *   | DEVICE_LOST  +------+--------+  ERROR        |
- *   |                     | ^                      |
- *   |      CHARGE_STARTED | | CHARGE_ENDED         |
- *   |                     | | CHARGE_STOPPED       |
- *   |                     v |                      |
- *   |              +--------+------+               |
- *   +--------------+   CHARGING    +---------------+
- *     DEVICE_LOST  +---------------+  ERROR
- *
- *
- * In download (update firmware) mode, the state machine transitions as follows:
- *
- *                  +---------------+
- *                  |   DOWNLOAD    |
- *                  +------+--------+
- *                         | ^
- *             UPDATE_OPEN | |
- *                         | | UPDATE_CLOSE
- *                         v |
- *                  +--------+------+
- *              +-->|  DOWNLOADING  |
- *              |   +------+--------+
- *              |          |
- *              +----------+
- *              UPDATE_WRITE
- */
-
-/* Size of event queue. Use it to initialize struct pchg.events. */
-#define PCHG_EVENT_QUEUE_SIZE	8
-
-enum pchg_event {
-	/* No event */
-	PCHG_EVENT_NONE = 0,
-
-	/* IRQ is pending. */
-	PCHG_EVENT_IRQ,
-
-	/* External Events */
-	PCHG_EVENT_RESET,
-	PCHG_EVENT_INITIALIZED,
-	PCHG_EVENT_ENABLED,
-	PCHG_EVENT_DISABLED,
-	PCHG_EVENT_DEVICE_DETECTED,
-	PCHG_EVENT_DEVICE_CONNECTED,
-	PCHG_EVENT_DEVICE_LOST,
-	PCHG_EVENT_CHARGE_STARTED,
-	PCHG_EVENT_CHARGE_UPDATE,
-	PCHG_EVENT_CHARGE_ENDED,
-	PCHG_EVENT_CHARGE_STOPPED,
-	PCHG_EVENT_UPDATE_OPENED,
-	PCHG_EVENT_UPDATE_CLOSED,
-	PCHG_EVENT_UPDATE_WRITTEN,
-	PCHG_EVENT_IN_NORMAL,
-
-	/* Errors */
-	PCHG_EVENT_CHARGE_ERROR,
-	PCHG_EVENT_UPDATE_ERROR,
-	PCHG_EVENT_OTHER_ERROR,
-
-	/* Internal (a.k.a. Host) Events */
-	PCHG_EVENT_ENABLE,
-	PCHG_EVENT_DISABLE,
-	PCHG_EVENT_UPDATE_OPEN,
-	PCHG_EVENT_UPDATE_WRITE,
-	PCHG_EVENT_UPDATE_CLOSE,
-
-	/* Counter. Add new entry above. */
-	PCHG_EVENT_COUNT,
-};
-
-enum pchg_error {
-	/* Errors reported by host. */
-	PCHG_ERROR_HOST,
-	PCHG_ERROR_OVER_TEMPERATURE,
-	PCHG_ERROR_OVER_CURRENT,
-	PCHG_ERROR_FOREIGN_OBJECT,
-	/* Errors reported by chip. */
-	PCHG_ERROR_FW_VERSION,
-	PCHG_ERROR_INVALID_FW,
-	PCHG_ERROR_WRITE_FLASH,
-	/* All other errors */
-	PCHG_ERROR_OTHER,
-};
-
-#define PCHG_ERROR_MASK(e)	BIT(e)
-
-enum pchg_mode {
-	PCHG_MODE_NORMAL = 0,
-	PCHG_MODE_DOWNLOAD,
-	/* Add no more entries below here. */
-	PCHG_MODE_COUNT,
-};
-
-/**
- * Data struct describing the configuration of a peripheral charging port.
- */
-struct pchg_config {
-	/* Charger driver */
-	const struct pchg_drv *drv;
-	/* I2C port number */
-	const int i2c_port;
-	/* GPIO pin used for IRQ */
-	const enum gpio_signal irq_pin;
-	/* Full battery percentage */
-	const uint8_t full_percent;
-	/* Update block size */
-	const uint32_t block_size;
-};
-
-struct pchg_update {
-	/* Version of new firmware. Usually used by EC_PCHG_UPDATE_CMD_OPEN. */
-	uint32_t version;
-	/* CRC32 of new firmware. Usually used by EC_PCHG_UPDATE_CMD_CLOSE. */
-	uint32_t crc32;
-	/* Address which <data> will be written to. */
-	uint32_t addr;
-	/* Size of <data> */
-	uint32_t size;
-	/* 0: No data. 1: Data is ready for write. */
-	uint8_t data_ready;
-	/* Partial data of new firmware */
-	uint8_t data[128];
-};
-
-/**
- * Data struct describing the status of a peripheral charging port. It provides
- * the state machine and a charger driver with a context to work on.
- */
-struct pchg {
-	/* Static configuration */
-	const struct pchg_config * const cfg;
-	/* Current state of the port */
-	enum pchg_state state;
-	/* Event queue */
-	struct queue const events;
-	/* Event queue mutex */
-	struct mutex mtx;
-	/* 1:Pending IRQ 0:No pending IRQ */
-	uint32_t irq;
-	/* Event currently being handled */
-	enum pchg_event event;
-	/* Error (enum pchg_error). Port is disabled until it's cleared. */
-	uint32_t error;
-	/* Battery percentage (0% ~ 100%) of the connected peripheral device */
-	uint8_t battery_percent;
-	/* Number of dropped events (due to queue overflow) */
-	uint32_t dropped_event_count;
-	/* enum pchg_mode */
-	uint8_t mode;
-	/* FW version */
-	uint32_t fw_version;
-	/* Context related to FW update */
-	struct pchg_update update;
-};
-
-/**
- * Peripheral charger driver
- */
-struct pchg_drv {
-	/* Reset charger chip. */
-	int (*reset)(struct pchg *ctx);
-	/* Initialize the charger. */
-	int (*init)(struct pchg *ctx);
-	/* Enable/disable the charger. */
-	int (*enable)(struct pchg *ctx, bool enable);
-	/* Get event info. */
-	int (*get_event)(struct pchg *ctx);
-	/* Get battery level. */
-	int (*get_soc)(struct pchg *ctx);
-	/* open update session */
-	int (*update_open)(struct pchg *ctx);
-	/* write update image */
-	int (*update_write)(struct pchg *ctx);
-	/* close update session */
-	int (*update_close)(struct pchg *ctx);
-};
-
-/**
- * Array storing configs and states of all the peripheral charging ports.
- * Should be defined in board.c.
- */
-extern struct pchg pchgs[];
-extern const int pchg_count;
-
-/* Utility macro converting port config to port number. */
-#define PCHG_CTX_TO_PORT(ctx)	((ctx) - &pchgs[0])
-
-/**
- * Interrupt handler for a peripheral charger.
- *
- * @param signal
- */
-void pchg_irq(enum gpio_signal signal);
-
-/**
- * Task running a state machine for charging peripheral devices.
- */
-void pchg_task(void *u);
-
-#endif /* __CROS_EC_PERIPHERAL_CHARGER_H */
diff --git a/include/physical_presence.h b/include/physical_presence.h
deleted file mode 100644
index 0acbc65691..0000000000
--- a/include/physical_presence.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Physical presence detection
- */
-#ifndef __CROS_EC_PHYSICAL_PRESENCE_H
-#define __CROS_EC_PHYSICAL_PRESENCE_H
-
-/**
- * Start physical presence detect.
- *
- * If the physical presence sequence is successful, callback() will be called
- * from the hook task context as a deferred function.
- *
- * On failure or abort, callback() will not be called.
- *
- * @param is_long	Use long (!=0) or short (0) sequence)
- * @param callback	Function to call when successful
- * @return EC_SUCCESS, EC_BUSY if detect already in progress, or other
- *	   non-zero error code if error.
- */
-int physical_detect_start(int is_long, void (*callback)(void));
-
-/**
- * Check if a physical detect attempt is in progress
- *
- * @return non-zero if in progress
- */
-int physical_detect_busy(void);
-
-/**
- * Abort a currently-running physical presence detect.
- *
- * Note there is a race condition between stopping detect and a running
- * detect finishing and calling its callback.  The intent of this function
- * is not to prevent that, but instead to avoid an aborted physical detect
- * tying up the button for long periods when we no longer care.
- */
-void physical_detect_abort(void);
-
-/**
- * Handle a physical detect button press.
- *
- * This may be called from interrupt level.
- *
- * Returns EC_SUCCESS if the press was consumed, or EC_ERROR_NOT_HANDLED if
- * physical detect was idle (so the press is for someone else).
- */
-int physical_detect_press(void);
-
-/**
- * Start/stop capturing the button for physical presence.
- *
- * When enabled, a debounced button press+release should call
- * physical_detect_press().
- *
- * This should be implemented by the board.
- *
- * @param enable	Enable (!=0) or disable (==0) capturing button.
- */
-void board_physical_presence_enable(int enable);
-
-/**
- * An API to report physical presence FSM state to an external entity. Of
- * interest are states when key press is currently required or is expected
- * soon.
- */
-enum pp_fsm_state {
-	PP_OTHER = 0,
-	PP_AWAITING_PRESS = 1,
-	PP_BETWEEN_PRESSES = 2,
-};
-enum pp_fsm_state physical_presense_fsm_state(void);
-
-#endif /* __CROS_EC_PHYSICAL_PRESENCE_H */
diff --git a/include/port80.h b/include/port80.h
deleted file mode 100644
index e6212ab593..0000000000
--- a/include/port80.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Port 80 module for Chrome EC */
-
-#ifndef __CROS_EC_PORT80_H
-#define __CROS_EC_PORT80_H
-
-#include "common.h"
-
-enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
-	PORT_80_IGNORE = 0xffff,	/* Invalid POST CODE */
-};
-
-/**
- * Store data from a LPC write to port 80, or a port_80_event code.
- *
- * @param data		Data written to port 80.
- */
-void port_80_write(int data);
-
-/**
- * Chip specific function to read from port 80.
- *
- * @return data from the last LPC write to port 80,
- *	or PORT_80_IGNORE if no data is available.
- */
-int port_80_read(void);
-
-#endif  /* __CROS_EC_PORT80_H */
diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h
deleted file mode 100644
index 62c617bd98..0000000000
--- a/include/power/alderlake_slg4bd44540.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Alder Lake chipset power control module using the SLG4BD44540 power
- * sequencer chip for Chrome EC
- */
-
-#ifndef __CROS_EC_ALDERLAKE_SLG4BD44540_H
-#define __CROS_EC_ALDERLAKE_SLG4BD44540_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-	X86_SLP_S0_DEASSERTED,
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S4_DEASSERTED,
-	X86_SLP_SUS_DEASSERTED,
-	X86_RSMRST_L_PGOOD,
-	X86_DSW_DPWROK,
-	X86_ALL_SYS_PGOOD,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-#endif /* __CROS_EC_ALDERLAKE_SLG4BD44540_H */
diff --git a/include/power/apollolake.h b/include/power/apollolake.h
deleted file mode 100644
index cc864f26c3..0000000000
--- a/include/power/apollolake.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Apollolake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_APOLLOLAKE_H
-#define __CROS_EC_APOLLOLAKE_H
-
-/*
- * Input state flags.
- * TODO: Normalize the power signal masks from board defines to SoC headers.
- */
-#define IN_RSMRST_N	POWER_SIGNAL_MASK(X86_RSMRST_N)
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_SLP_S3_N	POWER_SIGNAL_MASK(X86_SLP_S3_N)
-#define IN_SLP_S4_N	POWER_SIGNAL_MASK(X86_SLP_S4_N)
-#define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N
-#define IN_SUSPWRDNACK	POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
-#define IN_SUS_STAT_N	POWER_SIGNAL_MASK(X86_SUS_STAT_N)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \
-				  IN_SLP_S4_N)
-
-#define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PGOOD_ALL_CORE
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-enum power_signal {
-#ifdef CONFIG_POWER_S0IX
-	X86_SLP_S0_N,		/* PCH  -> SLP_S0_L */
-#endif
-	X86_SLP_S3_N,		/* PCH  -> SLP_S3_L */
-	X86_SLP_S4_N,		/* PCH  -> SLP_S4_L */
-	X86_SUSPWRDNACK,	/* PCH  -> SUSPWRDNACK */
-
-	X86_ALL_SYS_PG,		/* PMIC -> PMIC_EC_PWROK_OD */
-	X86_RSMRST_N,		/* PMIC -> PMIC_EC_RSMRST_ODL */
-	X86_PGOOD_PP3300,	/* PMIC -> PP3300_PG_OD */
-	X86_PGOOD_PP5000,	/* PMIC -> PP5000_PG_OD */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-#endif /* __CROS_EC_APOLLOLAKE_H */
diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h
deleted file mode 100644
index a056a96ec8..0000000000
--- a/include/power/cannonlake.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cannonlake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_CANNONLAKE_H
-#define __CROS_EC_CANNONLAKE_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-#endif /* __CROS_EC_CANNONLAKE_H */
diff --git a/include/power/cometlake-discrete.h b/include/power/cometlake-discrete.h
deleted file mode 100644
index 6f5370beee..0000000000
--- a/include/power/cometlake-discrete.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Chrome EC chipset power control for Cometlake with platform-controlled
- * discrete sequencing.
- */
-
-#ifndef __CROS_EC_COMETLAKE_DISCRETE_H
-#define __CROS_EC_COMETLATE_DISCRETE_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED \
-	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED)
-
-/*
- * Power mask used by intel_x86 to check that S5 is ready.
- *
- * This driver controls RSMRST in the G3->S5 transition so this check has nearly
- * no use, but letting the common Intel code read RSMRST allows us to avoid
- * duplicating the common code (introducing a little redundancy instead).
- *
- * PP3300 monitoring is analog-only: power_handle_state enforces that it's good
- * before continuing to common_intel_x86_power_handle_state. This means we can't
- * detect dropouts on that rail, however.
- *
- * Polling analog inputs as a signal for the common code would require
- * modification to support non-power signals as inputs and incurs a minimum 12
- * microsecond time penalty on NPCX7 to do an ADC conversion. Running the ADC
- * in repetitive scan mode and enabling threshold detection on the relevant
- * channels would permit immediate readings (that might be up to 100
- * microseconds old) but is not currently supported by the ADC driver.
- * TODO(b/143188569) try to implement analog watchdogs
- */
-#define CHIPSET_G3S5_POWERUP_SIGNAL          \
-	(POWER_SIGNAL_MASK(PP5000_A_PGOOD) | \
-	 POWER_SIGNAL_MASK(PP1800_A_PGOOD) | \
-	 POWER_SIGNAL_MASK(PP1050_A_PGOOD) | \
-	 POWER_SIGNAL_MASK(OUT_PCH_RSMRST_DEASSERTED))
-
-/*
- * Power mask used by intel_x86 to check that S3 is ready.
- *
- * Transition S5->S3 only involves turning on the DRAM power rails which are
- * controlled directly from the PCH, so this condition doesn't require any
- * special code, except this collection of signals is also polled in POWER_S3
- * and POWER_S0 states.
- *
- * During normal shutdown the PCH will turn off the DRAM rails before the EC
- * notices, so if this collection includes those rails a normal shutdown will be
- * treated as a power failure so the system immediately drops to G3 rather than
- * doing an orderly shutdown. This must only include those signals that are
- * EC-controlled, not those controlled by the PCH.
- */
-#define IN_PGOOD_ALL_CORE CHIPSET_G3S5_POWERUP_SIGNAL
-
-/*
- * intel_x86 power mask for S0 all-OK.
- *
- * This is only used on power task init to check whether the system is powered
- * up and already in S0, to correctly handle switching from RO to RW firmware.
- */
-#define IN_ALL_S0                                                   \
-	(IN_PGOOD_ALL_CORE | POWER_SIGNAL_MASK(PP2500_DRAM_PGOOD) | \
-	 POWER_SIGNAL_MASK(PP1200_DRAM_PGOOD) | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals, in power-on sequence order. */
-enum power_signal {
-	PP5000_A_PGOOD,
-	/* PP3300 monitoring is analog */
-	PP1800_A_PGOOD,
-	VPRIM_CORE_A_PGOOD,
-	PP1050_A_PGOOD,
-	OUT_PCH_RSMRST_DEASSERTED,
-	/* S5 ready */
-	X86_SLP_S4_DEASSERTED,
-	PP2500_DRAM_PGOOD,
-	PP1200_DRAM_PGOOD,
-	/* S3 ready */
-	X86_SLP_S3_DEASSERTED,
-	/* PP1050 monitoring is analog */
-	PP950_VCCIO_PGOOD,
-	/* S0 ready */
-	X86_SLP_S0_DEASSERTED,
-	CPU_C10_GATE_DEASSERTED,
-	IMVP8_READY,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-/*
- * Board-specific enable for any additional rails in S0.
- *
- * Input 0 to turn off, 1 to turn on.
- *
- * This function may be called from interrupts so must not assume it's running
- * in a task.
- */
-void board_enable_s0_rails(int enable);
-
-/*
- * Board-specific flag for whether EN_S0_RAILS can be turned off when
- * CPU_C10_GATED is asserted by the PCH.
- *
- * Return 0 if EN_S0_RAILS must be left on when in S0, even if the PCH asserts
- * the C10 gate.
- *
- * If this can ever return 1, the CPU_C10_GATE_L input from the PCH must also
- * be configured to call c10_gate_interrupt() rather than
- * power_signal_interrupt() in order to actually control the relevant core
- * rails.
- *
- * TODO: it is safe to remove this function and assume C10 gating is enabled if
- * support for rev0 puff boards is no longer required- it was added only for the
- * benefit of those boards.
- */
-int board_is_c10_gate_enabled(void);
-
-/*
- * Special interrupt for CPU_C10_GATE_L handling.
- *
- * Response time on resume from C10 has very strict timing requirements- no more
- * than 65 uS to turn on, and the load switches are specified to turn on in 65
- * uS max at 1V (30 uS typical). This means the response to changes on the C10
- * gate input must be as fast as possible to meet PCH timing requirements- much
- * faster than doing this handling in the power state machine can achieve
- * (hundreds of microseconds).
- */
-void c10_gate_interrupt(enum gpio_signal signal);
-
-/*
- * Special interrupt for SLP_S3_L handling.
- *
- * The time window in which to turn off some rails when dropping to S3 is
- * ~200us, and using the regular power state machine path tends to have latency
- * >1ms. This ISR short-circuits the relevant signals in a fast path before
- * scheduling a state machine update to ensure sufficiently low latency.
- */
-void slp_s3_interrupt(enum gpio_signal signal);
-
-#endif /* __CROS_EC_COMETLAKE_DISCRETE_H */
diff --git a/include/power/cometlake.h b/include/power/cometlake.h
deleted file mode 100644
index 0f48346c9e..0000000000
--- a/include/power/cometlake.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cometlake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_COMETLAKE_H
-#define __CROS_EC_COMETLAKE_H
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \
-	POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD))
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-	X86_SLP_S0_DEASSERTED,
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S4_DEASSERTED,
-	X86_RSMRST_L_PGOOD,
-	X86_PP5000_A_PGOOD,
-	X86_ALL_SYS_PGOOD,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-void all_sys_pgood_check_reboot(void);
-__override_proto void board_chipset_forced_shutdown(void);
-
-#endif /* __CROS_EC_COMETLAKE_H */
diff --git a/include/power/icelake.h b/include/power/icelake.h
deleted file mode 100644
index 08c14718ec..0000000000
--- a/include/power/icelake.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Icelake chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_ICELAKE_H
-#define __CROS_EC_ICELAKE_H
-
-#include "stdbool.h"
-
-/* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-	X86_SLP_S0_DEASSERTED,
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S4_DEASSERTED,
-	X86_SLP_SUS_DEASSERTED,
-	X86_RSMRST_L_PGOOD,
-	X86_DSW_DPWROK,
-	X86_ALL_SYS_PGOOD,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-struct intel_x86_pwrok_signal {
-	enum gpio_signal gpio;
-	bool active_low;
-	int delay_ms;
-};
-
-/*
- * Ice Lake/Tiger Lake/Jasper Lake PWROK Generation
- *
- * The following signals are controlled based on the state of the ALL_SYS_PWRGD
- * signal
- *
- *	VCCIN enable (input to the VCCIN voltage rail controller)
- *	VCCST_PWRGD (input to the SoC)
- *	PCH_PWROK (input to the SoC)
- *	SYS_PWROK (input to the SoC)
- *
- * For any the above signals that are controlled by the EC, create an entry
- * in the pwrok_signal_assert_list[] and pwrok_signal_deassert_list[] arrays.
- * The typical order for asserting the signals is shown above, the deassert
- * order is the reverse.
- *
- * ALL_SYS_PWRGD indicates when all the following are asserted.
- *	RSMRST_PWRGD & DPWROK
- *	S4 voltage rails good (DDR)
- *	VCCST voltage rail good
- *	S0 voltage rails good
- *
- * ALL_SYS_PWRGD can be implemented as a single GPIO if the platform power logic
- * combines the above power good signals. Otherwise your board can override
- * intel_x86_get_pg_ec_all_sys_pwrgd() to check multiple power good signals.
- */
-extern const struct intel_x86_pwrok_signal pwrok_signal_assert_list[];
-extern const int pwrok_signal_assert_count;
-extern const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[];
-extern const int pwrok_signal_deassert_count;
-
-#endif /* __CROS_EC_ICELAKE_H */
diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h
deleted file mode 100644
index 303db20de7..0000000000
--- a/include/power/intel_x86.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel X86 chipset power control module for Chrome EC */
-
-
-#ifndef __CROS_EC_INTEL_X86_H
-#define __CROS_EC_INTEL_X86_H
-
-#include "espi.h"
-#include "power.h"
-
-/* Chipset specific header files */
-#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)
-#include "alderlake_slg4bd44540.h"
-/* Geminilake and apollolake use same power sequencing. */
-#elif defined(CONFIG_CHIPSET_APL_GLK)
-#include "apollolake.h"
-#elif defined(CONFIG_CHIPSET_CANNONLAKE)
-#include "cannonlake.h"
-#elif defined(CONFIG_CHIPSET_COMETLAKE)
-#include "cometlake.h"
-#elif defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE)
-#include "cometlake-discrete.h"
-#elif defined(CONFIG_CHIPSET_ICELAKE)
-#include "icelake.h"
-#elif defined(CONFIG_CHIPSET_SKYLAKE)
-#include "skylake.h"
-#endif
-
-/* GPIO for power signal */
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define SLP_S3_SIGNAL_L VW_SLP_S3_L
-#else
-#define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L
-#endif
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define SLP_S4_SIGNAL_L VW_SLP_S4_L
-#else
-#define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L
-#endif
-
-/**
- * Handle RSMRST signal.
- *
- * @param state Current chipset state.
- */
-void common_intel_x86_handle_rsmrst(enum power_state state);
-
-/**
- * Force chipset to G3 state.
- *
- * @return power_state New chipset state.
- */
-enum power_state chipset_force_g3(void);
-
-/**
- * Handle power states.
- *
- * @param state        Current chipset state.
- * @return power_state New chipset state.
- */
-enum power_state common_intel_x86_power_handle_state(enum power_state state);
-
-/**
- * Wait for power-up to be allowed based on available power.
- *
- * This delays G3->S5 until there is enough power to boot the AP, waiting
- * first until the charger (if any) is ready, then for there to be sufficient
- * power.
- *
- * In case of error, the caller should not allow power-up past G3.
- *
- * @return EC_SUCCESS if OK.
- */
-enum ec_error_list intel_x86_wait_power_up_ok(void);
-
-/**
- * Get the value of PG_EC_DSW_PWROK.
- *
- * The default implementation is just to return the GPIO.  But if a
- * board doesn't have that GPIO, they may override this function.
- */
-__override_proto int intel_x86_get_pg_ec_dsw_pwrok(void);
-
-/**
- * Get the value of PG_EC_ALL_SYS_PWRGD.
- *
- * The default implementation is just to return the GPIO.  But if a
- * board doesn't have that GPIO, they may override this function.
- */
-__override_proto int intel_x86_get_pg_ec_all_sys_pwrgd(void);
-
-/**
- * Introduces SYS_RESET_L Debounce time delay
- *
- * The default implementation is to wait for a duration of 32 ms.
- * If board needs a different debounce time delay, they may override
- * this function
- */
-__override_proto void intel_x86_sys_reset_delay(void);
-
-#endif /* __CROS_EC_INTEL_X86_H */
diff --git a/include/power/mt8192.h b/include/power/mt8192.h
deleted file mode 100644
index e0c65c3bcc..0000000000
--- a/include/power/mt8192.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_POWER_MT8192_H_
-#define __CROS_EC_POWER_MT8192_H_
-
-enum power_signal {
-	PMIC_PWR_GOOD,
-	AP_IN_S3_L,
-	AP_WDT_ASSERTED,
-	POWER_SIGNAL_COUNT,
-};
-
-#endif /* __CROS_EC_POWER_MT8192_H_ */
diff --git a/include/power/qcom.h b/include/power/qcom.h
deleted file mode 100644
index 5f5247fa87..0000000000
--- a/include/power/qcom.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_POWER_QCOM_H_
-#define __CROS_EC_POWER_QCOM_H_
-
-#if defined(CONFIG_CHIPSET_SC7180) || defined(CONFIG_CHIPSET_SC7280)
-enum power_signal {
-	SC7X80_AP_RST_ASSERTED = 0,
-	SC7X80_PS_HOLD,
-	SC7X80_POWER_GOOD,
-	SC7X80_AP_SUSPEND,
-#ifdef CONFIG_CHIPSET_SC7180
-	SC7X80_WARM_RESET,
-	SC7X80_DEPRECATED_AP_RST_REQ,
-#endif
-	POWER_SIGNAL_COUNT,
-};
-#endif
-
-/* Swithcap functions */
-void board_set_switchcap_power(int enable);
-int board_is_switchcap_enabled(void);
-int board_is_switchcap_power_good(void);
-
-#endif /* __CROS_EC_POWER_QCOM_H_ */
diff --git a/include/power/skylake.h b/include/power/skylake.h
deleted file mode 100644
index c8a656c6c5..0000000000
--- a/include/power/skylake.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_SKYLAKE_H
-#define __CROS_EC_SKYLAKE_H
-
-/*
- * Input state flags.
- * TODO: Normalize the power signal masks from board defines to SoC headers.
- */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
-
-/*
- * DPWROK is NC / stuffing option on initial boards.
- * TODO(shawnn): Figure out proper control signals.
- */
-#define IN_PGOOD_ALL_CORE 0
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-#ifdef CONFIG_POWER_S0IX
-	X86_SLP_S0_DEASSERTED,
-#endif
-	X86_SLP_S3_DEASSERTED,
-	X86_SLP_S4_DEASSERTED,
-	X86_SLP_SUS_DEASSERTED,
-	X86_RSMRST_L_PWRGD,
-	X86_PMIC_DPWROK,
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT
-};
-
-/*
- * Board can define this function to indicate to the skylake
- * power code that it does not have working reset flags.
- */
-int board_has_working_reset_flags(void);
-
-#endif /* __CROS_EC_SKYLAKE_H */
diff --git a/include/power_button.h b/include/power_button.h
deleted file mode 100644
index 167ca21e2b..0000000000
--- a/include/power_button.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power button API for Chrome EC */
-
-#ifndef __CROS_EC_POWER_BUTTON_H
-#define __CROS_EC_POWER_BUTTON_H
-
-#include "common.h"
-
-/**
- * Return non-zero if power button is pressed.
- *
- * Uses the debounced button state, not the raw signal from the GPIO.
- */
-int power_button_is_pressed(void);
-
-/**
- * Wait for the power button to be released
- *
- * @param timeout_us Timeout in microseconds, or -1 to wait forever
- * @return EC_SUCCESS if ok, or
- *         EC_ERROR_TIMEOUT if power button failed to release
- */
-int power_button_wait_for_release(int timeout_us);
-
-/**
- * Return non-zero if power button signal asserted at hardware input.
- *
- */
-int power_button_signal_asserted(void);
-
-/**
- * Interrupt handler for power button.
- *
- * @param signal	Signal which triggered the interrupt.
- */
-void power_button_interrupt(enum gpio_signal signal);
-
-/**
- * For x86 systems, force-assert the power button signal to the PCH.
- */
-void power_button_pch_press(void);
-
-/**
- * For x86 systems, force-deassert the power button signal to the PCH.
- */
-void power_button_pch_release(void);
-
-/**
- * For x86 systems, force a pulse of the power button signal to the PCH.
- */
-void power_button_pch_pulse(void);
-
-/**
- * Returns the time when DSW_PWROK was asserted. It should be customized
- * by each board. See CONFIG_DELAY_DSW_PWROK_TO_PWRBTN for details.
- *
- * @return time in usec when DSW_PWROK was asserted.
- */
-int64_t get_time_dsw_pwrok(void);
-
-/**
- * This must be defined when CONFIG_POWER_BUTTON_TO_PCH_CUSTOM is defined. This
- * allows a board to override the default behavior of
- * gpio_set_level(GPIO_PCH_PWRBTN_L, level).
- */
-void board_pwrbtn_to_pch(int level);
-
-#endif  /* __CROS_EC_POWER_BUTTON_H */
diff --git a/include/power_led.h b/include/power_led.h
deleted file mode 100644
index 05ea7ead3c..0000000000
--- a/include/power_led.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power button LED control for Chrome EC */
-
-#ifndef __CROS_EC_POWER_LED_H
-#define __CROS_EC_POWER_LED_H
-
-#include "common.h"
-
-enum powerled_state {
-	POWERLED_STATE_OFF,
-	POWERLED_STATE_ON,
-	POWERLED_STATE_SUSPEND,
-	POWERLED_STATE_COUNT
-};
-
-#ifdef HAS_TASK_POWERLED
-
-/**
- * Set the power LED
- *
- * @param state		Target state
- */
-void powerled_set_state(enum powerled_state state);
-
-#else
-
-static inline void powerled_set_state(enum powerled_state state) {}
-
-#endif
-
-#endif /* __CROS_EC_POWER_LED_H */
diff --git a/include/pwm.h b/include/pwm.h
deleted file mode 100644
index 401d3dc0ec..0000000000
--- a/include/pwm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PWM_H
-#define __CROS_EC_PWM_H
-
-/* The values are defined in board.h */
-enum pwm_channel;
-
-/**
- * Enable/disable a PWM channel.
- */
-void pwm_enable(enum pwm_channel ch, int enabled);
-
-/**
- * Get PWM channel enabled status.
- */
-int pwm_get_enabled(enum pwm_channel ch);
-
-/**
- * Set PWM channel duty cycle (0-65535).
- */
-void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty);
-
-/**
- * Get PWM channel duty cycle.
- */
-uint16_t pwm_get_raw_duty(enum pwm_channel ch);
-
-/**
- * Set PWM channel duty cycle (0-100).
- */
-void pwm_set_duty(enum pwm_channel ch, int percent);
-
-/**
- * Get PWM channel duty cycle.
- */
-int pwm_get_duty(enum pwm_channel ch);
-
-
-/* Flags for PWM config table */
-
-/**
- * PWM output signal is inverted, so 100% duty means always low
- */
-#define PWM_CONFIG_ACTIVE_LOW		BIT(0)
-/**
- * PWM channel has a fan controller with a tach input and can auto-adjust
- * its duty cycle to produce a given fan RPM.
- */
-#define PWM_CONFIG_HAS_RPM_MODE		BIT(1)
-/**
- * PWM clock select alternate source.  The actual clock and alternate
- * source are chip dependent.
- */
-#define PWM_CONFIG_ALT_CLOCK		BIT(2)
-/**
- * PWM channel has a complementary output signal which should be enabled in
- * addition to the primary output.
- */
-#define PWM_CONFIG_COMPLEMENTARY_OUTPUT	BIT(3)
-/**
- * PWM channel must stay active in low-power idle, if enabled.
- */
-#define PWM_CONFIG_DSLEEP		BIT(4)
-/**
- * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.)
- */
-#define PWM_CONFIG_OPEN_DRAIN		BIT(5)
-#endif  /* __CROS_EC_PWM_H */
diff --git a/include/pwr_defs.h b/include/pwr_defs.h
deleted file mode 100644
index c01e602397..0000000000
--- a/include/pwr_defs.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PWR_DEFS_H
-#define __CROS_EC_PWR_DEFS_H
-
-#include "system.h"
-
-struct pwr_con_t {
-	uint16_t volts;
-	uint16_t milli_amps;
-};
-
-/*
- * Return power (in milliwatts) corresponding to input power connection
- * struct entry.
- */
-inline int pwr_con_to_milliwatts(struct pwr_con_t *pwr)
-{
-	return (pwr->volts * pwr->milli_amps);
-}
-
-#endif
diff --git a/include/regulator.h b/include/regulator.h
deleted file mode 100644
index 9dae7233c1..0000000000
--- a/include/regulator.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_REGULATOR_H
-#define __CROS_EC_REGULATOR_H
-
-#include "common.h"
-
-/*
- * Board dependent hooks on voltage regulators.
- *
- * These functions should be implemented by boards which
- * CONFIG_HOSTCMD_REGULATOR is defined.
- */
-
-/*
- * Get basic info of voltage regulator for given index.
- *
- * Note that the maximum length of name is EC_REGULATOR_NAME_MAX_LEN, and the
- * maximum length of the voltages_mv list is EC_REGULATOR_VOLTAGE_MAX_COUNT.
- */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *voltage_count, uint16_t *voltages_mv);
-
-/*
- * Configure the regulator as enabled / disabled.
- */
-int board_regulator_enable(uint32_t index, uint8_t enable);
-
-/*
- * Query if the regulator is enabled.
- */
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled);
-
-/*
- * Set voltage for the voltage regulator within the range specified.
- *
- * The driver should select the voltage in range closest to min_mv.
- *
- * Also note that this might be called before the regulator is enabled, and the
- * setting should be in effect after the regulator is enabled.
- */
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv);
-
-/*
- * Get the currently configured voltage for the voltage regulator.
- *
- * Note that this might be called before the regulator is enabled.
- */
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv);
-
-#endif /* !defined(__CROS_EC_REGULATOR_H) */
diff --git a/include/rma_auth.h b/include/rma_auth.h
deleted file mode 100644
index 0a4d7c7e71..0000000000
--- a/include/rma_auth.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* RMA challenge-response */
-
-#ifndef __CROS_EC_RMA_AUTH_H
-#define __CROS_EC_RMA_AUTH_H
-
-#include <stdint.h>
-
-#include "common.h"  /* For __packed. */
-
-/* Current challenge protocol version */
-#define RMA_CHALLENGE_VERSION 0
-
-/* Getters and setters for version_key_id byte */
-#define RMA_CHALLENGE_VKID_BYTE(version, keyid) \
-	(((version) << 6) | ((keyid) & 0x3f))
-#define RMA_CHALLENGE_GET_VERSION(vkidbyte) ((vkidbyte) >> 6)
-#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte) & 0x3f)
-
-#define RMA_DEVICE_ID_SIZE 8
-
-struct __packed rma_challenge {
-	/* Top 2 bits are protocol version; bottom 6 are server KeyID */
-	uint8_t version_key_id;
-
-	/* Ephemeral public key from device */
-	uint8_t device_pub_key[32];
-
-	/* Board ID (.type) */
-	uint8_t board_id[4];
-
-	/* Device ID */
-	uint8_t device_id[RMA_DEVICE_ID_SIZE];
-};
-
-/* Size of encoded challenge and response, and buffer sizes to hold them */
-#define RMA_CHALLENGE_CHARS 80
-#define RMA_CHALLENGE_BUF_SIZE (RMA_CHALLENGE_CHARS + 1)
-
-#define RMA_AUTHCODE_CHARS 8
-#define RMA_AUTHCODE_BUF_SIZE (RMA_AUTHCODE_CHARS + 1)
-
-/**
- * Create a new RMA challenge/response
- *
- * @return EC_SUCCESS, EC_ERROR_TIMEOUT if too soon since the last challenge,
- * or other non-zero error code.
- */
-int rma_create_challenge(void);
-
-/**
- * Get the current challenge string
- *
- * @return a pointer to the challenge string.  String will be empty if there
- * is no active challenge.
- */
-const char *rma_get_challenge(void);
-
-/**
- * Try a RMA authorization code
- *
- * @param code		Authorization code to try (buffer needs to be at least
- * RMA_AUTHCODE_CHARS bytes long, no matter the actual string length, as the
- * function uses safe_memcmp to prevent timing attacks).
- * @return EC_SUCCESS if the response was correct, or non-zero error code.
- */
-int rma_try_authcode(const char *code);
-
-/**
- * Get the device ID returned in RMA response.
- *
- * @param rma_device_id		Pointer to the buffer that will be filled with
- * the ID. The buffer must be of size RMA_DEVICE_ID_SIZE.
- */
-void get_rma_device_id(uint8_t rma_device_id[RMA_DEVICE_ID_SIZE]);
-
-#endif
diff --git a/include/rtc.h b/include/rtc.h
deleted file mode 100644
index cff1ee0f64..0000000000
--- a/include/rtc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* RTC cross-platform functions */
-
-#ifndef __CROS_EC_RTC_H
-#define __CROS_EC_RTC_H
-
-#include "common.h"
-
-#define SECS_PER_MINUTE     60
-#define SECS_PER_HOUR       (60 * SECS_PER_MINUTE)
-#define SECS_PER_DAY        (24 * SECS_PER_HOUR)
-#define SECS_PER_WEEK       (7 * SECS_PER_DAY)
-#define SECS_PER_YEAR       (365 * SECS_PER_DAY)
-/* The seconds elapsed from 01-01-1970 to 01-01-2000 */
-#define SECS_TILL_YEAR_2K   (946684800)
-#define IS_LEAP_YEAR(x)     \
-	(((x) % 4 == 0) && (((x) % 100 != 0) || ((x) % 400 == 0)))
-
-struct calendar_date {
-	/* The number of years since A.D. 2000, i.e. year = 17 for y2017 */
-	uint8_t year;
-	/* 1-based indexing, i.e. valid values range from 1 to 12 */
-	uint8_t month;
-	/* 1-based indexing, i.e. valid values range from 1 to 31 */
-	uint8_t day;
-};
-
-/**
- * Convert calendar date to seconds elapsed since epoch time.
- *
- * @param time  The calendar date (years, months, and days).
- * @return the seconds elapsed since epoch time (01-01-1970 00:00:00).
- */
-uint32_t date_to_sec(struct calendar_date time);
-
-/**
- * Convert seconds elapsed since epoch time to calendar date
- *
- * @param sec  The seconds elapsed since epoch time (01-01-1970 00:00:00).
- * @return the calendar date (years, months, and days).
- */
-struct calendar_date sec_to_date(uint32_t sec);
-
-#endif /* __CROS_EC_RTC_H */
diff --git a/include/sfdp.h b/include/sfdp.h
deleted file mode 100644
index 087708d799..0000000000
--- a/include/sfdp.h
+++ /dev/null
@@ -1,807 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* JEDEC Serial Flash Discoverable Parameters (SFDP) for Serial NOR Flash,
- * covering v1.0 (JESD216) & v1.5 (JESD216A). */
-#ifndef __CROS_EC_SFDP_H
-#define __CROS_EC_SFDP_H
-
-/**
- * Helper macros to declare and access SFDP defined bitfields at a JEDEC SFDP
- * defined double word (32b) granularity.
- */
-#define SFDP_DEFINE_BITMASK_32(name, hi, lo)                              \
-	static const uint32_t name = (((1ULL << ((hi) - (lo) + 1)) - 1UL) \
-				      << (lo));
-#define SFDP_DEFINE_SHIFT_32(name, hi, lo) \
-	static const size_t name = (lo);
-#define SFDP_DEFINE_BITFIELD(name, hi, lo)            \
-	SFDP_DEFINE_BITMASK_32(name ## _MASK, hi, lo) \
-	SFDP_DEFINE_SHIFT_32(name ## _SHIFT, hi, lo)
-#define SFDP_GET_BITFIELD(name, dw) \
-	(((dw) & name ## _MASK) >> name ## _SHIFT)
-
-/**
- * Helper macros to construct SFDP defined double words (32b). Note reserved or
- * unused fields must always be set to all 1's.
- */
-#define SFDP_BITFIELD(name, value) (((value) << name ## _SHIFT) & name ## _MASK)
-#define SFDP_UNUSED(hi, lo) (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo))
-
-/******************************************************************************/
-/* SFDP Header, always located at SFDP offset 0x0. Note that the SFDP space is
- * always read in 3 Byte addressing mode with a single cycle, where the
- * expected SFDP address space layout looks like the following:
- *
- *  ------------------0x00
- *  | SFDP Header        |  (specifying X number of Parameter Headers)
- *  ------------------0x08
- *  | Parameter Header 1 |  (specifying Y Parameter Table Pointer & Length L)
- *  ------------------0x10
- *          - - -
- *  --------------X * 0x08
- *  | Parameter Header X |  (specifying Z Parameter Table Pointer & Length K)
- *  --------(X + 1) * 0x08
- *          - - -
- *  ---------------------Y
- *  | Parameter Table 1  |
- *  -------------------Y+L
- *         - - -
- *  ---------------------Z            Key:    ------start_sfdp_offset
- *  | Parameter Table X  |                    | Region Name         |
- *  -------------------Z+K                    ------limit_sfdp_offset
- */
-
-/*
- * SFDP Header 1st DWORD
- * ---------------------
- * <31:24> : Fourth signature byte == 'P'
- * <23:16> : Third signature byte  == 'D'
- * <15:8>  : Second signature byte == 'F'
- * <7:0>   : First signature byte  == 'S'
- */
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_P, 31, 24);
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_D, 23, 16);
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_F, 15, 8);
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_S, 7, 0);
-#define SFDP_HEADER_DWORD_1(s, f, d, p)        \
-	(SFDP_BITFIELD(SFDP_HEADER_DW1_P, p) | \
-	 SFDP_BITFIELD(SFDP_HEADER_DW1_D, d) | \
-	 SFDP_BITFIELD(SFDP_HEADER_DW1_F, f) | \
-	 SFDP_BITFIELD(SFDP_HEADER_DW1_S, s))
-
-#define SFDP_HEADER_DW1_SFDP_SIGNATURE_VALID(x) (x == 0x50444653)
-
-/*
- * SFDP Header 2nd DWORD
- * ---------------------
- * <31:24> : Unused
- * <23:16> : Number of Parameter Headers (0-based, 0 indicates 1)
- * <15:8>  : SFDP Major Revision Number
- * <7:0>   : SFDP Minor Revision Number
- */
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_NPH, 23, 16);
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, 15, 8);
-SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0);
-#define SFDP_HEADER_DWORD_2(nph, major, minor)              \
-	(SFDP_UNUSED(31, 24) |                              \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) |          \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, minor))
-
-/******************************************************************************/
-/* SFDP v1.0 Parameter Headers, starts at SFDP offset 0x8 and there are as many
- * as specified in the v1.0 SFDP header. */
-
-/* In SFDP v1.0, the only reserved ID was the Basic Flash Parameter Table ID of
- * 0x00. Otherwise this field must be set to the vendor's manufacturer ID. Note,
- * the spec does not call out how to report the manufacturer bank number. */
- #define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00
-
-/*
- * SFDP v1.0: Parameter Header 1st DWORD
- * --------------------------
- * <31:24> : Parameter Table Length (1-based, 1 indicates 1)
- * <23:16> : Parameter Table Major Revision Number
- * <15:8>  : Parameter Table Minor Revision Number
- * <7:0>   : ID number
- */
-SFDP_DEFINE_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_PTL, 31, 24);
-SFDP_DEFINE_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MAJOR, 23, 16);
-SFDP_DEFINE_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MINOR, 15, 8);
-SFDP_DEFINE_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_ID, 7, 0);
-#define SFDP_1_0_PARAMETER_HEADER_DWORD_1(ptl, major, minor, id)           \
-	(SFDP_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_PTL, ptl) |           \
-	 SFDP_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MAJOR, major) | \
-	 SFDP_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_TABLE_MINOR, minor) | \
-	 SFDP_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_ID, id))
-
-/*
- * SFDP v1.0: Parameter Header 2nd DWORD
- * --------------------------
- * <31:24> : Unused (0xFF)
- * <23:0>  : Parameter Table Pointer (SFDP offset which must be word aligned)
- */
-SFDP_DEFINE_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW2_PTP, 23, 0);
-#define SFDP_1_0_PARAMETER_HEADER_DWORD_2(ptp) \
-	(SFDP_UNUSED(31, 24) |                 \
-	 SFDP_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW2_PTP, ptp))
-
-/******************************************************************************/
-/* SFDP v1.5 Parameter Headers, starts at SFDP offset 0x8 and there are as many
- * as specified in the v1.5 SFDP header. */
-
-/* Parameter ID MSB | Parameter ID LSB | Type                  | Owner
- * ==========================================================================
- * 0x00             | All              | Reserved              | JEDEC JC42.4
- * --------------------------------------------------------------------------
- * 0x01 - 0x7F      | odd parity       | JEDEC JEP106          | Vendor
- *                  |                  | Manufacturer ID       |
- *                  |                  | (mfn=LSB, bank=MSB)   |
- * --------------------------------------------------------------------------
- * 0x01 - 0x7F      | even parity      | Function Specific     | Vendor
- * --------------------------------------------------------------------------
- * 0x80 - 0xFE      | even parity      | Function Specific     | JEDEC JC42.4
- * --------------------------------------------------------------------------
- * 0xFF             | 0x00             | Basic Flash Parameter | JEDEC JC42.4
- *                  |                  | Table                 |
- * -------------------------------------------------------------------------- */
-
-#define BASIC_FLASH_PARAMETER_TABLE_1_5_ID_MSB 0xFF
-#define BASIC_FLASH_PARAMETER_TABLE_1_5_ID_LSB 0x00
-
-/*
- * SFDP v1.5: Parameter Header 1st DWORD
- * --------------------------
- * <31:24> : Parameter Table Length (1-based, 1 indicates 1)
- * <23:16> : Parameter Table Major Revision Number
- * <15:8>  : Parameter Table Minor Revision Number
- * <7:0>   : Parameter ID LSB
- */
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_PTL, 31, 24);
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_TABLE_MAJOR, 23, 16);
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_TABLE_MINOR, 15, 8);
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, 7, 0);
-#define SFDP_1_5_PARAMETER_HEADER_DWORD_1(ptl, major, minor, idlsb)        \
-	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_PTL, ptl) |           \
-	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_TABLE_MAJOR, major) | \
-	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_TABLE_MINOR, minor) | \
-	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, idlsb))
-
-/*
- * SFDP v1.5: Parameter Header 2nd DWORD
- * --------------------------
- * <31:24> : Parameter ID MSB
- * <23:0>  : Parameter Table Pointer (SFDP offset which must be word aligned)
- */
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, 31, 24);
-SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, 23, 0);
-#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp)                     \
-	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) |     \
-	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, ptp))
-
-/******************************************************************************/
-/* JEDEC (SPI Protocol) Basic Flash Parameter Table v1.0. The reporting of at
- * least one revision of this table is mandatory and must be specified by the
- * first parameter header.*/
-
-/* Basic Flash Parameter Table v1.0 1st DWORD
- * ------------------------------------------
- * <31:23> : Unused
- * <22>    : Supports 1-1-4 Fast Read (1 if supported)
- * <21>    : Supports 1-4-4 Fast Read (1 if supported)
- * <20>    : Supports 1-2-2 Fast Read (1 if supported)
- * <19>    : Supports Double Transfer Rate (DTR) Clocking (1 if supported)
- * <18:17> : Address Bytes:
- *            - 0x0 if 3 Byte addressing only
- *            - 0x1 if defaults to 3B addressing, enters 4B on command
- *            - 0x2 if 4 Byte addressing only
- * <16>    : Supports 1-1-2 Fast Read (1 if supported)
- * <15:8>  : 4KiB Erase Opcode (0xFF if unsupported)
- * <7:5>   : Unused
- * <4>     : Write Enable Opcode Select for Writing to Volatile Status Register:
- *            - 0x0 if 0x50 is the opcode to enable a status register write
- *            - 0x1 if 0x06 is the opcode to enable a status register write
- * <3>     : Write Enable Instruction Required for writing to Volatile Status
- *           Register:
- *            - 0x0 if target flash only has nonvolatile status bits and does
- *              not require status register to be written every power on
- *            - 0x1 if target flash requires 0x00 to be written to the status
- *              register in order to allow writes and erases
- * <2>     : Write granularity (0 if the buffer is less than 64B, 1 if larger)
- * <1:0>   : Block/Sector Erase granularity available for the entirety of flash:
- *            - 0x1 if 4KiB is uniformly available
- *            - 0x3 if 4KiB is unavailable
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, 22, 22);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, 21, 21);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, 20, 20);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, 19, 19);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, 18, 17);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, 16, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, 4, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_REQ, 3, 3);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, 2, 2);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, 1, 0);
-#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112,              \
-				    rm4kb, wrenop, wrenrq, wrgr,  ergr)      \
-	(SFDP_UNUSED(31, 23) |                                               \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) |                    \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) |              \
-	 SFDP_UNUSED(7, 5) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) |            \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) |               \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, ergr))
-
-/* Basic Flash Parameter Table v1.0 2nd DWORD
- * ------------------------------------------
- * <31>   : Density greater than 2 gibibits
- * <30:0> : N, where:
- *           - if =< 2 gibibits, flash memory density is N+1 bits
- *           - if > 2 gibibits, flash memory density is 2^N bits
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, 31, 31);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW2_N, 30, 0);
-#define BFPT_1_0_DWORD_2(gt_2_gibibits, n)                          \
-	(SFDP_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, gt_2_gibibits) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW2_N, n))
-
-/* Basic Flash Parameter Table v1.0 3rd DWORD
- * ------------------------------------------
- * <31:24> : 1-1-4 Fast Read Opcode
- * <23:21> : 1-1-4 Fast Read Number of Mode Bits (0 if unsupported)
- * <20:16> : 1-1-4 Fast Read Number of Wait States (Wait State Clocks)
- * <15:8>  : 1-4-4 Fast Read Opcode
- * <7:5>   : 1-4-4 Fast Read Number of Mode Bits (0 if unsupported)
- * <4:0>   : 1-4-4 Fast Read Number of Wait States (Wait State CLocks)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, 23, 21);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc,                \
-				    fr144op, fr144mb, fr144dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc))
-
-/* Basic Flash Parameter Table v1.0 4th DWORD
- * ------------------------------------------
- * <31:24> : 1-2-2 Fast Read Opcode
- * <23:21> : 1-2-2 Fast Read Number of Mode Bits (0 if unsupported)
- * <20:16> : 1-2-2 Fast Read Number of Wait States (Wait State Clocks)
- * <15:8>  : 1-1-2 Fast Read Opcode
- * <7:5>   : 1-1-2 Fast Read Number of Mode Bits (0 if unsupported)
- * <4:0>   : 1-1-2 Fast Read Number of Wait States (Wait State CLocks)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, 23, 21);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc,                \
-				    fr112op, fr112mb, fr112dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc))
-
-/* Basic Flash Parameter Table v1.0 5th DWORD
- * ------------------------------------------
- * <31:5> : Reserved (0x7FFFFFF)
- * <4>    : Supports 4-4-4 Fast Read (1 if supported)
- * <3:1>  : Reserved (0x7)
- * <0>    : Supports 2-2-2 Fast Read (1 if supported)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_4_4_4_SUPPORTED, 4, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0);
-#define BFPT_1_0_DWORD_5(fr444, fr222)                        \
-	(SFDP_UNUSED(31, 5) |                                 \
-	 SFDP_BITFIELD(BFPT_1_0_DW5_4_4_4_SUPPORTED, fr444) | \
-	 SFDP_UNUSED(3, 1) |                                  \
-	 SFDP_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, fr222))
-
-/* Basic Flash Parameter Table v1.0 6th DWORD
- * ------------------------------------------
- * <31:24> : 2-2-2 Fast Read Opcode
- * <23:21> : 2-2-2 Fast Read Number of Mode Bits (0 if unsupported)
- * <20:16> : 2-2-2 Fast Read Number of Wait States (Wait State Clocks)
- * <15:0>  : Reserved (0xFFFF)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \
-	 SFDP_UNUSED(15, 0))
-
-/* Basic Flash Parameter Table v1.0 7th DWORD
- * ------------------------------------------
- * <31:24> : 4-4-4 Fast Read Opcode
- * <23:21> : 4-4-4 Fast Read Number of Mode Bits (0 if unsupported)
- * <20:16> : 4-4-4 Fast Read Number of Wait States (Wait State Clocks)
- * <15:0>  : Reserved (0xFFFF)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \
-	 SFDP_UNUSED(15, 0))
-
-/* Basic Flash Parameter Table v1.0 8th DWORD
- * ------------------------------------------
- * <31:24> : Sector Type 2 Erase Opcode
- * <23:16> : Sector Type 2 Erase Size (2^N Bytes, 0 if unavailable)
- * <15:8>  : Sector Type 1 Erase Opcode
- * <7:0>   : Sector Type 1 Erase Size (2^N Bytes, 0 if unavailable)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_2_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_2_SIZE, 23, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_1_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_1_SIZE, 7, 0);
-#define BFPT_1_0_DWORD_8(rm2op, rm2sz, rm1op, rm1sz)              \
-	(SFDP_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_2_OPCODE, rm2op) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_2_SIZE, rm2sz) |   \
-	 SFDP_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_1_OPCODE, rm1op) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW8_ERASE_TYPE_1_SIZE, rm1sz))
-
-/* Basic Flash Parameter Table v1.0 9th DWORD
- * ------------------------------------------
- * <31:24> : Sector Type 4 Erase Opcode
- * <23:16> : Sector Type 4 Erase Size (2^N Bytes, 0 if unavailable)
- * <15:8>  : Sector Type 3 Erase Opcode
- * <7:0>   : Sector Type 3 Erase Size (2^N Bytes, 0 if unavailable)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_4_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_4_SIZE, 23, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_3_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_3_SIZE, 7, 0);
-#define BFPT_1_0_DWORD_9(rm4op, rm4sz, rm3op, rm3sz)              \
-	(SFDP_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_4_OPCODE, rm4op) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_4_SIZE, rm4sz) |   \
-	 SFDP_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_3_OPCODE, rm3op) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW9_ERASE_TYPE_3_SIZE, rm3sz))
-
-/******************************************************************************/
-/* JEDEC (SPI Protocol) Basic Flash Parameter Table v1.5. The reporting of at
- * least one revision of this table is mandatory and must be specified by the
- * first parameter header. Note that DWORDs 1-9 are identical to v1.0. */
-
-/* Basic Flash Parameter Table v1.5 10th DWORD
- * ------------------------------------------
- * <31:30> : Sector Type 4 Erase, Typical time units, where
- *           0x0: 1ms, 0x1: 16ms, 0x2: 128ms, 0x3: 1s
- * <29:25> : Sector Type 4 Erase, Typical time count, where
- *           time = (count + 1) * units
- * <24:23> : Sector Type 3 Erase, Typical time units, where
- *           0x0: 1ms, 0x1: 16ms, 0x2: 128ms, 0x3: 1s
- * <22:18> : Sector Type 3 Erase, Typical time count, where
- *           time = (count + 1) * units
- * <17:16> : Sector Type 2 Erase, Typical time units, where
- *           0x0: 1ms, 0x1: 16ms, 0x2: 128ms, 0x3: 1s
- * <15:11> : Sector Type 2 Erase, Typical time count, where
- *           time = (count + 1) * units
- * <10:9>  : Sector Type 1 Erase, Typical time units, where
- *           0x0: 1ms, 0x1: 16ms, 0x2: 128ms, 0x3: 1s
- * <8:4>   : Sector Type 1 Erase, Typical time count, where
- *           time = (count + 1) * units
- * <3:0>   : Multiplier from typical to maximum erase time, where
- *           maximum_time = 2 * (multiplier + 1) * typical_time
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, 31, 30);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, 29, 25);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, 24, 23);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, 22, 18);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, 17, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, 15, 11);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, 10, 9);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, 8, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, 3, 0);
-#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit,               \
-			  rm3count, rm2unit, rm2count,              \
-			  rm1unit, rm1count, maxmult)               \
-	(SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, maxmult))
-
-/* Basic Flash Parameter Table v1.5 11th DWORD
- * ------------------------------------------
- * <31>    : Reserved (0x1)
- * <30:29> : Chip Erase, Typical time units, where
- *           0x0: 16ms, 0x1: 256ms, 0x2: 4s, 0x3: 64s
- * <28:24> : Chip Erase, Typical time count, where time = (count + 1) * units
- * <23>    : Additional Byte Program, Typical time units (0: 1us, 1: 8us)
- * <22:19> : Additional Byte Program, Typical time count, where each byte takes
- *           time = (count + 1) * units * bytes. This should not be
- *           used if the additional bytes count exceeds 1/2 a page size.
- * <18>    : First Byte Program, Typical time units (0: 1us, 1: 8us)
- * <17:14> : First Byte Program, Typical time count, where each byte takes
- *           time = (count + 1) * units * bytes
- * <13>    : Page Program, Typical time units (0: 8us, 1: 64us)
- * <12:8>  : Page Program, Typical time count, where time = (count + 1) * units
- * <7:4>   : Page Size (2^N Bytes)
- * <3:0>   : Multiplier from typical time to max time for programming, where
- *           maximum_time = 2 * (multiplier + 1) * typical_time
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, 30, 29);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, 28, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, 23, 23);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, 22, 19);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, 18, 18);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, 17, 14);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, 13, 13);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, 12, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, 7, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, 3, 0);
-#define BFPT_1_5_DWORD_11(crmunit, crmcount, mrbunit, mrbcount, initunit,  \
-			  initcount, pgwrunit, pgwrcount, pagesz, maxmult) \
-	(SFDP_UNUSED(31, 31) |                                             \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT,                 \
-		       crmunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT,                  \
-		       crmcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT,               \
-		       mrbunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT,                \
-		       mrbcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT,               \
-		       initunit) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT,                \
-		       initcount) |                                        \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, pgwrunit) |        \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, pgwrcount) |        \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, pagesz) |                  \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, maxmult))
-
-/* Basic Flash Parameter Table v1.5 12th DWORD
- * ------------------------------------------
- * <31>    : Suspend / Resume unsupported (1 unsupported, 0 supported)
- * <30:29> : Suspend in-progress erase max latency units, where
- *           0x0: 128ns, 0x1: 1us, 0x2: 8us, 0x3: 64us
- * <28:24> : Suspend in-progress erase max latency count, where
- *           max latency = (count + 1) * units
- * <23:20> : Erase resume to suspend minimum interval, (count + 1) * 64us
- * <19:18> : Suspend in-progress program max latency units, where
- *           0x0: 128ns, 0x1: 1us, 0x2: 8us, 0x3: 64us
- * <17:13> : Suspend in-progress program max latency count, where
- *           max latency = (count + 1) * units
- * <12:9>  : Program resume to suspend minimum internal, (count + 1) * 64us
- * <8>     : Reserved (0x1)
- * <7:4>   : Prohibited Operations During Erase Suspend flags, where
- *           xxx0b May not initiate a new erase anywhere
- *                 (erase nesting not permitted)
- *           xxx1b May not initiate a new erase in the erase suspended sector
- *                 size
- *           xx0xb May not initiate a page program anywhere
- *           xx1xb May not initiate a page program in the erase suspended
- *                 sector size
- *           x0xxb Refer to vendor datasheet for read restrictions
- *           x1xxb May not initiate a read in the erase suspended sector size
- *           0xxxb Additional erase or program restrictions apply
- *           1xxxb The erase and program restrictions in bits 5:4 are
- *                 sufficient
- * <3:0>   : Prohibited Operations During Program Suspend flags, where
- *           xxx0b May not initiate a new erase anywhere
- *                 (erase nesting not permitted)
- *           xxx1b May not initiate a new erase in the program suspended page
- *                 size
- *           xx0xb May not initiate a new page program anywhere
- *                 (program nesting not permitted)
- *           xx1xb May not initiate a new page program in the program suspended
- *                 page size
- *           x0xxb Refer to vendor datasheet for read restrictions
- *           x1xxb May not initiate a read in the program suspended page size
- *           0xxxb Additional erase or program restrictions apply
- *           1xxxb The erase and program restrictions in bits 1:0 are
- *                 sufficient
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, 31, 31);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, 30, 29);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, 28, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT, 23, 20);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, 19, 18)
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, 17, 13);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, 12, 9);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, 7, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, 3, 0);
-#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \
-			  suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt,   \
-			  prohibopsrmsusp, prohibopswrsusp)                  \
-	(SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) |           \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT,                   \
-		       susprmlatun) |                                        \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT,                    \
-		       susprmlatcnt) |                                       \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT,                 \
-		       rmressusplatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT,                   \
-		       suspwrmaxlatunit) |                                   \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT,                    \
-		       suspwrmaxlatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT,                 \
-		       wrressuspcnt) |                                       \
-	 SFDP_UNUSED(8, 8) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP,              \
-		       prohibopsrmsusp) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP,              \
-		       prohibopswrsusp))
-
-/* Basic Flash Parameter Table v1.5 13th DWORD
- * ------------------------------------------
- * <31:24> : Suspend Instruction used to suspend a write or erase type operation
- * <23:16> : Resume Instruction used to resume a write or erase type operation
- * <15:8>  : Program Suspend Instruction used to suspend a program operation
- * <7:0>   : Program Resume Instruction used to resume a program operation
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW13_SUSPEND_OPCODE, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW13_RESUME_OPCODE, 23, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW13_WR_SUSPEND_OPCODE, 15, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW13_WR_RESUME_OPCODE, 7, 0);
-#define BFPT_1_5_DWORD_13(suspop, resop, wrsspop, wrresop)         \
-	(SFDP_BITFIELD(BFPT_1_5_DW13_SUSPEND_OPCODE, suspop) |     \
-	 SFDP_BITFIELD(BFPT_1_5_DW13_RESUME_OPCODE, resop) |       \
-	 SFDP_BITFIELD(BFPT_1_5_DW13_WR_SUSPEND_OPCODE, wrsspop) | \
-	 SFDP_BITFIELD(BFPT_1_5_DW13_WR_RESUME_OPCODE, wrresop))
-
-/* Basic Flash Parameter Table v1.5 14th DWORD
- * ------------------------------------------
- * <31>    : Deep powerdown unsupported (1 unsupported, 0 supported)
- * <30:23> : Enter deep powerdown instruction
- * <22:15> : Exit deep powerdown instruction
- * <14:13> : Exit deep powerdown to next operation delay units, where
- *           0x0: 128ns, 0x1: 1us, 0x2: 8us, 0x3: 64us
- * <12:8>  : Exit deep powerdown to next operation delay count, where
- *           delay = = (count + 1) * units
- * <7:2>   : Status Register Polling Device Busy Flags, where
- *           xx_xx1xb Bit 7 of the Flag Status Register may be polled any time
- *                    a Program, Erase, Suspend/Resume command is issued, or
- *                    after a Reset command while the device is busy. The read
- *                    instruction is 70h. Flag Status Register bit definitions:
- *                    bit[7]: Program or erase controller status
- *                    (0=busy; 1=ready)
- *           xx_xxx1b Use of legacy polling is supported by reading the Status
- *                    Register with 05h instruction and checking WIP bit[0]
- *                    (0=ready; 1=busy).
- * <1:0>   : Reserved (0x3)
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, 31, 31);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, 30, 23);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, 22, 15);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, 14, 13);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, 12, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, 7, 2);
-#define BFPT_1_5_DWORD_14(pwrdwnunsup, pwrdwnop, pwrupop, pwrupunit, pwrupcnt, \
-			  busypollflags)                                       \
-	(SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED,                   \
-			pwrdwnunsup) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, pwrdwnop) |            \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, pwrupop) |               \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT,                       \
-		       pwrupunit) |                                            \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, pwrupcnt) |            \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, busypollflags) |              \
-	 SFDP_UNUSED(1, 0))
-
-/* Basic Flash Parameter Table v1.5 15th DWORD
- * ------------------------------------------
- * <31:24> : Reserved (0xFF)
- * <23>    : HOLD and WIP disable supported by setting the non-volatile extended
- *           configuration register's bit 4 to 0.
- * <22:20> : Quad Enable Requirements (1-1-4, 1-4-4, 4-4-4 Fast Reads), where
- *           000b Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
- *                reads based on instruction. DQ3/HOLD# functions as hold during
- *                instruction phase.
- *           001b QE is bit 1 of status register 2. It is set via Write Status
- *                with two data bytes where bit 1 of the second byte is one. It
- *                is cleared via Write Status with two data bytes where bit
- *                1 of the second byte is zero. Writing only one byte to the
- *                status register has the side-effect of clearing status
- *                register 2, including the QE bit. The 100b code is used if
- *                writing one byte to the status register does not modify status
- *                register 2.
- *           010b QE is bit 6 of status register 1. It is set via Write Status
- *                with one data byte where bit 6 is one. It is cleared via Write
- *                Status with one data byte where bit 6 is zero.
- *           011b QE is bit 7 of status register 2. It is set via Write status
- *                register 2 instruction 3Eh with one data byte where bit 7 is
- *                one. It is cleared via Write status register 2 instruction
- *                3Eh with one data byte where bit 7 is zero. The status
- *                register 2 is read using instruction 3Fh.
- *           100b QE is bit 1 of status register 2. It is set via Write Status
- *                with two data bytes where bit 1 of the second byte is one. It
- *                is cleared via Write Status with two data bytes where bit 1
- *                of the second byte is zero. In contrast to the 001b code,
- *                writing one byte to the status register does not modify status
- *                register 2.
- *           101b QE is bit 1 of the status register 2. Status register 1 is
- *                read using Read Status instruction 05h. Status register 2 is
- *                read using instruction 35h. QE is set via Write Status
- *                instruction 01h with two data bytes where bit 1 of the second
- *                byte is one. It is cleared via Write Status with two data
- *                bytes where bit 1 of the second byte is zero.
- * <19:16> : 0-4-4 Mode Entry Method, where
- *           xxx1b Mode Bits[7:0] = A5h Note: QE must be set prior to using this
- *                 mode
- *           xx1xb Read the 8-bit volatile configuration register with
- *                 instruction 85h, set XIP bit[3] in the data read, and write
- *                 the modified data using the instruction 81h, then Mode Bits
- *                 [7:0] = 01h
- * <15:10> : 0-4-4 Mode Exit Method, where
- *           xx_xxx1b Mode Bits[7:0] = 00h will terminate this mode at the end
- *                    of the current read operation
- *           xx_xx1xb If 3-Byte address active, input Fh on DQ0-DQ3 for 8
- *                    clocks. If 4-Byte address active, input Fh on DQ0-DQ3 for
- *                    10 clocks. This will terminate the mode prior to the next
- *                    read operation.
- *           xx_1xxxb Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This
- *                    will terminate the mode prior to the next read operation.
- * <9>     : 0-4-4 mode supported (1 supported, 0 unsupported)
- * <8:4>   : 4-4-4 mode enable sequences, where
- *           x_xxx1b set QE per QER description above, then issue
- *                   instruction 38h
- *           x_xx1xb issue instruction 38h
- *           x_x1xxb issue instruction 35h
- *           x_1xxxb device uses a read-modify-write sequence of operations:
- *                   read configuration using instruction 65h followed by
- *                   address 800003h, set bit 6,
- *                   write configuration using instruction 71h followed by
- *                   address 800003h. This configuration is volatile.
- * <3:0>   : 4-4-4 mode disable sequences, where
- *           xxx1b issue FFh instruction
- *           xx1xb issue F5h instruction
- *           x1xxb device uses a read-modify-write sequence of operations:
- *                 read configuration using instruction 65h followed by address
- *                 800003h, clear bit 6,
- *                 write configuration using instruction 71h followed by
- *                 address 800003h. This configuration is volatile.
- *           1xxxb issue the Soft Reset 66/99 sequence
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_HOLD_WP_DISABLE, 23, 23);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_QE_REQ, 22, 20);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_0_4_4_ENTRY, 19, 16);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_0_4_4_EXIT, 15, 10);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_0_4_4_SUPPORTED, 9, 9);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, 8, 4);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, 3, 0);
-#define BFPT_1_5_DWORD_15(holdwpdis, qereq, fr044entry, fr044exit, fr044sup, \
-			  fr444entry, fr444exit)                             \
-	(SFDP_UNUSED(31, 24) |                                               \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_HOLD_WP_DISABLE, holdwpdis) |           \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_QE_REQ, qereq) |                        \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_0_4_4_ENTRY, fr044entry) |              \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_0_4_4_EXIT, fr044exit) |                \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_0_4_4_SUPPORTED, fr044sup) |            \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, fr444entry) |              \
-	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, fr444exit))
-
-
-/* Basic Flash Parameter Table v1.5 16th DWORD
- * -------------------------------------------
- * <31:24> : Enter 4-Byte Addressing, where
- *           xxxx_xxx1b issue instruction B7h
- *                      (preceding write enable not required)
- *           xxxx_xx1xb issue write enable instruction 06h, then issue
- *                      instruction B7h
- *           xxxx_x1xxb 8-bit volatile extended address register used to define
- *                      A[31:24] bits. Read with instruction C8h. Write
- *                      instruction is C5h with 1 byte of data. Select the
- *                      active 128 Mbit memory segment by setting the
- *                      appropriate A[31:24] bits and use 3-Byte addressing.
- *           xxxx_1xxxb 8-bit volatile bank register used to define A[30:A24]
- *                      bits. MSB (bit[7]) is used to enable/disable 4-byte
- *                      address mode. When MSB is set to ‘1’, 4-byte address
- *                      mode is active and A[30:24] bits are don’t care. Read
- *                      with instruction 16h. Write instruction is 17h with 1
- *                      byte of data. When MSB is cleared to ‘0’, select the
- *                      active 128 Mbit segment by setting the appropriate
- *                      A[30:24] bits and use 3-Byte addressing.
- *           xxx1_xxxxb A 16-bit nonvolatile configuration register controls
- *                      3-Byte/4-Byte address mode. Read instruction is B5h.
- *                      Bit[0] controls address mode [0=3-Byte; 1=4-Byte]. Write
- *                      configuration register instruction is B1h, data length
- *                      is 2 bytes.
- *           xx1x_xxxxb Supports dedicated 4-Byte address instruction set.
- *                      Consult vendor data sheet for the instruction set
- *                      definition.
- *           x1xx_xxxxb Always operates in 4-Byte address mode
- * <23:14> : Exit 4-Byte Addressing, where
- *           xx_xxxx_xxx1b issue instruction E9h to exit 4-Byte address mode
- *                         (write enable instruction 06h is not required)
- *           xx_xxxx_xx1xb issue write enable instruction 06h, then issue
- *                         instruction E9h to exit 4-Byte address mode
- *           xx_xxxx_x1xxb 8-bit volatile extended address register used to
- *                         define A[31:A24] bits. Read with instruction C8h.
- *                         Write instruction is C5h, data length is 1 byte.
- *                         Return to lowest memory segment by setting A[31:24]
- *                         to 00h and use 3-Byte addressing.
- *           xx_xxxx_1xxxb 8-bit volatile bank register used to define A[30:A24]
- *                         bits. MSB (bit[7]) is used to enable/disable 4-byte
- *                         address mode. When MSB is cleared to ‘0’, 3-byte
- *                         address mode is active and A30:A24 are used to select
- *                         the active 128 Mbit memory segment. Read with
- *                         instruction 16h. Write instruction is 17h, data
- *                         length is 1 byte.
- *           xx_xxx1_xxxxb A 16-bit nonvolatile configuration register controls
- *                         3-Byte/4-Byte address mode. Read instruction is B5h.
- *                         Bit[0] controls address mode [0=3-Byte; 1=4-Byte].
- *                         Write configuration register instruction is B1h, data
- *                         length is 2 bytes.
- *           xx_xx1x_xxxxb Hardware reset
- *           xx_x1xx_xxxxb Software reset (see bits 13:8 in this DWORD)
- *           xx_1xxx_xxxxb Power cycle
- * <13:8>  : Soft Reset and Rescue Sequence Support, where
- *           00_0000b no software reset instruction is supported
- *           xx_xxx1b drive Fh on all 4 data wires for 8 clocks
- *           xx_xx1xb drive Fh on all 4 data wires for 10 clocks if device is
- *                    operating in 4-byte address mode
- *           xx_x1xxb drive Fh on all 4 data wires for 16 clocks
- *           xx_1xxxb issue instruction F0h
- *           x1_xxxxb issue reset enable instruction 66h, then issue reset
- *                    instruction 99h. The reset enable, reset sequence may be
- *                    issued on 1, 2, or 4 wires depending on the device
- *                    operating mode.
- *           1x_xxxxb exit 0-4-4 mode is required prior to other reset sequences
- *                    above if the device may be operating in this mode.
- * <7>     : Reserved (0x1)
- * <6:0>   : Volatile or Non-Volatile Register and Write Enable Instruction for
- *           Status Register 1, where
- *           xx0_0000b status register is read only
- *           xxx_xxx1b Non-Volatile Status Register 1, powers-up to last written
- *                     value, use instruction 06h to enable write
- *           xxx_xx1xb Volatile Status Register 1, status register powers-up
- *                     with bits set to "1"s, use instruction 06h to enable
- *                     write
- *           xxx_x1xxb Volatile Status Register 1, status register powers-up
- *                     with bits set to "1"s, use instruction 50h to enable
- *                     write
- *           xxx_1xxxb Non-Volatile/Volatile status register 1 powers-up to last
- *                     written value in the non-volatile status register, use
- *                     instruction 06h to enable write to non-volatile status
- *                     register. Volatile status register may be activated after
- *                     power-up to override the non-volatile status register,
- *                     use instruction 50h to enable write and activate the
- *                     volatile status register.
- *           xx1_xxxxb Status Register 1 contains a mix of volatile and
- *                     non-volatile bits. The 06h instruction is used to enable
- *                     writing of the register.
- */
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_4_BYTE_ENTRY, 31, 24);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_4_BYTE_EXIT, 23, 14);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_SOFT_RESET, 13, 8);
-SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, 6, 0);
-#define BFPT_1_5_DWORD_16(entry, exit, softreset, statusreg1) \
-	(SFDP_BITFIELD(BFPT_1_5_DW16_4_BYTE_ENTRY, entry) |   \
-	 SFDP_BITFIELD(BFPT_1_5_DW16_4_BYTE_EXIT, exit) |     \
-	 SFDP_BITFIELD(BFPT_1_5_DW16_SOFT_RESET, softreset) | \
-	 SFDP_UNUSED(7, 7) |                                  \
-	 SFDP_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, statusreg1))
-
-#endif  /* __CROS_EC_SFDP_H */
diff --git a/include/sha1.h b/include/sha1.h
deleted file mode 100644
index 42c0f2612f..0000000000
--- a/include/sha1.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SHA-1 functions */
-
-#ifndef __CROS_EC_SHA1_H
-#define __CROS_EC_SHA1_H
-
-#include "common.h"
-#ifdef HOST_TOOLS_BUILD
-#include <string.h>
-#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y))
-#else
-#include "util.h"
-#endif
-
-#define SHA1_DIGEST_SIZE 20
-#define SHA1_BLOCK_SIZE 64
-
-/* SHA-1 context */
-struct sha1_ctx {
-	uint32_t count;
-	uint32_t state[5];
-	union {
-		uint8_t b[SHA1_BLOCK_SIZE];
-		uint32_t w[DIV_ROUND_UP(SHA1_BLOCK_SIZE, sizeof(uint32_t))];
-	} buf;
-};
-
-void sha1_init(struct sha1_ctx *ctx);
-void sha1_update(struct sha1_ctx *ctx, const uint8_t *data, uint32_t len);
-uint8_t *sha1_final(struct sha1_ctx *ctx);
-
-#endif  /* __CROS_EC_SHA1_H */
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h
deleted file mode 100644
index a0ffefc721..0000000000
--- a/include/spi_flash_reg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * SPI flash protection register translation functions for Chrome OS EC.
- */
-
-#ifndef __CROS_EC_SPI_FLASH_REG_H
-#define __CROS_EC_SPI_FLASH_REG_H
-
-#include "common.h"
-
-/*
- * Common register bits for SPI flash. All registers / bits may not be valid
- * for all parts.
- */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
-/* SR2 register existence based upon chip */
-#ifdef CONFIG_SPI_FLASH_W25X40
-#undef CONFIG_SPI_FLASH_HAS_SR2
-#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B)
-#define CONFIG_SPI_FLASH_HAS_SR2
-#endif
-
-/* W25Q128 16 Mbyte SPI flash for testing */
-#ifdef CONFIG_SPI_FLASH_W25Q128
-#define CONFIG_SPI_FLASH_HAS_SR2
-#endif
-
-/**
- * Computes block write protection range from registers
- * Returns start == len == 0 for no protection
- *
- * @param sr1 Status register 1
- * @param sr2 Status register 2
- * @param start Output pointer for protection start offset
- * @param len Output pointer for protection length
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
-			     unsigned int *len);
-
-/**
- * Computes block write protection registers from range
- *
- * @param start Desired protection start offset
- * @param len Desired protection length
- * @param sr1 Output pointer for status register 1
- * @param sr2 Output pointer for status register 2
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
-			     uint8_t *sr2);
-
-#endif  /* __CROS_EC_SPI_FLASH_REG_H */
diff --git a/include/spi_nor.h b/include/spi_nor.h
deleted file mode 100644
index f0c379cd43..0000000000
--- a/include/spi_nor.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* SPI Serial NOR Flash driver module for Chrome EC */
-
-#ifndef __CROS_EC_SPI_NOR_H
-#define __CROS_EC_SPI_NOR_H
-
-#include "common.h"
-#include "console.h"
-#include "shared_mem.h"
-#include "task.h"
-#include "util.h"
-
-/* Driver compatibility requirements based on JEDEC SFDP support:
- *
- * Parameter     | SFDP v1.(5+)     | SFDP v1.0 | All others
- * ============================================================================
- * Capacity      | N/A              | N/A       | Uses instantiated default
- *               --------------------------------------------------------------
- *               | The capacity must be less than 4GiB for compatibility.
- * ----------------------------------------------------------------------------
- * Page Size     | N/A              | 1B or 64B | Uses instantiated default
- * ----------------------------------------------------------------------------
- * Erase Opcodes | 4KiB Erase with an opcode of 0x20 is always required.
- * ----------------------------------------------------------------------------
- * 4B Addressing | 4B addressing mode must be supported if the part is larger
- *               | than 16MiB. 4B mode entry will be attempted through opcode
- *               | 0xB7 and exit through 0xE9 where writes are enabled for both
- *               | in case it is required
- * ----------------------------------------------------------------------------
- */
-
-/* Boards which use SPI NOR devices must provide enum spi_device indexing all
- * spi_device_t's in the board.h file. */
-enum spi_device;
-
-struct spi_nor_device_t {
-	/* Name of the Serial NOR Flash device. */
-	const char *name;
-
-	/* Index of the SPI controller which this device is connected
-	 * through.
-	 */
-	const enum spi_device spi_controller;
-
-	/* Maximum timeout per command in microseconds. */
-	const uint32_t timeout_usec;
-
-	/* when instantiating this device, the initialization values for the
-	 * following fields will be the default values. Note that the values
-	 * below may change on the fly based on device state and SFDP
-	 * discovery. */
-	uint32_t capacity;
-	size_t page_size;
-	int in_4b_addressing_mode;
-};
-
-extern struct spi_nor_device_t spi_nor_devices[];
-extern const unsigned int spi_nor_devices_used;
-
-/* Industry standard Serial NOR Flash opcodes. All other opcodes are part
- * specific and require SFDP discovery. */
-#define SPI_NOR_OPCODE_WRITE_STATUS  0x01 /* Write Status Register (1 Byte) */
-#define SPI_NOR_OPCODE_PAGE_PROGRAM  0x02 /* Page program */
-#define SPI_NOR_OPCODE_SLOW_READ     0x03 /* Read data (low frequency) */
-#define SPI_NOR_OPCODE_WRITE_DISABLE 0x04
-#define SPI_NOR_OPCODE_READ_STATUS   0x05 /* Read Status Register */
-#define SPI_NOR_OPCODE_WRITE_ENABLE  0x06
-#define SPI_NOR_OPCODE_FAST_READ     0x0b /* Read data (high frequency) */
-#define SPI_NOR_OPCODE_SFDP          0x5a /* Read JEDEC SFDP */
-#define SPI_NOR_OPCODE_JEDEC_ID      0x9f /* Read JEDEC ID */
-#define SPI_NOR_OPCODE_WREAR         0xc5 /* Write extended address register */
-#define SPI_NOR_OPCODE_CHIP_ERASE    0xc7 /* Erase whole flash chip */
-#define SPI_NOR_OPCODE_RDEAR         0xc8 /* Read extended address register */
-
-/* Flags for SPI_NOR_OPCODE_READ_STATUS */
-#define SPI_NOR_STATUS_REGISTER_WIP BIT(0)  /* Write in progres */
-#define SPI_NOR_STATUS_REGISTER_WEL BIT(1)  /* Write enabled latch */
-
-/* If needed in the future this driver can be extended to discover SFDP
- * advertised erase sizes and opcodes for SFDP v1.0+. */
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE  0x20
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8
-
-/* If needed in the future this driver can be extended to discover 4B entry and
- * exit methods for SFDP v1.5+. */
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B  0xe9
-
-/* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */
-#define SPI_NOR_JEDEC_ID_BANKS 12
-
-/**
- * Initialize the module, assumes the Serial NOR Flash devices are currently
- * all available for initialization. As part of the initialization the driver
- * will check if the part has a compatible SFDP Basic Flash Parameter table
- * and update the part's page_size, capacity, and forces the addressing mode.
- * Parts with more than 16MiB of capacity are initialized into 4B addressing
- * and parts with less are initialized into 3B addressing mode.
- *
- * WARNING: This must successfully return before invoking any other Serial NOR
- * Flash APIs.
- */
-int spi_nor_init(void);
-
-/**
- * Forces the Serial NOR Flash device to enter (or exit) 4 Byte addressing mode.
- *
- * WARNING:
- * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
- * 2) If there's a second SPI controller communicating with this Serial
- *    NOR Flash part on the board, the user is responsible for ensuring
- *    addressing mode compatibility and cooperation.
- * 3) The user must ensure that multiple users do not trample on each other
- *    by having multiple parties changing the device's addressing mode.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param enter_4b_addressing_mode Whether to enter (1) or exit (0) 4B mode.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
-			int enter_4b_addressing_mode);
-
-/**
- * Read JEDEC Identifier.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param size Number of Bytes to read.
- * @param data Destination buffer for data.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
-			  size_t size, uint8_t *data);
-
-/**
- * Read from the Serial NOR Flash device.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to read.
- * @param size Number of Bytes to read.
- * @param data Destination buffer for data.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data);
-
-/**
- * Erase flash on the Serial Flash Device.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to erase, must be aligned to the minimum physical
- *               erase size.
- * @param size Number of Bytes to erase, must be a multiple of the the minimum
- *             physical erase size.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
-		  uint32_t offset, size_t size);
-
-/**
- * Write to the Serial NOR Flash device. Assumes already erased.
- *
- * @param spi_nor_device The Serial NOR Flash device to use.
- * @param offset Flash offset to write.
- * @param size Number of Bytes to write.
- * @param data Data to write to flash.
- * @return ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
-		  uint32_t offset, size_t size, const uint8_t *data);
-
-/**
- * Write to the extended address register.
- * @param  spi_nor_device The Serial NOR Flash device to use.
- * @param  value          The value to write.
- * @return                ec_error_list (non-zero on error and timeout).
- */
-int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
-		      const uint8_t value);
-
-
-#endif  /* __CROS_EC_SPI_NOR_H */
diff --git a/include/stillness_detector.h b/include/stillness_detector.h
deleted file mode 100644
index 65598d4d5c..0000000000
--- a/include/stillness_detector.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_STILLNESS_DETECTOR_H
-#define __CROS_EC_STILLNESS_DETECTOR_H
-
-#include "common.h"
-#include "math_util.h"
-#include "stdbool.h"
-#include <stdint.h>
-
-struct still_det {
-	/** Variance threshold for the stillness confidence score. [units]^2 */
-	fp_t var_threshold;
-
-	/** The minimum window duration to consider a still sample. */
-	uint32_t min_batch_window;
-
-	/** The maximum window duration to consider a still sample. */
-	uint32_t max_batch_window;
-
-	/**
-	 * The minimum number of samples in a window to consider a still sample.
-	 */
-	uint16_t min_batch_size;
-
-	/** The timestamp of the first sample in the current batch. */
-	uint32_t window_start_time;
-
-	/** The number of samples in the current batch. */
-	uint16_t num_samples;
-
-	/** Accumulators used for calculating stillness. */
-	fp_t acc_x, acc_y, acc_z, acc_xx, acc_yy, acc_zz, mean_x, mean_y,
-		mean_z;
-};
-
-#define STILL_DET(VAR_THRES, MIN_BATCH_WIN, MAX_BATCH_WIN, MIN_BATCH_SIZE) \
-	((struct still_det){                                               \
-		.var_threshold = VAR_THRES,                                \
-		.min_batch_window = MIN_BATCH_WIN,                         \
-		.max_batch_window = MAX_BATCH_WIN,                         \
-		.min_batch_size = MIN_BATCH_SIZE,                          \
-		.window_start_time = 0,                                    \
-		.acc_x = 0.0f,                                             \
-		.acc_y = 0.0f,                                             \
-		.acc_z = 0.0f,                                             \
-		.acc_xx = 0.0f,                                            \
-		.acc_yy = 0.0f,                                            \
-		.acc_zz = 0.0f,                                            \
-		.mean_x = 0.0f,                                            \
-		.mean_y = 0.0f,                                            \
-		.mean_z = 0.0f,                                            \
-	})
-
-/**
- * Update a stillness detector with a new sample.
- *
- * @param sample_time The timestamp of the sample to add.
- * @param x The x component of the sample to add.
- * @param y The y component of the sample to add.
- * @param z The z component of the sample to add.
- * @return True if the sample triggered a complete batch and mean_* are now
- *         valid.
- */
-bool still_det_update(struct still_det *still_det, uint32_t sample_time, fp_t x,
-		      fp_t y, fp_t z);
-
-#endif /* __CROS_EC_STILLNESS_DETECTOR_H */
diff --git a/include/switch.h b/include/switch.h
deleted file mode 100644
index e026408af9..0000000000
--- a/include/switch.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Switch module for Chrome EC */
-
-#ifndef __CROS_EC_SWITCH_H
-#define __CROS_EC_SWITCH_H
-
-#include "common.h"
-#include "gpio.h"
-
-#ifdef CONFIG_SWITCH
-/**
- * Interrupt handler for switch inputs.
- *
- * @param signal	Signal which triggered the interrupt.
- */
-void switch_interrupt(enum gpio_signal signal);
-#else
-static inline void switch_interrupt(enum gpio_signal signal) { }
-#endif  /* !CONFIG_SWITCH */
-
-#endif  /* __CROS_EC_SWITCH_H */
diff --git a/include/temp_sensor.h b/include/temp_sensor.h
deleted file mode 100644
index 50a174193f..0000000000
--- a/include/temp_sensor.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for Chrome EC */
-
-#ifndef __CROS_EC_TEMP_SENSOR_H
-#define __CROS_EC_TEMP_SENSOR_H
-
-#include "common.h"
-
-/* "enum temp_sensor_id" must be defined for each board in board.h. */
-enum temp_sensor_id;
-
-/* Type of temperature sensors. */
-enum temp_sensor_type {
-	/* Ignore this temperature sensor. */
-	TEMP_SENSOR_TYPE_IGNORED = -1,
-	/* CPU temperature sensors. */
-	TEMP_SENSOR_TYPE_CPU = 0,
-	/* Other on-board temperature sensors. */
-	TEMP_SENSOR_TYPE_BOARD,
-	/* Case temperature sensors. */
-	TEMP_SENSOR_TYPE_CASE,
-	/* Battery temperature sensors. */
-	TEMP_SENSOR_TYPE_BATTERY,
-
-	TEMP_SENSOR_TYPE_COUNT
-};
-
-struct temp_sensor_t {
-	const char *name;
-	/* Temperature sensor type. */
-	enum temp_sensor_type type;
-	/*
-	 * TODO(b:201081891) Refactor temp_sensor_t references
-	 * to all use OO style sensor argument to get adc idx.
-	 */
-#ifdef CONFIG_ZEPHYR
-	/* Read sensor value in K into temp_ptr; return non-zero if error. */
-	int (*read)(const struct temp_sensor_t *sensor, int *temp_ptr);
-	struct thermistor_info *thermistor;
-#else
-	/* Read sensor value in K into temp_ptr; return non-zero if error. */
-	int (*read)(int idx, int *temp_ptr);
-#endif
-	/* Index among the same kind of sensors. */
-	int idx;
-};
-
-#ifdef CONFIG_TEMP_SENSOR
-/*
- * Defined in board_temp_sensor.c. Must be in the same order as
- * in enum temp_sensor_id.
- */
-extern const struct temp_sensor_t temp_sensors[];
-#endif
-
-/**
- * Get the most recently measured temperature (in degrees K) for the sensor.
- *
- * @param id		Sensor ID
- * @param temp_ptr	Destination for temperature
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr);
-
-/**
- * Console command to print temperature sensor values
- *
- * @param argc		argument count (Set argc = 1)
- * @param argv		argument vector (Set argv = NULL)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int console_command_temps(int argc, char **argv);
-
-#endif  /* __CROS_EC_TEMP_SENSOR_H */
diff --git a/include/temp_sensor_chip.h b/include/temp_sensor_chip.h
deleted file mode 100644
index 4f9ddf0bc0..0000000000
--- a/include/temp_sensor_chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Temperature sensor module for LM4 chip */
-
-#ifndef __CROS_EC_TEMP_SENSOR_CHIP_H
-#define __CROS_EC_TEMP_SENSOR_CHIP_H
-
-/**
- * Get the last polled value of the sensor.
- *
- * @param idx		Sensor index to read.
- * @param temp_ptr	Destination for temperature in K.
- *
- * @return EC_SUCCESS if successful, non-zero if error.
- */
-int chip_temp_sensor_get_val(int idx, int *temp_ptr);
-
-#endif /* __CROS_EC_TEMP_SENSOR_CHIP_H */
diff --git a/include/tests/enum_strings.h b/include/tests/enum_strings.h
deleted file mode 100644
index ece2df362f..0000000000
--- a/include/tests/enum_strings.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Defines helper function that convert Enums to strings for prints in tests */
-
-#include "usb_pd_tcpm.h"
-#include "usb_pd.h"
-
-#ifndef __CROS_EC_TEST_ENUM_STINGS_H
-#define __CROS_EC_TEST_ENUM_STINGS_H
-
-#ifndef TEST_BUILD
-#error enum_strings.h can only be used in test builds
-#endif
-
-static inline const char *from_tcpc_rp_value(enum tcpc_rp_value value)
-{
-	switch (value) {
-	case TYPEC_RP_USB:
-		return "USB-DEFAULT";
-	case TYPEC_RP_1A5:
-		return "1A5";
-	case TYPEC_RP_3A0:
-		return "3A0";
-	case TYPEC_RP_RESERVED:
-		return "RESERVED";
-	default:
-		return "UNKNOWN";
-	}
-}
-
-static inline const char *from_tcpc_cc_pull(enum tcpc_cc_pull value)
-{
-	switch (value) {
-	case TYPEC_CC_RA:
-		return "RA";
-	case TYPEC_CC_RP:
-		return "RP";
-	case TYPEC_CC_RD:
-		return "RD";
-	case TYPEC_CC_OPEN:
-		return "OPEN";
-	case TYPEC_CC_RA_RD:
-		return "RA_RD";
-	default:
-		return "UNKNOWN";
-	}
-}
-
-static inline const char *from_tcpc_cc_polarity(enum tcpc_cc_polarity value)
-{
-	switch (value) {
-	case POLARITY_CC1:
-		return "CC1";
-	case POLARITY_CC2:
-		return "CC2";
-	case POLARITY_CC1_DTS:
-		return "CC1 DTS";
-	case POLARITY_CC2_DTS:
-		return "CC2 DTS";
-	default:
-		return "UNKNOWN";
-	}
-}
-
-static inline const char *from_pd_power_role(enum pd_power_role value)
-{
-	switch (value) {
-	case PD_ROLE_SINK:
-		return "SNK";
-	case PD_ROLE_SOURCE:
-		return "SRC";
-	default:
-		return "UNKNOWN";
-	}
-}
-
-static inline const char *from_pd_data_role(enum pd_data_role value)
-{
-	switch (value) {
-	case PD_ROLE_UFP:
-		return "UFP";
-	case PD_ROLE_DFP:
-		return "DRP";
-	case PD_ROLE_DISCONNECTED:
-		return "DISCONNECTED";
-	default:
-		return "UNKNOWN";
-	}
-}
-
-#endif /* __CROS_EC_TEST_ENUM_STINGS_H */
diff --git a/include/thermal.h b/include/thermal.h
deleted file mode 100644
index 29d8073ca0..0000000000
--- a/include/thermal.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Thermal engine module for Chrome EC */
-
-#ifndef __CROS_EC_THERMAL_H
-#define __CROS_EC_THERMAL_H
-
-/* The thermal configuration for a single temp sensor is defined here. */
-#include "ec_commands.h"
-
-/* We need to to hold a config for each board's sensors. Not const, so we can
- * tweak it at run-time if we have to.
- */
-extern struct ec_thermal_config thermal_params[];
-
-/* Helper function to compute percent cooling */
-int thermal_fan_percent(int low, int high, int cur);
-
-/* Allow board custom fan control. Called after reading temperature sensors.
- *
- * @param fan Fan ID to control (0 to CONFIG_FANS)
- * @param tmp Array of temperatures (C) for each temperature sensor (size
- *            TEMP_SENSOR_COUNT)
- */
-void board_override_fan_control(int fan, int *tmp);
-
-#endif  /* __CROS_EC_THERMAL_H */
diff --git a/include/throttle_ap.h b/include/throttle_ap.h
deleted file mode 100644
index fbfa36aed3..0000000000
--- a/include/throttle_ap.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common interface to throttle the AP */
-
-#ifndef __CROS_EC_THROTTLE_AP_H
-#define __CROS_EC_THROTTLE_AP_H
-
-/**
- * Level of throttling desired.
- */
-enum throttle_level {
-	THROTTLE_OFF = 0,
-	THROTTLE_ON,
-};
-
-/**
- * Types of throttling desired. These are independent.
- */
-enum throttle_type {
-	THROTTLE_SOFT = 0,			/* for example, host events */
-	THROTTLE_HARD,				/* for example, PROCHOT */
-	NUM_THROTTLE_TYPES
-};
-
-/**
- * Possible sources for CPU throttling requests.
- */
-enum throttle_sources {
-	THROTTLE_SRC_THERMAL = 0,
-	THROTTLE_SRC_BAT_DISCHG_CURRENT,
-	THROTTLE_SRC_BAT_VOLTAGE,
-};
-
-/**
- * Enable/disable CPU throttling.
- *
- * This is a virtual "OR" operation. Any caller can enable CPU throttling of
- * any type, but all callers must agree in order to disable that type.
- *
- * @param level         Level of throttling desired
- * @param type          Type of throttling desired
- * @param source        Which task is requesting throttling
- */
-#if defined(CONFIG_THROTTLE_AP) || \
-	defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \
-	defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE)
-
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
-		 enum throttle_sources source);
-
-/**
- * Interrupt handler to monitor PROCHOT input to the EC. The PROCHOT signal
- * can be asserted by the AP or by other devices on the board, such as chargers
- * and voltage regulators.
- *
- * The board initialization is responsible for enabling the interrupt.
- *
- * @param signal    GPIO signal connected to PROCHOT input. The polarity of this
- *                  signal is active high unless CONFIG_CPU_PROCHOT_ACTIVE_LOW
- *                  is defined.
- */
-void throttle_ap_prochot_input_interrupt(enum gpio_signal signal);
-
-#else
-static inline void throttle_ap(enum throttle_level level,
-			       enum throttle_type type,
-			       enum throttle_sources source)
-{}
-#endif
-
-#endif	/* __CROS_EC_THROTTLE_AP_H */
diff --git a/include/touchpad.h b/include/touchpad.h
deleted file mode 100644
index 4e746d8dc1..0000000000
--- a/include/touchpad.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_TOUCHPAD_H
-#define __CROS_EC_TOUCHPAD_H
-
-void touchpad_interrupt(enum gpio_signal signal);
-
-/* Reset the touchpad, mainly used to recover it from malfunction. */
-void board_touchpad_reset(void);
-
-#endif
diff --git a/include/trng.h b/include/trng.h
deleted file mode 100644
index cea4555b41..0000000000
--- a/include/trng.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EC_INCLUDE_TRNG_H
-#define __EC_INCLUDE_TRNG_H
-
-#include <common.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/**
- * Initialize the true random number generator.
- *
- * Not supported by all platforms.
- **/
-void init_trng(void);
-
-/**
- * Shutdown the true random number generator.
- *
- * The opposite operation of init_trng(), disable the hardware resources
- * used by the TRNG to save power.
- *
- * Not supported by all platforms.
- **/
-void exit_trng(void);
-
-/**
- * Retrieve a 32 bit random value.
- *
- * Not supported on all platforms.
- **/
-#ifndef HIDE_EC_STDLIB
-uint32_t rand(void);
-#endif
-
-/**
- * Output len random bytes into buffer.
- *
- * Not supported on all platforms.
- **/
-void rand_bytes(void *buffer, size_t len);
-
-#endif /* __EC_INCLUDE_TRNG_H */
diff --git a/include/update_fw.h b/include/update_fw.h
deleted file mode 100644
index d345c4f667..0000000000
--- a/include/update_fw.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_UPDATE_FW_H
-#define __CROS_EC_UPDATE_FW_H
-
-#include <stddef.h>
-
-#include "compile_time_macros.h"
-
-/*
- * This file contains structures used to facilitate EC firmware updates
- * over USB (and over TPM for cr50).
- *
- * The firmware update protocol consists of two phases: connection
- * establishment and actual image transfer.
- *
- * Image transfer is done in 1K blocks. The host supplying the image
- * encapsulates blocks in PDUs by prepending a header including the flash
- * offset where the block is destined and its digest.
- *
- * The EC device responds to each PDU with a confirmation which is 1 byte
- * response. Zero value means success, non zero value is the error code
- * reported by EC.
- *
- * To establish the connection, the host sends a different PDU, which
- * contains no data and is destined to offset 0. Receiving such a PDU
- * signals the EC that the host intends to transfer a new image.
- *
- * The connection establishment response is described by the
- * first_response_pdu structure below.
- */
-
-#define UPDATE_PROTOCOL_VERSION 6
-
-/*
- * This is the format of the update PDU header.
- *
- * block digest: the first four bytes of the sha1 digest of the rest of the
- *               structure (can be 0 on boards where digest is ignored).
- * block_base:   offset of this PDU into the flash SPI.
- */
-struct update_command {
-	uint32_t  block_digest;
-	uint32_t  block_base;
-	/* The actual payload goes here. */
-} __packed;
-
-/*
- * This is the frame format the host uses when sending update PDUs over USB.
- *
- * The PDUs are up to 1K bytes in size, they are fragmented into USB chunks of
- * 64 bytes each and reassembled on the receive side before being passed to
- * the flash update function.
- *
- * The flash update function receives the unframed PDU body (starting at the
- * cmd field below), and puts its reply into the same buffer the PDU was in.
- */
-struct update_frame_header {
-	uint32_t block_size; /* Total frame size, including this field. */
-	struct update_command cmd;
-};
-
-/*
- * A convenience structure which allows to group together various revision
- * fields of the header created by the signer (cr50-specific).
- *
- * These fields are compared when deciding if versions of two images are the
- * same or when deciding which one of the available images to run.
- */
-struct signed_header_version {
-	uint32_t minor;
-	uint32_t major;
-	uint32_t epoch;
-};
-
-/*
- * Response to the connection establishment request.
- *
- * When responding to the very first packet of the update sequence, the
- * original USB update implementation was responding with a four byte value,
- * just as to any other block of the transfer sequence.
- *
- * It became clear that there is a need to be able to enhance the update
- * protocol, while staying backwards compatible.
- *
- * All newer protocol versions (starting with version 2) respond to the very
- * first packet with an 8 byte or larger response, where the first 4 bytes are
- * a version specific data, and the second 4 bytes - the protocol version
- * number.
- *
- * This way the host receiving of a four byte value in response to the first
- * packet is considered an indication of the target running the 'legacy'
- * protocol, version 1. Receiving of an 8 byte or longer response would
- * communicates the protocol version in the second 4 bytes.
- */
-struct first_response_pdu {
-	uint32_t return_value;
-
-	/* The below fields are present in versions 2 and up. */
-
-	/* Type of header following (one of first_response_pdu_header_type) */
-	uint16_t header_type;
-
-	/* Must be UPDATE_PROTOCOL_VERSION */
-	uint16_t protocol_version;
-
-	/* In version 6 and up, a board-specific header follows. */
-	union {
-		/* cr50 (header_type = UPDATE_HEADER_TYPE_CR50) */
-		struct {
-			/* The below fields are present in versions 3 and up. */
-			uint32_t  backup_ro_offset;
-			uint32_t  backup_rw_offset;
-
-			/* The below fields are present in versions 4 and up. */
-			/*
-			 * Versions of the currently active RO and RW sections.
-			 */
-			struct signed_header_version shv[2];
-
-			/* The below fields are present in versions 5 and up */
-			/* keyids of the currently active RO and RW sections. */
-			uint32_t keyid[2];
-		} cr50;
-		/* Common code (header_type = UPDATE_HEADER_TYPE_COMMON) */
-		struct {
-			/* Maximum PDU size */
-			uint32_t maximum_pdu_size;
-
-			/* Flash protection status */
-			uint32_t flash_protection;
-
-			/* Offset of the other region */
-			uint32_t offset;
-
-			/* Version string of the other region */
-			char version[32];
-
-			/* Minimum rollback version that RO will accept */
-			int32_t min_rollback;
-
-			/* RO public key version */
-			uint32_t key_version;
-		} common;
-	};
-};
-
-enum first_response_pdu_header_type {
-	UPDATE_HEADER_TYPE_CR50 = 0, /* Must be 0 for backwards compatibility */
-	UPDATE_HEADER_TYPE_COMMON = 1,
-};
-
-/* TODO: Handle this in update_fw.c, not usb_update.c */
-#define UPDATE_DONE          0xB007AB1E
-#define UPDATE_EXTRA_CMD     0xB007AB1F
-
-enum update_extra_command {
-	UPDATE_EXTRA_CMD_IMMEDIATE_RESET = 0,
-	UPDATE_EXTRA_CMD_JUMP_TO_RW = 1,
-	UPDATE_EXTRA_CMD_STAY_IN_RO = 2,
-	UPDATE_EXTRA_CMD_UNLOCK_RW = 3,
-	UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK = 4,
-	UPDATE_EXTRA_CMD_INJECT_ENTROPY = 5,
-	UPDATE_EXTRA_CMD_PAIR_CHALLENGE = 6,
-	UPDATE_EXTRA_CMD_TOUCHPAD_INFO = 7,
-	UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG = 8,
-	UPDATE_EXTRA_CMD_CONSOLE_READ_INIT = 9,
-	UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT = 10,
-};
-
-/*
- * Pair challenge (from host), note that the packet, with header, must fit
- * in a single USB packet (64 bytes), so its maximum length is 50 bytes.
- */
-struct pair_challenge {
-	uint8_t host_public[32]; /* X22519 public key from host */
-	uint8_t nonce[16]; /* nonce to be used for HMAC */
-};
-
-/*
- * Pair challenge response (from device).
- */
-struct pair_challenge_response {
-	uint8_t status; /* = EC_RES_SUCCESS */
-	uint8_t device_public[32]; /* X22519 device public key of device */
-	/*
-	 * Truncated output of
-	 * HMAC_SHA256(x25519(device_private, host_public), nonce)
-	 */
-	uint8_t authenticator[16];
-} __packed;
-
-struct touchpad_info {
-	uint8_t status; /* = EC_RES_SUCCESS */
-	uint8_t reserved; /* padding */
-	uint16_t vendor; /* Vendor USB id */
-
-	/*
-	 * Virtual address to write to to update TP FW over USB update protocol,
-	 * and FW size. Both are 0 if unsupported.
-	 */
-	uint32_t fw_address;
-	uint32_t fw_size;
-
-	/*
-	 * SHA256 hash of the trackpad FW accepted by this EC image.
-	 * This is used by the updater to make sure we do not attempt to flash
-	 * a touchpad FW that does not match the one shipped by the EC.
-	 */
-	uint8_t allowed_fw_hash[32];
-
-	/* Vendor specific data. */
-	union {
-		struct {
-			uint16_t id;
-			uint16_t fw_version;
-			uint16_t fw_checksum;
-		} elan __packed;
-		struct {
-			uint16_t id;
-			uint16_t fw_version;
-			uint16_t fw_checksum;
-		} st __packed;
-	} __packed;
-} __packed;
-
-/*
- * The response message must not exceed 64 bytes.
- * And our protocol has a 14 bytes header.
- * So the size of `struct touchpad_info` must be less
- * than or equal to 50 bytes
- */
-BUILD_ASSERT(sizeof(struct touchpad_info) <= 50);
-
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
-			       size_t *response_size);
-
-/* Used to tell fw update the update ran successfully and is finished */
-void fw_update_complete(void);
-
-/* Verify integrity of the PDU received. */
-int update_pdu_valid(struct update_command *cmd_body, size_t cmd_size);
-
-/* Various update command return values. */
-enum {
-	UPDATE_SUCCESS = 0,
-	UPDATE_BAD_ADDR = 1,
-	UPDATE_ERASE_FAILURE = 2,
-	UPDATE_DATA_ERROR = 3,
-	UPDATE_WRITE_FAILURE = 4,
-	UPDATE_VERIFY_ERROR = 5,
-	UPDATE_GEN_ERROR = 6,
-	UPDATE_MALLOC_ERROR = 7,
-	UPDATE_ROLLBACK_ERROR = 8,
-	UPDATE_RATE_LIMIT_ERROR = 9,
-	UPDATE_RWSIG_BUSY = 10,
-};
-
-/* Obtain touchpad information */
-int touchpad_get_info(struct touchpad_info *tp);
-
-/* Touchpad FW update: Write a FW block. */
-int touchpad_update_write(int offset, int size, const uint8_t *data);
-
-/**
- * Touchpad debugging interface, called whenever UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG
- * is received. Behaviour is touchpad-vendor dependent, with the following
- * restrictions: data must be allocated statically, and must not be larger than
- * 64 bytes.
- *
- * @param param        Data passed as parameter to command.
- * @param param_size   Number of bytes passed as parameter.
- * @param data         Data to write back to host, needs to be allocated
- *                     statically by touchpad handler.
- * @param data_size    Amount of data to write back to host (up to 64 bytes).
- *
- * @return EC_RES_SUCCESS on success, any other EC_RES_* status on error.
- */
-int touchpad_debug(const uint8_t *param, unsigned int param_size,
-		   uint8_t **data, unsigned int *data_size);
-
-/* SHA256 hash of the touchpad firmware expected by this image. */
-extern const uint8_t touchpad_fw_full_hash[32];
-
-#endif  /* ! __CROS_EC_UPDATE_FW_H */
diff --git a/include/usb_api.h b/include/usb_api.h
deleted file mode 100644
index 79ee9406e9..0000000000
--- a/include/usb_api.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB API definitions.
- *
- * This file includes definitions needed by common code that wants to control
- * the state of the USB peripheral, but doesn't need to know about the specific
- * implementation.
- */
-
-#ifndef __CROS_EC_USB_API_H
-#define __CROS_EC_USB_API_H
-
-/*
- * Initialize the USB peripheral, enabling its clock and configuring the DP/DN
- * GPIOs correctly.  This function is called via an init hook (unless the board
- * defined CONFIG_USB_INHIBIT_INIT), but may need to be called again if
- * usb_release is called.  This function will call usb_connect by default
- * unless CONFIG_USB_INHIBIT_CONNECT is defined.
- */
-void usb_init(void);
-
-/* Check if USB peripheral is enabled. */
-int usb_is_enabled(void);
-
-/*
- * Enable the pullup on the DP line to signal that this device exists to the
- * host and to start the enumeration process.
- */
-void usb_connect(void);
-
-/*
- * Disable the pullup on the DP line.  This causes the device to be disconnected
- * from the host.
- */
-void usb_disconnect(void);
-
-/*
- * Disconnect from the host by calling usb_disconnect and then turn off the USB
- * peripheral, releasing its GPIOs and disabling its clock.
- */
-void usb_release(void);
-
-/*
- * Returns true if USB device is currently suspended.
- * Requires CONFIG_USB_SUSPEND to be defined.
- */
-int usb_is_suspended(void);
-
-/*
- * Returns true if USB remote wakeup is currently enabled by host.
- * Requires CONFIG_USB_SUSPEND to be defined, always return 0 if
- * CONFIG_USB_REMOTE_WAKEUP is not defined.
- */
-int usb_is_remote_wakeup_enabled(void);
-
-/*
- * Preserve in non-volatile memory the state of the USB hardware registers
- * which cannot be simply re-initialized when powered up again.
- */
-void usb_save_suspended_state(void);
-
-/*
- * Restore from non-volatile memory the state of the USB hardware registers
- * which was lost by powering them down.
- */
-void usb_restore_suspended_state(void);
-
-/*
- * Tell the host to wake up. Does nothing if CONFIG_USB_REMOTE_WAKEUP is not
- * defined.
- *
- * Returns immediately, suspend status can be checked using usb_is_suspended.
- */
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-void usb_wake(void);
-#else
-static inline void usb_wake(void) {}
-#endif
-
-/* Board-specific USB wake, for side-band wake, called by usb_wake above. */
-void board_usb_wake(void);
-
-#endif /* __CROS_EC_USB_API_H */
diff --git a/include/usb_bb.h b/include/usb_bb.h
deleted file mode 100644
index 24225250be..0000000000
--- a/include/usb_bb.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB billboard definitions.
- */
-
-#ifndef __CROS_EC_USB_BB_H
-#define __CROS_EC_USB_BB_H
-
-/* per Billboard Device Class Spec Revision 1.0 */
-
-/* device descriptor fields */
-#define USB_BB_BCDUSB_MIN 0x0201 /* v2.01 minimum */
-#define USB_BB_SUBCLASS 0x00
-#define USB_BB_PROTOCOL 0x00
-#define USB_BB_EP0_PACKET_SIZE 8
-#define USB_BB_CAP_DESC_TYPE 0x0d
-
-
-#define USB_BB_CAPS_SVID_SIZE 4
-struct usb_bb_caps_svid_descriptor {
-	uint16_t wSVID;
-	uint8_t bAlternateMode;
-	uint8_t iAlternateModeString;
-} __packed;
-
-#define USB_BB_CAPS_BASE_SIZE 44
-struct usb_bb_caps_base_descriptor {
-	uint8_t bLength;
-	uint8_t bDescriptorType;
-	uint8_t bDevCapabilityType;
-	uint8_t iAdditionalInfoURL;
-	uint8_t bNumberOfAlternateModes;
-	uint8_t bPreferredAlternateMode;
-	uint16_t VconnPower;
-	uint8_t bmConfigured[32]; /* 2b per SVID w/ 128 SVIDs allowed. */
-	uint32_t bReserved; /* SBZ */
-} __packed;
-
-
-#define USB_BB_VCONN_PWRON(x)    (x << 15)
-#define USB_BB_VCONN_PWR_1W      0
-#define USB_BB_VCONN_PWR_1p5W    1
-#define USB_BB_VCONN_PWR_2W      2
-#define USB_BB_VCONN_PWR_3W      3
-#define USB_BB_VCONN_PWR_4W      4
-#define USB_BB_VCONN_PWR_5W      5
-#define USB_BB_VCONN_PWR_6W      6
-/* Note, 7W (111b) is reserved */
-
-
-#endif /* __CROS_EC_USB_BB_H */
-
diff --git a/include/usb_charge.h b/include/usb_charge.h
deleted file mode 100644
index 0dc009721e..0000000000
--- a/include/usb_charge.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB charging control module for Chrome EC */
-
-#ifndef __CROS_EC_USB_CHARGE_H
-#define __CROS_EC_USB_CHARGE_H
-
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "task.h"
-
-/* USB charger voltage */
-#define USB_CHARGER_VOLTAGE_MV  5000
-/* USB charger minimum current */
-#define USB_CHARGER_MIN_CURR_MA 500
-/*
- * USB charger maximum current
- *
- * The USB Type-C specification limits the maximum amount of current from BC 1.2
- * suppliers to 1.5A.  Technically, proprietary methods are not allowed, but we
- * will continue to allow those.
- */
-#define USB_CHARGER_MAX_CURR_MA 1500
-
-#define USB_SYSJUMP_TAG 0x5550 /* "UP" - Usb Port */
-#define USB_HOOK_VERSION 1
-
-#ifdef CONFIG_USB_PORT_POWER_SMART
-#define USB_PORT_ENABLE_COUNT CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-#elif defined(CONFIG_USB_PORT_POWER_DUMB)
-#define USB_PORT_ENABLE_COUNT USB_PORT_COUNT
-#endif
-
-/* GPIOs to enable/disable USB ports. Board specific. */
-#ifdef USB_PORT_ENABLE_COUNT
-#ifdef CONFIG_USB_PORT_ENABLE_DYNAMIC
-extern int usb_port_enable[USB_PORT_ENABLE_COUNT];
-#else
-extern const int usb_port_enable[USB_PORT_ENABLE_COUNT];
-#endif
-#endif /* USB_PORT_ENABLE_COUNT */
-
-/**
- * Set USB charge mode for the port.
- *
- * @param usb_port_id		Port to set.
- * @param mode			New mode for port.
- * @param inhibit_charge	Inhibit charging during system suspend.
- * @return EC_SUCCESS, or non-zero if error.
- */
-int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode,
-			enum usb_suspend_charge inhibit_charge);
-
-#define USB_CHG_EVENT_BC12	TASK_EVENT_CUSTOM_BIT(0)
-#define USB_CHG_EVENT_VBUS	TASK_EVENT_CUSTOM_BIT(1)
-#define USB_CHG_EVENT_INTR	TASK_EVENT_CUSTOM_BIT(2)
-#define USB_CHG_EVENT_DR_UFP	TASK_EVENT_CUSTOM_BIT(3)
-#define USB_CHG_EVENT_DR_DFP	TASK_EVENT_CUSTOM_BIT(4)
-#define USB_CHG_EVENT_CC_OPEN	TASK_EVENT_CUSTOM_BIT(5)
-#define USB_CHG_EVENT_MUX	TASK_EVENT_CUSTOM_BIT(6)
-
-/* Number of USB_CHG_* tasks */
-#ifdef HAS_TASK_USB_CHG_P2
-#define USB_CHG_TASK_COUNT 3
-#elif defined(HAS_TASK_USB_CHG_P1)
-#define USB_CHG_TASK_COUNT 2
-#elif defined(HAS_TASK_USB_CHG_P0) || defined(HAS_TASK_USB_CHG)
-#define USB_CHG_TASK_COUNT 1
-#else
-#define USB_CHG_TASK_COUNT 0
-#endif
-
-/*
- * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG__PORT() macros to
- * go between USB_CHG port number and task ID. Assume that TASK_ID_USB_CHG_P0,
- * is the lowest task ID and IDs are on a continuous range.
- */
-#ifdef HAS_TASK_USB_CHG_P0
-#define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port))
-#define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0)
-#else
-#define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */
-#define TASK_ID_TO_USB_CHG_PORT(id) 0
-#endif  /* HAS_TASK_USB_CHG_P0 */
-
-/**
- * Returns true if the passed port is a power source.
- *
- * @param port  Port number.
- * @return      True if port is sourcing vbus.
- */
-int usb_charger_port_is_sourcing_vbus(int port);
-
-enum usb_switch {
-	USB_SWITCH_CONNECT,
-	USB_SWITCH_DISCONNECT,
-	USB_SWITCH_RESTORE,
-};
-
-struct bc12_drv {
-	/* All fields below are optional */
-
-	/* BC1.2 detection task for this chip */
-	void (*usb_charger_task)(int port);
-	/* Configure USB data switches on type-C port */
-	void (*set_switches)(int port, enum usb_switch setting);
-	/* Check if ramping is allowed for given supplier */
-	int (*ramp_allowed)(int supplier);
-	/* Get the maximum current limit that we are allowed to ramp to */
-	int (*ramp_max)(int supplier, int sup_curr);
-};
-
-struct bc12_config {
-	const struct bc12_drv *drv;
-};
-/**
- * An array of length CHARGE_PORT_COUNT which associates each
- * pd port / dedicated charge port to bc12 driver.
- *
- * If CONFIG_BC12_SINGLE_DRIVER is defined, bc12 driver will provide a
- * definition of this array. Otherwise, board should define this by themselves.
- */
-extern struct bc12_config bc12_ports[];
-
-/**
- * Configure USB data switches on type-C port.
- *
- * @param port port number.
- * @param setting new switch setting to configure.
- */
-static inline void usb_charger_set_switches(int port, enum usb_switch setting)
-{
-	if (bc12_ports[port].drv->set_switches)
-		bc12_ports[port].drv->set_switches(port, setting);
-}
-
-/**
- * Notify USB_CHG task that VBUS level has changed.
- *
- * @param port port number.
- * @param vbus_level new VBUS level
- */
-void usb_charger_vbus_change(int port, int vbus_level);
-
-/**
- * Check if ramping is allowed for given supplier
- *
- * @param port port number.
- * @supplier Supplier to check
- *
- * @return Ramping is allowed for given supplier
- */
-static inline int usb_charger_ramp_allowed(int port, int supplier)
-{
-	if (port < 0 || !bc12_ports[port].drv->ramp_allowed)
-		return 0;
-	return bc12_ports[port].drv->ramp_allowed(supplier);
-}
-
-/**
- * Get the maximum current limit that we are allowed to ramp to
- *
- * @param port port number.
- * @supplier Active supplier type
- * @sup_curr Input current limit based on supplier
- *
- * @return Maximum current in mA
- */
-static inline int usb_charger_ramp_max(int port, int supplier, int sup_curr)
-{
-	if (port < 0 || !bc12_ports[port].drv->ramp_max)
-		return 0;
-	return bc12_ports[port].drv->ramp_max(supplier, sup_curr);
-}
-
-/**
- * Reset available BC 1.2 chargers on all ports
- * @param port
- */
-void usb_charger_reset_charge(int port);
-
-/**
- * Check if a particular port is sourcing VBUS
- *
- * This function is typically defined in the board file
- *
- * @param port port number
- * @return 0 if not source, non-zero if sourcing
- */
-int board_is_sourcing_vbus(int port);
-
-/**
- * Enable VBUS sink for a given port
- *
- * This function is typically defined in the board file
- *
- * @param port port number
- * @param enable 0 to disable, 1 to enable
- * @return EC_SUCCESS if OK, EC_ERROR_INVAL if @port is invalid
- */
-int board_vbus_sink_enable(int port, int enable);
-
-#endif  /* __CROS_EC_USB_CHARGE_H */
diff --git a/include/usb_common.h b/include/usb_common.h
deleted file mode 100644
index 5fc215798f..0000000000
--- a/include/usb_common.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_COMMON_H
-#define __CROS_EC_USB_COMMON_H
-
-/* Functions that are shared between old and new PD stacks */
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-enum pd_drp_next_states {
-	DRP_TC_DEFAULT,
-	DRP_TC_UNATTACHED_SNK,
-	DRP_TC_ATTACHED_WAIT_SNK,
-	DRP_TC_UNATTACHED_SRC,
-	DRP_TC_ATTACHED_WAIT_SRC,
-	DRP_TC_DRP_AUTO_TOGGLE
-};
-
-/**
- * Returns the next state to transition to while in the drp auto toggle state.
- *
- * @param drp_sink_time timer for handling TOGGLE_OFF/FORCE_SINK mode when
- *			auto-toggle enabled. This is an in/out variable.
- * @param power_role current power role
- * @param drp_state dual role states
- * @param cc1 value of CC1 set by tcpm_get_cc
- * @param cc2 value of CC2 set by tcpm_get_cc
- * @param auto_toggle_supported indicates hardware auto toggle support.
- *			Hardware auto toggle support will perform the
- *			unattached to attached debouncing before notifying
- *			us of a connection.
- *
- */
-enum pd_drp_next_states drp_auto_toggle_next_state(uint64_t *drp_sink_time,
-	enum pd_power_role power_role, enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported);
-
-enum pd_pref_type {
-	/* prefer voltage larger than or equal to pd_pref_config.mv */
-	PD_PREFER_BUCK,
-	/* prefer voltage less than or equal to pd_pref_config.mv */
-	PD_PREFER_BOOST,
-};
-
-struct pd_pref_config_t {
-	/* Preferred PD voltage in mV */
-	int mv;
-	/* above which percent the battery is in constant voltage stage */
-	int cv;
-	/* System PLT (minimum consuming) power in mW. */
-	int plt_mw;
-	/* Preferred PD voltage pick strategy */
-	enum pd_pref_type type;
-};
-
-/*
- * This function converts an 8 character ascii string with hex digits, without
- * the 0x prefix, into a signed 32-bit number.
- *
- * @param str pointer to hex string to convert
- * @param val pointer to where the integer version is stored
- * @return EC_SUCCSSS on success else EC_ERROR_INVAL on failure
- */
-int hex8tou32(char *str, uint32_t *val);
-
-/*
- * Flash a USB PD device using the ChromeOS Vendor Defined Command.
- *
- * @param argc number arguments in argv. Must be greater than 3.
- * @param argv [1] is the usb port
- *             [2] unused
- *             [3] is the command {"erase", "rebooot", "signature",
- *                                 "info", "version", "write"}
- *             [4] if command was "write", then this will be the
- *                 start of the data that will be written.
- * @return EC_SUCCESS on success, else EC_ERROR_PARAM_COUNT or EC_ERROR_PARAM2
- *         on failure.
- */
-int remote_flashing(int argc, char **argv);
-
-/*
- * When AP requests to suspend PD traffic on the EC so it can do
- * firmware upgrade (retimer firmware, or TCPC chips firmware),
- * it calls this function to check if power is ready for performing
- * the upgrade.
- * @param port USB-C port number
- * @dreturn true  - power is ready
- *          false - power is not ready
- */
-bool pd_firmware_upgrade_check_power_readiness(int port);
-
-/* Returns the battery percentage [0-100] of the system. */
-int usb_get_battery_soc(void);
-
-/*
- * Returns type C current limit (mA), potentially with the DTS flag, based upon
- * states of the CC lines on the partner side.
- *
- * @param polarity port polarity
- * @param cc1 value of CC1 set by tcpm_get_cc
- * @param cc2 value of CC2 set by tcpm_get_cc
- * @return current limit (mA) with DTS flag set if appropriate
- */
-typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2);
-
-/**
- * Returns the polarity of a Sink.
- *
- * @param cc1 value of CC1 set by tcpm_get_cc
- * @param cc2 value of CC2 set by tcpm_get_cc
- * @return polarity
- */
-enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
-
-/**
- * Returns the polarity of a Source.
- *
- * @param cc1 value of CC1 set by tcpm_get_cc
- * @param cc2 value of CC2 set by tcpm_get_cc
- * @return polarity
- */
-enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
-
-/**
- * Find PDO index that offers the most amount of power and stays within
- * max_mv voltage.
- *
- * @param src_cap_cnt
- * @param src_caps
- * @param max_mv maximum voltage (or -1 if no limit)
- * @param pdo raw pdo corresponding to index, or index 0 on error (output)
- * @return index of PDO within source cap packet
- */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-	int max_mv, uint32_t *selected_pdo);
-
-/**
- * Extract power information out of a Power Data Object (PDO)
- *
- * @param pdo raw pdo to extract
- * @param ma current of the PDO (output)
- * @param max_mv maximum voltage of the PDO (output)
- * @param min_mv minimum voltage of the PDO (output)
- */
-void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
-			  uint32_t *min_mv);
-
-/**
- * Decide which PDO to choose from the source capabilities.
- *
- * @param vpd_vdo VPD VDO
- * @param rdo  requested Request Data Object.
- * @param ma  selected current limit (stored on success)
- * @param mv  selected supply voltage (stored on success)
- * @param port USB-C port number
- */
-void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port);
-
-/**
- * Notifies a task that is waiting on a system jump, that it's complete.
- */
-void notify_sysjump_ready(void);
-
-/**
- * Set USB MUX with current data role
- *
- * @param port USB-C port number
- */
-void set_usb_mux_with_current_data_role(int port);
-
-/**
- * Check if the mux should be set to enable USB3.1 mode based only on being in a
- * UFP data role. This is mode is required when attached to a port partner that
- * is type-c only, but still needs to enable USB3.1 mode.
- *
- * @param port USB-C port number
- * @return true if USB3 mode should be enabled, false otherwise
- */
-__override_proto bool usb_ufp_check_usb3_enable(int port);
-
-/**
- * Configure the USB MUX in safe mode.
- * Before entering into alternate mode, state of the USB-C MUX needs to be in
- * safe mode.
- * Ref: USB Type-C Cable and Connector Specification
- * Section E.2.2 Alternate Mode Electrical Requirements
- *
- * @param port The PD port number
- */
-void usb_mux_set_safe_mode(int port);
-
-/**
- * Configure the USB MUX in safe mode while exiting an alternate mode.
- * Although the TCSS (virtual mux) has a distinct safe mode state, it
- * needs to be in a disconnected state to properly exit an alternate
- * mode. Therefore, do not treat the virtual mux as a special case, as
- * usb_mux_set_safe_mode does.
- *
- * @param port The PD port number
- */
-void usb_mux_set_safe_mode_exit(int port);
-
-/**
- * Get the PD flags stored in BB Ram
- *
- * @param port USB-C port number
- * @param flags pointer where flags are written to
- * @return EC_SUCCESS on success
- */
-int pd_get_saved_port_flags(int port, uint8_t *flags);
-
-/**
- * Update the flag in BB Ram with the give value
- *
- * @param port USB-C port number
- * @param flag BB Ram flag to update
- * @param do_set value written to the BB Ram flag
- */
-void pd_update_saved_port_flags(int port, uint8_t flag, uint8_t do_set);
-
-/**
- * Build PD alert message
- *
- * @param msg pointer where message is stored
- * @param len pointer where length of message is stored in bytes
- * @param pr  current PD power role
- * @return EC_SUCCESS on success else EC_ERROR_INVAL
- */
-int pd_build_alert_msg(uint32_t *msg, uint32_t *len, enum pd_power_role pr);
-
-/**
- * During USB retimer firmware update, process operation
- * requested by AP
- *
- * @param port USB-C port number
- * @param op
- *       0 - USB_RETIMER_FW_UPDATE_QUERY_PORT
- *       1 - USB_RETIMER_FW_UPDATE_SUSPEND_PD
- *       2 - USB_RETIMER_FW_UPDATE_RESUME_PD
- *       3 - USB_RETIMER_FW_UPDATE_GET_MUX
- *       4 - USB_RETIMER_FW_UPDATE_SET_USB
- *       5 - USB_RETIMER_FW_UPDATE_SET_SAFE
- *       6 - USB_RETIMER_FW_UPDATE_SET_TBT
- *       7 - USB_RETIMER_FW_UPDATE_DISCONNECT
- */
-void usb_retimer_fw_update_process_op(int port, int op);
-
-/**
- * Get result of last USB retimer firmware update operation requested
- * by AP. Result is passed to AP via EC_CMD_ACPI_READ.
- *
- * @return Result of last operation. It's
- *         which port has retimer if last operation is
- *         USB_RETIMER_FW_UPDATE_QUERY_PORT;
- *         PD task is enabled or not if last operations are
- *         USB_RETIMER_FW_UPDATE_SUSPEND_PD or
- *         USB_RETIMER_FW_UPDATE_QUERY_PORT;
- *         current mux if last operations are
- *         USB_RETIMER_FW_UPDATE_GET_MUX, USB_RETIMER_FW_UPDATE_SET_USB,
- *         USB_RETIMER_FW_UPDATE_SET_SAFE, USB_RETIMER_FW_UPDATE_SET_TBT,
- *         or USB_RETIMER_FW_UPDATE_DISCONNECT.
- */
-int usb_retimer_fw_update_get_result(void);
-
-/**
- * Process deferred retimer firmware update operations.
- *
- * @param port USB-C port number
- */
-void usb_retimer_fw_update_process_op_cb(int port);
-
-/**
- * Dump SourceCap information.
- *
- * @param port USB-C port number
- */
-void pd_srccaps_dump(int port);
-#endif /* __CROS_EC_USB_COMMON_H */
diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h
deleted file mode 100644
index 49114c38e0..0000000000
--- a/include/usb_descriptor.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB definitions.
- */
-
-#ifndef __CROS_EC_USB_DESCRIPTOR_H
-#define __CROS_EC_USB_DESCRIPTOR_H
-
-#include <stddef.h> /* for wchar_t */
-
-#define USB_MAX_PACKET_SIZE 64
-
-/* USB 2.0 chapter 9 definitions */
-
-/* Descriptor types */
-#define USB_DT_DEVICE                     0x01
-#define USB_DT_CONFIGURATION              0x02
-#define USB_DT_STRING                     0x03
-#define USB_DT_INTERFACE                  0x04
-#define USB_DT_ENDPOINT                   0x05
-#define USB_DT_DEVICE_QUALIFIER           0x06
-#define USB_DT_OTHER_SPEED_CONFIG         0x07
-#define USB_DT_INTERFACE_POWER            0x08
-#define USB_DT_DEBUG                      0x0a
-#define USB_DT_BOS                        0x0f
-#define USB_DT_DEVICE_CAPABILITY          0x10
-
-/* USB Device Descriptor */
-struct usb_device_descriptor {
-	uint8_t bLength;
-	uint8_t bDescriptorType;
-	uint16_t bcdUSB;
-	uint8_t bDeviceClass;
-	uint8_t bDeviceSubClass;
-	uint8_t bDeviceProtocol;
-	uint8_t bMaxPacketSize0;
-	uint16_t idVendor;
-	uint16_t idProduct;
-	uint16_t bcdDevice;
-	uint8_t iManufacturer;
-	uint8_t iProduct;
-	uint8_t iSerialNumber;
-	uint8_t bNumConfigurations;
-} __packed;
-#define USB_DT_DEVICE_SIZE                18
-
-/* BOS Descriptor ( USB3.1 rev1 Section 9.6.2 ) */
-struct bos_context {
-	void *descp;
-	int size;
-};
-
-struct usb_bos_hdr_descriptor {
-	uint8_t bLength;
-	uint8_t bDescriptorType; /* USB_DT_BOS */
-	uint16_t wTotalLength;   /* Total length of of hdr + all dev caps */
-	uint8_t bNumDeviceCaps;  /* Container ID Descriptor + others */
-} __packed;
-#define USB_DT_BOS_SIZE 5
-
-/* Container ID Descriptor */
-struct usb_contid_caps_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_xxx */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  ContainerID[16];     /* UUID */
-} __packed;
-#define USB_DT_CONTID_SIZE         20
-
-/* Device Cap Type Codes ( offset 2 of Device Capability Descriptor */
-#define USB_DC_DTYPE_WIRELESS  0x01
-#define USB_DC_DTYPE_USB20EXT  0x02
-#define USB_DC_DTYPE_USBSS     0x03
-#define USB_DC_DTYPE_CONTID    0x04
-#define USB_DC_DTYPE_PLATFORM  0x05
-#define USB_DC_DTYPE_PD        0x06
-#define USB_DC_DTYPE_BATTINFO  0x07
-#define USB_DC_DTYPE_CONSUMER  0x08
-#define USB_DC_DTYPE_PRODUCER  0x09
-#define USB_DC_DTYPE_USBSSP    0x0a
-#define USB_DC_DTYPE_PCSTIME   0x0b
-#define USB_DC_DTYPE_WUSBEXT   0x0c
-#define USB_DC_DTYPE_BILLBOARD 0x0d
-/* RESERVED 0x00, 0xOe - 0xff */
-
-/* Platform descriptor */
-struct usb_platform_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_PLATFORM */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */
-	uint16_t bcdVersion;          /* 0x0100 */
-	uint8_t  bVendorCode;
-	uint8_t  iLandingPage;
-} __packed;
-#define USB_DT_PLATFORM_SIZE   24
-
-/* Platform Capability UUIDs */
-#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \
-	{0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47,               \
-	 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65}
-
-/* Qualifier Descriptor */
-struct usb_qualifier_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint16_t bcdUSB;
-	uint8_t  bDeviceClass;
-	uint8_t  bDeviceSubClass;
-	uint8_t  bDeviceProtocol;
-	uint8_t  bMaxPacketSize0;
-	uint8_t  bNumConfigurations;
-	uint8_t  bReserved;
-} __packed;
-#define USB_DT_QUALIFIER_SIZE		10
-
-/* Configuration Descriptor */
-struct usb_config_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint16_t wTotalLength;
-	uint8_t  bNumInterfaces;
-	uint8_t  bConfigurationValue;
-	uint8_t  iConfiguration;
-	uint8_t  bmAttributes;
-	uint8_t  bMaxPower;
-} __packed;
-#define USB_DT_CONFIG_SIZE                9
-
-/* String Descriptor */
-struct usb_string_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint16_t wData[1];
-} __packed;
-
-/* Interface Descriptor */
-struct usb_interface_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bInterfaceNumber;
-	uint8_t  bAlternateSetting;
-	uint8_t  bNumEndpoints;
-	uint8_t  bInterfaceClass;
-	uint8_t  bInterfaceSubClass;
-	uint8_t  bInterfaceProtocol;
-	uint8_t  iInterface;
-} __packed;
-#define USB_DT_INTERFACE_SIZE           9
-
-/* Endpoint Descriptor */
-struct usb_endpoint_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bEndpointAddress;
-	uint8_t  bmAttributes;
-	uint16_t wMaxPacketSize;
-	uint8_t  bInterval;
-} __packed;
-#define USB_DT_ENDPOINT_SIZE            7
-
-/* USB Class codes */
-#define USB_CLASS_PER_INTERFACE           0x00
-#define USB_CLASS_AUDIO                   0x01
-#define USB_CLASS_COMM                    0x02
-#define USB_CLASS_HID                     0x03
-#define USB_CLASS_PHYSICAL                0x05
-#define USB_CLASS_STILL_IMAGE             0x06
-#define USB_CLASS_PRINTER                 0x07
-#define USB_CLASS_MASS_STORAGE            0x08
-#define USB_CLASS_HUB                     0x09
-#define USB_CLASS_CDC_DATA                0x0a
-#define USB_CLASS_CSCID                   0x0b
-#define USB_CLASS_CONTENT_SEC             0x0d
-#define USB_CLASS_VIDEO                   0x0e
-#define USB_CLASS_BILLBOARD               0x11
-#define USB_CLASS_WIRELESS_CONTROLLER     0xe0
-#define USB_CLASS_MISC                    0xef
-#define USB_CLASS_APP_SPEC                0xfe
-#define USB_CLASS_VENDOR_SPEC             0xff
-
-/* USB Vendor ID assigned to Google Inc. */
-#define USB_VID_GOOGLE 0x18d1
-
-/* Google specific SubClass/Protocol assignments */
-#define USB_SUBCLASS_GOOGLE_SERIAL 0x50
-#define USB_PROTOCOL_GOOGLE_SERIAL 0x01
-
-#define USB_SUBCLASS_GOOGLE_SPI    0x51
-#define USB_PROTOCOL_GOOGLE_SPI    0x02
-
-#define USB_SUBCLASS_GOOGLE_I2C    0x52
-#define USB_PROTOCOL_GOOGLE_I2C    0x01
-
-#define USB_SUBCLASS_GOOGLE_UPDATE 0x53
-#define USB_PROTOCOL_GOOGLE_UPDATE 0xff
-
-/* Double define for cr50 code freeze.
- * TODO(vbendeb): dedupe this. */
-#define USB_SUBCLASS_GOOGLE_CR50   0x53
-/* We can use any protocol we want */
-#define USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE 0xff
-
-#define USB_SUBCLASS_GOOGLE_POWER  0x54
-#define USB_PROTOCOL_GOOGLE_POWER  0x01
-
-#define USB_SUBCLASS_GOOGLE_HEATMAP 0x55
-#define USB_PROTOCOL_GOOGLE_HEATMAP 0x01
-
-/* Control requests */
-
-/* bRequestType fields */
-/* direction field */
-#define USB_DIR_OUT                0    /* from host to uC */
-#define USB_DIR_IN                 0x80 /* from uC to host */
-/* type field */
-#define USB_TYPE_MASK              (0x03 << 5)
-#define USB_TYPE_STANDARD          (0x00 << 5)
-#define USB_TYPE_CLASS             (0x01 << 5)
-#define USB_TYPE_VENDOR            (0x02 << 5)
-#define USB_TYPE_RESERVED          (0x03 << 5)
-/* recipient field */
-#define USB_RECIP_MASK             0x1f
-#define USB_RECIP_DEVICE           0x00
-#define USB_RECIP_INTERFACE        0x01
-#define USB_RECIP_ENDPOINT         0x02
-#define USB_RECIP_OTHER            0x03
-
-/* Standard requests for bRequest field in a SETUP packet. */
-#define USB_REQ_GET_STATUS         0x00
-#define USB_REQ_GET_STATUS_SELF_POWERED  BIT(0)
-#define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1)
-#define USB_REQ_CLEAR_FEATURE      0x01
-#define USB_REQ_SET_FEATURE        0x03
-#define USB_REQ_FEATURE_ENDPOINT_HALT        0x0000
-#define USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP 0x0001
-#define USB_REQ_FEATURE_TEST_MODE            0x0002
-#define USB_REQ_SET_ADDRESS        0x05
-#define USB_REQ_GET_DESCRIPTOR     0x06
-#define USB_REQ_SET_DESCRIPTOR     0x07
-#define USB_REQ_GET_CONFIGURATION  0x08
-#define USB_REQ_SET_CONFIGURATION  0x09
-#define USB_REQ_GET_INTERFACE      0x0A
-#define USB_REQ_SET_INTERFACE      0x0B
-#define USB_REQ_SYNCH_FRAME        0x0C
-
-/* WebUSB URL descriptors */
-#define WEBUSB_REQ_GET_URL         0x02
-#define USB_DT_WEBUSB_URL          0x03
-
-#define USB_URL_SCHEME_HTTP       0x00
-#define USB_URL_SCHEME_HTTPS      0x01
-#define USB_URL_SCHEME_NONE       0xff
-
-/*
- * URL descriptor helper.
- * (similar to string descriptor but UTF-8 instead of UTF-16)
- */
-#define USB_URL_DESC(scheme, str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		uint8_t _scheme; \
-		char _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
-		 * size of the UTF-8 text plus the len/type fields \
-		 * minus the string 0-termination \
-		 */ \
-		sizeof(str) + 3 - 1, \
-		USB_DT_WEBUSB_URL, \
-		USB_URL_SCHEME_##scheme, \
-		str \
-	}
-
-/* Setup Packet */
-struct usb_setup_packet {
-	uint8_t  bmRequestType;
-	uint8_t  bRequest;
-	uint16_t wValue;
-	uint16_t wIndex;
-	uint16_t wLength;
-};
-
-/* Helpers for descriptors */
-
-#define WIDESTR(quote) WIDESTR2(quote)
-#define WIDESTR2(quote) L##quote
-
-#define USB_STRING_DESC(str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		wchar_t _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
-		 * size of the UTF-16 text plus the len/type fields \
-                 * minus the string 0-termination \
-                 */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
-	}
-
-#ifdef CONFIG_USB_SERIALNO
-/* String Descriptor for USB, for editable strings. */
-struct usb_string_desc {
-	uint8_t _len;
-	uint8_t _type;
-	wchar_t _data[CONFIG_SERIALNO_LEN];
-};
-#define USB_WR_STRING_DESC(str) \
-	(&(struct usb_string_desc) { \
-		/* As above, two bytes metadata, no null terminator. */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
-})
-extern struct usb_string_desc *usb_serialno_desc;
-#endif
-
-/* Use these macros for declaring descriptors, to order them properly */
-#define USB_CONF_DESC_VAR(name, varname) varname		\
-	__keep __attribute__((section(".rodata.usb_desc_" STRINGIFY(name))))
-#define USB_CONF_DESC(name) USB_CONF_DESC_VAR(name, CONCAT2(usb_desc_, name))
-#define USB_IFACE_DESC(num) USB_CONF_DESC(CONCAT3(iface, num, _0iface))
-#define USB_CUSTOM_DESC_VAR(i, name, varname)			\
-	USB_CONF_DESC_VAR(CONCAT4(iface, i, _1, name), varname)
-#define USB_CUSTOM_DESC(i, name) USB_CONF_DESC(CONCAT4(iface, i, _1, name))
-#define USB_EP_DESC(i, num) USB_CONF_DESC(CONCAT4(iface, i, _2ep, num))
-
-/* USB Linker data */
-extern const uint8_t __usb_desc[];
-extern const uint8_t __usb_desc_end[];
-#define USB_DESC_SIZE (__usb_desc_end - __usb_desc)
-
-/* These descriptors defined in board code */
-extern const void * const usb_strings[];
-extern const uint8_t usb_string_desc[];
-/* USB string descriptor with the firmware version */
-extern const void * const usb_fw_version;
-extern const struct bos_context bos_ctx;
-extern const void *webusb_url;
-
-#endif /* __CROS_EC_USB_DESCRIPTOR_H */
diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h
deleted file mode 100644
index ea824ea476..0000000000
--- a/include/usb_dp_alt_mode.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * DisplayPort alternate mode support
- * Refer to VESA DisplayPort Alt Mode on USB Type-C Standard, version 2.0,
- * section 5.2
- */
-
-#ifndef __CROS_EC_USB_DP_ALT_MODE_H
-#define __CROS_EC_USB_DP_ALT_MODE_H
-
-#include <stdint.h>
-
-#include "tcpm/tcpm.h"
-
-/*
- * Initialize DP state for the specified port.
- *
- * @param port USB-C port number
- */
-void dp_init(int port);
-
-/*
- * Returns True if DisplayPort mode is in active state
- *
- * @param port      USB-C port number
- * @return          True if DisplayPort mode is in active state
- *                  False otherwise
- */
-bool dp_is_active(int port);
-
-/*
- * Checks whether the mode entry sequence for DisplayPort alternate mode is done
- * for a port.
- *
- * @param port      USB-C port number
- * @return          True if entry sequence for DisplayPort mode is completed
- *                  False otherwise
- */
-bool dp_entry_is_done(int port);
-
-/*
- * Handles received DisplayPort VDM ACKs.
- *
- * @param port      USB-C port number
- * @param type      Transmit type (SOP, SOP') for received ACK
- * @param vdo_count The number of VDOs in the ACK VDM
- * @param vdm       VDM from ACK
- */
-void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
-
-/*
- * Handles NAKed (or Not Supported or timed out) DisplayPort VDM requests.
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP') for request
- * @param svid    The SVID of the request
- * @param vdm_cmd The VDM command of the request
- */
-void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd);
-
-/*
- * Construct the next DisplayPort VDM that should be sent.
- *
- * @param port      USB-C port number
- * @param vdo_count The number of VDOs in vdm; must be at least VDO_MAX_SIZE
- * @param vdm       The VDM payload to be sent; output; must point to at least
- *                  VDO_MAX_SIZE elements
- * @return          The number of VDOs written to VDM or -1 to indicate error
- */
-int dp_setup_next_vdm(int port, int vdo_count, uint32_t *vdm);
-
-#endif  /* __CROS_EC_USB_DP_ALT_MODE_H */
diff --git a/include/usb_emsg.h b/include/usb_emsg.h
deleted file mode 100644
index 7b418cefdc..0000000000
--- a/include/usb_emsg.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Extended message buffer */
-
-#ifndef __CROS_EC_USB_EBUF_H
-#define __CROS_EC_USB_EBUF_H
-
-#ifdef CONFIG_USB_PD_REV30
-#define EXTENDED_BUFFER_SIZE 260
-#else
-#define EXTENDED_BUFFER_SIZE 28
-#endif
-
-struct extended_msg {
-	uint32_t header;
-	uint32_t len;
-	uint8_t buf[EXTENDED_BUFFER_SIZE];
-};
-
-/* Defined in usb_prl_sm.c */
-extern struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-extern struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
-#endif /* __CROS_EC_USB_EBUF_H */
diff --git a/include/usb_hid.h b/include/usb_hid.h
deleted file mode 100644
index e7b1cfe74b..0000000000
--- a/include/usb_hid.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB HID definitions.
- */
-
-#ifndef __CROS_EC_USB_HID_H
-#define __CROS_EC_USB_HID_H
-
-#define USB_HID_SUBCLASS_BOOT     1
-#define USB_HID_PROTOCOL_KEYBOARD 1
-#define USB_HID_PROTOCOL_MOUSE    2
-
-/* USB HID Class requests */
-#define USB_HID_REQ_GET_REPORT    0x01
-#define USB_HID_REQ_GET_IDLE      0x02
-#define USB_HID_REQ_GET_PROTOCOL  0x03
-#define USB_HID_REQ_SET_REPORT    0x09
-#define USB_HID_REQ_SET_IDLE      0x0A
-#define USB_HID_REQ_SET_PROTOCOL  0x0B
-
-/* USB HID class descriptor types */
-#define USB_HID_DT_HID            (USB_TYPE_CLASS | 0x01)
-#define USB_HID_DT_REPORT         (USB_TYPE_CLASS | 0x02)
-#define USB_HID_DT_PHYSICAL       (USB_TYPE_CLASS | 0x03)
-
-/* Pre-defined report types */
-#define REPORT_TYPE_INPUT         0x01
-#define REPORT_TYPE_OUTPUT        0x02
-#define REPORT_TYPE_FEATURE       0x03
-
-struct usb_hid_class_descriptor {
-	uint8_t  bDescriptorType;
-	uint16_t wDescriptorLength;
-} __packed;
-
-struct usb_hid_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint16_t bcdHID;
-	uint8_t  bCountryCode;
-	uint8_t  bNumDescriptors;
-	struct usb_hid_class_descriptor desc[1];
-} __packed;
-
-#endif /* USB_H */
diff --git a/include/usb_hid_touchpad.h b/include/usb_hid_touchpad.h
deleted file mode 100644
index 1e6d4cf832..0000000000
--- a/include/usb_hid_touchpad.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB HID definitions.
- */
-
-#ifndef __CROS_EC_USB_HID_TOUCHPAD_H
-#define __CROS_EC_USB_HID_TOUCHPAD_H
-
-#define USB_HID_TOUCHPAD_TIMESTAMP_UNIT 100 /* usec */
-
-#define REPORT_ID_TOUCHPAD		0x01
-#define REPORT_ID_DEVICE_CAPS		0x0A
-#define REPORT_ID_DEVICE_CERT		0x0B
-
-#define MAX_FINGERS			5
-
-struct usb_hid_touchpad_report {
-	uint8_t id; /* 0x01 */
-	struct {
-		uint16_t confidence:1;
-		uint16_t tip:1;
-		uint16_t inrange:1;
-		uint16_t id:4;
-		uint16_t pressure:9;
-		uint16_t width:12;
-		uint16_t height:12;
-		uint16_t x:12;
-		uint16_t y:12;
-	} __packed finger[MAX_FINGERS];
-	uint8_t count:7;
-	uint8_t button:1;
-	uint16_t timestamp;
-} __packed;
-
-/* class implementation interfaces */
-void set_touchpad_report(struct usb_hid_touchpad_report *report);
-
-#endif
diff --git a/include/usb_i2c.h b/include/usb_i2c.h
deleted file mode 100644
index fd79293014..0000000000
--- a/include/usb_i2c.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "consumer.h"
-#include "producer.h"
-#include "registers.h"
-#include "task.h"
-#include "usb_descriptor.h"
-#include "util.h"
-
-#ifndef __CROS_USB_I2C_H
-#define __CROS_USB_I2C_H
-
-/*
- * This header file describes i2c encapsulation when communicated over USB.
- *
- * Note that current implementation assumes that there is only one instance of
- * interface of this kind per device.
- *
- * 2 forms of command are supported:
- *   - When write payload + header is larger than 64 bytes, which exceed the
- *     common USB packet (64 bytes), remaining payload should send without
- *     header.
- *
- *   - CONFIG_USB_I2C_MAX_WRITE_COUNT / CONFIG_USB_I2C_MAX_READ_COUNT have to
- *     be defined properly based on the use cases.
- *
- *   - Read less than 128 (0x80) bytes.
- *   +---------+------+----+----+---------------+
- *   | wc/port | addr | wc | rc | write payload |
- *   +---------+------+----+----+---------------+
- *   |   1B    |  1B  | 1B | 1B |  < 256 bytes  |
- *   +---------+------+----+----+---------------+
- *
- *   - Read less than 32768 (0x8000) bytes.
- *   +---------+------+----+----+-----+----------+---------------+
- *   | wc/port | addr | wc | rc | rc1 | reserved | write payload |
- *   +---------+------+----+----+----------------+---------------+
- *   |    1B   |  1B  | 1B | 1B |  1B |    1B    |  < 256 bytes  |
- *   +---------+------+----+----+----------------+---------------+
- *
- *   - Special notes for rc and rc1:
- *     If the most significant bit in rc is set (rc >= 0x80), this indicates
- *     that we want to read back more than 127 bytes, so the first byte of
- *     data contains rc1 (read count continuation), and the final read count
- *     will be (rc1 << 7) | (rc & 0x7F).
- *
- *   Fields:
- *
- *   - wc/port: 1 byte: 4 top bits are the 4 top bits of the 12 bit write
- *         counter, the 4 bottom bits are the port address, i2c interface
- *         index.
- *
- *   - addr: peripheral address, 1 byte, i2c 7-bit bus address.
- *
- *   - wc: write count, 1 byte, zero based count of bytes to write. If the
- *         indicated write count cause the payload + header exceeds 64 bytes,
- *         Following packets are expected to continue the payload without
- *         header.
- *
- *   - rc: read count, 1 byte, zero based count of bytes to read. To read more
- *         than 127 (0x7F) bytes please see the special notes above.
- *
- *   - data: payload of data to write. See wc above for more information.
- *
- *   - rc1: extended read count, 1 byte. An extended version indicates we want
- *          to read more data. While the most significant bits is set in read
- *          count (rc >= 0x80), rc1 will concatenate with rc together. See the
- *          special notes above for concatenating details.
- *
- *   - reserved: reserved byte, 1 byte.
- *
- * Response:
- *     +-------------+---+---+--------------+
- *     | status : 2B | 0 | 0 | read payload |
- *     +-------------+---+---+--------------+
- *
- *   - read payload might not fit into a single USB packets. Remaining will be
- *     transimitted witout header. Receiving side should concatenate them.
- *
- *     status: 2 byte status
- *         0x0000: Success
- *         0x0001: I2C timeout
- *         0x0002: Busy, try again
- *             This can happen if someone else has acquired the shared memory
- *             buffer that the I2C driver uses as /dev/null
- *         0x0003: Write count invalid (mismatch with merged payload)
- *         0x0004: Read count invalid (e.g. larger than available buffer)
- *         0x0005: The port specified is invalid.
- *         0x0006: The I2C interface is disabled.
- *         0x8000: Unknown error mask
- *             The bottom 15 bits will contain the bottom 15 bits from the EC
- *             error code.
- *
- *     read payload: Depends on the buffer size and implementation. Length will
- *             match requested read count
- */
-
-enum usb_i2c_error {
-	USB_I2C_SUCCESS             = 0x0000,
-	USB_I2C_TIMEOUT             = 0x0001,
-	USB_I2C_BUSY                = 0x0002,
-	USB_I2C_WRITE_COUNT_INVALID = 0x0003,
-	USB_I2C_READ_COUNT_INVALID  = 0x0004,
-	USB_I2C_PORT_INVALID        = 0x0005,
-	USB_I2C_DISABLED            = 0x0006,
-	USB_I2C_MISSING_HANDLER     = 0x0007,
-	USB_I2C_UNSUPPORTED_COMMAND = 0x0008,
-	USB_I2C_UNKNOWN_ERROR       = 0x8000,
-};
-
-
-#define USB_I2C_WRITE_BUFFER (CONFIG_USB_I2C_MAX_WRITE_COUNT + 4)
-/* If read payload is larger or equal to 128 bytes, header contains rc1 */
-#define USB_I2C_READ_BUFFER  ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ?	\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 4) :				\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 6))
-
-#define USB_I2C_BUFFER_SIZE					\
-	(USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ?	\
-		USB_I2C_READ_BUFFER : USB_I2C_WRITE_BUFFER)
-
-BUILD_ASSERT(POWER_OF_TWO(USB_I2C_READ_BUFFER));
-BUILD_ASSERT(POWER_OF_TWO(USB_I2C_WRITE_BUFFER));
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB i2c.  This structure binds
- * together all information required to operate a USB i2c.
- */
-struct usb_i2c_config {
-	uint16_t *buffer;
-
-	/* Deferred function to call to handle SPI request. */
-	const struct deferred_data *deferred;
-
-	struct consumer const consumer;
-	struct queue const *tx_queue;
-};
-
-extern struct consumer_ops const usb_i2c_consumer_ops;
-
-/*
- * Convenience macro for defining a USB I2C bridge driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_i2c_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * I2C driver.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- */
-#define USB_I2C_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       INTERFACE_NAME,					\
-		       ENDPOINT)					\
-	static uint16_t							\
-		CONCAT2(NAME, _buffer_)					\
-			[USB_I2C_BUFFER_SIZE / 2];			\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	static struct queue const CONCAT2(NAME, _to_usb_);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _);		\
-	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_),			\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_I2C,			\
-			       USB_PROTOCOL_GOOGLE_I2C,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       USB_MAX_PACKET_SIZE,			\
-			       USB_MAX_PACKET_SIZE,			\
-			       CONCAT3(usb_to_, NAME, _),		\
-			       CONCAT2(NAME, _to_usb_))			\
-	struct usb_i2c_config const NAME = {				\
-		.buffer    = CONCAT2(NAME, _buffer_),			\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.consumer  = {						\
-			.queue = &CONCAT3(usb_to_, NAME, _),		\
-			.ops   = &usb_i2c_consumer_ops,			\
-		},							\
-		.tx_queue = &CONCAT2(NAME, _to_usb_),			\
-	};								\
-	static struct queue const CONCAT2(NAME, _to_usb_) =		\
-		QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t,	\
-		null_producer, CONCAT2(NAME, _usb_).consumer);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _) =		\
-		QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t,	\
-		CONCAT2(NAME, _usb_).producer, NAME.consumer);		\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_i2c_deferred(&NAME); }
-
-/*
- * Handle I2C request in a deferred callback.
- */
-void usb_i2c_deferred(struct usb_i2c_config const *config);
-
-/*
- * These functions should be implemented by the board to provide any board
- * specific operations required to enable or disable access to the I2C device,
- * and to return the current board enable state.
- */
-
-/**
- * Check if the I2C device is enabled
- *
- * @return 1 if enabled, 0 if disabled.
- */
-int usb_i2c_board_is_enabled(void);
-
-/*
- * Special i2c address to use when the client is required to execute some
- * command which does not directly involve the i2c controller driver.
- */
-#define USB_I2C_CMD_ADDR_FLAGS 0x78
-
-/*
- * Function to call to register a handler for commands sent to the special i2c
- * address above.
- */
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size));
-
-
-#endif  /* __CROS_USB_I2C_H */
diff --git a/include/usb_mode.h b/include/usb_mode.h
deleted file mode 100644
index 4333cc851e..0000000000
--- a/include/usb_mode.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * USB4 mode support
- * Refer USB Type-C Cable and Connector Specification Release 2.0 Section 5 and
- * USB Power Delivery Specification Revision 3.0, Version 2.0 Section 6.4.8
- */
-
-#ifndef __CROS_EC_USB_MODE_H
-#define __CROS_EC_USB_MODE_H
-
-#include <stdint.h>
-
-#include "tcpm/tcpm.h"
-#include "usb_pd_tcpm.h"
-
-/*
- * Initialize USB4 state for the specified port.
- *
- * @param port USB-C port number
- */
-void enter_usb_init(int port);
-
-/*
- * Checks whether the mode entry sequence for USB4 is done for a port.
- *
- * @param port      USB-C port number
- * @return          True if entry sequence for USB4 is completed
- *                  False otherwise
- */
-bool enter_usb_entry_is_done(int port);
-
-/*
- * Requests the retimer and mux to exit USB4 mode and re-initalizes the USB4
- * state machine.
- *
- * @param port USB-C port number
- */
-void usb4_exit_mode_request(int port);
-
-/*
- * Resets USB4 state and mux state.
- *
- * @param port USB-C port number
- */
-void enter_usb_failed(int port);
-
-/*
- * Returns True if port partner supports USB4 mode
- *
- * @param port    USB-C port number
- * @return        True if USB4 mode is supported by the port partner,
- *                False otherwise
- */
-bool enter_usb_port_partner_is_capable(int port);
-
-/*
- * Returns True if cable supports USB4 mode
- *
- * @param port    USB-C port number
- * @return        True if USB4 mode is supported by the cable,
- *                False otherwise
- */
-bool enter_usb_cable_is_capable(int port);
-
-/*
- * Handles accepted USB4 response
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP', SOP'') for request
- */
-void enter_usb_accepted(int port, enum tcpci_msg_type type);
-
-/*
- * Handles rejected USB4 response
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP', SOP'') for request
- */
-void enter_usb_rejected(int port, enum tcpci_msg_type type);
-
-/*
- * Constructs the next USB4 EUDO that should be sent.
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP', SOP'') for request
- */
-uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type);
-
-#endif
diff --git a/include/usb_mux.h b/include/usb_mux.h
deleted file mode 100644
index 9909f1c1c5..0000000000
--- a/include/usb_mux.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB mux driver */
-
-#ifndef __CROS_EC_USB_MUX_H
-#define __CROS_EC_USB_MUX_H
-
-#include "ec_commands.h"
-#include "i2c.h"
-#include "tcpm/tcpm.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-
-/* Flags used for usb_mux.flags */
-#define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */
-#define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */
-#define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */
-
-/*
- * USB-C mux state
- *
- * A bitwise combination of the USB_PD_MUX_* flags.
- * Note: this is 8 bits right now to make ec_response_usb_pd_mux_info size.
- */
-typedef uint8_t mux_state_t;
-
-/* Mux driver function pointers */
-struct usb_mux;
-struct usb_mux_driver {
-	/**
-	 * Initialize USB mux. This is called every time the MUX is
-	 * access after being put in a fully disconnected state (low
-	 * power mode).
-	 *
-	 * @param me usb_mux
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*init)(const struct usb_mux *me);
-
-	/**
-	 * Set USB mux state.
-	 *
-	 * @param[in]  me usb_mux
-	 * @param[in]  mux_state State to set mux to.
-	 * @param[out] bool ack_required - indication of whether this mux needs
-	 * to wait on a host command ACK at the end of a set
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*set)(const struct usb_mux *me, mux_state_t mux_state,
-		   bool *ack_required);
-
-	/**
-	 * Get current state of USB mux.
-	 *
-	 * @param me usb_mux
-	 * @param mux_state Gets set to current state of mux.
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*get)(const struct usb_mux *me, mux_state_t *mux_state);
-
-	/**
-	 * Return if retimer supports firmware update
-	 *
-	 * @return true  - supported
-	 *         false - not supported
-	 */
-	bool (*is_retimer_fw_update_capable)(void);
-
-	/**
-	 * Optional method that is called after the mux fully disconnects.
-	 *
-	 * Note: this method does not need to be defined for TCPC/MUX combos
-	 * where the TCPC is actively used since the PD state machine
-	 * will put the chip into lower power mode.
-	 *
-	 * @param me usb_mux
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*enter_low_power_mode)(const struct usb_mux *me);
-
-	/**
-	 * Optional method that is called on HOOK_CHIPSET_RESET.
-	 *
-	 * @param me usb_mux
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*chipset_reset)(const struct usb_mux *me);
-};
-
-/* Describes a USB mux present in the system */
-struct usb_mux {
-	/*
-	 * This is index into usb_muxes that points to the start of the
-	 * possible chain of usb_mux entries that this entry is on.
-	 */
-	int usb_port;
-
-	/*
-	 * I2C port and address. This is optional if your MUX is not
-	 * an I2C interface.  If this is the case, use usb_port to
-	 * index an exernal array to track your connection parameters,
-	 * if they are needed.  One case of this would be a driver
-	 * that will use usb_port as an index into tcpc_config_t to
-	 * gather the necessary information to communicate with the MUX
-	 */
-	uint16_t i2c_port;
-	uint16_t i2c_addr_flags;
-
-	/* Run-time flags with prefix USB_MUX_FLAG_ */
-	uint32_t flags;
-
-	/* Mux driver */
-	const struct usb_mux_driver *driver;
-
-	/* Linked list chain of secondary MUXes. NULL terminated */
-	const struct usb_mux *next_mux;
-
-	/**
-	 * Optional method for tuning for USB mux during mux->driver->init().
-	 *
-	 * @param me usb_mux
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*board_init)(const struct usb_mux *me);
-
-	/*
-	 * USB mux/retimer board specific set mux_state.
-	 *
-	 * @param me usb_mux
-	 * @param mux_state State to set mode to.
-	 * @return EC_SUCCESS on success, non-zero error code on failure.
-	 */
-	int (*board_set)(const struct usb_mux *me, mux_state_t mux_state);
-
-	/*
-	 * USB Type-C DP alt mode support. Notify Type-C controller
-	 * there is DP dongle hot-plug.
-	 *
-	 * @param me usb_mux
-	 * @param mux_state with HPD IRQ and HPD LVL flags set
-	 *        accordingly
-	 */
-	void (*hpd_update)(const struct usb_mux *me,
-			   mux_state_t mux_state);
-};
-
-/* Supported USB mux drivers */
-extern const struct usb_mux_driver amd_fp5_usb_mux_driver;
-extern const struct usb_mux_driver amd_fp6_usb_mux_driver;
-extern const struct usb_mux_driver anx7440_usb_mux_driver;
-extern const struct usb_mux_driver it5205_usb_mux_driver;
-extern const struct usb_mux_driver pi3usb3x532_usb_mux_driver;
-extern const struct usb_mux_driver ps8740_usb_mux_driver;
-extern const struct usb_mux_driver ps8743_usb_mux_driver;
-extern const struct usb_mux_driver ps8822_usb_mux_driver;
-extern const struct usb_mux_driver tcpm_usb_mux_driver;
-extern const struct usb_mux_driver tusb1064_usb_mux_driver;
-extern const struct usb_mux_driver virtual_usb_mux_driver;
-
-/* USB muxes present in system, ordered by PD port #, defined at board-level */
-#ifdef CONFIG_USB_MUX_RUNTIME_CONFIG
-extern struct usb_mux usb_muxes[];
-#else
-extern const struct usb_mux usb_muxes[];
-#endif
-
-/* Supported hpd_update functions */
-void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state);
-
-/*
- * Helper methods that either use tcpc communication or direct i2c
- * communication depending on how the TCPC/MUX device is configured.
- */
-#ifdef CONFIG_USB_PD_TCPM_MUX
-static inline int mux_write(const struct usb_mux *me, int reg, int val)
-{
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write(me->usb_port, reg, val);
-}
-
-static inline int mux_read(const struct usb_mux *me, int reg, int *val)
-{
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read(me->usb_port, reg, val);
-}
-
-static inline int mux_write16(const struct usb_mux *me, int reg, int val)
-{
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write16(me->usb_port, reg, val);
-}
-
-static inline int mux_read16(const struct usb_mux *me, int reg, int *val)
-{
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read16(me->usb_port, reg, val);
-}
-#endif /* CONFIG_USB_PD_TCPM_MUX */
-
-/**
- * Initialize USB mux to its default state.
- *
- * @param port Port number.
- */
-void usb_mux_init(int port);
-
-/**
- * Configure superspeed muxes on type-C port.
- *
- * @param port port number.
- * @param mux_mode mux selected function.
- * @param usb_config usb2.0 selected function.
- * @param polarity plug polarity (0=CC1, 1=CC2).
- */
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_config, int polarity);
-
-/**
- * Query superspeed mux status on type-C port.
- *
- * @param port port number.
- * @return current MUX state (USB_PD_MUX_*).
- */
-mux_state_t usb_mux_get(int port);
-
-/**
- * Flip the superspeed muxes on type-C port.
- *
- * This is used for factory test automation. Note that this function should
- * only flip the superspeed muxes and leave CC lines alone. Without further
- * changes, this function MUST ONLY be used for testing purpose, because
- * the protocol layer loses track of the superspeed polarity and DP/USB3.0
- * connection may break.
- *
- * @param port port number.
- */
-void usb_mux_flip(int port);
-
-/**
- * Update the hot-plug event.
- *
- * @param port port number.
- * @param mux_state HPD IRQ and LVL mux flags
- */
-void usb_mux_hpd_update(int port, mux_state_t mux_state);
-
-/**
- * Port information about retimer firmware update support.
- *
- * @return which ports support retimer firmware update
- *         Bits[7:0]: represent PD ports 0-7;
- *         each bit
- *         = 1, this port supports retimer firmware update;
- *         = 0, not support.
- */
-int usb_mux_retimer_fw_update_port_info(void);
-
-#endif
diff --git a/include/usb_pd_dp_ufp.h b/include/usb_pd_dp_ufp.h
deleted file mode 100644
index 64728d948e..0000000000
--- a/include/usb_pd_dp_ufp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Common functions for UFP-D devices.
- */
-
-#ifndef __CROS_EC_USB_PD_DP_UFP_H
-#define __CROS_EC_USB_PD_DP_UFP_H
-
-struct hpd_to_pd_config_t {
-	int port;
-	enum gpio_signal signal;
-};
-
-extern const struct hpd_to_pd_config_t hpd_config;
-/*
- * Function used to handle hpd gpio interrupts.
- *
- * @param signal -> gpio signal associated with hpd interrupt
- */
-void usb_pd_hpd_edge_event(int signal);
-
-/*
- * Function used to enable/disable the hpd->dp attention protocol converter
- *    - called with enable when enter mode command is processed.
- *    - called with disable when exit mode command is processed.
- *
- * @param enable -> converter on/off
- */
-void usb_pd_hpd_converter_enable(int enable);
-
-#endif  /* __CROS_EC_USB_PD_DP_UFP_H */
diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h
deleted file mode 100644
index 19d4c4fe6b..0000000000
--- a/include/usb_pd_dpm.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Device Policy Manager implementation
- * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
- */
-
-#ifndef __CROS_EC_USB_DPM_H
-#define __CROS_EC_USB_DPM_H
-
-#include "ec_commands.h"
-#include "usb_pd_tcpm.h"
-
-/*
- * Initializes DPM state for a port.
- *
- * @param port USB-C port number
- */
-void dpm_init(int port);
-
-/*
- * Informs the DPM that Exit Mode request is received
- *
- * @param port USB-C port number
- */
-void dpm_set_mode_exit_request(int port);
-
-/*
- * Informs the DPM that a VDM ACK was received.
- *
- * @param port      USB-C port number
- * @param type      Transmit type (SOP, SOP') for received ACK
- * @param vdo_count The number of VDOs in vdm; must be at least 1
- * @param vdm       The VDM payload of the ACK
- */
-void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
-
-/*
- * Informs the DPM that a VDM NAK was received. Also applies when a VDM request
- * received a Not Supported response or timed out waiting for a response.
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP') for request
- * @param svid    The SVID of the request
- * @param vdm_cmd The VDM command of the request
- */
-void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd);
-
-/*
- * Drives the Policy Engine through entry/exit mode process
- *
- * @param port USB-C port number
- */
-void dpm_run(int port);
-
-/*
- * Determines the current allocation for the connection, past the basic
- * CONFIG_USB_PD_PULLUP value set by the TC (generally 1.5 A)
- *
- * @param port		USB-C port number
- * @param vsafe5v_pdo	Copy of first Sink_Capability PDO, which should
- *			represent the vSafe5V fixed PDO
- */
-void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo);
-
-/*
- * Registers port as a non-PD sink, so that can be taken into account when
- * allocating current.
- *
- * @param port		USB-C port number
- */
-void dpm_add_non_pd_sink(int port);
-
-/*
- * Remove this port as a sink, and reallocate maximum current as needed.
- *
- * @param port		USB-C port number
- */
-void dpm_remove_sink(int port);
-
-/*
- * Remove this port as a source, and reallocate reserved FRS maximum current
- * as needed.
- *
- * @param port		USB-C port number
- */
-void dpm_remove_source(int port);
-
-/*
- * Return the appropriate Source Capability PDO to offer this port
- *
- * @param src_pdo	Will point to appropriate PDO to offer
- * @param port		USB-C port number
- * @return		Number of PDOs
- */
-int dpm_get_source_pdo(const uint32_t **src_pdo, const int port);
-
-/*
- * Report offered source current for this port
- *
- * @param port		USB-C port number
- * @return		Current offered, in mA
- */
-int dpm_get_source_current(const int port);
-
-#endif  /* __CROS_EC_USB_DPM_H */
diff --git a/include/usb_pd_policy.h b/include/usb_pd_policy.h
deleted file mode 100644
index a4f0c64ea6..0000000000
--- a/include/usb_pd_policy.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USBC PD Default Policies  */
-
-#ifndef __CROS_EC_USB_PD_POLICY_H
-#define __CROS_EC_USB_PD_POLICY_H
-
-#include "usb_pe_sm.h"
-
-/**
- * Port Discovery DR Swap Policy
- *
- * Different boards can implement its own DR swap policy during a port discovery
- * by implementing this function.
- *
- * @param port USB-C port number
- * @param dr   current port data role
- * @param dr_swap_flag   Data Role Swap Flag bit
- * @param return True if state machine should perform a DR swap, elsf False
- */
-__override_proto  bool port_discovery_dr_swap_policy(int port,
-		enum pd_data_role dr, bool dr_swap_flag);
-
-/**
- * Port Discovery VCONN Swap Policy
- *
- * Different boards can implement its own VCONN swap policy during a port
- * discovery by implementing this function.
- *
- * @param port USB-C port number
- * @param vconn_swap_to_on_flag   Vconn Swap to On Flag bit
- * @param return True if state machine should perform a VCONN swap, elsf False
- */
-__override_proto bool port_discovery_vconn_swap_policy(int port,
-		bool vconn_swap_flag);
-
-#endif /* __CROS_EC_USB_PD_POLICY_H */
-
diff --git a/include/usb_pd_tcpc.h b/include/usb_pd_tcpc.h
deleted file mode 100644
index 0a10f97e0e..0000000000
--- a/include/usb_pd_tcpc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery port controller */
-
-#ifndef __CROS_EC_USB_PD_TCPC_H
-#define __CROS_EC_USB_PD_TCPC_H
-
-#include <stdint.h>
-#include "usb_pd_tcpm.h"
-
-/* If we are a TCPC but not a TCPM, then we implement the peripheral TCPCI */
-#if defined(CONFIG_USB_PD_TCPC) && !defined(CONFIG_USB_PD_TCPM_STUB)
-#define TCPCI_I2C_PERIPHERAL
-#endif
-
-#ifdef TCPCI_I2C_PERIPHERAL
-/* Convert TCPC address to type-C port number */
-#define TCPC_ADDR_TO_PORT(addr) ((addr) \
-			- I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
-/* Check if the i2c address belongs to TCPC */
-#define ADDR_IS_TCPC(addr)      (((addr) & 0x7E) \
-			== I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
-#endif
-
-/**
- * Process incoming TCPCI I2C command
- *
- * @param read This is a read request. If 0, this is a write request.
- * @param len Length of incoming payload
- * @param payload Pointer to incoming and outgoing data
- * @param send_response Function to call to send response if necessary
- */
-void tcpc_i2c_process(int read, int port, int len, uint8_t *payload,
-		      void (*send_response)(int));
-
-/**
- * Handle VBUS wake interrupts
- *
- * @param signal The VBUS wake interrupt signal
- */
-void pd_vbus_evt_p0(enum gpio_signal signal);
-void pd_vbus_evt_p1(enum gpio_signal signal);
-
-/*
- * Methods for TCPCI peripherals (e.g. zinger) to get/set their internal
- * state
- */
-int tcpc_alert_status(int port, int *alert);
-int tcpc_alert_status_clear(int port, uint16_t mask);
-int tcpc_alert_mask_set(int port, uint16_t mask);
-int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
-int tcpc_select_rp_value(int port, int rp);
-int tcpc_set_cc(int port, int pull);
-int tcpc_set_polarity(int port, int polarity);
-int tcpc_set_power_status_mask(int port, uint8_t mask);
-int tcpc_set_vconn(int port, int enable);
-int tcpc_set_msg_header(int port, int power_role, int data_role);
-int tcpc_set_rx_enable(int port, int enable);
-int tcpc_get_message(int port, uint32_t *payload, int *head);
-int tcpc_transmit(int port, enum tcpci_msg_type type, uint16_t header,
-		  const uint32_t *data);
-int rx_buf_is_empty(int port);
-void rx_buf_clear(int port);
-
-#endif /* __CROS_EC_USB_PD_TCPC_H */
diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h
deleted file mode 100644
index 5757bd7ada..0000000000
--- a/include/usb_pd_timer.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Power delivery module */
-
-#ifndef __CROS_EC_USB_PD_TIMER_H
-#define __CROS_EC_USB_PD_TIMER_H
-
-#include <stdbool.h>
-
-/*
- * List of all timers that will be managed by usb_pd_timer
- */
-enum pd_task_timer {
-	/*
-	 * In BIST_TX mode, this timer is used by a UUT to ensure that a
-	 * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely
-	 * fashion.
-	 *
-	 * In BIST_RX mode, this timer is used to give the port partner time
-	 * to respond.
-	 */
-	PE_TIMER_BIST_CONT_MODE,
-
-	/*
-	 * PD 3.0, version 2.0, section 6.6.18.1: The ChunkingNotSupportedTimer
-	 * is used by a Source or Sink which does not support multi-chunk
-	 * Chunking but has received a Message Chunk. The
-	 * ChunkingNotSupportedTimer Shall be started when the last bit of the
-	 * EOP of a Message Chunk of a multi-chunk Message is received. The
-	 * Policy Engine Shall Not send its Not_Supported Message before the
-	 * ChunkingNotSupportedTimer expires.
-	 */
-	PE_TIMER_CHUNKING_NOT_SUPPORTED,
-
-	/*
-	 * This timer is used during an Explicit Contract when discovering
-	 * whether a Port Partner is PD Capable using SOP'.
-	 */
-	PE_TIMER_DISCOVER_IDENTITY,
-
-	/*
-	 * The NoResponseTimer is used by the Policy Engine in a Source
-	 * to determine that its Port Partner is not responding after a
-	 * Hard Reset.
-	 */
-	PE_TIMER_NO_RESPONSE,
-
-	/*
-	 * This timer tracks the time after receiving a Wait message in
-	 * response to a PR_Swap message.
-	 */
-	PE_TIMER_PR_SWAP_WAIT,
-
-	/*
-	 * This timer is used in a Source to ensure that the Sink has had
-	 * sufficient time to process Hard Reset Signaling before turning
-	 * off its power supply to VBUS.
-	 */
-	PE_TIMER_PS_HARD_RESET,
-
-	/*
-	 * This timer combines the PSSourceOffTimer and PSSourceOnTimer timers.
-	 * For PSSourceOffTimer, when this DRP device is currently acting as a
-	 * Sink, this timer times out on a PS_RDY Message during a Power Role
-	 * Swap sequence.
-	 *
-	 * For PSSourceOnTimer, when this DRP device is currently acting as a
-	 * Source that has just stopped sourcing power and is waiting to start
-	 * sinking power to timeout on a PS_RDY Message during a Power Role
-	 * Swap.
-	 */
-	PE_TIMER_PS_SOURCE,
-
-	/*
-	 * This timer is started when a request for a new Capability has been
-	 * accepted and will timeout after PD_T_PS_TRANSITION if a PS_RDY
-	 * Message has not been received.
-	 */
-	PE_TIMER_PS_TRANSITION,
-
-	/*
-	 * This timer is used to ensure that a Message requesting a response
-	 * (e.g. Get_Source_Cap Message) is responded to within a bounded time
-	 * of PD_T_SENDER_RESPONSE.
-	 */
-	PE_TIMER_SENDER_RESPONSE,
-
-	/*
-	 * This timer is used to ensure that the time before the next Sink
-	 * Request Message, after a Wait Message has been received from the
-	 * Source in response to a Sink Request Message.
-	 */
-	PE_TIMER_SINK_REQUEST,
-
-	/*
-	 * Prior to a successful negotiation, a Source Shall use the
-	 * SourceCapabilityTimer to periodically send out a
-	 * Source_Capabilities Message.
-	 */
-	PE_TIMER_SOURCE_CAP,
-
-	/*
-	 * Used to wait for tSrcTransition between sending an Accept for a
-	 * Request or receiving a GoToMin and transitioning the power supply.
-	 * See PD 3.0, table 7-11 and table 7-22 This is not a named timer in
-	 * the spec.
-	 */
-	PE_TIMER_SRC_TRANSITION,
-
-	/*
-	 * This timer is used by the new Source, after a Power Role Swap or
-	 * Fast Role Swap, to ensure that it does not send Source_Capabilities
-	 * Message before the new Sink is ready to receive the
-	 * Source_Capabilities Message.
-	 */
-	PE_TIMER_SWAP_SOURCE_START,
-
-	/* Temporary available timeout timer */
-	PE_TIMER_TIMEOUT,
-
-	/*
-	 * This timer is used during a VCONN Swap.
-	 */
-	PE_TIMER_VCONN_ON,
-
-	/*
-	 * This timer is used by the Initiator’s Policy Engine to ensure that
-	 * a Structured VDM Command request needing a response (e.g. Discover
-	 * Identity Command request) is responded to within a bounded time of
-	 * tVDMSenderResponse.
-	 */
-	PE_TIMER_VDM_RESPONSE,
-
-	/*
-	 * For PD2.0, this timer is used to wait 400ms and add some
-	 * jitter of up to 100ms before sending a message.
-	 * NOTE: This timer is not part of the TypeC/PD spec.
-	 */
-	PE_TIMER_WAIT_AND_ADD_JITTER,
-
-
-	/* Chunk Sender Response timer */
-	PR_TIMER_CHUNK_SENDER_RESPONSE,
-
-	/* Chunk Sender Request timer */
-	PR_TIMER_CHUNK_SENDER_REQUEST,
-
-	/* Hard Reset Complete timer */
-	PR_TIMER_HARD_RESET_COMPLETE,
-
-	/* Sink TX timer */
-	PR_TIMER_SINK_TX,
-
-	/* timeout to limit waiting on TCPC response (not in spec) */
-	PR_TIMER_TCPC_TX_TIMEOUT,
-
-
-	/* Time a port shall wait before it can determine it is attached */
-	TC_TIMER_CC_DEBOUNCE,
-
-	/* Time to debounce exit low power mode */
-	TC_TIMER_LOW_POWER_EXIT_TIME,
-
-	/* Time to enter low power mode */
-	TC_TIMER_LOW_POWER_TIME,
-
-	/* Role toggle timer */
-	TC_TIMER_NEXT_ROLE_SWAP,
-
-	/*
-	 * Time a Sink port shall wait before it can determine it is detached
-	 * due to the potential for USB PD signaling on CC as described in
-	 * the state definitions.
-	 */
-	TC_TIMER_PD_DEBOUNCE,
-
-	/* Generic timer */
-	TC_TIMER_TIMEOUT,
-
-	/*
-	 * Time a port shall wait before it can determine it is
-	 * re-attached during the try-wait process.
-	 */
-	TC_TIMER_TRY_WAIT_DEBOUNCE,
-
-	/*
-	 * Time to ignore Vbus absence due to external IC debounce detection
-	 * logic immediately after a power role swap.
-	 */
-	TC_TIMER_VBUS_DEBOUNCE,
-
-	PD_TIMER_COUNT
-};
-BUILD_ASSERT(PD_TIMER_COUNT <= 32);
-
-enum pd_timer_range {
-	PE_TIMER_RANGE,
-	PR_TIMER_RANGE,
-	TC_TIMER_RANGE,
-};
-#define PE_TIMER_START		PE_TIMER_BIST_CONT_MODE
-#define PE_TIMER_END		PE_TIMER_WAIT_AND_ADD_JITTER
-
-#define PR_TIMER_START		PR_TIMER_CHUNK_SENDER_RESPONSE
-#define PR_TIMER_END		PR_TIMER_TCPC_TX_TIMEOUT
-
-#define TC_TIMER_START		TC_TIMER_CC_DEBOUNCE
-#define TC_TIMER_END		TC_TIMER_VBUS_DEBOUNCE
-
-/*
- * pd_timer_init
- * Initialize Power Delivery Timer module
- *
- * @param port USB-C port number
- */
-void pd_timer_init(int port);
-
-/*
- * pd_timer_enable
- * Initiate an enabled timer
- *
- * @param port USB-C port number
- * @param timer Requested pd_task_timer
- * @param expires_us Expiration time relative to "now"
- */
-void pd_timer_enable(int port, enum pd_task_timer timer, uint32_t expires_us);
-
-/*
- * pd_timer_disable
- * Disable a timer
- *
- * @param port USB-C port number
- * @param timer Requested pd_task_timer
- */
-void pd_timer_disable(int port, enum pd_task_timer timer);
-
-/*
- * pd_timer_disable_range
- * Disable all of the timers in a group range
- *
- * @param port USB-C port number
- * @param range Group range to disable
- */
-void pd_timer_disable_range(int port, enum pd_timer_range range);
-
-/*
- * pd_timer_is_disabled
- * Determine if a timer is currently disabled
- *
- * @param port USB-C port number
- * @param timer Requested pd_task_timer
- * @return True if the timer is disabled, otherwise false
- */
-bool pd_timer_is_disabled(int port, enum pd_task_timer timer);
-
-/*
- * pd_timer_is_expired
- * Determine if a timer is expired
- *
- * @param port USB-C port number
- * @param timer Requested pd_task_timer
- * @return True if the timer is enabled and expired, otherwise false
- */
-bool pd_timer_is_expired(int port, enum pd_task_timer timer);
-
-/*
- * pd_timer_manage_expired
- * Convert an active/expired timer to be inactive/expired. This will allow
- * the code to continue to check for expired without having this timer as
- * part of the pd_timer_next_expiration decision.
- *
- * @param port USB-C port number
- */
-void pd_timer_manage_expired(int port);
-
-/*
- * pd_timer_next_expiration
- * Retrieve the next active expiration time
- *
- * @param port USB-C port number
- * @return >= 0 is the number of uSeconds until we should wake up.
- *	   -1 no pending timeout
- */
-int pd_timer_next_expiration(int port);
-
-
-/*
- * pd_timer_dump
- * Debug display of the timers for a given port
- *
- * @param port USB-C port number
- */
-void pd_timer_dump(int port);
-
-#endif  /* __CROS_EC_USB_PD_TIMER_H */
diff --git a/include/usb_pe_sm.h b/include/usb_pe_sm.h
deleted file mode 100644
index d6ecb4d400..0000000000
--- a/include/usb_pe_sm.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Policy Engine module */
-
-#ifndef __CROS_EC_USB_PE_H
-#define __CROS_EC_USB_PE_H
-
-#include "usb_pd_tcpm.h"
-#include "usb_sm.h"
-
-/* Policy Engine Receive and Transmit Errors */
-enum pe_error {
-	ERR_RCH_CHUNKED,
-	ERR_RCH_MSG_REC,
-	ERR_RCH_CHUNK_WAIT_TIMEOUT,
-	ERR_TCH_CHUNKED,
-	ERR_TCH_XMIT,
-};
-
-/**
- * Runs the Policy Engine State Machine
- *
- * @param port USB-C port number
- * @param evt  system event, ie: PD_EVENT_RX
- * @param en   0 to disable the machine, 1 to enable the machine
- */
-void pe_run(int port, int evt, int en);
-
-/**
- * Sets the debug level for the PRL layer
- *
- * @param level debug level
- */
-void pe_set_debug_level(enum debug_level level);
-
-/**
- * Informs the Policy Engine that a message was successfully sent
- *
- * @param port USB-C port number
- */
-void pe_message_sent(int port);
-
-/**
- * Informs the Policy Engine of an error.
- *
- * @param port USB-C port number
- * @param  e    error
- * @param type  port address where error was generated
- */
-void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type);
-
-/**
- * Informs the Policy Engine of a discard.
- *
- * @param port USB-C port number
- */
-void pe_report_discard(int port);
-
-/**
- * Called by the Protocol Layer to informs the Policy Engine
- * that a message has been received.
- *
- * @param port USB-C port number
- */
-void pe_message_received(int port);
-
-/**
- * Informs the Policy Engine that a hard reset was received.
- *
- * @param port USB-C port number
- */
-void pe_got_hard_reset(int port);
-
-/**
- * Informs the Policy Engine that a soft reset was received.
- *
- * @param port USB-C port number
- */
-void pe_got_soft_reset(int port);
-
-/**
- * Informs the Policy Engine that a hard reset was sent.
- *
- * @param port USB-C port number
- */
-void pe_hard_reset_sent(int port);
-
-/**
- * Get the id of the current Policy Engine state
- *
- * @param port USB-C port number
- */
-enum pe_states pe_get_state_id(int port);
-
-/**
- * Indicates if the Policy Engine State Machine is running.
- *
- * @param port USB-C port number
- * @return 1 if policy engine state machine is running, else 0
- */
-int pe_is_running(int port);
-
-/**
- * Informs the Policy Engine that the Power Supply is at it's default state
- *
- * @param port USB-C port number
- */
-void pe_ps_reset_complete(int port);
-
-/**
- * Informs the Policy Engine that a VCONN Swap has completed
- *
- * @param port USB-C port number
- */
-void pe_vconn_swap_complete(int port);
-
-/**
- * Indicates if an explicit contract is in place
- *
- * @param port  USB-C port number
- * @return 1 if an explicit contract is in place, else 0
- */
-int pe_is_explicit_contract(int port);
-
-/*
- * Return true if port partner is dualrole capable
- *
- * @param port  USB-C port number
- */
-int pd_is_port_partner_dualrole(int port);
-
-/*
- * Informs the Policy Engine that it should invalidate the
- * explicit contract.
- *
- * @param port USB-C port number
- */
-void pe_invalidate_explicit_contract(int port);
-
-/*
- * Return true if the PE is in middle of a fast role swap (FRS). If so, the
- * Rp/Rd will be flipped from the actual power roles.
- *
- *
- * @param port USB-C port number
- */
-bool pe_in_frs_mode(int port);
-
-/*
- * Return true if the PE is is within an atomic
- * messaging sequence that it initiated with a SOP* port partner.
- *
- * Note the PRL layer polls this instead of using AMS_START and AMS_END
- * notification from the PE that is called out by the spec
- *
- * @param port USB-C port number
- */
-bool pe_in_local_ams(int port);
-
-/**
- * Returns the name of the current PE state
- *
- * @param port USB-C port number
- * @return name of current pe state
- */
-const char *pe_get_current_state(int port);
-
-/**
- * Returns the flag mask of the PE state machine
- *
- * @param port USB-C port number
- * @return flag mask of the pe state machine
- */
-uint32_t pe_get_flags(int port);
-
-#ifdef TEST_BUILD
-/**
- * Clears all internal port data, as we would on a detach event
- *
- * @param port USB-C port number
- */
-void pe_clear_port_data(int port);
-#endif /* TEST_BUILD */
-
-#endif /* __CROS_EC_USB_PE_H */
diff --git a/include/usb_prl_sm.h b/include/usb_prl_sm.h
deleted file mode 100644
index 6607bd2824..0000000000
--- a/include/usb_prl_sm.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Protocol Layer module */
-
-#ifndef __CROS_EC_USB_PRL_H
-#define __CROS_EC_USB_PRL_H
-#include "common.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_sm.h"
-#include "timer.h"
-#include "usb_pd_tcpm.h"
-
-/**
- * Returns TX success time stamp.
- *
- * @param port USB-C port number
- * @return the time stamp of TCPC tx success.
- **/
-timestamp_t prl_get_tcpc_tx_success_ts(int port);
-
-/**
- * Returns true if Protocol Layer State Machine is in run mode
- *
- * @param port USB-C port number
- * @return 1 if state machine is running, else 0
- */
-int prl_is_running(int port);
-
-/**
- * Returns true if the Protocol Layer State Machine is in the
- * process of transmitting or receiving chunked messages.
- *
- * @param port USB-C port number
- * @return true if sending or receiving a chunked message, else false
- */
-bool prl_is_busy(int port);
-
-/**
- * Sets the debug level for the PRL layer
- *
- * @param level debug level
- */
-void prl_set_debug_level(enum debug_level level);
-
-/**
- * Resets the Protocol Layer state machine but does not reset the stored PD
- * revisions of the partners.
- *
- * @param port USB-C port number
- */
-void prl_reset_soft(int port);
-
-/**
- * resets the stored pd revisions for each sop type to their default value, the
- * highest revision supported by this implementation. per pd r3.0 v2.0,
- * ss6.2.1.1.5, this should only happen upon detach, hard reset, or error
- * recovery.
- *
- * @param port USB-C port number
- */
-void prl_set_default_pd_revision(int port);
-
-/**
- * Runs the Protocol Layer State Machine
- *
- * @param port USB-C port number
- * @param evt  system event, ie: PD_EVENT_RX
- * @param en   0 to disable the machine, 1 to enable the machine
- */
-void prl_run(int port, int evt, int en);
-
-/**
- * Set the PD revision
- *
- * @param port USB-C port number
- * @param type port address
- * @param rev revision
- */
-void prl_set_rev(int port, enum tcpci_msg_type type,
-					enum pd_rev_type rev);
-
-/**
- * Get the PD revision
- *
- * @param port USB-C port number
- * @param type port address
- * @return pd rev
- */
-enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type);
-
-/**
- * Sends a PD control message
- *
- * @param port USB-C port number
- * @param type Transmit type
- * @param msg  Control message type
- */
-void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
-	enum pd_ctrl_msg_type msg);
-
-/**
- * Sends a PD data message
- *
- * @param port USB-C port number
- * @param type Transmit type
- * @param msg  Data message type
- */
-void prl_send_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_data_msg_type msg);
-
-/**
- * Sends a PD extended data message
- *
- * @param port USB-C port number
- * @param type Transmit type
- * @param msg  Extended data message type
- */
-void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_ext_msg_type msg);
-
-/**
- * Informs the Protocol Layer that a hard reset has completed
- *
- * @param port USB-C port number
- */
-void prl_hard_reset_complete(int port);
-
-/**
- * Policy Engine calls this function to execute a hard reset.
- *
- * @param port USB-C port number
- */
-void prl_execute_hard_reset(int port);
-
-#endif /* __CROS_EC_USB_PRL_H */
diff --git a/include/usb_sm.h b/include/usb_sm.h
deleted file mode 100644
index 2b5939bc04..0000000000
--- a/include/usb_sm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB State Machine Framework */
-
-#ifndef __CROS_EC_USB_SM_H
-#define __CROS_EC_USB_SM_H
-
-#include "compiler.h"	/* for typeof() on Zephyr */
-
-/* Function pointer that implements a portion of a usb state */
-typedef void (*state_execution)(const int port);
-
-/*
- * General usb state that can be used in multiple state machines.
- *
- * entry - Optional method that will be run when this state is entered
- * run   - Optional method that will be run repeatedly during state machine loop
- * exit  - Optional method that will be run when this state exists
- * parent- Optional parent usb_state that contains common entry/run/exit
- *	implementation among various child usb_states.
- *	entry: Parent function executes BEFORE child function.
- *	run: Parent function executes AFTER child function.
- *	exit: Parent function executes AFTER child function.
- *
- *	Note: When transitioning between two child states with a shared parent,
- *	that parent's exit and entry functions do not execute.
- */
-struct usb_state {
-	const state_execution entry;
-	const state_execution run;
-	const state_execution exit;
-	const struct usb_state *parent;
-};
-
-typedef const struct usb_state *usb_state_ptr;
-
-/* Defines the current context of the usb statemachine. */
-struct sm_ctx {
-	usb_state_ptr current;
-	usb_state_ptr previous;
-	/* We use intptr_t type to accommodate host tests ptr size variance */
-	intptr_t internal[2];
-};
-
-/* Local state machine states */
-enum sm_local_state {
-	SM_INIT = 0, /* Ensure static variables initialize to SM_INIT */
-	SM_RUN,
-	SM_PAUSED,
-};
-
-/*
- * A state machine can use these debug levels to regulate the amount of debug
- * information printed on the EC console
- *
- * The states currently defined are
- *   Level 0: disabled
- *   Level 1: state names
- *
- * Note that higher log level causes timing changes and thus may affect
- * performance.
- */
-enum debug_level {
-	DEBUG_DISABLE,
-	DEBUG_LEVEL_1,
-	DEBUG_LEVEL_2,
-	DEBUG_LEVEL_3,
-	DEBUG_LEVEL_MAX = DEBUG_LEVEL_3
-};
-
-/**
- * Changes a state machines state. This handles exiting the previous state and
- * entering the target state. A common parent state will not exited nor be
- * re-entered.
- *
- * @param port      USB-C port number
- * @param ctx       State machine context
- * @param new_state State to transition to (NULL is valid and exits all states)
- */
-void set_state(int port, struct sm_ctx *ctx, usb_state_ptr new_state);
-
-/**
- * Runs one iteration of a state machine (including any parent states)
- *
- * @param port USB-C port number
- * @param ctx  State machine context
- */
-void run_state(int port, struct sm_ctx *ctx);
-
-#ifdef TEST_BUILD
-/*
- * Struct for test builds that allow unit tests to easily iterate through
- * state machines
- */
-struct test_sm_data {
-	/* Base pointer of the state machine array */
-	const usb_state_ptr base;
-	/* Size fo the state machine array above */
-	const int size;
-	/* The array of names for states, can be NULL */
-	const char * const * const names;
-	/* The size of the above names array */
-	const int names_size;
-};
-#endif
-
-/* Creates a state machine state that will never link. Useful with IS_ENABLED */
-#define GEN_NOT_SUPPORTED(state) extern typeof(state) state ## _NOT_SUPPORTED
-
-#endif /* __CROS_EC_USB_SM_H */
diff --git a/include/usb_tbt_alt_mode.h b/include/usb_tbt_alt_mode.h
deleted file mode 100644
index 1ea4828059..0000000000
--- a/include/usb_tbt_alt_mode.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Thunderbolt alternate mode support
- * Refer to USB Type-C Cable and Connector Specification Release 2.0 Section F
- */
-
-#ifndef __CROS_EC_USB_TBT_ALT_MODE_H
-#define __CROS_EC_USB_TBT_ALT_MODE_H
-
-#include <stdint.h>
-
-#include "tcpm/tcpm.h"
-#include "usb_pd_tcpm.h"
-
-/*
- * Initialize Thunderbolt state for the specified port.
- *
- * @param port USB-C port number
- */
-void tbt_init(int port);
-
-/*
- * Requests to exit the Thunderbolt alternate mode
- *
- * @param port USB-C port number
- */
-void tbt_exit_mode_request(int port);
-
-/*
- * Checks whether Thunderbolt cable mode entry is required prior to entering
- * USB4.
- *
- * @param port      USB-C port number
- * @return          True if Thunderbolt cable mode entry is required
- *		    False otherwise
- */
-bool tbt_cable_entry_required_for_usb4(int port);
-
-/*
- * Checks whether the mode entry sequence for Thunderbolt alternate mode is
- * done for a port.
- *
- * @param port      USB-C port number
- * @return          True if entry sequence for Thunderbolt mode is completed
- *                  False otherwise
- */
-bool tbt_entry_is_done(int port);
-
-/*
- * Checks if the cable entry into Thunderbolt alternate mode is done
- *
- * @param port      USB-C port number
- * @return          True if TBT_FLAG_CABLE_ENTRY_DONE is set
- *                  False otherwise
- */
-bool tbt_cable_entry_is_done(int port);
-
-/*
- * Returns True if Thunderbolt mode is not in inactive state
- *
- * @param port      USB-C port number
- * @return          True if Thunderbolt mode is not in inactive state
- *                  False otherwise
- */
-bool tbt_is_active(int port);
-
-/*
- * Handles received Thunderbolt VDM ACKs.
- *
- * @param port      USB-C port number
- * @param type      Transmit type (SOP, SOP') for received ACK
- * @param vdo_count The number of VDOs in the ACK VDM
- * @param vdm       VDM from ACK
- */
-void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
-
-/*
- * Handles NAKed (or Not Supported or timed out) Thunderbolt VDM requests.
- *
- * @param port    USB-C port number
- * @param type    Transmit type (SOP, SOP') for request
- * @param svid    The SVID of the request
- * @param vdm_cmd The VDM command of the request
- */
-void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd);
-
-/*
- * Construct the next Thunderbolt VDM that should be sent.
- *
- * @param port      USB-C port number
- * @param vdo_count The number of VDOs in vdm; must be at least VDO_MAX_SIZE
- * @param vdm       The VDM payload to be sent; output; must point to at least
- *                  VDO_MAX_SIZE elements
- * @param tx_type   Transmit type(SOP, SOP', SOP'') for next VDM to be sent
- * @return          The number of VDOs written to VDM or -1 to indicate error
- */
-int tbt_setup_next_vdm(int port, int vdo_count, uint32_t *vdm,
-		enum tcpci_msg_type *tx_type);
-
-#endif
diff --git a/include/usb_tc_sm.h b/include/usb_tc_sm.h
deleted file mode 100644
index 71b895b78f..0000000000
--- a/include/usb_tc_sm.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USB Type-C module */
-
-#ifndef __CROS_EC_USB_TC_H
-#define __CROS_EC_USB_TC_H
-
-#include "usb_sm.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-enum try_src_override_t {
-	TRY_SRC_OVERRIDE_OFF,
-	TRY_SRC_OVERRIDE_ON,
-	TRY_SRC_NO_OVERRIDE
-};
-
-/*
- * Type C supply voltage (mV)
- *
- * This is the maximum voltage a sink can request
- * while charging.
- */
-#define TYPE_C_VOLTAGE  5000 /* mV */
-
-/*
- * Type C default sink current (mA)
- *
- * This is the maximum current a sink can draw if charging
- * while in the Audio Accessory State.
- */
-#define TYPE_C_AUDIO_ACC_CURRENT  500 /* mA */
-
-/**
- * Returns true if TypeC State machine is in attached source state.
- *
- * @param port USB-C port number
- * @return 1 if in attached source state, else 0
- */
-int tc_is_attached_src(int port);
-
-/**
- * Returns true if TypeC State machine is in attached sink state.
- *
- * @param port USB-C port number
- * @return 1 if in attached source state, else 0
- */
-int tc_is_attached_snk(int port);
-
-/**
- * Get cable plug setting. This should be constant per build. This replaces
- * the power role bit in PD header for SOP' and SOP" packets.
- *
- * @param port USB-C port number
- * @return PD cable plug setting
- */
-enum pd_cable_plug tc_get_cable_plug(int port);
-
-/**
- * Get current polarity
- *
- * @param port USB-C port number
- * @return 0 for CC1 as primary, 1 for CC2 as primary
- */
-uint8_t tc_get_polarity(int port);
-
-/**
- * Get Power Deliever communication state. If disabled, both protocol and policy
- * engine are disabled and should not run.
- *
- * @param port USB-C port number
- * @return 0 if pd is disabled, 1 is pd is enabled
- */
-uint8_t tc_get_pd_enabled(int port);
-
-/**
- * Set the power role
- *
- * @param port USB-C port number
- * @param role power role
- */
-void tc_set_power_role(int port, enum pd_power_role role);
-
-/**
- * Set the data role
- *
- * @param port USB-C port number
- * @param role data role
- */
-void tc_set_data_role(int port, enum pd_data_role role);
-
-/**
- * Sets the USB Mux depending on current data role
- *   Mux is connected except when:
- *     1) PD is disconnected
- *     2) Current data role is UFP and we only support DFP
- *
- *  @param port USB-C port number
- */
-void set_usb_mux_with_current_data_role(int port);
-
-/**
- * Policy Engine informs the Type-C state machine if the port partner
- * is dualrole power.
- *
- * @param port USB_C port number
- * @param en   1 if port partner is dualrole power, else 0
- */
-void tc_partner_dr_power(int port, int en);
-
-/**
- * Policy Engine informs the Type-C state machine if the port partner
- * has unconstrained power
- *
- * @param port USB_C port number
- * @param en   1 if port partner has unconstrained power, else 0
- */
-void tc_partner_unconstrainedpower(int port, int en);
-
-/**
- * Policy Engine informs the Type-C state machine if the port partner
- * is USB comms.
- *
- * @param port USB_C port number
- * @param en   1 if port partner is USB comms, else 0
- */
-void tc_partner_usb_comm(int port, int en);
-
-/**
- * Policy Engine informs the Type-C state machine if the port partner
- * is dualrole data.
- *
- * @param port USB_C port number
- * @param en   1 if port partner is dualrole data, else 0
- */
-void tc_partner_dr_data(int port, int en);
-
-/**
- * Policy Engine informs the Type-C state machine if the port partner
- * had a previous pd connection
- *
- * @param port USB_C port number
- * @param en   1 if port partner had a previous pd connection, else 0
- */
-void tc_pd_connection(int port, int en);
-
-/**
- * Initiates a Power Role Swap from Attached.SRC to Attached.SNK. This function
- * has no effect if the current Type-C state is not Attached.SRC.
- *
- * @param port USB_C port number
- */
-void tc_prs_src_snk_assert_rd(int port);
-
-/**
- * Initiates a Power Role Swap from Attached.SNK to Attached.SRC. This function
- * has no effect if the current Type-C state is not Attached.SNK.
- *
- * @param port USB_C port number
- */
-void tc_prs_snk_src_assert_rp(int port);
-
-/**
- * Informs the Type-C State Machine that a Power Role Swap is starting.
- * This function is called from the Policy Engine.
- *
- * @parm port USB_C port number
- */
-void tc_request_power_swap(int port);
-
-/**
- * Informs the Type-C State Machine that a Power Role Swap is complete.
- * This function is called from the Policy Engine.
- *
- * @param port USB_C port number
- * @param success swap completed normally
- */
-void tc_pr_swap_complete(int port, bool success);
-
-/**
- * Instructs the Attached.SNK to stop drawing power. This function is called
- * from the Policy Engine and only has effect if the current Type-C state
- * Attached.SNK.
- *
- * @param port USB_C port number
- */
-void tc_snk_power_off(int port);
-
-/**
- * Instructs the Attached.SRC to stop supplying power. The function has
- * no effect if the current Type-C state is not Attached.SRC.
- *
- * @param port USB_C port number
- */
-void tc_src_power_off(int port);
-
-/**
- * Instructs the Attached.SRC to start supplying power. The function has
- * no effect if the current Type-C state is not Attached.SRC.
- *
- * @param port USB_C port number
- */
-int tc_src_power_on(int port);
-
-/**
- * Tests if a VCONN Swap is possible.
- *
- * @param port USB_C port number
- * @return 1 if vconn swap is possible, else 0
- */
-int tc_check_vconn_swap(int port);
-
-/**
- * Checks if VCONN is being sourced.
- *
- * @param port USB_C port number
- * @return 1 if vconn is being sourced, 0 if it's not.
- */
-int tc_is_vconn_src(int port);
-
-/**
- * Instructs the Attached.SRC or Attached.SNK to start sourcing VCONN.
- * This function is called from the Policy Engine and only has effect
- * if the current Type-C state Attached.SRC or Attached.SNK.
- *
- * @param port USB_C port number
- */
-void pd_request_vconn_swap_on(int port);
-
-/**
- * Instructs the Attached.SRC or Attached.SNK to stop sourcing VCONN.
- * This function is called from the Policy Engine and only has effect
- * if the current Type-C state Attached.SRC or Attached.SNK.
- *
- * @param port USB_C port number
- */
-void pd_request_vconn_swap_off(int port);
-
-/**
- * Returns the polarity of a Sink.
- *
- * @param cc1 value of CC1 set by tcpm_get_cc
- * @param cc2 value of CC2 set by tcpm_get_cc
- * @return 0 if cc1 is connected, else 1 for cc2
- */
-enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
-
-/**
- * Called by the state machine framework to initialize the
- * TypeC state machine
- *
- * @param port USB-C port number
- */
-void tc_state_init(int port);
-
-/**
- * Called by the state machine framework to handle events
- * that affect the state machine as a whole
- *
- * @param port USB-C port number
- * @param evt event
- */
-void tc_event_check(int port, int evt);
-
-/**
- * Runs the TypeC layer statemachine
- *
- * @param port USB-C port number
- */
-void tc_run(const int port);
-
-/**
- * Sets the debug level for the TC layer
- *
- * @param level debug level
- */
-void tc_set_debug_level(enum debug_level level);
-
-/**
- * Start error recovery
- *
- * @param port USB-C port number
- */
-void tc_start_error_recovery(int port);
-
-/**
- * Hard Reset the TypeC port
- *
- * @param port USB-C port number
- */
-void tc_hard_reset_request(int port);
-
-/**
- * Hard Reset is complete for the TypeC port
- *
- * @param port USB-C port number
- */
-void tc_hard_reset_complete(int port);
-
-/**
- * Start the state machine event loop
- *
- * @param port USB-C port number
- */
-void tc_start_event_loop(int port);
-
-/**
- * Pauses the state machine event loop
- *
- * @param port USB-C port number
- */
-void tc_pause_event_loop(int port);
-
-/**
- * Determine if the state machine event loop is paused
- *
- * @param port USB-C port number
- * @return true if paused, else false
- */
-bool tc_event_loop_is_paused(int port);
-
-/**
- * Allow system to override the control of TrySrc
- *
- * @param en	TRY_SRC_OVERRIDE_OFF - Force TrySrc OFF
- *		TRY_SRC_OVERRIDE_ON - Force TrySrc ON
- *		TRY_SRC_NO_OVERRIDE - Allow state machine to control TrySrc
- */
-void tc_try_src_override(enum try_src_override_t ov);
-
-/**
- * Get state of try_src_override
- *
- * @return	TRY_SRC_OVERRIDE_OFF - TrySrc is forced OFF
- *		TRY_SRC_OVERRIDE_ON - TrySrc is forced ON
- *		TRY_SRC_NO_OVERRIDE - TypeC state machine controls TrySrc
- */
-enum try_src_override_t tc_get_try_src_override(void);
-
-/**
- * Returns the name of the current typeC state
- *
- * @param port USB-C port number
- * @return name of current typeC state
- */
-const char *tc_get_current_state(int port);
-
-/**
- * Returns the flag mask of the typeC state machine
- *
- * @param port USB-C port number
- * @return flag mask of the typeC state machine
- */
-uint32_t tc_get_flags(int port);
-
-/**
- * USB retimer firmware update set run flag
- * Setting this flag indicates firmware update operations can be
- * processed unconditionally.
- *
- * @param port USB-C port number
- */
-void tc_usb_firmware_fw_update_run(int port);
-
-/**
- * USB retimer firmware update set limited run flag
- * Setting this flag indicates firmware update operations can be
- * processed under limitation: PD task has to be suspended.
- *
- * @param port USB-C port number
- */
-void tc_usb_firmware_fw_update_limited_run(int port);
-
-#ifdef CONFIG_USB_CTVPD
-
-/**
- * Resets the charge-through support timer. This can be
- * called many times but the support timer will only
- * reset once, while in the Attached.SNK state.
- *
- * @param port USB-C port number
- */
-void tc_reset_support_timer(int port);
-
-#else
-
-/**
- *
- */
-void tc_ctvpd_detected(int port);
-#endif /* CONFIG_USB_CTVPD */
-#endif /* __CROS_EC_USB_TC_H */
-
diff --git a/include/usbc_ocp.h b/include/usbc_ocp.h
deleted file mode 100644
index d31ce57724..0000000000
--- a/include/usbc_ocp.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USBC_OCP_H
-#define __CROS_EC_USBC_OCP_H
-
-/* Common APIs for USB Type-C Overcurrent Protection (OCP) Module */
-
-/**
- * Increment the overcurrent event counter.
- *
- * @param port: The Type-C port that has overcurrented.
- * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port.
- */
-int usbc_ocp_add_event(int port);
-
-/**
- * Clear the overcurrent event counter
- *
- * @param port: The Type-C port number.
- * @return EC_SUCCESS on success, EC_ERROR_INVAL if non-existent port
- */
-int usbc_ocp_clear_event_counter(int port);
-
-/**
- * Is the port latched off due to multiple overcurrent events in succession?
- *
- * @param port: The Type-C port number.
- * @return 1 if the port is latched off, 0 if it is not latched off.
- */
-int usbc_ocp_is_port_latched_off(int port);
-
-/**
- * Register a port as having a sink connected
- *
- * @param port: The Type-C port number.
- * @param connected: true if sink is now connected on port
- */
-void usbc_ocp_snk_is_connected(int port, bool connected);
-
-/**
- * Board specific callback when a port overcurrents.
- *
- * @param port: The Type-C port which overcurrented.
- * @param is_overcurrented: 1 if port overcurrented, 0 if the condition is gone.
- */
-__override_proto void board_overcurrent_event(int port, int is_overcurrented);
-
-#endif /* !defined(__CROS_EC_USBC_OCP_H) */
diff --git a/include/usbc_ppc.h b/include/usbc_ppc.h
deleted file mode 100644
index 8c18857961..0000000000
--- a/include/usbc_ppc.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USBC_PPC_H
-#define __CROS_EC_USBC_PPC_H
-
-#include "common.h"
-#include "usb_pd_tcpm.h"
-
-/* Common APIs for USB Type-C Power Path Controllers (PPC) */
-
-/* The role of connected device. */
-enum ppc_device_role {
-	PPC_DEV_SNK,
-	PPC_DEV_SRC,
-	PPC_DEV_DISCONNECTED,
-};
-
-/*
- * NOTE: The pointers to functions in the ppc_drv structure can now be NULL
- * which will indicate and return NOT_IMPLEMENTED from the main calling
- * function
- */
-struct ppc_drv {
-	/**
-	 * Initialize the PPC.
-	 *
-	 * @param port: The Type-C port number.
-	 * @return EC_SUCCESS when init was successful, error otherwise.
-	 */
-	int (*init)(int port);
-
-	/**
-	 * Is the port sourcing Vbus?
-	 *
-	 * @param port: The Type-C port number.
-	 * @return 1 if sourcing Vbus, 0 if not.
-	 */
-	int (*is_sourcing_vbus)(int port);
-
-	/**
-	 * Turn on/off the charge path FET, such that current flows into the
-	 * system.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param enable: 1: Turn on the FET, 0: turn off the FET.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*vbus_sink_enable)(int port, int enable);
-
-	/**
-	 * Turn on/off the source path FET, such that current flows from the
-	 * system.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param enable: 1: Turn on the FET, 0: turn off the FET.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*vbus_source_enable)(int port, int enable);
-
-#ifdef CONFIG_USBC_PPC_POLARITY
-	/**
-	 * Inform the PPC of the polarity of the CC pins.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param polarity: 1: CC2 used for comms, 0: CC1 used for comms.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*set_polarity)(int port, int polarity);
-#endif
-
-	/**
-	 * Set the Vbus source path current limit
-	 *
-	 * @param port: The Type-C port number.
-	 * @param rp: The Rp value which to approximately set the current limit.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*set_vbus_source_current_limit)(int port, enum tcpc_rp_value rp);
-
-	/**
-	 * Discharge PD VBUS on src/sink disconnect & power role swap
-	 *
-	 * @param port: The Type-C port number.
-	 * @param enable: 1 -> discharge vbus, 0 -> stop discharging vbus
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*discharge_vbus)(int port, int enable);
-
-	/**
-	 * Inform the PPC of the device is connected or disconnected.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param dev: PPC_DEV_SNK if a sink is connected, PPC_DEV_SRC if a
-	 *             source is connected, PPC_DEV_DISCONNECTED if the device
-	 *             is disconnected.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*dev_is_connected)(int port, enum ppc_device_role dev);
-
-#ifdef CONFIG_USBC_PPC_SBU
-	/**
-	 * Turn on/off the SBU FETs.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param enable: 1: enable SBU FETs 0: disable SBU FETs.
-	 */
-	int (*set_sbu)(int port, int enable);
-#endif /* CONFIG_USBC_PPC_SBU */
-
-#ifdef CONFIG_USBC_PPC_VCONN
-	/**
-	 * Turn on/off the VCONN FET.
-	 *
-	 * @param port: The Type-C port number.
-	 * @param enable: 1: enable VCONN FET 0: disable VCONN FET.
-	 */
-	int (*set_vconn)(int port, int enable);
-#endif
-
-#ifdef CONFIG_USB_PD_FRS_PPC
-	/**
-	 * Turn on/off the FRS trigger
-	 *
-	 * @param port: The Type-C port number.
-	 * @return EC_SUCCESS on success, error otherwise
-	 */
-	int (*set_frs_enable)(int port, int enable);
-#endif
-
-#ifdef CONFIG_CMD_PPC_DUMP
-	/**
-	 * Perform a register dump of the PPC.
-	 *
-	 * @param port: The Type-C port number.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*reg_dump)(int port);
-#endif /* defined(CONFIG_CMD_PPC_DUMP) */
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-	/**
-	 * Determine if VBUS is present or not.
-	 *
-	 * @param port: The Type-C port number.
-	 * @return 1 if VBUS is present, 0 if not.
-	 */
-	int (*is_vbus_present)(int port);
-#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
-
-	/**
-	 * Optional method to put the PPC into its lowest power state. In this
-	 * state it should still fire interrupts if Vbus changes etc.
-	 *
-	 * @param port: The Type-C port number.
-	 * @return EC_SUCCESS on success, error otherwise.
-	 */
-	int (*enter_low_power_mode)(int port);
-};
-
-struct ppc_config_t {
-	int i2c_port;
-	uint16_t i2c_addr_flags;
-	const struct ppc_drv *drv;
-	int frs_en;
-};
-
-extern struct ppc_config_t ppc_chips[];
-extern unsigned int ppc_cnt;
-
-/**
- * Common CPRINTS implementation so that PPC driver messages are consistent.
- *
- * @param string: message string to display on the console.
- * @param port: The Type-C port number
- */
-int ppc_prints(const char *string, int port);
-
-/**
- * Common CPRINTS for PPC drivers with an error code.
- *
- * @param string: message string to display on the console.
- * @param port: The Type-C port number
- * @param error: The error code to display at the end of the message.
- */
-int ppc_err_prints(const char *string, int port, int error);
-
-/**
- * Discharge PD VBUS on src/sink disconnect & power role swap
- *
- * @param port: The Type-C port number.
- * @param enable: 1 -> discharge vbus, 0 -> stop discharging vbus
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_discharge_vbus(int port, int enable);
-
-/**
- * Initializes the PPC for the specified port.
- *
- * @param port: The Type-C port number.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_init(int port);
-
-/**
- * Is the port sourcing Vbus?
- *
- * @param port: The Type-C port number.
- * @return 1 if sourcing Vbus, 0 if not.
- */
-int ppc_is_sourcing_vbus(int port);
-
-/**
- * Determine if VBUS is present or not.
- *
- * @param port: The Type-C port number.
- * @return 1 if VBUS is present, 0 if not.
- */
-int ppc_is_vbus_present(int port);
-
-/**
- * Inform the PPC module that a device (either sink or source) is connected.
- *
- * This is used such that it can determine when to clear the overcurrent events,
- * and disable discharge VBUS on a source device connected.
- * @param port: The Type-C port number.
- * @param dev: PPC_DEV_SNK if a sink is connected, PPC_DEV_SRC if a source is
- *             connected, PPC_DEV_DISCONNECTED if the device is disconnected.
- */
-int ppc_dev_is_connected(int port, enum ppc_device_role dev);
-
-/**
- * Inform the PPC of the polarity of the CC pins.
- *
- * @param port: The Type-C port number.
- * @param polarity: 1: CC2 used for comms, 0: CC1 used for comms.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_set_polarity(int port, int polarity);
-
-/**
- * Set the Vbus source path current limit
- *
- * @param port: The Type-C port number.
- * @param rp: The Rp value which to approximately set the current limit.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp);
-
-/**
- * Turn on/off the SBU FETs.
- *
- * @param port: The Type-C port number.
- * @param enable: 1: enable SBU FETs 0: disable SBU FETs.
- */
-int ppc_set_sbu(int port, int enable);
-
-/**
- * Turn on/off the VCONN FET.
- *
- * @param port: The Type-C port number.
- * @param enable: 1: enable VCONN FET 0: disable VCONN FET.
- */
-int ppc_set_vconn(int port, int enable);
-
-/**
- * Turn on/off the charge path FET, such that current flows into the
- * system.
- *
- * @param port: The Type-C port number.
- * @param enable: 1: Turn on the FET, 0: turn off the FET.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_vbus_sink_enable(int port, int enable);
-
-/**
- * Turn on/off the source path FET, such that current flows from the
- * system.
- *
- * @param port: The Type-C port number.
- * @param enable: 1: Turn on the FET, 0: turn off the FET.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_vbus_source_enable(int port, int enable);
-
-/**
- * Put the PPC into its lowest power state. In this state it should still fire
- * interrupts if Vbus changes etc. This is called by board-specific code when
- * appropriate.
- *
- * @param port: The Type-C port number.
- * @return EC_SUCCESS on success, error otherwise.
- */
-int ppc_enter_low_power_mode(int port);
-
-/**
- * Board specific callback to check if the PPC interrupt is still asserted
- *
- * @param port: The Type-C port number to check
- * @return 0 if interrupt is cleared, 1 if it is still on
- */
-int ppc_get_alert_status(int port);
-
-/**
- * Turn on/off the FRS trigger
- *
- * @param port: The Type-C port number.
- * @return EC_SUCCESS on success, error otherwise
- */
-int ppc_set_frs_enable(int port, int enable);
-
-#endif /* !defined(__CROS_EC_USBC_PPC_H) */
diff --git a/include/vboot_hash.h b/include/vboot_hash.h
deleted file mode 100644
index 126872393e..0000000000
--- a/include/vboot_hash.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Verified boot hashing memory module for Chrome EC */
-
-#ifndef __CROS_EC_VBOOT_HASH_H
-#define __CROS_EC_VBOOT_HASH_H
-
-#include "common.h"
-
-/**
- * Get hash of RW image.
- *
- * Your task will be blocked until hash computation is done. Hashing can be
- * aborted only due to internal errors (e.g. read error) but not external
- * causes.
- *
- * This is expected to be called before tasks are initialized. If it's called
- * after tasks are started, it may starve lower priority tasks.
- *
- * See chromium:1047870 for some optimization.
- *
- * @param dst	(OUT) Address where computed hash is stored.
- * @return	enum ec_error_list.
- */
-int vboot_get_rw_hash(const uint8_t **dst);
-
-/**
- * Invalidate the hash if the hashed data overlaps the specified region.
- *
- * @param offset	Region start offset in flash
- * @param size		Size of region in bytes
- *
- * @return non-zero if the region overlapped the hashed region.
- */
-int vboot_hash_invalidate(int offset, int size);
-
-/**
- * Get vboot progress status.
- *
- * @return 1 if vboot hashing is in progress, 0 otherwise.
- */
-int vboot_hash_in_progress(void);
-
-/**
- * Abort hash currently in progress, and invalidate any completed hash.
- */
-void vboot_hash_abort(void);
-
-#endif  /* __CROS_EC_VBOOT_HASH_H */
diff --git a/include/wireless.h b/include/wireless.h
deleted file mode 100644
index d209d69fed..0000000000
--- a/include/wireless.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Wireless API for Chrome EC */
-
-#ifndef __CROS_EC_WIRELESS_H
-#define __CROS_EC_WIRELESS_H
-
-#include "common.h"
-
-/* Wireless power state for wireless_set_state() */
-enum wireless_power_state {
-	WIRELESS_OFF,
-	WIRELESS_SUSPEND,
-	WIRELESS_ON
-};
-
-/**
- * Set wireless power state.
- */
-#ifdef CONFIG_WIRELESS
-void wireless_set_state(enum wireless_power_state state);
-#else
-static inline void wireless_set_state(enum wireless_power_state state) { }
-#endif
-
-#endif  /* __CROS_EC_WIRELESS_H */
diff --git a/navbar.md b/navbar.md
deleted file mode 100644
index 8df90c7cc8..0000000000
--- a/navbar.md
+++ /dev/null
@@ -1,11 +0,0 @@
-# CrOS EC (Embedded Controller)
-
-[logo]: https://chromium-review.googlesource.com/plugins/chromium-style/static/chromium_logo.png
-[home]: /README.md
-
-*   [Home][home]
-*   [Documentation](/docs/sitemap.md)
-*   [Getting Started Quickly](/docs/getting_started_quickly.md)
-*   [File a Bug](https://bugs.chromium.org/p/chromium/issues/entry?components=OS%3EFirmware%3EEC)
-*   [Report Security Issue](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/reporting_bugs.md#security)
-*   [Chromium OS Docs](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/README.md)
diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c
deleted file mode 100644
index e7ae9497a2..0000000000
--- a/power/alderlake_slg4bd44540.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This was originally copied form power/icelake.c (also used on TGL and
- * ADL) and adapted to support ADL designs using the Silergy SLG4BD44540
- * power sequencer chip.
- */
-
-#include "board_config.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "power/alderlake_slg4bd44540.h"
-#include "power/intel_x86.h"
-#include "timer.h"
-
-/*
- * These delays are used by the brya power sequence reference design and
- * should be suitable for variants.
- */
-
-/* SEQ_EC_ALL_SYS_PG high to VCCST_PWRGD high delay */
-#define VCCST_PWRGD_DELAY_MS	2
-
-/* IMVP9_VRRDY high to PCH_PWROK high delay */
-#define PCH_PWROK_DELAY_MS	2
-
-/* SEQ_EC_ALL_SYS_PG high to EC_PCH_SYS_PWROK high delay */
-#define SYS_PWROK_DELAY_MS	45
-
-/* IMVP9_VRRDY high timeout */
-#define VRRDY_TIMEOUT_MS	50
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-#ifdef CONFIG_BRINGUP
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level_verbose(CC_CHIPSET, signal, value)
-#else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
-#endif
-
-/* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_DEASSERTED] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH |
-			POWER_SIGNAL_DISABLE_AT_BOOT,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_DEASSERTED] = {
-		.gpio = SLP_S3_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		.gpio = SLP_S4_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S4_DEASSERTED",
-	},
-	[X86_SLP_SUS_DEASSERTED] = {
-		.gpio = GPIO_SLP_SUS_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_SUS_DEASSERTED",
-	},
-	[X86_RSMRST_L_PGOOD] = {
-		.gpio = GPIO_PG_EC_RSMRST_ODL,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "RSMRST_L_PGOOD",
-	},
-	[X86_DSW_DPWROK] = {
-		.gpio = GPIO_PG_EC_DSW_PWROK,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "DSW_DPWROK",
-	},
-	[X86_ALL_SYS_PGOOD] = {
-		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "ALL_SYS_PWRGD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-__overridable int intel_x86_get_pg_ec_dsw_pwrok(void)
-{
-	return gpio_get_level(GPIO_PG_EC_DSW_PWROK);
-}
-
-__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
-{
-	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	int timeout_ms = 50;
-
-	CPRINTS("%s() %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Turn off RMSRST_L  to meet tPCH12 */
-	board_before_rsmrst(0);
-	GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
-	board_after_rsmrst(0);
-
-	/* Turn off S5 rails */
-	GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 0);
-
-	/*
-	 * TODO(b/179519791): Replace this wait with
-	 * power_wait_signals_timeout()
-	 */
-	/* Now wait for DSW_PWROK and  RSMRST_ODL to go away. */
-	while (intel_x86_get_pg_ec_dsw_pwrok() &&
-	       gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
-		msleep(1);
-		timeout_ms--;
-	};
-
-	if (!timeout_ms)
-		CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low!  Assuming G3.");
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/* No special handling needed. */
-}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-static void ap_off(void)
-{
-	GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 0);
-	GPIO_SET_LEVEL(GPIO_PCH_PWROK, 0);
-	GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 0);
-}
-
-/*
- * We have asserted VCCST_PWRGO_OD, now wait for the IMVP9.1
- * to assert IMVP9_VRRDY_OD.
- *
- * Returns state of VRRDY.
- */
-
-static int wait_for_vrrdy(void)
-{
-	int timeout_ms = VRRDY_TIMEOUT_MS;
-	int vrrdy;
-
-	for (; timeout_ms > 0; --timeout_ms) {
-		vrrdy = gpio_get_level(GPIO_IMVP9_VRRDY_OD);
-		if (vrrdy != 0)
-			return 1;
-		msleep(1);
-	}
-	return 0;
-}
-
-/*
- * The relationship between these signals is described in
- * Intel PDG #627205 rev. 0.81.
- *
- * tCPU16: >= 0
- *	VCCST_PWRGD to PCH_PWROK
- * tPLT05: >= 0
- *	SYS_ALL_PWRGD to SYS_PWROK
- *	PCH_PWROK to SYS_PWROK
- */
-
-static void all_sys_pwrgd_pass_thru(void)
-{
-	int sys_pg;
-	int vccst_pg;
-	int pch_pok;
-	int sys_pok;
-
-	sys_pg = gpio_get_level(GPIO_SEQ_EC_ALL_SYS_PG);
-
-	if (IS_ENABLED(CONFIG_BRINGUP))
-		CPRINTS("SEQ_EC_ALL_SYS_PG is %d", sys_pg);
-
-	if (sys_pg == 0) {
-		ap_off();
-		return;
-	}
-
-	/* SEQ_EC_ALL_SYS_PG is asserted, enable VCCST_PWRGD_OD. */
-
-	vccst_pg = gpio_get_level(GPIO_VCCST_PWRGD_OD);
-	if (vccst_pg == 0) {
-		msleep(VCCST_PWRGD_DELAY_MS);
-		GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 1);
-	}
-
-	/* Enable PCH_PWROK, gated by VRRDY. */
-
-	pch_pok = gpio_get_level(GPIO_PCH_PWROK);
-	if (pch_pok == 0) {
-		if (wait_for_vrrdy() == 0) {
-			CPRINTS("Timed out waiting for VRRDY, "
-				"shutting AP off!");
-			ap_off();
-			return;
-		}
-		msleep(PCH_PWROK_DELAY_MS);
-		GPIO_SET_LEVEL(GPIO_PCH_PWROK, 1);
-	}
-
-	/* Enable PCH_SYS_PWROK. */
-
-	sys_pok = gpio_get_level(GPIO_EC_PCH_SYS_PWROK);
-	if (sys_pok == 0) {
-		msleep(SYS_PWROK_DELAY_MS);
-		/* Check if we lost power while waiting. */
-		sys_pg = gpio_get_level(GPIO_SEQ_EC_ALL_SYS_PG);
-		if (sys_pg == 0) {
-			CPRINTS("SEQ_EC_ALL_SYS_PG deasserted, "
-				"shutting AP off!");
-			ap_off();
-			return;
-		}
-		GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 1);
-		/* PCH will now release PLT_RST */
-	}
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	all_sys_pwrgd_pass_thru();
-
-	common_intel_x86_handle_rsmrst(state);
-
-	switch (state) {
-
-	case POWER_G3S5:
-		GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1);
-
-		if (power_wait_signals(IN_PGOOD_ALL_CORE))
-			break;
-
-		/*
-		 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
-		 * signal doesn't go high within 250 msec then go back to G3.
-		 */
-		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
-			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
-			return POWER_S5G3;
-		}
-		break;
-
-	case POWER_S5:
-		/* If SLP_SUS_L is asserted, we're no longer in S5. */
-		if (!power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
-			return POWER_S5G3;
-		break;
-
-	default:
-		break;
-	}
-
-	return common_intel_x86_power_handle_state(state);
-}
diff --git a/power/amd_x86.c b/power/amd_x86.c
deleted file mode 100644
index c1b7b2d853..0000000000
--- a/power/amd_x86.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AMD x86 power sequencing module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-#include "registers.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
-
-#define IN_S5_PGOOD POWER_SIGNAL_MASK(X86_S5_PGOOD)
-
-static int forcing_shutdown; /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s()", __func__);
-
-	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
-		forcing_shutdown = 1;
-		power_button_pch_press();
-		report_ap_reset(reason);
-	}
-}
-
-static void chipset_force_g3(void)
-{
-	/* Disable system power ("*_A" rails) in G3. */
-	gpio_set_level(GPIO_EN_PWR_A, 0);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		CPRINTS("Can't reset: SOC is off");
-		return;
-	}
-
-	report_ap_reset(reason);
-	/*
-	 * Send a pulse to SYS_RST to trigger a warm reset.
-	 */
-	gpio_set_level(GPIO_SYS_RESET_L, 0);
-	usleep(32 * MSEC);
-	gpio_set_level(GPIO_SYS_RESET_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-	CPRINTS("%s(%d)", __func__, throttle);
-	if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW))
-		throttle = !throttle;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * eSPI_Reset# pin being asserted without RSMRST# being asserted
-	 * means there is an unexpected power loss (global reset event).
-	 * In this case, check if the shutdown is forced by the EC (due
-	 * to battery, thermal, or console command). The forced shutdown
-	 * initiates a power button press that we need to release.
-	 *
-	 * NOTE: S5_PGOOD input is passed through to the RSMRST# output to
-	 * the AP.
-	 */
-	if ((power_get_signals() & IN_S5_PGOOD) && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state power_chipset_init(void)
-{
-	CPRINTS("%s: power_signal=0x%x", __func__, power_get_signals());
-
-	if (!system_jumped_to_this_image())
-		return POWER_G3;
-	/*
-	 * We are here as RW. We need to handle the following cases:
-	 *
-	 * 1. Late sysjump by software sync. AP is in S0.
-	 * 2. Shutting down in recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence down.
-	 * 3. Rebooting from recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence up.
-	 * 4. RO jumps to RW from main() by EFS2. (a.k.a. power on reset, cold
-	 *    reset). AP is in G3.
-	 */
-	if (gpio_get_level(GPIO_S0_PGOOD)) {
-		/* case #1. Disable idle task deep sleep when in S0. */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		CPRINTS("already in S0");
-		return POWER_S0;
-	}
-	if (power_get_signals() & IN_S5_PGOOD) {
-		/* case #2 & #3 */
-		CPRINTS("already in S5");
-		return POWER_S5;
-	}
-	/* case #4 */
-	chipset_force_g3();
-	return POWER_G3;
-}
-
-static void handle_pass_through(enum gpio_signal pin_in,
-				enum gpio_signal pin_out)
-{
-	/*
-	 * Pass through asynchronously, as SOC may not react
-	 * immediately to power changes.
-	 */
-	int in_level = gpio_get_level(pin_in);
-	int out_level = gpio_get_level(pin_out);
-
-	/*
-	 * Only pass through high S0_PGOOD (S0 power) when S5_PGOOD (S5 power)
-	 * is also high (S0_PGOOD is pulled high in G3 when S5_PGOOD is low).
-	 */
-	if ((pin_in == GPIO_S0_PGOOD) && !gpio_get_level(GPIO_S5_PGOOD))
-		in_level = 0;
-
-	/* Nothing to do. */
-	if (in_level == out_level)
-		return;
-
-	/*
-	 * SOC requires a delay of 1ms with stable power before
-	 * asserting PWR_GOOD.
-	 */
-	if ((pin_in == GPIO_S0_PGOOD) && in_level)
-		msleep(1);
-
-	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_DELAY) &&
-	    (pin_out == GPIO_PCH_RSMRST_L) && in_level)
-		msleep(10);
-
-	gpio_set_level(pin_out, in_level);
-
-	CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level);
-}
-
-#ifdef CONFIG_POWER_S0IX
-/*
- * Backup copies of SCI and SMI mask to preserve across S0ix suspend/resume
- * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
- * operations and hence SCI/SMI masks are programmed only once during boot-up.
- *
- * These backup variables are set whenever host expresses its interest to
- * enter S0ix and then lpc_host_event_mask for SCI and SMI are cleared. When
- * host resumes from S0ix, masks from backup variables are copied over to
- * lpc_host_event_mask for SCI and SMI.
- */
-static host_event_t backup_sci_mask;
-static host_event_t backup_smi_mask;
-
-/*
- * Clear host event masks for SMI and SCI when host is entering S0ix. This is
- * done to prevent any SCI/SMI interrupts when the host is in suspend. Since
- * BIOS is not involved in the suspend path, EC needs to take care of clearing
- * these masks.
- */
-static void lpc_s0ix_suspend_clear_masks(void)
-{
-	backup_sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
-	backup_smi_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
-
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0);
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0);
-}
-
-/*
- * Restore host event masks for SMI and SCI when host exits S0ix. This is done
- * because BIOS is not involved in the resume path and so EC needs to restore
- * the masks from backup variables.
- */
-static void lpc_s0ix_resume_restore_masks(void)
-{
-	/*
-	 * No need to restore SCI/SMI masks if both backup_sci_mask and
-	 * backup_smi_mask are zero. This indicates that there was a failure to
-	 * enter S0ix(SLP_S0# assertion) and hence SCI/SMI masks were never
-	 * backed up.
-	 */
-	if (!backup_sci_mask && !backup_smi_mask)
-		return;
-
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, backup_smi_mask);
-
-	backup_sci_mask = backup_smi_mask = 0;
-}
-
-static void lpc_s0ix_hang_detected(void)
-{
-	/*
-	 * Wake up the AP so they don't just chill in a non-suspended state and
-	 * burn power. Overload a vaguely related event bit since event bits are
-	 * at a premium. If the system never entered S0ix, then manually set the
-	 * wake mask to pretend it did, so that the hang detect event wakes the
-	 * system.
-	 */
-	if (power_get_state() == POWER_S0) {
-		host_event_t sleep_wake_mask;
-
-		get_lazy_wake_mask(POWER_S0ix, &sleep_wake_mask);
-		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
-	}
-
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-static void handle_chipset_suspend(void)
-{
-	/* Clear masks before any hooks are run for suspend. */
-	lpc_s0ix_suspend_clear_masks();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, handle_chipset_suspend, HOOK_PRIO_FIRST);
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_STANDBY)) {
-		CPRINTS("chipset reset: exit s0ix");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-
-void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-#endif /* CONFIG_POWER_S0IX */
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-__overridable void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	/* Default weak implementation -- no action required. */
-}
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	power_board_handle_host_sleep_event(state);
-
-#ifdef CONFIG_POWER_S0IX
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * s0ix/s3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-
-		sleep_start_suspend(ctx, lpc_s0ix_hang_detected);
-		power_signal_enable_interrupt(GPIO_PCH_SLP_S0_L);
-	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		lpc_s0ix_resume_restore_masks();
-		power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L);
-		sleep_complete_resume(ctx);
-		/*
-		 * If the sleep signal timed out and never transitioned, then
-		 * the wake mask was modified to its suspend state (S0ix), so
-		 * that the event wakes the system. Explicitly restore the wake
-		 * mask to its S0 state now.
-		 */
-		power_update_wake_mask();
-	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
-		power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L);
-	}
-#endif /* CONFIG_POWER_S0IX */
-}
-#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-enum power_state power_handle_state(enum power_state state)
-{
-	handle_pass_through(GPIO_S5_PGOOD, GPIO_PCH_RSMRST_L);
-
-	handle_pass_through(GPIO_S0_PGOOD, GPIO_PCH_SYS_PWROK);
-
-	if (state == POWER_S5 && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_G3S5:
-		/* Exit SOC G3 */
-		/* Enable system power ("*_A" rails) in S5. */
-		gpio_set_level(GPIO_EN_PWR_A, 1);
-
-		/*
-		 * Callback to do pre-initialization within the context of
-		 * chipset task.
-		 */
-		if (IS_ENABLED(CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK))
-			chipset_pre_init_callback();
-
-		if (power_wait_signals(IN_S5_PGOOD)) {
-			chipset_force_g3();
-			return POWER_G3;
-		}
-
-		CPRINTS("Exit SOC G3");
-
-		return POWER_S5;
-
-	case POWER_S5:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) {
-			/* Power up to next state */
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S5S3:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * Clearing the S0ix flag on the path to S0
-		 * to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state();
-#endif
-		return POWER_S3;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S3S0:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		}
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		lpc_s3_resume_clear_masks();
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		return POWER_S0;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Required rail went away */
-			return POWER_S5G3;
-		}
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * SLP_S0 may assert in system idle scenario without a kernel
-		 * freeze call. This may cause interrupt storm since there is
-		 * no freeze/unfreeze of threads/process in the idle scenario.
-		 * Ignore the SLP_S0 assertions in idle scenario by checking
-		 * the host sleep state.
-		 */
-		else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S0IX_SUSPEND &&
-				gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) {
-			return POWER_S0S0ix;
-		}
-#endif
-		else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * Call hooks only if we haven't notified listeners of S0ix
-		 * resume.
-		 */
-		sleep_notify_transition(SLEEP_NOTIFY_RESUME,
-					HOOK_CHIPSET_RESUME);
-#endif
-		break;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-#ifdef CONFIG_POWER_S0IX
-		/* re-init S0ix flag */
-		power_reset_host_sleep_state();
-#endif
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		return POWER_S5;
-
-	case POWER_S5G3:
-		chipset_force_g3();
-
-		return POWER_G3;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
-		if ((gpio_get_level(GPIO_PCH_SLP_S0_L) == 1) &&
-		    (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) {
-			return POWER_S0ixS0;
-		} else if (!power_has_signals(IN_S5_PGOOD)) {
-			/* Lost power, start transition to G3 */
-			return POWER_S0;
-		}
-
-		break;
-
-	case POWER_S0S0ix:
-		/*
-		 * Call hooks only if we haven't notified listeners of S0ix
-		 * suspend.
-		 */
-		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
-					HOOK_CHIPSET_SUSPEND);
-		sleep_suspend_transition();
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S0ix.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S0ix;
-
-	case POWER_S0ixS0:
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		sleep_resume_transition();
-		return POWER_S0;
-#endif /* CONFIG_POWER_S0IX */
-	default:
-		break;
-	}
-	return state;
-}
diff --git a/power/apollolake.c b/power/apollolake.c
deleted file mode 100644
index 2aaf7fc533..0000000000
--- a/power/apollolake.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Apollolake chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power/intel_x86.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/*
- * force_shutdown is used to maintain chipset shutdown request. This request
- * needs to be handled from within the chipset task.
- */
-static int force_shutdown;
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-#ifdef CONFIG_POWER_S0IX
-	[X86_SLP_S0_N] = {
-		GPIO_PCH_SLP_S0_L,
-		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"SLP_S0_DEASSERTED",
-	},
-#endif
-	[X86_SLP_S3_N] = {
-		GPIO_PCH_SLP_S3_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_N] = {
-		GPIO_PCH_SLP_S4_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S4_DEASSERTED",
-	},
-	[X86_SUSPWRDNACK] = {
-		GPIO_SUSPWRDNACK,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SUSPWRDNACK_DEASSERTED",
-	},
-	[X86_ALL_SYS_PG] = {
-		GPIO_ALL_SYS_PGOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"ALL_SYS_PGOOD",
-	},
-	[X86_RSMRST_N] = {
-		GPIO_RSMRST_L_PGOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"RSMRST_L",
-	},
-	[X86_PGOOD_PP3300] = {
-		GPIO_PP3300_PG,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP3300_PG",
-	},
-	[X86_PGOOD_PP5000] = {
-		GPIO_PP5000_PG,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP5000_PG",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-__attribute__((weak)) void chipset_do_shutdown(void)
-{
-	/* Need to implement board specific shutdown */
-}
-
-static void internal_chipset_shutdown(void)
-{
-	/*
-	 * UART buffer gets overwritten by other tasks if it is not explicitly
-	 * flushed before printing it on the console by same task. Hence, clean
-	 * up the UART buffer so that all the debug messages are printed on the
-	 * UART console before doing shutdown.
-	 */
-	cflush();
-
-	CPRINTS("%s()", __func__);
-
-	force_shutdown = 0;
-	chipset_do_shutdown();
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * This function is called from multiple tasks and hence it is racy! But
-	 * since things are going down hard, it does not matter if some task
-	 * misses out.
-	 */
-	force_shutdown = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-}
-
-static void handle_all_sys_pgood(enum power_state state)
-{
-	/*
-	 * Pass through asynchronously, as SOC may not react
-	 * immediately to power changes.
-	 */
-	int in_level = gpio_get_level(GPIO_ALL_SYS_PGOOD);
-	int out_level = gpio_get_level(GPIO_PCH_SYS_PWROK);
-
-	/* Nothing to do. */
-	if (in_level == out_level)
-		return;
-
-	gpio_set_level(GPIO_PCH_SYS_PWROK, in_level);
-
-	CPRINTS("Pass through GPIO_ALL_SYS_PGOOD: %d", in_level);
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	enum power_state new_state;
-
-	/* Process ALL_SYS_PGOOD state changes. */
-	handle_all_sys_pgood(state);
-
-	if (state == POWER_S5 && !power_has_signals(IN_PGOOD_ALL_CORE)) {
-		/* Required rail went away */
-		internal_chipset_shutdown();
-
-		new_state = POWER_S5G3;
-		goto rsmrst_handle;
-
-	}
-
-	/* If force shutdown is requested, perform that. */
-	if (force_shutdown)
-		internal_chipset_shutdown();
-
-	new_state = common_intel_x86_power_handle_state(state);
-
-rsmrst_handle:
-
-	/*
-	 * Process RSMRST_L state changes:
-	 * RSMRST_L de-assertion is passed to SoC only on G3S5 to S5 transition.
-	 * RSMRST_L is also checked in some states and, if asserted, will
-	 * force shutdown.
-	 */
-	common_intel_x86_handle_rsmrst(new_state);
-
-	return new_state;
-}
-
-/**
- * chipset check if PLTRST# is valid.
- *
- * @return non-zero if PLTRST# is valid, 0 if invalid.
- */
-int chipset_pltrst_is_valid(void)
-{
-	/*
-	 * Invalid PLTRST# from SOC unless RSMRST#
-	 * from PMIC through EC to soc is deasserted.
-	 */
-	return (gpio_get_level(GPIO_RSMRST_L_PGOOD) &&
-		gpio_get_level(GPIO_PCH_RSMRST_L));
-}
diff --git a/power/braswell.c b/power/braswell.c
deleted file mode 100644
index 288092c795..0000000000
--- a/power/braswell.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 braswell chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-#include "registers.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_RSMRST_L_PWRGD          POWER_SIGNAL_MASK(X86_RSMRST_L_PWRGD)
-#define IN_ALL_SYS_PWRGD           POWER_SIGNAL_MASK(X86_ALL_SYS_PWRGD)
-#define IN_SLP_S3_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_SLP_S4_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_RSMRST_L_PWRGD)
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_ALL_SYS_PWRGD)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_ALL_SYS_PWRGD)
-/* Rails required for S5 */
-#define IN_PGOOD_S5          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-#ifndef CONFIG_PMIC
-	gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-	forcing_shutdown = 1;
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Send a reset pulse to the PCH.  This just causes it to
-	 * assert INIT# to the CPU without dropping power or asserting
-	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-	 * ms debounce time, so assert the signal for twice that.
-	 */
-	gpio_set_level(GPIO_PCH_RCIN_L, 0);
-	usleep(32 * MSEC);
-	gpio_set_level(GPIO_PCH_RCIN_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-	throttle = !throttle;
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Pause in S5 when shutting down. */
-	power_set_pause_in_s5(1);
-
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_PGOOD_S0) == IN_PGOOD_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/*wireless_set_state(WIRELESS_OFF);*/
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_G3S5:
-		/* Exit SOC G3 */
-#ifdef CONFIG_PMIC
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-#else
-		gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0);
-#endif
-		CPRINTS("Exit SOC G3");
-
-		if (power_wait_signals(IN_PGOOD_S5)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_G3;
-		}
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-		return POWER_S5;
-
-	case POWER_S5:
-		/* Check for SLP S4 */
-		if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S5S3:
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		return POWER_S3;
-
-
-	case POWER_S3:
-
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S3S0:
-		/* Enable wireless */
-
-		/*wireless_set_state(WIRELESS_ON);*/
-
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-			return POWER_S3S5;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Wait 15 ms after all voltages good.  100 ms is only needed
-		 * for PCIe devices; mini-PCIe devices should need only 10 ms.
-		 */
-		msleep(15);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-		gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu);
-#else
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-
-		/* Set SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-
-		return POWER_S0;
-
-
-	case POWER_S0:
-
-		if (!power_has_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S0S3;
-		}
-
-		if (!power_has_signals(IN_ALL_S0)) {
-			return POWER_S0S3;
-		}
-
-		break;
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-#ifndef CONFIG_PMIC
-		/* Clear SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Suspend wireless */
-
-		/*wireless_set_state(WIRELESS_SUSPEND);*/
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/*
-		 * in case shutdown is already done by apshutdown
-		 * (or chipset_force_shutdown()), SOC already lost
-		 * power and can't assert PMC_SUSPWRDNACK any more.
-		 */
-		if (forcing_shutdown) {
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-#ifndef CONFIG_PMIC
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#else
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-
-			forcing_shutdown = 0;
-
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		}
-
-		if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) {
-			/* Assert RSMRST# */
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-
-			/* Enter SOC G3 */
-#ifdef CONFIG_PMIC
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			udelay(1);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-#else
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#endif
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		} else {
-			CPRINTS("waiting for PMC_SUSPWRDNACK to assert!");
-			return POWER_S5;
-		}
-	}
-	return state;
-}
diff --git a/power/build.mk b/power/build.mk
deleted file mode 100644
index e2b86a055e..0000000000
--- a/power/build.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Power management for application processor and peripherals
-#
-
-power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=alderlake_slg4bd44540.o
-power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=intel_x86.o
-power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o
-power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
-power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
-power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o
-power-$(CONFIG_CHIPSET_COMETLAKE_DISCRETE)+=cometlake-discrete.o intel_x86.o
-power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
-power-$(CONFIG_CHIPSET_ICELAKE)+=icelake.o intel_x86.o
-power-$(CONFIG_CHIPSET_MT817X)+=mt817x.o
-power-$(CONFIG_CHIPSET_MT8183)+=mt8183.o
-power-$(CONFIG_CHIPSET_MT8192)+=mt8192.o
-power-$(CONFIG_CHIPSET_CEZANNE)+=amd_x86.o
-power-$(CONFIG_CHIPSET_RK3288)+=rk3288.o
-power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
-power-$(CONFIG_CHIPSET_SC7180)+=qcom.o
-power-$(CONFIG_CHIPSET_SC7280)+=qcom.o
-power-$(CONFIG_CHIPSET_SDM845)+=sdm845.o
-power-$(CONFIG_CHIPSET_SKYLAKE)+=skylake.o intel_x86.o
-power-$(CONFIG_CHIPSET_STONEY)+=amd_x86.o
-power-$(CONFIG_POWER_COMMON)+=common.o
-power-$(CONFIG_POWER_TRACK_HOST_SLEEP_STATE)+=host_sleep.o
diff --git a/power/cannonlake.c b/power/cannonlake.c
deleted file mode 100644
index 392db669df..0000000000
--- a/power/cannonlake.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cannonlake chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "power/cannonlake.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-
-	/*
-	 * Force off. Sending a reset command to the PMIC will power off
-	 * the EC, so simulate a long power button press instead. This
-	 * condition will reset once the state machine transitions to G3.
-	 * Consider reducing the latency here by changing the power off
-	 * hold time on the PMIC.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		report_ap_reset(reason);
-		forcing_shutdown = 1;
-		power_button_pch_press();
-	}
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
-	 * it means that there is an unexpected power loss (global reset
-	 * event). In this case, check if shutdown was being forced by pressing
-	 * power button. If yes, release power button.
-	 */
-	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state chipset_force_g3(void)
-{
-	int timeout = 50;
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	/* Turn off DSW load switch. */
-	gpio_set_level(GPIO_EN_PP3300_DSW, 0);
-
-	/* Now wait for DSW_PWROK to go away. */
-	while (gpio_get_level(GPIO_PMIC_DPWROK) && (timeout > 0)) {
-		msleep(1);
-		timeout--;
-	};
-
-	if (!timeout)
-		CPRINTS("DSW_PWROK didn't go low!  Assuming G3.");
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	enum power_state new_state;
-	int dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
-	static int dswpwrok_out = -1;
-
-	/* Pass-through DSW_PWROK to CNL. */
-	if (dswpwrok_in != dswpwrok_out) {
-		CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
-		gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
-		dswpwrok_out = dswpwrok_in;
-	}
-
-	common_intel_x86_handle_rsmrst(state);
-
-	if (state == POWER_S5 && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-
-	switch (state) {
-	case POWER_G3:
-		/* If SLP_SUS_L is deasserted, we're no longer in G3. */
-		if (power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
-			return POWER_S5;
-		break;
-
-	case POWER_G3S5:
-		/* Turn on the PP3300_DSW rail. */
-		gpio_set_level(GPIO_EN_PP3300_DSW, 1);
-		if (power_wait_signals(IN_PGOOD_ALL_CORE))
-			break;
-
-		/* Pass thru DSWPWROK again since we changed it. */
-		dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
-		gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
-		CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
-		dswpwrok_out = dswpwrok_in;
-
-		/* Enable the 5V rail. */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-		power_5v_enable(task_get_current(), 1);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-		gpio_set_level(GPIO_EN_PP5000, 1);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-		break;
-
-	case POWER_S5G3:
-		/* Turn off the 5V rail. */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-		power_5v_enable(task_get_current(), 0);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-		gpio_set_level(GPIO_EN_PP5000, 0);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-		break;
-
-	default:
-		break;
-	};
-
-	new_state = common_intel_x86_power_handle_state(state);
-
-	return new_state;
-}
diff --git a/power/cometlake-discrete.c b/power/cometlake-discrete.c
deleted file mode 100644
index a22e32a69f..0000000000
--- a/power/cometlake-discrete.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Chrome EC chipset power control for Cometlake with platform-controlled
- * discrete sequencing.
- */
-
-#include "adc.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[PP5000_A_PGOOD] = {
-		GPIO_PG_PP5000_A_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP5000_A_PGOOD",
-	},
-	[PP1800_A_PGOOD] = {
-		GPIO_PG_PP1800_A_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP1800_A_PGOOD",
-	},
-	[VPRIM_CORE_A_PGOOD] = {
-		GPIO_PG_VPRIM_CORE_A_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"VPRIM_CORE_A_PGOOD",
-	},
-	[PP1050_A_PGOOD] = {
-		GPIO_PG_PP1050_A_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP1050_A_PGOOD",
-	},
-	[OUT_PCH_RSMRST_DEASSERTED] = {
-		GPIO_PCH_RSMRST_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"OUT_PCH_RSMRST_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		SLP_S4_SIGNAL_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S4_DEASSERTED",
-	},
-	[PP2500_DRAM_PGOOD] = {
-		GPIO_PG_PP2500_DRAM_U_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP2500_DRAM_PGOOD",
-	},
-	[PP1200_DRAM_PGOOD] = {
-		GPIO_PG_PP1200_U_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP1200_DRAM_PGOOD",
-	},
-	[X86_SLP_S3_DEASSERTED] = {
-		SLP_S3_SIGNAL_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S3_DEASSERTED",
-	},
-	[PP950_VCCIO_PGOOD] = {
-		GPIO_PG_PP950_VCCIO_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PP950_VCCIO_PGOOD",
-	},
-	[X86_SLP_S0_DEASSERTED] = {
-		GPIO_PCH_SLP_S0_L,
-		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"SLP_S0_DEASSERTED",
-	},
-	[CPU_C10_GATE_DEASSERTED] = {
-		GPIO_CPU_C10_GATE_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"CPU_C10_GATE_DEASSERTED",
-	},
-	[IMVP8_READY] = {
-		GPIO_IMVP8_VRRDY_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"IMVP8_READY",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/*
- * The EC is responsible for most of the power-on sequence with this driver,
- * enabling rails and waiting for power-good signals from regulators before
- * continuing. The power sequencing works as follows.
- *
- * 1. From G3 (all-off), power is applied and EC power supplies come up.
- *    The power button task kicks off platform power-up as desired.
- * 2. Power up the platform to reach S5
- *   a. Enable PP5000_A and wait for PP5000_A_PGOOD.
- *   b. Enable PP3300_A (EN_ROA_RAILS).
- *   c. Wait for PP3300_A power good. This regulator doesn't provide a power
- *      good output, so the EC monitors ADC_SNS_PP3300.
- *   d. Enable PP1800_A and wait for PP1800_A_PGOOD.
- *   e. PP1800_A_PGOOD automatically enables PPVAR_VPRIM_CORE_A, which receives
- *      power from PP3300_A (hence PP3300_A must precede PP1800_A, even though
- *      PP1800_A draws power from PP3300_G which is guaranteed to already be on)
- *   f. PPVAR_VPRIM_CORE_A_PGOOD automatically enables PP1050_A
- *   g. Wait for PP1050_A_PGOOD, indicating that both PPVAR_VPRIM_CORE_A and
- *      PP1050_A are good.
- *   h. Wait 10ms to satisfy tPCH03, then bring the PCH out of reset by
- *      deasserting RSMRST.
- * 3. The PCH controls transition from S5 up to S3 and higher-power states.
- *   a. PCH deasserts SLP_S4, automatically turning on PP2500_DRAM_U and
- *      PP1200_DRAM_U.
- *   b. Wait for PP2500_DRAM_PGOOD and PP1200_DRAM_PGOOD.
- * 4. PCH deasserts SLP_S3 to switch to S0
- *   a. SLP_S3 transition automatically enables PP1050_ST_S.
- *   b. Wait for PP1050_ST_S good. The power good output from this regulator is
- *      not connected, so the EC monitors ADC_SNS_PP1050_ST_S.
- *   c. Turn on EN_S0_RAILS (enabling PP1200_PLLOC and PP1050_STG).
- *      VCCIO must not ramp up before VCCST, VCCSTG and memory rails are good
- *      (PDG figure 424, note 14).
- *   d. Wait 2ms (for EN_S0_RAILS load switches to turn on).
- *   e. Enable PP950_VCCIO.
- *   f. Wait for PG_PP950_VCCIO. Although the PCH may be asserting CPU_C10_GATED
- *      which holds the VCCIO regulator in a low-power mode, the regulator will
- *      turn on normally and assert power good then drop into low power mode
- *      and continue asserting power good.
- * 5. Transition fully to S0 following SLP_S0
- *   a. Assert VCCST_PWRGD. This notionally tracks PP1050_ST_S but must be
- *      deasserted in S3 and lower.
- *   b. Enable IMVP8_VR.
- *   c. Wait 2ms.
- *   d. Assert SYS_PWROK.
- *   e. Wait for IMVP8_VRRDY.
- *   f. Wait 2ms.
- *   g. Assert PCH_PWROK.
- *
- * When CPU_C10_GATED is asserted, we are free to disable PP1200_PLLOC and
- * PP1050_STG by deasserting EN_S0_RAILS to save some power. VCCIO is
- * automatically placed in low-power mode by CPU_C10_GATED, and no further
- * action is required- power-good signals will not change, just the relevant
- * load switches (which are specified to meet the platform's minimum turn-on
- * time when CPU_C10_GATED is deasserted again) are turned off. This gating is
- * done asynchronously directly in the interrupt handler because its timing is
- * very tight.
- *
- * For further reference, Figure 421 and Table 370 in the Comet Lake U PDG
- * summarizes platform power rail requirements in a reasonably easy-to-digest
- * manner, while section 12.11 (containing those diagrams) details the required
- * operation.
- */
-
-/*
- * Reverse of S0->S3 transition.
- *
- * This is a separate function so it can be reused when forcing shutdown due to
- * power failure or other reasons.
- *
- * This function may be called from an ISR (slp_s3_interrupt) so must not
- * assume that it's running in a regular task.
- */
-static void shutdown_s0_rails(void)
-{
-	board_enable_s0_rails(0);
-	/*
-	 * Deassert VCCST_PG as early as possible to satisfy tCPU22; VDDQ is
-	 * derived directly from SLP_S3.
-	 */
-	gpio_set_level(GPIO_VCCST_PG_OD, 0);
-	gpio_set_level(GPIO_EC_PCH_PWROK, 0);
-	gpio_set_level(GPIO_EC_PCH_SYS_PWROK, 0);
-	gpio_set_level(GPIO_EN_IMVP8_VR, 0);
-	gpio_set_level(GPIO_EN_S0_RAILS, 0);
-	/*
-	 * * tPCH10: PCH_PWROK to VCCIO off >400ns (but only on unexpected
-	 *   power-down)
-	 * * tPLT18: SLP_S3_L to VCCIO disable <200us
-	 *
-	 * tPCH10 is only 7 CPU cycles at 16 MHz so we should satisfy that
-	 * minimum time with no extra code, and sleeping is likely to cause
-	 * a delay that exceeds tPLT18.
-	 */
-	gpio_set_level(GPIO_EN_PP950_VCCIO, 0);
-}
-
-/*
- * Reverse of G3->S5 transition.
- *
- * This is a separate function so it can be reused when forcing shutdown due to
- * power failure or other reasons.
- */
-static void shutdown_s5_rails(void)
-{
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-	/* tPCH12: RSMRST to VCCPRIM (PPVAR_VPRIM_CORE_A) off >400ns */
-	usleep(1);
-	gpio_set_level(GPIO_EN_PP1800_A, 0);
-	gpio_set_level(GPIO_EN_ROA_RAILS, 0);
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 0);
-#else
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-#endif
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	shutdown_s0_rails();
-	/* S3->S5 is automatic based on SLP_S3 driving memory rails. */
-	shutdown_s5_rails();
-}
-
-void chipset_handle_espi_reset_assert(void) {}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-/*
- * Wait for a power rail on an analog channel to become good.
- *
- * @param channel	ADC channel to read
- * @param min_voltage	Minimum required voltage for rail (in mV)
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-static int power_wait_analog(enum adc_channel channel, int min_voltage)
-{
-	timestamp_t deadline;
-	int reading;
-
-	/* One second timeout */
-	deadline = get_time();
-	deadline.val += SECOND;
-
-	do {
-		reading = adc_read_channel(channel);
-		if (reading == ADC_READ_ERROR)
-			return EC_ERROR_HW_INTERNAL;
-		if (timestamp_expired(deadline, NULL))
-			return EC_ERROR_TIMEOUT;
-	} while (reading < min_voltage);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Force system power state if we time out waiting for a power rail to become
- * good.
- *
- * In general the new state is to transition down to the next lower-power state,
- * so if we time out in G3->S5 we return POWER_G3 to turn things off again and
- * if S3->S0 times out we return POWER_S3S5 for the same reason.
- *
- * Correct sequencing of rails that might already be enabled is handled by
- * chipset_force_shutdown(), so the caller of this function doesn't need to
- * clean up after itself.
- */
-static enum power_state pgood_timeout(enum power_state new_state)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-	return new_state;
-}
-
-/*
- * Called in the chipset task when power signal inputs change state.
- * If this doesn't request a different state, power_common_state handles it.
- *
- * @param state Current power state
- * @return New power state
- */
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3S5:
-		if (intel_x86_wait_power_up_ok() != EC_SUCCESS) {
-			chipset_force_shutdown(
-				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
-			return POWER_G3;
-		}
-		/* Power-up steps 2a-2h. */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-		power_5v_enable(task_get_current(), 1);
-#else
-		gpio_set_level(GPIO_EN_PP5000_A, 1);
-#endif
-		if (power_wait_signals(POWER_SIGNAL_MASK(PP5000_A_PGOOD)))
-			return pgood_timeout(POWER_S5G3);
-		gpio_set_level(GPIO_EN_ROA_RAILS, 1);
-		if (power_wait_analog(ADC_SNS_PP3300, 3000) != EC_SUCCESS)
-			return pgood_timeout(POWER_S5G3);
-		gpio_set_level(GPIO_EN_PP1800_A, 1);
-		if (power_wait_signals(POWER_SIGNAL_MASK(PP1800_A_PGOOD) |
-				       POWER_SIGNAL_MASK(PP1050_A_PGOOD)))
-			return pgood_timeout(POWER_S5G3);
-		msleep(10);	/* tPCH03: VCCPRIM good -> RSMRST >10ms */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-		break;
-
-	case POWER_S5G3:
-		shutdown_s5_rails();
-		break;
-
-	case POWER_S5S3:
-		/* Power-up steps 3a-3b. */
-		if (power_wait_signals(POWER_SIGNAL_MASK(PP2500_DRAM_PGOOD) |
-				       POWER_SIGNAL_MASK(PP1200_DRAM_PGOOD)))
-			return pgood_timeout(POWER_S3S5);
-		break;
-
-	case POWER_S3S0:
-		/* Power-up steps 4a-4f. */
-		if (power_wait_analog(ADC_SNS_PP1050, 1000) != EC_SUCCESS)
-			return pgood_timeout(POWER_S3S5);
-		gpio_set_level(GPIO_EN_S0_RAILS, 1);
-		msleep(2);
-		gpio_set_level(GPIO_EN_PP950_VCCIO, 1);
-		if (power_wait_signals(POWER_SIGNAL_MASK(PP950_VCCIO_PGOOD)))
-			return pgood_timeout(POWER_S3S5);
-
-		/* Power-up steps 5a-5h */
-		gpio_set_level(GPIO_VCCST_PG_OD, 1);
-		gpio_set_level(GPIO_EN_IMVP8_VR, 1);
-		msleep(2);
-		gpio_set_level(GPIO_EC_PCH_SYS_PWROK, 1);
-		if (power_wait_signals(POWER_SIGNAL_MASK(IMVP8_READY)))
-			return pgood_timeout(POWER_S3S5);
-		msleep(2);
-		gpio_set_level(GPIO_EC_PCH_PWROK, 1);
-
-		board_enable_s0_rails(1);
-		break;
-
-	case POWER_S0S3:
-		/*
-		 * Handled in the slp_s3_interrupt fast path, but also run
-		 * here in case we miss the interrupt somehow.
-		 */
-		shutdown_s0_rails();
-		break;
-
-	case POWER_S5:
-		/*
-		 * Return to G3 if S5 rails are not on, probably because of
-		 * a forced power-off.
-		 */
-		if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL) !=
-		    CHIPSET_G3S5_POWERUP_SIGNAL)
-			return POWER_S5G3;
-		break;
-
-	default:
-		break;
-	}
-
-	/*
-	 * Power-up steps 3a-3b (S5->S3 via IN_PGOOD_ALL_CORE) plus general
-	 * bookkeeping.
-	 */
-	return common_intel_x86_power_handle_state(state);
-}
-
-#ifdef CONFIG_VBOOT_EFS
-/*
- * Called in main() to ensure chipset power is in a good state.
- *
- * This may be useful because EC reset could happen under unexpected
- * conditions and we want to ensure that if the AP is wedged for some
- * reason (for instance) we unwedge it before continuing.
- *
- * Because power sequencing here is all EC-controlled and this is called
- * as part of the init sequence, we don't need to do anything- EC reset
- * implies power sequencing is all-off and we don't have any external
- * PMIC to synchronize state with.
- */
-void chipset_handle_reboot(void) {}
-#endif /* CONFIG_VBOOT_EFS */
-
-void c10_gate_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * Per PDG, gate VccSTG and VCCIO on (SLP_S3_L && CPU_C10_GATE_L).
-	 *
-	 * When in S3 we let the state machine do it since timing is less
-	 * critical; when in S0/S0ix we do it here because timing is very
-	 * tight.
-	 */
-	if (board_is_c10_gate_enabled() && gpio_get_level(GPIO_SLP_S3_L)) {
-		int enable_core = gpio_get_level(GPIO_CPU_C10_GATE_L);
-
-		gpio_set_level(GPIO_EN_S0_RAILS, enable_core);
-	}
-
-	return power_signal_interrupt(signal);
-}
-
-void slp_s3_interrupt(enum gpio_signal signal)
-{
-	if (!gpio_get_level(GPIO_SLP_S3_L)
-	    && chipset_in_state(CHIPSET_STATE_ON)) {
-		/* Falling edge on SLP_S3_L means dropping to S3 from S0 */
-		shutdown_s0_rails();
-	}
-
-	return power_signal_interrupt(signal);
-}
diff --git a/power/cometlake.c b/power/cometlake.c
deleted file mode 100644
index 1b73bcc296..0000000000
--- a/power/cometlake.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Cometlake chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_DEASSERTED] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH |
-			POWER_SIGNAL_DISABLE_AT_BOOT,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_DEASSERTED] = {
-		.gpio = SLP_S3_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		.gpio = SLP_S4_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S4_DEASSERTED",
-	},
-	[X86_RSMRST_L_PGOOD] = {
-		.gpio = GPIO_RSMRST_L_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "RSMRST_L_PGOOD",
-	},
-	[X86_PP5000_A_PGOOD] = {
-		.gpio = GPIO_PP5000_A_PG_OD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "PP5000_A_PGOOD",
-	},
-	[X86_ALL_SYS_PGOOD] = {
-		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "ALL_SYS_PWRGD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-/* Default no action, overwrite it in board.c if necessary*/
-__overridable void board_chipset_forced_shutdown(void)
-{
-        return;
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	int timeout_ms = 50;
-
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Turn off RSMRST_L to meet tPCH12 */
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-	/* Turn off A (except PP5000_A) rails*/
-	gpio_set_level(GPIO_EN_A_RAILS, 0);
-
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	/* Issue a request to turn off the rail. */
-	power_5v_enable(task_get_current(), 0);
-#else
-	/* Turn off PP5000_A rail */
-	gpio_set_level(GPIO_EN_PP5000_A, 0);
-#endif
-
-	/* For b:143440730, stop checking GPIO_ALL_SYS_PGOOD if system is
-	 * already force to G3.
-         */
-	board_chipset_forced_shutdown();
-
-	/* Need to wait a min of 10 msec before check for power good */
-	msleep(10);
-
-	/* Now wait for PP5000_A and RSMRST_L to go low */
-	while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
-		power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
-		msleep(1);
-		timeout_ms--;
-	};
-
-	if (!timeout_ms)
-		CPRINTS("PP5000_A rail still up!  Assuming G3.");
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
-	 * it means that there is an unexpected power loss (global reset
-	 * event). In this case, check if shutdown was being forced by pressing
-	 * power button. If yes, release power button.
-	 */
-	if ((power_get_signals() & IN_PGOOD_ALL_CORE) && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-/* Default no action, overwrite it in board.c if necessary*/
-__attribute__((weak)) void all_sys_pgood_check_reboot(void)
-{
-	return;
-}
-
-/* Called by APL power state machine when transitioning from G3 to S5 */
-void chipset_pre_init_callback(void)
-{
-	/* Enable 5.0V and 3.3V rails, and wait for Power Good */
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 1);
-#else
-	/* Turn on PP5000_A rail */
-	gpio_set_level(GPIO_EN_PP5000_A, 1);
-#endif
-	/* Turn on A (except PP5000_A) rails*/
-	gpio_set_level(GPIO_EN_A_RAILS, 1);
-
-	/*
-	 * The status of the 5000_A rail is verifed in the calling function via
-	 * power_wait_signals() as PP5000_A_PGOOD is included in the
-	 * CHIPSET_G3S5_POWERUP_SIGNAL macro.
-	 */
-
-	/* For b:143440730, system might hang-up before enter S0/S3. Check
-	 * GPIO_ALL_SYS_PGOOD here to make sure it will trigger every time.
-	 */
-	all_sys_pgood_check_reboot();
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-
-	int all_sys_pwrgd_in;
-	int all_sys_pwrgd_out;
-
-	/*
-	 * Check if RSMRST_L signal state has changed and if so, pass the new
-	 * value along to the PCH. However, if the new transition of RSMRST_L
-	 * from the Sielgo is from low to high, then gate this transition to the
-	 * AP by the PP5000_A rail. If the new transition is from high to low,
-	 * then pass that through regardless of the PP5000_A value.
-	 *
-	 * The PP5000_A power good signal will float high if the
-	 * regulator is not powered, so checking both that the EN and the PG
-	 * signals are high.
-	 */
-	if ((gpio_get_level(GPIO_PP5000_A_PG_OD) &&
-	     gpio_get_level(GPIO_EN_PP5000_A)) ||
-	    gpio_get_level(GPIO_PCH_RSMRST_L))
-		common_intel_x86_handle_rsmrst(state);
-
-	switch (state) {
-
-	case POWER_S5:
-		if (forcing_shutdown) {
-			power_button_pch_release();
-			forcing_shutdown = 0;
-		}
-		/* If RSMRST_L is asserted, we're no longer in S5. */
-		if (!power_has_signals(IN_PGOOD_ALL_CORE))
-			return POWER_S5G3;
-		break;
-
-	case POWER_S0:
-		/*
-		 * Check value of PG_EC_ALL_SYS_PWRGD to see if PCH_SYS_PWROK
-		 * needs to be changed. If it's low->high transition, requires a
-		 * 2msec delay.
-		 */
-		all_sys_pwrgd_in = gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
-		all_sys_pwrgd_out = gpio_get_level(GPIO_PCH_SYS_PWROK);
-
-		if (all_sys_pwrgd_in != all_sys_pwrgd_out) {
-			if (all_sys_pwrgd_in)
-				msleep(2);
-			gpio_set_level(GPIO_PCH_SYS_PWROK, all_sys_pwrgd_in);
-		}
-		break;
-
-	default:
-		break;
-	}
-
-	return common_intel_x86_power_handle_state(state);
-}
diff --git a/power/common.c b/power/common.c
deleted file mode 100644
index 0f83a2ce61..0000000000
--- a/power/common.c
+++ /dev/null
@@ -1,1117 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Common functionality across all chipsets */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "display_7seg.h"
-#include "espi.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lpc.h"
-#include "power.h"
-#include "power/intel_x86.h"
-#include "power/qcom.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/*
- * Default timeout in us; if we've been waiting this long for an input
- * transition, just jump to the next state.
- */
-#define DEFAULT_TIMEOUT SECOND
-
-/* Timeout for dropping back from S5 to G3 in seconds */
-#ifdef CONFIG_CMD_S5_TIMEOUT
-static int s5_inactivity_timeout = 10;
-#else
-static const int s5_inactivity_timeout = 10;
-#endif
-
-static const char * const state_names[] = {
-	"G3",
-	"S5",
-	"S3",
-	"S0",
-#ifdef CONFIG_POWER_S0IX
-	"S0ix",
-#endif
-	"G3->S5",
-	"S5->S3",
-	"S3->S0",
-	"S0->S3",
-	"S3->S5",
-	"S5->G3",
-#ifdef CONFIG_POWER_S0IX
-	"S0ix->S0",
-	"S0->S0ix",
-#endif
-};
-
-static uint32_t in_signals;   /* Current input signal states (IN_PGOOD_*) */
-static uint32_t in_want;      /* Input signal state we're waiting for */
-static uint32_t in_debug;     /* Signal values which print debug output */
-
-static enum power_state state = POWER_G3;  /* Current state */
-static int want_g3_exit;      /* Should we exit the G3 state? */
-static uint64_t last_shutdown_time; /* When did we enter G3? */
-
-#ifdef CONFIG_HIBERNATE
-/* Delay before hibernating, in seconds */
-static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC;
-#endif
-
-#ifdef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-/* Pause in S5 on shutdown? */
-static int pause_in_s5;
-#endif
-
-static bool want_reboot_ap_at_g3;/* Want to reboot AP from G3? */
-/* Want to reboot AP from G3 with delay? */
-static uint64_t reboot_ap_at_g3_delay;
-
-static enum ec_status
-host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_reboot_ap_on_g3_v1 *cmd = args->params;
-
-	/* Store request for processing at g3 */
-	want_reboot_ap_at_g3 = true;
-
-	switch (args->version) {
-	case 0:
-		break;
-	case 1:
-		/* Store user specified delay to wait in G3 state */
-		reboot_ap_at_g3_delay = cmd->reboot_ap_at_g3_delay;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3,
-		     host_command_reboot_ap_on_g3,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-__overridable int power_signal_get_level(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
-		/* Check signal is from GPIOs or VWs */
-		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire(signal);
-	}
-	return gpio_get_level(signal);
-}
-
-int power_signal_disable_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
-		/* Check signal is from GPIOs or VWs */
-		if (espi_signal_is_vw(signal))
-			return espi_vw_disable_wire_int(signal);
-	}
-	return gpio_disable_interrupt(signal);
-}
-
-int power_signal_enable_interrupt(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) {
-		/* Check signal is from GPIOs or VWs */
-		if (espi_signal_is_vw(signal))
-			return espi_vw_enable_wire_int(signal);
-	}
-	return gpio_enable_interrupt(signal);
-}
-
-int power_signal_is_asserted(const struct power_signal_info *s)
-{
-	return power_signal_get_level(s->gpio) ==
-		!!(s->flags & POWER_SIGNAL_ACTIVE_STATE);
-}
-
-#ifdef CONFIG_BRINGUP
-static const char *power_signal_get_name(enum gpio_signal signal)
-{
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
-		/* Check signal is from GPIOs or VWs */
-		if (espi_signal_is_vw(signal))
-			return espi_vw_get_wire_name(signal);
-	}
-	return gpio_get_name(signal);
-}
-#endif
-
-/**
- * Update input signals mask
- */
-static void power_update_signals(void)
-{
-	uint32_t inew = 0;
-	const struct power_signal_info *s = power_signal_list;
-	int i;
-
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
-		if (power_signal_is_asserted(s))
-			inew |= 1 << i;
-	}
-
-	if ((in_signals & in_debug) != (inew & in_debug))
-		CPRINTS("power in 0x%04x", inew);
-
-	in_signals = inew;
-}
-
-uint32_t power_get_signals(void)
-{
-	return in_signals;
-}
-
-int power_has_signals(uint32_t want)
-{
-	if ((in_signals & want) == want)
-		return 1;
-
-	CPRINTS("power lost input; wanted 0x%04x, got 0x%04x",
-		want, in_signals & want);
-
-	return 0;
-}
-
-int power_wait_signals(uint32_t want)
-{
-	int ret = power_wait_signals_timeout(want, DEFAULT_TIMEOUT);
-
-	if (ret == EC_ERROR_TIMEOUT)
-		CPRINTS("power timeout on input; wanted 0x%04x, got 0x%04x",
-			want, in_signals & want);
-	return ret;
-}
-
-int power_wait_signals_timeout(uint32_t want, int timeout)
-{
-	return power_wait_mask_signals_timeout(want, want, timeout);
-}
-
-int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout)
-{
-	in_want = want;
-	if (!mask)
-		return EC_SUCCESS;
-
-	while ((in_signals & mask) != in_want) {
-		if (task_wait_event(timeout) == TASK_EVENT_TIMER) {
-			power_update_signals();
-			return EC_ERROR_TIMEOUT;
-		}
-		/*
-		 * TODO(crosbug.com/p/23772): should really shrink the
-		 * remaining timeout if we woke up but didn't have all the
-		 * signals we wanted.  Also need to handle aborts if we're no
-		 * longer in the same state we were when we started waiting.
-		 */
-	}
-	return EC_SUCCESS;
-}
-
-void power_set_state(enum power_state new_state)
-{
-	/* Record the time we go into G3 */
-	if (new_state == POWER_G3)
-		last_shutdown_time = get_time().val;
-
-	/* Print out the RTC value to help correlate EC and kernel logs. */
-	print_system_rtc(CC_CHIPSET);
-
-	state = new_state;
-
-	/*
-	 * Reset want_g3_exit flag here to prevent the situation that if the
-	 * error handler in POWER_S5S3 decides to force shutdown the system and
-	 * the flag is set, the system will go to G3 and then immediately exit
-	 * G3 again.
-	 */
-	if (state == POWER_S5S3)
-		want_g3_exit = 0;
-}
-
-enum power_state power_get_state(void)
-{
-	return state;
-}
-
-#ifdef CONFIG_HOSTCMD_X86
-
-/* If host doesn't program s0ix lazy wake mask, use default s0ix mask */
-#define DEFAULT_WAKE_MASK_S0IX  (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-				EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
- /*
-  * Set the wake mask according to the current power state:
-  * 1. On transition to S0, wake mask is reset.
-  * 2. In non-S0 states, active mask set by host gets a higher preference.
-  * 3. If host has not set any active mask, then check if a lazy mask exists
-  *    for the current power state.
-  * 4. If state is S0ix and no lazy or active wake mask is set, then use default
-  *    S0ix mask to be compatible with older BIOS versions.
-  */
-
-void power_update_wake_mask(void)
-{
-	host_event_t wake_mask;
-	enum power_state state;
-
-	state = power_get_state();
-
-	if (state == POWER_S0)
-		wake_mask = 0;
-	else if (lpc_is_active_wm_set_by_host())
-		return;
-	else if (get_lazy_wake_mask(state, &wake_mask))
-		return;
-#ifdef CONFIG_POWER_S0IX
-	if ((state == POWER_S0ix) && (wake_mask == 0))
-		wake_mask = DEFAULT_WAKE_MASK_S0IX;
-#endif
-
-	lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask);
-}
- /*
-  * Set wake mask after power state has stabilized, 5ms after power state
-  * change. The reason for making this a deferred call is to avoid race
-  * conditions occurring from S0ix periodic wakes on the SoC.
-  */
-
-static void power_update_wake_mask_deferred(void);
-DECLARE_DEFERRED(power_update_wake_mask_deferred);
-
-static void power_update_wake_mask_deferred(void)
-{
-	hook_call_deferred(&power_update_wake_mask_deferred_data, -1);
-	power_update_wake_mask();
-}
-
-static void power_set_active_wake_mask(void)
-{
-	/*
-	 * Allow state machine to stabilize and update wake mask after 5msec. It
-	 * was observed that on platforms where host wakes up periodically from
-	 * S0ix for hardware book-keeping activities, there is a small window
-	 * where host is not really up and running software, but still SLP_S0#
-	 * is de-asserted and hence setting wake mask right away can cause user
-	 * wake events to be missed.
-	 *
-	 * Time for deferred callback was chosen to be 5msec based on the fact
-	 * that it takes ~2msec for the periodic wake cycle to complete on the
-	 * host for KBL.
-	 */
-	hook_call_deferred(&power_update_wake_mask_deferred_data,
-			   5 * MSEC);
-}
-
-#else
-static void power_set_active_wake_mask(void) { }
-#endif
-
-#ifdef CONFIG_HIBERNATE
-#ifdef CONFIG_BATTERY
-/*
- * Smart discharge system
- *
- * EC controls how the system discharges differently depending on the remaining
- * capacity and the expected hours to zero.
- *
- * 0          X1                X2                                   full
- * |----------|-------------------|------------------------------------|
- *    cutoff        stay-up                       safe
- *
- * EC cuts off the battery at X1 mAh and hibernates the system at X2 mAh. X1 and
- * X2 are derived from the cutoff and hibernation discharge rate, respectively.
- *
- * TODO: Learn discharge rates dynamically.
- *
- * TODO: Save sdzone in non-volatile memory and restore it when waking up from
- * cutoff or hibernation.
- */
-static struct smart_discharge_zone sdzone;
-
-static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args)
-{
-	static uint16_t hours_to_zero;
-	static struct discharge_rate drate;
-	const struct ec_params_smart_discharge *p = args->params;
-	struct ec_response_smart_discharge *r = args->response;
-
-	if (p->flags & EC_SMART_DISCHARGE_FLAGS_SET) {
-		int cap;
-
-		if (battery_full_charge_capacity(&cap))
-			return EC_RES_UNAVAILABLE;
-
-		if (p->drate.hibern < p->drate.cutoff)
-			/* Hibernation discharge rate should be always higher */
-			return EC_RES_INVALID_PARAM;
-		else if (p->drate.cutoff > 0 && p->drate.hibern > 0)
-			drate = p->drate;
-		else if (p->drate.cutoff == 0 && p->drate.hibern == 0)
-			;  /* no-op. use the current drate. */
-		else
-			return EC_RES_INVALID_PARAM;
-
-		/* Commit */
-		hours_to_zero = p->hours_to_zero;
-		sdzone.stayup = MIN(hours_to_zero * drate.hibern / 1000, cap);
-		sdzone.cutoff = MIN(hours_to_zero * drate.cutoff / 1000,
-				    sdzone.stayup);
-	}
-
-	/* Return the effective values. */
-	r->hours_to_zero = hours_to_zero;
-	r->dzone = sdzone;
-	r->drate = drate;
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE,
-		     hc_smart_discharge,
-		     EC_VER_MASK(0));
-
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
-{
-	int remain;
-
-	if (now < *target)
-		return CRITICAL_SHUTDOWN_IGNORE;
-
-	if (battery_remaining_capacity(&remain)) {
-		CPRINTS("SDC Failed to get remaining capacity");
-		return CRITICAL_SHUTDOWN_HIBERNATE;
-	}
-
-	if (remain < sdzone.cutoff) {
-		CPRINTS("SDC Cutoff");
-		return CRITICAL_SHUTDOWN_CUTOFF;
-	} else if (remain < sdzone.stayup) {
-		CPRINTS("SDC Stay-up");
-		return CRITICAL_SHUTDOWN_IGNORE;
-	}
-
-	CPRINTS("SDC Safe");
-	return CRITICAL_SHUTDOWN_HIBERNATE;
-}
-#else
-/* Default implementation for battery-less systems */
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
-{
-	return now > *target ?
-			CRITICAL_SHUTDOWN_HIBERNATE : CRITICAL_SHUTDOWN_IGNORE;
-}
-#endif	/* CONFIG_BATTERY */
-#endif	/* CONFIG_HIBERNATE */
-
-/**
- * Common handler for steady states
- *
- * @param state		Current power state
- * @return Updated power state
- */
-static enum power_state power_common_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		if (want_g3_exit || want_reboot_ap_at_g3) {
-			uint64_t i;
-
-			want_g3_exit = 0;
-			want_reboot_ap_at_g3 = false;
-			reboot_ap_at_g3_delay = reboot_ap_at_g3_delay * MSEC;
-			/*
-			 * G3->S0 transition should happen only after the
-			 * user specified delay. Hence, wait until the
-			 * user specified delay times out.
-			 */
-			for (i = 0; i < reboot_ap_at_g3_delay; i += 100)
-				msleep(100);
-			reboot_ap_at_g3_delay = 0;
-
-			return POWER_G3S5;
-		}
-
-		in_want = 0;
-#ifdef CONFIG_HIBERNATE
-		{
-			uint64_t target, now, wait;
-			if (extpower_is_present()) {
-				task_wait_event(-1);
-				break;
-			}
-
-			now = get_time().val;
-			target = last_shutdown_time +
-					(uint64_t)hibernate_delay * SECOND;
-			switch (board_system_is_idle(last_shutdown_time,
-						     &target, now)) {
-			case CRITICAL_SHUTDOWN_HIBERNATE:
-				CPRINTS("Hibernate due to G3 idle");
-				system_hibernate(0, 0);
-				break;
-#ifdef CONFIG_BATTERY_CUT_OFF
-			case CRITICAL_SHUTDOWN_CUTOFF:
-				CPRINTS("Cutoff due to G3 idle");
-				/* Ensure logs are flushed. */
-				cflush();
-				board_cut_off_battery();
-				break;
-#endif
-			case CRITICAL_SHUTDOWN_IGNORE:
-			default:
-				break;
-			}
-
-			wait = MIN(target - now, TASK_MAX_WAIT_US);
-			task_wait_event(wait);
-		}
-#else /* !CONFIG_HIBERNATE */
-		task_wait_event(-1);
-#endif
-		break;
-
-	case POWER_S5:
-		/*
-		 * If the power button is pressed before S5 inactivity timer
-		 * expires, the timer will be cancelled and the task of the
-		 * power state machine will be back here again. Since we are
-		 * here, which means the system has been waiting for CPU
-		 * starting up, we don't need want_g3_exit flag to be set
-		 * anymore. Therefore, we can reset the flag here to prevent
-		 * the situation that the flag is still set after S5 inactivity
-		 * timer expires, which can cause the system to exit G3 again.
-		 */
-		want_g3_exit = 0;
-
-		power_wait_signals(0);
-
-		/* Wait for inactivity timeout, if desired */
-		if (s5_inactivity_timeout == 0) {
-			return POWER_S5G3;
-		} else if (s5_inactivity_timeout < 0) {
-			task_wait_event(-1);
-		} else if (task_wait_event(s5_inactivity_timeout * SECOND) ==
-			   TASK_EVENT_TIMER) {
-			/* Prepare to drop to G3; wake not requested yet */
-			return POWER_S5G3;
-		}
-		break;
-
-	case POWER_S3:
-		/* Wait for a message */
-		power_wait_signals(0);
-		task_wait_event(-1);
-		break;
-
-	case POWER_S0:
-		/* Wait for a message */
-		power_wait_signals(0);
-		task_wait_event(-1);
-		break;
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-		/* Wait for a message */
-		power_wait_signals(0);
-		task_wait_event(-1);
-		break;
-#endif
-	default:
-		/* No common functionality for transition states */
-		break;
-	}
-
-	return state;
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-int chipset_in_state(int state_mask)
-{
-	int need_mask = 0;
-
-	/*
-	 * TODO(crosbug.com/p/23773): what to do about state transitions?  If
-	 * the caller wants HARD_OFF|SOFT_OFF and we're in G3S5, we could still
-	 * return non-zero.
-	 */
-	switch (state) {
-	case POWER_G3:
-		need_mask = CHIPSET_STATE_HARD_OFF;
-		break;
-	case POWER_G3S5:
-	case POWER_S5G3:
-		/*
-		 * In between hard and soft off states.  Match only if caller
-		 * will accept both.
-		 */
-		need_mask = CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF;
-		break;
-	case POWER_S5:
-		need_mask = CHIPSET_STATE_SOFT_OFF;
-		break;
-	case POWER_S5S3:
-	case POWER_S3S5:
-		need_mask = CHIPSET_STATE_SOFT_OFF | CHIPSET_STATE_SUSPEND;
-		break;
-	case POWER_S3:
-		need_mask = CHIPSET_STATE_SUSPEND;
-		break;
-	case POWER_S3S0:
-	case POWER_S0S3:
-		need_mask = CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON;
-		break;
-	case POWER_S0:
-		need_mask = CHIPSET_STATE_ON;
-		break;
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ixS0:
-	case POWER_S0S0ix:
-		need_mask = CHIPSET_STATE_ON | CHIPSET_STATE_STANDBY;
-		break;
-	case POWER_S0ix:
-		need_mask = CHIPSET_STATE_STANDBY;
-		break;
-#endif
-	}
-
-	/* Return non-zero if all needed bits are present */
-	return (state_mask & need_mask) == need_mask;
-}
-
-int chipset_in_or_transitioning_to_state(int state_mask)
-{
-	switch (state) {
-	case POWER_G3:
-	case POWER_S5G3:
-		return state_mask & CHIPSET_STATE_HARD_OFF;
-	case POWER_S5:
-	case POWER_G3S5:
-	case POWER_S3S5:
-		return state_mask & CHIPSET_STATE_SOFT_OFF;
-	case POWER_S3:
-	case POWER_S5S3:
-	case POWER_S0S3:
-		return state_mask & CHIPSET_STATE_SUSPEND;
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-	case POWER_S0S0ix:
-		return state_mask & CHIPSET_STATE_STANDBY;
-#endif
-	case POWER_S0:
-	case POWER_S3S0:
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ixS0:
-#endif
-		return state_mask & CHIPSET_STATE_ON;
-	}
-
-	/* Unknown power state; return false. */
-	return 0;
-}
-
-void chipset_exit_hard_off(void)
-{
-	/*
-	 * If not in the soft-off state, hard-off state, or headed there,
-	 * nothing to do.
-	 */
-	if (state != POWER_G3 && state != POWER_S5G3 && state != POWER_S5)
-		return;
-
-	/*
-	 * Set a flag to leave G3, then wake the task. If the power state is
-	 * POWER_S5G3, or is POWER_S5 but the S5 inactivity timer has
-	 * expired, set this flag can let system go to G3 and then exit G3
-	 * immediately for powering on.
-	 */
-	want_g3_exit = 1;
-
-	/*
-	 * If the power state is in POWER_S5 and S5 inactivity timer is
-	 * running, to wake the chipset task can cancel S5 inactivity timer and
-	 * then restart the timer. This will give cpu a chance to start up if
-	 * S5 inactivity timer is about to expire while power button is
-	 * pressed. For other states here, to wake the chipset task to trigger
-	 * the event for leaving G3 is necessary.
-	 */
-	task_wake(TASK_ID_CHIPSET);
-}
-
-/*****************************************************************************/
-/* Task function */
-
-void chipset_task(void *u)
-{
-	enum power_state new_state;
-	static enum power_state last_state;
-	uint32_t this_in_signals;
-	static uint32_t last_in_signals;
-
-	while (1) {
-		/*
-		 * In order to prevent repeated console spam, only print the
-		 * current power state if something has actually changed.  It's
-		 * possible that one of the power signals goes away briefly and
-		 * comes back by the time we update our in_signals.
-		 */
-		this_in_signals = in_signals;
-		if (this_in_signals != last_in_signals || state != last_state) {
-			CPRINTS("power state %d = %s, in 0x%04x",
-				state, state_names[state], this_in_signals);
-			if (IS_ENABLED(CONFIG_SEVEN_SEG_DISPLAY))
-				display_7seg_write(SEVEN_SEG_EC_DISPLAY, state);
-			last_in_signals = this_in_signals;
-			last_state = state;
-		}
-
-		/* Always let the specific chipset handle the state first */
-		new_state = power_handle_state(state);
-
-		/*
-		 * If the state hasn't changed, run common steady-state
-		 * handler.
-		 */
-		if (new_state == state)
-			new_state = power_common_state(state);
-
-		/* Handle state changes */
-		if (new_state != state) {
-			power_set_state(new_state);
-			power_set_active_wake_mask();
-
-			/* Call hooks before we enter G3 */
-			if (new_state == POWER_G3)
-				hook_notify(HOOK_CHIPSET_HARD_OFF);
-		}
-	}
-}
-
-/*****************************************************************************/
-/* Hooks */
-
-static void power_common_init(void)
-{
-	const struct power_signal_info *s = power_signal_list;
-	int i;
-
-	/* Update input state */
-	power_update_signals();
-
-	/* Enable interrupts for input signals */
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++)
-		if (s->flags & POWER_SIGNAL_DISABLE_AT_BOOT)
-			power_signal_disable_interrupt(s->gpio);
-		else
-			power_signal_enable_interrupt(s->gpio);
-
-	/* Call chipset-specific init to set initial state */
-	power_set_state(power_chipset_init());
-
-	/*
-	 * Update input state again since there is a small window
-	 * before GPIO is enabled.
-	 */
-	power_update_signals();
-}
-DECLARE_HOOK(HOOK_INIT, power_common_init, HOOK_PRIO_INIT_CHIPSET);
-
-static void power_lid_change(void)
-{
-	/* Wake up the task to update power state */
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, power_lid_change, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_EXTPOWER
-static void power_ac_change(void)
-{
-	if (extpower_is_present()) {
-		CPRINTS("AC on");
-	} else {
-		CPRINTS("AC off");
-
-		if (state == POWER_G3) {
-			last_shutdown_time = get_time().val;
-			task_wake(TASK_ID_CHIPSET);
-		}
-	}
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, power_ac_change, HOOK_PRIO_DEFAULT);
-#endif
-
-/*****************************************************************************/
-/* Interrupts */
-
-#ifdef CONFIG_BRINGUP
-#define MAX_SIGLOG_ENTRIES 24
-
-static unsigned int siglog_entries;
-static unsigned int siglog_truncated;
-
-static struct {
-	timestamp_t time;
-	enum gpio_signal signal;
-	int level;
-} siglog[MAX_SIGLOG_ENTRIES];
-
-static void siglog_deferred(void)
-{
-	unsigned int i;
-	timestamp_t tdiff = {.val = 0};
-
-	/* Disable interrupts for input signals while we print stuff.*/
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++)
-		power_signal_disable_interrupt(power_signal_list[i].gpio);
-
-	CPRINTF("%d signal changes:\n", siglog_entries);
-	for (i = 0; i < siglog_entries; i++) {
-		if (i)
-			tdiff.val = siglog[i].time.val - siglog[i-1].time.val;
-		CPRINTF("  %.6lld  +%.6lld  %s => %d\n",
-			siglog[i].time.val, tdiff.val,
-			power_signal_get_name(siglog[i].signal),
-			siglog[i].level);
-	}
-	if (siglog_truncated)
-		CPRINTF("  SIGNAL LOG TRUNCATED...\n");
-	siglog_entries = siglog_truncated = 0;
-
-	/* Okay, turn 'em on again. */
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++)
-		power_signal_enable_interrupt(power_signal_list[i].gpio);
-}
-DECLARE_DEFERRED(siglog_deferred);
-
-static void siglog_add(enum gpio_signal signal)
-{
-	if (siglog_entries >= MAX_SIGLOG_ENTRIES) {
-		siglog_truncated = 1;
-		return;
-	}
-
-	siglog[siglog_entries].time = get_time();
-	siglog[siglog_entries].signal = signal;
-	siglog[siglog_entries].level = power_signal_get_level(signal);
-	siglog_entries++;
-
-	hook_call_deferred(&siglog_deferred_data, SECOND);
-}
-
-#define SIGLOG(S) siglog_add(S)
-
-#else
-#define SIGLOG(S)
-#endif	/* CONFIG_BRINGUP */
-
-#ifdef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
-/*
- * Print an interrupt storm warning when we receive more than
- * CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD interrupts of a
- * single source within 1 second.
- */
-static int power_signal_interrupt_count[POWER_SIGNAL_COUNT];
-
-static void reset_power_signal_interrupt_count(void)
-{
-	int i;
-
-	for (i = 0; i < POWER_SIGNAL_COUNT; ++i)
-		power_signal_interrupt_count[i] = 0;
-}
-DECLARE_HOOK(HOOK_SECOND,
-	     reset_power_signal_interrupt_count,
-	     HOOK_PRIO_DEFAULT);
-#endif
-
-void power_signal_interrupt(enum gpio_signal signal)
-{
-#ifdef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
-	int i;
-
-	/* Tally our interrupts and print a warning if necessary. */
-	for (i = 0; i < POWER_SIGNAL_COUNT; ++i) {
-		if (power_signal_list[i].gpio == signal) {
-			if (power_signal_interrupt_count[i]++ ==
-			   CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD)
-				CPRINTS("Interrupt storm! Signal %d", i);
-			break;
-		}
-	}
-#endif
-
-	SIGLOG(signal);
-
-	/* Shadow signals and compare with our desired signal state. */
-	power_update_signals();
-
-	/* Wake up the task */
-	task_wake(TASK_ID_CHIPSET);
-}
-
-#ifdef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-inline int power_get_pause_in_s5(void)
-{
-	return pause_in_s5;
-}
-
-inline void power_set_pause_in_s5(int pause)
-{
-	pause_in_s5 = pause;
-}
-#endif
-
-/*****************************************************************************/
-/* Console commands */
-
-static int command_powerinfo(int argc, char **argv)
-{
-	/*
-	 * Print power state in same format as state machine.  This is
-	 * used by FAFT tests, so must match exactly.
-	 */
-	ccprintf("power state %d = %s, in 0x%04x\n",
-		 state, state_names[state], in_signals);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo,
-			NULL,
-			"Show current power state");
-
-#ifdef CONFIG_CMD_POWERINDEBUG
-static int command_powerindebug(int argc, char **argv)
-{
-	const struct power_signal_info *s = power_signal_list;
-	int i;
-	char *e;
-
-	/* If one arg, set the mask */
-	if (argc == 2) {
-		int m = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		in_debug = m;
-	}
-
-	/* Print the mask */
-	ccprintf("power in:   0x%04x\n", in_signals);
-	ccprintf("debug mask: 0x%04x\n", in_debug);
-
-	/* Print the decode */
-
-	ccprintf("bit meanings:\n");
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
-		int mask = 1 << i;
-		ccprintf("  0x%04x %d %s\n",
-			 mask, in_signals & mask ? 1 : 0, s->name);
-	}
-
-	return EC_SUCCESS;
-};
-DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug,
-			"[mask]",
-			"Get/set power input debug mask");
-#endif
-
-#ifdef CONFIG_CMD_S5_TIMEOUT
-/* Allow command-line access to configure our S5 delay for power testing */
-static int command_s5_timeout(int argc, char **argv)
-{
-	char *e;
-
-	if (argc >= 2) {
-		uint32_t s = strtoi(argv[1], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		s5_inactivity_timeout = s;
-	}
-
-	/* Print the current setting */
-	ccprintf("S5 inactivity timeout: %d s\n", s5_inactivity_timeout);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout,
-			"[sec]",
-			"Set the timeout from S5 to G3 transition, "
-			"-1 to indicate no transition");
-#endif
-
-#ifdef CONFIG_HIBERNATE
-static int command_hibernation_delay(int argc, char **argv)
-{
-	char *e;
-	uint32_t time_g3 = ((uint32_t)(get_time().val - last_shutdown_time))
-				/ SECOND;
-
-	if (argc >= 2) {
-		uint32_t s = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		hibernate_delay = s;
-	}
-
-	/* Print the current setting */
-	ccprintf("Hibernation delay: %d s\n", hibernate_delay);
-	if (state == POWER_G3 && !extpower_is_present()) {
-		ccprintf("Time G3: %d s\n", time_g3);
-		ccprintf("Time left: %d s\n", hibernate_delay - time_g3);
-	}
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay,
-			"[sec]",
-			"Set the delay before going into hibernation");
-
-static enum ec_status
-host_command_hibernation_delay(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_hibernation_delay *p = args->params;
-	struct ec_response_hibernation_delay *r = args->response;
-
-	uint32_t time_g3;
-	uint64_t t = get_time().val - last_shutdown_time;
-
-	uint64divmod(&t, SECOND);
-	time_g3 = (uint32_t)t;
-
-	/* Only change the hibernation delay if seconds is non-zero. */
-	if (p->seconds)
-		hibernate_delay = p->seconds;
-
-	if (state == POWER_G3 && !extpower_is_present())
-		r->time_g3 = time_g3;
-	else
-		r->time_g3 = 0;
-
-	if ((time_g3 != 0) && (time_g3 > hibernate_delay))
-		r->time_remaining = 0;
-	else
-		r->time_remaining = hibernate_delay - time_g3;
-	r->hibernate_delay = hibernate_delay;
-
-	args->response_size = sizeof(struct ec_response_hibernation_delay);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY,
-		     host_command_hibernation_delay,
-		     EC_VER_MASK(0));
-#endif /* CONFIG_HIBERNATE */
-
-#ifdef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-static enum ec_status
-host_command_pause_in_s5(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_get_set_value *p = args->params;
-	struct ec_response_get_set_value *r = args->response;
-
-	if (p->flags & EC_GSV_SET)
-		pause_in_s5 = p->value;
-
-	r->value = pause_in_s5;
-
-	args->response_size = sizeof(*r);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5,
-		     host_command_pause_in_s5,
-		     EC_VER_MASK(0));
-
-static int command_pause_in_s5(int argc, char **argv)
-{
-	if (argc > 1 && !parse_bool(argv[1], &pause_in_s5))
-		return EC_ERROR_INVAL;
-
-	ccprintf("pause_in_s5 = %s\n", pause_in_s5 ? "on" : "off");
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5,
-			"[on|off]",
-			"Should the AP pause in S5 during shutdown?");
-#endif /* CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 */
-
-#ifdef CONFIG_POWER_PP5000_CONTROL
-__overridable void board_power_5v_enable(int enable)
-{
-	if (enable)
-		gpio_set_level(GPIO_EN_PP5000, 1);
-	else
-		gpio_set_level(GPIO_EN_PP5000, 0);
-}
-
-/* 5V enable request bitmask from various tasks. */
-static uint32_t pwr_5v_en_req;
-K_MUTEX_DEFINE(pwr_5v_ctl_mtx);
-
-void power_5v_enable(task_id_t tid, int enable)
-{
-	mutex_lock(&pwr_5v_ctl_mtx);
-
-	if (enable) /* Set the bit indicating the request. */
-		pwr_5v_en_req |= 1 << tid;
-	else /* Clear the task's request bit. */
-		pwr_5v_en_req &= ~(1 << tid);
-
-	/*
-	 * If there are any outstanding requests for the rail to be enabled,
-	 * turn on the rail.  Otherwise, turn it off.
-	 */
-	board_power_5v_enable(pwr_5v_en_req);
-	mutex_unlock(&pwr_5v_ctl_mtx);
-}
-
-#define P5_SYSJUMP_TAG 0x5005  /* "P5" */
-static void restore_enable_5v_state(void)
-{
-	const uint32_t *state;
-	int size;
-
-	state = (const uint32_t *) system_get_jump_tag(P5_SYSJUMP_TAG, 0,
-						       &size);
-	if (state && size == sizeof(pwr_5v_en_req)) {
-		mutex_lock(&pwr_5v_ctl_mtx);
-		pwr_5v_en_req |= *state;
-		mutex_unlock(&pwr_5v_ctl_mtx);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, restore_enable_5v_state, HOOK_PRIO_FIRST);
-
-static void preserve_enable_5v_state(void)
-{
-	mutex_lock(&pwr_5v_ctl_mtx);
-	system_add_jump_tag(P5_SYSJUMP_TAG, 0, sizeof(pwr_5v_en_req),
-	    &pwr_5v_en_req);
-	mutex_unlock(&pwr_5v_ctl_mtx);
-}
-DECLARE_HOOK(HOOK_SYSJUMP, preserve_enable_5v_state, HOOK_PRIO_DEFAULT);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
diff --git a/power/ec_driven.c b/power/ec_driven.c
deleted file mode 100644
index 282941b941..0000000000
--- a/power/ec_driven.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Mock power module for Sensor HUB.
- *
- * This implements the following features:
- * when AP_IN_SUSPEND is low, in S0, otherwise S3.
- *
- */
-
-#include "chipset.h"  /* This module implements chipset functions too */
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "task.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-#define IN_SUSPEND POWER_SIGNAL_MASK(ECDRIVEN_SUSPEND_ASSERTED)
-
-enum power_state power_chipset_init(void)
-{
-	return POWER_S3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_S3:
-		if (!(power_get_signals() & IN_SUSPEND)) {
-			hook_notify(HOOK_CHIPSET_RESUME);
-			return POWER_S0;
-		}
-		return state;
-
-	case POWER_S0:
-		if (power_get_signals() & IN_SUSPEND) {
-			hook_notify(HOOK_CHIPSET_SUSPEND);
-			return POWER_S3;
-		}
-		return state;
-	default:
-		CPRINTS("Unexpected state: $d", state);
-	}
-
-	return state;
-}
diff --git a/power/host_sleep.c b/power/host_sleep.c
deleted file mode 100644
index bfa5cbd90a..0000000000
--- a/power/host_sleep.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "power.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-/* Track last reported sleep event */
-static enum host_sleep_event host_sleep_state;
-
-__overridable void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	/* Default weak implementation -- no action required. */
-}
-
-static enum ec_status
-host_command_host_sleep_event(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_host_sleep_event_v1 *p = args->params;
-	struct ec_response_host_sleep_event_v1 *r = args->response;
-	struct host_sleep_event_context ctx;
-	enum host_sleep_event state = p->sleep_event;
-
-	host_sleep_state = state;
-	ctx.sleep_transitions = 0;
-	switch (state) {
-	case HOST_SLEEP_EVENT_S0IX_SUSPEND:
-	case HOST_SLEEP_EVENT_S3_SUSPEND:
-	case HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND:
-		ctx.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT;
-
-		/* The original version contained only state. */
-		if (args->version >= 1)
-			ctx.sleep_timeout_ms =
-				p->suspend_params.sleep_timeout_ms;
-
-		break;
-
-	default:
-		break;
-	}
-
-	power_chipset_handle_host_sleep_event(host_sleep_state, &ctx);
-	switch (state) {
-	case HOST_SLEEP_EVENT_S0IX_RESUME:
-	case HOST_SLEEP_EVENT_S3_RESUME:
-		if (args->version >= 1) {
-			r->resume_response.sleep_transitions =
-				ctx.sleep_transitions;
-
-			args->response_size = sizeof(*r);
-		}
-
-		break;
-
-	default:
-		break;
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT,
-		     host_command_host_sleep_event,
-		     EC_VER_MASK(0) | EC_VER_MASK(1));
-
-enum host_sleep_event power_get_host_sleep_state(void)
-{
-	return host_sleep_state;
-}
-
-void power_set_host_sleep_state(enum host_sleep_event state)
-{
-	host_sleep_state = state;
-}
-
-/* Flag to notify listeners about suspend/resume events. */
-enum sleep_notify_type sleep_notify = SLEEP_NOTIFY_NONE;
-
-/*
- * Note: the following sleep_ functions do not get called in the S3 path on
- * Intel devices. On Intel devices, they are called in the S0ix path.
- */
-void sleep_set_notify(enum sleep_notify_type notify)
-{
-	sleep_notify = notify;
-}
-
-void sleep_notify_transition(int check_state, int hook_id)
-{
-	if (sleep_notify != check_state)
-		return;
-
-	hook_notify(hook_id);
-	sleep_set_notify(SLEEP_NOTIFY_NONE);
-}
-
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-
-static uint16_t sleep_signal_timeout;
-static uint16_t host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
-static uint32_t sleep_signal_transitions;
-static void (*sleep_timeout_callback)(void);
-
-static void sleep_transition_timeout(void);
-DECLARE_DEFERRED(sleep_transition_timeout);
-
-static void sleep_increment_transition(void)
-{
-	if ((sleep_signal_transitions & EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK) <
-	    EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK)
-		sleep_signal_transitions += 1;
-}
-
-void sleep_suspend_transition(void)
-{
-	sleep_increment_transition();
-	hook_call_deferred(&sleep_transition_timeout_data, -1);
-}
-
-void sleep_resume_transition(void)
-{
-	sleep_increment_transition();
-
-	/*
-	 * Start the timer again to ensure the AP doesn't get itself stuck in
-	 * a state where it's no longer in a sleep state (S0ix/S3), but from
-	 * the Linux perspective is still suspended. Perhaps a bug in the SoC-
-	 * internal periodic housekeeping code might result in a situation
-	 * like this.
-	 */
-	if (sleep_signal_timeout)
-		hook_call_deferred(&sleep_transition_timeout_data,
-				   (uint32_t)sleep_signal_timeout * 1000);
-}
-
-static void sleep_transition_timeout(void)
-{
-	/* Mark the timeout. */
-	sleep_signal_transitions |= EC_HOST_RESUME_SLEEP_TIMEOUT;
-	hook_call_deferred(&sleep_transition_timeout_data, -1);
-
-	/* Call the custom callback */
-	if (sleep_timeout_callback)
-		sleep_timeout_callback();
-}
-
-void sleep_start_suspend(struct host_sleep_event_context *ctx,
-			 void (*callback)(void))
-{
-	uint16_t timeout = ctx->sleep_timeout_ms;
-
-	sleep_timeout_callback = callback;
-	sleep_signal_transitions = 0;
-
-	/* Use zero internally to indicate no timeout. */
-	if (timeout == EC_HOST_SLEEP_TIMEOUT_DEFAULT) {
-		timeout = host_sleep_timeout_default;
-	}
-
-	/* Use 0xFFFF to disable the timeout */
-	if (timeout == EC_HOST_SLEEP_TIMEOUT_INFINITE) {
-		sleep_signal_timeout = 0;
-		return;
-	}
-
-	sleep_signal_timeout = timeout;
-	hook_call_deferred(&sleep_transition_timeout_data,
-			   (uint32_t)timeout * 1000);
-}
-
-void sleep_complete_resume(struct host_sleep_event_context *ctx)
-{
-	/*
-	 * Ensure we don't schedule another sleep_transition_timeout
-	 * if the the HOST_SLEEP_EVENT_S0IX_RESUME message arrives before
-	 * the CHIPSET task transitions to the POWER_S0ixS0 state.
-	 */
-	sleep_signal_timeout = 0;
-	hook_call_deferred(&sleep_transition_timeout_data, -1);
-	ctx->sleep_transitions = sleep_signal_transitions;
-}
-
-void sleep_reset_tracking(void)
-{
-	sleep_signal_transitions = 0;
-	sleep_signal_timeout = 0;
-	sleep_timeout_callback = NULL;
-}
-
-static int command_sleep_fail_timeout(int argc, char **argv)
-{
-	if (argc < 2) {
-		/* no arguments - just print the current timeout */
-	} else if (!strcasecmp(argv[1], "default")) {
-		host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
-	} else if (!strcasecmp(argv[1], "infinite")) {
-		host_sleep_timeout_default = EC_HOST_SLEEP_TIMEOUT_INFINITE;
-	} else {
-		char *e;
-		int val;
-
-		val = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		if (val <= 0 || val >= EC_HOST_SLEEP_TIMEOUT_INFINITE) {
-			ccprintf("Error: timeout range is 1..%d [msec]\n",
-				EC_HOST_SLEEP_TIMEOUT_INFINITE - 1);
-			return EC_ERROR_PARAM1;
-		}
-
-		host_sleep_timeout_default = val;
-	}
-
-	if (host_sleep_timeout_default == EC_HOST_SLEEP_TIMEOUT_INFINITE)
-		ccprintf("Sleep failure detection timeout is disabled\n");
-	else
-		ccprintf("Sleep failure detection timeout is %d [msec]\n",
-			host_sleep_timeout_default);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sleeptimeout, command_sleep_fail_timeout,
-		"[default | infinite | <msec>]",
-		"Display or set host sleep failure detection timeout.\n"
-		"Valid arguments are:\n"
-		" default\n"
-		" infinite - disables the timeout\n"
-		" <msec> - custom length in milliseconds\n"
-		" <none> - prints the current setting");
-
-
-#else /* !CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-/* No action */
-void sleep_suspend_transition(void)
-{
-}
-
-void sleep_resume_transition(void)
-{
-}
-
-void sleep_start_suspend(struct host_sleep_event_context *ctx,
-			 void (*callback)(void))
-{
-}
-
-void sleep_complete_resume(struct host_sleep_event_context *ctx)
-{
-}
-
-void sleep_reset_tracking(void)
-{
-}
-
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
diff --git a/power/icelake.c b/power/icelake.c
deleted file mode 100644
index c47f44c146..0000000000
--- a/power/icelake.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Icelake chipset power control module for Chrome EC */
-
-#include "board_config.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "task.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-#ifdef CONFIG_BRINGUP
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level_verbose(CC_CHIPSET, signal, value)
-#else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
-#endif
-
-/* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
-
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_DEASSERTED] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH |
-			POWER_SIGNAL_DISABLE_AT_BOOT,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_DEASSERTED] = {
-		.gpio = SLP_S3_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		.gpio = SLP_S4_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S4_DEASSERTED",
-	},
-	[X86_SLP_SUS_DEASSERTED] = {
-		.gpio = GPIO_SLP_SUS_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_SUS_DEASSERTED",
-	},
-	[X86_RSMRST_L_PGOOD] = {
-		.gpio = GPIO_PG_EC_RSMRST_ODL,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "RSMRST_L_PGOOD",
-	},
-	[X86_DSW_DPWROK] = {
-		.gpio = GPIO_PG_EC_DSW_PWROK,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "DSW_DPWROK",
-	},
-	[X86_ALL_SYS_PGOOD] = {
-		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "ALL_SYS_PWRGD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-__overridable int intel_x86_get_pg_ec_dsw_pwrok(void)
-{
-	return gpio_get_level(GPIO_PG_EC_DSW_PWROK);
-}
-
-__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
-{
-	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	int timeout_ms = 50;
-
-	CPRINTS("%s() %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Turn off RMSRST_L  to meet tPCH12 */
-	board_before_rsmrst(0);
-	GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
-	board_after_rsmrst(0);
-
-	/* Turn off DSW_PWROK to meet tPCH14 */
-	GPIO_SET_LEVEL(GPIO_PCH_DSW_PWROK, 0);
-
-	/* Turn off DSW load switch. */
-	GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 0);
-
-	/*
-	 * For JSL, we need to wait 60ms before turning off PP5000_U to allow
-	 * VCCIN_AUX time to discharge.
-	 */
-	if (IS_ENABLED(CONFIG_CHIPSET_JASPERLAKE))
-		msleep(60);
-
-	/* Turn off PP5000 rail */
-	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
-		power_5v_enable(task_get_current(), 0);
-	else
-		GPIO_SET_LEVEL(GPIO_EN_PP5000, 0);
-
-	/*
-	 * TODO(b/111810925): Replace this wait with
-	 * power_wait_signals_timeout()
-	 */
-	/* Now wait for DSW_PWROK and  RSMRST_ODL to go away. */
-	while (intel_x86_get_pg_ec_dsw_pwrok() &&
-	       gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
-		msleep(1);
-		timeout_ms--;
-	};
-
-	if (!timeout_ms)
-		CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low!  Assuming G3.");
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
-	 * it means that there is an unexpected power loss (global reset
-	 * event). In this case, check if shutdown was being forced by pressing
-	 * power button. If yes, release power button.
-	 */
-	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-static void enable_pp5000_rail(void)
-{
-	if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
-		power_5v_enable(task_get_current(), 1);
-	else
-		GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
-
-}
-
-static void dsw_pwrok_pass_thru(void)
-{
-	int dswpwrok_in = intel_x86_get_pg_ec_dsw_pwrok();
-
-	/* Pass-through DSW_PWROK to ICL. */
-	if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) {
-		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
-			&& dswpwrok_in) {
-			/*
-			 * Once DSW_PWROK is high, reconfigure SLP_S3_L back to
-			 * an input after a short delay.
-			 */
-			msleep(1);
-			CPRINTS("Release SLP_S3_L");
-			gpio_reset(SLP_S3_SIGNAL_L);
-			power_signal_enable_interrupt(SLP_S3_SIGNAL_L);
-		}
-
-		CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
-		/*
-		 * A minimum 10 msec delay is required between PP3300_A being
-		 * stable and the DSW_PWROK signal being passed to the PCH.
-		 */
-		msleep(10);
-		GPIO_SET_LEVEL(GPIO_PCH_DSW_PWROK, dswpwrok_in);
-	}
-}
-
-/*
- * Set the PWROK signal state
- *
- * &param level		0 deasserts the signal, other values assert the signal
- */
-static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
-	int level)
-{
-	GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
-}
-
-/*
- * Pass through the state of the ALL_SYS_PWRGD input to all the PWROK outputs
- * defined by the board.
- */
-static void all_sys_pwrgd_pass_thru(void)
-{
-	int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd();
-	const struct intel_x86_pwrok_signal *pwrok_signal;
-	int signal_count;
-	int i;
-
-	if (all_sys_pwrgd_in) {
-		pwrok_signal = pwrok_signal_assert_list;
-		signal_count = pwrok_signal_assert_count;
-	} else {
-		pwrok_signal = pwrok_signal_deassert_list;
-		signal_count = pwrok_signal_deassert_count;
-	}
-
-	/*
-	 * Loop through all PWROK signals defined by the board and set
-	 * to match the current ALL_SYS_PWRGD input.
-	 */
-	for (i = 0; i < signal_count; i++, pwrok_signal++) {
-		if (pwrok_signal->delay_ms > 0)
-			msleep(pwrok_signal->delay_ms);
-
-		pwrok_signal_set(pwrok_signal, all_sys_pwrgd_in);
-	}
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-#ifdef CONFIG_CHIPSET_JASPERLAKE
-	int timeout_ms = 10;
-#endif /* CONFIG_CHIPSET_JASPERLAKE */
-
-	dsw_pwrok_pass_thru();
-
-	all_sys_pwrgd_pass_thru();
-
-	common_intel_x86_handle_rsmrst(state);
-
-	switch (state) {
-
-	case POWER_G3S5:
-		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
-			/*
-			 * Prevent glitches on the SLP_S3_L and PCH_PWROK
-			 * signals while when the PP3300_A rail is turned on.
-			 * Drive SLP_S3_L from the EC until DSW_PWROK is high.
-			 */
-			CPRINTS("Drive SLP_S3_L low during PP3300_A rampup");
-			power_signal_disable_interrupt(SLP_S3_SIGNAL_L);
-			gpio_set_flags(SLP_S3_SIGNAL_L, GPIO_ODR_LOW);
-		}
-
-		/* Default behavior - turn on PP5000 rail first */
-		if (!IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
-			enable_pp5000_rail();
-
-		/*
-		 * TODO(b/111121615): Should modify this to wait until the
-		 * common power state machine indicates that it's ok to try an
-		 * boot the AP prior to turning on the 3300_A rail. This could
-		 * be done using chipset_pre_init_callback()
-		 */
-		/* Turn on the PP3300_DSW rail. */
-		GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 1);
-		if (power_wait_signals(IN_PGOOD_ALL_CORE))
-			break;
-
-		/* Pass thru DSWPWROK again since we changed it. */
-		dsw_pwrok_pass_thru();
-
-		/* Turn on PP5000 after PP3300 and DSW PWROK when enabled */
-		if (IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
-			enable_pp5000_rail();
-
-		/*
-		 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
-		 * signal doesn't go high within 250 msec then go back to G3.
-		 */
-		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
-			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
-			return POWER_S5G3;
-		}
-		break;
-
-	case POWER_S5:
-		if (forcing_shutdown) {
-			power_button_pch_release();
-			forcing_shutdown = 0;
-		}
-		/* If SLP_SUS_L is asserted, we're no longer in S5. */
-		if (!power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
-			return POWER_S5G3;
-		break;
-
-#ifdef CONFIG_CHIPSET_JASPERLAKE
-	case POWER_S3S0:
-		GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1);
-		/* Now wait for ALL_SYS_PWRGD. */
-		while (!intel_x86_get_pg_ec_all_sys_pwrgd() &&
-			(timeout_ms > 0)) {
-			msleep(1);
-			timeout_ms--;
-		};
-		if (!timeout_ms)
-			CPRINTS("ALL_SYS_PWRGD not received.");
-		break;
-
-	case POWER_S0S3:
-		GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 0);
-		break;
-#endif /* CONFIG_CHIPSET_JASPERLAKE */
-
-	default:
-		break;
-	}
-
-	return common_intel_x86_power_handle_state(state);
-}
diff --git a/power/intel_x86.c b/power/intel_x86.c
deleted file mode 100644
index c4aae9db81..0000000000
--- a/power/intel_x86.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel X86 chipset power control module for Chrome EC */
-
-#include "board_config.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "power.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-#include "vboot.h"
-#include "wireless.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
-
-enum sys_sleep_state {
-	SYS_SLEEP_S3,
-	SYS_SLEEP_S4,
-#ifdef CONFIG_POWER_S0IX
-	SYS_SLEEP_S0IX,
-#endif
-};
-
-static const int sleep_sig[] = {
-	[SYS_SLEEP_S3] = SLP_S3_SIGNAL_L,
-	[SYS_SLEEP_S4] = SLP_S4_SIGNAL_L,
-#ifdef CONFIG_POWER_S0IX
-	[SYS_SLEEP_S0IX] = GPIO_PCH_SLP_S0_L,
-#endif
-};
-
-static int power_s5_up;       /* Chipset is sequencing up or down */
-
-#ifdef CONFIG_CHARGER
-/* Flag to indicate if power up was inhibited due to low battery SOC level. */
-static int power_up_inhibited;
-
-/*
- * Check if AP power up should be inhibited.
- * 0 = Ok to boot up AP
- * 1 = AP power up is inhibited.
- */
-static int is_power_up_inhibited(void)
-{
-	/* Defaulting to power button not pressed. */
-	const int power_button_pressed = 0;
-
-	return charge_prevent_power_on(power_button_pressed) ||
-		charge_want_shutdown();
-}
-
-static void power_up_inhibited_cb(void)
-{
-	if (!power_up_inhibited)
-		return;
-
-	if (is_power_up_inhibited()) {
-		CPRINTS("power-up still inhibited");
-		return;
-	}
-
-	CPRINTS("Battery SOC ok to boot AP!");
-	power_up_inhibited = 0;
-
-	chipset_exit_hard_off();
-}
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, power_up_inhibited_cb, HOOK_PRIO_DEFAULT);
-#endif
-
-/* Get system sleep state through GPIOs or VWs */
-static inline int chipset_get_sleep_signal(enum sys_sleep_state state)
-{
-	return power_signal_get_level(sleep_sig[state]);
-}
-
-#ifdef CONFIG_BOARD_HAS_RTC_RESET
-static void intel_x86_rtc_reset(void)
-{
-	CPRINTS("Asserting RTCRST# to PCH");
-	gpio_set_level(GPIO_PCH_RTCRST, 1);
-	udelay(100);
-	gpio_set_level(GPIO_PCH_RTCRST, 0);
-}
-
-static enum power_state power_wait_s5_rtc_reset(void)
-{
-	static int s5_exit_tries;
-
-	/* Wait for S5 exit and then attempt RTC reset */
-	while ((power_get_signals() & IN_PCH_SLP_S4_DEASSERTED) == 0) {
-		/* Handle RSMRST passthru event while waiting */
-		common_intel_x86_handle_rsmrst(POWER_S5);
-		if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) {
-			CPRINTS("timeout waiting for S5 exit");
-			chipset_force_g3();
-
-			/* Assert RTCRST# and retry 5 times */
-			intel_x86_rtc_reset();
-
-			if (++s5_exit_tries > 4) {
-				s5_exit_tries = 0;
-				return POWER_G3; /* Stay off */
-			}
-
-			udelay(10 * MSEC);
-			return POWER_G3S5; /* Power up again */
-		}
-	}
-
-	s5_exit_tries = 0;
-	return POWER_S5S3; /* Power up to next state */
-}
-#endif
-
-#ifdef CONFIG_POWER_S0IX
-/*
- * Backup copies of SCI and SMI mask to preserve across S0ix suspend/resume
- * cycle. If the host uses S0ix, BIOS is not involved during suspend and resume
- * operations and hence SCI/SMI masks are programmed only once during boot-up.
- *
- * These backup variables are set whenever host expresses its interest to
- * enter S0ix and then lpc_host_event_mask for SCI and SMI are cleared. When
- * host resumes from S0ix, masks from backup variables are copied over to
- * lpc_host_event_mask for SCI and SMI.
- */
-static host_event_t backup_sci_mask;
-static host_event_t backup_smi_mask;
-
-/*
- * Clear host event masks for SMI and SCI when host is entering S0ix. This is
- * done to prevent any SCI/SMI interrupts when the host is in suspend. Since
- * BIOS is not involved in the suspend path, EC needs to take care of clearing
- * these masks.
- */
-static void lpc_s0ix_suspend_clear_masks(void)
-{
-	backup_sci_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SCI);
-	backup_smi_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
-
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0);
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0);
-}
-
-/*
- * Restore host event masks for SMI and SCI when host exits S0ix. This is done
- * because BIOS is not involved in the resume path and so EC needs to restore
- * the masks from backup variables.
- */
-static void lpc_s0ix_resume_restore_masks(void)
-{
-	/*
-	 * No need to restore SCI/SMI masks if both backup_sci_mask and
-	 * backup_smi_mask are zero. This indicates that there was a failure to
-	 * enter S0ix(SLP_S0# assertion) and hence SCI/SMI masks were never
-	 * backed up.
-	 */
-	if (!backup_sci_mask && !backup_smi_mask)
-		return;
-
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, backup_sci_mask);
-	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, backup_smi_mask);
-
-	backup_sci_mask = backup_smi_mask = 0;
-}
-
-static void lpc_s0ix_hang_detected(void)
-{
-	/*
-	 * Wake up the AP so they don't just chill in a non-suspended state and
-	 * burn power. Overload a vaguely related event bit since event bits are
-	 * at a premium. If the system never entered S0ix, then manually set the
-	 * wake mask to pretend it did, so that the hang detect event wakes the
-	 * system.
-	 */
-	if (power_get_state() == POWER_S0) {
-		host_event_t sleep_wake_mask;
-
-		get_lazy_wake_mask(POWER_S0ix, &sleep_wake_mask);
-		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
-	}
-
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-static void handle_chipset_suspend(void)
-{
-	/* Clear masks before any hooks are run for suspend. */
-	lpc_s0ix_suspend_clear_masks();
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, handle_chipset_suspend, HOOK_PRIO_FIRST);
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_STANDBY)) {
-		CPRINTS("chipset reset: exit s0ix");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-
-void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-#endif /* CONFIG_POWER_S0IX */
-
-void chipset_throttle_cpu(int throttle)
-{
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-	throttle = !throttle;
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	CPRINTS("%s: power_signal=0x%x", __func__, power_get_signals());
-
-	if (!system_jumped_to_this_image())
-		return POWER_G3;
-	/*
-	 * We are here as RW. We need to handle the following cases:
-	 *
-	 * 1. Late sysjump by software sync. AP is in S0.
-	 * 2. Shutting down in recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence down.
-	 * 3. Rebooting from recovery mode then sysjump by EFS2. AP is in S5
-	 *    and expected to sequence up.
-	 * 4. RO jumps to RW from main() by EFS2. (a.k.a. power on reset, cold
-	 *    reset). AP is in G3.
-	 */
-	if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-		/* case #1. Disable idle task deep sleep when in S0. */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		CPRINTS("already in S0");
-		return POWER_S0;
-	}
-	if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL)
-			== CHIPSET_G3S5_POWERUP_SIGNAL) {
-		/* case #2 & #3 */
-		CPRINTS("already in S5");
-		return POWER_S5;
-	}
-	/* case #4 */
-	chipset_force_g3();
-	return POWER_G3;
-}
-
-enum power_state common_intel_x86_power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-#ifdef CONFIG_BOARD_HAS_RTC_RESET
-		/* Wait for S5 exit and attempt RTC reset if supported */
-		if (power_s5_up)
-			return power_wait_s5_rtc_reset();
-#endif
-
-		if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S0S3;
-		} else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * SLP_S0 may assert in system idle scenario without a kernel
-		 * freeze call. This may cause interrupt storm since there is
-		 * no freeze/unfreeze of threads/process in the idle scenario.
-		 * Ignore the SLP_S0 assertions in idle scenario by checking
-		 * the host sleep state.
-		 */
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S0IX_SUSPEND &&
-				chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) {
-			return POWER_S0S0ix;
-		} else {
-			sleep_notify_transition(SLEEP_NOTIFY_RESUME,
-						HOOK_CHIPSET_RESUME);
-#endif
-		}
-
-		break;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0ix:
-		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
-		if ((chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 1) &&
-		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
-			return POWER_S0ixS0;
-		} else if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			return POWER_S0;
-		}
-
-		break;
-#endif
-
-	case POWER_G3S5:
-		if (intel_x86_wait_power_up_ok() != EC_SUCCESS) {
-			chipset_force_shutdown(
-				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
-			return POWER_G3;
-		}
-#ifdef CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-		/*
-		 * Callback to do pre-initialization within the context of
-		 * chipset task.
-		 */
-		chipset_pre_init_callback();
-#endif
-
-		if (power_wait_signals(CHIPSET_G3S5_POWERUP_SIGNAL)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_G3;
-		}
-
-		power_s5_up = 1;
-		return POWER_S5;
-
-	case POWER_S5S3:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-#ifdef CONFIG_POWER_S0IX
-		/*
-		 * Clearing the S0ix flag on the path to S0
-		 * to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state();
-#endif
-		return POWER_S3;
-
-	case POWER_S3S0:
-		if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		}
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		lpc_s3_resume_clear_masks();
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-		gpio_set_level(GPIO_CPU_PROCHOT, 1);
-#else
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-#ifdef CONFIG_POWER_S0IX
-		/* re-init S0ix flag */
-		power_reset_host_sleep_state();
-#endif
-		return POWER_S3;
-
-#ifdef CONFIG_POWER_S0IX
-	case POWER_S0S0ix:
-		/*
-		 * Call hooks only if we haven't notified listeners of S0ix
-		 * suspend.
-		 */
-		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
-					HOOK_CHIPSET_SUSPEND);
-		sleep_suspend_transition();
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S0ix.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S0ix;
-
-	case POWER_S0ixS0:
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		sleep_resume_transition();
-		return POWER_S0;
-#endif
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Always enter into S5 state. The S5 state is required to
-		 * correctly handle global resets which have a bit of delay
-		 * while the SLP_Sx_L signals are asserted then deasserted.
-		 */
-		power_s5_up = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return chipset_force_g3();
-
-	default:
-		break;
-	}
-
-	return state;
-}
-
-void intel_x86_rsmrst_signal_interrupt(enum gpio_signal signal)
-{
-	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
-	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
-
-	/*
-	 * This function is called when rsmrst changes state. If rsmrst
-	 * has been asserted (high -> low) then pass this new state to PCH.
-	 */
-	if (!rsmrst_in && (rsmrst_in != rsmrst_out))
-		gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
-
-	/*
-	 * Call the main power signal interrupt handler to wake up the chipset
-	 * task which handles low->high rsmrst pass through.
-	 */
-	power_signal_interrupt(signal);
-}
-
-__overridable void board_before_rsmrst(int rsmrst)
-{
-}
-
-__overridable void board_after_rsmrst(int rsmrst)
-{
-}
-
-void common_intel_x86_handle_rsmrst(enum power_state state)
-{
-	/*
-	 * Pass through RSMRST asynchronously, as PCH may not react
-	 * immediately to power changes.
-	 */
-	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
-	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
-
-	/* Nothing to do. */
-	if (rsmrst_in == rsmrst_out)
-		return;
-
-	board_before_rsmrst(rsmrst_in);
-
-#ifdef CONFIG_CHIPSET_APL_GLK
-	/* Only passthrough RSMRST_L de-assertion on power up */
-	if (rsmrst_in && !power_s5_up)
-		return;
-#elif defined(CONFIG_CHIPSET_X86_RSMRST_DELAY)
-	/*
-	 * Wait at least 10ms between power signals going high
-	 * and deasserting RSMRST to PCH.
-	 */
-	if (rsmrst_in)
-		msleep(10);
-#endif
-
-	gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
-
-	CPRINTS("Pass through GPIO_RSMRST_L_PGOOD: %d", rsmrst_in);
-
-	board_after_rsmrst(rsmrst_in);
-}
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-
-__overridable void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
-{
-	/* Default weak implementation -- no action required. */
-}
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	power_board_handle_host_sleep_event(state);
-
-#ifdef CONFIG_POWER_S0IX
-	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * s0ix/s3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-
-		sleep_start_suspend(ctx, lpc_s0ix_hang_detected);
-		power_signal_enable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
-	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		lpc_s0ix_resume_restore_masks();
-		power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
-		sleep_complete_resume(ctx);
-		/*
-		 * If the sleep signal timed out and never transitioned, then
-		 * the wake mask was modified to its suspend state (S0ix), so
-		 * that the event wakes the system. Explicitly restore the wake
-		 * mask to its S0 state now.
-		 */
-		power_update_wake_mask();
-	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
-		power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
-	}
-#endif
-
-}
-
-#endif
-
-__overridable void intel_x86_sys_reset_delay(void)
-{
-	/*
-	 * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
-	 * to be safe.
-	 */
-	udelay(32 * MSEC);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	/*
-	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
-	 * perform a chipset reset. RCIN# which was used earlier to trigger
-	 * a warm reset is known to not work in certain cases where the CPU
-	 * is in a bad state (crbug.com/721853).
-	 *
-	 * The EC cannot control warm vs cold reset of the chipset using
-	 * SYS_RESET_L; it's more of a request.
-	 */
-	CPRINTS("%s: %d", __func__, reason);
-
-	/*
-	 * Toggling SYS_RESET_L will not have any impact when it's already
-	 * low (i,e. Chipset is in reset state).
-	 */
-	if (gpio_get_level(GPIO_SYS_RESET_L) == 0) {
-		CPRINTS("Chipset is in reset state");
-		return;
-	}
-
-	report_ap_reset(reason);
-
-	gpio_set_level(GPIO_SYS_RESET_L, 0);
-	intel_x86_sys_reset_delay();
-	gpio_set_level(GPIO_SYS_RESET_L, 1);
-}
-
-enum ec_error_list intel_x86_wait_power_up_ok(void)
-{
-#ifdef CONFIG_CHARGER
-	int tries = 0;
-
-	/*
-	 * Allow charger to be initialized for up to defined tries,
-	 * in case we're trying to boot the AP with no battery.
-	 */
-	while ((tries < CHARGER_INITIALIZED_TRIES) &&
-	       is_power_up_inhibited()) {
-		msleep(CHARGER_INITIALIZED_DELAY_MS);
-		tries++;
-	}
-
-	/*
-	 * Return to G3 if battery level is too low. Set
-	 * power_up_inhibited in order to check the eligibility to boot
-	 * AP up after battery SOC changes.
-	 */
-	if (tries == CHARGER_INITIALIZED_TRIES) {
-		CPRINTS("power-up inhibited");
-		power_up_inhibited = 1;
-		return EC_ERROR_TIMEOUT;
-	}
-
-	power_up_inhibited = 0;
-#endif
-
-#if defined(CONFIG_VBOOT_EFS) || defined(CONFIG_VBOOT_EFS2)
-	/*
-	 * We have to test power readiness here (instead of S5->S3)
-	 * because when entering S5, EC enables EC_ROP_SLP_SUS pin
-	 * which causes (short-powered) system to brown out.
-	 */
-	while (!system_can_boot_ap())
-		msleep(200);
-#endif
-
-	return EC_SUCCESS;
-}
diff --git a/power/mt817x.c b/power/mt817x.c
deleted file mode 100644
index e7e23605f2..0000000000
--- a/power/mt817x.c
+++ /dev/null
@@ -1,818 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * MT817x SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- *  When powered off:
- *  - Press pwron turns on the AP
- *  - Hold pwron turns on the AP, and then 8s later turns it off and leaves
- *    it off until pwron is released and pressed again
- *
- *  When powered on:
- *  - The PMIC PWRON signal is released <= 1 second after the power button is
- *    released
- *  - Holding pwron for 8s powers off the AP
- *  - Pressing and releasing pwron within that 8s is ignored
- *  - If POWER_GOOD is dropped by the AP, then we power the AP off
- *  - If SUSPEND_L goes low, enter suspend mode.
- *
- */
-
-#include "battery.h"
-#include "chipset.h" /* ./common/chipset.c implements chipset functions too */
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "power_led.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-#define INT_BOTH_PULL_UP	(GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
-
-/* masks for power signals */
-#define IN_POWER_GOOD POWER_SIGNAL_MASK(MTK_POWER_GOOD)
-#define IN_SUSPEND POWER_SIGNAL_MASK(MTK_SUSPEND_ASSERTED)
-
-/* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8000 * MSEC)	/* 8 seconds */
-
-/*
- * The power signal from SoC should be kept at least 50ms.
- */
-#define POWER_DEBOUNCE_TIME     (50 * MSEC)
-
-/*
- * The suspend signal from SoC should be kept at least 50ms.
- */
-#define SUSPEND_DEBOUNCE_TIME   (50 * MSEC)
-
-/*
- * The time to bootup the PMIC from power-off to power-on.
- */
-#define PMIC_PWRON_PRESS_TIME   (5000 * MSEC)
-
-/*
- * The minimum time to assert the PMIC THERM pin is 32us. However,
- * it needs to be extended to about 50ms to let the 5V rail
- * dissipate fully.
- */
-#define PMIC_THERM_HOLD_TIME  (50 * MSEC)
-
-/*
- * If the power key is pressed to turn on, then held for this long, we
- * power off.
- *
- * Normal case: User releases power button and chipset_task() goes
- *    into the inner loop, waiting for next event to occur (power button
- *    press or POWER_GOOD == 0).
- */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8000 * MSEC)	/* 8 seconds */
-
-/*
- * The hold time for pulling down the PMIC_WARM_RESET_H pin so that
- * the AP can entery the recovery mode (flash SPI flash from USB).
- */
-#define PMIC_WARM_RESET_H_HOLD_TIME (4 * MSEC)
-
-/*
- * The hold time for pulling down the SYSTEM_POWER_H pin.
- */
-#define PMIC_COLD_RESET_L_HOLD_TIME \
-	(SUSPEND_DEBOUNCE_TIME + POWER_DEBOUNCE_TIME + (20 * MSEC))
-
-/*
- * The first time the PMIC sees power (AC or battery) it needs 200ms (+/-12%
- * oscillator tolerance) for the RTC startup. In addition there is a startup
- * time of approx. 0.5msec until V2_5 regulator starts up. */
-#define PMIC_RTC_STARTUP (225 * MSEC)
-
-/* Wait for 5V power source stable */
-#define PMIC_WAIT_FOR_5V_POWER_GOOD (1 * MSEC)
-
-/*
- * If POWER_GOOD is lost, wait for PMIC to turn off its power completely
- * before we turn off VBAT by set_system_power(0)
- */
-#define PMIC_POWER_OFF_DELAY (50 * MSEC)
-
-/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
-/* 1 if the power button was pressed last time we checked */
-static char power_button_was_pressed;
-
-/* 1 if lid-open event has been detected */
-static char lid_opened;
-
-/* time where we will power off, if power button still held down */
-static timestamp_t power_off_deadline;
-
-/* force AP power on (used for recovery keypress) */
-static int auto_power_on;
-
-enum power_request_t {
-	POWER_REQ_NONE,
-	POWER_REQ_OFF,
-	POWER_REQ_ON,
-
-	POWER_REQ_COUNT,
-};
-
-static enum power_request_t power_request;
-
-/**
- * Return values for check_for_power_off_event().
- */
-enum power_off_event_t {
-	POWER_OFF_CANCEL,
-	POWER_OFF_BY_POWER_BUTTON_PRESSED,
-	POWER_OFF_BY_LONG_PRESS,
-	POWER_OFF_BY_POWER_GOOD_LOST,
-	POWER_OFF_BY_POWER_REQ,
-
-	POWER_OFF_EVENT_COUNT,
-};
-
-/**
- * Return values for check_for_power_on_event().
- */
-enum power_on_event_t {
-	POWER_ON_CANCEL,
-	POWER_ON_BY_IN_POWER_GOOD,
-	POWER_ON_BY_AUTO_POWER_ON,
-	POWER_ON_BY_LID_OPEN,
-	POWER_ON_BY_POWER_BUTTON_PRESSED,
-	POWER_ON_BY_POWER_REQ_NONE,
-
-	POWER_ON_EVENT_COUNT,
-};
-
-/**
- * Parameters of mtk_backlight_override().
- */
-enum blacklight_override_t {
-	MTK_BACKLIGHT_FORCE_OFF,
-	MTK_BACKLIGHT_CONTROL_BY_SOC,
-
-	MTK_BACKLIGHT_OVERRIDE_COUNT,
-};
-
-/* Forward declaration */
-static void chipset_turn_off_power_rails(void);
-
-/**
- * Check the suspend signal is on after SUSPEND_DEBOUNCE_TIME to avoid transient
- * state.
- *
- * @return non-zero if SUSPEND is asserted.
- */
-static int is_suspend_asserted(void)
-{
-#ifdef BOARD_OAK
-	if ((power_get_signals() & IN_SUSPEND) &&
-	    (system_get_board_version() < 4))
-		usleep(SUSPEND_DEBOUNCE_TIME);
-#endif
-
-	return power_get_signals() & IN_SUSPEND;
-}
-
-/**
- * Check the suspend signal is off after SUSPEND_DEBOUNCE_TIME to avoid
- * transient state.
- *
- * @return non-zero if SUSPEND is deasserted.
- */
-static int is_suspend_deasserted(void)
-{
-#ifdef BOARD_OAK
-	if (!(power_get_signals() & IN_SUSPEND) &&
-	    (system_get_board_version() < 4))
-		usleep(SUSPEND_DEBOUNCE_TIME);
-#endif
-
-	return !(power_get_signals() & IN_SUSPEND);
-}
-
-/**
- * Check power good signal is on after POWER_DEBOUNCE_TIME to avoid transient
- * state.
- *
- * @return non-zero if POWER_GOOD is asserted.
- */
-static int is_power_good_asserted(void)
-{
-	if (!gpio_get_level(GPIO_SYSTEM_POWER_H))
-		return 0;
-#ifdef BOARD_OAK
-	else if ((power_get_signals() & IN_POWER_GOOD) &&
-		 (system_get_board_version() < 4))
-		usleep(POWER_DEBOUNCE_TIME);
-#endif
-
-	return power_get_signals() & IN_POWER_GOOD;
-}
-
-/**
- * Check power good signal is off after POWER_DEBOUNCE_TIME to avoid transient
- * state.
- *
- * @return non-zero if POWER_GOOD is deasserted.
- */
-static int is_power_good_deasserted(void)
-{
-#ifdef BOARD_OAK
-	/*
-	 * Warm reset key from servo board lets the POWER_GOOD signal
-	 * deasserted temporarily (about 1~2 seconds) on rev4.
-	 * In order to detect this case, check the AP_RESET_L status,
-	 * ignore the transient state if reset key is pressing.
-	 */
-	if (system_get_board_version() >= 4) {
-		if (0 == gpio_get_level(GPIO_AP_RESET_L))
-			return 0;
-	} else {
-		if (!(power_get_signals() & IN_POWER_GOOD))
-			usleep(POWER_DEBOUNCE_TIME);
-	}
-#endif
-	if (0 == gpio_get_level(GPIO_AP_RESET_L))
-		return 0;
-
-	return !(power_get_signals() & IN_POWER_GOOD);
-}
-
-/**
- * Set the system power signal.
- *
- * @param asserted	off (=0) or on (=1)
- */
-static void set_system_power(int asserted)
-{
-	CPRINTS("set_system_power(%d)", asserted);
-	gpio_set_level(GPIO_SYSTEM_POWER_H, asserted);
-}
-
-/**
- * Set the PMIC PWRON signal.
- *
- * Note that asserting requires holding for PMIC_PWRON_PRESS_TIME.
- *
- * @param asserted	Assert (=1) or deassert (=0) the signal.  This is the
- *			logical level of the pin, not the physical level.
- */
-static void set_pmic_pwron(int asserted)
-{
-	timestamp_t poll_deadline;
-	/* Signal is active-high */
-	CPRINTS("set_pmic_pwron(%d)", asserted);
-	/* Oak rev1 power-on sequence:
-	 *   raise GPIO_SYSTEM_POWER_H
-	 *   wait for 5V power good, timeout 1 second
-	 */
-	if (asserted) {
-		set_system_power(asserted);
-		poll_deadline = get_time();
-		poll_deadline.val += SECOND;
-		while (asserted && !gpio_get_level(GPIO_5V_POWER_GOOD) &&
-		       get_time().val < poll_deadline.val)
-			usleep(PMIC_WAIT_FOR_5V_POWER_GOOD);
-		if (!gpio_get_level(GPIO_5V_POWER_GOOD))
-			CPRINTS("5V power not ready");
-	}
-
-	gpio_set_level(GPIO_PMIC_PWRON_H, asserted);
-}
-
-/**
- * Set the WARM RESET signal.
- *
- * @param asserted	off (=0) or on (=1)
- */
-static void set_warm_reset(int asserted)
-{
-	board_set_ap_reset(asserted);
-}
-
-/**
- * Check for some event triggering the shutdown.
- *
- * It can be either a long power button press or a shutdown triggered from the
- * AP and detected by reading POWER_GOOD.
- *
- * @return non-zero if a shutdown should happen, 0 if not
- */
-static int check_for_power_off_event(void)
-{
-	timestamp_t now;
-	int pressed = 0;
-
-	/*
-	 * Check for power button press.
-	 */
-	if (power_button_is_pressed()) {
-		pressed = POWER_OFF_BY_POWER_BUTTON_PRESSED;
-	} else if (power_request == POWER_REQ_OFF) {
-		power_request = POWER_REQ_NONE;
-		/* return non-zero for shudown down */
-		return POWER_OFF_BY_POWER_REQ;
-	}
-
-	now = get_time();
-	if (pressed) {
-		if (!power_button_was_pressed) {
-			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
-			CPRINTS("power waiting for long press %u",
-				power_off_deadline.le.lo);
-			/* Ensure we will wake up to check the power key */
-			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
-		} else if (timestamp_expired(power_off_deadline, &now)) {
-			power_off_deadline.val = 0;
-			CPRINTS("power off after long press now=%u, %u",
-				now.le.lo, power_off_deadline.le.lo);
-			return POWER_OFF_BY_LONG_PRESS;
-		}
-	} else if (power_button_was_pressed) {
-		CPRINTS("power off cancel");
-		timer_cancel(TASK_ID_CHIPSET);
-	}
-
-	power_button_was_pressed = pressed;
-
-	/* POWER_GOOD released by AP : shutdown immediate */
-	if (is_power_good_deasserted()) {
-		/*
-		 * Cancel long press timer if power is lost and the power button
-		 * still press, otherwise EC will crash.
-		 */
-		if (power_button_was_pressed)
-			timer_cancel(TASK_ID_CHIPSET);
-
-		CPRINTS("POWER_GOOD is lost");
-		return POWER_OFF_BY_POWER_GOOD_LOST;
-	}
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Set the LCD backlight enable pin and override the signal from SoC.
- *
- * @param asserted	MTK_BACKLIGHT_FORCE_OFF, force off the panel backlight
- *			MTK_BACKLIGHT_CONTROL_BY_SOC, leave the control to SOC
- */
-static void mtk_backlight_override(enum blacklight_override_t asserted)
-{
-	/* Signal is active-low */
-	gpio_set_level(GPIO_EC_BL_OVERRIDE, !asserted);
-}
-
-static void mtk_lid_event(void)
-{
-	enum blacklight_override_t bl_override;
-
-	/* Override the panel backlight enable signal from SoC,
-	 * force the backlight off on lid close.
-	 */
-	bl_override = lid_is_open() ?
-		MTK_BACKLIGHT_CONTROL_BY_SOC :
-		MTK_BACKLIGHT_FORCE_OFF;
-	mtk_backlight_override(bl_override);
-
-	/* Power task only cares about lid-open events */
-	if (!lid_is_open())
-		return;
-
-	lid_opened = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, mtk_lid_event, HOOK_PRIO_DEFAULT);
-
-enum power_state power_chipset_init(void)
-{
-	int init_power_state;
-	uint32_t reset_flags = system_get_reset_flags();
-
-	/*
-	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
-	 * the AP could stay in strange state.
-	 */
-	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("not sysjump; forcing AP shutdown");
-		chipset_turn_off_power_rails();
-
-		/*
-		 * The warm reset triggers AP into the recovery mode (
-		 * flash SPI from USB).
-		 */
-		chipset_reset(CHIPSET_RESET_UNKNOWN);
-
-		init_power_state = POWER_G3;
-	} else {
-		/* In the SYSJUMP case, we check if the AP is on */
-		if (is_power_good_asserted()) {
-			CPRINTS("SOC ON");
-			/*
-			 * Check and release PMIC power button signal,
-			 * if it's deferred callback function is not triggered
-			 * in RO before SYSJUMP.
-			 */
-			if (gpio_get_level(GPIO_PMIC_PWRON_H))
-				set_pmic_pwron(0);
-
-			init_power_state = POWER_S0;
-			if (is_suspend_asserted())
-				enable_sleep(SLEEP_MASK_AP_RUN);
-			else
-				disable_sleep(SLEEP_MASK_AP_RUN);
-		} else {
-			CPRINTS("SOC OFF");
-			init_power_state = POWER_G3;
-			enable_sleep(SLEEP_MASK_AP_RUN);
-		}
-	}
-
-	/* Leave power off only if requested by reset flags */
-	if (!(reset_flags & EC_RESET_FLAG_AP_OFF) &&
-	    !(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("reset_flag 0x%x", reset_flags);
-		auto_power_on = 1;
-	}
-
-	/*
-	 * Some batteries use clock stretching feature, which requires
-	 * more time to be stable. See http://crosbug.com/p/28289
-	 */
-	battery_wait_for_stable();
-
-	return init_power_state;
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-static void chipset_turn_off_power_rails(void)
-{
-	/* Release the power on pin, if it was asserted */
-	set_pmic_pwron(0);
-
-	/* system power off */
-	usleep(PMIC_POWER_OFF_DELAY);
-	set_system_power(0);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	chipset_turn_off_power_rails();
-
-	/* clean-up internal variable */
-	power_request = POWER_REQ_NONE;
-}
-
-/*****************************************************************************/
-
-/**
- * Power off the AP
- */
-static void power_off(void)
-{
-	/* Check the power off status */
-	if (!gpio_get_level(GPIO_SYSTEM_POWER_H))
-		return;
-
-	/* Call hooks before we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	/* switch off all rails */
-	chipset_turn_off_power_rails();
-
-	/* Change SUSPEND_L pin to high-Z to reduce power draw. */
-	gpio_set_flags(power_signal_list[MTK_SUSPEND_ASSERTED].gpio,
-		       GPIO_INPUT);
-
-	/* Change EC_INT to low */
-	gpio_set_level(GPIO_EC_INT_L, 0);
-
-	lid_opened = 0;
-	enable_sleep(SLEEP_MASK_AP_RUN);
-#ifdef HAS_TASK_POWERLED
-	powerled_set_state(POWERLED_STATE_OFF);
-#endif
-	CPRINTS("power shutdown complete");
-
-	/* Call hooks after we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-}
-
-/**
- * Check if there has been a power-on event
- *
- * This checks all power-on event signals and returns non-zero if any have been
- * triggered (with debounce taken into account).
- *
- * @return non-zero if there has been a power-on event, 0 if not.
- */
-static int check_for_power_on_event(void)
-{
-	int ap_off_flag;
-
-	ap_off_flag = system_get_reset_flags() & EC_RESET_FLAG_AP_OFF;
-	system_clear_reset_flags(EC_RESET_FLAG_AP_OFF);
-	/* check if system is already ON */
-	if (is_power_good_asserted()) {
-		if (ap_off_flag) {
-			CPRINTS("system is on, but EC_RESET_FLAG_AP_OFF is on");
-			return POWER_ON_CANCEL;
-		} else {
-			CPRINTS("system is on, thus clear " "auto_power_on");
-			/* no need to arrange another power on */
-			auto_power_on = 0;
-			return POWER_ON_BY_IN_POWER_GOOD;
-		}
-	} else {
-		if (ap_off_flag) {
-			CPRINTS("EC_RESET_FLAG_AP_OFF is on");
-			power_off();
-			return POWER_ON_CANCEL;
-		}
-
-		CPRINTS("POWER_GOOD is not asserted");
-	}
-
-	/* power on requested at EC startup for recovery */
-	if (auto_power_on) {
-		auto_power_on = 0;
-		return POWER_ON_BY_AUTO_POWER_ON;
-	}
-
-	/* Check lid open */
-	if (lid_opened) {
-		lid_opened = 0;
-		return POWER_ON_BY_LID_OPEN;
-	}
-
-	/* check for power button press */
-	if (power_button_is_pressed())
-		return POWER_ON_BY_POWER_BUTTON_PRESSED;
-
-	if (power_request == POWER_REQ_ON) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_NONE;
-	}
-
-	return POWER_OFF_CANCEL;
-}
-
-void release_pmic_pwron_deferred(void)
-{
-	/* Release PMIC power button */
-	set_pmic_pwron(0);
-}
-DECLARE_DEFERRED(release_pmic_pwron_deferred);
-
-/**
- * Power on the AP
- */
-static void power_on(void)
-{
-	uint64_t t;
-
-	/* Set pull-up and enable interrupt */
-	gpio_set_flags(power_signal_list[MTK_SUSPEND_ASSERTED].gpio,
-		       GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH);
-
-	/* Make sure we de-assert and GPIO_PMIC_WARM_RESET_H pin. */
-	set_warm_reset(0);
-
-	/*
-	 * Before we push PMIC power button, wait for the PMI RTC ready, which
-	 * takes PMIC_RTC_STARTUP from the AC/battery is plugged in.
-	 */
-	t = get_time().val;
-	if (t < PMIC_RTC_STARTUP) {
-		uint32_t wait = PMIC_RTC_STARTUP - t;
-
-		CPRINTS("wait for %dms for PMIC RTC start-up", wait / MSEC);
-		usleep(wait);
-	}
-
-	/*
-	 * When power_on() is called, we are at S5S3. Initialize components
-	 * to ready state before AP is up.
-	 */
-	hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-	/* Push the power button */
-	set_pmic_pwron(1);
-	hook_call_deferred(&release_pmic_pwron_deferred_data,
-			   PMIC_PWRON_PRESS_TIME);
-
-	/* enable interrupt */
-	gpio_set_flags(GPIO_SUSPEND_L, INT_BOTH_PULL_UP);
-
-#ifdef BOARD_OAK
-	if (system_get_board_version() <= 3)
-		gpio_set_flags(GPIO_EC_INT_L, GPIO_OUTPUT | GPIO_OUT_HIGH);
-	else
-		gpio_set_flags(GPIO_EC_INT_L, GPIO_ODR_HIGH);
-#else
-	gpio_set_flags(GPIO_EC_INT_L, GPIO_ODR_HIGH);
-#endif
-
-	disable_sleep(SLEEP_MASK_AP_RUN);
-#ifdef HAS_TASK_POWERLED
-	powerled_set_state(POWERLED_STATE_ON);
-#endif
-	/* Call hooks now that AP is running */
-	hook_notify(HOOK_CHIPSET_STARTUP);
-
-	CPRINTS("AP running ...");
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	set_warm_reset(1);
-	usleep(PMIC_WARM_RESET_H_HOLD_TIME);
-	/* deassert the reset signals */
-	set_warm_reset(0);
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	int value;
-	static int boot_from_g3;
-
-	switch (state) {
-	case POWER_G3:
-		boot_from_g3 = check_for_power_on_event();
-		if (boot_from_g3)
-			return POWER_G3S5;
-		break;
-
-	case POWER_G3S5:
-		return POWER_S5;
-
-	case POWER_S5:
-		if (boot_from_g3) {
-			value = boot_from_g3;
-			boot_from_g3 = 0;
-		} else {
-			value = check_for_power_on_event();
-		}
-
-		if (value) {
-			CPRINTS("power on %d", value);
-			return POWER_S5S3;
-		}
-		return state;
-
-	case POWER_S5S3:
-		power_on();
-		if (power_wait_signals(IN_POWER_GOOD) == EC_SUCCESS) {
-			CPRINTS("POWER_GOOD seen");
-			power_button_was_pressed = 0;
-			return POWER_S3;
-		} else {
-			CPRINTS("POWER_GOOD not seen in time");
-		}
-		set_pmic_pwron(0);
-		return POWER_S5;
-
-	case POWER_S3:
-		if (is_power_good_deasserted()) {
-			power_off();
-			return POWER_S3S5;
-		} else if (is_suspend_deasserted())
-			return POWER_S3S0;
-		return state;
-
-	case POWER_S3S0:
-		disable_sleep(SLEEP_MASK_AP_RUN);
-#ifdef HAS_TASK_POWERLED
-		powerled_set_state(POWERLED_STATE_ON);
-#endif
-		hook_notify(HOOK_CHIPSET_RESUME);
-		return POWER_S0;
-
-	case POWER_S0:
-		value = check_for_power_off_event();
-		if (value) {
-			CPRINTS("power off %d", value);
-			power_off();
-			return POWER_S0S3;
-		} else if (is_suspend_asserted())
-			return POWER_S0S3;
-		return state;
-
-	case POWER_S0S3:
-#ifdef HAS_TASK_POWERLED
-		if (lid_is_open())
-			powerled_set_state(POWERLED_STATE_SUSPEND);
-		else
-			powerled_set_state(POWERLED_STATE_OFF);
-#endif
-		/*
-		 * if the power button is pressing, we need cancel the long
-		 * press timer, otherwise EC will crash.
-		 */
-		if (power_button_was_pressed)
-			timer_cancel(TASK_ID_CHIPSET);
-
-		/* Call hooks here since we don't know it prior to AP suspend */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		power_button_wait_for_release(-1);
-		power_button_was_pressed = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-static void powerbtn_mtk_changed(void)
-{
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_mtk_changed, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console debug command */
-
-static const char *power_req_name[POWER_REQ_COUNT] = {
-	"none",
-	"off",
-	"on",
-};
-
-/* Power states that we can report */
-enum power_state_t {
-	PSTATE_UNKNOWN,
-	PSTATE_OFF,
-	PSTATE_SUSPEND,
-	PSTATE_ON,
-
-	PSTATE_COUNT,
-};
-
-static const char * const state_name[] = {
-	"unknown",
-	"off",
-	"suspend",
-	"on",
-};
-
-static int command_power(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		enum power_state_t state;
-
-		state = PSTATE_UNKNOWN;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			state = PSTATE_OFF;
-		if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			state = PSTATE_SUSPEND;
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			state = PSTATE_ON;
-		ccprintf("%s\n", state_name[state]);
-
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &v))
-		return EC_ERROR_PARAM1;
-
-	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
-	ccprintf("Requesting power %s\n", power_req_name[power_request]);
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
diff --git a/power/mt8183.c b/power/mt8183.c
deleted file mode 100644
index bdbd319601..0000000000
--- a/power/mt8183.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* mt8183 chipset power control module for Chrome EC */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/*
- * mt8183 has two different power sequence versions
- * 0: for normal tablet and detachable form factor
- * 1: for boards have GPIO_EN_PP1800_S5_L
- * CONFIG_CHIPSET_POWER_SEQ_VERSION defaults to 0, re-define the power seq
- * version if needed.
- */
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_PGOOD_PMIC		POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
-#define IN_SUSPEND_ASSERTED	POWER_SIGNAL_MASK(AP_IN_S3_L)
-
-/* Rails required for S3 and S0 */
-#define IN_PGOOD_S0		(IN_PGOOD_PMIC)
-#define IN_PGOOD_S3		(IN_PGOOD_PMIC)
-
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0		(IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
-
-/* Long power key press to force shutdown in S0. go/crosdebug */
-#ifdef VARIANT_KUKUI_JACUZZI
-#define FORCED_SHUTDOWN_DELAY	(8 * SECOND)
-#else
-#define FORCED_SHUTDOWN_DELAY	(10 * SECOND)
-#endif
-
-/* Long power key press to boot from S5/G3 state. */
-#ifndef POWERBTN_BOOT_DELAY
-#define POWERBTN_BOOT_DELAY	(1 * SECOND)
-#endif
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-#define PMIC_EN_PULSE_MS 50
-
-/* Maximum time it should for PMIC to turn on after toggling PMIC_EN_ODL. */
-#define PMIC_EN_TIMEOUT (300 * MSEC)
-
-/*
- * Amount of time we need to hold PMIC_FORCE_RESET_ODL to ensure PMIC is really
- * off and will not restart on its own.
- */
-#define PMIC_FORCE_RESET_TIME (10 * SECOND)
-
-/* Time delay in G3 to deassert EN_PP1800_S5_L */
-#define EN_PP1800_S5_L_DEASSERT_TIME (20 * MSEC)
-
-/* Data structure for a GPIO operation for power sequencing */
-struct power_seq_op {
-	/* enum gpio_signal in 8 bits */
-	uint8_t signal;
-	uint8_t level;
-	/* Number of milliseconds to delay after setting signal to level */
-	uint8_t delay;
-};
-BUILD_ASSERT(GPIO_COUNT < 256);
-
-/*
- * This is the power sequence for POWER_S5S3.
- * The entries in the table are handled sequentially from the top
- * to the bottom.
- */
-
-static const struct power_seq_op s5s3_power_seq[] = {
-	/* Release PMIC watchdog. */
-	{ GPIO_PMIC_WATCHDOG_L, 1, 0 },
-	/* Turn on AP. */
-	{ GPIO_AP_SYS_RST_L, 1, 2 },
-};
-
-/* The power sequence for POWER_S3S0 */
-static const struct power_seq_op s3s0_power_seq[] = {
-};
-
-/* The power sequence for POWER_S0S3 */
-static const struct power_seq_op s0s3_power_seq[] = {
-};
-
-/* The power sequence for POWER_S3S5 */
-static const struct power_seq_op s3s5_power_seq[] = {
-	/* Turn off AP. */
-	{ GPIO_AP_SYS_RST_L, 0, 0 },
-	/* Assert watchdog to PMIC (there may be a 1.6ms debounce) */
-	{ GPIO_PMIC_WATCHDOG_L, 0, 3 },
-};
-
-static int forcing_shutdown;
-static int boot_from_cutoff;
-
-void chipset_reset_request_interrupt(enum gpio_signal signal)
-{
-	chipset_reset(CHIPSET_RESET_AP_REQ);
-}
-
-/*
- * Triggers on falling edge of AP watchdog line only. The falling edge can
- * happen in these 3 cases:
- *  - AP asserts watchdog while the AP is on: this is a real AP-initiated reset.
- *  - EC asserted GPIO_AP_SYS_RST_L, so the AP is in reset and AP watchdog falls
- *    as well. This is _not_ a watchdog reset. We mask these cases by disabling
- *    the interrupt just before shutting down the AP, and re-enabling it just
- *    after starting the AP.
- *  - PMIC has shut down (e.g. the AP powered off by itself), this is not a
- *    watchdog reset either. This should be covered by the case above if the
- *    EC reacts quickly enough, but we mask those cases as well by testing if
- *    the PMIC is still on when the watchdog line falls.
- */
-void chipset_watchdog_interrupt(enum gpio_signal signal)
-{
-	if (power_get_signals() & IN_PGOOD_PMIC)
-		chipset_reset(CHIPSET_RESET_AP_WATCHDOG);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	forcing_shutdown = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_force_shutdown_button(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
-}
-DECLARE_DEFERRED(chipset_force_shutdown_button);
-
-void chipset_exit_hard_off_button(void)
-{
-	/* Power up from off */
-	forcing_shutdown = 0;
-	chipset_exit_hard_off();
-}
-DECLARE_DEFERRED(chipset_exit_hard_off_button);
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-static void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-		CPRINTS("Chipset reset: exit s3");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-/* If chipset needs to be reset, EC also reboots to RO. */
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	int flags = SYSTEM_RESET_HARD;
-
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	cflush();
-	if (reason == CHIPSET_RESET_AP_WATCHDOG)
-		flags |= SYSTEM_RESET_AP_WATCHDOG;
-
-	system_reset(flags);
-
-	/* This should not be reachable. */
-	while (1)
-		;
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Enable reboot / sleep control inputs from AP */
-	gpio_enable_interrupt(GPIO_WARM_RESET_REQ);
-	gpio_enable_interrupt(GPIO_AP_IN_SLEEP_L);
-
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			disable_sleep(SLEEP_MASK_AP_RUN);
-			gpio_enable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-			CPRINTS("already in S0");
-			return POWER_S0;
-		}
-	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
-		/* Force shutdown from S5 if the PMIC is already up. */
-		if (power_get_signals() & IN_PGOOD_PMIC) {
-			forcing_shutdown = 1;
-			return POWER_S5;
-		}
-	} else {
-		/* Auto-power on */
-		chipset_exit_hard_off();
-
-		if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN)
-			boot_from_cutoff = 1;
-	}
-
-	/* Start from S5 if the PMIC is already up. */
-	if (power_get_signals() & IN_PGOOD_PMIC)
-		return POWER_S5;
-
-	return POWER_G3;
-}
-
-/*
- * If we have to force reset the PMIC, we only need to do so for a few seconds,
- * then we need to release the GPIO to prevent leakage in G3.
- */
-static void release_pmic_force_reset(void)
-{
-	CPRINTS("Releasing PMIC force reset");
-	gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-}
-DECLARE_DEFERRED(release_pmic_force_reset);
-
-/**
- * Step through the power sequence table and do corresponding GPIO operations.
- *
- * @param	power_seq_ops	The pointer to the power sequence table.
- * @param	op_count	The number of entries of power_seq_ops.
- */
-static void power_seq_run(const struct power_seq_op *power_seq_ops,
-			  int op_count)
-{
-	int i;
-
-	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
-		if (!power_seq_ops[i].delay)
-			continue;
-		msleep(power_seq_ops[i].delay);
-	}
-}
-
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-static void deassert_en_pp1800_s5_l(void)
-{
-	gpio_set_level(GPIO_EN_PP1800_S5_L, 1);
-}
-DECLARE_DEFERRED(deassert_en_pp1800_s5_l);
-#endif
-
-enum power_state power_handle_state(enum power_state state)
-{
-	/*
-	 * Set if we already had a rising edge on AP_SYS_RST_L. If so, any
-	 * subsequent boot attempt will require an EC reset.
-	 */
-	static int booted;
-
-	/* Retry S5->S3 transition, if not zero. */
-	static int s5s3_retry;
-
-	/*
-	 * PMIC power went away (AP most likely decided to shut down):
-	 * transition to S5, G3.
-	 */
-	static int ap_shutdown;
-	uint16_t tries = 0;
-
-	switch (state) {
-	case POWER_G3:
-
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-		hook_call_deferred(&deassert_en_pp1800_s5_l_data,
-				   EN_PP1800_S5_L_DEASSERT_TIME);
-#endif
-
-		/* Go back to S5->G3 if the PMIC unexpectedly starts again. */
-		if (power_get_signals() & IN_PGOOD_PMIC)
-			return POWER_S5G3;
-		break;
-
-	case POWER_S5:
-		boot_from_cutoff = 0;
-
-		/*
-		 * If AP initiated shutdown, PMIC is off, and we can transition
-		 * to G3 immediately.
-		 */
-		if (ap_shutdown) {
-			ap_shutdown = 0;
-			return POWER_S5G3;
-		} else if (!forcing_shutdown) {
-			/* Powering up. */
-			s5s3_retry = 1;
-			return POWER_S5S3;
-		}
-
-		/* Forcing shutdown */
-
-		/* Long press has worked, transition to G3. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC))
-			return POWER_S5G3;
-
-		/*
-		 * Try to force PMIC shutdown with a long press. This takes 8s,
-		 * shorter than the common code S5->G3 timeout (10s).
-		 */
-		CPRINTS("Forcing shutdown with long press.");
-		gpio_set_level(GPIO_PMIC_EN_ODL, 0);
-
-		/*
-		 * Stay in S5, common code will drop to G3 after timeout
-		 * if the long press does not work.
-		 */
-		return POWER_S5;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown)
-			return POWER_S3S5;
-		else if (!(power_get_signals() & IN_SUSPEND_ASSERTED))
-			return POWER_S3S0;
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0) ||
-		    forcing_shutdown ||
-		    power_get_signals() & IN_SUSPEND_ASSERTED)
-			return POWER_S0S3;
-
-		break;
-
-	case POWER_G3S5:
-		forcing_shutdown = 0;
-
-#ifdef CONFIG_BATTERY_SMART
-		/*
-		 * b:148045048: With the adapter to activate the smart battery
-		 * which is shutdown mode, will enable PMIC during activation
-		 * and have heavy loading, which will prevent the system from
-		 * powering on. Delay to boot system until the smart battry
-		 * is ready.
-		 */
-		if (battery_hw_present() && boot_from_cutoff) {
-			static int total_sleep_ms;
-
-			if (total_sleep_ms < 4000) {
-				msleep(10);
-				total_sleep_ms += 10;
-				return POWER_G3S5;
-			}
-		}
-#endif
-
-		/*
-		 * Allow time for charger to be initialized, in case we're
-		 * trying to boot the AP with no battery.
-		 */
-		while (charge_prevent_power_on(0) &&
-		       tries++ < CHARGER_INITIALIZED_TRIES) {
-			msleep(CHARGER_INITIALIZED_DELAY_MS);
-		}
-
-		/* Return to G3 if battery level is too low. */
-		if (charge_want_shutdown() ||
-		    tries > CHARGER_INITIALIZED_TRIES) {
-			CPRINTS("power-up inhibited");
-			chipset_force_shutdown(
-				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
-			return POWER_G3;
-		}
-
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-		hook_call_deferred(&deassert_en_pp1800_s5_l_data, -1);
-#endif
-		hook_call_deferred(&release_pmic_force_reset_data, -1);
-		gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-		gpio_set_level(GPIO_EN_PP1800_S5_L, 0);
-#endif
-
-		/* Power up to next state */
-		return POWER_S5;
-
-	case POWER_S5S3:
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		/*
-		 * Release power button in case it was pressed by force shutdown
-		 * sequence.
-		 */
-		gpio_set_level(GPIO_PMIC_EN_ODL, 1);
-
-		/* If PMIC is off, switch it on by pulsing PMIC enable. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC)) {
-			msleep(PMIC_EN_PULSE_MS);
-			gpio_set_level(GPIO_PMIC_EN_ODL, 0);
-			msleep(PMIC_EN_PULSE_MS);
-			gpio_set_level(GPIO_PMIC_EN_ODL, 1);
-		}
-
-		/* If EC jumped, or has already booted once, reboot to RO. */
-		if (system_jumped_to_this_image() || booted) {
-			/*
-			 * TODO(b:109850749): How quickly does the EC come back
-			 * up? Would IN_PGOOD_PMIC be ready by the time we are
-			 * back? According to PMIC spec, it should take ~158 ms
-			 * after debounce (32 ms), minus PMIC_EN_PULSE_MS above.
-			 * It would be good to avoid another _EN pulse above.
-			 */
-			chipset_reset(CHIPSET_RESET_AP_REQ);
-		}
-
-		/*
-		 * Wait for PMIC to bring up rails. Retry if it fails
-		 * (it may take 2 attempts on restart after we use
-		 * force reset).
-		 */
-		if (power_wait_signals_timeout(IN_PGOOD_PMIC,
-					       PMIC_EN_TIMEOUT)) {
-			if (s5s3_retry) {
-				s5s3_retry = 0;
-				return POWER_S5S3;
-			}
-			/* Give up, go back to G3. */
-			return POWER_S5G3;
-		}
-
-		booted = 1;
-		/* Enable S3 power supplies, release AP reset. */
-		power_seq_run(s5s3_power_seq, ARRAY_SIZE(s5s3_power_seq));
-		gpio_enable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		/*
-		 * Clearing the sleep failure detection tracking on the path
-		 * to S0 to handle any reset conditions.
-		 */
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		power_reset_host_sleep_state();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-		/* Power up to next state */
-		return POWER_S3;
-
-	case POWER_S3S0:
-		power_seq_run(s3s0_power_seq, ARRAY_SIZE(s3s0_power_seq));
-
-		if (power_wait_signals(IN_PGOOD_S0)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S0S3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		sleep_resume_transition();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/* Power up to next state */
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		sleep_suspend_transition();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-		/*
-		 * TODO(b:109850749): Check if we need some delay here to
-		 * "debounce" entering suspend (rk3399 uses 20ms delay).
-		 */
-
-		power_seq_run(s0s3_power_seq, ARRAY_SIZE(s0s3_power_seq));
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * In case the power button is held awaiting power-off timeout,
-		 * power off immediately now that we're entering S3.
-		 */
-		if (power_button_is_pressed()) {
-			forcing_shutdown = 1;
-			hook_call_deferred(&chipset_force_shutdown_button_data,
-					-1);
-		}
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* PMIC has shutdown, transition to G3. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC))
-			ap_shutdown = 1;
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		gpio_disable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-		power_seq_run(s3s5_power_seq, ARRAY_SIZE(s3s5_power_seq));
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return POWER_S5;
-
-	case POWER_S5G3:
-		/* Release the power button, in case it was long pressed. */
-		if (forcing_shutdown)
-			gpio_set_level(GPIO_PMIC_EN_ODL, 1);
-
-		/*
-		 * If PMIC is still not off, assert PMIC_FORCE_RESET_ODL.
-		 * This should only happen for forced shutdown where the AP is
-		 * not able to send a command to the PMIC, and where the long
-		 * power+home press did not work (if the PMIC is misconfigured).
-		 * Also, PMIC will lose RTC state, in that case.
-		 */
-		if (power_get_signals() & IN_PGOOD_PMIC) {
-			CPRINTS("Forcing PMIC off");
-			gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
-			msleep(5);
-			hook_call_deferred(&release_pmic_force_reset_data,
-				PMIC_FORCE_RESET_TIME);
-
-			return POWER_S5G3;
-		}
-
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-static void suspend_hang_detected(void)
-{
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	CPRINTS("Handle sleep: %d", state);
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * S3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-		sleep_start_suspend(ctx, suspend_hang_detected);
-
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		sleep_complete_resume(ctx);
-
-	}
-}
-#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-static void power_button_changed(void)
-{
-	if (power_button_is_pressed()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			hook_call_deferred(&chipset_exit_hard_off_button_data,
-					   POWERBTN_BOOT_DELAY);
-
-		/* Delayed power down from S0/S3, cancel on PB release */
-		hook_call_deferred(&chipset_force_shutdown_button_data,
-				   FORCED_SHUTDOWN_DELAY);
-	} else {
-		/* Power button released, cancel deferred shutdown/boot */
-		hook_call_deferred(&chipset_exit_hard_off_button_data, -1);
-		hook_call_deferred(&chipset_force_shutdown_button_data, -1);
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_LID_SWITCH
-static void lid_changed(void)
-{
-	/* Power-up from off on lid open */
-	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		chipset_exit_hard_off();
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, lid_changed, HOOK_PRIO_DEFAULT);
-#endif
diff --git a/power/mt8192.c b/power/mt8192.c
deleted file mode 100644
index 323994faea..0000000000
--- a/power/mt8192.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * MT8192 SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- * When powered off:
- *  - Press power button turns on the AP
- *  - Hold power button turns on the AP, and then 8s later turns it off and
- *    leaves it off until pwron is released and press again.
- *  - Lid open turns on the AP
- *
- *  When powered on:
- *  - Holding power button for 8s powers off the AP
- *  - Pressing and releaseing pwron within that 8s is ignored
- */
-
-#include "battery.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-
-#ifdef CONFIG_BRINGUP
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level_verbose(CC_CHIPSET, signal, value)
-#else
-#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
-#endif
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
-
-/* Input state flags */
-#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3_L)
-#define IN_PGOOD_PMIC POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
-#define IN_AP_WDT_ASSERTED POWER_SIGNAL_MASK(AP_WDT_ASSERTED)
-
-/* Rails required for S3 and S0 */
-#define IN_PGOOD_S0 (IN_PGOOD_PMIC)
-#define IN_PGOOD_S3 (IN_PGOOD_PMIC)
-
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
-
-/* Long power key press to force shutdown in S0. go/crosdebug */
-#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
-
-/* Long power key press to boot from S5/G3 state. */
-#ifndef POWERBTN_BOOT_DELAY
-#define POWERBTN_BOOT_DELAY (10 * MSEC)
-#endif
-#define PMIC_EN_PULSE_MS 50
-
-/* Maximum time it should for PMIC to turn on after toggling PMIC_EN_ODL. */
-#define PMIC_EN_TIMEOUT (300 * MSEC)
-
-/* Time delay in G3 to deassert EN_PP1800_S5_L */
-#define EN_PP1800_S5_L_DEASSERT_TIME (20 * MSEC)
-
-/*
- * Time delay for AP on/off the AP_EC_WDT when received SYS_RST_ODL.
- * Generally it can be done within 3 ms.
- */
-#define AP_EC_WDT_TIMEOUT (100 * MSEC)
-
-/* 30 ms for hard reset, we hold it longer to prevent TPM false alarm. */
-#define SYS_RST_PULSE_LENGTH (50 * MSEC)
-
-/* power signal list.  Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	{GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-	{GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"},
-	{GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED"},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-static int forcing_shutdown;
-
-static void watchdog_interrupt_deferred(void)
-{
-	chipset_reset(CHIPSET_RESET_AP_WATCHDOG);
-}
-DECLARE_DEFERRED(watchdog_interrupt_deferred);
-
-static void reset_request_interrupt_deferred(void)
-{
-	chipset_reset(CHIPSET_RESET_AP_REQ);
-}
-DECLARE_DEFERRED(reset_request_interrupt_deferred);
-
-void chipset_reset_request_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&reset_request_interrupt_deferred_data, 0);
-}
-
-/*
- * Triggers on falling edge of AP watchdog line only. The falling edge can
- * happen in these 3 cases:
- *  - AP asserts watchdog while the AP is on: this is a real AP-initiated reset.
- *  - EC asserted GPIO_SYS_RST_ODL, so the AP is in reset and AP watchdog falls
- *    as well. This is _not_ a watchdog reset. We mask these cases by disabling
- *    the interrupt just before shutting down the AP, and re-enabling it just
- *    after starting the AP.
- *  - PMIC has shut down (e.g. the AP powered off by itself), this is not a
- *    watchdog reset either. This should be covered by the case above if the
- *    EC reacts quickly enough, but we mask those cases as well by testing if
- *    the PMIC is still on when the watchdog line falls.
- */
-void chipset_watchdog_interrupt(enum gpio_signal signal)
-{
-	/* Pass AP_EC_WATCHDOG_L signal to PMIC */
-	GPIO_SET_LEVEL(GPIO_EC_PMIC_WATCHDOG_L, gpio_get_level(signal));
-
-	/* Update power signals */
-	power_signal_interrupt(signal);
-
-	/*
-	 * case 1: PMIC is good, WDT asserts, and EC is not asserting
-	 * SYS_RST_ODL. This is AP initiated real WDT.
-	 */
-	if (gpio_get_level(GPIO_SYS_RST_ODL) &&
-	    power_get_signals() & IN_PGOOD_PMIC &&
-	    power_get_signals() & IN_AP_WDT_ASSERTED)
-		hook_call_deferred(&watchdog_interrupt_deferred_data, 0);
-
-	/*
-	 * case 2&3: Fall through. The chipset_reset should have been
-	 * invoked.
-	 */
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	forcing_shutdown = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_force_shutdown_button(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
-}
-DECLARE_DEFERRED(chipset_force_shutdown_button);
-
-void chipset_exit_hard_off_button(void)
-{
-	/* Power up from off */
-	forcing_shutdown = 0;
-	chipset_exit_hard_off();
-}
-DECLARE_DEFERRED(chipset_exit_hard_off_button);
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
-	usleep(SYS_RST_PULSE_LENGTH);
-	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
-}
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-static void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-		CPRINTS("Chipset reset: exit s3");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-enum power_state power_chipset_init(void)
-{
-	int exit_hard_off = 1;
-
-	/* Enable reboot / sleep control inputs from AP */
-	gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
-	gpio_enable_interrupt(GPIO_AP_IN_SLEEP_L);
-
-	if (system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			disable_sleep(SLEEP_MASK_AP_RUN);
-			power_signal_enable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-			CPRINTS("already in S0");
-			return POWER_S0;
-		}
-	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
-		exit_hard_off = 0;
-	} else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-			gpio_get_level(GPIO_AC_PRESENT)) {
-		/*
-		 * If AC present, assume this is a wake-up by AC insert.
-		 * Boot EC only.
-		 *
-		 * Note that extpower module is not initialized at this point,
-		 * the only way is to ask GPIO_AC_PRESENT directly.
-		 */
-		exit_hard_off = 0;
-	}
-
-	if (battery_is_present() == BP_YES)
-		/*
-		 * (crosbug.com/p/28289): Wait battery stable.
-		 * Some batteries use clock stretching feature, which requires
-		 * more time to be stable.
-		 */
-		battery_wait_for_stable();
-
-	if (exit_hard_off)
-		/* Auto-power on */
-		chipset_exit_hard_off();
-
-	/* Start from S5 if the PMIC is already up. */
-	if (power_get_signals() & IN_PGOOD_PMIC) {
-		/* Force shutdown from S5 if the PMIC is already up. */
-		if (!exit_hard_off)
-			forcing_shutdown = 1;
-		return POWER_S5;
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	/* Retry S5->S3 transition, if not zero. */
-	static int s5s3_retry;
-
-	/*
-	 * PMIC power went away (AP most likely decided to shut down):
-	 * transition to S5, G3.
-	 */
-	static int ap_shutdown;
-
-	switch (state) {
-	case POWER_G3:
-
-		/* Go back to S5->G3 if the PMIC unexpectedly starts again. */
-		if (power_get_signals() & IN_PGOOD_PMIC)
-			return POWER_S5G3;
-		break;
-
-	case POWER_S5:
-		/*
-		 * If AP initiated shutdown, PMIC is off, and we can transition
-		 * to G3 immediately.
-		 */
-		if (ap_shutdown) {
-			ap_shutdown = 0;
-			return POWER_S5G3;
-		} else if (!forcing_shutdown) {
-			/* Powering up. */
-			s5s3_retry = 1;
-			return POWER_S5S3;
-		}
-
-		/* Forcing shutdown */
-
-		/* Long press has worked, transition to G3. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC))
-			return POWER_S5G3;
-
-		/*
-		 * Try to force PMIC shutdown with a long press. This takes 8s,
-		 * shorter than the common code S5->G3 timeout (10s).
-		 *
-		 * Note: We might run twice at this line because we
-		 * deasserts SYS_RST_ODL in S5->S3 and then WDT interrupt
-		 * handler sets the wake event for chipset_task. This should be
-		 * no harm, but to prevent misunderstanding in the console, we
-		 * check EC_PMIC_EN_ODL before set.
-		 */
-		if (gpio_get_level(GPIO_EC_PMIC_EN_ODL)) {
-			CPRINTS("Forcing shutdown with long press.");
-			GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
-		}
-
-		/*
-		 * Stay in S5, common code will drop to G3 after timeout
-		 * if the long press does not work.
-		 */
-		return POWER_S5;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown)
-			return POWER_S3S5;
-		else if (!(power_get_signals() & IN_SUSPEND_ASSERTED))
-			return POWER_S3S0;
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0) || forcing_shutdown ||
-		    power_get_signals() & IN_SUSPEND_ASSERTED)
-			return POWER_S0S3;
-
-		break;
-
-	case POWER_G3S5:
-		forcing_shutdown = 0;
-
-		/* Power up to next state */
-		return POWER_S5;
-
-	case POWER_S5S3:
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		/*
-		 * Release power button in case it was pressed by force shutdown
-		 * sequence.
-		 */
-		GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
-
-		/* If PMIC is off, switch it on by pulsing PMIC enable. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC)) {
-			msleep(PMIC_EN_PULSE_MS);
-			GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
-			msleep(PMIC_EN_PULSE_MS);
-			GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
-		}
-
-		/*
-		 * Wait for PMIC to bring up rails. Retry if it fails
-		 * (it may take 2 attempts on restart after we use
-		 * force reset).
-		 */
-		if (power_wait_signals_timeout(IN_PGOOD_PMIC,
-					       PMIC_EN_TIMEOUT)) {
-			if (s5s3_retry) {
-				s5s3_retry = 0;
-				return POWER_S5S3;
-			}
-			/* Give up, go back to G3. */
-			return POWER_S5G3;
-		}
-
-		/* Release AP reset and waits for AP pulling WDT up. */
-		power_signal_enable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-		GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1);
-		if (power_wait_mask_signals_timeout(0, IN_AP_WDT_ASSERTED,
-						    AP_EC_WDT_TIMEOUT)) {
-			if (s5s3_retry) {
-				s5s3_retry = 0;
-				return POWER_S5S3;
-			}
-			/* Give up, go back to G3. */
-			return POWER_S5G3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		/*
-		 * Clearing the sleep failure detection tracking on the path
-		 * to S0 to handle any reset conditions.
-		 */
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		power_reset_host_sleep_state();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-		/* Power up to next state */
-		return POWER_S3;
-
-	case POWER_S3S0:
-		if (power_wait_signals(IN_PGOOD_S0)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S0S3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		sleep_resume_transition();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/* Power up to next state */
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-#ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-		sleep_suspend_transition();
-#endif /* CONFIG_POWER_SLEEP_FAILURE_DETECTION */
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * In case the power button is held awaiting power-off timeout,
-		 * power off immediately now that we're entering S3.
-		 */
-		if (power_button_is_pressed()) {
-			forcing_shutdown = 1;
-			hook_call_deferred(&chipset_force_shutdown_button_data,
-					   -1);
-		}
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* PMIC has shutdown, transition to G3. */
-		if (!(power_get_signals() & IN_PGOOD_PMIC))
-			ap_shutdown = 1;
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/*
-		 * Assert SYS_RST_ODL, and waits for AP finishing epilogue and
-		 * asserting WDT.
-		 */
-		GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
-		if (EC_ERROR_TIMEOUT ==
-		    power_wait_signals_timeout(IN_AP_WDT_ASSERTED,
-					       AP_EC_WDT_TIMEOUT)) {
-			CPRINTS("Timeout waitting AP watchdog, force if off");
-			GPIO_SET_LEVEL(GPIO_EC_PMIC_WATCHDOG_L, 0);
-		}
-		power_signal_disable_interrupt(GPIO_AP_EC_WATCHDOG_L);
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return POWER_S5;
-
-	case POWER_S5G3:
-		/* Release the power button, in case it was long pressed. */
-		if (forcing_shutdown)
-			GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 1);
-
-		/* If PMIC is not off, go back to S5 and try again. */
-		if (power_get_signals() & IN_PGOOD_PMIC)
-			return POWER_S5;
-
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-static void power_button_changed(void)
-{
-	if (power_button_is_pressed()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			hook_call_deferred(&chipset_exit_hard_off_button_data,
-					   POWERBTN_BOOT_DELAY);
-
-		/* Delayed power down from S0/S3, cancel on PB release */
-		hook_call_deferred(&chipset_force_shutdown_button_data,
-				   FORCED_SHUTDOWN_DELAY);
-	} else {
-		/* Power button released, cancel deferred shutdown/boot */
-		hook_call_deferred(&chipset_exit_hard_off_button_data, -1);
-		hook_call_deferred(&chipset_force_shutdown_button_data, -1);
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-static void suspend_hang_detected(void)
-{
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	CPRINTS("Handle sleep: %d", state);
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * S3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-		sleep_start_suspend(ctx, suspend_hang_detected);
-
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		sleep_complete_resume(ctx);
-
-	}
-}
-#endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-#ifdef CONFIG_LID_SWITCH
-static void lid_changed(void)
-{
-	/* Power-up from off on lid open */
-	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		chipset_exit_hard_off();
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, lid_changed, HOOK_PRIO_DEFAULT);
-#endif
diff --git a/power/qcom.c b/power/qcom.c
deleted file mode 100644
index ef9e329111..0000000000
--- a/power/qcom.c
+++ /dev/null
@@ -1,1169 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SC7X80 SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- *  When powered off:
- *  - Press power button turns on the AP
- *  - Hold power button turns on the AP, and then 8s later turns it off and
- *    leaves it off until pwron is released and pressed again
- *  - Lid open turns on the AP
- *
- *  When powered on:
- *  - Holding power button for 8s powers off the AP
- *  - Pressing and releasing pwron within that 8s is ignored
- *  - If POWER_GOOD is dropped by the AP, then we power the AP off
- */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power/qcom.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Power signal list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[SC7X80_AP_RST_ASSERTED] = {
-		GPIO_AP_RST_L,
-		POWER_SIGNAL_ACTIVE_LOW | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"AP_RST_ASSERTED",
-	},
-	[SC7X80_PS_HOLD] = {
-		GPIO_PS_HOLD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PS_HOLD",
-	},
-	[SC7X80_POWER_GOOD] = {
-		GPIO_POWER_GOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"POWER_GOOD",
-	},
-	[SC7X80_AP_SUSPEND] = {
-		GPIO_AP_SUSPEND,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"AP_SUSPEND",
-	},
-#ifdef CONFIG_CHIPSET_SC7180
-	[SC7X80_WARM_RESET] = {
-		GPIO_WARM_RESET_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"WARM_RESET_L",
-	},
-	[SC7X80_DEPRECATED_AP_RST_REQ] = {
-		GPIO_DEPRECATED_AP_RST_REQ,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"DEPRECATED_AP_RST_REQ",
-	},
-#endif /* defined(CONFIG_CHIPSET_SC7180) */
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SC7X80_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED)
-#define IN_SUSPEND		POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND)
-
-
-/* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
-
-/*
- * If the power button is pressed to turn on, then held for this long, we
- * power off.
- *
- * Normal case: User releases power button and chipset_task() goes
- *    into the inner loop, waiting for next event to occur (power button
- *    press or POWER_GOOD == 0).
- */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
-
-/*
- * After trigger PMIC power sequence, how long it triggers AP to turn on
- * or off. Observed that the worst case is ~150ms. Pick a safe vale.
- */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
-
-/*
- * After force off the switch cap, how long the PMIC/AP totally off.
- * Observed that the worst case is 2s. Pick a safe vale.
- */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
-
-/* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
-
-/* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
-
-/* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(1500 * MSEC)
-
-/* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(200 * MSEC)
-
-/* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(100 * MSEC)
-
-/* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(6 * MSEC)
-
-/*
- * Delay between power-on the system and power-on the PMIC.
- * Some latest PMIC firmware needs this delay longer, for doing a cold
- * reboot.
- *
- * Measured on Herobrine IOB + Trogdor MLB, the delay takes ~200ms. Set
- * it with margin.
- */
-#define SYSTEM_POWER_ON_DELAY		(300 * MSEC)
-
-/*
- * Delay between the PMIC power drop and power-off the system.
- * Qualcomm measured the entire POFF duration is around 70ms. Setting
- * this delay to the same value as the above power-on sequence, which
- * has much safer margin.
- */
-#define PMIC_POWER_OFF_DELAY		(150 * MSEC)
-
-/* The AP_RST_L transition count of a normal AP warm reset */
-#define EXPECTED_AP_RST_TRANSITIONS	3
-
-/*
- * The timeout of waiting the next AP_RST_L transition. We measured
- * the interval between AP_RST_L transitions is 130ms ~ 150ms. Pick
- * a safer value.
- */
-#define AP_RST_TRANSITION_TIMEOUT	(450 * MSEC)
-
-/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
-/* 1 if the power button was pressed last time we checked */
-static char power_button_was_pressed;
-
-/* 1 if lid-open event has been detected */
-static char lid_opened;
-
-/* Time where we will power off, if power button still held down */
-static timestamp_t power_off_deadline;
-
-/* Force AP power on (used for recovery keypress) */
-static int auto_power_on;
-
-enum power_request_t {
-	POWER_REQ_NONE,
-	POWER_REQ_OFF,
-	POWER_REQ_ON,
-	POWER_REQ_RESET,
-
-	POWER_REQ_COUNT,
-};
-
-static enum power_request_t power_request;
-
-/**
- * Return values for check_for_power_off_event().
- */
-enum power_off_event_t {
-	POWER_OFF_CANCEL,
-	POWER_OFF_BY_POWER_BUTTON_PRESSED,
-	POWER_OFF_BY_LONG_PRESS,
-	POWER_OFF_BY_POWER_GOOD_LOST,
-	POWER_OFF_BY_POWER_REQ_OFF,
-	POWER_OFF_BY_POWER_REQ_RESET,
-
-	POWER_OFF_EVENT_COUNT,
-};
-
-/**
- * Return values for check_for_power_on_event().
- */
-enum power_on_event_t {
-	POWER_ON_CANCEL,
-	POWER_ON_BY_AUTO_POWER_ON,
-	POWER_ON_BY_LID_OPEN,
-	POWER_ON_BY_POWER_BUTTON_PRESSED,
-	POWER_ON_BY_POWER_REQ_ON,
-	POWER_ON_BY_POWER_REQ_RESET,
-
-	POWER_ON_EVENT_COUNT,
-};
-
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-static int ap_rst_transitions;
-
-static void notify_chipset_reset(void)
-{
-	if (ap_rst_transitions != EXPECTED_AP_RST_TRANSITIONS)
-		CPRINTS("AP_RST_L transitions not expected: %d",
-			ap_rst_transitions);
-
-	ap_rst_transitions = 0;
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(notify_chipset_reset);
-#endif
-
-void chipset_ap_rst_interrupt(enum gpio_signal signal)
-{
-#ifdef CONFIG_CHIPSET_RESET_HOOK
-	int delay;
-
-	/*
-	 * Only care the raising edge and AP in S0/S3. The single raising edge
-	 * of AP power-on during S5S3 is ignored.
-	 */
-	if (gpio_get_level(GPIO_AP_RST_L) &&
-	    chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_SUSPEND)) {
-		ap_rst_transitions++;
-		if (ap_rst_transitions >= EXPECTED_AP_RST_TRANSITIONS) {
-			/*
-			 * Reach the expected transition count. AP is booting
-			 * up. Notify HOOK_CHIPSET_RESET immediately.
-			 */
-			delay = 0;
-		} else {
-			/*
-			 * Should have more transitions of the AP_RST_L signal.
-			 * In case the AP_RST_L signal is not toggled, still
-			 * notify HOOK_CHIPSET_RESET.
-			 */
-			delay = AP_RST_TRANSITION_TIMEOUT;
-		}
-		hook_call_deferred(&notify_chipset_reset_data, delay);
-	}
-#endif
-	power_signal_interrupt(signal);
-}
-
-/* Issue a request to initiate a reset sequence */
-static void request_cold_reset(void)
-{
-	power_request = POWER_REQ_RESET;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-#ifdef CONFIG_CHIPSET_SC7180
-
-/* 1 if AP_RST_L and PS_HOLD is overdriven by EC */
-static char ap_rst_overdriven;
-
-void chipset_warm_reset_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * The warm_reset signal is pulled-up by a rail from PMIC. If the
-	 * warm_reset drops, it means:
-	 *  * Servo or Cr50 holds the signal, or
-	 *  * its pull-up rail POWER_GOOD drops.
-	 */
-	if (!gpio_get_level(GPIO_WARM_RESET_L)) {
-		if (gpio_get_level(GPIO_POWER_GOOD)) {
-			/*
-			 * Servo or Cr50 holds the WARM_RESET_L signal.
-			 *
-			 * Overdrive AP_RST_L to hold AP. Overdrive PS_HOLD to
-			 * emulate AP being up to trick the PMIC into thinking
-			 * there’s nothing weird going on.
-			 */
-			ap_rst_overdriven = 1;
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
-		}
-		/* Ignore the else clause, the pull-up rail drops. */
-	} else {
-		if (ap_rst_overdriven) {
-			/*
-			 * Servo or Cr50 releases the WARM_RESET_L signal.
-			 *
-			 * Cold reset the PMIC, doing S0->S5->S0 transition,
-			 * by issuing a request to initiate a reset sequence,
-			 * to recover the system. The transition to S5 makes
-			 * POWER_GOOD drop that triggers an interrupt to
-			 * high-Z both AP_RST_L and PS_HOLD.
-			 */
-			CPRINTS("Long warm reset ended, "
-				"cold resetting to restore confidence.");
-			request_cold_reset();
-		}
-		/* If not overdriven, just a normal power-up, do nothing. */
-	}
-	power_signal_interrupt(signal);
-}
-
-void chipset_power_good_interrupt(enum gpio_signal signal)
-{
-	if (!gpio_get_level(GPIO_POWER_GOOD) && ap_rst_overdriven) {
-		/*
-		 * POWER_GOOD is the pull-up rail of WARM_RESET_L.
-		 * When POWER_GOOD drops, high-Z both AP_RST_L and PS_HOLD
-		 * to restore their states.
-		 */
-		gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
-		gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
-		ap_rst_overdriven = 0;
-	}
-	power_signal_interrupt(signal);
-}
-#endif /* defined(CONFIG_CHIPSET_SC7180) */
-
-static void sc7x80_lid_event(void)
-{
-	/* Power task only cares about lid-open events */
-	if (!lid_is_open())
-		return;
-
-	lid_opened = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, sc7x80_lid_event, HOOK_PRIO_DEFAULT);
-
-static void sc7x80_powerbtn_changed(void)
-{
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, sc7x80_powerbtn_changed,
-	     HOOK_PRIO_DEFAULT);
-
-/**
- * Wait the switchcap GPIO0 PVC_PG signal asserted.
- *
- * When the output voltage is over the threshold PVC_PG_ADJ,
- * the PVC_PG is asserted.
- *
- * PVG_PG_ADJ is configured to 3.0V.
- * GPIO0 is configured as PVC_PG.
- *
- * @param enable	1 to wait the PMIC/AP on.
- *			0 to wait the PMIC/AP off.
- *
- * @return EC_SUCCESS or error
- */
-static int wait_switchcap_power_good(int enable)
-{
-	timestamp_t poll_deadline;
-
-	poll_deadline = get_time();
-	poll_deadline.val += SWITCHCAP_PG_CHECK_TIMEOUT;
-	while (enable != board_is_switchcap_power_good() &&
-	       get_time().val < poll_deadline.val) {
-		usleep(SWITCHCAP_PG_CHECK_WAIT);
-	}
-
-	/*
-	 * Check the timeout case. Just show a message. More check later
-	 * will switch the power state.
-	 */
-	if (enable != board_is_switchcap_power_good()) {
-		if (enable)
-			CPRINTS("SWITCHCAP NO POWER GOOD!");
-		else
-			CPRINTS("SWITCHCAP STILL POWER GOOD!");
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Get the state of the system power signals.
- *
- * @return 1 if the system is powered, 0 if not
- */
-static int is_system_powered(void)
-{
-	return board_is_switchcap_enabled();
-}
-
-/**
- * Get the PMIC/AP power signal.
- *
- * We treat the PMIC chips and the AP as a whole here. Don't deal with
- * the individual chip.
- *
- * @return 1 if the PMIC/AP is powered, 0 if not
- */
-static int is_pmic_pwron(void)
-{
-	/* Use POWER_GOOD to indicate PMIC/AP is on/off */
-	return gpio_get_level(GPIO_POWER_GOOD);
-}
-
-/**
- * Wait the PMIC/AP power-on state.
- *
- * @param enable	1 to wait the PMIC/AP on.
- *			0 to wait the PMIC/AP off.
- * @param timeout	Number of microsecond of timeout.
- *
- * @return EC_SUCCESS or error
- */
-static int wait_pmic_pwron(int enable, unsigned int timeout)
-{
-	timestamp_t poll_deadline;
-
-	/* Check the AP power status */
-	if (enable == is_pmic_pwron())
-		return EC_SUCCESS;
-
-	poll_deadline = get_time();
-	poll_deadline.val += timeout;
-	while (enable != is_pmic_pwron() &&
-	       get_time().val < poll_deadline.val) {
-		usleep(PMIC_POWER_AP_WAIT);
-	}
-
-	/* Check the timeout case */
-	if (enable != is_pmic_pwron()) {
-		if (enable)
-			CPRINTS("AP POWER NOT READY!");
-		else
-			CPRINTS("AP POWER STILL UP!");
-
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
-/**
- * Set the state of the system power signals but without any check.
- *
- * The system power signals are the enable pins of SwitchCap.
- * They control the power of the set of PMIC chips and the AP.
- *
- * @param enable	1 to enable or 0 to disable
- */
-static void set_system_power_no_check(int enable)
-{
-	board_set_switchcap_power(enable);
-}
-
-/**
- * Set the state of the system power signals.
- *
- * The system power signals are the enable pins of SwitchCap.
- * They control the power of the set of PMIC chips and the AP.
- *
- * @param enable	1 to enable or 0 to disable
- *
- * @return EC_SUCCESS or error
- */
-static int set_system_power(int enable)
-{
-	int ret;
-
-	CPRINTS("%s(%d)", __func__, enable);
-	set_system_power_no_check(enable);
-
-	ret = wait_switchcap_power_good(enable);
-
-	if (!enable) {
-		/* Ensure POWER_GOOD drop to low if it is a forced shutdown */
-		ret |= wait_pmic_pwron(0, FORCE_OFF_RESPONSE_TIMEOUT);
-	}
-	usleep(SYSTEM_POWER_ON_DELAY);
-
-	return ret;
-}
-
-/**
- * Set the PMIC/AP power-on state.
- *
- * It triggers the PMIC/AP power-on and power-off sequence.
- *
- * @param enable	1 to power the PMIC/AP on.
- *			0 to power the PMIC/AP off.
- *
- * @return EC_SUCCESS or error
- */
-static int set_pmic_pwron(int enable)
-{
-	int ret;
-
-	CPRINTS("%s(%d)", __func__, enable);
-
-	/* Check the PMIC/AP power state */
-	if (enable == is_pmic_pwron())
-		return EC_SUCCESS;
-
-	if (!gpio_get_level(GPIO_PMIC_KPD_PWR_ODL)) {
-		CPRINTS("PMIC_KPD_PWR_ODL not pulled up by PMIC; cancel pwron");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/*
-	 * Power-on sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL, which is a power-on trigger
-	 * 2. PMIC supplies power to POWER_GOOD
-	 * 3. Release PMIC_KPD_PWR_ODL
-	 *
-	 * Power-off sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
-	 *    trigger (requiring reprogramming PMIC registers to make
-	 *    PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
-	 * 2. PMIC stops supplying power to POWER_GOOD (requiring
-	 *    reprogramming PMIC to set the stage-1 and stage-2 reset timers to
-	 *    0 such that the pull down happens just after the deboucing time
-	 *    of the trigger, like 2ms)
-	 * 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
-	 *
-	 * If the above PMIC registers not programmed or programmed wrong, it
-	 * falls back to the next functions, which cuts off the system power.
-	 */
-
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	ret = wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-
-	return ret;
-}
-
-enum power_state power_chipset_init(void)
-{
-	int init_power_state;
-	uint32_t reset_flags = system_get_reset_flags();
-
-	/* Enable interrupts */
-	if (IS_ENABLED(CONFIG_CHIPSET_SC7180)) {
-		gpio_enable_interrupt(GPIO_WARM_RESET_L);
-		gpio_enable_interrupt(GPIO_POWER_GOOD);
-	}
-
-	/*
-	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
-	 * the AP could stay in strange state.
-	 */
-	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("not sysjump; forcing system shutdown");
-		set_system_power_no_check(0);
-		init_power_state = POWER_G3;
-	} else {
-		/* In the SYSJUMP case, we check if the AP is on */
-		if (power_get_signals() & IN_POWER_GOOD) {
-			CPRINTS("SOC ON");
-			init_power_state = POWER_S0;
-
-			/*
-			 * Reenable the power signal AP_RST_L interrupt, which
-			 * should be enabled during S5->S3 but sysjump makes
-			 * it back to default, disabled.
-			 */
-			power_signal_enable_interrupt(GPIO_AP_RST_L);
-
-			/* Disable idle task deep sleep when in S0 */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-		} else {
-			CPRINTS("SOC OFF");
-			init_power_state = POWER_G3;
-		}
-	}
-
-	/* Leave power off only if requested by reset flags */
-	if (!(reset_flags & EC_RESET_FLAG_AP_OFF) &&
-	    !(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("auto_power_on set due to reset_flag 0x%x",
-			system_get_reset_flags());
-		auto_power_on = 1;
-	}
-
-	if (battery_is_present() == BP_YES) {
-		/*
-		 * (crosbug.com/p/28289): Wait battery stable.
-		 * Some batteries use clock stretching feature, which requires
-		 * more time to be stable.
-		 */
-		battery_wait_for_stable();
-	}
-
-	return init_power_state;
-}
-
-/*****************************************************************************/
-
-/**
- * Power off the AP
- */
-static void power_off(void)
-{
-	/* Check PMIC POWER_GOOD */
-	if (is_pmic_pwron()) {
-		/* Do a graceful way to shutdown PMIC/AP first */
-		set_pmic_pwron(0);
-		usleep(PMIC_POWER_OFF_DELAY);
-
-		/*
-		 * Disable signal interrupts, as they are floating when
-		 * switchcap off.
-		 */
-		power_signal_disable_interrupt(GPIO_AP_RST_L);
-	}
-
-	/* Check the switchcap status */
-	if (is_system_powered()) {
-		/* Force to switch off all rails */
-		set_system_power(0);
-	}
-
-	lid_opened = 0;
-}
-
-/**
- * Check if the power is enough to boot the AP.
- */
-static int power_is_enough(void)
-{
-	timestamp_t poll_deadline;
-
-	/* If powered by adapter only, wait a while for PD negoiation. */
-	poll_deadline = get_time();
-	poll_deadline.val += CAN_BOOT_AP_CHECK_TIMEOUT;
-
-	/*
-	 * Wait for PD negotiation. If a system with drained battery, don't
-	 * waste the time and exit the loop.
-	 */
-	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
-		usleep(CAN_BOOT_AP_CHECK_WAIT);
-	}
-
-	return system_can_boot_ap() && !charge_want_shutdown();
-}
-
-/**
- * Power on the AP
- *
- * @return EC_SUCCESS or error
- */
-static int power_on(void)
-{
-	int ret;
-
-	ret = set_system_power(1);
-	if (ret != EC_SUCCESS)
-		return ret;
-
-	/* Enable signal interrupts */
-	power_signal_enable_interrupt(GPIO_AP_RST_L);
-
-	ret = set_pmic_pwron(1);
-	if (ret != EC_SUCCESS) {
-		CPRINTS("POWER_GOOD not seen in time");
-		return ret;
-	}
-
-	CPRINTS("POWER_GOOD seen");
-	return EC_SUCCESS;
-}
-
-/**
- * Check if there has been a power-on event
- *
- * This checks all power-on event signals and returns non-zero if any have been
- * triggered (with debounce taken into account).
- *
- * @return non-zero if there has been a power-on event, 0 if not.
- */
-static uint8_t check_for_power_on_event(void)
-{
-	if (power_request == POWER_REQ_ON) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_ON;
-	} else if (power_request == POWER_REQ_RESET) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/* power on requested at EC startup for recovery */
-	if (auto_power_on) {
-		auto_power_on = 0;
-		return POWER_ON_BY_AUTO_POWER_ON;
-	}
-
-	/* Check lid open */
-	if (lid_opened) {
-		lid_opened = 0;
-		return POWER_ON_BY_LID_OPEN;
-	}
-
-	/* check for power button press */
-	if (power_button_is_pressed())
-		return POWER_ON_BY_POWER_BUTTON_PRESSED;
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Check for some event triggering the shutdown.
- *
- * It can be either a long power button press or a shutdown triggered from the
- * AP and detected by reading POWER_GOOD.
- *
- * @return non-zero if a shutdown should happen, 0 if not
- */
-static uint8_t check_for_power_off_event(void)
-{
-	timestamp_t now;
-	int pressed = 0;
-
-	if (power_request == POWER_REQ_OFF) {
-		power_request = POWER_REQ_NONE;
-		return POWER_OFF_BY_POWER_REQ_OFF;
-	} else if (power_request == POWER_REQ_RESET) {
-		/*
-		 * The power_request flag will be cleared later
-		 * in check_for_power_on_event() in S5.
-		 */
-		return POWER_OFF_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/*
-	 * Check for power button press.
-	 */
-	if (power_button_is_pressed())
-		pressed = POWER_OFF_BY_POWER_BUTTON_PRESSED;
-
-	now = get_time();
-	if (pressed) {
-		if (!power_button_was_pressed) {
-			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
-			CPRINTS("power waiting for long press %u",
-				power_off_deadline.le.lo);
-			/* Ensure we will wake up to check the power key */
-			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
-		} else if (timestamp_expired(power_off_deadline, &now)) {
-			power_off_deadline.val = 0;
-			CPRINTS("power off after long press now=%u, %u",
-				now.le.lo, power_off_deadline.le.lo);
-			return POWER_OFF_BY_LONG_PRESS;
-		}
-	} else if (power_button_was_pressed) {
-		CPRINTS("power off cancel");
-		timer_cancel(TASK_ID_CHIPSET);
-	}
-
-	power_button_was_pressed = pressed;
-
-	/* POWER_GOOD released by AP : shutdown immediately */
-	if (!power_has_signals(IN_POWER_GOOD)) {
-		CPRINTS("POWER_GOOD is lost");
-		return POWER_OFF_BY_POWER_GOOD_LOST;
-	}
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Cancel the power button timer.
- *
- * The timer was previously created in the check_for_power_off_event(),
- * which waited for the power button long press. Should cancel the timer
- * during the power state transition; otherwise, EC will crash.
- */
-static inline void cancel_power_button_timer(void)
-{
-	if (power_button_was_pressed)
-		timer_cancel(TASK_ID_CHIPSET);
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Issue a request to initiate a power-off sequence */
-	power_request = POWER_REQ_OFF;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	int rv;
-
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Warm reset sequence:
-	 * 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
-	 *    to do a warm reset (requiring reprogramming PMIC registers
-	 *    to make PMIC_RESIN_L as a warm reset trigger).
-	 * 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
-	 *    EC monitors the signal to see any low pulse.
-	 *    2.1. If a low pulse found, done.
-	 *    2.2. If a low pulse not found (the above PMIC registers
-	 *         not programmed or programmed wrong), issue a request
-	 *         to initiate a cold reset power sequence.
-	 */
-
-	gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	usleep(PMIC_RESIN_PULSE_LENGTH);
-	gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-
-	rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
-					PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	/* Exception case: PMIC not work as expected, request a cold reset */
-	if (rv != EC_SUCCESS) {
-		CPRINTS("AP refuses to warm reset. Cold resetting.");
-		request_cold_reset();
-	}
-}
-
-/*
- * Flag to fake the suspend signal to 1 or 0, or -1 means not fake it.
- *
- * TODO(waihong): Remove this flag and debug command when the AP_SUSPEND
- * signal is working.
- */
-static int fake_suspend = -1;
-
-static int command_fake_suspend(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		ccprintf("fake_suspend: %s\n",
-			 fake_suspend == -1 ? "reset"
-					    : (fake_suspend ? "on" : "off"));
-		return EC_SUCCESS;
-	}
-
-	if (!strcasecmp(argv[1], "reset"))
-		fake_suspend = -1;
-	else if (parse_bool(argv[1], &v))
-		fake_suspend = v;
-	else
-		return EC_ERROR_PARAM1;
-
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend,
-			"on/off/reset",
-			"Fake the AP_SUSPEND signal");
-
-/* Get system sleep state through GPIOs */
-static inline int chipset_get_sleep_signal(void)
-{
-	if (fake_suspend == -1)
-		return (power_get_signals() & IN_SUSPEND) == IN_SUSPEND;
-	else
-		return fake_suspend;
-}
-
-static void suspend_hang_detected(void)
-{
-	CPRINTS("Warning: Detected sleep hang! Waking host up!");
-	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
-}
-
-static void power_reset_host_sleep_state(void)
-{
-	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	sleep_reset_tracking();
-	power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
-					      NULL);
-}
-
-static void handle_chipset_reset(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
-		CPRINTS("Chipset reset: exit s3");
-		power_reset_host_sleep_state();
-		task_wake(TASK_ID_CHIPSET);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
-
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
-{
-	CPRINTS("Handle sleep: %d", state);
-
-	if (state == HOST_SLEEP_EVENT_S3_SUSPEND) {
-		/*
-		 * Indicate to power state machine that a new host event for
-		 * S3 suspend has been received and so chipset suspend
-		 * notification needs to be sent to listeners.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
-		sleep_start_suspend(ctx, suspend_hang_detected);
-		power_signal_enable_interrupt(GPIO_AP_SUSPEND);
-
-	} else if (state == HOST_SLEEP_EVENT_S3_RESUME) {
-		/*
-		 * Wake up chipset task and indicate to power state machine that
-		 * listeners need to be notified of chipset resume.
-		 */
-		sleep_set_notify(SLEEP_NOTIFY_RESUME);
-		task_wake(TASK_ID_CHIPSET);
-		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
-		sleep_complete_resume(ctx);
-
-	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
-		power_signal_disable_interrupt(GPIO_AP_SUSPEND);
-	}
-}
-
-/**
- * Power handler for steady states
- *
- * @param state		Current power state
- * @return Updated power state
- */
-enum power_state power_handle_state(enum power_state state)
-{
-	static uint8_t boot_from_off, shutdown_from_on;
-
-	switch (state) {
-	case POWER_G3:
-		boot_from_off = check_for_power_on_event();
-		if (boot_from_off)
-			return POWER_G3S5;
-		break;
-
-	case POWER_G3S5:
-		return POWER_S5;
-
-	case POWER_S5:
-		if (!boot_from_off)
-			boot_from_off = check_for_power_on_event();
-
-		if (boot_from_off) {
-			CPRINTS("power on %d", boot_from_off);
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S5S3:
-		/*
-		 * Wait for power button release before actually boot AP.
-		 * It may be a long-hold power button with volume buttons
-		 * to trigger the recovery button. We don't want AP up
-		 * during the long-hold.
-		 */
-		power_button_wait_for_release(-1);
-
-		/* If no enough power, return back to S5. */
-		if (!power_is_enough()) {
-			boot_from_off = 0;
-			return POWER_S5;
-		}
-
-		/* Initialize components to ready state before AP is up. */
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		if (power_on() != EC_SUCCESS) {
-			power_off();
-			boot_from_off = 0;
-			return POWER_S5;
-		}
-		CPRINTS("AP running ...");
-
-		/* Call hooks now that AP is running */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		/*
-		 * Clearing the sleep failure detection tracking on the path
-		 * to S0 to handle any reset conditions.
-		 */
-		power_reset_host_sleep_state();
-		return POWER_S3;
-
-	case POWER_S3:
-		if (!shutdown_from_on)
-			shutdown_from_on = check_for_power_off_event();
-
-		if (shutdown_from_on) {
-			CPRINTS("power off %d", shutdown_from_on);
-			return POWER_S3S5;
-		}
-
-		/*
-		 * AP has woken up and it deasserts the suspend signal;
-		 * go to S0.
-		 *
-		 * In S0, it will wait for a host event and then trigger the
-		 * RESUME hook.
-		 */
-		if (!chipset_get_sleep_signal())
-			return POWER_S3S0;
-		break;
-
-	case POWER_S3S0:
-		cancel_power_button_timer();
-
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		/*
-		 * Notify the RESUME_INIT hooks, i.e. enabling SPI driver
-		 * to receive host commands/events.
-		 *
-		 * If boot from an off state, notify the RESUME hooks too;
-		 * otherwise (resume from S3), the normal RESUME hooks will
-		 * be notified later, after receive a host resume event.
-		 */
-		hook_notify(HOOK_CHIPSET_RESUME_INIT);
-		if (boot_from_off)
-			hook_notify(HOOK_CHIPSET_RESUME);
-#else
-		hook_notify(HOOK_CHIPSET_RESUME);
-#endif
-		sleep_resume_transition();
-
-		boot_from_off = 0;
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S0;
-
-	case POWER_S0:
-		shutdown_from_on = check_for_power_off_event();
-		if (shutdown_from_on) {
-			return POWER_S0S3;
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S3_SUSPEND &&
-				chipset_get_sleep_signal()) {
-			return POWER_S0S3;
-		}
-		/* When receive the host event, trigger the RESUME hook. */
-		sleep_notify_transition(SLEEP_NOTIFY_RESUME,
-					HOOK_CHIPSET_RESUME);
-		break;
-
-	case POWER_S0S3:
-		cancel_power_button_timer();
-
-		/*
-		 * Call SUSPEND hooks only if we haven't notified listeners of
-		 * S3 suspend.
-		 */
-		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
-					HOOK_CHIPSET_SUSPEND);
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-		/*
-		 * Pair with the HOOK_CHIPSET_RESUME_INIT, i.e. disabling SPI
-		 * driver, by notifying the SUSPEND_COMPLETE hooks.
-		 *
-		 * If shutdown from an on state, notify the SUSPEND hooks too;
-		 * otherwise (suspend from S0), the normal SUSPEND hooks have
-		 * been notified in the above sleep_notify_transition() call.
-		 */
-		if (shutdown_from_on)
-			hook_notify(HOOK_CHIPSET_SUSPEND);
-		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
-#else
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-#endif
-		sleep_suspend_transition();
-
-		enable_sleep(SLEEP_MASK_AP_RUN);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		cancel_power_button_timer();
-
-		/* Call hooks before we drop power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		power_off();
-		CPRINTS("power shutdown complete");
-
-		/* Call hooks after we drop power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		shutdown_from_on = 0;
-
-		/*
-		 * Wait forever for the release of the power button; otherwise,
-		 * this power button press will then trigger a power-on in S5.
-		 */
-		power_button_wait_for_release(-1);
-		power_button_was_pressed = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-/*****************************************************************************/
-/* Console debug command */
-
-static const char *power_req_name[POWER_REQ_COUNT] = {
-	"none",
-	"off",
-	"on",
-};
-
-/* Power states that we can report */
-enum power_state_t {
-	PSTATE_UNKNOWN,
-	PSTATE_OFF,
-	PSTATE_ON,
-	PSTATE_COUNT,
-};
-
-static const char * const state_name[] = {
-	"unknown",
-	"off",
-	"on",
-};
-
-static int command_power(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		enum power_state_t state;
-
-		state = PSTATE_UNKNOWN;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			state = PSTATE_OFF;
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			state = PSTATE_ON;
-		ccprintf("%s\n", state_name[state]);
-
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &v))
-		return EC_ERROR_PARAM1;
-
-	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
-	ccprintf("Requesting power %s\n", power_req_name[power_request]);
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
diff --git a/power/rk3288.c b/power/rk3288.c
deleted file mode 100644
index c647ab97b2..0000000000
--- a/power/rk3288.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Rockchip SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- *  When powered off:
- *  - Press pwron turns on the AP
- *  - Hold pwron turns on the AP, and then 9s later turns it off and leaves
- *    it off until pwron is released and pressed again
- *
- *  When powered on:
- *  - Holding pwron for 10.2s powers off the AP
- *  - Pressing and releasing pwron within that 10.2s is ignored
- *  - If POWER_GOOD is dropped by the pmic, then we cut off the pmic source
- *  - If SUSPEND_L goes low, enter suspend mode.
- *
- */
-
-#include "battery.h"
-#include "charge_state.h"
-#include "chipset.h"  /* This module implements chipset functions too */
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "keyboard_scan.h"
-#include "power.h"
-#include "power_button.h"
-#include "power_led.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* masks for power signals */
-#define IN_POWER_GOOD POWER_SIGNAL_MASK(RK_POWER_GOOD)
-#define IN_SUSPEND POWER_SIGNAL_MASK(RK_SUSPEND_ASSERTED)
-
-/* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8 * SECOND)
-
-/*
- * If the power key is pressed to turn on, then held for this long, we
- * power off.
- *
- * Normal case: User releases power button and chipset_task() goes
- *    into the inner loop, waiting for next event to occur (power button
- *    press or power good == 0).
- */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
-
-/*
- * The hold time for pulling down the PMIC_WARM_RESET_L pin so that
- * the AP can entery the recovery mode (flash SPI flash from USB).
- */
-#define PMIC_WARM_RESET_L_HOLD_TIME (4 * MSEC)
-
-/*
- * Startup time for the PMIC source regulator.
- */
-#define PMIC_SOURCE_STARTUP_TIME (50 * MSEC)
-
-/*
- * Time before PMIC can be reset.
- */
-#define PMIC_STARTUP_MS 300
-
-/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
-/* 1 if the power button was pressed last time we checked */
-static char power_button_was_pressed;
-
-/* 1 if lid-open event has been detected */
-static char lid_opened;
-
-/* time where we will power off, if power button still held down */
-static timestamp_t power_off_deadline;
-
-/* force AP power on (used for recovery keypress) */
-static int auto_power_on;
-
-enum power_request_t {
-	POWER_REQ_NONE,
-	POWER_REQ_OFF,
-	POWER_REQ_ON,
-
-	POWER_REQ_COUNT,
-};
-
-static enum power_request_t power_request;
-
-
-/* Forward declaration */
-static void chipset_turn_off_power_rails(void);
-
-
-/**
- * Set the PMIC WARM RESET signal.
- *
- * @param asserted	Resetting (=0) or idle (=1)
- */
-static void set_pmic_warm_reset(int asserted)
-{
-	/* Signal is active-low */
-	gpio_set_level(GPIO_PMIC_WARM_RESET_L, asserted ? 0 : 1);
-}
-
-
-/**
- * Set the PMIC PWRON signal.
- *
- * @param asserted	Assert (=1) or deassert (=0) the signal.
- */
-static void set_pmic_pwron(int asserted)
-{
-	/* Signal is active-high */
-	gpio_set_level(GPIO_PMIC_PWRON, asserted ? 1 : 0);
-}
-
-/**
- * Set the PMIC source to force shutdown the AP.
- *
- * @param asserted	Assert (=1) or deassert (=0) the signal.
- */
-static void set_pmic_source(int asserted)
-{
-	/* Signal is active-high */
-	gpio_set_level(GPIO_PMIC_SOURCE_PWREN, asserted ? 1 : 0);
-}
-
-/**
- * Check for some event triggering the shutdown.
- *
- * It can be either a long power button press or a shutdown triggered from the
- * AP and detected by reading POWER_GOOD.
- *
- * @return non-zero if a shutdown should happen, 0 if not
- */
-static int check_for_power_off_event(void)
-{
-	timestamp_t now;
-	int pressed = 0;
-	int ret = 0;
-
-	/*
-	 * Check for power button press.
-	 */
-	if (power_button_is_pressed()) {
-		pressed = 1;
-	} else if (power_request == POWER_REQ_OFF) {
-		power_request = POWER_REQ_NONE;
-		return 4;  /* return non-zero for shudown down */
-	}
-
-	now = get_time();
-	if (pressed) {
-		if (!power_button_was_pressed) {
-			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
-			CPRINTS("power waiting for long press %u",
-				power_off_deadline.le.lo);
-			/* Ensure we will wake up to check the power key */
-			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
-		} else if (timestamp_expired(power_off_deadline, &now)) {
-			power_off_deadline.val = 0;
-			CPRINTS("power off after long press now=%u, %u",
-				now.le.lo, power_off_deadline.le.lo);
-			return 2;
-		}
-	} else if (power_button_was_pressed) {
-		CPRINTS("power off cancel");
-		timer_cancel(TASK_ID_CHIPSET);
-	}
-
-	/* POWER_GOOD released by AP : shutdown immediately */
-	if (!power_has_signals(IN_POWER_GOOD)) {
-		if (power_button_was_pressed)
-			timer_cancel(TASK_ID_CHIPSET);
-		ret = 3;
-	}
-
-	power_button_was_pressed = pressed;
-
-	return ret;
-}
-
-static void rockchip_lid_event(void)
-{
-	/* Power task only cares about lid-open events */
-	if (!lid_is_open())
-		return;
-
-	lid_opened = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, rockchip_lid_event, HOOK_PRIO_DEFAULT);
-
-enum power_state power_chipset_init(void)
-{
-	int init_power_state;
-	uint32_t reset_flags = system_get_reset_flags();
-
-	/*
-	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
-	 * the AP could stay in strange state.
-	 */
-	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("not sysjump; forcing AP shutdown");
-		chipset_turn_off_power_rails();
-
-		/*
-		 * The warm reset triggers AP into the RK recovery mode (
-		 * flash SPI from USB).
-		 */
-		chipset_reset(CHIPSET_RESET_INIT);
-
-		init_power_state = POWER_G3;
-	} else {
-		/* In the SYSJUMP case, we check if the AP is on */
-		if (power_get_signals() & IN_POWER_GOOD)
-			init_power_state = POWER_S0;
-		else
-			init_power_state = POWER_G3;
-	}
-
-	/* Leave power off only if requested by reset flags */
-	if (!(reset_flags & EC_RESET_FLAG_AP_OFF) &&
-	    !(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("auto_power_on set due to reset_flag 0x%x",
-			system_get_reset_flags());
-		auto_power_on = 1;
-	}
-
-	/*
-	 * Some batteries use clock stretching feature, which requires
-	 * more time to be stable. See http://crosbug.com/p/28289
-	 */
-	battery_wait_for_stable();
-
-	return init_power_state;
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-static void chipset_turn_off_power_rails(void)
-{
-	/* Release the power on pin, if it was asserted */
-	set_pmic_pwron(0);
-	/* Close the pmic power source immediately */
-	set_pmic_source(0);
-
-	/* Keep AP and PMIC in reset the whole time */
-	set_pmic_warm_reset(1);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-	chipset_turn_off_power_rails();
-
-	/* clean-up internal variable */
-	power_request = POWER_REQ_NONE;
-}
-
-/*****************************************************************************/
-
-/**
- * Check if there has been a power-on event
- *
- * This checks all power-on event signals and returns non-zero if any have been
- * triggered (with debounce taken into account).
- *
- * @return non-zero if there has been a power-on event, 0 if not.
- */
-static int check_for_power_on_event(void)
-{
-	int ap_off_flag;
-
-	ap_off_flag = system_get_reset_flags() & EC_RESET_FLAG_AP_OFF;
-	system_clear_reset_flags(EC_RESET_FLAG_AP_OFF);
-	/* check if system is already ON */
-	if (power_get_signals() & IN_POWER_GOOD) {
-		if (ap_off_flag) {
-			CPRINTS(
-				"system is on, but "
-				"EC_RESET_FLAG_AP_OFF is on");
-			return 0;
-		} else {
-			CPRINTS(
-				"system is on, thus clear "
-				"auto_power_on");
-			/* no need to arrange another power on */
-			auto_power_on = 0;
-			return 1;
-		}
-	}
-
-	/* power on requested at EC startup for recovery */
-	if (auto_power_on) {
-		auto_power_on = 0;
-		return 2;
-	}
-
-	/* Check lid open */
-	if (lid_opened) {
-		lid_opened = 0;
-		return 3;
-	}
-
-	/* check for power button press */
-	if (power_button_is_pressed())
-		return 4;
-
-	if (power_request == POWER_REQ_ON) {
-		power_request = POWER_REQ_NONE;
-		return 5;
-	}
-
-	return 0;
-}
-
-/**
- * Power on the AP
- */
-static void power_on(void)
-{
-	int i;
-
-	set_pmic_source(1);
-	usleep(PMIC_SOURCE_STARTUP_TIME);
-
-	set_pmic_pwron(1);
-	/*
-	 * BUG Workaround(crosbug.com/p/31635): usleep hangs in task when using
-	 * big delays.
-	 */
-	for (i = 0; i < PMIC_STARTUP_MS; i++)
-		usleep(1 * MSEC);
-
-	set_pmic_warm_reset(0);
-}
-
-/**
- * Power off the AP
- */
-static void power_off(void)
-{
-	unsigned int power_off_timeout = 100; /* ms */
-
-	/* Call hooks before we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	/* switch off all rails */
-	chipset_turn_off_power_rails();
-	/* Change SUSPEND_L and EC_INT pin to high-Z to reduce power draw. */
-	gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT);
-	gpio_set_flags(GPIO_EC_INT_L, GPIO_INPUT);
-
-	/* Wait till we actually turn off to not mess up the state machine. */
-	while (power_get_signals() & IN_POWER_GOOD) {
-		msleep(1);
-		power_off_timeout--;
-		ASSERT(power_off_timeout);
-	}
-
-	lid_opened = 0;
-	enable_sleep(SLEEP_MASK_AP_RUN);
-	powerled_set_state(POWERLED_STATE_OFF);
-
-	CPRINTS("power shutdown complete");
-
-	/* Call hooks after we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
-			PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
-	set_pmic_warm_reset(1);
-	usleep(PMIC_WARM_RESET_L_HOLD_TIME);
-	set_pmic_warm_reset(0);
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	int value;
-	static int boot_from_g3;
-
-	switch (state) {
-	case POWER_G3:
-		boot_from_g3 = check_for_power_on_event();
-		if (boot_from_g3)
-			return POWER_G3S5;
-		break;
-
-	case POWER_G3S5:
-		return POWER_S5;
-
-	case POWER_S5:
-		if (boot_from_g3) {
-			value = boot_from_g3;
-			boot_from_g3 = 0;
-		} else {
-			value = check_for_power_on_event();
-		}
-
-		if (value) {
-			CPRINTS("power on %d", value);
-			return POWER_S5S3;
-		}
-		return state;
-
-	case POWER_S5S3:
-		hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-		power_on();
-
-		disable_sleep(SLEEP_MASK_AP_RUN);
-		powerled_set_state(POWERLED_STATE_ON);
-
-		if (power_wait_signals(IN_POWER_GOOD) == EC_SUCCESS) {
-			CPRINTS("POWER_GOOD seen");
-			if (power_button_wait_for_release(
-					DELAY_SHUTDOWN_ON_POWER_HOLD) ==
-					EC_SUCCESS) {
-				power_button_was_pressed = 0;
-				set_pmic_pwron(0);
-
-				/* setup misc gpio for S3/S0 functionality */
-				gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT
-					| GPIO_INT_BOTH | GPIO_PULL_DOWN);
-				gpio_set_flags(GPIO_EC_INT_L, GPIO_OUTPUT
-						| GPIO_OUT_HIGH);
-
-				/* Call hooks now that AP is running */
-				hook_notify(HOOK_CHIPSET_STARTUP);
-
-				return POWER_S3;
-			} else {
-				CPRINTS("long-press button, shutdown");
-				power_off();
-				/*
-				 * Since the AP may be up already, return S0S3
-				 * state to go through the suspend hook.
-				 */
-				return POWER_S0S3;
-			}
-		} else {
-			CPRINTS("POWER_GOOD not seen in time");
-		}
-
-		chipset_turn_off_power_rails();
-		return POWER_S5;
-
-	case POWER_S3:
-		if (!(power_get_signals() & IN_POWER_GOOD))
-			return POWER_S3S5;
-		else if (!(power_get_signals() & IN_SUSPEND))
-			return POWER_S3S0;
-		return state;
-
-	case POWER_S3S0:
-		powerled_set_state(POWERLED_STATE_ON);
-		hook_notify(HOOK_CHIPSET_RESUME);
-		return POWER_S0;
-
-	case POWER_S0:
-		value = check_for_power_off_event();
-		if (value) {
-			CPRINTS("power off %d", value);
-			power_off();
-			return POWER_S0S3;
-		} else if (power_get_signals() & IN_SUSPEND)
-			return POWER_S0S3;
-		return state;
-
-	case POWER_S0S3:
-		if (lid_is_open())
-			powerled_set_state(POWERLED_STATE_SUSPEND);
-		else
-			powerled_set_state(POWERLED_STATE_OFF);
-		/* Call hooks here since we don't know it prior to AP suspend */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		power_button_wait_for_release(-1);
-		power_button_was_pressed = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-static void powerbtn_rockchip_changed(void)
-{
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_rockchip_changed,
-		HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Console debug command */
-
-static const char *power_req_name[POWER_REQ_COUNT] = {
-	"none",
-	"off",
-	"on",
-};
-
-/* Power states that we can report */
-enum power_state_t {
-	PSTATE_UNKNOWN,
-	PSTATE_OFF,
-	PSTATE_SUSPEND,
-	PSTATE_ON,
-
-	PSTATE_COUNT,
-};
-
-static const char * const state_name[] = {
-	"unknown",
-	"off",
-	"suspend",
-	"on",
-};
-
-static int command_power(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		enum power_state_t state;
-
-		state = PSTATE_UNKNOWN;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			state = PSTATE_OFF;
-		if (chipset_in_state(CHIPSET_STATE_SUSPEND))
-			state = PSTATE_SUSPEND;
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			state = PSTATE_ON;
-		ccprintf("%s\n", state_name[state]);
-
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &v))
-		return EC_ERROR_PARAM1;
-
-	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
-	ccprintf("Requesting power %s\n", power_req_name[power_request]);
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
diff --git a/power/rk3399.c b/power/rk3399.c
deleted file mode 100644
index 9db25f0b28..0000000000
--- a/power/rk3399.c
+++ /dev/null
@@ -1,610 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* rk3399 chipset power control module for Chrome EC */
-
-/*
- * The description of each CONFIG_CHIPSET_POWER_SEQ_VERSION:
- *
- * Version 0: Initial/default revision for clamshell / convertible.
- * Version 1: Simplified power tree for tablet / detachable.
- */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_PP1250_S3   POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
-	#define IN_PGOOD_PP900_S0    POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
-#else
-	#define IN_PGOOD_PP5000      POWER_SIGNAL_MASK(PP5000_PWR_GOOD)
-	#define IN_PGOOD_SYS         POWER_SIGNAL_MASK(SYS_PWR_GOOD)
-#endif
-
-#define IN_PGOOD_AP            POWER_SIGNAL_MASK(AP_PWR_GOOD)
-#define IN_SUSPEND_DEASSERTED  POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
-
-/* Rails requires for S3 and S0 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_S3    (IN_PGOOD_PP1250_S3)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
-	/* This board can optionally wake-on-USB in S3 */
-	#define S3_USB_WAKE
-	/* This board has non-INT power signal pins */
-	#define POWER_SIGNAL_POLLING
-	/* This board supports CR50 deep sleep mode */
-	#define CR50_DEEP_SLEEP
-	/*
-	 * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the
-	 * signal every 5ms, up to 200 times (~ 1 second timeout).
-	 */
-	#define PGOOD_S0_POLL_TIMEOUT  (5 * MSEC)
-	#define PGOOD_S0_POLL_TRIES    200
-#else
-	#define IN_PGOOD_S3    (IN_PGOOD_PP5000)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS)
-#endif
-
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0              (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
-
-/* Long power key press to force shutdown in S0 */
-#define FORCED_SHUTDOWN_DELAY  (8 * SECOND)
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Data structure for a GPIO operation for power sequencing */
-struct power_seq_op {
-	/* enum gpio_signal in 8 bits */
-	uint8_t signal;
-	uint8_t level;
-	/* Number of milliseconds to delay after setting signal to level */
-	uint8_t delay;
-};
-BUILD_ASSERT(GPIO_COUNT < 256);
-
-/*
- * This is the power sequence for POWER_S5S3.
- * The entries in the table are handled sequentially from the top
- * to the bottom.
- */
-
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-static const struct power_seq_op s5s3_power_seq[] = {
-	{ GPIO_PP900_S3_EN, 1, 2 },
-	{ GPIO_PP3300_S3_EN, 1, 2 },
-	{ GPIO_PP1800_S3_EN, 1, 2 },
-	{ GPIO_PP1250_S3_EN, 1, 2 },
-};
-#else
-static const struct power_seq_op s5s3_power_seq[] = {
-	{ GPIO_PPVAR_LOGIC_EN, 1, 0 },
-	{ GPIO_PP900_AP_EN, 1, 0 },
-	{ GPIO_PP900_PCIE_EN, 1, 2 },
-	{ GPIO_PP900_PMU_EN, 1, 0 },
-	{ GPIO_PP900_PLL_EN, 1, 0 },
-	{ GPIO_PP900_USB_EN, 1, 2 },
-	{ GPIO_SYS_RST_L, 0, 0 },
-	{ GPIO_PP1800_PMU_EN_L, 0, 2 },
-	{ GPIO_LPDDR_PWR_EN, 1, 2 },
-	{ GPIO_PP1800_USB_EN_L, 0, 2 },
-	{ GPIO_PP3300_USB_EN_L, 0, 0 },
-	{ GPIO_PP5000_EN, 1, 0 },
-	{ GPIO_PP3300_TRACKPAD_EN_L, 0, 1 },
-	{ GPIO_PP1800_LID_EN_L, 0, 0 },
-	{ GPIO_PP1800_SIXAXIS_EN_L, 0, 2 },
-	{ GPIO_PP1800_SENSOR_EN_L, 0, 0 },
-};
-#endif
-
-/* The power sequence for POWER_S3S0 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-static const struct power_seq_op s3s0_power_seq[] = {
-	{ GPIO_AP_CORE_EN, 1, 2 },
-	{ GPIO_PP1800_S0_EN, 1, 0 },
-};
-#else
-static const struct power_seq_op s3s0_power_seq[] = {
-	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },
-	{ GPIO_PP900_DDRPLL_EN, 1, 2 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 },
-	{ GPIO_AP_CORE_EN, 1, 2 },
-	{ GPIO_PP1800_S0_EN_L, 0, 2 },
-	{ GPIO_PP3300_S0_EN_L, 0, 0 },
-};
-#endif
-
-#ifdef S3_USB_WAKE
-/* Sigs that may already be on in S3, if we need to wake-on-USB */
-static const struct power_seq_op s3s0_usb_wake_power_seq[] = {
-	{ GPIO_PP900_S0_EN, 1, 2 },
-	{ GPIO_PP1800_USB_EN, 1, 2 },
-	{ GPIO_PP3300_S0_EN, 1, 2 },
-};
-#endif
-
-/* The power sequence for POWER_S0S3 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-static const struct power_seq_op s0s3_power_seq[] = {
-	{ GPIO_AP_CORE_EN, 0, 20 },
-};
-#else
-static const struct power_seq_op s0s3_power_seq[] = {
-	{ GPIO_PP3300_S0_EN_L, 1, 20 },
-	{ GPIO_PP1800_S0_EN_L, 1, 1 },
-	{ GPIO_AP_CORE_EN, 0, 20 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
-	{ GPIO_PP900_DDRPLL_EN, 0, 1 },
-	{ GPIO_PPVAR_CLOGIC_EN, 0, 0 },
-};
-#endif
-
-#ifdef S3_USB_WAKE
-/* Sigs that need to be left on in S3, if we need to wake-on-USB */
-static const struct power_seq_op s0s3_usb_wake_power_seq[] = {
-	{ GPIO_PP3300_S0_EN, 0, 20 },
-	{ GPIO_PP1800_S0_EN, 0, 1 },
-	{ GPIO_PP1800_USB_EN, 0, 1 },
-	{ GPIO_PP900_S0_EN, 0, 0 },
-};
-#endif
-
-/* The power sequence for POWER_S3S5 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_SYS_RST_L, 0, 0 },
-	{ GPIO_PP1250_S3_EN, 0, 2 },
-	{ GPIO_PP1800_S3_EN, 0, 2 },
-	{ GPIO_PP3300_S3_EN, 0, 2 },
-	{ GPIO_PP900_S3_EN, 0, 0 },
-};
-#else
-static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_PP1800_SENSOR_EN_L, 1, 0},
-	{ GPIO_PP1800_SIXAXIS_EN_L, 1, 0},
-	{ GPIO_PP1800_LID_EN_L, 1, 0 },
-	{ GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
-	{ GPIO_PP5000_EN, 0, 0 },
-	{ GPIO_PP3300_USB_EN_L, 1, 20 },
-	{ GPIO_PP1800_USB_EN_L, 1, 10 },
-	{ GPIO_LPDDR_PWR_EN, 0, 20 },
-	{ GPIO_PP1800_PMU_EN_L, 1, 2 },
-	{ GPIO_PP900_PLL_EN, 0, 0 },
-	{ GPIO_PP900_PMU_EN, 0, 0 },
-	{ GPIO_PP900_USB_EN, 0, 6 },
-	{ GPIO_PP900_PCIE_EN, 0, 0 },
-	{ GPIO_PP900_AP_EN, 0, 0 },
-	{ GPIO_PPVAR_LOGIC_EN, 0, 0 },
-};
-#endif
-
-static int forcing_shutdown;
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	forcing_shutdown = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-#define SYS_RST_HOLD_US (1 * MSEC)
-void chipset_reset(enum chipset_reset_reason reason)
-{
-#ifdef CONFIG_CMD_RTC
-	/* Print out the RTC to help correlate resets in logs. */
-	print_system_rtc(CC_CHIPSET);
-#endif
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Pulse SYS_RST */
-	gpio_set_level(GPIO_SYS_RST_L, 0);
-	if (in_interrupt_context())
-		udelay(SYS_RST_HOLD_US);
-	else
-		usleep(SYS_RST_HOLD_US);
-	gpio_set_level(GPIO_SYS_RST_L, 1);
-}
-
-enum power_state power_chipset_init(void)
-{
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			disable_sleep(SLEEP_MASK_AP_RUN);
-			CPRINTS("already in S0");
-			return POWER_S0;
-		}
-	} else if (!(system_get_reset_flags() & EC_RESET_FLAG_AP_OFF))
-		/* Auto-power on */
-		chipset_exit_hard_off();
-
-	return POWER_G3;
-}
-
-static void force_shutdown(void)
-{
-	forcing_shutdown = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_DEFERRED(force_shutdown);
-
-/*
- * Debounce PGOOD_AP if we lose it suddenly during S0, since output voltage
- * transitions may cause spurious pulses.
- */
-#define PGOOD_AP_DEBOUNCE_TIMEOUT (100 * MSEC)
-
-/*
- * The AP informs the EC of its S0 / S3 state through IN_SUSPEND_DEASSERTED /
- * AP_EC_S3_S0_L. Latency between deassertion and power rails coming up must
- * be minimized, so check for deassertion at various stages of our suspend
- * power sequencing, and immediately transition out of suspend if necessary.
- */
-#define SLEEP_INTERVAL_MS 5
-#define MSLEEP_CHECK_ABORTED_SUSPEND(msec) \
-	do { \
-		int sleep_remain = msec; \
-		do { \
-			msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS)); \
-			sleep_remain -= SLEEP_INTERVAL_MS; \
-			if (!forcing_shutdown && \
-			    power_get_signals() & IN_SUSPEND_DEASSERTED)  { \
-				CPRINTS("suspend aborted"); \
-				return POWER_S3S0; \
-			} \
-		} while (sleep_remain > 0); \
-	} while (0)
-BUILD_ASSERT(POWER_S3S0 != 0);
-
-/**
- * Step through the power sequence table and do corresponding GPIO operations.
- *
- * @param	power_seq_ops	The pointer to the power sequence table.
- * @param	op_count	The number of entries of power_seq_ops.
- * @return	non-zero if suspend aborted during POWER_S0S3, 0 otherwise.
- */
-static int power_seq_run(const struct power_seq_op *power_seq_ops, int op_count)
-{
-	int i;
-
-	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
-		if (!power_seq_ops[i].delay)
-			continue;
-		if ((power_seq_ops == s0s3_power_seq)
-#ifdef S3_USB_WAKE
-		    || (power_seq_ops == s0s3_usb_wake_power_seq)
-#endif
-		   )
-			MSLEEP_CHECK_ABORTED_SUSPEND(power_seq_ops[i].delay);
-		else
-			msleep(power_seq_ops[i].delay);
-	}
-	return 0;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-#ifndef CR50_DEEP_SLEEP
-	static int sys_reset_asserted;
-#endif
-#ifdef S3_USB_WAKE
-	static int usb_wake_enabled;
-#endif
-	int tries = 0;
-
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-		if (forcing_shutdown)
-			return POWER_S5G3;
-		else
-			return POWER_S5S3;
-		break;
-
-	case POWER_S3:
-		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown)
-			return POWER_S3S5;
-		else if (power_get_signals() & IN_SUSPEND_DEASSERTED)
-			return POWER_S3S0;
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
-		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
-			return POWER_S0S3;
-
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 1
-		/*
-		 * Wait up to PGOOD_AP_DEBOUNCE_TIMEOUT for IN_PGOOD_AP to
-		 * come back before transitioning back to S3. PGOOD_SYS can
-		 * also glitch, with a glitch duration < 1ms, so debounce
-		 * it here as well.
-		 */
-		if (power_wait_signals_timeout(IN_PGOOD_AP | IN_PGOOD_SYS,
-					       PGOOD_AP_DEBOUNCE_TIMEOUT)
-					       == EC_ERROR_TIMEOUT)
-			return POWER_S0S3;
-
-		/*
-		 * power_wait_signals_timeout() can block and consume task
-		 * wake events, so re-verify the state of the world.
-		 */
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
-		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
-			return POWER_S0S3;
-#endif
-
-		break;
-
-	case POWER_G3S5:
-		forcing_shutdown = 0;
-
-		/*
-		 * Allow time for charger to be initialized, in case we're
-		 * trying to boot the AP with no battery.
-		 */
-		while (charge_prevent_power_on(0) &&
-		       tries++ < CHARGER_INITIALIZED_TRIES) {
-			msleep(CHARGER_INITIALIZED_DELAY_MS);
-		}
-
-		/* Return to G3 if battery level is too low. */
-		if (charge_want_shutdown() ||
-		    tries > CHARGER_INITIALIZED_TRIES) {
-			CPRINTS("power-up inhibited");
-			chipset_force_shutdown(
-				CHIPSET_SHUTDOWN_BATTERY_INHIBIT);
-			return POWER_G3;
-		}
-
-		/* Power up to next state */
-		return POWER_S5;
-
-	case POWER_S5S3:
-		power_seq_run(s5s3_power_seq, ARRAY_SIZE(s5s3_power_seq));
-
-#ifndef CR50_DEEP_SLEEP
-		/*
-		 * Assert SYS_RST now, to be released in S3S0, to avoid
-		 * resetting the TPM soon after power-on.
-		 */
-		sys_reset_asserted = 1;
-#endif
-
-		if (power_wait_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S3S5;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		/* Power up to next state */
-		return POWER_S3;
-
-	case POWER_S3S0:
-#ifdef S3_USB_WAKE
-		/* Bring up S3 USB wake rails, if they are down */
-		if (!usb_wake_enabled)
-			power_seq_run(s3s0_usb_wake_power_seq,
-				      ARRAY_SIZE(s3s0_usb_wake_power_seq));
-		usb_wake_enabled = 0;
-#endif
-		power_seq_run(s3s0_power_seq, ARRAY_SIZE(s3s0_power_seq));
-
-#ifndef CR50_DEEP_SLEEP
-		/* Release SYS_RST if we came from S5 */
-		if (sys_reset_asserted) {
-#endif
-			msleep(10);
-			gpio_set_level(GPIO_SYS_RST_L, 1);
-
-#ifndef CR50_DEEP_SLEEP
-			sys_reset_asserted = 0;
-		}
-#endif
-
-#ifdef POWER_SIGNAL_POLLING
-		/*
-		 * Poll power signals every PGOOD_S0_POLL_TIMEOUT us, since
-		 * AP_PWR_GOOD assertion doesn't trigger a power signal
-		 * interrupt.
-		 */
-		while (power_wait_signals_timeout(IN_PGOOD_S0,
-		       PGOOD_S0_POLL_TIMEOUT) == EC_ERROR_TIMEOUT &&
-		       ++tries < PGOOD_S0_POLL_TRIES)
-			;
-
-		if (tries >= PGOOD_S0_POLL_TRIES) {
-			CPRINTS("power timeout on input; "
-				"wanted 0x%04x, got 0x%04x",
-				IN_PGOOD_S0, power_get_signals() & IN_PGOOD_S0);
-#else
-		if (power_wait_signals(IN_PGOOD_S0)) {
-#endif /* POWER_SIGNAL_POLLING */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_S0S3;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/* Power up to next state */
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		MSLEEP_CHECK_ABORTED_SUSPEND(20);
-
-		if (power_seq_run(s0s3_power_seq, ARRAY_SIZE(s0s3_power_seq)))
-			return POWER_S3S0;
-
-#ifdef S3_USB_WAKE
-		/* Leave up rails needed for S3 USB wake, if requested */
-		usb_wake_enabled = (power_get_host_sleep_state() ==
-				    HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND);
-		if (!usb_wake_enabled &&
-		    power_seq_run(s0s3_usb_wake_power_seq,
-				  ARRAY_SIZE(s0s3_usb_wake_power_seq)))
-			return POWER_S3S0;
-#endif
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * In case the power button is held awaiting power-off timeout,
-		 * power off immediately now that we're entering S3.
-		 */
-		if (power_button_is_pressed()) {
-			forcing_shutdown = 1;
-			hook_call_deferred(&force_shutdown_data, -1);
-		}
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-#ifdef S3_USB_WAKE
-		/* Make sure all S3 rails are off */
-		if (usb_wake_enabled) {
-			power_seq_run(s0s3_usb_wake_power_seq,
-				      ARRAY_SIZE(s0s3_usb_wake_power_seq));
-			usb_wake_enabled = 0;
-		}
-#endif
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		power_seq_run(s3s5_power_seq, ARRAY_SIZE(s3s5_power_seq));
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-static void power_button_changed(void)
-{
-	static uint8_t tablet_boot_on_button_release;
-
-	if (power_button_is_pressed()) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 1
-			/* Power up from off */
-			chipset_exit_hard_off();
-#else
-			tablet_boot_on_button_release = 1;
-#endif
-		}
-		/* Delayed power down from S0/S3, cancel on PB release */
-		hook_call_deferred(&force_shutdown_data,
-				   FORCED_SHUTDOWN_DELAY);
-	} else {
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-		if (tablet_boot_on_button_release) {
-			/* Power up from off */
-			chipset_exit_hard_off();
-			tablet_boot_on_button_release = 0;
-		}
-#endif
-		/* Power button released, cancel deferred shutdown */
-		hook_call_deferred(&force_shutdown_data, -1);
-	}
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_LID_SWITCH
-static void lid_changed(void)
-{
-	/* Power-up from off on lid open */
-	if (lid_is_open() && chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		chipset_exit_hard_off();
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, lid_changed, HOOK_PRIO_DEFAULT);
-#endif
-
-#ifdef POWER_SIGNAL_POLLING
-/*
- * Polling for non-INT power signal pins.
- * Call power_signal_interrupt() when the GPIO status of those pins changes.
- */
-static void power_signal_changed(void)
-{
-	static uint8_t in_signals; /* Current power signal status */
-	uint8_t inew = 0;
-	const struct power_signal_info *s = power_signal_list;
-	int i;
-
-	BUILD_ASSERT(POWER_SIGNAL_COUNT <= 8);
-
-	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
-		/* Skip if this is an INT pin. */
-		if (s->gpio < GPIO_IH_COUNT)
-			continue;
-
-		if (power_signal_is_asserted(s))
-			inew |= 1 << i;
-	}
-
-	if (inew != in_signals) {
-		/*
-		 * Pass a fake power gpio_signal to power_signal_interrupt().
-		 * Note that here we make power_signal_interrupt() reentrant.
-		 */
-		power_signal_interrupt(POWER_SIGNAL_COUNT);
-		in_signals = inew;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, power_signal_changed, HOOK_PRIO_DEFAULT);
-#endif
diff --git a/power/sdm845.c b/power/sdm845.c
deleted file mode 100644
index a8cc70b8ea..0000000000
--- a/power/sdm845.c
+++ /dev/null
@@ -1,882 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * SDM845 SoC power sequencing module for Chrome EC
- *
- * This implements the following features:
- *
- * - Cold reset powers on the AP
- *
- *  When powered off:
- *  - Press power button turns on the AP
- *  - Hold power button turns on the AP, and then 8s later turns it off and
- *    leaves it off until pwron is released and pressed again
- *  - Lid open turns on the AP
- *
- *  When powered on:
- *  - Holding power button for 8s powers off the AP
- *  - Pressing and releasing pwron within that 8s is ignored
- *  - If POWER_GOOD is dropped by the AP, then we power the AP off
- */
-
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "task.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SDM845_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED)
-
-
-/* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
-
-/*
- * If the power button is pressed to turn on, then held for this long, we
- * power off.
- *
- * Normal case: User releases power button and chipset_task() goes
- *    into the inner loop, waiting for next event to occur (power button
- *    press or POWER_GOOD == 0).
- */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
-
-/*
- * After trigger PMIC power sequence, how long it triggers AP to turn on
- * or off. Observed that the worst case is ~150ms. Pick a safe vale.
- */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
-
-/*
- * After force off the switch cap, how long the PMIC/AP totally off.
- * Observed that the worst case is 2s. Pick a safe vale.
- */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
-
-/* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
-
-/* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
-
-/* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(500 * MSEC)
-
-/* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(100 * MSEC)
-
-/* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(50 * MSEC)
-
-/* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(5 * MSEC)
-
-/* Delay between power-on the system and power-on the PMIC */
-#define SYSTEM_POWER_ON_DELAY		(10 * MSEC)
-
-/* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
-/* 1 if the power button was pressed last time we checked */
-static char power_button_was_pressed;
-
-/* 1 if lid-open event has been detected */
-static char lid_opened;
-
-/* 1 if AP_RST_L and PS_HOLD is overdriven by EC */
-static char ap_rst_overdriven;
-
-/* Time where we will power off, if power button still held down */
-static timestamp_t power_off_deadline;
-
-/* Force AP power on (used for recovery keypress) */
-static int auto_power_on;
-
-enum power_request_t {
-	POWER_REQ_NONE,
-	POWER_REQ_OFF,
-	POWER_REQ_ON,
-	POWER_REQ_RESET,
-
-	POWER_REQ_COUNT,
-};
-
-static enum power_request_t power_request;
-
-/**
- * Return values for check_for_power_off_event().
- */
-enum power_off_event_t {
-	POWER_OFF_CANCEL,
-	POWER_OFF_BY_POWER_BUTTON_PRESSED,
-	POWER_OFF_BY_LONG_PRESS,
-	POWER_OFF_BY_POWER_GOOD_LOST,
-	POWER_OFF_BY_POWER_REQ_OFF,
-	POWER_OFF_BY_POWER_REQ_RESET,
-
-	POWER_OFF_EVENT_COUNT,
-};
-
-/**
- * Return values for check_for_power_on_event().
- */
-enum power_on_event_t {
-	POWER_ON_CANCEL,
-	POWER_ON_BY_IN_POWER_GOOD,
-	POWER_ON_BY_AUTO_POWER_ON,
-	POWER_ON_BY_LID_OPEN,
-	POWER_ON_BY_POWER_BUTTON_PRESSED,
-	POWER_ON_BY_POWER_REQ_ON,
-	POWER_ON_BY_POWER_REQ_RESET,
-
-	POWER_ON_EVENT_COUNT,
-};
-
-/* Issue a request to initiate a reset sequence */
-static void request_cold_reset(void)
-{
-	power_request = POWER_REQ_RESET;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-/* AP-requested reset GPIO interrupt handlers */
-static void chipset_reset_request_handler(void)
-{
-	CPRINTS("AP wants reset");
-	chipset_reset(CHIPSET_RESET_AP_REQ);
-}
-DECLARE_DEFERRED(chipset_reset_request_handler);
-
-void chipset_reset_request_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&chipset_reset_request_handler_data, 0);
-}
-
-void chipset_warm_reset_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * The warm_reset signal is pulled-up by a rail from PMIC. If the
-	 * warm_reset drops, it means:
-	 *  * Servo or Cr50 holds the signal, or
-	 *  * its pull-up rail POWER_GOOD drops.
-	 */
-	if (!gpio_get_level(GPIO_WARM_RESET_L)) {
-		if (gpio_get_level(GPIO_POWER_GOOD)) {
-			/*
-			 * Servo or Cr50 holds the WARM_RESET_L signal.
-			 *
-			 * Overdrive AP_RST_L to hold AP. Overdrive PS_HOLD to
-			 * emulate AP being up to trick the PMIC into thinking
-			 * there’s nothing weird going on.
-			 */
-			ap_rst_overdriven = 1;
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
-		} else {
-			/*
-			 * The pull-up rail POWER_GOOD drops.
-			 *
-			 * High-Z both AP_RST_L and PS_HOLD to restore their
-			 * states.
-			 */
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
-			ap_rst_overdriven = 0;
-		}
-	} else {
-		if (ap_rst_overdriven) {
-			/*
-			 * Servo or Cr50 releases the WARM_RESET_L signal.
-			 *
-			 * Cold reset the PMIC, doing S0->S5->S0 transition,
-			 * by issuing a request to initiate a reset sequence,
-			 * to recover the system. The transition to S5 makes
-			 * POWER_GOOD drop that triggers an interrupt to
-			 * high-Z both AP_RST_L and PS_HOLD.
-			 */
-			request_cold_reset();
-		}
-		/* If not overdriven, just a normal power-up, do nothing. */
-	}
-
-	power_signal_interrupt(signal);
-}
-
-static void sdm845_lid_event(void)
-{
-	/* Power task only cares about lid-open events */
-	if (!lid_is_open())
-		return;
-
-	lid_opened = 1;
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, sdm845_lid_event, HOOK_PRIO_DEFAULT);
-
-static void powerbtn_sdm845_changed(void)
-{
-	task_wake(TASK_ID_CHIPSET);
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_sdm845_changed,
-	     HOOK_PRIO_DEFAULT);
-
-/**
- * Wait the switchcap GPIO0 PVC_PG signal asserted.
- *
- * When the output voltage is over the threshold PVC_PG_ADJ,
- * the PVC_PG is asserted.
- *
- * PVG_PG_ADJ is configured to 3.0V.
- * GPIO0 is configured as PVC_PG.
- *
- * @param enable	1 to wait the PMIC/AP on.
-			0 to wait the PMIC/AP off.
- */
-static void wait_switchcap_power_good(int enable)
-{
-	timestamp_t poll_deadline;
-
-	poll_deadline = get_time();
-	poll_deadline.val += SWITCHCAP_PG_CHECK_TIMEOUT;
-	while (enable != gpio_get_level(GPIO_DA9313_GPIO0) &&
-	       get_time().val < poll_deadline.val) {
-		usleep(SWITCHCAP_PG_CHECK_WAIT);
-	}
-
-	/*
-	 * Check the timeout case. Just show a message. More check later
-	 * will switch the power state.
-	 */
-	if (enable != gpio_get_level(GPIO_DA9313_GPIO0)) {
-		if (enable)
-			CPRINTS("SWITCHCAP NO POWER GOOD!");
-		else
-			CPRINTS("SWITCHCAP STILL POWER GOOD!");
-	}
-
-}
-
-/**
- * Get the state of the system power signals.
- *
- * @return 1 if the system is powered, 0 if not
- */
-static int is_system_powered(void)
-{
-	return gpio_get_level(GPIO_SWITCHCAP_ON_L);
-}
-
-/**
- * Get the PMIC/AP power signal.
- *
- * We treat the PMIC chips and the AP as a whole here. Don't deal with
- * the individual chip.
- *
- * @return 1 if the PMIC/AP is powered, 0 if not
- */
-static int is_pmic_pwron(void)
-{
-	/* Use POWER_GOOD to indicate PMIC/AP is on/off */
-	return gpio_get_level(GPIO_POWER_GOOD);
-}
-
-/**
- * Wait the PMIC/AP power-on state.
- *
- * @param enable	1 to wait the PMIC/AP on.
-			0 to wait the PMIC/AP off.
- * @param timeout	Number of microsecond of timeout.
- */
-static void wait_pmic_pwron(int enable, unsigned int timeout)
-{
-	timestamp_t poll_deadline;
-
-	/* Check the AP power status */
-	if (enable == is_pmic_pwron())
-		return;
-
-	poll_deadline = get_time();
-	poll_deadline.val += timeout;
-	while (enable != is_pmic_pwron() &&
-	       get_time().val < poll_deadline.val) {
-		usleep(PMIC_POWER_AP_WAIT);
-	}
-
-	/* Check the timeout case */
-	if (enable != is_pmic_pwron()) {
-		if (enable)
-			CPRINTS("AP POWER NOT READY!");
-		else
-			CPRINTS("AP POWER STILL UP!");
-	}
-}
-
-/**
- * Set the state of the system power signals.
- *
- * The system power signals are the enable pins of SwitchCap and VBOB.
- * They control the power of the set of PMIC chips and the AP.
- *
- * @param enable	1 to enable or 0 to disable
- */
-static void set_system_power(int enable)
-{
-	CPRINTS("%s(%d)", __func__, enable);
-	gpio_set_level(GPIO_SWITCHCAP_ON_L, enable);
-	wait_switchcap_power_good(enable);
-	gpio_set_level(GPIO_VBOB_EN, enable);
-	if (enable) {
-		usleep(SYSTEM_POWER_ON_DELAY);
-	} else {
-		/* Ensure POWER_GOOD drop to low if it is a forced shutdown */
-		wait_pmic_pwron(0, FORCE_OFF_RESPONSE_TIMEOUT);
-	}
-}
-
-/**
- * Set the PMIC/AP power-on state.
- *
- * It triggers the PMIC/AP power-on and power-off sequence.
- *
- * @param enable	1 to power the PMIC/AP on.
-			0 to power the PMIC/AP off.
- */
-static void set_pmic_pwron(int enable)
-{
-	CPRINTS("%s(%d)", __func__, enable);
-
-	/* Check the PMIC/AP power state */
-	if (enable == is_pmic_pwron())
-		return;
-
-	/*
-	 * Power-on sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL, which is a power-on trigger
-	 * 2. PM845 supplies power to POWER_GOOD
-	 * 3. Release PMIC_KPD_PWR_ODL
-	 *
-	 * Power-off sequence:
-	 * 1. Hold down PMIC_KPD_PWR_ODL and PMIC_RESIN_L, which is a power-off
-	 *    trigger (requiring reprogramming PMIC registers to make
-	 *    PMIC_KPD_PWR_ODL + PMIC_RESIN_L as a shutdown trigger)
-	 * 2. PM845 stops supplying power to POWER_GOOD (requiring
-	 *    reprogramming PMIC to set the stage-1 and stage-2 reset timers to
-	 *    0 such that the pull down happens just after the deboucing time
-	 *    of the trigger, like 2ms)
-	 * 3. Release PMIC_KPD_PWR_ODL and PMIC_RESIN_L
-	 *
-	 * If the above PMIC registers not programmed or programmed wrong, it
-	 * falls back to the next functions, which cuts off the system power.
-	 */
-
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 0);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	wait_pmic_pwron(enable, PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	gpio_set_level(GPIO_PMIC_KPD_PWR_ODL, 1);
-	if (!enable)
-		gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-}
-
-enum power_state power_chipset_init(void)
-{
-	int init_power_state;
-	uint32_t reset_flags = system_get_reset_flags();
-
-	/* Enable interrupts */
-	gpio_enable_interrupt(GPIO_AP_RST_REQ);
-	gpio_enable_interrupt(GPIO_WARM_RESET_L);
-	gpio_enable_interrupt(GPIO_POWER_GOOD);
-
-	/*
-	 * Force the AP shutdown unless we are doing SYSJUMP. Otherwise,
-	 * the AP could stay in strange state.
-	 */
-	if (!(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("not sysjump; forcing system shutdown");
-		set_system_power(0);
-		init_power_state = POWER_G3;
-	} else {
-		/* In the SYSJUMP case, we check if the AP is on */
-		if (power_get_signals() & IN_POWER_GOOD) {
-			CPRINTS("SOC ON");
-			init_power_state = POWER_S0;
-			/* Disable idle task deep sleep when in S0 */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-		} else {
-			CPRINTS("SOC OFF");
-			init_power_state = POWER_G3;
-		}
-	}
-
-	/* Leave power off only if requested by reset flags */
-	if (!(reset_flags & EC_RESET_FLAG_AP_OFF) &&
-	    !(reset_flags & EC_RESET_FLAG_SYSJUMP)) {
-		CPRINTS("auto_power_on set due to reset_flag 0x%x",
-			system_get_reset_flags());
-		auto_power_on = 1;
-	}
-
-	if (battery_is_present() == BP_YES) {
-		/*
-		 * (crosbug.com/p/28289): Wait battery stable.
-		 * Some batteries use clock stretching feature, which requires
-		 * more time to be stable.
-		 */
-		battery_wait_for_stable();
-	}
-
-	return init_power_state;
-}
-
-/*****************************************************************************/
-
-/**
- * Power off the AP
- */
-static void power_off(void)
-{
-	/* Check the power off status */
-	if (!is_system_powered())
-		return;
-
-	/* Call hooks before we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-	/* Do a graceful way to shutdown PMIC/AP first */
-	set_pmic_pwron(0);
-
-	/* Disable signal interrupts, as they are floating when switchcap off */
-	power_signal_disable_interrupt(GPIO_AP_RST_L);
-	power_signal_disable_interrupt(GPIO_PMIC_FAULT_L);
-
-	/* Force to switch off all rails */
-	set_system_power(0);
-
-	/* Turn off the 3.3V and 5V rails. */
-	gpio_set_level(GPIO_EN_PP3300_A, 0);
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 0);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-
-	lid_opened = 0;
-	enable_sleep(SLEEP_MASK_AP_RUN);
-	CPRINTS("power shutdown complete");
-
-	/* Call hooks after we drop power rails */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-}
-
-/**
- * Check if the power is enough to boot the AP.
- */
-static int power_is_enough(void)
-{
-	timestamp_t poll_deadline;
-
-	/* If powered by adapter only, wait a while for PD negoiation. */
-	poll_deadline = get_time();
-	poll_deadline.val += CAN_BOOT_AP_CHECK_TIMEOUT;
-
-	/*
-	 * Wait for PD negotiation. If a system with drained battery, don't
-	 * waste the time and exit the loop.
-	 */
-	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
-		usleep(CAN_BOOT_AP_CHECK_WAIT);
-	}
-
-	return system_can_boot_ap() && !charge_want_shutdown();
-}
-
-/**
- * Power on the AP
- */
-static void power_on(void)
-{
-	/*
-	 * If no enough power, return and the state machine will transition
-	 * back to S5.
-	 */
-	if (!power_is_enough())
-		return;
-
-	/*
-	 * When power_on() is called, we are at S5S3. Initialize components
-	 * to ready state before AP is up.
-	 */
-	hook_notify(HOOK_CHIPSET_PRE_INIT);
-
-	/* Enable the 3.3V and 5V rail. */
-	gpio_set_level(GPIO_EN_PP3300_A, 1);
-#ifdef CONFIG_POWER_PP5000_CONTROL
-	power_5v_enable(task_get_current(), 1);
-#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
-	gpio_set_level(GPIO_EN_PP5000, 1);
-#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
-
-	set_system_power(1);
-
-	/* Enable signal interrupts */
-	power_signal_enable_interrupt(GPIO_AP_RST_L);
-	power_signal_enable_interrupt(GPIO_PMIC_FAULT_L);
-
-	set_pmic_pwron(1);
-
-	disable_sleep(SLEEP_MASK_AP_RUN);
-
-	CPRINTS("AP running ...");
-}
-
-/**
- * Check if there has been a power-on event
- *
- * This checks all power-on event signals and returns non-zero if any have been
- * triggered (with debounce taken into account).
- *
- * @return non-zero if there has been a power-on event, 0 if not.
- */
-static uint8_t check_for_power_on_event(void)
-{
-	int ap_off_flag;
-
-	ap_off_flag = system_get_reset_flags() & EC_RESET_FLAG_AP_OFF;
-	system_clear_reset_flags(EC_RESET_FLAG_AP_OFF);
-
-	if (power_request == POWER_REQ_ON) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_ON;
-	} else if (power_request == POWER_REQ_RESET) {
-		power_request = POWER_REQ_NONE;
-		return POWER_ON_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/* check if system is already ON */
-	if (power_get_signals() & IN_POWER_GOOD) {
-		if (ap_off_flag) {
-			CPRINTS("system is on, but EC_RESET_FLAG_AP_OFF is on");
-			return POWER_ON_CANCEL;
-		}
-		CPRINTS("system is on, thus clear auto_power_on");
-		/* no need to arrange another power on */
-		auto_power_on = 0;
-		return POWER_ON_BY_IN_POWER_GOOD;
-	}
-	if (ap_off_flag) {
-		CPRINTS("EC_RESET_FLAG_AP_OFF is on");
-		power_off();
-		return POWER_ON_CANCEL;
-	}
-
-	CPRINTS("POWER_GOOD is not asserted");
-
-	/* power on requested at EC startup for recovery */
-	if (auto_power_on) {
-		auto_power_on = 0;
-		return POWER_ON_BY_AUTO_POWER_ON;
-	}
-
-	/* Check lid open */
-	if (lid_opened) {
-		lid_opened = 0;
-		return POWER_ON_BY_LID_OPEN;
-	}
-
-	/* check for power button press */
-	if (power_button_is_pressed())
-		return POWER_ON_BY_POWER_BUTTON_PRESSED;
-
-	return POWER_OFF_CANCEL;
-}
-
-/**
- * Check for some event triggering the shutdown.
- *
- * It can be either a long power button press or a shutdown triggered from the
- * AP and detected by reading POWER_GOOD.
- *
- * @return non-zero if a shutdown should happen, 0 if not
- */
-static uint8_t check_for_power_off_event(void)
-{
-	timestamp_t now;
-	int pressed = 0;
-
-	if (power_request == POWER_REQ_OFF) {
-		power_request = POWER_REQ_NONE;
-		return POWER_OFF_BY_POWER_REQ_OFF;
-	} else if (power_request == POWER_REQ_RESET) {
-		/*
-		 * The power_request flag will be cleared later
-		 * in check_for_power_on_event() in S5.
-		 */
-		return POWER_OFF_BY_POWER_REQ_RESET;
-	}
-	/* Clear invalid request */
-	power_request = POWER_REQ_NONE;
-
-	/*
-	 * Check for power button press.
-	 */
-	if (power_button_is_pressed())
-		pressed = POWER_OFF_BY_POWER_BUTTON_PRESSED;
-
-	now = get_time();
-	if (pressed) {
-		if (!power_button_was_pressed) {
-			power_off_deadline.val = now.val + DELAY_FORCE_SHUTDOWN;
-			CPRINTS("power waiting for long press %u",
-				power_off_deadline.le.lo);
-			/* Ensure we will wake up to check the power key */
-			timer_arm(power_off_deadline, TASK_ID_CHIPSET);
-		} else if (timestamp_expired(power_off_deadline, &now)) {
-			power_off_deadline.val = 0;
-			CPRINTS("power off after long press now=%u, %u",
-				now.le.lo, power_off_deadline.le.lo);
-			return POWER_OFF_BY_LONG_PRESS;
-		}
-	} else if (power_button_was_pressed) {
-		CPRINTS("power off cancel");
-		timer_cancel(TASK_ID_CHIPSET);
-	}
-
-	power_button_was_pressed = pressed;
-
-	/* POWER_GOOD released by AP : shutdown immediately */
-	if (!power_has_signals(IN_POWER_GOOD)) {
-		if (power_button_was_pressed)
-			timer_cancel(TASK_ID_CHIPSET);
-
-		CPRINTS("POWER_GOOD is lost");
-		return POWER_OFF_BY_POWER_GOOD_LOST;
-	}
-
-	return POWER_OFF_CANCEL;
-}
-
-/*****************************************************************************/
-/* Chipset interface */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Issue a request to initiate a power-off sequence */
-	power_request = POWER_REQ_OFF;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-	int rv;
-
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Warm reset sequence:
-	 * 1. Issue a low pulse to PMIC_RESIN_L, which triggers PMIC
-	 *    to do a warm reset (requiring reprogramming PMIC registers
-	 *    to make PMIC_RESIN_L as a warm reset trigger).
-	 * 2. PMIC then issues a low pulse to AP_RST_L to reset AP.
-	 *    EC monitors the signal to see any low pulse.
-	 *    2.1. If a low pulse found, done.
-	 *    2.2. If a low pulse not found (the above PMIC registers
-	 *         not programmed or programmed wrong), issue a request
-	 *         to initiate a cold reset power sequence.
-	 */
-
-	gpio_set_level(GPIO_PMIC_RESIN_L, 0);
-	usleep(PMIC_RESIN_PULSE_LENGTH);
-	gpio_set_level(GPIO_PMIC_RESIN_L, 1);
-
-	rv = power_wait_signals_timeout(IN_AP_RST_ASSERTED,
-					PMIC_POWER_AP_RESPONSE_TIMEOUT);
-	/* Exception case: PMIC not work as expected, request a cold reset */
-	if (rv != EC_SUCCESS)
-		request_cold_reset();
-}
-
-/**
- * Power handler for steady states
- *
- * @param state		Current power state
- * @return Updated power state
- */
-enum power_state power_handle_state(enum power_state state)
-{
-	uint8_t value;
-	static uint8_t boot_from_g3, shutdown_from_s0;
-
-	switch (state) {
-	case POWER_G3:
-		boot_from_g3 = check_for_power_on_event();
-		if (boot_from_g3)
-			return POWER_G3S5;
-		break;
-
-	case POWER_G3S5:
-		return POWER_S5;
-
-	case POWER_S5:
-		if (boot_from_g3) {
-			value = boot_from_g3;
-			boot_from_g3 = 0;
-		} else {
-			value = check_for_power_on_event();
-		}
-
-		if (value) {
-			CPRINTS("power on %d", value);
-			return POWER_S5S3;
-		}
-		break;
-
-	case POWER_S5S3:
-		/*
-		 * Wait for power button release before actually boot AP.
-		 * It may be a long-hold power button with volume buttons
-		 * to trigger the recovery button. We don't want AP up
-		 * during the long-hold.
-		 */
-		power_button_wait_for_release(-1);
-
-		power_on();
-		if (power_wait_signals(IN_POWER_GOOD) != EC_SUCCESS) {
-			CPRINTS("POWER_GOOD not seen in time");
-			set_system_power(0);
-			return POWER_S5;
-		}
-
-		CPRINTS("POWER_GOOD seen");
-		/* Call hooks now that AP is running */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		return POWER_S3;
-
-	case POWER_S3:
-		if (shutdown_from_s0) {
-			value = shutdown_from_s0;
-			shutdown_from_s0 = 0;
-		} else {
-			value = check_for_power_off_event();
-		}
-
-		if (value) {
-			CPRINTS("power off %d", value);
-			return POWER_S3S5;
-		}
-		/* Go to S3S0 directly, as don't know if it is in suspend */
-		return POWER_S3S0;
-
-	case POWER_S3S0:
-		hook_notify(HOOK_CHIPSET_RESUME);
-		return POWER_S0;
-
-	case POWER_S0:
-		shutdown_from_s0 = check_for_power_off_event();
-		if (shutdown_from_s0)
-			return POWER_S0S3;
-		break;
-
-	case POWER_S0S3:
-		/*
-		 * If the power button is pressing, we need cancel the long
-		 * press timer, otherwise EC will crash.
-		 */
-		if (power_button_was_pressed)
-			timer_cancel(TASK_ID_CHIPSET);
-
-		/* Call hooks here since we don't know it prior to AP suspend */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		power_off();
-		/*
-		 * Wait forever for the release of the power button; otherwise,
-		 * this power button press will then trigger a power-on in S5.
-		 */
-		power_button_wait_for_release(-1);
-		power_button_was_pressed = 0;
-		return POWER_S5;
-
-	case POWER_S5G3:
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-/*****************************************************************************/
-/* Console debug command */
-
-static const char *power_req_name[POWER_REQ_COUNT] = {
-	"none",
-	"off",
-	"on",
-};
-
-/* Power states that we can report */
-enum power_state_t {
-	PSTATE_UNKNOWN,
-	PSTATE_OFF,
-	PSTATE_ON,
-	PSTATE_COUNT,
-};
-
-static const char * const state_name[] = {
-	"unknown",
-	"off",
-	"on",
-};
-
-static int command_power(int argc, char **argv)
-{
-	int v;
-
-	if (argc < 2) {
-		enum power_state_t state;
-
-		state = PSTATE_UNKNOWN;
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			state = PSTATE_OFF;
-		if (chipset_in_state(CHIPSET_STATE_ON))
-			state = PSTATE_ON;
-		ccprintf("%s\n", state_name[state]);
-
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &v))
-		return EC_ERROR_PARAM1;
-
-	power_request = v ? POWER_REQ_ON : POWER_REQ_OFF;
-	ccprintf("Requesting power %s\n", power_req_name[power_request]);
-	task_wake(TASK_ID_CHIPSET);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
diff --git a/power/skylake.c b/power/skylake.c
deleted file mode 100644
index a4cb649fd5..0000000000
--- a/power/skylake.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lpc.h"
-#include "panic.h"
-#include "power/intel_x86.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-#ifdef CONFIG_POWER_S0IX
-	[X86_SLP_S0_DEASSERTED] = {
-		GPIO_PCH_SLP_S0_L,
-		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
-		"SLP_S0_DEASSERTED",
-	},
-#endif
-	[X86_SLP_S3_DEASSERTED] = {
-		SLP_S3_SIGNAL_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		SLP_S4_SIGNAL_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_S4_DEASSERTED",
-	},
-	[X86_SLP_SUS_DEASSERTED] = {
-		GPIO_PCH_SLP_SUS_L,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"SLP_SUS_DEASSERTED",
-	},
-	[X86_RSMRST_L_PWRGD] = {
-		GPIO_RSMRST_L_PGOOD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"RSMRST_N_PWRGD",
-	},
-	[X86_PMIC_DPWROK] = {
-		GPIO_PMIC_DPWROK,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PMIC_DPWROK",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s()", __func__);
-
-	/*
-	 * Force off. Sending a reset command to the PMIC will power off
-	 * the EC, so simulate a long power button press instead. This
-	 * condition will reset once the state machine transitions to G3.
-	 * Consider reducing the latency here by changing the power off
-	 * hold time on the PMIC.
-	 */
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		report_ap_reset(reason);
-		forcing_shutdown = 1;
-		power_button_pch_press();
-	}
-}
-
-__attribute__((weak)) void chipset_set_pmic_slp_sus_l(int level)
-{
-	gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
-}
-
-enum power_state chipset_force_g3(void)
-{
-	CPRINTS("Forcing fake G3.");
-
-	chipset_set_pmic_slp_sus_l(0);
-
-	return POWER_G3;
-}
-
-static void handle_slp_sus(enum power_state state)
-{
-	/* If we're down or going down don't do anythin with SLP_SUS_L. */
-	if (state == POWER_G3 || state == POWER_S5G3)
-		return;
-
-	/* Always mimic PCH SLP_SUS request for all other states. */
-	chipset_set_pmic_slp_sus_l(gpio_get_level(GPIO_PCH_SLP_SUS_L));
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/*
-	 * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
-	 * it means that there is an unexpected power loss (global reset
-	 * event). In this case, check if shutdown was being forced by pressing
-	 * power button. If yes, release power button.
-	 */
-	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	enum power_state new_state;
-
-	/* Process RSMRST_L state changes. */
-	common_intel_x86_handle_rsmrst(state);
-
-	if (state == POWER_S5 && forcing_shutdown) {
-		power_button_pch_release();
-		forcing_shutdown = 0;
-	}
-
-	new_state = common_intel_x86_power_handle_state(state);
-
-	/* Process SLP_SUS_L state changes after a new state is decided. */
-	handle_slp_sus(new_state);
-
-	return new_state;
-}
-
-/* Workaround for flags getting lost with power cycle */
-__attribute__((weak)) int board_has_working_reset_flags(void)
-{
-	return 1;
-}
-
-#ifdef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-void chipset_handle_reboot(void)
-{
-	int flags;
-
-	if (system_jumped_to_this_image())
-		return;
-
-	/* Interrogate current reset flags from previous reboot. */
-	flags = system_get_reset_flags();
-
-	/*
-	 * Do not make PMIC re-sequence the power rails if the following reset
-	 * conditions are not met.
-	 */
-	if (!(flags &
-		(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT |
-		 EC_RESET_FLAG_HARD)))
-		return;
-
-	/* Preserve AP off request. */
-	if (flags & EC_RESET_FLAG_AP_OFF) {
-		/* Do not issue PMIC reset if board cannot save reset flags */
-		if (!board_has_working_reset_flags()) {
-			ccprintf("Skip PMIC reset due to board issue.\n");
-			cflush();
-			return;
-		}
-		chip_save_reset_flags(EC_RESET_FLAG_AP_OFF);
-	}
-
-#ifdef CONFIG_CHIP_PANIC_BACKUP
-	/* Ensure panic data if any is backed up. */
-	chip_panic_data_backup();
-#endif
-
-	ccprintf("Restarting system with PMIC.\n");
-	/* Flush console */
-	cflush();
-
-	/* Bring down all rails but RTC rail (including EC power). */
-	gpio_set_level(GPIO_EC_PLATFORM_RST, 1);
-	while (1)
-		; /* wait here */
-}
-#if !defined(CONFIG_VBOOT_EFS) || !defined(CONFIG_VBOOT_EFS2)
-/* This is run in main for EFS1 & EFS2 */
-DECLARE_HOOK(HOOK_INIT, chipset_handle_reboot, HOOK_PRIO_FIRST);
-#endif
-#endif /* CONFIG_CHIPSET_HAS_PLATFORM_RESET */
diff --git a/setup.py b/setup.py
deleted file mode 100644
index fc6c5d396b..0000000000
--- a/setup.py
+++ /dev/null
@@ -1,91 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-from setuptools import setup
-
-setup(
-    name="ec3po",
-    version="1.0.0rc1",
-    author="Aseda Aboagye",
-    author_email="aaboagye@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
-    packages=["ec3po"],
-    py_modules=["ec3po.console", "ec3po.interpreter"],
-    description="EC console interpreter.",
-)
-
-setup(
-    name="ecusb",
-    version="1.0",
-    author="Nick Sanders",
-    author_email="nsanders@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/tigertool"},
-    packages=["ecusb"],
-    description="Tiny implementation of servod.",
-)
-
-setup(
-    name="servo_updater",
-    version="1.0",
-    author="Nick Sanders",
-    author_email="nsanders@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_updater"},
-    py_modules=["servo_updater", "fw_update"],
-    entry_points = {
-        "console_scripts": ["servo_updater=servo_updater:main"],
-    },
-    data_files=[("share/servo_updater/configs",
-                    ["extra/usb_updater/c2d2.json",
-                     "extra/usb_updater/servo_v4.json",
-                     "extra/usb_updater/servo_v4p1.json",
-                     "extra/usb_updater/servo_micro.json",
-                     "extra/usb_updater/sweetberry.json"])],
-    description="Servo usb updater.",
-)
-
-setup(
-    name="powerlog",
-    version="1.0",
-    author="Nick Sanders",
-    author_email="nsanders@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_power"},
-    py_modules=["powerlog", "stats_manager"],
-    entry_points = {
-        "console_scripts": ["powerlog=powerlog:main"],
-    },
-    description="Sweetberry power logger.",
-)
-
-setup(
-    name="console",
-    version="1.0",
-    author="Nick Sanders",
-    author_email="nsanders@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_serial"},
-    py_modules=["console"],
-    entry_points = {
-        "console_scripts": ["usb_console=console:main"],
-    },
-    description="Tool to open the usb console on servo, cr50.",
-)
-
-setup(
-    name="unpack_ftb",
-    version="1.0",
-    author="Wei-Han Chen",
-    author_email="stimim@chromium.org",
-    url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
-    py_modules=["unpack_ftb"],
-    entry_points = {
-        "console_scripts": ["unpack_ftb=unpack_ftb:main"],
-    },
-    description="Tool to convert ST touchpad .ftb file to .bin",
-)
-
diff --git a/test/accel_cal.c b/test/accel_cal.c
deleted file mode 100644
index de46822711..0000000000
--- a/test/accel_cal.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accel_cal.h"
-#include "test_util.h"
-#include "motion_sense.h"
-#include <math.h>
-
-struct motion_sensor_t motion_sensors[] = {};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct accel_cal_algo algos[2] = {
-	{
-		.newton_fit = NEWTON_FIT(8, 1, 0.01f, 0.25f, 1.0e-8f, 100),
-	},
-	{
-		.newton_fit = NEWTON_FIT(8, 1, 0.01f, 0.25f, 1.0e-8f, 100),
-	}
-};
-
-struct accel_cal cal = {
-	.still_det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5),
-	.algos = algos,
-	.num_temp_windows = ARRAY_SIZE(algos),
-};
-
-static bool accumulate(float x, float y, float z, float temperature)
-{
-	return accel_cal_accumulate(&cal, 0, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature)
-		| accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature);
-}
-
-DECLARE_EC_TEST(test_calibrated_correctly_with_kasa)
-{
-	bool has_bias;
-
-	accumulate(1.01f, 0.01f, 0.01f, 21.0f);
-	accumulate(-0.99f, 0.01f, 0.01f, 21.0f);
-	accumulate(0.01f, 1.01f, 0.01f, 21.0f);
-	accumulate(0.01f, -0.99f, 0.01f, 21.0f);
-	accumulate(0.01f, 0.01f, 1.01f, 21.0f);
-	accumulate(0.01f, 0.01f, -0.99f, 21.0f);
-	accumulate(0.7171f, 0.7171f, 0.7171f, 21.0f);
-	has_bias = accumulate(-0.6971f, -0.6971f, -0.6971f, 21.0f);
-
-	zassert_true(has_bias, NULL);
-	zassert_within(cal.bias[X], 0.01f, 0.0001f, "%f", cal.bias[X]);
-	zassert_within(cal.bias[Y], 0.01f, 0.0001f, "%f", cal.bias[Y]);
-	zassert_within(cal.bias[Z], 0.01f, 0.0001f, "%f", cal.bias[Z]);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_calibrated_correctly_with_newton)
-{
-	bool has_bias = false;
-	struct kasa_fit kasa;
-	fpv3_t kasa_bias;
-	float kasa_radius;
-	int i;
-	float data[] = {
-		1.00290f, 0.09170f, 0.09649f,
-		0.95183f, 0.23626f, 0.25853f,
-		0.95023f, 0.15387f, 0.31865f,
-		0.97374f, 0.01639f, 0.27675f,
-		0.88521f, 0.30212f, 0.39558f,
-		0.92787f, 0.35157f, 0.21209f,
-		0.95162f, 0.33173f, 0.10924f,
-		0.98397f, 0.22644f, 0.07737f,
-	};
-
-	kasa_reset(&kasa);
-	for (i = 0; i < ARRAY_SIZE(data); i += 3) {
-		zassert_false(has_bias, NULL);
-		kasa_accumulate(&kasa,  data[i], data[i + 1], data[i + 2]);
-		has_bias = accumulate(data[i], data[i + 1], data[i + 2], 21.0f);
-	}
-
-	kasa_compute(&kasa, kasa_bias, &kasa_radius);
-	zassert_true(has_bias, NULL);
-	/* Check that the bias is right */
-	zassert_within(cal.bias[X], 0.01f, 0.001f, "%f", cal.bias[X]);
-	zassert_within(cal.bias[Y], 0.01f, 0.001f, "%f", cal.bias[Y]);
-	zassert_within(cal.bias[Z], 0.01f, 0.001f, "%f", cal.bias[Z]);
-	/* Demonstrate that we got a better bias compared to kasa */
-	zassert_true(sqrtf(powf(cal.bias[X] - 0.01f, 2.0f) +
-			   powf(cal.bias[Y] - 0.01f, 2.0f) +
-			   powf(cal.bias[Z] - 0.01f, 2.0f)) <
-		     sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) +
-			   powf(kasa_bias[Y] - 0.01f, 2.0f) +
-			   powf(kasa_bias[Z] - 0.01f, 2.0f)),
-		     NULL);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_temperature_gates)
-{
-	bool has_bias;
-
-	accumulate(1.01f, 0.01f, 0.01f, 21.0f);
-	accumulate(-0.99f, 0.01f, 0.01f, 21.0f);
-	accumulate(0.01f, 1.01f, 0.01f, 21.0f);
-	accumulate(0.01f, -0.99f, 0.01f, 21.0f);
-	accumulate(0.01f, 0.01f, 1.01f, 21.0f);
-	accumulate(0.01f, 0.01f, -0.99f, 21.0f);
-	accumulate(0.7171f, 0.7171f, 0.7171f, 21.0f);
-	has_bias = accumulate(-0.6971f, -0.6971f, -0.6971f, 31.0f);
-
-	zassert_false(has_bias, NULL);
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	cal.still_det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	accel_cal_reset(&cal);
-}
-
-void after_test(void) {}
-
-TEST_MAIN()
-{
-	ztest_test_suite(test_accel_cal,
-			 ztest_unit_test_setup_teardown(
-				 test_calibrated_correctly_with_kasa,
-				 before_test, after_test),
-			 ztest_unit_test_setup_teardown(
-				 test_calibrated_correctly_with_newton,
-				 before_test, after_test),
-			 ztest_unit_test_setup_teardown(test_temperature_gates,
-							before_test,
-							after_test));
-	ztest_run_test_suite(test_accel_cal);
-}
diff --git a/test/accel_cal.tasklist b/test/accel_cal.tasklist
deleted file mode 100644
index 0e3696c3f0..0000000000
--- a/test/accel_cal.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/aes.c b/test/aes.c
deleted file mode 100644
index 1c71e2874e..0000000000
--- a/test/aes.c
+++ /dev/null
@@ -1,664 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-#include "aes.h"
-#include "aes-gcm.h"
-#include "console.h"
-#include "common.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/* Temporary buffer, to avoid using too much stack space. */
-static uint8_t tmp[512];
-
-/*
- * Do encryption, put result in |result|, and compare with |ciphertext|.
- */
-static int test_aes_gcm_encrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
-{
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	TEST_ASSERT(CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, result,
-					  plaintext_size));
-	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
-	TEST_ASSERT_ARRAY_EQ(ciphertext, result, plaintext_size);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Do decryption, put result in |result|, and compare with |plaintext|.
- */
-static int test_aes_gcm_decrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
-{
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
-	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-	TEST_ASSERT(CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, result,
-					  plaintext_size));
-	TEST_ASSERT(CRYPTO_gcm128_finish(&ctx, tag, tag_size));
-	TEST_ASSERT_ARRAY_EQ(plaintext, result, plaintext_size);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw_inplace(const uint8_t *key,
-				    int key_size,
-				    const uint8_t *plaintext,
-				    const uint8_t *ciphertext,
-				    int plaintext_size,
-				    const uint8_t *nonce,
-				    int nonce_size,
-				    const uint8_t *tag,
-				    int tag_size)
-{
-
-	/*
-	 * Make copies that will be clobbered during in-place encryption or
-	 * decryption.
-	 */
-	uint8_t plaintext_copy[plaintext_size];
-	uint8_t ciphertext_copy[plaintext_size];
-
-	memcpy(plaintext_copy, plaintext, plaintext_size);
-	memcpy(ciphertext_copy, ciphertext, plaintext_size);
-
-	TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy,
-					 key,
-					 key_size,
-					 plaintext_copy,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext_copy,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw_non_inplace(const uint8_t *key,
-					int key_size,
-					const uint8_t *plaintext,
-					const uint8_t *ciphertext,
-					int plaintext_size,
-					const uint8_t *nonce,
-					int nonce_size,
-					const uint8_t *tag,
-					int tag_size)
-{
-	TEST_ASSERT(test_aes_gcm_encrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	TEST_ASSERT(test_aes_gcm_decrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
-					 tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm_raw(const uint8_t *key,
-			    int key_size,
-			    const uint8_t *plaintext,
-			    const uint8_t *ciphertext,
-			    int plaintext_size,
-			    const uint8_t *nonce,
-			    int nonce_size,
-			    const uint8_t *tag,
-			    int tag_size)
-{
-	TEST_ASSERT(plaintext_size <= sizeof(tmp));
-
-	TEST_ASSERT(test_aes_gcm_raw_non_inplace(key,
-						 key_size,
-						 plaintext,
-						 ciphertext,
-						 plaintext_size,
-						 nonce,
-						 nonce_size,
-						 tag,
-						 tag_size) == EC_SUCCESS);
-	TEST_ASSERT(test_aes_gcm_raw_inplace(key,
-					     key_size,
-					     plaintext,
-					     ciphertext,
-					     plaintext_size,
-					     nonce,
-					     nonce_size,
-					     tag,
-					     tag_size) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes_gcm(void)
-{
-	/*
-	 * Test vectors from BoringSSL crypto/fipsmodule/modes/gcm_tests.txt
-	 * (only the ones with actual data, and no additional data).
-	 */
-	static const uint8_t key1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher1[] = {
-		0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92,
-		0xf3, 0x28, 0xc2, 0xb9, 0x71, 0xb2, 0xfe, 0x78,
-	};
-	static const uint8_t tag1[] = {
-		0xab, 0x6e, 0x47, 0xd4, 0x2c, 0xec, 0x13, 0xbd,
-		0xf5, 0x3a, 0x67, 0xb2, 0x12, 0x57, 0xbd, 0xdf,
-	};
-
-	static const uint8_t key2[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-	};
-	static const uint8_t plain2[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce2[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher2[] = {
-		0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
-		0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
-		0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
-		0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
-		0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
-		0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
-		0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
-		0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85,
-	};
-	static const uint8_t tag2[] = {
-		0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
-		0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4,
-	};
-
-	static const uint8_t key3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher3[] = {
-		0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
-		0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00,
-	};
-	static const uint8_t tag3[] = {
-		0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab,
-		0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb,
-	};
-
-	static const uint8_t key4[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-	};
-	static const uint8_t plain4[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce4[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher4[] = {
-		0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
-		0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
-		0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
-		0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
-		0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
-		0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
-		0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
-		0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56,
-	};
-	static const uint8_t tag4[] = {
-		0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
-		0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14,
-	};
-
-	static const uint8_t key5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t nonce5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher5[] = {
-		0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e,
-		0x07, 0x4e, 0xc5, 0xd3, 0xba, 0xf3, 0x9d, 0x18,
-	};
-	static const uint8_t tag5[] = {
-		0xd0, 0xd1, 0xc8, 0xa7, 0x99, 0x99, 0x6b, 0xf0,
-		0x26, 0x5b, 0x98, 0xb5, 0xd4, 0x8a, 0xb9, 0x19,
-	};
-
-	static const uint8_t key6[] = {
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
-		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
-	};
-	static const uint8_t plain6[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
-	};
-	static const uint8_t nonce6[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
-	};
-	static const uint8_t cipher6[] = {
-		0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
-		0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
-		0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
-		0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
-		0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
-		0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
-		0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
-		0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad,
-	};
-	static const uint8_t tag6[] = {
-		0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd,
-		0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c,
-	};
-
-	static const uint8_t key7[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t plain7[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	/* This nonce results in 0xfff in counter LSB. */
-	static const uint8_t nonce7[] = {
-		0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	static const uint8_t cipher7[] = {
-		0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a,
-		0x2b, 0x64, 0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14,
-		0x25, 0xf1, 0x0d, 0x47, 0xa7, 0x5a, 0x5f, 0xce,
-		0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a, 0xf2, 0x4f,
-		0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70,
-		0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18,
-		0xa9, 0xae, 0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf,
-		0xc6, 0xa7, 0x83, 0x97, 0xb9, 0xa8, 0x5b, 0x49,
-		0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67, 0xca, 0xab,
-		0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c,
-		0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c,
-		0xb4, 0xf3, 0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29,
-		0xc9, 0xe8, 0xc4, 0xdc, 0x0a, 0x2a, 0x5f, 0xf1,
-		0x90, 0x3e, 0x50, 0x15, 0x11, 0x22, 0x13, 0x76,
-		0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2,
-		0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce,
-		0xb0, 0xab, 0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f,
-		0x8c, 0x90, 0xbe, 0x40, 0x2d, 0xdf, 0x6d, 0x86,
-		0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1, 0x5b, 0xfb,
-		0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18,
-		0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65,
-		0x3c, 0x71, 0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42,
-		0x11, 0xf4, 0x2b, 0xae, 0x12, 0xaf, 0x46, 0x2b,
-		0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e, 0x36, 0x06,
-		0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24,
-		0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c,
-		0x4b, 0xcc, 0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4,
-		0x20, 0xa2, 0xf8, 0xeb, 0x66, 0xdc, 0xf3, 0x64,
-		0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69, 0x90, 0x03,
-		0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6,
-		0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90,
-		0x27, 0x83, 0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74,
-		0x18, 0x8a, 0x43, 0x9c, 0x7e, 0xbc, 0xc0, 0x67,
-		0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2, 0x79, 0x46,
-		0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78,
-		0x70, 0x8a, 0x70, 0xee, 0x7d, 0x75, 0x16, 0x5c,
-	};
-	static const uint8_t tag7[] = {
-		0x8b, 0x30, 0x7f, 0x6b, 0x33, 0x28, 0x6d, 0x0a,
-		0xb0, 0x26, 0xa9, 0xed, 0x3f, 0xe1, 0xe8, 0x5f,
-	};
-
-	TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1),
-			plain1, cipher1, sizeof(plain1),
-			nonce1, sizeof(nonce1), tag1, sizeof(tag1)));
-	TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2),
-			plain2, cipher2, sizeof(plain2),
-			nonce2, sizeof(nonce2), tag2, sizeof(tag2)));
-	TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3),
-			plain3, cipher3, sizeof(plain3),
-			nonce3, sizeof(nonce3), tag3, sizeof(tag3)));
-	TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4),
-			plain4, cipher4, sizeof(plain4),
-			nonce4, sizeof(nonce4), tag4, sizeof(tag4)));
-	TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5),
-			plain5, cipher5, sizeof(plain5),
-			nonce5, sizeof(nonce5), tag5, sizeof(tag5)));
-	TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6),
-			plain6, cipher6, sizeof(plain6),
-			nonce6, sizeof(nonce6), tag6, sizeof(tag6)));
-	TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7),
-			plain7, cipher7, sizeof(plain7),
-			nonce7, sizeof(nonce7), tag7, sizeof(tag7)));
-
-	return EC_SUCCESS;
-}
-
-static void test_aes_gcm_speed(void)
-{
-	int i;
-	static const uint8_t key[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	};
-	const int key_size = sizeof(key);
-	static const uint8_t plaintext[512] = { 0 };
-	const int plaintext_size = sizeof(plaintext);
-	static const uint8_t nonce[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
-	};
-	const int nonce_size = sizeof(nonce);
-	uint8_t tag[16] = {0};
-	const int tag_size = sizeof(tag);
-
-	uint8_t *out = tmp;
-	static AES_KEY aes_key;
-	static GCM128_CONTEXT ctx;
-	timestamp_t t0, t1;
-
-	assert(plaintext_size <= sizeof(tmp));
-
-	t0 = get_time();
-	for (i = 0; i < 1000; i++) {
-		AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-		CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
-		CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
-		CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, out,
-				plaintext_size);
-		CRYPTO_gcm128_tag(&ctx, tag, tag_size);
-	}
-	t1 = get_time();
-	ccprintf("AES-GCM duration %lld us\n", (long long)(t1.val - t0.val));
-}
-
-static int test_aes_raw(const uint8_t *key, int key_size,
-			const uint8_t *plaintext, const uint8_t *ciphertext)
-{
-	AES_KEY aes_key;
-	uint8_t *block = tmp;
-
-	TEST_ASSERT(AES_BLOCK_SIZE <= sizeof(tmp));
-
-	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	/* Test encryption. */
-	AES_encrypt(plaintext, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
-
-	/* Test in-place encryption. */
-	memcpy(block, plaintext, AES_BLOCK_SIZE);
-	AES_encrypt(block, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(ciphertext, block, AES_BLOCK_SIZE);
-
-	TEST_ASSERT(AES_set_decrypt_key(key, 8 * key_size, &aes_key) == 0);
-
-	/* Test decryption. */
-	AES_decrypt(ciphertext, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
-
-	/* Test in-place decryption. */
-	memcpy(block, ciphertext, AES_BLOCK_SIZE);
-	AES_decrypt(block, block, &aes_key);
-	TEST_ASSERT_ARRAY_EQ(plaintext, block, AES_BLOCK_SIZE);
-
-	return EC_SUCCESS;
-}
-
-static int test_aes(void)
-{
-	/* Test vectors from FIPS-197, Appendix C. */
-	static const uint8_t key1[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	};
-	static const uint8_t plain1[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher1[] = {
-		0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30,
-		0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a,
-	};
-
-	static const uint8_t key2[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	};
-	static const uint8_t plain2[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher2[] = {
-		0xdd, 0xa9, 0x7c, 0xa4, 0x86, 0x4c, 0xdf, 0xe0,
-		0x6e, 0xaf, 0x70, 0xa0, 0xec, 0x0d, 0x71, 0x91,
-	};
-
-	static const uint8_t key3[] = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
-	};
-	static const uint8_t plain3[] = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-	static const uint8_t cipher3[] = {
-		0x8e, 0xa2, 0xb7, 0xca, 0x51, 0x67, 0x45, 0xbf,
-		0xea, 0xfc, 0x49, 0x90, 0x4b, 0x49, 0x60, 0x89,
-	};
-
-	TEST_ASSERT(!test_aes_raw(key1, sizeof(key1), plain1, cipher1));
-	TEST_ASSERT(!test_aes_raw(key2, sizeof(key2), plain2, cipher2));
-	TEST_ASSERT(!test_aes_raw(key3, sizeof(key3), plain3, cipher3));
-
-	return EC_SUCCESS;
-}
-
-static void test_aes_speed(void)
-{
-	int i;
-	/* Test vectors from FIPS-197, Appendix C. */
-	static const uint8_t key[] __aligned(4) = {
-		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	};
-	const int key_size = sizeof(key);
-	static const uint8_t plaintext[] __aligned(4) = {
-		0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-		0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
-	};
-
-	AES_KEY aes_key;
-	uint8_t block[AES_BLOCK_SIZE];
-	timestamp_t t0, t1;
-
-	AES_set_encrypt_key(key, 8 * key_size, &aes_key);
-	AES_encrypt(plaintext, block, &aes_key);
-	t0 = get_time();
-	for (i = 0; i < 1000; i++)
-		AES_encrypt(block, block, &aes_key);
-	t1 = get_time();
-	ccprintf("AES duration %lld us\n", (long long)(t1.val - t0.val));
-}
-
-void run_test(int argc, char **argv)
-{
-	watchdog_reload();
-
-	/* do not check result, just as a benchmark */
-	test_aes_speed();
-
-	watchdog_reload();
-	RUN_TEST(test_aes);
-
-	/* do not check result, just as a benchmark */
-	test_aes_gcm_speed();
-
-	watchdog_reload();
-	RUN_TEST(test_aes_gcm);
-
-	test_print_result();
-}
diff --git a/test/aes.tasklist b/test/aes.tasklist
deleted file mode 100644
index 24870f2abb..0000000000
--- a/test/aes.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/base32.c b/test/base32.c
deleted file mode 100644
index faaefc266f..0000000000
--- a/test/base32.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test Base-32 encoding/decoding
- */
-
-#include <stdio.h>
-#include "common.h"
-#include "base32.h"
-#include "test_util.h"
-#include "util.h"
-
-DECLARE_EC_TEST(test_crc5)
-{
-	uint32_t seen;
-	int i, j, c;
-	int errors = 0;
-
-	/*
-	 * For every current CRC value and symbol, new CRC value is unique.
-	 * This guarantees a single-character typo will be detected.
-	 */
-	for (i = 0; i < 32; i++) {
-		seen = 0;
-		for (j = 0; j < 32; j++)
-			seen |= 1 << crc5_sym(j, i);
-		zassert_equal(seen, 0xffffffff, NULL);
-	}
-
-	/*
-	 * Do the same in the opposite order, to make sure a subsequent
-	 * character doesn't obscure a previous typo.
-	 */
-	for (i = 0; i < 32; i++) {
-		seen = 0;
-		for (j = 0; j < 32; j++)
-			seen |= 1 << crc5_sym(i, j);
-		zassert_equal(seen, 0xffffffff, NULL);
-	}
-
-	/* Transposing different symbols generates distinct CRCs */
-	for (c = 0; c < 32; c++) {
-		for (i = 0; i < 32; i++) {
-			for (j = i + 1; j < 32; j++) {
-				if (crc5_sym(j, crc5_sym(i, c)) ==
-				    crc5_sym(i, crc5_sym(j, c)))
-					errors++;
-			}
-		}
-	}
-	zassert_equal(errors, 0, NULL);
-
-	return EC_SUCCESS;
-}
-
-static int enctest(const void *src, int srcbits, int crc_every,
-		   const char *enc)
-{
-	char dest[32];
-
-	if (base32_encode(dest, sizeof(dest), src, srcbits, crc_every))
-		return -1;
-	if (strlen(dest) != strlen(enc) || strncmp(dest, enc, strlen(dest))) {
-		fprintf(stderr, "expected encode: \"%s\"\n", enc);
-		fprintf(stderr, "got encode:      \"%s\"\n", dest);
-		return -2;
-	}
-	return 0;
-}
-
-#define ENCTEST(a, b, c, d) zassert_equal(enctest(a, b, c, d), 0, NULL)
-
-DECLARE_EC_TEST(test_encode)
-{
-	const uint8_t src1[5] = {0xff, 0x00, 0xff, 0x00, 0xff};
-	char enc[32];
-
-	/* Test for enough space; error produces null string */
-	*enc = 1;
-	zassert_equal(base32_encode(enc, 3, src1, 15, 0), EC_ERROR_INVAL, NULL);
-	zassert_equal(*enc, 0, NULL);
-
-	/* Empty source */
-	ENCTEST("\x00", 0, 0, "");
-
-	/* Single symbol uses top 5 bits */
-	ENCTEST("\x07", 5, 0, "A");
-	ENCTEST("\xb8", 5, 0, "Z");
-	ENCTEST("\xc0", 5, 0, "2");
-	ENCTEST("\xf8", 5, 0, "9");
-
-	/* Multiples of 5 bits use top bits */
-	ENCTEST("\x08\x86", 10, 0, "BC");
-	ENCTEST("\x08\x86", 15, 0, "BCD");
-
-	/* Multiples of 8 bits pad with 0 bits */
-	ENCTEST("\xff", 8, 0, "96");
-	ENCTEST("\x08\x87", 16, 0, "BCDS");
-
-	/* Multiples of 40 bits use all the bits */
-	ENCTEST("\xff\x00\xff\x00\xff", 40, 0, "96AR8AH9");
-
-	/* CRC requires exact multiple of symbol count */
-	ENCTEST("\xff\x00\xff\x00\xff", 40, 4, "96ARU8AH9D");
-	ENCTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L");
-	zassert_equal(
-		base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff",
-			40, 6),
-		EC_ERROR_INVAL, NULL);
-	/* But what matters is symbol count, not bit count */
-	ENCTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
-
-	return EC_SUCCESS;
-}
-
-static int cmpbytes(const uint8_t *expect, const uint8_t *got, int len,
-		    const char *desc)
-{
-	int i;
-
-	if (!memcmp(expect, got, len))
-		return 0;
-
-	fprintf(stderr, "expected %s:", desc);
-	for (i = 0; i < len; i++)
-		fprintf(stderr, " %02x", expect[i]);
-	fprintf(stderr, "\ngot %s:     ", desc);
-	for (i = 0; i < len; i++)
-		fprintf(stderr, " %02x", got[i]);
-	fprintf(stderr, "\n");
-
-	return -2;
-}
-
-static int dectest(const void *dec, int decbits, int crc_every, const char *enc)
-{
-	uint8_t dest[32];
-	int destbits = decbits > 0 ? decbits : sizeof(dest) * 8;
-	int wantbits = decbits > 0 ? decbits : 5 * strlen(enc);
-	int gotbits = base32_decode(dest, destbits, enc, crc_every);
-
-	zassert_equal(gotbits, wantbits, NULL);
-	if (gotbits != wantbits)
-		return -1;
-	return cmpbytes(dec, dest, (decbits + 7) / 8, "decode");
-}
-
-#define DECTEST(a, b, c, d) zassert_equal(dectest(a, b, c, d), 0, NULL)
-
-DECLARE_EC_TEST(test_decode)
-{
-	uint8_t dec[32];
-
-	/* Decode tests, dest-limited */
-	DECTEST("\xf8", 5, 0, "97");
-	DECTEST("\x08", 5, 0, "BCDS");
-	DECTEST("\x08\x80", 10, 0, "BCDS");
-	DECTEST("\x08\x86", 15, 0, "BCDS");
-	DECTEST("\xff", 8, 0, "96");
-	DECTEST("\x08\x87", 16, 0, "BCDS");
-	DECTEST("\xff\x00\xff\x00\xff", 40, 0, "96AR8AH9");
-	DECTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
-
-	/* Decode ignores whitespace and dashes */
-	DECTEST("\xff\x00\xff\x00\xff", 40, 0, " 96\tA-R\r8A H9\n");
-
-	/* Invalid symbol fails */
-	zassert_equal(base32_decode(dec, 16, "AI", 0), -1, NULL);
-
-	/* If dest buffer is big, use all the source bits */
-	DECTEST("", 0, 0, "");
-	DECTEST("\xf8", 0, 0, "9");
-	DECTEST("\x07\xc0", 0, 0, "A9");
-	DECTEST("\x00\x3e", 0, 0, "AA9");
-	DECTEST("\x00\x01\xf0", 0, 0, "AAA9");
-	DECTEST("\xff\x00\xff\x00\xff", 0, 0, "96AR8AH9");
-
-	/* Decode always overwrites destination */
-	memset(dec, 0xff, sizeof(dec));
-	DECTEST("\x00\x00\x00\x00\x00", 0, 0, "AAAAAAAA");
-	memset(dec, 0x00, sizeof(dec));
-	DECTEST("\xff\xff\xff\xff\xff", 0, 0, "99999999");
-
-	/* Good CRCs */
-	DECTEST("\xff\x00\xff\x00\xff", 40, 4, "96ARU8AH9D");
-	DECTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L");
-
-	/* CRC requires exact multiple of symbol count */
-	zassert_equal(base32_decode(dec, 40, "96ARL8AH9", 4), -1, NULL);
-	/* But what matters is symbol count, not bit count */
-	DECTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
-
-	/* Detect errors in data, CRC, and transposition */
-	zassert_equal(base32_decode(dec, 40, "96AQL", 4), -1, NULL);
-	zassert_equal(base32_decode(dec, 40, "96ARM", 4), -1, NULL);
-	zassert_equal(base32_decode(dec, 40, "96RAL", 4), -1, NULL);
-
-	return EC_SUCCESS;
-}
-
-TEST_MAIN()
-{
-	ztest_test_suite(test_base32_lib,
-			 ztest_unit_test(test_crc5),
-			 ztest_unit_test(test_encode),
-			 ztest_unit_test(test_decode));
-	ztest_run_test_suite(test_base32_lib);
-}
diff --git a/test/base32.tasklist b/test/base32.tasklist
deleted file mode 100644
index 7150f17cbd..0000000000
--- a/test/base32.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/battery_get_params_smart.c b/test/battery_get_params_smart.c
deleted file mode 100644
index 3163fb587e..0000000000
--- a/test/battery_get_params_smart.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test the logic of battery_get_params() to be sure it sets the correct flags
- * when i2c reads fail.
- */
-
-#include "battery.h"
-#include "battery_smart.h"
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "test_util.h"
-#include "util.h"
-
-/* Test state */
-static int fail_on_first, fail_on_last;
-static int read_count, write_count;
-struct batt_params batt;
-
-
-void battery_compensate_params(struct batt_params *batt)
-{
-}
-
-void board_battery_compensate_params(struct batt_params *batt)
-{
-}
-
-static void reset_and_fail_on(int first, int last)
-{
-	/* We're not initializing the fake battery, so everything reads zero */
-	memset(&batt, 0, sizeof(typeof(batt)));
-	read_count = write_count = 0;
-	fail_on_first = first;
-	fail_on_last = last;
-}
-
-/* Mocked functions */
-int sb_read(int cmd, int *param)
-{
-	read_count++;
-	if (read_count >= fail_on_first && read_count <= fail_on_last)
-		return EC_ERROR_UNKNOWN;
-
-	return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			  cmd, param);
-}
-int sb_write(int cmd, int param)
-{
-	write_count++;
-	return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			   cmd, param);
-}
-
-
-/* Tests */
-static int test_param_failures(void)
-{
-	int i, num_reads;
-
-	/* No failures */
-	reset_and_fail_on(0, 0);
-	battery_get_params(&batt);
-	TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
-	TEST_ASSERT(!(batt.flags & BATT_FLAG_BAD_ANY));
-	num_reads = read_count;
-
-	/* Just a single failure */
-	for (i = 1; i <= num_reads; i++) {
-		reset_and_fail_on(i, i);
-		battery_get_params(&batt);
-		TEST_ASSERT(batt.flags & BATT_FLAG_BAD_ANY);
-		TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
-	}
-
-	/* Once it fails, it keeps failing */
-	for (i = 1; i <= num_reads; i++) {
-		reset_and_fail_on(i, num_reads);
-		battery_get_params(&batt);
-		TEST_ASSERT(batt.flags & BATT_FLAG_BAD_ANY);
-		if (i == 1)
-			/* If every read fails, it's not responsive */
-			TEST_ASSERT(!(batt.flags & BATT_FLAG_RESPONSIVE));
-		else
-			TEST_ASSERT(batt.flags & BATT_FLAG_RESPONSIVE);
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_param_failures);
-
-	test_print_result();
-}
diff --git a/test/battery_get_params_smart.tasklist b/test/battery_get_params_smart.tasklist
deleted file mode 100644
index c2eb8159a9..0000000000
--- a/test/battery_get_params_smart.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST	/* No test task */
diff --git a/test/bklight_lid.c b/test/bklight_lid.c
deleted file mode 100644
index 99167a71a6..0000000000
--- a/test/bklight_lid.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test backlight control based on lid
- */
-
-#include "backlight.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int mock_lid = 1;
-static int backlight_en;
-
-int gpio_get_level(enum gpio_signal signal)
-{
-	if (signal == GPIO_LID_OPEN)
-		return mock_lid;
-	return 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int level)
-{
-	if (signal == GPIO_ENABLE_BACKLIGHT)
-		backlight_en = level;
-}
-
-void set_lid_state(int is_open)
-{
-	mock_lid = is_open;
-	lid_interrupt(GPIO_LID_OPEN);
-	msleep(40);
-}
-
-static int send_bklight_hostcmd(int enabled)
-{
-	struct ec_params_switch_enable_backlight p;
-	p.enabled = enabled;
-
-	return test_send_host_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, &p,
-				      sizeof(p), NULL, 0);
-}
-
-static int test_passthrough(void)
-{
-	/* Initial state */
-	TEST_ASSERT(mock_lid == 1);
-	TEST_ASSERT(backlight_en);
-
-	/* Close lid. Backlight should turn off */
-	set_lid_state(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Open lid. Backlight turns on */
-	set_lid_state(1);
-	TEST_ASSERT(backlight_en);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcommand(void)
-{
-	/* Open lid */
-	set_lid_state(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Disable by host command */
-	send_bklight_hostcmd(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Close and open lid. Backlight should come up */
-	set_lid_state(0);
-	set_lid_state(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Close lid */
-	set_lid_state(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Enable by host command */
-	send_bklight_hostcmd(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Disable backlight by lid */
-	set_lid_state(1);
-	set_lid_state(0);
-	TEST_ASSERT(!backlight_en);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_passthrough);
-	RUN_TEST(test_hostcommand);
-
-	test_print_result();
-}
diff --git a/test/bklight_lid.tasklist b/test/bklight_lid.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/bklight_lid.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/bklight_passthru.c b/test/bklight_passthru.c
deleted file mode 100644
index 170cc734cd..0000000000
--- a/test/bklight_passthru.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test x86 backlight passthrough.
- */
-
-#include "backlight.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int mock_lid = 1;
-static int mock_pch_bklten;
-static int backlight_en;
-
-int gpio_get_level(enum gpio_signal signal)
-{
-	if (signal == GPIO_LID_OPEN)
-		return mock_lid;
-	if (signal == GPIO_PCH_BKLTEN)
-		return mock_pch_bklten;
-	return 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int level)
-{
-	if (signal == GPIO_ENABLE_BACKLIGHT)
-		backlight_en = level;
-}
-
-void set_lid_state(int is_open)
-{
-	mock_lid = is_open;
-	lid_interrupt(GPIO_LID_OPEN);
-	msleep(40);
-}
-
-void set_pch_bklten(int enabled)
-{
-	int orig = mock_pch_bklten;
-	mock_pch_bklten = enabled;
-	if (orig != enabled)
-		backlight_interrupt(GPIO_PCH_BKLTEN);
-}
-
-static int send_bklight_hostcmd(int enabled)
-{
-	struct ec_params_switch_enable_backlight p;
-	p.enabled = enabled;
-
-	return test_send_host_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, &p,
-				      sizeof(p), NULL, 0);
-}
-
-static int test_passthrough(void)
-{
-	/* Initial state */
-	TEST_ASSERT(mock_lid == 1 && mock_pch_bklten == 0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Enable backlight */
-	set_pch_bklten(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Disable backlight */
-	set_pch_bklten(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Enable backlight again */
-	set_pch_bklten(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Close lid. Backlight should turn off */
-	set_lid_state(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Open lid. Backlight turns on */
-	set_lid_state(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Close lid and disable backlight */
-	set_lid_state(0);
-	set_pch_bklten(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Open lid now. Backlight stays off */
-	set_lid_state(1);
-	TEST_ASSERT(!backlight_en);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcommand(void)
-{
-	/* Open lid and enable backlight */
-	set_lid_state(1);
-	set_pch_bklten(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Disable by host command */
-	send_bklight_hostcmd(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Close and open lid. Backlight should come up */
-	set_lid_state(0);
-	set_lid_state(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Close lid and disable backlight */
-	set_lid_state(0);
-	set_pch_bklten(0);
-	TEST_ASSERT(!backlight_en);
-
-	/* Enable by host command */
-	send_bklight_hostcmd(1);
-	TEST_ASSERT(backlight_en);
-
-	/* Disable backlight by lid */
-	set_lid_state(1);
-	set_lid_state(0);
-	TEST_ASSERT(!backlight_en);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_passthrough);
-	RUN_TEST(test_hostcommand);
-
-	test_print_result();
-}
diff --git a/test/bklight_passthru.tasklist b/test/bklight_passthru.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/bklight_passthru.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/body_detection.c b/test/body_detection.c
deleted file mode 100644
index aa131f0a31..0000000000
--- a/test/body_detection.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test body_detection algorithm
- */
-
-#include "accelgyro.h"
-#include "body_detection.h"
-#include "body_detection_test_data.h"
-#include "common.h"
-#include "motion_common.h"
-#include "motion_sense.h"
-#include "test_util.h"
-#include "util.h"
-
-static struct motion_sensor_t *sensor = &motion_sensors[BASE];
-static const int window_size = 50; /* sensor data rate (Hz) */
-
-static int filler(const struct motion_sensor_t *s, const float v)
-{
-	int resolution = s->drv->get_resolution(s);
-	int data_1g = BIT(resolution - 1) / s->current_range;
-
-	return (int)(v * data_1g / 9.8);
-}
-
-static void feed_body_detect_data(const struct body_detect_test_data *array,
-				  const int idx)
-{
-	sensor->xyz[X] = filler(sensor, array[idx].x);
-	sensor->xyz[Y] = filler(sensor, array[idx].y);
-	sensor->xyz[Z] = filler(sensor, array[idx].z);
-}
-
-static int get_trigger_time(const struct body_detect_test_data *data,
-			    const size_t size,
-			    const enum body_detect_states target_state)
-{
-	int i, action_index = -1, target_index = -1;
-
-	body_detect_reset();
-	/*
-	 * Clear on-body state when the window is initialized, so
-	 * that we do not need to wait for 15 second if the testcase
-	 * is in off-body initially.
-	 */
-	body_detect_change_state(BODY_DETECTION_OFF_BODY, false);
-	for (i = 0; i < size; ++i) {
-		enum body_detect_states motion_state;
-
-		if (data[i].action == 1 && action_index == -1) {
-			cprints(CC_ACCEL, "action start");
-			action_index = i;
-		}
-		feed_body_detect_data(data, i);
-		/* run the body detect */
-		body_detect();
-		/* skip if action not start yet */
-		if (action_index == -1)
-			continue;
-
-		motion_state = body_detect_get_state();
-		if (target_index == -1 && motion_state == target_state)
-			target_index = i;
-	}
-	if (target_index == -1)
-		return -1;
-	return target_index - action_index;
-}
-
-static int test_body_detect(void)
-{
-	int ret, trigger_time;
-
-	ret = sensor->drv->set_data_rate(sensor, window_size * 1000, 0);
-	TEST_ASSERT(ret == EC_SUCCESS);
-
-	body_detect_set_enable(true);
-	/* Onbody test */
-	cprints(CC_ACCEL, "start OnBody test");
-	trigger_time = get_trigger_time(kBodyDetectOnBodyTestData,
-					kBodyDetectOnBodyTestDataLength,
-					BODY_DETECTION_OFF_BODY);
-	/* It should not enter off-body state ever */
-	TEST_ASSERT(trigger_time == -1);
-
-	/* OffOn test */
-	cprints(CC_ACCEL, "start Off to On test");
-	trigger_time = get_trigger_time(kBodyDetectOffOnTestData,
-					kBodyDetectOffOnTestDataLength,
-					BODY_DETECTION_ON_BODY);
-	/* It should enter on-body state in 3 seconds */
-	TEST_ASSERT(trigger_time >= 0 && trigger_time < 3 * window_size);
-
-	/* OnOff test */
-	cprints(CC_ACCEL, "start On to Off test");
-	trigger_time = get_trigger_time(kBodyDetectOnOffTestData,
-					kBodyDetectOnOffTestDataLength,
-					BODY_DETECTION_OFF_BODY);
-	/* It should enter off-body state between 15 to 20 seconds */
-	TEST_ASSERT(15 * window_size <= trigger_time &&
-		    trigger_time < 20 * window_size);
-
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_body_detect);
-
-	test_print_result();
-}
diff --git a/test/body_detection.tasklist b/test/body_detection.tasklist
deleted file mode 100644
index 95a30e9973..0000000000
--- a/test/body_detection.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  \
-  TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/body_detection_data_literals.c b/test/body_detection_data_literals.c
deleted file mode 100644
index 96a0cc2f8f..0000000000
--- a/test/body_detection_data_literals.c
+++ /dev/null
@@ -1,6214 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "body_detection_test_data.h"
-
-const struct body_detect_test_data kBodyDetectOnBodyTestData[] = {
-	/*       x,		y,		z, action*/
-	{3.233367f,	1.968032f,	8.875299f,	0},
-	{3.190272f,	2.127247f,	9.054865f,	0},
-	{3.361457f,	2.057815f,	9.054865f,	0},
-	{3.377019f,	1.917754f,	9.093172f,	0},
-	{3.460816f,	1.817198f,	9.058456f,	0},
-	{3.500320f,	1.726218f,	8.900438f,	0},
-	{3.715799f,	1.363497f,	8.836992f,	0},
-	{3.883393f,	0.884657f,	8.832204f,	0},
-	{3.948036f,	0.577002f,	9.016558f,	0},
-	{3.600877f,	0.717063f,	9.200911f,	0},
-	{3.318361f,	0.854729f,	9.166195f,	0},
-	{3.272871f,	0.731428f,	9.149436f,	0},
-	{3.452436f,	0.250194f,	9.297876f,	0},
-	{3.817552f,	-0.353144f,	9.424768f,	0},
-	{3.828326f,	-0.495599f,	9.284708f,	0},
-	{3.312376f,	-0.040701f,	9.204502f,	0},
-	{3.049014f,	0.515950f,	9.223656f,	0},
-	{3.099292f,	0.980425f,	8.882483f,	0},
-	{3.153162f,	1.443703f,	8.154645f,	0},
-	{3.501518f,	1.487995f,	8.054089f,	0},
-	{4.235340f,	1.292868f,	8.480257f,	0},
-	{4.284421f,	1.511937f,	8.848964f,	0},
-	{3.988737f,	1.928528f,	9.149436f,	0},
-	{3.825932f,	2.076969f,	9.576800f,	0},
-	{3.903743f,	1.991974f,	10.133451f,	0},
-	{3.841494f,	2.000354f,	10.165773f,	0},
-	{3.706222f,	1.930922f,	9.649823f,	0},
-	{3.949233f,	1.614888f,	9.054865f,	0},
-	{4.237734f,	1.272517f,	8.625106f,	0},
-	{4.188653f,	1.134851f,	8.268370f,	0},
-	{4.242523f,	0.991199f,	8.091199f,	0},
-	{4.157528f,	0.970848f,	8.135491f,	0},
-	{3.951627f,	0.967257f,	8.353364f,	0},
-	{4.073731f,	0.994790f,	8.854949f,	0},
-	{3.840297f,	1.124077f,	9.249992f,	0},
-	{3.736149f,	1.142033f,	9.491806f,	0},
-	{3.809172f,	1.126471f,	9.651020f,	0},
-	{3.987540f,	1.173158f,	9.633064f,	0},
-	{4.237734f,	1.005564f,	9.467864f,	0},
-	{4.308363f,	0.939724f,	9.190137f,	0},
-	{4.367021f,	0.986410f,	9.021346f,	0},
-	{4.406525f,	1.033097f,	9.074018f,	0},
-	{4.185062f,	1.276109f,	9.235627f,	0},
-	{3.971978f,	1.363497f,	9.525325f,	0},
-	{4.031833f,	1.318007f,	10.833755f,	0},
-	{4.214989f,	1.144428f,	10.241191f,	0},
-	{4.808751f,	0.590170f,	9.690525f,	0},
-	{4.697421f,	0.372298f,	10.245979f,	0},
-	{4.490322f,	0.207098f,	9.682145f,	0},
-	{4.353853f,	0.494402f,	8.651442f,	0},
-	{3.981555f,	1.094149f,	8.230062f,	0},
-	{3.933671f,	1.310825f,	8.426387f,	0},
-	{4.107250f,	1.189917f,	9.068033f,	0},
-	{4.529827f,	0.888248f,	9.501383f,	0},
-	{4.699815f,	0.720654f,	9.765942f,	0},
-	{4.661508f,	0.647631f,	9.916777f,	0},
-	{4.627989f,	0.587776f,	9.925157f,	0},
-	{4.413708f,	0.587776f,	9.791081f,	0},
-	{4.369415f,	0.466869f,	9.840162f,	0},
-	{4.412511f,	0.335188f,	9.932339f,	0},
-	{4.234143f,	0.452504f,	9.502580f,	0},
-	{3.817552f,	1.055842f,	8.638274f,	0},
-	{3.130417f,	1.842337f,	7.748828f,	0},
-	{2.511516f,	2.430113f,	7.059299f,	0},
-	{2.267308f,	2.840718f,	6.742067f,	0},
-	{2.082954f,	3.129220f,	6.706154f,	0},
-	{1.653195f,	3.483561f,	6.813893f,	0},
-	{1.053448f,	3.797201f,	7.132322f,	0},
-	{0.333991f,	4.125207f,	7.364560f,	0},
-	{-0.039504f,	4.228158f,	8.018176f,	0},
-	{0.403423f,	3.726573f,	8.789108f,	0},
-	{1.179144f,	3.120840f,	9.289496f,	0},
-	{1.683123f,	2.905362f,	9.911988f,	0},
-	{1.442506f,	3.038240f,	10.551240f,	0},
-	{1.403001f,	2.936486f,	12.229574f,	0},
-	{1.601720f,	2.541443f,	14.815310f,	0},
-	{2.233789f,	2.037464f,	14.715951f,	0},
-	{2.664745f,	1.736992f,	12.216406f,	0},
-	{3.331529f,	1.385045f,	10.475822f,	0},
-	{3.337515f,	1.235407f,	9.133873f,	0},
-	{3.173512f,	1.292868f,	8.406036f,	0},
-	{3.201046f,	1.462856f,	8.306677f,	0},
-	{3.157950f,	1.595734f,	9.011769f,	0},
-	{2.759315f,	1.777694f,	10.049655f,	0},
-	{2.315192f,	2.105699f,	10.682920f,	0},
-	{2.063801f,	2.375046f,	10.832559f,	0},
-	{2.310403f,	2.485180f,	10.688907f,	0},
-	{2.553414f,	2.606087f,	10.153803f,	0},
-	{2.475603f,	2.731782f,	9.356534f,	0},
-	{2.710234f,	2.529472f,	9.297876f,	0},
-	{2.777272f,	2.193087f,	9.394841f,	0},
-	{2.938881f,	1.920148f,	9.531310f,	0},
-	{3.108869f,	1.635239f,	10.534480f,	0},
-	{3.187877f,	1.425746f,	10.899596f,	0},
-	{3.448845f,	1.331175f,	10.508144f,	0},
-	{3.606862f,	1.470039f,	9.440331f,	0},
-	{3.700236f,	1.162384f,	8.781926f,	0},
-	{3.713404f,	0.864306f,	8.845372f,	0},
-	{3.575738f,	0.404620f,	9.610319f,	0},
-	{3.495532f,	-0.130484f,	9.526522f,	0},
-	{3.403355f,	-0.411802f,	8.833401f,	0},
-	{3.203440f,	-0.380678f,	8.850161f,	0},
-	{2.822762f,	-0.191536f,	9.560040f,	0},
-	{2.488771f,	-0.459686f,	9.883258f,	0},
-	{3.065773f,	-0.764947f,	10.110707f,	0},
-	{1.993172f,	1.004367f,	9.798264f,	0},
-	{2.426522f,	1.732204f,	10.036487f,	0},
-	{3.213017f,	1.238999f,	10.182533f,	0},
-	{2.779666f,	2.394200f,	9.916777f,	0},
-	{3.187877f,	2.622846f,	9.593559f,	0},
-	{4.195836f,	1.867476f,	9.876076f,	0},
-	{3.720587f,	2.114079f,	9.998179f,	0},
-	{2.948457f,	2.766498f,	9.500186f,	0},
-	{3.869027f,	2.822762f,	9.572012f,	0},
-	{4.205412f,	2.656365f,	9.753971f,	0},
-	{4.151543f,	2.828747f,	9.751576f,	0},
-	{4.046198f,	2.905362f,	9.131479f,	0},
-	{3.915714f,	3.032254f,	8.237246f,	0},
-	{3.864239f,	3.126825f,	8.008599f,	0},
-	{3.466802f,	2.999933f,	8.634683f,	0},
-	{2.876631f,	2.902968f,	9.473849f,	0},
-	{2.329557f,	2.899376f,	10.187322f,	0},
-	{2.197876f,	3.608059f,	10.637431f,	0},
-	{2.357090f,	4.205412f,	10.235206f,	0},
-	{2.716220f,	4.076126f,	9.261963f,	0},
-	{3.520671f,	3.847480f,	8.461103f,	0},
-	{4.180274f,	3.879801f,	7.758405f,	0},
-	{4.691435f,	4.034227f,	7.019794f,	0},
-	{4.918884f,	3.915714f,	6.659468f,	0},
-	{4.722559f,	4.205412f,	6.113590f,	0},
-	{5.349840f,	4.169499f,	5.413286f,	0},
-	{6.423639f,	3.742135f,	5.009864f,	0},
-	{6.799528f,	3.581723f,	4.843467f,	0},
-	{6.915647f,	3.337515f,	4.921278f,	0},
-	{7.358574f,	3.173512f,	5.214568f,	0},
-	{7.584826f,	2.861069f,	5.182246f,	0},
-	{7.077255f,	2.771286f,	5.073310f,	0},
-	{7.192177f,	2.306812f,	5.501872f,	0},
-	{7.241258f,	2.145203f,	5.888535f,	0},
-	{7.599191f,	1.898601f,	6.099225f,	0},
-	{7.576446f,	2.138021f,	6.144714f,	0},
-	{7.465116f,	1.962047f,	6.021413f,	0},
-	{7.677002f,	1.740583f,	5.643129f,	0},
-	{7.966701f,	1.648407f,	4.964374f,	0},
-	{8.038527f,	1.636436f,	4.419693f,	0},
-	{8.176193f,	1.582566f,	4.183865f,	0},
-	{8.489834f,	1.460462f,	4.319137f,	0},
-	{8.804670f,	1.314416f,	4.444832f,	0},
-	{8.803473f,	1.308430f,	4.492716f,	0},
-	{8.580813f,	1.392227f,	4.501096f,	0},
-	{8.056483f,	1.595734f,	4.428073f,	0},
-	{8.418008f,	1.316810f,	4.600455f,	0},
-	{8.826219f,	1.170764f,	4.411314f,	0},
-	{8.652639f,	1.201888f,	3.910926f,	0},
-	{8.285130f,	0.927753f,	3.752909f,	0},
-	{8.475469f,	1.027112f,	3.569752f,	0},
-	{9.009375f,	0.708683f,	3.605665f,	0},
-	{8.797488f,	0.600944f,	3.107672f,	0},
-	{8.864526f,	0.620098f,	2.863463f,	0},
-	{8.833401f,	0.214281f,	2.640803f,	0},
-	{9.212882f,	0.150835f,	2.487574f,	0},
-	{9.308650f,	0.226252f,	2.375046f,	0},
-	{8.869314f,	0.094571f,	2.142809f,	0},
-	{9.208094f,	0.002394f,	2.132035f,	0},
-	{9.100354f,	0.015562f,	2.367864f,	0},
-	{8.973462f,	-0.011971f,	2.602495f,	0},
-	{8.872906f,	0.000000f,	2.564188f,	0},
-	{8.883679f,	0.092177f,	2.452858f,	0},
-	{8.857343f,	0.241814f,	2.480391f,	0},
-	{8.919592f,	0.371101f,	2.612072f,	0},
-	{9.002192f,	0.483628f,	2.536655f,	0},
-	{9.056062f,	0.521936f,	2.335542f,	0},
-	{9.023740f,	0.572214f,	2.012325f,	0},
-	{9.085989f,	0.592565f,	1.854308f,	0},
-	{9.127888f,	0.505176f,	1.783679f,	0},
-	{8.968674f,	0.653617f,	1.787270f,	0},
-	{8.872906f,	0.650025f,	1.867476f,	0},
-	{8.798685f,	0.628478f,	2.148795f,	0},
-	{8.841781f,	0.530315f,	2.687490f,	0},
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-	{13.658912f,	-2.050632f,	2.142809f,	0},
-	{13.063952f,	-2.145203f,	-0.293290f,	0},
-	{9.628276f,	-1.520317f,	-2.880223f,	0},
-	{6.360192f,	-1.479616f,	-3.886984f,	0},
-	{5.079296f,	-1.917754f,	-2.090137f,	0},
-	{6.202175f,	-3.551796f,	-0.855927f,	0},
-	{7.969095f,	-4.886562f,	-0.975637f,	0},
-	{11.101906f,	-4.876986f,	0.645237f,	0},
-	{11.766296f,	-4.067746f,	0.531512f,	0},
-	{10.569196f,	-3.503912f,	-0.644040f,	0},
-	{10.237599f,	-3.076547f,	-0.447715f,	0},
-	{9.629473f,	-2.752133f,	-0.193930f,	0},
-	{8.340196f,	-1.911769f,	-0.742202f,	0},
-	{7.272383f,	-1.003170f,	-1.213859f,	0},
-	{6.823470f,	-0.739808f,	-1.057039f,	0},
-	{7.050919f,	-0.673967f,	-0.834379f,	0},
-	{7.595600f,	-0.442927f,	-0.532710f,	0},
-	{8.060075f,	-0.168791f,	-0.527921f,	0},
-	{8.573630f,	0.094571f,	-1.207874f,	0},
-	{8.899241f,	0.466869f,	-1.898601f,	0},
-	{9.060850f,	0.805648f,	-1.408987f,	0},
-	{9.222459f,	0.831985f,	-0.489614f,	0},
-	{9.290693f,	0.647631f,	0.099359f,	0},
-	{8.882483f,	0.517147f,	-0.029928f,	0},
-	{8.628697f,	0.389058f,	-0.817619f,	0},
-	{9.248795f,	0.234632f,	-1.046265f,	0},
-	{9.690525f,	-0.081403f,	-1.126471f,	0},
-	{10.071202f,	-0.231040f,	-0.632069f,	0},
-	{10.299849f,	-0.039504f,	0.476446f,	0},
-	{10.965436f,	0.278924f,	0.920570f,	0},
-	{11.526876f,	0.132878f,	-0.335188f,	0},
-	{11.572366f,	0.118513f,	-0.995987f,	0},
-	{12.087119f,	0.074220f,	0.064643f,	0},
-	{14.025224f,	-0.268150f,	0.715866f,	0},
-	{13.812140f,	-0.075417f,	2.175131f,	0},
-	{10.393223f,	0.955286f,	4.447227f,	0},
-	{5.740095f,	2.165554f,	5.378571f,	0},
-	{2.682701f,	2.470814f,	4.266465f,	0},
-	{2.267308f,	1.452082f,	2.970005f,	0},
-	{5.784388f,	-0.737414f,	2.178722f,	0},
-	{8.700523f,	-2.176328f,	0.712274f,	0},
-	{8.658625f,	-2.545035f,	-1.139639f,	0},
-	{8.984236f,	-3.094504f,	-0.059855f,	0},
-	{10.274710f,	-4.108448f,	2.123656f,	0},
-	{11.112679f,	-5.146333f,	2.748542f,	0},
-	{12.083528f,	-5.299562f,	-0.111330f,	0},
-	{11.859670f,	-3.488349f,	-2.300826f,	0},
-	{10.259148f,	-1.679531f,	-0.063446f,	0},
-	{8.656230f,	-1.307233f,	1.798044f,	0},
-	{7.996628f,	-1.447294f,	1.592143f,	0},
-	{8.142674f,	-1.909375f,	0.881066f,	0},
-	{8.282735f,	-2.118867f,	0.978031f,	0},
-	{8.382094f,	-1.970427f,	1.248575f,	0},
-	{8.866920f,	-1.735795f,	0.386663f,	0},
-	{9.623487f,	-1.595734f,	-0.269348f,	0},
-	{9.806643f,	-1.525105f,	-0.345962f,	0},
-	{9.609122f,	-1.367088f,	0.299275f,	0},
-	{9.714467f,	-1.388636f,	1.693897f,	0},
-	{9.576800f,	-1.092952f,	2.396594f,	0},
-	{9.296679f,	-1.480813f,	2.565385f,	0},
-	{9.323015f,	-0.742202f,	2.341528f,	0},
-	{9.384068f,	-1.109712f,	1.960850f,	0},
-	{9.868893f,	-1.590946f,	2.421733f,	0},
-	{10.109509f,	-1.939302f,	2.955640f,	0},
-	{9.973041f,	-2.006340f,	3.324347f,	0},
-	{9.859316f,	-1.581369f,	3.942050f,	0},
-	{9.793475f,	-0.999579f,	3.818749f,	0},
-	{8.820233f,	-0.578199f,	2.885011f,	0},
-	{7.404064f,	-0.547075f,	1.671152f,	0},
-	{6.730096f,	-0.906205f,	0.976834f,	0},
-	{8.153448f,	-2.236183f,	0.503979f,	0},
-	{9.867696f,	-4.234143f,	-0.254982f,	0},
-	{7.984657f,	-2.888602f,	-1.261743f,	0},
-	{9.093172f,	-3.695448f,	-2.171540f,	0},
-	{9.166195f,	-3.958810f,	-1.365891f,	0},
-	{9.483426f,	-4.307166f,	-1.432929f,	0},
-	{9.564829f,	-4.777626f,	-2.000354f,	0},
-	{9.548070f,	-5.154713f,	-2.106896f,	0},
-	{9.175772f,	-5.427651f,	-1.608902f,	0},
-	{8.127112f,	-6.010639f,	-1.829169f,	0},
-	{8.129506f,	-6.432018f,	-1.207874f,	0},
-	{7.790727f,	-5.821497f,	0.189142f,	0},
-	{7.073664f,	-4.104856f,	2.110487f,	0},
-	{7.091620f,	-3.636790f,	1.745372f,	0},
-	{7.758405f,	-3.837903f,	0.458489f,	0},
-	{8.832204f,	-3.739741f,	0.357933f,	0},
-	{9.786293f,	-3.177104f,	0.160411f,	0},
-	{9.618699f,	-2.337936f,	-0.683544f,	0},
-	{9.124296f,	-1.669955f,	-0.986410f,	0},
-	{8.815445f,	-1.297656f,	0.074220f,	0},
-	{8.663413f,	-1.192312f,	0.752976f,	0},
-	{8.526943f,	-1.224633f,	0.095768f,	0},
-	{8.671793f,	-1.508346f,	-0.044293f,	0},
-	{9.041697f,	-1.966835f,	-1.302445f,	0},
-	{9.320621f,	-2.434901f,	-0.640449f,	0},
-	{9.319424f,	-2.719811f,	-0.933738f,	0},
-	{9.598348f,	-2.252942f,	0.096965f,	0},
-	{9.272737f,	-2.086545f,	-0.335188f,	0},
-	{9.397235f,	-1.977609f,	-0.829590f,	0},
-	{9.585180f,	-1.861491f,	-0.963666f,	0},
-	{9.563632f,	-1.543062f,	-1.194706f,	0},
-	{9.265554f,	-1.262941f,	-1.276109f,	0},
-	{8.941140f,	-0.998381f,	-1.148019f,	0},
-	{8.711297f,	-0.948103f,	-1.108515f,	0},
-	{8.803473f,	-1.259349f,	-1.027112f,	0},
-	{9.475047f,	-2.545035f,	-0.591367f,	0},
-	{10.941494f,	-4.028242f,	-0.374692f,	0},
-	{11.295835f,	-3.961204f,	0.489614f,	0},
-	{9.697707f,	-2.606087f,	1.587355f,	0},
-	{8.414416f,	-2.354696f,	1.309627f,	0},
-	{8.408431f,	-3.039437f,	0.598550f,	0},
-	{8.759181f,	-3.227382f,	0.460884f,	0},
-	{9.191334f,	-3.215411f,	0.717063f,	0},
-	{9.106340f,	-3.286040f,	-1.228225f,	0},
-	{9.215276f,	-3.016692f,	-0.532710f,	0},
-	{9.226050f,	-2.573765f,	1.215057f,	0},
-	{9.278723f,	-2.743753f,	0.444124f,	0},
-	{9.779110f,	-3.204637f,	1.349132f,	0},
-	{9.914383f,	-3.223790f,	1.940499f,	0},
-	{9.907200f,	-2.806002f,	1.668757f,	0},
-	{10.375266f,	-2.416945f,	2.098516f,	0},
-	{11.027685f,	-2.161963f,	2.414551f,	0},
-	{11.603491f,	-1.948879f,	2.486377f,	0},
-	{11.531665f,	-1.472433f,	2.813185f,	0},
-	{10.983393f,	-0.723048f,	2.525881f,	0},
-	{9.938325f,	0.086191f,	2.130838f,	0},
-	{8.816642f,	0.365116f,	2.731782f,	0},
-	{10.491385f,	0.019154f,	3.318361f,	0},
-	{10.913961f,	-0.289698f,	4.115630f,	0},
-	{9.964661f,	0.154426f,	4.765655f,	0},
-	{7.896072f,	1.101332f,	4.291604f,	0},
-	{7.783545f,	1.666363f,	4.158726f,	0},
-	{8.256399f,	1.159990f,	4.963177f,	0},
-	{8.441950f,	0.727837f,	5.633553f,	0},
-	{7.973883f,	0.981622f,	5.418075f,	0},
-	{7.131125f,	1.492784f,	4.759670f,	0},
-	{7.067678f,	1.640027f,	4.987119f,	0},
-	{7.246047f,	1.323993f,	5.380965f,	0},
-	{7.788333f,	1.154004f,	5.783190f,	0},
-	{8.256399f,	1.544259f,	6.980290f,	0},
-	{8.076834f,	2.169145f,	7.654258f,	0},
-	{7.649469f,	2.182313f,	7.368151f,	0},
-	{7.462722f,	2.094925f,	6.817485f,	0},
-	{6.956348f,	1.817198f,	6.009442f,	0},
-	{6.156685f,	1.295262f,	5.595245f,	0},
-	{5.171472f,	1.101332f,	5.043383f,	0},
-	{4.614820f,	1.007958f,	4.921278f,	0},
-	{4.693829f,	0.915781f,	5.402513f,	0},
-	{4.863817f,	1.090558f,	5.463564f,	0},
-	{4.620806f,	1.468842f,	5.919660f,	0},
-	{4.741713f,	1.361103f,	6.609190f,	0},
-	{4.047395f,	1.677137f,	6.482296f,	0},
-	{4.094082f,	1.859096f,	6.527786f,	0},
-	{4.349064f,	1.829169f,	6.309914f,	0},
-	{4.477154f,	1.816001f,	6.591233f,	0},
-	{4.513067f,	1.195903f,	7.651864f,	0},
-	{5.130771f,	0.706289f,	8.787911f,	0},
-	{5.143939f,	0.804451f,	8.456315f,	0},
-	{4.619609f,	0.244208f,	7.931985f,	0},
-	{3.963598f,	-0.852335f,	8.146266f,	0},
-	{4.163514f,	-1.314416f,	8.972264f,	0},
-	{4.601653f,	-1.395819f,	9.185349f,	0},
-	{4.854240f,	-1.686714f,	8.943534f,	0},
-	{4.542994f,	-2.023099f,	8.414416f,	0},
-	{3.835509f,	-2.602495f,	8.085214f,	0},
-	{2.978385f,	-2.853886f,	8.039723f,	0},
-	{2.686292f,	-2.522290f,	7.716507f,	0},
-	{2.425325f,	-2.989159f,	10.263936f,	0},
-	{1.680728f,	-3.276463f,	12.568354f,	0},
-	{1.449688f,	-2.462435f,	9.834177f,	0},
-	{1.904586f,	-2.296038f,	8.819036f,	0},
-	{2.072180f,	-2.254139f,	9.337380f,	0},
-	{2.197876f,	-2.144006f,	9.494201f,	0},
-	{2.105699f,	-1.899798f,	9.169786f,	0},
-	{1.717839f,	-1.751357f,	9.096764f,	0},
-	{1.574187f,	-1.813607f,	9.458287f,	0},
-	{1.502361f,	-1.717839f,	9.576800f,	0},
-	{1.379059f,	-1.528697f,	9.473849f,	0},
-	{1.168370f,	-1.182735f,	9.206897f,	0},
-	{1.060631f,	-1.138442f,	9.701299f,	0},
-	{0.893037f,	-1.142033f,	10.007756f,	0},
-	{0.729034f,	-1.097741f,	10.362098f,	0},
-	{0.847547f,	-1.270123f,	11.415545f,	0},
-	{0.700303f,	-1.437717f,	11.802209f,	0},
-	{0.657208f,	-0.940921f,	10.297455f,	0},
-	{0.820014f,	-0.262165f,	8.865723f,	0},
-	{1.120486f,	-0.100556f,	9.303862f,	0},
-	{1.000776f,	-0.172382f,	10.194504f,	0},
-	{0.691924f,	0.026336f,	8.984236f,	0},
-	{0.712274f,	0.058658f,	8.265976f,	0},
-	{0.530315f,	-0.462081f,	10.773900f,	0},
-	{0.463278f,	-0.685938f,	10.289075f,	0},
-	{0.442927f,	-0.518344f,	7.893678f,	0},
-	{0.445321f,	-0.438139f,	7.972686f,	0},
-	{0.378284f,	-0.450110f,	8.655033f,	0},
-	{0.043096f,	0.015562f,	8.980644f,	0},
-	{0.220266f,	0.984016f,	9.639050f,	0},
-	{0.154426f,	1.146822f,	9.488214f,	0},
-	{-0.119710f,	1.325190f,	9.168590f,	0},
-	{-0.130484f,	1.334767f,	9.746788f,	0},
-	{-0.025139f,	1.310825f,	10.338156f,	0},
-	{0.028730f,	1.616085f,	9.712072f,	0},
-	{0.044293f,	1.892615f,	8.583207f,	0},
-	{0.069432f,	1.480813f,	8.564054f,	0},
-	{0.033519f,	1.243787f,	8.768758f,	0},
-	{0.373495f,	1.514332f,	8.633486f,	0},
-	{0.353144f,	1.561018f,	8.446738f,	0},
-	{0.129287f,	1.313219f,	8.616726f,	0},
-	{-0.028730f,	0.976834f,	9.123099f,	0},
-	{-0.076614f,	0.966060f,	9.351746f,	0},
-	{-0.161609f,	1.165975f,	8.965082f,	0},
-	{-0.343568f,	1.641224f,	8.194150f,	0},
-	{-0.442927f,	1.661575f,	8.437161f,	0},
-	{-0.363918f,	1.365891f,	9.854527f,	0},
-	{-0.282516f,	1.326387f,	10.666162f,	0},
-	{-0.314837f,	1.443703f,	10.433924f,	0},
-	{-0.644040f,	1.332372f,	9.327804f,	0},
-	{-0.999579f,	1.479616f,	8.036133f,	0},
-	{-0.799663f,	1.452082f,	8.346182f,	0},
-	{-0.858321f,	1.567004f,	9.868893f,	0},
-	{-0.938526f,	1.495178f,	11.599899f,	0},
-	{-1.193509f,	1.498769f,	11.905160f,	0},
-	{-1.556230f,	1.338358f,	10.947480f,	0},
-	{-1.557427f,	1.256955f,	11.003743f,	0},
-	{-1.413775f,	1.060631f,	11.848896f,	0},
-	{-1.280897f,	0.922964f,	12.215209f,	0},
-	{-1.132457f,	0.927753f,	11.399983f,	0},
-	{-1.037886f,	0.881066f,	10.413573f,	0},
-	{-0.605733f,	0.897825f,	10.074794f,	0},
-	{-0.149638f,	0.872686f,	10.181335f,	0},
-	{0.278924f,	0.933738f,	10.765521f,	0},
-	{0.741005f,	1.137245f,	10.898398f,	0},
-	{1.114500f,	1.398213f,	10.672147f,	0},
-	{1.337161f,	1.841140f,	11.609476f,	0},
-	{1.916557f,	1.922543f,	13.679262f,	0},
-	{2.594116f,	1.768117f,	13.814534f,	0},
-	{3.088518f,	2.280476f,	12.144580f,	0},
-	{3.426100f,	2.173934f,	11.726792f,	0},
-	{3.564964f,	1.717839f,	11.662148f,	0},
-	{3.779245f,	1.653195f,	11.219221f,	0},
-	{3.823538f,	1.709459f,	10.377660f,	0},
-};
-
-const size_t kBodyDetectOnBodyTestDataLength =
-	ARRAY_SIZE(kBodyDetectOnBodyTestData);
-
-const struct body_detect_test_data kBodyDetectOffOnTestData[] = {
-	{-0.269348,	0.220266,	10.030501,	0},
-	{-0.259771,	0.216675,	10.113101,	0},
-	{-0.253785,	0.213084,	10.096342,	0},
-	{-0.262165,	0.201113,	10.098736,	0},
-	{-0.257377,	0.210690,	10.093947,	0},
-	{-0.253785,	0.202310,	10.096342,	0},
-	{-0.257377,	0.213084,	10.113101,	0},
-	{-0.257377,	0.221464,	10.096342,	0},
-	{-0.262165,	0.217872,	10.115496,	0},
-	{-0.258574,	0.219069,	10.102327,	0},
-	{-0.275333,	0.205901,	10.123875,	0},
-	{-0.262165,	0.209493,	10.085567,	0},
-	{-0.271742,	0.209493,	10.110707,	0},
-	{-0.275333,	0.220266,	10.096342,	0},
-	{-0.251391,	0.210690,	10.097539,	0},
-	{-0.262165,	0.210690,	10.090356,	0},
-	{-0.268150,	0.208295,	10.108313,	0},
-	{-0.258574,	0.210690,	10.098736,	0},
-	{-0.270545,	0.219069,	10.097539,	0},
-	{-0.263362,	0.211887,	10.102327,	0},
-	{-0.264559,	0.211887,	10.097539,	0},
-	{-0.262165,	0.204704,	10.090356,	0},
-	{-0.246603,	0.203507,	10.089159,	0},
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-	{5.723335,	0.399831,	8.002614,	0},
-	{5.712561,	0.343568,	7.995431,	0},
-	{5.741292,	0.323217,	8.110353,	0},
-	{5.766431,	0.349553,	8.237246,	0},
-	{5.704182,	0.367510,	8.276750,	0},
-	{5.651509,	0.348356,	8.161828,	0},
-	{5.655100,	0.367510,	7.977475,	0},
-	{5.770022,	0.269348,	8.037330,	0},
-	{5.765234,	0.149638,	8.125915,	0},
-	{5.671860,	0.073023,	7.973883,	0},
-	{5.667071,	0.105345,	7.836217,	0},
-	{5.662283,	0.092177,	7.824246,	0},
-	{5.702984,	0.031125,	7.970292,	0},
-	{5.731715,	-0.005986,	8.169010,	0},
-	{5.705379,	-0.038307,	8.178588,	0},
-	{5.635947,	-0.082600,	8.060075,	0},
-	{5.614399,	-0.087388,	7.846991,	0},
-	{5.607216,	-0.051475,	7.807487,	0},
-	{5.610808,	-0.033519,	7.864947,	0},
-	{5.594049,	0.014365,	7.959518,	0},
-	{5.595245,	0.070629,	8.085214,	0},
-	{5.577289,	0.046687,	8.267173,	0},
-	{5.512646,	-0.061052,	8.195347,	0},
-	{5.414484,	-0.068235,	7.988248,	0},
-	{5.358220,	0.023942,	7.862553,	0},
-	{5.412089,	0.094571,	7.925999,	0},
-	{5.420469,	0.159214,	8.106761,	0},
-	{5.276817,	0.208295,	8.341393,	0},
-	{5.264846,	0.239420,	8.215697,	0},
-	{5.281605,	0.105345,	8.564054,	0},
-	{5.311533,	-0.020351,	8.683764,	0},
-	{5.209779,	0.087388,	8.489834,	0},
-	{5.149924,	0.135272,	8.765166,	0},
-	{5.169078,	0.017957,	9.282313,	0},
-	{5.274423,	-0.105345,	9.628276,	0},
-	{5.270832,	-0.059855,	9.247598,	0},
-	{5.166684,	0.098162,	8.629894,	0},
-	{5.128376,	0.126893,	8.294706,	0},
-	{5.119997,	0.088585,	8.373714,	0},
-	{5.146333,	0.090980,	8.540112,	0},
-	{5.112814,	0.226252,	8.293509,	0},
-	{5.086478,	0.238223,	8.079228,	0},
-	{5.076901,	0.137667,	8.086411,	0},
-	{5.064930,	0.064643,	8.396460,	0},
-	{5.090069,	0.101754,	8.791503,	0},
-	{5.090069,	0.272939,	9.018951,	0},
-	{5.106829,	0.399831,	8.947125,	0},
-	{5.129574,	0.401029,	8.738831,	0},
-	{5.143939,	0.233435,	8.713691,	0},
-	{5.165487,	0.124498,	8.570039,	0},
-	{5.170275,	0.147243,	8.276750,	0},
-	{5.114011,	0.207098,	7.818260,	0},
-	{5.033806,	0.308852,	7.491452,	0},
-	{5.043383,	0.314837,	7.789530,	0},
-	{5.061339,	0.219069,	8.386883,	0},
-	{5.069719,	0.137667,	8.644259,	0},
-	{5.058945,	0.147243,	8.481454,	0},
-	{5.007470,	0.186748,	8.107959,	0},
-	{4.957191,	0.214281,	8.024161,	0},
-	{5.048171,	0.130484,	8.451527,	0},
-	{5.088872,	0.058658,	8.924380,	0},
-	{5.104434,	-0.016759,	9.154224,	0},
-	{5.117603,	-0.027533,	8.935155,	0},
-	{5.018243,	0.071826,	8.637076,	0},
-	{4.983528,	0.090980,	8.604755,	0},
-	{5.019441,	0.026336,	8.650245,	0},
-	{5.030214,	-0.013168,	8.646653,	0},
-	{4.939235,	-0.026336,	8.565250,	0},
-	{4.879380,	-0.089783,	8.562857,	0},
-	{4.832693,	-0.186748,	8.906425,	0},
-	{4.851846,	-0.294487,	9.361322,	0},
-	{4.910504,	-0.284910,	9.572012,	0},
-	{4.920081,	-0.166397,	9.233232,	0},
-	{4.865015,	-0.051475,	8.621514,	0},
-	{4.821919,	-0.007183,	8.482651,	0},
-	{4.851846,	-0.021548,	8.792700,	0},
-	{4.916490,	-0.056264,	9.081201,	0},
-	{4.939235,	-0.034716,	8.680172,	0},
-	{4.878182,	0.039504,	8.130703,	0},
-	{4.825510,	0.070629,	8.079228,	0},
-	{4.854240,	0.033519,	8.445540,	0},
-	{4.932052,	-0.016759,	8.767561,	0},
-	{4.988316,	-0.080206,	8.864526,	0},
-	{5.024229,	-0.152032,	8.710100,	0},
-	{5.026623,	-0.175974,	8.593981,	0},
-	{5.011061,	-0.119710,	8.465892,	0},
-	{5.051762,	-0.058658,	8.503001,	0},
-	{5.104434,	0.028730,	8.389277,	0},
-	{5.108026,	0.174777,	8.304283,	0},
-	{5.121194,	0.207098,	8.368926,	0},
-	{5.137953,	0.177171,	8.186967,	0},
-	{5.123588,	0.141258,	8.036133,	0},
-	{5.098449,	0.186748,	8.031344,	0},
-	{5.036200,	0.240617,	8.049300,	0},
-	{4.977542,	0.316034,	8.190558,	0},
-	{4.978739,	0.294487,	8.428782,	0},
-	{5.046974,	0.195127,	8.704114,	0},
-	{5.042185,	0.211887,	8.719677,	0},
-	{4.927264,	0.299275,	8.538915,	0},
-	{4.918884,	0.241814,	8.495819,	0},
-	{4.897336,	0.189142,	8.492228,	0},
-	{4.878182,	0.237026,	8.601164,	0},
-	{4.818327,	0.262165,	8.705312,	0},
-	{4.871000,	0.172382,	8.791503,	0},
-	{4.924870,	0.119710,	8.872906,	0},
-	{4.873394,	0.243011,	8.825022,	0},
-	{4.832693,	0.408211,	8.659822,	0},
-	{4.838678,	0.367510,	8.619121,	0},
-	{4.904519,	0.169988,	8.809459,	0},
-	{4.926067,	0.071826,	9.058456,	0},
-	{4.940432,	0.058658,	8.823824,	0},
-	{4.930855,	0.167594,	8.331817,	0},
-	{4.918884,	0.266953,	8.265976,	0},
-	{4.941629,	0.207098,	8.900438,	0},
-	{4.957191,	0.129287,	9.339774,	0},
-	{4.915293,	0.180762,	9.089581,	0},
-	{4.930855,	0.190339,	8.826219,	0},
-	{5.080492,	0.038307,	8.766363,	0},
-	{5.204991,	-0.108936,	8.631091,	0},
-	{5.202597,	-0.047884,	8.157040,	0},
-	{5.157107,	0.095768,	7.870933,	0},
-	{5.164289,	0.168791,	8.019373,	0},
-	{5.199006,	0.167594,	8.428782,	0},
-	{5.215765,	0.180762,	8.804670,	0},
-	{5.201400,	0.278924,	8.614332,	0},
-	{5.171472,	0.433350,	8.225274,	0},
-	{5.199006,	0.466869,	8.068454,	0},
-	{5.245692,	0.434547,	8.081622,	0},
-	{5.252875,	0.493205,	8.092396,	0},
-	{5.194217,	0.633266,	8.359349,	0},
-	{5.155910,	0.772130,	8.494622,	0},
-	{5.196611,	0.809240,	8.324634,	0},
-	{5.245692,	0.724246,	8.206120,	0},
-	{5.252875,	0.677559,	8.295903,	0},
-	{5.234919,	0.689530,	8.449132,	0},
-	{5.256466,	0.666785,	8.635880,	0},
-	{5.276817,	0.672770,	8.653836,	0},
-	{5.300759,	0.682347,	8.694537,	0},
-	{5.352234,	0.640449,	8.677778,	0},
-	{5.373782,	0.659602,	8.445540,	0},
-	{5.371388,	0.752976,	8.093594,	0},
-	{5.348643,	0.889445,	7.916422,	0},
-	{5.337869,	0.974439,	8.097184,	0},
-	{5.346249,	0.991199,	8.227669,	0},
-	{5.382162,	0.978031,	8.289918,	0},
-	{5.436031,	0.922964,	8.264779,	0},
-	{5.408498,	0.940921,	8.136689,	0},
-	{5.376176,	0.939724,	8.165420,	0},
-	{5.364205,	0.924161,	8.331817,	0},
-	{5.351037,	0.873883,	8.446738,	0},
-	{5.334278,	0.855927,	8.334210,	0},
-	{5.292379,	0.861912,	8.178588,	0},
-	{5.298365,	0.858321,	8.146266,	0},
-	{5.319912,	0.841561,	8.136689,	0},
-	{5.353431,	0.793677,	8.121126,	0},
-	{5.378571,	0.736217,	8.218092,	0},
-	{5.397724,	0.694318,	8.354561,	0},
-	{5.367796,	0.709880,	8.420402,	0},
-	{5.335475,	0.749385,	8.528141,	0},
-	{5.313927,	0.818816,	8.493424,	0},
-	{5.306745,	0.889445,	8.315057,	0},
-	{5.333081,	0.893037,	8.216895,	0},
-	{5.345052,	0.899022,	8.208515,	0},
-	{5.348643,	0.920570,	8.322240,	0},
-	{5.346249,	0.955286,	8.494622,	0},
-	{5.325898,	0.984016,	8.801080,	0},
-	{5.355825,	0.998381,	9.132676,	0},
-	{5.388147,	0.967257,	9.349351,	0},
-	{5.489901,	0.889445,	9.421177,	0},
-	{5.553347,	0.900219,	9.010572,	0},
-	{5.532996,	1.004367,	8.176193,	0},
-	{5.509054,	1.109712,	7.471101,	0},
-	{5.504266,	1.175552,	7.400473,	0},
-	{5.482718,	1.159990,	7.684185,	0},
-	{5.443214,	1.177946,	8.027753,	0},
-	{5.426455,	1.201888,	8.292312,	0},
-	{5.492295,	1.139639,	8.359349,	0},
-	{5.532996,	1.092952,	8.263581,	0},
-	{5.522223,	1.072602,	7.959518,	0},
-	{5.504266,	1.033097,	7.606374,	0},
-	{5.524617,	0.958877,	7.461524,	0},
-	{5.505463,	0.876277,	7.580038,	0},
-	{5.458776,	0.823605,	7.835020,	0},
-	{5.432440,	0.756567,	8.016979,	0},
-	{5.386950,	0.760159,	8.174996,	0},
-	{5.400118,	0.748188,	8.362941,	0},
-	{5.449199,	0.687135,	8.324634,	0},
-	{5.426455,	0.701501,	7.993037,	0},
-	{5.407301,	0.751779,	7.637498,	0},
-	{5.455185,	0.737414,	7.868538,	0},
-	{5.456382,	0.735019,	8.342590,	0},
-	{5.409695,	0.805648,	8.420402,	0},
-	{5.379767,	0.878671,	8.323437,	0},
-	{5.433637,	0.877474,	8.230062,	0},
-	{5.477930,	0.864306,	8.248019,	0},
-	{5.511448,	0.831985,	8.370124,	0},
-	{5.525814,	0.817619,	8.439555,	0},
-	{5.498281,	0.797269,	8.486242,	0},
-	{5.485112,	0.806845,	8.465892,	0},
-	{5.480324,	0.830787,	8.364138,	0},
-	{5.485112,	0.831985,	8.337802,	0},
-	{5.487506,	0.854729,	8.340196,	0},
-	{5.434834,	0.873883,	8.372518,	0},
-	{5.397724,	0.854729,	8.346182,	0},
-	{5.392936,	0.869095,	8.216895,	0},
-	{5.373782,	0.891840,	8.018176,	0},
-	{5.401315,	0.872686,	7.902057,	0},
-	{5.448002,	0.833182,	7.929591,	0},
-	{5.425257,	0.835576,	8.146266,	0},
-	{5.413286,	0.849941,	8.409628,	0},
-	{5.421666,	0.837970,	8.495819,	0},
-	{5.434834,	0.802057,	8.402445,	0},
-	{5.456382,	0.772130,	8.238442,	0},
-	{5.482718,	0.749385,	8.231260,	0},
-	{5.497083,	0.744596,	8.304283,	0},
-	{5.479127,	0.781706,	8.298298,	0},
-	{5.432440,	0.882263,	8.295903,	0},
-	{5.404907,	0.958877,	8.201332,	0},
-	{5.397724,	0.944512,	8.110353,	0},
-	{5.394133,	0.920570,	8.216895,	0},
-	{5.437228,	0.899022,	8.328225,	0},
-	{5.474339,	0.902613,	8.413219,	0},
-	{5.529405,	0.889445,	8.447935,	0},
-	{5.590457,	0.873883,	8.355759,	0},
-	{5.612005,	0.877474,	8.292312,	0},
-	{5.613202,	0.870292,	8.209712,	0},
-	{5.585669,	0.913387,	8.025358,	0},
-	{5.511448,	0.933738,	7.991840,	0},
-	{5.475535,	0.949300,	8.026556,	0},
-	{5.463564,	0.999579,	8.031344,	0},
-	{5.469550,	0.994790,	7.918817,	0},
-	{5.504266,	0.974439,	7.881707,	0},
-	{5.546165,	0.991199,	7.955927,	0},
-	{5.553347,	0.997184,	8.128309,	0},
-	{5.567712,	1.010352,	8.230062,	0},
-	{5.553347,	1.048660,	8.279144,	0},
-	{5.578486,	1.033097,	8.268370,	0},
-	{5.571303,	1.016338,	8.101973,	0},
-	{5.543770,	0.985213,	7.933182,	0},
-	{5.550953,	0.909796,	7.971489,	0},
-	{5.547361,	0.855927,	7.951138,	0},
-	{5.540179,	0.840364,	7.978672,	0},
-	{5.523419,	0.848744,	8.152251,	0},
-	{5.491098,	0.853532,	8.298298,	0},
-	{5.420469,	0.901416,	8.333014,	0},
-	{5.403709,	0.937329,	8.419205,	0},
-	{5.440820,	0.964863,	8.601164,	0},
-	{5.465959,	0.991199,	8.426387,	0},
-	{5.457579,	1.051054,	8.109156,	0},
-	{5.437228,	1.104923,	7.977475,	0},
-	{5.428849,	1.102529,	8.027753,	0},
-	{5.433637,	1.090558,	8.195347,	0},
-	{5.432440,	1.100135,	8.276750,	0},
-	{5.461170,	1.134851,	8.309072,	0},
-	{5.511448,	1.119289,	8.292312,	0},
-	{5.540179,	1.089361,	8.316254,	0},
-	{5.518631,	1.103726,	8.358152,	0},
-	{5.528208,	1.112106,	8.343787,	0},
-	{5.527011,	1.094149,	8.257596,	0},
-	{5.495886,	1.116894,	8.154645,	0},
-	{5.510252,	1.092952,	8.208515,	0},
-	{5.538982,	1.058236,	8.158237,	0},
-	{5.511448,	1.088164,	7.948744,	0},
-	{5.515040,	1.084573,	7.852976,	0},
-	{5.507857,	1.104923,	7.959518,	0},
-	{5.468353,	1.138442,	8.188165,	0},
-	{5.468353,	1.148019,	8.327028,	0},
-	{5.481521,	1.133654,	8.289918,	0},
-	{5.511448,	1.120486,	8.226472,	0},
-	{5.530602,	1.086967,	8.198938,	0},
-	{5.529405,	1.065419,	8.166616,	0},
-	{5.469550,	1.060631,	8.221684,	0},
-	{5.440820,	1.053448,	8.240837,	0},
-	{5.396527,	1.053448,	8.213304,	0},
-	{5.386950,	1.055842,	8.234851,	0},
-	{5.421666,	1.046265,	8.246822,	0},
-	{5.431243,	1.029506,	8.155843,	0},
-	{5.298365,	1.292868,	5.756854,	0},
-	{5.191823,	1.255758,	8.088805,	0},
-	{5.204991,	1.169567,	10.260345,	0}
-};
-
-const size_t kBodyDetectOffOnTestDataLength =
-	ARRAY_SIZE(kBodyDetectOffOnTestData);
-
-const struct body_detect_test_data kBodyDetectOnOffTestData[] = {
-	{-6.536166,	0.264559,	7.560884,	0},
-	{-6.253651,	0.108936,	8.167813,	0},
-	{-5.890929,	-0.029928,	8.061272,	0},
-	{-5.833468,	-0.045490,	8.250414,	0},
-	{-5.932828,	0.038307,	8.573630,	0},
-	{-5.995077,	0.104148,	8.634683,	0},
-	{-6.080071,	0.181959,	8.317451,	0},
-	{-6.069297,	0.177171,	8.151054,	0},
-	{-5.978318,	0.113724,	8.407233,	0},
-	{-5.895718,	0.033519,	8.592784,	0},
-	{-5.828680,	-0.022745,	8.299495,	0},
-	{-5.768825,	-0.070629,	7.958321,	0},
-	{-5.770022,	-0.089783,	8.028950,	0},
-	{-5.832272,	-0.074220,	8.360547,	0},
-	{-5.880156,	-0.067038,	8.488636,	0},
-	{-5.987895,	-0.017957,	8.342590,	0},
-	{-6.148306,	0.014365,	8.317451,	0},
-	{-6.337448,	0.102951,	8.492228,	0},
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-	{-0.248997,	0.075417,	10.137043,	0},
-	{-0.240617,	0.081403,	10.126269,	0},
-	{-0.225055,	0.075417,	10.117889,	0},
-	{-0.245406,	0.061052,	10.099933,	0},
-	{-0.229843,	0.071826,	10.133451,	0},
-	{-0.239420,	0.088585,	10.158591,	0},
-	{-0.251391,	0.079009,	10.111904,	0},
-	{-0.234632,	0.070629,	10.151408,	0},
-	{-0.232237,	0.068235,	10.127466,	0},
-	{-0.238223,	0.083797,	10.125072,	0},
-	{-0.240617,	0.083797,	10.104721,	0},
-	{-0.234632,	0.084994,	10.127466,	0},
-	{-0.243011,	0.068235,	10.098736,	0},
-	{-0.251391,	0.075417,	10.146620,	0},
-	{-0.257377,	0.082600,	10.117889,	0},
-	{-0.234632,	0.076614,	10.119086,	0},
-	{-0.244208,	0.080206,	10.132255,	0},
-	{-0.232237,	0.080206,	10.139438,	0},
-	{-0.235829,	0.083797,	10.134649,	0},
-	{-0.240617,	0.083797,	10.107116,	0},
-	{-0.239420,	0.087388,	10.134649,	0},
-	{-0.248997,	0.074220,	10.125072,	0},
-	{-0.247800,	0.064643,	10.150211,	0},
-	{-0.243011,	0.076614,	10.111904,	0},
-	{-0.247800,	0.069432,	10.139438,	0},
-	{-0.240617,	0.076614,	10.132255,	0},
-	{-0.240617,	0.076614,	10.129861,	0},
-	{-0.235829,	0.065841,	10.105919,	0},
-	{-0.252588,	0.080206,	10.113101,	0},
-	{-0.251391,	0.077812,	10.149014,	0},
-	{-0.241814,	0.082600,	10.056837,	0},
-	{-0.243011,	0.084994,	10.199292,	0},
-	{-0.253785,	0.077812,	10.098736,	0},
-	{-0.229843,	0.063446,	10.103524,	0},
-	{-0.250194,	0.069432,	10.183730,	0},
-	{-0.240617,	0.086191,	10.067612,	0},
-	{-0.246603,	0.070629,	10.201687,	0},
-	{-0.263362,	0.067038,	10.071202,	0},
-	{-0.245406,	0.059855,	10.166970,	0},
-	{-0.239420,	0.065841,	10.092751,	0},
-	{-0.238223,	0.068235,	10.139438,	0},
-	{-0.243011,	0.074220,	10.116693,	0},
-	{-0.240617,	0.081403,	10.122678,	0},
-	{-0.251391,	0.067038,	10.119086,	0},
-	{-0.240617,	0.075417,	10.113101,	0},
-	{-0.250194,	0.059855,	10.137043,	0},
-	{-0.244208,	0.062249,	10.129861,	0},
-	{-0.229843,	0.083797,	10.117889,	0},
-	{-0.246603,	0.076614,	10.123875,	0},
-	{-0.234632,	0.087388,	10.140635,	0},
-	{-0.254982,	0.079009,	10.119086,	0},
-	{-0.237026,	0.074220,	10.157393,	0},
-	{-0.247800,	0.088585,	10.115496,	0},
-	{-0.251391,	0.087388,	10.144226,	0},
-	{-0.238223,	0.071826,	10.116693,	0},
-	{-0.233435,	0.069432,	10.137043,	0},
-	{-0.231040,	0.081403,	10.119086,	0},
-	{-0.244208,	0.079009,	10.116693,	0},
-	{-0.245406,	0.073023,	10.147817,	0},
-	{-0.250194,	0.071826,	10.113101,	0},
-	{-0.238223,	0.077812,	10.135846,	0},
-	{-0.240617,	0.077812,	10.105919,	0},
-	{-0.239420,	0.076614,	10.145423,	0},
-	{-0.232237,	0.070629,	10.102327,	0},
-	{-0.241814,	0.080206,	10.119086,	0},
-	{-0.237026,	0.068235,	10.111904,	0},
-	{-0.260968,	0.082600,	10.137043,	0},
-	{-0.240617,	0.089783,	10.139438,	0},
-	{-0.238223,	0.077812,	10.128663,	0},
-	{-0.240617,	0.075417,	10.138240,	0},
-	{-0.247800,	0.075417,	10.129861,	0},
-	{-0.251391,	0.075417,	10.143028,	0},
-	{-0.254982,	0.076614,	10.128663,	0},
-	{-0.251391,	0.070629,	10.157393,	0},
-	{-0.253785,	0.086191,	10.134649,	0},
-	{-0.248997,	0.079009,	10.126269,	0},
-	{-0.244208,	0.087388,	10.117889,	0},
-	{-0.254982,	0.080206,	10.125072,	0},
-	{-0.244208,	0.071826,	10.122678,	0},
-	{-0.248997,	0.087388,	10.111904,	0},
-	{-0.246603,	0.075417,	10.133451,	0},
-	{-0.252588,	0.071826,	10.099933,	0},
-	{-0.245406,	0.082600,	10.132255,	0},
-	{-0.246603,	0.086191,	10.129861,	0},
-	{-0.227449,	0.067038,	10.151408,	0},
-	{-0.235829,	0.079009,	10.109509,	0},
-	{-0.239420,	0.080206,	10.137043,	0},
-	{-0.241814,	0.084994,	10.121481,	0},
-	{-0.251391,	0.081403,	10.116693,	0},
-	{-0.260968,	0.073023,	10.141831,	0},
-	{-0.245406,	0.073023,	10.122678,	0},
-	{-0.252588,	0.083797,	10.139438,	0},
-	{-0.243011,	0.080206,	10.122678,	0},
-	{-0.239420,	0.077812,	10.138240,	0},
-	{-0.241814,	0.068235,	10.113101,	0},
-	{-0.244208,	0.074220,	10.133451,	0},
-	{-0.257377,	0.079009,	10.128663,	0},
-	{-0.253785,	0.074220,	10.125072,	0},
-	{-0.238223,	0.062249,	10.132255,	0},
-	{-0.243011,	0.068235,	10.119086,	0},
-	{-0.240617,	0.074220,	10.132255,	0},
-	{-0.272939,	0.076614,	10.116693,	0},
-	{-0.234632,	0.075417,	10.138240,	0},
-	{-0.241814,	0.073023,	10.085567,	0},
-	{-0.246603,	0.075417,	10.163380,	0},
-	{-0.248997,	0.058658,	10.093947,	0},
-	{-0.243011,	0.070629,	10.146620,	0},
-	{-0.238223,	0.074220,	10.110707,	0},
-	{-0.252588,	0.065841,	10.141831,	0},
-	{-0.229843,	0.074220,	10.137043,	0},
-	{-0.248997,	0.076614,	10.099933,	0},
-	{-0.229843,	0.081403,	10.157393,	0},
-	{-0.243011,	0.082600,	10.074794,	0},
-	{-0.250194,	0.071826,	10.164577,	0},
-	{-0.263362,	0.076614,	10.103524,	0},
-	{-0.260968,	0.094571,	10.138240,	0},
-	{-0.240617,	0.077812,	10.116693,	0},
-	{-0.239420,	0.081403,	10.109509,	0},
-	{-0.253785,	0.086191,	10.135846,	0},
-	{-0.247800,	0.076614,	10.093947,	0},
-	{-0.256179,	0.068235,	10.158591,	0},
-	{-0.253785,	0.079009,	10.090356,	0},
-	{-0.239420,	0.076614,	10.151408,	0},
-	{-0.244208,	0.082600,	10.115496,	0},
-	{-0.244208,	0.081403,	10.134649,	0},
-	{-0.254982,	0.088585,	10.122678,	0},
-	{-0.252588,	0.069432,	10.120284,	0},
-	{-0.247800,	0.077812,	10.137043,	0},
-	{-0.250194,	0.076614,	10.117889,	0},
-	{-0.238223,	0.077812,	10.121481,	0},
-	{-0.245406,	0.065841,	10.186124,	0},
-	{-0.233435,	0.065841,	10.046063,	0},
-	{-0.237026,	0.094571,	10.243585,	0},
-	{-0.231040,	0.093374,	10.014939,	0},
-	{-0.243011,	0.084994,	10.223234,	0},
-	{-0.256179,	0.064643,	9.987406,	0},
-	{-0.250194,	0.098162,	10.247176,	0},
-	{-0.229843,	0.073023,	9.891638,	0},
-	{-0.268150,	0.062249,	10.406390,	0},
-	{-0.247800,	0.073023,	9.883258,	0},
-	{-0.237026,	0.076614,	10.360901,	0},
-	{-0.247800,	0.081403,	9.975434,	0},
-	{-0.225055,	0.080206,	10.178942,	0},
-	{-0.263362,	0.071826,	10.163380,	0},
-	{-0.237026,	0.076614,	10.062823,	0},
-	{-0.265756,	0.075417,	10.214854,	0},
-	{-0.234632,	0.083797,	10.053246,	0},
-	{-0.254982,	0.071826,	10.210066,	0},
-	{-0.241814,	0.076614,	10.001771,	0},
-	{-0.221464,	0.117316,	10.239994,	0},
-	{-0.269348,	0.076614,	10.064020,	0},
-	{-0.220266,	0.092177,	10.166970,	0},
-	{-0.252588,	0.075417,	10.111904,	0},
-	{-0.232237,	0.068235,	10.122678,	0},
-	{-0.259771,	0.075417,	10.110707,	0},
-	{-0.246603,	0.095768,	10.137043,	0},
-	{-0.235829,	0.076614,	10.138240,	0},
-	{-0.256179,	0.071826,	10.102327,	0},
-	{-0.229843,	0.089783,	10.175350,	0},
-	{-0.260968,	0.082600,	10.089159,	0},
-	{-0.225055,	0.086191,	10.169365,	0},
-	{-0.262165,	0.087388,	10.103524,	0},
-	{-0.234632,	0.077812,	10.149014,	0},
-	{-0.241814,	0.070629,	10.079582,	0},
-	{-0.256179,	0.077812,	10.163380,	0},
-	{-0.226252,	0.068235,	10.096342,	0},
-	{-0.253785,	0.080206,	10.117889,	0},
-	{-0.244208,	0.077812,	10.163380,	0},
-	{-0.269348,	0.076614,	10.097539,	0},
-	{-0.238223,	0.069432,	10.169365,	0},
-	{-0.254982,	0.068235,	10.096342,	0},
-	{-0.231040,	0.061052,	10.159788,	0},
-	{-0.248997,	0.075417,	10.079582,	0},
-	{-0.258574,	0.071826,	10.162182,	0},
-	{-0.232237,	0.079009,	10.102327,	0},
-	{-0.256179,	0.100556,	10.138240,	0},
-	{-0.232237,	0.084994,	10.116693,	0},
-	{-0.235829,	0.080206,	10.110707,	0},
-	{-0.225055,	0.065841,	10.129861,	0},
-	{-0.217872,	0.082600,	10.090356,	0},
-	{-0.244208,	0.081403,	10.157393,	0},
-};
-
-const size_t kBodyDetectOnOffTestDataLength =
-	ARRAY_SIZE(kBodyDetectOnOffTestData);
diff --git a/test/body_detection_test_data.h b/test/body_detection_test_data.h
deleted file mode 100644
index 4c22c3236f..0000000000
--- a/test/body_detection_test_data.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BODY_DETECTION_TEST_DATA_H
-#define __CROS_EC_BODY_DETECTION_TEST_DATA_H
-
-#include "body_detection.h"
-#include "motion_sense.h"
-
-struct body_detect_test_data {
-	float x, y, z;
-	int action;
-};
-
-extern const struct body_detect_test_data kBodyDetectOnBodyTestData[];
-extern const size_t kBodyDetectOnBodyTestDataLength;
-
-extern const struct body_detect_test_data kBodyDetectOffOnTestData[];
-extern const size_t kBodyDetectOffOnTestDataLength;
-
-extern const struct body_detect_test_data kBodyDetectOnOffTestData[];
-extern const size_t kBodyDetectOnOffTestDataLength;
-#endif
diff --git a/test/build.mk b/test/build.mk
deleted file mode 100644
index 61865009f6..0000000000
--- a/test/build.mk
+++ /dev/null
@@ -1,262 +0,0 @@
-# -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Device test binaries
-test-list-y ?= flash_write_protect pingpong timer_calib timer_dos timer_jump mutex utils utils_str
-#disable: powerdemo
-
-# Emulator tests
-ifneq ($(TEST_LIST_HOST),)
-test-list-host=$(TEST_LIST_HOST)
-else
-test-list-host = accel_cal
-test-list-host += aes
-test-list-host += base32
-test-list-host += battery_get_params_smart
-test-list-host += bklight_lid
-test-list-host += bklight_passthru
-test-list-host += body_detection
-test-list-host += button
-test-list-host += cbi
-test-list-host += cbi_wp
-test-list-host += cec
-test-list-host += charge_manager
-test-list-host += charge_manager_drp_charging
-test-list-host += charge_ramp
-test-list-host += compile_time_macros
-test-list-host += console_edit
-test-list-host += crc
-test-list-host += entropy
-test-list-host += extpwr_gpio
-test-list-host += fan
-test-list-host += flash
-test-list-host += float
-test-list-host += fp
-test-list-host += fpsensor
-test-list-host += fpsensor_crypto
-test-list-host += fpsensor_state
-test-list-host += gyro_cal
-test-list-host += hooks
-test-list-host += host_command
-test-list-host += i2c_bitbang
-test-list-host += inductive_charging
-test-list-host += interrupt
-test-list-host += irq_locking
-test-list-host += is_enabled
-test-list-host += is_enabled_error
-test-list-host += kasa
-test-list-host += kb_8042
-test-list-host += kb_mkbp
-test-list-host += kb_scan
-test-list-host += kb_scan_strict
-test-list-host += lid_sw
-test-list-host += lightbar
-test-list-host += mag_cal
-test-list-host += math_util
-test-list-host += motion_angle
-test-list-host += motion_angle_tablet
-test-list-host += motion_lid
-test-list-host += motion_sense_fifo
-test-list-host += mutex
-test-list-host += newton_fit
-test-list-host += online_calibration
-test-list-host += online_calibration_spoof
-test-list-host += pingpong
-test-list-host += power_button
-test-list-host += printf
-test-list-host += queue
-test-list-host += rsa
-test-list-host += rsa3
-test-list-host += rtc
-test-list-host += sbs_charging_v2
-test-list-host += sha256
-test-list-host += sha256_unrolled
-test-list-host += shmalloc
-test-list-host += static_if
-test-list-host += static_if_error
-test-list-host += system
-test-list-host += thermal
-test-list-host += timer_dos
-test-list-host += uptime
-test-list-host += usb_common
-test-list-host += usb_pd_int
-test-list-host += usb_pd
-test-list-host += usb_pd_giveback
-test-list-host += usb_pd_rev30
-test-list-host += usb_pd_pdo_fixed
-test-list-host += usb_ppc
-test-list-host += usb_sm_framework_h3
-test-list-host += usb_sm_framework_h2
-test-list-host += usb_sm_framework_h1
-test-list-host += usb_sm_framework_h0
-test-list-host += usb_typec_vpd
-test-list-host += usb_typec_ctvpd
-test-list-host += usb_typec_drp_acc_trysrc
-test-list-host += usb_prl_old
-test-list-host += usb_tcpmv2_compliance
-test-list-host += usb_prl
-test-list-host += usb_prl_noextended
-test-list-host += usb_pe_drp_old
-test-list-host += usb_pe_drp_old_noextended
-test-list-host += usb_pe_drp
-test-list-host += usb_pe_drp_noextended
-test-list-host += utils
-test-list-host += utils_str
-test-list-host += vboot
-test-list-host += version
-test-list-host += x25519
-test-list-host += stillness_detector
-endif
-
-# Build up the list of coverage test targets based on test-list-host, but
-# with some tests excluded because they cause code coverage to fail.
-
-# is_enabled_error is a shell script that does not produce coverage results
-cov-dont-test = is_enabled_error
-# static_if_error is a shell script that does not produce coverage results
-cov-dont-test += static_if_error
-# fpsensor: genhtml looks for build/host/fpsensor/cryptoc/util.c
-cov-dont-test += fpsensor
-# fpsensor_crypto: genhtml looks for build/host/fpsensor_crypto/cryptoc/util.c
-cov-dont-test += fpsensor_crypto
-# fpsensor_state: genhtml looks for build/host/fpsensor_state/cryptoc/util.c
-cov-dont-test += fpsensor_state
-# version: Only works in a chroot.
-cov-dont-test += version
-cov-test-list-host = $(filter-out $(cov-dont-test), $(test-list-host))
-
-accel_cal-y=accel_cal.o
-aes-y=aes.o
-base32-y=base32.o
-battery_get_params_smart-y=battery_get_params_smart.o
-bklight_lid-y=bklight_lid.o
-bklight_passthru-y=bklight_passthru.o
-body_detection-y=body_detection.o body_detection_data_literals.o motion_common.o
-button-y=button.o
-cbi-y=cbi.o
-cbi_wp-y=cbi_wp.o
-cec-y=cec.o
-charge_manager-y=charge_manager.o
-charge_manager_drp_charging-y=charge_manager.o
-charge_ramp-y+=charge_ramp.o
-compile_time_macros-y=compile_time_macros.o
-console_edit-y=console_edit.o
-crc-y=crc.o
-entropy-y=entropy.o
-extpwr_gpio-y=extpwr_gpio.o
-fan-y=fan.o
-flash-y=flash.o
-flash_physical-y=flash_physical.o
-flash_write_protect-y=flash_write_protect.o
-fpsensor-y=fpsensor.o
-fpsensor_crypto-y=fpsensor_crypto.o
-fpsensor_hw-y=fpsensor_hw.o
-fpsensor_state-y=fpsensor_state.o
-gyro_cal-y=gyro_cal.o gyro_cal_init_for_test.o
-hooks-y=hooks.o
-host_command-y=host_command.o
-i2c_bitbang-y=i2c_bitbang.o
-inductive_charging-y=inductive_charging.o
-interrupt-y=interrupt.o
-irq_locking-y=irq_locking.o
-is_enabled-y=is_enabled.o
-kb_8042-y=kb_8042.o
-kb_mkbp-y=kb_mkbp.o
-kb_scan-y=kb_scan.o
-kb_scan_strict-y=kb_scan.o
-lid_sw-y=lid_sw.o
-lightbar-y=lightbar.o
-mag_cal-y=mag_cal.o
-math_util-y=math_util.o
-motion_angle-y=motion_angle.o motion_angle_data_literals.o motion_common.o
-motion_angle_tablet-y=motion_angle_tablet.o motion_angle_data_literals_tablet.o motion_common.o
-motion_lid-y=motion_lid.o
-motion_sense_fifo-y=motion_sense_fifo.o
-online_calibration-y=online_calibration.o
-online_calibration_spoof-y=online_calibration_spoof.o gyro_cal_init_for_test.o
-kasa-y=kasa.o
-mpu-y=mpu.o
-mutex-y=mutex.o
-newton_fit-y=newton_fit.o
-pingpong-y=pingpong.o
-power_button-y=power_button.o
-powerdemo-y=powerdemo.o
-printf-y=printf.o
-queue-y=queue.o
-rollback-y=rollback.o
-rollback_entropy-y=rollback_entropy.o
-rsa-y=rsa.o
-rsa3-y=rsa.o
-rtc-y=rtc.o
-scratchpad-y=scratchpad.o
-sbs_charging-y=sbs_charging.o
-sbs_charging_v2-y=sbs_charging_v2.o
-sha256-y=sha256.o
-sha256_unrolled-y=sha256.o
-shmalloc-y=shmalloc.o
-static_if-y=static_if.o
-stm32f_rtc-y=stm32f_rtc.o
-stress-y=stress.o
-system-y=system.o
-thermal-y=thermal.o
-timer_calib-y=timer_calib.o
-timer_dos-y=timer_dos.o
-uptime-y=uptime.o
-usb_common-y=usb_common_test.o fake_battery.o
-usb_pd_int-y=usb_pd_int.o
-usb_pd-y=usb_pd.o
-usb_pd_giveback-y=usb_pd.o
-usb_pd_rev30-y=usb_pd.o
-usb_pd_pdo_fixed-y=usb_pd_pdo_fixed_test.o
-usb_ppc-y=usb_ppc.o
-usb_sm_framework_h3-y=usb_sm_framework_h3.o
-usb_sm_framework_h2-y=usb_sm_framework_h3.o
-usb_sm_framework_h1-y=usb_sm_framework_h3.o
-usb_sm_framework_h0-y=usb_sm_framework_h3.o
-usb_typec_vpd-y=usb_typec_ctvpd.o vpd_api.o usb_sm_checks.o fake_usbc.o
-usb_typec_ctvpd-y=usb_typec_ctvpd.o vpd_api.o usb_sm_checks.o fake_usbc.o
-usb_typec_drp_acc_trysrc-y=usb_typec_drp_acc_trysrc.o vpd_api.o \
-	usb_sm_checks.o
-usb_prl_old-y=usb_prl_old.o usb_sm_checks.o fake_usbc.o
-usb_prl-y=usb_prl.o usb_sm_checks.o
-usb_prl_noextended-y=usb_prl_noextended.o usb_sm_checks.o fake_usbc.o
-usb_pe_drp_old-y=usb_pe_drp_old.o usb_sm_checks.o fake_usbc.o
-usb_pe_drp_old_noextended-y=usb_pe_drp_old.o usb_sm_checks.o fake_usbc.o
-usb_pe_drp-y=usb_pe_drp.o usb_sm_checks.o
-usb_pe_drp_noextended-y=usb_pe_drp_noextended.o usb_sm_checks.o
-usb_tcpmv2_compliance-y=usb_tcpmv2_compliance.o usb_tcpmv2_compliance_common.o \
-	usb_tcpmv2_td_pd_ll_e3.o \
-	usb_tcpmv2_td_pd_ll_e4.o \
-	usb_tcpmv2_td_pd_ll_e5.o \
-	usb_tcpmv2_td_pd_src_e1.o \
-	usb_tcpmv2_td_pd_src_e2.o \
-	usb_tcpmv2_td_pd_src_e5.o \
-	usb_tcpmv2_td_pd_src3_e1.o \
-	usb_tcpmv2_td_pd_src3_e7.o \
-	usb_tcpmv2_td_pd_src3_e8.o \
-	usb_tcpmv2_td_pd_src3_e9.o \
-	usb_tcpmv2_td_pd_src3_e26.o \
-	usb_tcpmv2_td_pd_src3_e32.o \
-	usb_tcpmv2_td_pd_snk3_e12.o \
-	usb_tcpmv2_td_pd_vndi3_e3.o \
-	usb_tcpmv2_td_pd_other.o
-utils-y=utils.o
-utils_str-y=utils_str.o
-vboot-y=vboot.o
-version-y += version.o
-float-y=fp.o
-fp-y=fp.o
-x25519-y=x25519.o
-stillness_detector-y=stillness_detector.o
-
-host-is_enabled_error: TEST_SCRIPT=is_enabled_error.sh
-is_enabled_error-y=is_enabled_error.o.cmd
-
-host-static_if_error: TEST_SCRIPT=static_if_error.sh
-static_if_error-y=static_if_error.o.cmd
-
-run-genvif_test:
-	@echo "  TEST    genvif_test"
-	@test/genvif/genvif.sh
diff --git a/test/button.c b/test/button.c
deleted file mode 100644
index e457eaa786..0000000000
--- a/test/button.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test non-keyboard buttons.
-*
- * Using GPIOS and buttons[] defined in board/host/board.c
- * Volume down is active low with a debounce time of 30 mSec.
- * Volume up is active high with a debounce time of 60 mSec.
- *
- */
-
-#include "button.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "test_util.h"
-#include "timer.h"
-#include "keyboard_config.h"
-#include "keyboard_protocol.h"
-#include "util.h"
-
-#define UNCHANGED -1
-
-uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
-
-static const struct button_config *button_vol_down =
-	&buttons[BUTTON_VOLUME_DOWN];
-static const struct button_config *button_vol_up = &buttons[BUTTON_VOLUME_UP];
-
-static int button_state[BUTTON_COUNT];
-
-/*
- * Callback from the button handling logic.
- * This is normally implemented by a keyboard protocol handler.
- */
-void keyboard_update_button(enum keyboard_button_type button, int is_pressed)
-{
-	int i;
-
-	for (i = 0; i < BUTTON_COUNT; i++) {
-		if (buttons[i].type == button) {
-			button_state[i] = is_pressed;
-			break;
-		}
-	}
-}
-
-/* Test pressing a button */
-static int test_button_press(void)
-{
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(100);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-
-	return EC_SUCCESS;
-}
-
-/* Test releasing a button */
-static int test_button_release(void)
-{
-	gpio_set_level(button_vol_up->gpio, 0);
-	msleep(100);
-	gpio_set_level(button_vol_up->gpio, 1);
-	msleep(100);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == 0);
-
-	return EC_SUCCESS;
-}
-
-/* A press shorter than the debounce time should not trigger an update */
-static int test_button_debounce_short_press(void)
-{
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(10);
-	gpio_set_level(button_vol_down->gpio, 1);
-	msleep(100);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-
-	return EC_SUCCESS;
-}
-
-/* A short bounce while pressing should still result in a button press */
-static int test_button_debounce_short_bounce(void)
-{
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(10);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	gpio_set_level(button_vol_down->gpio, 1);
-	msleep(10);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-
-	return EC_SUCCESS;
-}
-
-/* Button level must be stable for the entire debounce interval */
-static int test_button_debounce_stability(void)
-{
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	gpio_set_level(button_vol_down->gpio, 1);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	msleep(60);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	gpio_set_level(button_vol_down->gpio, 1);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 0);
-	msleep(60);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 0);
-
-	return EC_SUCCESS;
-}
-
-/* Test pressing both buttons at different times */
-static int test_button_press_both(void)
-{
-	gpio_set_level(button_vol_down->gpio, 0);
-	msleep(10);
-	gpio_set_level(button_vol_up->gpio, 0);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == UNCHANGED);
-	msleep(30);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == UNCHANGED);
-	msleep(40);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == 1);
-
-	return EC_SUCCESS;
-}
-
-/* Button simulate test cases */
-static int send_button_hostcmd(uint32_t btn_mask, uint32_t press_ms)
-{
-	struct ec_params_button p;
-
-	p.press_ms = press_ms;
-	p.btn_mask = btn_mask;
-
-	return test_send_host_command(EC_CMD_BUTTON, 0, &p, sizeof(p), NULL, 0);
-}
-
-static void test_sim_button_util(uint32_t btn_mask, uint32_t press_ms)
-{
-	send_button_hostcmd(btn_mask, press_ms);
-	msleep(100);
-}
-
-/* Test simulate pressing a button */
-static int test_sim_button_press(void)
-{
-	test_sim_button_util(1 << KEYBOARD_BUTTON_VOLUME_DOWN, 100);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-
-	return EC_SUCCESS;
-}
-
-/* Test simulate releasing a button */
-static int test_sim_button_release(void)
-{
-	test_sim_button_util(1 << KEYBOARD_BUTTON_VOLUME_UP, 50);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == 0);
-
-	return EC_SUCCESS;
-}
-
-/* A press shorter than the debounce time should not trigger an update */
-static int test_sim_button_debounce_short_press(void)
-{
-	test_sim_button_util(1 << KEYBOARD_BUTTON_VOLUME_DOWN, 10);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-
-	return EC_SUCCESS;
-}
-
-/* A short bounce while pressing should still result in a button press */
-static int test_sim_button_debounce_short_bounce(void)
-{
-	uint32_t btn_mask = 0;
-
-	btn_mask |= (1 << KEYBOARD_BUTTON_VOLUME_DOWN);
-	send_button_hostcmd(btn_mask, 10);
-	msleep(50);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-
-	send_button_hostcmd(btn_mask, 100);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-
-	return EC_SUCCESS;
-}
-
-/* Button level must be stable for the entire debounce interval */
-static int test_sim_button_debounce_stability(void)
-{
-	uint32_t btn_mask = 0;
-
-	btn_mask |= (1 << KEYBOARD_BUTTON_VOLUME_DOWN);
-	send_button_hostcmd(btn_mask, 10);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-
-	send_button_hostcmd(btn_mask, 100);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	msleep(60);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	msleep(20);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 0);
-	msleep(60);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 0);
-
-	return EC_SUCCESS;
-}
-
-/* Test simulate pressing both buttons */
-static int test_sim_button_press_both(void)
-{
-	uint32_t btn_mask = 0;
-
-	btn_mask |= (1 << KEYBOARD_BUTTON_VOLUME_DOWN);
-	btn_mask |= (1 << KEYBOARD_BUTTON_VOLUME_UP);
-	send_button_hostcmd(btn_mask, 100);
-	msleep(10);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == UNCHANGED);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == UNCHANGED);
-	msleep(60);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 1);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == 1);
-	msleep(100);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_DOWN] == 0);
-	TEST_ASSERT(button_state[BUTTON_VOLUME_UP] == 0);
-
-	return EC_SUCCESS;
-}
-
-static void button_test_init(void)
-{
-	int i;
-
-	ccprints("Setting button GPIOs to inactive state");
-	for (i = 0; i < BUTTON_COUNT; i++)
-		gpio_set_level(buttons[i].gpio,
-			       !(buttons[i].flags & BUTTON_FLAG_ACTIVE_HIGH));
-
-	msleep(100);
-	for (i = 0; i < BUTTON_COUNT; i++)
-		button_state[i] = UNCHANGED;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	button_init();
-
-	button_test_init();
-	RUN_TEST(test_button_press);
-
-	button_test_init();
-	RUN_TEST(test_button_release);
-
-	button_test_init();
-	RUN_TEST(test_button_debounce_short_press);
-
-	button_test_init();
-	RUN_TEST(test_button_debounce_short_bounce);
-
-	button_test_init();
-	RUN_TEST(test_button_debounce_stability);
-
-	button_test_init();
-	RUN_TEST(test_button_press_both);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_press);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_release);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_debounce_short_press);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_debounce_short_bounce);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_debounce_stability);
-
-	button_test_init();
-	RUN_TEST(test_sim_button_press_both);
-
-	test_print_result();
-}
diff --git a/test/button.tasklist b/test/button.tasklist
deleted file mode 100644
index 5a8fb1bfbe..0000000000
--- a/test/button.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-        TASK_TEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE)
diff --git a/test/cbi.c b/test/cbi.c
deleted file mode 100644
index 688063f153..0000000000
--- a/test/cbi.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test CBI
- */
-
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "test_util.h"
-#include "util.h"
-
-static void test_setup(void)
-{
-	/* Make sure that write protect is disabled */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	gpio_set_level(GPIO_WP, 0);
-#else
-	gpio_set_level(GPIO_WP_L, 1);
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-
-	cbi_create();
-	cbi_write();
-}
-
-static void test_teardown(void)
-{
-}
-
-DECLARE_EC_TEST(test_uint8)
-{
-	uint8_t d8;
-	uint32_t d32;
-	uint8_t size;
-	const int tag = 0xff;
-
-	/* Set & get uint8_t */
-	d8 = 0xa5;
-	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
-		      NULL);
-	size = 1;
-	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_SUCCESS, NULL);
-	zassert_equal(d8, 0xa5, "0x%x, 0x%x", d8, 0xa5);
-	zassert_equal(size, 1, "%x, %x", size, 1);
-
-	/* Size-up */
-	d32 = 0x1234abcd;
-	zassert_equal(cbi_set_board_info(tag, (void *)&d32, sizeof(d32)),
-		      EC_SUCCESS, NULL);
-	size = 4;
-	zassert_equal(cbi_get_board_info(tag, (void *)&d32, &size), EC_SUCCESS,
-		      NULL);
-	zassert_equal(d32, 0x1234abcd, "0x%x, 0x%x", d32, 0x1234abcd);
-	zassert_equal(size, 4, "%u, %u", size, 4);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_uint32)
-{
-	uint8_t d8;
-	uint32_t d32;
-	uint8_t size;
-	const int tag = 0xff;
-
-	/* Set & get uint32_t */
-	d32 = 0x1234abcd;
-	zassert_equal(cbi_set_board_info(tag, (void *)&d32, sizeof(d32)),
-		      EC_SUCCESS, NULL);
-	size = 4;
-	zassert_equal(cbi_get_board_info(tag, (void *)&d32, &size), EC_SUCCESS,
-		      NULL);
-	zassert_equal(d32, 0x1234abcd, "0x%x, 0x%x", d32, 0x1234abcd);
-	zassert_equal(size, 4, "%u, %u", size, 4);
-
-	/* Size-down */
-	d8 = 0xa5;
-	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
-		      NULL);
-	size = 1;
-	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_SUCCESS, NULL);
-	zassert_equal(d8, 0xa5, "0x%x, 0x%x", d8, 0xa5);
-	zassert_equal(size, 1, "%u, %u", size, 1);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_string)
-{
-	const uint8_t string[] = "abcdefghijklmn";
-	uint8_t buf[32];
-	uint8_t size;
-	const int tag = 0xff;
-
-	/* Set & get string */
-	zassert_equal(cbi_set_board_info(tag, string, sizeof(string)),
-		      EC_SUCCESS, NULL);
-	size = sizeof(buf);
-	zassert_equal(cbi_get_board_info(tag, buf, &size), EC_SUCCESS, NULL);
-	zassert_equal(strncmp(buf, string, sizeof(string)), 0, NULL);
-	/* Size contains null byte */
-	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
-	 * which will generate compilation error.
-	 */
-	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
-		     (size_t)size - 1, strlen(buf));
-
-	/* Read buffer too small */
-	size = 4;
-	zassert_equal(cbi_get_board_info(tag, buf, &size), EC_ERROR_INVAL,
-		      NULL);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_not_found)
-{
-	uint8_t d8;
-	const int tag = 0xff;
-	uint8_t size;
-
-	size = 1;
-	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_ERROR_UNKNOWN,
-		      NULL);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_too_large)
-{
-	uint8_t buf[CBI_IMAGE_SIZE-1];
-	const int tag = 0xff;
-
-	/* Data too large */
-	memset(buf, 0xa5, sizeof(buf));
-	zassert_equal(cbi_set_board_info(tag, buf, sizeof(buf)),
-		      EC_ERROR_OVERFLOW, NULL);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_all_tags)
-{
-	uint8_t d8;
-	uint32_t d32;
-	uint64_t d64;
-	const char string[] = "abc";
-	uint8_t buf[32];
-	uint8_t size;
-	int count = 0;
-
-	/* Populate all data and read out */
-	d8 = 0x12;
-	zassert_equal(cbi_set_board_info(CBI_TAG_BOARD_VERSION, &d8,
-					 sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_ID, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_SKU_ID, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM,
-					 string, sizeof(string)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME,
-					 string, sizeof(string)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_MODEL_ID, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_FW_CONFIG, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8,
-					 sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_SSFC, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_REWORK_ID, &d8, sizeof(d8)),
-		      EC_SUCCESS, NULL);
-	count++;
-
-	/* Read out all */
-	zassert_equal(cbi_get_board_version(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_oem_id(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_sku_id(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	size = sizeof(buf);
-	zassert_equal(cbi_get_board_info(CBI_TAG_DRAM_PART_NUM, buf, &size),
-		      EC_SUCCESS, NULL);
-	zassert_equal(strncmp(buf, string, sizeof(string)), 0, NULL);
-	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
-	 * which will generate compilation error.
-	 */
-	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
-		     (size_t)size - 1, strlen(buf));
-	size = sizeof(buf);
-	zassert_equal(cbi_get_board_info(CBI_TAG_OEM_NAME, buf, &size),
-		      EC_SUCCESS, NULL);
-	zassert_equal(strncmp(buf, string, sizeof(string)), 0, NULL);
-	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
-	 * which will generate compilation error.
-	 */
-	zassert_true((size_t)size - 1 == strlen(buf), "%zu, %zu",
-		     (size_t)size - 1, strlen(buf));
-	zassert_equal(cbi_get_model_id(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_fw_config(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_pcb_supplier(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_ssfc(&d32), EC_SUCCESS, NULL);
-	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
-	zassert_equal(cbi_get_rework_id(&d64), EC_SUCCESS, NULL);
-	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
-	 * which will generate compilation error.
-	 */
-	zassert_true((unsigned long long)d64 == (unsigned long long)d8,
-		     "0x%llx, 0x%llx", (unsigned long long)d64,
-		     (unsigned long long)d8);
-
-	/* Fail if a (new) tag is missing from the unit test. */
-	zassert_equal(count, CBI_TAG_COUNT, "%d, %d", count, CBI_TAG_COUNT);
-
-	/* Write protect */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	gpio_set_level(GPIO_WP, 1);
-#else
-	gpio_set_level(GPIO_WP_L, 0);
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-	zassert_equal(cbi_write(), EC_ERROR_ACCESS_DENIED, NULL);
-
-	return EC_SUCCESS;
-}
-
-DECLARE_EC_TEST(test_bad_crc)
-{
-	uint8_t d8;
-	const int tag = 0xff;
-	uint8_t size;
-	int crc;
-
-	/* Bad CRC */
-	d8 = 0xa5;
-	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
-		      NULL);
-	i2c_read8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-		   offsetof(struct cbi_header, crc), &crc);
-	i2c_write8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-		   offsetof(struct cbi_header, crc), ++crc);
-	cbi_invalidate_cache();
-	size = sizeof(d8);
-	zassert_equal(cbi_get_board_info(tag, &d8, &size), EC_ERROR_UNKNOWN,
-		      NULL);
-
-	return EC_SUCCESS;
-}
-
-TEST_SUITE(test_suite_cbi)
-{
-	ztest_test_suite(test_cbi,
-			 ztest_unit_test_setup_teardown(test_uint8, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_uint32, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_string, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_not_found,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_too_large,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_all_tags,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_bad_crc,
-							test_setup,
-							test_teardown));
-	ztest_run_test_suite(test_cbi);
-}
diff --git a/test/cbi.tasklist b/test/cbi.tasklist
deleted file mode 100644
index 52c0d390ef..0000000000
--- a/test/cbi.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/cbi_wp.c b/test/cbi_wp.c
deleted file mode 100644
index 7bdfa4b0c8..0000000000
--- a/test/cbi_wp.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test CBI EEPROM WP
- */
-
-#include "common.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "gpio.h"
-#include "system.h"
-#include "test_util.h"
-#include "util.h"
-
-static int system_locked;
-
-static void test_setup(void)
-{
-	/* Make sure that write protect is disabled */
-	gpio_set_level(GPIO_WP, 0);
-	gpio_set_level(GPIO_EC_CBI_WP, 0);
-	system_locked = 0;
-}
-
-static void test_teardown(void)
-{
-}
-
-int system_is_locked(void)
-{
-	return system_locked;
-}
-
-DECLARE_EC_TEST(test_wp)
-{
-	int cbi_wp;
-
-	cbi_wp = gpio_get_level(GPIO_EC_CBI_WP);
-	zassert_equal(cbi_wp, 0, NULL);
-
-	cbi_latch_eeprom_wp();
-	cbi_wp = gpio_get_level(GPIO_EC_CBI_WP);
-	zassert_equal(cbi_wp, 1, NULL);
-
-	return EC_SUCCESS;
-}
-
-TEST_SUITE(test_suite_cbi_wp)
-{
-	ztest_test_suite(test_cbi_wp,
-			 ztest_unit_test_setup_teardown(test_wp,
-							test_setup,
-							test_teardown));
-	ztest_run_test_suite(test_cbi_wp);
-}
diff --git a/test/cbi_wp.tasklist b/test/cbi_wp.tasklist
deleted file mode 100644
index e54ea001bd..0000000000
--- a/test/cbi_wp.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/cec.c b/test/cec.c
deleted file mode 100644
index 9377e4fcd3..0000000000
--- a/test/cec.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test the buffer handling of HDMI CEC
- */
-
-#include <string.h>
-
-#include "cec.h"
-#include "test_util.h"
-
-struct overflow_msg {
-	struct cec_msg_transfer transfer;
-	uint8_t overflow_detector;
-} overflow_msg;
-/* Ensure the overflow detector is located directly after the buffer */
-BUILD_ASSERT(offsetof(struct overflow_msg, overflow_detector) ==
-	     offsetof(struct cec_msg_transfer, buf) + MAX_CEC_MSG_LEN);
-
-
-struct overflow_queue {
-	struct cec_rx_queue queue;
-	uint8_t overflow_detector[CEC_RX_BUFFER_SIZE];
-} overflow_queue;
-/* Ensure the overflow detector is located directly after the buffer */
-BUILD_ASSERT(offsetof(struct overflow_queue, overflow_detector) ==
-	     offsetof(struct cec_rx_queue, buf) + CEC_RX_BUFFER_SIZE);
-
-static struct cec_rx_queue *queue;
-
-/* Tests */
-static int test_msg_overflow(void)
-{
-	int i;
-
-	/* Overwrite the buffer by 1 byte */
-	for (i = 0; i < (MAX_CEC_MSG_LEN+1)*8; i++) {
-		cec_transfer_set_bit(&overflow_msg.transfer, 1);
-		cec_transfer_inc_bit(&overflow_msg.transfer);
-	}
-
-	/* Make sure we actually wrote the whole buffer with ones */
-	for (i = 0; i < MAX_CEC_MSG_LEN; i++)
-		TEST_ASSERT(overflow_msg.transfer.buf[i] == 0xff);
-
-	/* Verify that the attempt to overflow the buffer did not succeed */
-	TEST_ASSERT(overflow_msg.overflow_detector == 0);
-
-	/* The full indicator is when byte reaches MAX_CEC_MSG_LEN */
-	TEST_ASSERT(overflow_msg.transfer.byte == MAX_CEC_MSG_LEN);
-
-	/* Check that the indicator stays the same if we write another byte */
-	for (i = 0; i < 8; i++) {
-		cec_transfer_set_bit(&overflow_msg.transfer, 1);
-		cec_transfer_inc_bit(&overflow_msg.transfer);
-	}
-	TEST_ASSERT(overflow_msg.transfer.byte == MAX_CEC_MSG_LEN);
-
-	return EC_SUCCESS;
-}
-
-
-
-static int verify_no_queue_overflow(void)
-{
-	int i;
-
-	for (i = 0; i < CEC_RX_BUFFER_SIZE; i++) {
-		if (overflow_queue.overflow_detector[i] != 0)
-			return EC_ERROR_OVERFLOW;
-	}
-	return EC_SUCCESS;
-}
-
-
-static void clear_queue(void)
-{
-	memset(queue, 0, sizeof(struct cec_rx_queue));
-
-}
-
-static int fill_queue(uint8_t *msg, int msg_size)
-{
-	int i;
-
-	/*
-	 * Fill the queue. Every push adds the message and one extra byte for
-	 * the length field. The maximum data we can add is one less than
-	 * CEC_RX_BUFFER_SIZE since write_pointer==read_pointer is used to
-	 * indicate an empty buffer
-	 */
-	clear_queue();
-
-	for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1)/(msg_size + 1); i++)
-		TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) == 0);
-
-	/* Now the queue should be full */
-	TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) ==
-							EC_ERROR_OVERFLOW);
-
-	/* Verify nothing was written outside of the queue */
-	TEST_ASSERT(verify_no_queue_overflow() == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue_overflow(void)
-{
-	uint8_t msg[CEC_RX_BUFFER_SIZE];
-
-	memset(msg, 0xff, sizeof(msg));
-
-	TEST_ASSERT(fill_queue(msg, 1) == EC_SUCCESS);
-	TEST_ASSERT(fill_queue(msg, 2) == EC_SUCCESS);
-	TEST_ASSERT(fill_queue(msg, 3) == EC_SUCCESS);
-	TEST_ASSERT(fill_queue(msg, MAX_CEC_MSG_LEN) == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	queue = &overflow_queue.queue;
-
-	RUN_TEST(test_msg_overflow);
-
-	RUN_TEST(test_queue_overflow);
-
-	test_print_result();
-}
diff --git a/test/cec.tasklist b/test/cec.tasklist
deleted file mode 100644
index e7634958a9..0000000000
--- a/test/cec.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test the buffer handling of HDMI CEC
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/charge_manager.c b/test/charge_manager.c
deleted file mode 100644
index 2a64ca3e98..0000000000
--- a/test/charge_manager.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test charge manager module.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "common.h"
-#include "ec_commands.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "util.h"
-
-#define CHARGE_MANAGER_SLEEP_MS 50
-
-/* Charge supplier priority: lower number indicates higher priority. */
-const int supplier_priority[] = {
-	[CHARGE_SUPPLIER_TEST1] = 0,
-	[CHARGE_SUPPLIER_TEST2] = 1,
-	[CHARGE_SUPPLIER_TEST3] = 1,
-	[CHARGE_SUPPLIER_TEST4] = 1,
-	[CHARGE_SUPPLIER_TEST5] = 3,
-	[CHARGE_SUPPLIER_TEST6] = 3,
-	[CHARGE_SUPPLIER_TEST7] = 5,
-	[CHARGE_SUPPLIER_TEST8] = 6,
-	[CHARGE_SUPPLIER_TEST9] = 6,
-	[CHARGE_SUPPLIER_TEST10] = 7,
-};
-BUILD_ASSERT((int)CHARGE_SUPPLIER_COUNT == (int)CHARGE_SUPPLIER_TEST_COUNT);
-BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
-
-static unsigned int active_charge_limit = CHARGE_SUPPLIER_NONE;
-static unsigned int active_charge_port = CHARGE_PORT_NONE;
-static unsigned int charge_port_to_reject = CHARGE_PORT_NONE;
-static int new_power_request[CONFIG_USB_PD_PORT_MAX_COUNT];
-static enum pd_power_role power_role[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-/* Callback functions called by CM on state change */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	active_charge_limit = charge_ma;
-}
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-/* Sets a charge port that will be rejected as the active port. */
-static void set_charge_port_to_reject(int port)
-{
-	charge_port_to_reject = port;
-}
-
-int board_set_active_charge_port(int charge_port)
-{
-	if (charge_port != CHARGE_PORT_NONE &&
-	    charge_port == charge_port_to_reject)
-		return EC_ERROR_INVAL;
-
-	active_charge_port = charge_port;
-	return EC_SUCCESS;
-}
-
-void board_charge_manager_override_timeout(void)
-{
-}
-
-void pd_set_new_power_request(int port)
-{
-	new_power_request[port] = 1;
-}
-
-static void clear_new_power_requests(void)
-{
-	int i;
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i)
-		new_power_request[i] = 0;
-}
-
-static void pd_set_role(int port, int role)
-{
-	power_role[port] = role;
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return power_role[port];
-}
-
-void pd_request_power_swap(int port)
-{
-	if (power_role[port] == PD_ROLE_SINK)
-		power_role[port] = PD_ROLE_SOURCE;
-	else
-		power_role[port] = PD_ROLE_SINK;
-}
-
-static void wait_for_charge_manager_refresh(void)
-{
-	msleep(CHARGE_MANAGER_SLEEP_MS);
-}
-
-static void initialize_charge_table(int current, int voltage, int ceil)
-{
-	int i, j;
-	struct charge_port_info charge;
-
-	charge_manager_set_override(OVERRIDE_OFF);
-	set_charge_port_to_reject(CHARGE_PORT_NONE);
-	charge.current = current;
-	charge.voltage = voltage;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		for (j = 0; j < CEIL_REQUESTOR_COUNT; ++j)
-			charge_manager_set_ceil(i, j, ceil);
-		charge_manager_update_dualrole(i, CAP_DEDICATED);
-		pd_set_role(i, PD_ROLE_SINK);
-		for (j = 0; j < CHARGE_SUPPLIER_COUNT; ++j)
-			charge_manager_update_charge(j, i, &charge);
-	}
-	wait_for_charge_manager_refresh();
-}
-
-static int test_initialization(void)
-{
-	int i, j;
-	struct charge_port_info charge;
-
-	/*
-	 * No charge port should be selected until all ports + suppliers
-	 * have reported in with an initial charge.
-	 */
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-	charge.current = 1000;
-	charge.voltage = 5000;
-
-	/* Initialize all supplier/port pairs, except for the last one */
-	for (i = 0; i < CHARGE_SUPPLIER_COUNT; ++i)
-		for (j = 0; j < board_get_usb_pd_port_count(); ++j) {
-			if (i == 0)
-				charge_manager_update_dualrole(j,
-							       CAP_DEDICATED);
-			if (i == CHARGE_SUPPLIER_COUNT - 1 &&
-			    j == board_get_usb_pd_port_count() - 1)
-				break;
-			charge_manager_update_charge(i, j, &charge);
-		}
-
-	/* Verify no active charge port, since all pairs haven't updated */
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-
-	/* Update last pair and verify a charge port has been selected */
-	charge_manager_update_charge(CHARGE_SUPPLIER_COUNT-1,
-				     board_get_usb_pd_port_count()-1,
-				     &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port != CHARGE_PORT_NONE);
-
-	return EC_SUCCESS;
-}
-
-static int test_safe_mode(void)
-{
-	int port = 0;
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge */
-	initialize_charge_table(0, 5000, 5000);
-
-	/*
-	 * Set a 2A non-dedicated charger on port 0 and verify that
-	 * it is selected, due to safe mode.
-	 */
-	charge_manager_update_dualrole(port, CAP_DUALROLE);
-	charge.current = 2000;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, port, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == port);
-	TEST_ASSERT(active_charge_limit == 2000);
-
-	/* Verify ceil is ignored, due to safe mode. */
-	charge_manager_set_ceil(port, 0, 500);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_limit == 2000);
-
-	/*
-	 * Leave safe mode and verify normal port selection rules go
-	 * into effect.
-	 */
-	charge_manager_leave_safe_mode();
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	TEST_ASSERT(active_charge_port == port);
-	TEST_ASSERT(active_charge_limit == 500);
-#else
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-#endif
-
-	/* For subsequent tests, safe mode is exited. */
-	return EC_SUCCESS;
-}
-
-static int test_priority(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge */
-	initialize_charge_table(0, 5000, 5000);
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-
-	/*
-	 * Set a 1A charge via a high-priority supplier and a 2A charge via
-	 * a low-priority supplier, and verify the HP supplier is chosen.
-	 */
-	charge.current = 2000;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 0, &charge);
-	charge.current = 1000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 1000);
-
-	/*
-	 * Set a higher charge on a LP supplier and verify we still use the
-	 * lower charge.
-	 */
-	charge.current = 1500;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST7, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 1000);
-
-	/*
-	 * Zero our HP charge and verify fallback to next highest priority,
-	 * which happens to be a different port.
-	 */
-	charge.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 2000);
-
-	/* Add a charge at equal priority and verify highest charge selected */
-	charge.current = 2500;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST5, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 2500);
-
-	charge.current = 3000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 3000);
-
-	/*
-	 * Add a charge at equal priority and equal power, verify that the
-	 * active port doesn't change since the first plugged port is
-	 * selected as the tiebreaker.
-	 */
-	charge.current = 3000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 3000);
-
-	return EC_SUCCESS;
-}
-
-static int test_charge_ceil(void)
-{
-	int port;
-	struct charge_port_info charge;
-
-	/* Initialize table to 1A @ 5V, and verify port + limit */
-	initialize_charge_table(1000, 5000, 1000);
-	TEST_ASSERT(active_charge_port != CHARGE_PORT_NONE);
-	TEST_ASSERT(active_charge_limit == 1000);
-
-	/* Set a 500mA ceiling, verify port is unchanged */
-	port = active_charge_port;
-	charge_manager_set_ceil(port, 0, 500);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(port == active_charge_port);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/* Raise the ceiling to 2A, verify limit goes back to 1A */
-	charge_manager_set_ceil(port, 0, 2000);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(port == active_charge_port);
-	TEST_ASSERT(active_charge_limit == 1000);
-
-	/* Verify that ceiling is ignored in determining active charge port */
-	charge.current = 2000;
-	charge.voltage = 5000;
-	charge_manager_update_charge(0, 0, &charge);
-	charge.current = 2500;
-	charge_manager_update_charge(0, 1, &charge);
-	charge_manager_set_ceil(1, 0, 750);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 750);
-
-	/* Set a secondary lower ceiling and verify it takes effect */
-	charge_manager_set_ceil(1, 1, 500);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/* Raise the secondary ceiling and verify the primary takes effect */
-	charge_manager_set_ceil(1, 1, 800);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 750);
-
-	/* Remove the primary celing and verify the secondary takes effect */
-	charge_manager_set_ceil(1, 0, CHARGE_CEIL_NONE);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 800);
-
-	/* Remove all ceilings */
-	charge_manager_set_ceil(1, 1, CHARGE_CEIL_NONE);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 2500);
-
-	/* Verify forced ceil takes effect immediately */
-	charge_manager_force_ceil(1, 500);
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	return EC_SUCCESS;
-}
-
-static int test_new_power_request(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge */
-	initialize_charge_table(0, 5000, 5000);
-	/* Clear power requests, and verify they are zero'd */
-	clear_new_power_requests();
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 0);
-	TEST_ASSERT(new_power_request[1] == 0);
-
-	/* Charge from port 1 and verify NPR on port 1 only */
-	charge.current = 1000;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 0);
-	TEST_ASSERT(new_power_request[1] == 1);
-	clear_new_power_requests();
-
-	/* Reduce port 1 through ceil and verify no NPR */
-	charge_manager_set_ceil(1, 0, 500);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 0);
-	TEST_ASSERT(new_power_request[1] == 0);
-	clear_new_power_requests();
-
-	/* Change port 1 voltage and verify NPR on port 1 */
-	charge.voltage = 4000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 0);
-	TEST_ASSERT(new_power_request[1] == 1);
-	clear_new_power_requests();
-
-	/* Add low-priority source and verify no NPRs */
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 0);
-	TEST_ASSERT(new_power_request[1] == 0);
-	clear_new_power_requests();
-
-	/*
-	 * Add higher-priority source and verify NPR on both ports,
-	 * since we're switching charge ports.
-	 */
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(new_power_request[0] == 1);
-	TEST_ASSERT(new_power_request[1] == 1);
-	clear_new_power_requests();
-
-	return EC_SUCCESS;
-}
-
-static int test_override(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge */
-	initialize_charge_table(0, 5000, 1000);
-
-	/*
-	 * Set a low-priority supplier on p0 and high-priority on p1, then
-	 * verify that p1 is selected.
-	 */
-	charge.current = 500;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/* Set override to p0 and verify p0 is selected */
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-
-	/* Remove override and verify p1 is again selected */
-	charge_manager_set_override(OVERRIDE_OFF);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-
-	/*
-	 * Set override again to p0, but set p0 charge to 0, and verify p1
-	 * is again selected.
-	 */
-	charge.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-
-	/* Set non-zero charge on port 0 and verify override was auto-removed */
-	charge.current = 250;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST5, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-
-	/*
-	 * Verify current limit is still selected according to supplier
-	 * priority on the override port.
-	 */
-	charge.current = 300;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 300);
-	charge.current = 100;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 0, &charge);
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 100);
-
-	/*
-	 * Verify that a don't charge override request on a dual-role
-	 * port causes a swap to source.
-	 */
-	pd_set_role(0, PD_ROLE_SINK);
-	charge_manager_update_dualrole(0, CAP_DUALROLE);
-	charge_manager_set_override(OVERRIDE_DONT_CHARGE);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-
-	/*
-	 * Verify that an override request to a dual-role source port
-	 * causes a role swap to sink.
-	 */
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	charge.current = 200;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 200);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SINK);
-
-	/* Set override to "don't charge", then verify we're not charging */
-	charge_manager_set_override(OVERRIDE_DONT_CHARGE);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-	TEST_ASSERT(active_charge_limit == 0);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-
-	/* Update a charge supplier, verify that we still aren't charging */
-	charge.current = 200;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-	TEST_ASSERT(active_charge_limit == 0);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-
-	/* Turn override off, verify that we go back to the correct charge */
-	charge_manager_set_override(OVERRIDE_OFF);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-
-	return EC_SUCCESS;
-}
-
-static int test_dual_role(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge. */
-	initialize_charge_table(0, 5000, 1000);
-
-	/* Mark P0 as dual-role and set a charge. */
-	charge_manager_update_dualrole(0, CAP_DUALROLE);
-	charge.current = 500;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify we do charge from dual-role port */
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-#else
-	/* Verify we don't charge from dual-role port */
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-	TEST_ASSERT(active_charge_limit == 0);
-#endif
-
-	/* Mark P0 as the override port, verify that we now charge. */
-	charge_manager_set_override(0);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SINK);
-
-	/* Remove override and verify we go back to previous state */
-	charge_manager_set_override(OVERRIDE_OFF);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-#else
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-	TEST_ASSERT(active_charge_limit == 0);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-#endif
-
-	/* Mark P0 as the override port, verify that we again charge. */
-	charge_manager_set_override(0);
-	charge.current = 550;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 550);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SINK);
-
-	/*
-	 * Insert a dual-role charger into P1 and set the override. Verify
-	 * that the override correctly changes.
-	 */
-	charge_manager_update_dualrole(1, CAP_DUALROLE);
-	charge_manager_set_override(1);
-	charge.current = 500;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 500);
-	TEST_ASSERT(pd_get_power_role(1) == PD_ROLE_SINK);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-
-	/* Set override back to P0 and verify switch */
-	charge_manager_set_override(0);
-	charge.current = 600;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 600);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SINK);
-	TEST_ASSERT(pd_get_power_role(1) == PD_ROLE_SOURCE);
-
-	/* Insert a dedicated charger and verify override is removed */
-	charge.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 1, &charge);
-	wait_for_charge_manager_refresh();
-	charge_manager_update_dualrole(1, CAP_DEDICATED);
-	charge.current = 400;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 1, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 600);
-#else
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 400);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-#endif
-
-	/*
-	 * Verify the port is handled normally if the dual-role source is
-	 * unplugged and replaced with a dedicated source.
-	 */
-	charge_manager_update_dualrole(0, CAP_DEDICATED);
-	charge.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge.current = 500;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/*
-	 * Test one port connected to dedicated charger and one connected
-	 * to dual-role device.
-	 */
-	charge_manager_update_dualrole(0, CAP_DUALROLE);
-	charge.current = 0;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge.current = 500;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	charge.current = 200;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST6, 1, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify we charge from port with higher priority */
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-#else
-	/*
-	 * Verify that we charge from the dedicated port if a dual-role
-	 * source is also attached.
-	 */
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 200);
-	TEST_ASSERT(pd_get_power_role(0) == PD_ROLE_SOURCE);
-#endif
-
-	return EC_SUCCESS;
-}
-
-static int test_rejected_port(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge. */
-	initialize_charge_table(0, 5000, 1000);
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-
-	/* Set a charge on P0. */
-	charge.current = 500;
-	charge.voltage = 5000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/* Set P0 as rejected, and verify that it doesn't become active. */
-	set_charge_port_to_reject(1);
-	charge.current = 1000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-
-	/* Don't reject P0, and verify it can become active. */
-	set_charge_port_to_reject(CHARGE_PORT_NONE);
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST1, 1, &charge);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 1000);
-
-	return EC_SUCCESS;
-}
-
-static int test_unknown_dualrole_capability(void)
-{
-	struct charge_port_info charge;
-
-	/* Initialize table to no charge. */
-	initialize_charge_table(0, 5000, 2000);
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-
-	/* Set a charge on P0 with unknown dualrole capability, */
-	charge.current = 500;
-	charge.voltage = 5000;
-	charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify we do charge from that port */
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 500);
-#else
-	/* Verify that we don't charge from the port. */
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-#endif
-
-	/* Toggle to dedicated and verify port becomes active. */
-	charge_manager_update_dualrole(0, CAP_DEDICATED);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-
-	/* Add dualrole charger in port 1 */
-	charge.current = 1000;
-	charge_manager_update_dualrole(1, CAP_DUALROLE);
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 1, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 1000);
-#else
-	TEST_ASSERT(active_charge_port == 0);
-#endif
-
-	/* Remove charger on port 0 */
-	charge.current = 0;
-	charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	TEST_ASSERT(active_charge_port == 1);
-	TEST_ASSERT(active_charge_limit == 1000);
-#else
-	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
-#endif
-
-	/* Set override to charge on port 1 */
-	charge_manager_set_override(1);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-
-	/*
-	 * Toggle port 0 to dedicated, verify that override is still kept
-	 * because there's no charge on the port.
-	 */
-	charge_manager_update_dualrole(0, CAP_DEDICATED);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 1);
-
-	/* Insert UNKNOWN capability charger on port 0 */
-	charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	charge.current = 2000;
-	charge_manager_update_charge(CHARGE_SUPPLIER_TEST2, 0, &charge);
-	wait_for_charge_manager_refresh();
-	wait_for_charge_manager_refresh();
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify override is removed */
-	TEST_ASSERT(active_charge_port == 0);
-	TEST_ASSERT(active_charge_limit == 2000);
-#else
-	/* Verify override is still kept */
-	TEST_ASSERT(active_charge_port == 1);
-#endif
-
-	/* Toggle to dualrole */
-	charge_manager_update_dualrole(0, CAP_DUALROLE);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify no change */
-	TEST_ASSERT(active_charge_port == 0);
-#else
-	/* Verify override is still kept */
-	TEST_ASSERT(active_charge_port == 1);
-#endif
-
-	/* Toggle to dedicated */
-	charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	wait_for_charge_manager_refresh();
-#ifdef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-	/* Verify no change */
-	TEST_ASSERT(active_charge_port == 0);
-#else
-	/* Verify override is still kept */
-	TEST_ASSERT(active_charge_port == 1);
-#endif
-	charge_manager_update_dualrole(0, CAP_DEDICATED);
-	wait_for_charge_manager_refresh();
-	TEST_ASSERT(active_charge_port == 0);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_initialization);
-	RUN_TEST(test_safe_mode);
-	RUN_TEST(test_priority);
-	RUN_TEST(test_charge_ceil);
-	RUN_TEST(test_new_power_request);
-	RUN_TEST(test_override);
-	RUN_TEST(test_dual_role);
-	RUN_TEST(test_rejected_port);
-	RUN_TEST(test_unknown_dualrole_capability);
-
-	test_print_result();
-}
diff --git a/test/charge_manager.tasklist b/test/charge_manager.tasklist
deleted file mode 100644
index 1f6f139a63..0000000000
--- a/test/charge_manager.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST /* No test task */
diff --git a/test/charge_manager_drp_charging.tasklist b/test/charge_manager_drp_charging.tasklist
deleted file mode 100644
index e39c934e44..0000000000
--- a/test/charge_manager_drp_charging.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST /* No test task */
diff --git a/test/charge_ramp.c b/test/charge_ramp.c
deleted file mode 100644
index 84cac57b8e..0000000000
--- a/test/charge_ramp.c
+++ /dev/null
@@ -1,526 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test AC input current ramp.
- */
-
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-
-#define TASK_EVENT_OVERCURRENT (1 << 0)
-
-#define RAMP_STABLE_DELAY (120*SECOND)
-
-/*
- * Time to delay for detecting the charger type. This value follows
- * the value in common/charge_ramp.c, but must be less than the real
- * CHARGE_DETECT_DELAY so we guarantee we wake up before the ramp
- * has started.
- */
-#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100*MSEC)
-
-static int system_load_current_ma;
-static int vbus_low_current_ma = 500;
-static int overcurrent_current_ma = 3000;
-
-static int charge_limit_ma;
-
-/* Mock functions */
-
-__override uint8_t board_get_usb_pd_port_count(void)
-{
-	return CONFIG_USB_PD_PORT_MAX_COUNT;
-}
-
-/* Override test_mockable implementations in charge_ramp module */
-int chg_ramp_allowed(int port, int supplier)
-{
-	/* Ramp for TEST4-TEST8 */
-	return supplier > CHARGE_SUPPLIER_TEST3;
-}
-
-int chg_ramp_max(int port, int supplier, int sup_curr)
-{
-	if (supplier == CHARGE_SUPPLIER_TEST7)
-		return 1600;
-	else if (supplier == CHARGE_SUPPLIER_TEST8)
-		return 2400;
-	else
-		return 3000;
-}
-
-/* Mock bc12_ports[] array to make linker happy */
-struct bc12_config bc12_ports[0];
-
-int charge_is_consuming_full_input_current(void)
-{
-	return charge_limit_ma <= system_load_current_ma;
-}
-
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	return MIN(system_load_current_ma, charge_limit_ma) >
-	       vbus_low_current_ma;
-}
-
-void board_set_charge_limit(int port, int supplier, int limit_ma,
-			    int max_ma, int max_mv)
-{
-	charge_limit_ma = limit_ma;
-	if (charge_limit_ma > overcurrent_current_ma)
-		task_set_event(TASK_ID_TEST_RUNNER, TASK_EVENT_OVERCURRENT);
-}
-
-/* Test utilities */
-
-static void plug_charger_with_ts(int supplier_type, int port, int min_current,
-				 int vbus_low_current, int overcurrent_current,
-				 timestamp_t reg_time)
-{
-	vbus_low_current_ma = vbus_low_current;
-	overcurrent_current_ma = overcurrent_current;
-	chg_ramp_charge_supplier_change(port, supplier_type, min_current,
-					reg_time, 0);
-}
-
-static void plug_charger(int supplier_type, int port, int min_current,
-			 int vbus_low_current, int overcurrent_current)
-{
-	plug_charger_with_ts(supplier_type, port, min_current,
-			     vbus_low_current, overcurrent_current,
-			     get_time());
-}
-
-static void unplug_charger(void)
-{
-	chg_ramp_charge_supplier_change(CHARGE_PORT_NONE, CHARGE_SUPPLIER_NONE,
-					0, get_time(), 0);
-}
-
-static int unplug_charger_and_check(void)
-{
-	unplug_charger();
-	usleep(CHARGE_DETECT_DELAY_TEST);
-	return charge_limit_ma == 0;
-}
-
-static int wait_stable_no_overcurrent(void)
-{
-	return task_wait_event(RAMP_STABLE_DELAY) != TASK_EVENT_OVERCURRENT;
-}
-
-static int is_in_range(int x, int min, int max)
-{
-	return x >= min && x <= max;
-}
-
-/* Tests */
-
-static int test_no_ramp(void)
-{
-	system_load_current_ma = 3000;
-	/* A powerful charger, but hey, you're not allowed to ramp! */
-	plug_charger(CHARGE_SUPPLIER_TEST1, 0, 500, 3000, 3000);
-	/*
-	 * NOTE: Since this is currently the first test being run, give the
-	 * charge ramp task enough time to actually transition states and set
-	 * the charge limit.  This just needs at least transition to the
-	 * CHG_RAMP_OVERCURRENT_DETECT state.
-	 */
-	usleep(CHARGE_DETECT_DELAY_TEST + 200*MSEC);
-	/* That's right. Start at 500 mA */
-	TEST_ASSERT(charge_limit_ma == 500);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	/* ... and stays at 500 mA */
-	TEST_ASSERT(charge_limit_ma == 500);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_full_ramp(void)
-{
-	system_load_current_ma = 3000;
-	/* Now you get to ramp with this 3A charger */
-	plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 3000);
-	usleep(CHARGE_DETECT_DELAY_TEST);
-	/* Start with something around 500 mA */
-	TEST_ASSERT(is_in_range(charge_limit_ma, 500, 800));
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	/* And ramp up to 3A */
-	TEST_ASSERT(charge_limit_ma == 3000);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_vbus_dip(void)
-{
-	system_load_current_ma = 3000;
-	/* VBUS dips too low right before the charger shuts down */
-	plug_charger(CHARGE_SUPPLIER_TEST5, 0, 1000, 1500, 1600);
-
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1300, 1500));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_overcurrent(void)
-{
-	system_load_current_ma = 3000;
-	/* Huh...VBUS doesn't dip before the charger shuts down */
-	plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 3000, 1500);
-	usleep(CHARGE_DETECT_DELAY_TEST);
-	/* Ramp starts at 500 mA */
-	TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-
-	while (task_wait_event(RAMP_STABLE_DELAY) == TASK_EVENT_OVERCURRENT) {
-		/* Charger goes away but comes back after 0.6 seconds */
-		unplug_charger();
-		usleep(MSEC * 600);
-		plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 3000, 1500);
-		usleep(CHARGE_DETECT_DELAY_TEST);
-		/* Ramp restarts at 500 mA */
-		TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	}
-
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1300, 1500));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_switch_outlet(void)
-{
-	int i;
-
-	system_load_current_ma = 3000;
-	/* Here's a nice powerful charger */
-	plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 3000, 3000);
-
-	/*
-	 * Now the user decides to move it to a nearby outlet...actually
-	 * they decide to move it 5 times!
-	 */
-	for (i = 0; i < 5; ++i) {
-		usleep(SECOND * 20);
-		unplug_charger();
-		usleep(SECOND * 1.5);
-		plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 3000, 3000);
-		usleep(CHARGE_DETECT_DELAY_TEST);
-		/* Ramp restarts at 500 mA */
-		TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	}
-
-	/* Should still ramp up to 3000 mA */
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 3000);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_fast_switch(void)
-{
-	int i;
-
-	system_load_current_ma = 3000;
-	plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 3000);
-
-	/*
-	 * Here comes that naughty user again, and this time they are switching
-	 * outlet really quickly. Fortunately this time they only do it twice.
-	 */
-	for (i = 0; i < 2; ++i) {
-		usleep(SECOND * 20);
-		unplug_charger();
-		usleep(600 * MSEC);
-		plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 3000);
-		usleep(CHARGE_DETECT_DELAY_TEST);
-		/* Ramp restarts at 500 mA */
-		TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	}
-
-	/* Should still ramp up to 3000 mA */
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 3000);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_overcurrent_after_switch_outlet(void)
-{
-	system_load_current_ma = 3000;
-	/* Here's a less powerful charger */
-	plug_charger(CHARGE_SUPPLIER_TEST5, 0, 500, 3000, 1500);
-	usleep(SECOND * 5);
-
-	/* Now the user decides to move it to a nearby outlet */
-	unplug_charger();
-	usleep(SECOND * 1.5);
-	plug_charger(CHARGE_SUPPLIER_TEST5, 0, 500, 3000, 1500);
-
-	/* Okay the user is satisified */
-	while (task_wait_event(RAMP_STABLE_DELAY) == TASK_EVENT_OVERCURRENT) {
-		/* Charger goes away but comes back after 0.6 seconds */
-		unplug_charger();
-		usleep(MSEC * 600);
-		plug_charger(CHARGE_SUPPLIER_TEST5, 0, 500, 3000, 1500);
-		usleep(CHARGE_DETECT_DELAY_TEST);
-		/* Ramp restarts at 500 mA */
-		TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	}
-
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1300, 1500));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_partial_load(void)
-{
-	/* We have a 3A charger, but we just want 1.5A */
-	system_load_current_ma = 1500;
-	plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 2500);
-
-	/* We should end up with a little bit more than 1.5A */
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1500, 1600));
-
-	/* Ok someone just started watching YouTube */
-	system_load_current_ma = 2000;
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 2000, 2100));
-
-	/* Somehow the system load increases again */
-	system_load_current_ma = 2600;
-	while (task_wait_event(RAMP_STABLE_DELAY) == TASK_EVENT_OVERCURRENT) {
-		/* Charger goes away but comes back after 0.6 seconds */
-		unplug_charger();
-		usleep(MSEC * 600);
-		plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 2500);
-		usleep(CHARGE_DETECT_DELAY_TEST);
-		/* Ramp restarts at 500 mA */
-		TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	}
-
-	/* Alright the charger isn't powerful enough, so we'll stop at 2.5A */
-	TEST_ASSERT(is_in_range(charge_limit_ma, 2300, 2500));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_charge_supplier_stable(void)
-{
-	system_load_current_ma = 3000;
-	/* The charger says it's of type TEST4 initially */
-	plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 1500, 1600);
-	/*
-	 * And then it decides it's actually TEST2 after 0.5 seconds,
-	 * why? Well, this charger is just evil.
-	 */
-	usleep(500 * MSEC);
-	plug_charger(CHARGE_SUPPLIER_TEST2, 0, 3000, 3000, 3000);
-	/* We should get 3A right away. */
-	usleep(SECOND);
-	TEST_ASSERT(charge_limit_ma == 3000);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_charge_supplier_stable_ramp(void)
-{
-	system_load_current_ma = 3000;
-	/* This time we start with a non-ramp charge supplier */
-	plug_charger(CHARGE_SUPPLIER_TEST3, 0, 500, 3000, 3000);
-	/*
-	 * After 0.5 seconds, it's decided that the supplier is actually
-	 * a 1.5A ramp supplier.
-	 */
-	usleep(500 * MSEC);
-	plug_charger(CHARGE_SUPPLIER_TEST5, 0, 500, 1400, 1500);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1200, 1400));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_charge_supplier_change(void)
-{
-	system_load_current_ma = 3000;
-	/* Start with a 3A ramp charge supplier */
-	plug_charger(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 3000);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 3000);
-
-	/* The charger decides to change type to a 1.5A non-ramp supplier */
-	plug_charger(CHARGE_SUPPLIER_TEST1, 0, 1500, 3000, 3000);
-	usleep(500 * MSEC);
-	TEST_ASSERT(charge_limit_ma == 1500);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 1500);
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_charge_port_change(void)
-{
-	system_load_current_ma = 3000;
-	/* Start with a 1.5A ramp charge supplier on port 0 */
-	plug_charger(CHARGE_SUPPLIER_TEST5, 0, 500, 1400, 1500);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1200, 1400));
-
-	/* Here comes a 2.1A ramp charge supplier on port 1 */
-	plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 2000, 2100);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1800, 2000));
-
-	/* Now we have a 2.5A non-ramp charge supplier on port 0 */
-	plug_charger(CHARGE_SUPPLIER_TEST1, 0, 2500, 3000, 3000);
-	usleep(SECOND);
-	TEST_ASSERT(charge_limit_ma == 2500);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 2500);
-
-	/* Unplug on port 0 */
-	plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 2000, 2100);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1800, 2000));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_vbus_shift(void)
-{
-	system_load_current_ma = 3000;
-	/*
-	 * At first, the charger is able to supply up to 1900 mA before
-	 * the VBUS voltage starts to drop.
-	 */
-	plug_charger(CHARGE_SUPPLIER_TEST6, 0, 500, 1900, 2000);
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1700, 1900));
-
-	/* The charger heats up and VBUS voltage drops by 100mV */
-	vbus_low_current_ma = 1800;
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1600, 1800));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_equal_priority_overcurrent(void)
-{
-	int overcurrent_count = 0;
-	timestamp_t oc_time = get_time();
-
-	system_load_current_ma = 3000;
-
-	/*
-	 * Now we have two charge suppliers of equal priorties plugged into
-	 * port 0 and port 1. If the active one browns out, charge manager
-	 * switches to the other one.
-	 */
-	while (1) {
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000,
-				     2000, oc_time);
-		oc_time = get_time();
-		oc_time.val += 600 * MSEC;
-		if (wait_stable_no_overcurrent())
-			break;
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000,
-				     2000, oc_time);
-		oc_time = get_time();
-		oc_time.val += 600 * MSEC;
-		if (wait_stable_no_overcurrent())
-			break;
-		if (overcurrent_count++ >= 10) {
-			/*
-			 * Apparently we are in a loop and can never reach
-			 * stable state.
-			 */
-			unplug_charger();
-			return EC_ERROR_UNKNOWN;
-		}
-	}
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-static int test_ramp_limit(void)
-{
-	system_load_current_ma = 3000;
-
-	/* Plug in supplier that is limited to 1.6A */
-	plug_charger(CHARGE_SUPPLIER_TEST7, 0, 500, 3000, 3000);
-	usleep(SECOND);
-	TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 1600);
-
-	/* Switch to supplier that is limited to 2.4A */
-	plug_charger(CHARGE_SUPPLIER_TEST8, 1, 500, 3000, 3000);
-	usleep(SECOND);
-	TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(charge_limit_ma == 2400);
-
-	/* Go back to 1.6A limited, but VBUS goes low before that point */
-	plug_charger(CHARGE_SUPPLIER_TEST7, 0, 500, 1200, 1300);
-	usleep(SECOND);
-	TEST_ASSERT(is_in_range(charge_limit_ma, 500, 700));
-	TEST_ASSERT(wait_stable_no_overcurrent());
-	TEST_ASSERT(is_in_range(charge_limit_ma, 1000, 1200));
-
-	TEST_ASSERT(unplug_charger_and_check());
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	/*
-	 * If the following test order changes, make sure to add enough time for
-	 * the charge ramp task to make its first transition after plugging in a
-	 * charger.  See the comment in test_no_ramp().
-	 */
-	RUN_TEST(test_no_ramp);
-	RUN_TEST(test_full_ramp);
-	RUN_TEST(test_vbus_dip);
-	RUN_TEST(test_overcurrent);
-	RUN_TEST(test_switch_outlet);
-	RUN_TEST(test_fast_switch);
-	RUN_TEST(test_overcurrent_after_switch_outlet);
-	RUN_TEST(test_partial_load);
-	RUN_TEST(test_charge_supplier_stable);
-	RUN_TEST(test_charge_supplier_stable_ramp);
-	RUN_TEST(test_charge_supplier_change);
-	RUN_TEST(test_charge_port_change);
-	RUN_TEST(test_vbus_shift);
-	RUN_TEST(test_equal_priority_overcurrent);
-	RUN_TEST(test_ramp_limit);
-
-	test_print_result();
-}
diff --git a/test/charge_ramp.tasklist b/test/charge_ramp.tasklist
deleted file mode 100644
index 1e18846c75..0000000000
--- a/test/charge_ramp.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(CHG_RAMP, chg_ramp_task, NULL, SMALLER_TASK_STACK_SIZE)
diff --git a/test/compile_time_macros.c b/test/compile_time_macros.c
deleted file mode 100644
index 60b3bae7b6..0000000000
--- a/test/compile_time_macros.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test compile_time_macros.h
- */
-
-#include "stdbool.h"
-#include "common.h"
-#include "test_util.h"
-
-
-static int test_BIT(void)
-{
-	TEST_EQ(BIT(0),  0x00000001U, "%u");
-	TEST_EQ(BIT(25), 0x02000000U, "%u");
-	TEST_EQ(BIT(31), 0x80000000U, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_BIT_ULL(void)
-{
-	TEST_EQ(BIT_ULL(0),  0x0000000000000001ULL, "%Lu");
-	TEST_EQ(BIT_ULL(25), 0x0000000002000000ULL, "%Lu");
-	TEST_EQ(BIT_ULL(50), 0x0004000000000000ULL, "%Lu");
-	TEST_EQ(BIT_ULL(63), 0x8000000000000000ULL, "%Lu");
-
-	return EC_SUCCESS;
-}
-
-static int test_GENMASK(void)
-{
-	TEST_EQ(GENMASK(0, 0),   0x00000001U, "%u");
-	TEST_EQ(GENMASK(31, 0),  0xFFFFFFFFU, "%u");
-	TEST_EQ(GENMASK(4, 4),   0x00000010U, "%u");
-	TEST_EQ(GENMASK(4, 0),   0x0000001FU, "%u");
-	TEST_EQ(GENMASK(21, 21), 0x00200000U, "%u");
-	TEST_EQ(GENMASK(31, 31), 0x80000000U, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_GENMASK_ULL(void)
-{
-	TEST_EQ(GENMASK_ULL(0, 0),   0x0000000000000001ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(31, 0),  0x00000000FFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(63, 0),  0xFFFFFFFFFFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 4),   0x0000000000000010ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 0),   0x000000000000001FULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(21, 21), 0x0000000000200000ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(31, 31), 0x0000000080000000ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(63, 63), 0x8000000000000000ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(62, 60), 0x7000000000000000ULL, "%Lu");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_IS_ARRAY(void)
-{
-	int array[5];
-	int *pointer = array;
-
-	TEST_EQ(_IS_ARRAY(array), true, "%d");
-	TEST_EQ(_IS_ARRAY(pointer), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_BIT);
-	RUN_TEST(test_BIT_ULL);
-	RUN_TEST(test_GENMASK);
-	RUN_TEST(test_GENMASK_ULL);
-	RUN_TEST(test_IS_ARRAY);
-
-	test_print_result();
-}
diff --git a/test/compile_time_macros.tasklist b/test/compile_time_macros.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/compile_time_macros.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/console_edit.c b/test/console_edit.c
deleted file mode 100644
index 8d0721c14e..0000000000
--- a/test/console_edit.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test console editing and history.
- */
-
-#include "common.h"
-#include "console.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int cmd_1_call_cnt;
-static int cmd_2_call_cnt;
-
-static int command_test_1(int argc, char **argv)
-{
-	cmd_1_call_cnt++;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(test1, command_test_1, NULL, NULL);
-
-static int command_test_2(int argc, char **argv)
-{
-	cmd_2_call_cnt++;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(test2, command_test_2, NULL, NULL);
-
-/*****************************************************************************/
-/* Test utilities */
-
-enum arrow_key_t {
-	ARROW_UP = 0,
-	ARROW_DOWN,
-	ARROW_RIGHT,
-	ARROW_LEFT,
-};
-
-static void arrow_key(enum arrow_key_t k, int repeat)
-{
-	static char seq[4] = {0x1B, '[', 0, 0};
-	seq[2] = 'A' + k;
-	while (repeat--)
-		UART_INJECT(seq);
-}
-
-static void delete_key(void)
-{
-	UART_INJECT("\x1b[3~");
-}
-
-static void home_key(void)
-{
-	UART_INJECT("\x1b[1~");
-}
-
-static void end_key(void)
-{
-	UART_INJECT("\x1bOF");
-}
-
-static void ctrl_key(char c)
-{
-	static char seq[2] = {0, 0};
-	seq[0] = c - '@';
-	UART_INJECT(seq);
-}
-
-/*
- * Helper function to compare multiline strings. When comparing, CR's are
- * ignored.
- */
-static int compare_multiline_string(const char *s1, const char *s2)
-{
-	do {
-		while (*s1 == '\r')
-			++s1;
-		while (*s2 == '\r')
-			++s2;
-		if (*s1 != *s2)
-			return 1;
-		if (*s1 == 0 && *s2 == 0)
-			break;
-		++s1;
-		++s2;
-	} while (1);
-
-	return 0;
-}
-
-/*****************************************************************************/
-/* Tests */
-
-static int test_backspace(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("testx\b1\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_insert_char(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("tet1");
-	arrow_key(ARROW_LEFT, 2);
-	UART_INJECT("s\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_delete_char(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("testt1");
-	arrow_key(ARROW_LEFT, 1);
-	UART_INJECT("\b\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_insert_delete_char(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("txet1");
-	arrow_key(ARROW_LEFT, 4);
-	delete_key();
-	arrow_key(ARROW_RIGHT, 1);
-	UART_INJECT("s\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_home_end_key(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("est");
-	home_key();
-	UART_INJECT("t");
-	end_key();
-	UART_INJECT("1\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_ctrl_k(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("test123");
-	arrow_key(ARROW_LEFT, 2);
-	ctrl_key('K');
-	UART_INJECT("\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
-}
-
-static int test_history_up(void)
-{
-	cmd_1_call_cnt = 0;
-	UART_INJECT("test1\n");
-	msleep(30);
-	arrow_key(ARROW_UP, 1);
-	UART_INJECT("\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2);
-}
-
-static int test_history_up_up(void)
-{
-	cmd_1_call_cnt = 0;
-	cmd_2_call_cnt = 0;
-	UART_INJECT("test1\n");
-	msleep(30);
-	UART_INJECT("test2\n");
-	msleep(30);
-	arrow_key(ARROW_UP, 2);
-	UART_INJECT("\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1);
-}
-
-static int test_history_up_up_down(void)
-{
-	cmd_1_call_cnt = 0;
-	cmd_2_call_cnt = 0;
-	UART_INJECT("test1\n");
-	msleep(30);
-	UART_INJECT("test2\n");
-	msleep(30);
-	arrow_key(ARROW_UP, 2);
-	arrow_key(ARROW_DOWN, 1);
-	UART_INJECT("\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2);
-}
-
-static int test_history_edit(void)
-{
-	cmd_1_call_cnt = 0;
-	cmd_2_call_cnt = 0;
-	UART_INJECT("test1\n");
-	msleep(30);
-	arrow_key(ARROW_UP, 1);
-	UART_INJECT("\b2\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
-}
-
-static int test_history_stash(void)
-{
-	cmd_1_call_cnt = 0;
-	cmd_2_call_cnt = 0;
-	UART_INJECT("test1\n");
-	msleep(30);
-	UART_INJECT("test");
-	arrow_key(ARROW_UP, 1);
-	arrow_key(ARROW_DOWN, 1);
-	UART_INJECT("2\n");
-	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
-}
-
-static int test_history_list(void)
-{
-	const char *exp_output = "history\n" /* Input command */
-				 "test3\n"   /* Output 4 last commands */
-				 "test4\n"
-				 "test5\n"
-				 "history\n"
-				 "> ";
-
-	UART_INJECT("test1\n");
-	UART_INJECT("test2\n");
-	UART_INJECT("test3\n");
-	UART_INJECT("test4\n");
-	UART_INJECT("test5\n");
-	msleep(30);
-	test_capture_console(1);
-	UART_INJECT("history\n");
-	msleep(30);
-	test_capture_console(0);
-	TEST_ASSERT(compare_multiline_string(test_get_captured_console(),
-					     exp_output) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_output_channel(void)
-{
-	UART_INJECT("chan save\n");
-	msleep(30);
-	UART_INJECT("chan 0\n");
-	msleep(30);
-	test_capture_console(1);
-	cprintf(CC_SYSTEM, "shouldn't see this\n");
-	cputs(CC_TASK, "shouldn't see this either\n");
-	cflush();
-	test_capture_console(0);
-	TEST_ASSERT(compare_multiline_string(test_get_captured_console(),
-					     "") == 0);
-	UART_INJECT("chan restore\n");
-	msleep(30);
-	test_capture_console(1);
-	cprintf(CC_SYSTEM, "see me\n");
-	cputs(CC_TASK, "me as well\n");
-	cflush();
-	test_capture_console(0);
-	TEST_ASSERT(compare_multiline_string(test_get_captured_console(),
-					     "see me\nme as well\n") == 0);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_backspace);
-	RUN_TEST(test_insert_char);
-	RUN_TEST(test_delete_char);
-	RUN_TEST(test_insert_delete_char);
-	RUN_TEST(test_home_end_key);
-	RUN_TEST(test_ctrl_k);
-	RUN_TEST(test_history_up);
-	RUN_TEST(test_history_up_up);
-	RUN_TEST(test_history_up_up_down);
-	RUN_TEST(test_history_edit);
-	RUN_TEST(test_history_stash);
-	RUN_TEST(test_history_list);
-	RUN_TEST(test_output_channel);
-
-	test_print_result();
-}
diff --git a/test/console_edit.tasklist b/test/console_edit.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/console_edit.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/crc.c b/test/crc.c
deleted file mode 100644
index e65be72ace..0000000000
--- a/test/crc.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests crc32 sw implementation.
- */
-
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "crc8.h"
-#include "test_util.h"
-#include "util.h"
-
-// test that static version matches context version
-static int test_static_version(void)
-{
-	uint32_t crc;
-	const uint32_t input = 0xdeadbeef;
-
-	crc32_ctx_init(&crc);
-	crc32_ctx_hash32(&crc, input);
-
-	crc32_init();
-	crc32_hash32(input);
-	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
-
-	crc32_init();
-	crc32_hash(&input, sizeof(input));
-	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
-
-	return EC_SUCCESS;
-}
-
-// test that context bytes at a time matches static word at time
-static int test_8(void)
-{
-	uint32_t crc;
-	const uint32_t input = 0xdeadbeef;
-	const uint8_t *p = (const uint8_t *) &input;
-	int i;
-
-	crc32_init();
-	crc32_hash32(input);
-
-	crc32_ctx_init(&crc);
-	for (i = 0; i < sizeof(input); ++i)
-		crc32_ctx_hash8(&crc, p[i]);
-
-	TEST_ASSERT(crc32_result() == crc32_ctx_result(&crc));
-
-	return EC_SUCCESS;
-}
-
-// http://www.febooti.com/products/filetweak/members/hash-and-crc/test-vectors/
-static int test_kat0(void)
-{
-	uint32_t crc;
-	int i;
-	const char input[] = "The quick brown fox jumps over the lazy dog";
-
-	crc32_ctx_init(&crc);
-	for (i = 0; i < strlen(input); ++i)
-		crc32_ctx_hash8(&crc, input[i]);
-	TEST_ASSERT(crc32_ctx_result(&crc) == 0x414fa339);
-
-	crc32_ctx_init(&crc);
-	crc32_ctx_hash(&crc, input, strlen(input));
-	TEST_ASSERT(crc32_ctx_result(&crc) == 0x414fa339);
-
-	return EC_SUCCESS;
-}
-
-static int test_cros_crc8(void)
-{
-	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
-
-	int crc = cros_crc8(buffer, 10);
-
-	/* Verifies polynomial values of 0x07 representing x^8 + x^2 + x + 1 */
-	TEST_EQ(crc, 170, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_static_version);
-	RUN_TEST(test_8);
-	RUN_TEST(test_kat0);
-	RUN_TEST(test_cros_crc8);
-
-	test_print_result();
-}
diff --git a/test/crc.tasklist b/test/crc.tasklist
deleted file mode 100644
index f46a2eaa1d..0000000000
--- a/test/crc.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/entropy.c b/test/entropy.c
deleted file mode 100644
index fb066a6c5b..0000000000
--- a/test/entropy.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests entropy source.
- */
-
-#include "console.h"
-#include "common.h"
-#include "rollback.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-static int buckets[256];
-
-static const int log2_mult = 2;
-
-/*
- * log2 (multiplied by 2). For non-power of 2, this rounds to the closest
- * half-integer, otherwise the value is exact.
- */
-uint32_t log2(int32_t val)
-{
-	int val1 = 31 - __builtin_clz(val);
-	int val2 = 32 - __builtin_clz(val - 1);
-
-	return log2_mult * (val1 + val2)/2;
-}
-
-void run_test(int argc, char **argv)
-{
-	const int loopcount = 512;
-
-	uint8_t buffer[32];
-	timestamp_t t0, t1;
-	int i, j;
-	uint32_t entropy;
-	const int totalcount = loopcount * sizeof(buffer);
-	const int log2totalcount = log2(totalcount);
-
-	memset(buckets, 0, sizeof(buckets));
-
-	for (i = 0; i < loopcount; i++) {
-		t0 = get_time();
-		if (!board_get_entropy(buffer, sizeof(buffer))) {
-			ccprintf("Cannot get entropy\n");
-			test_fail();
-			return;
-		}
-		t1 = get_time();
-		if (i == 0)
-			ccprintf("Got %zd bytes in %" PRId64 " us\n",
-				sizeof(buffer), t1.val - t0.val);
-
-		for (j = 0; j < sizeof(buffer); j++)
-			buckets[buffer[j]]++;
-
-		watchdog_reload();
-	}
-
-	ccprintf("Total count: %d\n", totalcount);
-	ccprintf("Buckets: ");
-	entropy = 0;
-	for (j = 0; j < 256; j++) {
-		/*
-		 * Shannon entropy (base 2) is sum of -p[j] * log_2(p[j]).
-		 * p[j] = buckets[j]/totalcount
-		 * -p[j] * log_2(p[j])
-		 *  = -(buckets[j]/totalcount) * log_2(buckets[j]/totalcount)
-		 *  = buckets[j] * (log_2(totalcount) - log_2(buckets[j]))
-		 *                                               / totalcount
-		 * Our log2() function is scaled by log2_mult, and we defer the
-		 * division by totalcount until we get the total sum, so we need
-		 * to divide by (log2_mult * totalcount) at the end.
-		 */
-		entropy += buckets[j] * (log2totalcount - log2(buckets[j]));
-		ccprintf("%d;", buckets[j]);
-		cflush();
-	}
-	ccprintf("\n");
-
-	ccprintf("Entropy: %u/1000 bits\n",
-		entropy * 1000 / (log2_mult * totalcount));
-
-	/* We want at least 2 bits of entropy (out of a maximum of 8) */
-	if ((entropy / (log2_mult * totalcount)) >= 2)
-		test_pass();
-	else
-		test_fail();
-}
diff --git a/test/entropy.tasklist b/test/entropy.tasklist
deleted file mode 100644
index 80072bb620..0000000000
--- a/test/entropy.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/extpwr_gpio.c b/test/extpwr_gpio.c
deleted file mode 100644
index d1f77c9167..0000000000
--- a/test/extpwr_gpio.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test GPIO extpower module.
- */
-
-#include "common.h"
-#include "console.h"
-#include "extpower.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int ac_hook_count;
-
-static void set_ac(int val)
-{
-	gpio_set_level(GPIO_AC_PRESENT, val);
-	msleep(50);
-}
-
-static void ac_change_hook(void)
-{
-	ac_hook_count++;
-}
-DECLARE_HOOK(HOOK_AC_CHANGE, ac_change_hook, HOOK_PRIO_DEFAULT);
-
-static int test_hook(void)
-{
-	/* Remove AC for testing */
-	set_ac(0);
-	ac_hook_count = 0;
-	host_clear_events(0xffffffff);
-
-	set_ac(1);
-	TEST_ASSERT(ac_hook_count == 1);
-	TEST_ASSERT(extpower_is_present());
-	TEST_ASSERT(host_get_events() &
-		    EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED));
-
-	set_ac(0);
-	TEST_ASSERT(ac_hook_count == 2);
-	TEST_ASSERT(!extpower_is_present());
-	TEST_ASSERT(host_get_events() &
-		    EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED));
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_hook);
-
-	test_print_result();
-}
diff --git a/test/extpwr_gpio.tasklist b/test/extpwr_gpio.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/extpwr_gpio.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/fake_battery.c b/test/fake_battery.c
deleted file mode 100644
index 4442300572..0000000000
--- a/test/fake_battery.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Fake BATTERY module.
- */
-#include "battery.h"
-#include "common.h"
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = 0;
-	return 0;
-}
-
-enum battery_present battery_is_present(void)
-{
-	return BP_NO;
-}
-
-int battery_design_capacity(int *capacity)
-{
-	*capacity = 0;
-	return 0;
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	*capacity = 0;
-	return 0;
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	*capacity = 0;
-	return 0;
-}
-
-int battery_status(int *status)
-{
-	return EC_ERROR_UNIMPLEMENTED;
-}
diff --git a/test/fake_usbc.c b/test/fake_usbc.c
deleted file mode 100644
index dc631997cf..0000000000
--- a/test/fake_usbc.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Type-C module.
- */
-#include "common.h"
-#include "usb_tc_sm.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-
-__overridable int pd_is_vbus_present(int port)
-{
-	return 0;
-}
-
-__overridable void pd_request_data_swap(int port)
-{}
-
-__overridable void pd_request_power_swap(int port)
-{}
-
-void pd_request_vconn_swap_off(int port)
-{}
-
-void pd_request_vconn_swap_on(int port)
-{}
-
-
-static enum pd_data_role data_role;
-__overridable enum pd_data_role pd_get_data_role(int port)
-{
-	return data_role;
-}
-__overridable void tc_set_data_role(int port, enum pd_data_role role)
-{
-	data_role = role;
-}
-
-static enum pd_power_role power_role;
-__overridable enum pd_power_role pd_get_power_role(int port)
-{
-	return power_role;
-}
-__overridable void tc_set_power_role(int port, enum pd_power_role role)
-{
-	power_role = role;
-}
-
-__overridable bool pd_get_partner_usb_comm_capable(int port)
-{
-	return true;
-}
-
-__overridable enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	return PD_PLUG_FROM_DFP_UFP;
-}
-
-__overridable int pd_get_rev(int port, enum tcpci_msg_type type)
-{
-	return IS_ENABLED(CONFIG_USB_PD_REV30) ? PD_REV30 : PD_REV20;
-}
-
-int tc_check_vconn_swap(int port)
-{
-	return 0;
-}
-
-void tc_ctvpd_detected(int port)
-{}
-
-void tc_disc_ident_complete(int port)
-{}
-
-static int attached_snk;
-int tc_is_attached_snk(int port)
-{
-	return attached_snk;
-}
-
-static int attached_src;
-int tc_is_attached_src(int port)
-{
-	return attached_src;
-}
-
-int tc_is_vconn_src(int port)
-{
-	return 0;
-}
-
-void tc_hard_reset_request(int port)
-{}
-
-void tc_hard_reset_complete(int port)
-{}
-
-void tc_partner_dr_data(int port, int en)
-{}
-
-void tc_partner_dr_power(int port, int en)
-{}
-
-void tc_partner_unconstrainedpower(int port, int en)
-{}
-
-void tc_partner_usb_comm(int port, int en)
-{}
-
-void tc_pd_connection(int port, int en)
-{}
-
-void tc_pr_swap_complete(int port, bool success)
-{}
-
-void tc_prs_snk_src_assert_rp(int port)
-{
-	attached_snk = 0;
-	attached_src = 1;
-}
-
-void tc_prs_src_snk_assert_rd(int port)
-{
-	attached_snk = 1;
-	attached_src = 0;
-}
-
-void tc_src_power_off(int port)
-{}
-
-void tc_set_timeout(int port, uint64_t timeout)
-{}
-
-__overridable void tc_start_error_recovery(int port)
-{}
-
-__overridable void tc_snk_power_off(int port)
-{}
-
-__overridable void pe_invalidate_explicit_contract(int port)
-{
-}
-
-__overridable enum pd_dual_role_states pd_get_dual_role(int port)
-{
-	return PD_DRP_TOGGLE_ON;
-}
-
-__overridable void pd_dev_get_rw_hash(int port, uint16_t *dev_id,
-		uint8_t *rw_hash, uint32_t *current_image)
-{
-}
-
-__overridable int pd_comm_is_enabled(int port)
-{
-	return 0;
-}
-
-bool pd_get_partner_data_swap_capable(int port)
-{
-	return true;
-}
-
-bool pd_capable(int port)
-{
-	return true;
-}
-
-bool pd_waiting_on_partner_src_caps(int port)
-{
-	return false;
-}
-
-#ifndef CONFIG_TEST_USB_PE_SM
-enum idh_ptype get_usb_pd_mux_cable_type(int port)
-{
-	return IDH_PTYPE_UNDEF;
-}
-
-const uint32_t * const pd_get_src_caps(int port)
-{
-	return NULL;
-}
-
-void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
-{
-}
-
-uint8_t pd_get_src_cap_cnt(int port)
-{
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && \
-	!defined(CONFIG_USB_CTVPD)
-int pd_is_connected(int port)
-{
-	return true;
-}
-
-bool pd_is_disconnected(int port)
-{
-	return false;
-}
-#endif /* !CONFIG_USB_DRP_ACC_TRYSRC && !CONFIG_USB_CTVPD */
-
-#ifndef CONFIG_USB_DRP_ACC_TRYSRC
-__overridable void pd_set_dual_role(int port, enum pd_dual_role_states state)
-{
-}
-
-__overridable enum tcpc_cc_polarity pd_get_polarity(int port)
-{
-	return POLARITY_CC1;
-}
-
-bool pd_get_vconn_state(int port)
-{
-	return false;
-}
-
-bool pd_get_partner_dual_role_power(int port)
-{
-	return false;
-}
-
-uint8_t pd_get_task_state(int port)
-{
-	return 0;
-}
-
-enum pd_cc_states pd_get_task_cc_state(int port)
-{
-	return PD_CC_NONE;
-}
-
-bool pd_get_partner_unconstr_power(int port)
-{
-	return 0;
-}
-
-const char *pd_get_task_state_name(int port)
-{
-	return NULL;
-}
-#endif /* CONFIG_USB_DRP_ACC_TRYSRC */
-
-void dp_init(int port)
-{
-}
-
-void dp_vdm_acked(int port, int cmd)
-{
-}
-
-void dpm_init(int port)
-{
-}
-
-void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
-{
-}
-
-void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
-{
-}
-
-void dpm_set_mode_entry_done(int port)
-{
-}
-
-void dpm_set_mode_exit_request(int port)
-{
-}
-
-void dpm_run(int port)
-{
-}
-
-void dpm_evaluate_sink_fixed_pdo(int port, uint32_t vsafe5v_pdo)
-{
-}
-
-void dpm_add_non_pd_sink(int port)
-{
-}
-
-void dpm_remove_sink(int port)
-{
-}
-
-void dpm_remove_source(int port)
-{
-}
-
-int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
-{
-	*src_pdo = pd_src_pdo;
-	return pd_src_pdo_cnt;
-}
-
-static enum tcpc_rp_value lcl_rp;
-__overridable void typec_select_src_current_limit_rp(int port,
-						  enum tcpc_rp_value rp)
-{
-	lcl_rp = rp;
-}
-__overridable void typec_select_src_collision_rp(int port,
-						 enum tcpc_rp_value rp)
-{
-	lcl_rp = rp;
-}
-__overridable int typec_update_cc(int port)
-{
-	return EC_SUCCESS;
-}
diff --git a/test/fan.c b/test/fan.c
deleted file mode 100644
index d03aa0213c..0000000000
--- a/test/fan.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test thermal engine.
- */
-
-#include "common.h"
-#include "console.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "printf.h"
-#include "temp_sensor.h"
-#include "test_util.h"
-#include "thermal.h"
-#include "timer.h"
-#include "util.h"
-
-#define FAN_RPM(fan)	fans[fan].rpm
-
-/*****************************************************************************/
-/* Tests */
-
-void set_thermal_control_enabled(int fan, int enable);
-
-static int test_fan(void)
-{
-	/* "actual" fan speed from board/host/fan.c */
-	extern int mock_rpm;
-
-	sleep(2);
-
-	/* Fans initialize disabled. */
-	TEST_ASSERT(fan_get_rpm_actual(0) == 0);
-
-	set_thermal_control_enabled(0, 1);
-
-	/*
-	 * fan_set_percent_needed() is normally called once a second by the
-	 * thermal task, but we're not using a thermal test in this test so
-	 * we can dink around with the fans without having to wait. The host
-	 * implementation just sets mock_rpm to whatever it's asked for.
-	 */
-
-	/* Off */
-	fan_set_percent_needed(0, 0);
-	TEST_ASSERT(fan_get_rpm_actual(0) == 0);
-	fan_set_percent_needed(0, 0);
-	TEST_ASSERT(fan_get_rpm_actual(0) == 0);
-
-	/* On, but just barely */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_start);
-	/* fan is above min speed now, so should be set to min */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-
-	/* Full speed */
-	fan_set_percent_needed(0, 100);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_max);
-	fan_set_percent_needed(0, 100);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_max);
-
-	/* Slow again */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-
-	/* Off */
-	fan_set_percent_needed(0, 0);
-	TEST_ASSERT(fan_get_rpm_actual(0) == 0);
-	fan_set_percent_needed(0, 0);
-	TEST_ASSERT(fan_get_rpm_actual(0) == 0);
-
-	/* On, but just barely */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_start);
-	/* Force the mock_rpm to be slow, to simulate dragging */
-	mock_rpm = FAN_RPM(0)->rpm_min - 105;
-	/* It should keep trying for the start speed */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_start);
-	/* But we have to keep forcing the mock_rpm back down */
-	mock_rpm = FAN_RPM(0)->rpm_min - 105;
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_start);
-	/* Now let it turn just under rpm_min. Should be okay there. */
-	mock_rpm = FAN_RPM(0)->rpm_min - 10;
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-	/* Let it go a little faster, still okay */
-	mock_rpm = FAN_RPM(0)->rpm_min + 10;
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-	/* But if it drops too low, it should go back to the start speed */
-	mock_rpm = FAN_RPM(0)->rpm_min - 105;
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_start);
-	/* And then relax */
-	fan_set_percent_needed(0, 1);
-	TEST_ASSERT(fan_get_rpm_actual(0) == FAN_RPM(0)->rpm_min);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_fan);
-
-	test_print_result();
-}
diff --git a/test/fan.tasklist b/test/fan.tasklist
deleted file mode 100644
index 25dcf124db..0000000000
--- a/test/fan.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST   /* No test task */
diff --git a/test/flash.c b/test/flash.c
deleted file mode 100644
index 4f9ca74016..0000000000
--- a/test/flash.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Console commands to trigger flash host commands */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "flash.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int mock_wp = -1;
-
-static int mock_flash_op_fail = EC_SUCCESS;
-
-const char *testdata = "TestData00000000"; /* 16 bytes excluding NULL end */
-
-char flash_recorded_data[128];
-
-#define BOOT_WP_MASK TEST_STATE_MASK(TEST_STATE_STEP_2)
-
-/*****************************************************************************/
-/* Emulator-only mock functions */
-#ifdef EMU_BUILD
-static int mock_is_running_img;
-
-int system_unsafe_to_overwrite(uint32_t offset, uint32_t size)
-{
-	return mock_is_running_img;
-}
-#endif
-
-/*****************************************************************************/
-/* Mock functions */
-void host_send_response(struct host_cmd_handler_args *args)
-{
-	/* Do nothing */
-}
-
-int flash_pre_op(void)
-{
-	return mock_flash_op_fail;
-}
-
-int gpio_get_level(enum gpio_signal signal)
-{
-	if (mock_wp == -1)
-		mock_wp = !!(test_get_state() & BOOT_WP_MASK);
-
-#if defined(CONFIG_WP_ACTIVE_HIGH)
-	if (signal == GPIO_WP)
-		return mock_wp;
-#else
-	if (signal == GPIO_WP_L)
-		return !mock_wp;
-#endif
-
-	/* Signal other than write protect. Just return 0. */
-	return 0;
-}
-
-/*****************************************************************************/
-/* Test utilities */
-
-static void record_flash(int offset, int size)
-{
-	memcpy(flash_recorded_data, __host_flash + offset, size);
-}
-
-static int verify_flash(int offset, int size)
-{
-	TEST_ASSERT_ARRAY_EQ(flash_recorded_data, __host_flash + offset, size);
-	return EC_SUCCESS;
-}
-
-static int verify_write(int offset, int size, const char *data)
-{
-	int i;
-
-	for (i = 0; i < size; ++i)
-		if (__host_flash[offset + i] != data[i])
-			return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-static int verify_erase(int offset, int size)
-{
-	int i;
-
-	for (i = 0; i < size; ++i)
-		if ((__host_flash[offset + i] & 0xff) != 0xff)
-			return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-
-#define VERIFY_NO_WRITE(off, sz, d) \
-	do { \
-		record_flash(off, sz); \
-		TEST_ASSERT(host_command_write(off, sz, d) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
-	} while (0)
-
-#define VERIFY_NO_ERASE(off, sz) \
-	do { \
-		record_flash(off, sz); \
-		TEST_ASSERT(host_command_erase(off, sz) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
-	} while (0)
-
-#define VERIFY_WRITE(off, sz, d) \
-	do { \
-		TEST_ASSERT(host_command_write(off, sz, d) == EC_SUCCESS); \
-		TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS); \
-	} while (0)
-
-#define VERIFY_ERASE(off, sz) \
-	do { \
-		TEST_ASSERT(host_command_erase(off, sz) == EC_SUCCESS); \
-		TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS); \
-	} while (0)
-
-#define SET_WP_FLAGS(m, f) \
-	TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), \
-				NULL, NULL, NULL) == EC_RES_SUCCESS)
-
-#define ASSERT_WP_FLAGS(f) \
-	do { \
-		uint32_t flags; \
-		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(flags & (f)); \
-	} while (0)
-
-#define ASSERT_WP_NO_FLAGS(f) \
-	do { \
-		uint32_t flags; \
-		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT((flags & (f)) == 0); \
-	} while (0)
-
-#define VERIFY_REGION_INFO(r, o, s) \
-	do { \
-		uint32_t offset, size; \
-		TEST_ASSERT(host_command_region_info(r, &offset, &size) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(offset == (o)); \
-		TEST_ASSERT(size == (s)); \
-	} while (0)
-
-int host_command_read(int offset, int size, char *out)
-{
-	struct ec_params_flash_read params;
-
-	params.offset = offset;
-	params.size = size;
-
-	return test_send_host_command(EC_CMD_FLASH_READ, 0, &params,
-				      sizeof(params), out, size);
-}
-
-int host_command_write(int offset, int size, const char *data)
-{
-	uint8_t buf[256];
-	struct ec_params_flash_write *params =
-		(struct ec_params_flash_write *)buf;
-
-	params->offset = offset;
-	params->size = size;
-	memcpy(params + 1, data, size);
-
-	return test_send_host_command(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE,
-				      buf, size + sizeof(*params), NULL, 0);
-}
-
-int host_command_erase(int offset, int size)
-{
-	struct ec_params_flash_write params;
-
-	params.offset = offset;
-	params.size = size;
-
-	return test_send_host_command(EC_CMD_FLASH_ERASE, 0, &params,
-				      sizeof(params), NULL, 0);
-}
-
-int host_command_protect(uint32_t mask, uint32_t flags,
-			 uint32_t *flags_out, uint32_t *valid_out,
-			 uint32_t *writable_out)
-{
-	struct ec_params_flash_protect params;
-	struct ec_response_flash_protect resp;
-	int res;
-
-	params.mask = mask;
-	params.flags = flags;
-
-	res = test_send_host_command(EC_CMD_FLASH_PROTECT, 1, &params,
-				     sizeof(params), &resp, sizeof(resp));
-
-	if (res == EC_RES_SUCCESS) {
-		if (flags_out)
-			*flags_out = resp.flags;
-		if (valid_out)
-			*valid_out = resp.valid_flags;
-		if (writable_out)
-			*writable_out = resp.writable_flags;
-	}
-
-	return res;
-}
-
-int host_command_region_info(enum ec_flash_region reg, uint32_t *offset,
-				 uint32_t *size)
-{
-	struct ec_params_flash_region_info params;
-	struct ec_response_flash_region_info resp;
-	int res;
-
-	params.region = reg;
-
-	res = test_send_host_command(EC_CMD_FLASH_REGION_INFO, 1, &params,
-				     sizeof(params), &resp, sizeof(resp));
-
-	*offset = resp.offset;
-	*size = resp.size;
-
-	return res;
-}
-
-/*****************************************************************************/
-/* Tests */
-static int test_read(void)
-{
-	char buf[16];
-
-#ifdef EMU_BUILD
-	int i;
-	/* Fill in some numbers so they are not all 0xff */
-	for (i = 0; i < sizeof(buf); ++i)
-		__host_flash[i] = i * i + i;
-#endif
-
-	/* The first few bytes in the flash should always contain some code */
-	TEST_ASSERT(!crec_flash_is_erased(0, sizeof(buf)));
-
-	TEST_ASSERT(host_command_read(0, sizeof(buf), buf) == EC_RES_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(buf, (char *)CONFIG_PROGRAM_MEMORY_BASE,
-			     sizeof(buf));
-
-	return EC_SUCCESS;
-}
-
-static int test_is_erased(void)
-{
-	int i;
-
-#ifdef EMU_BUILD
-	memset(__host_flash, 0xff, 1024);
-	TEST_ASSERT(crec_flash_is_erased(0, 1024));
-
-	for (i = 0; i < 1024; ++i) {
-		__host_flash[i] = 0xec;
-		TEST_ASSERT(!crec_flash_is_erased(0, 1024));
-		__host_flash[i] = 0xff;
-	}
-#else
-	ccprintf("Skip. Emulator only test.\n");
-#endif
-
-	return EC_SUCCESS;
-}
-
-static int test_overwrite_current(void)
-{
-	uint32_t offset, size;
-
-	/* Test that we cannot overwrite current image */
-	if (system_get_image_copy() == EC_IMAGE_RO) {
-		offset = CONFIG_RO_STORAGE_OFF;
-		size = CONFIG_RO_SIZE;
-	} else {
-		offset = CONFIG_RW_STORAGE_OFF;
-		size = CONFIG_RW_SIZE;
-	}
-
-#ifdef EMU_BUILD
-	mock_is_running_img = 1;
-#endif
-
-	VERIFY_NO_ERASE(offset, strlen(testdata));
-	VERIFY_NO_ERASE(offset + size - strlen(testdata), strlen(testdata));
-	VERIFY_NO_WRITE(offset, strlen(testdata), testdata);
-	VERIFY_NO_WRITE(offset + size - strlen(testdata), strlen(testdata),
-			testdata);
-
-	return EC_SUCCESS;
-}
-
-static int test_overwrite_other(void)
-{
-	uint32_t offset, size;
-
-	/* Test that we can overwrite the other image */
-	if (system_is_in_rw()) {
-		offset = CONFIG_RO_STORAGE_OFF;
-		size = CONFIG_RO_SIZE;
-	} else {
-		offset = CONFIG_RW_STORAGE_OFF;
-		size = CONFIG_RW_SIZE;
-	}
-
-#ifdef EMU_BUILD
-	mock_is_running_img = 0;
-#endif
-
-	VERIFY_ERASE(offset, strlen(testdata));
-	VERIFY_ERASE(offset + size - strlen(testdata), strlen(testdata));
-	VERIFY_WRITE(offset, strlen(testdata), testdata);
-	VERIFY_WRITE(offset + size - strlen(testdata), strlen(testdata),
-		     testdata);
-
-	return EC_SUCCESS;
-}
-
-static int test_op_failure(void)
-{
-	mock_flash_op_fail = EC_ERROR_UNKNOWN;
-	VERIFY_NO_WRITE(CONFIG_RO_STORAGE_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_WRITE(CONFIG_RW_STORAGE_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_ERASE(CONFIG_RW_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
-	mock_flash_op_fail = EC_SUCCESS;
-
-	return EC_SUCCESS;
-}
-
-static int test_flash_info(void)
-{
-	struct ec_response_flash_info_1 resp;
-
-	TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0,
-		    &resp, sizeof(resp)) == EC_RES_SUCCESS);
-
-	TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE_BYTES) &&
-		   (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) &&
-		   (resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE) &&
-		   (resp.protect_block_size == CONFIG_FLASH_BANK_SIZE));
-}
-
-static int test_region_info(void)
-{
-	VERIFY_REGION_INFO(EC_FLASH_REGION_RO,
-			   CONFIG_EC_PROTECTED_STORAGE_OFF +
-			   CONFIG_RO_STORAGE_OFF, EC_FLASH_REGION_RO_SIZE);
-	VERIFY_REGION_INFO(EC_FLASH_REGION_ACTIVE,
-			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
-			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
-	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO,
-			   CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE);
-	VERIFY_REGION_INFO(EC_FLASH_REGION_UPDATE,
-			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
-			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
-
-	return EC_SUCCESS;
-}
-
-static int test_write_protect(void)
-{
-	/* Test we can control write protect GPIO */
-	mock_wp = 0;
-	ASSERT_WP_NO_FLAGS(EC_FLASH_PROTECT_GPIO_ASSERTED);
-
-	mock_wp = 1;
-	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_GPIO_ASSERTED);
-
-	/* Test software WP can be disable if nothing is actually protected */
-	SET_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT, 1);
-	SET_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
-	ASSERT_WP_NO_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	/* Actually protect flash and test software WP cannot be disabled */
-	SET_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT, 1);
-	SET_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW, 1);
-	SET_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
-	SET_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW, 0);
-	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	/* Check we cannot erase anything */
-	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
-	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RW_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
-
-	/* We should not even try to write/erase */
-	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_ERASE(CONFIG_RW_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_WRITE(CONFIG_RO_STORAGE_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_WRITE(CONFIG_RW_STORAGE_OFF, sizeof(testdata), testdata);
-
-	return EC_SUCCESS;
-}
-
-static int test_boot_write_protect(void)
-{
-	/* Check write protect state persists through reboot */
-	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
-	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int test_boot_no_write_protect(void)
-{
-	/* Check write protect is not enabled if WP GPIO is deasserted */
-	ASSERT_WP_NO_FLAGS(EC_FLASH_PROTECT_RO_NOW);
-	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	return EC_SUCCESS;
-}
-
-int test_clean_up_(void)
-{
-	SET_WP_FLAGS(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
-	return EC_SUCCESS;
-}
-
-void test_clean_up(void)
-{
-	test_clean_up_(); /* Throw away return value */
-}
-
-static void run_test_step1(void)
-{
-	test_reset();
-	mock_wp = 0;
-
-	RUN_TEST(test_read);
-	RUN_TEST(test_is_erased);
-	RUN_TEST(test_overwrite_current);
-	RUN_TEST(test_overwrite_other);
-	RUN_TEST(test_op_failure);
-	RUN_TEST(test_flash_info);
-	RUN_TEST(test_region_info);
-	RUN_TEST(test_write_protect);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_STEP_2);
-}
-
-static void run_test_step2(void)
-{
-	RUN_TEST(test_boot_write_protect);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_STEP_3);
-}
-
-static void run_test_step3(void)
-{
-	RUN_TEST(test_boot_no_write_protect);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_PASSED);
-}
-
-void test_run_step(uint32_t state)
-{
-	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1))
-		run_test_step1();
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2))
-		run_test_step2();
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3))
-		run_test_step3();
-}
-
-int task_test(void *data)
-{
-	test_run_multistep();
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	msleep(30); /* Wait for TASK_ID_TEST to initialize */
-	task_wake(TASK_ID_TEST);
-}
diff --git a/test/flash.tasklist b/test/flash.tasklist
deleted file mode 100644
index dae84c1635..0000000000
--- a/test/flash.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/flash_physical.c b/test/flash_physical.c
deleted file mode 100644
index 06dd495254..0000000000
--- a/test/flash_physical.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chip/stm32/flash-regs.h"
-#include "flash.h"
-#include "panic.h"
-#include "test_util.h"
-
-struct flash_info {
-	int num_flash_banks;
-	int write_protect_bank_offset;
-	int write_protect_bank_count;
-};
-
-#if defined(CHIP_VARIANT_STM32F412)
-struct flash_info flash_info = {
-	.num_flash_banks = 12,
-	.write_protect_bank_offset = 0,
-	.write_protect_bank_count = 5,
-};
-#elif defined(CHIP_VARIANT_STM32H7X3)
-struct flash_info flash_info = {
-	.num_flash_banks = 16,
-	.write_protect_bank_offset = 0,
-	.write_protect_bank_count = 6,
-};
-#else
-#error "Flash info not defined for this chip. Please add it."
-#endif
-
-
-test_static int test_lock_option_bytes(void)
-{
-	TEST_EQ(flash_option_bytes_locked(), true, "%d");
-
-	unlock_flash_option_bytes();
-
-	TEST_EQ(flash_option_bytes_locked(), false, "%d");
-
-	lock_flash_option_bytes();
-
-	TEST_EQ(flash_option_bytes_locked(), true, "%d");
-
-	unlock_flash_option_bytes();
-
-	TEST_EQ(flash_option_bytes_locked(), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_disable_option_bytes(void)
-{
-	TEST_EQ(flash_option_bytes_locked(), false, "%d");
-
-	disable_flash_option_bytes();
-
-	TEST_EQ(flash_option_bytes_locked(), true, "%d");
-
-	/* Since we've disabled the option bytes we'll get a bus fault. */
-	ignore_bus_fault(1);
-
-	unlock_flash_option_bytes();
-
-	ignore_bus_fault(0);
-
-	/* Option bytes should still be locked. */
-	TEST_EQ(flash_option_bytes_locked(), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_lock_flash_control_register(void)
-{
-	TEST_EQ(flash_control_register_locked(), true, "%d");
-
-	unlock_flash_control_register();
-
-	TEST_EQ(flash_control_register_locked(), false, "%d");
-
-	lock_flash_control_register();
-
-	TEST_EQ(flash_control_register_locked(), true, "%d");
-
-	unlock_flash_control_register();
-
-	TEST_EQ(flash_control_register_locked(), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_disable_flash_control_register(void)
-{
-	TEST_EQ(flash_control_register_locked(), false, "%d");
-
-	disable_flash_control_register();
-
-	TEST_EQ(flash_control_register_locked(), true, "%d");
-
-	/* Since we've disabled the option bytes we'll get a bus fault. */
-	ignore_bus_fault(1);
-
-	unlock_flash_control_register();
-
-	ignore_bus_fault(0);
-
-	/* Control register should still be locked. */
-	TEST_EQ(flash_control_register_locked(), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_flash_config(void)
-{
-	TEST_EQ(PHYSICAL_BANKS, flash_info.num_flash_banks, "%d");
-	TEST_EQ(WP_BANK_OFFSET, flash_info.write_protect_bank_offset, "%d");
-	TEST_EQ(WP_BANK_COUNT, flash_info.write_protect_bank_count, "%d");
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	ccprintf("Running flash physical test\n");
-	RUN_TEST(test_flash_config);
-
-	RUN_TEST(test_lock_option_bytes);
-	RUN_TEST(test_disable_option_bytes);
-	RUN_TEST(test_lock_flash_control_register);
-	RUN_TEST(test_disable_flash_control_register);
-	test_print_result();
-}
diff --git a/test/flash_physical.tasklist b/test/flash_physical.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/flash_physical.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/flash_write_protect.c b/test/flash_write_protect.c
deleted file mode 100644
index df20ede3fd..0000000000
--- a/test/flash_write_protect.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "flash.h"
-#include "gpio.h"
-#include "string.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-
-test_static int check_image_and_hardware_write_protect(void)
-{
-	int wp;
-
-	if (system_get_image_copy() != EC_IMAGE_RO) {
-		ccprintf("This test is only works when running RO\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-#ifdef CONFIG_WP_ALWAYS
-        wp = 1;
-#elif defined(CONFIG_WP_ACTIVE_HIGH)
-        wp = gpio_get_level(GPIO_WP);
-#else
-	wp = !gpio_get_level(GPIO_WP_L);
-#endif
-
-	if (!wp) {
-		ccprintf("Hardware write protect (GPIO_WP) must be enabled\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_flash_write_protect_enable(void)
-{
-	int rv;
-
-	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
-
-	/* Equivalent of ectool --name=cros_fp flashprotect enable */
-	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-				    EC_FLASH_PROTECT_RO_AT_BOOT);
-
-	return rv;
-}
-
-test_static int test_flash_write_protect_disable(void)
-{
-	int rv;
-
-	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
-
-	/* Equivalent of ectool --name=cros_fp flashprotect disable */
-	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT, 0);
-	TEST_NE(rv, EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static void run_test_step1(void)
-{
-	ccprintf("Step 1: Flash write protect test\n");
-	RUN_TEST(test_flash_write_protect_enable);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_STEP_2);
-}
-
-test_static void run_test_step2(void)
-{
-	ccprintf("Step 2: Flash write protect test\n");
-	RUN_TEST(test_flash_write_protect_disable);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else if (IS_ENABLED(CONFIG_EEPROM_CBI_WP))
-		test_reboot_to_next_step(TEST_STATE_STEP_3);
-	else
-		test_reboot_to_next_step(TEST_STATE_PASSED);
-}
-
-#ifdef CONFIG_EEPROM_CBI_WP
-test_static int test_cbi_wb_asserted_immediately(void)
-{
-	int rv;
-
-	TEST_EQ(check_image_and_hardware_write_protect(), EC_SUCCESS, "%d");
-
-	/* Ensure that EC_CBI_WP is not asserted. */
-	TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 0, "%d");
-
-	/* Equivalent of ectool --name=cros_fp flashprotect disable */
-	rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, 0);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	/* Now make sure EC_CBI_WP is asserted immediately. */
-	TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 1, "%d");
-
-
-	return EC_SUCCESS;
-}
-
-test_static void run_test_step3(void)
-{
-	ccprintf("Step 3: Flash write protect test\n");
-	RUN_TEST(test_cbi_wb_asserted_immediately);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_PASSED);
-}
-#endif /* CONFIG_EEPROM_CBI_WP */
-
-void test_run_step(uint32_t state)
-{
-	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1))
-		run_test_step1();
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2))
-		run_test_step2();
-#ifdef CONFIG_EEPROM_CBI_WP
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3))
-		run_test_step3();
-#endif /* CONFIG_EEPROM_CBI_WP */
-}
-
-int task_test(void *unused)
-{
-	test_run_multistep();
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	msleep(30); /* Wait for TASK_ID_TEST to initialize */
-	task_wake(TASK_ID_TEST);
-}
diff --git a/test/flash_write_protect.tasklist b/test/flash_write_protect.tasklist
deleted file mode 100644
index 21619decc3..0000000000
--- a/test/flash_write_protect.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(TEST, task_test, NULL, TASK_STACK_SIZE)
diff --git a/test/float.tasklist b/test/float.tasklist
deleted file mode 100644
index 9ad0114d8a..0000000000
--- a/test/float.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/fp.c b/test/fp.c
deleted file mode 100644
index 0324da6c8d..0000000000
--- a/test/fp.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Explicitly include common.h to populate predefined macros in test_config.h
- * early. e.g. CONFIG_FPU, which is needed in math_util.h
- */
-#include "common.h"
-
-#include "mat33.h"
-#include "mat44.h"
-#include "math_util.h"
-#include "test_util.h"
-#include "vec3.h"
-
-#if defined(TEST_FP) && !defined(CONFIG_FPU)
-#define NORM_TOLERANCE FLOAT_TO_FP(0.01f)
-#define NORM_SQUARED_TOLERANCE FLOAT_TO_FP(0.0f)
-#define DOT_TOLERANCE FLOAT_TO_FP(0.001f)
-#define SCALAR_MUL_TOLERANCE FLOAT_TO_FP(0.005f)
-#define EIGENBASIS_TOLERANCE FLOAT_TO_FP(0.03f)
-#define LUP_TOLERANCE FLOAT_TO_FP(0.0005f)
-#define SOLVE_TOLERANCE FLOAT_TO_FP(0.0005f)
-#elif defined(TEST_FLOAT) && defined(CONFIG_FPU)
-#define NORM_TOLERANCE FLOAT_TO_FP(0.00001f)
-#define NORM_SQUARED_TOLERANCE FLOAT_TO_FP(0.0f)
-#define DOT_TOLERANCE FLOAT_TO_FP(0.0f)
-#define SCALAR_MUL_TOLERANCE FLOAT_TO_FP(0.005f)
-#define EIGENBASIS_TOLERANCE FLOAT_TO_FP(0.02f)
-#define LUP_TOLERANCE FLOAT_TO_FP(0.00001f)
-#define SOLVE_TOLERANCE FLOAT_TO_FP(0.00001f)
-#else
-#error "No such test configuration."
-#endif
-
-#define IS_FPV3_VECTOR_EQUAL(a, b, diff)                                       \
-	(IS_FP_EQUAL((a)[0], (b)[0], (diff)) &&                                \
-	 IS_FP_EQUAL((a)[1], (b)[1], (diff)) &&                                \
-	 IS_FP_EQUAL((a)[2], (b)[2], (diff)))
-#define IS_FP_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff))
-#define IS_FLOAT_EQUAL(a, b, diff) IS_FP_EQUAL(a, b, diff)
-
-static int test_fpv3_scalar_mul(void)
-{
-	const int N = 3;
-	const float s = 2.0f;
-	floatv3_t r = {1.0f, 2.0f, 4.0f};
-	/* Golden result g = s * r; */
-	const floatv3_t g = {2.0f, 4.0f, 8.0f};
-	int i;
-	fpv3_t a;
-
-	for (i = 0; i < N; ++i)
-		a[i] = FLOAT_TO_FP(r[i]);
-
-	fpv3_scalar_mul(a, FLOAT_TO_FP(s));
-
-	for (i = 0; i < N; ++i)
-		TEST_ASSERT(IS_FP_EQUAL(a[i], FLOAT_TO_FP(g[i]), 0));
-
-	return EC_SUCCESS;
-}
-
-static int test_fpv3_dot(void)
-{
-	const int N = 3;
-	int i;
-	floatv3_t a = {1.8f, 2.12f, 4.12f};
-	floatv3_t b = {3.1f, 4.3f, 5.8f};
-	/* Golden result g = dot(a, b) */
-	float g = 38.592f;
-	fpv3_t fpa, fpb;
-	volatile fp_t result;
-
-	for (i = 0; i < N; ++i) {
-		fpa[i] = FLOAT_TO_FP(a[i]);
-		fpb[i] = FLOAT_TO_FP(b[i]);
-	}
-
-	result = fpv3_dot(fpa, fpb);
-	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g),
-				DOT_TOLERANCE));
-
-	return EC_SUCCESS;
-}
-
-static int test_fpv3_norm_squared(void)
-{
-	const int N = 3;
-	int i;
-	floatv3_t a = {3.0f, 4.0f, 5.0f};
-	/* Golden result g = norm_squared(a) */
-	float g = 50.0f;
-	fpv3_t fpa;
-
-	for (i = 0; i < N; ++i)
-		fpa[i] = FLOAT_TO_FP(a[i]);
-
-	TEST_ASSERT(IS_FP_EQUAL(fpv3_norm_squared(fpa), FLOAT_TO_FP(g),
-				NORM_SQUARED_TOLERANCE));
-
-	return EC_SUCCESS;
-}
-
-static int test_fpv3_norm(void)
-{
-	const int N = 3;
-	floatv3_t a = {3.1f, 4.2f, 5.3f};
-	/* Golden result g = norm(a) */
-	float g = 7.439086f;
-	int i;
-	fpv3_t fpa;
-	volatile fp_t result;
-
-	for (i = 0; i < N; ++i)
-		fpa[i] = FLOAT_TO_FP(a[i]);
-
-	result = fpv3_norm(fpa);
-	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), NORM_TOLERANCE));
-	return EC_SUCCESS;
-}
-
-static int test_int_sqrtf(void)
-{
-#ifndef CONFIG_FPU
-	TEST_ASSERT(int_sqrtf(0) == 0);
-	TEST_ASSERT(int_sqrtf(15) == 3);
-	TEST_ASSERT(int_sqrtf(25) == 5);
-	TEST_ASSERT(int_sqrtf(1111088889) == 33333);
-	TEST_ASSERT(int_sqrtf(123456789) == 11111);
-	TEST_ASSERT(int_sqrtf(1000000000000000005) == 1000000000);
-	/* Return zero for imaginary numbers */
-	TEST_ASSERT(int_sqrtf(-100) == 0);
-	/* Return INT32_MAX for input greater than INT32_MAX ^ 2 */
-	TEST_ASSERT(int_sqrtf(INT64_MAX) == INT32_MAX);
-#endif
-
-	return EC_SUCCESS;
-}
-
-static int test_mat33_fp_init_zero(void)
-{
-	const int N = 3;
-	int i, j;
-	mat33_fp_t a;
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j)
-			a[i][j] = FLOAT_TO_FP(55.66f);
-
-	mat33_fp_init_zero(a);
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j)
-			TEST_ASSERT(a[i][j] == FLOAT_TO_FP(0.0f));
-
-	return EC_SUCCESS;
-}
-
-static int test_mat33_fp_init_diagonal(void)
-{
-	const int N = 3;
-	int i, j;
-	mat33_fp_t a;
-	fp_t v = FLOAT_TO_FP(-3.45f);
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j)
-			a[i][j] = FLOAT_TO_FP(55.66f);
-
-	mat33_fp_init_diagonal(a, v);
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j) {
-			if (i == j)
-				TEST_ASSERT(a[i][j] == v);
-			else
-				TEST_ASSERT(a[i][j] == FLOAT_TO_FP(0.0f));
-		}
-
-	return EC_SUCCESS;
-}
-
-static int test_mat33_fp_scalar_mul(void)
-{
-	const int N = 3;
-	float scale = 3.11f;
-	mat33_float_t a = {
-		{1.0f, 2.0f, 3.0f},
-		{1.1f, 2.2f, 3.3f},
-		{0.38f, 13.2f, 88.3f}
-	};
-	/* Golden result g = scalar_mul(a, scale) */
-	mat33_float_t g = {{3.11f, 6.22f, 9.33f},
-			   {3.421f, 6.842f, 10.263f},
-			   {1.18179988861083984375f, 41.051998138427734375f,
-			    274.613006591796875f}
-	};
-	int i, j;
-	mat33_fp_t fpa;
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j)
-			fpa[i][j] = FLOAT_TO_FP(a[i][j]);
-
-	mat33_fp_scalar_mul(fpa, FLOAT_TO_FP(scale));
-
-	for (i = 0; i < N; ++i)
-		for (j = 0; j < N; ++j)
-			TEST_ASSERT(IS_FP_EQUAL(fpa[i][j], FLOAT_TO_FP(g[i][j]),
-						SCALAR_MUL_TOLERANCE));
-
-	return EC_SUCCESS;
-}
-
-static int test_mat33_fp_get_eigenbasis(void)
-{
-	mat33_fp_t s = {
-		{FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f)}
-	};
-	fpv3_t e_vals;
-	mat33_fp_t e_vecs;
-	int i, j;
-
-	/* Golden result from float version. */
-	mat33_fp_t gold_vecs = {
-		{FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f),
-		 FLOAT_TO_FP(0.55735206f)},
-		{FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f),
-		 FLOAT_TO_FP(0.0f)},
-		{FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f),
-		 FLOAT_TO_FP(0.81649655f)}
-	};
-	fpv3_t gold_vals = {FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f),
-			    FLOAT_TO_FP(2.0f)};
-
-	mat33_fp_get_eigenbasis(s, e_vals, e_vecs);
-
-	for (i = 0; i < 3; ++i) {
-		TEST_ASSERT(IS_FP_EQUAL(gold_vals[i], e_vals[i],
-					EIGENBASIS_TOLERANCE));
-		for (j = 0; j < 3; ++j) {
-			TEST_ASSERT(IS_FP_EQUAL(gold_vecs[i][j], e_vecs[i][j],
-						EIGENBASIS_TOLERANCE));
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_mat44_fp_decompose_lup(void)
-{
-	int i, j;
-	sizev4_t pivot;
-	mat44_fp_t fpa = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f),
-		 FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f),
-		 FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f)}
-	};
-	/* Golden result from float version. */
-	mat44_fp_t gold_lu = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f),
-		 FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f)}
-	};
-	sizev4_t gold_pivot = {0, 2, 2, 3};
-
-	mat44_fp_decompose_lup(fpa, pivot);
-
-	for (i = 0; i < 4; ++i) {
-		TEST_ASSERT(gold_pivot[i] == pivot[i]);
-		for (j = 0; j < 4; ++j)
-			TEST_ASSERT(IS_FP_EQUAL(gold_lu[i][j], fpa[i][j],
-						LUP_TOLERANCE));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_mat44_fp_solve(void)
-{
-	int i;
-	fpv4_t x;
-	mat44_fp_t A = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
-		 FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500286f), FLOAT_TO_FP(0.5107909f)}
-	};
-	sizev4_t pivot = {0, 2, 2, 3};
-	fpv4_t b = {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f),
-		    FLOAT_TO_FP(8.9f)};
-	/* Golden result from float version. */
-	fpv4_t gold_x = {FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f),
-			 FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f)};
-
-	mat44_fp_solve(A, x, b, pivot);
-
-	for (i = 0; i < 4; ++i)
-		TEST_ASSERT(IS_FP_EQUAL(gold_x[i], x[i], SOLVE_TOLERANCE));
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_fpv3_scalar_mul);
-	RUN_TEST(test_fpv3_dot);
-	RUN_TEST(test_fpv3_norm_squared);
-	RUN_TEST(test_fpv3_norm);
-	RUN_TEST(test_int_sqrtf);
-	RUN_TEST(test_mat33_fp_init_zero);
-	RUN_TEST(test_mat33_fp_init_diagonal);
-	RUN_TEST(test_mat33_fp_scalar_mul);
-	RUN_TEST(test_mat33_fp_get_eigenbasis);
-	RUN_TEST(test_mat44_fp_decompose_lup);
-	RUN_TEST(test_mat44_fp_solve);
-
-	test_print_result();
-}
diff --git a/test/fp.tasklist b/test/fp.tasklist
deleted file mode 100644
index 9ad0114d8a..0000000000
--- a/test/fp.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/fpsensor.c b/test/fpsensor.c
deleted file mode 100644
index 1e7015882d..0000000000
--- a/test/fpsensor.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include <stdbool.h>
-
-#include "ec_commands.h"
-#include "mock/fpsensor_detect_mock.h"
-#include "string.h"
-#include "test_util.h"
-#include "common/fpsensor/fpsensor_private.h"
-
-static const struct ec_response_get_protocol_info expected_info[] = {
-	[FP_TRANSPORT_TYPE_SPI] = {
-		.flags = 1,
-		.max_response_packet_size = 544,
-		.max_request_packet_size = 544,
-		.protocol_versions = 8,
-	},
-	[FP_TRANSPORT_TYPE_UART] = {
-		.flags = 1,
-		.max_response_packet_size = 256,
-		.max_request_packet_size = 544,
-		.protocol_versions = 8,
-	}
-};
-
-test_static int test_validate_fp_buffer_offset_success(void)
-{
-	TEST_EQ(validate_fp_buffer_offset(1, 0, 1), EC_SUCCESS, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_validate_fp_buffer_offset_failure_no_overflow(void)
-{
-	TEST_EQ(validate_fp_buffer_offset(1, 1, 1), EC_ERROR_INVAL, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_validate_fp_buffer_offset_failure_overflow(void)
-{
-	TEST_EQ(validate_fp_buffer_offset(1, UINT32_MAX, 1), EC_ERROR_OVERFLOW,
-		"%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_host_command_protocol_info(
-	enum fp_transport_type transport_type,
-	const struct ec_response_get_protocol_info *expected)
-{
-	struct ec_response_get_protocol_info info;
-	int rv;
-
-	mock_ctrl_fpsensor_detect.get_fp_sensor_type_return =
-		FP_SENSOR_TYPE_FPC;
-	mock_ctrl_fpsensor_detect.get_fp_transport_type_return = transport_type;
-
-	rv = test_send_host_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
-				    sizeof(info));
-
-	TEST_EQ(rv, EC_RES_SUCCESS, "%d");
-
-	TEST_EQ(info.flags, expected->flags, "%d");
-	TEST_EQ(info.max_request_packet_size, expected->max_request_packet_size,
-		"%d");
-	TEST_EQ(info.max_response_packet_size,
-		expected->max_response_packet_size, "%d");
-	TEST_EQ(info.protocol_versions, expected->protocol_versions, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_host_command_protocol_info_uart(void)
-{
-	return test_host_command_protocol_info(
-		FP_TRANSPORT_TYPE_UART, &expected_info[FP_TRANSPORT_TYPE_UART]);
-}
-
-test_static int test_host_command_protocol_info_spi(void)
-{
-	return test_host_command_protocol_info(
-		FP_TRANSPORT_TYPE_SPI, &expected_info[FP_TRANSPORT_TYPE_SPI]);
-}
-
-void run_test(int argc, char **argv)
-{
-	if (IS_ENABLED(HAS_TASK_FPSENSOR)) {
-		/* TODO(b/171924356): The "emulator" build only builds RO and
-		 *  the functions used in the tests are only in RW, so these
-		 *  tests are not run on the emulator.
-		 */
-		RUN_TEST(test_validate_fp_buffer_offset_success);
-		RUN_TEST(test_validate_fp_buffer_offset_failure_no_overflow);
-		RUN_TEST(test_validate_fp_buffer_offset_failure_overflow);
-	}
-
-	/* The tests after this only work on device right now. */
-	if (IS_ENABLED(EMU_BUILD)) {
-		test_print_result();
-		return;
-	}
-
-	if (argc < 2) {
-		ccprintf("usage: runtest [uart|spi]\n");
-		test_fail();
-		return;
-	}
-
-	/* The transport type is cached in a static variable, so the tests
-	 * cannot be run back to back (without reboot).
-	 */
-	if (strncmp(argv[1], "uart", 4) == 0 && IS_ENABLED(BOARD_BLOONCHIPPER))
-		RUN_TEST(test_host_command_protocol_info_uart);
-	else if (strncmp(argv[1], "spi", 3) == 0)
-		RUN_TEST(test_host_command_protocol_info_spi);
-
-	test_print_result();
-}
diff --git a/test/fpsensor.mocklist b/test/fpsensor.mocklist
deleted file mode 100644
index 7e8240bb8d..0000000000
--- a/test/fpsensor.mocklist
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef BOARD_HOST
-#define CONFIG_TEST_MOCK_LIST \
-	MOCK(FP_SENSOR)       \
-	MOCK(FPSENSOR_DETECT) \
-	MOCK(FPSENSOR_STATE)  \
-	MOCK(MKBP_EVENTS)     \
-	MOCK(ROLLBACK)        \
-	MOCK(TIMER)
-#elif defined(TEST_BUILD)
-/* Mock the sensor detection on dragonclaw v0.2 dev boards since we can't
- * otherwise change the detected version in hardware without a rework. See
- * https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/docs/schematics/dragonclaw
- */
-#define CONFIG_TEST_MOCK_LIST MOCK(FPSENSOR_DETECT)
-#endif /* BOARD_HOST */
diff --git a/test/fpsensor.tasklist b/test/fpsensor.tasklist
deleted file mode 100644
index ba137b7613..0000000000
--- a/test/fpsensor.tasklist
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
-
-#ifdef BOARD_HOST
-#undef CONFIG_TEST_TASK_LIST
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(FPSENSOR, fp_task_simulate, NULL, TASK_STACK_SIZE)
-#endif
diff --git a/test/fpsensor_crypto.c b/test/fpsensor_crypto.c
deleted file mode 100644
index d0fd92cf7c..0000000000
--- a/test/fpsensor_crypto.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fpsensor_crypto.h"
-#include "fpsensor_state.h"
-#include "mock/fpsensor_state_mock.h"
-#include "mock/rollback_mock.h"
-#include "mock/timer_mock.h"
-#include "test_util.h"
-#include "util.h"
-
-static const uint8_t fake_positive_match_salt[] = {
-	0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf,
-	0x04, 0x1d, 0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb,
-};
-
-static const uint8_t fake_user_id[] = {
-	0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88,
-	0xce, 0xc5, 0xd1, 0xfe, 0x1d, 0x58, 0x5b, 0x94,
-	0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea, 0xb1, 0xea,
-	0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64,
-};
-
-/*
- * |expected_positive_match_secret_for_empty_user_id| is obtained by running
- * BoringSSL locally.
- * From https://boringssl.googlesource.com/boringssl
- * commit 365b7a0fcbf273b1fa704d151059e419abd6cfb8
- *
- * Steps to reproduce:
- *
- * Open boringssl/crypto/hkdf/hkdf_test.cc
- * Add the following case to static const HKDFTestVector kTests[]
- *
- * // test positive match secret
- * {
- *   EVP_sha256,
- *   {
- *     // IKM:
- *     // fake_rollback_secret
- *     [ ***Copy 32 octets of fake_rollback_secret here*** ]
- *     // fake_tpm_seed
- *     [ ***Copy 32 octets of fake_tpm_seed here*** ]
- *   }, 64,
- *   {
- *     // fake_positive_match_salt
- *     [ ***Copy 16 octets of fake_positive_match_salt here*** ]
- *   }, 16,
- *   {
- *     // Info:
- *     // "positive_match_secret for user "
- *     0x70, 0x6f, 0x73, 0x69, 0x74, 0x69, 0x76, 0x65,
- *     0x5f, 0x6d, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x73,
- *     0x65, 0x63, 0x72, 0x65, 0x74, 0x20, 0x66, 0x6f,
- *     0x72, 0x20, 0x75, 0x73, 0x65, 0x72, 0x20,
- *     // user_id
- *     [ ***Type 32 octets of 0x00 here*** ]
- *   }, 63,
- *   {  // Expected PRK:
- *     0xc2, 0xff, 0x50, 0x2d, 0xb1, 0x7e, 0x87, 0xb1,
- *     0x25, 0x36, 0x3a, 0x88, 0xe1, 0xdb, 0x4f, 0x98,
- *     0x22, 0xb5, 0x66, 0x8c, 0xab, 0xb7, 0xc7, 0x5e,
- *     0xd7, 0x56, 0xbe, 0xde, 0x82, 0x3f, 0xd0, 0x62,
- *   }, 32,
- *   32, { // 32 = L = FP_POSITIVE_MATCH_SECRET_BYTES
- *     // Expected positive match secret:
- *     [ ***Copy 32 octets of expected positive_match_secret here*** ]
- *   }
- * },
- *
- * Then from boringssl/ execute:
- * mkdir build
- * cd build
- * cmake ..
- * make
- * cd ..
- * go run util/all_tests.go
- */
-static const uint8_t expected_positive_match_secret_for_empty_user_id[] = {
-	0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72,
-	0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b,
-	0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51,
-	0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
-};
-
-/*
- * Same as |expected_positive_match_secret_for_empty_user_id| but use
- * |fake_user_id| instead of all-zero user_id.
- */
-static const uint8_t expected_positive_match_secret_for_fake_user_id[] = {
-	0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66,
-	0x2f, 0x71, 0xf6, 0xc6, 0xca, 0x8a, 0x41, 0x69,
-	0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a, 0x5f, 0x4d,
-	0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30,
-};
-
-static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size,
-				const uint8_t *info, size_t info_size,
-				const uint8_t *expected_okm, size_t okm_size)
-{
-	uint8_t actual_okm[okm_size];
-
-	TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size,
-				info, info_size) == EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(expected_okm, actual_okm, okm_size);
-	return EC_SUCCESS;
-}
-
-test_static int test_hkdf_expand(void)
-{
-	/* Test vectors in https://tools.ietf.org/html/rfc5869#appendix-A */
-	static const uint8_t prk1[] = {
-		0x07, 0x77, 0x09, 0x36, 0x2c, 0x2e, 0x32, 0xdf,
-		0x0d, 0xdc, 0x3f, 0x0d, 0xc4, 0x7b, 0xba, 0x63,
-		0x90, 0xb6, 0xc7, 0x3b, 0xb5, 0x0f, 0x9c, 0x31,
-		0x22, 0xec, 0x84, 0x4a, 0xd7, 0xc2, 0xb3, 0xe5,
-	};
-	static const uint8_t info1[] = {
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9,
-	};
-	static const uint8_t expected_okm1[] = {
-		0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a,
-		0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a,
-		0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c,
-		0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf,
-		0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18,
-		0x58, 0x65,
-	};
-	static const uint8_t prk2[] = {
-		0x06, 0xa6, 0xb8, 0x8c, 0x58, 0x53, 0x36, 0x1a,
-		0x06, 0x10, 0x4c, 0x9c, 0xeb, 0x35, 0xb4, 0x5c,
-		0xef, 0x76, 0x00, 0x14, 0x90, 0x46, 0x71, 0x01,
-		0x4a, 0x19, 0x3f, 0x40, 0xc1, 0x5f, 0xc2, 0x44,
-	};
-	static const uint8_t info2[] = {
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
-		0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
-		0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
-		0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
-		0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
-		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
-		0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
-		0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
-	};
-	static const uint8_t expected_okm2[] = {
-		0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1,
-		0xc8, 0xe7, 0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34,
-		0x4f, 0x01, 0x2e, 0xda, 0x2d, 0x4e, 0xfa, 0xd8,
-		0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf, 0xa9, 0x7c,
-		0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72,
-		0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09,
-		0xda, 0x32, 0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8,
-		0x36, 0x77, 0x93, 0xa9, 0xac, 0xa3, 0xdb, 0x71,
-		0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec, 0x3e, 0x87,
-		0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f,
-		0x1d, 0x87,
-	};
-	static const uint8_t prk3[] = {
-		0x19, 0xef, 0x24, 0xa3, 0x2c, 0x71, 0x7b, 0x16,
-		0x7f, 0x33, 0xa9, 0x1d, 0x6f, 0x64, 0x8b, 0xdf,
-		0x96, 0x59, 0x67, 0x76, 0xaf, 0xdb, 0x63, 0x77,
-		0xac, 0x43, 0x4c, 0x1c, 0x29, 0x3c, 0xcb, 0x04,
-	};
-	static const uint8_t expected_okm3[] = {
-		0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f,
-		0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31,
-		0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e,
-		0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d,
-		0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a,
-		0x96, 0xc8,
-	};
-	static uint8_t unused_output[SHA256_DIGEST_SIZE] = { 0 };
-
-	TEST_ASSERT(test_hkdf_expand_raw(prk1, sizeof(prk1), info1,
-					 sizeof(info1), expected_okm1,
-					 sizeof(expected_okm1))
-			    == EC_SUCCESS);
-	TEST_ASSERT(test_hkdf_expand_raw(prk2, sizeof(prk2), info2,
-					 sizeof(info2), expected_okm2,
-					 sizeof(expected_okm2))
-			    == EC_SUCCESS);
-	TEST_ASSERT(test_hkdf_expand_raw(prk3, sizeof(prk3), NULL, 0,
-					 expected_okm3, sizeof(expected_okm3))
-			    == EC_SUCCESS);
-
-	TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1,
-				sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				NULL, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), NULL, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	/* Info size too long. */
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), info1, 1024)
-			    == EC_ERROR_INVAL);
-	/* OKM size too big. */
-	TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE,
-				prk1, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key_failure_seed_not_set(void)
-{
-	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
-
-	/* GIVEN that the TPM seed is not set. */
-	if (fp_tpm_seed_is_set()) {
-		ccprintf("%s:%s(): this test should be executed before setting"
-			 " TPM seed.\n",
-			 __FILE__, __func__);
-		return -1;
-	}
-
-	/* THEN derivation will fail. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_ERROR_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-}
-
-static int test_derive_encryption_key_raw(const uint32_t *user_id_,
-					  const uint8_t *salt,
-					  const uint8_t *expected_key)
-{
-	uint8_t key[SBP_ENC_KEY_LEN];
-	int rv;
-
-	/*
-	 * |user_id| is a global variable used as "info" in HKDF expand
-	 * in derive_encryption_key().
-	 */
-	memcpy(user_id, user_id_, sizeof(user_id));
-	rv = derive_encryption_key(key, salt);
-
-	TEST_ASSERT(rv == EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(key, expected_key, sizeof(key));
-
-	memset(user_id, 0, sizeof(user_id));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key(void)
-{
-	/*
-	 * These vectors are obtained by choosing the salt and the user_id
-	 * (used as "info" in HKDF), and running boringSSL's HKDF
-	 * (https://boringssl.googlesource.com/boringssl/+/c0b4c72b6d4c6f4828a373ec454bd646390017d4/crypto/hkdf/)
-	 * locally to get the output key. The IKM used in the run is the
-	 * concatenation of |fake_rollback_secret| and |fake_tpm_seed|.
-	 */
-	static const uint32_t user_id1[] = {
-		0x608b1b0b, 0xe10d3d24, 0x0bbbe4e6, 0x807b36d9,
-		0x2a1f8abc, 0xea38104a, 0x562d9431, 0x64d721c5,
-	};
-
-	static const uint8_t salt1[] = {
-		0xd0, 0x88, 0x34, 0x15, 0xc0, 0xfa, 0x8e, 0x22,
-		0x9f, 0xb4, 0xd5, 0xa9, 0xee, 0xd3, 0x15, 0x19,
-	};
-
-	static const uint8_t key1[] = {
-		0xdb, 0x49, 0x6e, 0x1b, 0x67, 0x8a, 0x35, 0xc6,
-		0xa0, 0x9d, 0xb6, 0xa0, 0x13, 0xf4, 0x21, 0xb3,
-	};
-
-	static const uint32_t user_id2[] = {
-		0x2546a2ca, 0xf1891f7a, 0x44aad8b8, 0x0d6aac74,
-		0x6a4ab846, 0x9c279796, 0x5a72eae1, 0x8276d2a3,
-	};
-
-	static const uint8_t salt2[] = {
-		0x72, 0x6b, 0xc1, 0xe4, 0x64, 0xd4, 0xff, 0xa2,
-		0x5a, 0xac, 0x5b, 0x0b, 0x06, 0x67, 0xe1, 0x53,
-	};
-
-	static const uint8_t key2[] = {
-		0x8d, 0x53, 0xaf, 0x4c, 0x96, 0xa2, 0xee, 0x46,
-		0x9c, 0xe2, 0xe2, 0x6f, 0xe6, 0x66, 0x3d, 0x3a,
-	};
-
-	/*
-	 * GIVEN that the TPM seed is set, and reading the rollback secret will
-	 * succeed.
-	 */
-	TEST_ASSERT(fp_tpm_seed_is_set() &&
-		    !mock_ctrl_rollback.get_secret_fail);
-
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(test_derive_encryption_key_raw(user_id1, salt1, key1) ==
-		    EC_SUCCESS);
-
-	TEST_ASSERT(test_derive_encryption_key_raw(user_id2, salt2, key2) ==
-		    EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_encryption_key_failure_rollback_fail(void)
-{
-	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
-
-	/* GIVEN that reading the rollback secret will fail. */
-	mock_ctrl_rollback.get_secret_fail = true;
-	/* THEN the derivation will fail. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_ERROR_HW_INTERNAL);
-
-	/* GIVEN that reading the rollback secret will succeed. */
-	mock_ctrl_rollback.get_secret_fail = false;
-	/* GIVEN that the TPM seed has been set. */
-	TEST_ASSERT(fp_tpm_seed_is_set());
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(derive_encryption_key(unused_key, unused_salt) ==
-		    EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_seed_not_set(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that seed is not set. */
-	TEST_ASSERT(!fp_tpm_seed_is_set());
-	/* THEN EVEN IF the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* Deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-
-}
-
-test_static int test_derive_new_pos_match_secret(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* First, for empty user_id. */
-	memset(user_id, 0, sizeof(user_id));
-
-	/* GIVEN that the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-	/*
-	 * GIVEN that the TPM seed is set, and reading the rollback secret will
-	 * succeed.
-	 */
-	TEST_ASSERT(
-		fp_tpm_seed_is_set() && !mock_ctrl_rollback.get_secret_fail);
-
-	/* GIVEN that the salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* THEN the derivation will succeed. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_empty_user_id,
-		sizeof(expected_positive_match_secret_for_empty_user_id));
-
-	/* Now change the user_id to be non-trivial. */
-	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_fake_user_id,
-		sizeof(expected_positive_match_secret_for_fake_user_id));
-	memset(user_id, 0, sizeof(user_id));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_rollback_fail(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that reading secret from anti-rollback block will fail. */
-	mock_ctrl_rollback.get_secret_fail = true;
-	/* THEN EVEN IF the encryption salt is not trivial. */
-	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
-				       sizeof(fake_positive_match_salt)));
-
-	/* Deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_HW_INTERNAL);
-	mock_ctrl_rollback.get_secret_fail = false;
-
-	return EC_SUCCESS;
-}
-
-test_static int test_derive_positive_match_secret_fail_salt_trivial(void)
-{
-	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
-
-	/* GIVEN that the salt is trivial. */
-	static const uint8_t salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { 0 };
-
-	/* THEN deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output, salt)
-		== EC_ERROR_INVAL);
-	return EC_SUCCESS;
-}
-
-static int test_enable_positive_match_secret_once(
-	struct positive_match_secret_state *dumb_state)
-{
-	const int8_t kIndexToEnable = 0;
-	timestamp_t now = get_time();
-
-	TEST_ASSERT(fp_enable_positive_match_secret(
-		kIndexToEnable, dumb_state) == EC_SUCCESS);
-	TEST_ASSERT(dumb_state->template_matched == kIndexToEnable);
-	TEST_ASSERT(dumb_state->readable);
-	TEST_ASSERT(dumb_state->deadline.val == now.val + (5 * SECOND));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_enable_positive_match_secret(void)
-{
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
-
-	/* Trying to enable again before reading secret should fail. */
-	TEST_ASSERT(fp_enable_positive_match_secret(0, &dumb_state) ==
-		EC_ERROR_UNKNOWN);
-	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
-	TEST_ASSERT(!dumb_state.readable);
-	TEST_ASSERT(dumb_state.deadline.val == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_disable_positive_match_secret(void)
-{
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
-
-	fp_disable_positive_match_secret(&dumb_state);
-	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
-	TEST_ASSERT(!dumb_state.readable);
-	TEST_ASSERT(dumb_state.deadline.val == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-	struct ec_response_fp_read_match_secret resp;
-	timestamp_t now = get_time();
-
-	/* For empty user_id. */
-	memset(user_id, 0, sizeof(user_id));
-
-	/* Invalid finger index should be rejected. */
-	params.fgr = FP_NO_SUCH_TEMPLATE;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-	params.fgr = FP_MAX_FINGER_COUNT;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	memset(&resp, 0, sizeof(resp));
-	/* GIVEN that finger index is valid. */
-	params.fgr = 0;
-
-	/* GIVEN that positive match secret is enabled. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-
-	/* GIVEN that salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* THEN reading positive match secret should succeed. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), &resp, sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
-		return -1;
-	}
-	/* AND the readable bit should be cleared after the read. */
-	TEST_ASSERT(positive_match_secret_state.readable == false);
-
-	TEST_ASSERT_ARRAY_EQ(
-		resp.positive_match_secret,
-		expected_positive_match_secret_for_empty_user_id,
-		sizeof(expected_positive_match_secret_for_empty_user_id));
-
-	/*
-	 * Now try reading secret again.
-	 * EVEN IF the deadline has not passed.
-	 */
-	positive_match_secret_state.deadline.val = now.val + 1 * SECOND;
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	/*
-	 * This time the command should fail because the
-	 * fp_pos_match_secret_readable bit is cleared when the secret was read
-	 * the first time.
-	 */
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_wrong_finger(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	/* GIVEN that the finger is not the matched or enrolled finger. */
-	params.fgr = 0;
-	/*
-	 * GIVEN that positive match secret is enabled for a different
-	 * finger.
-	 */
-	fp_enable_positive_match_secret(params.fgr + 1,
-					&positive_match_secret_state);
-
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_timeout(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	params.fgr = 0;
-	/* GIVEN that the read is too late. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-	set_time(positive_match_secret_state.deadline);
-
-	/* EVEN IF encryption salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_TIMEOUT);
-	return EC_SUCCESS;
-}
-
-test_static int test_command_read_match_secret_unreadable(void)
-{
-	int rv;
-	struct ec_params_fp_read_match_secret params;
-
-	params.fgr = 0;
-	/* GIVEN that the readable bit is not set. */
-	fp_enable_positive_match_secret(params.fgr,
-					&positive_match_secret_state);
-	positive_match_secret_state.readable = false;
-
-	/* EVEN IF the finger is just matched. */
-	TEST_ASSERT(positive_match_secret_state.template_matched
-		== params.fgr);
-
-	/* EVEN IF encryption salt is non-trivial. */
-	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
-	       sizeof(fp_positive_match_salt[0]));
-	/* Reading secret will fail. */
-	rv = test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0, &params,
-				    sizeof(params), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_hkdf_expand);
-	RUN_TEST(test_derive_encryption_key_failure_seed_not_set);
-	RUN_TEST(test_derive_positive_match_secret_fail_seed_not_set);
-
-	/*
-	 * Set the TPM seed here because it can only be set once and cannot be
-	 * cleared.
-	 */
-	ASSERT(fpsensor_state_mock_set_tpm_seed(default_fake_tpm_seed) ==
-		    EC_SUCCESS);
-
-	/* The following test requires TPM seed to be already set. */
-	RUN_TEST(test_derive_encryption_key);
-	RUN_TEST(test_derive_encryption_key_failure_rollback_fail);
-	RUN_TEST(test_derive_new_pos_match_secret);
-	RUN_TEST(test_derive_positive_match_secret_fail_rollback_fail);
-	RUN_TEST(test_derive_positive_match_secret_fail_salt_trivial);
-	RUN_TEST(test_enable_positive_match_secret);
-	RUN_TEST(test_disable_positive_match_secret);
-	RUN_TEST(test_command_read_match_secret);
-	RUN_TEST(test_command_read_match_secret_wrong_finger);
-	RUN_TEST(test_command_read_match_secret_timeout);
-	RUN_TEST(test_command_read_match_secret_unreadable);
-	test_print_result();
-}
diff --git a/test/fpsensor_crypto.mocklist b/test/fpsensor_crypto.mocklist
deleted file mode 120000
index 3ab27169be..0000000000
--- a/test/fpsensor_crypto.mocklist
+++ /dev/null
@@ -1 +0,0 @@
-fpsensor.mocklist
\ No newline at end of file
diff --git a/test/fpsensor_crypto.tasklist b/test/fpsensor_crypto.tasklist
deleted file mode 120000
index 7886010ad6..0000000000
--- a/test/fpsensor_crypto.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-fpsensor.tasklist
\ No newline at end of file
diff --git a/test/fpsensor_hw.c b/test/fpsensor_hw.c
deleted file mode 100644
index 1ca4a9f505..0000000000
--- a/test/fpsensor_hw.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "test_util.h"
-#include "fpc_private.h"
-
-/* Hardware-dependent smoke test that makes a SPI transaction with the
- * fingerprint sensor.
- */
-test_static int test_fp_check_hwid(void)
-{
-	/* TODO(b/187134801): modify fpc_check_hwid() to return the hwid. */
-	if (IS_ENABLED(SECTION_IS_RW))
-		TEST_EQ(fpc_check_hwid(), EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_fp_check_hwid);
-	test_print_result();
-}
diff --git a/test/fpsensor_hw.tasklist b/test/fpsensor_hw.tasklist
deleted file mode 100644
index 299cf25390..0000000000
--- a/test/fpsensor_hw.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/fpsensor_state.c b/test/fpsensor_state.c
deleted file mode 100644
index 3822fe49ab..0000000000
--- a/test/fpsensor_state.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "fpsensor_state.h"
-#include "mock/fpsensor_state_mock.h"
-#include "test_util.h"
-#include "util.h"
-
-test_static int test_fp_enc_status_valid_flags(void)
-{
-	/* Putting expected value here because test_static should take void */
-	const uint32_t expected = FP_ENC_STATUS_SEED_SET;
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): failed to get encryption status. rv = %d\n",
-			 __FILE__, __func__, rv);
-		return -1;
-	}
-
-	if (resp.valid_flags != expected) {
-		ccprintf("%s:%s(): expected valid flags 0x%08x, got 0x%08x\n",
-			 __FILE__, __func__, expected, resp.valid_flags);
-		return -1;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-static int
-check_seed_set_result(const int rv, const uint32_t expected,
-		      const struct ec_response_fp_encryption_status *resp)
-{
-	const uint32_t actual = resp->status & FP_ENC_STATUS_SEED_SET;
-
-	if (rv != EC_RES_SUCCESS || expected != actual) {
-		ccprintf("%s:%s(): rv = %d, seed is set: %d\n", __FILE__,
-			 __func__, rv, actual);
-		return -1;
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_fp_tpm_seed_not_set(void)
-{
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	/* Initially the seed should not have been set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, 0, &resp);
-}
-
-test_static int test_set_fp_tpm_seed(void)
-{
-	int rv;
-	struct ec_params_fp_seed params;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(params.seed, default_fake_tpm_seed,
-	       sizeof(default_fake_tpm_seed));
-
-	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
-				    NULL, 0);
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d, set seed failed\n", __FILE__,
-			 __func__, rv);
-		return -1;
-	}
-
-	/* Now seed should have been set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
-}
-
-test_static int test_set_fp_tpm_seed_again(void)
-{
-	int rv;
-	struct ec_params_fp_seed params;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	TEST_ASSERT(fp_tpm_seed_is_set());
-
-	params.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(params.seed, default_fake_tpm_seed,
-	       sizeof(default_fake_tpm_seed));
-
-	rv = test_send_host_command(EC_CMD_FP_SEED, 0, &params, sizeof(params),
-				    NULL, 0);
-	if (rv != EC_RES_ACCESS_DENIED) {
-		ccprintf("%s:%s(): rv = %d, setting seed the second time "
-			 "should result in EC_RES_ACCESS_DENIED but did not.\n",
-			 __FILE__, __func__, rv);
-		return -1;
-	}
-
-	/* Now seed should still be set. */
-	rv = test_send_host_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	return check_seed_set_result(rv, FP_ENC_STATUS_SEED_SET, &resp);
-}
-
-test_static int test_fp_set_sensor_mode(void)
-{
-	uint32_t requested_mode = 0;
-	uint32_t output_mode = 0;
-
-	/* Validate initial conditions */
-	TEST_ASSERT(FP_MAX_FINGER_COUNT == 5);
-	TEST_ASSERT(templ_valid == 0);
-	TEST_ASSERT(sensor_mode == 0);
-
-	/* GIVEN missing output parameter, THEN get error */
-	TEST_ASSERT(fp_set_sensor_mode(0, NULL) == EC_RES_INVALID_PARAM);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-
-	/* GIVEN requested mode includes FP_MODE_DONT_CHANGE, THEN succeed */
-	TEST_ASSERT(sensor_mode == 0);
-	TEST_ASSERT(output_mode == 0);
-	requested_mode = FP_MODE_DONT_CHANGE;
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_SUCCESS);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-	/* THEN output_mode matches sensor_mode */
-	TEST_ASSERT(output_mode == sensor_mode);
-
-	/* GIVEN request to change to valid sensor mode */
-	TEST_ASSERT(sensor_mode == 0);
-	requested_mode = FP_MODE_ENROLL_SESSION;
-	/* THEN succeed */
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_SUCCESS);
-	/* THEN requested mode is returned */
-	TEST_ASSERT(requested_mode == output_mode);
-	/* THEN sensor_mode is updated */
-	TEST_ASSERT(sensor_mode == requested_mode);
-
-	/* GIVEN max number of fingers already enrolled */
-	sensor_mode = 0;
-	output_mode = 0xdeadbeef;
-	templ_valid = FP_MAX_FINGER_COUNT;
-	requested_mode = FP_MODE_ENROLL_SESSION;
-	/* THEN additional enroll attempt will fail */
-	TEST_ASSERT(fp_set_sensor_mode(requested_mode, &output_mode) ==
-		    EC_RES_INVALID_PARAM);
-	/* THEN output parameters is unchanged */
-	TEST_ASSERT(output_mode = 0xdeadbeef);
-	/* THEN sensor_mode is unchanged */
-	TEST_ASSERT(sensor_mode == 0);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_fp_set_maintenance_mode(void)
-{
-	uint32_t output_mode = 0;
-
-	/* GIVEN request to change to maintenance sensor mode */
-	TEST_ASSERT(sensor_mode == 0);
-	/* THEN succeed */
-	TEST_ASSERT(fp_set_sensor_mode(FP_MODE_SENSOR_MAINTENANCE,
-				       &output_mode) == EC_RES_SUCCESS);
-	/* THEN requested mode is returned */
-	TEST_ASSERT(output_mode == FP_MODE_SENSOR_MAINTENANCE);
-	/* THEN sensor_mode is updated */
-	TEST_ASSERT(sensor_mode == FP_MODE_SENSOR_MAINTENANCE);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_fp_enc_status_valid_flags);
-	RUN_TEST(test_fp_tpm_seed_not_set);
-	RUN_TEST(test_set_fp_tpm_seed);
-	RUN_TEST(test_set_fp_tpm_seed_again);
-	RUN_TEST(test_fp_set_sensor_mode);
-	RUN_TEST(test_fp_set_maintenance_mode);
-	test_print_result();
-}
diff --git a/test/fpsensor_state.mocklist b/test/fpsensor_state.mocklist
deleted file mode 120000
index 3ab27169be..0000000000
--- a/test/fpsensor_state.mocklist
+++ /dev/null
@@ -1 +0,0 @@
-fpsensor.mocklist
\ No newline at end of file
diff --git a/test/fpsensor_state.tasklist b/test/fpsensor_state.tasklist
deleted file mode 120000
index 69b4562a97..0000000000
--- a/test/fpsensor_state.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-./fpsensor.tasklist
\ No newline at end of file
diff --git a/test/genvif/.gitignore b/test/genvif/.gitignore
deleted file mode 100644
index eabdcbd17f..0000000000
--- a/test/genvif/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-genvif
-vif_output
diff --git a/test/genvif/Makefile b/test/genvif/Makefile
deleted file mode 100644
index 566b6bb042..0000000000
--- a/test/genvif/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-
-CC=gcc
-CFLAGS=-O2 -Isrc -I../../include
-
-genvif: ../../util/genvif.c src/helper.c
-	@$(CC) -o $@ $^ $(CFLAGS)
-
-test: genvif
-	@mkdir vif_output 2>/dev/null
-	@./genvif -b test -o vif_output
-	@./genvif -b exp_test -o vif_output -n -v vif/exp_test_vif.xml
-	@diff vif_output/test_vif.xml vif_output/exp_test_vif.xml
-	@./genvif -b test_over -o vif_output -v vif/over_test_vif.xml
-	@./genvif -b exp_test_over -o vif_output -n -v vif/exp_test_over_vif.xml
-	@diff vif_output/test_over_vif.xml vif_output/exp_test_over_vif.xml
-
-.PHONY: clean
-clean:
-	@rm -f genvif
-	@rm -rf vif_output
diff --git a/test/genvif/genvif.sh b/test/genvif/genvif.sh
deleted file mode 100755
index 4a275ed2c1..0000000000
--- a/test/genvif/genvif.sh
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash -e
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cd test/genvif
-make clean
-make test
diff --git a/test/genvif/src/atomic.h b/test/genvif/src/atomic.h
deleted file mode 100644
index f2fa112e81..0000000000
--- a/test/genvif/src/atomic.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Blank shell to avoid including the real file
- */
diff --git a/test/genvif/src/board.h b/test/genvif/src/board.h
deleted file mode 100644
index 8f175443d0..0000000000
--- a/test/genvif/src/board.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
diff --git a/test/genvif/src/config_chip.h b/test/genvif/src/config_chip.h
deleted file mode 100644
index f2fa112e81..0000000000
--- a/test/genvif/src/config_chip.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Blank shell to avoid including the real file
- */
diff --git a/test/genvif/src/fuzz_config.h b/test/genvif/src/fuzz_config.h
deleted file mode 100644
index f2fa112e81..0000000000
--- a/test/genvif/src/fuzz_config.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Blank shell to avoid including the real file
- */
diff --git a/test/genvif/src/helper.c b/test/genvif/src/helper.c
deleted file mode 100644
index d604e63cfa..0000000000
--- a/test/genvif/src/helper.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "usb_pd.h"
-
-#ifndef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
-
-const uint32_t pd_src_pdo[] = {
-	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
-const uint32_t pd_src_pdo_max[] = {
-	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
-};
-const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
-
-const uint32_t pd_snk_pdo[] = {
-	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-	PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_OPERATING_POWER_MW),
-	PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
-};
-const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-#endif /* CONFIG_USB_PD_CUSTOM_PDO */
-
-uint8_t board_get_usb_pd_port_count(void)
-{
-	return 1;
-}
diff --git a/test/genvif/src/test_config.h b/test/genvif/src/test_config.h
deleted file mode 100644
index f2fa112e81..0000000000
--- a/test/genvif/src/test_config.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Blank shell to avoid including the real file
- */
diff --git a/test/genvif/src/timer.h b/test/genvif/src/timer.h
deleted file mode 100644
index f2fa112e81..0000000000
--- a/test/genvif/src/timer.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Blank shell to avoid including the real file
- */
diff --git a/test/genvif/vif/exp_test_over_vif.xml b/test/genvif/vif/exp_test_over_vif.xml
deleted file mode 100644
index 258430fd96..0000000000
--- a/test/genvif/vif/exp_test_over_vif.xml
+++ /dev/null
@@ -1,86 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>

-<VIF>

-  <VIF_Specification>3.12</VIF_Specification>

-  <Vendor_Name>Google</Vendor_Name>

-  <Model_Part_Number>SuperTestWithOverride</Model_Part_Number>

-  <Product_Revision>Final</Product_Revision>

-  <TID>12345</TID>

-  <VIF_Product_Type value="0">Port Product</VIF_Product_Type>

-  <Certification_Type value="0">End Product</Certification_Type>

-  <Product>

-    <Product_VID value="6353">18D1</Product_VID>

-  </Product>

-  <Component>

-    <Port_Label>0</Port_Label>

-    <Connector_Type value="2">Type-C®</Connector_Type>

-    <USB4_Supported value="false">NO</USB4_Supported>

-    <USB_PD_Support value="true">YES</USB_PD_Support>

-    <PD_Port_Type value="4">DRP</PD_Port_Type>

-    <Type_C_State_Machine value="2">DRP</Type_C_State_Machine>

-    <Captive_Cable value="false">NO</Captive_Cable>

-    <Port_Battery_Powered value="false">NO</Port_Battery_Powered>

-    <BC_1_2_Support value="0">None</BC_1_2_Support>

-    <PD_Spec_Revision_Major value="3" />

-    <PD_Spec_Revision_Minor value="0" />

-    <PD_Spec_Version_Major value="2" />

-    <PD_Spec_Version_Minor value="0" />

-    <PD_Specification_Revision value="2">Revision 3</PD_Specification_Revision>

-    <USB_Comms_Capable value="true">YES</USB_Comms_Capable>

-    <DR_Swap_To_DFP_Supported value="true">YES</DR_Swap_To_DFP_Supported>

-    <DR_Swap_To_UFP_Supported value="false">NO</DR_Swap_To_UFP_Supported>

-    <Unconstrained_Power value="false">NO</Unconstrained_Power>

-    <VCONN_Swap_To_On_Supported value="false">NO</VCONN_Swap_To_On_Supported>

-    <VCONN_Swap_To_Off_Supported value="false">NO</VCONN_Swap_To_Off_Supported>

-    <Responds_To_Discov_SOP_UFP value="false">NO</Responds_To_Discov_SOP_UFP>

-    <Responds_To_Discov_SOP_DFP value="false">NO</Responds_To_Discov_SOP_DFP>

-    <Attempts_Discov_SOP value="true">YES</Attempts_Discov_SOP>

-    <Chunking_Implemented_SOP value="false">NO</Chunking_Implemented_SOP>

-    <Unchunked_Extended_Messages_Supported value="false">NO</Unchunked_Extended_Messages_Supported>

-    <Manufacturer_Info_Supported_Port value="false">NO</Manufacturer_Info_Supported_Port>

-    <Security_Msgs_Supported_SOP value="false">NO</Security_Msgs_Supported_SOP>

-    <Num_Fixed_Batteries value="1" />

-    <Num_Swappable_Battery_Slots value="0" />

-    <ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</ID_Header_Connector_Type_SOP>

-    <SOP_Capable value="true">YES</SOP_Capable>

-    <SOP_P_Capable value="false">NO</SOP_P_Capable>

-    <SOP_PP_Capable value="false">NO</SOP_PP_Capable>

-    <SOP_P_Debug_Capable value="false">NO</SOP_P_Debug_Capable>

-    <SOP_PP_Debug_Capable value="false">NO</SOP_PP_Debug_Capable>

-    <Type_C_Implements_Try_SRC value="false">NO</Type_C_Implements_Try_SRC>

-    <Type_C_Implements_Try_SNK value="false">NO</Type_C_Implements_Try_SNK>

-    <RP_Value value="1">1.5A</RP_Value>

-    <Type_C_Is_VCONN_Powered_Accessory value="false">NO</Type_C_Is_VCONN_Powered_Accessory>

-    <Type_C_Is_Debug_Target_SRC value="true">YES</Type_C_Is_Debug_Target_SRC>

-    <Type_C_Is_Debug_Target_SNK value="true">YES</Type_C_Is_Debug_Target_SNK>

-    <Type_C_Can_Act_As_Host value="true">YES</Type_C_Can_Act_As_Host>

-    <Type_C_Is_Alt_Mode_Controller value="false">NO</Type_C_Is_Alt_Mode_Controller>

-    <Type_C_Can_Act_As_Device value="false">NO</Type_C_Can_Act_As_Device>

-    <Type_C_Power_Source value="1">UFP-powered</Type_C_Power_Source>

-    <Type_C_Port_On_Hub value="false">NO</Type_C_Port_On_Hub>

-    <Type_C_Supports_Audio_Accessory value="false">NO</Type_C_Supports_Audio_Accessory>

-    <Type_C_Sources_VCONN value="false">NO</Type_C_Sources_VCONN>

-    <PD_Power_As_Source value="15000">15000 mW</PD_Power_As_Source>

-    <USB_Suspend_May_Be_Cleared value="false">NO</USB_Suspend_May_Be_Cleared>

-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

-    <Master_Port value="false">NO</Master_Port>

-    <Num_Src_PDOs value="1" />

-    <Host_Supports_USB_Data value="true">YES</Host_Supports_USB_Data>

-    <Host_Speed value="1">USB 3.2 GEN 1x1</Host_Speed>

-    <Is_DFP_On_Hub value="false">NO</Is_DFP_On_Hub>

-    <Host_Contains_Captive_Retimer value="false">NO</Host_Contains_Captive_Retimer>

-    <Host_Is_Embedded value="false">NO</Host_Is_Embedded>

-    <PD_OC_Protection value="false">NO</PD_OC_Protection>

-    <Product_Total_Source_Power_mW value="15000">15000 mW</Product_Total_Source_Power_mW>

-    <Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>

-    <SrcPdoList>

-      <SrcPDO>

-        <Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>

-        <Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>

-        <Src_PDO_Voltage value="100">5000 mV</Src_PDO_Voltage>

-        <Src_PDO_Max_Current value="300">3000 mA</Src_PDO_Max_Current>

-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>

-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>

-      </SrcPDO>

-    </SrcPdoList>

-  </Component>

-</VIF>

diff --git a/test/genvif/vif/exp_test_vif.xml b/test/genvif/vif/exp_test_vif.xml
deleted file mode 100644
index b04bfbe9e1..0000000000
--- a/test/genvif/vif/exp_test_vif.xml
+++ /dev/null
@@ -1,84 +0,0 @@
-<VIF>

-  <VIF_Specification>3.12</VIF_Specification>

-  <Vendor_Name>Google</Vendor_Name>

-  <Model_Part_Number>test</Model_Part_Number>

-  <Product_Revision>FIX-ME</Product_Revision>

-  <TID>65535</TID>

-  <VIF_Product_Type value="0">Port Product</VIF_Product_Type>

-  <Certification_Type value="0">End Product</Certification_Type>

-  <Product>

-    <Product_VID value="6353">18D1</Product_VID>

-  </Product>

-  <Component>

-    <Port_Label>0</Port_Label>

-    <Connector_Type value="2">Type-C®</Connector_Type>

-    <USB4_Supported value="false">NO</USB4_Supported>

-    <USB_PD_Support value="true">YES</USB_PD_Support>

-    <PD_Port_Type value="4">DRP</PD_Port_Type>

-    <Type_C_State_Machine value="2">DRP</Type_C_State_Machine>

-    <Captive_Cable value="false">NO</Captive_Cable>

-    <Port_Battery_Powered value="false">NO</Port_Battery_Powered>

-    <BC_1_2_Support value="0">None</BC_1_2_Support>

-    <PD_Spec_Revision_Major value="3" />

-    <PD_Spec_Revision_Minor value="0" />

-    <PD_Spec_Version_Major value="2" />

-    <PD_Spec_Version_Minor value="0" />

-    <PD_Specification_Revision value="2">Revision 3</PD_Specification_Revision>

-    <USB_Comms_Capable value="true">YES</USB_Comms_Capable>

-    <DR_Swap_To_DFP_Supported value="true">YES</DR_Swap_To_DFP_Supported>

-    <DR_Swap_To_UFP_Supported value="false">NO</DR_Swap_To_UFP_Supported>

-    <Unconstrained_Power value="false">NO</Unconstrained_Power>

-    <VCONN_Swap_To_On_Supported value="false">NO</VCONN_Swap_To_On_Supported>

-    <VCONN_Swap_To_Off_Supported value="false">NO</VCONN_Swap_To_Off_Supported>

-    <Responds_To_Discov_SOP_UFP value="false">NO</Responds_To_Discov_SOP_UFP>

-    <Responds_To_Discov_SOP_DFP value="false">NO</Responds_To_Discov_SOP_DFP>

-    <Attempts_Discov_SOP value="true">YES</Attempts_Discov_SOP>

-    <Chunking_Implemented_SOP value="false">NO</Chunking_Implemented_SOP>

-    <Unchunked_Extended_Messages_Supported value="false">NO</Unchunked_Extended_Messages_Supported>

-    <Manufacturer_Info_Supported_Port value="false">NO</Manufacturer_Info_Supported_Port>

-    <Security_Msgs_Supported_SOP value="false">NO</Security_Msgs_Supported_SOP>

-    <Num_Fixed_Batteries value="1" />

-    <Num_Swappable_Battery_Slots value="0" />

-    <ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</ID_Header_Connector_Type_SOP>

-    <SOP_Capable value="true">YES</SOP_Capable>

-    <SOP_P_Capable value="false">NO</SOP_P_Capable>

-    <SOP_PP_Capable value="false">NO</SOP_PP_Capable>

-    <SOP_P_Debug_Capable value="false">NO</SOP_P_Debug_Capable>

-    <SOP_PP_Debug_Capable value="false">NO</SOP_PP_Debug_Capable>

-    <Type_C_Implements_Try_SRC value="false">NO</Type_C_Implements_Try_SRC>

-    <Type_C_Implements_Try_SNK value="false">NO</Type_C_Implements_Try_SNK>

-    <RP_Value value="1">1.5A</RP_Value>

-    <Type_C_Is_VCONN_Powered_Accessory value="false">NO</Type_C_Is_VCONN_Powered_Accessory>

-    <Type_C_Is_Debug_Target_SRC value="true">YES</Type_C_Is_Debug_Target_SRC>

-    <Type_C_Is_Debug_Target_SNK value="true">YES</Type_C_Is_Debug_Target_SNK>

-    <Type_C_Can_Act_As_Host value="true">YES</Type_C_Can_Act_As_Host>

-    <Type_C_Is_Alt_Mode_Controller value="false">NO</Type_C_Is_Alt_Mode_Controller>

-    <Type_C_Can_Act_As_Device value="false">NO</Type_C_Can_Act_As_Device>

-    <Type_C_Power_Source value="1">UFP-powered</Type_C_Power_Source>

-    <Type_C_Port_On_Hub value="false">NO</Type_C_Port_On_Hub>

-    <Type_C_Supports_Audio_Accessory value="false">NO</Type_C_Supports_Audio_Accessory>

-    <Type_C_Sources_VCONN value="false">NO</Type_C_Sources_VCONN>

-    <PD_Power_As_Source value="15000">15000 mW</PD_Power_As_Source>

-    <USB_Suspend_May_Be_Cleared value="false">NO</USB_Suspend_May_Be_Cleared>

-    <Sends_Pings value="false">NO</Sends_Pings>

-    <FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

-    <Master_Port value="false">NO</Master_Port>

-    <Num_Src_PDOs value="1" />

-    <Host_Supports_USB_Data value="true">YES</Host_Supports_USB_Data>

-    <Host_Speed value="1">USB 3.2 GEN 1x1</Host_Speed>

-    <Is_DFP_On_Hub value="false">NO</Is_DFP_On_Hub>

-    <Host_Contains_Captive_Retimer value="false">NO</Host_Contains_Captive_Retimer>

-    <Host_Is_Embedded value="false">NO</Host_Is_Embedded>

-    <PD_OC_Protection value="false">NO</PD_OC_Protection>

-    <Product_Total_Source_Power_mW value="15000">15000 mW</Product_Total_Source_Power_mW>

-    <Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>

-    <SrcPdoList>

-      <SrcPDO>

-        <Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>

-        <Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>

-        <Src_PDO_Voltage value="100">5000 mV</Src_PDO_Voltage>

-        <Src_PDO_Max_Current value="300">3000 mA</Src_PDO_Max_Current>

-      </SrcPDO>

-    </SrcPdoList>

-  </Component>

-</VIF>

diff --git a/test/genvif/vif/over_test_vif.xml b/test/genvif/vif/over_test_vif.xml
deleted file mode 100644
index 64e1148c68..0000000000
--- a/test/genvif/vif/over_test_vif.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<VIF>

-  <!-- Override the following fields -->

-  <Model_Part_Number>SuperTestWithOverride</Model_Part_Number>

-  <Product_Revision>Final</Product_Revision>

-  <TID>12345</TID>

-

-  <Component>

-    <!-- Remove Sends_Pings -->

-    <Sends_Pings />

-

-    <SrcPdoList>

-      <SrcPDO>

-        <!-- Add in missing fields for SrcPdo0 -->

-        <Src_PD_OCP_OC_Debounce value="50">50 msec</Src_PD_OCP_OC_Debounce>

-        <Src_PD_OCP_OC_Threshold value="360">3600 mA</Src_PD_OCP_OC_Threshold>

-      </SrcPDO>

-    </SrcPdoList>

-  </Component>

-</VIF>

diff --git a/test/gyro_cal.c b/test/gyro_cal.c
deleted file mode 100644
index 10d48ca18e..0000000000
--- a/test/gyro_cal.c
+++ /dev/null
@@ -1,511 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gyro_cal.h"
-#include "gyro_still_det.h"
-#include "gyro_cal_init_for_test.h"
-#include "motion_sense.h"
-#include "test_util.h"
-#include <string.h>
-#include <stdlib.h>
-#include <math.h>
-#include <stdio.h>
-
-float kToleranceGyroRps = 1e-6f;
-float kDefaultGravityMps2 = 9.81f;
-int kDefaultTemperatureKelvin = 298;
-
-#define NANOS_TO_SEC (1.0e-9f)
-#define NANO_PI (3.14159265359f)
-/** Unit conversion: milli-degrees to radians. */
-#define MDEG_TO_RAD (NANO_PI / 180.0e3f)
-
-#define MSEC_TO_NANOS(x) ((uint64_t)((x) * (uint64_t)(1000000)))
-#define SEC_TO_NANOS(x) MSEC_TO_NANOS((x) * (uint64_t)(1000))
-#define HZ_TO_PERIOD_NANOS(hz) (SEC_TO_NANOS(1024) / ((uint64_t)((hz)*1024)))
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE] = {},
-	[LID] = {},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/**
- * This function will return a uniformly distributed random value in the range
- * of (0,1). This is important that 0 and 1 are excluded because of how the
- * value is used in normal_random. For references:
- * - rand() / RAND_MAX yields the range [0,1]
- * - rand() / (RAND_MAX + 1) yields the range [0,1)
- * - (rand() + 1) / (RAND_MAX + 1) yields the range (0, 1)
- *
- * @return A uniformly distributed random value.
- */
-static double rand_gen(void)
-{
-	return ((double)(rand()) + 1.0) / ((double)(RAND_MAX) + 1.0);
-}
-
-/**
- * @return A normally distributed random value
- */
-static float normal_random(void)
-{
-	double v1 = rand_gen();
-	double v2 = rand_gen();
-
-	return (float)(cos(2 * 3.14 * v2) * sqrt(-2.0 * log(v1)));
-}
-
-/**
- * @param mean The mean to use for the normal distribution.
- * @param stddev The standard deviation to use for the normal distribution.
- * @return A normally distributed random value based on mean and stddev.
- */
-static float normal_random2(float mean, float stddev)
-{
-	return normal_random() * stddev + mean;
-}
-
-/**
- * Tests that a calibration is updated after a period where the IMU device is
- * stationary. Accelerometer and gyroscope measurements are simulated with data
- * sheet specs for the BMI160 at their respective noise floors. A magnetometer
- * sensor is also included in this test.
- *
- * @return EC_SUCCESS on success.
- */
-static int test_gyro_cal_calibration(void)
-{
-	int i;
-	struct gyro_cal gyro_cal;
-
-	/*
-	 * Statistics for simulated gyroscope data.
-	 * RMS noise = 70mDPS, offset = 150mDPS.
-	 */
-	/* [Hz] */
-	const float sample_rate = 400.0f;
-	/* [rad/sec] */
-	const float gyro_bias = MDEG_TO_RAD * 150.0f;
-	/* [rad/sec] */
-	const float gyro_rms_noise = MDEG_TO_RAD * 70.0f;
-	const uint64_t sample_interval_nanos = HZ_TO_PERIOD_NANOS(sample_rate);
-
-	/*
-	 * Statistics for simulated accelerometer data.
-	 * noise density = 200ug/rtHz, offset = 50mg.
-	 */
-	/* [m/sec^2] */
-	const float accel_bias = 0.05f * kDefaultGravityMps2;
-	/* [m/sec^2] */
-	const float accel_rms_noise =
-		0.0002f * kDefaultGravityMps2 * fp_sqrtf(0.5f * sample_rate);
-
-	/*
-	 * Statistics for simulated magnetometer data.
-	 * RMS noise = 0.4 micro Tesla (uT), offset = 0.2uT.
-	 */
-	const float mag_bias = 0.2f; /* [uT] */
-	const float mag_rms_noise = 0.4f; /* [uT] */
-
-	float bias[3];
-	float bias_residual[3];
-	int temperature_kelvin;
-	uint32_t calibration_time_us = 0;
-
-	bool calibration_received = false;
-
-	gyro_cal_initialization_for_test(&gyro_cal);
-
-	/* No calibration should be available yet. */
-	TEST_EQ(gyro_cal_new_bias_available(&gyro_cal), false, "%d");
-
-	/*
-	 * Simulate up to 20 seconds of sensor data (zero mean, additive white
-	 * Gaussian noise).
-	 */
-	for (i = 0; i < (int)(20.0f * sample_rate); ++i) {
-		const uint32_t timestamp_us =
-			(i * sample_interval_nanos) / 1000;
-
-		/* Generate and add an accelerometer sample. */
-		gyro_cal_update_accel(
-			&gyro_cal, timestamp_us,
-			normal_random2(accel_bias, accel_rms_noise),
-			normal_random2(accel_bias, accel_rms_noise),
-			normal_random2(accel_bias, accel_rms_noise));
-
-		/* Generate and add a gyroscrope sample. */
-		gyro_cal_update_gyro(&gyro_cal, timestamp_us,
-				     normal_random2(gyro_bias, gyro_rms_noise),
-				     normal_random2(gyro_bias, gyro_rms_noise),
-				     normal_random2(gyro_bias, gyro_rms_noise),
-				     kDefaultTemperatureKelvin);
-
-		/*
-		 * The simulated magnetometer here has a sampling rate that is
-		 * 4x slower than the accel/gyro
-		 */
-		if (i % 4 == 0) {
-			gyro_cal_update_mag(
-				&gyro_cal, timestamp_us,
-				normal_random2(mag_bias, mag_rms_noise),
-				normal_random2(mag_bias, mag_rms_noise),
-				normal_random2(mag_bias, mag_rms_noise));
-		}
-		calibration_received = gyro_cal_new_bias_available(&gyro_cal);
-		if (calibration_received)
-			break;
-	}
-
-	TEST_EQ(calibration_received, true, "%d");
-
-	gyro_cal_get_bias(&gyro_cal, bias, &temperature_kelvin,
-			  &calibration_time_us);
-	bias_residual[0] = gyro_bias - bias[0];
-	bias_residual[1] = gyro_bias - bias[1];
-	bias_residual[2] = gyro_bias - bias[2];
-
-	/*
-	 * Make sure that the bias estimate is within 20 milli-degrees per
-	 * second.
-	 */
-	TEST_LT(bias_residual[0], 20.f * MDEG_TO_RAD, "%f");
-	TEST_LT(bias_residual[1], 20.f * MDEG_TO_RAD, "%f");
-	TEST_LT(bias_residual[2], 20.f * MDEG_TO_RAD, "%f");
-
-	TEST_NEAR(gyro_cal.stillness_confidence, 1.0f, 0.0001f, "%f");
-
-	TEST_EQ(temperature_kelvin, kDefaultTemperatureKelvin, "%d");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Tests that calibration does not falsely occur for low-level motion.
- *
- * @return EC_SUCCESS on success.
- */
-static int test_gyro_cal_no_calibration(void)
-{
-	int i;
-	struct gyro_cal gyro_cal;
-
-	/* Statistics for simulated gyroscope data. */
-	/* RMS noise = 70mDPS, offset = 150mDPS. */
-	const float sample_rate = 400.0f; /* [Hz] */
-	const float gyro_bias = MDEG_TO_RAD * 150.0f; /* [rad/sec] */
-	const float gyro_rms_noise = MDEG_TO_RAD * 70.0f; /* [rad/sec] */
-	const uint64_t sample_interval_nanos = HZ_TO_PERIOD_NANOS(sample_rate);
-
-	/* Statistics for simulated accelerometer data. */
-	/* noise density = 200ug/rtHz, offset = 50mg. */
-	/* [m/sec^2] */
-	const float accel_bias = 0.05f * kDefaultGravityMps2;
-	/* [m/sec^2] */
-	const float accel_rms_noise =
-		200.0e-6f * kDefaultGravityMps2 * fp_sqrtf(0.5f * sample_rate);
-
-	/* Define sinusoidal gyroscope motion parameters. */
-	const float omega_dt =
-		2.0f * NANO_PI * sample_interval_nanos * NANOS_TO_SEC;
-	const float amplitude = MDEG_TO_RAD * 550.0f; /* [rad/sec] */
-
-	bool calibration_received = false;
-
-	gyro_cal_initialization_for_test(&gyro_cal);
-
-	for (i = 0; i < (int)(20.0f * sample_rate); ++i) {
-		const uint32_t timestamp_us =
-			(i * sample_interval_nanos) / 1000;
-
-		/* Generate and add an accelerometer sample. */
-		gyro_cal_update_accel(
-			&gyro_cal, timestamp_us,
-			normal_random2(accel_bias, accel_rms_noise),
-			normal_random2(accel_bias, accel_rms_noise),
-			normal_random2(accel_bias, accel_rms_noise));
-
-		/* Generate and add a gyroscope sample. */
-		gyro_cal_update_gyro(
-			&gyro_cal, timestamp_us,
-			normal_random2(gyro_bias, gyro_rms_noise) +
-				amplitude * sin(2.0f * omega_dt * i),
-			normal_random2(gyro_bias, gyro_rms_noise) -
-				amplitude * sin(2.1f * omega_dt * i),
-			normal_random2(gyro_bias, gyro_rms_noise) +
-				amplitude * cos(4.3f * omega_dt * i),
-			kDefaultTemperatureKelvin);
-
-		/* Check for calibration update. Break after first one. */
-		calibration_received = gyro_cal_new_bias_available(&gyro_cal);
-		if (calibration_received)
-			break;
-	}
-
-	/* Determine that NO calibration had occurred. */
-	TEST_EQ(calibration_received, false, "%d");
-
-	/* Make sure that the device was NOT classified as "still". */
-	TEST_GT(1.0f, gyro_cal.stillness_confidence, "%f");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Tests that a shift in a stillness window mean does not trigger a calibration.
- *
- * @return EC_SUCCESS on success.
- */
-static int test_gyro_cal_win_mean_shift(void)
-{
-	struct gyro_cal gyro_cal;
-	int i;
-
-	/* Statistics for simulated gyroscope data. */
-	const float sample_rate = 400.0f; /* [Hz] */
-	const float gyro_bias = MDEG_TO_RAD * 150.0f; /* [rad/sec] */
-	const float gyro_bias_shift = MDEG_TO_RAD * 60.0f; /* [rad/sec] */
-	const uint64_t sample_interval_nanos = HZ_TO_PERIOD_NANOS(sample_rate);
-
-	/* Initialize the gyro calibration. */
-	gyro_cal_initialization_for_test(&gyro_cal);
-
-	/*
-	 * Simulates 8 seconds of sensor data (no noise, just a gyro mean shift
-	 * after 4 seconds).
-	 * Assumptions: The max stillness period is 6 seconds, and the mean
-	 * delta limit is 50mDPS. The mean shift should be detected and exceed
-	 * the 50mDPS limit, and no calibration should be triggered. NOTE: This
-	 * step is not large enough to trip the variance checking within the
-	 * stillness detectors.
-	 */
-	for (i = 0; i < (int)(8.0f * sample_rate); i++) {
-		const uint32_t timestamp_us =
-			(i * sample_interval_nanos) / 1000;
-
-		/* Generate and add a accelerometer sample. */
-		gyro_cal_update_accel(&gyro_cal, timestamp_us, 0.0f, 0.0f,
-				      9.81f);
-
-		/* Generate and add a gyroscope sample. */
-		if (timestamp_us > 4 * SECOND) {
-			gyro_cal_update_gyro(&gyro_cal, timestamp_us,
-					     gyro_bias + gyro_bias_shift,
-					     gyro_bias + gyro_bias_shift,
-					     gyro_bias + gyro_bias_shift,
-					     kDefaultTemperatureKelvin);
-		} else {
-			gyro_cal_update_gyro(&gyro_cal, timestamp_us, gyro_bias,
-					     gyro_bias, gyro_bias,
-					     kDefaultTemperatureKelvin);
-		}
-	}
-
-	/* Determine that NO calibration had occurred. */
-	TEST_EQ(gyro_cal_new_bias_available(&gyro_cal), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Tests that a temperature variation outside the acceptable range prevents a
- * calibration.
- *
- * @return EC_SUCCESS on success.
- */
-static int test_gyro_cal_temperature_shift(void)
-{
-	int i;
-	struct gyro_cal gyro_cal;
-
-	/* Statistics for simulated gyroscope data. */
-	const float sample_rate = 400.0f; /* [Hz] */
-	const float gyro_bias = MDEG_TO_RAD * 150.0f; /* [rad/sec] */
-	const float temperature_shift_kelvin = 2.6f;
-	const uint64_t sample_interval_nanos = HZ_TO_PERIOD_NANOS(sample_rate);
-
-	gyro_cal_initialization_for_test(&gyro_cal);
-
-	/*
-	 * Simulates 8 seconds of sensor data (no noise, just a temperature
-	 * shift after 4 seconds).
-	 * Assumptions: The max stillness period is 6 seconds, and the
-	 * temperature delta limit is 1.5C. The shift should be detected and
-	 * exceed the limit, and no calibration should be triggered.
-	 */
-	for (i = 0; i < (int)(8.0f * sample_rate); i++) {
-		const uint32_t timestamp_us =
-			(i * sample_interval_nanos) / 1000;
-		float temperature_kelvin = kDefaultTemperatureKelvin;
-
-		/* Generate and add a accelerometer sample. */
-		gyro_cal_update_accel(&gyro_cal, timestamp_us, 0.0f, 0.0f,
-				      9.81f);
-
-		/* Sets the temperature value. */
-		if (timestamp_us > 4 * SECOND)
-			temperature_kelvin += temperature_shift_kelvin;
-
-		/* Generate and add a gyroscope sample. */
-		gyro_cal_update_gyro(&gyro_cal, timestamp_us, gyro_bias,
-				     gyro_bias, gyro_bias,
-				     (int)temperature_kelvin);
-	}
-
-	/* Determine that NO calibration had occurred. */
-	TEST_EQ(gyro_cal_new_bias_available(&gyro_cal), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Verifies that complete sensor stillness results in the correct bias estimate
- * and produces the correct timestamp.
- *
- * @return EC_SUCCESS on success;
- */
-static int test_gyro_cal_stillness_timestamp(void)
-{
-	struct gyro_cal gyro_cal;
-	int64_t time_us;
-
-	/*
-	 * 10Hz update rate for 11 seconds should trigger the in-situ
-	 * algorithms.
-	 */
-	const float gyro_bias_x = 0.09f;
-	const float gyro_bias_y = -0.04f;
-	const float gyro_bias_z = 0.05f;
-
-	float bias[3];
-	int temperature_kelvin = 273;
-	uint32_t calibration_time_us = 0;
-
-	gyro_cal_initialization_for_test(&gyro_cal);
-	for (time_us = 0; time_us < 11 * SECOND; time_us += 100 * MSEC) {
-		/* Generate and add a accelerometer sample. */
-		gyro_cal_update_accel(&gyro_cal, time_us, 0.0f, 0.0f, 9.81f);
-
-		/* Generate and add a gyroscope sample. */
-		gyro_cal_update_gyro(&gyro_cal, time_us, gyro_bias_x,
-				     gyro_bias_y, gyro_bias_z,
-				     kDefaultTemperatureKelvin);
-	}
-
-	/* Determine if there is a new calibration. Get the calibration value.
-	 */
-	TEST_EQ(gyro_cal_new_bias_available(&gyro_cal), 1, "%d");
-
-	gyro_cal_get_bias(&gyro_cal, bias, &temperature_kelvin,
-			  &calibration_time_us);
-
-	/* Make sure that the bias estimate is within kToleranceGyroRps. */
-	TEST_NEAR(gyro_bias_x - bias[0], 0.0f, 0.0001f, "%f");
-	TEST_NEAR(gyro_bias_y - bias[1], 0.0f, 0.0001f, "%f");
-	TEST_NEAR(gyro_bias_z - bias[2], 0.0f, 0.0001f, "%f");
-
-	/* Checks that the calibration occurred at the expected time. */
-	TEST_EQ(6 * SECOND, gyro_cal.calibration_time_us, "%u");
-
-	/* Make sure that the device was classified as 100% "still". */
-	TEST_NEAR(1.0f, gyro_cal.stillness_confidence, 0.0001f, "%f");
-
-	/* Make sure that the calibration temperature is correct. */
-	TEST_EQ(kDefaultTemperatureKelvin, temperature_kelvin, "%d");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Verifies that setting an initial bias works.
- *
- * @return EC_SUCCESS on success.
- */
-static int test_gyro_cal_set_bias(void)
-{
-	struct gyro_cal gyro_cal;
-
-	/* Get the initialized bias value; should be zero. */
-	float bias[3] = { 0.0f, 0.0f, 0.0f };
-	int temperature_kelvin = 273;
-	uint32_t calibration_time_us = 10;
-
-	/* Initialize the gyro calibration. */
-	gyro_cal_initialization_for_test(&gyro_cal);
-	gyro_cal_get_bias(&gyro_cal, bias, &temperature_kelvin,
-			  &calibration_time_us);
-	TEST_NEAR(0.0f, bias[0], 0.0001f, "%f");
-	TEST_NEAR(0.0f, bias[1], 0.0001f, "%f");
-	TEST_NEAR(0.0f, bias[2], 0.0001f, "%f");
-	TEST_EQ(0, temperature_kelvin, "%d");
-	TEST_EQ(0, calibration_time_us, "%d");
-
-	/* Set the calibration bias estimate. */
-	bias[0] = 1.0f;
-	bias[1] = 2.0f;
-	bias[2] = 3.0f;
-	gyro_cal_set_bias(&gyro_cal, bias, 31, 3 * 60 * SECOND);
-
-	bias[0] = 0.0f;
-	bias[1] = 0.0f;
-	bias[2] = 0.0f;
-	/* Check that it was set correctly. */
-	gyro_cal_get_bias(&gyro_cal, bias, &temperature_kelvin,
-			  &calibration_time_us);
-	TEST_NEAR(1.0f, bias[0], 0.0001f, "%f");
-	TEST_NEAR(2.0f, bias[1], 0.0001f, "%f");
-	TEST_NEAR(3.0f, bias[2], 0.0001f, "%f");
-	TEST_EQ(31, temperature_kelvin, "%d");
-	TEST_EQ(3 * 60 * SECOND, calibration_time_us, "%u");
-
-	return EC_SUCCESS;
-}
-
-/**
- * Verifies that the gyroCalRemoveBias function works as intended.
- *
- * @return EC_SUCCESS on success
- */
-static int test_gyro_cal_remove_bias(void)
-{
-	struct gyro_cal gyro_cal;
-	float bias[3] = { 1.0f, 2.0f, 3.0f };
-	float bias_out[3];
-
-	/* Initialize the gyro calibration. */
-	gyro_cal_initialization_for_test(&gyro_cal);
-
-	/* Set an calibration bias estimate. */
-	gyro_cal_set_bias(&gyro_cal, bias, kDefaultTemperatureKelvin,
-			  5 * 60 * SECOND);
-
-	/* Correct the bias, and check that it has been adequately removed. */
-	gyro_cal_remove_bias(&gyro_cal, bias, bias_out);
-
-	/* Make sure that the bias estimate is within kToleranceGyroRps. */
-	TEST_NEAR(0.0f, bias_out[0], 0.0001f, "%f");
-	TEST_NEAR(0.0f, bias_out[1], 0.0001f, "%f");
-	TEST_NEAR(0.0f, bias_out[2], 0.0001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_gyro_cal_calibration);
-	RUN_TEST(test_gyro_cal_no_calibration);
-	RUN_TEST(test_gyro_cal_win_mean_shift);
-	RUN_TEST(test_gyro_cal_temperature_shift);
-	RUN_TEST(test_gyro_cal_stillness_timestamp);
-	RUN_TEST(test_gyro_cal_set_bias);
-	RUN_TEST(test_gyro_cal_remove_bias);
-
-	test_print_result();
-}
diff --git a/test/gyro_cal.tasklist b/test/gyro_cal.tasklist
deleted file mode 100644
index 7d28eb5b64..0000000000
--- a/test/gyro_cal.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/gyro_cal_init_for_test.c b/test/gyro_cal_init_for_test.c
deleted file mode 100644
index 3963e5a207..0000000000
--- a/test/gyro_cal_init_for_test.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "timer.h"
-#include "gyro_cal_init_for_test.h"
-#include <string.h>
-
-#define NANO_PI (3.14159265359f)
-/** Unit conversion: milli-degrees to radians. */
-#define MDEG_TO_RAD (NANO_PI / 180.0e3f)
-
-/**
- *
- * @param det              Pointer to the stillness detector
- * @param var_threshold    The variance threshold in units^2
- * @param confidence_delta The confidence delta in units^2
- */
-static void gyro_still_det_initialization_for_test(struct gyro_still_det *det,
-						   float var_threshold,
-						   float confidence_delta)
-{
-	/* Clear all data structure variables to 0. */
-	memset(det, 0, sizeof(struct gyro_still_det));
-
-	/*
-	 * Set the delta about the variance threshold for calculation
-	 * of the stillness confidence score.
-	 */
-	if (confidence_delta < var_threshold)
-		det->confidence_delta = confidence_delta;
-	else
-		det->confidence_delta = var_threshold;
-
-	/*
-	 * Set the variance threshold parameter for the stillness
-	 * confidence score.
-	 */
-	det->var_threshold = var_threshold;
-
-	/* Signal to start capture of next stillness data window. */
-	det->start_new_window = true;
-}
-
-void gyro_cal_initialization_for_test(struct gyro_cal *gyro_cal)
-{
-	/* GyroCal initialization. */
-	memset(gyro_cal, 0, sizeof(struct gyro_cal));
-
-	/*
-	 * Initialize the stillness detectors.
-	 * Gyro parameter input units are [rad/sec].
-	 * Accel parameter input units are [m/sec^2].
-	 * Magnetometer parameter input units are [uT].
-	 */
-	gyro_still_det_initialization_for_test(&gyro_cal->gyro_stillness_detect,
-					       /* var_threshold */ 5e-5f,
-					       /* confidence_delta */ 1e-5f);
-	gyro_still_det_initialization_for_test(
-		&gyro_cal->accel_stillness_detect,
-		/* var_threshold */ 8e-3f,
-		/* confidence_delta */ 1.6e-3f);
-	gyro_still_det_initialization_for_test(&gyro_cal->mag_stillness_detect,
-					       /* var_threshold */ 1.4f,
-					       /* confidence_delta */ 0.25f);
-
-	/* Reset stillness flag and start timestamp. */
-	gyro_cal->prev_still = false;
-	gyro_cal->start_still_time_us = 0;
-
-	/* Set the min and max window stillness duration. */
-	gyro_cal->min_still_duration_us = 5 * SECOND;
-	gyro_cal->max_still_duration_us = 6 * SECOND;
-
-	/* Sets the duration of the stillness processing windows. */
-	gyro_cal->window_time_duration_us = 1500000;
-
-	/* Set the window timeout duration. */
-	gyro_cal->gyro_window_timeout_duration_us = 5 * SECOND;
-
-	/* Load the last valid cal from system memory. */
-	gyro_cal->bias_x = 0.0f; /* [rad/sec] */
-	gyro_cal->bias_y = 0.0f; /* [rad/sec] */
-	gyro_cal->bias_z = 0.0f; /* [rad/sec] */
-	gyro_cal->calibration_time_us = 0;
-
-	/* Set the stillness threshold required for gyro bias calibration. */
-	gyro_cal->stillness_threshold = 0.95f;
-
-	/*
-	 * Current window end-time used to assist in keeping sensor data
-	 * collection in sync. Setting this to zero signals that sensor data
-	 * will be dropped until a valid end-time is set from the first gyro
-	 * timestamp received.
-	 */
-	gyro_cal->stillness_win_endtime_us = 0;
-
-	/* Gyro calibrations will be applied (see, gyro_cal_remove_bias()). */
-	gyro_cal->gyro_calibration_enable = true;
-
-	/*
-	 * Sets the stability limit for the stillness window mean acceptable
-	 * delta.
-	 */
-	gyro_cal->stillness_mean_delta_limit = 50.0f * MDEG_TO_RAD;
-
-	/* Sets the min/max temperature delta limit for the stillness period. */
-	gyro_cal->temperature_delta_limit_kelvin = 1.5f;
-
-	/* Ensures that the data tracking functionality is reset. */
-	init_gyro_cal(gyro_cal);
-}
diff --git a/test/gyro_cal_init_for_test.h b/test/gyro_cal_init_for_test.h
deleted file mode 100644
index e32040bab9..0000000000
--- a/test/gyro_cal_init_for_test.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_GYRO_CAL_INIT_FOR_TEST
-#define __CROS_EC_GYRO_CAL_INIT_FOR_TEST
-
-#include "gyro_cal.h"
-#include "gyro_still_det.h"
-
-/**
- * Initialization function used for testing the gyroscope calibration.
- * This function will initialize to the following values:
- * - Gyrscope stillness detector
- *   - variance threshold:		5e-5
- *   - confidence delta:		1e-5
- * - Accelerometer stillness detector
- *   - variance threshold:		8e-3
- *   - confidence delta:		1.6e-3
- * - Magnetometer stillness detector
- *   - variance threshold:		1.4
- *   - confidence delta:		2.5e-1
- * - Minimum stillness duration:	5 seconds
- * - Maximum stillness duration:	6 seconds
- * - Window duration:			1.5 seconds
- * - Window timeout duration:		5 seconds
- * - Stillness threshold:		0.95
- * - Stillness mean delta limit:	50 millidegrees
- * - Temperature delta limit:		1.5K
- *
- * Once all the values are set, this function will call init_gyro_cal()
- * to finish initializing/resetting the struct data.
- *
- * @param gyro_cal Pointer to the calibration data structure to initialize.
- */
-void gyro_cal_initialization_for_test(struct gyro_cal *gyro_cal);
-
-#endif /* __CROS_EC_GYRO_CAL_INIT_FOR_TEST */
diff --git a/test/hooks.c b/test/hooks.c
deleted file mode 100644
index 8d12494688..0000000000
--- a/test/hooks.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test hooks.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int init_hook_count;
-static int tick_hook_count;
-static int tick2_hook_count;
-static int tick_count_seen_by_tick2;
-static timestamp_t tick_time[2];
-static int second_hook_count;
-static timestamp_t second_time[2];
-static int deferred_call_count;
-
-static void init_hook(void)
-{
-	init_hook_count++;
-}
-DECLARE_HOOK(HOOK_INIT, init_hook, HOOK_PRIO_DEFAULT);
-
-static void tick_hook(void)
-{
-	tick_hook_count++;
-	tick_time[0] = tick_time[1];
-	tick_time[1] = get_time();
-}
-DECLARE_HOOK(HOOK_TICK, tick_hook, HOOK_PRIO_DEFAULT);
-
-static void tick2_hook(void)
-{
-	tick2_hook_count++;
-	tick_count_seen_by_tick2 = tick_hook_count;
-}
-/* tick2_hook() prio means it should be called after tick_hook() */
-DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT+1);
-
-static void second_hook(void)
-{
-	second_hook_count++;
-	second_time[0] = second_time[1];
-	second_time[1] = get_time();
-}
-DECLARE_HOOK(HOOK_SECOND, second_hook, HOOK_PRIO_DEFAULT);
-
-static void deferred_func(void)
-{
-	deferred_call_count++;
-}
-DECLARE_DEFERRED(deferred_func);
-
-static void non_deferred_func(void)
-{
-	deferred_call_count++;
-}
-
-static const struct deferred_data non_deferred_func_data = {
-	non_deferred_func
-};
-
-static int test_init_hook(void)
-{
-	TEST_ASSERT(init_hook_count == 1);
-	return EC_SUCCESS;
-}
-
-static int test_ticks(void)
-{
-	int64_t interval;
-	int error_pct;
-
-	/*
-	 * HOOK_SECOND must have been fired at least once when HOOK
-	 * task starts. We only need to wait for just more than a second
-	 * to allow it fires for the second time.
-	 */
-	usleep(1300 * MSEC);
-
-	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
-	TEST_ASSERT_ABS_LESS(error_pct, 10);
-
-	interval = second_time[1].val - second_time[0].val;
-	error_pct = (interval - SECOND) * 100 / SECOND;
-	TEST_ASSERT_ABS_LESS(error_pct, 10);
-
-	return EC_SUCCESS;
-}
-
-static int test_priority(void)
-{
-	usleep(HOOK_TICK_INTERVAL);
-	TEST_ASSERT(tick_hook_count == tick2_hook_count);
-	TEST_ASSERT(tick_hook_count == tick_count_seen_by_tick2);
-
-	return EC_SUCCESS;
-}
-
-static int test_deferred(void)
-{
-	deferred_call_count = 0;
-	hook_call_deferred(&deferred_func_data, 50 * MSEC);
-	usleep(100 * MSEC);
-	TEST_ASSERT(deferred_call_count == 1);
-
-	hook_call_deferred(&deferred_func_data, 50 * MSEC);
-	usleep(25 * MSEC);
-	hook_call_deferred(&deferred_func_data, -1);
-	usleep(75 * MSEC);
-	TEST_ASSERT(deferred_call_count == 1);
-
-	hook_call_deferred(&deferred_func_data, 50 * MSEC);
-	usleep(25 * MSEC);
-	hook_call_deferred(&deferred_func_data, -1);
-	usleep(15 * MSEC);
-	hook_call_deferred(&deferred_func_data, 25 * MSEC);
-	usleep(50 * MSEC);
-	TEST_ASSERT(deferred_call_count == 2);
-
-	TEST_ASSERT(hook_call_deferred(&non_deferred_func_data, 50 * MSEC) !=
-		    EC_SUCCESS);
-	usleep(100 * MSEC);
-	TEST_ASSERT(deferred_call_count == 2);
-
-	return EC_SUCCESS;
-}
-
-static int repeating_deferred_count;
-static void deferred_repeating_func(void);
-DECLARE_DEFERRED(deferred_repeating_func);
-
-static void deferred_repeating_func(void)
-{
-	++repeating_deferred_count;
-
-	usleep(100 * MSEC);
-	if (repeating_deferred_count < 5)
-		hook_call_deferred(&deferred_repeating_func_data, SECOND);
-
-	usleep(100 * MSEC);
-}
-
-static int test_repeating_deferred(void)
-{
-	repeating_deferred_count = 0;
-	hook_call_deferred(&deferred_repeating_func_data, 0);
-	usleep(MINUTE);
-	TEST_EQ(repeating_deferred_count, 5, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_init_hook);
-	RUN_TEST(test_ticks);
-	RUN_TEST(test_priority);
-	RUN_TEST(test_deferred);
-	RUN_TEST(test_repeating_deferred);
-
-	test_print_result();
-}
diff --git a/test/hooks.tasklist b/test/hooks.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/hooks.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/host_command.c b/test/host_command.c
deleted file mode 100644
index ba1d4dcd96..0000000000
--- a/test/host_command.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test host command.
- */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-/* Request/response buffer size (and maximum command length) */
-#define BUFFER_SIZE 128
-
-struct host_packet pkt;
-static char resp_buf[BUFFER_SIZE];
-static char req_buf[BUFFER_SIZE + 4];
-struct ec_host_request *req = (struct ec_host_request *)req_buf;
-struct ec_params_hello *p = (struct ec_params_hello *)(req_buf + sizeof(*req));
-struct ec_host_response *resp = (struct ec_host_response *)resp_buf;
-struct ec_response_hello *r =
-	(struct ec_response_hello *)(resp_buf + sizeof(*resp));
-struct ec_response_get_chip_info *chip_info_r =
-	(struct ec_response_get_chip_info *)(resp_buf + sizeof(*resp));
-
-static void hostcmd_respond(struct host_packet *pkt)
-{
-	task_wake(TASK_ID_TEST_RUNNER);
-}
-
-static char calculate_checksum(const char *buf, int size)
-{
-	int c = 0;
-	int i;
-
-	for (i = 0; i < size; ++i)
-		c += buf[i];
-
-	return -c;
-}
-
-static void hostcmd_send(void)
-{
-	req->checksum = calculate_checksum(req_buf, pkt.request_size);
-	host_packet_receive(&pkt);
-	task_wait_event(-1);
-}
-
-static void hostcmd_fill_in_default(void)
-{
-	req->struct_version = 3;
-	req->checksum = 0;
-	req->command = EC_CMD_HELLO;
-	req->command_version = 0;
-	req->reserved = 0;
-	req->data_len = 4;
-	p->in_data = 0x11223344;
-
-	pkt.send_response = hostcmd_respond;
-	pkt.request = (const void *)req_buf;
-	pkt.request_temp = NULL;
-	pkt.request_max = BUFFER_SIZE;
-	pkt.request_size = sizeof(*req) + sizeof(*p);
-	pkt.response = (void *)resp_buf;
-	pkt.response_max = BUFFER_SIZE;
-	pkt.driver_result = 0;
-}
-
-static int test_hostcmd_ok(void)
-{
-	hostcmd_fill_in_default();
-
-	hostcmd_send();
-
-	TEST_ASSERT(calculate_checksum(resp_buf,
-				       sizeof(*resp) + resp->data_len) == 0);
-	TEST_ASSERT(resp->result == EC_RES_SUCCESS);
-	TEST_ASSERT(r->out_data == 0x12243648);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_too_short(void)
-{
-	hostcmd_fill_in_default();
-
-	/* Smaller than header */
-	pkt.request_size = sizeof(*req) - 4;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_REQUEST_TRUNCATED);
-
-	/* Smaller than expected data size */
-	pkt.request_size = sizeof(*req);
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_REQUEST_TRUNCATED);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_too_long(void)
-{
-	hostcmd_fill_in_default();
-
-	/* Larger than request buffer */
-	pkt.request_size = BUFFER_SIZE + 4;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_REQUEST_TRUNCATED);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_driver_error(void)
-{
-	hostcmd_fill_in_default();
-
-	pkt.driver_result = EC_RES_ERROR;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_ERROR);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_invalid_command(void)
-{
-	hostcmd_fill_in_default();
-
-	req->command = 0xff;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_INVALID_COMMAND);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_wrong_command_version(void)
-{
-	hostcmd_fill_in_default();
-
-	req->command_version = 1;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_INVALID_VERSION);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_wrong_struct_version(void)
-{
-	hostcmd_fill_in_default();
-
-	req->struct_version = 4;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_INVALID_HEADER);
-
-	req->struct_version = 2;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_INVALID_HEADER);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_invalid_checksum(void)
-{
-	hostcmd_fill_in_default();
-
-	req->checksum++;
-	hostcmd_send();
-	TEST_ASSERT(resp->result == EC_RES_INVALID_CHECKSUM);
-
-	return EC_SUCCESS;
-}
-
-static int test_hostcmd_reuse_response_buffer(void)
-{
-	struct ec_host_request *h = (struct ec_host_request *)resp_buf;
-	struct ec_params_hello *d =
-		(struct ec_params_hello *)(resp_buf + sizeof(*h));
-
-	h->struct_version = 3;
-	h->checksum = 0;
-	h->command = EC_CMD_HELLO;
-	h->command_version = 0;
-	h->reserved = 0;
-	h->data_len = 4;
-	d->in_data = 0x11223344;
-
-	pkt.send_response = hostcmd_respond;
-	/*
-	 * The original request buffer is shared with the response and the
-	 * request buffer is used as the temporary buffer
-	 */
-	pkt.request = (const void *)resp_buf;
-	pkt.request_temp = req_buf;
-	pkt.request_max = BUFFER_SIZE;
-	pkt.request_size = sizeof(*h) + sizeof(*d);
-	pkt.response = (void *)resp_buf;
-	pkt.response_max = BUFFER_SIZE;
-	pkt.driver_result = 0;
-
-	h->checksum = calculate_checksum(resp_buf, pkt.request_size);
-
-	ccprintf("\nBuffer contents before process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
-	host_packet_receive(&pkt);
-	task_wait_event(-1);
-
-	ccprintf("\nBuffer contents after process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
-
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
-	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
-	TEST_EQ(r->out_data, 0x12243648, "0x%x");
-
-	return EC_SUCCESS;
-}
-
-static void hostcmd_fill_chip_info(void)
-{
-	req->struct_version = 3;
-	req->checksum = 0;
-	req->command = EC_CMD_GET_CHIP_INFO;
-	req->command_version = 0;
-	req->reserved = 0;
-	req->data_len = 0;
-
-	pkt.send_response = hostcmd_respond;
-	pkt.request = (const void *)req_buf;
-	pkt.request_temp = NULL;
-	pkt.request_max = BUFFER_SIZE;
-	pkt.request_size = sizeof(*req);
-	pkt.response = (void *)resp_buf;
-	pkt.response_max = BUFFER_SIZE;
-	pkt.driver_result = 0;
-}
-
-static int test_hostcmd_clears_unused_data(void)
-{
-	int i, found_null;
-
-	/* Set the buffer to junk and ensure that is gets cleared */
-	memset(resp_buf, 0xAA, BUFFER_SIZE);
-	hostcmd_fill_chip_info();
-
-	hostcmd_send();
-
-	ccprintf("\nBuffer contents 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
-
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
-	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
-
-	/* Ensure partial strings have 0s after the NULL byte */
-	found_null = 0;
-	for (i = 0; i < sizeof(chip_info_r->name); ++i) {
-		if (!chip_info_r->name[i])
-			found_null = 1;
-
-		if (found_null) {
-			if (chip_info_r->name[i])
-				ccprintf("\nByte %d is not zero!\n", i);
-			TEST_EQ(chip_info_r->name[i], 0, "0x%x");
-		}
-	}
-
-	found_null = 0;
-	for (i = 0; i < sizeof(chip_info_r->revision); ++i) {
-		if (!chip_info_r->revision[i])
-			found_null = 1;
-
-		if (found_null) {
-			if (chip_info_r->revision[i])
-				ccprintf("\nByte %d is not zero!\n", i);
-			TEST_EQ(chip_info_r->revision[i], 0, "0x%x");
-		}
-	}
-
-	found_null = 0;
-	for (i = 0; i < sizeof(chip_info_r->vendor); ++i) {
-		if (!chip_info_r->vendor[i])
-			found_null = 1;
-
-		if (found_null) {
-			if (chip_info_r->vendor[i])
-				ccprintf("\nByte %d is not zero!\n", i);
-			TEST_EQ(chip_info_r->vendor[i], 0, "0x%x");
-		}
-	}
-
-	/* Ensure rest of buffer after valid response is also 0 */
-	for (i = resp->data_len + sizeof(*resp) + 1; i < BUFFER_SIZE; ++i) {
-		if (resp_buf[i])
-			ccprintf("\nByte %d is not zero!\n", i);
-		TEST_EQ(resp_buf[i], 0, "0x%x");
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	wait_for_task_started();
-	test_reset();
-
-	RUN_TEST(test_hostcmd_ok);
-	RUN_TEST(test_hostcmd_too_short);
-	RUN_TEST(test_hostcmd_too_long);
-	RUN_TEST(test_hostcmd_driver_error);
-	RUN_TEST(test_hostcmd_invalid_command);
-	RUN_TEST(test_hostcmd_wrong_command_version);
-	RUN_TEST(test_hostcmd_wrong_struct_version);
-	RUN_TEST(test_hostcmd_invalid_checksum);
-	RUN_TEST(test_hostcmd_reuse_response_buffer);
-	RUN_TEST(test_hostcmd_clears_unused_data);
-
-	test_print_result();
-}
diff --git a/test/host_command.tasklist b/test/host_command.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/host_command.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/i2c_bitbang.c b/test/i2c_bitbang.c
deleted file mode 100644
index ab1136a922..0000000000
--- a/test/i2c_bitbang.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "i2c.h"
-#include "i2c_bitbang.h"
-#include "test_util.h"
-#include "util.h"
-
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{"", 0, 100, GPIO_I2C_SCL, GPIO_I2C_SDA}
-};
-const unsigned int i2c_bitbang_ports_used = 1;
-
-struct pin_state {
-	int scl, sda;
-} history[64];
-
-int history_count;
-
-void reset_state(void)
-{
-	history[0] = (struct pin_state) {1, 1};
-	history_count = 1;
-	bitbang_set_started(0);
-}
-
-void gpio_set_level(enum gpio_signal signal, int level)
-{
-	struct pin_state new = history[history_count - 1];
-
-	/* reject if stack is full */
-	if (history_count >= ARRAY_SIZE(history))
-		return;
-
-	if (signal == GPIO_I2C_SDA)
-		new.sda = level;
-	else if (signal == GPIO_I2C_SCL)
-		new.scl = level;
-
-	if (new.scl != history[history_count - 1].scl ||
-			new.sda != history[history_count - 1].sda)
-		history[history_count++] = new;
-}
-
-int gpio_get_level(enum gpio_signal signal)
-{
-	if (signal == GPIO_I2C_SDA)
-		return history[history_count - 1].sda;
-	else if (signal == GPIO_I2C_SCL)
-		return history[history_count - 1].scl;
-
-	return 0;
-}
-
-static int test_i2c_start_stop(void)
-{
-	struct pin_state expected[] = {
-		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
-		/* stop */
-		{1, 0},
-		{1, 1},
-	};
-	int i;
-
-	reset_state();
-
-	bitbang_start_cond(&i2c_bitbang_ports[0]);
-	bitbang_stop_cond(&i2c_bitbang_ports[0]);
-
-	TEST_EQ((int)ARRAY_SIZE(expected), history_count, "%d");
-
-	for (i = 0; i < ARRAY_SIZE(expected); i++) {
-		TEST_EQ(expected[i].scl, history[i].scl, "%d");
-		TEST_EQ(expected[i].sda, history[i].sda, "%d");
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_i2c_repeated_start(void)
-{
-	struct pin_state expected[] = {
-		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
-		/* repeated start */
-		{0, 1},
-		{1, 1},
-		{1, 0},
-		{0, 0},
-	};
-	int i;
-
-	reset_state();
-
-	bitbang_start_cond(&i2c_bitbang_ports[0]);
-	bitbang_start_cond(&i2c_bitbang_ports[0]);
-
-	TEST_EQ((int)ARRAY_SIZE(expected), history_count, "%d");
-
-	for (i = 0; i < ARRAY_SIZE(expected); i++) {
-		TEST_EQ(expected[i].scl, history[i].scl, "%d");
-		TEST_EQ(expected[i].sda, history[i].sda, "%d");
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_i2c_write(void)
-{
-	struct pin_state expected[] = {
-		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
-		/* bit 7: 0 */
-		{1, 0},
-		{0, 0},
-		/* bit 6: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
-		/* bit 5: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
-		/* bit 4: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
-		/* bit 3: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
-		/* bit 2: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
-		/* bit 1: 1 */
-		{1, 1},
-		{0, 1},
-		/* bit 0: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
-		/* read bit */
-		{0, 1},
-		{1, 1},
-		{0, 1},
-		/* stop */
-		{0, 0},
-		{1, 0},
-		{1, 1},
-	};
-	int i, ret;
-
-	reset_state();
-
-	bitbang_start_cond(&i2c_bitbang_ports[0]);
-	ret = bitbang_write_byte(&i2c_bitbang_ports[0], 0x56);
-
-	/* expected to fail because no slave answering the nack bit */
-	TEST_EQ(EC_ERROR_BUSY, ret, "%d");
-
-	TEST_EQ((int)ARRAY_SIZE(expected), history_count, "%d");
-
-	for (i = 0; i < ARRAY_SIZE(expected); i++) {
-		TEST_EQ(expected[i].scl, history[i].scl, "%d");
-		TEST_EQ(expected[i].sda, history[i].sda, "%d");
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_i2c_start_stop);
-	RUN_TEST(test_i2c_repeated_start);
-	RUN_TEST(test_i2c_write);
-
-	test_print_result();
-}
diff --git a/test/i2c_bitbang.tasklist b/test/i2c_bitbang.tasklist
deleted file mode 100644
index 9fc1a80f4d..0000000000
--- a/test/i2c_bitbang.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/inductive_charging.c b/test/inductive_charging.c
deleted file mode 100644
index d487e171fd..0000000000
--- a/test/inductive_charging.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test inductive charging module.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "inductive_charging.h"
-#include "lid_switch.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#define START_CHARGE_DELAY 5000 /* ms */
-#define MONITOR_CHARGE_DONE_DELAY 1000 /* ms */
-#define TEST_CHECK_CHARGE_DELAY (START_CHARGE_DELAY + \
-				 MONITOR_CHARGE_DONE_DELAY + 500) /* ms */
-
-static void wait_for_lid_debounce(void)
-{
-	while (lid_is_open() != gpio_get_level(GPIO_LID_OPEN))
-		msleep(20);
-}
-
-static void set_lid_open(int lid_open)
-{
-	gpio_set_level(GPIO_LID_OPEN, lid_open);
-	wait_for_lid_debounce();
-}
-
-static int test_lid(void)
-{
-	/* Lid is open initially */
-	set_lid_open(1);
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-
-	/*
-	 * Close the lid. The EC should wait for 5 second before
-	 * enabling transmitter.
-	 */
-	set_lid_open(0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-
-	/* Transmitter should now be enabled. */
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-
-	/* Open the lid. Charging should stop. */
-	set_lid_open(1);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_charge_done(void)
-{
-	/* Close the lid to start charging */
-	set_lid_open(0);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-
-	/* Charging is done. Stop charging, but don't turn off transmitter. */
-	gpio_set_level(GPIO_CHARGE_DONE, 1);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	/* Oops, CHARGE_DONE changes again. We should ignore it. */
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	/* Open the lid. Charger should be turned off. */
-	set_lid_open(1);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_lid_open_during_charging(void)
-{
-	/* Close the lid. Start charging. */
-	set_lid_open(0);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-
-	/* Open the lid. Transmitter should be turned off. */
-	set_lid_open(1);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	/* Toggle charge done signal. Charging should not start. */
-	gpio_set_level(GPIO_CHARGE_DONE, 1);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_debounce_charge_done(void)
-{
-	/* Lid is open initially. */
-	set_lid_open(1);
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	/* Close the lid. Charging should start. */
-	set_lid_open(0);
-	msleep(START_CHARGE_DELAY + 100);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-
-	/* Within the first second, changes on CHARGE_DONE should be ignore. */
-	gpio_set_level(GPIO_CHARGE_DONE, 1);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-	msleep(100);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-	gpio_set_level(GPIO_CHARGE_DONE, 0);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-	msleep(100);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 1);
-
-	/* Changes on CHARGE_DONE after take effect. */
-	msleep(MONITOR_CHARGE_DONE_DELAY);
-	gpio_set_level(GPIO_CHARGE_DONE, 1);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 1);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	/* Open the lid. Charger should be turned off. */
-	set_lid_open(1);
-	msleep(TEST_CHECK_CHARGE_DELAY);
-	TEST_ASSERT(gpio_get_level(GPIO_BASE_CHG_VDD_EN) == 0);
-	TEST_ASSERT(gpio_get_level(GPIO_CHARGE_EN) == 0);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_lid);
-	RUN_TEST(test_charge_done);
-	RUN_TEST(test_lid_open_during_charging);
-	RUN_TEST(test_debounce_charge_done);
-
-	test_print_result();
-}
diff --git a/test/inductive_charging.tasklist b/test/inductive_charging.tasklist
deleted file mode 100644
index f5c894ccaf..0000000000
--- a/test/inductive_charging.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/interrupt.c b/test/interrupt.c
deleted file mode 100644
index ca98309e1f..0000000000
--- a/test/interrupt.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test interrupt support of EC emulator.
- */
-#include <stdio.h>
-
-#include "common.h"
-#include "console.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int main_count;
-static int has_error;
-static int interrupt_count;
-
-/* period between 50us and 3.2ms */
-#define PERIOD_US(num) (((num % 64) + 1) * 50)
-
-void my_isr(void)
-{
-	int i = main_count;
-	udelay(3 * PERIOD_US(prng_no_seed()));
-	if (i != main_count || !in_interrupt_context())
-		has_error = 1;
-	interrupt_count++;
-}
-
-static volatile uint32_t enable_ready_reg;
-
-static void set_ready_bit(void)
-{
-	if (enable_ready_reg & BIT(0))
-		enable_ready_reg |= BIT(1);
-}
-
-void interrupt_generator(void)
-{
-	while (1) {
-		udelay(3 * PERIOD_US(prng_no_seed()));
-		task_trigger_test_interrupt(my_isr);
-		task_trigger_test_interrupt(set_ready_bit);
-	}
-}
-
-static int interrupt_test(void)
-{
-	timestamp_t deadline = get_time();
-	deadline.val += SECOND / 2;
-	while (!timestamp_expired(deadline, NULL))
-		++main_count;
-
-	ccprintf("Interrupt count: %d\n", interrupt_count);
-	ccprintf("Main thread tick: %d\n", main_count);
-
-	TEST_ASSERT(!has_error);
-	TEST_ASSERT(!in_interrupt_context());
-
-	return EC_SUCCESS;
-}
-
-static int interrupt_disable_test(void)
-{
-	timestamp_t deadline = get_time();
-	int start_int_cnt, end_int_cnt;
-	deadline.val += SECOND / 2;
-
-	interrupt_disable();
-	start_int_cnt = interrupt_count;
-	while (!timestamp_expired(deadline, NULL))
-		;
-	end_int_cnt = interrupt_count;
-	interrupt_enable();
-
-	TEST_ASSERT(start_int_cnt == end_int_cnt);
-
-	return EC_SUCCESS;
-}
-
-static int test_wait_for_ready(void)
-{
-	wait_for_ready(&enable_ready_reg, BIT(0), BIT(1));
-	TEST_EQ(enable_ready_reg, BIT(0) | BIT(1), "%x");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(interrupt_test);
-	RUN_TEST(interrupt_disable_test);
-	RUN_TEST(test_wait_for_ready);
-
-	test_print_result();
-}
diff --git a/test/interrupt.tasklist b/test/interrupt.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/interrupt.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/irq_locking.c b/test/irq_locking.c
deleted file mode 100644
index 6d08b1175d..0000000000
--- a/test/irq_locking.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "task.h"
-#include "test_util.h"
-
-static uint32_t interrupt_disable_count;
-static uint32_t interrupt_enable_count;
-
-/** Mock implementation of interrupt_disable. */
-void interrupt_disable(void)
-{
-	++interrupt_disable_count;
-}
-
-/** Mock implementation of interrupt_enable. */
-void interrupt_enable(void)
-{
-	++interrupt_enable_count;
-}
-
-static int test_simple_lock_unlock(void)
-{
-	uint32_t key = irq_lock();
-
-	irq_unlock(key);
-
-	TEST_EQ(interrupt_disable_count, 1, "%u");
-	TEST_EQ(interrupt_enable_count, 1, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_unlock_when_all_keys_removed(void)
-{
-	uint32_t key0 = irq_lock();
-	uint32_t key1 = irq_lock();
-
-	TEST_EQ(interrupt_disable_count, 2, "%u");
-
-	irq_unlock(key1);
-
-	TEST_EQ(interrupt_enable_count, 0, "%u");
-
-	irq_unlock(key0);
-
-	TEST_EQ(interrupt_enable_count, 1, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_unlock_from_root_key(void)
-{
-	uint32_t key0 = irq_lock();
-	uint32_t key1 = irq_lock();
-
-	TEST_NE(key0, key1, "%u");
-	TEST_EQ(interrupt_disable_count, 2, "%u");
-
-	irq_unlock(key0);
-	TEST_EQ(interrupt_enable_count, 1, "%u");
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	interrupt_disable_count = 0;
-	interrupt_enable_count = 0;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_simple_lock_unlock);
-	RUN_TEST(test_unlock_when_all_keys_removed);
-	RUN_TEST(test_unlock_from_root_key);
-
-	test_print_result();
-}
diff --git a/test/irq_locking.tasklist b/test/irq_locking.tasklist
deleted file mode 100644
index 2d7fbb0541..0000000000
--- a/test/irq_locking.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST /* No test task. */
diff --git a/test/is_enabled.c b/test/is_enabled.c
deleted file mode 100644
index fe93bafc31..0000000000
--- a/test/is_enabled.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test the IS_ENABLED macro.
- */
-#include "common.h"
-#include "test_util.h"
-
-#undef	CONFIG_UNDEFINED
-#define	CONFIG_BLANK
-
-static int test_undef(void)
-{
-	TEST_ASSERT(IS_ENABLED(CONFIG_UNDEFINED) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_blank(void)
-{
-	TEST_ASSERT(IS_ENABLED(CONFIG_BLANK) == 1);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_undef);
-	RUN_TEST(test_blank);
-
-	test_print_result();
-}
diff --git a/test/is_enabled.tasklist b/test/is_enabled.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/is_enabled.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/is_enabled_error.c b/test/is_enabled_error.c
deleted file mode 100644
index 3fcd80afe0..0000000000
--- a/test/is_enabled_error.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test the IS_ENABLED macro fails on unexpected input.
- */
-#include "common.h"
-#include "test_util.h"
-
-#define	CONFIG_VALUE		TEST_VALUE
-
-static int test_invalid_value(void)
-{
-	/* This will cause a compilation error */
-	TEST_ASSERT(IS_ENABLED(CONFIG_VALUE) == 0);
-
-	return EC_ERROR_UNKNOWN;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_invalid_value);
-
-	test_print_result();
-}
diff --git a/test/is_enabled_error.sh b/test/is_enabled_error.sh
deleted file mode 100644
index 1e5407f31f..0000000000
--- a/test/is_enabled_error.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-TEST_DIR="$(dirname "${BASH_SOURCE[0]}")"
-
-TEST_CMD="$(cat "${TEST_DIR}/RO/test/is_enabled_error.o.cmd")"
-
-TEST_ERROR_COUNT=0
-
-for test_value in 0 1 2 A "5 + 5"; do
-	echo -n "Running TEST_VALUE=${test_value}..."
-	TEST_CMD_COMPLETE="${TEST_CMD} \"-DTEST_VALUE=${test_value}\""
-	if BUILD_OUTPUT="$(sh -c "$TEST_CMD_COMPLETE" 2>&1)"; then
-		echo "Fail"
-		echo "Compilation should not have succeeded for" \
-		     "TEST_VALUE=${test_value}"
-		echo "$BUILD_OUTPUT"
-		TEST_ERROR_COUNT=$((TEST_ERROR_COUNT+1))
-		continue
-	fi
-
-	EXPECTED_ERROR="CONFIG_VALUE must be <blank>, or not defined"
-	if grep -q "$EXPECTED_ERROR" <<< "$BUILD_OUTPUT"; then
-		echo "OK"
-	else
-		echo "Fail"
-		echo "Expected to find: $EXPECTED_ERROR"
-		echo "Actual error:"
-		echo "$BUILD_OUTPUT"
-		TEST_ERROR_COUNT=$((TEST_ERROR_COUNT+1))
-	fi
-done
-
-if [[ $TEST_ERROR_COUNT -eq 0 ]]; then
-	echo "Pass!"
-else
-	echo "Fail! (${TEST_ERROR_COUNT} tests)"
-fi
diff --git a/test/is_enabled_error.tasklist b/test/is_enabled_error.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/is_enabled_error.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/kasa.c b/test/kasa.c
deleted file mode 100644
index 3ecd32a556..0000000000
--- a/test/kasa.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "kasa.h"
-#include "test_util.h"
-#include "motion_sense.h"
-#include <stdio.h>
-
-struct motion_sensor_t motion_sensors[] = {};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int test_kasa_reset(void)
-{
-	struct kasa_fit kasa;
-
-	kasa_reset(&kasa);
-
-	TEST_EQ(kasa.nsamples, 0, "%u");
-	TEST_NEAR(kasa.acc_x, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_y, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_z, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_w, 0.0f, 0.000001f, "%f");
-
-	TEST_NEAR(kasa.acc_xx, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_xy, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_xz, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_xw, 0.0f, 0.000001f, "%f");
-
-	TEST_NEAR(kasa.acc_yy, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_yz, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_yw, 0.0f, 0.000001f, "%f");
-
-	TEST_NEAR(kasa.acc_zz, 0.0f, 0.000001f, "%f");
-	TEST_NEAR(kasa.acc_zw, 0.0f, 0.000001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-static int test_kasa_calculate(void)
-{
-	struct kasa_fit kasa;
-	fpv3_t bias;
-	float radius;
-
-	kasa_reset(&kasa);
-	kasa_accumulate(&kasa, 1.01f, 0.01f, 0.01f);
-	kasa_accumulate(&kasa, -0.99f, 0.01f, 0.01f);
-	kasa_accumulate(&kasa, 0.01f, 1.01f, 0.01f);
-	kasa_accumulate(&kasa, 0.01f, -0.99f, 0.01f);
-	kasa_accumulate(&kasa, 0.01f, 0.01f, 1.01f);
-	kasa_accumulate(&kasa, 0.01f, 0.01f, -0.99f);
-	kasa_compute(&kasa, bias, &radius);
-
-	TEST_NEAR(bias[0], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(bias[1], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(bias[2], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(radius, 1.0f, 0.0001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_kasa_reset);
-	RUN_TEST(test_kasa_calculate);
-
-	test_print_result();
-}
diff --git a/test/kasa.tasklist b/test/kasa.tasklist
deleted file mode 100644
index 0e3696c3f0..0000000000
--- a/test/kasa.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/kb_8042.c b/test/kb_8042.c
deleted file mode 100644
index 9705b506fe..0000000000
--- a/test/kb_8042.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests for keyboard MKBP protocol
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "i8042_protocol.h"
-#include "keyboard_8042.h"
-#include "keyboard_protocol.h"
-#include "keyboard_scan.h"
-#include "lpc.h"
-#include "power_button.h"
-#include "system.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static const char *action[2] = {"release", "press"};
-
-#define BUF_SIZE 16
-static char lpc_char_buf[BUF_SIZE];
-static unsigned int lpc_char_cnt;
-
-/*****************************************************************************/
-/* Mock functions */
-
-int lid_is_open(void)
-{
-	return 1;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	lpc_char_buf[lpc_char_cnt++] = chr;
-}
-
-/*****************************************************************************/
-/* Test utilities */
-
-static void press_key(int c, int r, int pressed)
-{
-	ccprintf("Input %s (%d, %d)\n", action[pressed], c, r);
-	keyboard_state_changed(r, c, pressed);
-}
-
-static void enable_keystroke(int enabled)
-{
-	uint8_t data = enabled ? I8042_CMD_ENABLE : I8042_CMD_RESET_DIS;
-	keyboard_host_write(data, 0);
-	msleep(30);
-}
-
-static void reset_8042(void)
-{
-	keyboard_host_write(I8042_CMD_RESET_DEF, 0);
-	msleep(30);
-}
-
-static void set_typematic(uint8_t val)
-{
-	keyboard_host_write(I8042_CMD_SETREP, 0);
-	msleep(30);
-	keyboard_host_write(val, 0);
-	msleep(30);
-}
-
-static void set_scancode(uint8_t s)
-{
-	keyboard_host_write(I8042_CMD_SSCANSET, 0);
-	msleep(30);
-	keyboard_host_write(s, 0);
-	msleep(30);
-}
-
-static void write_cmd_byte(uint8_t val)
-{
-	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
-	msleep(30);
-	keyboard_host_write(val, 0);
-	msleep(30);
-}
-
-static uint8_t read_cmd_byte(void)
-{
-	lpc_char_cnt = 0;
-	keyboard_host_write(I8042_READ_CMD_BYTE, 1);
-	msleep(30);
-	return lpc_char_buf[0];
-}
-
-static int __verify_lpc_char(char *arr, unsigned int sz, int delay_ms)
-{
-	int i;
-
-	lpc_char_cnt = 0;
-	for (i = 0; i < sz; ++i)
-		lpc_char_buf[i] = 0;
-	msleep(delay_ms);
-	TEST_ASSERT_ARRAY_EQ(arr, lpc_char_buf, sz);
-	return EC_SUCCESS;
-}
-
-#define VERIFY_LPC_CHAR(s) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), 30) == EC_SUCCESS)
-#define VERIFY_LPC_CHAR_DELAY(s, t) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), t) == EC_SUCCESS)
-
-static int __verify_no_char(void)
-{
-	lpc_char_cnt = 0;
-	msleep(30);
-	TEST_CHECK(lpc_char_cnt == 0);
-}
-
-#define VERIFY_NO_CHAR() TEST_ASSERT(__verify_no_char() == EC_SUCCESS)
-
-/*****************************************************************************/
-/* Tests */
-
-static int test_single_key_press(void)
-{
-	enable_keystroke(1);
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR("\x01");
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR("\x81");
-
-	press_key(12, 6, 1);
-	VERIFY_LPC_CHAR("\xe0\x4d");
-	press_key(12, 6, 0);
-	VERIFY_LPC_CHAR("\xe0\xcd");
-
-	return EC_SUCCESS;
-}
-
-static int test_disable_keystroke(void)
-{
-	enable_keystroke(0);
-	press_key(1, 1, 1);
-	VERIFY_NO_CHAR();
-	press_key(1, 1, 0);
-	VERIFY_NO_CHAR();
-
-	return EC_SUCCESS;
-}
-
-static int test_typematic(void)
-{
-	enable_keystroke(1);
-
-	/*
-	 * 250ms delay, 8 chars / sec.
-	 */
-	set_typematic(0xf);
-
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01\x01\x01", 650);
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR_DELAY("\x81", 300);
-
-	/*
-	 * 500ms delay, 10.9 chars / sec.
-	 */
-	reset_8042();
-
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01", 650);
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR_DELAY("\x81", 200);
-
-	return EC_SUCCESS;
-}
-
-static int test_scancode_set2(void)
-{
-	set_scancode(2);
-
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR("\x01");
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR("\x81");
-
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR("\x76");
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR("\xf0\x76");
-
-	return EC_SUCCESS;
-}
-
-static int test_power_button(void)
-{
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	set_scancode(1);
-	test_chipset_on();
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
-	VERIFY_LPC_CHAR_DELAY("\xe0\x5e", 100);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	VERIFY_LPC_CHAR_DELAY("\xe0\xde", 100);
-
-	set_scancode(2);
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
-	VERIFY_LPC_CHAR_DELAY("\xe0\x37", 100);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	VERIFY_LPC_CHAR_DELAY("\xe0\xf0\x37", 100);
-
-	test_chipset_off();
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
-	VERIFY_NO_CHAR();
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	VERIFY_NO_CHAR();
-
-	return EC_SUCCESS;
-}
-
-static int test_sysjump(void)
-{
-	set_scancode(2);
-	enable_keystroke(1);
-
-	system_run_image_copy(EC_IMAGE_RW);
-
-	/* Shouldn't reach here */
-	return EC_ERROR_UNKNOWN;
-}
-
-static int test_sysjump_cont(void)
-{
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR("\x01");
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR("\x81");
-
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
-	press_key(1, 1, 1);
-	VERIFY_LPC_CHAR("\x76");
-	press_key(1, 1, 0);
-	VERIFY_LPC_CHAR("\xf0\x76");
-
-	return EC_SUCCESS;
-}
-
-static const struct ec_response_keybd_config keybd_config = {
-	.num_top_row_keys = 13,
-	.action_keys = {
-		TK_BACK,		/* T1 */
-		TK_REFRESH,		/* T2 */
-		TK_FULLSCREEN,		/* T3 */
-		TK_OVERVIEW,		/* T4 */
-		TK_SNAPSHOT,		/* T5 */
-		TK_BRIGHTNESS_DOWN,	/* T6 */
-		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_KBD_BKLIGHT_DOWN,	/* T8 */
-		TK_KBD_BKLIGHT_UP,	/* T9 */
-		TK_PLAY_PAUSE,		/* T10 */
-		TK_VOL_MUTE,		/* T11 */
-		TK_VOL_DOWN,		/* T12 */
-		TK_VOL_UP,		/* T13 */
-	},
-};
-
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
-{
-	return &keybd_config;
-}
-
-static int test_ec_cmd_get_keybd_config(void)
-{
-	struct ec_response_keybd_config resp;
-	int rv;
-
-	rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0,
-				    &resp, sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("Error: EC_CMD_GET_KEYBD_CONFIG cmd returns %d\n", rv);
-		return EC_ERROR_INVAL;
-	}
-
-	if (memcmp(&resp, &keybd_config, sizeof(resp))) {
-		ccprintf("Error: EC_CMD_GET_KEYBD_CONFIG returned bad cfg\n");
-		return EC_ERROR_INVAL;
-	}
-
-	ccprintf("EC_CMD_GET_KEYBD_CONFIG response is good\n");
-	return EC_SUCCESS;
-}
-
-static int test_vivaldi_top_keys(void)
-{
-	set_scancode(2);
-
-	/* Test REFRESH key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(2, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x67");	/* Check REFRESH scancode in set-1 */
-
-	/* Test SNAPSHOT key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(4, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x13");	/* Check SNAPSHOT scancode in set-1 */
-
-	/* Test VOL_UP key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(5, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x30");	/* Check VOL_UP scancode in set-1 */
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-	wait_for_task_started();
-
-	if (system_get_image_copy() == EC_IMAGE_RO) {
-		RUN_TEST(test_single_key_press);
-		RUN_TEST(test_disable_keystroke);
-		RUN_TEST(test_typematic);
-		RUN_TEST(test_scancode_set2);
-		RUN_TEST(test_power_button);
-		RUN_TEST(test_ec_cmd_get_keybd_config);
-		RUN_TEST(test_vivaldi_top_keys);
-		RUN_TEST(test_sysjump);
-	} else {
-		RUN_TEST(test_sysjump_cont);
-	}
-
-	test_print_result();
-}
diff --git a/test/kb_8042.tasklist b/test/kb_8042.tasklist
deleted file mode 100644
index 8cd35e6145..0000000000
--- a/test/kb_8042.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
-	TASK_TEST(KEYSCAN, keyboard_scan_task, NULL, 256) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/kb_mkbp.c b/test/kb_mkbp.c
deleted file mode 100644
index 3b191a47ac..0000000000
--- a/test/kb_mkbp.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests for keyboard MKBP protocol
- */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "host_command.h"
-#include "keyboard_mkbp.h"
-#include "keyboard_protocol.h"
-#include "keyboard_scan.h"
-#include "test_util.h"
-#include "util.h"
-
-static uint8_t state[KEYBOARD_COLS_MAX];
-static int ec_int_level;
-
-static const char *action[2] = {"release", "press"};
-
-/*****************************************************************************/
-/* Mock functions */
-
-void host_send_response(struct host_cmd_handler_args *args)
-{
-	/* Do nothing */
-}
-
-void gpio_set_level(enum gpio_signal signal, int level)
-{
-	if (signal == GPIO_EC_INT_L)
-		ec_int_level = !!level;
-}
-
-int lid_is_open(void)
-{
-	return 1;
-}
-
-/*****************************************************************************/
-/* Test utilities */
-
-#define FIFO_EMPTY()     (ec_int_level == 1)
-#define FIFO_NOT_EMPTY() (ec_int_level == 0)
-
-void clear_state(void)
-{
-	memset(state, 0xff, KEYBOARD_COLS_MAX);
-}
-
-void set_state(int c, int r, int pressed)
-{
-	uint8_t mask = (1 << r);
-
-	if (pressed)
-		state[c] &= ~mask;
-	else
-		state[c] |= mask;
-}
-
-int press_key(int c, int r, int pressed)
-{
-	ccprintf("Input %s (%d, %d)\n", action[pressed], c, r);
-	set_state(c, r, pressed);
-	return mkbp_keyboard_add(state);
-}
-
-int verify_key(int c, int r, int pressed)
-{
-	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event event;
-	int i;
-
-	args.version = 0;
-	args.command = EC_CMD_GET_NEXT_EVENT;
-	args.params = NULL;
-	args.params_size = 0;
-	args.response = &event;
-	args.response_max = sizeof(event);
-	args.response_size = 0;
-
-	if (c >= 0 && r >= 0) {
-		ccprintf("Verify %s (%d, %d)\n", action[pressed], c, r);
-		set_state(c, r, pressed);
-
-		if (host_command_process(&args) != EC_RES_SUCCESS)
-			return 0;
-
-		for (i = 0; i < KEYBOARD_COLS_MAX; ++i)
-			if (event.data.key_matrix[i] != state[i])
-				return 0;
-	} else {
-		ccprintf("Verify no events available\n");
-		if (host_command_process(&args) != EC_RES_UNAVAILABLE)
-			return 0;
-	}
-
-	return 1;
-}
-
-int verify_key_v2(int c, int r, int pressed, int expect_more)
-{
-	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event_v1 event;
-	int i;
-
-	args.version = 2;
-	args.command = EC_CMD_GET_NEXT_EVENT;
-	args.params = NULL;
-	args.params_size = 0;
-	args.response = &event;
-	args.response_max = sizeof(event);
-	args.response_size = 0;
-
-	if (c >= 0 && r >= 0) {
-		ccprintf("Verify %s (%d, %d). Expect %smore.\n",
-			 action[pressed], c, r, expect_more ? "" : "no ");
-		set_state(c, r, pressed);
-
-		if (host_command_process(&args) != EC_RES_SUCCESS)
-			return 0;
-
-		if (!!(event.event_type & EC_MKBP_HAS_MORE_EVENTS) !=
-		    expect_more) {
-			ccprintf("Incorrect more events!\n");
-			return 0;
-		}
-
-		for (i = 0; i < KEYBOARD_COLS_MAX; ++i)
-			if (event.data.key_matrix[i] != state[i])
-				return 0;
-	} else {
-		ccprintf("Verify no events available\n");
-		if (host_command_process(&args) != EC_RES_UNAVAILABLE)
-			return 0;
-	}
-
-	return 1;
-}
-
-int mkbp_config(struct ec_params_mkbp_set_config params)
-{
-	struct host_cmd_handler_args args;
-
-	args.version = 0;
-	args.command = EC_CMD_MKBP_SET_CONFIG;
-	args.params = &params;
-	args.params_size = sizeof(params);
-	args.response = NULL;
-	args.response_max = 0;
-	args.response_size = 0;
-
-	return host_command_process(&args) == EC_RES_SUCCESS;
-}
-
-int set_fifo_size(int sz)
-{
-	struct ec_params_mkbp_set_config params;
-
-	params.config.valid_mask = EC_MKBP_VALID_FIFO_MAX_DEPTH;
-	params.config.valid_flags = 0;
-	params.config.fifo_max_depth = sz;
-
-	return mkbp_config(params);
-}
-
-int set_kb_scan_enabled(int enabled)
-{
-	struct ec_params_mkbp_set_config params;
-
-	params.config.valid_mask = 0;
-	params.config.valid_flags = EC_MKBP_FLAGS_ENABLE;
-	params.config.flags = (enabled ? EC_MKBP_FLAGS_ENABLE : 0);
-
-	return mkbp_config(params);
-}
-
-void clear_mkbp_events(void)
-{
-	struct host_cmd_handler_args args;
-	struct ec_response_get_next_event event;
-
-	args.version = 0;
-	args.command = EC_CMD_GET_NEXT_EVENT;
-	args.params = NULL;
-	args.params_size = 0;
-	args.response = &event;
-	args.response_max = sizeof(event);
-	args.response_size = 0;
-
-	/*
-	 * We should return EC_RES_UNAVAILABLE if there are no MKBP events left.
-	 */
-	while (host_command_process(&args) != EC_RES_UNAVAILABLE)
-		;
-}
-
-/*****************************************************************************/
-/* Tests */
-
-int single_key_press(void)
-{
-	keyboard_clear_buffer();
-	clear_state();
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-	TEST_ASSERT(press_key(0, 0, 0) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-
-	clear_state();
-	TEST_ASSERT(verify_key(0, 0, 1));
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-	TEST_ASSERT(verify_key(0, 0, 0));
-	TEST_ASSERT(FIFO_EMPTY());
-
-	return EC_SUCCESS;
-}
-
-int single_key_press_v2(void)
-{
-	keyboard_clear_buffer();
-	clear_state();
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-	TEST_ASSERT(press_key(0, 0, 0) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-
-	clear_state();
-	TEST_ASSERT(verify_key_v2(0, 0, 1, 1));
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-	TEST_ASSERT(verify_key_v2(0, 0, 0, 0));
-	TEST_ASSERT(FIFO_EMPTY());
-
-	return EC_SUCCESS;
-}
-
-int test_fifo_size(void)
-{
-	keyboard_clear_buffer();
-	clear_state();
-	TEST_ASSERT(set_fifo_size(1));
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-	TEST_ASSERT(press_key(0, 0, 0) == EC_ERROR_OVERFLOW);
-
-	clear_state();
-	TEST_ASSERT(verify_key(0, 0, 1));
-	TEST_ASSERT(FIFO_EMPTY());
-
-	/* Restore FIFO size */
-	TEST_ASSERT(set_fifo_size(100));
-
-	return EC_SUCCESS;
-}
-
-int test_enable(void)
-{
-	keyboard_clear_buffer();
-	clear_state();
-	TEST_ASSERT(set_kb_scan_enabled(0));
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_EMPTY());
-
-	TEST_ASSERT(set_kb_scan_enabled(1));
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-	TEST_ASSERT(FIFO_NOT_EMPTY());
-	TEST_ASSERT(verify_key(0, 0, 1));
-
-	return EC_SUCCESS;
-}
-
-int fifo_underrun(void)
-{
-	keyboard_clear_buffer();
-	clear_state();
-	TEST_ASSERT(press_key(0, 0, 1) == EC_SUCCESS);
-
-	clear_state();
-	TEST_ASSERT(verify_key(0, 0, 1));
-
-	/* When FIFO under run, host command reutns last known state */
-	TEST_ASSERT(verify_key(-1, -1, -1));
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	ec_int_level = 1;
-	test_reset();
-
-	/* Clear any pending events such as lid open. */
-	clear_mkbp_events();
-	RUN_TEST(single_key_press);
-	RUN_TEST(single_key_press_v2);
-	RUN_TEST(test_fifo_size);
-	RUN_TEST(test_enable);
-	RUN_TEST(fifo_underrun);
-
-	test_print_result();
-}
diff --git a/test/kb_mkbp.tasklist b/test/kb_mkbp.tasklist
deleted file mode 100644
index d84996c71c..0000000000
--- a/test/kb_mkbp.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(KEYSCAN, keyboard_scan_task, NULL, 256) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/kb_scan.c b/test/kb_scan.c
deleted file mode 100644
index a43808c0c1..0000000000
--- a/test/kb_scan.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- * Copyright 2013 Google Inc.
- *
- * Tests for keyboard scan deghosting and debouncing.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#define KEYDOWN_DELAY_MS     10
-#define KEYDOWN_RETRY        10
-#define NO_KEYDOWN_DELAY_MS  100
-
-#define CHECK_KEY_COUNT(old, expected) \
-	do { \
-		if (verify_key_presses(old, expected) != EC_SUCCESS) \
-			return EC_ERROR_UNKNOWN; \
-		old = fifo_add_count; \
-	} while (0)
-
-/* Emulated physical key state */
-static uint8_t mock_state[KEYBOARD_COLS_MAX];
-
-/* Snapshot of last known key state */
-static uint8_t key_state[KEYBOARD_COLS_MAX];
-
-/* Counters for key state changes (UP/DOWN) */
-static int key_state_change[KEYBOARD_COLS_MAX][KEYBOARD_ROWS];
-static int total_key_state_change;
-
-static int column_driven;
-static int fifo_add_count;
-static int lid_open;
-#ifdef EMU_BUILD
-static int hibernated;
-static int reset_called;
-#endif
-
-/*
- * Helper method to wake a given task, and provide immediate opportunity to run.
- */
-static void task_wake_then_sleep_1ms(int task_id)
-{
-	task_wake(task_id);
-	msleep(1);
-}
-
-#ifdef CONFIG_LID_SWITCH
-int lid_is_open(void)
-{
-	return lid_open;
-}
-#endif
-
-void keyboard_raw_drive_column(int out)
-{
-	column_driven = out;
-}
-
-int keyboard_raw_read_rows(void)
-{
-	int i;
-	int r = 0;
-
-	if (column_driven == KEYBOARD_COLUMN_NONE) {
-		return 0;
-	} else if (column_driven == KEYBOARD_COLUMN_ALL) {
-		for (i = 0; i < KEYBOARD_COLS_MAX; ++i)
-			r |= mock_state[i];
-		return r;
-	} else {
-		return mock_state[column_driven];
-	}
-}
-
-int mkbp_keyboard_add(const uint8_t *buffp)
-{
-	int c, r;
-
-	fifo_add_count++;
-
-	for (c = 0; c < KEYBOARD_COLS_MAX; c++) {
-		uint8_t diff = key_state[c] ^ buffp[c];
-
-		for (r = 0; r < KEYBOARD_ROWS; r++) {
-			if (diff & BIT(r)) {
-				key_state_change[c][r]++;
-				total_key_state_change++;
-			}
-		}
-	}
-
-	/* Save a snapshot. */
-	memcpy(key_state, buffp, sizeof(key_state));
-
-	return EC_SUCCESS;
-}
-
-#ifdef EMU_BUILD
-void system_hibernate(uint32_t s, uint32_t us)
-{
-	hibernated = 1;
-}
-
-void chipset_reset(void)
-{
-	reset_called = 1;
-}
-#endif
-
-#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_ ## k, \
-					KEYBOARD_COL_ ## k, \
-					p)
-
-#define mock_default_key(k, p) mock_key(KEYBOARD_DEFAULT_ROW_ ## k, \
-					KEYBOARD_DEFAULT_COL_ ## k, \
-					p)
-
-static void mock_key(int r, int c, int keydown)
-{
-	ccprintf("  %s (%d, %d)\n", keydown ? "Pressing" : "Releasing", r, c);
-	if (keydown)
-		mock_state[c] |= (1 << r);
-	else
-		mock_state[c] &= ~(1 << r);
-}
-
-static void reset_key_state(void)
-{
-	memset(mock_state, 0, sizeof(mock_state));
-	memset(key_state, 0, sizeof(key_state));
-	memset(key_state_change, 0, sizeof(key_state_change));
-	task_wake(TASK_ID_KEYSCAN);
-	msleep(NO_KEYDOWN_DELAY_MS);
-	total_key_state_change = 0;
-}
-
-static int expect_keychange(void)
-{
-	int old_count = fifo_add_count;
-	int retry = KEYDOWN_RETRY;
-	task_wake(TASK_ID_KEYSCAN);
-	while (retry--) {
-		msleep(KEYDOWN_DELAY_MS);
-		if (fifo_add_count > old_count)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-static int expect_no_keychange(void)
-{
-	int old_count = fifo_add_count;
-	task_wake(TASK_ID_KEYSCAN);
-	msleep(NO_KEYDOWN_DELAY_MS);
-	return (fifo_add_count == old_count) ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-}
-
-static int host_command_simulate(int r, int c, int keydown)
-{
-	struct ec_params_mkbp_simulate_key params;
-
-	params.col = c;
-	params.row = r;
-	params.pressed = keydown;
-
-	return test_send_host_command(EC_CMD_MKBP_SIMULATE_KEY, 0, &params,
-				      sizeof(params), NULL, 0);
-}
-
-static int verify_key_presses(int old, int expected)
-{
-	int retry = KEYDOWN_RETRY;
-
-	if (expected == 0) {
-		msleep(NO_KEYDOWN_DELAY_MS);
-		return (fifo_add_count == old) ? EC_SUCCESS : EC_ERROR_UNKNOWN;
-	} else {
-		while (retry--) {
-			msleep(KEYDOWN_DELAY_MS);
-			if (fifo_add_count == old + expected)
-				return EC_SUCCESS;
-		}
-		return EC_ERROR_UNKNOWN;
-	}
-}
-
-static int deghost_test(void)
-{
-	reset_key_state();
-
-	/* Test we can detect a keypress */
-	mock_key(1, 1, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 1, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	/* (1, 1) (1, 2) (2, 1) (2, 2) form ghosting keys */
-	mock_key(1, 1, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(2, 2, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 2, 1);
-	mock_key(2, 1, 1);
-	TEST_ASSERT(expect_no_keychange() == EC_SUCCESS);
-	mock_key(2, 1, 0);
-	mock_key(1, 2, 0);
-	TEST_ASSERT(expect_no_keychange() == EC_SUCCESS);
-	mock_key(2, 2, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 1, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	/* (1, 1) (2, 0) (2, 1) don't form ghosting keys */
-	mock_key(1, 1, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(2, 0, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 0, 1);
-	mock_key(2, 1, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 0, 0);
-	mock_key(2, 1, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(2, 0, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 1, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-
-static int strict_debounce_test(void)
-{
-	reset_key_state();
-
-	ccprintf("Test key press & hold.\n");
-	mock_key(1, 1, 1);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 1, "%d");
-	TEST_EQ(total_key_state_change, 1, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test a short stroke.\n");
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_no_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 0, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test ripples being suppressed.\n");
-	/* DOWN */
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 1, "%d");
-	TEST_EQ(total_key_state_change, 1, "%d");
-	/* UP */
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 2, "%d");
-	TEST_EQ(total_key_state_change, 2, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test simultaneous strokes.\n");
-	mock_key(1, 1, 1);
-	mock_key(2, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 1, "%d");
-	TEST_EQ(key_state_change[1][2], 1, "%d");
-	TEST_EQ(total_key_state_change, 2, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test simultaneous strokes in two columns.\n");
-	mock_key(1, 1, 1);
-	mock_key(1, 2, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 1, "%d");
-	TEST_EQ(key_state_change[2][1], 1, "%d");
-	TEST_EQ(total_key_state_change, 2, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test normal & short simultaneous strokes.\n");
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(2, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 0, "%d");
-	TEST_EQ(key_state_change[1][2], 1, "%d");
-	TEST_EQ(total_key_state_change, 1, "%d");
-	ccprintf("Pass.\n");
-
-	reset_key_state();
-
-	ccprintf("Test normal & short simultaneous strokes in two columns.\n");
-	reset_key_state();
-	mock_key(1, 1, 1);
-	task_wake(TASK_ID_KEYSCAN);
-	mock_key(1, 2, 1);
-	task_wake(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake(TASK_ID_KEYSCAN);
-	TEST_EQ(expect_keychange(), EC_SUCCESS, "%d");
-	TEST_EQ(key_state_change[1][1], 0, "%d");
-	TEST_EQ(key_state_change[2][1], 1, "%d");
-	TEST_EQ(total_key_state_change, 1, "%d");
-	ccprintf("Pass.\n");
-
-	return EC_SUCCESS;
-}
-
-static int debounce_test(void)
-{
-	int old_count = fifo_add_count;
-	int i;
-
-	reset_key_state();
-
-	/* One brief keypress is detected. */
-	msleep(40);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 2);
-
-	/* Brief bounce, followed by continuous press is detected as one. */
-	msleep(40);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 1);
-
-	/* Brief lifting, then re-presseing is detected as new keypress. */
-	msleep(40);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 2);
-
-	/* One bouncy re-contact while lifting is ignored. */
-	msleep(40);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	mock_key(1, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 1);
-
-	/*
-	 * Debounce interval of first key is not affected by continued
-	 * activity of other keys.
-	 */
-	msleep(40);
-	/* Push the first key */
-	mock_key(0, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	/*
-	 * Push down each subsequent key, until all 8 are pressed, each
-	 * time bouncing the former one once.
-	 */
-	for (i = 1 ; i < 8; i++) {
-		mock_key(i, 1, 1);
-		task_wake(TASK_ID_KEYSCAN);
-		msleep(3);
-		mock_key(i - 1, 1, 0);
-		task_wake(TASK_ID_KEYSCAN);
-		msleep(1);
-		mock_key(i - 1, 1, 1);
-		task_wake(TASK_ID_KEYSCAN);
-		msleep(1);
-	}
-	/* Verify that the bounces were. ignored */
-	CHECK_KEY_COUNT(old_count, 8);
-	/*
-	 * Now briefly lift and re-press the first one, which should now be past
-	 * its debounce interval
-	 */
-	mock_key(0, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 1);
-	mock_key(0, 1, 1);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-	CHECK_KEY_COUNT(old_count, 1);
-	/* For good measure, release all keys before proceeding. */
-	for (i = 0; i < 8; i++)
-		mock_key(i, 1, 0);
-	task_wake_then_sleep_1ms(TASK_ID_KEYSCAN);
-
-	return EC_SUCCESS;
-}
-
-static int simulate_key_test(void)
-{
-	int old_count;
-
-	reset_key_state();
-
-	task_wake(TASK_ID_KEYSCAN);
-	msleep(40); /* Wait for debouncing to settle */
-
-	old_count = fifo_add_count;
-	host_command_simulate(1, 1, 1);
-	TEST_ASSERT(fifo_add_count > old_count);
-	msleep(40);
-	old_count = fifo_add_count;
-	host_command_simulate(1, 1, 0);
-	TEST_ASSERT(fifo_add_count > old_count);
-	msleep(40);
-
-	return EC_SUCCESS;
-}
-
-#ifdef EMU_BUILD
-static int wait_variable_set(int *var)
-{
-	int retry = KEYDOWN_RETRY;
-	*var = 0;
-	task_wake(TASK_ID_KEYSCAN);
-	while (retry--) {
-		msleep(KEYDOWN_DELAY_MS);
-		if (*var == 1)
-			return EC_SUCCESS;
-	}
-	return EC_ERROR_UNKNOWN;
-}
-
-static int verify_variable_not_set(int *var)
-{
-	*var = 0;
-	task_wake(TASK_ID_KEYSCAN);
-	msleep(NO_KEYDOWN_DELAY_MS);
-	return *var ? EC_ERROR_UNKNOWN : EC_SUCCESS;
-}
-
-static int runtime_key_test(void)
-{
-	reset_key_state();
-
-	/* Alt-VolUp-H triggers system hibernation */
-	mock_defined_key(LEFT_ALT, 1);
-	mock_default_key(VOL_UP, 1);
-	mock_defined_key(KEY_H, 1);
-	TEST_ASSERT(wait_variable_set(&hibernated) == EC_SUCCESS);
-	mock_defined_key(LEFT_ALT, 0);
-	mock_default_key(VOL_UP, 0);
-	mock_defined_key(KEY_H, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	/* Alt-VolUp-R triggers chipset reset */
-	mock_defined_key(RIGHT_ALT, 1);
-	mock_default_key(VOL_UP, 1);
-	mock_defined_key(KEY_R, 1);
-	TEST_ASSERT(wait_variable_set(&reset_called) == EC_SUCCESS);
-	mock_defined_key(RIGHT_ALT, 0);
-	mock_default_key(VOL_UP, 0);
-	mock_defined_key(KEY_R, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	/* Must press exactly 3 keys to trigger runtime keys */
-	mock_defined_key(LEFT_ALT, 1);
-	mock_defined_key(KEY_H, 1);
-	mock_defined_key(KEY_R, 1);
-	mock_default_key(VOL_UP, 1);
-	TEST_ASSERT(verify_variable_not_set(&hibernated) == EC_SUCCESS);
-	TEST_ASSERT(verify_variable_not_set(&reset_called) == EC_SUCCESS);
-	mock_default_key(VOL_UP, 0);
-	mock_defined_key(KEY_R, 0);
-	mock_defined_key(KEY_H, 0);
-	mock_defined_key(LEFT_ALT, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-#endif
-
-#ifdef CONFIG_LID_SWITCH
-static int lid_test(void)
-{
-	reset_key_state();
-
-	msleep(40); /* Allow debounce to settle */
-
-	lid_open = 0;
-	hook_notify(HOOK_LID_CHANGE);
-	msleep(1); /* Allow hooks to run */
-	mock_key(1, 1, 1);
-	TEST_ASSERT(expect_no_keychange() == EC_SUCCESS);
-	mock_key(1, 1, 0);
-	TEST_ASSERT(expect_no_keychange() == EC_SUCCESS);
-
-	lid_open = 1;
-	hook_notify(HOOK_LID_CHANGE);
-	msleep(1); /* Allow hooks to run */
-	mock_key(1, 1, 1);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-	mock_key(1, 1, 0);
-	TEST_ASSERT(expect_keychange() == EC_SUCCESS);
-
-	return EC_SUCCESS;
-}
-#endif
-
-static int test_check_boot_esc(void)
-{
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC);
-}
-
-static int test_check_boot_down(void)
-{
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW);
-}
-
-void test_init(void)
-{
-	uint32_t state;
-
-	system_get_scratchpad(&state);
-
-	if (state & TEST_STATE_MASK(TEST_STATE_STEP_2)) {
-		/* Power-F3-ESC */
-		system_set_reset_flags(system_get_reset_flags() |
-				       EC_RESET_FLAG_RESET_PIN);
-		mock_key(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, 1);
-	} else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3)) {
-		/* Power-F3-Down */
-		system_set_reset_flags(system_get_reset_flags() |
-				       EC_RESET_FLAG_RESET_PIN);
-		mock_key(6, 11, 1);
-	}
-}
-
-static void run_test_step1(void)
-{
-	lid_open = 1;
-	hook_notify(HOOK_LID_CHANGE);
-	test_reset();
-
-	RUN_TEST(deghost_test);
-
-	if (IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
-		RUN_TEST(strict_debounce_test);
-	else
-		RUN_TEST(debounce_test);
-
-	if (0)  /* crbug.com/976974 */
-		RUN_TEST(simulate_key_test);
-#ifdef EMU_BUILD
-	RUN_TEST(runtime_key_test);
-#endif
-#ifdef CONFIG_LID_SWITCH
-	RUN_TEST(lid_test);
-#endif
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_STEP_2);
-}
-
-static void run_test_step2(void)
-{
-	lid_open = 1;
-	hook_notify(HOOK_LID_CHANGE);
-	test_reset();
-
-	RUN_TEST(test_check_boot_esc);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_STEP_3);
-}
-
-static void run_test_step3(void)
-{
-	lid_open = 1;
-	hook_notify(HOOK_LID_CHANGE);
-	test_reset();
-
-	RUN_TEST(test_check_boot_down);
-
-	if (test_get_error_count())
-		test_reboot_to_next_step(TEST_STATE_FAILED);
-	else
-		test_reboot_to_next_step(TEST_STATE_PASSED);
-}
-
-void test_run_step(uint32_t state)
-{
-	if (state & TEST_STATE_MASK(TEST_STATE_STEP_1))
-		run_test_step1();
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_2))
-		run_test_step2();
-	else if (state & TEST_STATE_MASK(TEST_STATE_STEP_3))
-		run_test_step3();
-}
-
-int test_task(void *data)
-{
-	test_run_multistep();
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	msleep(30); /* Wait for TASK_ID_TEST to initialize */
-	task_wake(TASK_ID_TEST);
-}
diff --git a/test/kb_scan.tasklist b/test/kb_scan.tasklist
deleted file mode 100644
index ded03b1112..0000000000
--- a/test/kb_scan.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(KEYSCAN, keyboard_scan_task, NULL, 256) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
-	TASK_TEST(TEST, test_task, NULL, TASK_STACK_SIZE)
diff --git a/test/kb_scan_strict.tasklist b/test/kb_scan_strict.tasklist
deleted file mode 120000
index d4d4fa1efb..0000000000
--- a/test/kb_scan_strict.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-kb_scan.tasklist
\ No newline at end of file
diff --git a/test/key_sequence.txt b/test/key_sequence.txt
deleted file mode 100644
index e9289f4745..0000000000
--- a/test/key_sequence.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-# Key test sequence
-#
-# Format is <beat>[ <keys>]
-#
-# Note that there must be a single space between <beat> and <keys>, if present.
-# The time is in units of beats, where the beat can be selected according to
-# taste. A typical beat value would be 10ms, meaning that the beat counter
-# will move on every 10,000us.
-#
-# The format of keys is a list of ascii characters, or & followed by a numeric
-# ascii value, or * followed by a numeric keycode value. Spaces are ignored
-# (use '*32' for space).
-#
-# Examples:
-# abc      - press a, b and c
-# a &20    - press a and space
-# *58 &13  - press KEY_CAPSLOCK and return (ctrl-m)
-#
-# It is possible for the beat counter to move forward at a variable speed.
-# Provided that keyboard repeat does not occur, this should produce the same
-# result.
-
-test 2-key rollover abc
-expect abc
-# Press a, then b, then release a, then release b
-seq 0
-seq 1 a
-seq 3 ab
-seq 4 abc
-seq 5 b
-seq 8
-seq 9
-endtest
-
-test another
-expect a
-seq 0
-seq 5 a
-seq 10
-endtest
-
-test fast
-expect ab
-seq 0
-seq 10 a
-seq 20 ab
-seq 30 b
-seq 40
-endtest
-
diff --git a/test/legacy_nvmem_dump.h b/test/legacy_nvmem_dump.h
deleted file mode 100644
index 6816673c23..0000000000
--- a/test/legacy_nvmem_dump.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This is a test NVMEM snapshot, it includes a couple of key,value pairs and
- * a set of TPM reserved and evictable objects, as created after the first
- * Chrome OS boot on a device.
- *
- * This binary dump is placed in a separate file not to free up the test file
- * using it.
- */
-	0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f,
-	0x36, 0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff,
-	0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70,
-	0x61, 0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00,
-	0x03, 0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00,
-	0x9b, 0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x5b, 0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3,
-	0xdd, 0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67,
-	0x5c, 0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca,
-	0x7d, 0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec,
-	0x1a, 0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20,
-	0x88, 0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c,
-	0xad, 0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09,
-	0xd1, 0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1,
-	0x66, 0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc,
-	0x1b, 0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d,
-	0x29, 0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32,
-	0x35, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x52, 0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f,
-	0xd3, 0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38,
-	0xc3, 0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd,
-	0x10, 0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7,
-	0xfb, 0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16,
-	0xd5, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
-	0x00, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01,
-	0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff,
-	/* Manually added nonempty pcr. Array 0, index 0 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff,
-	/* Manually added nonempty pcr. Array 1, index 1 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	/* Manually added ram index of size 0x20 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x20, 0x00, 0x00, 0x00, 0x55, 0x55,
-	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
-	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
-	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x69, 0x17, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00,
-	0xc0, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x01, 0x20, 0x04, 0x62, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0xef, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0xc0, 0x01, 0x30, 0x82, 0x03, 0xeb, 0x30, 0x82, 0x02, 0xd3, 0xa0, 0x03,
-	0x02, 0x01, 0x02, 0x02, 0x10, 0x71, 0x7b, 0xc1, 0xfb, 0x3b, 0x21, 0xb5,
-	0xfb, 0x02, 0x21, 0x1f, 0xb7, 0x0a, 0xbc, 0xe4, 0x88, 0x30, 0x0d, 0x06,
-	0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00,
-	0x30, 0x81, 0x80, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06,
-	0x13, 0x02, 0x55, 0x53, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 0x04,
-	0x08, 0x0c, 0x0a, 0x43, 0x61, 0x6c, 0x69, 0x66, 0x6f, 0x72, 0x6e, 0x69,
-	0x61, 0x31, 0x14, 0x30, 0x12, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x0b,
-	0x47, 0x6f, 0x6f, 0x67, 0x6c, 0x65, 0x20, 0x49, 0x6e, 0x63, 0x2e, 0x31,
-	0x24, 0x30, 0x22, 0x06, 0x03, 0x55, 0x04, 0x0b, 0x0c, 0x1b, 0x45, 0x6e,
-	0x67, 0x69, 0x6e, 0x65, 0x65, 0x72, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x6e,
-	0x64, 0x20, 0x44, 0x65, 0x76, 0x65, 0x6c, 0x6f, 0x70, 0x6d, 0x65, 0x6e,
-	0x74, 0x31, 0x20, 0x30, 0x1e, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x17,
-	0x43, 0x52, 0x4f, 0x53, 0x20, 0x54, 0x50, 0x4d, 0x20, 0x50, 0x52, 0x44,
-	0x20, 0x45, 0x4b, 0x20, 0x52, 0x4f, 0x4f, 0x54, 0x20, 0x43, 0x41, 0x30,
-	0x1e, 0x17, 0x0d, 0x31, 0x38, 0x30, 0x37, 0x30, 0x36, 0x30, 0x30, 0x30,
-	0x30, 0x30, 0x32, 0x5a, 0x17, 0x0d, 0x32, 0x38, 0x30, 0x37, 0x30, 0x36,
-	0x30, 0x30, 0x30, 0x30, 0x30, 0x32, 0x5a, 0x30, 0x00, 0x30, 0x82, 0x01,
-	0x22, 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
-	0x01, 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x0f, 0x00, 0x30, 0x82, 0x01,
-	0x0a, 0x02, 0x82, 0x01, 0x01, 0x00, 0xf8, 0x26, 0xde, 0x99, 0xfa, 0x25,
-	0xe1, 0xb6, 0xda, 0xb7, 0x88, 0x74, 0x77, 0x3d, 0x9a, 0x2e, 0xd0, 0xbd,
-	0xda, 0x68, 0x8b, 0x1b, 0x8c, 0xe7, 0xd1, 0x0b, 0xf4, 0xfe, 0x8e, 0x94,
-	0x09, 0x43, 0x11, 0x11, 0x46, 0xfc, 0x16, 0xb5, 0x15, 0x67, 0xab, 0x1b,
-	0x8f, 0x25, 0xa7, 0x28, 0x04, 0xcc, 0xed, 0xf0, 0x5c, 0xbe, 0xa3, 0xfd,
-	0x85, 0x85, 0x9b, 0xea, 0x6c, 0x61, 0x8b, 0x7e, 0xd2, 0x76, 0x2b, 0x37,
-	0x87, 0x30, 0xd3, 0x9f, 0x0d, 0xb7, 0x0e, 0x31, 0x39, 0x3b, 0x3a, 0xa3,
-	0xab, 0xb5, 0x21, 0x15, 0xb2, 0xc6, 0x7e, 0x78, 0xdc, 0x97, 0x53, 0x56,
-	0x3f, 0xe9, 0xb4, 0x4e, 0xb8, 0xdd, 0x09, 0xa6, 0x37, 0xd3, 0xf7, 0x11,
-	0xa2, 0x52, 0x50, 0xa6, 0x53, 0x44, 0xce, 0xb3, 0x9c, 0x02, 0xd8, 0x59,
-	0x04, 0x3b, 0xba, 0x6c, 0xce, 0xf1, 0x6b, 0x33, 0x60, 0x14, 0x6b, 0xa0,
-	0x3d, 0x2e, 0x66, 0x67, 0x82, 0x4f, 0x13, 0xa1, 0x82, 0xc4, 0x15, 0x08,
-	0x7e, 0x59, 0xba, 0x84, 0x3e, 0xac, 0x12, 0x42, 0x98, 0x3d, 0x6e, 0xda,
-	0xa9, 0xc3, 0xd7, 0x45, 0xeb, 0xc8, 0xec, 0x2a, 0x94, 0x9e, 0xc1, 0xf7,
-	0x71, 0xca, 0x3d, 0xb3, 0xd2, 0x68, 0x2a, 0xc0, 0xbe, 0x9e, 0x2f, 0x26,
-	0xf3, 0xf9, 0xb9, 0x7f, 0x21, 0x7f, 0x2f, 0x8b, 0x1b, 0x10, 0xb1, 0x09,
-	0xc8, 0xab, 0xae, 0xda, 0xae, 0x66, 0x07, 0x4a, 0xc0, 0x75, 0x2a, 0x29,
-	0x74, 0xb2, 0x99, 0xa6, 0x58, 0x84, 0xdc, 0x3e, 0x6b, 0x47, 0x37, 0xcb,
-	0xb1, 0xc8, 0xcc, 0x81, 0xb3, 0x8b, 0x3a, 0x0c, 0xd4, 0x6a, 0x11, 0x3f,
-	0x25, 0x17, 0x5d, 0xaf, 0x33, 0x8a, 0x32, 0x9d, 0x93, 0xef, 0xdb, 0x95,
-	0x60, 0x5a, 0x15, 0xc5, 0x20, 0x7a, 0xec, 0xce, 0xa9, 0x31, 0x70, 0x24,
-	0xd1, 0x4d, 0x29, 0xed, 0xeb, 0xec, 0xac, 0x53, 0x19, 0xc3, 0x02, 0x03,
-	0x01, 0x00, 0x01, 0xa3, 0x81, 0xdf, 0x30, 0x81, 0xdc, 0x30, 0x0e, 0x06,
-	0x03, 0x55, 0x1d, 0x0f, 0x01, 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, 0x00,
-	0x20, 0x30, 0x51, 0x06, 0x03, 0x55, 0x1d, 0x11, 0x01, 0x01, 0xff, 0x04,
-	0x47, 0x30, 0x45, 0xa4, 0x43, 0x30, 0x41, 0x31, 0x16, 0x30, 0x14, 0x06,
-	0x05, 0x67, 0x81, 0x05, 0x02, 0x01, 0x0c, 0x0b, 0x69, 0x64, 0x3a, 0x34,
-	0x37, 0x34, 0x46, 0x34, 0x46, 0x34, 0x37, 0x31, 0x0f, 0x30, 0x0d, 0x06,
-	0x05, 0x67, 0x81, 0x05, 0x02, 0x02, 0x0c, 0x04, 0x48, 0x31, 0x42, 0x32,
-	0x31, 0x16, 0x30, 0x14, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x03, 0x0c,
-	0x0b, 0x69, 0x64, 0x3a, 0x30, 0x30, 0x31, 0x33, 0x30, 0x30, 0x33, 0x37,
-	0x30, 0x0c, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04, 0x02,
-	0x30, 0x00, 0x30, 0x13, 0x06, 0x03, 0x55, 0x1d, 0x20, 0x04, 0x0c, 0x30,
-	0x0a, 0x30, 0x08, 0x06, 0x06, 0x67, 0x81, 0x0c, 0x01, 0x02, 0x02, 0x30,
-	0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16, 0x80, 0x14,
-	0x15, 0x39, 0x34, 0xfc, 0x59, 0x19, 0xcd, 0x29, 0x82, 0xf1, 0xf4, 0x7f,
-	0xad, 0x85, 0xd6, 0x44, 0x69, 0xa1, 0xa1, 0x7b, 0x30, 0x10, 0x06, 0x03,
-	0x55, 0x1d, 0x25, 0x04, 0x09, 0x30, 0x07, 0x06, 0x05, 0x67, 0x81, 0x05,
-	0x08, 0x01, 0x30, 0x21, 0x06, 0x03, 0x55, 0x1d, 0x09, 0x04, 0x1a, 0x30,
-	0x18, 0x30, 0x16, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x10, 0x31, 0x0d,
-	0x30, 0x0b, 0x0c, 0x03, 0x32, 0x2e, 0x30, 0x02, 0x01, 0x00, 0x02, 0x01,
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-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0x01, 0x20, 0x00, 0x03, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x04, 0x12, 0x00, 0x76, 0x61, 0x72, 0x31, 0x74, 0x68, 0x69, 0x73, 0x5f,
-	0x69, 0x73, 0x5f, 0x76, 0x61, 0x72, 0x69, 0x61, 0x62, 0x6c, 0x65, 0x5f,
-	0x31, 0x04, 0x12, 0x00, 0x76, 0x61, 0x72, 0x32, 0x74, 0x68, 0x69, 0x73,
-	0x5f, 0x69, 0x73, 0x5f, 0x76, 0x61, 0x72, 0x69, 0x61, 0x62, 0x6c, 0x65,
-	0x5f, 0x32, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/test/lid_sw.c b/test/lid_sw.c
deleted file mode 100644
index 8163f74716..0000000000
--- a/test/lid_sw.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test lid switch.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "lid_switch.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int lid_hook_count;
-
-static void lid_change_hook(void)
-{
-	lid_hook_count++;
-}
-DECLARE_HOOK(HOOK_LID_CHANGE, lid_change_hook, HOOK_PRIO_DEFAULT);
-
-int lid_memmap_state(void)
-{
-	uint8_t *memmap = host_get_memmap(EC_MEMMAP_SWITCHES);
-	return *memmap & EC_SWITCH_LID_OPEN;
-}
-
-static int test_hook(void)
-{
-	/* Close lid for testing */
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(100);
-	lid_hook_count = 0;
-	host_clear_events(0xffffffff);
-
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(50);
-	TEST_ASSERT(lid_hook_count == 1);
-	TEST_ASSERT(lid_is_open());
-	TEST_ASSERT(lid_memmap_state());
-	TEST_ASSERT(host_get_events() &
-		    EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
-
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(50);
-	TEST_ASSERT(lid_hook_count == 2);
-	TEST_ASSERT(!lid_is_open());
-	TEST_ASSERT(!lid_memmap_state());
-	TEST_ASSERT(host_get_events() &
-		    EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED));
-
-	return EC_SUCCESS;
-}
-
-static int test_debounce(void)
-{
-	/* Close lid for testing */
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(100);
-	lid_hook_count = 0;
-	host_clear_events(0xffffffff);
-
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(20);
-	TEST_ASSERT(lid_hook_count == 0);
-	TEST_ASSERT(!lid_is_open());
-	TEST_ASSERT(!lid_memmap_state());
-	TEST_ASSERT(!(host_get_events() &
-		      EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)));
-
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(50);
-	TEST_ASSERT(lid_hook_count == 0);
-	TEST_ASSERT(!lid_is_open());
-	TEST_ASSERT(!lid_memmap_state());
-	TEST_ASSERT(!(host_get_events() &
-		      EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)));
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_hook);
-	RUN_TEST(test_debounce);
-
-	test_print_result();
-}
diff --git a/test/lid_sw.tasklist b/test/lid_sw.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/lid_sw.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/lightbar.c b/test/lightbar.c
deleted file mode 100644
index 363d73a36b..0000000000
--- a/test/lightbar.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "lightbar.h"
-#include "host_command.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int get_seq(void)
-{
-	int rv;
-	struct ec_params_lightbar params;
-	struct ec_response_lightbar resp;
-
-	/* Get the state */
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = LIGHTBAR_CMD_GET_SEQ;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
-		return -1;
-	}
-
-	return resp.get_seq.num;
-}
-
-static int set_seq(int s)
-{
-	int rv;
-	struct ec_params_lightbar params;
-	struct ec_response_lightbar resp;
-
-	/* Get the state */
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = LIGHTBAR_CMD_SEQ;
-	params.seq.num = s;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	if (rv != EC_RES_SUCCESS) {
-		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
-		return -1;
-	}
-
-	return EC_RES_SUCCESS;
-}
-
-test_static int test_double_oneshots(void)
-{
-	/* Start in S0 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-	/* Invoke the oneshot */
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	/* Switch to a different oneshot while that one's running */
-	TEST_ASSERT(set_seq(LIGHTBAR_KONAMI) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_KONAMI);
-	/* Afterwards, it should go back to the original normal state */
-	usleep(30 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-
-	/* Same test, but with a bunch more oneshots. */
-	TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	TEST_ASSERT(set_seq(LIGHTBAR_KONAMI) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_KONAMI);
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	TEST_ASSERT(set_seq(LIGHTBAR_KONAMI) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_KONAMI);
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	/* It should still go back to the original normal state */
-	usleep(30 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-
-	/* But if the interruption is a normal state, that should stick. */
-	TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	TEST_ASSERT(set_seq(LIGHTBAR_KONAMI) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_KONAMI);
-	/* Here's a normal sequence */
-	TEST_ASSERT(set_seq(LIGHTBAR_S3) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-	/* And another one-shot */
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	TEST_ASSERT(set_seq(LIGHTBAR_KONAMI) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_KONAMI);
-	TEST_ASSERT(set_seq(LIGHTBAR_TAP) == EC_RES_SUCCESS);
-	usleep(SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_TAP);
-	/* It should go back to the new normal sequence */
-	usleep(30 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_oneshots_norm_msg(void)
-{
-	/* Revert to the next state when interrupted with a normal message. */
-	enum lightbar_sequence seqs[] = {
-		LIGHTBAR_KONAMI,
-		LIGHTBAR_TAP,
-	};
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(seqs); i++) {
-		/* Start in S0 */
-		TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		/* Invoke the oneshot */
-		TEST_ASSERT(set_seq(seqs[i]) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		/* Interrupt with S0S3 */
-		TEST_ASSERT(set_seq(LIGHTBAR_S0S3) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		/* It should be back right away */
-		TEST_ASSERT(get_seq() == LIGHTBAR_S0S3);
-		/* And transition on to the correct value */
-		usleep(30 * SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_stop_timeout(void)
-{
-	int i;
-
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++) {
-		/* Start in S0 */
-		TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		/* Tell it to stop */
-		TEST_ASSERT(set_seq(LIGHTBAR_STOP) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_STOP);
-		/* Try to interrupt it */
-		TEST_ASSERT(set_seq(i) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		/* What happened? */
-		if (i == LIGHTBAR_RUN ||
-		    i == LIGHTBAR_S0S3 || i ==  LIGHTBAR_S3 ||
-		    i ==  LIGHTBAR_S3S5 || i ==  LIGHTBAR_S5)
-			/* RUN or shutdown sequences should stop it */
-			TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-		else
-			/* All other sequences should be ignored */
-			TEST_ASSERT(get_seq() == LIGHTBAR_STOP);
-
-		/* Let it RUN again for the next iteration */
-		TEST_ASSERT(set_seq(LIGHTBAR_RUN) == EC_RES_SUCCESS);
-		usleep(SECOND);
-	}
-
-	TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-	return EC_SUCCESS;
-}
-
-test_static int test_oneshots_timeout(void)
-{
-	/* These should revert to the previous state after running */
-	enum lightbar_sequence seqs[] = {
-		LIGHTBAR_RUN,
-		LIGHTBAR_KONAMI,
-		LIGHTBAR_TAP,
-	};
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(seqs); i++) {
-		TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-		usleep(SECOND);
-		TEST_ASSERT(set_seq(seqs[i]) == EC_RES_SUCCESS);
-		/* Assume the oneshot sequence takes at least a second (except
-		 * for LIGHTBAR_RUN, which returns immediately) */
-		if (seqs[i] != LIGHTBAR_RUN) {
-			usleep(SECOND);
-			TEST_ASSERT(get_seq() == seqs[i]);
-		}
-		usleep(30 * SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_transition_states(void)
-{
-	/* S5S3 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S5S3) == EC_RES_SUCCESS);
-	usleep(10 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-
-	/* S3S0 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S3S0) == EC_RES_SUCCESS);
-	usleep(10 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-
-	/* S0S3 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S0S3) == EC_RES_SUCCESS);
-	usleep(10 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-
-	/* S3S5 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S3S5) == EC_RES_SUCCESS);
-	usleep(10 * SECOND);
-	TEST_ASSERT(get_seq() == LIGHTBAR_S5);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_stable_states(void)
-{
-	int i;
-
-	/* Wait for the lightbar task to initialize */
-	msleep(500);
-
-	/* It should come up in S5 */
-	TEST_ASSERT(get_seq() == LIGHTBAR_S5);
-
-	/* It should stay there */
-	for (i = 0; i < 30; i++) {
-		usleep(SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_S5);
-	}
-
-	/* S3 is sticky, too */
-	TEST_ASSERT(set_seq(LIGHTBAR_S3) == EC_RES_SUCCESS);
-	for (i = 0; i < 30; i++) {
-		usleep(SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_S3);
-	}
-
-	/* And S0 */
-	TEST_ASSERT(set_seq(LIGHTBAR_S0) == EC_RES_SUCCESS);
-	for (i = 0; i < 30; i++) {
-		usleep(SECOND);
-		TEST_ASSERT(get_seq() == LIGHTBAR_S0);
-	}
-
-	return EC_SUCCESS;
-}
-
-const struct lb_brightness_def lb_brightness_levels[] = {
-	{
-		/* regular brightness */
-		.lux_up = 60,
-		.lux_down = 40,
-	},
-	{
-		/* 25 - 50% brightness */
-		.lux_up = 40,
-		.lux_down = 20,
-	},
-	{
-		/* 0 .. 25% brightness */
-		.lux_up = 0,
-		.lux_down = 0,
-	},
-};
-const unsigned int lb_brightness_levels_count =
-		ARRAY_SIZE(lb_brightness_levels);
-
-int lux_level_to_google_color(const int lux);
-extern int google_color_id;
-
-int lid_is_open(void)
-{
-	return 1;
-}
-
-test_static int test_als_lightbar(void)
-{
-	int lux_data[] = { 500, 100, 35, 15, 30, 35, 55, 70, 55, 100 };
-	int exp_gcid[] = {   0,   0,  1,  2,  2,  2,  1,  0,  0,   0 };
-	int exp_chg[]  = {   0,   0,  1,  1,  0,  0,  1,  1,  0,   0 };
-	int i;
-
-	BUILD_ASSERT(ARRAY_SIZE(lux_data) == ARRAY_SIZE(exp_gcid));
-	BUILD_ASSERT(ARRAY_SIZE(lux_data) == ARRAY_SIZE(exp_chg));
-
-	google_color_id = 0;
-	for (i = 0; i < ARRAY_SIZE(lux_data); i++) {
-		TEST_ASSERT(exp_chg[i] ==
-			    lux_level_to_google_color(lux_data[i]));
-		TEST_ASSERT(exp_gcid[i] == google_color_id);
-	}
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	/* Ensure tasks are started before running tests */
-	usleep(SECOND);
-
-	RUN_TEST(test_stable_states);
-	RUN_TEST(test_transition_states);
-	RUN_TEST(test_oneshots_timeout);
-	RUN_TEST(test_stop_timeout);
-	RUN_TEST(test_oneshots_norm_msg);
-	RUN_TEST(test_double_oneshots);
-	RUN_TEST(test_als_lightbar);
-	test_print_result();
-}
diff --git a/test/lightbar.tasklist b/test/lightbar.tasklist
deleted file mode 100644
index b5e714765d..0000000000
--- a/test/lightbar.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-        TASK_TEST(LIGHTBAR, lightbar_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/mag_cal.c b/test/mag_cal.c
deleted file mode 100644
index 8ee3b41480..0000000000
--- a/test/mag_cal.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "mag_cal.h"
-#include "test_util.h"
-#include <stdio.h>
-
-/**
- * Various samples that might be seen in the wild. Normal range for magnetic
- * fields is around 80 uT. This translates to roughly +/-525 units for the
- * lis2mdl sensor.
- *
- * Random numbers were generated using the range of [518,532] (+- 2.14 uT) for
- * the high values and [-5,5] (+- 1.53 uT) for the low values.
- */
-static intv3_t samples[] = {
-	{ -522, 5, -5 },
-	{ -528, -3, 1 },
-	{ -531, -2, 0 },
-	{ -525, -1, 3 },
-
-	{ 527, 3, -2 },
-	{ 523, -5, 1 },
-	{ 520, -3, 2 },
-	{ 522, 0, -4 },
-
-	{ -3, -519, -2 },
-	{ 1, -521, 5 },
-	{ 2, -526, 4 },
-	{ 0, -532, -5 },
-
-	{ -5, 528, 4 },
-	{ -2, 531, -4 },
-	{ 1, 522, 2 },
-	{ 5, 532, 3 },
-
-	{ -5, 0, -524 },
-	{ -1, -2, -527 },
-	{ -3, 4, -532 },
-	{ 5, 3, -531 },
-
-	{ 4, -2, 524 },
-	{ 1, 3, 520 },
-	{ 5, -5, 528 },
-	{ 0, 2, 521 },
-};
-
-static int test_mag_cal_computes_bias(void)
-{
-	struct mag_cal_t cal;
-	int i;
-
-	init_mag_cal(&cal);
-	cal.batch_size = ARRAY_SIZE(samples);
-
-	/* Test that we don't calibrate until we added the final sample. */
-	for (i = 0; i < cal.batch_size - 1; ++i)
-		TEST_EQ(0, mag_cal_update(&cal, samples[i]), "%d");
-	/* Add the final sample and check calibration. */
-	TEST_EQ(1, mag_cal_update(&cal, samples[cal.batch_size - 1]), "%d");
-	TEST_EQ(525, FP_TO_INT(cal.radius), "%d");
-	TEST_EQ(1, cal.bias[0], "%d");
-	TEST_EQ(-1, cal.bias[1], "%d");
-	TEST_EQ(2, cal.bias[2], "%d");
-
-	/*
-	 * State should have reset, run the same code again to verify that
-	 * we get the same calibration.
-	 */
-	for (i = 0; i < cal.batch_size - 1; ++i)
-		TEST_EQ(0, mag_cal_update(&cal, samples[i]), "%d");
-	TEST_EQ(1, mag_cal_update(&cal, samples[cal.batch_size - 1]), "%d");
-	TEST_EQ(525, FP_TO_INT(cal.radius), "%d");
-	TEST_EQ(1, cal.bias[0], "%d");
-	TEST_EQ(-1, cal.bias[1], "%d");
-	TEST_EQ(2, cal.bias[2], "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_mag_cal_computes_bias);
-
-	test_print_result();
-}
diff --git a/test/mag_cal.tasklist b/test/mag_cal.tasklist
deleted file mode 100644
index ff715f69cd..0000000000
--- a/test/mag_cal.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
-
diff --git a/test/math_util.c b/test/math_util.c
deleted file mode 100644
index 6482888e55..0000000000
--- a/test/math_util.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test motion sense code.
- */
-
-#include <math.h>
-#include <stdio.h>
-#include "common.h"
-#include "math_util.h"
-#include "motion_sense.h"
-#include "test_util.h"
-#include "util.h"
-
-/*****************************************************************************/
-/*
- * Need to define motion sensor globals just to compile.
- * We include motion task to force the inclusion of math_util.c
- */
-struct motion_sensor_t motion_sensors[] = {};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*****************************************************************************/
-/* Test utilities */
-
-/* Macro to compare two floats and check if they are equal within diff. */
-#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b) - diff) && (a) <= ((b) + diff))
-
-#define ACOS_TOLERANCE_DEG 0.5f
-#define RAD_TO_DEG (180.0f / 3.1415926f)
-
-static int test_acos(void)
-{
-	float a, b;
-	float test;
-
-	/* Test a handful of values. */
-	for (test = -1.0; test <= 1.0; test += 0.01) {
-		a = FP_TO_FLOAT(arc_cos(FLOAT_TO_FP(test)));
-		b = acos(test) * RAD_TO_DEG;
-		TEST_ASSERT(IS_FLOAT_EQUAL(a, b, ACOS_TOLERANCE_DEG));
-	}
-
-	return EC_SUCCESS;
-}
-
-
-const mat33_fp_t test_matrices[] = {
-	{{ 0, FLOAT_TO_FP(-1), 0},
-	 {FLOAT_TO_FP(-1), 0, 0},
-	 { 0, 0, FLOAT_TO_FP(1)} },
-	{{ FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5)},
-	 { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6)},
-	 { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0} }
-};
-
-
-static int test_rotate(void)
-{
-	int i, j, k;
-	intv3_t v = {1, 2, 3};
-	intv3_t w;
-
-	for (i = 0; i < ARRAY_SIZE(test_matrices); i++) {
-		for (j = 0; j < 100; j += 10) {
-			for (k = X; k <= Z; k++) {
-				v[k] += j;
-				v[k] %= 7;
-			}
-
-			rotate(v, test_matrices[i], w);
-			rotate_inv(w, test_matrices[i], w);
-			for (k = X; k <= Z; k++)
-				TEST_ASSERT(v[k] == w[k]);
-		}
-	}
-	return EC_SUCCESS;
-}
-
-test_static int test_round_divide(void)
-{
-	/* Check function version */
-	TEST_EQ(round_divide(10, 1), 10, "%d");
-	TEST_EQ(round_divide(10, 2), 5, "%d");
-	TEST_EQ(round_divide(10, 3), 3, "%d");
-	TEST_EQ(round_divide(10, 4), 3, "%d");
-	TEST_EQ(round_divide(10, 5), 2, "%d");
-	TEST_EQ(round_divide(10, 6), 2, "%d");
-	TEST_EQ(round_divide(10, 7), 1, "%d");
-	TEST_EQ(round_divide(10, 9), 1, "%d");
-	TEST_EQ(round_divide(10, 10), 1, "%d");
-	TEST_EQ(round_divide(10, 11), 1, "%d");
-	TEST_EQ(round_divide(10, 20), 1, "%d");
-	TEST_EQ(round_divide(10, 21), 0, "%d");
-
-	/* Check negative conditions */
-	TEST_EQ(round_divide(-10, 6), -2, "%d");
-	TEST_EQ(round_divide(10, -6), -2, "%d");
-	TEST_EQ(round_divide(-10, -6), 2, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_temp_conversion(void)
-{
-	TEST_EQ(C_TO_K(100), 373, "%d");
-	TEST_EQ(K_TO_C(100), -173, "%d");
-
-	TEST_EQ((int)CELSIUS_TO_DECI_KELVIN(100), 3732, "%d");
-	TEST_EQ(DECI_KELVIN_TO_CELSIUS(100), -263, "%d");
-
-	TEST_EQ(MILLI_KELVIN_TO_MILLI_CELSIUS(100), -273050, "%d");
-	TEST_EQ(MILLI_CELSIUS_TO_MILLI_KELVIN(100), 273250, "%d");
-
-	TEST_EQ(MILLI_KELVIN_TO_KELVIN(5000), 5, "%d");
-	TEST_EQ(KELVIN_TO_MILLI_KELVIN(100), 100000, "%d");
-
-	TEST_EQ(CELSIUS_TO_MILLI_KELVIN(100), 373150, "%d");
-	TEST_EQ(MILLI_KELVIN_TO_CELSIUS(100), -273, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_acos);
-	RUN_TEST(test_rotate);
-	RUN_TEST(test_round_divide);
-	RUN_TEST(test_temp_conversion);
-
-	test_print_result();
-}
diff --git a/test/math_util.tasklist b/test/math_util.tasklist
deleted file mode 100644
index f5c894ccaf..0000000000
--- a/test/math_util.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/motion_angle.c b/test/motion_angle.c
deleted file mode 100644
index 30f663de14..0000000000
--- a/test/motion_angle.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test motion sense code: Check lid angle calculation and tablet mode
- * transition.
- */
-
-#include <math.h>
-#include <stdio.h>
-
-#include "accelgyro.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "motion_common.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "tablet_mode.h"
-#include "test_util.h"
-#include "util.h"
-
-/*****************************************************************************/
-/* Test utilities */
-
-/* Array units is in m/s^2 - old matrix format. */
-int filler(const struct motion_sensor_t *s, const float v)
-{
-	return (v * MOTION_SCALING_FACTOR) / s->current_range;
-}
-
-static int test_lid_angle_less180(void)
-{
-	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
-
-	/* We don't have TASK_CHIP so simulate init ourselves */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
-	TEST_ASSERT(lid->drv->get_data_rate(lid) == 0);
-
-	/* Go to S0 state */
-	hook_notify(HOOK_CHIPSET_SUSPEND);
-	hook_notify(HOOK_CHIPSET_RESUME);
-	msleep(1000);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S0);
-	TEST_ASSERT(lid->drv->get_data_rate(lid) == TEST_LID_FREQUENCY);
-
-	/* Open lid, testing close to 180 degree. */
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(1000);
-
-	cprints(CC_ACCEL, "start loop");
-	/* Check we will never enter tablet mode. */
-	while (index < kAccelerometerLaptopModeTestDataLength) {
-		feed_accel_data(kAccelerometerLaptopModeTestData,
-				&index, filler);
-		wait_for_valid_sample();
-		lid_angle = motion_lid_get_angle();
-		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
-		/* We need few sample to debounce and enter laptop mode. */
-		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
-			    !tablet_get_mode());
-	}
-
-	/* Check we will never exit tablet mode. */
-	index = 0;
-	while (index < kAccelerometerFullyOpenTestDataLength) {
-		feed_accel_data(kAccelerometerFullyOpenTestData,
-				&index, filler);
-		wait_for_valid_sample();
-		lid_angle = motion_lid_get_angle();
-		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
-		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
-			    tablet_get_mode());
-	}
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_lid_angle_less180);
-
-	test_print_result();
-}
diff --git a/test/motion_angle.tasklist b/test/motion_angle.tasklist
deleted file mode 100644
index 0b774ebb4a..0000000000
--- a/test/motion_angle.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  \
-  TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/motion_angle_data_literals.c b/test/motion_angle_data_literals.c
deleted file mode 100644
index 6c0fcb35c2..0000000000
--- a/test/motion_angle_data_literals.c
+++ /dev/null
@@ -1,1003 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "util.h"
-
-/*
- * Recopied from
- * chromium/src/ash/wm/tablet_mode/accelerometer_test_data_literals.cc
- *
- * The arrays contain actual accelerator readings.
- * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ]
- */
-const float kAccelerometerLaptopModeTestData[] = {
-    -0.166016f,   -0.00488281f,  0.924805f,     -0.770508f,    -0.0488281f,
-    -0.510742f,   -0.199219f,    -0.0078125f,   0.953125f,     -0.782227f,
-    -0.0244141f,  -0.652344f,    -0.177734f,    -0.0136719f,   0.936523f,
-    -0.772461f,   -0.0527344f,   -0.59375f,     -0.176758f,    -0.00878906f,
-    0.9375f,      -0.777344f,    -0.0419922f,   -0.637695f,    -0.165039f,
-    -0.00878906f, 0.942383f,     -0.782227f,    -0.046875f,    -0.613281f,
-    -0.180664f,   -0.00976562f,  0.943359f,     -0.777344f,    -0.0419922f,
-    -0.601562f,   -0.189453f,    -0.00488281f,  0.943359f,     -0.776367f,
-    -0.0263672f,  -0.613281f,    -0.166992f,    -0.00488281f,  0.935547f,
-    -0.78125f,    -0.0380859f,   -0.609375f,    -0.176758f,    -0.00878906f,
-    0.947266f,    -0.790039f,    -0.0576172f,   -0.585938f,    -0.173828f,
-    -0.0126953f,  0.93457f,      -0.780273f,    -0.0654297f,   -0.666016f,
-    -0.169922f,   -0.00195312f,  0.928711f,     -0.775391f,    -0.0351562f,
-    -0.561523f,   -0.193359f,    0.0f,          0.941406f,     -0.795898f,
-    -0.0478516f,  -0.640625f,    -0.162109f,    -0.00585938f,  0.917969f,
-    -0.768555f,   -0.0146484f,   -0.685547f,    -0.166992f,    -0.0136719f,
-    0.921875f,    -0.755859f,    -0.0166016f,   -0.425781f,    -0.175781f,
-    -0.0810547f,  1.00098f,      -0.802734f,    -0.117188f,    -0.585938f,
-    -0.210938f,   0.0214844f,    0.881836f,     -0.750977f,    -0.0302734f,
-    -0.677734f,   -0.285156f,    0.00976562f,   0.967773f,     -0.763672f,
-    -0.0283203f,  -0.850586f,    -0.222656f,    -0.0136719f,   0.943359f,
-    -0.763672f,   -0.0507812f,   -0.640625f,    -0.236328f,    0.0859375f,
-    0.892578f,    -0.742188f,    0.0302734f,    -0.484375f,    -0.269531f,
-    0.0263672f,   0.913086f,     -0.714844f,    -0.00585938f,  -0.745117f,
-    -0.275391f,   0.0927734f,    0.977539f,     -0.776367f,    -0.078125f,
-    -0.750977f,   -0.155273f,    -0.0341797f,   1.2334f,       -1.06445f,
-    -0.0478516f,  -0.823242f,    -0.196289f,    0.046875f,     1.19141f,
-    -1.00391f,    -0.140625f,    -0.541016f,    0.0917969f,    0.21582f,
-    0.717773f,    -0.764648f,    -0.0341797f,   -0.607422f,    -0.0351562f,
-    0.0888672f,   0.207031f,     -0.214844f,    -0.18457f,     -0.0664062f,
-    -0.0898438f,  0.0556641f,    0.418945f,     -0.232422f,    0.43457f,
-    0.0361328f,   0.143555f,     0.376953f,     1.23633f,      -1.09082f,
-    0.529297f,    0.0507812f,    0.205078f,     0.438477f,     1.66602f,
-    -1.59668f,    0.325195f,     -1.20996f,     -0.0791016f,   0.404297f,
-    1.50977f,     -1.40918f,     0.31543f,      -1.30273f,     -0.0654297f,
-    0.141602f,    0.699219f,     -0.589844f,    0.0732422f,    -0.27832f,
-    0.00488281f,  0.00683594f,   0.0566406f,    -0.0410156f,   -0.0292969f,
-    -0.0234375f,  -0.0488281f,   -0.00195312f,  -0.0292969f,   0.0849609f,
-    -0.139648f,   0.0585938f,    0.677734f,     0.667969f,     1.36523f,
-    -1.11816f,    0.412109f,     0.844727f,     0.142578f,     0.790039f,
-    1.73145f,     -1.68066f,     0.464844f,     -1.29492f,     -0.0800781f,
-    0.803711f,    0.879883f,     -0.765625f,    -0.0400391f,   -0.616211f,
-    -0.170898f,   0.879883f,     0.510742f,     0.158203f,     0.381836f,
-    -0.270508f,   -0.0693359f,   0.651367f,     0.431641f,     0.104492f,
-    0.991211f,    -0.0634766f,   -0.0478516f,   0.750977f,     0.283203f,
-    -0.0332031f,  1.52051f,      -0.00195312f,  -0.201172f,    1.08984f,
-    0.173828f,    0.0849609f,    1.44141f,      -0.214844f,    -0.0107422f,
-    1.29785f,     0.520508f,     0.00488281f,   1.73047f,      -0.523438f,
-    0.136719f,    1.42188f,      0.987305f,     0.0527344f,    1.74707f,
-    -0.525391f,   0.34668f,      0.469727f,     0.428711f,     0.114258f,
-    -0.788086f,   0.177734f,     0.400391f,     -0.106445f,    0.328125f,
-    -0.566406f,   -0.948242f,    0.670898f,     0.467773f,     -0.21875f,
-    0.55957f,     -0.767578f,    -0.232422f,    0.195312f,     0.625f,
-    -0.271484f,   0.865234f,     -0.765625f,    0.299805f,     0.0703125f,
-    0.378906f,    -0.526367f,    0.548828f,     -0.231445f,    -0.569336f,
-    0.455078f,    0.303711f,     -0.866211f,    -0.485352f,    0.566406f,
-    -1.60547f,    0.481445f,     0.183594f,     -0.782227f,    -0.260742f,
-    0.243164f,    -1.41504f,     0.373047f,     0.172852f,     -0.935547f,
-    -0.412109f,   0.133789f,     -1.69727f,     0.178711f,     0.407227f,
-    -0.952148f,   -0.227539f,    0.0751953f,    -1.67188f,     0.339844f,
-    0.498047f,    -0.795898f,    0.209961f,     0.177734f,     -1.3916f,
-    0.458984f,    0.295898f,     0.0390625f,    0.697266f,     0.258789f,
-    -0.0703125f,  -0.131836f,    0.56543f,      0.250977f,     0.913086f,
-    -0.353516f,   0.90332f,      0.191406f,     0.708008f,     0.352539f,
-    0.853516f,    -0.839844f,    0.955078f,     0.636719f,     0.657227f,
-    0.389648f,    0.620117f,     -0.725586f,    0.43457f,      0.485352f,
-    0.424805f,    0.479492f,     0.287109f,     -0.505859f,    -0.209961f,
-    0.0927734f,   0.21582f,      0.709961f,     0.492188f,     -0.413086f,
-    -0.0869141f,  0.0673828f,    -0.119141f,    1.20508f,      0.392578f,
-    0.229492f,    0.927734f,     -0.297852f,    0.142578f,     1.0293f,
-    0.430664f,    0.0449219f,    1.71875f,      -0.0283203f,   0.0107422f,
-    1.18164f,     0.0517578f,    0.0751953f,    1.80273f,      -0.0693359f,
-    -0.19043f,    1.1748f,       0.236328f,     0.0839844f,    1.78711f,
-    -0.472656f,   -0.270508f,    1.10254f,      0.964844f,     0.118164f,
-    1.75684f,     -0.901367f,    -0.211914f,    1.11133f,      0.65625f,
-    0.308594f,    0.142578f,     0.396484f,     0.239258f,     0.0800781f,
-    0.973633f,    -0.824219f,    -0.25293f,     0.485352f,     0.351562f,
-    -0.0771484f,  1.08984f,      -0.632812f,    0.240234f,     -0.258789f,
-    0.436523f,    -0.514648f,    0.491211f,     0.0664062f,    -0.244141f,
-    -0.148438f,   -0.171875f,    -0.477539f,    -0.459961f,    1.1084f,
-    -0.822266f,   -0.114258f,    -0.192383f,    -0.608398f,    -0.771484f,
-    1.11133f,     -1.25488f,     1.01953f,      -0.0839844f,   -0.620117f,
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-    2.0f,         -1.99902f,     0.226562f,     1.01465f,      0.669922f,
-    -0.373047f,   1.71484f,      1.99707f,      -0.0654297f,   1.00391f,
-    0.330078f,    -0.432617f,    0.704102f,     -0.96875f,     0.0800781f,
-    0.964844f,    0.702148f,     -0.5625f,      1.39746f,      -0.203125f,
-    0.255859f,    1.74512f,      1.52539f,      0.417969f,     2.0f,
-    -0.0976562f,  -0.482422f,    0.09375f,      0.151367f,     -0.328125f,
-    -1.88867f,    -0.0595703f,   0.117188f,     0.0751953f,    0.870117f,
-    -0.870117f,   0.046875f,     -0.280273f,    0.125f,        0.124023f,
-    1.0791f,      -0.964844f,    0.338867f,     -0.0791016f,   0.0751953f,
-    0.12207f,     0.920898f,     -0.888672f,    0.0273438f,    -0.250977f,
-    0.00488281f,  0.165039f,     1.01074f,      -0.944336f,    0.137695f,
-    -0.387695f,   -0.142578f,    0.238281f,     1.77246f,      -1.42285f,
-    0.90625f,     -0.856445f,    0.0556641f,    -0.219727f,    -0.785156f,
-    1.47266f,     -1.99902f,     1.27246f,      -0.132812f,    -0.746094f,
-    0.172852f,    -0.0830078f,   -1.3584f,      0.638672f,     0.0175781f,
-    -0.786133f,   0.754883f,     -0.729492f,    -0.808594f,    -0.291992f,
-    0.170898f,    -0.746094f,    0.623047f,     -0.667969f,    -0.743164f,
-    -0.241211f,   0.0693359f,    -0.725586f,    0.495117f,     -0.545898f,
-    -0.969727f,   -0.131836f,    0.0234375f,    -0.52832f,     0.280273f,
-    -0.327148f,   -1.0498f,      -0.210938f,    -0.253906f,    0.234375f,
-    0.661133f,    -0.0332031f,   -0.708008f,    -0.458984f,    0.31543f,
-    0.480469f,    1.59082f,      -1.22266f,     1.41602f,      -0.270508f,
-    0.263672f,    0.318359f,     1.21289f,      -1.12207f,     0.853516f,
-    -0.272461f,   0.158203f,     1.84766f,      2.0f,          0.341797f,
-    2.0f,         -0.788086f,    -0.264648f,    -0.326172f,    -1.25977f,
-    0.842773f,    -1.99902f,     -0.947266f,    0.249023f,     -0.642578f,
-    0.745117f,    -0.744141f,    -0.404297f,    -0.266602f,    0.0898438f,
-    -0.568359f,   0.501953f,     -0.494141f,    -0.858398f,    0.0722656f,
-    -0.543945f,   1.16895f,      1.12012f,      1.47461f,      -1.12988f,
-    -0.27832f,    0.53125f,      0.875f,        0.845703f,     -0.318359f,
-    1.68555f,     1.29199f,      -0.00195312f,  0.861328f,     0.601562f,
-    -0.519531f,   1.16211f,      -1.05957f,     0.0507812f,    0.904297f,
-    0.625977f,    -0.525391f,    1.16797f,      -0.163086f,    0.125977f,
-    1.99902f,     2.0f,          2.0f,          2.0f,          -0.00195312f,
-    -1.11719f,    -0.3125f,      -0.320312f,    0.585938f,     -1.99902f,
-    0.647461f,    0.198242f,     -0.538086f,    0.993164f,     -0.897461f,
-    -0.227539f,   -0.354492f,    0.0976562f,    -0.416016f,    0.623047f,
-    -0.682617f,   -0.832031f,    -0.223633f,    -0.160156f,    0.0751953f,
-    -0.791992f,   1.13379f,      -1.99902f,     -0.755859f,    0.669922f,
-    1.02637f,     1.26758f,      -0.293945f,    2.0f,          1.93457f,
-    -0.0126953f,  0.773438f,     0.475586f,     -0.59375f,     0.329102f,
-    -0.588867f,   0.113281f,     0.740234f,     0.749023f,     -0.716797f,
-    0.941406f,    -0.0878906f,   0.71875f,      1.8125f,       2.0f,
-    -0.289062f,   2.0f,          -1.01074f,     0.0117188f,    -0.183594f,
-    -0.969727f,   0.893555f,     -1.99902f,     0.333008f,     0.188477f,
-    -0.643555f,   0.504883f,     -0.511719f,    -0.804688f,    -0.957031f,
-    0.0546875f,   -0.305664f,    -0.0449219f,   -0.145508f,    -1.875f,
-    0.0996094f,   -0.155273f,    1.59668f,      1.5293f,       1.46973f,
-    2.0f,         -1.9834f,      0.375f,        1.20508f,      0.736328f,
-    -0.399414f,   2.0f,          2.0f,          0.123047f,     0.834961f,
-    1.04004f,     -0.808594f,    1.31934f,      -0.634766f,    0.548828f,
-    0.129883f,    -1.64746f,     2.0f,          -1.99902f,     0.819336f,
-    0.0273438f,   -0.254883f,    0.722656f,     -0.691406f,    -0.464844f,
-    -1.05566f,    0.0634766f,    -0.206055f,    1.02148f,      -0.90332f,
-    0.0595703f,   -0.03125f,     0.129883f,     -0.177734f,    0.697266f,
-    -0.713867f,   -0.351562f,    -0.169922f,    -0.119141f,    -0.172852f,
-    1.01855f,     -0.989258f,    -0.12793f,     -0.670898f,    -0.146484f,
-    -0.261719f,   1.16602f,      -1.05664f,     -0.302734f,    -0.25293f,
-    -0.0458984f,  -0.198242f,    0.90625f,      -0.876953f,    -0.144531f,
-    -0.424805f,   -0.151367f,    -0.147461f,    0.926758f,     -0.835938f,
-    -0.191406f,   -0.326172f,    -0.128906f,    -0.216797f,    0.910156f,
-    -0.851562f,   -0.291992f,    -0.549805f,    -0.0517578f,   -0.0869141f,
-    1.07715f,     -0.977539f,    -0.0361328f,   -0.418945f,    -0.148438f,
-    -0.133789f,   0.907227f,     -0.836914f,    -0.213867f,    -0.768555f,
-    -0.0664062f,  0.182617f,     1.0498f,       -0.915039f,    0.400391f,
-    -0.523438f,   0.015625f,     0.0f,          1.13184f,      -1.09961f,
-    -0.244141f,   -0.330078f,    -0.115234f,    0.0166016f,    0.944336f,
-    -0.868164f,   -0.430664f,    -0.246094f,    -0.0185547f,   -0.00976562f,
-    0.819336f,    -0.822266f,    -0.380859f,    -1.1709f,      0.0605469f,
-    -0.0498047f,  0.777344f,     -0.703125f,    0.0800781f,    -0.451172f,
-    0.304688f,    0.0517578f,    0.825195f,     -0.771484f,    0.145508f,
-    0.495117f,    -0.0888672f,   -0.243164f,    1.48145f,      -1.22168f,
-    0.0615234f,   -0.192383f,    -0.0537109f,   0.0195312f,    1.21582f,
-    -1.06836f,    0.175781f,     -0.394531f,    0.237305f,     -0.0126953f,
-    0.800781f,    -0.920898f,    -0.12207f,     -0.391602f,    -0.0917969f,
-    -0.0791016f,  1.08008f,      -1.03613f,     -0.0654297f,   -0.423828f,
-    0.0478516f,   -0.0253906f,   0.873047f,     -0.884766f,    -0.0722656f,
-    -0.579102f,   0.0136719f,    -0.0917969f,   0.954102f,     -0.922852f,
-    -0.172852f,   -0.244141f,    0.0f,          -0.141602f,    0.929688f,
-    -0.894531f,   -0.179688f,    -0.291992f,    0.0283203f,    -0.0947266f,
-    0.961914f,    -0.926758f,    -0.135742f,    -0.329102f,    0.0576172f,
-    -0.0351562f,  0.999023f,     -0.958984f,    -0.0498047f,   -0.248047f,
-    0.0869141f,   -0.078125f,    1.01074f,      -0.954102f,    0.00976562f,
-    -0.217773f,   0.0986328f,    -0.0556641f,   0.916992f,     -0.914062f,
-    -0.136719f,   -0.219727f,    0.0488281f,    -0.139648f,    0.985352f,
-    -0.952148f,   -0.152344f,    -0.286133f,    0.0166016f,    -0.0917969f,
-    1.0459f,      -0.972656f,    -0.0605469f,   -0.228516f,    0.0507812f,
-    -0.0810547f,  0.956055f,     -0.9375f,      -0.18457f,     -0.275391f,
-    0.0703125f,   -0.0986328f,   0.948242f,     -0.928711f,    -0.162109f,
-    -0.333008f};
-const size_t kAccelerometerLaptopModeTestDataLength =
-    ARRAY_SIZE(kAccelerometerLaptopModeTestData);
-
-const float kAccelerometerFullyOpenTestData[] = {
-    0.892578f,    -0.0810547f,  0.0146484f,    0.929688f,     -0.0644531f,
-    -0.0234375f,  0.996094f,    -0.0136719f,   0.0185547f,    1.02344f,
-    -0.0615234f,  -0.0449219f,  0.978516f,     0.125977f,     0.0400391f,
-    0.996094f,    0.0332031f,   -0.0117188f,   0.963867f,     0.107422f,
-    0.0214844f,   0.980469f,    0.0185547f,    -0.00683594f,  0.952148f,
-    0.0361328f,   0.0253906f,   0.976562f,     -0.00390625f,  -0.0126953f,
-    0.97168f,     0.0205078f,   0.0517578f,    1.01074f,      0.015625f,
-    -0.0234375f,  0.953125f,    -0.000976562f, 0.0390625f,    0.977539f,
-    -0.0224609f,  -0.00976562f, 0.954102f,     0.0244141f,    0.0439453f,
-    0.986328f,    0.00292969f,  -0.000976562f, 0.967773f,     0.0537109f,
-    0.046875f,    0.99707f,     0.0175781f,    -0.000976562f, 0.951172f,
-    0.0390625f,   0.0341797f,   0.974609f,     -0.00878906f,  -0.000976562f,
-    0.948242f,    0.0185547f,   0.0478516f,    0.976562f,     -0.000976562f,
-    -0.00683594f, 0.958984f,    0.0263672f,    0.078125f,     0.982422f,
-    -0.0205078f,  0.0283203f,   0.930664f,     0.00878906f,   0.0664062f,
-    0.970703f,    0.00390625f,  -0.0078125f,   0.945312f,     0.0380859f,
-    -0.00585938f, 0.972656f,    0.0419922f,    -0.0478516f,   1.01953f,
-    0.240234f,    -0.182617f,   1.00977f,      0.18457f,      -0.126953f,
-    1.05566f,     0.0751953f,   -0.0888672f,   1.09766f,      0.0732422f,
-    -0.0898438f,  1.21484f,     0.119141f,     -0.000976562f, 1.23633f,
-    0.194336f,    -0.447266f,   1.31445f,      0.213867f,     -0.118164f,
-    1.30762f,     0.0908203f,   -0.260742f,    0.860352f,     0.141602f,
-    -0.166016f,   0.868164f,    0.0429688f,    -0.258789f,    0.727539f,
-    0.0419922f,   -0.21875f,    0.740234f,     0.0126953f,    -0.162109f,
-    0.652344f,    -0.00292969f, -0.185547f,    0.666992f,     0.0800781f,
-    -0.272461f,   0.852539f,    -0.0478516f,   -0.228516f,    0.819336f,
-    -0.0996094f,  -0.180664f,   0.959961f,     -0.0537109f,   -0.240234f,
-    0.935547f,    -0.0917969f,  -0.269531f,    0.988281f,     -0.0507812f,
-    -0.197266f,   0.981445f,    -0.0712891f,   -0.323242f,    0.964844f,
-    -0.0683594f,  -0.203125f,   0.941406f,     -0.0898438f,   -0.236328f,
-    0.942383f,    -0.0429688f,  -0.206055f,    0.921875f,     -0.0527344f,
-    -0.239258f,   0.976562f,    -0.0742188f,   -0.261719f,    0.958008f,
-    -0.09375f,    -0.311523f,   0.949219f,     -0.0839844f,   -0.242188f,
-    0.949219f,    -0.0742188f,  -0.323242f,    0.973633f,     -0.0263672f,
-    -0.238281f,   0.958984f,    -0.0488281f,   -0.293945f,    0.931641f,
-    -0.0214844f,  -0.225586f,   0.931641f,     0.0195312f,    -0.225586f,
-    0.810547f,    -0.0947266f,  -0.15332f,     0.947266f,     0.241211f,
-    -0.100586f,   0.326172f,    0.286133f,     -0.12207f,     0.855469f,
-    0.677734f,    -0.228516f,   0.229492f,     1.08398f,      0.0224609f,
-    0.822266f,    0.759766f,    -0.0722656f,   0.294922f,     1.42676f,
-    0.147461f,    0.239258f,    0.755859f,     0.142578f,     -0.120117f,
-    1.00977f,     -0.0722656f,  -0.154297f,    0.832031f,     -0.0576172f,
-    -0.15332f,    1.10156f,     -0.0273438f,   -0.119141f,    1.05078f,
-    0.0166016f,   -0.0927734f,  1.09961f,      -0.0703125f,   -0.0751953f,
-    1.04688f,     -0.00195312f, -0.078125f,    0.897461f,     -0.0625f,
-    -0.078125f,   0.854492f,    -0.0947266f,   -0.123047f,    0.811523f,
-    -0.0488281f,  -0.113281f,   0.796875f,     0.0f,          -0.0488281f,
-    0.961914f,    -0.177734f,   -0.0898438f,   0.859375f,     -0.172852f,
-    0.0126953f,   1.1084f,      -0.158203f,    0.0292969f,    1.0791f,
-    -0.152344f,   0.154297f,    1.29492f,      -0.126953f,    0.134766f,
-    1.23145f,     -0.0878906f,  -0.200195f,    0.667969f,     -0.216797f,
-    -0.0888672f,  0.935547f,    -0.143555f,    0.000976562f,  1.13281f,
-    -0.0498047f,  0.00195312f,  1.05469f,      -0.231445f,    0.0927734f,
-    0.956055f,    -0.292969f,   0.0625f,       0.927734f,     -0.112305f,
-    0.0585938f,   0.975586f,    -0.163086f,    0.0957031f,    1.03418f,
-    -0.229492f,   0.000976562f, 0.985352f,     -0.09375f,     -0.00585938f,
-    0.945312f,    -0.140625f,   -0.0302734f,   0.998047f,     -0.208008f,
-    -0.0507812f,  0.916016f,    -0.112305f,    0.123047f,     0.981445f,
-    -0.205078f,   0.129883f,    1.02832f,      -0.211914f,    0.105469f,
-    1.01367f,     -0.142578f,   0.111328f,     1.00098f,      -0.110352f,
-    0.0986328f,   0.999023f,    -0.15918f,     0.0839844f,    0.922852f,
-    -0.223633f,   0.261719f,    1.06641f,      -0.138672f,    0.240234f,
-    0.916016f,    -0.296875f,   0.00488281f,   1.04199f,      -0.128906f,
-    0.0341797f,   1.0791f,      -0.265625f,    0.015625f,     0.963867f,
-    -0.161133f,   0.015625f,    0.958008f,     -0.0722656f,   -0.125f,
-    1.03125f,     -0.19043f,    -0.0722656f,   1.16602f,      -0.126953f,
-    -0.143555f,   1.12793f,     -0.197266f,    -0.120117f,    1.26465f,
-    -0.232422f,   -0.226562f,   1.125f,        -0.0712891f,   -0.0927734f,
-    1.26465f,     -0.145508f,   -0.551758f,    0.90918f,      -0.163086f,
-    -0.228516f,   1.2041f,      -0.0371094f,   -0.493164f,    0.827148f,
-    0.0371094f,   -0.162109f,   0.568359f,     -0.195312f,    -0.641602f,
-    0.438477f,    -0.212891f,   -0.513672f,    0.208008f,     -0.0488281f,
-    -0.776367f,   0.0488281f,   -0.115234f,    -0.84375f,     -0.314453f,
-    0.106445f,    -0.966797f,   -0.0078125f,   0.00976562f,   -1.01953f,
-    -0.220703f,   -0.0322266f,  -0.994141f,    0.0117188f,    -0.248047f,
-    -0.975586f,   0.121094f,    -0.0205078f,   -0.947266f,    0.00292969f,
-    -0.160156f,   -0.9375f,     0.0175781f,    -0.0986328f,   -0.916992f,
-    -0.0195312f,  -0.208008f,   -0.9375f,      -0.0654297f,   -0.134766f,
-    -0.948242f,   -0.0185547f,  -0.231445f,    -0.977539f,    -0.0537109f,
-    -0.198242f,   -1.0166f,     0.0439453f,    -0.433594f,    -0.994141f,
-    -0.0595703f,  -0.389648f,   -1.07129f,     0.0859375f,    -0.109375f,
-    -1.01953f,    0.0966797f,   -0.12207f,     -1.01074f,     0.125977f,
-    -0.192383f,   -1.0f,        0.0820312f,    -0.166016f,    -1.04688f,
-    0.0751953f,   -0.265625f,   -1.00879f,     0.139648f,     -0.135742f,
-    -1.00977f,    0.0644531f,   -0.235352f,    -0.989258f,    0.100586f,
-    -0.144531f,   -0.858398f,   0.0273438f,    -0.22168f,     -0.878906f,
-    -0.0634766f,  -0.1875f,     -0.905273f,    -0.0195312f,   -0.232422f,
-    -0.926758f,   -0.0732422f,  -0.319336f,    -1.05078f,     -0.00878906f,
-    -0.5625f,     -1.05176f,    0.111328f,     -0.456055f,    -0.942383f,
-    -0.0146484f,  -0.171875f,   -0.946289f,    -0.0224609f,   -0.174805f,
-    -0.901367f,   -0.0283203f,  -0.332031f,    -0.948242f,    -0.0732422f,
-    -0.262695f,   -0.867188f,   0.0351562f,    -0.271484f,    -0.913086f,
-    -0.0878906f,  -0.259766f,   -1.2793f,      -0.226562f,    -0.382812f,
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-    -0.959961f,   -0.511719f,   -0.381836f,    -1.04883f,     -0.924805f,
-    -0.756836f,   -1.17969f,    -0.521484f,    -0.105469f,    -1.16504f,
-    -0.767578f,   -0.477539f,   -0.401367f,    -0.0341797f,   -0.341797f,
-    0.0507812f,   0.389648f,    -0.507812f,    0.186523f,     0.438477f,
-    -1.33594f,    0.625977f,    0.518555f,     -0.671875f,    0.182617f,
-    0.432617f,    -1.18359f,    0.132812f,     0.414062f,     -0.782227f,
-    0.0615234f,   0.401367f,    -1.30176f,     -0.0683594f,   -0.100586f,
-    -0.586914f,   0.0302734f,   0.191406f,     -0.983398f,    -0.0273438f,
-    -0.735352f,   -0.224609f,   -0.342773f,    -0.241211f,    -0.566406f,
-    0.015625f,    -1.1084f,     -0.00976562f,  -0.652344f,    -0.75293f,
-    0.239258f,    -0.449219f,   -1.08789f,     0.107422f,     -0.572266f,
-    -0.887695f,   0.407227f,    -0.423828f,    -0.919922f,    0.173828f,
-    -0.705078f,   -0.825195f,   0.411133f,     -0.484375f,    -0.799805f,
-    0.237305f,    -0.776367f,   -0.745117f,    0.459961f,     -0.819336f,
-    -0.749023f,   0.208008f,    -0.788086f,    -0.716797f,    0.226562f,
-    -0.795898f,   -0.72168f,    0.123047f,     -0.790039f,    -0.705078f,
-    0.101562f,    -0.720703f,   -0.745117f,    -0.0517578f,   -0.771484f,
-    -0.701172f,   -0.0175781f,  -0.758789f,    -0.765625f,    -0.0917969f,
-    -0.745117f,   -0.751953f,   -0.149414f,    -0.6875f,      -0.660156f,
-    -0.0166016f,  -0.782227f,   -0.592773f,    -0.0205078f,   -0.726562f,
-    -0.376953f,   0.119141f,    -0.599609f,    -0.371094f,    0.0107422f,
-    -0.736328f,   -0.325195f,   0.0771484f,    -0.768555f,    -0.388672f,
-    -0.0273438f,  -0.750977f,   -0.477539f,    0.107422f,     -0.919922f,
-    -0.514648f,   0.125f,       -0.961914f,    -0.37793f,     0.0136719f,
-    -0.981445f,   -0.447266f,   -0.0107422f,   -0.823242f,    -0.303711f,
-    0.0986328f,   -1.00684f,    -0.366211f,    0.0986328f,    -1.14551f,
-    -0.239258f,   0.140625f,    -0.894531f,    -0.297852f,    0.0849609f,
-    -0.949219f,   -0.341797f,   0.131836f,     -0.966797f,    -0.380859f,
-    0.0947266f,   -0.75293f,    -0.391602f,    0.0839844f,    -0.908203f,
-    -0.40625f,    0.161133f,    -0.860352f,    -0.452148f,    0.1875f,
-    -0.950195f,   -0.496094f,   0.200195f,     -0.828125f,    -0.581055f,
-    0.0771484f,   -0.93457f,    -0.607422f,    0.0996094f,    -0.863281f,
-    -0.59375f,    0.0927734f,   -0.802734f,    -0.604492f,    0.0947266f,
-    -0.807617f,   -0.722656f,   0.101562f,     -0.844727f,    -0.711914f,
-    0.149414f,    -1.03125f,    -0.77832f,     0.125977f,     -0.78418f,
-    -0.740234f,   0.121094f,    -0.891602f,    -0.808594f,    0.164062f,
-    -0.650391f,   -0.80957f,    0.0888672f,    -0.416992f,    -0.866211f,
-    0.155273f,    -0.382812f,   -0.880859f,    0.0849609f,    -0.264648f,
-    -0.775391f,   0.229492f,    -0.389648f,    -0.814453f,    0.0664062f,
-    -0.226562f,   -0.625f,      0.414062f,     -0.274414f,    -0.681641f,
-    0.0292969f,   -0.0478516f,  -0.711914f,    0.794922f,     -0.388672f,
-    -0.584961f,   0.368164f,    -0.257812f,    -0.545898f,    1.09277f,
-    -0.277344f,   -0.125977f,   0.822266f,     -0.365234f,    -0.467773f,
-    0.714844f,    -0.413086f,   -0.136719f,    1.57227f,      -0.0947266f,
-    -0.223633f,   0.817383f,    -0.0556641f,   -0.0322266f,   1.18945f,
-    -0.191406f,   -0.498047f,   0.991211f,     -0.231445f,    -0.246094f,
-    0.8125f,      -0.239258f,   -0.755859f,    0.853516f,     -0.228516f,
-    -0.821289f,   0.503906f,    -0.121094f,    -0.795898f,    0.523438f,
-    -0.220703f,   -0.773438f,   0.517578f,     -0.274414f,    -0.757812f,
-    0.539062f,    -0.222656f,   -0.770508f,    0.396484f,     -0.115234f,
-    -1.2334f,     0.485352f,    -0.217773f,    -0.94043f,     1.01758f,
-    -0.202148f,   -0.605469f,   0.0546875f,    0.0957031f,    -0.639648f,
-    -0.661133f,   0.245117f,    -0.750977f,    0.0615234f,    -0.726562f,
-    -0.879883f,   -0.432617f,   -1.05859f,     -1.29688f,     0.00488281f,
-    0.193359f,    -0.939453f,   0.209961f,     -0.209961f,    -0.793945f,
-    0.251953f,    0.722656f,    -0.447266f,    0.0615234f,    0.855469f,
-    -0.454102f,   -0.0126953f,  0.0527344f,    -0.342773f,    0.154297f,
-    1.3877f,      -0.65918f,    0.133789f,     0.0576172f,    -0.233398f,
-    -0.12207f,    0.46582f,     -1.09961f,     0.438477f,     -0.641602f,
-    -0.861328f,   0.197266f,    -1.99902f,     -0.932617f,    0.234375f,
-    0.389648f,    -0.792969f,   -0.0908203f,   1.66797f,      -1.0459f,
-    0.0107422f,   -0.543945f,   -0.80957f,     0.206055f,     -0.27832f,
-    -0.915039f,   0.104492f,    -0.301758f,    -0.891602f,    0.0556641f,
-    -0.681641f,   -0.901367f,   0.0498047f,    -0.461914f,    -0.927734f,
-    -0.0390625f,  -0.229492f,   -1.04004f,     0.0869141f,    -0.435547f,
-    -1.02148f,    0.0947266f,   -0.527344f,    -0.979492f,    0.0751953f,
-    0.266602f,    -0.786133f,   -0.0224609f,   -0.0947266f,   -0.702148f,
-    -0.00683594f, -0.316406f,   -0.698242f,    -0.317383f,    1.92578f,
-    -1.0498f,     0.0273438f,   -1.14258f,     -0.226562f,    0.233398f,
-    -0.995117f,   -0.9375f,     0.0146484f,    -0.223633f,    -0.49707f,
-    -0.0078125f,  -1.95703f,    -0.847656f,    0.157227f,     0.129883f,
-    -0.459961f,   -0.114258f,   2.0f,          -1.13574f,     -0.0839844f,
-    -0.0878906f,  -0.783203f,   0.131836f,     -0.803711f,    -0.90332f,
-    0.208984f,    -0.365234f,   -0.97168f,     -0.0322266f,   0.186523f,
-    -0.924805f,   0.00292969f,  -0.272461f,    -0.890625f,    0.015625f,
-    -0.333008f,   -0.932617f,   0.180664f,     -0.459961f,    -0.90918f,
-    0.240234f,    -0.625977f,   -1.1582f,      0.0996094f,    -0.170898f,
-    -1.08887f,    -0.00976562f, -0.849609f,    -0.430664f,    0.139648f,
-    -0.308594f,   -0.572266f,   -0.722656f,    1.83496f,      -1.00977f,
-    0.387695f,    0.487305f,    -0.268555f,    0.0712891f,    -0.0136719f,
-    -1.5332f,     0.290039f,    -0.0351562f,   -0.861328f,    1.98535f,
-    -1.16602f,    -0.602539f,   0.441406f,     0.175781f,     -0.605469f,
-    -0.831055f,   0.686523f,    -0.984375f,    0.494141f,     -0.489258f,
-    -0.895508f,   0.371094f,    -0.665039f,    -1.14258f,     -0.214844f,
-    -0.140625f,   -1.06348f,    -0.0996094f,   0.255859f,     -0.874023f,
-    0.193359f,    -0.0947266f,  -0.959961f,    -0.0966797f,   0.00195312f,
-    -0.996094f,   -0.0117188f,  -0.174805f,    -0.962891f,    0.106445f,
-    -0.162109f,   -1.04297f,    -0.0283203f,   -0.306641f,    -1.06738f,
-    -0.0224609f,  -0.129883f,   -1.03223f,     0.129883f,     0.195312f,
-    -1.08789f,    -0.130859f,   0.649414f,     -0.572266f,    -0.0136719f,
-    -0.793945f,   -0.382812f,   0.0f,          -1.08301f,     -0.78125f,
-    -0.0224609f,  -0.339844f,   -0.629883f,    -0.0947266f,   -1.83789f,
-    -1.01562f,    0.046875f,    0.223633f,     -0.808594f,    0.0957031f,
-    1.09766f,     -0.756836f,   -0.0488281f,   0.157227f,     -0.59082f,
-    -0.103516f,   0.929688f,    -0.816406f,    -0.0322266f,   -0.426758f,
-    -0.868164f,   -0.209961f,   -1.99902f,     -0.986328f,    -0.00878906f,
-    -0.365234f,   -0.980469f,   0.0439453f,    0.59375f,      -0.994141f,
-    0.0253906f,   0.0371094f,   -0.970703f,    -0.0273438f,   -0.120117f,
-    -0.935547f,   0.00195312f,  -0.235352f,    -0.952148f,    -0.0263672f,
-    -0.194336f,   -0.917969f,   -0.0195312f,   -0.261719f,    -0.928711f,
-    -0.0234375f,  -0.219727f,   -0.945312f,    0.0107422f,    -0.228516f,
-    -0.938477f,   0.00683594f,  -0.178711f,    -0.791016f,    0.03125f,
-    -0.255859f,   -0.789062f,   0.0f,          -0.141602f,    -0.789062f,
-    0.232422f,    -0.285156f,   -0.788086f,    0.228516f,     -0.28125f,
-    -1.0f,        0.258789f,    -0.277344f,    -0.999023f,    0.28125f,
-    -0.25293f,    -1.06152f,    0.046875f,     -0.421875f,    -1.07715f,
-    0.0390625f,   -0.224609f,   -0.923828f,    -0.0205078f,   -0.335938f,
-    -0.984375f,   -0.0966797f,  -0.34668f,     -0.990234f,    -0.191406f,
-    -0.301758f,   -1.03613f,    -0.241211f,    -0.37207f,     -0.975586f,
-    -0.267578f,   -0.460938f,   -1.00977f,     -0.320312f,    -0.382812f,
-    -0.913086f,   -0.257812f,   -0.457031f,    -0.925781f,    -0.256836f,
-    -0.34668f,    -0.889648f,   -0.237305f,    -0.393555f,    -0.897461f,
-    -0.239258f,   -0.429688f,   -0.844727f,    -0.21875f,     -0.428711f,
-    -0.87207f,    -0.203125f,   -0.368164f,    -0.84668f,     -0.101562f,
-    -0.423828f,   -0.875977f,   -0.165039f,    -0.363281f,    -0.884766f,
-    -0.0625f,     -0.473633f,   -0.90332f,     -0.078125f,    -0.138672f,
-    -0.918945f,   -0.198242f,   -0.25f,        -0.928711f,    -0.138672f,
-    -0.267578f,   -1.08203f,    0.00488281f,   -0.575195f,    -1.125f,
-    -0.0332031f,  -0.4375f,     -0.924805f,    0.078125f,     -0.305664f,
-    -0.93457f,    -0.0166016f,  -0.475586f,    -0.94043f,     -0.00488281f,
-    -0.533203f,   -0.956055f,   0.00292969f,   -0.391602f,    -1.00293f,
-    0.0361328f,   -0.711914f,   -1.0166f,      0.0332031f,    -0.448242f,
-    -0.806641f,   -0.21582f,    -0.556641f,    -0.759766f,    -0.0214844f,
-    -0.626953f,   -0.700195f,   -0.263672f,    -0.308594f,    -0.608398f,
-    -0.236328f,   -0.253906f,   -0.616211f,    -0.378906f,    0.224609f,
-    -0.498047f,   -0.399414f,   0.206055f,     -0.516602f,    -0.228516f,
-    0.743164f,    -0.174805f,   -0.125f,       0.760742f,     -0.0214844f,
-    -0.135742f,   0.966797f,    0.240234f,     0.0332031f,    1.01855f,
-    0.105469f,    0.15332f,     0.950195f,     0.240234f,     0.0732422f,
-    1.16895f,     0.245117f,    0.206055f,     0.952148f,     0.273438f,
-    -0.0390625f,  1.2793f,      0.404297f,     0.303711f,     0.720703f,
-    0.369141f,    0.0966797f,   0.918945f,     0.329102f,     0.0390625f,
-    0.991211f,    0.397461f,    -0.124023f,    0.866211f,     0.210938f,
-    0.130859f,    1.08789f,     0.317383f,     0.0537109f,    0.858398f,
-    0.245117f,    0.0732422f,   0.741211f,     0.419922f,     0.0302734f,
-    0.681641f,    0.485352f,    -0.0214844f,   0.641602f,     0.520508f,
-    -0.129883f,   0.839844f,    0.490234f,     0.00390625f,   0.676758f,
-    0.581055f,    -0.0146484f,  0.692383f,     0.432617f,     -0.0371094f,
-    0.807617f,    0.664062f,    0.255859f,     0.216797f,     1.22559f,
-    0.0195312f,   1.22168f,     1.2793f,       -0.405273f,    1.72559f,
-    0.708984f,    -0.209961f,   0.579102f,     0.821289f,     0.0380859f,
-    0.605469f,    0.80957f,     0.147461f,     0.419922f,     0.869141f,
-    0.0390625f,   0.5625f,      0.786133f,     0.0654297f,    0.594727f,
-    0.879883f,    0.0166016f,   0.480469f,     0.835938f,     0.00195312f,
-    0.414062f,    0.899414f,    -0.03125f,     0.344727f,     0.889648f,
-    0.0185547f,   0.236328f,    0.932617f,     -0.00585938f,  0.255859f,
-    0.910156f,    0.0898438f,   0.262695f,     0.945312f,     0.0126953f,
-    0.279297f,    0.860352f,    0.0507812f,    0.322266f,     0.913086f,
-    0.00195312f,  0.296875f,    0.875977f,     0.0078125f,    0.373047f,
-    0.922852f,    -0.0244141f,  0.267578f,     0.884766f,     0.0117188f,
-    0.347656f,    0.926758f,    -0.0371094f,   0.266602f,     0.894531f,
-    -0.00683594f, 0.345703f,    0.926758f,     -0.0478516f,   0.269531f,
-    0.887695f,    0.0146484f,   0.360352f,     0.927734f,     -0.03125f,
-    0.272461f};
-const size_t kAccelerometerFullyOpenTestDataLength =
-    ARRAY_SIZE(kAccelerometerFullyOpenTestData);
-
diff --git a/test/motion_angle_data_literals_tablet.c b/test/motion_angle_data_literals_tablet.c
deleted file mode 100644
index 456779f457..0000000000
--- a/test/motion_angle_data_literals_tablet.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "util.h"
-
-/*
- * Recopied from
- * chromium/src/ash/wm/tablet_mode/accelerometer_test_data_literals.cc
- *
- * The arrays contain actual accelerator readings.
- */
-const float kAccelerometerVerticalHingeTestData[] = {
-    -0.0766145f,  6.02381f,     7.85298f,     -0.268151f,   -8.84897f,
-    -1.3216f,     -0.402226f,   5.11401f,     8.77236f,     -1.10133f,
-    -10.1706f,    1.24498f,     -1.18752f,    6.40688f,     8.0924f,
-    -2.60489f,    -8.99262f,    2.58574f,     0.632069f,    9.05008f,
-    3.61046f,     1.50356f,     -9.67257f,    1.93451f,     0.411803f,
-    8.81066f,     0.268151f,    -0.00957681f, -8.7532f,     2.15478f,
-    -0.0191536f,  9.49062f,     -0.68953f,    0.0383072f,   -8.94474f,
-    2.99754f,     -0.871489f,   9.80665f,     1.53229f,     -0.92895f,
-    -9.88326f,    0.957681f,    0.507571f,    9.19373f,     1.71425f,
-    0.287304f,    -9.03093f,    0.651223f,    0.363919f,    9.71088f,
-    1.18752f,     1.10133f,     -10.0556f,    2.98796f,     0.23942f,
-    9.39485f,     1.0343f,      0.842759f,    -9.73961f,    -1.12049f,
-    0.172383f,    9.50977f,     1.18752f,     0.0383072f,   -9.9503f,
-    0.957681f,    -0.373495f,   9.96946f,     1.01514f,     0.794875f,
-    -10.1897f,    -1.38864f,    -9.50977f,    -1.04387f,    0.325611f,
-    -9.76834f,    1.05345f,     -0.679953f,   -9.76834f,    -0.641646f,
-    0.488417f,    -9.2895f,     0.316035f,    0.258574f,    -9.29908f,
-    -0.890643f,   0.469264f,    -9.33739f,    0.823605f,    -0.45011f,
-    -9.69173f,    -1.02472f,    0.536301f,    -9.52892f,    0.90022f,
-    -0.411803f,   -9.34696f,    -0.890643f,   0.430956f,    -9.48104f,
-    0.823605f,    -0.603339f,   -9.7875f,     -0.565032f,   0.574608f,
-    -9.96946f,    0.536301f,    -0.699107f,   -9.57681f,    -0.823605f,
-    0.641646f,    -9.43316f,    0.593762f,    -0.775721f,   -9.35654f,
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-    2.19309f,     -8.49463f,    -4.95121f,    2.13563f,     7.91044f,
-    4.29999f,     2.1452f,      -8.76278f,    -2.24097f,    1.31202f,
-    8.59997f,     5.72693f,     0.746991f,    -9.55765f,    -3.54342f,
-    1.36948f,     8.5042f,      5.09486f,     1.17795f,     -9.62469f,
-    -4.1276f,     1.77171f,     8.69574f,     5.46836f,     1.63763f,
-    -9.40442f,    -2.32716f,    1.91536f,     7.75721f,     5.25767f,
-    2.04944f,     -8.81066f,    -2.40378f,    0.392649f,    7.73806f,
-    5.63116f,     1.45567f,     -9.24162f,    -1.49398f,    -0.258574f,
-    6.82826f,     7.34541f,     -0.42138f,    -9.07881f,    -1.30245f,
-    -0.517148f,   6.97192f,     7.6806f,      -0.890643f,   -9.58638f,
-    -4.81713f,    -0.21069f,    3.13162f,     9.20331f,     -0.967257f,
-    -10.0748f,    0.181959f,    -0.948104f,   -5.9855f,     7.4316f,
-    -1.00556f,    -9.5385f,     0.497994f,    0.162806f,    -8.47547f,
-    4.32872f,     0.248997f,    -9.165f,      -2.27928f,    0.143652f,
-    -8.6287f,     4.47237f,     0.354342f,    -9.51935f,    0.986411f,
-};
-
-const size_t kAccelerometerVerticalHingeTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeTestData);
-
-const float kAccelerometerVerticalHingeUnstableTestData[] = {
-    8.5904f,   -1.36948f,  -3.74453f,   8.72447f,  1.1971f,    4.00311f,
-    8.80109f,  -3.08373f,  2.27928f,    8.95431f,  -1.90578f,  -1.10133f,
-    8.93516f,  -2.03986f,  0.248997f,   9.05008f,  1.53229f,   -0.708684f,
-    -8.78193f, 1.43652f,   -2.63362f,   -8.66701f, 0.220267f,  2.79643f,
-    -8.66701f, -2.06859f,  2.42293f,    -8.79151f, -2.88262f,  -1.16837f,
-    8.74362f,  -1.9824f,   3.53384f,    9.04051f,  0.0574608f, -1.36948f,
-    8.78193f,  -4.1276f,   2.58574f,    8.8777f,   0.201113f,  -1.80044f,
-    8.70532f,  -0.296881f, 1.52271f,    9.02135f,  -0.871489f, -2.43251f,
-    -9.09797f, -1.3216f,   -3.60088f,   -8.97347f, 2.52828f,   2.6432f,
-    -8.82024f, 1.87705f,   0.354342f,   -7.93917f, -4.38618f,  0.258574f,
-    -8.81066f, 1.91536f,   -2.92093f,   -8.04452f, -5.4492f,   3.28484f,
-    -8.86812f, 2.05901f,   0.890643f,   -8.01579f, -5.65989f,  -2.20267f,
-    -9.0022f,  2.18351f,   -2.9305f,    -8.80109f, -4.01268f,  3.055f,
-    -9.37569f, -1.04387f,  0.277727f,   -6.80911f, 2.806f,     -6.0717f,
-    -8.79151f, -8.79151f,  -2.11647f,   -8.6287f,  -1.53229f,  3.58173f,
-    -8.97347f, -0.335188f, 1.26414f,    8.5042f,   1.51314f,   -2.20267f,
-    -9.19373f, -1.37906f,  1.41737f,    -7.67102f, 2.8922f,    -5.09486f,
-    -8.81066f, 0.986411f,  2.30801f,    -8.53294f, 3.26569f,   -3.11246f,
-    -9.03093f, 1.06303f,   1.39821f,    -8.8777f,  -4.47237f,  -0.632069f,
-    -8.74362f, -1.83875f,  -0.0957681f, -7.92002f, 1.0343f,    -3.84988f,
-    -8.92558f, 0.440533f,  1.26414f,    -8.71489f, -0.153229f, -3.64876f,
-};
-
-const size_t kAccelerometerVerticalHingeUnstableTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData);
diff --git a/test/motion_angle_tablet.c b/test/motion_angle_tablet.c
deleted file mode 100644
index 8eea053405..0000000000
--- a/test/motion_angle_tablet.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test motion sense code, when in tablet mode.
- */
-
-#include <math.h>
-#include <stdio.h>
-
-#include "accelgyro.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "motion_common.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "tablet_mode.h"
-#include "test_util.h"
-#include "util.h"
-
-
-/*****************************************************************************/
-/* Test utilities */
-
-/* convert array value from g to m.s^2. */
-int filler(const struct motion_sensor_t *s, const float v)
-{
-	return FP_TO_INT( fp_div(
-		FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR,
-		fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G)));
-}
-
-static int test_lid_angle_less180(void)
-{
-	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
-
-	/* We don't have TASK_CHIP so simulate init ourselves */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
-	TEST_ASSERT(lid->drv->get_data_rate(lid) == 0);
-
-	/* Go to S0 state */
-	hook_notify(HOOK_CHIPSET_SUSPEND);
-	hook_notify(HOOK_CHIPSET_RESUME);
-	msleep(1000);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S0);
-	TEST_ASSERT(lid->drv->get_data_rate(lid) == TEST_LID_FREQUENCY);
-
-	/* Open lid, testing close to 180 degree. */
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(1000);
-
-	cprints(CC_ACCEL, "start loop");
-	/* Force clamshell mode, to be sure we go in tablet mode ASAP. */
-	tablet_set_mode(0, TABLET_TRIGGER_LID);
-
-	/* Check we stay in tablet mode, even when hinge is vertical. */
-	while (index < kAccelerometerVerticalHingeTestDataLength) {
-		feed_accel_data(kAccelerometerVerticalHingeTestData,
-				&index, filler);
-		wait_for_valid_sample();
-		lid_angle = motion_lid_get_angle();
-		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
-		/* We need few sample to debounce and enter laptop mode. */
-		TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE * \
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
-			    tablet_get_mode());
-	}
-	/*
-	 * Check we stay in tablet mode, even when hinge is vertical and
-	 * shaked.
-	 */
-	tablet_set_mode(0, TABLET_TRIGGER_LID);
-	while (index < kAccelerometerVerticalHingeUnstableTestDataLength) {
-		feed_accel_data(kAccelerometerVerticalHingeUnstableTestData,
-				&index, filler);
-		wait_for_valid_sample();
-		lid_angle = motion_lid_get_angle();
-		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
-		/* We need few sample to debounce and enter laptop mode. */
-		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
-			    tablet_get_mode());
-	}
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_lid_angle_less180);
-
-	test_print_result();
-}
diff --git a/test/motion_angle_tablet.tasklist b/test/motion_angle_tablet.tasklist
deleted file mode 100644
index 0b774ebb4a..0000000000
--- a/test/motion_angle_tablet.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  \
-  TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/motion_common.c b/test/motion_common.c
deleted file mode 100644
index 135da43188..0000000000
--- a/test/motion_common.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common test code to test lid angle calculation.
- */
-
-#include "accelgyro.h"
-#include "driver/accelgyro_bmi_common.h"
-#include "host_command.h"
-#include "motion_common.h"
-#include "motion_sense.h"
-#include "task.h"
-#include "timer.h"
-
-/*****************************************************************************/
-/* Mock functions */
-static int accel_init(struct motion_sensor_t *s)
-{
-	return sensor_init_done(s);
-}
-
-static int accel_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	rotate(s->xyz, *s->rot_standard_ref, v);
-	return EC_SUCCESS;
-}
-
-static int accel_set_range(struct motion_sensor_t *s, int range, int rnd)
-{
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int accel_get_resolution(const struct motion_sensor_t *s)
-{
-#ifdef TEST_BODY_DETECTION
-	/* Assume we are using BMI160 */
-	return BMI_RESOLUTION;
-#endif
-	return 0;
-}
-
-int test_data_rate[2] = { 0 };
-
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
-{
-	test_data_rate[s - motion_sensors] = rate | (rnd ? ROUND_UP_FLAG : 0);
-	return EC_SUCCESS;
-}
-
-static int accel_get_data_rate(const struct motion_sensor_t *s)
-{
-	return test_data_rate[s - motion_sensors];
-}
-
-#ifdef TEST_BODY_DETECTION
-static int accel_get_rms_noise(const struct motion_sensor_t *s)
-{
-	/* Assume we are using BMI160 */
-	fp_t rate = INT_TO_FP(accel_get_data_rate(s) / 1000);
-	fp_t noise_100hz = INT_TO_FP(BMI160_ACCEL_RMS_NOISE_100HZ);
-	fp_t sqrt_rate_ratio = fp_sqrtf(fp_div(rate,
-					       INT_TO_FP(BMI_ACCEL_100HZ)));
-	return FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
-}
-#endif
-
-const struct accelgyro_drv test_motion_sense = {
-	.init = accel_init,
-	.read = accel_read,
-	.set_range = accel_set_range,
-	.get_resolution = accel_get_resolution,
-	.set_data_rate = accel_set_data_rate,
-	.get_data_rate = accel_get_data_rate,
-#ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = accel_get_rms_noise,
-#endif
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE] = {
-		.name = "base",
-		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-		.chip = MOTIONSENSE_CHIP_LSM6DS0,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &test_motion_sense,
-		.rot_standard_ref = NULL,
-		.default_range = 2,  /* g, enough for laptop. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = TEST_LID_FREQUENCY,
-			},
-		},
-	},
-	[LID] = {
-		.name = "lid",
-		.active_mask = SENSOR_ACTIVE_S0,
-		.chip = MOTIONSENSE_CHIP_KXCJ9,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &test_motion_sense,
-		.rot_standard_ref = NULL,
-		.default_range = 2,  /* g, enough for laptop. */
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = TEST_LID_FREQUENCY,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/* Read 6 samples from array to sensor vectors, convert units if necessary. */
-void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t*, const float))
-{
-	int i, j;
-
-	for (i = 0; i < motion_sensor_count; i++) {
-		struct motion_sensor_t *s = &motion_sensors[i];
-
-		for (j = X; j <= Z; j++)
-			s->xyz[j] = filler(s, array[*idx + i * 3 + j]);
-	}
-	*idx += 6;
-}
-
-void wait_for_valid_sample(void)
-{
-	uint8_t sample;
-	uint8_t *lpc_status = host_get_memmap(EC_MEMMAP_ACC_STATUS);
-
-	sample = *lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
-	usleep(TEST_LID_EC_RATE);
-	while ((*lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK) == sample)
-		usleep(TEST_LID_SLEEP_RATE);
-}
-
-
diff --git a/test/motion_common.h b/test/motion_common.h
deleted file mode 100644
index 45d856d9ef..0000000000
--- a/test/motion_common.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Common test code to test lid angle calculation.
- */
-#ifndef __CROS_EC_MOTION_COMMON_H
-#define __CROS_EC_MOTION_COMMON_H
-
-#include "motion_sense.h"
-/*
- * Period in us for the motion task period.
- * The task will read the vectors at that interval
- */
-#define TEST_LID_EC_RATE (1 * MSEC)
-#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE)   /* mHz */
-
-/*
- * Time in ms to wait for the task to read the vectors.
- */
-#define TEST_LID_SLEEP_RATE (TEST_LID_EC_RATE / 5)
-
-/* We gather 6 elements [2 vectors of 3 axis] per sample. */
-#define TEST_LID_SAMPLE_SIZE (2 * 3)
-
-extern enum chipset_state_mask sensor_active;
-
-extern struct motion_sensor_t motion_sensors[];
-extern const unsigned int motion_sensor_count;
-
-void wait_for_valid_sample(void);
-void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t *s, const float f));
-
-/*
- * External data - from
- * chromium/src/ash/wm/tablet_mode/tablet_mode_controller_unittest.cc
- *
- * Test accelerometer data taken with the lid at less than 180 degrees while
- * shaking the device around. The data is to be interpreted in groups of 6 where
- * each 6 values corresponds to the base accelerometer (-y / g, -x / g, -z / g)
- * followed by the lid accelerometer (-y / g , x / g, z / g).
- * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ]
- */
-extern const float kAccelerometerLaptopModeTestData[];
-extern const size_t kAccelerometerLaptopModeTestDataLength;
-
-/*
- * Test accelerometer data taken with the lid open 360 degrees while
- * shaking the device around. The data is to be interpreted in groups of 6 where
- * each 6 values corresponds to the base accelerometer (-y / g, -x / g, -z / g)
- * followed by the lid accelerometer (-y / g , x / g, z / g).
- * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ]
- */
-extern const float kAccelerometerFullyOpenTestData[];
-extern const size_t kAccelerometerFullyOpenTestDataLength;
-
-/*
- * Test accelerometer data taken with the lid open 360 degrees while the device
- * hinge was nearly vertical, while shaking the device around. The data is to be
- * interpreted in groups of 6 where each 6 values corresponds to the X, Y, and Z
- * readings from the base and lid accelerometers in this order.
- */
-extern const float kAccelerometerVerticalHingeTestData[];
-extern const size_t kAccelerometerVerticalHingeTestDataLength;
-extern const float kAccelerometerVerticalHingeUnstableTestData[];
-extern const size_t kAccelerometerVerticalHingeUnstableTestDataLength;
-#endif  /* __CROS_EC_MOTION_COMMON_H */
diff --git a/test/motion_lid.c b/test/motion_lid.c
deleted file mode 100644
index 9935767a68..0000000000
--- a/test/motion_lid.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test motion sense code.
- */
-
-#include <math.h>
-#include <stdio.h>
-
-#include "accelgyro.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "motion_lid.h"
-#include "motion_sense.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-extern enum chipset_state_mask sensor_active;
-extern int wait_us;
-
-/*
- * Period in us for the motion task period.
- * The task will read the vectors at that interval
- */
-#define TEST_LID_EC_RATE (10 * MSEC)
-
-/*
- * Time in us to wait for the task to read the vectors.
- */
-#define TEST_LID_SLEEP_RATE (TEST_LID_EC_RATE / 5)
-#define ONE_G_MEASURED (1 << 14)
-
-/*****************************************************************************/
-/* Mock functions */
-static int accel_init(struct motion_sensor_t *s)
-{
-	return EC_SUCCESS;
-}
-
-static int accel_read(const struct motion_sensor_t *s, intv3_t v)
-{
-	rotate(s->xyz, *s->rot_standard_ref, v);
-	return EC_SUCCESS;
-}
-
-static int accel_set_range(struct motion_sensor_t *s,
-			   const int range,
-			   const int rnd)
-{
-	s->current_range = range;
-	return EC_SUCCESS;
-}
-
-static int accel_get_resolution(const struct motion_sensor_t *s)
-{
-	return 0;
-}
-
-int test_data_rate[2] = { 0 };
-
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
-{
-	test_data_rate[s - motion_sensors] = rate;
-	return EC_SUCCESS;
-}
-
-static int accel_get_data_rate(const struct motion_sensor_t *s)
-{
-	return test_data_rate[s - motion_sensors];
-}
-
-const struct accelgyro_drv test_motion_sense = {
-	.init = accel_init,
-	.read = accel_read,
-	.set_range = accel_set_range,
-	.get_resolution = accel_get_resolution,
-	.set_data_rate = accel_set_data_rate,
-	.get_data_rate = accel_get_data_rate,
-};
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE] = {
-		.name = "base",
-		.active_mask = SENSOR_ACTIVE_S0_S3_S5,
-		.chip = MOTIONSENSE_CHIP_LSM6DS0,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &test_motion_sense,
-		.rot_standard_ref = NULL,
-		.default_range = MOTION_SCALING_FACTOR / ONE_G_MEASURED,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 119000 | ROUND_UP_FLAG,
-				.ec_rate = TEST_LID_EC_RATE
-			},
-			/* Used for double tap */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 119000 | ROUND_UP_FLAG,
-				.ec_rate = TEST_LID_EC_RATE * 100,
-			},
-		},
-	},
-	[LID] = {
-		.name = "lid",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_KXCJ9,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &test_motion_sense,
-		.rot_standard_ref = NULL,
-		.default_range = MOTION_SCALING_FACTOR / ONE_G_MEASURED,
-		.config = {
-			/* EC use accel for angle detection */
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 119000 | ROUND_UP_FLAG,
-				.ec_rate = TEST_LID_EC_RATE,
-			},
-			/* Used for double tap */
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 200000 | ROUND_UP_FLAG,
-				.ec_rate = TEST_LID_EC_RATE * 100,
-			},
-		},
-	},
-};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-/*****************************************************************************/
-/* Test utilities */
-static void wait_for_valid_sample(void)
-{
-	uint8_t sample;
-	uint8_t *lpc_status = host_get_memmap(EC_MEMMAP_ACC_STATUS);
-
-	sample = *lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
-	usleep(TEST_LID_EC_RATE);
-	while ((*lpc_status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK) == sample)
-		usleep(TEST_LID_SLEEP_RATE);
-}
-
-static int test_lid_angle(void)
-{
-
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	int lid_angle;
-
-	/* We don't have TASK_CHIP so simulate init ourselves */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	/* Wait for the sensor task to start */
-	msleep(50);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
-	TEST_ASSERT(accel_get_data_rate(lid) == 0);
-	TEST_ASSERT(base->collection_rate == 0);
-	TEST_ASSERT(lid->collection_rate == 0);
-	TEST_ASSERT(wait_us == -1);
-
-	/* Go to S0 state */
-	hook_notify(HOOK_CHIPSET_SUSPEND);
-	hook_notify(HOOK_CHIPSET_RESUME);
-	msleep(50);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S0);
-	TEST_ASSERT(accel_get_data_rate(lid) == 119000);
-	TEST_ASSERT(base->collection_rate != 0);
-	TEST_ASSERT(lid->collection_rate != 0);
-	TEST_ASSERT(wait_us > 0);
-
-	/*
-	 * Set the base accelerometer as if it were sitting flat on a desk
-	 * and set the lid to closed.
-	 */
-	base->xyz[X] = 0;
-	base->xyz[Y] = 0;
-	base->xyz[Z] = ONE_G_MEASURED;
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = 0;
-	lid->xyz[Z] = -ONE_G_MEASURED;
-	gpio_set_level(GPIO_LID_OPEN, 0);
-
-	wait_for_valid_sample();
-	lid_angle = motion_lid_get_angle();
-	cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-			lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-			base->xyz[X], base->xyz[Y], base->xyz[Z],
-			lid_angle);
-	TEST_ASSERT(lid_angle == 0);
-
-	/* Set lid open to 90 degrees. */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = ONE_G_MEASURED;
-	lid->xyz[Z] = 0;
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(100);
-	wait_for_valid_sample();
-
-	TEST_ASSERT(motion_lid_get_angle() == 90);
-
-	/* Set lid open to 225. */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = -1 * ONE_G_MEASURED * 0.707106;
-	lid->xyz[Z] = ONE_G_MEASURED * 0.707106;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 225);
-
-	/* Set lid open to 350 */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = -1 * ONE_G_MEASURED * 0.1736;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 350);
-
-	/*
-	 * Set lid open to 10.  Since the lid switch still indicates that it's
-	 * open, we should be getting an unreliable reading.
-	 */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = ONE_G_MEASURED * 0.1736;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
-
-	/* Rotate back to 180 and then 10 */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = 0;
-	lid->xyz[Z] = ONE_G_MEASURED;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 180);
-
-	/*
-	 * Again, since the lid isn't closed, the angle should be unreliable.
-	 * See SMALL_LID_ANGLE_RANGE.
-	 */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = ONE_G_MEASURED * 0.1736;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
-
-	/*
-	 * Align base with hinge and make sure it returns unreliable for angle.
-	 * In this test it doesn't matter what the lid acceleration vector is.
-	 */
-	base->xyz[X] = ONE_G_MEASURED;
-	base->xyz[Y] = 0;
-	base->xyz[Z] = 0;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
-
-	/*
-	 * Use all three axes and set lid to negative base and make sure
-	 * angle is 180.
-	 */
-	base->xyz[X] = 5296;
-	base->xyz[Y] = 7856;
-	base->xyz[Z] = 13712;
-	lid->xyz[X] = 5296;
-	lid->xyz[Y] = 7856;
-	lid->xyz[Z] = 13712;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 180);
-
-	/*
-	 * Close the lid and set the angle to 0.
-	 */
-	base->xyz[X] = 0;
-	base->xyz[Y] = 0;
-	base->xyz[Z] = ONE_G_MEASURED;
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = 0;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED;
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(100);
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 0);
-
-	/*
-	 * Make the angle large, but since the lid is closed, the angle should
-	 * be regarded as unreliable.
-	 */
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = -1 * ONE_G_MEASURED * 0.1736;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == LID_ANGLE_UNRELIABLE);
-
-	/*
-	 * Open the lid to 350, and then close the lid and set the angle
-	 * to 10. The reading of small angle shouldn't be corrected.
-	 */
-	gpio_set_level(GPIO_LID_OPEN, 1);
-	msleep(100);
-	gpio_set_level(GPIO_LID_OPEN, 0);
-	msleep(100);
-	lid->xyz[X] = 0;
-	lid->xyz[Y] = ONE_G_MEASURED * 0.1736;
-	lid->xyz[Z] = -1 * ONE_G_MEASURED * 0.9848;
-	wait_for_valid_sample();
-	TEST_ASSERT(motion_lid_get_angle() == 10);
-
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	msleep(1000);
-	TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S5);
-	/* Base ODR is 0, collection rate is 0. */
-	TEST_ASSERT(base->collection_rate == 0);
-	/* Lid is powered off, collection rate is 0. */
-	TEST_ASSERT(lid->collection_rate == 0);
-	TEST_ASSERT(wait_us == -1);
-
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_lid_angle);
-
-	test_print_result();
-}
diff --git a/test/motion_lid.tasklist b/test/motion_lid.tasklist
deleted file mode 100644
index 0b774ebb4a..0000000000
--- a/test/motion_lid.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  \
-  TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/motion_sense_fifo.c b/test/motion_sense_fifo.c
deleted file mode 100644
index b20eb9a36f..0000000000
--- a/test/motion_sense_fifo.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test motion_sense_fifo.
- */
-
-#include "stdio.h"
-#include "motion_sense_fifo.h"
-#include "test_util.h"
-#include "util.h"
-#include "hwtimer.h"
-#include "timer.h"
-#include "accelgyro.h"
-#include <sys/types.h>
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE] = {},
-	[LID] = {},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-uint32_t mkbp_last_event_time;
-
-static struct ec_response_motion_sensor_data data[CONFIG_ACCEL_FIFO_SIZE];
-static uint16_t data_bytes_read;
-
-static int test_insert_async_event(void)
-{
-	int read_count;
-
-	motion_sense_fifo_insert_async_event(motion_sensors, ASYNC_EVENT_FLUSH);
-	motion_sense_fifo_insert_async_event(motion_sensors + 1,
-					     ASYNC_EVENT_ODR);
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 2, "%d");
-	TEST_EQ(data_bytes_read,
-		(int)(2 * sizeof(struct ec_response_motion_sensor_data)), "%d");
-
-	TEST_BITS_SET(data[0].flags, ASYNC_EVENT_FLUSH);
-	TEST_BITS_CLEARED(data[0].flags, MOTIONSENSE_SENSOR_FLAG_ODR);
-	TEST_EQ(data[0].sensor_num, 0, "%d");
-
-	TEST_BITS_SET(data[1].flags, ASYNC_EVENT_ODR);
-	TEST_BITS_CLEARED(data[1].flags, MOTIONSENSE_SENSOR_FLAG_FLUSH);
-	TEST_EQ(data[1].sensor_num, 1, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_wake_up_needed(void)
-{
-	data[0].flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP;
-
-	motion_sense_fifo_stage_data(data, motion_sensors, 0, 100);
-	TEST_EQ(motion_sense_fifo_wake_up_needed(), 0, "%d");
-
-	motion_sense_fifo_commit_data();
-	TEST_EQ(motion_sense_fifo_wake_up_needed(), 1, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_wake_up_needed_overflow(void)
-{
-	int i;
-
-	data[0].flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP;
-	motion_sense_fifo_stage_data(data, motion_sensors, 0, 100);
-
-	data[0].flags = 0;
-	/*
-	 * Using CONFIG_ACCEL_FIFO_SIZE / 2 since 2 entries are inserted per
-	 * 'data':
-	 * - a timestamp
-	 * - the data
-	 */
-	for (i = 0; i < (CONFIG_ACCEL_FIFO_SIZE / 2); i++)
-		motion_sense_fifo_stage_data(data, motion_sensors, 0, 101 + i);
-
-	TEST_EQ(motion_sense_fifo_wake_up_needed(), 1, "%d");
-	return EC_SUCCESS;
-}
-
-static int test_adding_timestamp(void)
-{
-	int read_count;
-
-	motion_sense_fifo_add_timestamp(100);
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-
-	TEST_EQ(read_count, 1, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, 100, "%u");
-	return EC_SUCCESS;
-}
-
-static int test_stage_data_sets_xyz(void)
-{
-	motion_sensors->oversampling_ratio = 1;
-	motion_sensors->oversampling = 0;
-	data->data[0] = 1;
-	data->data[1] = 2;
-	data->data[2] = 3;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 100);
-
-	TEST_EQ(motion_sensors->xyz[0], 1, "%d");
-	TEST_EQ(motion_sensors->xyz[1], 2, "%d");
-	TEST_EQ(motion_sensors->xyz[2], 3, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_stage_data_removed_oversample(void)
-{
-	int read_count;
-
-	motion_sensors->oversampling_ratio = 2;
-	motion_sensors->oversampling = 0;
-	data->data[0] = 1;
-	data->data[1] = 2;
-	data->data[2] = 3;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 100);
-
-	data->data[0] = 4;
-	data->data[1] = 5;
-	data->data[2] = 6;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 110);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 3, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, 100, "%u");
-	TEST_BITS_CLEARED(data[1].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[1].data[0], 1, "%d");
-	TEST_EQ(data[1].data[1], 2, "%d");
-	TEST_EQ(data[1].data[2], 3, "%d");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, 110, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_stage_data_remove_all_oversampling(void)
-{
-	int read_count;
-
-	motion_sensors->oversampling_ratio = 0;
-	motion_sensors->oversampling = 0;
-	data->data[0] = 1;
-	data->data[1] = 2;
-	data->data[2] = 3;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 100);
-
-	data->data[0] = 4;
-	data->data[1] = 5;
-	data->data[2] = 6;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 110);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 2, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, 100, "%u");
-	TEST_BITS_SET(data[1].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[1].timestamp, 110, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_stage_data_evicts_data_with_timestamp(void)
-{
-	int i, read_count;
-
-	/* Fill the fifo */
-	motion_sensors->oversampling_ratio = 1;
-	for (i = 0; i < CONFIG_ACCEL_FIFO_SIZE / 2; i++)
-		motion_sense_fifo_stage_data(data, motion_sensors, 3, i * 100);
-
-	/* Add a single entry (should evict 2) */
-	motion_sense_fifo_add_timestamp(CONFIG_ACCEL_FIFO_SIZE * 100);
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, CONFIG_ACCEL_FIFO_SIZE - 1, "%d");
-	TEST_BITS_SET(data->flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data->timestamp, 100, "%u");
-	TEST_BITS_SET(data[CONFIG_ACCEL_FIFO_SIZE - 2].flags,
-		      MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[CONFIG_ACCEL_FIFO_SIZE - 2].timestamp,
-		CONFIG_ACCEL_FIFO_SIZE * 100, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_add_data_no_spreading_when_different_sensors(void)
-{
-	int read_count;
-	uint32_t now = __hw_clock_source_read();
-
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[1].oversampling_ratio = 1;
-
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now);
-	motion_sense_fifo_stage_data(data, motion_sensors + 1, 3, now);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_add_data_no_spreading_different_timestamps(void)
-{
-	int read_count;
-
-	motion_sensors[0].oversampling_ratio = 1;
-
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 100);
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, 120);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, 100, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, 120, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_spread_data_in_window(void)
-{
-	uint32_t now;
-	int read_count;
-
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
-	now = __hw_clock_source_read();
-
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18);
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18);
-	motion_sense_fifo_commit_data();
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 18, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	/* TODO(b/142892004): mock __hw_clock_source_read so we can check for
-	 * exact TS.
-	 */
-	TEST_NEAR(data[2].timestamp, now, 2, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_spread_data_by_collection_rate(void)
-{
-	const uint32_t now = __hw_clock_source_read();
-	int read_count;
-
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_commit_data();
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 25, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 5, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_spread_double_commit_same_timestamp(void)
-{
-	const uint32_t now = __hw_clock_source_read();
-	int read_count;
-
-	/*
-	 * Stage and commit the same sample. This is not expected to happen
-	 * since batches of sensor samples should be staged together and only
-	 * commit once. We assume that the driver did this on purpose and will
-	 * allow the same timestamp to be sent.
-	 */
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_commit_data();
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 25, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 25, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_commit_non_data_or_timestamp_entries(void)
-{
-	const uint32_t now = __hw_clock_source_read();
-	int read_count;
-
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
-
-	/* Insert non-data entry */
-	data[0].flags = MOTIONSENSE_SENSOR_FLAG_ODR;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-
-	/* Insert data entry */
-	data[0].flags = 0;
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-
-	motion_sense_fifo_commit_data();
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 25, "%u");
-	TEST_BITS_SET(data[1].flags, MOTIONSENSE_SENSOR_FLAG_ODR);
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 25, "%u");
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	motion_sense_fifo_commit_data();
-	motion_sense_fifo_read(sizeof(data), CONFIG_ACCEL_FIFO_SIZE, &data,
-			       &data_bytes_read);
-	motion_sense_fifo_reset_needed_flags();
-	memset(data, 0, sizeof(data));
-	motion_sense_fifo_reset();
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-	motion_sense_fifo_init();
-
-	RUN_TEST(test_insert_async_event);
-	RUN_TEST(test_wake_up_needed);
-	RUN_TEST(test_wake_up_needed_overflow);
-	RUN_TEST(test_adding_timestamp);
-	RUN_TEST(test_stage_data_sets_xyz);
-	RUN_TEST(test_stage_data_removed_oversample);
-	RUN_TEST(test_stage_data_remove_all_oversampling);
-	RUN_TEST(test_stage_data_evicts_data_with_timestamp);
-	RUN_TEST(test_add_data_no_spreading_when_different_sensors);
-	RUN_TEST(test_add_data_no_spreading_different_timestamps);
-	RUN_TEST(test_spread_data_in_window);
-	RUN_TEST(test_spread_data_by_collection_rate);
-	RUN_TEST(test_spread_double_commit_same_timestamp);
-	RUN_TEST(test_commit_non_data_or_timestamp_entries);
-
-	test_print_result();
-}
diff --git a/test/motion_sense_fifo.tasklist b/test/motion_sense_fifo.tasklist
deleted file mode 100644
index 0e3696c3f0..0000000000
--- a/test/motion_sense_fifo.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/mpu.c b/test/mpu.c
deleted file mode 100644
index 25b2c58903..0000000000
--- a/test/mpu.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-#include "mpu.h"
-#include "mpu_private.h"
-#include "string.h"
-#include "system.h"
-#include "test_util.h"
-
-struct mpu_info {
-	bool has_mpu;
-	int num_mpu_regions;
-	bool mpu_is_unified;
-};
-
-#if defined(CHIP_VARIANT_STM32F412)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 8,
-	.mpu_is_unified = true
-};
-
-struct mpu_rw_regions expected_rw_regions = { .num_regions = 2,
-					      .addr = { 0x08060000,
-							0x08080000 },
-					      .size = { 0x20000, 0x80000 } };
-#elif defined(CHIP_VARIANT_STM32H7X3)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 16,
-	.mpu_is_unified = true
-};
-
-struct mpu_rw_regions expected_rw_regions = { .num_regions = 1,
-					      .addr = { 0x08100000,
-							0x08200000 },
-					      .size = { 0x100000, 0 } };
-#else
-#error "MPU info not defined for this chip. Please add it."
-#endif
-
-test_static int test_mpu_info(void)
-{
-	TEST_EQ(mpu_num_regions(), mpu_info.num_mpu_regions, "%d");
-	TEST_EQ(has_mpu(), mpu_info.has_mpu, "%d");
-	TEST_EQ(mpu_is_unified(), mpu_info.mpu_is_unified, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int reset_mpu(void)
-{
-	int i;
-
-	mpu_disable();
-
-	for (i = 0; i < mpu_info.num_mpu_regions; ++i) {
-		/*
-		 * Disable all regions.
-		 *
-		 * We use the smallest possible size (32 bytes), but it
-		 * doesn't really matter since the regions are disabled.
-		 */
-		TEST_EQ(mpu_config_region(i, 0, 32, 0, 0), EC_SUCCESS, "%d");
-	}
-
-	mpu_enable();
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_update_region_valid_region(void)
-{
-	volatile char data __maybe_unused;
-
-	char * const ram_base = (char * const)CONFIG_RAM_BASE;
-	const uint8_t size_bit = 5;
-	uint16_t mpu_attr = MPU_ATTR_NO_NO;
-
-	/*
-	 * Initial read should work. MPU is not protecting the given address.
-	 */
-	data = ram_base[0];
-
-	TEST_EQ(mpu_update_region(0, (uint32_t)ram_base, size_bit, mpu_attr, 1,
-				  0),
-		EC_SUCCESS, "%d");
-
-	/* This panics with a data violation at CONFIG_RAM_BASE:
-	 *
-	 * Data access violation, mfar = <CONFIG_RAM_BASE>
-	 */
-	data = ram_base[0];
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_update_region_invalid_region(void)
-{
-	/* Test invalid region */
-	TEST_EQ(mpu_update_region(mpu_info.num_mpu_regions, 0x8020000, 17,
-				  0x1000, 1, 0),
-		-EC_ERROR_INVAL, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_update_region_invalid_alignment(void)
-{
-	/*
-	 * Test size that is not aligned to address.
-	 */
-	const uint32_t addr = 0x20000;
-	const uint32_t size = 0x40000;
-	const uint32_t size_bit = 18;
-
-	TEST_EQ(size, BIT(size_bit), "%d");
-	TEST_EQ(reset_mpu(), EC_SUCCESS, "%d");
-	TEST_EQ(mpu_update_region(0, addr, size_bit, 0, 1, 0), -EC_ERROR_INVAL,
-		"%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_lock_ro_flash(void)
-{
-	int rv;
-
-	rv = mpu_lock_ro_flash();
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_lock_rw_flash(void)
-{
-	int rv;
-
-	rv = mpu_lock_rw_flash();
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_protect_data_ram(void)
-{
-	int rv;
-
-	rv = mpu_protect_data_ram();
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_protect_code_ram(void)
-{
-	if (IS_ENABLED(CONFIG_EXTERNAL_STORAGE) ||
-	    !IS_ENABLED(CONFIG_FLASH_PHYSICAL)) {
-		int rv;
-
-		rv = mpu_protect_code_ram();
-		TEST_EQ(rv, EC_SUCCESS, "%d");
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_mpu_get_rw_regions(void)
-{
-	struct mpu_rw_regions rw_regions = mpu_get_rw_regions();
-	int rv = memcmp(&rw_regions, &expected_rw_regions,
-			sizeof(expected_rw_regions));
-
-	TEST_EQ(rv, 0, "%d");
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	enum ec_image cur_image = system_get_image_copy();
-
-	ccprintf("Running MPU test\n");
-
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_info);
-
-	/*
-	 * TODO(b/151105339): For all locked regions, check that we cannot
-	 * read/write/execute (depending on the configuration).
-	 */
-
-	/*
-	 * Since locking prevents code execution, we can only lock the region
-	 * that is not running or the test will hang.
-	 */
-	if (cur_image == EC_IMAGE_RW) {
-		RUN_TEST(reset_mpu);
-		RUN_TEST(test_mpu_lock_ro_flash);
-	}
-
-	if (cur_image == EC_IMAGE_RO) {
-		RUN_TEST(reset_mpu);
-		RUN_TEST(test_mpu_lock_rw_flash);
-	}
-
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_update_region_invalid_region);
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_update_region_invalid_alignment);
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_protect_code_ram);
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_protect_data_ram);
-	RUN_TEST(reset_mpu);
-	RUN_TEST(test_mpu_get_rw_regions);
-	RUN_TEST(reset_mpu);
-	/* This test must be last because it generates a panic */
-	RUN_TEST(test_mpu_update_region_valid_region);
-	RUN_TEST(reset_mpu);
-	test_print_result();
-}
diff --git a/test/mpu.tasklist b/test/mpu.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/mpu.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/mutex.c b/test/mutex.c
deleted file mode 100644
index 4fbf7d5cae..0000000000
--- a/test/mutex.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- * Copyright 2011 Google Inc.
- *
- * Tasks for mutexes basic tests.
- */
-
-#include "console.h"
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static struct mutex mtx;
-
-/* period between 50us and 3.2ms */
-#define PERIOD_US(num) (((num % 64) + 1) * 50)
-/* one of the 3 MTX3x tasks */
-#define RANDOM_TASK(num) (TASK_ID_MTX3C + (num % 3))
-
-int mutex_random_task(void *unused)
-{
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
-	/* wait to be activated */
-
-	while (1) {
-		task_wait_event(0);
-		ccprintf("%c+\n", letter);
-		mutex_lock(&mtx);
-		ccprintf("%c=\n", letter);
-		task_wait_event(0);
-		ccprintf("%c-\n", letter);
-		mutex_unlock(&mtx);
-	}
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-int mutex_second_task(void *unused)
-{
-	task_id_t id = task_get_current();
-
-	ccprintf("\n[Mutex second task %d]\n", id);
-
-	task_wait_event(0);
-	ccprintf("MTX2: locking...");
-	mutex_lock(&mtx);
-	ccprintf("done\n");
-	task_wake(TASK_ID_MTX1);
-	ccprintf("MTX2: unlocking...\n");
-	mutex_unlock(&mtx);
-
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-int mutex_main_task(void *unused)
-{
-	task_id_t id = task_get_current();
-	uint32_t rdelay = (uint32_t)0x0bad1dea;
-	uint32_t rtask = (uint32_t)0x1a4e1dea;
-	int i;
-
-	ccprintf("\n[Mutex main task %d]\n", id);
-
-	task_wait_event(0);
-
-	/* --- Lock/Unlock without contention --- */
-	ccprintf("No contention :");
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	mutex_lock(&mtx);
-	mutex_unlock(&mtx);
-	ccprintf("done.\n");
-
-	/* --- Serialization to test simple contention --- */
-	ccprintf("Simple contention :\n");
-	/* lock the mutex from the other task */
-	task_set_event(TASK_ID_MTX2, TASK_EVENT_WAKE);
-	task_wait_event(0);
-	/* block on the mutex */
-	ccprintf("MTX1: blocking...\n");
-	mutex_lock(&mtx);
-	ccprintf("MTX1: get lock\n");
-	mutex_unlock(&mtx);
-
-	/* --- mass lock-unlocking from several tasks --- */
-	ccprintf("Massive locking/unlocking :\n");
-	for (i = 0; i < 500; i++) {
-		/* Wake up a random task */
-		task_wake(RANDOM_TASK(rtask));
-		/* next pseudo random delay */
-		rtask = prng(rtask);
-		/* Wait for a "random" period */
-		task_wait_event(PERIOD_US(rdelay));
-		/* next pseudo random delay */
-		rdelay = prng(rdelay);
-	}
-
-	test_pass();
-	task_wait_event(0);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	wait_for_task_started();
-	task_wake(TASK_ID_MTX1);
-}
diff --git a/test/mutex.tasklist b/test/mutex.tasklist
deleted file mode 100644
index 8e3d08ddc2..0000000000
--- a/test/mutex.tasklist
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(MTX3C, mutex_random_task, NULL, 384) \
-  TASK_TEST(MTX3B, mutex_random_task, NULL, 384) \
-  TASK_TEST(MTX3A, mutex_random_task, NULL, 384) \
-  TASK_TEST(MTX2, mutex_second_task, NULL, 384) \
-  TASK_TEST(MTX1, mutex_main_task, NULL, 384)
diff --git a/test/newton_fit.c b/test/newton_fit.c
deleted file mode 100644
index 9648fbfd9a..0000000000
--- a/test/newton_fit.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "newton_fit.h"
-#include "motion_sense.h"
-#include "test_util.h"
-#include <stdio.h>
-
-/*
- * Need to define motion sensor globals just to compile.
- * We include motion task to force the inclusion of math_util.c
- */
-struct motion_sensor_t motion_sensors[] = {};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-#define ACC(FIT, X, Y, Z, EXPECTED) \
-	TEST_EQ(newton_fit_accumulate(FIT, X, Y, Z), EXPECTED, "%d")
-
-static int test_newton_fit_reset(void)
-{
-	struct newton_fit fit = NEWTON_FIT(4, 15, 0.01f, 0.25f, 1.0e-8f, 100);
-
-	newton_fit_reset(&fit);
-	newton_fit_accumulate(&fit, 1.0f, 0.0f, 0.0f);
-	TEST_EQ(queue_count(fit.orientations), (size_t)1, "%zu");
-	newton_fit_reset(&fit);
-
-	TEST_EQ(queue_count(fit.orientations), (size_t)0, "%zu");
-
-	return EC_SUCCESS;
-}
-
-static int test_newton_fit_accumulate(void)
-{
-	struct newton_fit fit = NEWTON_FIT(4, 15, 0.01f, 0.25f, 1.0e-8f, 100);
-	struct queue_iterator it;
-
-	newton_fit_reset(&fit);
-	newton_fit_accumulate(&fit, 1.0f, 0.0f, 0.0f);
-
-	TEST_EQ(queue_count(fit.orientations), (size_t)1, "%zu");
-	queue_begin(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 1, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_newton_fit_accumulate_merge(void)
-{
-	struct newton_fit fit = NEWTON_FIT(4, 15, 0.01f, 0.25f, 1.0e-8f, 100);
-	struct queue_iterator it;
-
-	newton_fit_reset(&fit);
-	newton_fit_accumulate(&fit, 1.0f, 0.0f, 0.0f);
-	newton_fit_accumulate(&fit, 1.05f, 0.0f, 0.0f);
-
-	TEST_EQ(queue_count(fit.orientations), (size_t)1, "%zu");
-	queue_begin(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 2, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_newton_fit_accumulate_prune(void)
-{
-	struct newton_fit fit = NEWTON_FIT(4, 15, 0.01f, 0.25f, 1.0e-8f, 100);
-	struct queue_iterator it;
-
-	newton_fit_reset(&fit);
-	newton_fit_accumulate(&fit, 1.0f, 0.0f, 0.0f);
-	newton_fit_accumulate(&fit, -1.0f, 0.0f, 0.0f);
-	newton_fit_accumulate(&fit, 0.0f, 1.0f, 0.0f);
-	newton_fit_accumulate(&fit, 0.0f, -1.0f, 0.0f);
-
-	TEST_EQ(queue_is_full(fit.orientations), 1, "%d");
-	queue_begin(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 1, "%u");
-	queue_next(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 1, "%u");
-	queue_next(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 1, "%u");
-	queue_next(fit.orientations, &it);
-	TEST_EQ(((struct newton_fit_orientation *)it.ptr)->nsamples, 1, "%u");
-
-	newton_fit_accumulate(&fit, 0.0f, 0.0f, 1.0f);
-	TEST_EQ(queue_is_full(fit.orientations), 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_newton_fit_calculate(void)
-{
-	struct newton_fit fit = NEWTON_FIT(4, 3, 0.01f, 0.25f, 1.0e-8f, 100);
-	floatv3_t bias;
-	float radius;
-
-	newton_fit_reset(&fit);
-
-	ACC(&fit, 1.01f, 0.01f, 0.01f, false);
-	ACC(&fit, 1.01f, 0.01f, 0.01f, false);
-	ACC(&fit, 1.01f, 0.01f, 0.01f, false);
-
-	ACC(&fit, -0.99f, 0.01f, 0.01f, false);
-	ACC(&fit, -0.99f, 0.01f, 0.01f, false);
-	ACC(&fit, -0.99f, 0.01f, 0.01f, false);
-
-	ACC(&fit, 0.01f, 1.01f, 0.01f, false);
-	ACC(&fit, 0.01f, 1.01f, 0.01f, false);
-	ACC(&fit, 0.01f, 1.01f, 0.01f, false);
-
-	ACC(&fit, 0.01f, 0.01f, 1.01f, false);
-	ACC(&fit, 0.01f, 0.01f, 1.01f, false);
-	ACC(&fit, 0.01f, 0.01f, 1.01f, true);
-
-	fpv3_init(bias, 0.0f, 0.0f, 0.0f);
-	newton_fit_compute(&fit, bias, &radius);
-
-	TEST_NEAR(bias[0], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(bias[1], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(bias[2], 0.01f, 0.0001f, "%f");
-	TEST_NEAR(radius, 1.0f, 0.0001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_newton_fit_reset);
-	RUN_TEST(test_newton_fit_accumulate);
-	RUN_TEST(test_newton_fit_accumulate_merge);
-	RUN_TEST(test_newton_fit_accumulate_prune);
-	RUN_TEST(test_newton_fit_calculate);
-
-	test_print_result();
-}
diff --git a/test/newton_fit.tasklist b/test/newton_fit.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/newton_fit.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/online_calibration.c b/test/online_calibration.c
deleted file mode 100644
index 1b3abf51bc..0000000000
--- a/test/online_calibration.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accel_cal.h"
-#include "accelgyro.h"
-#include "hwtimer.h"
-#include "mag_cal.h"
-#include "online_calibration.h"
-#include "test_util.h"
-#include "timer.h"
-#include <stdio.h>
-
-int mkbp_send_event(uint8_t event_type)
-{
-	return 1;
-}
-
-struct mock_read_temp_result {
-	void *s;
-	int temp;
-	int ret;
-	int used_count;
-	struct mock_read_temp_result *next;
-};
-
-static struct mock_read_temp_result *mock_read_temp_results;
-
-static int mock_read_temp(const struct motion_sensor_t *s, int *temp)
-{
-	struct mock_read_temp_result *ptr = mock_read_temp_results;
-
-	while (ptr) {
-		if (ptr->s == s) {
-			if (ptr->ret == EC_SUCCESS)
-				*temp = ptr->temp;
-			ptr->used_count++;
-			return ptr->ret;
-		}
-		ptr = ptr->next;
-	}
-
-	return EC_ERROR_UNKNOWN;
-}
-
-static struct accelgyro_drv mock_sensor_driver = {
-	.read_temp = mock_read_temp,
-};
-
-static struct accel_cal_algo base_accel_cal_algos[] = {
-	{
-		.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f),
-					 FLOAT_TO_FP(0.25f),
-					 FLOAT_TO_FP(1.0e-8f), 100),
-	}
-};
-
-static struct accel_cal base_accel_cal_data = {
-	.still_det = STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC,
-			       5),
-	.algos = base_accel_cal_algos,
-	.num_temp_windows = ARRAY_SIZE(base_accel_cal_algos),
-};
-
-static struct mag_cal_t lid_mag_cal_data;
-
-static bool next_accel_cal_accumulate_result;
-static fpv3_t next_accel_cal_bias;
-
-bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t sample_time, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
-{
-	if (next_accel_cal_accumulate_result) {
-		cal->bias[X] = next_accel_cal_bias[X];
-		cal->bias[Y] = next_accel_cal_bias[Y];
-		cal->bias[Z] = next_accel_cal_bias[Z];
-	}
-	return next_accel_cal_accumulate_result;
-}
-
-struct motion_sensor_t motion_sensors[] = {
-	[BASE] = {
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.default_range = 4,
-		.drv = &mock_sensor_driver,
-		.online_calib_data[0] = {
-			.type_specific_data = &base_accel_cal_data,
-		},
-	},
-	[LID] = {
-		.type = MOTIONSENSE_TYPE_MAG,
-		.default_range = 4,
-		.drv = &mock_sensor_driver,
-		.online_calib_data[0] = {
-			.type_specific_data = &lid_mag_cal_data,
-		}
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int test_read_temp_on_stage(void)
-{
-	struct mock_read_temp_result expected = { &motion_sensors[BASE], 200,
-						  EC_SUCCESS, 0, NULL };
-	struct ec_response_motion_sensor_data data;
-	int rc;
-
-	mock_read_temp_results = &expected;
-	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
-
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-	TEST_EQ(expected.used_count, 1, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_read_temp_from_cache_on_stage(void)
-{
-	struct mock_read_temp_result expected = { &motion_sensors[BASE], 200,
-						  EC_SUCCESS, 0, NULL };
-	struct ec_response_motion_sensor_data data;
-	int rc;
-
-	mock_read_temp_results = &expected;
-	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-
-	TEST_EQ(expected.used_count, 1, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_read_temp_twice_after_cache_stale(void)
-{
-	struct mock_read_temp_result expected = { &motion_sensors[BASE], 200,
-						  EC_SUCCESS, 0, NULL };
-	struct ec_response_motion_sensor_data data;
-	int rc;
-
-	mock_read_temp_results = &expected;
-	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-
-	sleep(2);
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-
-	TEST_EQ(expected.used_count, 2, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_new_calibration_value(void)
-{
-	struct mock_read_temp_result expected = { &motion_sensors[BASE], 200,
-						  EC_SUCCESS, 0, NULL };
-	struct ec_response_motion_sensor_data data;
-	struct ec_response_online_calibration_data cal_data;
-	int rc;
-
-	mock_read_temp_results = &expected;
-	next_accel_cal_accumulate_result = false;
-	data.sensor_num = BASE;
-
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-	TEST_EQ(online_calibration_has_new_values(), false, "%d");
-
-	next_accel_cal_accumulate_result = true;
-	next_accel_cal_bias[X] = 0.01f;		/* expect:  81  */
-	next_accel_cal_bias[Y] = -0.02f;	/* expect: -163 */
-	next_accel_cal_bias[Z] = 0;		/* expect:    0 */
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-	TEST_EQ(online_calibration_has_new_values(), true, "%d");
-
-	rc = online_calibration_read(&motion_sensors[BASE], &cal_data);
-	TEST_EQ(rc, true, "%d");
-	TEST_EQ(cal_data.data[X], 81, "%d");
-	TEST_EQ(cal_data.data[Y], -163, "%d");
-	TEST_EQ(cal_data.data[Z], 0, "%d");
-
-	TEST_EQ(online_calibration_has_new_values(), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-int test_mag_reading_updated_cal(void)
-{
-	struct mag_cal_t expected_results;
-	struct ec_response_motion_sensor_data data;
-	int rc;
-	int test_values[] = { 207, -17, -37 };
-
-	data.sensor_num = LID;
-	data.data[X] = test_values[X];
-	data.data[Y] = test_values[Y];
-	data.data[Z] = test_values[Z];
-
-	init_mag_cal(&expected_results);
-	mag_cal_update(&expected_results, test_values);
-
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[LID], __hw_clock_source_read());
-	TEST_EQ(rc, EC_SUCCESS, "%d");
-	TEST_EQ(expected_results.kasa_fit.nsamples,
-		lid_mag_cal_data.kasa_fit.nsamples, "%d");
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	mock_read_temp_results = NULL;
-	online_calibration_init();
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_read_temp_on_stage);
-	RUN_TEST(test_read_temp_from_cache_on_stage);
-	RUN_TEST(test_read_temp_twice_after_cache_stale);
-	RUN_TEST(test_new_calibration_value);
-	RUN_TEST(test_mag_reading_updated_cal);
-
-	test_print_result();
-}
diff --git a/test/online_calibration.tasklist b/test/online_calibration.tasklist
deleted file mode 100644
index 5b67239ff8..0000000000
--- a/test/online_calibration.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
-
diff --git a/test/online_calibration_spoof.c b/test/online_calibration_spoof.c
deleted file mode 100644
index 66ef5d01de..0000000000
--- a/test/online_calibration_spoof.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accel_cal.h"
-#include "accelgyro.h"
-#include "hwtimer.h"
-#include "mag_cal.h"
-#include "online_calibration.h"
-#include "test_util.h"
-#include "gyro_cal_init_for_test.h"
-#include "gyro_cal.h"
-#include "timer.h"
-#include <stdio.h>
-
-int mkbp_send_event(uint8_t event_type)
-{
-	return 1;
-}
-
-/*
- * Mocked driver (can be re-used for all sensors).
- */
-
-static int mock_read_temp(const struct motion_sensor_t *s, int *temp)
-{
-	if (temp)
-		*temp = 200;
-	return EC_SUCCESS;
-}
-
-static struct accelgyro_drv mock_sensor_driver = {
-	.read_temp = mock_read_temp,
-};
-
-/*
- * Accelerometer, magnetometer, and gyroscope data structs.
- */
-
-static struct accel_cal_algo accel_cal_algos[] = { {
-	.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), FLOAT_TO_FP(0.25f),
-				 FLOAT_TO_FP(1.0e-8f), 100),
-} };
-
-static struct accel_cal accel_cal_data = {
-	.still_det =
-		STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, 5),
-	.algos = accel_cal_algos,
-	.num_temp_windows = ARRAY_SIZE(accel_cal_algos),
-};
-
-static struct mag_cal_t mag_cal_data;
-
-static struct gyro_cal gyro_cal_data;
-
-/*
- * Motion sensor array and count.
- */
-
-struct motion_sensor_t motion_sensors[] = {
-	{
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.default_range = 4,
-		.drv = &mock_sensor_driver,
-		.online_calib_data[0] = {
-			.type_specific_data = &accel_cal_data,
-		},
-	},
-	{
-		.type = MOTIONSENSE_TYPE_MAG,
-		.default_range = 4,
-		.drv = &mock_sensor_driver,
-		.online_calib_data[0] = {
-			.type_specific_data = &mag_cal_data,
-		},
-	},
-	{
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.default_range = 4,
-		.drv = &mock_sensor_driver,
-		.online_calib_data[0] = {
-			.type_specific_data = &gyro_cal_data,
-		},
-	},
-};
-
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static void spoof_sensor_data(struct motion_sensor_t *s, int x, int y, int z)
-{
-	struct ec_response_motion_sensor_data data;
-	uint32_t timestamp = 0;
-
-	/* Set the data and flags. */
-	data.data[X] = x;
-	data.data[Y] = y;
-	data.data[Z] = z;
-	s->flags |= MOTIONSENSE_FLAG_IN_SPOOF_MODE;
-
-	/* Pass the data to online_calibdation. */
-	online_calibration_process_data(&data, s, timestamp);
-}
-
-/*
- * Begin testing.
- */
-
-static int test_accel_calibration_on_spoof(void)
-{
-	struct ec_response_online_calibration_data out;
-
-	/* Send spoof data (1, 2, 3). */
-	spoof_sensor_data(&motion_sensors[0], 1, 2, 3);
-
-	/* Check that we have new values. */
-	TEST_ASSERT(online_calibration_has_new_values());
-
-	/* Get the new values for sensor 0. */
-	TEST_ASSERT(online_calibration_read(&motion_sensors[0], &out));
-
-	/* Validate the new values. */
-	TEST_EQ(out.data[X], 1, "%d");
-	TEST_EQ(out.data[Y], 2, "%d");
-	TEST_EQ(out.data[Z], 3, "%d");
-
-	/* Validate that no other sensors have data. */
-	TEST_ASSERT(!online_calibration_has_new_values());
-
-	return EC_SUCCESS;
-}
-
-static int test_mag_calibration_on_spoof(void)
-{
-	struct ec_response_online_calibration_data out;
-
-	/* Send spoof data (4, 5, 6). */
-	spoof_sensor_data(&motion_sensors[1], 4, 5, 6);
-
-	/* Check that we have new values. */
-	TEST_ASSERT(online_calibration_has_new_values());
-
-	/* Get the new values for sensor 0. */
-	TEST_ASSERT(online_calibration_read(&motion_sensors[1], &out));
-
-	/* Validate the new values. */
-	TEST_EQ(out.data[X], 4, "%d");
-	TEST_EQ(out.data[Y], 5, "%d");
-	TEST_EQ(out.data[Z], 6, "%d");
-
-	/* Validate that no other sensors have data. */
-	TEST_ASSERT(!online_calibration_has_new_values());
-
-	return EC_SUCCESS;
-}
-
-static int test_gyro_calibration_on_spoof(void)
-{
-	struct ec_response_online_calibration_data out;
-
-	/* Send spoof data (7, 8, 9). */
-	spoof_sensor_data(&motion_sensors[2], 7, 8, 9);
-
-	/* Check that we have new values. */
-	TEST_ASSERT(online_calibration_has_new_values());
-
-	/* Get the new values for sensor 0. */
-	TEST_ASSERT(online_calibration_read(&motion_sensors[2], &out));
-
-	/* Validate the new values. */
-	TEST_EQ(out.data[X], 7, "%d");
-	TEST_EQ(out.data[Y], 8, "%d");
-	TEST_EQ(out.data[Z], 9, "%d");
-
-	/* Validate that no other sensors have data. */
-	TEST_ASSERT(!online_calibration_has_new_values());
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	online_calibration_init();
-	gyro_cal_initialization_for_test(&gyro_cal_data);
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_accel_calibration_on_spoof);
-	RUN_TEST(test_mag_calibration_on_spoof);
-	RUN_TEST(test_gyro_calibration_on_spoof);
-
-	test_print_result();
-}
diff --git a/test/online_calibration_spoof.tasklist b/test/online_calibration_spoof.tasklist
deleted file mode 100644
index 7d28eb5b64..0000000000
--- a/test/online_calibration_spoof.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(MOTIONSENSE, motion_sense_task, NULL, TASK_STACK_SIZE)
diff --git a/test/pingpong.c b/test/pingpong.c
deleted file mode 100644
index 9d3a7ed7af..0000000000
--- a/test/pingpong.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tasks for scheduling test.
- */
-
-#include "common.h"
-#include "console.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#define TEST_COUNT 3000
-
-static int wake_count[3];
-
-int task_abc(void *data)
-{
-	int myid = task_get_current() - TASK_ID_TESTA;
-	task_id_t next = task_get_current() + 1;
-	if (next > TASK_ID_TESTC)
-		next = TASK_ID_TESTA;
-
-	task_wait_event(-1);
-
-	ccprintf("\n[starting Task %c]\n", ('A' + myid));
-
-	while (1) {
-		wake_count[myid]++;
-		if (myid == 2 && wake_count[myid] == TEST_COUNT) {
-			if (wake_count[0] == TEST_COUNT &&
-			    wake_count[1] == TEST_COUNT)
-				test_pass();
-			else
-				test_fail();
-			wake_count[0] = wake_count[1] = wake_count[2] = 0;
-			task_wait_event(-1);
-		} else {
-			task_set_event(next, TASK_EVENT_WAKE);
-			task_wait_event(-1);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int task_tick(void *data)
-{
-	task_wait_event(-1);
-	ccprintf("\n[starting Task T]\n");
-
-	/* Wake up every tick */
-	while (1) {
-		/* Wait for timer interrupt message */
-		usleep(3000);
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	wait_for_task_started();
-	task_wake(TASK_ID_TICK);
-	task_wake(TASK_ID_TESTA);
-}
diff --git a/test/pingpong.tasklist b/test/pingpong.tasklist
deleted file mode 100644
index 760d204b67..0000000000
--- a/test/pingpong.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(TESTA, task_abc, NULL, TASK_STACK_SIZE) \
-  TASK_TEST(TESTB, task_abc, NULL, TASK_STACK_SIZE) \
-  TASK_TEST(TESTC, task_abc, NULL, TASK_STACK_SIZE) \
-  TASK_TEST(TICK, task_tick, NULL, 256)
diff --git a/test/power_button.c b/test/power_button.c
deleted file mode 100644
index 5fe9136105..0000000000
--- a/test/power_button.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test lid switch.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "power_button.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int pb_hook_count;
-
-int lid_is_open(void)
-{
-	return 1;
-}
-
-static void pb_change_hook(void)
-{
-	pb_hook_count++;
-}
-DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, pb_change_hook, HOOK_PRIO_DEFAULT);
-
-int pb_memmap_state(void)
-{
-	uint8_t *memmap = host_get_memmap(EC_MEMMAP_SWITCHES);
-	return *memmap & EC_SWITCH_POWER_BUTTON_PRESSED;
-}
-
-static int test_hook(void)
-{
-	/* Release power button for testing */
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	msleep(100);
-	pb_hook_count = 0;
-	host_clear_events(0xffffffff);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
-	msleep(50);
-	TEST_ASSERT(pb_hook_count == 1);
-	TEST_ASSERT(power_button_is_pressed());
-	TEST_ASSERT(pb_memmap_state());
-	TEST_ASSERT(host_get_events() &
-		    EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON));
-	host_clear_events(0xffffffff);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	msleep(50);
-	TEST_ASSERT(pb_hook_count == 2);
-	TEST_ASSERT(!power_button_is_pressed());
-	TEST_ASSERT(!pb_memmap_state());
-	TEST_ASSERT(!(host_get_events() &
-		      EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)));
-
-	return EC_SUCCESS;
-}
-
-static int test_debounce(void)
-{
-	/* Release power button for testing */
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	msleep(100);
-	pb_hook_count = 0;
-	host_clear_events(0xffffffff);
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
-	msleep(20);
-	TEST_ASSERT(pb_hook_count == 0);
-	TEST_ASSERT(!power_button_is_pressed());
-	TEST_ASSERT(!pb_memmap_state());
-	TEST_ASSERT(!(host_get_events() &
-		      EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)));
-
-	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	msleep(50);
-	TEST_ASSERT(pb_hook_count == 0);
-	TEST_ASSERT(!power_button_is_pressed());
-	TEST_ASSERT(!pb_memmap_state());
-	TEST_ASSERT(!(host_get_events() &
-		      EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)));
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_hook);
-	RUN_TEST(test_debounce);
-
-	test_print_result();
-}
diff --git a/test/power_button.tasklist b/test/power_button.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/power_button.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/powerdemo.c b/test/powerdemo.c
deleted file mode 100644
index e695bb8e5e..0000000000
--- a/test/powerdemo.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power state machine demo module for Chrome EC */
-
-#include "clock.h"
-#include "common.h"
-#include "powerdemo.h"
-#include "task.h"
-#include "timer.h"
-#include "registers.h"
-
-static volatile enum {
-	POWER_STATE_IDLE = 0,    /* Idle */
-	POWER_STATE_DOWN1,       /* Assert output for 1ms */
-	POWER_STATE_UP1,         /* Deassert output for 1ms */
-	POWER_STATE_DOWN10,      /* Assert output for 10ms */
-	POWER_STATE_UP5,         /* Deassert output for 5ms */
-	POWER_STATE_DOWN15,      /* Assert output for 15ms */
-	POWER_STATE_WAIT,        /* Wait for button to be released */
-	POWER_STATE_DOWN2        /* Assert output for 2ms */
-} state = POWER_STATE_IDLE;
-
-
-/* Stops the timer. */
-static void __stop_timer(void)
-{
-	/* Disable timer A */
-	LM4_TIMER_CTL(7) &= ~0x01;
-	/* Clear any pending interrupts */
-	LM4_TIMER_ICR(7) = LM4_TIMER_RIS(7);
-}
-
-
-/* Starts the timer with the specified delay.  If the timer is already
- * started, resets it. */
-static void __start_timer(int usec)
-{
-	/* Stop the timer, if it was started */
-	__stop_timer();
-	/* Set the delay, counting function overhead */
-	LM4_TIMER_TAILR(7) = usec;
-	/* Start timer A */
-	LM4_TIMER_CTL(7) |= 0x01;
-}
-
-
-static void __set_state(int new_state, int pin_value, int timeout)
-{
-	LM4_GPIO_DATA(LM4_GPIO_D, 0x08) = (pin_value ? 0x08 : 0);
-	if (timeout)
-		__start_timer(timeout);
-	else
-		__stop_timer();
-	state = new_state;
-}
-
-
-int power_demo_init(void)
-{
-	volatile uint32_t scratch __attribute__((unused));
-
-	/* Set up TIMER1 as our state timer */
-	/* Enable TIMER1 clock */
-	LM4_SYSTEM_RCGCWTIMER |= 0x02;
-	/* wait 3 clock cycles before using the module */
-	scratch = LM4_SYSTEM_RCGCWTIMER;
-	/* Ensure timer is disabled : TAEN = TBEN = 0 */
-	LM4_TIMER_CTL(7) &= ~0x101;
-	/* 32-bit timer mode */
-	LM4_TIMER_CFG(7) = 4;
-	/* Set the prescaler to increment every microsecond */
-	LM4_TIMER_TAPR(7) = clock_get_freq() / SECOND;
-	/* One-shot, counting down */
-	LM4_TIMER_TAMR(7) = 0x01;
-	/* Set overflow interrupt */
-	LM4_TIMER_IMR(7) = 0x1;
-
-	/* Enable clock to GPIO module D */
-	LM4_SYSTEM_RCGCGPIO |= 0x0008;
-
-	/* Clear GPIOAFSEL and enable digital function for pins 0-3 */
-	LM4_GPIO_AFSEL(LM4_GPIO_D) &= ~0x0f;
-	LM4_GPIO_DEN(LM4_GPIO_D) |= 0x0f;
-
-	/* Set pins 0-2 as input, pin 3 as output */
-	LM4_GPIO_DIR(LM4_GPIO_D) = (LM4_GPIO_DIR(LM4_GPIO_D) & ~0x0f) | 0x08;
-
-	/* Set pin 0 to edge-sensitive, both edges, pull-up */
-	LM4_GPIO_IS(LM4_GPIO_D) &= ~0x01;
-	LM4_GPIO_IBE(LM4_GPIO_D) |= 0x01;
-	LM4_GPIO_PUR(LM4_GPIO_D) |= 0x01;
-
-	/* Move to idle state */
-	__set_state(POWER_STATE_IDLE, 1, 0);
-
-	/* Enable interrupt on pin 0 */
-	LM4_GPIO_IM(LM4_GPIO_D) |= 0x01;
-
-	return EC_SUCCESS;
-}
-
-
-/* GPIO interrupt handler */
-static void __gpio_d_interrupt(void)
-{
-	uint32_t mis = LM4_GPIO_MIS(LM4_GPIO_D);
-
-	/* Clear the interrupt bits we're handling */
-	LM4_GPIO_ICR(LM4_GPIO_D) = mis;
-
-	/* Handle edges */
-	if (mis & 0x01) {
-		if (LM4_GPIO_DATA(LM4_GPIO_D, 0x01)) {
-			if (state == POWER_STATE_WAIT)
-				__set_state(POWER_STATE_DOWN2, 0, 2000 - 28);
-		} else {
-			if (state == POWER_STATE_IDLE)
-				__set_state(POWER_STATE_DOWN1, 0, 1000 - 28);
-		}
-	}
-}
-
-DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
-
-
-/* Timer interrupt handler */
-static void __timer_w1_interrupt(void)
-{
-	uint32_t mis = LM4_TIMER_RIS(7);
-	/* Clear the interrupt reasons we're handling */
-	LM4_TIMER_ICR(7) = mis;
-
-	/* Transition to next state */
-	switch (state) {
-	case POWER_STATE_IDLE:
-	case POWER_STATE_WAIT:
-		/* Ignore timer events when waiting for GPIO edges */
-		break;
-	case POWER_STATE_DOWN1:
-		__set_state(POWER_STATE_UP1, 1, 1000 - 28);
-		break;
-	case POWER_STATE_UP1:
-		__set_state(POWER_STATE_DOWN10, 0, 10000 - 228);
-		break;
-	case POWER_STATE_DOWN10:
-		__set_state(POWER_STATE_UP5, 1, 5000 - 128);
-		break;
-	case POWER_STATE_UP5:
-		__set_state(POWER_STATE_DOWN15, 0, 15000 - 328);
-		break;
-	case POWER_STATE_DOWN15:
-		if (LM4_GPIO_DATA(LM4_GPIO_D, 0x01)) {
-			/* Button has already been released; go straight to
-			 * idle */
-			__set_state(POWER_STATE_IDLE, 1, 0);
-		} else {
-			/* Wait for button release */
-			__set_state(POWER_STATE_WAIT, 1, 0);
-		}
-		break;
-	case POWER_STATE_DOWN2:
-		__set_state(POWER_STATE_IDLE, 1, 0);
-		break;
-	}
-}
-
-DECLARE_IRQ(LM4_IRQ_TIMERW1A, __timer_w1_interrupt, 1);
-
-int power_demo_task(void)
-{
-	/* Initialize the peripherals */
-	power_demo_init();
-
-	/* suspend this task forever */
-	task_wait_event(-1);
-
-	return EC_SUCCESS;
-}
diff --git a/test/powerdemo.h b/test/powerdemo.h
deleted file mode 100644
index 17ed482042..0000000000
--- a/test/powerdemo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Power state machine demo module for Chrome EC */
-
-#ifndef __TEST_POWERDEMO_H
-#define __TEST_POWERDEMO_H
-
-#include "common.h"
-
-/* Initializes the module. */
-int power_demo_init(void);
-
-#endif  /* __TEST_POWERDEMO_H */
diff --git a/test/powerdemo.tasklist b/test/powerdemo.tasklist
deleted file mode 100644
index a4fff562e3..0000000000
--- a/test/powerdemo.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(POWERDEMO, power_demo_task, NULL, TASK_STACK_SIZE)
diff --git a/test/printf.c b/test/printf.c
deleted file mode 100644
index f7e9b9dd2d..0000000000
--- a/test/printf.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stddef.h>
-
-#include "common.h"
-#include "printf.h"
-#include "test_util.h"
-#include "util.h"
-
-#define INIT_VALUE 0x5E
-#define NO_BYTES_TOUCHED NULL
-
-static const char err_str[] = "ERROR";
-static char output[1024];
-
-int run(int expect_ret, const char *expect,
-	bool output_null, size_t size_limit,
-	const char *format, va_list args)
-{
-	size_t expect_size = expect ? strlen(expect) + 1 : 0;
-	int rv;
-
-	ccprintf("\n");
-	ccprintf("size_limit=%-4zd | format='%s'\n", size_limit, format);
-	ccprintf("expect  ='%s'   | expect_status=%d\n",
-		 expect ? expect : "NO_BYTES_TOUCHED", expect_ret);
-
-	TEST_ASSERT(expect_size <= sizeof(output));
-	TEST_ASSERT(expect_size <= size_limit);
-	memset(output, INIT_VALUE, sizeof(output));
-
-	rv = vsnprintf(output_null ? NULL : output, size_limit,
-		       format, args);
-	ccprintf("received='%.*s'   | ret          =%d\n",
-		 30, output, rv);
-
-	TEST_ASSERT_ARRAY_EQ(output, expect, expect_size);
-	TEST_ASSERT_MEMSET(&output[expect_size], INIT_VALUE,
-			   sizeof(output) - expect_size);
-
-	if (rv >= 0) {
-		TEST_ASSERT(rv == expect_size - 1);
-		TEST_ASSERT(EC_SUCCESS == expect_ret);
-	} else {
-		TEST_ASSERT(rv == -expect_ret);
-	}
-
-	return EC_SUCCESS;
-}
-
-int expect_success(const char *expect, const char *format, ...)
-{
-	va_list args;
-	int rv;
-
-	va_start(args, format);
-	rv = run(EC_SUCCESS, expect,
-		 false, sizeof(output),
-		 format, args);
-	va_end(args);
-
-	return rv;
-}
-
-int expect(int expect_ret, const char *expect,
-	   bool output_null, size_t size_limit,
-	   const char *format, ...)
-{
-	va_list args;
-	int rv;
-
-	va_start(args, format);
-	rv = run(expect_ret, expect,
-		 output_null, size_limit,
-		 format, args);
-	va_end(args);
-
-	return rv;
-}
-
-#define T(n)                                                                  \
-	do {                                                                  \
-		int rv = (n);                                                 \
-		if (rv != EC_SUCCESS)                                         \
-			return rv;                                            \
-	} while (0)
-
-test_static int test_vsnprintf_args(void)
-{
-	T(expect_success("",          ""));
-	T(expect_success("a",         "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given 0 as output size limit */
-		 false, 0, ""));
-	T(expect(/* expect SUCCESS */
-		 EC_SUCCESS, "",
-		 /* given 1 as output size limit and a blank format */
-		 false, 1, ""));
-	T(expect(/* expect an overflow error */
-		 EC_ERROR_OVERFLOW, "",
-		 /* given 1 as output size limit with a non-blank format */
-		 false, 1, "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given NULL as the output buffer */
-		 true, sizeof(output), ""));
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given a NULL format string */
-		 false, sizeof(output), NULL));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_int(void)
-{
-	T(expect_success("123",       "%d",      123));
-	T(expect_success("-123",      "%d",     -123));
-	T(expect_success("+123",      "%+d",     123));
-	T(expect_success("-123",      "%+d",    -123));
-	T(expect_success("123",       "%-d",     123));
-	T(expect_success("-123",      "%-d",    -123));
-
-	T(expect_success("  123",     "%5d",     123));
-	T(expect_success(" +123",     "%+5d",    123));
-	T(expect_success("00123",     "%05d",    123));
-	T(expect_success("00123",     "%005d",   123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("+0123",     "%+05d",   123));
-	 * Actual: "0+123"
-	 * T(expect_success("+0123",     "%+005d",  123));
-	 * Actual: "0+123"
-	 */
-
-	T(expect_success("  123",     "%*d",     5, 123));
-	T(expect_success(" +123",     "%+*d",    5, 123));
-	T(expect_success("00123",     "%0*d",    5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("00123",     "%00*d",   5, 123));
-	 * Actual: "ERROR"
-	 */
-	T(expect_success("0+123",     "%+0*d",   5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("0+123",     "%+00*d",  5, 123));
-	 * Actual: "ERROR"
-	 */
-
-	T(expect_success("123  ",     "%-5d",    123));
-	T(expect_success("+123 ",     "%-+5d",   123));
-	T(expect_success(err_str,     "%+-5d",   123));
-	T(expect_success("123  ",     "%-05d",   123));
-	T(expect_success("123  ",     "%-005d",  123));
-	T(expect_success("+123 ",     "%-+05d",  123));
-	T(expect_success("+123 ",     "%-+005d", 123));
-
-	T(expect_success("0.00123",   "%.5d",    123));
-	T(expect_success("+0.00123",  "%+.5d",   123));
-	T(expect_success("0.00123",   "%7.5d",   123));
-	T(expect_success("  0.00123", "%9.5d",   123));
-	T(expect_success(" +0.00123", "%+9.5d",  123));
-
-	T(expect_success("123",        "%u",    123));
-	T(expect_success("4294967295", "%u",   -1));
-	T(expect_success("18446744073709551615", "%llu", (uint64_t)-1));
-
-	T(expect_success("0",         "%x",     0));
-	T(expect_success("0",         "%X",     0));
-	T(expect_success("5e",        "%x",     0X5E));
-	T(expect_success("5E",        "%X",     0X5E));
-
-	/*
-	 * %l is deprecated on 32-bit systems (see crbug.com/984041), but is
-	 * is still functional on 64-bit systems.
-	 */
-	if (sizeof(long) == sizeof(uint32_t)) {
-		T(expect_success(err_str,     "%lx",    0x7b));
-		T(expect_success(err_str,     "%08lu",  0x7b));
-		T(expect_success("13ERROR",   "%d%lu", 13, 14));
-	} else {
-		T(expect_success("7b",        "%lx",    0x7b));
-		T(expect_success("00000123",  "%08lu",  123));
-		T(expect_success("131415",    "%d%lu%d", 13, 14L, 15));
-	}
-
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_pointers(void)
-{
-	void *ptr = (void *)0x55005E00;
-	unsigned int val = 0;
-
-	T(expect_success("55005e00",  "%pP",     ptr));
-	T(expect_success(err_str,     "%P",      ptr));
-	/* %p by itself is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%p"));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%p "));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%pQ"));
-
-	/* Test %pb, binary format */
-	T(expect_success("0",         "%pb",     BINARY_VALUE(val, 0)));
-	val = 0x5E;
-	T(expect_success("1011110",   "%pb",     BINARY_VALUE(val, 0)));
-	T(expect_success("0000000001011110", "%pb", BINARY_VALUE(val, 16)));
-	val = 0x12345678;
-	T(expect_success("10010001101000101011001111000", "%pb",
-			 BINARY_VALUE(val, 0)));
-	val = 0xFEDCBA90;
-	/* Test a number that makes the longest string possible */
-	T(expect_success("11111110110111001011101010010000", "%pb",
-			 BINARY_VALUE(val, 0)));
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_chars(void)
-{
-	T(expect_success("a",         "%c",      'a'));
-	T(expect_success("*",         "%c",      '*'));
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_strings(void)
-{
-	T(expect_success("abc",       "%s",      "abc"));
-	T(expect_success("  abc",     "%5s",     "abc"));
-	T(expect_success("abc",       "%0s",     "abc"));
-	T(expect_success("abc  ",     "%-5s",    "abc"));
-	T(expect_success("abc",       "%*s",     0, "abc"));
-	T(expect_success("a",         "%.1s",    "abc"));
-	T(expect_success("a",         "%.*s",    1, "abc"));
-	T(expect_success("",          "%.0s",    "abc"));
-	T(expect_success("",          "%.*s",    0, "abc"));
-	/*
-	 * TODO(crbug.com/974084):
-	 * Ignoring the padding parameter is slightly
-	 * odd behavior and could use a review.
-	 */
-	T(expect_success("ab",        "%5.2s",   "abc"));
-	T(expect_success("abc",        "%.4s",   "abc"));
-
-	/*
-	 * Given a malformed string (address 0x1 is a good example),
-	 * if we ask for zero precision, expect no bytes to be read
-	 * from the malformed address and a blank output string.
-	 */
-	T(expect_success("",          "%.0s",    (char *)1));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_timestamps(void)
-{
-	uint64_t ts = 0;
-
-	T(expect_success("0.000000",       "%pT",      &ts));
-	ts = 123456;
-	T(expect_success("0.123456",       "%pT",      &ts));
-	ts = 9999999000000;
-	T(expect_success("9999999.000000", "%pT",      &ts));
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_hexdump(void)
-{
-	const char bytes[] = {0x00, 0x5E};
-
-	T(expect_success("005e",      "%ph",      HEX_BUF(bytes, 2)));
-	T(expect_success("",          "%ph",      HEX_BUF(bytes, 0)));
-	T(expect_success("00",        "%ph",      HEX_BUF(bytes, 1)));
-	return EC_SUCCESS;
-}
-
-test_static int test_vsnprintf_combined(void)
-{
-	T(expect_success("abc",       "%c%s",    'a', "bc"));
-	T(expect_success("12\tbc",    "%d\t%s",  12, "bc"));
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_vsnprintf_args);
-	RUN_TEST(test_vsnprintf_int);
-	RUN_TEST(test_vsnprintf_pointers);
-	RUN_TEST(test_vsnprintf_chars);
-	RUN_TEST(test_vsnprintf_strings);
-	RUN_TEST(test_vsnprintf_timestamps);
-	RUN_TEST(test_vsnprintf_hexdump);
-	RUN_TEST(test_vsnprintf_combined);
-
-	test_print_result();
-}
diff --git a/test/printf.tasklist b/test/printf.tasklist
deleted file mode 100644
index 9fc1a80f4d..0000000000
--- a/test/printf.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/queue.c b/test/queue.c
deleted file mode 100644
index e0be1b5d9a..0000000000
--- a/test/queue.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test queue.
- */
-
-#include "common.h"
-#include "console.h"
-#include "queue.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static struct queue const test_queue8 = QUEUE_NULL(8, char);
-static struct queue const test_queue2 = QUEUE_NULL(2, int16_t);
-
-static int test_queue8_empty(void)
-{
-	char tmp = 1;
-
-	TEST_ASSERT(queue_is_empty(&test_queue8));
-	TEST_ASSERT(!queue_remove_units(&test_queue8, &tmp, 1));
-	TEST_ASSERT(queue_add_units(&test_queue8, &tmp, 1) == 1);
-	TEST_ASSERT(!queue_is_empty(&test_queue8));
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_init(void)
-{
-	char tmp = 1;
-
-	TEST_ASSERT(queue_add_units(&test_queue8, &tmp, 1) == 1);
-	queue_init(&test_queue8);
-	TEST_ASSERT(queue_is_empty(&test_queue8));
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_fifo(void)
-{
-	char buf1[3] = {1, 2, 3};
-	char buf2[3];
-
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 0, 1) == 1);
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 1, 1) == 1);
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 2, 1) == 1);
-
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 3) == 3);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 3);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_multiple_units_add(void)
-{
-	char buf1[5] = {1, 2, 3, 4, 5};
-	char buf2[5];
-
-	TEST_ASSERT(queue_space(&test_queue8) >= 5);
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 5) == 5);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 5);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_removal(void)
-{
-	char buf1[5] = {1, 2, 3, 4, 5};
-	char buf2[5];
-
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
-	/* 1, 2, 3, 4, 5 */
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 3) == 3);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 3);
-	/* 4, 5 */
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 2) == 2);
-	/* 4, 5, 1, 2 */
-	TEST_ASSERT(queue_space(&test_queue8) == 4);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 1) == 1);
-	TEST_ASSERT(buf2[0] == 4);
-	/* 5, 1, 2 */
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 2, 2) == 2);
-	/* 5, 1, 2, 3, 4 */
-	TEST_ASSERT(queue_space(&test_queue8) == 3);
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 2, 3) == 3);
-	/* 5, 1, 2, 3, 4, 3, 4, 5 */
-	TEST_ASSERT(queue_space(&test_queue8) == 0);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 1) == 1);
-	TEST_ASSERT(buf2[0] == 5);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 4) == 4);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 4);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 3) == 3);
-	TEST_ASSERT_ARRAY_EQ(buf1 + 2, buf2, 3);
-	TEST_ASSERT(queue_is_empty(&test_queue8));
-	/* Empty */
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
-	TEST_ASSERT(queue_remove_units(&test_queue8, buf2, 5) == 5);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 5);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_peek(void)
-{
-	char buf1[5] = {1, 2, 3, 4, 5};
-	char buf2[5];
-
-	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
-	/* 1, 2, 3, 4, 5 */
-	TEST_ASSERT(queue_count(&test_queue8) == 5);
-	TEST_ASSERT(queue_space(&test_queue8) == 3);
-	TEST_ASSERT(queue_peek_units(&test_queue8, buf2, 2, 3) == 3);
-	TEST_ASSERT_ARRAY_EQ(buf1 + 2, buf2, 3);
-	TEST_ASSERT(queue_count(&test_queue8) == 5);
-	TEST_ASSERT(queue_space(&test_queue8) == 3);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue2_odd_even(void)
-{
-	uint16_t buf1[3] = {1, 2, 3};
-	uint16_t buf2[3];
-
-	TEST_ASSERT(queue_add_units(&test_queue2, buf1, 1) == 1);
-	/* 1 */
-	TEST_ASSERT(queue_space(&test_queue2) == 1);
-	TEST_ASSERT(queue_add_units(&test_queue2, buf1 + 1, 1) == 1);
-	/* 1, 2 */
-	TEST_ASSERT(queue_space(&test_queue2) == 0);
-	TEST_ASSERT(queue_remove_units(&test_queue2, buf2, 2) == 2);
-	TEST_ASSERT_ARRAY_EQ(buf1, buf2, 2);
-	TEST_ASSERT(queue_is_empty(&test_queue2));
-	/* Empty */
-	TEST_ASSERT(queue_space(&test_queue2) == 2);
-	TEST_ASSERT(queue_add_units(&test_queue2, buf1 + 2, 1) == 1);
-	/* 3 */
-	TEST_ASSERT(queue_remove_units(&test_queue2, buf2, 1) == 1);
-	TEST_ASSERT(buf2[0] == 3);
-	TEST_ASSERT(queue_is_empty(&test_queue2));
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks(void)
-{
-	static uint8_t const data[3] = {1, 2, 3};
-	struct queue_chunk chunk;
-
-	chunk = queue_get_write_chunk(&test_queue8, 0);
-
-	TEST_ASSERT(chunk.count == 8);
-
-	memcpy(chunk.buffer, data, 3);
-
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 3) == 3);
-
-	chunk = queue_get_read_chunk(&test_queue8);
-
-	TEST_ASSERT(chunk.count == 3);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 3);
-
-	TEST_ASSERT(queue_advance_head(&test_queue8, 3) == 3);
-	TEST_ASSERT(queue_is_empty(&test_queue8));
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks_wrapped(void)
-{
-	static uint8_t const data[3] = {1, 2, 3};
-
-	/* Move near the end of the queue */
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 6) == 6);
-	TEST_ASSERT(queue_advance_head(&test_queue8, 6) == 6);
-
-	/* Add three units, causing the tail to wrap */
-	TEST_ASSERT(queue_add_units(&test_queue8, data, 3) == 3);
-
-	/*
-	 * With a wrapped tail we should only be able to access the first two
-	 * elements for reading, but all five free elements for writing.
-	 */
-	TEST_ASSERT(queue_get_read_chunk(&test_queue8).count == 2);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 0).count == 5);
-
-	/* Signal that we have read an element */
-	TEST_ASSERT(queue_advance_head(&test_queue8, 1) == 1);
-
-	/*
-	 * Now we should only be able to see a single element for reading, but
-	 * all six free element.
-	 */
-	TEST_ASSERT(queue_get_read_chunk(&test_queue8).count == 1);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 0).count == 6);
-
-	/* Signal that we have read the last two elements */
-	TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2);
-
-	/*
-	 * Now there should be no elements available for reading, and only
-	 * seven, not eight elements available for writing.  This is because
-	 * the head/tail pointers now point to the second unit in the array.
-	 */
-	TEST_ASSERT(queue_get_read_chunk(&test_queue8).count == 0);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 0).count == 7);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks_full(void)
-{
-	static uint8_t const data[8] = {1, 2, 3, 4, 5, 6, 7, 8};
-	struct queue_chunk chunk;
-
-	/* Move near the end of the queue */
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 6) == 6);
-	TEST_ASSERT(queue_advance_head(&test_queue8, 6) == 6);
-
-	/* Fill the queue */
-	TEST_ASSERT(queue_add_units(&test_queue8, data, 8) == 8);
-
-	/* With a full queue we shouldn't be able to write */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 0).count == 0);
-
-	/* But we should be able to read, though only two entries at first */
-	chunk = queue_get_read_chunk(&test_queue8);
-
-	TEST_ASSERT(chunk.count == 2);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 2);
-
-	/* Signal that we have read both units */
-	TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2);
-
-	/* Now we should only be able to see the rest */
-	chunk = queue_get_read_chunk(&test_queue8);
-
-	TEST_ASSERT(chunk.count == 6);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data + 2, 6);
-
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks_empty(void)
-{
-	/* With an empty queue we shouldn't be able to read */
-	TEST_ASSERT(queue_get_read_chunk(&test_queue8).count == 0);
-
-	/* But we should be able to write, everything */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 0).count == 8);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks_advance(void)
-{
-	/*
-	 * We should only be able to advance the tail (add units) as many
-	 * units as there are in an empty queue.
-	 */
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 10) == 8);
-
-	/*
-	 * Similarly, we should only be able to advance the head (remove
-	 * units) as many units as there are in the now full queue.
-	 */
-	TEST_ASSERT(queue_advance_head(&test_queue8, 10) == 8);
-
-	/*
-	 * And it shouldn't matter if we start in the middle of the queue.
-	 */
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 3) == 3);
-	TEST_ASSERT(queue_advance_head(&test_queue8, 3) == 3);
-
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 10) == 8);
-	TEST_ASSERT(queue_advance_head(&test_queue8, 10) == 8);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_chunks_offset(void)
-{
-	/* Check offsetting by 1 */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).count == 7);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).buffer ==
-			test_queue8.buffer + 1);
-
-	/* Check offsetting by 4 */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 4);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer + 4);
-
-	/* Check offset wrapping around */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 10).count == 0);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 10).buffer == NULL);
-
-	/*
-	 * Check offsetting when used memory is in the middle:
-	 *    H T
-	 * |--xx----|
-	 */
-	TEST_ASSERT(queue_advance_tail(&test_queue8, 4) == 4);
-	TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2);
-
-	/* Get writable chunk to right of tail. */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).count == 2);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).buffer ==
-			test_queue8.buffer + 6);
-
-	/* Get writable chunk wrapped and before head. */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 2);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer);
-
-	/* Check offsetting into non-writable memory. */
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 6).count == 0);
-	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 6).buffer == NULL);
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_iterate_begin(void)
-{
-	struct queue const *q = &test_queue8;
-	char data[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-	struct queue_iterator it;
-
-	queue_begin(q, &it);
-	TEST_EQ(it.ptr, NULL, "%p");
-
-	queue_add_units(q, data, 4);
-	queue_begin(q, &it);
-	TEST_EQ(*((char *)it.ptr), 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_iterate_next(void)
-{
-	struct queue const *q = &test_queue8;
-	char data[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-	struct queue_iterator it;
-
-	queue_add_units(q, data, 4);
-	queue_begin(q, &it);
-	TEST_EQ(*((char *)it.ptr), 0, "%d");
-
-	queue_next(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	TEST_EQ(*((char *)it.ptr), 1, "%d");
-
-	queue_next(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	TEST_EQ(*((char *)it.ptr), 2, "%d");
-
-	queue_next(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	TEST_EQ(*((char *)it.ptr), 3, "%d");
-
-	queue_next(q, &it);
-	TEST_EQ(it.ptr, NULL, "%p");
-
-	return EC_SUCCESS;
-}
-
-static int test_queue2_iterate_next_full(void)
-{
-	struct queue const *q = &test_queue2;
-	int16_t data[2] = { 523, -788 };
-	struct queue_iterator it;
-
-	queue_add_units(q, data, 2);
-	queue_begin(q, &it);
-	TEST_EQ(*((int16_t *)it.ptr), 523, "%d");
-
-	queue_next(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	TEST_EQ(*((int16_t *)it.ptr), -788, "%d");
-
-	queue_next(q, &it);
-	TEST_EQ(it.ptr, NULL, "%p");
-
-	return EC_SUCCESS;
-}
-
-static int test_queue8_iterate_next_reset_on_change(void)
-{
-	struct queue const *q = &test_queue8;
-	char data[8] = { -88, -37, -5, -1, 3, 16, 56, 100 };
-	struct queue_iterator it;
-
-	queue_add_units(q, data, 4);
-	queue_begin(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	queue_add_units(q, data + 4, 4);
-	queue_next(q, &it);
-	TEST_EQ(it.ptr, NULL, "%p");
-
-	queue_begin(q, &it);
-	TEST_NE(it.ptr, NULL, "%p");
-	queue_advance_head(q, 3);
-	queue_next(q, &it);
-	TEST_EQ(it.ptr, NULL, "%p");
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	queue_init(&test_queue2);
-	queue_init(&test_queue8);
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_queue8_empty);
-	RUN_TEST(test_queue8_init);
-	RUN_TEST(test_queue8_fifo);
-	RUN_TEST(test_queue8_multiple_units_add);
-	RUN_TEST(test_queue8_removal);
-	RUN_TEST(test_queue8_peek);
-	RUN_TEST(test_queue2_odd_even);
-	RUN_TEST(test_queue8_chunks);
-	RUN_TEST(test_queue8_chunks_wrapped);
-	RUN_TEST(test_queue8_chunks_full);
-	RUN_TEST(test_queue8_chunks_empty);
-	RUN_TEST(test_queue8_chunks_advance);
-	RUN_TEST(test_queue8_chunks_offset);
-	RUN_TEST(test_queue8_iterate_begin);
-	RUN_TEST(test_queue8_iterate_next);
-	RUN_TEST(test_queue2_iterate_next_full);
-	RUN_TEST(test_queue8_iterate_next_reset_on_change);
-
-	test_print_result();
-}
diff --git a/test/queue.tasklist b/test/queue.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/queue.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/rollback.c b/test/rollback.c
deleted file mode 100644
index 2038333311..0000000000
--- a/test/rollback.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-#include "flash.h"
-#include "mpu.h"
-#include "string.h"
-#include "test_util.h"
-
-struct rollback_info {
-	int region_0_offset;
-	int region_1_offset;
-	uint32_t region_size_bytes;
-};
-
-/* These values are intentionally hardcoded here instead of using the chip
- * config headers, so that if the headers are accidentally changed we can catch
- * it.
- */
-#if defined(CHIP_VARIANT_STM32F412)
-struct rollback_info rollback_info = {
-	.region_0_offset = 0x20000,
-	.region_1_offset = 0x40000,
-	.region_size_bytes = 128 * 1024,
-};
-#elif defined(CHIP_VARIANT_STM32H7X3)
-struct rollback_info rollback_info = {
-	.region_0_offset = 0xC0000,
-	.region_1_offset = 0xE0000,
-	.region_size_bytes = 128 * 1024,
-};
-#else
-#error "Rollback info not defined for this chip. Please add it."
-#endif
-
-test_static int read_rollback_region(const struct rollback_info *info,
-				     int region)
-{
-	int i;
-	char data;
-	uint32_t bytes_read = 0;
-
-	int offset = region == 0 ? info->region_0_offset :
-				   info->region_1_offset;
-
-	for (i = 0; i < info->region_size_bytes; i++) {
-		if (crec_flash_read(offset + i, sizeof(data), &data) ==
-			EC_SUCCESS)
-			bytes_read++;
-	}
-
-	return bytes_read;
-}
-
-test_static int _test_lock_rollback(const struct rollback_info *info,
-				    int region)
-{
-	int rv;
-
-	/*
-	 * We expect the MPU to have already been enabled during the
-	 * initialization process (mpu_pre_init).
-	 */
-
-	rv = mpu_lock_rollback(0);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	/* unlocked we should be able to read both regions */
-	rv = read_rollback_region(info, 0);
-	TEST_EQ(rv, rollback_info.region_size_bytes, "%d");
-
-	rv = read_rollback_region(info, 1);
-	TEST_EQ(rv, rollback_info.region_size_bytes, "%d");
-
-	rv = mpu_lock_rollback(1);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	/* TODO(b/156112448): Validate that it actually reboots with the correct
-	 * data access violation.
-	 */
-	read_rollback_region(info, region);
-
-	/* Should not get here. Should reboot with:
-	 *
-	 * Data access violation, mfar = XXX
-	 *
-	 * where XXX = start of rollback
-	 */
-	TEST_ASSERT(false);
-
-	return EC_ERROR_UNKNOWN;
-}
-
-test_static int test_lock_rollback_region_0(void)
-{
-	/* This call should never return due to panic. */
-	return _test_lock_rollback(&rollback_info, 0);
-}
-
-test_static int test_lock_rollback_region_1(void)
-{
-	/* This call should never return due to panic. */
-	return _test_lock_rollback(&rollback_info, 1);
-}
-
-void run_test(int argc, char **argv)
-{
-	if (argc < 2) {
-		ccprintf("usage: runtest [region0|region1]\n");
-		return;
-	}
-
-	ccprintf("Running rollback test\n");
-
-	/*
-	 * TODO(b/156112448): For now you have to run the test separately for
-	 * each region.
-	 */
-	if (strncmp(argv[1], "region0", 7) == 0)
-		RUN_TEST(test_lock_rollback_region_0);
-	else if (strncmp(argv[1], "region1", 7) == 0)
-		RUN_TEST(test_lock_rollback_region_1);
-
-	test_print_result();
-}
diff --git a/test/rollback.tasklist b/test/rollback.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/rollback.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/rollback_entropy.c b/test/rollback_entropy.c
deleted file mode 100644
index 788fab2572..0000000000
--- a/test/rollback_entropy.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "rollback.h"
-#include "rollback_private.h"
-#include "string.h"
-#include "system.h"
-#include "test_util.h"
-
-static const uint32_t VALID_ROLLBACK_COOKIE = 0x0b112233;
-static const uint32_t UNINITIALIZED_ROLLBACK_COOKIE = 0xffffffff;
-
-static const uint8_t FAKE_ENTROPY[] = {
-	0xff, 0xff, 0xff, 0xff
-};
-
-/*
- * Generated by concatenating 32-bytes (256-bits) of zeros with the 4 bytes
- * of FAKE_ENTROPY and computing SHA256 sum:
- *
- * echo -n -e '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'\
- * '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'\
- * '\xFF\xFF\xFF\xFF'  | sha256sum
- *
- * 890ed82cf09f22243bdc4252e4d79c8a9810c1391f455dce37a7b732eb0a0e4f
- */
-#define EXPECTED_SECRET \
-	0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42, \
-	0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, 0x45, \
-	0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, 0x4f
-__maybe_unused static const uint8_t _EXPECTED_SECRET[] = {
-	EXPECTED_SECRET
-};
-BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE);
-
-/*
- * Generated by concatenating 32-bytes (256-bits) of EXPECTED_SECRET with the 4
- * bytes of FAKE_ENTROPY and computing SHA256 sum:
- *
- * echo -n -e '\x89\x0e\xd8\x2c\xf0\x9f\x22\x24\x3b\xdc\x42\x52\xe4\xd7\x9c'\
- * '\x8a\x98\x10\xc1\x39\x1f\x45\x5d\xce\x37\xa7\xb7\x32\xeb\x0a\x0e\x4f\xFF'\
- * '\FF\xFF' | sha256sum
- *
- * b5d2c08b1f9109ac5c67de15486f0ac267ef9501bd9f646f4ea80085cb08284c
- */
-#define EXPECTED_SECRET2 \
-	0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde, \
-	0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, 0x9f, \
-	0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, 0x4c
-__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = {
-	EXPECTED_SECRET2
-};
-BUILD_ASSERT(sizeof(_EXPECTED_SECRET2) == CONFIG_ROLLBACK_SECRET_SIZE);
-
-#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-__maybe_unused static const uint8_t
-_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = {
-	EXPECTED_UNINITIALIZED_ROLLBACK_SECRET
-};
-BUILD_ASSERT(sizeof(_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET) ==
-	     CONFIG_ROLLBACK_SECRET_SIZE);
-
-test_static void print_rollback(const struct rollback_data *rb_data)
-{
-	int i;
-
-	ccprintf("rollback secret: 0x");
-	for (i = 0; i < sizeof(rb_data->secret); i++)
-		ccprintf("%02x", rb_data->secret[i]);
-	ccprintf("\n");
-
-	ccprintf("rollback id: %d\n", rb_data->id);
-	ccprintf("rollback cookie: %0x\n", rb_data->cookie);
-	ccprintf("rollback_min_version: %d\n", rb_data->rollback_min_version);
-}
-
-test_static int check_equal(const struct rollback_data *actual,
-			    const struct rollback_data *expected)
-{
-	int rv = memcmp(actual->secret, expected->secret,
-			sizeof(*actual->secret));
-	TEST_EQ(rv, 0, "%d");
-	TEST_EQ(actual->rollback_min_version, expected->rollback_min_version,
-		"%d");
-	TEST_EQ(actual->id, expected->id, "%d");
-	TEST_EQ(actual->cookie, expected->cookie, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_add_entropy(void)
-{
-	int rv;
-	struct rollback_data rb_data;
-
-	const struct rollback_data expected_empty = {
-		.id = 0,
-		.rollback_min_version = 0,
-		.secret = { 0 },
-		.cookie = VALID_ROLLBACK_COOKIE
-	};
-
-	const struct rollback_data expected_uninitialized = {
-		.id = -1,
-		.rollback_min_version = -1,
-		.secret = { EXPECTED_UNINITIALIZED_ROLLBACK_SECRET },
-		.cookie = UNINITIALIZED_ROLLBACK_COOKIE
-	};
-
-	const struct rollback_data expected_secret = {
-		.id = 1,
-		.rollback_min_version = 0,
-		.secret = { EXPECTED_SECRET },
-		.cookie = VALID_ROLLBACK_COOKIE
-	};
-
-	const struct rollback_data expected_secret2 = {
-		.id = 2,
-		.rollback_min_version = 0,
-		.secret = { EXPECTED_SECRET2 },
-		.cookie = VALID_ROLLBACK_COOKIE
-	};
-
-	if (system_get_image_copy() != EC_IMAGE_RO) {
-		ccprintf("This test is only works when running RO\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/*
-	 * After flashing both rollback regions will be uninitialized (all
-	 * 0xFF). During the boot process, we expect region 0 to be initialized
-	 * by the call to rollback_get_minimum_version().
-	 */
-	rv = read_rollback(0, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_empty), EC_SUCCESS, "%d");
-
-	/* Immediately after boot region 1 should not yet be initialized. */
-	rv = read_rollback(1, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS, "%d");
-
-	/*
-	 * Add entropy. The result should end up being written to the unused
-	 * region (region 1).
-	 */
-	if (IS_ENABLED(SECTION_IS_RO)) {
-		rv = rollback_add_entropy(FAKE_ENTROPY, sizeof(FAKE_ENTROPY));
-		TEST_EQ(rv, EC_SUCCESS, "%d");
-	}
-
-	/* Validate that region 1 has been updated correctly. */
-	rv = read_rollback(1, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_secret), EC_SUCCESS, "%d");
-
-	/* Validate that region 0 has not changed. */
-	rv = read_rollback(0, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_empty), EC_SUCCESS, "%d");
-
-	/*
-	 * Add more entropy. The result should now end up being written to
-	 * region 0.
-	 */
-	if (IS_ENABLED(SECTION_IS_RO)) {
-		rv = rollback_add_entropy(FAKE_ENTROPY, sizeof(FAKE_ENTROPY));
-		TEST_EQ(rv, EC_SUCCESS, "%d");
-	}
-
-	/* Check region 0. */
-	rv = read_rollback(0, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_secret2), EC_SUCCESS, "%d");
-
-	/* Check region 1 has not changed. */
-	rv = read_rollback(1, &rb_data);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_secret), EC_SUCCESS, "%d");
-
-	return rv;
-}
-
-void run_test(int argc, char **argv)
-{
-	ccprintf("Running rollback_entropy test\n");
-	RUN_TEST(test_add_entropy);
-	test_print_result();
-}
diff --git a/test/rollback_entropy.tasklist b/test/rollback_entropy.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/rollback_entropy.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/rsa.c b/test/rsa.c
deleted file mode 100644
index 7170e2ff15..0000000000
--- a/test/rsa.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests RSA implementation.
- */
-
-#include "console.h"
-#include "common.h"
-#include "rsa.h"
-#include "test_util.h"
-#include "util.h"
-
-#ifdef TEST_RSA3
-#if CONFIG_RSA_KEY_SIZE == 3072
-#include "rsa3072-3.h"
-#else
-#include "rsa2048-3.h"
-#endif
-#else
-#include "rsa2048-F4.h"
-#endif
-
-static uint32_t rsa_workbuf[3 * RSANUMBYTES/4];
-
-void run_test(int argc, char **argv)
-{
-	int good;
-
-	good = rsa_verify(rsa_key, sig, hash, rsa_workbuf);
-	if (!good) {
-		ccprintf("RSA verify FAILED\n");
-		test_fail();
-		return;
-	}
-	ccprintf("RSA verify OK\n");
-
-	/* Test with a wrong hash */
-	good = rsa_verify(rsa_key, sig, hash_wrong, rsa_workbuf);
-	if (good) {
-		ccprintf("RSA verify OK (expected fail)\n");
-		test_fail();
-		return;
-	}
-	ccprintf("RSA verify FAILED (as expected)\n");
-
-	/* Test with a wrong signature */
-	good = rsa_verify(rsa_key, sig+1, hash, rsa_workbuf);
-	if (good) {
-		ccprintf("RSA verify OK (expected fail)\n");
-		test_fail();
-		return;
-	}
-	ccprintf("RSA verify FAILED (as expected)\n");
-
-	test_pass();
-}
-
diff --git a/test/rsa.tasklist b/test/rsa.tasklist
deleted file mode 100644
index f46a2eaa1d..0000000000
--- a/test/rsa.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/rsa2048-3.h b/test/rsa2048-3.h
deleted file mode 100644
index d1b15c15a4..0000000000
--- a/test/rsa2048-3.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * RSA 2048 with 3 exponent public key and verification.
- * Private key in rsa2048-3.pem.
- */
-
-/* First generate a key:
- * # openssl genrsa -3 -out key.pem 2048
- * # openssl rsa -in key.pem -pubout > key.pub
- * Then dump the key:
- * # dumpRSAPublicKey -pub key.pub | xxd -i
- */
-const uint8_t rsa_data[] = {
-	0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c,	0x11, 0x17, 0x38, 0xfd,
-	0xef, 0xa2, 0xb5, 0x2d, 0x6d, 0x76, 0xe1, 0x70, 0x7d, 0x67, 0xb1, 0x9a,
-	0x18, 0x78, 0x90, 0xe2, 0xce, 0xa6, 0x81, 0xa0, 0x13, 0x37, 0xf2, 0x71,
-	0xf0, 0x44, 0x96, 0xaf, 0x52, 0x53, 0xd4, 0x23, 0x51, 0x19, 0xe5, 0xb0,
-	0x6d, 0x95, 0x99, 0x11, 0x88, 0x5c, 0xed, 0x52, 0x62, 0x07, 0xa6, 0x02,
-	0xc6, 0xba, 0x48, 0xae, 0x78, 0xd9, 0xfb, 0x73, 0x7a, 0x33, 0xfe, 0x8b,
-	0xe5, 0x38, 0xf6, 0x8b, 0xa1, 0x3f, 0x1d, 0xe1, 0xfc, 0xae, 0x19, 0xf1,
-	0x80, 0x94, 0x06, 0xfc, 0x44, 0x69, 0x3c, 0xec, 0xb2, 0xf0, 0x29, 0x9a,
-	0x97, 0x09, 0x81, 0x88, 0x1a, 0x56, 0x2e, 0xcb, 0xf9, 0x0b, 0x08, 0x5c,
-	0xd3, 0x44, 0x6a, 0xce, 0xe2, 0xbc, 0x71, 0x03, 0x93, 0x0b, 0x80, 0x0e,
-	0x12, 0x4c, 0x25, 0x61, 0x97, 0x15, 0x8a, 0x91, 0x37, 0x1e, 0x63, 0x35,
-	0x83, 0xa0, 0xb8, 0xbb, 0x07, 0x80, 0x7f, 0xbf, 0x2c, 0x1e, 0xab, 0xeb,
-	0xfb, 0x3d, 0x2c, 0xe7, 0xee, 0x32, 0xca, 0x7f, 0x9b, 0xe5, 0xf7, 0x04,
-	0xcc, 0xd5, 0xc9, 0x99, 0x55, 0xd2, 0xdb, 0xe5, 0x27, 0x70, 0xac, 0x1a,
-	0x81, 0x07, 0xff, 0x99, 0x5f, 0x34, 0x6a, 0x91, 0x5a, 0xb3, 0x3a, 0x37,
-	0xef, 0x61, 0xd4, 0xab, 0xf2, 0x90, 0x98, 0x9a, 0xf7, 0x35, 0x73, 0x93,
-	0x64, 0xf1, 0x27, 0x3f, 0x9a, 0x52, 0xa6, 0x91, 0x89, 0xb0, 0x5e, 0x70,
-	0x4c, 0x7e, 0x9e, 0x80, 0x50, 0x2a, 0x25, 0x78, 0xea, 0x6d, 0xad, 0x96,
-	0x04, 0x45, 0x92, 0xaa, 0x03, 0x6f, 0xec, 0x31, 0xbf, 0x82, 0x4b, 0x4e,
-	0xb5, 0xf2, 0xc2, 0x0b, 0x88, 0x0a, 0x26, 0xac, 0x2e, 0x02, 0x08, 0x38,
-	0xce, 0xbd, 0x12, 0xd0, 0x1b, 0x6a, 0x82, 0xe2, 0xe9, 0xb2, 0x9a, 0x3c,
-	0x1f, 0x61, 0xa0, 0xac, 0xa6, 0x8d, 0x49, 0x60, 0xd6, 0xf5, 0x65, 0xda,
-	0xde, 0x9e, 0xda, 0x20, 0x67, 0x58, 0x0f, 0xd8, 0x71, 0xd4, 0x21, 0xf5,
-	0xef, 0x64, 0x91, 0x14, 0x1b, 0xc2, 0x2d, 0x8f, 0x5f, 0xa2, 0x09, 0xc4,
-	0x82, 0x7f, 0x3a, 0xca, 0xef, 0x5a, 0x12, 0x20, 0x0e, 0x68, 0x36, 0xf1,
-	0xe0, 0xa2, 0x03, 0x90, 0x68, 0x67, 0xdc, 0x6c, 0x44, 0x41, 0xc7, 0x49,
-	0xad, 0xa3, 0x93, 0xe7, 0xa3, 0xa1, 0x88, 0xd9, 0xf6, 0x14, 0x2d, 0x8a,
-	0xc2, 0x8f, 0xb9, 0x14, 0x06, 0xdc, 0x14, 0xd1, 0xe2, 0xf6, 0x04, 0x0b,
-	0x24, 0x42, 0x24, 0x8a, 0x2e, 0x09, 0x02, 0xeb, 0x55, 0x62, 0x57, 0x67,
-	0x34, 0xf0, 0xa4, 0x30, 0xb3, 0x06, 0xd9, 0xa3, 0x6c, 0xf3, 0x1f, 0x5f,
-	0x8f, 0x36, 0x82, 0x3c, 0x12, 0x97, 0x6a, 0xff, 0x84, 0xcd, 0x98, 0x88,
-	0xad, 0xc2, 0xa0, 0xcc, 0xea, 0x33, 0x7a, 0xc3, 0x7d, 0x29, 0x90, 0x1e,
-	0xd0, 0x3e, 0x2e, 0x0f, 0xa1, 0xc1, 0x16, 0x46, 0x1c, 0xcd, 0xb0, 0x4e,
-	0x44, 0x61, 0xa2, 0x77, 0x25, 0x40, 0xba, 0xe6, 0x89, 0xf8, 0xba, 0x5d,
-	0xe0, 0x4b, 0x6d, 0x8c, 0xe4, 0xe7, 0xf0, 0x5f, 0x13, 0x25, 0x51, 0x72,
-	0x3b, 0xeb, 0x32, 0xaf, 0x80, 0xde, 0xa6, 0x20, 0x63, 0x38, 0x43, 0x10,
-	0xf7, 0x8e, 0xfb, 0xd3, 0x06, 0xf9, 0x51, 0x98, 0xf8, 0xc1, 0x62, 0x0d,
-	0x23, 0x2b, 0x66, 0xd9, 0xe7, 0xd5, 0x03, 0xbb, 0xee, 0x36, 0xde, 0x5c,
-	0xd8, 0x22, 0x7c, 0x4b, 0xf9, 0x26, 0x63, 0x96, 0x6a, 0x4c, 0x9b, 0x59,
-	0xd0, 0xf2, 0xc4, 0xf8, 0x79, 0xf5, 0x43, 0x9b, 0xdf, 0x26, 0xeb, 0x2e,
-	0x80, 0xe2, 0x27, 0x9e, 0xd3, 0xa5, 0x45, 0x37, 0x4c, 0xbd, 0xf9, 0xb0,
-	0x23, 0xa1, 0x21, 0x4e, 0x1f, 0x6e, 0xdd, 0xac, 0xa6, 0x2c, 0x83, 0x61,
-	0xdf, 0x8f, 0x9a, 0xfb, 0x55, 0x0a, 0x88, 0x0b, 0x0b, 0x34, 0xbd, 0x35,
-	0x43, 0x2d, 0xe4, 0x49,
-};
-
-const struct rsa_public_key *rsa_key = (struct rsa_public_key *)rsa_data;
-BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
-
-/* SHA-256 sum to verify:
- * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
- */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
-
-/* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
-
-/* Generate signature using futility:
- * # futility create key.pem
- * # futility sign --type rwsig --prikey key.vbprik2 README README.out
- * # dd skip=56 bs=1 if=README.out | xxd -i
- */
-const uint8_t sig[] = {
-	0xad, 0x93, 0x9d, 0x5e, 0x4b, 0x66, 0xbd, 0xaa, 0xd0, 0x31, 0x15, 0x0f,
-	0x0c, 0x2c, 0x48, 0x61, 0xfc, 0x81, 0xef, 0xbf, 0x99, 0x7d, 0xc8, 0x51,
-	0x78, 0x84, 0xb0, 0x7c, 0x26, 0x09, 0x5c, 0x53, 0x36, 0x8c, 0xef, 0xef,
-	0x24, 0x71, 0xe8, 0xff, 0xa7, 0xac, 0x1a, 0xe3, 0xf7, 0xf3, 0x88, 0xde,
-	0xc8, 0x2c, 0x13, 0x29, 0x30, 0x90, 0xf9, 0xb0, 0xbc, 0x10, 0xcc, 0x72,
-	0xc7, 0xb0, 0x4c, 0x0e, 0x0c, 0x14, 0xe1, 0xca, 0x41, 0x4d, 0x3c, 0x40,
-	0x8e, 0x2e, 0x45, 0x90, 0x7a, 0xb4, 0xa5, 0xd6, 0x8f, 0xf6, 0xfb, 0xef,
-	0x51, 0x47, 0x60, 0x21, 0x6d, 0x6f, 0xae, 0x9b, 0xb1, 0x9b, 0x34, 0x48,
-	0x21, 0x9a, 0x5e, 0x70, 0xa3, 0x52, 0xa2, 0x00, 0x11, 0x20, 0x2d, 0x2a,
-	0xda, 0xc1, 0x23, 0x46, 0xbc, 0xb5, 0xa4, 0x0a, 0xec, 0x6a, 0x3a, 0xe4,
-	0x96, 0x17, 0x8a, 0x69, 0xce, 0x6f, 0xb0, 0x1d, 0x24, 0xd5, 0x20, 0x03,
-	0x0d, 0xe4, 0x6a, 0xf2, 0x8d, 0x19, 0x13, 0x7f, 0xd0, 0xe9, 0x51, 0xc7,
-	0x9b, 0x43, 0x11, 0xb4, 0x77, 0x1c, 0xed, 0xb9, 0xf0, 0xfc, 0xc3, 0xf7,
-	0x1a, 0xa0, 0x5e, 0x35, 0x2d, 0xc4, 0x35, 0x15, 0x42, 0xfa, 0x2f, 0xeb,
-	0xe6, 0xc6, 0xed, 0x98, 0x42, 0x93, 0xb1, 0x26, 0x61, 0x29, 0x37, 0xee,
-	0x87, 0x88, 0x7c, 0xc6, 0xa3, 0xd0, 0x5b, 0xaf, 0xb3, 0x19, 0xa1, 0x1d,
-	0x5f, 0x13, 0x37, 0x58, 0x33, 0x3b, 0xa8, 0xef, 0xea, 0x17, 0x87, 0x99,
-	0x43, 0xe3, 0x0a, 0x97, 0xdb, 0x8d, 0x54, 0x69, 0x33, 0x58, 0x9d, 0x2f,
-	0xfc, 0x32, 0x78, 0xca, 0x3a, 0x65, 0xca, 0x8e, 0x9b, 0x94, 0x18, 0xaa,
-	0xf0, 0x2b, 0x97, 0xcc, 0xa9, 0xd2, 0xd0, 0x8c, 0x73, 0xd6, 0x82, 0x99,
-	0xac, 0x07, 0x74, 0x47, 0x6e, 0x4c, 0x7b, 0xf9, 0x18, 0xf6, 0x13, 0x50,
-	0x9e, 0xea, 0xc7, 0x1c,
-	/* Padding */
-	0x00
-};
diff --git a/test/rsa2048-3.pem b/test/rsa2048-3.pem
deleted file mode 100644
index 0f89ecf9d3..0000000000
--- a/test/rsa2048-3.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEowIBAAKCAQEA2mX11mBJjaasoGEfPJqy6eKCahvQEr3OOAgCLqwmCogLwvK1
-TkuCvzHsbwOqkkUElq1t6nglKlCAnn5McF6wiZGmUpo/J/Fkk3M195qYkPKr1GHv
-NzqzWpFqNF+Z/weBGqxwJ+Xb0lWZydXMBPflm3/KMu7nLD3766seLL9/gAe7uKCD
-NWMeN5GKFZdhJUwSDoALkwNxvOLOakTTXAgL+csuVhqIgQmXminwsuw8aUT8BpSA
-8Rmu/OEdP6GL9jjli/4zenP72XiuSLrGAqYHYlLtXIgRmZVtsOUZUSPUU1KvlkTw
-cfI3E6CBps7ikHgYmrFnfXDhdm0ttaLv/TgXEQIBAwKCAQEAkZlOjurbs8RzFZYU
-0xHMm+xW8WfgDH6JerABdHLEBwVdLKHONDJXKiFISgJxttitucjz8aVuHDWrFFQy
-9ZR1sQvENxF/b/ZDDPd5T7xltfcdOEFKJNHM5wucIupmqgUAvHL1b+6SjDkRMTky
-rfqZElUxd0nvctP9R8dpcypVAAPsiicMqUCbqLyc+fovk8ooQ752pNZBYGI6VwgE
-PgXq2ltM/MAyZmH98R2/uSHTqa3kN5oYv36XnMwJ7LkMrZnipNcEKg+In3EGFhoF
-hiRGh4EFQd0yGx68Lq1DX5BhjZjDsDeAiKzSk2jJwcmr679cYokFfTj7zv2QtyEp
-rfeqSwKBgQDtpNcRRTuTkZEcmBiI6s8wtNtREo5l+ciGzB+IWXzp6UhRECYAEK6C
-hnlT6kLivQhHKyWMfn/ziXvqoduB8iU2Q8YWo8vjzLzhHAsnlq7fQx/IB5ShbRAc
-OiIfloAQbNpVfIpbGY1pbvlccuWmPn3KBfTTnx1vZLcTbkMvwFAevQKBgQDrRI7e
-8kahKOWCBoeQ3M2k9AcIiTOpsobwG5lEpYJByPnpytQ81sgYKgP9MvacLbfeiAfP
-U1vYCDMjurB2/6zbUPWWl5DLHZJEC4iWIsC+U/GdcielA9c3ML8Uq0sxkhM0kWdU
-i2GRx4n2kTq6cFtEAO8Lon34WznBNK4Bt/R45QKBgQCebeS2Lie3tmC9ursF8d91
-zeeLYbRD+9sEiBUFkP3xRjA2CsQACx8BrvuNRtdB01raHMOy/v/3sP1HFpJWoW4k
-LS65woftMyiWErIaZHSU12qFWmMWSLVoJsFqZFVgSJGOUwbnZl5GSfuS90PEKakx
-WU3iahOfmHoM9CzKgDVp0wKBgQCc2F8/TC8WG0OsBFpgkzPDTVoFsM0bzFn1Z7uD
-GQGBMKab3I195IVlcVf+Ifm9c8/psAU04j06sCIX0cr5/8iSNfkPD7XcvmGCslsO
-wdXUN/Zo9sUYrTokyyoNx4d2YWIjC5o4XOu2hQakYNHRoDzYAJ9dFv6lkiaAzclW
-eqL7QwKBgDgfnTj3blHv+u9PmxcStiP2LAh53fXutbqzkRTJ4y+Dzoi2NHrn0+uF
-LL61l2UDg+s/0oACZtaMV1Iqf/LdCEEb1IONE1OL6vm3WuKLB/QY82apnufP+TA5
-OujowZYvaIllZ2ujwPJ14t/XbFzBiaioLlPwIzyh5DFKA1hZJxSU
------END RSA PRIVATE KEY-----
diff --git a/test/rsa2048-F4.h b/test/rsa2048-F4.h
deleted file mode 100644
index afe66a198f..0000000000
--- a/test/rsa2048-F4.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * RSA 2048 with F4 exponent public key and verification.
- * Private key in rsa2048-F4.pem.
- */
-
-/* First generate a key:
- * # openssl genrsa -out key.pem 2048
- * # openssl rsa -in key.pem -pubout > key.pub
- * Then dump the key:
- * # dumpRSAPublicKey -pub key.pub | xxd -i
- */
-const uint8_t rsa_data[] = {
-	0x40, 0x00, 0x00, 0x00, 0xeb, 0xb6, 0x8c, 0xb4, 0x3d, 0xbe, 0xa2, 0xde,
-	0x0c, 0xa8, 0x6b, 0xcc, 0x1b, 0x58, 0x2e, 0x1b, 0x44, 0x3f, 0xda, 0xdb,
-	0x1d, 0xe1, 0xe4, 0xfd, 0x4b, 0xc5, 0x34, 0xc9, 0x7e, 0x58, 0xfc, 0x82,
-	0x6d, 0x95, 0x9f, 0x46, 0x01, 0xaf, 0x7c, 0xa1, 0x50, 0xd5, 0x9c, 0x22,
-	0xe1, 0x04, 0xcb, 0x41, 0x9a, 0xc4, 0xfe, 0xfa, 0xb6, 0x67, 0x89, 0x0f,
-	0xe5, 0x59, 0xa0, 0xd4, 0x55, 0xb3, 0xb1, 0x6f, 0x06, 0x28, 0x68, 0x1b,
-	0x0e, 0x25, 0x97, 0x47, 0xc6, 0xbe, 0x46, 0x14, 0x60, 0x77, 0x11, 0x46,
-	0xe2, 0x0c, 0x20, 0x59, 0x8c, 0x95, 0x87, 0x62, 0xe8, 0x05, 0xa9, 0xaf,
-	0x53, 0xab, 0x19, 0xca, 0xc0, 0xf4, 0x41, 0x05, 0x95, 0x3a, 0x6f, 0xd0,
-	0xdd, 0x87, 0xa7, 0xad, 0xcb, 0x5a, 0x43, 0x86, 0xb4, 0xf4, 0xe9, 0x45,
-	0x2a, 0x50, 0xe9, 0xe0, 0xf3, 0x16, 0x29, 0x87, 0xd9, 0xec, 0xc5, 0x48,
-	0xee, 0xf3, 0x53, 0xec, 0x18, 0x7f, 0x46, 0xdd, 0x4b, 0xb9, 0xf9, 0x4b,
-	0xcd, 0xe4, 0x2a, 0xc8, 0x7d, 0x1a, 0x5e, 0x58, 0x8b, 0x55, 0xf8, 0xed,
-	0x4d, 0x65, 0xc0, 0x4a, 0x8e, 0x27, 0x2f, 0x97, 0x82, 0x2f, 0x86, 0x69,
-	0xcf, 0xde, 0x00, 0x95, 0x0e, 0x90, 0x39, 0x12, 0x3e, 0x69, 0x2b, 0x7f,
-	0xd4, 0xc2, 0xb0, 0x4b, 0x89, 0x41, 0xb2, 0x8f, 0xb7, 0xfb, 0xed, 0xf3,
-	0x13, 0x1d, 0xb5, 0x01, 0x10, 0x00, 0xdf, 0x3a, 0xbe, 0x0d, 0x1f, 0x12,
-	0xd8, 0x9c, 0xeb, 0x30, 0xfa, 0x7e, 0x57, 0xde, 0x95, 0x7e, 0xdf, 0x06,
-	0x9f, 0x7e, 0x08, 0xfc, 0x4f, 0xd4, 0xfa, 0x8f, 0x9a, 0x8a, 0xc8, 0x03,
-	0xe7, 0xf2, 0xd0, 0x8e, 0x35, 0xb7, 0x33, 0x67, 0x02, 0x77, 0x1e, 0x8f,
-	0xe9, 0xc8, 0x80, 0x35, 0x6d, 0x24, 0xa2, 0xf9, 0x1c, 0x05, 0xd8, 0x1e,
-	0x79, 0x07, 0x7e, 0xd4, 0x48, 0xb8, 0x95, 0xfd, 0xf8, 0xb4, 0x0b, 0xd6,
-	0x29, 0x86, 0xb1, 0x7e, 0xbe, 0xf4, 0xe6, 0xfb, 0x24, 0x62, 0xf1, 0x00,
-	0x1c, 0xf1, 0x4a, 0x33, 0xea, 0x90, 0xf9, 0xbc, 0x5d, 0x4a, 0xf1, 0x6b,
-	0x07, 0xfe, 0x77, 0x62, 0x60, 0x83, 0xc2, 0x22, 0x54, 0xfa, 0x94, 0xf9,
-	0x59, 0x48, 0x62, 0x02, 0xd4, 0x97, 0x53, 0x3e, 0xfb, 0xfc, 0x06, 0x63,
-	0xf7, 0x28, 0x75, 0x34, 0x2c, 0xac, 0x98, 0xae, 0x8b, 0x78, 0xbd, 0x3c,
-	0x94, 0x58, 0x40, 0xdf, 0x8e, 0xec, 0x13, 0xcd, 0xe7, 0x20, 0xb8, 0x84,
-	0xda, 0xbd, 0x8e, 0x76, 0xbd, 0x1a, 0x7d, 0x3d, 0x18, 0x99, 0x91, 0x54,
-	0x19, 0xbb, 0xab, 0xbe, 0xc3, 0x8c, 0x0d, 0x23, 0x0b, 0xef, 0x5f, 0x1c,
-	0x49, 0xf0, 0xd1, 0x02, 0x81, 0x37, 0xc8, 0x75, 0x2e, 0xb9, 0x41, 0xf3,
-	0x90, 0xc4, 0xa2, 0xdc, 0x2f, 0xa2, 0x21, 0xd0, 0x8b, 0x3b, 0x40, 0x3a,
-	0xc4, 0x26, 0x7c, 0x7d, 0x7b, 0x79, 0xe2, 0x9b, 0xe3, 0xb7, 0x68, 0xd1,
-	0xcf, 0xc7, 0xce, 0x8c, 0x26, 0x8f, 0x2d, 0xd0, 0x89, 0xc3, 0x18, 0xd1,
-	0x07, 0x93, 0xa6, 0x1f, 0x9d, 0x13, 0x2a, 0xf2, 0xaf, 0xef, 0xbe, 0xb2,
-	0x02, 0x39, 0xd8, 0xd3, 0xeb, 0xdf, 0x97, 0xe7, 0x91, 0xb2, 0xc5, 0xd0,
-	0x21, 0x8f, 0xdd, 0x0c, 0x95, 0x30, 0xc0, 0x5b, 0xd6, 0x00, 0xd2, 0x62,
-	0x71, 0x89, 0x69, 0x2b, 0x22, 0x67, 0x05, 0x67, 0x1f, 0x02, 0x57, 0x6d,
-	0xc6, 0x3f, 0xed, 0xfe, 0x1f, 0x4c, 0x28, 0x7b, 0x36, 0x32, 0x3a, 0xa2,
-	0x61, 0xd2, 0x7a, 0xe1, 0xfd, 0x74, 0x02, 0xe3, 0x70, 0x76, 0x02, 0x19,
-	0x3a, 0x46, 0xe9, 0x86, 0x50, 0x6e, 0xce, 0x3f, 0x58, 0x0b, 0x0e, 0xef,
-	0xcf, 0x5a, 0xa2, 0x66, 0x7a, 0xa2, 0x0e, 0x02, 0x56, 0x87, 0x98, 0x67,
-	0x90, 0xf4, 0x9f, 0x3b, 0xf7, 0xaa, 0x1c, 0xd9, 0xda, 0x0d, 0x49, 0x12,
-	0x50, 0xa3, 0x70, 0x62,
-};
-
-const struct rsa_public_key *rsa_key = (struct rsa_public_key *)rsa_data;
-BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
-
-/* SHA-256 sum to verify:
- * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
- */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
-
-/* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
-
-/* Generate signature using futility:
- * # futility create key.pem
- * # futility sign --type rwsig --prikey key.vbprik2 README README.out
- * # dd skip=56 bs=1 if=README.out | xxd -i
- */
-const uint8_t sig[] = {
-	0x1a, 0xd8, 0xa0, 0x94, 0x1f, 0x96, 0x8c, 0x40, 0x22, 0xbf, 0xb7, 0xe0,
-	0x65, 0x30, 0xf8, 0xe1, 0xef, 0x9e, 0x70, 0x38, 0x02, 0xd9, 0x30, 0x10,
-	0x9f, 0xf9, 0x23, 0x34, 0xd8, 0xe3, 0x04, 0xed, 0x10, 0xcb, 0xde, 0x8b,
-	0xc3, 0x1e, 0x89, 0x58, 0x24, 0x90, 0xc1, 0x09, 0x3a, 0x08, 0xd9, 0x2f,
-	0x5b, 0xe9, 0xbe, 0x0c, 0x23, 0xd6, 0xd0, 0x5d, 0x1e, 0x85, 0x59, 0x62,
-	0xcb, 0x14, 0x76, 0x3f, 0x8f, 0xe6, 0xb9, 0xd2, 0xbd, 0x1c, 0xef, 0xd6,
-	0xb0, 0x21, 0xaf, 0x3d, 0x93, 0x6d, 0x2d, 0x78, 0x31, 0x87, 0x37, 0xab,
-	0xfe, 0xca, 0xe8, 0x32, 0xda, 0x86, 0x67, 0x48, 0x0e, 0xab, 0xd0, 0xdd,
-	0x14, 0x39, 0xe5, 0x8e, 0x65, 0xbb, 0x28, 0xe6, 0xcd, 0xb7, 0xad, 0xbe,
-	0x86, 0x95, 0xec, 0xf5, 0xc0, 0x00, 0x45, 0x92, 0x3d, 0x67, 0xd7, 0xb6,
-	0x30, 0x60, 0x6c, 0x6d, 0x86, 0xb5, 0xb5, 0x97, 0xe7, 0x52, 0xca, 0xa4,
-	0x21, 0xae, 0x48, 0xf9, 0x4a, 0xc8, 0xad, 0xeb, 0xd6, 0x0b, 0xa4, 0x58,
-	0x61, 0xf2, 0xaf, 0xbc, 0x2a, 0xe6, 0xd7, 0x78, 0x23, 0x66, 0x9c, 0x12,
-	0x87, 0x54, 0x30, 0x68, 0x4b, 0xdb, 0xc2, 0x66, 0xf6, 0x4b, 0x49, 0x44,
-	0xbd, 0xb9, 0x1a, 0xdc, 0x71, 0x0f, 0xa4, 0x63, 0xfc, 0x56, 0x41, 0x91,
-	0xe5, 0x30, 0xb6, 0xa9, 0xe6, 0x8c, 0x6f, 0x91, 0x8e, 0x36, 0xd6, 0x4d,
-	0xe1, 0xdd, 0x0e, 0x1d, 0x1a, 0x71, 0x51, 0x68, 0xf6, 0xf3, 0xea, 0x74,
-	0x3a, 0x5f, 0x35, 0x6a, 0x0f, 0xd4, 0x86, 0x96, 0x3e, 0x89, 0xab, 0x88,
-	0x03, 0x40, 0xe2, 0x2b, 0x72, 0xa5, 0xa5, 0xf7, 0x79, 0xd0, 0x5a, 0xcb,
-	0xfa, 0x40, 0x12, 0xe2, 0x0c, 0xf0, 0xfb, 0xd8, 0x9c, 0x41, 0x30, 0xab,
-	0x99, 0x5d, 0x26, 0xe0, 0x6a, 0xcf, 0x0b, 0x4b, 0x4f, 0xe4, 0x85, 0xe6,
-	0x8d, 0xe3, 0x11, 0xe0,
-	/* Padding */
-	0x00
-};
diff --git a/test/rsa2048-F4.pem b/test/rsa2048-F4.pem
deleted file mode 100644
index 1662f8ebb5..0000000000
--- a/test/rsa2048-F4.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEowIBAAKCAQEA1gu0+P2VuEjUfgd5HtgFHPmiJG01gMjpjx53AmcztzWO0PLn
-A8iKmo/61E/8CH6fBt9+ld5Xfvow65zYEh8NvjrfABABtR0T8+37t4+yQYlLsMLU
-fytpPhI5kA6VAN7PaYYvgpcvJ45KwGVN7fhVi1heGn3IKuTNS/m5S91GfxjsU/Pu
-SMXs2YcpFvPg6VAqRen0tIZDWsutp4fd0G86lQVB9MDKGatTr6kF6GKHlYxZIAzi
-RhF3YBRGvsZHlyUOG2goBm+xs1XUoFnlD4lntvr+xJpBywThIpzVUKF8rwFGn5Vt
-gvxYfsk0xUv95OEd29o/RBsuWBvMa6gM3qK+PQIDAQABAoIBAAc0ca0H7Cg921k6
-qysMnm9xP7H2MxzYpnP41IyyKJ18IgiKhJguAexd+FV5M8SdboDuuPYWe998UHU9
-3FAP14iVtrfr0gLkra1CT3zIS3nFQ1T52elF7s72EhX1R7K1zUmCCMteh2nPcliz
-kEH4X/jGyrQdk8VN2lM6XrBdDGhuwI6iGA+/lxc8xJAmNvpw6qPVAacv1/2af7/u
-s37JD/jpyCibhMvoguRDDozeWckWNcFEhICz6fmwCUHIG48XwwWV2sHPimG1WNwb
-uF6Ma5VxnUNHvNG8uAEy4437AKxBGIVVresTyfDpY2LSIpWAPag/MXEoUBBjcOTm
-8L5IjMkCgYEA9cZH0rrkUEHH+OajhWO1Ca/tgICxRn5PdlYHGhFXv1va5XPZbEdL
-R8s4Gth5c7jLqjehbfOv8p070oz1KMYsrjO+WpZbxmTzse1TzHEaZhwfdt09+y+v
-43dKZgMoj1whlILOWw39cS9jrbh7YWLeAYydwy2/V8pw/7MVFY0a2gsCgYEA3vN8
-cpudgrv4TnyVKJ388hSEwMVp2wompfou5toumlOnGosnQvcgXBt0EsJJUiD9KYOo
-wQDeExTGAkHntcU2VJuqsO3Wn7sI8gXQbU1XUTqhqEsLftWkKj2reLe09rGYWlSw
-ad5miBH4LTSO/2wZfUSxfxBaTcS7ISna9NsDPdcCgYAMQmCwxTvAORfFdZOwgqG0
-Iv9gyoqNLp2+FFp0VWsgE2/exCGTQhciNKPOyv974zrdebrmpiIfovIp9XgBGal+
-4vvavudDBSQWuvTUHMwpTbvQDQcbcWx/lyKx5fRu+jR+mOu8JP2AWNHLB4m3+NuE
-DkSMSMrjkSiDyKYDli9BswKBgQCAwysKnelYSetcmQMkVCp0PXl2RA2g3bn4fgd8
-eGIV615FLDzepg9gYtKkyuTBtB/CTDG4ViHr70F0qE+EYYPBVa49RP+BfOnrrYP0
-vIhDd5NJuR3IgOaxJrDTpXW0TFlrQiIo4rNgvtAQe5xi1DHccUH52p3s8EQLITs9
-0weKPQKBgANF9UkCnISX6HeOJmvSg9dBSZlQMON3Jwk01yTH9fDxFykfip6y/RC4
-izprxpUjWJIGlAAR/nW+/gGaK0EhuCnWcmE46u0ho6ylqpkScrKQ8jPqXoZ9gqn0
-uyKzLlyv0r+jEs87SWBjKc1Lt84piq93dNrlzXkf4/zCDPif5vML
------END RSA PRIVATE KEY-----
diff --git a/test/rsa3.tasklist b/test/rsa3.tasklist
deleted file mode 120000
index 6cfe0ef051..0000000000
--- a/test/rsa3.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-rsa.tasklist
\ No newline at end of file
diff --git a/test/rsa3072-3.h b/test/rsa3072-3.h
deleted file mode 100644
index c407a4ed2b..0000000000
--- a/test/rsa3072-3.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * RSA 3072 with 3 exponent public key and verification.
- * Private key in rsa3072-3.pem.
- */
-
-/* First generate a key:
- * # openssl genrsa -3 -out key.pem 3072
- * # openssl rsa -in key.pem -pubout > key.pub
- * Then dump the key: sudo emerge vboot_reference
- * # /usr/bin/dumpRSAPublicKey -pub key.pub | xxd -i
- */
-const uint8_t rsa_data[] = {
-	0x60, 0x00, 0x00, 0x00, 0xdd, 0x54, 0xe6, 0xe2, 0x8b, 0xdc, 0xea, 0xd2,
-	0x58, 0x10, 0x72, 0xf1, 0x39, 0x2d, 0x10, 0x6e, 0x37, 0x4b, 0x19, 0x0d,
-	0x0a, 0x02, 0x80, 0xdc, 0xb9, 0xee, 0xb4, 0x6b, 0xb6, 0x19, 0x73, 0x22,
-	0x43, 0x09, 0x22, 0x7e, 0xf1, 0x48, 0xdd, 0xf2, 0x66, 0x12, 0x90, 0xb9,
-	0x58, 0x54, 0x4b, 0xc4, 0xce, 0xf0, 0xb3, 0xbf, 0xad, 0x86, 0x1a, 0x6a,
-	0x23, 0x66, 0x08, 0x10, 0x83, 0xda, 0xa3, 0xec, 0x8e, 0x36, 0x2d, 0xb2,
-	0x91, 0x2c, 0xbd, 0x11, 0x2f, 0xa8, 0xdc, 0x8f, 0x52, 0x7a, 0x23, 0x58,
-	0xad, 0x36, 0x9b, 0xde, 0xd6, 0x0d, 0x21, 0x1b, 0x5d, 0x7b, 0x1d, 0x51,
-	0x6d, 0x7e, 0xa1, 0xca, 0x13, 0x0a, 0x11, 0x29, 0x63, 0xaa, 0x6e, 0x64,
-	0x7a, 0x15, 0xa3, 0xf6, 0xed, 0xfd, 0xce, 0x5d, 0x17, 0xfb, 0x16, 0x38,
-	0x55, 0x0b, 0xed, 0x6b, 0x12, 0xf9, 0xcf, 0x8b, 0xa7, 0xeb, 0x92, 0xd0,
-	0x5e, 0x91, 0x91, 0x4e, 0x6e, 0x41, 0xa2, 0x88, 0x51, 0xf9, 0xf9, 0x0b,
-	0x99, 0x72, 0x2e, 0xab, 0x50, 0xbb, 0xc6, 0xc0, 0x64, 0x88, 0x26, 0x7f,
-	0xc1, 0x91, 0x8d, 0xe8, 0xea, 0x5a, 0x15, 0x1c, 0x0a, 0xac, 0xa3, 0x8a,
-	0x8f, 0x42, 0x68, 0xc6, 0x7d, 0x3a, 0x53, 0xf6, 0x6a, 0x65, 0x7a, 0xb4,
-	0x51, 0xf0, 0xce, 0xe3, 0x49, 0xd8, 0x38, 0x1a, 0x30, 0x1a, 0xd3, 0xa2,
-	0x98, 0xf8, 0x53, 0x6d, 0xa2, 0x35, 0x22, 0x92, 0xd8, 0x46, 0x7b, 0x9d,
-	0xc7, 0x25, 0xb6, 0xc6, 0x28, 0x12, 0x0d, 0x0d, 0x91, 0xbf, 0x9b, 0x58,
-	0x73, 0xc1, 0x78, 0x39, 0xed, 0x16, 0x61, 0x90, 0x25, 0x14, 0xba, 0x9b,
-	0x17, 0x4f, 0xaa, 0xf9, 0x5c, 0xfd, 0xc7, 0x18, 0xf3, 0x1d, 0xd7, 0xaa,
-	0xea, 0x11, 0x18, 0xbb, 0x24, 0x3d, 0xf0, 0x57, 0x33, 0x9c, 0x23, 0x04,
-	0x33, 0x81, 0xa0, 0x10, 0xc3, 0x6d, 0x12, 0xb6, 0xd0, 0xdc, 0xad, 0xd2,
-	0x9c, 0x76, 0x01, 0x7a, 0x70, 0x04, 0x72, 0x29, 0xeb, 0x82, 0x60, 0x1b,
-	0xea, 0x19, 0xe6, 0xdc, 0xeb, 0xec, 0xaf, 0xad, 0xce, 0xfa, 0x5b, 0xbc,
-	0x81, 0x0c, 0x82, 0x19, 0xde, 0xbd, 0x65, 0xe6, 0x69, 0x1b, 0x8e, 0x38,
-	0x93, 0xf3, 0x3f, 0x9f, 0x75, 0x69, 0xa9, 0x0f, 0xb7, 0x94, 0xca, 0xfd,
-	0x30, 0xa9, 0x09, 0x59, 0x77, 0xd3, 0xef, 0x8d, 0x0a, 0x11, 0xfa, 0x07,
-	0xd8, 0xe5, 0x35, 0x59, 0x23, 0xb5, 0x20, 0x28, 0xa7, 0x9f, 0x6d, 0xb6,
-	0x18, 0x72, 0x51, 0x06, 0x02, 0xe7, 0x2b, 0xfb, 0xa5, 0x96, 0xf8, 0x8b,
-	0x2d, 0xb4, 0x01, 0xd8, 0x66, 0xd0, 0x12, 0xa3, 0xd3, 0x67, 0x94, 0x37,
-	0x21, 0xb4, 0xfc, 0xc5, 0x73, 0xd7, 0x77, 0x39, 0x75, 0xdd, 0xb2, 0x57,
-	0x62, 0x83, 0xcd, 0x2d, 0xca, 0x8a, 0xf9, 0xd8, 0xc3, 0x00, 0xc2, 0x64,
-	0x45, 0xaa, 0xaa, 0xe7, 0xf8, 0xdb, 0x9c, 0xd4, 0x33, 0x77, 0x5b, 0x55,
-	0x57, 0x12, 0xcd, 0x33, 0xbe, 0x70, 0xa5, 0x78, 0x26, 0x3c, 0x56, 0xee,
-	0xe3, 0xac, 0x23, 0xfe, 0x54, 0x98, 0xd6, 0x2e, 0xfe, 0xdd, 0xc4, 0x5a,
-	0x23, 0xca, 0x5a, 0x22, 0xec, 0x8e, 0x36, 0x3b, 0xfb, 0x9f, 0x97, 0x7d,
-	0x75, 0x37, 0xf7, 0x59, 0xef, 0x1d, 0x96, 0xad, 0x2b, 0x82, 0x19, 0x67,
-	0x46, 0x7f, 0x92, 0x1f, 0xcb, 0xf0, 0xf7, 0x31, 0x72, 0x34, 0x4d, 0xdd,
-	0x8b, 0x5b, 0x90, 0xe2, 0xeb, 0xdd, 0x04, 0x00, 0xde, 0x28, 0x15, 0x03,
-	0x6b, 0x4e, 0x4e, 0x6b, 0x03, 0xd0, 0x54, 0x81, 0xea, 0xe4, 0x26, 0xbb,
-	0x4c, 0x6f, 0x65, 0x70, 0x12, 0x6d, 0x84, 0x1d, 0x71, 0xfe, 0xc1, 0x63,
-	0x1c, 0x33, 0x43, 0xcd, 0x8a, 0x92, 0xa6, 0x2d, 0xa3, 0xbd, 0xef, 0x93,
-	0x39, 0x2f, 0x9b, 0xa9, 0x5c, 0x0d, 0xb9, 0x61, 0x23, 0xcf, 0x12, 0x1f,
-	0x98, 0x85, 0x19, 0xa7, 0x08, 0xfc, 0xee, 0x8e, 0x79, 0x25, 0x0b, 0xed,
-	0xb3, 0x72, 0xf4, 0x27, 0x9f, 0xee, 0x7b, 0x22, 0xd0, 0x6e, 0xdf, 0x4b,
-	0x05, 0xef, 0xbd, 0x13, 0xb6, 0x22, 0xeb, 0x9e, 0xc5, 0x7d, 0xb6, 0x1c,
-	0xfd, 0xf8, 0xc6, 0x82, 0x89, 0xd2, 0xc4, 0x01, 0xac, 0xec, 0xd5, 0xbd,
-	0x2d, 0xbb, 0x09, 0x17, 0x0f, 0xd6, 0xc1, 0xb9, 0x07, 0xf0, 0xce, 0x23,
-	0x81, 0x0c, 0xa9, 0x60, 0x58, 0x17, 0xbf, 0xf5, 0x14, 0xd0, 0x68, 0x33,
-	0xf6, 0xc6, 0xae, 0xc3, 0xc3, 0x1f, 0x01, 0xd6, 0xae, 0xc8, 0x94, 0xba,
-	0x35, 0x47, 0xa9, 0x77, 0x2b, 0x68, 0xd2, 0x75, 0x19, 0x75, 0x40, 0xce,
-	0x11, 0x93, 0xaa, 0xb9, 0x09, 0x37, 0x91, 0xca, 0x83, 0x3d, 0x7a, 0xb1,
-	0x03, 0x57, 0x34, 0x06, 0x37, 0x86, 0xf9, 0x64, 0xe4, 0xcf, 0x49, 0x0b,
-	0x20, 0x21, 0xda, 0x0a, 0x25, 0xd4, 0x17, 0x21, 0x73, 0x39, 0xf9, 0x2f,
-	0xeb, 0x81, 0x6f, 0x90, 0xea, 0x83, 0xfc, 0xc7, 0xe9, 0x44, 0xd1, 0xd2,
-	0x8b, 0xc5, 0xf3, 0x1f, 0x35, 0x1c, 0xc5, 0xa3, 0x75, 0x36, 0xb7, 0x84,
-	0xed, 0x67, 0xa0, 0xbd, 0xaf, 0x6b, 0x00, 0x15, 0x5a, 0x7c, 0x5c, 0xc7,
-	0x95, 0x22, 0x76, 0xd9, 0x9c, 0x1f, 0xf0, 0xb2, 0x6e, 0x5b, 0xcb, 0x32,
-	0x88, 0xa4, 0xc6, 0x7f, 0xfa, 0x2e, 0xc6, 0x40, 0x40, 0xa3, 0xe2, 0x57,
-	0xb7, 0x08, 0xe0, 0xe9, 0x93, 0x10, 0x95, 0x70, 0x2d, 0x90, 0x0c, 0xeb,
-	0x44, 0x50, 0xbc, 0xd9, 0xc7, 0xd5, 0x2b, 0x74, 0xac, 0x6e, 0x7f, 0xcf,
-	0xfa, 0x8c, 0xf6, 0x76, 0x77, 0x79, 0xf8, 0xf4, 0x11, 0x8e, 0x5a, 0xe4,
-	0x2c, 0xa2, 0x84, 0x56, 0xdb, 0x39, 0x54, 0x82, 0x8e, 0x85, 0x31, 0xc0,
-	0x51, 0xf7, 0x6c, 0x2c, 0x5f, 0xbc, 0x63, 0x5c, 0xf3, 0x68, 0x4e, 0xa4,
-	0x52, 0xc9, 0xe8, 0x06, 0xff, 0x94, 0xd3, 0xa1,
-};
-
-const struct rsa_public_key *rsa_key = (struct rsa_public_key *)rsa_data;
-BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
-
-/* SHA-256 sum to verify:
- * # sha256sum README.md | sed -e 's/\(..\)/0x\1, /mg'
- */
-const uint8_t hash[] = { 0xc7, 0xc3, 0xd0, 0xa3, 0x7e, 0xbd, 0x50, 0xe8,
-			 0x3c, 0xb3, 0x5b, 0xed, 0x02, 0xf9, 0x8f, 0x97,
-			 0xf8, 0xb5, 0x23, 0x43, 0x74, 0xda, 0x0a, 0x24,
-			 0xdb, 0x04, 0xe4, 0x1e, 0xbd, 0x43, 0x02, 0xdc };
-
-/* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
-			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
-			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
-
-/* Generate signature using openssl:
- * openssl dgst -sha256 -sign test/rsa3072-3.pem README.md | xxd -i
- */
-const uint8_t sig[] = {
-	0xb3, 0xac, 0xcb, 0x5c, 0xbc, 0x82, 0x74, 0x14, 0xce, 0x7d, 0xbd, 0x3b,
-	0xc6, 0x6e, 0x2d, 0x3e, 0xfd, 0xdb, 0x76, 0xb3, 0xfe, 0xed, 0x29, 0xd6,
-	0xb8, 0x20, 0x8a, 0x79, 0xf8, 0xe4, 0x1b, 0xc1, 0x99, 0x21, 0x77, 0xb0,
-	0xa7, 0x49, 0xfc, 0x31, 0x70, 0xe2, 0x5c, 0xc9, 0xc4, 0xc8, 0x5b, 0xbd,
-	0xf9, 0xc9, 0x81, 0x43, 0x7e, 0x16, 0x23, 0xc7, 0xb3, 0x8f, 0x95, 0xca,
-	0xb2, 0x56, 0x96, 0xfc, 0x53, 0xba, 0xf3, 0x77, 0x31, 0xde, 0x69, 0x9f,
-	0x2e, 0xb1, 0xc0, 0xe1, 0xb9, 0x05, 0x7a, 0xf2, 0x92, 0x9c, 0xf2, 0x0b,
-	0x54, 0xa1, 0x93, 0x58, 0x52, 0x2e, 0x9b, 0x02, 0x59, 0x05, 0x67, 0xc2,
-	0x8c, 0x27, 0x1d, 0xc2, 0x70, 0x2f, 0x5c, 0x4f, 0xb2, 0xb4, 0x87, 0x71,
-	0x75, 0x33, 0x2d, 0x96, 0x02, 0x81, 0x80, 0x13, 0xb1, 0xff, 0x8a, 0x73,
-	0x1c, 0x66, 0x54, 0xec, 0x97, 0x08, 0x4f, 0x98, 0xec, 0x01, 0xa6, 0x93,
-	0x59, 0xa9, 0x16, 0x28, 0x41, 0x60, 0x83, 0xb2, 0xe1, 0xe8, 0x42, 0xf7,
-	0x92, 0x96, 0x5c, 0x91, 0x06, 0xf8, 0xde, 0x45, 0x67, 0x4e, 0xef, 0xde,
-	0xb5, 0x87, 0x72, 0x02, 0x5e, 0x39, 0x7a, 0xa7, 0xf2, 0x22, 0xbc, 0x10,
-	0x59, 0x13, 0xfb, 0x53, 0x98, 0x99, 0x2a, 0x51, 0xc5, 0x46, 0x7e, 0xdf,
-	0x6f, 0xd8, 0xbd, 0xcd, 0x0e, 0xd7, 0x00, 0x2f, 0x76, 0x17, 0x8b, 0xce,
-	0x05, 0x56, 0xc2, 0xe1, 0xcd, 0x37, 0xa1, 0x2f, 0xa6, 0xc4, 0xcd, 0xd5,
-	0xaf, 0x10, 0x9b, 0x1f, 0x72, 0x28, 0x14, 0x3f, 0xa1, 0x9d, 0x08, 0x7f,
-	0x3d, 0x0a, 0xac, 0x80, 0x7b, 0xe3, 0x31, 0x4f, 0x9c, 0x79, 0x7c, 0x4b,
-	0xd7, 0x01, 0xcc, 0x9f, 0xbd, 0x9d, 0x52, 0x84, 0xd7, 0xea, 0xf8, 0xc8,
-	0xf5, 0xf3, 0x0c, 0x83, 0x5c, 0x30, 0x0c, 0x50, 0x66, 0x5f, 0xee, 0x4d,
-	0x23, 0x8a, 0x32, 0x07, 0x55, 0xb1, 0xfa, 0x5e, 0x89, 0x57, 0x18, 0x24,
-	0xcc, 0x20, 0x30, 0x79, 0xf0, 0x4c, 0x09, 0xe2, 0x9a, 0x34, 0xc7, 0x07,
-	0xf7, 0x29, 0x3a, 0xcf, 0x38, 0x18, 0x2c, 0x53, 0x2f, 0x33, 0xca, 0x95,
-	0xfc, 0x3b, 0x23, 0x75, 0xbc, 0x15, 0xac, 0x1a, 0xbd, 0xf1, 0xa5, 0x6c,
-	0x3e, 0x4b, 0xc3, 0x39, 0xb2, 0x1e, 0x18, 0xf1, 0xb9, 0x28, 0xcd, 0x13,
-	0x05, 0x32, 0xd5, 0x46, 0x3e, 0x9b, 0x55, 0x9f, 0x13, 0xe3, 0x5d, 0x53,
-	0x6a, 0xa8, 0x93, 0x33, 0xbb, 0x78, 0x1d, 0x3a, 0xeb, 0xbd, 0x3d, 0x2e,
-	0xd1, 0xdc, 0x1c, 0xb6, 0x76, 0x6f, 0x29, 0x9f, 0x9f, 0x59, 0x23, 0x45,
-	0xcc, 0x80, 0x23, 0xd7, 0x51, 0x06, 0xc8, 0x72, 0x94, 0x3a, 0xf8, 0x14,
-	0x4d, 0x76, 0x2d, 0x59, 0x3c, 0xd7, 0x4e, 0x17, 0x52, 0xad, 0x1a, 0xe4,
-	0xa9, 0xfb, 0x09, 0xc8, 0xb4, 0x28, 0x0b, 0x7d, 0xa8, 0x0a, 0x71, 0x81,
-	/* Padding */
-	0x00
-};
diff --git a/test/rsa3072-3.pem b/test/rsa3072-3.pem
deleted file mode 100644
index 78fbce265e..0000000000
--- a/test/rsa3072-3.pem
+++ /dev/null
@@ -1,39 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIG4wIBAAKCAYEA1Jzb+OeqqkVkwgDD2PmKyi3Ng2JXst11OXfXc8X8tCE3lGfT
-oxLQZtgBtC2L+Jal+yvnAgZRchi2bZ+nKCC1I1k15dgH+hEKje/Td1kJqTD9ypS3
-D6lpdZ8/85M4jhtp5mW93hmCDIG8W/rOra/s69zmGeobYILrKXIEcHoBdpzSrdzQ
-thJtwxCggTMEI5wzV/A9JLsYEeqq1x3zGMf9XPmqTxebuhQlkGEW7Tl4wXNYm7+R
-DQ0SKMa2Jcede0bYkiI1om1T+Jii0xowGjjYSePO8FG0emVq9lM6fcZoQo+Ko6wK
-HBVa6uiNkcF/JohkwMa7UKsucpkL+flRiKJBbk6RkV7Qkuuni8/5EmvtC1U4FvsX
-Xc797fajFXpkbqpjKREKE8qhfm1RHXtdGyEN1t6bNq1YI3pSj9yoLxG9LJGyLTaO
-7KPagxAIZiNqGoatv7PwzsRLVFi5kBJm8t1I8X4iCUMicxm2a7TuudyAAgoNGUs3
-bhAtOfFyEFjS6tyLAgEDAoIBgQCNvef7RRxxg5iBVdfl+7HcHokCQY/Mk6N7pTpN
-Lqh4FiUNmo0XYeBEkAEiyQf7DxlSHUSsBDZMEHmeam9wFc4XkM6ZOq/8C1xen+JP
-kLEbdf6HDc9fxkZOaiqiYiW0EkaZmSk+u6wIVn2SpzRzyp3yk0QRRrzrAfIboVhK
-/AD5veHJPeB5YZ6CCxWrd1gXvXeP9X4YfLq2nHHkvqIQhVOTURw0umfRYsO1lg9I
-0PsrojsSf7YIs2FwhHluhROnhI8qFy2Va0j/5ypoKtWitNOUb2K//I/E5a8s7N86
-GhG0Vn0iolTxgJfj5kI0/5B5jXRYrLCvOJvnmOL6rbR1HPOmSC62VorgvsF3ExXh
-Z+9mpjMjDdHZAZRLpr8Toj7nZabbIGZMfLFFutSvVXSvhNPezKeREJ3uS65E0oeK
-Vl3qi5IZA02X7WrlYJYop7HGH/ZSqR+iIIJEHhYhLt5oST3XZ3cSEUTupyWE1cxm
-2HBkuUULO8eIo9CmLEnLxUUjZlsCgcEA8yLuYy3pfAdUOJulycDHuTjN4BAsqXLV
-lpO/6Cq+jeNzChobcpWWUsx0E3gjaUfRTEEuSoHo/oHUIFjOGdv1VdsZjXIh0RS+
-3ltf2zMHoTwnsHIDrAIdyLMEylDQXefpKsievPj8YJx180/ZUcmaCV2s0YL//vxg
-moL3ynXkQQhHSbwz+TSEOkdU5r6G1TNiJnup3W3+elB7zmyU4yFboNC5P1clLiVM
-9InAq1mLn2CP9GCqtJTnU1ij55929C8NAoHBAN/cgt8efPy2jv4+Sdxo0zID7PBG
-sCmaDpxcK750jyYqW+Webz8+4MJCti7KAwbsZO+Cg/9UW5ix42Gb9L8a3p8HMfJq
-3nC4xnrX+GUc/lAfw7H0WOxKgbPJf622NbWp/7WX0eQWmzU4nCMrVMIQNf9N8wuR
-az8MbI4d5RUaTAu4D731Zo+LNfC30kJpWJwjWh06l34liXPbHI/fhHNOEI2SNi7S
-Fd75sS/qe3Q+S8uTlZQQ4WyFjO1WX3cRdEGT9wKBwQCiF0mXc/D9WjglvRkxKy/Q
-0IlACshw9zkPDSqaxymz7PdcEWehuQ7h3aK3pWzw2ouIK3Qxq/Cpq+LAOzQRPU45
-PLuzoWvguH8+55U8zK/A0sUgTAJyrBPbIgMxizWT7/DHMGnTUKhAaE6iNTuL27wG
-PnM2V1VUqEBnAfqG+ULWBYTb0s1Qza18L43vKa84zOwZp8aTnqmm4FKJnbiXa5Jr
-NdDU5MN0GN34W9XHkQe/lbVNlccjDe+M5cKaak9NdLMCgcEAlT2slL79/c8J/tQx
-PZs3dq1IoC8gG7wJvZLH1E20xBw9Q7701NSV1tckHzFXWfLt9QGtVOLnuyFCQRKj
-KhHpv1ohTEc+9dCEUeVQQ2ipir/Xy/g7SDGrzTD/ySQjznFVI7qL7WRneNBoF3I4
-gWAj/4lMsmDyKghIXr6YuLwysnq1KU5EX7Ij9c/hgZuQaBeRaNG6VBkGTTy9tT+t
-ojQLCQwkHza5P1EgypxSTX7dMmJjuAtA8wOzSOQ/pLZNgQ1PAoHAbZMZo5yF+yzC
-Ofu/Wq38ftt3KGzaiN+xwPu8MG8jFLNnQXCpI+qiszBK0lkS3W/yPlouUYJXfbec
-LCp/z+lfUe5glm7AUxvuSZ63ZBTx8q/Vgl7490mzFzOSoL5iBtnq3qzwGHWfM0au
-h3hlTdBpYnuIGqcU910JsJ3tdzcLoJe9OaihQrgBudGftAr9nm3uuvLtVRuHSAP1
-m6u+qq5Ae/0ejhJWnyPcYE4Gnv4JWLRYywBT0WpdSNiV/3aAPoq3
------END RSA PRIVATE KEY-----
diff --git a/test/rtc.c b/test/rtc.c
deleted file mode 100644
index 3e53f85611..0000000000
--- a/test/rtc.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests for rtc time conversions
- */
-
-#include "console.h"
-#include "common.h"
-#include "rtc.h"
-#include "test_util.h"
-#include "util.h"
-
-/* Known conversion pairs of date and epoch time. */
-static struct {
-	struct calendar_date time;
-	uint32_t sec;
-} test_case[] = {
-	{{8, 3, 1}, 1204329600},
-	{{17, 10, 1}, 1506816000},
-};
-
-static int calendar_time_comp(struct calendar_date time_1,
-			   struct calendar_date time_2)
-{
-	return (time_1.year == time_2.year &&
-		time_1.month == time_2.month &&
-		time_1.day == time_2.day);
-}
-
-static int test_time_conversion(void)
-{
-	struct calendar_date time_1;
-	struct calendar_date time_2;
-	uint32_t sec;
-	int i;
-
-	/* The seconds elapsed from 01-01-1970 to 01-01-2000 */
-	sec = SECS_TILL_YEAR_2K;
-	time_1.year = 0;
-	time_1.month = 1;
-	time_1.day = 1;
-
-	/* Test from year 2000 to 2050 */
-	for (i = 0; i <= 50; i++) {
-		/* Test Jan. 1 */
-		time_1.year = i;
-		time_1.month = 1;
-		time_1.day = 1;
-
-		TEST_ASSERT(date_to_sec(time_1) == sec);
-		time_2 = sec_to_date(sec);
-		TEST_ASSERT(calendar_time_comp(time_1, time_2));
-
-		/* Test the day boundary between Jan. 1 and Jan. 2 */
-		time_2 = sec_to_date(sec + SECS_PER_DAY - 1);
-		TEST_ASSERT(calendar_time_comp(time_1, time_2));
-
-		time_1.day = 2;
-
-		TEST_ASSERT(date_to_sec(time_1) == sec + SECS_PER_DAY);
-		time_2 = sec_to_date(sec + SECS_PER_DAY);
-		TEST_ASSERT(calendar_time_comp(time_1, time_2));
-
-		/*
-		 * Test the month boundary and leap year:
-		 * Is the 60th day of a year Mar. 1 or Feb. 29?
-		 */
-		time_2 = sec_to_date(sec + 59 * SECS_PER_DAY);
-		if (IS_LEAP_YEAR(i))
-			TEST_ASSERT(time_2.month == 2 && time_2.day == 29);
-		else
-			TEST_ASSERT(time_2.month == 3 && time_2.day == 1);
-
-		/* Test the year boundary on Dec. 31 */
-		sec += SECS_PER_YEAR - (IS_LEAP_YEAR(i) ? 0 : SECS_PER_DAY);
-		time_1.month = 12;
-		time_1.day = 31;
-
-		TEST_ASSERT(date_to_sec(time_1) == sec);
-		time_2 = sec_to_date(sec);
-		TEST_ASSERT(calendar_time_comp(time_1, time_2));
-
-		sec += SECS_PER_DAY;
-		time_2 = sec_to_date(sec - 1);
-		TEST_ASSERT(calendar_time_comp(time_1, time_2));
-	}
-
-	/* Verify known test cases */
-	for (i = 0; i < ARRAY_SIZE(test_case); i++) {
-		TEST_ASSERT(date_to_sec(test_case[i].time) == test_case[i].sec);
-		time_1 = sec_to_date(test_case[i].sec);
-		TEST_ASSERT(calendar_time_comp(time_1, test_case[i].time));
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_time_conversion);
-
-	test_print_result();
-}
diff --git a/test/rtc.tasklist b/test/rtc.tasklist
deleted file mode 100644
index 80072bb620..0000000000
--- a/test/rtc.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/run_device_tests.py b/test/run_device_tests.py
deleted file mode 100755
index 8207f83f66..0000000000
--- a/test/run_device_tests.py
+++ /dev/null
@@ -1,519 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Runs unit tests on device and displays the results.
-
-This script assumes you have a ~/.servodrc config file with a line that
-corresponds to the board being tested.
-
-See https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo.md#servodrc
-"""
-import argparse
-import concurrent
-import io
-import logging
-import os
-import re
-import subprocess
-import sys
-import time
-from concurrent.futures.thread import ThreadPoolExecutor
-from enum import Enum
-from pathlib import Path
-from typing import Optional, BinaryIO, List
-
-import colorama  # type: ignore[import]
-
-EC_DIR = Path(os.path.dirname(os.path.realpath(__file__))).parent
-JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_jlink.py')
-SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_ec')
-
-ALL_TESTS_PASSED_REGEX = re.compile(r'Pass!\r\n')
-ALL_TESTS_FAILED_REGEX = re.compile(r'Fail! \(\d+ tests\)\r\n')
-
-SINGLE_CHECK_PASSED_REGEX = re.compile(r'Pass: .*')
-SINGLE_CHECK_FAILED_REGEX = re.compile(r'.*failed:.*')
-
-ASSERTION_FAILURE_REGEX = re.compile(r'ASSERTION FAILURE.*')
-
-DATA_ACCESS_VIOLATION_8020000_REGEX = re.compile(
-    r'Data access violation, mfar = 8020000\r\n')
-DATA_ACCESS_VIOLATION_8040000_REGEX = re.compile(
-    r'Data access violation, mfar = 8040000\r\n')
-DATA_ACCESS_VIOLATION_80C0000_REGEX = re.compile(
-    r'Data access violation, mfar = 80c0000\r\n')
-DATA_ACCESS_VIOLATION_80E0000_REGEX = re.compile(
-    r'Data access violation, mfar = 80e0000\r\n')
-DATA_ACCESS_VIOLATION_20000000_REGEX = re.compile(
-    r'Data access violation, mfar = 20000000\r\n')
-DATA_ACCESS_VIOLATION_24000000_REGEX = re.compile(
-    r'Data access violation, mfar = 24000000\r\n')
-
-BLOONCHIPPER = 'bloonchipper'
-DARTMONKEY = 'dartmonkey'
-
-JTRACE = 'jtrace'
-SERVO_MICRO = 'servo_micro'
-
-GCC = 'gcc'
-CLANG = 'clang'
-
-
-class ImageType(Enum):
-    """EC Image type to use for the test."""
-    RO = 1
-    RW = 2
-
-
-class BoardConfig:
-    """Board-specific configuration."""
-
-    def __init__(self, name, servo_uart_name, servo_power_enable,
-                 rollback_region0_regex, rollback_region1_regex, mpu_regex):
-        self.name = name
-        self.servo_uart_name = servo_uart_name
-        self.servo_power_enable = servo_power_enable
-        self.rollback_region0_regex = rollback_region0_regex
-        self.rollback_region1_regex = rollback_region1_regex
-        self.mpu_regex = mpu_regex
-
-
-class TestConfig:
-    """Configuration for a given test."""
-
-    def __init__(self, name, image_to_use=ImageType.RW, finish_regexes=None,
-                 toggle_power=False, test_args=None, num_flash_attempts=2,
-                 timeout_secs=10, enable_hw_write_protect=False):
-        if test_args is None:
-            test_args = []
-        if finish_regexes is None:
-            finish_regexes = [ALL_TESTS_PASSED_REGEX, ALL_TESTS_FAILED_REGEX]
-
-        self.name = name
-        self.image_to_use = image_to_use
-        self.finish_regexes = finish_regexes
-        self.test_args = test_args
-        self.toggle_power = toggle_power
-        self.num_flash_attempts = num_flash_attempts
-        self.timeout_secs = timeout_secs
-        self.enable_hw_write_protect = enable_hw_write_protect
-        self.logs = []
-        self.passed = False
-        self.num_fails = 0
-        self.num_passes = 0
-
-
-# All possible tests.
-class AllTests:
-    """All possible tests."""
-
-    @staticmethod
-    def get(board_config: BoardConfig):
-        tests = {
-            'aes':
-                TestConfig(name='aes'),
-            'cec':
-                TestConfig(name='cec'),
-            'crc':
-                TestConfig(name='crc'),
-            'flash_physical':
-                TestConfig(name='flash_physical', image_to_use=ImageType.RO,
-                           toggle_power=True),
-            'flash_write_protect':
-                TestConfig(name='flash_write_protect',
-                           image_to_use=ImageType.RO,
-                           toggle_power=True, enable_hw_write_protect=True),
-            'fpsensor_hw':
-                TestConfig(name='fpsensor_hw'),
-            'fpsensor_spi_ro':
-                TestConfig(name='fpsensor', image_to_use=ImageType.RO,
-                           test_args=['spi']),
-            'fpsensor_spi_rw':
-                TestConfig(name='fpsensor', test_args=['spi']),
-            'fpsensor_uart_ro':
-                TestConfig(name='fpsensor', image_to_use=ImageType.RO,
-                           test_args=['uart']),
-            'fpsensor_uart_rw':
-                TestConfig(name='fpsensor', test_args=['uart']),
-            'mpu_ro':
-                TestConfig(name='mpu',
-                           image_to_use=ImageType.RO,
-                           finish_regexes=[board_config.mpu_regex]),
-            'mpu_rw':
-                TestConfig(name='mpu',
-                           finish_regexes=[board_config.mpu_regex]),
-            'mutex':
-                TestConfig(name='mutex'),
-            'pingpong':
-                TestConfig(name='pingpong'),
-            'printf':
-                TestConfig(name='printf'),
-            'queue':
-                TestConfig(name='queue'),
-            'rollback_region0':
-                TestConfig(name='rollback', finish_regexes=[
-                    board_config.rollback_region0_regex],
-                           test_args=['region0']),
-            'rollback_region1':
-                TestConfig(name='rollback', finish_regexes=[
-                    board_config.rollback_region1_regex],
-                           test_args=['region1']),
-            'rollback_entropy':
-                TestConfig(name='rollback_entropy', image_to_use=ImageType.RO),
-            'rtc':
-                TestConfig(name='rtc'),
-            'sha256':
-                TestConfig(name='sha256'),
-            'sha256_unrolled':
-                TestConfig(name='sha256_unrolled'),
-            'static_if':
-                TestConfig(name='static_if'),
-            'timer_dos':
-                TestConfig(name='timer_dos'),
-            'utils':
-                TestConfig(name='utils', timeout_secs=20),
-            'utils_str':
-                TestConfig(name='utils_str'),
-        }
-
-        if board_config.name == BLOONCHIPPER:
-            tests['stm32f_rtc'] = TestConfig(name='stm32f_rtc')
-
-        return tests
-
-
-BLOONCHIPPER_CONFIG = BoardConfig(
-    name=BLOONCHIPPER,
-    servo_uart_name='raw_fpmcu_console_uart_pty',
-    servo_power_enable='fpmcu_pp3300',
-    rollback_region0_regex=DATA_ACCESS_VIOLATION_8020000_REGEX,
-    rollback_region1_regex=DATA_ACCESS_VIOLATION_8040000_REGEX,
-    mpu_regex=DATA_ACCESS_VIOLATION_20000000_REGEX,
-)
-
-DARTMONKEY_CONFIG = BoardConfig(
-    name=DARTMONKEY,
-    servo_uart_name='raw_fpmcu_console_uart_pty',
-    servo_power_enable='fpmcu_pp3300',
-    rollback_region0_regex=DATA_ACCESS_VIOLATION_80C0000_REGEX,
-    rollback_region1_regex=DATA_ACCESS_VIOLATION_80E0000_REGEX,
-    mpu_regex=DATA_ACCESS_VIOLATION_24000000_REGEX,
-)
-
-BOARD_CONFIGS = {
-    'bloonchipper': BLOONCHIPPER_CONFIG,
-    'dartmonkey': DARTMONKEY_CONFIG,
-}
-
-
-def get_console(board_config: BoardConfig) -> Optional[str]:
-    """Get the name of the console for a given board."""
-    cmd = [
-        'dut-control',
-        board_config.servo_uart_name,
-    ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-
-    with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc:
-        for line in io.TextIOWrapper(proc.stdout):  # type: ignore[arg-type]
-            logging.debug(line)
-            pty = line.split(':')
-            if len(pty) == 2 and pty[0] == board_config.servo_uart_name:
-                return pty[1].strip()
-
-    return None
-
-
-def power(board_config: BoardConfig, on: bool) -> None:
-    """Turn power to board on/off."""
-    if on:
-        state = 'pp3300'
-    else:
-        state = 'off'
-
-    cmd = [
-        'dut-control',
-        board_config.servo_power_enable + ':' + state,
-    ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
-
-
-def hw_write_protect(enable: bool) -> None:
-    """Enable/disable hardware write protect."""
-    if enable:
-        state = 'force_on'
-    else:
-        state = 'force_off'
-
-    cmd = [
-        'dut-control',
-        'fw_wp_state:' + state,
-        ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
-
-
-def build(test_name: str, board_name: str, compiler: str) -> None:
-    """Build specified test for specified board."""
-    cmd = ['make']
-
-    if compiler == CLANG:
-        cmd = cmd + ['CC=arm-none-eabi-clang']
-
-    cmd = cmd + [
-        'BOARD=' + board_name,
-        'test-' + test_name,
-        '-j',
-    ]
-
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()
-
-
-def flash(test_name: str, board: str, flasher: str, remote: str) -> bool:
-    """Flash specified test to specified board."""
-    logging.info("Flashing test")
-
-    cmd = []
-    if flasher == JTRACE:
-        cmd.append(JTRACE_FLASH_SCRIPT)
-        if remote:
-            cmd.extend(['--remote', remote])
-    elif flasher == SERVO_MICRO:
-        cmd.append(SERVO_MICRO_FLASH_SCRIPT)
-    else:
-        logging.error('Unknown flasher: "%s"', flasher)
-        return False
-    cmd.extend([
-        '--board', board,
-        '--image', os.path.join(EC_DIR, 'build', board, test_name,
-                                test_name + '.bin'),
-    ])
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)
-    return completed_process.returncode == 0
-
-
-def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \
-             Optional[bytes]:
-    """Read a line with timeout."""
-    a = executor.submit(f.readline)
-    try:
-        return a.result(timeout_secs)
-    except concurrent.futures.TimeoutError:
-        return None
-
-
-def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> \
-                            List[bytes]:
-    """Continuously read lines for timeout_secs."""
-    lines: List[bytes] = []
-    while True:
-        line = readline(executor, f, timeout_secs)
-        if not line:
-            return lines
-        lines.append(line)
-
-
-def process_console_output_line(line: bytes, test: TestConfig):
-    try:
-        line_str = line.decode()
-
-        if SINGLE_CHECK_PASSED_REGEX.match(line_str):
-            test.num_passes += 1
-
-        if SINGLE_CHECK_FAILED_REGEX.match(line_str):
-            test.num_fails += 1
-
-        if ALL_TESTS_FAILED_REGEX.match(line_str):
-            test.num_fails += 1
-
-        if ASSERTION_FAILURE_REGEX.match(line_str):
-            test.num_fails += 1
-
-        return line_str
-    except UnicodeDecodeError:
-        # Sometimes we get non-unicode from the console (e.g., when the
-        # board reboots.) Not much we can do in this case, so we'll just
-        # ignore it.
-        return None
-
-
-def run_test(test: TestConfig, console: str, executor: ThreadPoolExecutor) ->\
-             bool:
-    """Run specified test."""
-    start = time.time()
-    with open(console, "wb+", buffering=0) as c:
-        # Wait for boot to finish
-        time.sleep(1)
-        c.write('\n'.encode())
-        if test.image_to_use == ImageType.RO:
-            c.write('reboot ro\n'.encode())
-            time.sleep(1)
-
-        test_cmd = 'runtest ' + ' '.join(test.test_args) + '\n'
-        c.write(test_cmd.encode())
-
-        while True:
-            c.flush()
-            line = readline(executor, c, 1)
-            if not line:
-                now = time.time()
-                if now - start > test.timeout_secs:
-                    logging.debug("Test timed out")
-                    return False
-                continue
-
-            logging.debug(line)
-            test.logs.append(line)
-            # Look for test_print_result() output (success or failure)
-            line_str = process_console_output_line(line, test)
-            if line_str is None:
-                # Sometimes we get non-unicode from the console (e.g., when the
-                # board reboots.) Not much we can do in this case, so we'll just
-                # ignore it.
-                continue
-
-            for r in test.finish_regexes:
-                if r.match(line_str):
-                    # flush read the remaining
-                    lines = readlines_until_timeout(executor, c, 1)
-                    logging.debug(lines)
-                    test.logs.append(lines)
-
-                    for line in lines:
-                        process_console_output_line(line, test)
-
-                    return test.num_fails == 0
-
-
-def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]:
-    """Get a list of tests to run."""
-    if test_args == 'all':
-        return list(AllTests.get(config).values())
-
-    test_list = []
-    for t in test_args:
-        logging.debug('test: %s', t)
-        test_config = AllTests.get(config).get(t)
-        if test_config is None:
-            logging.error('Unable to find test config for "%s"', t)
-            sys.exit(1)
-        test_list.append(test_config)
-
-    return test_list
-
-
-def main():
-    parser = argparse.ArgumentParser()
-
-    default_board = 'bloonchipper'
-    parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
-
-    default_tests = 'all'
-    parser.add_argument(
-        '--tests', '-t',
-        nargs='+',
-        help='Tests (default: ' + default_tests + ')',
-        default=default_tests)
-
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
-    parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
-    )
-
-    flasher_choices = [SERVO_MICRO, JTRACE]
-    parser.add_argument(
-         '--flasher', '-f',
-         choices=flasher_choices,
-         default=JTRACE
-     )
-
-    compiler_options = [GCC, CLANG]
-    parser.add_argument('--compiler', '-c',
-                        choices=compiler_options,
-                        default=GCC)
-
-    # This might be expanded to serve as a "remote" for flash_ec also, so
-    # we will leave it generic.
-    parser.add_argument(
-        '--remote', '-n',
-        help='The remote host:ip to connect to J-Link. '
-        'This is passed to flash_jlink.py.',
-    )
-
-    args = parser.parse_args()
-    logging.basicConfig(level=args.log_level)
-
-    if args.board not in BOARD_CONFIGS:
-        logging.error('Unable to find a config for board: "%s"', args.board)
-        sys.exit(1)
-
-    board_config = BOARD_CONFIGS[args.board]
-
-    e = ThreadPoolExecutor(max_workers=1)
-
-    test_list = get_test_list(board_config, args.tests)
-    logging.debug('Running tests: %s', [t.name for t in test_list])
-
-    for test in test_list:
-        # build test binary
-        build(test.name, args.board, args.compiler)
-
-        # flash test binary
-        # TODO(b/158327221): First attempt to flash fails after
-        #  flash_write_protect test is run; works after second attempt.
-        flash_succeeded = False
-        for i in range(0, test.num_flash_attempts):
-            logging.debug('Flash attempt %d', i + 1)
-            if flash(test.name, args.board, args.flasher, args.remote):
-                flash_succeeded = True
-                break
-            time.sleep(1)
-
-        if not flash_succeeded:
-            logging.debug('Flashing failed after max attempts: %d',
-                          test.num_flash_attempts)
-            test.passed = False
-            continue
-
-        if test.toggle_power:
-            power(board_config, on=False)
-            time.sleep(1)
-            power(board_config, on=True)
-
-        hw_write_protect(test.enable_hw_write_protect)
-
-        # run the test
-        logging.info('Running test: "%s"', test.name)
-        console = get_console(board_config)
-        test.passed = run_test(test, console, executor=e)
-
-    colorama.init()
-    exit_code = 0
-    for test in test_list:
-        # print results
-        print('Test "' + test.name + '": ', end='')
-        if test.passed:
-            print(colorama.Fore.GREEN + 'PASSED')
-        else:
-            print(colorama.Fore.RED + 'FAILED')
-            exit_code = 1
-
-        print(colorama.Style.RESET_ALL)
-
-    e.shutdown(wait=False)
-    sys.exit(exit_code)
-
-
-if __name__ == '__main__':
-  sys.exit(main())
diff --git a/test/sbs_charging_v2.c b/test/sbs_charging_v2.c
deleted file mode 100644
index bdca592d6c..0000000000
--- a/test/sbs_charging_v2.c
+++ /dev/null
@@ -1,940 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test charge_state_v2 behavior
- */
-
-#include "battery_smart.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "math_util.h"
-#include "power.h"
-#include "task.h"
-#include "test_util.h"
-#include "util.h"
-
-#define WAIT_CHARGER_TASK 600
-#define BATTERY_DETACH_DELAY 35000
-
-enum ec_charge_control_mode get_chg_ctrl_mode(void);
-
-static int mock_chipset_state = CHIPSET_STATE_ON;
-static int is_shutdown;
-static int is_force_discharge;
-static int is_hibernated;
-static int override_voltage, override_current, override_usec;
-static int display_soc;
-static int is_full;
-
-/* The simulation doesn't really hibernate, so we must reset this ourselves */
-extern timestamp_t shutdown_target_time;
-
-static void reset_mocks(void)
-{
-	mock_chipset_state = CHIPSET_STATE_ON;
-	is_shutdown = is_force_discharge = is_hibernated = 0;
-	override_voltage = override_current = override_usec = 0;
-	shutdown_target_time.val = 0ULL;
-	is_full = 0;
-}
-
-int board_cut_off_battery(void)
-{
-	return EC_SUCCESS;
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	is_shutdown = 1;
-	mock_chipset_state = CHIPSET_STATE_HARD_OFF;
-}
-
-int chipset_in_state(int state_mask)
-{
-	return state_mask & mock_chipset_state;
-}
-
-int chipset_in_or_transitioning_to_state(int state_mask)
-{
-	return state_mask & mock_chipset_state;
-}
-
-enum power_state power_get_state(void)
-{
-	if (is_shutdown)
-		return POWER_S5;
-	else if (is_hibernated)
-		return POWER_G3;
-	else
-		return POWER_S0;
-}
-
-int board_discharge_on_ac(int enabled)
-{
-	is_force_discharge = enabled;
-	return EC_SUCCESS;
-}
-
-void system_hibernate(int sec, int usec)
-{
-	is_hibernated = 1;
-}
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	if (override_voltage)
-		curr->requested_voltage = override_voltage;
-	if (override_current)
-		curr->requested_current = override_current;
-
-	if (override_usec)
-		return override_usec;
-
-	/* Don't let it sleep a whole minute when the AP is off */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-		return CHARGE_POLL_PERIOD_LONG;
-
-	return 0;
-}
-
-static uint32_t meh;
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
-		*value = meh;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	if (param == CS_PARAM_CUSTOM_PROFILE_MIN) {
-		meh = value;
-		return EC_RES_SUCCESS;
-	}
-	return EC_RES_INVALID_PARAM;
-}
-
-static int wait_charging_state(void)
-{
-	enum charge_state state;
-	task_wake(TASK_ID_CHARGER);
-	msleep(WAIT_CHARGER_TASK);
-	state = charge_get_state();
-	ccprintf("[CHARGING TEST] state = %d\n", state);
-	return state;
-}
-
-static int charge_control(enum ec_charge_control_mode mode)
-{
-	struct ec_params_charge_control p;
-
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = mode;
-	p.sustain_soc.lower = -1;
-	p.sustain_soc.upper = -1;
-	return test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
-				      NULL, 0);
-}
-
-__override int charge_get_display_charge(void)
-{
-	return display_soc;
-}
-
-__override int calc_is_full(void)
-{
-	return is_full;
-}
-
-/* Setup init condition */
-static void test_setup(int on_ac)
-{
-	const struct battery_info *bat_info = battery_get_info();
-
-	reset_mocks();
-
-	/* 50% of charge */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 50);
-	sb_write(SB_ABSOLUTE_STATE_OF_CHARGE, 50);
-	/* full charge capacity in mAh */
-	sb_write(SB_FULL_CHARGE_CAPACITY, 0xf000);
-	/* 25 degree Celsius */
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(25));
-	/* battery pack voltage */
-	sb_write(SB_VOLTAGE, bat_info->voltage_normal);
-	/* desired charging voltage/current */
-	sb_write(SB_CHARGING_VOLTAGE, bat_info->voltage_max);
-	sb_write(SB_CHARGING_CURRENT, 4000);
-
-	/* battery pack current is positive when charging */
-	if (on_ac) {
-		sb_write(SB_CURRENT, 1000);
-		gpio_set_level(GPIO_AC_PRESENT, 1);
-	} else {
-		sb_write(SB_CURRENT, -100);
-		gpio_set_level(GPIO_AC_PRESENT, 0);
-	}
-
-	/* Reset the charger state to initial state */
-	charge_control(CHARGE_CONTROL_NORMAL);
-
-	/* Let things stabilize */
-	wait_charging_state();
-}
-
-/* Host Event helpers */
-static int ev_is_set(int event)
-{
-	return host_get_events() & EC_HOST_EVENT_MASK(event);
-}
-static int ev_is_clear(int event)
-{
-	return !ev_is_set(event);
-}
-static void ev_clear(int event)
-{
-	host_clear_events(EC_HOST_EVENT_MASK(event));
-}
-
-static int test_charge_state(void)
-{
-	enum charge_state state;
-	uint32_t flags;
-
-	/* On AC */
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] AC on\n");
-
-	/* Detach battery, charging error */
-	ccprintf("[CHARGING TEST] Detach battery\n");
-	TEST_ASSERT(test_detach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS) ==
-		    EC_SUCCESS);
-	msleep(BATTERY_DETACH_DELAY);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_ERROR);
-
-	/* Attach battery again, charging */
-	ccprintf("[CHARGING TEST] Attach battery\n");
-	test_attach_i2c(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS);
-	/* And changing full capacity should trigger a host event */
-	ev_clear(EC_HOST_EVENT_BATTERY);
-	sb_write(SB_FULL_CHARGE_CAPACITY, 0xeff0);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY));
-
-	/* Unplug AC, discharging at 1000mAh */
-	ccprintf("[CHARGING TEST] AC off\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(!(flags & CHARGE_FLAG_EXTERNAL_POWER));
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Discharging waaaay overtemp is ignored */
-	ccprintf("[CHARGING TEST] AC off, batt temp = 0xffff\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, 0xffff);
-	state = wait_charging_state();
-	TEST_ASSERT(!is_shutdown);
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
-
-	/* Discharging overtemp */
-	ccprintf("[CHARGING TEST] AC off, batt temp = 90 C\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
-	state = wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(40));
-
-	/* Force idle */
-	ccprintf("[CHARGING TEST] AC on, force idle\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-	charge_control(CHARGE_CONTROL_IDLE);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
-	charge_control(CHARGE_CONTROL_NORMAL);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-
-	/* Force discharge */
-	ccprintf("[CHARGING TEST] AC on, force discharge\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	charge_control(CHARGE_CONTROL_DISCHARGE);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	TEST_ASSERT(is_force_discharge);
-	charge_control(CHARGE_CONTROL_NORMAL);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	TEST_ASSERT(!is_force_discharge);
-
-	return EC_SUCCESS;
-}
-
-static int test_low_battery(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] Low battery with AC and positive current\n");
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	sb_write(SB_CURRENT, 1000);
-	wait_charging_state();
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	TEST_ASSERT(!is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery with AC and negative current\n");
-	sb_write(SB_CURRENT, -1000);
-	wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery shutdown S0->S5\n");
-	mock_chipset_state = CHIPSET_STATE_ON;
-	hook_notify(HOOK_CHIPSET_PRE_INIT);
-	hook_notify(HOOK_CHIPSET_STARTUP);
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	is_hibernated = 0;
-	sb_write(SB_CURRENT, -1000);
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	wait_charging_state();
-	/* after a while, the EC should hibernate */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery shutdown S5\n");
-	is_hibernated = 0;
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
-	wait_charging_state();
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	/* after a while, the EC should hibernate */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_hibernated);
-
-	ccprintf("[CHARGING TEST] Low battery AP shutdown\n");
-	is_shutdown = 0;
-	mock_chipset_state = CHIPSET_STATE_ON;
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 10);
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	sb_write(SB_CURRENT, 1000);
-	wait_charging_state();
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	sb_write(SB_CURRENT, -1000);
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, 2);
-	wait_charging_state();
-	usleep(32 * SECOND);
-	wait_charging_state();
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_high_temp_battery(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] High battery temperature shutdown\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(90));
-	wait_charging_state();
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	ccprintf("[CHARGING TEST] High battery temp S0->S5 hibernate\n");
-	mock_chipset_state = CHIPSET_STATE_SOFT_OFF;
-	wait_charging_state();
-	TEST_ASSERT(is_hibernated);
-
-	return EC_SUCCESS;
-}
-
-static int test_cold_battery_with_ac(void)
-{
-	test_setup(1);
-
-	ccprintf("[CHARGING TEST] Cold battery no shutdown with AC\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
-	wait_charging_state();
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(!is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_cold_battery_no_ac(void)
-{
-	test_setup(0);
-
-	ccprintf("[CHARGING TEST] Cold battery shutdown when discharging\n");
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	sb_write(SB_TEMPERATURE, CELSIUS_TO_DECI_KELVIN(-90));
-	wait_charging_state();
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_external_funcs(void)
-{
-	int rv, temp;
-	uint32_t flags;
-	int state;
-
-	/* Connect the AC */
-	test_setup(1);
-
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Invalid or do-nothing commands first */
-	UART_INJECT("chg\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg blahblah\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg idle\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	UART_INJECT("chg idle blargh\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* Now let's force idle on and off */
-	UART_INJECT("chg idle on\n");
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
-
-	UART_INJECT("chg idle off\n");
-	wait_charging_state();
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_CHARGE);
-	flags = charge_get_flags();
-	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
-	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
-
-	/* and the rest */
-	TEST_ASSERT(charge_get_state() == PWR_STATE_CHARGE);
-	TEST_ASSERT(!charge_want_shutdown());
-	TEST_ASSERT(charge_get_percent() == 50);
-	temp = 0;
-	rv = charge_get_battery_temp(0, &temp);
-	TEST_ASSERT(rv == EC_SUCCESS);
-	TEST_ASSERT(K_TO_C(temp) == 25);
-
-	return EC_SUCCESS;
-}
-
-#define CHG_OPT1 0x2000
-#define CHG_OPT2 0x4000
-static int test_hc_charge_state(void)
-{
-	enum charge_state state;
-	int i, rv, tmp;
-	struct ec_params_charge_state params;
-	struct ec_response_charge_state resp;
-
-	/* Let's connect the AC again. */
-	test_setup(1);
-
-	/* Initialize the charger options with some nonzero value */
-	TEST_ASSERT(charger_set_option(CHG_OPT1) == EC_SUCCESS);
-
-	/* Get the state */
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(resp.get_state.ac);
-	TEST_ASSERT(resp.get_state.chg_voltage);
-	TEST_ASSERT(resp.get_state.chg_current);
-	TEST_ASSERT(resp.get_state.chg_input_current);
-	TEST_ASSERT(resp.get_state.batt_state_of_charge);
-
-	/* Check all the params */
-	for (i = 0; i < CS_NUM_BASE_PARAMS; i++) {
-
-		/* Read it */
-		memset(&resp, 0, sizeof(resp));
-		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		TEST_ASSERT(rv == EC_RES_SUCCESS);
-		if (i != CS_PARAM_LIMIT_POWER)
-			TEST_ASSERT(resp.get_param.value);
-		else
-			TEST_ASSERT(!resp.get_param.value);
-
-		/* Bump it up a bit */
-		tmp = resp.get_param.value;
-		switch (i) {
-		case CS_PARAM_CHG_VOLTAGE:
-		case CS_PARAM_CHG_CURRENT:
-		case CS_PARAM_CHG_INPUT_CURRENT:
-			tmp -= 128;		/* Should be valid delta */
-			break;
-		case CS_PARAM_CHG_STATUS:
-		case CS_PARAM_LIMIT_POWER:
-			/* These ones can't be set */
-			break;
-		case CS_PARAM_CHG_OPTION:
-			tmp = CHG_OPT2;
-			break;
-		}
-		params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-		params.set_param.param = i;
-		params.set_param.value = tmp;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		if (i == CS_PARAM_CHG_STATUS || i == CS_PARAM_LIMIT_POWER)
-			TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
-		else
-			TEST_ASSERT(rv == EC_RES_SUCCESS);
-		/* Allow the change to take effect */
-		state = wait_charging_state();
-		TEST_ASSERT(state == PWR_STATE_CHARGE);
-
-		/* Read it back again*/
-		memset(&resp, 0, sizeof(resp));
-		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
-		TEST_ASSERT(rv == EC_RES_SUCCESS);
-		TEST_ASSERT(resp.get_param.value == tmp);
-	}
-
-	/* And a custom profile param */
-	meh = 0xdeadbeef;
-	memset(&resp, 0, sizeof(resp));
-	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-	params.get_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(resp.get_param.value == meh);
-	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-	params.set_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
-	params.set_param.value = 0xc0def00d;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	/* Allow the change to take effect */
-	state = wait_charging_state();
-	TEST_ASSERT(meh == params.set_param.value);
-
-	/* param out of range */
-	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
-	params.get_param.param = CS_NUM_BASE_PARAMS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
-	params.set_param.param = CS_NUM_BASE_PARAMS;
-	params.set_param.value = 0x1000;	/* random value */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	/* command out of range */
-	params.cmd = CHARGE_STATE_NUM_CMDS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
-	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
-
-	/*
-	 * We've screwed with the charger settings, so let the state machine
-	 * reset itself before we stop.
-	 */
-	test_setup(0);
-	test_setup(1);
-
-	return EC_SUCCESS;
-}
-
-static int test_hc_current_limit(void)
-{
-	int rv, norm_current, lower_current;
-	struct ec_params_charge_state cs_params;
-	struct ec_response_charge_state cs_resp;
-	struct ec_params_current_limit cl_params;
-
-	/* On AC */
-	test_setup(1);
-
-	/* See what current the charger is delivering */
-	cs_params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	norm_current = cs_resp.get_state.chg_current;
-
-	/* Lower it a bit */
-	lower_current = norm_current - 256;
-	cl_params.limit = lower_current;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-
-	/* See that it's changed */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(lower_current == cs_resp.get_state.chg_current);
-
-	/* Remove the limit */
-	cl_params.limit = -1U;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-
-	/* See that it's back */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(norm_current == cs_resp.get_state.chg_current);
-
-	return EC_SUCCESS;
-}
-
-static int test_low_battery_hostevents(void)
-{
-	int state;
-
-	test_setup(0);
-
-	ccprintf("[CHARGING TEST] Low battery host events\n");
-
-	/* You know you make me wanna */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW + 1);
-	ev_clear(EC_HOST_EVENT_BATTERY_LOW);
-	ev_clear(EC_HOST_EVENT_BATTERY_CRITICAL);
-	ev_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_LOW - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL + 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN + 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	TEST_ASSERT(ev_is_clear(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-
-	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_SHUTDOWN - 1);
-	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_CRITICAL));
-	/* hey-hey-HEY-hey. Doesn't immediately shut down */
-	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_SHUTDOWN));
-	TEST_ASSERT(!is_shutdown);
-	/* after a while, the AP should shut down */
-	sleep(CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT);
-	TEST_ASSERT(is_shutdown);
-
-	return EC_SUCCESS;
-}
-
-static int test_battery_sustainer(void)
-{
-	struct ec_params_charge_control p;
-	struct ec_response_charge_control r;
-	int rv;
-
-	test_setup(1);
-
-	/* Enable sustainer */
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = CHARGE_CONTROL_NORMAL;
-	p.sustain_soc.lower = 79;
-	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-
-	p.cmd = EC_CHARGE_CONTROL_CMD_GET;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), &r, sizeof(r));
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(r.sustain_soc.lower == 79);
-	TEST_ASSERT(r.sustain_soc.upper == 80);
-
-	/* Check mode transition as the SoC changes. */
-
-	ccprintf("Test SoC < lower < upper.\n");
-	display_soc = 780;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test lower < upper < SoC.\n");
-	display_soc = 810;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test unplug AC.\n");
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test replug AC.\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test lower < SoC < upper.\n");
-	display_soc = 799;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test SoC < lower < upper.\n");
-	display_soc = 789;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test disable sustainer.\n");
-	charge_control(CHARGE_CONTROL_NORMAL);
-	display_soc = 810;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-	ccprintf("Pass.\n");
-
-	ccprintf("Test enable sustainer when battery is full.\n");
-	display_soc = 1000;
-	is_full = 1;
-	wait_charging_state();
-	/* Enable sustainer. */
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = CHARGE_CONTROL_NORMAL;
-	p.sustain_soc.lower = 79;
-	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
-	ccprintf("Pass.\n");
-
-	/* Disable sustainer, unplug AC, upper < SoC < 100. */
-	charge_control(CHARGE_CONTROL_NORMAL);
-	display_soc = 810;
-	is_full = 0;
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	wait_charging_state();
-
-	ccprintf("Test enable sustainer when AC is present.\n");
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	wait_charging_state();
-	/* Enable sustainer. */
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = CHARGE_CONTROL_NORMAL;
-	p.sustain_soc.lower = 79;
-	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
-	ccprintf("Pass.\n");
-
-	return EC_SUCCESS;
-}
-
-static int test_battery_sustainer_discharge_idle(void)
-{
-	struct ec_params_charge_control p;
-	int rv;
-
-	test_setup(1);
-
-	/* Enable sustainer */
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = CHARGE_CONTROL_NORMAL;
-	p.sustain_soc.lower = 80;
-	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-
-	/* Check mode transition as the SoC changes. */
-
-	/* SoC < lower (= upper) */
-	display_soc = 780;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-
-	/* (lower =) upper < SoC */
-	display_soc = 810;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_IDLE);
-
-	/* Unplug AC. Sustainer gets deactivated. */
-	gpio_set_level(GPIO_AC_PRESENT, 0);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-
-	/* Replug AC. Sustainer gets re-activated. */
-	gpio_set_level(GPIO_AC_PRESENT, 1);
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_IDLE);
-
-	/* lower = SoC = upper */
-	display_soc = 800;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_IDLE);
-
-	/* SoC < lower (= upper) */
-	display_soc = 789;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-
-	/* Disable sustainer */
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	p.mode = CHARGE_CONTROL_NORMAL;
-	p.sustain_soc.lower = -1;
-	p.sustain_soc.upper = -1;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-
-	/* This time, mode will stay in NORMAL even when upper < SoC. */
-	display_soc = 810;
-	wait_charging_state();
-	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_charge_state);
-	RUN_TEST(test_low_battery);
-	RUN_TEST(test_high_temp_battery);
-	RUN_TEST(test_cold_battery_with_ac);
-	RUN_TEST(test_cold_battery_no_ac);
-	RUN_TEST(test_external_funcs);
-	RUN_TEST(test_hc_charge_state);
-	RUN_TEST(test_hc_current_limit);
-	RUN_TEST(test_low_battery_hostevents);
-	RUN_TEST(test_battery_sustainer);
-	RUN_TEST(test_battery_sustainer_discharge_idle);
-
-	test_print_result();
-}
diff --git a/test/sbs_charging_v2.tasklist b/test/sbs_charging_v2.tasklist
deleted file mode 100644
index 3895762986..0000000000
--- a/test/sbs_charging_v2.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/scratchpad.c b/test/scratchpad.c
deleted file mode 100644
index 1bea76f7a1..0000000000
--- a/test/scratchpad.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "system.h"
-#include "test_util.h"
-
-/**
- * The first time this test runs, it should pass. After rebooting, the test
- * should fail because the scratchpad register is set to 1.
- */
-test_static int test_scratchpad(void)
-{
-	int rv;
-	uint32_t scratch;
-
-	TEST_EQ(system_get_scratchpad(&scratch), EC_SUCCESS, "%d");
-	TEST_EQ(scratch, 0, "%d");
-
-	rv = system_set_scratchpad(1);
-	TEST_EQ(rv, EC_SUCCESS, "%d");
-
-	TEST_EQ(system_get_scratchpad(&scratch), EC_SUCCESS, "%d");
-	TEST_EQ(scratch, 1, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_scratchpad);
-	test_print_result();
-}
diff --git a/test/scratchpad.tasklist b/test/scratchpad.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/scratchpad.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/sha256.c b/test/sha256.c
deleted file mode 100644
index 105ae8fec5..0000000000
--- a/test/sha256.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tests SHA256 implementation.
- */
-
-#include "console.h"
-#include "common.h"
-#include "sha256.h"
-#include "test_util.h"
-#include "util.h"
-
-/* Short Msg from NIST FIPS 180-4 (Len = 8) */
-static const uint8_t sha256_8_input[] = {
-	0xd3
-};
-static const uint8_t sha256_8_output[SHA256_DIGEST_SIZE] = {
-	0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad, 0x96,
-	0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea, 0x5c, 0x23,
-	0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1
-};
-
-/* Short Msg from NIST FIPS 180-4 (Len = 72) */
-static const uint8_t sha256_72_input[] = {
-	0x33, 0x34, 0xc5, 0x80, 0x75, 0xd3, 0xf4, 0x13, 0x9e
-};
-static const uint8_t sha256_72_output[SHA256_DIGEST_SIZE] = {
-	0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43, 0x3f,
-	0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0, 0x8b, 0x4b,
-	0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20
-};
-
-/* Long Msg from NIST FIPS 180-4 (Len = 2888) */
-static const uint8_t sha256_2888_input[] = {
-	0x82, 0x82, 0x96, 0x90, 0xaa, 0x37, 0x33, 0xc6, 0x2b, 0x90, 0xd3, 0x29,
-	0x78, 0x86, 0x95, 0x2f, 0xc1, 0xdc, 0x47, 0x3d, 0x67, 0xbb, 0x7d, 0x6b,
-	0xb2, 0x99, 0xe0, 0x88, 0xc6, 0x5f, 0xc9, 0x5e, 0xd3, 0xca, 0x0f, 0x36,
-	0x8d, 0x11, 0x1d, 0x9f, 0xdc, 0xc9, 0x47, 0x6c, 0xd4, 0x06, 0x5e, 0xfc,
-	0xe7, 0xc4, 0x81, 0xbe, 0x59, 0x85, 0x37, 0xf3, 0xf5, 0x3b, 0xbb, 0xb6,
-	0xff, 0x67, 0x97, 0x3a, 0x69, 0x83, 0x74, 0x54, 0x49, 0x9e, 0x31, 0x39,
-	0x8b, 0x46, 0x32, 0x88, 0xe3, 0xaa, 0xfb, 0x8b, 0x06, 0x00, 0xfd, 0xba,
-	0x1a, 0x25, 0xaf, 0x80, 0x6b, 0x83, 0xe1, 0x42, 0x5f, 0x38, 0x4e, 0x9e,
-	0xac, 0x75, 0x70, 0xf0, 0xc8, 0x23, 0x98, 0x1b, 0xa2, 0xcd, 0x3d, 0x86,
-	0x8f, 0xba, 0x94, 0x64, 0x87, 0x59, 0x62, 0x39, 0x91, 0xe3, 0x0f, 0x99,
-	0x7c, 0x3b, 0xfb, 0x33, 0xd0, 0x19, 0x15, 0x0f, 0x04, 0x67, 0xa9, 0x14,
-	0xf1, 0xeb, 0x79, 0xcd, 0x87, 0x27, 0x10, 0x6d, 0xbf, 0x7d, 0x53, 0x10,
-	0xd0, 0x97, 0x59, 0x43, 0xa6, 0x06, 0x7c, 0xc7, 0x90, 0x29, 0xb0, 0x92,
-	0x39, 0x51, 0x14, 0x17, 0xd9, 0x22, 0xc7, 0xc7, 0xac, 0x3d, 0xfd, 0xd8,
-	0xa4, 0x1c, 0x52, 0x45, 0x5b, 0x3c, 0x5e, 0x16, 0x4b, 0x82, 0x89, 0xe1,
-	0x41, 0xd8, 0x20, 0x91, 0x0f, 0x17, 0xa9, 0x66, 0x81, 0x29, 0x74, 0x3d,
-	0x93, 0x6f, 0x73, 0x12, 0xe1, 0x60, 0x4b, 0xc3, 0x5f, 0x73, 0xab, 0x16,
-	0x4a, 0x3f, 0xdd, 0xfe, 0x5f, 0xe1, 0x9b, 0x1a, 0x4a, 0x9f, 0x23, 0x7f,
-	0x61, 0xcb, 0x8e, 0xb7, 0x92, 0xe9, 0x5d, 0x09, 0x9a, 0x14, 0x55, 0xfb,
-	0x78, 0x9d, 0x8d, 0x16, 0x22, 0xf6, 0xc5, 0xe9, 0x76, 0xce, 0xf9, 0x51,
-	0x73, 0x7e, 0x36, 0xf7, 0xa9, 0xa4, 0xad, 0x19, 0xee, 0x0d, 0x06, 0x8e,
-	0x53, 0xd9, 0xf6, 0x04, 0x57, 0xd9, 0x14, 0x8d, 0x5a, 0x3c, 0xe8, 0x5a,
-	0x54, 0x6b, 0x45, 0xc5, 0xc6, 0x31, 0xd9, 0x95, 0xf1, 0x1f, 0x03, 0x7e,
-	0x47, 0x2f, 0xe4, 0xe8, 0x1f, 0xa7, 0xb9, 0xf2, 0xac, 0x40, 0x68, 0xb5,
-	0x30, 0x88, 0x58, 0xcd, 0x6d, 0x85, 0x86, 0x16, 0x5c, 0x9b, 0xd6, 0xb3,
-	0x22, 0xaf, 0xa7, 0x55, 0x40, 0x8d, 0xa9, 0xb9, 0x0a, 0x87, 0xf3, 0x73,
-	0x5a, 0x5f, 0x50, 0xeb, 0x85, 0x68, 0xda, 0xa5, 0x8e, 0xe7, 0xcb, 0xc5,
-	0x9a, 0xbf, 0x8f, 0xd2, 0xa4, 0x4e, 0x1e, 0xba, 0x72, 0x92, 0x88, 0x16,
-	0xc8, 0x90, 0xd1, 0xb0, 0xdb, 0xf6, 0x00, 0x42, 0x08, 0xff, 0x73, 0x81,
-	0xc6, 0x97, 0x75, 0x5a, 0xda, 0xc0, 0x13, 0x7c, 0xca, 0x34, 0x2b, 0x16,
-	0x93
-};
-static const uint8_t sha256_2888_output[SHA256_DIGEST_SIZE] = {
-	0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0, 0x09,
-	0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7, 0x8a, 0x2e,
-	0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40
-};
-
-/* HMAC short key (40 bytes) from NIST FIPS 198-1 (Count = 34) */
-static const uint8_t hmac_short_msg[] = {
-	0x49, 0x53, 0x40, 0x8b, 0xe3, 0xdd, 0xde, 0x42, 0x52, 0x1e, 0xb6, 0x25,
-	0xa3, 0x7a, 0xf0, 0xd2, 0xcf, 0x9e, 0xd1, 0x84, 0xf5, 0xb6, 0x27, 0xe5,
-	0xe7, 0xe0, 0xe8, 0x24, 0xe8, 0xe1, 0x16, 0x48, 0xb4, 0x18, 0xe5, 0xc4,
-	0xc1, 0xb0, 0x20, 0x4b, 0xc5, 0x19, 0xc9, 0xe5, 0x78, 0xb8, 0x00, 0x43,
-	0x9b, 0xdd, 0x25, 0x4f, 0x39, 0xf6, 0x41, 0x08, 0x2d, 0x03, 0xa2, 0x8d,
-	0xe4, 0x4a, 0xc6, 0x77, 0x64, 0x4c, 0x7b, 0x6c, 0x8d, 0xf7, 0x43, 0xf2,
-	0x9f, 0x1d, 0xfd, 0x80, 0xfd, 0x25, 0xc2, 0xdb, 0x31, 0x01, 0x0e, 0xa0,
-	0x2f, 0x60, 0x20, 0x1c, 0xde, 0x24, 0xa3, 0x64, 0xd4, 0x16, 0x8d, 0xa2,
-	0x61, 0xd8, 0x48, 0xae, 0xd0, 0x1c, 0x10, 0xde, 0xe9, 0x14, 0x9c, 0x1e,
-	0xbb, 0x29, 0x00, 0x43, 0x98, 0xf0, 0xd2, 0x9c, 0x60, 0x5a, 0x8b, 0xca,
-	0x03, 0x2b, 0x31, 0xd2, 0x41, 0xad, 0x33, 0x71
-};
-static const uint8_t hmac_short_key[] = {
-	0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9, 0xb5, 0x44,
-	0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca, 0x16, 0xb9, 0x2e, 0xe1,
-	0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad, 0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34,
-	0x39, 0x31, 0x1e, 0x04
-};
-static const uint8_t hmac_short_output[] = {
-	0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41, 0x75,
-	0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e, 0x86, 0x7e,
-	0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2
-};
-
-/* HMAC medium key (64 bytes) from NIST FIPS 198-1 (Count = 120) */
-static const uint8_t hmac_medium_msg[] = {
-	0xed, 0x4f, 0x26, 0x9a, 0x88, 0x51, 0xeb, 0x31, 0x54, 0x77, 0x15, 0x16,
-	0xb2, 0x72, 0x28, 0x15, 0x52, 0x00, 0x77, 0x80, 0x49, 0xb2, 0xdc, 0x19,
-	0x63, 0xf3, 0xac, 0x32, 0xba, 0x46, 0xea, 0x13, 0x87, 0xcf, 0xbb, 0x9c,
-	0x39, 0x15, 0x1a, 0x2c, 0xc4, 0x06, 0xcd, 0xc1, 0x3c, 0x3c, 0x98, 0x60,
-	0xa2, 0x7e, 0xb0, 0xb7, 0xfe, 0x8a, 0x72, 0x01, 0xad, 0x11, 0x55, 0x2a,
-	0xfd, 0x04, 0x1e, 0x33, 0xf7, 0x0e, 0x53, 0xd9, 0x7c, 0x62, 0xf1, 0x71,
-	0x94, 0xb6, 0x61, 0x17, 0x02, 0x8f, 0xa9, 0x07, 0x1c, 0xc0, 0xe0, 0x4b,
-	0xd9, 0x2d, 0xe4, 0x97, 0x2c, 0xd5, 0x4f, 0x71, 0x90, 0x10, 0xa6, 0x94,
-	0xe4, 0x14, 0xd4, 0x97, 0x7a, 0xbe, 0xd7, 0xca, 0x6b, 0x90, 0xba, 0x61,
-	0x2d, 0xf6, 0xc3, 0xd4, 0x67, 0xcd, 0xed, 0x85, 0x03, 0x25, 0x98, 0xa4,
-	0x85, 0x46, 0x80, 0x4f, 0x9c, 0xf2, 0xec, 0xfe
-};
-static const uint8_t hmac_medium_key[] = {
-	0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc, 0xbd,
-	0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8, 0x18, 0x64,
-	0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb, 0x5b, 0x50, 0x17,
-	0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9, 0x5c, 0x32, 0x10, 0xc3,
-	0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d, 0x1b, 0x4f, 0x39, 0x18, 0x17,
-	0xf4, 0xc3, 0x51, 0x24
-};
-static const uint8_t hmac_medium_output[] = {
-	0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b, 0x13,
-	0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39, 0xc1, 0x0d,
-	0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf
-};
-
-static int test_sha256(const uint8_t *input, int input_len,
-		       const uint8_t *output)
-{
-	struct sha256_ctx ctx;
-	uint8_t *tmp;
-	int i;
-
-	/* Basic test */
-	SHA256_init(&ctx);
-	SHA256_update(&ctx, input, input_len);
-	tmp = SHA256_final(&ctx);
-
-	if (memcmp(tmp, output, SHA256_DIGEST_SIZE) != 0) {
-		ccprintf("SHA256 test failed\n");
-		return 0;
-	}
-
-	/* Splitting the input string in chunks of 1 byte also works. */
-	SHA256_init(&ctx);
-	for (i = 0; i < input_len; i++)
-		SHA256_update(&ctx, &input[i], 1);
-	tmp = SHA256_final(&ctx);
-
-	if (memcmp(tmp, output, SHA256_DIGEST_SIZE) != 0) {
-		ccprintf("SHA256 test failed (1-byte chunks)\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-static int test_hmac(const uint8_t *key, int key_len,
-		     const uint8_t *input, int input_len,
-		     const uint8_t *output)
-{
-	uint8_t tmp[SHA256_DIGEST_SIZE];
-
-	hmac_SHA256(tmp, key, key_len, input, input_len);
-
-	if (memcmp(tmp, output, SHA256_DIGEST_SIZE) != 0) {
-		ccprintf("hmac_SHA256 test failed\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-void run_test(int argc, char **argv)
-{
-	ccprintf("Testing short message (8 bytes)\n");
-	if (!test_sha256(sha256_8_input, sizeof(sha256_8_input),
-			 sha256_8_output)) {
-		test_fail();
-		return;
-	}
-
-	ccprintf("Testing short message (72 bytes)\n");
-	if (!test_sha256(sha256_72_input, sizeof(sha256_72_input),
-			 sha256_72_output)) {
-		test_fail();
-		return;
-	}
-
-	ccprintf("Testing long message (2888 bytes)\n");
-	if (!test_sha256(sha256_2888_input, sizeof(sha256_2888_input),
-			 sha256_2888_output)) {
-		test_fail();
-		return;
-	}
-
-	ccprintf("HMAC: Testing short key\n");
-	if (!test_hmac(hmac_short_key, sizeof(hmac_short_key),
-		       hmac_short_msg, sizeof(hmac_short_msg),
-		       hmac_short_output)) {
-		test_fail();
-		return;
-	}
-
-	ccprintf("HMAC: Testing medium key\n");
-	if (!test_hmac(hmac_medium_key, sizeof(hmac_medium_key),
-		       hmac_medium_msg, sizeof(hmac_medium_msg),
-		       hmac_medium_output)) {
-		test_fail();
-		return;
-	}
-
-	/*
-	 * Note: Our HMAC implementation does not support longer than
-	 * 64 bytes keys.
-	 */
-
-	test_pass();
-}
diff --git a/test/sha256.tasklist b/test/sha256.tasklist
deleted file mode 100644
index 80072bb620..0000000000
--- a/test/sha256.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/sha256_unrolled.tasklist b/test/sha256_unrolled.tasklist
deleted file mode 120000
index 06d8620957..0000000000
--- a/test/sha256_unrolled.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-sha256.tasklist
\ No newline at end of file
diff --git a/test/shmalloc.c b/test/shmalloc.c
deleted file mode 100644
index a596d173e7..0000000000
--- a/test/shmalloc.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "link_defs.h"
-#include "shared_mem.h"
-#include "test_util.h"
-
-/*
- * Total size of memory in the malloc pool (shared between free and allocated
- * buffers.
- */
-static int total_size;
-
-/*
- * Number of randomized allocation/free attempts, large enough to execute all
- * branches in the malloc/free module.
- */
-static int counter = 500000;
-
-/*
- * A good random number generator approximation. Guaranteed to generate the
- * same sequence on all test runs.
- */
-static uint32_t next = 127;
-static uint32_t myrand(void)
-{
-	next = next * 1103515245 + 12345;
-	return ((uint32_t)(next/65536) % 32768);
-}
-
-/* Keep track of buffers allocated by the test function. */
-static struct {
-	void *buf;
-	size_t buffer_size;
-} allocations[12];  /* Up to 12 buffers could be allocated concurrently. */
-
-/*
- * Verify that allocated and free buffers do not overlap, and that our and
- * malloc's ideas of the number of allocated buffers match.
- */
-
-static int check_for_overlaps(void)
-{
-	int i;
-	int allocation_match;
-	int allocations_count, allocated_count;
-
-	allocations_count = allocated_count = 0;
-	for (i = 0; i < ARRAY_SIZE(allocations); i++) {
-		struct shm_buffer *allocced_buf;
-
-		if (!allocations[i].buf)
-			continue;
-
-		/*
-		 * Indication of finding the allocated buffer in internal
-		 * malloc structures.
-		 */
-		allocation_match = 0;
-
-		/* number of buffers allocated by the test program. */
-		allocations_count++;
-
-		/*
-		 * Number of allocated buffers malloc knows about, calculated
-		 * multiple times to keep things simple.
-		 */
-		allocated_count = 0;
-		for (allocced_buf = allocced_buf_chain;
-		     allocced_buf;
-		     allocced_buf = allocced_buf->next_buffer) {
-			int allocated_size, allocation_size;
-
-			allocated_count++;
-			if (allocations[i].buf != (allocced_buf + 1))
-				continue;
-
-			allocated_size = allocced_buf->buffer_size;
-			allocation_size = allocations[i].buffer_size;
-
-			/*
-			 * Verify that size requested by the allocator matches
-			 * the value used by malloc, i.e. does not exceed the
-			 * allocated size and is no less than two buffer
-			 * structures lower (which can happen when the
-			 * requested size was rounded up to cover gaps smaller
-			 * than the buffer header structure size).
-			 */
-			if ((allocation_size > allocated_size) ||
-			    ((allocated_size - allocation_size) >=
-			     (2 * sizeof(struct shm_buffer) + sizeof(int)))) {
-				ccprintf("inconsistency: allocated (size %d)"
-					 " allocation %d(size %d)\n",
-					 allocated_size, i, allocation_size);
-				return 0;
-			}
-
-			if (allocation_match++) {
-				ccprintf("inconsistency: duplicated match\n");
-				return 0;
-			}
-		}
-		if (!allocation_match) {
-			ccprintf("missing match %pP!\n", allocations[i].buf);
-			return 0;
-		}
-	}
-	if (allocations_count != allocated_count) {
-		ccprintf("count mismatch (%d != %d)!\n",
-			 allocations_count, allocated_count);
-		return 0;
-	}
-	return 1;
-}
-
-/*
- * Verify that shared memory is in a consistent state, i.e. that there is no
- * overlaps between allocated and free buffers, and that all memory is
- * accounted for (is either allocated or available).
- */
-
-static int shmem_is_ok(int line)
-{
-	int count = 0;
-	int running_size = 0;
-	struct shm_buffer *pbuf = free_buf_chain;
-
-	if (pbuf && pbuf->prev_buffer) {
-		ccprintf("Bad free buffer list start %pP\n", pbuf);
-		goto bailout;
-	}
-
-	while (pbuf) {
-		struct shm_buffer *top;
-
-		running_size += pbuf->buffer_size;
-		if (count++ > 100)
-			goto bailout;  /* Is there a loop? */
-
-		top = (struct shm_buffer *)((uintptr_t)pbuf +
-					     pbuf->buffer_size);
-		if (pbuf->next_buffer) {
-			if (top >= pbuf->next_buffer) {
-				ccprintf("%s:%d"
-					 " - inconsistent buffer size at %pP\n",
-					 __func__, __LINE__, pbuf);
-				goto bailout;
-			}
-			if (pbuf->next_buffer->prev_buffer != pbuf) {
-				ccprintf("%s:%d"
-					 " - inconsistent next buffer at %pP\n",
-					 __func__, __LINE__, pbuf);
-				goto bailout;
-			}
-		}
-		pbuf = pbuf->next_buffer;
-	}
-
-	if (pbuf) { /* Must be a loop. */
-		ccprintf("Too many buffers in the chain\n");
-		goto bailout;
-	}
-
-	/* Make sure there were at least 5 buffers allocated at one point. */
-	if (count > 5)
-		set_map_bit(1 << 24);
-
-	/* Add allocated sizes. */
-	for (pbuf = allocced_buf_chain; pbuf; pbuf = pbuf->next_buffer)
-		running_size += pbuf->buffer_size;
-
-	if (total_size) {
-		if (total_size != running_size)
-			goto bailout;
-	} else {
-		/* Remember total size for future reference. */
-		total_size = running_size;
-	}
-
-	if (!check_for_overlaps())
-		goto bailout;
-
-	return 1;
-
- bailout:
-	ccprintf("Line %d, counter %d. The list has been corrupted, "
-		 "total size %d, running size %d\n",
-		 line, counter, total_size, running_size);
-	return 0;
-}
-
-/*
- * Bitmap used to keep track of branches taken by malloc/free routines. Once
- * all bits in the 0..(MAX_MASK_BIT - 1) range are set, consider the test
- * completed.
- */
-static uint32_t test_map;
-
-void run_test(int argc, char **argv)
-{
-	int index;
-	const int shmem_size = shared_mem_size();
-
-	while (counter--) {
-		char *shptr;
-		uint32_t r_data;
-
-		r_data = myrand();
-
-		if (!(counter % 50000))
-			ccprintf("%d\n", counter);
-
-		/*
-		 * If all bits we care about are set in the map - the test is
-		 * over.
-		 */
-		if ((test_map & ALL_PATHS_MASK) == ALL_PATHS_MASK) {
-			if (test_map & ~ALL_PATHS_MASK) {
-				ccprintf("Unexpected mask bits set: %x"
-					 ", counter %d\n",
-					 test_map & ~ALL_PATHS_MASK,
-					 counter);
-				test_fail();
-				return;
-			}
-			ccprintf("Done testing, counter at %d\n", counter);
-			test_pass();
-			return;
-		}
-
-		/* Pick a random allocation entry. */
-		index = r_data % ARRAY_SIZE(allocations);
-		if (allocations[index].buf) {
-			/*
-			 * If there is a buffer associated with the entry -
-			 * release it.
-			 */
-			shared_mem_release(allocations[index].buf);
-			allocations[index].buf = 0;
-			if (!shmem_is_ok(__LINE__)) {
-				test_fail();
-				return;
-			}
-		} else {
-			size_t alloc_size = r_data % (shmem_size / 2);
-
-			/*
-			 * If the allocation entry is empty - allocate a
-			 * buffer of a random size up to max shared memory.
-			 */
-			if (shared_mem_acquire(alloc_size, &shptr) ==
-			    EC_SUCCESS) {
-				allocations[index].buf = (void *) shptr;
-				allocations[index].buffer_size = alloc_size;
-
-				/*
-				 * Make sure every allocated byte is
-				 * modified.
-				 */
-				while (alloc_size--)
-					shptr[alloc_size] =
-					shptr[alloc_size] ^ 0xff;
-
-				if (!shmem_is_ok(__LINE__)) {
-					test_fail();
-					return;
-				}
-			}
-		}
-	}
-
-	/*
-	 * The test is over, free all still allcated buffers, if any. Keep
-	 * verifying memory consistency after each free() invocation.
-	 */
-	for (index = 0; index < ARRAY_SIZE(allocations); index++)
-		if (allocations[index].buf) {
-			shared_mem_release(allocations[index].buf);
-			allocations[index].buf = NULL;
-			if (!shmem_is_ok(__LINE__)) {
-				test_fail();
-				return;
-			}
-		}
-
-	ccprintf("Did not pass all paths, map %x != %x\n",
-		 test_map, ALL_PATHS_MASK);
-	test_fail();
-}
-
-void set_map_bit(uint32_t mask)
-{
-	test_map |= mask;
-}
diff --git a/test/shmalloc.tasklist b/test/shmalloc.tasklist
deleted file mode 100644
index a8ef01a489..0000000000
--- a/test/shmalloc.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
-
diff --git a/test/static_if.c b/test/static_if.c
deleted file mode 100644
index f70f7d30c3..0000000000
--- a/test/static_if.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Test the STATIC_IF and STATIC_IF_NOT macros. */
-
-#include "common.h"
-#include "test_util.h"
-
-#undef CONFIG_UNDEFINED
-#define CONFIG_BLANK
-
-STATIC_IF(CONFIG_UNDEFINED) int this_var_is_extern;
-STATIC_IF_NOT(CONFIG_BLANK) int this_var_is_extern_too;
-STATIC_IF(CONFIG_BLANK) int this_var_is_static;
-STATIC_IF_NOT(CONFIG_UNDEFINED) int this_var_is_static_too;
-
-static int test_static_if_blank(void)
-{
-	TEST_ASSERT(this_var_is_static == 0);
-	TEST_ASSERT(this_var_is_static_too == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_static_if_unused_no_fail(void)
-{
-	/*
-	 * This should not cause linker errors because the variables
-	 * go unused (usage is optimized away).
-	 */
-	if (IS_ENABLED(CONFIG_UNDEFINED))
-		this_var_is_extern = 1;
-
-	if (!IS_ENABLED(CONFIG_BLANK))
-		this_var_is_extern_too = 1;
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_static_if_blank);
-	RUN_TEST(test_static_if_unused_no_fail);
-
-	test_print_result();
-}
diff --git a/test/static_if.tasklist b/test/static_if.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/static_if.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/static_if_error.c b/test/static_if_error.c
deleted file mode 100644
index 65882b3bbd..0000000000
--- a/test/static_if_error.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Test the STATIC_IF and STATIC_IF_NOT macros fail on unexpected
- * input.
- */
-
-#include "common.h"
-#include "test_util.h"
-
-#define CONFIG_FOO TEST_VALUE
-
-/*
- * At compiler invocation, define TEST_MACRO to STATIC_IF or
- * STATIC_IF_NOT.
- */
-#ifndef TEST_MACRO
-#error "This error should not be seen in the compiler output!"
-#endif
-
-/* This is intended to cause a compilation error. */
-TEST_MACRO(CONFIG_FOO) __maybe_unused int foo;
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	/* Nothing to do, observe compilation error */
-
-	test_print_result();
-}
diff --git a/test/static_if_error.sh b/test/static_if_error.sh
deleted file mode 100644
index efc7cd3e1e..0000000000
--- a/test/static_if_error.sh
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# This file is implemented similar to is_enabled_error.sh
-
-TEST_DIR="$(dirname "${BASH_SOURCE[0]}")"
-TEST_CMD="$(cat "${TEST_DIR}/RO/test/static_if_error.o.cmd")"
-TEST_ERROR_COUNT=0
-BAD_ERROR_MSG="This error should not be seen in the compiler output!"
-
-fail() {
-  echo "Fail"
-  echo "$1"
-  echo "$BUILD_OUTPUT"
-  TEST_ERROR_COUNT=$((TEST_ERROR_COUNT+1))
-}
-
-for test_macro in STATIC_IF STATIC_IF_NOT; do
-  for test_value in 0 1 2 A "5 + 5"; do
-    echo -n "Running TEST_MACRO=${test_macro} TEST_VALUE=${test_value}..."
-    TEST_CMD_COMPLETE="
-      ${TEST_CMD} \"-DTEST_MACRO=${test_macro}\" \"-DTEST_VALUE=${test_value}\""
-    echo "$TEST_CMD_COMPLETE"
-    if BUILD_OUTPUT="$(sh -c "$TEST_CMD_COMPLETE" 2>&1)"; then
-      fail "Compilation should not have succeeded."
-      continue
-    fi
-
-    if grep -q "$BAD_ERROR_MSG" <<<"$BUILD_OUTPUT"; then
-      fail "TEST_MACRO was not defined."
-      continue
-    fi
-  done
-done
-
-if [[ $TEST_ERROR_COUNT -eq 0 ]]; then
-  echo "Pass!"
-else
-  echo "Fail! (${TEST_ERROR_COUNT} tests)"
-fi
diff --git a/test/static_if_error.tasklist b/test/static_if_error.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/static_if_error.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/stillness_detector.c b/test/stillness_detector.c
deleted file mode 100644
index e881525491..0000000000
--- a/test/stillness_detector.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "stillness_detector.h"
-#include "motion_sense.h"
-#include "test_util.h"
-#include "timer.h"
-#include <stdio.h>
-
-/*****************************************************************************/
-/*
- * Need to define motion sensor globals just to compile.
- * We include motion task to force the inclusion of math_util.c
- */
-struct motion_sensor_t motion_sensors[] = {};
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-static int test_build_still_det_struct(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-
-	TEST_NEAR(det.var_threshold, 0.00025f, 0.000001f, "%f");
-	TEST_EQ(det.min_batch_window, 800 * MSEC, "%u");
-	TEST_EQ(det.max_batch_window, 1200 * MSEC, "%u");
-	TEST_EQ(det.min_batch_size, 5, "%u");
-
-	return EC_SUCCESS;
-}
-
-static int test_not_still_short_window(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 6; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      0.0f, 0.0f, 0.0f));
-
-	return EC_SUCCESS;
-}
-
-static int test_not_still_long_window(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 5; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC,
-					      0.0f, 0.0f, 0.0f));
-
-	return EC_SUCCESS;
-}
-
-static int test_not_still_not_enough_samples(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 4; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC,
-					      0.0f, 0.0f, 0.0f));
-
-	return EC_SUCCESS;
-}
-
-static int test_is_still_all_axes(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
-
-		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
-	}
-	TEST_NEAR(det.mean_x, 0.004f, 0.0001f, "%f");
-	TEST_NEAR(det.mean_y, 0.004f, 0.0001f, "%f");
-	TEST_NEAR(det.mean_z, 0.004f, 0.0001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-static int test_not_still_one_axis(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_resets(void)
-{
-	struct still_det det = STILL_DET(0.00025f, 800 * MSEC, 1200 * MSEC, 5);
-	int i;
-
-	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
-	}
-
-	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
-
-		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
-	}
-	TEST_NEAR(det.mean_x, 0.004f, 0.0001f, "%f");
-	TEST_NEAR(det.mean_y, 0.004f, 0.0001f, "%f");
-	TEST_NEAR(det.mean_z, 0.004f, 0.0001f, "%f");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_build_still_det_struct);
-	RUN_TEST(test_not_still_short_window);
-	RUN_TEST(test_not_still_long_window);
-	RUN_TEST(test_not_still_not_enough_samples);
-	RUN_TEST(test_is_still_all_axes);
-	RUN_TEST(test_not_still_one_axis);
-	RUN_TEST(test_resets);
-
-	test_print_result();
-}
diff --git a/test/stillness_detector.tasklist b/test/stillness_detector.tasklist
deleted file mode 100644
index 5ffe662d01..0000000000
--- a/test/stillness_detector.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/stm32f_rtc.c b/test/stm32f_rtc.c
deleted file mode 100644
index 0e60fcb73f..0000000000
--- a/test/stm32f_rtc.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock-f.h"
-#include "test_util.h"
-
-static uint32_t rtc_fired;
-static struct rtc_time_reg rtc_irq;
-static const int rtc_delay_ms = 500;
-
-/*
- * We will be testing that the RTC interrupt timestamp occurs
- * within +/- delay_tol_us (tolerance) of the above rtc_delay_ms.
- */
-static const int delay_tol_us = MSEC / 2;
-
-/* Override default RTC interrupt handler */
-void __rtc_alarm_irq(void)
-{
-	atomic_add(&rtc_fired, 1);
-	reset_rtc_alarm(&rtc_irq);
-}
-
-test_static int test_rtc_alarm(void)
-{
-	struct rtc_time_reg rtc;
-	uint32_t rtc_diff_us;
-	const int delay_us = rtc_delay_ms * MSEC;
-
-	set_rtc_alarm(0, delay_us, &rtc, 0);
-
-	msleep(2 * rtc_delay_ms);
-
-	/* Make sure the interrupt fired exactly once. */
-	TEST_EQ(1, atomic_clear(&rtc_fired), "%d");
-
-	rtc_diff_us = get_rtc_diff(&rtc, &rtc_irq);
-
-	ccprintf("Target delay was %dus\n", delay_us);
-	ccprintf("Actual delay was %dus\n", rtc_diff_us);
-	ccprintf("The delays are expected to be within +/- %dus\n", MSEC / 2);
-
-	/* Assume we'll always fire within 500us. May need to be adjusted if
-	 * this doesn't hold.
-	 *
-	 * delay_us-delay_tol_us < rtc_diff_us < delay_us+delay_tol_us
-	 */
-	TEST_LT(delay_us - delay_tol_us, rtc_diff_us, "%dus");
-	TEST_LT(rtc_diff_us, delay_us + delay_tol_us, "%dus");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_rtc_alarm);
-
-	test_print_result();
-}
diff --git a/test/stm32f_rtc.tasklist b/test/stm32f_rtc.tasklist
deleted file mode 100644
index 51734f058d..0000000000
--- a/test/stm32f_rtc.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* no tasks */
diff --git a/test/stress.c b/test/stress.c
deleted file mode 100644
index 91a65197f8..0000000000
--- a/test/stress.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Peripheral stress tests */
-
-#include "console.h"
-#include "ec_commands.h"
-#include "i2c.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#ifdef CONFIG_ADC
-#include "adc.h"
-#endif
-
-static int error_count;
-
-/*****************************************************************************/
-/* Test parameters */
-
-/* I2C test */
-#define I2C_TEST_ITERATION 2000
-
-struct i2c_test_param_t {
-	int width; /* 8 or 16 bits */
-	int port;
-	int addr;
-	int offset;
-	int data; /* Non-negative represents data to write. -1 to read. */
-} i2c_test_params[];
-
-/* Disable I2C test for boards without test configuration */
-#if defined(BOARD_BDS) || defined(BOARD_AURON)
-#undef CONFIG_I2C
-#endif
-
-/* ADC test */
-#define ADC_TEST_ITERATION 2000
-
-/*****************************************************************************/
-/* Test utilities */
-
-/* period between 500us and 32ms */
-#define RAND_US() (((prng_no_seed() % 64) + 1) * 500)
-
-static int stress(const char *name,
-		  int (*test_routine)(void),
-		  const int iteration)
-{
-	int i;
-
-	for (i = 0; i < iteration; ++i) {
-		if (i % 10 == 0) {
-			ccprintf("\r%s...%d/%d", name, i, iteration);
-			usleep(RAND_US());
-		}
-		if (test_routine() != EC_SUCCESS)
-			return EC_ERROR_UNKNOWN;
-	}
-
-	ccprintf("\r%s...%d/%d\n", name, iteration, iteration);
-	return EC_SUCCESS;
-}
-
-#define RUN_STRESS_TEST(n, r, iter) \
-	do { \
-		if (stress(n, r, iter) != EC_SUCCESS) { \
-			ccputs("Fail\n"); \
-			error_count++; \
-		} \
-	} while (0)
-
-/*****************************************************************************/
-/* Tests */
-#ifdef CONFIG_I2C_CONTROLLER
-static int test_i2c(void)
-{
-	int res = EC_ERROR_UNKNOWN;
-	int mock_data;
-	struct i2c_test_param_t *param;
-	param = i2c_test_params + (prng_no_seed() % (sizeof(i2c_test_params) /
-				   sizeof(struct i2c_test_param_t)));
-	if (param->width == 8 && param->data == -1)
-		res = i2c_read8(param->port, param->addr,
-				param->offset, &mock_data);
-	else if (param->width == 8 && param->data >= 0)
-		res = i2c_write8(param->port, param->addr,
-				 param->offset, param->data);
-	else if (param->width == 16 && param->data == -1)
-		res = i2c_read16(param->port, param->addr,
-				 param->offset, &mock_data);
-	else if (param->width == 16 && param->data >= 0)
-		res = i2c_write16(param->port, param->addr,
-				  param->offset, param->data);
-	else if (param->width == 32 && param->data == -1)
-		res = i2c_read32(param->port, param->addr,
-				 param->offset, &mock_data);
-	else if (param->width == 32 && param->data >= 0)
-		res = i2c_write32(param->port, param->addr,
-				  param->offset, param->data);
-
-	return res;
-}
-#endif
-
-#ifdef CONFIG_ADC
-__attribute__((weak)) int adc_read_all_channels(int *data)
-{
-	int i;
-	int rv = EC_SUCCESS;
-
-	for (i = 0; i < ADC_CH_COUNT; ++i) {
-		data[i] = adc_read_channel(i);
-		if (data[i] == ADC_READ_ERROR)
-			rv = EC_ERROR_UNKNOWN;
-	}
-
-	return rv;
-}
-
-static int test_adc(void)
-{
-	int data[ADC_CH_COUNT];
-	return adc_read_all_channels(data);
-}
-#endif
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-#ifdef CONFIG_I2C_CONTROLLER
-	RUN_STRESS_TEST("I2C Stress Test", test_i2c, I2C_TEST_ITERATION);
-#endif
-#ifdef CONFIG_ADC
-	RUN_STRESS_TEST("ADC Stress Test", test_adc, ADC_TEST_ITERATION);
-#endif
-
-	test_print_result();
-}
diff --git a/test/stress.tasklist b/test/stress.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/stress.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/system.c b/test/system.c
deleted file mode 100644
index 79383b82d9..0000000000
--- a/test/system.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test system_common.
- */
-
-#include "common.h"
-#include "console.h"
-#include "host_command.h"
-#include "system.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-#define TEST_STATE_STEP_2	(1 << 0)
-#define TEST_STATE_FAIL		(1 << 1)
-
-static int test_reboot_on_shutdown(void)
-{
-	struct ec_params_reboot_ec params;
-
-	/* Fails if the system reboots unexpectedly */
-	system_set_scratchpad(TEST_STATE_FAIL);
-
-	test_chipset_on();
-	msleep(30);
-
-	params.cmd = EC_REBOOT_COLD;
-	params.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
-
-	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
-				       sizeof(params), NULL, 0),
-		EC_SUCCESS, "%d");
-
-	system_set_scratchpad(TEST_STATE_STEP_2);
-	test_chipset_off();
-	msleep(30);
-
-	/* Shouldn't reach here */
-	return EC_ERROR_UNKNOWN;
-}
-
-static int test_cancel_reboot(void)
-{
-	struct ec_params_reboot_ec params;
-
-	/* Fails if the system reboots unexpectedly */
-	system_set_scratchpad(TEST_STATE_FAIL);
-
-	test_chipset_on();
-	msleep(30);
-
-	params.cmd = EC_REBOOT_COLD;
-	params.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
-
-	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
-				       sizeof(params), NULL, 0),
-		EC_SUCCESS, "%d");
-
-	params.cmd = EC_REBOOT_CANCEL;
-	params.flags = 0;
-
-	TEST_EQ(test_send_host_command(EC_CMD_REBOOT_EC, 0, &params,
-				       sizeof(params), NULL, 0),
-		EC_SUCCESS, "%d");
-
-	test_chipset_off();
-	msleep(30);
-
-	return EC_SUCCESS;
-}
-
-static void run_test_step1(void)
-{
-	if (test_reboot_on_shutdown() != EC_SUCCESS)
-		test_fail();
-}
-
-static void run_test_step2(void)
-{
-	if (test_cancel_reboot() != EC_SUCCESS)
-		test_fail();
-
-	system_set_scratchpad(0);
-	test_pass();
-}
-
-static void fail_and_clean_up(void)
-{
-	system_set_scratchpad(0);
-	test_fail();
-}
-
-void run_test(int argc, char **argv)
-{
-	uint32_t state = 0;
-
-	/* The return value isn't checked here on purpose. The scratchpad file
-	 * may exist from a previous run or it may be in a clean state. A
-	 * previous run of this test should reset the scratchpad value to 0
-	 * regardless of the final result.
-	 */
-	system_get_scratchpad(&state);
-
-	test_reset();
-
-	if (state == 0)
-		run_test_step1();
-	else if (state & TEST_STATE_STEP_2)
-		run_test_step2();
-	else if (state & TEST_STATE_FAIL)
-		fail_and_clean_up();
-}
diff --git a/test/system.tasklist b/test/system.tasklist
deleted file mode 100644
index 4e455a7ea3..0000000000
--- a/test/system.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/test-matrix.bin b/test/test-matrix.bin
deleted file mode 100644
index e48c761f77..0000000000
--- a/test/test-matrix.bin
+++ /dev/null
diff --git a/test/test_config.h b/test/test_config.h
deleted file mode 100644
index 5afc5d1282..0000000000
--- a/test/test_config.h
+++ /dev/null
@@ -1,622 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Per-test config flags */
-
-#ifndef __TEST_TEST_CONFIG_H
-#define __TEST_TEST_CONFIG_H
-
-/* Test config flags only apply for test builds */
-#ifdef TEST_BUILD
-
-#ifndef __ASSEMBLER__
-#include <stdint.h>
-#endif
-
-/* Host commands are sorted. */
-#define CONFIG_HOSTCMD_SECTION_SORTED
-
-/* Don't compile features unless specifically testing for them */
-#undef CONFIG_VBOOT_HASH
-#undef CONFIG_USB_PD_LOGGING
-
-#ifdef TEST_AES
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#endif
-
-#ifdef TEST_BASE32
-#define CONFIG_BASE32
-#endif
-
-#ifdef TEST_BKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID
-#endif
-
-#ifdef TEST_BKLIGHT_PASSTHRU
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
-#endif
-
-#ifdef TEST_CBI_WP
-#define CONFIG_EEPROM_CBI_WP
-#endif
-
-#ifdef TEST_FLASH_LOG
-#define CONFIG_CRC8
-#define CONFIG_FLASH_ERASED_VALUE32 (-1U)
-#define CONFIG_FLASH_LOG
-#define CONFIG_FLASH_LOG_BASE (CONFIG_PROGRAM_MEMORY_BASE + 0x800)
-#define CONFIG_FLASH_LOG_SPACE 0x800
-#define CONFIG_MALLOC
-#endif
-
-#ifdef TEST_KB_8042
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#endif
-
-#ifdef TEST_KB_MKBP
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#if defined(TEST_KB_SCAN) || defined(TEST_KB_SCAN_STRICT)
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#ifdef TEST_KB_SCAN_STRICT
-#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
-#endif
-#endif
-
-#ifdef TEST_MATH_UTIL
-#define CONFIG_MATH_UTIL
-#endif
-
-#ifdef TEST_MAG_CAL
-#define CONFIG_MAG_CALIBRATE
-#endif
-
-#ifdef TEST_STILLNESS_DETECTOR
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_TEMP_CACHE_STALE_THRES (5 * SECOND)
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_FLOAT
-#define CONFIG_FPU
-#define CONFIG_MAG_CALIBRATE
-#endif
-
-#ifdef TEST_FP
-#undef CONFIG_FPU
-#define CONFIG_MAG_CALIBRATE
-#endif
-
-#if defined(TEST_FPSENSOR) || defined(TEST_FPSENSOR_STATE) || \
-	defined(TEST_FPSENSOR_CRYPTO)
-#define CONFIG_AES
-#define CONFIG_AES_GCM
-#define CONFIG_ROLLBACK_SECRET_SIZE 32
-#define CONFIG_SHA256
-#endif
-
-#ifdef TEST_MOTION_SENSE_FIFO
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES 10
-#endif
-
-#ifdef TEST_KASA
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_ACCEL_CAL
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_ACCEL_CAL_MIN_TEMP 20.0f
-#define CONFIG_ACCEL_CAL_MAX_TEMP 40.0f
-#define CONFIG_ACCEL_CAL_KASA_RADIUS_THRES 0.1f
-#define CONFIG_ACCEL_CAL_NEWTON_RADIUS_THRES 0.1f
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_NEWTON_FIT
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_STILLNESS_DETECTOR
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_ONLINE_CALIBRATION
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#ifdef TEST_ONLINE_CALIBRATION_SPOOF
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#define CONFIG_ONLINE_CALIB_SPOOF_MODE
-#endif /* TEST_ONLINE_CALIBRATION_SPOOF */
-
-#ifdef TEST_GYRO_CAL
-#define CONFIG_FPU
-#define CONFIG_ONLINE_CALIB
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO
-#endif
-
-#if defined(CONFIG_ONLINE_CALIB) && \
-	!defined(CONFIG_TEMP_CACHE_STALE_THRES)
-#define CONFIG_TEMP_CACHE_STALE_THRES (1 * SECOND)
-#endif /* CONFIG_ONLINE_CALIB && !CONFIG_TEMP_CACHE_STALE_THRES */
-
-#if defined(CONFIG_ONLINE_CALIB) || \
-	defined(TEST_BODY_DETECTION) || \
-	defined(TEST_MOTION_ANGLE) || \
-	defined(TEST_MOTION_ANGLE_TABLET) || \
-	defined(TEST_MOTION_LID) || \
-	defined(TEST_MOTION_SENSE_FIFO)
-enum sensor_id {
-	BASE,
-	LID,
-	SENSOR_COUNT,
-};
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE
-#define CONFIG_LID_ANGLE_SENSOR_LID LID
-#define CONFIG_TABLET_MODE
-#define CONFIG_MOTION_FILL_LPC_SENSE_DATA
-
-#endif
-
-#if defined(TEST_MOTION_ANGLE)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
-	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
-#define CONFIG_ACCEL_STD_REF_FRAME_OLD
-#endif
-
-#if defined(TEST_MOTION_ANGLE_TABLET) || \
-	defined(TEST_MOTION_LID)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
-	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
-#endif
-
-#if defined(TEST_BODY_DETECTION)
-#define CONFIG_BODY_DETECTION
-#define CONFIG_BODY_DETECTION_SENSOR BASE
-#endif
-
-#ifdef TEST_RMA_AUTH
-
-/* Test server public and private keys */
-#define RMA_KEY_BLOB	{					\
-		0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, \
-		0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,	\
-		0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,	\
-		0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f, \
-		0x10						\
-	}
-
-#define RMA_TEST_SERVER_PRIVATE_KEY {				\
-		0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, \
-		0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,	\
-		0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,	\
-		0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad}
-#define RMA_TEST_SERVER_KEY_ID 0x10
-
-#define CONFIG_BASE32
-#define CONFIG_CURVE25519
-#define CONFIG_RMA_AUTH
-#define CONFIG_RNG
-#define CONFIG_SHA256
-#define CC_EXTENSION CC_COMMAND
-
-#endif
-
-#ifdef TEST_CRC
-#define CONFIG_CRC8
-#define CONFIG_SW_CRC
-#endif
-
-#ifdef TEST_RSA
-#define CONFIG_RSA
-#ifdef CONFIG_RSA_EXPONENT_3
-#error Your board uses RSA exponent 3, please build rsa3 test instead!
-#endif
-#define CONFIG_RWSIG_TYPE_RWSIG
-#endif
-
-#ifdef TEST_RSA3
-#define CONFIG_RSA
-#define CONFIG_RSA_EXPONENT_3
-#define CONFIG_RWSIG_TYPE_RWSIG
-#endif
-
-#ifdef TEST_SHA256
-#define CONFIG_SHA256
-#endif
-
-#ifdef TEST_SHA256_UNROLLED
-#define CONFIG_SHA256
-#define CONFIG_SHA256_UNROLLED
-#endif
-
-#ifdef TEST_SHMALLOC
-#define CONFIG_MALLOC
-#endif
-
-#ifdef TEST_SBS_CHARGING_V2
-#define CONFIG_BATTERY
-#define CONFIG_BATTERY_MOCK
-#define CONFIG_BATTERY_SMART
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_INPUT_CURRENT 4032
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-int board_discharge_on_ac(int enabled);
-#define I2C_PORT_MASTER 0
-#define I2C_PORT_BATTERY 0
-#define I2C_PORT_CHARGER 0
-#endif
-
-#ifdef TEST_THERMAL
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_FANS 1
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_THROTTLE_AP
-#define CONFIG_THERMISTOR
-#define CONFIG_THERMISTOR_NCP15WB
-#define I2C_PORT_THERMAL 0
-int ncp15wb_calculate_temp(uint16_t adc);
-#endif
-
-#ifdef TEST_FAN
-#define CONFIG_FANS 1
-#endif
-
-#ifdef TEST_BUTTON
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef CONFIG_KEYBOARD_VIVALDI
-#define CONFIG_VOLUME_BUTTONS
-#define CONFIG_HOSTCMD_BUTTON
-#endif
-
-#ifdef TEST_BATTERY_GET_PARAMS_SMART
-#define CONFIG_BATTERY_MOCK
-#define CONFIG_BATTERY_SMART
-#define CONFIG_CHARGER_INPUT_CURRENT 4032
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_MASTER 0
-#define I2C_PORT_BATTERY 0
-#define I2C_PORT_CHARGER 0
-#endif
-
-#ifdef TEST_CEC
-#define CONFIG_CEC
-#endif
-
-#ifdef TEST_LIGHTBAR
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_LIGHTBAR 0
-#define CONFIG_ALS_LIGHTBAR_DIMMING 0
-#endif
-
-#ifdef TEST_USB_COMMON
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#endif
-
-#ifdef TEST_USB_PD_PDO_FIXED
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#define CONFIG_USB_PD_ONLY_FIXED_PDOS
-#endif
-
-#if defined(TEST_USB_SM_FRAMEWORK_H3) || \
-	defined(TEST_USB_SM_FRAMEWORK_H2) || \
-	defined(TEST_USB_SM_FRAMEWORK_H1) || \
-	defined(TEST_USB_SM_FRAMEWORK_H0)
-#define CONFIG_TEST_SM
-#endif
-
-#if defined(TEST_USB_PRL_OLD) || defined(TEST_USB_PRL_NOEXTENDED)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_REV30
-
-#if defined(TEST_USB_PRL_OLD)
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#endif
-
-#define CONFIG_USB_PD_TCPMV2
-#undef CONFIG_USB_PE_SM
-#undef CONFIG_USB_TYPEC_SM
-#undef CONFIG_USB_PD_HOST_CMD
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#endif
-
-#if defined(TEST_USB_PRL)
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#define CONFIG_USB_PD_TCPMV2
-#undef CONFIG_USB_PE_SM
-#undef CONFIG_USB_TYPEC_SM
-#undef CONFIG_USB_PD_HOST_CMD
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_POWER_DELIVERY
-#endif
-
-#if defined(TEST_USB_PE_DRP_OLD) || defined(TEST_USB_PE_DRP_OLD_NOEXTENDED)
-#define CONFIG_TEST_USB_PE_SM
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PE_SM
-#define CONFIG_USB_PID 0x5036
-#define CONFIG_USB_POWER_DELIVERY
-#undef CONFIG_USB_PRL_SM
-#define CONFIG_USB_PD_REV30
-
-#if defined(TEST_USB_PE_DRP_OLD)
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#endif
-
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#undef CONFIG_USB_TYPEC_SM
-#define CONFIG_USBC_VCONN
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#undef CONFIG_USB_PD_HOST_CMD
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
-#endif
-
-#if defined(TEST_USB_PE_DRP) || defined(TEST_USB_PE_DRP_NOEXTENDED)
-#define CONFIG_TEST_USB_PE_SM
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PE_SM
-#define CONFIG_USB_PID 0x5036
-#define CONFIG_USB_POWER_DELIVERY
-#undef CONFIG_USB_PRL_SM
-#define CONFIG_USB_PD_REV30
-
-#if defined(TEST_USB_PE_DRP)
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#endif
-
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#undef CONFIG_USB_TYPEC_SM
-#define CONFIG_USBC_VCONN
-#define CONFIG_USB_PD_DISCHARGE_GPIO
-#undef CONFIG_USB_PD_HOST_CMD
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USBC_SS_MUX
-#define I2C_PORT_HOST_TCPC 0
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
-#endif /* TEST_USB_PE_DRP || TEST_USB_PE_DRP_NOEXTENDED */
-
-/* Common TypeC tests defines */
-#if defined(TEST_USB_TYPEC_VPD) || \
-	defined(TEST_USB_TYPEC_CTVPD)
-#define CONFIG_USB_PID 0x5036
-#define VPD_HW_VERSION 0x0001
-#define VPD_FW_VERSION 0x0001
-#define USB_BCD_DEVICE 0
-#define VPD_CT_CURRENT VPD_CT_CURRENT_3A
-/* Vbus impedance in milliohms */
-#define VPD_VBUS_IMPEDANCE 65
-
-/* GND impedance in milliohms */
-#define VPD_GND_IMPEDANCE 33
-
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PE_SM
-#define CONFIG_USB_PRL_SM
-#define CONFIG_USB_TYPEC_SM
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_SW_CRC
-#undef CONFIG_USB_PD_HOST_CMD
-#endif /* Common TypeC test defines */
-
-#ifdef TEST_USB_TYPEC_VPD
-#define CONFIG_USB_VPD
-#endif
-
-#ifdef TEST_USB_TYPEC_CTVPD
-#define CONFIG_USB_CTVPD
-#endif
-
-#ifdef TEST_USB_TYPEC_DRP_ACC_TRYSRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_TYPEC_SM
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_POWER_DELIVERY
-#undef CONFIG_USB_PRL_SM
-#undef CONFIG_USB_PE_SM
-#undef CONFIG_USB_PD_HOST_CMD
-#endif
-
-#ifdef TEST_USB_TCPMV2_COMPLIANCE
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_TEST_USB_PE_SM
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PID 0x5036
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_BATTERY
-#define CONFIG_NUM_FIXED_BATTERIES 1
-#define I2C_PORT_HOST_TCPC 0
-#define CONFIG_USB_PD_DEBUG_LEVEL 3
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_3A_PORTS 0 /* Host does not define a 3.0 A PDO */
-#endif
-
-#ifdef TEST_USB_PD_INT
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#endif
-
-#if defined(TEST_USB_PD) || defined(TEST_USB_PD_GIVEBACK) || \
-	defined(TEST_USB_PD_REV30)
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPC
-#define CONFIG_USB_PD_TCPM_STUB
-#define CONFIG_SHA256
-#define CONFIG_SW_CRC
-#ifdef TEST_USB_PD_REV30
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#define CONFIG_USB_PID 0x5000
-#endif
-#ifdef TEST_USB_PD_GIVEBACK
-#define CONFIG_USB_PD_GIVE_BACK
-#endif
-#endif /* TEST_USB_PD || TEST_USB_PD_GIVEBACK || TEST_USB_PD_REV30 */
-
-#ifdef TEST_USB_PPC
-#define CONFIG_USB_PD_PORT_MAX_COUNT 1
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_SBU
-#define CONFIG_USBC_PPC_VCONN
-#endif
-
-#if defined(TEST_CHARGE_MANAGER) || defined(TEST_CHARGE_MANAGER_DRP_CHARGING)
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_BATTERY
-#define CONFIG_BATTERY_SMART
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_BATTERY 0
-#endif /* TEST_CHARGE_MANAGER_* */
-
-#ifdef TEST_CHARGE_MANAGER_DRP_CHARGING
-#define CONFIG_CHARGE_MANAGER_DRP_CHARGING
-#else
-#undef CONFIG_CHARGE_MANAGER_DRP_CHARGING
-#endif /* TEST_CHARGE_MANAGER_DRP_CHARGING */
-
-#ifdef TEST_CHARGE_RAMP
-#define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#endif
-
-#ifdef TEST_RTC
-#define CONFIG_HOSTCMD_RTC
-#endif
-
-#ifdef TEST_VBOOT
-#define CONFIG_RWSIG
-#define CONFIG_SHA256
-#define CONFIG_RSA
-#define CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#endif
-
-#ifdef TEST_X25519
-#define CONFIG_CURVE25519
-#endif /* TEST_X25519 */
-
-#ifdef TEST_I2C_BITBANG
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_BITBANG
-#define I2C_BITBANG_PORT_COUNT 1
-#endif
-
-#endif  /* TEST_BUILD */
-#endif  /* __TEST_TEST_CONFIG_H */
diff --git a/test/thermal.c b/test/thermal.c
deleted file mode 100644
index 1161ecbf1b..0000000000
--- a/test/thermal.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test thermal engine.
- */
-
-#include "common.h"
-#include "console.h"
-#include "driver/temp_sensor/thermistor.h"
-#include "fan.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "printf.h"
-#include "temp_sensor.h"
-#include "test_util.h"
-#include "thermal.h"
-#include "timer.h"
-#include "util.h"
-
-
-/*****************************************************************************/
-/* Exported data */
-
-struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
-
-/* The tests below make some assumptions. */
-BUILD_ASSERT(TEMP_SENSOR_COUNT == 4);
-BUILD_ASSERT(EC_TEMP_THRESH_COUNT == 3);
-
-/*****************************************************************************/
-/* Mock functions */
-
-static int mock_temp[TEMP_SENSOR_COUNT];
-static int host_throttled;
-static int cpu_throttled;
-static int cpu_shutdown;
-static int fan_pct;
-static int no_temps_read;
-
-int mock_temp_get_val(int idx, int *temp_ptr)
-{
-	if (mock_temp[idx] >= 0) {
-		*temp_ptr = mock_temp[idx];
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_NOT_POWERED;
-}
-
-void chipset_force_shutdown(void)
-{
-	cpu_shutdown = 1;
-}
-
-void chipset_throttle_cpu(int throttled)
-{
-	cpu_throttled = throttled;
-}
-
-void host_throttle_cpu(int throttled)
-{
-	host_throttled = throttled;
-}
-
-void fan_set_percent_needed(int fan, int pct)
-{
-	fan_pct = pct;
-}
-
-void smi_sensor_failure_warning(void)
-{
-	no_temps_read = 1;
-}
-
-/*****************************************************************************/
-/* Test utilities */
-
-static void set_temps(int t0, int t1, int t2, int t3)
-{
-	mock_temp[0] = t0;
-	mock_temp[1] = t1;
-	mock_temp[2] = t2;
-	mock_temp[3] = t3;
-}
-
-static void all_temps(int t)
-{
-	set_temps(t, t, t, t);
-}
-
-static void reset_mocks(void)
-{
-	/* Ignore all sensors */
-	memset(thermal_params, 0, sizeof(thermal_params));
-
-	/* All sensors report error anyway */
-	set_temps(-1, -1 , -1, -1);
-
-	/* Reset expectations */
-	host_throttled = 0;
-	cpu_throttled = 0;
-	cpu_shutdown = 0;
-	fan_pct = 0;
-	no_temps_read = 0;
-}
-
-
-/*****************************************************************************/
-/* Tests */
-
-static int test_init_val(void)
-{
-	reset_mocks();
-	sleep(2);
-
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-	TEST_ASSERT(fan_pct == 0);
-	TEST_ASSERT(no_temps_read);
-
-	sleep(2);
-
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-	TEST_ASSERT(fan_pct == 0);
-	TEST_ASSERT(no_temps_read);
-
-	return EC_SUCCESS;
-}
-
-static int test_sensors_can_be_read(void)
-{
-	reset_mocks();
-	mock_temp[2] = 100;
-
-	sleep(2);
-
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-	TEST_ASSERT(fan_pct == 0);
-	TEST_ASSERT(no_temps_read == 0);
-
-	return EC_SUCCESS;
-}
-
-
-static int test_one_fan(void)
-{
-	reset_mocks();
-	thermal_params[2].temp_fan_off = 100;
-	thermal_params[2].temp_fan_max = 200;
-
-	all_temps(50);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	all_temps(100);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	all_temps(101);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 1);
-
-	all_temps(130);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 30);
-
-	all_temps(150);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	all_temps(170);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 70);
-
-	all_temps(200);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	all_temps(300);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	return EC_SUCCESS;
-}
-
-static int test_two_fans(void)
-{
-	reset_mocks();
-
-	thermal_params[1].temp_fan_off = 120;
-	thermal_params[1].temp_fan_max = 160;
-	thermal_params[2].temp_fan_off = 100;
-	thermal_params[2].temp_fan_max = 200;
-
-	all_temps(50);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	all_temps(100);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	all_temps(101);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 1);
-
-	all_temps(130);
-	sleep(2);
-	/* fan 2 is still higher */
-	TEST_ASSERT(fan_pct == 30);
-
-	all_temps(150);
-	sleep(2);
-	/* now fan 1 is higher: 150 = 75% of [120-160] */
-	TEST_ASSERT(fan_pct == 75);
-
-	all_temps(170);
-	sleep(2);
-	/* fan 1 is maxed now */
-	TEST_ASSERT(fan_pct == 100);
-
-	all_temps(200);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	all_temps(300);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	return EC_SUCCESS;
-}
-
-static int test_all_fans(void)
-{
-	reset_mocks();
-
-	thermal_params[0].temp_fan_off = 20;
-	thermal_params[0].temp_fan_max = 60;
-	thermal_params[1].temp_fan_off = 120;
-	thermal_params[1].temp_fan_max = 160;
-	thermal_params[2].temp_fan_off = 100;
-	thermal_params[2].temp_fan_max = 200;
-	thermal_params[3].temp_fan_off = 300;
-	thermal_params[3].temp_fan_max = 500;
-
-	set_temps(1, 1, 1, 1);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	/* Each sensor has its own range */
-	set_temps(40, 0, 0, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	set_temps(0, 140, 0, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	set_temps(0, 0, 150, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	set_temps(0, 0, 0, 400);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	set_temps(60, 0, 0, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	set_temps(0, 160, 0, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	set_temps(0, 0, 200, 0);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	set_temps(0, 0, 0, 500);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	/* But sensor 0 needs the most cooling */
-	all_temps(20);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 0);
-
-	all_temps(21);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 2);
-
-	all_temps(30);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 25);
-
-	all_temps(40);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 50);
-
-	all_temps(50);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 75);
-
-	all_temps(60);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	all_temps(65);
-	sleep(2);
-	TEST_ASSERT(fan_pct == 100);
-
-	return EC_SUCCESS;
-}
-
-static int test_one_limit(void)
-{
-	reset_mocks();
-	thermal_params[2].temp_host[EC_TEMP_THRESH_WARN] = 100;
-	thermal_params[2].temp_host[EC_TEMP_THRESH_HIGH] = 200;
-	thermal_params[2].temp_host[EC_TEMP_THRESH_HALT] = 300;
-
-	all_temps(50);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(100);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(101);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(100);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(99);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(199);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(200);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(201);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(200);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(199);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(99);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(201);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(99);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	all_temps(301);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 1);
-
-	/* We probably won't be able to read the CPU temp while shutdown,
-	 * so nothing will change. */
-	all_temps(-1);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	/* cpu_shutdown is only set for testing purposes. The thermal task
-	 * doesn't do anything that could clear it. */
-
-	all_temps(50);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_several_limits(void)
-{
-	reset_mocks();
-
-	thermal_params[1].temp_host[EC_TEMP_THRESH_WARN] = 150;
-	thermal_params[1].temp_host[EC_TEMP_THRESH_HIGH] = 200;
-	thermal_params[1].temp_host[EC_TEMP_THRESH_HALT] = 250;
-
-	thermal_params[2].temp_host[EC_TEMP_THRESH_WARN] = 100;
-	thermal_params[2].temp_host[EC_TEMP_THRESH_HIGH] = 200;
-	thermal_params[2].temp_host[EC_TEMP_THRESH_HALT] = 300;
-
-	thermal_params[3].temp_host[EC_TEMP_THRESH_WARN] = 20;
-	thermal_params[3].temp_host[EC_TEMP_THRESH_HIGH] = 30;
-	thermal_params[3].temp_host[EC_TEMP_THRESH_HALT] = 40;
-
-	set_temps(500, 100, 150, 10);
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1); /* 1=low, 2=warn, 3=low */
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	set_temps(500, 50, -1, 10);	/* 1=low, 2=X, 3=low */
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	set_temps(500, 170, 210, 10);	/* 1=warn, 2=high, 3=low */
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	set_temps(500, 100, 50, 40);	/* 1=low, 2=low, 3=high */
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 0);
-
-	set_temps(500, 100, 50, 41);	/* 1=low, 2=low, 3=shutdown */
-	sleep(2);
-	TEST_ASSERT(host_throttled == 1);
-	TEST_ASSERT(cpu_throttled == 1);
-	TEST_ASSERT(cpu_shutdown == 1);
-
-	all_temps(0);			/* reset from shutdown */
-	sleep(2);
-	TEST_ASSERT(host_throttled == 0);
-	TEST_ASSERT(cpu_throttled == 0);
-
-
-	return EC_SUCCESS;
-}
-
-/* Tests for ncp15wb thermistor ADC-to-temp calculation */
-#define LOW_ADC_TEST_VALUE	887 /* 0 C */
-#define HIGH_ADC_TEST_VALUE	100 /* > 100C */
-
-static int test_ncp15wb_adc_to_temp(void)
-{
-	int i;
-	uint8_t temp;
-	uint8_t new_temp;
-
-	/* ADC value to temperature table, data from datasheet */
-	struct {
-		int adc;
-		int temp;
-	} adc_temp_datapoints[] = {
-		{ 615, 30 },
-		{ 561, 35 },
-		{ 508, 40 },
-		{ 407, 50 },
-		{ 315, 60 },
-		{ 243, 70 },
-		{ 186, 80 },
-		{ 140, 90 },
-		{ 107, 100 },
-	};
-
-
-	/*
-	 * Verify that calculated temp is decreasing for entire ADC range,
-	 * and that a tick down in ADC value results in no more than 1C
-	 * decrease.
-	 */
-	i = LOW_ADC_TEST_VALUE;
-	temp = ncp15wb_calculate_temp(i);
-
-	while (--i > HIGH_ADC_TEST_VALUE) {
-		new_temp = ncp15wb_calculate_temp(i);
-		TEST_ASSERT(new_temp == temp ||
-			    new_temp == temp + 1);
-		temp = new_temp;
-	}
-
-	/* Verify several datapoints are within 1C accuracy */
-	for (i = 0; i < ARRAY_SIZE(adc_temp_datapoints); ++i) {
-		temp = ncp15wb_calculate_temp(adc_temp_datapoints[i].adc);
-		ASSERT(temp >= adc_temp_datapoints[i].temp - 1 &&
-		       temp <= adc_temp_datapoints[i].temp + 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-#define THERMISTOR_SCALING_FACTOR 13
-static int test_thermistor_linear_interpolate(void)
-{
-	int i, t, t0;
-	uint16_t mv;
-	/* Simple test case - a straight line. */
-	struct thermistor_data_pair line_data[] = {
-		{ 100, 0 }, { 0, 100 }
-	};
-	struct thermistor_info line_info = {
-		.scaling_factor = 1,
-		.num_pairs = ARRAY_SIZE(line_data),
-		.data = line_data,
-	};
-	/*
-	 * Modelled test case - Data derived from Seinhart-Hart equation in a
-	 * resistor divider circuit with Vdd=3300mV, R = 51.1Kohm, and Murata
-	 * NCP15WB-series thermistor (B = 4050, T0 = 298.15, nominal
-	 * resistance (R0) = 47Kohm).
-	 */
-	struct thermistor_data_pair data[] = {
-		{ 2512 / THERMISTOR_SCALING_FACTOR, 0 },
-		{ 2158 / THERMISTOR_SCALING_FACTOR, 10 },
-		{ 1772 / THERMISTOR_SCALING_FACTOR, 20 },
-		{ 1398 / THERMISTOR_SCALING_FACTOR, 30 },
-		{ 1070 / THERMISTOR_SCALING_FACTOR, 40 },
-		{ 803 / THERMISTOR_SCALING_FACTOR, 50 },
-		{ 597 / THERMISTOR_SCALING_FACTOR, 60 },
-		{ 443 / THERMISTOR_SCALING_FACTOR, 70 },
-		{ 329 / THERMISTOR_SCALING_FACTOR, 80 },
-		{ 247 / THERMISTOR_SCALING_FACTOR, 90 },
-		{ 188 / THERMISTOR_SCALING_FACTOR, 100 },
-	};
-	struct thermistor_info info = {
-		.scaling_factor = THERMISTOR_SCALING_FACTOR,
-		.num_pairs = ARRAY_SIZE(data),
-		.data = data,
-	};
-	/*
-	 * Reference data points to compare accuracy, taken from same set
-	 * of derived values but at temp - 1, temp + 1, and in between.
-	 */
-	struct {
-		uint16_t mv;	/* not scaled */
-		int temp;
-	} cmp[] = {
-		{ 3030, 1 },  { 2341, 5 }, { 2195, 9 },
-		{ 2120, 11 }, { 1966, 15 }, { 1811, 19 },
-		{ 1733, 21 }, { 1581, 25 }, { 1434, 29 },
-		{ 1363, 31 }, { 1227, 35 }, { 1100, 39 },
-		{ 1040, 41 }, { 929, 45 }, { 827, 49 },
-		{ 780, 51 }, { 693, 55 }, { 615, 59 },
-		{ 579, 61 }, { 514, 65 }, { 460, 69 },
-		{ 430, 71 }, { 382, 75 }, { 339, 79 },
-		{ 320, 81 }, { 285, 85 }, { 254, 89 },
-		{ 240, 91 }, { 214, 95 }, { 192, 99 },
-	};
-
-	/* Return lowest temperature in data set if voltage is too high. */
-	mv = (data[0].mv * info.scaling_factor) + 1;
-	t = thermistor_linear_interpolate(mv, &info);
-	TEST_ASSERT(t == data[0].temp);
-
-	/* Return highest temperature in data set if voltage is too low. */
-	mv = (data[info.num_pairs - 1].mv * info.scaling_factor) - 1;
-	t = thermistor_linear_interpolate(mv, &info);
-	TEST_ASSERT(t == data[info.num_pairs - 1].temp);
-
-	/* Simple line test */
-	for (mv = line_data[0].mv;
-		mv > line_data[line_info.num_pairs - 1].mv;
-		mv--) {
-		t = thermistor_linear_interpolate(mv, &line_info);
-		TEST_ASSERT(mv == line_data[line_info.num_pairs - 1].temp - t);
-	}
-
-	/*
-	 * Verify that calculated temperature monotonically
-	 * decreases with increase in voltage (0-5V, 10mV steps).
-	 */
-	for (mv = data[0].mv * info.scaling_factor, t0 = data[0].temp;
-		mv > data[info.num_pairs - 1].mv;
-		mv -= 10) {
-		int t1 = thermistor_linear_interpolate(mv, &info);
-
-		TEST_ASSERT(t1 >= t0);
-		t0 = t1;
-	}
-
-	/* Verify against modelled data, +/- 1C due to scaling. */
-	for (i = 0; i < info.num_pairs; i++) {
-		mv = data[i].mv * info.scaling_factor;
-
-		t = thermistor_linear_interpolate(mv, &info);
-		TEST_ASSERT(t >= data[i].temp - 1 && t <= data[i].temp + 1);
-	}
-
-	/*
-	 * Verify data points that are interpolated by algorithm, allowing
-	 * 1C of inaccuracy.
-	 */
-	for (i = 0; i < ARRAY_SIZE(cmp); i++) {
-		t = thermistor_linear_interpolate(cmp[i].mv, &info);
-		TEST_ASSERT(t >= cmp[i].temp - 1 && t <= cmp[i].temp + 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_init_val);
-	RUN_TEST(test_sensors_can_be_read);
-	RUN_TEST(test_one_fan);
-	RUN_TEST(test_two_fans);
-	RUN_TEST(test_all_fans);
-
-	RUN_TEST(test_one_limit);
-	RUN_TEST(test_several_limits);
-
-	RUN_TEST(test_ncp15wb_adc_to_temp);
-	RUN_TEST(test_thermistor_linear_interpolate);
-	test_print_result();
-}
diff --git a/test/thermal.tasklist b/test/thermal.tasklist
deleted file mode 100644
index d22719d1fb..0000000000
--- a/test/thermal.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/timer_calib.c b/test/timer_calib.c
deleted file mode 100644
index 68603762fe..0000000000
--- a/test/timer_calib.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tasks for scheduling test.
- */
-
-#include "common.h"
-#include "console.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-uint32_t difftime(timestamp_t t0, timestamp_t t1)
-{
-	return (uint32_t)(t1.val-t0.val);
-}
-
-int timer_calib_task(void *data)
-{
-	timestamp_t t0, t1;
-	unsigned d;
-
-	while (1) {
-		task_wait_event(-1);
-
-		ccprintf("\n=== Timer calibration ===\n");
-
-		t0 = get_time();
-		t1 = get_time();
-		ccprintf("- back-to-back get_time : %d us\n", difftime(t0, t1));
-
-		/* Sleep for 5 seconds */
-		ccprintf("- sleep 1s :\n  ");
-		cflush();
-		ccprintf("Go...");
-		t0 = get_time();
-		usleep(1000000);
-		t1 = get_time();
-		ccprintf("done. delay = %d us\n", difftime(t0, t1));
-
-		/* try small usleep */
-		ccprintf("- short sleep :\n");
-		cflush();
-		for (d = 128; d > 0; d = d / 2) {
-			t0 = get_time();
-			usleep(d);
-			t1 = get_time();
-			ccprintf("  %d us => %d us\n", d, difftime(t0, t1));
-			cflush();
-		}
-
-		ccprintf("Done.\n");
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	task_wake(TASK_ID_TESTTMR);
-}
diff --git a/test/timer_calib.py b/test/timer_calib.py
deleted file mode 100644
index 2a625d80c7..0000000000
--- a/test/timer_calib.py
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright 2011 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Check timers behavior
-#
-
-import time
-
-def one_pass(helper):
-      helper.wait_output("=== Timer calibration ===")
-      res = helper.wait_output("back-to-back get_time : (?P<lat>[0-9]+) us",
-                               use_re=True)["lat"]
-      minlat = int(res)
-      helper.trace("get_time latency %d us\n" % minlat)
-
-      helper.wait_output("sleep 1s")
-      t0 = time.time()
-      second = helper.wait_output("done. delay = (?P<second>[0-9]+) us",
-                               use_re=True)["second"]
-      t1 = time.time()
-      secondreal = t1 - t0
-      secondlat = int(second) - 1000000
-      helper.trace("1s timer latency %d us / real time %f s\n" % (secondlat,
-                                                                  secondreal))
-
-
-      us = {}
-      for pow2 in range(7):
-          delay = 1 << (7-pow2)
-          us[delay] = helper.wait_output("%d us => (?P<us>[0-9]+) us" % delay,
-                                  use_re=True)["us"]
-      helper.wait_output("Done.")
-
-      return minlat, secondlat, secondreal
-
-
-def test(helper):
-      one_pass(helper)
-
-      helper.ec_command("reboot")
-      helper.wait_output("--- UART initialized")
-
-      # get the timing results on the second pass
-      # to avoid binary translation overhead
-      minlat, secondlat, secondreal = one_pass(helper)
-
-      # check that the timings somewhat make sense
-      if minlat > 220 or secondlat > 500 or abs(secondreal-1.0) > 0.200:
-           helper.fail("imprecise timings " +
-                       "(get_time %d us sleep %d us / real time %.3f s)" %
-                       (minlat, secondlat, secondreal))
-
-      return True # PASS !
diff --git a/test/timer_calib.tasklist b/test/timer_calib.tasklist
deleted file mode 100644
index 51f5beb6c1..0000000000
--- a/test/timer_calib.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(TESTTMR, timer_calib_task, NULL, TASK_STACK_SIZE)
diff --git a/test/timer_dos.c b/test/timer_dos.c
deleted file mode 100644
index c681300102..0000000000
--- a/test/timer_dos.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Tasks for timer test.
- */
-
-#include "common.h"
-#include "console.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-/* period between 500us and 128ms */
-#define PERIOD_US(num) (((num % 256) + 1) * 500)
-
-#define TEST_TIME (3 * SECOND)
-
-#define ERROR_MARGIN 5
-
-static int calculate_golden(uint32_t seed)
-{
-	int golden = 0;
-	uint32_t elapsed = 0;
-	while (1) {
-		elapsed += PERIOD_US(seed);
-		++golden;
-		if (elapsed >= TEST_TIME)
-			return golden;
-		seed = prng(seed);
-	}
-}
-
-int task_timer(void *seed)
-{
-	uint32_t num = (uint32_t)(uintptr_t)seed;
-	int golden_cnt = calculate_golden(num);
-	task_id_t id = task_get_current();
-	timestamp_t start;
-	int cnt = 0;
-
-	while (1) {
-		task_wait_event(-1);
-
-		ccprintf("\n[Timer task %d]\n", id);
-		start = get_time();
-
-		while (get_time().val - start.val < TEST_TIME) {
-			/* Wait for a "random" period */
-			task_wait_event(PERIOD_US(num));
-			ccprintf("%01d\n", id);
-			cnt++;
-			/* next pseudo random delay */
-			num = prng(num);
-		}
-		ccprintf("Task %d: Count=%d Golden=%d\n", id, cnt, golden_cnt);
-		cnt -= golden_cnt;
-		if (cnt < 0)
-			cnt = -cnt;
-		if (cnt > ERROR_MARGIN) {
-			ccprintf("Count differs from Golden by more than %d!\n",
-				 ERROR_MARGIN);
-			test_fail();
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	wait_for_task_started();
-	task_wake(TASK_ID_TMRD);
-	task_wake(TASK_ID_TMRC);
-	task_wake(TASK_ID_TMRB);
-	task_wake(TASK_ID_TMRA);
-	usleep(TEST_TIME + SECOND);
-	test_pass();
-}
diff --git a/test/timer_dos.tasklist b/test/timer_dos.tasklist
deleted file mode 100644
index 4da3419f77..0000000000
--- a/test/timer_dos.tasklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-  TASK_TEST(TMRA, task_timer, (void *)1234, TASK_STACK_SIZE) \
-  TASK_TEST(TMRB, task_timer, (void *)5678, TASK_STACK_SIZE) \
-  TASK_TEST(TMRC, task_timer, (void *)8462, TASK_STACK_SIZE) \
-  TASK_TEST(TMRD, task_timer, (void *)3719, TASK_STACK_SIZE)
diff --git a/test/timer_jump.py b/test/timer_jump.py
deleted file mode 100644
index f506a69fcf..0000000000
--- a/test/timer_jump.py
+++ /dev/null
@@ -1,31 +0,0 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Timer test: check time consistency when jumping between images
-#
-
-import time
-
-DELAY = 5
-ERROR_MARGIN = 0.5
-
-def test(helper):
-      helper.wait_output("idle task started")
-      helper.ec_command("sysinfo")
-      copy = helper.wait_output("Copy:\s+(?P<c>\S+)", use_re=True)["c"]
-      if copy != "RO":
-          helper.ec_command("sysjump ro")
-          helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_start_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                         use_re=True)["t"]
-      time.sleep(DELAY)
-      helper.ec_command("sysjump a")
-      helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_end_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                       use_re=True)["t"]
-
-      time_diff = float(ec_end_time) - float(ec_start_time)
-      return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN
diff --git a/test/timer_jump.tasklist b/test/timer_jump.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/timer_jump.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/uptime.c b/test/uptime.c
deleted file mode 100644
index 651628ab7b..0000000000
--- a/test/uptime.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-
-#include "common.h"
-#include "ec_commands.h"
-#include "host_command.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static bool get_ap_reset_stats_should_succeed = true;
-
-/* Mocks */
-
-enum ec_error_list
-get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
-		   size_t num_reset_log_entries, uint32_t *resets_since_ec_boot)
-{
-	return get_ap_reset_stats_should_succeed ? EC_SUCCESS : EC_ERROR_INVAL;
-}
-
-timestamp_t get_time(void)
-{
-	timestamp_t fake_time = { .val = 42 * MSEC };
-	return fake_time;
-}
-
-/* Tests */
-
-test_static int test_host_uptime_info_command_success(void)
-{
-	int rv;
-	struct ec_response_uptime_info resp = { 0 };
-
-	get_ap_reset_stats_should_succeed = true;
-
-	rv = test_send_host_command(EC_CMD_GET_UPTIME_INFO, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	TEST_ASSERT(rv == EC_RES_SUCCESS);
-	TEST_ASSERT(resp.time_since_ec_boot_ms == 42);
-
-	return EC_RES_SUCCESS;
-}
-
-test_static int test_host_uptime_info_command_failure(void)
-{
-	int rv;
-	struct ec_response_uptime_info resp = { 0 };
-
-	get_ap_reset_stats_should_succeed = false;
-
-	rv = test_send_host_command(EC_CMD_GET_UPTIME_INFO, 0, NULL, 0, &resp,
-				    sizeof(resp));
-
-	TEST_ASSERT(rv == EC_RES_ERROR);
-
-	return EC_RES_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_host_uptime_info_command_success);
-	RUN_TEST(test_host_uptime_info_command_failure);
-
-	test_print_result();
-}
diff --git a/test/uptime.tasklist b/test/uptime.tasklist
deleted file mode 100644
index 9bf1c80c20..0000000000
--- a/test/uptime.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
-
diff --git a/test/usb_common.tasklist b/test/usb_common.tasklist
deleted file mode 100644
index 9bf1c80c20..0000000000
--- a/test/usb_common.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
-
diff --git a/test/usb_common_test.c b/test/usb_common_test.c
deleted file mode 100644
index 620e061f74..0000000000
--- a/test/usb_common_test.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB common module.
- */
-#include "test_util.h"
-#include "usb_common.h"
-
-int test_pd_get_cc_state(void)
-{
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_3_0),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_DEF),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_1_5),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_DEF),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_RP_3_0),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_RP_1_5),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_RP_DEF),
-		PD_CC_DFP_DEBUG_ACC, "%d");
-
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_OPEN),
-		PD_CC_DFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_OPEN),
-		PD_CC_DFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN),
-		PD_CC_DFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_3_0),
-		PD_CC_DFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_1_5),
-		PD_CC_DFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF),
-		PD_CC_DFP_ATTACHED, "%d");
-
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RD),
-		PD_CC_UFP_DEBUG_ACC, "%d");
-
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RA),
-		PD_CC_UFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_OPEN),
-		PD_CC_UFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD),
-		PD_CC_UFP_ATTACHED, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RD),
-		PD_CC_UFP_ATTACHED, "%d");
-
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RA),
-		PD_CC_UFP_AUDIO_ACC, "%d");
-
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN),
-		PD_CC_NONE, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA),
-		PD_CC_NONE, "%d");
-	TEST_EQ(pd_get_cc_state(TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_OPEN),
-		PD_CC_NONE, "%d");
-
-	return EC_SUCCESS;
-}
-
-/*
- * From USB Power Delivery Specification Revision 3.0, Version 2.0
- * Table 6-7 Power Data Object
- */
-#define MAKE_FIXED(v, c) (0 << 30 | (v / 50) << 10 | (c / 10))
-#define MAKE_BATT(v_max, v_min, p) \
-	(1 << 30 | (v_max / 50) << 20 | (v_min / 50) << 10 | (p / 250))
-#define MAKE_VAR(v_max, v_min, c) \
-	(2 << 30 | (v_max / 50) << 20 | (v_min / 50) << 10 | (c / 10))
-#define MAKE_AUG(v_max, v_min, c) \
-	(3 << 30 | (v_max / 100) << 17 | (v_min / 100) << 8 | (c / 50))
-
-/*
- * Tests various cases for pd_extract_pdo_power. It takes a very high voltage to
- * exceed PD_MAX_POWER_MW without also exceeding PD_MAX_CURRENT_MA, so those
- * tests are not particularly realistic.
- */
-int test_pd_extract_pdo_power(void)
-{
-	uint32_t ma;
-	uint32_t max_mv;
-	uint32_t min_mv;
-
-	pd_extract_pdo_power(MAKE_FIXED(/*v=*/5000, /*c=*/3000), &ma, &max_mv,
-			     &min_mv);
-	TEST_EQ(max_mv, 5000, "%d");
-	TEST_EQ(min_mv, 5000, "%d");
-	TEST_EQ(ma, 3000, "%d");
-	pd_extract_pdo_power(MAKE_FIXED(/*v=*/20000, /*c=*/2600), &ma, &max_mv,
-			     &min_mv);
-	TEST_EQ(max_mv, 20000, "%d");
-	TEST_EQ(min_mv, 20000, "%d");
-	TEST_EQ(ma, 2600, "%d");
-	pd_extract_pdo_power(MAKE_FIXED(/*v=*/20000, /*c=*/4000), &ma, &max_mv,
-			     &min_mv);
-	TEST_EQ(max_mv, 20000, "%d");
-	TEST_EQ(min_mv, 20000, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-	pd_extract_pdo_power(MAKE_FIXED(/*v=*/10000, /*c=*/4000), &ma, &max_mv,
-			     &min_mv);
-	TEST_EQ(max_mv, 10000, "%d");
-	TEST_EQ(min_mv, 10000, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-	pd_extract_pdo_power(MAKE_FIXED(/*v=*/21000, /*c=*/4000), &ma, &max_mv,
-			     &min_mv);
-	TEST_EQ(max_mv, 21000, "%d");
-	TEST_EQ(min_mv, 21000, "%d");
-	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
-
-	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/5700, /*v_min=*/3300,
-				       /*p=*/7000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 5700, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 2121, "%d"); /* 3300mV * 2121mA ~= 7000mW */
-	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/3300, /*v_min=*/2700,
-				       /*p=*/12000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 3300, "%d");
-	TEST_EQ(min_mv, 2700, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-
-	pd_extract_pdo_power(MAKE_BATT(/*v_max=*/25000, /*v_min=*/21000,
-				       /*p=*/61000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 25000, "%d");
-	TEST_EQ(min_mv, 21000, "%d");
-	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
-
-	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/5000, /*v_min=*/3300,
-				      /*c=*/3000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 5000, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 3000, "%d");
-	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/20000, /*v_min=*/5000,
-				      /*c=*/2600),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 20000, "%d");
-	TEST_EQ(min_mv, 5000, "%d");
-	TEST_EQ(ma, 2600, "%d");
-	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/20000, /*v_min=*/5000,
-				      /*c=*/4000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 20000, "%d");
-	TEST_EQ(min_mv, 5000, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/10000, /*v_min=*/3300,
-				      /*c=*/4000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 10000, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-	pd_extract_pdo_power(MAKE_VAR(/*v_max=*/22000, /*v_min=*/21000,
-				      /*c=*/4000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 22000, "%d");
-	TEST_EQ(min_mv, 21000, "%d");
-	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
-
-	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/5000, /*v_min=*/3300,
-				      /*c=*/3000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 5000, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 3000, "%d");
-	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/20000, /*v_min=*/3300,
-				      /*c=*/2600),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 20000, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 2600, "%d");
-	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/10000, /*v_min=*/3300,
-				      /*c=*/4000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 10000, "%d");
-	TEST_EQ(min_mv, 3300, "%d");
-	TEST_EQ(ma, 3000, "%d"); /* Capped at PD_MAX_CURRENT_MA */
-	pd_extract_pdo_power(MAKE_AUG(/*v_max=*/22000, /*v_min=*/21000,
-				      /*c=*/4000),
-			     &ma, &max_mv, &min_mv);
-	TEST_EQ(max_mv, 22000, "%d");
-	TEST_EQ(min_mv, 21000, "%d");
-	TEST_EQ(ma, 2857, "%d"); /* Capped at PD_MAX_POWER_MW */
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_pd_get_cc_state);
-	RUN_TEST(test_pd_extract_pdo_power);
-
-	test_print_result();
-}
diff --git a/test/usb_pd.c b/test/usb_pd.c
deleted file mode 100644
index 9fdb439b49..0000000000
--- a/test/usb_pd.c
+++ /dev/null
@@ -1,918 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PD module.
- */
-#include "battery.h"
-#include "common.h"
-#include "crc.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_pd_test_util.h"
-#include "util.h"
-
-#define PORT0	0
-#define PORT1	1
-
-#define BATTERY_DESIGN_VOLTAGE 7600
-#define BATTERY_DESIGN_CAPACITY 5131
-#define BATTERY_FULL_CHARGE_CAPACITY 5131
-#define BATTERY_REMAINING_CAPACITY 2566
-
-struct pd_port_t {
-	int host_mode;
-	int has_vbus;
-	int msg_tx_id;
-	int msg_rx_id;
-	int polarity;
-	int partner_role; /* -1 for none */
-	int partner_polarity;
-	int rev;
-} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static int give_back_called;
-
-/* Mock functions */
-#ifdef CONFIG_USB_PD_REV30
-
-uint16_t pd_get_identity_vid(int port)
-{
-	return 0;
-}
-
-uint16_t pd_get_identity_pid(int port)
-{
-	return 0;
-}
-
-int battery_status(int *status)
-{
-	*status = 1;
-	return 0;
-}
-
-int battery_remaining_capacity(int *capacity)
-{
-	*capacity = BATTERY_REMAINING_CAPACITY;
-	return 0;
-}
-
-int battery_full_charge_capacity(int *capacity)
-{
-	*capacity = BATTERY_FULL_CHARGE_CAPACITY;
-	return 0;
-}
-
-int battery_design_capacity(int *capacity)
-{
-	*capacity = BATTERY_DESIGN_CAPACITY;
-	return 0;
-}
-
-int battery_design_voltage(int *voltage)
-{
-	*voltage = BATTERY_DESIGN_VOLTAGE;
-	return 0;
-}
-
-#endif
-
-int pd_adc_read(int port, int cc)
-{
-	if (pd_port[port].host_mode &&
-	    pd_port[port].partner_role == PD_ROLE_SINK)
-		/* we are source connected to sink, return Rd/Open */
-		return (pd_port[port].partner_polarity == cc) ? 400 : 3000;
-	else if (!pd_port[port].host_mode &&
-		  pd_port[port].partner_role == PD_ROLE_SOURCE)
-		/* we are sink connected to source, return Rp/Open */
-		return (pd_port[port].partner_polarity == cc) ? 1700 : 0;
-	else if (pd_port[port].host_mode)
-		/* no sink on the other side, both CC are opened */
-		return 3000;
-	else if (!pd_port[port].host_mode)
-		/* no source on the other side, both CC are opened */
-		return 0;
-
-	/* should never get here */
-	return 0;
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return pd_port[port].has_vbus;
-}
-
-void pd_set_host_mode(int port, int enable)
-{
-	pd_port[port].host_mode = enable;
-}
-
-void pd_select_polarity(int port, int polarity)
-{
-	pd_port[port].polarity = polarity;
-}
-
-int pd_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
-{
-	return 0;
-}
-
-int board_select_rp_value(int port, int rp)
-{
-	return 0;
-}
-
-/* Tests */
-
-void inc_tx_id(int port)
-{
-	pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) % 7;
-}
-
-void inc_rx_id(int port)
-{
-	pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7;
-}
-
-static void init_ports(void)
-{
-	int i;
-
-	for (i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		pd_port[i].host_mode = 0;
-		pd_port[i].partner_role = -1;
-		pd_port[i].has_vbus = 0;
-#ifdef CONFIG_USB_PD_REV30
-		pd_port[i].rev = PD_REV30;
-#else
-		pd_port[i].rev = PD_REV20;
-#endif
-	}
-}
-
-static void simulate_rx_msg(int port, uint16_t header, int cnt,
-			    const uint32_t *data)
-{
-	int i;
-
-	pd_test_rx_set_preamble(port, 1);
-	pd_test_rx_msg_append_sop(port);
-	pd_test_rx_msg_append_short(port, header);
-
-	crc32_init();
-	crc32_hash16(header);
-	for (i = 0; i < cnt; ++i) {
-		pd_test_rx_msg_append_word(port, data[i]);
-		crc32_hash32(data[i]);
-	}
-	pd_test_rx_msg_append_word(port, crc32_result());
-
-	pd_test_rx_msg_append_eop(port);
-	pd_test_rx_msg_append_last_edge(port);
-
-	pd_simulate_rx(port);
-}
-
-static void simulate_wait(int port)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE,
-				    PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				    0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-}
-
-static void simulate_accept(int port)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-}
-
-static void simulate_reject(int port)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-}
-
-
-#ifdef CONFIG_USB_PD_REV30
-static void simulate_get_bat_cap(int port)
-{
-	uint16_t msg[2];
-	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_CAP, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
-
-	/* set extended header */
-	msg[0] = PD_EXT_HEADER(0, 0, 1);
-
-	/* set battery status ref */
-	msg[1] = 0;
-
-	simulate_rx_msg(port, header, 1, (const uint32_t *)msg);
-}
-
-static void simulate_get_bat_status(int port)
-{
-	uint16_t msg[2];
-	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_STATUS, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
-
-	/* set extended header */
-	msg[0] = PD_EXT_HEADER(0, 0, 1);
-
-	/* set battery status ref */
-	msg[1] = 0;
-
-	simulate_rx_msg(port, header, 1, (const uint32_t *)msg);
-}
-#endif
-
-static void simulate_source_cap(int port, uint32_t cnt)
-{
-	uint32_t src_pdo_cnt = (cnt == 0) ? 1 : pd_src_pdo_cnt;
-
-	uint16_t header = PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE,
-				    PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				    src_pdo_cnt, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, src_pdo_cnt, pd_src_pdo);
-}
-
-static void simulate_goodcrc(int port, int role, int id)
-{
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
-}
-
-static int verify_goodcrc(int port, int role, int id)
-{
-
-	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
-}
-
-static void plug_in_source(int port, int polarity)
-{
-	pd_port[port].has_vbus = 1;
-	pd_port[port].partner_role = PD_ROLE_SOURCE;
-	pd_port[port].partner_polarity = polarity;
-	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-}
-
-static void plug_in_sink(int port, int polarity)
-{
-	pd_port[port].has_vbus = 0;
-	pd_port[port].partner_role = PD_ROLE_SINK;
-	pd_port[port].partner_polarity = polarity;
-	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-}
-
-static void unplug(int port)
-{
-	pd_port[port].msg_tx_id = 0;
-	pd_port[port].msg_rx_id = 0;
-	pd_port[port].has_vbus = 0;
-	pd_port[port].partner_role = -1;
-	/* Indicate that the CC lines have changed. */
-	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	usleep(30 * MSEC);
-}
-
-void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv)
-{
-	if (*ma == 3000)
-		give_back_called = 1;
-}
-
-static void simulate_ps_rdy(int port)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-}
-
-static void simulate_goto_min(int port)
-{
-	uint16_t header = PD_HEADER(PD_CTRL_GOTO_MIN, PD_ROLE_SOURCE,
-		PD_ROLE_DFP, pd_port[port].msg_rx_id, 0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-}
-
-static int test_request_with_wait_and_contract(void)
-{
-#ifdef CONFIG_USB_PD_REV30
-	uint32_t expected_status_bsdo =
-		BSDO_CAP(DIV_ROUND_NEAREST(BATTERY_REMAINING_CAPACITY *
-					BATTERY_DESIGN_VOLTAGE, 100000)) |
-					BSDO_PRESENT;
-	uint16_t expected_cap_hdr = PD_EXT_HEADER(0, 0, 9);
-	uint16_t expected_cap_vid = USB_VID_GOOGLE;
-#ifdef CONFIG_USB_PID
-	uint16_t expected_cap_pid = CONFIG_USB_PID;
-#else
-	uint16_t expected_cap_pid = 0;
-#endif
-	uint16_t expected_cap_des =
-		DIV_ROUND_NEAREST(BATTERY_DESIGN_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
-	uint16_t expected_cap_ful =
-		DIV_ROUND_NEAREST(BATTERY_FULL_CHARGE_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
-	uint16_t expected_cap_type = 0;
-#endif
-
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	uint32_t expected_rdo =
-		RDO_FIXED(2, 3000, PD_MIN_CURRENT_MA, RDO_GIVE_BACK);
-#else
-	uint32_t expected_rdo = RDO_FIXED(2, 3000, 3000, 0);
-#endif
-	uint8_t port = PORT0;
-
-	plug_in_source(port, 0);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(2 * PD_T_CC_DEBOUNCE + 100 * MSEC);
-	TEST_ASSERT(pd_port[port].polarity == 0);
-
-	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
-	simulate_source_cap(port, 1);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-						pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send accept */
-	simulate_accept(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/*
-	 * We're in SNK_TRANSITION.
-	 * And we have an explicit power contract.
-	 */
-	simulate_source_cap(port, 1);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-					pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send wait */
-	simulate_wait(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	/* PD_T_SINK_REQUEST. Request is sent again after 100 ms */
-	task_wait_event(100 * MSEC);
-	inc_rx_id(port);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* We had an explicit contract. So request should have been resent. */
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1,
-			pd_port[port].rev, 0
-	)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send accept */
-	simulate_accept(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* We're in SNK_TRANSITION. Send ps_rdy */
-	simulate_ps_rdy(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/*
-	 * Test Extended Get_Battery_Cap and Get_Battery_Status messages.
-	 */
-#ifdef CONFIG_USB_PD_REV30
-	/* We're in SNK_READY. Send get battery cap. */
-	simulate_get_bat_cap(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-		PD_HEADER(PD_EXT_BATTERY_CAP, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1)));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_hdr));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_vid));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_pid));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_des));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_ful));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_type));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* Send get battery status. */
-	simulate_get_bat_status(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-		PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_status_bsdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-#endif
-	/* We're in SNK_READY. Send goto_min */
-	simulate_goto_min(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	TEST_ASSERT(give_back_called);
-#else
-	TEST_ASSERT(!give_back_called);
-#endif
-	/* We're done */
-	unplug(port);
-
-	return EC_SUCCESS;
-}
-
-static int test_request_with_wait(void)
-{
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
-#else
-	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
-#endif
-	uint8_t port = PORT0;
-
-	plug_in_source(port, 0);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(2 * PD_T_CC_DEBOUNCE + 100 * MSEC);
-	TEST_ASSERT(pd_port[port].polarity == 0);
-
-	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request is good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(0));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send wait */
-	simulate_wait(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* We didn't have an explicit contract. So we're in SNK_DISCOVERY. */
-	/* Resend Source Cap. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're done */
-	unplug(port);
-	return EC_SUCCESS;
-}
-
-static int test_request_with_wait_no_src_cap(void)
-{
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
-#else
-	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
-#endif
-	uint8_t port = PORT0;
-
-	plug_in_source(port, 0);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(2 * PD_T_CC_DEBOUNCE + 100 * MSEC);
-	TEST_ASSERT(pd_port[port].polarity == 0);
-
-	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request is good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(0));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send wait */
-	simulate_wait(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/*
-	 * Some port partners do not send another SRC_CAP and expect us to send
-	 * another REQUEST 100ms after the WAIT.
-	 */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(100 * MSEC); /* tSinkRequest: 100 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're done */
-	unplug(port);
-	return EC_SUCCESS;
-}
-
-static int test_request_with_reject(void)
-{
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
-#else
-	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
-#endif
-	uint8_t port = PORT0;
-
-	plug_in_source(port, 0);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(2 * PD_T_CC_DEBOUNCE + 100 * MSEC);
-	TEST_ASSERT(pd_port[port].polarity == 0);
-
-	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request is good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(0));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're in SNK_REQUESTED. Send reject */
-	simulate_reject(port);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(0, PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* We're in SNK_READY. Send source cap. again. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	/* We're done */
-	unplug(port);
-	return EC_SUCCESS;
-}
-
-static int test_request(void)
-{
-#ifdef CONFIG_USB_PD_GIVE_BACK
-	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
-#else
-	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
-#endif
-	uint8_t port = PORT0;
-
-	plug_in_source(port, 0);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(2 * PD_T_CC_DEBOUNCE + 100 * MSEC);
-	TEST_ASSERT(pd_port[port].polarity == 0);
-
-	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
-	simulate_source_cap(port, 0);
-	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	/* Wait for the power request */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(35 * MSEC); /* tSenderResponse: 24~30 ms */
-	inc_rx_id(port);
-
-	/* Process the request */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Request was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're done */
-	unplug(port);
-
-	return EC_SUCCESS;
-}
-
-static int test_sink(void)
-{
-	int i;
-	uint8_t port = PORT1;
-
-	plug_in_sink(port, 1);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(250 * MSEC); /* tTypeCSinkWaitCap: 210~250 ms */
-	TEST_ASSERT(pd_port[port].polarity == 1);
-
-	/* The source cap should be sent */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE,
-				  PD_ROLE_DFP, pd_port[port].msg_tx_id,
-				  pd_src_pdo_cnt, pd_port[port].rev, 0)));
-
-	for (i = 0; i < pd_src_pdo_cnt; ++i)
-		TEST_ASSERT(pd_test_tx_msg_verify_word(port, pd_src_pdo[i]));
-
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	/* Wake from pd_start_tx */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	usleep(30 * MSEC);
-
-	/* Looks good. Ack the source cap. */
-	simulate_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_tx_id);
-
-	/* Wake from pd_rx_start */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	usleep(30 * MSEC);
-	inc_tx_id(port);
-
-	/* We're done */
-	unplug(port);
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-	init_ports();
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_ON);
-	pd_set_dual_role(PORT1, PD_DRP_TOGGLE_ON);
-
-	RUN_TEST(test_request);
-	RUN_TEST(test_sink);
-	RUN_TEST(test_request_with_wait);
-	RUN_TEST(test_request_with_wait_no_src_cap);
-	RUN_TEST(test_request_with_wait_and_contract);
-	RUN_TEST(test_request_with_reject);
-
-	test_print_result();
-}
diff --git a/test/usb_pd.tasklist b/test/usb_pd.tasklist
deleted file mode 100644
index fbd319148e..0000000000
--- a/test/usb_pd.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_pd_console.c b/test/usb_pd_console.c
deleted file mode 100644
index 800eae7b3d..0000000000
--- a/test/usb_pd_console.c
+++ /dev/null
@@ -1,472 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test usb_pd_console
- */
-
-#include "common.h"
-#include "math.h"
-#include "stdio.h"
-#include "stdlib.h"
-#include "string.h"
-#include "usb_pe_sm.h"
-#include "usb_pd.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-#include "test_util.h"
-
-/* Defined in implementation */
-int hex8tou32(char *str, uint32_t *val);
-int command_pd(int argc, char **argv);
-int remote_flashing(int argc, char **argv);
-
-static enum try_src_override_t try_src_override;
-static int test_port;
-static enum pd_dpm_request request;
-static int max_volt;
-static int comm_enable;
-static int dev_info;
-static int vdm_cmd;
-static int vdm_count;
-static int vdm_vid;
-static uint32_t vdm_data[10];
-static enum pd_dual_role_states dr_state;
-
-/* Mock functions */
-void pe_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-					int count)
-{
-	int i;
-
-	test_port = port;
-	vdm_cmd = cmd;
-	vdm_count = count;
-	vdm_vid = vid;
-
-	if (data == NULL)
-		for (i = 0; i < 10; i++)
-			vdm_data[i] = -1;
-	else
-		for (i = 0; i < count; i++)
-			vdm_data[i] = data[i];
-}
-
-void pd_dpm_request(int port, enum pd_dpm_request req)
-{
-	test_port = port;
-	request = req;
-}
-
-unsigned int pd_get_max_voltage(void)
-{
-	return 10000;
-}
-
-void pd_request_source_voltage(int port, int mv)
-{
-	test_port = port;
-	max_volt = mv;
-}
-
-void pd_comm_enable(int port, int enable)
-{
-	test_port = port;
-	comm_enable = enable;
-}
-
-void tc_print_dev_info(int port)
-{
-	test_port = port;
-	dev_info = 1;
-}
-
-void pd_set_dual_role(int port, enum pd_dual_role_states state)
-{
-	test_port = port;
-	dr_state = state;
-}
-
-int pd_comm_is_enabled(int port)
-{
-	test_port = port;
-	return 0;
-}
-
-int pd_get_polarity(int port)
-{
-	test_port = port;
-	return 0;
-}
-
-uint32_t tc_get_flags(int port)
-{
-	test_port = port;
-	return 0;
-}
-
-const char *tc_get_current_state(int port)
-{
-	test_port = port;
-	return 0;
-}
-
-void tc_try_src_override(enum try_src_override_t ov)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) {
-		switch (ov) {
-		case TRY_SRC_OVERRIDE_OFF: /* 0 */
-			try_src_override = TRY_SRC_OVERRIDE_OFF;
-			break;
-		case TRY_SRC_OVERRIDE_ON: /* 1 */
-			try_src_override = TRY_SRC_OVERRIDE_ON;
-			break;
-		default:
-			try_src_override = TRY_SRC_NO_OVERRIDE;
-		}
-	}
-}
-
-enum try_src_override_t tc_get_try_src_override(void)
-{
-	return try_src_override;
-}
-
-static int test_hex8tou32(void)
-{
-	char const *tst_str[] = {"01234567", "89abcdef",
-					"AABBCCDD", "EEFF0011"};
-	uint32_t const tst_int[] = {0x01234567, 0x89abcdef,
-					0xaabbccdd, 0xeeff0011};
-	uint32_t val;
-	int i;
-
-	for (i = 0; i < 4; i++) {
-		hex8tou32(tst_str[i], &val);
-		TEST_ASSERT(val == tst_int[i]);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_arg_count(void)
-{
-	int argc;
-	char const *argv[] = {"pd", "", 0, 0, 0};
-
-	for (argc = 0; argc < 3; argc++)
-		TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_port_num(void)
-{
-	int argc = 3;
-	char const *argv[10] = {"pd", "5", 0, 0, 0};
-
-	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM2);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_try_src(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "trysrc", "2", 0, 0};
-
-	try_src_override = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(try_src_override == TRY_SRC_NO_OVERRIDE);
-
-	argv[2] = "1";
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(try_src_override == TRY_SRC_OVERRIDE_ON);
-
-	argv[2] = "0";
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(try_src_override == TRY_SRC_OVERRIDE_OFF);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_tx(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "0", "tx", 0, 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_SNK_STARTUP);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_charger(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "1", "charger", 0, 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 1);
-	TEST_ASSERT(request == DPM_REQUEST_SRC_STARTUP);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dev1(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dev", "20", 0};
-
-	request = 0;
-	max_volt = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_NEW_POWER_LEVEL);
-	TEST_ASSERT(max_volt == 20000);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dev2(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "1", "dev", 0, 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 1);
-	TEST_ASSERT(request == DPM_REQUEST_NEW_POWER_LEVEL);
-	TEST_ASSERT(max_volt == 10000);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_disable(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "0", "disable", 0, 0};
-
-	comm_enable = 1;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(comm_enable == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_enable(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "1", "enable", 0, 0};
-
-	comm_enable = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 1);
-	TEST_ASSERT(comm_enable == 1);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_hard(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "0", "hard", 0, 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_HARD_RESET_SEND);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_soft(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "0", "soft", 0, 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_SOFT_RESET_SEND);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_swap1(void)
-{
-	int argc = 3;
-	char const *argv[] = {"pd", "0", "swap", 0, 0};
-
-	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_swap2(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "power", 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_PR_SWAP);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_swap3(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "1", "swap", "data", 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 1);
-	TEST_ASSERT(request == DPM_REQUEST_DR_SWAP);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_swap4(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "vconn", 0};
-
-	request = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(request == DPM_REQUEST_VCONN_SWAP);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_swap5(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "swap", "xyz", 0};
-
-	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM3);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dualrole1(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "on", 0};
-
-	dr_state = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(dr_state == PD_DRP_TOGGLE_ON);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dualrole2(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "off", 0};
-
-	dr_state = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(dr_state == PD_DRP_TOGGLE_OFF);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dualrole3(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "freeze", 0};
-
-	dr_state = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(dr_state == PD_DRP_FREEZE);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dualrole4(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "sink", 0};
-
-	dr_state = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(dr_state == PD_DRP_FORCE_SINK);
-
-	return EC_SUCCESS;
-}
-
-static int test_command_pd_dualrole5(void)
-{
-	int argc = 4;
-	char const *argv[] = {"pd", "0", "dualrole", "source", 0};
-
-	dr_state = 0;
-	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
-	TEST_ASSERT(test_port == 0);
-	TEST_ASSERT(dr_state == PD_DRP_FORCE_SOURCE);
-
-	return EC_SUCCESS;
-}
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_hex8tou32);
-	RUN_TEST(test_command_pd_arg_count);
-	RUN_TEST(test_command_pd_port_num);
-	RUN_TEST(test_command_pd_try_src);
-	RUN_TEST(test_command_pd_tx);
-	RUN_TEST(test_command_pd_bist_tx);
-	RUN_TEST(test_command_pd_bist_rx);
-	RUN_TEST(test_command_pd_charger);
-	RUN_TEST(test_command_pd_dev1);
-	RUN_TEST(test_command_pd_dev2);
-	RUN_TEST(test_command_pd_disable);
-	RUN_TEST(test_command_pd_enable);
-	RUN_TEST(test_command_pd_hard);
-	RUN_TEST(test_command_pd_info);
-	RUN_TEST(test_command_pd_soft);
-	RUN_TEST(test_command_pd_swap1);
-	RUN_TEST(test_command_pd_swap2);
-	RUN_TEST(test_command_pd_swap3);
-	RUN_TEST(test_command_pd_swap4);
-	RUN_TEST(test_command_pd_swap5);
-	RUN_TEST(test_command_pd_ping);
-	RUN_TEST(test_command_pd_vdm1);
-	RUN_TEST(test_command_pd_vdm2);
-	RUN_TEST(test_command_pd_vdm3);
-	RUN_TEST(test_command_pd_vdm4);
-	RUN_TEST(test_command_pd_vdm5);
-	RUN_TEST(test_command_pd_vdm6);
-	RUN_TEST(test_command_pd_flash1);
-	RUN_TEST(test_command_pd_flash2);
-	RUN_TEST(test_command_pd_flash3);
-	RUN_TEST(test_command_pd_flash4);
-	RUN_TEST(test_command_pd_flash5);
-	RUN_TEST(test_command_pd_flash6);
-	RUN_TEST(test_command_pd_flash7);
-	RUN_TEST(test_command_pd_flash8);
-	RUN_TEST(test_command_pd_dualrole1);
-	RUN_TEST(test_command_pd_dualrole2);
-	RUN_TEST(test_command_pd_dualrole3);
-	RUN_TEST(test_command_pd_dualrole4);
-	RUN_TEST(test_command_pd_dualrole5);
-
-	test_print_result();
-}
-
diff --git a/test/usb_pd_giveback.tasklist b/test/usb_pd_giveback.tasklist
deleted file mode 120000
index 45cc6c8aa2..0000000000
--- a/test/usb_pd_giveback.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_pd.tasklist
\ No newline at end of file
diff --git a/test/usb_pd_int.c b/test/usb_pd_int.c
deleted file mode 100644
index 5d3cbbf0f2..0000000000
--- a/test/usb_pd_int.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB-PD interrupt task.
- */
-#include "task.h"
-#include "test_util.h"
-#include "mock/tcpc_mock.h"
-#include "mock/timer_mock.h"
-#include "mock/usb_mux_mock.h"
-
-#define PORT0 0
-
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-void board_reset_pd_mcu(void)
-{
-}
-
-static int deferred_resume_called;
-void pd_deferred_resume(int port)
-{
-		deferred_resume_called = 1;
-}
-
-static int num_events;
-uint16_t tcpc_get_alert_status(void)
-{
-		if (--num_events > 0)
-			return PD_STATUS_TCPC_ALERT_0;
-		else
-			return 0;
-}
-
-test_static int test_storm_not_triggered(void)
-{
-		num_events = 100;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 0, "%d");
-
-		return EC_SUCCESS;
-}
-
-test_static int test_storm_triggered(void)
-{
-		num_events = 1000;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 1, "%d");
-
-		return EC_SUCCESS;
-}
-
-test_static int test_storm_not_triggered_for_32bit_overflow(void)
-{
-		int i;
-		timestamp_t time;
-
-		/*
-		 * Ensure the MSB is 1 for overflow comparison tests.
-		 * But make sure not to move time backwards.
-		 */
-		time.val = (get_time().val + 0x100000000) | 0xff000000;
-		force_time(time);
-
-		/*
-		 * 100 events every second for 10 seconds should never trigger
-		 * a shutdown call.
-		 */
-		for (i = 0; i < 10; ++i) {
-			num_events = 100;
-			deferred_resume_called = 0;
-			schedule_deferred_pd_interrupt(PORT0);
-			task_wait_event(SECOND);
-
-			TEST_EQ(deferred_resume_called, 0, "%d");
-		}
-
-		return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-		pd_set_suspend(PORT0, 0);
-}
-
-void run_test(int argc, char **argv)
-{
-	/* Let tasks settle down */
-	task_wait_event(MINUTE);
-
-	RUN_TEST(test_storm_not_triggered);
-	RUN_TEST(test_storm_triggered);
-	RUN_TEST(test_storm_not_triggered_for_32bit_overflow);
-
-	test_print_result();
-}
diff --git a/test/usb_pd_int.mocklist b/test/usb_pd_int.mocklist
deleted file mode 100644
index 71c2e2cee9..0000000000
--- a/test/usb_pd_int.mocklist
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_MUX)           \
-	MOCK(TCPC)
diff --git a/test/usb_pd_int.tasklist b/test/usb_pd_int.tasklist
deleted file mode 100644
index 3487d55dc7..0000000000
--- a/test/usb_pd_int.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_pd_pdo_fixed.tasklist b/test/usb_pd_pdo_fixed.tasklist
deleted file mode 100644
index 9a1e6b3e08..0000000000
--- a/test/usb_pd_pdo_fixed.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
-
diff --git a/test/usb_pd_pdo_fixed_test.c b/test/usb_pd_pdo_fixed_test.c
deleted file mode 100644
index ad247c3ba2..0000000000
--- a/test/usb_pd_pdo_fixed_test.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB common module.
- */
-#include "test_util.h"
-#include "usb_common.h"
-
-#define PDO_FIXED_FLAGS \
-	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
-
-/* Test that a non-fixed PDO will never be selected by pd_find_pdo_index. */
-test_static int test_pd_find_pdo_index(void)
-{
-	const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_VAR(4750, PD_MAX_VOLTAGE_MV, PD_MAX_CURRENT_MA),
-		PDO_BATT(4750, PD_MAX_VOLTAGE_MV, PD_MAX_POWER_MW),
-		PDO_FIXED(9000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
-	};
-	const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
-	uint32_t pdo;
-
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 5000, &pdo), 0,
-		"%d");
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 9000, &pdo), 3,
-		"%d");
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 10000, &pdo), 3,
-		"%d");
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 12000, &pdo), 4,
-		"%d");
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 15000, &pdo), 4,
-		"%d");
-	TEST_EQ(pd_find_pdo_index(pd_snk_pdo_cnt, pd_snk_pdo, 20000, &pdo), 5,
-		"%d");
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_pd_find_pdo_index);
-
-	test_print_result();
-}
diff --git a/test/usb_pd_rev30.tasklist b/test/usb_pd_rev30.tasklist
deleted file mode 120000
index 45cc6c8aa2..0000000000
--- a/test/usb_pd_rev30.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_pd.tasklist
\ No newline at end of file
diff --git a/test/usb_pd_test_util.h b/test/usb_pd_test_util.h
deleted file mode 100644
index 02fae22b41..0000000000
--- a/test/usb_pd_test_util.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test utilities for USB PD unit test.
- */
-
-#ifndef __TEST_USB_PD_TEST_UTIL_H
-#define __TEST_USB_PD_TEST_UTIL_H
-
-/* Simulate Rx message */
-void pd_test_rx_set_preamble(int port, int has_preamble);
-void pd_test_rx_msg_append_bits(int port, uint32_t bits, int nb);
-void pd_test_rx_msg_append_kcode(int port, uint8_t kcode);
-void pd_test_rx_msg_append_sop(int port);
-void pd_test_rx_msg_append_sop_prime(int port);
-void pd_test_rx_msg_append_eop(int port);
-void pd_test_rx_msg_append_last_edge(int port);
-void pd_test_rx_msg_append_4b(int port, uint8_t val);
-void pd_test_rx_msg_append_short(int port, uint16_t val);
-void pd_test_rx_msg_append_word(int port, uint32_t val);
-void pd_simulate_rx(int port);
-
-/* Verify Tx message */
-int pd_test_tx_msg_verify_kcode(int port, uint8_t kcode);
-int pd_test_tx_msg_verify_sop(int port);
-int pd_test_tx_msg_verify_sop_prime(int port);
-int pd_test_tx_msg_verify_eop(int port);
-int pd_test_tx_msg_verify_4b5b(int port, uint8_t b4);
-int pd_test_tx_msg_verify_short(int port, uint16_t val);
-int pd_test_tx_msg_verify_word(int port, uint32_t val);
-int pd_test_tx_msg_verify_crc(int port);
-
-#endif  /* __TEST_USB_PD_TEST_UTIL_H */
diff --git a/test/usb_pe.h b/test/usb_pe.h
deleted file mode 100644
index a4967d02e5..0000000000
--- a/test/usb_pe.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PE module.
- */
-#ifndef __CROS_TEST_USB_PE_H
-#define __CROS_TEST_USB_PE_H
-
-#include "common.h"
-
-/*
- * Test references to port
- */
-#define PORT0 0
-
-/**
- * usb_pe_drp_sm.c locally defined.  If it changes there, it must
- * be changed here as well.
- */
-
-/*
- * Policy Engine Layer Flags
- */
-
-/* At least one successful PD communication packet received from port partner */
-#define PE_FLAGS_PD_CONNECTION               BIT(0)
-/* Accept message received from port partner */
-#define PE_FLAGS_ACCEPT                      BIT(1)
-/* Power Supply Ready message received from port partner */
-#define PE_FLAGS_PS_READY                    BIT(2)
-/* Protocol Error was determined based on error recovery current state */
-#define PE_FLAGS_PROTOCOL_ERROR              BIT(3)
-/* Set if we are in Modal Operation */
-#define PE_FLAGS_MODAL_OPERATION             BIT(4)
-/* A message we requested to be sent has been transmitted */
-#define PE_FLAGS_TX_COMPLETE                 BIT(5)
-/* A message sent by a port partner has been received */
-#define PE_FLAGS_MSG_RECEIVED                BIT(6)
-/* A hard reset has been requested but has not been sent, not currently used */
-#define PE_FLAGS_HARD_RESET_PENDING          BIT(7)
-/* Port partner sent a Wait message. Wait before we resend our message */
-#define PE_FLAGS_WAIT                        BIT(8)
-/* An explicit contract is in place with our port partner */
-#define PE_FLAGS_EXPLICIT_CONTRACT           BIT(9)
-/* Waiting for Sink Capabailities timed out.  Used for retry error handling */
-#define PE_FLAGS_SNK_WAIT_CAP_TIMEOUT        BIT(10)
-/* Power Supply voltage/current transition timed out */
-#define PE_FLAGS_PS_TRANSITION_TIMEOUT       BIT(11)
-/* Flag to note current Atomic Message Sequence is interruptible */
-#define PE_FLAGS_INTERRUPTIBLE_AMS           BIT(12)
-/* Flag to note Power Supply reset has completed */
-#define PE_FLAGS_PS_RESET_COMPLETE           BIT(13)
-/* VCONN swap operation has completed */
-#define PE_FLAGS_VCONN_SWAP_COMPLETE         BIT(14)
-/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
-#define PE_FLAGS_VDM_SETUP_DONE              BIT(15)
-/* Flag to note Swap Source Start timer should be set at PE_SRC_Startup entry */
-#define PE_FLAGS_RUN_SOURCE_START_TIMER      BIT(16)
-/* Flag to note Port Discovery port partner replied with BUSY */
-#define PE_FLAGS_VDM_REQUEST_BUSY            BIT(17)
-/* Flag to note Port Discovery port partner replied with NAK */
-#define PE_FLAGS_VDM_REQUEST_NAKED           BIT(18)
-/* Flag to note FRS/PRS context in shared state machine path */
-#define PE_FLAGS_FAST_ROLE_SWAP_PATH         BIT(19)
-/* Flag to note if FRS listening is enabled */
-#define PE_FLAGS_FAST_ROLE_SWAP_ENABLED      BIT(20)
-/* Flag to note TCPC passed on FRS signal from port partner */
-#define PE_FLAGS_FAST_ROLE_SWAP_SIGNALED     BIT(21)
-
-/* List of all Policy Engine level states */
-enum usb_pe_state {
-	/* Super States */
-	PE_PRS_FRS_SHARED,
-	PE_VDM_SEND_REQUEST,
-
-	/* Normal States */
-	PE_SRC_STARTUP,
-	PE_SRC_DISCOVERY,
-	PE_SRC_SEND_CAPABILITIES,
-	PE_SRC_NEGOTIATE_CAPABILITY,
-	PE_SRC_TRANSITION_SUPPLY,
-	PE_SRC_READY,
-	PE_SRC_DISABLED,
-	PE_SRC_CAPABILITY_RESPONSE,
-	PE_SRC_HARD_RESET,
-	PE_SRC_HARD_RESET_RECEIVED,
-	PE_SRC_TRANSITION_TO_DEFAULT,
-	PE_SNK_STARTUP,
-	PE_SNK_DISCOVERY,
-	PE_SNK_WAIT_FOR_CAPABILITIES,
-	PE_SNK_EVALUATE_CAPABILITY,
-	PE_SNK_SELECT_CAPABILITY,
-	PE_SNK_READY,
-	PE_SNK_HARD_RESET,
-	PE_SNK_TRANSITION_TO_DEFAULT,
-	PE_SNK_GIVE_SINK_CAP,
-	PE_SNK_GET_SOURCE_CAP,
-	PE_SNK_TRANSITION_SINK,
-	PE_SEND_SOFT_RESET,
-	PE_SOFT_RESET,
-	PE_SEND_NOT_SUPPORTED,
-	PE_SRC_PING,
-	PE_DRS_EVALUATE_SWAP,
-	PE_DRS_CHANGE,
-	PE_DRS_SEND_SWAP,
-	PE_PRS_SRC_SNK_EVALUATE_SWAP,
-	PE_PRS_SRC_SNK_TRANSITION_TO_OFF,
-	PE_PRS_SRC_SNK_ASSERT_RD,
-	PE_PRS_SRC_SNK_WAIT_SOURCE_ON,
-	PE_PRS_SRC_SNK_SEND_SWAP,
-	PE_PRS_SNK_SRC_EVALUATE_SWAP,
-	PE_PRS_SNK_SRC_TRANSITION_TO_OFF,
-	PE_PRS_SNK_SRC_ASSERT_RP,
-	PE_PRS_SNK_SRC_SOURCE_ON,
-	PE_PRS_SNK_SRC_SEND_SWAP,
-	PE_VCS_EVALUATE_SWAP,
-	PE_VCS_SEND_SWAP,
-	PE_VCS_WAIT_FOR_VCONN_SWAP,
-	PE_VCS_TURN_ON_VCONN_SWAP,
-	PE_VCS_TURN_OFF_VCONN_SWAP,
-	PE_VCS_SEND_PS_RDY_SWAP,
-	PE_VCS_CBL_SEND_SOFT_RESET,
-	PE_VDM_IDENTITY_REQUEST_CBL,
-	PE_INIT_PORT_VDM_IDENTITY_REQUEST,
-	PE_INIT_VDM_SVIDS_REQUEST,
-	PE_INIT_VDM_MODES_REQUEST,
-	PE_VDM_REQUEST_DPM,
-	PE_VDM_RESPONSE,
-	PE_HANDLE_CUSTOM_VDM_REQUEST,
-	PE_WAIT_FOR_ERROR_RECOVERY,
-	PE_BIST_TX,
-	PE_DEU_SEND_ENTER_USB,
-	PE_DR_SNK_GET_SINK_CAP,
-	PE_DR_SNK_GIVE_SOURCE_CAP,
-	PE_DR_SRC_GET_SOURCE_CAP,
-
-	/* PD3.0 only states below here*/
-	PE_FRS_SNK_SRC_START_AMS,
-	PE_GIVE_BATTERY_CAP,
-	PE_GIVE_BATTERY_STATUS,
-	PE_SEND_ALERT,
-	PE_SRC_CHUNK_RECEIVED,
-	PE_SNK_CHUNK_RECEIVED,
-};
-
-void set_state_pe(const int port, const enum usb_pe_state new_state);
-enum usb_pe_state get_state_pe(const int port);
-
-void pe_set_flag(int port, int flag);
-void pe_clr_flag(int port, int flag);
-int pe_chk_flag(int port, int flag);
-int pe_get_all_flags(int port);
-void pe_set_all_flags(int port, int flags);
-void pe_clr_dpm_requests(int port);
-
-#endif /* __CROS_TEST_USB_PE_H */
diff --git a/test/usb_pe_drp.c b/test/usb_pe_drp.c
deleted file mode 100644
index 189cb41987..0000000000
--- a/test/usb_pe_drp.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PE module.
- */
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_mux.h"
-#include "usb_pe.h"
-#include "usb_pe_sm.h"
-#include "usb_sm_checks.h"
-#include "mock/charge_manager_mock.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "mock/tcpc_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "mock/usb_pd_dpm_mock.h"
-#include "mock/dp_alt_mode_mock.h"
-#include "mock/usb_prl_mock.h"
-
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-void before_test(void)
-{
-	mock_tc_port_reset();
-	mock_tcpc_reset();
-	mock_usb_mux_reset();
-	mock_dpm_reset();
-	mock_dp_alt_mode_reset();
-	mock_prl_reset();
-	pe_clear_port_data(PORT0);
-
-	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
-	task_wait_event(SECOND);
-}
-
-/*
- * This assumes data messages only contain a single data object (uint32_t data).
- * TODO: Add support for multiple data objects (when a test is added here that
- * needs it).
- */
-test_static void rx_message(enum tcpci_msg_type sop,
-			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    enum pd_power_role prole,
-			    enum pd_data_role drole,
-			    uint32_t data)
-{
-	int type, cnt;
-
-	if (ctrl_msg != 0) {
-		type = ctrl_msg;
-		cnt = 0;
-	} else {
-		type = data_msg;
-		cnt = 1;
-	}
-	rx_emsg[PORT0].header = (PD_HEADER_SOP(sop)
-		| PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0));
-	rx_emsg[PORT0].len = cnt * 4;
-	*(uint32_t *)rx_emsg[PORT0].buf = data;
-	mock_prl_message_received(PORT0);
-}
-
-/*
- * This sequence is used by multiple tests, so pull out into a function to
- * avoid duplication.
- *
- * Send in how many SOP' DiscoverIdentity requests have been processed so far,
- * as this may vary depending on startup sequencing as a source.
- */
-test_static int finish_src_discovery(int startup_cable_probes)
-{
-	int i;
-
-	/* Expect GET_SOURCE_CAP, reply NOT_SUPPORTED. */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_GET_SOURCE_CAP, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	task_wait_event(10 * MSEC);
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-
-	/*
-	 * Cable identity discovery is attempted 6 times total. 1 was done
-	 * above, so expect 5 more now.
-	 */
-	for (i = startup_cable_probes; i < 6; i++) {
-		TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME,
-						 0, PD_DATA_VENDOR_DEF,
-						 60 * MSEC),
-			EC_SUCCESS, "%d");
-		mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
-	}
-
-	/* Expect VENDOR_DEF for partner identity, reply NOT_SUPPORTED. */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_VENDOR_DEF, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	task_wait_event(10 * MSEC);
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Verify that, before connection, PE_SRC_Send_Capabilities goes to
- * PE_SRC_Discovery on send error, not PE_Send_Soft_Reset.
- */
-test_static int test_send_caps_error_before_connected(void)
-{
-	/* Enable PE as source, expect SOURCE_CAP. */
-	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_tc_port[PORT0].pd_enable = 1;
-	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * Simulate error sending SOURCE_CAP, to test that before connection,
-	 * PE_SRC_Send_Capabilities goes to PE_SRC_Discovery on send error (and
-	 * does not send soft reset).
-	 */
-	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP);
-
-	/*
-	 * We should have gone to PE_SRC_Discovery on above error, so expect
-	 * VENDOR_DEF for cable identity, simulate no cable.
-	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME,
-					 0, PD_DATA_VENDOR_DEF, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
-
-	/*
-	 * Expect SOURCE_CAP again. This is a retry since the first one above
-	 * got ERR_TCH_XMIT. Now simulate success (ie GoodCRC).
-	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 110 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * From here, the sequence is very similar between
-	 * test_send_caps_error_before_connected and
-	 * test_send_caps_error_when_connected. We could end the test now, but
-	 * keep going just to check that the slightly different ordering of
-	 * cable identity discovery doesn't cause any issue below.
-	 */
-
-	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-
-	TEST_EQ(finish_src_discovery(1), EC_SUCCESS, "%d");
-
-	task_wait_event(5 * SECOND);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Verify that, after connection, PE_SRC_Send_Capabilities goes to
- * PE_Send_Soft_Reset on send error, not PE_SRC_Discovery.
- */
-test_static int test_send_caps_error_when_connected(void)
-{
-	/* Enable PE as source, expect SOURCE_CAP. */
-	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_tc_port[PORT0].pd_enable = 1;
-	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	task_wait_event(10 * MSEC);
-
-	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-
-	TEST_EQ(finish_src_discovery(0), EC_SUCCESS, "%d");
-
-	task_wait_event(5 * SECOND);
-
-	/*
-	 * Now connected. Send GET_SOURCE_CAP, to check how error sending
-	 * SOURCE_CAP is handled.
-	 */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
-		EC_SUCCESS, "%d");
-
-	/* Simulate error sending SOURCE_CAP. */
-	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP);
-
-	/*
-	 * Expect SOFT_RESET.
-	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State and section
-	 * 8.3.3.2.3 PE_SRC_Send_Capabilities State.
-	 * "The PE_SRC_Send_Soft_Reset state Shall be entered from any state
-	 * when ... A Message has not been sent after retries to the Sink"
-	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_SOFT_RESET, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-
-	task_wait_event(5 * SECOND);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Verify that when PR swap is interrupted during power transitiong, hard
- * reset is sent
- */
-test_static int test_interrupting_pr_swap(void)
-{
-	/* Enable PE as source, expect SOURCE_CAP. */
-	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_tc_port[PORT0].pd_enable = 1;
-	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	task_wait_event(10 * MSEC);
-
-	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-
-	TEST_EQ(finish_src_discovery(0), EC_SUCCESS, "%d");
-
-	task_wait_event(5 * SECOND);
-
-	/*
-	 * Now connected.  Initiate a PR swap and then interrupt it after the
-	 * Accept, when power is transitioning to off.
-	 */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_prl_message_sent(PORT0);
-
-	task_wait_event(5 * SECOND);
-
-	/* Interrupt the non-interruptible AMS */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-
-	/*
-	 * Expect a hard reset since power was transitioning during this
-	 * interruption
-	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET,
-					 0, 0, 10 * MSEC),
-		EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_send_caps_error_before_connected);
-	RUN_TEST(test_send_caps_error_when_connected);
-	RUN_TEST(test_interrupting_pr_swap);
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_pe_no_parent_cycles);
-
-	test_print_result();
-}
diff --git a/test/usb_pe_drp.mocklist b/test/usb_pe_drp.mocklist
deleted file mode 100644
index b8879415d8..0000000000
--- a/test/usb_pe_drp.mocklist
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(CHARGE_MANAGER) \
-	MOCK(USB_TC_SM) \
-	MOCK(TCPC) \
-	MOCK(USB_MUX) \
-	MOCK(USB_PD_DPM) \
-	MOCK(DP_ALT_MODE) \
-	MOCK(USB_PRL)
diff --git a/test/usb_pe_drp.tasklist b/test/usb_pe_drp.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_pe_drp.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_pe_drp_noextended.c b/test/usb_pe_drp_noextended.c
deleted file mode 100644
index 68da7426e2..0000000000
--- a/test/usb_pe_drp_noextended.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PE module.
- */
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_mux.h"
-#include "usb_pe.h"
-#include "usb_pe_sm.h"
-#include "usb_sm_checks.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "mock/tcpc_mock.h"
-#include "mock/usb_mux_mock.h"
-
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-void before_test(void)
-{
-	mock_tc_port_reset();
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_pe_no_parent_cycles);
-
-	test_print_result();
-}
diff --git a/test/usb_pe_drp_noextended.mocklist b/test/usb_pe_drp_noextended.mocklist
deleted file mode 120000
index c481115571..0000000000
--- a/test/usb_pe_drp_noextended.mocklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_pe_drp.mocklist
\ No newline at end of file
diff --git a/test/usb_pe_drp_noextended.tasklist b/test/usb_pe_drp_noextended.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_pe_drp_noextended.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_pe_drp_old.c b/test/usb_pe_drp_old.c
deleted file mode 100644
index e545667432..0000000000
--- a/test/usb_pe_drp_old.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PE module.
- */
-#include "battery.h"
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pe.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm_checks.h"
-#include "usb_tc_sm.h"
-#include "mock/usb_prl_mock.h"
-
-/**
- * STUB Section
- */
-const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static bool prl_is_busy_flag;
-
-bool prl_is_busy(int port)
-{
-	return prl_is_busy_flag;
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return 0;
-}
-void tc_request_power_swap(int port)
-{
-	/* Do nothing */
-}
-
-void pd_set_vbus_discharge(int port, int enable)
-{
-	gpio_set_level(GPIO_USB_C0_DISCHARGE, enable);
-}
-
-test_static uint8_t tc_enabled = 1;
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return tc_enabled;
-}
-
-void pd_comm_enable(int port, int enable)
-{
-	tc_enabled = !!enable;
-}
-
-bool pd_alt_mode_capable(int port)
-{
-	return 1;
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-
-}
-
-void pd_set_error_recovery(int port)
-{
-
-}
-
-test_static void setup_source(void)
-{
-	/* Start PE. */
-	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	/* As long as we're hacking our way to ready, clear any DPM requests */
-	pe_clr_dpm_requests(PORT0);
-	set_state_pe(PORT0, PE_SRC_READY);
-	task_wait_event(10 * MSEC);
-	/* At this point, the PE should be running in PE_SRC_Ready. */
-}
-
-test_static void setup_sink(void)
-{
-	tc_set_power_role(PORT0, PD_ROLE_SINK);
-	pd_comm_enable(PORT0, 0);
-	task_wait_event(10 * MSEC);
-	pd_comm_enable(PORT0, 1);
-	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	/* As long as we're hacking our way to ready, clear any DPM requests */
-	pe_clr_dpm_requests(PORT0);
-	set_state_pe(PORT0, PE_SNK_READY);
-	task_wait_event(10 * MSEC);
-	/* At this point, the PE should be running in PE_SNK_Ready. */
-}
-/**
- * Test section
- */
-/* PE Fast Role Swap */
-static int test_pe_frs(void)
-{
-	/*
-	 * TODO(b/173791979): This test should validate PE boundary API
-	 * differences -- not internal state changes.
-	 */
-
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(pe_is_running(PORT0));
-
-	/*
-	 * FRS will only trigger when we are SNK, with an Explicit
-	 * contract.  So set this state up manually.  Also ensure any
-	 * background tasks (ex. discovery) aren't running.
-	 */
-	tc_prs_src_snk_assert_rd(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	pe_clr_dpm_requests(PORT0);
-	set_state_pe(PORT0, PE_SNK_READY);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_SNK_READY);
-
-	/*
-	 * Trigger the Fast Role Switch from simulated ISR
-	 */
-	pd_got_frs_signal(PORT0);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED));
-
-	/*
-	 * Verify we detected FRS and ready to start swap
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SEND_SWAP);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT));
-
-	/*
-	 * Make sure that we sent FR_Swap
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(mock_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_FR_SWAP);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SEND_SWAP);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-
-	/*
-	 * Accept the partners PS_RDY control message
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_ACCEPT, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	/*
-	 * Send back our PS_RDY
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_PS_RDY, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	TEST_ASSERT(!tc_is_attached_src(PORT0));
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(tc_is_attached_src(PORT0));
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SOURCE_ON);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	/*
-	 * After delay we are ready to send our PS_RDY
-	 */
-	task_wait_event(PD_POWER_SUPPLY_TURN_ON_DELAY);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SOURCE_ON);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	TEST_ASSERT(mock_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_PS_RDY);
-
-	/*
-	 * Fake the Transmit complete and this will bring us to Source Startup
-	 */
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_SRC_STARTUP);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	return EC_SUCCESS;
-}
-
-static int test_snk_give_source_cap(void)
-{
-	setup_sink();
-
-	/*
-	 * Receive a Get_Source_Cap message; respond with Source_Capabilities
-	 * and return to PE_SNK_Ready once sent.
-	 */
-	rx_emsg[PORT0].header =
-		PD_HEADER(PD_CTRL_GET_SOURCE_CAP, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	task_wait_event(10 * MSEC);
-
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(get_state_pe(PORT0), PE_SNK_READY, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_vbus_gpio_discharge(void)
-{
-	pd_set_vbus_discharge(PORT0, 1);
-	TEST_EQ(gpio_get_level(GPIO_USB_C0_DISCHARGE), 1, "%d");
-
-	pd_set_vbus_discharge(PORT0, 0);
-	TEST_EQ(gpio_get_level(GPIO_USB_C0_DISCHARGE), 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_extended_message_not_supported(void)
-{
-	memset(rx_emsg[PORT0].buf, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
-
-	/*
-	 * Receive an extended, non-chunked message; expect a Not Supported
-	 * response.
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	mock_prl_clear_last_sent_msg(PORT0);
-	task_wait_event(10 * MSEC);
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * Receive an extended, chunked, single-chunk message; expect a Not
-	 * Supported response.
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	mock_prl_clear_last_sent_msg(PORT0);
-	task_wait_event(10 * MSEC);
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * Receive an extended, chunked, multi-chunk message; expect a Not
-	 * Supported response after tChunkingNotSupported (not earlier).
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	mock_prl_clear_last_sent_msg(PORT0);
-	task_wait_event(10 * MSEC);
-	/*
-	 * The PE should stay in PE_SRC_Chunk_Received for
-	 * tChunkingNotSupported.
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_NE(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-
-	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * TODO(b/160374787): Test responding with Not Supported to control
-	 * messages requesting extended messages as responses.
-	 */
-
-	return EC_SUCCESS;
-}
-
-test_static int test_extended_message_not_supported_src(void)
-{
-	setup_source();
-	return test_extended_message_not_supported();
-}
-
-test_static int test_extended_message_not_supported_snk(void)
-{
-	setup_sink();
-	return test_extended_message_not_supported();
-}
-
-test_static int test_prl_is_busy(enum pd_power_role pr)
-{
-	int ready_state;
-
-	if (pr == PD_ROLE_SOURCE)
-		ready_state = PE_SRC_READY;
-	else
-		ready_state = PE_SNK_READY;
-
-	/* Start in ready state with Protocol Layer busy */
-	TEST_ASSERT(get_state_pe(PORT0) == ready_state);
-	prl_is_busy_flag = true;
-
-	/* Make a request to perform a Port Discovery */
-	pd_dpm_request(PORT0, DPM_REQUEST_PORT_DISCOVERY);
-	task_wait_event(10 * MSEC);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * We should still be in ready state because the Protocol
-	 * Layer is busy and can't send our message at this time.
-	 */
-	TEST_ASSERT(get_state_pe(PORT0) == ready_state);
-
-	/* Protocol Layer is not busy now */
-	prl_is_busy_flag = false;
-	task_wait_event(10 * MSEC);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * The Protocol Layer is no longer busy so we can switch to the
-	 * state that will handle sending the Port Discovery messages.
-	 */
-	TEST_ASSERT(get_state_pe(PORT0) != ready_state);
-
-	return EC_SUCCESS;
-}
-
-test_static int test_prl_is_busy_snk(void)
-{
-	setup_sink();
-	return test_prl_is_busy(PD_ROLE_SINK);
-}
-
-test_static int test_prl_is_busy_src(void)
-{
-	setup_source();
-	return test_prl_is_busy(PD_ROLE_SOURCE);
-}
-
-static int test_send_caps_error(void)
-{
-	/*
-	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State and section
-	 * 8.3.3.2.3 PE_SRC_Send_Capabilities State.
-	 *
-	 * Transition to the PE_SRC_Discovery state when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are presently not Connected
-	 */
-	mock_prl_clear_last_sent_msg(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
-	pe_clr_flag(PORT0, PE_FLAGS_PD_CONNECTION);
-	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), 0, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_SRC_DISCOVERY, "%d");
-
-	/*
-	 * Send soft reset when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are already Connected
-	 */
-	mock_prl_clear_last_sent_msg(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
-	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
-	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_pe_frs);
-	RUN_TEST(test_snk_give_source_cap);
-	RUN_TEST(test_vbus_gpio_discharge);
-#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
-	RUN_TEST(test_extended_message_not_supported_src);
-	RUN_TEST(test_extended_message_not_supported_snk);
-#else
-	RUN_TEST(test_prl_is_busy_src);
-	RUN_TEST(test_prl_is_busy_snk);
-#endif
-	RUN_TEST(test_send_caps_error);
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_pe_no_parent_cycles);
-
-	test_print_result();
-}
diff --git a/test/usb_pe_drp_old.mocklist b/test/usb_pe_drp_old.mocklist
deleted file mode 100644
index 0582e5cbb3..0000000000
--- a/test/usb_pe_drp_old.mocklist
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_PRL)
diff --git a/test/usb_pe_drp_old.tasklist b/test/usb_pe_drp_old.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_pe_drp_old.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_pe_drp_old_noextended.c b/test/usb_pe_drp_old_noextended.c
deleted file mode 100644
index cefd77b7d2..0000000000
--- a/test/usb_pe_drp_old_noextended.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PE module.
- */
-#include "battery.h"
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_mux.h"
-#include "usb_pe.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm_checks.h"
-#include "usb_tc_sm.h"
-
-/**
- * STUB Section
- */
-const struct svdm_response svdm_rsp = {
-	.identity = NULL,
-	.svids = NULL,
-	.modes = NULL,
-};
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-int board_vbus_source_enabled(int port)
-{
-	return 0;
-}
-void tc_request_power_swap(int port)
-{
-	/* Do nothing */
-}
-
-void pd_set_vbus_discharge(int port, int enable)
-{
-	gpio_set_level(GPIO_USB_C0_DISCHARGE, enable);
-}
-
-test_static uint8_t tc_enabled = 1;
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return tc_enabled;
-}
-
-void pd_comm_enable(int port, int enable)
-{
-	tc_enabled = !!enable;
-}
-
-bool pd_alt_mode_capable(int port)
-{
-	return 1;
-}
-
-void pd_set_suspend(int port, int suspend)
-{
-
-}
-
-void pd_set_error_recovery(int port)
-{
-
-}
-
-test_static void setup_source(void)
-{
-	/* Start PE. */
-	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	set_state_pe(PORT0, PE_SRC_READY);
-	task_wait_event(10 * MSEC);
-	/* At this point, the PE should be running in PE_SRC_Ready. */
-}
-
-test_static void setup_sink(void)
-{
-	tc_set_power_role(PORT0, PD_ROLE_SINK);
-	pd_comm_enable(PORT0, 0);
-	task_wait_event(10 * MSEC);
-	pd_comm_enable(PORT0, 1);
-	task_wait_event(10 * MSEC);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	set_state_pe(PORT0, PE_SNK_READY);
-	task_wait_event(10 * MSEC);
-	/* At this point, the PE should be running in PE_SNK_Ready. */
-}
-/**
- * Test section
- */
-/* PE Fast Role Swap */
-static int test_pe_frs(void)
-{
-	/*
-	 * TODO: This test should validate PE boundary API differences -- not
-	 * internal state changes.
-	 */
-
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(pe_is_running(PORT0));
-
-	/*
-	 * FRS will only trigger when we are SNK, with an Explicit
-	 * contract.  So set this state up manually.  Also ensure any
-	 * background tasks (ex. discovery) aren't running.
-	 */
-	tc_prs_src_snk_assert_rd(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_VDM_SETUP_DONE);
-	pe_set_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT);
-	set_state_pe(PORT0, PE_SNK_READY);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_SNK_READY);
-
-	/*
-	 * Trigger the Fast Role Switch from simulated ISR
-	 */
-	pd_got_frs_signal(PORT0);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED));
-
-	/*
-	 * Verify we detected FRS and ready to start swap
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SEND_SWAP);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_EXPLICIT_CONTRACT));
-
-	/*
-	 * Make sure that we sent FR_Swap
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(fake_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_FR_SWAP);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SEND_SWAP);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	/*
-	 * Accept the partners PS_RDY control message
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_ACCEPT, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	/*
-	 * Send back our PS_RDY
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(PD_CTRL_PS_RDY, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	TEST_ASSERT(!tc_is_attached_src(PORT0));
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(tc_is_attached_src(PORT0));
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SOURCE_ON);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	/*
-	 * After delay we are ready to send our PS_RDY
-	 */
-	task_wait_event(PD_POWER_SUPPLY_TURN_ON_DELAY);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_PRS_SNK_SRC_SOURCE_ON);
-	TEST_ASSERT(pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-	TEST_ASSERT(fake_prl_get_last_sent_ctrl_msg(PORT0) == PD_CTRL_PS_RDY);
-
-	/*
-	 * Fake the Transmit complete and this will bring us to Source Startup
-	 */
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_ASSERT(get_state_pe(PORT0) == PE_SRC_STARTUP);
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_FAST_ROLE_SWAP_PATH));
-
-	return EC_SUCCESS;
-}
-
-static int test_snk_give_source_cap(void)
-{
-	setup_sink();
-
-	/*
-	 * Receive a Get_Source_Cap message; respond with Source_Capabilities
-	 * and return to PE_SNK_Ready once sent.
-	 */
-	rx_emsg[PORT0].header =
-		PD_HEADER(PD_CTRL_GET_SOURCE_CAP, 0, 0, 0, 0, 0, 0);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	task_wait_event(10 * MSEC);
-
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
-	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(get_state_pe(PORT0), PE_SNK_READY, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_vbus_gpio_discharge(void)
-{
-	pd_set_vbus_discharge(PORT0, 1);
-	TEST_EQ(gpio_get_level(GPIO_USB_C0_DISCHARGE), 1, "%d");
-
-	pd_set_vbus_discharge(PORT0, 0);
-	TEST_EQ(gpio_get_level(GPIO_USB_C0_DISCHARGE), 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_extended_message_not_supported(void)
-{
-	memset(rx_emsg[PORT0].buf, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
-
-	/*
-	 * Receive an extended, non-chunked message; expect a Not Supported
-	 * response.
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
-	task_wait_event(10 * MSEC);
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * Receive an extended, chunked, single-chunk message; expect a Not
-	 * Supported response.
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
-	task_wait_event(10 * MSEC);
-
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * Receive an extended, chunked, multi-chunk message; expect a Not
-	 * Supported response after tChunkingNotSupported (not earlier).
-	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
-	*(uint16_t *)rx_emsg[PORT0].buf =
-		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
-	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
-	task_wait_event(10 * MSEC);
-	/*
-	 * The PE should stay in PE_SRC_Chunk_Received for
-	 * tChunkingNotSupported.
-	 */
-	task_wait_event(10 * MSEC);
-	TEST_NE(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-
-	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
-	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
-	/* At this point, the PE should again be running in PE_SRC_Ready. */
-
-	/*
-	 * TODO(b/160374787): Test responding with Not Supported to control
-	 * messages requesting extended messages as responses.
-	 */
-
-	return EC_SUCCESS;
-}
-
-test_static int test_extended_message_not_supported_src(void)
-{
-	setup_source();
-	return test_extended_message_not_supported();
-}
-
-test_static int test_extended_message_not_supported_snk(void)
-{
-	setup_sink();
-	return test_extended_message_not_supported();
-}
-
-static int test_send_caps_error(void)
-{
-	/*
-	 * See section 8.3.3.4.1.1 PE_SRC_Send_Soft_Reset State and section
-	 * 8.3.3.2.3 PE_SRC_Send_Capabilities State.
-	 *
-	 * Transition to the PE_SRC_Discovery state when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are presently not Connected
-	 */
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
-	pe_clr_flag(PORT0, PE_FLAGS_PD_CONNECTION);
-	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), 0, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_SRC_DISCOVERY, "%d");
-
-	/*
-	 * Send soft reset when:
-	 *  1) The Protocol Layer indicates that the Message has not been sent
-	 *     and we are already Connected
-	 */
-	fake_prl_clear_last_sent_ctrl_msg(PORT0);
-	pe_set_flag(PORT0, PE_FLAGS_PROTOCOL_ERROR);
-	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
-	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
-	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
-	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_pe_frs);
-	RUN_TEST(test_snk_give_source_cap);
-	RUN_TEST(test_vbus_gpio_discharge);
-#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
-	RUN_TEST(test_extended_message_not_supported_src);
-	RUN_TEST(test_extended_message_not_supported_snk);
-#endif
-	RUN_TEST(test_send_caps_error);
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_pe_no_parent_cycles);
-	RUN_TEST(test_pe_no_empty_state);
-
-	test_print_result();
-}
diff --git a/test/usb_pe_drp_old_noextended.mocklist b/test/usb_pe_drp_old_noextended.mocklist
deleted file mode 100644
index 0582e5cbb3..0000000000
--- a/test/usb_pe_drp_old_noextended.mocklist
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_PRL)
diff --git a/test/usb_pe_drp_old_noextended.tasklist b/test/usb_pe_drp_old_noextended.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_pe_drp_old_noextended.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_ppc.c b/test/usb_ppc.c
deleted file mode 100644
index 0cf6f69bf3..0000000000
--- a/test/usb_ppc.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB PD module.
- */
-#include "common.h"
-#include "console.h"
-#include "crc.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-const struct ppc_drv null_drv = {
-	.init = NULL,
-	.is_sourcing_vbus = NULL,
-	.vbus_sink_enable = NULL,
-	.vbus_source_enable = NULL,
-	.set_polarity = NULL,
-	.set_vbus_source_current_limit = NULL,
-	.discharge_vbus = NULL,
-	.set_sbu = NULL,
-	.set_vconn = NULL,
-	.is_vbus_present = NULL,
-	.enter_low_power_mode = NULL,
-};
-
-struct ppc_config_t ppc_chips[] = {
-	[0] = {
-		.drv = &null_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct tcpc_config_t tcpc_config[] = {
-	[0] = {
-	},
-};
-
-static int test_ppc_init(void)
-{
-	int rv;
-
-	rv = ppc_init(1);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_init(0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_is_sourcing_vbus(void)
-{
-	int rv;
-
-	rv = ppc_is_sourcing_vbus(1);
-	TEST_ASSERT(rv == 0);
-	rv = ppc_is_sourcing_vbus(0);
-	TEST_ASSERT(rv == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_set_polarity(void)
-{
-	int rv;
-
-	rv = ppc_set_polarity(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_set_polarity(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_set_vbus_source_current_limit(void)
-{
-	int rv;
-
-	rv = ppc_set_vbus_source_current_limit(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_set_vbus_source_current_limit(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_set_sbu(void)
-{
-	int rv;
-
-	rv = ppc_set_sbu(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_set_sbu(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_set_vconn(void)
-{
-	int rv;
-
-	rv = ppc_set_vconn(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_set_vconn(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_discharge_vbus(void)
-{
-	int rv;
-
-	rv = ppc_discharge_vbus(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_discharge_vbus(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_vbus_sink_enable(void)
-{
-	int rv;
-
-	rv = ppc_vbus_sink_enable(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_vbus_sink_enable(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_enter_low_power_mode(void)
-{
-	int rv;
-
-	rv = ppc_enter_low_power_mode(1);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_enter_low_power_mode(0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_vbus_source_enable(void)
-{
-	int rv;
-
-	rv = ppc_vbus_source_enable(1, 0);
-	TEST_ASSERT(rv == EC_ERROR_INVAL);
-	rv = ppc_vbus_source_enable(0, 0);
-	TEST_ASSERT(rv == EC_ERROR_UNIMPLEMENTED);
-
-	return EC_SUCCESS;
-}
-
-static int test_ppc_is_vbus_present(void)
-{
-	int rv;
-
-	rv = ppc_is_vbus_present(1);
-	TEST_ASSERT(rv == 0);
-	rv = ppc_is_vbus_present(0);
-	TEST_ASSERT(rv == 0);
-
-	return EC_SUCCESS;
-}
-
-
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_ppc_init);
-	RUN_TEST(test_ppc_is_sourcing_vbus);
-	RUN_TEST(test_ppc_set_polarity);
-	RUN_TEST(test_ppc_set_vbus_source_current_limit);
-	RUN_TEST(test_ppc_set_sbu);
-	RUN_TEST(test_ppc_set_vconn);
-	RUN_TEST(test_ppc_discharge_vbus);
-	RUN_TEST(test_ppc_vbus_sink_enable);
-	RUN_TEST(test_ppc_enter_low_power_mode);
-	RUN_TEST(test_ppc_vbus_source_enable);
-	RUN_TEST(test_ppc_is_vbus_present);
-
-	test_print_result();
-}
diff --git a/test/usb_ppc.tasklist b/test/usb_ppc.tasklist
deleted file mode 100644
index 9fc1a80f4d..0000000000
--- a/test/usb_ppc.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/test/usb_prl.c b/test/usb_prl.c
deleted file mode 100644
index 061bb1ad3c..0000000000
--- a/test/usb_prl.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Protocol Layer module.
- */
-#include "common.h"
-#include "mock/tcpc_mock.h"
-#include "mock/tcpm_mock.h"
-#include "mock/usb_pe_sm_mock.h"
-#include "mock/usb_tc_sm_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_pd.h"
-#include "usb_pd_test_util.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm_checks.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define PORT0 0
-
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
-
-static void enable_prl(int port, int en)
-{
-	tcpm_set_rx_enable(port, en);
-
-	mock_tc_port[port].pd_enable = en;
-
-	task_wait_event(10*MSEC);
-
-	prl_set_rev(port, TCPCI_MSG_SOP, mock_tc_port[port].rev);
-}
-
-static int test_receive_control_msg(void)
-{
-	int port = PORT0;
-	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		pd_get_power_role(port),
-		pd_get_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
-
-	/* Set up the message to be received. */
-	mock_tcpm_rx_msg(port, header, 0, NULL);
-
-	/* Process the message. */
-	task_wait_event(10*MSEC);
-
-	/* Check results. */
-	TEST_NE(mock_pe_port[port].mock_pe_message_received, 0, "%d");
-	TEST_EQ(header, rx_emsg[port].header, "%d");
-	TEST_EQ(rx_emsg[port].len, 0, "%d");
-
-	TEST_LE(mock_pe_port[port].mock_pe_error, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_message_discarded, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_got_hard_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_hard_reset_sent, 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_send_control_msg(void)
-{
-	int port = PORT0;
-
-	/* Set up the message to be sent. */
-	prl_send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
-	task_wait_event(MSEC);
-	/* Simulate the TX complete that the PD_INT handler would signal */
-	pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
-
-	task_wait_event(10*MSEC);
-
-	/* Check results. */
-	TEST_NE(mock_pe_port[port].mock_pe_message_sent, 0, "%d");
-	TEST_LE(mock_pe_port[port].mock_pe_error, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_message_discarded, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_got_hard_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_hard_reset_sent, 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_discard_queued_tx_when_rx_happens(void)
-{
-	int port = PORT0;
-	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		pd_get_power_role(port),
-		pd_get_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
-	uint8_t *buf = tx_emsg[port].buf;
-	uint8_t len = 8;
-	uint8_t i = 0;
-
-	/* Set up the message to be sent. */
-	for (i = 0 ; i < len ; i++)
-		buf[i] = (uint8_t)i;
-
-	tx_emsg[port].len = len;
-	prl_send_data_msg(port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP);
-
-	/* Set up the message to be received. */
-	mock_tcpm_rx_msg(port, header, 0, NULL);
-
-	/* Process the message. */
-	task_wait_event(10*MSEC);
-
-	/* Check results. Source should have discarded its message queued up
-	 * to TX, and should have received the message from the sink.
-	 */
-	TEST_NE(mock_pe_port[port].mock_pe_message_discarded, 0, "%d");
-	TEST_NE(mock_pe_port[port].mock_pe_message_received, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_message_sent, 0, "%d");
-
-	TEST_LE(mock_pe_port[port].mock_pe_error, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_got_hard_reset, 0, "%d");
-	TEST_EQ(mock_pe_port[port].mock_pe_hard_reset_sent, 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-void before_test(void)
-{
-	mock_tc_port_reset();
-	mock_tc_port[PORT0].rev = PD_REV30;
-	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
-	mock_tc_port[PORT0].data_role = PD_ROLE_DFP;
-
-	mock_tcpm_reset();
-	mock_pe_port_reset();
-
-	prl_reset_soft(PORT0);
-	enable_prl(PORT0, 1);
-}
-
-void after_test(void)
-{
-	enable_prl(PORT0, 0);
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_receive_control_msg);
-	RUN_TEST(test_send_control_msg);
-	RUN_TEST(test_discard_queued_tx_when_rx_happens);
-	/* TODO add tests here */
-
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_prl_no_parent_cycles);
-	RUN_TEST(test_prl_all_states_named);
-
-	test_print_result();
-}
diff --git a/test/usb_prl.mocklist b/test/usb_prl.mocklist
deleted file mode 100644
index bf5357334a..0000000000
--- a/test/usb_prl.mocklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(TCPC) \
-	MOCK(TCPM) \
-	MOCK(USB_PE_SM) \
-	MOCK(USB_TC_SM)
diff --git a/test/usb_prl.tasklist b/test/usb_prl.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_prl.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c
deleted file mode 120000
index a47c01a13e..0000000000
--- a/test/usb_prl_noextended.c
+++ /dev/null
@@ -1 +0,0 @@
-usb_prl_old.c
\ No newline at end of file
diff --git a/test/usb_prl_noextended.tasklist b/test/usb_prl_noextended.tasklist
deleted file mode 120000
index 26ff35c76c..0000000000
--- a/test/usb_prl_noextended.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_prl_old.tasklist
\ No newline at end of file
diff --git a/test/usb_prl_old.c b/test/usb_prl_old.c
deleted file mode 100644
index 526015b6c9..0000000000
--- a/test/usb_prl_old.c
+++ /dev/null
@@ -1,1330 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Protocol Layer module.
- */
-#include "common.h"
-#include "crc.h"
-#include "task.h"
-#include "tcpm/tcpm.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_emsg.h"
-#include "usb_pd_test_util.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pe_sm.h"
-#include "usb_prl_sm.h"
-#include "usb_sm_checks.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-
-#define PORT0 0
-
-/*
- * These enum definitions are declared in usb_prl_sm and are private to that
- * file. If those definitions are re-ordered, then we need to update these
- * definitions (should be very rare).
- */
-enum usb_prl_tx_state {
-	PRL_TX_PHY_LAYER_RESET,
-	PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
-	PRL_TX_LAYER_RESET_FOR_TRANSMIT,
-	PRL_TX_WAIT_FOR_PHY_RESPONSE,
-	PRL_TX_SRC_SOURCE_TX,
-	PRL_TX_SNK_START_AMS,
-	PRL_TX_SRC_PENDING,
-	PRL_TX_SNK_PENDING,
-	PRL_TX_DISCARD_MESSAGE,
-};
-
-enum usb_prl_hr_state {
-	PRL_HR_WAIT_FOR_REQUEST,
-	PRL_HR_RESET_LAYER,
-	PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
-	PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
-};
-
-enum usb_rch_state {
-	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
-	RCH_PASS_UP_MESSAGE,
-	RCH_PROCESSING_EXTENDED_MESSAGE,
-	RCH_REQUESTING_CHUNK,
-	RCH_WAITING_CHUNK,
-	RCH_REPORT_ERROR,
-};
-
-enum usb_tch_state {
-	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
-	TCH_WAIT_FOR_TRANSMISSION_COMPLETE,
-	TCH_CONSTRUCT_CHUNKED_MESSAGE,
-	TCH_SENDING_CHUNKED_MESSAGE,
-	TCH_WAIT_CHUNK_REQUEST,
-	TCH_MESSAGE_RECEIVED,
-	TCH_MESSAGE_SENT,
-	TCH_REPORT_ERROR,
-};
-
-/* Defined in implementation */
-enum usb_prl_tx_state prl_tx_get_state(const int port);
-enum usb_prl_hr_state prl_hr_get_state(const int port);
-enum usb_rch_state rch_get_state(const int port);
-enum usb_tch_state tch_get_state(const int port);
-
-#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
-enum usb_rch_state rch_get_state(const int port)
-{
-	return RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER;
-}
-#endif
-
-
-static uint32_t test_data[] = {
-	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f,
-	0x10111213, 0x14151617, 0x1819a0b0, 0xc0d0e0f0,
-	0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
-	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f,
-	0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f,
-	0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
-	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f,
-	0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f,
-	0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
-	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f,
-	0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf,
-	0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
-	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf,
-	0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf,
-	0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
-	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff,
-	0x11223344
-};
-
-void pd_set_suspend(int port, int suspend)
-{
-}
-
-void pd_set_error_recovery(int port)
-{
-}
-
-static struct pd_prl {
-	int rev;
-	int pd_enable;
-	enum pd_power_role power_role;
-	enum pd_data_role data_role;
-	int msg_tx_id;
-	int msg_rx_id;
-	enum tcpci_msg_type sop;
-
-	int mock_pe_message_sent;
-	int mock_pe_error;
-	int mock_pe_hard_reset_sent;
-	int mock_pe_got_hard_reset;
-	int mock_pe_message_received;
-	int mock_got_soft_reset;
-	int mock_message_discard;
-} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static void init_port(int port, int rev)
-{
-	pd_port[port].rev = rev;
-	pd_port[port].pd_enable = 0;
-	pd_port[port].power_role = PD_ROLE_SINK;
-	pd_port[port].data_role = PD_ROLE_UFP;
-	pd_port[port].msg_tx_id = 0;
-	pd_port[port].msg_rx_id = 0;
-
-	tcpm_init(port);
-	tcpm_set_polarity(port, 0);
-	tcpm_set_rx_enable(port, 0);
-}
-
-static inline uint32_t pending_pd_task_events(int port)
-{
-	return *task_get_event_bitmap(PD_PORT_TO_TASK_ID(port));
-}
-
-void inc_tx_id(int port)
-{
-	pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) & 7;
-}
-
-void inc_rx_id(int port)
-{
-	pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7;
-}
-
-static int verify_goodcrc(int port, int role, int id)
-{
-	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-				role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
-}
-
-static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
-{
-	int i;
-
-	pd_test_rx_set_preamble(port, 1);
-	pd_test_rx_msg_append_sop(port);
-	pd_test_rx_msg_append_short(port, header);
-
-	crc32_init();
-	crc32_hash16(header);
-
-	for (i = 0; i < cnt; ++i) {
-		pd_test_rx_msg_append_word(port, data[i]);
-		crc32_hash32(data[i]);
-	}
-
-	pd_test_rx_msg_append_word(port, crc32_result());
-
-	pd_test_rx_msg_append_eop(port);
-	pd_test_rx_msg_append_last_edge(port);
-
-	pd_simulate_rx(port);
-}
-
-static void simulate_goodcrc(int port, int role, int id)
-{
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
-}
-
-static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
-{
-	int i;
-
-	for (i = 0; i < num; i++) {
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(time);
-	}
-}
-
-static int simulate_request_chunk(int port, enum pd_data_msg_type msg_type,
-							int chunk_num, int len)
-{
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-					pd_port[port].data_role,
-					pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 1);
-	uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len);
-
-	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
-	task_wait_event(30 * MSEC);
-
-	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
-		return 0;
-
-	return 1;
-}
-
-static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type)
-{
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_rx_id,
-			0, pd_port[port].rev, 0);
-
-	simulate_rx_msg(port, header, 0, NULL);
-	task_wait_event(30 * MSEC);
-
-	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
-		return 0;
-
-	return 1;
-}
-
-static int verify_data_reception(int port, uint16_t header, int len)
-{
-	int i;
-	int cnt = (len + 3) & ~3;
-
-	cycle_through_state_machine(port, 3, 10 * MSEC);
-
-	if (pd_port[port].mock_pe_error >= 0)
-		return 0;
-
-	if (!pd_port[port].mock_pe_message_received)
-		return 0;
-
-	if (rx_emsg[port].header != header)
-		return 0;
-
-	if (rx_emsg[port].len != cnt)
-		return 0;
-
-	for (i = 0; i < cnt; i++) {
-		if (i < len) {
-			if (rx_emsg[port].buf[i] !=
-					*((unsigned char *)test_data + i))
-				return 0;
-		} else {
-			if (rx_emsg[port].buf[i] != 0)
-				return 0;
-		}
-	}
-
-	return 1;
-}
-
-static int verify_chunk_data_reception(int port, uint16_t header, int len)
-{
-	int i;
-	uint8_t *td = (uint8_t *)test_data;
-
-	if (pd_port[port].mock_got_soft_reset) {
-		ccprintf("Got mock soft reset\n");
-		return 0;
-	}
-
-	if (!pd_port[port].mock_pe_message_received) {
-		ccprintf("No mock pe msg received\n");
-		return 0;
-	}
-
-	if (pd_port[port].mock_pe_error >= 0) {
-		ccprintf("Mock pe error (%d)\n", pd_port[port].mock_pe_error);
-		return 0;
-	}
-
-	if (rx_emsg[port].len != len) {
-		ccprintf("emsg len (%d) != 0\n", rx_emsg[port].len);
-		return 0;
-	}
-
-	for (i = 0; i < len; i++) {
-		if (rx_emsg[port].buf[i] != td[i]) {
-			ccprintf("emsg buf[%d] != td\n", i);
-			return 0;
-		}
-	}
-
-	return 1;
-}
-
-static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
-									int len)
-{
-	int i;
-	int nw = (len + 3) >> 2;
-	uint8_t td[28];
-	uint16_t header = PD_HEADER(msg_type, pd_port[port].power_role,
-		pd_port[port].data_role, pd_port[port].msg_rx_id,
-		nw, pd_port[port].rev, 0);
-
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_received = 0;
-	rx_emsg[port].header = 0;
-	rx_emsg[port].len = 0;
-	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
-
-	for (i = 0; i < 28; i++) {
-		if (i < len)
-			td[i] = *((uint8_t *)test_data + i);
-		else
-			td[i] = 0;
-	}
-
-	simulate_rx_msg(port, header, nw, (uint32_t *)td);
-	task_wait_event(30 * MSEC);
-
-	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
-		return 0;
-
-	inc_rx_id(port);
-
-	return verify_data_reception(port, header, len);
-}
-
-static int simulate_receive_extended_data(int port,
-					enum pd_data_msg_type msg_type, int len)
-{
-	int i;
-	int j;
-	int byte_len;
-	int nw;
-	int dsize;
-	uint8_t td[28];
-	int chunk_num = 0;
-	int data_offset = 0;
-	uint8_t *expected_data = (uint8_t *)test_data;
-	uint16_t header;
-
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_received = 0;
-	rx_emsg[port].header = 0;
-	rx_emsg[port].len = 0;
-	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
-
-	dsize = len;
-	for (j = 0; j < 10; j++) {
-		/* Let state machine settle before starting another round */
-		cycle_through_state_machine(port, 10, MSEC);
-
-		byte_len = len;
-		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
-			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-		memset(td, 0, 28);
-		*(uint16_t *)td = PD_EXT_HEADER(chunk_num, 0, dsize);
-
-		for (i = 0; i < byte_len; i++)
-			td[i + 2] = *(expected_data + data_offset++);
-
-		nw = (byte_len + 2 + 3) >> 2;
-		header = PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_rx_id,
-			nw, pd_port[port].rev, 1);
-
-		if (pd_port[port].mock_pe_error >= 0) {
-			ccprintf("Mock pe error (%d) iteration (%d)\n",
-				pd_port[port].mock_pe_error, j);
-			return 0;
-		}
-
-		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-				pd_port[port].mock_pe_message_received) {
-			ccprintf("Mock pe msg received iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (rx_emsg[port].len != 0) {
-			ccprintf("emsg len (%d) != 0 iteration (%d)\n",
-				rx_emsg[port].len, j);
-			return 0;
-		}
-
-		simulate_rx_msg(port, header, nw, (uint32_t *)td);
-		cycle_through_state_machine(port, 1, MSEC);
-
-		if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id)) {
-			ccprintf("Verify goodcrc bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		cycle_through_state_machine(port, 1, MSEC);
-		inc_rx_id(port);
-
-		if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-			if (pd_port[port].mock_pe_message_received)
-				return 1;
-			return 0;
-		}
-
-		/*
-		 * If no more data, do expected to get a chunk request
-		 */
-		if (len <= 0)
-			break;
-
-		/*
-		 * We need to ensure that the TX event has been set, which may
-		 * require an extra cycle through the state machine
-		 */
-		if (!(PD_EVENT_TX & pending_pd_task_events(port)))
-			cycle_through_state_machine(port, 1, MSEC);
-
-		chunk_num++;
-
-		/* Test Request next chunk packet */
-		if (!pd_test_tx_msg_verify_sop(port)) {
-			ccprintf("Verify sop bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type,
-				pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				1, pd_port[port].rev, 1))) {
-			ccprintf("Verify msg short bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_word(port,
-				PD_EXT_HEADER(chunk_num, 1, 0))) {
-			ccprintf("Verify msg word bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_crc(port)) {
-			ccprintf("Verify msg crc bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_eop(port)) {
-			ccprintf("Verify msg eop bad iteration (%d)\n", j);
-			return 0;
-		}
-
-		cycle_through_state_machine(port, 1, MSEC);
-
-		/* Request next chunk packet was good. Send GoodCRC */
-		simulate_goodcrc(port, pd_port[port].power_role,
-					pd_port[port].msg_tx_id);
-
-		cycle_through_state_machine(port, 1, MSEC);
-
-		inc_tx_id(port);
-	}
-
-	cycle_through_state_machine(port, 1, MSEC);
-
-	return verify_chunk_data_reception(port, header, dsize);
-}
-
-static int verify_ctrl_msg_transmission(int port,
-						enum pd_ctrl_msg_type msg_type)
-{
-	if (!pd_test_tx_msg_verify_sop(port))
-		return 0;
-
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id, 0,
-			pd_port[port].rev, 0)))
-		return 0;
-
-	if (!pd_test_tx_msg_verify_crc(port))
-		return 0;
-
-	if (!pd_test_tx_msg_verify_eop(port))
-		return 0;
-
-	return 1;
-}
-
-static int simulate_send_ctrl_msg_request_from_pe(int port,
-	enum tcpci_msg_type type, enum pd_ctrl_msg_type msg_type)
-{
-	pd_port[port].mock_got_soft_reset = 0;
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_sent = 0;
-	prl_send_ctrl_msg(port, type, msg_type);
-	cycle_through_state_machine(port, 1, MSEC);
-
-	return verify_ctrl_msg_transmission(port, msg_type);
-}
-
-static int verify_data_msg_transmission(int port,
-				enum pd_data_msg_type msg_type, int len)
-{
-	int i;
-	int num_words = (len + 3) >> 2;
-	int data_obj_in_bytes;
-	uint32_t td;
-
-	if (!pd_test_tx_msg_verify_sop(port))
-		return 0;
-
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id,
-			num_words, pd_port[port].rev, 0)))
-		return 0;
-
-	for (i = 0; i < num_words; i++) {
-		td = test_data[i];
-		data_obj_in_bytes = (i + 1) * 4;
-		if (data_obj_in_bytes > len) {
-			switch (data_obj_in_bytes - len) {
-			case 1:
-				td &= 0x00ffffff;
-				break;
-			case 2:
-				td &= 0x0000ffff;
-				break;
-			case 3:
-				td &= 0x000000ff;
-				break;
-			}
-		}
-
-		if (!pd_test_tx_msg_verify_word(port, td))
-			return 0;
-	}
-
-	if (!pd_test_tx_msg_verify_crc(port))
-		return 0;
-
-	if (!pd_test_tx_msg_verify_eop(port))
-		return 0;
-
-	return 1;
-}
-
-static int simulate_send_data_msg_request_from_pe(int port,
-	enum tcpci_msg_type type, enum pd_ctrl_msg_type msg_type, int len)
-{
-	int i;
-	uint8_t *buf = tx_emsg[port].buf;
-	uint8_t *td = (uint8_t *)test_data;
-
-	pd_port[port].mock_got_soft_reset = 0;
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_sent = 0;
-
-	for (i = 0; i < len; i++)
-		buf[i] = td[i];
-
-	tx_emsg[port].len = len;
-
-	prl_send_data_msg(port, type, msg_type);
-	cycle_through_state_machine(port, 1, MSEC);
-
-	return verify_data_msg_transmission(port, msg_type, len);
-}
-
-static int verify_extended_data_msg_transmission(int port,
-			enum pd_data_msg_type msg_type, int len)
-{
-	int i;
-	int j;
-	int nw;
-	int byte_len;
-	int dsize;
-	uint32_t td;
-	uint8_t *expected_data = (uint8_t *)&test_data;
-	int data_offset = 0;
-	int chunk_number_to_send = 0;
-
-	dsize = len;
-
-	for (j = 0; j < 10; j++) {
-		byte_len = len;
-		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
-			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-		nw = (byte_len + 2 + 3) >> 2;
-
-		if (!pd_test_tx_msg_verify_sop(port)) {
-			ccprintf("failed tx sop; iteration (%d)\n", j);
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type, pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				nw, pd_port[port].rev, 1))) {
-			ccprintf("failed tx short\n");
-			return 0;
-		}
-		td = PD_EXT_HEADER(chunk_number_to_send, 0, dsize);
-		td |= *(expected_data + data_offset++) << 16;
-		td |= *(expected_data + data_offset++) << 24;
-
-		if (byte_len == 1)
-			td &= 0x00ffffff;
-
-		if (!pd_test_tx_msg_verify_word(port, td)) {
-			ccprintf("failed tx word\n");
-			return 0;
-		}
-
-		byte_len -= 2;
-
-		if (byte_len > 0) {
-			nw = (byte_len + 3) >> 2;
-			for (i = 0; i < nw; i++) {
-				td = *(expected_data + data_offset++) << 0;
-				td |= *(expected_data +	data_offset++) << 8;
-				td |= *(expected_data +	data_offset++) << 16;
-				td |= *(expected_data +	data_offset++) << 24;
-
-				switch (byte_len) {
-				case 3:
-					td &= 0x00ffffff;
-					break;
-				case 2:
-					td &= 0x0000ffff;
-					break;
-				case 1:
-					td &= 0x000000ff;
-					break;
-				}
-
-				if (!pd_test_tx_msg_verify_word(port, td))
-					return 0;
-				byte_len -= 4;
-			}
-		}
-
-		if (!pd_test_tx_msg_verify_crc(port)) {
-			ccprintf("failed tx crc\n");
-			return 0;
-		}
-
-		if (!pd_test_tx_msg_verify_eop(port)) {
-			ccprintf("failed tx eop\n");
-			return 0;
-		}
-
-		cycle_through_state_machine(port, 1, MSEC);
-
-		/* Send GoodCRC */
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
-		cycle_through_state_machine(port, 1, MSEC);
-		inc_tx_id(port);
-
-		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-		if (len <= 0)
-			break;
-
-		chunk_number_to_send++;
-		/* Let state machine settle */
-		cycle_through_state_machine(port, 10, MSEC);
-		if (!simulate_request_chunk(port, msg_type,
-				chunk_number_to_send, dsize)) {
-			ccprintf("failed request chunk\n");
-			return 0;
-		}
-
-		cycle_through_state_machine(port, 1, MSEC);
-		inc_rx_id(port);
-	}
-
-	return 1;
-}
-
-static int simulate_send_extended_data_msg(int port,
-		enum tcpci_msg_type type, enum pd_ctrl_msg_type msg_type,
-		int len)
-{
-	int i;
-	uint8_t *buf = tx_emsg[port].buf;
-	uint8_t *td = (uint8_t *)test_data;
-
-	memset(buf, 0, ARRAY_SIZE(tx_emsg[port].buf));
-	tx_emsg[port].len = len;
-
-	/* don't overflow buffer */
-	if (len > ARRAY_SIZE(tx_emsg[port].buf))
-		len = ARRAY_SIZE(tx_emsg[port].buf);
-
-	for (i = 0; i < len; i++)
-		buf[i] = td[i];
-
-	prl_send_ext_data_msg(port, type, msg_type);
-	cycle_through_state_machine(port, 1, MSEC);
-
-	return verify_extended_data_msg_transmission(port, msg_type,
-							len);
-}
-
-uint8_t tc_get_pd_enabled(int port)
-{
-	return pd_port[port].pd_enable;
-}
-
-static void enable_prl(int port, int en)
-{
-	tcpm_set_rx_enable(port, en);
-
-	pd_port[port].pd_enable = en;
-	pd_port[port].msg_tx_id = 0;
-	pd_port[port].msg_rx_id = 0;
-
-	/* Init PRL */
-	cycle_through_state_machine(port, 10, MSEC);
-
-	prl_set_rev(port, TCPCI_MSG_SOP, pd_port[port].rev);
-}
-
-enum pd_power_role pd_get_power_role(int port)
-{
-	return pd_port[port].power_role;
-}
-
-enum pd_data_role pd_get_data_role(int port)
-{
-	return pd_port[port].data_role;
-}
-
-enum pd_cable_plug tc_get_cable_plug(int port)
-{
-	return PD_PLUG_FROM_DFP_UFP;
-}
-
-void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
-{
-	pd_port[port].mock_pe_error = e;
-	pd_port[port].sop = type;
-}
-
-void pe_report_discard(int port)
-{
-	pd_port[port].mock_message_discard = 1;
-}
-
-void pe_got_hard_reset(int port)
-{
-	pd_port[port].mock_pe_got_hard_reset = 1;
-}
-
-void pe_message_received(int port)
-{
-	pd_port[port].mock_pe_message_received = 1;
-}
-
-void pe_message_sent(int port)
-{
-	pd_port[port].mock_pe_message_sent = 1;
-}
-
-void pe_hard_reset_sent(int port)
-{
-	pd_port[port].mock_pe_hard_reset_sent = 1;
-}
-
-void pe_got_soft_reset(int port)
-{
-	pd_port[port].mock_got_soft_reset = 1;
-}
-
-bool pe_in_frs_mode(int port)
-{
-	return false;
-}
-
-bool pe_in_local_ams(int port)
-{
-	/* We will probably want to change this in the future */
-	return false;
-}
-
-static int test_prl_reset(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	prl_reset_soft(port);
-
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-	TEST_EQ(tch_get_state(port),
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, "%u");
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_REQUEST, "%u");
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_send_ctrl_msg(void)
-{
-	int i;
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Control message transmission and tx_id increment
-	 */
-	for (i = 0; i < 10; i++) {
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(40 * MSEC);
-
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-		TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-				TCPCI_MSG_SOP, PD_CTRL_ACCEPT), 0, "%d");
-
-		cycle_through_state_machine(port, 1, MSEC);
-
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
-		inc_tx_id(port);
-
-		/* Let statemachine settle */
-		cycle_through_state_machine(port, 10, MSEC);
-
-		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
-		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-	}
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_send_data_msg(void)
-{
-	int i;
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Sending data  message with 1 to 28 bytes
-	 */
-	for (i = 1; i <= 28; i++) {
-		cycle_through_state_machine(port, 1, MSEC);
-
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-		TEST_NE(simulate_send_data_msg_request_from_pe(port,
-				TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i), 0, "%d");
-
-		cycle_through_state_machine(port, 1, MSEC);
-
-		simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
-		inc_tx_id(port);
-
-		cycle_through_state_machine(port, 10, MSEC);
-
-		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
-		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-	}
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_send_data_msg_to_much_data(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Send data message with more than 28-bytes, should fail
-	 */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-	/* Try to send 29-bytes */
-	TEST_EQ(simulate_send_data_msg_request_from_pe(port,
-			TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 29), 0, "%d");
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	cycle_through_state_machine(port, 10, MSEC);
-
-	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_EQ(pd_port[port].mock_pe_message_sent, 0, "%d");
-	TEST_EQ(pd_port[port].mock_pe_error, ERR_TCH_XMIT, "%d");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_send_extended_data_msg(void)
-{
-	int i;
-	int port = PORT0;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		ccprints("CONFIG_USB_PD_EXTENDED_MESSAGES disabled; skipping");
-		return EC_SUCCESS;
-	}
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Sending extended data message with 29 to 260 bytes
-	 */
-
-	pd_port[port].mock_got_soft_reset = 0;
-	pd_port[port].mock_pe_error = -1;
-
-	ccprintf("Iteration ");
-	for (i = 29; i <= PD_MAX_EXTENDED_MSG_LEN; i++) {
-		ccprintf(".%d", i);
-		pd_port[port].mock_pe_message_sent = 0;
-
-		cycle_through_state_machine(port, 10, MSEC);
-
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%d");
-
-		TEST_NE(simulate_send_extended_data_msg(port, TCPCI_MSG_SOP,
-					PD_EXT_MANUFACTURER_INFO, i),
-					0, "%d");
-
-		cycle_through_state_machine(port, 10, MSEC);
-
-		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
-		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-	}
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_receive_soft_reset_msg(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Receiving Soft Reset
-	 */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-
-	pd_port[port].mock_got_soft_reset = 0;
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_received = 0;
-
-	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_SOFT_RESET), 0, "%d");
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	cycle_through_state_machine(port, 10, MSEC);
-
-	TEST_EQ(pd_port[port].mock_got_soft_reset, 1, "%d");
-	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-	/*
-	 * We don't want to get  pe_got_soft_reset and pe_message_received, just
-	 * pe_got_soft_reset.
-	 */
-	TEST_EQ(pd_port[port].mock_pe_message_received, 0, "%d");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_receive_control_msg(void)
-{
-	int port = PORT0;
-	int expected_header = PD_HEADER(PD_CTRL_DR_SWAP,
-				pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Receiving a control message
-	 */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-
-	pd_port[port].mock_got_soft_reset = 0;
-	pd_port[port].mock_pe_error = -1;
-	pd_port[port].mock_pe_message_received = 0;
-
-	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_DR_SWAP), 0, "%d");
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	cycle_through_state_machine(port, 3, 10 * MSEC);
-
-	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-	TEST_NE(pd_port[port].mock_pe_message_received, 0, "%d");
-	TEST_EQ(expected_header, rx_emsg[port].header, "%d");
-	TEST_EQ(rx_emsg[port].len, 0, "%d");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_receive_data_msg(void)
-{
-	int port = PORT0;
-	int i;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Receiving data message with 1 to 28 bytes
-	 */
-
-	for (i = 1; i <= 28; i++) {
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(40 * MSEC);
-
-		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, i), 0, "%d");
-	}
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_receive_extended_data_msg(void)
-{
-	int len;
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
-		/*
-		 * TEST: Receiving extended data message with 29 to 260 bytes
-		 */
-
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(40 * MSEC);
-
-		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-
-		for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) {
-			TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, len), 0, "%d");
-		}
-	} else {
-		/*
-		 * TEST: Receiving unsupported extended data message and then
-		 * subsequently receiving a support non-extended data message.
-		 */
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, 29), 0, "%d");
-
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, 28), 0, "%d");
-	}
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_send_soft_reset_msg(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Send soft reset
-	 */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET), 0, "%d");
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	simulate_goodcrc(port, pd_port[port].power_role,
-						pd_port[port].msg_tx_id);
-	inc_tx_id(port);
-
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
-
-	cycle_through_state_machine(port, 3, 10 * MSEC);
-
-	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
-	TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
-	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_pe_execute_hard_reset_msg(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	pd_port[port].mock_pe_hard_reset_sent = 0;
-
-	/*
-	 * TEST: Policy Engine initiated hard reset
-	 */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
-
-	/* Simulate receiving hard reset from policy engine */
-	prl_execute_hard_reset(port);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-	cycle_through_state_machine(port, 1, 10 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, "%u");
-
-	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
-	TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d");
-
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
-
-	/* Simulate policy engine indicating that it is done hard reset */
-	prl_hard_reset_complete(port);
-
-	cycle_through_state_machine(port, 1, 10 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_phy_execute_hard_reset_msg(void)
-{
-	int port = PORT0;
-
-	enable_prl(port, 1);
-
-	/*
-	 * TEST: Port partner initiated hard reset
-	 */
-
-	pd_port[port].mock_pe_got_hard_reset = 0;
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
-
-	/* Simulate receiving hard reset from port partner */
-	pd_execute_hard_reset(port);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-
-	cycle_through_state_machine(port, 1, 10 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
-
-	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
-	TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d");
-
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
-
-	/* Simulate policy engine indicating that it is done hard reset */
-	prl_hard_reset_complete(port);
-
-	cycle_through_state_machine(port, 1, 10 * MSEC);
-
-	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
-
-	enable_prl(port, 0);
-
-	return EC_SUCCESS;
-}
-
-/* Reset the state machine between each test */
-void before_test(void)
-{
-	/* This test relies on explicitly cycling through events manually */
-	tc_pause_event_loop(PORT0);
-
-	pd_port[PORT0].mock_pe_message_sent = 0;
-	pd_port[PORT0].mock_pe_error = -1;
-	pd_port[PORT0].mock_message_discard = 0;
-	pd_port[PORT0].mock_pe_hard_reset_sent = 0;
-	pd_port[PORT0].mock_pe_got_hard_reset = 0;
-	pd_port[PORT0].mock_pe_message_received = 0;
-	pd_port[PORT0].mock_got_soft_reset = 0;
-	pd_port[PORT0].pd_enable = false;
-	cycle_through_state_machine(PORT0, 10, MSEC);
-	pd_port[PORT0].pd_enable = true;
-	cycle_through_state_machine(PORT0, 10, MSEC);
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	/* Test PD 2.0 Protocol */
-	init_port(PORT0, PD_REV20);
-	RUN_TEST(test_prl_reset);
-	RUN_TEST(test_send_ctrl_msg);
-	RUN_TEST(test_send_data_msg);
-	RUN_TEST(test_send_data_msg_to_much_data);
-	RUN_TEST(test_receive_control_msg);
-	RUN_TEST(test_receive_data_msg);
-	RUN_TEST(test_receive_soft_reset_msg);
-	RUN_TEST(test_send_soft_reset_msg);
-	RUN_TEST(test_pe_execute_hard_reset_msg);
-	RUN_TEST(test_phy_execute_hard_reset_msg);
-
-	/* TODO(shurst): More PD 2.0 Tests */
-
-	ccprints("Starting PD 3.0 tests");
-
-	/* Test PD 3.0 Protocol */
-	init_port(PORT0, PD_REV30);
-	RUN_TEST(test_prl_reset);
-	RUN_TEST(test_send_ctrl_msg);
-	RUN_TEST(test_send_data_msg);
-	RUN_TEST(test_send_data_msg_to_much_data);
-	RUN_TEST(test_send_extended_data_msg);
-	RUN_TEST(test_receive_control_msg);
-	RUN_TEST(test_receive_data_msg);
-	RUN_TEST(test_receive_extended_data_msg);
-	RUN_TEST(test_receive_soft_reset_msg);
-	RUN_TEST(test_send_soft_reset_msg);
-	RUN_TEST(test_pe_execute_hard_reset_msg);
-	RUN_TEST(test_phy_execute_hard_reset_msg);
-
-	/* TODO(shurst): More PD 3.0 Tests */
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_prl_no_parent_cycles);
-	RUN_TEST(test_prl_all_states_named);
-
-	test_print_result();
-}
diff --git a/test/usb_prl_old.tasklist b/test/usb_prl_old.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_prl_old.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_sm_checks.c b/test/usb_sm_checks.c
deleted file mode 100644
index 03e5aa23c2..0000000000
--- a/test/usb_sm_checks.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Type-C VPD and CTVPD module.
- */
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-#include "usb_pd_test_util.h"
-#include "vpd_api.h"
-
-#ifdef CONFIG_USB_TYPEC_SM
-extern const struct test_sm_data test_tc_sm_data[];
-extern const int test_tc_sm_data_size;
-#else
-const struct test_sm_data test_tc_sm_data[] = {};
-const int test_tc_sm_data_size;
-#endif
-
-#ifdef CONFIG_USB_PRL_SM
-extern const struct test_sm_data test_prl_sm_data[];
-extern const int test_prl_sm_data_size;
-#else
-const struct test_sm_data test_prl_sm_data[] = {};
-const int test_prl_sm_data_size;
-#endif
-
-#ifdef CONFIG_USB_PE_SM
-extern const struct test_sm_data test_pe_sm_data[];
-extern const int test_pe_sm_data_size;
-#else
-const struct test_sm_data test_pe_sm_data[] = {};
-const int test_pe_sm_data_size;
-#endif
-
-test_static int test_no_parent_cycles(const struct test_sm_data * const sm_data)
-{
-	int i;
-
-	for (i = 0; i < sm_data->size; ++i) {
-		int depth = 0;
-		usb_state_ptr current = &sm_data->base[i];
-
-		while (current != NULL && ++depth <= sm_data->size)
-			current = current->parent;
-
-		if (depth > sm_data->size)
-			break;
-	}
-
-	/* Ensure all states end, otherwise the ith state has a cycle. */
-	TEST_EQ(i, sm_data->size, "%d");
-
-	return EC_SUCCESS;
-}
-
-int test_tc_no_parent_cycles(void)
-{
-	int i;
-
-	for (i = 0; i < test_tc_sm_data_size; ++i) {
-		const int rv = test_no_parent_cycles(&test_tc_sm_data[i]);
-
-		if (rv) {
-			ccprintf("TC State machine %d has a cycle!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int test_prl_no_parent_cycles(void)
-{
-	int i;
-
-	for (i = 0; i < test_prl_sm_data_size; ++i) {
-		const int rv = test_no_parent_cycles(&test_prl_sm_data[i]);
-
-		if (rv) {
-			ccprintf("PRL State machine %d has a cycle!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int test_pe_no_parent_cycles(void)
-{
-	int i;
-
-	for (i = 0; i < test_pe_sm_data_size; ++i) {
-		const int rv = test_no_parent_cycles(&test_pe_sm_data[i]);
-
-		if (rv) {
-			ccprintf("PE State machine %d has a cycle!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-static volatile int state_printed;
-
-/* Override the implement version of print */
-__override void print_current_state(const int port)
-{
-	state_printed = 1;
-}
-
-static int test_all_states_named(const struct test_sm_data * const sm_data)
-{
-	int i;
-
-	for (i = 0; i < sm_data->size; ++i) {
-		usb_state_ptr current = &sm_data->base[i];
-
-		state_printed = 0;
-
-		if (current->entry)
-			current->entry(0);
-
-		if (state_printed) {
-			if (i >= sm_data->names_size ||
-			    sm_data->names[i] == NULL) {
-				ccprintf("State %d does not have a name!\n", i);
-				TEST_ASSERT(0);
-			}
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int test_tc_all_states_named(void)
-{
-	int i;
-
-	for (i = 0; i < test_tc_sm_data_size; ++i) {
-		const int rv = test_all_states_named(&test_tc_sm_data[i]);
-
-		if (rv) {
-			ccprintf("TC State machine %d has empty name!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int test_prl_all_states_named(void)
-{
-	int i;
-
-	for (i = 0; i < test_prl_sm_data_size; ++i) {
-		const int rv = test_all_states_named(&test_prl_sm_data[i]);
-
-		if (rv) {
-			ccprintf("PRL State machine %d has empty name!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-int test_pe_all_states_named(void)
-{
-	int i;
-
-	for (i = 0; i < test_pe_sm_data_size; ++i) {
-		const int rv = test_all_states_named(&test_pe_sm_data[i]);
-
-		if (rv) {
-			ccprintf("PE State machine %d has empty name!\n", i);
-			TEST_ASSERT(0);
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
diff --git a/test/usb_sm_checks.h b/test/usb_sm_checks.h
deleted file mode 100644
index 92529ac385..0000000000
--- a/test/usb_sm_checks.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Validity tests for a state machine definition */
-
-#ifndef __CROS_EC_USB_SM_CHECKS_H
-#define __CROS_EC_USB_SM_CHECKS_H
-
-int test_tc_no_parent_cycles(void);
-int test_tc_all_states_named(void);
-
-
-int test_prl_no_parent_cycles(void);
-int test_prl_all_states_named(void);
-
-
-int test_pe_no_parent_cycles(void);
-int test_pe_all_states_named(void);
-
-#endif /* __CROS_EC_USB_SM_CHECKS_H */
\ No newline at end of file
diff --git a/test/usb_sm_framework_h0.tasklist b/test/usb_sm_framework_h0.tasklist
deleted file mode 120000
index b55922b1ee..0000000000
--- a/test/usb_sm_framework_h0.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_sm_framework_h3.tasklist
\ No newline at end of file
diff --git a/test/usb_sm_framework_h1.tasklist b/test/usb_sm_framework_h1.tasklist
deleted file mode 120000
index b55922b1ee..0000000000
--- a/test/usb_sm_framework_h1.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_sm_framework_h3.tasklist
\ No newline at end of file
diff --git a/test/usb_sm_framework_h2.tasklist b/test/usb_sm_framework_h2.tasklist
deleted file mode 120000
index b55922b1ee..0000000000
--- a/test/usb_sm_framework_h2.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_sm_framework_h3.tasklist
\ No newline at end of file
diff --git a/test/usb_sm_framework_h3.c b/test/usb_sm_framework_h3.c
deleted file mode 100644
index ba544a749a..0000000000
--- a/test/usb_sm_framework_h3.c
+++ /dev/null
@@ -1,1002 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Type-C VPD and CTVPD module.
- */
-#include "common.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-#include "usb_pd_test_util.h"
-#include "vpd_api.h"
-
-/*
- * Test State Hierarchy
- *   SM_TEST_A4 transitions to SM_TEST_B4
- *   SM_TEST_B4 transitions to SM_TEST_B5
- *   SM_TEST_B5 transitions to SM_TEST_B6
- *   SM_TEST_B6 transitions to SM_TEST_C
- *   SM_TEST_C  transitions to SM_TEST_A7
- *   SM_TEST_A7 transitions to SM_TEST_A6
- *   SM_TEST_A6 transitions to SM_TEST_A5
- *   SM_TEST_A5 transitions to SM_TEST_A4
- *
- * ---------------------------     ---------------------------
- * | SM_TEST_SUPER_A1        |     | SM_TEST_SUPER_B1        |
- * | ----------------------- |     | ----------------------- |
- * | | SM_TEST_SUPER_A2    | |     | | SM_TEST_SUPER_B2    | |
- * | | ------------------- | |     | | ------------------- | |
- * | | |SM_TEST_SUPER_A3 | | |     | | |SM_TEST_SUPER_B3 | | |
- * | | |                 | | |     | | |                 | | |
- * | | |  -------------  | | |     | | |  -------------  | | |
- * | | |  | SM_TEST_A4|------------------>| SM_TEST_B4|  | | |
- * | | |  -------------  | | |     | | |  -------------  | | |
- * | | |        ^        | | |     | | |--------|--------| | |
- * | | |        |        | | |     | |          |          | |
- * | | |  -------------- | | |     | |          \/         | |
- * | | |  | SM_TEST_A5 | | | |     | |    --------------   | |
- * | | |  -------------- | | |     | |    | SM_TEST_B5 |   | |
- * | | |--------^--------| | |     | |    --------------   | |
- * | |          |          | |     | |          |          | |
- * | |    --------------   | |     | -----------|----------- |
- * | |    | SM_TEST_A6 |   | |     |            \/           |
- * | |    --------------   | |     |      --------------     |
- * | |----------^----------| |     |      | SM_TEST_B6 |     |
- * |            |            |     |      --------------     |
- * |      --------------     |     |--------/----------------|
- * |      | SM_TEST_A7 |     |             /
- * |      --------------     |            /
- * |------------------^------|           /
- *                     \                /
- *                      \              \/
- *                        -------------
- *                        | SM_TEST_C |
- *                        -------------
- *
- * test_hierarchy_0: Tests a flat state machine without super states
- * test_hierarchy_1: Tests a hierarchical state machine with 1 super state
- * test_hierarchy_2: Tests a hierarchical state machine with 2 super states
- * test_hierarchy_3: Tests a hierarchical state machine with 3 super states
- *
- */
-
-#define SEQUENCE_SIZE 55
-
-enum state_id {
-	ENTER_A1 = 1,
-	RUN_A1,
-	EXIT_A1,
-	ENTER_A2,
-	RUN_A2,
-	EXIT_A2,
-	ENTER_A3,
-	RUN_A3,
-	EXIT_A3,
-	ENTER_A4,
-	RUN_A4,
-	EXIT_A4,
-	ENTER_A5,
-	RUN_A5,
-	EXIT_A5,
-	ENTER_A6,
-	RUN_A6,
-	EXIT_A6,
-	ENTER_A7,
-	RUN_A7,
-	EXIT_A7,
-	ENTER_B1,
-	RUN_B1,
-	EXIT_B1,
-	ENTER_B2,
-	RUN_B2,
-	EXIT_B2,
-	ENTER_B3,
-	RUN_B3,
-	EXIT_B3,
-	ENTER_B4,
-	RUN_B4,
-	EXIT_B4,
-	ENTER_B5,
-	RUN_B5,
-	EXIT_B5,
-	ENTER_B6,
-	RUN_B6,
-	EXIT_B6,
-	ENTER_C,
-	RUN_C,
-	EXIT_C,
-};
-
-#define PORT0   0
-
-struct sm_ {
-	/* struct sm_obj must be first */
-	struct sm_ctx ctx;
-	int sv_tmp;
-	int idx;
-	int seq[SEQUENCE_SIZE];
-} sm[1];
-
-enum state {
-	SM_TEST_SUPER_A1,
-	SM_TEST_SUPER_A2,
-	SM_TEST_SUPER_A3,
-	SM_TEST_SUPER_B1,
-	SM_TEST_SUPER_B2,
-	SM_TEST_SUPER_B3,
-	SM_TEST_A4,
-	SM_TEST_A5,
-	SM_TEST_A6,
-	SM_TEST_A7,
-	SM_TEST_B4,
-	SM_TEST_B5,
-	SM_TEST_B6,
-	SM_TEST_C,
-};
-static const struct usb_state states[];
-
-static struct control {
-	usb_state_ptr a3_entry_to;
-	usb_state_ptr b3_run_to;
-	usb_state_ptr b6_entry_to;
-	usb_state_ptr c_entry_to;
-	usb_state_ptr c_exit_to;
-} test_control;
-
-static void set_state_sm(const int port, const enum state new_state)
-{
-	set_state(port, &sm[port].ctx, &states[new_state]);
-}
-
-static void sm_test_super_A1_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_A1;
-}
-
-static void sm_test_super_A1_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_A1;
-}
-
-static void sm_test_super_A1_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A1;
-}
-
-static void sm_test_super_B1_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_B1;
-}
-
-static void sm_test_super_B1_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_B1;
-}
-
-static void sm_test_super_B1_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B1;
-}
-
-static void sm_test_super_A2_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_A2;
-}
-
-static void sm_test_super_A2_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_A2;
-}
-
-static void sm_test_super_A2_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A2;
-}
-
-
-static void sm_test_super_B2_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_B2;
-}
-
-static void sm_test_super_B2_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_B2;
-}
-
-static void sm_test_super_B2_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B2;
-}
-
-static void sm_test_super_A3_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_A3;
-	if (test_control.a3_entry_to)
-		set_state(port, &sm[port].ctx, test_control.a3_entry_to);
-}
-
-static void sm_test_super_A3_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_A3;
-}
-
-static void sm_test_super_A3_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A3;
-}
-
-static void sm_test_super_B3_entry(const int port)
-{
-	sm[port].seq[sm[port].idx++] = ENTER_B3;
-}
-
-static void sm_test_super_B3_run(const int port)
-{
-	sm[port].seq[sm[port].idx++] = RUN_B3;
-	if (test_control.b3_run_to)
-		set_state(port, &sm[port].ctx, test_control.b3_run_to);
-}
-
-static void sm_test_super_B3_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B3;
-}
-
-static void sm_test_A4_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_A4;
-}
-
-static void sm_test_A4_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_A4;
-	} else {
-		set_state_sm(port, SM_TEST_B4);
-	}
-}
-
-static void sm_test_A4_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A4;
-}
-
-
-static void sm_test_A5_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_A5;
-}
-
-static void sm_test_A5_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_A5;
-	} else {
-		set_state_sm(port, SM_TEST_A4);
-	}
-}
-
-static void sm_test_A5_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A5;
-}
-
-
-static void sm_test_A6_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_A6;
-}
-
-static void sm_test_A6_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_A6;
-	} else {
-		set_state_sm(port, SM_TEST_A5);
-	}
-}
-
-static void sm_test_A6_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A6;
-}
-
-static void sm_test_A7_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_A7;
-}
-
-static void sm_test_A7_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_A7;
-	} else {
-		set_state_sm(port, SM_TEST_A6);
-	}
-}
-
-static void sm_test_A7_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_A7;
-}
-
-static void sm_test_B4_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_B4;
-}
-
-static void sm_test_B4_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].seq[sm[port].idx++] = RUN_B4;
-		sm[port].sv_tmp = 1;
-	} else {
-		set_state_sm(port, SM_TEST_B5);
-	}
-}
-
-static void sm_test_B4_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B4;
-}
-
-
-static void sm_test_B5_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_B5;
-}
-
-static void sm_test_B5_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_B5;
-	} else {
-		set_state_sm(port, SM_TEST_B6);
-	}
-}
-
-static void sm_test_B5_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B5;
-}
-
-
-static void sm_test_B6_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_B6;
-	if (test_control.b6_entry_to)
-		set_state(port, &sm[port].ctx, test_control.b6_entry_to);
-}
-
-static void sm_test_B6_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].sv_tmp = 1;
-		sm[port].seq[sm[port].idx++] = RUN_B6;
-	} else {
-		set_state_sm(port, SM_TEST_C);
-	}
-}
-
-static void sm_test_B6_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_B6;
-}
-
-static void sm_test_C_entry(const int port)
-{
-	sm[port].sv_tmp = 0;
-	sm[port].seq[sm[port].idx++] = ENTER_C;
-	if (test_control.c_entry_to)
-		set_state(port, &sm[port].ctx, test_control.c_entry_to);
-}
-
-static void sm_test_C_run(const int port)
-{
-	if (sm[port].sv_tmp == 0) {
-		sm[port].seq[sm[port].idx++] = RUN_C;
-		sm[port].sv_tmp = 1;
-	} else {
-		set_state_sm(port, SM_TEST_A7);
-	}
-}
-
-static void sm_test_C_exit(const int port)
-{
-	sm[port].seq[sm[port].idx++] = EXIT_C;
-	if (test_control.c_exit_to)
-		set_state(port, &sm[port].ctx, test_control.c_exit_to);
-}
-
-static void run_sm(void)
-{
-	task_wake(TASK_ID_TEST);
-	task_wait_event(5 * MSEC);
-}
-
-test_static int test_hierarchy_0(void)
-{
-	int port = PORT0;
-	int i = 0;
-
-	set_state_sm(port, SM_TEST_A4);
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	for (; i < SEQUENCE_SIZE; i++)
-		TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_hierarchy_1(void)
-{
-	int port = PORT0;
-	int i = 0;
-
-	set_state_sm(port, SM_TEST_A4);
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	for (i = 33; i < SEQUENCE_SIZE; i++)
-		TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_hierarchy_2(void)
-{
-
-	int port = PORT0;
-	int i = 0;
-
-	set_state_sm(port, SM_TEST_A4);
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	for (; i < SEQUENCE_SIZE; i++)
-		TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_hierarchy_3(void)
-{
-
-	int port = PORT0;
-	int i = 0;
-
-	set_state_sm(port, SM_TEST_A4);
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
-	for (; i < SEQUENCE_SIZE; i++)
-		TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_set_state_from_parents(void)
-{
-	int port = PORT0;
-	int i = 0;
-
-	/* Start state machine */
-	test_control.a3_entry_to = &states[SM_TEST_B4];
-	run_sm();
-	set_state_sm(port, SM_TEST_A4);
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	/* Does not enter or exit A4 */
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-	/* Ensure we didn't go further than above statements */
-	TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	test_control.b3_run_to = &states[SM_TEST_B5];
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	/* Does not run b2 or b1 */
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-	/* Ensure we didn't go further than above statements */
-	TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-	/* Ensure we didn't go further than above statements */
-	TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	/*
-	 * Ensure that multiple chains of parent entry works. Also ensure
-	 * that set states in exit are ignored.
-	 */
-	test_control.b6_entry_to = &states[SM_TEST_C];
-	test_control.c_entry_to = &states[SM_TEST_A7];
-	test_control.c_exit_to = &states[SM_TEST_A4];
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-	/* Ensure we didn't go further than above statements */
-	TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	for (; i < SEQUENCE_SIZE; i++)
-		TEST_EQ(sm[port].seq[i], 0, "%d");
-
-	return EC_SUCCESS;
-}
-
-#ifdef TEST_USB_SM_FRAMEWORK_H3
-#define TEST_AT_LEAST_3
-#endif
-
-#if defined(TEST_AT_LEAST_3) || defined(TEST_USB_SM_FRAMEWORK_H2)
-#define TEST_AT_LEAST_2
-#endif
-
-#if defined(TEST_AT_LEAST_2) || defined(TEST_USB_SM_FRAMEWORK_H1)
-#define TEST_AT_LEAST_1
-#endif
-
-static const struct usb_state states[] = {
-	[SM_TEST_SUPER_A1] = {
-		.entry  = sm_test_super_A1_entry,
-		.run    = sm_test_super_A1_run,
-		.exit   = sm_test_super_A1_exit,
-	},
-	[SM_TEST_SUPER_A2] = {
-		.entry  = sm_test_super_A2_entry,
-		.run    = sm_test_super_A2_run,
-		.exit   = sm_test_super_A2_exit,
-#ifdef TEST_AT_LEAST_3
-		.parent = &states[SM_TEST_SUPER_A1],
-#endif
-	},
-	[SM_TEST_SUPER_A3] = {
-		.entry  = sm_test_super_A3_entry,
-		.run    = sm_test_super_A3_run,
-		.exit   = sm_test_super_A3_exit,
-#ifdef TEST_AT_LEAST_2
-		.parent = &states[SM_TEST_SUPER_A2],
-#endif
-	},
-	[SM_TEST_SUPER_B1] = {
-		.entry  = sm_test_super_B1_entry,
-		.run    = sm_test_super_B1_run,
-		.exit   = sm_test_super_B1_exit,
-	},
-	[SM_TEST_SUPER_B2] = {
-		.entry  = sm_test_super_B2_entry,
-		.run    = sm_test_super_B2_run,
-		.exit   = sm_test_super_B2_exit,
-#ifdef TEST_AT_LEAST_3
-		.parent = &states[SM_TEST_SUPER_B1],
-#endif
-	},
-	[SM_TEST_SUPER_B3] = {
-		.entry  = sm_test_super_B3_entry,
-		.run    = sm_test_super_B3_run,
-		.exit   = sm_test_super_B3_exit,
-#ifdef TEST_AT_LEAST_2
-		.parent = &states[SM_TEST_SUPER_B2],
-#endif
-	},
-	[SM_TEST_A4] = {
-		.entry  = sm_test_A4_entry,
-		.run    = sm_test_A4_run,
-		.exit   = sm_test_A4_exit,
-#ifdef TEST_AT_LEAST_1
-		.parent = &states[SM_TEST_SUPER_A3],
-#endif
-	},
-	[SM_TEST_A5] = {
-		.entry  = sm_test_A5_entry,
-		.run    = sm_test_A5_run,
-		.exit   = sm_test_A5_exit,
-#ifdef TEST_AT_LEAST_1
-		.parent = &states[SM_TEST_SUPER_A3],
-#endif
-	},
-	[SM_TEST_A6] = {
-		.entry  = sm_test_A6_entry,
-		.run    = sm_test_A6_run,
-		.exit   = sm_test_A6_exit,
-#ifdef TEST_AT_LEAST_2
-		.parent = &states[SM_TEST_SUPER_A2],
-#endif
-	},
-	[SM_TEST_A7] = {
-		.entry  = sm_test_A7_entry,
-		.run    = sm_test_A7_run,
-		.exit   = sm_test_A7_exit,
-#ifdef TEST_AT_LEAST_3
-		.parent = &states[SM_TEST_SUPER_A1],
-#endif
-	},
-	[SM_TEST_B4] = {
-		.entry  = sm_test_B4_entry,
-		.run    = sm_test_B4_run,
-		.exit   = sm_test_B4_exit,
-#ifdef TEST_AT_LEAST_1
-		.parent = &states[SM_TEST_SUPER_B3],
-#endif
-	},
-	[SM_TEST_B5] = {
-		.entry  = sm_test_B5_entry,
-		.run    = sm_test_B5_run,
-		.exit   = sm_test_B5_exit,
-#ifdef TEST_AT_LEAST_2
-		.parent = &states[SM_TEST_SUPER_B2],
-#endif
-	},
-	[SM_TEST_B6] = {
-		.entry  = sm_test_B6_entry,
-		.run    = sm_test_B6_run,
-		.exit   = sm_test_B6_exit,
-#ifdef TEST_AT_LEAST_3
-		.parent = &states[SM_TEST_SUPER_B1],
-#endif
-	},
-	[SM_TEST_C] = {
-		.entry  = sm_test_C_entry,
-		.run    = sm_test_C_run,
-		.exit   = sm_test_C_exit,
-	},
-};
-
-/* Run before each RUN_TEST line */
-void before_test(void)
-{
-	/* Rest test variables */
-	memset(&sm[PORT0], 0, sizeof(struct sm_));
-	memset(&test_control, 0, sizeof(struct control));
-}
-
-int test_task(void *u)
-{
-	int port = PORT0;
-
-	while (1) {
-		/* wait for next event/packet or timeout expiration */
-		task_wait_event(-1);
-		/* run state machine */
-		run_state(port, &sm[port].ctx);
-	}
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-#if defined(TEST_USB_SM_FRAMEWORK_H3)
-	RUN_TEST(test_hierarchy_3);
-	RUN_TEST(test_set_state_from_parents);
-#elif defined(TEST_USB_SM_FRAMEWORK_H2)
-	RUN_TEST(test_hierarchy_2);
-#elif defined(TEST_USB_SM_FRAMEWORK_H1)
-	RUN_TEST(test_hierarchy_1);
-#else
-	RUN_TEST(test_hierarchy_0);
-#endif
-	test_print_result();
-}
diff --git a/test/usb_sm_framework_h3.tasklist b/test/usb_sm_framework_h3.tasklist
deleted file mode 100644
index 998998fd6c..0000000000
--- a/test/usb_sm_framework_h3.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(TEST, test_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_tcpmv2_compliance.c b/test/usb_tcpmv2_compliance.c
deleted file mode 100644
index e0288feb18..0000000000
--- a/test/usb_tcpmv2_compliance.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tc_sm.h"
-#include "usb_tcpmv2_compliance.h"
-
-void before_test(void)
-{
-	partner_set_pd_rev(PD_REV30);
-	partner_tx_msg_id_reset(TCPCI_MSG_SOP_ALL);
-
-	mock_usb_mux_reset();
-	mock_tcpci_reset();
-
-	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
-	task_wait_event(SECOND);
-
-	/*
-	 * Default to not allowing DUT to TRY.SRC and set it to be allowed
-	 * specifically in the TRY.SRC tests
-	 */
-	tc_try_src_override(TRY_SRC_OVERRIDE_OFF);
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_td_pd_ll_e3_dfp);
-	RUN_TEST(test_td_pd_ll_e3_ufp);
-	RUN_TEST(test_td_pd_ll_e4_dfp);
-	RUN_TEST(test_td_pd_ll_e4_ufp);
-	RUN_TEST(test_td_pd_ll_e5_dfp);
-	RUN_TEST(test_td_pd_ll_e5_ufp);
-	RUN_TEST(test_td_pd_src_e1);
-	RUN_TEST(test_td_pd_src_e2);
-	RUN_TEST(test_td_pd_src_e5);
-
-	RUN_TEST(test_td_pd_src3_e1);
-	RUN_TEST(test_td_pd_src3_e7);
-	RUN_TEST(test_td_pd_src3_e8);
-	RUN_TEST(test_td_pd_src3_e9);
-	RUN_TEST(test_td_pd_src3_e26);
-	RUN_TEST(test_td_pd_src3_e32);
-	RUN_TEST(test_td_pd_snk3_e12);
-
-	RUN_TEST(test_td_pd_vndi3_e3_dfp);
-	RUN_TEST(test_td_pd_vndi3_e3_ufp);
-
-	RUN_TEST(test_connect_as_nonpd_sink);
-	RUN_TEST(test_retry_count_sop);
-	RUN_TEST(test_retry_count_hard_reset);
-
-	test_print_result();
-}
diff --git a/test/usb_tcpmv2_compliance.h b/test/usb_tcpmv2_compliance.h
deleted file mode 100644
index 331e3c5ee8..0000000000
--- a/test/usb_tcpmv2_compliance.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef USB_TCPMV2_COMPLIANCE_H
-#define USB_TCPMV2_COMPLIANCE_H
-
-#define PORT0 0
-
-enum mock_cc_state {
-	MOCK_CC_SRC_OPEN = 0,
-	MOCK_CC_SNK_OPEN = 0,
-	MOCK_CC_SRC_RA = 1,
-	MOCK_CC_SNK_RP_DEF = 1,
-	MOCK_CC_SRC_RD = 2,
-	MOCK_CC_SNK_RP_1_5 = 2,
-	MOCK_CC_SNK_RP_3_0 = 3,
-};
-enum mock_connect_result {
-	MOCK_CC_DUT_IS_SRC = 0,
-	MOCK_CC_DUT_IS_SNK = 1,
-};
-
-
-extern uint32_t rdo;
-extern uint32_t pdo;
-
-extern const struct tcpc_config_t tcpc_config[];
-extern const struct usb_mux usb_muxes[];
-
-
-void mock_set_cc(enum mock_connect_result cr,
-	enum mock_cc_state cc1, enum mock_cc_state cc2);
-void mock_set_role(int drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2);
-void mock_set_alert(int alert);
-uint16_t tcpc_get_alert_status(void);
-bool vboot_allow_usb_pd(void);
-int pd_check_vconn_swap(int port);
-void board_reset_pd_mcu(void);
-
-int tcpci_startup(void);
-
-void partner_set_data_role(enum pd_data_role data_role);
-enum pd_data_role partner_get_data_role(void);
-
-void partner_set_power_role(enum pd_power_role power_role);
-enum pd_power_role partner_get_power_role(void);
-
-void partner_set_pd_rev(enum pd_rev_type pd_rev);
-enum pd_rev_type partner_get_pd_rev(void);
-
-#define TCPCI_MSG_SOP_ALL -1
-void partner_tx_msg_id_reset(int sop);
-
-void partner_send_msg(enum tcpci_msg_type sop,
-		      uint16_t type,
-		      uint16_t cnt,
-		      uint16_t ext,
-		      uint32_t *payload);
-
-
-int handle_attach_expected_msgs(enum pd_data_role data_role);
-
-
-enum proc_pd_e1_attach {
-	INITIAL_ATTACH			= BIT(0),
-	ALREADY_ATTACHED		= BIT(1),
-	INITIAL_AND_ALREADY_ATTACHED	= INITIAL_ATTACH | ALREADY_ATTACHED
-};
-int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach);
-int proc_pd_e3(void);
-
-int test_td_pd_ll_e3_dfp(void);
-int test_td_pd_ll_e3_ufp(void);
-int test_td_pd_ll_e4_dfp(void);
-int test_td_pd_ll_e4_ufp(void);
-int test_td_pd_ll_e5_dfp(void);
-int test_td_pd_ll_e5_ufp(void);
-
-int test_td_pd_src_e1(void);
-int test_td_pd_src_e2(void);
-int test_td_pd_src_e5(void);
-
-int test_td_pd_src3_e1(void);
-int test_td_pd_src3_e7(void);
-int test_td_pd_src3_e8(void);
-int test_td_pd_src3_e9(void);
-int test_td_pd_src3_e26(void);
-int test_td_pd_src3_e32(void);
-
-int test_td_pd_snk3_e12(void);
-
-int test_td_pd_vndi3_e3_dfp(void);
-int test_td_pd_vndi3_e3_ufp(void);
-
-int test_connect_as_nonpd_sink(void);
-int test_retry_count_sop(void);
-int test_retry_count_hard_reset(void);
-
-#endif /* USB_TCPMV2_COMPLIANCE_H */
diff --git a/test/usb_tcpmv2_compliance.mocklist b/test/usb_tcpmv2_compliance.mocklist
deleted file mode 100644
index f364fb1050..0000000000
--- a/test/usb_tcpmv2_compliance.mocklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_MUX)           \
-	MOCK(TCPCI_I2C)         \
-	MOCK(BATTERY)
diff --git a/test/usb_tcpmv2_compliance.tasklist b/test/usb_tcpmv2_compliance.tasklist
deleted file mode 100644
index 654e4eca2b..0000000000
--- a/test/usb_tcpmv2_compliance.tasklist
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_TEST(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_tcpmv2_compliance_common.c b/test/usb_tcpmv2_compliance_common.c
deleted file mode 100644
index c1c4f21e09..0000000000
--- a/test/usb_tcpmv2_compliance_common.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "hooks.h"
-#include "mock/tcpci_i2c_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-uint32_t rdo = RDO_FIXED(1, 500, 500, 0);
-uint32_t pdo = PDO_FIXED(5000, 3000,
-			 PDO_FIXED_DUAL_ROLE |
-			 PDO_FIXED_DATA_SWAP |
-			 PDO_FIXED_COMM_CAP);
-
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_HOST_TCPC,
-			.addr_flags = MOCK_TCPCI_I2C_ADDR_FLAGS,
-		},
-		.drv = &tcpci_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-
-void mock_set_cc(enum mock_connect_result cr,
-	enum mock_cc_state cc1, enum mock_cc_state cc2)
-{
-	mock_tcpci_set_reg(TCPC_REG_CC_STATUS,
-		TCPC_REG_CC_STATUS_SET(cr, cc1, cc2));
-}
-
-void mock_set_role(int drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2)
-{
-	mock_tcpci_set_reg(TCPC_REG_ROLE_CTRL,
-		TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2));
-}
-
-static int mock_alert_count;
-void mock_set_alert(int alert)
-{
-	mock_tcpci_set_reg_bits(TCPC_REG_ALERT, alert);
-	mock_alert_count = 1;
-	schedule_deferred_pd_interrupt(PORT0);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	ccprints("mock_alert_count %d", mock_alert_count);
-	if (mock_alert_count > 0) {
-		mock_alert_count--;
-		return PD_STATUS_TCPC_ALERT_0;
-	}
-	return 0;
-}
-
-bool vboot_allow_usb_pd(void)
-{
-	return 1;
-}
-
-int pd_check_vconn_swap(int port)
-{
-	return 1;
-}
-
-void board_reset_pd_mcu(void) {}
-
-/*****************************************************************************
- * Partner utility functions
- */
-static enum pd_data_role partner_data_role;
-void partner_set_data_role(enum pd_data_role data_role)
-{
-	partner_data_role = data_role;
-}
-enum pd_data_role partner_get_data_role(void)
-{
-	return partner_data_role;
-}
-
-static enum pd_power_role partner_power_role;
-void partner_set_power_role(enum pd_power_role power_role)
-{
-	partner_power_role = power_role;
-}
-enum pd_power_role partner_get_power_role(void)
-{
-	return partner_power_role;
-}
-
-static enum pd_rev_type partner_pd_rev;
-void partner_set_pd_rev(enum pd_rev_type pd_rev)
-{
-	partner_pd_rev = pd_rev;
-}
-enum pd_rev_type partner_get_pd_rev(void)
-{
-	return partner_pd_rev;
-}
-
-static int partner_tx_id[NUM_SOP_STAR_TYPES];
-void partner_tx_msg_id_reset(int sop)
-{
-	if (sop == TCPCI_MSG_SOP_ALL)
-		for (sop = 0; sop < NUM_SOP_STAR_TYPES; ++sop)
-			partner_tx_id[sop] = 0;
-	else
-		partner_tx_id[sop] = 0;
-}
-
-void partner_send_msg(enum tcpci_msg_type sop,
-		      uint16_t type,
-		      uint16_t cnt,
-		      uint16_t ext,
-		      uint32_t *payload)
-{
-	uint16_t header;
-
-	partner_tx_id[sop] &= 7;
-	header = PD_HEADER(type,
-			sop == TCPCI_MSG_SOP ? partner_get_power_role()
-			: PD_PLUG_FROM_CABLE,
-			partner_get_data_role(),
-			partner_tx_id[sop],
-			cnt,
-			partner_get_pd_rev(),
-			ext);
-
-	mock_tcpci_receive(sop, header, payload);
-	++partner_tx_id[sop];
-	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
-}
-
-
-/*****************************************************************************
- * TCPCI clean power up
- */
-int tcpci_startup(void)
-{
-	/* Should be in low power mode before AP boots. */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
-	task_wait_event(10 * SECOND);
-
-	hook_notify(HOOK_CHIPSET_STARTUP);
-	task_wait_event(5 * MSEC);
-	hook_notify(HOOK_CHIPSET_RESUME);
-
-	task_wait_event(10 * SECOND);
-	/* Should be in low power mode and DRP auto-toggling with AP in S0. */
-	TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)
-		 & TCPC_REG_ROLE_CTRL_DRP_MASK),
-		TCPC_REG_ROLE_CTRL_DRP_MASK, "%d");
-	/* TODO: check previous command was TCPC_REG_COMMAND_LOOK4CONNECTION */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
-
-	/* TODO: this should be performed in TCPCI mock on startup but needs
-	 * more TCPCI functionality added before that can happen.  So until
-	 * that time, if the FAULT register is set, send the alert here.
-	 */
-	if (mock_tcpci_get_reg(TCPC_REG_FAULT_STATUS))
-		mock_set_alert(TCPC_REG_ALERT_FAULT);
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************
- * PROC.PD.E1. Bring-up procedure
- */
-int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
-{
-	if (attach & INITIAL_ATTACH) {
-		/*
-		 * a) The test starts in a disconnected state.
-		 */
-		mock_tcpci_set_reg(TCPC_REG_EXT_STATUS,
-				   TCPC_REG_EXT_STATUS_SAFE0V);
-		mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-		task_wait_event(10 * SECOND);
-		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC),
-			PD_ROLE_DISCONNECTED, "%d");
-
-		partner_set_data_role((data_role == PD_ROLE_UFP)
-						? PD_ROLE_DFP
-						: PD_ROLE_UFP);
-
-		partner_set_power_role((data_role == PD_ROLE_UFP)
-						? PD_ROLE_SOURCE
-						: PD_ROLE_SINK);
-
-		switch (partner_get_power_role()) {
-		case PD_ROLE_SOURCE:
-			/*
-			 * b) The tester applies Rp (PD3=1.5A, PD2=3A) and
-			 *    waits for the UUT attachment.
-			 */
-			mock_set_cc(MOCK_CC_DUT_IS_SNK,
-				    MOCK_CC_SNK_OPEN,
-				    (partner_get_pd_rev() == PD_REV30
-					? MOCK_CC_SNK_RP_1_5
-					: MOCK_CC_SNK_RP_3_0));
-			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-			task_wait_event(5 * MSEC);
-
-			/*
-			 * c) If Ra is detected, the tester applies Vconn.
-			 */
-
-			/*
-			 * d) The tester applies Vbus and waits 50 ms.
-			 */
-			mock_tcpci_set_reg_bits(TCPC_REG_POWER_STATUS,
-					TCPC_REG_POWER_STATUS_VBUS_PRES);
-
-			mock_tcpci_clr_reg_bits(TCPC_REG_EXT_STATUS,
-					TCPC_REG_EXT_STATUS_SAFE0V);
-			mock_set_alert(TCPC_REG_ALERT_EXT_STATUS |
-				       TCPC_REG_ALERT_POWER_STATUS);
-			task_wait_event(50 * MSEC);
-			break;
-
-		case PD_ROLE_SINK:
-			/*
-			 * b) The tester applies Rd and waits for Vbus for
-			 *    tNoResponse max (5.5 s).
-			 */
-			mock_set_cc(MOCK_CC_DUT_IS_SRC,
-				    MOCK_CC_SRC_OPEN,
-				    MOCK_CC_SRC_RD);
-			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-			break;
-		}
-	}
-
-	if (attach & ALREADY_ATTACHED) {
-		switch (partner_get_power_role()) {
-		case PD_ROLE_SOURCE:
-			/*
-			 * e) The tester transmits Source Capabilities until
-			 *    reception of GoodCrc for tNoResponse max (5.5s).
-			 *    The Source Capabilities includes Fixed 5V 3A PDO.
-			 */
-			task_wait_event(1 * MSEC);
-			partner_send_msg(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 1,
-					0, &pdo);
-
-			/*
-			 * f) The tester waits for the Request from the UUT for
-			 *    tSenderResponse max (30 ms).
-			 */
-			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0,
-						      PD_DATA_REQUEST),
-				EC_SUCCESS, "%d");
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-			/*
-			 * g) The tester sends Accept, and when Vbus is stable
-			 *    at the target voltage, sends PS_RDY.
-			 */
-			partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0, 0,
-					 NULL);
-			task_wait_event(10 * MSEC);
-			partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_PS_RDY, 0, 0,
-					 NULL);
-			task_wait_event(1 * MSEC);
-
-			TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-			break;
-
-		case PD_ROLE_SINK:
-			/*
-			 * c) The tester waits Source Capabilities for for
-			 *    tNoResponse max (5.5 s).
-			 */
-			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0,
-						      PD_DATA_SOURCE_CAP),
-				EC_SUCCESS, "%d");
-
-			/*
-			 * d) The tester replies GoodCrc on reception of the
-			 *    Source Capabilities.
-			 */
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-			task_wait_event(10 * MSEC);
-
-			/*
-			 * e) The tester requests 5V 0.5A.
-			 */
-			partner_send_msg(TCPCI_MSG_SOP, PD_DATA_REQUEST, 1, 0,
-					 &rdo);
-
-			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP,
-						      PD_CTRL_ACCEPT, 0),
-				EC_SUCCESS, "%d");
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-			/*
-			 * f) The tester waits PS_RDY for tPSSourceOn max
-			 *    (480 ms).
-			 */
-			TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP,
-						      PD_CTRL_PS_RDY, 0),
-				EC_SUCCESS, "%d");
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-			TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
-			break;
-		}
-		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC),
-			data_role, "%d");
-	}
-
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************
- * PROC.PD.E3. Wait to Start AMS for DFP(Source) UUT
- */
-int proc_pd_e3(void)
-{
-	/*
-	 * Make sure we are idle. Reject everything that is pending
-	 */
-	TEST_EQ(handle_attach_expected_msgs(PD_ROLE_DFP), EC_SUCCESS, "%d");
-
-	/*
-	 * PROC.PD.E3. Wait to Start AMS for DFP(Source) UUT:
-	 * a) The Tester keeps monitoring the Rp value and if the UUT doesn't
-	 * set the value to SinkTXOK if it doesn't have anything to send in 1s,
-	 * the test fails. During this period, the Tester replies any message
-	 * sent from the UUT with a proper response.
-	 */
-	TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
-	TEST_EQ(TCPC_REG_ROLE_CTRL_RP(mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)),
-		SINK_TX_OK, "%d");
-
-	task_wait_event(10 * SECOND);
-	return EC_SUCCESS;
-}
-
-/*****************************************************************************
- * handle_attach_expected_msgs
- *
- * Depending on the data role, the DUT will send a sequence of messages on
- * attach. Most of these can be rejected.
- */
-int handle_attach_expected_msgs(enum pd_data_role data_role)
-{
-	int rv;
-	int found_index;
-	struct possible_tx possible[4];
-
-	if (data_role == PD_ROLE_DFP) {
-		possible[0].tx_type = TCPCI_MSG_SOP;
-		possible[0].ctrl_msg = PD_CTRL_GET_SOURCE_CAP;
-		possible[0].data_msg = 0;
-
-		possible[1].tx_type = TCPCI_MSG_SOP;
-		possible[1].ctrl_msg = PD_CTRL_GET_SINK_CAP;
-		possible[1].data_msg = 0;
-
-		possible[2].tx_type = TCPCI_MSG_SOP_PRIME;
-		possible[2].ctrl_msg = 0;
-		possible[2].data_msg = PD_DATA_VENDOR_DEF;
-
-		possible[3].tx_type = TCPCI_MSG_SOP;
-		possible[3].ctrl_msg = 0;
-		possible[3].data_msg = PD_DATA_VENDOR_DEF;
-
-		do {
-			rv = verify_tcpci_possible_tx(possible,
-						 4,
-						 &found_index,
-						 NULL,
-						 0,
-						 NULL,
-						 -1);
-
-			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
-			if (rv == EC_ERROR_TIMEOUT)
-				break;
-
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-			task_wait_event(10 * MSEC);
-
-			switch (found_index) {
-			case 0:	/* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SOURCE_CAP,
-						 1, 0, &pdo);
-				break;
-			case 1: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SINK_CAP,
-						 1, 0, &pdo);
-				break;
-			case 2: /* TCPCI_MSG_SOP_PRIME PD_DATA_VENDOR_DEF */
-				partner_send_msg(TCPCI_MSG_SOP_PRIME,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
-				break;
-			case 3: /* TCPCI_MSG_SOP PD_DATA_VENDOR_DEF */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
-				break;
-			default:
-				TEST_ASSERT(0);
-				break;
-			}
-		} while (rv != EC_ERROR_TIMEOUT);
-	} else if (data_role == PD_ROLE_UFP) {
-		int vcs = 0;
-
-		possible[0].tx_type = TCPCI_MSG_SOP;
-		possible[0].ctrl_msg = PD_CTRL_GET_SINK_CAP;
-		possible[0].data_msg = 0;
-
-		possible[1].tx_type = TCPCI_MSG_SOP;
-		possible[1].ctrl_msg = PD_CTRL_DR_SWAP;
-		possible[1].data_msg = 0;
-
-		possible[2].tx_type = TCPCI_MSG_SOP;
-		possible[2].ctrl_msg = PD_CTRL_PR_SWAP;
-		possible[2].data_msg = 0;
-
-		possible[3].tx_type = TCPCI_MSG_SOP;
-		possible[3].ctrl_msg = PD_CTRL_VCONN_SWAP;
-		possible[3].data_msg = 0;
-
-		do {
-			rv = verify_tcpci_possible_tx(possible,
-						 4,
-						 &found_index,
-						 NULL,
-						 0,
-						 NULL,
-						 -1);
-
-			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
-			if (rv == EC_ERROR_TIMEOUT)
-				break;
-
-			mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-			task_wait_event(10 * MSEC);
-
-			switch (found_index) {
-			case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SINK_CAP,
-						 1, 0, &pdo);
-				break;
-			case 1: /* TCPCI_MSG_SOP PD_CTRL_DR_SWAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
-						 0, 0, NULL);
-				break;
-			case 2:	/* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
-						 0, 0, NULL);
-				break;
-			case 3: /* TCPCI_MSG_SOP PD_CTRL_VCONN_SWAP */
-				TEST_LT(vcs++, 4, "%d");
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
-						 0, 0, NULL);
-				break;
-			default:
-				TEST_ASSERT(0);
-				break;
-			}
-		} while (rv != EC_ERROR_TIMEOUT);
-	}
-	task_wait_event(1 * SECOND);
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_ll_e3.c b/test/usb_tcpmv2_td_pd_ll_e3.c
deleted file mode 100644
index 46fbee393f..0000000000
--- a/test/usb_tcpmv2_td_pd_ll_e3.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-/*****************************************************************************
- * TD.PD.LL.E3. Soft Reset Usage
- *
- * Description:
- *	Check that the UUT will issue a Soft Reset after unsuccessful retries,
- *	and that the link can be successfully recovered after that.
- */
-static int td_pd_ll_e3(enum pd_data_role data_role)
-{
-	int retries;
-
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * Make sure we are idle. Reject everything that is pending
-	 */
-	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Send a Get_Sink_Cap message to the UUT, wait for a reply
-	 *    and do not send GoodCrc for nRetryCount + 1 times
-	 *    (nRetryCount equals 3 since PD 2.1).
-	 */
-	partner_send_msg(TCPCI_MSG_SOP,
-			 PD_CTRL_GET_SINK_CAP,
-			 0, 0, NULL);
-
-	retries = (partner_get_pd_rev() == PD_REV30) ? 2 : 3;
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
-			retries),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-
-	/*
-	 * c) Check that the UUT issues a Soft Reset.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * d) Handle correctly the Soft Reset procedure.
-	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0, 0, NULL);
-
-	/*
-	 * e) Continue the bring-up procedure and check that the link is
-	 *    successfully established.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-int test_td_pd_ll_e3_dfp(void)
-{
-	return td_pd_ll_e3(PD_ROLE_DFP);
-}
-int test_td_pd_ll_e3_ufp(void)
-{
-	return td_pd_ll_e3(PD_ROLE_UFP);
-}
diff --git a/test/usb_tcpmv2_td_pd_ll_e4.c b/test/usb_tcpmv2_td_pd_ll_e4.c
deleted file mode 100644
index cb6aa8e8b6..0000000000
--- a/test/usb_tcpmv2_td_pd_ll_e4.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-/*****************************************************************************
- * TD.PD.LL.E4. Hard Reset Usage
- *
- * Description:
- *	Check that the UUT will issue a Soft Reset after unsuccessful retries,
- *	and that the link can be successfully recovered after that.
- *	Check that the UUT will issue a Hard Reset if the Soft Reset fails,
- *	and that the link can be successfully recovered after that.
- */
-static int td_pd_ll_e4(enum pd_data_role data_role)
-{
-	int retries;
-
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * Make sure we are idle. Reject everything that is pending
-	 */
-	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Send a Get_Sink_Cap message to the UUT, wait for a reply
-	 *    and do not send GoodCrc for nRetryCount + 1 times
-	 *    (nRetryCount equals 3 since PD 2.1).
-	 */
-	partner_send_msg(TCPCI_MSG_SOP,
-			 PD_CTRL_GET_SINK_CAP,
-			 0, 0, NULL);
-
-	retries = 3;
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
-			retries),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-
-	/*
-	 * c) Wait the nRetryCount + 1 (four) Soft Resets from the UUT and do
-	 *    not reply GoodCrc.
-	 */
-	retries = 3;
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET,
-				0, retries),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-	task_wait_event(1 * MSEC);
-
-	/*
-	 * d) Check that the UUT issues a Hard Reset.
-	 */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
-		TCPCI_MSG_TX_HARD_RESET, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
-	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
-	task_wait_event(1 * MSEC);
-
-	/*
-	 * e) Do the bring-up procedure for Link tests and check that the link
-	 *    is successfully established.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-int test_td_pd_ll_e4_dfp(void)
-{
-	return td_pd_ll_e4(PD_ROLE_DFP);
-}
-int test_td_pd_ll_e4_ufp(void)
-{
-	return td_pd_ll_e4(PD_ROLE_UFP);
-}
diff --git a/test/usb_tcpmv2_td_pd_ll_e5.c b/test/usb_tcpmv2_td_pd_ll_e5.c
deleted file mode 100644
index ae6409eb20..0000000000
--- a/test/usb_tcpmv2_td_pd_ll_e5.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-/*****************************************************************************
- * TD.PD.LL.E5. Soft Reset
- *
- * Description:
- *	Check that the UUT will correctly complete the Soft Reset procedure.
- */
-static int td_pd_ll_e5(enum pd_data_role data_role)
-{
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * Make sure we are idle. Reject everything that is pending
-	 */
-	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Initiate a Soft Reset and check that the procedure is completed
-	 *    successfully.
-	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 0, NULL);
-
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_ACCEPT, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	TEST_EQ(proc_pd_e1(data_role, ALREADY_ATTACHED), EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
-int test_td_pd_ll_e5_dfp(void)
-{
-	return td_pd_ll_e5(PD_ROLE_DFP);
-}
-int test_td_pd_ll_e5_ufp(void)
-{
-	return td_pd_ll_e5(PD_ROLE_UFP);
-}
diff --git a/test/usb_tcpmv2_td_pd_other.c b/test/usb_tcpmv2_td_pd_other.c
deleted file mode 100644
index 1882480150..0000000000
--- a/test/usb_tcpmv2_td_pd_other.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-#include "usb_prl_sm.h"
-
-int test_connect_as_nonpd_sink(void)
-{
-	task_wait_event(10 * SECOND);
-
-	/* Simulate a non-PD power supply being plugged in. */
-	mock_set_cc(MOCK_CC_DUT_IS_SNK, MOCK_CC_SNK_OPEN, MOCK_CC_SNK_RP_3_0);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	task_wait_event(50 * MSEC);
-
-	mock_tcpci_set_reg(TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_PRES);
-	mock_set_alert(TCPC_REG_ALERT_POWER_STATUS);
-
-	task_wait_event(10 * SECOND);
-	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-int test_retry_count_sop(void)
-{
-	/* DRP auto-toggling with AP in S0, source enabled. */
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * The test starts in a disconnected state.
-	 */
-	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
-	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-	task_wait_event(10 * SECOND);
-
-	/*
-	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
-	 */
-	mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	/*
-	 * The Tester waits for Source_Capabilities for tNoResponse max.
-	 *
-	 * Source Caps is SOP message which should be retried at TCPC layer.
-	 * The retry count for PD3 should be 2.
-	 */
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0,
-				PD_DATA_SOURCE_CAP, 2),
-		EC_SUCCESS, "%d");
-	return EC_SUCCESS;
-}
-
-int test_retry_count_hard_reset(void)
-{
-	/* DRP auto-toggling with AP in S0, source enabled. */
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * The test starts in a disconnected state.
-	 */
-	mock_tcpci_set_reg(TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V);
-	mock_set_alert(TCPC_REG_ALERT_EXT_STATUS);
-	task_wait_event(10 * SECOND);
-
-	/*
-	 * The Tester applies Rd and waits for Vbus for tNoResponse max.
-	 */
-	mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD);
-	mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
-
-	/*
-	 * The Tester waits for Source_Capabilities for tNoResponse max.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	/*
-	 * The Tester replies GoodCrc on reception of the Source_Capabilities.
-	 */
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-
-	/*
-	 * Now that PRL is running since we are connected, we can send a hard
-	 * reset.
-	 */
-
-	/* Request that DUT send hard reset */
-	prl_execute_hard_reset(PORT0);
-
-	/* The retry count for hard resets should be 0 */
-	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_TX_HARD_RESET, 0, 0, 0),
-		EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_snk3_e12.c b/test/usb_tcpmv2_td_pd_snk3_e12.c
deleted file mode 100644
index 0195d39dba..0000000000
--- a/test/usb_tcpmv2_td_pd_snk3_e12.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-
-/*****************************************************************************
- * TD.PD.SNK3.E12.Soft_Reset sent regardless of Rp value
- *
- * Description:
- *	As Provider (DFP), the Tester forces the UUT to send Soft_Reset and
- *	verifies Soft_Reset is sent regardless even though the Rp value is
- *	SinkTxNG.
- */
-int test_td_pd_snk3_e12(void)
-{
-	/*
-	 * TD.PD.SNK3.E12.Soft_Reset sent regardless of Rp value
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-	TEST_EQ(proc_pd_e1(PD_ROLE_UFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * b) The Tester keeps the Rp value as SinkTXNG and sends a
-	 * Get_Sink_Cap message to the UUT.
-	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
-
-	/*
-	 * c) Upon receipt of the Sink_Capabilities Message, the Tester doesn't
-	 * reply with GoodCRC.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-
-	/*
-	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
-	 * within tReceive max + tSoftReset max
-	 */
-	TEST_EQ(verify_tcpci_tx_timeout(
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 16 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e1.c b/test/usb_tcpmv2_td_pd_src3_e1.c
deleted file mode 100644
index 751e354b11..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e1.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-#define BUFFER_SIZE 100
-
-#define HEADER_BYTE_OFFSET 1
-#define HEADER_BYTE_CNT 2
-#define PDO_BYTE_CNT 4
-
-enum pd_revision {
-	REVISION_1 = 0,
-	REVISION_2 = 1,
-	REVISION_3 = 2,
-	REVISION_RESERVED = 3
-};
-
-/*****************************************************************************
- * TD.PD.SRC3.E1 Source Capabilities Fields Checks
- *
- * Description:
- *	As Consumer (UFP), the Tester waits for a Source_Capabilities message
- *	from the Provider (DFP,UUT) and verifies correct field values.
- */
-int test_td_pd_src3_e1(void)
-{
-	int i;
-	int msg_len;
-	uint8_t data[BUFFER_SIZE];
-	uint16_t header;
-	uint16_t pd_cnt;
-	uint32_t pdo;
-	uint32_t type;
-	uint32_t last_fixed_voltage = 0;
-	uint32_t last_battery_voltage = 0;
-	uint32_t last_variable_voltage = 0;
-	uint32_t last_programmable_voltage = 0;
-
-	partner_set_pd_rev(PD_REV30);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up For DFP UUT steps a and b.
-	 *
-	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
-	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
-	 * there to gather the actual message data.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Upon receipt of the Source_Capabilities message from the
-	 *    Provider, the Tester verifies:
-	 *    1. Number of Data Objects field equals the number of Src_PDOs in
-	 *       the message and is not 000b.
-	 *    2. Port Power Role field = 1b (Source)
-	 *    3. Specification Revision field = 10b (Rev 3.0)
-	 *    4. Port Data Role field = 1b (DFP)
-	 *    5. Message Type field = 00001b (Source Capabilities)
-	 *    6. Extended field = 0b
-	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					  PD_DATA_SOURCE_CAP,
-					  data,
-					  sizeof(data),
-					  &msg_len,
-					  0),
-		EC_SUCCESS, "%d");
-	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
-
-	header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
-	pd_cnt = PD_HEADER_CNT(header);
-	TEST_NE(pd_cnt, 0, "%d");
-	TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
-			 (pd_cnt * PDO_BYTE_CNT), "%d");
-	TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d");
-	TEST_EQ(PD_HEADER_REV(header), REVISION_3, "%d");
-	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
-	TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d");
-	TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
-
-	/*
-	 * c) For the first PDO, the Tester verifies:
-	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply).
-	 *    2. Voltage field = 100 (5 V)
-	 *    3. Bits 23..22 = 000b (Reserved)
-	 */
-	pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-					      HEADER_BYTE_CNT);
-
-	type = pdo & PDO_TYPE_MASK;
-	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
-
-	last_fixed_voltage = PDO_FIXED_VOLTAGE(pdo);
-	TEST_EQ(last_fixed_voltage, 5000, "%d");
-	TEST_EQ(pdo & GENMASK(23, 22), 0, "%d");
-
-	/*
-	 * d) For the other PDOs (if any), the Tester verifies:
-	 *    1. If Bits 31..30 are 00b
-	 *       -- Bits 29..22 are set to 0.
-	 *       NOTE: Bit 29 is Dual Role Power and looks correct for this
-	 *             to not be 0.  Bit 25 is Dual Role Data and looks
-	 *             correct for this to not be 0.
-	 *    2. If Bits 31..30 are 11b
-	 *       --  Bits 29..28 are 00b (Programmable Power Supply)
-	 *       --  Bits 26..25 are 00b (Reserved)
-	 *       --  Bit 16 is 0b (Reserved)
-	 *       --  Bit 7 is 0b (Reserved)
-	 *    3. PDOs are in the order of Fixed Supply Objects (if present),
-	 *       Battery Supply Objects (if present), Variable Supply Objects
-	 *       (if present) and then Programmable Power Supply Objects (if
-	 *       present).
-	 *    4. Fixed Supply Objects (if present) are in voltage order; lowest
-	 *       to highest.
-	 *    5. Battery Supply Objects (if present) are in Minimum Voltage
-	 *       order; lowest to highest.
-	 *    6. Variable Supply Objects (if present) are in Minimum Voltage
-	 *       order; lowest to highest.
-	 *    7. Programmable Power Supply Objects (if present) are in Maximum
-	 *       Voltage order; lowest to highest.
-	 */
-	for (i = 1; i < pd_cnt; ++i) {
-		int offset;
-		uint32_t voltage;
-
-		offset = HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
-			 (i * PDO_BYTE_CNT);
-		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
-
-		type = pdo & PDO_TYPE_MASK;
-		if (type == PDO_TYPE_FIXED) {
-			TEST_EQ(pdo & (GENMASK(28, 26)|GENMASK(24, 22)),
-				0, "%d");
-			TEST_EQ(last_battery_voltage, 0, "%d");
-			TEST_EQ(last_variable_voltage, 0, "%d");
-			TEST_EQ(last_programmable_voltage, 0, "%d");
-			voltage = PDO_FIXED_VOLTAGE(pdo);
-			TEST_GE(voltage, last_fixed_voltage, "%d");
-			last_fixed_voltage = voltage;
-		} else if (type == PDO_TYPE_BATTERY) {
-			TEST_EQ(last_variable_voltage, 0, "%d");
-			TEST_EQ(last_programmable_voltage, 0, "%d");
-			voltage = PDO_BATT_MIN_VOLTAGE(pdo);
-			TEST_GE(voltage, last_battery_voltage, "%d");
-			last_battery_voltage = voltage;
-		} else if (type == PDO_TYPE_VARIABLE) {
-			TEST_EQ(last_programmable_voltage, 0, "%d");
-			voltage = PDO_VAR_MIN_VOLTAGE(pdo);
-			TEST_GE(voltage, last_variable_voltage, "%d");
-			last_variable_voltage = voltage;
-		} else {
-			TEST_EQ(pdo & GENMASK(29, 28), 0, "%d");
-			TEST_EQ(pdo & GENMASK(26, 25), 0, "%d");
-			TEST_EQ(pdo & BIT(16), 0, "%d");
-			TEST_EQ(pdo & BIT(7), 0, "%d");
-			voltage = PDO_AUG_MAX_VOLTAGE(pdo);
-			TEST_GE(voltage, last_programmable_voltage, "%d");
-			last_programmable_voltage = voltage;
-		}
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e26.c b/test/usb_tcpmv2_td_pd_src3_e26.c
deleted file mode 100644
index f5f5bcd3c4..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e26.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-
-/*****************************************************************************
- * TD.PD.SRC3.E26.Soft_Reset sent regardless of Rp value
- *
- * Description:
- *	As Consumer (UFP), the Tester forces the UUT to send Soft_Reset and
- *	verifies Soft_Reset is sent regardless of the Rp value is SinkTxOK or
- *	SinkTxNG.
- */
-int test_td_pd_src3_e26(void)
-{
-	/*
-	 * TD.PD.SRC3.E26.Soft_Reset sent regardless of Rp value
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3)...
-	 */
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
-
-	/*
-	 * ...and sends a Get_Source_Cap message to the UUT.
-	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, 0, NULL);
-
-	/*
-	 * c) Upon receipt of the Source_Capabilities Message, the Tester
-	 * doesn’t reply with GoodCRC.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
-
-	/*
-	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
-	 * within tReceive max (1.1 ms) + tSoftReset max (15 ms).
-	 */
-	TEST_EQ(verify_tcpci_tx_timeout(
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 15 * MSEC),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e32.c b/test/usb_tcpmv2_td_pd_src3_e32.c
deleted file mode 100644
index 9ade7b83c8..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e32.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-
-#define PD_T_CHUNK_RECEIVER_REQUEST_MAX		(15 * MSEC)
-#define PD_T_CHUNK_SENDER_RSP_MAX		(30 * MSEC)
-#define PD_T_CHUNKING_NOT_SUPPORTED_MIN		(40 * MSEC)
-#define PD_T_CHUNKING_NOT_SUPPORTED_MAX		(50 * MSEC)
-
-static void setup_chunk_msg(int chunk, char *data)
-{
-	int i;
-	int base_msg_byte = chunk * PD_MAX_EXTENDED_MSG_CHUNK_LEN;
-
-	*(uint16_t *)data = PD_EXT_HEADER(chunk, 0,
-					  PD_MAX_EXTENDED_MSG_LEN);
-
-	for (i = 0; i < PD_MAX_EXTENDED_MSG_CHUNK_LEN; ++i) {
-		int val = (i + base_msg_byte) % 256;
-
-		data[i + sizeof(uint16_t)] = val;
-	}
-}
-
-/*****************************************************************************
- * TD.PD.SRC3.E32 ChunkSenderResponseTimer Timeout
- *
- * Description:
- *	As Consumer (UFP), the Tester verifies that the UUT recovers correctly
- *	after the Tester stops sending chunked messages in the middle.
- */
-int test_td_pd_src3_e32(void)
-{
-	int chunk = 0;
-	int msg_len;
-	uint32_t header;
-	char data[PD_MAX_EXTENDED_MSG_CHUNK_LEN + sizeof(uint16_t)];
-
-	int found_index;
-	struct possible_tx possible[2];
-
-	uint64_t start_time;
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role. The Tester
-	 * sets Unchunked Extended Messages Supported set to 0 in Request
-	 * message during this process.
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3)
-	 */
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
-
-	/*
-	 * ...and sends the first chunk of a chunked extended message
-	 * to the UUT, with Data Size set to 260 and Message Type set
-	 * to 11111b.  Bytes 0 to 259 of data block contain
-	 * incrementing values (mod 256) starting at 0x00.
-	 */
-	setup_chunk_msg(0, data);
-	partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
-	start_time = get_time().val;
-
-	/*
-	 * c) If a message is not received within tChunkingNotSupported
-	 * max (50ms), this test fails. The delay is messaged from the
-	 * time the last bit of the EOP of the chunk has been
-	 * transmitted until the first bit of the response Message
-	 * Preamble has been received.
-	 */
-	possible[0].tx_type = TCPCI_MSG_SOP;
-	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
-	possible[0].data_msg = 0;
-
-	possible[1].tx_type = TCPCI_MSG_SOP;
-	possible[1].ctrl_msg = 0;
-	possible[1].data_msg = 0x1F;
-
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 PD_T_CHUNKING_NOT_SUPPORTED_MAX),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	/*
-	 * d) If the received message is Not_Supported, the Tester verifies
-	 * the message is received after tChunkingNotSupported min (40ms)
-	 * and stops here.
-	 */
-	if (found_index == 0) {
-		TEST_ASSERT((get_time().val - start_time) >=
-			    PD_T_CHUNKING_NOT_SUPPORTED_MIN);
-		return EC_SUCCESS;
-	}
-	TEST_EQ(found_index, 1, "%d");
-
-	/*
-	 * e) If the message is not received within
-	 * tChunkReceiverRequest max (15ms), the test fails.
-	 */
-	TEST_ASSERT((get_time().val - start_time) <=
-					PD_T_CHUNK_RECEIVER_REQUEST_MAX);
-
-	while (chunk < 4) {
-		int next_chunk;
-
-		/*
-		 * f) Upon receipt of the message from the UUT to request for
-		 * the next chunk, the Tester sends the requested chunk to the
-		 * UUT.
-		 */
-		header = *(uint16_t *)&data[3];
-		next_chunk = PD_EXT_HEADER_CHUNK_NUM(header);
-		TEST_EQ(chunk + 1, next_chunk, "%d");
-		chunk = next_chunk;
-
-		setup_chunk_msg(chunk, data);
-		partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
-
-		TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					0x1F,
-					data,
-					sizeof(data),
-					&msg_len,
-					PD_T_CHUNK_RECEIVER_REQUEST_MAX),
-			EC_SUCCESS, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-		/*
-		 * g) Repeat f) until the Tester has finished sending 4 chunks
-		 * and intentionally does not send the 5th chunk to the UUT.
-		 */
-	}
-
-	/*
-	 * h) The Tester waits for tChunkSenderResponse max + 5 ms, waits until
-	 * it can start an AMS (Run PROC.PD.E3) and sends the first chunk to
-	 * the UUT.
-	 */
-	task_wait_event(PD_T_CHUNK_SENDER_RSP_MAX + (5 * MSEC));
-
-	setup_chunk_msg(0, data);
-	partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
-
-	/*
-	 * i) If a message is not received within tChunkReceiverRequest max,
-	 * the test fails.
-	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-				0x1F,
-				data,
-				sizeof(data),
-				&msg_len,
-				PD_T_CHUNK_RECEIVER_REQUEST_MAX),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	/*
-	 * j) Upon receipt of the message, the Tester verifies the following:
-	 *	1. For Message Header
-	 *	  Extended = 1
-	 *	   Number of Data Objects = 1
-	 *	  Port Power Role field = 1b (Source)
-	 *	  Port Data Role field = 1b (DFP)
-	 *	  Specification Revision = 10b (Rev 3.0)
-	 *	  Message Type = 11111b
-	 */
-	TEST_EQ(msg_len, 7, "%d");
-	header = *(uint32_t *)&data[1];
-	TEST_EQ(PD_HEADER_EXT(header), 1, "%d");
-	TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
-	TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
-	TEST_EQ(PD_HEADER_DROLE(header), 1, "%d");
-	TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
-	TEST_EQ(PD_HEADER_TYPE(header), 0x1F, "%d");
-
-	/*
-	 *	2. For Extended Message Header
-	 *	  Chunked = 1
-	 *	  Chunk Number = 1
-	 *	  Request Chunk = 1
-	 *	  Bit 9 = 0 (Reserved)
-	 *	  Data Size = 0
-	 */
-	header = *(uint16_t *)&data[3];
-	TEST_EQ(PD_EXT_HEADER_CHUNKED(header), 1, "%d");
-	TEST_EQ(PD_EXT_HEADER_CHUNK_NUM(header), 1, "%d");
-	TEST_EQ(PD_EXT_HEADER_REQ_CHUNK(header), 1, "%d");
-	TEST_EQ(header & BIT(9), 0, "%d");
-	TEST_EQ(PD_EXT_HEADER_DATA_SIZE(header), 0, "%d");
-
-	/*
-	 *	3. The total number of data bytes is consistent with the
-	 *	   Number of Data Objects field
-	 */
-	header = *(uint32_t *)&data[1];
-	TEST_EQ(msg_len - 3,
-		PD_HEADER_CNT(header) * 4,
-		"%d");
-
-	/*
-	 *	4. The last 2 bytes of the Data Object are 0
-	 */
-	TEST_EQ(data[5], 0, "%d");
-	TEST_EQ(data[6], 0, "%d");
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e7.c b/test/usb_tcpmv2_td_pd_src3_e7.c
deleted file mode 100644
index 409d0d6b80..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e7.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "driver/tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-#define BUFFER_SIZE 100
-
-#define HEADER_BYTE_OFFSET 1
-#define HEADER_BYTE_CNT 2
-#define SRC_CAP_EXT_NUM_BATTERY_OFFSET 22
-
-#define EXT_MSG_CHUNKED BIT(15)
-#define EXT_MSG_DATA_SIZE_1 1
-#define GBSDB_FIXED_BATTERY_0 (0 << 16)
-
-
-static int number_of_fixed_batteries(void)
-{
-	return CONFIG_NUM_FIXED_BATTERIES;
-}
-
-static int number_of_swappable_batteries(void)
-{
-	return 0;
-}
-
-/*****************************************************************************
- * TD.PD.SRC3.E7 Battery Status sent timely
- *
- * Description:
- *	As Consumer (UFP), the Tester verifies that the UUT replies
- *	Get_Battery_Status message with a Battery_Status message timely.
- */
-int test_td_pd_src3_e7(void)
-{
-	int msg_len;
-	uint8_t data[BUFFER_SIZE];
-	uint32_t ext_msg;
-
-	int found_index;
-	struct possible_tx possible[2];
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Source_Cap_Extended message to the UUT.
-	 */
-	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
-
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
-
-	/*
-	 * c) If a Not_Supported message is received, and Num_Fixed_Batteries
-	 *    and Num_Swappable_Battery_Slots in the VIF are 0, the test
-	 *    passes and stops here.
-	 */
-	possible[0].tx_type = TCPCI_MSG_SOP;
-	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
-	possible[0].data_msg = 0;
-
-	possible[1].tx_type = TCPCI_MSG_SOP;
-	possible[1].ctrl_msg = 0;
-	possible[1].data_msg = PD_EXT_SOURCE_CAP;
-
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
-		EC_SUCCESS, "%d");
-	if (found_index == 0) {
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		if (number_of_fixed_batteries() == 0 &&
-		    number_of_swappable_batteries() == 0)
-			return EC_SUCCESS;
-	}
-	/*
-	 * d) If the Number of Batteries/Battery Slots field in the returned
-	 *    Source_Capabilities_Extended message is 0, the test passes and
-	 *    stops here.
-	 */
-	else {
-		TEST_EQ(found_index, 1, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		if (data[HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
-			 SRC_CAP_EXT_NUM_BATTERY_OFFSET] == 0)
-			return EC_SUCCESS;
-	}
-
-	/*
-	 * e) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Battery_Status message to the UUT
-	 */
-	ext_msg = EXT_MSG_CHUNKED |
-		  EXT_MSG_DATA_SIZE_1 |
-		  GBSDB_FIXED_BATTERY_0;
-	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
-			&ext_msg);
-
-	/*
-	 * f) If a Battery_Status message is not received within
-	 *    tReceiverResponse max, the test fails. This delay is measured
-	 *    from the time the last bit of Get_Battery_Status message EOP has
-	 *    been transmitted to the time the first bit of the Battery_Status
-	 *    message preamble has been received.
-	 */
-	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP,
-					0,
-					PD_DATA_BATTERY_STATUS,
-					(15 * MSEC)),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-	task_wait_event(10 * MSEC);
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e8.c b/test/usb_tcpmv2_td_pd_src3_e8.c
deleted file mode 100644
index dee52f1753..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e8.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "driver/tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-#define BUFFER_SIZE 100
-
-#define EXT_MSG_CHUNKED BIT(15)
-#define EXT_MSG_DATA_SIZE_1 1
-
-#define HEADER_BYTE_OFFSET 1
-#define HEADER_NUM_BYTES 2
-
-#define SCEDB_NUM_BATTERY_OFFSET 22
-#define SCEDB_NUM_BYTES 24
-
-#define BSDO_NUM_BYTES 4
-#define BSDO_INV_BATTERY_REF(bsdo)	(((bsdo) >> 8) & 1)
-#define BSDO_BATTERY_PRESENT(bsdo)	(((bsdo) >> 9) & 1)
-#define BSDO_BATTERY_CHRG_STS(bsdo)	(((bsdo) >> 10) & 3)
-#define BSDO_BATTERY_INFO(bsdo)		(((bsdo) >> 8) & 0xFF)
-
-static int number_of_fixed_batteries(void)
-{
-	return CONFIG_NUM_FIXED_BATTERIES;
-}
-
-static int number_of_swappable_batteries(void)
-{
-	return 0;
-}
-
-/*****************************************************************************
- * TD.PD.SRC3.E8 Battery Status Field Checks
- *
- * Description:
- *	As Consumer (UFP), the Tester sends a Get_Battery_Status message to
- *	the UUT, verifies the UUT respond with a Battery_Status or
- *	Not_Supported message. If a Battery_Status message is received, the
- *	Tester verifies correct field values.
- */
-int test_td_pd_src3_e8(void)
-{
-	int msg_len;
-	uint8_t data[BUFFER_SIZE];
-	uint32_t ext_msg;
-	int num_fixed_batteries;
-	int num_swappable_battery_slots;
-
-	int ref;
-	int found_index;
-	struct possible_tx possible[2];
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Source_Cap_Extended message to the UUT.
-	 */
-	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
-
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
-
-	/*
-	 * c) If a Source_Capabilities_Extended message is received, the
-	 *    Tester record the Number of Batteries/Battery Slots field.
-	 */
-	possible[0].tx_type = TCPCI_MSG_SOP;
-	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
-	possible[0].data_msg = 0;
-
-	possible[1].tx_type = TCPCI_MSG_SOP;
-	possible[1].ctrl_msg = 0;
-	possible[1].data_msg = PD_EXT_SOURCE_CAP;
-
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
-		EC_SUCCESS, "%d");
-	if (found_index == 1) {
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 SCEDB_NUM_BYTES,
-			"%d");
-
-		num_fixed_batteries =
-				data[HEADER_BYTE_OFFSET +
-				     HEADER_NUM_BYTES +
-				     SCEDB_NUM_BATTERY_OFFSET] &
-				0x0F;
-		num_swappable_battery_slots =
-				(data[HEADER_BYTE_OFFSET +
-				      HEADER_NUM_BYTES +
-				      SCEDB_NUM_BATTERY_OFFSET] >> 4) &
-				0x0F;
-	}
-	/*
-	 *    If a Not_Supported message is received, the Tester reads the
-	 *    Number of Batteries/Battery Slots field (combine
-	 *    Num_Fixed_Batteries and Num_Swappable_Battery_Slots) from the
-	 *    VIF.
-	 */
-	else {
-		TEST_EQ(found_index, 0, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		num_fixed_batteries = number_of_fixed_batteries();
-		num_swappable_battery_slots = number_of_swappable_batteries();
-	}
-
-	/*
-	 * d) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Battery_Status message to the UUT, with Battery
-	 *    Status Ref set to 0 (step g includes doing d-f with Battery
-	 *    Status Ref set to 1 - 7).
-	 */
-	for (ref = 0; ref <= 7; ++ref) {
-		uint16_t header;
-		uint32_t bsdo;
-
-		ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 |
-			  (ref << 16);
-		partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
-				 &ext_msg);
-
-		/*
-		 * e) If a Battery_Status message is received, the Tester
-		 *    verifies:
-		 */
-		TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-						  PD_DATA_BATTERY_STATUS,
-						  data,
-						  sizeof(data),
-						  &msg_len,
-						  0),
-			EC_SUCCESS, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 BSDO_NUM_BYTES,
-			"%d");
-
-		/*
-		 *    1. Number of Data Objects field = 001b
-		 */
-		header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
-		TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
-
-		/*
-		 *    2. Port Power Role field = 1b (Source)
-		 */
-		TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
-
-		/*
-		 *    3. Specification Revision field = 10b (Rev 3.0)
-		 */
-		TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
-
-		/*
-		 *    4. Port Data Role field = 1b (DFP)
-		 */
-		TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
-
-		/*
-		 *    5. Extended = 0b
-		 */
-		TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
-
-		/*
-		 *    6. Invalid Battery Reference field (Bit 0) of the
-		 *       Battery Info field in the BSDO matches with the
-		 *       recorded Number of Batteries/Battery Slots field
-		 *    7. If Battery Status Ref referred to a fixed battery
-		 *       and Invalid Battery Reference field is 0, the Battery
-		 *       is present field (Bit 1) shall be 1
-		 *    8. If Invalid Battery Reference field is 1, Battery is
-		 *       present field shall be 0
-		 */
-		bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-						       HEADER_NUM_BYTES);
-
-		/* FIXED BATTERY */
-		if (ref < 4) {
-			if (ref < num_fixed_batteries) {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					0, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					1, "%d");
-			} else {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					1, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					0, "%d");
-			}
-		}
-		/* BATTERY SLOT */
-		else {
-			if ((ref - 4) < num_swappable_battery_slots) {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					0, "%d");
-			} else {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					1, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					0, "%d");
-			}
-		}
-
-		/*
-		 *    9. If Battery is present, Battery charging status
-		 *       (Bits 3..2) of Battery Info field is not 11b
-		 *   10. If Battery is not present, Bits 3..2 of Battery Info
-		 *       field is 00b
-		 *   11. Bits 7..4 of Battery Info field are 0
-		 *   12. Bits 7..0 of the BSDO are 0
-		 */
-		if (BSDO_BATTERY_PRESENT(bsdo))
-			TEST_NE(BSDO_BATTERY_CHRG_STS(bsdo), 3, "%d");
-		else
-			TEST_EQ(BSDO_BATTERY_CHRG_STS(bsdo), 0, "%d");
-
-		TEST_EQ(BSDO_BATTERY_INFO(bsdo) & GENMASK(7, 4), 0, "%d");
-		TEST_EQ(bsdo & GENMASK(7, 0), 0, "%d");
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src3_e9.c b/test/usb_tcpmv2_td_pd_src3_e9.c
deleted file mode 100644
index faeed0922d..0000000000
--- a/test/usb_tcpmv2_td_pd_src3_e9.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "driver/tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-#define BUFFER_SIZE 100
-
-#define EXT_MSG_CHUNKED BIT(15)
-#define EXT_MSG_DATA_SIZE_1 1
-
-#define HEADER_BYTE_OFFSET 1
-#define HEADER_NUM_BYTES 2
-
-#define SCEDB_NUM_BATTERY_OFFSET 22
-#define SCEDB_NUM_BYTES 24
-
-#define BSDO_INV_BATTERY_REF(bsdo)	(((bsdo) >> 8) & 1)
-#define BSDO_BATTERY_INFO(bsdo)		(((bsdo) >> 8) & 0xFF)
-
-static int number_of_fixed_batteries(void)
-{
-	return CONFIG_NUM_FIXED_BATTERIES;
-}
-
-static int number_of_swappable_batteries(void)
-{
-	return 0;
-}
-
-/*****************************************************************************
- * TD.PD.SRC3.E9 Battery Status Fields Checks - Invalid Battery reference
- *
- * Description:
- *	As Consumer (UFP), the Tester sends a Get_Battery_Status message with
- *	an invalid battery reference to the UUT, waits for a Battery_Status
- *	message from the Provider (DFP, UUT) and verifies correct field values.
- */
-int test_td_pd_src3_e9(void)
-{
-	int msg_len;
-	uint8_t data[BUFFER_SIZE];
-	uint32_t ext_msg;
-	int num_fixed_batteries;
-	int num_swappable_battery_slots;
-
-	int ref;
-	int found_index;
-	struct possible_tx possible[2];
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * b) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Source_Cap_Extended message to the UUT.
-	 */
-	TEST_EQ(proc_pd_e3(), EC_SUCCESS, "%d");
-
-	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP_EXT, 0, 0, NULL);
-
-	/*
-	 * c) If a Source_Capabilities_Extended message is received, the
-	 *    Tester record the Number of Batteries/Battery Slots field.
-	 */
-	possible[0].tx_type = TCPCI_MSG_SOP;
-	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
-	possible[0].data_msg = 0;
-
-	possible[1].tx_type = TCPCI_MSG_SOP;
-	possible[1].ctrl_msg = 0;
-	possible[1].data_msg = PD_EXT_SOURCE_CAP;
-
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
-		EC_SUCCESS, "%d");
-	if (found_index == 1) {
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 SCEDB_NUM_BYTES,
-			"%d");
-
-		num_fixed_batteries =
-				data[HEADER_BYTE_OFFSET +
-				     HEADER_NUM_BYTES +
-				     SCEDB_NUM_BATTERY_OFFSET] &
-				0x0F;
-		num_swappable_battery_slots =
-				(data[HEADER_BYTE_OFFSET +
-				      HEADER_NUM_BYTES +
-				      SCEDB_NUM_BATTERY_OFFSET] >> 4) &
-				0x0F;
-	}
-	/*
-	 *    If a Not_Supported message is received, the Tester reads the
-	 *    Number of Batteries/Battery Slots field (combine
-	 *    Num_Fixed_Batteries and Num_Swappable_Battery_Slots) from the
-	 *    VIF.
-	 */
-	else {
-		TEST_EQ(found_index, 0, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		num_fixed_batteries = number_of_fixed_batteries();
-		num_swappable_battery_slots = number_of_swappable_batteries();
-	}
-
-	/*
-	 * d) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
-	 *    sends a Get_Battery_Status message, with Battery Status Ref set
-	 *    to 8, to the UUT.
-	 */
-	ref = 8;
-	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 |
-		  (ref << 16);
-	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
-			 &ext_msg);
-
-	/*
-	 * e) If a Not_Supported message is received, and
-	 *    1. If the recorded Number of Batteries/Battery Slots field is 0,
-	 *       the test passes and stops here.
-	 *    2. If the recorded Number of Batteries/Battery Slots field is
-	 *       not 0, the test fails.
-	 */
-	possible[0].tx_type = TCPCI_MSG_SOP;
-	possible[0].ctrl_msg = PD_CTRL_NOT_SUPPORTED;
-	possible[0].data_msg = 0;
-
-	possible[1].tx_type = TCPCI_MSG_SOP;
-	possible[1].ctrl_msg = 0;
-	possible[1].data_msg = PD_DATA_BATTERY_STATUS;
-
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
-		EC_SUCCESS, "%d");
-	if (found_index == 0) {
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		TEST_EQ(num_fixed_batteries, 0, "%d");
-		TEST_EQ(num_swappable_battery_slots, 0, "%d");
-		return EC_SUCCESS;
-	}
-	/*
-	 * f) Upon receipt of the Battery_Status message, the Tester verifies:
-	 */
-	else {
-		uint16_t header;
-		uint32_t bsdo;
-
-		TEST_EQ(found_index, 1, "%d");
-		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-		task_wait_event(10 * MSEC);
-
-		/*
-		 *    1. Number of Data Objects field = 001b
-		 */
-		header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
-		TEST_EQ(PD_HEADER_CNT(header), 1, "%d");
-
-		/*
-		 *    2. Port Power Role field = 1b (Source)
-		 */
-		TEST_EQ(PD_HEADER_PROLE(header), 1, "%d");
-
-		/*
-		 *    3. Specification Revision field = 10b (Rev 3.0)
-		 */
-		TEST_EQ(PD_HEADER_REV(header), PD_REV30, "%d");
-
-		/*
-		 *    4. Port Data Role field = 1b (DFP)
-		 */
-		TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
-
-		/*
-		 *    5. Extended = 0b
-		 */
-		TEST_EQ(PD_HEADER_EXT(header), 0, "%d");
-
-		/*
-		 *    6. Invalid Battery Reference field (Bit 0) of the
-		 *       Battery Info field in the BSDO is 1
-		 */
-		bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-						       HEADER_NUM_BYTES);
-		TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
-
-		/*
-		 *    7. Bits 7..1 of Battery Info field in the BSDO are 0
-		 *    8. Bits 7..0 of the BSDO are 0
-		 */
-		TEST_EQ(BSDO_BATTERY_INFO(bsdo) & GENMASK(7, 1), 0, "%d");
-		TEST_EQ(bsdo & GENMASK(7, 0), 0, "%d");
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src_e1.c b/test/usb_tcpmv2_td_pd_src_e1.c
deleted file mode 100644
index a617f90ca2..0000000000
--- a/test/usb_tcpmv2_td_pd_src_e1.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-/*****************************************************************************
- * TD.PD.SRC.E1 Source Capabilities sent timely
- *
- * Description:
- *	As Consumer (UFP), the Tester verifies a Source Capabilities message
- *	from the Provider (DFP, UUT) is received timely
- */
-int test_td_pd_src_e1(void)
-{
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 *
-	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
-	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
-	 * there to use the timeout verify.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
-
-	/*
-	 * b) The test fails if the first bit of a Source Capabilities message
-	 *    is not received from the Provider within 250 ms (tFirstSourceCap
-	 *    max) after VBus present.
-	 */
-	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0,
-					PD_DATA_SOURCE_CAP,
-					250 * MSEC),
-		EC_SUCCESS, "%d");
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src_e2.c b/test/usb_tcpmv2_td_pd_src_e2.c
deleted file mode 100644
index f0e1b64c7e..0000000000
--- a/test/usb_tcpmv2_td_pd_src_e2.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-#define BUFFER_SIZE 100
-
-#define HEADER_BYTE_OFFSET 1
-#define HEADER_BYTE_CNT 2
-#define PDO_BYTE_CNT 4
-
-enum pd_revision {
-	REVISION_1 = 0,
-	REVISION_2 = 1,
-	REVISION_3 = 2,
-	REVISION_RESERVED = 3
-};
-
-/*****************************************************************************
- * TD.PD.SRC.E2 Source Capabilities Fields Checks
- *
- * Description:
- *	As Consumer (UFP), the Tester waits for a Source Capabilities message
- *	from the Provider (DFP,UUT) and verifies correct field values.
- */
-int test_td_pd_src_e2(void)
-{
-	int i;
-	int msg_len;
-	uint8_t data[BUFFER_SIZE];
-	uint16_t header;
-	uint16_t revision;
-	uint16_t pd_cnt;
-	uint32_t pdo;
-	uint32_t type;
-	uint32_t last_fixed_voltage = 0;
-	uint32_t last_battery_voltage = 0;
-	uint32_t last_variable_voltage = 0;
-
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 *
-	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
-	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
-	 * there to gather the actual message data.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Upon receipt of the Source Capabilities message from the
-	 *    Provider, if the Specification Revision field is 10b
-	 *    (Rev 3.0), the test passes and stops here,
-	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					  PD_DATA_SOURCE_CAP,
-					  data,
-					  sizeof(data),
-					  &msg_len,
-					  0),
-		EC_SUCCESS, "%d");
-	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
-
-	header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
-	revision = PD_HEADER_REV(header);
-	if (revision == REVISION_3)
-		return EC_SUCCESS;
-
-	/*
-	 *    otherwise the Tester verifies:
-	 *    1. Number of Data Objects field equals the number of Src_PDOs
-	 *       in the message and is not 000b.
-	 *    2. Port Power Role field = 1b (Source)
-	 *    3. Specification Revision field = 01b (Rev 2.0)
-	 *    4. Port Data Role field = 1b (DFP)
-	 *    5. Message Type field = 0001b (Source Capabilities)
-	 *    6. Bit 15 = 0b (Reserved)
-	 *    7. Bit 4 = 0b (Reserved)
-	 */
-	pd_cnt = PD_HEADER_CNT(header);
-	TEST_NE(pd_cnt, 0, "%d");
-	TEST_EQ(msg_len, HEADER_BYTE_CNT + (pd_cnt * PDO_BYTE_CNT) + 1, "%d");
-	TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d");
-	TEST_EQ(revision, REVISION_2, "%d");
-	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
-	TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d");
-	TEST_EQ(header & (BIT(4)|BIT(15)), 0, "%d");
-
-	/*
-	 * c) For the first PDO, the Tester verifies:
-	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply).
-	 *    2. Voltage field = 100 (5 V)
-	 *    3. Bits 24..22 = 000b (Reserved)
-	 */
-	pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-					      HEADER_BYTE_CNT);
-
-	type = pdo & PDO_TYPE_MASK;
-	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
-
-	last_fixed_voltage = PDO_FIXED_VOLTAGE(pdo);
-	TEST_EQ(last_fixed_voltage, 5000, "%d");
-	TEST_EQ(pdo & GENMASK(24, 22), 0, "%d");
-
-	/*
-	 * d) For the other PDOs (if any), the Tester verifies:
-	 *    1. Bits 31..30 (PDO type) are 00b (Fixed Supply), 01b (Battery),
-	 *       or 10b (Variable Supply).
-	 *    2. If Bits 31..30 are 00b, Bits 29..22 are set to 0.
-	 *    3. PDOs are in the order of Fixed Supply Objects (if present),
-	 *       Battery Supply Objects (if present) and then Variable Supply
-	 *       Objects (if present).
-	 *    4. Fixed Supply Objects (if present) are in voltage order; lowest
-	 *       to highest.
-	 *    5. Battery Supply Objects (if present) are in Minimum Voltage
-	 *       order; lowest to highest.
-	 *    6. Variable Supply Objects (if present) are in Minimum Voltage
-	 *       order; lowest to highest.
-	 */
-	for (i = 1; i < pd_cnt; ++i) {
-		int offset;
-		uint32_t voltage;
-
-		offset = HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
-			 (i * PDO_BYTE_CNT);
-		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
-
-		type = pdo & PDO_TYPE_MASK;
-		TEST_NE(type, PDO_TYPE_AUGMENTED, "%d");
-
-		if (type == PDO_TYPE_FIXED) {
-			TEST_EQ(pdo & GENMASK(29, 22), 0, "%d");
-			TEST_EQ(last_battery_voltage, 0, "%d");
-			TEST_EQ(last_variable_voltage, 0, "%d");
-			voltage = PDO_FIXED_VOLTAGE(pdo);
-			TEST_GE(voltage, last_fixed_voltage, "%d");
-			last_fixed_voltage = voltage;
-		} else if (type == PDO_TYPE_BATTERY) {
-			TEST_EQ(last_variable_voltage, 0, "%d");
-			voltage = PDO_BATT_MIN_VOLTAGE(pdo);
-			TEST_GE(voltage, last_battery_voltage, "%d");
-			last_battery_voltage = voltage;
-		} else {
-			voltage = PDO_VAR_MIN_VOLTAGE(pdo);
-			TEST_GE(voltage, last_variable_voltage, "%d");
-			last_variable_voltage = voltage;
-		}
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_src_e5.c b/test/usb_tcpmv2_td_pd_src_e5.c
deleted file mode 100644
index eac1b93e8f..0000000000
--- a/test/usb_tcpmv2_td_pd_src_e5.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-/*****************************************************************************
- * TD.PD.SRC.E5 SenderResponseTimer Timeout - Request
- *
- * Description:
- *	As Consumer (UFP), the Tester intentionally does not send the Request
- *	message, which is intended to cause a SenderResponseTimer timeout on
- *	the Provider (DFP, UUT). The Tester verifies correct implementation
- *	of this timer
- */
-int test_td_pd_src_e5(void)
-{
-	uint64_t end_time;
-
-	partner_set_pd_rev(PD_REV20);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 *
-	 * NOTE: Calling PROC.PD.E1 with INITIAL_ATTACH will stop just before
-	 * the PD_DATA_SOURCE_CAP is verified.  We need to stop the process
-	 * there to stop the REQUEST message.
-	 */
-	TEST_EQ(proc_pd_e1(PD_ROLE_DFP, INITIAL_ATTACH), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Upon receipt of the Source Capabilities message from the
-	 *    Provider, the Tester replies with a GoodCRC message.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	/* Save time GoodCRC was sent */
-	end_time = get_time().val;
-
-	/*
-	 * c) The Tester intentionally does not send a Request message and
-	 *    waits for a Hard Reset.
-	 */
-
-	/*
-	 * d) If a Hard Reset is not detected within 30 ms from the time the
-	 *    last bit of the GoodCRC message EOP has been sent, the test
-	 *    fails.
-	 * e) If a Hard Reset is detected before 24 ms from the time the
-	 *    last bit of the GoodCRC message EOP has been sent, the test
-	 *    fails.
-	 */
-	end_time += 24 * MSEC;
-	while (get_time().val < end_time) {
-		TEST_NE(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
-			TCPCI_MSG_TX_HARD_RESET, "%d");
-		task_wait_event(1 * MSEC);
-	}
-
-	end_time += 6 * MSEC;
-	while (get_time().val < end_time) {
-		if (mock_tcpci_get_reg(TCPC_REG_TRANSMIT) ==
-						TCPCI_MSG_TX_HARD_RESET)
-			break;
-		task_wait_event(1 * MSEC);
-	}
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
-		TCPCI_MSG_TX_HARD_RESET, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
-	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
-	task_wait_event(1 * MSEC);
-
-	return EC_SUCCESS;
-}
diff --git a/test/usb_tcpmv2_td_pd_vndi3_e3.c b/test/usb_tcpmv2_td_pd_vndi3_e3.c
deleted file mode 100644
index cbfc0d75e3..0000000000
--- a/test/usb_tcpmv2_td_pd_vndi3_e3.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mock/tcpci_i2c_mock.h"
-#include "task.h"
-#include "tcpm/tcpci.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_tcpmv2_compliance.h"
-#include "usb_tc_sm.h"
-
-uint32_t vdo = VDO(USB_SID_PD, 1,
-		   VDO_SVDM_VERS(VDM_VER20) |
-		   CMD_DISCOVER_IDENT);
-
-
-/*****************************************************************************
- * TD.PD.VNDI3.E3.VDM Identity
- *
- * Description:
- *	This test verifies that the VDM Information is as specified in the
- *	vendor-supplied information.
- */
-static int td_pd_vndi3_e3(enum pd_data_role data_role)
-{
-	partner_set_pd_rev(PD_REV30);
-
-	TEST_EQ(tcpci_startup(), EC_SUCCESS, "%d");
-
-	/*
-	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
-	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
-
-	/*
-	 * Make sure we are idle. Reject everything that is pending
-	 */
-	TEST_EQ(handle_attach_expected_msgs(data_role), EC_SUCCESS, "%d");
-
-	/*
-	 * b) Tester executes a Discover Identity exchange
-	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF,
-			 1, 0, &vdo);
-
-	/*
-	 * c) If the UUT is not a cable and if Responds_To_Discov_SOP is set to
-	 * No, the tester checks that the UUT replies Not_Supported.  The test
-	 * stops here in this case.
-	 */
-	TEST_EQ(verify_tcpci_transmit(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0),
-		EC_SUCCESS, "%d");
-	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
-
-	/*
-	 * TODO: Items d)-i) could be verified if the unit tests are configured
-	 * to reply to Identity messages.
-	 *
-	 * d) For Cables, the Tester checks the consistency of
-	 * Specification_Revision
-	 *
-	 * e) For all devices, the Tester checks in the ID Header consistency
-	 * of:
-	 *	1. Product_Type(UFP)
-	 *	2. Product Type(Cable Plug)
-	 *	3. Product Type (DFP)
-	 *	4. USB_VID(_SOP)
-	 *	5. Modal_Operation_Supported(_SOP)
-	 *	6. Data_Capable_as_USB_Host(_SOP)
-	 *	7. Data_Capable_as_USB_Device(_SOP)
-	 *
-	 * f) For all devices, the Tester checks in the Cert Stat VDO
-	 * consistency of:
-	 *	1. XID(_SOP)
-	 *
-	 * g) For all devices, the Tester checks in the Product VDO consistency
-	 * of:
-	 *	1. PID(_SOP)
-	 *	2. bcdDevice(_SOP)
-	 *
-	 * h) For Cables, the Tester checks in the Cable VDO consistency of:
-	 *	1. Cable_HW_Vers
-	 *	2. Cable_FW_Vers
-	 *	3. Type_C_to_Type_C_Capt_Vdm_V2
-	 *	4. Cable_Latency
-	 *	5. Cable_Termination_Type
-	 *	6. Max_VBUS_Voltage_Vdm_V2
-	 *	7. Cable_VBUS_Current
-	 *	8. VBUS_through_cable
-	 *	9. Cable_SOP''_controller
-	 *	10. Cable_Superspeed_Support
-	 *
-	 * i) For Alt Mode Adapters, the Tester checks in the AMA VDO
-	 * consistency of:
-	 *	1. AMA_HW_Vers
-	 *	2. AMA_FW_Vers
-	 *	3. AMA_VCONN_power
-	 *	4. AMA_VCONN_reqd
-	 *	5. AMA_VBUS_reqd
-	 *	6. AMA_Superspeed_Support
-	 */
-	return EC_SUCCESS;
-}
-int test_td_pd_vndi3_e3_dfp(void)
-{
-	return td_pd_vndi3_e3(PD_ROLE_DFP);
-}
-int test_td_pd_vndi3_e3_ufp(void)
-{
-	return td_pd_vndi3_e3(PD_ROLE_UFP);
-}
diff --git a/test/usb_test/Makefile b/test/usb_test/Makefile
deleted file mode 100644
index e18e4a7c3b..0000000000
--- a/test/usb_test/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-PROGRAM := device_configuration
-SOURCE  := $(PROGRAM).c
-LIBS    :=
-LFLAGS  :=
-CFLAGS  := -std=gnu99 \
-	-g3 \
-	-O3 \
-        -Wall \
-        -Werror \
-        -Wpointer-arith \
-        -Wcast-align \
-        -Wcast-qual \
-        -Wundef \
-        -Wsign-compare \
-        -Wredundant-decls \
-        -Wmissing-declarations
-
-#
-# Add libusb-1.0 required flags
-#
-LIBS    += $(shell pkg-config --libs   libusb-1.0)
-CFLAGS  += $(shell pkg-config --cflags libusb-1.0)
-
-$(PROGRAM): $(SOURCE) Makefile
-	gcc $(CFLAGS) $(SOURCE) $(LFLAGS) $(LIBS) -o $@
-
-.PHONY: clean
-
-clean:
-	rm -rf $(PROGRAM) *~
diff --git a/test/usb_test/README b/test/usb_test/README
deleted file mode 100644
index 5d7af93f7e..0000000000
--- a/test/usb_test/README
+++ /dev/null
@@ -1,2 +0,0 @@
-These tests need to be built and run by hand, unless/until we set up a lab
-with known devices attached to a test host.
diff --git a/test/usb_test/device_configuration.c b/test/usb_test/device_configuration.c
deleted file mode 100644
index 69f889c2d3..0000000000
--- a/test/usb_test/device_configuration.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <getopt.h>
-#include <libusb.h>
-#include <stdarg.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5014;			/* Cr50 */
-
-static char *progname;
-
-static void usage(int errs)
-{
-	printf("\nUsage: %s [vid:pid] [value]\n"
-	       "\n"
-	       "Set/Get the USB Device Configuration value\n"
-	       "\n"
-	       "The default vid:pid is %04x:%04x\n"
-	       "\n", progname, vid, pid);
-
-	exit(!!errs);
-}
-
-/* Globals */
-struct libusb_device_handle *devh = 0;
-
-static void stupid_usb(const char *format, ...)
-{
-	va_list ap;
-
-	va_start(ap, format);
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-
-	if (devh)
-		libusb_close(devh);
-
-	libusb_exit(NULL);
-
-	exit(1);
-}
-
-
-int main(int argc, char *argv[])
-{
-	int r = 1;
-	int errorcnt = 0;
-	int do_set = 0;
-	uint16_t setval = 0;
-	uint8_t buf[80];			/* Arbitrary size */
-	int i;
-
-	progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;				/* quiet, you */
-	while ((i = getopt(argc, argv, "")) != -1) {
-		switch (i) {
-		case 'h':
-			usage(errorcnt);
-			break;
-		case 0:				/* auto-handled option */
-			break;
-		case '?':
-			if (optopt)
-				printf("Unrecognized option: -%c\n", optopt);
-			else
-				printf("Unrecognized option: %s\n",
-				       argv[optind - 1]);
-			errorcnt++;
-			break;
-		case ':':
-			printf("Missing argument to %s\n", argv[optind - 1]);
-			errorcnt++;
-			break;
-		default:
-			printf("Internal error at %s:%d\n", __FILE__, __LINE__);
-			exit(1);
-		}
-	}
-
-	if (errorcnt)
-		usage(errorcnt);
-
-	if (optind < argc) {
-		uint16_t v, p;
-
-		if (2 == sscanf(argv[optind], "%hx:%hx", &v, &p)) {
-			vid = v;
-			pid = p;
-			optind++;
-		}
-	}
-
-	if (optind < argc) {
-		do_set = 1;
-		setval = atoi(argv[optind]);
-	}
-
-	r = libusb_init(NULL);
-	if (r) {
-		printf("libusb_init() returned 0x%x: %s\n",
-		       r, libusb_error_name(r));
-		return 1;
-	}
-
-	devh = libusb_open_device_with_vid_pid(NULL, vid, pid);
-	if (!devh) {
-		perror(progname);
-		stupid_usb("Can't open device %04x:%04x\n", vid, pid);
-	}
-
-
-	/* Set config*/
-	if (do_set) {
-		printf("SetCfg %d\n", setval);
-		r = libusb_control_transfer(
-			devh,
-			0x00,			/* bmRequestType */
-			0x09,			/* bRequest */
-			setval,			/* wValue */
-			0x0000,			/* wIndex */
-			NULL,			/* data */
-			0x0000,			/* wLength */
-			1000);			/* timeout (ms) */
-
-		if (r < 0)
-			printf("transfer returned 0x%x %s\n",
-			       r, libusb_error_name(r));
-	}
-
-	/* Get config */
-	memset(buf, 0, sizeof(buf));
-
-	r = libusb_control_transfer(
-		devh,
-		0x80,				/* bmRequestType */
-		0x08,				/* bRequest */
-		0x0000,				/* wValue */
-		0x0000,				/* wIndex */
-		buf,				/* data */
-		0x0001,				/* wLength */
-		1000);				/* timeout (ms) */
-
-	if (r <= 0)
-		stupid_usb("GetCfg transfer() returned 0x%x %s\n",
-			   r, libusb_error_name(r));
-
-	printf("GetCfg returned %d bytes:", r);
-	for (i = 0; i < r; i++)
-		printf(" 0x%02x", buf[i]);
-	printf("\n");
-
-	/* done */
-	if (devh)
-		libusb_close(devh);
-	libusb_exit(NULL);
-
-	return 0;
-}
diff --git a/test/usb_typec_ctvpd.c b/test/usb_typec_ctvpd.c
deleted file mode 100644
index 52c8be0639..0000000000
--- a/test/usb_typec_ctvpd.c
+++ /dev/null
@@ -1,1542 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Type-C VPD and CTVPD module.
- */
-#include "common.h"
-#include "crc.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_sm.h"
-#include "usb_tc_sm.h"
-#include "util.h"
-#include "usb_pd_tcpm.h"
-#include "usb_pd_test_util.h"
-#include "usb_sm_checks.h"
-#include "vpd_api.h"
-
-#define PORT0	0
-
-enum cc_type {CC1, CC2};
-enum vbus_type {VBUS_0 = 0, VBUS_5 = 5000};
-enum vconn_type {VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000};
-enum snk_con_voltage_type {SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0};
-
-/*
- * These enum definitions are declared in usb_tc_*_sm and are private to that
- * file. If those definitions are re-ordered, then we need to update these
- * definitions (should be very rare).
- */
-enum usb_tc_state {
-	/* Normal States */
-	TC_DISABLED,
-	TC_UNATTACHED_SNK,
-	TC_ATTACH_WAIT_SNK,
-	TC_ATTACHED_SNK,
-	TC_ERROR_RECOVERY,
-	TC_TRY_SNK,
-	TC_UNATTACHED_SRC,
-	TC_ATTACH_WAIT_SRC,
-	TC_TRY_WAIT_SRC,
-	TC_ATTACHED_SRC,
-	TC_CT_TRY_SNK,
-	TC_CT_ATTACH_WAIT_UNSUPPORTED,
-	TC_CT_ATTACHED_UNSUPPORTED,
-	TC_CT_UNATTACHED_UNSUPPORTED,
-	TC_CT_UNATTACHED_VPD,
-	TC_CT_DISABLED_VPD,
-	TC_CT_ATTACHED_VPD,
-	TC_CT_ATTACH_WAIT_VPD,
-};
-
-/* Defined in implementation */
-enum usb_tc_state get_state_tc(const int port);
-
-struct pd_port_t {
-	int host_mode;
-	int has_vbus;
-	int msg_tx_id;
-	int msg_rx_id;
-	int polarity;
-	int partner_role; /* -1 for none */
-	int partner_polarity;
-	int rev;
-} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-uint64_t wait_for_state_change(int port, uint64_t timeout)
-{
-	uint64_t start;
-	uint64_t wait;
-	enum usb_tc_state state = get_state_tc(port);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-
-	wait = get_time().val + timeout;
-	start = get_time().val;
-	while (get_state_tc(port) == state && get_time().val < wait) {
-		task_wake(PD_PORT_TO_TASK_ID(port));
-		task_wait_event(1 * MSEC);
-	}
-
-	return get_time().val - start;
-}
-
-#if defined(TEST_USB_TYPEC_CTVPD)
-static int ct_connect_sink(enum cc_type cc, enum snk_con_voltage_type v)
-{
-	int ret;
-
-	switch (v) {
-	case SRC_CON_DEF:
-		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV);
-		break;
-	case SRC_CON_1_5:
-		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV);
-		break;
-	case SRC_CON_3_0:
-		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV);
-		break;
-	default:
-		ret = 0;
-	}
-
-	return ret;
-}
-
-static int ct_disconnect_sink(void)
-{
-	int r1;
-	int r2;
-
-	r1 = mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_VNC_MV);
-	r2 = mock_set_cc2_rp3a0_rd_l(PD_SRC_DEF_VNC_MV);
-
-	return r1 & r2;
-}
-
-static int ct_connect_source(enum cc_type cc, enum vbus_type vbus)
-{
-	mock_set_ct_vbus(vbus);
-	return (cc) ? mock_set_cc2_rpusb_odh(PD_SNK_VA_MV) :
-				mock_set_cc1_rpusb_odh(PD_SNK_VA_MV);
-}
-
-static int ct_disconnect_source(void)
-{
-	int r1;
-	int r2;
-
-	mock_set_ct_vbus(VBUS_0);
-	r1 = mock_set_cc1_rpusb_odh(0);
-	r2 = mock_set_cc2_rpusb_odh(0);
-
-	return r1 & r2;
-}
-#endif
-
-static void host_disconnect_source(void)
-{
-	mock_set_host_vbus(VBUS_0);
-	mock_set_host_cc_source_voltage(0);
-	mock_set_host_cc_sink_voltage(0);
-}
-
-static void host_connect_source(enum vbus_type vbus)
-{
-	mock_set_host_vbus(vbus);
-	mock_set_host_cc_source_voltage(PD_SNK_VA_MV);
-}
-
-#if defined(TEST_USB_TYPEC_CTVPD)
-static void host_connect_sink(enum snk_con_voltage_type v)
-{
-	switch (v) {
-	case SRC_CON_DEF:
-		mock_set_host_cc_sink_voltage(PD_SRC_DEF_RD_THRESH_MV);
-		break;
-	case SRC_CON_1_5:
-		mock_set_host_cc_sink_voltage(PD_SRC_1_5_RD_THRESH_MV);
-		break;
-	case SRC_CON_3_0:
-		mock_set_host_cc_sink_voltage(PD_SRC_3_0_RD_THRESH_MV);
-		break;
-	}
-}
-#endif
-
-static void init_port(int port)
-{
-	pd_port[port].polarity = 0;
-	pd_port[port].rev = PD_REV30;
-	pd_port[port].msg_tx_id = 0;
-	pd_port[port].msg_rx_id = 0;
-}
-
-static int check_host_ra_rd(void)
-{
-	/* Make sure CC_RP3A0_RD_L is configured as GPO */
-	if (mock_get_cfg_cc_rp3a0_rd_l() != PIN_GPO)
-		return 0;
-
-	/* Make sure CC_RP3A0_RD_L is asserted low */
-	if (mock_get_cc_rp3a0_rd_l() != 0)
-		return 0;
-
-	/* Make sure VPDMCU_CC_EN is enabled */
-	if (mock_get_mcu_cc_en() != 1)
-		return 0;
-
-	/* Make sure CC_VPDMCU is configured as ADC */
-	if (mock_get_cfg_cc_vpdmcu() != PIN_ADC)
-		return 0;
-
-	/* Make sure CC_DB_EN_OD is HZ */
-	if (mock_get_cc_db_en_od() != GPO_HZ)
-		return 0;
-
-	return 1;
-}
-
-static int check_host_rd(void)
-{
-	/* Make sure CC_RP3A0_RD_L is configured as GPO */
-	if (mock_get_cfg_cc_rp3a0_rd_l() != PIN_GPO)
-		return 0;
-
-	/* Make sure CC_RP3A0_RD_L is asserted low */
-	if (mock_get_cc_rp3a0_rd_l() != 0)
-		return 0;
-
-	/* Make sure VPDMCU_CC_EN is enabled */
-	if (mock_get_mcu_cc_en() != 1)
-		return 0;
-
-	/* Make sure CC_VPDMCU is configured as ADC */
-	if (mock_get_cfg_cc_vpdmcu() != PIN_ADC)
-		return 0;
-
-	/* Make sure CC_DB_EN_OD is LOW */
-	if (mock_get_cc_db_en_od() != GPO_LOW)
-		return 0;
-
-	return 1;
-}
-
-#if defined(TEST_USB_TYPEC_CTVPD)
-static int check_host_rp3a0(void)
-{
-	/* Make sure CC_RP3A0_RD_L is asserted high */
-	if (mock_get_cc_rp3a0_rd_l() != 1)
-		return 0;
-
-	return 1;
-}
-
-static int check_host_rpusb(void)
-{
-	/* Make sure CC_RPUSB_ODH is asserted high */
-	if (mock_get_cc_rpusb_odh() != 1)
-		return 0;
-
-	/* Make sure CC_RP3A0_RD_L is configured as comparator */
-	if (mock_get_cfg_cc_rp3a0_rd_l() != PIN_CMP)
-		return 0;
-
-	return 1;
-}
-
-static int check_host_cc_open(void)
-{
-	/* Make sure CC_RPUSB_ODH is hi-z */
-	if (mock_get_cc_rpusb_odh() != GPO_HZ)
-		return 0;
-
-	/* Make sure CC_RP3A0_RD_L is set to comparitor */
-	if (mock_get_cfg_cc_rp3a0_rd_l() != PIN_CMP)
-		return 0;
-
-	/* Make sure cc_db_en_od is set low */
-	if (mock_get_cc_db_en_od() != GPO_LOW)
-		return 0;
-
-	return 1;
-}
-
-static int check_ct_ccs_hz(void)
-{
-	return (mock_get_ct_rd() == GPO_HIGH);
-}
-
-static int check_ct_ccs_rd(void)
-{
-	return (mock_get_ct_rd() == GPO_LOW);
-}
-
-static int check_ct_ccs_cc1_rpusb(void)
-{
-	return (mock_get_ct_cc1_rpusb() == 1);
-}
-#endif
-
-void inc_tx_id(int port)
-{
-	pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) % 7;
-}
-
-void inc_rx_id(int port)
-{
-	pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7;
-}
-
-static int verify_goodcrc(int port, int role, int id)
-{
-	return pd_test_tx_msg_verify_sop_prime(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
-}
-
-static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
-{
-	int i;
-
-	pd_test_rx_set_preamble(port, 1);
-	pd_test_rx_msg_append_sop_prime(port);
-	pd_test_rx_msg_append_short(port, header);
-
-	crc32_init();
-	crc32_hash16(header);
-
-	for (i = 0; i < cnt; ++i) {
-		pd_test_rx_msg_append_word(port, data[i]);
-		crc32_hash32(data[i]);
-	}
-
-	pd_test_rx_msg_append_word(port, crc32_result());
-
-	pd_test_rx_msg_append_eop(port);
-	pd_test_rx_msg_append_last_edge(port);
-
-	pd_simulate_rx(port);
-}
-
-static void simulate_goodcrc(int port, int role, int id)
-{
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-						pd_port[port].rev, 0), 0, NULL);
-}
-
-static void simulate_discovery_identity(int port)
-{
-	uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE,
-					0, pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 0);
-	uint32_t msg = VDO(USB_SID_PD,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_INIT) |
-			CMD_DISCOVER_IDENT);
-
-	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
-}
-
-static int test_vpd_host_src_detection(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host is configured properly and start state is UNATTACHED_SNK
-	 */
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	/*
-	 * TEST:
-	 * Host PORT Source Connection Detected
-	 */
-
-	host_connect_source(VBUS_0);
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	/*
-	 * TEST:
-	 * Host CC debounce in ATTACH_WAIT_SNK state
-	 */
-
-	host_disconnect_source();
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(5 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host CC debounce in ATTACH_WAIT_SNK state
-	 */
-
-	host_connect_source(VBUS_0);
-	mock_set_vconn(VCONN_0);
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(50 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host Port Connection Removed
-	 */
-	host_disconnect_source();
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	return EC_SUCCESS;
-}
-
-static int test_vpd_host_src_detection_vbus(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host is configured properly and start state is UNATTACHED_SNK
-	 */
-
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	/*
-	 * TEST:
-	 * Host Port Source Connection Detected
-	 */
-
-	host_connect_source(VBUS_0);
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	/*
-	 * TEST:
-	 * Host Port Source Detected for tCCDebounce and Host Port VBUS
-	 * Detected.
-	 */
-
-	host_connect_source(VBUS_5);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-
-	/*
-	 * TEST:
-	 * Host Port VBUS Removed
-	 */
-
-	host_connect_source(VBUS_0);
-
-	/*
-	 * The state changes from UNATTACHED_SNK to ATTACH_WAIT_SNK immediately
-	 * if Rp is detected.
-	 */
-	wait_for_state_change(port, 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	return EC_SUCCESS;
-}
-
-static int test_vpd_host_src_detection_vconn(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host is configured properly and start state is UNATTACHED_SNK
-	 */
-
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	/*
-	 * TEST:
-	 * Host Source Connection Detected
-	 */
-
-	host_connect_source(VBUS_0);
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	/*
-	 * TEST:
-	 * Host Port Source Detected for tCCDebounce and VCONN Detected
-	 */
-
-	host_connect_source(VBUS_0);
-	mock_set_vconn(VCONN_3);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-
-	/* VCONN was detected. Make sure RA is removed */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-	TEST_ASSERT(check_host_rd());
-
-	/*
-	 * TEST:
-	 * Host Port VCONN Removed
-	 */
-
-	mock_set_host_cc_source_voltage(0);
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 10 * MSEC);
-
-	TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d");
-
-	host_disconnect_source();
-
-	return EC_SUCCESS;
-}
-
-static int test_vpd_host_src_detection_message_reception(void)
-{
-	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
-			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
-			USB_VID_GOOGLE);
-	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
-	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-						VPD_VBUS_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-						VPD_GND_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						: VPD_CTS_NOT_SUPPORTED);
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * TEST:
-	 * Host is configured properly and start state is UNATTACHED_SNK
-	 */
-
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	/*
-	 * Transition to ATTACHED_SNK
-	 */
-
-	host_connect_source(VBUS_5);
-
-	wait_for_state_change(port, 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 20 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-
-	/* Run state machines to enable rx monitoring */
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/*
-	 * TEST:
-	 * Reception of Discovery Identity message
-	 */
-
-	simulate_discovery_identity(port);
-	task_wait_event(30 * MSEC);
-
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_rx_id(port);
-
-	/* Test Discover Identity Ack */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_product));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_vpd));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-
-	/* Ack was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(30 * MSEC);
-	inc_tx_id(port);
-
-	/*
-	 * TEST:
-	 * Host Port VBUS Removed
-	 */
-
-	host_disconnect_source();
-
-	wait_for_state_change(port, 100 * MSEC);
-
-	TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d");
-
-
-	return EC_SUCCESS;
-}
-
-#if defined(TEST_USB_TYPEC_CTVPD)
-static int test_ctvpd_behavior_case1(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 1: The following tests the behavior when a DRP is connected to a
-	 *	 Charge-Through VCONN-Powered USB Device (abbreviated CTVPD),
-	 *	 with no Power Source attached to the ChargeThrough port on
-	 *	 the CTVPD.
-	 */
-
-	/* 1. DRP and CTVPD are both in the unattached state */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	/*
-	 *   a. DRP alternates between Unattached.SRC and Unattached.SNK
-	 *
-	 *   b. CTVPD has applied Rd on its Charge-Through port’s CC1 and CC2
-	 *   pins and Rd on the Host-side port’s CC pin
-	 */
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(check_ct_ccs_rd());
-
-	/*
-	 * 2. DRP transitions from Unattached.SRC to AttachWait.SRC to
-	 *    Attached.SRC
-	 *
-	 *    a. DRP in Unattached.SRC detects the CC pull-down of CTVPD which
-	 *       is in Unattached.SNK and DRP enters AttachWait.SRC
-	 *    b. DRP in AttachWait.SRC detects that pull down on CC persists for
-	 *       tCCDebounce, enters Attached.SRC and turns on VBUS and VCONN
-	 */
-	host_connect_source(VBUS_5);
-	mock_set_vconn(VCONN_3);
-
-	/*
-	 * 3. CTVPD transitions from Unattached.SNK to Attached.SNK through
-	 *    AttachWait.SNK.
-	 *
-	 *    a. CTVPD detects the host-side CC pull-up of the DRP and CTVPD
-	 *       enters AttachWait.SNK
-	 *    b. CTVPD in AttachWait.SNK detects that pull up on the Host-side
-	 *       port’s CC persists for tCCDebounce, VCONN present and enters
-	 *       Attached.SNK
-	 *    c. CTVPD present a high-impedance to ground (above zOPEN) on its
-	 *       Charge-Through port’s CC1 and CC2 pins
-	 */
-	wait_for_state_change(port, 40 * MSEC);
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-	TEST_ASSERT(check_ct_ccs_hz());
-
-	/*
-	 * 4. While DRP and CTVPD are in their respective attached states, DRP
-	 *    discovers the ChargeThrough CTVPD and transitions to
-	 *    CTUnattached.SNK
-	 *
-	 *    a. DRP (as Source) queries the device identity via USB PD
-	 *       (Device Identity Command) on SOP’.
-	 *    b. CTVPD responds on SOP’, advertising that it is a
-	 *       Charge-Through VCONN-Powered USB Device
-	 *    c. DRP (as Source) removes VBUS
-	 *    d. DRP (as Source) changes its Rp to a Rd
-	 *    e. DRP (as Sink) continues to provide VCONN and enters
-	 *       CTUnattached.SNK
-	 */
-	host_disconnect_source();
-
-	/*
-	 * 5. CTVPD transitions to CTUnattached.VPD
-	 *
-	 *    a. CTVPD detects VBUS removal, VCONN presence, the low Host-side
-	 *       CC pin and enters CTUnattached.VPD
-	 *    b. CTVPD changes its host-side Rd to a Rp advertising 3.0 A
-	 *    c. CTVPD isolates itself from VBUS
-	 *    d. CTVPD apply Rd on its Charge-Through port’s CC1 and CC2 pins
-	 */
-	wait_for_state_change(port, 40 * MSEC);
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-
-	/*
-	 * 6. While the CTVPD in CTUnattached.VPD state and the DRP in
-	 *    CTUnattached.SNK state:
-	 *
-	 *    a. CTVPD monitors Charge-Though CC pins for a source or sink;
-	 *       when a Power Source attach is detected, enters
-	 *       CTAttachWait.VPD; when a sink is detected, enters
-	 *       CTAttachWait.Unsupported
-	 *    b. CTVPD monitors VCONN for Host detach and when detected, enters
-	 *       Unattached.SNK
-	 *    c. DRP monitors VBUS and CC for CTVPD detach for tVPDDetach and
-	 *       when detected, enters Unattached.SNK
-	 *    d. DRP monitors VBUS for Power Source attach and when detected,
-	 *       enters CTAttached.SNK
-	 */
-	/* Attach Power Source */
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_0));
-
-	wait_for_state_change(port, 40 * MSEC);
-	TEST_EQ(get_state_tc(port), TC_CT_ATTACH_WAIT_VPD, "%d");
-
-	/* Remove Power Source */
-	TEST_ASSERT(ct_disconnect_source());
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_EQ(get_state_tc(port), TC_CT_UNATTACHED_VPD, "%d");
-
-	/* Attach Sink */
-	TEST_ASSERT(ct_connect_sink(CC1, SRC_CON_DEF));
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_EQ(get_state_tc(port), TC_CT_ATTACH_WAIT_UNSUPPORTED, "%d");
-
-	/* Remove VCONN (Host detach) */
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_ctvpd_behavior_case2(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 2: The following tests the behavior when a Power Source is
-	 *	 connected to a Charge-Through VCONN-Powered USB Device
-	 *	 (abbreviated CTVPD), with a Host already attached to the
-	 *	 Host-Side port on the CTVPD.
-	 */
-
-	/*
-	 * 1. DRP is in CTUnattached.SNK state, CTVPD in CTUnattached.VPD, and
-	 *    Power Source in the unattached state
-	 *
-	 *    a. CTVPD has applied Rd on the Charge-Through port’s CC1 and CC2
-	 *       pins and Rp termination advertising 3.0 A on the Host-side
-	 *       port’s CC pin
-	 */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	host_connect_source(VBUS_5);
-	mock_set_vconn(VCONN_3);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-
-	/* Remove Host CC */
-	mock_set_host_cc_source_voltage(0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_rp3a0());
-
-	/*
-	 * 2. Power Source transitions from Unattached.SRC to Attached.SRC
-	 *    through AttachWait.SRC.
-	 *
-	 *    a. Power Source detects the CC pull-down of the CTVPD and enters
-	 *       AttachWait.SRC
-	 *    b. Power Source in AttachWait.SRC detects that pull down on CC
-	 *       persists for tCCDebounce, enters Attached.SRC and turns on
-	 *       VBUS
-	 */
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_5));
-
-	/*
-	 * 3. CTVPD transitions from CTUnattached.VPD through CTAttachWait.VPD
-	 *    to CTAttached.VPD
-	 *
-	 *    a. CTVPD detects the Source’s Rp on one of its Charge-Through CC
-	 *       pins, and transitions to CTAttachWait.VPD
-	 *    b. CTVPD finishes any active USB PD communication on SOP’ and
-	 *       ceases to respond to SOP’ queries
-	 *    c. CTVPD in CTAttachWait.VPD detects that the pull up on
-	 *       Charge-Through CC pin persists for tCCDebounce, detects VBUS
-	 *       and enters CTAttached.VPD
-	 *    d. CTVPD connects the active Charge-Through CC pin to the
-	 *       Host-side port’s CC pin
-	 *    e. CTVPD disables its Rp termination advertising 3.0 A on the
-	 *       Host-side port’s CC pin
-	 *    f. CTVPD disables its Rd on the Charge-Through CC pins
-	 *    g. CTVPD connects VBUS from the Charge-Through side to the Host
-	 *       side
-	 */
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_ATTACH_WAIT_VPD);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_ATTACHED_VPD);
-	TEST_ASSERT(moch_get_ct_cl_sel() == CT_CC2);
-	TEST_ASSERT(check_host_cc_open());
-	TEST_ASSERT(check_ct_ccs_hz());
-	TEST_ASSERT(mock_get_vbus_pass_en());
-
-	/*
-	 * 4. DRP (as Sink) transitions to CTAttached.SNK
-	 *    a. DRP (as Sink) detects VBUS, monitors vRd for available current
-	 *       and enter CTAttached.SNK
-	 */
-
-	/*
-	 * 5. While the devices are all in their respective attached states:
-	 *    a. CTVPD monitors VCONN for DRP detach and when detected,
-	 *       enters CTDisabled.VPD
-	 *    b. CTVPD monitors VBUS and CC for Power Source detach and when
-	 *       detected, enters CTUnattached.VPD within tVPDCTDD
-	 *    c. DRP (as Sink) monitors VBUS for Charge-Through Power Source
-	 *       detach and when detected, enters CTUnattached.SNK
-	 *    d. DRP (as Sink) monitors VBUS and CC for CTVPD detach and when
-	 *       detected, enters Unattached.SNK (and resumes toggling between
-	 *       Unattached.SNK and Unattached.SRC)
-	 *    e. Power Source monitors CC for CTVPD detach and when detected,
-	 *       enters Unattached.SRC
-	 */
-	mock_set_vconn(VCONN_0);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_DISABLED_VPD);
-
-	return EC_SUCCESS;
-}
-
-static int test_ctvpd_behavior_case3(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 3: The following describes the behavior when a Power Source is
-	 *	 connected to a ChargeThrough VCONN-Powered USB Device
-	 *	 (abbreviated CTVPD), with no Host attached to the Host-side
-	 *	 port on the CTVPD.
-	 */
-
-	/*
-	 * 1. CTVPD and Power Source are both in the unattached state
-	 *    a. CTVPD has applied Rd on the Charge-Through port’s CC1 and CC2
-	 *       pins and Rd on the Host-side port’s CC pin
-	 */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_ra_rd());
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_5));
-
-	/*
-	 * 2. Power Source transitions from Unattached.SRC to Attached.SRC
-	 *    through AttachWait.SRC.
-	 *
-	 *    a. Power Source detects the CC pull-down of the CTVPD and enters
-	 *       AttachWait.SRC
-	 *    b. Power Source in AttachWait.SRC detects that pull down on CC
-	 *       persists for tCCDebounce, enters Attached.SRC and turns on
-	 *       VBUS
-	 */
-
-	/* 3. CTVPD alternates between Unattached.SNk and Unattached.SRC
-	 *
-	 *    a. CTVPD detects the Source’s Rp on one of its Charge-Through CC
-	 *       pins, detects VBUS for tCCDebounce and starts alternating
-	 *       between Unattached.SRC and Unattached.SNK
-	 */
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SRC);
-
-	/*
-	 * 4. While the CTVPD alternates between Unattached.SRC and
-	 *    Unattached.SNK state and the Power Source in Attached.SRC state:
-	 *
-	 *    a. CTVPD monitors the Host-side port’s CC pin for device attach
-	 *       and when detected, enters AttachWait.SRC
-	 *    b. CTVPD monitors VBUS for Power Source detach and when detected,
-	 *       enters Unattached.SNK
-	 *    c. Power Source monitors CC for CTVPD detach and when detected,
-	 *       enters Unattached.SRC
-	 */
-
-	/* Attached host side device */
-	host_connect_sink(SRC_CON_DEF);
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SRC);
-
-	/* Remove VBUS */
-	TEST_ASSERT(ct_disconnect_source());
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	return EC_SUCCESS;
-}
-
-static int test_ctvpd_behavior_case4(void)
-{
-	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
-			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
-			USB_VID_GOOGLE);
-	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
-	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-						VPD_VBUS_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-						VPD_GND_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						: VPD_CTS_NOT_SUPPORTED);
-
-	init_port(port);
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 4: The following describes the behavior when a DRP is connected
-	 *	 to a Charge-Through VCONN-Powered USB Device
-	 *	 (abbreviated CTVPD), with a Power Source already attached to
-	 *	 the Charge-Through side on the CTVPD.
-	 */
-
-	/*
-	 * 1. DRP, CTVPD and Sink are all in the unattached state
-	 *
-	 *    a. DRP alternates between Unattached.SRC and Unattached.SNK
-	 *    b. CTVPD has applied Rd on its Charge-Through port’s CC1 and CC2
-	 *       pins and Rd on the Host-side port’s CC pin
-	 */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_ra_rd());
-
-	/*
-	 * 2. DRP transitions from Unattached.SRC to AttachWait.SRC to
-	 *    Attached.SRC
-	 *
-	 *    a. DRP in Unattached.SRC detects the CC pull-down of CTVPD which
-	 *       is in Unattached.SNK and DRP enters AttachWait.SRC
-	 *    b. DRP in AttachWait.SRC detects that pull down on CC persists
-	 *       for tCCDebounce, enters Attached.SRC and turns on VBUS and
-	 *       VCONN
-	 */
-
-	host_connect_source(VBUS_5);
-	mock_set_vconn(VCONN_3);
-
-	/*
-	 * 3. CTVPD transitions from Unattached.SNK to Attached.SNK through
-	 *    AttachWait.SNK.
-	 *
-	 *    a. CTVPD detects the host-side CC pull-up of the DRP and CTVPD
-	 *       enters AttachWait.SNK
-	 *    b. CTVPD in AttachWait.SNK detects that pull up on the
-	 *       Host-side port’s CC persists for tCCDebounce, VCONN present
-	 *       and enters Attached.SNK
-	 *    c. CTVPD present a high-impedance to ground (above zOPEN) on its
-	 *       Charge-Through port’s CC1 and CC2 pins
-	 */
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-	TEST_ASSERT(check_ct_ccs_hz());
-
-	/*
-	 * 4. While DRP and CTVPD are in their respective attached states, DRP
-	 *    discovers the ChargeThrough CTVPD and transitions to
-	 *    CTUnattached.SNK
-	 *
-	 *    a. DRP (as Source) queries the device identity via USB PD
-	 *       (Discover Identity Command) on SOP’.
-	 *    b. CTVPD responds on SOP’, advertising that it is a
-	 *       Charge-Through VCONN-Powered USB Device
-	 *    c. DRP (as Source) removes VBUS
-	 *    d. DRP (as Source) changes its Rp to a Rd
-	 *    e. DRP (as Sink) continues to provide VCONN and enters
-	 *       CTUnattached.SNK
-	 */
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	simulate_discovery_identity(port);
-	task_wait_event(40 * MSEC);
-
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-	inc_rx_id(port);
-
-	/* Test Discover Identity Ack */
-	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_product));
-	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_vpd));
-	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/* Ack was good. Send GoodCRC */
-	simulate_goodcrc(port, PD_ROLE_SOURCE, pd_port[port].msg_tx_id);
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-	inc_tx_id(port);
-
-	/*
-	 * 5. CTVPD transitions to CTUnattached.VPD
-	 *
-	 *    a. CTVPD detects VBUS removal, VCONN presence, the low Host-side
-	 *       CC pin and enters CTUnattached.VPD
-	 *    b. CTVPD changes its host-side Rd to a Rp termination advertising
-	 *       3.0 A
-	 *    c. CTVPD isolates itself from VBUS
-	 *    d. CTVPD apply Rd on its Charge-Through port’s CC1 and CC2 pins
-	 */
-	host_disconnect_source();
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_rp3a0());
-
-	/*
-	 * 6. CTVPD alternates between CTUnattached.VPD and
-	 *    CTUnattached.Unsupported
-	 */
-	wait_for_state_change(port, PD_T_DRP_SRC + 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_UNSUPPORTED);
-
-	wait_for_state_change(port, PD_T_DRP_SRC + 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_5));
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_ATTACH_WAIT_VPD);
-
-	return EC_SUCCESS;
-}
-
-static int test_ctvpd_behavior_case5(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 5: The following describes the behavior when a Power Source is
-	 *	 connected to a ChargeThrough VCONN-Powered USB Device
-	 *	 (abbreviated CTVPD), with a DRP (with dead battery) attached
-	 *	 to the Host-side port on the CTVPD.
-	 */
-
-	/*
-	 * 1. DRP, CTVPD and Power Source are all in the unattached state
-	 *
-	 *    a. DRP apply dead battery Rd
-	 *    b. CTVPD apply Rd on the Charge-Through port’s CC1 and CC2 pins
-	 *       and Rd on the Host-side port’s CC pin
-	 */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_ra_rd());
-
-	/*
-	 * 2. Power Source transitions from Unattached.SRC to Attached.SRC
-	 *    through AttachWait.SRC.
-	 *
-	 *    a. Power Source detects the CC pull-down of the CTVPD and enters
-	 *       AttachWait.SRC
-	 *    b. Power Source in AttachWait.SRC detects that pull down on CC
-	 *       persists for tCCDebounce, enters Attached.SRC and enable VBUS
-	 */
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_5));
-
-	/*
-	 * 3. CTVPD alternates between Unattached.SNK and Unattached.SRC
-	 *
-	 *    a. CTVPD detects the Source’s Rp on one of its Charge-Through CC
-	 *       pins, detects VBUS for tCCDebounce and starts alternating
-	 *       between Unattached.SRC and Unattached.SNK
-	 */
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SRC);
-
-	/* Connect Host With Dead Battery */
-	host_connect_sink(SRC_CON_DEF);
-
-	/*
-	 * 4. CTVPD transitions from Unattached.SRC to Try.SNK through
-	 *    AttachWait.SRC
-	 *
-	 *    a. CTVPD in Unattached.SRC detects the CC pull-down of DRP which
-	 *       is in Unattached.SNK and CTVPD enters AttachWait.SRC
-	 *    b. CTVPD in AttachWait.SRC detects that pull down on CC persists
-	 *       for tCCDebounce and enters Try.SNK
-	 *    c. CTVPD disables Rp termination advertising Default USB Power on
-	 *       the Host-side port’s CC
-	 *    d. CTVPD enables Rd on the Host-side port’s CC
-	 */
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SRC);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 10 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_TRY_SNK);
-	TEST_ASSERT(check_host_ra_rd());
-
-	/* 5. DRP in dead battery condition remains in Unattached.SNK */
-
-	/*
-	 * 6. CTVPD transitions from Try.SNK to Attached.SRC through
-	 *    TryWait.SRC
-	 *
-	 *    a. CTVPD didn’t detect the CC pull-up of the DRP for
-	 *       tTryDebounce after tDRPTry and enters TryWait.SRC
-	 *    b. CTVPD disables Rd on the Host-side port’s CC
-	 *    c. CTVPD enables Rp termination advertising Default USB Power on
-	 *       the Host-side port’s CC
-	 *    d. CTVPD detects the CC pull-down of the DRP for tTryCCDebounce
-	 *       and enters Attached.SRC
-	 *    e. CTVPD connects VBUS from the Charge-Through side to the Host
-	 *       side
-	 */
-	wait_for_state_change(port, PD_T_TRY_CC_DEBOUNCE +
-						PD_T_DRP_TRY + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_TRY_WAIT_SRC);
-	TEST_ASSERT(check_host_rpusb());
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SRC);
-	TEST_ASSERT(mock_get_vbus_pass_en());
-
-	/*
-	 * 7. DRP transitions from Unattached.SNK to Attached.SNK through
-	 *    AttachWait.SNK
-	 *
-	 *    a. DRP in Unattached.SNK detects the CC pull-up of CTVPD which is
-	 *       in Attached.SRC and DRP enters AttachWait.SNK
-	 *    b. DRP in AttachWait.SNK detects that pull up on CC persists for
-	 *       tCCDebounce, VBUS present and enters Attached.SNK
-	 */
-
-	/*
-	 * 8. While the devices are all in their respective attached states:
-	 *    a. CTVPD monitors the Host-side port’s CC pin for device attach
-	 *       and when detected, enters Unattached.SNK
-	 *    b. CTVPD monitors VBUS for Power Source detach and when detected,
-	 *       enters Unattached.SNK
-	 *    c. Power Source monitors CC for CTVPD detach and when detected,
-	 *       enters Unattached.SRC
-	 *    d. DRP monitors VBUS for CTVPD detach and when detected, enters
-	 *       Unattached.SNK
-	 *    e. Additionally, the DRP may query the identity of the cable via
-	 *       USB PD on SOP’ when it has sufficient battery power and when
-	 *       a Charge-Through VPD is identified enters TryWait.SRC if
-	 *       implemented, or enters Unattached.SRC if TryWait.SRC is not
-	 *       supported
-	 */
-	TEST_ASSERT(ct_connect_source(CC2, VBUS_0));
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-
-	return EC_SUCCESS;
-}
-
-static int test_ctvpd_behavior_case6(void)
-{
-	int port = PORT0;
-
-	mock_set_vconn(VCONN_0);
-	host_disconnect_source();
-	TEST_ASSERT(ct_disconnect_source());
-	TEST_ASSERT(ct_disconnect_sink());
-
-	task_wake(PD_PORT_TO_TASK_ID(port));
-	task_wait_event(40 * MSEC);
-
-	/*
-	 * CASE 6: The following describes the behavior when a DRP is connected
-	 *	 to a Charge-Through VCONN-Powered USB Device
-	 *	 (abbreviated CTVPD) and a Sink is attached to the
-	 *	 Charge-Through port on the CTVPD.
-	 */
-
-	/*
-	 * 1. DRP, CTVPD and Sink are all in the unattached state
-	 *
-	 *    a. DRP alternates between Unattached.SRC and Unattached.SNK
-	 *    b. CTVPD has applied Rd on its Charge-Through port’s CC1 and CC2
-	 *       pins and Rd on the Host-side port’s CC pin
-	 */
-	TEST_ASSERT(get_state_tc(port) == TC_UNATTACHED_SNK);
-	TEST_ASSERT(check_ct_ccs_rd());
-	TEST_ASSERT(check_host_ra_rd());
-
-	/*
-	 * 2. DRP transitions from Unattached.SRC to AttachWait.SRC to
-	 *    Attached.SRC
-	 *
-	 *    a. DRP in Unattached.SRC detects the CC pull-down of CTVPD which
-	 *       is in Unattached.SNK and DRP enters AttachWait.SRC
-	 *    b. DRP in AttachWait.SRC detects that pull down on CC persists
-	 *       for tCCDebounce, enters Attached.SRC and turns on VBUS and
-	 *       VCONN
-	 */
-	host_connect_source(VBUS_5);
-	mock_set_vconn(VCONN_3);
-
-	/*
-	 * 3. CTVPD transitions from Unattached.SNK to Attached.SNK through
-	 *    AttachWait.SNK.
-	 *
-	 *    a. CTVPD detects the host-side CC pull-up of the DRP and CTVPD
-	 *       enters AttachWait.SNK
-	 *    b. CTVPD in AttachWait.SNK detects that pull up on the Host-side
-	 *       port’s CC persists for tCCDebounce, VCONN present and enters
-	 *       Attached.SNK
-	 *    c. CTVPD present a high-impedance to ground (above zOPEN) on its
-	 *       Charge-Through port’s CC1 and CC2 pins
-	 */
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACH_WAIT_SNK);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_ATTACHED_SNK);
-	TEST_ASSERT(check_ct_ccs_hz());
-
-	/*
-	 * 4. While DRP and CTVPD are in their respective attached states, DRP
-	 *    discovers the ChargeThrough CTVPD and transitions to
-	 *    CTUnattached.SNK
-	 *
-	 *    a. DRP (as Source) queries the device identity via USB PD
-	 *       (Discover Identity Command) on SOP’.
-	 *    b. CTVPD responds on SOP’, advertising that it is a
-	 *       Charge-Through VCONN-Powered USB Device
-	 *    c. DRP (as Source) removes VBUS
-	 *    d. DRP (as Source) changes its Rp to a Rd
-	 *    e. DRP (as Sink) continues to provide VCONN and enters
-	 *       CTUnattached.SNK
-	 */
-
-	host_disconnect_source();
-	host_connect_sink(SRC_CON_DEF);
-
-	/*
-	 * 5. CTVPD transitions to CTUnattached.VPD
-	 *
-	 *    a. CTVPD detects VBUS removal, VCONN presence, the low Host-side
-	 *       CC pin and enters CTUnattached.VPD
-	 *    b. CTVPD changes its host-side Rd to a Rp termination advertising
-	 *       3.0 A
-	 *    c. CTVPD isolates itself from VBUS
-	 *    d. CTVPD apply Rd on its Charge-Through port’s CC1 and CC2 pins
-	 */
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-	TEST_ASSERT(check_host_rp3a0());
-	TEST_ASSERT(mock_get_vbus_pass_en() == 0);
-	TEST_ASSERT(check_ct_ccs_rd());
-
-	/*
-	 * 6. CTVPD alternates between CTUnattached.VPD and
-	 *    CTUnattached.Unsupported
-	 *
-	 *    a. CTVPD detects SRC.open on its Charge-Through CC pins and
-	 *       starts alternating between CTUnattached.VPD and
-	 *       CTUnattached.Unsupported
-	 */
-	wait_for_state_change(port, PD_T_DRP_SNK + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_UNSUPPORTED);
-
-	wait_for_state_change(port, PD_T_DRP_SNK + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-
-	wait_for_state_change(port, PD_T_DRP_SNK + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_UNSUPPORTED);
-
-	/*
-	 * 7. CTVPD transitions from CTUnattached.Unsupported to CTTry.SNK
-	 *    through CTAttachWait.Unsupported
-	 *
-	 *    a. CTVPD in CTUnattached.Unsupported detects the CC pull-down of
-	 *       the Sink which is in Unattached.SNK and CTVPD enters
-	 *       CTAttachWait.Unsupported
-	 *    b. CTVPD in CTAttachWait.Unsupported detects that pull down on CC
-	 *       persists for tCCDebounce and enters CTTry.SNK
-	 *    c. CTVPD disables Rp termination advertising Default USB Power on
-	 *       the ChargeThrough port’s CC pins
-	 *    d. CTVPD enables Rd on the Charge-Through port’s CC pins
-	 */
-	TEST_ASSERT(ct_connect_sink(CC1, SRC_CON_DEF));
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_ATTACH_WAIT_UNSUPPORTED);
-
-	wait_for_state_change(port, PD_T_CC_DEBOUNCE + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_TRY_SNK);
-	TEST_ASSERT(check_ct_ccs_rd());
-
-	/*
-	 * 8. CTVPD transitions from CTTry.SNK to CTAttached.Unsupported
-	 *
-	 *    a. CTVPD didn’t detect the CC pull-up of the potential Source
-	 *       for tDRPTryWait after tDRPTry and enters
-	 *       CTAttached.Unsupported
-	 */
-
-	wait_for_state_change(port, PD_T_DRP_TRY + PD_T_TRY_WAIT + 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED);
-
-	/*
-	 * 9. While the CTVPD in CTAttached.Unsupported state, the DRP in
-	 *    CTUnattached.SNK state and the Sink in Unattached.SNK state:
-	 *
-	 *    a. CTVPD disables the Rd termination on the Charge-Through
-	 *       port’s CC pins and applies Rp termination advertising
-	 *       Default USB Power
-	 *    b. CTVPD exposes a USB Billboard Device Class to the DRP
-	 *       indicating that it is connected to an unsupported device on
-	 *       its Charge Through port
-	 *    c. CTVPD monitors Charge-Though CC pins for Sink detach and when
-	 *       detected, enters CTUnattached.VPD
-	 *    d. CTVPD monitors VCONN for Host detach and when detected, enters
-	 *       Unattached.SNK
-	 *    e. DRP monitors CC for CTVPD detach for tVPDDetach and when
-	 *       detected, enters Unattached.SNK
-	 *    f. DRP monitors VBUS for CTVPD Charge-Through source attach and,
-	 *       when detected, enters CTAttached.SNK
-	 */
-
-	TEST_ASSERT(check_ct_ccs_cc1_rpusb());
-	TEST_ASSERT(mock_get_present_billboard() == BB_SNK);
-
-	TEST_ASSERT(ct_disconnect_sink());
-
-	wait_for_state_change(port, 40 * MSEC);
-
-	TEST_ASSERT(get_state_tc(port) == TC_CT_UNATTACHED_VPD);
-
-	return EC_SUCCESS;
-}
-#endif
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	init_port(PORT0);
-
-	/* VPD and CTVPD tests */
-	RUN_TEST(test_vpd_host_src_detection);
-	RUN_TEST(test_vpd_host_src_detection_vbus);
-	RUN_TEST(test_vpd_host_src_detection_vconn);
-	RUN_TEST(test_vpd_host_src_detection_message_reception);
-
-	/* CTVPD only tests */
-#if defined(TEST_USB_TYPEC_CTVPD)
-	/* DRP to VCONN-Powered USB Device (CTVPD) Behavior Tests */
-	RUN_TEST(test_ctvpd_behavior_case1);
-	RUN_TEST(test_ctvpd_behavior_case2);
-	RUN_TEST(test_ctvpd_behavior_case3);
-	RUN_TEST(test_ctvpd_behavior_case4);
-	RUN_TEST(test_ctvpd_behavior_case5);
-	RUN_TEST(test_ctvpd_behavior_case6);
-#endif
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_tc_no_parent_cycles);
-	RUN_TEST(test_tc_all_states_named);
-
-	/*
-	 * Since you have to include TypeC layer when adding PE layer, the
-	 * PE test would have the same build dependencies, so go ahead and test
-	 * te PE statemachine here so we don't have to create another test exe
-	 */
-	RUN_TEST(test_pe_no_parent_cycles);
-	RUN_TEST(test_pe_all_states_named);
-
-	test_print_result();
-}
-
diff --git a/test/usb_typec_ctvpd.tasklist b/test/usb_typec_ctvpd.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_typec_ctvpd.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_typec_drp_acc_trysrc.c b/test/usb_typec_drp_acc_trysrc.c
deleted file mode 100644
index 96ed5601b7..0000000000
--- a/test/usb_typec_drp_acc_trysrc.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test USB Type-C Dual Role Port, Audio Accessory, and Try.SRC Device module.
- */
-#include "charge_manager.h"
-#include "mock/tcpc_mock.h"
-#include "mock/usb_mux_mock.h"
-#include "system.h"
-#include "task.h"
-#include "test_util.h"
-#include "timer.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usb_sm_checks.h"
-#include "usb_tc_sm.h"
-
-#define PORT0 0
-
-/*
- * Amount of time to wait after a specified timeout. Allows for an extra loop
- * through statemachine plus 1000 calls to clock
- */
-#define FUDGE (6 * MSEC)
-
-/* Unreachable time in future */
-#define TIMER_DISABLED 0xffffffffffffffff
-
-/* Install Mock TCPC and MUX drivers */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.drv = &mock_tcpc_driver,
-	},
-};
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
-void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
-{
-	/* Do Nothing, but needed for linking */
-}
-
-void pd_resume_check_pr_swap_needed(int port)
-{
-	/* Do Nothing, but needed for linking */
-}
-
-/* Vbus is turned on at the board level, so mock it here for our purposes */
-static bool board_vbus_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-static bool mock_get_vbus_enabled(int port)
-{
-	return board_vbus_enabled[port];
-}
-
-static void mock_set_vbus_enabled(int port, bool enabled)
-{
-	board_vbus_enabled[port] = enabled;
-}
-
-static void mock_reset_vbus_enabled(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		mock_set_vbus_enabled(i, false);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	mock_set_vbus_enabled(port, true);
-	return EC_SUCCESS;
-}
-
-void pd_power_supply_reset(int port)
-{
-	mock_set_vbus_enabled(port, false);
-}
-
-__maybe_unused static int test_mux_con_dis_as_src(void)
-{
-	mock_tcpc.should_print_call = false;
-	mock_usb_mux.num_set_calls = 0;
-
-	/* Update CC lines send state machine event to process */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RD;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-	pd_set_dual_role(0, PD_DRP_TOGGLE_ON);
-
-	/* This wait trainsitions through AttachWait.SRC then Attached.SRC */
-	task_wait_event(SECOND);
-
-	/* We are in Attached.SRC now */
-	TEST_EQ(mock_usb_mux.state, USB_PD_MUX_USB_ENABLED, "%d");
-	TEST_EQ(mock_usb_mux.num_set_calls, 1, "%d");
-
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* This wait will go through TryWait.SNK then to Unattached.SNK */
-	task_wait_event(10 * SECOND);
-
-	/* We are in Unattached.SNK. The mux should have detached */
-	TEST_EQ(mock_usb_mux.state, USB_PD_MUX_NONE, "%d");
-	TEST_EQ(mock_usb_mux.num_set_calls, 2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_mux_con_dis_as_snk(void)
-{
-	mock_tcpc.should_print_call = false;
-	mock_usb_mux.num_set_calls = 0;
-
-	/*
-	 * we expect a PD-capable partner to be able to check below
-	 * whether it is data capable.
-	 */
-	tc_pd_connection(0, 1);
-
-	/* Update CC lines send state machine event to process */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* This wait will go through AttachWait.SNK to Attached.SNK */
-	task_wait_event(5 * SECOND);
-
-	/*
-	 * We are in Attached.SNK now, but the port partner isn't data capable
-	 * so we should not connect the USB data mux.
-	 */
-	TEST_EQ(mock_usb_mux.state, USB_PD_MUX_NONE, "%d");
-
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.vbus_level = 0;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* This wait will go through TryWait.SNK then to Unattached.SNK */
-	task_wait_event(10 * SECOND);
-
-	/* We are in Unattached.SNK. The mux should have detached */
-	TEST_EQ(mock_usb_mux.state, USB_PD_MUX_NONE, "%d");
-	TEST_LE(mock_usb_mux.num_set_calls, 2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_power_role_set(void)
-{
-	mock_tcpc.num_calls_to_set_header = 0;
-
-	/*
-	 * We need to allow auto toggling to see the port partner attach
-	 * as a sink
-	 */
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_ON);
-
-	/* Update CC lines send state machine event to process */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RD;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-	task_wait_event(10 * SECOND);
-
-	/* We are in Attached.SRC now */
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SOURCE, "%d");
-	TEST_EQ(mock_tcpc.last.data_role, PD_ROLE_DFP, "%d");
-
-	/*
-	 * We allow 2 separate calls to update the header since power and data
-	 * role updates can be separate calls depending on the state is came
-	 * from.
-	 */
-	TEST_LE(mock_tcpc.num_calls_to_set_header, 2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc1_default(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-DEF on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.vbus_level = 1;
-
-	/*
-	 * In this test we are expecting value of polarity, which is set by
-	 * default for tcpc mock. Initialize it with something else, in order
-	 * to catch possible errors.
-	 */
-	mock_tcpc.last.polarity = POLARITY_COUNT;
-
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc1_1A5(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-1A5 on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc1_3A0(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-3A0 on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc2_default(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-DEF on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc2_1A5(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-1A5 on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_cc2_3A0(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC USB-3A0 on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc1_default(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-Default on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc1_1A5(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-1A5 on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc1_3A0(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-1A5 on CC1");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc2_default(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-Default on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc2_1A5(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-1A5 on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_1_5;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_polarity_dts_cc2_3A0(void)
-{
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC DTS-1A5 on CC2");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RP_DEF;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE + FUDGE);
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2_DTS, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Record any calls that would change our CCs to Rp */
-static int changes_to_rp;
-static int record_changes_to_rp(int port, int pull)
-{
-	if (pull == TYPEC_CC_RP)
-		++changes_to_rp;
-
-	return EC_SUCCESS;
-};
-
-__maybe_unused static int test_try_src_disabled(void)
-{
-	changes_to_rp = 0;
-	mock_tcpc.callbacks.set_cc = &record_changes_to_rp;
-	tc_try_src_override(TRY_SRC_OVERRIDE_OFF);
-
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Wait a long time past many potential transitions */
-	task_wait_event(10 * SECOND);
-
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RD, "%d");
-	TEST_EQ(changes_to_rp, 0, "%d");
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SINK, "%d");
-	TEST_EQ(mock_tcpc.last.data_role, PD_ROLE_UFP, "%d");
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Act like a PD device that switches to opposite role */
-static int switch_to_opposite_role(int port, int pull)
-{
-	static enum tcpc_cc_pull last_pull = -1;
-
-	if (pull == last_pull)
-		return EC_SUCCESS;
-
-	last_pull = pull;
-
-	if (pull == TYPEC_CC_RP) {
-		/* If host is setting Rp, then CCs will negotiate as SNK */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_RD;
-		mock_tcpc.vbus_level = 0;
-		ccprints("[Test] Partner presents SNK");
-	} else if (pull == TYPEC_CC_RD) {
-		/* If host is setting Rd, then CCs will negotiate as SRC */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-		mock_tcpc.vbus_level = 1;
-		ccprints("[Test] Partner presents SRC with Vbus ON");
-	}
-
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	return EC_SUCCESS;
-};
-
-__maybe_unused static int test_try_src_partner_switches(void)
-{
-	mock_tcpc.callbacks.set_cc = &switch_to_opposite_role;
-	tc_try_src_override(TRY_SRC_OVERRIDE_ON);
-
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* We are in AttachWait.SNK now */
-	/* Before tCCDebounce elapses, we should still be a SNK */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RD, "%d");
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-
-	/* We are in Try.SRC now */
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RP, "%d");
-
-	/* Wait for tCCDebounce to elapse, then should be SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE);
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SOURCE, "%d");
-	TEST_EQ(mock_tcpc.last.data_role, PD_ROLE_DFP, "%d");
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-	TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Act like a non-PD charger that always presents Vbus and Rp lines */
-static int dumb_src_charger_cc_response(int port, int pull)
-{
-	static enum tcpc_cc_pull last_pull = -1;
-
-	if (pull == last_pull)
-		return EC_SUCCESS;
-
-	last_pull = pull;
-
-	if (pull == TYPEC_CC_RP) {
-		/* If host is setting Rp, then CCs will open */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	} else if (pull == TYPEC_CC_RD) {
-		/* If host is setting Rd, then CCs will negotiate */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	}
-	mock_tcpc.vbus_level = 1;
-
-	ccprints("[Test] Partner presents SRC with Vbus ON");
-
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	return EC_SUCCESS;
-};
-
-__maybe_unused static int test_try_src_partner_does_not_switch_vbus(void)
-{
-	tc_try_src_override(TRY_SRC_OVERRIDE_ON);
-	mock_tcpc.callbacks.set_cc = &dumb_src_charger_cc_response;
-
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* We are in AttachWait.SNK now */
-	/* Before tCCDebounce elapses, we should still be a SNK */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RD, "%d");
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-
-	/* We are in Try.SRC now */
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RP, "%d");
-
-	/*
-	 * Wait for tTryTimeout to elapse, then should be
-	 * presenting SNK resistors again but not connected yet, until we
-	 * debounce Vbus.
-	 */
-	task_wait_event(PD_T_TRY_TIMEOUT);
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SINK, "%d");
-	TEST_EQ(tc_is_attached_snk(PORT0), false, "%d");
-
-	/* Once we debouce Vbus, then we should be connected */
-	task_wait_event(PD_T_CC_DEBOUNCE);
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SINK, "%d");
-	TEST_EQ(mock_tcpc.last.data_role, PD_ROLE_UFP, "%d");
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Act like a PD charger that will drop Vbus when CC lines are open */
-static int src_charger_drops_vbus_cc_response(int port, int pull)
-{
-	static enum tcpc_cc_pull last_pull = -1;
-
-	if (pull == last_pull)
-		return EC_SUCCESS;
-
-	last_pull = pull;
-
-	if (pull == TYPEC_CC_RP) {
-		/* If host is setting Rp, then CCs will open */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.vbus_level = 0;
-		ccprints("[Test] Partner presents SRC with Vbus OFF");
-	} else if (pull == TYPEC_CC_RD) {
-		/* If host is setting Rd, then CCs will negotiate */
-		mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-		mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-		mock_tcpc.vbus_level = 1;
-		ccprints("[Test] Partner presents SRC with Vbus ON");
-	}
-
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	return EC_SUCCESS;
-};
-
-__maybe_unused static int test_try_src_partner_does_not_switch_no_vbus(void)
-{
-	tc_try_src_override(TRY_SRC_OVERRIDE_ON);
-	mock_tcpc.callbacks.set_cc = &src_charger_drops_vbus_cc_response;
-
-	/* Update CC lines send state machine event to process */
-	ccprints("[Test] Partner connects as SRC");
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* We are in AttachWait.SNK now */
-	/* Before tCCDebounce elapses, we should still be a SNK */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RD, "%d");
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-
-	/* We are in Try.SRC now */
-	/* Before tCCDebounce elapses, we should SRC */
-	task_wait_event(PD_T_CC_DEBOUNCE / 2);
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RP, "%d");
-
-	/*
-	 * Wait for tTryTimeout to elapse, then should be
-	 * presenting SNK resistors again but not connected yet, until we
-	 * debounce Vbus.
-	 */
-	task_wait_event(PD_T_DRP_TRY);
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SINK, "%d");
-	TEST_EQ(tc_is_attached_snk(PORT0), false, "%d");
-
-	/* Once we debouce Vbus, then we should be connected */
-	task_wait_event(PD_T_CC_DEBOUNCE);
-	TEST_EQ(mock_tcpc.last.power_role, PD_ROLE_SINK, "%d");
-	TEST_EQ(mock_tcpc.last.data_role, PD_ROLE_UFP, "%d");
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC2, "%d");
-	TEST_EQ(tc_is_attached_snk(PORT0), true, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Record the cc voltages */
-static enum tcpc_cc_pull cc_pull[16];
-static int cc_pull_count;
-static int record_cc_pull(int port, int pull)
-{
-	if (cc_pull_count < ARRAY_SIZE(cc_pull))
-		cc_pull[cc_pull_count++] = pull;
-
-	return EC_SUCCESS;
-};
-
-__maybe_unused static int test_cc_open_on_normal_reset(void)
-{
-	uint32_t flags = system_get_reset_flags();
-
-	cc_pull_count = 0;
-	mock_tcpc.callbacks.set_cc = &record_cc_pull;
-
-	system_clear_reset_flags(EC_RESET_FLAG_POWER_ON);
-
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
-	task_wait_event(SECOND * 10);
-
-	/* Ensure that the first CC set call was to open (error recovery). */
-	TEST_GT(cc_pull_count, 0, "%d");
-	TEST_EQ(cc_pull[0], TYPEC_CC_OPEN, "%d");
-
-	/* Ensure that the second CC set call was to Rd (sink) */
-	TEST_GT(cc_pull_count, 1, "%d");
-	TEST_EQ(cc_pull[1], TYPEC_CC_RD, "%d");
-
-	/* Reset system flags after test */
-	system_set_reset_flags(flags);
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_cc_rd_on_por_reset(void)
-{
-	uint32_t flags = system_get_reset_flags();
-
-	cc_pull_count = 0;
-	mock_tcpc.callbacks.set_cc = &record_cc_pull;
-
-	system_set_reset_flags(EC_RESET_FLAG_POWER_ON);
-
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
-	task_wait_event(SECOND * 10);
-
-	/* Ensure that the first CC set call was to Rd (sink) */
-	TEST_GT(cc_pull_count, 0, "%d");
-	TEST_EQ(cc_pull[0], TYPEC_CC_RD, "%d");
-
-	/* Reset system flags after test */
-	system_clear_reset_flags(~flags);
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_auto_toggle_delay(void)
-{
-	uint64_t time;
-
-	/* Start with auto toggle disabled so we can time the transition */
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_OFF);
-	task_wait_event(SECOND);
-
-	/* Enabled auto toggle and start the timer for the transition */
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_ON);
-	time = get_time().val;
-
-	/*
-	 * Ensure we do not transition to auto toggle from Rd or Rp in less time
-	 * than tDRP minimum (50 ms) * dcSRC.DRP minimum (30%) = 15 ms.
-	 * Otherwise we can confuse external partners with the first transition
-	 * to auto toggle.
-	 */
-	task_wait_event(SECOND);
-	TEST_GT(mock_tcpc.first_call_to_enable_auto_toggle - time,
-		(uint64_t)15 * MSEC, "%" PRIu64);
-
-	return EC_SUCCESS;
-}
-
-__maybe_unused static int test_auto_toggle_delay_early_connect(void)
-{
-	cc_pull_count = 0;
-	mock_tcpc.callbacks.set_cc = &record_cc_pull;
-	mock_tcpc.first_call_to_enable_auto_toggle = TIMER_DISABLED;
-
-	/* Start with auto toggle disabled */
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_OFF);
-	task_wait_event(SECOND);
-
-	/* Enabled auto toggle */
-	pd_set_dual_role(PORT0, PD_DRP_TOGGLE_ON);
-
-	/* Wait less than tDRP_SNK(40ms) and tDRP_SRC(30ms) */
-	task_wait_event(MIN(PD_T_DRP_SNK, PD_T_DRP_SRC) - (10 * MSEC));
-
-	/* Have partner connect as SRC */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_RP_3_0;
-	mock_tcpc.vbus_level = 1;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* Ensure the auto toggle enable was never called */
-	task_wait_event(SECOND);
-	TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle,
-		TIMER_DISABLED, "%" PRIu64);
-
-	/* Ensure that the first CC set call was to Rd. */
-	TEST_GT(cc_pull_count, 0, "%d");
-	TEST_EQ(cc_pull[0], TYPEC_CC_RD, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* TODO(b/153071799): test as SNK monitor for Vbus disconnect (not CC line) */
-__maybe_unused static int test_typec_dis_as_src(void)
-{
-	mock_tcpc.should_print_call = false;
-
-	/* Update CC lines send state machine event to process */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_RD;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-	pd_set_dual_role(0, PD_DRP_TOGGLE_ON);
-
-	/* This wait trainsitions through AttachWait.SRC then Attached.SRC */
-	task_wait_event(SECOND);
-
-	/*
-	 * We are in Attached.SRC now, verify:
-	 * - Vbus was turned on
-	 * - Rp is set
-	 * - polarity is detected as CC1
-	 * - Rp was set to default configured level
-	 */
-	TEST_EQ(mock_tcpc.last.cc, TYPEC_CC_RP, "%d");
-	TEST_EQ(mock_tcpc.last.polarity, POLARITY_CC1, "%d");
-	TEST_EQ(mock_tcpc.last.rp, CONFIG_USB_PD_PULLUP, "%d");
-	TEST_EQ(mock_get_vbus_enabled(0), true, "%d");
-
-	/* Force a detach through CC open */
-	mock_tcpc.cc1 = TYPEC_CC_VOLT_OPEN;
-	mock_tcpc.cc2 = TYPEC_CC_VOLT_OPEN;
-	task_set_event(TASK_ID_PD_C0, PD_EVENT_CC);
-
-	/* This wait will go through TryWait.SNK then to Unattached.SNK */
-	task_wait_event(10 * SECOND);
-
-	/* We are in Unattached.SNK. Verify Vbus has been removed */
-	TEST_EQ(mock_get_vbus_enabled(0), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-/* Reset the mocks before each test */
-void before_test(void)
-{
-	mock_usb_mux_reset();
-	mock_tcpc_reset();
-	mock_reset_vbus_enabled();
-
-	/* Restart the PD task and let it settle */
-	task_set_event(TASK_ID_PD_C0, TASK_EVENT_RESET_DONE);
-	task_wait_event(SECOND);
-
-	/* Print out TCPC calls for easier debugging */
-	mock_tcpc.should_print_call = true;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_polarity_cc1_default);
-	RUN_TEST(test_polarity_cc1_1A5);
-	RUN_TEST(test_polarity_cc1_3A0);
-
-	RUN_TEST(test_polarity_cc2_default);
-	RUN_TEST(test_polarity_cc2_1A5);
-	RUN_TEST(test_polarity_cc2_3A0);
-
-	RUN_TEST(test_polarity_dts_cc1_default);
-	RUN_TEST(test_polarity_dts_cc1_1A5);
-	RUN_TEST(test_polarity_dts_cc1_3A0);
-
-	RUN_TEST(test_polarity_dts_cc2_default);
-	RUN_TEST(test_polarity_dts_cc2_1A5);
-	RUN_TEST(test_polarity_dts_cc2_3A0);
-
-	RUN_TEST(test_mux_con_dis_as_src);
-	RUN_TEST(test_mux_con_dis_as_snk);
-	RUN_TEST(test_power_role_set);
-
-	RUN_TEST(test_typec_dis_as_src);
-
-	RUN_TEST(test_try_src_disabled);
-	RUN_TEST(test_try_src_partner_switches);
-	RUN_TEST(test_try_src_partner_does_not_switch_vbus);
-	RUN_TEST(test_try_src_partner_does_not_switch_no_vbus);
-
-	RUN_TEST(test_cc_open_on_normal_reset);
-	RUN_TEST(test_cc_rd_on_por_reset);
-	RUN_TEST(test_auto_toggle_delay);
-	RUN_TEST(test_auto_toggle_delay_early_connect);
-
-	/* Do basic state machine validity checks last. */
-	RUN_TEST(test_tc_no_parent_cycles);
-	RUN_TEST(test_tc_all_states_named);
-
-	test_print_result();
-}
diff --git a/test/usb_typec_drp_acc_trysrc.mocklist b/test/usb_typec_drp_acc_trysrc.mocklist
deleted file mode 100644
index 71c2e2cee9..0000000000
--- a/test/usb_typec_drp_acc_trysrc.mocklist
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- #define CONFIG_TEST_MOCK_LIST  \
-	MOCK(USB_MUX)           \
-	MOCK(TCPC)
diff --git a/test/usb_typec_drp_acc_trysrc.tasklist b/test/usb_typec_drp_acc_trysrc.tasklist
deleted file mode 100644
index eb41326e3e..0000000000
--- a/test/usb_typec_drp_acc_trysrc.tasklist
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TEST_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST \
-	TASK_TEST(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/test/usb_typec_vpd.tasklist b/test/usb_typec_vpd.tasklist
deleted file mode 120000
index 3e39415ded..0000000000
--- a/test/usb_typec_vpd.tasklist
+++ /dev/null
@@ -1 +0,0 @@
-usb_typec_ctvpd.tasklist
\ No newline at end of file
diff --git a/test/utils.c b/test/utils.c
deleted file mode 100644
index 7fe27b4549..0000000000
--- a/test/utils.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test common utilities.
- */
-
-#include "common.h"
-#include "console.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-static int test_memmove(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 101, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 100, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len);
-
-	/* Expected about 4x speed gain. Use 3x because it fluctuates */
-	if (!IS_ENABLED(EMU_BUILD)) {
-		/*
-		 * The speed gain is too unpredictable on host, especially on
-		 * buildbots. Skip it if we are running in the emulator.
-		 */
-		int expected_speedup = 3;
-
-		if (IS_ENABLED(CHIP_FAMILY_STM32H7))
-			expected_speedup = 2;
-
-		TEST_ASSERT((t1.val - t0.val) >
-			    (unsigned int)(t3.val - t2.val) * expected_speedup);
-	}
-
-	/* Test small moves */
-	memmove(buf + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1);
-	memmove(buf + 5, buf, 4);
-	memmove(buf + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memcpy(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int dest_offset = 500;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset + 1, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len);
-
-	/* Expected about 4x speed gain. Use 3x because it fluctuates */
-#ifndef EMU_BUILD
-	/*
-	 * The speed gain is too unpredictable on host, especially on
-	 * buildbots. Skip it if we are running in the emulator.
-	 */
-	TEST_ASSERT((t1.val-t0.val) > (unsigned)(t3.val-t2.val) * 3);
-#endif
-
-	memcpy(buf + dest_offset + 1, buf + 1, len - 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1);
-
-	/* Test small copies */
-	memcpy(buf + dest_offset, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1);
-	memcpy(buf + dest_offset, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4);
-	memcpy(buf + dest_offset + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1);
-	memcpy(buf + dest_offset + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-/* Plain memset, used as a reference to measure speed gain */
-static void *dumb_memset(void *dest, int c, int len)
-{
-	char *d = (char *)dest;
-	while (len > 0) {
-		*(d++) = c;
-		len--;
-	}
-	return dest;
-}
-
-static int test_memset(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		dumb_memset(buf, 1, len);
-	t1 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memset(buf, 1, len);
-	t3 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-
-	/*
-	 * Expected about 4x speed gain. Use smaller value since it
-	 * fluctuates.
-	 */
-	if (!IS_ENABLED(EMU_BUILD)) {
-		/*
-		 * The speed gain is too unpredictable on host, especially on
-		 * buildbots. Skip it if we are running in the emulator.
-		 */
-		int expected_speedup = 3;
-
-		if (IS_ENABLED(CHIP_FAMILY_STM32F4) ||
-		    IS_ENABLED(CHIP_FAMILY_STM32H7))
-			expected_speedup = 2;
-
-		TEST_ASSERT((t1.val - t0.val) >
-			    (unsigned int)(t3.val - t2.val) * expected_speedup);
-	}
-
-	memset(buf, 128, len);
-	TEST_ASSERT_MEMSET(buf, (char)128, len);
-
-	memset(buf, -2, len);
-	TEST_ASSERT_MEMSET(buf, (char)-2, len);
-
-	memset(buf + 1, 1, len - 2);
-	TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memchr(void)
-{
-	char *buf = "1234";
-
-	TEST_ASSERT(memchr("123567890", '4', 8) == NULL);
-	TEST_ASSERT(memchr("123", '3', 2) == NULL);
-	TEST_ASSERT(memchr(buf, '3', 4) == buf + 2);
-	TEST_ASSERT(memchr(buf, '4', 4) == buf + 3);
-	return EC_SUCCESS;
-}
-
-static int test_uint64divmod_0(void)
-{
-	uint64_t n = 8567106442584750ULL;
-	int d = 54870071;
-	int r = uint64divmod(&n, d);
-
-	TEST_CHECK(r == 5991285 && n == 156134415ULL);
-}
-
-static int test_uint64divmod_1(void)
-{
-	uint64_t n = 8567106442584750ULL;
-	int d = 2;
-	int r = uint64divmod(&n, d);
-
-	TEST_CHECK(r == 0 && n == 4283553221292375ULL);
-}
-
-static int test_uint64divmod_2(void)
-{
-	uint64_t n = 8567106442584750ULL;
-	int d = 0;
-	int r = uint64divmod(&n, d);
-
-	TEST_CHECK(r == 0 && n == 0ULL);
-}
-
-static int test_get_next_bit(void)
-{
-	uint32_t mask = 0x10001010;
-
-	TEST_ASSERT(get_next_bit(&mask) == 28);
-	TEST_ASSERT(mask == 0x1010);
-	TEST_ASSERT(get_next_bit(&mask) == 12);
-	TEST_ASSERT(mask == 0x10);
-	TEST_ASSERT(get_next_bit(&mask) == 4);
-	TEST_ASSERT(mask == 0x0);
-
-	return EC_SUCCESS;
-}
-
-static int test_shared_mem(void)
-{
-	int i;
-	int sz = shared_mem_size();
-	char *mem1, *mem2;
-
-	TEST_ASSERT(shared_mem_acquire(sz, &mem1) == EC_SUCCESS);
-	TEST_ASSERT(shared_mem_acquire(sz, &mem2) == EC_ERROR_BUSY);
-
-	for (i = 0; i < 256; ++i) {
-		memset(mem1, i, sz);
-		TEST_ASSERT_MEMSET(mem1, (char)i, sz);
-		if ((i & 0xf) == 0)
-			msleep(20); /* Yield to other tasks */
-	}
-
-	shared_mem_release(mem1);
-
-	return EC_SUCCESS;
-}
-
-static int test_scratchpad(void)
-{
-	uint32_t scratchpad_value;
-
-	system_set_scratchpad(0xfeed);
-	TEST_EQ(system_get_scratchpad(&scratchpad_value), EC_SUCCESS, "%d");
-	TEST_EQ(scratchpad_value, 0xfeed, "%d");
-
-	return EC_SUCCESS;
-}
-
-static int test_cond_t(void)
-{
-	cond_t c;
-
-	/* one-shot? */
-	cond_init_false(&c);
-	cond_set_true(&c);
-	TEST_ASSERT(cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	cond_set_false(&c);
-	TEST_ASSERT(cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-
-	/* one-shot when initially true? */
-	cond_init_true(&c);
-	cond_set_false(&c);
-	TEST_ASSERT(cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	cond_set_true(&c);
-	TEST_ASSERT(cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-
-	/* still one-shot even if set multiple times? */
-	cond_init_false(&c);
-	cond_set_true(&c);
-	cond_set_true(&c);
-	cond_set_true(&c);
-	cond_set_true(&c);
-	cond_set_true(&c);
-	cond_set_true(&c);
-	TEST_ASSERT(cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	cond_set_true(&c);
-	cond_set_false(&c);
-	cond_set_false(&c);
-	cond_set_false(&c);
-	cond_set_false(&c);
-	cond_set_false(&c);
-	TEST_ASSERT(cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-
-	/* only the detected transition direction resets it */
-	cond_set_true(&c);
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(cond_went_true(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	cond_set_false(&c);
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-
-	/* multiple transitions between checks should notice both edges */
-	cond_set_true(&c);
-	cond_set_false(&c);
-	cond_set_true(&c);
-	cond_set_false(&c);
-	cond_set_true(&c);
-	cond_set_false(&c);
-	TEST_ASSERT(cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_true(&c));
-	TEST_ASSERT(!cond_went_false(&c));
-
-	/* Still has last value? */
-	cond_set_true(&c);
-	cond_set_false(&c);
-	cond_set_true(&c);
-	cond_set_false(&c);
-	TEST_ASSERT(cond_is_false(&c));
-	cond_set_false(&c);
-	cond_set_true(&c);
-	cond_set_false(&c);
-	cond_set_true(&c);
-	TEST_ASSERT(cond_is_true(&c));
-
-	/* well okay then */
-	return EC_SUCCESS;
-}
-
-static int test_mula32(void)
-{
-	uint64_t r = 0x0;
-	uint64_t r2 = 0x0;
-	uint32_t b = 0x1;
-	uint32_t c = 0x1;
-	uint32_t i;
-	timestamp_t t0, t1;
-
-	t0 = get_time();
-	for (i = 0; i < 5000000; i++) {
-		r = mula32(b, c, r + (r >> 32));
-		r2 = mulaa32(b, c, r2 >> 32, r2);
-		b = (b << 13) ^ (b >> 2) ^ i;
-		c = (c << 16) ^ (c >> 7) ^ i;
-		watchdog_reload();
-	}
-	t1 = get_time();
-
-	ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n",
-		i, (uint32_t)(r >> 32), (uint32_t)r,
-		(uint32_t)(r2 >> 32), (uint32_t)r2, t1.le.lo-t0.le.lo);
-	TEST_ASSERT(r  == 0x9df59b9fb0ab9d96L);
-	TEST_ASSERT(r2 == 0x9df59b9fb0beabd6L);
-
-	/* well okay then */
-	return EC_SUCCESS;
-}
-
-#define SWAP_TEST_HARNESS(t, x, y) \
-	do { \
-		t a = x, b = y; \
-		swap(a, b); \
-		TEST_ASSERT(a == y); \
-		TEST_ASSERT(b == x); \
-	} while (0)
-
-
-static int test_swap(void)
-{
-	SWAP_TEST_HARNESS(uint8_t, UINT8_MAX, 0);
-	SWAP_TEST_HARNESS(uint16_t, UINT16_MAX, 0);
-	SWAP_TEST_HARNESS(uint32_t, UINT32_MAX, 0);
-	SWAP_TEST_HARNESS(float, 1, 0);
-	SWAP_TEST_HARNESS(double, 1, 0);
-	return EC_SUCCESS;
-}
-
-static int test_bytes_are_trivial(void)
-{
-	static const uint8_t all0x00[] = { 0x00, 0x00, 0x00 };
-	static const uint8_t all0xff[] = { 0xff, 0xff, 0xff, 0xff };
-	static const uint8_t nontrivial1[] = { 0x00, 0x01, 0x02 };
-	static const uint8_t nontrivial2[] = { 0xdd, 0xee, 0xff };
-	static const uint8_t nontrivial3[] = { 0x00, 0x00, 0x00, 0xff };
-	static const uint8_t nontrivial4[] = { 0xff, 0x00, 0x00, 0x00 };
-
-	TEST_ASSERT(bytes_are_trivial(all0x00, sizeof(all0x00)));
-	TEST_ASSERT(bytes_are_trivial(all0xff, sizeof(all0xff)));
-	TEST_ASSERT(!bytes_are_trivial(nontrivial1, sizeof(nontrivial1)));
-	TEST_ASSERT(!bytes_are_trivial(nontrivial2, sizeof(nontrivial2)));
-	TEST_ASSERT(!bytes_are_trivial(nontrivial3, sizeof(nontrivial3)));
-	TEST_ASSERT(!bytes_are_trivial(nontrivial4, sizeof(nontrivial4)));
-
-	return EC_SUCCESS;
-}
-
-test_static int test_is_aligned(void)
-{
-	TEST_EQ(is_aligned(2, 0), false, "%d");
-	TEST_EQ(is_aligned(2, 1), true, "%d");
-	TEST_EQ(is_aligned(2, 2), true, "%d");
-	TEST_EQ(is_aligned(2, 3), false, "%d");
-	TEST_EQ(is_aligned(2, 4), false, "%d");
-
-	TEST_EQ(is_aligned(3, 0), false, "%d");
-	TEST_EQ(is_aligned(3, 1), true, "%d");
-	TEST_EQ(is_aligned(3, 2), false, "%d");
-	TEST_EQ(is_aligned(3, 3), false, "%d");
-	TEST_EQ(is_aligned(3, 4), false, "%d");
-
-	return EC_SUCCESS;
-}
-
-test_static int test_safe_memcmp(void)
-{
-	const char str1[] = "abc";
-	const char str2[] = "def";
-	const char str3[] = "abc";
-
-	/* Verify that the compiler hasn't optimized str1 and str3 to point
-	 * to the same underlying memory.
-	 */
-	TEST_NE(str1, str3, "%p");
-
-	TEST_EQ(safe_memcmp(NULL, NULL, 0), 0, "%d");
-	TEST_EQ(safe_memcmp(str1, str2, sizeof(str1)), 1, "%d");
-	TEST_EQ(safe_memcmp(str1, str3, sizeof(str1)), 0, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_alignment_log2(void)
-{
-	TEST_EQ(alignment_log2(1), 0, "%d");
-	TEST_EQ(alignment_log2(2), 1, "%d");
-	TEST_EQ(alignment_log2(5), 0, "%d");
-	TEST_EQ(alignment_log2(0x10070000), 16, "%d");
-	TEST_EQ(alignment_log2(0x80000000), 31, "%d");
-	return EC_SUCCESS;
-}
-
-test_static int test_binary_first_base3_from_bits(void)
-{
-	int n0[] = {0, 0, 0};  /* LSB first */
-	int n7[] = {1, 1, 1};
-	int n8[] = {2, 0, 0};
-	int n9[] = {2, 1, 0};
-	int n10[] = {0, 2, 0};
-	int n11[] = {1, 2, 0};
-	int n18[] = {0, 0, 2};
-	int n26[] = {2, 2, 2};
-	int n38[] = {1, 2, 0, 1};
-
-	TEST_EQ(binary_first_base3_from_bits(n0, ARRAY_SIZE(n0)), 0, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n7, ARRAY_SIZE(n7)), 7, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n8, ARRAY_SIZE(n8)), 8, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n9, ARRAY_SIZE(n9)), 9, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n10, ARRAY_SIZE(n10)), 10, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n11, ARRAY_SIZE(n11)), 11, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n18, ARRAY_SIZE(n18)), 18, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n26, ARRAY_SIZE(n26)), 26, "%d");
-	TEST_EQ(binary_first_base3_from_bits(n38, ARRAY_SIZE(n38)), 38, "%d");
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_memmove);
-	RUN_TEST(test_memcpy);
-	RUN_TEST(test_memset);
-	RUN_TEST(test_memchr);
-	RUN_TEST(test_uint64divmod_0);
-	RUN_TEST(test_uint64divmod_1);
-	RUN_TEST(test_uint64divmod_2);
-	RUN_TEST(test_get_next_bit);
-	RUN_TEST(test_shared_mem);
-	RUN_TEST(test_scratchpad);
-	RUN_TEST(test_cond_t);
-	RUN_TEST(test_mula32);
-	RUN_TEST(test_swap);
-	RUN_TEST(test_bytes_are_trivial);
-	RUN_TEST(test_is_aligned);
-	RUN_TEST(test_safe_memcmp);
-	RUN_TEST(test_alignment_log2);
-	RUN_TEST(test_binary_first_base3_from_bits);
-
-	test_print_result();
-}
diff --git a/test/utils.tasklist b/test/utils.tasklist
deleted file mode 100644
index da0ab6211a..0000000000
--- a/test/utils.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/utils_str.c b/test/utils_str.c
deleted file mode 100644
index f184abffa6..0000000000
--- a/test/utils_str.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test common utilities (string functions).
- */
-
-#include "common.h"
-#include "console.h"
-#include "system.h"
-#include "printf.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-static int test_isalpha(void)
-{
-	TEST_CHECK(isalpha('a') && isalpha('z') && isalpha('A') &&
-		   isalpha('Z') && !isalpha('0') && !isalpha('~') &&
-		   !isalpha(' ') && !isalpha('\0') && !isalpha('\n'));
-}
-
-static int test_isprint(void)
-{
-	TEST_CHECK(isprint('a') && isprint('z') && isprint('A') &&
-		   isprint('Z') && isprint('0') && isprint('~') &&
-		   isprint(' ') && !isprint('\0') && !isprint('\n'));
-}
-
-static int test_strstr(void)
-{
-	const char s1[] = "abcde";
-
-	TEST_ASSERT(strstr(s1, "ab") == s1);
-	TEST_ASSERT(strstr(s1, "") == NULL);
-	TEST_ASSERT(strstr("", "ab") == NULL);
-	TEST_ASSERT(strstr("", "x") == NULL);
-	TEST_ASSERT(strstr(s1, "de") == &s1[3]);
-	TEST_ASSERT(strstr(s1, "def") == NULL);
-
-	return EC_SUCCESS;
-}
-
-static int test_strtoi(void)
-{
-	char *e;
-
-	TEST_ASSERT(strtoi("10", &e, 0) == 10);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("+010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("-010", &e, 0) == -8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("0x1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoi("0X1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoi("10a", &e, 16) == 266);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("+0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("-0x02C", &e, 16) == -44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("+0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("-0x02C", &e, 0) == -44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("+0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("-0X02C", &e, 16) == -44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("+0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("-0X02C", &e, 0) == -44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("   -12", &e, 0) == -12);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoi("!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoi("+!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoi("+0!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoi("+0x!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoi("+0X!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-
-	return EC_SUCCESS;
-}
-
-static int test_strtoull(void)
-{
-	char *e;
-
-	TEST_ASSERT(strtoull("10", &e, 0) == 10);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-010", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoull("10a", &e, 16) == 266);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("   -12", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0x!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0X!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-
-	return EC_SUCCESS;
-}
-
-static int test_parse_bool(void)
-{
-	int v;
-
-	TEST_ASSERT(parse_bool("on", &v) == 1);
-	TEST_ASSERT(v == 1);
-	TEST_ASSERT(parse_bool("off", &v) == 1);
-	TEST_ASSERT(v == 0);
-	TEST_ASSERT(parse_bool("enable", &v) == 1);
-	TEST_ASSERT(v == 1);
-	TEST_ASSERT(parse_bool("disable", &v) == 1);
-	TEST_ASSERT(v == 0);
-	TEST_ASSERT(parse_bool("di", &v) == 0);
-	TEST_ASSERT(parse_bool("en", &v) == 0);
-	TEST_ASSERT(parse_bool("of", &v) == 0);
-
-	return EC_SUCCESS;
-}
-
-static int test_strzcpy(void)
-{
-	char dest[10];
-
-	strzcpy(dest, "test", 10);
-	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
-	strzcpy(dest, "testtesttest", 10);
-	TEST_ASSERT_ARRAY_EQ("testtestt", dest, 10);
-	strzcpy(dest, "aaaa", -1);
-	TEST_ASSERT_ARRAY_EQ("testtestt", dest, 10);
-
-	return EC_SUCCESS;
-}
-
-static int test_strncpy(void)
-{
-	char dest[10];
-
-	strncpy(dest, "test", 10);
-	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
-	strncpy(dest, "12345", 6);
-	TEST_ASSERT_ARRAY_EQ("12345", dest, 6);
-	strncpy(dest, "testtesttest", 10);
-	TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10);
-
-	return EC_SUCCESS;
-}
-
-static int test_strncmp(void)
-{
-	TEST_ASSERT(strncmp("123", "123", 8) == 0);
-	TEST_ASSERT(strncmp("789", "456", 8) > 0);
-	TEST_ASSERT(strncmp("abc", "abd", 4) < 0);
-	TEST_ASSERT(strncmp("abc", "abd", 2) == 0);
-	return EC_SUCCESS;
-}
-
-static int test_strlen(void)
-{
-	TEST_CHECK(strlen("this is a string") == 16);
-}
-
-static int test_strnlen(void)
-{
-	TEST_ASSERT(strnlen("this is a string", 17) == 16);
-	TEST_ASSERT(strnlen("this is a string", 16) == 16);
-	TEST_ASSERT(strnlen("this is a string", 5) == 5);
-
-	return EC_SUCCESS;
-}
-
-static int test_strcasecmp(void)
-{
-	TEST_CHECK((strcasecmp("test string", "TEST strIng") == 0) &&
-		   (strcasecmp("test123!@#", "TesT123!@#") == 0) &&
-		   (strcasecmp("lower", "UPPER") != 0));
-}
-
-static int test_strncasecmp(void)
-{
-	TEST_CHECK((strncasecmp("test string", "TEST str", 4) == 0) &&
-		   (strncasecmp("test string", "TEST str", 8) == 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 5) != 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 4) == 0) &&
-		   (strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0) &&
-		   (strncasecmp("1test123", "teststr", 0) == 0));
-}
-
-static int test_atoi(void)
-{
-	TEST_CHECK((atoi("  901") == 901) &&
-		   (atoi("-12c") == -12) &&
-		   (atoi("   0  ") == 0) &&
-		   (atoi("\t111") == 111));
-}
-
-static int test_snprintf(void)
-{
-	char buffer[32];
-
-	TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4);
-	TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer)));
-}
-
-static int test_strcspn(void)
-{
-	const char str1[] = "abc";
-	const char str2[] = "This is a string\nwith newlines!";
-
-	TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu");
-	TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu");
-	TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu");
-	TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu");
-	TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu");
-	TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu");
-	TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu");
-
-	TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu");
-	TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu");
-	TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu");
-	TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu");
-	TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu");
-	TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_isalpha);
-	RUN_TEST(test_isprint);
-	RUN_TEST(test_strstr);
-	RUN_TEST(test_strtoi);
-	RUN_TEST(test_strtoull);
-	RUN_TEST(test_parse_bool);
-	RUN_TEST(test_strzcpy);
-	RUN_TEST(test_strncpy);
-	RUN_TEST(test_strncmp);
-	RUN_TEST(test_strlen);
-	RUN_TEST(test_strnlen);
-	RUN_TEST(test_strcasecmp);
-	RUN_TEST(test_strncasecmp);
-	RUN_TEST(test_atoi);
-	RUN_TEST(test_snprintf);
-	RUN_TEST(test_strcspn);
-
-	test_print_result();
-}
diff --git a/test/utils_str.tasklist b/test/utils_str.tasklist
deleted file mode 100644
index 7150f17cbd..0000000000
--- a/test/utils_str.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/vboot.c b/test/vboot.c
deleted file mode 100644
index 7dab08ac05..0000000000
--- a/test/vboot.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test vboot
- */
-
-#include "common.h"
-#include "rsa.h"
-#include "test_util.h"
-#include "vboot.h"
-#include "rsa2048-3.h"
-#include "rwsig.h"
-
-struct vboot_key {
-	struct vb21_packed_key vb21_key;
-	struct rsa_public_key key_data;
-};
-
-struct vboot_sig {
-	struct vb21_signature vb21_sig;
-	uint8_t sig_data[RSANUMBYTES];
-};
-
-static void reset_data(struct vboot_key *k, struct vboot_sig *s)
-{
-	k->vb21_key.c.magic = VB21_MAGIC_PACKED_KEY;
-	k->vb21_key.key_offset = sizeof(struct vb21_packed_key);
-	k->vb21_key.key_size = sizeof(rsa_data);
-	memcpy(&k->key_data, rsa_data, sizeof(rsa_data));
-
-	s->vb21_sig.c.magic = VB21_MAGIC_SIGNATURE;
-	s->vb21_sig.sig_size = RSANUMBYTES;
-	s->vb21_sig.sig_offset = sizeof(struct vb21_signature);
-	s->vb21_sig.sig_alg = k->vb21_key.sig_alg;
-	s->vb21_sig.hash_alg = k->vb21_key.hash_alg;
-	s->vb21_sig.data_size = CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE - 32;
-	memcpy(s->sig_data, sig, sizeof(s->sig_data));
-}
-
-static int test_vboot(void)
-{
-	struct vboot_key k;
-	struct vboot_sig s;
-	uint8_t data[CONFIG_RW_SIZE];
-	int len;
-	int err;
-
-	/* Success */
-	reset_data(&k, &s);
-	memset(data, 0xff, CONFIG_RW_SIZE);
-	err = vb21_is_packed_key_valid(&k.vb21_key);
-	TEST_ASSERT(err == EC_SUCCESS);
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_SUCCESS);
-	len = s.vb21_sig.data_size;
-	err = vboot_is_padding_valid(data, len,
-				     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
-	TEST_ASSERT(err == EC_SUCCESS);
-
-	/* Invalid magic */
-	reset_data(&k, &s);
-	k.vb21_key.c.magic = VB21_MAGIC_SIGNATURE;
-	err = vb21_is_packed_key_valid(&k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_KEY_MAGIC);
-
-	/* Invalid key size */
-	reset_data(&k, &s);
-	k.vb21_key.key_size--;
-	err = vb21_is_packed_key_valid(&k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_KEY_SIZE);
-
-	/* Invalid magic */
-	reset_data(&k, &s);
-	s.vb21_sig.c.magic = VB21_MAGIC_PACKED_KEY;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_SIG_MAGIC);
-
-	/* Invalid sig size */
-	reset_data(&k, &s);
-	s.vb21_sig.sig_size--;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_SIG_SIZE);
-
-	/* Sig algorithm mismatch */
-	reset_data(&k, &s);
-	s.vb21_sig.sig_alg++;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_SIG_ALGORITHM);
-
-	/* Hash algorithm mismatch */
-	reset_data(&k, &s);
-	s.vb21_sig.hash_alg++;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_HASH_ALGORITHM);
-
-	/* Invalid sig_offset */
-	reset_data(&k, &s);
-	s.vb21_sig.sig_offset--;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_SIG_OFFSET);
-
-	/* Invalid data size */
-	reset_data(&k, &s);
-	s.vb21_sig.data_size = CONFIG_RW_SIZE;
-	err = vb21_is_signature_valid(&s.vb21_sig, &k.vb21_key);
-	TEST_ASSERT(err == EC_ERROR_VBOOT_DATA_SIZE);
-
-	/* Invalid padding */
-	reset_data(&k, &s);
-	len = s.vb21_sig.data_size;
-	data[len] = 0;
-	err = vboot_is_padding_valid(data, len,
-				     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
-	TEST_ASSERT(err == EC_ERROR_INVAL);
-
-	/* Invalid padding size */
-	reset_data(&k, &s);
-	len = s.vb21_sig.data_size + 1;
-	err = vboot_is_padding_valid(data, len,
-				     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
-	TEST_ASSERT(err == EC_ERROR_INVAL);
-
-	/* Padding size is too large */
-	reset_data(&k, &s);
-	len = s.vb21_sig.data_size + 64;
-	err = vboot_is_padding_valid(data, len,
-				     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
-	TEST_ASSERT(err == EC_ERROR_INVAL);
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	test_reset();
-
-	RUN_TEST(test_vboot);
-
-	test_print_result();
-}
diff --git a/test/vboot.tasklist b/test/vboot.tasklist
deleted file mode 100644
index 7150f17cbd..0000000000
--- a/test/vboot.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/version.c b/test/version.c
deleted file mode 100644
index ad7571d5f6..0000000000
--- a/test/version.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test ec version
- */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "stddef.h"
-#include "system.h"
-#include "util.h"
-#include "test_util.h"
-
-/*
- * Tests that fw version adheres to the expected format.
- * Example fw version: host_v2.0.10135+b3e38e380c
- */
-static int test_version(void)
-{
-	const char *fw_version;
-	size_t board_name_length, major_version_length, minor_version_length,
-		sub_minor_version_length, hash_length;
-	const char *major_version_ptr, *minor_version_ptr,
-		*sub_minor_version_ptr, *hash_ptr;
-
-	fw_version = system_get_version(EC_IMAGE_RO);
-
-	TEST_ASSERT(fw_version != NULL);
-
-	ccprintf("fw_version: %s\n", fw_version);
-
-	TEST_LE(strlen(fw_version), (size_t)32, "%zu");
-
-	board_name_length = strcspn(fw_version, "_");
-
-	TEST_GE(board_name_length, (size_t)3, "%zu");
-
-	major_version_ptr = fw_version + board_name_length + 1;
-	major_version_length = strcspn(major_version_ptr, ".");
-
-	TEST_GE(major_version_length, (size_t)2, "%zu");
-	TEST_EQ(major_version_ptr[0], 'v', "%c");
-	for (int i = 1; i < major_version_length; i++)
-		TEST_ASSERT(isdigit(major_version_ptr[i]));
-
-	minor_version_ptr = major_version_ptr + major_version_length + 1;
-	minor_version_length = strcspn(minor_version_ptr, ".");
-
-	TEST_GE(minor_version_length, (size_t)1, "%zu");
-	for (int i = 0; i < minor_version_length; i++)
-		TEST_ASSERT(isdigit(minor_version_ptr[i]));
-
-	sub_minor_version_ptr = minor_version_ptr + minor_version_length + 1;
-	sub_minor_version_length = strcspn(sub_minor_version_ptr, "-+");
-
-	TEST_GE(sub_minor_version_length, (size_t)1, "%zu");
-	for (int i = 0; i < sub_minor_version_length; i++)
-		TEST_ASSERT(isdigit(sub_minor_version_ptr[i]));
-
-	hash_ptr = sub_minor_version_ptr + sub_minor_version_length + 1;
-	hash_length = strlen(hash_ptr);
-
-	TEST_GE(hash_length, (size_t)8, "%zu");
-	for (int i = 0; i < hash_length; i++)
-		TEST_ASSERT(isdigit(hash_ptr[i]) ||
-			    (hash_ptr[i] >= 'a' && hash_ptr[i] <= 'f'));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Tests that cros fwid adheres to the expected format.
- * Example cros fwid: host_14175.0.21_08_24
- */
-static int test_fwid(void)
-{
-	const char *cros_fwid;
-	size_t board_name_length, major_version_length, minor_version_length,
-		sub_minor_version_length;
-	const char *major_version_ptr, *minor_version_ptr,
-		*sub_minor_version_ptr;
-
-	cros_fwid = system_get_cros_fwid(EC_IMAGE_RO);
-
-	TEST_ASSERT(cros_fwid != NULL);
-
-	ccprintf("cros_fwid: %s\n", cros_fwid);
-
-	TEST_LE(strlen(cros_fwid), (size_t)32, "%zu");
-
-	board_name_length = strcspn(cros_fwid, "_");
-	TEST_GE(board_name_length, (size_t)3, "%zu");
-
-	major_version_ptr = cros_fwid + board_name_length + 1;
-	major_version_length = strcspn(major_version_ptr, ".");
-	TEST_GE(major_version_length, (size_t)5, "%zu");
-
-	for (int i = 0; i < major_version_length; i++)
-		TEST_ASSERT(isdigit(major_version_ptr[i]));
-
-	minor_version_ptr = major_version_ptr + major_version_length + 1;
-	minor_version_length = strcspn(minor_version_ptr, ".");
-	TEST_GE(minor_version_length, (size_t)1, "%zu");
-
-	for (int i = 0; i < minor_version_length; i++)
-		TEST_ASSERT(isdigit(minor_version_ptr[i]));
-
-	sub_minor_version_ptr = minor_version_ptr + minor_version_length + 1;
-	sub_minor_version_length = strlen(sub_minor_version_ptr);
-	TEST_GE(sub_minor_version_length, (size_t)1, "%zu");
-
-	for (int i = 0; i < sub_minor_version_length; i++)
-		TEST_ASSERT(isdigit(sub_minor_version_ptr[i]) ||
-			    sub_minor_version_ptr[i] == '_');
-
-	return EC_SUCCESS;
-}
-
-/*
- * Tests requesting TEST.
- * Example fw version: host_v2.0.10135+b3e38e380c
- */
-static int test_image_unknown(void)
-{
-	const char *fw_version;
-	const char *cros_fwid;
-
-	fw_version = system_get_version(EC_IMAGE_UNKNOWN);
-
-	TEST_ASSERT(fw_version != NULL);
-	TEST_LE(strlen(fw_version), (size_t)32, "%zu");
-
-	cros_fwid = system_get_cros_fwid(EC_IMAGE_UNKNOWN);
-
-	TEST_ASSERT(cros_fwid != NULL);
-	TEST_LE(strlen(cros_fwid), (size_t)32, "%zu");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
-{
-	RUN_TEST(test_version);
-	RUN_TEST(test_fwid);
-	RUN_TEST(test_image_unknown);
-
-	test_print_result();
-}
diff --git a/test/version.tasklist b/test/version.tasklist
deleted file mode 100644
index e54ea001bd..0000000000
--- a/test/version.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/vpd_api.c b/test/vpd_api.c
deleted file mode 100644
index 65e86adb96..0000000000
--- a/test/vpd_api.c
+++ /dev/null
@@ -1,586 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "vpd_api.h"
-#include "driver/tcpm/tcpm.h"
-#include "console.h"
-/*
- * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector
- * Specification)
- *
- * CC1    CC2    STATE             POSITION
- * ----------------------------------------
- * open   open   NC                N/A
- * Rd     open   UFP attached      1
- * open   Rd     UFP attached      2
- * open   Ra     pwr cable no UFP  N/A
- * Ra     open   pwr cable no UFP  N/A
- * Rd     Ra     pwr cable & UFP   1
- * Ra     Rd     pwr cable & UFP   2
- * Rd     Rd     dbg accessory     N/A
- * Ra     Ra     audio accessory   N/A
- *
- * Note, V(Rd) > V(Ra)
- */
-#ifndef PD_SRC_RD_THRESHOLD
-#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
-#endif
-#ifndef PD_SRC_VNC
-#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
-#endif
-
-#ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < pd_src_rd_threshold[ct_cc_rp_value])
-#endif
-#define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
-#ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
-#endif
-
-/*
- * Polarity based on 'UFP Perspective'.
- *
- * CC1    CC2    STATE             POSITION
- * ----------------------------------------
- * open   open   NC                N/A
- * Rp     open   DFP attached      1
- * open   Rp     DFP attached      2
- * Rp     Rp     Accessory attached N/A
- */
-#ifndef PD_SNK_VA
-#define PD_SNK_VA PD_SNK_VA_MV
-#endif
-
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
-
-/* Mock Board State */
-static enum vpd_pwr mock_vconn_pwr_sel_odl;
-static enum vpd_gpo mock_cc1_cc2_rd_l;
-static enum vpd_gpo mock_cc_db_en_od;
-static enum vpd_gpo mock_cc_rpusb_odh;
-static enum vpd_cc mock_ct_cl_sel;
-static int mock_mcu_cc_en;
-static enum vpd_billboard mock_present_billboard;
-static int mock_red_led;
-static int mock_green_led;
-static int mock_vbus_pass_en;
-
-static int mock_read_host_vbus;
-static int mock_read_ct_vbus;
-static int mock_read_vconn;
-
-static struct mock_pin mock_cc2_rpusb_odh;
-static struct mock_pin mock_cc2_rp3a0_rd_l;
-static struct mock_pin mock_cc1_rpusb_odh;
-static struct mock_pin mock_cc1_rp3a0_rd_l;
-static struct mock_pin mock_cc_vpdmcu;
-static struct mock_pin mock_cc_rp3a0_rd_l;
-
-/* Charge-Through pull up/down enabled */
-static int ct_cc_pull;
-/* Charge-Through pull up value */
-static int ct_cc_rp_value;
-
-/* Charge-Through pull up/down enabled */
-static int host_cc_pull;
-/* Charge-Through pull up value */
-static int host_cc_rp_value;
-
-/* Voltage thresholds for Ra attach in normal SRC mode */
-static int pd_src_rd_threshold[TYPEC_RP_RESERVED] = {
-	PD_SRC_DEF_RD_THRESH_MV,
-	PD_SRC_1_5_RD_THRESH_MV,
-	PD_SRC_3_0_RD_THRESH_MV,
-};
-
-enum vpd_pwr mock_get_vconn_pwr_source(void)
-{
-	return mock_vconn_pwr_sel_odl;
-}
-
-int mock_get_ct_cc1_rpusb(void)
-{
-	return mock_cc1_rpusb_odh.value;
-}
-
-int mock_get_ct_cc2_rpusb(void)
-{
-	return mock_cc2_rpusb_odh.value;
-}
-
-enum vpd_gpo mock_get_ct_rd(void)
-{
-	return mock_cc1_cc2_rd_l;
-}
-
-enum vpd_gpo mock_get_cc_rpusb_odh(void)
-{
-	return mock_cc_rpusb_odh;
-}
-
-enum vpd_gpo mock_get_cc_db_en_od(void)
-{
-	return mock_cc_db_en_od;
-}
-
-enum vpd_cc moch_get_ct_cl_sel(void)
-{
-	return mock_ct_cl_sel;
-}
-
-int mock_get_mcu_cc_en(void)
-{
-	return mock_mcu_cc_en;
-}
-
-enum vpd_billboard mock_get_present_billboard(void)
-{
-	return mock_present_billboard;
-}
-
-int mock_get_red_led(void)
-{
-	return mock_red_led;
-}
-
-int mock_get_green_led(void)
-{
-	return mock_green_led;
-}
-
-int mock_get_vbus_pass_en(void)
-{
-	return mock_vbus_pass_en;
-}
-
-void mock_set_host_cc_sink_voltage(int v)
-{
-	mock_cc_vpdmcu.value = v;
-}
-
-void mock_set_host_cc_source_voltage(int v)
-{
-	mock_cc_vpdmcu.value2 = v;
-}
-
-void mock_set_host_vbus(int v)
-{
-	mock_read_host_vbus = v;
-}
-
-void mock_set_ct_vbus(int v)
-{
-	mock_read_ct_vbus = v;
-}
-
-void mock_set_vconn(int v)
-{
-	mock_read_vconn = v;
-}
-
-int mock_get_cfg_cc2_rpusb_odh(void)
-{
-	return mock_cc2_rpusb_odh.cfg;
-}
-
-int mock_set_cc2_rpusb_odh(int v)
-{
-	if (mock_cc2_rpusb_odh.cfg == PIN_ADC) {
-		mock_cc2_rpusb_odh.value = v;
-		return 1;
-	}
-	return 0;
-}
-
-int mock_get_cfg_cc2_rp3a0_rd_l(void)
-{
-	return mock_cc2_rp3a0_rd_l.cfg;
-}
-
-int mock_set_cc2_rp3a0_rd_l(int v)
-{
-	if (mock_cc2_rp3a0_rd_l.cfg == PIN_ADC) {
-		mock_cc2_rp3a0_rd_l.value = v;
-		return 1;
-	}
-
-	return 0;
-}
-
-int mock_get_cc1_rpusb_odh(void)
-{
-	return mock_cc1_rpusb_odh.cfg;
-}
-
-int mock_set_cc1_rpusb_odh(int v)
-{
-	if (mock_cc1_rpusb_odh.cfg == PIN_ADC) {
-		mock_cc1_rpusb_odh.value = v;
-		return 1;
-	}
-
-	return 0;
-}
-
-int mock_get_cfg_cc_vpdmcu(void)
-{
-	return mock_cc_vpdmcu.cfg;
-}
-
-enum vpd_pin mock_get_cfg_cc_rp3a0_rd_l(void)
-{
-	return mock_cc_rp3a0_rd_l.cfg;
-}
-
-int mock_get_cc_rp3a0_rd_l(void)
-{
-	return mock_cc_rp3a0_rd_l.value;
-}
-
-int mock_get_cfg_cc1_rp3a0_rd_l(void)
-{
-	return mock_cc1_rp3a0_rd_l.cfg;
-}
-
-int mock_set_cc1_rp3a0_rd_l(int v)
-{
-	if (mock_cc1_rp3a0_rd_l.cfg == PIN_ADC) {
-		mock_cc1_rp3a0_rd_l.value = v;
-		return 1;
-	}
-
-	return 0;
-}
-
-/* Convert CC voltage to CC status */
-static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
-{
-	/* If we have a pull-up, then we are source, check for Rd. */
-	if (cc_pull == TYPEC_CC_RP) {
-		if (CC_NC(0, cc_volt, 0))
-			return TYPEC_CC_VOLT_OPEN;
-		else if (CC_RA(0, cc_volt, 0))
-			return TYPEC_CC_VOLT_RA;
-		else
-			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
-	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
-		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_3_0;
-		else if (cc_volt >= TYPE_C_SRC_1500_THRESHOLD)
-			return TYPEC_CC_VOLT_RP_1_5;
-		else if (CC_RP(cc_volt))
-			return TYPEC_CC_VOLT_RP_DEF;
-		else
-			return TYPEC_CC_VOLT_OPEN;
-	} else {
-		/* If we are open, then always return 0 */
-		return 0;
-	}
-}
-
-void vpd_ct_set_pull(int pull, int rp_value)
-{
-	ct_cc_pull = pull;
-
-	switch (pull) {
-	case TYPEC_CC_RP:
-		ct_cc_rp_value = rp_value;
-		vpd_cc1_cc2_db_en_l(GPO_HIGH);
-		switch (rp_value) {
-		case TYPEC_RP_USB:
-			vpd_config_cc1_rp3a0_rd_l(PIN_ADC, 0);
-			vpd_config_cc2_rp3a0_rd_l(PIN_ADC, 0);
-			vpd_config_cc1_rpusb_odh(PIN_GPO, 1);
-			vpd_config_cc2_rpusb_odh(PIN_GPO, 1);
-			break;
-		case TYPEC_RP_3A0:
-			vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-			vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-			vpd_config_cc1_rp3a0_rd_l(PIN_GPO, 1);
-			vpd_config_cc2_rp3a0_rd_l(PIN_GPO, 1);
-			break;
-		}
-		break;
-	case TYPEC_CC_RD:
-		vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc1_rp3a0_rd_l(PIN_ADC, 0);
-		vpd_config_cc2_rp3a0_rd_l(PIN_ADC, 0);
-		vpd_cc1_cc2_db_en_l(GPO_LOW);
-		break;
-	case TYPEC_CC_OPEN:
-		vpd_cc1_cc2_db_en_l(GPO_HIGH);
-		vpd_config_cc1_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc2_rpusb_odh(PIN_ADC, 0);
-		vpd_config_cc1_rp3a0_rd_l(PIN_ADC, 0);
-		vpd_config_cc2_rp3a0_rd_l(PIN_ADC, 0);
-		break;
-	}
-}
-
-void vpd_ct_get_cc(int *cc1, int *cc2)
-{
-	int cc1_v = 0;
-	int cc2_v = 0;
-
-	switch (ct_cc_pull) {
-	case TYPEC_CC_RP:
-		switch (ct_cc_rp_value) {
-		case TYPEC_RP_USB:
-			cc1_v = mock_cc1_rp3a0_rd_l.value;
-			cc2_v = mock_cc2_rp3a0_rd_l.value;
-			break;
-		case TYPEC_RP_3A0:
-			cc1_v = mock_cc1_rpusb_odh.value;
-			cc2_v = mock_cc2_rpusb_odh.value;
-			break;
-		}
-
-		if (!cc1_v && !cc2_v) {
-			cc1_v = PD_SRC_VNC;
-			cc2_v = PD_SRC_VNC;
-		}
-		break;
-	case TYPEC_CC_RD:
-		cc1_v = mock_cc1_rpusb_odh.value;
-		cc2_v = mock_cc2_rpusb_odh.value;
-		break;
-	case TYPEC_CC_OPEN:
-		*cc1 = 0;
-		*cc2 = 0;
-		return;
-	}
-
-	*cc1 = vpd_cc_voltage_to_status(cc1_v, ct_cc_pull);
-	*cc2 = vpd_cc_voltage_to_status(cc2_v, ct_cc_pull);
-}
-
-void vpd_host_set_pull(int pull, int rp_value)
-{
-	host_cc_pull = pull;
-
-	switch (pull) {
-	case TYPEC_CC_RP:
-		vpd_cc_db_en_od(GPO_LOW);
-		host_cc_rp_value = rp_value;
-		switch (rp_value) {
-		case TYPEC_RP_USB:
-			vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
-			vpd_cc_rpusb_odh(GPO_HIGH);
-			break;
-		case TYPEC_RP_3A0:
-			vpd_cc_rpusb_odh(GPO_HZ);
-			vpd_config_cc_rp3a0_rd_l(PIN_GPO, 1);
-			break;
-		}
-		break;
-	case TYPEC_CC_RD:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_cc_db_en_od(GPO_LOW);
-
-		vpd_config_cc_rp3a0_rd_l(PIN_GPO, 0);
-		break;
-	case TYPEC_CC_RA_RD:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_config_cc_rp3a0_rd_l(PIN_GPO, 0);
-
-		/*
-		 * RA is connected to VCONN
-		 * RD is connected to CC
-		 */
-		vpd_cc_db_en_od(GPO_HZ);
-		break;
-	case TYPEC_CC_OPEN:
-		vpd_cc_rpusb_odh(GPO_HZ);
-		vpd_config_cc_rp3a0_rd_l(PIN_CMP, 0);
-		vpd_cc_db_en_od(GPO_LOW);
-
-		/*
-		 * Do nothing. CC is open on entry to this function
-		 */
-		break;
-	}
-}
-
-void vpd_host_get_cc(int *cc)
-{
-	int v;
-
-	if (host_cc_pull == TYPEC_CC_OPEN) {
-		*cc = 0;
-		return;
-	} else if (host_cc_pull == TYPEC_CC_RP) {
-		v = mock_cc_vpdmcu.value;
-	} else {
-		v = mock_cc_vpdmcu.value2;
-	}
-
-	*cc = vpd_cc_voltage_to_status(v, host_cc_pull);
-}
-
-void vpd_rx_enable(int en)
-{
-	if (en) {
-		mock_ct_cl_sel = 0;
-		mock_mcu_cc_en = 1;
-	}
-
-	tcpm_set_polarity(0, 0);
-	tcpm_set_rx_enable(0, en);
-}
-
-/*
- * PA1: Configure as ADC, CMP, or GPO
- */
-void vpd_config_cc_vpdmcu(enum vpd_pin cfg, int en)
-{
-	mock_cc_vpdmcu.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc_vpdmcu.value = en ? 1 : 0;
-}
-
-/*
- * PA2: Configure as COMP2_INM6 or GPO
- */
-void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	mock_cc_rp3a0_rd_l.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc_rp3a0_rd_l.value = en ? 1 : 0;
-}
-
-/*
- * PA4: Configure as ADC, CMP, or GPO
- */
-void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	mock_cc1_rp3a0_rd_l.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc1_rp3a0_rd_l.value = en ? 1 : 0;
-}
-
-/*
- * PA5: Configure as ADC, COMP, or GPO
- */
-void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
-{
-	mock_cc2_rp3a0_rd_l.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc2_rp3a0_rd_l.value = en ? 1 : 0;
-}
-
-/*
- * PB0: Configure as ADC or GPO
- */
-void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en)
-{
-	mock_cc1_rpusb_odh.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc1_rpusb_odh.value = en ? 1 : 0;
-}
-
-/*
- * PB1: Configure as ADC or GPO
- */
-void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en)
-{
-	mock_cc2_rpusb_odh.cfg = cfg;
-
-	if (cfg == PIN_GPO)
-		mock_cc2_rpusb_odh.value = en ? 1 : 0;
-}
-
-int vpd_read_host_vbus(void)
-{
-	return mock_read_host_vbus;
-}
-
-int vpd_read_ct_vbus(void)
-{
-	return mock_read_ct_vbus;
-}
-
-int vpd_read_vconn(void)
-{
-	return mock_read_vconn;
-}
-
-int vpd_is_host_vbus_present(void)
-{
-	return (vpd_read_host_vbus() >= PD_SNK_VA);
-}
-
-int vpd_is_ct_vbus_present(void)
-{
-	return (vpd_read_ct_vbus() >= PD_SNK_VA);
-}
-
-int vpd_is_vconn_present(void)
-{
-	return (vpd_read_vconn() >= PD_SNK_VA);
-}
-
-int vpd_read_rdconnect_ref(void)
-{
-	return 200; /* 200 mV */
-}
-
-void vpd_red_led(int on)
-{
-	mock_red_led = on ? 0 : 1;
-}
-
-void vpd_green_led(int on)
-{
-	mock_green_led = on ? 0 : 1;
-}
-
-void vpd_vbus_pass_en(int en)
-{
-	mock_vbus_pass_en = en ? 1 : 0;
-}
-
-void vpd_present_billboard(enum vpd_billboard bb)
-{
-	mock_present_billboard = bb;
-}
-
-void vpd_mcu_cc_en(int en)
-{
-	mock_mcu_cc_en = en ? 1 : 0;
-}
-
-void vpd_ct_cc_sel(enum vpd_cc sel)
-{
-	mock_ct_cl_sel = sel;
-}
-
-/* Set as GPO High, GPO Low, or High-Z */
-void vpd_cc_db_en_od(enum vpd_gpo val)
-{
-	mock_cc_db_en_od = val;
-}
-
-void vpd_cc_rpusb_odh(enum vpd_gpo val)
-{
-	mock_cc_rpusb_odh = val;
-}
-
-void vpd_cc1_cc2_db_en_l(enum vpd_gpo val)
-{
-	mock_cc1_cc2_rd_l = val;
-}
-
-void vpd_vconn_pwr_sel_odl(enum vpd_pwr en)
-{
-	mock_vconn_pwr_sel_odl = en;
-}
diff --git a/test/vpd_api.h b/test/vpd_api.h
deleted file mode 100644
index f848138172..0000000000
--- a/test/vpd_api.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Vconn Power Device API module */
-
-#ifndef __CROS_EC_VPD_API_H
-#define __CROS_EC_VPD_API_H
-
-#include "gpio.h"
-#include "usb_pd.h"
-
-/*
- * Type C power source charge current limits are identified by their cc
- * voltage (set by selecting the proper Rd resistor). Any voltage below
- * TYPE_C_SRC_DEFAULT_THRESHOLD will not be identified as a type C charger.
- */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
-
-
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
-
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
-
-enum vpd_pwr {
-	PWR_VCONN,
-	PWR_VBUS,
-};
-
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
-
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
-
-struct mock_pin {
-	enum vpd_pin cfg;
-	int value;
-	int value2;
-};
-
-enum vpd_pwr mock_get_vconn_pwr_source(void);
-enum vpd_gpo mock_get_ct_rd(void);
-enum vpd_gpo mock_get_cc_rp1a5_odh(void);
-enum vpd_gpo mock_get_cc_rpusb_odh(void);
-enum vpd_gpo mock_get_cc_db_en_od(void);
-enum vpd_cc moch_get_ct_cl_sel(void);
-int mock_get_mcu_cc_en(void);
-enum vpd_billboard mock_get_present_billboard(void);
-int mock_get_red_led(void);
-int mock_get_green_led(void);
-int mock_get_vbus_pass_en(void);
-int mock_set_cc_vpdmcu(int v);
-void mock_set_host_vbus(int v);
-void mock_set_ct_vbus(int v);
-void mock_set_vconn(int v);
-int mock_get_cfg_cc2_rpusb_odh(void);
-int mock_set_cc2_rpusb_odh(int v);
-int mock_get_cfg_cc2_rp3a0_rd_l(void);
-int mock_set_cc2_rp3a0_rd_l(int v);
-int mock_get_cfg_cc1_rpusb_odh(void);
-int mock_set_cc1_rpusb_odh(int v);
-int mock_get_cfg_cc_vpdmcu(void);
-int mock_get_cc_vpdmcu(int v);
-enum vpd_pin mock_get_cfg_cc_rp3a0_rd_l(void);
-int mock_get_cc_rp3a0_rd_l(void);
-int mock_get_cfg_cc1_rp3a0_rd_l(void);
-int mock_set_cc1_rp3a0_rd_l(int v);
-void mock_set_host_cc_sink_voltage(int v);
-void mock_set_host_cc_source_voltage(int v);
-int mock_get_ct_cc1_rpusb(void);
-int mock_get_ct_cc2_rpusb(void);
-
-/**
- * Set Charge-Through Rp or Rd on CC lines
- *
- * @param pull      Either TYPEC_CC_RP or TYPEC_CC_RD
- * @param rp_value  When pull is RP, set this to
- *                  TYPEC_RP_USB or TYPEC_RP_1A5. Ignored
- *                  for TYPEC_CC_RD
- */
-void vpd_ct_set_pull(int pull, int rp_value);
-
-/**
- * Get the status of the Charge-Through CC lines
- *
- * @param cc1  Either TYPEC_CC_VOLT_OPEN,
- *		      TYPEC_CC_VOLT_RA,
- *                    TYPEC_CC_VOLT_RD,
- *                    any other value is considered RP
- * @param cc2  Either TYPEC_CC_VOLT_OPEN,
- *		      TYPEC_CC_VOLT_RA,
- *		      TYPEC_CC_VOLT_RD,
- *		      any other value is considered RP
- */
-void vpd_ct_get_cc(int *cc1, int *cc2);
-
-/**
- * Set Host Rp or Rd on CC lines
- *
- * @param pull      Either TYPEC_CC_RP or TYPEC_CC_RD
- * @param rp_value  When pull is RP, set this to
- *                  TYPEC_RP_USB or TYPEC_RP_1A5. Ignored
- *                  for TYPEC_CC_RD
- */
-void vpd_host_set_pull(int pull, int rp_value);
-
-/**
- * Get the status of the Host CC line
- *
- * @param cc  Either TYPEC_CC_VOLT_SNK_DEF, TYPEC_CC_VOLT_SNK_1_5,
- *                    TYPEC_CC_VOLT_SNK_3_0, or TYPEC_CC_RD
- */
-void vpd_host_get_cc(int *cc);
-
-/**
- * Set RX Enable flag
- *
- * @param en  1 for enable, 0 for disable
- */
-void vpd_rx_enable(int en);
-
-/**
- * Configure the cc_vpdmcu pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc_vpdmcu(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc1_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc2_rp3a0_rd_l pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc1_rpusb_odh pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc2_rpusb_odh pin as ADC, CMP, or GPO
- *
- * @param cfg  PIN_ADC, PIN_CMP, or PIN_GPO
- * @param en   When cfg is PIN_GPO, 1 sets pin high
- *             and 0 sets pin low. Else ignored
- */
-void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en);
-
-/**
- * Configure the cc_db_en_od pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_db_en_od(enum vpd_gpo val);
-
-/**
- * Configure the cc_rpusb_odh pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_rpusb_odh(enum vpd_gpo val);
-
-/**
- * Configure the cc_rp1a5_odh pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc_rp1a5_odh(enum vpd_gpo val);
-
-/**
- * Configure the cc1_cc2_db_en_l pin to High-Impedance, low, or high
- *
- * @param val  GPO_HZ, GPO_HIGH, GPO_LOW
- */
-void vpd_cc1_cc2_db_en_l(enum vpd_gpo val);
-
-/**
- * Get status of host vbus
- *
- * @return 1 if host vbus is present, else 0
- */
-int vpd_is_host_vbus_present(void);
-
-/**
- * Get status of charge-through vbus
- *
- * @return 1 if charge-through vbus is present, else 0
- */
-int vpd_is_ct_vbus_present(void);
-
-/**
- * Get status of vconn
- *
- * @return 1 if vconn is present, else 0
- */
-int vpd_is_vconn_present(void);
-
-/**
- * Read Host VBUS voltage. Range from 22000mV to 3000mV
- *
- * @return vbus voltage
- */
-int vpd_read_host_vbus(void);
-
-/**
- * Read Host CC voltage.
- *
- * @return cc voltage
- */
-int vpd_read_cc_host(void);
-
-/**
- * Read voltage on cc_vpdmcu pin
- *
- * @return cc_vpdmcu voltage
- */
-int vpd_read_cc_vpdmcu(void);
-
-/**
- * Read charge-through VBUS voltage. Range from 22000mV to 3000mV
- *
- * @return charge-through vbus voltage
- */
-int vpd_read_ct_vbus(void);
-
-/**
- * Read VCONN Voltage. Range from 5500mV to 3000mV
- *
- * @return vconn voltage
- */
-int vpd_read_vconn(void);
-
-/**
- * Turn ON/OFF Red LED. Should be off when performing power
- * measurements.
- *
- * @param on 0 turns LED off, any other value turns it ON
- */
-void vpd_red_led(int on);
-
-/**
- * Turn ON/OFF Green LED. Should be off when performing power
- * measurements.
- *
- * @param on 0 turns LED off, any other value turns it ON
- */
-void vpd_green_led(int on);
-
-/**
- * Connects/Disconnects the Host VBUS to the Charge-Through VBUS.
- *
- * @param en 0 disconnectes the VBUS, any other value connects VBUS.
- */
-void vpd_vbus_pass_en(int en);
-
-/**
- * Preset Billboard device
- *
- * @param bb  BB_NONE no billboard presented,
- *            BB_SRC source connected but not in charge-through
- *            BB_SNK sink connected
- */
-void vpd_present_billboard(enum vpd_billboard bb);
-
-/**
- * Enables the MCU to host cc communication
- *
- * @param en 1 enabled, 0 disabled
- */
-void vpd_mcu_cc_en(int en);
-
-/**
- * Selects which supply to power the VPD from
- *
- * @param en PWR_VCONN or PWR_VBUS
- */
-void vpd_vconn_pwr_sel_odl(enum vpd_pwr en);
-
-/**
- * Controls if the Charge-Through's CC1, CC2, or neither is
- * connected to Host CC
- *
- * @param sel CT_OPEN neither, CT_CC1 cc1, CT_CC2 cc2
- */
-void vpd_ct_cc_sel(enum vpd_cc sel);
-
-#endif /* __CROS_EC_VPD_API_H */
diff --git a/test/x25519.c b/test/x25519.c
deleted file mode 120000
index 75aefa9842..0000000000
--- a/test/x25519.c
+++ /dev/null
@@ -1 +0,0 @@
-../third_party/boringssl/test/x25519.c
\ No newline at end of file
diff --git a/test/x25519.tasklist b/test/x25519.tasklist
deleted file mode 100644
index 80072bb620..0000000000
--- a/test/x25519.tasklist
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TEST_TASK_LIST
diff --git a/third_party/bmi260/LICENSE b/third_party/bmi260/LICENSE
deleted file mode 100644
index 11a00c4a64..0000000000
--- a/third_party/bmi260/LICENSE
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2020 Bosch Sensortec GmbH. All rights reserved.
- *
- * BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
diff --git a/third_party/bmi260/METADATA b/third_party/bmi260/METADATA
deleted file mode 100644
index a2006da904..0000000000
--- a/third_party/bmi260/METADATA
+++ /dev/null
@@ -1,15 +0,0 @@
-name: "BMI260 implementation"
-description:
-    "Hex encoded binary for BMI260 driver initial configuration"
-
-third_party {
-  url {
-    type: HOMEPAGE
-    value: "https://www.bosch-sensortec.com/"
-  }
-  version: "v2.46.1"
-  last_upgrade_date { year: 2020 month: 01 day: 10 }
-  license_type: NOTICE
-  local_modifications: "Created LICENSE file."
-    "Adapted code to work with EC codebase."
-}
diff --git a/third_party/bmi260/accelgyro_bmi260_config_tbin.h b/third_party/bmi260/accelgyro_bmi260_config_tbin.h
deleted file mode 100644
index 11a4a90be5..0000000000
--- a/third_party/bmi260/accelgyro_bmi260_config_tbin.h
+++ /dev/null
@@ -1,703 +0,0 @@
-/*
- * Copyright (c) 2020 Bosch Sensortec GmbH. All rights reserved.
- *
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * @file accelgyro_bmi260_config_tbin.c
- * @date 2020-01-10
- * @version v2.46.1
- *
- */
-
-#include "common.h"
-
-const unsigned char __init_rom g_bmi260_config_tbin[] = {
-	0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x63, 0xb3, 0xc8, 0x2e, 0x00, 0x2e,
-	0x80, 0x2e, 0x15, 0x03, 0x80, 0x2e, 0xbb, 0xb4, 0x80, 0x2e, 0x91, 0x03,
-	0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0xe7, 0xb3, 0x50, 0x30, 0x21, 0x2e,
-	0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x4a, 0xf1, 0x21, 0x2e, 0x6a, 0xf5,
-	0x80, 0x2e, 0xe0, 0x01, 0x0d, 0x0d, 0x01, 0x00, 0x22, 0x00, 0x76, 0x00,
-	0x00, 0x10, 0x00, 0x10, 0xc8, 0x00, 0x01, 0x1c, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
-	0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0xfd, 0x2d, 0xe4, 0x78,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0d, 0x00, 0x00,
-	0x88, 0x00, 0x05, 0xe0, 0xaa, 0x38, 0x05, 0xe0, 0x90, 0x30, 0x86, 0x00,
-	0x30, 0x0a, 0x80, 0x40, 0x10, 0x27, 0xe8, 0x73, 0x04, 0x30, 0x00, 0x02,
-	0x00, 0x01, 0x00, 0x30, 0x10, 0x0b, 0x09, 0x08, 0xfa, 0x00, 0x96, 0x00,
-	0x4b, 0x09, 0x11, 0x00, 0x11, 0x00, 0x02, 0x00, 0x00, 0x00, 0x22, 0x07,
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-	0x7c, 0x86, 0x85, 0x52, 0x09, 0x2e, 0x7f, 0x0f, 0x8b, 0x54, 0xc4, 0x42,
-	0xd3, 0x86, 0x54, 0x40, 0x55, 0x40, 0x94, 0x42, 0x85, 0x42, 0x21, 0x2e,
-	0x6c, 0x01, 0x42, 0x40, 0x25, 0x2e, 0xfd, 0xf3, 0xc0, 0x42, 0x7e, 0x82,
-	0x05, 0x2e, 0xd7, 0x00, 0x80, 0xb2, 0x14, 0x2f, 0x05, 0x2e, 0x89, 0x00,
-	0x27, 0xbd, 0x2f, 0xb9, 0x80, 0x90, 0x02, 0x2f, 0x21, 0x2e, 0x6f, 0xf5,
-	0x0c, 0x2d, 0x07, 0x2e, 0x80, 0x0f, 0x14, 0x30, 0x1c, 0x09, 0x05, 0x2e,
-	0x77, 0xf7, 0x89, 0x56, 0x47, 0xbe, 0x93, 0x08, 0x94, 0x0a, 0x25, 0x2e,
-	0x77, 0xf7, 0xb3, 0x54, 0x50, 0x42, 0x4a, 0x0e, 0xfc, 0x2f, 0xb8, 0x2e,
-	0x50, 0x50, 0x02, 0x30, 0x43, 0x86, 0xb1, 0x50, 0xfb, 0x7f, 0xe3, 0x7f,
-	0xd2, 0x7f, 0xc0, 0x7f, 0xb1, 0x7f, 0x00, 0x2e, 0x41, 0x40, 0x00, 0x40,
-	0x48, 0x04, 0x98, 0x2e, 0x74, 0xc0, 0x1e, 0xaa, 0xd3, 0x6f, 0x14, 0x30,
-	0xb1, 0x6f, 0xe3, 0x22, 0xc0, 0x6f, 0x52, 0x40, 0xe4, 0x6f, 0x4c, 0x0e,
-	0x12, 0x42, 0xd3, 0x7f, 0xeb, 0x2f, 0x03, 0x2e, 0x95, 0x0f, 0x40, 0x90,
-	0x11, 0x30, 0x03, 0x2f, 0x23, 0x2e, 0x95, 0x0f, 0x02, 0x2c, 0x00, 0x30,
-	0xd0, 0x6f, 0xfb, 0x6f, 0xb0, 0x5f, 0xb8, 0x2e, 0x40, 0x50, 0xf1, 0x7f,
-	0x0a, 0x25, 0x3c, 0x86, 0xeb, 0x7f, 0x41, 0x33, 0x22, 0x30, 0x98, 0x2e,
-	0xc2, 0xc4, 0xd3, 0x6f, 0xf4, 0x30, 0xdc, 0x09, 0xb7, 0x58, 0xc2, 0x6f,
-	0x94, 0x09, 0xb9, 0x58, 0x6a, 0xbb, 0xdc, 0x08, 0xb4, 0xb9, 0xb1, 0xbd,
-	0xb5, 0x5a, 0x95, 0x08, 0x21, 0xbd, 0xf6, 0xbf, 0x77, 0x0b, 0x51, 0xbe,
-	0xf1, 0x6f, 0xeb, 0x6f, 0x52, 0x42, 0x54, 0x42, 0xc0, 0x2e, 0x43, 0x42,
-	0xc0, 0x5f, 0x50, 0x50, 0xcd, 0x50, 0x31, 0x30, 0x11, 0x42, 0xfb, 0x7f,
-	0x7b, 0x30, 0x0b, 0x42, 0x11, 0x30, 0x02, 0x80, 0x23, 0x33, 0x01, 0x42,
-	0x03, 0x00, 0x07, 0x2e, 0x80, 0x03, 0x05, 0x2e, 0xd5, 0x00, 0x49, 0x52,
-	0xe2, 0x7f, 0xd3, 0x7f, 0xc0, 0x7f, 0x98, 0x2e, 0xb6, 0x0e, 0xd1, 0x6f,
-	0x08, 0x0a, 0x1a, 0x25, 0x7b, 0x86, 0xd0, 0x7f, 0x01, 0x33, 0x12, 0x30,
-	0x98, 0x2e, 0xc2, 0xc4, 0xd1, 0x6f, 0x08, 0x0a, 0x00, 0xb2, 0x0d, 0x2f,
-	0xe3, 0x6f, 0x01, 0x2e, 0x80, 0x03, 0x51, 0x30, 0xc7, 0x86, 0x23, 0x2e,
-	0x21, 0xf2, 0x08, 0xbc, 0xc0, 0x42, 0x98, 0x2e, 0x0b, 0x03, 0x00, 0x2e,
-	0x00, 0x2e, 0xd0, 0x2e, 0xb0, 0x6f, 0x0b, 0xb8, 0x03, 0x2e, 0x1b, 0x00,
-	0x08, 0x1a, 0xb0, 0x7f, 0x70, 0x30, 0x04, 0x2f, 0x21, 0x2e, 0x21, 0xf2,
-	0x00, 0x2e, 0x00, 0x2e, 0xd0, 0x2e, 0x98, 0x2e, 0x6d, 0xc0, 0x98, 0x2e,
-	0x5d, 0xc0, 0xbb, 0x50, 0x98, 0x2e, 0x46, 0xc3, 0xbd, 0x50, 0x98, 0x2e,
-	0xfc, 0xc5, 0xbf, 0x50, 0x21, 0x2e, 0x77, 0x01, 0x6f, 0x50, 0x98, 0x2e,
-	0x64, 0xcf, 0xc3, 0x50, 0x21, 0x2e, 0x85, 0x01, 0xc1, 0x56, 0xc5, 0x52,
-	0x27, 0x2e, 0x86, 0x01, 0x23, 0x2e, 0x87, 0x01, 0xc7, 0x50, 0x98, 0x2e,
-	0x53, 0xc7, 0xc9, 0x50, 0x98, 0x2e, 0x44, 0xcb, 0x10, 0x30, 0x98, 0x2e,
-	0xcd, 0xb6, 0x20, 0x26, 0xc0, 0x6f, 0x02, 0x31, 0x12, 0x42, 0xab, 0x33,
-	0x0b, 0x42, 0x37, 0x80, 0x01, 0x30, 0x01, 0x42, 0xf3, 0x37, 0xcf, 0x52,
-	0xd3, 0x50, 0x44, 0x40, 0xa2, 0x0a, 0x42, 0x42, 0x8b, 0x31, 0x09, 0x2e,
-	0x5e, 0xf7, 0xd1, 0x54, 0xe3, 0x08, 0x83, 0x42, 0x1b, 0x42, 0x23, 0x33,
-	0x4b, 0x00, 0xbc, 0x84, 0x0b, 0x40, 0x33, 0x30, 0x83, 0x42, 0x0b, 0x42,
-	0xe0, 0x7f, 0xd1, 0x7f, 0x98, 0x2e, 0x07, 0x02, 0xd1, 0x6f, 0x80, 0x30,
-	0x40, 0x42, 0x03, 0x30, 0xe0, 0x6f, 0xcb, 0x54, 0x04, 0x30, 0x00, 0x2e,
-	0x00, 0x2e, 0x01, 0x89, 0x62, 0x0e, 0xfa, 0x2f, 0x43, 0x42, 0x11, 0x30,
-	0xfb, 0x6f, 0xc0, 0x2e, 0x01, 0x42, 0xb0, 0x5f, 0xc1, 0x4a, 0x00, 0x00,
-	0x6d, 0x57, 0x00, 0x00, 0x77, 0x8e, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff,
-	0xd3, 0xff, 0xff, 0xff, 0xe5, 0xff, 0xff, 0xff, 0xee, 0xe1, 0xff, 0xff,
-	0x7c, 0x13, 0x00, 0x00, 0x46, 0xe6, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
-	0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0xfd, 0x2d
-};
-
-BUILD_ASSERT(ARRAY_SIZE(g_bmi260_config_tbin) == 8192);
-const unsigned int g_bmi260_config_tbin_len = ARRAY_SIZE(g_bmi260_config_tbin);
-
diff --git a/third_party/boringssl/LICENSE b/third_party/boringssl/LICENSE
deleted file mode 100644
index 49c41fa7af..0000000000
--- a/third_party/boringssl/LICENSE
+++ /dev/null
@@ -1,251 +0,0 @@
-BoringSSL is a fork of OpenSSL. As such, large parts of it fall under OpenSSL
-licensing. Files that are completely new have a Google copyright and an ISC
-license. This license is reproduced at the bottom of this file.
-
-Contributors to BoringSSL are required to follow the CLA rules for Chromium:
-https://cla.developers.google.com/clas
-
-Files in third_party/ have their own licenses, as described therein. The MIT
-license, for third_party/fiat, which, unlike other third_party directories, is
-compiled into non-test libraries, is included below.
-
-The OpenSSL toolkit stays under a dual license, i.e. both the conditions of the
-OpenSSL License and the original SSLeay license apply to the toolkit. See below
-for the actual license texts. Actually both licenses are BSD-style Open Source
-licenses. In case of any license issues related to OpenSSL please contact
-openssl-core@openssl.org.
-
-The following are Google-internal bug numbers where explicit permission from
-some authors is recorded for use of their work. (This is purely for our own
-record keeping.)
-  27287199
-  27287880
-  27287883
-
-  OpenSSL License
-  ---------------
-
-/* ====================================================================
- * Copyright (c) 1998-2011 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ====================================================================
- *
- * This product includes cryptographic software written by Eric Young
- * (eay@cryptsoft.com).  This product includes software written by Tim
- * Hudson (tjh@cryptsoft.com).
- *
- */
-
- Original SSLeay License
- -----------------------
-
-/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
- * All rights reserved.
- *
- * This package is an SSL implementation written
- * by Eric Young (eay@cryptsoft.com).
- * The implementation was written so as to conform with Netscapes SSL.
- * 
- * This library is free for commercial and non-commercial use as long as
- * the following conditions are aheared to.  The following conditions
- * apply to all code found in this distribution, be it the RC4, RSA,
- * lhash, DES, etc., code; not just the SSL code.  The SSL documentation
- * included with this distribution is covered by the same copyright terms
- * except that the holder is Tim Hudson (tjh@cryptsoft.com).
- * 
- * Copyright remains Eric Young's, and as such any Copyright notices in
- * the code are not to be removed.
- * If this package is used in a product, Eric Young should be given attribution
- * as the author of the parts of the library used.
- * This can be in the form of a textual message at program startup or
- * in documentation (online or textual) provided with the package.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *    "This product includes cryptographic software written by
- *     Eric Young (eay@cryptsoft.com)"
- *    The word 'cryptographic' can be left out if the rouines from the library
- *    being used are not cryptographic related :-).
- * 4. If you include any Windows specific code (or a derivative thereof) from 
- *    the apps directory (application code) you must include an acknowledgement:
- *    "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
- * 
- * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * 
- * The licence and distribution terms for any publically available version or
- * derivative of this code cannot be changed.  i.e. this code cannot simply be
- * copied and put under another distribution licence
- * [including the GNU Public Licence.]
- */
-
-
-ISC license used for completely new code in BoringSSL:
-
-/* Copyright (c) 2015, Google Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-
-The code in third_party/fiat carries the MIT license:
-
-Copyright (c) 2015-2016 the fiat-crypto authors (see
-https://github.com/mit-plv/fiat-crypto/blob/master/AUTHORS).
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-
-
-Licenses for support code
--------------------------
-
-Parts of the TLS test suite are under the Go license. This code is not included
-in BoringSSL (i.e. libcrypto and libssl) when compiled, however, so
-distributing code linked against BoringSSL does not trigger this license:
-
-Copyright (c) 2009 The Go Authors. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-   * Redistributions of source code must retain the above copyright
-notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above
-copyright notice, this list of conditions and the following disclaimer
-in the documentation and/or other materials provided with the
-distribution.
-   * Neither the name of Google Inc. nor the names of its
-contributors may be used to endorse or promote products derived from
-this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-BoringSSL uses the Chromium test infrastructure to run a continuous build,
-trybots etc. The scripts which manage this, and the script for generating build
-metadata, are under the Chromium license. Distributing code linked against
-BoringSSL does not trigger this license.
-
-Copyright 2015 The Chromium Authors. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-   * Redistributions of source code must retain the above copyright
-notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above
-copyright notice, this list of conditions and the following disclaimer
-in the documentation and/or other materials provided with the
-distribution.
-   * Neither the name of Google Inc. nor the names of its
-contributors may be used to endorse or promote products derived from
-this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/third_party/boringssl/METADATA b/third_party/boringssl/METADATA
deleted file mode 100644
index 23545b2c8b..0000000000
--- a/third_party/boringssl/METADATA
+++ /dev/null
@@ -1,16 +0,0 @@
-name: "BoringSSL"
-description:
-    "BoringSSL is a fork of OpenSSL that is designed to meet Google's needs."
-
-third_party {
-  url {
-    type: GIT
-    value: "https://boringssl.googlesource.com/boringssl/"
-  }
-  version: "859679518d3433cdd0dd6cf534bd7bdb2a32dd60"
-  # TODO(crbug.com/884905): Refresh curve25519 to latest boringssl
-  # version_curve25519: "c034e2d3ce16df5f89134515bc113eb4f3a28e0e"
-  last_upgrade_date { year: 2018 month: 07 day: 05 }
-  license_type: NOTICE
-  local_modifications: "Adapted code to work with EC codebase."
-}
\ No newline at end of file
diff --git a/third_party/boringssl/common/aes-gcm.c b/third_party/boringssl/common/aes-gcm.c
deleted file mode 100644
index edb98b88b3..0000000000
--- a/third_party/boringssl/common/aes-gcm.c
+++ /dev/null
@@ -1,883 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2008 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#include "aes-gcm.h"
-#include "common.h"
-#include "endian.h"
-#include "util.h"
-
-#define STRICT_ALIGNMENT 1
-
-#define OPENSSL_memcpy memcpy
-#define OPENSSL_memset memset
-#define CRYPTO_memcmp safe_memcmp
-
-#ifdef CORE_CORTEX_M
-#define GHASH_ASM
-#define OPENSSL_ARM
-#define __ARM_ARCH__ 7
-#endif
-
-static inline uint32_t CRYPTO_bswap4(uint32_t x) {
-  return __builtin_bswap32(x);
-}
-
-static inline uint64_t CRYPTO_bswap8(uint64_t x) {
-  return __builtin_bswap64(x);
-}
-
-static inline size_t load_word_le(const void *in) {
-  size_t v;
-  OPENSSL_memcpy(&v, in, sizeof(v));
-  return v;
-}
-
-static inline void store_word_le(void *out, size_t v) {
-  OPENSSL_memcpy(out, &v, sizeof(v));
-}
-
-#define PACK(s) ((size_t)(s) << (sizeof(size_t) * 8 - 16))
-#define REDUCE1BIT(V)                                                 \
-  do {                                                                \
-    if (sizeof(size_t) == 8) {                                        \
-      uint64_t T = UINT64_C(0xe100000000000000) & (0 - ((V).lo & 1)); \
-      (V).lo = ((V).hi << 63) | ((V).lo >> 1);                        \
-      (V).hi = ((V).hi >> 1) ^ T;                                     \
-    } else {                                                          \
-      uint32_t T = 0xe1000000U & (0 - (uint32_t)((V).lo & 1));        \
-      (V).lo = ((V).hi << 63) | ((V).lo >> 1);                        \
-      (V).hi = ((V).hi >> 1) ^ ((uint64_t)T << 32);                   \
-    }                                                                 \
-  } while (0)
-
-static void gcm_init_4bit(u128 Htable[16], uint64_t H[2]) {
-  u128 V;
-
-  Htable[0].hi = 0;
-  Htable[0].lo = 0;
-  V.hi = H[0];
-  V.lo = H[1];
-
-  Htable[8] = V;
-  REDUCE1BIT(V);
-  Htable[4] = V;
-  REDUCE1BIT(V);
-  Htable[2] = V;
-  REDUCE1BIT(V);
-  Htable[1] = V;
-  Htable[3].hi = V.hi ^ Htable[2].hi, Htable[3].lo = V.lo ^ Htable[2].lo;
-  V = Htable[4];
-  Htable[5].hi = V.hi ^ Htable[1].hi, Htable[5].lo = V.lo ^ Htable[1].lo;
-  Htable[6].hi = V.hi ^ Htable[2].hi, Htable[6].lo = V.lo ^ Htable[2].lo;
-  Htable[7].hi = V.hi ^ Htable[3].hi, Htable[7].lo = V.lo ^ Htable[3].lo;
-  V = Htable[8];
-  Htable[9].hi = V.hi ^ Htable[1].hi, Htable[9].lo = V.lo ^ Htable[1].lo;
-  Htable[10].hi = V.hi ^ Htable[2].hi, Htable[10].lo = V.lo ^ Htable[2].lo;
-  Htable[11].hi = V.hi ^ Htable[3].hi, Htable[11].lo = V.lo ^ Htable[3].lo;
-  Htable[12].hi = V.hi ^ Htable[4].hi, Htable[12].lo = V.lo ^ Htable[4].lo;
-  Htable[13].hi = V.hi ^ Htable[5].hi, Htable[13].lo = V.lo ^ Htable[5].lo;
-  Htable[14].hi = V.hi ^ Htable[6].hi, Htable[14].lo = V.lo ^ Htable[6].lo;
-  Htable[15].hi = V.hi ^ Htable[7].hi, Htable[15].lo = V.lo ^ Htable[7].lo;
-
-#if defined(GHASH_ASM) && defined(OPENSSL_ARM)
-  for (int j = 0; j < 16; ++j) {
-    V = Htable[j];
-    Htable[j].hi = V.lo;
-    Htable[j].lo = V.hi;
-  }
-#endif
-}
-
-#if !defined(GHASH_ASM) || defined(OPENSSL_AARCH64) || defined(OPENSSL_PPC64LE)
-static const size_t rem_4bit[16] = {
-    PACK(0x0000), PACK(0x1C20), PACK(0x3840), PACK(0x2460),
-    PACK(0x7080), PACK(0x6CA0), PACK(0x48C0), PACK(0x54E0),
-    PACK(0xE100), PACK(0xFD20), PACK(0xD940), PACK(0xC560),
-    PACK(0x9180), PACK(0x8DA0), PACK(0xA9C0), PACK(0xB5E0)};
-
-static void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]) {
-  u128 Z;
-  int cnt = 15;
-  size_t rem, nlo, nhi;
-
-  nlo = ((const uint8_t *)Xi)[15];
-  nhi = nlo >> 4;
-  nlo &= 0xf;
-
-  Z.hi = Htable[nlo].hi;
-  Z.lo = Htable[nlo].lo;
-
-  while (1) {
-    rem = (size_t)Z.lo & 0xf;
-    Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-    Z.hi = (Z.hi >> 4);
-    if (sizeof(size_t) == 8) {
-      Z.hi ^= rem_4bit[rem];
-    } else {
-      Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-    }
-
-    Z.hi ^= Htable[nhi].hi;
-    Z.lo ^= Htable[nhi].lo;
-
-    if (--cnt < 0) {
-      break;
-    }
-
-    nlo = ((const uint8_t *)Xi)[cnt];
-    nhi = nlo >> 4;
-    nlo &= 0xf;
-
-    rem = (size_t)Z.lo & 0xf;
-    Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-    Z.hi = (Z.hi >> 4);
-    if (sizeof(size_t) == 8) {
-      Z.hi ^= rem_4bit[rem];
-    } else {
-      Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-    }
-
-    Z.hi ^= Htable[nlo].hi;
-    Z.lo ^= Htable[nlo].lo;
-  }
-
-  Xi[0] = CRYPTO_bswap8(Z.hi);
-  Xi[1] = CRYPTO_bswap8(Z.lo);
-}
-
-// Streamed gcm_mult_4bit, see CRYPTO_gcm128_[en|de]crypt for
-// details... Compiler-generated code doesn't seem to give any
-// performance improvement, at least not on x86[_64]. It's here
-// mostly as reference and a placeholder for possible future
-// non-trivial optimization[s]...
-static void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len) {
-  u128 Z;
-  int cnt;
-  size_t rem, nlo, nhi;
-
-  do {
-    cnt = 15;
-    nlo = ((const uint8_t *)Xi)[15];
-    nlo ^= inp[15];
-    nhi = nlo >> 4;
-    nlo &= 0xf;
-
-    Z.hi = Htable[nlo].hi;
-    Z.lo = Htable[nlo].lo;
-
-    while (1) {
-      rem = (size_t)Z.lo & 0xf;
-      Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-      Z.hi = (Z.hi >> 4);
-      if (sizeof(size_t) == 8) {
-        Z.hi ^= rem_4bit[rem];
-      } else {
-        Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-      }
-
-      Z.hi ^= Htable[nhi].hi;
-      Z.lo ^= Htable[nhi].lo;
-
-      if (--cnt < 0) {
-        break;
-      }
-
-      nlo = ((const uint8_t *)Xi)[cnt];
-      nlo ^= inp[cnt];
-      nhi = nlo >> 4;
-      nlo &= 0xf;
-
-      rem = (size_t)Z.lo & 0xf;
-      Z.lo = (Z.hi << 60) | (Z.lo >> 4);
-      Z.hi = (Z.hi >> 4);
-      if (sizeof(size_t) == 8) {
-        Z.hi ^= rem_4bit[rem];
-      } else {
-        Z.hi ^= (uint64_t)rem_4bit[rem] << 32;
-      }
-
-      Z.hi ^= Htable[nlo].hi;
-      Z.lo ^= Htable[nlo].lo;
-    }
-
-    Xi[0] = CRYPTO_bswap8(Z.hi);
-    Xi[1] = CRYPTO_bswap8(Z.lo);
-  } while (inp += 16, len -= 16);
-}
-#else  // GHASH_ASM
-void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                    size_t len);
-#endif
-
-#define GCM_MUL(ctx, Xi) gcm_gmult_4bit((ctx)->Xi.u, (ctx)->Htable)
-#if defined(GHASH_ASM)
-#define GHASH(ctx, in, len) gcm_ghash_4bit((ctx)->Xi.u, (ctx)->Htable, in, len)
-// GHASH_CHUNK is "stride parameter" missioned to mitigate cache
-// trashing effect. In other words idea is to hash data while it's
-// still in L1 cache after encryption pass...
-#define GHASH_CHUNK (3 * 1024)
-#endif
-
-
-#if defined(GHASH_ASM)
-
-#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
-#define GCM_FUNCREF_4BIT
-void gcm_init_clmul(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_clmul(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_clmul(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                     size_t len);
-
-#if defined(OPENSSL_X86_64)
-#define GHASH_ASM_X86_64
-void gcm_init_avx(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_avx(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_avx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *in,
-                   size_t len);
-#define AESNI_GCM
-size_t aesni_gcm_encrypt(const uint8_t *in, uint8_t *out, size_t len,
-                         const void *key, uint8_t ivec[16], uint64_t *Xi);
-size_t aesni_gcm_decrypt(const uint8_t *in, uint8_t *out, size_t len,
-                         const void *key, uint8_t ivec[16], uint64_t *Xi);
-#endif
-
-#if defined(OPENSSL_X86)
-#define GHASH_ASM_X86
-void gcm_gmult_4bit_mmx(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_4bit_mmx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                        size_t len);
-#endif
-
-#elif defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
-#if __ARM_ARCH__ >= 7
-#define GHASH_ASM_ARM
-#define GCM_FUNCREF_4BIT
-
-#if defined(OPENSSL_ARM_PMULL)
-static int pmull_capable(void) {
-  return CRYPTO_is_ARMv8_PMULL_capable();
-}
-
-void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                  size_t len);
-#else
-static int pmull_capable(void) {
-  return 0;
-}
-static void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]) {
-
-}
-static void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]) {
-
-}
-static void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16],
-                         const uint8_t *inp, size_t len) {
-
-}
-#endif
-
-#if defined(OPENSSL_ARM_NEON)
-// 32-bit ARM also has support for doing GCM with NEON instructions.
-static int neon_capable(void) {
-  return CRYPTO_is_NEON_capable();
-}
-
-void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                    size_t len);
-#else
-// AArch64 only has the ARMv8 versions of functions.
-static int neon_capable(void) {
-  return 0;
-}
-static void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]) {
-
-}
-static void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]) {
-
-}
-static void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len) {
-
-}
-#endif
-
-#endif
-#elif defined(OPENSSL_PPC64LE)
-#define GHASH_ASM_PPC64LE
-#define GCM_FUNCREF_4BIT
-void gcm_init_p8(u128 Htable[16], const uint64_t Xi[2]);
-void gcm_gmult_p8(uint64_t Xi[2], const u128 Htable[16]);
-void gcm_ghash_p8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                  size_t len);
-#endif
-#endif
-
-#ifdef GCM_FUNCREF_4BIT
-#undef GCM_MUL
-#define GCM_MUL(ctx, Xi) (*gcm_gmult_p)((ctx)->Xi.u, (ctx)->Htable)
-#ifdef GHASH
-#undef GHASH
-#define GHASH(ctx, in, len) (*gcm_ghash_p)((ctx)->Xi.u, (ctx)->Htable, in, len)
-#endif
-#endif
-
-#ifdef GHASH
-// kSizeTWithoutLower4Bits is a mask that can be used to zero the lower four
-// bits of a |size_t|.
-static const size_t kSizeTWithoutLower4Bits = (size_t) -16;
-#endif
-
-static void CRYPTO_ghash_init(gmult_func *out_mult, ghash_func *out_hash,
-                              u128 *out_key, u128 out_table[16],
-                              const uint8_t *gcm_key) {
-
-  union {
-    uint64_t u[2];
-    uint8_t c[16];
-  } H;
-
-  OPENSSL_memcpy(H.c, gcm_key, 16);
-
-  // H is stored in host byte order
-  H.u[0] = CRYPTO_bswap8(H.u[0]);
-  H.u[1] = CRYPTO_bswap8(H.u[1]);
-
-  OPENSSL_memcpy(out_key, H.c, 16);
-
-#if defined(GHASH_ASM_X86_64)
-  if (crypto_gcm_clmul_enabled()) {
-    if (((OPENSSL_ia32cap_get()[1] >> 22) & 0x41) == 0x41) {  // AVX+MOVBE
-      gcm_init_avx(out_table, H.u);
-      *out_mult = gcm_gmult_avx;
-      *out_hash = gcm_ghash_avx;
-      *out_is_avx = 1;
-      return;
-    }
-    gcm_init_clmul(out_table, H.u);
-    *out_mult = gcm_gmult_clmul;
-    *out_hash = gcm_ghash_clmul;
-    return;
-  }
-#elif defined(GHASH_ASM_X86)
-  if (crypto_gcm_clmul_enabled()) {
-    gcm_init_clmul(out_table, H.u);
-    *out_mult = gcm_gmult_clmul;
-    *out_hash = gcm_ghash_clmul;
-    return;
-  }
-#elif defined(GHASH_ASM_ARM)
-  if (pmull_capable()) {
-    gcm_init_v8(out_table, H.u);
-    *out_mult = gcm_gmult_v8;
-    *out_hash = gcm_ghash_v8;
-    return;
-  }
-
-  if (neon_capable()) {
-    gcm_init_neon(out_table, H.u);
-    *out_mult = gcm_gmult_neon;
-    *out_hash = gcm_ghash_neon;
-    return;
-  }
-#elif defined(GHASH_ASM_PPC64LE)
-  if (CRYPTO_is_PPC64LE_vcrypto_capable()) {
-    gcm_init_p8(out_table, H.u);
-    *out_mult = gcm_gmult_p8;
-    *out_hash = gcm_ghash_p8;
-    return;
-  }
-#endif
-
-  gcm_init_4bit(out_table, H.u);
-#if defined(GHASH_ASM_X86)
-  *out_mult = gcm_gmult_4bit_mmx;
-  *out_hash = gcm_ghash_4bit_mmx;
-#else
-  *out_mult = gcm_gmult_4bit;
-  *out_hash = gcm_ghash_4bit;
-#endif
-}
-
-void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *aes_key,
-                        block128_f block, int block_is_hwaes) {
-  OPENSSL_memset(ctx, 0, sizeof(*ctx));
-  ctx->block = block;
-
-  uint8_t gcm_key[16];
-  OPENSSL_memset(gcm_key, 0, sizeof(gcm_key));
-  (*block)(gcm_key, gcm_key, aes_key);
-
-  CRYPTO_ghash_init(&ctx->gmult, &ctx->ghash, &ctx->H, ctx->Htable,
-                    gcm_key);
-}
-
-void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key,
-                         const uint8_t *iv, size_t len) {
-  unsigned int ctr;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#endif
-
-  ctx->Yi.u[0] = 0;
-  ctx->Yi.u[1] = 0;
-  ctx->Xi.u[0] = 0;
-  ctx->Xi.u[1] = 0;
-  ctx->len.u[0] = 0;  // AAD length
-  ctx->len.u[1] = 0;  // message length
-  ctx->ares = 0;
-  ctx->mres = 0;
-
-  if (len == 12) {
-    OPENSSL_memcpy(ctx->Yi.c, iv, 12);
-    ctx->Yi.c[15] = 1;
-    ctr = 1;
-  } else {
-    uint64_t len0 = len;
-
-    while (len >= 16) {
-      for (size_t i = 0; i < 16; ++i) {
-        ctx->Yi.c[i] ^= iv[i];
-      }
-      GCM_MUL(ctx, Yi);
-      iv += 16;
-      len -= 16;
-    }
-    if (len) {
-      for (size_t i = 0; i < len; ++i) {
-        ctx->Yi.c[i] ^= iv[i];
-      }
-      GCM_MUL(ctx, Yi);
-    }
-    len0 <<= 3;
-    ctx->Yi.u[1] ^= CRYPTO_bswap8(len0);
-
-    GCM_MUL(ctx, Yi);
-    ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-  }
-
-  (*ctx->block)(ctx->Yi.c, ctx->EK0.c, key);
-  ++ctr;
-  ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-}
-
-int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len) {
-  unsigned int n;
-  uint64_t alen = ctx->len.u[0];
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  if (ctx->len.u[1]) {
-    return 0;
-  }
-
-  alen += len;
-  if (alen > (UINT64_C(1) << 61) || (sizeof(len) == 8 && alen < len)) {
-    return 0;
-  }
-  ctx->len.u[0] = alen;
-
-  n = ctx->ares;
-  if (n) {
-    while (n && len) {
-      ctx->Xi.c[n] ^= *(aad++);
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->ares = n;
-      return 1;
-    }
-  }
-
-  // Process a whole number of blocks.
-#ifdef GHASH
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    GHASH(ctx, aad, len_blocks);
-    aad += len_blocks;
-    len -= len_blocks;
-  }
-#else
-  while (len >= 16) {
-    for (size_t i = 0; i < 16; ++i) {
-      ctx->Xi.c[i] ^= aad[i];
-    }
-    GCM_MUL(ctx, Xi);
-    aad += 16;
-    len -= 16;
-  }
-#endif
-
-  // Process the remainder.
-  if (len != 0) {
-    n = (unsigned int)len;
-    for (size_t i = 0; i < len; ++i) {
-      ctx->Xi.c[i] ^= aad[i];
-    }
-  }
-
-  ctx->ares = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key,
-                          const uint8_t *in, uint8_t *out, size_t len) {
-  unsigned int n, ctr;
-  uint64_t mlen = ctx->len.u[1];
-  block128_f block = ctx->block;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  mlen += len;
-  if (mlen > ((UINT64_C(1) << 36) - 32) ||
-      (sizeof(len) == 8 && mlen < len)) {
-    return 0;
-  }
-  ctx->len.u[1] = mlen;
-
-  if (ctx->ares) {
-    // First call to encrypt finalizes GHASH(AAD)
-    GCM_MUL(ctx, Xi);
-    ctx->ares = 0;
-  }
-
-  ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-
-  n = ctx->mres;
-  if (n) {
-    while (n && len) {
-      ctx->Xi.c[n] ^= *(out++) = *(in++) ^ ctx->EKi.c[n];
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->mres = n;
-      return 1;
-    }
-  }
-  if (STRICT_ALIGNMENT &&
-      ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) {
-    for (size_t i = 0; i < len; ++i) {
-      if (n == 0) {
-        (*block)(ctx->Yi.c, ctx->EKi.c, key);
-        ++ctr;
-        ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      }
-      ctx->Xi.c[n] ^= out[i] = in[i] ^ ctx->EKi.c[n];
-      n = (n + 1) % 16;
-      if (n == 0) {
-        GCM_MUL(ctx, Xi);
-      }
-    }
-
-    ctx->mres = n;
-    return 1;
-  }
-#if defined(GHASH) && defined(GHASH_CHUNK)
-  while (len >= GHASH_CHUNK) {
-    size_t j = GHASH_CHUNK;
-
-    while (j) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      j -= 16;
-    }
-    GHASH(ctx, out - GHASH_CHUNK, GHASH_CHUNK);
-    len -= GHASH_CHUNK;
-  }
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    while (len >= 16) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      len -= 16;
-    }
-    GHASH(ctx, out - len_blocks, len_blocks);
-  }
-#else
-  while (len >= 16) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-      size_t tmp = load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)];
-      store_word_le(out + i, tmp);
-      ctx->Xi.t[i / sizeof(size_t)] ^= tmp;
-    }
-    GCM_MUL(ctx, Xi);
-    out += 16;
-    in += 16;
-    len -= 16;
-  }
-#endif
-  if (len) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    while (len--) {
-      ctx->Xi.c[n] ^= out[n] = in[n] ^ ctx->EKi.c[n];
-      ++n;
-    }
-  }
-
-  ctx->mres = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key,
-                          const unsigned char *in, unsigned char *out,
-                          size_t len) {
-  unsigned int n, ctr;
-  uint64_t mlen = ctx->len.u[1];
-  block128_f block = ctx->block;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#ifdef GHASH
-  void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp,
-                      size_t len) = ctx->ghash;
-#endif
-#endif
-
-  mlen += len;
-  if (mlen > ((UINT64_C(1) << 36) - 32) ||
-      (sizeof(len) == 8 && mlen < len)) {
-    return 0;
-  }
-  ctx->len.u[1] = mlen;
-
-  if (ctx->ares) {
-    // First call to decrypt finalizes GHASH(AAD)
-    GCM_MUL(ctx, Xi);
-    ctx->ares = 0;
-  }
-
-  ctr = CRYPTO_bswap4(ctx->Yi.d[3]);
-
-  n = ctx->mres;
-  if (n) {
-    while (n && len) {
-      uint8_t c = *(in++);
-      *(out++) = c ^ ctx->EKi.c[n];
-      ctx->Xi.c[n] ^= c;
-      --len;
-      n = (n + 1) % 16;
-    }
-    if (n == 0) {
-      GCM_MUL(ctx, Xi);
-    } else {
-      ctx->mres = n;
-      return 1;
-    }
-  }
-  if (STRICT_ALIGNMENT &&
-      ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) {
-    for (size_t i = 0; i < len; ++i) {
-      uint8_t c;
-      if (n == 0) {
-        (*block)(ctx->Yi.c, ctx->EKi.c, key);
-        ++ctr;
-        ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      }
-      c = in[i];
-      out[i] = c ^ ctx->EKi.c[n];
-      ctx->Xi.c[n] ^= c;
-      n = (n + 1) % 16;
-      if (n == 0) {
-        GCM_MUL(ctx, Xi);
-      }
-    }
-
-    ctx->mres = n;
-    return 1;
-  }
-#if defined(GHASH) && defined(GHASH_CHUNK)
-  while (len >= GHASH_CHUNK) {
-    size_t j = GHASH_CHUNK;
-
-    GHASH(ctx, in, GHASH_CHUNK);
-    while (j) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      j -= 16;
-    }
-    len -= GHASH_CHUNK;
-  }
-  size_t len_blocks = len & kSizeTWithoutLower4Bits;
-  if (len_blocks != 0) {
-    GHASH(ctx, in, len_blocks);
-    while (len >= 16) {
-      (*block)(ctx->Yi.c, ctx->EKi.c, key);
-      ++ctr;
-      ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-      for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-        store_word_le(out + i,
-                      load_word_le(in + i) ^ ctx->EKi.t[i / sizeof(size_t)]);
-      }
-      out += 16;
-      in += 16;
-      len -= 16;
-    }
-  }
-#else
-  while (len >= 16) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    for (size_t i = 0; i < 16; i += sizeof(size_t)) {
-      size_t c = load_word_le(in + i);
-      store_word_le(out + i, c ^ ctx->EKi.t[i / sizeof(size_t)]);
-      ctx->Xi.t[i / sizeof(size_t)] ^= c;
-    }
-    GCM_MUL(ctx, Xi);
-    out += 16;
-    in += 16;
-    len -= 16;
-  }
-#endif
-  if (len) {
-    (*block)(ctx->Yi.c, ctx->EKi.c, key);
-    ++ctr;
-    ctx->Yi.d[3] = CRYPTO_bswap4(ctr);
-    while (len--) {
-      uint8_t c = in[n];
-      ctx->Xi.c[n] ^= c;
-      out[n] = c ^ ctx->EKi.c[n];
-      ++n;
-    }
-  }
-
-  ctx->mres = n;
-  return 1;
-}
-
-int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len) {
-  uint64_t alen = ctx->len.u[0] << 3;
-  uint64_t clen = ctx->len.u[1] << 3;
-#ifdef GCM_FUNCREF_4BIT
-  void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult;
-#endif
-
-  if (ctx->mres || ctx->ares) {
-    GCM_MUL(ctx, Xi);
-  }
-
-  alen = CRYPTO_bswap8(alen);
-  clen = CRYPTO_bswap8(clen);
-
-  ctx->Xi.u[0] ^= alen;
-  ctx->Xi.u[1] ^= clen;
-  GCM_MUL(ctx, Xi);
-
-  ctx->Xi.u[0] ^= ctx->EK0.u[0];
-  ctx->Xi.u[1] ^= ctx->EK0.u[1];
-
-  if (tag && len <= sizeof(ctx->Xi)) {
-    return CRYPTO_memcmp(ctx->Xi.c, tag, len) == 0;
-  } else {
-    return 0;
-  }
-}
-
-void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, unsigned char *tag, size_t len) {
-  CRYPTO_gcm128_finish(ctx, NULL, 0);
-  OPENSSL_memcpy(tag, ctx->Xi.c,
-                 len <= sizeof(ctx->Xi.c) ? len : sizeof(ctx->Xi.c));
-}
-
-#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
-int crypto_gcm_clmul_enabled(void) {
-#ifdef GHASH_ASM
-  const uint32_t *ia32cap = OPENSSL_ia32cap_get();
-  return (ia32cap[0] & (1 << 24)) &&  // check FXSR bit
-         (ia32cap[1] & (1 << 1));     // check PCLMULQDQ bit
-#else
-  return 0;
-#endif
-}
-#endif
diff --git a/third_party/boringssl/common/aes.c b/third_party/boringssl/common/aes.c
deleted file mode 100644
index aa213eb907..0000000000
--- a/third_party/boringssl/common/aes.c
+++ /dev/null
@@ -1,806 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2002-2006 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#include "aes.h"
-#include "common.h"
-#include "endian.h"
-
-static inline uint32_t GETU32(const void *in) {
-  return be32toh(*(uint32_t *)in);
-}
-
-static inline void PUTU32(void *out, uint32_t v) {
-  *(uint32_t *)out = htobe32(v);
-}
-
-// Te0[x] = S [x].[02, 01, 01, 03];
-// Te1[x] = S [x].[03, 02, 01, 01];
-// Te2[x] = S [x].[01, 03, 02, 01];
-// Te3[x] = S [x].[01, 01, 03, 02];
-//
-// Td0[x] = Si[x].[0e, 09, 0d, 0b];
-// Td1[x] = Si[x].[0b, 0e, 09, 0d];
-// Td2[x] = Si[x].[0d, 0b, 0e, 09];
-// Td3[x] = Si[x].[09, 0d, 0b, 0e];
-// Td4[x] = Si[x].[01];
-
-static const uint32_t Te0[256] = {
-    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, 0xfff2f20dU,
-    0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, 0x60303050U, 0x02010103U,
-    0xce6767a9U, 0x562b2b7dU, 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U,
-    0xec76769aU, 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
-    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, 0x41adadecU,
-    0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, 0x239c9cbfU, 0x53a4a4f7U,
-    0xe4727296U, 0x9bc0c05bU, 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU,
-    0x4c26266aU, 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
-    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, 0xe2717193U,
-    0xabd8d873U, 0x62313153U, 0x2a15153fU, 0x0804040cU, 0x95c7c752U,
-    0x46232365U, 0x9dc3c35eU, 0x30181828U, 0x379696a1U, 0x0a05050fU,
-    0x2f9a9ab5U, 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
-    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, 0x1209091bU,
-    0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, 0x361b1b2dU, 0xdc6e6eb2U,
-    0xb45a5aeeU, 0x5ba0a0fbU, 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U,
-    0x7db3b3ceU, 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
-    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, 0x40202060U,
-    0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, 0xd46a6abeU, 0x8dcbcb46U,
-    0x67bebed9U, 0x7239394bU, 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U,
-    0x85cfcf4aU, 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
-    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, 0x8a4545cfU,
-    0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, 0xa05050f0U, 0x783c3c44U,
-    0x259f9fbaU, 0x4ba8a8e3U, 0xa25151f3U, 0x5da3a3feU, 0x804040c0U,
-    0x058f8f8aU, 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
-    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, 0x20101030U,
-    0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, 0x81cdcd4cU, 0x180c0c14U,
-    0x26131335U, 0xc3ecec2fU, 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU,
-    0x2e171739U, 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
-    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, 0xc06060a0U,
-    0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, 0x44222266U, 0x542a2a7eU,
-    0x3b9090abU, 0x0b888883U, 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U,
-    0x2814143cU, 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
-    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, 0x924949dbU,
-    0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, 0x9fc2c25dU, 0xbdd3d36eU,
-    0x43acacefU, 0xc46262a6U, 0x399191a8U, 0x319595a4U, 0xd3e4e437U,
-    0xf279798bU, 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
-    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, 0xd86c6cb4U,
-    0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, 0xca6565afU, 0xf47a7a8eU,
-    0x47aeaee9U, 0x10080818U, 0x6fbabad5U, 0xf0787888U, 0x4a25256fU,
-    0x5c2e2e72U, 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
-    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, 0x964b4bddU,
-    0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, 0xe0707090U, 0x7c3e3e42U,
-    0x71b5b5c4U, 0xcc6666aaU, 0x904848d8U, 0x06030305U, 0xf7f6f601U,
-    0x1c0e0e12U, 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
-    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, 0xd9e1e138U,
-    0xebf8f813U, 0x2b9898b3U, 0x22111133U, 0xd26969bbU, 0xa9d9d970U,
-    0x078e8e89U, 0x339494a7U, 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U,
-    0xc9e9e920U, 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
-    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, 0x65bfbfdaU,
-    0xd7e6e631U, 0x844242c6U, 0xd06868b8U, 0x824141c3U, 0x299999b0U,
-    0x5a2d2d77U, 0x1e0f0f11U, 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U,
-    0x2c16163aU, };
-
-static const uint32_t Te1[256] = {
-    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU, 0x0dfff2f2U,
-    0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U, 0x50603030U, 0x03020101U,
-    0xa9ce6767U, 0x7d562b2bU, 0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU,
-    0x9aec7676U, 0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,
-    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U, 0xec41adadU,
-    0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU, 0xbf239c9cU, 0xf753a4a4U,
-    0x96e47272U, 0x5b9bc0c0U, 0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U,
-    0x6a4c2626U, 0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,
-    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U, 0x93e27171U,
-    0x73abd8d8U, 0x53623131U, 0x3f2a1515U, 0x0c080404U, 0x5295c7c7U,
-    0x65462323U, 0x5e9dc3c3U, 0x28301818U, 0xa1379696U, 0x0f0a0505U,
-    0xb52f9a9aU, 0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,
-    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U, 0x1b120909U,
-    0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU, 0x2d361b1bU, 0xb2dc6e6eU,
-    0xeeb45a5aU, 0xfb5ba0a0U, 0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U,
-    0xce7db3b3U, 0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,
-    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU, 0x60402020U,
-    0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU, 0xbed46a6aU, 0x468dcbcbU,
-    0xd967bebeU, 0x4b723939U, 0xde944a4aU, 0xd4984c4cU, 0xe8b05858U,
-    0x4a85cfcfU, 0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,
-    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U, 0xcf8a4545U,
-    0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU, 0xf0a05050U, 0x44783c3cU,
-    0xba259f9fU, 0xe34ba8a8U, 0xf3a25151U, 0xfe5da3a3U, 0xc0804040U,
-    0x8a058f8fU, 0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,
-    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U, 0x30201010U,
-    0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U, 0x4c81cdcdU, 0x14180c0cU,
-    0x35261313U, 0x2fc3ececU, 0xe1be5f5fU, 0xa2359797U, 0xcc884444U,
-    0x392e1717U, 0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,
-    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U, 0xa0c06060U,
-    0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU, 0x66442222U, 0x7e542a2aU,
-    0xab3b9090U, 0x830b8888U, 0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U,
-    0x3c281414U, 0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,
-    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU, 0xdb924949U,
-    0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU, 0x5d9fc2c2U, 0x6ebdd3d3U,
-    0xef43acacU, 0xa6c46262U, 0xa8399191U, 0xa4319595U, 0x37d3e4e4U,
-    0x8bf27979U, 0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,
-    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U, 0xb4d86c6cU,
-    0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU, 0xafca6565U, 0x8ef47a7aU,
-    0xe947aeaeU, 0x18100808U, 0xd56fbabaU, 0x88f07878U, 0x6f4a2525U,
-    0x725c2e2eU, 0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,
-    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU, 0xdd964b4bU,
-    0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU, 0x90e07070U, 0x427c3e3eU,
-    0xc471b5b5U, 0xaacc6666U, 0xd8904848U, 0x05060303U, 0x01f7f6f6U,
-    0x121c0e0eU, 0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,
-    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU, 0x38d9e1e1U,
-    0x13ebf8f8U, 0xb32b9898U, 0x33221111U, 0xbbd26969U, 0x70a9d9d9U,
-    0x89078e8eU, 0xa7339494U, 0xb62d9b9bU, 0x223c1e1eU, 0x92158787U,
-    0x20c9e9e9U, 0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,
-    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU, 0xda65bfbfU,
-    0x31d7e6e6U, 0xc6844242U, 0xb8d06868U, 0xc3824141U, 0xb0299999U,
-    0x775a2d2dU, 0x111e0f0fU, 0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU,
-    0x3a2c1616U, };
-
-static const uint32_t Te2[256] = {
-    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU, 0xf20dfff2U,
-    0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U, 0x30506030U, 0x01030201U,
-    0x67a9ce67U, 0x2b7d562bU, 0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU,
-    0x769aec76U, 0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,
-    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U, 0xadec41adU,
-    0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU, 0x9cbf239cU, 0xa4f753a4U,
-    0x7296e472U, 0xc05b9bc0U, 0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U,
-    0x266a4c26U, 0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,
-    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U, 0x7193e271U,
-    0xd873abd8U, 0x31536231U, 0x153f2a15U, 0x040c0804U, 0xc75295c7U,
-    0x23654623U, 0xc35e9dc3U, 0x18283018U, 0x96a13796U, 0x050f0a05U,
-    0x9ab52f9aU, 0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,
-    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U, 0x091b1209U,
-    0x839e1d83U, 0x2c74582cU, 0x1a2e341aU, 0x1b2d361bU, 0x6eb2dc6eU,
-    0x5aeeb45aU, 0xa0fb5ba0U, 0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U,
-    0xb3ce7db3U, 0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,
-    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU, 0x20604020U,
-    0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU, 0x6abed46aU, 0xcb468dcbU,
-    0xbed967beU, 0x394b7239U, 0x4ade944aU, 0x4cd4984cU, 0x58e8b058U,
-    0xcf4a85cfU, 0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,
-    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U, 0x45cf8a45U,
-    0xf910e9f9U, 0x02060402U, 0x7f81fe7fU, 0x50f0a050U, 0x3c44783cU,
-    0x9fba259fU, 0xa8e34ba8U, 0x51f3a251U, 0xa3fe5da3U, 0x40c08040U,
-    0x8f8a058fU, 0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,
-    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U, 0x10302010U,
-    0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U, 0xcd4c81cdU, 0x0c14180cU,
-    0x13352613U, 0xec2fc3ecU, 0x5fe1be5fU, 0x97a23597U, 0x44cc8844U,
-    0x17392e17U, 0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,
-    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U, 0x60a0c060U,
-    0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU, 0x22664422U, 0x2a7e542aU,
-    0x90ab3b90U, 0x88830b88U, 0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U,
-    0x143c2814U, 0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,
-    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU, 0x49db9249U,
-    0x060a0c06U, 0x246c4824U, 0x5ce4b85cU, 0xc25d9fc2U, 0xd36ebdd3U,
-    0xacef43acU, 0x62a6c462U, 0x91a83991U, 0x95a43195U, 0xe437d3e4U,
-    0x798bf279U, 0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,
-    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U, 0x6cb4d86cU,
-    0x56faac56U, 0xf407f3f4U, 0xea25cfeaU, 0x65afca65U, 0x7a8ef47aU,
-    0xaee947aeU, 0x08181008U, 0xbad56fbaU, 0x7888f078U, 0x256f4a25U,
-    0x2e725c2eU, 0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,
-    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU, 0x4bdd964bU,
-    0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU, 0x7090e070U, 0x3e427c3eU,
-    0xb5c471b5U, 0x66aacc66U, 0x48d89048U, 0x03050603U, 0xf601f7f6U,
-    0x0e121c0eU, 0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,
-    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU, 0xe138d9e1U,
-    0xf813ebf8U, 0x98b32b98U, 0x11332211U, 0x69bbd269U, 0xd970a9d9U,
-    0x8e89078eU, 0x94a73394U, 0x9bb62d9bU, 0x1e223c1eU, 0x87921587U,
-    0xe920c9e9U, 0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,
-    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU, 0xbfda65bfU,
-    0xe631d7e6U, 0x42c68442U, 0x68b8d068U, 0x41c38241U, 0x99b02999U,
-    0x2d775a2dU, 0x0f111e0fU, 0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU,
-    0x163a2c16U, };
-
-static const uint32_t Te3[256] = {
-    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U, 0xf2f20dffU,
-    0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U, 0x30305060U, 0x01010302U,
-    0x6767a9ceU, 0x2b2b7d56U, 0xfefe19e7U, 0xd7d762b5U, 0xababe64dU,
-    0x76769aecU, 0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,
-    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU, 0xadadec41U,
-    0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U, 0x9c9cbf23U, 0xa4a4f753U,
-    0x727296e4U, 0xc0c05b9bU, 0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU,
-    0x26266a4cU, 0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,
-    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U, 0x717193e2U,
-    0xd8d873abU, 0x31315362U, 0x15153f2aU, 0x04040c08U, 0xc7c75295U,
-    0x23236546U, 0xc3c35e9dU, 0x18182830U, 0x9696a137U, 0x05050f0aU,
-    0x9a9ab52fU, 0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,
-    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU, 0x09091b12U,
-    0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U, 0x1b1b2d36U, 0x6e6eb2dcU,
-    0x5a5aeeb4U, 0xa0a0fb5bU, 0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U,
-    0xb3b3ce7dU, 0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,
-    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U, 0x20206040U,
-    0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U, 0x6a6abed4U, 0xcbcb468dU,
-    0xbebed967U, 0x39394b72U, 0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U,
-    0xcfcf4a85U, 0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,
-    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U, 0x4545cf8aU,
-    0xf9f910e9U, 0x02020604U, 0x7f7f81feU, 0x5050f0a0U, 0x3c3c4478U,
-    0x9f9fba25U, 0xa8a8e34bU, 0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U,
-    0x8f8f8a05U, 0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,
-    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U, 0x10103020U,
-    0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU, 0xcdcd4c81U, 0x0c0c1418U,
-    0x13133526U, 0xecec2fc3U, 0x5f5fe1beU, 0x9797a235U, 0x4444cc88U,
-    0x1717392eU, 0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,
-    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U, 0x6060a0c0U,
-    0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U, 0x22226644U, 0x2a2a7e54U,
-    0x9090ab3bU, 0x8888830bU, 0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU,
-    0x14143c28U, 0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,
-    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U, 0x4949db92U,
-    0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U, 0xc2c25d9fU, 0xd3d36ebdU,
-    0xacacef43U, 0x6262a6c4U, 0x9191a839U, 0x9595a431U, 0xe4e437d3U,
-    0x79798bf2U, 0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,
-    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U, 0x6c6cb4d8U,
-    0x5656faacU, 0xf4f407f3U, 0xeaea25cfU, 0x6565afcaU, 0x7a7a8ef4U,
-    0xaeaee947U, 0x08081810U, 0xbabad56fU, 0x787888f0U, 0x25256f4aU,
-    0x2e2e725cU, 0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,
-    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU, 0x4b4bdd96U,
-    0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU, 0x707090e0U, 0x3e3e427cU,
-    0xb5b5c471U, 0x6666aaccU, 0x4848d890U, 0x03030506U, 0xf6f601f7U,
-    0x0e0e121cU, 0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,
-    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U, 0xe1e138d9U,
-    0xf8f813ebU, 0x9898b32bU, 0x11113322U, 0x6969bbd2U, 0xd9d970a9U,
-    0x8e8e8907U, 0x9494a733U, 0x9b9bb62dU, 0x1e1e223cU, 0x87879215U,
-    0xe9e920c9U, 0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,
-    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU, 0xbfbfda65U,
-    0xe6e631d7U, 0x4242c684U, 0x6868b8d0U, 0x4141c382U, 0x9999b029U,
-    0x2d2d775aU, 0x0f0f111eU, 0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU,
-    0x16163a2cU, };
-
-static const uint32_t Td0[256] = {
-    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, 0x3bab6bcbU,
-    0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, 0x2030fa55U, 0xad766df6U,
-    0x88cc7691U, 0xf5024c25U, 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U,
-    0xb562a38fU, 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
-    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, 0x038f5fe7U,
-    0x15929c95U, 0xbf6d7aebU, 0x955259daU, 0xd4be832dU, 0x587421d3U,
-    0x49e06929U, 0x8ec9c844U, 0x75c2896aU, 0xf48e7978U, 0x99583e6bU,
-    0x27b971ddU, 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
-    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, 0xb16477e0U,
-    0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, 0x70486858U, 0x8f45fd19U,
-    0x94de6c87U, 0x527bf8b7U, 0xab73d323U, 0x724b02e2U, 0xe31f8f57U,
-    0x6655ab2aU, 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
-    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, 0x8acf1c2bU,
-    0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, 0x65daf4cdU, 0x0605bed5U,
-    0xd134621fU, 0xc4a6fe8aU, 0x342e539dU, 0xa2f355a0U, 0x058ae132U,
-    0xa4f6eb75U, 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
-    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, 0x91548db5U,
-    0x71c45d05U, 0x0406d46fU, 0x605015ffU, 0x1998fb24U, 0xd6bde997U,
-    0x894043ccU, 0x67d99e77U, 0xb0e842bdU, 0x07898b88U, 0xe7195b38U,
-    0x79c8eedbU, 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
-    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, 0xfd0efffbU,
-    0x0f853856U, 0x3daed51eU, 0x362d3927U, 0x0a0fd964U, 0x685ca621U,
-    0x9b5b54d1U, 0x24362e3aU, 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U,
-    0x1b9b919eU, 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
-    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, 0x0e090d0bU,
-    0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, 0x57f11985U, 0xaf75074cU,
-    0xee99ddbbU, 0xa37f60fdU, 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U,
-    0x5bfb7e34U, 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
-    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, 0x854a247dU,
-    0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, 0x1d9e2f4bU, 0xdcb230f3U,
-    0x0d8652ecU, 0x77c1e3d0U, 0x2bb3166cU, 0xa970b999U, 0x119448faU,
-    0x47e96422U, 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
-    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, 0xa6f581cfU,
-    0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, 0x2c3a9de4U, 0x5078920dU,
-    0x6a5fcc9bU, 0x547e4662U, 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU,
-    0x82c3aff5U, 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
-    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, 0xcd267809U,
-    0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, 0xe6956e65U, 0xaaffe67eU,
-    0x21bccf08U, 0xef15e8e6U, 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U,
-    0x29b07cd6U, 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
-    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, 0xf104984aU,
-    0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, 0x764dd68dU, 0x43efb04dU,
-    0xccaa4d54U, 0xe49604dfU, 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U,
-    0x4665517fU, 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
-    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, 0x9ad7618cU,
-    0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, 0xcea927eeU, 0xb761c935U,
-    0xe11ce5edU, 0x7a47b13cU, 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U,
-    0x73c737bfU, 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
-    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, 0x161dc372U,
-    0xbce2250cU, 0x283c498bU, 0xff0d9541U, 0x39a80171U, 0x080cb3deU,
-    0xd8b4e49cU, 0x6456c190U, 0x7bcb8461U, 0xd532b670U, 0x486c5c74U,
-    0xd0b85742U, };
-
-static const uint32_t Td1[256] = {
-    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU, 0xcb3bab6bU,
-    0xf11f9d45U, 0xabacfa58U, 0x934be303U, 0x552030faU, 0xf6ad766dU,
-    0x9188cc76U, 0x25f5024cU, 0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U,
-    0x8fb562a3U, 0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,
-    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U, 0xe7038f5fU,
-    0x9515929cU, 0xebbf6d7aU, 0xda955259U, 0x2dd4be83U, 0xd3587421U,
-    0x2949e069U, 0x448ec9c8U, 0x6a75c289U, 0x78f48e79U, 0x6b99583eU,
-    0xdd27b971U, 0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,
-    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU, 0xe0b16477U,
-    0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU, 0x58704868U, 0x198f45fdU,
-    0x8794de6cU, 0xb7527bf8U, 0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU,
-    0x2a6655abU, 0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,
-    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U, 0x2b8acf1cU,
-    0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U, 0xcd65daf4U, 0xd50605beU,
-    0x1fd13462U, 0x8ac4a6feU, 0x9d342e53U, 0xa0a2f355U, 0x32058ae1U,
-    0x75a4f6ebU, 0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,
-    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU, 0xb591548dU,
-    0x0571c45dU, 0x6f0406d4U, 0xff605015U, 0x241998fbU, 0x97d6bde9U,
-    0xcc894043U, 0x7767d99eU, 0xbdb0e842U, 0x8807898bU, 0x38e7195bU,
-    0xdb79c8eeU, 0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,
-    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U, 0xfbfd0effU,
-    0x560f8538U, 0x1e3daed5U, 0x27362d39U, 0x640a0fd9U, 0x21685ca6U,
-    0xd19b5b54U, 0x3a24362eU, 0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U,
-    0x9e1b9b91U, 0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,
-    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U, 0x0b0e090dU,
-    0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U, 0x8557f119U, 0x4caf7507U,
-    0xbbee99ddU, 0xfda37f60U, 0x9ff70126U, 0xbc5c72f5U, 0xc544663bU,
-    0x345bfb7eU, 0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,
-    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U, 0x7d854a24U,
-    0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U, 0x4b1d9e2fU, 0xf3dcb230U,
-    0xec0d8652U, 0xd077c1e3U, 0x6c2bb316U, 0x99a970b9U, 0xfa119448U,
-    0x2247e964U, 0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,
-    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU, 0xcfa6f581U,
-    0x28a57adeU, 0x26dab78eU, 0xa43fadbfU, 0xe42c3a9dU, 0x0d507892U,
-    0x9b6a5fccU, 0x62547e46U, 0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U,
-    0xf582c3afU, 0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,
-    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU, 0x09cd2678U,
-    0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU, 0x65e6956eU, 0x7eaaffe6U,
-    0x0821bccfU, 0xe6ef15e8U, 0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U,
-    0xd629b07cU, 0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,
-    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U, 0x4af10498U,
-    0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U, 0x8d764dd6U, 0x4d43efb0U,
-    0x54ccaa4dU, 0xdfe49604U, 0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU,
-    0x7f466551U, 0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,
-    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U, 0x8c9ad761U,
-    0x7a37a10cU, 0x8e59f814U, 0x89eb133cU, 0xeecea927U, 0x35b761c9U,
-    0xede11ce5U, 0x3c7a47b1U, 0x599cd2dfU, 0x3f55f273U, 0x791814ceU,
-    0xbf73c737U, 0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,
-    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U, 0x72161dc3U,
-    0x0cbce225U, 0x8b283c49U, 0x41ff0d95U, 0x7139a801U, 0xde080cb3U,
-    0x9cd8b4e4U, 0x906456c1U, 0x617bcb84U, 0x70d532b6U, 0x74486c5cU,
-    0x42d0b857U, };
-
-static const uint32_t Td2[256] = {
-    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U, 0x6bcb3babU,
-    0x45f11f9dU, 0x58abacfaU, 0x03934be3U, 0xfa552030U, 0x6df6ad76U,
-    0x769188ccU, 0x4c25f502U, 0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U,
-    0xa38fb562U, 0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,
-    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U, 0x5fe7038fU,
-    0x9c951592U, 0x7aebbf6dU, 0x59da9552U, 0x832dd4beU, 0x21d35874U,
-    0x692949e0U, 0xc8448ec9U, 0x896a75c2U, 0x7978f48eU, 0x3e6b9958U,
-    0x71dd27b9U, 0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,
-    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U, 0x77e0b164U,
-    0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U, 0x68587048U, 0xfd198f45U,
-    0x6c8794deU, 0xf8b7527bU, 0xd323ab73U, 0x02e2724bU, 0x8f57e31fU,
-    0xab2a6655U, 0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,
-    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U, 0x1c2b8acfU,
-    0xb492a779U, 0xf2f0f307U, 0xe2a14e69U, 0xf4cd65daU, 0xbed50605U,
-    0x621fd134U, 0xfe8ac4a6U, 0x539d342eU, 0x55a0a2f3U, 0xe132058aU,
-    0xeb75a4f6U, 0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,
-    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U, 0x8db59154U,
-    0x5d0571c4U, 0xd46f0406U, 0x15ff6050U, 0xfb241998U, 0xe997d6bdU,
-    0x43cc8940U, 0x9e7767d9U, 0x42bdb0e8U, 0x8b880789U, 0x5b38e719U,
-    0xeedb79c8U, 0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,
-    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU, 0xfffbfd0eU,
-    0x38560f85U, 0xd51e3daeU, 0x3927362dU, 0xd9640a0fU, 0xa621685cU,
-    0x54d19b5bU, 0x2e3a2436U, 0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU,
-    0x919e1b9bU, 0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,
-    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU, 0x0d0b0e09U,
-    0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU, 0x198557f1U, 0x074caf75U,
-    0xddbbee99U, 0x60fda37fU, 0x269ff701U, 0xf5bc5c72U, 0x3bc54466U,
-    0x7e345bfbU, 0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,
-    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U, 0x247d854aU,
-    0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U, 0x2f4b1d9eU, 0x30f3dcb2U,
-    0x52ec0d86U, 0xe3d077c1U, 0x166c2bb3U, 0xb999a970U, 0x48fa1194U,
-    0x642247e9U, 0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,
-    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U, 0x81cfa6f5U,
-    0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU, 0x9de42c3aU, 0x920d5078U,
-    0xcc9b6a5fU, 0x4662547eU, 0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U,
-    0xaff582c3U, 0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,
-    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU, 0x7809cd26U,
-    0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU, 0x6e65e695U, 0xe67eaaffU,
-    0xcf0821bcU, 0xe8e6ef15U, 0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU,
-    0x7cd629b0U, 0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,
-    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U, 0x984af104U,
-    0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U, 0xd68d764dU, 0xb04d43efU,
-    0x4d54ccaaU, 0x04dfe496U, 0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU,
-    0x517f4665U, 0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,
-    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U, 0x618c9ad7U,
-    0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U, 0x27eecea9U, 0xc935b761U,
-    0xe5ede11cU, 0xb13c7a47U, 0xdf599cd2U, 0x733f55f2U, 0xce791814U,
-    0x37bf73c7U, 0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,
-    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U, 0xc372161dU,
-    0x250cbce2U, 0x498b283cU, 0x9541ff0dU, 0x017139a8U, 0xb3de080cU,
-    0xe49cd8b4U, 0xc1906456U, 0x84617bcbU, 0xb670d532U, 0x5c74486cU,
-    0x5742d0b8U, };
-
-static const uint32_t Td3[256] = {
-    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU, 0xab6bcb3bU,
-    0x9d45f11fU, 0xfa58abacU, 0xe303934bU, 0x30fa5520U, 0x766df6adU,
-    0xcc769188U, 0x024c25f5U, 0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U,
-    0x62a38fb5U, 0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,
-    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU, 0x8f5fe703U,
-    0x929c9515U, 0x6d7aebbfU, 0x5259da95U, 0xbe832dd4U, 0x7421d358U,
-    0xe0692949U, 0xc9c8448eU, 0xc2896a75U, 0x8e7978f4U, 0x583e6b99U,
-    0xb971dd27U, 0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,
-    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U, 0x6477e0b1U,
-    0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U, 0x48685870U, 0x45fd198fU,
-    0xde6c8794U, 0x7bf8b752U, 0x73d323abU, 0x4b02e272U, 0x1f8f57e3U,
-    0x55ab2a66U, 0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,
-    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU, 0xcf1c2b8aU,
-    0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU, 0xdaf4cd65U, 0x05bed506U,
-    0x34621fd1U, 0xa6fe8ac4U, 0x2e539d34U, 0xf355a0a2U, 0x8ae13205U,
-    0xf6eb75a4U, 0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,
-    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU, 0x548db591U,
-    0xc45d0571U, 0x06d46f04U, 0x5015ff60U, 0x98fb2419U, 0xbde997d6U,
-    0x4043cc89U, 0xd99e7767U, 0xe842bdb0U, 0x898b8807U, 0x195b38e7U,
-    0xc8eedb79U, 0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,
-    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU, 0x0efffbfdU,
-    0x8538560fU, 0xaed51e3dU, 0x2d392736U, 0x0fd9640aU, 0x5ca62168U,
-    0x5b54d19bU, 0x362e3a24U, 0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U,
-    0x9b919e1bU, 0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,
-    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U, 0x090d0b0eU,
-    0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U, 0xf1198557U, 0x75074cafU,
-    0x99ddbbeeU, 0x7f60fda3U, 0x01269ff7U, 0x72f5bc5cU, 0x663bc544U,
-    0xfb7e345bU, 0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,
-    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U, 0x4a247d85U,
-    0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U, 0x9e2f4b1dU, 0xb230f3dcU,
-    0x8652ec0dU, 0xc1e3d077U, 0xb3166c2bU, 0x70b999a9U, 0x9448fa11U,
-    0xe9642247U, 0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,
-    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U, 0xf581cfa6U,
-    0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU, 0x3a9de42cU, 0x78920d50U,
-    0x5fcc9b6aU, 0x7e466254U, 0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU,
-    0xc3aff582U, 0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,
-    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU, 0x267809cdU,
-    0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U, 0x956e65e6U, 0xffe67eaaU,
-    0xbccf0821U, 0x15e8e6efU, 0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU,
-    0xb07cd629U, 0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,
-    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U, 0x04984af1U,
-    0xecdaf741U, 0xcd500e7fU, 0x91f62f17U, 0x4dd68d76U, 0xefb04d43U,
-    0xaa4d54ccU, 0x9604dfe4U, 0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U,
-    0x65517f46U, 0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,
-    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU, 0xd7618c9aU,
-    0xa10c7a37U, 0xf8148e59U, 0x133c89ebU, 0xa927eeceU, 0x61c935b7U,
-    0x1ce5ede1U, 0x47b13c7aU, 0xd2df599cU, 0xf2733f55U, 0x14ce7918U,
-    0xc737bf73U, 0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,
-    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U, 0x1dc37216U,
-    0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU, 0xa8017139U, 0x0cb3de08U,
-    0xb4e49cd8U, 0x56c19064U, 0xcb84617bU, 0x32b670d5U, 0x6c5c7448U,
-    0xb85742d0U, };
-
-static const uint8_t Td4[256] = {
-    0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, 0xbfU, 0x40U, 0xa3U,
-    0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU,
-    0xffU, 0x87U, 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, 0x54U,
-    0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, 0xeeU, 0x4cU, 0x95U, 0x0bU,
-    0x42U, 0xfaU, 0xc3U, 0x4eU, 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U,
-    0xb2U, 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, 0x72U, 0xf8U,
-    0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU,
-    0x65U, 0xb6U, 0x92U, 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
-    0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, 0x90U, 0xd8U, 0xabU,
-    0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U,
-    0x45U, 0x06U, 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, 0xc1U,
-    0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, 0x3aU, 0x91U, 0x11U, 0x41U,
-    0x4fU, 0x67U, 0xdcU, 0xeaU, 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U,
-    0x73U, 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, 0xe2U, 0xf9U,
-    0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU,
-    0x29U, 0xc5U, 0x89U, 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
-    0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, 0x9aU, 0xdbU, 0xc0U,
-    0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U,
-    0xc7U, 0x31U, 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, 0x60U,
-    0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, 0x2dU, 0xe5U, 0x7aU, 0x9fU,
-    0x93U, 0xc9U, 0x9cU, 0xefU, 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U,
-    0xb0U, 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, 0x17U, 0x2bU,
-    0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U,
-    0x21U, 0x0cU, 0x7dU, };
-
-static const uint32_t rcon[] = {
-    0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000,
-    0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000,
-    // for 128-bit blocks, Rijndael never uses more than 10 rcon values
-};
-
-int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits,
-			     AES_KEY *aeskey) {
-  uint32_t *rk;
-  int i = 0;
-  uint32_t temp;
-
-  if (!key || !aeskey) {
-    return -1;
-  }
-
-  switch (bits) {
-    case 128:
-      aeskey->rounds = 10;
-      break;
-    case 192:
-      aeskey->rounds = 12;
-      break;
-    case 256:
-      aeskey->rounds = 14;
-      break;
-    default:
-      return -2;
-  }
-
-  rk = aeskey->rd_key;
-
-  rk[0] = GETU32(key);
-  rk[1] = GETU32(key + 4);
-  rk[2] = GETU32(key + 8);
-  rk[3] = GETU32(key + 12);
-  if (bits == 128) {
-    while (1) {
-      temp = rk[3];
-      rk[4] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[5] = rk[1] ^ rk[4];
-      rk[6] = rk[2] ^ rk[5];
-      rk[7] = rk[3] ^ rk[6];
-      if (++i == 10) {
-        return 0;
-      }
-      rk += 4;
-    }
-  }
-  rk[4] = GETU32(key + 16);
-  rk[5] = GETU32(key + 20);
-  if (bits == 192) {
-    while (1) {
-      temp = rk[5];
-      rk[6] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[7] = rk[1] ^ rk[6];
-      rk[8] = rk[2] ^ rk[7];
-      rk[9] = rk[3] ^ rk[8];
-      if (++i == 8) {
-        return 0;
-      }
-      rk[10] = rk[4] ^ rk[9];
-      rk[11] = rk[5] ^ rk[10];
-      rk += 6;
-    }
-  }
-  rk[6] = GETU32(key + 24);
-  rk[7] = GETU32(key + 28);
-  if (bits == 256) {
-    while (1) {
-      temp = rk[7];
-      rk[8] = rk[0] ^ (Te2[(temp >> 16) & 0xff] & 0xff000000) ^
-              (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^
-              (Te0[(temp) & 0xff] & 0x0000ff00) ^
-              (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i];
-      rk[9] = rk[1] ^ rk[8];
-      rk[10] = rk[2] ^ rk[9];
-      rk[11] = rk[3] ^ rk[10];
-      if (++i == 7) {
-        return 0;
-      }
-      temp = rk[11];
-      rk[12] = rk[4] ^ (Te2[(temp >> 24)] & 0xff000000) ^
-               (Te3[(temp >> 16) & 0xff] & 0x00ff0000) ^
-               (Te0[(temp >> 8) & 0xff] & 0x0000ff00) ^
-               (Te1[(temp) & 0xff] & 0x000000ff);
-      rk[13] = rk[5] ^ rk[12];
-      rk[14] = rk[6] ^ rk[13];
-      rk[15] = rk[7] ^ rk[14];
-
-      rk += 8;
-    }
-  }
-  return 0;
-}
-
-int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits,
-			     AES_KEY *aeskey) {
-  uint32_t *rk;
-  int i, j, status;
-  uint32_t temp;
-
-  // first, start with an encryption schedule
-  status = AES_set_encrypt_key(key, bits, aeskey);
-  if (status < 0) {
-    return status;
-  }
-
-  rk = aeskey->rd_key;
-
-  // invert the order of the round keys:
-  for (i = 0, j = 4 * aeskey->rounds; i < j; i += 4, j -= 4) {
-    temp = rk[i];
-    rk[i] = rk[j];
-    rk[j] = temp;
-    temp = rk[i + 1];
-    rk[i + 1] = rk[j + 1];
-    rk[j + 1] = temp;
-    temp = rk[i + 2];
-    rk[i + 2] = rk[j + 2];
-    rk[j + 2] = temp;
-    temp = rk[i + 3];
-    rk[i + 3] = rk[j + 3];
-    rk[j + 3] = temp;
-  }
-  // apply the inverse MixColumn transform to all round keys but the first and
-  // the last:
-  for (i = 1; i < (int)aeskey->rounds; i++) {
-    rk += 4;
-    rk[0] =
-        Td0[Te1[(rk[0] >> 24)] & 0xff] ^ Td1[Te1[(rk[0] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[0] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[0]) & 0xff] & 0xff];
-    rk[1] =
-        Td0[Te1[(rk[1] >> 24)] & 0xff] ^ Td1[Te1[(rk[1] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[1] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[1]) & 0xff] & 0xff];
-    rk[2] =
-        Td0[Te1[(rk[2] >> 24)] & 0xff] ^ Td1[Te1[(rk[2] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[2] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[2]) & 0xff] & 0xff];
-    rk[3] =
-        Td0[Te1[(rk[3] >> 24)] & 0xff] ^ Td1[Te1[(rk[3] >> 16) & 0xff] & 0xff] ^
-        Td2[Te1[(rk[3] >> 8) & 0xff] & 0xff] ^ Td3[Te1[(rk[3]) & 0xff] & 0xff];
-  }
-  return 0;
-}
-
-void aes_nohw_encrypt(const uint8_t *in, uint8_t *out,
-		      const AES_KEY *key) {
-  const uint32_t *rk;
-  uint32_t s0, s1, s2, s3, t0, t1, t2, t3;
-  int r;
-
-  rk = key->rd_key;
-
-  // map byte array block to cipher state
-  // and add initial round key:
-  s0 = GETU32(in) ^ rk[0];
-  s1 = GETU32(in + 4) ^ rk[1];
-  s2 = GETU32(in + 8) ^ rk[2];
-  s3 = GETU32(in + 12) ^ rk[3];
-
-  // Nr - 1 full rounds:
-  r = key->rounds >> 1;
-  for (;;) {
-    t0 = Te0[(s0 >> 24)] ^ Te1[(s1 >> 16) & 0xff] ^ Te2[(s2 >> 8) & 0xff] ^
-         Te3[(s3) & 0xff] ^ rk[4];
-    t1 = Te0[(s1 >> 24)] ^ Te1[(s2 >> 16) & 0xff] ^ Te2[(s3 >> 8) & 0xff] ^
-         Te3[(s0) & 0xff] ^ rk[5];
-    t2 = Te0[(s2 >> 24)] ^ Te1[(s3 >> 16) & 0xff] ^ Te2[(s0 >> 8) & 0xff] ^
-         Te3[(s1) & 0xff] ^ rk[6];
-    t3 = Te0[(s3 >> 24)] ^ Te1[(s0 >> 16) & 0xff] ^ Te2[(s1 >> 8) & 0xff] ^
-         Te3[(s2) & 0xff] ^ rk[7];
-
-    rk += 8;
-    if (--r == 0) {
-      break;
-    }
-
-    s0 = Te0[(t0 >> 24)] ^ Te1[(t1 >> 16) & 0xff] ^ Te2[(t2 >> 8) & 0xff] ^
-         Te3[(t3) & 0xff] ^ rk[0];
-    s1 = Te0[(t1 >> 24)] ^ Te1[(t2 >> 16) & 0xff] ^ Te2[(t3 >> 8) & 0xff] ^
-         Te3[(t0) & 0xff] ^ rk[1];
-    s2 = Te0[(t2 >> 24)] ^ Te1[(t3 >> 16) & 0xff] ^ Te2[(t0 >> 8) & 0xff] ^
-         Te3[(t1) & 0xff] ^ rk[2];
-    s3 = Te0[(t3 >> 24)] ^ Te1[(t0 >> 16) & 0xff] ^ Te2[(t1 >> 8) & 0xff] ^
-         Te3[(t2) & 0xff] ^ rk[3];
-  }
-
-  //  apply last round and map cipher state to byte array block:
-  s0 = (Te2[(t0 >> 24)] & 0xff000000) ^ (Te3[(t1 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t2 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t3) & 0xff] & 0x000000ff) ^
-       rk[0];
-  PUTU32(out, s0);
-  s1 = (Te2[(t1 >> 24)] & 0xff000000) ^ (Te3[(t2 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t3 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t0) & 0xff] & 0x000000ff) ^
-       rk[1];
-  PUTU32(out + 4, s1);
-  s2 = (Te2[(t2 >> 24)] & 0xff000000) ^ (Te3[(t3 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t0 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t1) & 0xff] & 0x000000ff) ^
-       rk[2];
-  PUTU32(out + 8, s2);
-  s3 = (Te2[(t3 >> 24)] & 0xff000000) ^ (Te3[(t0 >> 16) & 0xff] & 0x00ff0000) ^
-       (Te0[(t1 >> 8) & 0xff] & 0x0000ff00) ^ (Te1[(t2) & 0xff] & 0x000000ff) ^
-       rk[3];
-  PUTU32(out + 12, s3);
-}
-
-void aes_nohw_decrypt(const uint8_t *in, uint8_t *out,
-		      const AES_KEY *key) {
-  const uint32_t *rk;
-  uint32_t s0, s1, s2, s3, t0, t1, t2, t3;
-  int r;
-
-  rk = key->rd_key;
-
-  // map byte array block to cipher state
-  // and add initial round key:
-  s0 = GETU32(in) ^ rk[0];
-  s1 = GETU32(in + 4) ^ rk[1];
-  s2 = GETU32(in + 8) ^ rk[2];
-  s3 = GETU32(in + 12) ^ rk[3];
-
-  // Nr - 1 full rounds:
-  r = key->rounds >> 1;
-  for (;;) {
-    t0 = Td0[(s0 >> 24)] ^ Td1[(s3 >> 16) & 0xff] ^ Td2[(s2 >> 8) & 0xff] ^
-         Td3[(s1) & 0xff] ^ rk[4];
-    t1 = Td0[(s1 >> 24)] ^ Td1[(s0 >> 16) & 0xff] ^ Td2[(s3 >> 8) & 0xff] ^
-         Td3[(s2) & 0xff] ^ rk[5];
-    t2 = Td0[(s2 >> 24)] ^ Td1[(s1 >> 16) & 0xff] ^ Td2[(s0 >> 8) & 0xff] ^
-         Td3[(s3) & 0xff] ^ rk[6];
-    t3 = Td0[(s3 >> 24)] ^ Td1[(s2 >> 16) & 0xff] ^ Td2[(s1 >> 8) & 0xff] ^
-         Td3[(s0) & 0xff] ^ rk[7];
-
-    rk += 8;
-    if (--r == 0) {
-      break;
-    }
-
-    s0 = Td0[(t0 >> 24)] ^ Td1[(t3 >> 16) & 0xff] ^ Td2[(t2 >> 8) & 0xff] ^
-         Td3[(t1) & 0xff] ^ rk[0];
-    s1 = Td0[(t1 >> 24)] ^ Td1[(t0 >> 16) & 0xff] ^ Td2[(t3 >> 8) & 0xff] ^
-         Td3[(t2) & 0xff] ^ rk[1];
-    s2 = Td0[(t2 >> 24)] ^ Td1[(t1 >> 16) & 0xff] ^ Td2[(t0 >> 8) & 0xff] ^
-         Td3[(t3) & 0xff] ^ rk[2];
-    s3 = Td0[(t3 >> 24)] ^ Td1[(t2 >> 16) & 0xff] ^ Td2[(t1 >> 8) & 0xff] ^
-         Td3[(t0) & 0xff] ^ rk[3];
-  }
-
-  // apply last round and
-  // map cipher state to byte array block:
-  s0 = ((uint32_t)Td4[(t0 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t3 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t2 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t1) & 0xff]) ^ rk[0];
-  PUTU32(out, s0);
-  s1 = ((uint32_t)Td4[(t1 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t0 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t3 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t2) & 0xff]) ^ rk[1];
-  PUTU32(out + 4, s1);
-  s2 = ((uint32_t)Td4[(t2 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t1 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t0 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t3) & 0xff]) ^ rk[2];
-  PUTU32(out + 8, s2);
-  s3 = ((uint32_t)Td4[(t3 >> 24)] << 24) ^
-       ((uint32_t)Td4[(t2 >> 16) & 0xff] << 16) ^
-       ((uint32_t)Td4[(t1 >> 8) & 0xff] << 8) ^
-       ((uint32_t)Td4[(t0) & 0xff]) ^ rk[3];
-  PUTU32(out + 12, s3);
-}
diff --git a/third_party/boringssl/common/curve25519-generic.c b/third_party/boringssl/common/curve25519-generic.c
deleted file mode 100644
index e0d09b2acb..0000000000
--- a/third_party/boringssl/common/curve25519-generic.c
+++ /dev/null
@@ -1,821 +0,0 @@
-/* Copyright 2015, Google Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP
- * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as
- * public domain but this file has the ISC license just to keep licencing
- * simple.
- *
- * The field functions are shared by Ed25519 and X25519 where possible. */
-
-#include "curve25519.h"
-#include "util.h"
-
-/*
- * fe means field element. Here the field is \Z/(2^255-19). An element t,
- * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77
- * t[3]+2^102 t[4]+...+2^230 t[9]. Bounds on each t[i] vary depending on
- * context.
- */
-typedef int32_t fe[10];
-
-static const int64_t kBottom25Bits = INT64_C(0x1ffffff);
-static const int64_t kBottom26Bits = INT64_C(0x3ffffff);
-static const int64_t kTop39Bits = INT64_C(0xfffffffffe000000);
-static const int64_t kTop38Bits = INT64_C(0xfffffffffc000000);
-
-static uint64_t load_3(const uint8_t *in) {
-  uint64_t result;
-  result = (uint64_t)in[0];
-  result |= ((uint64_t)in[1]) << 8;
-  result |= ((uint64_t)in[2]) << 16;
-  return result;
-}
-
-static uint64_t load_4(const uint8_t *in) {
-  uint64_t result;
-  result = (uint64_t)in[0];
-  result |= ((uint64_t)in[1]) << 8;
-  result |= ((uint64_t)in[2]) << 16;
-  result |= ((uint64_t)in[3]) << 24;
-  return result;
-}
-
-static void fe_frombytes(fe h, const uint8_t *s) {
-  /* Ignores top bit of h. */
-  int64_t h0 = load_4(s);
-  int64_t h1 = load_3(s + 4) << 6;
-  int64_t h2 = load_3(s + 7) << 5;
-  int64_t h3 = load_3(s + 10) << 3;
-  int64_t h4 = load_3(s + 13) << 2;
-  int64_t h5 = load_4(s + 16);
-  int64_t h6 = load_3(s + 20) << 7;
-  int64_t h7 = load_3(s + 23) << 5;
-  int64_t h8 = load_3(s + 26) << 4;
-  int64_t h9 = (load_3(s + 29) & 8388607) << 2;
-  int64_t carry0;
-  int64_t carry1;
-  int64_t carry2;
-  int64_t carry3;
-  int64_t carry4;
-  int64_t carry5;
-  int64_t carry6;
-  int64_t carry7;
-  int64_t carry8;
-  int64_t carry9;
-
-  carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits;
-  carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits;
-  carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits;
-  carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits;
-  carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits;
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-  carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits;
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-  carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits;
-  carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits;
-
-  h[0] = h0;
-  h[1] = h1;
-  h[2] = h2;
-  h[3] = h3;
-  h[4] = h4;
-  h[5] = h5;
-  h[6] = h6;
-  h[7] = h7;
-  h[8] = h8;
-  h[9] = h9;
-}
-
-/* Preconditions:
- *  |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
- *
- * Write p=2^255-19; q=floor(h/p).
- * Basic claim: q = floor(2^(-255)(h + 19 2^(-25)h9 + 2^(-1))).
- *
- * Proof:
- *   Have |h|<=p so |q|<=1 so |19^2 2^(-255) q|<1/4.
- *   Also have |h-2^230 h9|<2^231 so |19 2^(-255)(h-2^230 h9)|<1/4.
- *
- *   Write y=2^(-1)-19^2 2^(-255)q-19 2^(-255)(h-2^230 h9).
- *   Then 0<y<1.
- *
- *   Write r=h-pq.
- *   Have 0<=r<=p-1=2^255-20.
- *   Thus 0<=r+19(2^-255)r<r+19(2^-255)2^255<=2^255-1.
- *
- *   Write x=r+19(2^-255)r+y.
- *   Then 0<x<2^255 so floor(2^(-255)x) = 0 so floor(q+2^(-255)x) = q.
- *
- *   Have q+2^(-255)x = 2^(-255)(h + 19 2^(-25) h9 + 2^(-1))
- *   so floor(2^(-255)(h + 19 2^(-25) h9 + 2^(-1))) = q. */
-static void fe_tobytes(uint8_t *s, const fe h) {
-  int32_t h0 = h[0];
-  int32_t h1 = h[1];
-  int32_t h2 = h[2];
-  int32_t h3 = h[3];
-  int32_t h4 = h[4];
-  int32_t h5 = h[5];
-  int32_t h6 = h[6];
-  int32_t h7 = h[7];
-  int32_t h8 = h[8];
-  int32_t h9 = h[9];
-  int32_t q;
-
-  q = (19 * h9 + (((int32_t) 1) << 24)) >> 25;
-  q = (h0 + q) >> 26;
-  q = (h1 + q) >> 25;
-  q = (h2 + q) >> 26;
-  q = (h3 + q) >> 25;
-  q = (h4 + q) >> 26;
-  q = (h5 + q) >> 25;
-  q = (h6 + q) >> 26;
-  q = (h7 + q) >> 25;
-  q = (h8 + q) >> 26;
-  q = (h9 + q) >> 25;
-
-  /* Goal: Output h-(2^255-19)q, which is between 0 and 2^255-20. */
-  h0 += 19 * q;
-  /* Goal: Output h-2^255 q, which is between 0 and 2^255-20. */
-
-  h1 += h0 >> 26; h0 &= kBottom26Bits;
-  h2 += h1 >> 25; h1 &= kBottom25Bits;
-  h3 += h2 >> 26; h2 &= kBottom26Bits;
-  h4 += h3 >> 25; h3 &= kBottom25Bits;
-  h5 += h4 >> 26; h4 &= kBottom26Bits;
-  h6 += h5 >> 25; h5 &= kBottom25Bits;
-  h7 += h6 >> 26; h6 &= kBottom26Bits;
-  h8 += h7 >> 25; h7 &= kBottom25Bits;
-  h9 += h8 >> 26; h8 &= kBottom26Bits;
-                  h9 &= kBottom25Bits;
-                  /* h10 = carry9 */
-
-  /* Goal: Output h0+...+2^255 h10-2^255 q, which is between 0 and 2^255-20.
-   * Have h0+...+2^230 h9 between 0 and 2^255-1;
-   * evidently 2^255 h10-2^255 q = 0.
-   * Goal: Output h0+...+2^230 h9.  */
-
-  s[0] = h0 >> 0;
-  s[1] = h0 >> 8;
-  s[2] = h0 >> 16;
-  s[3] = (h0 >> 24) | ((uint32_t)(h1) << 2);
-  s[4] = h1 >> 6;
-  s[5] = h1 >> 14;
-  s[6] = (h1 >> 22) | ((uint32_t)(h2) << 3);
-  s[7] = h2 >> 5;
-  s[8] = h2 >> 13;
-  s[9] = (h2 >> 21) | ((uint32_t)(h3) << 5);
-  s[10] = h3 >> 3;
-  s[11] = h3 >> 11;
-  s[12] = (h3 >> 19) | ((uint32_t)(h4) << 6);
-  s[13] = h4 >> 2;
-  s[14] = h4 >> 10;
-  s[15] = h4 >> 18;
-  s[16] = h5 >> 0;
-  s[17] = h5 >> 8;
-  s[18] = h5 >> 16;
-  s[19] = (h5 >> 24) | ((uint32_t)(h6) << 1);
-  s[20] = h6 >> 7;
-  s[21] = h6 >> 15;
-  s[22] = (h6 >> 23) | ((uint32_t)(h7) << 3);
-  s[23] = h7 >> 5;
-  s[24] = h7 >> 13;
-  s[25] = (h7 >> 21) | ((uint32_t)(h8) << 4);
-  s[26] = h8 >> 4;
-  s[27] = h8 >> 12;
-  s[28] = (h8 >> 20) | ((uint32_t)(h9) << 6);
-  s[29] = h9 >> 2;
-  s[30] = h9 >> 10;
-  s[31] = h9 >> 18;
-}
-
-/* h = f */
-static void fe_copy(fe h, const fe f) {
-  memmove(h, f, sizeof(int32_t) * 10);
-}
-
-/* h = 0 */
-static void fe_0(fe h) { memset(h, 0, sizeof(int32_t) * 10); }
-
-/* h = 1 */
-static void fe_1(fe h) {
-  memset(h, 0, sizeof(int32_t) * 10);
-  h[0] = 1;
-}
-
-/* h = f + g
- * Can overlap h with f or g.
- *
- * Preconditions:
- *    |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
- *    |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
- *
- * Postconditions:
- *    |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */
-static void fe_add(fe h, const fe f, const fe g) {
-  unsigned i;
-  for (i = 0; i < 10; i++) {
-    h[i] = f[i] + g[i];
-  }
-}
-
-/* h = f - g
- * Can overlap h with f or g.
- *
- * Preconditions:
- *    |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
- *    |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
- *
- * Postconditions:
- *    |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */
-static void fe_sub(fe h, const fe f, const fe g) {
-  unsigned i;
-  for (i = 0; i < 10; i++) {
-    h[i] = f[i] - g[i];
-  }
-}
-
-/* h = f * g
- * Can overlap h with f or g.
- *
- * Preconditions:
- *    |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
- *    |g| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
- *
- * Postconditions:
- *    |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc.
- *
- * Notes on implementation strategy:
- *
- * Using schoolbook multiplication.
- * Karatsuba would save a little in some cost models.
- *
- * Most multiplications by 2 and 19 are 32-bit precomputations;
- * cheaper than 64-bit postcomputations.
- *
- * There is one remaining multiplication by 19 in the carry chain;
- * one *19 precomputation can be merged into this,
- * but the resulting data flow is considerably less clean.
- *
- * There are 12 carries below.
- * 10 of them are 2-way parallelizable and vectorizable.
- * Can get away with 11 carries, but then data flow is much deeper.
- *
- * With tighter constraints on inputs can squeeze carries into int32. */
-static void fe_mul(fe h, const fe f, const fe g) {
-  int32_t f0 = f[0];
-  int32_t f1 = f[1];
-  int32_t f2 = f[2];
-  int32_t f3 = f[3];
-  int32_t f4 = f[4];
-  int32_t f5 = f[5];
-  int32_t f6 = f[6];
-  int32_t f7 = f[7];
-  int32_t f8 = f[8];
-  int32_t f9 = f[9];
-  int32_t g0 = g[0];
-  int32_t g1 = g[1];
-  int32_t g2 = g[2];
-  int32_t g3 = g[3];
-  int32_t g4 = g[4];
-  int32_t g5 = g[5];
-  int32_t g6 = g[6];
-  int32_t g7 = g[7];
-  int32_t g8 = g[8];
-  int32_t g9 = g[9];
-  int32_t g1_19 = 19 * g1; /* 1.959375*2^29 */
-  int32_t g2_19 = 19 * g2; /* 1.959375*2^30; still ok */
-  int32_t g3_19 = 19 * g3;
-  int32_t g4_19 = 19 * g4;
-  int32_t g5_19 = 19 * g5;
-  int32_t g6_19 = 19 * g6;
-  int32_t g7_19 = 19 * g7;
-  int32_t g8_19 = 19 * g8;
-  int32_t g9_19 = 19 * g9;
-  int32_t f1_2 = 2 * f1;
-  int32_t f3_2 = 2 * f3;
-  int32_t f5_2 = 2 * f5;
-  int32_t f7_2 = 2 * f7;
-  int32_t f9_2 = 2 * f9;
-  int64_t f0g0    = f0   * (int64_t) g0;
-  int64_t f0g1    = f0   * (int64_t) g1;
-  int64_t f0g2    = f0   * (int64_t) g2;
-  int64_t f0g3    = f0   * (int64_t) g3;
-  int64_t f0g4    = f0   * (int64_t) g4;
-  int64_t f0g5    = f0   * (int64_t) g5;
-  int64_t f0g6    = f0   * (int64_t) g6;
-  int64_t f0g7    = f0   * (int64_t) g7;
-  int64_t f0g8    = f0   * (int64_t) g8;
-  int64_t f0g9    = f0   * (int64_t) g9;
-  int64_t f1g0    = f1   * (int64_t) g0;
-  int64_t f1g1_2  = f1_2 * (int64_t) g1;
-  int64_t f1g2    = f1   * (int64_t) g2;
-  int64_t f1g3_2  = f1_2 * (int64_t) g3;
-  int64_t f1g4    = f1   * (int64_t) g4;
-  int64_t f1g5_2  = f1_2 * (int64_t) g5;
-  int64_t f1g6    = f1   * (int64_t) g6;
-  int64_t f1g7_2  = f1_2 * (int64_t) g7;
-  int64_t f1g8    = f1   * (int64_t) g8;
-  int64_t f1g9_38 = f1_2 * (int64_t) g9_19;
-  int64_t f2g0    = f2   * (int64_t) g0;
-  int64_t f2g1    = f2   * (int64_t) g1;
-  int64_t f2g2    = f2   * (int64_t) g2;
-  int64_t f2g3    = f2   * (int64_t) g3;
-  int64_t f2g4    = f2   * (int64_t) g4;
-  int64_t f2g5    = f2   * (int64_t) g5;
-  int64_t f2g6    = f2   * (int64_t) g6;
-  int64_t f2g7    = f2   * (int64_t) g7;
-  int64_t f2g8_19 = f2   * (int64_t) g8_19;
-  int64_t f2g9_19 = f2   * (int64_t) g9_19;
-  int64_t f3g0    = f3   * (int64_t) g0;
-  int64_t f3g1_2  = f3_2 * (int64_t) g1;
-  int64_t f3g2    = f3   * (int64_t) g2;
-  int64_t f3g3_2  = f3_2 * (int64_t) g3;
-  int64_t f3g4    = f3   * (int64_t) g4;
-  int64_t f3g5_2  = f3_2 * (int64_t) g5;
-  int64_t f3g6    = f3   * (int64_t) g6;
-  int64_t f3g7_38 = f3_2 * (int64_t) g7_19;
-  int64_t f3g8_19 = f3   * (int64_t) g8_19;
-  int64_t f3g9_38 = f3_2 * (int64_t) g9_19;
-  int64_t f4g0    = f4   * (int64_t) g0;
-  int64_t f4g1    = f4   * (int64_t) g1;
-  int64_t f4g2    = f4   * (int64_t) g2;
-  int64_t f4g3    = f4   * (int64_t) g3;
-  int64_t f4g4    = f4   * (int64_t) g4;
-  int64_t f4g5    = f4   * (int64_t) g5;
-  int64_t f4g6_19 = f4   * (int64_t) g6_19;
-  int64_t f4g7_19 = f4   * (int64_t) g7_19;
-  int64_t f4g8_19 = f4   * (int64_t) g8_19;
-  int64_t f4g9_19 = f4   * (int64_t) g9_19;
-  int64_t f5g0    = f5   * (int64_t) g0;
-  int64_t f5g1_2  = f5_2 * (int64_t) g1;
-  int64_t f5g2    = f5   * (int64_t) g2;
-  int64_t f5g3_2  = f5_2 * (int64_t) g3;
-  int64_t f5g4    = f5   * (int64_t) g4;
-  int64_t f5g5_38 = f5_2 * (int64_t) g5_19;
-  int64_t f5g6_19 = f5   * (int64_t) g6_19;
-  int64_t f5g7_38 = f5_2 * (int64_t) g7_19;
-  int64_t f5g8_19 = f5   * (int64_t) g8_19;
-  int64_t f5g9_38 = f5_2 * (int64_t) g9_19;
-  int64_t f6g0    = f6   * (int64_t) g0;
-  int64_t f6g1    = f6   * (int64_t) g1;
-  int64_t f6g2    = f6   * (int64_t) g2;
-  int64_t f6g3    = f6   * (int64_t) g3;
-  int64_t f6g4_19 = f6   * (int64_t) g4_19;
-  int64_t f6g5_19 = f6   * (int64_t) g5_19;
-  int64_t f6g6_19 = f6   * (int64_t) g6_19;
-  int64_t f6g7_19 = f6   * (int64_t) g7_19;
-  int64_t f6g8_19 = f6   * (int64_t) g8_19;
-  int64_t f6g9_19 = f6   * (int64_t) g9_19;
-  int64_t f7g0    = f7   * (int64_t) g0;
-  int64_t f7g1_2  = f7_2 * (int64_t) g1;
-  int64_t f7g2    = f7   * (int64_t) g2;
-  int64_t f7g3_38 = f7_2 * (int64_t) g3_19;
-  int64_t f7g4_19 = f7   * (int64_t) g4_19;
-  int64_t f7g5_38 = f7_2 * (int64_t) g5_19;
-  int64_t f7g6_19 = f7   * (int64_t) g6_19;
-  int64_t f7g7_38 = f7_2 * (int64_t) g7_19;
-  int64_t f7g8_19 = f7   * (int64_t) g8_19;
-  int64_t f7g9_38 = f7_2 * (int64_t) g9_19;
-  int64_t f8g0    = f8   * (int64_t) g0;
-  int64_t f8g1    = f8   * (int64_t) g1;
-  int64_t f8g2_19 = f8   * (int64_t) g2_19;
-  int64_t f8g3_19 = f8   * (int64_t) g3_19;
-  int64_t f8g4_19 = f8   * (int64_t) g4_19;
-  int64_t f8g5_19 = f8   * (int64_t) g5_19;
-  int64_t f8g6_19 = f8   * (int64_t) g6_19;
-  int64_t f8g7_19 = f8   * (int64_t) g7_19;
-  int64_t f8g8_19 = f8   * (int64_t) g8_19;
-  int64_t f8g9_19 = f8   * (int64_t) g9_19;
-  int64_t f9g0    = f9   * (int64_t) g0;
-  int64_t f9g1_38 = f9_2 * (int64_t) g1_19;
-  int64_t f9g2_19 = f9   * (int64_t) g2_19;
-  int64_t f9g3_38 = f9_2 * (int64_t) g3_19;
-  int64_t f9g4_19 = f9   * (int64_t) g4_19;
-  int64_t f9g5_38 = f9_2 * (int64_t) g5_19;
-  int64_t f9g6_19 = f9   * (int64_t) g6_19;
-  int64_t f9g7_38 = f9_2 * (int64_t) g7_19;
-  int64_t f9g8_19 = f9   * (int64_t) g8_19;
-  int64_t f9g9_38 = f9_2 * (int64_t) g9_19;
-  int64_t h0 = f0g0+f1g9_38+f2g8_19+f3g7_38+f4g6_19+f5g5_38+f6g4_19+f7g3_38+f8g2_19+f9g1_38;
-  int64_t h1 = f0g1+f1g0   +f2g9_19+f3g8_19+f4g7_19+f5g6_19+f6g5_19+f7g4_19+f8g3_19+f9g2_19;
-  int64_t h2 = f0g2+f1g1_2 +f2g0   +f3g9_38+f4g8_19+f5g7_38+f6g6_19+f7g5_38+f8g4_19+f9g3_38;
-  int64_t h3 = f0g3+f1g2   +f2g1   +f3g0   +f4g9_19+f5g8_19+f6g7_19+f7g6_19+f8g5_19+f9g4_19;
-  int64_t h4 = f0g4+f1g3_2 +f2g2   +f3g1_2 +f4g0   +f5g9_38+f6g8_19+f7g7_38+f8g6_19+f9g5_38;
-  int64_t h5 = f0g5+f1g4   +f2g3   +f3g2   +f4g1   +f5g0   +f6g9_19+f7g8_19+f8g7_19+f9g6_19;
-  int64_t h6 = f0g6+f1g5_2 +f2g4   +f3g3_2 +f4g2   +f5g1_2 +f6g0   +f7g9_38+f8g8_19+f9g7_38;
-  int64_t h7 = f0g7+f1g6   +f2g5   +f3g4   +f4g3   +f5g2   +f6g1   +f7g0   +f8g9_19+f9g8_19;
-  int64_t h8 = f0g8+f1g7_2 +f2g6   +f3g5_2 +f4g4   +f5g3_2 +f6g2   +f7g1_2 +f8g0   +f9g9_38;
-  int64_t h9 = f0g9+f1g8   +f2g7   +f3g6   +f4g5   +f5g4   +f6g3   +f7g2   +f8g1   +f9g0   ;
-  int64_t carry0;
-  int64_t carry1;
-  int64_t carry2;
-  int64_t carry3;
-  int64_t carry4;
-  int64_t carry5;
-  int64_t carry6;
-  int64_t carry7;
-  int64_t carry8;
-  int64_t carry9;
-
-  /* |h0| <= (1.65*1.65*2^52*(1+19+19+19+19)+1.65*1.65*2^50*(38+38+38+38+38))
-   *   i.e. |h0| <= 1.4*2^60; narrower ranges for h2, h4, h6, h8
-   * |h1| <= (1.65*1.65*2^51*(1+1+19+19+19+19+19+19+19+19))
-   *   i.e. |h1| <= 1.7*2^59; narrower ranges for h3, h5, h7, h9 */
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-  /* |h0| <= 2^25 */
-  /* |h4| <= 2^25 */
-  /* |h1| <= 1.71*2^59 */
-  /* |h5| <= 1.71*2^59 */
-
-  carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits;
-  carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits;
-  /* |h1| <= 2^24; from now on fits into int32 */
-  /* |h5| <= 2^24; from now on fits into int32 */
-  /* |h2| <= 1.41*2^60 */
-  /* |h6| <= 1.41*2^60 */
-
-  carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits;
-  carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits;
-  /* |h2| <= 2^25; from now on fits into int32 unchanged */
-  /* |h6| <= 2^25; from now on fits into int32 unchanged */
-  /* |h3| <= 1.71*2^59 */
-  /* |h7| <= 1.71*2^59 */
-
-  carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits;
-  carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits;
-  /* |h3| <= 2^24; from now on fits into int32 unchanged */
-  /* |h7| <= 2^24; from now on fits into int32 unchanged */
-  /* |h4| <= 1.72*2^34 */
-  /* |h8| <= 1.41*2^60 */
-
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-  carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits;
-  /* |h4| <= 2^25; from now on fits into int32 unchanged */
-  /* |h8| <= 2^25; from now on fits into int32 unchanged */
-  /* |h5| <= 1.01*2^24 */
-  /* |h9| <= 1.71*2^59 */
-
-  carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits;
-  /* |h9| <= 2^24; from now on fits into int32 unchanged */
-  /* |h0| <= 1.1*2^39 */
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-  /* |h0| <= 2^25; from now on fits into int32 unchanged */
-  /* |h1| <= 1.01*2^24 */
-
-  h[0] = h0;
-  h[1] = h1;
-  h[2] = h2;
-  h[3] = h3;
-  h[4] = h4;
-  h[5] = h5;
-  h[6] = h6;
-  h[7] = h7;
-  h[8] = h8;
-  h[9] = h9;
-}
-
-/* h = f * f
- * Can overlap h with f.
- *
- * Preconditions:
- *    |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
- *
- * Postconditions:
- *    |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc.
- *
- * See fe_mul.c for discussion of implementation strategy. */
-static void fe_sq(fe h, const fe f) {
-  int32_t f0 = f[0];
-  int32_t f1 = f[1];
-  int32_t f2 = f[2];
-  int32_t f3 = f[3];
-  int32_t f4 = f[4];
-  int32_t f5 = f[5];
-  int32_t f6 = f[6];
-  int32_t f7 = f[7];
-  int32_t f8 = f[8];
-  int32_t f9 = f[9];
-  int32_t f0_2 = 2 * f0;
-  int32_t f1_2 = 2 * f1;
-  int32_t f2_2 = 2 * f2;
-  int32_t f3_2 = 2 * f3;
-  int32_t f4_2 = 2 * f4;
-  int32_t f5_2 = 2 * f5;
-  int32_t f6_2 = 2 * f6;
-  int32_t f7_2 = 2 * f7;
-  int32_t f5_38 = 38 * f5; /* 1.959375*2^30 */
-  int32_t f6_19 = 19 * f6; /* 1.959375*2^30 */
-  int32_t f7_38 = 38 * f7; /* 1.959375*2^30 */
-  int32_t f8_19 = 19 * f8; /* 1.959375*2^30 */
-  int32_t f9_38 = 38 * f9; /* 1.959375*2^30 */
-  int64_t f0f0    = f0   * (int64_t) f0;
-  int64_t f0f1_2  = f0_2 * (int64_t) f1;
-  int64_t f0f2_2  = f0_2 * (int64_t) f2;
-  int64_t f0f3_2  = f0_2 * (int64_t) f3;
-  int64_t f0f4_2  = f0_2 * (int64_t) f4;
-  int64_t f0f5_2  = f0_2 * (int64_t) f5;
-  int64_t f0f6_2  = f0_2 * (int64_t) f6;
-  int64_t f0f7_2  = f0_2 * (int64_t) f7;
-  int64_t f0f8_2  = f0_2 * (int64_t) f8;
-  int64_t f0f9_2  = f0_2 * (int64_t) f9;
-  int64_t f1f1_2  = f1_2 * (int64_t) f1;
-  int64_t f1f2_2  = f1_2 * (int64_t) f2;
-  int64_t f1f3_4  = f1_2 * (int64_t) f3_2;
-  int64_t f1f4_2  = f1_2 * (int64_t) f4;
-  int64_t f1f5_4  = f1_2 * (int64_t) f5_2;
-  int64_t f1f6_2  = f1_2 * (int64_t) f6;
-  int64_t f1f7_4  = f1_2 * (int64_t) f7_2;
-  int64_t f1f8_2  = f1_2 * (int64_t) f8;
-  int64_t f1f9_76 = f1_2 * (int64_t) f9_38;
-  int64_t f2f2    = f2   * (int64_t) f2;
-  int64_t f2f3_2  = f2_2 * (int64_t) f3;
-  int64_t f2f4_2  = f2_2 * (int64_t) f4;
-  int64_t f2f5_2  = f2_2 * (int64_t) f5;
-  int64_t f2f6_2  = f2_2 * (int64_t) f6;
-  int64_t f2f7_2  = f2_2 * (int64_t) f7;
-  int64_t f2f8_38 = f2_2 * (int64_t) f8_19;
-  int64_t f2f9_38 = f2   * (int64_t) f9_38;
-  int64_t f3f3_2  = f3_2 * (int64_t) f3;
-  int64_t f3f4_2  = f3_2 * (int64_t) f4;
-  int64_t f3f5_4  = f3_2 * (int64_t) f5_2;
-  int64_t f3f6_2  = f3_2 * (int64_t) f6;
-  int64_t f3f7_76 = f3_2 * (int64_t) f7_38;
-  int64_t f3f8_38 = f3_2 * (int64_t) f8_19;
-  int64_t f3f9_76 = f3_2 * (int64_t) f9_38;
-  int64_t f4f4    = f4   * (int64_t) f4;
-  int64_t f4f5_2  = f4_2 * (int64_t) f5;
-  int64_t f4f6_38 = f4_2 * (int64_t) f6_19;
-  int64_t f4f7_38 = f4   * (int64_t) f7_38;
-  int64_t f4f8_38 = f4_2 * (int64_t) f8_19;
-  int64_t f4f9_38 = f4   * (int64_t) f9_38;
-  int64_t f5f5_38 = f5   * (int64_t) f5_38;
-  int64_t f5f6_38 = f5_2 * (int64_t) f6_19;
-  int64_t f5f7_76 = f5_2 * (int64_t) f7_38;
-  int64_t f5f8_38 = f5_2 * (int64_t) f8_19;
-  int64_t f5f9_76 = f5_2 * (int64_t) f9_38;
-  int64_t f6f6_19 = f6   * (int64_t) f6_19;
-  int64_t f6f7_38 = f6   * (int64_t) f7_38;
-  int64_t f6f8_38 = f6_2 * (int64_t) f8_19;
-  int64_t f6f9_38 = f6   * (int64_t) f9_38;
-  int64_t f7f7_38 = f7   * (int64_t) f7_38;
-  int64_t f7f8_38 = f7_2 * (int64_t) f8_19;
-  int64_t f7f9_76 = f7_2 * (int64_t) f9_38;
-  int64_t f8f8_19 = f8   * (int64_t) f8_19;
-  int64_t f8f9_38 = f8   * (int64_t) f9_38;
-  int64_t f9f9_38 = f9   * (int64_t) f9_38;
-  int64_t h0 = f0f0  +f1f9_76+f2f8_38+f3f7_76+f4f6_38+f5f5_38;
-  int64_t h1 = f0f1_2+f2f9_38+f3f8_38+f4f7_38+f5f6_38;
-  int64_t h2 = f0f2_2+f1f1_2 +f3f9_76+f4f8_38+f5f7_76+f6f6_19;
-  int64_t h3 = f0f3_2+f1f2_2 +f4f9_38+f5f8_38+f6f7_38;
-  int64_t h4 = f0f4_2+f1f3_4 +f2f2   +f5f9_76+f6f8_38+f7f7_38;
-  int64_t h5 = f0f5_2+f1f4_2 +f2f3_2 +f6f9_38+f7f8_38;
-  int64_t h6 = f0f6_2+f1f5_4 +f2f4_2 +f3f3_2 +f7f9_76+f8f8_19;
-  int64_t h7 = f0f7_2+f1f6_2 +f2f5_2 +f3f4_2 +f8f9_38;
-  int64_t h8 = f0f8_2+f1f7_4 +f2f6_2 +f3f5_4 +f4f4   +f9f9_38;
-  int64_t h9 = f0f9_2+f1f8_2 +f2f7_2 +f3f6_2 +f4f5_2;
-  int64_t carry0;
-  int64_t carry1;
-  int64_t carry2;
-  int64_t carry3;
-  int64_t carry4;
-  int64_t carry5;
-  int64_t carry6;
-  int64_t carry7;
-  int64_t carry8;
-  int64_t carry9;
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-
-  carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits;
-  carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits;
-
-  carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits;
-  carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits;
-
-  carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits;
-  carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits;
-
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-  carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits;
-
-  carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits;
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-
-  h[0] = h0;
-  h[1] = h1;
-  h[2] = h2;
-  h[3] = h3;
-  h[4] = h4;
-  h[5] = h5;
-  h[6] = h6;
-  h[7] = h7;
-  h[8] = h8;
-  h[9] = h9;
-}
-
-static void fe_invert(fe out, const fe z) {
-  fe t0;
-  fe t1;
-  fe t2;
-  fe t3;
-  int i;
-
-  fe_sq(t0, z);
-  fe_sq(t1, t0);
-  for (i = 1; i < 2; ++i) {
-    fe_sq(t1, t1);
-  }
-  fe_mul(t1, z, t1);
-  fe_mul(t0, t0, t1);
-  fe_sq(t2, t0);
-  fe_mul(t1, t1, t2);
-  fe_sq(t2, t1);
-  for (i = 1; i < 5; ++i) {
-    fe_sq(t2, t2);
-  }
-  fe_mul(t1, t2, t1);
-  fe_sq(t2, t1);
-  for (i = 1; i < 10; ++i) {
-    fe_sq(t2, t2);
-  }
-  fe_mul(t2, t2, t1);
-  fe_sq(t3, t2);
-  for (i = 1; i < 20; ++i) {
-    fe_sq(t3, t3);
-  }
-  fe_mul(t2, t3, t2);
-  fe_sq(t2, t2);
-  for (i = 1; i < 10; ++i) {
-    fe_sq(t2, t2);
-  }
-  fe_mul(t1, t2, t1);
-  fe_sq(t2, t1);
-  for (i = 1; i < 50; ++i) {
-    fe_sq(t2, t2);
-  }
-  fe_mul(t2, t2, t1);
-  fe_sq(t3, t2);
-  for (i = 1; i < 100; ++i) {
-    fe_sq(t3, t3);
-  }
-  fe_mul(t2, t3, t2);
-  fe_sq(t2, t2);
-  for (i = 1; i < 50; ++i) {
-    fe_sq(t2, t2);
-  }
-  fe_mul(t1, t2, t1);
-  fe_sq(t1, t1);
-  for (i = 1; i < 5; ++i) {
-    fe_sq(t1, t1);
-  }
-  fe_mul(out, t1, t0);
-}
-
-/* Replace (f,g) with (g,f) if b == 1;
- * replace (f,g) with (f,g) if b == 0.
- *
- * Preconditions: b in {0,1}. */
-static void fe_cswap(fe f, fe g, unsigned int b) {
-  unsigned i;
-  b = 0-b;
-  for (i = 0; i < 10; i++) {
-    int32_t x = f[i] ^ g[i];
-    x &= b;
-    f[i] ^= x;
-    g[i] ^= x;
-  }
-}
-
-/* h = f * 121666
- * Can overlap h with f.
- *
- * Preconditions:
- *    |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
- *
- * Postconditions:
- *    |h| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. */
-static void fe_mul121666(fe h, fe f) {
-  int32_t f0 = f[0];
-  int32_t f1 = f[1];
-  int32_t f2 = f[2];
-  int32_t f3 = f[3];
-  int32_t f4 = f[4];
-  int32_t f5 = f[5];
-  int32_t f6 = f[6];
-  int32_t f7 = f[7];
-  int32_t f8 = f[8];
-  int32_t f9 = f[9];
-  int64_t h0 = f0 * (int64_t) 121666;
-  int64_t h1 = f1 * (int64_t) 121666;
-  int64_t h2 = f2 * (int64_t) 121666;
-  int64_t h3 = f3 * (int64_t) 121666;
-  int64_t h4 = f4 * (int64_t) 121666;
-  int64_t h5 = f5 * (int64_t) 121666;
-  int64_t h6 = f6 * (int64_t) 121666;
-  int64_t h7 = f7 * (int64_t) 121666;
-  int64_t h8 = f8 * (int64_t) 121666;
-  int64_t h9 = f9 * (int64_t) 121666;
-  int64_t carry0;
-  int64_t carry1;
-  int64_t carry2;
-  int64_t carry3;
-  int64_t carry4;
-  int64_t carry5;
-  int64_t carry6;
-  int64_t carry7;
-  int64_t carry8;
-  int64_t carry9;
-
-  carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits;
-  carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits;
-  carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits;
-  carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits;
-  carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits;
-
-  carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits;
-  carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits;
-  carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits;
-  carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits;
-  carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits;
-
-  h[0] = h0;
-  h[1] = h1;
-  h[2] = h2;
-  h[3] = h3;
-  h[4] = h4;
-  h[5] = h5;
-  h[6] = h6;
-  h[7] = h7;
-  h[8] = h8;
-  h[9] = h9;
-}
-
-void x25519_scalar_mult(uint8_t out[32],
-			const uint8_t scalar[32],
-			const uint8_t point[32]) {
-  fe x1, x2, z2, x3, z3, tmp0, tmp1;
-  unsigned swap;
-  int pos;
-
-  uint8_t e[32];
-  memcpy(e, scalar, 32);
-  e[0] &= 248;
-  e[31] &= 127;
-  e[31] |= 64;
-  fe_frombytes(x1, point);
-  fe_1(x2);
-  fe_0(z2);
-  fe_copy(x3, x1);
-  fe_1(z3);
-
-  swap = 0;
-  for (pos = 254; pos >= 0; --pos) {
-    unsigned b = 1 & (e[pos / 8] >> (pos & 7));
-    swap ^= b;
-    fe_cswap(x2, x3, swap);
-    fe_cswap(z2, z3, swap);
-    swap = b;
-    fe_sub(tmp0, x3, z3);
-    fe_sub(tmp1, x2, z2);
-    fe_add(x2, x2, z2);
-    fe_add(z2, x3, z3);
-    fe_mul(z3, tmp0, x2);
-    fe_mul(z2, z2, tmp1);
-    fe_sq(tmp0, tmp1);
-    fe_sq(tmp1, x2);
-    fe_add(x3, z3, z2);
-    fe_sub(z2, z3, z2);
-    fe_mul(x2, tmp1, tmp0);
-    fe_sub(tmp1, tmp1, tmp0);
-    fe_sq(z2, z2);
-    fe_mul121666(z3, tmp1);
-    fe_sq(x3, x3);
-    fe_add(tmp0, tmp0, z3);
-    fe_mul(z3, x1, z2);
-    fe_mul(z2, tmp1, tmp0);
-  }
-  fe_cswap(x2, x3, swap);
-  fe_cswap(z2, z3, swap);
-
-  fe_invert(z2, z2);
-  fe_mul(x2, x2, z2);
-  fe_tobytes(out, x2);
-}
diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c
deleted file mode 100644
index 2a7fad6509..0000000000
--- a/third_party/boringssl/common/curve25519.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2015, Google Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP
- * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as
- * public domain but this file has the ISC license just to keep licencing
- * simple.
- *
- * The field functions are shared by Ed25519 and X25519 where possible. */
-
-#include "common.h"
-#include "curve25519.h"
-#include "trng.h"
-#include "util.h"
-#define CRYPTO_memcmp safe_memcmp
-
-#ifdef CONFIG_RNG
-void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) {
-  rand_bytes(out_private_key, 32);
-
-  /* All X25519 implementations should decode scalars correctly (see
-   * https://tools.ietf.org/html/rfc7748#section-5). However, if an
-   * implementation doesn't then it might interoperate with random keys a
-   * fraction of the time because they'll, randomly, happen to be correctly
-   * formed.
-   *
-   * Thus we do the opposite of the masking here to make sure that our private
-   * keys are never correctly masked and so, hopefully, any incorrect
-   * implementations are deterministically broken.
-   *
-   * This does not affect security because, although we're throwing away
-   * entropy, a valid implementation of scalarmult should throw away the exact
-   * same bits anyway. */
-  out_private_key[0] |= 7;
-  out_private_key[31] &= 63;
-  out_private_key[31] |= 128;
-
-  X25519_public_from_private(out_public_value, out_private_key);
-}
-#endif
-
-int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32],
-           const uint8_t peer_public_value[32]) {
-  static const uint8_t kZeros[32] = {0};
-  x25519_scalar_mult(out_shared_key, private_key, peer_public_value);
-  /* The all-zero output results when the input is a point of small order. */
-  return CRYPTO_memcmp(kZeros, out_shared_key, 32) != 0;
-}
-
-void X25519_public_from_private(uint8_t out_public_value[32],
-                                const uint8_t private_key[32]) {
-  static const uint8_t kMongomeryBasePoint[32] = {9};
-  x25519_scalar_mult(out_public_value, private_key, kMongomeryBasePoint);
-}
diff --git a/third_party/boringssl/core/cortex-m/aes.S b/third_party/boringssl/core/cortex-m/aes.S
deleted file mode 100644
index 10d3cdabba..0000000000
--- a/third_party/boringssl/core/cortex-m/aes.S
+++ /dev/null
@@ -1,1189 +0,0 @@
-@ Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved.
-@
-@ Licensed under the OpenSSL license (the "License").  You may not use
-@ this file except in compliance with the License.  You can obtain a copy
-@ in the file LICENSE in the source distribution or at
-@ https://www.openssl.org/source/license.html
-
-
-@ ====================================================================
-@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
-@ project. The module is, however, dual licensed under OpenSSL and
-@ CRYPTOGAMS licenses depending on where you obtain it. For further
-@ details see http://www.openssl.org/~appro/cryptogams/.
-@ ====================================================================
-
-@ AES for ARMv4
-
-@ January 2007.
-@
-@ Code uses single 1K S-box and is >2 times faster than code generated
-@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
-@ allows to merge logical or arithmetic operation with shift or rotate
-@ in one instruction and emit combined result every cycle. The module
-@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
-@ key [on single-issue Xscale PXA250 core].
-
-@ May 2007.
-@
-@ AES_set_[en|de]crypt_key is added.
-
-@ July 2010.
-@
-@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
-@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
-
-@ February 2011.
-@
-@ Profiler-assisted and platform-specific optimization resulted in 16%
-@ improvement on Cortex A8 core and ~21.5 cycles per byte.
-
-#define __ARM_ARCH__ 7
-
-.text
-#if defined(__thumb2__) && !defined(__APPLE__)
-.syntax	unified
-.thumb
-#else
-.code	32
-#undef __thumb2__
-#endif
-
-.type	AES_Te,%object
-.align	5
-AES_Te:
-.word	0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
-.word	0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
-.word	0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
-.word	0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
-.word	0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
-.word	0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
-.word	0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
-.word	0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
-.word	0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
-.word	0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
-.word	0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
-.word	0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
-.word	0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
-.word	0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
-.word	0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
-.word	0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
-.word	0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
-.word	0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
-.word	0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
-.word	0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
-.word	0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
-.word	0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
-.word	0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
-.word	0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
-.word	0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
-.word	0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
-.word	0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
-.word	0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
-.word	0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
-.word	0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
-.word	0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
-.word	0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
-.word	0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
-.word	0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
-.word	0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
-.word	0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
-.word	0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
-.word	0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
-.word	0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
-.word	0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
-.word	0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
-.word	0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
-.word	0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
-.word	0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
-.word	0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
-.word	0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
-.word	0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
-.word	0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
-.word	0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
-.word	0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
-.word	0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
-.word	0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
-.word	0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
-.word	0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
-.word	0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
-.word	0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
-.word	0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
-.word	0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
-.word	0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
-.word	0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
-.word	0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
-.word	0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
-.word	0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
-.word	0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
-@ Te4[256]
-.byte	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
-.byte	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
-.byte	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
-.byte	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
-.byte	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
-.byte	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
-.byte	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
-.byte	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
-.byte	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
-.byte	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
-.byte	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
-.byte	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
-.byte	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
-.byte	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
-.byte	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
-.byte	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
-.byte	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
-.byte	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
-.byte	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
-.byte	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
-.byte	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
-.byte	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
-.byte	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
-.byte	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
-.byte	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
-.byte	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
-.byte	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
-.byte	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
-.byte	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
-.byte	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
-.byte	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
-.byte	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
-@ rcon[]
-.word	0x01000000, 0x02000000, 0x04000000, 0x08000000
-.word	0x10000000, 0x20000000, 0x40000000, 0x80000000
-.word	0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
-.size	AES_Te,.-AES_Te
-
-@ void aes_nohw_encrypt(const unsigned char *in, unsigned char *out,
-@ 		                  const AES_KEY *key) {
-.global aes_nohw_encrypt
-.type   aes_nohw_encrypt,%function
-.align	5
-aes_nohw_encrypt:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_encrypt
-#else
-	adr	r3,.
-#endif
-	stmdb   sp!,{r1,r4-r12,lr}
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Te
-#else
-	sub	r10,r3,#aes_nohw_encrypt-AES_Te	@ Te
-#endif
-	mov	r12,r0		@ inp
-	mov	r11,r2
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	orr	r3,r3,r5,lsl#16
-	orr	r3,r3,r6,lsl#24
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-#endif
-	bl	_armv4_AES_encrypt
-
-	ldr	r12,[sp],#4		@ pop out
-#if __ARM_ARCH__>=7
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r12,#0]
-	str	r1,[r12,#4]
-	str	r2,[r12,#8]
-	str	r3,[r12,#12]
-#else
-	mov	r4,r0,lsr#24		@ write output in endian-neutral
-	mov	r5,r0,lsr#16		@ manner...
-	mov	r6,r0,lsr#8
-	strb	r4,[r12,#0]
-	strb	r5,[r12,#1]
-	mov	r4,r1,lsr#24
-	strb	r6,[r12,#2]
-	mov	r5,r1,lsr#16
-	strb	r0,[r12,#3]
-	mov	r6,r1,lsr#8
-	strb	r4,[r12,#4]
-	strb	r5,[r12,#5]
-	mov	r4,r2,lsr#24
-	strb	r6,[r12,#6]
-	mov	r5,r2,lsr#16
-	strb	r1,[r12,#7]
-	mov	r6,r2,lsr#8
-	strb	r4,[r12,#8]
-	strb	r5,[r12,#9]
-	mov	r4,r3,lsr#24
-	strb	r6,[r12,#10]
-	mov	r5,r3,lsr#16
-	strb	r2,[r12,#11]
-	mov	r6,r3,lsr#8
-	strb	r4,[r12,#12]
-	strb	r5,[r12,#13]
-	strb	r6,[r12,#14]
-	strb	r3,[r12,#15]
-#endif
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_encrypt,.-aes_nohw_encrypt
-
-.type   _armv4_AES_encrypt,%function
-.align	2
-_armv4_AES_encrypt:
-	str	lr,[sp,#-4]!		@ push lr
-	ldmia	r11!,{r4-r7}
-	eor	r0,r0,r4
-	ldr	r12,[r11,#240-16]
-	eor	r1,r1,r5
-	eor	r2,r2,r6
-	eor	r3,r3,r7
-	sub	r12,r12,#1
-	mov	lr,#255
-
-	and	r7,lr,r0
-	and	r8,lr,r0,lsr#8
-	and	r9,lr,r0,lsr#16
-	mov	r0,r0,lsr#24
-.Lenc_loop:
-	ldr	r4,[r10,r7,lsl#2]	@ Te3[s0>>0]
-	and	r7,lr,r1,lsr#16	@ i0
-	ldr	r5,[r10,r8,lsl#2]	@ Te2[s0>>8]
-	and	r8,lr,r1
-	ldr	r6,[r10,r9,lsl#2]	@ Te1[s0>>16]
-	and	r9,lr,r1,lsr#8
-	ldr	r0,[r10,r0,lsl#2]	@ Te0[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldr	r7,[r10,r7,lsl#2]	@ Te1[s1>>16]
-	ldr	r8,[r10,r8,lsl#2]	@ Te3[s1>>0]
-	ldr	r9,[r10,r9,lsl#2]	@ Te2[s1>>8]
-	eor	r0,r0,r7,ror#8
-	ldr	r1,[r10,r1,lsl#2]	@ Te0[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r5,r8,ror#8
-	and	r8,lr,r2,lsr#16	@ i1
-	eor	r6,r6,r9,ror#8
-	and	r9,lr,r2
-	ldr	r7,[r10,r7,lsl#2]	@ Te2[s2>>8]
-	eor	r1,r1,r4,ror#24
-	ldr	r8,[r10,r8,lsl#2]	@ Te1[s2>>16]
-	mov	r2,r2,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Te3[s2>>0]
-	eor	r0,r0,r7,ror#16
-	ldr	r2,[r10,r2,lsl#2]	@ Te0[s2>>24]
-	and	r7,lr,r3		@ i0
-	eor	r1,r1,r8,ror#8
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r6,r9,ror#16
-	and	r9,lr,r3,lsr#16	@ i2
-	ldr	r7,[r10,r7,lsl#2]	@ Te3[s3>>0]
-	eor	r2,r2,r5,ror#16
-	ldr	r8,[r10,r8,lsl#2]	@ Te2[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Te1[s3>>16]
-	eor	r0,r0,r7,ror#24
-	ldr	r7,[r11],#16
-	eor	r1,r1,r8,ror#16
-	ldr	r3,[r10,r3,lsl#2]	@ Te0[s3>>24]
-	eor	r2,r2,r9,ror#8
-	ldr	r4,[r11,#-12]
-	eor	r3,r3,r6,ror#8
-
-	ldr	r5,[r11,#-8]
-	eor	r0,r0,r7
-	ldr	r6,[r11,#-4]
-	and	r7,lr,r0
-	eor	r1,r1,r4
-	and	r8,lr,r0,lsr#8
-	eor	r2,r2,r5
-	and	r9,lr,r0,lsr#16
-	eor	r3,r3,r6
-	mov	r0,r0,lsr#24
-
-	subs	r12,r12,#1
-	bne	.Lenc_loop
-
-	add	r10,r10,#2
-
-	ldrb	r4,[r10,r7,lsl#2]	@ Te4[s0>>0]
-	and	r7,lr,r1,lsr#16	@ i0
-	ldrb	r5,[r10,r8,lsl#2]	@ Te4[s0>>8]
-	and	r8,lr,r1
-	ldrb	r6,[r10,r9,lsl#2]	@ Te4[s0>>16]
-	and	r9,lr,r1,lsr#8
-	ldrb	r0,[r10,r0,lsl#2]	@ Te4[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s1>>16]
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s1>>0]
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s1>>8]
-	eor	r0,r7,r0,lsl#8
-	ldrb	r1,[r10,r1,lsl#2]	@ Te4[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r8,r5,lsl#8
-	and	r8,lr,r2,lsr#16	@ i1
-	eor	r6,r9,r6,lsl#8
-	and	r9,lr,r2
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s2>>8]
-	eor	r1,r4,r1,lsl#24
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s2>>16]
-	mov	r2,r2,lsr#24
-
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s2>>0]
-	eor	r0,r7,r0,lsl#8
-	ldrb	r2,[r10,r2,lsl#2]	@ Te4[s2>>24]
-	and	r7,lr,r3		@ i0
-	eor	r1,r1,r8,lsl#16
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r9,r6,lsl#8
-	and	r9,lr,r3,lsr#16	@ i2
-	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s3>>0]
-	eor	r2,r5,r2,lsl#24
-	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s3>>16]
-	eor	r0,r7,r0,lsl#8
-	ldr	r7,[r11,#0]
-	ldrb	r3,[r10,r3,lsl#2]	@ Te4[s3>>24]
-	eor	r1,r1,r8,lsl#8
-	ldr	r4,[r11,#4]
-	eor	r2,r2,r9,lsl#16
-	ldr	r5,[r11,#8]
-	eor	r3,r6,r3,lsl#24
-	ldr	r6,[r11,#12]
-
-	eor	r0,r0,r7
-	eor	r1,r1,r4
-	eor	r2,r2,r5
-	eor	r3,r3,r6
-
-	sub	r10,r10,#2
-	ldr	pc,[sp],#4		@ pop and return
-.size	_armv4_AES_encrypt,.-_armv4_AES_encrypt
-
-.global aes_nohw_set_encrypt_key
-.type   aes_nohw_set_encrypt_key,%function
-.align	5
-aes_nohw_set_encrypt_key:
-_armv4_AES_set_encrypt_key:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_set_encrypt_key
-#else
-	adr	r3,.
-#endif
-	teq	r0,#0
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	moveq	r0,#-1
-	beq	.Labrt
-	teq	r2,#0
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	moveq	r0,#-1
-	beq	.Labrt
-
-	teq	r1,#128
-	beq	.Lok
-	teq	r1,#192
-	beq	.Lok
-	teq	r1,#256
-#ifdef	__thumb2__
-	itt	ne			@ Thumb2 thing, validity check in ARM
-#endif
-	movne	r0,#-1
-	bne	.Labrt
-
-.Lok:	stmdb   sp!,{r4-r12,lr}
-	mov	r12,r0		@ inp
-	mov	lr,r1			@ bits
-	mov	r11,r2			@ key
-
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Te+1024				@ Te4
-#else
-	sub	r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024	@ Te4
-#endif
-
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	str	r0,[r11],#16
-	orr	r3,r3,r5,lsl#16
-	str	r1,[r11,#-12]
-	orr	r3,r3,r6,lsl#24
-	str	r2,[r11,#-8]
-	str	r3,[r11,#-4]
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r11],#16
-	str	r1,[r11,#-12]
-	str	r2,[r11,#-8]
-	str	r3,[r11,#-4]
-#endif
-
-	teq	lr,#128
-	bne	.Lnot128
-	mov	r12,#10
-	str	r12,[r11,#240-16]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-
-.L128_loop:
-	and	r5,lr,r3,lsr#24
-	and	r7,lr,r3,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r3,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r3
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r5,r5,r4
-	eor	r0,r0,r5			@ rk[4]=rk[0]^...
-	eor	r1,r1,r0			@ rk[5]=rk[1]^rk[4]
-	str	r0,[r11],#16
-	eor	r2,r2,r1			@ rk[6]=rk[2]^rk[5]
-	str	r1,[r11,#-12]
-	eor	r3,r3,r2			@ rk[7]=rk[3]^rk[6]
-	str	r2,[r11,#-8]
-	subs	r12,r12,#1
-	str	r3,[r11,#-4]
-	bne	.L128_loop
-	sub	r2,r11,#176
-	b	.Ldone
-
-.Lnot128:
-#if __ARM_ARCH__<7
-	ldrb	r8,[r12,#19]
-	ldrb	r4,[r12,#18]
-	ldrb	r5,[r12,#17]
-	ldrb	r6,[r12,#16]
-	orr	r8,r8,r4,lsl#8
-	ldrb	r9,[r12,#23]
-	orr	r8,r8,r5,lsl#16
-	ldrb	r4,[r12,#22]
-	orr	r8,r8,r6,lsl#24
-	ldrb	r5,[r12,#21]
-	ldrb	r6,[r12,#20]
-	orr	r9,r9,r4,lsl#8
-	orr	r9,r9,r5,lsl#16
-	str	r8,[r11],#8
-	orr	r9,r9,r6,lsl#24
-	str	r9,[r11,#-4]
-#else
-	ldr	r8,[r12,#16]
-	ldr	r9,[r12,#20]
-#ifdef __ARMEL__
-	rev	r8,r8
-	rev	r9,r9
-#endif
-	str	r8,[r11],#8
-	str	r9,[r11,#-4]
-#endif
-
-	teq	lr,#192
-	bne	.Lnot192
-	mov	r12,#12
-	str	r12,[r11,#240-24]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-	mov	r12,#8
-
-.L192_loop:
-	and	r5,lr,r9,lsr#24
-	and	r7,lr,r9,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r9,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r9
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r9,r5,r4
-	eor	r0,r0,r9			@ rk[6]=rk[0]^...
-	eor	r1,r1,r0			@ rk[7]=rk[1]^rk[6]
-	str	r0,[r11],#24
-	eor	r2,r2,r1			@ rk[8]=rk[2]^rk[7]
-	str	r1,[r11,#-20]
-	eor	r3,r3,r2			@ rk[9]=rk[3]^rk[8]
-	str	r2,[r11,#-16]
-	subs	r12,r12,#1
-	str	r3,[r11,#-12]
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	subeq	r2,r11,#216
-	beq	.Ldone
-
-	ldr	r7,[r11,#-32]
-	ldr	r8,[r11,#-28]
-	eor	r7,r7,r3			@ rk[10]=rk[4]^rk[9]
-	eor	r9,r8,r7			@ rk[11]=rk[5]^rk[10]
-	str	r7,[r11,#-8]
-	str	r9,[r11,#-4]
-	b	.L192_loop
-
-.Lnot192:
-#if __ARM_ARCH__<7
-	ldrb	r8,[r12,#27]
-	ldrb	r4,[r12,#26]
-	ldrb	r5,[r12,#25]
-	ldrb	r6,[r12,#24]
-	orr	r8,r8,r4,lsl#8
-	ldrb	r9,[r12,#31]
-	orr	r8,r8,r5,lsl#16
-	ldrb	r4,[r12,#30]
-	orr	r8,r8,r6,lsl#24
-	ldrb	r5,[r12,#29]
-	ldrb	r6,[r12,#28]
-	orr	r9,r9,r4,lsl#8
-	orr	r9,r9,r5,lsl#16
-	str	r8,[r11],#8
-	orr	r9,r9,r6,lsl#24
-	str	r9,[r11,#-4]
-#else
-	ldr	r8,[r12,#24]
-	ldr	r9,[r12,#28]
-#ifdef __ARMEL__
-	rev	r8,r8
-	rev	r9,r9
-#endif
-	str	r8,[r11],#8
-	str	r9,[r11,#-4]
-#endif
-
-	mov	r12,#14
-	str	r12,[r11,#240-32]
-	add	r6,r10,#256			@ rcon
-	mov	lr,#255
-	mov	r12,#7
-
-.L256_loop:
-	and	r5,lr,r9,lsr#24
-	and	r7,lr,r9,lsr#16
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r9,lsr#8
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r9
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#24
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r6],#4			@ rcon[i++]
-	orr	r5,r5,r9,lsl#8
-	eor	r9,r5,r4
-	eor	r0,r0,r9			@ rk[8]=rk[0]^...
-	eor	r1,r1,r0			@ rk[9]=rk[1]^rk[8]
-	str	r0,[r11],#32
-	eor	r2,r2,r1			@ rk[10]=rk[2]^rk[9]
-	str	r1,[r11,#-28]
-	eor	r3,r3,r2			@ rk[11]=rk[3]^rk[10]
-	str	r2,[r11,#-24]
-	subs	r12,r12,#1
-	str	r3,[r11,#-20]
-#ifdef	__thumb2__
-	itt	eq			@ Thumb2 thing, validity check in ARM
-#endif
-	subeq	r2,r11,#256
-	beq	.Ldone
-
-	and	r5,lr,r3
-	and	r7,lr,r3,lsr#8
-	ldrb	r5,[r10,r5]
-	and	r8,lr,r3,lsr#16
-	ldrb	r7,[r10,r7]
-	and	r9,lr,r3,lsr#24
-	ldrb	r8,[r10,r8]
-	orr	r5,r5,r7,lsl#8
-	ldrb	r9,[r10,r9]
-	orr	r5,r5,r8,lsl#16
-	ldr	r4,[r11,#-48]
-	orr	r5,r5,r9,lsl#24
-
-	ldr	r7,[r11,#-44]
-	ldr	r8,[r11,#-40]
-	eor	r4,r4,r5			@ rk[12]=rk[4]^...
-	ldr	r9,[r11,#-36]
-	eor	r7,r7,r4			@ rk[13]=rk[5]^rk[12]
-	str	r4,[r11,#-16]
-	eor	r8,r8,r7			@ rk[14]=rk[6]^rk[13]
-	str	r7,[r11,#-12]
-	eor	r9,r9,r8			@ rk[15]=rk[7]^rk[14]
-	str	r8,[r11,#-8]
-	str	r9,[r11,#-4]
-	b	.L256_loop
-
-.align	2
-.Ldone:	mov	r0,#0
-	ldmia   sp!,{r4-r12,lr}
-.Labrt:
-#if __ARM_ARCH__>=5
-	bx	lr				@ .word	0xe12fff1e
-#else
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_set_encrypt_key,.-aes_nohw_set_encrypt_key
-
-.global aes_nohw_set_decrypt_key
-.type   aes_nohw_set_decrypt_key,%function
-.align	5
-aes_nohw_set_decrypt_key:
-	str	lr,[sp,#-4]!            @ push lr
-	bl	_armv4_AES_set_encrypt_key
-	teq	r0,#0
-	ldr	lr,[sp],#4              @ pop lr
-	bne	.Labrt
-
-	mov	r0,r2			@ aes_nohw_set_encrypt_key preserves r2,
-	mov	r1,r2			@ which is AES_KEY *key
-	b	_armv4_AES_set_enc2dec_key
-.size	aes_nohw_set_decrypt_key,.-aes_nohw_set_decrypt_key
-
-@ void AES_set_enc2dec_key(const AES_KEY *inp,AES_KEY *out)
-.global	AES_set_enc2dec_key
-.type	AES_set_enc2dec_key,%function
-.align	5
-AES_set_enc2dec_key:
-_armv4_AES_set_enc2dec_key:
-	stmdb   sp!,{r4-r12,lr}
-
-	ldr	r12,[r0,#240]
-	mov	r7,r0			@ input
-	add	r8,r0,r12,lsl#4
-	mov	r11,r1			@ output
-	add	r10,r1,r12,lsl#4
-	str	r12,[r1,#240]
-
-.Linv:	ldr	r0,[r7],#16
-	ldr	r1,[r7,#-12]
-	ldr	r2,[r7,#-8]
-	ldr	r3,[r7,#-4]
-	ldr	r4,[r8],#-16
-	ldr	r5,[r8,#16+4]
-	ldr	r6,[r8,#16+8]
-	ldr	r9,[r8,#16+12]
-	str	r0,[r10],#-16
-	str	r1,[r10,#16+4]
-	str	r2,[r10,#16+8]
-	str	r3,[r10,#16+12]
-	str	r4,[r11],#16
-	str	r5,[r11,#-12]
-	str	r6,[r11,#-8]
-	str	r9,[r11,#-4]
-	teq	r7,r8
-	bne	.Linv
-
-	ldr	r0,[r7]
-	ldr	r1,[r7,#4]
-	ldr	r2,[r7,#8]
-	ldr	r3,[r7,#12]
-	str	r0,[r11]
-	str	r1,[r11,#4]
-	str	r2,[r11,#8]
-	str	r3,[r11,#12]
-	sub	r11,r11,r12,lsl#3
-	ldr	r0,[r11,#16]!		@ prefetch tp1
-	mov	r7,#0x80
-	mov	r8,#0x1b
-	orr	r7,r7,#0x8000
-	orr	r8,r8,#0x1b00
-	orr	r7,r7,r7,lsl#16
-	orr	r8,r8,r8,lsl#16
-	sub	r12,r12,#1
-	mvn	r9,r7
-	mov	r12,r12,lsl#2	@ (rounds-1)*4
-
-.Lmix:	and	r4,r0,r7
-	and	r1,r0,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r1,r4,r1,lsl#1	@ tp2
-
-	and	r4,r1,r7
-	and	r2,r1,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r2,r4,r2,lsl#1	@ tp4
-
-	and	r4,r2,r7
-	and	r3,r2,r9
-	sub	r4,r4,r4,lsr#7
-	and	r4,r4,r8
-	eor	r3,r4,r3,lsl#1	@ tp8
-
-	eor	r4,r1,r2
-	eor	r5,r0,r3		@ tp9
-	eor	r4,r4,r3		@ tpe
-	eor	r4,r4,r1,ror#24
-	eor	r4,r4,r5,ror#24	@ ^= ROTATE(tpb=tp9^tp2,8)
-	eor	r4,r4,r2,ror#16
-	eor	r4,r4,r5,ror#16	@ ^= ROTATE(tpd=tp9^tp4,16)
-	eor	r4,r4,r5,ror#8	@ ^= ROTATE(tp9,24)
-
-	ldr	r0,[r11,#4]		@ prefetch tp1
-	str	r4,[r11],#4
-	subs	r12,r12,#1
-	bne	.Lmix
-
-	mov	r0,#0
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	AES_set_enc2dec_key,.-AES_set_enc2dec_key
-
-.type	AES_Td,%object
-.align	5
-AES_Td:
-.word	0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
-.word	0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
-.word	0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
-.word	0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
-.word	0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
-.word	0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
-.word	0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
-.word	0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
-.word	0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
-.word	0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
-.word	0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
-.word	0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
-.word	0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
-.word	0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
-.word	0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
-.word	0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
-.word	0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
-.word	0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
-.word	0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
-.word	0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
-.word	0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
-.word	0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
-.word	0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
-.word	0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
-.word	0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
-.word	0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
-.word	0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
-.word	0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
-.word	0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
-.word	0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
-.word	0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
-.word	0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
-.word	0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
-.word	0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
-.word	0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
-.word	0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
-.word	0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
-.word	0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
-.word	0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
-.word	0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
-.word	0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
-.word	0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
-.word	0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
-.word	0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
-.word	0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
-.word	0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
-.word	0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
-.word	0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
-.word	0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
-.word	0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
-.word	0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
-.word	0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
-.word	0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
-.word	0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
-.word	0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
-.word	0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
-.word	0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
-.word	0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
-.word	0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
-.word	0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
-.word	0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
-.word	0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
-.word	0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
-.word	0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
-@ Td4[256]
-.byte	0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
-.byte	0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
-.byte	0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
-.byte	0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
-.byte	0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
-.byte	0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
-.byte	0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
-.byte	0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
-.byte	0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
-.byte	0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
-.byte	0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
-.byte	0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
-.byte	0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
-.byte	0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
-.byte	0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
-.byte	0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
-.byte	0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
-.byte	0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
-.byte	0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
-.byte	0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
-.byte	0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
-.byte	0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
-.byte	0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
-.byte	0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
-.byte	0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
-.byte	0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
-.byte	0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
-.byte	0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
-.byte	0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
-.byte	0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
-.byte	0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
-.byte	0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
-.size	AES_Td,.-AES_Td
-
-@ void aes_nohw_decrypt(const unsigned char *in, unsigned char *out,
-@ 		                  const AES_KEY *key) {
-.global aes_nohw_decrypt
-.type   aes_nohw_decrypt,%function
-.align	5
-aes_nohw_decrypt:
-#ifndef	__thumb2__
-	sub	r3,pc,#8		@ aes_nohw_decrypt
-#else
-	adr	r3,.
-#endif
-	stmdb   sp!,{r1,r4-r12,lr}
-#if defined(__thumb2__) || defined(__APPLE__)
-	adr	r10,AES_Td
-#else
-	sub	r10,r3,#aes_nohw_decrypt-AES_Td	@ Td
-#endif
-	mov	r12,r0		@ inp
-	mov	r11,r2
-#if __ARM_ARCH__<7
-	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
-	ldrb	r4,[r12,#2]	@ manner...
-	ldrb	r5,[r12,#1]
-	ldrb	r6,[r12,#0]
-	orr	r0,r0,r4,lsl#8
-	ldrb	r1,[r12,#7]
-	orr	r0,r0,r5,lsl#16
-	ldrb	r4,[r12,#6]
-	orr	r0,r0,r6,lsl#24
-	ldrb	r5,[r12,#5]
-	ldrb	r6,[r12,#4]
-	orr	r1,r1,r4,lsl#8
-	ldrb	r2,[r12,#11]
-	orr	r1,r1,r5,lsl#16
-	ldrb	r4,[r12,#10]
-	orr	r1,r1,r6,lsl#24
-	ldrb	r5,[r12,#9]
-	ldrb	r6,[r12,#8]
-	orr	r2,r2,r4,lsl#8
-	ldrb	r3,[r12,#15]
-	orr	r2,r2,r5,lsl#16
-	ldrb	r4,[r12,#14]
-	orr	r2,r2,r6,lsl#24
-	ldrb	r5,[r12,#13]
-	ldrb	r6,[r12,#12]
-	orr	r3,r3,r4,lsl#8
-	orr	r3,r3,r5,lsl#16
-	orr	r3,r3,r6,lsl#24
-#else
-	ldr	r0,[r12,#0]
-	ldr	r1,[r12,#4]
-	ldr	r2,[r12,#8]
-	ldr	r3,[r12,#12]
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-#endif
-	bl	_armv4_AES_decrypt
-
-	ldr	r12,[sp],#4		@ pop out
-#if __ARM_ARCH__>=7
-#ifdef __ARMEL__
-	rev	r0,r0
-	rev	r1,r1
-	rev	r2,r2
-	rev	r3,r3
-#endif
-	str	r0,[r12,#0]
-	str	r1,[r12,#4]
-	str	r2,[r12,#8]
-	str	r3,[r12,#12]
-#else
-	mov	r4,r0,lsr#24		@ write output in endian-neutral
-	mov	r5,r0,lsr#16		@ manner...
-	mov	r6,r0,lsr#8
-	strb	r4,[r12,#0]
-	strb	r5,[r12,#1]
-	mov	r4,r1,lsr#24
-	strb	r6,[r12,#2]
-	mov	r5,r1,lsr#16
-	strb	r0,[r12,#3]
-	mov	r6,r1,lsr#8
-	strb	r4,[r12,#4]
-	strb	r5,[r12,#5]
-	mov	r4,r2,lsr#24
-	strb	r6,[r12,#6]
-	mov	r5,r2,lsr#16
-	strb	r1,[r12,#7]
-	mov	r6,r2,lsr#8
-	strb	r4,[r12,#8]
-	strb	r5,[r12,#9]
-	mov	r4,r3,lsr#24
-	strb	r6,[r12,#10]
-	mov	r5,r3,lsr#16
-	strb	r2,[r12,#11]
-	mov	r6,r3,lsr#8
-	strb	r4,[r12,#12]
-	strb	r5,[r12,#13]
-	strb	r6,[r12,#14]
-	strb	r3,[r12,#15]
-#endif
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r12,pc}
-#else
-	ldmia   sp!,{r4-r12,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	aes_nohw_decrypt,.-aes_nohw_decrypt
-
-.type   _armv4_AES_decrypt,%function
-.align	2
-_armv4_AES_decrypt:
-	str	lr,[sp,#-4]!		@ push lr
-	ldmia	r11!,{r4-r7}
-	eor	r0,r0,r4
-	ldr	r12,[r11,#240-16]
-	eor	r1,r1,r5
-	eor	r2,r2,r6
-	eor	r3,r3,r7
-	sub	r12,r12,#1
-	mov	lr,#255
-
-	and	r7,lr,r0,lsr#16
-	and	r8,lr,r0,lsr#8
-	and	r9,lr,r0
-	mov	r0,r0,lsr#24
-.Ldec_loop:
-	ldr	r4,[r10,r7,lsl#2]	@ Td1[s0>>16]
-	and	r7,lr,r1		@ i0
-	ldr	r5,[r10,r8,lsl#2]	@ Td2[s0>>8]
-	and	r8,lr,r1,lsr#16
-	ldr	r6,[r10,r9,lsl#2]	@ Td3[s0>>0]
-	and	r9,lr,r1,lsr#8
-	ldr	r0,[r10,r0,lsl#2]	@ Td0[s0>>24]
-	mov	r1,r1,lsr#24
-
-	ldr	r7,[r10,r7,lsl#2]	@ Td3[s1>>0]
-	ldr	r8,[r10,r8,lsl#2]	@ Td1[s1>>16]
-	ldr	r9,[r10,r9,lsl#2]	@ Td2[s1>>8]
-	eor	r0,r0,r7,ror#24
-	ldr	r1,[r10,r1,lsl#2]	@ Td0[s1>>24]
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r8,r5,ror#8
-	and	r8,lr,r2		@ i1
-	eor	r6,r9,r6,ror#8
-	and	r9,lr,r2,lsr#16
-	ldr	r7,[r10,r7,lsl#2]	@ Td2[s2>>8]
-	eor	r1,r1,r4,ror#8
-	ldr	r8,[r10,r8,lsl#2]	@ Td3[s2>>0]
-	mov	r2,r2,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Td1[s2>>16]
-	eor	r0,r0,r7,ror#16
-	ldr	r2,[r10,r2,lsl#2]	@ Td0[s2>>24]
-	and	r7,lr,r3,lsr#16	@ i0
-	eor	r1,r1,r8,ror#24
-	and	r8,lr,r3,lsr#8	@ i1
-	eor	r6,r9,r6,ror#8
-	and	r9,lr,r3		@ i2
-	ldr	r7,[r10,r7,lsl#2]	@ Td1[s3>>16]
-	eor	r2,r2,r5,ror#8
-	ldr	r8,[r10,r8,lsl#2]	@ Td2[s3>>8]
-	mov	r3,r3,lsr#24
-
-	ldr	r9,[r10,r9,lsl#2]	@ Td3[s3>>0]
-	eor	r0,r0,r7,ror#8
-	ldr	r7,[r11],#16
-	eor	r1,r1,r8,ror#16
-	ldr	r3,[r10,r3,lsl#2]	@ Td0[s3>>24]
-	eor	r2,r2,r9,ror#24
-
-	ldr	r4,[r11,#-12]
-	eor	r0,r0,r7
-	ldr	r5,[r11,#-8]
-	eor	r3,r3,r6,ror#8
-	ldr	r6,[r11,#-4]
-	and	r7,lr,r0,lsr#16
-	eor	r1,r1,r4
-	and	r8,lr,r0,lsr#8
-	eor	r2,r2,r5
-	and	r9,lr,r0
-	eor	r3,r3,r6
-	mov	r0,r0,lsr#24
-
-	subs	r12,r12,#1
-	bne	.Ldec_loop
-
-	add	r10,r10,#1024
-
-	ldr	r5,[r10,#0]		@ prefetch Td4
-	ldr	r6,[r10,#32]
-	ldr	r4,[r10,#64]
-	ldr	r5,[r10,#96]
-	ldr	r6,[r10,#128]
-	ldr	r4,[r10,#160]
-	ldr	r5,[r10,#192]
-	ldr	r6,[r10,#224]
-
-	ldrb	r0,[r10,r0]		@ Td4[s0>>24]
-	ldrb	r4,[r10,r7]		@ Td4[s0>>16]
-	and	r7,lr,r1		@ i0
-	ldrb	r5,[r10,r8]		@ Td4[s0>>8]
-	and	r8,lr,r1,lsr#16
-	ldrb	r6,[r10,r9]		@ Td4[s0>>0]
-	and	r9,lr,r1,lsr#8
-
-	add	r1,r10,r1,lsr#24
-	ldrb	r7,[r10,r7]		@ Td4[s1>>0]
-	ldrb	r1,[r1]		@ Td4[s1>>24]
-	ldrb	r8,[r10,r8]		@ Td4[s1>>16]
-	eor	r0,r7,r0,lsl#24
-	ldrb	r9,[r10,r9]		@ Td4[s1>>8]
-	eor	r1,r4,r1,lsl#8
-	and	r7,lr,r2,lsr#8	@ i0
-	eor	r5,r5,r8,lsl#8
-	and	r8,lr,r2		@ i1
-	ldrb	r7,[r10,r7]		@ Td4[s2>>8]
-	eor	r6,r6,r9,lsl#8
-	ldrb	r8,[r10,r8]		@ Td4[s2>>0]
-	and	r9,lr,r2,lsr#16
-
-	add	r2,r10,r2,lsr#24
-	ldrb	r2,[r2]		@ Td4[s2>>24]
-	eor	r0,r0,r7,lsl#8
-	ldrb	r9,[r10,r9]		@ Td4[s2>>16]
-	eor	r1,r8,r1,lsl#16
-	and	r7,lr,r3,lsr#16	@ i0
-	eor	r2,r5,r2,lsl#16
-	and	r8,lr,r3,lsr#8	@ i1
-	ldrb	r7,[r10,r7]		@ Td4[s3>>16]
-	eor	r6,r6,r9,lsl#16
-	ldrb	r8,[r10,r8]		@ Td4[s3>>8]
-	and	r9,lr,r3		@ i2
-
-	add	r3,r10,r3,lsr#24
-	ldrb	r9,[r10,r9]		@ Td4[s3>>0]
-	ldrb	r3,[r3]		@ Td4[s3>>24]
-	eor	r0,r0,r7,lsl#16
-	ldr	r7,[r11,#0]
-	eor	r1,r1,r8,lsl#8
-	ldr	r4,[r11,#4]
-	eor	r2,r9,r2,lsl#8
-	ldr	r5,[r11,#8]
-	eor	r3,r6,r3,lsl#24
-	ldr	r6,[r11,#12]
-
-	eor	r0,r0,r7
-	eor	r1,r1,r4
-	eor	r2,r2,r5
-	eor	r3,r3,r6
-
-	sub	r10,r10,#1024
-	ldr	pc,[sp],#4		@ pop and return
-.size	_armv4_AES_decrypt,.-_armv4_AES_decrypt
-.asciz	"AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
-.align	2
diff --git a/third_party/boringssl/core/cortex-m/ghash.S b/third_party/boringssl/core/cortex-m/ghash.S
deleted file mode 100644
index a1eb97b9c5..0000000000
--- a/third_party/boringssl/core/cortex-m/ghash.S
+++ /dev/null
@@ -1,575 +0,0 @@
-@ Generated by crypto/fipsmodule/modes/asm/ghash-armv4.pl, which carries
-@ this license:
-@
-@ Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved.
-@
-@ Licensed under the OpenSSL license (the "License").  You may not use
-@ this file except in compliance with the License.  You can obtain a copy
-@ in the file LICENSE in the source distribution or at
-@ https://www.openssl.org/source/license.html
-
-#define __ARM_ARCH__ 7
-
-.text
-#if defined(__thumb2__) || defined(__clang__)
-.syntax	unified
-#endif
-#if defined(__thumb2__)
-.thumb
-#else
-.code	32
-#endif
-
-#ifdef  __clang__
-#define ldrplb  ldrbpl
-#define ldrneb  ldrbne
-#endif
-
-.type	rem_4bit,%object
-.align	5
-rem_4bit:
-.short	0x0000,0x1C20,0x3840,0x2460
-.short	0x7080,0x6CA0,0x48C0,0x54E0
-.short	0xE100,0xFD20,0xD940,0xC560
-.short	0x9180,0x8DA0,0xA9C0,0xB5E0
-.size	rem_4bit,.-rem_4bit
-
-.type	rem_4bit_get,%function
-rem_4bit_get:
-#if defined(__thumb2__)
-	adr	r2,rem_4bit
-#else
-	sub	r2,pc,#8+32	@ &rem_4bit
-#endif
-	b	.Lrem_4bit_got
-	nop
-	nop
-.size	rem_4bit_get,.-rem_4bit_get
-
-.global	gcm_ghash_4bit
-.type	gcm_ghash_4bit,%function
-.align	4
-gcm_ghash_4bit:
-#if defined(__thumb2__)
-	adr	r12,rem_4bit
-#else
-	sub	r12,pc,#8+48		@ &rem_4bit
-#endif
-	add	r3,r2,r3		@ r3 to point at the end
-	stmdb	sp!,{r3-r11,lr}		@ save r3/end too
-
-	ldmia	r12,{r4-r11}		@ copy rem_4bit ...
-	stmdb	sp!,{r4-r11}		@ ... to stack
-
-	ldrb	r12,[r2,#15]
-	ldrb	r14,[r0,#15]
-.Louter:
-	eor	r12,r12,r14
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	mov	r3,#14
-
-	add	r7,r1,r12,lsl#4
-	ldmia	r7,{r4-r7}	@ load Htbl[nlo]
-	add	r11,r1,r14
-	ldrb	r12,[r2,#14]
-
-	and	r14,r4,#0xf		@ rem
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	add	r14,r14,r14
-	eor	r4,r8,r4,lsr#4
-	ldrh	r8,[sp,r14]		@ rem_4bit[rem]
-	eor	r4,r4,r5,lsl#28
-	ldrb	r14,[r0,#14]
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-	eor	r12,r12,r14
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	eor	r7,r7,r8,lsl#16
-
-.Linner:
-	add	r11,r1,r12,lsl#4
-	and	r12,r4,#0xf		@ rem
-	subs	r3,r3,#1
-	add	r12,r12,r12
-	ldmia	r11,{r8-r11}	@ load Htbl[nlo]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	ldrh	r8,[sp,r12]		@ rem_4bit[rem]
-	eor	r6,r10,r6,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r12,[r2,r3]
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	add	r14,r14,r14
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	eor	r4,r8,r4,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r8,[r0,r3]
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	ldrh	r9,[sp,r14]
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-#ifdef	__thumb2__
-	it	pl
-#endif
-	eorpl	r12,r12,r8
-	eor	r7,r11,r7,lsr#4
-#ifdef	__thumb2__
-	itt	pl
-#endif
-	andpl	r14,r12,#0xf0
-	andpl	r12,r12,#0x0f
-	eor	r7,r7,r9,lsl#16	@ ^= rem_4bit[rem]
-	bpl	.Linner
-
-	ldr	r3,[sp,#32]		@ re-load r3/end
-	add	r2,r2,#16
-	mov	r14,r4
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r4,r4
-	str	r4,[r0,#12]
-#elif defined(__ARMEB__)
-	str	r4,[r0,#12]
-#else
-	mov	r9,r4,lsr#8
-	strb	r4,[r0,#12+3]
-	mov	r10,r4,lsr#16
-	strb	r9,[r0,#12+2]
-	mov	r11,r4,lsr#24
-	strb	r10,[r0,#12+1]
-	strb	r11,[r0,#12]
-#endif
-	cmp	r2,r3
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r5,r5
-	str	r5,[r0,#8]
-#elif defined(__ARMEB__)
-	str	r5,[r0,#8]
-#else
-	mov	r9,r5,lsr#8
-	strb	r5,[r0,#8+3]
-	mov	r10,r5,lsr#16
-	strb	r9,[r0,#8+2]
-	mov	r11,r5,lsr#24
-	strb	r10,[r0,#8+1]
-	strb	r11,[r0,#8]
-#endif
-	
-#ifdef __thumb2__
-	it	ne
-#endif
-	ldrbne	r12,[r2,#15]
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r6,r6
-	str	r6,[r0,#4]
-#elif defined(__ARMEB__)
-	str	r6,[r0,#4]
-#else
-	mov	r9,r6,lsr#8
-	strb	r6,[r0,#4+3]
-	mov	r10,r6,lsr#16
-	strb	r9,[r0,#4+2]
-	mov	r11,r6,lsr#24
-	strb	r10,[r0,#4+1]
-	strb	r11,[r0,#4]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r7,r7
-	str	r7,[r0,#0]
-#elif defined(__ARMEB__)
-	str	r7,[r0,#0]
-#else
-	mov	r9,r7,lsr#8
-	strb	r7,[r0,#0+3]
-	mov	r10,r7,lsr#16
-	strb	r9,[r0,#0+2]
-	mov	r11,r7,lsr#24
-	strb	r10,[r0,#0+1]
-	strb	r11,[r0,#0]
-#endif
-	
-	bne	.Louter
-
-	add	sp,sp,#36
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r11,pc}
-#else
-	ldmia	sp!,{r4-r11,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	gcm_ghash_4bit,.-gcm_ghash_4bit
-
-.global	gcm_gmult_4bit
-.type	gcm_gmult_4bit,%function
-gcm_gmult_4bit:
-	stmdb	sp!,{r4-r11,lr}
-	ldrb	r12,[r0,#15]
-	b	rem_4bit_get
-.Lrem_4bit_got:
-	and	r14,r12,#0xf0
-	and	r12,r12,#0x0f
-	mov	r3,#14
-
-	add	r7,r1,r12,lsl#4
-	ldmia	r7,{r4-r7}	@ load Htbl[nlo]
-	ldrb	r12,[r0,#14]
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	add	r14,r14,r14
-	eor	r4,r8,r4,lsr#4
-	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-	and	r14,r12,#0xf0
-	eor	r7,r7,r8,lsl#16
-	and	r12,r12,#0x0f
-
-.Loop:
-	add	r11,r1,r12,lsl#4
-	and	r12,r4,#0xf		@ rem
-	subs	r3,r3,#1
-	add	r12,r12,r12
-	ldmia	r11,{r8-r11}	@ load Htbl[nlo]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	eor	r5,r5,r6,lsl#28
-	ldrh	r8,[r2,r12]	@ rem_4bit[rem]
-	eor	r6,r10,r6,lsr#4
-#ifdef	__thumb2__
-	it	pl
-#endif
-	ldrbpl	r12,[r0,r3]
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-
-	add	r11,r1,r14
-	and	r14,r4,#0xf		@ rem
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	add	r14,r14,r14
-	ldmia	r11,{r8-r11}	@ load Htbl[nhi]
-	eor	r4,r8,r4,lsr#4
-	eor	r4,r4,r5,lsl#28
-	eor	r5,r9,r5,lsr#4
-	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
-	eor	r5,r5,r6,lsl#28
-	eor	r6,r10,r6,lsr#4
-	eor	r6,r6,r7,lsl#28
-	eor	r7,r11,r7,lsr#4
-#ifdef	__thumb2__
-	itt	pl
-#endif
-	andpl	r14,r12,#0xf0
-	andpl	r12,r12,#0x0f
-	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
-	bpl	.Loop
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r4,r4
-	str	r4,[r0,#12]
-#elif defined(__ARMEB__)
-	str	r4,[r0,#12]
-#else
-	mov	r9,r4,lsr#8
-	strb	r4,[r0,#12+3]
-	mov	r10,r4,lsr#16
-	strb	r9,[r0,#12+2]
-	mov	r11,r4,lsr#24
-	strb	r10,[r0,#12+1]
-	strb	r11,[r0,#12]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r5,r5
-	str	r5,[r0,#8]
-#elif defined(__ARMEB__)
-	str	r5,[r0,#8]
-#else
-	mov	r9,r5,lsr#8
-	strb	r5,[r0,#8+3]
-	mov	r10,r5,lsr#16
-	strb	r9,[r0,#8+2]
-	mov	r11,r5,lsr#24
-	strb	r10,[r0,#8+1]
-	strb	r11,[r0,#8]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r6,r6
-	str	r6,[r0,#4]
-#elif defined(__ARMEB__)
-	str	r6,[r0,#4]
-#else
-	mov	r9,r6,lsr#8
-	strb	r6,[r0,#4+3]
-	mov	r10,r6,lsr#16
-	strb	r9,[r0,#4+2]
-	mov	r11,r6,lsr#24
-	strb	r10,[r0,#4+1]
-	strb	r11,[r0,#4]
-#endif
-	
-#if __ARM_ARCH__>=7 && defined(__ARMEL__)
-	rev	r7,r7
-	str	r7,[r0,#0]
-#elif defined(__ARMEB__)
-	str	r7,[r0,#0]
-#else
-	mov	r9,r7,lsr#8
-	strb	r7,[r0,#0+3]
-	mov	r10,r7,lsr#16
-	strb	r9,[r0,#0+2]
-	mov	r11,r7,lsr#24
-	strb	r10,[r0,#0+1]
-	strb	r11,[r0,#0]
-#endif
-	
-#if __ARM_ARCH__>=5
-	ldmia	sp!,{r4-r11,pc}
-#else
-	ldmia	sp!,{r4-r11,lr}
-	tst	lr,#1
-	moveq	pc,lr			@ be binary compatible with V4, yet
-	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
-#endif
-.size	gcm_gmult_4bit,.-gcm_gmult_4bit
-#ifdef __ARM_NEON__
-.arch	armv7-a
-.fpu	neon
-
-.global	gcm_init_neon
-.type	gcm_init_neon,%function
-.align	4
-gcm_init_neon:
-	vld1.64		d7,[r1]!		@ load H
-	vmov.i8		q8,#0xe1
-	vld1.64		d6,[r1]
-	vshl.i64	d17,#57
-	vshr.u64	d16,#63		@ t0=0xc2....01
-	vdup.8		q9,d7[7]
-	vshr.u64	d26,d6,#63
-	vshr.s8		q9,#7			@ broadcast carry bit
-	vshl.i64	q3,q3,#1
-	vand		q8,q8,q9
-	vorr		d7,d26		@ H<<<=1
-	veor		q3,q3,q8		@ twisted H
-	vstmia		r0,{q3}
-
-	bx	lr					@ bx lr
-.size	gcm_init_neon,.-gcm_init_neon
-
-.global	gcm_gmult_neon
-.type	gcm_gmult_neon,%function
-.align	4
-gcm_gmult_neon:
-	vld1.64		d7,[r0]!		@ load Xi
-	vld1.64		d6,[r0]!
-	vmov.i64	d29,#0x0000ffffffffffff
-	vldmia		r1,{d26-d27}	@ load twisted H
-	vmov.i64	d30,#0x00000000ffffffff
-#ifdef __ARMEL__
-	vrev64.8	q3,q3
-#endif
-	vmov.i64	d31,#0x000000000000ffff
-	veor		d28,d26,d27		@ Karatsuba pre-processing
-	mov		r3,#16
-	b		.Lgmult_neon
-.size	gcm_gmult_neon,.-gcm_gmult_neon
-
-.global	gcm_ghash_neon
-.type	gcm_ghash_neon,%function
-.align	4
-gcm_ghash_neon:
-	vld1.64		d1,[r0]!		@ load Xi
-	vld1.64		d0,[r0]!
-	vmov.i64	d29,#0x0000ffffffffffff
-	vldmia		r1,{d26-d27}	@ load twisted H
-	vmov.i64	d30,#0x00000000ffffffff
-#ifdef __ARMEL__
-	vrev64.8	q0,q0
-#endif
-	vmov.i64	d31,#0x000000000000ffff
-	veor		d28,d26,d27		@ Karatsuba pre-processing
-
-.Loop_neon:
-	vld1.64		d7,[r2]!		@ load inp
-	vld1.64		d6,[r2]!
-#ifdef __ARMEL__
-	vrev64.8	q3,q3
-#endif
-	veor		q3,q0			@ inp^=Xi
-.Lgmult_neon:
-	vext.8		d16, d26, d26, #1	@ A1
-	vmull.p8	q8, d16, d6		@ F = A1*B
-	vext.8		d0, d6, d6, #1	@ B1
-	vmull.p8	q0, d26, d0		@ E = A*B1
-	vext.8		d18, d26, d26, #2	@ A2
-	vmull.p8	q9, d18, d6		@ H = A2*B
-	vext.8		d22, d6, d6, #2	@ B2
-	vmull.p8	q11, d26, d22		@ G = A*B2
-	vext.8		d20, d26, d26, #3	@ A3
-	veor		q8, q8, q0		@ L = E + F
-	vmull.p8	q10, d20, d6		@ J = A3*B
-	vext.8		d0, d6, d6, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q0, d26, d0		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d6, d6, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d26, d22		@ K = A*B4
-	veor		q10, q10, q0		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q0, d26, d6		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q0, q0, q8
-	veor		q0, q0, q10
-	veor		d6,d6,d7	@ Karatsuba pre-processing
-	vext.8		d16, d28, d28, #1	@ A1
-	vmull.p8	q8, d16, d6		@ F = A1*B
-	vext.8		d2, d6, d6, #1	@ B1
-	vmull.p8	q1, d28, d2		@ E = A*B1
-	vext.8		d18, d28, d28, #2	@ A2
-	vmull.p8	q9, d18, d6		@ H = A2*B
-	vext.8		d22, d6, d6, #2	@ B2
-	vmull.p8	q11, d28, d22		@ G = A*B2
-	vext.8		d20, d28, d28, #3	@ A3
-	veor		q8, q8, q1		@ L = E + F
-	vmull.p8	q10, d20, d6		@ J = A3*B
-	vext.8		d2, d6, d6, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q1, d28, d2		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d6, d6, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d28, d22		@ K = A*B4
-	veor		q10, q10, q1		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q1, d28, d6		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q1, q1, q8
-	veor		q1, q1, q10
-	vext.8		d16, d27, d27, #1	@ A1
-	vmull.p8	q8, d16, d7		@ F = A1*B
-	vext.8		d4, d7, d7, #1	@ B1
-	vmull.p8	q2, d27, d4		@ E = A*B1
-	vext.8		d18, d27, d27, #2	@ A2
-	vmull.p8	q9, d18, d7		@ H = A2*B
-	vext.8		d22, d7, d7, #2	@ B2
-	vmull.p8	q11, d27, d22		@ G = A*B2
-	vext.8		d20, d27, d27, #3	@ A3
-	veor		q8, q8, q2		@ L = E + F
-	vmull.p8	q10, d20, d7		@ J = A3*B
-	vext.8		d4, d7, d7, #3	@ B3
-	veor		q9, q9, q11		@ M = G + H
-	vmull.p8	q2, d27, d4		@ I = A*B3
-	veor		d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
-	vand		d17, d17, d29
-	vext.8		d22, d7, d7, #4	@ B4
-	veor		d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
-	vand		d19, d19, d30
-	vmull.p8	q11, d27, d22		@ K = A*B4
-	veor		q10, q10, q2		@ N = I + J
-	veor		d16, d16, d17
-	veor		d18, d18, d19
-	veor		d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
-	vand		d21, d21, d31
-	vext.8		q8, q8, q8, #15
-	veor		d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
-	vmov.i64	d23, #0
-	vext.8		q9, q9, q9, #14
-	veor		d20, d20, d21
-	vmull.p8	q2, d27, d7		@ D = A*B
-	vext.8		q11, q11, q11, #12
-	vext.8		q10, q10, q10, #13
-	veor		q8, q8, q9
-	veor		q10, q10, q11
-	veor		q2, q2, q8
-	veor		q2, q2, q10
-	veor		q1,q1,q0		@ Karatsuba post-processing
-	veor		q1,q1,q2
-	veor		d1,d1,d2
-	veor		d4,d4,d3	@ Xh|Xl - 256-bit result
-
-	@ equivalent of reduction_avx from ghash-x86_64.pl
-	vshl.i64	q9,q0,#57		@ 1st phase
-	vshl.i64	q10,q0,#62
-	veor		q10,q10,q9		@
-	vshl.i64	q9,q0,#63
-	veor		q10, q10, q9		@
- 	veor		d1,d1,d20	@
-	veor		d4,d4,d21
-
-	vshr.u64	q10,q0,#1		@ 2nd phase
-	veor		q2,q2,q0
-	veor		q0,q0,q10		@
-	vshr.u64	q10,q10,#6
-	vshr.u64	q0,q0,#1		@
-	veor		q0,q0,q2		@
-	veor		q0,q0,q10		@
-
-	subs		r3,#16
-	bne		.Loop_neon
-
-#ifdef __ARMEL__
-	vrev64.8	q0,q0
-#endif
-	sub		r0,#16
-	vst1.64		d1,[r0]!		@ write out Xi
-	vst1.64		d0,[r0]
-
-	bx	lr					@ bx lr
-.size	gcm_ghash_neon,.-gcm_ghash_neon
-#endif
-.asciz  "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
-.align  2
diff --git a/third_party/boringssl/include/aes-gcm.h b/third_party/boringssl/include/aes-gcm.h
deleted file mode 100644
index e3ef457224..0000000000
--- a/third_party/boringssl/include/aes-gcm.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2008 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#ifndef __CROS_EC_AES_GCM_H
-#define __CROS_EC_AES_GCM_H
-
-#include "common.h"
-#include "endian.h"
-#include "util.h"
-
-// block128_f is the type of a 128-bit, block cipher.
-typedef void (*block128_f)(const uint8_t in[16], uint8_t out[16],
-                           const void *key);
-
-// GCM definitions
-typedef struct { uint64_t hi,lo; } u128;
-
-// gmult_func multiplies |Xi| by the GCM key and writes the result back to
-// |Xi|.
-typedef void (*gmult_func)(uint64_t Xi[2], const u128 Htable[16]);
-
-// ghash_func repeatedly multiplies |Xi| by the GCM key and adds in blocks from
-// |inp|. The result is written back to |Xi| and the |len| argument must be a
-// multiple of 16.
-typedef void (*ghash_func)(uint64_t Xi[2], const u128 Htable[16],
-                           const uint8_t *inp, size_t len);
-
-// This differs from upstream's |gcm128_context| in that it does not have the
-// |key| pointer, in order to make it |memcpy|-friendly. Rather the key is
-// passed into each call that needs it.
-struct gcm128_context {
-  // Following 6 names follow names in GCM specification
-  union {
-    uint64_t u[2];
-    uint32_t d[4];
-    uint8_t c[16];
-    size_t t[16 / sizeof(size_t)];
-  } Yi, EKi, EK0, len, Xi;
-
-  // Note that the order of |Xi|, |H| and |Htable| is fixed by the MOVBE-based,
-  // x86-64, GHASH assembly.
-  u128 H;
-  u128 Htable[16];
-  gmult_func gmult;
-  ghash_func ghash;
-
-  unsigned int mres, ares;
-  block128_f block;
-};
-
-
-// GCM.
-//
-// This API differs from the upstream API slightly. The |GCM128_CONTEXT| does
-// not have a |key| pointer that points to the key as upstream's version does.
-// Instead, every function takes a |key| parameter. This way |GCM128_CONTEXT|
-// can be safely copied.
-
-typedef struct gcm128_context GCM128_CONTEXT;
-
-// CRYPTO_gcm128_init initialises |ctx| to use |block| (typically AES) with
-// the given key. |block_is_hwaes| is one if |block| is |aes_hw_encrypt|.
-void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *key,
-                                       block128_f block, int block_is_hwaes);
-
-// CRYPTO_gcm128_setiv sets the IV (nonce) for |ctx|. The |key| must be the
-// same key that was passed to |CRYPTO_gcm128_init|.
-void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key,
-                                        const uint8_t *iv, size_t iv_len);
-
-// CRYPTO_gcm128_aad sets the authenticated data for an instance of GCM.
-// This must be called before and data is encrypted. It returns one on success
-// and zero otherwise.
-int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad,
-                                     size_t len);
-
-// CRYPTO_gcm128_encrypt encrypts |len| bytes from |in| to |out|. The |key|
-// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one
-// on success and zero otherwise.
-int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key,
-                                         const uint8_t *in, uint8_t *out,
-                                         size_t len);
-
-// CRYPTO_gcm128_decrypt decrypts |len| bytes from |in| to |out|. The |key|
-// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one
-// on success and zero otherwise.
-int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key,
-                                         const uint8_t *in, uint8_t *out,
-                                         size_t len);
-
-// CRYPTO_gcm128_finish calculates the authenticator and compares it against
-// |len| bytes of |tag|. It returns one on success and zero otherwise.
-int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag,
-                                        size_t len);
-
-// CRYPTO_gcm128_tag calculates the authenticator and copies it into |tag|.
-// The minimum of |len| and 16 bytes are copied into |tag|.
-void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, uint8_t *tag,
-                                      size_t len);
-
-
-#endif  // __CROS_EC_AES_GCM_H
diff --git a/third_party/boringssl/include/aes.h b/third_party/boringssl/include/aes.h
deleted file mode 100644
index 6418a350eb..0000000000
--- a/third_party/boringssl/include/aes.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ====================================================================
- * Copyright (c) 2002-2006 The OpenSSL Project.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. All advertising materials mentioning features or use of this
- *    software must display the following acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
- *
- * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For written permission, please contact
- *    openssl-core@openssl.org.
- *
- * 5. Products derived from this software may not be called "OpenSSL"
- *    nor may "OpenSSL" appear in their names without prior written
- *    permission of the OpenSSL Project.
- *
- * 6. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by the OpenSSL Project
- *    for use in the OpenSSL Toolkit (http://www.openssl.org/)"
- *
- * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
- * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
- * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- * ==================================================================== */
-
-#ifndef __CROS_EC_AES_H
-#define __CROS_EC_AES_H
-
-#include <stdint.h>
-
-#define AES_ENCRYPT 1
-#define AES_DECRYPT 0
-
-/* AES_MAXNR is the maximum number of AES rounds. */
-#define AES_MAXNR 14
-
-#define AES_BLOCK_SIZE 16
-
-/*
- * aes_key_st should be an opaque type, but EVP requires that the size be
- * known.
- */
-struct aes_key_st {
-  uint32_t rd_key[4 * (AES_MAXNR + 1)];
-  unsigned rounds;
-};
-typedef struct aes_key_st AES_KEY;
-
-/*
- * These functions are provided by either common/aes.c, or assembly code,
- * and should not be called directly.
- */
-void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key);
-void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key);
-int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits,
-                             AES_KEY *aeskey);
-int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits,
-                             AES_KEY *aeskey);
-
-/**
- * AES_set_encrypt_key configures |aeskey| to encrypt with the |bits|-bit key,
- * |key|.
- *
- * WARNING: unlike other OpenSSL functions, this returns zero on success and a
- * negative number on error.
- */
-static inline int AES_set_encrypt_key(const uint8_t *key, unsigned int bits,
-				      AES_KEY *aeskey)
-{
-	return aes_nohw_set_encrypt_key(key, bits, aeskey);
-}
-
-/**
- * AES_set_decrypt_key configures |aeskey| to decrypt with the |bits|-bit key,
- * |key|.
- *
- * WARNING: unlike other OpenSSL functions, this returns zero on success and a
- * negative number on error.
- */
-static inline int AES_set_decrypt_key(const uint8_t *key, unsigned int bits,
-				      AES_KEY *aeskey)
-{
-	return aes_nohw_set_decrypt_key(key, bits, aeskey);
-}
-
-/**
- * AES_encrypt encrypts a single block from |in| to |out| with |key|. The |in|
- * and |out| pointers may overlap.
- */
-static inline void AES_encrypt(const uint8_t *in, uint8_t *out,
-			       const AES_KEY *key)
-{
-	aes_nohw_encrypt(in, out, key);
-}
-
-/**
- * AES_decrypt decrypts a single block from |in| to |out| with |key|. The |in|
- * and |out| pointers may overlap.
- */
-static inline void AES_decrypt(const uint8_t *in, uint8_t *out,
-			const AES_KEY *key)
-{
-	aes_nohw_decrypt(in, out, key);
-}
-
-#endif  /* __CROS_EC_AES_H */
diff --git a/third_party/boringssl/include/curve25519.h b/third_party/boringssl/include/curve25519.h
deleted file mode 100644
index 8287c94466..0000000000
--- a/third_party/boringssl/include/curve25519.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CURVE25519_H
-#define __CROS_EC_CURVE25519_H
-
-#include <stdint.h>
-
-/* Curve25519.
- *
- * Curve25519 is an elliptic curve. See https://tools.ietf.org/html/rfc7748.
- */
-
-
-/* X25519.
- *
- * X25519 is the Diffie-Hellman primitive built from curve25519. It is
- * sometimes referred to as “curve25519�, but “X25519� is a more precise
- * name.
- * See http://cr.yp.to/ecdh.html and https://tools.ietf.org/html/rfc7748.
- */
-
-#define X25519_PRIVATE_KEY_LEN 32
-#define X25519_PUBLIC_VALUE_LEN 32
-
-/**
- * Generate a public/private key pair.
- * @param out_public_value generated public key.
- * @param out_private_value generated private key.
- */
-void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]);
-
-/**
- * Diffie-Hellman function.
- * @param out_shared_key
- * @param private_key
- * @param out_public_value
- * @return one on success and zero on error.
- *
- * X25519() writes a shared key to @out_shared_key that is calculated from the
- * given private key and the peer's public value.
- *
- * Don't use the shared key directly, rather use a KDF and also include the two
- * public values as inputs.
- */
-int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32],
-	   const uint8_t peers_public_value[32]);
-
-/**
- * Compute the matching public key.
- * @param out_public_value computed public key.
- * @param private_key private key to use.
- *
- * X25519_public_from_private() calculates a Diffie-Hellman public value from
- * the given private key and writes it to @out_public_value.
- */
-void X25519_public_from_private(uint8_t out_public_value[32],
-				const uint8_t private_key[32]);
-
-/*
- * Low-level x25519 function, defined by either the generic or cortex-m0
- * implementation. Must not be called directly.
- */
-void x25519_scalar_mult(uint8_t out[32],
-			const uint8_t scalar[32],
-			const uint8_t point[32]);
-
-#endif /* __CROS_EC_CURVE25519_H */
diff --git a/third_party/boringssl/test/x25519.c b/third_party/boringssl/test/x25519.c
deleted file mode 100644
index dac8795b63..0000000000
--- a/third_party/boringssl/test/x25519.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Copyright (c) 2015, Google Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
-
-#include "console.h"
-#include "common.h"
-#include "curve25519.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-#include "watchdog.h"
-
-/*
- * Define this to test 1 million iterations of x25519 (takes up to
- * a few minutes on host, up to a few days on microcontroller).
- */
-#undef TEST_X25519_1M_ITERATIONS
-
-static int test_x25519(void)
-{
-	/* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */
-	static const uint8_t scalar1[32] = {
-		0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d,
-		0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd,
-		0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18,
-		0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4,
-	};
-	static const uint8_t point1[32] = {
-		0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb,
-		0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c,
-		0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b,
-		0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c,
-	};
-	static const uint8_t expected1[32] = {
-		0xc3, 0xda, 0x55, 0x37, 0x9d, 0xe9, 0xc6, 0x90,
-		0x8e, 0x94, 0xea, 0x4d, 0xf2, 0x8d, 0x08, 0x4f,
-		0x32, 0xec, 0xcf, 0x03, 0x49, 0x1c, 0x71, 0xf7,
-		0x54, 0xb4, 0x07, 0x55, 0x77, 0xa2, 0x85, 0x52,
-	};
-	static const uint8_t scalar2[32] = {
-		0x4b, 0x66, 0xe9, 0xd4, 0xd1, 0xb4, 0x67, 0x3c,
-		0x5a, 0xd2, 0x26, 0x91, 0x95, 0x7d, 0x6a, 0xf5,
-		0xc1, 0x1b, 0x64, 0x21, 0xe0, 0xea, 0x01, 0xd4,
-		0x2c, 0xa4, 0x16, 0x9e, 0x79, 0x18, 0xba, 0x0d,
-	};
-	static const uint8_t point2[32] = {
-		0xe5, 0x21, 0x0f, 0x12, 0x78, 0x68, 0x11, 0xd3,
-		0xf4, 0xb7, 0x95, 0x9d, 0x05, 0x38, 0xae, 0x2c,
-		0x31, 0xdb, 0xe7, 0x10, 0x6f, 0xc0, 0x3c, 0x3e,
-		0xfc, 0x4c, 0xd5, 0x49, 0xc7, 0x15, 0xa4, 0x93,
-	};
-	static const uint8_t expected2[32] = {
-		0x95, 0xcb, 0xde, 0x94, 0x76, 0xe8, 0x90, 0x7d,
-		0x7a, 0xad, 0xe4, 0x5c, 0xb4, 0xb8, 0x73, 0xf8,
-		0x8b, 0x59, 0x5a, 0x68, 0x79, 0x9f, 0xa1, 0x52,
-		0xe6, 0xf8, 0xf7, 0x64, 0x7a, 0xac, 0x79, 0x57,
-	};
-	uint8_t out[32];
-
-	X25519(out, scalar1, point1);
-
-	if (memcmp(expected1, out, sizeof(out)) != 0) {
-		ccprintf("X25519 test one failed.\n");
-		return 0;
-	}
-
-
-	X25519(out, scalar2, point2);
-
-	if (memcmp(expected2, out, sizeof(out)) != 0) {
-		ccprintf("X25519 test two failed.\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-static int test_x25519_small_order(void)
-{
-	static const uint8_t kSmallOrderPoint[32] = {
-		0xe0, 0xeb, 0x7a, 0x7c, 0x3b, 0x41, 0xb8, 0xae,
-		0x16, 0x56, 0xe3, 0xfa, 0xf1, 0x9f, 0xc4, 0x6a,
-		0xda, 0x09, 0x8d, 0xeb, 0x9c, 0x32, 0xb1, 0xfd,
-		0x86, 0x62, 0x05, 0x16, 0x5f, 0x49, 0xb8,
-	};
-	uint8_t out[32], private_key[32];
-
-	memset(private_key, 0x11, sizeof(private_key));
-
-	if (X25519(out, private_key, kSmallOrderPoint)) {
-		ccprintf("X25519 returned success with a small-order input.\n");
-		return 0;
-	}
-
-	return 1;
-}
-
-static int test_x25519_iterated(void)
-{
-	/* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */
-	static const uint8_t expected_1K[32] = {
-		0x68, 0x4c, 0xf5, 0x9b, 0xa8, 0x33, 0x09, 0x55,
-		0x28, 0x00, 0xef, 0x56, 0x6f, 0x2f, 0x4d, 0x3c,
-		0x1c, 0x38, 0x87, 0xc4, 0x93, 0x60, 0xe3, 0x87,
-		0x5f, 0x2e, 0xb9, 0x4d, 0x99, 0x53, 0x2c, 0x51,
-	};
-#ifdef TEST_X25519_1M_ITERATIONS
-	static const uint8_t expected_1M[32] = {
-		0x7c, 0x39, 0x11, 0xe0, 0xab, 0x25, 0x86, 0xfd,
-		0x86, 0x44, 0x97, 0x29, 0x7e, 0x57, 0x5e, 0x6f,
-		0x3b, 0xc6, 0x01, 0xc0, 0x88, 0x3c, 0x30, 0xdf,
-		0x5f, 0x4d, 0xd2, 0xd2, 0x4f, 0x66, 0x54, 0x24
-	};
-#endif
-	uint8_t scalar[32] = {9}, point[32] = {9}, out[32];
-	unsigned i;
-
-	for (i = 0; i < 1000; i++) {
-		watchdog_reload();
-		X25519(out, scalar, point);
-		memcpy(point, scalar, sizeof(point));
-		memcpy(scalar, out, sizeof(scalar));
-	}
-
-	if (memcmp(expected_1K, scalar, sizeof(expected_1K)) != 0) {
-		ccprintf("1,000 iterations X25519 test failed\n");
-		return 0;
-	}
-
-#ifdef TEST_X25519_1M_ITERATIONS
-	for (; i < 1000000; i++) {
-		watchdog_reload();
-		X25519(out, scalar, point);
-		memcpy(point, scalar, sizeof(point));
-		memcpy(scalar, out, sizeof(scalar));
-		if ((i % 10000) == 0)
-			ccprints("%d", i);
-	}
-
-	if (memcmp(expected_1M, scalar, sizeof(expected_1M)) != 0) {
-		ccprintf("1,000,000 iterations X25519 test failed\n");
-		return 0;
-	}
-#endif
-
-	return 1;
-}
-
-static void test_x25519_speed(void)
-{
-	static const uint8_t scalar1[32] = {
-		0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d,
-		0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd,
-		0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18,
-		0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4,
-	};
-	static const uint8_t point1[32] = {
-		0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb,
-		0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c,
-		0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b,
-		0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c,
-	};
-	uint8_t out[32];
-	timestamp_t t0, t1;
-
-	X25519(out, scalar1, point1);
-	t0 = get_time();
-	X25519(out, scalar1, point1);
-	t1 = get_time();
-	ccprintf("X25519 duration %lld us\n", (long long)(t1.val - t0.val));
-}
-
-void run_test(int argc, char **argv)
-{
-	watchdog_reload();
-	/* do not check speed, just as a benchmark */
-	test_x25519_speed();
-
-	watchdog_reload();
-	if (!test_x25519() || !test_x25519_iterated() ||
-	    !test_x25519_small_order()) {
-		test_fail();
-		return;
-	}
-
-	test_pass();
-}
diff --git a/third_party/incbin/.travis.yml b/third_party/incbin/.travis.yml
deleted file mode 100644
index 4337da6e67..0000000000
--- a/third_party/incbin/.travis.yml
+++ /dev/null
@@ -1,12 +0,0 @@
-language: c
-
-os:
-- linux
-- osx
-
-compiler:
-- gcc
-- clang
-
-script:
-- make -C test test
diff --git a/third_party/incbin/README.md b/third_party/incbin/README.md
deleted file mode 100644
index da32103e9e..0000000000
--- a/third_party/incbin/README.md
+++ /dev/null
@@ -1,174 +0,0 @@
-# incbin
-
-Include binary files in your C/C++ applications with ease
-
-## Example
-
-```c
-    #include "incbin.h"
-
-    INCBIN(Icon, "icon.png");
-
-    // This translation unit now has three symbols
-    // const unsigned char gIconData[];
-    // const unsigned char *const gIconEnd; // a marker to the end, take the address to get the ending pointer
-    // const unsigned int gIconSize;
-
-    // Reference in other translation units like this
-    INCBIN_EXTERN(Icon);
-
-    // This translation unit now has three extern symbols
-    // Use `extern "C"` in case of writing C++ code
-    // extern const unsigned char gIconData[];
-    // extern const unsigned char *const gIconEnd; // a marker to the end, take the address to get the ending pointer
-    // extern const unsigned int gIconSize;
-```
-
-## Portability
-
-Known to work on the following compilers
-
-*   GCC
-*   Clang
-*   PathScale
-*   Intel
-*   Solaris & Sun Studio
-*   Green Hills
-*   SNC (ProDG)
-*   Diab C++ (WindRiver)
-*   XCode
-*   ArmCC
-*   RealView
-*   ImageCraft
-*   Stratus VOS C
-*   TinyCC
-*   cparser & libfirm
-*   LCC
-*   MSVC _See MSVC below_
-
-If your compiler is not listed, as long as it supports GCC inline assembler,
-this should work.
-
-## MISRA
-
-INCBIN can be used in MISRA C setting. However it should be independently
-checked due to its use of inline assembly to achieve what it does. Independent
-verification of the header has been done several times based on commit:
-7e327a28ba5467c4202ec37874beca7084e4b08c
-
-## Alignment
-
-The data included by this tool will be aligned on the architectures word
-boundary unless some variant of SIMD is detected, then it's aligned on a byte
-boundary that respects SIMD convention just in case your binary data may be used
-in vectorized code. The table of the alignments for SIMD this header recognizes
-is as follows:
-
-SIMD                                   | Alignment
--------------------------------------- | ---------
-SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 | 16
-Neon                                   | 16
-AVX, AVX2                              | 32
-AVX512                                 | 64
-
-## Prefix
-
-By default, `incbin.h` emits symbols with a `g` prefix. This can be adjusted by
-defining `INCBIN_PREFIX` before including `incbin.h` with a desired prefix. For
-instance
-
-```c
-    #define INCBIN_PREFIX g_
-    #include "incbin.h"
-    INCBIN(test, "test.txt");
-
-    // This translation unit now has three symbols
-    // const unsigned char g_testData[];
-    // const unsigned char *const g_testEnd;
-    // const unsigned int g_testSize;
-```
-
-You can also choose to have no prefix by defining the prefix with nothing, for
-example:
-
-```c
-    #define INCBIN_PREFIX
-    #include "incbin.h"
-    INCBIN(test, "test.txt");
-
-    // This translation unit now has three symbols
-    // const unsigned char testData[];
-    // const unsigned char *const testEnd;
-    // const unsigned int testSize;
-```
-
-## Style
-
-By default, `incbin.h` emits symbols with `CamelCase` style. This can be
-adjusted by defining `INCBIN_STYLE` before including `incbin.h` to change the
-style. There are two possible styles to choose from
-
-*   INCBIN_STYLE_CAMEL (CamelCase)
-*   INCBIN_STYLE_SNAKE (snake_case)
-
-For instance:
-
-```c
-    #define INCBIN_STYLE INCBIN_STYLE_SNAKE
-    #include "incbin.h"
-    INCBIN(test, "test.txt");
-
-    // This translation unit now has three symbols
-    // const unsigned char gtest_data[];
-    // const unsigned char *const gtest_end;
-    // const unsigned int gtest_size;
-```
-
-Combining both the style and prefix allows for you to adjust `incbin.h` to suite
-your existing style and practices.
-
-## Overriding Linker Output section
-
-By default, `incbin.h` emits into the read-only linker output section used on
-the detected platform. If you need to override this for whatever reason, you can
-manually specify the linker output section.
-
-For example, to emit data into program memory for
-[esp8266/Arduino](github.com/esp8266/Arduino):
-
-```c
-#define INCBIN_OUTPUT_SECTION ".irom.text"
-#include "incbin.h"
-INCBIN(Foo, "foo.txt");
-// Data is emitted into program memory that never gets copied to RAM
-```
-
-## Explanation
-
-`INCBIN` is a macro which uses the inline assembler provided by almost all
-compilers to include binary files. It achieves this by utilizing the `.incbin`
-directive of the inline assembler. It then uses the assembler to calculate the
-size of the included binary and exports two global symbols that can be
-externally referenced in other translation units which contain the data and size
-of the included binary data respectively.
-
-## MSVC
-
-Supporting MSVC is slightly harder as MSVC lacks an inline assembler which can
-include data. To support this we ship a tool which can process source files
-containing `INCBIN` macro usage and generate an external source file containing
-the data of all of them combined. This file is named `data.c` by default. Just
-include it into your build and use the `incbin.h` to reference data as needed.
-It's suggested you integrate this tool as part of your projects's pre-build
-events so that this can be automated. A more comprehensive list of options for
-this tool can be viewed by invoking the tool with `-help`
-
-If you're using a custom prefix, be sure to specify the prefix on the command
-line with `-p <prefix>` so that everything matches up; similarly, if you're
-using a custom style, be sure to specify the style on the command line with `-S
-<style>` as well.
-
-## Miscellaneous
-
-Documentation for the API is provided by the header using Doxygen notation. For
-licensing information see UNLICENSE.
diff --git a/third_party/incbin/UNLICENSE b/third_party/incbin/UNLICENSE
deleted file mode 100644
index 68a49daad8..0000000000
--- a/third_party/incbin/UNLICENSE
+++ /dev/null
@@ -1,24 +0,0 @@
-This is free and unencumbered software released into the public domain.
-
-Anyone is free to copy, modify, publish, use, compile, sell, or
-distribute this software, either in source code form or as a compiled
-binary, for any purpose, commercial or non-commercial, and by any
-means.
-
-In jurisdictions that recognize copyright laws, the author or authors
-of this software dedicate any and all copyright interest in the
-software to the public domain. We make this dedication for the benefit
-of the public at large and to the detriment of our heirs and
-successors. We intend this dedication to be an overt act of
-relinquishment in perpetuity of all present and future rights to this
-software under copyright law.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-OTHER DEALINGS IN THE SOFTWARE.
-
-For more information, please refer to <http://unlicense.org/>
diff --git a/third_party/incbin/incbin.c b/third_party/incbin/incbin.c
deleted file mode 100644
index 4d4f64c9bf..0000000000
--- a/third_party/incbin/incbin.c
+++ /dev/null
@@ -1,289 +0,0 @@
-#ifdef _MSC_VER
-#  define _CRT_SECURE_NO_WARNINGS
-#endif
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <ctype.h>
-#include <limits.h>
-
-#ifndef PATH_MAX
-#  define PATH_MAX 260
-#endif
-
-#define SEARCH_PATHS_MAX 64
-#define FILE_PATHS_MAX 1024
-
-static int fline(char **line, size_t *n, FILE *fp) {
-    int chr;
-    char *pos;
-    if (!line || !n || !fp)
-        return -1;
-    if (!*line)
-        if (!(*line = (char *)malloc((*n=64))))
-            return -1;
-    chr = *n;
-    pos = *line;
-    for (;;) {
-        int c = fgetc(fp);
-        if (chr < 2) {
-            *n += (*n > 16) ? *n : 64;
-            chr = *n + *line - pos;
-            if (!(*line = (char *)realloc(*line,*n)))
-                return -1;
-            pos = *n - chr + *line;
-        }
-        if (ferror(fp))
-            return -1;
-        if (c == EOF) {
-            if (pos == *line)
-                return -1;
-            else
-                break;
-        }
-        *pos++ = c;
-        chr--;
-        if (c == '\n')
-            break;
-    }
-    *pos = '\0';
-    return pos - *line;
-}
-
-static FILE *open_file(const char *name, const char *mode, const char (*searches)[PATH_MAX], int count) {
-    int i;
-    for (i = 0; i < count; i++) {
-        char buffer[FILENAME_MAX + PATH_MAX];
-        FILE *fp;
-#ifndef _MSC_VER
-        snprintf(buffer, sizeof(buffer), "%s/%s", searches[i], name);
-#else
-        _snprintf(buffer, sizeof(buffer), "%s/%s", searches[i], name);
-#endif
-        if ((fp = fopen(buffer, mode)))
-            return fp;
-    }
-    return !count ? fopen(name, mode) : NULL;
-}
-
-static int strcicmp(const char *s1, const char *s2) {
-    const unsigned char *us1 = (const unsigned char *)s1,
-                        *us2 = (const unsigned char *)s2;
-    while (tolower(*us1) == tolower(*us2)) {
-        if (*us1++ == '\0')
-            return 0;
-        us2++;
-    }
-    return tolower(*us1) - tolower(*us2);
-}
-
-/* styles */
-enum { kCamel, kSnake };
-/* identifiers */
-enum { kData, kEnd, kSize };
-
-static const char *styled(int style, int ident) {
-    switch (style) {
-    case kCamel:
-        switch (ident) {
-        case kData: return "Data";
-        case kEnd: return "End";
-        case kSize: return "Size";
-        }
-        break;
-    case kSnake:
-        switch (ident) {
-        case kData: return "_data";
-        case kEnd: return "_end";
-        case kSize: return "_size";
-        }
-        break;
-    }
-}
-
-int main(int argc, char **argv) {
-    int ret, i, paths, files = 0, style = kCamel;
-    char outfile[FILENAME_MAX] = "data.c";
-    char search_paths[SEARCH_PATHS_MAX][PATH_MAX];
-    char prefix[FILENAME_MAX] = "g";
-    char file_paths[FILE_PATHS_MAX][PATH_MAX];
-    FILE *out = NULL;
-
-    argc--;
-    argv++;
-
-    #define s(IDENT) styled(style, IDENT)
-
-    if (argc == 0) {
-usage:
-        fprintf(stderr, "%s [-help] [-Ipath...] | <files> | [-o output] | [-p prefix]\n", argv[-1]);
-        fprintf(stderr, "   -o         - output file [default is \"data.c\"]\n");
-        fprintf(stderr, "   -p         - specify a prefix for symbol names (default is \"g\")\n");
-        fprintf(stderr, "   -S<style>  - specify a style for symbol generation (default is \"camelcase\")\n");
-        fprintf(stderr, "   -I<path>   - specify an include path for the tool to use\n");
-        fprintf(stderr, "   -help      - this\n");
-        fprintf(stderr, "example:\n");
-        fprintf(stderr, "   %s icon.png music.mp3 -o file.c\n", argv[-1]);
-        fprintf(stderr, "styles (for -S):\n");
-        fprintf(stderr, "   camelcase\n");
-        fprintf(stderr, "   snakecase\n");
-        return 1;
-    }
-
-    for (i = 0, paths = 0; i < argc; i++) {
-        if (!strcmp(argv[i], "-o")) {
-            if (i + 1 < argc) {
-                strcpy(outfile, argv[i + 1]);
-                memmove(argv+i+1, argv+i+2, (argc-i-2) * sizeof *argv);
-                argc--;
-                continue;
-            }
-        } else if (!strcmp(argv[i], "-p")) {
-            /* supports "-p" with no prefix as well as
-             * "-p -" which is another way of saying "no prefix"
-             * and "-p <prefix>" for an actual prefix.
-             */
-            if (argv[i+1][0] == '-') {
-                prefix[0] = '\0';
-                /* is it just a -? */
-                if (i + 1 < argc && !strcmp(argv[i+1], "-")) {
-                    memmove(argv+i+1, argv+i+2, (argc-i-2) * sizeof *argv);
-                    argc--;
-                }
-                continue;
-            }
-            strcpy(prefix, argv[i + 1]);
-            memmove(argv+i+1, argv+i+2, (argc-i-2) * sizeof *argv);
-            argc--;
-            continue;
-        } else if (!strncmp(argv[i], "-I", 2)) {
-            char *name = argv[i] + 2; /* skip "-I"; */
-            if (paths >= SEARCH_PATHS_MAX) {
-                fprintf(stderr, "maximum search paths exceeded\n");
-                return 1;
-            }
-            strcpy(search_paths[paths++], name);
-            continue;
-        } else if (!strncmp(argv[i], "-S", 2)) {
-            char *name = argv[i] + 2; /* skip "-S"; */
-            if (!strcicmp(name, "camel") || !strcicmp(name, "camelcase"))
-                style = kCamel;
-            else if (!strcicmp(name, "snake") || !strcicmp(name, "snakecase"))
-                style = kSnake;
-            else
-                goto usage;
-            continue;
-        } else if (!strcmp(argv[i], "-help")) {
-            goto usage;
-        } else {
-            if (files >= sizeof file_paths / sizeof *file_paths) {
-                fprintf(stderr, "maximum file paths exceeded\n");
-                return 1;
-            }
-            strcpy(file_paths[files++], argv[i]);
-        }
-    }
-
-    if (!(out = fopen(outfile, "w"))) {
-        fprintf(stderr, "failed to open `%s' for output\n", outfile);
-        return 1;
-    }
-
-    fprintf(out, "/* File automatically generated by incbin */\n");
-    /* Be sure to define the prefix if we're not using the default */
-    if (strcmp(prefix, "g"))
-        fprintf(out, "#define INCBIN_PREFIX %s\n", prefix);
-    if (style != 0)
-        fprintf(out, "#define INCBIN_STYLE INCBIN_STYLE_SNAKE\n");
-    fprintf(out, "#include \"incbin.h\"\n\n");
-    fprintf(out, "#ifdef __cplusplus\n");
-    fprintf(out, "extern \"C\" {\n");
-    fprintf(out, "#endif\n\n");
-
-    for (i = 0; i < files; i++) {
-        FILE *fp = open_file(file_paths[i], "r", search_paths, paths);
-        char *line = NULL;
-        size_t size = 0;
-        if (!fp) {
-            fprintf(stderr, "failed to open `%s' for reading\n", file_paths[i]);
-            fclose(out);
-            return 1;
-        }
-        while (fline(&line, &size, fp) != -1) {
-            char *inc, *beg, *sep, *end, *name, *file;
-            FILE *f;
-            if (!(inc = strstr(line, "INCBIN"))) continue;
-            if (!(beg = strchr(inc, '(')))       continue;
-            if (!(sep = strchr(beg, ',')))       continue;
-            if (!(end = strchr(sep, ')')))       continue;
-            name = beg + 1;
-            file = sep + 1;
-            while (isspace(*name)) name++;
-            while (isspace(*file)) file++;
-            sep--;
-            while (isspace(*sep)) sep--;
-            *++sep = '\0';
-            end--;
-            while (isspace(*end)) end--;
-            *++end = '\0';
-            fprintf(out, "/* INCBIN(%s, %s); */\n", name, file);
-            fprintf(out, "INCBIN_CONST INCBIN_ALIGN unsigned char %s%s%s[] = {\n    ", prefix, name, s(kData));
-            *--end = '\0';
-            file++;
-            if (!(f = open_file(file, "rb", search_paths, paths))) {
-                fprintf(stderr, "failed to include data `%s'\n", file);
-                goto end;
-            } else {
-                long size, i;
-                unsigned char *data, count = 0;
-                fseek(f, 0, SEEK_END);
-                size = ftell(f);
-                fseek(f, 0, SEEK_SET);
-                if (!(data = (unsigned char *)malloc(size))) {
-                    fprintf(stderr, "out of memory\n");
-                    fclose(f);
-                    ret = 1;
-                    goto end;
-                }
-                if (fread(data, size, 1, f) != 1) {
-                    fprintf(stderr, "failed reading include data `%s'\n", file);
-                    free(data);
-                    fclose(f);
-                    ret = 1;
-                    goto end;
-                }
-                for (i = 0; i < size; i++) {
-                    if (count == 12) {
-                        fprintf(out, "\n    ");
-                        count = 0;
-                    }
-                    fprintf(out, i != size - 1 ? "0x%02X, " : "0x%02X", data[i]);
-                    count++;
-                }
-                free(data);
-                fclose(f);
-            }
-            fprintf(out, "\n};\n");
-            fprintf(out, "INCBIN_CONST INCBIN_ALIGN unsigned char *const %s%s%s = %s%s%s + sizeof(%s%s%s);\n", prefix, name, s(kEnd), prefix, name, s(kData), prefix, name, s(kData));
-            fprintf(out, "INCBIN_CONST unsigned int %s%s%s = sizeof(%s%s%s);\n", prefix, name, s(kSize), prefix, name, s(kData));
-        }
-end:
-        free(line);
-        fclose(fp);
-        printf("included `%s'\n", file_paths[i]);
-    }
-
-    if (ret == 0) {
-        fprintf(out, "\n#ifdef __cplusplus\n");
-        fprintf(out, "}\n");
-        fprintf(out, "#endif\n");
-        fclose(out);
-        printf("generated `%s'\n", outfile);
-        return 0;
-    }
-
-    fclose(out);
-    remove(outfile);
-    return 1;
-}
diff --git a/third_party/incbin/incbin.h b/third_party/incbin/incbin.h
deleted file mode 100644
index c19684d724..0000000000
--- a/third_party/incbin/incbin.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/**
- * @file incbin.h
- * @author Dale Weiler
- * @brief Utility for including binary files
- *
- * Facilities for including binary files into the current translation unit and
- * making use from them externally in other translation units.
- */
-#ifndef INCBIN_HDR
-#define INCBIN_HDR
-#include <limits.h>
-#if   defined(__AVX512BW__) || \
-      defined(__AVX512CD__) || \
-      defined(__AVX512DQ__) || \
-      defined(__AVX512ER__) || \
-      defined(__AVX512PF__) || \
-      defined(__AVX512VL__) || \
-      defined(__AVX512F__)
-# define INCBIN_ALIGNMENT_INDEX 6
-#elif defined(__AVX__)      || \
-      defined(__AVX2__)
-# define INCBIN_ALIGNMENT_INDEX 5
-#elif defined(__SSE__)      || \
-      defined(__SSE2__)     || \
-      defined(__SSE3__)     || \
-      defined(__SSSE3__)    || \
-      defined(__SSE4_1__)   || \
-      defined(__SSE4_2__)   || \
-      defined(__neon__)
-# define INCBIN_ALIGNMENT_INDEX 4
-#elif ULONG_MAX != 0xffffffffu
-# define INCBIN_ALIGNMENT_INDEX 3
-# else
-# define INCBIN_ALIGNMENT_INDEX 2
-#endif
-
-/* Lookup table of (1 << n) where `n' is `INCBIN_ALIGNMENT_INDEX' */
-#define INCBIN_ALIGN_SHIFT_0 1
-#define INCBIN_ALIGN_SHIFT_1 2
-#define INCBIN_ALIGN_SHIFT_2 4
-#define INCBIN_ALIGN_SHIFT_3 8
-#define INCBIN_ALIGN_SHIFT_4 16
-#define INCBIN_ALIGN_SHIFT_5 32
-#define INCBIN_ALIGN_SHIFT_6 64
-
-/* Actual alignment value */
-#define INCBIN_ALIGNMENT \
-    INCBIN_CONCATENATE( \
-        INCBIN_CONCATENATE(INCBIN_ALIGN_SHIFT, _), \
-        INCBIN_ALIGNMENT_INDEX)
-
-/* Stringize */
-#define INCBIN_STR(X) \
-    #X
-#define INCBIN_STRINGIZE(X) \
-    INCBIN_STR(X)
-/* Concatenate */
-#define INCBIN_CAT(X, Y) \
-    X ## Y
-#define INCBIN_CONCATENATE(X, Y) \
-    INCBIN_CAT(X, Y)
-/* Deferred macro expansion */
-#define INCBIN_EVAL(X) \
-    X
-#define INCBIN_INVOKE(N, ...) \
-    INCBIN_EVAL(N(__VA_ARGS__))
-
-/* Green Hills uses a different directive for including binary data */
-#if defined(__ghs__)
-#  if (__ghs_asm == 2)
-#    define INCBIN_MACRO ".file"
-/* Or consider the ".myrawdata" entry in the ld file */
-#  else
-#    define INCBIN_MACRO "\tINCBIN"
-#  endif
-#else
-#  define INCBIN_MACRO ".incbin"
-#endif
-
-#ifndef _MSC_VER
-#  define INCBIN_ALIGN \
-    __attribute__((aligned(INCBIN_ALIGNMENT)))
-#else
-#  define INCBIN_ALIGN __declspec(align(INCBIN_ALIGNMENT))
-#endif
-
-#if defined(__arm__) || /* GNU C and RealView */ \
-    defined(__arm) || /* Diab */ \
-    defined(_ARM) /* ImageCraft */
-#  define INCBIN_ARM
-#endif
-
-#ifdef __GNUC__
-/* Utilize .balign where supported */
-#  define INCBIN_ALIGN_HOST ".balign " INCBIN_STRINGIZE(INCBIN_ALIGNMENT) "\n"
-#  define INCBIN_ALIGN_BYTE ".balign 1\n"
-#elif defined(INCBIN_ARM)
-/*
- * On arm assemblers, the alignment value is calculated as (1 << n) where `n' is
- * the shift count. This is the value passed to `.align'
- */
-#  define INCBIN_ALIGN_HOST ".align " INCBIN_STRINGIZE(INCBIN_ALIGNMENT_INDEX) "\n"
-#  define INCBIN_ALIGN_BYTE ".align 0\n"
-#else
-/* We assume other inline assembler's treat `.align' as `.balign' */
-#  define INCBIN_ALIGN_HOST ".align " INCBIN_STRINGIZE(INCBIN_ALIGNMENT) "\n"
-#  define INCBIN_ALIGN_BYTE ".align 1\n"
-#endif
-
-/* INCBIN_CONST is used by incbin.c generated files */
-#if defined(__cplusplus)
-#  define INCBIN_EXTERNAL extern "C"
-#  define INCBIN_CONST    extern const
-#else
-#  define INCBIN_EXTERNAL extern
-#  define INCBIN_CONST    const
-#endif
-
-/**
- * @brief Optionally override the linker section into which data is emitted.
- *
- * @warning If you use this facility, you'll have to deal with platform-specific linker output
- * section naming on your own
- *
- * Overriding the default linker output section, e.g for esp8266/Arduino:
- * @code
- * #define INCBIN_OUTPUT_SECTION ".irom.text"
- * #include "incbin.h"
- * INCBIN(Foo, "foo.txt");
- * // Data is emitted into program memory that never gets copied to RAM
- * @endcode
- */
-#if !defined(INCBIN_OUTPUT_SECTION)
-#  if defined(__APPLE__)
-#    define INCBIN_OUTPUT_SECTION         ".const_data"
-#  else
-#    define INCBIN_OUTPUT_SECTION         ".rodata"
-#  endif
-#endif
-
-#if defined(__APPLE__)
-/* The directives are different for Apple branded compilers */
-#  define INCBIN_SECTION         INCBIN_OUTPUT_SECTION "\n"
-#  define INCBIN_GLOBAL(NAME)    ".globl " INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME "\n"
-#  define INCBIN_INT             ".long "
-#  define INCBIN_MANGLE          "_"
-#  define INCBIN_BYTE            ".byte "
-#  define INCBIN_TYPE(...)
-#else
-#  define INCBIN_SECTION         ".section " INCBIN_OUTPUT_SECTION "\n"
-#  define INCBIN_GLOBAL(NAME)    ".global " INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME "\n"
-#  if defined(__ghs__)
-#    define INCBIN_INT           ".word "
-#  else
-#    define INCBIN_INT           ".int "
-#  endif
-#  if defined(__USER_LABEL_PREFIX__)
-#    define INCBIN_MANGLE        INCBIN_STRINGIZE(__USER_LABEL_PREFIX__)
-#  else
-#    define INCBIN_MANGLE        ""
-#  endif
-#  if defined(INCBIN_ARM)
-/* On arm assemblers, `@' is used as a line comment token */
-#    define INCBIN_TYPE(NAME)    ".type " INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME ", %object\n"
-#  elif defined(__MINGW32__) || defined(__MINGW64__)
-/* Mingw doesn't support this directive either */
-#    define INCBIN_TYPE(NAME)
-#  else
-/* It's safe to use `@' on other architectures */
-#    define INCBIN_TYPE(NAME)    ".type " INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME ", @object\n"
-#  endif
-#  define INCBIN_BYTE            ".byte "
-#endif
-
-/* List of style types used for symbol names */
-#define INCBIN_STYLE_CAMEL 0
-#define INCBIN_STYLE_SNAKE 1
-
-/**
- * @brief Specify the prefix to use for symbol names.
- *
- * By default this is `g', producing symbols of the form:
- * @code
- * #include "incbin.h"
- * INCBIN(Foo, "foo.txt");
- *
- * // Now you have the following symbols:
- * // const unsigned char gFooData[];
- * // const unsigned char *const gFooEnd;
- * // const unsigned int gFooSize;
- * @endcode
- *
- * If however you specify a prefix before including: e.g:
- * @code
- * #define INCBIN_PREFIX incbin
- * #include "incbin.h"
- * INCBIN(Foo, "foo.txt");
- *
- * // Now you have the following symbols instead:
- * // const unsigned char incbinFooData[];
- * // const unsigned char *const incbinFooEnd;
- * // const unsigned int incbinFooSize;
- * @endcode
- */
-#if !defined(INCBIN_PREFIX)
-#  define INCBIN_PREFIX g
-#endif
-
-/**
- * @brief Specify the style used for symbol names.
- *
- * Possible options are
- * - INCBIN_STYLE_CAMEL "CamelCase"
- * - INCBIN_STYLE_SNAKE "snake_case"
- *
- * Default option is *INCBIN_STYLE_CAMEL* producing symbols of the form:
- * @code
- * #include "incbin.h"
- * INCBIN(Foo, "foo.txt");
- *
- * // Now you have the following symbols:
- * // const unsigned char <prefix>FooData[];
- * // const unsigned char *const <prefix>FooEnd;
- * // const unsigned int <prefix>FooSize;
- * @endcode
- *
- * If however you specify a style before including: e.g:
- * @code
- * #define INCBIN_STYLE INCBIN_STYLE_SNAKE
- * #include "incbin.h"
- * INCBIN(foo, "foo.txt");
- *
- * // Now you have the following symbols:
- * // const unsigned char <prefix>foo_data[];
- * // const unsigned char *const <prefix>foo_end;
- * // const unsigned int <prefix>foo_size;
- * @endcode
- */
-#if !defined(INCBIN_STYLE)
-#  define INCBIN_STYLE INCBIN_STYLE_CAMEL
-#endif
-
-/* Style lookup tables */
-#define INCBIN_STYLE_0_DATA Data
-#define INCBIN_STYLE_0_END End
-#define INCBIN_STYLE_0_SIZE Size
-#define INCBIN_STYLE_1_DATA _data
-#define INCBIN_STYLE_1_END _end
-#define INCBIN_STYLE_1_SIZE _size
-
-/* Style lookup: returning identifier */
-#define INCBIN_STYLE_IDENT(TYPE) \
-    INCBIN_CONCATENATE( \
-        INCBIN_STYLE_, \
-        INCBIN_CONCATENATE( \
-            INCBIN_EVAL(INCBIN_STYLE), \
-            INCBIN_CONCATENATE(_, TYPE)))
-
-/* Style lookup: returning string literal */
-#define INCBIN_STYLE_STRING(TYPE) \
-    INCBIN_STRINGIZE( \
-        INCBIN_STYLE_IDENT(TYPE)) \
-
-/* Generate the global labels by indirectly invoking the macro with our style
- * type and concatenating the name against them. */
-#define INCBIN_GLOBAL_LABELS(NAME, TYPE) \
-    INCBIN_INVOKE( \
-        INCBIN_GLOBAL, \
-        INCBIN_CONCATENATE( \
-            NAME, \
-            INCBIN_INVOKE( \
-                INCBIN_STYLE_IDENT, \
-                TYPE))) \
-    INCBIN_INVOKE( \
-        INCBIN_TYPE, \
-        INCBIN_CONCATENATE( \
-            NAME, \
-            INCBIN_INVOKE( \
-                INCBIN_STYLE_IDENT, \
-                TYPE)))
-
-/**
- * @brief Externally reference binary data included in another translation unit.
- *
- * Produces three external symbols that reference the binary data included in
- * another translation unit.
- *
- * The symbol names are a concatenation of `INCBIN_PREFIX' before *NAME*; with
- * "Data", as well as "End" and "Size" after. An example is provided below.
- *
- * @param NAME The name given for the binary data
- *
- * @code
- * INCBIN_EXTERN(Foo);
- *
- * // Now you have the following symbols:
- * // extern const unsigned char <prefix>FooData[];
- * // extern const unsigned char *const <prefix>FooEnd;
- * // extern const unsigned int <prefix>FooSize;
- * @endcode
- */
-#define INCBIN_EXTERN(NAME) \
-    INCBIN_EXTERNAL const INCBIN_ALIGN unsigned char \
-        INCBIN_CONCATENATE( \
-            INCBIN_CONCATENATE(INCBIN_PREFIX, NAME), \
-            INCBIN_STYLE_IDENT(DATA))[]; \
-    INCBIN_EXTERNAL const INCBIN_ALIGN unsigned char *const \
-    INCBIN_CONCATENATE( \
-        INCBIN_CONCATENATE(INCBIN_PREFIX, NAME), \
-        INCBIN_STYLE_IDENT(END)); \
-    INCBIN_EXTERNAL const unsigned int \
-        INCBIN_CONCATENATE( \
-            INCBIN_CONCATENATE(INCBIN_PREFIX, NAME), \
-            INCBIN_STYLE_IDENT(SIZE))
-
-/**
- * @brief Include a binary file into the current translation unit.
- *
- * Includes a binary file into the current translation unit, producing three symbols
- * for objects that encode the data and size respectively.
- *
- * The symbol names are a concatenation of `INCBIN_PREFIX' before *NAME*; with
- * "Data", as well as "End" and "Size" after. An example is provided below.
- *
- * @param NAME The name to associate with this binary data (as an identifier.)
- * @param FILENAME The file to include (as a string literal.)
- *
- * @code
- * INCBIN(Icon, "icon.png");
- *
- * // Now you have the following symbols:
- * // const unsigned char <prefix>IconData[];
- * // const unsigned char *const <prefix>IconEnd;
- * // const unsigned int <prefix>IconSize;
- * @endcode
- *
- * @warning This must be used in global scope
- * @warning The identifiers may be different if INCBIN_STYLE is not default
- *
- * To externally reference the data included by this in another translation unit
- * please @see INCBIN_EXTERN.
- */
-#ifdef _MSC_VER
-#define INCBIN(NAME, FILENAME) \
-    INCBIN_EXTERN(NAME)
-#else
-#define INCBIN(NAME, FILENAME) \
-    __asm__(INCBIN_SECTION \
-            INCBIN_GLOBAL_LABELS(NAME, DATA) \
-            INCBIN_ALIGN_HOST \
-            INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME INCBIN_STYLE_STRING(DATA) ":\n" \
-            INCBIN_MACRO " \"" FILENAME "\"\n" \
-            INCBIN_GLOBAL_LABELS(NAME, END) \
-            INCBIN_ALIGN_BYTE \
-            INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME INCBIN_STYLE_STRING(END) ":\n" \
-                INCBIN_BYTE "1\n" \
-            INCBIN_GLOBAL_LABELS(NAME, SIZE) \
-            INCBIN_ALIGN_HOST \
-            INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME INCBIN_STYLE_STRING(SIZE) ":\n" \
-                INCBIN_INT INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME INCBIN_STYLE_STRING(END) " - " \
-                           INCBIN_MANGLE INCBIN_STRINGIZE(INCBIN_PREFIX) #NAME INCBIN_STYLE_STRING(DATA) "\n" \
-            INCBIN_ALIGN_HOST \
-            ".text\n" \
-    ); \
-    INCBIN_EXTERN(NAME)
-
-#endif
-#endif
diff --git a/third_party/incbin/test/.gitignore b/third_party/incbin/test/.gitignore
deleted file mode 100644
index 377c803c47..0000000000
--- a/third_party/incbin/test/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/asserts
diff --git a/third_party/incbin/test/Makefile b/third_party/incbin/test/Makefile
deleted file mode 100644
index aa31beca34..0000000000
--- a/third_party/incbin/test/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-test: asserts
-	./asserts
-
-asserts: asserts.c ../incbin.h
-	$(CC) -o asserts asserts.c
diff --git a/third_party/incbin/test/asserts.c b/third_party/incbin/test/asserts.c
deleted file mode 100644
index 9028a2ad1a..0000000000
--- a/third_party/incbin/test/asserts.c
+++ /dev/null
@@ -1,20 +0,0 @@
-#include <assert.h>
-#include <stdlib.h>
-#include "../incbin.h"
-
-INCBIN(Lorem, "loremipsum.txt");
-INCBIN(Onebyte, "onebyte.txt");
-INCBIN(Sevenbytes, "sevenbytes.txt");
-
-int main(int argc, char **argv)
-{
-	assert(gLoremSize==962);
-	assert(&gLoremData[gLoremSize] == (const unsigned char*) &gLoremEnd);
-
-	assert(gOnebyteSize == 1);
-	assert(&gOnebyteData[gOnebyteSize] == (const unsigned char*) &gOnebyteEnd);
-
-	assert(gSevenbytesSize==7);
-	assert(&gSevenbytesData[gSevenbytesSize] == (const unsigned char*) &gSevenbytesEnd);
-	exit(0);
-}
diff --git a/third_party/incbin/test/loremipsum.txt b/third_party/incbin/test/loremipsum.txt
deleted file mode 100644
index 424477fe2a..0000000000
--- a/third_party/incbin/test/loremipsum.txt
+++ /dev/null
@@ -1 +0,0 @@
-Lorem ipsum dolor sit amet, consectetur adipiscing elit. Donec a diam lectus. Sed sit amet ipsum mauris. Maecenas congue ligula ac quam viverra nec consectetur ante hendrerit. Donec et mollis dolor. Praesent et diam eget libero egestas mattis sit amet vitae augue. Nam tincidunt congue enim, ut porta lorem lacinia consectetur. Donec ut libero sed arcu vehicula ultricies a non tortor. Lorem ipsum dolor sit amet, consectetur adipiscing elit. Aenean ut gravida lorem. Ut turpis felis, pulvinar a semper sed, adipiscing id dolor. Pellentesque auctor nisi id magna consequat sagittis. Curabitur dapibus enim sit amet elit pharetra tincidunt feugiat nisl imperdiet. Ut convallis libero in urna ultrices accumsan. Donec sed odio eros. Donec viverra mi quis quam pulvinar at malesuada arcu rhoncus. Cum sociis natoque penatibus et magnis dis parturient montes, nascetur ridiculus mus. In rutrum accumsan ultricies. Mauris vitae nisi at sem facilisis semper ac in est.
\ No newline at end of file
diff --git a/third_party/incbin/test/onebyte.txt b/third_party/incbin/test/onebyte.txt
deleted file mode 100644
index 500c0709ca..0000000000
--- a/third_party/incbin/test/onebyte.txt
+++ /dev/null
@@ -1 +0,0 @@
-X
\ No newline at end of file
diff --git a/third_party/incbin/test/sevenbytes.txt b/third_party/incbin/test/sevenbytes.txt
deleted file mode 100644
index 462f61f1b1..0000000000
--- a/third_party/incbin/test/sevenbytes.txt
+++ /dev/null
@@ -1 +0,0 @@
-XXXXXXX
\ No newline at end of file
diff --git a/third_party/libaeabi-cortexm0/LICENSE b/third_party/libaeabi-cortexm0/LICENSE
deleted file mode 100644
index abb14b642c..0000000000
--- a/third_party/libaeabi-cortexm0/LICENSE
+++ /dev/null
@@ -1,13 +0,0 @@
-Licensed under the ISC licence (similar to the MIT/Expat license).
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
diff --git a/third_party/libaeabi-cortexm0/METADATA b/third_party/libaeabi-cortexm0/METADATA
deleted file mode 100644
index 02ac01504c..0000000000
--- a/third_party/libaeabi-cortexm0/METADATA
+++ /dev/null
@@ -1,17 +0,0 @@
-name: "libaeabi-cortexm0"
-description:
-    "ARM Run-Time ABI for the Cortex-M0 processor"
-
-third_party {
-  url {
-    type: GIT
-    value: "https://github.com/bobbl/libaeabi-cortexm0"
-  }
-  # TODO(crbug.com/884905): Refresh as needed from upstream
-  version: "<as of 2014>"
-  last_upgrade_date { year: 2014 month: 04 day: 01 }
-  license_type: NOTICE
-  local_modifications: "cortex-m0: See git log. "
-    "cortex-m: Adapted from cortex-m0 code. "
-    "Created LICENSE file."
-}
\ No newline at end of file
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S
deleted file mode 100644
index f3709af41a..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M
- * ldivmod.S: signed 64 bit division (quotient and remainder)
- *
- * Copyright (c) 2012 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-
-
-	.syntax unified
-	.text
-	.code 16
-
-
-@ {long long quotient, long long remainder}
-@ __aeabi_ldivmod(long long numerator, long long denominator)
-@
-@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder in
-@ r3:r2 (all signed)
-@
-	.thumb_func
-	.section .text.__aeabi_ldivmod
-        .global __aeabi_ldivmod
-__aeabi_ldivmod:
-
-	cmp	r1, #0
-	bge	L_num_pos
-
-	push	{r4, lr}
-	movs	r4, #0			@ num = -num
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-
-	cmp	r3, #0
-	bge	L_neg_both
-
-	movs	r4, #0			@ den = -den
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ rem = -rem
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	pop	{r4, pc}
-
-L_neg_both:
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ quot = -quot
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-	movs	r4, #0			@ rem = -rem
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	pop	{r4, pc}
-
-L_num_pos:
-	cmp	r3, #0
-	bge	__aeabi_uldivmod
-
-	push	{r4, lr}
-	movs	r4, #0			@ den = -den
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ quot = -quot
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-	pop	{r4, pc}
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
deleted file mode 100644
index 63f060891b..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S
+++ /dev/null
@@ -1,180 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M
- * uldivmod.S: unsigned 64 bit division
- *
- * Copyright (c) 2012 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "software_panic.h"
-
-
-	.syntax unified
-	.text
-	.code 16
-
-
-
-@ {unsigned long long quotient, unsigned long long remainder}
-@ __aeabi_uldivmod(unsigned long long numerator, unsigned long long denominator)
-@
-@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder
-@ in r3:r2 (all unsigned)
-@
-	.thumb_func
-	.section .text.__aeabi_uldivmod
-        .global __aeabi_uldivmod
-__aeabi_uldivmod:
-
-	cmp	r3, #0
-	bne	L_large_denom
-	cmp	r2, #0
-	beq	L_divison_by_0
-	cmp	r1, #0
-	beq	L_fallback_32bits
-
-
-
-	@ case 1: num >= 2^32 and denom < 2^32
-	@ Result might be > 2^32, therefore we first calculate the upper 32
-	@ bits of the result. It is done similar to the calculation of the
-	@ lower 32 bits, but with a denominator that is shifted by 32.
-	@ Hence the lower 32 bits of the denominator are always 0 and the
-	@ costly 64 bit shift and sub operations can be replaced by cheap 32
-	@ bit operations.
-
-	push	{r4, r5, r6, r7, lr}
-
-	@ shift left the denominator until it is greater than the numerator
-	@ denom(r7:r6) = r3:r2 << 32
-
-	@ TODO(crosbug.com/p/36128): Loops like this (which occur in several
-	@ places in this file) are inefficent in ARMv6-m.
-
-	movs	r5, #1		@ bitmask
-	adds	r7, r2, #0	@ dont shift if denominator would overflow
-	bmi	L_upper_result
-	cmp	r1, r7
-	blo	L_upper_result
-
-L_denom_shift_loop1:
-	lsl	r5, #1
-	lsls	r7, #1
-	bmi	L_upper_result	@ dont shift if overflow
-	cmp	r1, r7
-	bhs	L_denom_shift_loop1
-
-L_upper_result:
-	mov	r3, r1
-	mov	r2, r0
-	mov	r1, #0		@ upper result = 0
-	mov	r6, #0
-
-L_sub_loop1:
-	orr	r1, r5		@ result(r7:r6) |= bitmask(r5)
-	subs	r2, r6		@ num -= denom
-	sbcs	r3, r7
-	bhs	L_done_sub1
-
-	eor	r1, r5		@ undo add mask
-	adds	r2, r6		@ undo subtract
-	adc	r3, r3, r7
-
-L_done_sub1:
-	lsrs	r7, #1		@ denom(r7:r6) >>= 1
-	rrx	r6, r6
-	lsrs	r5, #1		@ bitmask(r5) >>= 1
-	bne	L_sub_loop1
-
-	rrx r5, r5
-	b	L_lower_result
-
-
-
-	@ case 2: division by 0
-	@ call __aeabi_ldiv0
-
-L_divison_by_0:
-	b	__aeabi_ldiv0
-
-
-
-	@ case 3: num < 2^32 and denom < 2^32
-	@ fallback to 32 bit division
-
-L_fallback_32bits:
-	mov	r1, r0
-	udiv	r0, r0, r2	@ r0 = quotient
-	mul	r3, r0, r2	@ r3 = quotient * divisor
-	sub	r2, r1, r3	@ r2 = remainder
-	mov	r1, #0
-	mov	r3, #0
-	bx	lr
-
-
-
-	@ case 4: denom >= 2^32
-	@ result is smaller than 2^32
-
-L_large_denom:
-	push	{r4, r5, r6, r7, lr}
-
-	mov	r7, r3
-	mov	r6, r2
-	mov	r3, r1
-	mov	r2, r0
-
-	@ Shift left the denominator until it is greater than the numerator
-
-	mov	r1, #0		@ high word of result is 0
-	mov	r5, #1		@ bitmask
-	adds	r7, #0		@ dont shift if denominator would overflow
-	bmi	L_lower_result
-	cmp	r3, r7
-	blo	L_lower_result
-
-L_denom_shift_loop4:
-	lsl	r5, #1
-	lsls	r6, #1		@ denom(r7:r6) <<= 1
-	adcs	r7, r7
-	bmi	L_lower_result	@ dont shift if overflow
-	cmp	r3, r7
-	bhs	L_denom_shift_loop4
-
-
-
-L_lower_result:
-	movs	r0, #0
-
-L_sub_loop4:
-	orr	r0, r5		@ result(r1:r0) |= bitmask(r5)
-	subs	r2, r6		@ numerator -= denom
-	sbcs	r3, r7
-	bhs	L_done_sub4
-
-	eor	r0, r5		 @ undo add mask
-	adds	r2, r6		 @ undo subtract
-	adc	r3, r3, r7
-
-L_done_sub4:
-	lsrs	r7, #1		@ denom(r7:r6) >>= 1
-	rrx	r6, r6
-	lsrs	r5, #1		@ bitmask(r5) >>= 1
-	bne	L_sub_loop4
-
-	pop	{r4, r5, r6, r7, pc}
-
-__aeabi_ldiv0:
-	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
-	mov	SOFTWARE_PANIC_INFO_REG, r14
-	bl	exception_panic
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/div.S b/third_party/libaeabi-cortexm0/core/cortex-m0/div.S
deleted file mode 100644
index 06dc7afacb..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/div.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M0
- * idiv.S: signed 32 bit division (only quotient)
- * idivmod.S: signed 32 bit division (quotient and remainder)
- * uidivmod.S: unsigned 32 bit division
- *
- * Copyright (c) 2012 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "software_panic.h"
-
-
-	.syntax unified
-	.text
-	.thumb
-	.cpu cortex-m0
-
-@ int __aeabi_idiv(int num:r0, int denom:r1)
-@
-@ Divide r0 by r1 and return quotient in r0 (all signed).
-@ Use __aeabi_uidivmod() but check signs before and change signs afterwards.
-@
-	.thumb_func
-	.section .text.__aeabi_idiv
-	.global __aeabi_idiv
-__aeabi_idiv:
-
-	cmp	r0, #0
-	bge	L_num_pos
-
-	rsbs	r0, r0, #0		@ num = -num
-
-	cmp	r1, #0
-	bge	L_neg_result
-
-	rsbs	r1, r1, #0		@ den = -den
-	b	__aeabi_uidivmod
-
-L_num_pos:
-	cmp	r1, #0
-	bge	__aeabi_uidivmod
-
-	rsbs	r1, r1, #0		@ den = -den
-
-L_neg_result:
-	push	{lr}
-	bl	__aeabi_uidivmod
-	rsbs	r0, r0, #0		@ quot = -quot
-	pop	{pc}
-
-
-
-@ {int quotient:r0, int remainder:r1}
-@ __aeabi_idivmod(int numerator:r0, int denominator:r1)
-@
-@ Divide r0 by r1 and return the quotient in r0 and the remainder in r1
-@
-	.thumb_func
-	.section .text.__aeabi_idivmod
-	.global __aeabi_idivmod
-__aeabi_idivmod:
-
-	cmp	r0, #0
-	bge	L_num_pos_bis
-
-	rsbs	r0, r0, #0		@ num = -num
-
-	cmp	r1, #0
-	bge	L_neg_both
-
-	rsbs	r1, r1, #0		@ den = -den
-	push	{lr}
-	bl	__aeabi_uidivmod
-	rsbs	r1, r1, #0		@ rem = -rem
-	pop	{pc}
-
-L_neg_both:
-	push	{lr}
-	bl	__aeabi_uidivmod
-	rsbs	r0, r0, #0		@ quot = -quot
-	rsbs	r1, r1, #0		@ rem = -rem
-	pop	{pc}
-
-L_num_pos_bis:
-	cmp	r1, #0
-	bge	__aeabi_uidivmod
-
-	rsbs	r1, r1, #0		@ den = -den
-	push	{lr}
-	bl	__aeabi_uidivmod
-	rsbs	r0, r0, #0		@ quot = -quot
-	pop	{pc}
-
-
-
-@ unsigned __aeabi_uidiv(unsigned num, unsigned denom)
-@
-@ Just an alias for __aeabi_uidivmod(), the remainder is ignored
-@
-	.thumb_func
-	.section .text.__aeabi_uidivmod
-	.global __aeabi_uidiv
-__aeabi_uidiv:
-
-
-
-@ {unsigned quotient:r0, unsigned remainder:r1}
-@  __aeabi_uidivmod(unsigned numerator:r0, unsigned denominator:r1)
-@
-@ Divide r0 by r1 and return the quotient in r0 and the remainder in r1
-@
-	.thumb_func
-	.global __aeabi_uidivmod
-__aeabi_uidivmod:
-
-
-	cmp	r1, #0
-	bne	L_no_div0
-	b	__aeabi_idiv0
-L_no_div0:
-
-	@ Shift left the denominator until it is greater than the numerator
-	movs	r2, #1		@ counter
-	movs	r3, #0		@ result
-	cmp	r0, r1
-	bls	L_sub_loop0
-	adds	r1, #0		@ dont shift if denominator would overflow
-	bmi	L_sub_loop0
-
-L_denom_shift_loop:
-	lsls	r2, #1
-	lsls	r1, #1
-	bmi	L_sub_loop0
-	cmp	r0, r1
-	bhi	L_denom_shift_loop
-
-L_sub_loop0:
-	cmp	r0, r1
-	bcc	L_dont_sub0	@ if (num>denom)
-
-	subs	r0, r1		@ numerator -= denom
-	orrs	r3, r2		@ result(r3) |= bitmask(r2)
-L_dont_sub0:
-
-	lsrs	r1, #1		@ denom(r1) >>= 1
-	lsrs	r2, #1		@ bitmask(r2) >>= 1
-	bne	L_sub_loop0
-
-	mov	r1, r0		@ remainder(r1) = numerator(r0)
-	mov	r0, r3		@ quotient(r0) = result(r3)
-	bx	lr
-
-__aeabi_idiv0:
-	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
-	mov	SOFTWARE_PANIC_INFO_REG, r14
-	bl	exception_panic
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S
deleted file mode 100644
index f552829ab2..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M0
- * ldivmod.S: signed 64 bit division (quotient and remainder)
- *
- * Copyright 2012 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-
-
-	.syntax unified
-	.text
-	.thumb
-	.cpu cortex-m0
-
-
-
-@ {long long quotient, long long remainder}
-@ __aeabi_ldivmod(long long numerator, long long denominator)
-@
-@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder in
-@ r3:r2 (all signed)
-@
-	.thumb_func
-	.section .text.__aeabi_ldivmod
-        .global __aeabi_ldivmod
-__aeabi_ldivmod:
-
-	cmp	r1, #0
-	bge	L_num_pos
-
-	push	{r4, lr}
-	movs	r4, #0			@ num = -num
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-
-	cmp	r3, #0
-	bge	L_neg_both
-
-	movs	r4, #0			@ den = -den
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ rem = -rem
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	pop	{r4, pc}
-
-L_neg_both:
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ quot = -quot
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-	movs	r4, #0			@ rem = -rem
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	pop	{r4, pc}
-
-L_num_pos:
-	cmp	r3, #0
-	blt	L_den_neg
-	push	{r4, lr}
-	bl	__aeabi_uldivmod	@ offset too big for b / bge
-	pop	{r4, pc}
-
-L_den_neg:
-	push	{r4, lr}
-	movs	r4, #0			@ den = -den
-	rsbs	r2, r2, #0
-	sbcs	r4, r3
-	mov	r3, r4
-	bl	__aeabi_uldivmod
-	movs	r4, #0			@ quot = -quot
-	rsbs	r0, r0, #0
-	sbcs	r4, r1
-	mov	r1, r4
-	pop	{r4, pc}
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/lmul.S b/third_party/libaeabi-cortexm0/core/cortex-m0/lmul.S
deleted file mode 100644
index ab04fd488f..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/lmul.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M0
- * lmul.S: 64 bit multiplication
- *
- * Copyright (c) 2013 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-
-
-	.syntax unified
-	.text
-	.thumb
-	.cpu cortex-m0
-
-
-
-@ long long __aeabi_lmul(long long r1:r0, long long r3:r2)
-@
-@ Multiply r1:r0 and r3:r2 and return the product in r1:r0
-@ Can also be used for unsigned long product
-@
-	.thumb_func
-	.section .text.__aeabi_lmul
-	.global __aeabi_lmul
-__aeabi_lmul:
-
-	push	{r4, lr}
-	muls	r1, r2
-	muls	r3, r0
-	adds	r1, r3
-
-	lsrs	r3, r0, #16
-	lsrs	r4, r2, #16
-	muls	r3, r4
-	adds	r1, r3
-
-	lsrs	r3, r0, #16
-	uxth	r0, r0
-	uxth	r2, r2
-	muls	r3, r2
-	muls	r4, r0
-	muls	r0, r2
-
-	movs	r2, #0
-	adds	r3, r4
-	adcs	r2, r2
-	lsls	r2, #16
-	adds	r1, r2
-
-	lsls	r2, r3, #16
-	lsrs	r3, #16
-	adds	r0, r2
-	adcs	r1, r3
-	pop	{r4, pc}
diff --git a/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S b/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
deleted file mode 100644
index 6c0a469d65..0000000000
--- a/third_party/libaeabi-cortexm0/core/cortex-m0/uldivmod.S
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Runtime ABI for the ARM Cortex-M0
- * uldivmod.S: unsigned 64 bit division
- *
- * Copyright 2012 Jörg Mische <bobbl@gmx.de>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "software_panic.h"
-
-
-	.syntax unified
-	.text
-	.thumb
-	.cpu cortex-m0
-
-
-
-@ {unsigned long long quotient, unsigned long long remainder}
-@ __aeabi_uldivmod(unsigned long long numerator, unsigned long long denominator)
-@
-@ Divide r1:r0 by r3:r2 and return the quotient in r1:r0 and the remainder
-@ in r3:r2 (all unsigned)
-@
-	.thumb_func
-	.section .text.__aeabi_uldivmod
-        .global __aeabi_uldivmod
-__aeabi_uldivmod:
-
-	cmp	r3, #0
-	bne	L_large_denom
-	cmp	r2, #0
-	beq	L_divison_by_0
-	cmp	r1, #0
-	beq	L_fallback_32bits
-
-
-
-	@ case 1: num >= 2^32 and denom < 2^32
-	@ Result might be > 2^32, therefore we first calculate the upper 32
-	@ bits of the result. It is done similar to the calculation of the
-	@ lower 32 bits, but with a denominator that is shifted by 32.
-	@ Hence the lower 32 bits of the denominator are always 0 and the
-	@ costly 64 bit shift and sub operations can be replaced by cheap 32
-	@ bit operations.
-
-	push	{r4, r5, r6, r7, lr}
-
-	@ shift left the denominator until it is greater than the numerator
-	@ denom(r7:r6) = r3:r2 << 32
-
-	movs	r5, #1		@ bitmask
-	adds	r7, r2, #0	@ dont shift if denominator would overflow
-	bmi	L_upper_result
-	cmp	r1, r7
-	blo	L_upper_result
-
-L_denom_shift_loop1:
-	lsls	r5, #1
-	lsls	r7, #1
-	bmi	L_upper_result	@ dont shift if overflow
-	cmp	r1, r7
-	bhs	L_denom_shift_loop1
-
-L_upper_result:
-	mov	r3, r1
-	mov	r2, r0
-	movs	r1, #0		@ upper result = 0
-
-L_sub_loop1:
-	cmp	r3, r7
-	bcc	L_dont_sub1	@ if (num>denom)
-
-	subs	r3, r7		@ num -= denom
-	orrs	r1, r5		@ result(r7:r6) |= bitmask(r5)
-L_dont_sub1:
-
-	lsrs	r7, #1		@ denom(r7:r6) >>= 1
-	lsrs	r5, #1		@ bitmask(r5) >>= 1
-	bne	L_sub_loop1
-
-	movs	r5, #1
-	lsls	r5, #31
-	movs	r6, #0
-	b	L_lower_result
-
-
-
-	@ case 2: division by 0
-	@ call __aeabi_ldiv0
-
-L_divison_by_0:
-	b	__aeabi_ldiv0
-
-
-
-	@ case 3: num < 2^32 and denom < 2^32
-	@ fallback to 32 bit division
-
-L_fallback_32bits:
-	mov	r1, r2
-	push	{lr}
-	bl	__aeabi_uidivmod
-	mov	r2, r1
-	movs	r1, #0
-	movs	r3, #0
-	pop	{pc}
-
-
-
-	@ case 4: denom >= 2^32
-	@ result is smaller than 2^32
-
-L_large_denom:
-	push	{r4, r5, r6, r7, lr}
-
-	mov	r7, r3
-	mov	r6, r2
-	mov	r3, r1
-	mov	r2, r0
-
-	@ Shift left the denominator until it is greater than the numerator
-
-	movs	r1, #0		@ high word of result is 0
-	movs	r5, #1		@ bitmask
-	adds	r7, #0		@ dont shift if denominator would overflow
-	bmi	L_lower_result
-	cmp	r3, r7
-	blo	L_lower_result
-
-L_denom_shift_loop4:
-	lsls	r5, #1
-	lsls	r7, #1
-	lsls	r6, #1
-	adcs	r7, r1		@ r1=0
-	bmi	L_lower_result	@ dont shift if overflow
-	cmp	r3, r7
-	bhs	L_denom_shift_loop4
-
-
-
-L_lower_result:
-	movs	r0, #0
-
-L_sub_loop4:
-	mov	r4, r3
-	cmp	r2, r6
-	sbcs	r4, r7
-	bcc	L_dont_sub4	@ if (num>denom)
-
-	subs	r2, r6		@ numerator -= denom
-	sbcs	r3, r7
-	orrs	r0, r5		@ result(r1:r0) |= bitmask(r5)
-L_dont_sub4:
-
-	lsls	r4, r7, #31	@ denom(r7:r6) >>= 1
-	lsrs	r6, #1
-	lsrs	r7, #1
-	orrs	r6, r4
-	lsrs	r5, #1		@ bitmask(r5) >>= 1
-	bne	L_sub_loop4
-
-	pop	{r4, r5, r6, r7, pc}
-
-__aeabi_ldiv0:
-	ldr	SOFTWARE_PANIC_REASON_REG, =PANIC_SW_DIV_ZERO
-	mov	SOFTWARE_PANIC_INFO_REG, r14
-	bl	exception_panic
diff --git a/third_party/linux/LICENSE b/third_party/linux/LICENSE
deleted file mode 100644
index f85e365de0..0000000000
--- a/third_party/linux/LICENSE
+++ /dev/null
@@ -1,17 +0,0 @@
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
diff --git a/third_party/linux/METADATA b/third_party/linux/METADATA
deleted file mode 100644
index e682210706..0000000000
--- a/third_party/linux/METADATA
+++ /dev/null
@@ -1,14 +0,0 @@
-name: "Linux Kernel Overflow Macros"
-description:
-    "Macros for checking arithmetic overflow."
-
-third_party {
-  url {
-    type: GIT
-    value: "https://github.com/torvalds/linux.git"
-  }
-  version: "5925fa68fe8244651b3f78a88c4af99190a88f0d"
-  last_upgrade_date { year: 2020 month: 9 day: 18 }
-  license_type: NOTICE
-}
-
diff --git a/third_party/linux/overflow.h b/third_party/linux/overflow.h
deleted file mode 100644
index caa720e6ad..0000000000
--- a/third_party/linux/overflow.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-#ifndef __LINUX_OVERFLOW_H
-#define __LINUX_OVERFLOW_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * In the fallback code below, we need to compute the minimum and
- * maximum values representable in a given type. These macros may also
- * be useful elsewhere, so we provide them outside the
- * COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW block.
- *
- * It would seem more obvious to do something like
- *
- * #define type_min(T) (T)(is_signed_type(T) ? (T)1 << (8*sizeof(T)-1) : 0)
- * #define type_max(T) (T)(is_signed_type(T) ? ((T)1 << (8*sizeof(T)-1)) - 1 : ~(T)0)
- *
- * Unfortunately, the middle expressions, strictly speaking, have
- * undefined behaviour, and at least some versions of gcc warn about
- * the type_max expression (but not if -fsanitize=undefined is in
- * effect; in that case, the warning is deferred to runtime...).
- *
- * The slightly excessive casting in type_min is to make sure the
- * macros also produce sensible values for the exotic type _Bool. [The
- * overflow checkers only almost work for _Bool, but that's
- * a-feature-not-a-bug, since people shouldn't be doing arithmetic on
- * _Bools. Besides, the gcc builtins don't allow _Bool* as third
- * argument.]
- *
- * Idea stolen from
- * https://mail-index.netbsd.org/tech-misc/2007/02/05/0000.html -
- * credit to Christian Biere.
- */
-#define is_signed_type(type)       (((type)(-1)) < (type)1)
-#define __type_half_max(type) ((type)1 << (8*sizeof(type) - 1 - is_signed_type(type)))
-#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
-#define type_min(T) ((T)((T)-type_max(T)-(T)1))
-
-/*
- * Avoids triggering -Wtype-limits compilation warning,
- * while using unsigned data types to check a < 0.
- */
-#define is_non_negative(a) ((a) > 0 || (a) == 0)
-#define is_negative(a) (!(is_non_negative(a)))
-
-#ifdef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
-/*
- * For simplicity and code hygiene, the fallback code below insists on
- * a, b and *d having the same type (similar to the min() and max()
- * macros), whereas gcc's type-generic overflow checkers accept
- * different types. Hence we don't just make check_add_overflow an
- * alias for __builtin_add_overflow, but add type checks similar to
- * below.
- */
-#define check_add_overflow(a, b, d) ({		\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	__builtin_add_overflow(__a, __b, __d);	\
-})
-
-#define check_sub_overflow(a, b, d) ({		\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	__builtin_sub_overflow(__a, __b, __d);	\
-})
-
-#define check_mul_overflow(a, b, d) ({		\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	__builtin_mul_overflow(__a, __b, __d);	\
-})
-
-#else
-
-
-/* Checking for unsigned overflow is relatively easy without causing UB. */
-#define __unsigned_add_overflow(a, b, d) ({	\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	*__d = __a + __b;			\
-	*__d < __a;				\
-})
-#define __unsigned_sub_overflow(a, b, d) ({	\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	*__d = __a - __b;			\
-	__a < __b;				\
-})
-/*
- * If one of a or b is a compile-time constant, this avoids a division.
- */
-#define __unsigned_mul_overflow(a, b, d) ({		\
-	typeof(a) __a = (a);				\
-	typeof(b) __b = (b);				\
-	typeof(d) __d = (d);				\
-	(void) (&__a == &__b);				\
-	(void) (&__a == __d);				\
-	*__d = __a * __b;				\
-	__builtin_constant_p(__b) ?			\
-	  __b > 0 && __a > type_max(typeof(__a)) / __b : \
-	  __a > 0 && __b > type_max(typeof(__b)) / __a;	 \
-})
-
-/*
- * For signed types, detecting overflow is much harder, especially if
- * we want to avoid UB. But the interface of these macros is such that
- * we must provide a result in *d, and in fact we must produce the
- * result promised by gcc's builtins, which is simply the possibly
- * wrapped-around value. Fortunately, we can just formally do the
- * operations in the widest relevant unsigned type (uint64_t) and then
- * truncate the result - gcc is smart enough to generate the same code
- * with and without the (uint64_t) casts.
- */
-
-/*
- * Adding two signed integers can overflow only if they have the same
- * sign, and overflow has happened iff the result has the opposite
- * sign.
- */
-#define __signed_add_overflow(a, b, d) ({	\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	*__d = (uint64_t)__a + (uint64_t)__b;	\
-	(((~(__a ^ __b)) & (*__d ^ __a))	\
-		& type_min(typeof(__a))) != 0;	\
-})
-
-/*
- * Subtraction is similar, except that overflow can now happen only
- * when the signs are opposite. In this case, overflow has happened if
- * the result has the opposite sign of a.
- */
-#define __signed_sub_overflow(a, b, d) ({	\
-	typeof(a) __a = (a);			\
-	typeof(b) __b = (b);			\
-	typeof(d) __d = (d);			\
-	(void) (&__a == &__b);			\
-	(void) (&__a == __d);			\
-	*__d = (uint64_t)__a - (uint64_t)__b;	\
-	((((__a ^ __b)) & (*__d ^ __a))		\
-		& type_min(typeof(__a))) != 0;	\
-})
-
-/*
- * Signed multiplication is rather hard. gcc always follows C99, so
- * division is truncated towards 0. This means that we can write the
- * overflow check like this:
- *
- * (a > 0 && (b > MAX/a || b < MIN/a)) ||
- * (a < -1 && (b > MIN/a || b < MAX/a) ||
- * (a == -1 && b == MIN)
- *
- * The redundant casts of -1 are to silence an annoying -Wtype-limits
- * (included in -Wextra) warning: When the type is u8 or u16, the
- * __b_c_e in check_mul_overflow obviously selects
- * __unsigned_mul_overflow, but unfortunately gcc still parses this
- * code and warns about the limited range of __b.
- */
-
-#define __signed_mul_overflow(a, b, d) ({				\
-	typeof(a) __a = (a);						\
-	typeof(b) __b = (b);						\
-	typeof(d) __d = (d);						\
-	typeof(a) __tmax = type_max(typeof(a));				\
-	typeof(a) __tmin = type_min(typeof(a));				\
-	(void) (&__a == &__b);						\
-	(void) (&__a == __d);						\
-	*__d = (uint64_t)__a * (uint64_t)__b;				\
-	(__b > 0   && (__a > __tmax/__b || __a < __tmin/__b)) ||	\
-	(__b < (typeof(__b))-1  && (__a > __tmin/__b || __a < __tmax/__b)) || \
-	(__b == (typeof(__b))-1 && __a == __tmin);			\
-})
-
-
-#define check_add_overflow(a, b, d)					\
-	__builtin_choose_expr(is_signed_type(typeof(a)),		\
-			__signed_add_overflow(a, b, d),			\
-			__unsigned_add_overflow(a, b, d))
-
-#define check_sub_overflow(a, b, d)					\
-	__builtin_choose_expr(is_signed_type(typeof(a)),		\
-			__signed_sub_overflow(a, b, d),			\
-			__unsigned_sub_overflow(a, b, d))
-
-#define check_mul_overflow(a, b, d)					\
-	__builtin_choose_expr(is_signed_type(typeof(a)),		\
-			__signed_mul_overflow(a, b, d),			\
-			__unsigned_mul_overflow(a, b, d))
-
-
-#endif /* COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW */
-
-/** check_shl_overflow() - Calculate a left-shifted value and check overflow
- *
- * @a: Value to be shifted
- * @s: How many bits left to shift
- * @d: Pointer to where to store the result
- *
- * Computes *@d = (@a << @s)
- *
- * Returns true if '*d' cannot hold the result or when 'a << s' doesn't
- * make sense. Example conditions:
- * - 'a << s' causes bits to be lost when stored in *d.
- * - 's' is garbage (e.g. negative) or so large that the result of
- *   'a << s' is guaranteed to be 0.
- * - 'a' is negative.
- * - 'a << s' sets the sign bit, if any, in '*d'.
- *
- * '*d' will hold the results of the attempted shift, but is not
- * considered "safe for use" if false is returned.
- */
-#define check_shl_overflow(a, s, d) ({					\
-	typeof(a) _a = a;						\
-	typeof(s) _s = s;						\
-	typeof(d) _d = d;						\
-	uint64_t _a_full = _a;						\
-	unsigned int _to_shift =					\
-		is_non_negative(_s) && _s < 8 * sizeof(*d) ? _s : 0;	\
-	*_d = (_a_full << _to_shift);					\
-	(_to_shift != _s || is_negative(*_d) || is_negative(_a) ||	\
-	(*_d >> _to_shift) != _a);					\
-})
-
-/*
- * Disabling for EC since we don't currently have SIZE_MAX defined in our
- * stdint.h.
- */
-#if 0
-/**
- * array_size() - Calculate size of 2-dimensional array.
- *
- * @a: dimension one
- * @b: dimension two
- *
- * Calculates size of 2-dimensional array: @a * @b.
- *
- * Returns: number of bytes needed to represent the array or SIZE_MAX on
- * overflow.
- */
-static inline /*__must_check*/ size_t array_size(size_t a, size_t b)
-{
-	size_t bytes;
-
-	if (check_mul_overflow(a, b, &bytes))
-		return SIZE_MAX;
-
-	return bytes;
-}
-
-/**
- * array3_size() - Calculate size of 3-dimensional array.
- *
- * @a: dimension one
- * @b: dimension two
- * @c: dimension three
- *
- * Calculates size of 3-dimensional array: @a * @b * @c.
- *
- * Returns: number of bytes needed to represent the array or SIZE_MAX on
- * overflow.
- */
-static inline /*__must_check*/ size_t array3_size(size_t a, size_t b, size_t c)
-{
-	size_t bytes;
-
-	if (check_mul_overflow(a, b, &bytes))
-		return SIZE_MAX;
-	if (check_mul_overflow(bytes, c, &bytes))
-		return SIZE_MAX;
-
-	return bytes;
-}
-
-/*
- * Compute a*b+c, returning SIZE_MAX on overflow. Internal helper for
- * struct_size() below.
- */
-static inline /*__must_check*/ size_t __ab_c_size(size_t a, size_t b, size_t c)
-{
-	size_t bytes;
-
-	if (check_mul_overflow(a, b, &bytes))
-		return SIZE_MAX;
-	if (check_add_overflow(bytes, c, &bytes))
-		return SIZE_MAX;
-
-	return bytes;
-}
-#endif
-
-/**
- * struct_size() - Calculate size of structure with trailing array.
- * @p: Pointer to the structure.
- * @member: Name of the array member.
- * @count: Number of elements in the array.
- *
- * Calculates size of memory needed for structure @p followed by an
- * array of @count number of @member elements.
- *
- * Return: number of bytes needed or SIZE_MAX on overflow.
- */
-#define struct_size(p, member, count)					\
-	__ab_c_size(count,						\
-		    sizeof(*(p)->member) + __must_be_array((p)->member),\
-		    sizeof(*(p)))
-
-/**
- * flex_array_size() - Calculate size of a flexible array member
- *                     within an enclosing structure.
- *
- * @p: Pointer to the structure.
- * @member: Name of the flexible array member.
- * @count: Number of elements in the array.
- *
- * Calculates size of a flexible array of @count number of @member
- * elements, at the end of structure @p.
- *
- * Return: number of bytes needed or SIZE_MAX on overflow.
- */
-#define flex_array_size(p, member, count)				\
-	array_size(count,						\
-		    sizeof(*(p)->member) + __must_be_array((p)->member))
-
-#endif /* __LINUX_OVERFLOW_H */
diff --git a/third_party/rules.mk b/third_party/rules.mk
deleted file mode 100644
index 16fd1e52e3..0000000000
--- a/third_party/rules.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-# -*- makefile -*-
-# vim: set filetype=make :
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Embedded Controller firmware build system - third_party rules/targets
-#
-
-# Build and link against libcryptoc.
-# See https://chromium.googlesource.com/chromiumos/third_party/cryptoc .
-ifeq ($(CONFIG_LIBCRYPTOC),y)
-
-# The cryptoc path can be overridden on invocation, as in the following example:
-# $ make CRYPTOC_DIR=~/src/cryptoc BOARD=bloonchipper
-CRYPTOC_DIR ?= $(realpath ../../third_party/cryptoc)
-
-# SUPPORT_UNALIGNED indicates to libcryptoc that provided data buffers
-# may be unaligned and please handle them safely.
-cmd_libcryptoc = $(MAKE) -C $(CRYPTOC_DIR) \
-	obj=$(realpath $(out))/cryptoc \
-	SUPPORT_UNALIGNED=1
-cmd_libcryptoc_clean = $(cmd_libcryptoc) -q && echo clean
-
-ifneq ($(BOARD),host)
-CPPFLAGS += -I$(abspath ./builtin)
-endif
-CPPFLAGS += -I$(CRYPTOC_DIR)/include
-CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc
-
-# Conditionally force the rebuilding of libcryptoc.a only if it would be
-# changed.
-# Note, we use ifndef to ensure the likelyhood of rebuilding is much higher.
-# For example, if variable cmd_libcryptoc_clean is modified or blank,
-# we will rebuild.
-ifneq ($(shell $(cmd_libcryptoc_clean)),clean)
-.PHONY: $(out)/cryptoc/libcryptoc.a
-endif
-$(out)/cryptoc/libcryptoc.a:
-	+$(call quiet,libcryptoc,MAKE   )
-
-# Link RO and RW against cryptoc.
-$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/RO/ec.RO.elf $(out)/RO/ec.RO_B.elf: $(out)/cryptoc/libcryptoc.a
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: $(out)/cryptoc/libcryptoc.a
-# Host test executables (including fuzz tests).
-$(out)/$(PROJECT).exe: LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(out)/$(PROJECT).exe: $(out)/cryptoc/libcryptoc.a
-# On-device tests.
-test-targets=$(foreach test,$(test-list-y),\
-	$(out)/RW/$(test).RW.elf $(out)/RO/$(test).RO.elf)
-$(test-targets): LDFLAGS_EXTRA += $(CRYPTOC_LDFLAGS)
-$(test-targets): $(out)/cryptoc/libcryptoc.a
-
-endif # CONFIG_LIBCRYPTOC
diff --git a/third_party/sha2/LICENSE b/third_party/sha2/LICENSE
deleted file mode 100644
index 87e21badf3..0000000000
--- a/third_party/sha2/LICENSE
+++ /dev/null
@@ -1,23 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. Neither the name of the project nor the names of its contributors
-   may be used to endorse or promote products derived from this software
-   without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
\ No newline at end of file
diff --git a/third_party/sha2/METADATA b/third_party/sha2/METADATA
deleted file mode 100644
index 50b90022a9..0000000000
--- a/third_party/sha2/METADATA
+++ /dev/null
@@ -1,16 +0,0 @@
-name: "SHA-256 implementation"
-description:
-    "Fast software implementation in C of the FIPS 180-2 hash algorithms"
-    "SHA-224, SHA-256, SHA-384 and SHA-512"
-
-third_party {
-  url {
-    type: GIT
-    value: "https://github.com/ogay/sha2"
-  }
-  version: "79116b5d5d449311c27a24e16c99d8bccb4d1301"
-  last_upgrade_date { year: 2014 month: 04 day: 01 }
-  license_type: NOTICE
-  local_modifications: "See git log. "
-    "Created LICENSE file."
-}
\ No newline at end of file
diff --git a/third_party/sha2/sha256.c b/third_party/sha2/sha256.c
deleted file mode 100644
index 2d6eaa43f2..0000000000
--- a/third_party/sha2/sha256.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/* SHA-256 and SHA-512 implementation based on code by Oliver Gay
- * <olivier.gay@a3.epfl.ch> under a BSD-style license. See below.
- */
-
-/*
- * FIPS 180-2 SHA-224/256/384/512 implementation
- * Last update: 02/02/2007
- * Issue date:  04/30/2005
- *
- * Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the project nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include "sha256.h"
-#include "util.h"
-
-#define SHFR(x, n)    (x >> n)
-#define ROTR(x, n)   ((x >> n) | (x << ((sizeof(x) << 3) - n)))
-#define ROTL(x, n)   ((x << n) | (x >> ((sizeof(x) << 3) - n)))
-#define CH(x, y, z)  ((x & y) ^ (~x & z))
-#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
-
-#define SHA256_F1(x) (ROTR(x,  2) ^ ROTR(x, 13) ^ ROTR(x, 22))
-#define SHA256_F2(x) (ROTR(x,  6) ^ ROTR(x, 11) ^ ROTR(x, 25))
-#define SHA256_F3(x) (ROTR(x,  7) ^ ROTR(x, 18) ^ SHFR(x,  3))
-#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10))
-
-#define UNPACK32(x, str)				\
-	{						\
-		*((str) + 3) = (uint8_t) ((x));		\
-		*((str) + 2) = (uint8_t) ((x) >>  8);	\
-		*((str) + 1) = (uint8_t) ((x) >> 16);	\
-		*((str) + 0) = (uint8_t) ((x) >> 24);	\
-	}
-
-#define PACK32(str, x)						\
-	{							\
-		*(x) = ((uint32_t) *((str) + 3))		\
-			| ((uint32_t) *((str) + 2) <<  8)	\
-			| ((uint32_t) *((str) + 1) << 16)	\
-			| ((uint32_t) *((str) + 0) << 24);	\
-	}
-
-/* Macros used for loops unrolling */
-
-#define SHA256_SCR(i)						\
-	{							\
-		w[i] =  SHA256_F4(w[i -  2]) + w[i -  7]	\
-			+ SHA256_F3(w[i - 15]) + w[i - 16];	\
-	}
-
-#define SHA256_EXP(a, b, c, d, e, f, g, h, j)				\
-	{								\
-		t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g])	\
-			+ sha256_k[j] + w[j];				\
-		t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]);	\
-		wv[d] += t1;						\
-		wv[h] = t1 + t2;					\
-	}
-
-static const uint32_t sha256_h0[8] = {
-	0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
-	0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19};
-
-static const uint32_t sha256_k[64] = {
-	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
-	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
-	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
-	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
-	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
-	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
-	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
-	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
-	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
-	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
-	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
-	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
-	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
-	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
-	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
-	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2};
-
-void SHA256_init(struct sha256_ctx *ctx)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		ctx->h[i] = sha256_h0[i];
-
-	ctx->len = 0;
-	ctx->tot_len = 0;
-}
-
-static void SHA256_transform(struct sha256_ctx *ctx, const uint8_t *message,
-			     unsigned int block_nb)
-{
-	/* Note: this function requires a considerable amount of stack */
-	uint32_t w[64];
-	uint32_t wv[8];
-	uint32_t t1, t2;
-	const unsigned char *sub_block;
-	int i, j;
-
-	for (i = 0; i < (int) block_nb; i++) {
-		sub_block = message + (i << 6);
-
-		for (j = 0; j < 16; j++)
-			PACK32(&sub_block[j << 2], &w[j]);
-
-#ifdef CONFIG_SHA256_UNROLLED
-		for (j = 16; j < 64; j += 8) {
-			SHA256_SCR(j);
-			SHA256_SCR(j+1);
-			SHA256_SCR(j+2);
-			SHA256_SCR(j+3);
-			SHA256_SCR(j+4);
-			SHA256_SCR(j+5);
-			SHA256_SCR(j+6);
-			SHA256_SCR(j+7);
-		}
-#else
-		for (j = 16; j < 64; j++)
-			SHA256_SCR(j);
-#endif
-
-		for (j = 0; j < 8; j++)
-			wv[j] = ctx->h[j];
-
-#ifdef CONFIG_SHA256_UNROLLED
-		for (j = 0; j < 64; j += 8) {
-			SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, j);
-			SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, j+1);
-			SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, j+2);
-			SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, j+3);
-			SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, j+4);
-			SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, j+5);
-			SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, j+6);
-			SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, j+7);
-		}
-#else
-		for (j = 0; j < 64; j++) {
-			t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6])
-				+ sha256_k[j] + w[j];
-			t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]);
-			wv[7] = wv[6];
-			wv[6] = wv[5];
-			wv[5] = wv[4];
-			wv[4] = wv[3] + t1;
-			wv[3] = wv[2];
-			wv[2] = wv[1];
-			wv[1] = wv[0];
-			wv[0] = t1 + t2;
-		}
-#endif
-
-		for (j = 0; j < 8; j++)
-			ctx->h[j] += wv[j];
-	}
-}
-
-void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
-{
-	unsigned int block_nb;
-	unsigned int new_len, rem_len, tmp_len;
-	const uint8_t *shifted_data;
-
-	tmp_len = SHA256_BLOCK_SIZE - ctx->len;
-	rem_len = len < tmp_len ? len : tmp_len;
-
-	memcpy(&ctx->block[ctx->len], data, rem_len);
-
-	if (ctx->len + len < SHA256_BLOCK_SIZE) {
-		ctx->len += len;
-		return;
-	}
-
-	new_len = len - rem_len;
-	block_nb = new_len / SHA256_BLOCK_SIZE;
-
-	shifted_data = data + rem_len;
-
-	SHA256_transform(ctx, ctx->block, 1);
-	SHA256_transform(ctx, shifted_data, block_nb);
-
-	rem_len = new_len % SHA256_BLOCK_SIZE;
-
-	memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len);
-
-	ctx->len = rem_len;
-	ctx->tot_len += (block_nb + 1) << 6;
-}
-
-/*
- * Specialized SHA256_init + SHA256_update that takes the first data block of
- * size SHA256_BLOCK_SIZE as input.
- */
-static void SHA256_init_1b(struct sha256_ctx *ctx, const uint8_t *data)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		ctx->h[i] = sha256_h0[i];
-
-	SHA256_transform(ctx, data, 1);
-
-	ctx->len = 0;
-	ctx->tot_len = SHA256_BLOCK_SIZE;
-}
-
-uint8_t *SHA256_final(struct sha256_ctx *ctx)
-{
-	unsigned int block_nb;
-	unsigned int pm_len;
-	unsigned int len_b;
-	int i;
-
-	block_nb = (1 + ((SHA256_BLOCK_SIZE - 9)
-			 < (ctx->len % SHA256_BLOCK_SIZE)));
-
-	len_b = (ctx->tot_len + ctx->len) << 3;
-	pm_len = block_nb << 6;
-
-	memset(ctx->block + ctx->len, 0, pm_len - ctx->len);
-	ctx->block[ctx->len] = 0x80;
-	UNPACK32(len_b, ctx->block + pm_len - 4);
-
-	SHA256_transform(ctx, ctx->block, block_nb);
-
-	for (i = 0; i < 8; i++)
-		UNPACK32(ctx->h[i], &ctx->buf[i << 2]);
-
-	return ctx->buf;
-}
-
-static void hmac_SHA256_step(uint8_t *output, uint8_t mask,
-			const uint8_t *key, const int key_len,
-			const uint8_t *data, const int data_len) {
-	struct sha256_ctx ctx;
-	uint8_t *key_pad = ctx.block;
-	uint8_t *tmp;
-	int i;
-
-	/* key_pad = key (zero-padded) ^ mask */
-	memset(key_pad, mask, SHA256_BLOCK_SIZE);
-	for (i = 0; i < key_len; i++)
-		key_pad[i] ^= key[i];
-
-	/* tmp = hash(key_pad || message) */
-	SHA256_init_1b(&ctx, key_pad);
-	SHA256_update(&ctx, data, data_len);
-	tmp = SHA256_final(&ctx);
-	memcpy(output, tmp, SHA256_DIGEST_SIZE);
-}
-
-void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
-		 const uint8_t *message, const int message_len) {
-	/* This code does not support key_len > block_size. */
-	ASSERT(key_len <= SHA256_BLOCK_SIZE);
-
-	/*
-	 * i_key_pad = key (zero-padded) ^ 0x36
-	 * output = hash(i_key_pad || message)
-	 * (Use output as temporary buffer)
-	 */
-	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
-
-	/*
-	 * o_key_pad = key (zero-padded) ^ 0x5c
-	 * output = hash(o_key_pad || output)
-	 */
-	hmac_SHA256_step(output, 0x5c,
-			 key, key_len, output, SHA256_DIGEST_SIZE);
-}
diff --git a/third_party/unacl-curve25519/LICENSE b/third_party/unacl-curve25519/LICENSE
deleted file mode 100644
index d45ad380d2..0000000000
--- a/third_party/unacl-curve25519/LICENSE
+++ /dev/null
@@ -1,38 +0,0 @@
-=== core/cortex-m0/curve25519/*.S
-
-public domain.
-
-=== core/cortex-m0/curve25519/scalarmult.c
-
-Creative Commons CC0 1.0 Universal
-
-Statement of Purpose
-
-The laws of most jurisdictions throughout the world automatically confer exclusive Copyright and Related Rights (defined below) upon the creator and subsequent owner(s) (each and all, an "owner") of an original work of authorship and/or a database (each, a "Work").
-
-Certain owners wish to permanently relinquish those rights to a Work for the purpose of contributing to a commons of creative, cultural and scientific works ("Commons") that the public can reliably and without fear of later claims of infringement build upon, modify, incorporate in other works, reuse and redistribute as freely as possible in any form whatsoever and for any purposes, including without limitation commercial purposes. These owners may contribute to the Commons to promote the ideal of a free culture and the further production of creative, cultural and scientific works, or to gain reputation or greater distribution for their Work in part through the use and efforts of others.
-
-For these and/or other purposes and motivations, and without any expectation of additional consideration or compensation, the person associating CC0 with a Work (the "Affirmer"), to the extent that he or she is an owner of Copyright and Related Rights in the Work, voluntarily elects to apply CC0 to the Work and publicly distribute the Work under its terms, with knowledge of his or her Copyright and Related Rights in the Work and the meaning and intended legal effect of CC0 on those rights.
-
-1. Copyright and Related Rights. A Work made available under CC0 may be protected by copyright and related or neighboring rights ("Copyright and Related Rights"). Copyright and Related Rights include, but are not limited to, the following:
-
-    the right to reproduce, adapt, distribute, perform, display, communicate, and translate a Work;
-    moral rights retained by the original author(s) and/or performer(s);
-    publicity and privacy rights pertaining to a person's image or likeness depicted in a Work;
-    rights protecting against unfair competition in regards to a Work, subject to the limitations in paragraph 4(a), below;
-    rights protecting the extraction, dissemination, use and reuse of data in a Work;
-    database rights (such as those arising under Directive 96/9/EC of the European Parliament and of the Council of 11 March 1996 on the legal protection of databases, and under any national implementation thereof, including any amended or successor version of such directive); and
-    other similar, equivalent or corresponding rights throughout the world based on applicable law or treaty, and any national implementations thereof.
-
-2. Waiver. To the greatest extent permitted by, but not in contravention of, applicable law, Affirmer hereby overtly, fully, permanently, irrevocably and unconditionally waives, abandons, and surrenders all of Affirmer's Copyright and Related Rights and associated claims and causes of action, whether now known or unknown (including existing as well as future claims and causes of action), in the Work (i) in all territories worldwide, (ii) for the maximum duration provided by applicable law or treaty (including future time extensions), (iii) in any current or future medium and for any number of copies, and (iv) for any purpose whatsoever, including without limitation commercial, advertising or promotional purposes (the "Waiver"). Affirmer makes the Waiver for the benefit of each member of the public at large and to the detriment of Affirmer's heirs and successors, fully intending that such Waiver shall not be subject to revocation, rescission, cancellation, termination, or any other legal or equitable action to disrupt the quiet enjoyment of the Work by the public as contemplated by Affirmer's express Statement of Purpose.
-
-3. Public License Fallback. Should any part of the Waiver for any reason be judged legally invalid or ineffective under applicable law, then the Waiver shall be preserved to the maximum extent permitted taking into account Affirmer's express Statement of Purpose. In addition, to the extent the Waiver is so judged Affirmer hereby grants to each affected person a royalty-free, non transferable, non sublicensable, non exclusive, irrevocable and unconditional license to exercise Affirmer's Copyright and Related Rights in the Work (i) in all territories worldwide, (ii) for the maximum duration provided by applicable law or treaty (including future time extensions), (iii) in any current or future medium and for any number of copies, and (iv) for any purpose whatsoever, including without limitation commercial, advertising or promotional purposes (the "License"). The License shall be deemed effective as of the date CC0 was applied by Affirmer to the Work. Should any part of the License for any reason be judged legally invalid or ineffective under applicable law, such partial invalidity or ineffectiveness shall not invalidate the remainder of the License, and in such case Affirmer hereby affirms that he or she will not (i) exercise any of his or her remaining Copyright and Related Rights in the Work or (ii) assert any associated claims and causes of action with respect to the Work, in either case contrary to Affirmer's express Statement of Purpose.
-
-4. Limitations and Disclaimers.
-
-    No trademark or patent rights held by Affirmer are waived, abandoned, surrendered, licensed or otherwise affected by this document.
-    Affirmer offers the Work as-is and makes no representations or warranties of any kind concerning the Work, express, implied, statutory or otherwise, including without limitation warranties of title, merchantability, fitness for a particular purpose, non infringement, or the absence of latent or other defects, accuracy, or the present or absence of errors, whether or not discoverable, all to the greatest extent permissible under applicable law.
-    Affirmer disclaims responsibility for clearing rights of other persons that may apply to the Work or any use thereof, including without limitation any person's Copyright and Related Rights in the Work. Further, Affirmer disclaims responsibility for obtaining any necessary consents, permissions or other rights required for any use of the Work.
-    Affirmer understands and acknowledges that Creative Commons is not a party to this document and has no duty or obligation with respect to this CC0 or use of the Work.
-
-
diff --git a/third_party/unacl-curve25519/METADATA b/third_party/unacl-curve25519/METADATA
deleted file mode 100644
index feb93e5586..0000000000
--- a/third_party/unacl-curve25519/METADATA
+++ /dev/null
@@ -1,25 +0,0 @@
-name: "uNaCl - Curve25519 for ARM Cortex-M0"
-description:
-    "μNaCl – The Networking and Cryptography library for microcontrollers"
-    "Standalone Curve25519 implementation for ARM Cortex-M0, optimized for"
-    "speed. About 3 times faster than compiled code from C."
-
-third_party {
-  url {
-    type: HOMEPAGE
-    value: "https://munacl.cryptojedi.org/curve25519-cortexm0.shtml"
-  }
-  url {
-    type: PACKAGE
-    value: "https://munacl.cryptojedi.org/data/curve25519-cortexm0-20150813.tar.bz2"
-  }
-  version: "20150813"
-  last_upgrade_date { year: 2017 month: 07 day: 20 }
-  license_type: UNENCUMBERED
-  local_modifications:
-    "1. LICENSE file has been created for compliance purposes. "
-    "CC0 1.0 included in original distribution, and added a note about most of "
-    "the code being public domain."
-    "2. Adapted the code for the EC codebase, see git log."
-}
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S
deleted file mode 100644
index d2a467459b..0000000000
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S
+++ /dev/null
@@ -1,181 +0,0 @@
-// Implementation of multiplication of an fe25519 bit value with the curve constant 121666.
-//
-// B. Haase, Endress + Hauser Conducta GmbH & Ko. KG
-// public domain.
-//
-// gnu assembler format.
-//
-// Generated and tested with C++ functions in the test subdirectory.
-//
-// ATTENTION:
-// Not yet tested on target hardware.
-
-
-	.code	16
-	.text
-	.align	2
-
-	.global	fe25519_mpyWith121666_asm
-	.code	16
-	.thumb_func
-	.type	fe25519_mpyWith121666_asm, %function
-
-fe25519_mpyWith121666_asm:
-    push {r4,r5,r6,r7,r14}
-    ldr r7,=56130
-    ldr r2,[r1,#28]
-    lsl r5,r2,#16
-    lsr r6,r2,#16
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    lsl r2,r5,#1
-    lsr r2,r2,#1
-    str r2,[r0,#28]
-    lsr r5,r5,#31
-    lsl r6,r6,#1
-    orr r5,r6
-    mov r6,#19
-    mul r5,r6
-    mov r6,#0
-    ldr r2,[r1,#0]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    str r5,[r0,#0]
-    mov r5,#0
-    ldr r2,[r1,#4]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
-    str r6,[r0,#4]
-    mov r6,#0
-    ldr r2,[r1,#8]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    str r5,[r0,#8]
-    mov r5,#0
-    ldr r2,[r1,#12]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
-    str r6,[r0,#12]
-    mov r6,#0
-    ldr r2,[r1,#16]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    str r5,[r0,#16]
-    mov r5,#0
-    ldr r2,[r1,#20]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r6,r3
-    adc r5,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r6,r2
-    mov r2,#0
-    adc r5,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r6,r2
-    adc r5,r3
-    str r6,[r0,#20]
-    mov r6,#0
-    ldr r2,[r1,#24]
-    lsl r3,r2,#16
-    lsr r4,r2,#16
-    add r5,r3
-    adc r6,r4
-    lsr r3,r2,#16
-    uxth r2,r2
-    mul r2,r7
-    mul r3,r7
-    add r5,r2
-    mov r2,#0
-    adc r6,r2
-    lsl r2,r3,#16
-    lsr r3,r3,#16
-    add r5,r2
-    adc r6,r3
-    str r5,[r0,#24]
-    mov r5,#0
-    ldr r2,[r0,#28]
-    add r6,r2
-    str r6,[r0,#28]
-    pop {r4,r5,r6,r7,r15}
-
-	.size	fe25519_mpyWith121666_asm, .-fe25519_mpyWith121666_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S
deleted file mode 100644
index 366713a7a3..0000000000
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S
+++ /dev/null
@@ -1,1111 +0,0 @@
- .align	2
-	.global	multiply256x256_asm
-	.type	multiply256x256_asm, %function
-multiply256x256_asm:
-	push {r4-r7,lr}
-	mov r3, r8
-	mov r4, r9
-	mov r5, r10
-	mov r6, r11
-	push {r0-r6}
-	mov r12, r0
-	mov r10, r2
-	mov r11, r1
-	mov r0,r2
-	//ldm r0!, {r4,r5,r6,r7}
-	ldm r0!, {r4,r5}
-  add r0,#8
-	ldm r1!, {r2,r3,r6,r7}
-	push {r0,r1}
-	/////////BEGIN LOW PART //////////////////////
-		/////////MUL128/////////////
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		//////////////////////////
-	mov r4, r12
-	stm r4!, {r0,r1}
-	push {r4}
-		push {r0,r1}
-		mov r1, r10
-		mov r10, r2
-		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
-		push {r2, r7}
-		mov r2, r11
-		mov r11, r3
-		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
-		mov r12, r7
-		push {r0, r1}
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		mov r4, r10
-		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
-		mov r10, r2
-		mov r11, r3
-		pop {r2-r5}
-		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		pop {r4, r5}
-		mov r6, r12
-		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2
-		adc r7,r2
-		pop {r2, r3}
-		mov r8, r2
-		mov r9, r3
-		add r2, r0
-		adc r3, r1
-		mov r0, r10
-		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
-	////////END LOW PART/////////////////////
-	pop {r0}
-	stm r0!, {r2,r3}
-	pop {r1,r2}
-	push {r0}
-	push {r4-r7}
-	mov r10, r1
-	mov r11, r2
-	ldm r1!, {r4, r5}
-	ldm r2, {r2, r3}
-	/////////BEGIN HIGH PART////////////////
-		/////////MUL128/////////////
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		push {r0,r1}
-		mov r1, r10
-		mov r10, r2
-		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
-		push {r2, r7}
-		mov r2, r11
-		mov r11, r3
-		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
-		mov r12, r7
-		push {r0, r1}
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		mov r4, r10
-		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
-		mov r10, r2
-		mov r11, r3
-		pop {r2-r5}
-		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		pop {r4, r5}
-		mov r6, r12
-		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2 //0,1
-		adc r7,r2
-		pop {r2, r3}
-		mov r8, r2
-		mov r9, r3
-		add r2, r0
-		adc r3, r1
-		mov r0, r10
-		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
-	////////END HIGH PART/////////////////////
-	mov r0, r8
-	mov r1, r9
-	mov r8, r6
-	mov r9, r7
-	pop {r6, r7}
-	add r0, r6
-	adc r1, r7
-	pop {r6, r7}
-	adc r2, r6
-	adc r3, r7
-	pop {r7}
-	stm r7!, {r0-r3}
-	mov r10, r7
-	eor r0,r0
-	mov r6, r8
-	mov r7, r9
-	adc r4, r0
-	adc r5, r0
-	adc r6, r0
-	adc r7, r0
-	pop {r0,r1,r2}
-	mov r12, r2
-	push {r0, r4-r7}
-	ldm r1, {r0-r7}
-	sub r0, r4
-	sbc r1, r5
-	sbc r2, r6
-	sbc r3, r7
-	eor r4, r4
-	sbc r4, r4
-	eor r0, r4
-	eor r1, r4
-	eor r2, r4
-	eor r3, r4
-	sub r0, r4
-	sbc r1, r4
-	sbc r2, r4
-	sbc r3, r4
-	mov r6, r12
-	mov r12, r4 //carry
-	mov r5, r10
-	stm r5!, {r0-r3}
-	mov r11, r5
-	mov r8, r0
-	mov r9, r1
-	ldm r6, {r0-r7}
-	sub r4, r0
-	sbc r5, r1
-	sbc r6, r2
-	sbc r7, r3
-	eor r0, r0
-	sbc r0, r0
-	eor r4, r0
-	eor r5, r0
-	eor r6, r0
-	eor r7, r0
-	sub r4, r0
-	sbc r5, r0
-	sbc r6, r0
-	sbc r7, r0
-	mov r1, r12
-	eor r0, r1
-	mov r1, r11
-	stm r1!, {r4-r7}
-	push {r0}
-	mov r2, r8
-	mov r3, r9
-	/////////BEGIN MIDDLE PART////////////////
-		/////////MUL128/////////////
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		push {r0,r1}
-		mov r1, r10
-		mov r10, r2
-		ldm r1, {r0, r1, r4, r5}
-		mov r2, r4
-		mov r7, r5
-		sub r2, r0
-		sbc r7, r1
-		sbc r6, r6
-		eor r2, r6
-		eor r7, r6
-		sub r2, r6
-		sbc r7, r6
-		push {r2, r7}
-		mov r2, r11
-		mov r11, r3
-		ldm r2, {r0, r1, r2, r3}
-		sub r0, r2
-		sbc r1, r3
-		sbc r7, r7
-		eor r0, r7
-		eor r1, r7
-		sub r0, r7
-		sbc r1, r7
-		eor r7, r6
-		mov r12, r7
-		push {r0, r1}
-			//MUL64
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		mov r4, r10
-		mov r5, r11
-		eor r6, r6
-		add r0, r4
-		adc r1, r5
-		adc r2, r6
-		adc r3, r6
-		mov r10, r2
-		mov r11, r3
-		pop {r2-r5}
-		push {r0, r1}
-			mov r6, r5
-			mov r1, r2
-			sub r5, r4
-			sbc r0, r0
-			eor r5, r0
-			sub r5, r0
-			sub r1, r3
-			sbc r7, r7
-			eor r1, r7
-			sub r1, r7
-			eor r7, r0
-			mov r9, r1
-			mov r8, r5
-			lsr r1,r4,#16
-			uxth r4,r4
-			mov r0,r4
-			uxth r5,r2
-			lsr r2,#16
-			mul r0,r5//00
-			mul r5,r1//10
-			mul r4,r2//01
-			mul r1,r2//11
-			lsl r2,r4,#16
-			lsr r4,r4,#16
-			add r0,r2
-			adc r1,r4
-			lsl r2,r5,#16
-			lsr r4,r5,#16
-			add r0,r2
-			adc r1,r4
-			lsr r4, r6,#16
-			uxth r6, r6
-			uxth r5, r3
-			lsr r3, r3, #16
-			mov r2, r6
-			mul r2, r5
-			mul r5, r4
-			mul r6, r3
-			mul r3, r4
-			lsl r4,r5,#16
-			lsr r5,r5,#16
-			add r2,r4
-			adc r3,r5
-			lsl r4,r6,#16
-			lsr r5,r6,#16
-			add r2,r4
-			adc r3,r5
-			eor r6, r6
-			add r2, r1
-			adc r3, r6
-			mov r1, r9
-			mov r5, r8
-			mov r8, r0
-			lsr r0, r1,#16
-			uxth r1,r1
-			mov r4,r1
-			lsr r6,r5,#16
-			uxth r5,r5
-			mul r1,r5
-			mul r4,r6
-			mul r5,r0
-			mul r0,r6
-			lsl r6,r4,#16
-			lsr r4,#16
-			add r1,r6
-			adc r0,r4
-			lsl r6,r5,#16
-			lsr r5,#16
-			add r1,r6
-			adc r0,r5
-			eor r1,r7
-			eor r0,r7
-			eor r4, r4
-			asr r7, r7, #1
-			adc r1, r2
-			adc r2, r0
-			adc r7, r4
-			mov r0, r8
-			add r1, r0
-			adc r2, r3
-			adc r3, r7
-		pop {r4, r5}
-		mov r6, r12
-		mov r7, r12
-		eor r0, r6
-		eor r1, r6
-		eor r2, r6
-		eor r3, r6
-		asr r6, r6, #1
-		adc r0, r4
-		adc r1, r5
-		adc r4, r2
-		adc r5, r3
-		eor r2, r2
-		adc r6,r2 //0,1
-		adc r7,r2
-		pop {r2, r3}
-		mov r8, r2
-		mov r9, r3
-		add r2, r0
-		adc r3, r1
-		mov r0, r10
-		mov r1, r11
-		adc r4, r0
-		adc r5, r1
-		adc r6, r0
-		adc r7, r1
-	//////////END MIDDLE PART////////////////
-	pop {r0,r1} //r0,r1
-	mov r12, r0 //negative
-	eor r2, r0
-	eor r3, r0
-	eor r4, r0
-	eor r5, r0
-	eor r6, r0
-	eor r7, r0
-	push {r4-r7}
-	ldm r1!, {r4-r7}
-	mov r11, r1 //reference
-	mov r1, r9
-	eor r1, r0
-	mov r10, r4
-	mov r4, r8
-	asr r0, #1
-	eor r0, r4
-	mov r4, r10
-	adc r0, r4
-	adc r1, r5
-	adc r2, r6
-	adc r3, r7
-	eor r4, r4
-	adc r4, r4
-	mov r10, r4 //carry
-	mov r4, r11
-	ldm r4, {r4-r7}
-	add r0, r4
-	adc r1, r5
-	adc r2, r6
-	adc r3, r7
-	mov r9, r4
-	mov r4, r11
-	stm r4!, {r0-r3}
-	mov r11, r4
-	pop {r0-r3}
-	mov r4, r9
-	adc r4, r0
-	adc r5, r1
-	adc r6, r2
-	adc r7, r3
-	mov r1, #0
-	adc r1, r1
-	mov r0, r10
-	mov r10, r1 //carry
-	asr r0, #1
-	pop {r0-r3}
-	adc r4, r0
-	adc r5, r1
-	adc r6, r2
-	adc r7, r3
-	mov r8, r0
-	mov r0, r11
-	stm r0!, {r4-r7}
-	mov r11, r0
-	mov r0, r8
-	mov r6, r12
-	mov r5, r10
-	eor r4, r4
-	adc r5, r6
-	adc r6, r4
-	add r0, r5
-	adc r1, r6
-	adc r2, r6
-	adc r3, r6
-	mov r7, r11
-	stm r7!, {r0-r3}
-	pop {r3-r6}
-	mov r8, r3
-	mov r9, r4
-	mov r10, r5
-	mov r11, r6
-	pop {r4-r7,pc}
-	bx	lr
-.size	multiply256x256_asm, .-multiply256x256_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S
deleted file mode 100644
index 9a3c29a0f6..0000000000
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S
+++ /dev/null
@@ -1,163 +0,0 @@
-// Implementation of a partial reduction modulo 2^255 - 38.
-//
-// B. Haase, Endress + Hauser Conducta GmbH & Ko. KG
-// public domain.
-//
-// gnu assembler format.
-//
-// Generated and tested with C++ functions in the test subdirectory and on the target.
-//
-
-	.code	16
-
-	.text
-	.align	2
-
-	.global	fe25519_reduceTo256Bits_asm
-	.code	16
-	.thumb_func
-	.type	fe25519_reduceTo256Bits_asm, %function
-
-fe25519_reduceTo256Bits_asm:
-    push {r4,r5,r6,r7,r14}
-    ldr r2,[r1,#60]
-    lsr r3,r2,#16
-    uxth r2,r2
-    mov r7,#38
-    mul r2,r7
-    mul r3,r7
-    ldr r4,[r1,#28]
-    lsr r5,r3,#16
-    lsl r3,r3,#16
-    mov r6,#0
-    add r4,r2
-    adc r5,r6
-    add r4,r3
-    adc r5,r6
-    lsl r2,r4,#1
-    lsr r2,r2,#1
-    str r2,[r0,#28]
-    lsr r4,r4,#31
-    lsl r5,r5,#1
-    orr r4,r5
-    mov r2,#19
-    mul r2,r4
-    ldr r4,[r1,#0]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
-    ldr r4,[r1,#32]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
-    str r2,[r0,#0]
-    ldr r4,[r1,#4]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
-    ldr r4,[r1,#36]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
-    str r3,[r0,#4]
-    ldr r4,[r1,#8]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
-    ldr r4,[r1,#40]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
-    str r2,[r0,#8]
-    ldr r4,[r1,#12]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
-    ldr r4,[r1,#44]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
-    str r3,[r0,#12]
-    ldr r4,[r1,#16]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
-    ldr r4,[r1,#48]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
-    str r2,[r0,#16]
-    ldr r4,[r1,#20]
-    add r3,r4
-    mov r2,#0
-    adc r2,r6
-    ldr r4,[r1,#52]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r3,r4
-    adc r2,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r3,r4
-    adc r2,r5
-    str r3,[r0,#20]
-    ldr r4,[r1,#24]
-    add r2,r4
-    mov r3,#0
-    adc r3,r6
-    ldr r4,[r1,#56]
-    lsr r5,r4,#16
-    uxth r4,r4
-    mul r5,r7
-    mul r4,r7
-    add r2,r4
-    adc r3,r6
-    lsl r4,r5,#16
-    lsr r5,r5,#16
-    add r2,r4
-    adc r3,r5
-    str r2,[r0,#24]
-    ldr r4,[r0,#28]
-    add r4,r3
-    str r4,[r0,#28]
-    pop {r4,r5,r6,r7,r15}
-
-	.size	fe25519_reduceTo256Bits_asm, .-fe25519_reduceTo256Bits_asm
-
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/scalarmult.c b/third_party/unacl-curve25519/core/cortex-m0/curve25519/scalarmult.c
deleted file mode 100644
index 07e2b144e7..0000000000
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/scalarmult.c
+++ /dev/null
@@ -1,588 +0,0 @@
-/*                          =======================
-  ============================ C/C++ HEADER FILE =============================
-                            =======================
-
-    Collection of all required submodules from naclM0 required for curve25519
-    scalar multiplication  (not including randomization, etc.) alone.
-
-    Library naclM0 largely bases on work avrNacl of M. Hutter and P. Schwabe.
-
-    Will compile to the two functions
-
-    int
-    crypto_scalarmult_base_curve25519(
-        unsigned char*       q,
-        const unsigned char* n
-    );
-
-    int
-    crypto_scalarmult_curve25519 (
-        unsigned char*       r,
-        const unsigned char* s,
-        const unsigned char* p
-    );
-
-    Requires inttypes.h header and the four external assembly functions
-
-    extern void
-    fe25519_reduceTo256Bits_asm (
-        fe25519              *res,
-        const UN_512bitValue *in
-    );
-
-    extern void
-    fe25519_mpyWith121666_asm (
-        fe25519*       out,
-        const fe25519* in
-    );
-
-    extern void
-    multiply256x256_asm (
-        UN_512bitValue*       result,
-        const UN_256bitValue* x,
-        const UN_256bitValue* y
-    );
-
-    extern void
-    square256_asm (
-        UN_512bitValue*       result,
-        const UN_256bitValue* x
-    );
-
-    \file scalarmult.c
-
-    \Author B. Haase, Endress + Hauser Conducta GmbH & Co. KG
-
-    Distributed under the conditions of the
-    Creative Commons CC0 1.0 Universal public domain dedication
-  ============================================================================*/
-
-#include "curve25519.h"
-#include "util.h"
-
-typedef uint8_t  uint8;
-typedef uint16_t uint16;
-typedef uint32_t uint32;
-typedef uint64_t uint64;
-typedef uintptr_t uintptr;
-
-typedef int8_t  int8;
-typedef int16_t int16;
-typedef int32_t int32;
-typedef int64_t int64;
-typedef intptr_t intptr;
-
-// Note that it's important to define the unit8 as first union member, so that
-// an array of uint8 may be used as initializer.
-typedef union UN_256bitValue_
-{
-    uint8          as_uint8[32];
-    uint16         as_uint16[16];
-    uint32         as_uint32[8];
-    uint64         as_uint64[4];
-} UN_256bitValue;
-
-// Note that it's important to define the unit8 as first union member, so that
-// an array of uint8 may be used as initializer.
-typedef union UN_512bitValue_
-{
-    uint8          as_uint8[64];
-    uint16         as_uint16[32];
-    uint32         as_uint32[16];
-    uint64         as_uint64[8];
-    UN_256bitValue as_256_bitValue[2];
-} UN_512bitValue;
-
-typedef UN_256bitValue fe25519;
-
-// ****************************************************
-// Assembly functions.
-// ****************************************************
-
-extern void
-fe25519_reduceTo256Bits_asm(
-    fe25519              *res,
-    const UN_512bitValue *in
-);
-
-#define fe25519_mpyWith121666 fe25519_mpyWith121666_asm
-extern void
-fe25519_mpyWith121666_asm (
-    fe25519*       out,
-    const fe25519* in
-);
-
-#define multiply256x256 multiply256x256_asm
-extern void
-multiply256x256(
-    UN_512bitValue*       result,
-    const UN_256bitValue* x,
-    const UN_256bitValue* y
-);
-
-#define square256 square256_asm
-extern void
-square256(
-    UN_512bitValue*       result,
-    const UN_256bitValue* x
-);
-
-// ****************************************************
-// C functions for fe25519
-// ****************************************************
-
-static void
-fe25519_cpy(
-    fe25519*       dest,
-    const fe25519* source
-)
-{
-    memcpy(dest, source, 32);
-}
-
-static void
-fe25519_unpack(
-    fe25519*            out,
-    const unsigned char in[32]
-)
-{
-    memcpy(out, in, 32);
-
-    out->as_uint8[31] &= 0x7f; // make sure that the last bit is cleared.
-}
-
-static void
-fe25519_sub(
-    fe25519*       out,
-    const fe25519* baseValue,
-    const fe25519* valueToSubstract
-)
-{
-    uint16 ctr;
-    int64  accu = 0;
-
-    // First subtract the most significant word, so that we may
-    // reduce the result "on the fly".
-    accu = baseValue->as_uint32[7];
-    accu -= valueToSubstract->as_uint32[7];
-
-    // We always set bit #31, and compensate this by subtracting 1 from the reduction
-    // value.
-    out->as_uint32[7] = ((uint32)accu) | 0x80000000ul;
-
-    accu = 19 * ((int32)(accu >> 31) - 1);
-    // ^ "-1" is the compensation for the "| 0x80000000ul" above.
-    // This choice makes sure, that the result will be positive!
-
-    for (ctr = 0; ctr < 7; ctr += 1)
-    {
-        accu += baseValue->as_uint32[ctr];
-        accu -= valueToSubstract->as_uint32[ctr];
-
-        out->as_uint32[ctr] = (uint32)accu;
-        accu >>= 32;
-    }
-    accu += out->as_uint32[7];
-    out->as_uint32[7] = (uint32)accu;
-}
-
-static void
-fe25519_add(
-    fe25519*       out,
-    const fe25519* baseValue,
-    const fe25519* valueToAdd
-)
-{
-    uint16 ctr = 0;
-    uint64 accu = 0;
-
-    // We first add the most significant word, so that we may reduce
-    // "on the fly".
-    accu = baseValue->as_uint32[7];
-    accu += valueToAdd->as_uint32[7];
-    out->as_uint32[7] = ((uint32)accu) & 0x7ffffffful;
-
-    accu = ((uint32)(accu >> 31)) * 19;
-
-    for (ctr = 0; ctr < 7; ctr += 1)
-    {
-        accu += baseValue->as_uint32[ctr];
-        accu += valueToAdd->as_uint32[ctr];
-
-        out->as_uint32[ctr] = (uint32)accu;
-        accu >>= 32;
-    }
-    accu += out->as_uint32[7];
-    out->as_uint32[7] = (uint32)accu;
-}
-
-static void
-fe25519_mul(
-    fe25519*       result,
-    const fe25519* in1,
-    const fe25519* in2
-)
-{
-    UN_512bitValue tmp;
-
-    multiply256x256(&tmp, in1, in2);
-    fe25519_reduceTo256Bits_asm(result,&tmp);
-}
-
-static void
-fe25519_square(
-    fe25519*       result,
-    const fe25519* in
-)
-{
-    UN_512bitValue tmp;
-
-    square256(&tmp, in);
-    fe25519_reduceTo256Bits_asm(result,&tmp);
-}
-
-static void
-fe25519_reduceCompletely(
-    fe25519* inout
-)
-{
-    uint32 numberOfTimesToSubstractPrime;
-    uint32 initialGuessForNumberOfTimesToSubstractPrime = inout->as_uint32[7] >>
-                                                          31;
-    uint64 accu;
-    uint8  ctr;
-
-    // add one additional 19 to the estimated number of reductions.
-    // Do the calculation without writing back the results to memory.
-    //
-    // The initial guess of required numbers of reductions is based
-    // on bit #32 of the most significant word.
-    // This initial guess may be wrong, since we might have a value
-    // v in the range
-    // 2^255 - 19 <= v < 2^255
-    // . After adding 19 to the value, we will be having the correct
-    // Number of required subtractions.
-    accu = initialGuessForNumberOfTimesToSubstractPrime * 19 + 19;
-
-    for (ctr = 0; ctr < 7; ctr++)
-    {
-        accu += inout->as_uint32[ctr];
-        accu >>= 32;
-    }
-    accu += inout->as_uint32[7];
-
-    numberOfTimesToSubstractPrime = (uint32)(accu >> 31);
-
-    // Do the reduction.
-    accu = numberOfTimesToSubstractPrime * 19;
-
-    for (ctr = 0; ctr < 7; ctr++)
-    {
-        accu += inout->as_uint32[ctr];
-        inout->as_uint32[ctr] = (uint32)accu;
-        accu >>= 32;
-    }
-    accu += inout->as_uint32[7];
-    inout->as_uint32[7] = accu & 0x7ffffffful;
-}
-
-/// We are already using a packed radix 16 representation for fe25519. The real use for this function
-/// is for architectures that use more bits for storing a fe25519 in a representation where multiplication
-/// may be calculated more efficiently.
-/// Here we simply copy the data.
-static void
-fe25519_pack(
-    unsigned char out[32],
-    fe25519*      in
-)
-{
-    fe25519_reduceCompletely(in);
-
-    memcpy(out, in, 32);
-}
-
-// Note, that r and x are allowed to overlap!
-static void
-fe25519_invert_useProvidedScratchBuffers(
-    fe25519*       r,
-    const fe25519* x,
-    fe25519*       t0,
-    fe25519*       t1,
-    fe25519*       t2
-)
-{
-    fe25519 *z11 = r; // store z11 in r (in order to save one temporary).
-    fe25519 *z2_10_0 = t1;
-    fe25519 *z2_50_0 = t2;
-    fe25519 *z2_100_0 = z2_10_0;
-
-    uint8   i;
-
-    {
-         fe25519 *z2 = z2_50_0;
-
-        /* 2 */ fe25519_square(z2, x);
-        /* 4 */ fe25519_square(t0, z2);
-        /* 8 */ fe25519_square(t0, t0);
-        /* 9 */ fe25519_mul(z2_10_0, t0, x);
-        /* 11 */ fe25519_mul(z11, z2_10_0, z2);
-
-        // z2 is dead.
-    }
-
-    /* 22 */ fe25519_square(t0, z11);
-    /* 2^5 - 2^0 = 31 */ fe25519_mul(z2_10_0, t0, z2_10_0);
-
-    /* 2^6 - 2^1 */ fe25519_square(t0, z2_10_0);
-    /* 2^7 - 2^2 */ fe25519_square(t0, t0);
-    /* 2^8 - 2^3 */ fe25519_square(t0, t0);
-    /* 2^9 - 2^4 */ fe25519_square(t0, t0);
-    /* 2^10 - 2^5 */ fe25519_square(t0, t0);
-    /* 2^10 - 2^0 */ fe25519_mul(z2_10_0, t0, z2_10_0);
-
-    /* 2^11 - 2^1 */ fe25519_square(t0, z2_10_0);
-
-    /* 2^20 - 2^10 */ for (i = 1; i < 10; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^20 - 2^0 */ fe25519_mul(z2_50_0, t0, z2_10_0);
-
-    /* 2^21 - 2^1 */ fe25519_square(t0, z2_50_0);
-
-    /* 2^40 - 2^20 */ for (i = 1; i < 20; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^40 - 2^0 */ fe25519_mul(t0, t0, z2_50_0);
-
-    /* 2^41 - 2^1 */ fe25519_square(t0, t0);
-
-    /* 2^50 - 2^10 */ for (i = 1; i < 10; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^50 - 2^0 */ fe25519_mul(z2_50_0, t0, z2_10_0);
-
-    /* 2^51 - 2^1 */ fe25519_square(t0, z2_50_0);
-
-    /* 2^100 - 2^50 */ for (i = 1; i < 50; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^100 - 2^0 */ fe25519_mul(z2_100_0, t0, z2_50_0);
-
-    /* 2^101 - 2^1 */ fe25519_square(t0, z2_100_0);
-
-    /* 2^200 - 2^100 */ for (i = 1; i < 100; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^200 - 2^0 */ fe25519_mul(t0, t0, z2_100_0);
-
-    /* 2^250 - 2^50 */ for (i = 0; i < 50; i ++)
-    {
-        fe25519_square(t0, t0);
-    }
-    /* 2^250 - 2^0 */ fe25519_mul(t0, t0, z2_50_0);
-
-    /* 2^255 - 2^5 */ for (i = 0; i < 5; i ++)
-    {
-         fe25519_square(t0, t0);
-    }
-    /* 2^255 - 21 */ fe25519_mul(r, t0, z11);
-}
-
-static void
-fe25519_setzero(
-    fe25519* out
-)
-{
-    uint8 ctr;
-
-    for (ctr = 0; ctr < 8; ctr++)
-    {
-        out->as_uint32[ctr] = 0;
-    }
-}
-
-static void
-fe25519_setone(
-    fe25519* out
-)
-{
-    uint8 ctr;
-
-    out->as_uint32[0] = 1;
-
-    for (ctr = 1; ctr < 8; ctr++)
-    {
-        out->as_uint32[ctr] = 0;
-    }
-}
-
-static void
-fe25519_cswap(
-    fe25519* in1,
-    fe25519* in2,
-    int      condition
-)
-{
-    int32 mask = condition;
-    uint32 ctr;
-
-    mask = -mask;
-
-    for (ctr = 0; ctr < 8; ctr++)
-    {
-    	uint32 val1 = in1->as_uint32[ctr];
-    	uint32 val2 = in2->as_uint32[ctr];
-    	uint32 temp = val1;
-
-    	val1 ^= mask & (val2 ^ val1);
-    	val2 ^= mask & (val2 ^ temp);
-
-
-    	in1->as_uint32[ctr] = val1;
-    	in2->as_uint32[ctr] = val2;
-    }
-}
-
-// ****************************************************
-// Scalarmultiplication implementation.
-// ****************************************************
-
-typedef struct _ST_curve25519ladderstepWorkingState
-{
-    // The base point in affine coordinates
-    fe25519 x0;
-
-    // The two working points p, q, in projective coordinates. Possibly randomized.
-    fe25519 xp;
-    fe25519 zp;
-    fe25519 xq;
-    fe25519 zq;
-
-    UN_256bitValue s;
-
-    int nextScalarBitToProcess;
-    uint8 previousProcessedBit;
-} ST_curve25519ladderstepWorkingState;
-
-static void
-curve25519_ladderstep(
-    ST_curve25519ladderstepWorkingState* pState
-)
-{
-    // Implements the "ladd-1987-m-3" differential-addition-and-doubling formulas
-    // Source: 1987 Montgomery "Speeding the Pollard and elliptic curve methods of factorization", page 261,
-    //         fifth and sixth displays, plus common-subexpression elimination.
-    //
-    // Notation from the explicit formulas database:
-    // (X2,Z2) corresponds to (xp,zp),
-    // (X3,Z3) corresponds to (xq,zq)
-    // Result (X4,Z4) (X5,Z5) expected in (xp,zp) and (xq,zq)
-    //
-    // A = X2+Z2; AA = A^2; B = X2-Z2; BB = B^2; E = AA-BB; C = X3+Z3; D = X3-Z3;
-    // DA = D*A; CB = C*B; t0 = DA+CB; t1 = t0^2; X5 = Z1*t1; t2 = DA-CB;
-    // t3 = t2^2; Z5 = X1*t3; X4 = AA*BB; t4 = a24*E; t5 = BB+t4; Z4 = E*t5 ;
-    //
-    // Re-Ordered for using less temporaries.
-
-    fe25519 t1, t2;
-
-    fe25519 *b1=&pState->xp; fe25519 *b2=&pState->zp;
-    fe25519 *b3=&pState->xq; fe25519 *b4=&pState->zq;
-
-    fe25519 *b5= &t1; fe25519 *b6=&t2;
-
-    fe25519_add(b5,b1,b2); // A = X2+Z2
-    fe25519_sub(b6,b1,b2); // B = X2-Z2
-    fe25519_add(b1,b3,b4); // C = X3+Z3
-    fe25519_sub(b2,b3,b4); // D = X3-Z3
-    fe25519_mul(b3,b2,b5); // DA= D*A
-    fe25519_mul(b2,b1,b6); // CB= C*B
-    fe25519_add(b1,b2,b3); // T0= DA+CB
-    fe25519_sub(b4,b3,b2); // T2= DA-CB
-    fe25519_square(b3,b1); // X5==T1= T0^2
-    fe25519_square(b1,b4); // T3= t2^2
-    fe25519_mul(b4,b1,&pState->x0); // Z5=X1*t3
-    fe25519_square(b1,b5); // AA=A^2
-    fe25519_square(b5,b6); // BB=B^2
-    fe25519_sub(b2,b1,b5); // E=AA-BB
-    fe25519_mul(b1,b5,b1); // X4= AA*BB
-    fe25519_mpyWith121666 (b6,b2); // T4 = a24*E
-    fe25519_add(b6,b6,b5); // T5 = BB + t4
-    fe25519_mul(b2,b6,b2); // Z4 = E*t5
-}
-
-static void
-curve25519_cswap(
-    ST_curve25519ladderstepWorkingState* state,
-    uint8                                b
-)
-{
-    fe25519_cswap (&state->xp, &state->xq,b);
-    fe25519_cswap (&state->zp, &state->zq,b);
-}
-
-void
-x25519_scalar_mult(
-    uint8_t r[32],
-    const uint8_t s[32],
-    const uint8_t p[32]
-)
-{
-    ST_curve25519ladderstepWorkingState state;
-    unsigned char i;
-
-
-    // Prepare the scalar within the working state buffer.
-    for (i = 0; i < 32; i++)
-    {
-        state.s.as_uint8 [i] = s[i];
-    }
-    state.s.as_uint8 [0] &= 248;
-    state.s.as_uint8 [31] &= 127;
-    state.s.as_uint8 [31] |= 64;
-
-    // Copy the affine x-axis of the base point to the state.
-    fe25519_unpack (&state.x0, p);
-
-    // Prepare the working points within the working state struct.
-
-    fe25519_setone (&state.zq);
-    fe25519_cpy (&state.xq, &state.x0);
-
-    fe25519_setone(&state.xp);
-    fe25519_setzero(&state.zp);
-
-    state.nextScalarBitToProcess = 254;
-
-    state.previousProcessedBit = 0;
-
-    // Process all the bits except for the last three where we explicitly double the result.
-    while (state.nextScalarBitToProcess >= 0)
-    {
-    	uint8 byteNo = state.nextScalarBitToProcess >> 3;
-    	uint8 bitNo = state.nextScalarBitToProcess & 7;
-        uint8 bit;
-        uint8 swap;
-
-        bit = 1 & (state.s.as_uint8 [byteNo] >> bitNo);
-        swap = bit ^ state.previousProcessedBit;
-        state.previousProcessedBit = bit;
-        curve25519_cswap(&state, swap);
-        curve25519_ladderstep(&state);
-        state.nextScalarBitToProcess --;
-    }
-
-    curve25519_cswap(&state,state.previousProcessedBit);
-
-    // optimize for stack usage.
-    fe25519_invert_useProvidedScratchBuffers (&state.zp, &state.zp, &state.xq, &state.zq, &state.x0);
-    fe25519_mul(&state.xp, &state.xp, &state.zp);
-    fe25519_reduceCompletely(&state.xp);
-
-    fe25519_pack (r, &state.xp);
-}
diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S
deleted file mode 100644
index b62121adb7..0000000000
--- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/sqr.S
+++ /dev/null
@@ -1,1164 +0,0 @@
-// Author: Ana Helena Sánchez, Björn Haase (second implementation).
-//
-// public domain
-//
-
- .align	2
-	.global	square256_asm
-	.type	square256_asm, %function
-square256_asm:
-// ######################
-// ASM Square 256 refined karatsuba:
-// ######################
- // sqr 256 Refined Karatsuba
- // pInput in r1
- // pResult in r0
- // adheres to arm eabi calling convention.
-    push {r1,r4,r5,r6,r7,r14}
-    .syntax unified
-    mov r3,r8
-    mov r4,r9
-    mov r5,r10
-    mov r6,r11
-    mov r7,r12
-    .syntax divided
-    push {r3,r4,r5,r6,r7}
-    .syntax unified
-    mov r14,r0
-    .syntax divided
-    ldm r1!,{r4,r5,r6,r7}
- // sqr 128 Refined Karatsuba
- // Input in r4 ... r7
- // Result in r0 ... r7
- // clobbers all registers except for r14
-    .syntax unified
-    mov r0,r4
-    mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
-    mov r8,r0
-    mov r9,r1
-    mov r10,r6
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r4,r5
- // Result in r0,r1,r2,r3
- // Clobbers: r4-r6
- // START: sqr 32
- // Input operand in r4
- // Result in r0 ,r1
- // Clobbers: r2, r3
-    uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
-    mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
- // End: sqr 32
- // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
- // START: sqr 32
- // Input operand in r5
- // Result in r2 ,r3
- // Clobbers: r5, r6
-    uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
-    mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
- // End: sqr 32
- // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
- // START: sqr 32
- // Input operand in r4
- // Result in r4 ,r5
- // Clobbers: r1, r6
-    lsr r5,r4,#16
-    uxth r4,r4
-    .syntax unified
-    mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
- // End: sqr 32
- // Result in r4 ,r5
-    .syntax unified
-    mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
-    mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r0,r1,r2,r3
- // Leaves r6 zero.
-    .syntax unified
-    mov r6,r10
-    mov r10,r0
-    mov r11,r1
-    mov r12,r2
-    mov r1,r3
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r6,r7
- // Result in r2,r3,r4,r5
- // Clobbers: r0,r7,r6
- // START: sqr 32
- // Input operand in r6
- // Result in r2 ,r3
- // Clobbers: r4, r5
-    uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
-    mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
- // End: sqr 32
- // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
- // START: sqr 32
- // Input operand in r7
- // Result in r4 ,r5
- // Clobbers: r0, r7
-    uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
-    mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
- // End: sqr 32
- // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
- // START: sqr 32
- // Input operand in r6
- // Result in r7 ,r0
- // Clobbers: r6, r3
-    uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
-    mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
- // End: sqr 32
- // Result in r7 ,r0
-    .syntax unified
-    mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
-    mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r2,r3,r4,r5
- // Leaves r6 zero.
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
-    mov r12,r2
-    mov r2,r8
-    mov r8,r3
-    mov r3,r9
-    mov r9,r4
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r2,r3
- // Result in r6,r7,r0,r1
- // Clobbers: r2,r3,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r6 ,r7
- // Clobbers: r0, r1
-    uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
-    mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
- // End: sqr 32
- // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
- // START: sqr 32
- // Input operand in r3
- // Result in r0 ,r1
- // Clobbers: r3, r4
-    uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
-    mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
- // End: sqr 32
- // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r3 ,r4
- // Clobbers: r2, r7
-    uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
-    mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
- // End: sqr 32
- // Result in r3 ,r4
-    .syntax unified
-    mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
-    mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
- // END: sqr 64 Refined Karatsuba
- // Result in r6,r7,r0,r1
- // Returns r4 as zero.
-    .syntax unified
-    mov r2,r12
-    mov r3,r8
-    mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
-    mov r6,r4
-    mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
-    mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
-    mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
- // END: sqr 128 Refined Karatsuba
- // Result in r0 ... r7
-    push {r4,r5,r6,r7}
-    .syntax unified
-    mov r4,r14
-    .syntax divided
-    stm r4!,{r0,r1,r2,r3}
-    ldr r4,[SP,#36]
-    add r4,#16
-    ldm r4,{r4,r5,r6,r7}
- // sqr 128 Refined Karatsuba
- // Input in r4 ... r7
- // Result in r0 ... r7
- // clobbers all registers except for r14
-    .syntax unified
-    mov r0,r4
-    mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
-    mov r8,r0
-    mov r9,r1
-    mov r10,r6
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r4,r5
- // Result in r0,r1,r2,r3
- // Clobbers: r4-r6
- // START: sqr 32
- // Input operand in r4
- // Result in r0 ,r1
- // Clobbers: r2, r3
-    uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
-    mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
- // End: sqr 32
- // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
- // START: sqr 32
- // Input operand in r5
- // Result in r2 ,r3
- // Clobbers: r5, r6
-    uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
-    mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
- // End: sqr 32
- // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
- // START: sqr 32
- // Input operand in r4
- // Result in r4 ,r5
- // Clobbers: r1, r6
-    lsr r5,r4,#16
-    uxth r4,r4
-    .syntax unified
-    mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
- // End: sqr 32
- // Result in r4 ,r5
-    .syntax unified
-    mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
-    mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r0,r1,r2,r3
- // Leaves r6 zero.
-    .syntax unified
-    mov r6,r10
-    mov r10,r0
-    mov r11,r1
-    mov r12,r2
-    mov r1,r3
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r6,r7
- // Result in r2,r3,r4,r5
- // Clobbers: r0,r7,r6
- // START: sqr 32
- // Input operand in r6
- // Result in r2 ,r3
- // Clobbers: r4, r5
-    uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
-    mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
- // End: sqr 32
- // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
- // START: sqr 32
- // Input operand in r7
- // Result in r4 ,r5
- // Clobbers: r0, r7
-    uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
-    mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
- // End: sqr 32
- // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
- // START: sqr 32
- // Input operand in r6
- // Result in r7 ,r0
- // Clobbers: r6, r3
-    uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
-    mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
- // End: sqr 32
- // Result in r7 ,r0
-    .syntax unified
-    mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
-    mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r2,r3,r4,r5
- // Leaves r6 zero.
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
-    mov r12,r2
-    mov r2,r8
-    mov r8,r3
-    mov r3,r9
-    mov r9,r4
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r2,r3
- // Result in r6,r7,r0,r1
- // Clobbers: r2,r3,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r6 ,r7
- // Clobbers: r0, r1
-    uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
-    mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
- // End: sqr 32
- // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
- // START: sqr 32
- // Input operand in r3
- // Result in r0 ,r1
- // Clobbers: r3, r4
-    uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
-    mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
- // End: sqr 32
- // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r3 ,r4
- // Clobbers: r2, r7
-    uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
-    mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
- // End: sqr 32
- // Result in r3 ,r4
-    .syntax unified
-    mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
-    mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
- // END: sqr 64 Refined Karatsuba
- // Result in r6,r7,r0,r1
- // Returns r4 as zero.
-    .syntax unified
-    mov r2,r12
-    mov r3,r8
-    mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
-    mov r6,r4
-    mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
-    mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
-    mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
- // END: sqr 128 Refined Karatsuba
- // Result in r0 ... r7
-    .syntax unified
-    mov r8,r4
-    mov r9,r5
-    mov r10,r6
-    mov r11,r7
-    .syntax divided
-    pop {r4,r5,r6,r7}
-    add r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    .syntax unified
-    mov r4,r8
-    mov r5,r9
-    mov r6,r10
-    mov r7,r11
-    mov r8,r0
-    .syntax divided
-    mov r0,#0
-    adc r4,r0
-    adc r5,r0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
-    mov r0,r8
-    .syntax divided
-    push {r0,r1,r2,r3,r4,r5,r6,r7}
-    ldr r4,[SP,#52]
-    ldm r4,{r0,r1,r2,r3,r4,r5,r6,r7}
-    sub r4,r0
-    sbc r5,r1
-    sbc r6,r2
-    sbc r7,r3
-    sbc r0,r0
-    eor r4,r0
-    eor r5,r0
-    eor r6,r0
-    eor r7,r0
-    sub r4,r0
-    sbc r5,r0
-    sbc r6,r0
-    sbc r7,r0
- // sqr 128 Refined Karatsuba
- // Input in r4 ... r7
- // Result in r0 ... r7
- // clobbers all registers except for r14
-    .syntax unified
-    mov r0,r4
-    mov r1,r5
-    .syntax divided
-    sub r0,r6
-    sbc r1,r7
-    sbc r2,r2
-    eor r0,r2
-    eor r1,r2
-    sub r0,r2
-    sbc r1,r2
-    .syntax unified
-    mov r8,r0
-    mov r9,r1
-    mov r10,r6
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r4,r5
- // Result in r0,r1,r2,r3
- // Clobbers: r4-r6
- // START: sqr 32
- // Input operand in r4
- // Result in r0 ,r1
- // Clobbers: r2, r3
-    uxth r0,r4
-    lsr r1,r4,#16
-    .syntax unified
-    mov r2,r0
-    .syntax divided
-    mul r2,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r3,r2,#15
-    lsl r2,r2,#17
-    add r0,r2
-    adc r1,r3
- // End: sqr 32
- // Result in r0 ,r1
-    sub r4,r5
-    sbc r6,r6
-    eor r4,r6
-    sub r4,r6
- // START: sqr 32
- // Input operand in r5
- // Result in r2 ,r3
- // Clobbers: r5, r6
-    uxth r2,r5
-    lsr r3,r5,#16
-    .syntax unified
-    mov r5,r2
-    .syntax divided
-    mul r5,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r6,r5,#15
-    lsl r5,r5,#17
-    add r2,r5
-    adc r3,r6
- // End: sqr 32
- // Result in r2 ,r3
-    mov r6,#0
-    add r2,r1
-    adc r3,r6
- // START: sqr 32
- // Input operand in r4
- // Result in r4 ,r5
- // Clobbers: r1, r6
-    lsr r5,r4,#16
-    uxth r4,r4
-    .syntax unified
-    mov r1,r4
-    .syntax divided
-    mul r1,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r6,r1,#15
-    lsl r1,r1,#17
-    add r4,r1
-    adc r5,r6
- // End: sqr 32
- // Result in r4 ,r5
-    .syntax unified
-    mov r1,r2
-    .syntax divided
-    sub r1,r4
-    sbc r2,r5
-    .syntax unified
-    mov r5,r3
-    .syntax divided
-    mov r6,#0
-    sbc r3,r6
-    add r1,r0
-    adc r2,r5
-    adc r3,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r0,r1,r2,r3
- // Leaves r6 zero.
-    .syntax unified
-    mov r6,r10
-    mov r10,r0
-    mov r11,r1
-    mov r12,r2
-    mov r1,r3
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r6,r7
- // Result in r2,r3,r4,r5
- // Clobbers: r0,r7,r6
- // START: sqr 32
- // Input operand in r6
- // Result in r2 ,r3
- // Clobbers: r4, r5
-    uxth r2,r6
-    lsr r3,r6,#16
-    .syntax unified
-    mov r4,r2
-    .syntax divided
-    mul r4,r3
-    mul r2,r2
-    mul r3,r3
-    lsr r5,r4,#15
-    lsl r4,r4,#17
-    add r2,r4
-    adc r3,r5
- // End: sqr 32
- // Result in r2 ,r3
-    sub r6,r7
-    sbc r4,r4
-    eor r6,r4
-    sub r6,r4
- // START: sqr 32
- // Input operand in r7
- // Result in r4 ,r5
- // Clobbers: r0, r7
-    uxth r4,r7
-    lsr r5,r7,#16
-    .syntax unified
-    mov r0,r4
-    .syntax divided
-    mul r0,r5
-    mul r4,r4
-    mul r5,r5
-    lsr r7,r0,#15
-    lsl r0,r0,#17
-    add r4,r0
-    adc r5,r7
- // End: sqr 32
- // Result in r4 ,r5
-    mov r7,#0
-    add r4,r3
-    adc r5,r7
- // START: sqr 32
- // Input operand in r6
- // Result in r7 ,r0
- // Clobbers: r6, r3
-    uxth r7,r6
-    lsr r0,r6,#16
-    .syntax unified
-    mov r6,r7
-    .syntax divided
-    mul r6,r0
-    mul r7,r7
-    mul r0,r0
-    lsr r3,r6,#15
-    lsl r6,r6,#17
-    add r7,r6
-    adc r0,r3
- // End: sqr 32
- // Result in r7 ,r0
-    .syntax unified
-    mov r3,r4
-    .syntax divided
-    sub r3,r7
-    sbc r4,r0
-    .syntax unified
-    mov r0,r5
-    .syntax divided
-    mov r6,#0
-    sbc r5,r6
-    add r3,r2
-    adc r4,r0
-    adc r5,r6
- // END: sqr 64 Refined Karatsuba
- // Result in r2,r3,r4,r5
- // Leaves r6 zero.
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    add r2,r0
-    adc r3,r1
-    adc r4,r6
-    adc r5,r6
-    .syntax unified
-    mov r12,r2
-    mov r2,r8
-    mov r8,r3
-    mov r3,r9
-    mov r9,r4
-    .syntax divided
- // START: sqr 64 Refined Karatsuba
- // Input operands in r2,r3
- // Result in r6,r7,r0,r1
- // Clobbers: r2,r3,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r6 ,r7
- // Clobbers: r0, r1
-    uxth r6,r2
-    lsr r7,r2,#16
-    .syntax unified
-    mov r0,r6
-    .syntax divided
-    mul r0,r7
-    mul r6,r6
-    mul r7,r7
-    lsr r1,r0,#15
-    lsl r0,r0,#17
-    add r6,r0
-    adc r7,r1
- // End: sqr 32
- // Result in r6 ,r7
-    sub r2,r3
-    sbc r4,r4
-    eor r2,r4
-    sub r2,r4
- // START: sqr 32
- // Input operand in r3
- // Result in r0 ,r1
- // Clobbers: r3, r4
-    uxth r0,r3
-    lsr r1,r3,#16
-    .syntax unified
-    mov r3,r0
-    .syntax divided
-    mul r3,r1
-    mul r0,r0
-    mul r1,r1
-    lsr r4,r3,#15
-    lsl r3,r3,#17
-    add r0,r3
-    adc r1,r4
- // End: sqr 32
- // Result in r0 ,r1
-    mov r4,#0
-    add r0,r7
-    adc r1,r4
- // START: sqr 32
- // Input operand in r2
- // Result in r3 ,r4
- // Clobbers: r2, r7
-    uxth r3,r2
-    lsr r4,r2,#16
-    .syntax unified
-    mov r2,r3
-    .syntax divided
-    mul r2,r4
-    mul r3,r3
-    mul r4,r4
-    lsr r7,r2,#15
-    lsl r2,r2,#17
-    add r3,r2
-    adc r4,r7
- // End: sqr 32
- // Result in r3 ,r4
-    .syntax unified
-    mov r7,r0
-    .syntax divided
-    sub r7,r3
-    sbc r0,r4
-    .syntax unified
-    mov r2,r1
-    .syntax divided
-    mov r4,#0
-    sbc r1,r4
-    add r7,r6
-    adc r0,r2
-    adc r1,r4
- // END: sqr 64 Refined Karatsuba
- // Result in r6,r7,r0,r1
- // Returns r4 as zero.
-    .syntax unified
-    mov r2,r12
-    mov r3,r8
-    mov r4,r9
-    .syntax divided
-    sub r2,r6
-    sbc r3,r7
-    .syntax unified
-    mov r6,r4
-    mov r7,r5
-    .syntax divided
-    sbc r4,r0
-    sbc r5,r1
-    mov r0,#0
-    sbc r6,r0
-    sbc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
-    add r2,r0
-    .syntax unified
-    mov r1,r11
-    .syntax divided
-    adc r3,r1
-    .syntax unified
-    mov r0,r12
-    .syntax divided
-    adc r4,r0
-    .syntax unified
-    mov r0,r8
-    .syntax divided
-    adc r5,r0
-    mov r0,#0
-    adc r6,r0
-    adc r7,r0
-    .syntax unified
-    mov r0,r10
-    .syntax divided
- // END: sqr 128 Refined Karatsuba
- // Result in r0 ... r7
-    mvn r0,r0
-    mvn r1,r1
-    mvn r2,r2
-    mvn r3,r3
-    mvn r4,r4
-    mvn r5,r5
-    mvn r6,r6
-    mvn r7,r7
-    .syntax unified
-    mov r8,r4
-    mov r9,r5
-    mov r10,r6
-    mov r11,r7
-    .syntax divided
-    mov r4,#143
-    asr r4,r4,#1
-    pop {r4,r5,r6,r7}
-    adc r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    .syntax unified
-    mov r12,r4
-    .syntax divided
-    mov r4,#16
-    add r4,r14
-    stm r4!,{r0,r1,r2,r3}
-    .syntax unified
-    mov r4,r12
-    mov r0,r8
-    .syntax divided
-    adc r0,r4
-    .syntax unified
-    mov r8,r0
-    mov r1,r9
-    .syntax divided
-    adc r1,r5
-    .syntax unified
-    mov r9,r1
-    mov r2,r10
-    .syntax divided
-    adc r2,r6
-    .syntax unified
-    mov r10,r2
-    mov r3,r11
-    .syntax divided
-    adc r3,r7
-    .syntax unified
-    mov r11,r3
-    .syntax divided
-    mov r0,#0
-    adc r0,r0
-    .syntax unified
-    mov r12,r0
-    mov r0,r14
-    .syntax divided
-    ldm r0,{r0,r1,r2,r3,r4,r5,r6,r7}
-    add r0,r4
-    adc r1,r5
-    adc r2,r6
-    adc r3,r7
-    mov r4,#16
-    add r4,r14
-    stm r4!,{r0,r1,r2,r3}
-    .syntax unified
-    mov r14,r4
-    mov r0,r13
-    .syntax divided
-    ldm r0!,{r4,r5,r6,r7}
-    .syntax unified
-    mov r1,r8
-    .syntax divided
-    adc r4,r1
-    .syntax unified
-    mov r1,r9
-    .syntax divided
-    adc r5,r1
-    .syntax unified
-    mov r1,r10
-    .syntax divided
-    adc r6,r1
-    .syntax unified
-    mov r1,r11
-    .syntax divided
-    adc r7,r1
-    .syntax unified
-    mov r0,r14
-    .syntax divided
-    stm r0!,{r4,r5,r6,r7}
-    pop {r4,r5,r6,r7}
-    .syntax unified
-    mov r1,r12
-    .syntax divided
-    mov r2,#0
-    mvn r2,r2
-    adc r1,r2
-    asr r2,r1,#4
-    add r4,r1
-    adc r5,r2
-    adc r6,r2
-    adc r7,r2
-    stm r0!,{r4,r5,r6,r7}
-    pop {r3,r4,r5,r6,r7}
-    .syntax unified
-    mov r8,r3
-    mov r9,r4
-    mov r10,r5
-    mov r11,r6
-    mov r12,r7
-    .syntax divided
-    pop {r0,r4,r5,r6,r7,r15}
-//Cycle Count ASM-Version of 256 sqr (Refined Karatsuba) (Cortex M0): 793 (697 instructions).
-	.size	square256_asm, .-square256_asm
diff --git a/util/battery_temp b/util/battery_temp
deleted file mode 100755
index c69e3d4778..0000000000
--- a/util/battery_temp
+++ /dev/null
@@ -1,56 +0,0 @@
-#!/bin/bash
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Description: Read and output temperature of device's primary battery in
-# degrees Celsius.
-#
-# TODO(tbroch) revisit for detachables with multiple batteries.
-
-# Read battery temperature from sysfs power_supply and return in degC.
-batt_temp_sysfs() {
-    local temp=""
-
-    for psdir in /sys/class/power_supply/* ; do
-        if [[ -e "${psdir}/temp" ]] ; then
-            pstype=$(cat $psdir/type)
-            if [[ "${pstype}" -eq "Battery" ]] ; then
-                temp=$(bc <<< "scale=2; $(cat ${psdir}/temp)/10")
-                break
-            fi
-        fi
-    done
-    echo ${temp}
-}
-
-# Read battery temperature from EC and return in degC.
-batt_temp_ec() {
-    local temp=""
-
-    local sensor_str=$(ectool tempsinfo all 2>/dev/null | grep Battery)
-    if [[ $? -eq 0 ]] && [[ ! -z "${sensor_str}" ]] ; then
-        local idx=$(echo ${sensor_str} | cut -d: -f1)
-        # ectool temps <idx> looks like 'Reading temperature...298 K'
-        temp_str=$(ectool temps ${idx})
-        temp="${temp_str//[!0-9]/}"
-        if [[ -z "${temp}" ]] ; then
-            temp="error"
-        else
-            temp=$(bc <<< "scale=2; ${temp} - 273.15")
-        fi
-    fi
-    echo $temp
-}
-
-# Main
-TEMP_DEGC=$(batt_temp_sysfs)
-if [[ -z "${TEMP_DEGC}" ]] ; then
-    TEMP_DEGC=$(batt_temp_ec)
-fi
-
-if [[ -z "${TEMP_DEGC}" ]] ; then
-    echo "unknown"
-else
-    echo ${TEMP_DEGC}
-fi
diff --git a/util/bin2h.sh b/util/bin2h.sh
deleted file mode 100755
index 1507bc4004..0000000000
--- a/util/bin2h.sh
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# This script converts input binary blob into output .h file,
-#
-# The three command line arguments are:
-#
-#  - name of the variable to define in the output .h file
-#  - input binary blob to be converted to hex ASCII
-#  - name of the output file
-#
-# The output file contains a C #define statement assigning the variable to hex
-# dump of the input file.
-#
-# This script is supposed to be invoked from the make file, no command line
-# argument verification is done.
-
-# Make sure the user is alerted if not enough command line arguments are
-# supplied.
-set -u
-
-variable_name="${1}"
-input_file="${2}"
-output_file="${3}"
-
-key_dump="$(od -An -tx1 -w8 ${input_file} | \
-    sed 's/^ /\t0x/;s/ /, 0x/g;s/$/, \\/')"
-
-cat > ${output_file} <<EOF
-/*
- * This is a generated file, do not edit.
- */
-
-#define ${variable_name} { \\
-${key_dump}
-}
-
-EOF
diff --git a/util/build.mk b/util/build.mk
deleted file mode 100644
index 9f9430a3b4..0000000000
--- a/util/build.mk
+++ /dev/null
@@ -1,112 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Host tools build
-#
-
-# See Makefile for description.
-host-util-bin-y += ectool lbplay stm32mon ec_sb_firmware_update lbcc \
-	ec_parse_panicinfo cbi-util iteflash
-build-util-art-y += util/export_taskinfo.so
-
-build-util-bin-$(CHIP_NPCX) += ecst
-build-util-bin-$(BOARD_NOCTURNE_FP) += ectool_servo
-
-host-util-bin-y += uartupdatetool
-uartupdatetool-objs=uut/main.o uut/cmd.o uut/opr.o uut/l_com_port.o \
-	uut/lib_crc.o
-$(out)/util/uartupdatetool: HOST_CFLAGS+=-Iutil/
-
-# If the util/ directory in the private repo is symlinked into util/private,
-# we want to build host-side tools from it, too.
-ifneq ("$(wildcard util/private/build.mk)","")
-include util/private/build.mk
-endif
-
-comm-objs=$(util-lock-objs:%=lock/%) comm-host.o comm-dev.o
-comm-objs+=comm-lpc.o comm-i2c.o misc_util.o
-
-iteflash-objs = iteflash.o usb_if.o
-ectool-objs=ectool.o ectool_keyscan.o ec_flash.o ec_panicinfo.o $(comm-objs)
-ectool-objs+=../common/crc.o
-ectool_servo-objs=$(ectool-objs) comm-servo-spi.o
-ec_sb_firmware_update-objs=ec_sb_firmware_update.o $(comm-objs) misc_util.o
-ec_sb_firmware_update-objs+=powerd_lock.o
-lbplay-objs=lbplay.o $(comm-objs)
-
-util/ectool.c: $(out)/ec_version.h
-
-ec_parse_panicinfo-objs=ec_parse_panicinfo.o ec_panicinfo.o
-
-# USB type-C Vendor Information File generation
-ifeq ($(CONFIG_USB_POWER_DELIVERY),y)
-build-util-bin-y+=genvif
-build-util-art-y+=$(BOARD)_vif.xml
-
-# usb_pd_policy.c can be in baseboard, or board, or both.
-genvif-pd-srcs=$(sort $(wildcard $(BASEDIR)/usb_pd_policy.c \
-			board/$(BOARD)/usb_pd_policy.c))
-genvif-pd-objs=$(genvif-pd-srcs:%.c=$(out)/util/%.o)
-genvif-pd-objs += $(out)/common/usb_common.o
-deps-$(CONFIG_USB_POWER_DELIVERY) += $(genvif-pd-objs:%.o=%.o.d)
-
-$(out)/util/genvif: $(genvif-pd-objs) util/genvif.h board/$(BOARD)/board.h \
-			include/usb_pd.h include/usb_pd_tcpm.h
-$(out)/util/genvif: BUILD_LDFLAGS+=$(genvif-pd-objs) -flto
-
-STANDALONE_FLAGS=-ffreestanding -fno-builtin -nostdinc \
-			-Ibuiltin/ -D"__keep= " -DVIF_BUILD=$(EMPTY)
-
-$(out)/util/%/usb_pd_policy.o: %/usb_pd_policy.c
-	-@ mkdir -p $(@D)
-	$(call quiet,c_to_vif,BUILDCC)
-$(out)/common/usb_common.o: common/usb_common.c
-	-@ mkdir -p $(@D)
-	$(call quiet,c_to_vif,BUILDCC)
-endif # CONFIG_USB_POWER_DELIVERY
-
-ifneq ($(CONFIG_BOOTBLOCK),)
-build-util-bin-y += gen_emmc_transfer_data
-
-# Bootblock is only packed in RO image.
-$(out)/util/gen_emmc_transfer_data: BUILD_LDFLAGS += -DSECTION_IS_RO=$(EMPTY)
-endif # CONFIG_BOOTBLOCK
-
-ifneq ($(CONFIG_IPI),)
-build-util-bin-y += gen_ipi_table
-
-$(out)/util/gen_ipi_table: board/$(BOARD)/board.h
-$(out)/ipi_table_gen.inc: $(out)/util/gen_ipi_table
-	$(call quiet,ipi_table,IPITBL )
-endif
-
-ifneq ($(CONFIG_TOUCHPAD_HASH_FW),)
-build-util-bin-y += gen_touchpad_hash
-
-# Assume RW section (touchpad FW must be identical for both RO+RW)
-$(out)/util/gen_touchpad_hash: BUILD_LDFLAGS += -DSECTION_IS_RW=$(EMPTY)
-
-HOST_OPENSSL_CFLAGS := $(shell $(HOST_PKG_CONFIG) --cflags openssl)
-HOST_OPENSSL_LDFLAGS := $(shell $(HOST_PKG_CONFIG) --libs openssl)
-
-$(out)/util/gen_touchpad_hash: BUILD_CFLAGS += $(HOST_OPENSSL_CFLAGS)
-$(out)/util/gen_touchpad_hash: BUILD_LDFLAGS += $(HOST_OPENSSL_LDFLAGS)
-
-deps-y += $(out)/util/gen_touchpad_hash.d
-endif # CONFIG_TOUCHPAD_VIRTUAL_OFF
-
-cbi-util-objs=../common/crc8.o ../common/cbi.o
-
-$(out)/util/export_taskinfo.so: $(out)/util/export_taskinfo_ro.o \
-			$(out)/util/export_taskinfo_rw.o
-	$(call quiet,link_taskinfo,BUILDLD)
-
-$(out)/util/export_taskinfo_ro.o: util/export_taskinfo.c
-	$(call quiet,c_to_taskinfo,BUILDCC,RO)
-
-$(out)/util/export_taskinfo_rw.o: util/export_taskinfo.c
-	$(call quiet,c_to_taskinfo,BUILDCC,RW)
-
-deps-y += $(out)/util/export_taskinfo_ro.o.d $(out)/util/export_taskinfo_rw.o.d
diff --git a/util/build_allowed.sh b/util/build_allowed.sh
deleted file mode 100755
index 6ef4fe03a5..0000000000
--- a/util/build_allowed.sh
+++ /dev/null
@@ -1,83 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Taken from U-Boot and modified.
-
-# This grubby little script creates the list of allowed configurations. This
-# file contains all the config options which are allowed to be used outside
-# Kconfig. Please do not add things to the list. Instead, add your new option to
-# Kconfig.
-#
-# Usage:
-#   build_allowed.sh [-u]
-#
-#   -u : Update the existing allowed file
-
-export LC_ALL=C LC_COLLATE=C
-
-# Current list of allowed ad-hoc CONFIGs
-allowed=util/config_allowed.txt
-
-[ "$1" == "-u" ] && update=1
-
-tmp=$(mktemp -d)
-kconfigs="${tmp}/kconfigs"
-
-#
-# Look for the CONFIG options, excluding those in Kconfig and defconfig files.
-#
-git grep CONFIG_ | \
-	grep -E -vi "(Kconfig:|defconfig:|README|\.py|\.pl:)" \
-	| tr ' \t' '\n' \
-	| sed -n 's/^\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' \
-	| sort | uniq >"${tmp}/allowed.tmp1";
-
-# We need a list of the valid Kconfig options to exclude these from the allowed
-# list.
-find . -type f -name "Kconfig*" -exec cat {} \; | sed -n -e \
-	's/^\s*\(config\|menuconfig\) *\([A-Za-z0-9_]*\)$/CONFIG_\2/p' \
-	| sort | uniq > "${kconfigs}"
-
-# Most Kconfigs follow the pattern of CONFIG_PLATFORM_EC_*.  Strip PLATFORM_EC_
-# from the config name to match the cros-ec namespace.
-sed -e 's/^CONFIG_PLATFORM_EC_/CONFIG_/p' "${kconfigs}" | sort | uniq \
-	> "${tmp}/allowed.tmp2"
-
-# Use only the options that are present in the first file but not the second.
-# These comprise new ad-hoc CONFIG options.
-comm -23 "${tmp}/allowed.tmp1" "${tmp}/allowed.tmp2" \
-	| sort | uniq >"${tmp}/allowed.tmp3"
-
-# If ${allowed} already exists, take the intersection of the current
-# list and the new one.  We do not want to increase the allowed options.
-if [ -r "${allowed}" ]; then
-	comm -12 "${tmp}/allowed.tmp3" "${allowed}" > "${tmp}/allowed.tmp4"
-
-	# Find any ad-hoc configs that now have Kconfig options
-	comm -13 "${tmp}/allowed.tmp4" "${allowed}" > "${tmp}/allowed.tmp5"
-	if [ -n "${update}" ]; then
-		echo >&2 "Removing these CONFIG options from the allowed list:"
-		comm -13 "${tmp}/allowed.tmp4" "${allowed}"
-		mv "${tmp}/allowed.tmp4" "${allowed}"
-	elif [ -s "${tmp}/allowed.tmp5" ]; then
-		echo >&2 "Congratulations! The following options are now in"
-		echo >&2 "Kconfig:"
-		cat "${tmp}/allowed.tmp5"
-		echo >&2
-		echo >&2 "Please run this to update the list of allowed ad-hoc"
-		echo >&2 "CONFIGs and include this update in your CL."
-		echo >&2
-		echo -e >&2 "\t./util/build_allowed.sh -u"
-	fi
-else
-	# If there is no file yet, add one. This allows it to be regenerated
-	# from scratch if needed.
-	mv "${tmp}/allowed.tmp3" "${allowed}"
-fi
-
-rm -rf "${tmp}"
-
-unset LC_ALL LC_COLLATE
diff --git a/util/cbi-util.c b/util/cbi-util.c
deleted file mode 100644
index fe0c4c2bce..0000000000
--- a/util/cbi-util.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Cros Board Info utility
- */
-
-#include <compile_time_macros.h>
-#include <errno.h>
-#include <dirent.h>
-#include <getopt.h>
-#include <limits.h>
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <unistd.h>
-
-#include "cros_board_info.h"
-#include "crc8.h"
-
-#define ARGS_MASK_BOARD_VERSION		BIT(0)
-#define ARGS_MASK_FILENAME		BIT(1)
-#define ARGS_MASK_SIZE			BIT(2)
-#define ARGS_MASK_SKU_ID		BIT(3)
-
-/* TODO: Set it by macro */
-const char cmd_name[] = "cbi-util";
-
-/* Command line options */
-enum {
-	OPT_FILENAME,
-	OPT_BOARD_VERSION,
-	OPT_OEM_ID,
-	OPT_SKU_ID,
-	OPT_DRAM_PART_NUM,
-	OPT_OEM_NAME,
-	OPT_MODEL_ID,
-	OPT_FW_CONFIG,
-	OPT_PCB_SUPPLIER,
-	OPT_SSFC,
-	OPT_REWORK_ID,
-	OPT_SIZE,
-	OPT_ERASE_BYTE,
-	OPT_SHOW_ALL,
-	OPT_HELP,
-};
-
-static const struct option opts_create[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"board_version", 1, 0, OPT_BOARD_VERSION},
-	{"oem_id", 1, 0, OPT_OEM_ID},
-	{"sku_id", 1, 0, OPT_SKU_ID},
-	{"dram_part_num", 1, 0, OPT_DRAM_PART_NUM},
-	{"oem_name", 1, 0, OPT_OEM_NAME},
-	{"model_id", 1, 0, OPT_MODEL_ID},
-	{"fw_config", 1, 0, OPT_FW_CONFIG},
-	{"pcb_supplier", 1, 0, OPT_PCB_SUPPLIER},
-	{"ssfc", 1, 0, OPT_SSFC},
-	{"rework_id", 1, 0, OPT_REWORK_ID},
-	{"size", 1, 0, OPT_SIZE},
-	{"erase_byte", 1, 0, OPT_ERASE_BYTE},
-	{NULL, 0, 0, 0}
-};
-
-static const struct option opts_show[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"all", 0, 0, OPT_SHOW_ALL},
-	{NULL, 0, 0, 0}
-};
-
-static const char *field_name[] = {
-	/* Same order as enum cbi_data_tag */
-	"BOARD_VERSION",
-	"OEM_ID",
-	"SKU_ID",
-	"DRAM_PART_NUM",
-	"OEM_NAME",
-	"MODEL_ID",
-	"FW_CONFIG",
-	"PCB_SUPPLIER",
-	"SSFC",
-	"REWORK_ID",
-};
-BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT);
-
-const char help_create[] =
-	"\n"
-	"'%s create [ARGS]' creates an EEPROM image file.\n"
-	"Required ARGS are:\n"
-	"  --file <file>              Path to output file\n"
-	"  --board_version <value>    Board version\n"
-	"  --sku_id <value>           SKU ID\n"
-	"  --size <size>              Size of output file in bytes\n"
-	"\n"
-	"Optional ARGS are:\n"
-	"  --dram_part_num <string>   DRAM PART NUM\n"
-	"  --oem_id <value>           OEM ID\n"
-	"  --oem_name <string>        OEM NAME\n"
-	"  --erase_byte <uint8>       Byte used for empty space. Default:0xff\n"
-	"  --format_version <uint16>  Data format version\n"
-	"  --model_id <value>         Model ID\n"
-	"  --fw_config <value>        Firmware configuration bit-field\n"
-	"  --pcb_supplier <value>     PCB supplier\n"
-	"  --ssfc <value>             Second Source Factory Cache bit-field\n"
-	"  --rework_id <lvalue>       REWORK_ID\n"
-	"\n"
-	"<value> must be a positive integer <= 0XFFFFFFFF, <lvalue> must be a\n"
-	"  positive integer <= 0xFFFFFFFFFFFFFFFF and field size can be\n"
-	"  optionally specified by <value:size> notation: e.g. 0xabcd:4.\n"
-	"<size> must be a positive integer <= 0XFFFF.\n"
-	"<string> is a string\n"
-	"\n";
-
-const char help_show[] =
-	"\n"
-	"'%s show [ARGS]' shows data in an EEPROM image file.\n"
-	"Required ARGS are:\n"
-	"  --file <file>               Path to input file\n"
-	"Optional ARGS are:\n"
-	"  --all                       Dump all information\n"
-	"It also validates the contents against the checksum and\n"
-	"returns non-zero if validation fails.\n"
-	"\n";
-
-struct integer_field {
-	uint32_t val;
-	int size;
-};
-
-struct long_integer_field {
-	uint64_t val;
-	int size;
-};
-
-static void print_help_create(void)
-{
-	printf(help_create, cmd_name);
-}
-
-static void print_help_show(void)
-{
-	printf(help_show, cmd_name);
-}
-
-static void print_help(void)
-{
-	printf("\nUsage: %s <create|show> [ARGS]\n"
-		"\n"
-		"Utility for CBI:Cros Board Info images.\n", cmd_name);
-	print_help_create();
-	print_help_show();
-}
-
-static int write_file(const char *filename, const char *buf, int size)
-{
-	FILE *f;
-	int i;
-
-	/* Write to file */
-	f = fopen(filename, "wb");
-	if (!f) {
-		perror("Error opening output file");
-		return -1;
-	}
-	i = fwrite(buf, 1, size, f);
-	fclose(f);
-	if (i != size) {
-		perror("Error writing to file");
-		return -1;
-	}
-
-	return 0;
-}
-
-static uint8_t *read_file(const char *filename, uint32_t *size_ptr)
-{
-	FILE *f;
-	uint8_t *buf;
-	long size;
-
-	*size_ptr = 0;
-
-	f = fopen(filename, "rb");
-	if (!f) {
-		fprintf(stderr, "Unable to open file %s\n", filename);
-		return NULL;
-	}
-
-	fseek(f, 0, SEEK_END);
-	size = ftell(f);
-	rewind(f);
-
-	if (size < 0 || size > UINT32_MAX) {
-		fclose(f);
-		return NULL;
-	}
-
-	buf = malloc(size);
-	if (!buf) {
-		fclose(f);
-		return NULL;
-	}
-
-	if (1 != fread(buf, size, 1, f)) {
-		fprintf(stderr, "Unable to read from %s\n", filename);
-		fclose(f);
-		free(buf);
-		return NULL;
-	}
-
-	fclose(f);
-
-	*size_ptr = size;
-	return buf;
-}
-
-static int estimate_field_size(uint32_t value)
-{
-	if (value <= UINT8_MAX)
-		return 1;
-	if (value <= UINT16_MAX)
-		return 2;
-	return 4;
-}
-
-static int parse_integer_field(const char *arg, struct integer_field *f)
-{
-	uint64_t val;
-	char *e;
-	char *ch;
-
-	val = strtoull(arg, &e, 0);
-	if (val > UINT32_MAX || !*arg || (e && *e && *e != ':')) {
-		fprintf(stderr, "Invalid integer value\n");
-		return -1;
-	}
-	f->val = val;
-
-	ch = strchr(arg, ':');
-	if (ch) {
-		ch++;
-		val = strtoull(ch, &e, 0);
-		if (val < 1 || 4 < val || !*ch || (e && *e)) {
-			fprintf(stderr, "Invalid size suffix\n");
-			return -1;
-		}
-		f->size = val;
-	} else {
-		f->size = estimate_field_size(f->val);
-	}
-
-	if (f->val > (1ull << f->size * 8)) {
-		fprintf(stderr, "Value (0x%x) exceeds field size (%d)\n",
-			f->val, f->size);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int parse_uint64_field(const char *arg, struct long_integer_field *f)
-{
-	uint64_t val;
-	char *e;
-	char *ch;
-
-	val = strtoul(arg, &e, 0);
-	/* strtoul sets an errno for invalid input. If the value read is out of
-	 * range of representable values by an unsigned long int, the function
-	 * returns ULONG_MAX or ULONG_MIN and the errno is set to ERANGE.
-	 */
-	if (errno == ERANGE || !*arg || (e && *e && *e != ':')) {
-		fprintf(stderr, "Invalid integer value\n");
-		return -1;
-	}
-	f->val = val;
-
-	ch = strchr(arg, ':');
-	if (ch) {
-		ch++;
-		val = strtoul(ch, &e, 0);
-		if (val < 1 || 8 < val || !*ch || (e && *e)) {
-			fprintf(stderr, "Invalid size suffix\n");
-			return -1;
-		}
-		f->size = val;
-	} else {
-		if (f->val < UINT32_MAX)
-			f->size = estimate_field_size(f->val);
-		else
-			f->size = 8; /* assign default long int size */
-	}
-
-	if (f->size < 8 && (f->val > (1ull << f->size * 8))) {
-		fprintf(stderr, "Value (0x%llx) exceeds field size (%d)\n",
-			(unsigned long long)f->val, f->size);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int cmd_create(int argc, char **argv)
-{
-	uint8_t *cbi;
-	struct board_info {
-		struct integer_field ver;
-		struct integer_field oem;
-		struct integer_field sku;
-		struct integer_field model;
-		struct integer_field fw_config;
-		struct integer_field pcb_supplier;
-		struct integer_field ssfc;
-		struct long_integer_field rework;
-		const char *dram_part_num;
-		const char *oem_name;
-	} bi;
-	struct cbi_header *h;
-	int rv;
-	uint8_t *p;
-	const char *filename;
-	uint32_t set_mask = 0;
-	uint16_t size;
-	uint8_t erase = 0xff;
-	int i;
-
-	memset(&bi, 0, sizeof(bi));
-
-	while ((i = getopt_long(argc, argv, "", opts_create, NULL)) != -1) {
-		uint64_t val;
-		char *e;
-		switch (i) {
-		case '?': /* Unhandled option */
-			print_help_create();
-			return -1;
-		case OPT_HELP:
-			print_help_create();
-			return 0;
-		case OPT_BOARD_VERSION:
-			if (parse_integer_field(optarg, &bi.ver))
-				return -1;
-			set_mask |= ARGS_MASK_BOARD_VERSION;
-			break;
-		case OPT_ERASE_BYTE:
-			erase = strtoull(optarg, &e, 0);
-			if (!*optarg || (e && *e)) {
-				fprintf(stderr, "Invalid --erase_byte\n");
-				return -1;
-			}
-			break;
-		case OPT_FILENAME:
-			filename = optarg;
-			set_mask |= ARGS_MASK_FILENAME;
-			break;
-		case OPT_OEM_ID:
-			if (parse_integer_field(optarg, &bi.oem))
-				return -1;
-			break;
-		case OPT_SIZE:
-			val = strtoull(optarg, &e, 0);
-			if (val > UINT16_MAX || !*optarg || (e && *e)) {
-				fprintf(stderr, "Invalid --size\n");
-				return -1;
-			}
-			size = val;
-			set_mask |= ARGS_MASK_SIZE;
-			break;
-		case OPT_SKU_ID:
-			if (parse_integer_field(optarg, &bi.sku))
-				return -1;
-			set_mask |= ARGS_MASK_SKU_ID;
-			break;
-		case OPT_DRAM_PART_NUM:
-			bi.dram_part_num = optarg;
-			break;
-		case OPT_OEM_NAME:
-			bi.oem_name = optarg;
-			break;
-		case OPT_MODEL_ID:
-			if (parse_integer_field(optarg, &bi.model))
-				return -1;
-			break;
-		case OPT_FW_CONFIG:
-			if (parse_integer_field(optarg, &bi.fw_config))
-				return -1;
-			break;
-		case OPT_PCB_SUPPLIER:
-			if (parse_integer_field(optarg, &bi.pcb_supplier))
-				return -1;
-			break;
-		case OPT_SSFC:
-			if (parse_integer_field(optarg, &bi.ssfc))
-				return -1;
-			break;
-		case OPT_REWORK_ID:
-			if (parse_uint64_field(optarg, &bi.rework))
-				return -1;
-			break;
-		}
-	}
-
-	if (set_mask != (ARGS_MASK_BOARD_VERSION | ARGS_MASK_FILENAME |
-			ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) {
-		fprintf(stderr, "Missing required arguments\n");
-		print_help_create();
-		return -1;
-	}
-
-	cbi = malloc(size);
-	if (!cbi) {
-		fprintf(stderr, "Failed to allocate memory\n");
-		return -1;
-	}
-	memset(cbi, erase, size);
-
-	h = (struct cbi_header *)cbi;
-	memcpy(h->magic, cbi_magic, sizeof(cbi_magic));
-	h->major_version = CBI_VERSION_MAJOR;
-	h->minor_version = CBI_VERSION_MINOR;
-	p = h->data;
-	p = cbi_set_data(p, CBI_TAG_BOARD_VERSION, &bi.ver.val, bi.ver.size);
-	p = cbi_set_data(p, CBI_TAG_OEM_ID, &bi.oem.val, bi.oem.size);
-	p = cbi_set_data(p, CBI_TAG_SKU_ID, &bi.sku.val, bi.sku.size);
-	p = cbi_set_data(p, CBI_TAG_MODEL_ID, &bi.model.val, bi.model.size);
-	p = cbi_set_data(p, CBI_TAG_FW_CONFIG, &bi.fw_config.val,
-			 bi.fw_config.size);
-	p = cbi_set_data(p, CBI_TAG_PCB_SUPPLIER, &bi.pcb_supplier.val,
-			bi.pcb_supplier.size);
-	p = cbi_set_data(p, CBI_TAG_SSFC, &bi.ssfc.val, bi.ssfc.size);
-	p = cbi_set_data(p, CBI_TAG_REWORK_ID, &bi.rework.val, bi.rework.size);
-	p = cbi_set_string(p, CBI_TAG_DRAM_PART_NUM, bi.dram_part_num);
-	p = cbi_set_string(p, CBI_TAG_OEM_NAME, bi.oem_name);
-
-	h->total_size = p - cbi;
-	h->crc = cbi_crc8(h);
-
-	/* Output image */
-	rv = write_file(filename, cbi, size);
-	free(cbi);
-	if (rv) {
-		fprintf(stderr, "Unable to write CBI image to %s\n", filename);
-		return rv;
-	}
-
-	fprintf(stderr, "CBI image is created successfully\n");
-
-	return 0;
-}
-
-static void print_string(const uint8_t *buf, enum cbi_data_tag tag)
-{
-	struct cbi_data *d = cbi_find_tag(buf, tag);
-	const char *name;
-
-	if (!d)
-		return;
-
-	name = d->tag < CBI_TAG_COUNT ? field_name[d->tag] : "???";
-
-	printf("    %s: %.*s (%u, %u)\n", name, d->size, (const char *)d->value,
-		d->tag, d->size);
-}
-
-static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)
-{
-	uint64_t v;
-
-	struct cbi_data *d = cbi_find_tag(buf, tag);
-	const char *name;
-
-	if (!d)
-		return;
-
-	name = d->tag < CBI_TAG_COUNT ? field_name[d->tag] : "???";
-
-	switch (d->size) {
-	case 1:
-		v = *(uint8_t *)d->value;
-		break;
-	case 2:
-		v = *(uint16_t *)d->value;
-		break;
-	case 4:
-		v = *(uint32_t *)d->value;
-		break;
-	case 8:
-		v = *(uint64_t *)d->value;
-		break;
-	default:
-		printf("    %s: Integer of size %d not supported\n",
-		       name, d->size);
-		return;
-	}
-	printf("    %s: %llu (0x%llx, %u, %u)\n", name, (unsigned long long)v,
-		(unsigned long long)v, d->tag, d->size);
-}
-
-static int cmd_show(int argc, char **argv)
-{
-	uint8_t *buf;
-	uint32_t size;
-	struct cbi_header *h;
-	uint32_t set_mask = 0;
-	const char *filename;
-	int show_all = 0;
-	int i;
-
-	while ((i = getopt_long(argc, argv, "", opts_show, NULL)) != -1) {
-		switch (i) {
-		case '?': /* Unhandled option */
-			print_help_show();
-			return -1;
-		case OPT_HELP:
-			print_help_show();
-			return 0;
-		case OPT_FILENAME:
-			filename = optarg;
-			set_mask |= ARGS_MASK_FILENAME;
-			break;
-		case OPT_SHOW_ALL:
-			show_all = 1;
-			break;
-		}
-	}
-
-	if (set_mask != ARGS_MASK_FILENAME) {
-		fprintf(stderr, "Missing required arguments\n");
-		print_help_show();
-		return -1;
-	}
-
-	buf = read_file(filename, &size);
-	if (!buf) {
-		fprintf(stderr, "Unable to read CBI image\n");
-		return -1;
-	}
-
-	h = (struct cbi_header *)buf;
-	printf("CBI image: %s\n", filename);
-
-	if (memcmp(h->magic, cbi_magic, sizeof(cbi_magic))) {
-		fprintf(stderr, "Invalid Magic\n");
-		free(buf);
-		return -1;
-	}
-
-	if (cbi_crc8(h) != h->crc) {
-		fprintf(stderr, "Invalid CRC\n");
-		free(buf);
-		return -1;
-	}
-
-	printf("  TOTAL_SIZE: %u\n", h->total_size);
-	if (show_all)
-		printf("  CBI_VERSION: %u\n", h->version);
-	printf("  Data Field: name: value (hex, tag, size)\n");
-	print_integer(buf, CBI_TAG_BOARD_VERSION);
-	print_integer(buf, CBI_TAG_OEM_ID);
-	print_integer(buf, CBI_TAG_SKU_ID);
-	print_integer(buf, CBI_TAG_MODEL_ID);
-	print_integer(buf, CBI_TAG_FW_CONFIG);
-	print_integer(buf, CBI_TAG_PCB_SUPPLIER);
-	print_integer(buf, CBI_TAG_SSFC);
-	print_integer(buf, CBI_TAG_REWORK_ID);
-	print_string(buf, CBI_TAG_DRAM_PART_NUM);
-	print_string(buf, CBI_TAG_OEM_NAME);
-
-	free(buf);
-
-	printf("Data validated successfully\n");
-	return 0;
-}
-
-int main(int argc, char **argv)
-{
-	if (argc < 2) {
-		fprintf(stderr, "Unknown option or missing value\n");
-		print_help();
-		return -1;
-	}
-
-	if (!strncmp(argv[1], "create", sizeof("create")))
-		return cmd_create(--argc, ++argv);
-	else if (!strncmp(argv[1], "show", sizeof("show")))
-		return cmd_show(--argc, ++argv);
-
-	fprintf(stderr, "Unknown option or missing value\n");
-	print_help();
-
-	return -1;
-}
diff --git a/util/chargen b/util/chargen
deleted file mode 100644
index 9ba14d3d6a..0000000000
--- a/util/chargen
+++ /dev/null
@@ -1,69 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import sys
-
-def chargen(modulo, max_chars):
-    """Generate a stream of characters on the console.
-
-    The stream is an ever incrementing pattern of characters from the
-    following set: 0..9A..Za..z.
-
-    Args:
-      modulo:    an int, restart the pattern every modulo characters, if
-                 modulo is non zero
-      max_chars: an int, stop printing after this number of characters if non
-                 zero, if zero - print indefinitely
-    """
-
-    base = '0'
-    c = base
-    counter = 0
-    while True:
-        sys.stdout.write(c)
-        counter = counter + 1
-
-        if (max_chars != 0) and (counter == max_chars):
-            sys.stdout.write('\n')
-            return
-
-        if modulo and ((counter % modulo) == 0):
-            c = base
-            continue
-
-        if c == 'z':
-            c = base
-        elif c == 'Z':
-            c = 'a'
-        elif c == '9':
-            c = 'A'
-        else:
-            c = '%c' % (ord(c) + 1)
-
-
-def main(args):
-    '''Process command line arguments and invoke chargen if args are valid'''
-
-    modulo = 0
-    max_chars = 0
-
-    try:
-        if len(args) > 0:
-            modulo = int(args[0])
-            if len(args) > 1:
-                max_chars = int(args[1])
-    except ValueError:
-        sys.stderr.write('usage %s:'
-                         "['seq_length' ['max_chars']]\n")
-        sys.exit(1)
-
-    try:
-        chargen(modulo, max_chars)
-    except KeyboardInterrupt:
-        print()
-
-if __name__ == '__main__':
-    main(sys.argv[1:])
-    sys.exit(0)
diff --git a/util/check_allowed.sh b/util/check_allowed.sh
deleted file mode 100755
index 0881409036..0000000000
--- a/util/check_allowed.sh
+++ /dev/null
@@ -1,88 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Taken from U-Boot and modified.
-#
-# Check that the .config file provided does not introduce any new ad-hoc CONFIG
-# options
-#
-# Use util/build_allowed.sh to generate the list of current ad-hoc
-# CONFIG options (those which are not in Kconfig).
-
-# Usage
-#    check_allowed.sh <path to .config> <path to allow file> <source dir>
-#
-# For example:
-#   scripts/check_allowed.sh build/volteer/.config config_allowed.txt .
-
-set -e
-set -u
-
-PROG_NAME="${0##*/}"
-
-usage() {
-	echo >&2 "Check that a build does not introduce new ad-hoc CONFIGs"
-	echo >&2 "Usage:"
-	echo -e >&2 "\t${PROG_NAME} <.config file> <allow file> <source dir>"
-	exit 1
-}
-
-[ $# -ge 3 ] || usage
-
-config="$1"
-allow="$2"
-srctree="$3"
-
-tmp=$(mktemp -d)
-
-# Temporary files
-new_configs="${tmp}/configs"
-suspects="${tmp}/suspects"
-kconfigs="${tmp}/kconfigs"
-ok="${tmp}/ok"
-new_adhoc="${tmp}/adhoc"
-
-export LC_ALL=C LC_COLLATE=C
-
-# Get a sorted list of CONFIG options in the .config file
-sed -n 's/^\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' "${config}" | sort | uniq \
-	>"${new_configs}"
-
-# Find any not mentioned in the allowed file
-comm -23 "${new_configs}" "${allow}" > "${suspects}"
-
-# Find all the Kconfig options so far defined
-find "${srctree}" -type f -name "Kconfig*" -exec cat {} \; | sed -n -e \
-	's/^\s*\(config\|menuconfig\) *\([A-Za-z0-9_]*\)$/CONFIG_\2/p' \
-	| sort | uniq > "${kconfigs}"
-
-# Most Kconfigs follow the pattern of CONFIG_PLATFORM_EC_*.  Strip PLATFORM_EC_
-# from the config name to match the cros-ec namespace.
-sed -e 's/^CONFIG_PLATFORM_EC_/CONFIG_/p' "${kconfigs}" | sort | uniq > "${ok}"
-
-# Complain about any new ad-hoc CONFIGs
-comm -23 "${suspects}" "${ok}" >"${new_adhoc}"
-if [ -s "${new_adhoc}" ]; then
-	echo >&2 "Error: The EC is in the process of migrating to Zephyr."
-	echo -e >&2 "\tZephyr uses Kconfig for configuration rather than"
-	echo -e >&2 "\tad-hoc #defines."
-	echo -e >&2 "\tAny new EC CONFIG options must ALSO be added to Zephyr"
-	echo -e >&2 "\tso that new functionality is available in Zephyr also."
-	echo -e >&2 "\tThe following new ad-hoc CONFIG options were detected:"
-	echo >&2
-	cat >&2 "${new_adhoc}"
-	echo >&2
-	echo >&2 "Please add these via Kconfig instead. Find a suitable Kconfig"
-	echo >&2 "file in zephyr/ and add a 'config' or 'menuconfig' option."
-	echo >&2 "Also see details in http://issuetracker.google.com/181253613"
-	echo >&2
-	echo >&2 "To temporarily disable this, use: ALLOW_CONFIG=1 make ..."
-else
-	# Check if we can remove some things from the allowed file
-	./util/build_allowed.sh
-fi
-
-rm -rf "${tmp}"
diff --git a/util/comm-dev.c b/util/comm-dev.c
deleted file mode 100644
index e73538b323..0000000000
--- a/util/comm-dev.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <poll.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "cros_ec_dev.h"
-#include "comm-host.h"
-#include "ec_commands.h"
-#include "misc_util.h"
-
-static int fd = -1;
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0]))
-#endif
-
-static const char * const meanings[] = {
-	"SUCCESS",
-	"INVALID_COMMAND",
-	"ERROR",
-	"INVALID_PARAM",
-	"ACCESS_DENIED",
-	"INVALID_RESPONSE",
-	"INVALID_VERSION",
-	"INVALID_CHECKSUM",
-	"IN_PROGRESS",
-	"UNAVAILABLE",
-	"TIMEOUT",
-	"OVERFLOW",
-	"INVALID_HEADER",
-	"REQUEST_TRUNCATED",
-	"RESPONSE_TOO_BIG",
-	"BUS_ERROR",
-	"BUSY",
-	"INVALID_HEADER_VERSION",
-	"INVALID_HEADER_CRC",
-	"INVALID_DATA_CRC",
-	"DUP_UNAVAILABLE",
-};
-
-static const char *strresult(int i)
-{
-	if (i < 0 || i >= ARRAY_SIZE(meanings))
-		return "<unknown>";
-	return meanings[i];
-}
-
-/* Old ioctl format, used by Chrome OS 3.18 and older */
-
-static int ec_command_dev(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct cros_ec_command s_cmd;
-	int r;
-
-	s_cmd.command = command;
-	s_cmd.version = version;
-	s_cmd.result = 0xff;
-	s_cmd.outsize = outsize;
-	s_cmd.outdata = (uint8_t *)outdata;
-	s_cmd.insize = insize;
-	s_cmd.indata = (uint8_t *)(indata);
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-	if (r < 0) {
-		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
-			r, errno, strerror(errno), s_cmd.result,
-			strresult(s_cmd.result));
-		if (errno == EAGAIN && s_cmd.result == EC_RES_IN_PROGRESS) {
-			s_cmd.command = EC_CMD_RESEND_RESPONSE;
-			r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd.result,
-				strresult(s_cmd.result));
-		}
-	} else if (s_cmd.result != EC_RES_SUCCESS) {
-		fprintf(stderr, "EC result %d (%s)\n", s_cmd.result,
-			strresult(s_cmd.result));
-		return -EECRESULT - s_cmd.result;
-	}
-
-	return r;
-}
-
-static int ec_readmem_dev(int offset, int bytes, void *dest)
-{
-	struct cros_ec_readmem s_mem;
-	struct ec_params_read_memmap r_mem;
-	int r;
-	static int fake_it;
-
-	if (!fake_it) {
-		s_mem.offset = offset;
-		s_mem.bytes = bytes;
-		s_mem.buffer = (char *)(dest);
-		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM, &s_mem);
-		if (r < 0 && errno == ENOTTY)
-			fake_it = 1;
-		else
-			return r;
-	}
-
-	r_mem.offset = offset;
-	r_mem.size = bytes;
-	return ec_command_dev(EC_CMD_READ_MEMMAP, 0,
-			      &r_mem, sizeof(r_mem),
-			      dest, bytes);
-}
-
-/* New ioctl format, used by Chrome OS 4.4 and later as well as upstream 4.0+ */
-
-static int ec_command_dev_v2(int command, int version,
-			     const void *outdata, int outsize,
-			     void *indata, int insize)
-{
-	struct cros_ec_command_v2 *s_cmd;
-	int r;
-
-	assert(outsize == 0 || outdata != NULL);
-	assert(insize == 0 || indata != NULL);
-
-	s_cmd = (struct cros_ec_command_v2 *)(malloc(
-		sizeof(struct cros_ec_command_v2) + MAX(outsize, insize)));
-	if (s_cmd == NULL)
-		return -EC_RES_ERROR;
-
-	s_cmd->command = command;
-	s_cmd->version = version;
-	s_cmd->result = 0xff;
-	s_cmd->outsize = outsize;
-	s_cmd->insize = insize;
-	memcpy(s_cmd->data, outdata, outsize);
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, s_cmd);
-	if (r < 0) {
-		fprintf(stderr, "ioctl %d, errno %d (%s), EC result %d (%s)\n",
-			r, errno, strerror(errno), s_cmd->result,
-			strresult(s_cmd->result));
-		if (errno == EAGAIN && s_cmd->result == EC_RES_IN_PROGRESS) {
-			s_cmd->command = EC_CMD_RESEND_RESPONSE;
-			r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd->result,
-				strresult(s_cmd->result));
-		}
-	} else {
-		memcpy(indata, s_cmd->data, MIN(r, insize));
-		if (s_cmd->result != EC_RES_SUCCESS) {
-			fprintf(stderr, "EC result %d (%s)\n", s_cmd->result,
-				strresult(s_cmd->result));
-			r =  -EECRESULT - s_cmd->result;
-		}
-	}
-	free(s_cmd);
-
-	return r;
-}
-
-static int ec_readmem_dev_v2(int offset, int bytes, void *dest)
-{
-	struct cros_ec_readmem_v2 s_mem;
-	struct ec_params_read_memmap r_mem;
-	int r;
-	static int fake_it;
-
-	if (!fake_it) {
-		s_mem.offset = offset;
-		s_mem.bytes = bytes;
-		r = ioctl(fd, CROS_EC_DEV_IOCRDMEM_V2, &s_mem);
-		if (r < 0 && errno == ENOTTY) {
-			fake_it = 1;
-		} else {
-			memcpy(dest, s_mem.buffer, bytes);
-			return r;
-		}
-	}
-
-	r_mem.offset = offset;
-	r_mem.size = bytes;
-	return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0,
-				 &r_mem, sizeof(r_mem),
-				 dest, bytes);
-}
-
-/*
- * Attempt to communicate with kernel using old ioctl format.
- * If it returns ENOTTY, assume that this kernel uses the new format.
- */
-static int ec_dev_is_v2(void)
-{
-	struct ec_params_hello h_req = {
-		.in_data = 0xa0b0c0d0
-	};
-	struct ec_response_hello h_resp;
-	struct cros_ec_command s_cmd = { };
-	int r;
-
-	s_cmd.command = EC_CMD_HELLO;
-	s_cmd.result = 0xff;
-	s_cmd.outsize = sizeof(h_req);
-	s_cmd.outdata = (uint8_t *)&h_req;
-	s_cmd.insize = sizeof(h_resp);
-	s_cmd.indata = (uint8_t *)&h_resp;
-
-	r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-	if (r < 0 && errno == ENOTTY)
-		return 1;
-
-	return 0;
-}
-
-static int ec_pollevent_dev(unsigned long mask, void *buffer, size_t buf_size,
-			    int timeout)
-{
-	int rv;
-	struct pollfd pf = { .fd = fd, .events = POLLIN };
-
-	ioctl(fd, CROS_EC_DEV_IOCEVENTMASK_V2, mask);
-
-	rv = poll(&pf, 1, timeout);
-	if (rv != 1)
-		return rv;
-
-	if (pf.revents != POLLIN)
-		return -pf.revents;
-
-	return read(fd, buffer, buf_size);
-}
-
-int comm_init_dev(const char *device_name)
-{
-	int (*ec_cmd_readmem)(int offset, int bytes, void *dest);
-	char version[80];
-	char device[80] = "/dev/";
-	int r;
-	char *s;
-
-	strncat(device, (device_name ? device_name : CROS_EC_DEV_NAME), 40);
-	fd = open(device, O_RDWR);
-	if (fd < 0)
-		return 1;
-
-	r = read(fd, version, sizeof(version)-1);
-	if (r <= 0) {
-		close(fd);
-		return 2;
-	}
-	version[r] = '\0';
-	s = strchr(version, '\n');
-	if (s)
-		*s = '\0';
-	if (strcmp(version, CROS_EC_DEV_VERSION)) {
-		close(fd);
-		return 3;
-	}
-
-	if (ec_dev_is_v2()) {
-		ec_command_proto = ec_command_dev_v2;
-		ec_cmd_readmem = ec_readmem_dev_v2;
-	} else {
-		ec_command_proto = ec_command_dev;
-		ec_cmd_readmem = ec_readmem_dev;
-	}
-
-	if (ec_cmd_readmem(EC_MEMMAP_ID, 2, version) == 2 &&
-	    version[0] == 'E' && version[1] == 'C')
-		ec_readmem = ec_cmd_readmem;
-	ec_pollevent = ec_pollevent_dev;
-
-	/*
-	 * Set temporary size, will be updated later.
-	 */
-	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
-	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	return 0;
-}
diff --git a/util/comm-host.c b/util/comm-host.c
deleted file mode 100644
index 45d6f85a02..0000000000
--- a/util/comm-host.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "comm-host.h"
-#include "cros_ec_dev.h"
-#include "ec_commands.h"
-#include "misc_util.h"
-
-
-int (*ec_command_proto)(int command, int version,
-			const void *outdata, int outsize,
-			void *indata, int insize);
-
-int (*ec_readmem)(int offset, int bytes, void *dest);
-
-int (*ec_pollevent)(unsigned long mask, void *buffer, size_t buf_size,
-		    int timeout);
-
-int ec_max_outsize, ec_max_insize;
-void *ec_outbuf;
-void *ec_inbuf;
-static int command_offset;
-
-int comm_init_dev(const char *device_name) __attribute__((weak));
-int comm_init_lpc(void) __attribute__((weak));
-int comm_init_i2c(int i2c_bus) __attribute__((weak));
-int comm_init_servo_spi(const char *device_name) __attribute__((weak));
-
-static int fake_readmem(int offset, int bytes, void *dest)
-{
-	struct ec_params_read_memmap p;
-	int c;
-	char *buf;
-
-	p.offset = offset;
-
-	if (bytes) {
-		p.size = bytes;
-		c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p),
-			       dest, p.size);
-		if (c < 0)
-			return c;
-		return p.size;
-	}
-
-	p.size = EC_MEMMAP_TEXT_MAX;
-
-	c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest, p.size);
-	if (c < 0)
-		return c;
-
-	buf = (char *)(dest);
-	for (c = 0; c < EC_MEMMAP_TEXT_MAX; c++) {
-		if (buf[c] == 0)
-			return c;
-	}
-
-	buf[EC_MEMMAP_TEXT_MAX - 1] = 0;
-	return EC_MEMMAP_TEXT_MAX - 1;
-}
-
-void set_command_offset(int offset)
-{
-	command_offset = offset;
-}
-
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,
-	       void *indata, int insize)
-{
-	/* Offset command code to support sub-devices */
-	return ec_command_proto(command_offset + command, version,
-				outdata, outsize,
-				indata, insize);
-}
-
-int comm_init_alt(int interfaces, const char *device_name, int i2c_bus)
-{
-	bool dev_is_cros_ec;
-
-	/* Default memmap access */
-	ec_readmem = fake_readmem;
-
-	if ((interfaces & COMM_SERVO) && comm_init_servo_spi &&
-	    !comm_init_servo_spi(device_name))
-		return 0;
-
-	/* Do not fallback to other communication methods if target is not a
-	 * cros_ec device */
-	dev_is_cros_ec = !strcmp(CROS_EC_DEV_NAME, device_name);
-
-	/* Fallback to direct LPC on x86 */
-	if (dev_is_cros_ec && (interfaces & COMM_LPC) &&
-			comm_init_lpc && !comm_init_lpc())
-		return 0;
-
-	/* Fallback to direct I2C */
-	if ((dev_is_cros_ec || i2c_bus != -1) && (interfaces & COMM_I2C) &&
-			comm_init_i2c && !comm_init_i2c(i2c_bus))
-		return 0;
-
-	/* Give up */
-	fprintf(stderr, "Unable to establish host communication\n");
-	return 1;
-}
-
-int comm_init_buffer(void)
-{
-	int allow_large_buffer;
-	struct ec_response_get_protocol_info info;
-
-	allow_large_buffer = kernel_version_ge(3, 14, 0);
-	if (allow_large_buffer < 0) {
-		fprintf(stderr, "Unable to check linux version\n");
-		return 1;
-	}
-
-	/* Allocate shared I/O buffers */
-	ec_outbuf = malloc(ec_max_outsize);
-	ec_inbuf = malloc(ec_max_insize);
-	if (!ec_outbuf || !ec_inbuf) {
-		fprintf(stderr, "Unable to allocate buffers\n");
-		return 1;
-	}
-
-	/* read max request / response size from ec for protocol v3+ */
-	if (ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
-		sizeof(info)) == sizeof(info)) {
-		int outsize = info.max_request_packet_size -
-			sizeof(struct ec_host_request);
-		int insize = info.max_response_packet_size -
-			sizeof(struct ec_host_response);
-		if ((allow_large_buffer) || (outsize < ec_max_outsize))
-			ec_max_outsize = outsize;
-		if ((allow_large_buffer) || (insize < ec_max_insize))
-			ec_max_insize = insize;
-
-		ec_outbuf = realloc(ec_outbuf, ec_max_outsize);
-		ec_inbuf = realloc(ec_inbuf, ec_max_insize);
-
-		if (!ec_outbuf || !ec_inbuf) {
-			fprintf(stderr, "Unable to reallocate buffers\n");
-			return 1;
-		}
-	}
-
-	return 0;
-}
diff --git a/util/comm-host.h b/util/comm-host.h
deleted file mode 100644
index 309c97eeb5..0000000000
--- a/util/comm-host.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * For hysterical raisins, there are several mechanisms for communicating with
- * the EC. This abstracts them.
- */
-
-#ifndef __UTIL_COMM_HOST_H
-#define __UTIL_COMM_HOST_H
-
-#include "common.h"
-#include "ec_commands.h"
-
-/* ec_command return value for non-success result from EC */
-#define EECRESULT 1000
-
-/* Maximum output and input sizes for EC command, in bytes */
-extern int ec_max_outsize, ec_max_insize;
-
-/*
- * Maximum-size output and input buffers, for use by callers.  This saves each
- * caller needing to allocate/free its own buffers.
- */
-extern void *ec_outbuf;
-extern void *ec_inbuf;
-
-/* Interfaces to allow for comm_init() */
-enum comm_interface {
-	COMM_DEV = BIT(0),
-	COMM_LPC = BIT(1),
-	COMM_I2C = BIT(2),
-	COMM_SERVO = BIT(3),
-	COMM_ALL = -1
-};
-
-/**
- * Initialize alternative interfaces
- *
- * @param interfaces	Interfaces to try; use COMM_ALL to try all of them.
- * @param device_name For DEV option, the device file to use.
- * @param i2c_bus For I2C option, the bus number to use (or -1 to autodetect).
- * @return 0 in case of success, or error code.
- */
-int comm_init_alt(int interfaces, const char *device_name, int i2c_bus);
-
-/**
- * Initialize dev interface
- *
- * @return 0 in case of success, or error code.
- */
-int comm_init_dev(const char *device_name);
-
-/**
- * Initialize input & output buffers
- *
- * @return 0 in case of success, or error code.
- */
-int comm_init_buffer(void);
-
-/**
- * Send a command to the EC.  Returns the length of output data returned (0 if
- * none), or negative on error.
- */
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,   /* to the EC */
-	       void *indata, int insize);	   /* from the EC */
-
-/**
- * Set the offset to be applied to the command number when ec_command() calls
- * ec_command_proto().
- */
-void set_command_offset(int offset);
-
-/**
- * Send a command to the EC.  Returns the length of output data returned (0 if
- * none), or negative on error.  This is the low-level interface implemented
- * by the protocol-specific driver.  DO NOT call this version directly from
- * anywhere but ec_command(), or the --device option will not work.
- */
-extern int (*ec_command_proto)(int command, int version,
-			       const void *outdata, int outsize, /* to EC */
-			       void *indata, int insize);        /* from EC */
-
-/**
- * Return the content of the EC information area mapped as "memory".
- * The offsets are defined by the EC_MEMMAP_ constants. Returns the number
- * of bytes read, or negative on error. Specifying bytes=0 will read a
- * string (always including the trailing '\0').
- */
-extern int (*ec_readmem)(int offset, int bytes, void *dest);
-
-/**
- * Wait for a MKBP event matching 'mask' for at most 'timeout' milliseconds.
- * Then read the incoming event content in 'buffer' (or at most
- * 'buf_size' bytes of it).
- * Return the size of the event read on success, 0 in case of timeout,
- * or a negative value in case of error.
- */
-extern int (*ec_pollevent)(unsigned long mask, void *buffer, size_t buf_size,
-			   int timeout);
-
-#endif /* __UTIL_COMM_HOST_H */
diff --git a/util/comm-i2c.c b/util/comm-i2c.c
deleted file mode 100644
index d76749fbe5..0000000000
--- a/util/comm-i2c.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _GNU_SOURCE
-#define _GNU_SOURCE /* for asprintf */
-#endif
-
-#include <errno.h>
-#include <fcntl.h>
-#include <linux/i2c.h>
-#include <linux/i2c-dev.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-#include "i2c.h"
-
-#define EC_I2C_ADDR 0x1e
-
-#define I2C_ADAPTER_NODE "/sys/class/i2c-adapter/i2c-%d/%d-%04x/name"
-#define I2C_ADAPTER_NAME "cros-ec-i2c"
-#define I2C_MAX_ADAPTER  32
-#define I2C_NODE "/dev/i2c-%d"
-
-#ifdef DEBUG
-#define debug(format, arg...) printf(format, ##arg)
-#else
-#define debug(...)
-#endif
-
-static int i2c_fd = -1;
-
-static int sum_bytes(const void *data, int length)
-{
-	const uint8_t *bytes = (const uint8_t *)data;
-	int sum = 0;
-	int i;
-
-	for (i = 0; i < length; i++)
-		sum += bytes[i];
-	return sum;
-}
-
-static void dump_buffer(const uint8_t *data, int length)
-{
-	int i;
-
-	for (i = 0; i < length; i++)
-		fprintf(stderr, "%02X ", data[i]);
-	fprintf(stderr, "\n");
-}
-
-/*
- * Sends a command to the EC (protocol v3). Returns the command status code
- * (>= 0), or a negative EC_RES_* value on error.
- */
-static int ec_command_i2c_3(int command, int version,
-			    const void *outdata, int outsize,
-			    void *indata, int insize)
-{
-	int ret = -EC_RES_ERROR;
-	int error;
-	int req_len, resp_len;
-	uint8_t *req_buf = NULL;
-	uint8_t *resp_buf = NULL;
-	struct ec_host_request *req;
-	struct ec_host_response *resp;
-	uint8_t command_return_code;
-	struct i2c_msg i2c_msg;
-	struct i2c_rdwr_ioctl_data data;
-
-	if (outsize > ec_max_outsize) {
-		fprintf(stderr, "Request is too large (%d > %d).\n", outsize,
-			ec_max_outsize);
-		return -EC_RES_ERROR;
-	}
-	if (insize > ec_max_insize) {
-		fprintf(stderr, "Response would be too large (%d > %d).\n",
-			insize, ec_max_insize);
-		return -EC_RES_ERROR;
-	}
-	req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request)
-		+ outsize;
-	req_buf = (uint8_t *)(calloc(1, req_len));
-	if (!req_buf)
-		goto done;
-
-	req_buf[0] = EC_COMMAND_PROTOCOL_3;
-	req = (struct ec_host_request *)&req_buf[1];
-	req->struct_version = EC_HOST_REQUEST_VERSION;
-	req->checksum = 0;
-	req->command = command;
-	req->command_version = version;
-	req->reserved = 0;
-	req->data_len = outsize;
-
-	memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE
-			+ sizeof(struct ec_host_request)],
-	       outdata, outsize);
-
-	req->checksum =
-		(uint8_t)(-sum_bytes(&req_buf[I2C_REQUEST_HEADER_SIZE],
-				     req_len - I2C_REQUEST_HEADER_SIZE));
-
-	i2c_msg.addr = EC_I2C_ADDR;
-	i2c_msg.flags = 0;
-	i2c_msg.len = req_len;
-	i2c_msg.buf = req_buf;
-
-	resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response)
-		+ insize;
-	resp_buf = (uint8_t *)(calloc(1, resp_len));
-	if (!resp_buf)
-		goto done;
-	memset(resp_buf, 0, resp_len);
-
-	if (IS_ENABLED(DEBUG)) {
-		fprintf(stderr, "Sending: 0x");
-		dump_buffer(req_buf, req_len);
-	}
-
-	/*
-	 * Combining these two ioctls makes the write-read interval too short
-	 * for some chips (such as the MAX32660) to handle.
-	 */
-	data.msgs = &i2c_msg;
-	data.nmsgs = 1;
-	error = ioctl(i2c_fd, I2C_RDWR, &data);
-	if (error < 0) {
-		fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
-		goto done;
-	}
-
-	i2c_msg.addr = EC_I2C_ADDR;
-	i2c_msg.flags = I2C_M_RD;
-	i2c_msg.len = resp_len;
-	i2c_msg.buf = resp_buf;
-	error = ioctl(i2c_fd, I2C_RDWR, &data);
-	if (error < 0) {
-		fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
-		goto done;
-	}
-
-	if (IS_ENABLED(DEBUG)) {
-		fprintf(stderr, "Received: 0x");
-		dump_buffer(resp_buf, resp_len);
-	}
-
-	command_return_code = resp_buf[0];
-	if (command_return_code != EC_RES_SUCCESS) {
-		debug("command 0x%02x returned an error %d\n", command,
-		      command_return_code);
-		ret = -EECRESULT - command_return_code;
-		goto done;
-	}
-
-	if (resp_buf[1] > sizeof(struct ec_host_response) + insize) {
-		debug("EC returned too much data.\n");
-		ret = -EC_RES_RESPONSE_TOO_BIG;
-		goto done;
-	}
-
-	resp = (struct ec_host_response *)(&resp_buf[2]);
-	if (resp->struct_version != EC_HOST_RESPONSE_VERSION) {
-		debug("EC response version mismatch.\n");
-		ret = -EC_RES_INVALID_RESPONSE;
-		goto done;
-	}
-
-	if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE], resp_buf[1])
-			!= 0) {
-		debug("Bad checksum on EC response.\n");
-		ret = -EC_RES_INVALID_CHECKSUM;
-		goto done;
-	}
-
-	memcpy(indata, &resp_buf[I2C_RESPONSE_HEADER_SIZE
-				 + sizeof(struct ec_host_response)],
-	       insize);
-
-	ret = resp->data_len;
-done:
-	if (req_buf)
-		free(req_buf);
-	if (resp_buf)
-		free(resp_buf);
-
-	return ret;
-}
-
-int comm_init_i2c(int i2c_bus)
-{
-	char *file_path;
-	char buffer[64];
-	int i;
-
-	if (i2c_bus != -1) {
-		i = i2c_bus;
-
-		if (i >= I2C_MAX_ADAPTER) {
-			fprintf(stderr, "Invalid I2C bus number %d. (The highest possible bus number is %d.)\n",
-				i, I2C_MAX_ADAPTER);
-			return -1;
-		}
-	} else {
-		/* find the device number based on the adapter name */
-		for (i = 0; i < I2C_MAX_ADAPTER; i++) {
-			FILE *f;
-
-			if (asprintf(&file_path, I2C_ADAPTER_NODE,
-				     i, i, EC_I2C_ADDR) < 0)
-				return -1;
-			f = fopen(file_path, "r");
-			if (f) {
-				if (fgets(buffer, sizeof(buffer), f) &&
-				    !strncmp(buffer, I2C_ADAPTER_NAME, 6)) {
-					free(file_path);
-					fclose(f);
-					break;
-				}
-				fclose(f);
-			}
-			free(file_path);
-		}
-		if (i == I2C_MAX_ADAPTER) {
-			fprintf(stderr, "Cannot find I2C adapter\n");
-			return -1;
-		}
-	}
-
-	if (asprintf(&file_path, I2C_NODE, i) < 0)
-		return -1;
-	debug("using I2C adapter %s\n", file_path);
-	i2c_fd = open(file_path, O_RDWR);
-	if (i2c_fd < 0)
-		fprintf(stderr, "Cannot open %s : %d\n", file_path, errno);
-
-	free(file_path);
-
-	ec_command_proto = ec_command_i2c_3;
-	ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE
-		- sizeof(struct ec_host_request);
-	ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE
-		- sizeof(struct ec_host_response);
-
-	return 0;
-}
diff --git a/util/comm-lpc.c b/util/comm-lpc.c
deleted file mode 100644
index d1ce761fc2..0000000000
--- a/util/comm-lpc.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* The I/O asm funcs exist only on x86. */
-#if defined(__i386__) || defined(__x86_64__)
-
-#include <stdint.h>
-#include <stdio.h>
-#include <sys/io.h>
-#include <sys/param.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-
-#define INITIAL_UDELAY 5     /* 5 us */
-#define MAXIMUM_UDELAY 10000 /* 10 ms */
-
-/*
- * Wait for the EC to be unbusy.  Returns 0 if unbusy, non-zero if
- * timeout.
- */
-static int wait_for_ec(int status_addr, int timeout_usec)
-{
-	int i;
-	int delay = INITIAL_UDELAY;
-
-	for (i = 0; i < timeout_usec; i += delay) {
-		/*
-		 * Delay first, in case we just sent out a command but the EC
-		 * hasn't raised the busy flag.  However, I think this doesn't
-		 * happen since the LPC commands are executed in order and the
-		 * busy flag is set by hardware.  Minor issue in any case,
-		 * since the initial delay is very short.
-		 */
-		usleep(MIN(delay, timeout_usec - i));
-
-		if (!(inb(status_addr) & EC_LPC_STATUS_BUSY_MASK))
-			return 0;
-
-		/* Increase the delay interval after a few rapid checks */
-		if (i > 20)
-			delay = MIN(delay * 2, MAXIMUM_UDELAY);
-	}
-	return -1;  /* Timeout */
-}
-
-static int ec_command_lpc(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct ec_lpc_host_args args;
-	const uint8_t *d;
-	uint8_t *dout;
-	int csum;
-	int i;
-
-	/* Fill in args */
-	args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
-	args.command_version = version;
-	args.data_size = outsize;
-
-	/* Initialize checksum */
-	csum = command + args.flags + args.command_version + args.data_size;
-
-	/* Write data and update checksum */
-	for (i = 0, d = (uint8_t *)outdata; i < outsize; i++, d++) {
-		outb(*d, EC_LPC_ADDR_HOST_PARAM + i);
-		csum += *d;
-	}
-
-	/* Finalize checksum and write args */
-	args.checksum = (uint8_t)csum;
-	for (i = 0, d = (const uint8_t *)&args; i < sizeof(args); i++, d++)
-		outb(*d, EC_LPC_ADDR_HOST_ARGS + i);
-
-	outb(command, EC_LPC_ADDR_HOST_CMD);
-
-	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
-		fprintf(stderr, "Timeout waiting for EC response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Check result */
-	i = inb(EC_LPC_ADDR_HOST_DATA);
-	if (i) {
-		fprintf(stderr, "EC returned error result code %d\n", i);
-		return -EECRESULT - i;
-	}
-
-	/* Read back args */
-	for (i = 0, dout = (uint8_t *)&args; i < sizeof(args); i++, dout++)
-		*dout = inb(EC_LPC_ADDR_HOST_ARGS + i);
-
-	/*
-	 * If EC didn't modify args flags, then somehow we sent a new-style
-	 * command to an old EC, which means it would have read its params
-	 * from the wrong place.
-	 */
-	if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
-		fprintf(stderr, "EC protocol mismatch\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (args.data_size > insize) {
-		fprintf(stderr, "EC returned too much data\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	/* Start calculating response checksum */
-	csum = command + args.flags + args.command_version + args.data_size;
-
-	/* Read response and update checksum */
-	for (i = 0, dout = (uint8_t *)indata; i < args.data_size;
-	     i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PARAM + i);
-		csum += *dout;
-	}
-
-	/* Verify checksum */
-	if (args.checksum != (uint8_t)csum) {
-		fprintf(stderr, "EC response has invalid checksum\n");
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return actual amount of data received */
-	return args.data_size;
-}
-
-static int ec_command_lpc_3(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
-{
-	struct ec_host_request rq;
-	struct ec_host_response rs;
-	const uint8_t *d;
-	uint8_t *dout;
-	int csum = 0;
-	int i;
-
-	/* Fail if output size is too big */
-	if (outsize + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE)
-		return -EC_RES_REQUEST_TRUNCATED;
-
-	/* Fill in request packet */
-	/* TODO(crosbug.com/p/23825): This should be common to all protocols */
-	rq.struct_version = EC_HOST_REQUEST_VERSION;
-	rq.checksum = 0;
-	rq.command = command;
-	rq.command_version = version;
-	rq.reserved = 0;
-	rq.data_len = outsize;
-
-	/* Copy data and start checksum */
-	for (i = 0, d = (const uint8_t *)outdata; i < outsize; i++, d++) {
-		outb(*d, EC_LPC_ADDR_HOST_PACKET + sizeof(rq) + i);
-		csum += *d;
-	}
-
-	/* Finish checksum */
-	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
-		csum += *d;
-
-	/* Write checksum field so the entire packet sums to 0 */
-	rq.checksum = (uint8_t)(-csum);
-
-	/* Copy header */
-	for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++)
-		outb(*d, EC_LPC_ADDR_HOST_PACKET + i);
-
-	/* Start the command */
-	outb(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD);
-
-	if (wait_for_ec(EC_LPC_ADDR_HOST_CMD, 1000000)) {
-		fprintf(stderr, "Timeout waiting for EC response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Check result */
-	i = inb(EC_LPC_ADDR_HOST_DATA);
-	if (i) {
-		fprintf(stderr, "EC returned error result code %d\n", i);
-		return -EECRESULT - i;
-	}
-
-	/* Read back response header and start checksum */
-	csum = 0;
-	for (i = 0, dout = (uint8_t *)&rs; i < sizeof(rs); i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PACKET + i);
-		csum += *dout;
-	}
-
-	if (rs.struct_version != EC_HOST_RESPONSE_VERSION) {
-		fprintf(stderr, "EC response version mismatch\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.reserved) {
-		fprintf(stderr, "EC response reserved != 0\n");
-		return -EC_RES_INVALID_RESPONSE;
-	}
-
-	if (rs.data_len > insize) {
-		fprintf(stderr, "EC returned too much data\n");
-		return -EC_RES_RESPONSE_TOO_BIG;
-	}
-
-	/* Read back data and update checksum */
-	for (i = 0, dout = (uint8_t *)indata; i < rs.data_len; i++, dout++) {
-		*dout = inb(EC_LPC_ADDR_HOST_PACKET + sizeof(rs) + i);
-		csum += *dout;
-	}
-
-	/* Verify checksum */
-	if ((uint8_t)csum) {
-		fprintf(stderr, "EC response has invalid checksum\n");
-		return -EC_RES_INVALID_CHECKSUM;
-	}
-
-	/* Return actual amount of data received */
-	return rs.data_len;
-}
-
-static int ec_readmem_lpc(int offset, int bytes, void *dest)
-{
-	int i = offset;
-	char *s = (char *)(dest);
-	int cnt = 0;
-
-	if (offset >= EC_MEMMAP_SIZE - bytes)
-		return -1;
-
-	if (bytes) {				/* fixed length */
-		for (; cnt < bytes; i++, s++, cnt++)
-			*s = inb(EC_LPC_ADDR_MEMMAP + i);
-	} else {				/* string */
-		for (; i < EC_MEMMAP_SIZE; i++, s++) {
-			*s = inb(EC_LPC_ADDR_MEMMAP + i);
-			cnt++;
-			if (!*s)
-				break;
-		}
-	}
-
-	return cnt;
-}
-
-int comm_init_lpc(void)
-{
-	int i;
-	int byte = 0xff;
-
-	/* Request I/O privilege */
-	if (iopl(3) < 0) {
-		perror("Error getting I/O privilege");
-		return -3;
-	}
-
-	/*
-	 * Test if the I/O port has been configured for Chromium EC LPC
-	 * interface.  Chromium EC guarantees that at least one status bit will
-	 * be 0, so if the command and data bytes are both 0xff, very likely
-	 * that Chromium EC is not present.  See crosbug.com/p/10963.
-	 */
-	byte &= inb(EC_LPC_ADDR_HOST_CMD);
-	byte &= inb(EC_LPC_ADDR_HOST_DATA);
-	if (byte == 0xff) {
-		fprintf(stderr, "Port 0x%x,0x%x are both 0xFF.\n",
-			EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_DATA);
-		fprintf(stderr,
-			"Very likely this board doesn't have a Chromium EC.\n");
-		return -4;
-	}
-
-	/*
-	 * Test if LPC command args are supported.
-	 *
-	 * The cheapest way to do this is by looking for the memory-mapped
-	 * flag.  This is faster than sending a new-style 'hello' command and
-	 * seeing whether the EC sets the EC_HOST_ARGS_FLAG_FROM_HOST flag
-	 * in args when it responds.
-	 */
-	if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) != 'E' ||
-	    inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) != 'C') {
-		fprintf(stderr, "Missing Chromium EC memory map.\n");
-		return -5;
-	}
-
-	/* Check which command version we'll use */
-	i = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS);
-
-	if (i & EC_HOST_CMD_FLAG_VERSION_3) {
-		/* Protocol version 3 */
-		ec_command_proto = ec_command_lpc_3;
-		ec_max_outsize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_request);
-		ec_max_insize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_response);
-
-	} else if (i & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) {
-		/* Protocol version 2 */
-		ec_command_proto = ec_command_lpc;
-		ec_max_outsize = ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	} else {
-		fprintf(stderr, "EC doesn't support protocols we need.\n");
-		return -5;
-	}
-
-	/* Either one supports reading mapped memory directly. */
-	ec_readmem = ec_readmem_lpc;
-	return 0;
-}
-
-#endif
diff --git a/util/comm-servo-spi.c b/util/comm-servo-spi.c
deleted file mode 100644
index ef6dc7880b..0000000000
--- a/util/comm-servo-spi.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/*
- * Transport using the Servo V2 SPI1 interface through the FT4232 MPSSE
- * hardware engine (driven by libftdi) in order to send host commands V3
- * directly to a MCU slave SPI controller.
- *
- * It allows to drive a MCU with the cros_ec host SPI interface directly from
- * a developer workstation or another test system.
- *
- * The USB serial number of the servo board can be passed in the 'name'
- * parameter, e.g. :
- * sudo ectool_servo --name=905537-00474 version
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include <libftdi1/ftdi.h>
-
-#include "comm-host.h"
-#include "cros_ec_dev.h"
-
-/* Servo V2 SPI1 interface identifiers */
-#define SERVO_V2_USB_VID 0x18d1
-#define SERVO_V2_USB_PID 0x5003
-#define SERVO_V2_USB_SPI1_INTERFACE INTERFACE_B
-
-/* SPI clock frequency in Hz */
-#define SPI_CLOCK_FREQ 1000000
-
-#define FTDI_LATENCY_1MS 2
-
-/* Timeout when waiting for the EC answer to our request */
-#define RESP_TIMEOUT 2 /* second */
-
-#ifdef DEBUG
-#define debug(format, arg...) printf(format, ##arg)
-#else
-#define debug(...)
-#endif
-
-/* Communication context */
-static struct ftdi_context ftdi;
-
-/* Size of a MPSSE command packet */
-#define MPSSE_CMD_SIZE 3
-
-enum mpsse_commands {
-	ENABLE_ADAPTIVE_CLOCK = 0x96,
-	DISABLE_ADAPTIVE_CLOCK = 0x97,
-	TCK_X5 = 0x8A,
-	TCK_D5 = 0x8B,
-	TRISTATE_IO = 0x9E,
-};
-
-enum mpsse_pins {
-	SCLK = 1,
-	MOSI = 2,
-	MISO = 4,
-	CS_L = 8,
-};
-/* SCLK/MOSI/CS_L are outputs, MISO is an input */
-#define PINS_DIR (SCLK | MOSI | CS_L)
-
-/* SPI mode 0:
- * propagates data on the falling edge
- * and reads data on the rising edge of the clock.
- */
-#define SPI_CMD_TX   (MPSSE_DO_WRITE | MPSSE_WRITE_NEG)
-#define SPI_CMD_RX   (MPSSE_DO_READ)
-#define SPI_CMD_TXRX (MPSSE_DO_WRITE | MPSSE_DO_READ | MPSSE_WRITE_NEG)
-
-static int raw_read(uint8_t *buf, int size)
-{
-	int rlen;
-
-	while (size) {
-		rlen = ftdi_read_data(&ftdi, buf, size);
-		if (rlen < 0)
-			break;
-		buf += rlen;
-		size -= rlen;
-	}
-	return !!size;
-}
-
-static int mpsse_set_pins(uint8_t levels)
-{
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-
-	buf[0] = SET_BITS_LOW;
-	buf[1] = levels;
-	buf[2] = PINS_DIR;
-
-	return ftdi_write_data(&ftdi, buf, sizeof(buf)) != sizeof(buf);
-}
-
-static int send_request(int cmd, int version,
-			const uint8_t *outdata, size_t outsize)
-{
-	uint8_t *txbuf;
-	struct ec_host_request *request;
-	size_t i;
-	int ret = -EC_RES_ERROR;
-	uint8_t csum = 0;
-	size_t block_size = sizeof(struct ec_host_request) + outsize;
-	size_t total_len = MPSSE_CMD_SIZE + block_size;
-
-	txbuf = (uint8_t *)(calloc(1, total_len));
-	if (!txbuf)
-		return -ENOMEM;
-
-	/* MPSSE block size is the full command minus 1 byte */
-	txbuf[0] = SPI_CMD_TXRX;
-	txbuf[1] = ((block_size - 1) & 0xFF);
-	txbuf[2] = (((block_size - 1) >> 8) & 0xFF);
-
-	/* Command header first */
-	request = (struct ec_host_request *)(txbuf + MPSSE_CMD_SIZE);
-	request->struct_version = EC_HOST_REQUEST_VERSION;
-	request->checksum = 0;
-	request->command = cmd;
-	request->command_version = version;
-	request->reserved = 0;
-	request->data_len = outsize;
-
-	/* copy the data to transmit after the command header */
-	memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request),
-	       outdata, outsize);
-
-	/* Compute the checksum */
-	for (i = MPSSE_CMD_SIZE; i < total_len; i++)
-		csum += txbuf[i];
-	request->checksum = -csum;
-
-	if (ftdi_write_data(&ftdi, txbuf, total_len) != total_len)
-		goto free_request;
-
-	if (raw_read(txbuf, block_size) != 0)
-		goto free_request;
-
-	/* Make sure the EC was listening */
-	ret = 0;
-	for (i = 0; i < block_size; i++) {
-		switch (txbuf[i]) {
-		case EC_SPI_PAST_END:
-		case EC_SPI_RX_BAD_DATA:
-		case EC_SPI_NOT_READY:
-			ret = txbuf[i];
-			/* Fall-through */
-		default:
-			break;
-		}
-		if (ret)
-			break;
-	}
-
-free_request:
-	free(txbuf);
-	return ret;
-}
-
-static int spi_read(uint8_t *buf, size_t size)
-{
-	uint8_t cmd[MPSSE_CMD_SIZE];
-
-	cmd[0] = SPI_CMD_RX;
-	cmd[1] = ((size - 1) & 0xFF);
-	cmd[2] = (((size - 1) >> 8) & 0xFF);
-
-	if (ftdi_write_data(&ftdi, cmd, sizeof(cmd)) != sizeof(cmd))
-		return -EC_RES_ERROR;
-
-	return raw_read(buf, size) != 0;
-}
-
-static int get_response(uint8_t *bodydest, size_t bodylen)
-{
-	uint8_t sum = 0;
-	size_t i;
-	struct ec_host_response hdr;
-	uint8_t status;
-	time_t deadline = time(NULL) + RESP_TIMEOUT;
-
-	/*
-	 * Read a byte at a time until we see the start of the frame.
-	 * This is slow, but often still faster than the EC.
-	 */
-	while (time(NULL) < deadline) {
-		if (spi_read(&status, sizeof(status)))
-			goto read_error;
-		if (status == EC_SPI_FRAME_START)
-			break;
-	}
-	if (status != EC_SPI_FRAME_START) {
-		fprintf(stderr, "timeout wait for response\n");
-		return -EC_RES_ERROR;
-	}
-
-	/* Now read the response header */
-	if (spi_read((uint8_t *)(&hdr), sizeof(hdr)))
-		goto read_error;
-
-	/* Check the header */
-	if (hdr.struct_version != EC_HOST_RESPONSE_VERSION) {
-		fprintf(stderr, "response version %d (should be %d)\n",
-			hdr.struct_version,
-			EC_HOST_RESPONSE_VERSION);
-		return -EC_RES_ERROR;
-	}
-	if (hdr.data_len > bodylen) {
-		fprintf(stderr, "response data_len %d is > %zd\n",
-			hdr.data_len, bodylen);
-		return -EC_RES_ERROR;
-	}
-
-	/* Read the data if needed */
-	if (hdr.data_len && spi_read(bodydest, hdr.data_len))
-		goto read_error;
-
-	/* Verify the checksum */
-	for (i = 0; i < sizeof(struct ec_host_response); i++)
-		sum += ((uint8_t *)&hdr)[i];
-	for (i = 0; i < hdr.data_len; i++)
-		sum += bodydest[i];
-	if (sum) {
-		fprintf(stderr, "Checksum invalid\n");
-		return -EC_RES_ERROR;
-	}
-
-	return hdr.result ? -EECRESULT - hdr.result : 0;
-
-read_error:
-	fprintf(stderr, "Read failed: %s\n", ftdi_get_error_string(&ftdi));
-	return -EC_RES_ERROR;
-}
-
-static int ec_command_servo_spi(int cmd, int version,
-				const void *outdata, int outsize,
-				void *indata, int insize)
-{
-	int ret = -EC_RES_ERROR;
-
-	/* Set the chip select low */
-	if (mpsse_set_pins(0) != 0) {
-		fprintf(stderr, "Start failed: %s\n",
-			ftdi_get_error_string(&ftdi));
-		return -EC_RES_ERROR;
-	}
-
-	if (send_request(cmd, version, (const uint8_t *)(outdata), outsize) ==
-	    0)
-		ret = get_response((uint8_t *)(indata), insize);
-
-	if (mpsse_set_pins(CS_L) != 0) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ftdi_get_error_string(&ftdi));
-		return -EC_RES_ERROR;
-	}
-	/* SPI protocol gap ... */
-	usleep(10);
-
-	return ret;
-}
-
-static int mpsse_set_clock(uint32_t freq)
-{
-	uint32_t system_clock = 0;
-	uint16_t divisor = 0;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-
-	if (freq > 6000000) {
-		buf[0] = TCK_X5;
-		system_clock = 60000000;
-	} else {
-		buf[0] = TCK_D5;
-		system_clock = 12000000;
-	}
-
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		return -EC_RES_ERROR;
-
-	divisor = (((system_clock / freq) / 2) - 1);
-
-	buf[0] = TCK_DIVISOR;
-	buf[1] = (divisor & 0xFF);
-	buf[2] = ((divisor >> 8) & 0xFF);
-
-	return ftdi_write_data(&ftdi, buf, MPSSE_CMD_SIZE) != MPSSE_CMD_SIZE;
-}
-
-static void servo_spi_close(void)
-{
-	ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
-	ftdi_usb_close(&ftdi);
-	ftdi_deinit(&ftdi);
-}
-
-int comm_init_servo_spi(const char *device_name)
-{
-	int status;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
-	/* if the user mentioned a device name, use it as serial string */
-	const char *serial = strcmp(CROS_EC_DEV_NAME, device_name) ?
-		device_name : NULL;
-
-	if (ftdi_init(&ftdi))
-		return -EC_RES_ERROR;
-	ftdi_set_interface(&ftdi, SERVO_V2_USB_SPI1_INTERFACE);
-
-	status = ftdi_usb_open_desc(&ftdi, SERVO_V2_USB_VID, SERVO_V2_USB_PID,
-				    NULL, serial);
-	if (status) {
-		debug("Can't find a Servo v2 USB device\n");
-		return -EC_RES_ERROR;
-	}
-
-	status |= ftdi_usb_reset(&ftdi);
-	status |= ftdi_set_latency_timer(&ftdi, FTDI_LATENCY_1MS);
-	status |= ftdi_set_bitmode(&ftdi, 0, BITMODE_RESET);
-	if (status)
-		goto err_close;
-
-	ftdi_set_bitmode(&ftdi, 0, BITMODE_MPSSE);
-	if (mpsse_set_clock(SPI_CLOCK_FREQ))
-		goto err_close;
-
-	/* Disable FTDI internal loopback */
-	buf[0] = LOOPBACK_END;
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		goto err_close;
-	/* Ensure adaptive clock is disabled */
-	buf[0] = DISABLE_ADAPTIVE_CLOCK;
-	if (ftdi_write_data(&ftdi, buf, 1) != 1)
-		goto err_close;
-	/* Set the idle pin states */
-	if (mpsse_set_pins(CS_L) != 0)
-		goto err_close;
-
-	ec_command_proto = ec_command_servo_spi;
-	/* Set temporary size, will be updated later. */
-	ec_max_outsize = EC_PROTO2_MAX_PARAM_SIZE - 8;
-	ec_max_insize = EC_PROTO2_MAX_PARAM_SIZE;
-
-	return 0;
-
-err_close:
-	servo_spi_close();
-	return -EC_RES_ERROR;
-}
diff --git a/util/compare_build.sh b/util/compare_build.sh
deleted file mode 100755
index 1b6030453a..0000000000
--- a/util/compare_build.sh
+++ /dev/null
@@ -1,292 +0,0 @@
-#!/bin/bash
-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Tool to compare two commits and make sure that the resulting build output is
-# exactly the same.
-#
-# The board parameter is a space separated list containing any valid board
-# or special board group listed below. Items added to the list can be prefixed
-# with a + or - to enforce that it is added or removed from the active set of
-# boards. Boards are added or removed in the order in which they appear.
-# * all       - All boards that are built by the "buildall" target
-# * fp        - All relevant boards for fingerprint
-# * stm32     - All boards that use an STM32 chip
-# * stm32f4   - All boards that use an STM32F4 family of chip
-# * stm32h7   - All boards that use an STM32H7 family of chip
-# * npcx      - "
-# * mchp      - "
-# * ish       - "
-# * it83xx    - "
-# * lm4       - "
-# * mec1322   - "
-# * max32660  - "
-# * mt_scp    - "
-#
-# Example: --boards "+all -stm32"
-
-# Cr50 doesn't have reproducible builds.
-# The following fails:
-# git commit --allow-empty -m "Test" &&
-# ./util/compare_build.sh --boards cr50 --ref1 HEAD --ref2 HEAD^
-#
-# Note to Developers
-# Although this script is a good proving ground for new testing techniques,
-# care should be taken to offload functionality to other core components.
-
-. /usr/share/misc/shflags
-
-FLAGS_PRIVATE_DEFAULT="${FLAGS_FALSE}"
-if [[ -d private ]]; then
-  FLAGS_PRIVATE_DEFAULT="${FLAGS_TRUE}"
-fi
-
-DEFINE_string 'boards' "nocturne_fp" 'Boards to build (all, fp, stm32, hatch)' \
-              'b'
-DEFINE_string 'ref1' "HEAD" 'Git reference (commit, branch, etc)'
-DEFINE_string 'ref2' "HEAD^" 'Git reference (commit, branch, etc)'
-DEFINE_boolean 'keep' "${FLAGS_FALSE}" \
-               'Remove the temp directory after comparison.' 'k'
-# Integer type can still be passed blank ("")
-DEFINE_integer 'jobs' "-1" 'Number of jobs to pass to make' 'j'
-# When compiling both refs for all boards, mem usage was larger than 32GB.
-# If you don't have more than 32GB, you probably don't want to build both
-# refs at the same time. Use the -o flag.
-DEFINE_boolean 'oneref' "${FLAGS_FALSE}" \
-               'Build only one set of boards at a time. This limits mem.' 'o'
-DEFINE_boolean 'private' "${FLAGS_PRIVATE_DEFAULT}" \
-               'Link the private repo/dir into test build source tree.'
-
-# Usage: assoc-add-keys <associate_array_name> [item1 [item2...]]
-assoc-add-keys() {
-  local -n arr="${1}"
-  shift
-
-  for key in "${@}"; do
-    arr["${key}"]="${key}"
-  done
-}
-
-# Usage: assoc-rm-keys <associate_array_name> [item1 [item2...]
-assoc-rm-keys() {
-  local -n arr="${1}"
-  shift
-
-  for key in "${@}"; do
-    unset arr["${key}"]
-  done
-}
-
-# Usage: make-print-boards
-#
-# Cache the make print-boards output
-make-print-boards() {
-  local file="${TMP_DIR}/make-print-boards-cache"
-  if [[ ! -f "${file}" ]]; then
-    # This command take about 1 second to run
-    make print-boards >"${file}"
-  fi
-  cat "${file}"
-}
-
-# Usage: boards-with CHIP
-boards-with() {
-  local pattern="${1}"
-
-  for b in $(make-print-boards); do
-    grep -E -q "${pattern}" "board/${b}/build.mk" && echo "${b}"
-  done
-}
-
-# Usage: parse-boards <associate_array_name> [board-grp1 [board-grp2...]]
-parse-boards() {
-  # shellcheck disable=SC2034
-  local -n boards="$1"
-  shift
-
-  # Board groups
-  #
-  # Get all CHIP variants in use:
-  # grep -E 'CHIP[[:space:]]*\:' board/*/build.mk \
-  #   | sed 's/.*:=[[:space:]]*//' | sort -u
-  local -A BOARD_GROUPS=(
-    # make-print-boards already filters out the skipped boards
-    [all]="$(make-print-boards)"
-    [fp]="dartmonkey bloonchipper nucleo-dartmonkey nucleo-h743zi"
-    [stm32]="$(boards-with 'CHIP[[:space:]:=]*stm32')"
-    [stm32f4]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32f4')"
-    [stm32h7]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32h7')"
-    [npcx]="$(boards-with 'CHIP[[:space:]:=]*npcx')"
-    [mchp]="$(boards-with 'CHIP[[:space:]:=]*mchp')"
-    [ish]="$(boards-with 'CHIP[[:space:]:=]*ish')"
-    [it83xx]="$(boards-with 'CHIP[[:space:]:=]*it83xx')"
-    [lm4]="$(boards-with 'CHIP[[:space:]:=]*lm4')"
-    [mec1322]="$(boards-with 'CHIP[[:space:]:=]*mec1322')"
-    [max32660]="$(boards-with 'CHIP[[:space:]:=]*max32660')"
-    [mt_scp]="$(boards-with 'CHIP[[:space:]:=]*mt_scp')"
-  )
-
-  local -a BOARDS_VALID_RAW=( )
-  mapfile -t BOARDS_VALID_RAW < <(basename -a board/*)
-  local -A BOARDS_VALID=( )
-  assoc-add-keys BOARDS_VALID "${!BOARD_GROUPS[@]}" "${BOARDS_VALID_RAW[@]}"
-
-  # Parse boards selection
-  local b name name_arr=( )
-  for b; do
-    # Remove + or - prefix
-    name="$(sed -E 's/^(-|\+)//' <<<"${b}")"
-    # Check for a valid board
-    if [[ "${BOARDS_VALID[${name}]}" != "${name}" ]]; then
-      echo "# Error - Board '${name}' does not exist" >&2
-      return 1
-    fi
-    # Check for expansion target
-    if [[ -n "${BOARD_GROUPS[${name}]}" ]]; then
-      name="${BOARD_GROUPS[${name}]}"
-    fi
-    read -d "" -r -a name_arr <<< "${name}"
-    # Process addition or deletion
-    case "${b}" in
-      -*)
-        assoc-rm-keys boards "${name_arr[@]}"
-        ;;
-      +*|*)
-        assoc-add-keys boards "${name_arr[@]}"
-        ;;
-    esac
-  done
-}
-
-
-##########################################################################
-# Argument Parsing and Parameter Setup                                   #
-##########################################################################
-
-TMP_DIR="$(mktemp -d -t compare_build.XXXX)"
-
-# Process commandline flags.
-FLAGS "${@}" || exit 1
-eval set -- "${FLAGS_ARGV}"
-
-set -e
-
-# Can specify any valid git ref (e.g., commits or branches).
-# We need the long sha for fetching changes
-OLD_REF="$(git rev-parse "${FLAGS_ref1}")"
-NEW_REF="$(git rev-parse "${FLAGS_ref2}")"
-
-MAKE_FLAGS=( )
-# Specify -j 1 for sequential
-if (( FLAGS_jobs > 0 )); then
-  MAKE_FLAGS+=( "-j" "${FLAGS_jobs}" )
-else
-  MAKE_FLAGS+=( "-j" )
-fi
-
-declare -A BOARDS=( )
-read -r -a FLAGS_boards <<< "${FLAGS_boards}"
-parse-boards BOARDS "${FLAGS_boards[@]}" || exit $?
-
-if [[ ${#BOARDS[@]} -eq 0 ]]; then
-  echo "# Error - No boards selected" >&2
-  exit 1
-fi
-echo "# Board Selection:"
-printf "%s\n" "${BOARDS[@]}" | sort | column
-
-# Symbolically linked directories
-LINKS=( )
-if [[ "${FLAGS_private}" == "${FLAGS_TRUE}" ]]; then
-  echo "# Requesting private directory link"
-  LINKS+=( private )
-fi
-
-##########################################################################
-# Runtime                                                                #
-##########################################################################
-
-# We want make to initiate the builds for ref1 and ref2 so that a
-# single jobserver manages the process.
-# We should do the build comparison in the Makefile to allow for easier
-# debugging when --keep is enabled.
-echo "# Preparing Makefile"
-cat > "${TMP_DIR}/Makefile" <<HEREDOC
-ORIGIN ?= $(realpath .)
-CRYPTOC_DIR ?= $(realpath ../../third_party/cryptoc)
-BOARDS ?= ${BOARDS[*]}
-LINKS ?= ${LINKS[*]}
-
-.PHONY: all
-all: build-${OLD_REF} build-${NEW_REF}
-
-ec-%:
-	git clone --quiet --no-checkout \$(ORIGIN) \$@
-	git -C \$@ checkout --quiet \$(@:ec-%=%)
-ifneq (\$(LINKS),)
-	ln -s \$(addprefix \$(ORIGIN)/,\$(LINKS)) \$@
-endif
-
-build-%: ec-%
-	\$(MAKE) --no-print-directory -C \$(@:build-%=ec-%)                   \\
-		STATIC_VERSION=1                                              \\
-		CRYPTOC_DIR=\$(CRYPTOC_DIR)                                   \\
-		\$(addprefix proj-,\$(BOARDS))
-	@printf "  MKDIR   %s\n" "\$@"
-	@mkdir -p \$@
-	@for b in \$(BOARDS); do	                                      \\
-		printf "  CP -l   '%s' to '%s'\n"                             \\
-			"\$(@:build-%=ec-%)/build/\$\$b/ec.bin"               \\
-                        "\$@/\$\$b-ec.bin";                                   \\
-		cp -l \$(@:build-%=ec-%)/build/\$\$b/ec.bin \$@/\$\$b-ec.bin; \\
-	done
-
-# So that make doesn't try to remove them
-ec-${OLD_REF}:
-ec-${NEW_REF}:
-HEREDOC
-
-
-build() {
-  echo make --no-print-directory -C "${TMP_DIR}" "${MAKE_FLAGS[@]}"  "$@"
-  make --no-print-directory -C "${TMP_DIR}" "${MAKE_FLAGS[@]}"  "$@"
-  return $?
-}
-
-echo "# Launching build. Cover your eyes."
-result=0
-if [[ "${FLAGS_oneref}" == "${FLAGS_FALSE}" ]]; then
-  build "build-${OLD_REF}" "build-${NEW_REF}" || result=$?
-else
-  build "build-${OLD_REF}" && build "build-${NEW_REF}" || result=$?
-fi
-if [[ ${result} -ne 0 ]]; then
-  echo >&2
-  echo "# Failed to make one or more of the refs." >&2
-  exit 1
-fi
-echo
-
-echo "# Comparing Files"
-echo
-if diff "${TMP_DIR}/build-"{"${OLD_REF}","${NEW_REF}"}; then
-  echo "# Verdict: MATCH"
-  result=0
-else
-  echo "# Verdict: FAILURE"
-  result=1
-fi
-echo
-
-# Do keep in mind that temp directory take a few GB if all boards are built.
-if [[ "${FLAGS_keep}" == "${FLAGS_TRUE}" ]]; then
-  echo "# Keeping temp directory around for your inspection."
-  echo "# ${TMP_DIR}"
-else
-  echo "# Removing temp directory"
-  rm -rf "${TMP_DIR}"
-fi
-
-exit "${result}"
diff --git a/util/config_allowed.txt b/util/config_allowed.txt
deleted file mode 100644
index 16f88d5a90..0000000000
--- a/util/config_allowed.txt
+++ /dev/null
@@ -1,1117 +0,0 @@
-CONFIG_
-CONFIG_8042_AUX
-CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
-CONFIG_ACCELGYRO_BMI160_INT_EVENT
-CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT
-CONFIG_ACCELGYRO_BMI260_INT_EVENT
-CONFIG_ACCELGYRO_ICM42607_INT_EVENT
-CONFIG_ACCELGYRO_ICM426XX_INT_EVENT
-CONFIG_ACCELGYRO_LSM6DS0
-CONFIG_ACCELGYRO_LSM6DSM
-CONFIG_ACCELGYRO_LSM6DSO
-CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
-CONFIG_ACCEL_CAL_KASA_RADIUS_THRES
-CONFIG_ACCEL_CAL_MAX_TEMP
-CONFIG_ACCEL_CAL_MIN_TEMP
-CONFIG_ACCEL_CAL_NEWTON_RADIUS_THRES
-CONFIG_ACCEL_FORCE_MODE_MASK
-CONFIG_ACCEL_KXCJ9
-CONFIG_ACCEL_LIS2DE
-CONFIG_ACCEL_LIS2DH
-CONFIG_ACCEL_LIS2DS
-CONFIG_ACCEL_LIS2DS_INT_EVENT
-CONFIG_ACCEL_LIS2DW12_INT_EVENT
-CONFIG_ACCEL_LIS2DWL
-CONFIG_ACCEL_LIS2DW_AS_BASE
-CONFIG_ACCEL_LIS2DW_COMMON
-CONFIG_ACCEL_LIS2D_COMMON
-CONFIG_ACCEL_LNG2DM
-CONFIG_ACCEL_LSM6DSM_INT_EVENT
-CONFIG_ACCEL_LSM6DSO_INT_EVENT
-CONFIG_ACCEL_STD_REF_FRAME_OLD
-CONFIG_ADC_BUTTONS
-CONFIG_ADC_PROFILE
-CONFIG_ADC_PROFILE_FAST_CONTINUOUS
-CONFIG_ADC_PROFILE_SINGLE
-CONFIG_ADC_SAMPLE_TIME
-CONFIG_ADC_VOLTAGE_COMPARATOR
-CONFIG_ADC_WATCHDOG
-CONFIG_AES
-CONFIG_AES_GCM
-CONFIG_ALS_AL3010
-CONFIG_ALS_BH1730
-CONFIG_ALS_BH1730_LUXTH_PARAMS
-CONFIG_ALS_ISL29035
-CONFIG_ALS_LIGHTBAR_DIMMING
-CONFIG_ALS_OPT3001
-CONFIG_ALS_SI114X
-CONFIG_ALS_SI114X_CHECK_REVISION
-CONFIG_ALS_SI114X_INT_EVENT
-CONFIG_ALS_SI114X_POLLING
-CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT
-CONFIG_ALS_TCS3400_INT_EVENT
-CONFIG_AON_PERSISTENT_BASE
-CONFIG_AON_PERSISTENT_SIZE
-CONFIG_AON_RAM_BASE
-CONFIG_AON_RAM_SIZE
-CONFIG_AP_HANG_DETECT
-CONFIG_AP_WARM_RESET_INTERRUPT
-CONFIG_ARCH_POSIX
-CONFIG_ARM64
-CONFIG_ARMV7M_CACHE
-CONFIG_ASSEMBLY_MULA32
-CONFIG_ASSERT
-CONFIG_AUDIO_CODEC
-CONFIG_AUDIO_CODEC_
-CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-CONFIG_AUDIO_CODEC_DMIC
-CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN
-CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN
-CONFIG_AUDIO_CODEC_I2S_RX
-CONFIG_AUDIO_CODEC_WOV
-CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_LEN
-CONFIG_AUDIO_CODEC_WOV_AUDIO_BUF_TYPE
-CONFIG_AUDIO_CODEC_WOV_LANG_BUF_LEN
-CONFIG_AUDIO_CODEC_WOV_LANG_BUF_TYPE
-CONFIG_AUX_TIMER_PERIOD_MS
-CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-CONFIG_BACKLIGHT_REQ_GPIO
-CONFIG_BARO_BMP280
-CONFIG_BASE32
-CONFIG_BASE_ATTACHED_SWITCH
-CONFIG_BATTERY_
-CONFIG_BATTERY_BQ20Z453
-CONFIG_BATTERY_BQ27541
-CONFIG_BATTERY_BQ27621
-CONFIG_BATTERY_BQ4050
-CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-CONFIG_BATTERY_COUNT
-CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT
-CONFIG_BATTERY_CUTOFF_DELAY_US
-CONFIG_BATTERY_LEVEL_NEAR_FULL
-CONFIG_BATTERY_MAX17055
-CONFIG_BATTERY_MAX17055_ALERT
-CONFIG_BATTERY_MAX17055_FULL_MODEL
-CONFIG_BATTERY_MAX_IMBALANCE_MV
-CONFIG_BATTERY_MEASURE_IMBALANCE
-CONFIG_BATTERY_MM8013
-CONFIG_BATTERY_MOCK
-CONFIG_BATTERY_PRECHARGE_TIMEOUT
-CONFIG_BATTERY_PRESENT_
-CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-CONFIG_BATTERY_RETRY_NACK
-CONFIG_BATTERY_V2
-CONFIG_BATTERY_VENDOR_PARAM
-CONFIG_BATT_HOST_FULL_FACTOR
-CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
-CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
-CONFIG_BC12_DETECT_MAX14637
-CONFIG_BC12_DETECT_PI3USB9281
-CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT
-CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS
-CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-CONFIG_BD9995X_POWER_SAVE_MODE
-CONFIG_BLANK
-CONFIG_BLINK
-CONFIG_BLINK_LEDS
-CONFIG_BLUETOOTH_HCI_DEBUG
-CONFIG_BLUETOOTH_LE
-CONFIG_BLUETOOTH_LE_RADIO_TEST
-CONFIG_BLUETOOTH_LE_STACK
-CONFIG_BLUETOOTH_LL_DEBUG
-CONFIG_BMI_ORIENTATION_SENSOR
-CONFIG_BMI_SEC_I2C
-CONFIG_BOARD_DEEP_SLEEP
-CONFIG_BOARD_EC_HANDLES_ALL_SYS_PWRGD
-CONFIG_BOARD_FORCE_RESET_PIN
-CONFIG_BOARD_HAS_ALL_SYS_PWRGD
-CONFIG_BOARD_HAS_RTC_RESET
-CONFIG_BOARD_I2C_ADDR_FLAGS
-CONFIG_BOARD_ID_CMD_ACPI_EC1
-CONFIG_BOARD_POST_GPIO_INIT
-CONFIG_BOARD_PRE_INIT
-CONFIG_BODY_DETECTION
-CONFIG_BODY_DETECTION_CONFIDENCE_DELTA
-CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE
-CONFIG_BODY_DETECTION_OFF_BODY_CON
-CONFIG_BODY_DETECTION_ON_BODY_CON
-CONFIG_BODY_DETECTION_SENSOR
-CONFIG_BODY_DETECTION_STATIONARY_DURATION
-CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR
-CONFIG_BODY_DETECTION_VAR_THRESHOLD
-CONFIG_BOOTBLOCK
-CONFIG_BOOTCFG_VALUE
-CONFIG_BOOT_HEADER_STORAGE_OFF
-CONFIG_BOOT_HEADER_STORAGE_SIZE
-CONFIG_BUTTONS_RUNTIME_CONFIG
-CONFIG_BUTTON_COUNT
-CONFIG_BUTTON_TRIGGERED_RECOVERY
-CONFIG_CAPSENSE
-CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
-CONFIG_CEC
-CONFIG_CHARGER
-CONFIG_CHARGER_BATTERY_TSENSE
-CONFIG_CHARGER_BD9995X
-CONFIG_CHARGER_BD9995X_CHGEN
-CONFIG_CHARGER_BQ24715
-CONFIG_CHARGER_BQ24770
-CONFIG_CHARGER_BQ24773
-CONFIG_CHARGER_BQ25703
-CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
-CONFIG_CHARGER_CURRENT_LIMIT
-CONFIG_CHARGER_EN_ACTIVE_LOW
-CONFIG_CHARGER_EN_GPIO
-CONFIG_CHARGER_ILIM_PIN_DISABLED
-CONFIG_CHARGER_LIMIT_
-CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
-CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-CONFIG_CHARGER_MAX_INPUT_CURRENT
-CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
-CONFIG_CHARGER_MT6370
-CONFIG_CHARGER_MT6370_BACKLIGHT
-CONFIG_CHARGER_MT6370_BC12_GPIO
-CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
-CONFIG_CHARGER_RAA489000
-CONFIG_CHARGER_RT9466
-CONFIG_CHARGER_RT9467
-CONFIG_CHARGER_RUNTIME_CONFIG
-CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710
-CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
-CONFIG_CHARGER_SINGLE_CHIP
-CONFIG_CHARGER_SM5803
-CONFIG_CHARGER_SY21612
-CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT
-CONFIG_CHARGE_MANAGER_DRP_CHARGING
-CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
-CONFIG_CHARGE_MANAGER_SAFE_MODE
-CONFIG_CHARGE_STATE_DEBUG
-CONFIG_CHIPSET_ALDERLAKE
-CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
-CONFIG_CHIPSET_APL_GLK
-CONFIG_CHIPSET_APOLLOLAKE
-CONFIG_CHIPSET_BRASWELL
-CONFIG_CHIPSET_CANNONLAKE
-CONFIG_CHIPSET_CEZANNE
-CONFIG_CHIPSET_COMETLAKE
-CONFIG_CHIPSET_COMETLAKE_DISCRETE
-CONFIG_CHIPSET_DEBUG
-CONFIG_CHIPSET_ECDRIVEN
-CONFIG_CHIPSET_GEMINILAKE
-CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
-CONFIG_CHIPSET_HAS_PLATFORM_RESET
-CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-CONFIG_CHIPSET_ICELAKE
-CONFIG_CHIPSET_JASPERLAKE
-CONFIG_CHIPSET_MT817X
-CONFIG_CHIPSET_MT8183
-CONFIG_CHIPSET_MT8192
-CONFIG_CHIPSET_POWER_SEQ_VERSION
-CONFIG_CHIPSET_PP3300_RAIL_FIRST
-CONFIG_CHIPSET_RK3288
-CONFIG_CHIPSET_RK3399
-CONFIG_CHIPSET_SC7180
-CONFIG_CHIPSET_SC7280
-CONFIG_CHIPSET_SDM845
-CONFIG_CHIPSET_SKYLAKE
-CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
-CONFIG_CHIPSET_STONEY
-CONFIG_CHIPSET_TIGERLAKE
-CONFIG_CHIPSET_X86_RSMRST_DELAY
-CONFIG_CHIP_DATA_IN_INIT_ROM
-CONFIG_CHIP_INIT_ROM_REGION
-CONFIG_CHIP_LFW_USE_ROM_SPI
-CONFIG_CHIP_MEMORY_REGIONS
-CONFIG_CHIP_PANIC_BACKUP
-CONFIG_CHIP_PRE_INIT
-CONFIG_CHIP_UNCACHED_REGION
-CONFIG_CLOCK_CRYSTAL
-CONFIG_CLOCK_SRC_EXTERNAL
-CONFIG_CMD_ACCELS
-CONFIG_CMD_ACCELSPOOF
-CONFIG_CMD_ACCEL_FIFO
-CONFIG_CMD_ACCEL_INFO
-CONFIG_CMD_ADC
-CONFIG_CMD_ALS
-CONFIG_CMD_APTHROTTLE
-CONFIG_CMD_AP_RESET_LOG
-CONFIG_CMD_BATDEBUG
-CONFIG_CMD_BATTFAKE
-CONFIG_CMD_BATT_MFG_ACCESS
-CONFIG_CMD_CBI
-CONFIG_CMD_CHARGEN
-CONFIG_CMD_CHARGER
-CONFIG_CMD_CHARGER_ADC_AMON_BMON
-CONFIG_CMD_CHARGER_DUMP
-CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-CONFIG_CMD_CHARGE_SUPPLIER_INFO
-CONFIG_CMD_CHGRAMP
-CONFIG_CMD_CLOCKGATES
-CONFIG_CMD_COMXTEST
-CONFIG_CMD_CRASH
-CONFIG_CMD_DEVICE_EVENT
-CONFIG_CMD_DLOG
-CONFIG_CMD_ECTEMP
-CONFIG_CMD_FASTCHARGE
-CONFIG_CMD_FLASH
-CONFIG_CMD_FLASHINFO
-CONFIG_CMD_FLASH_TRISTATE
-CONFIG_CMD_FLASH_WP
-CONFIG_CMD_FORCETIME
-CONFIG_CMD_FPSENSOR_DEBUG
-CONFIG_CMD_GETTIME
-CONFIG_CMD_GL3590
-CONFIG_CMD_GPIO_EXTENDED
-CONFIG_CMD_GPIO_POWER_DOWN
-CONFIG_CMD_GT7288
-CONFIG_CMD_HASH
-CONFIG_CMD_HCDEBUG
-CONFIG_CMD_HOSTCMD
-CONFIG_CMD_I2CWEDGE
-CONFIG_CMD_I2C_PROTECT
-CONFIG_CMD_I2C_SCAN
-CONFIG_CMD_I2C_STRESS_TEST
-CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-CONFIG_CMD_I2C_STRESS_TEST_ALS
-CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-CONFIG_CMD_I2C_STRESS_TEST_TCPC
-CONFIG_CMD_I2C_XFER
-CONFIG_CMD_I2C_XFER_RAW
-CONFIG_CMD_IDLE_STATS
-CONFIG_CMD_INA
-CONFIG_CMD_JUMPTAGS
-CONFIG_CMD_KEYBOARD
-CONFIG_CMD_LEDTEST
-CONFIG_CMD_MCDP
-CONFIG_CMD_MD
-CONFIG_CMD_MEM
-CONFIG_CMD_MFALLOW
-CONFIG_CMD_MMAPINFO
-CONFIG_CMD_PD
-CONFIG_CMD_PD_DEV_DUMP_INFO
-CONFIG_CMD_PD_FLASH
-CONFIG_CMD_PECI
-CONFIG_CMD_PLL
-CONFIG_CMD_POWERINDEBUG
-CONFIG_CMD_POWERLED
-CONFIG_CMD_POWER_AP
-CONFIG_CMD_PPC_DUMP
-CONFIG_CMD_PS2
-CONFIG_CMD_PWR_AVG
-CONFIG_CMD_RAND
-CONFIG_CMD_REGULATOR
-CONFIG_CMD_RESET_FLAGS
-CONFIG_CMD_RETIMER
-CONFIG_CMD_RTC
-CONFIG_CMD_RTC_ALARM
-CONFIG_CMD_RW
-CONFIG_CMD_S5_TIMEOUT
-CONFIG_CMD_SCRATCHPAD
-CONFIG_CMD_SEVEN_SEG_DISPLAY
-CONFIG_CMD_SHA256_TEST
-CONFIG_CMD_SHMEM
-CONFIG_CMD_SLEEP
-CONFIG_CMD_SLEEPMASK
-CONFIG_CMD_SLEEPMASK_SET
-CONFIG_CMD_SPI_FLASH
-CONFIG_CMD_SPI_NOR
-CONFIG_CMD_SPI_XFER
-CONFIG_CMD_STACKOVERFLOW
-CONFIG_CMD_SYSINFO
-CONFIG_CMD_SYSJUMP
-CONFIG_CMD_SYSLOCK
-CONFIG_CMD_TASKREADY
-CONFIG_CMD_TASK_RESET
-CONFIG_CMD_TCPC_DUMP
-CONFIG_CMD_TEMP_SENSOR
-CONFIG_CMD_TIMERINFO
-CONFIG_CMD_TYPEC
-CONFIG_CMD_USART_INFO
-CONFIG_CMD_USB_PD_CABLE
-CONFIG_CMD_USB_PD_PE
-CONFIG_CMD_WAITMS
-CONFIG_CODE_RAM_SIZE
-CONFIG_COMMON_GPIO
-CONFIG_COMMON_GPIO_SHORTNAMES
-CONFIG_COMMON_PANIC_OUTPUT
-CONFIG_COMMON_RUNTIME
-CONFIG_COMMON_TIMER
-CONFIG_CONSOLE_CMDHELP
-CONFIG_CONSOLE_COMMAND_FLAGS
-CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT
-CONFIG_CONSOLE_ENABLE_READ_V1
-CONFIG_CONSOLE_HISTORY
-CONFIG_CONSOLE_INPUT_LINE_SIZE
-CONFIG_CONSOLE_UART
-CONFIG_CONSOLE_VERBOSE
-CONFIG_CPU_CORTEX_M
-CONFIG_CPU_PROCHOT_ACTIVE_LOW
-CONFIG_CRC8
-CONFIG_CROS_EC_RO_MEM_SIZE
-CONFIG_CROS_EC_RW_MEM_SIZE
-CONFIG_CTN730
-CONFIG_CTS_TASK_LIST
-CONFIG_CURVE25519
-CONFIG_CUSTOM_FAN_CONTROL
-CONFIG_DAC
-CONFIG_DATA_RAM_SIZE
-CONFIG_DEBUG_BRINGUP
-CONFIG_DEBUG_DISABLE_WRITE_BUFFER
-CONFIG_DEBUG_EXCEPTIONS
-CONFIG_DEBUG_ORIENTATION
-CONFIG_DEBUG_PRINTF
-CONFIG_DEBUG_STACK_OVERFLOW
-CONFIG_DEDICATED_CHARGE_PORT_COUNT
-CONFIG_DEDICATED_RECOVERY_BUTTON
-CONFIG_DEDICATED_RECOVERY_BUTTON_2
-CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
-CONFIG_DETACHABLE_BASE
-CONFIG_DEVICE_EVENT
-CONFIG_DEVICE_STATE
-CONFIG_DMA
-CONFIG_DMA_DEFAULT_HANDLERS
-CONFIG_DMA_HELP
-CONFIG_DMA_PAGING
-CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
-CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
-CONFIG_DPTF_MULTI_PROFILE
-CONFIG_DRAM_BASE
-CONFIG_DRAM_BASE_LOAD
-CONFIG_DRAM_SIZE
-CONFIG_DSW_PWROK_TO_PWRBTN_US
-CONFIG_EC_CMD_PD_CHIP_INFO
-CONFIG_EC_EC_COMM_BATTERY
-CONFIG_EC_EC_COMM_BATTERY_CLIENT
-CONFIG_EC_EC_COMM_BATTERY_SERVER
-CONFIG_EC_EC_COMM_CLIENT
-CONFIG_EC_EC_COMM_SERVER
-CONFIG_EC_MAX_SENSOR_FREQ_DEFAULT_MILLIHZ
-CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ
-CONFIG_EC_PROTECTED_STORAGE_OFF
-CONFIG_EC_PROTECTED_STORAGE_SIZE
-CONFIG_EC_WRITABLE_STORAGE_OFF
-CONFIG_EC_WRITABLE_STORAGE_SIZE
-CONFIG_EEPROM
-CONFIG_ENABLE_JTAG_SELECTION
-CONFIG_ESPI_DEBUG
-CONFIG_ESPI_LOG_LEVEL
-CONFIG_EVENT_LOG_SIZE
-CONFIG_EXPERIMENTAL_CONSOLE
-CONFIG_EXTENDED_VERSION_INFO
-CONFIG_EXTPOWER
-CONFIG_EXTPOWER_DEBOUNCE_MS
-CONFIG_FAKE_SHMEM
-CONFIG_FANS
-CONFIG_FAN_DSLEEP
-CONFIG_FAN_DYNAMIC
-CONFIG_FAN_INIT_SPEED
-CONFIG_FAN_RPM_CUSTOM
-CONFIG_FAN_UPDATE_PERIOD
-CONFIG_FINGERPRINT_MCU
-CONFIG_FLASH_BANK_SIZE
-CONFIG_FLASH_DEFERRED_ERASE
-CONFIG_FLASH_ERASED_VALUE32
-CONFIG_FLASH_ERASE_SIZE
-CONFIG_FLASH_LOG
-CONFIG_FLASH_LOG_BASE
-CONFIG_FLASH_LOG_SPACE
-CONFIG_FLASH_MULTIPLE_REGION
-CONFIG_FLASH_PHYSICAL
-CONFIG_FLASH_PROTECT_NEXT_BOOT
-CONFIG_FLASH_PROTECT_RW
-CONFIG_FLASH_PSTATE_BANK
-CONFIG_FLASH_PSTATE_LOCKED
-CONFIG_FLASH_READOUT_PROTECTION
-CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-CONFIG_FLASH_REGION_TYPE_COUNT
-CONFIG_FLASH_SELECT_REQUIRED
-CONFIG_FLASH_SIZE_BYTES
-CONFIG_FLASH_WRITE_IDEAL_SIZE
-CONFIG_FLASH_WRITE_SIZE
-CONFIG_FMAP
-CONFIG_FOO
-CONFIG_FORCE_CONSOLE_RESUME
-CONFIG_FP_SENSOR_ELAN515
-CONFIG_FP_SENSOR_ELAN80
-CONFIG_FP_SENSOR_FPC1025
-CONFIG_FP_SENSOR_FPC1035
-CONFIG_FP_SENSOR_FPC1145
-CONFIG_FRONT_PROXIMITY_SWITCH
-CONFIG_FW_INCLUDE_RO
-CONFIG_FW_LIMITED_IMAGE
-CONFIG_FW_PSTATE_OFF
-CONFIG_FW_PSTATE_SIZE
-CONFIG_GESTURE_DETECTION
-CONFIG_GESTURE_DETECTION_MASK
-CONFIG_GESTURE_HOST_DETECTION
-CONFIG_GESTURE_ORIENTATION
-CONFIG_GESTURE_SAMPLING_INTERVAL_MS
-CONFIG_GESTURE_SENSOR_DOUBLE_TAP
-CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST
-CONFIG_GESTURE_SIGMO
-CONFIG_GESTURE_SIGMO_PROOF_MS
-CONFIG_GESTURE_SIGMO_SENSOR
-CONFIG_GESTURE_SIGMO_SKIP_MS
-CONFIG_GESTURE_SIGMO_THRES_MG
-CONFIG_GESTURE_SW_DETECTION
-CONFIG_GESTURE_TAP_FOR_HOST
-CONFIG_GESTURE_TAP_INNER_WINDOW_T
-CONFIG_GESTURE_TAP_MAX_INTERSTICE_T
-CONFIG_GESTURE_TAP_MIN_INTERSTICE_T
-CONFIG_GESTURE_TAP_OUTER_WINDOW_T
-CONFIG_GESTURE_TAP_SENSOR
-CONFIG_GESTURE_TAP_THRES_MG
-CONFIG_GMR_TABLET_MODE_CUSTOM
-CONFIG_GPIO_GET_EXTENDED
-CONFIG_GPIO_POWER_DOWN
-CONFIG_GYRO_L3GD20H
-CONFIG_H2RAM_BASE
-CONFIG_H2RAM_HOST_LPC_IO_BASE
-CONFIG_H2RAM_SIZE
-CONFIG_HAS_TASK_PD_INT
-CONFIG_HIBERNATE
-CONFIG_HIBERNATE_BATT_PCT
-CONFIG_HIBERNATE_BATT_SEC
-CONFIG_HIBERNATE_DELAY_SEC
-CONFIG_HIBERNATE_PSL_COMPENSATE_RTC
-CONFIG_HIBERNATE_PSL_OUT_FLAGS
-CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP
-CONFIG_HIBERNATE_WAKEUP_PINS
-CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
-CONFIG_HID_HECI
-CONFIG_HOOK_DEBUG
-CONFIG_HOSTCMD_ALIGNED
-CONFIG_HOSTCMD_AP_SET_SKUID
-CONFIG_HOSTCMD_BATTERY_V2
-CONFIG_HOSTCMD_BUTTON
-CONFIG_HOSTCMD_ESPI
-CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
-CONFIG_HOSTCMD_ESPI_EC_MODE
-CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-CONFIG_HOSTCMD_EVENTS
-CONFIG_HOSTCMD_FLASHPD
-CONFIG_HOSTCMD_FLASH_SPI_INFO
-CONFIG_HOSTCMD_HECI
-CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-CONFIG_HOSTCMD_I2C_SLAVE_ADDR
-CONFIG_HOSTCMD_LOCATE_CHIP
-CONFIG_HOSTCMD_LPC
-CONFIG_HOSTCMD_PD
-CONFIG_HOSTCMD_PD_CHG_CTRL
-CONFIG_HOSTCMD_PD_PANIC
-CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST
-CONFIG_HOSTCMD_RATE_LIMITING_PERIOD
-CONFIG_HOSTCMD_RATE_LIMITING_RECESS
-CONFIG_HOSTCMD_RWHASHPD
-CONFIG_HOSTCMD_SECTION_SORTED
-CONFIG_HOSTCMD_SHI
-CONFIG_HOSTCMD_SKUID
-CONFIG_HOSTCMD_X86
-CONFIG_HOST_COMMAND_STATUS
-CONFIG_HOST_ESPI_VW_POWER_SIGNAL
-CONFIG_HOST_EVENT64
-CONFIG_HOST_EVENT64_REPORT_MASK
-CONFIG_HOST_EVENT_REPORT_MASK
-CONFIG_HWTIMER_64BIT
-CONFIG_HW_CRC
-CONFIG_HW_SPECIFIC_UDELAY
-CONFIG_I2C_BITBANG
-CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE
-CONFIG_I2C_CONTROLLER
-CONFIG_I2C_EXTRA_PACKET_SIZE
-CONFIG_I2C_HID_TOUCHPAD
-CONFIG_I2C_MULTI_PORT_CONTROLLER
-CONFIG_I2C_NACK_RETRY_COUNT
-CONFIG_I2C_PERIPHERAL
-CONFIG_I2C_SCL_GATE_ADDR
-CONFIG_I2C_SCL_GATE_ADDR_FLAGS
-CONFIG_I2C_SCL_GATE_GPIO
-CONFIG_I2C_SCL_GATE_PORT
-CONFIG_I2C_UPDATE_IF_CHANGED
-CONFIG_I2C_XFER_BOARD_CALLBACK
-CONFIG_I2C_XFER_LARGE_TRANSFER
-CONFIG_INA219
-CONFIG_INA231
-CONFIG_INA3221
-CONFIG_INDUCTIVE_CHARGING
-CONFIG_INTEL_RVP_MECC_VERSION_0_9
-CONFIG_INTEL_RVP_MECC_VERSION_1_0
-CONFIG_IO_EXPANDER
-CONFIG_IO_EXPANDER_CCGXXF
-CONFIG_IO_EXPANDER_IT8801
-CONFIG_IO_EXPANDER_IT8801_PWM
-CONFIG_IO_EXPANDER_NCT38XX
-CONFIG_IO_EXPANDER_PCA9534
-CONFIG_IO_EXPANDER_PCA9675
-CONFIG_IO_EXPANDER_PCAL6408
-CONFIG_IO_EXPANDER_PORT_COUNT
-CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-CONFIG_IO_EXPANDER_TCA64XXA
-CONFIG_IPC_SHARED_OBJ_ADDR
-CONFIG_IPC_SHARED_OBJ_BUF_SIZE
-CONFIG_IPI
-CONFIG_IRQ_COUNT
-CONFIG_ISH_BOOT_START
-CONFIG_ISH_CLEAR_FABRIC_ERRORS
-CONFIG_ISH_D0I2_MIN_USEC
-CONFIG_ISH_D0I3_MIN_USEC
-CONFIG_ISH_DW_UART
-CONFIG_ISH_HOST2ISH_COMBINED_ISR
-CONFIG_ISH_IPAPG
-CONFIG_ISH_NEW_PM
-CONFIG_ISH_PM_AONTASK
-CONFIG_ISH_PM_D0I1
-CONFIG_ISH_PM_D0I2
-CONFIG_ISH_PM_D0I3
-CONFIG_ISH_PM_D3
-CONFIG_ISH_PM_RESET_PREP
-CONFIG_ISH_UART_0
-CONFIG_ISL9241_SWITCHING_FREQ
-CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
-CONFIG_IT83XX_FLASH_CLOCK_48MHZ
-CONFIG_IT83XX_HARD_RESET_BY_GPG1
-CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM
-CONFIG_IT83XX_SMCLK2_ON_GPC7
-CONFIG_IT83XX_TUNE_CC_PHY
-CONFIG_IT83XX_VCC_1P8V
-CONFIG_IT83XX_VCC_3P3V
-CONFIG_ITE_FLASH_SUPPORT
-CONFIG_KERNEL_INIT_PRIORITY_DEFAULT
-CONFIG_KEYBOARD_ASSISTANT_KEY
-CONFIG_KEYBOARD_BACKLIGHT
-CONFIG_KEYBOARD_BOOT_KEYS
-CONFIG_KEYBOARD_CUSTOMIZATION
-CONFIG_KEYBOARD_DEBUG
-CONFIG_KEYBOARD_FACTORY_TEST
-CONFIG_KEYBOARD_IRQ_GPIO
-CONFIG_KEYBOARD_KSO_BASE
-CONFIG_KEYBOARD_KSO_HIGH_DRIVE
-CONFIG_KEYBOARD_LANGUAGE_ID
-CONFIG_KEYBOARD_NOT_RAW
-CONFIG_KEYBOARD_POST_SCAN_CLOCKS
-CONFIG_KEYBOARD_PRINT_SCAN_TIMES
-CONFIG_KEYBOARD_REFRESH_ROW3
-CONFIG_KEYBOARD_RUNTIME_KEYS
-CONFIG_KEYBOARD_SCANCODE_CALLBACK
-CONFIG_KEYBOARD_SUPPRESS_NOISE
-CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-CONFIG_KEYBOARD_TEST
-CONFIG_KX022_ORIENTATION_SENSOR
-CONFIG_LED_BAT_ACTIVE_LOW
-CONFIG_LED_DRIVER_DS2413
-CONFIG_LED_DRIVER_LM3509
-CONFIG_LED_DRIVER_LM3630A
-CONFIG_LED_DRIVER_LP5562
-CONFIG_LED_DRIVER_OZ554
-CONFIG_LED_ONOFF_STATES
-CONFIG_LED_ONOFF_STATES_BAT_LOW
-CONFIG_LED_POLICY_STD
-CONFIG_LED_POWER_ACTIVE_LOW
-CONFIG_LED_POWER_LED
-CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
-CONFIG_LED_PWM_CHARGE_COLOR
-CONFIG_LED_PWM_CHARGE_ERROR_COLOR
-CONFIG_LED_PWM_CHARGE_STATE_ONLY
-CONFIG_LED_PWM_LOW_BATT_COLOR
-CONFIG_LED_PWM_NEAR_FULL_COLOR
-CONFIG_LED_PWM_SOC_ON_COLOR
-CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-CONFIG_LFW_OFFSET
-CONFIG_LIBCRYPTOC
-CONFIG_LID_ANGLE_INVALID_CHECK
-CONFIG_LID_ANGLE_SENSOR_BASE
-CONFIG_LID_ANGLE_SENSOR_LID
-CONFIG_LID_ANGLE_TABLET_MODE
-CONFIG_LID_SWITCH_GPIO_LIST
-CONFIG_LIGHTBAR_POWER_RAILS
-CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
-CONFIG_LLSR_TEST
-CONFIG_LN9310
-CONFIG_LOADER_MEM_OFF
-CONFIG_LOADER_SIZE
-CONFIG_LOADER_STORAGE_OFF
-CONFIG_LOG
-CONFIG_LOW_POWER_IDLE_LIMITED
-CONFIG_LOW_POWER_S0
-CONFIG_LOW_POWER_USE_LFIOSC
-CONFIG_LPRAM_BASE
-CONFIG_LPRAM_SIZE
-CONFIG_LSM6DSM_SEC_I2C
-CONFIG_MAC_ADDR
-CONFIG_MAC_ADDR_LEN
-CONFIG_MAG_BMI_BMM150
-CONFIG_MAG_BMI_LIS2MDL
-CONFIG_MAG_BMM150
-CONFIG_MAG_CALIBRATE
-CONFIG_MAG_LIS2MDL
-CONFIG_MAG_LSM6DSM_BMM150
-CONFIG_MAG_LSM6DSM_LIS2MDL
-CONFIG_MALLOC
-CONFIG_MAPPED_STORAGE_BASE
-CONFIG_MATH_UTIL
-CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
-CONFIG_MCDP28X0
-CONFIG_MCHP_48MHZ_OUT
-CONFIG_MCHP_DEBUG_LPC
-CONFIG_MCHP_DEEP_SLP_DEBUG
-CONFIG_MCHP_DEEP_SLP_GPIO_PWR_DOWN
-CONFIG_MCHP_ESPI_DEBUG
-CONFIG_MCHP_ESPI_EC_CMD
-CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
-CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
-CONFIG_MCHP_GPSPI
-CONFIG_MCHP_GPSPI_TX_DMA
-CONFIG_MCHP_I2C0_SLAVE_ADDRS
-CONFIG_MCHP_I2C1_SLAVE_ADDRS
-CONFIG_MCHP_I2C2_SLAVE_ADDRS
-CONFIG_MCHP_I2C3_SLAVE_ADDRS
-CONFIG_MCHP_I2C4_SLAVE_ADDRS
-CONFIG_MCHP_I2C5_SLAVE_ADDRS
-CONFIG_MCHP_I2C6_SLAVE_ADDRS
-CONFIG_MCHP_I2C7_SLAVE_ADDRS
-CONFIG_MCHP_JTAG_MODE
-CONFIG_MCHP_LFW_DEBUG
-CONFIG_MCHP_QMSPI_TX_DMA
-CONFIG_MCHP_TFDP
-CONFIG_MEC1701_TFDP
-CONFIG_MEC_GPIO_EC_CMDS
-CONFIG_MEC_SRAM_BASE_END
-CONFIG_MEC_SRAM_BASE_START
-CONFIG_MEC_SRAM_SIZE
-CONFIG_MEC_TEST_EC_RORW_CRC
-CONFIG_MEMORY_REGIONS
-CONFIG_MFT_INPUT_LFCLK
-CONFIG_MIA_WDT_VEC
-CONFIG_MKBP_
-CONFIG_MKBP_USE_
-CONFIG_MKBP_USE_HECI
-CONFIG_MOTION_FILL_LPC_SENSE_DATA
-CONFIG_MOTION_MIN_SENSE_WAIT_TIME
-CONFIG_MOTION_SENSE_RESUME_DELAY_US
-CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
-CONFIG_MP4245
-CONFIG_NAME
-CONFIG_NB7V904M_LPM_OVERRIDE
-CONFIG_NO_PINHOLD
-CONFIG_NUM_FIXED_BATTERIES
-CONFIG_OCPC
-CONFIG_OCPC_DEF_RBATT_MOHMS
-CONFIG_ONEWIRE
-CONFIG_ONLINE_CALIB
-CONFIG_ONLINE_CALIB_SPOOF_MODE
-CONFIG_ORIENTATION_SENSOR
-CONFIG_OTP
-CONFIG_PANIC_DATA_BASE
-CONFIG_PANIC_DATA_SIZE
-CONFIG_PD_RETRY_COUNT
-CONFIG_PD_USE_DAC_AS_REF
-CONFIG_PECI
-CONFIG_PECI_COMMON
-CONFIG_PECI_TJMAX
-CONFIG_PERIPHERAL_CHARGER
-CONFIG_PLATFORM_EC_
-CONFIG_PLATFORM_EC_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-CONFIG_PMIC_FW_LONG_PRESS_TIMER
-CONFIG_PMU_HARD_RESET
-CONFIG_POLLING_UART
-CONFIG_PORT80_HISTORY_LEN
-CONFIG_PORT80_PRINT_IN_INT
-CONFIG_POWER_BUTTON_FLAGS
-CONFIG_POWER_BUTTON_IGNORE_LID
-CONFIG_POWER_BUTTON_INIT_IDLE
-CONFIG_POWER_BUTTON_INIT_TIMEOUT
-CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
-CONFIG_POWER_BUTTON_X86
-CONFIG_POWER_COMMON
-CONFIG_POWER_PP5000_CONTROL
-CONFIG_POWER_S0IX
-CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
-CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
-CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
-CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-CONFIG_PRESERVE_LOGS
-CONFIG_PRINTF_LEGACY_LI_FORMAT
-CONFIG_PRINT_IN_INT
-CONFIG_PROGRAM_MEMORY_BASE
-CONFIG_PROGRAM_MEMORY_BASE_LOAD
-CONFIG_PS2
-CONFIG_PSTORE
-CONFIG_PVD
-CONFIG_PWM_INPUT_LFCLK
-CONFIG_PWR_STATE_DISCHARGE_FULL
-CONFIG_RAM_BANKS
-CONFIG_RAM_BANK_SIZE
-CONFIG_RAM_BASE
-CONFIG_RAM_SIZE
-CONFIG_REGULATOR_IR357X
-CONFIG_RESTRICTED_CONSOLE_COMMANDS
-CONFIG_RMA_AUTH
-CONFIG_RMA_AUTH_USE_P256
-CONFIG_RNG
-CONFIG_ROLLBACK
-CONFIG_ROLLBACK_MPU_PROTECT
-CONFIG_ROLLBACK_OFF
-CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
-CONFIG_ROLLBACK_SECRET_SIZE
-CONFIG_ROLLBACK_SIZE
-CONFIG_ROLLBACK_UPDATE
-CONFIG_ROLLBACK_VERSION
-CONFIG_ROM_BASE
-CONFIG_ROM_SIZE
-CONFIG_RO_HDR_MEM_OFF
-CONFIG_RO_HDR_SIZE
-CONFIG_RO_HEAD_ROOM
-CONFIG_RO_MEM_OFF
-CONFIG_RO_MEM_SIZE
-CONFIG_RO_PUBKEY_ADDR
-CONFIG_RO_PUBKEY_SIZE
-CONFIG_RO_PUBKEY_STORAGE_OFF
-CONFIG_RO_ROM_RESIDENT_MEM_OFF
-CONFIG_RO_ROM_RESIDENT_SIZE
-CONFIG_RO_SIZE
-CONFIG_RO_STORAGE_OFF
-CONFIG_RPMSG_NAME_SERVICE
-CONFIG_RSA
-CONFIG_RSA_EXPONENT_3
-CONFIG_RSA_KEY_SIZE
-CONFIG_RSA_OPTIMIZED
-CONFIG_RWSIG
-CONFIG_RWSIG_DONT_CHECK_ON_PIN_RESET
-CONFIG_RWSIG_JUMP_TIMEOUT
-CONFIG_RWSIG_TYPE_RWSIG
-CONFIG_RWSIG_TYPE_USBPD1
-CONFIG_RW_A_SIGN_STORAGE_OFF
-CONFIG_RW_A_STORAGE_OFF
-CONFIG_RW_B
-CONFIG_RW_BOOT_HEADER_STORAGE_OFF
-CONFIG_RW_BOOT_HEADER_STORAGE_SIZE
-CONFIG_RW_B_MEM_OFF
-CONFIG_RW_B_SIGN_STORAGE_OFF
-CONFIG_RW_B_SIG_ADDR
-CONFIG_RW_B_STORAGE_OFF
-CONFIG_RW_HEAD_ROOM
-CONFIG_RW_MEM_OFF
-CONFIG_RW_MEM_SIZE
-CONFIG_RW_ROM_RESIDENT_MEM_OFF
-CONFIG_RW_ROM_RESIDENT_SIZE
-CONFIG_RW_SIG_ADDR
-CONFIG_RW_SIG_SIZE
-CONFIG_RW_SIZE
-CONFIG_RW_STORAGE_OFF
-CONFIG_SB_PASSTHROUGH
-CONFIG_SCI_GPIO
-CONFIG_SENSORHUB_LSM6DSM
-CONFIG_SENSOR_ORIENTATION
-CONFIG_SERIALNO_LEN
-CONFIG_SEVEN_SEG_DISPLAY
-CONFIG_SHA256
-CONFIG_SHA256_HW
-CONFIG_SHA256_UNROLLED
-CONFIG_SHAREDLIB
-CONFIG_SHAREDLIB_MEM_OFF
-CONFIG_SHAREDLIB_SIZE
-CONFIG_SHAREDLIB_STORAGE_OFF
-CONFIG_SHAREDMEM_MINIMUM_SIZE
-CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG
-CONFIG_SIMULATED_BUTTON
-CONFIG_SLEEP_TIMEOUT_MS
-CONFIG_SMBUS
-CONFIG_SOFTWARE_CLZ
-CONFIG_SOFTWARE_CTZ
-CONFIG_SOMETHING
-CONFIG_SPI
-CONFIG_SPI_ACCEL_PORT
-CONFIG_SPI_CONTROLLER
-CONFIG_SPI_CS_GPIO
-CONFIG_SPI_FLASH
-CONFIG_SPI_FLASH_GD25LQ40
-CONFIG_SPI_FLASH_GD25Q41B
-CONFIG_SPI_FLASH_HAS_SR2
-CONFIG_SPI_FLASH_PORT
-CONFIG_SPI_FLASH_READ_WAIT_MS
-CONFIG_SPI_FLASH_W25Q128
-CONFIG_SPI_FLASH_W25Q40
-CONFIG_SPI_FLASH_W25Q64
-CONFIG_SPI_FLASH_W25Q80
-CONFIG_SPI_FLASH_W25X40
-CONFIG_SPI_FP_PORT
-CONFIG_SPI_HALFDUPLEX
-CONFIG_SPI_NOR
-CONFIG_SPI_NOR_BLOCK_ERASE
-CONFIG_SPI_NOR_DEBUG
-CONFIG_SPI_NOR_MAX_MESSAGE_SIZE
-CONFIG_SPI_NOR_MAX_READ_SIZE
-CONFIG_SPI_NOR_MAX_WRITE_SIZE
-CONFIG_SPI_NOR_SMART_ERASE
-CONFIG_SPI_PROTOCOL_V2
-CONFIG_SPI_RX_BUF_SIZE
-CONFIG_SPI_TOUCHPAD_PORT
-CONFIG_SPI_TX_BUF_SIZE
-CONFIG_STACK_SIZE
-CONFIG_STANDARD_OUTPUT
-CONFIG_STEINHART_HART_6V0_51K1_47K_4050B
-CONFIG_STM32G4_UCPD_DEBUG
-CONFIG_STM32L_FAKE_HIBERNATE
-CONFIG_STM32_CHARGER_DETECT
-CONFIG_STM32_CLOCK_HSE_HZ
-CONFIG_STM32_CLOCK_LSE
-CONFIG_STM32_SPI1_CONTROLLER
-CONFIG_STM_HWTIMER32
-CONFIG_STREAM_SIGNATURE
-CONFIG_STREAM_USART
-CONFIG_STREAM_USART1
-CONFIG_STREAM_USART2
-CONFIG_STREAM_USART3
-CONFIG_STREAM_USART4
-CONFIG_STREAM_USB
-CONFIG_SUPPORT_CHIP_HIBERNATION
-CONFIG_SUPPRESSED_HOST_COMMANDS
-CONFIG_SWITCH_DEDICATED_RECOVERY
-CONFIG_SW_CRC
-CONFIG_SYNC
-CONFIG_SYNC_COMMAND
-CONFIG_SYNC_INT_EVENT
-CONFIG_SYNC_QUEUE_SIZE
-CONFIG_SYV682X_HV_ILIM
-CONFIG_TASK_LIST
-CONFIG_TASK_PROFILING
-CONFIG_TASK_RESET_LIST
-CONFIG_TCPC_I2C_BASE_ADDR
-CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
-CONFIG_TCS_USE_LUX_TABLE
-CONFIG_TEMP_CACHE_STALE_THRES
-CONFIG_TEMP_SENSOR_ADT7481
-CONFIG_TEMP_SENSOR_AMD_R19ME4070
-CONFIG_TEMP_SENSOR_BD99992GW
-CONFIG_TEMP_SENSOR_EC_ADC
-CONFIG_TEMP_SENSOR_F75303
-CONFIG_TEMP_SENSOR_G753
-CONFIG_TEMP_SENSOR_G781
-CONFIG_TEMP_SENSOR_G782
-CONFIG_TEMP_SENSOR_OTI502
-CONFIG_TEMP_SENSOR_POWER_GPIO
-CONFIG_TEMP_SENSOR_SB_TSI
-CONFIG_TEMP_SENSOR_TMP006
-CONFIG_TEMP_SENSOR_TMP112
-CONFIG_TEMP_SENSOR_TMP411
-CONFIG_TEMP_SENSOR_TMP432
-CONFIG_TEMP_SENSOR_TMP468
-CONFIG_TEST_1P8V
-CONFIG_TEST_MOCK_LIST
-CONFIG_TEST_SM
-CONFIG_TEST_TASK_LIST
-CONFIG_TEST_USB_PE_SM
-CONFIG_THERMISTOR_NCP15WB
-CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-CONFIG_THROTTLE_AP_ON_BAT_OLTAGE
-CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
-CONFIG_TICK
-CONFIG_TOUCHPAD
-CONFIG_TOUCHPAD_ELAN
-CONFIG_TOUCHPAD_FW_CHUNKS
-CONFIG_TOUCHPAD_GT7288
-CONFIG_TOUCHPAD_HASH_FW
-CONFIG_TOUCHPAD_I2C_ADDR_FLAGS
-CONFIG_TOUCHPAD_I2C_PORT
-CONFIG_TOUCHPAD_ST
-CONFIG_TOUCHPAD_VIRTUAL_OFF
-CONFIG_TOUCHPAD_VIRTUAL_SIZE
-CONFIG_TRICKLE_CHARGING
-CONFIG_TUSB544_EQ_BY_REGISTER
-CONFIG_UART_BAUD_RATE
-CONFIG_UART_CONSOLE
-CONFIG_UART_HOST
-CONFIG_UART_HOST_COMMAND_BAUD_RATE
-CONFIG_UART_HOST_COMMAND_HW
-CONFIG_UART_INPUT_FILTER
-CONFIG_UART_PAD_SWITCH
-CONFIG_UART_RX_BUF_SIZE
-CONFIG_UART_RX_DMA
-CONFIG_UART_RX_DMA_CH
-CONFIG_UART_RX_DMA_RECHECKS
-CONFIG_UART_RX_REQ_CH
-CONFIG_UART_TX_BUF_SIZE
-CONFIG_UART_TX_DMA
-CONFIG_UART_TX_DMA_CH
-CONFIG_UART_TX_DMA_PH
-CONFIG_UART_TX_REQ_CH
-CONFIG_UNDEFINED
-CONFIG_UPDATE_PDU_SIZE
-CONFIG_USART_HOST_COMMAND
-CONFIG_USB
-CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
-CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF
-CONFIG_USBC_PPC_AOZ1380
-CONFIG_USBC_PPC_NX20P3481
-CONFIG_USBC_PPC_NX20P3483
-CONFIG_USBC_RETIMER_NB7V904M
-CONFIG_USBC_RETIMER_PI3DPX1207
-CONFIG_USBC_RETIMER_PI3HDX1204
-CONFIG_USBC_RETIMER_PS8802
-CONFIG_USBC_RETIMER_PS8818
-CONFIG_USBC_RETIMER_TUSB544
-CONFIG_USBC_VCONN_SWAP
-CONFIG_USBC_VCONN_SWAP_DELAY_US
-CONFIG_USB_
-CONFIG_USB_ALT_MODE_ADAPTER
-CONFIG_USB_BOS
-CONFIG_USB_CONSOLE
-CONFIG_USB_CONSOLE_CRC
-CONFIG_USB_CONSOLE_READ
-CONFIG_USB_CONSOLE_STREAM
-CONFIG_USB_CONSOLE_TX_BUF_SIZE
-CONFIG_USB_DWC_FS
-CONFIG_USB_FRS
-CONFIG_USB_GPIO
-CONFIG_USB_HID
-CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS
-CONFIG_USB_HID_KEYBOARD
-CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-CONFIG_USB_HID_KEYBOARD_VIVALDI
-CONFIG_USB_HID_TOUCHPAD
-CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE
-CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X
-CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y
-CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X
-CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y
-CONFIG_USB_HUB_GL3590
-CONFIG_USB_I2C
-CONFIG_USB_I2C_MAX_READ_COUNT
-CONFIG_USB_I2C_MAX_WRITE_COUNT
-CONFIG_USB_INHIBIT_CONNECT
-CONFIG_USB_INHIBIT_INIT
-CONFIG_USB_ISOCHRONOUS
-CONFIG_USB_MAXPOWER_MA
-CONFIG_USB_MUX_AMD_FP5
-CONFIG_USB_MUX_AMD_FP6
-CONFIG_USB_MUX_ANX3443
-CONFIG_USB_MUX_ANX7440
-CONFIG_USB_MUX_ANX7451
-CONFIG_USB_MUX_AP_ACK_REQUEST
-CONFIG_USB_MUX_IT5205H_SBU_OVP
-CONFIG_USB_MUX_PI3USB30532
-CONFIG_USB_MUX_PI3USB31532
-CONFIG_USB_MUX_PS8740
-CONFIG_USB_MUX_PS8742
-CONFIG_USB_MUX_PS8822
-CONFIG_USB_MUX_TUSB1064
-CONFIG_USB_PAIRING
-CONFIG_USB_PD_3A_PORTS
-CONFIG_USB_PD_5V_CHARGER_CTRL
-CONFIG_USB_PD_5V_EN_ACTIVE_LOW
-CONFIG_USB_PD_ALT_MODE_UFP_DP
-CONFIG_USB_PD_ANX7688
-CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
-CONFIG_USB_PD_COMM_DISABLED
-CONFIG_USB_PD_COMM_LOCKED
-CONFIG_USB_PD_CUSTOM_PDO
-CONFIG_USB_PD_DEBUG_DR
-CONFIG_USB_PD_DPS
-CONFIG_USB_PD_DYNAMIC_SRC_CAP
-CONFIG_USB_PD_EXTENDED_MESSAGES
-CONFIG_USB_PD_FLASH
-CONFIG_USB_PD_FLASH_ERASE_CHECK
-CONFIG_USB_PD_GIVE_BACK
-CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR
-CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR
-CONFIG_USB_PD_I2C_ADDR_FLAGS
-CONFIG_USB_PD_IDENTITY_HW_VERS
-CONFIG_USB_PD_IDENTITY_SW_VERS
-CONFIG_USB_PD_INITIAL_DRP_STATE
-CONFIG_USB_PD_INTERNAL_COMP
-CONFIG_USB_PD_LOW_POWER
-CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
-CONFIG_USB_PD_MANUFACTURER_INFO
-CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-CONFIG_USB_PD_MAX_TOTAL_SOURCE_CURRENT
-CONFIG_USB_PD_MODEL_PART_NUMBER
-CONFIG_USB_PD_PCIE_TUNNELING
-CONFIG_USB_PD_PORT_LABEL
-CONFIG_USB_PD_PREFER_MV
-CONFIG_USB_PD_PRODUCT_REVISION
-CONFIG_USB_PD_PULLUP
-CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-CONFIG_USB_PD_RESET_MIN_BATT_SOC
-CONFIG_USB_PD_RX_COMP_IRQ
-CONFIG_USB_PD_SECURITY_MSGS
-CONFIG_USB_PD_SIMPLE_DFP
-CONFIG_USB_PD_TBT_GEN3_CAPABLE
-CONFIG_USB_PD_TCPC
-CONFIG_USB_PD_TCPC_BOARD_INIT
-CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-CONFIG_USB_PD_TCPC_ON_CHIP
-CONFIG_USB_PD_TCPC_TRACK_VBUS
-CONFIG_USB_PD_TCPMV1
-CONFIG_USB_PD_TCPMV1_DEBUG
-CONFIG_USB_PD_TCPMV2
-CONFIG_USB_PD_TCPM_ANX3429
-CONFIG_USB_PD_TCPM_ANX740X
-CONFIG_USB_PD_TCPM_ANX741X
-CONFIG_USB_PD_TCPM_ANX7447
-CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
-CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
-CONFIG_USB_PD_TCPM_ANX74XX
-CONFIG_USB_PD_TCPM_ANX7688
-CONFIG_USB_PD_TCPM_CCGXXF
-CONFIG_USB_PD_TCPM_FUSB302
-CONFIG_USB_PD_TCPM_FUSB307
-CONFIG_USB_PD_TCPM_MT6370
-CONFIG_USB_PD_TCPM_NCT38XX
-CONFIG_USB_PD_TCPM_PS8
-CONFIG_USB_PD_TCPM_PS8705
-CONFIG_USB_PD_TCPM_PS875
-CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
-CONFIG_USB_PD_TCPM_PS8755
-CONFIG_USB_PD_TCPM_RAA489000
-CONFIG_USB_PD_TCPM_STM32GX
-CONFIG_USB_PD_TCPM_STUB
-CONFIG_USB_PD_TID
-CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC
-CONFIG_USB_PD_TX_PHY_ONLY
-CONFIG_USB_PD_USB4_DRD
-CONFIG_USB_PD_VBUS_DETECT_GPIO
-CONFIG_USB_PORT_ENABLE_DYNAMIC
-CONFIG_USB_PORT_POWER_SMART
-CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
-CONFIG_USB_PORT_POWER_SMART_INVERTED
-CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
-CONFIG_USB_PORT_POWER_SMART_SIMPLE
-CONFIG_USB_POWER
-CONFIG_USB_RAM_ACCESS_SIZE
-CONFIG_USB_RAM_ACCESS_TYPE
-CONFIG_USB_RAM_BASE
-CONFIG_USB_RAM_SIZE
-CONFIG_USB_REMOTE_WAKEUP
-CONFIG_USB_SELF_POWERED
-CONFIG_USB_SERIALNO
-CONFIG_USB_SPI
-CONFIG_USB_SUSPEND
-CONFIG_USB_UPDATE
-CONFIG_VALUE
-CONFIG_VBOOT_EFS
-CONFIG_VBOOT_EFS2
-CONFIG_WATCHDOG_HELP
-CONFIG_WATCHDOG_MAX_RETRIES
-CONFIG_WEBUSB_URL
-CONFIG_WIRELESS
-CONFIG_WIRELESS_CHARGER_P9221_R7
-CONFIG_WIRELESS_SUSPEND
-CONFIG_WLAN_POWER_ACTIVE_LOW
-CONFIG_WOV_FIFO_THRESH_WORDS
-CONFIG_WOV_THRESHOLD_WORDS
-CONFIG_WP_ACTIVE_HIGH
-CONFIG_WP_ALWAYS
-CONFIG_WP_STORAGE_OFF
-CONFIG_WP_STORAGE_SIZE
-CONFIG_X86_64
-CONFIG_ZEPHYR
-CONFIG_ZTEST
diff --git a/util/config_option_check.py b/util/config_option_check.py
deleted file mode 100755
index 29e8fb8611..0000000000
--- a/util/config_option_check.py
+++ /dev/null
@@ -1,388 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Configuration Option Checker.
-
-Script to ensure that all configuration options for the Chrome EC are defined
-in config.h.
-"""
-from __future__ import print_function
-import enum
-import os
-import re
-import subprocess
-import sys
-
-
-class Line(object):
-  """Class for each changed line in diff output.
-
-  Attributes:
-    line_num: The integer line number that this line appears in the file.
-    string: The literal string of this line.
-    line_type: '+' or '-' indicating if this line was an addition or
-      deletion.
-  """
-
-  def __init__(self, line_num, string, line_type):
-    """Inits Line with the line number and the actual string."""
-    self.line_num = line_num
-    self.string = string
-    self.line_type = line_type
-
-
-class Hunk(object):
-  """Class for a git diff hunk.
-
-  Attributes:
-    filename: The name of the file that this hunk belongs to.
-    lines: A list of Line objects that are a part of this hunk.
-  """
-
-  def __init__(self, filename, lines):
-    """Inits Hunk with the filename and the list of lines of the hunk."""
-    self.filename = filename
-    self.lines = lines
-
-
-# Master file which is supposed to include all CONFIG_xxxx descriptions.
-CONFIG_FILE = 'include/config.h'
-
-# Specific files which the checker should ignore.
-ALLOWLIST = [CONFIG_FILE, 'util/config_option_check.py']
-
-# Specific directories which the checker should ignore.
-ALLOW_PATTERN = re.compile('zephyr/.*')
-
-# Specific CONFIG_* flags which the checker should ignore.
-ALLOWLIST_CONFIGS = ['CONFIG_ZTEST']
-
-def obtain_current_config_options():
-  """Obtains current config options from include/config.h.
-
-  Scans through the master config file defined in CONFIG_FILE for all CONFIG_*
-  options.
-
-  Returns:
-    config_options: A list of all the config options in the master CONFIG_FILE.
-  """
-
-  config_options = []
-  config_option_re = re.compile(r'^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)')
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      result = config_option_re.search(line)
-      if not result:
-        continue
-      word = result.groups()[1]
-      if word not in config_options:
-        config_options.append(word)
-  return config_options
-
-def obtain_config_options_in_use():
-  """Obtains all the config options in use in the repo.
-
-  Scans through the entire repo looking for all CONFIG_* options actively used.
-
-  Returns:
-   options_in_use: A set of all the config options in use in the repo.
-  """
-  file_list = []
-  cwd = os.getcwd()
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-  config_debug_option_re = re.compile(r'\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)')
-  options_in_use = set()
-  for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True):
-    # Ignore the build and private directories (taken from .gitignore)
-    if 'build' in dirnames:
-      dirnames.remove('build')
-    if 'private' in dirnames:
-      dirnames.remove('private')
-    for f in filenames:
-      # Ignore hidden files.
-      if f.startswith('.'):
-        continue
-      # Only consider C source, assembler, and Make-style files.
-      if (os.path.splitext(f)[1] in ('.c', '.h', '.inc', '.S', '.mk') or
-          'Makefile' in f):
-        file_list.append(os.path.join(dirpath, f))
-
-  # Search through each file and build a set of the CONFIG_* options being
-  # used.
-
-  for f in file_list:
-    if CONFIG_FILE in f:
-      continue
-    with open(f, 'r') as cur_file:
-      for line in cur_file:
-        match = config_option_re.findall(line)
-        if match:
-          for option in match:
-            if not in_comment(f, line, option):
-              if option not in options_in_use:
-                options_in_use.add(option)
-
-  # Since debug options can be turned on at any time, assume that they are
-  # always in use in case any aren't being used.
-
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      match = config_debug_option_re.findall(line)
-      if match:
-        for option in match:
-          if not in_comment(CONFIG_FILE, line, option):
-            if option not in options_in_use:
-              options_in_use.add(option)
-
-  return options_in_use
-
-def print_missing_config_options(hunks, config_options):
-  """Searches thru all the changes in hunks for missing options and prints them.
-
-  Args:
-    hunks: A list of Hunk objects which represent the hunks from the git
-      diff output.
-    config_options: A list of all the config options in the master CONFIG_FILE.
-
-  Returns:
-    missing_config_option: A boolean indicating if any CONFIG_* options
-      are missing from the master CONFIG_FILE in this commit or if any CONFIG_*
-      options removed are no longer being used in the repo.
-  """
-  missing_config_option = False
-  print_banner = True
-  deprecated_options = set()
-  # Determine longest CONFIG_* length to be used for formatting.
-  max_option_length = max(len(option) for option in config_options)
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-
-  # Search for all CONFIG_* options in use in the repo.
-  options_in_use = obtain_config_options_in_use()
-
-  # Check each hunk's line for a missing config option.
-  for h in hunks:
-    for l in h.lines:
-      # Check for the existence of a CONFIG_* in the line.
-      match = filter(lambda opt: opt in ALLOWLIST_CONFIGS,
-                     config_option_re.findall(l.string))
-      if not match:
-        continue
-
-      # At this point, an option was found in the line.  However, we need to
-      # verify that it is not within a comment.
-      violations = set()
-
-      for option in match:
-        if not in_comment(h.filename, l.string, option):
-          # Since the CONFIG_* option is not within a comment, we've found a
-          # violation.  We now need to determine if this line is a deletion or
-          # not.  For deletions, we will need to verify if this CONFIG_* option
-          # is no longer being used in the entire repo.
-
-          if l.line_type == '-':
-            if option not in options_in_use and option in config_options:
-              deprecated_options.add(option)
-          else:
-            violations.add(option)
-
-      # Check to see if the CONFIG_* option is in the config file and print the
-      # violations.
-      for option in match:
-        if option not in config_options and option in violations:
-          # Print the banner once.
-          if print_banner:
-            print('The following config options were found to be missing '
-                  'from %s.\n'
-                  'Please add new config options there along with '
-                  'descriptions.\n\n' % CONFIG_FILE)
-            print_banner = False
-            missing_config_option = True
-          # Print the misssing config option.
-          print('> %-*s %s:%s' % (max_option_length, option,
-                                  h.filename,
-                                  l.line_num))
-
-  if deprecated_options:
-    print('\n\nThe following config options are being removed and also appear'
-          ' to be the last uses\nof that option.  Please remove these '
-          'options from %s.\n\n' % CONFIG_FILE)
-    for option in deprecated_options:
-      print('> %s' % option)
-      missing_config_option = True
-
-  return missing_config_option
-
-def in_comment(filename, line, substr):
-  """Checks if given substring appears in a comment.
-
-  Args:
-    filename: The filename where this line is from.  This is used to determine
-      what kind of comments to look for.
-    line: String of line to search in.
-    substr: Substring to search for in the line.
-
-  Returns:
-    is_in_comment: Boolean indicating if substr was in a comment.
-  """
-
-  c_style_ext = ('.c', '.h', '.inc', '.S')
-  make_style_ext = ('.mk')
-  is_in_comment = False
-
-  extension = os.path.splitext(filename)[1]
-  substr_idx = line.find(substr)
-
-  # Different files have different comment syntax;  Handle appropriately.
-  if extension in c_style_ext:
-    beg_comment_idx = line.find('/*')
-    end_comment_idx = line.find('*/')
-    if end_comment_idx == -1:
-      end_comment_idx = len(line)
-
-    if beg_comment_idx == -1:
-      # Check to see if this line is from a multi-line comment.
-      if line.lstrip().startswith('* '):
-        # It _seems_ like it is.
-        is_in_comment = True
-    else:
-      # Check to see if its actually inside the comment.
-      if beg_comment_idx < substr_idx < end_comment_idx:
-        is_in_comment = True
-  elif extension in make_style_ext or 'Makefile' in filename:
-    beg_comment_idx = line.find('#')
-    # Ignore everything to the right of the hash.
-    if beg_comment_idx < substr_idx and beg_comment_idx != -1:
-      is_in_comment = True
-  return is_in_comment
-
-def get_hunks():
-  """Gets the hunks of the most recent commit.
-
-  States:
-    new_file: Searching for a new file in the git diff.
-    filename_search: Searching for the filename of this hunk.
-    hunk: Searching for the beginning of a new hunk.
-    lines: Counting line numbers and searching for changes.
-
-  Returns:
-    hunks: A list of Hunk objects which represent the hunks in the git diff
-      output.
-  """
-
-  diff = []
-  hunks = []
-  hunk_lines = []
-  line = ''
-  filename = ''
-  i = 0
-  line_num = 0
-
-  # Regex patterns
-  new_file_re = re.compile(r'^diff --git')
-  filename_re = re.compile(r'^[+]{3} (.*)')
-  hunk_line_num_re = re.compile(r'^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*')
-  line_re = re.compile(r'^([+| |-])(.*)')
-
-  # Get the diff output.
-  proc = subprocess.run(['git', 'diff', '--cached', '-GCONFIG_*', '--no-prefix',
-                         '--no-ext-diff', 'HEAD~1'],
-                        stdout=subprocess.PIPE,
-                        encoding='utf-8',
-                        check=True)
-  diff = proc.stdout.splitlines()
-  if not diff:
-    return []
-  line = diff[0]
-
-  state = enum.Enum('state', 'NEW_FILE FILENAME_SEARCH HUNK LINES')
-  current_state = state.NEW_FILE
-
-  while True:
-    # Search for the beginning of a new file.
-    if current_state is state.NEW_FILE:
-      match = new_file_re.search(line)
-      if match:
-        current_state = state.FILENAME_SEARCH
-
-    # Search the diff output for a file name.
-    elif current_state is state.FILENAME_SEARCH:
-      # Search for a file name.
-      match = filename_re.search(line)
-      if match:
-        filename = match.groups(1)[0]
-        if filename in ALLOWLIST or ALLOW_PATTERN.match(filename):
-          # Skip the file if it's allowlisted.
-          current_state = state.NEW_FILE
-        else:
-          current_state = state.HUNK
-
-    # Search for a hunk.  Each hunk starts with a line describing the line
-    # numbers in the file.
-    elif current_state is state.HUNK:
-      hunk_lines = []
-      match = hunk_line_num_re.search(line)
-      if match:
-        # Extract the line number offset.
-        line_num = int(match.groups(1)[0])
-        current_state = state.LINES
-
-    # Start looking for changes.
-    elif current_state is state.LINES:
-      # Check if state needs updating.
-      new_hunk = hunk_line_num_re.search(line)
-      new_file = new_file_re.search(line)
-      if new_hunk:
-        current_state = state.HUNK
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-      elif new_file:
-        current_state = state.NEW_FILE
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-
-      match = line_re.search(line)
-      if match:
-        line_type = match.groups(1)[0]
-        # We only care about modifications.
-        if line_type != ' ':
-          hunk_lines.append(Line(line_num, match.groups(2)[1], line_type))
-        # Deletions don't count towards the line numbers.
-        if line_type != '-':
-          line_num += 1
-
-    # Advance to the next line
-    try:
-      i += 1
-      line = diff[i]
-    except IndexError:
-      # We've reached the end of the diff.  Return what we have.
-      if hunk_lines:
-        hunks.append(Hunk(filename, hunk_lines))
-      return hunks
-
-def main():
-  """Searches through committed changes for missing config options.
-
-  Checks through committed changes for CONFIG_* options.  Then checks to make
-  sure that all CONFIG_* options used are defined in include/config.h.  Finally,
-  reports any missing config options.
-  """
-  # Obtain the hunks of the commit to search through.
-  hunks = get_hunks()
-  # Obtain config options from include/config.h.
-  config_options = obtain_current_config_options()
-  # Find any missing config options from the hunks and print them.
-  missing_opts = print_missing_config_options(hunks, config_options)
-
-  if missing_opts:
-    print('\nIt may also be possible that you have a typo.')
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
diff --git a/util/cros_ec_dev.h b/util/cros_ec_dev.h
deleted file mode 100644
index 41930f97dd..0000000000
--- a/util/cros_ec_dev.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __UTIL_CROS_EC_DEV_H
-#define __UTIL_CROS_EC_DEV_H
-
-#include <linux/ioctl.h>
-#include <linux/types.h>
-#include "ec_commands.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CROS_EC_DEV_NAME "cros_ec"
-#define CROS_EC_DEV_VERSION "1.0.0"
-
-/*
- * @version: Command version number (often 0)
- * @command: Command to send (EC_CMD_...)
- * @outdata: Outgoing data to EC
- * @outsize: Outgoing length in bytes
- * @indata: Where to put the incoming data from EC
- * @insize: On call, how much we can accept. On return, how much we got.
- * @result: EC's response to the command (separate from communication failure)
- * ioctl returns zero on success, negative on error
- */
-struct cros_ec_command {
-	uint32_t version;
-	uint32_t command;
-	uint8_t *outdata;
-	uint32_t outsize;
-	uint8_t *indata;
-	uint32_t insize;
-	uint32_t result;
-};
-
-/*
- * @offset: within EC_LPC_ADDR_MEMMAP region
- * @bytes: number of bytes to read. zero means "read a string" (including '\0')
- *         (at most only EC_MEMMAP_SIZE bytes can be read)
- * @buffer: where to store the result
- * ioctl returns the number of bytes read, negative on error
- */
-struct cros_ec_readmem {
-	uint32_t offset;
-	uint32_t bytes;
-	char *buffer;
-};
-
-#define CROS_EC_DEV_IOC              ':'
-#define CROS_EC_DEV_IOCXCMD    _IOWR(':', 0, struct cros_ec_command)
-#define CROS_EC_DEV_IOCRDMEM   _IOWR(':', 1, struct cros_ec_readmem)
-
-/*
- * @version: Command version number (often 0)
- * @command: Command to send (EC_CMD_...)
- * @outsize: Outgoing length in bytes
- * @insize: Max number of bytes to accept from EC
- * @result: EC's response to the command (separate from communication failure)
- * @data: Where to put the incoming data from EC and outgoing data to EC
- */
-struct cros_ec_command_v2 {
-	uint32_t version;
-	uint32_t command;
-	uint32_t outsize;
-	uint32_t insize;
-	uint32_t result;
-	uint8_t data[0];
-};
-
-/*
- * @offset: within EC_LPC_ADDR_MEMMAP region
- * @bytes: number of bytes to read. zero means "read a string" (including '\0')
- *         (at most only EC_MEMMAP_SIZE bytes can be read)
- * @buffer: where to store the result
- * ioctl returns the number of bytes read, negative on error
- */
-struct cros_ec_readmem_v2 {
-	uint32_t offset;
-	uint32_t bytes;
-	uint8_t buffer[EC_MEMMAP_SIZE];
-};
-
-#define CROS_EC_DEV_IOC_V2	0xEC
-#define CROS_EC_DEV_IOCXCMD_V2	_IOWR(CROS_EC_DEV_IOC_V2, 0, \
-				      struct cros_ec_command_v2)
-#define CROS_EC_DEV_IOCRDMEM_V2	_IOWR(CROS_EC_DEV_IOC_V2, 1, \
-				      struct cros_ec_readmem_v2)
-#define CROS_EC_DEV_IOCEVENTMASK_V2	_IO(CROS_EC_DEV_IOC_V2, 2)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __UTIL_CROS_EC_DEV_H */
diff --git a/util/dedede-relevant-paths.txt b/util/dedede-relevant-paths.txt
deleted file mode 100644
index 692e7090a4..0000000000
--- a/util/dedede-relevant-paths.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-# Here you can place files of interest to be included in the commit message for
-# merge commits to firmware-dedede-13606.B
-common/charge_state_v2.c
-common/mkbp_*
-common/ocpc.c
-common/usbc/usb_tc_drp_acc_trysrc_sm.c
-common/usbc/usb_sm.c
-common/usbc/*_pd_*
-common/usbc/dp_alt_mode.c
-common/usbc/usb_prl_sm.c
-common/usbc/usb_pe_drp_sm.c
-common/usb_charger.c
-common/usb_common.c
-common/usbc_ocp.c
-driver/charger/sm5803.*
-driver/charger/isl923x.*
-driver/tcpm/raa489000.*
-driver/tcpm/it83*
-include/power/icelake.h
-include/intel_x86.h
-power/icelake.c
-power/intel_x86.c
\ No newline at end of file
diff --git a/util/ec3po/OWNERS b/util/ec3po/OWNERS
deleted file mode 100644
index 5d4c97339d..0000000000
--- a/util/ec3po/OWNERS
+++ /dev/null
@@ -1,3 +0,0 @@
-aaboagye@chromium.org
-coconutruben@chromium.org
-matthewb@chromium.org
diff --git a/util/ec3po/__init__.py b/util/ec3po/__init__.py
deleted file mode 100644
index 376ffdba04..0000000000
--- a/util/ec3po/__init__.py
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""The EC console interpreter.
-
-EC-3PO is a console interpreter which migrates the rich debug console from the
-EC itself to the host.  This allows for a rich debug console without impacting
-EC image sizes while also allowing the development of new console features.
-
-The package consists of two modules: console and interpreter.  The console
-module provides the interactive console interface between the user and the
-interpreter.  It handles the presentation of the EC console including editing
-methods as well as session-persistent command history.
-
-The interpreter module provides the interpretation layer between the EC UART and
-the user.  The user does not necessarily have to be the interactive console, but
-could be something like autotest.  The interpreter is also responsible for the
-automatic command retrying if the EC drops a character in a command.  This is a
-stopgap until all commands are communicated via host commands.
-"""
diff --git a/util/ec3po/console.py b/util/ec3po/console.py
deleted file mode 100755
index 9f28c8b7bf..0000000000
--- a/util/ec3po/console.py
+++ /dev/null
@@ -1,1171 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""EC-3PO Interactive Console Interface
-
-console provides the console interface between the user and the interpreter.  It
-handles the presentation of the EC console including editing methods as well as
-session-persistent command history.
-"""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import argparse
-import binascii
-import ctypes
-from datetime import datetime
-import logging
-import os
-import pty
-import re
-import select
-import stat
-import sys
-import traceback
-
-import six
-
-from ec3po import interpreter
-from ec3po import threadproc_shim
-
-
-PROMPT = b'> '
-CONSOLE_INPUT_LINE_SIZE = 80  # Taken from the CONFIG_* with the same name.
-CONSOLE_MAX_READ = 100  # Max bytes to read at a time from the user.
-LOOK_BUFFER_SIZE = 256  # Size of search window when looking for the enhanced EC
-                        # image string.
-
-# In console_init(), the EC will print a string saying that the EC console is
-# enabled.  Enhanced images will print a slightly different string.  These
-# regular expressions are used to determine at reboot whether the EC image is
-# enhanced or not.
-ENHANCED_IMAGE_RE = re.compile(br'Enhanced Console is enabled '
-                               br'\(v([0-9]+\.[0-9]+\.[0-9]+)\)')
-NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ')
-
-# The timeouts are really only useful for enhanced EC images, but otherwise just
-# serve as a delay for non-enhanced EC images.  Therefore, we can keep this
-# value small enough so that there's not too much of a delay, but long enough
-# that enhanced EC images can respond in time.  Once we've detected an enhanced
-# EC image, we can increase the timeout for stability just in case it takes a
-# bit longer to receive an ACK for some reason.
-NON_ENHANCED_EC_INTERROGATION_TIMEOUT = 0.3  # Maximum number of seconds to wait
-                                             # for a response to an
-                                             # interrogation of a non-enhanced
-                                             # EC image.
-ENHANCED_EC_INTERROGATION_TIMEOUT = 1.0  # Maximum number of seconds to wait for
-                                         # a response to an interrogation of an
-                                         # enhanced EC image.
-# List of modes which control when interrogations are performed with the EC.
-INTERROGATION_MODES = [b'never', b'always', b'auto']
-# Format for printing host timestamp
-HOST_STRFTIME="%y-%m-%d %H:%M:%S.%f"
-
-
-class EscState(object):
-  """Class which contains an enumeration for states of ESC sequences."""
-  ESC_START = 1
-  ESC_BRACKET = 2
-  ESC_BRACKET_1 = 3
-  ESC_BRACKET_3 = 4
-  ESC_BRACKET_8 = 5
-
-
-class ControlKey(object):
-  """Class which contains codes for various control keys."""
-  BACKSPACE = 0x08
-  CTRL_A = 0x01
-  CTRL_B = 0x02
-  CTRL_D = 0x04
-  CTRL_E = 0x05
-  CTRL_F = 0x06
-  CTRL_K = 0x0b
-  CTRL_N = 0xe
-  CTRL_P = 0x10
-  CARRIAGE_RETURN = 0x0d
-  ESC = 0x1b
-
-
-class Console(object):
-  """Class which provides the console interface between the EC and the user.
-
-  This class essentially represents the console interface between the user and
-  the EC.  It handles all of the console editing behaviour
-
-  Attributes:
-    logger: A logger for this module.
-    master_pty: File descriptor to the master side of the PTY.  Used for driving
-      output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of
-      band management for the interactive console.
-    input_buffer: A string representing the current input command.
-    input_buffer_pos: An integer representing the current position in the buffer
-      to insert a char.
-    partial_cmd: A string representing the command entered on a line before
-      pressing the up arrow keys.
-    esc_state: An integer represeting the current state within an escape
-      sequence.
-    line_limit: An integer representing the maximum number of characters on a
-      line.
-    history: A list of strings containing the past entered console commands.
-    history_pos: An integer representing the current history buffer position.
-      This index is used to show previous commands.
-    prompt: A string representing the console prompt displayed to the user.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      until we perform some handshaking.
-    interrogation_timeout: A float representing the current maximum seconds to
-      wait for a response to an interrogation.
-    receiving_oobm_cmd: A boolean indicating whether or not the console is in
-      the middle of receiving an out of band command.
-    pending_oobm_cmd: A string containing the pending OOBM command.
-    interrogation_mode: A string containing the current mode of whether
-      interrogations are performed with the EC or not and how often.
-    raw_debug: Flag to indicate whether per interrupt data should be logged to
-      debug
-    output_line_log_buffer: buffer for lines coming from the EC to log to debug
-  """
-
-  def __init__(self, master_pty, user_pty, interface_pty, cmd_pipe, dbg_pipe,
-               name=None):
-    """Initalises a Console object with the provided arguments.
-
-    Args:
-    master_pty: File descriptor to the master side of the PTY.  Used for driving
-      output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    interface_pty: A string representing the PTY name of the served command
-      interface.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    name: the console source name
-    """
-    # Create a unique logger based on the console name
-    console_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Console' % console_prefix)
-    self.logger = interpreter.LoggerAdapter(logger, {'pty': user_pty})
-    self.master_pty = master_pty
-    self.user_pty = user_pty
-    self.interface_pty = interface_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.oobm_queue = threadproc_shim.Queue()
-    self.input_buffer = b''
-    self.input_buffer_pos = 0
-    self.partial_cmd = b''
-    self.esc_state = 0
-    self.line_limit = CONSOLE_INPUT_LINE_SIZE
-    self.history = []
-    self.history_pos = 0
-    self.prompt = PROMPT
-    self.enhanced_ec = False
-    self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-    self.receiving_oobm_cmd = False
-    self.pending_oobm_cmd = b''
-    self.interrogation_mode = b'auto'
-    self.timestamp_enabled = True
-    self.look_buffer = b''
-    self.raw_debug = False
-    self.output_line_log_buffer = []
-
-  def __str__(self):
-    """Show internal state of Console object as a string."""
-    string = []
-    string.append('master_pty: %s' % self.master_pty)
-    string.append('user_pty: %s' % self.user_pty)
-    string.append('interface_pty: %s' % self.interface_pty)
-    string.append('cmd_pipe: %s' % self.cmd_pipe)
-    string.append('dbg_pipe: %s' % self.dbg_pipe)
-    string.append('oobm_queue: %s' % self.oobm_queue)
-    string.append('input_buffer: %s' % self.input_buffer)
-    string.append('input_buffer_pos: %d' % self.input_buffer_pos)
-    string.append('esc_state: %d' % self.esc_state)
-    string.append('line_limit: %d' % self.line_limit)
-    string.append('history: %r' % self.history)
-    string.append('history_pos: %d' % self.history_pos)
-    string.append('prompt: %r' % self.prompt)
-    string.append('partial_cmd: %r'% self.partial_cmd)
-    string.append('interrogation_mode: %r' % self.interrogation_mode)
-    string.append('look_buffer: %r' % self.look_buffer)
-    return '\n'.join(string)
-
-  def LogConsoleOutput(self, data):
-    """Log to debug user MCU output to master_pty when line is filled.
-
-    The logging also suppresses the Cr50 spinner lines by removing characters
-    when it sees backspaces.
-
-    Args:
-      data: bytes - string received from MCU
-    """
-    data = list(data)
-    # For compatibility with python2 and python3, standardize on the data
-    # being a list of integers. This requires one more transformation in py2
-    if not isinstance(data[0], int):
-      data = [ord(c) for c in data]
-
-    # This is a list of already filtered characters (or placeholders).
-    line = self.output_line_log_buffer
-
-    # TODO(b/177480273): use raw strings here
-    symbols = {
-            ord(b'\n'): u'\\n',
-            ord(b'\r'): u'\\r',
-            ord(b'\t'): u'\\t'
-    }
-    # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data))
-    while data:
-      # Recall, data is a list of integers, namely the byte values sent by
-      # the MCU.
-      byte = data.pop(0)
-      # This means that |byte| is an int.
-      if byte == ord('\n'):
-        line.append(symbols[byte])
-        if line:
-          self.logger.debug(u'%s', ''.join(line))
-        line = []
-      elif byte == ord('\b'):
-        # Backspace: trim the last character off the buffer
-        if line:
-          line.pop(-1)
-      elif byte in symbols:
-        line.append(symbols[byte])
-      elif byte < ord(' ') or byte > ord('~'):
-        # Turn any character that isn't printable ASCII into escaped hex.
-        # ' ' is chr(20), and 0-19 are unprintable control characters.
-        # '~' is chr(126), and 127 is DELETE.  128-255 are control and Latin-1.
-        line.append(u'\\x%02x' % byte)
-      else:
-        # byte is printable. Thus it is safe to use chr() to get the printable
-        # character out of it again.
-        line.append(u'%s' % chr(byte))
-    self.output_line_log_buffer = line
-
-  def PrintHistory(self):
-    """Print the history of entered commands."""
-    fd = self.master_pty
-    # Make it pretty by figuring out how wide to pad the numbers.
-    wide = (len(self.history) // 10) + 1
-    for i in range(len(self.history)):
-      line = b' %*d %s\r\n' % (wide, i, self.history[i])
-      os.write(fd, line)
-
-  def ShowPreviousCommand(self):
-    """Shows the previous command from the history list."""
-    # There's nothing to do if there's no history at all.
-    if not self.history:
-      self.logger.debug('No history to print.')
-      return
-
-    # Don't do anything if there's no more history to show.
-    if self.history_pos == 0:
-      self.logger.debug('No more history to show.')
-      return
-
-    self.logger.debug('current history position: %d.', self.history_pos)
-
-    # Decrement the history buffer position.
-    self.history_pos -= 1
-    self.logger.debug('new history position.: %d', self.history_pos)
-
-    # Save the text entered on the console if any.
-    if self.history_pos == len(self.history)-1:
-      self.logger.debug('saving partial_cmd: %r', self.input_buffer)
-      self.partial_cmd = self.input_buffer
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the last entry in the history buffer.
-    self.logger.debug('printing previous entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    fd = self.master_pty
-    prev_cmd = self.history[self.history_pos]
-    os.write(fd, prev_cmd)
-    # Update the input buffer.
-    self.input_buffer = prev_cmd
-    self.input_buffer_pos = len(prev_cmd)
-
-  def ShowNextCommand(self):
-    """Shows the next command from the history list."""
-    # Don't do anything if there's no history at all.
-    if not self.history:
-      self.logger.debug('History buffer is empty.')
-      return
-
-    fd = self.master_pty
-
-    self.logger.debug('current history position: %d', self.history_pos)
-    # Increment the history position.
-    self.history_pos += 1
-
-    # Restore the partial cmd.
-    if self.history_pos == len(self.history):
-      self.logger.debug('Restoring partial command of %r', self.partial_cmd)
-      # Backspace the line.
-      for _ in range(self.input_buffer_pos):
-        self.SendBackspace()
-      # Print the partially entered command if any.
-      os.write(fd, self.partial_cmd)
-      self.input_buffer = self.partial_cmd
-      self.input_buffer_pos = len(self.input_buffer)
-      # Now that we've printed it, clear the partial cmd storage.
-      self.partial_cmd = b''
-      # Reset history position.
-      self.history_pos = len(self.history)
-      return
-
-    self.logger.debug('new history position: %d', self.history_pos)
-    if self.history_pos > len(self.history)-1:
-      self.logger.debug('No more history to show.')
-      self.history_pos -= 1
-      self.logger.debug('Reset history position to %d', self.history_pos)
-      return
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the newer entry from the history buffer.
-    self.logger.debug('printing next entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    next_cmd = self.history[self.history_pos]
-    os.write(fd, next_cmd)
-    # Update the input buffer.
-    self.input_buffer = next_cmd
-    self.input_buffer_pos = len(next_cmd)
-    self.logger.debug('new history position: %d.', self.history_pos)
-
-  def SliceOutChar(self):
-    """Remove a char from the line and shift everything over 1 column."""
-    fd = self.master_pty
-    # Remove the character at the input_buffer_pos by slicing it out.
-    self.input_buffer = self.input_buffer[0:self.input_buffer_pos] + \
-                        self.input_buffer[self.input_buffer_pos+1:]
-    # Write the rest of the line
-    moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos:])
-    # Write a space to clear out the last char
-    moved_col += os.write(fd, b' ')
-    # Update the input buffer position.
-    self.input_buffer_pos += moved_col
-    # Reset the cursor
-    self.MoveCursor('left', moved_col)
-
-  def HandleEsc(self, byte):
-    """HandleEsc processes escape sequences.
-
-    Args:
-      byte: An integer representing the current byte in the sequence.
-    """
-    # We shouldn't be handling an escape sequence if we haven't seen one.
-    assert self.esc_state != 0
-
-    if self.esc_state is EscState.ESC_START:
-      self.logger.debug('ESC_START')
-      if byte == ord('['):
-        self.esc_state = EscState.ESC_BRACKET
-        return
-
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
-        self.esc_state = 0
-
-    elif self.esc_state is EscState.ESC_BRACKET:
-      self.logger.debug('ESC_BRACKET')
-      # Left Arrow key was pressed.
-      if byte == ord('D'):
-        self.logger.debug('Left arrow key pressed.')
-        self.MoveCursor('left', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Right Arrow key.
-      elif byte == ord('C'):
-        self.logger.debug('Right arrow key pressed.')
-        self.MoveCursor('right', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Up Arrow key.
-      elif byte == ord('A'):
-        self.logger.debug('Up arrow key pressed.')
-        self.ShowPreviousCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Down Arrow key.
-      elif byte == ord('B'):
-        self.logger.debug('Down arrow key pressed.')
-        self.ShowNextCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # For some reason, minicom sends a 1 instead of 7. /shrug
-      # TODO(aaboagye): Figure out why this happens.
-      elif byte == ord('1') or byte == ord('7'):
-        self.esc_state = EscState.ESC_BRACKET_1
-
-      elif byte == ord('3'):
-        self.esc_state = EscState.ESC_BRACKET_3
-
-      elif byte == ord('8'):
-        self.esc_state = EscState.ESC_BRACKET_8
-
-      else:
-        self.logger.error(r'Bad or unhandled escape sequence. got ^[%c\(%d)',
-                          chr(byte), byte)
-        self.esc_state = 0
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_1:
-      self.logger.debug('ESC_BRACKET_1')
-      # HOME key.
-      if byte == ord('~'):
-        self.logger.debug('Home key pressed.')
-        self.MoveCursor('left', self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_3:
-      self.logger.debug('ESC_BRACKET_3')
-      # DEL key.
-      if byte == ord('~'):
-        self.logger.debug('Delete key pressed.')
-        if self.input_buffer_pos != len(self.input_buffer):
-          self.SliceOutChar()
-        self.esc_state = 0 # Reset the state.
-
-    elif self.esc_state is EscState.ESC_BRACKET_8:
-      self.logger.debug('ESC_BRACKET_8')
-      # END key.
-      if byte == ord('~'):
-        self.logger.debug('End key pressed.')
-        self.MoveCursor('right',
-                        len(self.input_buffer) - self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
-        self.esc_state = 0
-
-    else:
-      self.logger.error('Unexpected sequence. %c', byte)
-      self.esc_state = 0
-
-  def ProcessInput(self):
-    """Captures the input determines what actions to take."""
-    # There's nothing to do if the input buffer is empty.
-    if len(self.input_buffer) == 0:
-      return
-
-    # Don't store 2 consecutive identical commands in the history.
-    if (self.history and self.history[-1] != self.input_buffer
-        or not self.history):
-      self.history.append(self.input_buffer)
-
-    # Split the command up by spaces.
-    line = self.input_buffer.split(b' ')
-    self.logger.debug('cmd: %s', self.input_buffer)
-    cmd = line[0].lower()
-
-    # The 'history' command is a special case that we handle locally.
-    if cmd == 'history':
-      self.PrintHistory()
-      return
-
-    # Send the command to the interpreter.
-    self.logger.debug('Sending command to interpreter.')
-    self.cmd_pipe.send(self.input_buffer)
-
-  def CheckForEnhancedECImage(self):
-    """Performs an interrogation of the EC image.
-
-    Send a SYN and expect an ACK.  If no ACK or the response is incorrect, then
-    assume that the current EC image that we are talking to is not enhanced.
-
-    Returns:
-      is_enhanced: A boolean indicating whether the EC responded to the
-        interrogation correctly.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.dbg_pipe.recv().
-    """
-    # Send interrogation byte and wait for the response.
-    self.logger.debug('Performing interrogation.')
-    self.cmd_pipe.send(interpreter.EC_SYN)
-
-    response = ''
-    if self.dbg_pipe.poll(self.interrogation_timeout):
-      response = self.dbg_pipe.recv()
-      self.logger.debug('response: %r', binascii.hexlify(response))
-    else:
-      self.logger.debug('Timed out waiting for EC_ACK')
-
-    # Verify the acknowledgment.
-    is_enhanced = response == interpreter.EC_ACK
-
-    if is_enhanced:
-      # Increase the interrogation timeout for stability purposes.
-      self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Increasing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-    else:
-      # Reduce the timeout in order to reduce the perceivable delay.
-      self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Reducing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-
-    return is_enhanced
-
-  def HandleChar(self, byte):
-    """HandleChar does a certain action when it receives a character.
-
-    Args:
-      byte: An integer representing the character received from the user.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.CheckForEnhancedECImage()
-          i.e. from self.dbg_pipe.recv().
-    """
-    fd = self.master_pty
-
-    # Enter the OOBM prompt mode if the user presses '%'.
-    if byte == ord('%'):
-      self.logger.debug('Begin OOBM command.')
-      self.receiving_oobm_cmd = True
-      # Print a "prompt".
-      os.write(self.master_pty, b'\r\n% ')
-      return
-
-    # Add chars to the pending OOBM command if we're currently receiving one.
-    if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN:
-      tmp_bytes = six.int2byte(byte)
-      self.pending_oobm_cmd += tmp_bytes
-      self.logger.debug('%s', tmp_bytes)
-      os.write(self.master_pty, tmp_bytes)
-      return
-
-    if byte == ControlKey.CARRIAGE_RETURN:
-      if self.receiving_oobm_cmd:
-        # Terminate the command and place it in the OOBM queue.
-        self.logger.debug('End OOBM command.')
-        if self.pending_oobm_cmd:
-          self.oobm_queue.put(self.pending_oobm_cmd)
-          self.logger.debug('Placed %r into OOBM command queue.',
-                            self.pending_oobm_cmd)
-
-        # Reset the state.
-        os.write(self.master_pty, b'\r\n' + self.prompt)
-        self.input_buffer = b''
-        self.input_buffer_pos = 0
-        self.receiving_oobm_cmd = False
-        self.pending_oobm_cmd = b''
-        return
-
-      if self.interrogation_mode == b'never':
-        self.logger.debug('Skipping interrogation because interrogation mode'
-                          ' is set to never.')
-      elif self.interrogation_mode == b'always':
-        # Only interrogate the EC if the interrogation mode is set to 'always'.
-        self.enhanced_ec = self.CheckForEnhancedECImage()
-        self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-    if not self.enhanced_ec:
-      # Send everything straight to the EC to handle.
-      self.cmd_pipe.send(six.int2byte(byte))
-      # Reset the input buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      self.logger.log(1, 'Reset input buffer.')
-      return
-
-    # Keep handling the ESC sequence if we're in the middle of it.
-    if self.esc_state != 0:
-      self.HandleEsc(byte)
-      return
-
-    # When we're at the end of the line, we should only allow going backwards,
-    # backspace, carriage return, up, or down.  The arrow keys are escape
-    # sequences, so we let the escape...escape.
-    if (self.input_buffer_pos >= self.line_limit and
-        byte not in [ControlKey.CTRL_B, ControlKey.ESC, ControlKey.BACKSPACE,
-                     ControlKey.CTRL_A, ControlKey.CARRIAGE_RETURN,
-                     ControlKey.CTRL_P, ControlKey.CTRL_N]):
-      return
-
-    # If the input buffer is full we can't accept new chars.
-    buffer_full = len(self.input_buffer) >= self.line_limit
-
-
-    # Carriage_Return/Enter
-    if byte == ControlKey.CARRIAGE_RETURN:
-      self.logger.debug('Enter key pressed.')
-      # Put a carriage return/newline and the print the prompt.
-      os.write(fd, b'\r\n')
-
-      # TODO(aaboagye): When we control the printing of all output, print the
-      # prompt AFTER printing all the output.  We can't do it yet because we
-      # don't know how much is coming from the EC.
-
-      # Print the prompt.
-      os.write(fd, self.prompt)
-      # Process the input.
-      self.ProcessInput()
-      # Now, clear the buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      # Reset history buffer pos.
-      self.history_pos = len(self.history)
-      # Clear partial command.
-      self.partial_cmd = b''
-
-    # Backspace
-    elif byte == ControlKey.BACKSPACE:
-      self.logger.debug('Backspace pressed.')
-      if self.input_buffer_pos > 0:
-        # Move left 1 column.
-        self.MoveCursor('left', 1)
-        # Remove the character at the input_buffer_pos by slicing it out.
-        self.SliceOutChar()
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-    # Ctrl+A. Move cursor to beginning of the line
-    elif byte == ControlKey.CTRL_A:
-      self.logger.debug('Control+A pressed.')
-      self.MoveCursor('left', self.input_buffer_pos)
-
-    # Ctrl+B. Move cursor left 1 column.
-    elif byte == ControlKey.CTRL_B:
-      self.logger.debug('Control+B pressed.')
-      self.MoveCursor('left', 1)
-
-    # Ctrl+D. Delete a character.
-    elif byte == ControlKey.CTRL_D:
-      self.logger.debug('Control+D pressed.')
-      if self.input_buffer_pos != len(self.input_buffer):
-        # Remove the character by slicing it out.
-        self.SliceOutChar()
-
-    # Ctrl+E. Move cursor to end of the line.
-    elif byte == ControlKey.CTRL_E:
-      self.logger.debug('Control+E pressed.')
-      self.MoveCursor('right',
-                      len(self.input_buffer) - self.input_buffer_pos)
-
-    # Ctrl+F. Move cursor right 1 column.
-    elif byte == ControlKey.CTRL_F:
-      self.logger.debug('Control+F pressed.')
-      self.MoveCursor('right', 1)
-
-    # Ctrl+K. Kill line.
-    elif byte == ControlKey.CTRL_K:
-      self.logger.debug('Control+K pressed.')
-      self.KillLine()
-
-    # Ctrl+N. Next line.
-    elif byte == ControlKey.CTRL_N:
-      self.logger.debug('Control+N pressed.')
-      self.ShowNextCommand()
-
-    # Ctrl+P. Previous line.
-    elif byte == ControlKey.CTRL_P:
-      self.logger.debug('Control+P pressed.')
-      self.ShowPreviousCommand()
-
-    # ESC sequence
-    elif byte == ControlKey.ESC:
-      # Starting an ESC sequence
-      self.esc_state = EscState.ESC_START
-
-    # Only print printable chars.
-    elif IsPrintable(byte):
-      # Drop the character if we're full.
-      if buffer_full:
-        self.logger.debug('Dropped char: %c(%d)', byte, byte)
-        return
-      # Print the character.
-      os.write(fd, six.int2byte(byte))
-      # Print the rest of the line (if any).
-      extra_bytes_written = os.write(fd,
-                                     self.input_buffer[self.input_buffer_pos:])
-
-      # Recreate the input buffer.
-      self.input_buffer = (self.input_buffer[0:self.input_buffer_pos] +
-                           six.int2byte(byte) +
-                           self.input_buffer[self.input_buffer_pos:])
-      # Update the input buffer position.
-      self.input_buffer_pos += 1 + extra_bytes_written
-
-      # Reset the cursor if we wrote any extra bytes.
-      if extra_bytes_written:
-        self.MoveCursor('left', extra_bytes_written)
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-  def MoveCursor(self, direction, count):
-    """MoveCursor moves the cursor left or right by count columns.
-
-    Args:
-      direction: A string that should be either 'left' or 'right' representing
-        the direction to move the cursor on the console.
-      count: An integer representing how many columns the cursor should be
-        moved.
-
-    Raises:
-      AssertionError: If the direction is not equal to 'left' or 'right'.
-    """
-    # If there's nothing to move, we're done.
-    if not count:
-      return
-    fd = self.master_pty
-    seq = b'\033[' + str(count).encode('ascii')
-    if direction == 'left':
-      # Bind the movement.
-      if count > self.input_buffer_pos:
-        count = self.input_buffer_pos
-      seq += b'D'
-      self.logger.debug('move cursor left %d', count)
-      self.input_buffer_pos -= count
-
-    elif direction == 'right':
-      # Bind the movement.
-      if (count + self.input_buffer_pos) > len(self.input_buffer):
-        count = 0
-      seq += b'C'
-      self.logger.debug('move cursor right %d', count)
-      self.input_buffer_pos += count
-
-    else:
-      raise AssertionError(('The only valid directions are \'left\' and '
-                            '\'right\''))
-
-    self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-    # Move the cursor.
-    if count != 0:
-      os.write(fd, seq)
-
-  def KillLine(self):
-    """Kill the rest of the line based on the input buffer position."""
-    # Killing the line is killing all the text to the right.
-    diff = len(self.input_buffer) - self.input_buffer_pos
-    self.logger.debug('diff: %d', diff)
-    # Diff shouldn't be negative, but if it is for some reason, let's try to
-    # correct the cursor.
-    if diff < 0:
-      self.logger.warning('Resetting input buffer position to %d...',
-                          len(self.input_buffer))
-      self.MoveCursor('left', -diff)
-      return
-    if diff:
-      self.MoveCursor('right', diff)
-      for _ in range(diff):
-        self.SendBackspace()
-      self.input_buffer_pos -= diff
-      self.input_buffer = self.input_buffer[0:self.input_buffer_pos]
-
-  def SendBackspace(self):
-    """Backspace a character on the console."""
-    os.write(self.master_pty, b'\033[1D \033[1D')
-
-  def ProcessOOBMQueue(self):
-    """Retrieve an item from the OOBM queue and process it."""
-    item = self.oobm_queue.get()
-    self.logger.debug('OOBM cmd: %r', item)
-    cmd = item.split(b' ')
-
-    if cmd[0] == b'loglevel':
-      # An integer is required in order to set the log level.
-      if len(cmd) < 2:
-        self.logger.debug('Insufficient args')
-        self.PrintOOBMHelp()
-        return
-      try:
-        self.logger.debug('Log level change request.')
-        new_log_level = int(cmd[1])
-        self.logger.logger.setLevel(new_log_level)
-        self.logger.info('Log level changed to %d.', new_log_level)
-
-        # Forward the request to the interpreter as well.
-        self.cmd_pipe.send(item)
-      except ValueError:
-        # Ignoring the request if an integer was not provided.
-        self.PrintOOBMHelp()
-
-    elif cmd[0] == b'timestamp':
-      mode = cmd[1].lower()
-      self.timestamp_enabled = (mode == b'on')
-      self.logger.info('%sabling uart timestamps.',
-                       'En' if self.timestamp_enabled else 'Dis')
-
-    elif cmd[0] == b'rawdebug':
-      mode = cmd[1].lower()
-      self.raw_debug = (mode == b'on')
-      self.logger.info('%sabling per interrupt debug logs.',
-                       'En' if self.raw_debug else 'Dis')
-
-    elif cmd[0] == b'interrogate' and len(cmd) >= 2:
-      enhanced = False
-      mode = cmd[1]
-      if len(cmd) >= 3 and cmd[2] == b'enhanced':
-        enhanced = True
-
-      # Set the mode if correct.
-      if mode in INTERROGATION_MODES:
-        self.interrogation_mode = mode
-        self.logger.debug('Updated interrogation mode to %s.', mode)
-
-        # Update the assumptions of the EC image.
-        self.enhanced_ec = enhanced
-        self.logger.debug('Enhanced EC image is now %r', self.enhanced_ec)
-
-        # Send command to interpreter as well.
-        self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      else:
-        self.PrintOOBMHelp()
-
-    else:
-      self.PrintOOBMHelp()
-
-  def PrintOOBMHelp(self):
-    """Prints out the OOBM help."""
-    # Print help syntax.
-    os.write(self.master_pty, b'\r\n' + b'Known OOBM commands:\r\n')
-    os.write(self.master_pty, b'  interrogate <never | always | auto> '
-             b'[enhanced]\r\n')
-    os.write(self.master_pty, b'  loglevel <int>\r\n')
-
-  def CheckBufferForEnhancedImage(self, data):
-    """Adds data to a look buffer and checks to see for enhanced EC image.
-
-    The EC's console task prints a string upon initialization which says that
-    "Console is enabled; type HELP for help.".  The enhanced EC images print a
-    different string as a part of their init.  This function searches through a
-    "look" buffer, scanning for the presence of either of those strings and
-    updating the enhanced_ec state accordingly.
-
-    Args:
-      data: A string containing the data sent from the interpreter.
-    """
-    self.look_buffer += data
-
-    # Search the buffer for any of the EC image strings.
-    enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer)
-    non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer)
-
-    # Update the state if any matches were found.
-    if enhanced_match or non_enhanced_match:
-      if enhanced_match:
-        self.enhanced_ec = True
-      elif non_enhanced_match:
-        self.enhanced_ec = False
-
-      # Inform the interpreter of the result.
-      self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-      # Clear look buffer since a match was found.
-      self.look_buffer = b''
-
-    # Move the sliding window.
-    self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:]
-
-
-def CanonicalizeTimeString(timestr):
-  """Canonicalize the timestamp string.
-
-  Args:
-    timestr: A timestamp string ended with 6 digits msec.
-
-  Returns:
-    A string with 3 digits msec and an extra space.
-  """
-  return timestr[:-3].encode('ascii') + b' '
-
-
-def IsPrintable(byte):
-  """Determines if a byte is printable.
-
-  Args:
-    byte: An integer potentially representing a printable character.
-
-  Returns:
-    A boolean indicating whether the byte is a printable character.
-  """
-  return byte >= ord(' ') and byte <= ord('~')
-
-
-def StartLoop(console, command_active, shutdown_pipe=None):
-  """Starts the infinite loop of console processing.
-
-  Args:
-    console: A Console object that has been properly initialzed.
-    command_active: ctypes data object or multiprocessing.Value indicating if
-      servod owns the console, or user owns the console. This prevents input
-      collisions.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    console.logger.debug('Console is being served on %s.', console.user_pty)
-    console.logger.debug('Console master is on %s.', console.master_pty)
-    console.logger.debug('Command interface is being served on %s.',
-        console.interface_pty)
-    console.logger.debug(console)
-
-    # This checks for HUP to indicate if the user has connected to the pty.
-    ep = select.epoll()
-    ep.register(console.master_pty, select.EPOLLHUP)
-
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    # Used for determining when to print host timestamps
-    tm_req = True
-
-    while continue_looping:
-      # Check to see if pts is connected to anything
-      events = ep.poll(0)
-      master_connected = not events
-
-      # Check to see if pipes or the console are ready for reading.
-      read_list = [console.interface_pty,
-                   console.cmd_pipe, console.dbg_pipe]
-      if master_connected:
-        read_list.append(console.master_pty)
-      if shutdown_pipe is not None:
-        read_list.append(shutdown_pipe)
-
-      # Check if any input is ready, or wait for .1 sec and re-poll if
-      # a user has connected to the pts.
-      select_output = select.select(read_list, [], [], .1)
-      if not select_output:
-        continue
-      ready_for_reading = select_output[0]
-
-      for obj in ready_for_reading:
-        if obj is console.master_pty:
-          if not command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            try:
-              line = bytearray(os.read(console.master_pty, CONSOLE_MAX_READ))
-              console.logger.debug('Input from user: %s, locked:%s',
-                  str(line).strip(), command_active.value)
-              for i in line:
-                try:
-                  # Handle each character as it arrives.
-                  console.HandleChar(i)
-                except EOFError:
-                  console.logger.debug(
-                      'ec3po console received EOF from dbg_pipe in HandleChar()'
-                      ' while reading console.master_pty')
-                  continue_looping = False
-                  break
-            except OSError:
-              console.logger.debug('Ptm read failed, probably user disconnect.')
-
-        elif obj is console.interface_pty:
-          if command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            line = bytearray(os.read(console.interface_pty, CONSOLE_MAX_READ))
-            console.logger.debug('Input from interface: %s, locked:%s',
-                str(line).strip(), command_active.value)
-            for i in line:
-              try:
-                # Handle each character as it arrives.
-                console.HandleChar(i)
-              except EOFError:
-                console.logger.debug(
-                    'ec3po console received EOF from dbg_pipe in HandleChar()'
-                    ' while reading console.interface_pty')
-                continue_looping = False
-                break
-
-        elif obj is console.cmd_pipe:
-          try:
-            data = console.cmd_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from cmd_pipe')
-            continue_looping = False
-          else:
-            # Write it to the user console.
-            if console.raw_debug:
-              console.logger.debug('|CMD|-%s->%r',
-                                   ('u' if master_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
-            if master_connected:
-              os.write(console.master_pty, data)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is console.dbg_pipe:
-          try:
-            data = console.dbg_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from dbg_pipe')
-            continue_looping = False
-          else:
-            if console.interrogation_mode == b'auto':
-              # Search look buffer for enhanced EC image string.
-              console.CheckBufferForEnhancedImage(data)
-            # Write it to the user console.
-            if len(data) > 1 and console.raw_debug:
-              console.logger.debug('|DBG|-%s->%r',
-                                   ('u' if master_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
-            console.LogConsoleOutput(data)
-            if master_connected:
-              end = len(data) - 1
-              if console.timestamp_enabled:
-                # A timestamp is required at the beginning of this line
-                if tm_req is True:
-                  now = datetime.now()
-                  tm = CanonicalizeTimeString(now.strftime(HOST_STRFTIME))
-                  os.write(console.master_pty, tm)
-                  tm_req = False
-
-                # Insert timestamps into the middle where appropriate
-                # except if the last character is a newline
-                nls_found = data.count(b'\n', 0, end)
-                now = datetime.now()
-                tm = CanonicalizeTimeString(now.strftime('\n' + HOST_STRFTIME))
-                data_tm = data.replace(b'\n', tm, nls_found)
-              else:
-                data_tm = data
-
-              # timestamp required on next input
-              if data[end] == b'\n'[0]:
-                tm_req = True
-              os.write(console.master_pty, data_tm)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is shutdown_pipe:
-          console.logger.debug(
-              'ec3po console received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      while not console.oobm_queue.empty():
-        console.logger.debug('OOBM queue ready for reading.')
-        console.ProcessOOBMQueue()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    ep.unregister(console.master_pty)
-    console.dbg_pipe.close()
-    console.cmd_pipe.close()
-    os.close(console.master_pty)
-    os.close(console.interface_pty)
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    console.logger.debug('Exit ec3po console loop for %s', console.user_pty)
-
-
-def main(argv):
-  """Kicks off the EC-3PO interactive console interface and interpreter.
-
-  We create some pipes to communicate with an interpreter, instantiate an
-  interpreter, create a PTY pair, and begin serving the console interface.
-
-  Args:
-    argv: A list of strings containing the arguments this module was called
-      with.
-  """
-  # Set up argument parser.
-  parser = argparse.ArgumentParser(description=('Start interactive EC console '
-                                                'and interpreter.'))
-  parser.add_argument('ec_uart_pty',
-                      help=('The full PTY name that the EC UART'
-                            ' is present on. eg: /dev/pts/12'))
-  parser.add_argument('--log-level',
-                      default='info',
-                      help='info, debug, warning, error, or critical')
-
-  # Parse arguments.
-  opts = parser.parse_args(argv)
-
-  # Set logging level.
-  opts.log_level = opts.log_level.lower()
-  if opts.log_level == 'info':
-    log_level = logging.INFO
-  elif opts.log_level == 'debug':
-    log_level = logging.DEBUG
-  elif opts.log_level == 'warning':
-    log_level = logging.WARNING
-  elif opts.log_level == 'error':
-    log_level = logging.ERROR
-  elif opts.log_level == 'critical':
-    log_level = logging.CRITICAL
-  else:
-    parser.error('Invalid log level. (info, debug, warning, error, critical)')
-
-  # Start logging with a timestamp, module, and log level shown in each log
-  # entry.
-  logging.basicConfig(level=log_level, format=('%(asctime)s - %(module)s -'
-                                               ' %(levelname)s - %(message)s'))
-
-  # Create some pipes to communicate between the interpreter and the console.
-  # The command pipe is bidirectional.
-  cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe()
-  # The debug pipe is unidirectional from interpreter to console only.
-  dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False)
-
-  # Create an interpreter instance.
-  itpr = interpreter.Interpreter(opts.ec_uart_pty, cmd_pipe_interp,
-                                 dbg_pipe_interp, log_level)
-
-  # Spawn an interpreter process.
-  itpr_process = threadproc_shim.ThreadOrProcess(
-      target=interpreter.StartLoop, args=(itpr,))
-  # Make sure to kill the interpreter when we terminate.
-  itpr_process.daemon = True
-  # Start the interpreter.
-  itpr_process.start()
-
-  # Open a new pseudo-terminal pair
-  (master_pty, user_pty) = pty.openpty()
-  # Set the permissions to 660.
-  os.chmod(os.ttyname(user_pty), (stat.S_IRGRP | stat.S_IWGRP |
-                                  stat.S_IRUSR | stat.S_IWUSR))
-  # Create a console.
-  console = Console(master_pty, os.ttyname(user_pty), cmd_pipe_interactive,
-                    dbg_pipe_interactive)
-  # Start serving the console.
-  v = threadproc_shim.Value(ctypes.c_bool, False)
-  StartLoop(console, v)
-
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py
deleted file mode 100755
index 3a44e0efce..0000000000
--- a/util/ec3po/console_unittest.py
+++ /dev/null
@@ -1,1569 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Unit tests for the EC-3PO Console interface."""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import binascii
-import logging
-import mock
-import tempfile
-import unittest
-
-import six
-
-from ec3po import console
-from ec3po import interpreter
-from ec3po import threadproc_shim
-
-ESC_STRING = six.int2byte(console.ControlKey.ESC)
-
-class Keys(object):
-  """A class that contains the escape sequences for special keys."""
-  LEFT_ARROW = [console.ControlKey.ESC, ord('['), ord('D')]
-  RIGHT_ARROW = [console.ControlKey.ESC, ord('['), ord('C')]
-  UP_ARROW = [console.ControlKey.ESC, ord('['), ord('A')]
-  DOWN_ARROW = [console.ControlKey.ESC, ord('['), ord('B')]
-  HOME = [console.ControlKey.ESC, ord('['), ord('1'), ord('~')]
-  END = [console.ControlKey.ESC, ord('['), ord('8'), ord('~')]
-  DEL = [console.ControlKey.ESC, ord('['), ord('3'), ord('~')]
-
-class OutputStream(object):
-  """A class that has methods which return common console output."""
-
-  @staticmethod
-  def MoveCursorLeft(count):
-    """Produces what would be printed to the console if the cursor moved left.
-
-    Args:
-      count: An integer representing how many columns to move left.
-
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved left.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'D'
-    return string
-
-  @staticmethod
-  def MoveCursorRight(count):
-    """Produces what would be printed to the console if the cursor moved right.
-
-    Args:
-      count: An integer representing how many columns to move right.
-
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved right.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'C'
-    return string
-
-BACKSPACE_STRING = b''
-# Move cursor left 1 column.
-BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
-# Write a space.
-BACKSPACE_STRING += b' '
-# Move cursor left 1 column.
-BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
-
-def BytesToByteList(string):
-  """Converts a bytes string to list of bytes.
-
-  Args:
-    string: A literal bytes to turn into a list of bytes.
-
-  Returns:
-    A list of integers representing the byte value of each character in the
-      string.
-  """
-  if six.PY3:
-    return [c for c in string]
-  return [ord(c) for c in string]
-
-def CheckConsoleOutput(test_case, exp_console_out):
-  """Verify what was sent out the console matches what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_console_out: A string representing the console output stream.
-  """
-  # Read what was sent out the console.
-  test_case.tempfile.seek(0)
-  console_out = test_case.tempfile.read()
-
-  test_case.assertEqual(exp_console_out, console_out)
-
-def CheckInputBuffer(test_case, exp_input_buffer):
-  """Verify that the input buffer contains what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_input_buffer: A string containing the contents of the current input
-      buffer.
-  """
-  test_case.assertEqual(exp_input_buffer, test_case.console.input_buffer,
-                        (b'input buffer does not match expected.\n'
-                         b'expected: |' + exp_input_buffer + b'|\n'
-                         b'got:      |' + test_case.console.input_buffer +
-                         b'|\n' + str(test_case.console).encode('ascii')))
-
-def CheckInputBufferPosition(test_case, exp_pos):
-  """Verify the input buffer position.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_pos: An integer representing the expected input buffer position.
-  """
-  test_case.assertEqual(exp_pos, test_case.console.input_buffer_pos,
-                        'input buffer position is incorrect.\ngot: ' +
-                        str(test_case.console.input_buffer_pos) + '\nexp: ' +
-                        str(exp_pos) + '\n' + str(test_case.console))
-
-def CheckHistoryBuffer(test_case, exp_history):
-  """Verify that the items in the history buffer are what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_history: A list of strings representing the expected contents of the
-      history buffer.
-  """
-  # First, check to see if the length is what we expect.
-  test_case.assertEqual(len(exp_history), len(test_case.console.history),
-                        ('The number of items in the history is unexpected.\n'
-                         'exp: ' + str(len(exp_history)) + '\n'
-                         'got: ' + str(len(test_case.console.history)) + '\n'
-                         'internal state:\n' + str(test_case.console)))
-
-  # Next, check the actual contents of the history buffer.
-  for i in range(len(exp_history)):
-    test_case.assertEqual(exp_history[i], test_case.console.history[i],
-                          (b'history buffer contents are incorrect.\n'
-                           b'exp: ' + exp_history[i] + b'\n'
-                           b'got: ' + test_case.console.history[i] + b'\n'
-                           b'internal state:\n' +
-                           str(test_case.console).encode('ascii')))
-
-
-class TestConsoleEditingMethods(unittest.TestCase):
-  """Test case to verify all console editing methods."""
-
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Create some mock pipes. These won't be used since we'll mock out sends
-    # to the interpreter.
-    mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-    # Console editing methods are only valid for enhanced EC images, therefore
-    # we have to assume that the "EC" we're talking to is enhanced.  By default,
-    # the console believes that the EC it's communicating with is NOT enhanced
-    # which is why we have to override it here.
-    self.console.enhanced_ec = True
-    self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True)
-
-  def test_EnteringChars(self):
-    """Verify that characters are echoed onto the console."""
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = len(test_str)
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Verify that the input buffer is correct.
-    expected_buffer = test_str
-    CheckInputBuffer(self, expected_buffer)
-
-    # Check console output
-    exp_console_out = test_str
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringDeletingMoreCharsThanEntered(self):
-    """Verify that we can press backspace more than we have entered chars."""
-    test_str = b'spamspam'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Now backspace 1 more than what we sent.
-    input_stream = []
-    for _ in range(len(test_str) + 1):
-      input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send that sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, examine the output stream for the correct sequence.
-    exp_console_out = test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Now, verify that we got what we expected.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringMoreThanCharLimit(self):
-    """Verify that we drop characters when the line is too long."""
-    test_str = self.console.line_limit * b'o' # All allowed.
-    test_str += 5 * b'x' # All should be dropped.
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that input buffer position should be equal to the line
-    # limit.
-    exp_pos = self.console.line_limit
-    CheckInputBufferPosition(self, exp_pos)
-
-    # The input buffer should only hold until the line limit.
-    exp_buffer = test_str[0:self.console.line_limit]
-    CheckInputBuffer(self, exp_buffer)
-
-    # Lastly, check that the extra characters are not printed.
-    exp_console_out = exp_buffer
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ValidKeysOnLongLine(self):
-    """Verify that we can still press valid keys if the line is too long."""
-    # Fill the line.
-    test_str = self.console.line_limit * b'o'
-    exp_console_out = test_str
-    # Try to fill it even more; these should all be dropped.
-    test_str += 5 * b'x'
-    input_stream = BytesToByteList(test_str)
-
-    # We should be able to press the following keys:
-    # - Backspace
-    # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N
-    # - Delete
-    # - Home/CTRL+A
-    # - End/CTRL+E
-    # - Carriage Return
-
-    # Backspace 1 character
-    input_stream.append(console.ControlKey.BACKSPACE)
-    exp_console_out += BACKSPACE_STRING
-    # Refill the line.
-    input_stream.extend(BytesToByteList(b'o'))
-    exp_console_out += b'o'
-
-    # Left arrow key.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # CTRL+B
-    input_stream.append(console.ControlKey.CTRL_B)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # CTRL+F
-    input_stream.append(console.ControlKey.CTRL_F)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Let's press enter now so we can test up and down.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    exp_console_out += b'\r\n' + self.console.prompt
-
-    # Up arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Down arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # CTRL+P
-    input_stream.append(console.ControlKey.CTRL_P)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # CTRL+N
-    input_stream.append(console.ControlKey.CTRL_N)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # Press the Up arrow key to reprint the long line.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Press the Home key to jump to the beginning of the line.
-    input_stream.extend(Keys.HOME)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press the End key to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Press CTRL+A to jump to the beginning of the line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press CTRL+E to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Move left one column so we can delete a character.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Press the delete key.
-    input_stream.extend(Keys.DEL)
-    # This should look like a space, and then move cursor left 1 column since
-    # we're at the end of line.
-    exp_console_out += b' ' + OutputStream.MoveCursorLeft(1)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify everything happened correctly.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceOnEmptyLine(self):
-    """Verify that we can backspace on an empty line with no bad effects."""
-    # Send a single backspace.
-    test_str = [console.ControlKey.BACKSPACE]
-
-    # Send the characters in.
-    for byte in test_str:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = 0
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Check that buffer is empty.
-    exp_input_buffer = b''
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Check that the console output is empty.
-    exp_console_out = b''
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceWithinLine(self):
-    """Verify that we shift the chars over when backspacing within a line."""
-    # Misspell 'help'
-    test_str = b'heelp'
-    input_stream = BytesToByteList(test_str)
-    # Use the arrow key to go back to fix it.
-    # Move cursor left 1 column.
-    input_stream.extend(2*Keys.LEFT_ARROW)
-    # Backspace once to remove the extra 'e'.
-    input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify the input buffer
-    exp_input_buffer = b'help'
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position. It should be at 2 (cursor over the 'l')
-    CheckInputBufferPosition(self, 2)
-
-    # We expect the console output to be the test string, with two moves to the
-    # left, another move left, and then the rest of the line followed by a
-    # space.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Move cursor left 1 column.
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Rest of the line and a space. (test_str in this case)
-    exp_console_out += b'lp '
-    # Reset the cursor 2 + 1 to the left.
-    exp_console_out += OutputStream.MoveCursorLeft(3)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToBeginningOfLineViaCtrlA(self):
-    """Verify that we can jump to the beginning of a line with Ctrl+A."""
-    # Enter some chars and press CTRL+A
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A]
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to see our test string followed by a move cursor left.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-
-    # Check to see what whas printed on the console.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Check that the input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Check input buffer still contains our test string.
-    CheckInputBuffer(self, test_str)
-
-  def test_JumpToBeginningOfLineViaHomeKey(self):
-    """Jump to beginning of line via HOME key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.HOME)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, verify that the input buffer did not change.
-    CheckInputBuffer(self, test_str)
-
-    # Lastly, check that the cursor moved correctly.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaEndKey(self):
-    """Jump to the end of the line using the END key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream += [console.ControlKey.CTRL_A]
-    # Now, jump to the end of the line.
-    input_stream.extend(Keys.END)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is correct.  This should be at the
-    # end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # The expected output should be the test string, followed by a jump to the
-    # beginning of the line, and lastly a jump to the end of the line.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Now the jump back to the end of the line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify console output stream.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaCtrlE(self):
-    """Enter some chars and then try to jump to the end. (Should be a no-op)"""
-    test_str = b'sysinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_E)
-
-    # Send out the stream
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position isn't any further than we expect.
-    # At this point, the position should be at the end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Now, let's try to jump to the beginning and then jump back to the end.
-    input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Lastly try to jump again, beyond the end.
-    input_stream = [console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # We expect to see the test string, a jump to the beginning of the line, and
-    # one jump to the end of the line.
-    exp_console_out = test_str
-    # Jump to beginning.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump back to end.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithArrowKey(self):
-    """Move cursor left one column with arrow key."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.LEFT_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithCtrlB(self):
-    """Move cursor back one column with Ctrl+B."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_B)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveRightWithArrowKey(self):
-    """Move cursor one column to the right with the arrow key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Press right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveRightWithCtrlF(self):
-    """Move cursor forward one column with Ctrl+F."""
-    test_str = b'panicinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Now, move right one column.
-    input_stream.append(console.ControlKey.CTRL_F)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ImpossibleMoveLeftWithArrowKey(self):
-    """Verify that we can't move left at the beginning of the line."""
-    # We shouldn't be able to move left if we're at the beginning of the line.
-    input_stream = Keys.LEFT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_ImpossibleMoveRightWithArrowKey(self):
-    """Verify that we can't move right at the end of the line."""
-    # We shouldn't be able to move right if we're at the end of the line.
-    input_stream = Keys.RIGHT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_KillEntireLine(self):
-    """Verify that we can kill an entire line with Ctrl+K."""
-    test_str = b'accelinfo on'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line and then kill it with Ctrl+K.
-    input_stream.extend([console.ControlKey.CTRL_A, console.ControlKey.CTRL_K])
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that the input buffer is empty.
-    CheckInputBuffer(self, b'')
-
-    # The buffer position should be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # What we expect to see on the console stream should be the following.  The
-    # test string, a jump to the beginning of the line, then jump back to the
-    # end of the line and replace the line with spaces.
-    exp_console_out = test_str
-    # Jump to beginning of line.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump to end of line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-    # Replace line with spaces, which looks like backspaces.
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_KillPartialLine(self):
-    """Verify that we can kill a portion of a line."""
-    test_str = b'accelread 0 1'
-    input_stream = BytesToByteList(test_str)
-    len_to_kill = 5
-    for _ in range(len_to_kill):
-      # Move cursor left
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now kill
-    input_stream.append(console.ControlKey.CTRL_K)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, check that the input buffer was truncated.
-    exp_input_buffer = test_str[:-len_to_kill]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position.
-    CheckInputBufferPosition(self, len(test_str) - len_to_kill)
-
-    # The console output stream that we expect is the test string followed by a
-    # move left of len_to_kill, then a jump to the end of the line and backspace
-    # of len_to_kill.
-    exp_console_out = test_str
-    for _ in range(len_to_kill):
-      # Move left 1 column.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Then jump to the end of the line
-    exp_console_out += OutputStream.MoveCursorRight(len_to_kill)
-    # Backspace of len_to_kill
-    for _ in range(len_to_kill):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_InsertingCharacters(self):
-    """Verify that we can insert characters within the line."""
-    test_str = b'accel 0 1' # Here we forgot the 'read' part in 'accelread'
-    input_stream = BytesToByteList(test_str)
-    # We need to move over to the 'l' and add read.
-    insertion_point = test_str.find(b'l') + 1
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now, add in 'read'
-    added_str = b'read'
-    input_stream.extend(BytesToByteList(added_str))
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that the input buffer is correct.
-    exp_input_buffer = test_str[:insertion_point] + added_str
-    exp_input_buffer += test_str[insertion_point:]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify that the input buffer position is correct.
-    exp_input_buffer_pos = insertion_point + len(added_str)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-    # The console output stream that we expect is the test string, followed by
-    # move cursor left until the 'l' was found, the added test string while
-    # shifting characters around.
-    exp_console_out = test_str
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Now for each character, write the rest of the line will be shifted to the
-    # right one column.
-    for i in range(len(added_str)):
-      # Printed character.
-      exp_console_out += added_str[i:i+1]
-      # The rest of the line
-      exp_console_out += test_str[insertion_point:]
-      # Reset the cursor back left
-      reset_dist = len(test_str[insertion_point:])
-      exp_console_out += OutputStream.MoveCursorLeft(reset_dist)
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_StoreCommandHistory(self):
-    """Verify that entered commands are stored in the history."""
-    test_commands = []
-    test_commands.append(b'help')
-    test_commands.append(b'version')
-    test_commands.append(b'accelread 0 1')
-    input_stream = []
-    for c in test_commands:
-      input_stream.extend(BytesToByteList(c))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to have the test commands in the history buffer.
-    exp_history_buf = test_commands
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_CycleUpThruCommandHistory(self):
-    """Verify that the UP arrow key will print itmes in the history buffer."""
-    # Enter some commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key to print the previous entries.
-    for i in range(len(test_commands)):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be test commands with prompts printed in
-    # between, followed by line kills with the previous test commands printed.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 0, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
-        exp_console_out += BACKSPACE_STRING
-
-    # The last command should just be printed out with no backspacing.
-    exp_console_out += test_commands[0]
-
-    # Now, verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_UpArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Press the up arrow key twice.
-    input_stream = 2 * Keys.UP_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_UpArrowDoesNotGoOutOfBounds(self):
-    """Verify that pressing the up arrow many times won't go out of bounds."""
-    # Enter one command.
-    test_str = b'help version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # Then press the up arrow key twice.
-    input_stream.extend(2 * Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.
-    exp_history_buf = [test_str]
-    CheckHistoryBuffer(self, exp_history_buf)
-
-    # We expect that the console output should only contain our entered command,
-    # a new prompt, and then our command aggain.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    # Pressing up should reprint the command we entered.
-    exp_console_out += test_str
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_CycleDownThruCommandHistory(self):
-    """Verify that we can select entries by hitting the down arrow."""
-    # Enter at least 4 commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key twice to print the previous two entries.
-    for i in range(2):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Now, hit the DOWN arrow key twice to print the newer entries.
-    input_stream.extend(2*Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be commands that we entered, followed by
-    # prompts, then followed by our last two commands in reverse.  Then, we
-    # should see the last entry in the list, followed by the saved partial cmd
-    # of a blank line.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 1, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
-        exp_console_out += BACKSPACE_STRING
-
-    # When we press down, it should have cleared the last command (which we
-    # covered with the previous for loop), and then prints the next command.
-    exp_console_out += test_commands[3]
-    for i in range(len(test_commands[3])):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = b'' # Empty because our partial command was empty.
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_SavingPartialCommandWhenNavigatingHistory(self):
-    """Verify that partial commands are saved when navigating history."""
-    # Enter a command.
-    test_str = b'accelinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Enter a partial command.
-    partial_cmd = b'ver'
-    input_stream.extend(BytesToByteList(partial_cmd))
-
-    # Hit the UP arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    # Then, the DOWN arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, a prompt, the
-    # partial command, clearing of the partial command, the command entered,
-    # clearing of the command entered, and then the partial command.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    exp_console_out += partial_cmd
-    for _ in range(len(partial_cmd)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += partial_cmd
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = partial_cmd
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_DownArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Then press the up down arrow twice.
-    input_stream = 2 * Keys.DOWN_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_DeleteCharsUsingDELKey(self):
-    """Verify that we can delete characters using the DEL key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-
-    # Hit the left arrow key 2 times.
-    input_stream.extend(2 * Keys.LEFT_ARROW)
-
-    # Press the DEL key.
-    input_stream.extend(Keys.DEL)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, 2 individual cursor
-    # moves to the left, and then removing a char and shifting everything to the
-    # left one column.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Remove the char by shifting everything to the left one, slicing out the
-    # remove char.
-    exp_console_out += test_str[-1:] + b' '
-
-    # Reset the cursor by moving back 2 columns because of the 'n' and space.
-    exp_console_out += OutputStream.MoveCursorLeft(2)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.  The input buffer should have the char sliced out and
-    # be positioned where the char was removed.
-    exp_input_buffer = test_str[:-2] + test_str[-1:]
-    exp_input_buffer_pos = len(exp_input_buffer) - 1
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_RepeatedCommandInHistory(self):
-    """Verify that we don't store 2 consecutive identical commands in history"""
-    # Enter a few commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    # Repeat the last command.
-    test_commands.append(test_commands[len(test_commands)-1])
-
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.  The last command, since
-    # it was repeated, should not have been added to the history.
-    exp_history_buf = test_commands[0:len(test_commands)-1]
-    CheckHistoryBuffer(self, exp_history_buf)
-
-
-class TestConsoleCompatibility(unittest.TestCase):
-  """Verify that console can speak to enhanced and non-enhanced EC images."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_ActAsPassThruInNonEnhancedMode(self, mock_check):
-    """Verify we simply pass everything thru to non-enhanced ECs.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # Assume EC interrogations indicate that the image is non-enhanced.
-    mock_check.return_value = False
-
-    # Press enter, followed by the command, and another enter.
-    input_stream = []
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    test_command = b'version'
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Expected calls to send down the pipe would be each character of the test
-    # command.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify that the calls happened.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-    # Since we're acting as a pass-thru, the input buffer should be empty and
-    # input_buffer_pos is 0.
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromNonEnhancedToEnhanced(self, mock_check):
-    """Verify that we transition correctly to enhanced mode.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an enhanced EC image.
-    mock_check.return_value = True
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was a non-enhanced image.
-    self.console.enhanced_ec = False
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-
-    expected_calls = []
-    # All keystrokes to the console should be directed straight through to the
-    # EC until we press the enter key.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-
-    # Press the enter key.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # The enter key should not be sent to the pipe since we should negotiate
-    # to an enhanced EC image.
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # At this point, we should have negotiated to enhanced.
-    self.assertTrue(self.console.enhanced_ec, msg=('Did not negotiate to '
-                                                   'enhanced EC image.'))
-
-    # The command would have been dropped however, so verify this...
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-    # ...and repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're enhanced now, we should have sent the entire command as one
-    # string with no trailing carriage return
-    expected_calls.append(mock.call(test_command))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromEnhancedToNonEnhanced(self, mock_check):
-    """Verify that we transition correctly to non-enhanced mode.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an non-enhanced EC
-    # image.
-    mock_check.return_value = False
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was an enhanced image.
-    self.console.enhanced_ec = True
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # But, we will negotiate to non-enhanced however, dropping this command.
-    # Verify this.
-    self.assertFalse(self.console.enhanced_ec, msg=('Did not negotiate to'
-                                                    'non-enhanced EC image.'))
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-    # The carriage return should have passed through though.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Since the command was dropped, repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're not enhanced now, we should have sent each character in the
-    # entire command separately and a carriage return.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  def test_EnhancedCheckIfTimedOut(self):
-    """Verify that the check returns false if it times out."""
-    # Make the debug pipe "time out".
-    self.console.dbg_pipe.poll.return_value = False
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfACKReceived(self):
-    """Verify that the check returns true if the ACK is received."""
-    # Make the debug pipe return EC_ACK.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK
-    self.assertTrue(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfWrong(self):
-    """Verify that the check returns false if byte received is wrong."""
-    # Make the debug pipe return the wrong byte.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = b'\xff'
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckUsingBuffer(self):
-    """Verify that given reboot output, enhanced EC images are detected."""
-    enhanced_output_stream = b"""
---- UART initialized after reboot ---
-[Reset cause: reset-pin soft]
-[Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:26:20 aaboagye@lithium.mtv.corp.google.com]
-[0.001695 KB boot key 0]
-[0.001790 Inits done]
-[0.001923 not sysjump; forcing AP shutdown]
-[0.002047 EC triggered warm reboot]
-[0.002155 assert GPIO_PMIC_WARM_RESET_L for 4 ms]
-[0.006326 auto_power_on set due to reset_flag 0x22]
-[0.006477 Wait for battery stabilized during 1000000]
-[0.007368 battery responded with status c0]
-[0.009099 hash start 0x00010000 0x0000eb7c]
-[0.009307 KB init state: -- -- -- -- -- -- -- -- -- -- -- -- --]
-[0.009531 KB wait]
-Enhanced Console is enabled (v1.0.0); type HELP for help.
-> [0.009782 event set 0x00002000]
-[0.009903 hostcmd init 0x2000]
-[0.010031 power state 0 = G3, in 0x0000]
-[0.010173 power state 4 = G3->S5, in 0x0000]
-[0.010324 power state 1 = S5, in 0x0000]
-[0.010466 power on 2]
-[0.010566 power state 5 = S5->S3, in 0x0000]
-[0.037713 event set 0x00000080]
-[0.037836 event set 0x00400000]
-[0.038675 Battery 89% / 1092h:15 to empty]
-[0.224060 hash done 41dac382e3a6e3d2ea5b4d789c1bc46525cae7cc5ff6758f0de8d8369b506f57]
-[0.375150 POWER_GOOD seen]
-"""
-    for line in enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
-
-    # Since the enhanced console string was present in the output, the console
-    # should have caught it.
-    self.assertTrue(self.console.enhanced_ec)
-
-    # Also should check that the command was sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced True')
-
-    # Now test the non-enhanced EC image.
-    self.console.cmd_pipe.reset_mock()
-    non_enhanced_output_stream = b"""
---- UART initialized after reboot ---
-[Reset cause: reset-pin soft]
-[Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:03:15 aaboagye@lithium.mtv.corp.google.com]
-[0.001695 KB boot key 0]
-[0.001790 Inits done]
-[0.001923 not sysjump; forcing AP shutdown]
-[0.002047 EC triggered warm reboot]
-[0.002156 assert GPIO_PMIC_WARM_RESET_L for 4 ms]
-[0.006326 auto_power_on set due to reset_flag 0x22]
-[0.006477 Wait for battery stabilized during 1000000]
-[0.007368 battery responded with status c0]
-[0.008951 hash start 0x00010000 0x0000ed78]
-[0.009159 KB init state: -- -- -- -- -- -- -- -- -- -- -- -- --]
-[0.009383 KB wait]
-Console is enabled; type HELP for help.
-> [0.009602 event set 0x00002000]
-[0.009722 hostcmd init 0x2000]
-[0.009851 power state 0 = G3, in 0x0000]
-[0.009993 power state 4 = G3->S5, in 0x0000]
-[0.010144 power state 1 = S5, in 0x0000]
-[0.010285 power on 2]
-[0.010385 power state 5 = S5->S3, in 0x0000]
-"""
-    for line in non_enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
-
-    # Since the default console string is present in the output, it should be
-    # determined to be non enhanced now.
-    self.assertFalse(self.console.enhanced_ec)
-
-    # Check that command was also sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced False')
-
-
-class TestOOBMConsoleCommands(unittest.TestCase):
-  """Verify that OOBM console commands work correctly."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the master and slave PTYs to the file to
-    # create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-    self.console.oobm_queue = mock.MagicMock()
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_InterrogateCommand(self, mock_check):
-    """Verify that 'interrogate' command works as expected.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECIMage()
-        method.
-    """
-    input_stream = []
-    expected_calls = []
-    mock_check.side_effect = [False]
-
-    # 'interrogate never' should disable the interrogation from happening at
-    # all.
-    cmd = b'interrogate never'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate auto' should not interrogate at all.  It should only be
-    # scanning the output stream for the 'console is enabled' strings.
-    cmd = b'interrogate auto'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate always' should, like its name implies, interrogate always
-    # after each press of the enter key.  This was the former way of doing
-    # interrogation.
-    cmd = b'interrogate always'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # The Check method should be called 3 times here.
-    mock_check.side_effect = [False, False, False]
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'help list'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'taskinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hibdelay'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check method should have been called 3 times here.
-    expected_calls = [mock.call(), mock.call(), mock.call()]
-    mock_check.assert_has_calls(expected_calls)
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Now, let's try to assume that the image is enhanced while still disabling
-    # interrogation.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-    input_stream = []
-    cmd = b'interrogate never enhanced'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'chgstate'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hash'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysjump rw'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The check method should have never been called.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be enhanced.
-    self.assertTrue(self.console.enhanced_ec, 'The image should be'
-                    ' assumed to be enhanced.')
-
-
-if __name__ == '__main__':
-  unittest.main()
diff --git a/util/ec3po/interpreter.py b/util/ec3po/interpreter.py
deleted file mode 100644
index 4e151083bd..0000000000
--- a/util/ec3po/interpreter.py
+++ /dev/null
@@ -1,467 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""EC-3PO EC Interpreter
-
-interpreter provides the interpretation layer between the EC UART and the user.
-It receives commands through its command pipe, formats the commands for the EC,
-and sends the command to the EC.  It also presents data from the EC to either be
-displayed via the interactive console interface, or some other consumer.  It
-additionally supports automatic command retrying if the EC drops a character in
-a command.
-"""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import binascii
-import copy
-import logging
-import os
-import select
-import traceback
-
-import six
-
-
-COMMAND_RETRIES = 3  # Number of attempts to retry a command.
-EC_MAX_READ = 1024  # Max bytes to read at a time from the EC.
-EC_SYN = b'\xec'  # Byte indicating EC interrogation.
-EC_ACK = b'\xc0'  # Byte representing correct EC response to interrogation.
-
-
-class LoggerAdapter(logging.LoggerAdapter):
-  """Class which provides a small adapter for the logger."""
-
-  def process(self, msg, kwargs):
-    """Prepends the served PTY to the beginning of the log message."""
-    return '%s - %s' % (self.extra['pty'], msg), kwargs
-
-
-class Interpreter(object):
-  """Class which provides the interpretation layer between the EC and user.
-
-  This class essentially performs all of the intepretation for the EC and the
-  user.  It handles all of the automatic command retrying as well as the
-  formation of commands for EC images which support that.
-
-  Attributes:
-    logger: A logger for this module.
-    ec_uart_pty: An opened file object to the raw EC UART PTY.
-    ec_uart_pty_name: A string containing the name of the raw EC UART PTY.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the command pipe.  This must be a
-      bidirectional pipe.  Commands and responses will utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the debug pipe. This must be a
-      unidirectional pipe with write capabilities.  EC debug output will utilize
-      this pipe.
-    cmd_retries: An integer representing the number of attempts the console
-      should retry commands if it receives an error.
-    log_level: An integer representing the numeric value of the log level.
-    inputs: A list of objects that the intpreter selects for reading.
-      Initially, these are the EC UART and the command pipe.
-    outputs: A list of objects that the interpreter selects for writing.
-    ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART.
-    last_cmd: A string that represents the last command sent to the EC.  If an
-      error is encountered, the interpreter will attempt to retry this command
-      up to COMMAND_RETRIES.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      and is changed depending on the result of an interrogation.
-    interrogating: A boolean indicating if we are in the middle of interrogating
-      the EC.
-    connected: A boolean indicating if the interpreter is actually connected to
-      the UART and listening.
-  """
-  def __init__(self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO,
-               name=None):
-    """Intializes an Interpreter object with the provided args.
-
-    Args:
-      ec_uart_pty: A string representing the EC UART to connect to.
-      cmd_pipe: A socket.socket or multiprocessing.Connection object which
-        represents the Interpreter side of the command pipe.  This must be a
-        bidirectional pipe.  Commands and responses will utilize this pipe.
-      dbg_pipe: A socket.socket or multiprocessing.Connection object which
-        represents the Interpreter side of the debug pipe. This must be a
-        unidirectional pipe with write capabilities.  EC debug output will
-        utilize this pipe.
-      cmd_retries: An integer representing the number of attempts the console
-        should retry commands if it receives an error.
-      log_level: An optional integer representing the numeric value of the log
-        level.  By default, the log level will be logging.INFO (20).
-      name: the console source name
-    """
-    # Create a unique logger based on the interpreter name
-    interpreter_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Interpreter' % interpreter_prefix)
-    self.logger = LoggerAdapter(logger, {'pty': ec_uart_pty})
-    # TODO(https://crbug.com/1162189): revist the 2 TODOs below
-    # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
-    # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
-    # that gets fixed, or keep two pty: one for reading and one for writing
-    self.ec_uart_pty = open(ec_uart_pty, 'r+b', buffering=0)
-    self.ec_uart_pty_name = ec_uart_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.cmd_retries = COMMAND_RETRIES
-    self.log_level = log_level
-    self.inputs = [self.ec_uart_pty, self.cmd_pipe]
-    self.outputs = []
-    self.ec_cmd_queue = six.moves.queue.Queue()
-    self.last_cmd = b''
-    self.enhanced_ec = False
-    self.interrogating = False
-    self.connected = True
-
-  def __str__(self):
-    """Show internal state of the Interpreter object.
-
-    Returns:
-      A string that shows the values of the attributes.
-    """
-    string = []
-    string.append('%r' % self)
-    string.append('ec_uart_pty: %s' % self.ec_uart_pty)
-    string.append('cmd_pipe: %r' % self.cmd_pipe)
-    string.append('dbg_pipe: %r' % self.dbg_pipe)
-    string.append('cmd_retries: %d' % self.cmd_retries)
-    string.append('log_level: %d' % self.log_level)
-    string.append('inputs: %r' % self.inputs)
-    string.append('outputs: %r' % self.outputs)
-    string.append('ec_cmd_queue: %r' % self.ec_cmd_queue)
-    string.append('last_cmd: \'%s\'' % self.last_cmd)
-    string.append('enhanced_ec: %r' % self.enhanced_ec)
-    string.append('interrogating: %r' % self.interrogating)
-    return '\n'.join(string)
-
-  def EnqueueCmd(self, command):
-    """Enqueue a command to be sent to the EC UART.
-
-    Args:
-      command: A string which contains the command to be sent.
-    """
-    self.ec_cmd_queue.put(command)
-    self.logger.log(1, 'Commands now in queue: %d', self.ec_cmd_queue.qsize())
-
-    # Add the EC UART as an output to be serviced.
-    if self.connected and self.ec_uart_pty not in self.outputs:
-      self.outputs.append(self.ec_uart_pty)
-
-  def PackCommand(self, raw_cmd):
-    r"""Packs a command for use with error checking.
-
-    For error checking, we pack console commands in a particular format.  The
-    format is as follows:
-
-      &&[x][x][x][x]&{cmd}\n\n
-      ^ ^    ^^    ^^  ^  ^-- 2 newlines.
-      | |    ||    ||  |-- the raw console command.
-      | |    ||    ||-- 1 ampersand.
-      | |    ||____|--- 2 hex digits representing the CRC8 of cmd.
-      | |____|-- 2 hex digits reprsenting the length of cmd.
-      |-- 2 ampersands
-
-    Args:
-      raw_cmd: A pre-packed string which contains the raw command.
-
-    Returns:
-      A string which contains the packed command.
-    """
-    # Don't pack a single carriage return.
-    if raw_cmd != b'\r':
-      # The command format is as follows.
-      # &&[x][x][x][x]&{cmd}\n\n
-      packed_cmd = []
-      packed_cmd.append(b'&&')
-      # The first pair of hex digits are the length of the command.
-      packed_cmd.append(b'%02x' % len(raw_cmd))
-      # Then the CRC8 of cmd.
-      packed_cmd.append(b'%02x' % Crc8(raw_cmd))
-      packed_cmd.append(b'&')
-      # Now, the raw command followed by 2 newlines.
-      packed_cmd.append(raw_cmd)
-      packed_cmd.append(b'\n\n')
-      return b''.join(packed_cmd)
-    else:
-      return raw_cmd
-
-  def ProcessCommand(self, command):
-    """Captures the input determines what actions to take.
-
-    Args:
-      command: A string representing the command sent by the user.
-    """
-    if command == b'disconnect':
-      if self.connected:
-        self.logger.debug('UART disconnect request.')
-        # Drop all pending commands if any.
-        while not self.ec_cmd_queue.empty():
-          c = self.ec_cmd_queue.get()
-          self.logger.debug('dropped: \'%s\'', c)
-        if self.enhanced_ec:
-          # Reset retry state.
-          self.cmd_retries = COMMAND_RETRIES
-          self.last_cmd = b''
-        # Get the UART that the interpreter is attached to.
-        fileobj = self.ec_uart_pty
-        self.logger.debug('fileobj: %r', fileobj)
-        # Remove the descriptor from the inputs and outputs.
-        self.inputs.remove(fileobj)
-        if fileobj in self.outputs:
-          self.outputs.remove(fileobj)
-        self.logger.debug('Removed fileobj. Remaining inputs: %r', self.inputs)
-        # Close the file.
-        fileobj.close()
-        # Mark the interpreter as disconnected now.
-        self.connected = False
-        self.logger.debug('Disconnected from %s.', self.ec_uart_pty_name)
-      return
-
-    elif command == b'reconnect':
-      if not self.connected:
-        self.logger.debug('UART reconnect request.')
-        # Reopen the PTY.
-        # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
-        # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
-        # that gets fixed, or keep two pty: one for reading and one for writing
-        fileobj = open(self.ec_uart_pty_name, 'r+b', buffering=0)
-        self.logger.debug('fileobj: %r', fileobj)
-        self.ec_uart_pty = fileobj
-        # Add the descriptor to the inputs.
-        self.inputs.append(fileobj)
-        self.logger.debug('fileobj added. curr inputs: %r', self.inputs)
-        # Mark the interpreter as connected now.
-        self.connected = True
-        self.logger.debug('Connected to %s.', self.ec_uart_pty_name)
-      return
-
-    elif command.startswith(b'enhanced'):
-      self.enhanced_ec = command.split(b' ')[1] == b'True'
-      return
-
-    # Ignore any other commands while in the disconnected state.
-    self.logger.log(1, 'command: \'%s\'', command)
-    if not self.connected:
-      self.logger.debug('Ignoring command because currently disconnected.')
-      return
-
-    # Remove leading and trailing spaces only if this is an enhanced EC image.
-    # For non-enhanced EC images, commands will be single characters at a time
-    # and can be spaces.
-    if self.enhanced_ec:
-      command = command.strip(b' ')
-
-    # There's nothing to do if the command is empty.
-    if len(command) == 0:
-      return
-
-    # Handle log level change requests.
-    if command.startswith(b'loglevel'):
-      self.logger.debug('Log level change request.')
-      new_log_level = int(command.split(b' ')[1])
-      self.logger.logger.setLevel(new_log_level)
-      self.logger.info('Log level changed to %d.', new_log_level)
-      return
-
-    # Check for interrogation command.
-    if command == EC_SYN:
-      # User is requesting interrogation.  Send SYN as is.
-      self.logger.debug('User requesting interrogation.')
-      self.interrogating = True
-      # Assume the EC isn't enhanced until we get a response.
-      self.enhanced_ec = False
-    elif self.enhanced_ec:
-      # Enhanced EC images require the plaintext commands to be packed.
-      command = self.PackCommand(command)
-      # TODO(aaboagye): Make a dict of commands and keys and eventually,
-      # handle partial matching based on unique prefixes.
-
-    self.EnqueueCmd(command)
-
-  def HandleCmdRetries(self):
-    """Attempts to retry commands if possible."""
-    if self.cmd_retries > 0:
-      # The EC encountered an error.  We'll have to retry again.
-      self.logger.warning('Retrying command...')
-      self.cmd_retries -= 1
-      self.logger.warning('Retries remaining: %d', self.cmd_retries)
-      # Retry the command and add the EC UART to the writers again.
-      self.EnqueueCmd(self.last_cmd)
-      self.outputs.append(self.ec_uart_pty)
-    else:
-      # We're out of retries, so just give up.
-      self.logger.error('Command failed.  No retries left.')
-      # Clear the command in progress.
-      self.last_cmd = b''
-      # Reset the retry count.
-      self.cmd_retries = COMMAND_RETRIES
-
-  def SendCmdToEC(self):
-    """Sends a command to the EC."""
-    # If we're retrying a command, just try to send it again.
-    if self.cmd_retries < COMMAND_RETRIES:
-      cmd = self.last_cmd
-    else:
-      # If we're not retrying, we should not be writing to the EC if we have no
-      # items in our command queue.
-      assert not self.ec_cmd_queue.empty()
-      # Get the command to send.
-      cmd = self.ec_cmd_queue.get()
-
-    # Send the command.
-    self.ec_uart_pty.write(cmd)
-    self.ec_uart_pty.flush()
-    self.logger.log(1, 'Sent command to EC.')
-
-    if self.enhanced_ec and cmd != EC_SYN:
-      # Now, that we've sent the command, store the current command as the last
-      # command sent.  If we encounter an error string, we will attempt to retry
-      # this command.
-      if cmd != self.last_cmd:
-        self.last_cmd = cmd
-        # Reset the retry count.
-        self.cmd_retries = COMMAND_RETRIES
-
-    # If no command is pending to be sent, then we can remove the EC UART from
-    # writers.  Might need better checking for command retry logic in here.
-    if self.ec_cmd_queue.empty():
-      # Remove the EC UART from the writers while we wait for a response.
-      self.logger.debug('Removing EC UART from writers.')
-      self.outputs.remove(self.ec_uart_pty)
-
-  def HandleECData(self):
-    """Handle any debug prints from the EC."""
-    self.logger.log(1, 'EC has data')
-    # Read what the EC sent us.
-    data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ)
-    self.logger.log(1, 'got: \'%s\'', binascii.hexlify(data))
-    if b'&E' in data and self.enhanced_ec:
-      # We received an error, so we should retry it if possible.
-      self.logger.warning('Error string found in data.')
-      self.HandleCmdRetries()
-      return
-
-    # If we were interrogating, check the response and update our knowledge
-    # of the current EC image.
-    if self.interrogating:
-      self.enhanced_ec = data == EC_ACK
-      if self.enhanced_ec:
-        self.logger.debug('The current EC image seems enhanced.')
-      else:
-        self.logger.debug('The current EC image does NOT seem enhanced.')
-      # Done interrogating.
-      self.interrogating = False
-    # For now, just forward everything the EC sends us.
-    self.logger.log(1, 'Forwarding to user...')
-    self.dbg_pipe.send(data)
-
-  def HandleUserData(self):
-    """Handle any incoming commands from the user.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.cmd_pipe.recv().
-    """
-    self.logger.log(1, 'Command data available.  Begin processing.')
-    data = self.cmd_pipe.recv()
-    # Process the command.
-    self.ProcessCommand(data)
-
-
-def Crc8(data):
-  """Calculates the CRC8 of data.
-
-  The generator polynomial used is: x^8 + x^2 + x + 1.
-  This is the same implementation that is used in the EC.
-
-  Args:
-    data: A string of data that we wish to calculate the CRC8 on.
-
-  Returns:
-    crc >> 8: An integer representing the CRC8 value.
-  """
-  crc = 0
-  for byte in six.iterbytes(data):
-    crc ^= (byte << 8)
-    for _ in range(8):
-      if crc & 0x8000:
-        crc ^= (0x1070 << 3)
-      crc <<= 1
-  return crc >> 8
-
-
-def StartLoop(interp, shutdown_pipe=None):
-  """Starts an infinite loop of servicing the user and the EC.
-
-  StartLoop checks to see if there are any commands to process, processing them
-  if any, and forwards EC output to the user.
-
-  When sending a command to the EC, we send the command once and check the
-  response to see if the EC encountered an error when receiving the command.  An
-  error condition is reported to the interpreter by a string with at least one
-  '&' and 'E'.  The full string is actually '&&EE', however it's possible that
-  the leading ampersand or trailing 'E' could be dropped.  If an error is
-  encountered, the interpreter will retry up to the amount configured.
-
-  Args:
-    interp: An Interpreter object that has been properly initialised.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    while continue_looping:
-      # The inputs list is created anew in each loop iteration because the
-      # Interpreter class sometimes modifies the interp.inputs list.
-      if shutdown_pipe is None:
-        inputs = interp.inputs
-      else:
-        inputs = list(interp.inputs)
-        inputs.append(shutdown_pipe)
-
-      readable, writeable, _ = select.select(inputs, interp.outputs, [])
-
-      for obj in readable:
-        # Handle any debug prints from the EC.
-        if obj is interp.ec_uart_pty:
-          interp.HandleECData()
-
-        # Handle any commands from the user.
-        elif obj is interp.cmd_pipe:
-          try:
-            interp.HandleUserData()
-          except EOFError:
-            interp.logger.debug(
-                'ec3po interpreter received EOF from cmd_pipe in '
-                'HandleUserData()')
-            continue_looping = False
-
-        elif obj is shutdown_pipe:
-          interp.logger.debug(
-              'ec3po interpreter received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      for obj in writeable:
-        # Send a command to the EC.
-        if obj is interp.ec_uart_pty:
-          interp.SendCmdToEC()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    interp.cmd_pipe.close()
-    interp.dbg_pipe.close()
-    interp.ec_uart_pty.close()
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    interp.logger.debug('Exit ec3po interpreter loop for %s',
-                        interp.ec_uart_pty_name)
diff --git a/util/ec3po/interpreter_unittest.py b/util/ec3po/interpreter_unittest.py
deleted file mode 100755
index fe4d43c351..0000000000
--- a/util/ec3po/interpreter_unittest.py
+++ /dev/null
@@ -1,380 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Unit tests for the EC-3PO interpreter."""
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-
-import logging
-import mock
-import tempfile
-import unittest
-
-import six
-
-from ec3po import interpreter
-from ec3po import threadproc_shim
-
-
-def GetBuiltins(func):
-  if six.PY2:
-    return '__builtin__.' + func
-  return 'builtins.' + func
-
-
-class TestEnhancedECBehaviour(unittest.TestCase):
-  """Test case to verify all enhanced EC interpretation tasks."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_HandlingCommandsThatProduceNoOutput(self, mock_os):
-    """Verify that the Interpreter correctly handles non-output commands.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now that the interrogation was complete, it's time to send down the real
-    # command.
-    test_cmd = b'chan save'
-    # Send the test command down the pipe.
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Now that the first command was sent, we should send another command which
-    # produces no output.  The console would send another interrogation.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Again, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now send the second test command.
-    test_cmd = b'chan 0'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Finally, verify that the appropriate writes were actually sent to the EC.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_CommandRetryingOnError(self, mock_os):
-    """Verify that commands are retried if an error is encountered.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Let's send a command that is received on the EC-side with an error.
-    test_cmd = b'accelinfo'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    packed_cmd = self.itpr.PackCommand(test_cmd)
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    # Have the EC return the error string twice.
-    mock_os.read.side_effect = [b'&&EE', b'&&EE']
-    for i in range(2):
-      # When reading the EC, the interpreter will call file.fileno() to pass to
-      # os.read().
-      expected_ec_calls.append(mock.call().fileno())
-      # Simulate the response.
-      self.itpr.HandleECData()
-
-      # Since an error was received, the EC should attempt to retry the command.
-      expected_ec_calls.extend([mock.call().write(packed_cmd),
-                                mock.call().flush()])
-      # Verify that the retry count was decremented.
-      self.assertEqual(interpreter.COMMAND_RETRIES-i-1, self.itpr.cmd_retries,
-                       'Unexpected cmd_remaining count.')
-      # Actually retry the command.
-      self.itpr.SendCmdToEC()
-
-    # Now assume that the last one goes through with no trouble.
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    self.itpr.SendCmdToEC()
-
-    # Verify all the calls.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  def test_PackCommandsForEnhancedEC(self):
-    """Verify that the interpreter packs commands for enhanced EC images."""
-    # Assume current EC image is enhanced.
-    self.itpr.enhanced_ec = True
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_called_once_with(test_cmd)
-
-  def test_DontPackCommandsForNonEnhancedEC(self):
-    """Verify the interpreter doesn't pack commands for non-enhanced images."""
-    # Assume current EC image is not enhanced.
-    self.itpr.enhanced_ec = False
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_not_called()
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_KeepingTrackOfInterrogation(self, mock_os):
-    """Verify that the interpreter can track the state of the interrogation.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module. for this test
-        case.
-    """
-    # Upon init, the interpreter should assume that the current EC image is not
-    # enhanced.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec upon'
-                                                 ' init is not False.'))
-
-    # Assume an interrogation request comes in from the user.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify the state is now within an interrogation.
-    self.assertTrue(self.itpr.interrogating, 'interrogating should be True')
-    # The state of enhanced_ec should not be changed yet because we haven't
-    # received a valid response yet.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec is '
-                                                 'not False.'))
-
-    # Assume that the EC responds with an EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    self.itpr.HandleECData()
-
-    # Now, the interrogation should be complete and we should know that the
-    # current EC image is enhanced.
-    self.assertFalse(self.itpr.interrogating, msg=('interrogating should be '
-                                                   'False'))
-    self.assertTrue(self.itpr.enhanced_ec, msg='enhanced_ec sholud be True')
-
-    # Now let's perform another interrogation, but pretend that the EC ignores
-    # it.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify interrogating state.
-    self.assertTrue(self.itpr.interrogating, 'interrogating sholud be True')
-    # We should assume that the image is not enhanced until we get the valid
-    # response.
-    self.assertFalse(self.itpr.enhanced_ec, 'enhanced_ec should be False now.')
-
-    # Let's pretend that we get a random debug print.  This should clear the
-    # interrogating flag.
-    mock_os.read.side_effect = [b'[1660.593076 HC 0x103]']
-    self.itpr.HandleECData()
-
-    # Verify that interrogating flag is cleared and enhanced_ec is still False.
-    self.assertFalse(self.itpr.interrogating, 'interrogating should be False.')
-    self.assertFalse(self.itpr.enhanced_ec,
-                     'enhanced_ec should still be False.')
-
-
-class TestUARTDisconnection(unittest.TestCase):
-  """Test case to verify interpreter disconnection/reconnection."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-    # First, check that interpreter is initialized to connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          ' initialized in a connected state'))
-
-  def test_DisconnectStopsECTraffic(self):
-    """Verify that when in disconnected state, no debug prints are sent."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs.  The
-    # interpreter will never pull data from the EC if it's not a member of the
-    # inputs list.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-
-  def test_CommandsDroppedWhenDisconnected(self):
-    """Verify that when in disconnected state, commands are dropped."""
-    # Send a command, followed by 'disconnect'.
-    self.cmd_pipe_user.send(b'taskinfo')
-    self.itpr.HandleUserData()
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Have the user send a few more commands in the disconnected state.
-    command = 'help\n'
-    for char in command:
-      self.cmd_pipe_user.send(char.encode('utf-8'))
-      self.itpr.HandleUserData()
-
-    # The command queue should be empty.
-    self.assertEqual(0, self.itpr.ec_cmd_queue.qsize())
-
-    # Now send the reconnect command.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected)
-    # Verify that EC UART is a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since no command was sent after reconnection, verify that the EC UART is
-    # not a member of the outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-  def test_ReconnectAllowsECTraffic(self):
-    """Verify that when connected, EC UART traffic is allowed."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Issue reconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          'connected.'))
-    # Verify that the EC UART is now a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since we have issued no commands during the disconnected state, no
-    # commands are pending and therefore the PTY should not be added to the
-    # outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-
-if __name__ == '__main__':
-  unittest.main()
diff --git a/util/ec3po/run_tests.sh b/util/ec3po/run_tests.sh
deleted file mode 100755
index ba513abe30..0000000000
--- a/util/ec3po/run_tests.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set -e
-
-my_dir="$(realpath -e -- "$(dirname -- "$0")")"
-parent_dir="$(realpath -e -- "$my_dir/..")"
-
-PYTHONPATH="$parent_dir" python3 -s -m unittest \
-    ec3po.console_unittest \
-    ec3po.interpreter_unittest \
-    && touch -- "$my_dir/.tests-passed"
diff --git a/util/ec3po/threadproc_shim.py b/util/ec3po/threadproc_shim.py
deleted file mode 100644
index da5440b1f3..0000000000
--- a/util/ec3po/threadproc_shim.py
+++ /dev/null
@@ -1,66 +0,0 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""This is a shim library for the ec3po transition from subprocesses to threads.
-
-This is necessary because ec3po is split between the platform/ec/ and
-third_party/hdctools/ repositories, so the transition cannot happen atomically
-in one change.  See http://b/79684405 #39.
-
-This contains only the multiprocessing objects or threading-oriented equivalents
-that are actually in use by ec3po.  There is no need for further functionality,
-because this shim will be deleted after the migration is complete.
-
-TODO(b/79684405): Stop using multiprocessing.Pipe.  The
-multiprocessing.Connection objects it returns serialize and deserialize objects
-(via Python pickling), which is necessary for sending them between processes,
-but is unnecessary overhead between threads.  This will not be a simple change,
-because the ec3po Console and Interpreter classes use the underlying pipe/socket
-pairs with select/poll/epoll alongside other file descriptors.  A drop-in
-replacement would be non-trivial and add undesirable complexity.  The correct
-solution will be to split off the polling of the pipes/queues from this module
-into separate threads, so that they can be transitioned to another form of
-cross-thread synchronization, e.g. directly waiting on queue.Queue.get() or a
-lower-level thread synchronization primitive.
-
-TODO(b/79684405): After this library has been updated to contain
-threading-oriented equivalents to its original multiprocessing implementations,
-and some reasonable amount of time has elapsed for thread-based ec3po problems
-to be discovered, migrate both the platform/ec/ and third_party/hdctools/ sides
-of ec3po off of this shim and then delete this file.  IMPORTANT: This should
-wait until after completing the TODO above to stop using multiprocessing.Pipe!
-"""
-
-# Imports to bring objects into this namespace for users of this module.
-from multiprocessing import Pipe
-from six.moves.queue import Queue
-from threading import Thread as ThreadOrProcess
-
-# True if this module has ec3po using subprocesses, False if using threads.
-USING_SUBPROCS = False
-
-
-def _DoNothing():
-  """Do-nothing function for use as a callback with DoIf()."""
-
-
-def DoIf(subprocs=_DoNothing, threads=_DoNothing):
-  """Return a callback or not based on ec3po use of subprocesses or threads.
-
-  Args:
-    subprocs: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using subprocesses.  This is
-        OPTIONAL, the default value is a do-nothing callback that returns None.
-    threads: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using threads.  This is OPTIONAL,
-        the default value is a do-nothing callback that returns None.
-
-  Returns:
-    Either the subprocs or threads argument will be returned.
-  """
-  return subprocs if USING_SUBPROCS else threads
-
-
-def Value(ctype, *args):
-  return ctype(*args)
diff --git a/util/ec_flash.c b/util/ec_flash.c
deleted file mode 100644
index ffa4eca4b7..0000000000
--- a/util/ec_flash.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "comm-host.h"
-#include "misc_util.h"
-#include "timer.h"
-
-static const uint32_t ERASE_ASYNC_TIMEOUT = 10 * SECOND;
-static const uint32_t ERASE_ASYNC_WAIT = 500 * MSEC;
-static const int FLASH_ERASE_BUSY_RV = -EECRESULT - EC_RES_BUSY;
-
-int ec_flash_read(uint8_t *buf, int offset, int size)
-{
-	struct ec_params_flash_read p;
-	int rv;
-	int i;
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += ec_max_insize) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, ec_max_insize);
-		rv = ec_command(EC_CMD_FLASH_READ, 0,
-				&p, sizeof(p), ec_inbuf, p.size);
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			return rv;
-		}
-		memcpy(buf + i, ec_inbuf, p.size);
-	}
-
-	return 0;
-}
-
-int ec_flash_verify(const uint8_t *buf, int offset, int size)
-{
-	uint8_t *rbuf = (uint8_t *)(malloc(size));
-	int rv;
-	int i;
-
-	if (!rbuf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	rv = ec_flash_read(rbuf, offset, size);
-	if (rv < 0) {
-		free(rbuf);
-		return rv;
-	}
-
-	for (i = 0; i < size; i++) {
-		if (buf[i] != rbuf[i]) {
-			fprintf(stderr, "Mismatch at offset 0x%x: "
-				"want 0x%02x, got 0x%02x\n",
-				i, buf[i], rbuf[i]);
-			free(rbuf);
-			return -1;
-		}
-	}
-
-	free(rbuf);
-	return 0;
-}
-
-/**
- * @param info_response  pointer to response that will be filled on success
- * @return Zero or positive on success, negative on failure
- */
-static int get_flash_info_v2(struct ec_response_flash_info_2 *info_response)
-{
-	struct ec_params_flash_info_2 info_params = {
-		/*
-		 * By setting this to zero we indicate that we don't care
-		 * about getting the bank description in the response.
-		 */
-		.num_banks_desc = 0
-	};
-
-	return ec_command(EC_CMD_FLASH_INFO, 2, &info_params,
-			  sizeof(info_params), info_response,
-			  sizeof(*info_response));
-}
-
-/**
- * @param info_response  pointer to response that will be filled on success
- * @return Zero or positive on success, negative on failure
- */
-static int get_flash_info_v0(struct ec_response_flash_info *info_response)
-{
-	return ec_command(EC_CMD_FLASH_INFO, 0, NULL, 0, info_response,
-			  sizeof(*info_response));
-}
-
-/**
- * @return Write size on success, negative on failure
- */
-static int get_flash_write_size(void)
-{
-	int rv = 0;
-	int write_size;
-	int flash_info_version = -1;
-	struct ec_response_flash_info info_response_v0 = { 0 };
-	struct ec_response_flash_info_2 info_response_v2 = { 0 };
-
-	if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 2))
-		flash_info_version = 2;
-	else if (ec_cmd_version_supported(EC_CMD_FLASH_INFO, 0))
-		flash_info_version = 0;
-
-	if (flash_info_version < 0)
-		return -1;
-
-	if (flash_info_version == 2) {
-		rv = get_flash_info_v2(&info_response_v2);
-		write_size = info_response_v2.write_ideal_size;
-	} else {
-		rv = get_flash_info_v0(&info_response_v0);
-		write_size = info_response_v0.write_block_size;
-	}
-
-	if (rv < 0)
-		return rv;
-
-	return write_size;
-}
-
-int ec_flash_write(const uint8_t *buf, int offset, int size)
-{
-	struct ec_params_flash_write *p =
-		(struct ec_params_flash_write *)ec_outbuf;
-	int write_size;
-	int pdata_max_size = (int)(ec_max_outsize - sizeof(*p));
-	int step;
-	int rv;
-	int i;
-
-	/*
-	 * Determine whether we can use version 1 of the EC_CMD_FLASH_WRITE
-	 * command with more data, or only version 0.
-	 */
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE))
-		pdata_max_size = EC_FLASH_WRITE_VER0_SIZE;
-
-	write_size = get_flash_write_size();
-	if (write_size < 0)
-		return write_size;
-
-	/*
-	 * shouldn't ever happen, but report an error rather than a division
-	 * by zero in the next statement.
-	 */
-	if (write_size == 0)
-		return -1;
-
-	step = (pdata_max_size / write_size) * write_size;
-
-	if (!step) {
-		fprintf(stderr, "Write block size %d > max param size %d\n",
-			write_size, pdata_max_size);
-		return -1;
-	}
-
-	/* Write data in chunks */
-	printf("Write size %d...\n", step);
-
-	for (i = 0; i < size; i += step) {
-		p->offset = offset + i;
-		p->size = MIN(size - i, step);
-		memcpy(p + 1, buf + i, p->size);
-		rv = ec_command(EC_CMD_FLASH_WRITE, 0, p, sizeof(*p) + p->size,
-				NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "Write error at offset %d\n", i);
-			return rv;
-		}
-	}
-
-	return 0;
-}
-
-int ec_flash_erase(int offset, int size)
-{
-	struct ec_params_flash_erase p;
-
-	p.offset = offset;
-	p.size = size;
-
-	return ec_command(EC_CMD_FLASH_ERASE, 0, &p, sizeof(p), NULL, 0);
-}
-
-int ec_flash_erase_async(int offset, int size)
-{
-	struct ec_params_flash_erase_v1 p = { 0 };
-	uint32_t timeout = 0;
-	int rv = FLASH_ERASE_BUSY_RV;
-
-	p.cmd = FLASH_ERASE_SECTOR_ASYNC;
-	p.params.offset = offset;
-	p.params.size = size;
-
-	rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
-
-	if (rv < 0)
-		return rv;
-
-	rv = FLASH_ERASE_BUSY_RV;
-
-	while (rv < 0 && timeout < ERASE_ASYNC_TIMEOUT) {
-		/*
-		 * The erase is not complete until FLASH_ERASE_GET_RESULT
-		 * returns success. It's important that we retry even when the
-		 * underlying ioctl returns an error (not just
-		 * FLASH_ERASE_BUSY_RV).
-		 *
-		 * See https://crrev.com/c/511805 for details.
-		 */
-		usleep(ERASE_ASYNC_WAIT);
-		timeout += ERASE_ASYNC_WAIT;
-		p.cmd = FLASH_ERASE_GET_RESULT;
-		rv = ec_command(EC_CMD_FLASH_ERASE, 1, &p, sizeof(p), NULL, 0);
-	}
-	return rv;
-}
diff --git a/util/ec_flash.h b/util/ec_flash.h
deleted file mode 100644
index f4aea3b7a3..0000000000
--- a/util/ec_flash.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __UTIL_EC_FLASH_H
-#define __UTIL_EC_FLASH_H
-
-/**
- * Read EC flash memory
- *
- * @param buf		Destination buffer
- * @param offset	Offset in EC flash to read
- * @param size		Number of bytes to read
- *
- * @return 0 if success, negative if error.
- */
-int ec_flash_read(uint8_t *buf, int offset, int size);
-
-/**
- * Verify EC flash memory
- *
- * @param buf		Source buffer to verify against EC flash
- * @param offset	Offset in EC flash to check
- * @param size		Number of bytes to check
- *
- * @return 0 if success, negative if error.
- */
-int ec_flash_verify(const uint8_t *buf, int offset, int size);
-
-/**
- * Write EC flash memory
- *
- * @param buf		Source buffer
- * @param offset	Offset in EC flash to write
- * @param size		Number of bytes to write
- *
- * @return 0 if success, negative if error.
- */
-int ec_flash_write(const uint8_t *buf, int offset, int size);
-
-/**
- * Erase EC flash memory
- *
- * @param offset	Offset in EC flash to erase
- * @param size		Number of bytes to erase
- *
- * @return 0 if success, negative if error.
- */
-int ec_flash_erase(int offset, int size);
-
-/**
- * Erase EC flash memory asynchronously
- *
- * @param offset	Offset in EC flash to erase
- * @param size		Number of bytes to erase
- *
- * @return 0 if success, negative if error.
- */
-int ec_flash_erase_async(int offset, int size);
-
-#endif
diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c
deleted file mode 100644
index ad6867fdc9..0000000000
--- a/util/ec_panicinfo.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include "compile_time_macros.h"
-
-#include "ec_panicinfo.h"
-
-static void print_panic_reg(int regnum, const uint32_t *regs, int index)
-{
-	static const char * const regname[] = {
-		"r0 ", "r1 ", "r2 ", "r3 ", "r4 ",
-		"r5 ", "r6 ", "r7 ", "r8 ", "r9 ",
-		"r10", "r11", "r12", "sp ", "lr ",
-		"pc "};
-
-	printf("%s:", regname[regnum]);
-	if (regs)
-		printf("%08x", regs[index]);
-	else
-		printf("        ");
-	printf((regnum & 3) == 3 ? "\n" : " ");
-}
-
-static int parse_panic_info_cm(const struct panic_data *pdata)
-{
-	const uint32_t *lregs = pdata->cm.regs;
-	const uint32_t *sregs = NULL;
-	enum {
-		ORIG_UNKNOWN = 0,
-		ORIG_PROCESS,
-		ORIG_HANDLER
-	} origin = ORIG_UNKNOWN;
-	int i;
-	const char *panic_origins[3] = {"", "PROCESS", "HANDLER"};
-
-	printf("Saved panic data:%s\n",
-	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
-
-	if (pdata->struct_version == 2)
-		origin = ((lregs[11] & 0xf) == 1 || (lregs[11] & 0xf) == 9) ?
-			 ORIG_HANDLER : ORIG_PROCESS;
-
-	/*
-	 * In pdata struct, 'regs', which is allocated before 'frame', has
-	 * one less elements in version 1. Therefore, if the data is from
-	 * version 1, shift 'sregs' by one element to align with 'frame' in
-	 * version 1.
-	 */
-	if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
-		sregs = pdata->cm.frame - (pdata->struct_version == 1 ? 1 : 0);
-
-	printf("=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
-	       panic_origins[origin],
-	       lregs[1] & 0xff, sregs ? sregs[7] : -1);
-	for (i = 0; i < 4; ++i)
-		print_panic_reg(i, sregs, i);
-	for (i = 4; i < 10; ++i)
-		print_panic_reg(i, lregs, i - 1);
-	print_panic_reg(10, lregs, 9);
-	print_panic_reg(11, lregs, 10);
-	print_panic_reg(12, sregs, 4);
-	print_panic_reg(13, lregs, origin == ORIG_HANDLER ? 2 : 0);
-	print_panic_reg(14, sregs, 5);
-	print_panic_reg(15, sregs, 6);
-
-	return 0;
-}
-
-static int parse_panic_info_nds32(const struct panic_data *pdata)
-{
-	const uint32_t *regs = pdata->nds_n8.regs;
-	uint32_t itype = pdata->nds_n8.itype;
-	uint32_t ipc = pdata->nds_n8.ipc;
-	uint32_t ipsw = pdata->nds_n8.ipsw;
-
-	printf("Saved panic data:%s\n",
-	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
-
-	printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
-	printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff));
-
-	return 0;
-}
-
-static int parse_panic_info_rv32i(const struct panic_data *pdata)
-{
-	uint32_t *regs, mcause, mepc;
-
-	regs = (uint32_t *)pdata->riscv.regs;
-	mcause = pdata->riscv.mcause;
-	mepc = pdata->riscv.mepc;
-
-	printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-	       regs[0], regs[1], regs[2], regs[3]);
-	printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-	       regs[4], regs[5], regs[6], regs[7]);
-	printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-	       regs[8], regs[9], regs[10], regs[11]);
-	printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-	       regs[12], regs[13], regs[14], regs[15]);
-	printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-	       regs[16], regs[17], regs[18], regs[19]);
-	printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-	       regs[20], regs[21], regs[22], regs[23]);
-	printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-	       regs[24], regs[25], regs[26], regs[27]);
-	printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-	       regs[28], regs[29], regs[30], mepc);
-
-	return 0;
-}
-
-int parse_panic_info(const char *data, size_t size)
-{
-	/* Size of the panic information "header". */
-	const size_t header_size = 4;
-	/* Size of the panic information "trailer" (struct_size and magic). */
-	const size_t trailer_size = sizeof(struct panic_data) -
-				 offsetof(struct panic_data, struct_size);
-
-	struct panic_data pdata = { 0 };
-	size_t copy_size;
-
-	if (size < (header_size + trailer_size)) {
-		fprintf(stderr, "ERROR: Panic data too short (%zd).\n", size);
-		return -1;
-	}
-
-	if (size > sizeof(pdata)) {
-		fprintf(stderr, "WARNING: Panic data too large (%zd > %zd). "
-			"Following data may be incorrect!\n",
-			size, sizeof(pdata));
-		copy_size = sizeof(pdata);
-	} else {
-		copy_size = size;
-	}
-	/* Copy the data into pdata, as the struct size may have changed. */
-	memcpy(&pdata, data, copy_size);
-	/* Then copy the trailer in position. */
-	memcpy((char *)&pdata + (sizeof(struct panic_data) - trailer_size),
-		data + (size - trailer_size), trailer_size);
-
-	/*
-	 * We only understand panic data with version <= 2. Warn the user
-	 * of higher versions.
-	 */
-	if (pdata.struct_version > 2)
-		fprintf(stderr, "WARNING: Unknown panic data version (%d). "
-			"Following data may be incorrect!\n",
-			pdata.struct_version);
-
-	/* Validate magic number */
-	if (pdata.magic != PANIC_DATA_MAGIC)
-		fprintf(stderr, "WARNING: Incorrect panic magic (%d). "
-			"Following data may be incorrect!\n",
-			pdata.magic);
-
-	if (pdata.struct_size != size)
-		fprintf(stderr,
-			"WARNING: Panic struct size inconsistent (%u vs %zd). "
-			"Following data may be incorrect!\n",
-			pdata.struct_size, size);
-
-	switch (pdata.arch) {
-	case PANIC_ARCH_CORTEX_M:
-		return parse_panic_info_cm(&pdata);
-	case PANIC_ARCH_NDS32_N8:
-		return parse_panic_info_nds32(&pdata);
-	case PANIC_ARCH_RISCV_RV32I:
-		return parse_panic_info_rv32i(&pdata);
-	default:
-		fprintf(stderr, "ERROR: Unknown architecture (%d).\n",
-			pdata.arch);
-		break;
-	}
-	return -1;
-}
diff --git a/util/ec_panicinfo.h b/util/ec_panicinfo.h
deleted file mode 100644
index c61cf797e6..0000000000
--- a/util/ec_panicinfo.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef EC_PANICINFO_H
-#define EC_PANICINFO_H
-
-#include "panic.h"
-
-/**
- * Prints panic information to stdout.
- *
- * @param pdata  Panic information to print
- * @return 0 if success or non-zero error code if error.
- */
-int parse_panic_info(const char *data, size_t size);
-
-#endif /* EC_PANICINFO_H */
diff --git a/util/ec_parse_panicinfo.c b/util/ec_parse_panicinfo.c
deleted file mode 100644
index 3a2da4590a..0000000000
--- a/util/ec_parse_panicinfo.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Standalone utility to parse EC panicinfo.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "compile_time_macros.h"
-#include "ec_panicinfo.h"
-
-int main(int argc, char *argv[])
-{
-	/*
-	 * panic_data size could change with time, as new architecture are
-	 * added (or, less likely, removed).
-	 */
-	char pdata[4096];
-	size_t size = 0;
-	size_t read;
-
-	BUILD_ASSERT(sizeof(pdata) > sizeof(struct panic_data)*2);
-
-	/*
-	 * Provide a minimal help message.
-	 */
-	if (argc > 1) {
-		printf("Usage: cat <PANIC_BLOB_PATH> | ec_parse_panicinfo\n");
-		printf("Print the plain text panic info from a raw EC panic "
-		       "data blob.\n\n");
-		printf("Example:\n");
-		printf("ec_parse_panicinfo "
-		       "</sys/kernel/debug/cros_ec/panicinfo\n");
-		return 1;
-	}
-
-	while (1) {
-		read = fread(&pdata[size], 1, sizeof(pdata)-size, stdin);
-		if (read < 0) {
-			fprintf(stderr, "Cannot read panicinfo from stdin.\n");
-			return 1;
-		}
-		if (read == 0)
-			break;
-
-		size += read;
-		if (size == sizeof(pdata)) {
-			fprintf(stderr, "Too much panicinfo data in stdin.\n");
-			return 1;
-		}
-	}
-
-	return parse_panic_info(pdata, size) ? 1 : 0;
-}
diff --git a/util/ec_sb_firmware_update.c b/util/ec_sb_firmware_update.c
deleted file mode 100644
index a959cd6fe9..0000000000
--- a/util/ec_sb_firmware_update.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "comm-host.h"
-#include "compile_time_macros.h"
-#include "ec_sb_firmware_update.h"
-#include "ec_commands.h"
-#include "lock/gec_lock.h"
-#include "misc_util.h"
-#include "powerd_lock.h"
-
-/* Subcommands: [check|update] */
-enum {
-	OP_UNKNOWN = 0,
-	OP_CHECK   = 1,
-	OP_UPDATE  = 2,
-};
-
-struct delay_value {
-	uint32_t steps;
-	uint32_t value;
-};
-
-/* Default retry counter on errors */
-#define SB_FW_UPDATE_DEFAULT_RETRY_CNT 3
-/* Default delay value */
-#define SB_FW_UPDATE_DEFAULT_DELAY  1000
-
-#define DELAY_US_BEGIN  500000
-#define DELAY_US_END   1000000
-#define DELAY_US_BUSY  1000000
-#define DELAY_US_WRITE_END  50000
-
-static struct delay_value sb_delays[] = {
-	{1,             100000},
-	{2,            9000000},
-	{4,             100000},
-	{771,            30000},
-	{2200,           10000},
-	{0xFFFFFF,       50000},
-};
-
-enum fw_update_state {
-	S0_READ_STATUS   = 0,
-	S1_READ_INFO     = 1,
-	S2_WRITE_PREPARE = 2,
-	S3_READ_STATUS   = 3,
-	S4_WRITE_UPDATE  = 4,
-	S5_READ_STATUS   = 5,
-	S6_WRITE_BLOCK   = 6,
-	S7_READ_STATUS   = 7,
-	S8_WRITE_END     = 8,
-	S9_READ_STATUS   = 9,
-	S10_TERMINAL     = 10
-};
-
-#define MAX_FW_IMAGE_NAME_SIZE 80
-
-/* Firmware Update Control Flags */
-enum {
-	F_AC_PRESENT    = 0x1, /* AC Present */
-	F_VERSION_CHECK = 0x2, /* do firmware version check */
-	F_UPDATE        = 0x4, /* do firmware update */
-	F_NEED_UPDATE   = 0x8,  /* need firmware update */
-	F_POWERD_DISABLED = 0x10,  /* powerd is disabled */
-	F_LFCC_ZERO =       0x20,  /* last full charge is zero */
-	F_BATT_DISCHARGE =  0x40   /* battery discharging */
-};
-
-struct fw_update_ctrl {
-	uint32_t flags; /* fw update control flags */
-	int size;    /* size of battery firmware image */
-	char *ptr;   /* current read pointer of the firmware image */
-	int  offset; /* current block write offset */
-	struct sb_fw_header *fw_img_hdr; /*pointer to firmware image header*/
-	struct sb_fw_update_status status;
-	struct sb_fw_update_info info;
-	int err_retry_cnt;
-	int fec_err_retry_cnt;
-	int busy_retry_cnt;
-	int step_size;
-	int rv;
-	char image_name[MAX_FW_IMAGE_NAME_SIZE];
-	char msg[256];
-};
-
-/*
- * Global Firmware Update Control Data Structure
- */
-static struct fw_update_ctrl fw_update;
-
-static uint32_t get_delay_value(uint32_t offset, uint32_t step_size)
-{
-	int sz = ARRAY_SIZE(sb_delays);
-	int i;
-	for (i = 0; i < sz; i++) {
-		if (offset <= sb_delays[i].steps * step_size)
-			return sb_delays[i].value;
-	}
-	return sb_delays[sz-1].value;
-}
-
-static void print_battery_firmware_image_hdr(
-	struct sb_fw_header *hdr)
-{
-	printf("Latest Battery Firmware:\n");
-	printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n",
-		hdr->signature[0],
-		hdr->signature[1],
-		hdr->signature[2],
-		hdr->signature[3],
-		hdr->hdr_version, hdr->pkg_version_major_minor);
-
-	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		hdr->vendor_id, hdr->battery_type, hdr->fw_version,
-		hdr->data_table_version);
-
-	printf("\tbinary offset:0x%08x size:0x%08x chk_sum:0x%02x\n",
-		hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum);
-}
-
-static void print_info(struct sb_fw_update_info *info)
-{
-	printf("\nCurrent Battery Firmware:\n");
-	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		info->maker_id,
-		info->hardware_id,
-		info->fw_version,
-		info->data_version);
-	return;
-}
-
-static void print_status(struct sb_fw_update_status *sts)
-{
-	printf("f_maker_id:%d f_hw_id:%d f_fw_ver:%d f_permnent:%d\n",
-		sts->v_fail_maker_id,
-		sts->v_fail_hw_id,
-		sts->v_fail_fw_version,
-		sts->v_fail_permanent);
-	printf("permanent failure:%d abnormal:%d fw_update:%d\n",
-		sts->permanent_failure,
-		sts->abnormal_condition,
-		sts->fw_update_supported);
-	printf("fw_update_mode:%d fw_corrupted:%d cmd_reject:%d\n",
-		sts->fw_update_mode,
-		sts->fw_corrupted,
-		sts->cmd_reject);
-	printf("invliad data:%d fw_fatal_err:%d fec_err:%d busy:%d\n",
-		sts->invalid_data,
-		sts->fw_fatal_error,
-		sts->fec_error,
-		sts->busy);
-	printf("\n");
-	return;
-}
-
-/* @return 1 (True) if img signature is valid */
-static int check_battery_firmware_image_signature(
-	struct sb_fw_header *hdr)
-{
-	return (hdr->signature[0] == 'B') &&
-		(hdr->signature[1] == 'T') &&
-		(hdr->signature[2] == 'F') &&
-		(hdr->signature[3] == 'W');
-}
-
-/* @return 1 (True) if img checksum is valid. */
-static int check_battery_firmware_image_checksum(
-	struct sb_fw_header *hdr)
-{
-	int i;
-	uint8_t sum = 0;
-	uint8_t *img = (uint8_t *)hdr;
-
-	img += hdr->fw_binary_offset;
-	for (i = 0; i < hdr->fw_binary_size; i++)
-		sum += img[i];
-	sum += hdr->checksum;
-	return sum == 0;
-}
-
-/* @return 1 (True) if img versions are ok to update. */
-static int check_battery_firmware_image_version(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
-{
-	/*
-	 * If the battery firmware has a newer fw version
-	 * or a newer data table version, then it is ok to update.
-	 */
-	return (hdr->fw_version > p->fw_version)
-		|| (hdr->data_table_version > p->data_version);
-}
-
-
-static int check_battery_firmware_ids(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
-{
-	return ((hdr->vendor_id == p->maker_id) &&
-		(hdr->battery_type == p->hardware_id));
-}
-
-/* check_if_need_update_fw
- * @return 1 (true) if need; 0 (false) if not.
- */
-static int check_if_valid_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
-{
-	return check_battery_firmware_image_signature(hdr)
-		&& check_battery_firmware_ids(hdr, info)
-		&& check_battery_firmware_image_checksum(hdr);
-}
-
-/* check_if_need_update_fw
- * @return 1 (true) if need; 0 (false) if not.
- */
-static int check_if_need_update_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
-{
-	return check_battery_firmware_image_version(hdr, info);
-}
-
-static void log_msg(struct fw_update_ctrl *fw_update,
-			enum fw_update_state state, const char *msg)
-{
-	sprintf(fw_update->msg,
-		"Battery Firmware Updater State:%d %s", state, msg);
-}
-
-
-static char *read_fw_image(struct fw_update_ctrl *fw_update)
-{
-	int size;
-	char *buf;
-	fw_update->size = 0;
-	fw_update->ptr = NULL;
-	fw_update->fw_img_hdr = (struct sb_fw_header *)NULL;
-
-	/* Read the input file */
-	buf = read_file(fw_update->image_name, &size);
-	if (!buf)
-		return NULL;
-
-	fw_update->size = size;
-	fw_update->ptr = buf;
-	fw_update->fw_img_hdr = (struct sb_fw_header *)buf;
-	print_battery_firmware_image_hdr(fw_update->fw_img_hdr);
-
-	if (fw_update->fw_img_hdr->fw_binary_offset >= fw_update->size ||
-		fw_update->size < 256) {
-		printf("Load Firmware Image[%s] Error offset:%d size:%d\n",
-			fw_update->image_name,
-			fw_update->fw_img_hdr->fw_binary_offset,
-			fw_update->size);
-		free(buf);
-		return NULL;
-	}
-	return buf;
-}
-
-static int get_status(struct sb_fw_update_status *status)
-{
-	int rv = EC_RES_SUCCESS;
-	int cnt = 0;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	struct ec_response_sb_fw_update *resp =
-		(struct ec_response_sb_fw_update *)ec_inbuf;
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_STATUS;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_STATUS_SIZE);
-	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (rv < 0) {
-		memset(status, 0, SB_FW_UPDATE_CMD_STATUS_SIZE);
-		return -EC_RES_ERROR;
-	}
-
-	memcpy(status, resp->status.data, SB_FW_UPDATE_CMD_STATUS_SIZE);
-	return EC_RES_SUCCESS;
-}
-
-static int get_info(struct sb_fw_update_info *info)
-{
-	int rv = EC_RES_SUCCESS;
-	int cnt = 0;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	struct ec_response_sb_fw_update *resp =
-		(struct ec_response_sb_fw_update *)ec_inbuf;
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_INFO;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_INFO_SIZE);
-	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (rv < 0) {
-		memset(info, 0, SB_FW_UPDATE_CMD_INFO_SIZE);
-		return -EC_RES_ERROR;
-	}
-
-	memcpy(info, resp->info.data, SB_FW_UPDATE_CMD_INFO_SIZE);
-	return EC_RES_SUCCESS;
-}
-
-static int send_subcmd(int subcmd)
-{
-	int rv = EC_RES_SUCCESS;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	param->hdr.subcmd = subcmd;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_sb_fw_update_header), NULL, 0);
-	if (rv < 0) {
-		printf("Firmware Update subcmd:%d Error\n", subcmd);
-		return -EC_RES_ERROR;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static int write_block(struct fw_update_ctrl *fw_update,
-			int offset, int bsize)
-{
-	int rv;
-
-	struct ec_params_sb_fw_update *param =
-		(struct ec_params_sb_fw_update *)ec_outbuf;
-
-	memcpy(param->write.data, fw_update->ptr+offset, bsize);
-
-	param->hdr.subcmd = EC_SB_FW_UPDATE_WRITE;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_params_sb_fw_update), NULL, 0);
-	if (rv < 0) {
-		printf("Firmware Update Write Error ptr:%p offset@%x\n",
-			fw_update->ptr, offset);
-		return -EC_RES_ERROR;
-	}
-	return EC_RES_SUCCESS;
-}
-
-static void dump_data(char *data, int offset, int size)
-{
-	int i = 0;
-
-	if (data == NULL)
-		return;
-
-	printf("Offset:0x%X\n", offset);
-	for (i = 0; i < size; i++) {
-		if ((i%16) == 0)
-			printf("\n");
-		printf("%02X ", data[i]);
-	}
-	printf("\n");
-}
-
-static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update)
-{
-	if (fw_update->busy_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S0_READ_STATUS, "Busy");
-		return S10_TERMINAL;
-	}
-
-	fw_update->busy_retry_cnt--;
-
-	fw_update->rv = get_status(&fw_update->status);
-	if (fw_update->rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S0_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	if (!((fw_update->status.abnormal_condition == 0)
-		&& (fw_update->status.fw_update_supported == 1))) {
-		return S0_READ_STATUS;
-	}
-
-	if (fw_update->status.busy) {
-		usleep(DELAY_US_BUSY);
-		return S0_READ_STATUS;
-	} else
-		return S1_READ_INFO;
-}
-
-static enum fw_update_state s1_read_battery_info(
-		struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	if (fw_update->err_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Retry Error");
-		return S10_TERMINAL;
-	}
-
-	fw_update->err_retry_cnt--;
-
-	rv = get_info(&fw_update->info);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-	print_info(&fw_update->info);
-
-	sprintf(fw_update->image_name,
-			"/lib/firmware/battery/maker.%04x.hwid.%04x.bin",
-			fw_update->info.maker_id,
-			fw_update->info.hardware_id);
-
-	if (NULL == read_fw_image(fw_update)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO, "Open Image File");
-		return S10_TERMINAL;
-	}
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	rv = check_if_valid_fw(fw_update->fw_img_hdr, &fw_update->info);
-	if (rv == 0) {
-		fw_update->rv = -EC_RES_INVALID_PARAM;
-		log_msg(fw_update, S1_READ_INFO, "Invalid Firmware");
-		return S10_TERMINAL;
-	}
-
-	rv = check_if_need_update_fw(fw_update->fw_img_hdr, &fw_update->info);
-	if (rv == 0 && (fw_update->flags & F_VERSION_CHECK)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO, "Latest Firmware");
-		return S10_TERMINAL;
-	}
-
-	fw_update->flags |= F_NEED_UPDATE;
-
-	if (!(fw_update->flags & F_UPDATE)) {
-		fw_update->rv = 0;
-		return S10_TERMINAL;
-	}
-
-	if (!(fw_update->flags & F_AC_PRESENT)) {
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO,
-			"Require AC Adapter Connected.");
-		return S10_TERMINAL;
-	}
-
-	if ((fw_update->flags & F_BATT_DISCHARGE) &&
-	    (fw_update->flags & F_AC_PRESENT)) {
-		/*
-		 * If battery discharge due to battery learning mode,
-		 * we can't update battery FW, because device will shutdown
-		 * during FW update.
-		 */
-		fw_update->rv = 0;
-		log_msg(fw_update, S1_READ_INFO,
-			"battery can't update in learning mode");
-		return S10_TERMINAL;
-	}
-
-	return S2_WRITE_PREPARE;
-}
-
-static enum fw_update_state s2_write_prepare(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = disable_power_management();
-	if (0 == rv)
-		fw_update->flags |= F_POWERD_DISABLED;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_PREPARE);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S2_WRITE_PREPARE, "Interface Error");
-		return S10_TERMINAL;
-	}
-	return S3_READ_STATUS;
-}
-
-static enum fw_update_state s3_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S3_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	return S4_WRITE_UPDATE;
-
-}
-
-static enum fw_update_state s4_write_update(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_BEGIN);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S4_WRITE_UPDATE, "Interface Error");
-		return S10_TERMINAL;
-	}
-	usleep(DELAY_US_BEGIN);
-	return S5_READ_STATUS;
-}
-
-static enum fw_update_state s5_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv = get_status(&fw_update->status);
-
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S5_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	if (fw_update->status.fw_update_mode == 0)
-		return S2_WRITE_PREPARE;
-
-	/* Init Write Block Loop Controls */
-	fw_update->ptr += fw_update->fw_img_hdr->fw_binary_offset;
-	fw_update->size -= fw_update->fw_img_hdr->fw_binary_offset;
-	fw_update->offset = 0;
-
-	return S6_WRITE_BLOCK;
-}
-
-static enum fw_update_state s6_write_block(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-	int bsize;
-	int offset = fw_update->offset;
-
-	if (offset >= fw_update->size)
-		return S8_WRITE_END;
-
-	bsize = fw_update->step_size;
-
-	if ((offset & 0xFFFF) == 0x0)
-		printf("\n%X\n", offset);
-
-	if (fw_update->fec_err_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S6_WRITE_BLOCK, "FEC Retry Error");
-		return S10_TERMINAL;
-	}
-	fw_update->fec_err_retry_cnt--;
-
-	rv = write_block(fw_update, offset, bsize);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S6_WRITE_BLOCK, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	/*
-	 * Add more delays after the last few (3) block writes.
-	 * 3 is chosen based on current test results.
-	 */
-	if ((offset + 3*fw_update->step_size) >= fw_update->size)
-		usleep(DELAY_US_WRITE_END);
-
-	usleep(get_delay_value(offset, fw_update->step_size));
-
-	return S7_READ_STATUS;
-}
-
-static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-	int offset = fw_update->offset;
-	int bsize;
-	int cnt = 0;
-
-	bsize = fw_update->step_size;
-	do {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = get_status(&fw_update->status);
-		if (rv) {
-			dump_data(fw_update->ptr+offset, offset, bsize);
-			print_status(&fw_update->status);
-			fw_update->rv = -1;
-			log_msg(fw_update, S7_READ_STATUS, "Interface Error");
-			return S10_TERMINAL;
-		}
-	} while (fw_update->status.busy &&
-			(cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
-
-	if (fw_update->status.fec_error) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = 0;
-		return S6_WRITE_BLOCK;
-	}
-	if (fw_update->status.permanent_failure ||
-		fw_update->status.v_fail_permanent) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = -1;
-		log_msg(fw_update, S7_READ_STATUS, "Battery Permanent Error");
-		return S8_WRITE_END;
-	}
-	if (fw_update->status.v_fail_maker_id ||
-		fw_update->status.v_fail_hw_id ||
-		fw_update->status.v_fail_fw_version ||
-		fw_update->status.fw_corrupted ||
-		fw_update->status.cmd_reject ||
-		fw_update->status.invalid_data ||
-		fw_update->status.fw_fatal_error) {
-
-		dump_data(fw_update->ptr+offset, offset, bsize);
-		print_status(&fw_update->status);
-		fw_update->rv = 0;
-		return S1_READ_INFO;
-	}
-
-	fw_update->fec_err_retry_cnt = SB_FW_UPDATE_FEC_ERROR_RETRY_CNT;
-	fw_update->offset += fw_update->step_size;
-	return S6_WRITE_BLOCK;
-}
-
-
-static enum fw_update_state s8_write_end(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	rv = send_subcmd(EC_SB_FW_UPDATE_END);
-	if (rv && (0 == fw_update->rv)) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S8_WRITE_END, "Interface Error");
-	}
-
-	if (fw_update->rv)
-		return S10_TERMINAL;
-
-	usleep(DELAY_US_END);
-	fw_update->busy_retry_cnt = SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT;
-	return S9_READ_STATUS;
-}
-
-static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update)
-{
-	int rv;
-
-	if (fw_update->busy_retry_cnt == 0) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S9_READ_STATUS, "Busy");
-		return S10_TERMINAL;
-	}
-
-	rv = get_status(&fw_update->status);
-	if (rv) {
-		fw_update->rv = -1;
-		log_msg(fw_update, S9_READ_STATUS, "Interface Error");
-		return S10_TERMINAL;
-	}
-	if ((fw_update->status.fw_update_mode == 1)
-		|| (fw_update->status.busy == 1)) {
-		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		fw_update->busy_retry_cnt--;
-		return S9_READ_STATUS;
-	}
-	log_msg(fw_update, S9_READ_STATUS, "Complete");
-	fw_update->flags &= ~F_NEED_UPDATE;
-	return S10_TERMINAL;
-}
-
-
-typedef enum fw_update_state (*fw_state_func)(struct fw_update_ctrl *fw_update);
-
-fw_state_func state_table[] = {
-	s0_read_status,
-	s1_read_battery_info,
-	s2_write_prepare,
-	s3_read_status,
-	s4_write_update,
-	s5_read_status,
-	s6_write_block,
-	s7_read_status,
-	s8_write_end,
-	s9_read_status
-};
-
-
-/**
- * Update Smart Battery Firmware
- *
- * @param fw_update struct fw_update_ctrl
- *
- * @return 0 if success, negative if error.
- */
-static int ec_sb_firmware_update(struct fw_update_ctrl *fw_update)
-{
-	enum fw_update_state state;
-
-	fw_update->err_retry_cnt = SB_FW_UPDATE_ERROR_RETRY_CNT;
-	fw_update->fec_err_retry_cnt = SB_FW_UPDATE_FEC_ERROR_RETRY_CNT;
-	fw_update->busy_retry_cnt = SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT;
-	fw_update->step_size = SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE;
-
-	state = S0_READ_STATUS;
-	while (state != S10_TERMINAL)
-		state = state_table[state](fw_update);
-
-	if (fw_update->fw_img_hdr)
-		free(fw_update->fw_img_hdr);
-
-	return fw_update->rv;
-}
-
-#define GEC_LOCK_TIMEOUT_SECS   30  /* 30 secs */
-void usage(char *argv[])
-{
-	printf("Usage: %s [check|update]\n"
-		"	check: check if AC Adaptor is connected.\n"
-		"	update: trigger battery firmware update.\n",
-		argv[0]);
-}
-
-int main(int argc, char *argv[])
-{
-	int rv = 0;
-	int op = OP_UNKNOWN;
-	uint8_t val = 0;
-
-	if (argc != 2) {
-		usage(argv);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "check"))
-		op = OP_CHECK;
-	else if (!strcmp(argv[1], "update"))
-		op = OP_UPDATE;
-	else {
-		op = OP_UNKNOWN;
-		usage(argv);
-		return -1;
-	}
-
-	if (comm_init_dev(NULL)) {
-		printf("Couldn't initialize /dev.\n");
-		return -1;
-	}
-
-	if (comm_init_buffer()) {
-		fprintf(stderr, "Couldn't initialize buffers\n");
-		return -1;
-	}
-
-	fw_update.flags = 0;
-	rv = ec_readmem(EC_MEMMAP_BATT_FLAG, sizeof(val), &val);
-	if (rv <= 0) {
-		printf("EC Memmap read error:%d\n", rv);
-		goto out;
-	}
-
-	rv = get_status(&fw_update.status);
-	if (rv) {
-		fw_update.rv = -1;
-		log_msg(&fw_update, S1_READ_INFO, "Interface Error");
-		return S10_TERMINAL;
-	}
-
-	if (fw_update.status.fw_update_mode) {
-		/*
-		 * Previous battery firmware update was interrupted,
-		 * and we may not detect the presence of AC correctly.
-		 * Therefore, lie about our AC status.
-		 */
-		fw_update.flags |= F_AC_PRESENT;
-		printf("Assuming AC_PRESENT due to interrupted FW update\n");
-	} else {
-		if (val & EC_BATT_FLAG_AC_PRESENT) {
-			fw_update.flags |= F_AC_PRESENT;
-			printf("AC_PRESENT\n");
-		}
-	}
-
-	if (val & EC_BATT_FLAG_DISCHARGING) {
-		fw_update.flags |= F_BATT_DISCHARGE;
-		printf("Battery is in discharge state\n");
-	}
-	rv = ec_readmem(EC_MEMMAP_BATT_LFCC, sizeof(val), &val);
-	if (rv <= 0) {
-		printf("EC Memmap read error:%d\n", rv);
-		goto out;
-	}
-	if (val == 0)
-		fw_update.flags |= F_LFCC_ZERO;
-
-	if (op == OP_UPDATE)
-		fw_update.flags |= F_UPDATE;
-
-	fw_update.flags |= F_VERSION_CHECK;
-
-	rv = ec_sb_firmware_update(&fw_update);
-	printf("Battery Firmware Update:0x%02x %s\n%s\n",
-			fw_update.flags,
-			((rv) ? "FAIL " : " "),
-			fw_update.msg);
-
-	/* Update battery firmware update interface to be protected */
-	if (!(fw_update.flags & F_NEED_UPDATE))
-		rv |= send_subcmd(EC_SB_FW_UPDATE_PROTECT);
-
-	if (fw_update.flags & F_POWERD_DISABLED)
-		rv |= restore_power_management();
-out:
-	if (rv)
-		return -1;
-	else
-		return fw_update.flags & (F_LFCC_ZERO | F_NEED_UPDATE);
-}
diff --git a/util/ec_sb_firmware_update.h b/util/ec_sb_firmware_update.h
deleted file mode 100644
index 5bddebaf4a..0000000000
--- a/util/ec_sb_firmware_update.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Smart battery Firmware Update driver.
- * Ref: Common Smart Battery System Interface Specification v8.0.
- *
- * cmd.0x35, Write Word
- *   0x1000: Prepare to Update
- *   0x2000: End of Update
- *   0xF000: Update Firmware
- *
- * cmd.0x35, Read Word
- *   Firmware Update Status
- *
- * cmd.0x36 Write Block
- *   Send 32 byte firmware image
- *
- * cmd.0x37 Read Word
- *   Get Battery Information
- *   sequence:=b1,b0,b3,b2,b5,b5,b7,b6
- *
- * Command Sequence for Battery FW Update
- *
- *  0. cmd.0x35.read
- *  1. cmd.0x37.read
- *  2. cmd.0x35.write.0x1000
- *  3. cmd.0x35.read.status (optional)
- *  4. cmd.0x35.write.0xF000
- *  5. cmd.0x35.read.status
- *     if bit8-0, go to step 2
- *  6. cmd.0x36.write.32byte
- *  7. cmd.0x35.read.status
- *     if FEC.b13=1, go to step 6
- *     if fatal.b12=1, go to step 2
- *     if b11,b10,b9,b2,b1,b0; go to step 1
- *     if b5,b3; go to step 8
- *    (repeat 6,7)
- *  8. cmd.0x36.write.0x2000
- *  9. cmd.0x35.read.status
- */
-
-#ifndef __UTIL_EC_SB_FIRMWARE_UPDATE_H
-#define __UTIL_EC_SB_FIRMWARE_UPDATE_H
-
-struct sb_fw_header {
-	uint8_t signature[4]; /* "BTFW" */
-	uint16_t hdr_version; /* 0x0100 */
-	uint16_t pkg_version_major_minor;
-
-	uint16_t vendor_id; /* 8,9 */
-	uint16_t battery_type; /* A B */
-
-	uint16_t fw_version; /* C D */
-	uint16_t data_table_version; /* E F */
-	uint32_t fw_binary_offset; /*0x10 0x11 0x12 0x13 */
-	uint32_t fw_binary_size; /* 0x14 0x15 0x16 0x17 */
-	uint8_t  checksum; /* 0x18 */
-};
-
-/**
- * sb.fw.update.cmd.0x35, Read Word
- *    Firmware Update Status
- */
-struct sb_fw_update_status {
-	uint16_t v_fail_maker_id:1; /* b0 */
-	uint16_t v_fail_hw_id:1; /* b1 */
-	uint16_t v_fail_fw_version:1; /* b2 */
-	uint16_t v_fail_permanent:1; /* b3 */
-
-	uint16_t rsvd5:1; /* b4 */
-	uint16_t permanent_failure:1; /* b5 */
-	uint16_t abnormal_condition:1; /* b6 */
-	uint16_t fw_update_supported:1; /* b7 */
-
-	uint16_t fw_update_mode:1; /* b8 */
-	uint16_t fw_corrupted:1; /* b9 */
-	uint16_t cmd_reject:1; /* b10 */
-	uint16_t invalid_data:1; /* b11 */
-
-	uint16_t fw_fatal_error:1; /* b12 */
-	uint16_t fec_error:1; /* b13 */
-	uint16_t busy:1; /* b14 */
-	uint16_t rsvd15:1; /* b15 */
-} __packed;
-
-/**
- * sb.fw.update.cmd.0x37 Read Word
- *     Get Battery Information
- *     sequence:=b1,b0,b3,b2,b5,b5,b7,b6
- */
-struct sb_fw_update_info {
-	uint16_t maker_id;    /* b0, b1 */
-	uint16_t hardware_id; /* b2, b3 */
-	uint16_t fw_version;  /* b4, b5 */
-	uint16_t data_version;/* b6, b7 */
-} __packed;
-
-/**
- * smart.battery.maker.id
- */
-enum sb_maker_id {
-	sb_maker_id_lgc       = 0x0001, /* b0=0; b1=1 */
-	sb_maker_id_panasonic = 0x0002,
-	sb_maker_id_sanyo     = 0x0003,
-	sb_maker_id_sony      = 0x0004,
-	sb_maker_id_simplo    = 0x0005,
-	sb_maker_id_celxpert  = 0x0006,
-};
-
-/*
- * Ref: Common Smart Battery System Interface Specification v8.0 page 21-24.
- * case 1. If permanent error:b5,b3, go to setp8.
- * case 2. If error:b11,b10,b9 b2,b1,b0, go to step1. Retry < 3 times.
- * case 3. If firmware update fatal error:b12, go to step2. Retry < 3 times.
- *         In order to simply the implementation, I merged case 2 and 3.
- *         If firmware update fatal error:b12, go to step1 as well.
- * case 4. If error.FEC.b13=1, go to step6. Retry < 3 times.
- * case 5. If battery interface is busy, retry < 10 times.
- *    Delay 1 second between retries.
- */
-#define SB_FW_UPDATE_ERROR_RETRY_CNT      2
-#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT  2
-#define SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT 4
-
-#endif
diff --git a/util/ecst.c b/util/ecst.c
deleted file mode 100644
index 95aee7b73d..0000000000
--- a/util/ecst.c
+++ /dev/null
@@ -1,2486 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This utility is used to generate/modify the firmware header which holds
- * data used by NPCX ROM code (booter).
- */
-
-#include "compile_time_macros.h"
-#include "ecst.h"
-
-/* Global Variables */
-enum verbose_level g_verbose;
-char input_file_name[NAME_SIZE];
-char output_file_name[NAME_SIZE];
-char arg_file_name[NAME_SIZE];
-char g_hdr_input_name[NAME_SIZE];
-char hdr_args[MAX_ARGS][ARG_SIZE];
-char tmp_hdr_args[MAX_ARGS][ARG_SIZE];
-FILE *input_file_pointer;
-FILE *g_hfd_pointer;
-FILE *arg_file_pointer;
-FILE *api_file_pointer;
-FILE *g_hdr_pointer;
-void *gh_console;
-unsigned short g_text_atrib;
-unsigned short g_bg_atrib;
-enum calc_type g_calc_type;
-unsigned int ptr_fw_addr;
-unsigned int fw_offset;
-int is_ptr_merge;
-unsigned int g_ram_start_address;
-unsigned int g_ram_size;
-int api_file_size_bytes;
-int is_mrider15 = FALSE;
-
-/* Chips information, RAM start address and RAM size. */
-struct chip_info chip_info[] = {
-	[NPCX5M5G] = {NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE},
-	[NPCX5M6G] = {NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE},
-	[NPCX7M5] = {NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE},
-	[NPCX7M6] = {NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE},
-	[NPCX7M7] = {NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE},
-	[NPCX9M3] = {NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE},
-	[NPCX9M6] = {NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE},
-};
-BUILD_ASSERT(ARRAY_SIZE(chip_info) == NPCX_CHIP_RAM_VAR_NONE);
-
-/* Support chips name strings */
-const char *supported_chips = "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
-		"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
-		"npcx7m7wc, npcx9m3f or npcx9m6f";
-
-static unsigned int calc_api_csum_bin(void);
-static unsigned int initialize_crc_32(void);
-static unsigned int update_crc_32(unsigned int crc, char c);
-static unsigned int finalize_crc_32(unsigned int crc);
-
-/*
- * Expects a path in `path`, returning a transformation as follows in `result`
- *
- * The last element of `path` is prefixed with `prefix` if the resulting
- * string fits in an array of `resultsz` characters (incl 0-termination).
- *
- * On success returns TRUE,
- * on error (path too long) prints an error on the TERR channel
- *    and returns FALSE.
- */
-static int splice_into_path(char *result, const char *path, int resultsz,
-	const char *prefix) {
-	char *last_delim, *result_last_delim;
-
-	if (strlen(path) + strlen(prefix) + 1 > resultsz) {
-		my_printf(TERR,
-			"\n\nfilename '%s' with prefix '%s' too long\n\n",
-			path, prefix);
-		my_printf(TINF,
-			"\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n",
-			strlen(path), strlen(prefix), resultsz);
-		return FALSE;
-	}
-
-	last_delim = strrchr(path, '/');
-
-	if (last_delim == NULL) {
-		/* no delimiter: prefix and exit */
-		sprintf(result, "%s%s", prefix, path);
-		return TRUE;
-	}
-
-	/* delimiter: copy, then patch in the prefix */
-	strcpy(result, path);
-	result_last_delim = result + (last_delim - path);
-	sprintf(result_last_delim + 1, "%s%s", prefix, last_delim + 1);
-	return TRUE;
-}
-
-/**
- * Convert the chip name (string) to the chip's RAM variant.
- * @param    chip_name - the string of the npcx chip variant.
- *
- * @return   one of enum value of npcx_chip_ram_variant,
- *           NPCX_CHIP_RAM_VAR_NONE otherwise.
- */
-static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
-{
-	if (str_cmp_no_case(chip_name, "npcx9m6f") == 0)
-		return NPCX9M6;
-	else if (str_cmp_no_case(chip_name, "npcx9m3f") == 0)
-		return NPCX9M3;
-	else if (str_cmp_no_case(chip_name, "npcx7m7wb") == 0)
-		return NPCX7M7;
-	else if (str_cmp_no_case(chip_name, "npcx7m7wc") == 0)
-		return NPCX7M7;
-	else if (str_cmp_no_case(chip_name, "npcx7m7fc") == 0)
-		return NPCX7M7;
-	else if (str_cmp_no_case(chip_name, "npcx7m6f") == 0)
-		return NPCX7M6;
-	else if (str_cmp_no_case(chip_name, "npcx7m6fb") == 0)
-		return NPCX7M6;
-	else if (str_cmp_no_case(chip_name, "npcx7m6fc") == 0)
-		return NPCX7M6;
-	else if (str_cmp_no_case(chip_name, "npcx7m6g") == 0)
-		return  NPCX7M6;
-	else if (str_cmp_no_case(chip_name, "npcx7m5g") == 0)
-		return NPCX7M5;
-	else if (str_cmp_no_case(chip_name, "npcx5m6g") == 0)
-		return NPCX5M6G;
-	else if (str_cmp_no_case(chip_name, "npcx5m5g") == 0)
-		return NPCX5M5G;
-	else
-		return NPCX_CHIP_RAM_VAR_NONE;
-}
-
-/*
- *----------------------------------------------------------------------
- * Function:	main()
- * Parameters:	argc, argv
- * Return:		0
- * Description:	Parse the arguments
- *		Chose manipulation routine according to arguments
- *
- *		In case of bin, save optional parameters given by user
- *----------------------------------------------------------------------
- */
-int main(int argc, char *argv[])
-
-{
-
-	int mode_choose = FALSE;
-	/* Do we get a bin File? */
-	int main_fw_hdr_flag = FALSE;
-	/* Do we get a API bin File? */
-	int main_api_flag = FALSE;
-	/* Do we need to create a BootLoader Header file? */
-	int main_hdr_flag = FALSE;
-
-	/* Following variables: common to all modes */
-	int main_status = TRUE;
-	unsigned int  main_temp = 0L;
-	char main_str_temp[TMP_STR_SIZE];
-	char *end_ptr;
-
-	int arg_num;
-	int arg_ind;
-	int tmp_ind;
-	int tmp_arg_num;
-	int cur_arg_index;
-	FILE *tmp_file;
-
-	/* Following variables are used when bin file is provided */
-	struct tbinparams bin_params;
-
-	bin_params.bin_params = 0;
-
-	input_file_name[0] = '\0';
-	memset(input_file_name, 0, NAME_SIZE);
-	output_file_name[0] = '\0';
-	memset(output_file_name, 0, NAME_SIZE);
-	arg_file_name[0] = '\0';
-	memset(arg_file_name, 0, NAME_SIZE);
-	g_hdr_input_name[0] = '\0';
-	memset(g_hdr_input_name, 0, NAME_SIZE);
-
-	/* Initialize Global variables */
-	g_verbose = NO_VERBOSE;
-
-	g_ram_start_address = chip_info[DEFAULT_CHIP].ram_addr;
-	g_ram_size          = chip_info[DEFAULT_CHIP].ram_size;
-
-	/* Set default values */
-	g_calc_type = CALC_TYPE_NONE;
-	bin_params.spi_max_clk = SPI_MAX_CLOCK_DEFAULT;
-	bin_params.spi_clk_ratio = 0x00;
-	bin_params.spi_read_mode = SPI_READ_MODE_DEFAULT;
-	bin_params.fw_load_addr =
-				chip_info[DEFAULT_CHIP].ram_addr;
-	bin_params.fw_ep =
-				chip_info[DEFAULT_CHIP].ram_addr;
-	bin_params.fw_err_detec_s_addr = FW_CRC_START_ADDR;
-	bin_params.fw_err_detec_e_addr = FW_CRC_START_ADDR;
-	bin_params.flash_size = FLASH_SIZE_DEFAULT;
-	bin_params.fw_hdr_offset = 0;
-
-	ptr_fw_addr = 0x00000000;
-	fw_offset = 0x00000000;
-	is_ptr_merge = FALSE;
-
-	/* Get Standard Output Handler */
-
-	/* Wrong Number of Arguments ? No problem */
-	if (argc < 3)
-		exit_with_usage();
-
-	/* Read all arguments to local array. */
-	for (arg_num = 0; arg_num < argc; arg_num++)
-		strncpy(hdr_args[arg_num], argv[arg_num], ARG_SIZE);
-
-	/* Loop all arguments. */
-	/* Parse the Arguments - supports ecrp and bin */
-	for (arg_ind = 1; arg_ind < arg_num; arg_ind++) {
-		/* -h display help screen */
-		if (str_cmp_no_case(hdr_args[arg_ind], "-h") == 0)
-			exit_with_usage();
-
-		/* -v verbose */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-v") == 0)
-			g_verbose = REGULAR_VERBOSE;
-
-		/* Super verbose. */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-vv") == 0)
-			g_verbose = SUPER_VERBOSE;
-
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-							"-mode") == 0) {
-			mode_choose = TRUE;
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s", main_str_temp) != 1)) {
-				my_printf(TERR, "\nCannot read operation mode");
-				my_printf(TERR, ", bt, bh or api. !\n");
-				main_status = FALSE;
-			} else {
-				/* bt, bh and api should not coexist */
-				if (main_fw_hdr_flag ||
-				    main_api_flag ||
-				    main_hdr_flag) {
-					my_printf(TERR, "\nOperation modes bt");
-					my_printf(TERR, ", bh, and api should");
-					my_printf(TERR, " not coexist.\n");
-					main_status = FALSE;
-				}
-
-				if (str_cmp_no_case(main_str_temp, "bt") == 0)
-					main_fw_hdr_flag = TRUE;
-				else if (str_cmp_no_case(main_str_temp,
-							 "bh") == 0)
-					main_hdr_flag = TRUE;
-				else if (str_cmp_no_case(main_str_temp,
-							 "api") == 0)
-					main_api_flag = TRUE;
-				else {
-					my_printf(TERR,
-						  "\nInvalid operation mode ");
-					my_printf(TERR,
-						  "(%s)\n", main_str_temp);
-					main_status = FALSE;
-				}
-			}
-		}
-
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-chip") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
-				my_printf(TERR, "\nCannot read chip name %s.\n",
-						supported_chips);
-				main_status = FALSE;
-			} else {
-				enum npcx_chip_ram_variant ram_variant;
-
-				ram_variant = chip_to_ram_var(main_str_temp);
-				if (ram_variant == NPCX_CHIP_RAM_VAR_NONE) {
-					my_printf(TERR,
-						  "\nInvalid chip name (%s) ",
-						  main_str_temp);
-					my_printf(TERR, ", it should be %s.\n",
-						supported_chips);
-					main_status = FALSE;
-					break;
-				}
-
-				if ((bin_params.bin_params
-					& BIN_FW_LOAD_START_ADDR) ==
-					0x00000000)
-					bin_params.fw_load_addr =
-					chip_info[ram_variant].ram_addr;
-
-				if ((bin_params.bin_params
-					& BIN_FW_ENTRY_POINT) ==
-					0x00000000)
-					bin_params.fw_ep =
-					chip_info[ram_variant].ram_addr;
-
-				g_ram_start_address =
-					chip_info[ram_variant].ram_addr;
-				g_ram_size =
-					chip_info[ram_variant].ram_size;
-
-				if ((ram_variant == NPCX5M5G) ||
-					(ram_variant == NPCX5M6G)) {
-					is_mrider15 = TRUE;
-				}
-			}
-		  /* -argfile Read argument file. File name must be after it.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-argfile") == 0) {
-			arg_ind++;
-			if (arg_ind < arg_num) {
-				strncpy(arg_file_name,
-						hdr_args[arg_ind],
-						sizeof(arg_file_name) - 1);
-				arg_file_pointer = fopen(arg_file_name, "rt");
-				if (arg_file_pointer == NULL) {
-					my_printf(TERR,
-						  "\n\nCannot open %s\n\n",
-						  arg_file_name);
-					main_status = FALSE;
-				} else {
-					cur_arg_index = arg_ind;
-
-					/* Copy the arguments to temp array. */
-					for (tmp_ind = 0;
-					     (tmp_ind + arg_ind + 1) < arg_num;
-					     tmp_ind++)
-						strncpy(tmp_hdr_args[tmp_ind],
-							hdr_args
-							   [tmp_ind+arg_ind+1],
-							ARG_SIZE);
-
-					tmp_arg_num = tmp_ind;
-
-					/* Read arguments from file to array */
-					for (arg_ind++;
-					     fscanf(arg_file_pointer,
-						    "%s",
-						    hdr_args[arg_ind]) == 1;
-					     arg_ind++)
-						;
-
-					fclose(arg_file_pointer);
-					arg_file_pointer = NULL;
-
-					/* Copy back the restored arguments. */
-					for (tmp_ind = 0;
-						 (tmp_ind < tmp_arg_num) &&
-						 (arg_ind < MAX_ARGS);
-						 tmp_ind++) {
-						strncpy(hdr_args[arg_ind++],
-							tmp_hdr_args[tmp_ind],
-							ARG_SIZE);
-					}
-					arg_num = arg_ind;
-					arg_ind = cur_arg_index;
-				}
-
-			} else {
-				my_printf(TERR,
-					  "\nMissing Argument File Name\n");
-				main_status = FALSE;
-			}
-			/* -i get input file name. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind], "-i") == 0) {
-			arg_ind++;
-			if (arg_ind < arg_num) {
-				strncpy(input_file_name,
-				hdr_args[arg_ind],
-				sizeof(input_file_name) - 1);
-			} else {
-				my_printf(TERR, "\nMissing Input File Name\n");
-				main_status = FALSE;
-			}
-		  /* -o Get output file name. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind], "-o") == 0) {
-			arg_ind++;
-			if (arg_ind < arg_num) {
-				strncpy(output_file_name,
-					hdr_args[arg_ind],
-					sizeof(output_file_name) - 1);
-			} else {
-				my_printf(TERR,
-					  "\nMissing Output File Name.\n");
-				main_status = FALSE;
-			}
-		  /* -usearmrst get FW entry point from FW image offset 4.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-usearmrst") == 0) {
-			if ((bin_params.bin_params &
-			     BIN_FW_ENTRY_POINT) != 0x00000000) {
-				my_printf(TERR, "\n-usearmrst not allowed, ");
-				my_printf(TERR, "FW entry point already set ");
-				my_printf(TERR, "using -fwep !\n");
-				main_status = FALSE;
-			} else
-				bin_params.bin_params |=
-							BIN_FW_USER_ARM_RESET;
-		/* -nohcrs disable header CRC*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind], "-nohcrc") == 0)
-			bin_params.bin_params |=
-							BIN_FW_HDR_CRC_DISABLE;
-		/* -ph merg header in BIN file. */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-ph") == 0) {
-			bin_params.bin_params |=
-							BIN_FW_HDR_OFFSET;
-			if ((strlen(hdr_args[arg_ind+1]) == 0) ||
-				(sscanf(hdr_args[arg_ind+1],
-					"%x",
-					&main_temp) != 1))
-				bin_params.fw_hdr_offset = 0;
-			else {
-				arg_ind++;
-				bin_params.fw_hdr_offset = main_temp;
-			}
-		/* -spimaxclk  Get SPI flash max clock. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spimaxclk") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d", &main_temp) != 1)) {
-				my_printf(TERR, "\nCannot read SPI Flash Max");
-				my_printf(TERR, " Clock !\n");
-				main_status = FALSE;
-			} else
-				bin_params.spi_max_clk =
-						(unsigned char) main_temp;
-		/* -spiclkratio  Get SPI flash max clock ratio. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-			"-spiclkratio") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-				"%d", &main_temp) != 1)) {
-				my_printf(TERR,
-					  "\nCannot read SPI Clock Ratio\n");
-				main_status = FALSE;
-			} else
-				bin_params.spi_clk_ratio =
-						(unsigned char)main_temp;
-
-		/* spireadmode	get SPI read mode. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spireadmode") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-						"%20s",
-						main_str_temp) != 1)) {
-				my_printf(TERR, "\nCannot read SPI Flash");
-				my_printf(TERR, " Read Mode !\n");
-				main_status = FALSE;
-			} else {
-				if (str_cmp_no_case(main_str_temp,
-						SPI_NORMAL_MODE_VAL) == 0)
-					bin_params.spi_read_mode =
-					(unsigned char) SPI_NORMAL_MODE;
-				else if (str_cmp_no_case(main_str_temp,
-					 SPI_SINGLE_MODE_VAL) == 0)
-					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_SINGLE_MODE;
-				else if (str_cmp_no_case(main_str_temp,
-					 SPI_DUAL_MODE_VAL) == 0)
-					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_DUAL_MODE;
-				else if (str_cmp_no_case(main_str_temp,
-					SPI_QUAD_MODE_VAL) == 0)
-					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_QUAD_MODE;
-				else {
-					my_printf(TERR,
-						  "\nInvalid SPI Flash Read ");
-					my_printf(TERR,
-						  "Mode (%s), it should be ",
-						  main_str_temp);
-					my_printf(TERR,
-						  "normal, singleMode, ");
-					my_printf(TERR,
-						  "dualMode or quadMode !\n");
-					main_status = FALSE;
-				}
-			}
-
-		}
-		/* -unlimburst enable unlimited burst */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-unlimburst") == 0)
-			bin_params.bin_params |= BIN_UNLIM_BURST_ENABLE;
-		/* -nofcrc disable FW CRC. */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-nofcrc") == 0)
-			bin_params.bin_params |= BIN_FW_CRC_DISABLE;
-
-		/* -fwloadaddr,  Get the FW load address. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-fwloadaddr") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-				my_printf(TERR, "\nCannot read FW Load ");
-				my_printf(TERR, "\nstart address !\n");
-				main_status = FALSE;
-			} else {
-				/* Check that the address is 16-bytes aligned */
-				if ((main_temp &
-					ADDR_16_BYTES_ALIGNED_MASK) != 0) {
-					my_printf(TERR,
-						  "\nFW load address start ");
-					my_printf(TERR,
-						  "address (0x%08X) is not ",
-						  main_temp);
-					my_printf(TERR,
-						  "16-bytes aligned !\n");
-					main_status = FALSE;
-				} else {
-					bin_params.fw_load_addr =
-								     main_temp;
-					bin_params.bin_params |=
-							BIN_FW_LOAD_START_ADDR;
-				}
-			}
-		  /* -fwep, Get the FW entry point. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind], "-fwep") == 0) {
-			if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET)
-								!= 0x00000000) {
-				my_printf(TERR,
-					 "\n-fwep not allowed, FW entry point");
-				my_printf(TERR,
-					  " already set using -usearmrst!\n");
-				main_status = FALSE;
-			} else {
-				arg_ind++;
-				if ((hdr_args[arg_ind] == NULL) ||
-					(sscanf(hdr_args[arg_ind],
-						"%x",
-						&main_temp) != 1)) {
-					my_printf(TERR,
-						  "\nCan't read FW E-Point\n");
-					main_status = FALSE;
-				} else {
-					bin_params.fw_ep =
-								main_temp;
-					bin_params.bin_params |=
-							BIN_FW_ENTRY_POINT;
-				}
-			}
-		  /*
-		   * -crcstart, Get the address from where to calculate
-		   * the FW CRC.
-		   */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcstart") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-						my_printf(TERR,
-						  "\nCannot read FW CRC");
-						my_printf(TERR,
-						  " start address !\n");
-				main_status = FALSE;
-			} else {
-				bin_params.fw_err_detec_e_addr =
-					bin_params.fw_err_detec_e_addr -
-					bin_params.fw_err_detec_s_addr
-					+ main_temp;
-				bin_params.fw_err_detec_s_addr =
-								main_temp;
-				bin_params.bin_params |= BIN_FW_CKS_START;
-			}
-		  /* -crcsize,  Get the area size that need to be CRCed. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcsize") == 0) {
-			arg_ind++;
-			main_temp = 0x00;
-			if (hdr_args[arg_ind] == NULL)
-				end_ptr = NULL;
-			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
-
-			if (hdr_args[arg_ind] == end_ptr) {
-				my_printf(TERR,
-					  "\nCannot read FW CRC area size !\n");
-				main_status = FALSE;
-			} else {
-				bin_params.fw_err_detec_e_addr =
-					bin_params.fw_err_detec_s_addr
-					+ main_temp - 1;
-				bin_params.bin_params |= BIN_FW_CKS_SIZE;
-			}
-		}
-		/* -fwlen, Get the FW length. */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-fwlen") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-				my_printf(TERR, "\nCannot read FW length !\n");
-				main_status = FALSE;
-			} else {
-				bin_params.fw_len = main_temp;
-				bin_params.bin_params |= BIN_FW_LENGTH;
-			}
-		}
-		/* flashsize, Get the flash size. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-flashsize") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d",
-					&main_temp) != 1)) {
-				my_printf(TERR, "\nCannot read Flash size !\n");
-				main_status = FALSE;
-			} else
-				bin_params.flash_size = main_temp;
-		  /* -apisign, Get the method for error detect calculation. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-apisign") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
-				my_printf(TERR, "\nCannot read API sign, CRC,");
-				my_printf(TERR, " CheckSum or None. !\n");
-				main_status = FALSE;
-			} else {
-				if (!main_api_flag) {
-					my_printf(TERR, "\n-apisign is valid ");
-					my_printf(TERR, "-only with -api.\n");
-					main_status = FALSE;
-				}
-
-				if (str_cmp_no_case(main_str_temp, "crc") == 0)
-					g_calc_type = CALC_TYPE_CRC;
-
-				else if (str_cmp_no_case(main_str_temp,
-							 "checksum") == 0)
-					g_calc_type = CALC_TYPE_CHECKSUM;
-
-				else {
-					my_printf(TERR,
-						  "\nInvalid API sign (%s)\n",
-						  main_str_temp);
-					main_status = FALSE;
-				}
-
-			}
-		  /* -pointer,  Get the FW image address. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-pointer") == 0) {
-			arg_ind++;
-			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-				my_printf(TERR,
-					  "\nCannot read FW Image address !\n");
-				main_status = FALSE;
-			} else {
-				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
-					my_printf(TERR,
-						  "\nFW Image address (0x%08X)"
-						  " isn't 16-bytes aligned !\n",
-						  main_temp);
-					main_status = FALSE;
-				}
-
-				if (main_temp > MAX_FLASH_SIZE) {
-					my_printf(TERR,
-						  "\nPointer address (0x%08X) ",
-						  main_temp);
-					my_printf(TERR,
-						  "is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
-						  MAX_FLASH_SIZE);
-					main_status = FALSE;
-				} else {
-					ptr_fw_addr = main_temp;
-					is_ptr_merge = FALSE;
-				}
-			}
-		}
-		/* -bhoffset,  BootLoader Header Offset (BH location in BT). */
-		else if (str_cmp_no_case(hdr_args[arg_ind], "-bhoffset") == 0) {
-			arg_ind++;
-			main_temp = 0x00;
-			if (hdr_args[arg_ind] == NULL)
-				end_ptr = NULL;
-			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
-
-			if (hdr_args[arg_ind] == end_ptr) {
-				my_printf(TERR, "\nCannot read BootLoader");
-				my_printf(TERR, " Header Offset !\n");
-				main_status = FALSE;
-			} else {
-				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
-					my_printf(TERR,
-						  "\nFW Image address (0x%08X) ",
-						  main_temp);
-					my_printf(TERR,
-						  "is not 16-bytes aligned!\n");
-				}
-
-				if (main_temp > MAX_FLASH_SIZE) {
-					my_printf(TERR,
-						  "\nFW Image address (0x%08X)",
-						  main_temp);
-					my_printf(TERR,
-						  " is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
-						  MAX_FLASH_SIZE);
-					main_status = FALSE;
-				} else {
-					fw_offset = main_temp;
-					is_ptr_merge = TRUE;
-				}
-			}
-		} else {
-			my_printf(TERR,
-				  "\nUnknown flag: %s\n",
-				  hdr_args[arg_ind]);
-			main_status = FALSE;
-		}
-	}
-
-	/*
-	* If the input and output file have the same name then exit with error.
-	*/
-	if (strcmp(output_file_name, input_file_name) == 0) {
-		my_printf(TINF,
-			"Input file name (%s) should be differed from\n",
-			input_file_name);
-		my_printf(TINF, "Output file name (%s).\n", output_file_name);
-		main_status = FALSE;
-	}
-
-	/* No problems reading argv? So go on... */
-	if (main_status) {
-
-		/* if output file already exist, then delete it. */
-		tmp_file = fopen(output_file_name, "w");
-		if (tmp_file != NULL)
-			fclose(tmp_file);
-
-		/* If no mode choose than "bt" is the default mode.*/
-		if (mode_choose == FALSE)
-			main_fw_hdr_flag = TRUE;
-
-		/* Chose manipulation routine according to arguments */
-		if (main_fw_hdr_flag)
-			main_status = main_bin(bin_params);
-		else if (main_api_flag)
-			main_status = main_api();
-		else if (main_hdr_flag)
-			main_status = main_hdr();
-		else
-			exit_with_usage();
-	}
-
-	/* Be sure there's no open file before you leave */
-	if (input_file_pointer)
-		fclose(input_file_pointer);
-	if (g_hfd_pointer)
-		fclose(g_hfd_pointer);
-	if (api_file_pointer)
-		fclose(api_file_pointer);
-
-	/* Delete temprary header file. */
-	remove(g_hdr_input_name);
-
-	/* Say Bye Bye */
-	if (main_status) {
-		my_printf(TPAS, "\n\n******************************");
-		my_printf(TPAS,   "\n***    SUCCESS     ***");
-		my_printf(TPAS,   "\n******************************\n");
-
-		exit(EXIT_SUCCESS);
-	} else {
-		my_printf(TERR, "\n\n******************************");
-		my_printf(TERR,   "\n***    FAILED      ***");
-		my_printf(TERR,   "\n******************************\n");
-
-		exit(EXIT_FAILURE);
-	}
-
-}
-
-/*
- *-----------------------------------------------------------------------
- * Function:	exit_with_usage()
- * Parameters:	none
- * Return:		none
- * Description: No Words...
- *-----------------------------------------------------------------------
- */
-void exit_with_usage(void)
-{
-	my_printf(TUSG,
-		  "\nECST, Embedded Controller Sign Tool, version %d.%d.%d",
-		  T_VER, T_REV_MAJOR, T_REV_MINOR);
-	my_printf(TUSG, "\n");
-	my_printf(TUSG, "\nUsage:");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\n ECST -mode <bt|bh|api> -i <filename> [Flags]");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\nOperation Modes: ");
-	my_printf(TUSG, "\n bt  - BootLoader Table");
-	my_printf(TUSG, "\n bh  - BootLoader Header");
-	my_printf(TUSG, "\n api - Download from Flash API");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\nCommon flags:");
-	my_printf(TUSG, "\n -mode <type>        - Operation mode: ");
-	my_printf(TUSG, "bt|bh|api (default is bt)");
-	my_printf(TUSG, "\n -i <filename>       - Input file name; ");
-	my_printf(TUSG, "must differ from the output file name");
-	my_printf(TUSG, "\n -o <filename>       - Output file name ");
-	my_printf(TUSG, "(default is out_<input_filename>.bin)");
-	my_printf(TUSG, "\n -argfile <filename> - Arguments file name; ");
-	my_printf(TUSG, "includes multiple flags");
-	my_printf(TUSG, "\n -chip <name>        - Supported EC Chip Name: ");
-	my_printf(TUSG, "%s. ", supported_chips);
-	my_printf(TUSG, "(default is npcx5m5g)");
-	my_printf(TUSG, "\n -v          - Verbose; prints ");
-	my_printf(TUSG, "information messages");
-	my_printf(TUSG, "\n -vv         - Super Verbose; prints ");
-	my_printf(TUSG, "intermediate calculations");
-	my_printf(TUSG, "\n -h          - Show this help screen");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\nBootLoader Table mode flags:");
-	my_printf(TUSG, "\n -nohcrc     - Disable CRC on header ");
-	my_printf(TUSG, "(default is ON)");
-	my_printf(TUSG, "\n -nofcrc     - Disable CRC on firmware ");
-	my_printf(TUSG, "(default is ON)");
-	my_printf(TUSG, "\n -spimaxclk <val>    - SPI Flash Maximum Clock, in");
-	my_printf(TUSG, " MHz: 20|25|33|40|50 (default is 20)");
-	my_printf(TUSG, "\n -spiclkratio <val>  - Core Clock / SPI Flash ");
-	my_printf(TUSG, "Clocks Ratio: 1 | 2 (default is 1)");
-	my_printf(TUSG, "\n                       ");
-	my_printf(TUSG, "Note: Not relevant for npcx5mng chips family");
-	my_printf(TUSG, "\n -spireadmode <type> - SPI Flash Read Mode: ");
-	my_printf(TUSG, "normal|fast|dual|quad (default is normal)");
-	my_printf(TUSG, "\n -unlimburst         - Enable FIU Unlimited ");
-	my_printf(TUSG, "\n                       ");
-	my_printf(TUSG, "Note: Not relevant for npcx5mng chips family");
-	my_printf(TUSG, "Burst for SPI Flash Accesses (default is disable).");
-	my_printf(TUSG, "\n -fwloadaddr <addr>  - Firmware load start ");
-	my_printf(TUSG, "address (default is Start-of-RAM)");
-	my_printf(TUSG, "\n           Located in code RAM, ");
-	my_printf(TUSG, "16-bytes aligned, hex format");
-	my_printf(TUSG, "\n -usearmrst      - Use the ARM reset table ");
-	my_printf(TUSG, "entry as the Firmware Entry Point");
-	my_printf(TUSG, "\n           Can't be used with -fwep");
-	my_printf(TUSG, "\n -fwep <addr>        - Firmware entry ");
-	my_printf(TUSG, "point (default is Firmware Entry Point)");
-	my_printf(TUSG, "\n           Located in firmware area,");
-	my_printf(TUSG, " hex format");
-	my_printf(TUSG, "\n -crcstart <offset>  - Firmware CRC start offset ");
-	my_printf(TUSG, "(default is 00000000)");
-	my_printf(TUSG, "\n           Offset from firmware image,");
-	my_printf(TUSG, " 4B-aligned, for partial CRC, hex format");
-	my_printf(TUSG, "\n -crcsize <val>      - Firmware CRC size ");
-	my_printf(TUSG, "(default is entire firmware size)");
-	my_printf(TUSG, "\n           4B-aligned, for partial ");
-	my_printf(TUSG, "CRC, hex format");
-	my_printf(TUSG, "\n -fwlen <val>        - Firmware length, ");
-	my_printf(TUSG, "16B-aligned, hex format (default is file size).");
-	my_printf(TUSG, "\n -flashsize <val>    - Flash size, in MB: ");
-	my_printf(TUSG, "1|2|4|8|16 (default is 16)");
-	my_printf(TUSG, "\n -ph <offset>        - Paste the Firmware ");
-	my_printf(TUSG, "Header in the input file copy at the selected");
-	my_printf(TUSG, "\n           offset ");
-	my_printf(TUSG, "(default is 00000000), hex format.");
-	my_printf(TUSG, "\n           The firmware itself is ");
-	my_printf(TUSG, "expected to start at offset + 64 bytes.");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\nBootLoader Header mode flags:");
-	my_printf(TUSG, "\n -pointer <offset>   - BootLoader Table location");
-	my_printf(TUSG, " in the flash, hex format");
-	my_printf(TUSG, "\n -bhoffset <offset>  - BootLoader Header Offset");
-	my_printf(TUSG, " in file, hex format (BH location in BT)");
-	my_printf(TUSG, "\n ");
-	my_printf(TUSG, "\nAPI mode flags:");
-	my_printf(TUSG, "\n -apisign <type> - Signature type: ");
-	my_printf(TUSG, "crc|checksum (default is OFF)");
-	my_printf(TUSG, "\n\n");
-
-	exit(EXIT_FAILURE);
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	copy_file_to_file()
- * Parameters:	dst_file_name	- Destination file name.
- *		src_file_name	- Source file name.
- *		offset		- number of bytes from the origin.
- *		origin		- From where to seek, START, END, or CURRENT of
- *				  file.
- * Return: Number of copied bytes
- * Description: Copy the source file to the end of the destination file.
- *--------------------------------------------------------------------------
- */
-int copy_file_to_file(char *dst_file_name,
-		      char *src_file_name,
-		      int offset,
-		      int  origin)
-{
-
-	int index = 0;
-	int result = 0;
-	unsigned char local_val;
-	int src_file_size;
-	FILE *dst_file;
-	FILE *src_file;
-
-	/* Open the destination file for append. */
-	dst_file = fopen(dst_file_name, "r+b");
-	if (dst_file == NULL) {
-		/* destination file not exist, create it. */
-		dst_file = fopen(dst_file_name, "ab");
-		if (dst_file == NULL)
-			return 0;
-	}
-
-	/* Open the source file for read. */
-	src_file = fopen(src_file_name, "rb");
-	if (src_file == NULL) {
-		fclose(dst_file);
-		return 0;
-	}
-
-	/* Get the source file length in bytes. */
-	src_file_size = get_file_length(src_file);
-
-	/* Point to the end of the destination file, and to the start */
-	/* of the source file. */
-	if (fseek(dst_file, offset, origin) < 0)
-		goto out;
-	if (fseek(src_file, 0, SEEK_SET) < 0)
-		goto out;
-
-	/* Loop over all destination file and write it to the source file.*/
-	for (index = 0; index < src_file_size; index++) {
-		/* Read byte from source file. */
-		result = (int)(fread(&local_val, 1, 1, src_file));
-
-		/* If byte reading pass than write it to the destination, */
-		/* else exit from the reading loop. */
-		if (result) {
-			/* Read pass, so write it to destination file.*/
-			result = fwrite(&local_val, 1, 1, dst_file);
-			if (!result)
-				/*
-				 * Write failed,
-				 * return with the copied bytes number.
-				 */
-				break;
-		} else
-			/* Read failed, return with the copied bytes number. */
-			break;
-	}
-
-out:
-	/* Close the files. */
-	fclose(dst_file);
-	fclose(src_file);
-
-	/* Copy ended, return with the number of bytes that were copied. */
-	return index;
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	my_printf()
- * Parameters:	as in printf + error level
- * Return:		none
- * Description: No Words...
- *--------------------------------------------------------------------------
- */
-void my_printf(int error_level, char *fmt, ...)
-{
-	va_list argptr;
-
-	if ((g_verbose == NO_VERBOSE) && (error_level == TINF))
-		return;
-
-	if ((g_verbose != SUPER_VERBOSE) && (error_level == TDBG))
-		return;
-
-	va_start(argptr, fmt);
-	vprintf(fmt, argptr);
-	va_end(argptr);
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	 write_to_file
- * Parameters:	 TBD
- * Return:	 TRUE on successful write
- * Description:	 Writes to ELF or BIN files - whatever is open
- *--------------------------------------------------------------------------
- */
-int write_to_file(unsigned int write_value,
-		  unsigned int offset,
-		  unsigned char num_of_bytes,
-		  char *print_string)
-{
-
-	int result = 0;
-	int index;
-	unsigned int localValue4;
-	unsigned short localValue2;
-	unsigned char localValue1;
-
-	if (fseek(g_hfd_pointer, offset, SEEK_SET) < 0)
-		return FALSE;
-
-	switch (num_of_bytes) {
-	case(1):
-		localValue1 = (unsigned char)write_value;
-		result = (int)(fwrite(&localValue1, 1,
-							  1, g_hfd_pointer));
-	break;
-	case(2):
-		localValue2 = (unsigned short)write_value;
-		result = (int)(fwrite(&localValue2,
-				      2,
-				      1,
-				      g_hfd_pointer));
-		break;
-	case(4):
-		localValue4 = write_value;
-		result = (int)(fwrite(&localValue4,
-				      4,
-				      1,
-				      g_hfd_pointer));
-		break;
-	default:
-		/* Pad the same value N times. */
-		localValue1 = (unsigned char)write_value;
-		for (index = 0; index < num_of_bytes; index++)
-			result = (int)(fwrite(&localValue1,
-					      1,
-					      1,
-					      g_hfd_pointer));
-		break;
-	}
-
-	my_printf(TINF, "\nIn write_to_file  - %s", print_string);
-
-	if (result) {
-		my_printf(TINF,
-			" - Offset %2d - value 0x%x",
-			offset, write_value);
-	} else {
-		my_printf(TERR,
-			"\n\nCouldn't write %x to file at %x\n\n",
-			write_value, offset);
-		return FALSE;
-	}
-
-	return TRUE;
-
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	 read_from_file
- * Parameters:	 TBD
- * Return:       TRUE on successful read
- * Description : Reads from open BIN file
- *--------------------------------------------------------------------------
- */
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string)
-{
-	int result;
-	unsigned int localValue4;
-	unsigned short localValue2;
-	unsigned char localValue1;
-
-	if (fseek(input_file_pointer, offset, SEEK_SET) < 0)
-		return FALSE;
-
-	switch (size_to_read) {
-	case(1):
-		result = (int)(fread(&localValue1,
-				     1,
-				     1,
-				     input_file_pointer));
-		*read_value = localValue1;
-		break;
-	case(2):
-		result = (int)(fread(&localValue2,
-				     2,
-				     1,
-				     input_file_pointer));
-		*read_value = localValue2;
-		break;
-	case(4):
-		result = (int)(fread(&localValue4,
-				     4,
-				     1,
-				     input_file_pointer));
-		*read_value = localValue4;
-		break;
-	default:
-		my_printf(TERR, "\nIn read_from_file - %s", print_string);
-		my_printf(TERR, "\n\nInvalid call to read_from_file\n\n");
-		return FALSE;
-	}
-
-	my_printf(TINF, "\nIn read_from_file - %s", print_string);
-
-	if (result) {
-		my_printf(TINF,
-			" - Offset %d - value %x",
-			offset, *read_value);
-	} else {
-		my_printf(TERR,
-			"\n\nCouldn't read from file at %x\n\n",
-			offset);
-		return FALSE;
-	}
-
-	return TRUE;
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	init_calculation
- * Parameters:	unsigned int check_sum_crc (I\O)
- * Return:
- * Description:	Initialize the variable according to the selected
- *				calculation
- *--------------------------------------------------------------------------
- */
-void init_calculation(unsigned int *check_sum_crc)
-{
-	switch (g_calc_type) {
-	case CALC_TYPE_NONE:
-	case CALC_TYPE_CHECKSUM:
-		*check_sum_crc = 0;
-		break;
-	case CALC_TYPE_CRC:
-		*check_sum_crc = initialize_crc_32();
-		break;
-	}
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	 finalize_calculation
- * Parameters:	 unsigned int check_sum_crc (I\O)
- * Return:
- * Description:	Finalize the variable according to the selected calculation
- *--------------------------------------------------------------------------
- */
-void finalize_calculation(unsigned int *check_sum_crc)
-{
-	switch (g_calc_type) {
-	case CALC_TYPE_NONE:
-	case CALC_TYPE_CHECKSUM:
-		/* Do nothing */
-		break;
-	case CALC_TYPE_CRC:
-		*check_sum_crc = finalize_crc_32(*check_sum_crc);
-		break;
-	}
-}
-
-/*--------------------------------------------------------------------------
- * Function:	 update_calculation
- * Parameters:	 unsigned int check_sum_crc (I\O)
- *		 unsigned int byte_to_add (I)
- * Return:
- * Description:	 Calculate a new checksum\crc with the new byte_to_add
- *		 given the previous checksum\crc
- *--------------------------------------------------------------------------
- */
-void update_calculation(unsigned int *check_sum_crc,
-						unsigned char byte_to_add)
-{
-	switch (g_calc_type) {
-	case CALC_TYPE_NONE:
-			/* Do nothing */
-		break;
-	case CALC_TYPE_CHECKSUM:
-		*check_sum_crc += byte_to_add;
-		break;
-	case CALC_TYPE_CRC:
-		*check_sum_crc = update_crc_32(*check_sum_crc, byte_to_add);
-		break;
-	}
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	 str_cmp_no_case
- * Parameters:	 s1, s2: Strings to compare.
- * Return:	 function returns an integer less than, equal to, or
- *		 greater than zero if s1 (or the first n bytes thereof) is
- *		 found, respectively, to be less than, to match, or be
- *		 greater than s2.
- * Description:	 Compare two string without case sensitive.
- *--------------------------------------------------------------------------
- */
-int str_cmp_no_case(const char *s1, const char *s2)
-{
-	return strcasecmp(s1, s2);
-}
-
-/*
- *--------------------------------------------------------------------------
- * Function:	 get_file_length
- * Parameters:	 stream - Pointer to a FILE object
- * Return:		 File length in bytes or -1 on error
- * Description:	 Gets the file length in bytes.
- *--------------------------------------------------------------------------
- */
-int get_file_length(FILE *stream)
-{
-	int current_position;
-	int file_len;
-
-	/* Store current position. */
-	current_position = ftell(stream);
-	if (current_position < 0)
-		return -1;
-
-	/* End position of the file is its length. */
-	if (fseek(stream, 0, SEEK_END) < 0)
-		return -1;
-	file_len = ftell(stream);
-
-	/* Restore the original position. */
-	if (fseek(stream, current_position, SEEK_SET) < 0)
-		return -1;
-
-	/* return file length. */
-	return file_len;
-}
-
-/*
- ***************************************************************************
- *							"bt" mode Handler
- ***************************************************************************
- */
-
-/*
- ***************************************************************************
- * Function:	 main_bin
- * Parameters:	 TBD
- * Return:		 True for success
- * Description:
- *	 TBD
- ***************************************************************************
- */
-int main_bin(struct tbinparams binary_params)
-{
-	unsigned int bin_file_size_bytes;
-	unsigned int bin_fw_offset = 0;
-	unsigned int tmp_param;
-	FILE *output_file_pointer;
-
-	/* If input file was not declared, then print error message. */
-	if (strlen(input_file_name) == 0) {
-		my_printf(TERR, "\n\nDefine input file, using -i flag\n\n");
-		return FALSE;
-	}
-
-	/* Open input file */
-	input_file_pointer = fopen(input_file_name, "r+b");
-	if (input_file_pointer == NULL) {
-		my_printf(TERR, "\n\nCannot open %s\n\n", input_file_name);
-		return FALSE;
-	}
-
-	/*
-	 * Check Binary file size, this file contain the image itself,
-	 * without any header.
-	 */
-	bin_file_size_bytes = get_file_length(input_file_pointer);
-	if (bin_file_size_bytes == 0) {
-		my_printf(TINF,
-			  "\nBIN Input file name %s is empty (size is %d)\n",
-			  input_file_name, bin_file_size_bytes);
-		return FALSE;
-	}
-
-	/*
-	 * If the binary file contains also place for the header, then the FW
-	 * size is the length of the file minus the header length
-	 */
-	if ((binary_params.bin_params & BIN_FW_HDR_OFFSET) != 0)
-		bin_fw_offset = binary_params.fw_hdr_offset + HEADER_SIZE;
-
-	my_printf(TINF, "\nBIN file:  %s, size: %d (0x%x) bytes\n",
-			  input_file_name,
-			  bin_file_size_bytes,
-			  bin_file_size_bytes);
-
-	/* Check validity of FW header offset. */
-	if (((int)binary_params.fw_hdr_offset < 0) ||
-		(binary_params.fw_hdr_offset > bin_file_size_bytes)) {
-		my_printf(TERR,
-			  "\nFW header offset 0x%08x (%d) should be in the"
-			  " range of 0 and file size (%d).\n",
-			  binary_params.fw_hdr_offset,
-			  binary_params.fw_hdr_offset,
-			  bin_file_size_bytes);
-		return FALSE;
-	}
-
-	/* Create the header file in the same directory as the input file. */
-	if (!splice_into_path(g_hdr_input_name, input_file_name,
-		sizeof(g_hdr_input_name), "hdr_"))
-		return FALSE;
-	g_hfd_pointer = fopen(g_hdr_input_name, "w+b");
-	if (g_hfd_pointer == NULL) {
-		my_printf(TERR, "\n\nCannot open %s\n\n", g_hdr_input_name);
-		return FALSE;
-	}
-
-	if (strlen(output_file_name) == 0) {
-		if (!splice_into_path(output_file_name, input_file_name,
-			sizeof(output_file_name), "out_"))
-			return FALSE;
-	}
-
-	my_printf(TINF, "Output file name: %s\n", output_file_name);
-
-	/*
-	 *********************************************************************
-	 * Set the ANCHOR & Extended-ANCHOR
-	 *********************************************************************
-	 */
-	/* Write the ancore. */
-	if (!write_to_file(FW_HDR_ANCHOR,
-			   HDR_ANCHOR_OFFSET,
-			   4,
-			   "HDR - FW Header ANCHOR		  "))
-		return FALSE;
-
-	/* Write the extended anchor. */
-	if (binary_params.bin_params & BIN_FW_HDR_CRC_DISABLE) {
-
-		/* Write the ancore and the extended anchor. */
-		if (!write_to_file(FW_HDR_EXT_ANCHOR_DISABLE,
-				   HDR_EXTENDED_ANCHOR_OFFSET, 2,
-				   "HDR - Header EXTENDED ANCHOR "))
-			return FALSE;
-	} else {
-		/* Write the anchor and the extended anchor. */
-		if (!write_to_file(FW_HDR_EXT_ANCHOR_ENABLE,
-				   HDR_EXTENDED_ANCHOR_OFFSET, 2,
-				   "HDR - Header EXTENDED ANCHOR "))
-			return FALSE;
-	}
-
-	/* Write the SPI flash MAX clock. */
-	switch (binary_params.spi_max_clk) {
-	case SPI_MAX_CLOCK_20_MHZ_VAL:
-		tmp_param = SPI_MAX_CLOCK_20_MHZ;
-		break;
-	case SPI_MAX_CLOCK_25_MHZ_VAL:
-		tmp_param = SPI_MAX_CLOCK_25_MHZ;
-		break;
-	case SPI_MAX_CLOCK_33_MHZ_VAL:
-		tmp_param = SPI_MAX_CLOCK_33_MHZ;
-		break;
-	case SPI_MAX_CLOCK_40_MHZ_VAL:
-		tmp_param = SPI_MAX_CLOCK_40_MHZ;
-		break;
-	case SPI_MAX_CLOCK_50_MHZ_VAL:
-		tmp_param = SPI_MAX_CLOCK_50_MHZ;
-		break;
-	default:
-		my_printf(TERR, "\n\nInvalid SPI Flash MAX clock (%d MHz) ",
-				  binary_params.spi_max_clk);
-		my_printf(TERR, "- it should be 20, 25, 33, 40 or 50 MHz");
-		return FALSE;
-	}
-
-	/* If SPI clock ratio set for MRIDER15, then it is error. */
-	if ((binary_params.spi_clk_ratio != 0x00) && (is_mrider15 == TRUE)) {
-
-		my_printf(TERR, "\nspiclkratio is not relevant for");
-		my_printf(TERR, " npcx5mng chips family !\n");
-
-		return FALSE;
-	}
-
-	/*
-	 * In case SPIU clock ratio didn't set by the user,
-	 *  set it to its default value.
-	 */
-	if (binary_params.spi_clk_ratio == 0x00)
-		binary_params.spi_clk_ratio = SPI_CLOCK_RATIO_1_VAL;
-
-	switch (binary_params.spi_clk_ratio) {
-	case SPI_CLOCK_RATIO_1_VAL:
-		tmp_param &= SPI_CLOCK_RATIO_1;
-		break;
-	case SPI_CLOCK_RATIO_2_VAL:
-		tmp_param |= SPI_CLOCK_RATIO_2;
-		break;
-	default:
-		my_printf(TERR, "\n\nInvalid SPI Core Clock Ratio (%d) ",
-			binary_params.spi_clk_ratio);
-		my_printf(TERR, "- it should be 1 or 2");
-		return FALSE;
-	}
-
-	if (!write_to_file(tmp_param, HDR_SPI_MAX_CLK_OFFSET, 1,
-					   "HDR - SPI flash MAX Clock	  "))
-		return FALSE;
-
-	/* Write the SPI flash Read Mode. */
-	tmp_param = binary_params.spi_read_mode;
-	/* If needed, set the unlimited burst bit. */
-	if (binary_params.bin_params & BIN_UNLIM_BURST_ENABLE) {
-		if (is_mrider15 == TRUE) {
-
-			my_printf(TERR, "\nunlimburst is not relevant for");
-			my_printf(TERR, " npcx5mng chips family !\n");
-
-			return FALSE;
-		}
-
-		tmp_param |= SPI_UNLIMITED_BURST_ENABLE;
-	}
-	if (!write_to_file(tmp_param,
-					   HDR_SPI_READ_MODE_OFFSET, 1,
-					   "HDR - SPI flash Read Mode	   "))
-		return FALSE;
-
-	/* Write the error detection configuration. */
-	if (binary_params.bin_params & BIN_FW_CRC_DISABLE) {
-		if (!write_to_file(FW_CRC_DISABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET,
-				   1,
-				   "HDR - FW CRC Disabled		   "))
-			return FALSE;
-	} else {
-		/* Write the ancore and the extended anchor. */
-		if (!write_to_file(FW_CRC_ENABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET, 1,
-				   "HDR - FW CRC Enabled		  "))
-			return FALSE;
-	}
-
-	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_load_addr >
-					(g_ram_start_address + g_ram_size)) ||
-		(binary_params.fw_load_addr < g_ram_start_address)) {
-		my_printf(TERR,
-			  "\nFW load address (0x%08x) should be between ",
-			  binary_params.fw_load_addr);
-		my_printf(TERR,
-			  "start (0x%08x) and end (0x%08x) of RAM ).",
-			  g_ram_start_address,
-			  (g_ram_start_address + g_ram_size));
-
-		return FALSE;
-	}
-
-	/* Write the FW load start address */
-	if (!write_to_file(binary_params.fw_load_addr,
-					   HDR_FW_LOAD_START_ADDR_OFFSET, 4,
-					   "HDR - FW load start address	 "))
-		return FALSE;
-
-	/*
-	 * Write the FW length. (MUST BE SET BEFORE fw_err_detec_e_addr)
-	 */
-	if ((binary_params.bin_params & BIN_FW_LENGTH) == 0x00000000) {
-		/*
-		 * In case the FW length was not set, then the FW length is the
-		 * size of the binary file minus the offset of the start of the
-		 * FW.
-		 */
-		binary_params.fw_len = bin_file_size_bytes-bin_fw_offset;
-	}
-
-	if ((int)binary_params.fw_len < 0) {
-		my_printf(TERR,
-			  "\nFW length %d (0x%08x) should be greater than 0x0.",
-			  binary_params.fw_len,
-			  binary_params.fw_len);
-		return FALSE;
-	}
-
-	if (((int)binary_params.fw_len >
-				(bin_file_size_bytes - bin_fw_offset)) ||
-		((int)binary_params.fw_len > g_ram_size)) {
-		my_printf(TERR,
-			  "\nFW length %d (0x%08x) should be within the",
-			  binary_params.fw_len, binary_params.fw_len);
-		my_printf(TERR,
-			  " input-file (related to the FW offset)");
-		my_printf(TERR,
-			  "\n (0x%08x) and within the RAM (RAM size: 0x%08x).",
-			  (bin_file_size_bytes - bin_fw_offset), g_ram_size);
-		return FALSE;
-	}
-
-	if ((binary_params.bin_params & BIN_FW_USER_ARM_RESET) != 0x00000000) {
-		read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET),
-			4,
-			&binary_params.fw_ep,
-			"read FW entry point for FW image ");
-
-		if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-			(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
-			my_printf(TERR,
-				  "\nFW entry point (0x%08x) should be between",
-				  binary_params.fw_ep);
-			my_printf(TERR,
-				  " the FW load address (0x%08x) ",
-				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  "and FW length (0x%08x).\n",
-				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
-			return FALSE;
-		}
-	}
-
-	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-		(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
-		if (((binary_params.bin_params & BIN_FW_ENTRY_POINT) ==
-								0x00000000) &&
-			((binary_params.bin_params &
-			  BIN_FW_LOAD_START_ADDR) != 0x00000000)) {
-			binary_params.fw_ep =
-					binary_params.fw_load_addr;
-		} else {
-			my_printf(TERR,
-				  "\nFW entry point (0x%08x) should be ",
-				  binary_params.fw_ep);
-			my_printf(TERR,
-				  "\between the FW load address (0x%08x)",
-				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  " and FW length (0x%08x).\n",
-				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
-			return FALSE;
-		}
-	}
-
-	/* Write the FW entry point */
-	if (!write_to_file(binary_params.fw_ep,
-			   HDR_FW_ENTRY_POINT_OFFSET,
-			   4,
-			   "HDR - FW Entry point		 "))
-		return FALSE;
-
-	/* Calculate the CRC end address. */
-	if ((binary_params.bin_params & BIN_FW_CKS_SIZE) == 0x00000000) {
-		/*
-		 * In case the size was not set, then CRC end address is
-		 * the size of the binary file.
-		 */
-		binary_params.fw_err_detec_e_addr =
-						binary_params.fw_len - 1;
-	} else {
-		/* CRC end address should be less than FW length. */
-		if (binary_params.fw_err_detec_e_addr >
-					(binary_params.fw_len - 1)) {
-			my_printf(TERR,
-				  "\nCRC end address (0x%08x) should be less ",
-				  binary_params.fw_err_detec_e_addr);
-			my_printf(TERR,
-				  "than the FW length %d (0x%08x)",
-				  (binary_params.fw_len),
-				  (binary_params.fw_len));
-			return FALSE;
-		}
-	}
-
-	/* Check CRC start and end addresses. */
-	if (binary_params.fw_err_detec_s_addr >
-					binary_params.fw_err_detec_e_addr) {
-		my_printf(TERR,
-			  "\nCRC start address (0x%08x) should be less or ",
-			  binary_params.fw_err_detec_s_addr);
-		my_printf(TERR,
-			  "equal to CRC end address (0x%08x)\nPlease check ",
-			  binary_params.fw_err_detec_e_addr);
-		my_printf(TERR,
-			  "CRC start address and CRC size arguments.");
-		return FALSE;
-	}
-
-	/* CRC start addr should be between the FW load address and RAM size */
-	if (binary_params.fw_err_detec_s_addr >
-				binary_params.fw_len) {
-		my_printf(TERR, "\nCRC start address (0x%08x) should ",
-			  binary_params.fw_err_detec_s_addr);
-		my_printf(TERR, "be FW length (0x%08x).",
-			  binary_params.fw_len);
-		return FALSE;
-	}
-
-	/* Write the CRC start address */
-	if (!write_to_file(binary_params.fw_err_detec_s_addr,
-			   HDR_FW_ERR_DETECT_START_ADDR_OFFSET,
-			   4,
-			   "HDR - FW CRC Start			 "))
-		return FALSE;
-
-	/* CRC end addr should be between the CRC start address and RAM size */
-	if ((binary_params.fw_err_detec_e_addr <
-				binary_params.fw_err_detec_s_addr) ||
-		(binary_params.fw_err_detec_e_addr >
-				binary_params.fw_len)) {
-		my_printf(TERR,
-			  "\nCRC end address (0x%08x) should be between the ",
-			  binary_params.fw_err_detec_e_addr);
-		my_printf(TERR,
-			  "CRC start address (0x%08x) and FW length (0x%08x).",
-			  binary_params.fw_err_detec_s_addr,
-			  binary_params.fw_len);
-		return FALSE;
-	}
-
-	/* Write the CRC end address */
-	if (!write_to_file(binary_params.fw_err_detec_e_addr,
-			   HDR_FW_ERR_DETECT_END_ADDR_OFFSET,
-			   4,
-			   "HDR - FW CRC End			 "))
-		return FALSE;
-
-	/* Let the FW length to be aligned to 16 */
-	tmp_param = binary_params.fw_len % 16;
-	if (tmp_param)
-		binary_params.fw_len += (16 - tmp_param);
-
-	/* FW load address + FW length should be less than the RAM size. */
-	if ((binary_params.fw_load_addr +
-			binary_params.fw_len) >
-					(g_ram_start_address + g_ram_size)) {
-		my_printf(TERR,
-			  "\nFW load address + FW length should (0x%08x) be ",
-			  (binary_params.fw_load_addr + binary_params.fw_len));
-		my_printf(TERR,
-			  "less than the RAM size (0x%08x).",
-			  (g_ram_start_address + g_ram_size));
-		return FALSE;
-	}
-
-	/* Write the FW length */
-	if (!write_to_file(binary_params.fw_len,
-			   HDR_FW_LENGTH_OFFSET,
-			   4,
-			   "HDR - FW Length			   "))
-		return FALSE;
-
-	/* Write the SPI flash MAX clock. */
-	switch (binary_params.flash_size) {
-	case FLASH_SIZE_1_MBYTES_VAL:
-		tmp_param = FLASH_SIZE_1_MBYTES;
-		break;
-	case FLASH_SIZE_2_MBYTES_VAL:
-		tmp_param = FLASH_SIZE_2_MBYTES;
-		break;
-	case FLASH_SIZE_4_MBYTES_VAL:
-		tmp_param = FLASH_SIZE_4_MBYTES;
-		break;
-	case FLASH_SIZE_8_MBYTES_VAL:
-		tmp_param = FLASH_SIZE_8_MBYTES;
-		break;
-	case FLASH_SIZE_16_MBYTES_VAL:
-		tmp_param = FLASH_SIZE_16_MBYTES;
-		break;
-	default:
-		my_printf(TERR, "\n\nInvalid Flash size (%d MBytes) -",
-				  binary_params.flash_size);
-		my_printf(TERR, " it should be 1, 2, 4, 8 or 16 MBytes\n");
-		return FALSE;
-	}
-	if (!write_to_file(tmp_param,
-			   HDR_FLASH_SIZE_OFFSET,
-			   1,
-			   "HDR - Flash size			 "))
-
-		return FALSE;
-
-	/* Write the reserved bytes. */
-	if (!write_to_file(PAD_VALUE, HDR_RESERVED, 26,
-					   "HDR - Reserved (26 bytes)	  "))
-		return FALSE;
-
-
-	/* Refresh the FW header bin file in order to calculate CRC */
-	if (g_hfd_pointer) {
-		fclose(g_hfd_pointer);
-		g_hfd_pointer = fopen(g_hdr_input_name, "r+b");
-		if (g_hfd_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s\n\n",
-				  input_file_name);
-			return FALSE;
-		}
-	}
-
-	/* Calculate the FW header CRC */
-	if ((binary_params.bin_params & BIN_FW_HDR_CRC_DISABLE) == 0) {
-		/* Calculate ... */
-		g_calc_type = CALC_TYPE_CRC;
-		if (!calc_header_crc_bin(&binary_params.hdr_crc))
-			return FALSE;
-
-		g_calc_type = CALC_TYPE_NONE;
-	} else
-		binary_params.hdr_crc = 0;
-
-	/* Write FW header CRC to header file */
-	if (!write_to_file(binary_params.hdr_crc,
-			   HDR_FW_HEADER_SIG_OFFSET,
-			   4,
-			   "HDR - Header CRC				"))
-		return FALSE;
-
-	/* Calculate the FW	 CRC */
-	if ((binary_params.bin_params & BIN_FW_CRC_DISABLE) == 0) {
-		/* Calculate ... */
-		g_calc_type = CALC_TYPE_CRC;
-		if (!calc_firmware_csum_bin(&binary_params.fw_crc,
-			(bin_fw_offset +
-				binary_params.fw_err_detec_s_addr),
-			(binary_params.fw_err_detec_e_addr -
-				binary_params.fw_err_detec_s_addr+1)))
-			return FALSE;
-
-		g_calc_type = CALC_TYPE_NONE;
-	} else
-		binary_params.fw_crc = 0;
-
-	/* Write the FW CRC into file header file */
-	if (!write_to_file(binary_params.fw_crc,
-			   HDR_FW_IMAGE_SIG_OFFSET,
-			   4,
-			   "HDR - FW CRC				   "))
-		return FALSE;
-
-	/* Close if needed... */
-	if (input_file_pointer) {
-		fclose(input_file_pointer);
-		input_file_pointer = NULL;
-	}
-
-	if (g_hfd_pointer) {
-		fclose(g_hfd_pointer);
-		g_hfd_pointer = NULL;
-	}
-
-	/* Create empty output file. */
-	output_file_pointer = fopen(output_file_name, "wb");
-	if (output_file_pointer)
-		fclose(output_file_pointer);
-
-	if ((binary_params.bin_params & BIN_FW_HDR_OFFSET) != 0) {
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
-				  SEEK_SET);
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  binary_params.fw_hdr_offset,
-				  SEEK_SET);
-	} else {
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  0,
-				  SEEK_END);
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
-				  SEEK_END);
-	}
-
-	my_printf(TINF, "\n\n");
-
-	return TRUE;
-}
-
-/*******************************************************************
- * Function:	calc_header_crc_bin
- * Parameters:	unsigned short header checksum (O)
- *		unsigned int header offset from first byte in
- *		the binary (I)
- * Return:	TRUE if successful
- * Description:	 Go thru bin file and calculate checksum
- *******************************************************************
- */
-int calc_header_crc_bin(unsigned int *p_cksum)
-{
-	int i;
-	unsigned int calc_header_checksum_crc = 0;
-	unsigned char g_header_array[HEADER_SIZE];
-	int line_print_size = 32;
-
-	init_calculation(&calc_header_checksum_crc);
-
-	/* Go thru the BIN File and calculate the Checksum */
-	if (fseek(g_hfd_pointer, 0x00000000, SEEK_SET) < 0)
-		return FALSE;
-
-	if (fread(g_header_array,
-		  HEADER_SIZE,
-		  1,
-		  g_hfd_pointer) != 1)
-		return FALSE;
-
-	for (i = 0; i < (HEADER_SIZE - HEADER_CRC_FIELDS_SIZE); i++) {
-
-		/*
-		 * I had once the Verbose check inside the my_printf, but
-		 * it made ECST run sloooowwwwwly....
-		 */
-		if (g_verbose == SUPER_VERBOSE) {
-			if (i%line_print_size == 0)
-				my_printf(TDBG, "\n[%.4x]: ", i);
-
-			my_printf(TDBG, "%.2x ", g_header_array[i]);
-		}
-
-		update_calculation(&calc_header_checksum_crc,
-				   g_header_array[i]);
-
-		if (g_verbose == SUPER_VERBOSE) {
-			if ((i + 1) % line_print_size == 0)
-				my_printf(TDBG,
-					  "FW Header ChecksumCRC = %.8x",
-					   calc_header_checksum_crc);
-
-		}
-	}
-
-	finalize_calculation(&calc_header_checksum_crc);
-	*p_cksum = calc_header_checksum_crc;
-
-	return TRUE;
-}
-
-/*
- *******************************************************************
- * Function:	 calc_firmware_csum_bin
- * Parameters:	 unsigned int fwStart (I)
- *				 unsigned int firmware size in words (I)
- *				 unsigned int - firmware checksum (O)
- * Return:
- * Description:	 TBD
- *******************************************************************
- */
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length)
-{
-
-	unsigned int i;
-	unsigned int calc_read_bytes;
-	unsigned int calc_num_of_bytes_to_read;
-	unsigned int calc_curr_position;
-	unsigned int calc_fw_checksum_crc = 0;
-	unsigned char g_fw_array[BUFF_SIZE];
-	int line_print_size = 32;
-
-	calc_num_of_bytes_to_read = fw_length;
-	calc_curr_position = fw_offset;
-
-	if (g_verbose == REGULAR_VERBOSE) {
-		my_printf(TINF,
-			  "\nFW Error Detect Start Dddress: 0x%08x",
-			  calc_curr_position);
-		my_printf(TINF,
-			  "\nFW Error Detect End Dddress: 0x%08x",
-			  calc_curr_position + calc_num_of_bytes_to_read - 1);
-		my_printf(TINF,
-			  "\nFW Error Detect Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
-	}
-
-	init_calculation(&calc_fw_checksum_crc);
-
-	while (calc_num_of_bytes_to_read > 0) {
-		if (calc_num_of_bytes_to_read > BUFF_SIZE)
-			calc_read_bytes = BUFF_SIZE;
-		else
-			calc_read_bytes = calc_num_of_bytes_to_read;
-
-		if (fseek(input_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
-			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  input_file_pointer) != 1)
-			return 0;
-
-		for (i = 0; i < calc_read_bytes; i++) {
-			/*
-			 * I had once the Verbose check inside the my_printf,
-			 * but it made ECST run sloooowwwwwly....
-			 */
-			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-						  "\n[%.4x]: ",
-						  calc_curr_position + i);
-
-				my_printf(TDBG, "%.2x ", g_fw_array[i]);
-			}
-
-			update_calculation(&calc_fw_checksum_crc,
-					   g_fw_array[i]);
-
-			if (g_verbose == SUPER_VERBOSE) {
-				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
-						  calc_fw_checksum_crc);
-			}
-		}
-		calc_num_of_bytes_to_read -= calc_read_bytes;
-		calc_curr_position += calc_read_bytes;
-	} /* end of while(calc_num_of_bytes_to_read > 0) */
-
-	finalize_calculation(&calc_fw_checksum_crc);
-	*p_cksum = calc_fw_checksum_crc;
-
-	return TRUE;
-}
-
-/*
- ***************************************************************************
- *			"bh" mode Handler
- ***************************************************************************
- */
-
-/*
- *******************************************************************
- * Function:	 main_hdr
- * Parameters:	 TBD
- * Return:	 True for success
- * Description:
- *******************************************************************
- */
-int main_hdr(void)
-{
-	int result = 0;
-	char tmp_file_name[NAME_SIZE + 1];
-	unsigned int tmp_long_val;
-	unsigned int bin_file_size_bytes;
-
-	tmp_file_name[NAME_SIZE] = '\0';
-
-	if (is_ptr_merge) {
-		if (strlen(input_file_name) == 0) {
-			my_printf(TERR, "\n\nNo input BIN file selected for");
-			my_printf(TERR, " BootLoader header file.\n\n");
-			return FALSE;
-		}
-
-		if (strlen(output_file_name) == 0)
-			strncpy(tmp_file_name,
-				input_file_name,
-				sizeof(tmp_file_name) - 1);
-		else {
-			copy_file_to_file(output_file_name,
-					  input_file_name,
-					  0,
-					  SEEK_END);
-			strncpy(tmp_file_name,
-				output_file_name,
-				sizeof(tmp_file_name) - 1);
-		}
-
-		/* Open Header file */
-		g_hdr_pointer = fopen(tmp_file_name, "r+b");
-		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
-				  tmp_file_name);
-			return FALSE;
-		}
-
-		bin_file_size_bytes = get_file_length(g_hdr_pointer);
-
-		/* Offset should be less than file size. */
-		if (fw_offset > bin_file_size_bytes) {
-			my_printf(TERR,
-				  "\n\nFW offset 0x%08x should be less than ",
-				  fw_offset);
-			my_printf(TERR,
-				  "file size 0x%x (%d).\n\n",
-				  bin_file_size_bytes, bin_file_size_bytes);
-			 return FALSE;
-		}
-
-		/* FW table should be less than file size. */
-		if (ptr_fw_addr > bin_file_size_bytes) {
-			my_printf(TERR, "\n\nFW table 0x%08x should be less ",
-				  ptr_fw_addr);
-			my_printf(TERR, "than file size 0x%x (%d).\n\n",
-				bin_file_size_bytes, bin_file_size_bytes);
-			return FALSE;
-		}
-
-		if (fseek(g_hdr_pointer, fw_offset, SEEK_SET) < 0)
-			return FALSE;
-
-		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
-
-		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
-				  tmp_file_name);
-			my_printf(TINF,
-				  " Offset: 0x%08X,  Signature: 0x%08X,",
-				  fw_offset, HDR_PTR_SIGNATURE);
-			my_printf(TINF,
-				  " Pointer: 0x%08X\n",
-				  ptr_fw_addr);
-		} else {
-			my_printf(TERR,
-				  "\n\nCouldn't write signature (%x) and "
-				  "pointer to BootLoader header file (%s)\n\n",
-				  tmp_long_val, tmp_file_name);
-			return FALSE;
-		}
-
-	} else {
-
-		if (strlen(output_file_name) == 0) {
-			my_printf(TERR, "\n\nNo output file selected ");
-			my_printf(TERR, "for BootLoader header file.\n\n");
-			return FALSE;
-		}
-
-		/* Open Output file */
-		g_hdr_pointer = fopen(output_file_name, "w+b");
-		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
-				  output_file_name);
-			return FALSE;
-		}
-
-		if (fseek(g_hdr_pointer, 0L, SEEK_SET) < 0)
-			return FALSE;
-
-		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
-
-		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
-				  output_file_name);
-			my_printf(TINF,
-				  "     Signature: 0x%08X,   Pointer: 0x%08X\n",
-				  HDR_PTR_SIGNATURE,
-				  ptr_fw_addr);
-		} else {
-			my_printf(TERR,
-				  "\n\nCouldn't write signature (%x) and ",
-				  tmp_long_val);
-			my_printf(TERR,
-				  "pointer to BootLoader header file (%s)\n\n",
-				  output_file_name);
-			return FALSE;
-		}
-
-	}
-
-	/* Close if needed... */
-	if (g_hdr_pointer) {
-		fclose(g_hdr_pointer);
-		g_hdr_pointer = NULL;
-	}
-
-	return TRUE;
-}
-
-/*
- ***************************************************************************
- *		"api" mode Handler
- ***************************************************************************
- */
-
-/*
- *******************************************************************
- * Function:		main_api
- * Parameters:		TBD
- * Return:			True for success
- * Description:
- *	TBD
- *******************************************************************
- */
-int main_api(void)
-{
-	char tmp_file_name[NAME_SIZE + 1];
-	int result = 0;
-	unsigned int crc_checksum;
-
-	tmp_file_name[NAME_SIZE] = '\0';
-	api_file_size_bytes = 0;
-
-	/* If API input file was not declared, then print error message. */
-	if (strlen(input_file_name) == 0) {
-		my_printf(TERR,
-			"\n\nNeed to define API input file, using -i flag\n\n");
-		return FALSE;
-
-	}
-
-	if (strlen(output_file_name) == 0) {
-		if (!splice_into_path(tmp_file_name, input_file_name,
-			sizeof(tmp_file_name), "api_"))
-			return FALSE;
-	} else
-		strncpy(tmp_file_name, output_file_name,
-			sizeof(tmp_file_name) - 1);
-
-	/* Make sure that new empty file is created. */
-	api_file_pointer = fopen(tmp_file_name, "w");
-	if (api_file_pointer == NULL) {
-		my_printf(TERR, "\n\nCannot open %s\n\n", tmp_file_name);
-		return FALSE;
-	}
-	fclose(api_file_pointer);
-
-	copy_file_to_file(tmp_file_name, input_file_name, 0, SEEK_END);
-
-	/* Open API input file */
-	api_file_pointer = fopen(tmp_file_name, "r+b");
-	if (api_file_pointer == NULL) {
-		my_printf(TERR, "\n\nCannot open %s\n\n", tmp_file_name);
-		return FALSE;
-	}
-
-	/*
-	 * Check Binary file size, this file contain the image itself,
-	 * without any header.
-	 */
-	api_file_size_bytes = get_file_length(api_file_pointer);
-	if (api_file_size_bytes < 0)
-		return FALSE;
-	my_printf(TINF,
-		  "\nAPI file: %s, size: %d bytes (0x%x)\n",
-		  tmp_file_name,
-		  api_file_size_bytes,
-		  api_file_size_bytes);
-
-	crc_checksum = calc_api_csum_bin();
-
-	if (fseek(api_file_pointer, api_file_size_bytes, SEEK_SET) < 0)
-		return FALSE;
-
-	result = (int)(fwrite(&crc_checksum,
-			      4,
-			      1,
-			      api_file_pointer));
-
-	if (result)
-		my_printf(TINF,
-			  "\nIn API BIN file - Offset 0x%08X - value 0x%08X",
-			  api_file_size_bytes,
-			  crc_checksum);
-	else {
-		my_printf(TERR,
-			  "\n\nCouldn't write %x to API BIN file at %08x\n\n",
-			  crc_checksum, api_file_size_bytes);
-		return FALSE;
-	}
-
-	/* Close if needed... */
-	if (api_file_pointer) {
-		fclose(api_file_pointer);
-		api_file_pointer = NULL;
-	}
-
-	return TRUE;
-}
-
-
-/*
- *******************************************************************
- * Function: calc_api_csum_bin
- * Parameters:
- *
- * Return: Return the CRC \ checksum, or "0" in case of fail.
- * Description:	 TBD
- *******************************************************************
-*/
-unsigned int calc_api_csum_bin(void)
-{
-
-	unsigned int i;
-	unsigned int calc_read_bytes;
-	int calc_num_of_bytes_to_read;
-	unsigned int calc_curr_position;
-	unsigned int calc_fw_checksum_crc = 0;
-	unsigned char g_fw_array[BUFF_SIZE];
-	int line_print_size = 32;
-
-	calc_num_of_bytes_to_read = api_file_size_bytes;
-	calc_curr_position = 0;
-
-	if (g_verbose == SUPER_VERBOSE) {
-		my_printf(TDBG,
-			  "\nAPI CRC \\ Checksum First Byte Address: 0x%08x",
-			  calc_curr_position);
-		my_printf(TDBG,
-			  "\nAPI CRC \\ Checksum Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
-	}
-
-	init_calculation(&calc_fw_checksum_crc);
-
-	while (calc_num_of_bytes_to_read > 0) {
-		if (calc_num_of_bytes_to_read > BUFF_SIZE)
-			calc_read_bytes = BUFF_SIZE;
-		else
-			calc_read_bytes = calc_num_of_bytes_to_read;
-
-		if (fseek(api_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
-			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  api_file_pointer) != 1)
-			return 0;
-
-		for (i = 0; i < calc_read_bytes; i++) {
-			/*
-			 * I had once the Verbose check inside the my_printf,
-			 * but it made ecst run sloooowwwwwly....
-			 */
-			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-					"\n[%.4x]: ",
-					calc_curr_position + i);
-
-				my_printf(TDBG, "%.2x ", g_fw_array[i]);
-			}
-
-			update_calculation(&calc_fw_checksum_crc,
-					   g_fw_array[i]);
-
-			if (g_verbose == SUPER_VERBOSE) {
-				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
-						  calc_fw_checksum_crc);
-			}
-		}
-		calc_num_of_bytes_to_read -= calc_read_bytes;
-		calc_curr_position += calc_read_bytes;
-	} /* end of while(calc_num_of_bytes_to_read > 0) */
-
-	finalize_calculation(&calc_fw_checksum_crc);
-
-	return calc_fw_checksum_crc;
-
-}
-
-/*
- **************************************************************************
- *			CRC Handler
- **************************************************************************
-*/
-
-/*
- *******************************************************************
- *
- * #define P_xxxx
- *
- * The CRC's are computed using polynomials. The  coefficients
- * for the algorithms are defined by the following constants.
- *
- *******************************************************************
- */
-
-#define P_32        0xEDB88320L
-
-/*
- *******************************************************************
- *
- *	static int crc_tab...init
- *	static unsigned ... crc_tab...[]
- *
- *	The algorithms use tables with pre-calculated  values.  This
- *	speeds	up	the calculation dramatically. The first time the
- *	CRC function is called, the table for that specific	 calcu-
- *	lation	is set up. The ...init variables are used to deter-
- *	mine if the initialization has taken place. The	 calculated
- *	values are stored in the crc_tab... arrays.
- *
- *	The variables are declared static. This makes them invisible
- *	for other modules of the program.
- *
- *******************************************************************
- */
-static int crc_tab32_init = FALSE;
-static unsigned int crc_tab32[256];
-
-/*
- ********************************************************************
- *
- *	static void init_crc...tab();
- *
- *	Three local functions are used to initialize the tables
- *	with values for the algorithm.
- *
- *******************************************************************
- */
-
-static void init_crc32_tab(void);
-
-/*
- *******************************************************************
- *
- * unsigned int initialize_crc_32( void );
- *
- * The function update_crc_32 calculates a new  CRC-32  value
- * based  on  the previous value of the CRC and the next byte
- * of the data to be checked.
- *
- *******************************************************************
- */
-
-unsigned int initialize_crc_32(void)
-{
-	return 0xffffffffL;
-}  /* initialize_crc_32 */
-
-/*
- *******************************************************************
- *
- * unsigned int update_crc_32( unsigned int crc, char c );
- *
- * The function update_crc_32 calculates a new  CRC-32  value
- * based  on  the previous value of the CRC and the next byte
- * of the data to be checked.
- *
- *******************************************************************
- */
-
-unsigned int update_crc_32(unsigned int crc, char c)
-{
-
-	unsigned int tmp, long_c;
-
-	long_c = 0x000000ffL & (unsigned int)c;
-
-	if (!crc_tab32_init)
-		init_crc32_tab();
-
-	tmp = crc ^ long_c;
-	crc = (crc >> 8) ^ crc_tab32[tmp & 0xff];
-
-	return crc;
-
-}  /* update_crc_32 */
-
-/*
- *******************************************************************
- *
- *	static void init_crc32_tab( void );
- *
- *	The function init_crc32_tab() is used  to  fill the  array
- *	for calculation of the CRC-32 with values.
- *
- *******************************************************************
- */
-static void init_crc32_tab(void)
-{
-
-	int i, j;
-	unsigned int crc;
-
-	for (i = 0; i < 256; i++) {
-
-		crc = (unsigned int)i;
-
-		for (j = 0; j < 8; j++) {
-
-			if (crc & 0x00000001L)
-				crc = (crc >> 1) ^ P_32;
-			else
-				crc = crc >> 1;
-		}
-
-		crc_tab32[i] = crc;
-	}
-
-	crc_tab32_init = TRUE;
-
-}  /* init_crc32_tab */
-
-/*
- *******************************************************************
- *
- * unsigned int finalize_crc_32( unsigned int crc );
- *
- * The function finalize_crc_32 finalizes a  CRC-32 calculation
- * by performing a bit convolution (bit 0 is bit 31, etc').
- *
- *******************************************************************
- */
-
-unsigned int finalize_crc_32(unsigned int crc)
-{
-
-	int i;
-	unsigned int result = 0;
-
-	for (i = 0; i < NUM_OF_BYTES; i++)
-		SET_VAR_BIT(result, NUM_OF_BYTES - (i+1), READ_VAR_BIT(crc, i));
-
-	return result;
-
-}  /* finalize_crc_32 */
-
diff --git a/util/ecst.h b/util/ecst.h
deleted file mode 100644
index 04d696c7c5..0000000000
--- a/util/ecst.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ECST_H
-#define ECST_H
-
-/*---------------------------------------------------------------------------
-  Includes
-  --------------------------------------------------------------------------*/
-
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-#include <curses.h>
-
-
-/*---------------------------------------------------------------------------
-  Defines
-  --------------------------------------------------------------------------*/
-
-/* For the beauty */
-#define TRUE                            1
-#define FALSE                           0
-
-/* CHANGEME when the version is updated */
-#define T_VER                           1
-#define T_REV_MAJOR                     0
-#define T_REV_MINOR                     3
-
-/* Header starts by default at 0x20000 */
-#define FIRMWARE_OFFSET_FROM_HEADER     0x40
-
-#define ARM_FW_ENTRY_POINT_OFFSET       0x04
-
-/* Some useful offsets inside the header */
-#define	HDR_ANCHOR_OFFSET                    0
-#define	HDR_EXTENDED_ANCHOR_OFFSET           4
-#define	HDR_SPI_MAX_CLK_OFFSET               6
-#define	HDR_SPI_READ_MODE_OFFSET             7
-#define	HDR_ERR_DETECTION_CONF_OFFSET        8
-#define	HDR_FW_LOAD_START_ADDR_OFFSET        9
-#define	HDR_FW_ENTRY_POINT_OFFSET            13
-#define	HDR_FW_ERR_DETECT_START_ADDR_OFFSET  17
-#define	HDR_FW_ERR_DETECT_END_ADDR_OFFSET    21
-#define	HDR_FW_LENGTH_OFFSET                 25
-#define	HDR_FLASH_SIZE_OFFSET                29
-#define HDR_RESERVED                         30
-#define	HDR_FW_HEADER_SIG_OFFSET             56
-#define HDR_FW_IMAGE_SIG_OFFSET              60
-
-
-#define FIRMW_CKSM_OFFSET               0x3C
-
-/* Header field known values */
-#define FW_HDR_ANCHOR                   0x2A3B4D5E
-#define FW_HDR_EXT_ANCHOR_ENABLE        0xAB1E
-#define FW_HDR_EXT_ANCHOR_DISABLE       0x54E1
-#define FW_CRC_DISABLE                  0x00
-#define FW_CRC_ENABLE                   0x02
-#define HEADER_CRC_FIELDS_SIZE          8
-
-#define HDR_PTR_SIGNATURE               0x55AA650E
-
-#define CKSMCRC_INV_BIT_OFFSET          0x1
-
-/* Some common Sizes */
-#define STR_SIZE                        200
-#define	ARG_SIZE                        100
-#define NAME_SIZE                       160
-#define BUFF_SIZE                       0x400
-#define HEADER_SIZE                     64
-#define TMP_STR_SIZE                    20
-#define PAD_VALUE                       0x00
-
-
-#define MAX_ARGS                        100
-
-/* Text Colors */
-#define TDBG                            0x02  /* Dark Green     */
-#define TPAS                            0x0A  /* light green    */
-#define TINF                            0x0B  /* light turquise */
-#define TERR                            0x0C  /* light red      */
-#define TUSG                            0x0E  /* light yellow   */
-
-/* Indicates bin Command line parameters */
-#define BIN_FW_HDR_CRC_DISABLE          0x0001
-#define BIN_FW_CRC_DISABLE              0x0002
-#define BIN_FW_START                    0x0004
-#define BIN_FW_SIZE                     0x0008
-#define BIN_CK_FIRMWARE                 0x0010
-#define BIN_FW_CKS_START                0x0020
-#define BIN_FW_CKS_SIZE                 0x0040
-#define BIN_FW_CHANGE_SIG               0x0080
-#define BIN_FW_SPI_MAX_CLK              0x0100
-#define BIN_FW_LOAD_START_ADDR          0x0200
-#define BIN_FW_ENTRY_POINT              0x0400
-#define BIN_FW_LENGTH                   0x0800
-#define BIN_FW_HDR_OFFSET               0x1000
-#define	BIN_FW_USER_ARM_RESET           0x2000
-#define BIN_UNLIM_BURST_ENABLE          0x4000
-
-#define ECRP_OFFSET                     0x01
-#define ECRP_INPUT_FILE                 0x02
-#define ECRP_OUTPUT_FILE                0x04
-
-#define SPI_MAX_CLOCK_20_MHZ_VAL        20
-#define SPI_MAX_CLOCK_25_MHZ_VAL        25
-#define SPI_MAX_CLOCK_33_MHZ_VAL        33
-#define SPI_MAX_CLOCK_40_MHZ_VAL        40
-#define SPI_MAX_CLOCK_50_MHZ_VAL        50
-
-#define SPI_MAX_CLOCK_20_MHZ            0x00
-#define SPI_MAX_CLOCK_25_MHZ            0x01
-#define SPI_MAX_CLOCK_33_MHZ            0x02
-#define SPI_MAX_CLOCK_40_MHZ            0x03
-#define SPI_MAX_CLOCK_50_MHZ            0x04
-#define SPI_MAX_CLOCK_MASK              0xF8
-
-#define SPI_CLOCK_RATIO_1_VAL           1
-#define SPI_CLOCK_RATIO_2_VAL           2
-
-#define SPI_CLOCK_RATIO_1               0x07
-#define SPI_CLOCK_RATIO_2               0x08
-
-#define SPI_NORMAL_MODE_VAL             "normal"
-#define SPI_SINGLE_MODE_VAL             "fast"
-#define SPI_DUAL_MODE_VAL               "dual"
-#define SPI_QUAD_MODE_VAL               "quad"
-
-#define SPI_NORMAL_MODE                 0x00
-#define SPI_SINGLE_MODE                 0x01
-#define SPI_DUAL_MODE                   0x03
-#define SPI_QUAD_MODE                   0x04
-
-#define SPI_UNLIMITED_BURST_ENABLE      0x08
-
-#define FLASH_SIZE_1_MBYTES_VAL         1
-#define FLASH_SIZE_2_MBYTES_VAL         2
-#define FLASH_SIZE_4_MBYTES_VAL         4
-#define FLASH_SIZE_8_MBYTES_VAL         8
-#define FLASH_SIZE_16_MBYTES_VAL        16
-
-#define FLASH_SIZE_1_MBYTES             0x01
-#define FLASH_SIZE_2_MBYTES             0x03
-#define FLASH_SIZE_4_MBYTES             0x07
-#define FLASH_SIZE_8_MBYTES             0x0F
-#define FLASH_SIZE_16_MBYTES            0x1F
-
-/* Header fields default values. */
-#define SPI_MAX_CLOCK_DEFAULT           SPI_MAX_CLOCK_20_MHZ_VAL
-#define SPI_READ_MODE_DEFAULT           SPI_NORMAL_MODE
-#define FLASH_SIZE_DEFAULT              FLASH_SIZE_16_MBYTES_VAL
-#define	FW_CRC_START_ADDR               0x00000000
-
-#define ADDR_16_BYTES_ALIGNED_MASK      0x0000000F
-#define ADDR_4_BYTES_ALIGNED_MASK       0x00000003
-
-#define MAX_FLASH_SIZE                  0x03ffffff
-
-/* Chips: convert from name to index. */
-enum npcx_chip_ram_variant {
-	NPCX5M5G = 0,
-	NPCX5M6G = 1,
-	NPCX7M5 = 2,
-	NPCX7M6 = 3,
-	NPCX7M7 = 4,
-	NPCX9M3 = 5,
-	NPCX9M6 = 6,
-	NPCX_CHIP_RAM_VAR_NONE
-};
-
-#define DEFAULT_CHIP                    NPCX5M5G
-
-/* NPCX5 */
-#define NPCX5M5G_RAM_ADDR               0x100A8000
-#define NPCX5M5G_RAM_SIZE               0x20000
-#define NPCX5M6G_RAM_ADDR               0x10088000
-#define NPCX5M6G_RAM_SIZE               0x40000
-/* NPCX7 */
-#define NPCX7M5X_RAM_ADDR               0x100A8000
-#define NPCX7M5X_RAM_SIZE               0x20000
-#define NPCX7M6X_RAM_ADDR               0x10090000
-#define NPCX7M6X_RAM_SIZE               0x40000
-#define NPCX7M7X_RAM_ADDR               0x10070000
-#define NPCX7M7X_RAM_SIZE               0x60000
-/* NPCX9 */
-#define NPCX9M3X_RAM_ADDR               0x10080000
-#define NPCX9M3X_RAM_SIZE               0x50000
-#define NPCX9M6X_RAM_ADDR               0x10090000
-#define NPCX9M6X_RAM_SIZE               0x40000
-
-/*---------------------------------------------------------------------------
-  Typedefs
-  --------------------------------------------------------------------------*/
-
-/* Parameters for Binary manipulation */
-struct tbinparams {
-	unsigned int	anchor;
-	unsigned short	ext_anchor;
-	unsigned char	spi_max_clk;
-	unsigned char	spi_clk_ratio;
-	unsigned char	spi_read_mode;
-	unsigned char	err_detec_cnf;
-	unsigned int	fw_load_addr;
-	unsigned int	fw_ep;
-	unsigned int	fw_err_detec_s_addr;
-	unsigned int	fw_err_detec_e_addr;
-	unsigned int	fw_len;
-	unsigned int	flash_size;
-	unsigned int	hdr_crc;
-	unsigned int	fw_crc;
-	unsigned int	fw_hdr_offset;
-	unsigned int	bin_params;
-} bin_params_struct;
-
-enum verbose_level {
-	NO_VERBOSE = 0,
-	REGULAR_VERBOSE,
-	SUPER_VERBOSE
-};
-
-enum calc_type {
-	CALC_TYPE_NONE	= 0,
-	CALC_TYPE_CHECKSUM ,
-	CALC_TYPE_CRC
-};
-
-struct chip_info {
-	unsigned int	ram_addr;
-	unsigned int   ram_size;
-} chip_info_struct;
-
-/*------------------------------------------------------------------------*/
-/* CRC Variable bit operation macros                                      */
-/*------------------------------------------------------------------------*/
-#define NUM_OF_BYTES					32
-#define READ_VAR_BIT(var, nb)			(((var) >> (nb)) & 0x1)
-#define SET_VAR_BIT(var, nb, val)		((var) |= ((val)<<(nb)))
-
-/*---------------------------------------------------------------------------
-  Functions Declaration
-  --------------------------------------------------------------------------*/
-
-/* main manipulation */
-int main_bin(struct tbinparams binary_parameters);
-int main_api(void);
-int main_hdr(void);
-
-/* General Checksum\CRC calculation */
-void init_calculation(unsigned int *check_sum_crc);
-void finalize_calculation(unsigned int *check_sum_crc);
-void update_calculation_information(unsigned char crc_con_dat);
-
-
-/* Checksum calculation etc. (BIN Specific) */
-int calc_header_crc_bin(unsigned int *pointer_header_checksum);
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length);
-
-/* Checksum calculation etc. (ERP Specific) */
-int calc_erp_csum_bin(unsigned short *region_pointer_header_checksum,
-					  unsigned int region_pointer_ofs);
-
-/* No words - General */
-void exit_with_usage(void);
-int copy_file_to_file(char *dst_file_name,
-					  char *src_file_name,
-					  int offset,
-					  int origin);
-int write_to_file(unsigned int write_value,
-				  unsigned int offset,
-				  unsigned char num_of_bytes,
-				  char *print_string);
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string);
-
-/* Nice Particular Printf - General */
-__attribute__((__format__(__printf__, 2, 3)))
-void my_printf(int error_level, char *fmt, ...);
-
-int str_cmp_no_case(const char *s1, const char *s2);
-int get_file_length(FILE *stream);
-
-#endif /* ECST_H */
diff --git a/util/ectool.c b/util/ectool.c
deleted file mode 100644
index c4a3401d59..0000000000
--- a/util/ectool.c
+++ /dev/null
@@ -1,10964 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <errno.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <signal.h>
-#include <stdbool.h>
-
-#include "battery.h"
-#include "comm-host.h"
-#include "chipset.h"
-#include "compile_time_macros.h"
-#include "crc.h"
-#include "cros_ec_dev.h"
-#include "ec_panicinfo.h"
-#include "ec_flash.h"
-#include "ec_version.h"
-#include "ectool.h"
-#include "i2c.h"
-#include "lightbar.h"
-#include "lock/gec_lock.h"
-#include "misc_util.h"
-#include "panic.h"
-#include "usb_pd.h"
-
-/* Maximum flash size (16 MB, conservative) */
-#define MAX_FLASH_SIZE 0x1000000
-
-/*
- * Calculate the expected response for a hello ec command.
- */
-#define HELLO_RESP(in_data) ((in_data) + 0x01020304)
-
-/* Command line options */
-enum {
-	OPT_DEV = 1000,
-	OPT_INTERFACE,
-	OPT_NAME,
-	OPT_ASCII,
-	OPT_I2C_BUS,
-};
-
-static struct option long_opts[] = {
-	{"dev", 1, 0, OPT_DEV},
-	{"interface", 1, 0, OPT_INTERFACE},
-	{"name", 1, 0, OPT_NAME},
-	{"ascii", 0, 0, OPT_ASCII},
-	{"i2c_bus", 1, 0, OPT_I2C_BUS},
-	{NULL, 0, 0, 0}
-};
-
-#define GEC_LOCK_TIMEOUT_SECS	30  /* 30 secs */
-
-const char help_str[] =
-	"Commands:\n"
-	"  adcread <channel>\n"
-	"      Read an ADC channel.\n"
-	"  addentropy [reset]\n"
-	"      Add entropy to device secret\n"
-	"  apreset\n"
-	"      Issue AP reset\n"
-	"  autofanctrl <on>\n"
-	"      Turn on automatic fan speed control.\n"
-	"  backlight <enabled>\n"
-	"      Enable/disable LCD backlight\n"
-	"  basestate [attach | detach | reset]\n"
-	"      Manually force base state to attached, detached or reset.\n"
-	"  battery\n"
-	"      Prints battery info\n"
-	"  batterycutoff [at-shutdown]\n"
-	"      Cut off battery output power\n"
-	"  batteryparam\n"
-	"      Read or write board-specific battery parameter\n"
-	"  boardversion\n"
-	"      Prints the board version\n"
-	"  button [vup|vdown|rec] <Delay-ms>\n"
-	"      Simulates button press.\n"
-	"  cbi\n"
-	"      Get/Set/Remove Cros Board Info\n"
-	"  chargecurrentlimit\n"
-	"      Set the maximum battery charging current\n"
-	"  chargecontrol\n"
-	"      Force the battery to stop charging or discharge\n"
-	"  chargeoverride\n"
-	"      Overrides charge port selection logic\n"
-	"  chargestate\n"
-	"      Handle commands related to charge state v2 (and later)\n"
-	"  chipinfo\n"
-	"      Prints chip info\n"
-	"  cmdversions <cmd>\n"
-	"      Prints supported version mask for a command number\n"
-	"  console\n"
-	"      Prints the last output to the EC debug console\n"
-	"  cec\n"
-	"      Read or write CEC messages and settings\n"
-	"  echash [CMDS]\n"
-	"      Various EC hash commands\n"
-	"  eventclear <mask>\n"
-	"      Clears EC host events flags where mask has bits set\n"
-	"  eventclearb <mask>\n"
-	"      Clears EC host events flags copy B where mask has bits set\n"
-	"  eventget\n"
-	"      Prints raw EC host event flags\n"
-	"  eventgetb\n"
-	"      Prints raw EC host event flags copy B\n"
-	"  eventgetscimask\n"
-	"      Prints SCI mask for EC host events\n"
-	"  eventgetsmimask\n"
-	"      Prints SMI mask for EC host events\n"
-	"  eventgetwakemask\n"
-	"      Prints wake mask for EC host events\n"
-	"  eventsetscimask <mask>\n"
-	"      Sets the SCI mask for EC host events\n"
-	"  eventsetsmimask <mask>\n"
-	"      Sets the SMI mask for EC host events\n"
-	"  eventsetwakemask <mask>\n"
-	"      Sets the wake mask for EC host events\n"
-	"  extpwrlimit\n"
-	"      Set the maximum external power limit\n"
-	"  fanduty <percent>\n"
-	"      Forces the fan PWM to a constant duty cycle\n"
-	"  flasherase <offset> <size>\n"
-	"      Erases EC flash\n"
-	"  flasheraseasync <offset> <size>\n"
-	"      Erases EC flash asynchronously\n"
-	"  flashinfo\n"
-	"      Prints information on the EC flash\n"
-	"  flashspiinfo\n"
-	"      Prints information on EC SPI flash, if present\n"
-	"  flashpd <dev_id> <port> <filename>\n"
-	"      Flash commands over PD\n"
-	"  flashprotect [now] [enable | disable]\n"
-	"      Prints or sets EC flash protection state\n"
-	"  flashread <offset> <size> <outfile>\n"
-	"      Reads from EC flash to a file\n"
-	"  flashwrite <offset> <infile>\n"
-	"      Writes to EC flash from a file\n"
-	"  forcelidopen <enable>\n"
-	"      Forces the lid switch to open position\n"
-	"  fpcontext\n"
-	"      Sets the fingerprint sensor context\n"
-	"  fpencstatus\n"
-	"      Prints status of Fingerprint sensor encryption engine\n"
-	"  fpframe\n"
-	"      Retrieve the finger image as a PGM image\n"
-	"  fpinfo\n"
-	"      Prints information about the Fingerprint sensor\n"
-	"  fpmode [mode... [capture_type]]\n"
-	"      Configure/Read the fingerprint sensor current mode\n"
-	"      mode: capture|deepsleep|fingerdown|fingerup|enroll|match|\n"
-	"            reset|reset_sensor|maintenance\n"
-	"      capture_type: vendor|pattern0|pattern1|qual|test_reset\n"
-	"  fpseed\n"
-	"      Sets the value of the TPM seed.\n"
-	"  fpstats\n"
-	"      Prints timing statisitcs relating to capture and matching\n"
-	"  fptemplate [<infile>|<index 0..2>]\n"
-	"      Add a template if <infile> is provided, else dump it\n"
-	"  gpioget <GPIO name>\n"
-	"      Get the value of GPIO signal\n"
-	"  gpioset <GPIO name>\n"
-	"      Set the value of GPIO signal\n"
-	"  hangdetect <flags> <event_msec> <reboot_msec> | stop | start\n"
-	"      Configure or start/stop the hang detect timer\n"
-	"  hello\n"
-	"      Checks for basic communication with EC\n"
-	"  hibdelay [sec]\n"
-	"      Set the delay before going into hibernation\n"
-	"  hostsleepstate\n"
-	"      Report host sleep state to the EC\n"
-	"  hostevent\n"
-	"      Get & set host event masks.\n"
-	"  i2cprotect <port> [status]\n"
-	"      Protect EC's I2C bus\n"
-	"  i2cread\n"
-	"      Read I2C bus\n"
-	"  i2cwrite\n"
-	"      Write I2C bus\n"
-	"  i2cxfer <port> <peripheral_addr> <read_count> [write bytes...]\n"
-	"      Perform I2C transfer on EC's I2C bus\n"
-	"  infopddev <port>\n"
-	"      Get info about USB type-C accessory attached to port\n"
-	"  inventory\n"
-	"      Return the list of supported features\n"
-	"  kbfactorytest\n"
-	"      Scan out keyboard if any pins are shorted\n"
-	"  kbid\n"
-	"      Get keyboard ID of supported keyboards\n"
-	"  kbinfo\n"
-	"      Dump keyboard matrix dimensions\n"
-	"  kbpress\n"
-	"      Simulate key press\n"
-	"  keyscan <beat_us> <filename>\n"
-	"      Test low-level key scanning\n"
-	"  led <name> <query | auto | off | <color> | <color>=<value>...>\n"
-	"      Set the color of an LED or query brightness range\n"
-	"  lightbar [CMDS]\n"
-	"      Various lightbar control commands\n"
-	"  mkbpget <buttons|switches>\n"
-	"      Get MKBP buttons/switches supported mask and current state\n"
-	"  mkbpwakemask <get|set> <event|hostevent> [mask]\n"
-	"      Get or Set the MKBP event wake mask, or host event wake mask\n"
-	"  motionsense [CMDS]\n"
-	"      Various motion sense control commands\n"
-	"  panicinfo\n"
-	"      Prints saved panic info\n"
-	"  pause_in_s5 [on|off]\n"
-	"      Whether or not the AP should pause in S5 on shutdown\n"
-	"  pchg [<port>]\n"
-	"      Get peripheral charge port count and status\n"
-	"  pdcontrol [suspend|resume|reset|disable|on]\n"
-	"      Controls the PD chip\n"
-	"  pdchipinfo <port>\n"
-	"      Get PD chip information\n"
-	"  pdlog\n"
-	"      Prints the PD event log entries\n"
-	"  pdwritelog <type> <port>\n"
-	"      Writes a PD event log of the given <type>\n"
-	"  pdgetmode <port>\n"
-	"      Get All USB-PD alternate SVIDs and modes on <port>\n"
-	"  pdsetmode <port> <svid> <opos>\n"
-	"      Set USB-PD alternate SVID and mode on <port>\n"
-	"  port80flood\n"
-	"      Rapidly write bytes to port 80\n"
-	"  port80read\n"
-	"      Print history of port 80 write\n"
-	"  powerinfo\n"
-	"      Prints power-related information\n"
-	"  protoinfo\n"
-	"       Prints EC host protocol information\n"
-	"  pse\n"
-	"      Get and set PoE PSE port power status\n"
-	"  pstoreinfo\n"
-	"      Prints information on the EC host persistent storage\n"
-	"  pstoreread <offset> <size> <outfile>\n"
-	"      Reads from EC host persistent storage to a file\n"
-	"  pstorewrite <offset> <infile>\n"
-	"      Writes to EC host persistent storage from a file\n"
-	"  pwmgetfanrpm [<index> | all]\n"
-	"      Prints current fan RPM\n"
-	"  pwmgetkblight\n"
-	"      Prints current keyboard backlight percent\n"
-	"  pwmgetnumfans\n"
-	"      Prints the number of fans present\n"
-	"  pwmgetduty\n"
-	"      Prints the current 16 bit duty cycle for given PWM\n"
-	"  pwmsetfanrpm <targetrpm>\n"
-	"      Set target fan RPM\n"
-	"  pwmsetkblight <percent>\n"
-	"      Set keyboard backlight in percent\n"
-	"  pwmsetduty\n"
-	"      Set 16 bit duty cycle of given PWM\n"
-	"  rand <num_bytes>\n"
-	"      generate <num_bytes> of random numbers\n"
-	"  readtest <patternoffset> <size>\n"
-	"      Reads a pattern from the EC via LPC\n"
-	"  reboot_ec <RO|RW|cold|hibernate|hibernate-clear-ap-off|disable-jump|cold-ap-off>"
-			" [at-shutdown|switch-slot]\n"
-	"      Reboot EC to RO or RW\n"
-	"  reboot_ap_on_g3 [<delay>]\n"
-	"      Requests that the EC will automatically reboot the AP after a\n"
-	"      configurable number of seconds the next time we enter the G3\n"
-	"      power state.\n"
-	"  rollbackinfo\n"
-	"      Print rollback block information\n"
-	"  rtcget\n"
-	"      Print real-time clock\n"
-	"  rtcgetalarm\n"
-	"      Print # of seconds before real-time clock alarm goes off.\n"
-	"  rtcset <time>\n"
-	"      Set real-time clock\n"
-	"  rtcsetalarm <sec>\n"
-	"      Set real-time clock alarm to go off in <sec> seconds\n"
-	"  rwhashpd <dev_id> <HASH[0] ... <HASH[4]>\n"
-	"      Set entry in PD MCU's device rw_hash table.\n"
-	"  rwsig <info|dump|action|status> ...\n"
-	"      info: get all info about rwsig\n"
-	"      dump: show individual rwsig field\n"
-	"      action: Control the behavior of RWSIG task.\n"
-	"      status: Run RW signature verification and get status.\n{"
-	"  rwsigaction (DEPRECATED; use \"rwsig action\")\n"
-	"      Control the behavior of RWSIG task.\n"
-	"  rwsigstatus (DEPRECATED; use \"rwsig status\"\n"
-	"      Run RW signature verification and get status.\n"
-	"  sertest\n"
-	"      Serial output test for COM2\n"
-	"  smartdischarge\n"
-	"      Set/Get smart discharge parameters\n"
-	"  stress [reboot] [help]\n"
-	"      Stress test the ec host command interface.\n"
-	"  sysinfo [flags|reset_flags|firmware_copy]\n"
-	"      Display system info.\n"
-	"  switches\n"
-	"      Prints current EC switch positions\n"
-	"  temps <sensorid>\n"
-	"      Print temperature.\n"
-	"  tempsinfo <sensorid>\n"
-	"      Print temperature sensor info.\n"
-	"  thermalget <platform-specific args>\n"
-	"      Get the threshold temperature values from the thermal engine.\n"
-	"  thermalset <platform-specific args>\n"
-	"      Set the threshold temperature values for the thermal engine.\n"
-	"  tpselftest\n"
-	"      Run touchpad self test.\n"
-	"  tpframeget\n"
-	"      Get touchpad frame data.\n"
-	"  tmp006cal <tmp006_index> [params...]\n"
-	"      Get/set TMP006 calibration\n"
-	"  tmp006raw <tmp006_index>\n"
-	"      Get raw TMP006 data\n"
-	"  typeccontrol <port> <command>\n"
-	"      Control USB PD policy\n"
-	"  typecdiscovery <port> <type>\n"
-	"      Get discovery information for port and type\n"
-	"  typecstatus <port>\n"
-	"      Get status information for port\n"
-	"  uptimeinfo\n"
-	"      Get info about how long the EC has been running and the most\n"
-	"      recent AP resets\n"
-	"  usbchargemode <port> <mode> [<inhibit_charge>]\n"
-	"      Set USB charging mode\n"
-	"  usbmux <mux>\n"
-	"      Set USB mux switch state\n"
-	"  usbpd <port> <auto | "
-			"[toggle|toggle-off|sink|source] [none|usb|dp|dock] "
-			"[dr_swap|pr_swap|vconn_swap]>\n"
-	"      Control USB PD/type-C [deprecated]\n"
-	"  usbpdmuxinfo\n"
-	"      Get USB-C SS mux info\n"
-	"  usbpdpower [port]\n"
-	"      Get USB PD power information\n"
-	"  version\n"
-	"      Prints EC version\n"
-	"  waitevent <type> [<timeout>]\n"
-	"      Wait for the MKBP event of type and display it\n"
-	"  wireless <flags> [<mask> [<suspend_flags> <suspend_mask>]]\n"
-	"      Enable/disable WLAN/Bluetooth radio\n"
-	"";
-
-/* Note: depends on enum ec_image */
-static const char * const image_names[] = {"unknown", "RO", "RW"};
-
-/* Note: depends on enum ec_led_colors */
-static const char * const led_color_names[] = {
-	"red", "green", "blue", "yellow", "white", "amber"};
-BUILD_ASSERT(ARRAY_SIZE(led_color_names) == EC_LED_COLOR_COUNT);
-
-/* Note: depends on enum ec_led_id */
-static const char * const led_names[] = {
-	"battery", "power", "adapter", "left", "right", "recovery_hwreinit",
-	"sysrq debug" };
-BUILD_ASSERT(ARRAY_SIZE(led_names) == EC_LED_ID_COUNT);
-
-/* ASCII mode for printing, default off */
-static int ascii_mode = 0;
-
-/* Check SBS numerical value range */
-int is_battery_range(int val)
-{
-	return (val >= 0 && val <= 65535) ? 1 : 0;
-}
-
-int parse_bool(const char *s, int *dest)
-{
-	if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) ||
-	    tolower(*s) == 'f' || tolower(*s) == 'n') {
-		*dest = 0;
-		return 1;
-	} else if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
-	    tolower(*s) == 't' || tolower(*s) == 'y') {
-		*dest = 1;
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-void print_help(const char *prog, int print_cmds)
-{
-	printf("Usage: %s [--dev=n] [--interface=dev|i2c|lpc] [--i2c_bus=n]",
-	       prog);
-	printf("[--name=cros_ec|cros_fp|cros_pd|cros_scp|cros_ish] [--ascii] ");
-	printf("<command> [params]\n\n");
-	printf("  --i2c_bus=n  Specifies the number of an I2C bus to use. For\n"
-	       "               example, to use /dev/i2c-7, pass --i2c_bus=7.\n"
-	       "               Implies --interface=i2c.\n\n");
-	if (print_cmds)
-		puts(help_str);
-	else
-		printf("Use '%s help' to print a list of commands.\n", prog);
-}
-
-static uint8_t read_mapped_mem8(uint8_t offset)
-{
-	int ret;
-	uint8_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static uint16_t read_mapped_mem16(uint8_t offset)
-{
-	int ret;
-	uint16_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static uint32_t read_mapped_mem32(uint8_t offset)
-{
-	int ret;
-	uint32_t val;
-
-	ret = ec_readmem(offset, sizeof(val), &val);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return val;
-}
-
-static int read_mapped_string(uint8_t offset, char *buffer, int max_size)
-{
-	int ret;
-
-	ret = ec_readmem(offset, max_size, buffer);
-	if (ret <= 0) {
-		fprintf(stderr, "failure in %s(): %d\n", __func__, ret);
-		exit(1);
-	}
-	return ret;
-}
-
-static int wait_event(long event_type,
-		      struct ec_response_get_next_event_v1 *buffer,
-		      size_t buffer_size, long timeout)
-{
-	int rv;
-
-	rv = ec_pollevent(1 << event_type, buffer, buffer_size, timeout);
-	if (rv == 0) {
-		fprintf(stderr, "Timeout waiting for MKBP event\n");
-		return -ETIMEDOUT;
-	} else if (rv < 0) {
-		perror("Error polling for MKBP event\n");
-		return -EIO;
-	}
-
-	return rv;
-}
-
-int cmd_adc_read(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_adc_read p;
-	struct ec_response_adc_read r;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <adc channel>\n", argv[0]);
-		return -1;
-	}
-
-	p.adc_channel = (uint8_t)strtoull(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "\"%s\": invalid channel!\n", argv[1]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_ADC_READ, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv > 0) {
-		printf("%s: %d\n", argv[1], r.adc_value);
-		return 0;
-	}
-
-	return rv;
-}
-
-int cmd_add_entropy(int argc, char *argv[])
-{
-	struct ec_params_rollback_add_entropy p;
-	int rv;
-	int tries = 100; /* Wait for 10 seconds at most */
-
-	if (argc >= 2 && !strcmp(argv[1], "reset"))
-		p.action = ADD_ENTROPY_RESET_ASYNC;
-	else
-		p.action = ADD_ENTROPY_ASYNC;
-
-	rv = ec_command(EC_CMD_ADD_ENTROPY, 0, &p, sizeof(p), NULL, 0);
-
-	if (rv != EC_RES_SUCCESS)
-		goto out;
-
-	while (tries--) {
-		usleep(100000);
-
-		p.action = ADD_ENTROPY_GET_RESULT;
-		rv = ec_command(EC_CMD_ADD_ENTROPY, 0, &p, sizeof(p), NULL, 0);
-
-		if (rv == EC_RES_SUCCESS) {
-			printf("Entropy added successfully\n");
-			return EC_RES_SUCCESS;
-		}
-
-		/* Abort if EC returns an error other than EC_RES_BUSY. */
-		if (rv <= -EECRESULT && rv != -EECRESULT-EC_RES_BUSY)
-			goto out;
-	}
-
-	rv = -EECRESULT-EC_RES_TIMEOUT;
-out:
-	fprintf(stderr, "Failed to add entropy: %d\n", rv);
-	return rv;
-}
-
-int cmd_hello(int argc, char *argv[])
-{
-	struct ec_params_hello p;
-	struct ec_response_hello r;
-	int rv;
-
-	p.in_data = 0xa0b0c0d0;
-
-	rv = ec_command(EC_CMD_HELLO, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.out_data != 0xa1b2c3d4) {
-		fprintf(stderr, "Expected response 0x%08x, got 0x%08x\n",
-			0xa1b2c3d4, r.out_data);
-		return -1;
-	}
-
-	printf("EC says hello!\n");
-	return 0;
-}
-
-int cmd_hibdelay(int argc, char *argv[])
-{
-	struct ec_params_hibernation_delay p;
-	struct ec_response_hibernation_delay r;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		p.seconds = 0; /* Just read the current settings. */
-	} else {
-		p.seconds = strtoull(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid number\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "err: rv=%d\n", rv);
-		return -1;
-	}
-
-	printf("Hibernation delay: %u s\n", r.hibernate_delay);
-	printf("Time G3: %u s\n", r.time_g3);
-	printf("Time left: %u s\n", r.time_remaining);
-	return 0;
-}
-
-static void cmd_hostevent_help(char *cmd)
-{
-	fprintf(stderr,
-	"  Usage: %s get <type>\n"
-	"  Usage: %s set <type> <value>\n"
-	"    <type> is one of:\n"
-	"      1: EC_HOST_EVENT_B\n"
-	"      2: EC_HOST_EVENT_SCI_MASK\n"
-	"      3: EC_HOST_EVENT_SMI_MASK\n"
-	"      4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n"
-	"      5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n"
-	"      6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n"
-	"      7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n"
-	"      8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n"
-		, cmd, cmd);
-}
-
-static int cmd_hostevent(int argc, char *argv[])
-{
-	struct ec_params_host_event p;
-	struct ec_response_host_event r;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_hostevent_help(argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "get")) {
-		if (argc != 3) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_hostevent_help(argv[0]);
-			return -1;
-		}
-		p.action = EC_HOST_EVENT_GET;
-	} else if (!strcasecmp(argv[1], "set")) {
-		if (argc != 4) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_hostevent_help(argv[0]);
-			return -1;
-		}
-		p.action = EC_HOST_EVENT_SET;
-		p.value = strtoull(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad value\n");
-			return -1;
-		}
-	} else {
-		fprintf(stderr, "Bad subcommand: %s\n", argv[1]);
-		return -1;
-	}
-
-	p.mask_type = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv == -EC_RES_ACCESS_DENIED - EECRESULT) {
-		fprintf(stderr, "%s isn't permitted for mask %d.\n",
-			p.action == EC_HOST_EVENT_SET ? "Set" : "Get",
-			p.mask_type);
-		return rv;
-	} else if (rv < 0) {
-		return rv;
-	}
-
-	if (p.action == EC_HOST_EVENT_GET)
-		printf("0x%" PRIx64 "\n", r.value);
-
-	return 0;
-}
-
-static int get_latest_cmd_version(uint8_t cmd, int *version)
-{
-	struct ec_params_get_cmd_versions p;
-	struct ec_response_get_cmd_versions r;
-	int rv;
-
-	*version = 0;
-	/* Figure out the latest version of the given command the EC supports */
-	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		if (rv == -EC_RES_INVALID_PARAM)
-			printf("Command 0x%02x not supported by EC.\n",
-					EC_CMD_GET_CMD_VERSIONS);
-		return rv;
-	}
-
-	if (r.version_mask)
-		*version = __fls(r.version_mask);
-
-	return rv;
-}
-
-int cmd_hostsleepstate(int argc, char *argv[])
-{
-	struct ec_params_host_sleep_event p;
-	struct ec_params_host_sleep_event_v1 p1;
-	struct ec_response_host_sleep_event_v1 r;
-	void *pp = &p;
-	size_t psize = sizeof(p), rsize = 0;
-	char *afterscan;
-	int rv;
-	int version = 0, max_version = 0;
-	uint32_t timeout, transitions;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s "
-			"[suspend|wsuspend|resume|freeze|thaw] [timeout]\n",
-			argv[0]);
-		return -1;
-	}
-
-	rv = get_latest_cmd_version(EC_CMD_HOST_SLEEP_EVENT, &max_version);
-	if (rv < 0)
-		return rv;
-
-	if (!strcmp(argv[1], "suspend"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND;
-	else if (!strcmp(argv[1], "wsuspend"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND;
-	else if (!strcmp(argv[1], "resume"))
-		p.sleep_event = HOST_SLEEP_EVENT_S3_RESUME;
-	else if (!strcmp(argv[1], "freeze")) {
-		p.sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND;
-		if (max_version >= 1) {
-			p1.sleep_event = p.sleep_event;
-			p1.reserved = 0;
-			p1.suspend_params.sleep_timeout_ms =
-				EC_HOST_SLEEP_TIMEOUT_DEFAULT;
-
-			if (argc > 2) {
-				p1.suspend_params.sleep_timeout_ms =
-					strtoull(argv[2], &afterscan, 0);
-
-				if ((*afterscan != '\0') ||
-				    (afterscan == argv[2])) {
-					fprintf(stderr,
-						"Invalid value: %s\n",
-						argv[2]);
-
-					return -1;
-				}
-			}
-
-			pp = &p1;
-			psize = sizeof(p1);
-			version = 1;
-		}
-
-	} else if (!strcmp(argv[1], "thaw")) {
-		p.sleep_event = HOST_SLEEP_EVENT_S0IX_RESUME;
-		if (max_version >= 1) {
-			version = 1;
-			rsize = sizeof(r);
-		}
-	} else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_SLEEP_EVENT, version, pp, psize, &r, rsize);
-	if (rv < 0) {
-		fprintf(stderr, "EC host sleep command failed: %d\n", rv);
-		return rv;
-	}
-
-	if (rsize) {
-		timeout = r.resume_response.sleep_transitions &
-			  EC_HOST_RESUME_SLEEP_TIMEOUT;
-
-		transitions = r.resume_response.sleep_transitions &
-			      EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK;
-
-		printf("%s%d sleep line transitions.\n",
-		       timeout ? "Timeout: " : "",
-		       transitions);
-	}
-
-	return 0;
-}
-
-int cmd_test(int argc, char *argv[])
-{
-	struct ec_params_test_protocol p = {
-		.buf = { 1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11,
-			 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
-			 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }
-	};
-	struct ec_response_test_protocol r;
-	int rv, version = 0;
-	char *e;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s result length [version]\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.ec_result = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "invalid param (result)\n");
-		return -1;
-	}
-	p.ret_len = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "invalid param (length)\n");
-		return -1;
-	}
-
-	if (argc > 3) {
-		version = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid param (version)\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_TEST_PROTOCOL, version,
-			&p, sizeof(p), &r, sizeof(r));
-	printf("rv = %d\n", rv);
-
-	return rv;
-}
-
-int cmd_s5(int argc, char *argv[])
-{
-	struct ec_params_get_set_value p;
-	struct ec_params_get_set_value r;
-	int rv, param;
-
-	p.flags = 0;
-
-	if (argc > 1) {
-		p.flags |= EC_GSV_SET;
-		if (!parse_bool(argv[1], &param)) {
-			fprintf(stderr, "invalid arg \"%s\"\n", argv[1]);
-			return -1;
-		}
-		p.value = param;
-	}
-
-	rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv > 0)
-		printf("%s\n", r.value ? "on" : "off");
-
-	return rv < 0;
-}
-
-static const char * const ec_feature_names[] = {
-	[EC_FEATURE_LIMITED] = "Limited image, load RW for more",
-	[EC_FEATURE_FLASH] = "Flash",
-	[EC_FEATURE_PWM_FAN] = "Direct Fan power management",
-	[EC_FEATURE_PWM_KEYB] = "Keyboard backlight",
-	[EC_FEATURE_LIGHTBAR] = "Lightbar",
-	[EC_FEATURE_LED] = "LED",
-	[EC_FEATURE_MOTION_SENSE] = "Motion Sensors",
-	[EC_FEATURE_KEYB] = "Keyboard",
-	[EC_FEATURE_PSTORE] = "Host Permanent Storage",
-	[EC_FEATURE_PORT80] = "BIOS Port 80h access",
-	[EC_FEATURE_THERMAL] = "Thermal management",
-	[EC_FEATURE_BKLIGHT_SWITCH] = "Switch backlight on/off",
-	[EC_FEATURE_WIFI_SWITCH] = "Switch wifi on/off",
-	[EC_FEATURE_HOST_EVENTS] = "Host event",
-	[EC_FEATURE_GPIO] = "GPIO",
-	[EC_FEATURE_I2C] = "I2C controller",
-	[EC_FEATURE_CHARGER] = "Charger",
-	[EC_FEATURE_BATTERY] = "Simple Battery",
-	[EC_FEATURE_SMART_BATTERY] = "Smart Battery",
-	[EC_FEATURE_HANG_DETECT] = "Host hang detection",
-	[EC_FEATURE_PMU] = "Power Management",
-	[EC_FEATURE_SUB_MCU] = "Control downstream MCU",
-	[EC_FEATURE_USB_PD] = "USB Cros Power Delivery",
-	[EC_FEATURE_USB_MUX] = "USB Multiplexer",
-	[EC_FEATURE_MOTION_SENSE_FIFO] = "FIFO for Motion Sensors events",
-	[EC_FEATURE_VSTORE] = "Temporary secure vstore",
-	[EC_FEATURE_USBC_SS_MUX_VIRTUAL] = "Host-controlled USB-C SS mux",
-	[EC_FEATURE_RTC] = "Real-time clock",
-	[EC_FEATURE_FINGERPRINT] = "Fingerprint",
-	[EC_FEATURE_TOUCHPAD] = "Touchpad",
-	[EC_FEATURE_RWSIG] = "RWSIG task",
-	[EC_FEATURE_DEVICE_EVENT] = "Device events reporting",
-	[EC_FEATURE_UNIFIED_WAKE_MASKS] = "Unified wake masks for LPC/eSPI",
-	[EC_FEATURE_HOST_EVENT64] = "64-bit host events",
-	[EC_FEATURE_EXEC_IN_RAM] = "Execute code in RAM",
-	[EC_FEATURE_CEC] = "Consumer Electronics Control",
-	[EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS] =
-		"Tight timestamp for sensors events",
-	[EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS] =
-		"Refined tablet mode hysteresis",
-	[EC_FEATURE_EFS2] = "Early Firmware Selection v2",
-	[EC_FEATURE_ISH] = "Intel Integrated Sensor Hub",
-	[EC_FEATURE_TYPEC_CMD] = "TCPMv2 Type-C commands",
-	[EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY] =
-		"Host-controlled Type-C mode entry",
-	[EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK] =
-		"AP ack for Type-C mux configuration",
-};
-
-int cmd_inventory(int argc, char *argv[])
-{
-	struct ec_response_get_features r;
-	int rv, i, j, idx;
-
-	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("EC supported features:\n");
-	for (i = 0, idx = 0; i < 2; i++) {
-		for (j = 0; j < 32; j++, idx++) {
-			if (r.flags[i] & BIT(j)) {
-				if (idx >= ARRAY_SIZE(ec_feature_names) ||
-				    !ec_feature_names[idx] ||
-				    strlen(ec_feature_names[idx]) == 0)
-					printf("%-4d: Unknown feature\n", idx);
-				else
-					printf("%-4d: %s support\n",
-					       idx, ec_feature_names[idx]);
-			}
-		}
-	}
-	return 0;
-}
-
-
-int cmd_cmdversions(int argc, char *argv[])
-{
-	struct ec_params_get_cmd_versions p;
-	struct ec_response_get_cmd_versions r;
-	char *e;
-	int cmd;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <cmd>\n", argv[0]);
-		return -1;
-	}
-	cmd = strtol(argv[1], &e, 0);
-	if ((e && *e) || cmd < 0 || cmd > 0xff) {
-		fprintf(stderr, "Bad command number.\n");
-		return -1;
-	}
-
-	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
-	if (rv < 0) {
-		if (rv == -EC_RES_INVALID_PARAM)
-			printf("Command 0x%02x not supported by EC.\n", cmd);
-
-		return rv;
-	}
-
-	printf("Command 0x%02x supports version mask 0x%08x\n",
-	       cmd, r.version_mask);
-	return 0;
-}
-
-/*
- * Convert a reset cause ID to human-readable string, providing total coverage
- * of the 'cause' space.  The returned string points to static storage and must
- * not be free()ed.
- */
-static const char *reset_cause_to_str(uint16_t cause)
-{
-	static const char * const reset_causes[] = {
-		"(reset unknown)",
-		"reset: board custom",
-		"reset: ap hang detected",
-		"reset: console command",
-		"reset: host command",
-		"reset: keyboard sysreset",
-		"reset: keyboard warm reboot",
-		"reset: debug warm reboot",
-		"reset: at AP's request",
-		"reset: during EC initialization",
-		"reset: AP watchdog",
-	};
-	BUILD_ASSERT(ARRAY_SIZE(reset_causes) == CHIPSET_RESET_COUNT);
-
-	static const char * const shutdown_causes[] = {
-		"shutdown: power failure",
-		"shutdown: during EC initialization",
-		"shutdown: board custom",
-		"shutdown: battery voltage startup inhibit",
-		"shutdown: power wait asserted",
-		"shutdown: critical battery",
-		"shutdown: by console command",
-		"shutdown: entering G3",
-		"shutdown: thermal",
-		"shutdown: power button",
-	};
-	BUILD_ASSERT(ARRAY_SIZE(shutdown_causes) ==
-		     CHIPSET_SHUTDOWN_COUNT - CHIPSET_SHUTDOWN_BEGIN);
-
-	if (cause < CHIPSET_RESET_COUNT)
-		return reset_causes[cause];
-
-	if (cause < CHIPSET_SHUTDOWN_BEGIN)
-		return "(reset unknown)";
-
-	if (cause < CHIPSET_SHUTDOWN_COUNT)
-		return shutdown_causes[cause - CHIPSET_SHUTDOWN_BEGIN];
-
-	return "(shutdown unknown)";
-}
-
-int cmd_uptimeinfo(int argc, char *argv[])
-{
-	struct ec_response_uptime_info r;
-	int rv;
-	int i;
-	int flag_count;
-	uint32_t flag;
-	static const char * const reset_flag_descs[] = {
-		#include "reset_flag_desc.inc"
-	};
-
-	if (argc != 1) {
-		fprintf(stderr, "uptimeinfo takes no arguments");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GET_UPTIME_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_UPTIME_INFO failed; %d\n",
-			rv);
-		return rv;
-	}
-
-	printf("EC uptime: %d.%03d seconds\n",
-		r.time_since_ec_boot_ms / 1000,
-		r.time_since_ec_boot_ms % 1000);
-
-	printf("AP resets since EC boot: %d\n", r.ap_resets_since_ec_boot);
-
-	printf("Most recent AP reset causes:\n");
-	for (i = 0; i != ARRAY_SIZE(r.recent_ap_reset); ++i) {
-		if (r.recent_ap_reset[i].reset_time_ms == 0)
-			continue;
-
-		printf("\t%d.%03d: %s\n",
-			r.recent_ap_reset[i].reset_time_ms / 1000,
-			r.recent_ap_reset[i].reset_time_ms % 1000,
-			reset_cause_to_str(r.recent_ap_reset[i].reset_cause));
-	}
-
-	printf("EC reset flags at last EC boot: ");
-
-	if (!r.ec_reset_flags) {
-		printf("unknown\n");
-		return 0;
-	}
-
-	flag_count = 0;
-	for (flag = 0; flag < ARRAY_SIZE(reset_flag_descs); ++flag) {
-		if ((r.ec_reset_flags & BIT(flag)) != 0) {
-			if (flag_count)
-				printf(" | ");
-			printf(reset_flag_descs[flag]);
-			flag_count++;
-		}
-	}
-
-	if (r.ec_reset_flags >= BIT(flag)) {
-		if (flag_count)
-			printf(" | ");
-		printf("no-desc");
-	}
-	printf("\n");
-	return 0;
-}
-
-int cmd_version(int argc, char *argv[])
-{
-	struct ec_response_get_version_v1 r;
-	char *build_string = (char *)ec_inbuf;
-	int rv;
-
-	if (ec_cmd_version_supported(EC_CMD_GET_VERSION, 1)) {
-		rv = ec_command(EC_CMD_GET_VERSION, 1, NULL, 0, &r,
-				sizeof(struct ec_response_get_version_v1));
-	} else {
-		/* Fall-back to version 0 if version 1 is not supported */
-		rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &r,
-				sizeof(struct ec_response_get_version));
-		/* These fields are not supported in version 0, ensure empty */
-		r.cros_fwid_ro[0] = '\0';
-		r.cros_fwid_rw[0] = '\0';
-	}
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_VERSION failed: %d\n", rv);
-		goto exit;
-	}
-
-	rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-			NULL, 0, ec_inbuf, ec_max_insize);
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_GET_BUILD_INFO failed: %d\n",
-				rv);
-		goto exit;
-	}
-
-	rv = 0;
-
-	/* Ensure versions are null-terminated before we print them */
-	r.version_string_ro[sizeof(r.version_string_ro) - 1] = '\0';
-	r.version_string_rw[sizeof(r.version_string_rw) - 1] = '\0';
-	build_string[ec_max_insize - 1] = '\0';
-	r.cros_fwid_ro[sizeof(r.cros_fwid_ro) - 1] = '\0';
-	r.cros_fwid_rw[sizeof(r.cros_fwid_rw) - 1] = '\0';
-	/* Print versions */
-	printf("RO version:    %s\n", r.version_string_ro);
-	if (strlen(r.cros_fwid_ro))
-		printf("RO cros fwid:  %s\n", r.cros_fwid_ro);
-	printf("RW version:    %s\n", r.version_string_rw);
-	if (strlen(r.cros_fwid_rw))
-		printf("RW cros fwid:  %s\n", r.cros_fwid_rw);
-	printf("Firmware copy: %s\n",
-	       (r.current_image < ARRAY_SIZE(image_names) ?
-		image_names[r.current_image] : "?"));
-	printf("Build info:    %s\n", build_string);
-exit:
-	printf("Tool version:  %s %s %s\n", CROS_ECTOOL_VERSION, DATE, BUILDER);
-
-	return rv;
-}
-
-
-int cmd_read_test(int argc, char *argv[])
-{
-	struct ec_params_read_test p;
-	struct ec_response_read_test r;
-	int offset, size;
-	int errors = 0;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-	uint32_t *b;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <pattern_offset> <size>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes with pattern offset 0x%x...\n", size, offset);
-
-	buf = (char *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += sizeof(r.data)) {
-		p.offset = offset + i / sizeof(uint32_t);
-		p.size = MIN(size - i, sizeof(r.data));
-		rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p),
-				&r, sizeof(r));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-		memcpy(buf + i, r.data, p.size);
-	}
-
-	/* Check data */
-	for (i = 0, b = (uint32_t *)buf; i < size / 4; i++, b++) {
-		if (*b != i + offset) {
-			printf("Mismatch at byte offset 0x%x: "
-			       "expected 0x%08x, got 0x%08x\n",
-			       (int)(i * sizeof(uint32_t)), i + offset, *b);
-			errors++;
-		}
-	}
-
-	free(buf);
-	if (errors) {
-		printf("Found %d errors\n", errors);
-		return -1;
-	}
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_reboot_ec(int argc, char *argv[])
-{
-	struct ec_params_reboot_ec p;
-	int rv, i;
-
-	if (argc < 2) {
-		/*
-		 * No params specified so tell the EC to reboot immediately.
-		 * That reboots the AP as well, so unlikely we'll be around
-		 * to see a return code from this...
-		 */
-		rv = ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
-		return (rv < 0 ? rv : 0);
-	}
-
-	/* Parse command */
-	if (!strcmp(argv[1], "cancel"))
-		p.cmd = EC_REBOOT_CANCEL;
-	else if (!strcmp(argv[1], "RO"))
-		p.cmd = EC_REBOOT_JUMP_RO;
-	else if (!strcmp(argv[1], "RW"))
-		p.cmd = EC_REBOOT_JUMP_RW;
-	else if (!strcmp(argv[1], "cold"))
-		p.cmd = EC_REBOOT_COLD;
-	else if (!strcmp(argv[1], "disable-jump"))
-		p.cmd = EC_REBOOT_DISABLE_JUMP;
-	else if (!strcmp(argv[1], "hibernate"))
-		p.cmd = EC_REBOOT_HIBERNATE;
-	else if (!strcmp(argv[1], "hibernate-clear-ap-off"))
-		p.cmd = EC_REBOOT_HIBERNATE_CLEAR_AP_OFF;
-	else if (!strcmp(argv[1], "cold-ap-off"))
-		p.cmd = EC_REBOOT_COLD_AP_OFF;
-	else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	/* Parse flags, if any */
-	p.flags = 0;
-	for (i = 2; i < argc; i++) {
-		if (!strcmp(argv[i], "at-shutdown")) {
-			p.flags |= EC_REBOOT_FLAG_ON_AP_SHUTDOWN;
-		} else if (!strcmp(argv[i], "switch-slot")) {
-			p.flags |= EC_REBOOT_FLAG_SWITCH_RW_SLOT;
-		} else {
-			fprintf(stderr, "Unknown flag: %s\n", argv[i]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_REBOOT_EC, 0, &p, sizeof(p), NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_reboot_ap_on_g3(int argc, char *argv[])
-{
-	struct ec_params_reboot_ap_on_g3_v1 p;
-	int rv;
-	char *e;
-	int cmdver;
-
-	if (argc < 2) {
-		p.reboot_ap_at_g3_delay = 0;
-	} else {
-		p.reboot_ap_at_g3_delay = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid number\n");
-			return -1;
-		}
-	}
-	if (ec_cmd_version_supported(EC_CMD_REBOOT_AP_ON_G3, 1))
-		cmdver = 1;
-	else
-		cmdver = 0;
-
-	rv = ec_command(EC_CMD_REBOOT_AP_ON_G3, cmdver, &p, sizeof(p), NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_button(int argc, char *argv[])
-{
-	struct ec_params_button p;
-	char *e;
-	int argv_idx;
-	int button = KEYBOARD_BUTTON_COUNT;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Invalid num param %d.\n", argc);
-		return -1;
-	}
-
-	p.press_ms = 50;
-	p.btn_mask = 0;
-
-	for (argv_idx = 1; argv_idx < argc; argv_idx++) {
-		if (!strcasecmp(argv[argv_idx], "vup"))
-			button = KEYBOARD_BUTTON_VOLUME_UP;
-		else if (!strcasecmp(argv[argv_idx], "vdown"))
-			button = KEYBOARD_BUTTON_VOLUME_DOWN;
-		else if (!strcasecmp(argv[argv_idx], "rec"))
-			button = KEYBOARD_BUTTON_RECOVERY;
-		else {
-			/* If last parameter check if it is an integer. */
-			if (argv_idx == argc - 1) {
-				p.press_ms = strtol(argv[argv_idx], &e, 0);
-				/* If integer, break out of the loop. */
-				if (!*e)
-					break;
-			}
-			button = KEYBOARD_BUTTON_COUNT;
-		}
-
-		if (button == KEYBOARD_BUTTON_COUNT) {
-			fprintf(stderr, "Invalid button input.\n");
-			return -1;
-		}
-
-		p.btn_mask |= (1 << button);
-	}
-	if (!p.btn_mask)
-		return 0;
-
-	rv = ec_command(EC_CMD_BUTTON, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Button(s) %d set to %d ms\n", p.btn_mask, p.press_ms);
-	return 0;
-}
-
-int cmd_flash_info(int argc, char *argv[])
-{
-	struct ec_response_flash_info_1 r;
-	int cmdver = 1;
-	int rsize = sizeof(r);
-	int rv;
-
-	memset(&r, 0, sizeof(r));
-
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_INFO, cmdver)) {
-		/* Fall back to version 0 command */
-		cmdver = 0;
-		rsize = sizeof(struct ec_response_flash_info);
-	}
-
-	rv = ec_command(EC_CMD_FLASH_INFO, cmdver, NULL, 0, &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	printf("FlashSize %d\nWriteSize %d\nEraseSize %d\nProtectSize %d\n",
-	       r.flash_size, r.write_block_size, r.erase_block_size,
-	       r.protect_block_size);
-
-	if (cmdver >= 1) {
-		/* Fields added in ver.1 available */
-		printf("WriteIdealSize %d\nFlags 0x%x\n",
-		       r.write_ideal_size, r.flags);
-	}
-
-	return 0;
-}
-
-int cmd_rand(int argc, char *argv[])
-{
-	struct ec_params_rand_num p;
-	struct ec_response_rand_num *r;
-	size_t r_size;
-	int64_t num_bytes;
-	int64_t i;
-	char *e;
-	int rv = 0;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <num_bytes>\n", argv[0]);
-		return -1;
-	}
-
-	num_bytes = strtol(argv[1], &e, 0);
-	if ((e && *e) || (errno == ERANGE)) {
-		fprintf(stderr, "Invalid num_bytes argument\n");
-		return -1;
-	}
-
-	r = (struct ec_response_rand_num *)(ec_inbuf);
-
-	for (i = 0; i < num_bytes; i += ec_max_insize) {
-		p.num_rand_bytes = ec_max_insize;
-		if (num_bytes - i < p.num_rand_bytes)
-			p.num_rand_bytes = num_bytes - i;
-
-		r_size = p.num_rand_bytes;
-
-		rv = ec_command(EC_CMD_RAND_NUM, EC_VER_RAND_NUM, &p, sizeof(p),
-				r, r_size);
-		if (rv < 0) {
-			fprintf(stderr, "Random number command failed\n");
-			return -1;
-		}
-
-		rv = write(STDOUT_FILENO, r->rand, r_size);
-		if (rv != r_size) {
-			fprintf(stderr, "Failed to write stdout\n");
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-int cmd_flash_spi_info(int argc, char *argv[])
-{
-	struct ec_response_flash_spi_info r;
-	int rv;
-
-	memset(&r, 0, sizeof(r));
-
-	/* Print SPI flash info if available */
-	if (!ec_cmd_version_supported(EC_CMD_FLASH_SPI_INFO, 0)) {
-		printf("EC has no info (does not use SPI flash?)\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_FLASH_SPI_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("JEDECManufacturerID 0x%02x\n", r.jedec[0]);
-	printf("JEDECDeviceID 0x%02x 0x%02x\n", r.jedec[1], r.jedec[2]);
-	printf("JEDECCapacity %d\n", 1 << r.jedec[2]);
-	printf("ManufacturerID 0x%02x\n", r.mfr_dev_id[0]);
-	printf("DeviceID 0x%02x\n", r.mfr_dev_id[1]);
-	printf("StatusRegister1 0x%02x\n", r.sr1);
-	printf("StatusRegister2 0x%02x\n", r.sr2);
-	return 0;
-}
-
-int cmd_flash_read(int argc, char *argv[])
-{
-	int offset, size;
-	int rv;
-	char *e;
-	uint8_t *buf;
-
-	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes at offset %d...\n", size, offset);
-
-	buf = (uint8_t *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	rv = ec_flash_read(buf, offset, size);
-	if (rv < 0) {
-		free(buf);
-		return rv;
-	}
-
-	rv = write_file(argv[3], (const char *)(buf), size);
-	free(buf);
-	if (rv)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_flash_write(int argc, char *argv[])
-{
-	int offset, size;
-	int rv;
-	char *e;
-	char *buf;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
-		return -1;
-	}
-
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[2], &size);
-	if (!buf)
-		return -1;
-
-	printf("Writing to offset %d...\n", offset);
-
-	/* Write data in chunks */
-	rv = ec_flash_write((const uint8_t *)(buf), offset,
-			    size);
-
-	free(buf);
-
-	if (rv < 0)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_flash_erase(int argc, char *argv[])
-{
-	int offset, size;
-	char *e;
-	int rv;
-	bool async = false;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <size>\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[0], "flasheraseasync") == 0)
-		async = true;
-
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > MAX_FLASH_SIZE) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-
-	printf("Erasing %d bytes at offset %d...\n", size, offset);
-	if (async)
-		rv = ec_flash_erase_async(offset, size);
-	else
-		rv = ec_flash_erase(offset, size);
-	if (rv < 0)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-
-static void print_flash_protect_flags(const char *desc, uint32_t flags)
-{
-	printf("%s 0x%08x", desc, flags);
-	if (flags & EC_FLASH_PROTECT_GPIO_ASSERTED)
-		printf(" wp_gpio_asserted");
-	if (flags & EC_FLASH_PROTECT_RO_AT_BOOT)
-		printf(" ro_at_boot");
-	if (flags & EC_FLASH_PROTECT_RW_AT_BOOT)
-		printf(" rw_at_boot");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT)
-		printf(" rollback_at_boot");
-	if (flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		printf(" all_at_boot");
-	if (flags & EC_FLASH_PROTECT_RO_NOW)
-		printf(" ro_now");
-	if (flags & EC_FLASH_PROTECT_RW_NOW)
-		printf(" rw_now");
-	if (flags & EC_FLASH_PROTECT_ROLLBACK_NOW)
-		printf(" rollback_now");
-	if (flags & EC_FLASH_PROTECT_ALL_NOW)
-		printf(" all_now");
-	if (flags & EC_FLASH_PROTECT_ERROR_STUCK)
-		printf(" STUCK");
-	if (flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT)
-		printf(" INCONSISTENT");
-	printf("\n");
-}
-
-
-int cmd_flash_protect(int argc, char *argv[])
-{
-	struct ec_params_flash_protect p;
-	struct ec_response_flash_protect r;
-	int rv, i;
-
-	/*
-	 * Set up requested flags.  If no flags were specified, p.mask will
-	 * be 0 and nothing will change.
-	 */
-	p.mask = p.flags = 0;
-	for (i = 1; i < argc; i++) {
-		if (!strcasecmp(argv[i], "now")) {
-			p.mask |= EC_FLASH_PROTECT_ALL_NOW;
-			p.flags |= EC_FLASH_PROTECT_ALL_NOW;
-		} else if (!strcasecmp(argv[i], "enable")) {
-			p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT;
-			p.flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-		} else if (!strcasecmp(argv[i], "disable"))
-			p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT;
-	}
-
-	rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (rv < sizeof(r)) {
-		fprintf(stderr, "Too little data returned.\n");
-		return -1;
-	}
-
-	/* Print returned flags */
-	print_flash_protect_flags("Flash protect flags:", r.flags);
-	print_flash_protect_flags("Valid flags:        ", r.valid_flags);
-	print_flash_protect_flags("Writable flags:     ", r.writable_flags);
-
-	/* Check if we got all the flags we asked for */
-	if ((r.flags & p.mask) != (p.flags & p.mask)) {
-		fprintf(stderr, "Unable to set requested flags "
-			"(wanted mask 0x%08x flags 0x%08x)\n",
-			p.mask, p.flags);
-		if (p.mask & ~r.writable_flags)
-			fprintf(stderr, "Which is expected, because writable "
-				"mask is 0x%08x.\n", r.writable_flags);
-
-		return -1;
-	}
-
-	return 0;
-}
-
-int cmd_rw_hash_pd(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_rw_hash_entry *p =
-		(struct ec_params_usb_pd_rw_hash_entry *)ec_outbuf;
-	int i, rv;
-	char *e;
-	uint32_t val;
-	uint8_t *rwp;
-
-	if (argc < 7) {
-		fprintf(stderr, "Usage: %s <dev_id> <HASH[0]> ... <HASH[4]>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p->dev_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad device ID\n");
-		return -1;
-	}
-
-	rwp = p->dev_rw_hash;
-	for (i = 2; i < 7; i++) {
-		val = strtol(argv[i], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad RW hash\n");
-			return -1;
-		}
-		rwp[0] = (uint8_t)  (val >> 0) & 0xff;
-		rwp[1] = (uint8_t)  (val >> 8) & 0xff;
-		rwp[2] = (uint8_t) (val >> 16) & 0xff;
-		rwp[3] = (uint8_t) (val >> 24) & 0xff;
-		rwp += 4;
-	}
-	rv = ec_command(EC_CMD_USB_PD_RW_HASH_ENTRY, 0, p, sizeof(*p), NULL, 0);
-
-	return rv;
-}
-
-int cmd_rwsig_status(int argc, char *argv[])
-{
-	int rv;
-	struct ec_response_rwsig_check_status resp;
-
-	rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0,
-			&resp, sizeof(resp));
-	if (rv < 0)
-		return rv;
-
-	printf("RW signature check: %s\n", resp.status ? "OK" : "FAILED");
-
-	return 0;
-}
-
-static int rwsig_action(const char *command)
-{
-	struct ec_params_rwsig_action req;
-
-	if (!strcasecmp(command, "abort"))
-		req.action = RWSIG_ACTION_ABORT;
-	else if (!strcasecmp(command, "continue"))
-		req.action = RWSIG_ACTION_CONTINUE;
-	else
-		return -1;
-
-	return ec_command(EC_CMD_RWSIG_ACTION, 0, &req, sizeof(req), NULL, 0);
-}
-
-int cmd_rwsig_action_legacy(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s [abort | continue]\n", argv[0]);
-		return -1;
-	}
-
-	return rwsig_action(argv[1]);
-}
-
-int cmd_rwsig_action(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Usage: ectool rwsig action [abort | "
-				"continue]\n");
-		return -1;
-	}
-
-	return rwsig_action(argv[1]);
-}
-
-enum rwsig_info_fields {
-	RWSIG_INFO_FIELD_SIG_ALG = BIT(0),
-	RWSIG_INFO_FIELD_KEY_VERSION = BIT(1),
-	RWSIG_INFO_FIELD_HASH_ALG = BIT(2),
-	RWSIG_INFO_FIELD_KEY_IS_VALID = BIT(3),
-	RWSIG_INFO_FIELD_KEY_ID = BIT(4),
-	RWSIG_INFO_FIELD_ALL = RWSIG_INFO_FIELD_SIG_ALG |
-		RWSIG_INFO_FIELD_KEY_VERSION | RWSIG_INFO_FIELD_HASH_ALG |
-		RWSIG_INFO_FIELD_KEY_IS_VALID | RWSIG_INFO_FIELD_KEY_ID
-};
-
-static int rwsig_info(enum rwsig_info_fields fields)
-{
-	int i;
-	int rv;
-	struct ec_response_rwsig_info r;
-	bool print_prefix = false;
-
-	rv = ec_command(EC_CMD_RWSIG_INFO, EC_VER_RWSIG_INFO, NULL, 0, &r,
-			sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "rwsig info command failed\n");
-		return -1;
-	}
-
-	if ((fields & RWSIG_INFO_FIELD_ALL) == RWSIG_INFO_FIELD_ALL)
-		print_prefix = true;
-
-	if (fields & RWSIG_INFO_FIELD_SIG_ALG) {
-		if (print_prefix)
-			printf("sig_alg: ");
-
-		printf("%d\n", r.sig_alg);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_VERSION) {
-		if (print_prefix)
-			printf("key_version: ");
-
-		printf("%d\n", r.key_version);
-	}
-	if (fields & RWSIG_INFO_FIELD_HASH_ALG) {
-		if (print_prefix)
-			printf("hash_alg: ");
-
-		printf("%d\n", r.hash_alg);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_IS_VALID) {
-		if (print_prefix)
-			printf("key_is_valid: ");
-
-		printf("%d\n", r.key_is_valid);
-	}
-	if (fields & RWSIG_INFO_FIELD_KEY_ID) {
-		if (print_prefix)
-			printf("key_id: ");
-
-		for (i = 0; i < sizeof(r.key_id); i++)
-			printf("%02x", r.key_id[i]);
-		printf("\n");
-	}
-
-	return 0;
-}
-
-static int cmd_rwsig_info(int argc, char *argv[])
-{
-	int i;
-
-	struct rwsig_dump_cmds {
-		const char *cmd;
-		enum rwsig_info_fields field;
-	};
-
-	struct rwsig_dump_cmds cmd_map[] = {
-		{ "sig_alg", RWSIG_INFO_FIELD_SIG_ALG },
-		{ "key_version", RWSIG_INFO_FIELD_KEY_VERSION },
-		{ "hash_alg", RWSIG_INFO_FIELD_HASH_ALG },
-		{ "key_valid", RWSIG_INFO_FIELD_KEY_IS_VALID },
-		{ "key_id", RWSIG_INFO_FIELD_KEY_ID },
-	};
-
-	if (argc == 0)
-		return -1;
-
-	if (strcmp(argv[0], "info") == 0)
-		return rwsig_info(RWSIG_INFO_FIELD_ALL);
-
-	if (strcmp(argv[0], "dump") == 0) {
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: rwsig dump "
-				"[sig_alg|key_version|hash_alg|key_valid|key_id]\n");
-			return -1;
-		}
-		for (i = 0; i < ARRAY_SIZE(cmd_map); i++)
-			if (strcmp(argv[1], cmd_map[i].cmd) == 0)
-				return rwsig_info(cmd_map[i].field);
-
-		return -1;
-	}
-
-	return -1;
-}
-
-int cmd_rwsig(int argc, char **argv)
-{
-	struct rwsig_subcommand {
-		const char *subcommand;
-		int (*handler)(int argc, char *argv[]);
-	};
-
-	const struct rwsig_subcommand rwsig_subcommands[] = {
-		{ "info", cmd_rwsig_info },
-		{ "dump", cmd_rwsig_info },
-		{ "action", cmd_rwsig_action },
-		{ "status", cmd_rwsig_status }
-	};
-
-	int i;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <info|dump|action|status>\n",
-			argv[0]);
-		return -1;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(rwsig_subcommands); i++)
-		if (strcmp(argv[1], rwsig_subcommands[i].subcommand) == 0)
-			return rwsig_subcommands[i].handler(--argc, &argv[1]);
-
-	return -1;
-}
-
-enum sysinfo_fields {
-	SYSINFO_FIELD_NONE = 0,
-	SYSINFO_FIELD_RESET_FLAGS = BIT(0),
-	SYSINFO_FIELD_CURRENT_IMAGE = BIT(1),
-	SYSINFO_FIELD_FLAGS = BIT(2),
-	SYSINFO_INFO_FIELD_ALL = SYSINFO_FIELD_RESET_FLAGS |
-				 SYSINFO_FIELD_CURRENT_IMAGE |
-				 SYSINFO_FIELD_FLAGS
-};
-
-static int sysinfo(struct ec_response_sysinfo *info)
-{
-	int rv;
-
-	rv = ec_command(EC_CMD_SYSINFO, 0, NULL, 0, info, sizeof(*info));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_SYSINFO failed: %d\n", rv);
-		return rv;
-	}
-
-	return 0;
-}
-
-int cmd_sysinfo(int argc, char **argv)
-{
-	struct ec_response_sysinfo r;
-	enum sysinfo_fields fields = SYSINFO_FIELD_NONE;
-	bool print_prefix = false;
-
-	if (argc != 1 && argc != 2)
-		goto sysinfo_error_usage;
-
-	if (argc == 1) {
-		fields = SYSINFO_INFO_FIELD_ALL;
-		print_prefix = true;
-	} else if (argc == 2) {
-		if (strcmp(argv[1], "flags") == 0)
-			fields = SYSINFO_FIELD_FLAGS;
-		else if (strcmp(argv[1], "reset_flags") == 0)
-			fields = SYSINFO_FIELD_RESET_FLAGS;
-		else if (strcmp(argv[1], "firmware_copy") == 0)
-			fields = SYSINFO_FIELD_CURRENT_IMAGE;
-		else
-			goto sysinfo_error_usage;
-	}
-
-	memset(&r, '\0', sizeof(r));
-	if (sysinfo(&r) != 0)
-		return -1;
-
-	if (fields & SYSINFO_FIELD_RESET_FLAGS) {
-		if (print_prefix)
-			printf("Reset flags: ");
-		printf("0x%08x\n", r.reset_flags);
-	}
-
-	if (fields & SYSINFO_FIELD_FLAGS) {
-		if (print_prefix)
-			printf("Flags: ");
-		printf("0x%08x\n", r.flags);
-
-	}
-
-	if (fields & SYSINFO_FIELD_CURRENT_IMAGE) {
-		if (print_prefix)
-			printf("Firmware copy: ");
-		printf("%d\n", r.current_image);
-	}
-
-	return 0;
-
-sysinfo_error_usage:
-	fprintf(stderr, "Usage: %s "
-			"[flags|reset_flags|firmware_copy]\n",
-		argv[0]);
-	return -1;
-}
-
-int cmd_rollback_info(int argc, char *argv[])
-{
-	struct ec_response_rollback_info r;
-	int rv;
-
-	rv = ec_command(EC_CMD_ROLLBACK_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "ERROR: EC_CMD_ROLLBACK_INFO failed: %d\n", rv);
-		return rv;
-	}
-
-	/* Print versions */
-	printf("Rollback block id:    %d\n", r.id);
-	printf("Rollback min version: %d\n", r.rollback_min_version);
-	printf("RW rollback version:  %d\n", r.rw_rollback_version);
-
-	return 0;
-}
-
-int cmd_apreset(int argc, char *argv[])
-{
-	return ec_command(EC_CMD_AP_RESET, 0, NULL, 0, NULL, 0);
-}
-
-#define FP_FRAME_INDEX_SIMPLE_IMAGE -1
-
-/*
- * Download a frame buffer from the FPMCU.
- *
- * Might be either the finger image or a finger template depending on 'index'.
- *
- * @param info a pointer to store the struct ec_response_fp_info retrieved by
- * this command.
- * @param index the specific frame to retrieve, might be:
- *  -1 (aka FP_FRAME_INDEX_SIMPLE_IMAGE) for the a single grayscale image.
- *   0  (aka FP_FRAME_INDEX_RAW_IMAGE) for the full vendor raw finger image.
- *   1..n for a finger template.
- *
- * @returns a pointer to the buffer allocated to contain the frame or NULL
- * if case of error. The caller must call free() once it no longer needs the
- * buffer.
- */
-static void *fp_download_frame(struct ec_response_fp_info *info, int index)
-{
-	struct ec_params_fp_frame p;
-	int rv = 0;
-	size_t stride, size;
-	void *buffer;
-	uint8_t *ptr;
-	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(*info)
-				: sizeof(struct ec_response_fp_info_v0);
-	const int max_attempts = 3;
-	int num_attempts;
-
-	/* templates not supported in command v0 */
-	if (index > 0 && cmdver == 0)
-		return NULL;
-
-	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, info, rsize);
-	if (rv < 0)
-		return NULL;
-
-	if (index == FP_FRAME_INDEX_SIMPLE_IMAGE) {
-		size = (size_t)info->width * info->bpp/8 * info->height;
-		index = FP_FRAME_INDEX_RAW_IMAGE;
-	} else if (index == FP_FRAME_INDEX_RAW_IMAGE) {
-		size = info->frame_size;
-	} else {
-		size = info->template_size;
-	}
-
-	buffer = malloc(size);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate memory for the image\n");
-		return NULL;
-	}
-
-	ptr = (uint8_t *)(buffer);
-	p.offset = index << FP_FRAME_INDEX_SHIFT;
-	while (size) {
-		stride = MIN(ec_max_insize, size);
-		p.size = stride;
-		num_attempts = 0;
-		while (num_attempts < max_attempts) {
-			num_attempts++;
-			rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p),
-					ptr, stride);
-			if (rv >= 0)
-				break;
-			if (rv == -EECRESULT - EC_RES_ACCESS_DENIED)
-				break;
-			usleep(100000);
-		}
-		if (rv < 0) {
-			free(buffer);
-			return NULL;
-		}
-		p.offset += stride;
-		size -= stride;
-		ptr += stride;
-	}
-
-	return buffer;
-}
-
-int cmd_fp_mode(int argc, char *argv[])
-{
-	struct ec_params_fp_mode p;
-	struct ec_response_fp_mode r;
-	uint32_t mode = 0;
-	uint32_t capture_type = FP_CAPTURE_SIMPLE_IMAGE;
-	int i, rv;
-
-	if (argc == 1)
-		mode = FP_MODE_DONT_CHANGE;
-	for (i = 1; i < argc; i++) {
-		/* modes */
-		if (!strncmp(argv[i], "deepsleep", 9))
-			mode |= FP_MODE_DEEPSLEEP;
-		else if (!strncmp(argv[i], "fingerdown", 10))
-			mode |= FP_MODE_FINGER_DOWN;
-		else if (!strncmp(argv[i], "fingerup", 8))
-			mode |= FP_MODE_FINGER_UP;
-		else if (!strncmp(argv[i], "enroll", 6))
-			mode |= FP_MODE_ENROLL_IMAGE | FP_MODE_ENROLL_SESSION;
-		else if (!strncmp(argv[i], "match", 5))
-			mode |= FP_MODE_MATCH;
-		else if (!strncmp(argv[i], "reset_sensor", 12))
-			mode = FP_MODE_RESET_SENSOR;
-		else if (!strncmp(argv[i], "reset", 5))
-			mode = 0;
-		else if (!strncmp(argv[i], "maintenance", 11))
-			mode |= FP_MODE_SENSOR_MAINTENANCE;
-		else if (!strncmp(argv[i], "capture", 7))
-			mode |= FP_MODE_CAPTURE;
-		/* capture types */
-		else if (!strncmp(argv[i], "vendor", 6))
-			capture_type = FP_CAPTURE_VENDOR_FORMAT;
-		else if (!strncmp(argv[i], "pattern0", 8))
-			capture_type = FP_CAPTURE_PATTERN0;
-		else if (!strncmp(argv[i], "pattern1", 8))
-			capture_type = FP_CAPTURE_PATTERN1;
-		else if (!strncmp(argv[i], "qual", 4))
-			capture_type = FP_CAPTURE_QUALITY_TEST;
-		else if (!strncmp(argv[i], "test_reset", 10))
-			capture_type = FP_CAPTURE_RESET_TEST;
-	}
-	if (mode & FP_MODE_CAPTURE)
-		mode |= capture_type << FP_MODE_CAPTURE_TYPE_SHIFT;
-
-	p.mode = mode;
-	rv = ec_command(EC_CMD_FP_MODE, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("FP mode: (0x%x) ", r.mode);
-	if (r.mode & FP_MODE_DEEPSLEEP)
-		printf("deepsleep ");
-	if (r.mode & FP_MODE_FINGER_DOWN)
-		printf("finger-down ");
-	if (r.mode & FP_MODE_FINGER_UP)
-		printf("finger-up ");
-	if (r.mode & FP_MODE_ENROLL_SESSION)
-		printf("enroll%s ",
-			r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : "");
-	if (r.mode & FP_MODE_MATCH)
-		printf("match ");
-	if (r.mode & FP_MODE_CAPTURE)
-		printf("capture ");
-	printf("\n");
-	return 0;
-}
-
-int cmd_fp_seed(int argc, char *argv[])
-{
-	struct ec_params_fp_seed p;
-	char *seed;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <seed>\n", argv[0]);
-		return 1;
-	}
-	seed = argv[1];
-	if (strlen(seed) != FP_CONTEXT_TPM_BYTES) {
-		printf("Invalid seed '%s' is %zd bytes long instead of %d.\n",
-		       seed, strlen(seed), FP_CONTEXT_TPM_BYTES);
-		return 1;
-	}
-	printf("Setting seed '%s'\n", seed);
-	p.struct_version = FP_TEMPLATE_FORMAT_VERSION;
-	memcpy(p.seed, seed, FP_CONTEXT_TPM_BYTES);
-
-	return ec_command(EC_CMD_FP_SEED, 0, &p, sizeof(p), NULL, 0);
-}
-
-int cmd_fp_stats(int argc, char *argv[])
-{
-	struct ec_response_fp_stats r;
-	int rv;
-	unsigned long long ts;
-
-	rv = ec_command(EC_CMD_FP_STATS, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	ts = (uint64_t)r.overall_t0.hi << 32 | r.overall_t0.lo;
-	printf("FP stats (t0=%llu us):\n", ts);
-	printf("Last capture time:  ");
-	if (r.timestamps_invalid & FPSTATS_CAPTURE_INV)
-		printf("Invalid\n");
-	else
-		printf("%d us\n", r.capture_time_us);
-
-	printf("Last matching time: ");
-	if (r.timestamps_invalid & FPSTATS_MATCHING_INV)
-		printf("Invalid\n");
-	else
-		printf("%d us (finger: %d)\n", r.matching_time_us,
-			r.template_matched);
-
-	printf("Last overall time:  ");
-	if (r.timestamps_invalid)
-		printf("Invalid\n");
-	else
-		printf("%d us\n", r.overall_time_us);
-
-	return 0;
-}
-
-int cmd_fp_info(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	int rv;
-	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(r)
-				: sizeof(struct ec_response_fp_info_v0);
-	uint16_t dead;
-
-	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	printf("Fingerprint sensor: vendor %x product %x model %x version %x\n",
-		r.vendor_id, r.product_id, r.model_id, r.version);
-	printf("Image: size %dx%d %d bpp\n", r.width, r.height, r.bpp);
-	printf("Error flags: %s%s%s%s\n",
-	       r.errors & FP_ERROR_NO_IRQ ? "NO_IRQ " : "",
-	       r.errors & FP_ERROR_SPI_COMM ? "SPI_COMM " : "",
-	       r.errors & FP_ERROR_BAD_HWID ? "BAD_HWID " : "",
-	       r.errors & FP_ERROR_INIT_FAIL ? "INIT_FAIL " : "");
-	dead = FP_ERROR_DEAD_PIXELS(r.errors);
-	if (dead == FP_ERROR_DEAD_PIXELS_UNKNOWN) {
-		printf("Dead pixels: UNKNOWN\n");
-	} else {
-		printf("Dead pixels: %u\n", dead);
-	}
-
-	if (cmdver == 1) {
-		printf("Templates: version %d size %d count %d/%d"
-		       " dirty bitmap %x\n",
-		       r.template_version, r.template_size, r.template_valid,
-		       r.template_max, r.template_dirty);
-	}
-
-	return 0;
-}
-
-static void print_fp_enc_flags(const char *desc, uint32_t flags)
-{
-	printf("%s 0x%08x", desc, flags);
-	if (flags & FP_ENC_STATUS_SEED_SET)
-		printf(" FPTPM_seed_set");
-	printf("\n");
-}
-
-static int cmd_fp_context(int argc, char *argv[])
-{
-	struct ec_params_fp_context_v1 p;
-	int rv;
-	int tries = 20; /* Wait at most two seconds */
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <context>\n", argv[0]);
-		return -1;
-	}
-
-	/*
-	 * Note that we treat the resulting "userid" as raw byte array, so we
-	 * don't want to copy the NUL from the end of the string.
-	 */
-	if (strlen(argv[1]) != sizeof(p.userid)) {
-		fprintf(stderr, "Context must be exactly %zu bytes\n",
-			sizeof(p.userid));
-		return -1;
-	}
-
-	p.action = FP_CONTEXT_ASYNC;
-	memcpy(p.userid, argv[1], sizeof(p.userid));
-
-	rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
-
-	if (rv != EC_RES_SUCCESS)
-		goto out;
-
-	while (tries--) {
-		usleep(100000);
-
-		p.action = FP_CONTEXT_GET_RESULT;
-		rv = ec_command(EC_CMD_FP_CONTEXT, 1, &p, sizeof(p), NULL, 0);
-
-		if (rv == EC_RES_SUCCESS) {
-			printf("Set context successfully\n");
-			return EC_RES_SUCCESS;
-		}
-
-		/* Abort if EC returns an error other than EC_RES_BUSY. */
-		if (rv <= -EECRESULT && rv != -EECRESULT - EC_RES_BUSY)
-			goto out;
-	}
-
-	rv = -EECRESULT - EC_RES_TIMEOUT;
-
-out:
-	fprintf(stderr, "Failed to reset context: %d\n", rv);
-	return rv;
-}
-
-int cmd_fp_enc_status(int argc, char *argv[])
-{
-	int rv;
-	struct ec_response_fp_encryption_status resp = { 0 };
-
-	rv = ec_command(EC_CMD_FP_ENC_STATUS, 0, NULL, 0, &resp, sizeof(resp));
-	if (rv < 0) {
-		printf("Get FP sensor encryption status failed.\n");
-	} else {
-		print_fp_enc_flags("FPMCU encryption status:", resp.status);
-		print_fp_enc_flags("Valid flags:            ",
-				   resp.valid_flags);
-		rv = 0;
-	}
-	return rv;
-}
-
-int cmd_fp_frame(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	int idx = (argc == 2 && !strcasecmp(argv[1], "raw")) ?
-		FP_FRAME_INDEX_RAW_IMAGE : FP_FRAME_INDEX_SIMPLE_IMAGE;
-	uint8_t *buffer = (uint8_t *)(fp_download_frame(&r, idx));
-	uint8_t *ptr = buffer;
-	int x, y;
-
-	if (!buffer) {
-		fprintf(stderr, "Failed to get FP sensor frame\n");
-		return -1;
-	}
-
-	if (idx == FP_FRAME_INDEX_RAW_IMAGE) {
-		fwrite(buffer, r.frame_size, 1, stdout);
-		goto frame_done;
-	}
-
-	/* Print 8-bpp PGM ASCII header */
-	printf("P2\n%d %d\n%d\n", r.width, r.height, (1 << r.bpp) - 1);
-
-	for (y = 0; y < r.height; y++) {
-		for (x = 0; x < r.width; x++, ptr++)
-			printf("%d ", *ptr);
-		printf("\n");
-	}
-	printf("# END OF FILE\n");
-frame_done:
-	free(buffer);
-	return 0;
-}
-
-int cmd_fp_template(int argc, char *argv[])
-{
-	struct ec_response_fp_info r;
-	struct ec_params_fp_template *p =
-		(struct ec_params_fp_template *)(ec_outbuf);
-	/* TODO(b/78544921): removing 32 bits is a workaround for the MCU bug */
-	int max_chunk = ec_max_outsize
-			- offsetof(struct ec_params_fp_template, data) - 4;
-	int idx = -1;
-	char *e;
-	int size;
-	char *buffer = NULL;
-	uint32_t offset = 0;
-	int rv = 0;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s [<infile>|<index>]\n", argv[0]);
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if (!(e && *e)) {
-		buffer = (char *)(fp_download_frame(&r, idx + 1));
-		if (!buffer) {
-			fprintf(stderr, "Failed to get FP template %d\n", idx);
-			return -1;
-		}
-		fwrite(buffer, r.template_size, 1, stdout);
-		free(buffer);
-		return 0;
-	}
-	/* not an index, is it a filename ? */
-	buffer = read_file(argv[1], &size);
-	if (!buffer) {
-		fprintf(stderr, "Invalid parameter: %s\n", argv[1]);
-		return -1;
-	}
-	printf("sending template from: %s (%d bytes)\n", argv[1], size);
-	while (size) {
-		uint32_t tlen = MIN(max_chunk, size);
-
-		p->offset = offset;
-		p->size = tlen;
-		size -= tlen;
-		if (!size)
-			p->size |= FP_TEMPLATE_COMMIT;
-		memcpy(p->data, buffer + offset, tlen);
-		rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p, tlen +
-				offsetof(struct ec_params_fp_template, data),
-				NULL, 0);
-		if (rv < 0)
-			break;
-		offset += tlen;
-	}
-	if (rv < 0)
-		fprintf(stderr, "Failed with %d\n", rv);
-	else
-		rv = 0;
-	free(buffer);
-	return rv;
-}
-
-/**
- * determine if in GFU mode or not.
- *
- * NOTE, Sends HOST commands that modify ec_outbuf contents.
- *
- * @opos return value of GFU mode object position or zero if not found
- * @port port number to query
- * @return 1 if in GFU mode, 0 if not, -1 if error
- */
-static int in_gfu_mode(int *opos, int port)
-{
-	int i;
-	struct ec_params_usb_pd_get_mode_request *p =
-		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
-	struct ec_params_usb_pd_get_mode_response *r =
-		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
-	p->port = port;
-	p->svid_idx = 0;
-	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
-		if (!r->svid || (r->svid == USB_VID_GOOGLE))
-			break;
-		p->svid_idx++;
-	} while (p->svid_idx < SVID_DISCOVERY_MAX);
-
-	if (r->svid != USB_VID_GOOGLE) {
-		fprintf(stderr, "Google VID not returned\n");
-		return -1;
-	}
-
-	*opos = 0; /* invalid ... must be 1 thru 6 */
-	for (i = 0; i < PDO_MODES; i++) {
-		if (r->vdo[i] == MODE_GOOGLE_FU) {
-			*opos = i + 1;
-			break;
-		}
-	}
-
-	return r->opos == *opos;
-}
-
-/**
- * Enter GFU mode.
- *
- * NOTE, Sends HOST commands that modify ec_outbuf contents.
- *
- * @port port number to enter GFU on.
- * @return 1 if entered GFU mode, 0 if not, -1 if error
- */
-static int enter_gfu_mode(int port)
-{
-	int opos;
-	struct ec_params_usb_pd_set_mode_request *p =
-		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
-	int gfu_mode = in_gfu_mode(&opos, port);
-
-	if (gfu_mode < 0) {
-		fprintf(stderr, "Failed to query GFU mode support\n");
-		return 0;
-	} else if (!gfu_mode) {
-		if (!opos) {
-			fprintf(stderr, "Invalid object position %d\n", opos);
-			return 0;
-		}
-		p->port = port;
-		p->svid = USB_VID_GOOGLE;
-		p->opos = opos;
-		p->cmd = PD_ENTER_MODE;
-
-		ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p),
-			   NULL, 0);
-		usleep(500000); /* sleep to allow time for set mode */
-		gfu_mode = in_gfu_mode(&opos, port);
-	}
-	return gfu_mode;
-}
-
-int cmd_pd_device_info(int argc, char *argv[])
-{
-	int i, rv, port;
-	char *e;
-	struct ec_params_usb_pd_info_request *p =
-		(struct ec_params_usb_pd_info_request *)ec_outbuf;
-	struct ec_params_usb_pd_rw_hash_entry *r0 =
-		(struct ec_params_usb_pd_rw_hash_entry *)ec_inbuf;
-	struct ec_params_usb_pd_discovery_entry *r1;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
-		return -1;
-	}
-
-	port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->port = port;
-	r1 = (struct ec_params_usb_pd_discovery_entry *)ec_inbuf;
-	rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!r1->vid)
-		printf("Port:%d has no discovered device\n", port);
-	else {
-		printf("Port:%d ptype:%d vid:0x%04x pid:0x%04x\n", port,
-		       r1->ptype, r1->vid, r1->pid);
-	}
-
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		return -1;
-	}
-
-	p->port = port;
-	rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!r0->dev_id)
-		printf("Port:%d has no valid device\n", port);
-	else {
-		uint8_t *rwp = r0->dev_rw_hash;
-		printf("Port:%d DevId:%d.%d Hash:", port,
-		       HW_DEV_ID_MAJ(r0->dev_id), HW_DEV_ID_MIN(r0->dev_id));
-		for (i = 0; i < 5; i++) {
-			printf(" 0x%02x%02x%02x%02x", rwp[3], rwp[2], rwp[1],
-			       rwp[0]);
-			rwp += 4;
-		}
-		printf(" CurImg:%s\n", image_names[r0->current_image]);
-	}
-
-	return rv;
-}
-
-int cmd_flash_pd(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_fw_update *p =
-		(struct ec_params_usb_pd_fw_update *)ec_outbuf;
-	int i, dev_id, port;
-	int rv, fsize, step = 96;
-	char *e;
-	char *buf;
-	char *data = (char *)p + sizeof(*p);
-
-	if (argc < 4) {
-		fprintf(stderr, "Usage: %s <dev_id> <port> <filename>\n",
-			argv[0]);
-		return -1;
-	}
-
-	dev_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad device ID\n");
-		return -1;
-	}
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[3], &fsize);
-	if (!buf)
-		return -1;
-
-	/* Erase the current RW RSA signature */
-	fprintf(stderr, "Erasing expected RW hash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_ERASE_SIG;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	/* Reboot */
-	fprintf(stderr, "Rebooting\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_REBOOT;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	usleep(3000000); /* 3sec to reboot and get CC line idle */
-
-	/* re-enter GFU after reboot */
-	if (enter_gfu_mode(port) != 1) {
-		fprintf(stderr, "Failed to enter GFU mode\n");
-		goto pd_flash_error;
-	}
-
-	/* Erase RW flash */
-	fprintf(stderr, "Erasing RW flash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_FLASH_ERASE;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	/* 3 secs should allow ample time for 2KB page erases at 40ms */
-	usleep(3000000);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	/* Write RW flash */
-	fprintf(stderr, "Writing RW flash\n");
-	p->dev_id = dev_id;
-	p->port = port;
-	p->cmd = USB_PD_FW_FLASH_WRITE;
-	p->size = step;
-
-	for (i = 0; i < fsize; i += step) {
-		p->size = MIN(fsize - i, step);
-		memcpy(data, buf + i, p->size);
-		rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-				p, p->size + sizeof(*p), NULL, 0);
-		if (rv < 0)
-			goto pd_flash_error;
-
-		/*
-		 * TODO(crosbug.com/p/33905) throttle so EC doesn't watchdog on
-		 * other tasks.  Remove once issue resolved.
-		 */
-		usleep(10000);
-	}
-
-	/* 100msec to guarantee writes finish */
-	usleep(100000);
-
-	/* Reboot into new RW */
-	fprintf(stderr, "Rebooting PD into new RW\n");
-	p->cmd = USB_PD_FW_REBOOT;
-	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
-
-	if (rv < 0)
-		goto pd_flash_error;
-
-	free(buf);
-	fprintf(stderr, "Complete\n");
-	return 0;
-
-pd_flash_error:
-	free(buf);
-	fprintf(stderr, "PD flash error\n");
-	return -1;
-}
-
-int cmd_pd_set_amode(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_usb_pd_set_mode_request *p =
-		(struct ec_params_usb_pd_set_mode_request *)ec_outbuf;
-
-	if (argc < 5) {
-		fprintf(stderr, "Usage: %s <port> <svid> <opos> <cmd>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p->port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->svid = strtol(argv[2], &e, 0);
-	if ((e && *e) || !p->svid) {
-		fprintf(stderr, "Bad svid\n");
-		return -1;
-	}
-
-	p->opos = strtol(argv[3], &e, 0);
-	if ((e && *e) || !p->opos) {
-		fprintf(stderr, "Bad opos\n");
-		return -1;
-	}
-
-	p->cmd = strtol(argv[4], &e, 0);
-	if ((e && *e) || (p->cmd >= PD_MODE_CMD_COUNT)) {
-		fprintf(stderr, "Bad cmd\n");
-		return -1;
-	}
-	return ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0);
-}
-
-int cmd_pd_get_amode(int argc, char *argv[])
-{
-	int i;
-	char *e;
-	struct ec_params_usb_pd_get_mode_request *p =
-		(struct ec_params_usb_pd_get_mode_request *)ec_outbuf;
-	struct ec_params_usb_pd_get_mode_response *r =
-		(struct ec_params_usb_pd_get_mode_response *)ec_inbuf;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port>\n", argv[0]);
-		return -1;
-	}
-
-	p->port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p->svid_idx = 0;
-	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
-		if (!r->svid)
-			break;
-		printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ',
-		       r->svid);
-		for (i = 0; i < PDO_MODES; i++) {
-			printf("%c0x%08x ", (r->opos && (r->opos == i + 1)) ?
-			       '*' : ' ', r->vdo[i]);
-		}
-		printf("\n");
-		p->svid_idx++;
-	} while (p->svid_idx < SVID_DISCOVERY_MAX);
-	return -1;
-}
-
-/* The I/O asm funcs exist only on x86. */
-#if defined(__i386__) || defined(__x86_64__)
-#include <sys/io.h>
-
-int cmd_serial_test(int argc, char *argv[])
-{
-	const char *c = "COM2 sample serial output from host!\r\n";
-
-	printf("Writing sample serial output to COM2\n");
-
-	while (*c) {
-		/* Wait for space in transmit FIFO */
-		while (!(inb(0x2fd) & 0x20))
-			;
-
-		/* Put the next character */
-		outb(*c++, 0x2f8);
-	}
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_port_80_flood(int argc, char *argv[])
-{
-	int i;
-
-	for (i = 0; i < 256; i++)
-		outb(i, 0x80);
-	return 0;
-}
-#else
-int cmd_serial_test(int argc, char *argv[])
-{
-	printf("x86 specific command\n");
-	return -1;
-}
-
-int cmd_port_80_flood(int argc, char *argv[])
-{
-	printf("x86 specific command\n");
-	return -1;
-}
-#endif
-
-static void cmd_smart_discharge_usage(const char *command)
-{
-	printf("Usage: %s [hours_to_zero [hibern] [cutoff]]\n", command);
-	printf("\n");
-	printf("Set/Get smart discharge parameters\n");
-	printf("hours_to_zero: Desired hours for state of charge to zero\n");
-	printf("hibern: Discharge rate in hibernation (uA)\n");
-	printf("cutoff: Discharge rate in battery cutoff (uA)\n");
-}
-
-int cmd_smart_discharge(int argc, char *argv[])
-{
-	struct ec_params_smart_discharge *p =
-		(struct ec_params_smart_discharge *)(ec_outbuf);
-	struct ec_response_smart_discharge *r =
-		(struct ec_response_smart_discharge *)(ec_inbuf);
-	uint32_t cap;
-	char *e;
-	int rv;
-
-	if (argc > 1) {
-		if (strcmp(argv[1], "help") == 0) {
-			cmd_smart_discharge_usage(argv[0]);
-			return 0;
-		}
-		p->flags = EC_SMART_DISCHARGE_FLAGS_SET;
-		p->hours_to_zero = strtol(argv[1], &e, 0);
-		if (p->hours_to_zero < 0 || (e && *e)) {
-			perror("Bad value for [hours_to_zero]");
-			return -1;
-		}
-		if (argc == 4) {
-			p->drate.hibern = strtol(argv[2], &e, 0);
-			if (p->drate.hibern < 0 || (e && *e)) {
-				perror("Bad value for [hibern]");
-				return -1;
-			}
-			p->drate.cutoff = strtol(argv[3], &e, 0);
-			if (p->drate.cutoff < 0 || (e && *e)) {
-				perror("Bad value for [cutoff]");
-				return -1;
-			}
-		} else if (argc != 2) {
-			/* If argc != 4, it has to be 2. */
-			perror("Invalid number of parameters");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p),
-			r, ec_max_insize);
-	if (rv < 0) {
-		perror("ERROR: EC_CMD_SMART_DISCHARGE failed");
-		return rv;
-	}
-
-	cap = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
-	if (!is_battery_range(cap)) {
-		perror("WARN: Failed to read battery capacity");
-		cap = 0;
-	}
-
-	printf("%-27s %5d h\n", "Hours to zero capacity:", r->hours_to_zero);
-	printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:",
-	       r->dzone.stayup, cap > 0 ? r->dzone.stayup * 100 / cap : -1);
-	printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:",
-	       r->dzone.cutoff, cap > 0 ? r->dzone.cutoff * 100 / cap : -1);
-	printf("%-27s %5d uA\n", "Hibernate discharge rate:", r->drate.hibern);
-	printf("%-27s %5d uA\n", "Cutoff discharge rate:", r->drate.cutoff);
-
-	return 0;
-}
-
-/*
- * This boolean variable and handler are used for
- * catching signals that translate into a quit/shutdown
- * of a runtime loop.
- * This is used in cmd_stress_test.
- */
-static bool sig_quit;
-static void sig_quit_handler(int sig)
-{
-	sig_quit = true;
-}
-
-int cmd_stress_test(int argc, char *argv[])
-{
-	int i;
-	bool reboot = false;
-	time_t now;
-	time_t start_time, last_update_time;
-	unsigned int rand_seed = 0;
-	uint64_t round = 1, attempt = 1;
-	uint64_t failures = 0;
-
-	const int max_sleep_usec = 1000; /* 1ms */
-	const int loop_update_interval = 10000;
-
-	for (i = 1; i < argc; i++) {
-		if (strcmp(argv[i], "help") == 0) {
-			printf("Usage: %s [reboot] [help]\n", argv[0]);
-			printf("Stress tests the host command interface by"
-			       " repeatedly issuing common host commands.\n");
-			printf("The intent is to expose errors in kernel<->mcu"
-			       " communication, such as exceeding timeouts.\n");
-			printf("\n");
-			printf("reboot - Reboots the target before"
-			       " starting the stress test.\n");
-			printf("         This may force restart the host,"
-			       " if the main ec is the target.\n");
-			return 0;
-		} else if (strcmp(argv[i], "reboot") == 0) {
-			reboot = true;
-		} else {
-			fprintf(stderr, "Error - Unknown argument '%s'\n",
-				argv[i]);
-			return 1;
-		}
-	}
-
-	printf("Stress test tool version: %s %s %s\n",
-	       CROS_ECTOOL_VERSION, DATE, BUILDER);
-
-	start_time = time(NULL);
-	last_update_time = start_time;
-	printf("Start time: %s\n", ctime(&start_time));
-
-	if (reboot) {
-		printf("Issuing ec reboot. Expect a few early failed"
-		       " ioctl messages.\n");
-		ec_command(EC_CMD_REBOOT, 0, NULL, 0, NULL, 0);
-		sleep(2);
-	}
-
-	sig_quit = false;
-	signal(SIGINT, sig_quit_handler);
-	while (!sig_quit) {
-		int rv;
-		struct ec_response_get_version ver_r;
-		char *build_string = (char *)ec_inbuf;
-		struct ec_params_flash_protect flash_p;
-		struct ec_response_flash_protect flash_r;
-		struct ec_params_hello hello_p;
-		struct ec_response_hello hello_r;
-
-		/* Request EC Version Strings */
-		rv = ec_command(EC_CMD_GET_VERSION, 0,
-				NULL, 0, &ver_r, sizeof(ver_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_GET_VERSION failed");
-		}
-		ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1]
-			= '\0';
-		ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1]
-			= '\0';
-		if (strlen(ver_r.version_string_ro) == 0) {
-			failures++;
-			fprintf(stderr, "RO version string is empty\n");
-		}
-		if (strlen(ver_r.version_string_rw) == 0) {
-			failures++;
-			fprintf(stderr, "RW version string is empty\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request EC Build String */
-		rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_GET_BUILD_INFO failed");
-		}
-		build_string[ec_max_insize - 1] = '\0';
-		if (strlen(build_string) == 0) {
-			failures++;
-			fprintf(stderr, "Build string is empty\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request Flash Protect Status */
-		rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
-				&flash_p, sizeof(flash_p), &flash_r,
-				sizeof(flash_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_FLASH_PROTECT failed");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		/* Request Hello */
-		hello_p.in_data = 0xa0b0c0d0;
-		rv = ec_command(EC_CMD_HELLO, 0, &hello_p, sizeof(hello_p),
-				&hello_r, sizeof(hello_r));
-		if (rv < 0) {
-			failures++;
-			perror("ERROR: EC_CMD_HELLO failed");
-		}
-		if (hello_r.out_data != HELLO_RESP(hello_p.in_data)) {
-			failures++;
-			fprintf(stderr, "Hello response was invalid.\n");
-		}
-
-		usleep(rand_r(&rand_seed) % max_sleep_usec);
-
-		if ((attempt % loop_update_interval) == 0) {
-			now = time(NULL);
-			printf("Update: attempt %" PRIu64 " round %" PRIu64
-			       " | took %.f seconds\n",
-			       attempt, round,
-			       difftime(now, last_update_time));
-			last_update_time = now;
-		}
-
-		if (attempt++ == UINT64_MAX)
-			round++;
-	}
-	printf("\n");
-
-	now = time(NULL);
-	printf("End time:        %s\n", ctime(&now));
-	printf("Total runtime:   %.f seconds\n",
-		difftime(time(NULL), start_time));
-	printf("Total failures:  %" PRIu64 "\n", failures);
-	return 0;
-}
-
-int read_mapped_temperature(int id)
-{
-	int rv;
-
-	if (!read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION)) {
-		/*
-		 *  The temp_sensor_init() is not called, which implies no
-		 * temp sensor is defined.
-		 */
-		rv = EC_TEMP_SENSOR_NOT_PRESENT;
-	} else if (id < EC_TEMP_SENSOR_ENTRIES)
-		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR + id);
-	else if (read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION) >= 2)
-		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B +
-				      id - EC_TEMP_SENSOR_ENTRIES);
-	else {
-		/* Sensor in second bank, but second bank isn't supported */
-		rv = EC_TEMP_SENSOR_NOT_PRESENT;
-	}
-	return rv;
-}
-
-
-int cmd_temperature(int argc, char *argv[])
-{
-	int rv;
-	int id;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[1], "all") == 0) {
-		for (id = 0;
-		     id < EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES;
-		     id++) {
-			rv = read_mapped_temperature(id);
-			switch (rv) {
-			case EC_TEMP_SENSOR_NOT_PRESENT:
-				break;
-			case EC_TEMP_SENSOR_ERROR:
-				fprintf(stderr, "Sensor %d error\n", id);
-				break;
-			case EC_TEMP_SENSOR_NOT_POWERED:
-				fprintf(stderr, "Sensor %d disabled\n", id);
-				break;
-			case EC_TEMP_SENSOR_NOT_CALIBRATED:
-				fprintf(stderr, "Sensor %d not calibrated\n",
-					id);
-				break;
-			default:
-				printf("%d: %d K\n", id,
-				       rv + EC_TEMP_SENSOR_OFFSET);
-			}
-		}
-		return 0;
-	}
-
-	id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor ID.\n");
-		return -1;
-	}
-
-	if (id < 0 ||
-	    id >= EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) {
-		printf("Sensor ID invalid.\n");
-		return -1;
-	}
-
-	printf("Reading temperature...");
-	rv = read_mapped_temperature(id);
-
-	switch (rv) {
-	case EC_TEMP_SENSOR_NOT_PRESENT:
-		printf("Sensor not present\n");
-		return -1;
-	case EC_TEMP_SENSOR_ERROR:
-		printf("Error\n");
-		return -1;
-	case EC_TEMP_SENSOR_NOT_POWERED:
-		printf("Sensor disabled/unpowered\n");
-		return -1;
-	case EC_TEMP_SENSOR_NOT_CALIBRATED:
-		fprintf(stderr, "Sensor not calibrated\n");
-		return -1;
-	default:
-		printf("%d K\n", rv + EC_TEMP_SENSOR_OFFSET);
-		return 0;
-	}
-}
-
-
-int cmd_temp_sensor_info(int argc, char *argv[])
-{
-	struct ec_params_temp_sensor_get_info p;
-	struct ec_response_temp_sensor_get_info r;
-	int rv;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sensorid> | all\n", argv[0]);
-		return -1;
-	}
-
-	if (strcmp(argv[1], "all") == 0) {
-		for (p.id = 0;
-		     p.id < EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES;
-		     p.id++) {
-			if (read_mapped_temperature(p.id) ==
-			    EC_TEMP_SENSOR_NOT_PRESENT)
-				continue;
-			rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-					&p, sizeof(p), &r, sizeof(r));
-			if (rv < 0)
-				continue;
-			printf("%d: %d %s\n", p.id, r.sensor_type,
-			       r.sensor_name);
-		}
-		return 0;
-	}
-
-	p.id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor ID.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Sensor name: %s\n", r.sensor_name);
-	printf("Sensor type: %d\n", r.sensor_type);
-
-	return 0;
-}
-
-
-int cmd_thermal_get_threshold_v0(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold p;
-	struct ec_response_thermal_get_threshold r;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <sensortypeid> <thresholdid>\n", argv[0]);
-		return -1;
-	}
-
-	p.sensor_type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor type ID.\n");
-		return -1;
-	}
-
-	p.threshold_id = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold ID.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Threshold %d for sensor type %d is %d K.\n",
-			p.threshold_id, p.sensor_type, r.value);
-
-	return 0;
-}
-
-
-int cmd_thermal_set_threshold_v0(int argc, char *argv[])
-{
-	struct ec_params_thermal_set_threshold p;
-	char *e;
-	int rv;
-
-	if (argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <sensortypeid> <thresholdid> <value>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.sensor_type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad sensor type ID.\n");
-		return -1;
-	}
-
-	p.threshold_id = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold ID.\n");
-		return -1;
-	}
-
-	p.value = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad threshold value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Threshold %d for sensor type %d set to %d.\n",
-			p.threshold_id, p.sensor_type, p.value);
-
-	return 0;
-}
-
-
-int cmd_thermal_get_threshold_v1(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold_v1 p;
-	struct ec_thermal_config r;
-	struct ec_params_temp_sensor_get_info pi;
-	struct ec_response_temp_sensor_get_info ri;
-	int rv;
-	int i;
-
-	printf("sensor  warn  high  halt   fan_off fan_max   name\n");
-	for (i = 0; i < 99; i++) {	/* number of sensors is unknown */
-
-		/* ask for one */
-		p.sensor_num = i;
-		rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv <= 0)		/* stop on first failure */
-			break;
-
-		/* ask for its name, too */
-		pi.id = i;
-		rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-				&pi, sizeof(pi), &ri, sizeof(ri));
-
-		/* print what we know */
-		printf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-		       i,
-		       r.temp_host[EC_TEMP_THRESH_WARN],
-		       r.temp_host[EC_TEMP_THRESH_HIGH],
-		       r.temp_host[EC_TEMP_THRESH_HALT],
-		       r.temp_fan_off, r.temp_fan_max,
-		       rv > 0 ? ri.sensor_name : "?");
-	}
-	if (i)
-		printf("(all temps in degrees Kelvin)\n");
-
-	return 0;
-}
-
-int cmd_thermal_set_threshold_v1(int argc, char *argv[])
-{
-	struct ec_params_thermal_get_threshold_v1 p;
-	struct ec_thermal_config r;
-	struct ec_params_thermal_set_threshold_v1 s;
-	int i, n, val, rv;
-	char *e;
-
-	if (argc < 3 || argc > 7) {
-		printf("Usage: %s"
-		       " sensor warn [high [shutdown [fan_off [fan_max]]]]\n",
-		       argv[0]);
-		return 1;
-	}
-
-	n = strtod(argv[1], &e);
-	if (e && *e) {
-		printf("arg %d is invalid\n", 1);
-		return 1;
-	}
-
-	p.sensor_num = n;
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-			&p, sizeof(p), &r, sizeof(r));
-	if (rv <= 0)
-		return rv;
-
-	s.sensor_num = n;
-	s.cfg = r;
-
-	for (i = 2; i < argc; i++) {
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			printf("arg %d is invalid\n", i);
-			return 1;
-		}
-
-		if (val < 0)
-			continue;
-		switch (i) {
-		case 2:
-		case 3:
-		case 4:
-			s.cfg.temp_host[i-2] = val;
-			break;
-		case 5:
-			s.cfg.temp_fan_off = val;
-			break;
-		case 6:
-			s.cfg.temp_fan_max = val;
-			break;
-		}
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1,
-			&s, sizeof(s), NULL, 0);
-
-	return rv;
-}
-
-int cmd_thermal_get_threshold(int argc, char *argv[])
-{
-	if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 1))
-		return cmd_thermal_get_threshold_v1(argc, argv);
-	else if (ec_cmd_version_supported(EC_CMD_THERMAL_GET_THRESHOLD, 0))
-		return cmd_thermal_get_threshold_v0(argc, argv);
-
-	printf("I got nuthin.\n");
-	return -1;
-}
-
-int cmd_thermal_set_threshold(int argc, char *argv[])
-{
-	if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 1))
-		return cmd_thermal_set_threshold_v1(argc, argv);
-	else if (ec_cmd_version_supported(EC_CMD_THERMAL_SET_THRESHOLD, 0))
-		return cmd_thermal_set_threshold_v0(argc, argv);
-
-	printf("I got nuthin.\n");
-	return -1;
-}
-
-
-static int get_num_fans(void)
-{
-	int idx, rv;
-	struct ec_response_get_features r;
-
-	/*
-	 * iff the EC supports the GET_FEATURES,
-	 * check whether it has fan support enabled.
-	 */
-	rv = ec_command(EC_CMD_GET_FEATURES, 0, NULL, 0, &r, sizeof(r));
-	if (rv >= 0 && !(r.flags[0] & BIT(EC_FEATURE_PWM_FAN)))
-		return 0;
-
-	for (idx = 0; idx < EC_FAN_SPEED_ENTRIES; idx++) {
-		rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
-		if (rv == EC_FAN_SPEED_NOT_PRESENT)
-			break;
-	}
-
-	return idx;
-}
-
-int cmd_thermal_auto_fan_ctrl(int argc, char *argv[])
-{
-	int rv, num_fans;
-	struct ec_params_auto_fan_ctrl_v1 p_v1;
-	char *e;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver)
-	    || (argc == 1)) {
-		/* If no argument is provided then enable auto fan ctrl */
-		/* for all fans by using version 0 of the host command */
-
-		rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0,
-				NULL, 0, NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Automatic fan control is now on for all fans.\n");
-		return 0;
-	}
-
-	if (argc > 2 || !strcmp(argv[1], "help")) {
-		printf("Usage: %s [idx]\n", argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.fan_idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-		fprintf(stderr, "Bad fan index.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver,
-			&p_v1, sizeof(p_v1), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Automatic fan control is now on for fan %d\n", p_v1.fan_idx);
-
-	return 0;
-}
-
-static int print_fan(int idx)
-{
-	int rv = read_mapped_mem16(EC_MEMMAP_FAN + 2 * idx);
-
-	switch (rv) {
-	case EC_FAN_SPEED_NOT_PRESENT:
-		return -1;
-	case EC_FAN_SPEED_STALLED:
-		printf("Fan %d stalled!\n", idx);
-		break;
-	default:
-		printf("Fan %d RPM: %d\n", idx, rv);
-		break;
-	}
-
-	return 0;
-}
-
-int cmd_pwm_get_num_fans(int argc, char *argv[])
-{
-	int num_fans;
-
-	num_fans = get_num_fans();
-
-	printf("Number of fans = %d\n", num_fans);
-
-	return 0;
-}
-
-int cmd_pwm_get_fan_rpm(int argc, char *argv[])
-{
-	int i, num_fans;
-
-	num_fans = get_num_fans();
-	if (argc < 2 || !strcasecmp(argv[1], "all")) {
-		/* Print all the fan speeds */
-		for (i = 0; i < num_fans; i++)
-			print_fan(i);
-	} else {
-		char *e;
-		int idx;
-
-		idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || idx < 0 || idx >= num_fans) {
-			fprintf(stderr, "Bad index.\n");
-			return -1;
-		}
-
-		print_fan(idx);
-	}
-
-	return 0;
-}
-
-
-int cmd_pwm_set_fan_rpm(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_fan_target_rpm_v1 p_v1;
-	char *e;
-	int rv, num_fans;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver)) {
-		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
-
-		/* Fall back to command version 0 command */
-		cmdver = 0;
-
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <targetrpm>\n", argv[0]);
-			return -1;
-		}
-		p_v0.rpm = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad RPM.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan target RPM set for all fans.\n");
-		return 0;
-	}
-
-	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
-		printf("Usage: %s [idx] <targetrpm>\n", argv[0]);
-		printf("'%s 0 3000' - Set fan 0 RPM to 3000\n", argv[0]);
-		printf("'%s 3000' - Set all fans RPM to 3000\n", argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.rpm = strtol(argv[argc - 1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad RPM.\n");
-		return -1;
-	}
-
-	if (argc == 2) {
-		/* Reuse version 0 command if we're setting targetrpm
-		 * for all fans */
-		struct ec_params_pwm_set_fan_target_rpm_v0 p_v0;
-
-		cmdver = 0;
-		p_v0.rpm = p_v1.rpm;
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan target RPM set for all fans.\n");
-	} else {
-		p_v1.fan_idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-			fprintf(stderr, "Bad fan index.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan %d target RPM set.\n", p_v1.fan_idx);
-	}
-
-	return 0;
-}
-
-int cmd_pwm_get_keyboard_backlight(int argc, char *argv[])
-{
-	struct ec_response_pwm_get_keyboard_backlight r;
-	int rv;
-
-	rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.enabled == 1)
-		printf("Current keyboard backlight percent: %d\n", r.percent);
-	else
-		printf("Keyboard backlight disabled.\n");
-
-	return 0;
-}
-
-
-int cmd_pwm_set_keyboard_backlight(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_keyboard_backlight p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <percent>\n", argv[0]);
-		return -1;
-	}
-	p.percent = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad percent.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Keyboard backlight set.\n");
-	return 0;
-}
-
-int cmd_pwm_get_duty(int argc, char *argv[])
-{
-	struct ec_params_pwm_get_duty p;
-	struct ec_response_pwm_get_duty r;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp\n", argv[0]);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "kb")) {
-		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
-		p.index = 0;
-	} else if (!strcmp(argv[1], "disp")) {
-		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
-		p.index = 0;
-	} else {
-		p.pwm_type = EC_PWM_TYPE_GENERIC;
-		p.index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad pwm_idx\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PWM_GET_DUTY, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current PWM duty: %d\n", r.duty);
-	return 0;
-}
-
-
-int cmd_pwm_set_duty(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_duty p;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr, "Usage: %s <pwm_idx> | kb | disp <duty>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcmp(argv[1], "kb")) {
-		p.pwm_type = EC_PWM_TYPE_KB_LIGHT;
-		p.index = 0;
-	} else if (!strcmp(argv[1], "disp")) {
-		p.pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
-		p.index = 0;
-	} else {
-		p.pwm_type = EC_PWM_TYPE_GENERIC;
-		p.index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad pwm_idx\n");
-			return -1;
-		}
-	}
-
-	p.duty = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad duty.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PWM_SET_DUTY, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("PWM set.\n");
-	return 0;
-}
-
-int cmd_fanduty(int argc, char *argv[])
-{
-	struct ec_params_pwm_set_fan_duty_v1 p_v1;
-	char *e;
-	int rv, num_fans;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_PWM_SET_FAN_DUTY, cmdver)) {
-		struct ec_params_pwm_set_fan_duty_v0 p_v0;
-
-		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <percent>\n", argv[0]);
-			return -1;
-		}
-		p_v0.percent = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad percent arg.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan duty cycle set.\n");
-		return 0;
-	}
-
-	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
-		printf("Usage: %s [idx] <percent>\n", argv[0]);
-		printf("'%s 0 50' - Set fan 0 duty cycle to 50 percent\n",
-			argv[0]);
-		printf("'%s 30' - Set all fans duty cycle to 30 percent\n",
-			argv[0]);
-		return -1;
-	}
-
-	num_fans = get_num_fans();
-	p_v1.percent = strtol(argv[argc - 1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad percent arg.\n");
-		return -1;
-	}
-
-	if (argc == 2) {
-		/* Reuse version 0 command if we're setting duty cycle
-		 * for all fans */
-		struct ec_params_pwm_set_fan_duty_v0 p_v0;
-
-		cmdver = 0;
-		p_v0.percent = p_v1.percent;
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan duty cycle set for all fans.\n");
-	} else {
-		p_v1.fan_idx = strtol(argv[1], &e, 0);
-		if ((e && *e) || (p_v1.fan_idx >= num_fans)) {
-			fprintf(stderr, "Bad fan index.\n");
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Fan %d duty cycle set.\n", p_v1.fan_idx);
-	}
-
-	return 0;
-}
-
-#define LBMSG(state) #state
-#include "lightbar_msg_list.h"
-static const char * const lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
-#undef LBMSG
-
-/* Size of field <FLD> in structure <ST> */
-#define ST_FLD_SIZE(ST, FLD) sizeof(((struct ST *)0)->FLD)
-
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_lightbar, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_lightbar, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_lightbar, SUBCMD)
-
-static const struct {
-	uint8_t insize;
-	uint8_t outsize;
-} lb_command_paramcount[] = {
-	{ ST_CMD_SIZE, ST_RSP_SIZE(dump) },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_PRM_SIZE(set_brightness), 0},
-	{ ST_PRM_SIZE(seq), 0},
-	{ ST_PRM_SIZE(reg), 0},
-	{ ST_PRM_SIZE(set_rgb), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_seq) },
-	{ ST_PRM_SIZE(demo), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v0) },
-	{ ST_PRM_SIZE(set_params_v0), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(version) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_brightness) },
-	{ ST_PRM_SIZE(get_rgb), ST_RSP_SIZE(get_rgb) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_demo) },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v1) },
-	{ ST_PRM_SIZE(set_params_v1), 0},
-	{ ST_PRM_SIZE(set_program), 0},
-	{ ST_PRM_SIZE(manual_suspend_ctrl), 0},
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, 0 },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_timing) },
-	{ ST_PRM_SIZE(set_v2par_timing), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_tap) },
-	{ ST_PRM_SIZE(set_v2par_tap), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_osc) },
-	{ ST_PRM_SIZE(set_v2par_osc), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_bright) },
-	{ ST_PRM_SIZE(set_v2par_bright), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_thlds) },
-	{ ST_PRM_SIZE(set_v2par_thlds), 0},
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_colors) },
-	{ ST_PRM_SIZE(set_v2par_colors), 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-
-static int lb_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                         - dump all regs\n", cmd);
-	printf("  %s off                     - enter standby\n", cmd);
-	printf("  %s on                      - leave standby\n", cmd);
-	printf("  %s init                    - load default vals\n", cmd);
-	printf("  %s brightness [NUM]        - get/set intensity(0-ff)\n", cmd);
-	printf("  %s seq [NUM|SEQUENCE]      - run given pattern"
-		 " (no arg for list)\n", cmd);
-	printf("  %s CTRL REG VAL            - set LED controller regs\n", cmd);
-	printf("  %s LED RED GREEN BLUE      - set color manually"
-		 " (LED=4 for all)\n", cmd);
-	printf("  %s LED                     - get current LED color\n", cmd);
-	printf("  %s demo [0|1]              - turn demo mode on & off\n", cmd);
-	printf("  %s params [setfile]        - get params"
-	       " (or set from file)\n", cmd);
-	printf("  %s params2 group [setfile] - get params by group\n"
-	       " (or set from file)\n", cmd);
-	printf("  %s program file            - load program from file\n", cmd);
-	return 0;
-}
-
-static uint8_t lb_find_msg_by_name(const char *str)
-{
-	uint8_t i;
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		if (!strcasecmp(str, lightbar_cmds[i]))
-			return i;
-
-	return LIGHTBAR_NUM_SEQUENCES;
-}
-
-static int lb_do_cmd(enum lightbar_command cmd,
-		     struct ec_params_lightbar *in,
-		     struct ec_response_lightbar *out)
-{
-	int rv;
-	in->cmd = cmd;
-	rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0,
-			in, lb_command_paramcount[cmd].insize,
-			out, lb_command_paramcount[cmd].outsize);
-	return (rv < 0 ? rv : 0);
-}
-
-static int lb_show_msg_names(void)
-{
-	int i, current_state;
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-
-	i = lb_do_cmd(LIGHTBAR_CMD_GET_SEQ, &param, &resp);
-	if (i < 0)
-		return i;
-	current_state = resp.get_seq.num;
-
-	printf("sequence names:");
-	for (i = 0; i < LIGHTBAR_NUM_SEQUENCES; i++)
-		printf(" %s", lightbar_cmds[i]);
-	printf("\nCurrent = 0x%x %s\n", current_state,
-	       lightbar_cmds[current_state]);
-
-	return 0;
-}
-
-static int lb_read_params_v0_from_file(const char *filename,
-				       struct lightbar_params_v0 *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-
-	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->new_s0 = val[0];
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_params_v0(const struct lightbar_params_v0 *p)
-{
-	int i;
-
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .new_s0\n", p->new_s0);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_read_params_v1_from_file(const char *filename,
-				       struct lightbar_params_v1 *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-
-	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
-	READ(3);
-	p->tap_idx[0] = val[0];
-	p->tap_idx[1] = val[1];
-	p->tap_idx[2] = val[2];
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_params_v1(const struct lightbar_params_v1 *p)
-{
-	int i;
-
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
-	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
-	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
-	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
-	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
-	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
-	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
-	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_rd_timing_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_timing *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_tap_v2par_from_file(const char *filename,
-				     struct lightbar_params_v2_tap *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
-	READ(3);
-	p->tap_idx[0] = val[0];
-	p->tap_idx[1] = val[1];
-	p->tap_idx[2] = val[2];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_osc_v2par_from_file(const char *filename,
-				     struct lightbar_params_v2_oscillation *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(2);
-	p->osc_min[0] = val[0];
-	p->osc_min[1] = val[1];
-	READ(2);
-	p->osc_max[0] = val[0];
-	p->osc_max[1] = val[1];
-	READ(2);
-	p->w_ofs[0] = val[0];
-	p->w_ofs[1] = val[1];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_bright_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_brightness *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(2);
-	p->bright_bl_off_fixed[0] = val[0];
-	p->bright_bl_off_fixed[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_min[0] = val[0];
-	p->bright_bl_on_min[1] = val[1];
-
-	READ(2);
-	p->bright_bl_on_max[0] = val[0];
-	p->bright_bl_on_max[1] = val[1];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_thlds_v2par_from_file(const char *filename,
-				       struct lightbar_params_v2_thresholds *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(3);
-	p->battery_threshold[0] = val[0];
-	p->battery_threshold[1] = val[1];
-	p->battery_threshold[2] = val[2];
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static int lb_rd_colors_v2par_from_file(const char *filename,
-					struct lightbar_params_v2_colors *p)
-{
-	FILE *fp;
-	char buf[80];
-	int val[4];
-	int r = 1;
-	int line = 0;
-	int want, got;
-	int i;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
-	} while (0)
-
-	READ(4);
-	p->s0_idx[0][0] = val[0];
-	p->s0_idx[0][1] = val[1];
-	p->s0_idx[0][2] = val[2];
-	p->s0_idx[0][3] = val[3];
-
-	READ(4);
-	p->s0_idx[1][0] = val[0];
-	p->s0_idx[1][1] = val[1];
-	p->s0_idx[1][2] = val[2];
-	p->s0_idx[1][3] = val[3];
-
-	READ(4);
-	p->s3_idx[0][0] = val[0];
-	p->s3_idx[0][1] = val[1];
-	p->s3_idx[0][2] = val[2];
-	p->s3_idx[0][3] = val[3];
-
-	READ(4);
-	p->s3_idx[1][0] = val[0];
-	p->s3_idx[1][1] = val[1];
-	p->s3_idx[1][2] = val[2];
-	p->s3_idx[1][3] = val[3];
-	for (i = 0; i < ARRAY_SIZE(p->color); i++) {
-		READ(3);
-		p->color[i].r = val[0];
-		p->color[i].g = val[1];
-		p->color[i].b = val[2];
-	}
-
-#undef READ
-
-	/* Yay */
-	r = 0;
-done:
-	if (r)
-		fprintf(stderr, "problem with line %d: wanted %d, got %d\n",
-			line, want, got);
-	fclose(fp);
-	return r;
-}
-
-static void lb_show_v2par_timing(const struct lightbar_params_v2_timing *p)
-{
-	printf("%d\t\t# .google_ramp_up\n", p->google_ramp_up);
-	printf("%d\t\t# .google_ramp_down\n", p->google_ramp_down);
-	printf("%d\t\t# .s3s0_ramp_up\n", p->s3s0_ramp_up);
-	printf("%d\t\t# .s0_tick_delay (battery)\n", p->s0_tick_delay[0]);
-	printf("%d\t\t# .s0_tick_delay (AC)\n", p->s0_tick_delay[1]);
-	printf("%d\t\t# .s0a_tick_delay (battery)\n", p->s0a_tick_delay[0]);
-	printf("%d\t\t# .s0a_tick_delay (AC)\n", p->s0a_tick_delay[1]);
-	printf("%d\t\t# .s0s3_ramp_down\n", p->s0s3_ramp_down);
-	printf("%d\t\t# .s3_sleep_for\n", p->s3_sleep_for);
-	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
-	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
-	printf("%d\t\t# .tap_tick_delay\n", p->tap_tick_delay);
-	printf("%d\t\t# .tap_gate_delay\n", p->tap_gate_delay);
-	printf("%d\t\t# .tap_display_time\n", p->tap_display_time);
-}
-
-static void lb_show_v2par_tap(const struct lightbar_params_v2_tap *p)
-{
-	printf("%d\t\t# .tap_pct_red\n", p->tap_pct_red);
-	printf("%d\t\t# .tap_pct_green\n", p->tap_pct_green);
-	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
-	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
-	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
-}
-
-static void lb_show_v2par_osc(const struct lightbar_params_v2_oscillation *p)
-{
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
-}
-
-static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p)
-{
-	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
-	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
-	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
-	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
-	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-}
-
-static void lb_show_v2par_thlds(const struct lightbar_params_v2_thresholds *p)
-{
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-}
-
-static void lb_show_v2par_colors(const struct lightbar_params_v2_colors *p)
-{
-	int i;
-
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
-
-	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
-}
-
-static int lb_load_program(const char *filename, struct lightbar_program *prog)
-{
-	FILE *fp;
-	size_t got;
-	int rc;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
-		return 1;
-	}
-
-	rc = fseek(fp, 0, SEEK_END);
-	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
-		fclose(fp);
-		return 1;
-	}
-	rc = (int) ftell(fp);
-	if (rc > EC_LB_PROG_LEN) {
-		fprintf(stderr, "File %s is too long, aborting\n", filename);
-		fclose(fp);
-		return 1;
-	}
-	rewind(fp);
-
-	memset(prog->data, 0, EC_LB_PROG_LEN);
-	got = fread(prog->data, 1, EC_LB_PROG_LEN, fp);
-	if (rc != got)
-		fprintf(stderr, "Warning: did not read entire file\n");
-	prog->size = got;
-	fclose(fp);
-	return 0;
-}
-
-static int cmd_lightbar_params_v0(int argc, char **argv)
-{
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-	int r;
-
-	if (argc > 2) {
-		r = lb_read_params_v0_from_file(argv[2],
-						&param.set_params_v0);
-		if (r)
-			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0,
-				 &param, &resp);
-	}
-	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V0, &param, &resp);
-	if (!r)
-		lb_show_params_v0(&resp.get_params_v0);
-	return r;
-}
-
-static int cmd_lightbar_params_v1(int argc, char **argv)
-{
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-	int r;
-
-	if (argc > 2) {
-		r = lb_read_params_v1_from_file(argv[2],
-						&param.set_params_v1);
-		if (r)
-			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1,
-				 &param, &resp);
-	}
-	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V1, &param, &resp);
-	if (!r)
-		lb_show_params_v1(&resp.get_params_v1);
-	return r;
-}
-
-static void lb_param_v2_help(void)
-{
-	printf("Usage:\n");
-	printf("lightbar params2 group [setfile]\n");
-	printf("group list:\n");
-	printf("  timing\n");
-	printf("  tap\n");
-	printf("  oscillation\n");
-	printf("  brightness\n");
-	printf("  thresholds\n");
-	printf("  colors\n");
-
-	return;
-}
-
-static int cmd_lightbar_params_v2(int argc, char **argv)
-{
-	struct ec_params_lightbar p;
-	struct ec_response_lightbar resp;
-	int r = 0;
-	int set = 0;
-
-	memset(&p, 0, sizeof(struct ec_params_lightbar));
-	memset(&resp, 0, sizeof(struct ec_response_lightbar));
-
-	if (argc < 3) {
-		lb_param_v2_help();
-		return 1;
-	}
-
-	/* Set new params if provided with a setfile */
-	if (argc > 3)
-		set = 1;
-
-	/* Show selected v2 params */
-	if (!strncasecmp(argv[2], "timing", 6)) {
-		if (set) {
-			r = lb_rd_timing_v2par_from_file(argv[3],
-							 &p.set_v2par_timing);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TIMING, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_timing(&resp.get_params_v2_timing);
-	} else if (!strcasecmp(argv[2], "tap")) {
-		if (set) {
-			r = lb_rd_tap_v2par_from_file(argv[3],
-						      &p.set_v2par_tap);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_TAP, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_tap(&resp.get_params_v2_tap);
-	} else if (!strncasecmp(argv[2], "oscillation", 11)) {
-		if (set) {
-			r = lb_rd_osc_v2par_from_file(argv[3],
-						      &p.set_v2par_osc);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_osc(&resp.get_params_v2_osc);
-	} else if (!strncasecmp(argv[2], "brightness", 10)) {
-		if (set) {
-			r = lb_rd_bright_v2par_from_file(argv[3],
-							 &p.set_v2par_bright);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_bright(&resp.get_params_v2_bright);
-	} else if (!strncasecmp(argv[2], "thresholds", 10)) {
-		if (set) {
-			r = lb_rd_thlds_v2par_from_file(argv[3],
-							&p.set_v2par_thlds);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p,
-			      &resp);
-		if (r)
-			return r;
-		lb_show_v2par_thlds(&resp.get_params_v2_thlds);
-	} else if (!strncasecmp(argv[2], "colors", 6)) {
-		if (set) {
-			r = lb_rd_colors_v2par_from_file(argv[3],
-							 &p.set_v2par_colors);
-			if (r)
-				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS,
-				      &p, &resp);
-			if (r)
-				return r;
-		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_COLORS, &p, &resp);
-		if (r)
-			return r;
-		lb_show_v2par_colors(&resp.get_params_v2_colors);
-	} else {
-		lb_param_v2_help();
-	}
-
-	return r;
-}
-
-static int cmd_lightbar(int argc, char **argv)
-{
-	int i, r;
-	struct ec_params_lightbar param;
-	struct ec_response_lightbar resp;
-
-	if (1 == argc) {		/* no args = dump 'em all */
-		r = lb_do_cmd(LIGHTBAR_CMD_DUMP, &param, &resp);
-		if (r)
-			return r;
-		for (i = 0; i < ARRAY_SIZE(resp.dump.vals); i++) {
-			printf(" %02x     %02x     %02x\n",
-			       resp.dump.vals[i].reg,
-			       resp.dump.vals[i].ic0,
-			       resp.dump.vals[i].ic1);
-		}
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "init"))
-		return lb_do_cmd(LIGHTBAR_CMD_INIT, &param, &resp);
-
-	if (argc == 2 && !strcasecmp(argv[1], "off"))
-		return lb_do_cmd(LIGHTBAR_CMD_OFF, &param, &resp);
-
-	if (argc == 2 && !strcasecmp(argv[1], "on"))
-		return lb_do_cmd(LIGHTBAR_CMD_ON, &param, &resp);
-
-	if (!strcasecmp(argv[1], "params0"))
-		return cmd_lightbar_params_v0(argc, argv);
-
-	if (!strcasecmp(argv[1], "params1"))
-		return cmd_lightbar_params_v1(argc, argv);
-
-	if (!strcasecmp(argv[1], "params2"))
-		return cmd_lightbar_params_v2(argc, argv);
-
-	if (!strcasecmp(argv[1], "params")) {
-		/* Just try them both */
-		fprintf(stderr, "trying params1 ...\n");
-		if (0 == cmd_lightbar_params_v1(argc, argv))
-			return 0;
-		fprintf(stderr, "trying params0 ...\n");
-		return cmd_lightbar_params_v0(argc, argv);
-	}
-
-	if (!strcasecmp(argv[1], "version")) {
-		r = lb_do_cmd(LIGHTBAR_CMD_VERSION, &param, &resp);
-		if (!r)
-			printf("version %d flags 0x%x\n",
-			       resp.version.num, resp.version.flags);
-		return r;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "brightness")) {
-		char *e;
-		int rv;
-		if (argc > 2) {
-			param.set_brightness.num = 0xff &
-				strtoull(argv[2], &e, 16);
-			return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS,
-					 &param, &resp);
-		}
-		rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS,
-			       &param, &resp);
-		if (rv)
-			return rv;
-		printf("%02x\n", resp.get_brightness.num);
-		return 0;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "demo")) {
-		int rv;
-		if (argc > 2) {
-			if (!strcasecmp(argv[2], "on") || argv[2][0] == '1')
-				param.demo.num = 1;
-			else if (!strcasecmp(argv[2], "off") ||
-				 argv[2][0] == '0')
-				param.demo.num = 0;
-			else {
-				fprintf(stderr, "Invalid arg\n");
-				return -1;
-			}
-			return lb_do_cmd(LIGHTBAR_CMD_DEMO, &param, &resp);
-		}
-
-		rv = lb_do_cmd(LIGHTBAR_CMD_GET_DEMO, &param, &resp);
-		if (rv)
-			return rv;
-		printf("%s\n", resp.get_demo.num ? "on" : "off");
-		return 0;
-	}
-
-	if (argc >= 2 && !strcasecmp(argv[1], "seq")) {
-		char *e;
-		uint8_t num;
-		if (argc == 2)
-			return lb_show_msg_names();
-		num = 0xff & strtoull(argv[2], &e, 16);
-		if (e && *e)
-			num = lb_find_msg_by_name(argv[2]);
-		if (num >= LIGHTBAR_NUM_SEQUENCES) {
-			fprintf(stderr, "Invalid arg\n");
-			return -1;
-		}
-		param.seq.num = num;
-		return lb_do_cmd(LIGHTBAR_CMD_SEQ, &param, &resp);
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "program")) {
-		lb_load_program(argv[2], &param.set_program);
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PROGRAM, &param, &resp);
-	}
-
-	if (argc == 4) {
-		char *e;
-		param.reg.ctrl = 0xff & strtoull(argv[1], &e, 16);
-		param.reg.reg = 0xff & strtoull(argv[2], &e, 16);
-		param.reg.value = 0xff & strtoull(argv[3], &e, 16);
-		return lb_do_cmd(LIGHTBAR_CMD_REG, &param, &resp);
-	}
-
-	if (argc == 5) {
-		char *e;
-		param.set_rgb.led = strtoull(argv[1], &e, 16);
-		param.set_rgb.red = strtoull(argv[2], &e, 16);
-		param.set_rgb.green = strtoull(argv[3], &e, 16);
-		param.set_rgb.blue = strtoull(argv[4], &e, 16);
-		return lb_do_cmd(LIGHTBAR_CMD_SET_RGB, &param, &resp);
-	}
-
-	/* Only thing left is to try to read an LED value */
-	if (argc == 2) {
-		char *e;
-		param.get_rgb.led = strtoull(argv[1], &e, 0);
-		if (!(e && *e)) {
-			r = lb_do_cmd(LIGHTBAR_CMD_GET_RGB, &param, &resp);
-			if (r)
-				return r;
-			printf("%02x %02x %02x\n",
-			       resp.get_rgb.red,
-			       resp.get_rgb.green,
-			       resp.get_rgb.blue);
-			return 0;
-		}
-	}
-
-	return lb_help(argv[0]);
-}
-
-/* Create an array to store sizes of motion sense param and response structs. */
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_motion_sense, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_motion_sense, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_motion_sense, SUBCMD)
-#define ST_BOTH_SIZES(SUBCMD) { ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) }
-
-/*
- * For ectool only, assume no more than 16 sensors.  More advanced
- * implementation would allocate the right amount of memory depending on the
- * number of sensors.
- */
-#define ECTOOL_MAX_SENSOR 16
-
-static const struct {
-	uint8_t outsize;
-	uint8_t insize;
-} ms_command_sizes[] = {
-	{
-		ST_PRM_SIZE(dump),
-		ST_RSP_SIZE(dump) +
-		sizeof(struct ec_response_motion_sensor_data) *
-		ECTOOL_MAX_SENSOR
-	},
-	ST_BOTH_SIZES(info_4),
-	ST_BOTH_SIZES(ec_rate),
-	ST_BOTH_SIZES(sensor_odr),
-	ST_BOTH_SIZES(sensor_range),
-	ST_BOTH_SIZES(kb_wake_angle),
-	ST_BOTH_SIZES(data),
-	{
-		ST_CMD_SIZE,
-		ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR
-	},
-	ST_BOTH_SIZES(fifo_flush),
-	ST_BOTH_SIZES(fifo_read),
-	ST_BOTH_SIZES(perform_calib),
-	ST_BOTH_SIZES(sensor_offset),
-	ST_BOTH_SIZES(list_activities),
-	{ ST_PRM_SIZE(set_activity), 0 },
-	{ ST_CMD_SIZE, ST_RSP_SIZE(lid_angle) },
-	ST_BOTH_SIZES(fifo_int_enable),
-	ST_BOTH_SIZES(spoof),
-	ST_BOTH_SIZES(tablet_mode_threshold),
-	ST_BOTH_SIZES(sensor_scale),
-	ST_BOTH_SIZES(online_calib_read),
-	ST_BOTH_SIZES(get_activity),
-};
-BUILD_ASSERT(ARRAY_SIZE(ms_command_sizes) == MOTIONSENSE_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-#undef ST_BOTH_SIZES
-
-static int ms_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                              - dump all motion data\n",
-		cmd);
-	printf("  %s active                       - print active flag\n", cmd);
-	printf("  %s info NUM                     - print sensor info\n", cmd);
-	printf("  %s ec_rate [RATE_MS]            - set/get sample rate\n",
-		cmd);
-	printf("  %s odr NUM [ODR [ROUNDUP]]      - set/get sensor ODR\n",
-		cmd);
-	printf("  %s range NUM [RANGE [ROUNDUP]]  - set/get sensor range\n",
-		cmd);
-	printf("  %s offset NUM [-- X Y Z [TEMP]] - set/get sensor offset\n",
-		cmd);
-	printf("  %s kb_wake NUM                  - set/get KB wake ang\n",
-		cmd);
-	printf("  %s fifo_info                    - print fifo info\n", cmd);
-	printf("  %s fifo_int_enable [0/1]        - enable/disable/get fifo "
-		"interrupt status\n", cmd);
-	printf("  %s fifo_read MAX_DATA           - read fifo data\n", cmd);
-	printf("  %s fifo_flush NUM               - trigger fifo interrupt\n",
-		cmd);
-	printf("  %s list_activities              - list supported "
-		"activities\n", cmd);
-	printf("  %s set_activity ACT EN          - enable/disable activity\n",
-		cmd);
-	printf("  %s get_activity ACT             - get activity status\n",
-		cmd);
-	printf("  %s lid_angle                    - print lid angle\n", cmd);
-	printf("  %s spoof -- NUM [0/1] [X Y Z]   - enable/disable spoofing\n",
-		cmd);
-	printf("  %s spoof -- NUM activity ACT [0/1] [STATE] - enable/disable "
-		"activity spoofing\n", cmd);
-	printf("  %s tablet_mode_angle ANG HYS    - set/get tablet mode "
-		"angle\n", cmd);
-	printf("  %s calibrate NUM                - run sensor calibration\n",
-		cmd);
-
-	return 0;
-}
-
-static void motionsense_display_activities(uint32_t activities)
-{
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_SIG_MOTION))
-		printf("%d: Significant motion\n",
-		       MOTIONSENSE_ACTIVITY_SIG_MOTION);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP))
-		printf("%d: Double tap\n",
-		       MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_ORIENTATION))
-		printf("%d: Orientation\n",
-		       MOTIONSENSE_ACTIVITY_ORIENTATION);
-	if (activities & BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION))
-		printf("%d: Body Detection\n",
-		       MOTIONSENSE_ACTIVITY_BODY_DETECTION);
-}
-
-static int cmd_motionsense(int argc, char **argv)
-{
-	int i, rv, status_only = (argc == 2);
-	struct ec_params_motion_sense param;
-	/* The largest size using resp as a response buffer */
-	uint8_t resp_buffer[ms_command_sizes[MOTIONSENSE_CMD_DUMP].insize];
-	struct ec_response_motion_sense *resp =
-		(struct ec_response_motion_sense *)resp_buffer;
-	char *e;
-	/*
-	 * Warning: the following strings printed out are read in an
-	 * autotest. Do not change string without consulting autotest
-	 * for kernel_CrosECSysfsAccel.
-	 */
-	const char *motion_status_string[2][2] = {
-		{ "Motion sensing inactive", "0"},
-		{ "Motion sensing active", "1"},
-	};
-
-	/* No motionsense command has more than 7 args. */
-	if (argc > 7)
-		return ms_help(argv[0]);
-
-	if ((argc == 1) ||
-	    (argc == 2 && !strcasecmp(argv[1], "active"))) {
-		param.cmd = MOTIONSENSE_CMD_DUMP;
-		param.dump.max_sensor_count = ECTOOL_MAX_SENSOR;
-		rv = ec_command(
-			EC_CMD_MOTION_SENSE_CMD, 1,
-			&param, ms_command_sizes[param.cmd].outsize,
-			resp, ms_command_sizes[param.cmd].insize);
-		if (rv > 0) {
-			printf("%s\n", motion_status_string[
-					!!(resp->dump.module_flags &
-					   MOTIONSENSE_MODULE_FLAG_ACTIVE)][
-					status_only]);
-			if (status_only)
-				return 0;
-
-			if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR) {
-				printf("Too many sensors to handle: %d",
-						resp->dump.sensor_count);
-				return -1;
-			}
-			for (i = 0; i < resp->dump.sensor_count; i++) {
-				/*
-				 * Warning: the following string printed out
-				 * is read by an autotest. Do not change string
-				 * without consulting autotest for
-				 * kernel_CrosECSysfsAccel.
-				 */
-				printf("Sensor %d: ", i);
-				if (resp->dump.sensor[i].flags &
-						MOTIONSENSE_SENSOR_FLAG_PRESENT)
-					printf("%d\t%d\t%d\n",
-						resp->dump.sensor[i].data[0],
-						resp->dump.sensor[i].data[1],
-						resp->dump.sensor[i].data[2]);
-				else
-					printf("None\n");
-			}
-			return 0;
-		} else {
-			return rv;
-		}
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "info")) {
-		int version = 0;
-
-		rv = get_latest_cmd_version(EC_CMD_MOTION_SENSE_CMD, &version);
-		if (rv < 0)
-			return rv;
-
-		param.cmd = MOTIONSENSE_CMD_INFO;
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Type:     ");
-		switch (resp->info.type) {
-		case MOTIONSENSE_TYPE_ACCEL:
-			printf("accel\n");
-			break;
-		case MOTIONSENSE_TYPE_GYRO:
-			printf("gyro\n");
-			break;
-		case MOTIONSENSE_TYPE_MAG:
-			printf("magnetometer\n");
-			break;
-		case MOTIONSENSE_TYPE_LIGHT:
-			printf("light\n");
-			break;
-		case MOTIONSENSE_TYPE_LIGHT_RGB:
-			printf("rgb light\n");
-			break;
-		case MOTIONSENSE_TYPE_PROX:
-			printf("proximity\n");
-			break;
-		case MOTIONSENSE_TYPE_ACTIVITY:
-			printf("activity\n");
-			break;
-		case MOTIONSENSE_TYPE_BARO:
-			printf("barometer\n");
-			break;
-		case MOTIONSENSE_TYPE_SYNC:
-			printf("sync\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		printf("Location: ");
-		switch (resp->info.location) {
-		case MOTIONSENSE_LOC_BASE:
-			printf("base\n");
-			break;
-		case MOTIONSENSE_LOC_LID:
-			printf("lid\n");
-			break;
-		case MOTIONSENSE_LOC_CAMERA:
-			printf("camera\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		printf("Chip:     ");
-		switch (resp->info.chip) {
-		case MOTIONSENSE_CHIP_KXCJ9:
-			printf("kxcj9\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DS0:
-			printf("lsm6ds0\n");
-			break;
-		case MOTIONSENSE_CHIP_BMI160:
-			printf("bmi160\n");
-			break;
-		case MOTIONSENSE_CHIP_SI1141:
-			printf("si1141\n");
-			break;
-		case MOTIONSENSE_CHIP_KX022:
-			printf("kx022\n");
-			break;
-		case MOTIONSENSE_CHIP_L3GD20H:
-			printf("l3gd20h\n");
-			break;
-		case MOTIONSENSE_CHIP_BMA255:
-			printf("bma255\n");
-			break;
-		case MOTIONSENSE_CHIP_BMP280:
-			printf("bmp280\n");
-			break;
-		case MOTIONSENSE_CHIP_OPT3001:
-			printf("opt3001\n");
-			break;
-		case MOTIONSENSE_CHIP_BH1730:
-			printf("bh1730\n");
-			break;
-		case MOTIONSENSE_CHIP_GPIO:
-			printf("gpio\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DH:
-			printf("lis2dh\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DSM:
-			printf("lsm6dsm\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DE:
-			printf("lis2de\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2MDL:
-			printf("lis2mdl\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DS3:
-			printf("lsm6ds3\n");
-			break;
-		case MOTIONSENSE_CHIP_LSM6DSO:
-			printf("lsm6dso\n");
-			break;
-		case MOTIONSENSE_CHIP_LNG2DM:
-			printf("lng2dm\n");
-			break;
-		case MOTIONSENSE_CHIP_TCS3400:
-			printf("tcs3400\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DW12:
-			printf("lis2dw12\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DWL:
-			printf("lis2dwl\n");
-			break;
-		case MOTIONSENSE_CHIP_LIS2DS:
-			printf("lis2ds\n");
-			break;
-		case MOTIONSENSE_CHIP_BMI260:
-			printf("bmi260\n");
-			break;
-		case MOTIONSENSE_CHIP_ICM426XX:
-			printf("icm426xx\n");
-			break;
-		case MOTIONSENSE_CHIP_ICM42607:
-			printf("icm42607\n");
-			break;
-		case MOTIONSENSE_CHIP_BMI323:
-			printf("bmi323\n");
-			break;
-		case MOTIONSENSE_CHIP_BMA422:
-			printf("bma422\n");
-			break;
-		default:
-			printf("unknown\n");
-		}
-
-		if (version >= 3) {
-			printf("Min Frequency:              %d mHz\n",
-				resp->info_3.min_frequency);
-			printf("Max Frequency:              %d mHz\n",
-				resp->info_3.max_frequency);
-			printf("FIFO Max Event Count:       %d\n",
-				resp->info_3.fifo_max_event_count);
-		}
-		if (version >= 4) {
-			printf("Flags:                      %d\n",
-			       resp->info_4.flags);
-		}
-		return 0;
-	}
-
-	if (argc < 4 && !strcasecmp(argv[1], "ec_rate")) {
-		param.cmd = MOTIONSENSE_CMD_EC_RATE;
-		param.ec_rate.data = EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 3) {
-			param.ec_rate.data = strtol(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->ec_rate.ret);
-		return 0;
-	}
-
-	if (argc > 2 && !strcasecmp(argv[1], "odr")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_ODR;
-		param.sensor_odr.data = EC_MOTION_SENSE_NO_VALUE;
-		param.sensor_odr.roundup = 1;
-
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			param.sensor_odr.data = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		}
-
-		if (argc == 5) {
-			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[4]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->sensor_odr.ret);
-		return 0;
-	}
-
-	if (argc > 2 && !strcasecmp(argv[1], "range")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_RANGE;
-		param.sensor_range.data = EC_MOTION_SENSE_NO_VALUE;
-		param.sensor_range.roundup = 1;
-
-		param.sensor_range.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			param.sensor_range.data = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		}
-
-		if (argc == 5) {
-			param.sensor_odr.roundup = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[4]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->sensor_range.ret);
-		return 0;
-	}
-
-	if (argc < 4 && !strcasecmp(argv[1], "kb_wake")) {
-		param.cmd = MOTIONSENSE_CMD_KB_WAKE_ANGLE;
-		param.kb_wake_angle.data = EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 3) {
-			param.kb_wake_angle.data = strtol(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->kb_wake_angle.ret);
-		return 0;
-	}
-
-	if (argc < 5 && !strcasecmp(argv[1], "tablet_mode_angle")) {
-		param.cmd = MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE;
-		/*
-		 * EC_MOTION_SENSE_NO_VALUE indicates to the EC that host is
-		 * attempting to only read the current values.
-		 */
-		param.tablet_mode_threshold.lid_angle =
-			EC_MOTION_SENSE_NO_VALUE;
-		param.tablet_mode_threshold.hys_degree =
-			EC_MOTION_SENSE_NO_VALUE;
-
-		if (argc == 4) {
-			param.tablet_mode_threshold.lid_angle = strtol(argv[2],
-								     &e, 0);
-
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[2]);
-				return -1;
-			}
-
-			param.tablet_mode_threshold.hys_degree = strtol(argv[3],
-								     &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-		} else if (argc != 2) {
-			return ms_help(argv[0]);
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("tablet_mode_angle=%d hys=%d\n",
-		       resp->tablet_mode_threshold.lid_angle,
-		       resp->tablet_mode_threshold.hys_degree);
-
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "fifo_info")) {
-		int sensor_count;
-
-		param.cmd = MOTIONSENSE_CMD_DUMP;
-		param.dump.max_sensor_count = 0;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		sensor_count = resp->dump.sensor_count;
-
-		param.cmd = MOTIONSENSE_CMD_FIFO_INFO;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Size:     %d\n", resp->fifo_info.size);
-		printf("Count:    %d\n", resp->fifo_info.count);
-		printf("Timestamp:%" PRIx32 "\n", resp->fifo_info.timestamp);
-		printf("Total lost: %d\n", resp->fifo_info.total_lost);
-		for (i = 0; i < sensor_count; i++) {
-			int lost = resp->fifo_info.lost[i];
-			if (lost != 0)
-				printf("Lost %d:     %d\n", i, lost);
-		}
-		return 0;
-	}
-
-	if (argc >= 2 && !strcasecmp(argv[1], "fifo_int_enable")) {
-		param.cmd = MOTIONSENSE_CMD_FIFO_INT_ENABLE;
-		if (argc == 3)
-			param.fifo_int_enable.enable = strtol(argv[2], &e, 0);
-		else
-			param.fifo_int_enable.enable = EC_MOTION_SENSE_NO_VALUE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("%d\n", resp->fifo_int_enable.ret);
-		return 0;
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "fifo_read")) {
-		/* large number to test fragmentation */
-		struct {
-			uint32_t number_data;
-			struct ec_response_motion_sensor_data data[512];
-		} fifo_read_buffer = {
-			.number_data = UINT32_MAX,
-		};
-		int print_data = 0,  max_data = strtol(argv[2], &e, 0);
-
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-		while (fifo_read_buffer.number_data != 0 &&
-		       print_data < max_data) {
-			struct ec_response_motion_sensor_data *vector;
-			param.cmd = MOTIONSENSE_CMD_FIFO_READ;
-			param.fifo_read.max_data_vector =
-				MIN(ARRAY_SIZE(fifo_read_buffer.data),
-				    max_data - print_data);
-
-			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-					&param,
-					ms_command_sizes[param.cmd].outsize,
-					&fifo_read_buffer, ec_max_insize);
-			if (rv < 0)
-				return rv;
-
-			print_data += fifo_read_buffer.number_data;
-			for (i = 0; i < fifo_read_buffer.number_data; i++) {
-				vector = &fifo_read_buffer.data[i];
-				if (vector->flags &
-					(MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
-					 MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
-
-					printf("Timestamp:%" PRIx32 "%s\n",
-						vector->timestamp,
-						(vector->flags &
-						 MOTIONSENSE_SENSOR_FLAG_FLUSH ?
-						 " - Flush" : ""));
-				} else {
-					printf("Sensor %d: %d\t%d\t%d "
-					       "(as uint16: %u\t%u\t%u)\n",
-						vector->sensor_num,
-						vector->data[0],
-						vector->data[1],
-						vector->data[2],
-						vector->data[0],
-						vector->data[1],
-						vector->data[2]);
-				}
-			}
-		}
-		return 0;
-	}
-	if (argc == 3 && !strcasecmp(argv[1], "fifo_flush")) {
-		param.cmd = MOTIONSENSE_CMD_FIFO_FLUSH;
-
-		param.sensor_odr.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		return rv < 0 ? rv : 0;
-	}
-
-	if (argc == 3 && !strcasecmp(argv[1], "calibrate")) {
-		param.cmd = MOTIONSENSE_CMD_PERFORM_CALIB;
-		param.perform_calib.enable = 1;
-		param.perform_calib.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("--- Calibrated well ---\n");
-		printf("New offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->perform_calib.offset[0],
-			resp->perform_calib.offset[1],
-			resp->perform_calib.offset[2]);
-		if ((uint16_t)resp->perform_calib.temp ==
-		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
-			printf("Temperature at calibration unknown\n");
-		else
-			printf("Temperature at calibration: %d.%02d C\n",
-			       resp->perform_calib.temp / 100,
-			       resp->perform_calib.temp % 100);
-		return 0;
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "offset")) {
-		param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET;
-		param.sensor_offset.flags = 0;
-		param.sensor_offset.temp = EC_MOTION_SENSE_INVALID_CALIB_TEMP;
-
-		param.sensor_offset.sensor_num = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-
-		if (argc >= 4) {
-			/* Regarded as a command to set offset */
-			if (argc >= 6 && argc < 8) {
-				/* Set offset : X, Y, Z */
-				param.sensor_offset.flags = MOTION_SENSE_SET_OFFSET;
-				for (i = 0; i < 3; i++) {
-					param.sensor_offset.offset[i] = strtol(argv[3+i], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[3+i]);
-						return -1;
-					}
-				}
-				if (argc == 7) {
-					/* Set offset : Temperature */
-					param.sensor_offset.temp = strtol(argv[6], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[6]);
-						return -1;
-					}
-				}
-			} else {
-				return ms_help(argv[0]);
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-
-		if (rv < 0)
-			return rv;
-
-		printf("Offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->sensor_offset.offset[0],
-			resp->sensor_offset.offset[1],
-			resp->sensor_offset.offset[2]);
-		if ((uint16_t)resp->sensor_offset.temp ==
-		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
-			printf("temperature at calibration unknown\n");
-		else
-			printf("temperature at calibration: %d.%02d C\n",
-			       resp->sensor_offset.temp / 100,
-			       resp->sensor_offset.temp % 100);
-		return 0;
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "list_activities")) {
-		param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Enabled:\n");
-		motionsense_display_activities(resp->list_activities.enabled);
-		printf("Disabled:\n");
-		motionsense_display_activities(resp->list_activities.disabled);
-		return 0;
-	}
-	if (argc == 4 && !strcasecmp(argv[1], "set_activity")) {
-		param.cmd = MOTIONSENSE_CMD_SET_ACTIVITY;
-		param.set_activity.activity = strtol(argv[2], &e, 0);
-		param.set_activity.enable = strtol(argv[3], &e, 0);
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		return 0;
-	}
-	if (argc == 3 && !strcasecmp(argv[1], "get_activity")) {
-		param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY;
-		param.get_activity.activity = strtol(argv[2], &e, 0);
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-		printf("State: %d\n", resp->get_activity.state);
-		return 0;
-	}
-	if (argc == 2 && !strcasecmp(argv[1], "lid_angle")) {
-		param.cmd = MOTIONSENSE_CMD_LID_ANGLE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Lid angle: ");
-		if (resp->lid_angle.value == LID_ANGLE_UNRELIABLE)
-			printf("unreliable\n");
-		else
-			printf("%d\n", resp->lid_angle.value);
-
-		return 0;
-	}
-
-	if (argc >= 3 && !strcasecmp(argv[1], "spoof")) {
-		param.cmd = MOTIONSENSE_CMD_SPOOF;
-		/* By default, just query the current spoof status. */
-		param.spoof.spoof_enable = MOTIONSENSE_SPOOF_MODE_QUERY;
-		param.spoof.sensor_id = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad %s arg.\n", argv[2]);
-			return -1;
-		}
-		/* spoof activity state */
-		if (argc >= 5 && !strcasecmp(argv[3], "activity")) {
-			int enable = 0;
-
-			param.spoof.activity_num = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Base %s arg.\n", argv[4]);
-				return -1;
-			}
-			if (argc >= 6) {
-				enable = strtol(argv[5], &e, 0);
-				if ((e && *e) || (enable != 0 && enable != 1)) {
-					fprintf(stderr, "Bad %s arg.\n",
-						argv[5]);
-					return -1;
-				}
-			}
-			if ((enable == 1) && (argc == 6)) {
-				/* Enable spoofing, but lock to current state */
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT;
-			} else if ((enable == 1) && (argc == 7)) {
-				/* Enable spoofing, but use provided state */
-				int state = strtol(argv[6], &e, 0);
-
-				if ((e && *e) || (state != 0 && state != 1)) {
-					fprintf(stderr, "Bad %s arg.\n",
-						argv[6]);
-					return -1;
-				}
-				param.spoof.activity_state = state;
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_CUSTOM;
-			} else if ((enable == 0) && (argc == 6)) {
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_DISABLE;
-			} else if (argc != 5) {
-				return ms_help(argv[0]);
-			}
-		/* spoof accel data */
-		} else if (argc >= 4) {
-			int enable, i;
-			int16_t val;
-
-			enable = strtol(argv[3], &e, 0);
-			if ((e && *e) || (enable != 0 && enable != 1)) {
-				fprintf(stderr, "Bad %s arg.\n", argv[3]);
-				return -1;
-			}
-
-			if ((enable == 1) && (argc == 4)) {
-				/*
-				 * Enable spoofing, but lock to current sensor
-				 * values.
-				 */
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT;
-			} else if ((enable == 1) && (argc == 7)) {
-				/*
-				 * Enable spoofing, but use provided component
-				 * values.
-				 */
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_CUSTOM;
-				for (i = 0; i < 3; i++) {
-					val = strtol(argv[4+i], &e, 0);
-					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n",
-							argv[4+i]);
-						return -1;
-					}
-					param.spoof.components[i] = val;
-				}
-			} else if (enable == 0) {
-				param.spoof.spoof_enable =
-					MOTIONSENSE_SPOOF_MODE_DISABLE;
-			} else {
-				return ms_help(argv[0]);
-			}
-		}
-
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
-		if (rv < 0)
-			return rv;
-
-		if (param.spoof.spoof_enable == MOTIONSENSE_SPOOF_MODE_QUERY)
-			/*
-			 * Response is the current spoof status of the
-			 * sensor.
-			 */
-			printf("Sensor %d spoof mode is %s.\n",
-			       param.spoof.sensor_id,
-			       resp->spoof.ret ? "enabled" : "disabled");
-
-		return 0;
-	}
-
-	return ms_help(argv[0]);
-}
-
-int cmd_next_event(int argc, char *argv[])
-{
-	uint8_t *rdata = (uint8_t *)ec_inbuf;
-	int rv;
-	int i;
-
-	rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0,
-			NULL, 0, rdata, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	printf("Next event is 0x%02x\n", rdata[0]);
-	if (rv > 1) {
-		printf("Event data:\n");
-		for (i = 1; i < rv; ++i) {
-			printf("%02x ", rdata[i]);
-			if (!(i & 0xf))
-				printf("\n");
-		}
-		printf("\n");
-	}
-
-	return 0;
-}
-
-static int find_led_color_by_name(const char *color)
-{
-	int i;
-
-	for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
-		if (!strcasecmp(color, led_color_names[i]))
-			return i;
-
-	return -1;
-}
-
-static int find_led_id_by_name(const char *led)
-{
-	int i;
-
-	for (i = 0; i < EC_LED_ID_COUNT; ++i)
-		if (!strcasecmp(led, led_names[i]))
-			return i;
-
-	return -1;
-}
-
-int cmd_led(int argc, char *argv[])
-{
-	struct ec_params_led_control p;
-	struct ec_response_led_control r;
-	char *e, *ptr;
-	int rv, i, j;
-
-	memset(p.brightness, 0, sizeof(p.brightness));
-	p.flags = 0;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <name> <query | auto | "
-			"off | <color> | <color>=<value>...>\n", argv[0]);
-		return -1;
-	}
-
-	p.led_id = find_led_id_by_name(argv[1]);
-	if (p.led_id == (uint8_t)-1) {
-		fprintf(stderr, "Bad LED name: %s\n", argv[1]);
-		fprintf(stderr, "Valid LED names: ");
-		for (i = 0; i < EC_LED_ID_COUNT; i++)
-			fprintf(stderr, "%s ", led_names[i]);
-		fprintf(stderr, "\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[2], "query")) {
-		p.flags = EC_LED_FLAGS_QUERY;
-		rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p),
-				&r, sizeof(r));
-		printf("Brightness range for LED %d:\n", p.led_id);
-		if (rv < 0) {
-			fprintf(stderr, "Error: Unsupported LED.\n");
-			return rv;
-		}
-		for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
-			printf("\t%s\t: 0x%x\n",
-			       led_color_names[i],
-			       r.brightness_range[i]);
-		return 0;
-	}
-
-	if (!strcasecmp(argv[2], "off")) {
-		/* Brightness initialized to 0 for each color. */
-	} else if (!strcasecmp(argv[2], "auto")) {
-		p.flags = EC_LED_FLAGS_AUTO;
-	} else if ((i = find_led_color_by_name(argv[2])) != -1) {
-		p.brightness[i] = 0xff;
-	} else {
-		for (i = 2; i < argc; ++i) {
-			ptr = strtok(argv[i], "=");
-			j = find_led_color_by_name(ptr);
-			if (j == -1) {
-				fprintf(stderr, "Bad color name: %s\n", ptr);
-				fprintf(stderr, "Valid colors: ");
-				for (j = 0; j < EC_LED_COLOR_COUNT; j++)
-					fprintf(stderr, "%s ",
-						led_color_names[j]);
-				fprintf(stderr, "\n");
-				return -1;
-			}
-			ptr = strtok(NULL, "=");
-			if (ptr == NULL) {
-				fprintf(stderr, "Missing brightness value\n");
-				return -1;
-			}
-			p.brightness[j] = strtol(ptr, &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad brightness: %s\n", ptr);
-				return -1;
-			}
-		}
-	}
-
-	rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r, sizeof(r));
-	return (rv < 0 ? rv : 0);
-}
-
-
-int cmd_usb_charge_set_mode(int argc, char *argv[])
-{
-	struct ec_params_usb_charge_set_mode p;
-	char *e;
-	int rv;
-
-	if (argc != 3 && argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <port_id> <mode_id> [<inhibit_charge>]\n",
-			argv[0]);
-		return -1;
-	}
-	p.usb_port_id = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port ID.\n");
-		return -1;
-	}
-	p.mode = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mode ID.\n");
-		return -1;
-	}
-	p.inhibit_charge = 0;
-	if (argc == 4) {
-		p.inhibit_charge = strtol(argv[3], &e, 0);
-		if ((e && *e) || (p.inhibit_charge != 0 &&
-			p.inhibit_charge != 1)) {
-			fprintf(stderr, "Bad value\n");
-			return -1;
-		}
-	}
-
-	printf("Setting port %d to mode %d inhibit_charge %d...\n",
-		p.usb_port_id, p.mode, p.inhibit_charge);
-
-	rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("USB charging mode set.\n");
-	return 0;
-}
-
-
-int cmd_usb_mux(int argc, char *argv[])
-{
-	struct ec_params_usb_mux p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mux>\n", argv[0]);
-		return -1;
-	}
-
-	p.mux = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mux value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_USB_MUX, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Set USB mux to 0x%x.\n", p.mux);
-
-	return 0;
-}
-
-
-int cmd_usb_pd(int argc, char *argv[])
-{
-	const char *role_str[] = {"", "toggle", "toggle-off", "sink", "source",
-				  "freeze"};
-	const char *mux_str[] = {"", "none", "usb", "dp", "dock", "auto"};
-	const char *swap_str[] = {"", "dr_swap", "pr_swap", "vconn_swap"};
-	struct ec_params_usb_pd_control p;
-	struct ec_response_usb_pd_control_v2 *r_v2 =
-		(struct ec_response_usb_pd_control_v2 *)ec_inbuf;
-	struct ec_response_usb_pd_control_v1 *r_v1 =
-		(struct ec_response_usb_pd_control_v1 *)ec_inbuf;
-	struct ec_response_usb_pd_control *r =
-		(struct ec_response_usb_pd_control *)ec_inbuf;
-	int rv, i, j;
-	int option_ok;
-	char *e;
-	int cmdver;
-
-	BUILD_ASSERT(ARRAY_SIZE(role_str) == USB_PD_CTRL_ROLE_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(mux_str) == USB_PD_CTRL_MUX_COUNT);
-	BUILD_ASSERT(ARRAY_SIZE(swap_str) == USB_PD_CTRL_SWAP_COUNT);
-	p.role = USB_PD_CTRL_ROLE_NO_CHANGE;
-	p.mux = USB_PD_CTRL_MUX_NO_CHANGE;
-	p.swap = USB_PD_CTRL_SWAP_NONE;
-
-	if (argc < 2) {
-		fprintf(stderr, "No port specified.\n");
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Invalid param (port)\n");
-		return -1;
-	}
-
-	for (i = 2; i < argc; ++i) {
-		option_ok = 0;
-		if (!strcmp(argv[i], "auto")) {
-			if (argc != 3) {
-				fprintf(stderr, "\"auto\" may not be used "
-						"with other options.\n");
-				return -1;
-			}
-			p.role = USB_PD_CTRL_ROLE_TOGGLE_ON;
-			p.mux = USB_PD_CTRL_MUX_AUTO;
-			continue;
-		}
-
-		for (j = 0; j < ARRAY_SIZE(role_str); ++j) {
-			if (!strcmp(argv[i], role_str[j])) {
-				if (p.role != USB_PD_CTRL_ROLE_NO_CHANGE) {
-					fprintf(stderr,
-						"Only one role allowed.\n");
-					return -1;
-				}
-				p.role = j;
-				option_ok = 1;
-				break;
-			}
-		}
-		if (option_ok)
-			continue;
-
-		for (j = 0; j < ARRAY_SIZE(mux_str); ++j) {
-			if (!strcmp(argv[i], mux_str[j])) {
-				if (p.mux != USB_PD_CTRL_MUX_NO_CHANGE) {
-					fprintf(stderr,
-						"Only one mux type allowed.\n");
-					return -1;
-				}
-				p.mux = j;
-				option_ok = 1;
-				break;
-			}
-		}
-		if (option_ok)
-			continue;
-
-		for (j = 0; j < ARRAY_SIZE(swap_str); ++j) {
-			if (!strcmp(argv[i], swap_str[j])) {
-				if (p.swap != USB_PD_CTRL_SWAP_NONE) {
-					fprintf(stderr,
-						"Only one swap type allowed.\n");
-					return -1;
-				}
-				p.swap = j;
-				option_ok = 1;
-				break;
-			}
-		}
-
-
-		if (!option_ok) {
-			fprintf(stderr, "Unknown option: %s\n", argv[i]);
-			return -1;
-		}
-	}
-
-	if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 2))
-		cmdver = 2;
-	else if (ec_cmd_version_supported(EC_CMD_USB_PD_CONTROL, 1))
-		cmdver = 1;
-	else
-		cmdver = 0;
-
-	rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-
-	if (rv < 0 || argc != 2)
-		return (rv < 0) ? rv : 0;
-
-	if (cmdver == 0) {
-		printf("Port C%d is %sabled, Role:%s Polarity:CC%d State:%d\n",
-		       p.port, (r->enabled) ? "en" : "dis",
-		       r->role == PD_ROLE_SOURCE ? "SRC" : "SNK",
-		       r->polarity + 1, r->state);
-	} else {
-		printf("Port C%d: %s, %s  State:%s\n"
-		       "Role:%s %s%s, Polarity:CC%d\n",
-		       p.port,
-		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_COMMS) ?
-				"enabled" : "disabled",
-		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) ?
-				"connected" : "disconnected",
-		       r_v1->state,
-
-		       (r_v1->role & PD_CTRL_RESP_ROLE_POWER) ? "SRC" : "SNK",
-		       (r_v1->role & PD_CTRL_RESP_ROLE_DATA) ? "DFP" : "UFP",
-		       (r_v1->role & PD_CTRL_RESP_ROLE_VCONN) ? " VCONN" : "",
-		       r_v1->polarity + 1);
-
-		if (cmdver == 2) {
-			printf("CC State:");
-			if (r_v2->cc_state == PD_CC_NONE)
-				printf("None");
-			else if (r_v2->cc_state == PD_CC_UFP_AUDIO_ACC)
-				printf("UFP Audio accessory");
-			else if (r_v2->cc_state == PD_CC_UFP_DEBUG_ACC)
-				printf("UFP Debug accessory");
-			else if (r_v2->cc_state == PD_CC_UFP_ATTACHED)
-				printf("UFP attached");
-			else if (r_v2->cc_state == PD_CC_DFP_DEBUG_ACC)
-				printf("DFP Debug accessory");
-			else if (r_v2->cc_state == PD_CC_DFP_ATTACHED)
-				printf("DFP attached");
-			else
-				printf("UNKNOWN");
-			printf("\n");
-
-			if (r_v2->dp_mode) {
-				printf("DP pin mode:");
-				if (r_v2->dp_mode == MODE_DP_PIN_A)
-					printf("A");
-				else if (r_v2->dp_mode == MODE_DP_PIN_B)
-					printf("B");
-				else if (r_v2->dp_mode == MODE_DP_PIN_C)
-					printf("C");
-				else if (r_v2->dp_mode == MODE_DP_PIN_D)
-					printf("D");
-				else if (r_v2->dp_mode == MODE_DP_PIN_E)
-					printf("E");
-				else if (r_v2->dp_mode == MODE_DP_PIN_F)
-					printf("F");
-				else
-					printf("UNKNOWN");
-				printf("\n");
-			}
-
-			printf("Cable type:%s\n",
-				r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ?
-					"Active" : "Passive");
-
-			printf("TBT Adapter type:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_TBT_LEGACY_ADAPTER ?
-					"Legacy" : "Gen3");
-
-			printf("Optical Cable:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_OPTICAL_CABLE ? "True" : "False");
-
-			printf("Link LSRX Communication:%s-directional\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_ACTIVE_LINK_UNIDIR ? "Uni" : "Bi");
-
-			printf("TBT Cable Speed:");
-			switch (r_v2->cable_speed) {
-			case TBT_SS_U31_GEN1:
-				printf("TBT Gen1");
-				break;
-			case TBT_SS_U32_GEN1_GEN2:
-				printf("TBT Gen1 and TBT Gen2");
-				break;
-			case TBT_SS_TBT_GEN3:
-				printf("TBT Gen3");
-				break;
-			default:
-				printf("UNKNOWN");
-			}
-			printf("\n");
-
-			printf("Rounded support: 3rd Gen %srounded support\n",
-				r_v2->cable_gen ? "and 4th Gen " : "");
-		}
-		/* If connected to a PD device, then print port partner info */
-		if ((r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) &&
-		    (r_v1->enabled & PD_CTRL_RESP_ENABLED_PD_CAPABLE))
-			printf("PD Partner Capabilities:\n%s%s%s%s",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ?
-					" DR power\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ?
-					" DR data\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ?
-					" USB capable\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ?
-					" Unconstrained power\n" : "");
-	}
-	return 0;
-}
-
-static void print_pd_power_info(struct ec_response_usb_pd_power_info *r)
-{
-	switch (r->role) {
-	case USB_PD_PORT_POWER_DISCONNECTED:
-		printf("Disconnected");
-		break;
-	case USB_PD_PORT_POWER_SOURCE:
-		printf("SRC");
-		break;
-	case USB_PD_PORT_POWER_SINK:
-		printf("SNK");
-		break;
-	case USB_PD_PORT_POWER_SINK_NOT_CHARGING:
-		printf("SNK (not charging)");
-		break;
-	default:
-		printf("Unknown");
-	}
-
-	if ((r->role == USB_PD_PORT_POWER_SOURCE) &&
-	    (r->meas.current_max))
-		printf(" %dmA", r->meas.current_max);
-
-	if ((r->role == USB_PD_PORT_POWER_DISCONNECTED) ||
-	    (r->role == USB_PD_PORT_POWER_SOURCE)) {
-		printf("\n");
-		return;
-	}
-
-	printf(r->dualrole ? " DRP" : " Charger");
-	switch (r->type) {
-	case USB_CHG_TYPE_PD:
-		printf(" PD");
-		break;
-	case USB_CHG_TYPE_C:
-		printf(" Type-C");
-		break;
-	case USB_CHG_TYPE_PROPRIETARY:
-		printf(" Proprietary");
-		break;
-	case USB_CHG_TYPE_BC12_DCP:
-		printf(" DCP");
-		break;
-	case USB_CHG_TYPE_BC12_CDP:
-		printf(" CDP");
-		break;
-	case USB_CHG_TYPE_BC12_SDP:
-		printf(" SDP");
-		break;
-	case USB_CHG_TYPE_OTHER:
-		printf(" Other");
-		break;
-	case USB_CHG_TYPE_VBUS:
-		printf(" VBUS");
-		break;
-	case USB_CHG_TYPE_UNKNOWN:
-		printf(" Unknown");
-		break;
-	}
-	printf(" %dmV / %dmA, max %dmV / %dmA",
-		r->meas.voltage_now, r->meas.current_lim, r->meas.voltage_max,
-		r->meas.current_max);
-	if (r->max_power)
-		printf(" / %dmW", r->max_power / 1000);
-	printf("\n");
-}
-
-int cmd_usb_pd_mux_info(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_mux_info p;
-	struct ec_response_usb_pd_mux_info r;
-	int num_ports, rv, i;
-
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-	num_ports = ((struct ec_response_usb_pd_ports *)ec_inbuf)->num_ports;
-
-	for (i = 0; i < num_ports; i++) {
-		p.port = i;
-		rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0,
-				&p, sizeof(p),
-				&r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("Port %d: ", i);
-		printf("USB=%d ", !!(r.flags & USB_PD_MUX_USB_ENABLED));
-		printf("DP=%d ", !!(r.flags & USB_PD_MUX_DP_ENABLED));
-		printf("POLARITY=%s ", r.flags & USB_PD_MUX_POLARITY_INVERTED ?
-					"INVERTED" : "NORMAL");
-		printf("HPD_IRQ=%d ", !!(r.flags & USB_PD_MUX_HPD_IRQ));
-		printf("HPD_LVL=%d ", !!(r.flags & USB_PD_MUX_HPD_LVL));
-		printf("SAFE=%d ", !!(r.flags & USB_PD_MUX_SAFE_MODE));
-		printf("TBT=%d ", !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED));
-		printf("USB4=%d ", !!(r.flags & USB_PD_MUX_USB4_ENABLED));
-		printf("\n");
-	}
-
-	return 0;
-}
-
-int cmd_usb_pd_power(int argc, char *argv[])
-{
-	struct ec_params_usb_pd_power_info p;
-	struct ec_response_usb_pd_power_info *r =
-		(struct ec_response_usb_pd_power_info *)ec_inbuf;
-	int num_ports, i, rv;
-	char *e;
-
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-	num_ports = ((struct ec_response_usb_pd_ports *)r)->num_ports;
-
-	if (argc < 2) {
-		for (i = 0; i < num_ports; i++) {
-			p.port = i;
-			rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-					&p, sizeof(p),
-					ec_inbuf, ec_max_insize);
-			if (rv < 0)
-				return rv;
-
-			printf("Port %d: ", i);
-			print_pd_power_info(r);
-		}
-	} else {
-		p.port = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad port.\n");
-			return -1;
-		}
-		rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-				&p, sizeof(p),
-				ec_inbuf, ec_max_insize);
-		if (rv < 0)
-			return rv;
-
-		printf("Port %d: ", p.port);
-		print_pd_power_info(r);
-	}
-
-	return 0;
-}
-
-int cmd_kbpress(int argc, char *argv[])
-{
-	struct ec_params_mkbp_simulate_key p;
-	char *e;
-	int rv;
-
-	if (argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <row> <col> <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.row = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad row.\n");
-		return -1;
-	}
-	p.col = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad column.\n");
-		return -1;
-	}
-	p.pressed = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad pressed flag.\n");
-		return -1;
-	}
-
-	printf("%s row %d col %d.\n", p.pressed ? "Pressing" : "Releasing",
-				      p.row,
-				      p.col);
-
-	rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-	printf("Done.\n");
-	return 0;
-}
-
-int cmd_keyboard_factory_test(int argc, char *argv[])
-{
-	struct ec_response_keyboard_factory_test r;
-	int rv;
-
-	rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.shorted != 0)
-		printf("Keyboard %d and %d pin are shorted.\n",
-				r.shorted & 0x00ff, r.shorted >> 8);
-	else
-		printf("Keyboard factory test passed.\n");
-
-	return 0;
-}
-
-int cmd_panic_info(int argc, char *argv[])
-{
-	int rv;
-
-	rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (rv == 0) {
-		printf("No panic data.\n");
-		return 0;
-	}
-
-	return parse_panic_info((char *)(ec_inbuf), rv);
-}
-
-
-int cmd_power_info(int argc, char *argv[])
-{
-	struct ec_response_power_info_v1 r;
-	int rv;
-
-	rv = ec_command(EC_CMD_POWER_INFO, 1, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Power source:\t");
-	switch (r.system_power_source) {
-	case POWER_SOURCE_UNKNOWN:
-		printf("Unknown\n");
-		break;
-	case POWER_SOURCE_BATTERY:
-		printf("Battery\n");
-		break;
-	case POWER_SOURCE_AC:
-		printf("AC\n");
-		break;
-	case POWER_SOURCE_AC_BATTERY:
-		printf("AC + battery\n");
-		break;
-	}
-
-	printf("Battery state-of-charge: %d%%\n", r.battery_soc);
-	printf("Max AC power: %d Watts\n", r.ac_adapter_100pct);
-	printf("Battery 1Cd rate: %d\n", r.battery_1cd);
-	printf("RoP Avg: %d Watts\n", r.rop_avg);
-	printf("RoP Peak: %d Watts\n", r.rop_peak);
-	printf("Battery DBPT support level: %d\n",
-	       r.intel.batt_dbpt_support_level);
-	printf("Battery DBPT Max Peak Power: %d Watts\n",
-	       r.intel.batt_dbpt_max_peak_power);
-	printf("Battery DBPT Sus Peak Power: %d Watts\n",
-	       r.intel.batt_dbpt_sus_peak_power);
-	return 0;
-}
-
-
-int cmd_pse(int argc, char *argv[])
-{
-	struct ec_params_pse p;
-	struct ec_response_pse_status r;
-	int rsize = 0;
-	char *e;
-	int rv;
-
-	if (argc < 2 || argc > 3 || !strcmp(argv[1], "help")) {
-		printf("Usage: %s <port> [<subcmd>]\n", argv[0]);
-		printf("'pse <port> [status]' - Get port status\n");
-		printf("'pse <port> disable' - Disable port\n");
-		printf("'pse <port> enable' - Enable port\n");
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	if (argc == 2 || !strcmp(argv[2], "status")) {
-		p.cmd = EC_PSE_STATUS;
-		rsize = sizeof(r);
-	} else if (!strcmp(argv[2], "disable")) {
-		p.cmd = EC_PSE_DISABLE;
-	} else if (!strcmp(argv[2], "enable")) {
-		p.cmd = EC_PSE_ENABLE;
-	} else {
-		fprintf(stderr, "Unknown command: %s\n", argv[2]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_PSE, 0, &p, sizeof(p), &r, rsize);
-	if (rv < 0)
-		return rv;
-
-	if (p.cmd == EC_PSE_STATUS) {
-		const char *status;
-
-		switch (r.status) {
-		case EC_PSE_STATUS_DISABLED:
-			status = "disabled";
-			break;
-		case EC_PSE_STATUS_ENABLED:
-			status = "enabled";
-			break;
-		case EC_PSE_STATUS_POWERED:
-			status = "powered";
-			break;
-		default:
-			status = "unknown";
-			break;
-		}
-
-		printf("Port %d: %s\n", p.port, status);
-	}
-
-	return 0;
-}
-
-
-int cmd_pstore_info(int argc, char *argv[])
-{
-	struct ec_response_pstore_info r;
-	int rv;
-
-	rv = ec_command(EC_CMD_PSTORE_INFO, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("PstoreSize %d\nAccessSize %d\n", r.pstore_size, r.access_size);
-	return 0;
-}
-
-
-int cmd_pstore_read(int argc, char *argv[])
-{
-	struct ec_params_pstore_read p;
-	uint8_t rdata[EC_PSTORE_SIZE_MAX];
-	int offset, size;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-
-	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > 0x10000) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	size = strtol(argv[2], &e, 0);
-	if ((e && *e) || size <= 0 || size > 0x10000) {
-		fprintf(stderr, "Bad size.\n");
-		return -1;
-	}
-	printf("Reading %d bytes at offset %d...\n", size, offset);
-
-	buf = (char *)malloc(size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-
-	/* Read data in chunks */
-	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
-		rv = ec_command(EC_CMD_PSTORE_READ, 0,
-				&p, sizeof(p), rdata, sizeof(rdata));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-		memcpy(buf + i, rdata, p.size);
-	}
-
-	rv = write_file(argv[3], buf, size);
-	free(buf);
-	if (rv)
-		return rv;
-
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_pstore_write(int argc, char *argv[])
-{
-	struct ec_params_pstore_write p;
-	int offset, size;
-	int rv;
-	int i;
-	char *e;
-	char *buf;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <offset> <filename>\n", argv[0]);
-		return -1;
-	}
-	offset = strtol(argv[1], &e, 0);
-	if ((e && *e) || offset < 0 || offset > 0x10000) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	/* Read the input file */
-	buf = read_file(argv[2], &size);
-	if (!buf)
-		return -1;
-
-	printf("Writing to offset %d...\n", offset);
-
-	/* Write data in chunks */
-	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
-		p.offset = offset + i;
-		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
-		memcpy(p.data, buf + i, p.size);
-		rv = ec_command(EC_CMD_PSTORE_WRITE, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "Write error at offset %d\n", i);
-			free(buf);
-			return rv;
-		}
-	}
-
-	free(buf);
-	printf("done.\n");
-	return 0;
-}
-
-
-int cmd_host_event_get_raw(int argc, char *argv[])
-{
-	uint32_t events = read_mapped_mem32(EC_MEMMAP_HOST_EVENTS);
-
-	if (events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
-		printf("Current host events: invalid\n");
-		return -1;
-	}
-
-	printf("Current host events: 0x%08x\n", events);
-	return 0;
-}
-
-
-int cmd_host_event_get_b(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (rv < sizeof(r)) {
-		fprintf(stderr, "Insufficient data received.\n");
-		return -1;
-	}
-
-	if (r.mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) {
-		printf("Current host events-B: invalid\n");
-		return -1;
-	}
-
-	printf("Current host events-B: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_smi_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event SMI mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_sci_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event SCI mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_get_wake_mask(int argc, char *argv[])
-{
-	struct ec_response_host_event_mask r;
-	int rv;
-
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0,
-			NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current host event wake mask: 0x%08x\n", r.mask);
-	return 0;
-}
-
-
-int cmd_host_event_set_smi_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_set_sci_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_set_wake_mask(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Mask set.\n");
-	return 0;
-}
-
-
-int cmd_host_event_clear(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Host events cleared.\n");
-	return 0;
-}
-
-
-int cmd_host_event_clear_b(int argc, char *argv[])
-{
-	struct ec_params_host_event_mask p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <mask>\n", argv[0]);
-		return -1;
-	}
-	p.mask = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad mask.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Host events-B cleared.\n");
-	return 0;
-}
-
-
-int cmd_switches(int argc, char *argv[])
-{
-	uint8_t s = read_mapped_mem8(EC_MEMMAP_SWITCHES);
-	printf("Current switches:   0x%02x\n", s);
-	printf("Lid switch:         %s\n",
-	       (s & EC_SWITCH_LID_OPEN ? "OPEN" : "CLOSED"));
-	printf("Power button:       %s\n",
-	       (s & EC_SWITCH_POWER_BUTTON_PRESSED ? "DOWN" : "UP"));
-	printf("Write protect:      %sABLED\n",
-	       (s & EC_SWITCH_WRITE_PROTECT_DISABLED ? "DIS" : "EN"));
-	printf("Dedicated recovery: %sABLED\n",
-	       (s & EC_SWITCH_DEDICATED_RECOVERY ? "EN" : "DIS"));
-
-	return 0;
-}
-
-
-int cmd_wireless(int argc, char *argv[])
-{
-	char *e;
-	int rv;
-	int now_flags;
-
-	if (argc < 2) {
-		fprintf(stderr,
-			"Usage: %s <flags> [<mask> [<susflags> <susmask>]]\n",
-			argv[0]);
-		fprintf(stderr, "  0x1 = WLAN radio\n"
-				"  0x2 = Bluetooth radio\n"
-				"  0x4 = WWAN power\n"
-				"  0x8 = WLAN power\n");
-		return -1;
-	}
-
-	now_flags = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad flags.\n");
-		return -1;
-	}
-
-	if (argc < 3) {
-		/* Old-style - current flags only */
-		struct ec_params_switch_enable_wireless_v0 p;
-
-		p.enabled = now_flags;
-		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0)
-			return rv;
-
-		printf("Success.\n");
-	} else {
-		/* New-style - masks and suspend flags */
-		struct ec_params_switch_enable_wireless_v1 p;
-		struct ec_response_switch_enable_wireless_v1 r;
-
-		memset(&p, 0, sizeof(p));
-
-		p.now_flags = now_flags;
-
-		p.now_mask = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad mask.\n");
-			return -1;
-		}
-
-		if (argc > 4) {
-			p.suspend_flags = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad suspend flags.\n");
-				return -1;
-			}
-
-			p.suspend_mask = strtol(argv[4], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad suspend mask.\n");
-				return -1;
-			}
-		}
-
-		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS,
-				EC_VER_SWITCH_ENABLE_WIRELESS,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("Now=0x%x, suspend=0x%x\n",
-		       r.now_flags, r.suspend_flags);
-	}
-
-	return 0;
-}
-
-
-int cmd_i2c_protect(int argc, char *argv[])
-{
-	struct ec_params_i2c_passthru_protect p;
-	char *e;
-	int rv;
-
-	if (argc != 2 && (argc != 3 || strcmp(argv[2], "status"))) {
-		fprintf(stderr, "Usage: %s <port> [status]\n",
-				argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	if (argc == 3) {
-		struct ec_response_i2c_passthru_protect r;
-
-		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS;
-
-		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
-				&r, sizeof(r));
-
-		if (rv < 0)
-			return rv;
-
-		printf("I2C port %d: %s (%d)\n", p.port,
-			r.status ? "Protected" : "Unprotected", r.status);
-	} else {
-		p.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE;
-
-		rv = ec_command(EC_CMD_I2C_PASSTHRU_PROTECT, 0, &p, sizeof(p),
-				NULL, 0);
-
-		if (rv < 0)
-			return rv;
-	}
-	return 0;
-}
-
-
-int do_i2c_xfer(unsigned int port, unsigned int addr,
-		uint8_t *write_buf, int write_len,
-		uint8_t **read_buf, int read_len) {
-	struct ec_params_i2c_passthru *p =
-		(struct ec_params_i2c_passthru *)ec_outbuf;
-	struct ec_response_i2c_passthru *r =
-		(struct ec_response_i2c_passthru *)ec_inbuf;
-	struct ec_params_i2c_passthru_msg *msg = p->msg;
-	uint8_t *pdata;
-	int size;
-	int rv;
-
-	p->port = port;
-	p->num_msgs = (read_len != 0) + (write_len != 0);
-
-	size = sizeof(*p) + p->num_msgs * sizeof(*msg);
-	if (size + write_len > ec_max_outsize) {
-		fprintf(stderr, "Params too large for buffer\n");
-		return -1;
-	}
-	if (sizeof(*r) + read_len > ec_max_insize) {
-		fprintf(stderr, "Read length too big for buffer\n");
-		return -1;
-	}
-
-	pdata = (uint8_t *)p + size;
-	if (write_len) {
-		msg->addr_flags = addr;
-		msg->len = write_len;
-
-		memcpy(pdata, write_buf, write_len);
-		msg++;
-	}
-
-	if (read_len) {
-		msg->addr_flags = addr | EC_I2C_FLAG_READ;
-		msg->len = read_len;
-	}
-
-	rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len,
-			r, sizeof(*r) + read_len);
-	if (rv < 0)
-		return rv;
-
-	/* Parse response */
-	if (r->i2c_status & (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)) {
-		fprintf(stderr, "Transfer failed with status=0x%x\n",
-			r->i2c_status);
-		return -1;
-	}
-
-	if (rv < sizeof(*r) + read_len) {
-		fprintf(stderr, "Truncated read response\n");
-		return -1;
-	}
-
-	if (read_len)
-		*read_buf = r->data;
-
-	return 0;
-}
-
-static void cmd_i2c_help(void)
-{
-	fprintf(stderr,
-	"  Usage: i2cread <8 | 16> <port> <addr8> <offset>\n"
-	"  Usage: i2cwrite <8 | 16> <port> <addr8> <offset> <data>\n"
-	"  Usage: i2cxfer <port> <addr7> <read_count> [bytes...]\n"
-	"    <port> i2c port number\n"
-	"    <addr8> 8-bit i2c address\n"
-	"    <addr7> 7-bit i2c address\n"
-	"    <offset> offset to read from or write to\n"
-	"    <data> data to write\n"
-	"    <read_count> number of bytes to read\n"
-	"    [bytes ...] data to write\n"
-	);
-
-}
-
-int cmd_i2c_read(int argc, char *argv[])
-{
-	unsigned int port, addr8, addr7;
-	int read_len, write_len;
-	uint8_t write_buf[1];
-	uint8_t *read_buf = NULL;
-	char *e;
-	int rv;
-
-	if (argc != 5) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	read_len = strtol(argv[1], &e, 0);
-	if ((e && *e) || (read_len != 8 && read_len != 16)) {
-		fprintf(stderr, "Bad read size.\n");
-		return -1;
-	}
-	read_len = read_len / 8;
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr8 = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad address.\n");
-		return -1;
-	}
-	addr7 = addr8 >> 1;
-
-	write_buf[0] = strtol(argv[4], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-	write_len = 1;
-
-	rv = do_i2c_xfer(port, addr7, write_buf, write_len, &read_buf,
-			 read_len);
-
-	if (rv < 0)
-		return rv;
-
-	printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n",
-		port, addr8, write_buf[0], *(uint16_t *)read_buf);
-	return 0;
-}
-
-
-int cmd_i2c_write(int argc, char *argv[])
-{
-	unsigned int port, addr8, addr7;
-	int write_len;
-	uint8_t write_buf[3];
-	char *e;
-	int rv;
-
-	if (argc != 6) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	write_len = strtol(argv[1], &e, 0);
-	if ((e && *e) || (write_len != 8 && write_len != 16)) {
-		fprintf(stderr, "Bad write size.\n");
-		return -1;
-	}
-	/* Include offset (length 1) */
-	write_len = 1 + write_len / 8;
-
-	port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr8 = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad address.\n");
-		return -1;
-	}
-	addr7 = addr8 >> 1;
-
-	write_buf[0] = strtol(argv[4], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad offset.\n");
-		return -1;
-	}
-
-	*((uint16_t *)&write_buf[1]) = strtol(argv[5], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad data.\n");
-		return -1;
-	}
-
-	rv = do_i2c_xfer(port, addr7, write_buf, write_len, NULL, 0);
-
-	if (rv < 0)
-		return rv;
-
-	printf("Wrote 0x%x to I2C port %d at 0x%x offset 0x%x.\n",
-	       *((uint16_t *)&write_buf[1]), port, addr8, write_buf[0]);
-	return 0;
-}
-
-int cmd_i2c_xfer(int argc, char *argv[])
-{
-	unsigned int port, addr;
-	int read_len, write_len;
-	uint8_t *write_buf = NULL;
-	uint8_t *read_buf;
-	char *e;
-	int rv, i;
-
-	if (argc < 4) {
-		cmd_i2c_help();
-		return -1;
-	}
-
-	port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port.\n");
-		return -1;
-	}
-
-	addr = strtol(argv[2], &e, 0) & 0x7f;
-	if (e && *e) {
-		fprintf(stderr, "Bad peripheral address.\n");
-		return -1;
-	}
-
-	read_len = strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad read length.\n");
-		return -1;
-	}
-
-	/* Skip over params to bytes to write */
-	argc -= 4;
-	argv += 4;
-	write_len = argc;
-
-	if (write_len) {
-		write_buf = (uint8_t *)(malloc(write_len));
-		if (write_buf == NULL)
-			return -1;
-		for (i = 0; i < write_len; i++) {
-			write_buf[i] = strtol(argv[i], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad write byte %d\n", i);
-				free(write_buf);
-				return -1;
-			}
-		}
-	}
-
-	rv = do_i2c_xfer(port, addr, write_buf, write_len, &read_buf, read_len);
-
-	if (write_len)
-		free(write_buf);
-
-	if (rv)
-		return rv;
-
-	if (read_len) {
-		if (ascii_mode) {
-			for (i = 0; i < read_len; i++)
-				printf(isprint(read_buf[i]) ? "%c" : "\\x%02x",
-				       read_buf[i]);
-		} else {
-			printf("Read bytes:");
-			for (i = 0; i < read_len; i++)
-				printf(" %#02x", read_buf[i]);
-		}
-		printf("\n");
-	} else {
-		printf("Write successful.\n");
-	}
-
-	return 0;
-}
-
-static void cmd_locate_chip_help(const char *const cmd)
-{
-	fprintf(stderr,
-		"Usage: %s <type> <index>\n"
-		"  <type> is one of:\n"
-		"    0: CBI_EEPROM\n"
-		"    1: TCPCs\n"
-		"  <index> instance # of <type>\n",
-		cmd);
-}
-
-static const char *bus_type[] = {
-	"I2C",
-	"EMBEDDED"
-};
-
-int cmd_locate_chip(int argc, char *argv[])
-{
-	struct ec_params_locate_chip p;
-	struct ec_response_locate_chip r = {0};
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	p.type = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type.\n");
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	p.index = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad index.\n");
-		cmd_locate_chip_help(argv[0]);
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_LOCATE_CHIP, 0, &p, sizeof(p), &r, sizeof(r));
-
-	if (rv == -EC_RES_INVALID_PARAM - EECRESULT) {
-		fprintf(stderr, "Bus type %d not supported.\n", p.type);
-		return rv;
-	}
-
-	if (rv == -EC_RES_UNAVAILABLE - EECRESULT) {
-		fprintf(stderr, "Chip not found\n");
-		return rv;
-	}
-
-	if (rv == -EC_RES_OVERFLOW - EECRESULT) {
-		fprintf(stderr, "Index too large\n");
-		return rv;
-	}
-
-	if (rv < 0)
-		return rv;
-
-	if (r.bus_type >= EC_BUS_TYPE_COUNT
-			|| r.bus_type >= ARRAY_SIZE(bus_type)) {
-		fprintf(stderr, "Unknown bus type (%d)\n", r.bus_type);
-		return -1;
-	}
-
-	/*
-	 * When changing the format of this print, make sure FAFT
-	 * (firmware_ECCbiEeprom) still passes. It may silently skip the test.
-	 */
-	printf("Bus: %s; Port: %d; Address: 0x%02x (7-bit format)\n",
-	       bus_type[r.bus_type], r.i2c_info.port,
-	       I2C_STRIP_FLAGS(r.i2c_info.addr_flags));
-
-	return 0;
-}
-
-int cmd_lcd_backlight(int argc, char *argv[])
-{
-	struct ec_params_switch_enable_backlight p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.enabled = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Success.\n");
-	return 0;
-}
-
-static void cmd_basestate_help(void)
-{
-	fprintf(stderr,
-		"Usage: ectool basestate [attach | detach | reset]\n");
-}
-
-int cmd_basestate(int argc, char *argv[])
-{
-	struct ec_params_set_base_state p;
-
-	if (argc != 2) {
-		cmd_basestate_help();
-		return -1;
-	}
-
-	if (!strncmp(argv[1], "attach", 6)) {
-		p.cmd = EC_SET_BASE_STATE_ATTACH;
-	} else if (!strncmp(argv[1], "detach", 6)) {
-		p.cmd = EC_SET_BASE_STATE_DETACH;
-	} else if (!strncmp(argv[1], "reset", 5)) {
-		p.cmd = EC_SET_BASE_STATE_RESET;
-	} else {
-		cmd_basestate_help();
-		return -1;
-	}
-
-	return ec_command(EC_CMD_SET_BASE_STATE, 0,
-			  &p, sizeof(p), NULL, 0);
-}
-
-int cmd_ext_power_limit(int argc, char *argv[])
-{
-	/* Version 1 is used, no support for obsolete version 0 */
-	struct ec_params_external_power_limit_v1 p;
-	char *e;
-
-	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <max_current_mA> <max_voltage_mV>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.current_lim = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad param1.\n");
-		return -1;
-	}
-
-	p.voltage_lim = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad param2.\n");
-		return -1;
-	}
-
-	/* Send version 1 of command */
-	return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p),
-			  NULL, 0);
-}
-
-
-int cmd_charge_current_limit(int argc, char *argv[])
-{
-	struct ec_params_current_limit p;
-	int rv;
-	char *e;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <max_current_mA>\n", argv[0]);
-		return -1;
-	}
-
-	p.limit = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p),
-			NULL, 0);
-	return rv;
-}
-
-static void cmd_charge_control_help(const char *cmd, const char *msg)
-{
-	if (msg)
-		fprintf(stderr, "ERROR: %s\n", msg);
-
-	fprintf(stderr,
-	"\n"
-	"  Usage: %s\n"
-	"    Get current settings.\n"
-	"  Usage: %s normal|idle|discharge\n"
-	"    Set charge mode (and disable battery sustainer).\n"
-	"  Usage: %s normal <lower> <upper>\n"
-	"    Enable battery sustainer. <lower> and <upper> are battery SoC\n"
-	"    between which EC tries to keep the battery level.\n"
-	"\n",
-	cmd, cmd, cmd);
-}
-
-int cmd_charge_control(int argc, char *argv[])
-{
-	struct ec_params_charge_control p;
-	struct ec_response_charge_control r;
-	int version = 2;
-	const char * const charge_mode_text[] = EC_CHARGE_MODE_TEXT;
-	char *e;
-	int rv;
-
-	if (!ec_cmd_version_supported(EC_CMD_CHARGE_CONTROL, 2))
-		version = 1;
-
-	if (argc == 1) {
-		if (version < 2) {
-			cmd_charge_control_help(argv[0],
-						"Old EC doesn't support GET.");
-			return -1;
-		}
-		p.cmd = EC_CHARGE_CONTROL_CMD_GET;
-		rv = ec_command(EC_CMD_CHARGE_CONTROL, version,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv < 0) {
-			fprintf(stderr, "Command failed.\n");
-			return rv;
-		}
-		printf("Charge mode = %s (%d)\n",
-		       r.mode < ARRAY_SIZE(charge_mode_text)
-		       		? charge_mode_text[r.mode] : "UNDEFINED",
-		       r.mode);
-		printf("Battery sustainer = %s (%d%% ~ %d%%)\n",
-		       (r.sustain_soc.lower != -1 && r.sustain_soc.upper != -1)
-				? "on" : "off",
-		       r.sustain_soc.lower, r.sustain_soc.upper);
-		return 0;
-	}
-
-	p.cmd = EC_CHARGE_CONTROL_CMD_SET;
-	if (!strcasecmp(argv[1], "normal")) {
-		p.mode = CHARGE_CONTROL_NORMAL;
-		if (argc == 2) {
-			p.sustain_soc.lower = -1;
-			p.sustain_soc.upper = -1;
-		} else if (argc == 4) {
-			if (version < 2) {
-				cmd_charge_control_help(argv[0],
-					"Old EC doesn't support sustainer.");
-				return -1;
-			}
-			p.sustain_soc.lower = strtol(argv[2], &e, 0);
-			if (e && *e) {
-				cmd_charge_control_help(argv[0],
-						"Bad character in <lower>");
-				return -1;
-			}
-			p.sustain_soc.upper = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				cmd_charge_control_help(argv[0],
-						"Bad character in <upper>");
-				return -1;
-			}
-		} else {
-			cmd_charge_control_help(argv[0], "Bad arguments");
-			return -1;
-		}
-	} else if (!strcasecmp(argv[1], "idle")) {
-		if (argc != 2) {
-			cmd_charge_control_help(argv[0], "Bad arguments");
-			return -1;
-		}
-		p.mode = CHARGE_CONTROL_IDLE;
-	} else if (!strcasecmp(argv[1], "discharge")) {
-		if (argc != 2) {
-			cmd_charge_control_help(argv[0], "Bad arguments");
-			return -1;
-		}
-		p.mode = CHARGE_CONTROL_DISCHARGE;
-	} else {
-		cmd_charge_control_help(argv[0], "Bad sub-command");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_CHARGE_CONTROL, version, &p, sizeof(p), NULL, 0);
-	if (rv < 0) {
-		fprintf(stderr, "Is AC connected?\n");
-		return rv;
-	}
-
-	switch (p.mode) {
-	case CHARGE_CONTROL_NORMAL:
-		printf("Charge state machine is in normal mode%s.\n",
-		       (p.sustain_soc.lower == -1 || p.sustain_soc.upper == -1)
-		       		? "" : " with sustainer enabled");
-		break;
-	case CHARGE_CONTROL_IDLE:
-		printf("Charge state machine force idle.\n");
-		break;
-	case CHARGE_CONTROL_DISCHARGE:
-		printf("Charge state machine force discharge.\n");
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-
-
-#define ST_CMD_SIZE ST_FLD_SIZE(ec_params_charge_state, cmd)
-#define ST_PRM_SIZE(SUBCMD) \
-	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_charge_state, SUBCMD))
-#define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_charge_state, SUBCMD)
-
-/* Table of subcommand sizes for EC_CMD_CHARGE_STATE */
-static const struct {
-	uint8_t to_ec_size;
-	uint8_t from_ec_size;
-} cs_paramcount[] = {
-	/* Order must match enum charge_state_command */
-	{ ST_CMD_SIZE, ST_RSP_SIZE(get_state) },
-	{ ST_PRM_SIZE(get_param), ST_RSP_SIZE(get_param) },
-	{ ST_PRM_SIZE(set_param), 0},
-};
-BUILD_ASSERT(ARRAY_SIZE(cs_paramcount) == CHARGE_STATE_NUM_CMDS);
-
-#undef ST_CMD_SIZE
-#undef ST_PRM_SIZE
-#undef ST_RSP_SIZE
-
-static int cs_do_cmd(struct ec_params_charge_state *to_ec,
-		     struct ec_response_charge_state *from_ec)
-{
-	int rv;
-	int cmd = to_ec->cmd;
-
-	rv = ec_command(EC_CMD_CHARGE_STATE, 0,
-			to_ec, cs_paramcount[cmd].to_ec_size,
-			from_ec, cs_paramcount[cmd].from_ec_size);
-
-	return (rv < 0 ? 1 : 0);
-}
-
-static const char * const base_params[] = {
-	"chg_voltage",
-	"chg_current",
-	"chg_input_current",
-	"chg_status",
-	"chg_option",
-	"limit_power",
-};
-BUILD_ASSERT(ARRAY_SIZE(base_params) == CS_NUM_BASE_PARAMS);
-
-static int cmd_charge_state(int argc, char **argv)
-{
-	struct ec_params_charge_state param;
-	struct ec_response_charge_state resp;
-	uint32_t p, v;
-	int i, r;
-	char *e;
-
-	if (argc > 1 && !strcasecmp(argv[1], "show")) {
-		param.cmd = CHARGE_STATE_CMD_GET_STATE;
-		r = cs_do_cmd(&param, &resp);
-		if (r)
-			return r;
-		printf("ac = %d\n", resp.get_state.ac);
-		printf("chg_voltage = %dmV\n", resp.get_state.chg_voltage);
-		printf("chg_current = %dmA\n", resp.get_state.chg_current);
-		printf("chg_input_current = %dmA\n",
-		       resp.get_state.chg_input_current);
-		printf("batt_state_of_charge = %d%%\n",
-		       resp.get_state.batt_state_of_charge);
-		return 0;
-	}
-
-	if (argc > 1 && !strcasecmp(argv[1], "param")) {
-		switch (argc) {
-		case 3:
-			if (!strcasecmp(argv[2], "help"))
-				break;
-			param.cmd = CHARGE_STATE_CMD_GET_PARAM;
-			p = strtoull(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad param: %s\n", argv[2]);
-				return -1;
-			}
-			param.get_param.param = p;
-			r = cs_do_cmd(&param, &resp);
-			if (r)
-				return r;
-			v = resp.get_param.value;
-			if (p < CS_NUM_BASE_PARAMS)
-				printf("%d (0x%x)       # %s\n", v, v,
-				       base_params[p]);
-			else
-				printf("%d (0x%x)\n", v, v);
-			return 0;
-		case 4:
-			param.cmd = CHARGE_STATE_CMD_SET_PARAM;
-			p = strtoull(argv[2], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad param: %s\n", argv[2]);
-				return -1;
-			}
-			v = strtoull(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad value: %s\n", argv[3]);
-				return -1;
-			}
-			param.set_param.param = p;
-			param.set_param.value = v;
-			return cs_do_cmd(&param, &resp);
-		}
-
-		printf("base params:\n");
-		for (i = 0; i < CS_NUM_BASE_PARAMS; i++)
-			printf("  %d   %s\n", i, base_params[i]);
-		printf("custom profile params:\n");
-		printf("  0x%x - 0x%x\n", CS_PARAM_CUSTOM_PROFILE_MIN,
-		       CS_PARAM_CUSTOM_PROFILE_MAX);
-
-		return 0;
-	}
-
-	printf("Usage:\n");
-	printf("  %s show                  - show current state\n", argv[0]);
-	printf("  %s param NUM [VALUE]     - get/set param NUM\n", argv[0]);
-	printf("  %s param help            - show known param NUMs\n", argv[0]);
-	return 0;
-}
-
-int cmd_gpio_get(int argc, char *argv[])
-{
-	struct ec_params_gpio_get_v1 p_v1;
-	struct ec_response_gpio_get_v1 r_v1;
-	int i, rv, subcmd, num_gpios;
-	int cmdver = 1;
-
-	if (!ec_cmd_version_supported(EC_CMD_GPIO_GET, cmdver)) {
-		struct ec_params_gpio_get p;
-		struct ec_response_gpio_get r;
-
-		/* Fall back to version 0 command */
-		cmdver = 0;
-		if (argc != 2) {
-			fprintf(stderr, "Usage: %s <GPIO name>\n", argv[0]);
-			return -1;
-		}
-
-		if (strlen(argv[1]) + 1 > sizeof(p.name)) {
-			fprintf(stderr, "GPIO name too long.\n");
-			return -1;
-		}
-		strcpy(p.name, argv[1]);
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p,
-				sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		printf("GPIO %s = %d\n", p.name, r.val);
-		return 0;
-	}
-
-	if (argc > 2 || (argc == 2 && !strcmp(argv[1], "help"))) {
-		printf("Usage: %s [<subcmd> <GPIO name>]\n", argv[0]);
-		printf("'gpioget <GPIO_NAME>' - Get value by name\n");
-		printf("'gpioget count' - Get count of GPIOS\n");
-		printf("'gpioget all' - Get info for all GPIOs\n");
-		return -1;
-	}
-
-	/* Keeping it consistent with console command behavior */
-	if (argc == 1)
-		subcmd = EC_GPIO_GET_INFO;
-	else if (!strcmp(argv[1], "count"))
-		subcmd = EC_GPIO_GET_COUNT;
-	else if (!strcmp(argv[1], "all"))
-		subcmd = EC_GPIO_GET_INFO;
-	else
-		subcmd = EC_GPIO_GET_BY_NAME;
-
-	if (subcmd == EC_GPIO_GET_BY_NAME) {
-		p_v1.subcmd = EC_GPIO_GET_BY_NAME;
-		if (strlen(argv[1]) + 1 > sizeof(p_v1.get_value_by_name.name)) {
-			fprintf(stderr, "GPIO name too long.\n");
-			return -1;
-		}
-		strcpy(p_v1.get_value_by_name.name, argv[1]);
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
-
-		if (rv < 0)
-			return rv;
-
-		printf("GPIO %s = %d\n", p_v1.get_value_by_name.name,
-			r_v1.get_value_by_name.val);
-		return 0;
-	}
-
-	/* Need GPIO count for EC_GPIO_GET_COUNT or EC_GPIO_GET_INFO */
-	p_v1.subcmd = EC_GPIO_GET_COUNT;
-	rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-			sizeof(p_v1), &r_v1, sizeof(r_v1));
-	if (rv < 0)
-		return rv;
-
-	if (subcmd == EC_GPIO_GET_COUNT) {
-		printf("GPIO COUNT = %d\n", r_v1.get_count.val);
-		return 0;
-	}
-
-	/* subcmd EC_GPIO_GET_INFO */
-	num_gpios = r_v1.get_count.val;
-	p_v1.subcmd = EC_GPIO_GET_INFO;
-
-	for (i = 0; i < num_gpios; i++) {
-		p_v1.get_info.index = i;
-
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
-		if (rv < 0)
-			return rv;
-
-		printf("%2d %-32s 0x%04X\n", r_v1.get_info.val,
-			r_v1.get_info.name, r_v1.get_info.flags);
-	}
-
-	return 0;
-}
-
-
-int cmd_gpio_set(int argc, char *argv[])
-{
-	struct ec_params_gpio_set p;
-	char *e;
-	int rv;
-
-	if (argc != 3) {
-		fprintf(stderr, "Usage: %s <GPIO name> <0 | 1>\n", argv[0]);
-		return -1;
-	}
-
-	if (strlen(argv[1]) + 1 > sizeof(p.name)) {
-		fprintf(stderr, "GPIO name too long.\n");
-		return -1;
-	}
-	strcpy(p.name, argv[1]);
-
-	p.val = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GPIO_SET, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("GPIO %s set to %d\n", p.name, p.val);
-	return 0;
-}
-
-void print_battery_flags(int flags)
-{
-	printf("  Flags                   0x%02x", flags);
-	if (flags & EC_BATT_FLAG_AC_PRESENT)
-		printf(" AC_PRESENT");
-	if (flags & EC_BATT_FLAG_BATT_PRESENT)
-		printf(" BATT_PRESENT");
-	if (flags & EC_BATT_FLAG_DISCHARGING)
-		printf(" DISCHARGING");
-	if (flags & EC_BATT_FLAG_CHARGING)
-		printf(" CHARGING");
-	if (flags & EC_BATT_FLAG_LEVEL_CRITICAL)
-		printf(" LEVEL_CRITICAL");
-	printf("\n");
-}
-
-int get_battery_command(int index)
-{
-	struct ec_params_battery_static_info static_p;
-	struct ec_response_battery_static_info_v1 static_r;
-	struct ec_params_battery_dynamic_info dynamic_p;
-	struct ec_response_battery_dynamic_info dynamic_r;
-	int rv;
-
-	printf("Battery %d info:\n", index);
-
-	static_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1,
-			&static_p, sizeof(static_p),
-			&static_r, sizeof(static_r));
-	if (rv < 0)
-		return -1;
-
-	dynamic_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0,
-			&dynamic_p, sizeof(dynamic_p),
-			&dynamic_r, sizeof(dynamic_r));
-	if (rv < 0)
-		return -1;
-
-	if (dynamic_r.flags & EC_BATT_FLAG_INVALID_DATA) {
-		printf("  Invalid data (not present?)\n");
-		return -1;
-	}
-
-	if (!is_string_printable(static_r.manufacturer_ext))
-		goto cmd_error;
-	printf("  OEM name:               %s\n", static_r.manufacturer_ext);
-
-	if (!is_string_printable(static_r.model_ext))
-		goto cmd_error;
-	printf("  Model number:           %s\n", static_r.model_ext);
-
-	if (!is_string_printable(static_r.type_ext))
-		goto cmd_error;
-	printf("  Chemistry   :           %s\n", static_r.type_ext);
-
-	if (!is_string_printable(static_r.serial_ext))
-		goto cmd_error;
-	printf("  Serial number:          %s\n", static_r.serial_ext);
-
-	if (!is_battery_range(static_r.design_capacity))
-		goto cmd_error;
-	printf("  Design capacity:        %u mAh\n", static_r.design_capacity);
-
-	if (!is_battery_range(dynamic_r.full_capacity))
-		goto cmd_error;
-	printf("  Last full charge:       %u mAh\n", dynamic_r.full_capacity);
-
-	if (!is_battery_range(static_r.design_voltage))
-		goto cmd_error;
-	printf("  Design output voltage   %u mV\n", static_r.design_voltage);
-
-	if (!is_battery_range(static_r.cycle_count))
-		goto cmd_error;
-	printf("  Cycle count             %u\n", static_r.cycle_count);
-
-	if (!is_battery_range(dynamic_r.actual_voltage))
-		goto cmd_error;
-	printf("  Present voltage         %u mV\n", dynamic_r.actual_voltage);
-
-	/* current can be negative */
-	printf("  Present current         %d mA\n", dynamic_r.actual_current);
-
-	if (!is_battery_range(dynamic_r.remaining_capacity))
-		goto cmd_error;
-	printf("  Remaining capacity      %u mAh\n",
-						dynamic_r.remaining_capacity);
-
-	if (!is_battery_range(dynamic_r.desired_voltage))
-		goto cmd_error;
-	printf("  Desired voltage         %u mV\n", dynamic_r.desired_voltage);
-
-	if (!is_battery_range(dynamic_r.desired_current))
-		goto cmd_error;
-	printf("  Desired current         %u mA\n", dynamic_r.desired_current);
-
-	print_battery_flags(dynamic_r.flags);
-	return 0;
-
-cmd_error:
-	fprintf(stderr, "Bad battery info value.\n");
-	return -1;
-}
-
-int cmd_battery(int argc, char *argv[])
-{
-	char batt_text[EC_MEMMAP_TEXT_MAX];
-	int rv, val;
-	char *e;
-	int index = 0;
-
-	if (argc > 2) {
-		fprintf(stderr, "Usage: %s [index]\n", argv[0]);
-		return -1;
-	} else if (argc == 2) {
-		index = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad battery index.\n");
-			return -1;
-		}
-	}
-
-	/*
-	 * Read non-primary batteries through hostcmd, and all batteries
-	 * if longer strings are supported for static info.
-	 */
-	if (index > 0 ||
-	    ec_cmd_version_supported(EC_CMD_BATTERY_GET_STATIC, 1))
-		return get_battery_command(index);
-
-	val = read_mapped_mem8(EC_MEMMAP_BATTERY_VERSION);
-	if (val < 1) {
-		fprintf(stderr, "Battery version %d is not supported\n", val);
-		return -1;
-	}
-
-	printf("Battery info:\n");
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_MFGR, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  OEM name:               %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_MODEL, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  Model number:           %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_TYPE, batt_text,
-			sizeof(batt_text));
-	if (rv < 0 || !is_string_printable(batt_text))
-		goto cmd_error;
-	printf("  Chemistry   :           %s\n", batt_text);
-
-	rv = read_mapped_string(EC_MEMMAP_BATT_SERIAL, batt_text,
-			sizeof(batt_text));
-	printf("  Serial number:          %s\n", batt_text);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_DCAP);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Design capacity:        %u mAh\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_LFCC);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Last full charge:       %u mAh\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_DVLT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Design output voltage   %u mV\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_CCNT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Cycle count             %u\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_VOLT);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Present voltage         %u mV\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_RATE);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Present current         %u mA\n", val);
-
-	val = read_mapped_mem32(EC_MEMMAP_BATT_CAP);
-	if (!is_battery_range(val))
-		goto cmd_error;
-	printf("  Remaining capacity      %u mAh\n", val);
-
-	val = read_mapped_mem8(EC_MEMMAP_BATT_FLAG);
-	print_battery_flags(val);
-
-	return 0;
-cmd_error:
-	fprintf(stderr, "Bad battery info value. Check protocol version.\n");
-	return -1;
-}
-
-int cmd_battery_cut_off(int argc, char *argv[])
-{
-	struct ec_params_battery_cutoff p;
-	int cmd_version;
-	int rv;
-
-	memset(&p, 0, sizeof(p));
-	if (ec_cmd_version_supported(EC_CMD_BATTERY_CUT_OFF, 1)) {
-		cmd_version = 1;
-		if (argc > 1) {
-			if (!strcasecmp(argv[1], "at-shutdown")) {
-				p.flags = EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN;
-			} else {
-				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
-				return -1;
-			}
-		}
-	} else {
-		/* Fall back to version 0 command */
-		cmd_version = 0;
-		if (argc > 1) {
-			if (!strcasecmp(argv[1], "at-shutdown")) {
-				fprintf(stderr, "Explicit 'at-shutdown' ");
-				fprintf(stderr, "parameter not supported.\n");
-			} else {
-				fprintf(stderr, "Bad parameter: %s\n", argv[1]);
-			}
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_BATTERY_CUT_OFF, cmd_version, &p, sizeof(p),
-			NULL, 0);
-	rv = (rv < 0 ? rv : 0);
-
-	if (rv < 0) {
-		fprintf(stderr, "Failed to cut off battery, rv=%d\n", rv);
-		fprintf(stderr, "It is expected if the rv is -%d "
-				"(EC_RES_INVALID_COMMAND) if the battery "
-				"doesn't support cut-off function.\n",
-				EC_RES_INVALID_COMMAND);
-	} else {
-		printf("\n");
-		printf("SUCCESS. The battery has arranged a cut-off.\n");
-
-		if (cmd_version == 1 &&
-		    (p.flags & EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN))
-			printf("The battery will be cut off after shutdown.\n");
-		else
-			printf("The system should be shutdown immediately.\n");
-
-		printf("\n");
-	}
-	return rv;
-}
-
-int cmd_battery_vendor_param(int argc, char *argv[])
-{
-	struct ec_params_battery_vendor_param p;
-	struct ec_response_battery_vendor_param r;
-	char *e;
-	int rv;
-
-	if (argc < 3)
-		goto cmd_battery_vendor_param_usage;
-
-	if (!strcasecmp(argv[1], "get"))
-		p.mode = BATTERY_VENDOR_PARAM_MODE_GET;
-	else if (!strcasecmp(argv[1], "set"))
-		p.mode = BATTERY_VENDOR_PARAM_MODE_SET;
-	else
-		goto cmd_battery_vendor_param_usage;
-
-	p.param = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Invalid param.\n");
-		goto cmd_battery_vendor_param_usage;
-	}
-
-	if (p.mode == BATTERY_VENDOR_PARAM_MODE_SET) {
-		if (argc != 4) {
-			fprintf(stderr, "Missing value.\n");
-			goto cmd_battery_vendor_param_usage;
-		}
-
-		p.value = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Invalid value.\n");
-			goto cmd_battery_vendor_param_usage;
-		}
-	}
-
-	rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p),
-			&r, sizeof(r));
-
-	if (rv < 0)
-		return rv;
-
-	printf("0x%08x\n", r.value);
-
-	return 0;
-
-cmd_battery_vendor_param_usage:
-	fprintf(stderr,
-		"Usage:\t %s get <param>\n"
-		"\t %s set <param> <value>\n",
-		argv[0], argv[0]);
-	return -1;
-}
-
-int cmd_board_version(int argc, char *argv[])
-{
-	struct ec_response_board_version response;
-	int rv;
-
-	rv = ec_command(EC_CMD_GET_BOARD_VERSION, 0, NULL, 0, &response,
-			sizeof(response));
-	if (rv < 0)
-		return rv;
-
-	printf("%d\n", response.board_version);
-	return rv;
-}
-
-static void cmd_cbi_help(char *cmd)
-{
-	fprintf(stderr,
-	"  Usage: %s get <tag> [get_flag]\n"
-	"  Usage: %s set <tag> <value/string> <size> [set_flag]\n"
-	"  Usage: %s remove <tag> [set_flag]\n"
-	"    <tag> is one of:\n"
-	"      0: BOARD_VERSION\n"
-	"      1: OEM_ID\n"
-	"      2: SKU_ID\n"
-	"      3: DRAM_PART_NUM (string)\n"
-	"      4: OEM_NAME (string)\n"
-	"      5: MODEL_ID\n"
-	"      6: FW_CONFIG\n"
-	"      7: PCB_VENDOR\n"
-	"      8: SSFC\n"
-	"      9: REWORK_ID\n"
-	"    <size> is the size of the data in byte. It should be zero for\n"
-	"      string types.\n"
-	"    <value/string> is an integer or a string to be set\n"
-	"    [get_flag] is combination of:\n"
-	"      01b: Invalidate cache and reload data from EEPROM\n"
-	"    [set_flag] is combination of:\n"
-	"      01b: Skip write to EEPROM. Use for back-to-back writes\n"
-	"      10b: Set all fields to defaults first\n", cmd, cmd, cmd);
-}
-
-static int cmd_cbi_is_string_field(enum cbi_data_tag tag)
-{
-	return tag == CBI_TAG_DRAM_PART_NUM || tag == CBI_TAG_OEM_NAME;
-}
-
-/*
- * Write value to CBI
- *
- * TODO: Support asynchronous write
- */
-static int cmd_cbi(int argc, char *argv[])
-{
-	enum cbi_data_tag tag;
-	char *e;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cbi_help(argv[0]);
-		return -1;
-	}
-
-	/* Tag */
-	tag = (enum cbi_data_tag)(strtol(argv[2], &e, 0));
-	if (e && *e) {
-		fprintf(stderr, "Bad tag\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "get")) {
-		struct ec_params_get_cbi p = { 0 };
-		int i;
-
-		p.tag = tag;
-		if (argc > 3) {
-			p.flag = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_GET_CROS_BOARD_INFO, 0, &p, sizeof(p),
-				ec_inbuf, ec_max_insize);
-		if (rv < 0) {
-			fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		if (rv < sizeof(uint8_t)) {
-			fprintf(stderr, "Invalid size: %d\n", rv);
-			return -1;
-		}
-		if (cmd_cbi_is_string_field(tag)) {
-			printf("%.*s", rv, (const char *)ec_inbuf);
-		} else {
-			const uint8_t * const buffer =
-				(const uint8_t *const)(ec_inbuf);
-			uint64_t int_value = 0;
-                        for(i = 0; i < rv; i++)
-				int_value |= (uint64_t)buffer[i] << (i * 8);
-
-                        printf("As uint: %llu (0x%llx)\n",
-				(unsigned long long)int_value,
-                                (unsigned long long)int_value);
-			printf("As binary:");
-			for (i = 0; i < rv; i++) {
-				if (i % 32 == 31)
-					printf("\n");
-				printf(" %02x", buffer[i]);
-			}
-		}
-		printf("\n");
-		return 0;
-	} else if (!strcasecmp(argv[1], "set")) {
-		struct ec_params_set_cbi *p =
-				(struct ec_params_set_cbi *)ec_outbuf;
-		void *val_ptr;
-		uint64_t val = 0;
-		uint8_t size;
-		uint8_t bad_size = 0;
-		if (argc < 5) {
-			fprintf(stderr, "Invalid number of params\n");
-			cmd_cbi_help(argv[0]);
-			return -1;
-		}
-		memset(p, 0, ec_max_outsize);
-		p->tag = tag;
-
-		if (cmd_cbi_is_string_field(tag)) {
-			val_ptr = argv[3];
-			size = strlen((char *)(val_ptr)) + 1;
-		} else {
-			val = strtoul(argv[3], &e, 0);
-			/* strtoul sets an errno for invalid input. If the value
-			 * read is out of range of representable values by an
-			 * unsigned long int, the function returns ULONG_MAX
-			 * or ULONG_MIN and the errno is set to ERANGE.
-			 */
-			if ((e && *e) || errno == ERANGE) {
-				fprintf(stderr, "Bad value\n");
-				return -1;
-			}
-			size = strtol(argv[4], &e, 0);
-			if (tag == CBI_TAG_REWORK_ID) {
-				if ((e && *e) || size < 1 || size > 8 ||
-				     (size < 8 && val >= (1ull << size*8)))
-					bad_size = 1;
-			} else {
-				if ((e && *e) || size < 1 || 4 < size ||
-						 val >= (1ull << size*8))
-					bad_size = 1;
-			}
-			if (bad_size == 1) {
-				fprintf(stderr, "Bad size: %d\n", size);
-				return -1;
-			}
-
-			val_ptr = &val;
-		}
-
-		if (size > ec_max_outsize - sizeof(*p)) {
-			fprintf(stderr, "Size exceeds parameter buffer: %d\n",
-				size);
-			return -1;
-		}
-		/* Little endian */
-		memcpy(p->data, val_ptr, size);
-		p->size = size;
-		if (argc > 5) {
-			p->flag = strtol(argv[5], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				p, sizeof(*p) + size, NULL, 0);
-		if (rv < 0) {
-			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
-					"EC explicitly refused to change the "
-					"requested field.\n");
-			else
-				fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		return 0;
-	} else if (!strcasecmp(argv[1], "remove")) {
-		struct ec_params_set_cbi p = { 0 };
-
-		p.tag = tag;
-		p.size = 0;
-		if (argc > 3) {
-			p.flag = strtol(argv[3], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "Bad flag\n");
-				return -1;
-			}
-		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				&p, sizeof(p), NULL, 0);
-		if (rv < 0) {
-			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
-					"EC explicitly refused to change the "
-					"requested field.\n");
-			else
-				fprintf(stderr, "Error code: %d\n", rv);
-			return rv;
-		}
-		return 0;
-	}
-
-	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
-	cmd_cbi_help(argv[0]);
-
-	return -1;
-}
-
-int cmd_chipinfo(int argc, char *argv[])
-{
-	struct ec_response_get_chip_info info;
-	int rv;
-
-	printf("Chip info:\n");
-
-	rv = ec_command(EC_CMD_GET_CHIP_INFO, 0, NULL, 0, &info, sizeof(info));
-	if (rv < 0)
-		return rv;
-	printf("  vendor:    %s\n", info.vendor);
-	printf("  name:      %s\n", info.name);
-	printf("  revision:  %s\n", info.revision);
-
-	return 0;
-}
-
-int cmd_proto_info(int argc, char *argv[])
-{
-	struct ec_response_get_protocol_info info;
-	int rv;
-	int i;
-
-	printf("Protocol info:\n");
-
-	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0,
-			&info, sizeof(info));
-	if (rv < 0) {
-		fprintf(stderr, "Protocol info unavailable.  EC probably only "
-				"supports protocol version 2.\n");
-		return rv;
-	}
-
-	printf("  protocol versions:");
-	for (i = 0; i < 32; i++) {
-		if (info.protocol_versions & BIT(i))
-			printf(" %d", i);
-	}
-	printf("\n");
-
-	printf("  max request:  %4d bytes\n", info.max_request_packet_size);
-	printf("  max response: %4d bytes\n", info.max_response_packet_size);
-	printf("  flags: 0x%08x\n", info.flags);
-	if (info.flags & EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED)
-		printf("    EC_RES_IN_PROGRESS supported\n");
-	return 0;
-}
-
-static int ec_hash_help(const char *cmd)
-{
-	printf("Usage:\n");
-	printf("  %s                        - get last hash\n", cmd);
-	printf("  %s abort                  - abort hashing\n", cmd);
-	printf("  %s start [<offset> <size> [<nonce>]] - start hashing\n", cmd);
-	printf("  %s recalc [<offset> <size> [<nonce>]] - sync rehash\n", cmd);
-	printf("\n"
-	       "If <offset> is RO or RW, offset and size are computed\n"
-	       "automatically for the EC-RO or EC-RW firmware image.\n");
-
-	return 0;
-}
-
-
-static int ec_hash_print(const struct ec_response_vboot_hash *r)
-{
-	int i;
-
-	if (r->status == EC_VBOOT_HASH_STATUS_BUSY) {
-		printf("status:  busy\n");
-		return 0;
-	} else if (r->status == EC_VBOOT_HASH_STATUS_NONE) {
-		printf("status:  unavailable\n");
-		return 0;
-	} else if (r->status != EC_VBOOT_HASH_STATUS_DONE) {
-		printf("status:  %d\n", r->status);
-		return 0;
-	}
-
-	printf("status:  done\n");
-	if (r->hash_type == EC_VBOOT_HASH_TYPE_SHA256)
-		printf("type:    SHA-256\n");
-	else
-		printf("type:    %d\n", r->hash_type);
-
-	printf("offset:  0x%08x\n", r->offset);
-	printf("size:    0x%08x\n", r->size);
-
-	printf("hash:    ");
-	for (i = 0; i < r->digest_size; i++)
-		printf("%02x", r->hash_digest[i]);
-	printf("\n");
-	return 0;
-}
-
-
-int cmd_ec_hash(int argc, char *argv[])
-{
-	struct ec_params_vboot_hash p;
-	struct ec_response_vboot_hash r;
-	char *e;
-	int rv;
-
-	memset(&p, 0, sizeof(p));
-	if (argc < 2) {
-		/* Get hash status */
-		p.cmd = EC_VBOOT_HASH_GET;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv < 0)
-			return rv;
-
-		return ec_hash_print(&r);
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "abort")) {
-		/* Abort hash calculation */
-		p.cmd = EC_VBOOT_HASH_ABORT;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
-		return (rv < 0 ? rv : 0);
-	}
-
-	/* The only other commands are start and recalc */
-	if (!strcasecmp(argv[1], "start"))
-		p.cmd = EC_VBOOT_HASH_START;
-	else if (!strcasecmp(argv[1], "recalc"))
-		p.cmd = EC_VBOOT_HASH_RECALC;
-	else
-		return ec_hash_help(argv[0]);
-
-	p.hash_type = EC_VBOOT_HASH_TYPE_SHA256;
-
-	if (argc < 3) {
-		fprintf(stderr, "Must specify offset\n");
-		return -1;
-	}
-
-	if (!strcasecmp(argv[2], "ro")) {
-		p.offset = EC_VBOOT_HASH_OFFSET_RO;
-		p.size = 0;
-		printf("Hashing EC-RO...\n");
-	} else if (!strcasecmp(argv[2], "rw")) {
-		p.offset = EC_VBOOT_HASH_OFFSET_ACTIVE;
-		p.size = 0;
-		printf("Hashing EC-RW...\n");
-	} else if (argc < 4) {
-		fprintf(stderr, "Must specify size\n");
-		return -1;
-	} else {
-		p.offset = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad offset.\n");
-			return -1;
-		}
-		p.size = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad size.\n");
-			return -1;
-		}
-		printf("Hashing %d bytes at offset %d...\n", p.size, p.offset);
-	}
-
-	if (argc == 5) {
-		/*
-		 * Technically nonce can be any binary data up to 64 bytes,
-		 * but this command only supports a 32-bit value.
-		 */
-		uint32_t nonce = strtol(argv[4], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad nonce integer.\n");
-			return -1;
-		}
-		memcpy(p.nonce_data, &nonce, sizeof(nonce));
-		p.nonce_size = sizeof(nonce);
-	} else
-		p.nonce_size = 0;
-
-	rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	/* Start command doesn't wait for hashing to finish */
-	if (p.cmd == EC_VBOOT_HASH_START)
-		return 0;
-
-	/* Recalc command does wait around, so a result is ready now */
-	return ec_hash_print(&r);
-}
-
-
-int cmd_rtc_get(int argc, char *argv[])
-{
-	struct ec_response_rtc r;
-	int rv;
-
-	rv = ec_command(EC_CMD_RTC_GET_VALUE, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("Current time: 0x%08x (%d)\n", r.time, r.time);
-	return 0;
-}
-
-
-int cmd_rtc_set(int argc, char *argv[])
-{
-	struct ec_params_rtc p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <time>\n", argv[0]);
-		return -1;
-	}
-	p.time = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad time.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_RTC_SET_VALUE, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Time set.\n");
-	return 0;
-}
-
-int cmd_rtc_set_alarm(int argc, char *argv[])
-{
-	struct ec_params_rtc p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <sec>\n", argv[0]);
-		return -1;
-	}
-	p.time = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad time.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_RTC_SET_ALARM, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	if (p.time == 0)
-		printf("Disabling alarm.\n");
-	else
-		printf("Alarm set to go off in %d secs.\n", p.time);
-	return 0;
-}
-
-int cmd_rtc_get_alarm(int argc, char *argv[])
-{
-	struct ec_response_rtc r;
-	int rv;
-
-	rv = ec_command(EC_CMD_RTC_GET_ALARM, 0, NULL, 0, &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (r.time == 0)
-		printf("Alarm not set\n");
-	else
-		printf("Alarm to go off in %d secs\n", r.time);
-	return 0;
-}
-
-int cmd_console(int argc, char *argv[])
-{
-	char *out = (char *)ec_inbuf;
-	int rv;
-
-	/* Snapshot the EC console */
-	rv = ec_command(EC_CMD_CONSOLE_SNAPSHOT, 0, NULL, 0, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	/* Loop and read from the snapshot until it's done */
-	while (1) {
-		rv = ec_command(EC_CMD_CONSOLE_READ, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
-		if (rv < 0)
-			return rv;
-
-		/* Empty response means done */
-		if (!rv || !*out)
-			break;
-
-		/* Make sure output is null-terminated, then dump it */
-		out[ec_max_insize - 1] = '\0';
-		fputs(out, stdout);
-	}
-	printf("\n");
-	return 0;
-}
-struct param_info {
-	const char *name;	/* name of this parameter */
-	const char *help;	/* help message */
-	int size;		/* size in bytes */
-	int offset;		/* offset within structure */
-};
-
-#define FIELD(fname, field, help_str) \
-	{ \
-		.name = fname, \
-		.help = help_str, \
-		.size = sizeof(((struct ec_mkbp_config *)NULL)->field), \
-		.offset = __builtin_offsetof(struct ec_mkbp_config, field), \
-	}
-
-static const struct param_info keyconfig_params[] = {
-	FIELD("scan_period", scan_period_us, "period between scans"),
-	FIELD("poll_timeout", poll_timeout_us,
-	      "revert to irq mode after no activity for this long"),
-	FIELD("min_post_scan_delay", min_post_scan_delay_us,
-	      "minimum post-scan delay before starting a new scan"),
-	FIELD("output_settle", output_settle_us,
-	      "delay to wait for output to settle"),
-	FIELD("debounce_down", debounce_down_us,
-	      "time for debounce on key down"),
-	FIELD("debounce_up", debounce_up_us, "time for debounce on key up"),
-	FIELD("fifo_max_depth", fifo_max_depth,
-	      "maximum depth to allow for fifo (0 = disable)"),
-	FIELD("flags", flags, "0 to disable scanning, 1 to enable"),
-};
-
-static const struct param_info *find_field(const struct param_info *params,
-		int count, const char *name, unsigned int *nump)
-{
-	const struct param_info *param;
-	int i;
-
-	for (i = 0, param = params; i < count; i++, param++) {
-		if (0 == strcmp(param->name, name)) {
-			if (nump)
-				*nump = i;
-			return param;
-		}
-	}
-
-	fprintf(stderr, "Unknown parameter '%s'\n", name);
-	return NULL;
-}
-
-static int get_value(const struct param_info *param, const char *config)
-{
-	const char *field;
-
-	field = config + param->offset;
-	switch (param->size) {
-	case 1:
-		return *(uint8_t *)field;
-	case 2:
-		return *(uint16_t *)field;
-	case 4:
-		return *(uint32_t *)field;
-	default:
-		fprintf(stderr, "Internal error: unknown size %d\n",
-			param->size);
-	}
-
-	return -1;
-}
-
-static int show_fields(struct ec_mkbp_config *config, int argc, char *argv[])
-{
-	const struct param_info *param;
-	uint32_t mask;
-	int i;
-
-	if (!argc) {
-		mask = -1U;	/* show all fields */
-	} else {
-		mask = 0;
-		while (argc > 0) {
-			unsigned int num;
-
-			param = find_field(keyconfig_params,
-					   ARRAY_SIZE(keyconfig_params),
-					   argv[0], &num);
-			if (!param)
-				return -1;
-			mask |= 1 << num;
-			argc--;
-			argv++;
-		}
-	}
-
-	param = keyconfig_params;
-	for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
-		if (mask & BIT(i)) {
-			fprintf(stderr, "%-12s   %u\n", param->name,
-				get_value(param, (char *)config));
-		}
-	}
-
-	return 0;
-}
-
-static int cmd_kbinfo(int argc, char *argv[])
-{
-	struct ec_params_mkbp_info info = {
-		.info_type = EC_MKBP_INFO_KBD,
-	};
-	struct ec_response_mkbp_info resp;
-	int rv;
-
-	if (argc > 1) {
-		fprintf(stderr, "Too many args\n");
-		return -1;
-	}
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &info, sizeof(info), &resp,
-			sizeof(resp));
-	if (rv < 0)
-		return rv;
-
-	printf("Matrix rows: %d\n", resp.rows);
-	printf("Matrix columns: %d\n", resp.cols);
-
-	return 0;
-}
-
-static int cmd_kbid(int argc, char *argv[])
-{
-	struct ec_response_keyboard_id response;
-	int rv;
-
-	if (argc > 1) {
-		fprintf(stderr, "Too many args\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_GET_KEYBOARD_ID, 0, NULL, 0, &response,
-			sizeof(response));
-	if (rv < 0)
-		return rv;
-	switch (response.keyboard_id) {
-	case KEYBOARD_ID_UNSUPPORTED:
-		/* Keyboard ID was not supported */
-		printf("Keyboard doesn't support ID\n");
-		break;
-	case KEYBOARD_ID_UNREADABLE:
-		/* Ghosting ID was detected */
-		printf("Reboot and keep hands off the keyboard during"
-		       " next boot-up\n");
-		break;
-	default:
-		/* Valid keyboard ID value was reported*/
-		printf("%x\n", response.keyboard_id);
-	}
-	return rv;
-}
-
-static int cmd_keyconfig(int argc, char *argv[])
-{
-	struct ec_params_mkbp_set_config req;
-	int cmd;
-	int rv;
-
-	if (argc < 2) {
-		const struct param_info *param;
-		int i;
-
-		fprintf(stderr, "Usage: %s get [<param>] - print params\n"
-			"\t%s set [<param>> <value>]\n"
-			"   Available params are: (all time values are in us)",
-			argv[0], argv[0]);
-
-		param = keyconfig_params;
-		for (i = 0; i < ARRAY_SIZE(keyconfig_params); i++, param++) {
-			fprintf(stderr, "%-12s   %s\n", param->name,
-				param->name);
-		}
-		return -1;
-	}
-
-	/* Get the command */
-	if (0 == strcmp(argv[1], "get")) {
-		cmd = EC_CMD_MKBP_GET_CONFIG;
-	} else if (0 == strcmp(argv[1], "set")) {
-		cmd = EC_CMD_MKBP_SET_CONFIG;
-	} else {
-		fprintf(stderr, "Invalid command '%s\n", argv[1]);
-		return -1;
-	}
-
-	switch (cmd) {
-	case EC_CMD_MKBP_GET_CONFIG:
-		/* Read the existing config */
-		rv = ec_command(cmd, 0, NULL, 0, &req, sizeof(req));
-		if (rv < 0)
-			return rv;
-		show_fields(&req.config, argc - 2, argv + 2);
-		break;
-	}
-
-	return 0;
-}
-
-static const char * const mkbp_button_strings[] = {
-	[EC_MKBP_POWER_BUTTON] = "Power",
-	[EC_MKBP_VOL_UP] = "Volume up",
-	[EC_MKBP_VOL_DOWN] = "Volume down",
-	[EC_MKBP_RECOVERY] = "Recovery",
-};
-
-static const char * const mkbp_switch_strings[] = {
-	[EC_MKBP_LID_OPEN] = "Lid open",
-	[EC_MKBP_TABLET_MODE] = "Tablet mode",
-	[EC_MKBP_BASE_ATTACHED] = "Base attached",
-};
-
-static int cmd_mkbp_get(int argc, char *argv[])
-{
-	struct ec_params_mkbp_info p;
-	union ec_response_get_next_data r;
-	int rv;
-	int i;
-	uint32_t supported;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <buttons|switches>\n", argv[0]);
-		return -1;
-	}
-
-	if (strncmp(argv[1], "button", 6) == 0) {
-		p.event_type = EC_MKBP_EVENT_BUTTON;
-	} else if (strncmp(argv[1], "switch", 6) == 0) {
-		p.event_type = EC_MKBP_EVENT_SWITCH;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
-		return -1;
-	}
-
-	p.info_type = EC_MKBP_INFO_SUPPORTED;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-	if (p.event_type == EC_MKBP_EVENT_BUTTON)
-		supported = r.buttons;
-	else if (p.event_type == EC_MKBP_EVENT_SWITCH)
-		supported = r.switches;
-	else
-		return -1;
-
-	p.info_type = EC_MKBP_INFO_CURRENT;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	if (p.event_type == EC_MKBP_EVENT_BUTTON) {
-		printf("MKBP buttons state: 0x%04x (supported: 0x%04x)\n",
-		       r.buttons, supported);
-		for (i = 0; i < ARRAY_SIZE(mkbp_button_strings); i++) {
-			if (supported & BIT(i) && mkbp_button_strings[i]) {
-				printf("%s: %s\n", mkbp_button_strings[i],
-				       r.buttons & BIT(i) ? "ON" : "OFF");
-				supported &= ~BIT(i);
-			}
-		}
-		if (supported)
-			printf("Unknown buttons: 0x%04x\n", supported);
-	} else if (p.event_type == EC_MKBP_EVENT_SWITCH) {
-		printf("MKBP switches state: 0x%04x (supported: 0x%04x)\n",
-		       r.switches, supported);
-		for (i = 0; i < ARRAY_SIZE(mkbp_switch_strings); i++) {
-			if (supported & BIT(i) && mkbp_switch_strings[i]) {
-				printf("%s: %s\n", mkbp_switch_strings[i],
-				       r.switches & BIT(i) ? "ON" : "OFF");
-				supported &= ~BIT(i);
-			}
-		}
-		if (supported)
-			printf("Unknown switches: 0x%04x\n", supported);
-	}
-
-	return 0;
-}
-
-static int cmd_mkbp_wake_mask(int argc, char *argv[])
-{
-	struct ec_params_mkbp_event_wake_mask p;
-	struct ec_response_mkbp_event_wake_mask r;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s get <event|hostevent>\n"
-			"\t%s set <event|hostevent> <mask>\n", argv[0],
-			argv[0]);
-		return -1;
-	}
-
-	/* Determine if the user want to get or set the wake mask. */
-	if (strncmp(argv[1], "get", 3) == 0) {
-		p.action = GET_WAKE_MASK;
-	} else if (strncmp(argv[1], "set", 3) == 0) {
-		p.action = SET_WAKE_MASK;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[1]);
-		return -1;
-	}
-
-	/* Determine which mask is of interest. */
-	if (strncmp(argv[2], "event", 5) == 0) {
-		p.mask_type = EC_MKBP_EVENT_WAKE_MASK;
-	} else if (strncmp(argv[2], "hostevent", 9) == 0) {
-		p.mask_type = EC_MKBP_HOST_EVENT_WAKE_MASK;
-	} else {
-		fprintf(stderr, "Invalid param: '%s'\n", argv[2]);
-		return -1;
-	}
-
-	if (p.action == SET_WAKE_MASK) {
-		char *e;
-
-		if (argc < 4) {
-			fprintf(stderr, "Missing mask value!");
-			return -1;
-		}
-
-		p.new_wake_mask = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad mask: '%s'", argv[1]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0) {
-		if (rv == -EECRESULT-EC_RES_INVALID_PARAM) {
-			fprintf(stderr, "Unknown mask, or mask is not in use.  "
-				"You may need to enable the "
-				"CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n"
-				, p.mask_type == EC_MKBP_EVENT_WAKE_MASK ?
-				"EVENT" : "HOSTEVENT");
-		}
-		return rv;
-	}
-
-	if (p.action == GET_WAKE_MASK)
-		printf("MBKP %s wake mask: 0x%08x\n", argv[2], r.wake_mask);
-	else if (p.action == SET_WAKE_MASK)
-		printf("MKBP %s wake mask set.\n", argv[2]);
-
-	return 0;
-}
-
-/* Index is already checked. argv[0] is first param value */
-static int cmd_tmp006cal_v0(int idx, int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_calibration pg;
-	struct ec_response_tmp006_get_calibration_v0 rg;
-	struct ec_params_tmp006_set_calibration_v0 ps;
-	float val;
-	char *e;
-	int i, rv;
-
-	/* Get current values */
-	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0,
-			&pg, sizeof(pg), &rg, sizeof(rg));
-	if (rv < 0)
-		return rv;
-
-	if (!argc) {
-		/* If no new values are given, just print what we have */
-		printf("S0: %e\n", rg.s0);
-		printf("b0: %e\n", rg.b0);
-		printf("b1: %e\n", rg.b1);
-		printf("b2: %e\n", rg.b2);
-		return EC_SUCCESS;
-	}
-
-	/* Prepare to reuse the current values */
-	memset(&ps, 0, sizeof(ps));
-	ps.index = idx;
-	ps.s0 = rg.s0;
-	ps.b0 = rg.b0;
-	ps.b1 = rg.b1;
-	ps.b2 = rg.b2;
-
-	/* Parse up to four args, skipping any that are just "-" */
-	for (i = 0; i < argc && i < 4; i++) {
-		if (!strcmp(argv[i], "-"))
-			continue;
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			fprintf(stderr,
-				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
-				argv[i]);
-			return -1;
-		}
-		switch (i) {
-		case 0:
-			ps.s0 = val;
-			break;
-		case 1:
-			ps.b0 = val;
-			break;
-		case 2:
-			ps.b1 = val;
-			break;
-		case 3:
-			ps.b2 = val;
-			break;
-		}
-	}
-
-	/* Set 'em */
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0,
-			  &ps, sizeof(ps), NULL, 0);
-}
-
-/* Index is already checked. argv[0] is first param value */
-static int cmd_tmp006cal_v1(int idx, int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_calibration pg;
-	struct ec_response_tmp006_get_calibration_v1 *rg =
-		(struct ec_response_tmp006_get_calibration_v1 *)(ec_inbuf);
-	struct ec_params_tmp006_set_calibration_v1 *ps =
-		(struct ec_params_tmp006_set_calibration_v1 *)(ec_outbuf);
-	float val;
-	char *e;
-	int i, rv, cmdsize;
-
-	/* Algorithm 1 parameter names */
-	static const char * const alg1_pname[] = {
-		"s0", "a1", "a2", "b0", "b1", "b2", "c2",
-		"d0", "d1", "ds", "e0", "e1",
-	};
-
-	/* Get current values */
-	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1,
-			&pg, sizeof(pg), rg, ec_max_insize);
-	if (rv < 0)
-		return rv;
-
-	if (!argc) {
-		/* If no new values are given, just print what we have */
-		printf("algorithm:  %d\n", rg->algorithm);
-		printf("params:\n");
-		/* We only know about alg 1 at the moment */
-		if (rg->algorithm == 1)
-			for (i = 0; i < rg->num_params; i++)
-				printf("  %s  %e\n", alg1_pname[i], rg->val[i]);
-		else
-			for (i = 0; i < rg->num_params; i++)
-				printf("  param%d  %e\n", i, rg->val[i]);
-		return EC_SUCCESS;
-	}
-
-	/* Prepare to reuse the current values */
-	memset(ps, 0, ec_max_outsize);
-	ps->index = idx;
-	ps->algorithm = rg->algorithm;
-	ps->num_params = rg->num_params;
-	for (i = 0; i < rg->num_params; i++)
-		ps->val[i] = rg->val[i];
-
-	/* Parse the args, skipping any that are just "-" */
-	for (i = 0; i < argc && i < rg->num_params; i++) {
-		if (!strcmp(argv[i], "-"))
-			continue;
-		val = strtod(argv[i], &e);
-		if (e && *e) {
-			fprintf(stderr,
-				"Bad arg \"%s\". Use \"-\" to skip a param.\n",
-				argv[i]);
-			return -1;
-		}
-		ps->val[i] = val;
-	}
-
-	/* Set 'em */
-	cmdsize = sizeof(*ps) + ps->num_params * sizeof(ps->val[0]);
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1,
-			  ps, cmdsize, NULL, 0);
-}
-
-int cmd_tmp006cal(int argc, char *argv[])
-{
-	char *e;
-	int idx;
-
-	if (argc < 2) {
-		fprintf(stderr, "Must specify tmp006 index.\n");
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || idx < 0 || idx > 255) {
-		fprintf(stderr, "Bad index.\n");
-		return -1;
-	}
-
-	/* Pass just the params (if any) to the helper function */
-	argc -= 2;
-	argv += 2;
-
-	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 1))
-		return cmd_tmp006cal_v1(idx, argc, argv);
-
-	if (ec_cmd_version_supported(EC_CMD_TMP006_GET_CALIBRATION, 0))
-		return cmd_tmp006cal_v0(idx, argc, argv);
-
-	printf("The EC is being stupid\n");
-	return -1;
-}
-
-int cmd_tmp006raw(int argc, char *argv[])
-{
-	struct ec_params_tmp006_get_raw p;
-	struct ec_response_tmp006_get_raw r;
-	char *e;
-	int idx;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Must specify tmp006 index.\n");
-		return -1;
-	}
-
-	idx = strtol(argv[1], &e, 0);
-	if ((e && *e) || idx < 0 || idx > 255) {
-		fprintf(stderr, "Bad index.\n");
-		return -1;
-	}
-
-	p.index = idx;
-
-	rv = ec_command(EC_CMD_TMP006_GET_RAW, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("T: %d.%02d K\n", r.t / 100, r.t % 100);
-	printf("V: %d nV\n", r.v);
-	return EC_SUCCESS;
-}
-
-static int cmd_hang_detect(int argc, char *argv[])
-{
-	struct ec_params_hang_detect req;
-	char *e;
-
-	memset(&req, 0, sizeof(req));
-
-	if (argc == 2 && !strcasecmp(argv[1], "stop")) {
-		req.flags = EC_HANG_STOP_NOW;
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	if (argc == 2 && !strcasecmp(argv[1], "start")) {
-		req.flags = EC_HANG_START_NOW;
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	if (argc == 4) {
-		req.flags = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad flags.\n");
-			return -1;
-		}
-
-		req.host_event_timeout_msec = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad event timeout.\n");
-			return -1;
-		}
-
-		req.warm_reboot_timeout_msec = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad reboot timeout.\n");
-			return -1;
-		}
-
-		printf("hang flags=0x%x\n"
-		       "event_timeout=%d ms\n"
-		       "reboot_timeout=%d ms\n",
-		       req.flags, req.host_event_timeout_msec,
-		       req.warm_reboot_timeout_msec);
-
-		return ec_command(EC_CMD_HANG_DETECT, 0, &req, sizeof(req),
-				  NULL, 0);
-	}
-
-	fprintf(stderr,
-		"Must specify start/stop or <flags> <event_ms> <reboot_ms>\n");
-	return -1;
-}
-
-enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
-};
-
-int cmd_port80_read(int argc, char *argv[])
-{
-	struct ec_params_port80_read p;
-	int cmdver = 1, rv;
-	int i, head, tail;
-	uint16_t *history;
-	uint32_t writes, history_size;
-	struct ec_response_port80_read rsp;
-	int printed = 0;
-
-	if (!ec_cmd_version_supported(EC_CMD_PORT80_READ, cmdver)) {
-		/* fall back to last boot */
-		struct ec_response_port80_last_boot r;
-		rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0,
-				NULL, 0, &r, sizeof(r));
-		fprintf(stderr, "Last boot %2x\n", r.code);
-		printf("done.\n");
-		return 0;
-	}
-
-
-	/* read writes and history_size */
-	p.subcmd = EC_PORT80_GET_INFO;
-	rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-			&p, sizeof(p), &rsp, sizeof(rsp));
-	if (rv < 0) {
-		fprintf(stderr, "Read error at writes\n");
-		return rv;
-	}
-	writes = rsp.get_info.writes;
-	history_size = rsp.get_info.history_size;
-
-	history = (uint16_t *)(
-		malloc(history_size * sizeof(uint16_t)));
-	if (!history) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		return -1;
-	}
-	/* As the history buffer is quite large, we read data in chunks, with
-	    size in bytes of EC_PORT80_SIZE_MAX in each chunk.
-	    Incrementing offset until all history buffer has been read. To
-	    simplify the design, chose HISTORY_LEN is always multiple of
-	    EC_PORT80_SIZE_MAX.
-
-	    offset: entry offset from the beginning of history buffer.
-	    num_entries: number of entries requested.
-	*/
-	p.subcmd = EC_PORT80_READ_BUFFER;
-	for (i = 0; i < history_size; i += EC_PORT80_SIZE_MAX) {
-		p.read_buffer.offset = i;
-		p.read_buffer.num_entries = EC_PORT80_SIZE_MAX;
-		rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-				&p, sizeof(p), &rsp, sizeof(rsp));
-		if (rv < 0) {
-			fprintf(stderr, "Read error at offset %d\n", i);
-			free(history);
-			return rv;
-		}
-		memcpy((void *)(history + i), rsp.data.codes,
-			EC_PORT80_SIZE_MAX*sizeof(uint16_t));
-	}
-
-	head = writes;
-	if (head > history_size)
-		tail = head - history_size;
-	else
-		tail = 0;
-
-	fprintf(stderr, "Port 80 writes");
-	for (i = tail; i < head; i++) {
-		int e = history[i % history_size];
-		switch (e) {
-		case PORT_80_EVENT_RESUME:
-			fprintf(stderr, "\n(S3->S0)");
-			printed = 0;
-			break;
-		case PORT_80_EVENT_RESET:
-			fprintf(stderr, "\n(RESET)");
-			printed = 0;
-			break;
-		default:
-			if (!(printed++ % 20))
-				fprintf(stderr, "\n ");
-			fprintf(stderr, " %02x", e);
-		}
-	}
-	fprintf(stderr, " <--new\n");
-
-	free(history);
-	printf("done.\n");
-	return 0;
-}
-
-int cmd_force_lid_open(int argc, char *argv[])
-{
-	struct ec_params_force_lid_open p;
-	char *e;
-	int rv;
-
-	if (argc != 2) {
-		fprintf(stderr, "Usage: %s <0|1>\n", argv[0]);
-		return -1;
-	}
-	p.enabled = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad value.\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_FORCE_LID_OPEN, 0, &p, sizeof(p), NULL, 0);
-	if (rv < 0)
-		return rv;
-	printf("Success.\n");
-	return 0;
-}
-
-int cmd_charge_port_override(int argc, char *argv[])
-{
-	struct ec_params_charge_port_override p;
-	char *e;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <port# | dontcharge | off>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "dontcharge"))
-		p.override_port = OVERRIDE_DONT_CHARGE;
-	else if (!strcasecmp(argv[1], "off"))
-		p.override_port = OVERRIDE_OFF;
-	else {
-		p.override_port = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad parameter.\n");
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Override port set to %d\n", p.override_port);
-	return 0;
-}
-
-static void cmd_pchg_help(char *cmd)
-{
-	fprintf(stderr,
-	"  Usage1: %s\n"
-	"          Print the number of ports.\n"
-	"\n"
-	"  Usage2: %s <port>\n"
-	"          Print the status of <port>.\n"
-	"\n"
-	"  Usage3: %s <port> reset\n"
-	"          Reset <port>.\n"
-	"\n"
-	"  Usage4: %s <port> update <version> <addr1> <file1> <addr2> <file2> ...\n"
-	"          Update firmware of <port>.\n",
-	cmd, cmd, cmd, cmd);
-}
-
-static int cmd_pchg_info(const struct ec_response_pchg *res)
-{
-	static const char * const pchg_state_text[] = EC_PCHG_STATE_TEXT;
-
-	BUILD_ASSERT(ARRAY_SIZE(pchg_state_text) == PCHG_STATE_COUNT);
-
-	printf("State: %s (%d)\n", res->state < PCHG_STATE_COUNT
-	       ? pchg_state_text[res->state] : "UNDEF", res->state);
-	printf("Battery: %u%%\n", res->battery_percentage);
-	printf("Errors: 0x%x\n", res->error);
-	printf("FW Version: 0x%x\n", res->fw_version);
-	printf("Dropped events: %u\n", res->dropped_event_count);
-	return 0;
-}
-
-static int cmd_pchg_wait_event(int port, uint32_t expected)
-{
-	struct ec_response_get_next_event_v1 event;
-	const long timeout = 5000;
-	uint32_t *e = &event.data.host_event;
-	int rv;
-
-	rv = wait_event(EC_MKBP_EVENT_PCHG, &event, sizeof(event), timeout);
-	if (rv < 0)
-		return rv;
-
-	if (EC_MKBP_PCHG_EVENT_TO_PORT(*e) == port) {
-		if (*e & EC_MKBP_PCHG_UPDATE_ERROR) {
-			fprintf(stderr, "\nReceived update error\n");
-			return -1;
-		}
-		if (*e & expected)
-			return 0;
-	}
-
-	fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n",
-		expected, *e);
-	return -1;
-}
-
-static int cmd_pchg_update_open(int port, uint32_t version,
-				uint32_t *block_size, uint32_t *crc)
-{
-	struct ec_params_pchg_update *p =
-		(struct ec_params_pchg_update *)(ec_outbuf);
-	struct ec_response_pchg_update *r =
-		(struct ec_response_pchg_update *)(ec_inbuf);
-	int rv;
-
-	/* Open session. */
-	p->port = port;
-	p->cmd = EC_PCHG_UPDATE_CMD_OPEN;
-	p->version = version;
-	rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p), r, sizeof(*r));
-	if (rv < 0) {
-		fprintf(stderr, "\nFailed to open update session: %d\n", rv);
-		return rv;
-	}
-
-	if (r->block_size + sizeof(*p) > ec_max_outsize) {
-		fprintf(stderr, "\nBlock size (%d) is too large.\n",
-			r->block_size);
-		return -1;
-	}
-
-	rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_UPDATE_OPENED);
-	if (rv)
-		return rv;
-
-	printf("Opened update session (port=%d ver=0x%x bsize=%d):\n",
-	       port, version, r->block_size);
-
-	*block_size = r->block_size;
-	crc32_ctx_init(crc);
-
-	return 0;
-}
-
-static int cmd_pchg_update_write(int port, uint32_t address,
-				 const char *filename, uint32_t block_size,
-				 uint32_t *crc)
-{
-	struct ec_params_pchg_update *p =
-		(struct ec_params_pchg_update *)(ec_outbuf);
-	FILE *fp;
-	size_t len, total;
-	int progress = 0;
-	int rv;
-
-	fp = fopen(filename, "rb");
-	if (!fp) {
-		fprintf(stderr, "\nCan't open %s: %s\n",
-			filename, strerror(errno));
-		return -1;
-	}
-
-	fseek(fp, 0L, SEEK_END);
-	total = ftell(fp);
-	rewind(fp);
-	printf("Writing %s (%zu bytes).\n", filename, total);
-
-	p->cmd = EC_PCHG_UPDATE_CMD_WRITE;
-	p->addr = address;
-
-	/* Write firmware in blocks. */
-	len = fread(p->data, 1, block_size, fp);
-	while (len > 0) {
-		int previous_progress = progress;
-		int i;
-
-		crc32_ctx_hash(crc, p->data, len);
-		p->size = len;
-		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p,
-				sizeof(*p) + len, NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "\nFailed to write FW: %d\n", rv);
-			fclose(fp);
-			return rv;
-		}
-
-		rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_WRITE_COMPLETE);
-		if (rv)
-			return rv;
-
-		p->addr += len;
-		progress = (p->addr - address) * 100 / total;
-		for (i = 0; i < progress - previous_progress; i++) {
-			printf("*");
-			fflush(stdout);
-		}
-
-		len = fread(p->data, 1, block_size, fp);
-	}
-
-	printf("\n");
-	fclose(fp);
-
-	return 0;
-}
-
-static int cmd_pchg_update_close(int port, uint32_t *crc)
-{
-	struct ec_params_pchg_update *p =
-		(struct ec_params_pchg_update *)(ec_outbuf);
-	int rv;
-
-	p->cmd = EC_PCHG_UPDATE_CMD_CLOSE;
-	p->crc32 = crc32_ctx_result(crc);
-	rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p), NULL, 0);
-
-	if (rv < 0) {
-		fprintf(stderr, "\nFailed to close update session: %d\n", rv);
-		return rv;
-	}
-
-	rv = cmd_pchg_wait_event(port, EC_MKBP_PCHG_UPDATE_CLOSED);
-	if (rv)
-		return rv;
-
-	printf("Firmware was updated successfully (CRC32=0x%x).\n", p->crc32);
-
-	return 0;
-}
-
-static int cmd_pchg(int argc, char *argv[])
-{
-	const size_t max_input_files = 8;
-	int port, port_count;
-	struct ec_response_pchg_count rcnt;
-	struct ec_params_pchg p;
-	struct ec_response_pchg r;
-	char *e;
-	int rv;
-
-	rv = ec_command(EC_CMD_PCHG_COUNT, 0, NULL, 0, &rcnt, sizeof(rcnt));
-	if (rv < 0) {
-		fprintf(stderr, "\nFailed to get port count: %d\n", rv);
-		return rv;
-	}
-	port_count = rcnt.port_count;
-
-	if (argc == 1) {
-		/* Usage.1 */
-		printf("%d\n", port_count);
-		return 0;
-	}
-
-	port = strtol(argv[1], &e, 0);
-	if ((e && *e) || port >= port_count) {
-		fprintf(stderr, "\nBad port index: %s\n", argv[1]);
-		cmd_pchg_help(argv[0]);
-		return -1;
-	}
-
-	p.port = port;
-	rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0) {
-		fprintf(stderr, "\nError code: %d\n", rv);
-		return rv;
-	}
-
-	if (argc == 2) {
-		/* Usage.2 */
-		return cmd_pchg_info(&r);
-	} else if (argc == 3 && !strcmp(argv[2], "reset")) {
-		/* Usage.3 */
-		struct ec_params_pchg_update *u =
-			(struct ec_params_pchg_update *)(ec_outbuf);
-
-		u->cmd = EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL;
-		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, u, sizeof(*u), NULL, 0);
-		if (rv < 0) {
-			fprintf(stderr, "\nFailed to reset port %d: %d\n",
-				port, rv);
-			cmd_pchg_help(argv[0]);
-			return rv;
-		}
-		printf("Reset port %d complete.\n", port);
-		return 0;
-	} else if (argc >= 6 && !strcmp(argv[2], "update")) {
-		/*
-		 * Usage.4:
-		 * argv[3]: <version>
-		 * argv[4]: <addr1>
-		 * argv[5]: <file1>
-		 * argv[6]: <addr2>
-		 * argv[7]: <file2>
-		 * ...
-		 */
-		uint32_t address, version;
-		uint32_t block_size = 0;
-		uint32_t crc;
-		int i;
-
-		if (argc > 4 + max_input_files * 2) {
-			fprintf(stderr, "\nToo many input files.\n");
-			return -1;
-		}
-
-		version = strtol(argv[3], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "\nBad version: %s.\n", argv[3]);
-			cmd_pchg_help(argv[0]);
-			return -1;
-		}
-
-		rv = cmd_pchg_update_open(port, version, &block_size, &crc);
-		if (rv < 0 || block_size == 0) {
-			fprintf(stderr, "\nFailed to open update session: %d\n",
-				rv);
-			return -1;
-		}
-
-		/* Write files one by one. */
-		for (i = 4; i + 1 < argc; i += 2) {
-			address = strtol(argv[i], &e, 0);
-			if (e && *e) {
-				fprintf(stderr, "\nBad address: %s\n", argv[i]);
-				cmd_pchg_help(argv[0]);
-				return -1;
-			}
-			rv = cmd_pchg_update_write(port, address, argv[i+1],
-						   block_size, &crc);
-			if (rv < 0) {
-				fprintf(stderr,
-					"\nFailed to write file '%s': %d",
-					argv[i+i], rv);
-				return -1;
-			}
-		}
-
-		rv = cmd_pchg_update_close(port, &crc);
-		if (rv < 0) {
-			fprintf(stderr, "\nFailed to close update session: %d",
-				rv);
-			return -1;
-		}
-
-		return 0;
-	}
-
-	fprintf(stderr, "Invalid parameter\n\n");
-	cmd_pchg_help(argv[0]);
-
-	return -1;
-}
-
-int cmd_pd_log(int argc, char *argv[])
-{
-	union {
-		struct ec_response_pd_log r;
-		uint32_t words[8]; /* space for the payload */
-	} u;
-	struct mcdp_info minfo;
-	struct ec_response_usb_pd_power_info pinfo;
-	int rv;
-	unsigned long long milliseconds;
-	unsigned seconds;
-	time_t now;
-	struct tm ltime;
-	char time_str[64];
-
-	while (1) {
-		now = time(NULL);
-		rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0,
-				NULL, 0, &u, sizeof(u));
-		if (rv < 0)
-			return rv;
-
-		if (u.r.type == PD_EVENT_NO_ENTRY) {
-			printf("--- END OF LOG ---\n");
-			break;
-		}
-
-		/* the timestamp is in 1024th of seconds */
-		milliseconds = ((uint64_t)u.r.timestamp <<
-					 PD_LOG_TIMESTAMP_SHIFT) / 1000;
-		/* the timestamp is the number of milliseconds in the past */
-		seconds = (milliseconds + 999) / 1000;
-		milliseconds -= seconds * 1000;
-		now -= seconds;
-		localtime_r(&now, &ltime);
-		strftime(time_str, sizeof(time_str), "%F %T", &ltime);
-		printf("%s.%03lld P%d ", time_str, -milliseconds,
-			PD_LOG_PORT(u.r.size_port));
-		if (u.r.type == PD_EVENT_MCU_CHARGE) {
-			if (u.r.data & CHARGE_FLAGS_OVERRIDE)
-				printf("override ");
-			if (u.r.data & CHARGE_FLAGS_DELAYED_OVERRIDE)
-				printf("pending_override ");
-			memcpy(&pinfo.meas, u.r.payload,
-				sizeof(struct usb_chg_measures));
-			pinfo.dualrole = !!(u.r.data & CHARGE_FLAGS_DUAL_ROLE);
-			pinfo.role = u.r.data & CHARGE_FLAGS_ROLE_MASK;
-			pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK)
-					>> CHARGE_FLAGS_TYPE_SHIFT;
-			pinfo.max_power = 0;
-			print_pd_power_info(&pinfo);
-		} else if (u.r.type == PD_EVENT_MCU_CONNECT) {
-			printf("New connection\n");
-		} else if (u.r.type == PD_EVENT_MCU_BOARD_CUSTOM) {
-			printf("Board-custom event\n");
-		} else if (u.r.type == PD_EVENT_ACC_RW_FAIL) {
-			printf("RW signature check failed\n");
-		} else if (u.r.type == PD_EVENT_PS_FAULT) {
-			static const char * const fault_names[] = {
-				"---", "OCP", "fast OCP", "OVP", "Discharge"
-			};
-			const char *fault = u.r.data < ARRAY_SIZE(fault_names) ?
-					fault_names[u.r.data] : "???";
-			printf("Power supply fault: %s\n", fault);
-		} else if (u.r.type == PD_EVENT_VIDEO_DP_MODE) {
-			printf("DP mode %sabled\n", (u.r.data == 1) ?
-			       "en" : "dis");
-		} else if (u.r.type == PD_EVENT_VIDEO_CODEC) {
-			memcpy(&minfo, u.r.payload,
-			       sizeof(struct mcdp_info));
-			printf("HDMI info: family:%04x chipid:%04x "
-			       "irom:%d.%d.%d fw:%d.%d.%d\n",
-			       MCDP_FAMILY(minfo.family),
-			       MCDP_CHIPID(minfo.chipid),
-			       minfo.irom.major, minfo.irom.minor,
-			       minfo.irom.build, minfo.fw.major,
-			       minfo.fw.minor, minfo.fw.build);
-		} else { /* Unknown type */
-			int i;
-			printf("Event %02x (%04x) [", u.r.type, u.r.data);
-			for (i = 0; i < PD_LOG_SIZE(u.r.size_port); i++)
-				printf("%02x ", u.r.payload[i]);
-			printf("]\n");
-		}
-	}
-
-	return 0;
-}
-
-int cmd_pd_control(int argc, char *argv[])
-{
-	struct ec_params_pd_control p;
-	int rv;
-
-	if (argc < 2) {
-		fprintf(stderr, "Missing parameter\n");
-		return -1;
-	}
-
-	/* Parse command */
-	if (!strcmp(argv[1], "reset"))
-		p.subcmd = PD_RESET;
-	else if (!strcmp(argv[1], "suspend"))
-		p.subcmd = PD_SUSPEND;
-	else if (!strcmp(argv[1], "resume"))
-		p.subcmd = PD_RESUME;
-	else if (!strcmp(argv[1], "disable"))
-		p.subcmd = PD_CONTROL_DISABLE;
-	else if (!strcmp(argv[1], "on") || !strcmp(argv[1], "chip_on"))
-		p.subcmd = PD_CHIP_ON;
-	else {
-		fprintf(stderr, "Unknown command: %s\n", argv[1]);
-		return -1;
-	}
-
-	if (argc == 2) {
-		p.chip = 0;
-	} else {
-		char *e;
-		p.chip = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad port number '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = ec_command(EC_CMD_PD_CONTROL, 0, &p, sizeof(p), NULL, 0);
-	return (rv < 0 ? rv : 0);
-}
-
-int cmd_pd_chip_info(int argc, char *argv[])
-{
-	struct ec_params_pd_chip_info p;
-	struct ec_response_pd_chip_info_v1 r;
-	char *e;
-	int rv;
-	int cmdver = 1;
-
-	if (argc < 2 || 3 < argc) {
-		fprintf(stderr, "Usage: %s <port> [<live>]\n"
-			"live parameter can take values 0 or 1\n"
-			"0 -> Return hard-coded value for VID/PID and\n"
-			"     cached value for Firmware Version\n"
-			"1 -> Return live chip value for VID/PID/FW Version\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port number.\n");
-		return -1;
-	}
-
-	p.live = 0;
-	if (argc == 3) {
-		p.live = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "invalid arg \"%s\"\n", argv[2]);
-			return -1;
-		}
-	}
-
-	if (!ec_cmd_version_supported(EC_CMD_PD_CHIP_INFO, cmdver))
-		cmdver = 0;
-
-	rv = ec_command(EC_CMD_PD_CHIP_INFO, cmdver, &p, sizeof(p), &r,
-			sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("vendor_id: 0x%x\n", r.vendor_id);
-	printf("product_id: 0x%x\n", r.product_id);
-	printf("device_id: 0x%x\n", r.device_id);
-
-	if (r.fw_version_number != -1)
-		printf("fw_version: 0x%" PRIx64 "\n", r.fw_version_number);
-	else
-		printf("fw_version: UNSUPPORTED\n");
-
-	if (cmdver >= 1)
-		printf("min_req_fw_version: 0x%" PRIx64 "\n",
-		       r.min_req_fw_version_number);
-	else
-		printf("min_req_fw_version: UNSUPPORTED\n");
-
-	return 0;
-}
-
-int cmd_pd_write_log(int argc, char *argv[])
-{
-	struct ec_params_pd_write_log_entry p;
-	char *e;
-
-	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <log_type> <port>\n",
-			argv[0]);
-		return -1;
-	}
-
-	if (!strcasecmp(argv[1], "charge"))
-		p.type = PD_EVENT_MCU_CHARGE;
-	else {
-		p.type = strtol(argv[1], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad log_type parameter.\n");
-			return -1;
-		}
-	}
-
-	p.port = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port parameter.\n");
-		return -1;
-	}
-
-	return ec_command(EC_CMD_PD_WRITE_LOG_ENTRY, 0, &p, sizeof(p), NULL, 0);
-}
-
-int cmd_typec_control(int argc, char *argv[])
-{
-	struct ec_params_typec_control p;
-	long conversion_result;
-	char *endptr;
-	int rv;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <port> <command> [args]\n"
-			"  <port> is the type-c port to query\n"
-			"  <command> is one of:\n"
-			"    0: Exit modes\n"
-			"    1: Clear events\n"
-			"        args: <event mask>\n"
-			"    2: Enter mode\n"
-			"        args: <0: DP, 1:TBT, 2:USB4>\n",
-			argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p.command = strtol(argv[2], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad command\n");
-		return -1;
-	}
-
-	switch (p.command) {
-	case TYPEC_CONTROL_COMMAND_CLEAR_EVENTS:
-		if (argc < 4) {
-			fprintf(stderr, "Missing event mask\n");
-			return -1;
-		}
-
-		p.clear_events_mask = strtol(argv[3], &endptr, 0);
-		if (endptr && *endptr) {
-			fprintf(stderr, "Bad event mask\n");
-			return -1;
-		}
-		break;
-	case TYPEC_CONTROL_COMMAND_ENTER_MODE:
-		if (argc < 4) {
-			fprintf(stderr, "Missing mode\n");
-			return -1;
-		}
-
-		conversion_result = strtol(argv[3], &endptr, 0);
-		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
-				conversion_result < 0) {
-			fprintf(stderr, "Bad mode\n");
-			return -1;
-		}
-		p.mode_to_enter = conversion_result;
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return -1;
-
-	return 0;
-}
-
-int cmd_typec_discovery(int argc, char *argv[])
-{
-	struct ec_params_typec_discovery p;
-	struct ec_response_typec_discovery *r =
-				(struct ec_response_typec_discovery *)ec_inbuf;
-	char *e;
-	int rv, i, j;
-
-	if (argc < 3) {
-		fprintf(stderr,
-			"Usage: %s <port> <type>\n"
-			"  <port> is the type-c port to query\n"
-			"  <type> is one of:\n"
-			"    0: SOP\n"
-			"    1: SOP prime\n", argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	p.partner_type = strtol(argv[2], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad type\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv < 0)
-		return -1;
-
-	if (r->identity_count == 0) {
-		printf("No identity discovered\n");
-		return 0;
-	}
-
-	printf("Identity VDOs:\n");
-	for (i = 0; i < r->identity_count; i++)
-		printf("0x%08x\n", r->discovery_vdo[i]);
-
-	if (r->svid_count == 0) {
-		printf("No SVIDs discovered\n");
-		return 0;
-	}
-
-	for (i = 0; i < r->svid_count; i++) {
-		printf("SVID 0x%04x Modes:\n", r->svids[i].svid);
-		for (j = 0; j < r->svids[i].mode_count; j++)
-			printf("0x%08x\n", r->svids[i].mode_vdo[j]);
-	}
-
-	return 0;
-}
-
-/* Print shared fields of sink and source cap PDOs */
-static inline void print_pdo_fixed(uint32_t pdo)
-{
-	printf("    Fixed: %dmV %dmA %s%s%s%s",
-	       PDO_FIXED_VOLTAGE(pdo),
-	       PDO_FIXED_CURRENT(pdo),
-	       pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "",
-	       pdo & PDO_FIXED_UNCONSTRAINED ? "UP " : "",
-	       pdo & PDO_FIXED_COMM_CAP ? "USB " : "",
-	       pdo & PDO_FIXED_DATA_SWAP ? "DRD" : "");
-}
-
-static inline void print_pdo_battery(uint32_t pdo)
-{
-	printf("    Battery: max %dmV min %dmV max %dmW\n",
-	       PDO_BATT_MAX_VOLTAGE(pdo),
-	       PDO_BATT_MIN_VOLTAGE(pdo),
-	       PDO_BATT_MAX_POWER(pdo));
-}
-
-static inline void print_pdo_variable(uint32_t pdo)
-{
-	printf("    Variable: max %dmV min %dmV max %dmA\n",
-	       PDO_VAR_MAX_VOLTAGE(pdo),
-	       PDO_VAR_MIN_VOLTAGE(pdo),
-	       PDO_VAR_MAX_CURRENT(pdo));
-}
-
-static inline void print_pdo_augmented(uint32_t pdo)
-{
-	printf("    Augmented: max %dmV min %dmV max %dmA\n",
-	       PDO_AUG_MAX_VOLTAGE(pdo),
-	       PDO_AUG_MIN_VOLTAGE(pdo),
-	       PDO_AUG_MAX_CURRENT(pdo));
-}
-
-int cmd_typec_status(int argc, char *argv[])
-{
-	struct ec_params_typec_status p;
-	struct ec_response_typec_status *r =
-				(struct ec_response_typec_status *)ec_inbuf;
-	char *endptr;
-	int rv, i;
-	const char *desc;
-
-	if (argc != 2) {
-		fprintf(stderr,
-			"Usage: %s <port>\n"
-			"  <port> is the type-c port to query\n", argv[0]);
-		return -1;
-	}
-
-	p.port = strtol(argv[1], &endptr, 0);
-	if (endptr && *endptr) {
-		fprintf(stderr, "Bad port\n");
-		return -1;
-	}
-
-	rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
-	if (rv == -EC_RES_INVALID_COMMAND - EECRESULT)
-		/* Fall back to PD_CONTROL to support older ECs */
-		return cmd_usb_pd(argc, argv);
-	else if (rv < 0)
-		return -1;
-
-	printf("Port C%d: %s, %s  State:%s\n"
-	       "Role:%s %s%s, Polarity:CC%d\n",
-		p.port,
-		r->pd_enabled ? "enabled" : "disabled",
-		r->dev_connected ? "connected" : "disconnected",
-		r->tc_state,
-		(r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK",
-		(r->data_role == PD_ROLE_DFP) ? "DFP" :
-			(r->data_role == PD_ROLE_UFP) ? "UFP" : "",
-		(r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "",
-		(r->polarity % 2 + 1));
-
-	switch (r->cc_state) {
-	case PD_CC_NONE:
-		desc = "None";
-		break;
-	case PD_CC_UFP_AUDIO_ACC:
-		desc = "UFP Audio accessory";
-		break;
-	case PD_CC_UFP_DEBUG_ACC:
-		desc = "UFP Debug accessory";
-		break;
-	case PD_CC_UFP_ATTACHED:
-		desc = "UFP attached";
-		break;
-	case PD_CC_DFP_DEBUG_ACC:
-		desc = "DFP Debug accessory";
-		break;
-	case PD_CC_DFP_ATTACHED:
-		desc = "DFP attached";
-		break;
-	default:
-		desc = "UNKNOWN";
-		break;
-	}
-	printf("CC State: %s\n", desc);
-
-	if (r->dp_pin) {
-		switch (r->dp_pin) {
-		case MODE_DP_PIN_A:
-			desc = "A";
-			break;
-		case MODE_DP_PIN_B:
-			desc = "B";
-			break;
-		case MODE_DP_PIN_C:
-			desc = "C";
-			break;
-		case MODE_DP_PIN_D:
-			desc = "D";
-			break;
-		case MODE_DP_PIN_E:
-			desc = "E";
-			break;
-		case MODE_DP_PIN_F:
-			desc = "F";
-			break;
-		default:
-			desc = "UNKNOWN";
-			break;
-		}
-		printf("DP pin mode: %s\n", desc);
-	}
-
-	if (r->mux_state) {
-		printf("MUX: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d HPD_LVL=%d\n"
-		       "     SAFE=%d TBT=%d USB4=%d\n",
-		       !!(r->mux_state & USB_PD_MUX_USB_ENABLED),
-		       !!(r->mux_state & USB_PD_MUX_DP_ENABLED),
-			(r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
-						"INVERTED" : "NORMAL",
-		       !!(r->mux_state & USB_PD_MUX_HPD_IRQ),
-		       !!(r->mux_state & USB_PD_MUX_HPD_LVL),
-		       !!(r->mux_state & USB_PD_MUX_SAFE_MODE),
-		       !!(r->mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
-		       !!(r->mux_state & USB_PD_MUX_USB4_ENABLED));
-	}
-
-	printf("Port events: 0x%08x\n", r->events);
-
-	if (r->sop_revision)
-		printf("SOP  PD Rev: %d.%d\n",
-		       PD_STATUS_REV_GET_MAJOR(r->sop_revision),
-		       PD_STATUS_REV_GET_MINOR(r->sop_revision));
-
-	if (r->sop_prime_revision)
-		printf("SOP' PD Rev: %d.%d\n",
-		       PD_STATUS_REV_GET_MAJOR(r->sop_prime_revision),
-		       PD_STATUS_REV_GET_MINOR(r->sop_prime_revision));
-
-	for (i = 0; i < r->source_cap_count; i++) {
-		/*
-		 * Bits 31:30 always indicate the type of PDO
-		 *
-		 * Table 6-7 PD Rev 3.0 Ver 2.0
-		 */
-		uint32_t pdo = r->source_cap_pdos[i];
-		int pdo_type = pdo & PDO_TYPE_MASK;
-
-		if (i == 0)
-			printf("Source Capabilities:\n");
-
-		if (pdo_type == PDO_TYPE_FIXED) {
-			print_pdo_fixed(pdo);
-			printf("\n");
-		} else if (pdo_type == PDO_TYPE_BATTERY) {
-			print_pdo_battery(pdo);
-		} else if (pdo_type == PDO_TYPE_VARIABLE) {
-			print_pdo_variable(pdo);
-		} else {
-			print_pdo_augmented(pdo);
-		}
-	}
-
-	for (i = 0; i < r->sink_cap_count; i++) {
-		/*
-		 * Bits 31:30 always indicate the type of PDO
-		 *
-		 * Table 6-7 PD Rev 3.0 Ver 2.0
-		 */
-		uint32_t pdo = r->sink_cap_pdos[i];
-		int pdo_type = pdo & PDO_TYPE_MASK;
-
-		if (i == 0)
-			printf("Sink Capabilities:\n");
-
-		if (pdo_type == PDO_TYPE_FIXED) {
-			print_pdo_fixed(pdo);
-			/* Note: FRS bits are reserved in PD 2.0 spec */
-			printf("%s\n", pdo & PDO_FIXED_FRS_CURR_MASK ?
-			       "FRS" : "");
-		} else if (pdo_type == PDO_TYPE_BATTERY) {
-			print_pdo_battery(pdo);
-		} else if (pdo_type == PDO_TYPE_VARIABLE) {
-			print_pdo_variable(pdo);
-		} else {
-			print_pdo_augmented(pdo);
-		}
-	}
-
-	return 0;
-}
-
-int cmd_tp_self_test(int argc, char* argv[])
-{
-	int rv;
-
-	rv = ec_command(EC_CMD_TP_SELF_TEST, 0, NULL, 0, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	printf("Touchpad self test: %s\n",
-	       rv == EC_RES_SUCCESS ? "passed" : "failed");
-
-	return rv;
-}
-
-int cmd_tp_frame_get(int argc, char* argv[])
-{
-	int i, j;
-	uint32_t remaining = 0, offset = 0;
-	int rv = EC_SUCCESS;
-	uint8_t *data;
-	struct ec_response_tp_frame_info* r;
-	struct ec_params_tp_frame_get p;
-
-	data = (uint8_t *)(malloc(ec_max_insize));
-	r = (struct ec_response_tp_frame_info *)(malloc(ec_max_insize));
-
-	if (data == NULL || r == NULL) {
-		fprintf(stderr, "Couldn't allocate memory.\n");
-		free(r);
-		free(data);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	rv = ec_command(EC_CMD_TP_FRAME_INFO, 0, NULL, 0, r, ec_max_insize);
-	if (rv < 0) {
-		fprintf(stderr, "Failed to get touchpad frame info.\n");
-		goto err;
-	}
-
-	rv = ec_command(EC_CMD_TP_FRAME_SNAPSHOT, 0, NULL, 0, NULL, 0);
-	if (rv < 0) {
-		fprintf(stderr, "Failed to snapshot frame.\n");
-		goto err;
-	}
-
-	for (i = 0; i < r->n_frames; i++) {
-		p.frame_index = i;
-		offset = 0;
-		remaining = r->frame_sizes[i];
-
-		while (remaining > 0) {
-			p.offset = offset;
-			p.size = MIN(remaining, ec_max_insize);
-
-			rv = ec_command(EC_CMD_TP_FRAME_GET, 0,
-					&p, sizeof(p), data, p.size);
-			if (rv < 0) {
-				fprintf(stderr, "Failed to get frame data "
-						"at offset 0x%x\n", offset);
-				goto err;
-			}
-
-			for (j = 0; j < p.size; j++)
-				printf("%02x ", data[j]);
-
-			offset += p.size;
-			remaining -= p.size;
-		}
-		printf("\n");
-	}
-
-err:
-	free(data);
-	free(r);
-
-	return rv < 0;
-}
-
-int cmd_wait_event(int argc, char *argv[])
-{
-	int rv, i;
-	struct ec_response_get_next_event_v1 buffer;
-	long timeout = 5000;
-	long event_type;
-	char *e;
-
-	if (!ec_pollevent) {
-		fprintf(stderr, "Polling for MKBP event not supported\n");
-		return -EINVAL;
-	}
-
-	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <type> [<timeout>]\n",
-			argv[0]);
-		return -1;
-	}
-
-	event_type = strtol(argv[1], &e, 0);
-	if ((e && *e) || event_type < 0 || event_type >= EC_MKBP_EVENT_COUNT) {
-		fprintf(stderr, "Bad event type '%s'.\n", argv[1]);
-		return -1;
-	}
-	if (argc >= 3) {
-		timeout = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = wait_event(event_type, &buffer, sizeof(buffer), timeout);
-	if (rv < 0)
-		return rv;
-
-	printf("MKBP event %d data: ", buffer.event_type);
-	for (i = 0; i < rv - 1; ++i)
-		printf("%02x ", buffer.data.key_matrix[i]);
-	printf("\n");
-
-	return 0;
-}
-
-static void cmd_cec_help(const char *cmd)
-{
-	fprintf(stderr,
-		"  Usage: %s write [write bytes...]\n"
-		"    Write message on the CEC bus\n"
-		"  Usage: %s read [timeout]\n"
-		"    [timeout] in seconds\n"
-		"  Usage: %s get <param>\n"
-		"  Usage: %s set <param> <val>\n"
-		"    <param> is one of:\n"
-		"      address: CEC receive address\n"
-		"        <val> is the new CEC address\n"
-		"      enable: Enable or disable CEC\n"
-		"        <val> is 1 to enable, 0 to disable\n",
-		cmd, cmd, cmd, cmd);
-
-}
-
-static int cmd_cec_write(int argc, char *argv[])
-{
-	char *e;
-	long val;
-	int rv, i, msg_len;
-	struct ec_params_cec_write p;
-	struct ec_response_get_next_event_v1 buffer;
-
-	if (argc < 3 || argc > 18) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	msg_len = argc - 2;
-	for (i = 0; i < msg_len; i++) {
-		val = strtol(argv[i + 2], &e, 16);
-		if (e && *e)
-			return -1;
-		if (val < 0 || val > 0xff)
-			return -1;
-		p.msg[i] = (uint8_t)val;
-	}
-
-	printf("Write to CEC: ");
-	for (i = 0; i < msg_len; i++)
-		printf("0x%02x ", p.msg[i]);
-	printf("\n");
-
-	rv = ec_command(EC_CMD_CEC_WRITE_MSG, 0, &p, msg_len, NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	rv = wait_event(EC_MKBP_EVENT_CEC_EVENT, &buffer, sizeof(buffer), 1000);
-	if (rv < 0)
-		return rv;
-
-	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_OK)
-		return 0;
-
-	if (buffer.data.cec_events & EC_MKBP_CEC_SEND_FAILED) {
-		fprintf(stderr, "Send failed\n");
-		return -1;
-	}
-
-	fprintf(stderr, "No send result received\n");
-
-	return -1;
-}
-
-static int cmd_cec_read(int argc, char *argv[])
-{
-	int i, rv;
-	char *e;
-	struct ec_response_get_next_event_v1 buffer;
-	long timeout = 5000;
-
-	if (!ec_pollevent) {
-		fprintf(stderr, "Polling for MKBP event not supported\n");
-		return -EINVAL;
-	}
-
-	if (argc >= 3) {
-		timeout = strtol(argv[2], &e, 0);
-		if (e && *e) {
-			fprintf(stderr, "Bad timeout value '%s'.\n", argv[2]);
-			return -1;
-		}
-	}
-
-	rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer,
-			sizeof(buffer), timeout);
-	if (rv < 0)
-		return rv;
-
-	printf("CEC data: ");
-	for (i = 0; i < rv - 1; i++)
-		printf("0x%02x ", buffer.data.cec_message[i]);
-	printf("\n");
-
-	return 0;
-}
-
-static int cec_cmd_from_str(const char *str)
-{
-	if (!strcmp("address", str))
-		return CEC_CMD_LOGICAL_ADDRESS;
-	if (!strcmp("enable", str))
-		return CEC_CMD_ENABLE;
-	return -1;
-}
-
-static int cmd_cec_set(int argc, char *argv[])
-{
-	char *e;
-	struct ec_params_cec_set p;
-	uint8_t val;
-	int cmd;
-
-	if (argc != 4) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	val = (uint8_t)strtol(argv[3], &e, 0);
-	if (e && *e) {
-		fprintf(stderr, "Bad parameter '%s'.\n", argv[3]);
-		return -1;
-	}
-
-	cmd = cec_cmd_from_str(argv[2]);
-	if (cmd < 0) {
-		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
-		return -1;
-	}
-	p.cmd = cmd;
-	p.val = val;
-
-	return ec_command(EC_CMD_CEC_SET,
-			  0, &p, sizeof(p), NULL, 0);
-}
-
-
-static int cmd_cec_get(int argc, char *argv[])
-{
-	int rv, cmd;
-	struct ec_params_cec_get p;
-	struct ec_response_cec_get r;
-
-
-	if (argc != 3) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-
-	cmd = cec_cmd_from_str(argv[2]);
-	if (cmd < 0) {
-		fprintf(stderr, "Invalid command '%s'.\n", argv[2]);
-		return -1;
-	}
-	p.cmd = cmd;
-
-
-	rv = ec_command(EC_CMD_CEC_GET, 0, &p, sizeof(p), &r, sizeof(r));
-	if (rv < 0)
-		return rv;
-
-	printf("%d\n", r.val);
-
-	return 0;
-}
-
-int cmd_cec(int argc, char *argv[])
-{
-	if (argc < 2) {
-		fprintf(stderr, "Invalid number of params\n");
-		cmd_cec_help(argv[0]);
-		return -1;
-	}
-	if (!strcmp(argv[1], "write"))
-		return cmd_cec_write(argc, argv);
-	if (!strcmp(argv[1], "read"))
-		return cmd_cec_read(argc, argv);
-	if (!strcmp(argv[1], "get"))
-		return cmd_cec_get(argc, argv);
-	if (!strcmp(argv[1], "set"))
-		return cmd_cec_set(argc, argv);
-
-	fprintf(stderr, "Invalid sub command: %s\n", argv[1]);
-	cmd_cec_help(argv[0]);
-
-	return -1;
-}
-
-/* NULL-terminated list of commands */
-const struct command commands[] = {
-	{"adcread", cmd_adc_read},
-	{"addentropy", cmd_add_entropy},
-	{"apreset", cmd_apreset},
-	{"autofanctrl", cmd_thermal_auto_fan_ctrl},
-	{"backlight", cmd_lcd_backlight},
-	{"basestate", cmd_basestate},
-	{"battery", cmd_battery},
-	{"batterycutoff", cmd_battery_cut_off},
-	{"batteryparam", cmd_battery_vendor_param},
-	{"boardversion", cmd_board_version},
-	{"button", cmd_button},
-	{"cbi", cmd_cbi},
-	{"chargecurrentlimit", cmd_charge_current_limit},
-	{"chargecontrol", cmd_charge_control},
-	{"chargeoverride", cmd_charge_port_override},
-	{"chargestate", cmd_charge_state},
-	{"chipinfo", cmd_chipinfo},
-	{"cmdversions", cmd_cmdversions},
-	{"console", cmd_console},
-	{"cec", cmd_cec},
-	{"echash", cmd_ec_hash},
-	{"eventclear", cmd_host_event_clear},
-	{"eventclearb", cmd_host_event_clear_b},
-	{"eventget", cmd_host_event_get_raw},
-	{"eventgetb", cmd_host_event_get_b},
-	{"eventgetscimask", cmd_host_event_get_sci_mask},
-	{"eventgetsmimask", cmd_host_event_get_smi_mask},
-	{"eventgetwakemask", cmd_host_event_get_wake_mask},
-	{"eventsetscimask", cmd_host_event_set_sci_mask},
-	{"eventsetsmimask", cmd_host_event_set_smi_mask},
-	{"eventsetwakemask", cmd_host_event_set_wake_mask},
-	{"extpwrlimit", cmd_ext_power_limit},
-	{"fanduty", cmd_fanduty},
-	{"flasherase", cmd_flash_erase},
-	{"flasheraseasync", cmd_flash_erase},
-	{"flashprotect", cmd_flash_protect},
-	{"flashread", cmd_flash_read},
-	{"flashwrite", cmd_flash_write},
-	{"flashinfo", cmd_flash_info},
-	{"flashspiinfo", cmd_flash_spi_info},
-	{"flashpd", cmd_flash_pd},
-	{"forcelidopen", cmd_force_lid_open},
-	{"fpcontext", cmd_fp_context},
-	{"fpencstatus", cmd_fp_enc_status},
-	{"fpframe", cmd_fp_frame},
-	{"fpinfo", cmd_fp_info},
-	{"fpmode", cmd_fp_mode},
-	{"fpseed", cmd_fp_seed},
-	{"fpstats", cmd_fp_stats},
-	{"fptemplate", cmd_fp_template},
-	{"gpioget", cmd_gpio_get},
-	{"gpioset", cmd_gpio_set},
-	{"hangdetect", cmd_hang_detect},
-	{"hello", cmd_hello},
-	{"hibdelay", cmd_hibdelay},
-	{"hostevent", cmd_hostevent},
-	{"hostsleepstate", cmd_hostsleepstate},
-	{"locatechip", cmd_locate_chip},
-	{"i2cprotect", cmd_i2c_protect},
-	{"i2cread", cmd_i2c_read},
-	{"i2cwrite", cmd_i2c_write},
-	{"i2cxfer", cmd_i2c_xfer},
-	{"infopddev", cmd_pd_device_info},
-	{"inventory", cmd_inventory},
-	{"led", cmd_led},
-	{"lightbar", cmd_lightbar},
-	{"kbfactorytest", cmd_keyboard_factory_test},
-	{"kbid", cmd_kbid},
-	{"kbinfo", cmd_kbinfo},
-	{"kbpress", cmd_kbpress},
-	{"keyconfig", cmd_keyconfig},
-	{"keyscan", cmd_keyscan},
-	{"mkbpget", cmd_mkbp_get},
-	{"mkbpwakemask", cmd_mkbp_wake_mask},
-	{"motionsense", cmd_motionsense},
-	{"nextevent", cmd_next_event},
-	{"panicinfo", cmd_panic_info},
-	{"pause_in_s5", cmd_s5},
-	{"pchg", cmd_pchg},
-	{"pdgetmode", cmd_pd_get_amode},
-	{"pdsetmode", cmd_pd_set_amode},
-	{"port80read", cmd_port80_read},
-	{"pdlog", cmd_pd_log},
-	{"pdcontrol", cmd_pd_control},
-	{"pdchipinfo", cmd_pd_chip_info},
-	{"pdwritelog", cmd_pd_write_log},
-	{"powerinfo", cmd_power_info},
-	{"protoinfo", cmd_proto_info},
-	{"pse", cmd_pse},
-	{"pstoreinfo", cmd_pstore_info},
-	{"pstoreread", cmd_pstore_read},
-	{"pstorewrite", cmd_pstore_write},
-	{"pwmgetfanrpm", cmd_pwm_get_fan_rpm},
-	{"pwmgetkblight", cmd_pwm_get_keyboard_backlight},
-	{"pwmgetnumfans", cmd_pwm_get_num_fans},
-	{"pwmgetduty", cmd_pwm_get_duty},
-	{"pwmsetfanrpm", cmd_pwm_set_fan_rpm},
-	{"pwmsetkblight", cmd_pwm_set_keyboard_backlight},
-	{"pwmsetduty", cmd_pwm_set_duty},
-	{"rand", cmd_rand},
-	{"readtest", cmd_read_test},
-	{"reboot_ec", cmd_reboot_ec},
-	{"rollbackinfo", cmd_rollback_info},
-	{"rtcget", cmd_rtc_get},
-	{"rtcgetalarm", cmd_rtc_get_alarm},
-	{"rtcset", cmd_rtc_set},
-	{"rtcsetalarm", cmd_rtc_set_alarm},
-	{"rwhashpd", cmd_rw_hash_pd},
-	{"rwsig", cmd_rwsig},
-	{"rwsigaction", cmd_rwsig_action_legacy},
-	{"rwsigstatus", cmd_rwsig_status},
-	{"sertest", cmd_serial_test},
-	{"smartdischarge", cmd_smart_discharge},
-	{"stress", cmd_stress_test},
-	{"sysinfo", cmd_sysinfo},
-	{"port80flood", cmd_port_80_flood},
-	{"switches", cmd_switches},
-	{"temps", cmd_temperature},
-	{"tempsinfo", cmd_temp_sensor_info},
-	{"test", cmd_test},
-	{"thermalget", cmd_thermal_get_threshold},
-	{"thermalset", cmd_thermal_set_threshold},
-	{"tpselftest", cmd_tp_self_test},
-	{"tpframeget", cmd_tp_frame_get},
-	{"tmp006cal", cmd_tmp006cal},
-	{"tmp006raw", cmd_tmp006raw},
-	{"typeccontrol", cmd_typec_control},
-	{"typecdiscovery", cmd_typec_discovery},
-	{"typecstatus", cmd_typec_status},
-	{"uptimeinfo", cmd_uptimeinfo},
-	{"usbchargemode", cmd_usb_charge_set_mode},
-	{"usbmux", cmd_usb_mux},
-	{"usbpd", cmd_usb_pd},
-	{"usbpdmuxinfo", cmd_usb_pd_mux_info},
-	{"usbpdpower", cmd_usb_pd_power},
-	{"version", cmd_version},
-	{"waitevent", cmd_wait_event},
-	{"wireless", cmd_wireless},
-	{"reboot_ap_on_g3", cmd_reboot_ap_on_g3},
-	{NULL, NULL}
-};
-
-int main(int argc, char *argv[])
-{
-	const struct command *cmd;
-	int dev = 0;
-	int interfaces = COMM_ALL;
-	int i2c_bus = -1;
-	char device_name[41] = CROS_EC_DEV_NAME;
-	int rv = 1;
-	int parse_error = 0;
-	char *e;
-	int i;
-
-	BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
-
-	while ((i = getopt_long(argc, argv, "?", long_opts, NULL)) != -1) {
-		switch (i) {
-		case '?':
-			/* Unhandled option */
-			parse_error = 1;
-			break;
-
-		case OPT_DEV:
-			dev = strtoull(optarg, &e, 0);
-			if (!*optarg || (e && *e)) {
-				fprintf(stderr, "Invalid --dev\n");
-				parse_error = 1;
-			}
-			break;
-
-		case OPT_INTERFACE:
-			if (!strcasecmp(optarg, "dev")) {
-				interfaces = COMM_DEV;
-			} else if (!strcasecmp(optarg, "lpc")) {
-				interfaces = COMM_LPC;
-			} else if (!strcasecmp(optarg, "i2c")) {
-				interfaces = COMM_I2C;
-			} else if (!strcasecmp(optarg, "servo")) {
-				interfaces = COMM_SERVO;
-			} else {
-				fprintf(stderr, "Invalid --interface\n");
-				parse_error = 1;
-			}
-			break;
-		case OPT_NAME:
-			strncpy(device_name, optarg, 40);
-			device_name[40] = '\0';
-			break;
-		case OPT_I2C_BUS:
-			i2c_bus = strtoull(optarg, &e, 0);
-			if (*optarg == '\0' || (e && *e != '\0')
-			    || i2c_bus < 0) {
-				fprintf(stderr, "Invalid --i2c_bus\n");
-				parse_error = 1;
-			}
-			break;
-		case OPT_ASCII:
-			ascii_mode = 1;
-			break;
-		}
-	}
-
-	if (i2c_bus != -1)  {
-		if (!(interfaces & COMM_I2C)) {
-			fprintf(stderr, "--i2c_bus is specified, but --interface is set to something other than I2C\n");
-			parse_error = 1;
-		} else {
-			interfaces = COMM_I2C;
-		}
-	}
-
-	/* Must specify a command */
-	if (!parse_error && optind == argc)
-		parse_error = 1;
-
-	/* 'ectool help' prints help with commands */
-	if (!parse_error && !strcasecmp(argv[optind], "help")) {
-		print_help(argv[0], 1);
-		exit(1);
-	}
-
-	/* Handle sub-devices command offset */
-	if (dev > 0 && dev < 4) {
-		set_command_offset(EC_CMD_PASSTHRU_OFFSET(dev));
-	} else if (dev == 8) {
-		/* Special offset for Fingerprint MCU */
-		strcpy(device_name, "cros_fp");
-	} else if (dev != 0) {
-		fprintf(stderr, "Bad device number %d\n", dev);
-		parse_error = 1;
-	}
-
-	if (parse_error) {
-		print_help(argv[0], 0);
-		exit(1);
-	}
-
-	/* Prefer /dev method, which supports built-in mutex */
-	if (!(interfaces & COMM_DEV) || comm_init_dev(device_name)) {
-		/* If dev is excluded or isn't supported, find alternative */
-		if (acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) {
-			fprintf(stderr, "Could not acquire GEC lock.\n");
-			exit(1);
-		}
-		if (comm_init_alt(interfaces, device_name, i2c_bus)) {
-			fprintf(stderr, "Couldn't find EC\n");
-			goto out;
-		}
-	}
-
-	if (comm_init_buffer()) {
-		fprintf(stderr, "Couldn't initialize buffers\n");
-		goto out;
-	}
-
-	/* Handle commands */
-	for (cmd = commands; cmd->name; cmd++) {
-		if (!strcasecmp(argv[optind], cmd->name)) {
-			rv = cmd->handler(argc - optind, argv + optind);
-			goto out;
-		}
-	}
-
-	/* If we're still here, command was unknown */
-	fprintf(stderr, "Unknown command '%s'\n\n", argv[optind]);
-	print_help(argv[0], 0);
-
-out:
-	release_gec_lock();
-	return !!rv;
-}
diff --git a/util/ectool.h b/util/ectool.h
deleted file mode 100644
index c47edbf27c..0000000000
--- a/util/ectool.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/** @brief A handler for an `ectool` command.  */
-struct command {
-	/** The name of the command. */
-	const char *name;
-
-	/**
-	 * The function to handle the command.
-	 *
-	 * @param argc The length of `argv`
-	 * @param argv The arguments passed, including the command itself but
-	 *             not 'ectool'.
-	 * @return 0 if successful, or a negative `enum ec_status` value.
-	 */
-	int (*handler)(int argc, char *argv[]);
-};
-
-/**
- * Test low-level key scanning
- *
- * ectool keyscan <beat_us> <filename>
- *
- * <beat_us> is the length of a beat in microseconds. This indicates the
- * typing speed. Typically we scan at 10ms in the EC, so the beat period
- * will typically be 1-5ms, with the scan changing only every 20-30ms at
- * most.
- * <filename> specifies a file containing keys that are depressed on each
- * beat in the following format:
- *
- *   <beat> <keys_pressed>
- *
- * <beat> is a beat number (0, 1, 2). The timestamp of this event will
- * be <start_time> + <beat> * <beat_us>.
- * <keys_pressed> is a (possibly empty) list of ASCII keys
- *
- * The key matrix is read from the fdt.
- */
-int cmd_keyscan(int argc, char *argv[]);
diff --git a/util/ectool_keyscan.c b/util/ectool_keyscan.c
deleted file mode 100644
index 4f5393157d..0000000000
--- a/util/ectool_keyscan.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <termios.h>
-#include <unistd.h>
-#include <sys/stat.h>
-#include <endian.h>
-
-#include "comm-host.h"
-#include "keyboard_config.h"
-#include "ectool.h"
-
-enum {
-	/* Alloc this many more scans when needed */
-	KEYSCAN_ALLOC_STEP	= 64,
-	KEYSCAN_MAX_TESTS	= 10,	/* Maximum number of tests supported */
-	KEYSCAN_MAX_INPUT_LEN	= 20,	/* Maximum characters we can receive */
-};
-
-/* A single entry of the key matrix */
-struct matrix_entry {
-	int row;	/* key matrix row */
-	int col;	/* key matrix column */
-	int keycode;	/* corresponding linux key code */
-};
-
-struct keyscan_test_item {
-	uint32_t beat;			/* Beat number */
-	uint8_t scan[KEYBOARD_COLS_MAX];	/* Scan data */
-};
-
-/* A single test, consisting of a list of key scans and expected ascii input */
-struct keyscan_test {
-	char *name;		/* name of test */
-	char *expect;		/* resulting input we expect to see */
-	int item_count;		/* number of items in data */
-	int item_alloced;	/* number of items alloced in data */
-	struct keyscan_test_item *items;	/* key data for EC */
-};
-
-/* A list of tests that we can run */
-struct keyscan_info {
-	unsigned int beat_us;	/* length of each beat in microseconds */
-	struct keyscan_test tests[KEYSCAN_MAX_TESTS];	/* the tests */
-	int test_count;		/* number of tests */
-	struct matrix_entry *matrix;	/* the key matrix info */
-	int matrix_count;	/* number of keys in matrix */
-};
-
-/**
- * Read the key matrix from the device tree
- *
- * Keymap entries in the fdt take the form of 0xRRCCKKKK where
- * RR=Row CC=Column KKKK=Key Code
- *
- * @param keyscan	keyscan information
- * @param path		path to device tree file containing data
- * @return 0 if ok, -1 on error
- */
-static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan,
-				   const char *path)
-{
-	struct stat buf;
-	uint32_t word;
-	int upto;
-	FILE *f;
-	int err;
-
-	/* Allocate memory for key matrix */
-	if (stat(path, &buf)) {
-		fprintf(stderr, "Cannot stat key matrix file '%s'\n", path);
-		return -1;
-	}
-	keyscan->matrix_count = buf.st_size / 4;
-	keyscan->matrix = (struct matrix_entry *)(calloc(
-		keyscan->matrix_count, sizeof(*keyscan->matrix)));
-	if (!keyscan->matrix) {
-		fprintf(stderr, "Out of memory for key matrix\n");
-		return -1;
-	}
-
-	f = fopen(path, "rb");
-	if (!f) {
-		fprintf(stderr, "Cannot open key matrix file '%s'\n", path);
-		return -1;
-	}
-
-	/* Now read the data */
-	upto = err = 0;
-	while (fread(&word, 1, sizeof(word), f) == sizeof(word)) {
-		struct matrix_entry *matrix = &keyscan->matrix[upto++];
-
-		word = be32toh(word);
-		matrix->row = word >> 24;
-		matrix->col = (word >> 16) & 0xff;
-		matrix->keycode = word & 0xffff;
-
-		/* Hard-code some limits for now */
-		if (matrix->row >= KEYBOARD_ROWS ||
-		    matrix->col >= KEYBOARD_COLS_MAX) {
-			fprintf(stderr, "Matrix pos out of range (%d,%d)\n",
-				matrix->row, matrix->col);
-			fclose(f);
-			return -1;
-		}
-	}
-	fclose(f);
-	if (!err && upto != keyscan->matrix_count) {
-		fprintf(stderr, "Read mismatch from matrix file '%s'\n", path);
-		err = -1;
-	}
-
-	return err;
-}
-
-/*
- * translate Linux's KEY_... values into ascii. We change space into 0xfe
- * since we use the numeric value (&32) for space. That avoids ambiguity
- * when we see a space in a key sequence file.
- */
-static const unsigned char kbd_plain_xlate[] = {
-	0xff, 0x1b, '1',  '2',  '3',  '4',  '5',  '6',
-	'7',  '8',  '9',  '0',  '-',  '=', '\b', '\t',	/* 0x00 - 0x0f */
-	'q',  'w',  'e',  'r',  't',  'y',  'u',  'i',
-	'o',  'p',  '[',  ']', '\r', 0xff,  'a',  's',  /* 0x10 - 0x1f */
-	'd',  'f',  'g',  'h',  'j',  'k',  'l',  ';',
-	'\'',  '`', 0xff, '\\', 'z',  'x',  'c',  'v',	/* 0x20 - 0x2f */
-	'b',  'n',  'm',  ',' ,  '.', '/', 0xff, 0xff, 0xff,
-	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  '7',
-	'8',  '9',  '-',  '4',  '5',  '6',  '+',  '1',	/* 0x40 - 0x4f */
-	'2',  '3',  '0',  '.', 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
-	'\r', 0xff, 0xff, '\0'
-};
-
-/**
- * Add a new key to a scan
- *
- * Given a new key, this looks it up in the matrix and adds it to the scan,
- * so that if this scan were reported by the EC, the AP would the given key.
- *
- * The format of keys is a list of ascii characters, or & followed by a numeric
- * ascii value, or * followed by a numeric keycode value. Spaces are ignored
- * (use '*32' for space).
- *
- * Examples:
- * a        - a
- * &20      - space
- * *58      - KEY_CAPSLOCK
- *
- * @param keyscan	keyscan information
- * @param keysp		point to the current key string on entry; on exit it
- *			is updated to point to just after the string, plus any
- *			following space
- * @param path		path to device tree file containing data
- * @return 0 if ok, -1 on error
- */
-static int keyscan_add_to_scan(struct keyscan_info *keyscan, char **keysp,
-			       uint8_t scan[])
-{
-	const uint8_t *pos;
-	struct matrix_entry *matrix;
-	int keycode = -1, i;
-	char *keys = *keysp;
-	int key = ' ';
-
-	if (*keys == '&') {
-		/* Numeric ascii code */
-		keys++;
-		key = strtol(keys, &keys, 10);
-		if (!key || keys == *keysp) {
-			fprintf(stderr, "Invalid numeric ascii\n");
-			return -1;
-		}
-		if (*keys == ' ')
-			keys++;
-		else if (*keys) {
-			fprintf(stderr, "Expect space after numeric ascii\n");
-			return -1;
-		}
-	} else if (*keys == '*') {
-		/* Numeric ascii code */
-		keys++;
-		keycode = strtol(keys, &keys, 10);
-		if (!keycode || keys == *keysp) {
-			fprintf(stderr, "Invalid numeric keycode\n");
-			return -1;
-		}
-		if (*keys == ' ')
-			keys++;
-		else if (*keys) {
-			fprintf(stderr, "Expect space after num. keycode\n");
-			return -1;
-		}
-	} else {
-		key = *keys++;
-	}
-
-	/* Convert keycode to key if needed */
-	if (keycode == -1) {
-		pos = (uint8_t *)(strchr((char *)kbd_plain_xlate, key));
-		if (!pos) {
-			fprintf(stderr, "Key '%c' not found in xlate table\n",
-				key);
-			return -1;
-		}
-		keycode = pos - kbd_plain_xlate;
-	}
-
-	/* Look up keycode in matrix */
-	for (i = 0, matrix = keyscan->matrix; i < keyscan->matrix_count;
-			i++, matrix++) {
-		if (matrix->keycode == keycode) {
-#ifdef DEBUG
-			printf("%d: %d,%d\n", matrix->keycode, matrix->row,
-			       matrix->col);
-#endif
-			scan[matrix->col] |= 1 << matrix->row;
-			*keysp = keys;
-			return 0;
-		}
-	}
-	fprintf(stderr, "Key '%c' (keycode %d) not found in matrix\n", key,
-		keycode);
-
-	return -1;
-}
-
-/**
- * Add a new keyscan to the given test
- *
- * This processes a new keyscan, consisting of a beat number and a sequence
- * of keys.
- *
- * The format of keys is a beat number followed by a list of keys, each
- * either ascii characters, or & followed by a numeric ascii value, or *
- * followed by a numeric keycode value. Spaces are ignored (use '*32' for
- * space).
- *
- * Examples:
- * 0 abc      - beat 0, press a, b and c
- * 4 a &20    - beat 4, press a and space
- * 8 *58 &13  - beat 8, press KEY_CAPSLOCK
- *
- * @param keyscan	keyscan information
- * @param linenum	line number we are reading from (for error reporting)
- * @param test		test to add this scan to
- * @param keys		key string to process
- * @return 0 if ok, -1 on error
- */
-static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum,
-				struct keyscan_test *test, char *keys)
-{
-	struct keyscan_test_item *item;
-	unsigned long int beat;
-
-	/* Allocate more items if needed */
-	if (!test->item_alloced || test->item_count == test->item_alloced) {
-		int size, new_size;
-
-		size = test->item_alloced * sizeof(struct keyscan_test_item);
-		new_size = size + KEYSCAN_ALLOC_STEP *
-					  sizeof(struct keyscan_test_item);
-		test->items = (struct keyscan_test_item *)(realloc(test->items,
-								   new_size));
-		if (!test->items) {
-			fprintf(stderr, "Out of memory realloc()\n");
-			return -1;
-		}
-		memset((char *)test->items + size, '\0', new_size - size);
-		test->item_alloced += KEYSCAN_ALLOC_STEP;
-		new_size = size;
-	}
-
-	/* read the beat number */
-	item = &test->items[test->item_count];
-	beat = strtol(keys, &keys, 10);
-	item->beat = beat;
-
-	/* Read keys and add them to our scan */
-	if (*keys == ' ') {
-		keys++;
-		while (*keys) {
-			if (keyscan_add_to_scan(keyscan, &keys, item->scan)) {
-				fprintf(stderr, "Line %d: Cannot parse"
-					" key input '%s'\n", linenum,
-					keys);
-				return -1;
-			}
-		}
-	} else if (*keys) {
-		fprintf(stderr, "Line %d: Need space after beat\n",
-			linenum);
-		return -1;
-	}
-	test->item_count++;
-
-	return 0;
-}
-
-/* These are the commands we understand in a key sequence file */
-enum keyscan_cmd {
-	KEYSCAN_CMD_TEST,	/* start a new test */
-	KEYSCAN_CMD_ENDTEST,	/* end a test */
-	KEYSCAN_CMD_SEQ,	/* add a keyscan to a test sequence */
-	KEYSCAN_CMD_EXPECT,	/* indicate what input is expected */
-
-	KEYSCAN_CMD_COUNT
-};
-
-/* Names for each of the keyscan commands */
-static const char *keyscan_cmd_name[KEYSCAN_CMD_COUNT] = {
-	"test",
-	"endtest",
-	"seq",
-	"expect",
-};
-
-/**
- * Read a command from a string and return it
- *
- * @param str	String containing command
- * @param len	Length of command string
- * @return detected command, or -1 if none
- */
-static enum keyscan_cmd keyscan_read_cmd(const char *str, int len)
-{
-	int i;
-
-	for (i = 0; i < KEYSCAN_CMD_COUNT; i++) {
-		if (!strncmp(keyscan_cmd_name[i], str, len))
-			return (enum keyscan_cmd)(i);
-	}
-
-	return (enum keyscan_cmd)(-1);
-}
-
-/**
- * Process a key sequence file a build up a list of tets from it
- *
- * @param f		File containing keyscan info
- * @param keyscan	keyscan information
- * @return 0 if ok, -1 on error
- */
-static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
-{
-	struct keyscan_test *cur_test;
-	char line[256];
-	char *str;
-	int linenum;
-
-	keyscan->test_count = 0;
-
-	linenum = 0;
-	cur_test = NULL;
-	while (str = fgets(line, sizeof(line), f), str) {
-		char *args, *end;
-		int cmd, len;
-
-		linenum++;
-		len = strlen(str);
-
-		/* chomp the trailing newline */
-		if (len > 0 && str[len - 1] == '\n') {
-			len--;
-			str[len] = '\0';
-		}
-
-		/* deal with blank lines and comments */
-		if (!len || *str == '#')
-			continue;
-
-		/* get the command */
-		for (end = str; *end && *end != ' '; end++)
-			;
-
-		cmd = keyscan_read_cmd(str, end - str);
-		args = end + (*end != '\0');
-		switch (cmd) {
-		case KEYSCAN_CMD_TEST:
-			/* Start a new test */
-			if (keyscan->test_count == KEYSCAN_MAX_TESTS) {
-				fprintf(stderr, "KEYSCAN_MAX_TESTS "
-					"exceeded\n");
-				return -1;
-			}
-			cur_test = &keyscan->tests[keyscan->test_count];
-			cur_test->name = strdup(args);
-			if (!cur_test->name) {
-				fprintf(stderr, "Line %d: out of memory\n",
-					linenum);
-			}
-			break;
-		case KEYSCAN_CMD_EXPECT:
-			/* Get expect string */
-			if (!cur_test) {
-				fprintf(stderr, "Line %d: expect should be "
-					"inside test\n", linenum);
-				return -1;
-			}
-			cur_test->expect = strdup(args);
-			if (!cur_test->expect) {
-				fprintf(stderr, "Line %d: out of memory\n",
-					linenum);
-			}
-			break;
-		case KEYSCAN_CMD_ENDTEST:
-			/* End of a test */
-			keyscan->test_count++;
-			cur_test = NULL;
-			break;
-		case KEYSCAN_CMD_SEQ:
-			if (keyscan_process_keys(keyscan, linenum, cur_test,
-					args)) {
-				fprintf(stderr, "Line %d: Cannot parse key "
-					"input '%s'\n", linenum, args);
-				return -1;
-			}
-			break;
-		default:
-			fprintf(stderr, "Line %d: Uknown command '%1.*s'\n",
-				linenum, (int)(end - str), str);
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-/**
- * Print out a list of all tests
- *
- * @param keyscan	keyscan information
- */
-static void keyscan_print(struct keyscan_info *keyscan)
-{
-	int testnum;
-	int i;
-
-	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
-		struct keyscan_test *test = &keyscan->tests[testnum];
-
-		printf("Test: %s\n", test->name);
-		for (i = 0; i < test->item_count; i++) {
-			struct keyscan_test_item *item;
-			int j;
-
-			item = &test->items[i];
-			printf("%2d  %7d:  ", i, item->beat);
-			for (j = 0; j < sizeof(item->scan); j++)
-				printf("%02x ", item->scan[j]);
-			printf("\n");
-		}
-		printf("\n");
-	}
-}
-
-/**
- * Set the terminal to raw mode, or cooked
- *
- * @param tty_fd	Terminal file descriptor to change
- * @Param raw		0 for cooked, non-zero for raw
- */
-static void set_to_raw(int tty_fd, int raw)
-{
-	struct termios tty_attr;
-	int value;
-
-	value = fcntl(tty_fd, F_GETFL);
-
-	tcgetattr(tty_fd, &tty_attr);
-	if (raw) {
-		tty_attr.c_lflag &= ~ICANON;
-		value |= O_NONBLOCK;
-	} else {
-		tty_attr.c_lflag |= ICANON;
-		value &= ~O_NONBLOCK;
-	}
-	tcsetattr(tty_fd, TCSANOW, &tty_attr);
-	fcntl(tty_fd, F_SETFL, value);
-}
-
-/**
- * Read input for a whlie until wee see no more
- *
- * @param fd		File descriptor for input
- * @param input		Place to put input string
- * @param max_len	Maximum length of input string
- * @param wait		Number of microseconds to wait for input
- */
-static void keyscan_get_input(int fd, char *input, int max_len, int wait)
-{
-	int len;
-
-	usleep(wait);
-	input[0] = '\0';
-	len = read(fd, input, max_len - 1);
-	if (len > 0)
-		input[len] = '\0';
-}
-
-static int keyscan_send_sequence(struct keyscan_info *keyscan,
-				 struct keyscan_test *test)
-{
-	struct ec_params_keyscan_seq_ctrl *req;
-	struct keyscan_test_item *item;
-	int upto, size, rv;
-
-	size = sizeof(*req) + sizeof(item->scan);
-	req = (struct ec_params_keyscan_seq_ctrl *)malloc(size);
-	if (!req) {
-		fprintf(stderr, "Out of memory for message\n");
-		return -1;
-	}
-	for (upto = rv = 0, item = test->items; rv >= 0 &&
-			upto < test->item_count; upto++, item++) {
-		req->cmd = EC_KEYSCAN_SEQ_ADD;
-		req->add.time_us = item->beat * keyscan->beat_us;
-		memcpy(req->add.scan, item->scan, sizeof(item->scan));
-		rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, req, size, NULL, 0);
-	}
-	free(req);
-	if (rv < 0)
-		return rv;
-
-	return 0;
-}
-
-/**
- * Run a single test
- *
- * @param keyscan	keyscan information
- * @param test		test to run
- * @return 0 if test passes, -ve if some error occurred
- */
-static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
-{
-	struct ec_params_keyscan_seq_ctrl ctrl;
-	char input[KEYSCAN_MAX_INPUT_LEN];
-	struct ec_result_keyscan_seq_ctrl *resp;
-	int wait_us;
-	int size;
-	int rv;
-	int fd = 0;
-	int i;
-
-	/* First clear the sequence */
-	ctrl.cmd = EC_KEYSCAN_SEQ_CLEAR;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	rv = keyscan_send_sequence(keyscan, test);
-	if (rv < 0)
-		return rv;
-
-	/* Start it */
-	set_to_raw(fd, 1);
-	ctrl.cmd = EC_KEYSCAN_SEQ_START;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
-	if (rv < 0)
-		return rv;
-
-	/* Work out how long we need to wait */
-	wait_us = 100 * 1000;	/* Wait 100ms to at least */
-	if (test->item_count) {
-		struct keyscan_test_item *ksi;
-
-		ksi = &test->items[test->item_count - 1];
-		wait_us += ksi->beat * keyscan->beat_us;
-	}
-
-	/* Wait for input */
-	keyscan_get_input(fd, input, sizeof(input), wait_us);
-	set_to_raw(fd, 0);
-
-	/* Ask EC for results */
-	size = sizeof(*resp) + test->item_count;
-	resp = (struct ec_result_keyscan_seq_ctrl *)(malloc(size));
-	if (!resp) {
-		fprintf(stderr, "Out of memory for results\n");
-		return -1;
-	}
-	ctrl.cmd = EC_KEYSCAN_SEQ_COLLECT;
-	ctrl.collect.start_item = 0;
-	ctrl.collect.num_items = test->item_count;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			resp, size);
-	if (rv < 0)
-		return rv;
-
-	/* Check what scans were skipped */
-	for (i = 0; i < resp->collect.num_items; i++) {
-		struct ec_collect_item *item;
-		struct keyscan_test_item *ksi;
-
-		item = &resp->collect.item[i];
-		ksi = &test->items[i];
-		if (!(item->flags & EC_KEYSCAN_SEQ_FLAG_DONE))
-			printf(" [skip %d at beat %u] ", i, ksi->beat);
-	}
-
-	if (strcmp(input, test->expect)) {
-		printf("Expected '%s', got '%s' ", test->expect, input);
-		return -1;
-	}
-
-	return 0;
-}
-
-/**
- * Run all tests
- *
- * @param keyscan	keyscan information
- * @return 0 if ok, -1 on error
- */
-static int keyscan_run_tests(struct keyscan_info *keyscan)
-{
-	int testnum;
-	int any_err = 0;
-
-	for (testnum = 0; testnum < keyscan->test_count; testnum++) {
-		struct keyscan_test *test = &keyscan->tests[testnum];
-		int err;
-
-		fflush(stdout);
-		err = run_test(keyscan, test);
-		any_err |= err;
-		if (err) {
-			printf("%d: %s:  : FAIL\n", testnum, test->name);
-		}
-	}
-
-	return any_err ? -1 : 0;
-}
-
-int cmd_keyscan(int argc, char *argv[])
-{
-	struct keyscan_info keyscan;
-	FILE *f;
-	int err;
-
-	argc--;
-	argv++;
-	if (argc < 2) {
-		fprintf(stderr, "Must specify beat period and filename\n");
-		return -1;
-	}
-	memset(&keyscan, '\0', sizeof(keyscan));
-	keyscan.beat_us = atoi(argv[0]);
-	if (keyscan.beat_us < 100)
-		fprintf(stderr, "Warning: beat period is normally > 100us\n");
-	f = fopen(argv[1], "r");
-	if (!f) {
-		perror("Cannot open file\n");
-		return -1;
-	}
-
-	/* TODO(crosbug.com/p/23826): Read key matrix from fdt */
-	err = keyscan_read_fdt_matrix(&keyscan, "test/test-matrix.bin");
-	if (!err)
-		err = keyscan_process_file(f, &keyscan);
-	if (!err)
-		keyscan_print(&keyscan);
-	if (!err)
-		err = keyscan_run_tests(&keyscan);
-	fclose(f);
-
-	return err;
-}
diff --git a/util/env_changed.sh b/util/env_changed.sh
deleted file mode 100755
index 5bab64760d..0000000000
--- a/util/env_changed.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# This script accepts two parameters: a file name and a string.
-#
-# If the file does not exist, or does not contain the passed in string wrapped
-# in '/*... */, the file is written with the wrapped passed in string.
-
-h_file="$1"
-current_set="/* $2 */"
-
-if [[ -f "${h_file}" ]]; then
-  old_set="$(cat "${h_file}")"
-  if [[ "${current_set}" == "${old_set}" ]]; then
-    exit 0
-  fi
-else
-  dest_dir="$(dirname "${h_file}")"
-  [[ -d "${dest_dir}" ]] || mkdir -p "${dest_dir}"
-fi
-printf "${current_set}" > "${h_file}"
diff --git a/util/export_taskinfo.c b/util/export_taskinfo.c
deleted file mode 100644
index 4c09bafb90..0000000000
--- a/util/export_taskinfo.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * The cmd_c_to_taskinfo will compile this file with different
- * section definitions to export different tasklists.
- */
-
-#include <stdint.h>
-
-#include "config.h"
-#include "task_id.h"
-
-#ifdef SECTION_IS_RO
-#define GET_TASKINFOS_FUNC get_ro_taskinfos
-#elif defined(SECTION_IS_RW)
-#define GET_TASKINFOS_FUNC get_rw_taskinfos
-#else
-#error "Current section (RO/RW) is not defined."
-#endif
-
-struct taskinfo {
-	char *name;
-	char *routine;
-	uint32_t stack_size;
-};
-
-#define TASK(n, r, d, s, ...)  {	\
-	.name = #n,			\
-	.routine = #r,			\
-	.stack_size = s,		\
-},
-static const struct taskinfo taskinfos[] = {
-	CONFIG_TASK_LIST
-};
-#undef TASK
-
-uint32_t GET_TASKINFOS_FUNC(const struct taskinfo **infos)
-{
-	*infos = taskinfos;
-	/* Calculate the number of tasks */
-	return sizeof(taskinfos) / sizeof(*taskinfos);
-}
diff --git a/util/fingerprint-relevant-paths.txt b/util/fingerprint-relevant-paths.txt
deleted file mode 100644
index e530c038cd..0000000000
--- a/util/fingerprint-relevant-paths.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# Paths of interest to be included in the commit message for
-# merge commits to the firmware-fpmcu-<BOARD>-release branch when
-# using update_release_branch.py.
-common/fpsensor
-docs/fingerprint
-driver/fingerprint
diff --git a/util/flash_cr50.py b/util/flash_cr50.py
deleted file mode 100755
index 760a788627..0000000000
--- a/util/flash_cr50.py
+++ /dev/null
@@ -1,771 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Flash Cr50 using gsctool or cr50-rescue.
-
-gsctool example:
-util/flash_cr50.py --image cr50.bin.prod
-util/flash_cr50.py --release prod
-
-cr50-rescue example:
-util/flash_cr50.py --image cr50.bin.prod -c cr50-rescue -p 9999
-util/flash_cr50.py --release prod -c cr50-rescue -p 9999
-"""
-
-import argparse
-import logging
-import os
-import pprint
-import re
-import select
-import shutil
-import subprocess
-import sys
-import tempfile
-import threading
-import time
-
-from chromite.lib import cros_build_lib
-
-CR50_FIRMWARE_BASE = '/opt/google/cr50/firmware/cr50.bin.'
-RELEASE_PATHS = {
-    'prepvt': CR50_FIRMWARE_BASE + 'prepvt',
-    'prod': CR50_FIRMWARE_BASE + 'prod',
-}
-# Dictionary mapping a setup to controls used to verify that the setup is
-# correct. The keys are strings and the values are lists of strings.
-REQUIRED_CONTROLS = {
-    'cr50_uart': [
-        r'raw_cr50_uart_pty:\S+',
-        r'cr50_ec3po_interp_connect:\S+',
-    ],
-    'cr50_reset_odl': [
-        r'cr50_reset_odl:\S+',
-    ],
-    'ec_uart': [
-        r'ec_board:\S+',
-    ],
-    'flex': [
-        r'servo_type:.*servo_.[^4]',
-    ],
-    'type-c_servo_v4': [
-        r'servo_v4_type:type-c',
-        r'servo_v4_role:\S+',
-    ],
-}
-# Supported methods to resetting cr50.
-SUPPORTED_RESETS = (
-    'battery_cutoff',
-    'cr50_reset_odl',
-    'manual_reset',
-)
-
-
-class Error(Exception):
-    """Exception class for flash_cr50 utility."""
-
-
-def run_command(cmd, check_error=True):
-    """Run the given command.
-
-    Args:
-        cmd: The command to run as a list of arguments.
-        check_error: Raise an error if the command fails.
-
-    Returns:
-        (exit_status, The command output)
-
-    Raises:
-        The command error if the command fails and check_error is True.
-    """
-    try:
-        result = cros_build_lib.run(cmd,
-                                    check=check_error,
-                                    print_cmd=True,
-                                    capture_output=True,
-                                    encoding='utf-8',
-                                    stderr=subprocess.STDOUT,
-                                    debug_level=logging.DEBUG,
-                                    log_output=True)
-    except cros_build_lib.RunCommandError as cmd_error:
-        if check_error:
-            raise
-        # OSErrors are handled differently. They're raised even if check is
-        # False. Return the errno and message for OS errors.
-        return cmd_error.exception.errno, cmd_error.msg
-    return result.returncode, result.stdout.strip()
-
-
-class Cr50Image(object):
-    """Class to handle cr50 image conversions."""
-
-    SUFFIX_LEN = 6
-    RW_NAME_BASE = 'cr50.rw.'
-
-    def __init__(self, image, artifacts_dir):
-        """Create an image object that can be used by cr50 updaters."""
-        self._remove_dir = False
-        if not os.path.exists(image):
-            raise Error('Could not find image: %s' % image)
-        if not artifacts_dir:
-            self._remove_dir = tempfile.mkdtemp()
-            artifacts_dir = self._remove_dir
-        if not os.path.isdir(artifacts_dir):
-            raise Error('Directory does not exist: %s' % artifacts_dir)
-        self._original_image = image
-        self._artifacts_dir = artifacts_dir
-        self._generate_file_names()
-
-    def __del__(self):
-        """Remove temporary files."""
-        if self._remove_dir:
-            shutil.rmtree(self._remove_dir)
-
-    def _generate_file_names(self):
-        """Create some filenames to use for image conversion artifacts."""
-        self._tmp_rw_bin = os.path.join(self._artifacts_dir,
-                                        self.RW_NAME_BASE + '.bin')
-        self._tmp_rw_hex = os.path.join(self._artifacts_dir,
-                                        self.RW_NAME_BASE + '.hex')
-        self._tmp_cr50_bin = os.path.join(self._artifacts_dir,
-                                          self.RW_NAME_BASE + '.orig.bin')
-
-    def extract_rw_a_hex(self):
-        """Extract RW_A.hex from the original image."""
-        run_command(['cp', self.get_bin(), self._tmp_cr50_bin])
-        run_command(['dd', 'if=' + self._tmp_cr50_bin, 'of=' + self._tmp_rw_bin,
-                     'skip=16384', 'count=233472', 'bs=1'])
-        run_command(['objcopy', '-I', 'binary', '-O', 'ihex',
-                     '--change-addresses', '0x44000', self._tmp_rw_bin,
-                     self._tmp_rw_hex])
-
-    def get_rw_hex(self):
-        """cr50-rescue uses the .hex file."""
-        if not os.path.exists(self._tmp_rw_hex):
-            self.extract_rw_a_hex()
-        return self._tmp_rw_hex
-
-    def get_bin(self):
-        """Get the filename of the update image."""
-        return self._original_image
-
-    def get_original_basename(self):
-        """Get the basename of the original image."""
-        return os.path.basename(self._original_image)
-
-
-class Servo(object):
-    """Class to interact with servo."""
-
-    # Wait 3 seconds for device to settle after running the dut control command.
-    SHORT_WAIT = 3
-
-    def __init__(self, port):
-        """Initialize servo class.
-
-        Args:
-            port: The servo port for the device being updated.
-        """
-        self._port = port
-
-    def dut_control(self, cmd, check_error=True, wait=False):
-        """Run dut control commands
-
-        Args:
-            cmd: the command to run
-            check_error: Raise RunCommandError if the command returns a non-zero
-                         exit status.
-            wait: If True, wait SHORT_WAIT seconds after running the command
-
-        Returns:
-            (exit_status, output string) - The exit_status will be non-zero if
-            the command failed and check_error is True.
-
-        Raises:
-            RunCommandError if the command fails and check_error is False
-        """
-        dut_control_cmd = ['dut-control', cmd, '-p', self._port]
-        exit_status, output = run_command(dut_control_cmd, check_error)
-        if wait:
-            time.sleep(self.SHORT_WAIT)
-        return exit_status, output.split(':', 1)[-1]
-
-    def get_raw_cr50_pty(self):
-        """Return raw_cr50_pty. Disable ec3po, so the raw pty can be used."""
-        # Disconnect EC3PO, raw_cr50_uart_pty will control the cr50
-        # output and input.
-        self.dut_control('cr50_ec3po_interp_connect:off', wait=True)
-        return self.dut_control('raw_cr50_uart_pty')[1]
-
-    def get_cr50_version(self):
-        """Return the current cr50 version string."""
-        # Make sure ec3po is enabled, so getting cr50_version works.
-        self.dut_control('cr50_ec3po_interp_connect:on', wait=True)
-        return self.dut_control('cr50_version')[1]
-
-
-class Cr50Reset(object):
-    """Class to enter and exit cr50 reset."""
-
-    # A list of requirements for the setup. The requirement strings must match
-    # something in the REQUIRED_CONTROLS dictionary.
-    REQUIRED_SETUP = ()
-
-    def __init__(self, servo, name):
-        """Make sure the setup supports the given reset_type.
-
-        Args:
-            servo: The Servo object for the device.
-            name: The reset type.
-        """
-        self._servo = servo
-        self._reset_name = name
-        self.verify_setup()
-        self._original_watchdog_state = self.ccd_watchdog_enabled()
-        self._servo_type = self._servo.dut_control('servo_type')[1]
-
-    def verify_setup(self):
-        """Verify the setup has all required controls to flash cr50.
-
-        Raises:
-            Error if something is wrong with the setup.
-        """
-        # If this failed before and didn't cleanup correctly, the device may be
-        # cutoff. Try to set the servo_v4_role to recover the device before
-        # checking the device state.
-        self._servo.dut_control('servo_v4_role:src', check_error=False)
-
-        logging.info('Requirements for %s: %s', self._reset_name,
-                     pprint.pformat(self.REQUIRED_SETUP))
-
-        # Get the specific control requirements for the necessary categories.
-        required_controls = []
-        for category in self.REQUIRED_SETUP:
-            required_controls.extend(REQUIRED_CONTROLS[category])
-
-        logging.debug('Required controls for %r:\n%s', self._reset_name,
-                      pprint.pformat(required_controls))
-        setup_issues = []
-        # Check the setup has all required controls in the correct state.
-        for required_control in required_controls:
-            control, exp_response = required_control.split(':')
-            returncode, output = self._servo.dut_control(control, False)
-            logging.debug('%s: got %s expect %s', control, output, exp_response)
-            match = re.search(exp_response, output)
-            if returncode:
-                setup_issues.append('%s: %s' % (control, output))
-            elif not match:
-                setup_issues.append('%s: need %s found %s' %
-                                    (control, exp_response, output))
-            else:
-                logging.debug('matched control: %s:%s', control, match.string)
-                # Save controls, so they can be restored during cleanup.
-                setattr(self, '_' + control, output)
-
-        if setup_issues:
-            raise Error('Cannot run update using %s. Setup issues: %s' %
-                        (self._reset_name, setup_issues))
-        logging.info('Device Setup: ok')
-        logging.info('Reset Method: %s', self._reset_name)
-
-    def cleanup(self):
-        """Try to get the device out of reset and restore all controls."""
-        logging.info('Cleaning up')
-        self.restore_control('cr50_ec3po_interp_connect')
-
-        # Toggle the servo v4 role if possible to try and get the device out of
-        # cutoff.
-        self._servo.dut_control('servo_v4_role:snk', check_error=False)
-        self._servo.dut_control('servo_v4_role:src', check_error=False)
-        self.restore_control('servo_v4_role')
-
-        # Restore the ccd watchdog.
-        self.enable_ccd_watchdog(self._original_watchdog_state)
-
-    def restore_control(self, control):
-        """Restore the control setting, if it has been saved.
-
-        Args:
-            control: The name of the servo control to restore.
-        """
-        setting = getattr(self, control, None)
-        if setting is None:
-            return
-        self._servo.dut_control('%s:%s' % (control, setting))
-
-    def ccd_watchdog_enabled(self):
-        """Return True if servod is monitoring ccd"""
-        if 'ccd_cr50' not in self._servo_type:
-            return False
-        watchdog_state = self._servo.dut_control('watchdog')[1]
-        logging.debug(watchdog_state)
-        return not re.search('ccd:.*disconnect ok', watchdog_state)
-
-    def enable_ccd_watchdog(self, enable):
-        """Control the CCD watchdog.
-
-        Servo will die if it's watching CCD and cr50 is held in reset. Disable
-        the CCD watchdog, so it's ok for CCD to disconnect.
-
-        This function does nothing if ccd_cr50 isn't in the servo type.
-
-        Args:
-            enable: If True, enable the CCD watchdog. Otherwise disable it.
-        """
-        if 'ccd_cr50' not in self._servo_type:
-            logging.debug('Servo is not watching ccd device.')
-            return
-
-        if enable:
-            self._servo.dut_control('watchdog_add:ccd')
-        else:
-            self._servo.dut_control('watchdog_remove:ccd')
-
-        if self.ccd_watchdog_enabled() != enable:
-            raise Error('Could not %sable ccd watchdog' %
-                        ('en' if enable else 'dis'))
-
-    def enter_reset(self):
-        """Disable the CCD watchdog then run the reset cr50 function."""
-        logging.info('Using %r to enter reset', self._reset_name)
-        # Disable the CCD watchdog before putting servo into reset otherwise
-        # servo will die in the middle of flashing cr50.
-        self.enable_ccd_watchdog(False)
-        try:
-            self.run_reset()
-        except Exception as e:
-            logging.warning('%s enter reset failed: %s', self._reset_name, e)
-            raise
-
-    def exit_reset(self):
-        """Exit cr50 reset."""
-        logging.info('Recovering from %s', self._reset_name)
-        try:
-            self.recover_from_reset()
-        except Exception as e:
-            logging.warning('%s exit reset failed: %s', self._reset_name, e)
-            raise
-
-    def run_reset(self):
-        """Start the cr50 reset process.
-
-        Cr50 doesn't have to enter reset in this function. It just needs to do
-        whatever setup is necessary for the exit reset function.
-        """
-        raise NotImplementedError()
-
-    def recover_from_reset(self):
-        """Recover from Cr50 reset.
-
-        Cr50 has to hard or power-on reset during this function for rescue to
-        work. Uart is disabled on deep sleep recovery, so deep sleep is not a
-        valid reset.
-        """
-        raise NotImplementedError()
-
-
-class Cr50ResetODLReset(Cr50Reset):
-    """Class for using the servo cr50_reset_odl to reset cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # cr50_reset_odl is used to hold cr50 in reset. This control only exists
-        # if it actually resets cr50.
-        'cr50_reset_odl',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-    )
-
-    def cleanup(self):
-        """Use the Cr50 reset signal to hold Cr50 in reset."""
-        try:
-            self.restore_control('cr50_reset_odl')
-        finally:
-            super(Cr50ResetODLReset, self).cleanup()
-
-    def run_reset(self):
-        """Use cr50_reset_odl to hold Cr50 in reset."""
-        logging.info('cr50_reset_odl:on')
-        self._servo.dut_control('cr50_reset_odl:on')
-
-    def recover_from_reset(self):
-        """Release the reset signal."""
-        logging.info('cr50_reset_odl:off')
-        self._servo.dut_control('cr50_reset_odl:off')
-
-
-class BatteryCutoffReset(Cr50Reset):
-    """Class for using a battery cutoff through EC commands to reset cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # We need type c servo v4 to recover from battery_cutoff.
-        'type-c_servo_v4',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-        # EC console needs to be read-write to issue cutoff command.
-        'ec_uart',
-    )
-
-    def run_reset(self):
-        """Use EC commands to cutoff the battery."""
-        self._servo.dut_control('servo_v4_role:snk')
-
-        if self._servo.dut_control('ec_board', check_error=False)[0]:
-            logging.warning('EC is unresponsive. Cutoff may not work.')
-
-        self._servo.dut_control('ec_uart_cmd:cutoff', check_error=False,
-                                wait=True)
-        self._servo.dut_control('ec_uart_cmd:reboot', check_error=False,
-                                wait=True)
-
-        if not self._servo.dut_control('ec_board', check_error=False)[0]:
-            raise Error('EC still responsive after cutoff')
-        logging.info('Device is cutoff')
-
-    def recover_from_reset(self):
-        """Connect power using servo v4 to recover from cutoff."""
-        logging.info('"Connecting" adapter')
-        self._servo.dut_control('servo_v4_role:src', wait=True)
-
-
-class ManualReset(Cr50Reset):
-    """Class for using a manual reset to reset Cr50."""
-
-    REQUIRED_SETUP = (
-        # Rescue is done through Cr50 uart. It requires a flex cable not ccd.
-        'flex',
-        # Cr50 rescue is done through cr50 uart.
-        'cr50_uart',
-    )
-
-    PROMPT_WAIT = 5
-    USER_RESET_TIMEOUT = 60
-
-    def run_reset(self):
-        """Nothing to do. User will reset cr50."""
-
-    def recover_from_reset(self):
-        """Wait for the user to reset cr50."""
-        end_time = time.time() + self.USER_RESET_TIMEOUT
-        while time.time() < end_time:
-            logging.info('Press enter after you reset cr50')
-            user_input = select.select([sys.stdin], [], [], self.PROMPT_WAIT)[0]
-            if user_input:
-                logging.info('User reset done')
-                return
-        logging.warning('User input timeout: assuming cr50 reset')
-
-
-class FlashCr50(object):
-    """Class for updating cr50."""
-
-    NAME = 'FlashCr50'
-    PACKAGE = ''
-    DEFAULT_UPDATER = ''
-
-    def __init__(self, cmd):
-        """Verify the update command exists.
-
-        Args:
-            cmd: The updater command.
-
-        Raises:
-            Error if no valid updater command was found.
-        """
-        updater = self.get_updater(cmd)
-        if not updater:
-            emerge_msg = (('Try emerging ' + self.PACKAGE) if self.PACKAGE
-                          else '')
-            raise Error('Could not find %s command.%s' % (self, emerge_msg))
-        self._updater = updater
-
-    def get_updater(self, cmd):
-        """Find a valid updater command.
-
-        Args:
-            cmd: the updater command.
-
-        Returns:
-            A command string or None if none of the commands ran successfully.
-            The command string will be the one supplied or the DEFAULT_UPDATER
-            command.
-        """
-        if not self.updater_works(cmd):
-            return cmd
-
-        use_default = (self.DEFAULT_UPDATER and
-                       not self.updater_works(self.DEFAULT_UPDATER))
-        if use_default:
-            logging.debug('%r failed using %r to update.', cmd,
-                          self.DEFAULT_UPDATER)
-            return self.DEFAULT_UPDATER
-        return None
-
-    @staticmethod
-    def updater_works(cmd):
-        """Verify the updater command.
-
-        Returns:
-          non-zero status if the command failed.
-        """
-        logging.debug('Testing update command %r.', cmd)
-        exit_status, output = run_command([cmd, '-h'], check_error=False)
-        if 'Usage' in output:
-            return 0
-        if exit_status:
-            logging.debug('Could not run %r (%s): %s', cmd, exit_status, output)
-        return exit_status
-
-    def update(self, image):
-        """Try to update cr50 to the given image."""
-        raise NotImplementedError()
-
-    def __str__(self):
-        """Use the updater name for the tostring."""
-        return self.NAME
-
-
-class GsctoolUpdater(FlashCr50):
-    """Class to flash cr50 using gsctool."""
-
-    NAME = 'gsctool'
-    PACKAGE = 'ec-utils'
-    DEFAULT_UPDATER = '/usr/sbin/gsctool'
-
-    # Common failures exit with this status. Use STANDARD_ERRORS to map the
-    # exit status to reasons for the failure.
-    STANDARD_ERROR_REGEX = r'Error: status (\S+)'
-    STANDARD_ERRORS = {
-        '0x8': 'Rejected image with old header.',
-        '0x9': 'Update too soon.',
-        '0xc': 'Board id mismatch',
-    }
-
-    def __init__(self, cmd, serial=None):
-        """Generate the gsctool command.
-
-        Args:
-            cmd: gsctool updater command.
-            serial: The serial number of the CCD device being updated.
-        """
-        super(GsctoolUpdater, self).__init__(cmd)
-        self._gsctool_cmd = [self._updater]
-        if serial:
-            self._gsctool_cmd.extend(['-n', serial])
-
-    def update(self, image):
-        """Use gsctool to update cr50.
-
-        Args:
-            image: Cr50Image object.
-        """
-        update_cmd = self._gsctool_cmd[:]
-        update_cmd.append(image.get_bin())
-        exit_status, output = run_command(update_cmd, check_error=False)
-        if not exit_status or (exit_status == 1 and 'image updated' in output):
-            logging.info('update ok')
-            return
-        if exit_status == 3:
-            match = re.search(self.STANDARD_ERROR_REGEX, output)
-            if match:
-                update_error = match.group(1)
-                logging.info('Update error %s', update_error)
-                raise Error(self.STANDARD_ERRORS[update_error])
-        raise Error('gsctool update error: %s' % output.splitlines()[-1])
-
-
-class Cr50RescueUpdater(FlashCr50):
-    """Class to flash cr50 through servo micro uart."""
-
-    NAME = 'cr50-rescue'
-    PACKAGE = 'cr50-utils'
-    DEFAULT_UPDATER = '/usr/bin/cr50-rescue'
-
-    WAIT_FOR_UPDATE = 120
-    RESCUE_RESET_DELAY = 5
-
-    def __init__(self, cmd, port, reset_type):
-        """Initialize cr50-rescue updater.
-
-        cr50-rescue can only be done through servo, because it needs access to
-        a lot of dut-controls and cr50 uart through servo micro. During rescue
-        Cr50 has to do a hard reset, so the user should supply a valid reset
-        method for the setup that's being used.
-
-        Args:
-            cmd: The cr50-rescue command.
-            port: The servo port of the device being updated.
-            reset_type: A string (one of SUPPORTED_RESETS) that describes how
-                        to reset Cr50 during cr50-rescue.
-        """
-        super(Cr50RescueUpdater, self).__init__(cmd)
-        self._servo = Servo(port)
-        self._rescue_thread = None
-        self._rescue_process = None
-        self._cr50_reset = self.get_cr50_reset(reset_type)
-
-    def get_cr50_reset(self, reset_type):
-        """Get the cr50 reset object for the given reset_type.
-
-        Args:
-            reset_type: a string describing how cr50 will be reset. It must be
-                        in SUPPORTED_RESETS.
-
-        Returns:
-            The Cr50Reset object for the given reset_type.
-        """
-        assert reset_type in SUPPORTED_RESETS, '%s is unsupported.' % reset_type
-        if reset_type == 'battery_cutoff':
-            return BatteryCutoffReset(self._servo, reset_type)
-        elif reset_type == 'cr50_reset_odl':
-            return Cr50ResetODLReset(self._servo, reset_type)
-        return ManualReset(self._servo, reset_type)
-
-    def update(self, image):
-        """Use cr50-rescue to update cr50 then cleanup.
-
-        Args:
-            image: Cr50Image object.
-        """
-        update_file = image.get_rw_hex()
-        try:
-            self.run_update(update_file)
-        finally:
-            self.restore_state()
-
-    def start_rescue_process(self, update_file):
-        """Run cr50-rescue in a process, so it can be killed it if it hangs."""
-        pty = self._servo.get_raw_cr50_pty()
-
-        rescue_cmd = [self._updater, '-v', '-i', update_file, '-d', pty]
-        logging.info('Starting cr50-rescue: %s',
-                     cros_build_lib.CmdToStr(rescue_cmd))
-
-        self._rescue_process = subprocess.Popen(rescue_cmd)
-        self._rescue_process.communicate()
-        logging.info('Rescue Finished')
-
-    def start_rescue_thread(self, update_file):
-        """Start cr50-rescue."""
-        self._rescue_thread = threading.Thread(target=self.start_rescue_process,
-                                               args=[update_file])
-        self._rescue_thread.start()
-
-    def run_update(self, update_file):
-        """Run the Update"""
-        # Enter reset before starting rescue, so any extra cr50 messages won't
-        # interfere with cr50-rescue.
-        self._cr50_reset.enter_reset()
-
-        self.start_rescue_thread(update_file)
-
-        time.sleep(self.RESCUE_RESET_DELAY)
-        # Resume from cr50 reset.
-        self._cr50_reset.exit_reset()
-
-        self._rescue_thread.join(self.WAIT_FOR_UPDATE)
-
-        logging.info('cr50_version:%s', self._servo.get_cr50_version())
-
-    def restore_state(self):
-        """Try to get the device out of reset and restore all controls"""
-        try:
-            self._cr50_reset.cleanup()
-        finally:
-            self.cleanup_rescue_thread()
-
-    def cleanup_rescue_thread(self):
-        """Cleanup the rescue process and handle any errors."""
-        if not self._rescue_thread:
-            return
-        if self._rescue_thread.is_alive():
-            logging.info('Killing cr50-rescue process')
-            self._rescue_process.terminate()
-            self._rescue_thread.join()
-
-        self._rescue_thread = None
-        if self._rescue_process.returncode:
-            logging.info('cr50-rescue failed.')
-            logging.info('stderr: %s', self._rescue_process.stderr)
-            logging.info('stdout: %s', self._rescue_process.stdout)
-            logging.info('returncode: %s', self._rescue_process.returncode)
-            raise Error('cr50-rescue failed (%d)' %
-                        self._rescue_process.returncode)
-
-
-def parse_args(argv):
-    """Parse commandline arguments.
-
-    Args:
-        argv: command line args
-
-    Returns:
-        options: an argparse.Namespace.
-    """
-    usage = ('%s -i $IMAGE [ -c cr50-rescue -p $SERVO_PORT [ -r '
-             '$RESET_METHOD]]' % os.path.basename(argv[0]))
-    parser = argparse.ArgumentParser(usage=usage, description=__doc__)
-    parser.add_argument('-d', '--debug', action='store_true', default=False,
-                        help='enable debug messages.')
-    parser.add_argument('-i', '--image', type=str,
-                        help='Path to cr50 binary image.')
-    parser.add_argument('-R', '--release', type=str,
-                        choices=RELEASE_PATHS.keys(),
-                        help='Type of cr50 release. Use instead of the image '
-                        'arg.')
-    parser.add_argument('-c', '--updater-cmd', type=str, default='gsctool',
-                        help='Tool to update cr50. Either gsctool or '
-                        'cr50-rescue')
-    parser.add_argument('-s', '--serial', type=str, default='',
-                        help='serial number to pass to gsctool.')
-    parser.add_argument('-p', '--port', type=str, default='',
-                        help='port servod is listening on (required for '
-                        'rescue).')
-    parser.add_argument('-r', '--reset-type', default='battery_cutoff',
-                        choices=SUPPORTED_RESETS,
-                        type=str, help='The method for cr50 reset.')
-    parser.add_argument('-a', '--artifacts-dir', default=None, type=str,
-                        help='Location to store artifacts')
-    opts = parser.parse_args(argv[1:])
-    if 'cr50-rescue' in opts.updater_cmd and not opts.port:
-        raise parser.error('Servo port is required for cr50 rescue')
-    return opts
-
-
-def get_updater(opts):
-    """Get the updater object."""
-    if 'cr50-rescue' in opts.updater_cmd:
-        return Cr50RescueUpdater(opts.updater_cmd, opts.port, opts.reset_type)
-    if 'gsctool' in opts.updater_cmd:
-        return GsctoolUpdater(opts.updater_cmd, opts.serial)
-    raise Error('Unsupported update command %r' % opts.updater_cmd)
-
-
-def main(argv):
-    """Update cr50 using gsctool or cr50-rescue."""
-    opts = parse_args(argv)
-
-    loglevel = logging.INFO
-    log_format = '%(asctime)s - %(levelname)7s'
-    if opts.debug:
-        loglevel = logging.DEBUG
-        log_format += ' - %(lineno)3d:%(funcName)-15s'
-    log_format += ' - %(message)s'
-    logging.basicConfig(level=loglevel, format=log_format)
-
-    image = Cr50Image(RELEASE_PATHS.get(opts.release, opts.image),
-                      opts.artifacts_dir)
-    flash_cr50 = get_updater(opts)
-
-    logging.info('Using %s to update to %s', flash_cr50,
-                 image.get_original_basename())
-    flash_cr50.update(image)
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv))
diff --git a/util/flash_ec b/util/flash_ec
deleted file mode 100755
index 8fcde8d14b..0000000000
--- a/util/flash_ec
+++ /dev/null
@@ -1,1615 +0,0 @@
-#!/bin/bash
-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-SCRIPT="$(readlink -f "$0")"
-SCRIPT_DIR="$(dirname "$SCRIPT")"
-
-EC_DIR="$(readlink -f "${SCRIPT_DIR}/..")"
-if [[ "$(basename "${EC_DIR}")" != "ec" ]]; then
-	EC_DIR=
-fi
-
-# Loads script libraries.
-. "/usr/share/misc/shflags" || exit 1
-
-# Redirects tput to stderr, and drop any error messages.
-tput2() {
-	tput "$@" 1>&2 2>/dev/null || true
-}
-
-error() {
-	tput2 bold && tput2 setaf 1
-	echo "ERROR: $*" >&2
-	tput2 sgr0
-}
-
-
-info() {
-	tput2 bold && tput2 setaf 2
-	echo "INFO: $*" >&2
-	tput2 sgr0
-}
-
-warn() {
-	tput2 bold && tput2 setaf 3
-	echo "WARNING: $*" >&2
-	tput2 sgr0
-}
-
-die() {
-	[ -z "$*" ] || error "$@"
-	exit 1
-}
-
-
-# Include a board name to the BOARDS_${EC_CHIP} array below ONLY IF servod is
-# not aware of its 'ec_chip'. If servod becomes able to answer 'ec_chip'
-# for the board, remove it from BOARDS_XXXX array below.
-BOARDS_IT83XX=(
-	adlrvpm_ite
-	adlrvpp_ite
-	it83xx_evb
-	jslrvp_ite
-	reef_it8320
-	tglrvpu_ite
-	tglrvpu_ite_tcpmv1
-	tglrvpy_ite
-	tglrvpy_ite_tcpmv1
-)
-
-BOARDS_IT83XX_SPI_PROGRAMMING=(
-	it8xxx2_evb
-	it8xxx2_pdevb
-)
-
-BOARDS_STM32=(
-	bloonchipper
-	chell_pd
-	coffeecake
-	chocodile_bec
-	chocodile_vpdmcu
-	dartmonkey
-	glados_pd
-	hatch_fp
-	jerry
-	minimuffin
-	nami_fp
-	nocturne_fp
-	oak_pd
-	pit
-	plankton
-	rainier
-	strago_pd
-	zinger
-)
-BOARDS_STM32_PROG_EN=(
-	plankton
-)
-
-BOARDS_STM32_DFU=(
-	c2d2
-	dingdong
-	hoho
-	twinkie
-	discovery
-	servo_v4
-	servo_v4p1
-	servo_micro
-	sweetberry
-	polyberry
-	stm32f446e-eval
-	tigertail
-	fluffy
-)
-
-BOARDS_NPCX_5M5G_JTAG=(
-	npcx_evb
-	npcx_evb_arm
-)
-
-BOARDS_NPCX_5M6G_JTAG=(
-)
-
-BOARDS_NPCX_7M6X_JTAG=(
-)
-
-BOARDS_NPCX_7M7X_JTAG=(
-	npcx7_evb
-)
-
-BOARDS_NPCX_SPI=(
-)
-
-BOARDS_NPCX_INT_SPI=(
-	adlrvpp_npcx
-)
-
-BOARDS_SPI_1800MV=(
-	coral
-	reef
-)
-
-BOARDS_RAIDEN=(
-	coral
-	eve
-	fizz
-	kukui
-	nami
-	nautilus
-	poppy
-	rammus
-	reef
-	scarlet
-	soraka
-)
-
-DEFAULT_PORT="${SERVOD_PORT:-9999}"
-BITBANG_RATE="57600"  # Could be overwritten by a command line option.
-
-# Flags
-DEFINE_integer bitbang_rate "${BITBANG_RATE}" \
-	"UART baud rate to use when bit bang programming, "\
-"standard UART rates from 9600 to 57600 are supported."
-DEFINE_string board "${DEFAULT_BOARD}" \
-	"The board to run debugger on."
-DEFINE_string chip "" \
-	"The chip to run debugger on."
-DEFINE_boolean dry_run "${FLAGS_FALSE}" \
-	"Print the commands to be run instead of actually running them."
-DEFINE_string image "" \
-	"Full pathname of the EC firmware image to flash."
-DEFINE_string logfile "" \
-	"Stm32 only: pathname of the file to store communications log."
-DEFINE_string offset "0" \
-	"Offset where to program the image from."
-DEFINE_integer port "${DEFAULT_PORT}" \
-	"Port to communicate to servo on."
-DEFINE_boolean raiden "${FLAGS_FALSE}" \
-	"Use raiden_debug_spi programmer"
-DEFINE_string read "" "Pathname of the file to store EC firmware image."
-DEFINE_boolean ro "${FLAGS_FALSE}" \
-	"Write only the read-only partition"
-DEFINE_boolean servo_micro_uart_rx_rework "${FLAGS_FALSE}" \
-	"The servo micro for flashing has b/143163043#comment3 rework"
-DEFINE_integer timeout 600 \
-	"Timeout for flashing the EC, measured in seconds."
-DEFINE_boolean verbose "${FLAGS_FALSE}" \
-	"Verbose hw control logging"
-DEFINE_boolean verify "${FLAGS_FALSE}" \
-	"Verify EC firmware image after programming."
-DEFINE_boolean zephyr "${FLAGS_FALSE}" \
-	"Program a Zephyr EC image instead of a CrOS EC image"
-
-# Parse command line
-FLAGS_HELP="usage: $0 [flags]"
-FLAGS "$@" || exit 1
-eval set -- "${FLAGS_ARGV}"
-if [[ $# -gt 0 ]]; then
-	die "invalid arguments: \"$*\""
-fi
-
-# Error messages
-MSG_PROGRAM_FAIL="Failed to flash EC firmware image"
-MSG_READ_FAIL="Failed to read EC firmware image"
-MSG_VERIFY_FAIL="Failed to verify EC firmware image."
-
-set -e
-
-DUT_CONTROL_CMD=( "dut-control" "--port=${FLAGS_port}" )
-DUT_CTRL_PREFIX=""
-
-# Run a command which mutates the state of an attached device.
-# This is used by the --dry_run flag, when enabled, the command will
-# only print.  When disabled, the command will run without printing
-# any message.
-function print_or_run() {
-	if [ "${FLAGS_dry_run}" = "${FLAGS_TRUE}" ]; then
-		local arg
-		local -a quoted_args
-
-		# Quote each of the arguments so it can easily be
-		# copy-pasted into a shell.
-		for arg in "$@"; do
-			quoted_args+=("$(printf "%q" "${arg}")")
-		done
-
-		tput2 bold && tput2 setaf 4
-		echo "DRY RUN:" "${quoted_args[@]}" >&2
-		tput2 sgr0
-	else
-		"$@"
-	fi
-}
-
-function dut_control() {
-	local DUT_CTRL_CML=( "${DUT_CONTROL_CMD[@]}" )
-
-	for p in $@ ; do
-		# Only add the prefix if the arg is a control name.
-		if [[ ${p} != -* ]] ; then
-			p="${DUT_CTRL_PREFIX}${p}"
-		fi
-		DUT_CTRL_CML+=( "$p" )
-	done
-
-	if [ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]; then
-		echo "${DUT_CTRL_CML[*]}" 1>&2
-	fi
-
-	print_or_run "${DUT_CTRL_CML[@]}" >/dev/null
-}
-
-function dut_control_or_die {
-	dut_control "$@" || die "command exited $? (non-zero): dut-control $*"
-}
-
-function dut_control_get() {
-	if [ $# -gt 1 ]; then
-		error "${FUNCNAME[0]} failed: more than one argument: $@"
-		return 1
-	fi
-
-	local ARGS DUT_GETVAL RETVAL
-	ARGS=( "${DUT_CONTROL_CMD[@]}" "--value_only" "${DUT_CTRL_PREFIX}$1" )
-	RETVAL=0
-	# || statement is attached to avoid an exit if error exit is enabled.
-	DUT_GETVAL=$( "${ARGS[@]}" ) || RETVAL="$?"
-	if (( "${RETVAL}" )) ; then
-		warn "${FUNCNAME[0]} failed: ${ARGS[*]} returned ${RETVAL}."
-		return "${RETVAL}"
-	fi
-
-	echo "${DUT_GETVAL}"
-}
-
-function dut_control_get_or_die {
-	dut_control_get "$@" || \
-	    die "command exited $? (non-zero): dut-control --value_only $*"
-}
-
-: ${BOARD:=${FLAGS_board}}
-
-# Find the Zephyr project directory for the specified board. Zephyr projects
-# organized under ./zephyr/projects as <baseboard>/<board> directory.
-: ${ZEPHYR_DIR:=$(find zephyr/projects -mindepth 2 -maxdepth 2 \
-		-type d -name "${BOARD}")}
-
-in_array() {
-	local n=$#
-	local value=${!n}
-
-	for (( i=1; i<$#; i++ )) do
-		if [ "${!i}" == "${value}" ]; then
-			return 0
-		fi
-	done
-	return 1
-}
-
-declare -a SUPPORTED_CHIPS
-
-if $(in_array "${BOARDS_STM32[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("stm32")
-fi
-
-if $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("stm32_dfu")
-fi
-
-if $(in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_5m5g_jtag")
-fi
-
-if $(in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_5m6g_jtag")
-fi
-
-if $(in_array "${BOARDS_NPCX_7M6X_JTAG[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_7m6x_jtag")
-fi
-
-if $(in_array "${BOARDS_NPCX_7M7X_JTAG[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_7m7x_jtag")
-fi
-
-if $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_spi")
-fi
-
-if $(in_array "${BOARDS_NPCX_INT_SPI[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("npcx_int_spi")
-fi
-
-if $(in_array "${BOARDS_IT83XX[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("it83xx")
-fi
-
-if $(in_array "${BOARDS_IT83XX_SPI_PROGRAMMING[@]}" "${BOARD}"); then
-	SUPPORTED_CHIPS+=("ite_spi")
-fi
-
-if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 && -n "${FLAGS_chip}" ]]; then
-	SUPPORTED_CHIPS+="${FLAGS_chip}"
-fi
-
-if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
-	SERVO_EC_CHIP="$(dut_control_get ec_chip)"
-	SERVO_EC_CHIP="${SERVO_EC_CHIP,,}"
-	if [[ "${SERVO_EC_CHIP}" =~ "unknown" || -z "${SERVO_EC_CHIP}" ]]; then
-		die "Please check that servod is running or," \
-		"manually specify either --board or --chip."
-	fi
-	SUPPORTED_CHIPS+=("${SERVO_EC_CHIP}")
-fi
-
-if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
-	# This happens if ${FLAGS_board} is not known in this flash_ec yet,
-	# ${FLAGS_chip} is not given, and servod doesn't know ec_chip.
-	# In this case, '--chip' should be specified in the command line.
-	die "board '${BOARD}' not supported." \
-	    "Please check that servod is running, or manually specify --chip."
-elif [[ ${#SUPPORTED_CHIPS[@]} -eq 1 ]]; then
-	CHIP="${SUPPORTED_CHIPS[0]}"
-elif [ -n "${FLAGS_chip}" ]; then
-	if $(in_array "${SUPPORTED_CHIPS[@]}" "${FLAGS_chip}"); then
-		CHIP="${FLAGS_chip}"
-	else
-		die "board ${BOARD} only supports (${SUPPORTED_CHIPS[@]})," \
-			"not ${FLAGS_chip}."
-	fi
-else
-	# Ideally, ec_chip per servo_type should be specified in servo overlay
-	# file, instead of having multiple board-to-chip mapping info in this
-	# script. Please refer to crrev.com/c/1496460 for example.
-	die "board ${BOARD} supports multiple chips" \
-	"(${FILTERED_CHIPS[@]}). Use --chip= to choose one."
-fi
-
-if [ -n "${FLAGS_chip}" -a "${CHIP}" != "${FLAGS_chip}" ]; then
-	die "board ${BOARD} doesn't use chip ${FLAGS_chip}"
-fi
-
-if [[ "${CHIP}" = "stm32_dfu" ]]; then
-	NEED_SERVO="no"
-fi
-
-# Servo variables management
-case "${BOARD}" in
-	chocodile_bec ) MCU="usbpd" ;;
-	oak_pd|strago_pd ) MCU="usbpd" ;;
-	chell_pd|glados_pd ) MCU="usbpd" ;;
-	bloonchipper|dartmonkey|hatch_fp|nami_fp|nocturne_fp ) MCU="fpmcu" ;;
-	dingdong|hoho|twinkie ) DUT_CONTROL_CMD=( "true" ); MCU="ec" ;;
-	*) MCU="ec" ;;
-esac
-
-case "${CHIP}" in
-	"stm32"|"npcx_spi"|"npcx_int_spi"|"it83xx"|"npcx_uut"|"ite_spi"| \
-			"ite_spi_ccd_i2c")
-		;;
-	*)
-		if [[ -n "${FLAGS_read}" ]]; then
-			die "The flag is not yet supported on ${CHIP}."
-		fi
-
-		# If verification is not supported, then show a warning message.
-		# Keep it running however.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			warn "Ignoring '--verify'" \
-			"since read is not supported on ${CHIP}."
-		fi
-		;;
-esac
-
-SERVO_TYPE="$(dut_control_get servo_type || :)"
-
-if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*$ ]]; then
-	ACTIVE_DEVICE="$(dut_control_get active_dut_controller)"
-else
-	ACTIVE_DEVICE="${SERVO_TYPE}"
-fi
-
-if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*_and_.*$ ]]; then
-	# If there are two devices, servo v4 type will show both devices. The
-	# default device is first. The other device is second.
-	# servo_type:servo_v4{p1}_with_servo_micro_and_ccd_cr50
-	SECOND_DEVICE="${SERVO_TYPE#*_and_}"
-	# servo_v4p1 can shared the same type with servo_v4, since there's no
-	# difference handling the flash.
-	SERVO_TYPE="servo_v4_with_${ACTIVE_DEVICE}"
-	# Controls sent through the default device don't have a prefix. The
-	# second device controls do. If the default device isn't active, we
-	# need to use the second device controls to send commands. Use the
-	# prefix for all dut control commands.
-	if [[ "${SECOND_DEVICE}" = "${ACTIVE_DEVICE}" ]]; then
-		DUT_CTRL_PREFIX="${ACTIVE_DEVICE}."
-	fi
-fi
-
-servo_is_ccd() {
-	[[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] || \
-	[[ "${SERVO_TYPE}" =~ "ccd_ti50" ]]
-}
-
-servo_has_warm_reset() {
-	dut_control -i warm_reset >/dev/null 2>&1
-}
-
-servo_has_cold_reset() {
-	dut_control -i cold_reset >/dev/null 2>&1
-}
-
-servo_has_dut_i2c_mux() {
-	dut_control -i dut_i2c_mux >/dev/null 2>&1
-}
-
-servo_ec_hard_reset_or_die() {
-	dut_control_or_die cold_reset:on
-	dut_control_or_die cold_reset:off
-
-	# Cold reset on C2D2 is H1 reset, which will double reset the EC
-	# We need to wait a little bit to ensure we catch final EC reset
-	if [[ "${SERVO_TYPE}" =~ "c2d2" ]]; then
-		print_or_run sleep 0.2
-	fi
-}
-
-servo_ec_hard_reset() {
-	dut_control cold_reset:on
-	dut_control cold_reset:off
-}
-
-c2d2_ec_hard_reset() {
-	# This is an H1-level reset (instead of just an EC-level reset)
-	dut_control cold_reset:on
-	dut_control cold_reset:off
-}
-
-servo_usbpd_hard_reset() {
-	dut_control usbpd_reset:on sleep:0.5 usbpd_reset:off
-}
-
-servo_fpmcu_hard_reset() {
-	dut_control fpmcu_reset:on sleep:0.5 fpmcu_reset:off
-}
-
-servo_sh_hard_reset() {
-	dut_control sh_reset:on
-	dut_control sh_reset:off
-}
-
-ec_reset() {
-	local stype
-
-	if [[ "${SERVO_TYPE}" =~ "servo" ]] || servo_is_ccd; then
-		stype="servo"
-	else
-		stype=${SERVO_TYPE}
-	fi
-
-	if [[ -n "${stype}" ]]; then
-		eval ${stype}_${MCU}_hard_reset
-	fi
-}
-
-ccd_ec_boot0() {
-	local on_value="${1}"
-	local boot_mode="${2}"
-
-	info "Using CCD ${boot_mode}."
-
-	if [[ "${on_value}" == "on" ]] && [[ "${boot_mode}" == "uut" ]] ; then
-		# Ti50 requires EC reset to be asserted before UUT mode can be
-		# enabled, Cr50 should not mind.
-		dut_control cold_reset:on
-	fi
-
-	dut_control "ccd_ec_boot_mode_${boot_mode}":"${on_value}"
-}
-
-servo_micro_ec_boot0() {
-	# Some devices (e.g. hatch) control the RX UART pin via an on-board
-	# circuit that is controlled by the EC_FLASH_ODL pin. For those boards,
-	# we want to continue to drive the EC_FLASH_ODL if they do not have the
-	# servo micro rework listed below.
-	if [[ "${FLAGS_servo_micro_uart_rx_rework}" == ${FLAGS_TRUE} ]]; then
-		info "Servo micro $2 mode: $1 (using rx_rework)"
-
-		# Setting the test point allows the EC_TX_SERVO_RX line
-		# to be driven by the servo for 'on' value. 'off' value
-		# lets the EC drive the EC_TX_SERVO_RX net.
-		#
-		# HW Rework (b/143163043#comment3):
-		#   - Disconnect U45.1 from ground
-		#   - Connected U45.1 to TP1 pad
-		dut_control tp1:$1
-		dut_control servo_micro_ec_boot_mode_$2:$1
-	else
-		info "Servo micro $2 mode: $1 (using FW_UP_L)"
-		dut_control ec_boot_mode:$1
-	fi
-}
-
-servo_ec_boot0() {
-	dut_control ec_boot_mode:$1
-}
-
-c2d2_ec_boot0() {
-	dut_control ec_boot_mode_uut:$1
-}
-
-servo_usbpd_boot0() {
-	dut_control usbpd_boot_mode:$1
-}
-
-servo_fpmcu_boot0() {
-	dut_control fpmcu_boot_mode:"$1"
-}
-
-servo_micro_fpmcu_boot0() {
-	servo_fpmcu_boot0 "$@"
-}
-
-servo_micro_usbpd_boot0() {
-	servo_usbpd_boot0 "$@"
-}
-
-servo_sh_boot0() {
-	dut_control sh_boot_mode:$1
-}
-
-ec_switch_boot0() {
-	local on_value=$1
-	# Enable programming GPIOs
-	if $(in_array "${BOARDS_STM32_PROG_EN[@]}" "${BOARD}"); then
-		servo_save_add "prog_en"
-
-		dut_control prog_en:yes
-	fi
-	if servo_is_ccd ; then
-		stype=ccd
-	elif [[ "${SERVO_TYPE}" =~ "servo_micro" ]] ; then
-		stype=servo_micro
-	elif [[ "${SERVO_TYPE}" =~ "servo" ]] ; then
-		stype=servo
-	else
-		stype=${SERVO_TYPE}
-	fi
-	eval ${stype}_${MCU}_boot0 "${on_value}" $2
-}
-
-ec_enable_boot0() {
-	ec_switch_boot0 "on" $1
-}
-
-ec_disable_boot0() {
-	ec_switch_boot0 "off" $1
-}
-
-# Returns 0 on success (if on beaglebone)
-on_servov3() {
-	grep -qs '^CHROMEOS_RELEASE_BOARD=beaglebone_servo' /etc/lsb-release
-}
-
-# Returns 0 on success (if raiden should be used instead of servo)
-error_reported=  # Avoid double printing the error message.
-on_raiden() {
-	if [[ "${SERVO_TYPE}" =~ "servo_v4" ]] || \
-	   servo_is_ccd || \
-	   [[ "${SERVO_TYPE}" =~ "servo_micro" ]]; then
-		return 0
-	fi
-	if [ -z "${BOARD}" ]; then
-		[ "${FLAGS_raiden}" = ${FLAGS_TRUE} ] && return 0 || return 1
-	fi
-	if [ "${FLAGS_raiden}" = ${FLAGS_TRUE} ]; then
-		if in_array "${BOARDS_RAIDEN[@]}" "${BOARD}"; then
-			return 0
-		fi
-		if [ -z "${error_reported}" ]; then
-			error_reported="y"
-			die "raiden mode not supported on ${BOARD}" >&2
-		fi
-	fi
-	return 1
-}
-
-declare -a DELETE_LIST 	# Array of file/dir names to delete at exit
-
-# Put back the servo and the system in a clean state at exit
-FROZEN_PIDS=""
-cleanup() {
-	for pid in ${FROZEN_PIDS}; do
-		info "Sending SIGCONT to process ${pid}!"
-		kill -CONT "${pid}"
-	done
-
-	# Delete all files or directories in DELETE_LIST.
-	for item in "${DELETE_LIST[@]}"; do
-		if [[ -e "${item}" ]]; then
-			print_or_run rm -rf "${item}" &> /dev/null
-		fi
-	done
-
-	if [ "${CHIP}" = "it83xx" ]; then
-		if [ "${SERVO_TYPE}" = "servo_v2" ]; then
-			info "Reinitializing ftdi_i2c interface"
-			# Ask servod to close its FTDI I2C interface because it
-			# could be open or closed at this point.  Using
-			# ftdii2c_cmd:close when it's already closed is okay,
-			# however ftdii2c_cmd:open when it's already open
-			# triggers an error.
-			#
-			# If there is a simple, reliable way to detect whether
-			# servod FTDI I2C interface is open or closed, it would
-			# be preferable to check and only re-initialize if it's
-			# closed.  Patches welcome.
-			dut_control ftdii2c_cmd:close
-			dut_control ftdii2c_cmd:init
-			dut_control ftdii2c_cmd:open
-			dut_control ftdii2c_cmd:setclock
-		fi
-	fi
-
-	servo_restore
-
-	if [ "${CHIP}" = "stm32" -o "${CHIP}" = "npcx_uut" ]; then
-		dut_control "${MCU}"_boot_mode:off
-	fi
-
-	if servo_is_ccd; then
-		dut_control ccd_ec_boot_mode_uut:off
-		dut_control ccd_ec_boot_mode_bitbang:off
-	fi
-
-	if ! on_raiden || servo_has_cold_reset; then
-		ec_reset
-	fi
-}
-trap cleanup EXIT
-
-# TODO: the name of the RO images created for zephyr vary based on whether
-# the RO image includes a header.
-# NPCX images use "build-ro/zephyr/zephyr.npcx.bin"
-# ITE images use "build-ro/zephyr/zephyr.bin"
-if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] && [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ]
-then
-	die "The --ro flag is not supported with the --zephyr flag"
-fi
-
-# Possible default EC images
-if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
-	EC_FILE=ec.RO.flat
-elif [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ] ; then
-	EC_FILE=zephyr.bin
-else
-	EC_FILE=ec.bin
-fi
-
-LOCAL_BUILD=
-if [[ -n "${EC_DIR}" ]]; then
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
-		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/RO/${EC_FILE}"
-	elif [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ] ; then
-		LOCAL_BUILD="${EC_DIR}/build/${ZEPHYR_DIR}/output/${EC_FILE}"
-	else
-		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/${EC_FILE}"
-	fi
-fi
-
-# Get baseboard from build system if present
-BASEBOARD=
-
-# We do not want to exit script if make call fails; we turn -e back on after
-# setting BASEBOARD
-set +e
-if [[ -n "${EC_DIR}" ]]; then
-	BASEBOARD=$(make --quiet -C ${EC_DIR} BOARD=${BOARD} print-baseboard \
-		2>/dev/null)
-elif [[ -d "${HOME}/trunk/src/platform/ec" ]]; then
-	BASEBOARD=$(make --quiet -C ${HOME}/trunk/src/platform/ec \
-		BOARD=${BOARD} print-baseboard 2>/dev/null)
-else
-	info "Could not find ec build folder to calculate baseboard."
-fi
-if [ $? -ne 0 ]; then
-	info "EC build system didn't recognize ${BOARD}. Assuming no baseboard."
-fi
-set -e
-
-if [[ -n "${BASEBOARD}" ]]; then
-	EMERGE_BUILD=/build/${BASEBOARD}/firmware/${BOARD}/${EC_FILE}
-else
-	EMERGE_BUILD=/build/${BOARD}/firmware/${EC_FILE}
-fi
-
-# Find the EC image to use
-function ec_image() {
-	# No image specified on the command line, try default ones
-	if [[ -n "${FLAGS_image}" ]] ; then
-		if [ -f "${FLAGS_image}" ] || \
-		   [ "${FLAGS_image}" == "-" ]; then
-			echo "${FLAGS_image}"
-			return
-		fi
-		die "Invalid image path : ${FLAGS_image}"
-	else
-		if [ -f "${LOCAL_BUILD}" ]; then
-			echo "${LOCAL_BUILD}"
-			return
-		fi
-		if [ -f "${EMERGE_BUILD}" ]; then
-			echo "${EMERGE_BUILD}"
-			return
-		fi
-	fi
-	die "no EC image found : build one or specify one."
-}
-
-# Get the correct UART for flashing. The resulting string is concatenated with
-# the various UART control suffixes, such as "_pty", "_en", "_parity", etc.
-function servo_ec_uart_prefix() {
-	if [[ "${MCU}" == "fpmcu" ]]; then
-		# The FPMCU has multiple UARTs. Use the platform UART since it's a
-		# bootloader capable UART on all devices. See
-		# http://go/cros-fingerprint-reference-designs#uart-console.
-		echo "fpmcu_platform_uart"
-		return
-	fi
-
-	echo "${MCU}_uart"
-}
-
-# Find the EC UART provided by servo.
-function servo_ec_uart() {
-	SERVOD_FAIL="Cannot communicate with servod. Is servod running?"
-	local EC_UART_PREFIX
-	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
-	PTY=$(dut_control_get "raw_${EC_UART_PREFIX}_pty" ||
-	      dut_control_get "${EC_UART_PREFIX}_pty")
-	if [[ -z "${PTY}" ]]; then
-	    die "${SERVOD_FAIL}"
-	fi
-	echo $PTY
-}
-
-# Not every control is supported on every servo type.  Therefore, define which
-# controls are supported by each servo type.
-servo_v2_VARS=( "cold_reset" )
-servo_micro_VARS=( "cold_reset" )
-servo_v4_with_ccd_cr50_VARS=( "cold_reset" )
-c2d2_VARS=( "cold_reset" )
-
-# Some servo boards use the same controls.
-servo_v3_VARS=( "${servo_v2_VARS[@]}" )
-servo_v4_with_servo_micro_VARS=( "${servo_micro_VARS[@]}" )
-
-declare -a save
-
-#######################################
-# Store DUT control value to restore in LIFO order.
-# Arguments:
-#   $1: Control name
-#   $2: (optional) Value to restore for the name at exit.
-#######################################
-function servo_save_add() {
-	local CTRL_RESULT=
-	case $# in
-		1) CTRL_RESULT="$( "${DUT_CONTROL_CMD[@]}" \
-				"${DUT_CTRL_PREFIX}$@" )"
-		   if [[ -n "${CTRL_RESULT}" ]]; then
-			# Don't save the control with the prefix, because
-			# dut_control will add the prefix again when we restore
-			# the settings.
-			save=( "${CTRL_RESULT#$DUT_CTRL_PREFIX}" "${save[@]}" )
-		   fi
-		   ;;
-		2) save=( "$1:$2" "${save[@]}" )
-		   ;;
-		*) die "${FUNCNAME[0]} failed: arguments error"
-		   ;;
-	esac
-}
-
-function servo_save() {
-	local SERVO_VARS_NAME="${SERVO_TYPE}_VARS[@]"
-	for ctrl in "${!SERVO_VARS_NAME}"; do
-		servo_save_add "${ctrl}"
-	done
-
-	if [[ "${SERVO_TYPE}" == "servo_v2" ]]; then
-		servo_save_add "i2c_mux_en"
-		servo_save_add "i2c_mux"
-
-		dut_control i2c_mux_en:on
-		dut_control i2c_mux:remote_adc
-	fi
-}
-
-function servo_restore() {
-	info "Restoring servo settings..."
-	for ctrl in "${save[@]}"; do
-		if [[ -n "${ctrl}" ]]; then
-			dut_control "${ctrl}"
-		fi
-	done
-}
-
-function claim_pty() {
-	if grep -q cros_sdk /proc/1/cmdline; then
-		die "You must run this tool in a chroot that was entered with" \
-		    "'cros_sdk --no-ns-pid' (see crbug.com/444931 for details)"
-	fi
-
-	if [[ -z "$1" ]]; then
-		warn "No parameter passed to claim_pty()"
-		return
-	fi
-
-	# Disconnect the EC-3PO interpreter from the UART since it will
-	# interfere with flashing.
-	servo_save_add "${MCU}_ec3po_interp_connect"
-
-	dut_control ${MCU}_ec3po_interp_connect:off || \
-	    warn "hdctools cannot disconnect the EC-3PO interpreter from" \
-	    "the UART."
-
-	pids=$(lsof -FR 2>/dev/null -- $1 | grep -v '^f' | tr -d 'pR')
-	FROZEN_PIDS=""
-
-	# reverse order to SIGSTOP parents before children
-	for pid in $(echo ${pids} | tac -s " "); do
-		if ps -o cmd= "${pid}" | grep -qE "(servod|/sbin/init)"; then
-			info "Skip stopping servod or init: process ${pid}."
-		else
-			info "Sending SIGSTOP to process ${pid}!"
-			FROZEN_PIDS+=" ${pid}"
-			sleep 0.02
-			kill -STOP ${pid}
-		fi
-	done
-}
-
-# Returns the serialnumber of the specified servo.
-function get_serial() {
-	if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_servo_micro ]]; then
-		if [[ -z "${BOARD}" ]]; then
-			sn_ctl="servo_micro_"
-		elif [[ "$(dut_control_get "servo_micro_for_${BOARD}_serialname")" =~ \
-				"unknown" ]] ; then
-			# Fall back to servo_micro_ if S/N is uknown.
-			sn_ctl="servo_micro_"
-		else
-			sn_ctl="servo_micro_for_${BOARD}_"
-		fi
-	elif [[ "${SERVO_TYPE}" =~ "_with_ccd" ]] ; then
-		sn_ctl="ccd_"
-	else
-		# If it's none of the above, the main serialname will do.
-		sn_ctl=""
-	fi
-
-	dut_control_get "${sn_ctl}serialname"
-}
-
-function c2d2_wait_for_h1_power_on_or_reset() {
-	# Ensure we have the latest c2d2 fw and hdctools. This could
-	# be removed eventually (estimate removal 2020/06/01)
-	dut_control h1_vref_present || die "Need to kill servod and run:
-repo sync && sudo emerge hdctools servo-firmware && sudo servo_updater -b c2d2"
-
-	# Handle the case when flash_ec starts before DUT power is
-	# applied. Otherwise just use h1-level reset.
-	if [[ "$(dut_control_get h1_vref_present)" = "off" ]] ; then
-		info "Please attach C2D2 to DUT and power DUT now!"
-		# Waits ~40 seconds for Vref presence before timeout
-		local LOOP_COUNTER=100
-		while [[ "$(dut_control_get h1_vref_present)" = "off" \
-			&& "${LOOP_COUNTER}" -gt 1 ]] ; do
-			sleep 0.1
-			let LOOP_COUNTER=LOOP_COUNTER-1
-		done
-		# If we ran out of time, then just die now
-		if [[ "${LOOP_COUNTER}" -eq 1 ]] ; then
-			die "H1 Vref not present after waiting"
-		fi
-	else
-		# Ensure DUT is in clean state with H1 Reset
-		dut_control cold_reset:on
-		dut_control cold_reset:off
-	fi
-}
-
-# Board specific flashing scripts
-
-# helper function for using servo v2/3 with openocd
-function flash_openocd() {
-	OCD_CFG="servo.cfg"
-	if [[ -z "${EC_DIR}" ]]; then
-		# check if we're on beaglebone
-		if [[ -e "/usr/share/ec-devutils" ]]; then
-			OCD_PATH="/usr/share/ec-devutils"
-		else
-			die "Cannot locate openocd configs"
-		fi
-	else
-		OCD_PATH="${EC_DIR}/util/openocd"
-	fi
-
-	servo_save_add "jtag_buf_on_flex_en"
-	servo_save_add "jtag_buf_en"
-
-	dut_control jtag_buf_on_flex_en:on
-	dut_control jtag_buf_en:on
-
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-		openocd -s "${OCD_PATH}" -f "${OCD_CFG}" -f "${OCD_CHIP_CFG}" \
-		-c "${OCD_CMDS}" || \
-	die "Failed to program ${IMG}"
-}
-
-# helper function for using servo with flashrom
-function flash_flashrom() {
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH:/usr/sbin"
-	FLASHROM=$(PATH="${TOOL_PATH}" which flashrom)
-
-	if on_servov3; then
-		FLASHROM_ARGS="-p linux_spi"
-	elif on_raiden; then
-	    if [[ "${SERVO_TYPE}" =~ "servo_micro" ]]; then
-		# Servo micro doesn't use the "target" parameter.
-		FLASHROM_ARGS="-p raiden_debug_spi:"
-	    else
-		FLASHROM_ARGS="-p raiden_debug_spi:target=EC,"
-	    fi
-	else
-		FLASHROM_ARGS="-p ft2232_spi:type=google-servo-v2,port=B,"
-	fi
-
-	if [ ! -x "$FLASHROM" ]; then
-		die "no flashrom util found."
-	fi
-
-	if ! on_servov3; then
-		SERIALNAME=$(get_serial)
-		if [[ "$SERIALNAME" != "" ]] ; then
-			FLASHROM_ARGS+="serial=${SERIALNAME}"
-		fi
-	fi
-
-	if ! on_raiden || [[ "${SERVO_TYPE}" =~ "servo_micro" ]] ; then
-		if $(in_array "${BOARDS_SPI_1800MV[@]}" "${BOARD}"); then
-			SPI_VOLTAGE="pp1800"
-		elif [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
-			SPI_VOLTAGE="pp1800"
-		else
-			SPI_VOLTAGE="pp3300"
-		fi
-
-		dut_control cold_reset:on
-
-		# If spi flash is in npcx's ec, enable gang programer mode
-		if [[ "${CHIP}" == "npcx_int_spi" ]]; then
-			servo_save_add "fw_up" "off"
-
-			# Set GP_SEL# as low then start ec
-			dut_control fw_up:on
-			sleep 0.1
-			dut_control cold_reset:off
-		fi
-
-		# Enable SPI programming mode.
-		if [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
-			# Set hardware strap pin (GPG6) of SPI programming as low then start ec
-			dut_control fw_up:on
-			sleep 0.1
-			dut_control cold_reset:off
-			sleep 0.1
-			# We have to release the HW strap pin because it also SPI clock pin.
-			dut_control fw_up:off
-		fi
-
-		servo_save_add "spi1_vref" "off"
-		servo_save_add "spi1_buf_en" "off"
-
-		# Turn on SPI1 interface on servo for SPI Flash Chip
-		dut_control spi1_vref:${SPI_VOLTAGE} spi1_buf_en:on
-		if [[ ! "${SERVO_TYPE}" =~ "servo_micro" ]]; then
-			# Servo micro doesn't support this control.
-			servo_save_add "spi1_buf_on_flex_en" "off"
-			dut_control spi1_buf_on_flex_en:on
-		fi
-	else
-		if [[ "${CHIP}" == "npcx_int_spi" ]]; then
-			servo_save_add "fw_up" "off"
-
-			# Set GP_SEL# as low then start ec
-			dut_control cold_reset:on
-			dut_control fw_up:on
-			# sleep 0.1
-			dut_control cold_reset:off
-		else
-			# Assert EC reset.
-			dut_control cold_reset:on
-		fi
-
-		# Temp layout
-		L=/tmp/flash_spi_layout_$$
-		DELETE_LIST+=( "${L}" )
-
-		[[ -z "${FLAGS_read}" ]] && dump_fmap -F "${IMG}" > "${L}"
-
-		FLASHROM_OPTIONS="-i EC_RW -i WP_RO -l "${L}" --noverify-all"
-	fi
-
-	# Generate the correct flashrom command base.
-	FLASHROM_CMDLINE="${FLASHROM} ${FLASHROM_ARGS}"
-	if [[ -z "${FLAGS_read}" ]]; then
-		# Program EC image.
-		# flashrom should report the image size at the end of the output.
-		local FLASHROM_GETSIZE="sudo ${FLASHROM_CMDLINE} --flash-size"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_GETSIZE}" 1>&2
-		fi
-		SPI_SIZE=$(${FLASHROM_GETSIZE} | grep -oe '[0-9]\+$' |
-			   tail -n1) || die "Failed to determine chip size!"
-		[[ ${SPI_SIZE} -eq 0 ]] && die "Chip size is 0!"
-
-		PATCH_SIZE=$((${SPI_SIZE} - ${IMG_SIZE}))
-
-		# Temp image
-		T=/tmp/flash_spi_$$
-		DELETE_LIST+=( "${T}" )
-
-		if [[ "${CHIP}" =~ ^npcx(|_int)_spi$ ]] || \
-		   [[ "${CHIP}" =~ "ite_spi_ccd_i2c" ]] ||
-		   [[ "${CHIP}" =~ "ite_spi" ]] ; then
-		{	# Patch temp image up to SPI_SIZE
-			cat "$IMG"
-			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
-					tr '\0' '\377'
-			fi
-		} > $T
-		else
-		{	# Patch temp image up to SPI_SIZE
-			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
-					tr '\0' '\377'
-			fi
-			cat "$IMG"
-		} > $T
-		fi
-
-		info "Programming EC firmware image."
-		local FLASHROM_WRITE="${FLASHROM_CMDLINE} ${FLASHROM_OPTIONS}"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_WRITE} -w ${T}" 1>&2
-		fi
-		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_WRITE} -w "${T}" \
-			|| die "${MSG_PROGRAM_FAIL}"
-	else
-		# Read EC image.
-		info "Reading EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_CMDLINE} -r ${FLAGS_read}" 1>&2
-		fi
-		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_CMDLINE} -r "${FLAGS_read}" \
-			|| die "${MSG_READ_FAIL}"
-	fi
-}
-
-function flash_stm32() {
-	local STM32MON
-	local STM32MON_OPT
-
-	if ! servo_has_cold_reset; then
-		die "Cold reset must be available for STM32 programming"
-	fi
-
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	STM32MON=$(PATH="${TOOL_PATH}" which stm32mon)
-	EC_UART="$(servo_ec_uart)"
-	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
-	if [ ! -x "$STM32MON" ]; then
-		die "no stm32mon util found."
-	fi
-
-	info "Using serial flasher : ${STM32MON}"
-	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
-	STM32MON_OPT="-d ${EC_UART}"
-
-	# Make sure EC reboots in serial monitor mode.
-	ec_enable_boot0 "bitbang"
-
-	# Pulse EC reset.
-	ec_reset
-
-	if ! on_raiden && [[ "${SERVO_TYPE}" =~ "servo" ]] ; then
-		servo_save_add "${EC_UART_PREFIX}_en"
-
-		dut_control "${EC_UART_PREFIX}_en:on"
-	fi
-
-	servo_save_add "${EC_UART_PREFIX}_parity"
-
-	dut_control "${EC_UART_PREFIX}_parity:even"
-
-	if servo_is_ccd ; then
-		case "${FLAGS_bitbang_rate}" in
-			(9600|19200|38400|57600) : ;;
-			(*)
-			    die "${FLAGS_bitbang_rate} is not a valid" \
-			    "bit bang rate"
-			    ;;
-		esac
-		info "Programming at ${FLAGS_bitbang_rate} baud"
-
-		servo_save_add "${EC_UART_PREFIX}_baudrate"
-		servo_save_add "${EC_UART_PREFIX}_bitbang_en"
-
-		dut_control "${EC_UART_PREFIX}_baudrate:${FLAGS_bitbang_rate}"
-		dut_control "${EC_UART_PREFIX}_bitbang_en:on"
-	else
-		servo_save_add "${EC_UART_PREFIX}_baudrate"
-
-		dut_control "${EC_UART_PREFIX}_baudrate:115200"
-	fi
-
-	# Add a delay long enough for cr50 to update the ccdstate. Cr50 updates
-	# ccdstate once a second, so a 2 second delay should be safe.
-	if servo_is_ccd ; then
-		sleep 2
-		STM32MON_OPT+=" -c"
-	fi
-
-	if [ -n "${FLAGS_logfile}" ]; then
-		info "Saving log in ${FLAGS_logfile}"
-		STM32MON_OPT+=" -L ${FLAGS_logfile}"
-	fi
-
-	local IMG_READ="${FLAGS_read}"
-	# Program EC image.
-	if [[ -z "${IMG_READ}" ]]; then
-		info "Programming EC firmware image."
-		# Unprotect flash, erase, and write
-		local STM32MON_COMMAND="${STM32MON} ${STM32MON_OPT} -U -u -e -w"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_COMMAND} ${IMG}"
-		fi
-		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_COMMAND} "${IMG}" \
-			|| die "${MSG_PROGRAM_FAIL}"
-
-		# If it is a program-verify request, then make a temporary
-		# directory to store the image
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
-
-			IMG_READ="${TEMP_DIR}/ec.read.bin"
-			DELETE_LIST+=( "${TEMP_DIR}" )
-		fi
-	fi
-
-	# Read EC image.
-	if [[ -n "${IMG_READ}" ]]; then
-		info "Reading EC firmware image."
-		local STM32MON_READ_CMD="${STM32MON} ${STM32MON_OPT} -U -r"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_READ_CMD} ${IMG_READ}"
-		fi
-		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_READ_CMD} "${IMG_READ}" \
-			|| die "${MSG_READ_FAIL}"
-	fi
-
-	# Verify the flash by comparing the source image to the read image,
-	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-		info "Verifying EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
-		fi
-		cmp -s -n "${IMG_SIZE}" "${IMG}" "${IMG_READ}" \
-			|| die "${MSG_VERIFY_FAIL}"
-	fi
-
-	# Remove the Application processor reset
-	# TODO(crosbug.com/p/30738): we cannot rely on servo_VARS to restore it
-	if servo_has_warm_reset; then
-		dut_control warm_reset:off
-	fi
-}
-
-function flash_stm32_dfu() {
-	DFU_DEVICE=0483:df11
-	ADDR=0x08000000
-	DFU_UTIL='dfu-util'
-	which $DFU_UTIL &> /dev/null || die \
-		"no dfu-util util found.  Did you 'sudo emerge dfu-util'"
-
-	info "Using dfu flasher : ${DFU_UTIL}"
-
-	dev_cnt=$(lsusb -d $DFU_DEVICE | wc -l)
-	if [ $dev_cnt -eq 0 ] ; then
-		die "unable to locate dfu device at $DFU_DEVICE"
-	elif [ $dev_cnt -ne 1 ] ; then
-		die "too many dfu devices (${dev_cnt}). Disconnect all but one."
-	fi
-
-	SIZE=$(wc -c ${IMG} | cut -d' ' -f1)
-	# Remove read protection
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE}:force:unprotect -D "${IMG}"
-	# Wait for mass-erase and reboot after unprotection
-	print_or_run sleep 1
-	# Actual image flashing
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE} -D "${IMG}"
-}
-
-function dut_i2c_dev() {
-	if [ -n "$DUT_I2C_DEV" ]; then
-		[ -e "$DUT_I2C_DEV" ] ||
-			die "\$DUT_I2C_DEV is a non-existent path: $DUT_I2C_DEV"
-		echo "$DUT_I2C_DEV"
-		return
-	fi
-
-	local adap_num=
-	adap_num="$(dut_control_get_or_die \
-	    "${ACTIVE_DEVICE}_i2c_pseudo_adapter_num")"
-	echo /dev/i2c-"$adap_num"
-}
-
-function flash_it83xx() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local ITEFLASH_BIN=$(PATH="${TOOL_PATH}" which iteflash)
-
-	if [[ ! -x "$ITEFLASH_BIN" ]]; then
-		die "no iteflash util found."
-	fi
-
-	# We need to ensure that c2d2 and dut-side path are set up for i2c
-	if [[ "${SERVO_TYPE}" =~ "c2d2" ]]; then
-		c2d2_wait_for_h1_power_on_or_reset
-
-		# Don't let the EC come out of reset after H1 reset
-		dut_control ec_reset:on
-
-		# Enable i2c bus on C2D2 at 400kbps
-		servo_save_add "i2c_ec_bus_speed"
-		dut_control_or_die i2c_ec_bus_speed:400
-
-		# We need to swing the DUT-side muxes to I2C instead of UART.
-		# This is done by convention with EC_FLASH_SELECT pin from H1
-		dut_control_or_die ec_flash_select:on
-	fi
-
-	# Now the we have enabled the I2C mux on the servo to talk to the dut,
-	# we need to switch the I2C mux on the dut to allow ec programing (if
-	# there is a mux on the dut)
-	if servo_has_dut_i2c_mux; then
-		info "Switching DUT I2C Mux to ${CHIP}"
-		servo_save_add "dut_i2c_mux"
-		dut_control dut_i2c_mux:ec_prog
-	fi
-
-	# We need to send the special waveform very soon after the EC powers on
-	if [[ "${SERVO_TYPE}" =~ "c2d2" ]]; then
-		# The EC was held in reset above
-		dut_control ec_reset:off
-	elif servo_has_cold_reset; then
-		servo_ec_hard_reset_or_die
-	fi
-
-	# Send the special waveform to the ITE EC.
-	if [[ "${SERVO_TYPE}" =~ "servo_micro" || \
-	      "${SERVO_TYPE}" =~ "c2d2" ]] ; then
-		info "Asking servo to send the dbgr special waveform to ${CHIP}"
-		dut_control_or_die enable_ite_dfu
-	elif servo_is_ccd; then
-		local CCD_I2C_CAP="$(dut_control_get ccd_i2c_en)"
-		if [[ "${CCD_I2C_CAP,,}" != "always" ]]; then
-			die "CCD I2C capability is not set as 'Always'" \
-				": ${CCD_I2C_CAP}"
-		fi
-
-		info "Asking CR50 to send the dbgr special waveform to ${CHIP}"
-		sleep 2
-		dut_control_or_die cr50_i2c_ctrl:ite_debugger_mode
-		sleep 3
-	elif [[ "${SERVO_TYPE}" == "servo_v2" ]]; then
-		info "Closing servod connection to ftdi_i2c interface"
-		dut_control_or_die ftdii2c_cmd:close
-	else
-		die "This servo type is not yet supported: ${SERVO_TYPE}"
-	fi
-
-	# Build the iteflash command line.
-	local ITEFLASH_ARGS=( "${ITEFLASH_BIN}" )
-
-	if [[ "${SERVO_TYPE}" == "servo_v2" ]]; then
-		ITEFLASH_ARGS+=( "--send-waveform=1" "--i2c-interface=ftdi" )
-	else
-		ITEFLASH_ARGS=( "sudo" "--" "${ITEFLASH_ARGS[@]}" \
-			"--send-waveform=0" "--i2c-interface=linux" \
-			"--i2c-dev-path=$(dut_i2c_dev)" )
-		if servo_is_ccd; then
-			ITEFLASH_ARGS+=( "--block-write-size=256" )
-		fi
-	fi
-
-	local ERROR_MSG
-	if [[ -n "${FLAGS_read}" ]]; then
-		ITEFLASH_ARGS+=( "--read=${FLAGS_read}" )
-		info "Reading EC firmware image using iteflash..."
-		ERROR_MSG="${MSG_READ_FAIL}"
-	else
-		ITEFLASH_ARGS+=( "--erase" "--write=${IMG}" )
-		info "Programming EC firmware image using iteflash..."
-		ERROR_MSG="${MSG_PROGRAM_FAIL}"
-	fi
-
-	if [[ "${FLAGS_verify}" == "${FLAGS_FALSE}" ]]; then
-		ITEFLASH_ARGS+=( "--noverify" )
-	fi
-
-	if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-		ITEFLASH_ARGS+=( "--debug" )
-		echo "${ITEFLASH_ARGS[@]}"
-	fi
-
-	# Ensure the CR50 doesn't go into low power while flashing
-	# otherwise the DUT side muxes will get cut. Note this also needs to
-	# happen once the CR50 hooks have settled and H1 realizes that the
-	# "AP [is] Off", since that over writes the idle action with sleep.
-	if [[ "${SERVO_TYPE}" =~ "c2d2" ]]; then
-		dut_control cr50_idle_level:active
-	fi
-
-	print_or_run "${ITEFLASH_ARGS[@]}" || die "${ERROR_MSG}"
-}
-
-function flash_ite_spi() {
-	flash_flashrom
-}
-
-function flash_ite_spi_ccd_i2c() {
-	if [[ "${SERVO_TYPE}" =~ "servo_micro" || \
-	      "${SERVO_TYPE}" =~ "servo_v2" ]] ; then
-		flash_flashrom
-	else
-		flash_it83xx
-	fi
-}
-
-function flash_lm4() {
-	OCD_CHIP_CFG="lm4_chip.cfg"
-	OCD_CMDS="init; flash_lm4 ${IMG} ${FLAGS_offset}; shutdown;"
-
-	flash_openocd
-
-}
-
-function flash_nrf51() {
-	OCD_CHIP_CFG="nrf51_chip.cfg"
-	OCD_CMDS="init; flash_nrf51 ${IMG} ${FLAGS_offset}; exit_debug_mode_nrf51; shutdown;"
-
-	flash_openocd
-
-	# waiting 100us for the reset pulse is not necessary, it takes ~2.5ms
-	dut_control swd_reset:on swd_reset:off
-}
-
-function flash_npcx_jtag() {
-	IMG_PATH="${EC_DIR}/build/${BOARD}"
-	OCD_CHIP_CFG="npcx_chip.cfg"
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
-		# Program RO region only
-		OCD_CMDS="init; flash_npcx_ro ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;"
-	else
-		# Program all EC regions
-		OCD_CMDS="init; flash_npcx_all ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;"
-	fi
-
-	# Reset the EC
-	ec_reset
-
-	flash_openocd
-}
-
-function flash_npcx_uut() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local NPCX_UUT=$(PATH="${TOOL_PATH}" which uartupdatetool)
-	local EC_UART="$(servo_ec_uart)"
-
-	# Look for npcx_monitor.bin in multiple directories, starting with
-	# the same path as the EC binary.
-	local MON=""
-	for dir in \
-		"$(dirname "$IMG")/chip/npcx/spiflashfw" \
-		"$(dirname "$IMG")" \
-		"${EC_DIR}/build/${BOARD}/chip/npcx/spiflashfw" \
-		"${EC_DIR}/build/${ZEPHYR_DIR}/output" \
-		"$(dirname "$LOCAL_BUILD")" \
-		"$(dirname "$EMERGE_BUILD")" ;
-	do
-		if [ -f "$dir/npcx_monitor.bin" ] ; then
-			MON="$dir/npcx_monitor.bin"
-			break
-		fi
-	done
-	if [ -z "${MON}" ] ; then
-		echo "Failed to find npcx_monitor.bin"
-		exit 1
-	fi
-	info "Using NPCX image : ${MON}"
-
-	# The start address to restore monitor firmware binary
-	local MON_ADDR="0x200C3020"
-
-	if [ ! -x "$NPCX_UUT" ]; then
-		die "no NPCX UART Update Tool found."
-	fi
-
-	info "Using: NPCX UART Update Tool"
-	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
-
-	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
-		# Ti50 does not yet support ccd_keepalive option which
-		# requires ccdstate command on the GSC console.
-		# TODO(b/161483597) remove the check when Ti50 CCD is on par.
-		servo_save_add ccd_keepalive_en
-		dut_control ccd_keepalive_en:on
-	fi
-
-	# C2D2 does not use waits and has to ensure that the EC does not come
-	# out of reset after using a H1-level reset
-	if [[ "${SERVO_TYPE}" =~ "c2d2" ]] ; then
-		c2d2_wait_for_h1_power_on_or_reset
-
-		# Don't let the EC come out of reset after H1 reset
-		dut_control ec_reset:on
-
-		# Force the EC to boot in UART update mode coming out of reset
-		ec_enable_boot0 "uut"
-		dut_control ec_reset:off
-
-		# Ensure normal UART operation
-		ec_disable_boot0 "uut"
-	else
-		# Force the EC to boot in UART update mode
-		ec_enable_boot0 "uut"
-		ec_reset
-
-		# Have to wait a bit for EC boot-up
-		print_or_run sleep 0.1
-
-		# Ensure normal UART operation
-		ec_disable_boot0 "uut"
-		print_or_run sleep 0.1
-	fi
-
-	# Remove the prefix "/dev/" because uartupdatetool will add it.
-	local UUT_ARGS=( "--port=${EC_UART#/dev/}" " --baudrate=115200" )
-	local IMG_READ="${FLAGS_read}"
-
-	# Program EC image.
-	if [[ -z "${IMG_READ}" ]]; then
-		info "Loading monitor binary."
-		local UUT_MON=( "${NPCX_UUT}" "${UUT_ARGS[@]}"  \
-				"--opr=wr" "--addr=${MON_ADDR}" \
-				"--file=${MON}" )
-
-		# Load monitor binary to address 0x200C3020
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
-			echo "${UUT_MON[*]}"
-		fi
-		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			"${UUT_MON[@]}" || die "Failed to load monitor binary."
-
-		info "Programming EC firmware image."
-		local UUT_WR=( "${NPCX_UUT}" "${UUT_ARGS[@]}"      \
-			       "--auto" "--offset=${FLAGS_offset}" \
-			       "--file=${IMG}" )
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
-			echo "${UUT_WR[*]}"
-		fi
-		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			"${UUT_WR[@]}" || die "${MSG_PROGRAM_FAIL}"
-
-		# If it is a program-verify request, then make a temporary
-		# directory to store the image.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}.$$"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
-
-			IMG_READ="${TEMP_DIR}/ec.read.bin"
-			DELETE_LIST+=( "${TEMP_DIR}" )
-		fi
-	fi
-
-	# Read EC image.
-	if [[ -n "${IMG_READ}" ]]; then
-		info "Reading EC firmware image."
-
-		local UUT_RD=( "${NPCX_UUT}" "${UUT_ARGS[@]}"   \
-			      "--read-flash" "--file=${IMG_READ}" )
-
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${UUT_RD[*]}"
-		fi
-		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			"${UUT_RD[@]}" || die "${MSG_READ_FAIL}"
-	fi
-
-	# Verify the flash by comparing the source image to the read image,
-	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-		info "Verifying EC firmware image."
-
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
-		fi
-
-		print_or_run cmp -s -n "${IMG_SIZE}" "${IMG}" "${IMG_READ}" \
-			|| die "${MSG_VERIFY_FAIL}"
-	fi
-}
-
-function flash_npcx_5m5g_jtag() {
-	flash_npcx_jtag
-}
-
-function flash_npcx_5m6g_jtag() {
-	flash_npcx_jtag
-}
-
-function flash_npcx_7m6x_jtag() {
-	flash_npcx_jtag
-}
-
-function flash_npcx_7m7x_jtag() {
-	flash_npcx_jtag
-}
-
-function flash_npcx_spi() {
-	flash_flashrom
-}
-
-function flash_npcx_int_spi() {
-	flash_flashrom
-}
-
-function flash_mec1322() {
-	flash_flashrom
-}
-
-info "Using ${SERVO_TYPE}."
-
-# Only if it is a flash program request, call ec_image.
-if [[ -z "${FLAGS_read}" ]]; then
-	IMG="$(ec_image)"
-	info "Using ${MCU} image : ${IMG}"
-	IMG_SIZE=$(stat -c%s "${IMG}")
-fi
-
-if [ "${NEED_SERVO}" != "no" ] ; then
-	servo_save
-fi
-
-info "Flashing chip ${CHIP}."
-flash_${CHIP}
-info "Flashing done."
diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu
deleted file mode 100644
index 679478f1e2..0000000000
--- a/util/flash_fp_mcu
+++ /dev/null
@@ -1,750 +0,0 @@
-#!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-. /usr/share/misc/shflags
-
-readonly DEFAULT_RETRIES=${DEFAULT_RETRIES:-4}
-readonly STM32MON_CONNECT_RETRIES=${STM32MON_CONNECT_RETRIES:-6}
-readonly STM32MON_SERIAL_BAUDRATE=${STM32MON_SERIAL_BAUDRATE:-115200}
-
-DEFINE_boolean 'read' "${FLAGS_FALSE}" 'Read instead of write' 'r'
-# Both flash read and write protection are removed by default, but you
-# can optionally enable them (for testing purposes).
-DEFINE_boolean 'remove_flash_read_protect' "${FLAGS_TRUE}" \
-  'Remove flash read protection while performing command' 'U'
-DEFINE_boolean 'remove_flash_write_protect' "${FLAGS_TRUE}" \
-  'Remove flash write protection while performing command' 'u'
-DEFINE_integer 'retries' "${DEFAULT_RETRIES}" 'Specify number of retries' 'R'
-DEFINE_integer 'baudrate' "${STM32MON_SERIAL_BAUDRATE}" 'Specify UART baudrate' 'B'
-DEFINE_boolean 'hello' "${FLAGS_FALSE}" 'Only ping the bootloader' 'H'
-DEFINE_boolean 'services' "${FLAGS_TRUE}" \
-  'Stop and restart conflicting fingerprint services' 's'
-FLAGS_HELP="Usage: ${0} [flags] [ec.bin]"
-
-#        EXIT_SUCCESS=0
-#        EXIT_FAILURE=1
-#        EXIT_BASHBUILTIN=2
-readonly EXIT_ARGUMENT=3
-readonly EXIT_CONFIG=4
-readonly EXIT_PRECONDITION=5
-readonly EXIT_RUNTIME=6
-
-# Process commandline flags
-FLAGS "${@}" || exit "${EXIT_ARGUMENT}"
-eval set -- "${FLAGS_ARGV}"
-
-readonly CROS_EC_SPI_MODALIAS_STR="of:NcrfpTCgoogle,cros-ec-spi"
-
-readonly CROS_EC_UART_MODALIAS_STR="of:NcrfpTCgoogle,cros-ec-uart"
-
-klog() {
-  echo "flash_fp_mcu: $*" > /dev/kmsg
-}
-
-check_hardware_write_protect_disabled() {
-  local hardware_write_protect_state
-  if ! hardware_write_protect_state="$(crossystem wpsw_cur)"; then
-    echo "Failed to get hardware write protect status" >&2
-    exit "${EXIT_PRECONDITION}"
-  fi
-  if [[ "${hardware_write_protect_state}" != "0" ]]; then
-    echo "Please make sure hardware write protect is disabled."
-    echo "See https://www.chromium.org/chromium-os/firmware-porting-guide/firmware-ec-write-protection"
-    exit "${EXIT_PRECONDITION}"
-  fi
-}
-
-# Get the spiid for the fingerprint sensor based on the modalias
-# string: https://crbug.com/955117
-get_spiid() {
-  # TODO(b/179533783): Fix modalias on strongbad and remove this bypass.
-  if [[ -n "${DEVICEID}" ]]; then
-    echo "${DEVICEID}"
-    return 0
-  fi
-
-  for dev in /sys/bus/spi/devices/*; do
-    if [[ "$(cat "${dev}/modalias")" == "${CROS_EC_SPI_MODALIAS_STR}" ]]; then
-      basename "${dev}"
-      return 0
-    fi
-  done
-
-  return 1
-}
-
-# Get the uartid for the fingerprint sensor based on the modalias
-get_uartid() {
-  for dev in /sys/bus/serial/devices/*; do
-    if [ -f "${dev}/modalias" ]; then
-      if [[ "$(cat "${dev}/modalias")" == "${CROS_EC_UART_MODALIAS_STR}" ]]; then
-        basename "${dev}"
-        return 0
-      fi
-    fi
-  done
-
-  return 1
-}
-
-# Usage: gpio <unexport|export|in|out|0|1|get> <signal> [signal...]
-gpio() {
-  local cmd="$1"
-  shift
-
-  for signal in "$@"; do
-    case "${cmd}" in
-      unexport|export)
-        klog "Set gpio ${signal} to ${cmd}"
-        echo "${signal}" > "/sys/class/gpio/${cmd}"
-        ;;
-      in|out)
-        local direction="${cmd}"
-        klog "Set gpio ${signal} direction to ${direction}"
-        echo "${direction}" > "/sys/class/gpio/gpio${signal}/direction"
-        ;;
-      0|1)
-        local value="${cmd}"
-        klog "Set gpio ${signal} to ${value}"
-        echo "${value}" > "/sys/class/gpio/gpio${signal}/value"
-        ;;
-      get)
-        local value="${cmd}"
-        klog "Get gpio ${signal}"
-        cat "/sys/class/gpio/gpio${signal}/value"
-        ;;
-      *)
-        echo "Invalid gpio command: ${cmd}" >&2
-        exit "${EXIT_RUNTIME}"
-        ;;
-    esac
-  done
-}
-
-# Usage: warn_gpio <signal> <expected_value> <msg>
-warn_gpio() {
-  local signal=$1
-  local expected_value=$2
-  local msg=$3
-
-  local value
-  if ! value="$(gpio get "${signal}")"; then
-    echo "Error fetching gpio value ${signal}" >&2
-    exit "${EXIT_RUNTIME}"
-  fi
-
-  if [[ "${value}" != "${expected_value}" ]]; then
-    echo "${msg}" >&2
-    return 1
-  fi
-}
-
-# Taken verbatim from
-# https://chromium.googlesource.com/chromiumos/docs/+/master/lsb-release.md#shell
-# This should not be used by anything except get_platform_name.
-# See https://crbug.com/98462.
-lsbval() {
-  local key="$1"
-  local lsbfile="${2:-/etc/lsb-release}"
-
-  if ! echo "${key}" | grep -Eq '^[a-zA-Z0-9_]+$'; then
-    return 1
-  fi
-
-  sed -E -n -e \
-    "/^[[:space:]]*${key}[[:space:]]*=/{
-      s:^[^=]+=[[:space:]]*::
-      s:[[:space:]]+$::
-      p
-    }" "${lsbfile}"
-}
-
-# Get the underlying board (reference design) that we're running on (not the
-# FPMCU or sensor).
-# This may be an extended platform name, like nami-kernelnext, hatch-arc-r,
-# or hatch-borealis.
-get_platform_name() {
-  local platform_name
-
-  # We used to use "cros_config /identity platform-name", but that is specific
-  # to mosys and does not actually provide the board name in all cases.
-  # cros_config intentionally does not provide a way to get the board
-  # name: b/156650654.
-
-  # If there was a way to get the board name from cros_config, it's possible
-  # that it could fail in the following cases:
-  #
-  # 1) We're running on a non-unibuild device (the only one with FP is nocturne)
-  # 2) We're running on a proto device during bringup and the cros_config
-  #    settings haven't yet been setup.
-  #
-  # In all cases we can fall back to /etc/lsb-release. It's not recommended
-  # to do this, but we don't have any other options in this case.
-  echo "Getting platform name from /etc/lsb-release." 1>&2
-  platform_name="$(lsbval "CHROMEOS_RELEASE_BOARD")"
-  if [[ -z "${platform_name}" ]]; then
-    return 1
-  fi
-
-  echo "${platform_name}"
-}
-
-# Given a full platform name, extract the base platform.
-#
-# Tests are also run on modified images, like hatch-arc-r, hatch-borealis, or
-# hatch-kernelnext. These devices still have fingerprint and are expected to
-# pass tests. The full platform name reflects these modifications and might
-# be needed to apply an alternative configuration (kernelnext). Other modified
-# tests (arc-r) just need to default to the base platform config, which is
-# identified by this function.
-# See b/186697064.
-#
-# Examples:
-# * platform_base_name "hatch-kernelnext" --> "hatch"
-# * platform_base_name "hatch-arc-r"      --> "hatch"
-# * platform_base_name "hatch-borealis"   --> "hatch"
-# * platform_base_name "hatch"            --> "hatch"
-#
-# Usage: platform_base_name <platform_name>
-platform_base_name() {
-  local platform_name="$1"
-
-  # We remove any suffix starting at the first '-'.
-  echo "${platform_name%%-*}"
-}
-
-get_default_fw() {
-  local board
-  board="$(cros_config /fingerprint board)"
-
-  # If cros_config returns "", that is okay assuming there is only
-  # one firmware file on disk.
-
-  local -a fws
-  mapfile -t fws < <(find /opt/google/biod/fw -name "${board}*.bin")
-
-  if [[ "${#fws[@]}" -ne 1 ]]; then
-    return 1
-  fi
-
-  echo "${fws[0]}"
-}
-
-# Find processes that have the named file, active or deleted, open.
-#
-# Deleted files are important because unbinding/rebinding cros-ec
-# with biod/timberslide running will result in the processes holding open
-# a deleted version of the files. Issues can arise if the process continue
-# to interact with the deleted files (ex kernel panic) while the raw driver
-# is being used in flash_fp_mcu. The lsof and fuser tools can't seem to
-# identify usages of the deleted named file directly, without listing all
-# files. This takes a large amount out time on Chromebooks, thus we need this
-# custom search routine.
-#
-# Usage: proc_open_file [file_pattern]
-proc_open_file() {
-  local file_pattern="$1"
-
-  # Avoid overloading kernel max arguments with the number of file names.
-  local -a FDS=( /proc/*/fd/* )
-  xargs ls -l <<<"${FDS[*]}" 2>/dev/null | grep "${file_pattern}" | \
-    awk '{split($9,p,"/"); print "PID", p[3], "->", $11, $12}'
-  return "${PIPESTATUS[1]}"
-}
-
-flash_fp_mcu_stm32() {
-  local transport="${1}"
-  local device="${2}"
-  local gpio_nrst="${3}"
-  local gpio_boot0="${4}"
-  local gpio_pwren="${5}"
-  local file="${6}"
-  local deviceid
-
-  local stm32mon_flags="-p --retries ${STM32MON_CONNECT_RETRIES}"
-
-  if [[ "${transport}" == "UART" ]]; then
-    stm32mon_flags+=" --baudrate ${FLAGS_baudrate} --device ${device}"
-  else
-    stm32mon_flags+=" -s ${device}"
-  fi
-
-  if [[ "${FLAGS_hello}" -eq "${FLAGS_FALSE}" ]]; then
-    if [[ "${FLAGS_remove_flash_write_protect}" -eq "${FLAGS_TRUE}" ]]; then
-      stm32mon_flags+=" -u"
-    fi
-
-    if [[ "${FLAGS_remove_flash_read_protect}" -eq "${FLAGS_TRUE}" ]]; then
-      stm32mon_flags+=" -U"
-    fi
-
-    if [[ "${FLAGS_read}" -eq "${FLAGS_TRUE}" ]]; then
-      # Read from FPMCU to file
-      if [[ -e "${file}" ]]; then
-        echo "Output file already exists: ${file}"
-        return "${EXIT_PRECONDITION}"
-      fi
-      echo "# Reading to '${file}' over ${transport}"
-      stm32mon_flags+=" -r ${file}"
-    else
-      # Write to FPMCU from file
-      if [[ ! -f "${file}" ]]; then
-        echo "Invalid image file: ${file}"
-        return "${EXIT_PRECONDITION}"
-      fi
-      echo "# Flashing '${file}' over ${transport}"
-      stm32mon_flags+=" -e -w ${file}"
-    fi
-  else
-    echo "# Saying hello over ${transport}"
-  fi
-
-
-  check_hardware_write_protect_disabled
-
-  if [[ "${transport}" == "UART" ]]; then
-    if ! deviceid="$(get_uartid)"; then
-      echo "Unable to find FP sensor UART device: ${CROS_EC_UART_MODALIAS_STR}"
-      return "${EXIT_PRECONDITION}"
-    fi
-  else
-
-    if ! deviceid="$(get_spiid)"; then
-      echo "Unable to find FP sensor SPI device: ${CROS_EC_SPI_MODALIAS_STR}"
-      return "${EXIT_PRECONDITION}"
-    fi
-  fi
-
-  echo "Flashing ${transport} device ID: ${deviceid}"
-
-  # Remove cros_fp if present
-  klog "Unbinding cros-ec driver"
-  if [[ "${transport}" == "UART" ]]; then
-    echo "${deviceid}" > /sys/bus/serial/drivers/cros-ec-uart/unbind
-  else
-    echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/unbind
-  fi
-
-  # Configure the MCU Boot0 and NRST GPIOs
-  gpio export "${gpio_boot0}" "${gpio_nrst}"
-  gpio out    "${gpio_boot0}" "${gpio_nrst}"
-
-  # Reset sequence to enter bootloader mode
-  gpio 1 "${gpio_boot0}"
-  gpio 0 "${gpio_nrst}"
-  sleep 0.001
-
-  klog "Binding raw driver"
-  if [[ "${transport}" == "UART" ]]; then
-    # load AMDI0020:01 ttyS1
-    echo AMDI0020:01 > /sys/bus/platform/drivers/dw-apb-uart/unbind;
-    echo AMDI0020:01 > /sys/bus/platform/drivers/dw-apb-uart/bind;
-  else
-    echo spidev > "/sys/bus/spi/devices/${deviceid}/driver_override"
-    echo "${deviceid}" > /sys/bus/spi/drivers/spidev/bind
-    # The following sleep is a workaround to mitigate the effects of a
-    # poorly behaved chip select line. See b/145023809.
-  fi
-  sleep 0.5
-
-  # We do not expect the drivers to change the pin state when binding.
-  # If you receive this warning, the driver needs to be fixed on this board
-  # and this flash attempt will probably fail.
-  warn_gpio "${gpio_boot0}" 1 \
-    "WARNING: One of the drivers changed BOOT0 pin state on bind attempt."
-  warn_gpio "${gpio_nrst}" 0 \
-    "WARNING: One of the drivers changed NRST pin state on bind attempt."
-
-  if [[ ! -c "${device}" ]]; then
-    echo "Failed to bind raw device driver." >&2
-    return "${EXIT_RUNTIME}"
-  fi
-
-  local attempt=0
-  local cmd_exit_status=1
-  local cmd="stm32mon ${stm32mon_flags}"
-
-  for attempt in $(seq "${FLAGS_retries}"); do
-    # Reset sequence to enter bootloader mode
-    gpio 0 "${gpio_nrst}"
-    sleep 0.01
-
-    # Release reset as the SPI bus is now ready
-    gpio 1 "${gpio_nrst}"
-
-    # As per section '68: Bootloader timings' from application note below:
-    # https://www.st.com/resource/en/application_note/cd00167594-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.pdf
-    # bootloader startup time is 16.63 ms for STM32F74xxx/75xxx and 53.975 ms
-    # for STM32H74xxx/75xxx. SPI needs 1 us delay for one SPI byte sending.
-    # Keeping some margin, add delay of 100 ms to consider minimum bootloader
-    # startup time after the reset for stm32 devices.
-    sleep 0.1
-
-    # Print out the actual underlying command we're running and run it
-    echo "# ${cmd}"
-    ${cmd}
-    cmd_exit_status=$?
-
-    if [[ "${cmd_exit_status}" -eq 0 ]]; then
-      break
-    fi
-    echo "# Attempt ${attempt} failed."
-    echo
-    sleep 1
-  done
-
-  # unload device
-  if [[ "${transport}" != "UART" ]]; then
-    klog "Unbinding raw driver"
-    echo "${deviceid}" > /sys/bus/spi/drivers/spidev/unbind
-  fi
-
-  # Go back to normal mode
-  gpio out "${gpio_nrst}"
-  gpio 0   "${gpio_boot0}" "${gpio_nrst}"
-  gpio 1   "${gpio_nrst}"
-
-  # Give up GPIO control, unless we need to keep these driving as
-  # outputs because they're not open-drain signals.
-  # TODO(b/179839337): Make this the default and properly support
-  # open-drain outputs on other platforms.
-  if [[ "${PLATFORM_NAME}" != "strongbad" ]] &&
-     [[ "${PLATFORM_NAME}" != "herobrine" ]]; then
-    gpio in       "${gpio_boot0}" "${gpio_nrst}"
-  fi
-  gpio unexport "${gpio_boot0}" "${gpio_nrst}"
-
-  # Dartmonkey's RO has a flashprotect logic issue that forces reboot loops
-  # when SW-WP is enabled and HW-WP is disabled. It is avoided if a POR is
-  # detected on boot. We force a POR here to ensure we avoid this reboot loop.
-  # See to b/146428434.
-  if [[ "${gpio_pwren}" -gt 0 ]]; then
-    echo "Power cycling the FPMCU."
-    gpio export "${gpio_pwren}"
-    gpio out    "${gpio_pwren}"
-    gpio 0      "${gpio_pwren}"
-    # Must outlast hardware soft start, which is typically ~3ms.
-    sleep 0.5
-    gpio 1      "${gpio_pwren}"
-    # Power enable line is externally pulled down, so leave as output-high.
-    gpio unexport "${gpio_pwren}"
-  fi
-
-  # Put back cros_fp driver if transport is SPI
-  if [[ "${transport}" != "UART" ]]; then
-    # wait for FP MCU to come back up (including RWSIG delay)
-    sleep 2
-    klog "Binding cros-ec driver"
-    echo "" > "/sys/bus/spi/devices/${deviceid}/driver_override"
-    echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/bind
-  fi
-
-  if [[ "${cmd_exit_status}" -ne 0 ]]; then
-    return "${EXIT_RUNTIME}"
-  fi
-
-  # Inform user to reboot if transport is UART.
-  # Display fw version is transport is SPI
-  if [[ "${transport}" == "UART" ]]; then
-    echo "Please reboot this device."
-  else
-    # Test it
-    klog "Query version and reset flags"
-    ectool --name=cros_fp version
-    ectool --name=cros_fp uptimeinfo
-  fi
-}
-
-config_hatch() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev1.1"
-  # See
-  # third_party/coreboot/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
-  # for pin name to number mapping.
-  # Examine `cat /sys/kernel/debug/pinctrl/INT34BB:00/gpio-ranges` on a hatch
-  # device to determine gpio number from pin number.
-  readonly GPIO_CHIP="gpiochip200"
-  # FPMCU RST_ODL is on GPP_A12 = 200 + 12 = 212
-  readonly GPIO_NRST=212
-  # FPMCU BOOT0 is on GPP_A22 = 200 + 22 = 222
-  readonly GPIO_BOOT0=222
-  # FP_PWR_EN is on GPP_C11 = 456 + (192 - 181) = 456 + 11 = 467
-  readonly GPIO_PWREN=467
-}
-
-config_herobrine() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev11.0"
-  # TODO(b/179533783): Fix this script to look for non-ACPI modalias
-  readonly DEVICEID="spi11.0"
-
-  readonly GPIO_CHIP="gpiochip336"
-  # FPMCU RST_ODL is $(gpiofind FP_RST_L) is gpiochip0 78
-  readonly GPIO_NRST=$((336 + $(gpiofind FP_RST_L|cut -f2 -d" ")))
-  # FPMCU BOOT0 is $(gpiofind FPMCU_BOOT0) is gpiochip0 77
-  readonly GPIO_BOOT0=$((336 + $(gpiofind FPMCU_BOOT0|cut -f2 -d" ")))
-  # EN FP RAILS is $(gpiofind EN_FP_RAILS) is gpiochip0 42
-  readonly GPIO_PWREN=$((336 + $(gpiofind EN_FP_RAILS|cut -f2 -d" ")))
-}
-
-config_nami() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev32765.0"
-
-  readonly GPIO_CHIP="gpiochip360"
-  # FPMCU RST_ODL is on GPP_C9 = 360 + 57 = 417
-  readonly GPIO_NRST=417
-  # FPMCU BOOT0 is on GPP_D5 = 360 + 77 = 437
-  readonly GPIO_BOOT0=437
-  # FP_PWR_EN is on GPP_B11 = 360 + 35 = 395
-  readonly GPIO_PWREN=395
-}
-
-config_nami-kernelnext() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev1.0"
-
-  readonly GPIO_CHIP="gpiochip360"
-  # FPMCU RST_ODL is on GPP_C9 = 360 + 57 = 417
-  readonly GPIO_NRST=417
-  # FPMCU BOOT0 is on GPP_D5 = 360 + 77 = 437
-  readonly GPIO_BOOT0=437
-  # FP_PWR_EN is on GPP_B11 = 360 + 35 = 395
-  readonly GPIO_PWREN=395
-}
-
-config_nocturne() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev32765.0"
-
-  readonly GPIO_CHIP="gpiochip360"
-  # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
-  readonly GPIO_NRST=418
-  # FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416
-  readonly GPIO_BOOT0=416
-  # FP_PWR_EN is on GPP_A11 = 360 + 11 = 371
-  readonly GPIO_PWREN=371
-}
-
-config_nocturne-kernelnext() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev1.0"
-
-  readonly GPIO_CHIP="gpiochip360"
-  # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
-  readonly GPIO_NRST=418
-  # FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416
-  readonly GPIO_BOOT0=416
-  # FP_PWR_EN is on GPP_A11 = 360 + 11 = 371
-  readonly GPIO_PWREN=371
-}
-
-config_strongbad() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev10.0"
-  # TODO(b/179533783): Fix modalias on strongbad and remove this bypass.
-  readonly DEVICEID="spi10.0"
-
-  readonly GPIO_CHIP="gpiochip392"
-  # FPMCU RST_ODL is $(gpiofind FP_RST_L) is gpiochip0 22
-  readonly GPIO_NRST=$((392 + $(gpiofind FP_RST_L|cut -f2 -d" ")))
-  # FPMCU BOOT0 is $(gpiofind FPMCU_BOOT0) is gpiochip0 10
-  readonly GPIO_BOOT0=$((392 + $(gpiofind FPMCU_BOOT0|cut -f2 -d" ")))
-  # TODO(b/179839337): Hardware currently doesn't support PWREN, but the
-  # next revision will. Add a comment here about the power enable gpio.
-  readonly GPIO_PWREN=-1
-}
-
-config_volteer() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev1.0"
-
-  # See kernel/v5.4/drivers/pinctrl/intel/pinctrl-tigerlake.c
-  # for pin name and pin number.
-  # Examine `cat /sys/kernel/debug/pinctrl/INT34C5:00/gpio-ranges` on a
-  # volteer device to determine gpio number from pin number.
-  # For example: GPP_C23 is UART2_CTS which can be queried from EDS
-  # the pin number is 194. From the gpio-ranges, the gpio value is
-  # 408 + (194-171) = 431
-
-  readonly GPIO_CHIP="gpiochip152"
-  # FPMCU RST_ODL is on GPP_C23 = 408 + (194 - 171) = 431
-  readonly GPIO_NRST=431
-  # FPMCU BOOT0 is on GPP_C22 = 408 + (193 - 171) = 430
-  readonly GPIO_BOOT0=430
-  # FP_PWR_EN is on GPP_A21 = 216 + (63 - 42) = 237
-  readonly GPIO_PWREN=237
-}
-
-config_brya() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev0.0"
-
-  # See kernel/v5.10/drivers/pinctrl/intel/pinctrl-tigerlake.c
-  # for pin name and pin number.
-  # Examine `cat /sys/kernel/debug/pinctrl/INTC1055:00/gpio-ranges` on a
-  # brya device to determine gpio number from pin number.
-  # For example: GPP_D1 is ISH_GP_1 which can be queried from EDS
-  # the pin number is 100 from the pinctrl-tigerlake.c.
-  # From the gpio-ranges, the gpio value is 312 + (100-99) = 313
-
-  readonly GPIO_CHIP="gpiochip152"
-  # FPMCU RST_ODL is on GPP_D1 = 312 + (100 - 99) = 313
-  readonly GPIO_NRST=313
-  # FPMCU BOOT0 is on GPP_D0 = 312 + (99 - 99) = 312
-  readonly GPIO_BOOT0=312
-  # FP_PWR_EN is on GPP_D2 = 312 + (101 - 99) = 314
-  readonly GPIO_PWREN=314
-}
-
-config_zork() {
-  readonly TRANSPORT="UART"
-  readonly DEVICE="/dev/ttyS1"
-
-  readonly GPIO_CHIP="gpiochip256"
-  # FPMCU RST_ODL is on AGPIO 11 = 256 + 11 = 267
-  readonly GPIO_NRST=267
-  # FPMCU BOOT0 is on AGPIO 69 = 256 + 69 = 325
-  readonly GPIO_BOOT0=325
-  # FPMCU PWR_EN is on AGPIO 32 = 256 + 32 = 288, but should not be
-  # necessary for flashing. Set invalid value.
-  readonly GPIO_PWREN=-1
-}
-
-config_guybrush() {
-  readonly TRANSPORT="UART"
-
-  readonly DEVICE="/dev/ttyS1"
-
-  readonly GPIO_CHIP="gpiochip256"
-  # FPMCU RST_ODL is on AGPIO 11 = 256 + 11 = 267
-  readonly GPIO_NRST=267
-  # FPMCU BOOT0 is on AGPIO 144 = 256 + 144 = 400
-  readonly GPIO_BOOT0=400
-  # FPMCU PWR_EN is on AGPIO 32 = 256 + 32 = 288, but should not be
-  # necessary for flashing. Set invalid value.
-  readonly GPIO_PWREN=-1
-}
-
-main() {
-  local filename="$1"
-
-  # print out canonical path to differentiate between /usr/local/bin and
-  # /usr/bin installs
-  readlink -f "$0"
-
-  # The "platform name" corresponds to the underlying board (reference design)
-  # that we're running on (not the FPMCU or sensor). At the moment all of the
-  # reference designs use the same GPIOs. If for some reason a design differs in
-  # the future, we will want to add a nested check in the config_<platform_name>
-  # function. Doing it in this manner allows us to reduce the number of
-  # configurations that we have to maintain (and reduces the amount of testing
-  # if we're only updating a specific config_<platform_name>).
-  if ! PLATFORM_NAME="$(get_platform_name)"; then
-    echo "Failed to get platform name"
-    exit "${EXIT_CONFIG}"
-  fi
-  readonly PLATFORM_NAME
-
-  if ! PLATFORM_BASE_NAME="$(platform_base_name "${PLATFORM_NAME}")"; then
-    echo "Failed to get platform base name"
-    exit "${EXIT_CONFIG}"
-  fi
-  readonly PLATFORM_BASE_NAME
-
-  echo "Platform name is ${PLATFORM_NAME} (${PLATFORM_BASE_NAME})."
-
-  # Check that the config function exists
-  if [[ "$(type -t "config_${PLATFORM_NAME}")" == "function" ]]; then
-    readonly PLATFORM_CONFIG="${PLATFORM_NAME}"
-  elif [[ "$(type -t "config_${PLATFORM_BASE_NAME}")" == "function" ]]; then
-    readonly PLATFORM_CONFIG="${PLATFORM_BASE_NAME}"
-  else
-    echo "No config for platform ${PLATFORM_NAME}." >&2
-    exit "${EXIT_CONFIG}"
-  fi
-
-  echo "Using config for ${PLATFORM_CONFIG}."
-
-  if ! "config_${PLATFORM_CONFIG}"; then
-    echo "Configuration failed for platform ${PLATFORM_CONFIG}." >&2
-    exit "${EXIT_CONFIG}"
-  fi
-
-  # Help the user out with defaults, if no *file* was given.
-  if [[ "$#" -eq 0 ]]; then
-    # If we are actually reading, set to a timestamped temp file.
-    if [[ "${FLAGS_read}" -eq "${FLAGS_TRUE}" ]]; then
-      filename="/tmp/fpmcu-fw-$(date --iso-8601=seconds).bin"
-    else
-      # Assume we are "writing" the default firmware to the FPMCU.
-      if ! filename="$(get_default_fw)"; then
-        echo "Failed to identify a default firmware file" >&2
-        exit "${EXIT_CONFIG}"
-      fi
-    fi
-  fi
-
-  # Check that the gpiochip exists
-  if [[ ! -e "/sys/class/gpio/${GPIO_CHIP}" ]]; then
-    echo "Cannot find GPIO chip: ${GPIO_CHIP}"
-    exit "${EXIT_CONFIG}"
-  fi
-
-  if [[ "${FLAGS_services}" -eq "${FLAGS_TRUE}" ]]; then
-    echo "# Stopping biod and timberslide"
-    stop biod
-    stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
-  fi
-
-  # If cros-ec driver isn't bound on startup, this means the final rebinding
-  # may fail.
-  if [[ ! -c "/dev/cros_fp" ]]; then
-    echo "WARNING: The cros-ec driver was not bound on startup." >&2
-  fi
-  if [[ -c "${DEVICE}" ]]; then
-    echo "WARNING: The raw driver was bound on startup." >&2
-  fi
-  local files_open
-  # Ensure no processes have cros_fp device or debug device open.
-  # This might be biod and/or timberslide.
-  if files_open=$(proc_open_file "/dev/cros_fp\|/sys/kernel/debug/cros_fp/*")
-  then
-    echo "WARNING: Another process has a cros_fp device file open." >&2
-    echo "${files_open}" >&2
-    echo "Try 'stop biod' and" >&2
-    echo "'stop timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log'" >&2
-    echo "before running this script." >&2
-    echo "See b/188985272." >&2
-  fi
-  # Ensure no processes are using the raw driver. This might be a wedged
-  # stm32mon process spawned by this script.
-  if files_open=$(proc_open_file "${DEVICE}"); then
-    echo "WARNING: Another process has ${DEVICE} open." >&2
-    echo "${files_open}" >&2
-    echo "Try 'fuser -k ${DEVICE}' before running this script." >&2
-    echo "See b/188985272." >&2
-  fi
-
-  local ret
-  flash_fp_mcu_stm32 \
-    "${TRANSPORT}"   \
-    "${DEVICE}"      \
-    "${GPIO_NRST}"   \
-    "${GPIO_BOOT0}"  \
-    "${GPIO_PWREN}"  \
-    "${filename}"
-  ret=$?
-
-  if [[ "${FLAGS_services}" -eq "${FLAGS_TRUE}" ]]; then
-    echo "# Restarting biod and timberslide"
-    start timberslide LOG_PATH=/sys/kernel/debug/cros_fp/console_log
-    start biod
-  fi
-
-  exit "${ret}"
-}
-
-main "$@"
diff --git a/util/flash_jlink.py b/util/flash_jlink.py
deleted file mode 100755
index d2fd4dec15..0000000000
--- a/util/flash_jlink.py
+++ /dev/null
@@ -1,208 +0,0 @@
-#!/usr/bin/env python3
-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Flashes firmware using Segger J-Link.
-
-This script requires Segger hardware attached via JTAG/SWD.
-
-See
-https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-debugging.md#flash
-for instructions.
-"""
-
-import argparse
-import logging
-import os
-import shutil
-import socket
-import subprocess
-import sys
-import tempfile
-import time
-
-
-DEFAULT_SEGGER_REMOTE_PORT = 19020
-
-# Commands are documented here: https://wiki.segger.com/J-Link_Commander
-JLINK_COMMANDS = '''
-exitonerror 1
-r
-loadfile {FIRMWARE} {FLASH_ADDRESS}
-r
-go
-exit
-'''
-
-
-class BoardConfig:
-    def __init__(self, interface, device, flash_address):
-        self.interface = interface
-        self.device = device
-        self.flash_address = flash_address
-
-
-SWD_INTERFACE = 'SWD'
-STM32_DEFAULT_FLASH_ADDRESS = '0x8000000'
-DRAGONCLAW_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32F412CG',
-                                flash_address=STM32_DEFAULT_FLASH_ADDRESS)
-ICETOWER_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32H743ZI',
-                              flash_address=STM32_DEFAULT_FLASH_ADDRESS)
-
-BOARD_CONFIGS = {
-    'dragonclaw': DRAGONCLAW_CONFIG,
-    'bloonchipper': DRAGONCLAW_CONFIG,
-    'nucleo-f412zg': DRAGONCLAW_CONFIG,
-    'dartmonkey': ICETOWER_CONFIG,
-    'icetower': ICETOWER_CONFIG,
-    'nucleo-dartmonkey': ICETOWER_CONFIG,
-    'nucleo-h743zi': ICETOWER_CONFIG,
-}
-
-
-def is_tcp_port_open(host: str, tcp_port: int) -> bool:
-    """Checks if the TCP host port is open."""
-
-    sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
-    sock.settimeout(2)  # 2 Second Timeout
-    try:
-        sock.connect((host, tcp_port))
-        sock.shutdown(socket.SHUT_RDWR)
-    except ConnectionRefusedError:
-        return False
-    except socket.timeout:
-        return False
-    finally:
-        sock.close()
-    # Other errors are propagated as odd exceptions.
-
-    # We shutdown and closed the connection, but the server may need a second
-    # to start listening again. If the following error is seen, this timeout
-    # should be increased. 300ms seems to be the minimum.
-    #
-    # Connecting to J-Link via IP...FAILED: Can not connect to J-Link via \
-    #   TCP/IP (127.0.0.1, port 19020)
-    time.sleep(0.5)
-    return True
-
-
-def create_jlink_command_file(firmware_file, config):
-    tmp = tempfile.NamedTemporaryFile()
-    tmp.write(JLINK_COMMANDS.format(FIRMWARE=firmware_file,
-                                    FLASH_ADDRESS=config.flash_address).encode(
-        'utf-8'))
-    tmp.flush()
-    return tmp
-
-
-def flash(jlink_exe, remote, device, interface, cmd_file):
-    cmd = [
-        jlink_exe,
-    ]
-
-    if remote:
-        logging.debug(f'Connecting to J-Link over TCP/IP {remote}.')
-        remote_components = remote.split(':')
-        if len(remote_components) not in [1, 2]:
-            logging.debug(f'Given remote "{remote}" is malformed.')
-            return 1
-
-        host = remote_components[0]
-        try:
-            ip = socket.gethostbyname(host)
-        except socket.gaierror as e:
-            logging.error(f'Failed to resolve host "{host}": {e}.')
-            return 1
-        logging.debug(f'Resolved {host} as {ip}.')
-        port = DEFAULT_SEGGER_REMOTE_PORT
-
-        if len(remote_components) == 2:
-            try:
-                port = int(remote_components[1])
-            except ValueError:
-                logging.error(
-                    f'Given remote port "{remote_components[1]}" is malformed.')
-                return 1
-
-        remote = f'{ip}:{port}'
-
-        logging.debug(f'Checking connection to {remote}.')
-        if not is_tcp_port_open(ip, port):
-            logging.error(
-                f'JLink server doesn\'t seem to be listening on {remote}.')
-            logging.error('Ensure that JLinkRemoteServerCLExe is running.')
-            return 1
-        cmd.extend(['-ip', remote])
-
-    cmd.extend([
-        '-device', device,
-        '-if', interface,
-        '-speed', 'auto',
-        '-autoconnect', '1',
-        '-CommandFile', cmd_file,
-        ])
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)
-    logging.debug('JLink return code: %d', completed_process.returncode)
-    return completed_process.returncode
-
-
-def main(argv: list):
-
-    parser = argparse.ArgumentParser()
-
-    default_jlink = './JLink_Linux_V684a_x86_64/JLinkExe'
-    if shutil.which(default_jlink) is None:
-        default_jlink = 'JLinkExe'
-    parser.add_argument(
-        '--jlink', '-j',
-        help='JLinkExe path (default: ' + default_jlink + ')',
-        default=default_jlink)
-
-    parser.add_argument(
-        '--remote', '-n',
-        help='Use TCP/IP host[:port] to connect to a J-Link or '
-        'JLinkRemoteServerCLExe. If unspecified, connect over USB.')
-
-    default_board = 'bloonchipper'
-    parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
-
-    default_firmware = os.path.join('./build', default_board, 'ec.bin')
-    parser.add_argument(
-        '--image', '-i',
-        help='Firmware binary (default: ' + default_firmware + ')',
-        default=default_firmware)
-
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
-    parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
-    )
-
-    args = parser.parse_args(argv)
-    logging.basicConfig(level=args.log_level)
-
-    if args.board not in BOARD_CONFIGS:
-        logging.error('Unable to find a config for board: "%s"', args.board)
-        sys.exit(1)
-
-    config = BOARD_CONFIGS[args.board]
-
-    args.image = os.path.realpath(args.image)
-    args.jlink = args.jlink
-
-    cmd_file = create_jlink_command_file(args.image, config)
-    ret_code = flash(args.jlink, args.remote, config.device, config.interface,
-                     cmd_file.name)
-    cmd_file.close()
-    return ret_code
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/util/fptool.py b/util/fptool.py
deleted file mode 100755
index 9c59c1014c..0000000000
--- a/util/fptool.py
+++ /dev/null
@@ -1,56 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""A tool to manage the fingerprint system on Chrome OS."""
-
-import argparse
-import os
-import shutil
-import subprocess
-import sys
-
-
-def cmd_flash(args: argparse.Namespace) -> int:
-    """
-    Flash the entire firmware FPMCU using the native bootloader.
-
-    This requires the Chromebook to be in dev mode with hardware write protect
-    disabled.
-    """
-
-    if not shutil.which('flash_fp_mcu'):
-        print('Error - The flash_fp_mcu utility does not exist.')
-        return 1
-
-    cmd = ['flash_fp_mcu']
-    if args.image:
-        if not os.path.isfile(args.image):
-            print(f'Error - image {args.image} is not a file.')
-            return 1
-        cmd.append(args.image)
-
-    print(f'Running {" ".join(cmd)}.')
-    sys.stdout.flush()
-    p = subprocess.run(cmd)
-    return p.returncode
-
-
-def main(argv: list) -> int:
-    parser = argparse.ArgumentParser(description=__doc__)
-    subparsers = parser.add_subparsers(dest='subcommand', title='subcommands')
-    # This method of setting required is more compatible with older python.
-    subparsers.required = True
-
-    # Parser for "flash" subcommand.
-    parser_decrypt = subparsers.add_parser('flash', help=cmd_flash.__doc__)
-    parser_decrypt.add_argument(
-        'image', nargs='?', help='Path to the firmware image')
-    parser_decrypt.set_defaults(func=cmd_flash)
-    opts = parser.parse_args(argv)
-    return opts.func(opts)
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/util/gdbinit b/util/gdbinit
deleted file mode 100644
index ff71e4c39c..0000000000
--- a/util/gdbinit
+++ /dev/null
@@ -1,219 +0,0 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# This file is intended to be used as a .gdbinit for an EC debugging session.
-# It defines some useful functions for analyzing the EC state.
-#
-# Setup Automatic Import:
-# ln -s util/gdbinit .gdbinit
-#
-# Environment Variables:
-# BOARD=[nocturne_fp|bloonchipper|...]
-# GDBSERVER=[segger|openocd]
-# GDBPORT=[gdb-server-port-number]
-#
-# Warning, this is a working collection that is not guaranteed to function
-# properly on all platforms. The ec-tasks functions is a good example of a
-# function that works well on most simple platforms, but may have issues on
-# platforms with data cache enabled.
-#
-# Note, this file must maintain space indention to allow easy copy/paste
-# while in active debugging. Using tabs interferes with the embedded python
-# during copy/paste.
-
-#####################################################################
-# Environment Setup and Initialization                              #
-#####################################################################
-
-set verbose on
-
-# Start of python code
-
-# Setup environment and pull in object files for the particular BOARD.
-# This requires setting the environment variables mentioned above.
-python
-import distutils.util
-import os
-
-BOARD = os.getenv('BOARD', '')
-GDBSERVER = os.getenv('GDBSERVER', 'openocd')
-USING_CLION = distutils.util.strtobool(os.getenv('USING_CLION', 'FALSE'))
-# BIN_NAME can be changed to be the name of a unit test, such as "sha256"
-BIN_NAME = os.getenv('BIN_NAME', 'ec')
-
-BIN_DIR = ''
-if BIN_NAME != 'ec':
-  BIN_DIR = BIN_NAME
-
-if GDBSERVER == "openocd":
-    DEFAULT_GDB_PORT = '3333'
-else:
-    DEFAULT_GDB_PORT = '2331'
-
-GDBPORT = os.getenv('GDBPORT', DEFAULT_GDB_PORT)
-
-EC_DIR = os.getenv('EC_DIR', os.path.join(os.getenv('HOME'),
-                   'chromiumos/src/platform/ec'))
-
-if not os.path.isdir(EC_DIR):
-    print('Error - EC_DIR "' + EC_DIR + '" doesn\'t exist. Aborting.')
-    gdb.execute('quit')
-
-# Monitor commands must be run after connecting to the remote target
-# See https://stackoverflow.com/a/39828850
-# https://youtrack.jetbrains.com/issue/CPP-7322
-# https://sourceware.org/gdb/onlinedocs/gdb/Hooks.html
-post_remote_hook='''
-define target hookpost-remote
-    echo \ Flashing EC binary
-    load {EC_DIR}/build/{BOARD}/{BIN_DIR}/{BIN_NAME}.obj
-    echo \ Resetting target
-    monitor reset
-    echo \ Setting breakpoint on main
-    b main
-end\n
-'''.format(BOARD=BOARD, EC_DIR=EC_DIR, BIN_DIR=BIN_DIR, BIN_NAME=BIN_NAME)
-
-gdb.execute('set $BOARD = "%s"'%BOARD)
-gdb.execute('set $GDBSERVER = "%s"'%GDBSERVER)
-gdb.execute('set $GDBPORT = "%s"'%GDBPORT)
-
-build = os.path.join(EC_DIR, 'build', BOARD)
-if BOARD != "":
-    if not os.path.isdir(build):
-        print('Error - Build path "' + build + '" doesn\'t exist. Aborting.')
-        gdb.execute('quit')
-
-    # When using gdb from CLion, this kills gdb.
-    if not USING_CLION:
-        gdb.execute('file ' + os.path.join(build, 'ec.obj'))
-    gdb.execute('add-symbol-file ' + os.path.join(build, BIN_DIR, 'RO', BIN_NAME + '.RO.elf'))
-    gdb.execute('add-symbol-file ' + os.path.join(build, BIN_DIR, 'RW', BIN_NAME + '.RW.elf'))
-
-if GDBSERVER == "openocd":
-    gdb.execute('set $GDBSERVER_OPENOCD = 1')
-    gdb.execute('set $GDBSERVER_SEGGER = 0')
-elif GDBSERVER == "segger":
-    gdb.execute('set $GDBSERVER_OPENOCD = 0')
-    gdb.execute('set $GDBSERVER_SEGGER = 1')
-    gdb.execute(post_remote_hook)
-else:
-    print('Error - GDBSERVER="' + GDBSERVER + '" is invalid.')
-    gdb.execute('quit')
-
-# End of python code
-end
-
-# OpenOCD specific config
-if $GDBSERVER_OPENOCD
-    # Don't auto choose hw/sw breakpoints from memory-map
-    set breakpoint auto-hw off
-end
-
-# Segger specific config
-if $GDBSERVER_SEGGER
-    # If enabled, disable flash breakpoints.
-    #monitor flash breakpoints = 0
-end
-
-# If enabled, force breakpoints to be inserted at all times.
-# They will not be reinserted on reconnects.
-#set breakpoint always-inserted on
-
-#####################################################################
-# Helper Functions                                                  #
-#####################################################################
-
-# Usage: ec-reg32 <address> [offset]
-# Read a 32 bit register
-define ec-reg32
-    set $a = $arg0
-    if $argc > 1
-        set $a += $arg1
-    end
-    set $v = *((uint32_t *)$a)
-    print $v
-    print /x $v
-    print /t $v
-end
-alias reg32 = ec-reg32
-
-# Usage: ec-connect
-# Issue the overly long target connect command using the
-# specified gdb server port.
-define ec-connect
-python
-# May want to only use "target remote".
-gdb.execute(f'target extended-remote :{GDBPORT}')
-end
-end
-alias connect = ec-connect
-
-# Usage: ec-reset
-# Issue the reset sequence for the debugger to halt on boot.
-define ec-reset
-    if $GDBSERVER_OPENOCD
-        monitor halt
-        monitor reset halt
-    else
-        monitor halt
-        monitor reset
-    end
-end
-alias reset = ec-reset
-
-# Usage: ec-tasks
-# Prints out information about current EC task set and tries to determine
-# if the task's stack has been overrun.
-# This function may not work properly if MCU data cache is enabled.
-define ec-tasks
-    set $taskid_cur = current_task - tasks
-    set $id = 0
-    set $taskcount = sizeof(tasks)/sizeof(tasks[0])
-    printf "Task Ready Name         Events      Time (s)  StkUsed\n"
-    while $id < $taskcount
-        set $is_ready = (tasks_ready & (1<<$id)) ? 'R' : ' '
-        set $unused = (uint32_t)0xdeadd00d
-        set $stacksize = tasks_init[$id].stack_size
-        set $stackused = $stacksize
-        set $s = tasks[$id].stack
-        while $s < (uint32_t *)tasks[$id].sp && *$s == $unused
-            set $stackused -= sizeof(uint32_t)
-            set $s++
-        end
-        printf "%4d %-5c %-16s %08x %11.6ld  %3d/%3d", $id, $is_ready,  task_names[$id], tasks[$id].events, tasks[$id].runtime, $stackused, tasks_init[$id].stack_size
-        if $stackused == $stacksize
-            printf "\t [overrun]"
-        end
-        if $id == $taskid_cur
-            printf "\t*"
-        end
-        printf "\n"
-        set $id++
-    end
-    if $taskid_cur == scratchpad
-        printf "Current task is set to scratchpad\n"
-    end
-end
-
-# Usage: ec-stayro
-# Adds magic breakpoint that changes the outcome of the RW signature
-# validation step that forces the MCU to stay in the RO section.
-# This function needs improvements to not be dependent on line numbers.
-define ec-stayro
-    break common/rwsig.c:282
-    commands
-        set evt = 1
-        printf "Continuing as RO\n"
-        continue
-    end
-end
-
-# Usage: ec-brexception
-# Set breakpoints on EC exception handlers.
-define ec-brexception
-    break exception_panic
-    break bus_fault_handler
-    break panic_assert_fail
-end
diff --git a/util/gen_emmc_transfer_data.c b/util/gen_emmc_transfer_data.c
deleted file mode 100644
index 98417beb9b..0000000000
--- a/util/gen_emmc_transfer_data.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Generate transferring data from a file. The transferring data emulates the
- * eMMC protocol.
- */
-
-#include <err.h>
-#include <errno.h>
-#include <getopt.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#include <compile_time_macros.h>
-
-/* eMMC transfer block size */
-#define BLOCK_SIZE		512
-#define BLOCK_RAW_DATA		"bootblock_raw_data"
-
-uint16_t crc16_arg(uint8_t data, uint16_t previous_crc)
-{
-	unsigned int crc = previous_crc << 8;
-	int i;
-
-	crc ^= (data << 16);
-	for (i = 8; i; i--) {
-		if (crc & 0x800000)
-			crc ^= (0x11021 << 7);
-		crc <<= 1;
-	}
-
-	return (uint16_t)(crc >> 8);
-}
-
-void header_format(FILE *fin, FILE *fout)
-{
-	uint8_t data[BLOCK_SIZE];
-	int blk, j;
-	uint16_t crc16;
-	size_t cnt = 0;
-
-	fprintf(fout, "/* This file is auto-generated. Do not modify. */\n"
-		"#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"#define __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"\n"
-		"#include <stdint.h>\n"
-		"\n"
-		);
-
-	fprintf(fout,
-		"static const uint8_t %s[] __attribute__((aligned(4))) =\n"
-		"{\n"
-		"\t0xff, 0x97, /* Acknowledge boot mode: 1 S=0 010 E=1 11 */\n"
-		"\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n",
-		BLOCK_RAW_DATA);
-
-	for (blk = 0;; blk++) {
-		crc16 = 0;
-		if (fin)
-			cnt = fread(data, 1, BLOCK_SIZE, fin);
-
-		if (cnt == 0)
-			break;
-		else if (cnt < BLOCK_SIZE)
-			memset(&data[cnt], 0xff, BLOCK_SIZE-cnt);
-
-		fprintf(fout, "\t/* Block %d (%ld) */\n", blk, cnt);
-		fprintf(fout, "\t0xff, 0xfe, /* idle, start bit. */");
-		for (j = 0; j < sizeof(data); j++) {
-			fprintf(fout, "%s0x%02x,",
-				(j % 8) == 0 ? "\n\t" : " ", data[j]);
-			crc16 = crc16_arg(data[j], crc16);
-		}
-		fprintf(fout, "\n");
-
-		fprintf(fout, "\t0x%02x, 0x%02x, 0xff,"
-			" /* CRC, end bit, idle */\n",
-			crc16 >> 8, crc16 & 0xff);
-	}
-
-	fprintf(fout, "\t/* Last block: idle */\n");
-	fprintf(fout, "\t0xff, 0xff, 0xff, 0xff\n");
-	fprintf(fout, "};\n");
-	fprintf(fout, "#endif /* __CROS_EC_BOOTBLOCK_DATA_H */\n");
-}
-
-int main(int argc, char **argv)
-{
-	int nopt;
-	int ret = 0;
-	const char *output_name = NULL;
-	char *input_name = NULL;
-	FILE *fin = NULL;
-	FILE *fout = NULL;
-
-	const char short_opts[] = "i:ho:";
-	const struct option long_opts[] = {
-		{ "input", 1, NULL, 'i' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
-	const char usage[] = "USAGE: %s [-i <input>] -o <output>\n";
-
-	while ((nopt = getopt_long(argc, argv, short_opts, long_opts,
-								NULL)) != -1) {
-		switch (nopt) {
-		case 'i': /* -i or --input*/
-			input_name = optarg;
-			break;
-		case 'h': /* -h or --help */
-			fprintf(stdout, usage, argv[0]);
-			return 0;
-		case 'o': /* -o or --out */
-			output_name = optarg;
-			break;
-		default: /* Invalid parameter. */
-			fprintf(stderr, usage, argv[0]);
-			return 1;
-		}
-	}
-
-	if (output_name == NULL) {
-		fprintf(stderr, usage, argv[0]);
-		return 1;
-	}
-
-	if (input_name == NULL) {
-		printf("No bootblock provided, outputting default file.\n");
-	} else {
-		fin = fopen(input_name, "r");
-		if (!fin) {
-			printf("Cannot open input file: %s\n", input_name);
-			ret = 1;
-			goto out;
-		}
-	}
-
-	fout = fopen(output_name, "w");
-
-	if (!fout) {
-		printf("Cannot open output file: %s\n", output_name);
-		ret = 1;
-		goto out;
-	}
-
-	header_format(fin, fout);
-
-	fclose(fout);
-
-out:
-	if (fin)
-		fclose(fin);
-
-	return ret;
-}
diff --git a/util/gen_ipi_table.c b/util/gen_ipi_table.c
deleted file mode 100644
index 07a3a39be0..0000000000
--- a/util/gen_ipi_table.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Generate IPI tables, and inputs come from IPI_COUNT macro in board.h.
- */
-
-#include <stdio.h>
-
-/* Prevent from including gpio configs . */
-#define __ASSEMBLER__
-
-#include "board.h"
-
-#define FPRINTF(format, args...) fprintf(fout, format, ## args)
-
-int main(int argc, char **argv)
-{
-	FILE *fout;
-	int i;
-
-	if (argc != 2) {
-		fprintf(stderr, "USAGE: %s <output>\n", argv[0]);
-		return 1;
-	}
-
-	fout = fopen(argv[1], "w");
-
-	if (!fout) {
-		fprintf(stderr, "Cannot open output file %s\n", argv[1]);
-		return 1;
-	}
-
-	FPRINTF("/* This is a generated file. Do not modify. */\n");
-	FPRINTF("\n");
-	FPRINTF("/*\n");
-	FPRINTF(" * Table to hold all the IPI handler function pointer.\n");
-	FPRINTF(" */\n");
-	FPRINTF("table(ipi_handler_t, ipi_handler_table,\n");
-
-	for (i = 0; i < IPI_COUNT; ++i)
-		FPRINTF("ipi_x_func(handler, ipi_arguments, %d)\n", i);
-
-	FPRINTF(");\n");
-
-	FPRINTF("/*\n");
-	FPRINTF(" * Table to hold all the wake-up bool address.\n");
-	FPRINTF(" */\n");
-	FPRINTF("table(int *, ipi_wakeup_table,\n");
-
-	for (i = 0; i < IPI_COUNT; ++i)
-		FPRINTF("ipi_x_var(wakeup, %d)\n", i);
-
-	FPRINTF(");\n");
-
-	fclose(fout);
-	return 0;
-}
diff --git a/util/gen_touchpad_hash.c b/util/gen_touchpad_hash.c
deleted file mode 100644
index e03c4638f3..0000000000
--- a/util/gen_touchpad_hash.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <err.h>
-#include <getopt.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <openssl/sha.h>
-
-#include "config.h"
-
-static void print_hex(FILE *out, uint8_t *digest, int len, int last)
-{
-	int i;
-
-	fputs("{ ", out);
-	for (i = 0; i < len; i++)
-		fprintf(out, "0x%02x, ", digest[i]);
-
-	fprintf(out, "}%c\n", last ? ';' : ',');
-}
-
-/* Output blank hashes */
-static int hash_fw_blank(FILE *hashes)
-{
-	uint8_t digest[SHA256_DIGEST_LENGTH] = { 0 };
-	int len;
-
-	fprintf(hashes, "const uint8_t touchpad_fw_hashes[%d][%d] = {\n",
-		CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE,
-		SHA256_DIGEST_LENGTH);
-	for (len = 0; len < CONFIG_TOUCHPAD_VIRTUAL_SIZE;
-				len += CONFIG_UPDATE_PDU_SIZE) {
-		print_hex(hashes, digest, sizeof(digest), 0);
-	}
-	fputs("};\n", hashes);
-
-	fprintf(hashes, "const uint8_t touchpad_fw_full_hash[%d] =\n\t",
-		SHA256_DIGEST_LENGTH);
-	print_hex(hashes, digest, SHA256_DIGEST_LENGTH, 1);
-
-	return 0;
-}
-
-static int hash_fw(FILE *tp_fw, FILE *hashes)
-{
-	uint8_t buffer[CONFIG_UPDATE_PDU_SIZE];
-	int len = 0;
-	int rb;
-	SHA256_CTX ctx;
-	SHA256_CTX ctx_all;
-	uint8_t digest[SHA256_DIGEST_LENGTH];
-
-	SHA256_Init(&ctx_all);
-	fprintf(hashes, "const uint8_t touchpad_fw_hashes[%d][%d] = {\n",
-		CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE,
-		SHA256_DIGEST_LENGTH);
-	while (1) {
-		rb = fread(buffer, 1, sizeof(buffer), tp_fw);
-		len += rb;
-
-		if (rb == 0)
-			break;
-
-		/* Calculate hash for the block. */
-		SHA256_Init(&ctx);
-		SHA256_Update(&ctx, buffer, rb);
-		SHA256_Final(digest, &ctx);
-
-		SHA256_Update(&ctx_all, buffer, rb);
-
-		print_hex(hashes, digest, sizeof(digest), 0);
-
-		if (rb < sizeof(buffer))
-			break;
-	}
-	fputs("};\n", hashes);
-
-	SHA256_Final(digest, &ctx_all);
-	fprintf(hashes, "const uint8_t touchpad_fw_full_hash[%d] =\n\t",
-		SHA256_DIGEST_LENGTH);
-	print_hex(hashes, digest, SHA256_DIGEST_LENGTH, 1);
-
-	if (!feof(tp_fw) || ferror(tp_fw)) {
-		warn("Error reading input file");
-		return 1;
-	}
-
-	if (len != CONFIG_TOUCHPAD_VIRTUAL_SIZE) {
-		warnx("Incorrect TP FW size (%d vs %d)", len,
-			CONFIG_TOUCHPAD_VIRTUAL_SIZE);
-		return 1;
-	}
-
-	return 0;
-}
-
-int main(int argc, char **argv)
-{
-	int nopt;
-	int ret;
-	const char *out = NULL;
-	char *tp_fw_name = NULL;
-	FILE *tp_fw = NULL;
-	FILE *hashes;
-	const char short_opt[] = "f:ho:";
-	const struct option long_opts[] = {
-		{ "firmware", 1, NULL, 'f' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
-	const char usage[] = "USAGE: %s -f <touchpad FW> -o <output file>\n";
-
-	while ((nopt = getopt_long(argc, argv, short_opt,
-						long_opts, NULL)) != -1) {
-		switch (nopt) {
-		case 'f': /* -f or --firmware */
-			tp_fw_name = optarg;
-			break;
-
-		case 'h': /* -h or --help */
-			fprintf(stdout, usage, argv[0]);
-			return 0;
-
-		case 'o': /* -o or --out */
-			out = optarg;
-			break;
-
-		default: /* Invalid parameter. */
-			fprintf(stderr, usage, argv[0]);
-			return 1;
-		}
-	};
-
-	if (out == NULL)
-		return 1;
-
-	hashes = fopen(out, "we");
-	if (!hashes)
-		err(1, "Cannot open output file");
-
-	fputs("#include <stdint.h>\n\n", hashes);
-	if (tp_fw_name) {
-		tp_fw = fopen(tp_fw_name, "re");
-
-		if (!tp_fw) {
-			warn("Cannot open firmware");
-			ret = 1;
-			goto out;
-		}
-
-		ret = hash_fw(tp_fw, hashes);
-
-		fclose(tp_fw);
-	} else {
-		printf("No touchpad FW provided, outputting blank hashes.\n");
-		ret = hash_fw_blank(hashes);
-	}
-
-out:
-	fclose(hashes);
-
-	/* In case of failure, remove output file. */
-	if (ret != 0)
-		unlink(out);
-
-	return ret;
-}
diff --git a/util/genvif.c b/util/genvif.c
deleted file mode 100644
index 6722df9349..0000000000
--- a/util/genvif.c
+++ /dev/null
@@ -1,3860 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define _GNU_SOURCE /* for asprintf */
-
-#include <errno.h>
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <getopt.h>
-#include <dirent.h>
-#include <limits.h>
-#include <ctype.h>
-
-#include "config.h"
-#include "usb_pd.h"
-#include "usb_pd_tcpm.h"
-#include "charge_manager.h"
-
-#include "genvif.h"
-
-#define VIF_APP_VENDOR_VALUE	"Google"
-#define VIF_APP_NAME_VALUE	"EC GENVIF"
-#define VIF_APP_VERSION_VALUE	"3.0.0.10"
-#define VENDOR_NAME_VALUE	"Google"
-
-#define DEFAULT_MISSING_TID	0xFFFF
-#define DEFAULT_MISSING_PID	0xFFFF
-#define DEFAULT_MISSING_BCD_DEV	0x0000
-
-const uint32_t *src_pdo;
-uint32_t src_pdo_cnt;
-
-struct vif_t vif;
-
-/*
- * local type to make decisions on the output for Source, Sink and DRP
- */
-enum dtype {
-	SRC = 0,
-	SNK,
-	DRP
-};
-
-enum ptype {
-	PORT_CONSUMER_ONLY = 0,
-	PORT_CONSUMER_PRODUCER = 1,
-	PORT_PRODUCER_CONSUMER = 2,
-	PORT_PROVIDER_ONLY = 3,
-	PORT_DRP = 4,
-	PORT_EMARKER = 5,
-};
-
-/*
- * Device_Speed options, defined in the VIF specification
- */
-enum usb_speed {
-	USB_2 = 0,
-	USB_GEN11 = 1,
-	USB_GEN21 = 2,
-	USB_GEN12 = 3,
-	USB_GEN22 = 4
-};
-
-/*
- * BC_1_2_SUPPORT options
- */
-enum bc_1_2_support {
-	BC_1_2_SUPPORT_NONE = 0,
-	BC_1_2_SUPPORT_PORTABLE_DEVICE = 1,
-	BC_1_2_SUPPORT_CHARGING_PORT = 2,
-	BC_1_2_SUPPORT_BOTH = 3
-};
-
-enum power_source {
-	POWER_EXTERNAL = 0,
-	POWER_UFP = 1,
-	POWER_BOTH = 2,
-};
-
-/*
- * index of component being set
- */
-int component_index;
-
-/*
- * TAG Name Strings
- */
-#define NAME_INIT(str) [str] = #str
-
-const char *vif_name[] = {
-	NAME_INIT(VIF_Specification),
-	NAME_INIT(Vendor_Name),
-	NAME_INIT(Model_Part_Number),
-	NAME_INIT(Product_Revision),
-	NAME_INIT(TID),
-	NAME_INIT(VIF_Product_Type),
-	NAME_INIT(Certification_Type),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_name) == VIF_Indexes);
-
-const char *vif_app_name[] = {
-	NAME_INIT(Vendor),
-	NAME_INIT(Name),
-	NAME_INIT(Version),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_app_name) == VIF_App_Indexes);
-
-const char *vif_component_name[] = {
-	NAME_INIT(Port_Label),
-	NAME_INIT(Connector_Type),
-	NAME_INIT(USB4_Supported),
-	NAME_INIT(USB_PD_Support),
-	NAME_INIT(PD_Port_Type),
-	NAME_INIT(Type_C_State_Machine),
-	NAME_INIT(Port_Battery_Powered),
-	NAME_INIT(BC_1_2_Support),
-	NAME_INIT(PD_Spec_Revision_Major),
-	NAME_INIT(PD_Spec_Revision_Minor),
-	NAME_INIT(PD_Spec_Version_Major),
-	NAME_INIT(PD_Spec_Version_Minor),
-	NAME_INIT(PD_Specification_Revision),
-	NAME_INIT(SOP_Capable),
-	NAME_INIT(SOP_P_Capable),
-	NAME_INIT(SOP_PP_Capable),
-	NAME_INIT(SOP_P_Debug_Capable),
-	NAME_INIT(SOP_PP_Debug_Capable),
-	NAME_INIT(Manufacturer_Info_Supported_Port),
-	NAME_INIT(Manufacturer_Info_VID_Port),
-	NAME_INIT(Manufacturer_Info_PID_Port),
-	NAME_INIT(USB_Comms_Capable),
-	NAME_INIT(DR_Swap_To_DFP_Supported),
-	NAME_INIT(DR_Swap_To_UFP_Supported),
-	NAME_INIT(Unconstrained_Power),
-	NAME_INIT(VCONN_Swap_To_On_Supported),
-	NAME_INIT(VCONN_Swap_To_Off_Supported),
-	NAME_INIT(Responds_To_Discov_SOP_UFP),
-	NAME_INIT(Responds_To_Discov_SOP_DFP),
-	NAME_INIT(Attempts_Discov_SOP),
-	NAME_INIT(Chunking_Implemented_SOP),
-	NAME_INIT(Unchunked_Extended_Messages_Supported),
-	NAME_INIT(Security_Msgs_Supported_SOP),
-	NAME_INIT(Num_Fixed_Batteries),
-	NAME_INIT(Num_Swappable_Battery_Slots),
-	NAME_INIT(ID_Header_Connector_Type_SOP),
-	NAME_INIT(Type_C_Can_Act_As_Host),
-	NAME_INIT(Type_C_Can_Act_As_Device),
-	NAME_INIT(Type_C_Implements_Try_SRC),
-	NAME_INIT(Type_C_Implements_Try_SNK),
-	NAME_INIT(Type_C_Supports_Audio_Accessory),
-	NAME_INIT(Type_C_Supports_VCONN_Powered_Accessory),
-	NAME_INIT(Type_C_Is_VCONN_Powered_Accessory),
-	NAME_INIT(Type_C_Is_Debug_Target_SRC),
-	NAME_INIT(Type_C_Is_Debug_Target_SNK),
-	NAME_INIT(Captive_Cable),
-	NAME_INIT(RP_Value),
-	NAME_INIT(Type_C_Port_On_Hub),
-	NAME_INIT(Type_C_Power_Source),
-	NAME_INIT(Type_C_Sources_VCONN),
-	NAME_INIT(Type_C_Is_Alt_Mode_Controller),
-	NAME_INIT(Type_C_Is_Alt_Mode_Adapter),
-	NAME_INIT(USB4_Router_Index),
-	NAME_INIT(USB4_Lane_0_Adapter),
-	NAME_INIT(USB4_Max_Speed),
-	NAME_INIT(USB4_DFP_Supported),
-	NAME_INIT(USB4_UFP_Supported),
-	NAME_INIT(USB4_USB3_Tunneling_Supported),
-	NAME_INIT(USB4_DP_Tunneling_Supported),
-	NAME_INIT(USB4_PCIe_Tunneling_Supported),
-	NAME_INIT(USB4_TBT3_Compatibility_Supported),
-	NAME_INIT(USB4_CL1_State_Supported),
-	NAME_INIT(USB4_CL2_State_Supported),
-	NAME_INIT(USB4_Num_Retimers),
-	NAME_INIT(USB4_DP_Bit_Rate),
-	NAME_INIT(USB4_Num_DP_Lanes),
-	NAME_INIT(Host_Supports_USB_Data),
-	NAME_INIT(Host_Speed),
-	NAME_INIT(Host_Contains_Captive_Retimer),
-	NAME_INIT(Host_Truncates_DP_For_tDHPResponse),
-	NAME_INIT(Host_Gen1x1_tLinkTurnaround),
-	NAME_INIT(Host_Gen2x1_tLinkTurnaround),
-	NAME_INIT(Host_Is_Embedded),
-	NAME_INIT(Host_Suspend_Supported),
-	NAME_INIT(Is_DFP_On_Hub),
-	NAME_INIT(Hub_Port_Number),
-	NAME_INIT(Device_Supports_USB_Data),
-	NAME_INIT(Device_Speed),
-	NAME_INIT(Device_Contains_Captive_Retimer),
-	NAME_INIT(Device_Truncates_DP_For_tDHPResponse),
-	NAME_INIT(Device_Gen1x1_tLinkTurnaround),
-	NAME_INIT(Device_Gen2x1_tLinkTurnaround),
-	NAME_INIT(BC_1_2_Charging_Port_Type),
-	NAME_INIT(PD_Power_As_Source),
-	NAME_INIT(USB_Suspend_May_Be_Cleared),
-	NAME_INIT(Sends_Pings),
-	NAME_INIT(Accepts_PR_Swap_As_Src),
-	NAME_INIT(Accepts_PR_Swap_As_Snk),
-	NAME_INIT(Requests_PR_Swap_As_Src),
-	NAME_INIT(Requests_PR_Swap_As_Snk),
-	NAME_INIT(FR_Swap_Supported_As_Initial_Sink),
-	NAME_INIT(FR_Swap_Type_C_Current_Capability_As_Initial_Sink),
-	NAME_INIT(FR_Swap_Reqd_Type_C_Current_As_Initial_Source),
-	NAME_INIT(Master_Port),
-	NAME_INIT(Num_Src_PDOs),
-	NAME_INIT(PD_OC_Protection),
-	NAME_INIT(PD_OCP_Method),
-	NAME_INIT(PD_Power_As_Sink),
-	NAME_INIT(No_USB_Suspend_May_Be_Set),
-	NAME_INIT(GiveBack_May_Be_Set),
-	NAME_INIT(Higher_Capability_Set),
-	NAME_INIT(Num_Snk_PDOs),
-	NAME_INIT(XID_SOP),
-	NAME_INIT(Data_Capable_As_USB_Host_SOP),
-	NAME_INIT(Data_Capable_As_USB_Device_SOP),
-	NAME_INIT(Product_Type_UFP_SOP),
-	NAME_INIT(Product_Type_DFP_SOP),
-	NAME_INIT(DFP_VDO_Port_Number),
-	NAME_INIT(Modal_Operation_Supported_SOP),
-	NAME_INIT(USB_VID_SOP),
-	NAME_INIT(PID_SOP),
-	NAME_INIT(bcdDevice_SOP),
-	NAME_INIT(SVID_Fixed_SOP),
-	NAME_INIT(Num_SVIDs_Min_SOP),
-	NAME_INIT(Num_SVIDs_Max_SOP),
-	NAME_INIT(AMA_HW_Vers),
-	NAME_INIT(AMA_FW_Vers),
-	NAME_INIT(AMA_VCONN_Reqd),
-	NAME_INIT(AMA_VCONN_Power),
-	NAME_INIT(AMA_VBUS_Reqd),
-	NAME_INIT(AMA_Superspeed_Support),
-	NAME_INIT(Product_Total_Source_Power_mW),
-	NAME_INIT(Port_Source_Power_Type),
-	NAME_INIT(Port_Source_Power_Gang),
-	NAME_INIT(Port_Source_Power_Gang_Max_Power),
-	NAME_INIT(XID),
-	NAME_INIT(Data_Capable_As_USB_Host),
-	NAME_INIT(Data_Capable_As_USB_Device),
-	NAME_INIT(Product_Type),
-	NAME_INIT(Modal_Operation_Supported),
-	NAME_INIT(USB_VID),
-	NAME_INIT(PID),
-	NAME_INIT(bcdDevice),
-	NAME_INIT(Cable_HW_Vers),
-	NAME_INIT(Cable_FW_Vers),
-	NAME_INIT(Type_C_To_Type_A_B_C),
-	NAME_INIT(Type_C_To_Type_C_Capt_Vdm_V2),
-	NAME_INIT(Cable_Latency),
-	NAME_INIT(Cable_Termination_Type),
-	NAME_INIT(VBUS_Through_Cable),
-	NAME_INIT(Cable_VBUS_Current),
-	NAME_INIT(Cable_Superspeed_Support),
-	NAME_INIT(Cable_USB_Highest_Speed),
-	NAME_INIT(Max_VBUS_Voltage_Vdm_V2),
-	NAME_INIT(Manufacturer_Info_Supported),
-	NAME_INIT(Manufacturer_Info_VID),
-	NAME_INIT(Manufacturer_Info_PID),
-	NAME_INIT(Chunking_Implemented),
-	NAME_INIT(Security_Msgs_Supported),
-	NAME_INIT(ID_Header_Connector_Type),
-	NAME_INIT(SVID_Fixed),
-	NAME_INIT(Cable_Num_SVIDs_Min),
-	NAME_INIT(Cable_Num_SVIDs_Max),
-	NAME_INIT(VPD_HW_Vers),
-	NAME_INIT(VPD_FW_Vers),
-	NAME_INIT(VPD_Max_VBUS_Voltage),
-	NAME_INIT(VPD_Charge_Through_Support),
-	NAME_INIT(VPD_Charge_Through_Current),
-	NAME_INIT(VPD_VBUS_Impedance),
-	NAME_INIT(VPD_Ground_Impedance),
-	NAME_INIT(Cable_SOP_PP_Controller),
-	NAME_INIT(SBU_Supported),
-	NAME_INIT(SBU_Type),
-	NAME_INIT(Active_Cable_Operating_Temp_Support),
-	NAME_INIT(Active_Cable_Max_Operating_Temp),
-	NAME_INIT(Active_Cable_Shutdown_Temp_Support),
-	NAME_INIT(Active_Cable_Shutdown_Temp),
-	NAME_INIT(Active_Cable_U3_CLd_Power),
-	NAME_INIT(Active_Cable_U3_U0_Trans_Mode),
-	NAME_INIT(Active_Cable_Physical_Connection),
-	NAME_INIT(Active_Cable_Active_Element),
-	NAME_INIT(Active_Cable_USB4_Support),
-	NAME_INIT(Active_Cable_USB2_Hub_Hops_Consumed),
-	NAME_INIT(Active_Cable_USB2_Supported),
-	NAME_INIT(Active_Cable_USB32_Supported),
-	NAME_INIT(Active_Cable_USB_Lanes),
-	NAME_INIT(Active_Cable_Optically_Isolated),
-	NAME_INIT(Active_Cable_USB_Gen),
-	NAME_INIT(Repeater_One_Type),
-	NAME_INIT(Repeater_Two_Type),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_component_name) == Component_Indexes);
-
-const char *vif_component_snk_pdo_name[] = {
-	NAME_INIT(Snk_PDO_Supply_Type),
-	NAME_INIT(Snk_PDO_Voltage),
-	NAME_INIT(Snk_PDO_Op_Power),
-	NAME_INIT(Snk_PDO_Min_Voltage),
-	NAME_INIT(Snk_PDO_Max_Voltage),
-	NAME_INIT(Snk_PDO_Op_Current),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_component_snk_pdo_name) == Snk_PDO_Indexes);
-
-const char *vif_component_src_pdo_name[] = {
-	NAME_INIT(Src_PDO_Supply_Type),
-	NAME_INIT(Src_PDO_Peak_Current),
-	NAME_INIT(Src_PDO_Voltage),
-	NAME_INIT(Src_PDO_Max_Current),
-	NAME_INIT(Src_PDO_Min_Voltage),
-	NAME_INIT(Src_PDO_Max_Voltage),
-	NAME_INIT(Src_PDO_Max_Power),
-	NAME_INIT(Src_PD_OCP_OC_Debounce),
-	NAME_INIT(Src_PD_OCP_OC_Threshold),
-	NAME_INIT(Src_PD_OCP_UV_Debounce),
-	NAME_INIT(Src_PD_OCP_UV_Threshold_Type),
-	NAME_INIT(Src_PD_OCP_UV_Threshold),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_component_src_pdo_name) == Src_PDO_Indexes);
-
-const char *vif_component_sop_svid_mode_name[] = {
-	NAME_INIT(SVID_Mode_Enter_SOP),
-	NAME_INIT(SVID_Mode_Recog_Mask_SOP),
-	NAME_INIT(SVID_Mode_Recog_Value_SOP),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_mode_name) ==
-						SopSVID_Mode_Indexes);
-
-const char *vif_component_sop_svid_name[] = {
-	NAME_INIT(SVID_SOP),
-	NAME_INIT(SVID_Modes_Fixed_SOP),
-	NAME_INIT(SVID_Num_Modes_Min_SOP),
-	NAME_INIT(SVID_Num_Modes_Max_SOP),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_name) == SopSVID_Indexes);
-
-const char *vif_cable_mode_name[] = {
-	NAME_INIT(SVID_Mode_Enter),
-	NAME_INIT(SVID_Mode_Recog_Mask),
-	NAME_INIT(SVID_Mode_Recog_Value),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_cable_mode_name) == CableSVID_Mode_Indexes);
-
-const char *vif_cable_svid_name[] = {
-	NAME_INIT(SVID),
-	NAME_INIT(SVID_Modes_Fixed),
-	NAME_INIT(SVID_Num_Modes_Min),
-	NAME_INIT(SVID_Num_Modes_Max),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_cable_svid_name) == CableSVID_Indexes);
-
-const char *vif_product_name[] = {
-	NAME_INIT(Product_VID),
-	NAME_INIT(USB4_Dock),
-	NAME_INIT(USB4_Num_Internal_Host_Controllers),
-	NAME_INIT(USB4_Num_PCIe_DN_Bridges),
-	NAME_INIT(USB4_Audio_Supported),
-	NAME_INIT(USB4_HID_Supported),
-	NAME_INIT(USB4_Printer_Supported),
-	NAME_INIT(USB4_Mass_Storage_Supported),
-	NAME_INIT(USB4_Video_Supported),
-	NAME_INIT(USB4_Comms_Networking_Supported),
-	NAME_INIT(USB4_Media_Transfer_Protocol_Supported),
-	NAME_INIT(USB4_Smart_Card_Supported),
-	NAME_INIT(USB4_Still_Image_Capture_Supported),
-	NAME_INIT(USB4_Monitor_Device_Supported),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_product_name) == Product_Indexes);
-
-const char *vif_product_pcie_endpoint_name[] = {
-	NAME_INIT(USB4_PCIe_Endpoint_Vendor_ID),
-	NAME_INIT(USB4_PCIe_Endpoint_Device_ID),
-	NAME_INIT(USB4_PCIe_Endpoint_Class_Code),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_product_pcie_endpoint_name) ==
-						PCIe_Endpoint_Indexes);
-
-const char *vif_product_usb4_router_name[] = {
-	NAME_INIT(USB4_Router_ID),
-	NAME_INIT(USB4_Silicon_VID),
-	NAME_INIT(USB4_Num_Lane_Adapters),
-	NAME_INIT(USB4_Num_USB3_DN_Adapters),
-	NAME_INIT(USB4_Num_DP_IN_Adapters),
-	NAME_INIT(USB4_Num_DP_OUT_Adapters),
-	NAME_INIT(USB4_Num_PCIe_DN_Adapters),
-	NAME_INIT(USB4_TBT3_Not_Supported),
-	NAME_INIT(USB4_PCIe_Wake_Supported),
-	NAME_INIT(USB4_USB3_Wake_Supported),
-	NAME_INIT(USB4_Num_Unused_Adapters),
-	NAME_INIT(USB4_TBT3_VID),
-	NAME_INIT(USB4_PCIe_Switch_Vendor_ID),
-	NAME_INIT(USB4_PCIe_Switch_Device_ID),
-	NAME_INIT(USB4_Num_PCIe_Endpoints),
-};
-BUILD_ASSERT(ARRAY_SIZE(vif_product_usb4_router_name) == USB4_Router_Indexes);
-
-
-static bool streq(const char *str1, const char *str2)
-{
-	return strcasecmp(str1, str2) == 0;
-}
-
-/*****************************************************************************
- * VIF Structure Override Value Retrieve Functions
- */
-/** Number **/
-static bool get_vif_field_tag_number(struct vif_field_t *vif_field, int *value)
-{
-	if (vif_field->tag_value == NULL)
-		return false;
-
-	*value = atoi(vif_field->tag_value);
-	return true;
-}
-static bool get_vif_field_str_number(struct vif_field_t *vif_field, int *value)
-{
-	if (vif_field->str_value == NULL)
-		return false;
-
-	*value = atoi(vif_field->str_value);
-	return true;
-}
-static bool get_vif_field_number(struct vif_field_t *vif_field, int *value)
-{
-	bool rv;
-
-	rv = get_vif_field_tag_number(vif_field, value);
-	if (!rv)
-		rv = get_vif_field_str_number(vif_field, value);
-
-	return rv;
-}
-__maybe_unused
-static bool get_vif_number(struct vif_field_t *vif_field, int default_value)
-{
-	int ret_value;
-
-	if (!get_vif_field_number(vif_field, &ret_value))
-		ret_value = default_value;
-
-	return ret_value;
-}
-
-/** Boolean **/
-static bool get_vif_field_tag_bool(struct vif_field_t *vif_field, bool *value)
-{
-	if (vif_field->tag_value == NULL)
-		return false;
-
-	*value = streq(vif_field->tag_value, "true");
-	return true;
-}
-static bool get_vif_field_str_bool(struct vif_field_t *vif_field, bool *value)
-{
-	if (vif_field->str_value == NULL)
-		return false;
-
-	*value = streq(vif_field->str_value, "YES");
-	return true;
-}
-static bool get_vif_field_bool(struct vif_field_t *vif_field, bool *value)
-{
-	bool rv;
-
-	rv = get_vif_field_tag_bool(vif_field, value);
-	if (!rv)
-		rv = get_vif_field_str_bool(vif_field, value);
-
-	return rv;
-}
-static bool get_vif_bool(struct vif_field_t *vif_field, bool default_value)
-{
-	bool ret_value;
-
-	if (!get_vif_field_bool(vif_field, &ret_value))
-		ret_value = default_value;
-
-	return ret_value;
-}
-
-/** String **/
-__maybe_unused
-static bool get_vif_field_tag_str(struct vif_field_t *vif_field, char **value)
-{
-	if (vif_field->tag_value == NULL)
-		return false;
-
-	*value = vif_field->tag_value;
-	return true;
-}
-__maybe_unused
-static bool get_vif_field_str_str(struct vif_field_t *vif_field, char **value)
-{
-	if (vif_field->str_value == NULL)
-		return false;
-
-	*value = vif_field->str_value;
-	return true;
-}
-/*
- * VIF Structure Override Value Retrieve Functions
- *****************************************************************************/
-
-
-/*****************************************************************************
- * Generic Helper Functions
- */
-static bool is_src(void)
-{
-	int override_value;
-	bool was_overridden;
-
-	/* Determine if we are DRP, SRC or SNK */
-	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
-	if (was_overridden) {
-		switch (override_value) {
-		case SRC:
-		case DRP:
-			return true;
-		case SNK:
-			return false;
-		default:
-			was_overridden = false;
-			break;
-		}
-	}
-	if (!was_overridden) {
-		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
-		if (was_overridden) {
-			switch (override_value) {
-			case PORT_PROVIDER_ONLY:	/* SRC */
-			case PORT_DRP:			/* DRP */
-				return true;
-			case PORT_CONSUMER_ONLY:	/* SNK */
-				return false;
-			default:
-				was_overridden = false;
-			}
-		}
-	}
-	return src_pdo_cnt;
-}
-static bool is_snk(void)
-{
-	int override_value;
-	bool was_overridden;
-
-	/* Determine if we are DRP, SRC or SNK */
-	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
-	if (was_overridden) {
-		switch (override_value) {
-		case SNK:
-		case DRP:
-			return true;
-		case SRC:
-			return false;
-		default:
-			was_overridden = false;
-			break;
-		}
-	}
-	if (!was_overridden) {
-		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
-		if (was_overridden) {
-			switch (override_value) {
-			case PORT_CONSUMER_ONLY:	/* SNK */
-			case PORT_DRP:			/* DRP */
-				return true;
-			case PORT_PROVIDER_ONLY:	/* SRC */
-				return false;
-			default:
-				was_overridden = false;
-			}
-		}
-	}
-	return (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ? pd_snk_pdo_cnt : 0;
-}
-static bool is_drp(void)
-{
-	int override_value;
-	bool was_overridden;
-
-	/* Determine if we are DRP, SRC or SNK */
-	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
-	if (was_overridden) {
-		switch (override_value) {
-		case DRP:
-			return true;
-		case SNK:
-			return false;
-		case SRC:
-		default:
-			was_overridden = false;
-			break;
-		}
-	}
-	if (!was_overridden) {
-		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
-		if (was_overridden) {
-			switch (override_value) {
-			case PORT_DRP:			/* DRP */
-				return true;
-			case PORT_CONSUMER_ONLY:	/* SNK */
-				return false;
-			case PORT_PROVIDER_ONLY:	/* SRC */
-			default:
-				was_overridden = false;
-			}
-		}
-	}
-	if (is_src())
-		return !!(src_pdo[0] & PDO_FIXED_DUAL_ROLE);
-	return false;
-}
-
-static bool can_act_as_device(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Can_Act_As_Device],
-#if defined(USB_DEV_CLASS) && defined(USB_CLASS_BILLBOARD)
-			    USB_DEV_CLASS == USB_CLASS_BILLBOARD
-#else
-			    false
-#endif
-			);
-}
-
-static bool can_act_as_host(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Can_Act_As_Host],
-			    (!(IS_ENABLED(CONFIG_USB_CTVPD) ||
-			       IS_ENABLED(CONFIG_USB_VPD))));
-}
-
-static bool is_usb4_supported(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB4_Supported],
-			    IS_ENABLED(CONFIG_USB_PD_USB4));
-}
-
-static bool is_usb_pd_supported(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB_PD_Support],
-			    (is_usb4_supported() ||
-			     IS_ENABLED(CONFIG_USB_PRL_SM) ||
-			     IS_ENABLED(CONFIG_USB_POWER_DELIVERY)));
-}
-
-static bool is_usb_comms_capable(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB_Comms_Capable],
-			    is_usb4_supported() ||
-			    (!(IS_ENABLED(CONFIG_USB_VPD) ||
-			       IS_ENABLED(CONFIG_USB_CTVPD))));
-}
-
-static bool is_alt_mode_controller(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Is_Alt_Mode_Controller],
-			    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP));
-}
-
-static bool does_respond_to_discov_sop_ufp(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Responds_To_Discov_SOP_UFP],
-			    (is_usb4_supported() ||
-			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
-}
-
-static bool does_respond_to_discov_sop_dfp(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Responds_To_Discov_SOP_DFP],
-			    (is_usb4_supported() ||
-			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
-}
-
-static bool does_support_device_usb_data(void)
-{
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Device_Supports_USB_Data],
-			    (is_usb4_supported() ||
-			     can_act_as_device()));
-}
-
-static bool does_support_host_usb_data(void)
-{
-	int type_c_state_machine;
-
-	if (!get_vif_field_tag_number(
-			&vif.Component[component_index]
-				.vif_field[Type_C_State_Machine],
-			&type_c_state_machine))
-		return false;
-
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Host_Supports_USB_Data],
-			    can_act_as_host());
-}
-
-static void init_src_pdos(void)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_DYNAMIC_SRC_CAP)) {
-		src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, 0);
-	} else {
-		if (IS_ENABLED(CONFIG_USB_PD_CUSTOM_PDO)) {
-			src_pdo_cnt = pd_src_pdo_cnt;
-			src_pdo = pd_src_pdo;
-		} else {
-			src_pdo_cnt = pd_src_pdo_max_cnt;
-			src_pdo = pd_src_pdo_max;
-		}
-	}
-}
-
-static bool vif_fields_present(struct vif_field_t *vif_fields, int count)
-{
-	int index;
-
-	for (index = 0; index < count; ++index) {
-		if (vif_fields[index].str_value ||
-		    vif_fields[index].tag_value) {
-			return true;
-		}
-	}
-	return false;
-}
-/*
- * Generic Helper Functions
- *****************************************************************************/
-
-
-/*****************************************************************************
- * VIF XML Output Functions
- */
-static void vif_out_str(FILE *vif_file, int level, char *str)
-{
-	while (level-- > 0)
-		fprintf(vif_file, "  ");
-	fprintf(vif_file, "%s\r\n", str);
-}
-
-static void vif_out_field(FILE *vif_file, int level,
-			  struct vif_field_t *vif_field)
-{
-	if (vif_field->str_value || vif_field->tag_value) {
-		while (level-- > 0)
-			fprintf(vif_file, "  ");
-
-		fprintf(vif_file, "<%s", vif_field->name);
-		if (vif_field->tag_value)
-			fprintf(vif_file, " value=\"%s\"",
-				vif_field->tag_value);
-		if (vif_field->str_value)
-			fprintf(vif_file, ">%s</%s>\r\n",
-				vif_field->str_value,
-				vif_field->name);
-		else
-			fprintf(vif_file, " />\r\n");
-	}
-}
-
-static void vif_out_fields_range(FILE *vif_file, int level,
-			   struct vif_field_t *vif_fields,
-			   int start, int count)
-{
-	int index;
-
-	for (index = start; index < count; ++index)
-		vif_out_field(vif_file, level, &vif_fields[index]);
-}
-
-static void vif_out_fields(FILE *vif_file, int level,
-			   struct vif_field_t *vif_fields, int count)
-{
-	vif_out_fields_range(vif_file, level, vif_fields, 0, count);
-}
-
-
-
-static void vif_output_vif_component_cable_svid_mode_list(FILE *vif_file,
-			struct vif_cableSVIDList_t *svid_list, int level)
-{
-	int index;
-
-	if (!vif_fields_present(svid_list->CableSVIDModeList[0].vif_field,
-				CableSVID_Mode_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<CableSVIDModeList>");
-	for (index = 0; index < MAX_NUM_CABLE_SVID_MODES; ++index) {
-		struct vif_cableSVIDModeList_t *mode_list =
-				&svid_list->CableSVIDModeList[index];
-
-		if (!vif_fields_present(mode_list->vif_field,
-					CableSVID_Mode_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<SOPSVIDMode>");
-		vif_out_fields(vif_file, level,
-			       mode_list->vif_field, CableSVID_Mode_Indexes);
-		vif_out_str(vif_file, --level, "</SOPSVIDMode>");
-	}
-	vif_out_str(vif_file, --level, "</CableSVIDModeList>");
-}
-
-static void vif_output_vif_component_cable_svid_list(FILE *vif_file,
-			struct vif_Component_t *component, int level)
-{
-	int index;
-
-	if (!vif_fields_present(component->CableSVIDList[0].vif_field,
-				CableSVID_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<CableSVIDList>");
-	for (index = 0; index < MAX_NUM_CABLE_SVIDS; ++index) {
-		struct vif_cableSVIDList_t *svid_list =
-				&component->CableSVIDList[index];
-
-		if (!vif_fields_present(svid_list->vif_field,
-					CableSVID_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<CableSVID>");
-		vif_out_fields(vif_file, level,
-			       svid_list->vif_field, CableSVID_Indexes);
-		vif_output_vif_component_cable_svid_mode_list(vif_file,
-						svid_list, level);
-		vif_out_str(vif_file, --level, "</CableSVID>");
-	}
-	vif_out_str(vif_file, --level, "</CableSVIDList>");
-}
-
-static void vif_output_vif_component_sop_svid_mode_list(FILE *vif_file,
-			struct vif_sopSVIDList_t *svid_list, int level)
-{
-	int index;
-
-	if (!vif_fields_present(svid_list->SOPSVIDModeList[0].vif_field,
-				SopSVID_Mode_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<SOPSVIDModeList>");
-	for (index = 0; index < MAX_NUM_SOP_SVID_MODES; ++index) {
-		struct vif_sopSVIDModeList_t *mode_list =
-				&svid_list->SOPSVIDModeList[index];
-
-		if (!vif_fields_present(mode_list->vif_field,
-					SopSVID_Mode_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<SOPSVIDMode>");
-		vif_out_fields(vif_file, level,
-			       mode_list->vif_field, SopSVID_Mode_Indexes);
-		vif_out_str(vif_file, --level, "</SOPSVIDMode>");
-	}
-	vif_out_str(vif_file, --level, "</SOPSVIDModeList>");
-}
-
-static void vif_output_vif_component_sop_svid_list(FILE *vif_file,
-			struct vif_Component_t *component, int level)
-{
-	int index;
-
-	if (!vif_fields_present(component->SOPSVIDList[0].vif_field,
-				SopSVID_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<SOPSVIDList>");
-	for (index = 0; index < MAX_NUM_SOP_SVIDS; ++index) {
-		struct vif_sopSVIDList_t *svid_list =
-				&component->SOPSVIDList[index];
-
-		if (!vif_fields_present(svid_list->vif_field,
-					SopSVID_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<SOPSVID>");
-		vif_out_fields(vif_file, level,
-			       svid_list->vif_field, SopSVID_Indexes);
-		vif_output_vif_component_sop_svid_mode_list(vif_file,
-						svid_list, level);
-		vif_out_str(vif_file, --level, "</SOPSVID>");
-	}
-	vif_out_str(vif_file, --level, "</SOPSVIDList>");
-}
-
-static void vif_output_vif_component_snk_pdo_list(FILE *vif_file,
-			struct vif_Component_t *component, int level)
-{
-	int index;
-
-	if (!vif_fields_present(component->SnkPdoList[0].vif_field,
-				Snk_PDO_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<SnkPdoList>");
-	for (index = 0; index < MAX_NUM_SNK_PDOS; ++index) {
-		struct vif_snkPdoList_t *pdo_list =
-				&component->SnkPdoList[index];
-
-		if (!vif_fields_present(pdo_list->vif_field,
-					Snk_PDO_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<SnkPDO>");
-		vif_out_fields(vif_file, level,
-			       pdo_list->vif_field, Snk_PDO_Indexes);
-		vif_out_str(vif_file, --level, "</SnkPDO>");
-	}
-	vif_out_str(vif_file, --level, "</SnkPdoList>");
-}
-
-static void vif_output_vif_component_src_pdo_list(FILE *vif_file,
-			struct vif_Component_t *component, int level)
-{
-	int index;
-
-	if (!vif_fields_present(component->SrcPdoList[0].vif_field,
-				Src_PDO_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<SrcPdoList>");
-	for (index = 0; index < MAX_NUM_SRC_PDOS; ++index) {
-		struct vif_srcPdoList_t *pdo_list =
-				&component->SrcPdoList[index];
-
-		if (!vif_fields_present(pdo_list->vif_field,
-					Src_PDO_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<SrcPDO>");
-		vif_out_fields(vif_file, level,
-			       pdo_list->vif_field, Src_PDO_Indexes);
-		vif_out_str(vif_file, --level, "</SrcPDO>");
-	}
-	vif_out_str(vif_file, --level, "</SrcPdoList>");
-}
-
-static void vif_output_vif_component(FILE *vif_file,
-			struct vif_t *vif, int level)
-{
-	int index;
-
-	for (index = 0; index < MAX_NUM_COMPONENTS; ++index) {
-		struct vif_Component_t *component = &vif->Component[index];
-
-		if (!vif_fields_present(component->vif_field,
-					Component_Indexes))
-			return;
-
-		vif_out_str(vif_file, level++, "<Component>");
-		vif_out_fields(vif_file, level,
-			       component->vif_field, Component_Indexes);
-		vif_output_vif_component_snk_pdo_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_src_pdo_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_sop_svid_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_cable_svid_list(vif_file,
-						component,
-						level);
-		vif_out_str(vif_file, --level, "</Component>");
-	}
-}
-
-static void vif_output_vif_product_usb4router_endpoint(FILE *vif_file,
-			struct vif_Usb4RouterListType_t *router, int level)
-{
-	int index;
-
-	if (!vif_fields_present(router->PCIeEndpointList[0].vif_field,
-				PCIe_Endpoint_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<PCIeEndpointList>");
-	for (index = 0; index < MAX_NUM_PCIE_ENDPOINTS; ++index) {
-		struct vif_PCIeEndpointListType_t *endpont =
-				&router->PCIeEndpointList[index];
-
-		if (!vif_fields_present(endpont->vif_field,
-					PCIe_Endpoint_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<PCIeEndpoint>");
-		vif_out_fields(vif_file, level,
-			       endpont->vif_field, PCIe_Endpoint_Indexes);
-		vif_out_str(vif_file, --level, "</PCIeEndpoint>");
-	}
-	vif_out_str(vif_file, --level, "</PCIeEndpointList>");
-}
-
-static void vif_output_vif_product_usb4router(FILE *vif_file,
-			struct vif_t *vif, int level)
-{
-	int index;
-
-	if (!vif_fields_present(vif->Product.USB4RouterList[0].vif_field,
-				USB4_Router_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<USB4RouterList>");
-	for (index = 0; index < MAX_NUM_USB4_ROUTERS; ++index) {
-		struct vif_Usb4RouterListType_t *router =
-				&vif->Product.USB4RouterList[index];
-
-		if (!vif_fields_present(router->vif_field,
-					USB4_Router_Indexes))
-			break;
-
-		vif_out_str(vif_file, level++, "<Usb4Router>");
-		vif_out_fields(vif_file, level,
-			       router->vif_field, USB4_Router_Indexes);
-		vif_output_vif_product_usb4router_endpoint(vif_file,
-							   router,
-							   level);
-		vif_out_str(vif_file, --level, "</Usb4Router>");
-	}
-	vif_out_str(vif_file, --level, "</USB4RouterList>");
-}
-
-static void vif_output_vif_product(FILE *vif_file,
-			struct vif_t *vif, int level)
-{
-	if (!vif_fields_present(vif->Product.vif_field, Product_Indexes))
-		return;
-
-	vif_out_str(vif_file, level++, "<Product>");
-	vif_out_fields(vif_file, level,
-		       vif->Product.vif_field, Product_Indexes);
-	vif_output_vif_product_usb4router(vif_file, vif, level);
-	vif_out_str(vif_file, --level, "</Product>");
-}
-
-static void vif_output_vif_xml(FILE *vif_file, struct vif_t *vif, int level)
-{
-	vif_out_field(vif_file, level, &vif->vif_field[VIF_Specification]);
-
-	vif_out_str(vif_file, level++, "<VIF_App>");
-	vif_out_fields(vif_file, level, vif->vif_app_field, VIF_App_Indexes);
-	vif_out_str(vif_file, --level, "</VIF_App>");
-
-	vif_out_fields_range(vif_file, level,
-		       vif->vif_field, Vendor_Name, VIF_Indexes);
-}
-
-static int vif_output_xml(const char *name, struct vif_t *vif)
-{
-	int level = 0;
-	FILE *vif_file;
-
-	vif_file = fopen(name, "w+");
-	if (vif_file == NULL) {
-		fprintf(stderr, "Output file '%s' could not be created\n",
-			name);
-		return 1;
-	}
-
-	vif_out_str(vif_file, level,
-		"<?xml version=\"1.0\" encoding=\"utf-8\"?>");
-	vif_out_str(vif_file, level++,
-		"<VIF xmlns=\"http://usb.org/VendorInfoFile.xsd\">");
-
-	vif_output_vif_xml(vif_file, vif, level);
-	vif_output_vif_product(vif_file, vif, level);
-	vif_output_vif_component(vif_file, vif, level);
-
-	vif_out_str(vif_file, --level, "</VIF>");
-
-	fclose(vif_file);
-	return 0;
-}
-/*
- * VIF XML Output Functions
- *****************************************************************************/
-
-
-/*****************************************************************************
- * VIF Structure Override from XML file functions
- */
-FILE *override_file;
-
-int pushback_cnt;
-char pushback_stack[20];
-
-static bool ov_open(const char *over_name)
-{
-	override_file = fopen(over_name, "r");
-
-	pushback_cnt = 0;
-	return override_file != NULL;
-}
-static int ov_getc(void)
-{
-	if (!override_file)
-		return EOF;
-
-	if (pushback_cnt)
-		return pushback_stack[--pushback_cnt];
-	return getc(override_file);
-}
-static void ovpre_getc(int cnt)
-{
-	if (pushback_cnt < cnt) {
-		int new_pushback_cnt = cnt;
-
-		while (cnt > 0)
-			pushback_stack[--cnt] = ov_getc();
-		pushback_cnt = new_pushback_cnt;
-	}
-}
-static void ovpre_drop(int cnt)
-{
-	pushback_cnt -= cnt;
-	if (pushback_cnt < 0)
-		pushback_cnt = 0;
-}
-static int ovpre_peek(int index)
-{
-	return pushback_stack[pushback_cnt - index - 1];
-}
-static void ov_pushback(int ch)
-{
-	pushback_stack[pushback_cnt++] = ch;
-}
-static void ov_close(void)
-{
-	if (override_file)
-		fclose(override_file);
-
-	pushback_cnt = 0;
-	override_file = NULL;
-}
-
-
-static void set_override_vif_field(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const char *str_value)
-{
-	char *ptr;
-
-	if (vif_field->str_value) {
-		free(vif_field->str_value);
-		vif_field->str_value = NULL;
-	}
-	if (vif_field->tag_value) {
-		free(vif_field->tag_value);
-		vif_field->tag_value = NULL;
-	}
-
-	vif_field->name = name;
-	if (tag_value && tag_value[0]) {
-		ptr = malloc(strlen(tag_value)+1);
-		strcpy(ptr, tag_value);
-		vif_field->tag_value = ptr;
-
-		/*
-		 * If the tag_value was provided and the str_value was
-		 * not and this is a boolean value, then fill in the
-		 * str_value
-		 */
-		if (!str_value || str_value[0] == '\0') {
-			if (streq(tag_value, "true"))
-				str_value = "YES";
-			else if (streq(tag_value, "false"))
-				str_value = "NO";
-		}
-	}
-	if (str_value && str_value[0]) {
-		ptr = malloc(strlen(str_value)+1);
-		strcpy(ptr, str_value);
-		vif_field->str_value = ptr;
-	}
-}
-
-static void ignore_xml_version_tag(void)
-{
-	int ch;
-
-	while ((ch = ov_getc()) != EOF) {
-		if (ch == '?') {
-			ch = ov_getc();
-			if (ch == '>')
-				break;
-			ov_pushback(ch);
-		}
-	}
-}
-static void ignore_comment_tag(void)
-{
-	int ch;
-
-	while ((ch = ov_getc()) != EOF) {
-		if (ch ==  '-') {
-			ovpre_getc(2);
-			if (ovpre_peek(0) == '-' &&
-			    ovpre_peek(1) == '>') {
-				/* --> */
-				ovpre_drop(2);
-				break;
-			}
-		}
-	}
-}
-static void ignore_white_space(void)
-{
-	int ch;
-
-	while ((ch = ov_getc()) != EOF) {
-		if (!isspace(ch)) {
-			ov_pushback(ch);
-			break;
-		}
-	}
-}
-static void ignore_to_end_tag(void)
-{
-	int ch;
-
-	while ((ch = ov_getc()) != EOF) {
-		if (ch == '>')
-			break;
-	}
-}
-static bool get_next_tag(char *name,
-			 char *tag_value,
-			 char *str_value)
-{
-	int ch;
-	int name_index = 0;
-	int tag_index = 0;
-	int str_index = 0;
-
-	name[0] = '\0';
-	tag_value[0] = '\0';
-	str_value[0] = '\0';
-
-	/*
-	 * Ignore <? .... ?>
-	 * Ignore <!-- ... -->
-	 * Find tags <X/>, <X> and </X>
-	 */
-	while ((ch = ov_getc()) != EOF) {
-		if (ch == '<') {
-			/*
-			 * Ignore XML version <? ... ?>
-			 */
-			ovpre_getc(1);
-			if (ovpre_peek(0) == '?') {
-				ovpre_drop(1);
-				ignore_xml_version_tag();
-				continue;
-			}
-
-			/*
-			 * Ignore XML comment <!-- ... -->
-			 */
-			ovpre_getc(3);
-			if (ovpre_peek(0) == '!' &&
-			    ovpre_peek(1) == '-' &&
-			    ovpre_peek(2) == '-') {
-				ovpre_drop(3);
-				ignore_comment_tag();
-				continue;
-			}
-
-			/* Looking for terminating tag */
-			ovpre_getc(1);
-			if (ovpre_peek(0) == '/') {
-				while ((ch = ov_getc()) != EOF) {
-					if (ch == '>')
-						break;
-					name[name_index++] = ch;
-				}
-				name[name_index] = '\0';
-				return true;
-			}
-
-			/* Looking for a tag name */
-			while ((ch = ov_getc()) != EOF) {
-				if (ch == '_' || isalpha(ch) || isdigit(ch)) {
-					name[name_index++] = ch;
-				} else {
-					ov_pushback(ch);
-					break;
-				}
-			}
-			name[name_index] = '\0';
-
-			/* Consume any whitespace */
-			ignore_white_space();
-
-			/* See if there is a tag_string value */
-			ovpre_getc(7);
-			if (ovpre_peek(0) == 'v' &&
-			    ovpre_peek(1) == 'a' &&
-			    ovpre_peek(2) == 'l' &&
-			    ovpre_peek(3) == 'u' &&
-			    ovpre_peek(4) == 'e' &&
-			    ovpre_peek(5) == '=' &&
-			    ovpre_peek(6) == '"') {
-				ovpre_drop(7);
-				while ((ch = ov_getc()) != EOF) {
-					if (ch == '"')
-						break;
-					tag_value[tag_index++] = ch;
-				}
-				tag_value[tag_index] = '\0';
-			}
-
-			/* Consume any whitespace */
-			ignore_white_space();
-
-			/* /> ending the tag will conclude this tag */
-			ovpre_getc(2);
-			if (ovpre_peek(0) == '/' &&
-			    ovpre_peek(1) == '>') {
-				ovpre_drop(2);
-				return true;
-			}
-			if (ovpre_peek(0) == '>') {
-				ovpre_drop(1);
-				while ((ch = ov_getc()) != EOF) {
-					if (ch == '<') {
-						ov_pushback(ch);
-						break;
-					}
-					str_value[str_index++] = ch;
-				}
-				str_value[str_index] = '\0';
-
-				ovpre_getc(2);
-				if (ovpre_peek(0) == '<' &&
-				    ovpre_peek(1) == '/') {
-					ovpre_drop(2);
-					ignore_to_end_tag();
-				}
-			}
-			return true;
-		}
-	}
-	return false;
-}
-
-static void override_vif_product_pcie_endpoint_field(
-		struct vif_PCIeEndpointListType_t *endpoint)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/PCIeEndpoint"))
-			break;
-
-		for (i = 0; i < PCIe_Endpoint_Indexes; i++)
-			if (streq(name, vif_product_pcie_endpoint_name[i]))
-				break;
-		if (i != PCIe_Endpoint_Indexes)
-			set_override_vif_field(
-				&endpoint->vif_field[i],
-				vif_product_pcie_endpoint_name[i],
-				tag_value,
-				str_value);
-		else
-			fprintf(stderr,
-				"VIF/Component/Usb4Router/PCIeEndpoint:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-static void override_vif_product_pcie_endpoint_list_field(
-		struct vif_PCIeEndpointListType_t *endpoint_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int endpoint_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/PCIeEndpointList"))
-			break;
-
-		if (streq(name, "PCIeEndpoint"))
-			override_vif_product_pcie_endpoint_field(
-					&endpoint_list[endpoint_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Product/Usb4Router/PCIeEndpointList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_product_usb4router_fields(
-		struct vif_Usb4RouterListType_t *router)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int endpoint_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/Usb4Router"))
-			break;
-
-		if (streq(name, "PCIeEndpointList"))
-			override_vif_product_pcie_endpoint_list_field(
-				&router->PCIeEndpointList[endpoint_index++]);
-		else {
-			int i;
-
-			for (i = 0; i < USB4_Router_Indexes; i++)
-				if (streq(name,
-					  vif_product_usb4_router_name[i]))
-					break;
-			if (i != USB4_Router_Indexes)
-				set_override_vif_field(
-					&router->vif_field[i],
-					vif_product_usb4_router_name[i],
-					tag_value,
-					str_value);
-			else
-				fprintf(stderr,
-					"VIF/Component/Usb4Router:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-}
-static void override_vif_product_usb4routerlist_fields(
-		struct vif_Usb4RouterListType_t *router_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int router_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/USB4RouterList"))
-			break;
-
-		if (streq(name, "Usb4Router"))
-			override_vif_product_usb4router_fields(
-				&router_list[router_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Product/USB4RouterList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_product_fields(struct vif_Product_t *vif_product)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/Product"))
-			break;
-
-		if (streq(name, "USB4RouterList"))
-			override_vif_product_usb4routerlist_fields(
-				vif_product->USB4RouterList);
-		else {
-			int i;
-
-			for (i = 0; i < Product_Indexes; i++)
-				if (streq(name, vif_product_name[i]))
-					break;
-			if (i != Product_Indexes)
-				set_override_vif_field(
-					&vif_product->vif_field[i],
-					vif_product_name[i],
-					tag_value,
-					str_value);
-			else
-				fprintf(stderr,
-					"VIFF/Product:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-}
-
-static void override_vif_component_src_pdo_fields(
-		struct vif_srcPdoList_t *vif_src_pdo)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/SrcPdo"))
-			break;
-
-		for (i = 0; i < Src_PDO_Indexes; i++)
-			if (streq(name, vif_component_src_pdo_name[i]))
-				break;
-		if (i != Src_PDO_Indexes)
-			set_override_vif_field(
-				&vif_src_pdo->vif_field[i],
-				vif_component_src_pdo_name[i],
-				tag_value,
-				str_value);
-		else
-			fprintf(stderr,
-				"VIF/Component/SrcPdo:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-static void override_vif_component_src_pdo_list_fields(
-		struct vif_srcPdoList_t *vif_src_pdo_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int src_pdo_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/SrcPdoList"))
-			break;
-
-		if (streq(name, "SrcPdo"))
-			override_vif_component_src_pdo_fields(
-				&vif_src_pdo_list[src_pdo_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/SrcPdoList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_snk_pdo_fields(
-		struct vif_snkPdoList_t *vif_snk_pdo)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/SnkPdo"))
-			break;
-
-		for (i = 0; i < Snk_PDO_Indexes; i++)
-			if (streq(name, vif_component_snk_pdo_name[i]))
-				break;
-		if (i != Snk_PDO_Indexes)
-			set_override_vif_field(
-				&vif_snk_pdo->vif_field[i],
-				vif_component_snk_pdo_name[i],
-				tag_value,
-				str_value);
-		else
-			fprintf(stderr,
-				"VIF/Component/SnkPdo:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-static void override_vif_component_snk_pdo_list_fields(
-		struct vif_snkPdoList_t *vif_snk_pdo_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int snk_pdo_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/SnkPdoList"))
-			break;
-
-		if (streq(name, "SnkPdo"))
-			override_vif_component_snk_pdo_fields(
-				&vif_snk_pdo_list[snk_pdo_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/SnkPdoList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_sop_svid_mode_fields(
-		struct vif_sopSVIDModeList_t *svid_mode)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/SOPSVIDMode"))
-			break;
-
-		for (i = 0; i < SopSVID_Indexes; i++)
-			if (streq(name, vif_component_sop_svid_mode_name[i]))
-				break;
-		if (i != SopSVID_Indexes)
-			set_override_vif_field(
-				&svid_mode->vif_field[i],
-				vif_component_sop_svid_mode_name[i],
-				tag_value,
-				str_value);
-		else
-			fprintf(stderr,
-				"VIF/Component/SOPSVIDMode:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-static void override_vif_component_sop_svid_mode_list_fields(
-		struct vif_sopSVIDModeList_t *svid_mode_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int mode_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/SOPSVIDModeList"))
-			break;
-
-		if (streq(name, "SOPSVIDMode"))
-			override_vif_component_sop_svid_mode_fields(
-				&svid_mode_list[mode_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/SOPSVIDModeList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_sop_svid_fields(
-		struct vif_sopSVIDList_t *vif_sop_svid)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/SOPSVID"))
-			break;
-
-		if (streq(name, "SOPSVIDModeList"))
-			override_vif_component_sop_svid_mode_list_fields(
-				vif_sop_svid->SOPSVIDModeList);
-		else {
-			int i;
-
-			for (i = 0; i < SopSVID_Indexes; i++)
-				if (streq(name,
-					  vif_component_sop_svid_name[i]))
-					break;
-			if (i != SopSVID_Indexes)
-				set_override_vif_field(
-					&vif_sop_svid->vif_field[i],
-					vif_component_sop_svid_name[i],
-					tag_value,
-					str_value);
-			else
-				fprintf(stderr,
-					"VIF/Component/SOPSVID:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-}
-static void override_vif_component_sop_svid_list_fields(
-		struct vif_sopSVIDList_t *vif_sop_svid_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int sop_svid_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/SOPSVIDList"))
-			break;
-
-		if (streq(name, "SOPSVID"))
-			override_vif_component_sop_svid_fields(
-				&vif_sop_svid_list[sop_svid_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/SOPSVIDList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_cable_svid_mode_fields(
-		struct vif_cableSVIDModeList_t *vif_cable_mode)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/CableSVIDMode"))
-			break;
-
-		for (i = 0; i < CableSVID_Mode_Indexes; i++)
-			if (streq(name, vif_cable_mode_name[i]))
-				break;
-		if (i != CableSVID_Mode_Indexes)
-			set_override_vif_field(
-				&vif_cable_mode->vif_field[i],
-				vif_cable_mode_name[i],
-				tag_value,
-				str_value);
-		else
-			fprintf(stderr,
-				"VIF/Component/CableSVIDMode:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-static void override_vif_component_cable_svid_mode_list_fields(
-		struct vif_cableSVIDModeList_t *vif_cable_mode_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int mode_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/CableSVIDModeList"))
-			break;
-
-		if (streq(name, "CableSVIDMode"))
-			override_vif_component_cable_svid_mode_fields(
-				&vif_cable_mode_list[mode_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/CableSVIDModeList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_cable_svid_fields(
-		struct vif_cableSVIDList_t *vif_cable_svid)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int mode_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/CableSVID"))
-			break;
-
-		if (streq(name, "CableSVIDModeList"))
-			override_vif_component_cable_svid_mode_list_fields(
-				&vif_cable_svid->CableSVIDModeList[
-							mode_index++]);
-		else {
-			int i;
-
-			for (i = 0; i < CableSVID_Indexes; i++)
-				if (streq(name, vif_cable_svid_name[i]))
-					break;
-			if (i != CableSVID_Indexes)
-				set_override_vif_field(
-					&vif_cable_svid->vif_field[i],
-					vif_cable_svid_name[i],
-					tag_value,
-					str_value);
-			else
-				fprintf(stderr,
-					"VIF/Component/CableSVID:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-}
-static void override_vif_component_cable_svid_list_fields(
-		struct vif_cableSVIDList_t *vif_cable_svid_list)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-	int cable_svid_index = 0;
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/CableSVIDList"))
-			break;
-
-		if (streq(name, "CableSVID"))
-			override_vif_component_cable_svid_fields(
-				&vif_cable_svid_list[cable_svid_index++]);
-		else
-			fprintf(stderr,
-				"VIF/Component/CableSVIDList:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_component_fields(
-		struct vif_Component_t *vif_component)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/Component"))
-			break;
-
-		if (streq(name, "SrcPdoList"))
-			override_vif_component_src_pdo_list_fields(
-					vif_component->SrcPdoList);
-		else if (streq(name, "SnkPdoList"))
-			override_vif_component_snk_pdo_list_fields(
-					vif_component->SnkPdoList);
-		else if (streq(name, "SOPSVIDList"))
-			override_vif_component_sop_svid_list_fields(
-					vif_component->SOPSVIDList);
-		else if (streq(name, "CableSVIDList"))
-			override_vif_component_cable_svid_list_fields(
-					vif_component->CableSVIDList);
-		else {
-			int i;
-
-			for (i = 0; i < Component_Indexes; i++)
-				if (streq(name, vif_component_name[i]))
-					break;
-			if (i != Component_Indexes)
-				set_override_vif_field(
-						&vif_component->vif_field[i],
-						vif_component_name[i],
-						tag_value,
-						str_value);
-			else
-				fprintf(stderr,
-					"VIF/Component:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-}
-
-static void override_vif_app_fields(struct vif_t *vif)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		int i;
-
-		if (streq(name, "/VIF_App"))
-			break;
-
-		for (i = 0; i < VIF_App_Indexes; i++)
-			if (streq(name, vif_app_name[i]))
-				break;
-		if (i == VIF_App_Indexes)
-			fprintf(stderr,
-				"VIFF/VIF_App:"
-				" Unknown tag '%s'\n", name);
-	}
-}
-
-static void override_vif_fields(struct vif_t *vif)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	component_index = 0;
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "/VIF"))
-			break;
-
-		if (streq(name, "VIF_App"))
-			override_vif_app_fields(vif);
-		else if (streq(name, "Component"))
-			override_vif_component_fields(
-				&vif->Component[component_index++]);
-		else if (streq(name, "Product"))
-			override_vif_product_fields(&vif->Product);
-		else {
-			int i;
-
-			for (i = 0; i < VIF_Indexes; i++)
-				if (streq(name, vif_name[i]))
-					break;
-			if (i != VIF_Indexes)
-				set_override_vif_field(
-						&vif->vif_field[i],
-						vif_name[i],
-						tag_value,
-						str_value);
-			else
-				fprintf(stderr,
-					"VIF:"
-					" Unknown tag '%s'\n", name);
-		}
-	}
-
-	/*
-	 * Don't care what they requested, I am making the file and that
-	 * means VIF/VIF_App is to be set by me.
-	 */
-	set_override_vif_field(&vif->vif_app_field[Vendor],
-		vif_app_name[Vendor],
-		NULL,
-		VIF_APP_VENDOR_VALUE);
-
-	set_override_vif_field(&vif->vif_app_field[Name],
-		vif_app_name[Name],
-		NULL,
-		VIF_APP_NAME_VALUE);
-
-	set_override_vif_field(&vif->vif_app_field[Version],
-		vif_app_name[Version],
-		NULL,
-		VIF_APP_VERSION_VALUE);
-}
-
-static int override_gen_vif(char *over_name, struct vif_t *vif)
-{
-	char name[80];
-	char tag_value[80];
-	char str_value[80];
-
-	if (!ov_open(over_name)) {
-		fprintf(stderr, "Override file '%s' could not be opened\n",
-			over_name);
-		return 1;
-	}
-
-	while (get_next_tag(name, tag_value, str_value)) {
-		if (streq(name, "VIF"))
-			override_vif_fields(vif);
-		else
-			fprintf(stderr,
-				"Unknown tag '%s'\n", name);
-	}
-
-	ov_close();
-	return 0;
-}
-/*
- * VIF Structure Override from XML file functions
- *****************************************************************************/
-
-
-/*****************************************************************************
- * VIF Structure Initialization Helper Functions
- */
-static void set_vif_field(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const char *str_value)
-{
-	char *ptr;
-
-	/*
-	 * Override already set or trying to set to nothing should do
-	 * nothing. Just return
-	 */
-	if ((vif_field->name || vif_field->str_value || vif_field->tag_value) ||
-	    (str_value == NULL && tag_value == NULL))
-		return;
-
-	vif_field->name = name;
-	if (tag_value) {
-		ptr = malloc(strlen(tag_value)+1);
-		strcpy(ptr, tag_value);
-		vif_field->tag_value = ptr;
-	}
-	if (str_value) {
-		ptr = malloc(strlen(str_value)+1);
-		strcpy(ptr, str_value);
-		vif_field->str_value = ptr;
-	}
-}
-__maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field,
-			const char *name,
-			const bool val)
-{
-	if (val)
-		set_vif_field(vif_field, name, "true", "YES");
-	else
-		set_vif_field(vif_field, name, "false", "NO");
-}
-__maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const int str_value)
-{
-	char str_str[20];
-
-	sprintf(str_str, "%d", str_value);
-	set_vif_field(vif_field, name, tag_value, str_str);
-}
-__maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field,
-			const char *name,
-			const int tag_value,
-			const char *str_value)
-{
-	char str_tag[20];
-
-	sprintf(str_tag, "%d", tag_value);
-	set_vif_field(vif_field, name, str_tag, str_value);
-}
-__maybe_unused static void set_vif_field_itis(struct vif_field_t *vif_field,
-			const char *name,
-			const int tag_value,
-			const int str_value)
-{
-	char str_tag[20];
-	char str_str[20];
-
-	sprintf(str_tag, "%d", tag_value);
-	sprintf(str_str, "%d", str_value);
-	set_vif_field(vif_field, name, str_tag, str_str);
-}
-/*
- * VIF Structure Initialization Helper Functions
- *****************************************************************************/
-
-/*****************************************************************************
- * VIF Structure Initialization from Config Functions
- */
-/*
- * TODO: Generic todo to fill in additional fields as the need presents
- * itself
- *
- * Fields that are not currently being initialized
- *
- * vif_Component USB4 Port Fields
- *	USB4_Lane_0_Adapter			numericFieldType
- *	USB4_Max_Speed				numericFieldType
- *	USB4_DFP_Supported			booleanFieldType
- *	USB4_UFP_Supported			booleanFieldType
- *	USB4_USB3_Tunneling_Supported		booleanFieldType
- *	USB4_DP_Tunneling_Supported		booleanFieldType
- *	USB4_PCIe_Tunneling_Supported		booleanFieldType
- *	USB4_TBT3_Compatibility_Supported	booleanFieldType
- *	USB4_CL1_State_Supported		booleanFieldType
- *	USB4_CL2_State_Supported		booleanFieldType
- *	USB4_Num_Retimers			numericFieldType
- *	USB4_DP_Bit_Rate			numericFieldType
- *	USB4_Num_DP_Lanes			numericFieldType
- *
- * vif_Component USB4 Product Fields
- *	USB4_Dock				booleanFieldType
- *	USB4_Num_Internal_Host_Controllers	numericFieldType
- *	USB4_Num_PCIe_DN_Bridges		numericFieldType
- *
- * vif_Component USB4 Device Class Fallback Support
- *	USB4_Audio_Supported			booleanFieldType
- *	USB4_HID_Supported			booleanFieldType
- *	USB4_Printer_Supported			booleanFieldType
- *	USB4_Mass_Storage_Supported		booleanFieldType
- *	USB4_Video_Supported			booleanFieldType
- *	USB4_Comms_Networking_Supported		booleanFieldType
- *	USB4_Media_Transfer_Protocol_Supported	booleanFieldType
- *	USB4_Smart_Card_Supported		booleanFieldType
- *	USB4_Still_Image_Capture_Supported	booleanFieldType
- *	USB4_Monitor_Device_Supported		booleanFieldType
- *
- * vif_Usb4RouterListType USB4 Router Fields
- *	USB4_Router_ID				numericFieldType
- *	USB4_Silicon_VID			numericFieldType
- *	USB4_Num_Lane_Adapters			numericFieldType
- *	USB4_Num_USB3_DN_Adapters		numericFieldType
- *	USB4_Num_DP_IN_Adapters			numericFieldType
- *	USB4_Num_DP_OUT_Adapters		numericFieldType
- *	USB4_Num_PCIe_DN_Adapters		numericFieldType
- *	USB4_TBT3_Not_Supported			numericFieldType
- *	USB4_PCIe_Wake_Supported		booleanFieldType
- *	USB4_USB3_Wake_Supported		booleanFieldType
- *	USB4_Num_Unused_Adapters		numericFieldType
- *	USB4_TBT3_VID				numericFieldType
- *	USB4_PCIe_Switch_Vendor_ID		numericFieldType
- *	USB4_PCIe_Switch_Device_ID		numericFieldType
- *	USB4_Num_PCIe_Endpoints			numericFieldType
- *
- * vif_PCIeEndpointListType PCIe Endpoint Fields
- *	USB4_PCIe_Endpoint_Vendor_ID		numericFieldType
- *	USB4_PCIe_Endpoint_Device_ID		numericFieldType
- *	USB4_PCIe_Endpoint_Class_Code		numericFieldType
- *
- * vif_sopSVIDList SOP SVIDs
- *	SVID_SOP				numericFieldType
- *	SVID_Modes_Fixed_SOP			booleanFieldType
- *	SVID_Num_Modes_Min_SOP			numericFieldType
- *	SVID_Num_Modes_Max_SOP			numericFieldType
- *
- * vif_sopSVIDModeList SOP SVID Modes
- *	SVID_Mode_Enter_SOP			booleanFieldType
- *	SVID_Mode_Recog_Mask_SOP		numericFieldType
- *	SVID_Mode_Recog_Value_SOP		numericFieldType
- *
- * vif_Component Alternate Mode Adapter Fields
- *	AMA_HW_Vers				numericFieldType
- *	AMA_FW_Vers				numericFieldType
- *	AMA_VCONN_Power				booleanFieldType
- *	AMA_VCONN_Reqd				booleanFieldType
- *	AMA_VBUS_Reqd				booleanFieldType
- *	AMA_Superspeed_Support			numericFieldType
- *
- * vif_Component Cable/eMarker Fields
- *	XID					numericFieldType
- *	Data_Capable_As_USB_Host		booleanFieldType
- *	Data_Capable_As_USB_Device		booleanFieldType
- *	Product_Type				numericFieldType
- *	Modal_Operation_Supported		booleanFieldType
- *	USB_VID					numericFieldType
- *	PID					numericFieldType
- *	bcdDevice				numericFieldType
- *	Cable_HW_Vers				numericFieldType
- *	Cable_FW_Vers				numericFieldType
- *	Type_C_To_Type_A_B_C			numericFieldType
- *	Type_C_To_Type_C_Capt_Vdm_V2		numericFieldType
- *	Cable_Latency				numericFieldType
- *	Cable_Termination_Type			numericFieldType
- *	Cable_VBUS_Current			numericFieldType
- *	VBUS_Through_Cable			booleanFieldType
- *	Cable_Superspeed_Support		numericFieldType
- *	Cable_USB_Highest_Speed			numericFieldType
- *	Max_VBUS_Voltage_Vdm_V2			numericFieldType
- *	Manufacturer_Info_Supported,		booleanFieldType
- *	Manufacturer_Info_VID,			numericFieldType
- *	Manufacturer_Info_PID,			numericFieldType
- *	Chunking_Implemented			booleanFieldType
- *	Security_Msgs_Supported			booleanFieldType
- *	ID_Header_Connector_Type		numericFieldType
- *	Cable_Num_SVIDs_Min			numericFieldType
- *	Cable_Num_SVIDs_Max			numericFieldType
- *	SVID_Fixed				booleanFieldType
- *
- * vif_cableSVIDList Cable SVIDs
- *	SVID					numericFieldType
- *	SVID_Modes_Fixed			booleanFieldType
- *	SVID_Num_Modes_Min			numericFieldType
- *	SVID_Num_Modes_Max			numericFieldType
- *
- * vif_cableSVIDModeList Cable SVID Modes
- *	SVID_Mode_Enter				booleanFieldType
- *	SVID_Mode_Recog_Mask			numericFieldType
- *	SVID_Mode_Recog_Value			numericFieldType
- *
- * vif_Component Active Cable Fields
- *	Cable_SOP_PP_Controller			booleanFieldType
- *	SBU_Supported				booleanFieldType
- *	SBU_Type				numericFieldType
- *	Active_Cable_Operating_Temp_Support	booleanFieldType
- *	Active_Cable_Max_Operating_Temp		numericFieldType
- *	Active_Cable_Shutdown_Temp_Support	booleanFieldType
- *	Active_Cable_Shutdown_Temp		numericFieldType
- *	Active_Cable_U3_CLd_Power		numericFieldType
- *	Active_Cable_U3_U0_Trans_Mode		numericFieldType
- *	Active_Cable_Physical_Connection	numericFieldType
- *	Active_Cable_Active_Element		numericFieldType
- *	Active_Cable_USB4_Support		booleanFieldType
- *	Active_Cable_USB2_Supported		booleanFieldType
- *	Active_Cable_USB2_Hub_Hops_Consumed	numericFieldType
- *	Active_Cable_USB32_Supported		booleanFieldType
- *	Active_Cable_USB_Lanes			numericFieldType
- *	Active_Cable_Optically_Isolated		booleanFieldType
- *	Active_Cable_USB_Gen			numericFieldType
- *
- * vif_Component VCONN Powered Device
- *	VPD_HW_Vers				numericFieldType
- *	VPD_FW_Vers				numericFieldType
- *	VPD_Max_VBUS_Voltage			numericFieldType
- *	VPD_Charge_Through_Support		booleanFieldType
- *	VPD_Charge_Through_Current		numericFieldType
- *	VPD_VBUS_Impedance			numericFieldType
- *	VPD_Ground_Impedance			numericFieldType
- *
- * vif_Component Repeater Fields
- *	Repeater_One_Type			numericFieldType
- *	Repeater_Two_Type			numericFieldType
- */
-
-__maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
-					       uint32_t pdo)
-{
-	int32_t power_mw;
-	char str[40];
-
-	/*********************************************************************
-	 * Sink PDOs
-	 */
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
-		uint32_t current = pdo & 0x3ff;
-		uint32_t current_ma = current * 10;
-		uint32_t voltage = (pdo >> 10) & 0x3ff;
-		uint32_t voltage_mv = voltage * 50;
-
-		power_mw = (current_ma * voltage_mv) / 1000;
-
-		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"0", "Fixed");
-		sprintf(str, "%d mV", voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Voltage],
-			voltage, str);
-		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
-			current, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t max_voltage_mv = max_voltage * 50;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-		uint32_t min_voltage_mv = min_voltage * 50;
-		int32_t power;
-
-		power = pdo & 0x3ff;
-		power_mw = power * 250;
-
-		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"1", "Battery");
-		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
-			min_voltage, str);
-		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
-			max_voltage, str);
-		sprintf(str, "%d mW", power_mw);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Power],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Power],
-			power, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t max_voltage_mv = max_voltage * 50;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-		uint32_t min_voltage_mv = min_voltage * 50;
-		uint32_t current = pdo & 0x3ff;
-		uint32_t current_ma = current * 10;
-
-		power_mw = (current_ma * max_voltage_mv) / 1000;
-
-		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"2", "Variable");
-		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
-			min_voltage, str);
-		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
-			max_voltage, str);
-		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
-			current, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-		uint32_t pps = (pdo >> 28) & 3;
-		uint32_t pps_max_voltage = (pdo >> 17) & 0xff;
-		uint32_t pps_max_voltage_mv = pps_max_voltage * 100;
-		uint32_t pps_min_voltage = (pdo >> 8) & 0xff;
-		uint32_t pps_min_voltage_mv = pps_min_voltage * 100;
-		uint32_t pps_current = pdo & 0x7f;
-		uint32_t pps_current_ma = pps_current * 50;
-
-		if (pps) {
-			fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-			return -1;
-		}
-
-		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
-
-		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"3", "PPS");
-		sprintf(str, "%d mA", pps_current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
-			pps_current, str);
-		sprintf(str, "%d mV", pps_min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
-			pps_min_voltage, str);
-		sprintf(str, "%d mV", pps_max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
-			pps_max_voltage, str);
-	} else {
-		fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-		return -1;
-	}
-
-	return power_mw;
-}
-
-__maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
-					       uint32_t pdo)
-{
-	int32_t power_mw;
-	char str[40];
-
-	/*********************************************************************
-	 * Source PDOs
-	 *
-	 * TODO: Generic todo to fill in additional fields as the need presents
-	 * itself
-	 *
-	 * Fields that are not currently being initialized
-	 *
-	 * vif_srcPdoList
-	 *	Src_PD_OCP_OC_Debounce			numericFieldType
-	 *	Src_PD_OCP_OC_Threshold			numericFieldType
-	 *	Src_PD_OCP_UV_Debounce			numericFieldType
-	 *	Src_PD_OCP_UV_Threshold_Type		numericFieldType
-	 *	Src_PD_OCP_UV_Threshold			numericFieldType
-	 */
-	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_FIXED) {
-		uint32_t current = pdo & 0x3ff;
-		uint32_t current_ma = current * 10;
-		uint32_t voltage = (pdo >> 10) & 0x3ff;
-		uint32_t voltage_mv = voltage * 50;
-
-		power_mw = (current_ma * voltage_mv) / 1000;
-
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"0", "Fixed");
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
-			vif_component_src_pdo_name[Src_PDO_Peak_Current],
-			"0", "100% IOC");
-		sprintf(str, "%d mV", voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Voltage],
-			voltage, str);
-		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
-			vif_component_src_pdo_name[Src_PDO_Max_Current],
-			current, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t max_voltage_mv = max_voltage * 50;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-		uint32_t min_voltage_mv = min_voltage * 50;
-		int32_t power;
-
-		power = pdo & 0x3ff;
-		power_mw = power * 250;
-
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"1", "Battery");
-		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
-			min_voltage, str);
-		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
-			max_voltage, str);
-		sprintf(str, "%d mW", power_mw);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Power],
-			vif_component_src_pdo_name[Src_PDO_Max_Power],
-			power, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
-		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
-		uint32_t max_voltage_mv = max_voltage * 50;
-		uint32_t min_voltage = (pdo >> 10) & 0x3ff;
-		uint32_t min_voltage_mv = min_voltage * 50;
-		uint32_t current = pdo & 0x3ff;
-		uint32_t current_ma = current * 10;
-
-		power_mw = (current_ma * max_voltage_mv) / 1000;
-
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"2", "Variable");
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
-			vif_component_src_pdo_name[Src_PDO_Peak_Current],
-			"0", "100% IOC");
-		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
-			min_voltage, str);
-		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
-			max_voltage, str);
-		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
-			vif_component_src_pdo_name[Src_PDO_Max_Current],
-			current, str);
-
-	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
-		uint32_t pps = (pdo >> 28) & 3;
-		uint32_t pps_max_voltage = (pdo >> 17) & 0xff;
-		uint32_t pps_max_voltage_mv = pps_max_voltage * 100;
-		uint32_t pps_min_voltage = (pdo >> 8) & 0xff;
-		uint32_t pps_min_voltage_mv = pps_min_voltage * 100;
-		uint32_t pps_current = pdo & 0x7f;
-		uint32_t pps_current_ma = pps_current * 50;
-
-		if (pps) {
-			fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-			return -1;
-		}
-
-		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
-
-		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"3", "PPS");
-		sprintf(str, "%d mA", pps_current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
-			vif_component_src_pdo_name[Src_PDO_Max_Current],
-			pps_current, str);
-		sprintf(str, "%d mV", pps_min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
-			pps_min_voltage, str);
-		sprintf(str, "%d mV", pps_max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
-			pps_max_voltage, str);
-
-	} else {
-		fprintf(stderr, "ERROR: Invalid PDO_TYPE %d.\n", pdo);
-		return -1;
-	}
-
-	return power_mw;
-}
-
-/*********************************************************************
- * Init VIF Fields
- */
-static void init_vif_fields(struct vif_field_t *vif_fields,
-			struct vif_field_t *vif_app_fields,
-			const char *board)
-{
-	set_vif_field(&vif_fields[VIF_Specification],
-		vif_name[VIF_Specification],
-		NULL,
-		"3.12");
-
-	set_vif_field(&vif_app_fields[Vendor],
-		vif_app_name[Vendor],
-		NULL,
-		VIF_APP_VENDOR_VALUE);
-
-	set_vif_field(&vif_app_fields[Name],
-		vif_app_name[Name],
-		NULL,
-		VIF_APP_NAME_VALUE);
-
-	set_vif_field(&vif_app_fields[Version],
-		vif_app_name[Version],
-		NULL,
-		VIF_APP_VERSION_VALUE);
-
-	set_vif_field(&vif_fields[Vendor_Name],
-		vif_name[Vendor_Name],
-		NULL,
-		VENDOR_NAME_VALUE);
-
-	#if defined(CONFIG_USB_PD_MODEL_PART_NUMBER)
-		set_vif_field(&vif_fields[Model_Part_Number],
-			vif_name[Model_Part_Number],
-			NULL,
-			CONFIG_USB_PD_MODEL_PART_NUMBER);
-	#else
-		if (board && strlen(board) > 0)
-			set_vif_field(&vif_fields[Model_Part_Number],
-				vif_name[Model_Part_Number],
-				NULL,
-				board);
-		else
-			set_vif_field(&vif_fields[Model_Part_Number],
-				vif_name[Model_Part_Number],
-				NULL,
-				"FIX-ME");
-	#endif
-
-	#if defined(CONFIG_USB_PD_PRODUCT_REVISION)
-		set_vif_field(&vif_fields[Product_Revision],
-			vif_name[Product_Revision],
-			NULL,
-			CONFIG_USB_PD_PRODUCT_REVISION);
-	#else
-		set_vif_field(&vif_fields[Product_Revision],
-			vif_name[Product_Revision],
-			NULL,
-			"FIX-ME");
-	#endif
-
-	#if defined(CONFIG_USB_PD_TID)
-		set_vif_field_stis(&vif_fields[TID],
-			vif_name[TID],
-			NULL,
-			CONFIG_USB_PD_TID);
-	#else
-		set_vif_field_stis(&vif_fields[TID],
-			vif_name[TID],
-			NULL,
-			DEFAULT_MISSING_TID);
-	#endif
-
-	set_vif_field(&vif_fields[VIF_Product_Type],
-		vif_name[VIF_Product_Type],
-		"0",
-		"Port Product");
-
-	set_vif_field(&vif_fields[Certification_Type],
-		vif_name[Certification_Type],
-		"0",
-		"End Product");
-}
-
-/*********************************************************************
- * Init VIF/Product Fields
- */
-static void init_vif_product_fields(struct vif_field_t *vif_fields)
-{
-	char hex_str[10];
-
-	sprintf(hex_str, "%04X", USB_VID_GOOGLE);
-	set_vif_field_itss(&vif_fields[Product_VID],
-		vif_product_name[Product_VID],
-		USB_VID_GOOGLE, hex_str);
-}
-
-/*********************************************************************
- * Init VIF/Component[] Fields
- */
-static void init_vif_component_fields(struct vif_field_t *vif_fields,
-			enum bc_1_2_support *bc_support,
-			enum dtype type)
-{
-	#if defined(CONFIG_USB_PD_PORT_LABEL)
-		set_vif_field_stis(&vif_fields[Port_Label],
-			vif_component_name[Port_Label],
-			NULL,
-			CONFIG_USB_PD_PORT_LABEL);
-	#else
-		set_vif_field_stis(&vif_fields[Port_Label],
-			vif_component_name[Port_Label],
-			NULL,
-			component_index);
-	#endif
-
-	set_vif_field(&vif_fields[Connector_Type],
-		vif_component_name[Connector_Type],
-		"2",
-		"Type-C®");
-
-	if (is_usb4_supported()) {
-		int router_index;
-
-		set_vif_field_b(&vif_fields[USB4_Supported],
-			vif_component_name[USB4_Supported],
-			true);
-
-		if (!get_vif_field_tag_number(
-				&vif.Product.USB4RouterList[0]
-					.vif_field[USB4_Router_ID],
-				&router_index)) {
-			router_index = 0;
-		}
-		set_vif_field_itss(&vif_fields[USB4_Router_Index],
-			vif_component_name[USB4_Router_Index],
-			router_index,
-			NULL);
-	} else {
-		set_vif_field_b(&vif_fields[USB4_Supported],
-			vif_component_name[USB4_Supported],
-			false);
-	}
-
-	set_vif_field_b(&vif_fields[USB_PD_Support],
-		vif_component_name[USB_PD_Support],
-		is_usb_pd_supported());
-
-	if (is_usb_pd_supported()) {
-		switch (type) {
-		case SNK:
-			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"0",
-				"Consumer Only");
-			break;
-		case SRC:
-			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"3",
-				"Provider Only");
-			break;
-		case DRP:
-			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"4",
-				"DRP");
-			break;
-		}
-	}
-
-	switch (type) {
-	case SNK:
-		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"1",
-			"SNK");
-		break;
-	case SRC:
-		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"0",
-			"SRC");
-		break;
-	case DRP:
-		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"2",
-			"DRP");
-		break;
-	}
-
-	set_vif_field_b(&vif_fields[Captive_Cable],
-		vif_component_name[Captive_Cable],
-		false);
-
-	set_vif_field_b(&vif_fields[Port_Battery_Powered],
-		vif_component_name[Port_Battery_Powered],
-		IS_ENABLED(CONFIG_BATTERY));
-
-	*bc_support = BC_1_2_SUPPORT_NONE;
-	if (IS_ENABLED(CONFIG_BC12_DETECT_MAX14637))
-		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
-	if (IS_ENABLED(CONFIG_BC12_DETECT_MT6360))
-		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
-	if (IS_ENABLED(CONFIG_BC12_DETECT_PI3USB9201))
-		*bc_support = BC_1_2_SUPPORT_BOTH;
-	if (IS_ENABLED(CONFIG_BC12_DETECT_PI3USB9281))
-		*bc_support = BC_1_2_SUPPORT_PORTABLE_DEVICE;
-
-	switch (*bc_support) {
-	case BC_1_2_SUPPORT_NONE:
-		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"0",
-			"None");
-		break;
-	case BC_1_2_SUPPORT_PORTABLE_DEVICE:
-		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"1",
-			"Portable Device");
-		break;
-	case BC_1_2_SUPPORT_CHARGING_PORT:
-		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"2",
-			"Charging Port");
-		break;
-	case BC_1_2_SUPPORT_BOTH:
-		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"3",
-			"Both");
-		break;
-	}
-}
-
-/*********************************************************************
- * Init VIF/Component[] General PD Fields
- */
-static void init_vif_component_general_pd_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM)) {
-		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
-			vif_component_name[PD_Spec_Revision_Major],
-			"3",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
-			vif_component_name[PD_Spec_Revision_Minor],
-			"0",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Version_Major],
-			vif_component_name[PD_Spec_Version_Major],
-			"2",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
-			vif_component_name[PD_Spec_Version_Minor],
-			"0",
-			NULL);
-
-		set_vif_field(&vif_fields[PD_Specification_Revision],
-			vif_component_name[PD_Specification_Revision],
-			"2",
-			"Revision 3");
-	} else {
-		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
-			vif_component_name[PD_Spec_Revision_Major],
-			"2",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
-			vif_component_name[PD_Spec_Revision_Minor],
-			"0",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Version_Major],
-			vif_component_name[PD_Spec_Version_Major],
-			"1",
-			NULL);
-		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
-			vif_component_name[PD_Spec_Version_Minor],
-			"3",
-			NULL);
-
-		set_vif_field(&vif_fields[PD_Specification_Revision],
-			vif_component_name[PD_Specification_Revision],
-			"1",
-			"Revision 2");
-	}
-
-	set_vif_field_b(&vif_fields[USB_Comms_Capable],
-			vif_component_name[USB_Comms_Capable],
-			is_usb_comms_capable());
-
-	/*
-	 * DR_Swap_To_DFP_Supported
-	 *
-	 * Set to YES if Qualifying Product can respond with an Accept to a
-	 * DR_Swap request to switch from a UFP to a DFP.
-	 *
-	 * If Type_C_State_Machine is set to DRP and Type_C_Can_Act_As_Host
-	 * is set to YES and Type_C_Can_Act_As_Device is set to NO then this
-	 * field shall be set to YES.
-	 *
-	 * If Type_C_State_Machine is set to SNK and either
-	 * Type_C_Can_Act_As_Host or Type_C_Is_Alt_Mode_Controller is set to
-	 * YES, then this field shall be set to YES.
-	 *
-	 * If Type_C_State_Machine is set to SRC and Type_C_Can_Act_As_Device
-	 * is set to YES, then this field shall be set to YES.
-	 *
-	 * If VIF_Product_Type is set to 1 (Cable) or PD_Port_Type is set to
-	 * 5 (eMarker) then this field shall be ignored by Testers.
-	 *
-	 * TODO(b/172437046): USB4 has not been added and this last statement
-	 * needs to be handled when it is:
-	 * If USB4_DFP_Supported is set to YES and Type_C_Port_On_Hub is set
-	 * to NO, then this field shall be set to YES.
-	 */
-	{
-		bool supports_to_dfp = false;
-
-		switch (type) {
-		case SRC:
-			supports_to_dfp = can_act_as_device();
-			break;
-		case SNK:
-			supports_to_dfp = (can_act_as_host() ||
-					   is_alt_mode_controller());
-			break;
-		case DRP:
-			supports_to_dfp = (can_act_as_host() &&
-					   !can_act_as_device());
-			break;
-		}
-
-		set_vif_field_b(&vif_fields[DR_Swap_To_DFP_Supported],
-			vif_component_name[DR_Swap_To_DFP_Supported],
-			supports_to_dfp);
-	}
-
-	/*
-	 * DR_Swap_To_UFP_Supported
-	 *
-	 * Set to YES if Qualifying Product can respond with an Accept to a
-	 * DR_Swap request to switch from a DFP to a UFP.
-	 *
-	 * If Type_C_State_Machine is set to DRP and Type_C_Can_Act_As_Device
-	 * is set to YES and Type_C_Can_Act_As_Host is set to NO then this
-	 * field shall be set to YES.
-	 *
-	 * If Type_C_State_Machine is set to SNK and either
-	 * Type_C_Can_Act_As_Host or Type_C_Is_Alt_Mode_Controller is set to
-	 * YES, then this field shall be set to YES.
-	 *
-	 * If Type_C_State_Machine is set to SRC and Type_C_Can_Act_As_Device
-	 * is set to YES, then this field shall be set to YES.
-	 *
-	 * If VIF_Product_Type is set to 1 (Cable) or PD_Port_Type is set to
-	 * 5 (eMarker) then this field shall be ignored by Testers.
-	 */
-	{
-		bool supports_to_ufp = false;
-
-		switch (type) {
-		case SRC:
-			supports_to_ufp = can_act_as_device();
-			break;
-		case SNK:
-			supports_to_ufp = (can_act_as_host() ||
-					   is_alt_mode_controller());
-			break;
-		case DRP:
-			supports_to_ufp = (can_act_as_device() &&
-					   !can_act_as_host());
-			break;
-		}
-
-		set_vif_field_b(&vif_fields[DR_Swap_To_UFP_Supported],
-			vif_component_name[DR_Swap_To_UFP_Supported],
-			supports_to_ufp);
-	}
-
-	if (is_src()) {
-		/* SRC capable */
-		if (IS_ENABLED(CONFIG_CHARGER))
-			/* USB-C UP bit set */
-			set_vif_field_b(&vif_fields[Unconstrained_Power],
-				vif_component_name[Unconstrained_Power],
-				(src_pdo[0] & PDO_FIXED_UNCONSTRAINED));
-		else {
-			/* Barrel charger being used */
-			int32_t dedicated_charge_port_count = 0;
-
-			#ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT
-				dedicated_charge_port_count =
-					CONFIG_DEDICATED_CHARGE_PORT_COUNT;
-			#endif
-
-			set_vif_field_b(&vif_fields[Unconstrained_Power],
-				vif_component_name[Unconstrained_Power],
-				(dedicated_charge_port_count > 0));
-		}
-	} else {
-		/* Not SRC capable */
-		set_vif_field_b(&vif_fields[Unconstrained_Power],
-			vif_component_name[Unconstrained_Power],
-			false);
-	}
-
-	set_vif_field_b(&vif_fields[VCONN_Swap_To_On_Supported],
-		vif_component_name[VCONN_Swap_To_On_Supported],
-		IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
-
-	set_vif_field_b(&vif_fields[VCONN_Swap_To_Off_Supported],
-		vif_component_name[VCONN_Swap_To_Off_Supported],
-		IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
-
-	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_UFP],
-		vif_component_name[Responds_To_Discov_SOP_UFP],
-		does_respond_to_discov_sop_ufp());
-
-	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_DFP],
-		vif_component_name[Responds_To_Discov_SOP_DFP],
-		does_respond_to_discov_sop_dfp());
-
-	set_vif_field_b(&vif_fields[Attempts_Discov_SOP],
-		vif_component_name[Attempts_Discov_SOP],
-		((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) ||
-		 (type != SRC)));
-
-	set_vif_field_b(&vif_fields[Chunking_Implemented_SOP],
-		vif_component_name[Chunking_Implemented_SOP],
-		(IS_ENABLED(CONFIG_USB_PD_REV30) &&
-		 IS_ENABLED(CONFIG_USB_PRL_SM)));
-
-	set_vif_field_b(&vif_fields[Unchunked_Extended_Messages_Supported],
-		vif_component_name[Unchunked_Extended_Messages_Supported],
-		false);
-
-	if (IS_ENABLED(CONFIG_USB_PD_MANUFACTURER_INFO)) {
-		char hex_str[10];
-
-		set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port],
-			vif_component_name[Manufacturer_Info_Supported_Port],
-			true);
-
-		sprintf(hex_str, "%04X", USB_VID_GOOGLE);
-		set_vif_field_itss(&vif_fields[Manufacturer_Info_VID_Port],
-			vif_component_name[Manufacturer_Info_VID_Port],
-			USB_VID_GOOGLE, hex_str);
-
-		#if defined(CONFIG_USB_PID)
-			sprintf(hex_str, "%04X", CONFIG_USB_PID);
-			set_vif_field_itss(&vif_fields[
-				Manufacturer_Info_PID_Port],
-				vif_component_name[Manufacturer_Info_PID_Port],
-				CONFIG_USB_PID, hex_str);
-		#else
-			sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
-			set_vif_field_itss(&vif_fields[
-				Manufacturer_Info_PID_Port],
-				vif_component_name[Manufacturer_Info_PID_Port],
-				DEFAULT_MISSING_PID, hex_str);
-		#endif
-	} else {
-		set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port],
-			vif_component_name[Manufacturer_Info_Supported_Port],
-			false);
-	}
-
-	set_vif_field_b(&vif_fields[Security_Msgs_Supported_SOP],
-		vif_component_name[Security_Msgs_Supported_SOP],
-		IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS));
-
-	#if defined(CONFIG_NUM_FIXED_BATTERIES)
-		set_vif_field_itss(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			CONFIG_NUM_FIXED_BATTERIES, NULL);
-	#elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-		set_vif_field(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			"0", NULL);
-	#else
-		set_vif_field(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			"1", NULL);
-	#endif
-
-	set_vif_field(&vif_fields[Num_Swappable_Battery_Slots],
-		vif_component_name[Num_Swappable_Battery_Slots],
-		"0", NULL);
-
-	set_vif_field(&vif_fields[ID_Header_Connector_Type_SOP],
-		vif_component_name[ID_Header_Connector_Type_SOP],
-		"2", "USB Type-C® Receptacle");
-}
-
-/*********************************************************************
- * Init VIF/Component[] SOP* Capabilities Fields
- */
-static void init_vif_component_sop_capabilities_fields(
-			struct vif_field_t *vif_fields)
-{
-	set_vif_field_b(&vif_fields[SOP_Capable],
-		vif_component_name[SOP_Capable],
-		can_act_as_host());
-
-	set_vif_field_b(&vif_fields[SOP_P_Capable],
-		vif_component_name[SOP_P_Capable],
-		IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
-
-	set_vif_field_b(&vif_fields[SOP_PP_Capable],
-		vif_component_name[SOP_PP_Capable],
-		IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
-
-	set_vif_field_b(&vif_fields[SOP_P_Debug_Capable],
-		vif_component_name[SOP_P_Debug_Capable],
-		false);
-
-	set_vif_field_b(&vif_fields[SOP_PP_Debug_Capable],
-		vif_component_name[SOP_PP_Debug_Capable],
-		false);
-}
-
-/*********************************************************************
- * Init VIF/Component[] USB Type-C Fields
- */
-static void init_vif_component_usb_type_c_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
-{
-	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SRC],
-		vif_component_name[Type_C_Implements_Try_SRC],
-		IS_ENABLED(CONFIG_USB_PD_TRY_SRC));
-
-	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SNK],
-		vif_component_name[Type_C_Implements_Try_SNK],
-		false);
-
-	{
-		int rp = CONFIG_USB_PD_PULLUP;
-
-		#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
-			rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
-		#endif
-
-		switch (rp) {
-		case 0:
-			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"0", "Default");
-			break;
-		case 1:
-			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"1", "1.5A");
-			break;
-		case 2:
-			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"2", "3A");
-			break;
-		default:
-			set_vif_field_itss(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				rp, NULL);
-		}
-	}
-
-	if (type == SNK)
-		set_vif_field_b(
-			&vif_fields[Type_C_Supports_VCONN_Powered_Accessory],
-			vif_component_name
-				[Type_C_Supports_VCONN_Powered_Accessory],
-			false);
-
-	set_vif_field_b(&vif_fields[Type_C_Is_VCONN_Powered_Accessory],
-		vif_component_name[Type_C_Is_VCONN_Powered_Accessory],
-		false);
-
-	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SRC],
-		vif_component_name[Type_C_Is_Debug_Target_SRC],
-		true);
-
-	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SNK],
-		vif_component_name[Type_C_Is_Debug_Target_SNK],
-		true);
-
-	set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Host],
-		vif_component_name[Type_C_Can_Act_As_Host],
-		can_act_as_host());
-
-	set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Controller],
-		vif_component_name[Type_C_Is_Alt_Mode_Controller],
-		is_alt_mode_controller());
-
-	if (can_act_as_device()) {
-		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
-			vif_component_name[Type_C_Can_Act_As_Device],
-			true);
-
-		if (is_usb_pd_supported() &&
-		    does_respond_to_discov_sop_ufp())
-			set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter],
-				vif_component_name[Type_C_Is_Alt_Mode_Adapter],
-				IS_ENABLED(CONFIG_USB_ALT_MODE_ADAPTER));
-	} else {
-		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
-			vif_component_name[Type_C_Can_Act_As_Device],
-			false);
-	}
-
-	{
-		int ps = POWER_UFP;
-
-		if (IS_ENABLED(CONFIG_BATTERY))
-			ps = POWER_BOTH;
-#if defined(CONFIG_DEDICATED_CHARGE_PORT_COUNT)
-		else if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 1)
-			ps = POWER_EXTERNAL;
-		else if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 1)
-			ps = POWER_BOTH;
-#endif
-
-		switch (ps) {
-		case POWER_EXTERNAL:
-			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"0", "Externally Powered");
-			break;
-		case POWER_UFP:
-			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"1", "UFP-powered");
-			break;
-		case POWER_BOTH:
-			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"2", "Both");
-			break;
-		default:
-			set_vif_field_itss(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				ps, NULL);
-		}
-	}
-
-	set_vif_field_b(&vif_fields[Type_C_Port_On_Hub],
-		vif_component_name[Type_C_Port_On_Hub],
-		false);
-
-	set_vif_field_b(&vif_fields[Type_C_Supports_Audio_Accessory],
-		vif_component_name[Type_C_Supports_Audio_Accessory],
-		false);
-
-	set_vif_field_b(&vif_fields[Type_C_Sources_VCONN],
-		vif_component_name[Type_C_Sources_VCONN],
-		IS_ENABLED(CONFIG_USBC_VCONN));
-}
-
-/*********************************************************************
- * Init VIF/Component[] USB Data - Upstream Facing Port Fields
- *
- * TODO: Generic todo to fill in additional fields as the need presents
- * itself
- *
- * Fields that are not currently being initialized
- *
- * vif_Component
- *	Device_Contains_Captive_Retimer		booleanFieldType
- *	Device_Truncates_DP_For_tDHPResponse	booleanFieldType
- *	Device_Gen1x1_tLinkTurnaround		numericFieldType
- *	Device_Gen2x1_tLinkTurnaround		numericFieldType
- */
-static void init_vif_component_usb_data_ufp_fields(
-			struct vif_field_t *vif_fields)
-{
-	/*
-	 * TOTO(b:172441959) Adjust the speed based on CONFIG_
-	 */
-	enum usb_speed ds = USB_GEN11;
-	bool supports_usb_data;
-
-	/*
-	 * The fields in this section shall be ignored by Testers unless
-	 * Connector_Type is set to 1 (Type-B) or 3 (Micro A/B), or
-	 * Connector_Type is set to 2 (Type-C) and Type_C_Can_Act_As_Device
-	 * is set to YES.
-	 *
-	 * NOTE: We currently are always a Connector_Type of 2 (Type-C)
-	 */
-	if (!can_act_as_device())
-		return;
-
-	supports_usb_data = does_support_device_usb_data();
-	set_vif_field_b(
-		&vif_fields[Device_Supports_USB_Data],
-		vif_component_name[Device_Supports_USB_Data],
-		supports_usb_data);
-
-	if (supports_usb_data) {
-		switch (ds) {
-		case USB_2:
-			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_2, "USB 2");
-			break;
-		case USB_GEN11:
-			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN11, "USB 3.2 GEN 1x1");
-			break;
-		case USB_GEN21:
-			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN21, "USB 3.2 GEN 2x1");
-			break;
-		case USB_GEN12:
-			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN12, "USB 3.2 GEN 1x2");
-			break;
-		case USB_GEN22:
-			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN22, "USB 3.2 GEN 2x2");
-			break;
-		}
-	}
-}
-
-/*********************************************************************
- * Init VIF/Component[] USB Data - Downstream Facing Port Fields
- *
- * TODO: Generic todo to fill in additional fields as the need presents
- * itself
- *
- * Fields that are not currently being initialized
- *
- * vif_Component
- *	Hub_Port_Number				numericFieldType
- *	Host_Truncates_DP_For_tDHPResponse	booleanFieldType
- *	Host_Gen1x1_tLinkTurnaround		numericFieldType
- *	Host_Gen2x1_tLinkTurnaround		numericFieldType
- *	Host_Suspend_Supported			booleanFieldType
- */
-static void init_vif_component_usb_data_dfp_fields(
-			struct vif_field_t *vif_fields)
-{
-	/*
-	 * TOTO(b:172438944) Adjust the speed based on CONFIG_
-	 */
-	enum usb_speed ds = USB_GEN11;
-	bool supports_usb_data;
-	bool is_dfp_on_hub;
-
-	/*
-	 * The fields in this section shall be ignored by Testers unless
-	 * Connector_Type is set to 0 (Type-A), or
-	 * COnnector Type is set to 3 (Micro A/B); or
-	 * Connector_Type is set to 2 (Type-C) and Type_C_Can_Act_As_Host
-	 * is set to YES
-	 *
-	 * NOTE: We currently are always a Connector_Type of 2 (Type-C)
-	 */
-	if (!can_act_as_host())
-		return;
-
-	supports_usb_data = does_support_host_usb_data();
-	set_vif_field_b(&vif_fields[Host_Supports_USB_Data],
-		vif_component_name[Host_Supports_USB_Data],
-		supports_usb_data);
-
-	if (supports_usb_data) {
-		switch (ds) {
-		case USB_2:
-			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_2, "USB 2");
-			break;
-		case USB_GEN11:
-			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN11, "USB 3.2 GEN 1x1");
-			break;
-		case USB_GEN21:
-			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN21, "USB 3.2 GEN 2x1");
-			break;
-		case USB_GEN12:
-			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN12, "USB 3.2 GEN 1x2");
-			break;
-		case USB_GEN22:
-			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN22, "USB 3.2 GEN 2x2");
-			break;
-		}
-
-		if (!get_vif_field_tag_bool(
-				&vif_fields[Type_C_Port_On_Hub],
-				&is_dfp_on_hub))
-			is_dfp_on_hub = false;
-
-		set_vif_field_b(&vif_fields[Is_DFP_On_Hub],
-			vif_component_name[Is_DFP_On_Hub],
-			is_dfp_on_hub);
-
-		set_vif_field_b(&vif_fields[Host_Contains_Captive_Retimer],
-			vif_component_name[Host_Contains_Captive_Retimer],
-			false);
-
-		set_vif_field_b(&vif_fields[Host_Is_Embedded],
-			vif_component_name[Host_Is_Embedded],
-			false);
-	}
-}
-
-/*********************************************************************
- * Init VIF/Component[] PD Source Fields
- */
-static int init_vif_component_pd_source_fields(
-			struct vif_field_t *vif_fields,
-			struct vif_srcPdoList_t *comp_src_pdo_list,
-			int32_t *src_max_power,
-			enum dtype type)
-{
-	if (type == DRP || type == SRC) {
-		int i;
-		char str[40];
-
-		/* Source PDOs */
-		for (i = 0; i < src_pdo_cnt; i++) {
-			int32_t pwr;
-
-			pwr = init_vif_src_pdo(&comp_src_pdo_list[i],
-					       src_pdo[i]);
-			if (pwr < 0) {
-				fprintf(stderr, "ERROR: Setting SRC PDO.\n");
-				return 1;
-			}
-
-			if (pwr > *src_max_power)
-				*src_max_power = pwr;
-		}
-
-		sprintf(str, "%d mW", *src_max_power);
-		set_vif_field_itss(&vif_fields[PD_Power_As_Source],
-			vif_component_name[PD_Power_As_Source],
-			*src_max_power, str);
-	}
-
-	if (type == DRP || type == SRC)
-		set_vif_field_b(&vif_fields[USB_Suspend_May_Be_Cleared],
-			vif_component_name[USB_Suspend_May_Be_Cleared],
-			false);
-
-	if (type == DRP || type == SRC)
-		set_vif_field_b(&vif_fields[Sends_Pings],
-			vif_component_name[Sends_Pings],
-			false);
-
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    type == DRP &&
-	    IS_ENABLED(CONFIG_USB_PD_FRS))
-		set_vif_field(&vif_fields[
-			FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
-			vif_component_name
-			[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
-			"3", "3A @ 5V");
-	else
-		set_vif_field(&vif_fields[
-			FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
-			vif_component_name
-			[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
-			"0", "FR_Swap not supported");
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM))
-		set_vif_field_b(&vif_fields[Master_Port],
-				vif_component_name[Master_Port],
-				false);
-
-	if (type == DRP || type == SRC)
-		set_vif_field_itss(&vif_fields[Num_Src_PDOs],
-			vif_component_name[Num_Src_PDOs],
-			src_pdo_cnt, NULL);
-
-	if (type == DRP || type == SRC) {
-		if (IS_ENABLED(CONFIG_USBC_OCP)) {
-			int resp = 0;
-
-			set_vif_field_b(&vif_fields[PD_OC_Protection],
-				vif_component_name[PD_OC_Protection],
-				true);
-
-			switch (resp) {
-			case 0:
-				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"0", "Over-Current Response");
-				break;
-			case 1:
-				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"1", "Under-Voltage Response");
-				break;
-			case 2:
-				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"2", "Both");
-				break;
-			default:
-				set_vif_field_itss(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					resp, NULL);
-			}
-		} else {
-			set_vif_field_b(&vif_fields[PD_OC_Protection],
-				vif_component_name[PD_OC_Protection],
-				false);
-		}
-	}
-
-	return 0;
-}
-
-/*********************************************************************
- * Init VIF/Component[] PD Sink Fields
- */
-static int init_vif_component_pd_sink_fields(
-			struct vif_field_t *vif_fields,
-			struct vif_snkPdoList_t *comp_snk_pdo_list,
-			enum dtype type)
-{
-	int i;
-	int32_t snk_max_power = 0;
-	char str[40];
-
-	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type == SRC)
-		return 0;
-
-	/* Sink PDOs */
-	for (i = 0; i < pd_snk_pdo_cnt; i++) {
-		int32_t pwr;
-
-		pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i],
-				       pd_snk_pdo[i]);
-		if (pwr < 0) {
-			fprintf(stderr, "ERROR: Setting SNK PDO.\n");
-			return 1;
-		}
-
-		if (pwr > snk_max_power)
-			snk_max_power = pwr;
-	}
-
-	sprintf(str, "%d mW", snk_max_power);
-	set_vif_field_itss(&vif_fields[PD_Power_As_Sink],
-		vif_component_name[PD_Power_As_Sink],
-		snk_max_power, str);
-
-	set_vif_field_b(&vif_fields[No_USB_Suspend_May_Be_Set],
-		vif_component_name[No_USB_Suspend_May_Be_Set],
-		true);
-
-	set_vif_field_b(&vif_fields[GiveBack_May_Be_Set],
-		vif_component_name[GiveBack_May_Be_Set],
-		IS_ENABLED(CONFIG_USB_PD_GIVE_BACK));
-
-	set_vif_field_b(&vif_fields[Higher_Capability_Set],
-		vif_component_name[Higher_Capability_Set],
-		false);
-
-	set_vif_field(&vif_fields[
-		FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
-		vif_component_name
-			[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
-		"0", "FR_Swap not supported");
-
-	set_vif_field_itss(&vif_fields[Num_Snk_PDOs],
-		vif_component_name[Num_Snk_PDOs],
-		pd_snk_pdo_cnt, NULL);
-
-	return 0;
-}
-
-/*********************************************************************
- * Init VIF/Component[] PD Dual Role Fields
- */
-static void init_vif_component_pd_dual_role_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
-{
-	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type != DRP)
-		return;
-
-	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Src],
-		vif_component_name[Accepts_PR_Swap_As_Src],
-		true);
-
-	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Snk],
-		vif_component_name[Accepts_PR_Swap_As_Snk],
-		true);
-
-	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Src],
-		vif_component_name[Requests_PR_Swap_As_Src],
-		true);
-
-	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Snk],
-		vif_component_name[Requests_PR_Swap_As_Snk],
-		true);
-
-	set_vif_field_b(&vif_fields[FR_Swap_Supported_As_Initial_Sink],
-		vif_component_name[FR_Swap_Supported_As_Initial_Sink],
-		IS_ENABLED(CONFIG_USB_PD_FRS));
-}
-
-/*********************************************************************
- * Init VIF/Component[] SOP Discovery Fields
- *
- * TODO: Generic todo to fill in additional fields as the need presents
- * itself
- *
- * Fields that are not currently being initialized
- *
- * vif_Component
- *	Product_Type_UFP_SOP			numericFieldType
- *	Product_Type_DFP_SOP			numericFieldType
- *	Modal_Operation_Supported_SOP		booleanFieldType
- *	Num_SVIDs_Min_SOP			numericFieldType
- *	Num_SVIDs_Max_SOP			numericFieldType
- *	SVID_Fixed_SOP				booleanFieldType
- */
-static void init_vif_component_sop_discovery_fields(
-			struct vif_field_t *vif_fields)
-{
-	char hex_str[10];
-
-	/*
-	 * The fields in this section shall be ignored by Testers unless at
-	 * least one of Responds_To_Discov_SOP_UFP and
-	 * Responds_To_Discov_SOP_DFP is set to YES.
-	 */
-	if (!does_respond_to_discov_sop_ufp() &&
-	    !does_respond_to_discov_sop_dfp())
-		return;
-
-	set_vif_field(&vif_fields[XID_SOP],
-		vif_component_name[XID_SOP],
-		"0",
-		NULL);
-
-	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Host_SOP],
-		vif_component_name[Data_Capable_As_USB_Host_SOP],
-		can_act_as_host());
-
-	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Device_SOP],
-		vif_component_name[Data_Capable_As_USB_Device_SOP],
-		can_act_as_device());
-
-	if (does_respond_to_discov_sop_dfp() &&
-	    is_usb4_supported()) {
-#if defined(CONFIG_USB_PD_PORT_LABEL)
-		set_vif_field_stis(&vif_fields[DFP_VDO_Port_Number],
-			vif_component_name[DFP_VDO_Port_Number],
-			NULL,
-			CONFIG_USB_PD_PORT_LABEL);
-#else
-		set_vif_field_stis(&vif_fields[DFP_VDO_Port_Number],
-			vif_component_name[DFP_VDO_Port_Number],
-			NULL,
-			component_index);
-#endif
-	}
-
-	sprintf(hex_str, "%04X", USB_VID_GOOGLE);
-	set_vif_field_itss(&vif_fields[USB_VID_SOP],
-		vif_component_name[USB_VID_SOP],
-		USB_VID_GOOGLE, hex_str);
-
-	#if defined(CONFIG_USB_PID)
-		sprintf(hex_str, "%04X", CONFIG_USB_PID);
-		set_vif_field_itss(&vif_fields[PID_SOP],
-			vif_component_name[PID_SOP],
-			CONFIG_USB_PID, hex_str);
-	#else
-		sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
-		set_vif_field_itss(&vif_fields[PID_SOP],
-			vif_component_name[PID_SOP],
-			DEFAULT_MISSING_PID, hex_str);
-	#endif
-
-	#if defined(CONFIG_USB_BCD_DEV)
-		sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV);
-		set_vif_field_itss(&vif_fields[bcdDevice_SOP],
-			vif_component_name[bcdDevice_SOP],
-			CONFIG_USB_BCD_DEV, hex_str);
-	#else
-		sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV);
-		set_vif_field_itss(&vif_fields[bcdDevice_SOP],
-			vif_component_name[bcdDevice_SOP],
-			DEFAULT_MISSING_BCD_DEV, hex_str);
-	#endif
-}
-
-/*********************************************************************
- * Init VIF/Component[] Battery Charging 1.2 Fields
- */
-static void init_vif_component_bc_1_2_fields(
-			struct vif_field_t *vif_fields,
-			enum bc_1_2_support bc_support)
-{
-	if (bc_support == BC_1_2_SUPPORT_CHARGING_PORT ||
-	    bc_support == BC_1_2_SUPPORT_BOTH)
-		set_vif_field(&vif_fields[BC_1_2_Charging_Port_Type],
-			vif_component_name[BC_1_2_Charging_Port_Type],
-			"1",
-			"CDP");
-}
-
-/*********************************************************************
- * Init VIF/Component[] Product Power Fields
- *
- * TODO: Generic todo to fill in additional fields as the need presents
- * itself
- *
- * Fields that are not currently being initialized
- *
- * vif_Component
- *	Port_Source_Power_Gang			nonEmptyString
- *	Port_Source_Power_Gang_Max_Power	numericFieldType
- */
-static void init_vif_component_product_power_fields(
-			struct vif_field_t *vif_fields,
-			int32_t src_max_power,
-			enum dtype type)
-{
-	if (type == DRP || type == SRC) {
-		char str[10];
-
-		sprintf(str, "%d mW", src_max_power);
-		set_vif_field_itss(&vif_fields[Product_Total_Source_Power_mW],
-			vif_component_name[Product_Total_Source_Power_mW],
-			src_max_power, str);
-	}
-
-	if (type == DRP || type == SRC)
-		set_vif_field(&vif_fields[Port_Source_Power_Type],
-			vif_component_name[Port_Source_Power_Type],
-			"0", "Assured");
-}
-
-static int gen_vif(const char *board,
-		   struct vif_t *vif)
-{
-	int max_component_index = board_get_usb_pd_port_count();
-
-	/*********************************************************************
-	 * Initialize the vif structure
-	 */
-	init_vif_fields(
-			vif->vif_field,
-			vif->vif_app_field,
-			board);
-
-	init_vif_product_fields(
-			vif->Product.vif_field);
-
-	for (component_index = 0;
-	     component_index < max_component_index;
-	     component_index++) {
-		int override_value;
-		bool was_overridden;
-		enum dtype type;
-		int32_t src_max_power = 0;
-		enum bc_1_2_support bc_support = BC_1_2_SUPPORT_NONE;
-
-		/* Determine if we are DRP, SRC or SNK */
-		was_overridden =
-			get_vif_field_tag_number(
-				&vif->Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
-		if (was_overridden) {
-			switch (override_value) {
-			case SRC:
-			case SNK:
-			case DRP:
-				type = (enum dtype)override_value;
-				break;
-			default:
-				was_overridden = false;
-			}
-		}
-		if (!was_overridden) {
-			was_overridden =
-				get_vif_field_tag_number(
-					&vif->Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
-			if (was_overridden) {
-				switch (override_value) {
-				case PORT_CONSUMER_ONLY:	/* SNK */
-					type = SNK;
-					break;
-				case PORT_PROVIDER_ONLY:	/* SRC */
-					type = SRC;
-					break;
-				case PORT_DRP:			/* DRP */
-					type = DRP;
-					break;
-				default:
-					was_overridden = false;
-				}
-			}
-		}
-		if (!was_overridden) {
-			if (is_drp())
-				type = DRP;
-			else if (is_src() && is_snk())
-				/*
-				 * No DRP with SRC and SNK PDOs detected. So
-				 * ignore.  ie. Twinkie or Plankton
-				 */
-				return 0;
-			else if (is_src())
-				type = SRC;
-			else if (is_snk())
-				type = SNK;
-			else
-				return 1;
-		}
-
-
-		init_vif_component_fields(
-				vif->Component[component_index].vif_field,
-				&bc_support,
-				type);
-
-		init_vif_component_general_pd_fields(
-				vif->Component[component_index].vif_field,
-				type);
-
-		init_vif_component_sop_capabilities_fields(
-				vif->Component[component_index].vif_field);
-
-		init_vif_component_usb_type_c_fields(
-				vif->Component[component_index].vif_field,
-				type);
-
-		init_vif_component_usb_data_ufp_fields(
-				vif->Component[component_index].vif_field);
-
-		init_vif_component_usb_data_dfp_fields(
-				vif->Component[component_index].vif_field);
-
-		if (init_vif_component_pd_source_fields(
-				vif->Component[component_index].vif_field,
-				vif->Component[component_index].SrcPdoList,
-				&src_max_power,
-				type))
-			return 1;
-
-		if (init_vif_component_pd_sink_fields(
-				vif->Component[component_index].vif_field,
-				vif->Component[component_index].SnkPdoList,
-				type))
-			return 1;
-
-		init_vif_component_pd_dual_role_fields(
-				vif->Component[component_index].vif_field,
-				type);
-
-		init_vif_component_sop_discovery_fields(
-				vif->Component[component_index].vif_field);
-
-		init_vif_component_bc_1_2_fields(
-				vif->Component[component_index].vif_field,
-				bc_support);
-
-		init_vif_component_product_power_fields(
-				vif->Component[component_index].vif_field,
-				src_max_power,
-				type);
-	}
-
-	return 0;
-}
-/*
- * VIF Structure Initialization from Config Functions
- *****************************************************************************/
-
-int main(int argc, char **argv)
-{
-	int nopt;
-	int ret;
-	const char *out = NULL;
-	const char *board = NULL;
-	bool do_config_init = true;
-	DIR *vifdir;
-	char *name;
-	int name_size;
-	const char * const short_opt = "hb:o:nv:";
-	const struct option long_opts[] = {
-		{ "help",      0, NULL, 'h' },
-		{ "board",     1, NULL, 'b' },
-		{ "out",       1, NULL, 'o' },
-		{ "no-config", 0, NULL, 'n' },
-		{ "over",      1, NULL, 'v' },
-		{ NULL }
-	};
-
-	/* Clear the VIF structure */
-	memset(&vif, 0, sizeof(struct vif_t));
-
-	do {
-		nopt = getopt_long(argc, argv, short_opt, long_opts, NULL);
-		switch (nopt) {
-		case 'h': /* -h or --help */
-			printf("USAGE: genvif -b|--board <board name>\n"
-			       "              -o|--out <out directory>\n"
-			       "              [-n|--no-config]\n"
-			       "              [-v|--over <override XML file>]\n");
-			return 1;
-
-		case 'b': /* -b or --board */
-			board = optarg;
-			break;
-
-		case 'o': /* -o or --out */
-			out = optarg;
-			break;
-
-		case 'n': /* -n or --no-config */
-			do_config_init = false;
-			break;
-
-		case 'v': /* -v or --over */
-			/* Handle overrides */
-			if (override_gen_vif(optarg, &vif))
-				return 1;
-			break;
-
-		case -1:
-			break;
-
-		default:
-			abort();
-		}
-	} while (nopt != -1);
-
-	if (out == NULL || board == NULL)
-		return 1;
-
-	/* Make sure VIF directory exists */
-	vifdir = opendir(out);
-	if (vifdir == NULL) {
-		fprintf(stderr, "ERROR: %s directory does not exist.\n", out);
-		return 1;
-	}
-	closedir(vifdir);
-
-	init_src_pdos();
-
-	/* Finish CONFIG initialization file */
-	if (do_config_init) {
-		ret = gen_vif(board, &vif);
-		if (ret)
-			return 1;
-	}
-
-	name_size = asprintf(&name, "%s/%s_vif.xml", out, board);
-	if (name_size < 0) {
-		fprintf(stderr, "ERROR: Out of memory.\n");
-		return 1;
-	}
-
-	/* Format the structure in XML and output it to file */
-	ret = vif_output_xml(name, &vif);
-
-	free(name);
-	return ret;
-}
diff --git a/util/genvif.h b/util/genvif.h
deleted file mode 100644
index 634dbfc861..0000000000
--- a/util/genvif.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __GENVIF_H__
-#define __GENVIF_H__
-
-#define MAX_NUM_CABLE_SVIDS 10
-#define MAX_NUM_CABLE_SVID_MODES 10
-#define MAX_NUM_COMPONENTS 10
-#define MAX_NUM_PCIE_ENDPOINTS 10
-#define MAX_NUM_SNK_PDOS 10
-#define MAX_NUM_SRC_PDOS 10
-#define MAX_NUM_SOP_SVIDS 10
-#define MAX_NUM_SOP_SVID_MODES 10
-#define MAX_NUM_USB4_ROUTERS 16
-
-
-struct vif_field_t {
-	const char *name;
-	char *tag_value;
-	char *str_value;
-};
-
-
-enum vif_cableSVIDModeList_indexes {
-	SVID_Mode_Enter,			/* booleanFieldType */
-	SVID_Mode_Recog_Mask,			/* numericFieldType */
-	SVID_Mode_Recog_Value,			/* numericFieldType */
-	CableSVID_Mode_Indexes
-};
-struct vif_cableSVIDModeList_t {
-	struct vif_field_t		vif_field[CableSVID_Mode_Indexes];
-};
-
-
-enum vif_cableSVIDList_indexes {
-	SVID,					/* numericFieldType */
-	SVID_Modes_Fixed,			/* booleanFieldType */
-	SVID_Num_Modes_Min,			/* numericFieldType */
-	SVID_Num_Modes_Max,			/* numericFieldType */
-	CableSVID_Indexes
-};
-struct vif_cableSVIDList_t {
-	struct vif_field_t		vif_field[CableSVID_Indexes];
-
-	struct vif_cableSVIDModeList_t
-			CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES];
-};
-
-
-enum vif_sopSVIDModeList_indexes {
-	SVID_Mode_Enter_SOP,			/* booleanFieldType */
-	SVID_Mode_Recog_Mask_SOP,		/* numericFieldType */
-	SVID_Mode_Recog_Value_SOP,		/* numericFieldType */
-	SopSVID_Mode_Indexes
-};
-struct vif_sopSVIDModeList_t {
-	struct vif_field_t		vif_field[SopSVID_Mode_Indexes];
-};
-
-
-enum vif_sopSVIDList_indexes {
-	SVID_SOP,				/* numericFieldType */
-	SVID_Modes_Fixed_SOP,			/* booleanFieldType */
-	SVID_Num_Modes_Min_SOP,			/* numericFieldType */
-	SVID_Num_Modes_Max_SOP,			/* numericFieldType */
-	SopSVID_Indexes
-};
-struct vif_sopSVIDList_t {
-	struct vif_field_t		vif_field[SopSVID_Indexes];
-
-	struct vif_sopSVIDModeList_t
-			SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES];
-};
-
-
-enum vif_snkPdoList_indexes {
-	Snk_PDO_Supply_Type,			/* numericFieldType */
-	Snk_PDO_Voltage,			/* numericFieldType */
-	Snk_PDO_Op_Power,			/* numericFieldType */
-	Snk_PDO_Min_Voltage,			/* numericFieldType */
-	Snk_PDO_Max_Voltage,			/* numericFieldType */
-	Snk_PDO_Op_Current,			/* numericFieldType */
-	Snk_PDO_Indexes
-};
-struct vif_snkPdoList_t {
-	struct vif_field_t		vif_field[Snk_PDO_Indexes];
-};
-
-
-enum vif_srcPdoList_indexes {
-	Src_PDO_Supply_Type,			/* numericFieldType */
-	Src_PDO_Peak_Current,			/* numericFieldType */
-	Src_PDO_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Current,			/* numericFieldType */
-	Src_PDO_Min_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Power,			/* numericFieldType */
-	Src_PD_OCP_OC_Debounce,			/* numericFieldType */
-	Src_PD_OCP_OC_Threshold,		/* numericFieldType */
-	Src_PD_OCP_UV_Debounce,			/* numericFieldType */
-	Src_PD_OCP_UV_Threshold_Type,		/* numericFieldType */
-	Src_PD_OCP_UV_Threshold,		/* numericFieldType */
-	Src_PDO_Indexes
-};
-struct vif_srcPdoList_t {
-	struct vif_field_t		vif_field[Src_PDO_Indexes];
-};
-
-
-enum vif_PCIeEndpointListType_indexes {
-	USB4_PCIe_Endpoint_Vendor_ID,		/* numericFieldType */
-	USB4_PCIe_Endpoint_Device_ID,		/* numericFieldType */
-	USB4_PCIe_Endpoint_Class_Code,		/* numericFieldType */
-	PCIe_Endpoint_Indexes
-};
-struct vif_PCIeEndpointListType_t {
-	struct vif_field_t		vif_field[PCIe_Endpoint_Indexes];
-};
-
-
-enum vif_Usb4RouterListType_indexes {
-	USB4_Router_ID,				/* numericFieldType */
-	USB4_Silicon_VID,			/* numericFieldType */
-	USB4_Num_Lane_Adapters,			/* numericFieldType */
-	USB4_Num_USB3_DN_Adapters,		/* numericFieldType */
-	USB4_Num_DP_IN_Adapters,		/* numericFieldType */
-	USB4_Num_DP_OUT_Adapters,		/* numericFieldType */
-	USB4_Num_PCIe_DN_Adapters,		/* numericFieldType */
-	USB4_TBT3_Not_Supported,		/* numericFieldType */
-	USB4_PCIe_Wake_Supported,		/* booleanFieldType */
-	USB4_USB3_Wake_Supported,		/* booleanFieldType */
-	USB4_Num_Unused_Adapters,		/* numericFieldType */
-	USB4_TBT3_VID,				/* numericFieldType */
-	USB4_PCIe_Switch_Vendor_ID,		/* numericFieldType */
-	USB4_PCIe_Switch_Device_ID,		/* numericFieldType */
-	USB4_Num_PCIe_Endpoints,		/* numericFieldType */
-	USB4_Router_Indexes
-};
-struct vif_Usb4RouterListType_t {
-	struct vif_field_t		vif_field[USB4_Router_Indexes];
-
-	struct vif_PCIeEndpointListType_t
-			PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS];
-};
-
-
-enum vif_Component_indexes {
-	Port_Label,				/* nonEmptyString */
-	Connector_Type,				/* numericFieldType */
-	USB4_Supported,				/* booleanFieldType */
-	USB4_Router_Index,			/* numericFieldType */
-	USB_PD_Support,				/* booleanFieldType */
-	PD_Port_Type,				/* numericFieldType */
-	Type_C_State_Machine,			/* numericFieldType */
-	Captive_Cable,				/* booleanFieldType */
-	Port_Battery_Powered,			/* booleanFieldType */
-	BC_1_2_Support,				/* numericFieldType */
-	PD_Spec_Revision_Major,			/* numericFieldType */
-	PD_Spec_Revision_Minor,			/* numericFieldType */
-	PD_Spec_Version_Major,			/* numericFieldType */
-	PD_Spec_Version_Minor,			/* numericFieldType */
-	PD_Specification_Revision,		/* numericFieldType */
-	USB_Comms_Capable,			/* booleanFieldType */
-	DR_Swap_To_DFP_Supported,		/* booleanFieldType */
-	DR_Swap_To_UFP_Supported,		/* booleanFieldType */
-	Unconstrained_Power,			/* booleanFieldType */
-	VCONN_Swap_To_On_Supported,		/* booleanFieldType */
-	VCONN_Swap_To_Off_Supported,		/* booleanFieldType */
-	Responds_To_Discov_SOP_UFP,		/* booleanFieldType */
-	Responds_To_Discov_SOP_DFP,		/* booleanFieldType */
-	Attempts_Discov_SOP,			/* booleanFieldType */
-	Chunking_Implemented_SOP,		/* booleanFieldType */
-	Unchunked_Extended_Messages_Supported,	/* booleanFieldType */
-	Manufacturer_Info_Supported_Port,	/* booleanFieldType */
-	Manufacturer_Info_VID_Port,		/* numericFieldType */
-	Manufacturer_Info_PID_Port,		/* numericFieldType */
-	Security_Msgs_Supported_SOP,		/* booleanFieldType */
-	Num_Fixed_Batteries,			/* numericFieldType */
-	Num_Swappable_Battery_Slots,		/* numericFieldType */
-	ID_Header_Connector_Type_SOP,		/* numericFieldType */
-	SOP_Capable,				/* booleanFieldType */
-	SOP_P_Capable,				/* booleanFieldType */
-	SOP_PP_Capable,				/* booleanFieldType */
-	SOP_P_Debug_Capable,			/* booleanFieldType */
-	SOP_PP_Debug_Capable,			/* booleanFieldType */
-	Type_C_Implements_Try_SRC,		/* booleanFieldType */
-	Type_C_Implements_Try_SNK,		/* booleanFieldType */
-	RP_Value,				/* numericFieldType */
-	Type_C_Supports_VCONN_Powered_Accessory,/* booleanFieldType */
-	Type_C_Is_VCONN_Powered_Accessory,	/* booleanFieldType */
-	Type_C_Is_Debug_Target_SRC,		/* booleanFieldType */
-	Type_C_Is_Debug_Target_SNK,		/* booleanFieldType */
-	Type_C_Can_Act_As_Host,			/* booleanFieldType */
-	Type_C_Is_Alt_Mode_Controller,		/* booleanFieldType */
-	Type_C_Can_Act_As_Device,		/* booleanFieldType */
-	Type_C_Is_Alt_Mode_Adapter,		/* booleanFieldType */
-	Type_C_Power_Source,			/* numericFieldType */
-	Type_C_Port_On_Hub,			/* booleanFieldType */
-	Type_C_Supports_Audio_Accessory,	/* booleanFieldType */
-	Type_C_Sources_VCONN,			/* booleanFieldType */
-	USB4_Lane_0_Adapter,			/* numericFieldType */
-	USB4_Max_Speed,				/* numericFieldType */
-	USB4_DFP_Supported,			/* booleanFieldType */
-	USB4_UFP_Supported,			/* booleanFieldType */
-	USB4_USB3_Tunneling_Supported,		/* booleanFieldType */
-	USB4_DP_Tunneling_Supported,		/* booleanFieldType */
-	USB4_PCIe_Tunneling_Supported,		/* booleanFieldType */
-	USB4_TBT3_Compatibility_Supported,	/* booleanFieldType */
-	USB4_CL1_State_Supported,		/* booleanFieldType */
-	USB4_CL2_State_Supported,		/* booleanFieldType */
-	USB4_Num_Retimers,			/* numericFieldType */
-	USB4_DP_Bit_Rate,			/* numericFieldType */
-	USB4_Num_DP_Lanes,			/* numericFieldType */
-	Device_Supports_USB_Data,		/* booleanFieldType */
-	Device_Speed,				/* numericFieldType */
-	Device_Contains_Captive_Retimer,	/* booleanFieldType */
-	Device_Truncates_DP_For_tDHPResponse,	/* booleanFieldType */
-	Device_Gen1x1_tLinkTurnaround,		/* numericFieldType */
-	Device_Gen2x1_tLinkTurnaround,		/* numericFieldType */
-	Host_Supports_USB_Data,			/* booleanFieldType */
-	Host_Speed,				/* numericFieldType */
-	Is_DFP_On_Hub,				/* booleanFieldType */
-	Hub_Port_Number,			/* numericFieldType */
-	Host_Contains_Captive_Retimer,		/* booleanFieldType */
-	Host_Truncates_DP_For_tDHPResponse,	/* booleanFieldType */
-	Host_Gen1x1_tLinkTurnaround,		/* numericFieldType */
-	Host_Gen2x1_tLinkTurnaround,		/* numericFieldType */
-	Host_Is_Embedded,			/* booleanFieldType */
-	Host_Suspend_Supported,			/* booleanFieldType */
-	PD_Power_As_Source,			/* numericFieldType */
-	USB_Suspend_May_Be_Cleared,		/* booleanFieldType */
-	Sends_Pings,				/* booleanFieldType */
-	FR_Swap_Type_C_Current_Capability_As_Initial_Sink,/* numericFieldType */
-	Master_Port,				/* booleanFieldType */
-	Num_Src_PDOs,				/* numericFieldType */
-	PD_OC_Protection,			/* booleanFieldType */
-	PD_OCP_Method,				/* numericFieldType */
-	PD_Power_As_Sink,			/* numericFieldType */
-	No_USB_Suspend_May_Be_Set,		/* booleanFieldType */
-	GiveBack_May_Be_Set,			/* booleanFieldType */
-	Higher_Capability_Set,			/* booleanFieldType */
-	FR_Swap_Reqd_Type_C_Current_As_Initial_Source,/* numericFieldType */
-	Num_Snk_PDOs,				/* numericFieldType */
-	Accepts_PR_Swap_As_Src,			/* booleanFieldType */
-	Accepts_PR_Swap_As_Snk,			/* booleanFieldType */
-	Requests_PR_Swap_As_Src,		/* booleanFieldType */
-	Requests_PR_Swap_As_Snk,		/* booleanFieldType */
-	FR_Swap_Supported_As_Initial_Sink,	/* booleanFieldType */
-	XID_SOP,				/* numericFieldType */
-	Data_Capable_As_USB_Host_SOP,		/* booleanFieldType */
-	Data_Capable_As_USB_Device_SOP,		/* booleanFieldType */
-	Product_Type_UFP_SOP,			/* numericFieldType */
-	Product_Type_DFP_SOP,			/* numericFieldType */
-	DFP_VDO_Port_Number,			/* numericFieldType */
-	Modal_Operation_Supported_SOP,		/* booleanFieldType */
-	USB_VID_SOP,				/* numericFieldType */
-	PID_SOP,				/* numericFieldType */
-	bcdDevice_SOP,				/* numericFieldType */
-	Num_SVIDs_Min_SOP,			/* numericFieldType */
-	Num_SVIDs_Max_SOP,			/* numericFieldType */
-	SVID_Fixed_SOP,				/* booleanFieldType */
-	AMA_HW_Vers,				/* numericFieldType */
-	AMA_FW_Vers,				/* numericFieldType */
-	AMA_VCONN_Power,			/* booleanFieldType */
-	AMA_VCONN_Reqd,				/* booleanFieldType */
-	AMA_VBUS_Reqd,				/* booleanFieldType */
-	AMA_Superspeed_Support,			/* numericFieldType */
-	BC_1_2_Charging_Port_Type,		/* numericFieldType */
-	XID,					/* numericFieldType */
-	Data_Capable_As_USB_Host,		/* booleanFieldType */
-	Data_Capable_As_USB_Device,		/* booleanFieldType */
-	Product_Type,				/* numericFieldType */
-	Modal_Operation_Supported,		/* booleanFieldType */
-	USB_VID,				/* numericFieldType */
-	PID,					/* numericFieldType */
-	bcdDevice,				/* numericFieldType */
-	Cable_HW_Vers,				/* numericFieldType */
-	Cable_FW_Vers,				/* numericFieldType */
-	Type_C_To_Type_A_B_C,			/* numericFieldType */
-	Type_C_To_Type_C_Capt_Vdm_V2,		/* numericFieldType */
-	Cable_Latency,				/* numericFieldType */
-	Cable_Termination_Type,			/* numericFieldType */
-	Cable_VBUS_Current,			/* numericFieldType */
-	VBUS_Through_Cable,			/* booleanFieldType */
-	Cable_Superspeed_Support,		/* numericFieldType */
-	Cable_USB_Highest_Speed,		/* numericFieldType */
-	Max_VBUS_Voltage_Vdm_V2,		/* numericFieldType */
-	Manufacturer_Info_Supported,		/* booleanFieldType */
-	Manufacturer_Info_VID,			/* numericFieldType */
-	Manufacturer_Info_PID,			/* numericFieldType */
-	Chunking_Implemented,			/* booleanFieldType */
-	Security_Msgs_Supported,		/* booleanFieldType */
-	ID_Header_Connector_Type,		/* numericFieldType */
-	Cable_Num_SVIDs_Min,			/* numericFieldType */
-	Cable_Num_SVIDs_Max,			/* numericFieldType */
-	SVID_Fixed,				/* booleanFieldType */
-	Cable_SOP_PP_Controller,		/* booleanFieldType */
-	SBU_Supported,				/* booleanFieldType */
-	SBU_Type,				/* numericFieldType */
-	Active_Cable_Operating_Temp_Support,	/* booleanFieldType */
-	Active_Cable_Max_Operating_Temp,	/* numericFieldType */
-	Active_Cable_Shutdown_Temp_Support,	/* booleanFieldType */
-	Active_Cable_Shutdown_Temp,		/* numericFieldType */
-	Active_Cable_U3_CLd_Power,		/* numericFieldType */
-	Active_Cable_U3_U0_Trans_Mode,		/* numericFieldType */
-	Active_Cable_Physical_Connection,	/* numericFieldType */
-	Active_Cable_Active_Element,		/* numericFieldType */
-	Active_Cable_USB4_Support,		/* booleanFieldType */
-	Active_Cable_USB2_Supported,		/* booleanFieldType */
-	Active_Cable_USB2_Hub_Hops_Consumed,	/* numericFieldType */
-	Active_Cable_USB32_Supported,		/* booleanFieldType */
-	Active_Cable_USB_Lanes,			/* numericFieldType */
-	Active_Cable_Optically_Isolated,	/* booleanFieldType */
-	Active_Cable_USB_Gen,			/* numericFieldType */
-	VPD_HW_Vers,				/* numericFieldType */
-	VPD_FW_Vers,				/* numericFieldType */
-	VPD_Max_VBUS_Voltage,			/* numericFieldType */
-	VPD_Charge_Through_Support,		/* booleanFieldType */
-	VPD_Charge_Through_Current,		/* numericFieldType */
-	VPD_VBUS_Impedance,			/* numericFieldType */
-	VPD_Ground_Impedance,			/* numericFieldType */
-	Repeater_One_Type,			/* numericFieldType */
-	Repeater_Two_Type,			/* numericFieldType */
-	Product_Total_Source_Power_mW,		/* numericFieldType */
-	Port_Source_Power_Type,			/* numericFieldType */
-	Port_Source_Power_Gang,			/* nonEmptyString */
-	Port_Source_Power_Gang_Max_Power,	/* numericFieldType */
-	Component_Indexes
-};
-struct vif_Component_t {
-	struct vif_field_t		vif_field[Component_Indexes];
-
-	struct vif_srcPdoList_t		SrcPdoList[MAX_NUM_SRC_PDOS];
-	struct vif_snkPdoList_t		SnkPdoList[MAX_NUM_SNK_PDOS];
-	struct vif_sopSVIDList_t	SOPSVIDList[MAX_NUM_SOP_SVIDS];
-	struct vif_cableSVIDList_t	CableSVIDList[MAX_NUM_CABLE_SVIDS];
-
-
-	/*
-	 * The following fields are deprecated.  They should not be written
-	 * to file in this version or any later version of the schema.
-	 *
-	 * Deprecated in VIF Version 3.10
-	 *    vif_numericFieldType_t type_c_to_plug_receptacle;
-	 *    vif_numericFieldType_t retimer_type;
-	 * Deprecated in VIF Version 3.12
-	 *    vif_numericFieldType_t active_cable_usb2_hub_hops_supported;
-	 *    vif_booleanFieldType_t active_cable_optically_isololated;
-	 */
-};
-
-
-enum vif_Product_indexes {
-	Product_VID,				/* numericFieldType */
-	USB4_Dock,				/* booleanFieldType */
-	USB4_Num_Internal_Host_Controllers,	/* numericFieldType */
-	USB4_Num_PCIe_DN_Bridges,		/* numericFieldType */
-	USB4_Audio_Supported,			/* booleanFieldType */
-	USB4_HID_Supported,			/* booleanFieldType */
-	USB4_Printer_Supported,			/* booleanFieldType */
-	USB4_Mass_Storage_Supported,		/* booleanFieldType */
-	USB4_Video_Supported,			/* booleanFieldType */
-	USB4_Comms_Networking_Supported,	/* booleanFieldType */
-	USB4_Media_Transfer_Protocol_Supported,	/* booleanFieldType */
-	USB4_Smart_Card_Supported,		/* booleanFieldType */
-	USB4_Still_Image_Capture_Supported,	/* booleanFieldType */
-	USB4_Monitor_Device_Supported,		/* booleanFieldType */
-	Product_Indexes
-};
-struct vif_Product_t {
-	struct vif_field_t		vif_field[Product_Indexes];
-
-	struct vif_Usb4RouterListType_t USB4RouterList[MAX_NUM_USB4_ROUTERS];
-};
-
-
-enum vif_indexes {
-	VIF_Specification,		/* version */
-	Vendor_Name,			/* nonEmptyString */
-	Model_Part_Number,		/* nonEmptyString */
-	Product_Revision,		/* nonEmptyString */
-	TID,				/* nonEmptyString */
-	VIF_Product_Type,		/* numericFieldType */
-	Certification_Type,		/* numericFieldType */
-	VIF_Indexes
-};
-enum vif_app_indexes {
-	Vendor,				/* nonEmptyString */
-	Name,				/* nonEmptyString */
-	Version,			/* version */
-	VIF_App_Indexes
-};
-struct vif_t {
-	struct vif_field_t		vif_field[VIF_Indexes];
-	struct vif_field_t		vif_app_field[VIF_App_Indexes];
-
-	struct vif_Product_t		Product;
-	struct vif_Component_t		Component[MAX_NUM_COMPONENTS];
-};
-
-#endif /* __GENVIF_H__ */
diff --git a/util/gpios_to_zephyr_dts.c b/util/gpios_to_zephyr_dts.c
deleted file mode 100644
index 166c16dde7..0000000000
--- a/util/gpios_to_zephyr_dts.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This code is intended for developer use to convert a CrOS EC OS
- * "gpio.inc" file into the expected device-tree format for Zephyr.
- * The only use of it is to do a proof-of-concept build of a CrOS EC
- * device using Zephyr OS, as Zephyr-only devices won't have a
- * equivalent CrOS EC build.
- *
- * It does not handle all cases (i.e., low voltage selection), and
- * some manual modifications to the output may be required.
- *
- **********************************************************************
- * DO NOT CREATE TESTS, SYSTEMS, OR INFRASTRUCTURE WHICH RELIES ON    *
- * THIS CODE.  It's seriously ugly code that's probably prone to      *
- * breakage.  It leaks memory.  In other words, consider it           *
- * "contrib-quality" code that should be deleted one day (once we are *
- * no longer doing proof-of-concept Zephyr builds).                   *
- **********************************************************************
- *
- * To compile:
- *   gcc -Iboard/${BOARD} -std=gnu11 util/gpios_to_zephyr_dts.c \
- *       -o /tmp/print_gpios
- *
- * Then run /tmp/print_gpios and paste the result into your gpio DTS
- * overlay.
- */
-
-#define _POSIX_C_SOURCE 200809L
-
-#include <ctype.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-/*
- * Implement the macros used in the gpio.inc files, but print DTS
- * format equivalents.
- */
-#define GPIO_INT_RISING GPIO_INPUT
-#define GPIO_INT_FALLING GPIO_INPUT
-#define GPIO_INT_BOTH GPIO_INPUT
-#define GPIO_HIB_WAKE_HIGH 0
-#define GPIO_HIB_WAKE_LOW 0
-#define GPIO_LOCKED 0
-#define GPIO_SEL_1P8V 0
-#define GPIO_INT(name, pin, opts, int) GPIO(name, pin, opts)
-#define GPIO(name, pin, opts) _gpio(#name, pin, opts)
-#define UNUSED(pin)
-#define UNIMPLEMENTED(name)
-#define _gpio(name, pin, opts)                                   \
-	printf("%s {\n\tgpios = <&%s %s>;\n\tlabel = %s;\n};\n", \
-	       strlower(name), strlower(pin),                    \
-	       maybe_parens(strip_zero_ors(#opts)), #name);
-#define PIN(A, B) "gpio" #A " " #B
-#define ALTERNATE(...)
-#define IOEX(...)
-#define IOEX_INT(...)
-
-/* Strip out " | 0" and "0 | " from a string */
-static char *strip_zero_ors(const char *s)
-{
-	char *out = malloc(strlen(s) + 2);
-	const char *rd_ptr = s;
-	char *wr_ptr = out;
-
-	while (*rd_ptr) {
-		if (!strncmp(rd_ptr, " | 0", 4) ||
-		    !strncmp(rd_ptr, "0 | ", 4)) {
-			rd_ptr += 4;
-		} else {
-			*wr_ptr = *rd_ptr;
-			rd_ptr++;
-			wr_ptr++;
-		}
-	}
-
-	*wr_ptr = '\0';
-	return out;
-}
-
-/*
- * Add parenthesis around the outside of a string if it contains the
- * '|' character.
- */
-static char *maybe_parens(const char *s)
-{
-	size_t out_sz = strlen(s) + 3;
-	char *out = malloc(out_sz);
-
-	if (strchr(s, '|'))
-		snprintf(out, out_sz, "(%s)", s);
-	else
-		snprintf(out, out_sz, "%s", s);
-
-	return out;
-}
-
-/* Convert a string to lowercase */
-static char *strlower(const char *s)
-{
-	char *out = strdup(s);
-
-	for (int i = 0; out[i]; i++)
-		out[i] = tolower(out[i]);
-
-	return out;
-}
-
-int main(int argc, char *argv[])
-{
-#include "gpio.inc"
-	return 0;
-}
diff --git a/util/host_command_check.sh b/util/host_command_check.sh
deleted file mode 100755
index f699803b2e..0000000000
--- a/util/host_command_check.sh
+++ /dev/null
@@ -1,138 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-excludes=( --exclude-dir=build --exclude=TAGS )
-
-#######################################
-# Test if the following conditions hold for the ec host command
-# The alpha numeric value of the define starts with 0x
-# The alpha numeric value of the define is 4-hex digits
-# The hex digits "A B C D E F" are capitalized
-# Arguments:
-#   string - ec host command to check
-# Returns:
-#   0 if command is ok, else 1
-########################################
-check_cmd() {
-  IFS=" "
-  # Remove any tabs that may exist
-  tts=$(echo "$1" | sed 's/\t/ /g')
-  arr=( $tts )
-
-  # Check for 0x
-  if [[ "${arr[2]}" != 0x* ]]; then
-    return 1
-  fi
-
-  # Check that length is 6. 0x + 4 hex digits
-  if [[ ${#arr[2]} != 6 ]]; then
-    return 1
-  fi
-
-  # Check that hex digits are valid and uppercase
-  hd=${arr[2]:2}
-  if ! [[ $hd =~ ^[0-9A-F]{4}$ ]]; then
-    return 1
-  fi
-
-  # command is ok
-  return 0
-}
-
-#######################################
-# Test if the string arg is in one of the following formats:
-#  file.X:#define EC_CMD_X XxXXXX
-#  file.X:#define EC_PRV_CMD_X XxXXXX
-# Arguments:
-#   string - potential ec host command
-# Returns:
-#   0 if command is formated properly, else 1
-########################################
-should_check() {
-  IFS=" "
-  arr=( $1 )
-
-  # Check for file.X:#define
-  IFS=":"
-  temp=( ${arr[0]} )
-  # Check for file.X
-  if [ ! -f  "${temp[0]}" ]; then
-    return 1
-  fi
-
-  # Check for #define
-  if [[ "${temp[1]}" != "#define" ]]; then
-    return 1
-  fi
-
-  # Check for EC_CMD_XXX or EC_PRV_CMD_XXX
-  if [[ "${arr[1]}" != EC_CMD_* ]] && [[ "${arr[1]}" != EC_PRV_CMD_* ]]; then
-    return 1
-  fi
-
-  # Check for EC_XXX_XXX(n)
-  if [[ "${arr[1]}" =~ ')'$ ]]; then
-    return 1
-  fi
-
-  return 0
-}
-
-main() {
-
-  # Do not run the check unless an EC_[xxx]CMD change is present.
-  if [[ -z "$(git diff --no-ext-diff "${PRESUBMIT_COMMIT}~" \
-          "${PRESUBMIT_COMMIT}" -U0 |
-      egrep 'EC_[^ ]*CMD')" ]]; then
-    exit 0
-  fi
-
-  ec_errors=()
-  ei=0
-  # Search all file occurrences of "EC_CMD" and store in array
-  IFS=$'\n'
-  ec_cmds=($(grep "${excludes[@]}" -r "EC_CMD"))
-
-  # Loop through and find valid occurrences of "EC_CMD" to check
-  length=${#ec_cmds[@]}
-  for ((i = 0; i != length; i++)); do
-    if should_check "${ec_cmds[i]}"; then
-      if ! check_cmd "${ec_cmds[i]}"; then
-        ec_errors[$ei]="${ec_cmds[i]}"
-        ((ei++))
-      fi
-    fi
-  done
-
-  # Search all file occurrances of "EC_PRV_CMD" and store in array
-  IFS=$'\n'
-  ec_prv_cmds=($(grep "${excludes[@]}" -r "EC_PRV_CMD"))
-
-  # Loop through and find valid occurrences of "EC_PRV_CMD" to check
-  length=${#ec_prv_cmds[@]}
-  for ((i = 0; i != length; i++)); do
-    if should_check "${ec_prv_cmds[i]}"; then
-      if ! check_cmd "${ec_prv_cmds[i]}"; then
-        ec_errors[$ei]="${ec_prv_cmds[i]}"
-        ((ei++))
-      fi
-    fi
-  done
-
-  # Check if any malformed ec host commands were found
-  if [ ! $ei -eq 0 ]; then
-    echo "The following host commands are malformed:"
-    # print all malformed host commands
-    for ((i = 0; i != ei; i++)); do
-      echo "FILE: ${ec_errors[i]}"
-    done
-    exit 1
-  fi
-
-  exit 0
-}
-
-main "$@"
diff --git a/util/ide-config.sh b/util/ide-config.sh
deleted file mode 100755
index 25edca2407..0000000000
--- a/util/ide-config.sh
+++ /dev/null
@@ -1,475 +0,0 @@
-#!/bin/bash
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Usage: ./util/ide-config.sh vscode all all:RO | tee .vscode/c_cpp_properties.json
-# This tool needs to be run from the base ec directory.
-#
-# Future works should be put towards adding new IDE generators and adding
-# mechanism for passing IDE specific parameters to the IDE generator.
-
-DEFAULT_IMAGE=RW
-INDENT_WIDTH=${INDENT_WIDTH:-1}
-INDENT_CHAR=${INDENT_CHAR:-$'\t'}
-INCLUDES_DROP_ROOT=${INCLUDES_DROP_ROOT:-false}
-PARALLEL_CACHE_FILL=${PARALLEL_CACHE_FILL:-true}
-FORCE_INCLUDE_CONFIG_H=${FORCE_INCLUDE_CONFIG_H:-false}
-# JOB_BATCH_SIZE is the number of jobs allowed to spawn at any given point.
-# This is an inefficient manner of resource management, but at least it
-# throttles process creation. Due to the low utilization or each job,
-# multiply the number of real processors by 2.
-JOB_BATCH_SIZE=${JOB_BATCH_SIZE:-$(($(nproc) * 2))}
-
-MAKE_CACHE_DIR=""
-
-init() {
-	MAKE_CACHE_DIR=$(mktemp -t -d ide-config.XXXX)
-	mkdir -p "${MAKE_CACHE_DIR}/defines"
-	mkdir -p "${MAKE_CACHE_DIR}/includes"
-	trap deinit EXIT
-}
-
-deinit() {
-	rm -rf "${MAKE_CACHE_DIR}"
-}
-
-usage() {
-	cat <<-HEREDOC
-	Usage: ide-config.sh <vscode|eclipse> [BOARD:IMAGE] [BOARD:IMAGE...]
-	Generate a C language configuration for a given IDE and EC board.
-
-	Examples:
-	ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
-	ide-config.sh vscode nocturne # implicitly :RW
-	ide-config.sh vscode nocturne_fp:RO
-	ide-config.sh vscode nocturne:RO hatch:RW
-	ide-config.sh vscode all      # implicitly :RW
-	ide-config.sh eclipse nocturne_fp > ~/Downloads/nocturne_fp-RW.xml
-	HEREDOC
-}
-
-# Usage: iprintf <indent-level> <printf-fmt> [printf-args...]
-iprintf() {
-	local level=$1
-	shift
-
-	local n=$((INDENT_WIDTH*level))
-	if [[ $n -ne 0 ]]; then
-		eval printf '"${INDENT_CHAR}%.0s"' "{1..$n}"
-	fi
-	# shellcheck disable=SC2059
-	printf "$@"
-	return $?
-}
-
-# Usage: parse-cfg-board <cfg-string>
-#
-# Example: parse-cfg-board nocturne:RW
-parse-cfg-board() {
-	local cfg=$1
-	# Remove possible :RW or :RO
-	local board=${cfg%%:*}
-	if [[ -z ${board} ]]; then
-		return 1
-	fi
-	echo "${board}"
-}
-
-# Usage: parse-cfg-image <cfg-string>
-#
-# Example: parse-cfg-image nocturne:RW
-# Example: parse-cfg-image nocturne
-parse-cfg-image() {
-	local cfg=$1
-
-	local board
-	if ! board=$(parse-cfg-board "${cfg}"); then
-		return 1
-	fi
-	# Remove known board part
-	cfg=${cfg#${board}}
-	cfg=${cfg#":"}
-	# Use default image if none set
-	cfg=${cfg:-${DEFAULT_IMAGE}}
-
-	case ${cfg} in
-		RW|RO)
-			echo "${cfg}"
-			return 0
-			;;
-		*)
-			return 1
-			;;
-	esac
-}
-
-# Usage: make-defines <board> <RO|RW>
-make-defines() {
-	local board=$1
-	local image=$2
-
-	local cache="${MAKE_CACHE_DIR}/defines/${board}-${image}"
-
-	if [[ ! -f "${cache}" ]]; then
-		make print-defines BOARD="${board}" BLD="${image}" >"${cache}"
-	fi
-
-	cat "${cache}"
-}
-
-# Usage: make-includes <board> <RO|RW>
-#
-# Rerun a newline separated list of include directories relative to the ec's
-# root directory.
-make-includes() {
-	local board=$1
-	local image=$2
-
-	local cache="${MAKE_CACHE_DIR}/includes/${board}-${image}"
-
-	if [[ ! -f "${cache}" ]]; then
-		make print-includes BOARD="${board}" BLD="${image}" \
-		| xargs realpath --relative-to=. \
-		| {
-			if [[ "${INCLUDES_DROP_ROOT}" == true ]]; then
-				grep -v "^\.$"
-			else
-				cat
-			fi
-		  } >"${cache}"
-	fi
-
-	cat "${cache}"
-}
-
-# Usage: make-boards
-make-boards() {
-	local cache="${MAKE_CACHE_DIR}/boards"
-
-	if [[ ! -f "${cache}" ]]; then
-		make print-boards >"${cache}"
-	fi
-
-	cat "${cache}"
-}
-
-# Usage: <newline-list> |  join <left> <right> <separator>
-#
-# JSON: includes nocturne_fp RW | join '"' '"' ',\n'
-# C:    includes nocturne_fp RW | join '"' '",' '\n'
-join() {
-	local left=$1
-	local right=$2
-	local sep=$3
-
-	local first=true
-	while read -r line; do
-		# JSON is ridiculous for not allowing a trailing ,
-		if [[ "${first}" == true ]]; then
-			first=false
-		else
-			printf "%b" "${sep}"
-		fi
-		printf "%b%s%b" "${left}" "${line}" "${right}"
-	done
-	echo
-}
-
-# Usage: <content> | encap <header> <footer> [indent]
-#
-# Encapsulate the content from stdin with a header, footer, and indentation.
-encap() {
-	local header=$1
-	local footer=$2
-	local indent=${3:-0}
-
-	iprintf "${indent}" "%b" "${header}"
-	while IFS="" read -r line; do
-		iprintf $((1+indent)) "%s\n" "${line}"
-	done
-	iprintf "${indent}" "%b" "${footer}"
-}
-
-##########################################################################
-
-# Usage: vscode [cfg...]
-#
-# Generate the content for one c_cpp_properties.json that contains
-# multiple selectable configurations for each board-image pair.
-# In VSCode you can select the config in the bottom right, next to the
-# "Select Language Mode". You will only see this option when a C/C++ file
-# is open. Additionally, you can select a configuration by pressing
-# Ctrl-Shift-P and selecting the "C/C++ Select a Configuration..." option.
-vscode() {
-	local first=true
-	{
-		for cfg; do
-			local board image
-			if ! board=$(parse-cfg-board "${cfg}"); then
-				echo "Failed to parse board from cfg '${cfg}'"
-				return 1
-			fi
-			if ! image=$(parse-cfg-image "${cfg}"); then
-				echo "Failed to parse image from cfg '${cfg}'"
-				return 1
-			fi
-			{
-				printf '"name": "%s",\n' "${board}:${image}"
-				make-includes "${board}" "${image}" \
-					| join '"' '"' ',\n' \
-					| encap '"includePath": [\n' '],\n'
-				make-defines "${board}" "${image}" \
-					| join '"' '"' ',\n' \
-					| encap '"defines": [\n' '],\n'
-
-				if [[ "${FORCE_INCLUDE_CONFIG_H}" == true ]]; then
-					echo '"include/config.h"' \
-						| encap '"forcedInclude": [\n' '],\n'
-				fi
-
-				echo '"compilerPath": "/usr/bin/arm-none-eabi-gcc",'
-				# echo '"compilerArgs": [],'
-				# The macro __STDC_VERSION__ is 201710L, which corresponds to c18.
-				# VSCode doesn't have a C18 option, so go with C17. Since we seem
-				# to use a lot of GNUC features, let's go with gnu17 instead of c17.
-				echo '"cStandard": "gnu17",'
-				# echo '"cppStandard": "c++17",'
-				echo '"intelliSenseMode": "gcc-x64"'
-			} | {
-				# A single named configuration
-				if [[ "${first}" == true ]]; then
-					encap '{\n' '}'
-				else
-					encap ',\n{\n' '}'
-				fi
-			}
-			first=false
-		done
-		echo
-	} \
-	| {
-		encap '"configurations": [\n' '],\n'
-		echo '"version": 4'
-	} \
-	| encap '{\n' '}\n'
-}
-
-# Usage: eclipse-cdt-import [cfg...]
-#
-# * Add odd EC "File Types"
-#   - *.tasklist *.mocklist *.testlist *.irqlist "C Header File"
-#   - *.inc "C Header File"
-#   - gpio.wrap "C Header File"
-# * Enable the indexer to follow current build configuration
-#   - Enable "Index all header variants"
-#   - Enable "Use active build configuration" (ensure this options sticks)
-#   - Probably bump up the Cache Limit->"Absolute Limit"
-# * Remove default system includes
-#   - Depending on your eclipse toolchain configuration, it may be possible
-#     to remove the standard C headers.
-#     This helps satisfy the EC's -nostdinc usage.
-eclipse-cdt-import() {
-	if [[ $# -gt 1 ]]; then
-		echo "Error - eclipse generator can only process one board cfg" >&2
-		return 1
-	fi
-
-	local cfg=$1
-	local board image
-
-	board=$(parse-cfg-board "${cfg}")
-	image=$(parse-cfg-image "${cfg}")
-
-	local includes
-	# Grab workspace/project local paths
-	includes+="$(make-includes "${board}" "${image}" | grep -v "^\.\." \
-			| join '<includepath workspace_path="true">' '</includepath>' '\n\t\t\t')"
-	# Add separator manually
-	includes+="$(printf "\n\t\t\t")"
-	# Grab external paths (wil start with .. because forced relative)
-	# shellcheck disable=SC2016
-	includes+="$(make-includes "${board}" "${image}" | grep "^\.\." \
-			| join '<includepath>${ProjDirPath}/' '</includepath>' '\n\t\t\t')"
-
-	local macros
-	macros="$(
-		while read -r name value; do
-			{
-				join '<name>' '</name>' '' <<<"${name}"
-				join '<value>' '</value>' '' <<<"${value}"
-			} | encap '<macro>\n' '</macro>\n' 3
-		done < <(make-defines "${board}" "${image}" | tr '=' '\t')
-	)"
-
-	cat <<EOF
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Generated for ${board}:${image} -->
-<cdtprojectproperties>
-	<section name="org.eclipse.cdt.internal.ui.wizards.settingswizards.IncludePaths">
-		<!-- Start Normal CDT -->
-		<language name="holder for library settings"></language>
-
-		<language name="Assembly">
-			${includes}
-		</language>
-
-		<language name="GNU C++">
-			${includes}
-		</language>
-
-		<language name="GNU C">
-			${includes}
-		</language>
-		<!-- End Normal CDT -->
-
-		<!-- Start CDT Cross/Embedded -->
-		<language name="C Source File">
-			${includes}
-		</language>
-
-		<language name="Object File">
-		</language>
-
-		<language name="Assembly Source File">
-			${includes}
-		</language>
-		<!-- End CDT Cross/Embedded -->
-	</section>
-
-	<section name="org.eclipse.cdt.internal.ui.wizards.settingswizards.Macros">
-		<!-- Start Normal CDT -->
-		<language name="holder for library settings"></language>
-
-		<language name="Assembly">
-${macros}
-		</language>
-
-		<language name="GNU C++">
-${macros}
-		</language>
-
-		<language name="GNU C">
-${macros}
-		</language>
-		<!-- End Normal CDT -->
-
-		<!-- Start CDT Cross/Embedded -->
-		<language name="C Source File">
-${macros}
-		</language>
-
-		<language name="Object File">
-		</language>
-
-		<language name="Assembly Source File">
-${macros}
-		</language>
-		<!-- End CDT Cross/Embedded -->
-	</section>
-</cdtprojectproperties>
-EOF
-}
-
-# Usage: main <ide> [cfgs...]
-main() {
-	# Disaply help if no args
-	if [[ $# -lt 1 ]]; then
-		usage
-		exit 1
-	fi
-	# Search for help flag
-	for flag; do
-		case ${flag} in
-			help|--help|-h)
-				usage
-				exit 0
-				;;
-		esac
-	done
-
-	local ide=$1
-	shift
-
-	# Expand possible "all" cfgs
-	local board image
-	local -a cfgs=( )
-	for cfg; do
-		# We parse both board and image to pre-sanatize the input
-		if ! board=$(parse-cfg-board "${cfg}"); then
-			echo "Failed to parse board from cfg '${cfg}'" >&2
-			exit 1
-		fi
-		if ! image=$(parse-cfg-image "${cfg}"); then
-			echo "Failed to parse image from cfg '${cfg}'" >&2
-			exit 1
-		fi
-		# Note "all:*" could be specified multiple times for RO and RW
-		# Note "all:*" could be specified with other specific board:images
-		if [[ "${board}" == all ]]; then
-			local -a allboards=( )
-			mapfile -t allboards < <(make-boards)
-			cfgs+=( "${allboards[@]/%/:${image}}" )
-		else
-			cfgs+=( "${cfg}" )
-		fi
-	done
-
-	# Technically, we have not sanitized the cfgs generated from
-	# "all" expression.
-
-	# Make configs unique (and sorted)
-	mapfile -t cfgs < <(echo "${cfgs[@]}" | tr ' ' '\n' | sort -u)
-	echo "# Generating a config for the following board:images: " >&2
-	echo "${cfgs[@]}" | tr ' ' '\n' | sort -u | column >&2
-
-	# Prefill the make cache in parallel
-	# This is important because each make request take about 700ms.
-	# When running on all boards, this could result in (127*2)*700ms = 3mins.
-	if [[ "${PARALLEL_CACHE_FILL}" == true ]]; then
-		echo "# Fetching make defines and includes. Please wait." >&2
-
-		# We run into process limits if we launch all processes at the
-		# same time, so we must split them in half.
-		# This need some jobserver management.
-
-		# Run make for RWs and ROs
-		local -i jobs=0
-		for cfg in "${cfgs[@]}"; do
-			if ! board="$(parse-cfg-board "${cfg}")"; then
-				echo "Failed to parse board from cfg '${cfg}'" >&2
-				exit 1
-			fi
-			if ! image="$(parse-cfg-image "${cfg}")"; then
-				echo "Failed to parse image from cfg '${cfg}'" >&2
-				exit 1
-			fi
-			make-defines "${board}" "${image}" >/dev/null &
-			((++jobs % JOB_BATCH_SIZE == 0)) && wait
-			make-includes "${board}" "${image}" >/dev/null &
-			((++jobs % JOB_BATCH_SIZE == 0)) && wait
-		done
-		wait
-	fi
-
-	# Run the IDE's generator
-	case "${ide}" in
-		vscode)
-			vscode "${cfgs[@]}" || exit $?
-			;;
-		eclipse)
-			eclipse-cdt-import "${cfgs[@]}" || exit $?
-			;;
-		*)
-			echo "Error - IDE '${ide}' is an unsupported." >&2
-			exit 1
-			;;
-	esac
-}
-
-init
-
-# Only start if not being sourced
-if [[ "$0" == "${BASH_SOURCE[0]}" ]]; then
-	main "$@"
-fi
diff --git a/util/inject-keys.py b/util/inject-keys.py
deleted file mode 100755
index bd10b693ad..0000000000
--- a/util/inject-keys.py
+++ /dev/null
@@ -1,130 +0,0 @@
-#!/usr/bin/env python
-# -*- coding: utf-8 -*-
-#
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import string
-import subprocess
-import sys
-
-
-KEYMATRIX = {'`': (3, 1), '1': (6, 1), '2': (6, 4), '3': (6, 2), '4': (6, 3),
-             '5': (3, 3), '6': (3, 6), '7': (6, 6), '8': (6, 5), '9': (6, 9),
-             '0': (6, 8), '-': (3, 8), '=': (0, 8), 'q': (7, 1), 'w': (7, 4),
-             'e': (7, 2), 'r': (7, 3), 't': (2, 3), 'y': (2, 6), 'u': (7, 6),
-             'i': (7, 5), 'o': (7, 9), 'p': (7, 8), '[': (2, 8), ']': (2, 5),
-             '\\': (3, 11), 'a': (4, 1), 's': (4, 4), 'd': (4, 2), 'f': (4, 3),
-             'g': (1, 3), 'h': (1, 6), 'j': (4, 6), 'k': (4, 5), 'l': (4, 9),
-             ';': (4, 8), '\'': (1, 8), 'z': (5, 1), 'x': (5, 4), 'c': (5, 2),
-             'v': (5, 3), 'b': (0, 3), 'n': (0, 6), 'm': (5, 6), ',': (5, 5),
-             '.': (5, 9), '/': (5, 8), ' ': (5, 11), '<right>': (6, 12),
-             '<alt_r>': (0, 10), '<down>': (6, 11), '<tab>': (2, 1),
-             '<f10>': (0, 4), '<shift_r>': (7, 7), '<ctrl_r>': (4, 0),
-             '<esc>': (1, 1), '<backspace>': (1, 11), '<f2>': (3, 2),
-             '<alt_l>': (6, 10), '<ctrl_l>': (2, 0), '<f1>': (0, 2),
-             '<search>': (0, 1), '<f3>': (2, 2), '<f4>': (1, 2), '<f5>': (3, 4),
-             '<f6>': (2, 4), '<f7>': (1, 4), '<f8>': (2, 9), '<f9>': (1, 9),
-             '<up>': (7, 11), '<shift_l>': (5, 7), '<enter>': (4, 11),
-             '<left>': (7, 12)}
-
-
-UNSHIFT_TABLE = { '~': '`', '!': '1', '@': '2', '#': '3', '$': '4',
-                  '%': '5', '^': '6', '&': '7', '*': '8', '(': '9',
-                  ')': '0', '_': '-', '+': '=', '{': '[', '}': ']',
-                  '|': '\\',
-                  ':': ';', '"': "'", '<': ',', '>': '.', '?': '/'}
-
-for c in string.ascii_lowercase:
-    UNSHIFT_TABLE[c.upper()] = c
-
-
-def inject_event(key, press):
-    if len(key) >= 2 and key[0] != '<':
-        key = '<' + key + '>'
-    if key not in KEYMATRIX:
-        print("%s: invalid key: %s" % (this_script, key))
-        sys.exit(1)
-    (row, col) = KEYMATRIX[key]
-    subprocess.call(["ectool", "kbpress", str(row), str(col),
-                     "1" if press else "0"])
-
-
-def inject_key(key):
-    inject_event(key, True)
-    inject_event(key, False)
-
-
-def inject_string(string):
-    for c in string:
-        if c in KEYMATRIX:
-            inject_key(c)
-        elif c in UNSHIFT_TABLE:
-            inject_event("<shift_l>", True)
-            inject_key(UNSHIFT_TABLE[c])
-            inject_event("<shift_l>", False)
-        else:
-            print("unimplemented character:", c)
-            sys.exit(1)
-
-
-def usage():
-    print("Usage: %s [-s <string>] [-k <key>]" % this_script,
-          "[-p <pressed-key>] [-r <released-key>] ...")
-    print("Examples:")
-    print("%s -s MyPassw0rd -k enter" % this_script)
-    print("%s -p ctrl_l -p alt_l -k f3 -r alt_l -r ctrl_l" % this_script)
-
-
-def help():
-    usage()
-    print("Valid keys are:")
-    i = 0
-    for key in KEYMATRIX:
-        print("%12s" % key, end='')
-        i += 1
-        if i % 4 == 0:
-            print()
-    print()
-    print("angle brackets may be omitted")
-
-
-def usage_check(asserted_condition, message):
-    if asserted_condition:
-        return
-    print("%s:" % this_script, message)
-    usage()
-    sys.exit(1)
-
-
-# -- main
-
-this_script = sys.argv[0]
-arg_len = len(sys.argv)
-
-if arg_len > 1 and sys.argv[1] == "--help":
-    help()
-    sys.exit(0)
-
-usage_check(arg_len > 1, "not enough arguments")
-usage_check(arg_len % 2 == 1, "mismatched arguments")
-
-for i in range(1, arg_len, 2):
-    usage_check(sys.argv[i] in ("-s", "-k", "-p", "-r"),
-                "unknown flag: %s" % sys.argv[i])
-
-for i in range(1, arg_len, 2):
-    flag = sys.argv[i]
-    arg = sys.argv[i+1]
-    if flag == "-s":
-        inject_string(arg)
-    elif flag == "-k":
-        inject_key(arg)
-    elif flag == "-p":
-        inject_event(arg, True)
-    elif flag == "-r":
-        inject_event(arg, False)
diff --git a/util/iteflash.c b/util/iteflash.c
deleted file mode 100644
index a4a166d3d8..0000000000
--- a/util/iteflash.c
+++ /dev/null
@@ -1,2445 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ITE83xx SoC in-system programming tool
- */
-
-/* remove when ftdi_usb_purge_buffers has been replaced to follow libftdi */
-#define _FTDI_DISABLE_DEPRECATED
-
-#include <errno.h>
-#include <fcntl.h>
-#include <ftdi.h>
-#include <getopt.h>
-#include <linux/i2c-dev.h>
-#include <linux/i2c.h>
-#include <signal.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <time.h>
-#include <unistd.h>
-#include <sys/wait.h>
-
-#include "compile_time_macros.h"
-#include "usb_if.h"
-
-/* Default FTDI device : Servo v2. */
-#define SERVO_USB_VID 0x18d1
-#define SERVO_USB_PID 0x5002
-#define SERVO_INTERFACE INTERFACE_B
-
-/* Default CCD device: Cr50. */
-#define CR50_USB_VID 0x18d1
-#define CR50_USB_PID 0x5014
-
-/* Cr50 exposed properties of the USB I2C endpoint. */
-#define CR50_I2C_SUBCLASS  82
-#define CR50_I2C_PROTOCOL  1
-
-#define CROS_CMD_ADDR		0x78	/* USB_I2C_CMD_ADDR 0xF0 >> 1 */
-#define CROS_CMD_ITE_SYNC	0
-
-/* DBGR I2C addresses */
-#define I2C_CMD_ADDR   0x5A
-#define I2C_DATA_ADDR  0x35
-#define I2C_BLOCK_ADDR 0x79
-
-#define FTDI_I2C_FREQ 400000
-
-/* I2C pins on the FTDI interface */
-#define SCL_BIT        BIT(0)
-#define SDA_BIT        BIT(1)
-
-/* Chip ID register value */
-#define CHIP_ID 0x8380
-
-/* Embedded flash page size */
-#define PAGE_SIZE		(1<<8)
-
-/* Embedded flash block write size for different programming modes. */
-#define FTDI_BLOCK_WRITE_SIZE	(1<<16)
-
-/* JEDEC SPI Flash commands */
-#define SPI_CMD_PAGE_PROGRAM	0x02
-#define SPI_CMD_WRITE_DISABLE	0x04
-#define SPI_CMD_READ_STATUS	0x05
-#define SPI_CMD_WRITE_ENABLE	0x06
-#define SPI_CMD_FAST_READ	0x0B
-#define SPI_CMD_CHIP_ERASE	0x60
-#define SPI_CMD_SECTOR_ERASE_1K	0xD7
-#define SPI_CMD_SECTOR_ERASE_4K	0x20
-#define SPI_CMD_WORD_PROGRAM	0xAD
-#define SPI_CMD_EWSR		0x50 /* Enable Write Status Register */
-#define SPI_CMD_WRSR		0x01 /* Write Status Register */
-#define SPI_CMD_RDID		0x9F /* Read Flash ID */
-
-/* Size for FTDI outgoing buffer */
-#define FTDI_CMD_BUF_SIZE (1<<12)
-
-/* Reset Status */
-#define RSTS_VCCDO_PW_ON	0x40
-#define RSTS_VFSPIPG		0x20
-#define RSTS_HGRST		0x08
-#define RSTS_GRST		0x04
-
-/* I2C MUX Configuration: TCA9543 or PCA9546 */
-#define I2C_MUX_CMD_ADDR		0x70
-#define I2C_MUX_CMD_NONE		0x00
-#define I2C_MUX_CMD_INAS		0x01
-#define I2C_MUX_CMD_EC			0x02
-
-/* Eflash Type*/
-#define EFLASH_TYPE_8315	0x01
-#define EFLASH_TYPE_KGD		0x02
-#define EFLASH_TYPE_NONE	0xFF
-
-uint8_t eflash_type;
-uint8_t spi_cmd_sector_erase;
-
-/* Embedded flash number of pages in a sector erase */
-uint8_t sector_erase_pages;
-
-
-static volatile sig_atomic_t exit_requested;
-
-struct i2c_interface;
-
-/* Config mostly comes from the command line.  Defaults are set in main(). */
-struct iteflash_config {
-	char *input_filename;
-	char *output_filename;
-	int send_waveform;  /* boolean */
-	int erase;  /* boolean */
-	int i2c_mux; /* boolean */
-	int debug;  /* boolean */
-	int disable_watchdog;  /* boolean */
-	int disable_protect_path;  /* boolean */
-	int block_write_size;
-	int usb_interface;
-	int usb_vid;
-	int usb_pid;
-	int verify;  /* boolean */
-	char *usb_serial;
-	char *i2c_dev_path;
-	const struct i2c_interface *i2c_if;
-	size_t range_base;
-	size_t range_size;
-};
-
-struct common_hnd {
-	struct iteflash_config conf;
-	int flash_size;
-	int flash_cmd_v2;      /* boolean */
-	int dbgr_addr_3bytes;  /* boolean */
-	union {
-		int i2c_dev_fd;
-		struct usb_endpoint uep;
-		struct ftdi_context *ftdi_hnd;
-	};
-};
-
-struct cmds {
-	uint8_t addr;
-	uint8_t cmd;
-};
-
-/* For all callback return values, zero indicates success, non-zero failure. */
-struct i2c_interface {
-	/* Optional, may be NULL. */
-	int (*interface_init)(struct common_hnd *chnd);
-	/* Always called if non-NULL, even if special waveform is skipped! */
-	/* Optional, may be NULL. */
-	int (*interface_post_waveform)(struct common_hnd *chnd);
-	/* Called exactly once if and only if interface_init() succeeded. */
-	/* Optional, may be NULL. */
-	int (*interface_shutdown)(struct common_hnd *chnd);
-	/* Optional, may be NULL (unsupported for this I2C interface type). */
-	int (*send_special_waveform)(struct common_hnd *chnd);
-	/* Required, must not be NULL. */
-	int (*byte_transfer)(struct common_hnd *chnd, uint8_t addr,
-		uint8_t *data, int write, int numbytes);
-	/* Required, must be positive. */
-	int default_block_write_size;
-};
-
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc);
-
-static void null_and_free(void **ptr)
-{
-	void *holder;
-
-	if (*ptr) {
-		holder = *ptr;
-		*ptr = NULL;
-		free(holder);
-	}
-}
-
-/* This releases any memory owned by *conf.  This does NOT free conf itself! */
-/* Not all pointers in conf necessarily point to memory owned by it. */
-static void config_release(struct iteflash_config *conf)
-{
-	null_and_free((void **)&conf->input_filename);
-	null_and_free((void **)&conf->output_filename);
-	null_and_free((void **)&conf->usb_serial);
-	null_and_free((void **)&conf->i2c_dev_path);
-}
-
-/* number of bytes to send consecutively before checking for ACKs */
-#define FTDI_TX_BUFFER_LIMIT	32
-
-static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
-				    uint8_t *data, int write, int numbytes)
-{
-	/* If we got a termination signal, stop sending data */
-	if (exit_requested)
-		return -1;
-
-	return chnd->conf.i2c_if->byte_transfer(chnd, addr, data, write,
-		numbytes);
-}
-
-static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
-				   uint8_t *data, int write, int numbytes)
-{
-	static const int nmsgs = 1;
-	int ret, extra_int;
-	struct i2c_msg i2cmsg = {};
-	struct i2c_rdwr_ioctl_data msgset = {};
-
-	i2cmsg.addr = addr;
-	if (!write)
-		i2cmsg.flags |= I2C_M_RD;
-	i2cmsg.buf = data;
-	i2cmsg.len = numbytes;
-
-	msgset.msgs = &i2cmsg;
-	msgset.nmsgs = nmsgs;
-
-	ret = ioctl(chnd->i2c_dev_fd, I2C_RDWR, &msgset);
-	if (ret < 0) {
-		extra_int = errno;
-		fprintf(stderr, "%s: ioctl() failed with return value %d and "
-			"errno %d\n", __func__, ret, extra_int);
-		if (ret == -1 && extra_int)
-			ret = -abs(extra_int);
-	} else if (ret < nmsgs) {
-		fprintf(stderr, "%s: failed to send %d of %d I2C messages\n",
-			__func__, (nmsgs - ret), nmsgs);
-		ret = -1;
-	} else {
-		ret = 0;
-	}
-	return ret;
-}
-
-static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
-			     uint8_t *ptr, uint8_t *tbuf, int tcnt, int debug)
-{
-	int ret, i, j, remaining_data, ack_idx;
-	int tx_buffered = 0;
-	static uint8_t ack[FTDI_TX_BUFFER_LIMIT];
-	uint8_t *b = ptr;
-	uint8_t failed_ack = 0;
-
-	for (i = 0; i < tcnt; i++) {
-		/* WORKAROUND: force SDA before sending the next byte */
-		*b++ = SET_BITS_LOW; *b++ = SDA_BIT; *b++ = SCL_BIT | SDA_BIT;
-		/* write byte */
-		*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-		*b++ = 0x07; *b++ = *tbuf++;
-		/* prepare for ACK */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
-		/* read ACK */
-		*b++ = MPSSE_DO_READ | MPSSE_BITMODE | MPSSE_LSB;
-		*b++ = 0;
-		*b++ = SEND_IMMEDIATE;
-
-		tx_buffered++;
-
-		/*
-		 * On the last byte, or every FTDI_TX_BUFFER_LIMIT bytes, read
-		 * the ACK bits.
-		 */
-		if (i == tcnt-1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) {
-			/* write data */
-			ret = ftdi_write_data(ftdi, buf, b - buf);
-			if (ret < 0) {
-				fprintf(stderr, "failed to write byte\n");
-				return ret;
-			}
-
-			/* read ACK bits */
-			remaining_data = tx_buffered;
-			ack_idx = 0;
-			do {
-				ret = ftdi_read_data(ftdi, &ack[ack_idx],
-					remaining_data);
-				if (ret < 0) {
-					fprintf(stderr, "read ACK failed\n");
-					return ret;
-				}
-				remaining_data -= ret;
-				ack_idx += ret;
-			} while (remaining_data);
-			for (j = 0; j < tx_buffered; j++) {
-				if ((ack[j] & 0x80) != 0)
-					failed_ack = ack[j];
-			}
-
-			/* check ACK bits */
-			if (ret < 0 || failed_ack) {
-				if (debug)
-					fprintf(stderr,
-						"write ACK fail: %d, 0x%02x\n",
-						ret, failed_ack);
-				return  -ENXIO;
-			}
-
-			/* reset for next set of transactions */
-			b = ptr;
-			tx_buffered = 0;
-		}
-	}
-	return 0;
-}
-
-static int i2c_add_recv_bytes(struct ftdi_context *ftdi, uint8_t *buf,
-			      uint8_t *ptr, uint8_t *rbuf, int rcnt)
-{
-	int ret, i, rbuf_idx;
-	uint8_t *b = ptr;
-
-	for (i = 0; i < rcnt; i++) {
-		/* set SCL low */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
-		/* read the byte on the wire */
-		*b++ = MPSSE_DO_READ; *b++ = 0; *b++ = 0;
-
-		if (i == rcnt - 1) {
-			/* NACK last byte */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
-			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0xff; *b++ = SEND_IMMEDIATE;
-		} else {
-			/* ACK all other bytes */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
-			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0; *b++ = SEND_IMMEDIATE;
-		}
-	}
-
-	ret = ftdi_write_data(ftdi, buf, b - buf);
-	if (ret < 0) {
-		fprintf(stderr, "failed to prepare read\n");
-		return ret;
-	}
-
-	rbuf_idx = 0;
-	do {
-		ret = ftdi_read_data(ftdi, &rbuf[rbuf_idx], rcnt);
-		if (ret < 0) {
-			fprintf(stderr, "read byte failed\n");
-			break;
-		}
-		rcnt -= ret;
-		rbuf_idx += ret;
-	} while (rcnt);
-
-	return ret;
-}
-
-#define USB_I2C_HEADER_SIZE 4
-static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
-				 uint8_t *data, int write, int numbytes)
-{
-	uint8_t usb_buffer[USB_I2C_HEADER_SIZE + numbytes +
-			   (((!write * numbytes) > 0x7f) ? 2 : 0)];
-	size_t response_size;
-	size_t extra = 0;
-
-	/*
-	 * Build a message following format described in ./include/usb_i2c.h.
-	 *
-	 * Hardcode port, the lowest 4 bits of the first byte, to 0; may need
-	 * to make this a command line option.
-	 */
-	usb_buffer[0] = 0;
-
-	usb_buffer[1] = addr;
-	if (write) {
-		/*
-		 * Write count might spill over into the top 4 bits of the
-		 * first byte. We trust the caller not to pass numbytes
-		 * exceeding (2^12 - 1).
-		 */
-		if (numbytes > 255)
-			usb_buffer[0] |= (numbytes >> 4) & 0xf0;
-		usb_buffer[2] = numbytes & 0xff;
-		usb_buffer[3] = 0;
-		memcpy(usb_buffer + USB_I2C_HEADER_SIZE, data, numbytes);
-	} else {
-		usb_buffer[2] = 0;
-		if (numbytes < 0x80) {
-			usb_buffer[3] = numbytes;
-		} else {
-			usb_buffer[3] = (numbytes & 0x7f) | 0x80;
-			usb_buffer[4] = numbytes >> 7;
-			usb_buffer[5] = 0;
-			extra = 2;
-		}
-	}
-
-	response_size = 0;
-	usb_trx(&chnd->uep, usb_buffer,
-		write ? sizeof(usb_buffer) : USB_I2C_HEADER_SIZE + extra,
-		usb_buffer, sizeof(usb_buffer), 1, &response_size);
-
-	if (response_size < (USB_I2C_HEADER_SIZE  + (write ? 0 : numbytes))) {
-		fprintf(stderr, "%s: got too few bytes (%zd) in response\n",
-			__func__, response_size);
-		return -1;
-	}
-
-	if (usb_buffer[0]) {
-		uint32_t rv;
-
-		/*
-		 * Error is reported as a 16 bit value in little endian byte
-		 * order.
-		 */
-		rv = usb_buffer[1];
-		rv = (rv << 8) + usb_buffer[0];
-
-		fprintf(stderr, "%s: usb i2c error %d\n",
-			__func__,
-			(((uint16_t)usb_buffer[1]) << 8) + usb_buffer[0]);
-
-		return -rv;
-	}
-
-	if (!write)
-		memcpy(data, usb_buffer + USB_I2C_HEADER_SIZE, numbytes);
-
-	return 0;
-}
-
-static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
-				  uint8_t *data, int write, int numbytes)
-{
-	int ret, rets;
-	static uint8_t buf[FTDI_CMD_BUF_SIZE];
-	uint8_t *b;
-	uint8_t slave_addr;
-	struct ftdi_context *ftdi;
-
-	ret = 0;
-	b = buf;
-	ftdi = chnd->ftdi_hnd;
-
-	/* START condition */
-	/* SCL & SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	/* SCL low, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
-
-	/* send address */
-	slave_addr = (addr << 1) | (write ? 0 : 1);
-	ret = i2c_add_send_byte(ftdi, buf, b, &slave_addr, 1, chnd->conf.debug);
-	if (ret < 0) {
-		if (chnd->conf.debug)
-			fprintf(stderr, "address %02x failed\n", addr);
-		ret = -ENXIO;
-		goto exit_xfer;
-	}
-
-	b = buf;
-	if (write) /* write data */
-		ret = i2c_add_send_byte(ftdi, buf, b, data, numbytes,
-			chnd->conf.debug);
-	else /* read data */
-		ret = i2c_add_recv_bytes(ftdi, buf, b, data, numbytes);
-
-exit_xfer:
-	b = buf;
-	/* STOP condition */
-	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	/* SCL high, SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-
-	rets = ftdi_write_data(ftdi, buf, b - buf);
-	if (rets < 0)
-		fprintf(stderr, "failed to send STOP\n");
-	return ret;
-}
-
-static int i2c_write_byte(struct common_hnd *chnd, uint8_t cmd, uint8_t data)
-{
-	int ret;
-
-	ret = i2c_byte_transfer(chnd, I2C_CMD_ADDR, &cmd, 1, 1);
-	if (ret < 0)
-		return -EIO;
-	ret = i2c_byte_transfer(chnd, I2C_DATA_ADDR, &data, 1, 1);
-	if (ret < 0)
-		return -EIO;
-
-	return 0;
-}
-
-static int i2c_read_byte(struct common_hnd *chnd, uint8_t cmd, uint8_t *data)
-{
-	int ret;
-
-	ret = i2c_byte_transfer(chnd, I2C_CMD_ADDR, &cmd, 1, 1);
-	if (ret < 0)
-		return -EIO;
-	ret = i2c_byte_transfer(chnd, I2C_DATA_ADDR, data, 0, 1);
-	if (ret < 0)
-		return -EIO;
-
-	return 0;
-}
-
-/* Configure I2C MUX to choose EC Prog channel */
-static int config_i2c_mux(struct common_hnd *chnd, uint8_t cmd)
-{
-	int ret;
-
-	ret = i2c_byte_transfer(chnd, I2C_MUX_CMD_ADDR, &cmd, 1, 1);
-	if (ret < 0) {
-		fprintf(stderr, "Failed to configure I2C MUX.");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/* Get 3rd Byte Chip ID */
-static int get_3rd_chip_id_byte(struct common_hnd *chnd, uint8_t *chip_id)
-{
-	int ret = 0;
-
-	ret = i2c_write_byte(chnd, 0x80, 0xf0);
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x85);
-	ret |= i2c_read_byte(chnd, 0x30, chip_id);
-
-	if (ret < 0)
-		fprintf(stderr, "Failed to get id of 3rd byte.");
-
-	return ret;
-}
-
-static int check_flashid(struct common_hnd *chnd)
-{
-	int ret = 0;
-	uint8_t id[16], i;
-	struct cmds commands[] = {
-		{0x07, 0x7f},
-		{0x06, 0xff},
-		{0x04, 0x00},
-		{0x05, 0xfe},
-		{0x08, 0x00},
-		{0x05, 0xfd},
-		{0x08, 0x9f}
-	};
-
-	for (i = 0; i < ARRAY_SIZE(commands); i++) {
-		ret = i2c_write_byte(chnd, commands[i].addr, commands[i].cmd);
-		if (ret) {
-			fprintf(stderr, "Flash ID Failed : cmd %x ,data %x\n",
-			commands[i].addr, commands[i].cmd);
-			return ret;
-		}
-	}
-
-	ret = i2c_byte_transfer(chnd, I2C_DATA_ADDR, id, 0, 16);
-
-	if (ret < 0)
-		fprintf(stderr, "Check Flash ID FAILED\n");
-
-	if ((id[0] == 0xFF) && (id[1] == 0xFF) && (id[2] == 0xFE)) {
-		printf("EFLASH TYPE = 8315\n\r");
-		eflash_type = EFLASH_TYPE_8315;
-	} else if ((id[0] == 0xC8) || (id[0] == 0xEF)) {
-		printf("EFLASH TYPE = KGD\n\r");
-		eflash_type = EFLASH_TYPE_KGD;
-	} else {
-		printf("Invalid EFLASH TYPE : ");
-		printf("FLASH ID = %02x %02x %02x\n\r", id[0], id[1], id[2]);
-		eflash_type = EFLASH_TYPE_NONE;
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-/* Fills in chnd->flash_size */
-static int check_chipid(struct common_hnd *chnd)
-{
-	int ret;
-	uint8_t ver = 0xff;
-	uint32_t id = 0xffff;
-	uint16_t v2[7] = {128, 192, 256, 384, 512, 0, 1024};
-	/*
-	 * Chip Version is mapping from bit 3-0
-	 * Flash size is mapping from bit 7-4
-	 *
-	 * Chip Version (bit 3-0)
-	 * 0: AX
-	 * 1: BX
-	 * 2: CX
-	 * 3: DX
-	 *
-	 * CX before flash size (bit 7-4)
-	 * 0:128KB
-	 * 4:192KB
-	 * 8:256KB
-	 *
-	 * DX flash size(bit 7-4)
-	 * 0:128KB
-	 * 2:192KB
-	 * 4:256KB
-	 * 6:384KB
-	 * 8:512KB
-	 *
-	 * flash size(bit 7-4) of it8xxx1 or it8xxx2 series
-	 * 0:128KB
-	 * 4:256KB
-	 * 8:512KB
-	 * C:1024KB
-	 */
-
-	ret = i2c_read_byte(chnd, 0x00, (uint8_t *)&id + 1);
-	if (ret < 0)
-		return ret;
-	ret = i2c_read_byte(chnd, 0x01, (uint8_t *)&id);
-	if (ret < 0)
-		return ret;
-	ret = i2c_read_byte(chnd, 0x02, &ver);
-	if (ret < 0)
-		return ret;
-
-	if ((id & 0xff00) != (CHIP_ID & 0xff00)) {
-		id |= 0xff0000;
-		ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id+2);
-		if (ret < 0)
-			return ret;
-
-		if ((id & 0xf000f) == 0x80001 || (id & 0xf000f) == 0x80002) {
-			chnd->flash_cmd_v2 = 1;
-			chnd->dbgr_addr_3bytes = 1;
-		} else {
-			fprintf(stderr, "Invalid chip id: %05x\n", id);
-			return -EINVAL;
-		}
-	} else {
-		chnd->dbgr_addr_3bytes = 0;
-		if ((ver & 0x0f) >= 0x03)
-			chnd->flash_cmd_v2 = 1;
-		else
-			chnd->flash_cmd_v2 = 0;
-	}
-	/* compute embedded flash size from CHIPVER field */
-	if (chnd->flash_cmd_v2)
-		chnd->flash_size = v2[(ver & 0xF0)>>5] * 1024;
-	else
-		chnd->flash_size = (128 + (ver & 0xF0)) * 1024;
-
-	if (chnd->flash_size == 0) {
-		fprintf(stderr, "Invalid Flash Size");
-		return -EINVAL;
-	}
-
-	printf("CHIPID %05x, CHIPVER %02x, Flash size %d kB\n", id, ver,
-		chnd->flash_size / 1024);
-
-	return 0;
-}
-
-/* DBGR Reset */
-static int dbgr_reset(struct common_hnd *chnd, unsigned char val)
-{
-	int ret = 0;
-
-	/* Reset CPU only, and we keep power state until flashing is done. */
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x06);
-
-	/* Enable the Reset Status by val */
-	ret |= i2c_write_byte(chnd, 0x30, val);
-
-	ret |= i2c_write_byte(chnd, 0x27, 0x80);
-	if (ret < 0)
-		fprintf(stderr, "DBGR RESET FAILED\n");
-
-	return 0;
-}
-
-/* Exit DBGR mode */
-static int exit_dbgr_mode(struct common_hnd *chnd)
-{
-	int ret = 0;
-
-	printf("Exit DBGR mode...\n");
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-	ret |= i2c_write_byte(chnd, 0x2f, 0x1c);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x08);
-	ret |= i2c_write_byte(chnd, 0x30, BIT(4));
-
-	if (ret < 0)
-		fprintf(stderr, "EXIT DBGR MODE FAILED\n");
-
-	return 0;
-}
-
-/* DBGR reset GPIOs to default */
-static int dbgr_reset_gpio(struct common_hnd *chnd)
-{
-	int ret = 0;
-
-	printf("Reset GPIOs to default.\n");
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x07);
-	ret |= i2c_write_byte(chnd, 0x30, BIT(1));
-
-	if (ret < 0)
-		fprintf(stderr, "DBGR RESET GPIO FAILED\n");
-
-	return 0;
-}
-
-/* disable watchdog */
-static int dbgr_disable_watchdog(struct common_hnd *chnd)
-{
-	int ret = 0;
-
-	printf("Disabling watchdog...\n");
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-
-	ret |= i2c_write_byte(chnd, 0x2f, 0x1f);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x05);
-	ret |= i2c_write_byte(chnd, 0x30, 0x30);
-
-	if (ret < 0)
-		fprintf(stderr, "DBGR DISABLE WATCHDOG FAILED!\n");
-
-	return ret;
-}
-
-/* disable protect path from DBGR */
-static int dbgr_disable_protect_path(struct common_hnd *chnd)
-{
-	int ret = 0, i;
-
-	printf("Disabling protect path...\n");
-
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	for (i = 0; i < 32; i++) {
-		ret |= i2c_write_byte(chnd, 0x2e, 0xa0+i);
-		ret |= i2c_write_byte(chnd, 0x30, 0);
-	}
-
-	if (ret < 0)
-		fprintf(stderr, "DISABLE PROTECT PATH FROM DBGR FAILED!\n");
-
-	return ret;
-}
-
-/* Enter follow mode and FSCE# high level */
-static int spi_flash_follow_mode(struct common_hnd *chnd, char *desc)
-{
-	int ret = 0;
-
-	ret |= i2c_write_byte(chnd, 0x07, 0x7f);
-	ret |= i2c_write_byte(chnd, 0x06, 0xff);
-	ret |= i2c_write_byte(chnd, 0x05, 0xfe);
-	ret |= i2c_write_byte(chnd, 0x04, 0x00);
-	ret |= i2c_write_byte(chnd, 0x08, 0x00);
-
-	ret = (ret ? -EIO : 0);
-	if (ret < 0)
-		fprintf(stderr, "Flash %s enter follow mode FAILED (%d)\n",
-			desc, ret);
-
-	return ret;
-}
-
-/* Exit follow mode */
-static int spi_flash_follow_mode_exit(struct common_hnd *chnd, char *desc)
-{
-	int ret = 0;
-
-	ret |= i2c_write_byte(chnd, 0x07, 0x00);
-	ret |= i2c_write_byte(chnd, 0x06, 0x00);
-
-	ret = (ret ? -EIO : 0);
-	if (ret < 0)
-		fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n",
-			desc, ret);
-
-	return ret;
-}
-
-/* Stop EC by sending follow mode command */
-static int dbgr_stop_ec(struct common_hnd *chnd)
-{
-	int ret = 0;
-
-	ret |= spi_flash_follow_mode(chnd, "enter follow mode");
-	ret |= spi_flash_follow_mode_exit(chnd, "exit follow mode");
-
-	if (ret < 0)
-		fprintf(stderr, "DBGR STOP EC FAILED!\n");
-
-	return ret;
-}
-
-/* SPI Flash generic command, short version */
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc)
-{
-	int ret = 0;
-
-	ret |= i2c_write_byte(chnd, 0x05, 0xfe);
-	ret |= i2c_write_byte(chnd, 0x08, 0x00);
-	ret |= i2c_write_byte(chnd, 0x05, 0xfd);
-	ret |= i2c_write_byte(chnd, 0x08, cmd);
-
-	ret = (ret ? -EIO : 0);
-	if (ret < 0)
-		fprintf(stderr, "Flash CMD %s FAILED (%d)\n", desc, ret);
-
-	return ret;
-}
-
-/* SPI Flash set erase page */
-static int spi_flash_set_erase_page(struct common_hnd *chnd,
-				    int page, char *desc)
-{
-	int ret = 0;
-
-	ret |= i2c_write_byte(chnd, 0x08, page >> 8);
-	ret |= i2c_write_byte(chnd, 0x08, page & 0xff);
-	ret |= i2c_write_byte(chnd, 0x08, 0);
-
-	ret = (ret ? -EIO : 0);
-	if (ret < 0)
-		fprintf(stderr, "Flash %s set page FAILED (%d)\n", desc, ret);
-
-	return ret;
-}
-
-/* Poll SPI Flash Read Status register until BUSY is reset */
-static int spi_poll_busy(struct common_hnd *chnd, char *desc)
-{
-	uint8_t reg = 0xff;
-	int ret = -EIO;
-
-	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for busy bit") < 0) {
-		fprintf(stderr, "Flash %s wait busy cleared FAILED\n", desc);
-		goto failed_read_status;
-	}
-
-	while (1) {
-		if (i2c_byte_transfer(chnd, I2C_DATA_ADDR, &reg, 0, 1) < 0) {
-			fprintf(stderr, "Flash polling busy cleared FAILED\n");
-			break;
-		}
-
-		if ((reg & 0x01) == 0) {
-			/* busy bit cleared */
-			ret = 0;
-			break;
-		}
-	}
-failed_read_status:
-	return ret;
-}
-
-static int spi_check_write_enable(struct common_hnd *chnd, char *desc)
-{
-	uint8_t reg = 0xff;
-	int ret = -EIO;
-
-	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for write enable bit") < 0) {
-		fprintf(stderr, "Flash %s wait WE FAILED\n", desc);
-		goto failed_read_status;
-	}
-
-	while (1) {
-		if (i2c_byte_transfer(chnd, I2C_DATA_ADDR, &reg, 0, 1) < 0) {
-			fprintf(stderr, "Flash polling WE FAILED\n");
-			break;
-		}
-
-		if ((reg & 0x03) == 2) {
-			/* busy bit cleared and WE bit set */
-			ret = 0;
-			break;
-		}
-	}
-failed_read_status:
-	return ret;
-}
-
-static int ftdi_config_i2c(struct ftdi_context *ftdi)
-{
-	int ret;
-	static const uint16_t divisor =
-		60000000 / (2 * FTDI_I2C_FREQ * 3 / 2 /* 3-phase CLK */) - 1;
-	uint8_t clock_buf[] = {
-		EN_3_PHASE,
-		DIS_DIV_5,
-		TCK_DIVISOR,
-		divisor & 0xff,
-		divisor >> 8};
-
-	ret = ftdi_set_latency_timer(ftdi, 16 /* ms */);
-	if (ret < 0)
-		fprintf(stderr, "Cannot set latency\n");
-
-	ret = ftdi_set_bitmode(ftdi, 0, BITMODE_RESET);
-	if (ret < 0) {
-		fprintf(stderr, "Cannot reset MPSSE\n");
-		return -EIO;
-	}
-	ret = ftdi_set_bitmode(ftdi, 0, BITMODE_MPSSE);
-	if (ret < 0) {
-		fprintf(stderr, "Cannot enable MPSSE\n");
-		return -EIO;
-	}
-
-	ret = ftdi_usb_purge_buffers(ftdi);
-	if (ret < 0)
-		fprintf(stderr, "Cannot purge buffers\n");
-
-	/* configure the clock */
-	ret = ftdi_write_data(ftdi, clock_buf, sizeof(clock_buf));
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
-
-/* Special waveform definition */
-#define SPECIAL_LEN_USEC 50000ULL /* us */
-#define SPECIAL_FREQ    400000ULL
-
-#define SPECIAL_PATTERN 0x0000020301010302ULL
-#define SPECIAL_PATTERN_SDA_L_SCL_L 0x0000000000000000ULL
-#define SPECIAL_PATTERN_SDA_H_SCL_L 0x0202020202020202ULL
-#define SPECIAL_PATTERN_SDA_L_SCL_H 0x0101010101010101ULL
-#define SPECIAL_PATTERN_SDA_H_SCL_H 0x0303030303030303ULL
-#define TICK_COUNT 24
-
-#define MSEC    1000
-#define USEC 1000000
-
-#define SPECIAL_BUFFER_SIZE \
-	(((SPECIAL_LEN_USEC * SPECIAL_FREQ * 2 / USEC) + 7) & ~7)
-
-static int connect_to_ccd_i2c_bridge(struct common_hnd *chnd)
-{
-	int rv;
-
-	rv = usb_findit(chnd->conf.usb_serial, chnd->conf.usb_vid,
-			chnd->conf.usb_pid, CR50_I2C_SUBCLASS,
-			CR50_I2C_PROTOCOL, &chnd->uep);
-
-	if (rv) {
-		fprintf(stderr, "%s: usb_findit returned error %d\n",
-			__func__, rv);
-	}
-
-	return rv;
-}
-
-static int ccd_trigger_special_waveform(struct common_hnd *chnd)
-{
-	uint8_t response[20];
-	size_t rsize;
-	uint8_t req[] = {
-		0, /* Port 0. Might be necessary to modify. */
-		CROS_CMD_ADDR, /* Chrome OS dedicated address. */
-		1,	/* Will send a single byte command. */
-		0,	/* No need to read back anything. */
-		CROS_CMD_ITE_SYNC
-	};
-
-	usb_trx(&chnd->uep, req, sizeof(req), response, sizeof(response), 1,
-		&rsize);
-
-	if (rsize < USB_I2C_HEADER_SIZE)
-		return -1;
-
-	if (response[0])
-		return -response[0];
-	/*
-	 * The target is about to get reset, let's shut down the USB
-	 * connection.
-	 */
-	usb_shut_down(&chnd->uep);
-
-	sleep(3);
-
-	return connect_to_ccd_i2c_bridge(chnd);
-}
-
-static int ftdi_send_special_waveform(struct common_hnd *chnd)
-{
-	int ret;
-	int i;
-	uint64_t *wave;
-	struct ftdi_context *ftdi = chnd->ftdi_hnd;
-	uint8_t release_lines[] = {SET_BITS_LOW, 0, 0};
-
-	wave = malloc(SPECIAL_BUFFER_SIZE);
-	if (!wave) {
-		fprintf(stderr, "malloc(%zu) failed\n",
-			(size_t)SPECIAL_BUFFER_SIZE);
-		return -1;
-	}
-
-	/* Reset the FTDI into a known state */
-	ret = ftdi_set_bitmode(ftdi, 0xFF, BITMODE_RESET);
-	if (ret) {
-		fprintf(stderr, "failed to reset FTDI\n");
-		goto free_and_return;
-	}
-
-	/*
-	 * set the clock divider, so we output a new bitbang value every
-	 * 2.5us.
-	 */
-	ret = ftdi_set_baudrate(ftdi, 160000);
-	if (ret) {
-		fprintf(stderr, "failed to set bitbang clock\n");
-		goto free_and_return;
-	}
-
-	/* Enable asynchronous bit-bang mode */
-	ret = ftdi_set_bitmode(ftdi, 0xFF, BITMODE_BITBANG);
-	if (ret) {
-		fprintf(stderr, "failed to set bitbang mode\n");
-		goto free_and_return;
-	}
-
-	/* do usb special waveform */
-	wave[0] = 0x0;
-	ftdi_write_data(ftdi, (uint8_t *)wave, 1);
-	usleep(5000);
-
-	/* program each special tick */
-	for (i = 0; i < TICK_COUNT; ) {
-		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
-		wave[i++] = SPECIAL_PATTERN_SDA_H_SCL_L;
-		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
-	}
-	wave[19] = SPECIAL_PATTERN_SDA_H_SCL_H;
-
-	/* fill the buffer with the waveform pattern */
-	for (i = TICK_COUNT; i < SPECIAL_BUFFER_SIZE / sizeof(uint64_t); i++)
-		wave[i] = SPECIAL_PATTERN;
-
-	ret = ftdi_write_data(ftdi, (uint8_t *)wave, SPECIAL_BUFFER_SIZE);
-	if (ret < 0)
-		fprintf(stderr, "Cannot output special waveform\n");
-	else
-		/* no error */
-		ret = 0;
-
-	/* clean everything to go back to regular I2C communication */
-	ftdi_usb_purge_buffers(ftdi);
-	ftdi_set_bitmode(ftdi, 0xff, BITMODE_RESET);
-	ftdi_config_i2c(ftdi);
-	ftdi_write_data(ftdi, release_lines, sizeof(release_lines));
-
- free_and_return:
-	free(wave);
-	return ret;
-}
-
-static int send_special_waveform(struct common_hnd *chnd)
-{
-	const int max_iterations = 10;
-	int ret;
-	int iterations;
-
-	if (!chnd->conf.i2c_if->send_special_waveform) {
-		fprintf(stderr, "This binary does not support sending the ITE "
-			"special waveform with the chosen I2C interface.\n");
-		return -1;
-	}
-
-	iterations = 0;
-
-	do {
-		ret = chnd->conf.i2c_if->send_special_waveform(chnd);
-		if (ret)
-			break;
-
-		/* wait for PLL stable for 5ms (plus remaining USB transfers) */
-		usleep(10 * MSEC);
-
-		/* Stop EC ASAP after sending special waveform. */
-		if (dbgr_stop_ec(chnd) >= 0) {
-			/*
-			 * If we can talk to chip, then we can break the retry
-			 * loop.
-			 */
-			ret = check_chipid(chnd);
-		} else {
-			ret = -1;
-			if (!(iterations % max_iterations))
-				fprintf(stderr, "!please reset EC if flashing"
-					" sequence is not starting!\n");
-		}
-	} while (ret && (iterations++ < max_iterations));
-
-	if (ret)
-		fprintf(stderr, "Failed to send special waveform!\n");
-	else
-		printf("Done with sending special waveform.\n");
-
-	return ret;
-}
-
-static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
-static void draw_spinner(uint32_t remaining, uint32_t size)
-{
-	int percent = (size - remaining)*100/size;
-	fprintf(stderr, "\r%c%3d%%", wheel[windex++], percent);
-	windex %= sizeof(wheel);
-}
-
-/* Note: this function must be called in follow mode */
-static int spi_send_cmd_fast_read(struct common_hnd *chnd, uint32_t addr)
-{
-	int ret = 0;
-	uint8_t cmd = 0x9;
-
-	/* Fast Read command */
-	ret = spi_flash_command_short(chnd, SPI_CMD_FAST_READ, "fast read");
-	/* Send address */
-	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 16) & 0xff)); /* addr_h */
-	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff));  /* addr_m */
-	ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff));         /* addr_l */
-	/* fake byte */
-	ret |= i2c_write_byte(chnd, 0x08, 0x00);
-	/* use i2c block read command */
-	ret |= i2c_byte_transfer(chnd, I2C_CMD_ADDR, &cmd, 1, 1);
-	if (ret < 0)
-		fprintf(stderr, "Send fast read command failed\n");
-
-	return ret;
-}
-
-static int command_read_pages(struct common_hnd *chnd, uint32_t address,
-			      uint32_t size, uint8_t *buffer)
-{
-	int res = -EIO;
-	uint32_t remaining = size;
-	int cnt;
-
-	if (address & 0xFF) {
-		fprintf(stderr, "page read requested at non-page boundary: "
-			"0x%X\n", address);
-		return -EINVAL;
-	}
-
-	if (spi_flash_follow_mode(chnd, "fast read") < 0)
-		goto failed_read;
-
-	if (spi_send_cmd_fast_read(chnd, address) < 0)
-		goto failed_read;
-
-	while (remaining) {
-		cnt = (remaining > PAGE_SIZE) ? PAGE_SIZE : remaining;
-		draw_spinner(remaining, size);
-
-		/* read page data */
-		res = i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, buffer, 0, cnt);
-		if (res < 0) {
-			fprintf(stderr, "page data read failed\n");
-			goto failed_read;
-		}
-
-		address += cnt;
-		remaining -= cnt;
-		buffer += cnt;
-
-		/* We need to resend fast read command at 256KB boundary. */
-		if (!(address % 0x40000) && remaining) {
-			if (spi_send_cmd_fast_read(chnd, address) < 0)
-				goto failed_read;
-		}
-	}
-	/* No error so far */
-	res = size;
-failed_read:
-	if (spi_flash_follow_mode_exit(chnd, "fast read") < 0)
-		res = -EIO;
-
-	return res;
-}
-
-static bool is_empty_page(uint8_t *buffer, int size)
-{
-	int i;
-
-	for (i = 0; i < size; i++) {
-		if (buffer[i] != 0xFF)
-			return false;
-	}
-
-	return true;
-}
-
-static int command_write_pages(struct common_hnd *chnd, uint32_t address,
-			       uint32_t size, uint8_t *buffer)
-{
-	int res = -EIO;
-	int block_write_size = chnd->conf.block_write_size;
-	uint32_t remaining = size;
-	int cnt;
-	uint8_t addr_H, addr_M, addr_L;
-	uint8_t data;
-
-	if (spi_flash_follow_mode(chnd, "AAI write") < 0)
-		goto failed_write;
-
-	while (remaining) {
-		cnt = (remaining > block_write_size) ?
-			block_write_size : remaining;
-		addr_H = (address >> 16) & 0xFF;
-		addr_M = (address >> 8) & 0xFF;
-		addr_L = address & 0xFF;
-
-		draw_spinner(remaining, size);
-
-		/* Write enable */
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for AAI write") < 0)
-			goto failed_write;
-
-		/* Check write enable bit */
-		if (spi_check_write_enable(chnd, "AAI write") < 0)
-			goto failed_write;
-
-		/* Setup write */
-		if (spi_flash_command_short(chnd, SPI_CMD_WORD_PROGRAM,
-			"AAI write") < 0)
-			goto failed_write;
-
-		/* Set eflash page address */
-		res = i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_H, 1, 1);
-		res |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_M, 1, 1);
-		res |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_L, 1, 1);
-		if (res < 0) {
-			fprintf(stderr, "Flash write set page FAILED (%d)\n",
-					res);
-			goto failed_write;
-		}
-
-		/* Wait until not busy */
-		if (spi_poll_busy(chnd, "AAI write") < 0)
-			goto failed_write;
-
-		/* Write up to block_write_size data */
-		res = i2c_write_byte(chnd, 0x10, 0x20);
-		res = i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, buffer, 1, cnt);
-		buffer += cnt;
-
-		if (res < 0) {
-			fprintf(stderr, "Flash data write failed\n");
-			goto failed_write;
-		}
-
-		data = 0xFF;
-		res = i2c_byte_transfer(chnd, I2C_DATA_ADDR, &data, 1, 1);
-		res |= i2c_write_byte(chnd, 0x10, 0x00);
-		if (res < 0) {
-			fprintf(stderr, "Flash end data write FAILED (%d)\n",
-					res);
-			goto failed_write;
-		}
-
-		/* Write disable */
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for AAI write") < 0)
-			goto failed_write;
-
-		/* Wait until available */
-		if (spi_poll_busy(chnd, "write disable for AAI write") < 0)
-			goto failed_write;
-
-		address += cnt;
-		remaining -= cnt;
-	}
-	draw_spinner(remaining, size);
-	/* No error so far */
-	res = size;
-failed_write:
-	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit AAI write") < 0)
-		res = -EIO;
-
-	if (spi_flash_follow_mode_exit(chnd, "AAI write") < 0)
-		res = -EIO;
-
-	return res;
-}
-
-/*
- * Test for spi page program command
- */
-static int command_write_pages3(struct common_hnd *chnd, uint32_t address,
-				uint32_t size, uint8_t *buffer)
-{
-	int ret = 0;
-	uint8_t addr_H, addr_M, addr_L;
-
-	/* SMB_SPI_Flash_Write_Enable */
-	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-		"SPI Command Write Enable") < 0) {
-		ret = -EIO;
-		goto failed_write;
-	}
-
-	if (spi_flash_command_short(chnd, SPI_CMD_PAGE_PROGRAM,
-		"SPI_CMD_PAGE_PROGRAM") < 0) {
-		ret = -EIO;
-		goto failed_write;
-	}
-
-	addr_H = (address >> 16) & 0xFF;
-	addr_M = (address >> 8) & 0xFF;
-	addr_L = address & 0xFF;
-
-	ret = i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_H, 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_M, 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_L, 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, buffer, 1, size);
-	if (ret < 0)
-		goto failed_write;
-
-	/* Wait until not busy */
-	if (spi_poll_busy(chnd, "Page Program") < 0)
-		ret = -EIO;
-
-	/* No error so far */
-failed_write:
-	return ret;
-}
-
-
-
-static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
-{
-	int res = -EIO;
-	int page = 0;
-	uint32_t remaining = len;
-
-	printf("Erasing chip...\n");
-
-	if (off != 0 || len != chnd->flash_size) {
-		fprintf(stderr, "Only full chip erase is supported\n");
-		return -EINVAL;
-	}
-
-	if (spi_flash_follow_mode(chnd, "erase") < 0)
-		goto failed_erase;
-
-	while (remaining) {
-		draw_spinner(remaining, len);
-
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
-			goto failed_erase;
-
-		if (spi_check_write_enable(chnd, "erase") < 0)
-			goto failed_erase;
-
-		/* do chip erase */
-		if (remaining == chnd->flash_size) {
-			if (spi_flash_command_short(chnd, SPI_CMD_CHIP_ERASE,
-				"chip erase") < 0)
-				goto failed_erase;
-			goto wait_busy_cleared;
-		}
-
-		/* do sector erase */
-		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
-			goto failed_erase;
-
-		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
-			goto failed_erase;
-
-wait_busy_cleared:
-		if (spi_poll_busy(chnd, "erase") < 0)
-			goto failed_erase;
-
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
-			goto failed_erase;
-
-		if (remaining == chnd->flash_size)  {
-			remaining = 0;
-			draw_spinner(remaining, len);
-		} else {
-			page += sector_erase_pages;
-			remaining -= sector_erase_pages * PAGE_SIZE;
-		}
-	}
-
-	/* No error so far */
-	printf("\n\rErasing Done.\n");
-	res = 0;
-
-failed_erase:
-	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
-		res = -EIO;
-
-	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
-		res = -EIO;
-
-	return res;
-}
-
-/*
- * This function can Erase First Sector or Erase All Sector by reset value
- * Some F/W will produce the H/W watchdog reset and it will happen
- * reset issue while flash.
- * Add such function to prevent the reset issue.
- */
-static int command_erase2(struct common_hnd *chnd, uint32_t len,
-			  uint32_t off, uint32_t reset)
-{
-	int res = -EIO;
-	int page = 0;
-	uint32_t remaining = len;
-
-	/*
-	 * TODOD(b/<>):
-	 * Using sector erase instead of chip erase
-	 * For some new chip , the chip erase may not work
-	 * well on the original flow
-	 */
-
-	printf("Erasing flash...erase size=%d\n", len);
-
-	if (off != 0 || len != chnd->flash_size) {
-		fprintf(stderr, "Only full chip erase is supported\n");
-		return -EINVAL;
-	}
-
-	if (spi_flash_follow_mode(chnd, "erase") < 0)
-		goto failed_erase;
-
-	while (remaining) {
-
-		draw_spinner(remaining, len);
-
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
-			goto failed_erase;
-
-		if (spi_check_write_enable(chnd, "erase") < 0)
-			goto failed_erase;
-
-		/* do sector erase */
-		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
-			goto failed_erase;
-
-		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
-			goto failed_erase;
-
-		if (spi_poll_busy(chnd, "erase") < 0)
-			goto failed_erase;
-
-		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
-			goto failed_erase;
-
-		if (reset) {
-			printf("\n\rreset to prevent the watchdog reset...\n");
-			break;
-		}
-
-		page += sector_erase_pages;
-		remaining -= sector_erase_pages * PAGE_SIZE;
-		draw_spinner(remaining, len);
-
-	}
-
-	/* No error so far */
-	printf("\n\rErasing Done.\n");
-	res = 0;
-
-failed_erase:
-	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
-		res = -EIO;
-
-	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
-		res = -EIO;
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-static int read_flash(struct common_hnd *chnd)
-{
-	int res;
-	FILE *hnd;
-	uint8_t *buffer;
-	const char *filename = chnd->conf.input_filename;
-	size_t offset = chnd->conf.range_base;
-	size_t size;
-
-	if (!offset && !chnd->conf.range_size) {
-		size = chnd->flash_size;
-	} else {
-		/*
-		 * Zero conf.range_size means the user did not enter range
-		 * size in the command line.
-		 */
-		if (chnd->conf.range_size)
-			size = chnd->conf.range_size;
-		else
-			size = chnd->flash_size - offset;
-
-		if (!size) {
-			fprintf(stderr,
-				"Error: not reading a zero sized range!\n");
-			return -EINVAL;
-		}
-
-		if ((size + offset) > chnd->flash_size) {
-			fprintf(stderr,
-				"Error: Read range exceeds flash size!\n");
-			return -EINVAL;
-		}
-	}
-
-	buffer = malloc(size);
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %zd bytes\n", size);
-		return -ENOMEM;
-	}
-
-	hnd = fopen(filename, "w");
-	if (!hnd) {
-		fprintf(stderr, "Cannot open file %s for writing\n", filename);
-		free(buffer);
-		return -EIO;
-	}
-
-	printf("Reading %zd bytes at %#08zx\n", size, offset);
-	res = command_read_pages(chnd, offset, size, buffer);
-	if (res > 0) {
-		if (fwrite(buffer, res, 1, hnd) != 1)
-			fprintf(stderr, "Cannot write %s\n", filename);
-	}
-	printf("\r   %d bytes read.\n", res);
-
-	fclose(hnd);
-	free(buffer);
-	return (res < 0) ? res : 0;
-}
-
-/* Return zero on success, a negative error value on failures. */
-static int write_flash(struct common_hnd *chnd, const char *filename,
-		       uint32_t offset)
-{
-	int res, written;
-	FILE *hnd;
-	int size = chnd->flash_size;
-	uint8_t *buffer = malloc(size);
-
-	if (!buffer) {
-		fprintf(stderr, "%s: Cannot allocate %d bytes\n", __func__,
-			size);
-		return -ENOMEM;
-	}
-
-	hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "%s: Cannot open file %s for reading\n",
-			__func__, filename);
-		free(buffer);
-		return -EIO;
-	}
-	res = fread(buffer, 1, size, hnd);
-	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
-		free(buffer);
-		fclose(hnd);
-		return -EIO;
-	}
-	fclose(hnd);
-
-	printf("Writing %d bytes at 0x%08x\n", res, offset);
-	written = command_write_pages(chnd, offset, res, buffer);
-	if (written != res) {
-		fprintf(stderr, "%s: Error writing to flash\n", __func__);
-		free(buffer);
-		return -EIO;
-	}
-	printf("\n\rWriting Done.\n");
-
-	free(buffer);
-	return 0;
-}
-
-/*
- * Return zero on success, a negative error value on failures.
- *
- * Change the program command to match the ITE Download
- * The original flow may not work on the DX chip.
- *
- */
-static int write_flash2(struct common_hnd *chnd, const char *filename,
-			uint32_t offset)
-{
-	int res;
-	int block_write_size = chnd->conf.block_write_size;
-	FILE *hnd;
-	int size = chnd->flash_size;
-	int cnt, two_bytes_sent, ret;
-	uint8_t addr_h, addr_m, addr_l, data_ff = 0xff;
-	uint8_t *buffer = malloc(size);
-
-	if (!buffer) {
-		fprintf(stderr, "%s: Cannot allocate %d bytes\n", __func__,
-			size);
-		return -ENOMEM;
-	}
-
-	hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "%s: Cannot open file %s for reading\n",
-			__func__, filename);
-		free(buffer);
-		return -EIO;
-	}
-	res = fread(buffer, 1, size, hnd);
-	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
-		fclose(hnd);
-		free(buffer);
-		return -EIO;
-	}
-	fclose(hnd);
-
-	/* Enter follow mode */
-	if (spi_flash_follow_mode(chnd, "AAI write") < 0) {
-		ret = -EIO;
-		goto failed_enter_mode;
-	}
-
-	printf("Writing %d bytes at 0x%08x.......\n", res, offset);
-
-__send_aai_cmd:
-	addr_h = (offset >> 16) & 0xff;
-	addr_m = (offset >> 8) & 0xff;
-	addr_l = offset & 0xff;
-
-	/* write enable command */
-	ret = spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE, "SPI WE");
-	/* AAI command */
-	ret |= spi_flash_command_short(chnd, SPI_CMD_WORD_PROGRAM, "SPI AAI");
-	/* address of AAI command */
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_h, 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_m, 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_l, 1, 1);
-	/* Send first two bytes of buffe */
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset], 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset+1], 1, 1);
-	/* we had sent two bytes */
-	offset += 2;
-	res -= 2;
-	two_bytes_sent = 1;
-	/* Wait until not busy */
-	if (spi_poll_busy(chnd, "wait busy bit cleared at AAI write ") < 0) {
-		ret = -EIO;
-		goto failed_write;
-	}
-	/* enable quick AAI mode */
-	ret |= i2c_write_byte(chnd, 0x10, 0x20);
-	if (ret < 0)
-		goto failed_write;
-
-	while (res) {
-		cnt = (res > block_write_size) ? block_write_size : res;
-		/* we had sent two bytes */
-		if (two_bytes_sent) {
-			two_bytes_sent = 0;
-			cnt -= 2;
-		}
-		if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset],
-			1, cnt) < 0) {
-			ret = -EIO;
-			goto failed_write;
-		}
-
-		res -= cnt;
-		offset += cnt;
-		draw_spinner(res, res + offset);
-
-		/* We need to resend aai write command at 256KB boundary. */
-		if (!(offset % 0x40000) && res) {
-			/* disable quick AAI mode */
-			i2c_byte_transfer(chnd, I2C_DATA_ADDR, &data_ff, 1, 1);
-			i2c_write_byte(chnd, 0x10, 0x00);
-			/* write disable command */
-			spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-				"SPI write disable");
-			goto __send_aai_cmd;
-		}
-	}
-
-failed_write:
-	/* disable quick AAI mode */
-	i2c_byte_transfer(chnd, I2C_DATA_ADDR, &data_ff, 1, 1);
-	i2c_write_byte(chnd, 0x10, 0x00);
-	/* write disable command */
-	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
-failed_enter_mode:
-	/* exit follow mode */
-	spi_flash_follow_mode_exit(chnd, "AAI write");
-
-	if (ret < 0)
-		printf("\n\rWriting Failed.\n");
-	else
-		printf("\n\rWriting Done.\n");
-
-	free(buffer);
-
-	return ret;
-}
-
-/*
- * Return zero on success, a negative error value on failures.
- *
- * Change the program command to match the ITE Download
- * The original flow may not work on the DX chip.
- *
- */
-static int write_flash3(struct common_hnd *chnd, const char *filename,
-			uint32_t offset)
-{
-	int res, ret = 0;
-	int block_write_size = chnd->conf.block_write_size;
-	FILE *hnd;
-	int size = chnd->flash_size;
-	int cnt;
-	uint8_t *buf = malloc(size);
-
-	if (!buf) {
-		fprintf(stderr, "%s: Cannot allocate %d bytes\n", __func__,
-			size);
-		return -ENOMEM;
-	}
-
-	hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "%s: Cannot open file %s for reading\n",
-			__func__, filename);
-		free(buf);
-		return -EIO;
-	}
-	res = fread(buf, 1, size, hnd);
-	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
-		fclose(hnd);
-		free(buf);
-		return -EIO;
-	}
-	fclose(hnd);
-
-	printf("Writing %d bytes at 0x%08x.......\n", res, offset);
-
-	/* Enter follow mode */
-	ret = spi_flash_follow_mode(chnd, "Page program");
-	if (ret < 0)
-		goto failed_write;
-
-	/* Page program instruction allows up to 256 bytes */
-	if (block_write_size > 256)
-		block_write_size = 256;
-
-	while (res) {
-		cnt = (res > block_write_size) ? block_write_size : res;
-		if (chnd->conf.erase && is_empty_page(&buf[offset], cnt)) {
-			/* do nothing */
-		} else if (command_write_pages3(chnd, offset, cnt, &buf[offset])
-				< 0) {
-			ret = -EIO;
-			goto failed_write;
-		}
-
-		res -= cnt;
-		offset += cnt;
-		draw_spinner(res, res + offset);
-	}
-
-failed_write:
-	free(buf);
-	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
-	spi_flash_follow_mode_exit(chnd, "Page program");
-	if (ret < 0)
-		fprintf(stderr, "%s: Error writing to flash\n", __func__);
-	else
-		printf("\n\rWriting Done.\n");
-
-	return ret;
-}
-
-
-
-/* Return zero on success, a non-zero value on failures. */
-static int verify_flash(struct common_hnd *chnd, const char *filename,
-			uint32_t offset)
-{
-	int res;
-	int file_size;
-	FILE *hnd;
-	uint8_t *buffer  = malloc(chnd->flash_size);
-	uint8_t *buffer2 = malloc(chnd->flash_size);
-
-	if (!buffer || !buffer2) {
-		fprintf(stderr, "%s: Cannot allocate %d bytes\n", __func__,
-			chnd->flash_size);
-		free(buffer);
-		free(buffer2);
-		return -ENOMEM;
-	}
-
-	hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "%s: Cannot open file %s for reading\n",
-			__func__, filename);
-		res = -EIO;
-		goto exit;
-	}
-
-	file_size = fread(buffer, 1, chnd->flash_size, hnd);
-	if (file_size <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, chnd->flash_size, filename,
-			ferror(hnd));
-		fclose(hnd);
-		res = -EIO;
-		goto exit;
-	}
-	fclose(hnd);
-
-	printf("Verify %d bytes at 0x%08x\n", file_size, offset);
-	res = command_read_pages(chnd, offset, chnd->flash_size, buffer2);
-	if (res > 0)
-		res = memcmp(buffer, buffer2, file_size);
-
-	printf("\n\rVerify %s\n", res ? "Failed!" : "Done.");
-
-exit:
-	free(buffer);
-	free(buffer2);
-	return res;
-}
-
-static struct ftdi_context *open_ftdi_device(int vid, int pid,
-					     int interface, const char *serial)
-{
-	struct ftdi_context *ftdi;
-	int ret;
-
-	ftdi = ftdi_new();
-	if (!ftdi) {
-		fprintf(stderr, "Cannot allocate context memory\n");
-		return NULL;
-	}
-
-	ret = ftdi_set_interface(ftdi, interface);
-	if (ret < 0) {
-		fprintf(stderr, "cannot set ftdi interface %d: %s(%d)\n",
-			interface, ftdi_get_error_string(ftdi), ret);
-		goto open_failed;
-	}
-	ret = ftdi_usb_open_desc(ftdi, vid, pid, NULL, serial);
-	if (ret < 0) {
-		fprintf(stderr, "unable to open ftdi device: %s(%d)\n",
-			ftdi_get_error_string(ftdi), ret);
-		goto open_failed;
-	}
-	return ftdi;
-
-open_failed:
-	ftdi_free(ftdi);
-	return NULL;
-}
-
-static int linux_i2c_interface_init(struct common_hnd *chnd)
-{
-	int err;
-
-	if (!chnd->conf.i2c_dev_path) {
-		fprintf(stderr, "Must set --i2c_dev_path when using "
-				"Linux i2c-dev interface.\n");
-		return -1;
-	}
-	printf("Attempting to open Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
-	chnd->i2c_dev_fd = open(chnd->conf.i2c_dev_path, O_RDWR);
-	if (chnd->i2c_dev_fd < 0) {
-		err = errno;
-		perror("Failed to open Linux i2c-dev file path with error");
-		fprintf(stderr, "Linux i2c-dev file path from --i2c_dev_path "
-			"is: %s\n", chnd->conf.i2c_dev_path);
-		return err ? err : -1;
-	}
-	printf("Successfully opened Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
-	return 0;
-}
-
-static int linux_i2c_interface_shutdown(struct common_hnd *chnd)
-{
-	int err;
-
-	printf("Attempting to close Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
-	if (close(chnd->i2c_dev_fd)) {
-		err = errno;
-		perror("Failed to close Linux i2c-dev file descriptor with "
-			"error");
-		return err ? err : -1;
-	}
-	printf("Successfully closed Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
-	return 0;
-}
-
-static int ccd_i2c_interface_init(struct common_hnd *chnd)
-{
-	chnd->conf.usb_vid = CR50_USB_VID;
-	chnd->conf.usb_pid = CR50_USB_PID;
-	return connect_to_ccd_i2c_bridge(chnd);
-}
-
-static int ccd_i2c_interface_shutdown(struct common_hnd *chnd)
-{
-	usb_shut_down(&chnd->uep);
-	return 0;
-}
-
-static int ftdi_i2c_interface_init(struct common_hnd *chnd)
-{
-	chnd->ftdi_hnd = open_ftdi_device(chnd->conf.usb_vid,
-		chnd->conf.usb_pid, chnd->conf.usb_interface,
-		chnd->conf.usb_serial);
-	if (chnd->ftdi_hnd == NULL)
-		return -1;
-	return 0;
-}
-
-static int ftdi_i2c_interface_post_waveform(struct common_hnd *chnd)
-{
-	return chnd->conf.send_waveform ? 0 : ftdi_config_i2c(chnd->ftdi_hnd);
-}
-
-/* Close the FTDI USB handle */
-static int ftdi_i2c_interface_shutdown(struct common_hnd *chnd)
-{
-	ftdi_usb_close(chnd->ftdi_hnd);
-	ftdi_free(chnd->ftdi_hnd);
-	return 0;
-}
-
-static const struct i2c_interface linux_i2c_interface = {
-	.interface_init = linux_i2c_interface_init,
-	.interface_shutdown = linux_i2c_interface_shutdown,
-	.byte_transfer = linux_i2c_byte_transfer,
-	/*
-	 * 254 bytes is the largest size that works with Servo Micro as of
-	 * 2018-11-30. Odd numbers up to 255 result in corruption, and 256 or
-	 * greater fails with a timeout from the I2C bus. Fixing that so this
-	 * can be increased to match FTDI_BLOCK_WRITE_SIZE would be a useful
-	 * speedup.
-	 *
-	 * 254 byte block sizes cause corruption with Ampton (using any kind of
-	 * servo).  128 bytes is the largest block_write_size compatible with
-	 * both Ampton and Servo Micro.
-	 *
-	 * See https://issuetracker.google.com/79684405 for background.
-	 */
-	.default_block_write_size = 128,
-};
-
-static const struct i2c_interface ccd_i2c_interface = {
-	.interface_init = ccd_i2c_interface_init,
-	.interface_shutdown = ccd_i2c_interface_shutdown,
-	.send_special_waveform = ccd_trigger_special_waveform,
-	.byte_transfer = ccd_i2c_byte_transfer,
-	.default_block_write_size = PAGE_SIZE,
-};
-
-static const struct i2c_interface ftdi_i2c_interface = {
-	.interface_init = ftdi_i2c_interface_init,
-	.interface_post_waveform = ftdi_i2c_interface_post_waveform,
-	.interface_shutdown = ftdi_i2c_interface_shutdown,
-	.send_special_waveform = ftdi_send_special_waveform,
-	.byte_transfer = ftdi_i2c_byte_transfer,
-	.default_block_write_size = FTDI_BLOCK_WRITE_SIZE,
-};
-
-static int post_waveform_work(struct common_hnd *chnd)
-{
-	int ret;
-
-	if (chnd->conf.i2c_if->interface_post_waveform) {
-		ret = chnd->conf.i2c_if->interface_post_waveform(chnd);
-		if (ret)
-			return ret;
-	}
-
-	if (chnd->conf.disable_watchdog) {
-		ret = dbgr_disable_watchdog(chnd);
-		if (ret)
-			return ret;
-	}
-
-	if (chnd->conf.disable_protect_path) {
-		ret = dbgr_disable_protect_path(chnd);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int strdup_with_errmsg(const char *source, char **dest, const char *name)
-{
-	int ret = 0;
-	*dest = strdup(source);
-	if (!(*dest)) {
-		ret = errno ? errno : -1;
-		fprintf(stderr, "strdup() of %zu size string from %s failed.\n",
-			strlen(source), name);
-	}
-	return ret;
-}
-
-static const struct option longopts[] = {
-	{"block-write-size", 1, 0, 'b'},
-	{"debug", 0, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"help", 0, 0, 'h'},
-	{"i2c-dev-path", 1, 0, 'D'},
-	{"i2c-interface", 1, 0, 'c'},
-	{"i2c-mux", 0, 0, 'm'},
-	{"interface", 1, 0, 'i'},
-	{"nodisable-protect-path", 0, 0, 'Z'},
-	{"nodisable-watchdog", 0, 0, 'z'},
-	{"noverify", 0, 0, 'n'},
-	{"product", 1, 0, 'p'},
-	{"range", 1, 0, 'R'},
-	{"read", 1, 0, 'r'},
-	{"send-waveform", 1, 0, 'W'},
-	{"serial", 1, 0, 's'},
-	{"vendor", 1, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
-};
-
-static void display_usage(const char *program)
-{
-	fprintf(stderr, "Usage: %s [-d] [-v <VID>] [-p <PID>] \\\n"
-		"\t[-c <linux|ccd|ftdi>] [-D /dev/i2c-<N>] [-i <1|2>] [-S] \\\n"
-		"\t[-s <serial>] [-e] [-r <file>] [-W <0|1|false|true>] \\\n"
-		"\t[-w <file>] [-R base[:size]] [-m] [-b <size>]\n",
-		program);
-	fprintf(stderr, "-d, --debug : Output debug traces.\n");
-	fprintf(stderr, "-e, --erase : Erase all the flash content.\n");
-	fprintf(stderr, "-c, --i2c-interface <linux|ccd|ftdi> : I2C interface "
-			"to use\n");
-	fprintf(stderr, "-D, --i2c-dev-path /dev/i2c-<N> : Path to "
-			"Linux i2c-dev file e.g. /dev/i2c-5;\n"
-			"\tonly applicable with --i2c-interface=linux\n");
-	fprintf(stderr, "-i, --interface <1> : FTDI interface: A=1, B=2,"
-			" ...\n");
-	fprintf(stderr, "-m, --i2c-mux : Enable i2c-mux (to EC).\n"
-		"\tSpecify this flag only if the board has an I2C MUX and\n"
-		"\tyou are not using servod.\n");
-	fprintf(stderr, "-n, --noverify : Don't auto verify.\n");
-	fprintf(stderr, "-b, --block-write-size <size> : Perform writes in\n"
-		"\tblocks of this many bytes.\n");
-	fprintf(stderr, "-p, --product <0x1234> : USB product ID\n");
-	fprintf(stderr, "-R, --range base[:size] : Allow to read or write"
-		" just a slice\n"
-		"\tof the file, starting at <base>:<size> bytes, or til\n"
-		"\tthe end of the file if <size> is not specified, expressed\n"
-		"\tin hex.\n");
-	fprintf(stderr, "-r, --read <file> : Read the flash content and"
-			" write it into <file>.\n");
-	fprintf(stderr, "-s, --serial <serialname> : USB serial string\n");
-	fprintf(stderr, "-v, --vendor <0x1234> : USB vendor ID\n");
-	fprintf(stderr, "-W, --send-waveform <0|1|false|true> : Send the"
-		" special waveform.\n"
-		"\tDefault is true. Set to false if ITE direct firmware\n"
-		"\tupdate mode has already been enabled.\n");
-	fprintf(stderr, "-w, --write <file> : Write <file> to flash.\n");
-	fprintf(stderr, "-z, --nodisable-watchdog : Do *not* disable EC "
-		"watchdog.\n");
-	fprintf(stderr, "-Z, --nodisable-protect-path : Do *not* disable EC "
-		"protect path.\n");
-}
-
-/*
- * Parses -R command line option parameter, returns zero on success and
- * -1 on errors (non hex values, missing values, etc.).
- */
-static int parse_range_options(char *str, struct iteflash_config *conf)
-{
-	char *size;
-
-	if (!str) {
-		fprintf(stderr,	"missing range base address specification\n");
-		return -1;
-	}
-
-	conf->range_base = strtoull(str, &size, 16);
-	if (!size || !*size)
-		return 0;
-
-	if (*size++ != ':') {
-		fprintf(stderr, "wrong range base address specification\n");
-		return -1;
-	}
-
-	if (!*size) {
-		fprintf(stderr, "missing range size specification\n");
-		return -1;
-	}
-
-	conf->range_size = strtoull(size, &size, 16);
-	if ((size && *size) || !conf->range_size) {
-		fprintf(stderr, "wrong range size specification\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
-{
-	int opt, idx, ret = 0;
-
-	while (!ret &&
-	       (opt = getopt_long(argc, argv, "?b:c:D:dehi:mp:R:r:s:uv:W:w:Zz",
-				  longopts, &idx)) != -1) {
-		switch (opt) {
-		case 'b':
-			conf->block_write_size = strtol(optarg, NULL, 10);
-			break;
-		case 'c':
-			if (!strcasecmp(optarg, "linux")) {
-				conf->i2c_if = &linux_i2c_interface;
-			} else if (!strcasecmp(optarg, "ccd")) {
-				conf->i2c_if = &ccd_i2c_interface;
-			} else if (!strcasecmp(optarg, "ftdi")) {
-				conf->i2c_if = &ftdi_i2c_interface;
-			} else {
-				fprintf(stderr, "Unexpected -c / "
-					"--i2c-interface value: %s\n", optarg);
-				ret = -1;
-			}
-			break;
-		case 'D':
-			ret = strdup_with_errmsg(optarg, &conf->i2c_dev_path,
-				"-D / --i2c-dev-path");
-			break;
-		case 'd':
-			conf->debug = 1;
-			break;
-		case 'e':
-			conf->erase = 1;
-			break;
-		case 'h':
-		case '?':
-			display_usage(argv[0]);
-			ret = 2;
-			break;
-		case 'i':
-			conf->usb_interface = strtol(optarg, NULL, 10);
-			break;
-		case 'm':
-			conf->i2c_mux = 1;
-			break;
-		case 'n':
-			conf->verify = 0;
-			break;
-		case 'p':
-			conf->usb_pid = strtol(optarg, NULL, 16);
-			break;
-		case 'R':
-			ret = parse_range_options(optarg, conf);
-			break;
-		case 'r':
-			ret = strdup_with_errmsg(optarg, &conf->input_filename,
-				"-r / --read");
-			break;
-		case 's':
-			ret = strdup_with_errmsg(optarg, &conf->usb_serial,
-				"-s / --serial");
-			break;
-		case 'v':
-			conf->usb_vid = strtol(optarg, NULL, 16);
-			break;
-		case 'W':
-			if (!strcmp(optarg, "0") ||
-			    !strcasecmp(optarg, "false")) {
-				conf->send_waveform = 0;
-				break;
-			}
-			if (!strcmp(optarg, "1") ||
-			    !strcasecmp(optarg, "true")) {
-				conf->send_waveform = 1;
-				break;
-			}
-			fprintf(stderr, "Unexpected -W / --special-waveform "
-				"value: %s\n", optarg);
-			ret = -1;
-			break;
-		case 'w':
-			ret = strdup_with_errmsg(optarg, &conf->output_filename,
-				"-w / --write");
-			break;
-		case 'z':
-			conf->disable_watchdog = 0;
-			break;
-		case 'Z':
-			conf->disable_protect_path = 0;
-			break;
-		}
-	}
-
-	if (ret)
-		config_release(conf);
-	return ret;
-}
-
-static void sighandler(int signum)
-{
-	int status;
-	printf("\nCaught signal %d: %s\nExiting...\n",
-		signum, strsignal(signum));
-	wait(&status);
-	exit_requested = status;
-}
-
-static void register_sigaction(void)
-{
-	struct sigaction sigact;
-
-	memset(&sigact, 0, sizeof(sigact));
-	sigact.sa_handler = sighandler;
-	sigemptyset(&sigact.sa_mask);
-	sigact.sa_flags = 0;
-	sigaction(SIGINT, &sigact, NULL);
-	sigaction(SIGTERM, &sigact, NULL);
-	sigaction(SIGQUIT, &sigact, NULL);
-}
-
-int main(int argc, char **argv)
-{
-	int ret = 1, other_ret;
-	struct common_hnd chnd = {
-		/* Default flag settings. */
-		.conf = {
-			.send_waveform = 1,
-			.disable_watchdog = 1,
-			.disable_protect_path = 1,
-			.usb_interface = SERVO_INTERFACE,
-			.usb_vid = SERVO_USB_VID,
-			.usb_pid = SERVO_USB_PID,
-			.verify = 1,
-			.i2c_if = &ftdi_i2c_interface,
-		},
-	};
-
-	/* Parse command line options */
-	other_ret = parse_parameters(argc, argv, &chnd.conf);
-	if (other_ret)
-		return other_ret;
-
-	/* Fill in block_write_size if not set from command line. */
-	if (!chnd.conf.block_write_size)
-		chnd.conf.block_write_size =
-			chnd.conf.i2c_if->default_block_write_size;
-
-	/* Open the communications channel. */
-	if (chnd.conf.i2c_if->interface_init &&
-	    chnd.conf.i2c_if->interface_init(&chnd))
-		goto return_after_parse;
-
-	/* Register signal handler after opening the communications channel. */
-	register_sigaction();
-
-	if (chnd.conf.i2c_mux) {
-		printf("configuring I2C MUX to EC.\n");
-
-		if (config_i2c_mux(&chnd, I2C_MUX_CMD_EC))
-			goto return_after_init;
-	}
-
-	/* Trigger embedded monitor detection */
-	if (chnd.conf.send_waveform) {
-		if (send_special_waveform(&chnd))
-			goto return_after_init;
-	} else {
-		/* Stop EC ASAP after sending special waveform. */
-		dbgr_stop_ec(&chnd);
-
-		ret = check_chipid(&chnd);
-		if (ret) {
-			fprintf(stderr, "Failed to get ITE chip ID.  This "
-				"could be because the ITE direct firmware "
-				"update (DFU) mode is not enabled.\n");
-			goto return_after_init;
-		}
-	}
-
-	/* Turn off power rails by reset GPIOs to default (input). */
-	dbgr_reset_gpio(&chnd);
-
-	check_flashid(&chnd);
-
-	ret = post_waveform_work(&chnd);
-	if (ret)
-		goto return_after_init;
-
-	if (chnd.conf.input_filename) {
-		ret = read_flash(&chnd);
-		if (ret)
-			goto return_after_init;
-	}
-
-	switch (eflash_type) {
-	case EFLASH_TYPE_8315:
-		sector_erase_pages = 4;
-		spi_cmd_sector_erase = SPI_CMD_SECTOR_ERASE_1K;
-		break;
-	case EFLASH_TYPE_KGD:
-		sector_erase_pages = 16;
-		spi_cmd_sector_erase = SPI_CMD_SECTOR_ERASE_4K;
-		break;
-	default:
-		printf("Invalid EFLASH TYPE!");
-		ret = -EINVAL;
-		break;
-	}
-
-	if (ret)
-		goto return_after_init;
-
-	if (chnd.conf.erase) {
-		if (chnd.flash_cmd_v2)
-			/* Do Normal Erase Function */
-			command_erase2(&chnd, chnd.flash_size, 0, 0);
-		else
-			command_erase(&chnd, chnd.flash_size, 0);
-		/* Call DBGR Rest to clear the EC lock status after erasing */
-		dbgr_reset(&chnd, RSTS_VCCDO_PW_ON|RSTS_HGRST|RSTS_GRST);
-	}
-
-	if (chnd.conf.output_filename) {
-		if (chnd.flash_cmd_v2)
-			switch (eflash_type) {
-			case EFLASH_TYPE_8315:
-				ret = write_flash2(&chnd,
-					chnd.conf.output_filename, 0);
-				break;
-			case EFLASH_TYPE_KGD:
-				ret = write_flash3(&chnd,
-					chnd.conf.output_filename, 0);
-				break;
-			default:
-				printf("Invalid EFLASH TYPE!");
-				ret = -EINVAL;
-				break;
-			}
-		else
-			ret = write_flash(&chnd, chnd.conf.output_filename, 0);
-		if (ret)
-			goto return_after_init;
-		if (chnd.conf.verify) {
-			ret = verify_flash(&chnd, chnd.conf.output_filename, 0);
-			if (ret)
-				goto return_after_init;
-		}
-	}
-
-	/* Normal exit */
-	ret = 0;
-
- return_after_init:
-	/*
-	 * Exit DBGR mode. This ensures EC won't hold clock/data pins of I2C.
-	 * Avoid resetting EC here because flash_ec will after iteflash exits.
-	 * This avoids double reset after flash sequence.
-	 */
-	exit_dbgr_mode(&chnd);
-
-	if (chnd.conf.i2c_mux) {
-		printf("configuring I2C MUX to none.\n");
-		config_i2c_mux(&chnd, I2C_MUX_CMD_NONE);
-	}
-
-	if (chnd.conf.i2c_if->interface_shutdown) {
-		other_ret = chnd.conf.i2c_if->interface_shutdown(&chnd);
-		if (!ret && other_ret)
-			ret = other_ret;
-	}
-
- return_after_parse:
-	config_release(&chnd.conf);
-	return ret;
-}
diff --git a/util/iteflash.md b/util/iteflash.md
deleted file mode 100644
index 4d0db0fcc6..0000000000
--- a/util/iteflash.md
+++ /dev/null
@@ -1,167 +0,0 @@
-# Reflashing an ITE EC
-
-This doc: [http://go/cros-ite-ec-reflash](https://goto.google.com/cros-ite-ec-reflash)
-<br>
-First written: 2019-04-02
-<br>
-Last updated: 2019-04-03
-
-Familiarity with [Chromium OS](https://www.chromium.org/chromium-os)
-[Embedded Controller (EC) development](../README.md) is assumed.
-
-[TOC]
-
-## Background
-
-### Terminology
-
-**ITE EC** refers to the [ITE](http://www.ite.com.tw/)
-[IT8320](http://www.ite.com.tw/en/product/view?mid=96)
-[Embedded Controller (EC)](https://en.wikipedia.org/wiki/Embedded_controller)
-microcontroller when used as a Chromium OS / Chrome OS EC.
-
-**CrOS** refers to Chromium OS, Chrome OS, or both, depending on the context.
-The distinction between Chromium OS and Chrome OS is largely immaterial to this
-document.
-
-**Servo** refers to a debug board providing direct debug access to various
-circuits on a Chrome OS device motherboard. As of this writing, the most common
-[servos](https://www.chromium.org/chromium-os/servo) used by CrOS developers are
-[CR50 (CCD)](https://www.chromium.org/chromium-os/ccd),
-[Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro), and
-[Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2). (Note that
-[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) is **not** a
-Servo in this sense. It is a USB hub with a microcontroller that proxies Servo
-functionality from either CR50 or Servo Micro.) See also
-[Case-Closed Debug in Chromebooks and Servo Micro](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/board/servo_micro/ccd.md).
-
-### How ITE EC reflashing works
-
-An ITE EC is reflashed using a Servo by:
-
-1.  Sending special non-I2C waveforms over its I2C clock and data lines, to
-    enable a debug mode / direct firmware update (DFU) mode.
-
-1.  Communicating with it using I2C, including transferring the actual EC image
-    over I2C.  The ITE EC will only respond over I2C after receiving the special
-    waveforms.
-
-### Further reading
-
-Googlers, and Partners involved in ITE EC projects, see
-[The State of ITE CrOS EC Reflashing](https://docs.google.com/document/d/1fs29eBvwKrOWYozLZXTg7ObwAO5dyM4Js2Vq301EwAU/preview).
-That document is not public, do not request access if you lack it.
-
-## How to reflash
-
-### Prerequisites for CR50 CCD
-
-This section applies whether using CR50 CCD via
-[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or
-[SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
-
-CR50 MP minimum firmware version: `0.3.15`
-<br>
-CR50 pre-PVT minimum firmware version: `0.4.15`
-
-Googlers, to upgrade CR50 firmware if needed see
-[How to use CCD on CR50](https://docs.google.com/document/d/1MqDAoBsmGTmrFi-WNOoC5R-UFeuQK37_9kaEdCFU8QE/preview).
-That document is not public, do not request access if you lack it.
-
-The CR50 CCD capabilities must be set to `always`. To achieve this:
-
-1.  Open CCD.
-    *   root shell: `$ gsctool -o`
-    *   CR50 console: `ccd open`
-1.  Reset CCD to `factory` mode.
-    *   CR50 console: `ccd reset factory`
-
-Reflashing with CR50 also requires the [i2c-pseudo kernel module](#i2c-pseudo),
-unless using the [CR50 CCD sans servod](#ccd-sans-servod) alternative method.
-
-### Prerequisites for Servo Micro
-
-This section applies whether the
-[Servo Micro](https://www.chromium.org/chromium-os/servo/servomicro) is
-connected directly to your development host, or through a
-[Servo v4](https://www.chromium.org/chromium-os/servo/servov4).
-
-Servo Micro minimum firmware version: `servo_micro_v2.3.5`
-
-To upgrade Servo Micro firmware if needed:
-
-1.  Enter the chroot.
-    *   `$ cros_sdk`
-1.  Run servo_updater.
-    *   `$ sudo servo_updater --board=servo_micro`
-
-If that still results in too old of a firmware version, use `repo sync` and
-`update_chroot` to update your CrOS development environment, then try again.
-
-Reflashing with Servo Micro also requires the
-[i2c-pseudo kernel module](#i2c-pseudo).
-
-### Installing i2c-pseudo {#i2c-pseudo}
-
-1.  Install the `i2c-pseudo` Linux kernel module. (Do this **outside** of the
-    chroot!)
-    *   `$ cd src/platform/ec/extra/i2c_pseudo`
-    *   `$ ./install`
-
-If the above fails, your system may be missing packages necessary for building
-kernel modules. Consult your Linux distribution's documentation and support
-forums. After installing any packages that might be missing, simply try the
-install script again.
-
-You will need to reinstall `i2c-pseudo` after each kernel upgrade.
-
-There is an intention to
-[upstream i2c-pseudo](https://issuetracker.google.com/129565355), though even if
-accepted upstream, it may or may not become included with common Linux
-distribution kernels.
-
-### Common reflash instructions
-
-These instructions apply when using any kind of Servo, including those with no
-special prerequisites (such as
-[Servo v2](https://www.chromium.org/chromium-os/servo/servo-v2) with its Yoshi
-flex cable connected to the DUT).
-
-1.  Enter the chroot (for servod).
-    *   `$ cros_sdk --no-ns-pid`
-1.  Start servod.
-    *   `$ sudo servod --board=<servod_board_name>`
-    *   For some boards the servod board name is different than the EC codebase
-        board name used below!
-1.  Enter the chroot (for flash_ec).
-    *   `$ cros_sdk`
-1.  Build the EC image for your board.
-    *   `$ cd ~/trunk/src/platform/ec`
-    *   `$ board=<board_name>`
-    *   `$ make -j BOARD="$board"`
-1.  Run flash_ec from the util directory.
-    *   `$ util/flash_ec --board="$board" --image=build/"$board"/ec.bin`
-
-## CR50 CCD sans servod alternative {#ccd-sans-servod}
-
-This section applies whether using CR50 CCD via
-[Servo v4](https://www.chromium.org/chromium-os/servo/servov4) or
-[SuzyQ aka SuzyQable](https://www.sparkfun.com/products/14746).
-
-When using CR50 CCD, it is possible to reflash without servod, which _must not_
-be running when using this method.
-
-1.  Enter the chroot.
-    *   `$ cros_sdk`
-1.  Build the EC image for your board.
-    *   `$ cd ~/trunk/src/platform/ec`
-    *   `$ board=<board_name>`
-    *   `$ make -j BOARD="$board"`
-1.  Run iteflash from the build/\<board\>/util directory.
-    *   `$ build/"$board"/util/iteflash --i2c-interface=ccd --i2c-mux
-        --send-waveform=1 --erase --write=build/"$board"/ec.bin`
-
-WARNING: The `--i2c-mux` flag is only required for some ITE EC boards. For
-boards without an I2C mux between CR50 and the EC, that flag _must not_ be
-specified. (This is handled for you when using `flash_ec` + `servod` because the
-latter has knowledge of which boards are expected to have the I2C mux.)
diff --git a/util/kconfig_check.py b/util/kconfig_check.py
deleted file mode 100755
index b6b9fda8de..0000000000
--- a/util/kconfig_check.py
+++ /dev/null
@@ -1,209 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Kconfig checker
-
-Checks that the .config file provided does not introduce any new ad-hoc CONFIG
-options
-"""
-
-import argparse
-import os
-import re
-import sys
-
-
-def parse_args(argv):
-    """Parse the program arguments
-
-    Args:
-        argv: List of arguments to parse, excluding the program name
-
-    Returns:
-        argparse.Namespace object containing the results
-    """
-    epilog = """Checks that new ad-hoc CONFIG options are not introduced without
-a corresponding Kconfig option for Zephyr"""
-
-    parser = argparse.ArgumentParser(epilog=epilog)
-    parser.add_argument('-a', '--allowed', type=str,
-                        default='util/config_allowed.txt',
-                        help='File containing list of allowed ad-hoc CONFIGs')
-    parser.add_argument('-c', '--configs', type=str, default='.config',
-                        help='File containing CONFIG options to check')
-    parser.add_argument(
-        '-D', '--debug', action='store_true',
-        help='Enabling debugging (provides a full traceback on error)')
-    parser.add_argument('-p', '--prefix', type=str, default='PLATFORM_EC_',
-                        help='Prefix to string from Kconfig options')
-    parser.add_argument('-s', '--srctree', type=str, default='.',
-                        help='Path to source tree to look for Kconfigs')
-
-    subparsers = parser.add_subparsers(dest='cmd', required=True)
-    subparsers.add_parser('check', help='Check for new ad-hoc CONFIGs')
-
-    return parser.parse_args(argv)
-
-
-class KconfigCheck:
-    """Class for handling checking of CONFIG options against Kconfig options
-
-    The goal is to make sure that CONFIG_xxx options used by a build have an
-    equivalent Kconfig option defined as well.
-
-    For example if a Kconfig file has:
-
-         config PREFIX_MY_CONFIG
-             ...
-
-    and the CONFIG files has
-
-         CONFIG_MY_CONFIG
-
-    then we consider these equivalent (with the prefix 'PREFIX_') and thus
-    CONFIG_MY_CONFIG is allowed to be used.
-
-    If any CONFIG option is found that does not have an equivalent in the Kconfig,
-    the user is exhorted to add a new Kconfig. This helps avoid adding new ad-hoc
-    CONFIG options, eventually returning the number to zero.
-    """
-    @classmethod
-    def find_new_adhoc(cls, configs, kconfigs, allowed):
-        """Get a list of new ad-hoc CONFIG options
-
-        Arguments and return value should omit the 'CONFIG_' prefix, so
-        CONFIG_LTO should be provided as 'LTO'.
-
-        Args:
-            configs: List of existing CONFIG options
-            kconfigs: List of existing Kconfig options
-            allowed: List of allowed CONFIG options
-
-        Returns:
-            List of new CONFIG options, with the CONFIG_ prefix removed
-        """
-        return sorted(list(set(configs) - set(kconfigs) - set(allowed)))
-
-    @classmethod
-    def read_configs(cls, configs_file):
-        """Read CONFIG options from a file
-
-        Args:
-            configs_file: Filename to read from
-
-        Returns:
-            List of CONFIG_xxx options found in the file, with the 'CONFIG_'
-                prefixremoved
-        """
-        with open(configs_file, 'r') as inf:
-            configs = re.findall('CONFIG_([A-Za-z0-9_]*)', inf.read())
-        return configs
-
-    @classmethod
-    def find_kconfigs(cls, srcdir):
-        """Find all the Kconfig files in a source directory, recursively
-
-        Any subdirectory called 'Kconfig' is ignored, since Zephyr generates
-        this in its build directory.
-
-        Args:
-            srcdir: Directory to scan
-
-        Returns:
-            List of pathnames found
-        """
-        kconfig_files = []
-        for root, dirs, files in os.walk(srcdir):
-            kconfig_files += [os.path.join(root, fname)
-                              for fname in files if fname.startswith('Kconfig')]
-            if 'Kconfig' in dirs:
-                dirs.remove('Kconfig')
-        return kconfig_files
-
-    def scan_kconfigs(self, srcdir, prefix=''):
-        """Scan a source tree for Kconfig options
-
-        Args:
-            srcdir: Directory to scan
-            prefix: Prefix to strip from the name (e.g. 'PLATFORM_EC_')
-
-        Returns:
-            List of config and menuconfig options found,
-        """
-        kconfigs = []
-
-        # Remove the prefix if present
-        expr = re.compile(r'(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n' %
-                          prefix)
-        for fname in self.find_kconfigs(srcdir):
-            with open(fname) as inf:
-                found = re.findall(expr, inf.read())
-                kconfigs += [name for kctype, _, name in found]
-        return kconfigs
-
-    def find_new_adhoc_configs(self, configs_file, srcdir, allowed_file,
-                               prefix=''):
-        """Find new ad-hoc configs in the configs_file
-
-        Args:
-            configs_file: Filename containing CONFIG options to check
-            srcdir: Source directory to scan for Kconfig files
-            allowed_file: File containing allowed CONFIG options
-            prefix: Prefix to strip from the start of each Kconfig
-                (e.g. 'PLATFORM_EC_')
-        """
-        configs = self.read_configs(configs_file)
-        kconfigs = self.scan_kconfigs(srcdir, prefix)
-        allowed = self.read_configs(allowed_file)
-        new_adhoc = self.find_new_adhoc(configs, kconfigs, allowed)
-        return new_adhoc
-
-    def do_check(self, configs_file, srcdir, allowed_file, prefix):
-        """Find new ad-hoc configs in the configs_file
-
-        Args:
-            configs_file: Filename containing CONFIG options to check
-            srcdir: Source directory to scan for Kconfig files
-            allowed_file: File containing allowed CONFIG options
-            prefix: Prefix to strip from the start of each Kconfig
-                (e.g. 'PLATFORM_EC_')
-
-        Returns:
-            Exit code: 0 if OK, 1 if a problem was found
-        """
-        new_adhoc = self.find_new_adhoc_configs(configs_file, srcdir,
-                                                allowed_file, prefix)
-        if new_adhoc:
-            print("""Error:\tThe EC is in the process of migrating to Zephyr.
-\tZephyr uses Kconfig for configuration rather than ad-hoc #defines.
-\tAny new EC CONFIG options must ALSO be added to Zephyr so that new
-\tfunctionality is available in Zephyr also. The following new ad-hoc
-\tCONFIG options were detected:
-
-%s
-
-Please add these via Kconfig instead. Find a suitable Kconfig
-file in zephyr/ and add a 'config' or 'menuconfig' option.
-Also see details in http://issuetracker.google.com/181253613
-
-To temporarily disable this, use: ALLOW_CONFIG=1 make ...
-""" % '\n'.join(['CONFIG_%s' % name for name in new_adhoc]), file=sys.stderr)
-            return 1
-        return 0
-
-
-def main(argv):
-    """Main function"""
-    args = parse_args(argv)
-    if not args.debug:
-        sys.tracebacklimit = 0
-    checker = KconfigCheck()
-    if args.cmd == 'check':
-        return checker.do_check(args.configs, args.srctree, args.allowed,
-                                args.prefix)
-    return 2
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/util/keeby-relevant-paths.txt b/util/keeby-relevant-paths.txt
deleted file mode 120000
index 9b63ef59c7..0000000000
--- a/util/keeby-relevant-paths.txt
+++ /dev/null
@@ -1 +0,0 @@
-dedede-relevant-paths.txt
\ No newline at end of file
diff --git a/util/lbcc.c b/util/lbcc.c
deleted file mode 100644
index 4a3633153e..0000000000
--- a/util/lbcc.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "lb_common.h"
-#include "lightbar.h"
-
-static const char usage[] =
-	"\n"
-	"Usage:  %s [OPTIONS] [INFILE [OUTFILE]]\n"
-	"\n"
-	"This compiles or decompiles the lightbar programmable bytecode.\n"
-	"\n"
-	"Options:\n"
-	"  -d         Decode binary to ascii\n"
-	"  -v         Decode output should be verbose\n"
-	"\n";
-
-/* globals */
-static int hit_errors;
-static int opt_verbose;
-static int is_jump_target[EC_LB_PROG_LEN];	/* does program jump here? */
-static int is_instruction[EC_LB_PROG_LEN];	/* instruction or operand? */
-static char *label[EC_LB_PROG_LEN];		/* labels we've seen */
-static char *reloc_label[EC_LB_PROG_LEN];	/* put label target here */
-
-static void Error(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	fprintf(stderr, "ERROR: ");
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-	hit_errors++;
-}
-
-static void Warning(const char *format, ...)
-{
-	va_list ap;
-	va_start(ap, format);
-	fprintf(stderr, "Warning: ");
-	vfprintf(stderr, format, ap);
-	va_end(ap);
-}
-
-/* The longest line should have a label, an opcode, and the max operands */
-#define LB_PROG_MAX_OPERANDS 4
-#define MAX_WORDS (2 + LB_PROG_MAX_OPERANDS)
-
-struct safe_lightbar_program {
-	struct lightbar_program p;
-	uint8_t zeros[LB_PROG_MAX_OPERANDS];
-} __packed;
-
-#define OP(NAME, BYTES, MNEMONIC) NAME,
-#include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) BYTES,
-#include "lightbar_opcode_list.h"
-static const int num_operands[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-#define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
-#include "lightbar_opcode_list.h"
-static const char * const opcode_sym[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
-#undef OP
-
-static const char * const control_sym[] = {
-	"beg", "end", "phase", "<invalid>"
-};
-static const char * const color_sym[] = {
-	"r", "g", "b", "<invalid>"
-};
-
-static void read_binary(FILE *fp, struct safe_lightbar_program *prog)
-{
-	int got;
-
-	memset(prog, 0, sizeof(*prog));
-
-	/* Read up to one more byte than we need, so we know if it's too big */
-	got = fread(prog->p.data, 1, EC_LB_PROG_LEN + 1, fp);
-	if (got < 1) {
-		Error("Unable to read any input: ");
-		if (feof(fp))
-			fprintf(stderr, "EOF\n");
-		else if (ferror(fp))
-			fprintf(stderr, "%s\n", strerror(errno));
-		else
-			fprintf(stderr, "no idea why.\n");
-	} else if (got > EC_LB_PROG_LEN) {
-		Warning("Truncating input at %d bytes\n", EC_LB_PROG_LEN);
-		prog->zeros[0] = 0;
-		got = EC_LB_PROG_LEN;
-	} else {
-		prog->p.size = got;
-	}
-}
-
-static uint32_t val32(uint8_t *ptr)
-{
-	uint32_t val;
-	val = (ptr[0] << 24) | (ptr[1] << 16) | (ptr[2] << 8) | ptr[3];
-	return val;
-}
-
-static int is_jump(uint8_t op)
-{
-	/* TODO: probably should be a field in the opcode list */
-	return op >= JUMP && op <= JUMP_IF_CHARGING;
-}
-
-static void print_led_set(FILE *fp, uint8_t led)
-{
-	int i, first = 1;
-
-	fprintf(fp, "{");
-	for (i = 0; i < NUM_LEDS; i++)
-		if (led & BIT(i)) {
-			if (!first)
-				fprintf(fp, ",");
-			fprintf(fp, "%d", i);
-			first = 0;
-		}
-	fprintf(fp, "}");
-}
-
-/* returns number of operands consumed */
-static int print_op(FILE *fp, uint8_t addr, uint8_t cmd, uint8_t *arg)
-{
-	uint8_t led, color, control;
-	int i, operands;
-
-	operands = num_operands[cmd];
-
-	/* assume valid instruction for now */
-	is_instruction[addr] = 1;
-
-	if (opt_verbose) {
-		fprintf(fp, "%02x:  %02x", addr, cmd);
-		for (i = 0; i < LB_PROG_MAX_OPERANDS; i++)
-			if (i < operands)
-				fprintf(fp, " %02x", arg[i]);
-			else
-				fprintf(fp, "   ");
-		fprintf(fp, "\t");
-	}
-	if (is_jump_target[addr])
-		fprintf(fp, "L00%02x:", addr);
-	fprintf(fp, "\t");
-
-	if (cmd < MAX_OPCODE)
-		fprintf(fp, "%s", opcode_sym[cmd]);
-
-	switch (cmd) {
-	case JUMP:
-	case JUMP_IF_CHARGING:
-		fprintf(fp, "\tL00%02x\n", arg[0]);
-		break;
-	case JUMP_BATTERY:
-		fprintf(fp, "\tL00%02x L00%02x\n", arg[0], arg[1]);
-		break;
-	case SET_WAIT_DELAY:
-	case SET_RAMP_DELAY:
-		fprintf(fp, "\t%d\n", val32(arg));
-		break;
-	case SET_BRIGHTNESS:
-		fprintf(fp, "\t%d\n", arg[0]);
-		break;
-	case SET_COLOR_SINGLE:
-		led = arg[0] >> 4;
-		control = (arg[0] >> 2) & 0x03;
-		color = arg[0] & 0x03;
-		fprintf(fp, "\t");
-
-		print_led_set(fp, led);
-		fprintf(fp, ".%s", control_sym[control]);
-		fprintf(fp, ".%s", color_sym[color]);
-		fprintf(fp, "\t0x%02x\n", arg[1]);
-		break;
-	case SET_COLOR_RGB:
-		led = arg[0] >> 4;
-		control = (arg[0] >> 2) & 0x03;
-		fprintf(fp, "\t");
-
-		print_led_set(fp, led);
-		fprintf(fp, ".%s", control_sym[control]);
-		fprintf(fp, "\t0x%02x 0x%02x 0x%02x\n", arg[1], arg[2], arg[3]);
-		break;
-	case ON:
-	case OFF:
-	case WAIT:
-	case GET_COLORS:
-	case SWAP_COLORS:
-	case RAMP_ONCE:
-	case CYCLE_ONCE:
-	case CYCLE:
-	case HALT:
-		fprintf(fp, "\n");
-		break;
-	default:
-		fprintf(fp, "-- invalid opcode 0x%02x --\n", cmd);
-		is_instruction[addr] = 0;
-		hit_errors++;
-	}
-
-	return operands;
-}
-
-static void set_jump_target(uint8_t targ)
-{
-	if (targ >= EC_LB_PROG_LEN) {
-		Warning("program jumps to 0x%02x, "
-			"which out of bounds\n", targ);
-		return;
-	}
-	is_jump_target[targ] = 1;
-}
-
-static void disassemble_prog(FILE *fp, struct safe_lightbar_program *prog)
-{
-	int i;
-	uint8_t *ptr, op;
-
-	/* Scan the program once to identify all the jump targets,
-	 * so we can print the labels when we encounter them. */
-	for (i = 0; i < prog->p.size; i++) {
-		ptr = &prog->p.data[i];
-		op = *ptr;
-		if (is_jump(op))
-			set_jump_target(ptr[1]);
-		if (op == JUMP_BATTERY)
-			set_jump_target(ptr[2]);
-		i += num_operands[op];
-	}
-
-	/* Now disassemble */
-	for (i = 0; i < prog->p.size; i++) {
-		ptr = &prog->p.data[i];
-		i += print_op(fp, i, *ptr, ptr + 1);
-	}
-
-	/* Finally, make sure the program doesn't jump to any location other
-	 * than a valid instruction */
-	for (i = 0; i < EC_LB_PROG_LEN; i++)
-		if (is_jump_target[i] && !is_instruction[i]) {
-			Warning("program jumps to 0x%02x, "
-				"which is not a valid instruction\n", i);
-		}
-}
-
-/* We'll split each line into an array of these. */
-struct parse_s {
-	char *word;
-	int is_num;
-	uint32_t val;
-};
-
-/* Fills in struct, returns number of words found. Note that pointers are only
- * copied. The strings they point to are not duplicated.  */
-static int split_line(char *buf, const char *delim, struct parse_s *elt,
-		      int max)
-{
-	char *w, *ptr, *buf_savetok;
-	int i;
-	char *e = 0;
-
-	memset(elt, 0, max * sizeof(*elt));
-
-	for (ptr = buf, i = 0;
-	     i < max && (w = strtok_r(ptr, delim, &buf_savetok)) != 0;
-	     ptr = 0, i++) {
-		elt[i].word = w;
-		elt[i].val = (uint32_t)strtoull(w, &e, 0);
-		if (!e || !*e)
-			elt[i].is_num = 1;
-
-	}
-
-	return i;
-}
-
-/* Decode led set. Return 0 if bogus, 1 if okay. */
-static int is_led_set(char *buf, uint8_t *valp)
-{
-	uint8_t led = 0;
-	unsigned long int next_led;
-	char *ptr;
-
-	if (!buf)
-		return 0;
-
-	if (*buf != '{')
-		return 0;
-
-	buf++;
-	for (;;) {
-		next_led = strtoull(buf, &ptr, 0);
-		if (buf == ptr) {
-			if (buf[0] == '}' && buf[1] == 0) {
-				*valp = led;
-				return 1;
-			} else
-				return 0;
-		}
-
-		if (next_led >= NUM_LEDS)
-			return 0;
-
-		led |= 1 << next_led;
-
-		buf = ptr;
-		if (*buf == ',')
-			buf++;
-	}
-}
-
-/* Decode color arg based on expected control param sections.
- * Return 0 if bogus, 1 if okay.
- */
-static int is_color_arg(char *buf, int expected, uint32_t *valp)
-{
-	struct parse_s token[MAX_WORDS];
-	uint8_t led, control, color;
-	int i;
-
-	if (!buf)
-		return 0;
-
-	/* There should be three terms, separated with '.' */
-	i = split_line(buf, ".", token, MAX_WORDS);
-	if (i != expected)
-		return 0;
-
-	if (!is_led_set(token[0].word, &led)) {
-		Error("Invalid LED set \"%s\"\n", token[0].word);
-		return 0;
-	}
-
-	for (i = 0; i < LB_CONT_MAX; i++)
-		if (!strcmp(token[1].word, control_sym[i])) {
-			control = i;
-			break;
-		}
-	if (i >= LB_CONT_MAX)
-		return 0;
-
-	if (expected == 3) {
-		for (i = 0; i < ARRAY_SIZE(color_sym); i++)
-			if (!strcmp(token[2].word, color_sym[i])) {
-				color = i;
-				break;
-			}
-		if (i >= ARRAY_SIZE(color_sym))
-			return 0;
-	} else
-		color = 0;
-
-
-	*valp = ((led & 0xF) << 4) | ((control & 0x3) << 2) | (color & 0x3);
-	return 1;
-}
-
-static void fixup_symbols(struct safe_lightbar_program *prog)
-{
-	int i, j;
-
-	for (i = 0; i < EC_LB_PROG_LEN; i++) {
-		if (reloc_label[i]) {
-			/* Looking for reloc label */
-			for (j = 0; j < EC_LB_PROG_LEN; j++) {
-				if (label[j] && !strcmp(label[j],
-							reloc_label[i])) {
-					prog->p.data[i] = j;
-					break;
-				}
-			}
-			if (j >= EC_LB_PROG_LEN)
-				Error("Can't find label %s\n", reloc_label[i]);
-		}
-	}
-}
-
-
-static void compile(FILE *fp, struct safe_lightbar_program *prog)
-{
-	char buf[128];
-	struct parse_s token[MAX_WORDS];
-	char *s;
-	int line = 0, chopping = 0;
-	uint8_t addr = 0;
-	int opcode;
-	int wnum, wordcnt;
-	int i;
-
-	while (fgets(buf, sizeof(buf), fp)) {
-
-		/* We truncate lines that are too long */
-		s = strchr(buf, '\n');
-		if (chopping) {
-			if (s)
-				chopping = 0;
-			continue;
-		}
-
-		/* Got something to look at */
-		line++;
-		if (!s) {
-			chopping = 1;
-			Warning("truncating line %d\n", line);
-		}
-
-		/* Ignore comments */
-		s = strchr(buf, '#');
-		if (s)
-			*s = '\0';
-
-		wordcnt = split_line(buf, " \t\n", token, MAX_WORDS);
-		if (!wordcnt)
-			continue;
-
-		wnum = 0;
-
-		/* A label must be the first word, ends with a ':' (no spaces
-		 * before it), and doesn't start with a ':' */
-		s = strchr(token[0].word, ':');
-		if (s && s[1] == '\0' && s != token[0].word) {
-			*s = '\0';
-			label[addr] = strdup(token[0].word);
-			wnum++;
-		}
-
-		/* How about an opcode? */
-		for (opcode = 0; opcode < MAX_OPCODE; opcode++)
-			if (!strcasecmp(token[wnum].word, opcode_sym[opcode]))
-				break;
-
-		if (opcode >= MAX_OPCODE) {
-			Error("Unrecognized opcode \"%s\""
-			      " at line %d\n", token[wnum].word, line);
-			continue;
-		}
-
-		/* Do we even have a place to write this opcode? */
-		if (addr >= EC_LB_PROG_LEN) {
-			Error("out of program space at line %d\n", line);
-			break;
-		}
-
-		/* Got an opcode. Save it! */
-		prog->p.data[addr++] = opcode;
-		wnum++;
-
-		/* Now we need operands. */
-		switch (opcode) {
-		case JUMP:
-		case JUMP_IF_CHARGING:
-			/* a label */
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else
-				Error("Missing jump target at line %d\n", line);
-			break;
-		case JUMP_BATTERY:
-			/* two labels*/
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else {
-				Error("Missing first jump target "
-				      "at line %d\n", line);
-				break;
-			}
-			wnum++;
-			if (token[wnum].word)
-				reloc_label[addr++] = strdup(token[wnum].word);
-			else
-				Error("Missing second jump target "
-				      "at line %d\n", line);
-			break;
-
-		case SET_BRIGHTNESS:
-			/* one 8-bit arg */
-			if (token[wnum].is_num)
-				prog->p.data[addr++] = token[wnum].val;
-			else
-				Error("Missing/invalid arg at line %d\n", line);
-			break;
-
-		case SET_WAIT_DELAY:
-		case SET_RAMP_DELAY:
-			/* one 32-bit arg */
-			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					(token[wnum].val >> 24) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 16) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 8) & 0xff;
-				prog->p.data[addr++] =
-					token[wnum].val & 0xff;
-			} else {
-				Error("Missing/invalid arg at line %d\n", line);
-			}
-			break;
-
-		case SET_COLOR_SINGLE:
-			/* one magic word, then one more 8-bit arg */
-			i = is_color_arg(token[wnum].word, 3, &token[wnum].val);
-			if (!i) {
-				Error("Missing/invalid arg at line %d\n", line);
-				break;
-			}
-			/* save the magic number */
-			prog->p.data[addr++] = token[wnum++].val;
-			/* and the color immediate */
-			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					token[wnum++].val;
-			} else {
-				Error("Missing/Invalid arg "
-				      "at line %d\n", line);
-				break;
-			}
-			break;
-		case SET_COLOR_RGB:
-			/* one magic word, then three more 8-bit args */
-			i = is_color_arg(token[wnum].word, 2, &token[wnum].val);
-			if (!i) {
-				Error("Missing/invalid arg at line %d\n", line);
-				break;
-			}
-			/* save the magic number */
-			prog->p.data[addr++] = token[wnum++].val;
-			/* and the color immediates */
-			for (i = 0; i < 3; i++) {
-				if (token[wnum].is_num) {
-					prog->p.data[addr++] =
-						token[wnum++].val;
-				} else {
-					Error("Missing/Invalid arg "
-					      "at line %d\n", line);
-					break;
-				}
-			}
-			break;
-
-		default:
-			/* No args needed */
-			break;
-		}
-
-		/* Did we run past the end? */
-		if (addr > EC_LB_PROG_LEN) {
-			Error("out of program space at line %d\n", line);
-			break;
-		}
-	}
-	if (ferror(fp))
-		Error("problem while reading input: %s\n", strerror(errno));
-
-	if (!hit_errors)
-		fixup_symbols(prog);
-
-	if (!hit_errors)
-		prog->p.size = addr;
-
-	if (!prog->p.size)
-		Error("input file produced no output bytes\n");
-}
-
-int main(int argc, char *argv[])
-{
-	struct safe_lightbar_program safe_prog;
-	int opt_decode = 0;
-	int c;
-	int errorcnt = 0;
-	const char *infile, *outfile;
-	FILE *ifp, *ofp;
-
-	char *progname = strrchr(argv[0], '/');
-	if (progname)
-		progname++;
-	else
-		progname = argv[0];
-
-	opterr = 0;                     /* quiet, you */
-	while ((c = getopt(argc, argv, ":dv")) != -1) {
-		switch (c) {
-		case 'd':
-			opt_decode = 1;
-			break;
-		case 'v':
-			opt_verbose = 1;
-			break;
-
-		case '?':
-			fprintf(stderr, "%s: unrecognized switch: -%c\n",
-				progname, optopt);
-			errorcnt++;
-			break;
-		case ':':
-			fprintf(stderr, "%s: missing argument to -%c\n",
-				progname, optopt);
-			errorcnt++;
-			break;
-		default:
-			errorcnt++;
-			break;
-		}
-	}
-
-	if (errorcnt) {
-		fprintf(stderr, usage, progname);
-		exit(1);
-	}
-
-	if (argc - optind > 0) {
-		infile = argv[optind];
-		ifp = fopen(infile, "rb");
-		if (!ifp) {
-			fprintf(stderr,
-				"%s: Unable to open %s for reading: %s\n",
-				progname, infile, strerror(errno));
-			exit(1);
-		}
-	} else {
-		infile = "stdin";
-		ifp = stdin;
-	}
-
-	if (argc - optind > 1) {
-		outfile = argv[optind + 1];
-		ofp = fopen(outfile, "wb");
-		if (!ofp) {
-			fprintf(stderr,
-				"%s: Unable to open %s for writing: %s\n",
-				progname, outfile, strerror(errno));
-			exit(1);
-		}
-	} else {
-		outfile = "stdout";
-		ofp = stdout;
-	}
-
-	if (opt_decode) {
-		read_binary(ifp, &safe_prog);
-		fclose(ifp);
-		if (hit_errors)
-			return 1;
-		fprintf(ofp, "# %s\n", infile);
-		disassemble_prog(ofp, &safe_prog);
-		fclose(ofp);
-	} else {
-		memset(&safe_prog, 0, sizeof(safe_prog));
-		compile(ifp, &safe_prog);
-		fclose(ifp);
-		if (!hit_errors) {
-			if (1 != fwrite(safe_prog.p.data,
-					safe_prog.p.size, 1, ofp))
-				Error("%s: Unable to write to %s: %s\n",
-				      progname, outfile, strerror(errno));
-			else
-				fprintf(stderr, "0x%02x bytes written to %s\n",
-					safe_prog.p.size, outfile);
-		}
-		fclose(ofp);
-	}
-
-	return hit_errors;
-}
diff --git a/util/lbplay.c b/util/lbplay.c
deleted file mode 100644
index 9ab0564b74..0000000000
--- a/util/lbplay.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <strings.h>
-#include <sys/file.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#define LIGHTBAR "/sys/devices/virtual/chromeos/cros_ec/lightbar"
-
-int main(int argc, char **argv)
-{
-	int major, minor, fd_v;
-	int i, tries, fd_s, fd_l;
-	char buf[80];
-	int ret = 1;
-
-	/* Check version */
-	fd_v = open(LIGHTBAR "/version", O_RDONLY);
-	if (fd_v < 0) {
-		perror("can't open version file");
-		goto out;
-	}
-	ret = read(fd_v, buf, sizeof(buf) - 1);
-	if (ret <= 0) {
-		perror("can't read version");
-		close(fd_v);
-		goto out;
-	}
-	buf[ret] = '\0';
-	close(fd_v);
-
-	errno = 0;
-	/* Expect "MAJOR MINOR" */
-	if (2 != sscanf(buf, "%d %d", &major, &minor)) {
-		if (errno)
-			perror("can't parse version string");
-		else
-			fprintf(stderr, "can't parse version string\n");
-		goto out;
-	}
-	/* Pixel is "0 0". Minor change will be compatible, Major may not */
-	if (major != 0) {
-		fprintf(stderr, "Don't know how to handle version %d.%d\n",
-			major, minor);
-		goto out;
-	}
-
-	/* Take over lightbar sequencing. */
-	fd_s = open(LIGHTBAR "/sequence", O_RDWR | O_SYNC);
-	if (fd_s < 0) {
-		perror("can't open sequence control");
-		goto out;
-	}
-
-	/* NOTE: Cooperative locking only. Rude programs may not play nice. */
-	if (flock(fd_s, LOCK_EX | LOCK_NB) < 0) {
-		perror("can't lock sequence control");
-		goto out_close;
-	}
-
-	/*
-	 * If power events are changing the sequence our request to stop may
-	 * be missed, so try a few times before giving up.
-	 *
-	 * Note that every write to a control file should be prefaced with an
-	 * lseek() to the beginning. sysfs files don't work quite like normal
-	 * files.
-	 */
-	tries = 3;
-	while (1) {
-		lseek(fd_s, 0, SEEK_SET);
-		if (read(fd_s, buf, sizeof(buf)) <= 0) {
-			perror("can't read sequence control");
-			goto out_unlock;
-		}
-
-		if (!strncasecmp(buf, "stop", 4))
-			break;
-
-		if (!tries--) {
-			fprintf(stderr, "couldn't get EC to stop\n");
-			goto out_unlock;
-		}
-
-		lseek(fd_s, 0, SEEK_SET);
-		strcpy(buf, "stop");
-		if (write(fd_s, buf, strlen(buf) + 1) <= 0) {
-			perror("can't write sequence control");
-			goto out_unlock;
-		}
-	}
-
-	/* Turn the brightness all the way up */
-	fd_l = open(LIGHTBAR "/brightness", O_WRONLY | O_SYNC);
-	if (fd_l < 0) {
-		perror("can't open brightness control");
-		goto out_run;
-	}
-	strcpy(buf, "255");
-	if (write(fd_l, buf, strlen(buf) + 1) < 0) {
-		perror("can't write brightness control");
-		goto out_led;
-	}
-	close(fd_l);
-
-	/* Now let's drive the colors. */
-	fd_l = open(LIGHTBAR "/led_rgb", O_WRONLY | O_SYNC);
-	if (fd_l < 0) {
-		perror("can't open led control");
-		goto out_run;
-	}
-
-	/* Cycle through some colors. We can update multiple LEDs at once,
-	 * but there's a limit on how often we can send commands to the
-	 * lightbar. Going too fast will block, although buffering combined
-	 * with lseek() may just cause data to be lost. Read "/interval_msec"
-	 * to see what the limit is. The default is 50msec (20Hz).
-	 */
-	for (i = 0; i < 256; i += 4) {
-		sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d",
-			i, 0, 0,
-			0, 0, i,
-			255-i, 255, 0,
-			0, 255, 255-i);
-		lseek(fd_l, 0, SEEK_SET);
-		if (write(fd_l, buf, strlen(buf) + 1) < 0)
-			perror("write to led control");
-
-		usleep(100000);
-	}
-
-	/* all white */
-	strcpy(buf, "4 255 255 255");
-	lseek(fd_l, 0, SEEK_SET);
-	if (write(fd_l, buf, strlen(buf) + 1) < 0)
-		perror("write to led control");
-
-	usleep(400000);
-
-	/* Done. */
-	ret = 0;
-out_led:
-	close(fd_l);
-out_run:
-	/* Let EC drive lightbar again */
-	strcpy(buf, "run");
-	lseek(fd_s, 0, SEEK_SET);
-	if (write(fd_s, buf, strlen(buf) + 1) < 0)
-		perror("write to sequence control");
-out_unlock:
-	flock(fd_s, LOCK_UN);
-out_close:
-	close(fd_s);
-out:
-	return ret;
-}
diff --git a/util/linux_ec_commands_h_check.sh b/util/linux_ec_commands_h_check.sh
deleted file mode 100755
index 4c55faca0a..0000000000
--- a/util/linux_ec_commands_h_check.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set -e
-
-ec_commands_file_in="include/ec_commands.h"
-ec_commands_file_out="build/kernel/include/linux/mfd/cros_ec_commands.h"
-
-# Check if ec_commands.h has changed.
-echo ${PRESUBMIT_FILES} | grep -q "${ec_commands_file_in}" || exit 0
-
-if [ ! -f "${ec_commands_file_out}" ]; then
-  echo "A new cros_ec_commands.h must be generated."
-  echo 'Please run "make buildall" or "make build_cros_ec_commands"'.
-  exit 1
-fi
-
-if [ "${ec_commands_file_out}" -ot "${ec_commands_file_in}" ]; then
-  echo "cros_ec_commands.h is out of date."
-  echo 'Please run "make buildall" or "make build_cros_ec_commands"'.
-  exit 1
-fi
diff --git a/util/llvm-gcov.sh b/util/llvm-gcov.sh
deleted file mode 100755
index 7c1c97a7d5..0000000000
--- a/util/llvm-gcov.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-exec llvm-cov gcov "$@"
diff --git a/util/lock/android.c b/util/lock/android.c
deleted file mode 100644
index 8472b6db68..0000000000
--- a/util/lock/android.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#include <stdlib.h>
-
-#include "android.h"
-
-int in_android(void)
-{
-	if (getenv("ANDROID_ROOT"))
-		return 1;
-
-	return 0;
-}
-
-char *android_tmpdir_path(void)
-{
-	return getenv("TMPDIR");
-}
diff --git a/util/lock/android.h b/util/lock/android.h
deleted file mode 100644
index bb08486919..0000000000
--- a/util/lock/android.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef ANDROID_H__
-#define ANDROID_H__
-
-/*
- * in_android - Test to see if the underlying OS is Android
- *
- * returns boolean 1 to indicate true, 0 otherwise
- */
-extern int in_android(void);
-
-/**
- * Determine where temporary files go.
- *
- * @return A pointer to value of directory containing temporary files if
- *         successful, or NULL otherwise
- */
-extern char *android_tmpdir_path(void);
-
-#endif
diff --git a/util/lock/build.mk b/util/lock/build.mk
deleted file mode 100644
index 65a63ab9db..0000000000
--- a/util/lock/build.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Lock library
-#
-
-util-lock-objs=file_lock.o gec_lock.o
-util-lock-objs+=android.o
diff --git a/util/lock/file_lock.c b/util/lock/file_lock.c
deleted file mode 100644
index 36b420d287..0000000000
--- a/util/lock/file_lock.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2016, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- *
- * file_lock.c: Implementation for a binary semaphore using a file lock.
- *
- * Warning: This relies on flock() which is known to be broken on NFS.
- *
- * The file will remain persistent once the lock has been used. Unfortunately,
- * unlinking the file can introduce a race condition so we leave the file
- * in place.
- *
- * The current process's PID will be written to the file for debug purposes.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <sys/file.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#include "android.h"
-#include "ipc_lock.h"
-#include "locks.h"
-
-#define SLEEP_INTERVAL_MS	50
-
-static void msecs_to_timespec(int msecs, struct timespec *tmspec)
-{
-	tmspec->tv_sec = msecs / 1000;
-	tmspec->tv_nsec = (msecs % 1000) * 1000 * 1000;
-}
-
-static int lock_is_held(struct ipc_lock *lock)
-{
-	return lock->is_held;
-}
-
-static int test_dir(const char *path)
-{
-	struct stat s;
-
-	if (lstat(path, &s) < 0) {
-		fprintf(stderr, "Cannot stat %s.\n", path);
-		return -1;
-	}
-
-	if (!S_ISDIR(s.st_mode)) {
-		fprintf(stderr, "%s is not a directory.\n", path);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_open_or_create(struct ipc_lock *lock)
-{
-	char path[PATH_MAX];
-
-	if (in_android()) {
-		char *tmpdir;
-
-		tmpdir = android_tmpdir_path();
-		if (!tmpdir)
-			return -1;
-
-		if (snprintf(path, sizeof(path), "%s/%s",
-				tmpdir, lock->filename) < 0) {
-			return -1;
-		}
-	} else {
-		const char *dir = SYSTEM_LOCKFILE_DIR;
-		const char fallback[] = "/tmp";
-
-		if (test_dir(dir)) {
-			dir = fallback;
-			fprintf(stderr, "Trying fallback directory: %s\n", dir);
-			if (test_dir(dir))
-				return -1;
-		}
-
-		if (snprintf(path, sizeof(path),
-			"%s/%s", dir, lock->filename) < 0)
-			return -1;
-
-	}
-
-	lock->fd = open(path, O_RDWR | O_CREAT, 0600);
-	if (lock->fd < 0) {
-		fprintf(stderr, "Cannot open lockfile %s", path);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_get(struct ipc_lock *lock, int timeout_msecs)
-{
-	int msecs_remaining = timeout_msecs;
-	struct timespec sleep_interval, rem;
-	int ret = -1;
-
-	if (timeout_msecs == 0)
-		return flock(lock->fd, LOCK_EX | LOCK_NB);
-
-	msecs_to_timespec(SLEEP_INTERVAL_MS, &sleep_interval);
-
-	while ((ret = flock(lock->fd, LOCK_EX | LOCK_NB)) != 0) {
-		if (errno != EWOULDBLOCK) {
-			fprintf(stderr, "Error obtaining lock");
-			return -1;
-		}
-
-		if (msecs_remaining < SLEEP_INTERVAL_MS)
-			msecs_to_timespec(msecs_remaining, &sleep_interval);
-
-		while (nanosleep(&sleep_interval, &rem) != 0) {
-			if (errno == EINTR) {
-				sleep_interval = rem;
-				continue;
-			} else {
-				fprintf(stderr, "nanosleep() failed");
-				return ret;
-			}
-		}
-
-		if (timeout_msecs < 0)
-			continue;
-
-		msecs_remaining -= SLEEP_INTERVAL_MS;
-		if (msecs_remaining < 0)
-			break;
-	}
-
-	if (ret != 0) {
-		fprintf(stderr, "Timed out waiting for file lock.\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-static int file_lock_write_pid(struct ipc_lock *lock)
-{
-	ssize_t len;
-	/*
-         * PIDs are usually 5 digits, but we'll reserve enough room for
-	 * a value of 2^32 (10 digits) out of paranoia.
-         */
-	char pid_str[11];
-
-	if (ftruncate(lock->fd, 0) < 0) {
-		fprintf(stderr, "Cannot truncate lockfile");
-		return -1;
-	}
-
-	snprintf(pid_str, sizeof(pid_str), "%lu", (unsigned long)getpid());
-	len = write(lock->fd, pid_str, strlen(pid_str));
-	if (len < 0) {
-		fprintf(stderr, "Cannot write PID to lockfile");
-		return -1;
-	}
-
-	return 0;
-}
-
-static void file_lock_release(struct ipc_lock *lock)
-{
-	if (flock(lock->fd, LOCK_UN) < 0)
-		fprintf(stderr, "Cannot release lock");
-
-	if (close(lock->fd) < 0)
-		fprintf(stderr, "Cannot close lockfile");
-}
-
-/*
- * timeout <0 = no timeout (try forever)
- * timeout 0  = do not wait (return immediately)
- * timeout >0 = wait up to $timeout milliseconds
- *
- * returns 0 to indicate lock acquired
- * returns >0 to indicate lock was already held
- * returns <0 to indicate failed to acquire lock
- */
-int acquire_lock(struct ipc_lock *lock, int timeout_msecs)
-{
-	/* check if it is already held */
-	if (lock_is_held(lock))
-		return 1;
-
-	if (file_lock_open_or_create(lock))
-		return -1;
-
-	if (file_lock_get(lock, timeout_msecs)) {
-		lock->is_held = 0;
-		close(lock->fd);
-		return -1;
-	} else {
-		lock->is_held = 1;
-	}
-
-	/*
-	 * Write PID to lockfile for debug purposes. Failure to write to
-	 * the file should not be considered fatal. There might be something
-	 * bad happening with the filesystem, but the lock has already been
-	 * obtained and we may need our tools for diagnostics and repairs
-	 * so we should continue anyway.
-	 */
-	file_lock_write_pid(lock);
-	return 0;
-}
-
-/*
- * returns 0 if lock was released successfully
- * returns -1 if lock had not been held before the call
- */
-int release_lock(struct ipc_lock *lock)
-{
-	if (lock_is_held(lock)) {
-		file_lock_release(lock);
-		lock->is_held = 0;
-		return 0;
-	}
-
-	return -1;
-}
diff --git a/util/lock/gec_lock.c b/util/lock/gec_lock.c
deleted file mode 100644
index d354ea08f3..0000000000
--- a/util/lock/gec_lock.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gec_lock.h"
-#include "ipc_lock.h"
-#include "locks.h"
-
-static struct ipc_lock gec_lock = LOCKFILE_INIT(CROS_EC_LOCKFILE_NAME);
-
-int acquire_gec_lock(int timeout_secs)
-{
-	return acquire_lock(&gec_lock, timeout_secs * 1000);
-}
-
-int release_gec_lock(void)
-{
-	return release_lock(&gec_lock);
-}
diff --git a/util/lock/gec_lock.h b/util/lock/gec_lock.h
deleted file mode 100644
index 8480700ddd..0000000000
--- a/util/lock/gec_lock.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTIL_GEC_LOCK_H
-#define __UTIL_GEC_LOCK_H
-
-/*
- * acquire_gec_lock  -  acquire global lock
- *
- * returns 0 to indicate lock acquired
- * returns >0 to indicate lock was already held
- * returns <0 to indicate failed to acquire lock
- */
-extern int acquire_gec_lock(int timeout_secs);
-
-/*
- * release_gec_lock  -  release global lock
- *
- * returns 0 if lock was released successfully
- * returns -1 if lock had not been held before the call
- */
-extern int release_gec_lock(void);
-
-#endif /* __UTIL_GEC_LOCK_H */
diff --git a/util/lock/ipc_lock.h b/util/lock/ipc_lock.h
deleted file mode 100644
index 5d0d321af4..0000000000
--- a/util/lock/ipc_lock.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTIL_IPC_LOCK_H
-#define __UTIL_IPC_LOCK_H
-
-struct ipc_lock {
-	int is_held;	/* internal */
-	const char *filename;	/* provided by the developer */
-	int fd;		/* internal */
-};
-
-/* don't use C99 initializers here, so this can be used in C++ code */
-#define LOCKFILE_INIT(lockfile) \
-	{ \
-		0,		/* is_held */	\
-		lockfile,	/* filename */	\
-		-1,		/* fd */	\
-	}
-
-/*
- * acquire_lock: acquire a lock
- *
- * timeout <0 = no timeout (try forever)
- * timeout 0  = do not wait (return immediately)
- * timeout >0 = wait up to $timeout milliseconds (subject to kernel scheduling)
- *
- * return 0   = lock acquired
- * return >0  = lock was already held
- * return <0  = failed to acquire lock
- */
-extern int acquire_lock(struct ipc_lock *lock, int timeout_msecs);
-
-/*
- * release_lock: release a lock
- *
- * returns 0 if lock was released successfully
- * returns -1 if lock had not been held before the call
- */
-extern int release_lock(struct ipc_lock *lock);
-
-#endif /* __UTIL_IPC_LOCK_H */
diff --git a/util/lock/locks.h b/util/lock/locks.h
deleted file mode 100644
index 6875d91454..0000000000
--- a/util/lock/locks.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above
- *      copyright notice, this list of conditions and the following
- *      disclaimer in the documentation and/or other materials provided
- *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
- *      contributors may be used to endorse or promote products derived
- *      from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTIL_LOCKS_H
-#define __UTIL_LOCKS_H
-
-#define SYSTEM_LOCKFILE_DIR	"/run/lock"
-#define LOCKFILE_NAME		"firmware_utility_lock"
-#define CROS_EC_LOCKFILE_NAME	"cros_ec_lock"
-
-#endif /* __UTIL_LOCKS_H */
diff --git a/util/make_linux_ec_commands_h.sh b/util/make_linux_ec_commands_h.sh
deleted file mode 100755
index 4deeaeef32..0000000000
--- a/util/make_linux_ec_commands_h.sh
+++ /dev/null
@@ -1,81 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Generate a kernel include file from ec_commands.h.
-
-usage() {
-  cat << EOF
-Generate an ec_commands.h file suitable for upstreaming to kernel.org.
-Syntax:
-$0 source_ec_commands.h target_cros_ec_commands.h
-
-source_ec_commands.h: source file, usually include/ec_commands.h
-target_cros_ec_commands.h: target file that will be upstreamed.
-EOF
-}
-
-set -e
-
-in="$1"
-out="$2"
-
-if [ $# -ne 2 ]; then
-  usage
-  exit 1
-fi
-
-if [ ! -d "${CROS_WORKON_SRCROOT}" ]; then
-  printf "Not in Chrome OS chroot!\n\n"
-  usage
-  exit 0
-fi
-
-out_dir="$(dirname "${out}")"
-mkdir -p "${out_dir}"
-tmp="$(mktemp -p "${out_dir}" cros_ec_XXX.h)"
-cp "${in}" "${tmp}"
-
-cleanup() {
-  rm -f "${tmp}"*
-}
-
-trap cleanup EXIT
-
-# Replace license
-patch "${tmp}" << EOF
-@@ -1,6 +1,11 @@
--/* Copyright 2014 The Chromium OS Authors. All rights reserved.
-- * Use of this source code is governed by a BSD-style license that can be
-- * found in the LICENSE file.
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/*
-+ * Host communication command constants for ChromeOS EC
-+ *
-+ * Copyright (C) 2012 Google, Inc
-+ *
-+ * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
-+ * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h
-  */
- 
- /* Host communication command constants for Chrome EC */
-EOF
-
-# Change header guards
-sed -i "s/__CROS_EC_EC_COMMANDS_H/__CROS_EC_COMMANDS_H/" "${tmp}"
-
-# Convert UINT32_MAX into U32_MAX (and friends).
-sed -i "s/UINT\([0-9]\{1,2\}\)_MAX/U\1_MAX/" "${tmp}"
-sed -i "s/INT\([0-9]\{1,2\}\)_MAX/S\1_MAX/" "${tmp}"
-sed -i "s/INT\([0-9]\{1,2\}\)_MIN/S\1_MIN/" "${tmp}"
-
-# Remove non kernel code to prevent checkpatch warnings and simplify the .h.
-unifdef -x2 -m -UCONFIG_HOSTCMD_ALIGNED -U__ACPI__ -D__KERNEL__ -U__cplusplus \
-  -UCHROMIUM_EC "${tmp}"
-
-# Check kernel checkpatch passes.
-"${CROS_WORKON_SRCROOT}/src/repohooks/checkpatch.pl" -f "${tmp}"
-
-cp "${tmp}" "${out}"
diff --git a/util/misc_util.c b/util/misc_util.c
deleted file mode 100644
index 9813dc72b4..0000000000
--- a/util/misc_util.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ctype.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/utsname.h>
-
-#include "comm-host.h"
-#include "misc_util.h"
-
-int write_file(const char *filename, const char *buf, int size)
-{
-	FILE *f;
-	int i;
-
-	/* Write to file */
-	f = fopen(filename, "wb");
-	if (!f) {
-		perror("Error opening output file");
-		return -1;
-	}
-	i = fwrite(buf, 1, size, f);
-	fclose(f);
-	if (i != size) {
-		perror("Error writing to file");
-		return -1;
-	}
-
-	return 0;
-}
-
-char *read_file(const char *filename, int *size)
-{
-	FILE *f = fopen(filename, "rb");
-	char *buf;
-	int i;
-
-	if (!f) {
-		perror("Error opening input file");
-		return NULL;
-	}
-
-	fseek(f, 0, SEEK_END);
-	*size = ftell(f);
-	rewind(f);
-	if ((*size > 0x100000) || (*size < 0)) {
-		if (*size < 0)
-			perror("ftell failed");
-		else
-			fprintf(stderr, "File seems unreasonably large\n");
-		fclose(f);
-		return NULL;
-	}
-
-	buf = (char *)malloc(*size);
-	if (!buf) {
-		fprintf(stderr, "Unable to allocate buffer.\n");
-		fclose(f);
-		return NULL;
-	}
-
-	printf("Reading %d bytes from %s...\n", *size, filename);
-	i = fread(buf, 1, *size, f);
-	fclose(f);
-	if (i != *size) {
-		perror("Error reading file");
-		free(buf);
-		return NULL;
-	}
-
-	return buf;
-}
-
-int is_string_printable(const char *buf)
-{
-	while (*buf) {
-		if (!isprint(*buf))
-			return 0;
-		buf++;
-	}
-
-	return 1;
-}
-
-/**
- * Get the versions of the command supported by the EC.
- *
- * @param cmd		Command
- * @param pmask		Destination for version mask; will be set to 0 on
- *			error.
- * @return 0 if success, <0 if error
- */
-int ec_get_cmd_versions(int cmd, uint32_t *pmask)
-{
-	struct ec_params_get_cmd_versions_v1 pver_v1;
-	struct ec_params_get_cmd_versions pver;
-	struct ec_response_get_cmd_versions rver;
-	int rv;
-
-	*pmask = 0;
-
-	pver_v1.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 1, &pver_v1, sizeof(pver_v1),
-			&rver, sizeof(rver));
-
-	if (rv < 0) {
-		pver.cmd = cmd;
-		rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &pver, sizeof(pver),
-				&rver, sizeof(rver));
-	}
-
-	if (rv < 0)
-		return rv;
-
-	*pmask = rver.version_mask;
-	return 0;
-}
-
-/**
- * Return non-zero if the EC supports the command and version
- *
- * @param cmd		Command to check
- * @param ver		Version to check
- * @return non-zero if command version supported; 0 if not.
- */
-int ec_cmd_version_supported(int cmd, int ver)
-{
-	uint32_t mask = 0;
-
-	if (ec_get_cmd_versions(cmd, &mask))
-		return 0;
-
-	return (mask & EC_VER_MASK(ver)) ? 1 : 0;
-}
-
-/**
- * Return 1 is the current kernel version is greater or equal to
- * <major>.<minor>.<sublevel>
- */
-int kernel_version_ge(int major, int minor, int sublevel)
-{
-	struct utsname uts;
-	int atoms, kmajor, kminor, ksublevel;
-
-	if (uname(&uts) < 0)
-		return -1;
-	atoms = sscanf(uts.release, "%d.%d.%d", &kmajor, &kminor, &ksublevel);
-	if (atoms < 1)
-		return -1;
-
-	if (kmajor > major)
-		return 1;
-	if (kmajor < major)
-		return 0;
-
-	/* kmajor == major */
-	if (atoms < 2)
-		return 0 == minor && 0 == sublevel;
-	if (kminor > minor)
-		return 1;
-	if (kminor < minor)
-		return 0;
-
-	/* kminor == minor */
-	if (atoms < 3)
-		return 0 == sublevel;
-
-	return ksublevel >= sublevel;
-}
-
diff --git a/util/misc_util.h b/util/misc_util.h
deleted file mode 100644
index 240d735556..0000000000
--- a/util/misc_util.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __UTIL_MISC_UTIL_H
-#define __UTIL_MISC_UTIL_H
-
-/* Don't use a macro where an inline will do... */
-static inline int MIN(int a, int b) { return a < b ? a : b; }
-static inline int MAX(int a, int b) { return a > b ? a : b; }
-
-/**
- * Write a buffer to the file.
- *
- * @param filename	Target filename
- * @param buf		Buffer to write
- * @param size		Size of buffer in bytes
- * @return non-zero if error
- */
-int write_file(const char *filename, const char *buf, int size);
-
-/**
- * Read a file into a newly-allocated buffer.
- *
- * @param filename	Source filename
- * @param size		Size of data in bytes will be stored here on success.
- * @return A newly allocated buffer with the data, which must be freed with
- *         free() by the caller, or NULL if error.
- */
-char *read_file(const char *filename, int *size);
-
-/**
- * Check if a string contains only printable characters.
- *
- * @param buf		Null-terminated string to check
- * @return non-zero if buf contains only printable characters; zero if not.
- */
-int is_string_printable(const char *buf);
-
-/**
- * Get the versions of the command supported by the EC.
- *
- * @param cmd		Command
- * @param pmask		Destination for version mask; will be set to 0 on
- *			error.
- * @return 0 if success, <0 if error
- */
-int ec_get_cmd_versions(int cmd, uint32_t *pmask);
-
-/**
- * Return non-zero if the EC supports the command and version
- *
- * @param cmd		Command to check
- * @param ver		Version to check
- * @return non-zero if command version supported; 0 if not.
- */
-int ec_cmd_version_supported(int cmd, int ver);
-
-/**
- * Return 1 is the current kernel version is greater or equal to
- * <major>.<minor>.<sublevel>
- */
-int kernel_version_ge(int major, int minor, int sublevel);
-#endif
diff --git a/util/openocd/lm4_chip.cfg b/util/openocd/lm4_chip.cfg
deleted file mode 100644
index 3dffa2dc66..0000000000
--- a/util/openocd/lm4_chip.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-
-ftdi_layout_init 0x0018 0x009b
-
-# open collector oe only
-ftdi_layout_signal nSRST -oe 0x0020
-
-reset_config trst_only
-
-source [find target/stellaris.cfg]
-source [find lm4x_cmds.tcl]
-
diff --git a/util/openocd/lm4x_cmds.tcl b/util/openocd/lm4x_cmds.tcl
deleted file mode 100644
index 59c2dbdeb6..0000000000
--- a/util/openocd/lm4x_cmds.tcl
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Blizzard LM4F chip
-
-# Program internal flash
-
-proc flash_lm4 {path offset} {
-	reset halt;
-	flash write_image erase $path $offset;
-	reset
-}
-
-proc flash_lm4_board {board} {
-	flash_lm4 ../../build/$board/ec.bin 0
-}
-
-proc flash_lm4_ro {board} {
-	flash_lm4 ../../build/$board/RO/ec.RO.flat 0
-}
-
-proc flash_lm4_rw {board} {
-	flash_lm4 ../../build/$board/RW/ec.RW.bin 131072
-}
-
-# Boards with CONFIG_FLASH_PSTATE_BANK have pstate following RO
-proc unprotect_pstate { } {
-	reset halt
-	flash erase_sector 0 126 127
-	reset
-}
-
-# Boot a software using internal RAM only
-
-proc ramboot_lm4 {path} {
-	reset halt
-	load_image $path 0x20000000 bin
-	reg 15 0x20000400
-	resume
-}
-
-proc ramboot_lm4_board {board} {
-	ramboot_lm4 ../../../build/$board/ec.RO.flat
-}
-
-proc flash_emerged_board {board} {
-	set firmware_image ../../../../../../chroot/build/$board/firmware/ec.bin
-
-	flash_lm4 $firmware_image 0
-}
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
deleted file mode 100644
index 0ab2b42888..0000000000
--- a/util/openocd/npcx.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nuvoton-m4 devices support both JTAG and SWD transports.
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME npcx_ec
-}
-
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
-} else {
-   set  _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x4BA00477
-}
-
-#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \
-		$_CHIPNAME.cpu -work-area-phys 0x200C0000 \
-		-work-area-size $_WORKAREASIZE
-
-# JTAG speed
-adapter_khz 100
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-# use sysresetreq to perform a system reset
-cortex_m reset_config sysresetreq
-
-#reset configuration
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event reset-start {
-	echo "NPCX Reset..."
-	halt
-	adapter_khz 1000
-}
diff --git a/util/openocd/npcx_chip.cfg b/util/openocd/npcx_chip.cfg
deleted file mode 100644
index ddd01df5a4..0000000000
--- a/util/openocd/npcx_chip.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-
-source [find npcx.cfg]
-source [find npcx_cmds.tcl]
-
-ftdi_layout_init 0x0018 0x009b
-
-# open collector oe only
-ftdi_layout_signal nSRST -oe 0x0020
-
-reset_config trst_only
-
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
deleted file mode 100644
index 759e897131..0000000000
--- a/util/openocd/npcx_cmds.tcl
+++ /dev/null
@@ -1,184 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for NPCX5M5G chip
-
-# Program spi flash
-source [find mem_helper.tcl]
-
-proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} {
-	set UPLOAD_FLAG 0x200C4000;
-	set UUT_TAG 0x200C3000;
-
-	echo "*** NPCX Reset and halt CPU first ***"
-	reset halt
-
-	# Clear whole Code RAM
-	mwb $cram_addr 0xFF $image_size
-	# Upload binary image to Code RAM
-	load_image $image_path $cram_addr
-
-	# Upload program spi image FW to lower 16KB Data RAM
-	load_image $spifw_image 0x200C3020
-
-	# Set sp to upper 16KB Data RAM
-	reg sp 0x200C8000
-	# Set spi offset address of uploaded image
-	reg r0 $image_offset
-	# Set spi program size of uploaded image
-	reg r1 $image_size
-	# Set pc to start of spi program function
-	reg pc 0x200C3021
-	# Clear upload flag
-	mww $UPLOAD_FLAG 0x0
-
-	# Clear UUT Tag
-	mww $UUT_TAG 0x0
-
-	echo "*** Program ...  ***"
-	# Start to program spi flash
-	resume
-
-	# Wait for any pending flash operations to complete
-	while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1000 }
-
-	if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} {
-		echo "*** Program Fail ***"
-	} else {
-		echo "*** Program Done ***"
-	}
-
-	# Halt CPU
-	halt
-}
-
-proc flash_npcx5m5g {image_path image_offset spifw_image} {
-	# 96 KB for RO & RW regions
-	set fw_size   0x18000
-	# Code RAM start address
-	set cram_addr 0x100A8000
-
-	echo "*** Start to program npcx5m5g with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx5m5g ***\r\n"
-}
-
-proc flash_npcx5m6g {image_path image_offset spifw_image} {
-	# 224 KB for RO & RW regions
-	set fw_size   0x38000
-	# Code RAM start address
-	set cram_addr 0x10088000
-
-	echo "*** Start to program npcx5m6g with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx5m6g ***\r\n"
-}
-
-proc flash_npcx7m6x {image_path image_offset spifw_image} {
-	# 192 KB for RO & RW regions
-	set fw_size   0x30000
-	# Code RAM start address
-	set cram_addr 0x10090000
-
-	echo "*** Start to program npcx7m6f/g/w with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx7m6f/g/w ***\r\n"
-}
-
-proc flash_npcx7m7x {image_path image_offset spifw_image} {
-	# 320 KB for RO & RW regions
-	set fw_size   0x50000
-	# Code RAM start address
-	set cram_addr 0x10070000
-
-	echo "*** Start to program npcx7m7f/g/w with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx7m7f/g/w ***\r\n"
-}
-
-proc flash_npcx_ro {chip_name image_dir image_offset} {
-	set MPU_RNR  0xE000ED98;
-	set MPU_RASR 0xE000EDA0;
-
-	# images path
-	set ro_image_path $image_dir/RO/ec.RO.flat
-	set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
-
-	# Halt CPU first
-	halt
-
-	# disable MPU for Data RAM
-	mww $MPU_RNR  0x1
-	mww $MPU_RASR 0x0
-
-	if {$chip_name == "npcx_5m5g_jtag"} {
-		# program RO region
-		flash_npcx5m5g $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_5m6g_jtag"} {
-		# program RO region
-		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m6x_jtag"} {
-		# program RO region
-		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m7x_jtag"} {
-		# program RO region
-		flash_npcx7m7x $ro_image_path $image_offset $spifw_image
-	} else {
-		echo $chip_name "no supported."
-	}
-}
-
-proc flash_npcx_all {chip_name image_dir image_offset} {
-	set MPU_RNR  0xE000ED98;
-	set MPU_RASR 0xE000EDA0;
-
-	# images path
-	set ro_image_path $image_dir/RO/ec.RO.flat
-	set rw_image_path $image_dir/RW/ec.RW.bin
-	set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
-
-	# Halt CPU first
-	halt
-
-	# disable MPU for Data RAM
-	mww $MPU_RNR  0x1
-	mww $MPU_RASR 0x0
-
-	if {$chip_name == "npcx_5m5g_jtag"} {
-		# RW images offset - 128 KB
-		set rw_image_offset  [expr ($image_offset + 0x20000)]
-		# program RO region
-		flash_npcx5m5g $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx5m5g $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_5m6g_jtag"} {
-		# RW images offset - 256 KB
-		set rw_image_offset  [expr ($image_offset + 0x40000)]
-		# program RO region
-		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx5m6g $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m6x_jtag"} {
-		# RW images offset - 256 KB
-		set rw_image_offset  [expr ($image_offset + 0x40000)]
-		# program RO region
-		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx7m6x $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m7x_jtag"} {
-		# RW images offset - 512 KB
-		set rw_image_offset  [expr ($image_offset + 0x80000)]
-		# program RO region
-		flash_npcx7m7x $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx7m7x $rw_image_path $rw_image_offset $spifw_image
-	} else {
-		echo $chip_name "no supported."
-	}
-}
-
-proc reset_halt_cpu { } {
-	echo "*** NPCX Reset and halt CPU first ***"
-	reset halt
-}
diff --git a/util/openocd/nrf51_chip.cfg b/util/openocd/nrf51_chip.cfg
deleted file mode 100644
index f0e78897d6..0000000000
--- a/util/openocd/nrf51_chip.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-
-#nRF51 uses SWD
-transport select swd
-# Since nTRST is repurposed, we need a different layout_init setting
-ftdi_layout_init 0x0008 0x009b
-
-ftdi_layout_signal SWDIO_OE -nalias nTRST
-ftdi_layout_signal SWD_EN -alias TMS
-
-#Disable fast flashing, it only works with ST-Link and CMSIS-DAP
-set WORKAREASIZE 0
-source [find target/nrf51.cfg]
-source [find nrf51_cmds.tcl]
-
diff --git a/util/openocd/nrf51_cmds.tcl b/util/openocd/nrf51_cmds.tcl
deleted file mode 100644
index 711b27574d..0000000000
--- a/util/openocd/nrf51_cmds.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Nordic nRF51 chip
-
-proc flash_nrf51 {path offset} {
-	reset halt;
-	program $path $offset;
-}
-
-proc unprotect_nrf51 { } {
-	reset halt;
-	nrf51 mass_erase;
-}
-
-# enable reset by writing 1 to the RESET register
-# This will disconnect the debugger with the following message:
-# Polling target nrf51.cpu failed, trying to reexamine
-proc exit_debug_mode_nrf51 { } {
-	mww 0x40000544 1;
-}
diff --git a/util/openocd/servo.cfg b/util/openocd/servo.cfg
deleted file mode 100644
index 8331a9bc08..0000000000
--- a/util/openocd/servo.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-telnet_port 4444
-gdb_port 3333
-gdb_memory_map enable
-gdb_flash_program enable
-
-interface ftdi
-# VID/PID for servo v2, servo v3
-ftdi_vid_pid 0x18d1 0x5002 0x18d1 0x5004 0x18d1 0x500d
-# Only initialize Port A
-ftdi_channel 0
-
-# unbuffered connection data == oe
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-
diff --git a/util/powerd_lock.c b/util/powerd_lock.c
deleted file mode 100644
index df34d03c6c..0000000000
--- a/util/powerd_lock.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is ported from the flashrom project.
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- * powerd_lock.c: power management routines
- */
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "powerd_lock.h"
-
-/*
- * Path to a file containing flashrom's PID. While present, powerd avoids
- * suspending or shutting down the system.
- */
-static const char lock_file_path[] =
-	"/run/lock/power_override/battery_tool.lock";
-
-int disable_power_management()
-{
-	FILE *lock_file;
-	int rc = 0;
-	lock_file = fopen(lock_file_path, "w");
-	if (!lock_file)
-		return POWERD_CREATE_LOCK_FILE_ERROR;
-
-	if (fprintf(lock_file, "%ld", (long)getpid()) < 0)
-		rc = POWERD_WRITE_LOCK_FILE_ERROR;
-
-	if (fclose(lock_file) != 0)
-		rc |= POWERD_CLOSE_LOCK_FILE_ERROR;
-	return rc;
-}
-
-int restore_power_management()
-{
-	int result = 0;
-	result = unlink(lock_file_path);
-	if (result != 0 && errno != ENOENT)
-		return POWERD_DELETE_LOCK_FILE_ERROR;
-	return 0;
-}
diff --git a/util/powerd_lock.h b/util/powerd_lock.h
deleted file mode 100644
index 86be184a19..0000000000
--- a/util/powerd_lock.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is ported from the flashrom project.
- *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- * powerd_lock.h: header file for power management routines
- */
-
-#ifndef __UTIL_POWERD_LOCK_H
-#define __UTIL_POWERD_LOCK_H 1
-
-enum POWERD_ERROR_CODE {
-	POWERD_OK = 0,
-	POWERD_CREATE_LOCK_FILE_ERROR = 0x1,
-	POWERD_WRITE_LOCK_FILE_ERROR  = 0x2,
-	POWERD_CLOSE_LOCK_FILE_ERROR  = 0x4,
-	POWERD_DELETE_LOCK_FILE_ERROR = 0x8
-};
-
-/* Disable power management. */
-int disable_power_management(void);
-
-/* Re-enable power management. */
-int restore_power_management(void);
-
-#endif	/* __UTIL_POWERD_LOCK_H */
diff --git a/util/presubmit_check.sh b/util/presubmit_check.sh
deleted file mode 100755
index 7d46f38a0f..0000000000
--- a/util/presubmit_check.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Verify there is no CPRINTS("....\n", ...) statements added to the code.
-upstream_branch="$(git rev-parse --abbrev-ref --symbolic-full-name @{u} \
-    2>/dev/null)"
-if [[ -z ${upstream_branch} ]]; then
-  echo "Current branch does not have an upstream branch" >&2
-  exit 1
-fi
-# This will print the offending CPRINTS invocations, if any, and the names of
-# the files they are in.
-if git diff --no-ext-diff "${upstream_branch}" HEAD |
-    grep -e '^+\(.*CPRINTS(.*\\n"\|++\)' |
-    grep CPRINTS -B1 >&2 ; then
-  echo "error: CPRINTS strings should not include newline characters" >&2
-  exit 1
-fi
-
-# Directories that need to be tested by separate unit tests.
-unittest_dirs="util/ec3po/ extra/stack_analyzer/"
-
-for dir in $unittest_dirs; do
-    dir_files=$(echo "${PRESUBMIT_FILES}" | grep "${dir}")
-    if [[ -z "${dir_files}" ]]; then
-        continue
-    fi
-
-    if [[ ! -e "${dir}/.tests-passed" ]]; then
-        echo "Unit tests have not passed.  Please run \"${dir}run_tests.sh\"."
-        exit 1
-    fi
-
-    changed_files=$(find ${dir_files} -newer "${dir}/.tests-passed")
-    if [[ -n "${changed_files}" ]] && [[ -n "${dir_files}" ]]; then
-        echo "Files have changed since last time unit tests passed:"
-        echo "${changed_files}" | sed -e 's/^/  /'
-        echo "Please run \"${dir}run_tests.sh\"."
-        exit 1
-    fi
-done
diff --git a/util/run_ects.py b/util/run_ects.py
deleted file mode 100644
index 9178328e5f..0000000000
--- a/util/run_ects.py
+++ /dev/null
@@ -1,96 +0,0 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""Run all eCTS tests and publish results."""
-
-
-import argparse
-import logging
-import os
-import subprocess
-import sys
-
-# List of tests to run.
-TESTS = ['meta', 'gpio', 'hook', 'i2c', 'interrupt', 'mutex', 'task', 'timer']
-
-
-class CtsRunner(object):
-  """Class running eCTS tests."""
-
-  def __init__(self, ec_dir, dryrun):
-    self.ec_dir = ec_dir
-    self.cts_py = []
-    if dryrun:
-      self.cts_py += ['echo']
-    self.cts_py += [os.path.join(ec_dir, 'cts/cts.py')]
-
-  def run_cmd(self, cmd):
-    try:
-      rc = subprocess.call(cmd)
-      if rc != 0:
-        return False
-    except OSError:
-      return False
-    return True
-
-  def run_test(self, test):
-    cmd = self.cts_py + ['-m', test]
-    self.run_cmd(cmd)
-
-  def run(self, tests):
-    for test in tests:
-      logging.info('Running', test, 'test.')
-      self.run_test(test)
-
-  def sync(self):
-    logging.info('Syncing tree...')
-    os.chdir(self.ec_dir)
-    cmd = ['repo', 'sync', '.']
-    return self.run_cmd(cmd)
-
-  def upload(self):
-    logging.info('Uploading results...')
-
-
-def main():
-  if not os.path.exists('/etc/cros_chroot_version'):
-    logging.error('This script has to run inside chroot.')
-    sys.exit(-1)
-
-  ec_dir = os.path.realpath(os.path.dirname(__file__) + '/..')
-
-  parser = argparse.ArgumentParser(description='Run eCTS and report results.')
-  parser.add_argument('-d',
-                      '--dryrun',
-                      action='store_true',
-                      help='Echo commands to be executed without running them.')
-  parser.add_argument('-s',
-                      '--sync',
-                      action='store_true',
-                      help='Sync tree before running tests.')
-  parser.add_argument('-u',
-                      '--upload',
-                      action='store_true',
-                      help='Upload test results.')
-  args = parser.parse_args()
-
-  runner = CtsRunner(ec_dir, args.dryrun)
-
-  if args.sync:
-    if not runner.sync():
-      logging.error('Failed to sync.')
-      sys.exit(-1)
-
-  runner.run(TESTS)
-
-  if args.upload:
-    runner.upload()
-
-
-if __name__ == '__main__':
-  main()
diff --git a/util/run_host_test b/util/run_host_test
deleted file mode 100755
index 15013d91b6..0000000000
--- a/util/run_host_test
+++ /dev/null
@@ -1,129 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Wrapper that runs a host test. Handles timeout and stopping the emulator."""
-
-import argparse
-import enum
-import io
-import os
-import pathlib
-import select
-import subprocess
-import sys
-import time
-
-
-class TestResult(enum.Enum):
-  """An Enum representing the result of running a test."""
-  SUCCESS = 0
-  FAIL = 1
-  TIMEOUT = 2
-  UNEXPECTED_TERMINATION = 3
-
-  @property
-  def reason(self):
-    return {
-        TestResult.SUCCESS: 'passed',
-        TestResult.FAIL: 'failed',
-        TestResult.TIMEOUT: 'timed out',
-        TestResult.UNEXPECTED_TERMINATION: 'terminated unexpectedly',
-    }[self]
-
-
-def run_test(path, timeout=10):
-  start_time = time.monotonic()
-  env = dict(os.environ)
-  env['ASAN_OPTIONS'] = 'log_path=stderr'
-
-  proc = subprocess.Popen(
-      [path],
-      bufsize=0,
-      stdin=subprocess.PIPE,
-      stdout=subprocess.PIPE,
-      env=env,
-      encoding='utf-8',
-      errors='replace',
-  )
-
-  # Put the output pipe in non-blocking mode. We will then select(2)
-  # on the pipe to know when we have bytes to process.
-  os.set_blocking(proc.stdout.fileno(), False)
-
-  try:
-    output_buffer = io.StringIO()
-    while True:
-      select_timeout = timeout - (time.monotonic() - start_time)
-      if select_timeout <= 0:
-        return TestResult.TIMEOUT, output_buffer.getvalue()
-
-      readable, _, _ = select.select([proc.stdout], [], [], select_timeout)
-
-      if not readable:
-        # Indicates that select(2) timed out.
-        return TestResult.TIMEOUT, output_buffer.getvalue()
-
-      output_buffer.write(proc.stdout.read())
-      output_log = output_buffer.getvalue()
-
-      if 'Pass!' in output_log:
-        return TestResult.SUCCESS, output_log
-      if 'Fail!' in output_log:
-        return TestResult.FAIL, output_log
-      if proc.poll():
-        return TestResult.UNEXPECTED_TERMINATION, output_log
-  finally:
-    # Check if the process has exited. If not, send it a SIGTERM, wait for it
-    # to exit, and if it times out, kill the process directly.
-    if not proc.poll():
-      try:
-        proc.terminate()
-        proc.wait(timeout)
-      except subprocess.TimeoutExpired:
-        proc.kill()
-
-
-def parse_options(argv):
-  parser = argparse.ArgumentParser()
-  parser.add_argument('-t', '--timeout', type=float, default=60,
-                      help='Timeout to kill test after.')
-  parser.add_argument('--coverage', action='store_const', const='coverage',
-                      default='host', dest='test_target',
-                      help='Flag if this is a code coverage test.')
-  parser.add_argument('--verbose', '-v', action='store_true',
-                      help='Dump emulator output always, even if successful.')
-  parser.add_argument('test_name', type=str)
-  return parser.parse_args(argv)
-
-
-def main(argv):
-  opts = parse_options(argv)
-
-  # Tests will be located in build/host, unless the --coverage flag was
-  # provided, in which case they will be in build/coverage.
-  exec_path = pathlib.Path('build', opts.test_target, opts.test_name,
-                           f'{opts.test_name}.exe')
-  if not exec_path.is_file():
-    print(f'No test named {opts.test_name} exists!')
-    return 1
-
-  start_time = time.monotonic()
-  result, output = run_test(exec_path, timeout=opts.timeout)
-  elapsed_time = time.monotonic() - start_time
-
-  print('{} {}! ({:.3f} seconds)'.format(
-      opts.test_name, result.reason, elapsed_time),
-        file=sys.stderr)
-
-  if result is not TestResult.SUCCESS or opts.verbose:
-    print('====== Emulator output ======', file=sys.stderr)
-    print(output, file=sys.stderr)
-    print('=============================', file=sys.stderr)
-  return result.value
-
-
-if __name__ == '__main__':
-  sys.exit(main(sys.argv[1:]))
diff --git a/util/stm32mon.c b/util/stm32mon.c
deleted file mode 100644
index 7be802b1ed..0000000000
--- a/util/stm32mon.c
+++ /dev/null
@@ -1,1758 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * STM32 SoC system monitor interface tool
- * For Serial, implement protocol v2.0 as defined in:
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
- * document/application_note/CD00264342.pdf
- *
- * For i2C, implement protocol v1.0 as defined in:
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/\
- * document/application_note/DM00072315.pdf
- *
- * For SPI, implement protocol v1.1 as defined in:
- * https://www.st.com/resource/en/application_note/dm00081379.pdf
- */
-
-/* use cfmakeraw() */
-#define _DEFAULT_SOURCE /* Newer glibc */
-#define _BSD_SOURCE     /* Older glibc */
-
-#include <arpa/inet.h>
-#include <compile_time_macros.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <linux/i2c-dev.h>
-#include <linux/spi/spidev.h>
-#include <termios.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "ec_version.h"
-
-#define KBYTES_TO_BYTES		1024
-
-/*
- * Some Ubuntu versions do not export SPI_IOC_WR_MODE32 even though
- * the kernel shipped on those supports it.
- */
-#ifndef SPI_IOC_WR_MODE32
-#define SPI_IOC_WR_MODE32		_IOW(SPI_IOC_MAGIC, 5, __u32)
-#endif
-
-/* Monitor command set */
-#define CMD_INIT 0x7f    /* Starts the monitor */
-
-#define CMD_GETCMD   0x00 /* Gets the allowed commands */
-#define CMD_GETVER   0x01 /* Gets the bootloader version */
-#define CMD_GETID    0x02 /* Gets the Chip ID */
-#define CMD_READMEM  0x11 /* Reads memory */
-#define CMD_GO       0x21 /* Jumps to user code */
-#define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */
-#define CMD_ERASE    0x43 /* Erases n pages of Flash memory */
-#define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */
-#define CMD_NO_STRETCH_ERASE 0x45 /* Erases while sending busy frame */
-#define CMD_WP       0x63 /* Enables write protect */
-#define CMD_WU       0x73 /* Disables write protect */
-#define CMD_RP       0x82 /* Enables the read protection */
-#define CMD_RU       0x92 /* Disables the read protection */
-
-#define CMD_LOOKUP_ENTRY(COMMAND) {CMD_##COMMAND, #COMMAND}
-const struct {
-	const uint8_t cmd;
-	const char *name;
-} cmd_lookup_table[] = {
-	CMD_LOOKUP_ENTRY(INIT),
-	CMD_LOOKUP_ENTRY(GETCMD),
-	CMD_LOOKUP_ENTRY(GETVER),
-	CMD_LOOKUP_ENTRY(GETID),
-	CMD_LOOKUP_ENTRY(READMEM),
-	CMD_LOOKUP_ENTRY(GO),
-	CMD_LOOKUP_ENTRY(WRITEMEM),
-	CMD_LOOKUP_ENTRY(ERASE),
-	CMD_LOOKUP_ENTRY(EXTERASE),
-	CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE),
-	CMD_LOOKUP_ENTRY(WP),
-	CMD_LOOKUP_ENTRY(WU),
-	CMD_LOOKUP_ENTRY(RP),
-	CMD_LOOKUP_ENTRY(RU),
-};
-
-const char *cmd_lookup_name(uint8_t cmd)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(cmd_lookup_table); i++) {
-		if (cmd_lookup_table[i].cmd == cmd)
-			return cmd_lookup_table[i].name;
-	}
-
-	return NULL;
-}
-
-#define RESP_NACK        0x1f
-#define RESP_ACK         0x79 /* 0b 0111 1001 */
-#define RESP_BUSY        0x76
-#define RESP_DAMAGED_ACK 0xBC /* 0b 1011 1100, 1 bit shifted REST_ACK */
-
-/* SPI Start of Frame */
-#define SOF          0x5A
-
-/* Extended erase special parameters */
-#define ERASE_ALL    0xffff
-#define ERASE_BANK1  0xfffe
-#define ERASE_BANK2  0xfffd
-
-/* Upper bound of rebooting the monitor */
-#define MAX_DELAY_REBOOT 100000 /* us */
-
-/* Standard addresses common across various ST chips */
-#define STM32_MAIN_MEMORY_ADDR		0x08000000
-#define STM32_SYSTEM_MEMORY_ADDR	0x1FFF0000
-
-#define STM32_UNIQUE_ID_SIZE_BYTES	12
-
-/*
- * Device electronic signature contains factory-programmed identification
- * and calibration data to automatically match the characteristics of the
- * microcontroller.
- */
-struct stm32_device_signature {
-	/*
-	 * Address of the Unique Device ID register. This register contains a
-	 * 96-bit value that is unique across all chips.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t unique_device_id_addr;
-	/*
-	 * Address of the Flash Size register. This 16-bit register contains the
-	 * flash size in KB.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t flash_size_addr;
-	/*
-	 * Address of the Package Data register. This 16-bit register contains a
-	 * value that differentiates between package types of a given chip.
-	 * Zero means ignore/unknown.
-	 */
-	uint32_t package_data_addr;
-};
-
-struct memory_info {
-	/* Zero means ignore/unknown/not-applicable */
-	uint32_t addr;
-	/* If addr is non-zero
-	 * - zero here means value is dynamic and will be read from bootloader.
-	 * If addr is zero,
-	 * - zero here means ignore/unknown/not-applicable.
-	 */
-	uint32_t size_bytes;
-};
-
-struct memory_layout {
-	struct memory_info main_memory;
-	struct memory_info system_memory;
-	struct memory_info otp_area;
-	struct memory_info option_bytes;
-};
-
-/* known STM32 SoC parameters */
-struct stm32_def {
-	uint16_t   id;
-	const char *name;
-	uint32_t flash_size;
-	uint32_t page_size;
-	uint32_t cmds_len[2];
-	const struct memory_layout memory_layout;
-	const struct stm32_device_signature device_signature;
-} chip_defs[] = {
-	{0x416, "STM32L15xxB",   0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x429, "STM32L15xxB-A", 0x20000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x427, "STM32L15xxC",   0x40000,   256, {13, 13}, { { 0 } }, { 0 } },
-	{0x435, "STM32L44xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x420, "STM32F100xx",   0x20000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x410, "STM32F102R8",   0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x440, "STM32F05x",     0x10000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x444, "STM32F03x",     0x08000,  1024, {13, 13}, { { 0 } }, { 0 } },
-	{0x448, "STM32F07xB",    0x20000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x432, "STM32F37xx",    0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x442, "STM32F09x",     0x40000,  2048, {13, 13}, { { 0 } }, { 0 } },
-	{0x431, "STM32F411",     0x80000, 16384, {13, 19}, { { 0 } }, { 0 } },
-	{
-		.id =		0x441,
-		.name =		"STM32F412",
-		.flash_size =	0x100000,
-		.page_size =	16384,
-		.cmds_len =	{13, 19},
-		/*
-		 * STM32F412:
-		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
-		 * Section 3.3 Table 5 Flash module organization
-		 */
-		.memory_layout = {
-			.main_memory = {
-				.addr = STM32_MAIN_MEMORY_ADDR,
-				.size_bytes = 0, /* set by flash reg read */
-			},
-			.system_memory = {
-				.addr = STM32_SYSTEM_MEMORY_ADDR,
-				.size_bytes = 30 * KBYTES_TO_BYTES,
-			},
-			.otp_area = {
-				.addr = 0x1FFF7800,
-				.size_bytes = 528,
-			},
-			.option_bytes = {
-				.addr = 0x1FFFC000,
-				.size_bytes = 16,
-			}
-		},
-		/*
-		 * STM32F412:
-		 * See https://www.st.com/resource/en/reference_manual/dm00180369.pdf
-		 * Section 31 Device electronic signature
-		 */
-		.device_signature = {
-			.unique_device_id_addr =	0x1FFF7A10,
-			.flash_size_addr =		0x1FFF7A22,
-			/*
-			 * Out of range for bootloader on this chip, so we don't
-			 * attempt to read.
-			 */
-			.package_data_addr =		0, /* 0x1FFF7BF0 */
-		}
-	},
-	{0x450, "STM32H74x",    0x200000, 131768, {13, 19}, { { 0 } }, { 0 } },
-	{0x451, "STM32F76x",    0x200000, 32768, {13, 19}, { { 0 } }, { 0 } },
-	{
-		.id =		0x460,
-		.name =		"STM32G071xx",
-		.flash_size =	0x20000,
-		.page_size =	2048,
-		.cmds_len =	{13, 13},
-		/*
-		 * STM32G0x1:
-		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
-		 * Section 3.3.1 Table 6 Flash module organization
-		 */
-		.memory_layout = {
-			.main_memory = {
-				.addr = STM32_MAIN_MEMORY_ADDR,
-				.size_bytes = 0, /* set by flash reg read */
-			},
-			.system_memory = {
-				.addr = STM32_SYSTEM_MEMORY_ADDR,
-				.size_bytes = 28 * KBYTES_TO_BYTES,
-			},
-			.otp_area = {
-				.addr = 0x1FFF7000,
-				.size_bytes = 1024,
-			},
-			.option_bytes = {
-				.addr = 0x1FFF7800,
-				.size_bytes = 128,
-			}
-		},
-		/*
-		 * STM32G0x1:
-		 * See https://www.st.com/resource/en/reference_manual/dm00371828.pdf
-		 * Section 38 Device electronic signature
-		 */
-		.device_signature = {
-			.unique_device_id_addr =	0x1FFF7590,
-			.flash_size_addr =		0x1FFF75E0,
-			/*
-			 * Datasheet litst as same address as e.g. STM32F412,
-			 * hence declaring as zero as for that other chip.
-			 */
-			.package_data_addr =		0, /* 0x1FFF7500 */
-		}
-	},
-	{ 0 }
-};
-
-#define DEFAULT_CONNECT_RETRIES 5
-#define DEFAULT_TIMEOUT 4 /* seconds */
-#define EXT_ERASE_TIMEOUT 20 /* seconds */
-#define DEFAULT_BAUDRATE B38400
-#define PAGE_SIZE 256
-#define INVALID_I2C_ADAPTER -1
-#define MAX_ACK_RETRY_COUNT	(EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT)
-#define MAX_RETRY_COUNT		3
-
-enum interface_mode {
-	MODE_SERIAL,
-	MODE_I2C,
-	MODE_SPI,
-} mode = MODE_SERIAL;
-
-/* I2c address the EC is listening depends on the device:
- * stm32f07xxx: 0x76
- * stm32f411xx: 0x72
- */
-#define DEFAULT_I2C_SLAVE_ADDRESS 0x76
-
-/* store custom parameters */
-speed_t baudrate = DEFAULT_BAUDRATE;
-int connect_retries = DEFAULT_CONNECT_RETRIES;
-int i2c_adapter = INVALID_I2C_ADAPTER;
-const char *spi_adapter;
-int i2c_slave_address = DEFAULT_I2C_SLAVE_ADDRESS;
-uint8_t boot_loader_version;
-const char *serial_port = "/dev/ttyUSB1";
-const char *input_filename;
-const char *output_filename;
-uint32_t offset = 0x08000000, length = 0;
-int retry_on_damaged_ack;
-
-/* STM32MON function return values */
-enum {
-	STM32_SUCCESS   = 0,
-	STM32_EIO       = -1,	/* IO error */
-	STM32_EINVAL    = -2,	/* Got a faulty response from device */
-	STM32_ETIMEDOUT = -3,	/* Device didn't respond in a time window. */
-	STM32_ENOMEM    = -4,	/* Failed to allocate memory. */
-	STM32_ENACK     = -5,	/* Got NACK. */
-	STM32_EDACK     = -6,	/* Got a damanged ACK. */
-};
-BUILD_ASSERT(STM32_SUCCESS == 0);
-#define IS_STM32_ERROR(res)		((res) < STM32_SUCCESS)
-
-/* optional command flags */
-enum {
-	FLAG_UNPROTECT      = 0x01,
-	FLAG_ERASE          = 0x02,
-	FLAG_GO             = 0x04,
-	FLAG_READ_UNPROTECT = 0x08,
-	FLAG_CR50_MODE	    = 0x10,
-};
-
-typedef struct {
-	int size;
-	uint8_t *data;
-} payload_t;
-
-/* List all possible flash erase functions */
-typedef int command_erase_t(int fd, uint16_t count, uint16_t start);
-command_erase_t command_erase;
-command_erase_t command_ext_erase;
-command_erase_t command_erase_i2c;
-
-command_erase_t *erase;
-
-static void discard_input(int);
-
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-
-/* On user request save all data exchange with the target in this log file. */
-static FILE *log_file;
-
-/* Statistic data structure for response kind. */
-struct {
-	const char * const event_name;
-	uint32_t event_count;
-} stat_resp[] = {
-	{ "RESP_ACK",	0 },
-	{ "RESP_NACK",	0 },
-	{ "RESP_BUSY",	0 },
-	{ "RESP_DAMAGED_ACK", 0 },
-	{ "JUNK",	0 },
-};
-
-enum {
-	RESP_ACK_IDX = 0,
-	RESP_NACK_IDX,
-	RESP_BUSY_IDX,
-	RESP_DAMAGED_ACK_IDX,
-	JUNK_IDX,
-	MAX_EVENT_IDX
-};
-
-BUILD_ASSERT(ARRAY_SIZE(stat_resp) == MAX_EVENT_IDX);
-
-/*
- * Print data into the log file, in hex, 16 bytes per line, prefix the first
- * line with the value supplied by the caller (usually 'r' or 'w' for
- * read/write).
- */
-static void dump_log(const char *prefix, const void *data, size_t count)
-{
-	size_t i;
-
-	fprintf(log_file, "%s: ", prefix);
-	for (i = 0; i < count; i++) {
-		if (i && !(i  % 16))
-			fprintf(log_file, "\n   ");
-		fprintf(log_file, " %02x", ((uint8_t *)data)[i]);
-	}
-
-	if (count % 16)
-		fprintf(log_file, "\n");
-
-	/* Make sure all data is there even in case of aborts/crashes. */
-	fflush(log_file);
-}
-
-/*
- * Wrappers for standard library read() and write() functions. Add transferred
- * data to the log if log file is opened.
- */
-static ssize_t read_wrapper(int fd, void *buf, size_t count)
-{
-	ssize_t rv = read(fd, buf, count);
-
-	if (log_file && (rv > 0))
-		dump_log("r", buf, rv);
-
-	return rv;
-}
-
-static ssize_t write_wrapper(int fd, const void *buf, size_t count)
-{
-	ssize_t rv;
-
-	rv = write(fd, buf, count);
-
-	if (log_file && (rv > 0))
-		dump_log("w", buf, rv);
-
-	return rv;
-}
-
-int open_serial(const char *port, int cr50_mode)
-{
-	int fd, res;
-	struct termios cfg, cfg_copy;
-
-	fd = open(port, O_RDWR | O_NOCTTY);
-	if (fd == -1) {
-		perror("Unable to open serial port");
-		return -1;
-	}
-
-	/* put the tty in "raw" mode at the defined baudrate */
-	res = tcgetattr(fd, &cfg);
-	if (res == -1) {
-		perror("Cannot read tty attributes");
-		close(fd);
-		return -1;
-	}
-	cfmakeraw(&cfg);
-
-	/* Don't bother setting speed and parity when programming over Cr50. */
-	if (!cr50_mode) {
-		cfsetspeed(&cfg, baudrate);
-		/* serial mode should be 8e1 */
-		cfg.c_cflag |= PARENB;
-	}
-
-	/* 200 ms timeout */
-	cfg.c_cc[VTIME] = 2;
-	cfg.c_cc[VMIN] = 0;
-	memcpy(&cfg_copy, &cfg, sizeof(cfg_copy));
-
-	/*
-	 * tcsetattr() returns success if any of the modifications succeed, so
-	 * its return value of zero is not an indication of success, one needs
-	 * to check the result explicitly.
-	 */
-	tcsetattr(fd, TCSANOW, &cfg);
-	if (tcgetattr(fd, &cfg)) {
-		perror("Failed to re-read tty attributes");
-		close(fd);
-		return -1;
-	}
-
-	if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
-		/*
-		 * On some systems the setting which does not come through is
-		 * the parity. We can try continuing without it when using
-		 * certain interfaces, let's try.
-		 */
-		cfg_copy.c_cflag &= ~PARENB;
-		if (memcmp(&cfg, &cfg_copy, sizeof(cfg))) {
-			/*
-			 * Something other than parity failed to get set, this
-			 * is an error.
-			 */
-			perror("Cannot set tty attributes");
-			close(fd);
-			return -1;
-		} else {
-			fprintf(stderr, "Failed to enable parity\n");
-		}
-	}
-
-	discard_input(fd); /* in case were were invoked soon after reset */
-	return fd;
-}
-
-int open_i2c(const int port)
-{
-	int fd;
-	char filename[20];
-
-	snprintf(filename, 19, "/dev/i2c-%d", port);
-	fd = open(filename, O_RDWR);
-	if (fd < 0) {
-		perror("Unable to open i2c adapter");
-		return -1;
-	}
-	if (ioctl(fd, I2C_SLAVE, i2c_slave_address >> 1) < 0) {
-		perror("Unable to select proper address");
-		close(fd);
-		return -1;
-	}
-
-	return fd;
-}
-
-int open_spi(const char *port)
-{
-	int fd;
-	int res;
-	uint32_t mode = SPI_MODE_0;
-	uint8_t bits = 8;
-
-	fd = open(port, O_RDWR);
-	if (fd == -1) {
-		perror("Unable to open SPI controller");
-		return -1;
-	}
-
-	res = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
-	if (res == -1) {
-		perror("Cannot set SPI mode");
-		close(fd);
-		return -1;
-	}
-
-	res = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
-	if (res == -1) {
-		perror("Cannot set SPI bits per word");
-		close(fd);
-		return -1;
-	}
-
-	return fd;
-}
-
-static void discard_input(int fd)
-{
-	uint8_t buffer[64];
-	int res, i;
-	int count_of_zeros;
-
-	/* Skip in i2c and spi modes */
-	if (mode != MODE_SERIAL)
-		return;
-
-	/* eat trailing garbage */
-	count_of_zeros = 0;
-	do {
-		res = read_wrapper(fd, buffer, sizeof(buffer));
-		if (res > 0) {
-
-			/* Discard zeros in the beginning of the buffer. */
-			for (i = 0; i < res; i++)
-				if (buffer[i])
-					break;
-
-			count_of_zeros += i;
-			if (i == res) {
-				/* Only zeros, nothing to print out. */
-				continue;
-			}
-
-			/* Discard zeros in the end of the buffer. */
-			while (!buffer[res - 1]) {
-				count_of_zeros++;
-				res--;
-			}
-
-			printf("Recv[%d]:", res - i);
-			for (; i < res; i++)
-				printf("%02x ", buffer[i]);
-			printf("\n");
-		}
-	} while (res > 0);
-
-	if (count_of_zeros)
-		printf("%d zeros ignored\n", count_of_zeros);
-}
-
-int wait_for_ack(int fd)
-{
-	uint8_t resp;
-	int res;
-	time_t deadline = time(NULL) + DEFAULT_TIMEOUT;
-	const uint8_t ack = RESP_ACK;
-
-	while (time(NULL) < deadline) {
-		res = read_wrapper(fd, &resp, 1);
-		if ((res < 0) && (errno != EAGAIN)) {
-			perror("Failed to read answer");
-			return STM32_EIO;
-		}
-
-		if (res != 1)
-			continue;
-
-		switch (resp) {
-		case RESP_ACK:
-			stat_resp[RESP_ACK_IDX].event_count++;
-			if (mode == MODE_SPI) /* Ack the ACK */
-				if (write_wrapper(fd, &ack, 1) != 1)
-					return STM32_EIO;
-			return STM32_SUCCESS;
-
-		case RESP_NACK:
-			stat_resp[RESP_NACK_IDX].event_count++;
-			fprintf(stderr, "NACK\n");
-			if (mode == MODE_SPI) /* Ack the NACK */
-				if (write_wrapper(fd, &ack, 1) != 1)
-					return STM32_EIO;
-			discard_input(fd);
-			return STM32_ENACK;
-
-		case RESP_BUSY:
-			stat_resp[RESP_BUSY_IDX].event_count++;
-			/* I2C Boot protocol 1.1 */
-			deadline = time(NULL) + DEFAULT_TIMEOUT;
-			break;
-
-		case RESP_DAMAGED_ACK:
-			if (retry_on_damaged_ack) {
-				/* It is a damaged ACK. However, device is
-				 * likely to believe it sent ACK, so let's not
-				 * treat it as junk.
-				 */
-				stat_resp[RESP_DAMAGED_ACK_IDX].event_count++;
-				fprintf(stderr, "DAMAGED_ACK\n");
-				return STM32_EDACK;
-			}
-
-			/* Do not break so that it can be handled as junk */
-		default:
-			stat_resp[JUNK_IDX].event_count++;
-			if (mode == MODE_SERIAL)
-				fprintf(stderr, "Receive junk: %02x\n", resp);
-			break;
-		}
-	}
-	fprintf(stderr, "Timeout\n");
-	return STM32_ETIMEDOUT;
-}
-
-int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt,
-		 uint8_t *resp, int resp_size, int ack_requested)
-{
-	int res, i, c;
-	payload_t *p;
-	int readcnt = 0;
-
-	uint8_t cmd_frame[] = { SOF, cmd,
-				/* XOR checksum */
-				(uint8_t)(0xff ^ cmd) };
-	/* only the SPI mode needs the Start Of Frame byte */
-	int cmd_off = mode == MODE_SPI ? 0 : 1;
-	int count_damaged_ack = 0;
-
-	/* Send the command index */
-	res = write_wrapper(fd, cmd_frame + cmd_off,
-			    sizeof(cmd_frame) - cmd_off);
-	if (res <= 0) {
-		perror("Failed to write command frame");
-		return STM32_EIO;
-	}
-
-	/* Wait for the ACK */
-	res = wait_for_ack(fd);
-	if (res == STM32_EDACK) {
-		++count_damaged_ack;
-	} else if (IS_STM32_ERROR(res)) {
-		const char *name = cmd_lookup_name(cmd);
-		char hex[sizeof("0xFF")];
-		snprintf(hex, sizeof(hex), "0x%02x", cmd);
-		fprintf(stderr, "Failed to get command %s ACK\n",
-			name ? name : hex);
-		return res;
-	}
-
-	/* Send the command payloads */
-	for (p = loads, c = 0; c < cnt; c++, p++) {
-		uint8_t crc = 0;
-		int size = p->size;
-		uint8_t *data = (uint8_t *)(malloc(size + 1)), *data_ptr;
-
-		if (data == NULL) {
-			fprintf(stderr,
-				"Failed to allocate memory for load %d\n", c);
-			return STM32_ENOMEM;
-		}
-		memcpy(data, p->data, size);
-		for (i = 0; i < size; i++)
-			crc ^= data[i];
-		if (size == 1)
-			crc = 0xff ^ crc;
-		data[size] = crc;
-		size++;
-		data_ptr = data;
-		while (size) {
-			res = write_wrapper(fd, data_ptr, size);
-			if (res < 0) {
-				perror("Failed to write command payload");
-				free(data);
-				return STM32_EIO;
-			}
-			size -= res;
-			data_ptr += res;
-		}
-		free(data);
-
-		/* Wait for the ACK */
-		res = wait_for_ack(fd);
-		if (res == STM32_EDACK) {
-			++count_damaged_ack;
-		} else if (IS_STM32_ERROR(res)) {
-			if (res != STM32_ETIMEDOUT)
-				fprintf(stderr,
-					"payload %d ACK failed for CMD%02x\n",
-					c, cmd);
-			return res;
-		}
-	}
-
-	/* Read the answer payload */
-	if (resp) {
-		if (mode == MODE_SPI) /* ignore extra byte */
-			if (read_wrapper(fd, resp, 1) < 0)
-				return STM32_EIO;
-		while ((resp_size > 0) &&
-		       (res = read_wrapper(fd, resp, resp_size))) {
-			if (res < 0) {
-				perror("Failed to read payload");
-				return STM32_EIO;
-			}
-			readcnt += res;
-			resp += res;
-			resp_size -= res;
-		}
-
-		/* Wait for the ACK */
-		if (ack_requested) {
-			res = wait_for_ack(fd);
-			if (res == STM32_EDACK) {
-				++count_damaged_ack;
-			} else if (IS_STM32_ERROR(res)) {
-				fprintf(stderr,
-					"Failed to get response to command"
-					" 0x%02x ACK\n", cmd);
-				return res;
-			}
-		}
-	}
-
-	if (count_damaged_ack)
-		return STM32_EDACK;
-
-	return readcnt;
-}
-
-int send_command_retry(int fd, uint8_t cmd, payload_t *loads,
-		int cnt, uint8_t *resp, int resp_size, int ack_requested)
-{
-	int res;
-	int retries = MAX_RETRY_COUNT;
-
-	do {
-		int ack_tries = MAX_ACK_RETRY_COUNT;
-
-		res = send_command(fd, cmd, loads, cnt, resp, resp_size,
-			ack_requested);
-
-		while (res == STM32_ETIMEDOUT && ack_tries--) {
-			if (cmd == CMD_WRITEMEM) {
-				/* send garbage byte */
-				res = write_wrapper(fd, loads->data, 1);
-				/* Don't care much since it is a  garbage
-				 * transfer to let the device not wait for
-				 * any missing data, if any.
-				 */
-				if (res < 0)
-					fprintf(stderr, "warn: write failed\n");
-			}
-			res = wait_for_ack(fd);
-		}
-	} while ((res == STM32_ENACK || res == STM32_EDACK) && retries--);
-
-	return res;
-}
-
-struct stm32_def *command_get_id(int fd)
-{
-	int res;
-	uint8_t id[3];
-	uint16_t chipid;
-	struct stm32_def *def;
-
-	res = send_command(fd, CMD_GETID, NULL, 0, id, sizeof(id), 1);
-	if (res > 0) {
-		if (id[0] != 1) {
-			fprintf(stderr, "unknown ID : %02x %02x %02x\n",
-				id[0], id[1], id[2]);
-			return NULL;
-		}
-		chipid = (id[1] << 8) | id[2];
-		for (def = chip_defs; def->id; def++)
-			if (def->id == chipid)
-				break;
-		if (def->id == 0)
-			def = NULL;
-		printf("ChipID 0x%03x : %s\n", chipid, def ? def->name : "???");
-		return def;
-	}
-
-	return NULL;
-}
-
-int init_monitor(int fd)
-{
-	int res = 0;
-	int attempts = connect_retries + 1;
-	uint8_t init = mode == MODE_SPI ? SOF : CMD_INIT;
-
-	/* Skip in i2c mode */
-	if (mode == MODE_I2C)
-		return STM32_SUCCESS;
-
-	printf("Waiting for the monitor startup ...");
-	fflush(stdout);
-
-	while (connect_retries < 0 || attempts--) {
-		/* Send the command index */
-		res = write_wrapper(fd, &init, 1);
-		if (res <= 0) {
-			perror("Failed to write command");
-			return STM32_EIO;
-		}
-		/* Wait for the ACK */
-		res = wait_for_ack(fd);
-		if (res == STM32_SUCCESS)
-			break;
-		if (res == STM32_ENACK) {
-			/* we got NACK'ed, the loader might be already started
-			 * let's ping it to check
-			 */
-			if (command_get_id(fd)) {
-				printf("Monitor already started.\n");
-				return STM32_SUCCESS;
-			}
-		}
-		if (IS_STM32_ERROR(res) && res != STM32_ETIMEDOUT)
-			return res;
-		fflush(stdout);
-	}
-
-	if (IS_STM32_ERROR(res)) {
-		printf("Giving up after %d attempts.\n", connect_retries + 1);
-		return res;
-	}
-
-	printf("Done.\n");
-
-	/* read trailing chars */
-	discard_input(fd);
-
-	return STM32_SUCCESS;
-}
-
-int command_get_commands(int fd, struct stm32_def *chip)
-{
-	int res, i;
-	uint8_t cmds[64];
-
-	/*
-	 * For i2c, we have to request the exact amount of bytes we expect.
-	 */
-	res = send_command(fd, CMD_GETCMD, NULL, 0, cmds,
-			   chip->cmds_len[(mode == MODE_I2C ? 1 : 0)], 1);
-	if (res > 0) {
-		if (cmds[0] > sizeof(cmds) - 2) {
-			fprintf(stderr, "invalid GET answer (%02x...)\n",
-				cmds[0]);
-			return STM32_EINVAL;
-		}
-		printf("Bootloader v%d.%d, commands : ",
-		       cmds[1] >> 4, cmds[1] & 0xf);
-		boot_loader_version = cmds[1];
-
-		erase = command_erase;
-		for (i = 2; i < 2 + cmds[0]; i++) {
-			const char *name;
-			if (cmds[i] == CMD_EXTERASE)
-				erase = command_ext_erase;
-			name = cmd_lookup_name(cmds[i]);
-			if (name)
-				printf("%s ", name);
-			else
-				printf("0x%02x ", cmds[i]);
-		}
-
-		if (mode == MODE_I2C)
-			erase = command_erase_i2c;
-		printf("\n");
-
-		return STM32_SUCCESS;
-	}
-
-	fprintf(stderr, "Cannot get bootloader command list.\n");
-	return STM32_EINVAL;
-}
-
-static int use_progressbar;
-static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
-static void draw_spinner(uint32_t remaining, uint32_t size)
-{
-	int percent = (size - remaining)*100/size;
-	if (use_progressbar) {
-		int dots = percent / 4;
-
-		while (dots > windex) {
-			putchar('#');
-			windex++;
-		}
-	} else {
-		printf("\r%c%3d%%", wheel[windex++], percent);
-		windex %= sizeof(wheel);
-	}
-	fflush(stdout);
-}
-
-int command_read_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
-{
-	int res;
-	uint32_t remaining = size;
-	uint32_t addr_be;
-	uint8_t cnt;
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{1, &cnt}
-	};
-
-	while (remaining) {
-		uint32_t bytes = MIN(remaining, PAGE_SIZE);
-
-		cnt = (uint8_t) (bytes - 1);
-		addr_be = htonl(address);
-
-		draw_spinner(remaining, size);
-
-		res = send_command_retry(fd, CMD_READMEM, loads, 2, buffer,
-					 bytes, 0);
-		if (IS_STM32_ERROR(res))
-			return STM32_EIO;
-
-		buffer += bytes;
-		address += bytes;
-		remaining -= bytes;
-	}
-
-	return size;
-}
-
-int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
-{
-	int res = 0;
-	int i;
-	uint32_t remaining = size;
-	uint32_t addr_be;
-	uint32_t cnt;
-	uint8_t outbuf[257];
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{sizeof(outbuf), outbuf}
-	};
-
-	while (remaining) {
-		cnt = MIN(remaining, PAGE_SIZE);
-		/* skip empty blocks to save time */
-		for (i = 0; i < cnt && buffer[i] == 0xff; i++)
-			;
-		if (i != cnt) {
-			addr_be = htonl(address);
-			outbuf[0] = cnt - 1;
-			loads[1].size = cnt + 1;
-			memcpy(outbuf + 1, buffer, cnt);
-
-			draw_spinner(remaining, size);
-
-			res = send_command_retry(fd, CMD_WRITEMEM, loads, 2,
-					   NULL, 0, 1);
-			if (IS_STM32_ERROR(res))
-				return STM32_EIO;
-		}
-		buffer += cnt;
-		address += cnt;
-		remaining -= cnt;
-	}
-
-	return size;
-}
-
-int command_ext_erase(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint16_t count_be = htons(count);
-	payload_t load = { 2, (uint8_t *)&count_be };
-	uint16_t *pages = NULL;
-
-	if (count < 0xfff0) {
-		int i;
-		/* not a special value : build a list of pages */
-		load.size = 2 * (count + 1);
-		pages = (uint16_t *)(malloc(load.size));
-		if (!pages)
-			return STM32_ENOMEM;
-		load.data = (uint8_t *)pages;
-		pages[0] = htons(count - 1);
-		for (i = 0; i < count; i++)
-			pages[i+1] = htons(start + i);
-	}
-
-	printf("Erasing...\n");
-	res = send_command_retry(fd, CMD_EXTERASE, &load, 1, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-int command_erase_i2c(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint8_t erase_cmd;
-	uint16_t count_be = htons(count);
-	payload_t load[2] = {
-		{ 2, (uint8_t *)&count_be},
-		{ 0, NULL},
-	};
-	int load_cnt = 1;
-	uint16_t *pages = NULL;
-
-	if (count < 0xfff) {
-		int i;
-		/* not a special value : build a list of pages */
-		/*
-		 * I2c protocol requires 2 messages, the count has to be acked
-		 * before the addresses can be sent.
-		 * TODO(gwendal): Still broken on i2c.
-		 */
-		load_cnt = 2;
-		load[1].size = 2 * count;
-		pages = (uint16_t *)(malloc(load[1].size));
-		if (!pages)
-			return STM32_ENOMEM;
-		load[1].data = (uint8_t *)pages;
-		count_be = htons(count - 1);
-		for (i = 0; i < count; i++)
-			pages[i] = htons(start + i);
-	}
-
-	erase_cmd = (boot_loader_version == 0x10) ? CMD_EXTERASE :
-		     CMD_NO_STRETCH_ERASE;
-
-	printf("Erasing...\n");
-	res = send_command(fd, erase_cmd, load, load_cnt, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-
-int command_erase(int fd, uint16_t count, uint16_t start)
-{
-	int res;
-	uint8_t count_8bit = count;
-	payload_t load = { 1, &count_8bit };
-	uint8_t *pages = NULL;
-
-	if (count < 0xff) {
-		int i;
-		/* not a special value : build a list of pages */
-		load.size = count + 1;
-		pages = (uint8_t *)(malloc(load.size));
-		if (!pages)
-			return STM32_ENOMEM;
-		load.data = (uint8_t *)pages;
-		pages[0] = count - 1;
-		for (i = 0; i < count; i++)
-			pages[i+1] = start + i;
-	}
-
-	printf("Erasing...\n");
-	res = send_command(fd, CMD_ERASE, &load, 1, NULL, 0, 1);
-	if (!IS_STM32_ERROR(res))
-		printf("Flash erased.\n");
-
-	if (pages)
-		free(pages);
-	return res;
-}
-
-int command_read_unprotect(int fd)
-{
-	int res;
-	int retries = MAX_ACK_RETRY_COUNT;
-
-	printf("Unprotecting flash read...\n");
-
-	res = send_command(fd, CMD_RU, NULL, 0, NULL, 0, 1);
-	/*
-	 * Read unprotect can trigger a mass erase, which can take long time
-	 * (e.g. 13s+ on STM32H7)
-	 */
-	do {
-		res = wait_for_ack(fd);
-	} while ((res == STM32_ETIMEDOUT) && --retries);
-
-	if (IS_STM32_ERROR(res)) {
-		fprintf(stderr, "Failed to get read-protect ACK\n");
-		return res;
-	}
-	printf("Flash read unprotected.\n");
-
-	/*
-	 * This command triggers a reset.
-	 *
-	 * Wait at least the reboot delay, else we could reconnect
-	 * before the actual reset depending on the bootloader.
-	 */
-	usleep(MAX_DELAY_REBOOT);
-	if (IS_STM32_ERROR(init_monitor(fd))) {
-		fprintf(stderr, "Cannot recover after RU reset\n");
-		return STM32_EIO;
-	}
-
-	return STM32_SUCCESS;
-}
-
-int command_write_unprotect(int fd)
-{
-	int res;
-
-	res = send_command(fd, CMD_WU, NULL, 0, NULL, 0, 1);
-	if (IS_STM32_ERROR(res))
-		return STM32_EIO;
-
-	/* Wait for the ACK */
-	if (wait_for_ack(fd) < 0) {
-		fprintf(stderr, "Failed to get write-protect ACK\n");
-		return STM32_EINVAL;
-	}
-	printf("Flash write unprotected.\n");
-
-	/*
-	 * This command triggers a reset.
-	 *
-	 * Wait at least the reboot delay, else we could reconnect
-	 * before the actual reset depending on the bootloader.
-	 */
-	usleep(MAX_DELAY_REBOOT);
-	if (IS_STM32_ERROR(init_monitor(fd))) {
-		fprintf(stderr, "Cannot recover after WP reset\n");
-		return STM32_EIO;
-	}
-
-	return STM32_SUCCESS;
-}
-
-int command_go(int fd, uint32_t address)
-{
-	int res;
-	uint32_t addr_be = htonl(address);
-	payload_t load = { 4, (uint8_t *)&addr_be };
-
-	res = send_command(fd, CMD_GO, &load, 1, NULL, 0, 1);
-	if (IS_STM32_ERROR(res))
-		return STM32_EIO;
-
-#if 0 /* this ACK should exist according to the documentation ... */
-	/* Wait for the ACK */
-	if (wait_for_ack(fd) < 0) {
-		fprintf(stderr, "Failed to get GO ACK\n");
-		return -EINVAL;
-	}
-#endif
-
-	printf("Program started at 0x%08x.\n", address);
-	return STM32_SUCCESS;
-}
-
-/*
- * The bootloader does not allow reading directly from the "device signature"
- * registers. However, it does allow reading the OTP region, so this function
- * starts a read from the last byte in that region and reads an additional
- * number of bytes to read the requested register.
- *
- * Example:
- *
- * Given a chip with OTP region starting at address 0x1FFF7800 with a size of
- * 528 bytes and a register that we want to read at address 0x1FFF7A10 with a
- * size of 12 bytes:
- *
- * We start the read at the last byte in the OTP region:
- *
- * 0x1FFF7800 + 528 - 1 = 0x1FFF7A0F
- *
- * From 0x1FFF7A0F we perform a read of (12 + 1) = 13 bytes in order to read the
- * 12 bytes starting at 0x1FFF7A10 (the actual register we care about).
- *
- * Returns zero on success, negative on failure.
- */
-int read_device_signature_register(int fd, const struct stm32_def *chip,
-				   uint32_t addr, uint32_t size_bytes,
-				   uint8_t *out_buffer)
-{
-	int res;
-	uint8_t *buffer;
-	struct memory_info otp = chip->memory_layout.otp_area;
-	uint32_t otp_end_addr = otp.addr + otp.size_bytes - 1;
-	uint32_t offset = addr - otp_end_addr;
-	uint32_t read_size_bytes = offset + size_bytes;
-
-	if (!otp.addr) {
-		fprintf(stderr, "No otp_area.addr specified for given chip.\n");
-		return STM32_EINVAL;
-	}
-
-	if (addr <= otp_end_addr) {
-		fprintf(stderr, "Attempting to read from invalid address: "
-				"%08X\n", addr);
-		return STM32_EINVAL;
-	}
-
-	/*
-	 * The USART/SPI/I2C bootloader can only read at most 256 bytes in a
-	 * single read command (see AN4286 section 2.5 or AN3155 section 3.4).
-	 *
-	 * command_read_mem will correctly chunk larger requests, but the
-	 * subsequent reads will fail because the bootloader won't allow reads
-	 * from a starting address that is beyond the OTP region.
-	 */
-	if (read_size_bytes > PAGE_SIZE) {
-		fprintf(stderr,
-			"Requested register 0x%08X is outside read range.\n",
-			addr);
-		return STM32_EINVAL;
-	}
-
-	buffer = (uint8_t *)(malloc(read_size_bytes));
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %" PRIu32 " bytes\n",
-			read_size_bytes);
-		return STM32_ENOMEM;
-	}
-
-	res = command_read_mem(fd, otp_end_addr, read_size_bytes, buffer);
-	if (res == read_size_bytes)
-		memcpy(out_buffer, buffer + offset, size_bytes);
-	else
-		fprintf(stderr,
-			"Cannot read %" PRIu32 " bytes from address 0x%08X",
-			read_size_bytes, otp_end_addr);
-
-	free(buffer);
-	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_flash_size_register(int fd, struct stm32_def *chip,
-			     uint16_t *flash_size_kbytes)
-{
-	int res;
-	uint32_t flash_size_addr = chip->device_signature.flash_size_addr;
-
-	if (!flash_size_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip,
-		flash_size_addr, sizeof(*flash_size_kbytes),
-		(uint8_t *)flash_size_kbytes);
-
-	if (!IS_STM32_ERROR(res))
-		printf("Flash size: %" PRIu16 " KB\n", *flash_size_kbytes);
-	else
-		fprintf(stderr,
-			"Unable to read flash size register (0x%08X).\n",
-			flash_size_addr);
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_unique_device_id_register(int fd, struct stm32_def *chip,
-	uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES])
-{
-	int i;
-	int res;
-	uint32_t unique_device_id_addr =
-		chip->device_signature.unique_device_id_addr;
-
-	if (!unique_device_id_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip, unique_device_id_addr,
-		STM32_UNIQUE_ID_SIZE_BYTES, device_id);
-
-	if (!IS_STM32_ERROR(res)) {
-		printf("Unique Device ID: 0x");
-		for (i = STM32_UNIQUE_ID_SIZE_BYTES - 1; i >= 0; i--)
-			printf("%02X", device_id[i]);
-		printf("\n");
-	} else {
-		fprintf(stderr,
-			"Unable to read unique device ID register (0x%08X). "
-			"Ignoring non-critical failure.\n",
-			unique_device_id_addr);
-	}
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_package_data_register(int fd, struct stm32_def *chip,
-			       uint16_t *package_data)
-{
-	int res;
-	uint32_t package_data_addr = chip->device_signature.package_data_addr;
-
-	if (!package_data_addr)
-		return STM32_EINVAL;
-
-	res = read_device_signature_register(fd, chip, package_data_addr,
-					     sizeof(*package_data),
-					     (uint8_t *)package_data);
-
-	if (!IS_STM32_ERROR(res))
-		printf("Package data register: %04X\n", *package_data);
-	else
-		fprintf(stderr,
-			"Failed to read package data register (0x%08X). "
-			"Ignoring non-critical failure.\n", package_data_addr);
-
-	return res;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int read_flash(int fd, struct stm32_def *chip, const char *filename,
-	       uint32_t offset, uint32_t size)
-{
-	int res;
-	FILE *hnd;
-	uint8_t *buffer;
-
-	if (!size)
-		size = chip->flash_size;
-	buffer = (uint8_t *)(malloc(size));
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return STM32_ENOMEM;
-	}
-
-	hnd = fopen(filename, "w");
-	if (!hnd) {
-		fprintf(stderr, "Cannot open file %s for writing\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-
-	printf("Reading %d bytes at 0x%08x\n", size, offset);
-	res = command_read_mem(fd, offset, size, buffer);
-	if (res > 0) {
-		if (fwrite(buffer, res, 1, hnd) != 1)
-			fprintf(stderr, "Cannot write %s\n", filename);
-	}
-	printf("\r   %d bytes read.\n", res);
-
-	fclose(hnd);
-	free(buffer);
-	return IS_STM32_ERROR(res) ? res : STM32_SUCCESS;
-}
-
-/* Return zero on success, a negative error value on failures. */
-int write_flash(int fd, struct stm32_def *chip, const char *filename,
-		uint32_t offset)
-{
-	int res, written;
-	FILE *hnd;
-	int size = chip->flash_size;
-	uint8_t *buffer = (uint8_t *)(malloc(size));
-
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return STM32_ENOMEM;
-	}
-
-	if (!strncmp(filename, "-", sizeof("-")))
-		hnd = fdopen(STDIN_FILENO, "r");
-	else
-		hnd = fopen(filename, "r");
-	if (!hnd) {
-		fprintf(stderr, "Cannot open file %s for reading\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-	res = fread(buffer, 1, size, hnd);
-	fclose(hnd);
-	if (res <= 0) {
-		fprintf(stderr, "Cannot read %s\n", filename);
-		free(buffer);
-		return STM32_EIO;
-	}
-
-	/* faster write: skip empty trailing space */
-	while (res && buffer[res - 1] == 0xff)
-		res--;
-	/* ensure 'res' is multiple of 4 given 'size' is and res <= size */
-	res = (res + 3) & ~3;
-
-	printf("Writing %d bytes at 0x%08x\n", res, offset);
-	written = command_write_mem(fd, offset, res, buffer);
-	if (written != res) {
-		fprintf(stderr, "Error writing to flash\n");
-		free(buffer);
-		return STM32_EIO;
-	}
-	printf("\r   %d bytes written.\n", written);
-
-	free(buffer);
-	return STM32_SUCCESS;
-}
-
-static const struct option longopts[] = {
-	{"adapter", 1, 0, 'a'},
-	{"baudrate", 1, 0, 'b'},
-	{"cr50", 0, 0, 'c'},
-	{"device", 1, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"go", 0, 0, 'g'},
-	{"help", 0, 0, 'h'},
-	{"length", 1, 0, 'n'},
-	{"location", 1, 0, 'l'},
-	{"logfile", 1, 0, 'L'},
-	{"offset", 1, 0, 'o'},
-	{"progressbar", 0, 0, 'p'},
-	{"read", 1, 0, 'r'},
-	{"retries", 1, 0, 'R'},
-	{"spi", 1, 0, 's'},
-	{"unprotect", 0, 0, 'u'},
-	{"version", 0, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
-};
-
-void display_usage(char *program)
-{
-	fprintf(stderr,
-		"Usage: %s [-a <i2c_adapter> [-l address ]] | [-s]"
-		" [-d <tty>] [-b <baudrate>]] [-u] [-e] [-U]"
-		" [-r <file>] [-w <file>] [-o offset] [-n length] [-g] [-p]"
-		" [-L <log_file>] [-c] [-v]\n",
-		program);
-	fprintf(stderr, "Can access the controller via serial port or i2c\n");
-	fprintf(stderr, "Serial port mode:\n");
-	fprintf(stderr, "--d[evice] <tty> : use <tty> as the serial port\n");
-	fprintf(stderr, "--b[audrate] <baudrate> : set serial port speed "
-			"to <baudrate> bauds\n");
-	fprintf(stderr, "i2c mode:\n");
-	fprintf(stderr, "--a[dapter] <id> : use i2c adapter <id>.\n");
-	fprintf(stderr, "--l[ocation]  <address> : use address <address>.\n");
-	fprintf(stderr, "--s[pi]: use spi mode.\n");
-	fprintf(stderr, "--u[nprotect] : remove flash write protect\n");
-	fprintf(stderr, "--U[nprotect] : remove flash read protect\n");
-	fprintf(stderr, "--e[rase] : erase all the flash content\n");
-	fprintf(stderr, "--r[ead] <file> : read the flash content and "
-			"write it into <file>\n");
-	fprintf(stderr, "--s[pi] </dev/spi> : use SPI adapter on </dev>.\n");
-	fprintf(stderr, "--w[rite] <file|-> : read <file> or\n\t"
-			"standard input and write it to flash\n");
-	fprintf(stderr, "--o[ffset] : offset to read/write/start from/to\n");
-	fprintf(stderr, "--n[length] : amount to read/write\n");
-	fprintf(stderr, "--g[o] : jump to execute flash entrypoint\n");
-	fprintf(stderr, "--p[rogressbar] : use a progress bar instead of "
-			"the spinner\n");
-	fprintf(stderr, "--R[etries] <num> : limit connect retries to num\n");
-	fprintf(stderr, "-L[ogfile] <file> : save all communications exchange "
-		"in a log file\n");
-	fprintf(stderr, "-c[r50_mode] : consider device to be a Cr50 interface,"
-		" no need to set UART port attributes\n");
-	fprintf(stderr, "--v[ersion] : print version and exit\n");
-
-	exit(2);
-}
-
-void display_version(const char *exe_name)
-{
-	printf("%s version: %s %s %s\n", exe_name, CROS_STM32MON_VERSION, DATE,
-		BUILDER);
-}
-
-speed_t parse_baudrate(const char *value)
-{
-	int rate = atoi(value);
-
-	switch (rate) {
-	case 9600:
-		return B9600;
-	case 19200:
-		return B19200;
-	case 38400:
-		return B38400;
-	case 57600:
-		return B57600;
-	case 115200:
-		return B115200;
-	default:
-		fprintf(stderr, "Invalid baudrate %s, using %d\n",
-			value, DEFAULT_BAUDRATE);
-		return DEFAULT_BAUDRATE;
-	}
-}
-
-int parse_parameters(int argc, char **argv)
-{
-	int opt, idx;
-	int flags = 0;
-	const char *log_file_name = NULL;
-
-	while ((opt = getopt_long(argc, argv, "a:l:b:cd:eghL:n:o:pr:R:s:w:uUv?",
-				  longopts, &idx)) != -1) {
-		switch (opt) {
-		case 'a':
-			i2c_adapter = atoi(optarg);
-			mode = MODE_I2C;
-			break;
-		case 'l':
-			i2c_slave_address = strtol(optarg, NULL, 0);
-			break;
-		case 'b':
-			baudrate = parse_baudrate(optarg);
-			break;
-		case 'c':
-			flags |= FLAG_CR50_MODE;
-			break;
-		case 'd':
-			serial_port = optarg;
-			mode = MODE_SERIAL;
-			break;
-		case 'e':
-			flags |= FLAG_ERASE;
-			break;
-		case 'g':
-			flags |= FLAG_GO;
-			break;
-		case 'h':
-		case '?':
-			display_usage(argv[0]);
-			break;
-		case 'L':
-			log_file_name = optarg;
-			break;
-		case 'n':
-			length = strtol(optarg, NULL, 0);
-			break;
-		case 'o':
-			offset = strtol(optarg, NULL, 0);
-			break;
-		case 'p':
-			use_progressbar = 1;
-			break;
-		case 'r':
-			input_filename = optarg;
-			break;
-		case 'R':
-			connect_retries = atoi(optarg);
-			break;
-		case 's':
-			spi_adapter = optarg;
-			mode = MODE_SPI;
-			break;
-		case 'w':
-			output_filename = optarg;
-			break;
-		case 'u':
-			flags |= FLAG_UNPROTECT;
-			break;
-		case 'U':
-			flags |= FLAG_READ_UNPROTECT;
-			break;
-		case 'v':
-			display_version(argv[0]);
-			exit(0);
-		}
-	}
-
-	if (log_file_name) {
-		log_file = fopen(log_file_name, "w");
-		if (!log_file) {
-			fprintf(stderr, "failed to open %s for writing\n",
-				log_file_name);
-			exit(2);
-		}
-	}
-	return flags;
-}
-
-static void display_stat_response(void)
-{
-	uint32_t total_events = MAX_EVENT_IDX;
-	uint32_t idx;
-
-	printf("--\n");
-	for (idx = 0; idx < total_events; ++idx) {
-		printf("%-18s %d\n", stat_resp[idx].event_name,
-				stat_resp[idx].event_count);
-	}
-	printf("--\n");
-}
-
-int main(int argc, char **argv)
-{
-	int ser;
-	struct stm32_def *chip;
-	int ret = STM32_EIO;
-	int res;
-	int flags;
-	uint16_t flash_size_kbytes = 0;
-	uint8_t unique_device_id[STM32_UNIQUE_ID_SIZE_BYTES] = { 0 };
-	uint16_t package_data_reg = 0;
-
-	/* Parse command line options */
-	flags = parse_parameters(argc, argv);
-
-	display_version(argv[0]);
-
-	retry_on_damaged_ack = !!(flags & FLAG_CR50_MODE);
-
-	switch (mode) {
-	case MODE_SPI:
-		ser = open_spi(spi_adapter);
-		break;
-	case MODE_I2C:
-		ser = open_i2c(i2c_adapter);
-		break;
-	case MODE_SERIAL:
-	default:
-		/* Open the serial port tty */
-		ser = open_serial(serial_port, !!(flags & FLAG_CR50_MODE));
-	}
-	if (ser < 0)
-		return 1;
-	/* Trigger embedded monitor detection */
-	res = init_monitor(ser);
-	if (IS_STM32_ERROR(res))
-		goto terminate;
-
-	chip = command_get_id(ser);
-	if (!chip)
-		goto terminate;
-
-	if (command_get_commands(ser, chip) < 0)
-		goto terminate;
-
-	if (flags & FLAG_READ_UNPROTECT)
-		command_read_unprotect(ser);
-
-	/*
-	 * Use the actual size if we were able to read it since some chips
-	 * have the same chip ID, but different flash sizes based on the
-	 * package.
-	 */
-	res = read_flash_size_register(ser, chip, &flash_size_kbytes);
-	if (!IS_STM32_ERROR(res))
-		chip->flash_size = flash_size_kbytes * KBYTES_TO_BYTES;
-
-	/*
-	 * This is simply informative at the moment, so we don't care about the
-	 * return value.
-	 */
-	(void)read_unique_device_id_register(ser, chip, unique_device_id);
-
-	/*
-	 * This is simply informative at the moment, so we don't care about the
-	 * return value.
-	 */
-	(void)read_package_data_register(ser, chip, &package_data_reg);
-
-	if (flags & FLAG_UNPROTECT)
-		command_write_unprotect(ser);
-
-	if (flags & FLAG_ERASE || output_filename) {
-		if ((!strncmp("STM32L15", chip->name, 8)) ||
-		    (!strncmp("STM32F411", chip->name, 9))) {
-			/* Mass erase is not supported on these chips*/
-			int i, page_count = chip->flash_size / chip->page_size;
-			for (i = 0; i < page_count; i += 128) {
-				int count = MIN(128, page_count - i);
-				ret = erase(ser, count, i);
-				if (IS_STM32_ERROR(ret))
-					goto terminate;
-			}
-		} else {
-			ret = erase(ser, 0xFFFF, 0);
-			if (IS_STM32_ERROR(ret))
-				goto terminate;
-		}
-	}
-
-	if (input_filename) {
-		ret = read_flash(ser, chip, input_filename, offset, length);
-		if (IS_STM32_ERROR(ret))
-			goto terminate;
-	}
-
-	if (output_filename) {
-		ret = write_flash(ser, chip, output_filename, offset);
-		if (IS_STM32_ERROR(ret))
-			goto terminate;
-	}
-
-	/* Run the program from flash */
-	if (flags & FLAG_GO)
-		command_go(ser, offset);
-
-	/* Normal exit */
-	ret = STM32_SUCCESS;
-terminate:
-	if (log_file)
-		fclose(log_file);
-
-	/* Close serial port */
-	close(ser);
-
-	if (retry_on_damaged_ack)
-		display_stat_response();
-
-	if (IS_STM32_ERROR(ret)) {
-		fprintf(stderr, "Failed: %d\n", ret);
-		return 1;
-	}
-
-	printf("Done.\n");
-	return 0;
-}
diff --git a/util/tagbranch.sh b/util/tagbranch.sh
deleted file mode 100755
index 3e196b6f25..0000000000
--- a/util/tagbranch.sh
+++ /dev/null
@@ -1,84 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Generate git strings for tagging EC branches.
-#
-# This script builds up on ideas put by vpalatin@ into util/getversion.sh
-#
-# Git allows to count number of patches between the current state of the tree
-# and any directly preceding tag in the tree. That is if we tag the first
-# patch in the current branch, we can tell how many patches are in the branch
-# above that tag. And if we tag the branch such that the tag string includes
-# the branch name, we can also say what branch we are in looking at the
-# closest tag in the tree.
-#
-# This admittedly brittle script automates the process of tagging for the EC
-# git tree in Chrome OS repo, but it could be used for any other Chrome OS
-# repo git tree just as well.
-#
-# The script is brittle because it relies on the following assumptions which
-# are true for Chrome OS repo at the time of writing:
-#
-# - the upstream branch alias name shows up in the 'git branch -a' output
-#   separated by ->
-# - the upstream branch alias name has the format of
-#   cros/<branch name>
-# - the remote git server name shows up in 'git config -l' output in the
-#   line starting with "remote.cros.url="
-# - firmware branch names have format of firmware-<board>-XXXXXX
-# - the current branch was cut off of <remote name>/master
-#
-# The tag name generated by this script would be the XXXXX string with dots,
-# if any, replaced by underscores.
-
-# Retrieve the upstream branch alias name
-UPSTREAM="$(git branch -a | awk '/->/ {print $3}')"
-if [[ -z "${UPSTREAM}" ]]; then
-  echo "Failed to determine upstream branch alias" >&2
-  exit 1
-fi
-
-export ORIGIN_NAME="cros"
-ORIGIN="$(git config "remote.${ORIGIN_NAME}.url")"
-
-# The last common patch between this branch and the master.
-BRANCH_POINT="$(git merge-base "${UPSTREAM}" "${ORIGIN_NAME}/master")"
-if [[ -z "${BRANCH_POINT}" ]]; then
-  echo "Failed to determine cros/master branch point" >&2
-  exit 1
-fi
-
-# Derive tag base string from the upstream branch name as described above.
-TAG_BASE="$(sed 's/.*-//       # drop everything up to including the last -
-                 s/\./_/g      # replace dots and dashes with underscores
-      ' <<< "${UPSTREAM}" )"
-
-if [[ "${TAG_BASE}" == "master" ]]; then
-  echo "Nothing to tag in master branch" >&2
-  exit 1
-fi
-
-TAG="v1.${TAG_BASE}.0"
-
-#SHA1 of the first patch of this branch
-BASE_SHA="$(git rev-list --ancestry-path "${BRANCH_POINT}".."${UPSTREAM}" |
-    tail -1)"
-
-echo "Will run git tag -a -m \"firmware branch ${TAG}\" ${TAG} ${BASE_SHA}"
-if git tag -a -m "firmware branch ${TAG}" "${TAG}" "${BASE_SHA}"; then
-  cat <<EOF
-
-A new tag '$TAG' has been set. Use the following command
-to push it to the server
-
-git push --tags ${ORIGIN} ${TAG}
-
-Or if you want to delete it:
-
-git tag -d $TAG
-
-EOF
-fi
diff --git a/util/temp_metrics.conf b/util/temp_metrics.conf
deleted file mode 100644
index ccd3254beb..0000000000
--- a/util/temp_metrics.conf
+++ /dev/null
@@ -1,396 +0,0 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description     "Temporary, quick-hack metrics collection & thermal daemon"
-author          "chromium-os-dev@chromium.org"
-
-# This is for quickly adding UMA stats that we may need for
-# short-term experiments, when we don't have the time to add
-# stuff to metrics_daemon.  That's where it should go in the
-# long term.
-#
-# This is also currently doing a userland thermal loop to allow
-# for quick experimentation.  This thermal loop will eventually
-# move to the BIOS once the data from experiments help prove its
-# efficacy.
-
-start on started system-services
-stop on stopping system-services
-respawn
-
-script
-  TEMP_OFFSET=273  # difference between K (reported by EC) and C (used in UMA)
-
-  # Thermal loop fields
-  CPU_MAX_FREQ_FIELD=1
-  CPU_MIN_FREQ_FIELD=2
-  GPU_MAX_FREQ_FIELD=3
-  CPU_DUTY_CYCLE_FIELD=4
-  PKG_POWER_LIMIT_FIELD=5
-
-  # Thermal loop steps
-  all_steps="
-  1801000 800000 1150 0 0x180aa00dd8088 # no throttling
-  1801000 800000 1150 0 0x180aa00dd8080 # cap pkg to 16W
-  1801000 800000 1150 0 0x180aa00dd8078 # cap pkg to 15W
-  1801000 800000 1150 0 0x180aa00dd8070 # cap pkg to 14W
-  1801000 800000 1150 0 0x180aa00dd8068 # cap pkg to 13W
-  1800000 800000 900 0 0x180aa00dd8068 # disable turbo
-  1600000 800000 800 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  1400000 800000 700 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  1200000 800000 600 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  1000000 800000 500 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  800000 800000 400 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  800000 800000 350 0 0x180aa00dd8068 # cap CPU & GPU frequency
-  800000 800000 350 0x1c 0x180aa00dd8068 # duty cycle CPU
-  800000 800000 350 0x18 0x180aa00dd8068 # duty cycle CPU
-  "
-  max_steps=$(($(echo "$all_steps" | wc -l) - 3))
-
-  get_step() {
-    row=$(($1 + 2))
-    out=$(echo "$all_steps" | awk "{if (NR==$row) print}")
-    echo "$out"
-  }
-
-  get_field() {
-    out=$(echo "$2" | awk "{print \$$1}")
-    echo $out
-  }
-
-  get_peci_temp() {
-    tempk=$(ectool temps 9 | sed 's/[^0-9]//g')
-    tempc=$((tempk - $TEMP_OFFSET))
-    echo $tempc
-  }
-
-  get_sensor_temp() {
-    s=$1
-    tempc=0
-    if out=$(ectool temps $s); then
-       tempk=$(echo $out | sed 's/[^0-9]//g')
-       tempc=$((tempk - $TEMP_OFFSET))
-    fi
-    echo $tempc
-  }
-
-  get_sensor_list() {
-    # USB C-Object: 1 or 13
-    # PCH D-Object: 3
-    # Hinge C-Object: 5 or 15
-    # Charger D-Object: 7
-    if ectool tempsinfo 1 | grep -q "USB C-Object"; then
-      usb_c_object=1
-    else
-      usb_c_object=13
-    fi
-    charger_d_object=7
-    echo $usb_c_object $charger_d_object
-  }
-
-  set_calibration_data() {
-    B0='-2.94e-5'
-    B1='-5.7e-7'
-    B2='4.63e-9'
-
-    USB_C_S0='2.712e-14'
-    PCH_D_S0='9.301e-14'
-    HINGE_C_S0='-11.000e-14'
-    CHARGER_D_S0='5.141e-14'
-
-    # Note that the sensor numbering is different between the ectool tmp006
-    # and temps/tempsinfo commands.
-    USB_C="0 $USB_C_S0 $B0 $B1 $B2"
-    PCH_D="1 $PCH_D_S0 $B0 $B1 $B2"
-    HINGE_C="2 $HINGE_C_S0 $B0 $B1 $B2"
-    CHARGER_D="3 $CHARGER_D_S0 $B0 $B1 $B2"
-
-    for i in "$USB_C" "$PCH_D" "$HINGE_C" "$CHARGER_D"; do
-      # Add "--" otherwise ectool will barf when trying to parse negative
-      # coefficients.
-      ectool tmp006cal -- $i
-    done
-  }
-
-  max_skin_temp=0
-  sensor_temperatures=
-
-  get_max_skin_temp() {
-    sensor_temperatures=
-    max_skin_temp=0
-    for i in $*; do
-      t=$(get_sensor_temp $i)
-      sensor_temperatures=$sensor_temperatures$i:$t:
-      if [ $t -gt $max_skin_temp ]; then
-        max_skin_temp=$t
-      fi
-    done
-
-    # Record the PECI CPU temperature also.
-    i=9
-    t=$(get_sensor_temp $i)
-    sensor_temperatures=$sensor_temperatures$i:$t:
-  }
-
-  set_cpu_freq() {
-    max_freq=$1
-    min_freq=$2
-    for cpu in /sys/devices/system/cpu/cpu?/cpufreq; do
-      echo 800000 > $cpu/scaling_min_freq
-      echo 800000 > $cpu/scaling_max_freq
-      echo $max_freq > $cpu/scaling_max_freq
-      echo $min_freq > $cpu/scaling_min_freq
-    done
-  }
-
-  set_gpu_min_freq() {
-    GPU_MIN_FREQ=450
-    echo $GPU_MIN_FREQ > /sys/kernel/debug/dri/0/i915_min_freq
-  }
-
-  set_gpu_max_freq() {
-    gpu_max_freq=$1
-    if [ $GPU_MIN_FREQ -gt $gpu_max_freq ]; then
-      gpu_max_freq=$GPU_MIN_FREQ
-    fi
-    echo $gpu_max_freq > /sys/kernel/debug/dri/0/i915_max_freq
-  }
-
-  set_duty_cycle() {
-    duty_cycle=$1
-    for i in 0 1 2 3; do
-      iotools wrmsr $i 0x19a $duty_cycle
-    done
-  }
-
-  set_pkg_power_limit() {
-    pwr_limit=$1
-    iotools wrmsr 0 0x610 $pwr_limit
-  }
-
-  log_message() {
-    logger -t temp_metrics "$*"
-  }
-
-  TEMP_THRESHOLD_1=38
-  TEMP_THRESHOLD_1_WM=40
-  TEMP_THRESHOLD_2=45
-  TEMP_THRESHOLD_2_WM=47
-  TEMP_THRESHOLD_3=50
-  TEMP_THRESHOLD_3_WM=50
-
-  TEMP_THRESHOLD_0_MIN_STEP=0
-  TEMP_THRESHOLD_0_MAX_STEP=0
-  TEMP_THRESHOLD_1_MIN_STEP=1
-  TEMP_THRESHOLD_1_MAX_STEP=5
-  TEMP_THRESHOLD_2_MIN_STEP=6
-  TEMP_THRESHOLD_2_MAX_STEP=9
-  TEMP_THRESHOLD_3_MIN_STEP=10
-  TEMP_THRESHOLD_3_MAX_STEP=13
-
-  current_step=1
-  new_step=0
-
-  thermal_loop() {
-    # Hack to reset turbo activation threshold since BIOS can change it
-    # underneath us.
-    iotools wrmsr 0 0x64c 0x12
-
-    skin_temp=$1
-    if [ $skin_temp -gt $TEMP_THRESHOLD_3 ]; then
-      temp_watermark=$TEMP_THRESHOLD_3_WM
-      min_step=$TEMP_THRESHOLD_3_MIN_STEP
-      max_step=$TEMP_THRESHOLD_3_MAX_STEP
-    elif [ $skin_temp -gt $TEMP_THRESHOLD_2 ]; then
-      temp_watermark=$TEMP_THRESHOLD_2_WM
-      min_step=$TEMP_THRESHOLD_2_MIN_STEP
-      max_step=$TEMP_THRESHOLD_2_MAX_STEP
-    elif [ $skin_temp -gt $TEMP_THRESHOLD_1 ]; then
-      temp_watermark=$TEMP_THRESHOLD_1_WM
-      min_step=$TEMP_THRESHOLD_1_MIN_STEP
-      max_step=$TEMP_THRESHOLD_1_MAX_STEP
-    else
-      temp_watermark=0
-      min_step=$TEMP_THRESHOLD_0_MIN_STEP
-      max_step=$TEMP_THRESHOLD_0_MAX_STEP
-    fi
-
-    if [ $skin_temp -gt $temp_watermark ]; then
-      if [ $current_step -ne $max_step ]; then
-        new_step=$(($current_step + 1))
-      fi
-    elif [ $skin_temp -lt $temp_watermark ]; then
-      if [ $current_step -gt $min_step ]; then
-        new_step=$(($current_step - 1))
-      fi
-    else
-      new_step=$current_step
-    fi
-
-    if [ $new_step -gt $max_step ]; then
-        new_step=$max_step
-    elif [ $new_step -lt $min_step ]; then
-        new_step=$min_step
-    fi
-
-    if  [ $new_step -eq $current_step ]; then
-      return
-    fi
-
-    current_step=$new_step
-    step=$(get_step $new_step)
-
-    log_message "Throttling (temps: $sensor_temperatures):" $step
-
-    cpu_max_freq=$(get_field $CPU_MAX_FREQ_FIELD "$step")
-    cpu_min_freq=$(get_field $CPU_MIN_FREQ_FIELD "$step")
-    gpu_max_freq=$(get_field $GPU_MAX_FREQ_FIELD "$step")
-    cpu_duty_cycle=$(get_field $CPU_DUTY_CYCLE_FIELD "$step")
-    pkg_power_limit=$(get_field $PKG_POWER_LIMIT_FIELD "$step")
-
-    set_cpu_freq $cpu_max_freq $cpu_min_freq
-    set_gpu_max_freq $gpu_max_freq
-    set_duty_cycle $cpu_duty_cycle
-    set_pkg_power_limit $pkg_power_limit
-  }
-
-  get_fan_rpm() {
-    echo $(ectool pwmgetfanrpm | sed 's/[^0-9]//g')
-  }
-
-  set_fan_rpm() {
-    ectool pwmsetfanrpm $1
-  }
-
-  reset_fan_thresholds() {
-    temp_low1=105
-    temp_low2=105
-    temp_low3=105
-    temp_low4=105
-    temp_low5=105
-    temp_low6=105
-  }
-
-  last_rpm=10
-  temp_low1=105
-  temp_low2=105
-  temp_low3=105
-  temp_low4=105
-  temp_low5=105
-  temp_low6=105
-
-  fan_loop() {
-    skin_temp=$1
-
-    if [ $skin_temp -gt 48 ] || [ $skin_temp -gt $temp_low1 ]; then
-      rpm=9300
-      reset_fan_thresholds
-      temp_low1=46
-    elif [ $skin_temp -gt 44 ] || [ $skin_temp -gt $temp_low2 ]; then
-      rpm=8000
-      reset_fan_thresholds
-      temp_low2=43
-    elif [ $skin_temp -gt 42 ] || [ $skin_temp -gt $temp_low3 ]; then
-      rpm=7000
-      reset_fan_thresholds
-      temp_low3=41
-    elif [ $skin_temp -gt 40 ] || [ $skin_temp -gt $temp_low4 ]; then
-      rpm=5500
-      reset_fan_thresholds
-      temp_low4=39
-    elif [ $skin_temp -gt 38 ] || [ $skin_temp -gt $temp_low5 ]; then
-      rpm=4000
-      reset_fan_thresholds
-      temp_low5=34
-    elif [ $skin_temp -gt 33 ] || [ $skin_temp -gt $temp_low6 ]; then
-      rpm=3000
-      reset_fan_thresholds
-      temp_low6=30
-    else
-      rpm=0
-      reset_fan_thresholds
-    fi
-
-    # During S0->S3->S0 transitions, the EC sets the fan RPM to 0. This script
-    # isn't aware of such transitions. Read the current fan RPM again to see
-    # if it got set to 0. Note that comparing the current fan RPM against last
-    # requested RPM won't suffice since the actual fan RPM may not be exactly
-    # what was requested.
-    cur_rpm=$(get_fan_rpm)
-    if ([ $cur_rpm -ne 0 ] && [ $last_rpm -eq $rpm ]) || \
-       ([ $cur_rpm -eq 0 ] && [ $rpm -eq 0 ]); then
-      last_rpm=$rpm
-      return
-    fi
-
-    log_message "Setting fan RPM (temps: $sensor_temperatures): $last_rpm -> $rpm"
-
-    last_rpm=$rpm
-    set_fan_rpm $rpm
-  }
-
-  # Thermal zone 1 is for operating systems where a userland thermal loop
-  # doesn't exist. Disable it.
-  if [ -e /sys/class/thermal/thermal_zone1/mode ]; then
-    echo -n 'disabled' > /sys/class/thermal/thermal_zone1/mode
-  fi
-
-  # Enable the fan in case no other code has enabled it.
-  ectool fanduty 0
-
-  # Get list of sensors to monitor.
-  sensor_list=$(get_sensor_list)
-
-  # Set sensor calibration data.
-  set_calibration_data
-
-  # Set minimum GPU frequency.
-  set_gpu_min_freq
-
-  loop_count=0
-  ec_fan_loop=0
-
-  while true; do
-    sleep 10
-    loop_count=$(($loop_count + 1))
-
-    # Read the max skin temperature.
-    get_max_skin_temp $sensor_list
-
-    if [ $max_skin_temp -eq 0 ]; then
-      if [ $ec_fan_loop -eq 0 ]; then
-        log_message "Invalid max skin temp. Switching to EC fan loop."
-        ectool autofanctrl
-        ec_fan_loop=1
-        last_rpm=10
-      fi
-    else
-      # Run the fan loop.
-      fan_loop $max_skin_temp
-      ec_fan_loop=0
-
-      # Run the thermal loop.
-      thermal_loop $max_skin_temp
-    fi
-
-    # Report the metrics once every 30 seconds.
-    if [ $loop_count -lt 3 ]; then
-      continue
-    fi
-    loop_count=0
-
-    ectool temps all | while read line; do
-      index=$(printf "%02d" "${line%%:*}")
-      tempk="${line##* }"
-      tempc=$(($tempk - $TEMP_OFFSET))
-      # ignore values below freezing
-      if [ $tempc -lt 0 ]; then
-        tempc=0
-      fi
-      # Use a linear histogram with 1 C buckets starting at 0.
-      N_SLOTS=180
-      metrics_client -e Platform.Temperature.Sensor$index $tempc $N_SLOTS
-    done
-  done
-end script
diff --git a/util/test-inject-keys.sh b/util/test-inject-keys.sh
deleted file mode 100755
index 031452150e..0000000000
--- a/util/test-inject-keys.sh
+++ /dev/null
@@ -1,111 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Regression test for inject-keys.py.  Works by creating a "fake" ectool
-# and comparing expected ectool commands with expected ones.
-
-TMPX=/tmp/inject-key-test$$_x
-TMPY=/tmp/inject-key-test$$_y
-
-cleanup() {
-  rm -f ./ectool $TMPX $TMPY
-}
-
-fail() {
-  echo $*
-  exit 1
-}
-
-trap cleanup SIGINT
-
-PATH=.:$PATH
-
-if [ -e ectool ]; then
-  if [ "$(echo $(cat ectool))" != '#! /bin/bash echo $*' ]; then
-    echo "./ectool exists, please remove it to run this script"
-    exit 1
-  fi
-fi
-
-echo "#! /bin/bash" > ectool
-echo 'echo $*' >> ectool
-chmod a+x ectool
-
-# tests that should fail
-
-# bad args
-./inject-keys.py        >& /dev/null && fail "undetected zero args"
-./inject-keys.py -k     >& /dev/null && fail "undetected mismatched args (1)"
-./inject-keys.py -k a b >& /dev/null && fail "undetected mismatched args (2)"
-./inject-keys.py -z a   >& /dev/null && fail "undetected bad flag"
-
-# bad key
-./inject-keys.py -p foobar >& /dev/null && fail "undetected bad key"
-
-# tests that should succeed with the expected output
-
-# simple string
-./inject-keys.py -s abcd > $TMPX
-
-cat > $TMPY <<EOF
-kbpress 4 1 1
-kbpress 4 1 0
-kbpress 0 3 1
-kbpress 0 3 0
-kbpress 5 2 1
-kbpress 5 2 0
-kbpress 4 2 1
-kbpress 4 2 0
-EOF
-
-cmp $TMPX $TMPY || fail $TMPX and $TMPY differ
-
-# string with shifted characters
-./inject-keys.py -s A@%Bx > $TMPX
-
-cat > $TMPY <<EOF
-kbpress 5 7 1
-kbpress 4 1 1
-kbpress 4 1 0
-kbpress 5 7 0
-kbpress 5 7 1
-kbpress 6 4 1
-kbpress 6 4 0
-kbpress 5 7 0
-kbpress 5 7 1
-kbpress 3 3 1
-kbpress 3 3 0
-kbpress 5 7 0
-kbpress 5 7 1
-kbpress 0 3 1
-kbpress 0 3 0
-kbpress 5 7 0
-kbpress 5 4 1
-kbpress 5 4 0
-EOF
-
-cmp $TMPX $TMPY || fail $TMPX and $TMPY differ
-
-# keystroke injection
-./inject-keys.py -k enter > $TMPX
-
-cat > $TMPY <<EOF
-kbpress 4 11 1
-kbpress 4 11 0
-EOF
-
-cmp $TMPX $TMPY || fail $TMPX and $TMPY differ
-
-# key event injection
-./inject-keys.py -p enter > $TMPX
-
-cat > $TMPY <<EOF
-kbpress 4 11 1
-EOF
-
-cmp $TMPX $TMPY || fail $TMPX and $TMPY differ
-
-cleanup
diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py
deleted file mode 100644
index 0426dc3e6f..0000000000
--- a/util/test_kconfig_check.py
+++ /dev/null
@@ -1,154 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Test for Kconfig checker"""
-
-import contextlib
-import io
-import os
-import re
-import sys
-import tempfile
-import unittest
-
-import kconfig_check
-
-# Prefix that we strip from each Kconfig option, when considering whether it is
-# equivalent to a CONFIG option with the same name
-PREFIX = 'PLATFORM_EC_'
-
-@contextlib.contextmanager
-def capture_sys_output():
-    """Capture output for testing purposes
-
-    Use this to suppress stdout/stderr output:
-        with capture_sys_output() as (stdout, stderr)
-            ...do something...
-    """
-    capture_out, capture_err = io.StringIO(), io.StringIO()
-    old_out, old_err = sys.stdout, sys.stderr
-    try:
-        sys.stdout, sys.stderr = capture_out, capture_err
-        yield capture_out, capture_err
-    finally:
-        sys.stdout, sys.stderr = old_out, old_err
-
-
-# Use unittest since it produced less verbose output than pytest and can be run
-# directly from Python. You can still run this test with 'pytest' if you like.
-class KconfigCheck(unittest.TestCase):
-    """Tests for the KconfigCheck class"""
-    def test_simple_check(self):
-        """Check it detected a new ad-hoc CONFIG"""
-        checker = kconfig_check.KconfigCheck()
-        self.assertEqual(['NEW_ONE'], checker.find_new_adhoc(
-            configs=['NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'],
-            kconfigs=['IN_KCONFIG'],
-            allowed=['OLD_ONE']))
-
-    def test_sorted_check(self):
-        """Check it sorts the results in order"""
-        checker = kconfig_check.KconfigCheck()
-        self.assertSequenceEqual(
-            ['ANOTHER_NEW_ONE', 'NEW_ONE'],
-            checker.find_new_adhoc(
-                configs=['NEW_ONE', 'ANOTHER_NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'],
-                kconfigs=['IN_KCONFIG'],
-                allowed=['OLD_ONE']))
-
-    def test_read_configs(self):
-        """Test KconfigCheck.read_configs()"""
-        checker = kconfig_check.KconfigCheck()
-        with tempfile.NamedTemporaryFile() as configs:
-            with open(configs.name, 'w') as out:
-                out.write("""CONFIG_OLD_ONE=y
-NOT_A_CONFIG
-CONFIG_STRING="something"
-CONFIG_INT=123
-CONFIG_HEX=45ab
-""")
-            self.assertEqual(['OLD_ONE', 'STRING', 'INT', 'HEX'],
-                             checker.read_configs(configs.name))
-
-    @classmethod
-    def setup_srctree(cls, srctree):
-        """Set up some Kconfig files in a directory and subdirs
-
-        Args:
-            srctree: Directory to write to
-        """
-        with open(os.path.join(srctree, 'Kconfig'), 'w') as out:
-            out.write('config PLATFORM_EC_MY_KCONFIG\n')
-        subdir = os.path.join(srctree, 'subdir')
-        os.mkdir(subdir)
-        with open(os.path.join(subdir, 'Kconfig.wibble'), 'w') as out:
-            out.write('menuconfig PLATFORM_EC_MENU_KCONFIG\n')
-
-        # Add a directory which should be ignored
-        bad_subdir = os.path.join(subdir, 'Kconfig')
-        os.mkdir(bad_subdir)
-        with open(os.path.join(bad_subdir, 'Kconfig.bad'), 'w') as out:
-            out.write('menuconfig PLATFORM_EC_BAD_KCONFIG')
-
-    def test_find_kconfigs(self):
-        """Test KconfigCheck.find_kconfigs()"""
-        checker = kconfig_check.KconfigCheck()
-        with tempfile.TemporaryDirectory() as srctree:
-            self.setup_srctree(srctree)
-            files = checker.find_kconfigs(srctree)
-            fnames = [fname[len(srctree):] for fname in files]
-            self.assertEqual(['/Kconfig', '/subdir/Kconfig.wibble'], fnames)
-
-    def test_scan_kconfigs(self):
-        """Test KconfigCheck.scan_configs()"""
-        checker = kconfig_check.KconfigCheck()
-        with tempfile.TemporaryDirectory() as srctree:
-            self.setup_srctree(srctree)
-            self.assertEqual(['MY_KCONFIG', 'MENU_KCONFIG'],
-                             checker.scan_kconfigs(srctree, PREFIX))
-
-    @classmethod
-    def setup_allowed_and_configs(cls, allowed_fname, configs_fname):
-        """Set up the 'allowed' and 'configs' files for tests
-
-        Args:
-            allowed_fname: Filename to write allowed CONFIGs to
-            configs_fname: Filename to which CONFIGs to check should be written
-        """
-        with open(allowed_fname, 'w') as out:
-            out.write('CONFIG_OLD_ONE')
-        with open(configs_fname, 'w') as out:
-            out.write('\n'.join(['CONFIG_OLD_ONE', 'CONFIG_NEW_ONE',
-                                 'CONFIG_MY_KCONFIG']))
-
-    def test_find_new_adhoc_configs(self):
-        """Test KconfigCheck.find_new_adhoc_configs()"""
-        checker = kconfig_check.KconfigCheck()
-        with tempfile.TemporaryDirectory() as srctree:
-            self.setup_srctree(srctree)
-            with tempfile.NamedTemporaryFile() as allowed:
-                with tempfile.NamedTemporaryFile() as configs:
-                    self.setup_allowed_and_configs(allowed.name, configs.name)
-                    result = checker.find_new_adhoc_configs(
-                        configs.name, srctree, allowed.name, PREFIX)
-                    self.assertEqual(['NEW_ONE'], result)
-
-    def test_check(self):
-        """Test running the 'check' subcommand"""
-        with capture_sys_output() as (stdout, stderr):
-            with tempfile.TemporaryDirectory() as srctree:
-                self.setup_srctree(srctree)
-                with tempfile.NamedTemporaryFile() as allowed:
-                    with tempfile.NamedTemporaryFile() as configs:
-                        self.setup_allowed_and_configs(allowed.name, configs.name)
-                        ret_code = kconfig_check.main(
-                            ['-c', configs.name, '-s', srctree,
-                             '-a', allowed.name, '-p', PREFIX, 'check'])
-                        self.assertEqual(1, ret_code)
-        self.assertEqual('', stdout.getvalue())
-        found = re.findall('(CONFIG_.*)', stderr.getvalue())
-        self.assertEqual(['CONFIG_NEW_ONE'], found)
-
-
-if __name__ == '__main__':
-    unittest.main()
diff --git a/util/uart_stress_tester.py b/util/uart_stress_tester.py
deleted file mode 100755
index b3db60060e..0000000000
--- a/util/uart_stress_tester.py
+++ /dev/null
@@ -1,562 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-"""ChromeOS Uart Stress Test
-
-This tester runs the command 'chargen' on EC and/or AP, captures the
-output, and compares it against the expected output to check any characters
-lost.
-
-Prerequisite:
-    (1) This test needs PySerial. Please check if it is available before test.
-        Can be installed by 'pip install pyserial'
-    (2) If servod is running, turn uart_timestamp off before running this test.
-        e.g. dut-control cr50_uart_timestamp:off
-"""
-
-from __future__ import absolute_import
-from __future__ import division
-from __future__ import print_function
-
-import argparse
-import atexit
-import logging
-import os
-import stat
-import sys
-import threading
-import time
-
-import serial
-
-BAUDRATE = 115200                # Default baudrate setting for UART port
-CROS_USERNAME = 'root'           # Account name to login to ChromeOS
-CROS_PASSWORD = 'test0000'       # Password to login to ChromeOS
-CHARGEN_TXT = '0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz'
-                                 # The result of 'chargen 62 62'
-CHARGEN_TXT_LEN = len(CHARGEN_TXT)
-CR = '\r'                        # Carriage Return
-LF = '\n'                        # Line Feed
-CRLF = CR + LF
-FLAG_FILENAME = '/tmp/chargen_testing'
-TPM_CMD = ('trunks_client --key_create --rsa=2048 --usage=sign'
-           ' --key_blob=/tmp/blob &> /dev/null')
-                                 # A ChromeOS TPM command for the cr50 stress
-                                 # purpose.
-CR50_LOAD_GEN_CMD = ('while [[ -f %s ]]; do   %s; done &'
-                     % (FLAG_FILENAME, TPM_CMD))
-                                 # A command line to run TPM_CMD in background
-                                 # infinitely.
-
-
-class ChargenTestError(Exception):
-  """Exception for Uart Stress Test Error"""
-  pass
-
-
-class UartSerial(object):
-  """Test Object for a single UART serial device
-
-  Attributes:
-    UART_DEV_PROFILES
-    char_loss_occurrences: Number that character loss happens
-    cleanup_cli: Command list to perform before the test exits
-    cr50_workload: True if cr50 should be stressed, or False otherwise
-    usb_output: True if output should be generated to USB channel
-    dev_prof: Dictionary of device profile
-    duration: Time to keep chargen running
-    eol: Characters to add at the end of input
-    logger: object that store the log
-    num_ch_exp: Expected number of characters in output
-    num_ch_cap: Number of captured characters in output
-    test_cli: Command list to run for chargen test
-    test_thread: Thread object that captures the UART output
-    serial: serial.Serial object
-  """
-  UART_DEV_PROFILES = (
-      # Kernel
-      {
-          'prompt':'localhost login:',
-          'device_type':'AP',
-          'prepare_cmd':[
-              CROS_USERNAME,             # Login
-              CROS_PASSWORD,             # Password
-              'dmesg -D',                # Disable console message
-              'touch ' + FLAG_FILENAME,  # Create a temp file
-          ],
-          'cleanup_cmd':[
-              'rm -f ' + FLAG_FILENAME,  # Remove the temp file
-              'dmesg -E',                # Enable console message
-              'logout',                  # Logout
-          ],
-          'end_of_input':LF,
-      },
-      # EC
-      {
-          'prompt':'> ',
-          'device_type':'EC',
-          'prepare_cmd':[
-              'chan save',
-              'chan 0'                   # Disable console message
-          ],
-          'cleanup_cmd':['', 'chan restore'],
-          'end_of_input':CRLF,
-      },
-  )
-
-  def __init__(self, port, duration, timeout=1,
-               baudrate=BAUDRATE, cr50_workload=False,
-               usb_output=False):
-    """Initialize UartSerial
-
-    Args:
-      port: UART device path. e.g. /dev/ttyUSB0
-      duration: Time to test, in seconds
-      timeout: Read timeout value.
-      baudrate: Baud rate such as 9600 or 115200.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
-    """
-
-    # Initialize serial object
-    self.serial = serial.Serial()
-    self.serial.port = port
-    self.serial.timeout = timeout
-    self.serial.baudrate = baudrate
-
-    self.duration = duration
-    self.cr50_workload = cr50_workload
-    self.usb_output = usb_output
-
-    self.logger = logging.getLogger(type(self).__name__ + '| ' + port)
-    self.test_thread = threading.Thread(target=self.stress_test_thread)
-
-    self.dev_prof = {}
-    self.cleanup_cli = []
-    self.test_cli = []
-    self.eol = CRLF
-    self.num_ch_exp = 0
-    self.num_ch_cap = 0
-    self.char_loss_occurrences = 0
-    atexit.register(self.cleanup)
-
-  def run_command(self, command_lines, delay=0):
-    """Run command(s) at UART prompt
-
-    Args:
-      command_lines: list of commands to run.
-      delay: delay after a command in second
-    """
-    for cli in command_lines:
-      self.logger.debug('run %r', cli)
-
-      self.serial.write((cli + self.eol).encode())
-      self.serial.flush()
-      if delay:
-        time.sleep(delay)
-
-  def cleanup(self):
-    """Before termination, clean up the UART device."""
-    self.logger.debug('Closing...')
-
-    self.serial.open()
-    self.run_command(self.cleanup_cli)          # Run cleanup commands
-    self.serial.close()
-
-    self.logger.debug('Cleanup done')
-
-  def get_output(self):
-    """Capture the UART output
-
-    Args:
-      stop_char: Read output buffer until it reads stop_char.
-
-    Returns:
-      text from UART output.
-    """
-    if self.serial.inWaiting() == 0:
-      time.sleep(1)
-
-    return self.serial.read(self.serial.inWaiting()).decode()
-
-  def prepare(self):
-    """Prepare the test:
-
-    Identify the type of UART device (EC or Kernel?), then
-    decide what kind of commands to use to generate stress loads.
-
-    Raises:
-      ChargenTestError if UART source can't be identified.
-    """
-    try:
-      self.logger.info('Preparing...')
-
-      self.serial.open()
-
-      # Prepare the device for test
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      self.get_output()      # drain data
-
-      # Give a couple of line feeds, and capture the prompt text
-      self.run_command(['', ''])
-      prompt_txt = self.get_output()
-
-      # Detect the device source: EC or AP?
-      # Detect if the device is AP or EC console based on the captured.
-      for dev_prof in self.UART_DEV_PROFILES:
-        if dev_prof['prompt'] in prompt_txt:
-          self.dev_prof = dev_prof
-          break
-      else:
-        # No prompt patterns were found. UART seems not responding or in
-        # an undesirable status.
-        if prompt_txt:
-          raise ChargenTestError('%s: Got an unknown prompt text: %s\n'
-                                 'Check manually whether %s is available.' %
-                                 (self.serial.port, prompt_txt,
-                                  self.serial.port))
-        else:
-          raise ChargenTestError('%s: Got no input. Close any other connections'
-                                 ' to this port, and try it again.' %
-                                 self.serial.port)
-
-      self.logger.info('Detected as %s UART', self.dev_prof['device_type'])
-      # Log displays the UART type (AP|EC) instead of device filename.
-      self.logger = logging.getLogger(type(self).__name__ + '| ' +
-                                      self.dev_prof['device_type'])
-
-      # Either login to AP or run some commands to prepare the device
-      # for test
-      self.eol = self.dev_prof['end_of_input']
-      self.run_command(self.dev_prof['prepare_cmd'], delay=2)
-      self.cleanup_cli += self.dev_prof['cleanup_cmd']
-
-      # 'chargen' of AP does not have option for USB output.
-      # Force it work on UART.
-      if self.dev_prof['device_type'] == 'AP':
-        self.usb_output = False
-
-      # Check whether the command 'chargen' is available in the device.
-      # 'chargen 1 4' is supposed to print '0000'
-      self.get_output()      # drain data
-
-      chargen_cmd = 'chargen 1 4'
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.run_command([chargen_cmd])
-      tmp_txt = self.get_output()
-
-      # Check whether chargen command is available.
-      if '0000' not in tmp_txt:
-        raise ChargenTestError('%s: Chargen got an unexpected result: %s' %
-                               (self.dev_prof['device_type'], tmp_txt))
-
-      self.num_ch_exp = int(self.serial.baudrate * self.duration / 10)
-      chargen_cmd = 'chargen ' + str(CHARGEN_TXT_LEN) + ' ' + \
-                    str(self.num_ch_exp)
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.test_cli = [chargen_cmd]
-
-      self.logger.info('Ready to test')
-    finally:
-      self.serial.close()
-
-  def stress_test_thread(self):
-    """Test thread
-
-    Raises:
-      ChargenTestError: if broken character is found.
-    """
-    try:
-      self.serial.open()
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      # Run TPM command in background to burden cr50.
-      if self.dev_prof['device_type'] == 'AP' and self.cr50_workload:
-        self.run_command([CR50_LOAD_GEN_CMD])
-        self.logger.debug('run TPM job while %s exists', FLAG_FILENAME)
-
-      # Run the command 'chargen', one time
-      self.run_command([''])  # Give a line feed
-      self.get_output()    # Drain the output
-      self.run_command(self.test_cli)
-      self.serial.readline()    # Drain the echoed command line.
-
-      err_msg = '%s: Expected %r but got %s after %d char received'
-
-      # Keep capturing the output until the test timer is expired.
-      self.num_ch_cap = 0
-      self.char_loss_occurrences = 0
-      data_starve_count = 0
-
-      total_num_ch = self.num_ch_exp    # Expected number of characters in total
-      ch_exp = CHARGEN_TXT[0]
-      ch_cap = 'z'      # any character value is ok for loop initial condition.
-      while self.num_ch_cap < total_num_ch:
-        captured = self.get_output()
-
-        if captured:
-          # There is some output data. Reset the data starvation count.
-          data_starve_count = 0
-        else:
-          data_starve_count += 1
-          if data_starve_count > 1:
-            # If nothing was captured more than once, then terminate the test.
-            self.logger.debug('No more output')
-            break
-
-        for ch_cap in captured:
-          if ch_cap not in CHARGEN_TXT:
-            # If it is not alpha-numeric, terminate the test.
-            if ch_cap not in CRLF:
-              # If it is neither a CR nor LF, then it is an error case.
-              self.logger.error('Whole captured characters: %r', captured)
-              raise ChargenTestError(err_msg % ('Broken char captured', ch_exp,
-                                                hex(ord(ch_cap)),
-                                                self.num_ch_cap))
-
-            # Set the loop termination condition true.
-            total_num_ch = self.num_ch_cap
-
-          if self.num_ch_cap >= total_num_ch:
-            break
-
-          if ch_exp != ch_cap:
-            # If it is alpha-numeric but not continuous, then some characters
-            # are lost.
-            self.logger.error(err_msg, 'Char loss detected',
-                              ch_exp, repr(ch_cap), self.num_ch_cap)
-            self.char_loss_occurrences += 1
-
-            # Recalculate the expected number of characters to adjust
-            # termination condition. The loss might be bigger than this
-            # adjustment, but it is okay since it will terminates by either
-            # CR/LF detection or by data starvation.
-            idx_ch_exp = CHARGEN_TXT.find(ch_exp)
-            idx_ch_cap = CHARGEN_TXT.find(ch_cap)
-            if idx_ch_cap < idx_ch_exp:
-              idx_ch_cap += len(CHARGEN_TXT)
-            total_num_ch -= (idx_ch_cap - idx_ch_exp)
-
-          self.num_ch_cap += 1
-
-          # Determine What character is expected next?
-          ch_exp = CHARGEN_TXT[(CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN]
-
-    finally:
-      self.serial.close()
-
-  def start_test(self):
-    """Start the test thread"""
-    self.logger.info('Test thread starts')
-    self.test_thread.start()
-
-  def wait_test_done(self):
-    """Wait until the test thread get done and join"""
-    self.test_thread.join()
-    self.logger.info('Test thread is done')
-
-  def get_result(self):
-    """Display the result
-
-    Returns:
-      Integer = the number of lost character
-
-    Raises:
-      ChargenTestError: if the capture is corrupted.
-    """
-    # If more characters than expected are captured, it means some messages
-    # from other than chargen are mixed. Stop processing further.
-    if self.num_ch_exp < self.num_ch_cap:
-      raise ChargenTestError('%s: UART output is corrupted.' %
-                             self.dev_prof['device_type'])
-
-    # Get the count difference between the expected to the captured
-    # as the number of lost character.
-    char_lost = self.num_ch_exp - self.num_ch_cap
-    self.logger.info('%8d char lost / %10d (%.1f %%)',
-                     char_lost, self.num_ch_exp,
-                     char_lost * 100.0 / self.num_ch_exp)
-
-    return char_lost, self.num_ch_exp, self.char_loss_occurrences
-
-
-class ChargenTest(object):
-  """UART stress tester
-
-  Attributes:
-    logger: logging object
-    serials: Dictionary where key is filename of UART device, and the value is
-             UartSerial object
-  """
-
-  def __init__(self, ports, duration, cr50_workload=False,
-               usb_output=False):
-    """Initialize UART stress tester
-
-    Args:
-      ports: List of UART ports to test.
-      duration: Time to keep testing in seconds.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
-
-    Raises:
-      ChargenTestError: if any of ports is not a valid character device.
-    """
-
-    # Save the arguments
-    for port in ports:
-      try:
-        mode = os.stat(port).st_mode
-      except OSError as e:
-        raise ChargenTestError(e)
-      if not stat.S_ISCHR(mode):
-        raise ChargenTestError('%s is not a character device.' % port)
-
-    if duration <= 0:
-      raise ChargenTestError('Input error: duration is not positive.')
-
-    # Initialize logging object
-    self.logger = logging.getLogger(type(self).__name__)
-
-    # Create an UartSerial object per UART port
-    self.serials = {}     # UartSerial objects
-    for port in ports:
-      self.serials[port] = UartSerial(port=port, duration=duration,
-                                      cr50_workload=cr50_workload,
-                                      usb_output=usb_output)
-
-  def prepare(self):
-    """Prepare the test for each UART port"""
-    self.logger.info('Prepare ports for test')
-    for _, ser in self.serials.items():
-      ser.prepare()
-    self.logger.info('Ports are ready to test')
-
-  def print_result(self):
-    """Display the test result for each UART port
-
-    Returns:
-      char_lost: Total number of characters lost
-    """
-    char_lost = 0
-    for _, ser in self.serials.items():
-      (tmp_lost, _, _) = ser.get_result()
-      char_lost += tmp_lost
-
-    # If any characters are lost, then test fails.
-    msg = 'lost %d character(s) from the test' % char_lost
-    if char_lost > 0:
-      self.logger.error('FAIL: %s', msg)
-    else:
-      self.logger.info('PASS: %s', msg)
-
-    return char_lost
-
-  def run(self):
-    """Run the stress test on UART port(s)
-
-    Raises:
-      ChargenTestError: If any characters are lost.
-    """
-
-    # Detect UART source type, and decide which command to test.
-    self.prepare()
-
-    # Run the test on each UART port in thread.
-    self.logger.info('Test starts')
-    for _, ser in self.serials.items():
-      ser.start_test()
-
-    # Wait all tests to finish.
-    for _, ser in self.serials.items():
-      ser.wait_test_done()
-
-    # Print the result.
-    char_lost = self.print_result()
-    if char_lost:
-      raise ChargenTestError('Test failed: lost %d character(s)' %
-                             char_lost)
-
-    self.logger.info('Test is done')
-
-def parse_args(cmdline):
-  """Parse command line arguments.
-
-  Args:
-    cmdline: list to be parsed
-
-  Returns:
-    tuple (options, args) where args is a list of cmdline arguments that the
-    parser was unable to match i.e. they're servod controls, not options.
-  """
-  description = """%(prog)s repeats sending a uart console command
-to each UART device for a given time, and check if output
-has any missing characters.
-
-Examples:
-    %(prog)s /dev/ttyUSB2 --time 3600
-    %(prog)s /dev/ttyUSB1 /dev/ttyUSB2 --debug
-    %(prog)s /dev/ttyUSB1 /dev/ttyUSB2 --cr50
-"""
-
-  parser = argparse.ArgumentParser(description=description,
-                                   formatter_class=argparse.RawTextHelpFormatter
-                                  )
-  parser.add_argument('port', type=str, nargs='*',
-                      help='UART device path to test')
-  parser.add_argument('-c', '--cr50', action='store_true', default=False,
-                      help='generate TPM workload on cr50')
-  parser.add_argument('-d', '--debug', action='store_true', default=False,
-                      help='enable debug messages')
-  parser.add_argument('-t', '--time', type=int,
-                      help='Test duration in second', default=300)
-  parser.add_argument('-u', '--usb', action='store_true', default=False,
-                      help='Generate output to USB channel instead')
-  return parser.parse_known_args(cmdline)
-
-
-def main():
-  """Main function wrapper"""
-  try:
-    (options, _) = parse_args(sys.argv[1:])
-
-    # Set Log format
-    log_format = '%(asctime)s %(levelname)-6s | %(name)-25s'
-    date_format = '%Y-%m-%d %H:%M:%S'
-    if options.debug:
-      log_format += ' | %(filename)s:%(lineno)4d:%(funcName)-18s'
-      loglevel = logging.DEBUG
-    else:
-      loglevel = logging.INFO
-    log_format += ' | %(message)s'
-
-    logging.basicConfig(level=loglevel, format=log_format,
-                        datefmt=date_format)
-
-    # Create a ChargenTest object
-    utest = ChargenTest(options.port, options.time,
-                        cr50_workload=options.cr50,
-                        usb_output=options.usb)
-    utest.run()    # Run
-
-  except KeyboardInterrupt:
-    sys.exit(0)
-
-  except ChargenTestError as e:
-    logging.error(str(e))
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
diff --git a/util/unpack_ftb.py b/util/unpack_ftb.py
deleted file mode 100755
index 03127a7089..0000000000
--- a/util/unpack_ftb.py
+++ /dev/null
@@ -1,122 +0,0 @@
-#!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
-
-# Note: This is a py2/3 compatible file.
-
-from __future__ import print_function
-import argparse
-import ctypes
-import os
-
-
-class Header(ctypes.Structure):
-  _pack_ = 1
-  _fields_ = [
-      ('signature', ctypes.c_uint32),
-      ('ftb_ver', ctypes.c_uint32),
-      ('chip_id', ctypes.c_uint32),
-      ('svn_ver', ctypes.c_uint32),
-      ('fw_ver', ctypes.c_uint32),
-      ('config_id', ctypes.c_uint32),
-      ('config_ver', ctypes.c_uint32),
-      ('reserved', ctypes.c_uint8 * 8),
-      ('release_info', ctypes.c_ulonglong),
-      ('sec_size', ctypes.c_uint32 * 4),
-      ('crc', ctypes.c_uint32),
-  ]
-
-FW_HEADER_SIZE = 64
-FW_HEADER_SIGNATURE = 0xAA55AA55
-FW_FTB_VER = 0x00000001
-FW_CHIP_ID = 0x3936
-FW_BYTES_ALIGN = 4
-FW_BIN_VER_OFFSET = 16
-FW_BIN_CONFIG_ID_OFFSET = 20
-
-# Starting address in flash for each section
-FLASH_SEC_ADDR = [
-    0x0000 * 4,  # CODE
-    0x7C00 * 4,  # CONFIG
-    0x7000 * 4,  # CX
-    None  # This section shouldn't exist
-]
-
-UPDATE_PDU_SIZE = 4096
-
-# Bin file format:
-#   FTB header (padded to `UPDATE_PDU_SIZE`)
-#   Flash sections
-#     CODE
-#     CX
-#     CONFIG
-OUTPUT_FILE_SIZE = UPDATE_PDU_SIZE + 128 * 1024
-
-
-def main():
-  parser = argparse.ArgumentParser()
-  parser.add_argument('--input', '-i', required=True)
-  parser.add_argument('--output', '-o', required=True)
-  args = parser.parse_args()
-
-  with open(args.input, 'rb') as f:
-    bs = f.read()
-
-  size = len(bs)
-  if size < FW_HEADER_SIZE + FW_BYTES_ALIGN:
-    raise Exception('FW size too small')
-
-  print('FTB file size:', size)
-
-  header = Header()
-  assert ctypes.sizeof(header) == FW_HEADER_SIZE
-
-  ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header))
-  if (header.signature != FW_HEADER_SIGNATURE or
-      header.ftb_ver != FW_FTB_VER or
-      header.chip_id != FW_CHIP_ID):
-    raise Exception('Invalid header')
-
-  for key, _ in header._fields_:
-    v = getattr(header, key)
-    if isinstance(v, ctypes.Array):
-      print(key, list(map(hex, v)))
-    else:
-      print(key, hex(v))
-
-  dimension = sum(header.sec_size)
-
-  assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size
-  data = bs[FW_HEADER_SIZE:FW_HEADER_SIZE + dimension]
-
-  with open(args.output, 'wb') as f:
-    # ensure the file size
-    f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET)
-    f.write(b'\x00')
-
-    f.seek(0, os.SEEK_SET)
-    f.write(bs[0 : ctypes.sizeof(header)])
-
-    offset = 0
-    # write each sections
-    for i, addr in enumerate(FLASH_SEC_ADDR):
-      size = header.sec_size[i]
-      assert addr is not None or size == 0
-
-      if size == 0:
-        continue
-
-      f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET)
-      f.write(data[offset : offset + size])
-      offset += size
-
-    f.flush()
-
-
-if __name__ == '__main__':
-  main()
diff --git a/util/update_release_branch.py b/util/update_release_branch.py
deleted file mode 100755
index 222c7b01ba..0000000000
--- a/util/update_release_branch.py
+++ /dev/null
@@ -1,260 +0,0 @@
-#!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Release branch updater tool.
-
-This is a tool to merge from the main branch into a release branch.
-
-Inspired by the fingerprint release process:
-http://go/cros-fingerprint-firmware-branching-and-signing and now used by other
-boards.
-"""
-from __future__ import print_function
-import argparse
-import os
-import re
-import subprocess
-import sys
-import textwrap
-
-BUG_NONE_PATTERN = re.compile('none', flags=re.IGNORECASE)
-
-
-def git_commit_msg(branch, head, merge_head, rel_paths):
-    """Generates a merge commit message based off of relevant changes.
-
-    This function obtains the relevant commits from the given relative paths in
-    order to extract the bug numbers. It constructs the git commit message
-    showing the command used to find the relevant commits.
-
-    Args:
-        branch: String indicating the release branch name
-        head: String indicating the HEAD refspec
-        merge_head: String indicating the merge branch refspec.
-        rel_paths: String containing all the relevant paths for this particular
-                   baseboard or board.
-
-    Returns:
-        A String containing the git commit message with the exception of the
-        Signed-Off-By field and Change-ID field.
-    """
-    relevant_commits_cmd, relevant_commits = get_relevant_commits(head,
-                                                                  merge_head,
-                                                                  '--oneline',
-                                                                  rel_paths)
-
-    _, relevant_bugs = get_relevant_commits(head, merge_head, '', rel_paths)
-    relevant_bugs = set(re.findall('BUG=(.*)', relevant_bugs))
-    # Filter out "none" from set of bugs
-    filtered = []
-    for bug_line in relevant_bugs:
-        bug_line = bug_line.replace(',', ' ')
-        bugs = bug_line.split(' ')
-        for bug in bugs:
-            if bug and not BUG_NONE_PATTERN.match(bug):
-                filtered.append(bug)
-    relevant_bugs = filtered
-
-    # TODO(b/179509333): remove Cq-Include-Trybots line when regular CQ and
-    # firmware CQ do not behave differently.
-    COMMIT_MSG_TEMPLATE = """
-Merge remote-tracking branch cros/main into {BRANCH}
-
-Relevant changes:
-
-{RELEVANT_COMMITS_CMD}
-
-{RELEVANT_COMMITS}
-
-BRANCH=None
-{BUG_FIELD}
-TEST=`make -j buildall`
-
-Cq-Include-Trybots: chromeos/cq:cq-orchestrator
-"""
-    # Wrap the relevant commits command and bug field such that we don't exceed
-    # 72 cols.
-    relevant_commits_cmd = textwrap.fill(relevant_commits_cmd, width=72)
-    # Wrap at 68 cols to save room for 'BUG='
-    bugs = textwrap.wrap(' '.join(relevant_bugs), width=68)
-    bug_field = ''
-    for line in bugs:
-        bug_field += 'BUG=' + line + '\n'
-    # Remove the final newline since the template adds it for us.
-    bug_field = bug_field[:-1]
-
-    return COMMIT_MSG_TEMPLATE.format(BRANCH=branch,
-                                      RELEVANT_COMMITS_CMD=relevant_commits_cmd,
-                                      RELEVANT_COMMITS=relevant_commits,
-                                      BUG_FIELD=bug_field)
-
-
-def get_relevant_boards(baseboard):
-    """Searches through the EC repo looking for boards that use the given
-    baseboard.
-
-    Args:
-        baseboard: String containing the baseboard to consider
-
-    Returns:
-        A list of strings containing the boards based off of the baseboard.
-    """
-    proc = subprocess.run(['git', 'grep', 'BASEBOARD:=' + baseboard, '--',
-                           'board/'],
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True)
-    boards = []
-    res = proc.stdout.splitlines()
-    for line in res:
-        boards.append(line.split('/')[1])
-    return boards
-
-
-def get_relevant_commits(head, merge_head, fmt, relevant_paths):
-    """Searches git history to find changes since the last merge which modify
-    files present in relevant_paths.
-
-    Args:
-        head: String indicating the HEAD refspec
-        merge_head: String indicating the merge branch refspec.
-        fmt: An optional string containing the format option for `git log`
-        relevant_paths: String containing all the relevant paths for this
-                        particular baseboard or board.
-
-    Returns:
-        A tuple containing the arguments passed to the git log command and
-        stdout.
-    """
-    if fmt:
-        cmd = ['git', 'log', fmt, head + '..' + merge_head, '--',
-               relevant_paths]
-    else:
-        cmd = ['git', 'log', head + '..' + merge_head, '--', relevant_paths]
-
-    # Pass cmd as a string to subprocess.run() since we need to run with shell
-    # equal to True.  The reason we are using shell equal to True is to take
-    # advantage of the glob expansion for the relevant paths.
-    cmd = ' '.join(cmd)
-    proc = subprocess.run(cmd,
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True,
-                          shell=True)
-    return ''.join(proc.args), proc.stdout
-
-
-def main(argv):
-    """Generates a merge commit from ToT to a desired release branch.
-
-    For the commit message, it finds all the commits that have modified a
-    relevant path. By default this is the baseboard or board directory.  The
-    user may optionally specify a path to a text file which contains a longer
-    list of relevant files.  The format should be in the glob syntax that git
-    log expects.
-
-    Args:
-        argv: A list of the command line arguments passed to this script.
-    """
-    # Set up argument parser.
-    parser = argparse.ArgumentParser(description=("A script that generates a "
-                                                  "merge commit from cros/main"
-                                                  " to a desired release "
-                                                  "branch.  By default, the "
-                                                  "'recursive' merge strategy "
-                                                  "with the 'theirs' strategy "
-                                                  "option is used."))
-    parser.add_argument('--baseboard')
-    parser.add_argument('--board')
-    parser.add_argument('release_branch', help=('The name of the target release'
-                                                ' branch'))
-    parser.add_argument('--relevant_paths_file',
-                        help=('A path to a text file which includes other '
-                              'relevant paths of interest for this board '
-                              'or baseboard'))
-    parser.add_argument('--merge_strategy', '-s', default='recursive',
-                        help='The merge strategy to pass to `git merge -s`')
-    parser.add_argument('--strategy_option', '-X',
-                        help=('The strategy option for the chosen merge '
-                              'strategy'))
-
-    opts = parser.parse_args(argv)
-
-    baseboard_dir = ''
-    board_dir = ''
-
-    if opts.baseboard:
-        # Dereference symlinks so "git log" works as expected.
-        baseboard_dir = os.path.relpath('baseboard/' + opts.baseboard)
-        baseboard_dir = os.path.relpath(os.path.realpath(baseboard_dir))
-
-        boards = get_relevant_boards(opts.baseboard)
-    elif opts.board:
-        board_dir = os.path.relpath('board/' + opts.board)
-        board_dir = os.path.relpath(os.path.realpath(board_dir))
-        boards = [opts.board]
-    else:
-        parser.error('You must specify a board OR a baseboard')
-
-    print("Gathering relevant paths...")
-    relevant_paths = []
-    if opts.baseboard:
-        relevant_paths.append(baseboard_dir)
-    else:
-        relevant_paths.append(board_dir)
-
-    for board in boards:
-        relevant_paths.append('board/' + board)
-
-    # Check for the existence of a file that has other paths of interest.
-    if opts.relevant_paths_file and os.path.exists(opts.relevant_paths_file):
-        with open(opts.relevant_paths_file, 'r') as relevant_paths_file:
-            for line in relevant_paths_file:
-                if not line.startswith('#'):
-                    relevant_paths.append(line.rstrip())
-    relevant_paths.append('util/getversion.sh')
-    relevant_paths = ' '.join(relevant_paths)
-
-    # Now that we have the paths of interest, let's perform the merge.
-    print("Updating remote...")
-    subprocess.run(['git', 'remote', 'update'], check=True)
-    subprocess.run(['git', 'checkout', '-B', opts.release_branch, 'cros/' +
-                    opts.release_branch], check=True)
-    print("Attempting git merge...")
-    if opts.merge_strategy == 'recursive' and not opts.strategy_option:
-        opts.strategy_option = 'theirs'
-    print("Using '%s' merge strategy" % opts.merge_strategy,
-          ("with strategy option '%s'" % opts.strategy_option
-           if opts.strategy_option else ''))
-    arglist = ['git', 'merge', '--no-ff', '--no-commit', 'cros/main', '-s',
-               opts.merge_strategy]
-    if opts.strategy_option:
-        arglist.append('-X' + opts.strategy_option)
-    subprocess.run(arglist, check=True)
-
-    print("Generating commit message...")
-    branch = subprocess.run(['git', 'rev-parse', '--abbrev-ref', 'HEAD'],
-                            stdout=subprocess.PIPE,
-                            encoding='utf-8',
-                            check=True).stdout.rstrip()
-    head = subprocess.run(['git', 'rev-parse', '--short', 'HEAD'],
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True).stdout.rstrip()
-    merge_head = subprocess.run(['git', 'rev-parse', '--short',
-                                 'MERGE_HEAD'],
-                                stdout=subprocess.PIPE,
-                                encoding='utf-8',
-                                check=True).stdout.rstrip()
-
-    print("Typing as fast as I can...")
-    commit_msg = git_commit_msg(branch, head, merge_head, relevant_paths)
-    subprocess.run(['git', 'commit', '--signoff', '-m', commit_msg], check=True)
-    subprocess.run(['git', 'commit', '--amend'], check=True)
-    print(("Finished! **Please review the commit to see if it's to your "
-           "liking.**"))
-
-
-if __name__ == '__main__':
-    main(sys.argv[1:])
\ No newline at end of file
diff --git a/util/usb_if.c b/util/usb_if.c
deleted file mode 100644
index f8aa6bfd7e..0000000000
--- a/util/usb_if.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "usb_if.h"
-
-/* Return 0 on error, since it's never gonna be EP 0 */
-static int find_endpoint(const struct libusb_interface_descriptor *iface,
-			 uint16_t subclass,
-			 uint16_t protocol,
-			 struct usb_endpoint *uep)
-{
-	const struct libusb_endpoint_descriptor *ep;
-
-	if (iface->bInterfaceClass == 255 &&
-	    iface->bInterfaceSubClass == subclass &&
-	    iface->bInterfaceProtocol == protocol &&
-	    iface->bNumEndpoints) {
-		ep = &iface->endpoint[0];
-		uep->ep_num = ep->bEndpointAddress & 0x7f;
-		uep->chunk_len = ep->wMaxPacketSize;
-		return 1;
-	}
-
-	return 0;
-}
-
-/* Return -1 on error */
-static int find_interface(uint16_t subclass,
-			  uint16_t protocol,
-			  struct usb_endpoint *uep)
-{
-	int iface_num = -1;
-	int r, i, j;
-	struct libusb_device *dev;
-	struct libusb_config_descriptor *conf = 0;
-	const struct libusb_interface *iface0;
-	const struct libusb_interface_descriptor *iface;
-
-	dev = libusb_get_device(uep->devh);
-	r = libusb_get_active_config_descriptor(dev, &conf);
-	if (r < 0) {
-		USB_ERROR("libusb_get_active_config_descriptor", r);
-		goto out;
-	}
-
-	for (i = 0; i < conf->bNumInterfaces; i++) {
-		iface0 = &conf->interface[i];
-		for (j = 0; j < iface0->num_altsetting; j++) {
-			iface = &iface0->altsetting[j];
-			if (find_endpoint(iface, subclass, protocol, uep)) {
-				iface_num = i;
-				goto out;
-			}
-		}
-	}
-
-out:
-	libusb_free_config_descriptor(conf);
-	return iface_num;
-}
-
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, const char *serial)
-{
-	struct libusb_device_descriptor desc;
-	libusb_device_handle *handle = NULL;
-	char sn[256];
-	size_t sn_size = 0;
-
-	if (libusb_get_device_descriptor(dev, &desc) < 0)
-		return NULL;
-
-	if (libusb_open(dev, &handle) != LIBUSB_SUCCESS)
-		return NULL;
-
-	if (desc.iSerialNumber && serial) {
-		sn_size = libusb_get_string_descriptor_ascii(handle,
-				desc.iSerialNumber, (unsigned char *)sn,
-				sizeof(sn));
-	}
-	/*
-	 * If the VID, PID, and serial number don't match, then it's not the
-	 * correct device. Close the handle and return NULL.
-	 */
-	if ((vid && vid != desc.idVendor) ||
-	    (pid && pid != desc.idProduct) ||
-	    (serial && ((sn_size != strlen(serial)) ||
-	    memcmp(sn, serial, sn_size)))) {
-		libusb_close(handle);
-		return NULL;
-	}
-	return handle;
-}
-
-int usb_findit(const char *serial, uint16_t vid, uint16_t pid,
-	       uint16_t subclass, uint16_t protocol, struct usb_endpoint *uep)
-{
-	int iface_num, r, i;
-	libusb_device **devs;
-	libusb_device_handle *devh = NULL;
-	ssize_t count;
-
-	memset(uep, 0, sizeof(*uep));
-
-	/* Must supply either serial or vendor and product ids. */
-	if (!serial && !(vid && pid))
-		goto terminate_usb_findit;
-
-	r = libusb_init(NULL);
-	if (r < 0) {
-		USB_ERROR("libusb_init", r);
-		goto terminate_usb_findit;
-	}
-
-	printf("finding_device ");
-	if (vid)
-		printf("%04x:%04x ", vid, pid);
-	if (serial)
-		printf("%s", serial);
-	printf("\n");
-
-	count = libusb_get_device_list(NULL, &devs);
-	if (count < 0)
-		goto terminate_usb_findit;
-
-	for (i = 0; i < count; i++) {
-		devh = check_device(devs[i], vid, pid, serial);
-		if (devh) {
-			printf("Found device.\n");
-			break;
-		}
-	}
-
-	libusb_free_device_list(devs, 1);
-
-	if (!devh) {
-		fprintf(stderr, "Can't find device\n");
-		goto terminate_usb_findit;
-	}
-	uep->devh = devh;
-
-	iface_num = find_interface(subclass, protocol, uep);
-	if (iface_num < 0) {
-		fprintf(stderr, "USB interface %d is not found\n", uep->ep_num);
-		goto terminate_usb_findit;
-	}
-	if (!uep->chunk_len) {
-		fprintf(stderr, "wMaxPacketSize isn't valid\n");
-		goto terminate_usb_findit;
-	}
-
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
-
-	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
-	r = libusb_claim_interface(uep->devh, iface_num);
-	if (r < 0) {
-		USB_ERROR("libusb_claim_interface", r);
-		goto terminate_usb_findit;
-	}
-
-	printf("READY\n-------\n");
-	return 0;
-
-terminate_usb_findit:
-	if (uep->devh)
-		usb_shut_down(uep);
-	return -1;
-}
-
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less, size_t *rxed_count)
-{
-
-	int r, actual;
-
-	/* Send data out */
-	if (outbuf && outlen) {
-		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
-					 &actual, 1000);
-		if (r < 0) {
-			USB_ERROR("libusb_bulk_transfer", r);
-			return -1;
-		}
-		if (actual != outlen) {
-			fprintf(stderr, "%s:%d, only sent %d/%d bytes\n",
-				__FILE__, __LINE__, actual, outlen);
-			usb_shut_down(uep);
-		}
-	}
-
-	/* Read reply back */
-	if (inbuf && inlen) {
-
-		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 1000);
-		if (r < 0) {
-			USB_ERROR("libusb_bulk_transfer", r);
-			return -1;
-		}
-		if ((actual != inlen) && !allow_less) {
-			fprintf(stderr, "%s:%d, only received %d/%d bytes\n",
-				__FILE__, __LINE__, actual, inlen);
-			usb_shut_down(uep);
-		}
-
-		if (rxed_count)
-			*rxed_count = actual;
-	}
-
-	return 0;
-}
-
-void usb_shut_down(struct usb_endpoint *uep)
-{
-	libusb_close(uep->devh);
-	libusb_exit(NULL);
-}
diff --git a/util/usb_if.h b/util/usb_if.h
deleted file mode 100644
index 8cc1088c6e..0000000000
--- a/util/usb_if.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_EXTRA_USB_UPDATER_USB_IF_H
-#define __EC_EXTRA_USB_UPDATER_USB_IF_H
-
-#include <libusb.h>
-
-/* This describes USB endpoint used to communicate with Cr50. */
-struct usb_endpoint {
-	struct libusb_device_handle *devh;
-	uint8_t ep_num;
-	int     chunk_len;
-};
-
-/*
- * Find the requested USB endpoint. This finds the device using the device
- * serial number, vendor id, and product id. The subclass and protocol are used
- * to find the correct endpoint. If a matching endpoint is found, fill up the
- * uep structure. If succeeded, usb_shut_down() must be invoked before program
- * exits.
- *
- * Return 0 on success, -1 on failure.
- */
-int usb_findit(const char *serialno, uint16_t vid, uint16_t pid,
-	       uint16_t subclass, uint16_t protocol, struct usb_endpoint *uep);
-
-/*
- * Actual USB transfer function, the 'allow_less' flag indicates that the
- * valid response could be shorter than allotted memory, the 'rxed_count'
- * pointer, if provided along with 'allow_less', lets the caller know how many
- * bytes were received.
- */
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less,
-	    size_t *rxed_count);
-
-/*
- * This function should be called for graceful tear down of the USB interface
- * when the program exits, either normally or due to error. This is required
- * only after USB connection was established, i.e. after successful invocation
- * of usb_findit().
- */
-void usb_shut_down(struct usb_endpoint *uep);
-
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
-
-#endif  /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */
diff --git a/util/uut/cmd.c b/util/uut/cmd.c
deleted file mode 100644
index 57cf75a29e..0000000000
--- a/util/uut/cmd.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file creates the UART Program Protocol API commands. */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "cmd.h"
-#include "lib_crc.h"
-#include "main.h"
-
- /* Extracting Byte - 8 bit: MSB, LSB */
-#define MSB(u16) ((uint8_t)((uint16_t)(u16) >> 8))
-#define LSB(u16) ((uint8_t)(u16))
-
-/*----------------------------------------------------------------------------
- *  SPI Flash commands
- *---------------------------------------------------------------------------
- */
-
-#define SPI_READ_JEDEC_ID_CMD 0x9F
-#define SPI_WRITE_ENABLE_CMD 0x06
-#define SPI_WRITE_DISABLE_CMD 0x04
-#define SPI_READ_STATUS_REG_CMD 0x05
-#define SPI_WRITE_STATUS_REG_CMD 0x01
-#define SPI_READ_DATA_CMD 0x03
-#define SPI_PAGE_PRGM_CMD 0x02
-#define SPI_SECTOR_ERASE_CMD 0xD8
-#define SPI_BULK_ERASE_CMD 0xC7
-#define SPI_READ_PID_CMD 0x90
-
-union cmd_addr {
-	uint8_t c_adr[4];
-	uint32_t h_adr;
-};
-
-/*----------------------------------------------------------------------------
- * Function implementation
- *---------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_sync
- *
- * Parameters:	   cmd_info - Pointer to a command buffer.
- *		   cmd_len  - Pointer to command length.
- * Returns:	   none.
- * Side effects:
- * Description:
- *		Create a Host to Device SYNC protocol command.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_H2D_SYNC_CMD;
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*---------------------------------------------------------------------------
- * Function:       cmd_create_write
- *
- * Parameters:	addr    - Memory address to write to.
- *		size    - Size of daya (in bytes) to write to memory.
- *		data_buf - Pointer to data buffer containing raw data to write.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:     none.
- * Side effects:
- * Description:
- *	Create a WRITE protocol command.
- *	The command buffer is enclosed by CRC, calculated on command
- *	information and raw data.
- *	The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_WRITE_CMD;
-	cmd_info[len++] = (uint8_t)(size - 1);
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Insert data */
-	memcpy(&cmd_info[len], data_buf, size);
-	len += size;
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_read
- *
- * Parameters:	addr    - Memory address to read from.
- *		size    - Size of daya (in bytes) to read from memory.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Create a READ protocol command.
- *		The command buffer is enclosed by CRC, calculated on command
- *		information and raw data.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_READ_CMD;
-	cmd_info[len++] = (uint8_t)size;
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_create_exec
- *
- * Parameters:	addr    - Memory address to execute from.
- *		cmd_info - Pointer to a command buffer.
- *		cmd_len  - Pointer to command length.
- * Returns:     none.
- * Side effects:
- * Description:
- *		Create an FCALL protocol command.
- *		The command buffer is enclosed by CRC, calculated on command
- *		information and raw data.
- *		The total command length is written to 'cmd_len'.
- *---------------------------------------------------------------------------
- */
-void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len)
-{
-	uint32_t i;
-	union cmd_addr adr_tr;
-	uint16_t crc = 0;
-	uint32_t len = 0;
-
-	/* Build the command buffer */
-	cmd_info[len++] = UFPP_FCALL_CMD;
-	cmd_info[len++] = 0;
-
-	/* Insert Address */
-	adr_tr.h_adr = addr;
-	cmd_info[len++] = adr_tr.c_adr[3];
-	cmd_info[len++] = adr_tr.c_adr[2];
-	cmd_info[len++] = adr_tr.c_adr[1];
-	cmd_info[len++] = adr_tr.c_adr[0];
-
-	/* Calculate CRC */
-	for (i = 0; i < len; i++)
-		crc = update_crc(crc, (char)cmd_info[i]);
-
-	/* Insert CRC */
-	cmd_info[len++] = MSB(crc);
-	cmd_info[len++] = LSB(crc);
-
-	/* Return total command length */
-	*cmd_len = len;
-}
-
-/*---------------------------------------------------------------------------
- * Function:        cmd_build_sync
- *
- * Parameters:	cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Description:
- *		Build a synchronization command buffer.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_sync(cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 1;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_build_exec_exit
- *
- * Parameters:	addr   - Memory address to execute from.
- *		cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Build an Excute command buffer.
- *		Command does not expect the executed code to return, that is,
- *		only FCALL protocol
- *		command code is expected.
- *		Determine the expected response size per each command.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 1;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_build_exec_ret
- *
- * Parameters:	addr   - Memory address to execute from.
- *		cmd_buf - Pointer to a command buffer.
- *		cmd_num - Pointer to command number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Build an Excute command buffer.
- *		Command expects the executed code to return, that is,
- *		FCALL_RSLT protocol command
- *		code is expected, together with the execution result.
- *		Determine the expected response size per each command.
- *		The total command number is written to 'cmd_num'.
- *---------------------------------------------------------------------------
- */
-void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
-{
-	uint32_t cmd = 0;
-
-	cmd_create_exec(addr, cmd_buf[cmd].cmd, &cmd_buf[cmd].cmd_size);
-	cmd_buf[cmd].resp_size = 3;
-	cmd++;
-
-	*cmd_num = cmd;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_sync
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display SYNC command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_sync(uint8_t *resp_buf)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_D2H_SYNC_CMD)) {
-		display_color_msg(SUCCESS, "Host/Device are synchronized\n");
-		return true;
-	}
-
-	display_color_msg(FAIL, "Host/Device synchronization failed!!!\n");
-	return false;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_write
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- *		resp_size - Response size.
- *		resp_num - Response packet number.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display WRITE command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					  uint32_t total_size)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"\rTransmitted packet of size %u bytes, packet "
-			"[%u]out of [%u]",
-			resp_size, resp_num, total_size);
-		return true;
-	}
-
-	display_color_msg(FAIL, "\nWrite packet [%lu] Failed\n", resp_num);
-	return false;
-}
-
-/*-----------------------------------------------------------------------------
- * Function:	cmd_disp_read
- *
- * Parameters:	resp_buf  - Pointer to a response buffer.
- *		resp_size - Response size.
- *		resp_num  - Response packet number.
- * Returns:	TRUE if successful, FALSE in the case of an error.
- * Side effects:
- * Description:
- *		Display READ command response information.
- *---------------------------------------------------------------------------
- */
-bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
-		display_color_msg(SUCCESS,
-			"\rReceived packet of size %u bytes, packet [%u] out "
-			"of [%u]",
-			resp_size, resp_num, total_size);
-		return true;
-	}
-
-	display_color_msg(FAIL, "\nRead packet [%u] Failed\n", resp_num);
-	return false;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_data
- *
- * Parameters:	resp_buf  - Pointer to a response buffer.
- *		resp_size - Response size.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display raw data, read from memory.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size)
-{
-	uint32_t idx;
-	uint32_t i;
-
-	for (idx = 0; idx < resp_size; idx += 4) {
-		if ((idx % 16) == 0)
-			printf("\n");
-
-		printf("0x");
-		for (i = 4; i > 0; i--)
-			printf("%02x", resp_buf[idx + i - 1]);
-
-		if ((idx % 4) == 0)
-			printf(" ");
-	}
-
-	printf("\n");
-}
-
-/*----------------------------------------------------------------------------
- * Function:	cmd_disp_flash_erase_dev
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- *		dev_num  - Flash Device Number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display BULK_ERASE command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"Flash Erase of device [%u] Passed\n", dev_num);
-	} else {
-		display_color_msg(
-			FAIL, "Flash Erase of device [%u] Failed\n", dev_num);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_flash_erase_sect
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display BULK_ERASE command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
-			"Sector Erase of device [%lu] Passed\n", dev_num);
-	} else {
-		display_color_msg(
-			FAIL, "Sector Erase of device [%lu] Failed\n", dev_num);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_exec_exit
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display Execute command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_exec_exit(uint8_t *resp_buf)
-{
-	if (resp_buf[0] == (uint8_t)(UFPP_FCALL_CMD))
-		display_color_msg(SUCCESS, "Execute Command Passed\n");
-	else
-		display_color_msg(FAIL, "Execute Command Failed\n");
-}
-
-/*---------------------------------------------------------------------------
- * Function:	cmd_disp_exec_ret
- *
- * Parameters:	resp_buf - Pointer to a response buffer.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Display Execute Result command response information.
- *---------------------------------------------------------------------------
- */
-void cmd_disp_exec_ret(uint8_t *resp_buf)
-{
-	if (resp_buf[1] == (uint8_t)(UFPP_FCALL_RSLT_CMD)) {
-		display_color_msg(SUCCESS,
-			"Execute Command Passed, execution result is [0x%X]\n",
-			resp_buf[2]);
-	} else {
-		display_color_msg(FAIL,
-			"Execute Command Failed  [0x%X]  [0x%X], rslt=[0x%X]\n",
-			resp_buf[0], resp_buf[1], resp_buf[2]);
-	}
-}
diff --git a/util/uut/cmd.h b/util/uut/cmd.h
deleted file mode 100644
index 44cebbe989..0000000000
--- a/util/uut/cmd.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __UTIL_UUT_CMD_H
-#define __UTIL_UUT_CMD_H
-
-#include <stdbool.h>
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-#define MAX_CMD_BUF_SIZE 10
-#define MAX_RESP_BUF_SIZE 512
-
-enum uart_protocol_cmd {
-	UFPP_H2D_SYNC_CMD = 0x55,   /* Single-Byte Host to Device	 */
-				    /* synchronization command	 */
-	UFPP_D2H_SYNC_CMD = 0x5A,   /* Single-Byte Device to Host	 */
-				    /* synchronization response	 */
-	UFPP_WRITE_CMD = 0x07,      /* Write command and response	 */
-	UFPP_READ_CMD = 0x1C,       /* Read command and response	 */
-	UFPP_READ_CRC_CMD = 0x89,   /* Read CRC command and response */
-	UFPP_FCALL_CMD = 0x70,      /* Call function command	 */
-	UFPP_FCALL_RSLT_CMD = 0x73, /* Call function response	 */
-	UFPP_SPI_CMD = 0x92,        /* SPI specific command		 */
-	UFPP_ERROR_CMD = 0xFF       /* Error response		 */
-};
-
-struct command_node {
-	uint8_t cmd[512];
-	uint32_t cmd_size;
-	uint32_t resp_size;
-};
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len);
-void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len);
-void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len);
-void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len);
-
-void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num);
-void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
-void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
-
-bool cmd_disp_sync(uint8_t *resp_buf);
-bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
-bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
-void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size);
-void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num);
-void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num);
-void cmd_disp_exec_exit(uint8_t *resp_buf);
-void cmd_disp_exec_ret(uint8_t *resp_buf);
-
-#endif /* __UTIL_UUT_CMD_H */
diff --git a/util/uut/com_port.h b/util/uut/com_port.h
deleted file mode 100644
index 36331f2fb6..0000000000
--- a/util/uut/com_port.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file defines the ComPort interface header file. */
-
-#ifndef __UTIL_UUT_COM_PORT_H
-#define __UTIL_UUT_COM_PORT_H
-
-#include <stdbool.h>
-#include <termios.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*---------------------------------------------------------------------------
- *                                      ComPort INTERFACE
- *---------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-#define INVALID_HANDLE_VALUE -1
-
-/*---------------------------------------------------------------------------
- * Type definitions
- *---------------------------------------------------------------------------
- */
-#define COMP_PORT_PREFIX_1 "ttyS"
-#define COMP_PORT_PREFIX_2 "ttyUSB"
-#define COMP_PORT_PREFIX_3 "pts"
-
-struct comport_fields {
-	uint32_t baudrate;    /* Baudrate at which running               */
-	tcflag_t byte_size;   /* Number of bits/byte, 4-8                */
-	tcflag_t parity;       /* 0-4=None,Odd,Even,Mark,Space            */
-	uint8_t stop_bits;    /* 0,1,2 = 1, 1.5, 2                       */
-	uint8_t flow_control; /* 0-none, 1-SwFlowControl,2-HwFlowControl */
-};
-
-/*---------------------------------------------------------------------------
- * Function: int com_port_open()
- *
- * Purpose:  Open the specified ComPort device.
- *
- *  Params:   com_port_dev_name - The name of the device to open
- *           com_port_fields - a struct filled with Comport settings, see
- *                           definition above.
- *
- * Returns:  INVALID_HANDLE_VALUE (-1) - invalid handle.
- *           Other value - Handle to be used in other Comport APIs
- *
- * Comments: The returned handle can be used for other Win32 API communication
- *           function by casting it to HANDLE.
- *
- *---------------------------------------------------------------------------
- */
-int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields);
-
-/*---------------------------------------------------------------------------
- * Function: int com_config_uart()
- *
- * Purpose:  Configures the Uart port properties.
- *
- * Params:   h_dev_drv - the opened handle returned by com_port_open()
- *           com_port_fields - a struct filled with Comport settings, see
- *                           definition above.
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- *---------------------------------------------------------------------------
- */
-bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields);
-
-/*---------------------------------------------------------------------------
- * Function: bool ComPortClose()
- *
- * Purpose:  Close the ComPort device specified by Handle
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- *---------------------------------------------------------------------------
- */
-bool com_port_close(int device_id);
-
-/*---------------------------------------------------------------------------
- * Function: bool com_port_write_bin()
- *
- * Purpose:  Send binary data through Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - contains the binary data to send
- *           buf_size - the size of data to send
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- * Comments: The caller must ensure that buf_size is not bigger than
- *           Buffer size.
- *
- *---------------------------------------------------------------------------
- */
-bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size);
-
-/*---------------------------------------------------------------------------
- * Function: uint32_t com_port_read_bin()
- *
- * Purpose:  Read a binary data from Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - this buffer will contain the arrived data
- *           buf_size - maximum data size to read
- *
- * Returns:  The number of bytes read.
- *
- * Comments: The caller must ensure that Size is not bigger than Buffer size.
- *
- *---------------------------------------------------------------------------
- */
-uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size);
-
-/*---------------------------------------------------------------------------
- * Function: uint32_t com_port_wait_read()
- *
- * Purpose:  Wait until a byte is received for read
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  The number of bytes that are waiting in RX queue.
- *
- *---------------------------------------------------------------------------
- */
-uint32_t com_port_wait_read(int device_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __UTIL_UUT_COM_PORT_H */
diff --git a/util/uut/l_com_port.c b/util/uut/l_com_port.c
deleted file mode 100644
index 018dec9950..0000000000
--- a/util/uut/l_com_port.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <poll.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-#include <sys/ioctl.h>
-#include <termios.h>
-#include <unistd.h>
-
-#include "com_port.h"
-#include "main.h"
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-#define INBUFSIZE 2048
-#define OUTBUFSIZE 2048
-#define LOWER_THRESHOLD 16
-#define UPPER_THRESHOLD 512
-#define XOFF_CHAR 0x13
-#define XON_CHAR 0x11
-
-#define UART_FIFO_SIZE 16
-
-#define COMMAND_TIMEOUT 10000 /* 10 seconds */
-
-/*---------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-static struct termios savetty;
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-/*--------------------------------------------------------------------------
- * Local Function implementation
- *--------------------------------------------------------------------------
- */
-
-/*--------------------------------------------------------------------------
- * Function:	convert_baudrate_to_baudrate_mask
- *
- * Parameters:
- *		baudrate - Bauderate value.
- *
- * Returns:	Baudrate mask.
- * Side effects:
- * Description:
- *		This routine convert from baudrate mode to paudrate mask.
- *--------------------------------------------------------------------------
- */
-static speed_t convert_baudrate_to_baudrate_mask(uint32_t baudrate)
-{
-	switch (baudrate) {
-	case 9600:
-		return B9600;
-	case 19200:
-		return B19200;
-	case 38400:
-		return B38400;
-	case 57600:
-		return B57600;
-	case 115200:
-		return B115200;
-	default:
-		return B0;
-	}
-}
-
-/*-------------------------------------------------------------------------
- * Function:	set_read_blocking
- *
- * Parameters:
- *		dev_drv	- The opened handle returned by com_port_open()
- *		block		- TRUE means read in blocking mode
- *				  FALSE means read in non-blocking mode.
- *
- * Returns:	none
- * Side effects:
- * Description:
- *		This routine set/unset read blocking mode.
- *--------------------------------------------------------------------------
- */
-void set_read_blocking(int dev_drv, bool block)
-{
-	struct termios tty;
-
-	memset(&tty, 0, sizeof(tty));
-
-	if (tcgetattr(dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
-			"set_read_blocking Error: %d Fail to get attribute "
-			"from Device number %d.\n",
-			errno, dev_drv);
-		return;
-	}
-
-	tty.c_cc[VMIN] = block;
-	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */
-
-	if (tcsetattr(dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
-			"set_read_blocking Error: %d Fail to set attribute to "
-			"Device number %d.\n",
-			errno, dev_drv);
-	}
-}
-
-/*--------------------------------------------------------------------------
- * Global Function implementation
- *--------------------------------------------------------------------------
- */
-
-/******************************************************************************
- * Function: int com_config_uart()
- *
- * Purpose:  Configures the Uart port properties.
- *
- * Params:   h_dev_drv - the opened handle returned by com_port_open()
- *	    com_port_fields  - a struct filled with Comport settings, see
- *			     definition above.
- *
- * Returns:  1 if successful
- *	    0 in the case of an error.
- *
- *****************************************************************************
- */
-bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
-{
-	struct termios tty;
-	speed_t baudrate;
-
-	memset(&tty, 0, sizeof(tty));
-
-	if (tcgetattr(h_dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
-			"com_config_uart Error: Fail to get attribute from "
-			"Device number %d.\n",
-			h_dev_drv);
-		return false;
-	}
-
-	baudrate = convert_baudrate_to_baudrate_mask(com_port_fields.baudrate);
-	cfsetospeed(&tty, baudrate);
-	cfsetispeed(&tty, baudrate);
-
-	tty.c_cflag |= baudrate;
-
-	tty.c_cflag |= com_port_fields.byte_size;
-
-	/*
-	 * disable IGNBRK for mismatched speed tests; otherwise receive break
-	 * as \000 chars
-	 */
-
-	/* Set port to be in a "raw" mode. */
-	tty.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR |
-			 ICRNL | IXON);
-	tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
-
-	tty.c_oflag = ~OPOST;
-	tty.c_cc[VMIN] = 0;  /* read doesn't block		*/
-	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout	*/
-
-	tty.c_iflag |= (com_port_fields.flow_control == 0x01)
-			       ? (IXON | IXOFF)
-			       : 0x00; /* xon/xoff ctrl */
-
-	tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */
-	/* enable reading */
-	tty.c_cflag &= ~(PARENB | PARODD); /* shut off parity */
-	tty.c_cflag |= com_port_fields.parity;
-	/* Stop bits */
-	tty.c_cflag |= (com_port_fields.stop_bits == 0x02) ? CSTOPB : 0x00;
-	/* HW flow control */
-	tty.c_cflag |= (com_port_fields.flow_control == 0x02) ? CRTSCTS : 0x00;
-
-	/* Flush Port, then applies attributes */
-	tcflush(h_dev_drv, TCIFLUSH);
-
-	if (tcsetattr(h_dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
-			"com_config_uart Error: %d setting port handle %d: %s.\n",
-			errno, h_dev_drv, strerror(errno));
-		return false;
-	}
-
-	return true;
-}
-
-/**
- * Drain the console RX buffer before programming. The device should be in
- * programming mode and shouldn't be printing anything. Anything that's
- * currently in the buffer could interfere with programming. discard_input
- * will discard everything currently in the buffer. It prints any non zero
- * characters and returns when the console is empty and ready for programming.
- *
- * This is the same as discard_input in stm32mon.
- * TODO: create common library for initializing serial consoles.
- */
-static void discard_input(int fd)
-{
-	uint8_t buffer[64];
-	int res, i;
-	int count_of_zeros;
-
-	/* Keep track of discarded zeros */
-	count_of_zeros = 0;
-	do {
-		res = read(fd, buffer, sizeof(buffer));
-		if (res > 0) {
-
-			/* Discard zeros in the beginning of the buffer. */
-			for (i = 0; i < res; i++)
-				if (buffer[i])
-					break;
-
-			count_of_zeros += i;
-			if (i == res) {
-				/* Only zeros, nothing to print out. */
-				continue;
-			}
-
-			/* Discard zeros in the end of the buffer. */
-			while (!buffer[res - 1]) {
-				count_of_zeros++;
-				res--;
-			}
-
-			printf("Recv[%d]:", res - i);
-			for (; i < res; i++)
-				printf("%02x ", buffer[i]);
-			printf("\n");
-		}
-	} while (res > 0);
-
-	if (count_of_zeros)
-		printf("%d zeros ignored\n", count_of_zeros);
-}
-
-
-/******************************************************************************
- * Function: int com_port_open()
- *
- * Purpose:  Open the specified ComPort device and return its handle.
- *
- * Params:   com_port_dev_name - The name of the device to open
- *           com_port_fields - a struct filled with Comport settings
- *
- * Returns:  INVALID_HANDLE_VALUE (-1) - invalid handle.
- *           Other value - Handle to be used in other Comport APIs
- *
- * Comments: The returned handle can be used for other Win32 API communication
- *           function.
- *
- *****************************************************************************
- */
-int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields)
-{
-	int port_handler;
-
-	port_handler = open(com_port_dev_name, O_RDWR | O_NOCTTY);
-
-	if (port_handler < 0) {
-		display_color_msg(FAIL,
-				"com_port_open Error %d opening %s: %s\n",
-				errno, com_port_dev_name, strerror(errno));
-		return INVALID_HANDLE_VALUE;
-	}
-
-	tcgetattr(port_handler, &savetty);
-
-	if (!com_config_uart(port_handler, com_port_fields)) {
-		display_color_msg(FAIL,
-			"com_port_open() Error %d, Failed on com_config_uart() %s, "
-			"%s\n",
-			errno, com_port_dev_name, strerror(errno));
-		close(port_handler);
-		return INVALID_HANDLE_VALUE;
-	}
-
-	/*
-	 * Drain the console, so what ever is already in the EC console wont
-	 * interfere with programming.
-	 */
-	discard_input(port_handler);
-
-	return port_handler;
-}
-
-/******************************************************************************
- * Function: com_port_close()
- *
- * Purpose:  Close the ComPort device specified by Handle
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- *****************************************************************************
- */
-bool com_port_close(int device_id)
-{
-	tcsetattr(device_id, TCSANOW, &savetty);
-
-	if (close(device_id) == INVALID_HANDLE_VALUE) {
-		display_color_msg(FAIL,
-			"com_port_close() Error: %d Device com%u was not opened, "
-			"%s.\n",
-			errno, (uint32_t)device_id, strerror(errno));
-		return false;
-	}
-
-	return true;
-}
-
-/******************************************************************************
- * Function: com_port_write_bin()
- *
- * Purpose:  Send binary data through Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - contains the binary data to send
- *           buf_size - the size of data to send
- *
- * Returns:  1 if successful
- *           0 in the case of an error.
- *
- * Comments: The caller must ensure that buf_size is not bigger than
- *           buffer size.
- *
- *****************************************************************************
- */
-bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size)
-{
-	uint32_t bytes_written;
-
-	bytes_written = write(device_id, buffer, buf_size);
-	if (bytes_written != buf_size) {
-		display_color_msg(FAIL,
-			"com_port_write_bin() Error: %d  Failed to write data to "
-			"Uart Port %d, %s.\n",
-			errno, (uint32_t)device_id, strerror(errno));
-
-		return false;
-	}
-
-	return true;
-}
-
-/******************************************************************************
- * Function: uint32_t com_port_read_bin()
- *
- * Purpose:  Read a binary data from Comport
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *           buffer - this buffer will contain the arrived data
- *           buf_size - maximum data size to read
- *
- * Returns:  The number of bytes read.
- *
- * Comments: The caller must ensure that Size is not bigger than buffer size.
- *
- *****************************************************************************
- */
-uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size)
-{
-	int32_t read_bytes;
-
-	/* Reset read blocking mode */
-	set_read_blocking(device_id, false);
-
-	read_bytes = read(device_id, buffer, buf_size);
-
-	if (read_bytes == -1) {
-		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u was not "
-			"opened, %s.\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
-	}
-
-	return read_bytes;
-}
-
-/******************************************************************************
- * Function: uint32_t com_port_wait_read()
- *
- * Purpose:  Wait until a byte is received for read
- *
- * Params:   device_id - the opened handle returned by com_port_open()
- *
- * Returns:  The number of bytes that are waiting in RX queue.
- *
- *****************************************************************************
- */
-uint32_t com_port_wait_read(int device_id)
-{
-	int32_t bytes;
-	int32_t ret_val;
-	struct pollfd fds;
-
-	/* Set read blocking mode */
-	set_read_blocking(device_id, true);
-
-	/* Wait up to 10 sec until byte is received for read. */
-	fds.fd = device_id;
-	fds.events = POLLIN;
-	ret_val = poll(&fds, 1, COMMAND_TIMEOUT);
-	if (ret_val < 0) {
-		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u %s\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
-		return 0;
-	}
-
-	bytes = 0;
-
-	/* If data is ready for read. */
-	if (ret_val > 0) {
-		/* Get number of bytes that are ready to be read. */
-		if (ioctl(device_id, FIONREAD, &bytes) < 0) {
-			display_color_msg(FAIL,
-				"com_port_wait_for_read() Error: %d Device number "
-				"%u %s\n",
-				errno, (uint32_t)device_id, strerror(errno));
-			return 0;
-		}
-	}
-
-	return bytes;
-}
diff --git a/util/uut/lib_crc.c b/util/uut/lib_crc.c
deleted file mode 100644
index 176e91327c..0000000000
--- a/util/uut/lib_crc.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The file lib_crc.c contains the  functions used for the calculation of
- * CRC-16 cyclic redundancy values.
- */
-
-#include "lib_crc.h"
-
-/*********************************************************************
- *                                                                   *
- *   Library         : lib_crc                                       *
- *   File            : lib_crc.c                                     *
- *   Author          : Lammert Bies  1999-2005                       *
- *   E-mail          : info@lammertbies.nl                           *
- *   Language        : ANSI C                                        *
- *                                                                   *
- *                                                                   *
- *   Description                                                     *
- *   ===========                                                     *
- *                                                                   *
- *   The file lib_crc.c contains the private  and  public  func-     *
- *   tions  used  for  the  calculation of CRC-16, CRC-CCITT and     *
- *   CRC-32 cyclic redundancy values.                                *
- *                                                                   *
- *                                                                   *
- *   Dependencies                                                    *
- *   ============                                                    *
- *                                                                   *
- *   lib_crc.h       CRC definitions and prototypes                  *
- *                                                                   *
- *                                                                   *
- *   Modification history                                            *
- *   ====================                                            *
- *                                                                   *
- *   Date        Version Comment                                     *
- *                                                                   *
- *   2005-05-14  1.12    Added CRC-CCITT with start value 0          *
- *                                                                   *
- *   2005-02-05  1.11    Fixed bug in CRC-DNP routine                *
- *                                                                   *
- *   2005-02-04  1.10    Added CRC-DNP routines                      *
- *                                                                   *
- *   1999-02-21  1.01    Added FALSE and TRUE mnemonics              *
- *                                                                   *
- *   1999-01-22  1.00    Initial source                              *
- *                                                                   *
- *********************************************************************
- */
-
-/* CRC16 lookup table for polynom 0xA001 */
-static const unsigned short crc16_tab[256] = {
-	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
-	0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
-	0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
-	0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
-	0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
-	0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
-	0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
-	0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
-	0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
-	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
-	0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
-	0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
-	0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
-	0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
-	0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
-	0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
-	0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
-	0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
-	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
-	0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
-	0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
-	0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
-	0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
-	0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
-	0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
-	0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
-	0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
-	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
-	0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
-	0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
-	0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
-	0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
-};
-
-/*********************************************************************
- *                                                                   *
- *   unsigned short update_crc( unsigned long crc, unsigned char c ) *
- *                                                                   *
- *   The function update_crc calculates a  new  CRC-16  value        *
- *   based  on  the  previous value of the CRC and the next byte     *
- *   of the data to be checked.                                      *
- *                                                                   *
- *********************************************************************
- */
-unsigned short update_crc(unsigned short crc, unsigned char c)
-{
-	unsigned short tmp;
-
-	tmp = crc ^ (0x00ff & (unsigned short)c);
-	crc = (crc >> 8) ^ crc16_tab[tmp & 0xff];
-
-	return crc;
-}
diff --git a/util/uut/lib_crc.h b/util/uut/lib_crc.h
deleted file mode 100644
index 58db81c4e5..0000000000
--- a/util/uut/lib_crc.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This file contains public definitions and prototypes for the CRC functions.
- */
-
-#ifndef __UTIL_UUT_LIB_CRC_H
-#define __UTIL_UUT_LIB_CRC_H
-
-/*-------------------------------------------------------------------*\
- *                                                                   *
- *   Library         : lib_crc                                       *
- *   File            : lib_crc.h                                     *
- *   Author          : Lammert Bies  1999-2005                       *
- *   E-mail          : info@lammertbies.nl                           *
- *   Language        : ANSI C                                        *
- *                                                                   *
- *                                                                   *
- *   Description                                                     *
- *   ===========                                                     *
- *                                                                   *
- *   The file lib_crc.h contains public definitions  and  proto-     *
- *   types for the CRC functions present in lib_crc.c.               *
- *                                                                   *
- *                                                                   *
- *   Dependencies                                                    *
- *   ============                                                    *
- *                                                                   *
- *   none                                                            *
- *                                                                   *
- *                                                                   *
- *   Modification history                                            *
- *   ====================                                            *
- *                                                                   *
- *   Date        Version Comment                                     *
- *                                                                   *
- *   2005-02-14  1.12    Added CRC-CCITT with initial value 0        *
- *                                                                   *
- *   2005-02-05  1.11    Fixed bug in CRC-DNP routine                *
- *                                                                   *
- *   2005-02-04  1.10    Added CRC-DNP routines                      *
- *                                                                   *
- *   2005-01-07  1.02    Changes in tst_crc.c                        *
- *                                                                   *
- *   1999-02-21  1.01    Added FALSE and TRUE mnemonics              *
- *                                                                   *
- *   1999-01-22  1.00    Initial source                              *
- *                                                                   *
- *-------------------------------------------------------------------*
- */
-
-/*---------------------------------------------------------------------------
- * CRC library constant definitions
- *---------------------------------------------------------------------------
- */
-#define CRC_VERSION "1.12"
-
-/*---------------------------------------------------------------------------
- * CRC library API
- *---------------------------------------------------------------------------
- */
-unsigned short update_crc(unsigned short crc, unsigned char c);
-
-#endif /* __UTIL_UUT_LIB_CRC_H */
diff --git a/util/uut/main.c b/util/uut/main.c
deleted file mode 100644
index 146ddc0275..0000000000
--- a/util/uut/main.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <errno.h>
-#include <getopt.h>
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/stat.h>
-
-#include "com_port.h"
-#include "compile_time_macros.h"
-#include "main.h"
-#include "misc_util.h"
-#include "opr.h"
-
-/*----------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-#define MAX_FILE_NAME_SIZE 512
-#define MAX_PARAM_SIZE 32
-#define MAX_MSG_SIZE 128
-#define MAX_SYNC_RETRIES 3
-
-/* Default values */
-#define DEFAULT_BAUD_RATE 115200
-#define DEFAULT_PORT_NAME "ttyS0"
-#define DEFAULT_DEV_NUM 0
-#define DEFAULT_FLASH_OFFSET 0
-
-/* The magic number in monitor header */
-#define MONITOR_HDR_TAG        0xA5075001
-/* The location of monitor header */
-#define MONITOR_HDR_ADDR       0x200C3000
-/* The start address of the monitor little firmware to execute */
-#define MONITOR_ADDR           0x200C3020
-/* The start address to store the firmware segment to be programmed */
-#define FIRMWARE_START_ADDR    0x10090000
-/* Divide the ec firmware image into 4K byte */
-#define FIRMWARE_SEGMENT       0x1000
-/* Register address for chip ID */
-#define NPCX_SRID_CR           0x400C101C
-/* Register address for device ID */
-#define NPCX_DEVICE_ID_CR      0x400C1022
-#define NPCX_FLASH_BASE_ADDR   0x64000000
-
-/*---------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-bool verbose;
-bool console;
-struct comport_fields port_cfg;
-
-/*---------------------------------------------------------------------------
- * Local variables
- *---------------------------------------------------------------------------
- */
-
-static const char tool_name[] = {"LINUX UART Update Tool"};
-static const char tool_version[] = {"2.0.1"};
-
-static char port_name[MAX_PARAM_SIZE];
-static char opr_name[MAX_PARAM_SIZE];
-static char file_name[MAX_FILE_NAME_SIZE];
-static char addr_str[MAX_PARAM_SIZE];
-static char size_str[MAX_PARAM_SIZE];
-static uint32_t baudrate;
-static uint32_t dev_num;
-static uint32_t flash_offset;
-static bool auto_mode;
-static bool read_flash_flag;
-
-struct npcx_chip_info {
-	uint8_t device_id;
-	uint8_t chip_id;
-	uint32_t flash_size;
-};
-
-const static struct npcx_chip_info chip_info[] = {
-	{
-		/* NPCX796FA */
-		.device_id = 0x21,
-		.chip_id = 0x06,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX796FB */
-		.device_id = 0x21,
-		.chip_id = 0x07,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX796FC */
-		.device_id = 0x29,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX797FC */
-		.device_id = 0x20,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX797WB */
-		.device_id = 0x24,
-		.chip_id = 0x07,
-		.flash_size = 1024 * 1024,
-	},
-
-	{
-		/* NPCX797WC */
-		.device_id = 0x2C,
-		.chip_id = 0x07,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX993F */
-		.device_id = 0x25,
-		.chip_id = 0x09,
-		.flash_size = 512 * 1024,
-	},
-
-	{
-		/* NPCX996F */
-		.device_id = 0x21,
-		.chip_id = 0x09,
-		.flash_size = 512 * 1024,
-	},
-};
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-static void param_parse_cmd_line(int argc, char *argv[]);
-static void param_check_opr_num(const char *opr);
-static uint32_t param_get_file_size(const char *file_name);
-static uint32_t param_get_str_size(char *string);
-static void main_print_version(void);
-static void tool_usage(void);
-static void exit_uart_app(int32_t exit_status);
-
-enum EXIT_CODE {
-	EC_OK = 0x00,
-	EC_PORT_ERR = 0x01,
-	EC_BAUDRATE_ERR = 0x02,
-	EC_SYNC_ERR = 0x03,
-	EC_DEV_NUM_ERR = 0x04,
-	EC_OPR_MUM_ERR = 0x05,
-	EC_ALIGN_ERR = 0x06,
-	EC_FILE_ERR = 0x07,
-	EC_UNSUPPORTED_CMD_ERR = 0x08
-};
-
-/*---------------------------------------------------------------------------
- * Function implementation
- *---------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------
- * Function:	image_auto_write
- *
- * Parameters:    offset - The start address of the flash to write the firmware
- *                         to.
- *                buffer - The buffer holds data of the firmware.
- *                file_size - the size to be programmed.
- * Returns:       1 for a successful operation, 0 otherwise.
- * Side effects:
- * Description:
- *               Divide the firmware to segments and program them one by one.
- *---------------------------------------------------------------------------
- */
-static bool image_auto_write(uint32_t offset, uint8_t *buffer,
-				uint32_t file_size)
-{
-	uint32_t data_buf[4];
-	uint32_t addr, chunk_remain, file_seg, flash_index, seg;
-	uint32_t count, percent, total;
-	uint32_t i;
-
-	flash_index = offset;
-	/* Monitor tag */
-	data_buf[0] = MONITOR_HDR_TAG;
-
-	file_seg = file_size;
-	total = 0;
-	while (file_seg) {
-		seg = (file_seg > FIRMWARE_SEGMENT) ?
-					FIRMWARE_SEGMENT : file_seg;
-		/*
-		 * Check if the content of the segment is all 0xff.
-		 * If yes, there is no need to write.
-		 * Call the monitor to erase the segment only for
-		 * time efficiency.
-		 */
-		for (i = 0; i < seg && buffer[i] == 0xFF; i++)
-			;
-		if (i == seg) {
-			data_buf[1] = seg;
-			/*
-			 * Set src_addr = 0 as a flag. When the monitor read 0
-			 * from this field, it will do sector erase only.
-			 */
-			data_buf[2] = 0;
-			data_buf[3] = flash_index;
-			opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
-			if (opr_execute_return(MONITOR_ADDR) != true)
-				return false;
-			file_seg -= seg;
-			flash_index += seg;
-			buffer += seg;
-			total += seg;
-			percent = total * 100 / file_size;
-			printf("\r[%d%%] %d/%d", percent, total, file_size);
-			fflush(stdout);
-			continue;
-		}
-		chunk_remain = seg;
-		addr = FIRMWARE_START_ADDR;
-		/* the size to be programmed */
-		data_buf[1] = seg;
-		/* The source(RAM) address where the firmware is stored. */
-		data_buf[2] = FIRMWARE_START_ADDR;
-		/*
-		 * The offset of the flash where the segment to be programmed.
-		 */
-		data_buf[3] = flash_index;
-		/* Write the monitor header to RAM */
-		opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
-		while (chunk_remain) {
-			count = (chunk_remain > MAX_RW_DATA_SIZE) ?
-						MAX_RW_DATA_SIZE : chunk_remain;
-			if (opr_write_chunk(buffer, addr, count) != true)
-				return false;
-
-			addr += count;
-			buffer += count;
-			chunk_remain -= count;
-			total += count;
-			percent = total * 100 / file_size;
-			printf("\r[%d%%] %d/%d", percent, total, file_size);
-		}
-		fflush(stdout);
-		if (opr_execute_return(MONITOR_ADDR) != true)
-			return false;
-		file_seg -= seg;
-		flash_index += seg;
-	}
-	printf("\n");
-	/* Clear the UUT header tag */
-	data_buf[0] = 0;
-	opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR, 4);
-	return true;
-}
-
-static bool get_flash_size(uint32_t *flash_size)
-{
-	uint8_t dev_id, chip_id, i;
-
-	if (opr_read_chunk(&dev_id, NPCX_DEVICE_ID_CR, 1) != true)
-		return false;
-
-	if (opr_read_chunk(&chip_id, NPCX_SRID_CR, 1) != true)
-		return false;
-
-	for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
-		if (chip_info[i].device_id == dev_id &&
-				chip_info[i].chip_id == chip_id) {
-			*flash_size = chip_info[i].flash_size;
-			return true;
-		}
-	}
-	printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n",
-				dev_id, chip_id);
-
-	return false;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	read_input_file
- *
- * Parameters:    size - The size of input file.
- *                file_name - The name if input file.
- * Returns:       The address of the buffer allocated to stroe file content.
- * Side effects:
- * Description:
- *               Read the file content into an allocated buffer.
- *---------------------------------------------------------------------------
- */
-static uint8_t *read_input_file(uint32_t size, const char *file_name)
-{
-	uint8_t *buffer;
-	FILE *input_fp;
-
-	buffer = (uint8_t *)(malloc(size));
-	if (!buffer) {
-		fprintf(stderr, "Cannot allocate %d bytes\n", size);
-		return NULL;
-	}
-	input_fp = fopen(file_name, "r");
-	if (!input_fp) {
-		display_color_msg(FAIL,
-			"ERROR: cannot open file %s\n", file_name);
-		free(buffer);
-		return NULL;
-	}
-	if (fread(buffer, size, 1, input_fp) != 1) {
-		fprintf(stderr, "Cannot read %s\n", file_name);
-		fclose(input_fp);
-		free(buffer);
-		return NULL;
-	}
-	fclose(input_fp);
-	return buffer;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	main
- *
- * Parameters:		argc - Argument Count.
- *			argv - Argument Vector.
- * Returns:		1 for a successful operation, 0 otherwise.
- * Side effects:
- * Description:
- *		Console application main operation.
- *---------------------------------------------------------------------------
- */
-int main(int argc, char *argv[])
-{
-	char *stop_str;
-	char aux_buf[MAX_FILE_NAME_SIZE];
-	uint32_t size = 0;
-	uint32_t addr = 0;
-	enum sync_result sr;
-	uint8_t *buffer;
-	int sync_cnt;
-
-	if (argc <= 1)
-		exit(EC_UNSUPPORTED_CMD_ERR);
-
-	/* Setup defaults */
-	strncpy(port_name, DEFAULT_PORT_NAME, sizeof(port_name));
-	baudrate = DEFAULT_BAUD_RATE;
-	dev_num = DEFAULT_DEV_NUM;
-	flash_offset = DEFAULT_FLASH_OFFSET;
-	opr_name[0] = '\0';
-	verbose = true;
-	console = false;
-	auto_mode = false;
-	read_flash_flag = false;
-
-	param_parse_cmd_line(argc, argv);
-
-	/* Configure COM Port parameters */
-	port_cfg.baudrate = MAX(baudrate, BR_LOW_LIMIT);
-	port_cfg.byte_size = CS8;
-	port_cfg.flow_control = 0;
-	port_cfg.parity = 0;
-	port_cfg.stop_bits = 0;
-
-	/*
-	 * Open a ComPort device. If user haven't specified such, use ComPort 1
-	 */
-	if (opr_open_port(port_name, port_cfg) != true)
-		exit(EC_PORT_ERR);
-
-	if (baudrate == 0) { /* Scan baud rate range */
-		opr_scan_baudrate();
-		exit_uart_app(EC_OK);
-	}
-
-	/* Verify Host and Device are synchronized */
-	DISPLAY_MSG(("Performing a Host/Device synchronization check...\n"));
-	for (sync_cnt = 1; sync_cnt <= MAX_SYNC_RETRIES; sync_cnt++) {
-		sr = opr_check_sync(baudrate);
-		if (sr == SR_OK)
-			break;
-		/*
-		 * If it fails, try it again up to three times.
-		 * It might fail for garbage data drainage from H1, or
-		 * for timeout due to unstable data transfer yet.
-		 */
-		display_color_msg(FAIL,
-			"Host/Device synchronization failed, error = %d,"
-			" fail count = %d\n", sr, sync_cnt);
-	}
-	if (sync_cnt > MAX_SYNC_RETRIES)
-		exit_uart_app(EC_SYNC_ERR);
-
-	if (auto_mode) {
-		size = param_get_file_size(file_name);
-		if (size == 0)
-			exit_uart_app(EC_FILE_ERR);
-
-		buffer = read_input_file(size, file_name);
-		if (!buffer)
-			exit_uart_app(EC_FILE_ERR);
-
-		printf("Write file %s at %d with %d bytes\n",
-					file_name, flash_offset, size);
-		if (image_auto_write(flash_offset, buffer, size)) {
-			printf("Flash Done.\n");
-			free(buffer);
-			exit_uart_app(EC_OK);
-		}
-		free(buffer);
-		exit_uart_app(-1);
-	}
-
-	if (read_flash_flag) {
-		uint32_t flash_size;
-
-		if (get_flash_size(&flash_size)) {
-			printf("Read %d bytes from flash...\n", flash_size);
-			opr_read_mem(file_name, NPCX_FLASH_BASE_ADDR,
-					flash_size);
-			exit_uart_app(EC_OK);
-		}
-
-		printf("Fail to read the flash size\n");
-		exit_uart_app(-1);
-	}
-
-	param_check_opr_num(opr_name);
-
-	/* Write buffer data to chosen address */
-	if (strcmp(opr_name, OPR_WRITE_MEM) == 0) {
-		addr = strtoull(addr_str, &stop_str, 0);
-
-		if (console) {
-			/*
-			 * Copy the input string to an auxiliary buffer, since
-			 * string is altered by param_get_str_size
-			 */
-			memcpy(aux_buf, file_name, sizeof(file_name));
-			/* Retrieve input size */
-			size = param_get_str_size(file_name);
-			/* Ensure non-zero size */
-			if (size == 0)
-				exit_uart_app(EC_FILE_ERR);
-			opr_write_mem((uint8_t *)(aux_buf), addr, size);
-		} else {
-			size = param_get_file_size(file_name);
-			if (size == 0)
-				exit_uart_app(EC_FILE_ERR);
-			buffer = read_input_file(size, file_name);
-			if (!buffer)
-				exit_uart_app(EC_FILE_ERR);
-			opr_write_mem(buffer, addr, size);
-			free(buffer);
-		}
-	} else if (strcmp(opr_name, OPR_READ_MEM) == 0) {
-		/* Read data to chosen address */
-
-		addr = strtoull(addr_str, &stop_str, 0);
-		size = strtoull(size_str, &stop_str, 0);
-
-		opr_read_mem(file_name, addr, size);
-	} else if (strcmp(opr_name, OPR_EXECUTE_EXIT) == 0) {
-		/* Execute From Address a non-return code */
-
-		addr = strtoull(addr_str, &stop_str, 0);
-
-		opr_execute_exit(addr);
-		exit_uart_app(EC_OK);
-	} else if (strcmp(opr_name, OPR_EXECUTE_CONT) == 0) {
-		/* Execute From Address a returnable code */
-
-		addr = strtoull(addr_str, &stop_str, 0);
-
-		opr_execute_return(addr);
-	} else {
-		exit_uart_app(EC_UNSUPPORTED_CMD_ERR);
-	}
-
-	exit_uart_app(EC_OK);
-	return 0;
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_parse_cmd_line
- *
- * Parameters:		argc - Argument Count.
- *			argv - Argument Vector.
- * Returns:		None.
- * Side effects:
- * Description:
- *		Parse command line parameters.
- *---------------------------------------------------------------------------
- */
-
-static const struct option long_opts[] = {
-	{"version",         0, 0, 'v'},
-	{"help",            0, 0, 'h'},
-	{"quiet",           0, 0, 'q'},
-	{"console",         0, 0, 'c'},
-	{"auto",            0, 0, 'A'},
-	{"read-flash",      0, 0, 'r'},
-	{"baudrate",        1, 0, 'b'},
-	{"opr",             1, 0, 'o'},
-	{"port",            1, 0, 'p'},
-	{"file",            1, 0, 'f'},
-	{"addr",            1, 0, 'a'},
-	{"size",            1, 0, 's'},
-	{"offset",          1, 0, 'O'},
-	{NULL,       0, 0, 0}
-};
-
-static const char *short_opts = "vhqcArb:o:p:f:a:s:O:?";
-
-static void param_parse_cmd_line(int argc, char *argv[])
-{
-	int opt, idx;
-
-	while ((opt = getopt_long(argc, argv, short_opts,
-				long_opts, &idx)) != -1) {
-
-		switch (opt) {
-		case 'v':
-			main_print_version();
-			exit(EC_OK);
-		case 'h':
-		case '?':
-			tool_usage();
-			opr_usage();
-			exit(EC_OK);
-		case 'q':
-			verbose = false;
-			break;
-		case 'c':
-			console = true;
-			break;
-		case 'A':
-			auto_mode = true;
-			break;
-		case 'r':
-			read_flash_flag = true;
-			break;
-		case 'b':
-			if (sscanf(optarg, "%du", &baudrate) == 0)
-				exit(EC_BAUDRATE_ERR);
-			break;
-		case 'o':
-			strncpy(opr_name, optarg, sizeof(opr_name));
-			opr_name[sizeof(opr_name)-1] = '\0';
-			break;
-		case 'p':
-			strncpy(port_name, optarg, sizeof(port_name));
-			port_name[sizeof(port_name)-1] = '\0';
-			break;
-		case 'f':
-			strncpy(file_name, optarg, sizeof(file_name));
-			file_name[sizeof(file_name)-1] = '\0';
-			break;
-		case 'a':
-			strncpy(addr_str, optarg, sizeof(addr_str));
-			addr_str[sizeof(addr_str)-1] = '\0';
-			break;
-		case 's':
-			strncpy(size_str, optarg, sizeof(size_str));
-			size_str[sizeof(size_str)-1] = '\0';
-			break;
-		case 'O':
-			flash_offset = strtol(optarg, NULL, 0);
-			break;
-		}
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_check_opr_num
- *
- * Parameters:	opr - Operation Number.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Verify the validity of operation Number.
- *---------------------------------------------------------------------------
- */
-static void param_check_opr_num(const char *opr)
-{
-
-	if ((strcasecmp(opr, OPR_WRITE_MEM) != 0) &&
-		(strcasecmp(opr, OPR_READ_MEM) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) {
-		display_color_msg(FAIL,
-			"ERROR: Operation %s not supported, Supported "
-			"operations are %s, %s, %s & %s\n",
-			opr, OPR_WRITE_MEM, OPR_READ_MEM, OPR_EXECUTE_EXIT,
-			OPR_EXECUTE_CONT);
-		exit_uart_app(EC_OPR_MUM_ERR);
-	}
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_get_file_size
- *
- * Parameters:	file_name - input file name.
- * Returns:	size of file (in bytes).
- * Side effects:
- * Description:
- *		Retrieve the size (in bytes) of a given file.
- *--------------------------------------------------------------------------
- */
-static uint32_t param_get_file_size(const char *file_name)
-{
-	struct stat fst;
-
-	if (stat(file_name, &fst)) {
-		display_color_msg(FAIL,
-				"ERROR: Could not stat file [%s]\n", file_name);
-		return 0;
-	}
-	return fst.st_size;
-
-}
-
-/*---------------------------------------------------------------------------
- * Function:	param_get_str_size
- *
- * Parameters:	string - input string.
- * Returns:	size of double-words (in bytes).
- * Side effects:
- * Description:
- *	Retrieve the size (in bytes) of double-word values in a given string.
- *	E.g., given the string "1234 AB5678 FF", return 12 (for three
- *	double-words).
- *---------------------------------------------------------------------------
- */
-static uint32_t param_get_str_size(char *string)
-{
-	uint32_t str_size = 0;
-	char seps[] = " ";
-	char *token = NULL;
-
-	/* Verify string is non-NULL */
-	if ((string == NULL) || (strlen(string) == 0)) {
-		display_color_msg(FAIL,
-			"ERROR: Zero length input string provided\n");
-		return 0;
-	}
-
-	/* Read first token from string */
-	token = strtok(string, seps);
-
-	/* Loop while there are tokens in "string" */
-	while (token != NULL) {
-		str_size++;
-		token = strtok(NULL, seps);
-	}
-
-	/* Refer to each token as a double-word */
-	str_size *= sizeof(uint32_t);
-	return str_size;
-}
-
-/*--------------------------------------------------------------------------
- * Function:	tool_usage
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Prints the console application help menu.
- *--------------------------------------------------------------------------
- */
-static void tool_usage(void)
-{
-	printf("%s version %s\n\n", tool_name, tool_version);
-	printf("General switches:\n");
-	printf("  -v, --version        - Print version\n");
-	printf("  -h, --help           - Help menu\n");
-	printf("  -q, --quiet          - Suppress verbose mode (default is "
-	       "verbose ON)\n");
-	printf("  -c, --console        - Print data to console (default is "
-	       "print to file)\n");
-	printf("  -p, --port <name>    - Serial port name (default is %s)\n",
-		DEFAULT_PORT_NAME);
-	printf("  -b, --baudrate <num> - COM Port baud-rate (default is %d)\n",
-		DEFAULT_BAUD_RATE);
-	printf("  -A, --auto           - Enable auto mode. (default is off)\n");
-	printf("  -O, --offset <num>   - With --auto, assign the offset of");
-	printf(" flash where the image to be written.\n");
-	printf("  -r, --read-flash     - With --file=<file>, Read the whole"
-			" flash content and write it to <file>.\n");
-	printf("\n");
-	printf("Operation specific switches:\n");
-	printf("  -o, --opr   <name>   - Operation number (see list below)\n");
-	printf("  -f, --file  <name>   - Input/output file name\n");
-	printf("  -a, --addr  <num>    - Start memory address\n");
-	printf("  -s, --size  <num>    - Size of data to read\n");
-	printf("\n");
-}
-
-/*--------------------------------------------------------------------------
- * Function:	main_print_version
- *
- * Parameters:	none
- * Returns:	none
- * Side effects:
- * Description:
- *		This routine prints the tool version
- *--------------------------------------------------------------------------
- */
-static void main_print_version(void)
-{
-	printf("%s version %s\n\n", tool_name, tool_version);
-}
-
-/*---------------------------------------------------------------------------
- * Function:	exit_uart_app
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Exit "nicely" the application.
- *---------------------------------------------------------------------------
- */
-static void exit_uart_app(int32_t exit_status)
-{
-	if (opr_close_port() != true)
-		display_color_msg(FAIL, "ERROR: Port close failed.\n");
-
-	exit(exit_status);
-}
-
-/*---------------------------------------------------------------------------
- * Function:	display_color_msg
- *
- * Parameters:
- *		success - SUCCESS for successful message, FAIL for erroneous
- *			  massage.
- *		fmt     - Massage to dispaly (format and arguments).
- *
- * Returns:	none
- * Side effects: Using DISPLAY_MSG macro.
- * Description:
- *		This routine displays a message using color attributes:
- *		In case of a successful message, use green foreground text on
- *		black background.
- *		In case of an erroneous message, use red foreground text on
- *		black background.
- *---------------------------------------------------------------------------
- */
-void display_color_msg(bool success, const char *fmt, ...)
-{
-	va_list argptr;
-
-	va_start(argptr, fmt);
-	vprintf(fmt, argptr);
-	va_end(argptr);
-}
diff --git a/util/uut/main.h b/util/uut/main.h
deleted file mode 100644
index 2885e7368a..0000000000
--- a/util/uut/main.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __UTIL_UUT_MAIN_H
-#define __UTIL_UUT_MAIN_H
-
-#include <stdbool.h>
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-/* Maximum Read/Write data size per packet */
-#define MAX_RW_DATA_SIZE 256
-
-/* Base for string conversion */
-#define BASE_DECIMAL 10
-#define BASE_HEXADECIMAL 16
-
-/* Verbose control messages display */
-#define DISPLAY_MSG(msg) \
-{                        \
-	if (verbose)         \
-		printf msg;      \
-}
-
-#define SUCCESS true
-#define FAIL false
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*--------------------------------------------------------------------------
- * Global variables
- *--------------------------------------------------------------------------
- */
-
-extern bool verbose;
-extern bool console;
-
-/*--------------------------------------------------------------------------
- * Global functions
- *--------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------
- * Function:	display_color_msg
- *
- * Parameters:
- *		success - SUCCESS for successful message, FAIL for erroneous
- *			  massage.
- *		fmt     - Massage to dispaly (format and arguments).
- *
- * Returns:	none
- * Side effects:	Using DISPLAY_MSG macro.
- * Description:
- *	This routine displays a message using color attributes:
- *		In case of a successful message, use green foreground text on
- *		black background.
- *		In case of an erroneous message, use red foreground text on
- *		black background.
- *--------------------------------------------------------------------------
- */
-void display_color_msg(bool success, const char *fmt, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __UTIL_UUT_MAIN_H */
diff --git a/util/uut/opr.c b/util/uut/opr.c
deleted file mode 100644
index 2105a199a1..0000000000
--- a/util/uut/opr.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file implements the UART console application operations. */
-
-#ifndef _GNU_SOURCE
-#define _GNU_SOURCE /* for asprintf */
-#endif
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "com_port.h"
-#include "cmd.h"
-#include "main.h"
-#include "misc_util.h"
-#include "opr.h"
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------
- */
-int port_handle = INVALID_HANDLE_VALUE;
-
-/*----------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-#define MAX_PORT_NAME_SIZE 32
-#define OPR_TIMEOUT 10L		 /* 10  seconds */
-#define FLASH_ERASE_TIMEOUT 120L /* 120 seconds */
-
-#define STS_MSG_MIN_SIZE 8
-#define STS_MSG_APP_END 0x09
-
-#define MAX_SYNC_TRIALS 3
-
-/*----------------------------------------------------------------------------
- * Global variables
- *---------------------------------------------------------------------------
- */
-struct command_node cmd_buf[MAX_CMD_BUF_SIZE];
-uint8_t resp_buf[MAX_RESP_BUF_SIZE];
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num);
-
-/*----------------------------------------------------------------------------
- * Function implementation
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Function:	opr_usage
- *
- * Parameters:	none.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Prints the console application operation menu.
- *---------------------------------------------------------------------------
- */
-void opr_usage(void)
-{
-	printf("Operations:\n");
-	printf("       %s\t\t- Write To Memory/Flash\n", OPR_WRITE_MEM);
-	printf("       %s\t\t- Read From Memory/Flash\n", OPR_READ_MEM);
-	printf("       %s\t\t- Execute a non-return code\n", OPR_EXECUTE_EXIT);
-	printf("       %s\t\t- Execute a returnable code\n", OPR_EXECUTE_CONT);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_close_port
- *
- * Parameters:	none
- * Returns:
- * Side effects:
- * Description:
- *		This routine closes the opened COM port by the application
- *---------------------------------------------------------------------------
- */
-bool opr_close_port(void)
-{
-	return com_port_close(port_handle);
-}
-
-/*----------------------------------------------------------------------------
- * Function:        opr_open_port
- *
- * Parameters:	port_name - COM Port name.
- *		port_cfg - COM Port configuration structure.
- * Returns:	1 if successful, 0 in the case of an error.
- * Side effects:
- * Description:
- *		Open a specified ComPort device.
- *---------------------------------------------------------------------------
- */
-bool opr_open_port(const char *port_name, struct comport_fields port_cfg)
-{
-	char *full_port_name;
-
-	if (asprintf(&full_port_name, "/dev/%s", port_name) == -1)
-		return false;
-
-	if (port_handle > 0)
-		com_port_close(port_handle);
-
-	port_handle = com_port_open((const char *)full_port_name, port_cfg);
-
-	if (port_handle <= 0) {
-		display_color_msg(FAIL, "\nERROR: COM Port failed to open.\n");
-		DISPLAY_MSG(
-			("Please select the right serial port or check if "
-			 "other serial\n"));
-		DISPLAY_MSG(("communication applications are opened.\n"));
-		return false;
-	}
-
-	display_color_msg(SUCCESS, "Port %s Opened\n", full_port_name);
-
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_write_chunk
- *
- * Parameters:
- *      buffer  - Input data buffer.
- *      addr    - Memory address to write to.
- *      size    - Data size to write.
- * Returns: true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *   Write data to RAM, starting from the given  address (addr).
- *   Data size is limited to the max chunk size (256 bytes).
- *---------------------------------------------------------------------------
- */
-bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	struct command_node wr_cmd_buf;
-
-	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
-	}
-	/* Initialize response size */
-	wr_cmd_buf.resp_size = 1;
-	cmd_create_write(addr, size, buffer,
-			wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-	return opr_send_cmds(&wr_cmd_buf, 1);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_read_chunk
- *
- * Parameters:
- *      buffer  - Data read buffer.
- *      addr    - Memory address to read from.
- *      size    - Data size to read.
- * Returns: true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *   Read data from RAM, starting from the given  address (addr).
- *   Data size is limited to the max chunk size (256 bytes).
- *---------------------------------------------------------------------------
- */
-bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	struct command_node rd_cmd_buf;
-
-	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
-		return false;
-	}
-
-	cmd_create_read(addr, ((uint8_t)size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
-	rd_cmd_buf.resp_size = size + 3;
-	if (opr_send_cmds(&rd_cmd_buf, 1)) {
-		if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
-			memcpy(buffer, &resp_buf[1], size);
-			return true;
-		}
-	}
-	return false;
-}
-/*----------------------------------------------------------------------------
- * Function:	opr_write_mem
- *
- * Parameters:	input	- Input (file-name/console), containing data to write.
- *		addr	- Memory address to write to.
- *		size	- Data size to write.
- * Returns:	none.
- * Side effects:
- * Description:
- *	Write data to memory, starting from a given address.
- *	Memory may be Flash (SPI), DRAM (DDR) or SRAM.
- *	The data is retrieved either from an input file or from a console.
- *	Data size is not limited.
- *	Data is sent in 256 bytes chunks (file mode) or 4 bytes chunks
- *	(console mode).
- *---------------------------------------------------------------------------
- */
-void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size)
-{
-	uint32_t cur_addr = addr;
-	uint8_t data_buf[256];
-	uint32_t write_size, size_remain;
-	uint32_t cmd_idx = 1;
-	char seps[] = " ";
-	char *token = NULL;
-	char *stop_str;
-	uint32_t block_size = (console) ? sizeof(uint32_t) : MAX_RW_DATA_SIZE;
-	struct command_node wr_cmd_buf;
-
-	/* Initialize response size */
-	wr_cmd_buf.resp_size = 1;
-
-	DISPLAY_MSG(("Writing [%d] bytes in [%d] packets\n", size,
-		((size + (block_size - 1)) / block_size)));
-
-	/* Read first token from string */
-	if (console)
-		token = strtok((char *)(buffer), seps);
-
-	size_remain = size;
-	/* Main write loop */
-	while (true) {
-		if (console) {
-			/*
-			 * Invert token to double-word and insert the value to
-			 * data buffer
-			 */
-			(*(uint32_t *)data_buf) =
-				strtoull(token, &stop_str, BASE_HEXADECIMAL);
-
-			/* Prepare the next iteration */
-			token = strtok(NULL, seps);
-		}
-		write_size = (size_remain > block_size) ?
-					block_size : size_remain;
-		if (console) {
-			cmd_create_write(cur_addr, write_size, data_buf,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-		} else {
-			cmd_create_write(cur_addr, write_size, buffer,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
-			buffer += write_size;
-		}
-		if (opr_send_cmds(&wr_cmd_buf, 1) != true)
-			break;
-
-		cmd_disp_write(resp_buf, write_size, cmd_idx,
-			((size + (block_size - 1)) / block_size));
-		cur_addr += write_size;
-		size_remain -= write_size;
-		cmd_idx++;
-		if (size_remain == 0)
-			break;
-	}
-
-	DISPLAY_MSG(("\n"));
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_read_mem
- *
- * Parameters:	output - Output file name, containing data that was read.
- *		addr   - Memory address to read from.
- *		size   - Data size to read.
- * Returns:	none.
- * Side effects:
- * Description:
- *		Read data from memory, starting from a given address.
- *		Memory may be Flash (SPI), DRAM (DDR) or SRAM.
- *		The data is written into an output file, data size is limited
- *		as specified.
- *		Data is received in 256 bytes chunks.
- *---------------------------------------------------------------------------
- */
-void opr_read_mem(char *output, uint32_t addr, uint32_t size)
-{
-	FILE *output_file_id = NULL;
-	uint32_t cur_addr;
-	uint32_t bytes_left;
-	uint32_t read_size;
-	uint32_t cmd_idx = 1;
-	struct command_node rd_cmd_buf;
-
-	if (!console) {
-		output_file_id = fopen(output, "w+b");
-
-		if (output_file_id == NULL) {
-			display_color_msg(FAIL,
-				"ERROR: could not open output file [%s]\n",
-				output);
-			return;
-		}
-	}
-
-	DISPLAY_MSG(("Reading [%d] bytes in [%d] packets\n", size,
-		((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)));
-
-	for (cur_addr = addr; cur_addr < (addr + size);
-		cur_addr += MAX_RW_DATA_SIZE) {
-		bytes_left = (uint32_t)(addr + size - cur_addr);
-		read_size = MIN(bytes_left, MAX_RW_DATA_SIZE);
-
-		cmd_create_read(cur_addr, ((uint8_t)read_size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
-		rd_cmd_buf.resp_size = read_size + 3;
-
-		if (opr_send_cmds(&rd_cmd_buf, 1) != true)
-			break;
-
-		cmd_disp_read(resp_buf, read_size, cmd_idx,
-			((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE));
-
-		if (console)
-			cmd_disp_data((resp_buf + 1), read_size);
-		else
-			fwrite((resp_buf + 1), 1, read_size, output_file_id);
-
-		cmd_idx++;
-	}
-
-	DISPLAY_MSG(("\n"));
-	if (!console)
-		fclose(output_file_id);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_execute_exit
- *
- * Parameters:	addr - Start address to execute from.
- * Returns:	none.
- * Side effects:	ROM-Code is not in UART command mode anymore.
- * Description:
- *	Execute code starting from a given address.
- *	Memory address may be in Flash (SPI), DRAM (DDR) or SRAM.
- *	No further communication with thr ROM-Code is expected at this point.
- *---------------------------------------------------------------------------
- */
-void opr_execute_exit(uint32_t addr)
-{
-	uint32_t cmd_num;
-
-	cmd_build_exec_exit(addr, cmd_buf, &cmd_num);
-	if (opr_send_cmds(cmd_buf, cmd_num) != true)
-		return;
-
-	cmd_disp_exec_exit(resp_buf);
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_execute_return
- *
- * Parameters:	addr - Start address to execute from.
- * Returns:	true if successful, false in the case of an error.
- * Side effects:
- * Description:
- *  Execute code starting from the given address and then check the result.
- *  The executed code should return with the execution result.
- *---------------------------------------------------------------------------
- */
-bool opr_execute_return(uint32_t addr)
-{
-	uint32_t cmd_num;
-
-	cmd_build_exec_ret(addr, cmd_buf, &cmd_num);
-	if (opr_send_cmds(cmd_buf, cmd_num) != true)
-		return false;
-
-	/*
-	 * Check the response command code is UFPP_FCALL_RSLT_CMD and
-	 * the return value from monitor is 0x03. (program finish and verify ok)
-	 */
-	if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD)
-					|| resp_buf[2] != 0x03)
-		return false;
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_check_sync
- *
- * Parameters:
- *		baudrate - baud rate to check
- *
- * Returns:
- * Side effects:
- * Description:
- *	Checks whether the Host and the Core are synchoronized in the
- *	specified baud rate
- *---------------------------------------------------------------------------
- */
-enum sync_result opr_check_sync(uint32_t baudrate)
-{
-	uint32_t cmd_num;
-	struct command_node *cur_cmd = cmd_buf;
-	uint32_t bytes_read = 0;
-	uint32_t i;
-
-	port_cfg.baudrate = baudrate;
-	if (!com_config_uart(port_handle, port_cfg))
-		return SR_ERROR;
-
-	cmd_build_sync(cmd_buf, &cmd_num);
-
-	if (!com_port_write_bin(port_handle, cur_cmd->cmd, cur_cmd->cmd_size))
-		return SR_ERROR;
-
-	/* Allow several SYNC trials */
-	for (i = 0; i < MAX_SYNC_TRIALS; i++) {
-		bytes_read = com_port_read_bin(port_handle, resp_buf, 1);
-
-		/* Quit if succeeded to read a response */
-		if (bytes_read == 1)
-			break;
-		/* Otherwise give the ROM-Code time to answer */
-		sleep(1);
-	}
-
-	if (bytes_read == 0)
-		/*
-		 * Unable to read a response from ROM-Code in a reasonable
-		 * time
-		 */
-		return SR_TIMEOUT;
-
-	if (resp_buf[0] != (uint8_t)(UFPP_D2H_SYNC_CMD))
-		/* ROM-Code response is not as expected */
-		return SR_WRONG_DATA;
-
-	/* Good response */
-	return SR_OK;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_scan_baudrate
- *
- * Parameters:	none
- * Returns:
- * Side effects:
- * Description:
- *		Scans the baud rate range by sending sync request to the core
- *		and prints the response
- *---------------------------------------------------------------------------
- */
-bool opr_scan_baudrate(void)
-{
-	uint32_t baud = 0;
-	uint32_t step;
-	enum sync_result sr;
-	bool synched = false;
-	bool data_received = false;
-
-	/* Scan with HUGE STEPS */
-	/* BR_BIG_STEP is percents */
-	step = (BR_LOW_LIMIT * BR_BIG_STEP) / 100;
-	for (baud = BR_LOW_LIMIT; baud < BR_HIGH_LIMIT; baud += step) {
-		sr = opr_check_sync(baud);
-		step = (baud * BR_BIG_STEP) / 100;
-		if (sr == SR_OK) {
-			printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-			synched = true;
-			step = (baud * BR_SMALL_STEP) / 100;
-		} else if (sr == SR_WRONG_DATA) {
-			printf("SR_WRONG_DATA: Baud rate - %d, resp_buf - "
-			       "0x%x\n", baud, resp_buf[0]);
-			data_received = true;
-			step = (baud * BR_MEDIUM_STEP) / 100;
-		} else if (sr == SR_TIMEOUT) {
-			printf("SR_TIMEOUT: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-
-			if (synched || data_received)
-				break;
-		} else if (sr == SR_ERROR) {
-			printf("SR_ERROR: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
-			if (synched || data_received)
-				break;
-		} else
-			printf("Unknown error code: Baud rate - %d, resp_buf - "
-				"0x%x\n", baud, resp_buf[0]);
-	}
-
-	return true;
-}
-
-/*----------------------------------------------------------------------------
- * Function:	opr_send_cmds
- *
- * Parameters:	cmd_buf - Pointer to a Command Buffer.
- *		cmd_num - Number of commands to send.
- * Returns:	1 if successful, 0 in the case of an error.
- * Side effects:
- * Description:
- *	Send a group of commands through COM port.
- *	A command is sent only after a valid response for the previous command
- *	was received.
- *---------------------------------------------------------------------------
- */
-static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num)
-{
-	struct command_node *cur_cmd = cmd_buf;
-	uint32_t cmd;
-	uint32_t read;
-	time_t start;
-	double elapsed_time;
-
-	for (cmd = 0; cmd < cmd_num; cmd++, cur_cmd++) {
-		if (com_port_write_bin(port_handle, cur_cmd->cmd,
-						cur_cmd->cmd_size) == true) {
-			time(&start);
-
-			do {
-				read = com_port_wait_read(port_handle);
-				elapsed_time = difftime(time(NULL), start);
-			} while ((read < cur_cmd->resp_size) &&
-				 (elapsed_time <= OPR_TIMEOUT));
-			com_port_read_bin(port_handle, resp_buf,
-							cur_cmd->resp_size);
-
-			if (elapsed_time > OPR_TIMEOUT)
-				display_color_msg(FAIL,
-					"ERROR: [%d] bytes received for read, "
-					"[%d] bytes are expected\n",
-					read, cur_cmd->resp_size);
-		} else {
-			display_color_msg(FAIL,
-				"ERROR: Failed to send Command number %d\n",
-				cmd);
-			return false;
-		}
-	}
-
-	return true;
-}
-
diff --git a/util/uut/opr.h b/util/uut/opr.h
deleted file mode 100644
index 3b166f0c7e..0000000000
--- a/util/uut/opr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file defines the UART console application operations. */
-
-#ifndef __UTIL_UUT_OPR_H
-#define __UTIL_UUT_OPR_H
-
-/*---------------------------------------------------------------------------
- * Constant definitions
- *---------------------------------------------------------------------------
- */
-
-/* Baud rate scan steps: */
-#define BR_BIG_STEP 20       /* in percents from current baud rate */
-#define BR_MEDIUM_STEP 10    /* in percents from current baud rate */
-#define BR_SMALL_STEP 1      /* in percents from current baud rate */
-#define BR_MIN_STEP 5        /* in absolute baud rate units */
-#define BR_LOW_LIMIT 400     /* Automatic BR detection starts at this value */
-#define BR_HIGH_LIMIT 150000 /* Automatic BR detection ends at this value */
-
-#define OPR_WRITE_MEM "wr"      /* Write To Memory/Flash */
-#define OPR_READ_MEM "rd"       /* Read From Memory/Flash */
-#define OPR_EXECUTE_EXIT "go"   /* Execute a non-return code */
-#define OPR_EXECUTE_CONT "call" /* Execute returnable code */
-
-enum sync_result {
-	SR_OK = 0x00,
-	SR_WRONG_DATA = 0x01,
-	SR_TIMEOUT = 0x02,
-	SR_ERROR = 0x03
-};
-
-/*----------------------------------------------------------------------------
- * External Variables
- *---------------------------------------------------------------------------
- */
-extern struct comport_fields port_cfg;
-
-/*---------------------------------------------------------------------------
- * Functions prototypes
- *---------------------------------------------------------------------------
- */
-
-void opr_usage(void);
-bool opr_close_port(void);
-bool opr_open_port(const char *port_name, struct comport_fields port_cfg);
-bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size);
-bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size);
-void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size);
-void opr_read_mem(char *output, uint32_t addr, uint32_t size);
-void opr_execute_exit(uint32_t addr);
-bool opr_execute_return(uint32_t addr);
-bool opr_scan_baudrate(void);
-enum sync_result opr_check_sync(uint32_t baudrate);
-#endif /* __UTIL_UUT_OPR_H */
diff --git a/util/volteer-relevant-paths.txt b/util/volteer-relevant-paths.txt
deleted file mode 100644
index a45c44dcf6..0000000000
--- a/util/volteer-relevant-paths.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-# Here you can place files of interest to be included in the commit message for
-# merge commits to firmware-volteer-13672.B-main
-chip/npcx/*npcx7*
-driver/accel_bma2x2.*
-driver/accelgyro_bmi260.*
-driver/als_tcs3400.*
-driver/bc12/piusb9201.*
-driver/charger/isl9241.*
-driver/ppc/sn5s330.*
-driver/ppc/syv682x.*
-driver/retimer/bb_retimer.*
-driver/retimer/kb800x.*
-driver/tcpm/ps8xxx.*
-driver/tcpm/rt1715.*
-driver/usb_mux/virtual.*
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
deleted file mode 100644
index e896f6d841..0000000000
--- a/zephyr/CMakeLists.txt
+++ /dev/null
@@ -1,407 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Note: this cmake system implements only a zephyr module, and is not
-# intended to build a complete EC.  To build projects in platform/ec,
-# you should continue to use the Makefile system.
-#
-# Googlers can find the design doc at go/zephyr-shim.
-
-if(NOT DEFINED ZEPHYR_CURRENT_MODULE_DIR)
-  message(FATAL_ERROR "This Cmake system implements only a Zephyr module, and
-          should not be invoked directly.  Please continue to use the Makefile
-          system for non-Zephyr builds.")
-endif()
-
-set(PLATFORM_EC "${ZEPHYR_CURRENT_MODULE_DIR}" CACHE PATH
-    "Path to the platform/ec repo.")
-# Zephyr 2.3 will set ZEPHYR_CURRENT_MODULE_DIR to the directory of the
-# CMakeLists.txt file, whereas 2.4 will set it to the actual module
-# directory.  Try to detect the condition by searching for
-# zephyr/module.yml.
-if(NOT EXISTS "${PLATFORM_EC}/zephyr/module.yml")
-  set(PLATFORM_EC "${PLATFORM_EC}/..")
-  assert_exists("${PLATFORM_EC}/zephyr/module.yml")
-endif()
-
-if(DEFINED ZMAKE_INCLUDE_DIR)
-  zephyr_include_directories("${ZMAKE_INCLUDE_DIR}")
-endif()
-
-if(DEFINED CONFIG_PLATFORM_EC)
-  # Add CHROMIUM_EC definition, which is used by ec_commands.h to
-  # determine that the header is being compiled for the EC instead of
-  # by another third-party C codebase.
-  zephyr_compile_definitions("CHROMIUM_EC")
-
-  # Add CONFIG_ZEPHYR, which is commonly used to guard code for use
-  # with Zephyr builds only.
-  zephyr_compile_definitions("CONFIG_ZEPHYR")
-
-  # Force compiler warnings to generate errors
-  zephyr_compile_options(-Werror)
-
-  include(fpu.cmake)
-
-  # When LTO is enabled, enable only for the "app" library, which compiles
-  # and links all Chromium OS sources.
-  # TODO: Enable LTO for all sources when Zephyr supports it.
-  # See https://github.com/zephyrproject-rtos/zephyr/issues/2112
-  if (DEFINED CONFIG_LTO)
-    # The Zephyr toolchain generates linker errors if both CONFIG_LTO and
-    # CONFIG_FPU are used. See b/184302085.
-    if(("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "zephyr") AND
-     (DEFINED CONFIG_FPU))
-      message(STATUS "Zephyr toolchain and CONFIG_FPU detected: disabling LTO")
-    else()
-      set_property(TARGET app PROPERTY INTERPROCEDURAL_OPTIMIZATION True)
-    endif()
-  endif()
-endif()
-
-# Switch from the "zephyr" library to the "app" library for all Chromium OS
-# sources.
-set(ZEPHYR_CURRENT_LIBRARY app)
-
-add_subdirectory(linker)
-
-zephyr_library_include_directories(include)
-
-if (DEFINED CONFIG_PLATFORM_EC)
-  zephyr_library_include_directories(
-    "${PLATFORM_EC}/zephyr/shim/include"
-    "${PLATFORM_EC}/fuzz"
-    "${PLATFORM_EC}/test"
-    "${PLATFORM_EC}"
-    "${PLATFORM_EC}/include"
-    "${PLATFORM_EC}/include/driver"
-    "${PLATFORM_EC}/third_party")
-endif()
-
-add_subdirectory("app")
-add_subdirectory("drivers")
-add_subdirectory("emul")
-
-add_subdirectory_ifdef(CONFIG_PLATFORM_EC "shim")
-# Creates a phony target all.libraries in case you only want to build the
-# libraries and not the binaries. For example for creating the initial zero
-# coverage files.
-get_property(ZEPHYR_LIBS_PROPERTY GLOBAL PROPERTY ZEPHYR_LIBS)
-add_custom_target(
-  all.libraries
-  DEPENDS
-  ${ZEPHYR_LIBS_PROPERTY}
-  kernel
-  ${CMAKE_BINARY_DIR}/gcov.sh
-  )
-configure_file(gcov.tmpl.sh ${CMAKE_BINARY_DIR}/gcov.sh)
-
-# CONFIG_PLATFORM_EC files that don't relate to something below should be
-# included here, sorted by filename. This is common functionality which is
-# supported by all boards and emulators (including unit tests) using the shim
-# layer.
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c"
-                                                "${PLATFORM_EC}/common/console_output.c"
-                                                "${PLATFORM_EC}/common/ec_features.c"
-                                                "${PLATFORM_EC}/common/gpio_commands.c"
-                                                "${PLATFORM_EC}/common/peripheral.c"
-                                                "${PLATFORM_EC}/common/printf.c"
-                                                "${PLATFORM_EC}/common/queue.c"
-                                                "${PLATFORM_EC}/common/shared_mem.c"
-                                                "${PLATFORM_EC}/common/uart_printf.c"
-                                                "${PLATFORM_EC}/common/util.c"
-                                                "${PLATFORM_EC}/common/version.c")
-
-# Now include files that depend on or relate to other CONFIG options, sorted by
-# CONFIG
-zephyr_library_sources_ifdef(CONFIG_HAS_TASK_POWERBTN
-                                                "${PLATFORM_EC}/common/power_button_x86.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_BMA255
-                                                "${PLATFORM_EC}/driver/accel_bma2x2.c"
-                                                "${PLATFORM_EC}/common/math_util.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_KX022
-                                                "${PLATFORM_EC}/driver/accel_kionix.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
-                                                "${PLATFORM_EC}/driver/accel_lis2dw12.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI
-                                                "${PLATFORM_EC}/driver/accelgyro_bmi_common.c"
-                                                "${PLATFORM_EC}/common/math_util.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
-                                                "${PLATFORM_EC}/driver/accelgyro_bmi160.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
-                                                "${PLATFORM_EC}/driver/accelgyro_bmi260.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM
-                                                "${PLATFORM_EC}/driver/accelgyro_icm_common.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX
-                                                "${PLATFORM_EC}/driver/accelgyro_icm426xx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_FIFO
-                                                "${PLATFORM_EC}/common/motion_sense_fifo.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ADC_CMD
-                                                "${PLATFORM_EC}/common/adc.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_TCS3400
-                                                "${PLATFORM_EC}/driver/als_tcs3400.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACPI
-                                                "${PLATFORM_EC}/common/acpi.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BACKLIGHT_LID
-                                                "${PLATFORM_EC}/common/backlight_lid.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
-                                                "${PLATFORM_EC}/common/battery.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE
-                                                "${PLATFORM_EC}/common/battery_fuel_gauge.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_SMART
-                                                "${PLATFORM_EC}/driver/battery/smart.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
-                                                "${PLATFORM_EC}/driver/bc12/pi3usb9201.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BC12_DETECT_MT6360
-                                                "${PLATFORM_EC}/driver/bc12/mt6360.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9237
-                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9238
-                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9238C
-                                                "${PLATFORM_EC}/driver/charger/isl923x.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_ISL9241
-                                                "${PLATFORM_EC}/driver/charger/isl9241.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25710
-                                                "${PLATFORM_EC}/driver/charger/bq25710.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_BQ25720
-                                                "${PLATFORM_EC}/driver/charger/bq25710.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER
-                                                "${PLATFORM_EC}/common/charger.c"
-                                                "${PLATFORM_EC}/common/charge_manager.c"
-                                                "${PLATFORM_EC}/common/charge_state_v2.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
-                                                "${PLATFORM_EC}/common/charge_ramp.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_SW
-                                                "${PLATFORM_EC}/common/charge_ramp.c"
-                                                "${PLATFORM_EC}/common/charge_ramp_sw.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM
-                                                "${PLATFORM_EC}/common/cbi.c"
-                                                "${PLATFORM_EC}/common/cbi_eeprom.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_GPIO
-                                                "${PLATFORM_EC}/common/cbi.c"
-                                                "${PLATFORM_EC}/common/cbi_gpio.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM
-                                                "${PLATFORM_EC}/common/memory_commands.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_DPTF
-                                                "${PLATFORM_EC}/common/dptf.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
-                                                "${PLATFORM_EC}/common/chipset.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI
-                                                "${PLATFORM_EC}/common/espi.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/extpower_common.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTPOWER_GPIO
-                                                "${PLATFORM_EC}/common/extpower_gpio.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN
-                                                "${PLATFORM_EC}/common/fan.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FLASH_CROS
-                                                "${PLATFORM_EC}/common/flash.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD
-                                                "${PLATFORM_EC}/common/host_command.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD
-                                                "${PLATFORM_EC}/common/host_event_commands.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE
-                                                "${PLATFORM_EC}/common/uart_hostcmd.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
-                                                "${PLATFORM_EC}/common/uptime.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_REGULATOR
-                                                "${PLATFORM_EC}/common/regulator.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
-                                                "${PLATFORM_EC}/common/i2c_controller.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C_DEBUG
-                                                "${PLATFORM_EC}/common/i2c_trace.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY
-                                                "${PLATFORM_EC}/common/virtual_battery.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD
-                                                "${PLATFORM_EC}/common/keyboard_scan.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
-                                                "${PLATFORM_EC}/common/keyboard_8042.c"
-                                                "${PLATFORM_EC}/common/keyboard_8042_sharedlib.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
-                                                "${PLATFORM_EC}/common/keyboard_mkbp.c"
-                                                "${PLATFORM_EC}/common/mkbp_fifo.c"
-                                                "${PLATFORM_EC}/common/mkbp_info.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES
-                                                "${PLATFORM_EC}/common/mkbp_input_devices.c"
-                                                "${PLATFORM_EC}/common/mkbp_fifo.c"
-                                                "${PLATFORM_EC}/common/mkbp_info.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_VIVALDI
-                                                "${PLATFORM_EC}/common/keyboard_vivaldi.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_KBLIGHT
-                                                "${PLATFORM_EC}/common/keyboard_backlight.c"
-                                                "${PLATFORM_EC}/common/pwm_kblight.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-                                                "${PLATFORM_EC}/common/led_common.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_PWM
-                                                "${PLATFORM_EC}/common/led_pwm.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_ANGLE
-                                                "${PLATFORM_EC}/common/motion_lid.c"
-                                                "${PLATFORM_EC}/common/math_util.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE
-                                                "${PLATFORM_EC}/common/lid_angle.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LID_SWITCH
-                                                "${PLATFORM_EC}/common/lid_switch.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT
-                                                "${PLATFORM_EC}/common/mkbp_event.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
-                                                "${PLATFORM_EC}/common/motion_sense.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MP2964
-                                                "${PLATFORM_EC}/driver/mp2964.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PORT80
-                                                "${PLATFORM_EC}/common/port80.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON
-                                                "${PLATFORM_EC}/common/power_button.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
-                                                "${PLATFORM_EC}/power/common.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_AMD
-                                                "${PLATFORM_EC}/power/amd_x86.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_COMETLAKE
-                                                "${PLATFORM_EC}/power/cometlake.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE
-                                                "${PLATFORM_EC}/power/icelake.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL
-                                                "${PLATFORM_EC}/power/intel_x86.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP
-                                                "${PLATFORM_EC}/power/host_sleep.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_MT8192
-						"${PLATFORM_EC}/power/mt8192.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_SC7180
-                                                "${PLATFORM_EC}/power/qcom.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_SC7280
-                                                "${PLATFORM_EC}/power/qcom.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PANIC
-                                                "${PLATFORM_EC}/common/panic_output.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM
-                                                "${PLATFORM_EC}/common/pwm.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SHA256_SW
-                                                "${PLATFORM_EC}/common/sha256.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCH
-                                                "${PLATFORM_EC}/common/switch.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCHCAP_LN9310
-                                                "${PLATFORM_EC}/driver/ln9310.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SPI_FLASH_REGS
-                                                "${PLATFORM_EC}/common/spi_flash_reg.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_STM_MEMS_COMMON
-                                                "${PLATFORM_EC}/driver/stm_mems_common.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TABLET_MODE
-                                                "${PLATFORM_EC}/common/tablet_mode.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR
-                                                "${PLATFORM_EC}/common/thermal.c"
-                                                "${PLATFORM_EC}/common/temp_sensor.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_THERMISTOR
-                                                "${PLATFORM_EC}/driver/temp_sensor/thermistor.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_THROTTLE_AP
-                                                "${PLATFORM_EC}/common/throttle_ap.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TIMER
-                                                "${PLATFORM_EC}/common/timer.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_CHARGER
-                                                "${PLATFORM_EC}/common/usb_charger.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB
-                                                "${PLATFORM_EC}/common/usb_port_power_dumb.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
-                                                "${PLATFORM_EC}/common/usb_common.c"
-                                                "${PLATFORM_EC}/common/usbc/usbc_task.c"
-                                                "${PLATFORM_EC}/common/usbc/usb_pd_timer.c"
-                                                "${PLATFORM_EC}/common/usbc/usb_sm.c"
-                                                "${PLATFORM_EC}/common/usbc_intr_task.c"
-                                                "${PLATFORM_EC}/common/usb_pd_flags.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN
-                                                "${PLATFORM_EC}/common/chargen.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_PD
-                                                "${PLATFORM_EC}/common/usbc/usb_pd_console.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE
-                                                "${PLATFORM_EC}/common/usbc/usb_retimer_fw_update.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
-                                                "${PLATFORM_EC}/driver/retimer/bb_retimer.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_SS_MUX
-                                                "${PLATFORM_EC}/driver/usb_mux/usb_mux.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_IT5205
-                                                "${PLATFORM_EC}/driver/usb_mux/it5205.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_PS8743
-                                                "${PLATFORM_EC}/driver/usb_mux/ps8743.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL
-                                                "${PLATFORM_EC}/driver/usb_mux/virtual.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_LOGGING
-                                                "${PLATFORM_EC}/common/event_log.c"
-                                                "${PLATFORM_EC}/common/pd_log.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
-                                                "${PLATFORM_EC}/common/usbc/tbt_alt_mode.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_USB4
-                                                "${PLATFORM_EC}/common/usbc/usb_mode.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_OCP
-                                                "${PLATFORM_EC}/common/usbc_ocp.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_DFP
-                                                "${PLATFORM_EC}/common/usb_pd_alt_mode_dfp.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP
-                                                "${PLATFORM_EC}/common/usb_pd_alt_mode_ufp.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE
-                                                "${PLATFORM_EC}/common/usb_pd_dual_role.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_CONSOLE_CMD
-                                                "${PLATFORM_EC}/common/usb_pd_console_cmd.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_HOST_CMD
-                                                "${PLATFORM_EC}/common/usb_pd_host_cmd.c"
-                                                "${PLATFORM_EC}/common/usbc/usb_pd_host.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_VPD
-                                                "${PLATFORM_EC}/common/usbc/usb_tc_vpd_sm.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_CTVPD
-                                                "${PLATFORM_EC}/common/usbc/usb_tc_ctvpd_sm.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC
-                                                "${PLATFORM_EC}/common/usbc/usb_tc_drp_acc_trysrc_sm.c"
-                                                "${PLATFORM_EC}/common/usbc/usb_pe_drp_sm.c"
-                                                "${PLATFORM_EC}/common/usbc/usb_pd_dpm.c"
-						"${PLATFORM_EC}/common/usbc/usbc_pd_policy.c"
-                                                "${PLATFORM_EC}/common/usbc/dp_alt_mode.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PRL_SM
-                                                "${PLATFORM_EC}/common/usbc/usb_prl_sm.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751
-                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805
-                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815
-                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715
-                                                "${PLATFORM_EC}/driver/tcpm/rt1715.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422
-                                                "${PLATFORM_EC}/driver/tcpm/tusb422.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI
-                                                "${PLATFORM_EC}/driver/tcpm/tcpci.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-                                                "${PLATFORM_EC}/driver/tcpm/ite_pd_intc.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
-                                                "${PLATFORM_EC}/driver/tcpm/it83xx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
-                                                "${PLATFORM_EC}/driver/tcpm/it8xxx2.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC
-                                                "${PLATFORM_EC}/common/usbc_ppc.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_SN5S330
-                                                "${PLATFORM_EC}/driver/ppc/sn5s330.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_PPC_SYV682X
-                                                "${PLATFORM_EC}/driver/ppc/syv682x.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VBOOT_HASH
-                                                "${PLATFORM_EC}/common/vboot_hash.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VOLUME_BUTTONS
-                                                "${PLATFORM_EC}/common/button.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VBOOT_EFS2
-                                                "${PLATFORM_EC}/common/vboot/efs2.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_VSTORE
-                                                "${PLATFORM_EC}/common/vstore.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RTC
-						"${PLATFORM_EC}/common/rtc.c")
diff --git a/zephyr/Kconfig b/zephyr/Kconfig
deleted file mode 100644
index 07f09ae46e..0000000000
--- a/zephyr/Kconfig
+++ /dev/null
@@ -1,879 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-rsource "app/Kconfig"
-rsource "drivers/Kconfig"
-rsource "emul/Kconfig"
-
-if ZTEST
-
-config HAS_TEST_TASKS
-	bool "Whether or not this test includes custom tasks"
-	help
-	  This enables custom tasks for tests. When set to 'y', the file
-	  "shimmed_test_tasks.h" will be included and is expected to set
-	  CROS_EC_TASK_LIST.
-
-endif # ZTEST
-
-menuconfig PLATFORM_EC
-	bool "Chromium OS EC shim"
-	imply PRINTK
-	imply SHELL
-	help
-	  The platform/ec Zephyr module allows some code from the
-	  existing Chromium OS EC project to be "shimmed" into Zephyr. With
-	  this it is possible to use the existing code base within Zephyr.
-
-	  Once we manage to get a platform fully running with Zephyr we will
-	  progressively upstream components and turn off the shim for each
-	  one until eventually all code is on the Zephyr side.
-
-if PLATFORM_EC
-
-rsource "shim/chip/npcx/Kconfig.npcx"
-rsource "Kconfig.adc"
-rsource "Kconfig.battery"
-rsource "Kconfig.board_version"
-rsource "Kconfig.console"
-rsource "Kconfig.console_cmd_mem"
-rsource "Kconfig.debug_assert"
-rsource "Kconfig.defaults"
-rsource "Kconfig.espi"
-rsource "Kconfig.flash"
-rsource "Kconfig.header"
-rsource "Kconfig.init_priority"
-rsource "Kconfig.keyboard"
-rsource "Kconfig.led"
-rsource "Kconfig.panic"
-rsource "Kconfig.port80"
-rsource "Kconfig.powerseq"
-rsource "Kconfig.pmic"
-rsource "Kconfig.mkbp_event"
-rsource "Kconfig.motionsense"
-rsource "Kconfig.rtc"
-rsource "Kconfig.stacks"
-rsource "Kconfig.system"
-rsource "Kconfig.tasks"
-rsource "Kconfig.temperature"
-rsource "Kconfig.timer"
-rsource "Kconfig.throttle_ap"
-rsource "Kconfig.usbc"
-rsource "Kconfig.watchdog"
-
-# Define PLATFORM_EC_... options to enable EC features. Each Kconfig should be
-# matched by a line in zephyr/shim/include/config_chip.h which #defines the
-# corresponding EC CONFIG if this Kconfig is enabled.
-#
-# Please keep these in alphabetical order
-
-config PLATFORM_EC_ACPI
-	bool "Advanced Confiugration and Power Interface (ACPI)"
-	default y if AP_X86 && PLATFORM_EC_ESPI
-	help
-	  Enable the Advanced Configuration and Power Interface (ACPI) in the
-	  EC. ACPI is a standard interface to the Application Processor (AP)
-	  that abstracts the hardware specific details for controlling and
-	  managing the board.
-
-	  This includes interfaces for monitoring or controlling features,
-	  including:
-	    keyboard backlight
-	    fan speed
-	    temperature sensors
-	    charging properties
-	    device orientation (tablet or laptop mode)
-
-	  https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
-
-config PLATFORM_EC_AP_RESET_LOG
-	bool "Enable the Application Processor reset log"
-	depends on PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
-	default y if PLATFORM_EC_POWERSEQ
-	help
-	  Enable logging of AP reset events. This information is provided in
-	  response to the EC_CMD_GET_UPTIME_INFO host command.
-
-config PLATFORM_EC_BACKLIGHT_LID
-	bool "Control the display backlight based on the lid switch"
-	depends on PLATFORM_EC_HOSTCMD
-	default y
-	help
-	  Support controlling the display backlight based on the state of the
-	  lid switch. The EC will disable the backlight when the lid is closed.
-
-	  This option enables the EC_CMD_SWITCH_ENABLE_BKLIGHT host command,
-	  which allows the AP to override the backlight setting until the next
-	  change in the lid state.
-
-config PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
-	bool "Work around H1 reset issue"
-	help
-	  Enable this if H1 resets the EC after power-on. This is needed so the EC
-	  can delay its start-up until the reset happens. Without this option
-	  the EC starts up, performs some amount of processing and then gets a
-	  reset that it is not expecting.
-
-config PLATFORM_EC_WAIT_RESET_CYCLES_PER_ITERATION
-	int "CPU execution cycle per iteration for waiting the H1 reset"
-	default 4
-	depends on PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
-	help
-	  This options specifies the number of CPU execution cycles per delay
-	  loop iteration, while waiting for the H1 to reset.
-
-config PLATFORM_EC_PREINIT_HW_CYCLES_PER_SEC
-	int "CPU power up clock cycle per second"
-	default 100000000
-	depends on PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
-	help
-	  This option specifies the frequency (in Hz) of the CPU core when
-	  coming out of a power on reset.
-
-config PLATFORM_EC_BRINGUP
-	bool "Enable early bringup debugging features"
-	help
-	  Enable the CONFIG_BRINGUP platform/ec configuration option,
-	  turning on a variety of miscellaneous early bringup
-	  debugging features.
-
-	  These features include:
-	  - The device will not power on when the EC starts.  The
-	    power button will need to be pressed, or the "powerbtn"
-	    command issued.
-	  - Enable power signal logging, showing relative timestamps
-	    for each power signal change.
-	  - And more!  You can search the codebase for CONFIG_BRINGUP
-            to see all of the features this flag will toggle.
-
-config PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK
-	bool "Bypass CBI EEPROM Write Protect"
-	help
-	  Bypass the CBI EEPROM write protect checks. This should ONLY be
-	  defined during bringup, and should never be defined on a shipping or
-	  release platform.
-
-	  When defined, ectool can be used to reprogram all CBI fields,
-	  regardless of the state of the hardware write protect.
-
-config PLATFORM_EC_EEPROM_CBI_WP
-	bool "EC can independently set the CBI EEPROM WP signal"
-	help
-	   Define this if the EC can independently set the CBI EEPROM WP
-	   signal. The accompanying hardware must ensure that the CBI WP gets
-	   latched and is only reset when EC_RST_ODL is asserted.
-	select PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK
-
-choice PLATFORM_EC_CBI_STORAGE_TYPE
-	prompt "Select CBI storage Type"
-	optional
-	help
-	  CBI is a means for accessing board information, typically set
-	  during the factory process. This allows selection of the physical
-	  storage of CBI source.
-
-	  See here for detailed information on CBI:
-
-	  https://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md
-
-config PLATFORM_EC_CBI_EEPROM
-	bool "CBI EEPROM support"
-	depends on PLATFORM_EC_I2C
-	help
-	  Enables Chromium OS Board Info (CBI) from EEPROM.
-
-	  One must specify both I2C_PORT_EEPROM and I2C_ADDR_EEPROM_FLAGS to the
-	  CBI EEPROM's i2c port and 7-bit i2c address.
-
-config PLATFORM_EC_CBI_GPIO
-	bool "CBI GPIO support"
-	help
-	  Enables Chromium OS Board Info (CBI) from strapping pins. EC reads
-	  the BOARD ID and SKU ID from GPIOs and then substantiate in-memory
-	  CBI for AP to query.
-
-endchoice
-
-config PLATFORM_EC_CHIPSET_RESET_HOOK
-	bool "Provide a hook for when the AP resets"
-	default y
-	help
-	  Enables support for the HOOK_CHIPSET_RESET hook. This can be used by
-	  code that needs to run before a programmatic reset actually happens.
-	  Note that these hooks don't run with a cold reset, only when the AP
-	  decides to reset itself.
-
-	  You can declare a hook like this:
-
-	     DECLARE_HOOK(HOOK_CHIPSET_RESET, do_something, HOOK_PRIO_DEFAULT);
-
-	  Then do_something() will be called just before the reset happens.
-
-config PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
-	bool "Enable chipset resume-init and suspend-complete hooks"
-	help
-	  Enables support for the HOOK_CHIPSET_RESUME_INIT and
-	  HOOK_CHIPSET_SUSPEND_COMPLETE hooks. These hooks are usually used to
-	  initialize/disable the SPI driver, which goes to sleep on suspend.
-	  Require to initialize it first such that it can receive a host resume
-	  event, that notifies the normal resume hook.
-
-config PLATFORM_EC_CONSOLE_CMD_HCDEBUG
-	bool "Console command: hcdebug"
-	default y
-	depends on PLATFORM_EC_HOSTCMD
-	help
-	  Enable the 'hcdebug' console command. This comamnd is used to change,
-	  at runtime, the amount of debug generated by the host command
-	  processing.
-
-	    hcdebug [off | normal | every | params]
-
-	  See PLATFORM_EC_HOSTCMD_DEBUG_MODE for more detail.
-
-config PLATFORM_EC_CONSOLE_CMD_MEM
-	bool "Console command: md, rw"
-	default y
-	help
-	  Enable memory related console commands.
-
-	     md - dump memory values
-	     rw - read or write in memory
-
-config PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
-	bool "Console command: sleepmask read"
-	default y if PM
-	help
-	  Enable the 'sleepmask' console command. This command is used to
-	  display the state of the sleep mask, which controls whether the EC
-	  chip is allowed to enter deep sleep states to save power.
-
-config PLATFORM_EC_CONSOLE_CMD_SLEEPMASK_SET
-	bool "Console command: sleepmask set"
-	depends on PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
-	default y
-	help
-	  Enable changing the state of the current sleep mask.
-
-	    sleepmask on     -  Sets the SLEEP_MASK_FORCE_NO_DSLEEP bit in the
-	                        sleep mask, preventing the system from entering
-	                        sleep.
-	    sleepmask off    -  Clears the SLEEP_MASK_FORCE_NO_DSLEEP bit in the
-	                        sleep mask. The system may enter deep sleep
-	                        depending on the state of other mask bits.
-	    sleepmask <value> - Sets the sleepmask to <value>, overriding all
-	                        bits with the specified value.
-
-config PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
-	bool "Console command: s5_timeout"
-	default n
-	help
-	  This command allows the user to specify a time to remain in S5 before
-	  dropping to G3, in order to help power testing.
-
-config PLATFORM_EC_CONSOLE_CMD_SHMEM
-	bool "Console command: shmem"
-	default y
-	help
-	  This command prints basic information about the EC shared memory,
-	  located at the top of RAM, above all RAM symbols: total size, bytes
-	  used and the maximum number of bytes that have been used since
-	  the EC started running.
-
-config PLATFORM_EC_CROS_FWID_VERSION
-	bool "Include CrOS FWID version"
-	default y
-	help
-	  Include Chrome OS FWID in version output. The CrOS FWID will be common
-	  across OS, AP firmware and EC firmware when built together.
-
-config PLATFORM_EC_DEBUG_ASSERT
-	bool "Enable assertion failures"
-	default y
-	help
-	  Assertion failures are used to flag conditions which should not occur
-	  and thus indicate the software is unable to continue execution. This
-	  option can be disabled so that the assert() macro becomes a NOP. In
-	  this case, execution will continue but the results are unpredictable.
-
-	  Messages are of the form:
-
-	     ASSERTION FAILURE '<expr>' in function() at file:line
-
-	  Note: There is also ASSERT() which is an alias of assert(), used in
-	  host code where cstdlib is used.
-
-config PLATFORM_EC_DP_REDRIVER_TDP142
-	bool "Include TDP142 DisplayPort redriver driver"
-	default n
-	help
-	  Include a driver for the Texas Instruments TDP142 DisplayPort linear
-	  redriver chip.
-
-config PLATFORM_EC_EMULATED_SYSRQ
-	bool "Emulate sysrq events to AP"
-	help
-	  The magic SysRq key is a key combo which allows the user to perform
-	  various low-level commands regardless of the system's state.
-
-	  See here for the key combos:
-
-	  https://www.kernel.org/doc/html/latest/admin-guide/sysrq.html
-
-	  This option enables support for sending emulated SysRq events to AP
-	  (on designs with a keyboard, SysRq is passed as normal key presses).
-
-menuconfig PLATFORM_EC_ESPI
-	bool "eSPI"
-	depends on ESPI && AP
-	default y
-	help
-	  Enable the Enhanced Serial Peripheral Interface (eSPI) shim layer.
-	  eSPI supports a shared physical connection between several on-board
-	  devices, similar to SPI. It adds a few optional signals and a protocol
-	  layer to provide independent 'channels' for each device to communicate
-	  over.
-
-	  eSPI is the replacement for LPC (Low-Pin-Count bus).
-
-	  See here for information about eSPI:
-
-	  https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf
-
-config PLATFORM_EC_EXTPOWER_GPIO
-	bool "GPIO-based external power detection"
-	depends on PLATFORM_EC_HOOKS && PLATFORM_EC_HOSTCMD
-	help
-	  Enable shimming the extpower_gpio module, which provides
-	  GPIO-based external power presence detection features.  The
-	  project should define a GPIO pin named GPIO_AC_PRESENT, with
-	  extpower_interrupt configured as the handler in gpio_map.h.
-
-config PLATFORM_EC_FLASH_CROS
-	bool "Enable flash support"
-	default y if FLASH_SIZE > 0
-	help
-	  Enables access to the device's flash through a simple API. With
-	  this is it possible for the EC to update its flash while running,
-	  e.g. to support auto-update. Various write-protection features are
-	  also provided.
-
-config PLATFORM_EC_FPU
-	bool "Support floating point"
-	depends on FPU && CPU_CORTEX_M && !NEWLIB_LIBC
-	default y
-	help
-	  This enables support for floating point. This is generally already
-	  provided in Zephyr, but the EC side expects a few functions to be
-	  available which are not available with Zephyr's minimal lib: sqrtf()
-	  and fabsf(). Enabling this options defines them.
-
-	  For now this is only supported on Cortex-M4.
-
-config PLATFORM_EC_HOOKS
-	bool "Hooks and deferred compatibility shim"
-	default y
-	help
-	  Enable translation of DECLARE_DEFERRED() and hook_call_deferred()
-	  to Zephyr's work queues, along with a compatible DECLARE_HOOK
-	  implementation.
-
-	  This option is needed by many features in the EC. Disabling it will
-	  likely cause build errors.
-
-menuconfig PLATFORM_EC_HOSTCMD
-	bool "Host commands"
-	default n if ARCH_POSIX
-	default y if AP
-	select HAS_TASK_HOSTCMD
-	help
-	  Enable the host commands shim in platform/ec. This handles
-	  communication with the AP. The AP sends a command to the EC and it
-	  responds when able. An interrupt can be used to indicate to the AP
-	  that the EC has something for it.
-
-config PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
-	bool "Host command: EC_CMD_GET_UPTIME_INFO"
-	default PLATFORM_EC_HOSTCMD
-	help
-	  Enable the EC_CMD_GET_UPTIME_INFO host command which reports the time
-	  the EC has been powered up, the number of AP resets, an optional log
-	  of AP-reset events and some flags.
-
-config PLATFORM_EC_HOSTCMD_REGULATOR
-	bool "Host command of voltage regulator control"
-	help
-	  Enable host commands (EC_CMD_REGULATOR_) for controlling voltage
-	  regulator. The board should also implement board functions defined in
-	  include/regulator.h.
-
-choice PLATFORM_EC_HOSTCMD_DEBUG_MODE
-	prompt "Select method to use for HostCmd Debug Mode"
-	depends on PLATFORM_EC_HOSTCMD
-	default HCDEBUG_NORMAL
-	help
-	  Sets the value of the host command debug mode to use on
-	  startup.
-
-config HCDEBUG_OFF
-	bool "Host command debug mode OFF"
-	help
-	  No host command debug messages are shown.  Host
-	  command error messages will still output.
-
-config HCDEBUG_NORMAL
-	bool "Host command debug mode NORMAL"
-	help
-	  Display host commands receieved from the AP. Repeated
-	  commands are shown with a "+" and "++" symbol.
-
-config HCDEBUG_EVERY
-	bool "Host command debug mode EVERY"
-	help
-	  Display all host commands received from the AP,
-	  including repeated commands.
-
-config HCDEBUG_PARAMS
-	bool "Host command debug mode PARAMS"
-	help
-	  Display all host commands and the parameters received
-	  from the AP.
-
-endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE
-
-config PLATFORM_EC_I2C
-	bool "I2C shim"
-	default n if ARCH_POSIX
-	default y
-	imply I2C
-	help
-	  Enable compilation of the EC i2c module. Once enabled, it will be
-	  possible to make calls using the old platform/ec i2c APIs defined
-	  in include/i2c.h and implemented in common/i2c_master.c. Doing so
-	  should make shimming other platform/ec modules which rely on i2c
-	  communication "just work" without requiring any further code changes.
-
-config PLATFORM_EC_I2C_DEBUG
-	bool "I2C Tracing"
-	default n if ARCH_POSIX
-	depends on PLATFORM_EC_I2C
-	help
-	  This option enables I2C bus communication tracing. Use the console
-	  command "i2ctrace" to enable and disable tracing on specific I2C
-	  peripherals.
-
-	  Please see the I2C debugging documentation for more details:
-
-	  https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/docs/i2c-debugging.md
-
-config PLATFORM_EC_I2C_DEBUG_PASSTHRU
-	bool "I2C Passthru Debug"
-	default n if ARCH_POSIX
-	depends on PLATFORM_EC_I2C
-	help
-	  This option enables extra debug for I2C passthru operations initiated
-	  by the AP.
-
-config PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP
-	bool "Console command: i2c_portmap"
-	default y
-	depends on PLATFORM_EC_I2C
-	help
-	  Enable the 'i2c_portmap' console command. This comamnd is used to
-	  display the mapping of the I2C ports defined by the named-i2c-ports
-	  node to the physical port and remote port indexes.
-
-config PLATFORM_EC_CONSOLE_CMD_I2C_SPEED
-	bool "Console command: i2cspeed"
-	default n
-	depends on PLATFORM_EC_I2C
-	help
-	  Enable the 'i2cspeed' console command. This comamnd is used to
-	  display an I2C port's bus speed. Additionally, for ports with
-	  the DYNAMIC_SPEED port flag set, the speed can be set. In all
-	  cases, the bus speed is in units of kHz.
-
-config PLATFORM_EC_SMBUS_PEC
-	bool "Packet error checking support for SMBus"
-	help
-	  If enabled, adds error checking support for i2c_readN, i2c_writeN,
-	  i2c_read_string and i2c_write_block. Where
-	  - write operation appends an error checking byte at end of transfer, and
-	  - read operatoin verifies the correctness of error checking byte from the
-	  slave.
-	  Set I2C_FLAG on addr_flags parameter to use this feature.
-
-	  This option also enables error checking function on smart batteries.
-
-config PLATFORM_EC_LID_SWITCH
-	bool "Lid switch"
-	help
-	  Enable shimming the lid switch implementation and related
-	  commands in platform/ec. The lid switch can affect power-on
-	  behaviour. For example, when the lid is opened, the device may
-	  automatically power on.
-
-	  This requires a GPIO named GPIO_LID_OPEN to be defined in gpio_map.h.
-
-config PLATFORM_EC_MKBP_INPUT_DEVICES
-	bool "Input devices via MKBP"
-	help
-	  Enable passing events from various input sources to AP via MKBP.
-	  This include buttons (power, volume); switches (lid, tablet mode)
-	  and sysrq.
-
-config PLATFORM_EC_LOW_POWER_IDLE
-	bool
-	default y if PM
-	help
-	  Enable low power idle modes in the EC chipset. This is automatically
-	  enabled when the Zephyr power management options are enabled with the
-	  PM option.
-
-config PLATFORM_EC_MKBP_EVENT
-    bool "MKBP event"
-    help
-      Enable this to support MKBP event. MKBP event is used not only
-      for matrix keyboard but also for other many events like button,
-      switch, fingerprint, and etc.
-
-      This requires a MKBP event delivery method(GPIO, HOST_EVENT, and etc)
-
-config PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK
-    bool "MKBP event wakeup mask"
-    depends on PLATFORM_EC_MKBP_EVENT
-    help
-      Enable which MKBP events should wakeup the system in suspend.
-      For example:
-        The MKBP events are enabled in the devicetree by the wakeup-mask
-        property of the ec-mkbp-event-wakeup-mask node as follows:
-        wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
-                          MKBP_EVENT_HOST_EVENT | \
-                          MKBP_EVENT_SENSOR_FIFO)>;
-      The mkbp events are defined in dt-bindings/wake_mask_event_defines.h
-
-config PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK
-    bool "MKBP host event wakeup mask"
-    depends on PLATFORM_EC_MKBP_EVENT
-    help
-      Enable which host events should wakeup the system in suspend.
-      For example:
-        The host events are enabled in the devicetree by the wakeup-mask
-        property of the ec-mkbp-host-event-wakeup-mask node as follows:
-          wakeup-mask = <(HOST_EVENT_LID_OPEN | \
-                          HOST_EVENT_POWER_BUTTON | \
-                          HOST_EVENT_AC_CONNECTED)>;
-      The host events are defined in dt-bindings/wake_mask_event_defines.h
-
-config PLATFORM_EC_MPU
-	bool "Support Memory-Protection Unit (MPU)"
-	depends on CPU_CORTEX_M
-	select ARM_MPU
-	default y
-	help
-	  This enables support a Memory-Protection Unit which can limit access
-	  to certain areas of memory. This can be used to protect code or data
-	  from being written to improve security or to find bugs.
-
-	  It causes any code in the iram.text section to be protected when
-	  system jump is disabled (see system_disable_jump()). It also stops
-	  execution of the image that is not currently being executed (read-only
-	  or read-write). If internal storage is used, this is achieved by not
-	  allowing code execution in that area. For external storage, it
-	  disallows loading any code into RAM.
-
-config PLATFORM_EC_PANIC
-	bool "Panic output"
-	default y
-	help
-	  Enable support for collecting and reporting panic information,
-	  caused by exceptions in the EC. This can be the result of a watchdog
-	  firing, a division by zero, unaligned access, stack overflow or
-	  assertion failure.
-
-	  The panic information is made available to the AP via the
-	  EC_CMD_GET_PANIC_INFO host command and a 'panicinfo' console command
-
-config PLATFORM_EC_PORT80
-	bool "Port 80 support"
-	default y if AP_X86 && PLATFORM_EC_POWERSEQ
-	help
-	  Enable the port80 module, a way to report progress of the AP's boot
-	  sequence, assuming that the EC can detect these writes on the I/O
-	  bus. The EC buffers calls to port_80_write() and occasionally prints
-	  a message when there are new writes.
-
-	  See here for more information:
-
-	  https://en.wikipedia.org/wiki/Power-on_self-test#Progress_and_error_reporting
-
-config PLATFORM_EC_POWER_BUTTON
-	bool "Power-button support"
-	depends on PLATFORM_EC_HOSTCMD
-	help
-	  Enable shimming the power button implementation and related
-	  commands in platform/ec.  This is used to implement the Chromium OS
-	  shutdown sequence.
-
-	  This requires a GPIO named GPIO_POWER_BUTTON_L in gpio_map.h.
-
-config PLATFORM_EC_PWM
-	bool "PWM (Pulse Width Modulation) module"
-	help
-	  Enable the PWM (Pulse Width Modulation) module. This module is used to
-	  support variable brightness LEDs, backlight controls, and
-	  variable-speed fans.
-
-config PLATFORM_EC_PWM_DISPLIGHT
-	bool "PWM display backlight"
-	depends on PLATFORM_EC_PWM
-	help
-	  Enables display backlight controlled by a PWM signal connected
-	  directly to the EC chipset. The board files must define the C
-	  reference PWM_CH_DISPLIGHT to the PWM channel used for the
-	  display backlight control.
-
-config PLATFORM_EC_RTC
-	bool "Real-time clock (RTC)"
-	help
-	  Enable support for a real-time clock. Typically this is available
-	  on-chip in the EC. It provides a way to track the passage of time
-	  in terms of second and minutes. Once set, and provided that it has a
-	  suitable power source, it should be able to keep reasonably accurate
-	  time over a period of days and weeks.
-
-	  The starting EC clock is typically set by the AP, since it has access
-	  to the outside world and can often obtain the current time when
-	  desired.
-
-choice "SHA256 method"
-	prompt "Select method to use for computing SHA256 hashes"
-	help
-	  The verified boot mechanism requests the hash of the entire read-write
-	  portion of the EC image. This is typically done using a hashing block
-	  in the EC, so that it is as fast as possible. A fallback software
-	  algorithm is available if needed.
-
-config PLATFORM_EC_SHA256_SW
-	bool "Compute SHA256 in software"
-	help
-	  Enable this if your EC chip does not support hardware-accelerated
-	  SHA256 computation. This enables the software algorithm which is
-	  quite slow but will work in a pinch.
-
-config PLATFORM_EC_SHA256_HW_ACCELERATE
-	bool "Compute SHA256 in hardware"
-	help
-	  Enable this if your EC chip supports hardware-accelerated SHA256
-	  computation. This is faster than running the algorithm in software,
-	  so is desirable.
-
-	  The chip support must implement the functions in sha256.h
-
-endchoice # SHA256 method
-
-config PLATFORM_EC_SWITCH
-	bool "Memory mapped switches"
-	depends on PLATFORM_EC_HOSTCMD
-	default y
-	help
-	  Enable the reporting of the platform switches state to the AP using
-	  memory mapped storage provided by the host command interface.
-
-	  The platform switches include:
-	    LID open
-	    power button pressed
-	    write protect disabled
-	    recovery switch
-
-          This also enables the "mmapinfo" console command to report the current
-          state of all switches.
-
-choice PLATFORM_EC_SWITCHCAP_TYPE
-	prompt "Enable switchcap support"
-	optional
-	help
-	  Enable support for switchcap used to power on the AP.
-	  If enabled, type of switchcap must be selected and node in device
-	  tree must be added that describes the driver and pins used to control
-	  the switchcap.
-
-config PLATFORM_EC_SWITCHCAP_GPIO
-	bool "GPIO controlled switchcap"
-	help
-	  Enable support for the GPIO controlled switchcap.
-	  Pins used for controlling the switchcap must be defined in board's
-	  device tree.
-
-config PLATFORM_EC_SWITCHCAP_LN9310
-	bool "LN9310 switchcap driver"
-	depends on PLATFORM_EC_I2C
-	help
-	  Enable support for the LION Semiconductor LN9310 switched
-	  capacitor converter.  This will export definitions for
-	  ln9310_init, ln9310_interrupt, and ln9310_power_good, which
-	  project-specific code should call appropriately if there's
-	  no switchcap node in device tree.
-
-endchoice
-
-config PLATFORM_EC_SYSTEM_UNLOCKED
-	bool "System unlocked: allow dangerous commands while in development"
-	default y if PLATFORM_EC_BRINGUP
-	help
-	  System should remain unlocked even if write protect is enabled.
-
-	  NOTE: This should ONLY be defined during bringup, and should never be
-	  defined on a shipping / released platform.
-
-	  When defined, CBI allows ectool to reprogram all the fields.
-	  Normally, it refuses to change certain fields. (e.g. board version,
-	  OEM ID)
-
-	  Also, this enables PD in RO for TCPMv2.
-
-config PLATFORM_EC_THROTTLE_AP
-	bool "CPU throttling"
-	help
-	  Enable throttling the CPU based on the temperature sensors. When they
-	  detect that the CPU is getting too hot, the CPU is throttled to
-	  a lower speed. This reduce the CPU's power output and eventually
-	  results in a lower temperature.
-
-menuconfig PLATFORM_EC_TIMER
-	bool "Timer module"
-	default y
-	help
-	  Enable compilation of the EC timer module. This provides support for
-	  delays, getting the current time and setting alarms.
-
-	  This option is needed by many features in the EC. Disabling it will
-	  likely cause build errors.
-
-config PLATFORM_EC_VBOOT_EFS2
-	bool "EFS2 verified EC boot"
-	default y if !SOC_POSIX
-	help
-	  Enables Early Firmware Selection v2 (EFS2) verified boot. When booting
-	  a Chromium OS image we're actually packing both an RO image and an RW
-	  image into flash. The RO image is loaded first. EFS2 runs at boot and
-	  verifies the integrity of the RW image by sending a hash of the image
-	  to the Google Security Chip (GSC). Once the GSC verifies the hash,
-	  EFS2 calls sysjump and reboot the EC using the RW image.
-
-config PLATFORM_EC_VBOOT_HASH
-	bool "Host command: EC_CMD_VBOOT_HASH"
-	depends on PLATFORM_EC_HOSTCMD
-	default y
-	help
-	  Allows the AP to request hashing functions from the EC.
-
-	  Verified boot can update the EC's read/write code when it detects
-	  that it is an incorrect version. It detects this by asking the EC to
-	  hash itself. If the hash is incorrect, new code is write to the EC's
-	  read/write area.
-
-config PLATFORM_EC_VSTORE
-	bool "Secure temporary storage for verified boot"
-	default y
-	help
-	  Enable support for storing a block of data received from the AP so it
-	  can be read back later by the AP. This is helpful since the AP may
-	  reboot or resume and want the data early in its start-up before it
-	  has access to SDRAM.
-
-	  There are a fixed number of slots and each can hold a fixed amount of
-	  data (EC_VSTORE_SLOT_SIZE bytes). Once a slot is written it is locked
-	  and cannot be written again unless explicitly unlocked.
-
-	  Stored data is preserved when the EC moved from RO to RW.
-
-config PLATFORM_EC_VSTORE_SLOT_COUNT
-	int "Number of slots"
-	depends on PLATFORM_EC_VSTORE
-	default 1
-	help
-	  Set the number of slots available in the verified-boot store. The
-	  number required depends on the AP firmware. Typically the vstore is
-	  used only for recording a hash of the read-write AP firmware for
-	  checking on resume. For this, one slot is enough.
-
-menuconfig PLATFORM_EC_WATCHDOG
-	bool "Watchdog"
-	depends on WATCHDOG
-	default y
-	help
-	  Enable the watchdog functionality. The watchdog timer will reboot the
-	  system if the hook task (which is the lowest-priority task on the
-	  system) gets starved for CPU time and isn't able to fire its
-	  HOOK_TICK event.
-
-	  Chromium EC system uses an auxiliary timer to handle the system
-	  warning event. This leaves some time to the system for preparing &
-	  printing the debug information. The interval between reloads of the
-	  watchdog timer should be less than half of the auxiliary timer
-	  (PLATFORM_EC_WATCHDOG_PERIOD_MS -
-	  PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS).
-
-config PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API
-	bool "Workaround needed for npcx9 ES1 chip"
-	depends on SOC_SERIES_NPCX9
-	help
-	  There's a bug in the flash download API on the ES1 version of the
-	  npcx9 chips that requires some workarounds. This is needed for sysjump
-	  to work properly.
-
-config PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT
-	bool "Assert CCD Mode"
-	help
-	  Assert CCD_MODE_ODL when a DTS debug accessory is connected to the
-	  CCD USBC port. GPIO_CCD_MODE_ODL should be configured with
-	  GPIO_ODR_HIGH flag.
-
-config PLATFORM_EC_CCD_USBC_PORT_NUMBER
-	int "CCD USB Port Number"
-	default 0
-	help
-	  USB port number of the CCD enabled USBC port.
-
-config PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-	bool "Restrict I2C PASSTHRU command"
-	depends on PLATFORM_EC_I2C
-	help
-	  Enables board-specific restrictions for the I2C PASSTHRU host command.
-	  Once enabled, board_allow_i2c_passthru function has to be implemented,
-	  which defines the allowed usage of the command.
-
-config PLATFORM_EC_HOST_COMMAND_STATUS
-	bool "Return in-progress status for slow host commands"
-	default n
-	help
-	  When the AP is attached to the EC via a serialized bus such as I2C or
-	  SPI, it needs a way to minimize the length of time an EC command will
-	  tie up the bus (and the kernel driver on the AP). If this config is
-	  defined, the EC may return an in-progress result code for slow
-	  commands such as flash erase/write instead of stalling until the
-	  command finishes processing, and the AP may then inquire the status
-	  of the current command and/or the result of the previous command.
-
-config PLATFORM_EC_AMD_SB_RMI
-	bool "Enable driver for AMD SB-RMI interface"
-	help
-	  AMD platforms provide the Side-Band Remote Management Interface.
-	  SB-RMI provides an interface for an external SMBus master to perform
-	  tasks such as managing power consumption and power limits of the CPU
-	  socket.
-
-config PLATFORM_EC_AMD_STT
-	bool "Enable driver for AMD STT interface"
-	depends on PLATFORM_EC_AMD_SB_RMI
-	help
-	  AMD platforms provide the Skin Temperature Tracking (STT) interface.
-	  Skin temperature management can be used to maximize the system
-	  performance while keeping the skin temperature within its
-	  specification. It makes use of the thermal capacitance of the system
-	  to temporarily boost above the sustainable power limit, while the
-	  chassis skin temperatures are below limits.
-
-endif # PLATFORM_EC
diff --git a/zephyr/Kconfig.accelgyro_bmi b/zephyr/Kconfig.accelgyro_bmi
deleted file mode 100644
index bb8239f6d8..0000000000
--- a/zephyr/Kconfig.accelgyro_bmi
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-
-if PLATFORM_EC_ACCELGYRO_BMI
-menu "BMI Sensor Common"
-
-choice PLATFORM_EC_ACCELGYRO_BMI_COMM
-	prompt "Accelgyro BMI's communication mode"
-	help
-	  When using the BMI drivers, there's the option to communicate with the
-	  chip via several methods. This choice helps improve code size by only
-	  compiling the needed communication channels.
-
-config PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI
-	bool "Use SPI communication"
-	help
-	  The BMI chip is using SPI communication. This config value is used to
-	  save on code size as only the SPI communication code will be included
-	  for the BMI chip.
-
-config PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C
-	bool "Use I2C communication"
-	help
-	  The BMI chip is using I2C communication. This config value is used to
-	  save on code size as only the I2C communication code will be included
-	  for the BMI chip.
-
-endchoice
-
-endmenu # BMI Sensor
-endif # PLATFORM_EC_ACCELGYRO_BMI
\ No newline at end of file
diff --git a/zephyr/Kconfig.accelgyro_icm b/zephyr/Kconfig.accelgyro_icm
deleted file mode 100644
index 2bee9184b5..0000000000
--- a/zephyr/Kconfig.accelgyro_icm
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-
-if PLATFORM_EC_ACCELGYRO_ICM
-menu "ICM Sensor Common"
-
-choice PLATFORM_EC_ACCELGYRO_ICM_COMM
-	prompt "Accelgyro ICM's communication mode"
-	help
-	  When using the ICM drivers, there's the option to communicate with the
-	  chip via several methods. This choice helps improve code size by only
-	  compiling the needed communication channels.
-
-config PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI
-	bool "Use SPI communication"
-	help
-	  The ICM chip is using SPI communication. This config value is used to
-	  save on code size as only the SPI communication code will be included
-	  for the ICM chip.
-
-config PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C
-	bool "Use I2C communication"
-	help
-	  The ICM chip is using I2C communication. This config value is used to
-	  save on code size as only the I2C communication code will be included
-	  for the ICM chip.
-
-endchoice
-
-endmenu # ICM Sensor
-endif # PLATFORM_EC_ACCELGYRO_ICM
\ No newline at end of file
diff --git a/zephyr/Kconfig.adc b/zephyr/Kconfig.adc
deleted file mode 100644
index a1e3bd63eb..0000000000
--- a/zephyr/Kconfig.adc
+++ /dev/null
@@ -1,62 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_ADC
-	bool "ADC shim"
-	default n if ARCH_POSIX
-	default y
-	imply ADC
-	help
-	  Enable compilation of the EC ADC module. Once enabled, it is
-	  possible to call platform/ec adc_read_channel() function.
-
-if PLATFORM_EC_ADC
-
-# Chromium EC provides it's own "adc" command.  Disable the Zephyr
-# built-in ADC shell command.
-# TODO(b:188434233) Investigate moving to zephyr adc shell
-config ADC_SHELL
-	default n
-
-config PLATFORM_EC_ADC_CMD
-	bool "ADC host/console command"
-	default y
-	help
-	  Enables support for printing ADC channels state with the "adc"
-	  console command and reading a state of ADC channel with the
-	  EC_CMD_ADC_READ host command. Replaces generic Zephyr "adc"
-	  command.
-
-config PLATFORM_EC_ADC_RESOLUTION
-	int "ADC resolution"
-	default 10
-	help
-	  The resolution, in bits, to use for the ADC conversion. Determines
-	  the sample values range: 0 .. 2^resolution -1. The supported
-	  resolution values depend on specific hardware.
-
-config PLATFORM_EC_ADC_OVERSAMPLING
-	int "ADC oversampling"
-	default 0
-	help
-	  ADC oversampling to use for the ADC conversion. Each sample is
-	  averaged from 2^oversampling conversion results. Oversampling can
-	  help in providing more stable readings. The supported oversampling
-	  values depend on specific hardware.
-
-config PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
-	bool "ADC runtime config"
-	default n
-	help
-	  Allows the configuration of the ADC channels to be set up at
-	  runtime. This makes the adc_channels[] array writable,
-	  i.e. not const. It should be declared as such in the board
-	  config.
-
-	  This is useful when the board has runtime information that
-	  changes the configuration, such as board revision information.
-	  Without this, multiple EC images would need to be installed
-	  depending on the board.
-
-endif # PLATFORM_EC_ADC
diff --git a/zephyr/Kconfig.battery b/zephyr/Kconfig.battery
deleted file mode 100644
index c1753ccefc..0000000000
--- a/zephyr/Kconfig.battery
+++ /dev/null
@@ -1,491 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_BATTERY
-	bool "Battery support"
-	select HAS_TASK_CHARGER
-	help
-	  Enables battery support on the board. Requires selection of a battery
-	  and a charger IC.
-
-	  If using I2C batteries, you must define I2C_PORT_BATTERY in your
-	  board's i2c_map.h file so that the EC code will know which I2C
-	  port the battery is on.
-
-if PLATFORM_EC_BATTERY
-
-choice "Battery select"
-	prompt "Select the battery to use"
-	help
-	  Select the battery used on the board. If you are ensure, select the
-	  smart battery option.
-
-config PLATFORM_EC_BATTERY_SMART
-	bool "Support a smart battery"
-	depends on PLATFORM_EC_I2C
-	help
-	  Many batteries support the Smart Battery Specification and therefore
-	  have common registers which can be accessed to control and monitor
-	  the battery.
-
-	  See here for the spec: http://sbs-forum.org/specs/sbdat110.pdf
-
-endchoice
-
-choice "Battery presence detection"
-	prompt "Method to use to detect the battery"
-	help
-	  This selects the method to use to detect the presence of a battery.
-
-	  Battery detection is important since it can be used to indicate that
-	  the case is open, so security features can be disabled. It is also
-	  useful to report to the user when the battery is missing, e.g. with
-	  a desktop icon.
-
-config PLATFORM_EC_BATTERY_PRESENT_CUSTOM
-	bool "Call a board-provided function"
-	help
-	  Use this method to provide a board-provided battery_is_present()
-	  function to determine whether the battery is currently present.
-	  This should be implemented in the board code and can use any
-	  reasonable method to detect the battery.
-
-config PLATFORM_EC_BATTERY_PRESENT_GPIO
-	bool "Check a GPIO"
-	help
-	  Use this method if a GPIO signals whether the battery is present. The
-	  GPIO should read low if the battery is present, high if absent.
-
-	  The GPIO is hard-coded to GPIO_BATT_PRES_ODL so you should define this
-	  in the device tree and GPIO map. The convention is to use the signal
-	  name from schematic as both the node name and label for the GPIO. For
-	  example:
-
-	    /* gpio.dts */
-	    ec_batt_pres_odl {
-	    	gpios = <&gpioe 5 GPIO_INPUT>;
-	    	label = "EC_BATT_PRES_ODL";
-	    };
-
-	    /* gpio_map.h */
-	    #define GPIO_BATT_PRES_ODL		NAMED_GPIO(ec_batt_pres_odl)
-
-endchoice  # battery presence
-
-config PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
-	bool "Provide information about battery chemistry"
-	help
-	  Enable this to specify the chemistry of the battery device. It is
-	  only used for stress testing of reading the battery information over
-	  I2C.
-
-config PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY
-	string "Battery-device chemistry"
-	depends on PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
-	help
-	  Specify the battery chemistry for use with the I2C stress test.
-	  The value provided here must match what is read from the real
-	  battery. This is used in sb_i2c_test_read() to check that the battery
-	  is returning the right information. If it is not, there might be
-	  something wrong with the I2C implementation.
-
-config PLATFORM_EC_I2C_VIRTUAL_BATTERY
-	bool "I2C virtual battery"
-	help
-	  Enables driver for a virtual battery. It is used to minimalize I2C
-	  traffic which is generated by the I2C_PASSTHRU host command.
-	  The battery parameters, which are already cached in EC are used to
-	  return desired data to host instead of issuing I2C transaction every
-	  time.
-
-choice "Charger select"
-	prompt "Select the charger to use"
-	help
-	  Select the battery charger IC used on the board. Only one charger may
-	  be selected.
-
-config PLATFORM_EC_CHARGER_ISL9237
-	bool "Use the ISL9237 charger"
-	depends on PLATFORM_EC_I2C
-	select PLATFORM_EC_CHARGER_NARROW_VDC
-	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
-	help
-	  Enables a driver for the ISL9237 VCD Battery Charger. This is a
-	  digitally-configurable, buck-boost battery charger that supporting
-	  Narrow Voltage Direct Charging (NVDC). It supports an input voltage
-	  range of 3.2-23.4V and output of 2.4-13.8V. It provides an I2C
-	  interface for configuration an provides a USB On-The-Go (OTG)
-	  function for 2- and 3-cell battery applications.
-
-config PLATFORM_EC_CHARGER_ISL9238
-	bool "Use the ISL9238 charger"
-	depends on PLATFORM_EC_I2C
-	select PLATFORM_EC_CHARGER_NARROW_VDC
-	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
-	help
-	  Enables a driver for the ISL9238 VCD Battery Charger. This is a
-	  digitally-configurable, buck-boost battery charger that supporting
-	  Narrow Voltage Direct Charging (NVDC). It supports an input voltage
-	  range of 3.2-23.4V and output of 2.4-18.3V. It provides an I2C
-	  interface for configuration.
-
-config PLATFORM_EC_CHARGER_ISL9238C
-	bool "Use the ISL9238 Rev C charger"
-	depends on PLATFORM_EC_I2C
-	select PLATFORM_EC_CHARGER_NARROW_VDC
-	select PLATFORM_EC_CHARGER_OTG_SUPPORTED
-	help
-	  Enable a driver for the ISL9238 Rev C VCD Battery Charger. This
-	  is a digitally-configurable, buck-boost battery charger that
-	  supporting Narrow Voltage Direct Charging (NVDC). It supports an input
-	  voltage range of 3.2-23.4V and output of 2.4-18.3V. It provides an I2C
-	  interface for configuration.
-
-	  This option is separate from PLATFORM_EC_CHARGER_ISL9238 since there
-	  is no way in software to distinguish between rev. A/B and rev. C.
-
-config PLATFORM_EC_CHARGER_ISL9241
-	bool "Use the ISL9241 charger"
-	depends on PLATFORM_EC_I2C
-	# Hardware based charge ramp is broken in the ISL9241 (b/169350714)
-	select PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
-	help
-	  Enables a driver for the ISL9241 VCD Battery Charger. This is a
-	  digitally-configurable, buck-boost battery charger that can support
-	  both Narrow Voltage Direct Charging (NVDC) and Hybrid Power Buck Boost
-	  (HPBB/Bypass) charging and switch between the modes under firmware
-	  control. It supports an input voltage range of 3.9-23.4V and output
-	  of 3.9-18.3V. It provides an I2C interface for configuration.
-
-config PLATFORM_EC_CHARGER_BQ25710
-	bool "Use the BQ25710 charger"
-	depends on PLATFORM_EC_I2C
-	select PLATFORM_EC_CHARGER_NARROW_VDC
-	help
-	  Enables the driver for the TI BQ25710 battery charger
-	  controller. This is a synchronous narrow voltage DC buck-boost
-	  battery charger for one to four battery cell applications. A
-	  wide range of input power sources are supported such as high
-	  voltage USB-C power delivery.
-
-config PLATFORM_EC_CHARGER_BQ25720
-	bool "Use the BQ25720 charger"
-	depends on PLATFORM_EC_I2C
-	select PLATFORM_EC_CHARGER_NARROW_VDC
-	help
-	  Enables the driver for the TI BQ25720 battery charger
-	  controller. This is a synchronous narrow voltage DC buck-boost
-	  battery charger for one to four battery cell applications. A
-	  wide range of input power sources are supported such as high
-	  voltage USB-C power delivery.
-
-endchoice  # "Charger select"
-
-config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
-	bool "Board supports discharge mode"
-	help
-	  Enable this if the board supports discharging the battery even when
-	  AC power is present. This is used for testing. The function is
-	  provided either by the charger or by custom code in the board.
-
-if PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
-
-choice "Discharge control method"
-	prompt "Select the method of controlling discharge"
-	help
-	  Select which method is provided to enable and disable the discharge
-	  mode.
-
-config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER
-	bool "Charger controls discharge mode"
-	help
-	  Enable this if the charger controls selection of discharge mode.
-	  In this case the charger must provide a function:
-
-	     int charger_discharge_on_ac(int enabled)
-
-	  It should enable this feature if enabled is true, else disable it.
-	  The function should return EC_SUCCESS
-
-config PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CUSTOM
-	bool "Custom control of discharge mode"
-	help
-	  Enable this if the discharge mode is controlled by a custom function.
-	  This function is typically provided by the board implementation:
-
-	     int board_discharge_on_ac(int enabled)
-
-	  It should enable this feature if enabled is true, else disable it.
-	  The function should return EC_SUCCESS
-
-endchoice  # "Discharge control method"
-
-endif  # PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
-
-config PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-	bool "VSYS_TH2 override"
-	depends on PLATFORM_EC_CHARGER_BQ25720
-	help
-	  Enable customizing the charger's VSYS_TH2 threshold.
-
-config PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV
-	int "VSYS threshold 2 in deci-volts"
-	range 32 95
-	default 32
-	depends on PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-	help
-	  Sets the VSYS threshold 2 in deci volts. This is the first
-	  threshold that will be encountered when VSYS droops, typically
-	  due to high power demand from the main processor. The charger
-	  chip reacts by asserting PROCHOT which the main processor uses
-	  as an indication to throttle back and reduce power demand. The
-	  charger chip uses default thresholds which may be low enough
-	  to cause system instability. The default for 1S batteries is
-	  3.2v and 5.9v for 2S or higher batteries.  The valid range is
-	  3.2v - 3.9v for 1S and 3.2 - 9.5v for 2S or higher batteries.
-
-config PLATFORM_EC_CHARGER_MAINTAIN_VBAT
-	bool "Maintain VBAT voltage regardless of AC state"
-	help
-	  Leave the charger VBAT configured to battery-requested voltage under
-	  all conditions, even when AC is not present. This may be necessary to
-	  work around quirks of certain charger chips, such as the BD9995X.
-
-config PLATFORM_EC_CHARGER_NARROW_VDC
-	bool
-	help
-	  Select this if the charger uses a Narrow Voltage Direct Charging.
-	  Narrow VDC (NVDC) reduces power loss by reducing the voltage range of
-	  the VDC node. This reduction is accomplished by replacing the
-	  battery-charger circuit with a system-charger voltage regulator, thus
-	  narrowing the VDC range. This in turn enables DC/DC converter
-	  optimisations in the system and allows the removal of the power-path
-	  switch, saving additional power, board area, and cost.
-
-	  This should be enabled by charger drivers which need it. It cannot
-	  be set otherwise, even in prj.conf
-
-config PLATFORM_EC_CHARGER_OTG_SUPPORTED
-	bool
-	help
-	  Indicates that the charger supports an OTG (On-The-Go) function,
-	  which allows supplying output power from the battery to a connected
-	  device.
-
-	  This should be enabled by charger drivers which support it. It cannot
-	  be set otherwise, even in prj.conf
-
-config PLATFORM_EC_CHARGER_OTG
-	bool "Allow supplying output power from the battery"
-	depends on PLATFORM_EC_CHARGER_OTG_SUPPORTED
-	help
-	  Enable charger's OTG functions, i.e. make it possible to supply
-	  output power from the battery. This option is available if the
-	  selected charger supports it.
-
-config PLATFORM_EC_CHARGER_PROFILE_OVERRIDE
-	bool "Override the charger profile"
-	help
-	  Select this if the charger should call battery_override_params() to
-	  limit/correct the voltage and current requested by the battery pack
-	  before acting on the request.
-
-	  The board must provide this function:
-
-	    void battery_override_params(struct batt_params *batt);
-
-	  It may modify the parameters as needed.
-
-config PLATFORM_EC_CHARGER_PSYS
-	bool "Support system power-monitor (PSYS) function"
-	help
-	  Enable this to support monitoring of system power using the charger's
-	  PSYS function. The charger provides an output which can be read
-	  using an ADC channel on the EC.
-
-config PLATFORM_EC_CHARGER_PSYS_READ
-	bool "Allow reading PSYS (system power) value"
-	depends on PLATFORM_EC_CHARGER_PSYS
-	help
-	  Enable support for reading the system-power value (PSYS). This
-	  calls the function charger_get_system_power() which is provided
-	  by the charger.
-
-	  It also enables the "psys" console command.
-
-	  Sample output:
-
-	    PSYS from chg_adc: 456 mW
-
-config PLATFORM_EC_CHARGER_SENSE_RESISTOR
-	int "Value of the charge sense-resistor, in mOhms"
-	help
-	  The charge sense-resistor is used to detect the charge current to the
-	  battery. Its value must be known for the calculation to be correct.
-	  The value is typically around 10 mOhms.
-
-config PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
-	int "Value of the input sense-resistor, in mOhms"
-	help
-	  The input sense-resistor is used to detect the input current from the
-	  external AC power supply. Its value must be known for the calculation
-	  to be correct. The value is typically around 10 mOhms.
-
-config PLATFORM_EC_BATTERY_FUEL_GAUGE
-	bool "Board supplies battery info"
-	help
-	  The fuel gauge information is used to cut off the battery for shipping
-	  mode and to check the charge/discharge FET status.  The battery
-	  information is used to set voltage, current and temperature operating
-	  limits for the battery.
-
-config PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
-	bool
-	help
-	  This is selected if the charger's support for hardware-controlled
-	  charge ramping is broken. In some cases the charger has problems
-	  which make it unusable and we must fall back to software-controlled
-	  charge ramping.
-
-	  This should be enabled by charger drivers which need it. It cannot
-	  be set otherwise, even in prj.conf
-
-choice "Charge-ramp method"
-	prompt "Select the charge-ramp method"
-	help
-	  Select the method used for ramping up charging of a battery. It is
-	  preferred to use the hardware method if the charger chip can support
-	  it. If not, software-controlled charging can be used, with a slight
-	  increase in code size.
-
-config PLATFORM_EC_CHARGE_RAMP_HW
-	bool "Hardware-controlled charging"
-	depends on !PLATFORM_EC_CHARGER_CHGRAMP_BROKEN
-	help
-	   Disables software control of ramping up charging. This is used when
-	   the hardware has a a mechanism for ramping input current and
-	   backing-off as needed.
-
-config PLATFORM_EC_CHARGE_RAMP_SW
-	bool "Software-controlled charging"
-	select HAS_TASK_CHG_RAMP
-	help
-	  Enables ramping up charging from an external source to the maximum
-	  available within the source's limits and taking into account the
-	  current needs of the device. It handles the user plugging chargers in
-	  and removing them.
-
-endchoice  # "Charge-ramp method"
-
-config PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
-	bool "Console command: amonbmon"
-	help
-	  Enable the 'amonbmon' command. This shows the charger adapter-current
-	  monitor (AMON) and battery-charging current monitor (BMON).
-
-	     amonbmon a | b
-
-config PLATFORM_EC_CONSOLE_CMD_CHGRAMP
-	bool "Console command: chgramp"
-	depends on PLATFORM_EC_CHARGE_RAMP_SW
-	default y
-	help
-	  Enable the "chgramp" command. This shows the current state of the
-	  chg_ramp task. It shows the state of each port and the current limit
-	  for each port. The 'State' shown is from enum chg_ramp_state.
-
-	  Chg Ramp:
-	    State: 5
-	    Min ICL: 2000
-	    Active ICL: 2000
-	    Port 0:
-	      OC idx:0
-	      OC 0: s-1 oc_det0 icl0
-	      OC 1: s0 oc_det0 icl0
-	      OC 2: s0 oc_det0 icl0
-	    Port 1:
-	      OC idx:0
-	      OC 0: s-1 oc_det0 icl0
-	      OC 1: s0 oc_det0 icl0
-	      OC 2: s0 oc_det0 icl0
-
-config PLATFORM_EC_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-	bool "Enable battery cut off on critical power level"
-	help
-	  If this option is enabled, the battery will enter cut-off
-	  mode in case of critical power level.
-
-config PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-	bool "Monitor battery temperature while charging"
-	help
-	  Enable monitoring of battery temperature while charging and
-	  stop charging if is outside of the safe range.
-
-config PLATFORM_EC_BATTERY_CUT_OFF
-	bool "Host/Console command: battery cut-off"
-	help
-	  Enables support for disconnecting the battery using the "cutoff"
-	  console command and the EC_CMD_BATTERY_CUT_OFF host command.
-	  Once defined, a board specific board_cut_off_battery() function
-	  has to be provided.
-
-config PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM
-	bool "Hardware check of battery presence"
-	help
-	  Once defined, the charger will check a board specific function
-	  battery_hw_present() for battery hw presence as an additional
-	  condition to determine if power on is allowed for factory override,
-	  where allowing booting of a bare board with no battery and no power
-	  button press is required.
-
-config PLATFORM_EC_BATTERY_REVIVE_DISCONNECT
-	bool "Check battery disconnect state"
-	help
-	  Check for battery in disconnect state (similar to cut-off state).
-	  If this battery is found to be in disconnect state, take it out of
-	  this state by force-applying a charge current. Once defined,
-	  a battery_get_disconnect_state() function has to be provided.
-
-config PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
-	bool "Measure the battery cells imbalance"
-	help
-	  Smart battery driver should measure the voltage cell imbalance in the
-	  battery pack.
-	  This requires a battery driver capable of the measurement.
-	  If enabled, the AP enabling may be prevented if battery is too
-	  imbalanced.
-
-config PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV
-	int "Max battery imbalance in millivolts"
-	depends on PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
-	default 200
-	help
-	  Imbalanced battery packs in this situation appear to have balanced
-	  charge very quickly after beginning the charging cycle, since dV/dQ
-	  rapidly decreases as the cell is charged out of deep discharge.
-	  Increasing the value of
-	  CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON will make a
-	  system tolerant of larger values of
-	  CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV.
-
-config PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
-	int "Minimum battery percentage for power on with an imbalanced pack"
-	depends on PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
-	default 5
-	range 0 100
-	help
-	  If battery pack is in imbalanced state and current state of charge is
-	  below this value, the AP won't be powered on.
-
-config PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
-	int "Voltage limit in mV when battery is full and AP is off"
-	depends on PLATFORM_EC_USB_PE_SM && PLATFORM_EC_CHARGE_MANAGER
-	default -1
-	help
-	  If set to a non-negative value, input voltage will be reduced to given
-	  value when chipset is in S5/G3 state and battery is fully charged.
-	  This condition is checked on chipset shutdown and startup, AC change
-	  and battery SOC change.
-
-endif # PLATFORM_EC_BATTERY
diff --git a/zephyr/Kconfig.board_version b/zephyr/Kconfig.board_version
deleted file mode 100644
index e24957764d..0000000000
--- a/zephyr/Kconfig.board_version
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-choice PLATFORM_EC_BOARD_VERSION_SOURCE
-	prompt "Select the source of the board version number"
-	optional
-	help
-	  This allow selection of the source of the board version number
-	  information. Several options are available, but BOARD_VERSION_CBI is
-	  preferred for new boards, so long as the hardware supports it (i.e.
-	  has an EEPROM).
-
-config PLATFORM_EC_BOARD_VERSION_CBI
-	bool "Chromium OS Board Info (CBI)"
-	depends on PLATFORM_EC_CBI_EEPROM
-	help
-	  Choose this if the board version comes from Chromium Board Info
-	  within the EEPROM. This is the recommended approach and is used on
-	  newer boards. The version information is written into the EEPROM as
-	  part of the factory process.
-
-config PLATFORM_EC_BOARD_VERSION_GPIO
-	bool "Strapping GPIOs"
-	help
-	  Choose this if the board version is encoded with three GPIO signals
-	  (GPIO_BOARD_VERSION1, GPIO_BOARD_VERSION2 and GPIO_BOARD_VERSION3)
-	  forming the 3-digit binary number. GPIO_BOARD_VERSION1 is the LSB.
-	  This provides 8 possible combinations.
-
-	  The GPIOs should have external pull-up/pull-down resistors installed
-	  at the factory to select the correct value.
-
-endchoice
diff --git a/zephyr/Kconfig.console b/zephyr/Kconfig.console
deleted file mode 100644
index 04e1d137bd..0000000000
--- a/zephyr/Kconfig.console
+++ /dev/null
@@ -1,69 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config PLATFORM_EC_CONSOLE_CHANNEL
-	bool "Console channels"
-	depends on CONSOLE
-	default y
-	help
-	  Make it possible for console to be output to different channels that
-	  can be turned on and off. Channels are organized by functional area
-	  such as "charger", "motionsense", "usbpd" and others.
-
-	  This is useful as a developer convenience when the console is crowded
-	  with messages, to make it easier to use the interactive console.
-
-	  The `chan` console command with no arguments shows all available
-	  channels.
-
-	  FAFT and servod also use this feature.
-
-	  Boards may #undef this to reduce image size.
-
-# Adjusted to the longest print message from the timer_info command
-config SHELL_PRINTF_BUFF_SIZE
-	default 130
-
-# Some boards may need to increase the size, depending on the amount of output
-#
-# TODO(b/196627937): zephyr: hang when running help with CONFIG_SHELL_HELP
-# enabled.  Increase the TX buffer size to workaround the hang when the help
-# is enabled.
-config SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE
-	default 4096 if SHELL_HELP
-	default 1024
-
-menuconfig PLATFORM_EC_HOSTCMD_CONSOLE
-	bool "Console Host Command"
-	depends on PLATFORM_EC_HOSTCMD
-	default y
-	help
-	  Enable the EC_CMD_CONSOLE_SNAPSHOT and EC_CMD_CONSOLE_READ
-	  host commands, used for reading the EC console from the AP.
-
-if PLATFORM_EC_HOSTCMD_CONSOLE
-
-config PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE
-	int "Console buffer size"
-	default 4096
-	help
-	  The EC will use a circular buffer to store bytes outputted
-	  to the console for the AP to read.  This changes the maximal
-	  number of bytes from the console output which can be saved.
-
-	  Choosing a power-of-two for this value is optimal, as
-	  modular arithmetic is used.
-
-endif # PLATFORM_EC_HOSTCMD_CONSOLE
-
-config PLATFORM_EC_CONSOLE_USES_PRINTK
-	bool "Console uses printk"
-	depends on CONSOLE
-	help
-	  Implement zephyr_print using printk for all cases instead
-	  of using shell_fprintf for non-ISR uses in
-	  shim/common/console.c.
-	  Some devices have not been able to output to the console
-	  fast enough using shell_fprintf and end up timing out
-	  unrelated functionality.
diff --git a/zephyr/Kconfig.console_cmd_mem b/zephyr/Kconfig.console_cmd_mem
deleted file mode 100644
index 4b69cc1778..0000000000
--- a/zephyr/Kconfig.console_cmd_mem
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_CONSOLE_CMD_MEM
-config PLATFORM_EC_CONSOLE_CMD_MD
-	bool "Console command: md"
-	default y
-	help
-	  Enable the "md" command. This dumps memory value from a specified
-	  address, optionally specifying the format.
-
-	  Example:
-	     md 0x64000000 10
-
-	     64000000: 2a3b4d5e 030054e1 07000000 09297110
-	     64000010: 00000010 03db4f00 03db5000 00000100
-	     64000020: 00000000 00000000
-
-config PLATFORM_EC_CONSOLE_CMD_RW
-	bool "Console command: rw"
-	default y
-	help
-	  Enable the "rw" command. This Read or write in memory optionally
-	  specifying the size.
-
-	  Example:
-	     rw 0x64000000
-
-	     read 0x64000000 = 0x2a3b4d5e
-
-endif # PLATFORM_EC_CONSOLE_CMD_MEM
diff --git a/zephyr/Kconfig.debug_assert b/zephyr/Kconfig.debug_assert
deleted file mode 100644
index d568bc7e34..0000000000
--- a/zephyr/Kconfig.debug_assert
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_DEBUG_ASSERT
-choice "Behaviour on assertion failure"
-	prompt "Select behaviour on assertion failure"
-	help
-	  This selects the action taken when the board hits an assertion
-	  failure in the code. This should not happen in normal operation,
-	  but can appear during development when the code is not yet fully
-	  tested.
-
-config PLATFORM_EC_DEBUG_ASSERT_REBOOTS
-	bool "Reboot"
-	help
-	  Prints a message and reboot if an assert() macro fails at runtime.
-	  If PLATFORM_EC_SOFTWARE_PANIC is enabled then the information is
-	  written to the panic log before rebooting.
-
-config PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT
-	bool "Generate a breakpoint"
-	help
-	  Immediately hits a breakpoint instruction (without printing a message)
-	  so that a connected JTAG debugger can be used to debug the problem
-	  from there. If there is no debugger connected then the breakpoint
-	  instruction will cause the board to reboot immediately.
-
-endchoice # "Behaviour on assertion failure"
-
-config PLATFORM_EC_DEBUG_ASSERT_BRIEF
-	bool "Use brief assertion-failure messages"
-	depends on PLATFORM_EC_DEBUG_ASSERT_REBOOTS
-	help
-	  Normally the assertion-failure messages include the expression that
-	  failed and the function name where the failure occurred. These are
-	  both stored as strings and can add a lot to the size of the image,
-	  since they are generated for every call to assert(). Use this option
-	  to drop them so that only the file and line number are shown.
-
-	  This option is of course not available with
-	  PLATFORM_EC_DEBUG_ASSERT_BREAKPOINT, since that does not print a
-	  message at all.
-
-endif # PLATFORM_EC_DEBUG_ASSERT
diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults
deleted file mode 100644
index 2b55e72156..0000000000
--- a/zephyr/Kconfig.defaults
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kconfig overrides that applies to all platforms.
-
-# Disable timeslicing, it's compiled in by default and can be enabled at
-# runtime but not used in Zephyr EC.
-config TIMESLICING
-	default n
diff --git a/zephyr/Kconfig.espi b/zephyr/Kconfig.espi
deleted file mode 100644
index 81b9f11e57..0000000000
--- a/zephyr/Kconfig.espi
+++ /dev/null
@@ -1,28 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_ESPI
-
-config PLATFORM_EC_ESPI_VW_SLP_S3
-	bool "SLP_S3 is an eSPI virtual wire instead of a GPIO"
-	help
-	  For power sequencing, use an eSPI virtual wire instead of
-	  defining GPIO_PCH_SLP_S3 in gpio_map.h.
-
-config PLATFORM_EC_ESPI_VW_SLP_S4
-	bool "SLP_S4 is an eSPI virtual wire instead of a GPIO"
-	help
-	  For power sequencing, use an eSPI virtual wire instead of
-	  defining GPIO_PCH_SLP_S4 in gpio_map.h.
-
-config PLATFORM_EC_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-	bool "Reset SLP VW signals on eSPI reset"
-	help
-	  Enable this config to reset SLP* VW when eSPI_RST is asserted
-	  for the Global Reset event case.  Don't enable this config if
-	  the platform implements the Deep-Sx entry as EC needs to
-	  maintain these pins' states per request. Note that this is
-	  currently unimplemented for Zephyr. Please see b/183148073.
-
-endif # PLATFORM_EC_ESPI
\ No newline at end of file
diff --git a/zephyr/Kconfig.flash b/zephyr/Kconfig.flash
deleted file mode 100644
index f6a8b2d103..0000000000
--- a/zephyr/Kconfig.flash
+++ /dev/null
@@ -1,107 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_FLASH_CROS
-
-config PLATFORM_EC_SPI_FLASH_REGS
-	bool "Enable SPI flash registers"
-	default y if SOC_FAMILY_NPCX
-	help
-	  Enables flash registers for SPI flash (both internal and external).
-	  When enabled, two new functions will become available: (1) a function
-	  to compute the block write protection range from a set of status
-	  registers, and (2) the inverse function to set the status registers
-	  based on the desired protection offset/length.
-
-config PLATFORM_EC_CONSOLE_CMD_CHARGEN
-	bool "Console command: chargen"
-	depends on UART_INTERRUPT_DRIVEN
-	help
-	  Enables the "chargen" console command, which sends a continuous
-	  stream of characters to the EC console.
-
-	  This allows to create tests which validate console output by
-	  verifying that no characters in the received sequence were lost.
-
-config PLATFORM_EC_CONSOLE_CMD_FLASH
-	bool "Console commands: flasherase, flashread, flashwrite"
-	help
-	  Enables various console commands:
-
-	     flasherase - erase flash region
-	     flashread - read from flash to memory
-	     flashwrite - write memory to flash
-
-config PLATFORM_EC_CONSOLE_CMD_FLASHINFO
-	bool "Console commands: flashinfo"
-	default y
-	help
-	  Enables various console commands:
-
-	     flashinfo - displays information about the flash storage
-
-config PLATFORM_EC_CONSOLE_CMD_FLASH_WP
-	bool "Console commands: flashwp"
-	default y
-	help
-	  Enables various console commands:
-
-	     flashwp - change write-protection settings
-
-config PLATFORM_EC_CONSOLE_CMD_SYSJUMP
-	bool "Console command: sysjump"
-	default y
-	help
-	  Enables the sysjump console command used for testing and verifying
-	  that we're able to jump between images. Normally, in an EC build,
-	  there will exist 2 images (sometimes more): read-only (RO) and
-	  read-write (RW). This console command allows us to manually jump
-	  between the various images (or even to a random starting address) by
-	  copying the image data from flash to ram, then jumping to the image's
-	  entry point.
-
-choice PLATFORM_EC_STORAGE_TYPE
-       prompt "Code storage type"
-       default PLATFORM_EC_EXTERNAL_STORAGE if SOC_FAMILY_NPCX
-       default PLATFORM_EC_INTERNAL_STORAGE if SOC_FAMILY_RISCV_ITE
-       help
-         Sets the EC code storage type.
-
-config PLATFORM_EC_EXTERNAL_STORAGE
-	bool "Flash is stored external to the EC"
-	help
-	  This indicates that the EC's flash is stored separately and is it
-	  not possible execute directly from it. Code must be loaded from
-	  the flash into internal SRAM before it can be executed. It is still
-	  possible to read and write the flash.
-
-config PLATFORM_EC_INTERNAL_STORAGE
-	bool "Flash is stored internal to the EC"
-	help
-	  This indicates that the EC code can reside on internal storage.
-	  This option implies XIP(eXecute-In-Place) semantics.
-	  i.e. code is being fetched directly from storage media.
-
-endchoice
-
-config PLATFORM_EC_MAPPED_STORAGE
-	bool "Flash is mapped into the EC's address space"
-	default y if SOC_FAMILY_NPCX || SOC_FAMILY_RISCV_ITE
-	help
-	  This indicates that the EC's flash is directly mapped into
-	  its address space. This makes it easier to read and write the flash.
-	  If this is not defined, the flash driver must implement
-	  flash_physical_read().
-
-config PLATFORM_EC_FLASH_PSTATE
-	bool "Store persistent write protect for the flash inside"
-	default y if SOC_FAMILY_RISCV_ITE
-	help
-	  Store persistent write protect for the flash inside the flash data
-	  itself.  This allows ECs with internal flash to emulate something
-	  closer to a SPI flash write protect register.  If this is not
-	  defined, write protect state is maintained solely by the physical
-	  flash driver.
-
-endif # PLATFORM_EC_FLASH_CROS
diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
deleted file mode 100644
index 43e66ec3e4..0000000000
--- a/zephyr/Kconfig.header
+++ /dev/null
@@ -1,30 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config PLATFORM_EC_RO_HEADER
-	bool "RO section includes a header"
-	default y
-	depends on CROS_EC_RO
-	depends on SOC_FAMILY_NPCX
-	help
-	  The RO image residing on flash memory has a header section. The header
-	  is used on some chips (such as the npcx) to load the image correctly
-	  from flash. The values for offset and size are used by the linker
-	  scripts to generate the header. See core/cortex-m/ec.lds.S for
-	  reference.
-
-config PLATFORM_EC_RO_HEADER_OFFSET
-	hex "Offset in memory for the location of the header"
-	default 0x0
-	help
-	  The offset (in bytes) of the header relative to the start address of
-	  the RO image.
-
-config PLATFORM_EC_RO_HEADER_SIZE
-	hex "Size of the RO header"
-	default 0x40 if SOC_FAMILY_NPCX
-	default 0x0
-	help
-	  The size of the RO header in bytes. This values should come from the
-	  datasheet of the chip being used.
diff --git a/zephyr/Kconfig.init_priority b/zephyr/Kconfig.init_priority
deleted file mode 100644
index af858a5296..0000000000
--- a/zephyr/Kconfig.init_priority
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config PLATFORM_EC_FLASH_INIT_PRIORITY
-  int "Init priority of the flash module"
-  default 52
-  help
-    The initialization priority of the flash module. This should always be
-    greater than PLATFORM_EC_GPIO_INIT_PRIORITY.
-
-config PLATFORM_EC_GPIO_INIT_PRIORITY
-  int "Init priority of the GPIO module"
-  default 51
-  help
-    The initialization priority of the GPIO module. This should always happen
-    after the gpio drivers are initialized.
-
-config PLATFORM_EC_PWM_INIT_PRIORITY
-	int "Initialization priority of the PWM module"
-	depends on PLATFORM_EC_PWM
-	default 51
-	help
-	  Sets the initialization priority of the PWM module. This MUST be a
-	  value greater than the PWM driver's initialization priority which
-	  currently defaults to KERNEL_INIT_PRIORITY_DEVICE.
diff --git a/zephyr/Kconfig.keyboard b/zephyr/Kconfig.keyboard
deleted file mode 100644
index 9ad7fb8316..0000000000
--- a/zephyr/Kconfig.keyboard
+++ /dev/null
@@ -1,177 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_KEYBOARD
-	bool "Keyboard support"
-	select HAS_TASK_KEYSCAN
-	default n if ARCH_POSIX
-	default y
-	help
-	  Enable compilation of support for scanning a keyboard and providing
-	  the resulting input to the AP over the host interface. This consists
-	  of a keyboard-scanning task which provides key scans via it calling
-	  keyboard_state_changed() (for i8042) or its client calling
-	  keyboard_scan_get_state() (for MKBP).
-
-	  Enabling this automatically enables HAS_TASK_KEYSCAN since keyboard
-	  scanning must run in its own task.
-
-if PLATFORM_EC_KEYBOARD
-
-choice "Protocol select"
-	prompt "Select the keyboard protocol to use"
-	help
-	  Select the keyboard protocol used to communicate key presses to the
-	  AP. PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is supported by x86-compatible
-	  application processors, and PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP is
-	  used for ARM application processors.
-
-config PLATFORM_EC_KEYBOARD_PROTOCOL_8042
-	bool "i8042"
-	select HAS_TASK_KEYPROTO
-	help
-	  Use the i8042 protocol to communicate with the AP. This dates from the
-	  Intel 8042 keyboard controller chip released in 1976. It uses two-way
-	  communication via a few 8-bit registers, allowing key codes to be
-	  sent to the AP when keys are pressed and released.
-
-	  See here for docs: https://wiki.osdev.org/%228042%22_PS/2_Controller
-
-config PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
-	bool "mkbp"
-	help
-	  Use the MKBP protocol to communicate with the AP. This protocol is
-	  usually used on ARM-based platforms. It sends the raw scan code, like
-	  (row, col), to the AP and the kernel driver will map this scan code to
-	  a key.
-
-endchoice # PLATFORM_EC_KEYBOARD
-
-config PLATFORM_EC_KEYBOARD_KEYPAD
-	bool "Support a numeric keypad"
-	help
-	  Enable support for a keypad, a palm-sized keyboard section usually
-	  placed on the far right. This contains nuumber keys and also some
-	  commonly used symbols, to help speed up numeric data entry.
-
-config PLATFORM_EC_KEYBOARD_VIVALDI
-	bool "Vivaldi keyboard support"
-	depends on PLATFORM_EC_KEYBOARD_PROTOCOL_8042
-	default y
-	help
-	  Enable code for Vivaldi keyboard (standard for new Chromium OS
-	  devices). A Chromium OS device is Vivaldi compatible if the keyboard
-	  matrix complies with: go/vivaldi-matrix.
-
-	  Vivaldi code enables:
-	  - A response to EC_CMD_GET_KEYBD_CONFIG command.
-	  - Boards can specify their custom layout for top keys.
-
-choice "Power button interference"
-	prompt "Select the impact of pressing the power button"
-	help
-	  On some boards one of the keyboard-scan inputs is affected by pressing
-	  the power button. When the power button is pressed, that input needs
-	  to be ignored in that case.
-
-config PLATFORM_EC_KEYBOARD_PWRBTN_INDEPENDENT
-	bool "No impact on keyboard-scan inputs"
-	help
-	  Select this if pressing the power button does not affect any
-	  keyboard-scan inputs.
-
-config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2
-	bool "Forces KSI2 to be asserted"
-	help
-	  Enable this if KSI2 is stuck 'asserted' for all scan columns if the
-	  power button is held. We must be aware of this case in order to
-	  correctly handle recovery-mode key combinations.
-
-config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3
-	bool "Forces KSI3 to be asserted"
-	help
-	  Enable this if KSI3 is stuck 'asserted' for all scan columns if the
-	  power button is held. We must be aware of this case in order to
-	  correctly handle recovery-mode key combinations.
-
-endchoice # "Power button interference"
-
-config PLATFORM_EC_KEYBOARD_COL2_INVERTED
-	bool "A mechanism for passing KSO2 to H1 which inverts the signal"
-	help
-	  This option enables a mechanism for passing the column 2
-	  to H1 which inverts the signal. The signal passing through H1
-	  adds more delay. Need a larger delay value. Otherwise, pressing
-	  Refresh key will also trigger T key, which is in the next scanning
-	  column line. See http://b/156007029.
-
-config PLATFORM_EC_KEYBOARD_REFRESH_ROW3
-	bool "Move the refresh key matrix to row 3 instead of row 2"
-	help
-	  The Vivaldi keyboards have the refresh key on row 3 instead of row 2.
-	  The legacy keyboards with the assistant key also move the refresh key
-	  matrix to row 3. This is used by the boot key detection code to
-	  determine if the refresh key is held down at boot.
-
-config PLATFORM_EC_VOLUME_BUTTONS
-	bool "Board has volume-up and volume-down buttons"
-	help
-	  Enable this if the board has physical buttons for the volume controls.
-	  These are buttons controlled by GPIOs and are not part of the keyboard
-	  matrix.
-
-	  Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L in
-	  gpio_map.h
-
-config PLATFORM_EC_CMD_BUTTON
-	bool "Console command: button"
-	help
-	  This command simulates button press. The buttons are like volume-up,
-	  volume-down, and recovery buttons.
-
-config PLATFORM_EC_CONSOLE_CMD_KEYBOARD
-	bool "Console command: ksstate, kbpress, 8042"
-	default y if PLATFORM_EC_KEYBOARD
-	help
-	  Enable keyboard related console commands.
-
-	    ksstate     - Show or toggle printing keyboard scan state
-	    kbpress     - Simulate keypress
-
-	  If PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is enabled, it includes 8042
-	  command which prints the state of the i8042 keyboard protocol and
-	  includes the following subcommands:
-
-	    codeset	- Get/set keyboard codeset
-	    ctrlram	- Get/set keyboard controller RAM
-	    internal    - Show internal information
-	    kbd		- Print or toggle keyboard info
-	    kblog	- Print or toggle keyboard event log (current disabled)
-	    typematic	- Get/set typematic delays
-
-choice
-	prompt "Keyboard backlight"
-	optional
-	help
-	  Enable support for EC control of a keyboard backlight. This enables
-	  the "kblight" console command for manual control of the keyboard
-	  backlight. This also enables the EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT and
-	  EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT host commands for automatic control
-	  by the AP.
-
-	  TODO: support CONFIG_IO_EXPANDER_IT8801 driver which provides
-	  PWM keyboard support.
-
-config PLATFORM_EC_PWM_KBLIGHT
-	bool "PWM keyboard backlight"
-	depends on PLATFORM_EC_PWM
-	help
-	  Enables a PWM-controlled keyboard backlight controlled by a PWM signal
-	  connected directly to the EC chipset. The board files must define
-	  the C reference PWM_CH_KBLIGHT to the PWM channel used for the
-	  keyboard backlight control.
-
-endchoice  # Keyboard backlight
-
-endif # PLATFORM_EC_KEYBOARD
diff --git a/zephyr/Kconfig.led b/zephyr/Kconfig.led
deleted file mode 100644
index 8955675d92..0000000000
--- a/zephyr/Kconfig.led
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_LED_COMMON
-	bool "LED Support"
-	help
-	  Enable the common LED module supporting automatic control of the
-	  battery and power LEDs.
-
-if PLATFORM_EC_LED_COMMON
-
-# TODO: Add other choices
-#  CONFIG_LED_POLICY_STD
-#  CONFIG_LED_PWM_CHARGE_STATE_ONLY
-#  CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY
-#  CONFIG_LED_ONOFF_STATES
-
-config PLATFORM_EC_LED_PWM
-	bool "PWM (Pulse Width Modulation) LEDs"
-	depends on PLATFORM_EC_PWM
-	help
-	  Enable PWM (Pulse Width Modulation) controlled LEDs that conform to
-	  the Chromium OS LED behavior specification.
-
-	  Your board files must implement led_set_brightness() function, which
-	  is used by the LED PWM module to set the board LEDs in response to
-	  power and charging events.
-
-if PLATFORM_EC_LED_PWM
-
-config PLATFORM_EC_CONSOLE_CMD_LEDTEST
-	bool "Console command: ledtest"
-	default y
-	help
-	  Enable the "ledtest" command. This command lets you override the
-	  automatic control of the platform LEDs. For example:
-
-	    ledtest 0 enable red
-
-	  disables automatic control of the first PWM LED and forces the LED
-	  color to red.  Set the 2nd parameter to "disable" to return back
-	  to automatic control:
-
-	    ledtest 0 disable
-
-endif # PLATFORM_EC_LED_PWM
-endif # PLATFORM_EC_LED_COMMON
diff --git a/zephyr/Kconfig.mkbp_event b/zephyr/Kconfig.mkbp_event
deleted file mode 100644
index e24cf370d2..0000000000
--- a/zephyr/Kconfig.mkbp_event
+++ /dev/null
@@ -1,49 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_MKBP_EVENT
-
-choice
-    prompt "MKBP delivery method"
-    default PLATFORM_EC_MKBP_USE_GPIO
-    help
-      Select MKBP delivery method
-
-config PLATFORM_EC_MKBP_USE_GPIO
-    bool "Use GPIO"
-    help
-      Select to send MKBP events via GPIO. You should define GPIO_EC_INT_L
-      in gpio_map.h as output from the EC. The GPIO is used to indicate an
-      event is ready for serving by the AP.
-
-config PLATFORM_EC_MKBP_USE_HOST_EVENT
-    bool "Use host event"
-    help
-      Select to send MKBP events via host event.
-
-config PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT
-    bool "Use GPIO and host event"
-    help
-      MKBP events are notified by using both a GPIO and a host event.
-
-      You should use this if you are using a GPIO to notify the AP of an MKBP
-      event, and you need an MKBP event to wake the AP in suspend and the
-      AP cannot wake from the GPIO.  Since you are using both a GPIO and
-      a hostevent for the notification, make sure that the S0 hostevent mask
-      does NOT include MKBP events.  Otherwise, you will have multiple
-      consumers for a single event. However, make sure to configure the
-      host event *sleep* mask in coreboot to include MKBP events. In order to
-      prevent all MKBP events from waking the AP, use
-      CONFIG_MKBP_EVENT_WAKEUP_MASK to filter the events.
-
-config PLATFORM_EC_MKBP_USE_CUSTOM
-    bool "Use custom method"
-    help
-      Select to send MKBP events using custom method. You need to define
-      mkbp_set_host_active_via_custom() which is called when there's a MKBP event
-      to be sent. for more about the function, refer to mkbp_event.h.
-
-endchoice
-
-endif # PLATFORM_EC_MKBP_EVENT
diff --git a/zephyr/Kconfig.motionsense b/zephyr/Kconfig.motionsense
deleted file mode 100644
index daf2bbcdf8..0000000000
--- a/zephyr/Kconfig.motionsense
+++ /dev/null
@@ -1,190 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_MOTIONSENSE
-    bool "Motion Sense"
-    select HAS_TASK_MOTIONSENSE
-    help
-      Enable motion sense task. The task collects data from available sensors
-      and report them to AP. Besides the task reports the sensor data to AP.
-      Based on the data, it also does other things like calculating lid angle
-      and detect tablet mode.
-
-config PLATFORM_EC_ACCEL_FIFO
-    bool "Sensor FIFO"
-    help
-      Enable this to add the sensor FIFO used by sensor device drivers to fill.
-      Using FIFO reduces power consumption since it reduces the number of
-      AP wake-ups.
-
-if PLATFORM_EC_ACCEL_FIFO
-
-config PLATFORM_EC_ACCEL_FIFO_SIZE
-    int "Motion Sense FIFO Size"
-    default 256
-    help
-      This sets the size of the sensor FIFO, must be a power of 2.
-
-config PLATFORM_EC_ACCEL_FIFO_THRES
-    int "FIFO Threshold"
-    default 85      # (PLATFORM_EC_ACCEL_FIFO_SIZE / 3)
-    help
-      This sets the amount of free entries that trigger an interrupt to the AP.
-
-endif # PLATFORM_EC_ACCEL_FIFO
-
-config PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS
-    bool "Extra Sensor Timestamp"
-    help
-      If this is defined, motion_sense sends
-      sensor events to the AP in the format
-      +-----------+
-      | Timestamp |
-      |  Payload  |
-      | Timestamp |
-      |  Payload  |
-      |    ...    |
-      +-----------+
-      If this is not defined, the events will be sent in the format
-      +-----------+
-      |  Payload  |
-      |  Payload  |
-      |  Payload  |
-      |    ...    |
-      | Timestamp |
-      +-----------+
-      The former format enables improved filtering of sensor event
-      timestamps on the AP, but comes with stricter jitter requirements.
-
-config PLATFORM_EC_ACCEL_INTERRUPTS
-    bool "Accelerometer Interrupts"
-    help
-      Enable this to allow a sensor driver to send an event to motion task when
-      the sensor gets the data ready interrupt. On the event, motion task calls
-      the driver's irq_handler to collect data.
-
-# TODO(b/173507858) config PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
-# if PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
-#endif # PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA
-
-config PLATFORM_EC_ALS
-    bool "Ambient Light Sensor(ALS)"
-    default y if HAS_TASK_ALS
-    help
-      Enable this to indicate there's at least one or more ALS devices available.
-      If PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA is set, then motion task updates
-      the designated part of EC memmap with the ALS data. The updating EC memmap
-      can be also done by the dedicated ALS task with HAS_ALS_TASK set.
-      Number of ALS entries reserved in EC memmap are defined by EC_ALS_ENTRIES
-      in ec_commands.h.
-
-if PLATFORM_EC_ALS
-
-config PLATFORM_EC_ALS_COUNT
-    int "Number of ALS devices"
-    default 1
-    help
-      This sets the number of ALS devices. This should be less than or equal to
-      EC_ALS_ENTRIES in ec_commands.h
-      TODO(b/173507858) move this to device tree
-
-endif # PLATFORM_EC_ALS
-
-config PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT
-    bool "Dynamic Motion Sensor Count"
-    help
-      Enable this to allow changing motion sensor count dynamically.
-
-config PLATFORM_EC_LID_ANGLE
-    bool "Lid Angle"
-    help
-      Enable this to detect lid angle with two accelerometers. The andgle
-      calculation requires the information about which sensor is on the lid
-      and which one is on the base. The measured lid angle can be used for
-      tablet mode detection(refer "Tablet Mode below") and enabling/disabling
-      peripheral devices(refer "Lid Angle Update" below).
-      # TODO(b/173507858): add more detail after .dts change
-
-if PLATFORM_EC_LID_ANGLE
-
-config PLATFORM_EC_LID_ANGLE_UPDATE
-    bool "Lid Angle Update"
-    help
-      Enable this to allow using the lid angle measurement to determine if
-      peripheral devices should be enabled or disabled, like key scanning,
-      trackpad interrupt.
-
-config PLATFORM_EC_TABLET_MODE
-    bool "Tablet Mode"
-    help
-      Enable this for a device which can be a tablet as well as a clamshell.
-      Tablet mode detection is done either by using the lid angle measurement
-      or by the dedicated GMR sensor.
-
-if PLATFORM_EC_TABLET_MODE
-
-config PLATFORM_EC_TABLET_MODE_SWITCH
-    bool "Tablet Mode Switch"
-    depends on PLATFORM_EC_MKBP_INPUT_DEVICES
-    help
-      Enable a virtual switch to indicate when we are in tablet mode. The tablet
-      mode state is sent to AP via MKBP protocol(switch event).
-
-config PLATFORM_EC_GMR_TABLET_MODE
-    bool "Giant Magnetoresistance(GMR) Tablet Mode"
-    help
-      Enable this to use GMR sensor to detect tablet mode.
-      It requires to set GMR_TABLET_MODE_GPIO_L to map the interrupt from
-      the sensor and direct its mapping to gmr_tablet_switch_isr
-      in common/tablet_mode.c.
-
-endif # PLATFORM_EC_TABLET_MODE
-endif # PLATFORM_EC_LID_ANGLE
-
-config PLATFORM_EC_CONSOLE_CMD_ACCELS
-    bool "Console commands: accels, accelrate, accelinit, accelinfo, etc."
-    help
-      Enables console commands:
-
-        accelrange <sensor id> <data> <roundup> - Read or write accelerometer
-        range
-        accelres <sensor id> <data> <roundup> - Read or write accelerometer
-        resolution
-        accelrate <sensor id> <data> <roundup> - Read or write accelerometer
-        ODR
-        accelread <sensor id> [n(iteration)] - Read sensor x/y/z
-        accelinit <sensor id> - Init sensor
-
-if PLATFORM_EC_CONSOLE_CMD_ACCELS
-
-config PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO
-    bool "Console Command: accelinfo"
-    help
-      Enable console command:
-
-        accelinfo on/off [interval] - Print motion sensor info, lid angle
-        calculations and set calculation frequency.
-
-endif # PLATFORM_EC_CONSOLE_CMD_ACCELS
-
-config PLATFORM_EC_ACCEL_SPOOF_MODE
-	bool "Sensor spoof mode"
-	help
-	  Enable this to allow sensors values spoofed to any arbitrary value.
-	  This is useful for testing the motion sense framework if the hardware
-	  sensor or the sensor driver code is not ready.
-
-if PLATFORM_EC_ACCEL_SPOOF_MODE
-
-config PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF
-	bool "Console Command: accelspoof"
-	help
-	  Enable console command:
-
-	    accelspoof id [on/off] [X] [Y] [Z] - Enable/Disable spoofing of
-	    sensor readings.
-
-endif # PLATFORM_EC_ACCEL_SPOOF_MODE
-
-rsource "Kconfig.sensor_devices"
diff --git a/zephyr/Kconfig.panic b/zephyr/Kconfig.panic
deleted file mode 100644
index 322aaee25d..0000000000
--- a/zephyr/Kconfig.panic
+++ /dev/null
@@ -1,43 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_PANIC
-
-config PLATFORM_EC_SOFTWARE_PANIC
-	bool "Software panic"
-	default y
-	help
-	  Sometimes the EC has bugs that are provoked by unexpected events.
-	  This enables storing a panic log and halt the system for
-	  software-related reasons, such as stack overflow or assertion
-	  failure.
-
-config PLATFORM_EC_CONSOLE_CMD_CRASH
-	bool "Console command: crash"
-	default y
-	help
-	  For testing purposes it is useful to be able to generation exceptions
-	  to check that the panic reporting is working correctly. The enables
-	  the 'crash' command which supports generating various exceptions,
-	  selected by its parameter:
-
-	     assert              - assertion failure (ASSERT() macro)
-	     divzero             - division by zero
-	     udivzero            - division of unsigned value by zero
-	     stack (if enabled)  - stack overflow
-	     unaligned           - unaligned access (e.g. word load from 0x123)
-	     watchdog            - watchdog timer fired
-	     hang                - infinite loop in the EC code
-
-config PLATFORM_EC_STACKOVERFLOW
-	bool "Console command: crash stack"
-	depends on PLATFORM_EC_CONSOLE_CMD_CRASH
-	default y if !ZTEST && !SOC_POSIX
-	help
-	  This enables the 'stack' parameter for the 'crash' command. This
-	  causes a stack overflow by recursing repeatedly while task switching.
-	  This can be used to check that stack-overflow detection is working
-	  as expected.
-
-endif # PLATFORM_EC_PANIC
diff --git a/zephyr/Kconfig.pmic b/zephyr/Kconfig.pmic
deleted file mode 100644
index dc79305439..0000000000
--- a/zephyr/Kconfig.pmic
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_PMIC
-	bool "Power Management IC support"
-	help
-	  Enables support for controlling PMICs (Power Management ICs).
-	  A system may have one or more PMICs to control various power
-	  rails. These devices operate autonomously, but can sometimes
-	  be accessed to tune operational parameters or read fault
-	  codes.
-
-if PLATFORM_EC_PMIC
-
-config PLATFORM_EC_MP2964
-	bool "Enable MP2964 PMIC support"
-	depends on AP_X86_INTEL
-	depends on PLATFORM_EC_I2C
-	help
-	  Enables support for the MPS MP2964 PMIC (Power Management IC).
-	  This is a dual rail IMVP8 - IMVP9.1 compatible Digital
-	  Multi-Phase Controller with an I2C interface.  This driver
-	  enables reprogramming configuration registers when initial the
-	  factory settings need to be tuned in prototype devices.
-
-endif # PLATFORM_EC_PMIC
diff --git a/zephyr/Kconfig.port80 b/zephyr/Kconfig.port80
deleted file mode 100644
index b3ff8ab60b..0000000000
--- a/zephyr/Kconfig.port80
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_ESPI
-
-config PLATFORM_EC_PORT80_4_BYTE
-	bool "Allow accept 4-byte Port80 codes"
-	help
-	  Enable this config to allow the common Port80 layer to accept 4-byte
-	  codes when AP sends 4-byte Port80 codes via eSPI PUT_IOWR_SHORT
-	  protocol in a single transaction.
-
-endif # PLATFORM_EC_ESPI
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq
deleted file mode 100644
index 0045a69ad8..0000000000
--- a/zephyr/Kconfig.powerseq
+++ /dev/null
@@ -1,190 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_POWERSEQ
-	bool "Power sequencing"
-	depends on AP
-	select HAS_TASK_CHIPSET
-	help
-	  Enable shimming the platform/ec AP power sequencing code. This
-	  handles powering the chipset on and off.
-
-	  Enabling this automatically enables HAS_TASK_CHIPSET since power
-	  sequencing must run in its own task.
-
-if PLATFORM_EC_POWERSEQ
-
-config PLATFORM_EC_POWERSEQ_HOST_SLEEP
-	bool "Track host sleep states"
-	help
-	  Enable EC code to track the AP sleep states.  This is
-	  required for S0ix support on Intel platforms, and optional
-	  for boards without S0ix support.
-
-config PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION
-	bool "Detect failure to enter a sleep state (S0ix/S3)"
-	depends on PLATFORM_EC_POWERSEQ_HOST_SLEEP
-	help
-	  Enables detection of the AP failing to go to sleep, perhaps due to a
-	  bug in the internal SoC periodic housekeeping code.
-
-	  Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host
-	  command.
-
-config PLATFORM_EC_HOSTCMD_AP_RESET
-	bool "Host command: EC_CMD_AP_RESET"
-	depends on PLATFORM_EC_HOSTCMD
-	help
-	  Enable support for EC_CMD_AP_RESET, used by the AP to request that
-	  the EC perform a reset of the AP.
-
-	  Warning: This command skips the normal reset mechanism on the AP and
-	  may leave data unsaved.
-
-config PLATFORM_EC_POWERSEQ_PP5000_CONTROL
-	bool "Enable a task-safe way to control the PP5000 rail"
-	depends on !AP_X86_AMD
-	default y
-	help
-	  Guard access to the PP5000 GPIO using mutex locks, allowing
-	  the rail to be changed in a task-safe manner.
-
-menuconfig PLATFORM_EC_POWERSEQ_AMD
-	bool "AMD power sequencing"
-	depends on AP_X86_AMD
-	select HAS_TASK_POWERBTN
-	default y
-	help
-	  Enable AMD power sequencing code.
-
-if PLATFORM_EC_POWERSEQ_AMD
-
-config PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM
-	bool "Custom board_pwrbtn_to_pch"
-	help
-	  The board support code provides a custom function,
-	  board_pwrbtn_to_pch, that replaces the standard GPIO set
-	  level to the SoC.
-
-endif  # PLATFORM_EC_POWERSEQ_AMD
-
-menuconfig PLATFORM_EC_POWERSEQ_INTEL
-	bool "Enable shimming common Intel power sequencing code"
-	depends on AP_X86_INTEL
-	select HAS_TASK_POWERBTN
-	default y
-	help
-	  Enable shimming platform/ec AP power sequencing code for
-	  Intel.
-
-if PLATFORM_EC_POWERSEQ_INTEL
-
-config PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
-	bool "The CPU_PROCHOT signal is an active low signal"
-	default y
-	help
-	  If CPU_PROCHOT should be treated as active-low, enable this
-	  configuration option.
-
-config PLATFORM_EC_POWERSEQ_RSMRST_DELAY
-	bool "Wait at least 10ms before deasserting RSMRST to PCH"
-	default y if AP_X86_INTEL_TGL
-	help
-	  Wait at least 10ms between power signals going high and
-	  deasserting RSMRST to PCH.
-
-config PLATFORM_EC_POWERSEQ_RTC_RESET
-	bool "Board has an RTC reset"
-	help
-	  This project has a gpio named GPIO_PCH_RTCRST defined in
-	  gpio_map.h, which can be used to reset the AP's RTC when set
-	  high.
-
-config PLATFORM_EC_POWERSEQ_S0IX
-	bool "Enable S0ix sleep states"
-	select PLATFORM_EC_POWERSEQ_HOST_SLEEP
-	help
-	  Enable the CONFIG_POWER_S0IX platform/ec configuration
-	  option, Intel's low-power idle sleep state, also known as
-	  "modern sleep".
-
-config PLATFORM_EC_POWERSEQ_COMETLAKE
-	bool "Use common Comet Lake code for power sequencing"
-	depends on AP_X86_INTEL_CML
-	default y
-	help
-	  Use the Comet Lake code for power sequencing.
-
-menuconfig PLATFORM_EC_POWERSEQ_ICELAKE
-	bool "Use common Icelake code for power sequencing"
-	default y if AP_X86_INTEL_TGL
-	default y if AP_X86_INTEL_ADL
-	help
-	  Use the Icelake common code for power sequencing.  Note that
-	  this applies to more platforms than just Icelake.  For
-	  example, Tigerlake uses this code too.
-
-if PLATFORM_EC_POWERSEQ_ICELAKE
-
-config PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
-	bool "Enable a quirk to release SLP_S3_L after DSW_PWROK is high"
-	default y if AP_X86_INTEL_TGL
-	help
-	  Enable a quirk to reconfigure SLP_S3_L back to an input a
-	  short delay after DSW_PWROK goes high.
-
-config PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
-	bool "Turn on the PP3300 rail before PP5000"
-	default y if AP_X86_INTEL_TGL
-	help
-	  When switching from G3 to S5, turn on the PP3300 rail before
-	  the PP5500 rail.
-
-endif # PLATFORM_EC_POWERSEQ_ICELAKE
-
-endif # PLATFORM_EC_POWERSEQ_INTEL
-
-menuconfig PLATFORM_EC_POWERSEQ_IT8XXX2
-	bool "Enable shimming common ITE8xxx2 power sequencing code"
-	depends on AP_ARM_MTK_MT8192
-	default y
-	help
-	  Enable shimming platform/ec AP power sequencing code for
-	  IT8xxx2.
-
-if PLATFORM_EC_POWERSEQ_IT8XXX2
-
-config PLATFORM_EC_POWERSEQ_MT8192
-	bool "Use common MT8192 code for power sequencing"
-	default y
-	help
-	  Use the Comet Lake code for power sequencing.
-
-endif # PLATFORM_EC_POWERSEQ_ITE8XXX2
-
-config PLATFORM_EC_POWERSEQ_SC7180
-	bool "SC7180 power sequencing"
-	depends on AP_ARM_QUALCOMM_SC7180
-	default y
-	help
-	  Enable power sequencing for the Qualcomm Snapdragon SC7180
-	  chipset.
-
-config PLATFORM_EC_POWERSEQ_SC7280
-	bool "SC7280 power sequencing"
-	depends on AP_ARM_QUALCOMM_SC7280
-	default y
-	help
-	  Enable power sequencing for the Qualcomm Snapdragon SC7280
-	  chipset.
-
-config PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
-	bool "Console command: s5_timeout"
-	help
-	  Enable the console command 's5_timeout'. This command is used to
-	  change the timeout waiting for inactivity in the S5 power state before
-	  transitioning to the G3 state. This command is useful for power
-	  testing.
-
-endif # PLATFORM_EC_POWERSEQ
diff --git a/zephyr/Kconfig.rtc b/zephyr/Kconfig.rtc
deleted file mode 100644
index 5f36893122..0000000000
--- a/zephyr/Kconfig.rtc
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_RTC
-
-config PLATFORM_EC_CONSOLE_CMD_RTC
-	bool "Console command: rtc"
-	help
-	  This command allows getting and setting the current RTC value. The
-	  value is in seconds since the Epoch (midnight on 1/1/70). You can
-	  convert this to a human date on the command line with 'date -u -d @n'
-	  where n is the numeric value. To convert a time to seconds, use:
-
-	     date -d '1970-01-01 UTC + n seconds'
-
-config PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
-	bool "Console command: rtc_alarm"
-	depends on PLATFORM_EC_CONSOLE_CMD_RTC
-	help
-	  This command supports setting a real-time-clock (RTC) alarm that
-	  causes an interrupt when the timer reaches that point. To set the
-	  alarm:
-
-	     rtc <sec> [<usec>]
-
-	  where:
-	    <sec> is the number of seconds since the epoch
-	    <usec> is the optional number of microseconds (fractional seconds)
-
-config PLATFORM_EC_HOSTCMD_RTC
-	bool "Host command: EC_CMD_RTC_GET_VALUE etc."
-	depends on PLATFORM_EC_HOSTCMD
-	help
-	  Enables support for EC_CMD_RTC_GET_VALUE, EC_CMD_RTC_SET_VALUE,
-	  EC_CMD_RTC_GET_ALARM and EC_CMD_RTC_SET_ALARM which colectively allow
-	  the AP to control the EC's real-time-clock. The AP typically makes
-	  use of the EC's RTC to avoid needing a discrete RTC chip on the board.
-
-endif # PLATFORM_EC_RTC
diff --git a/zephyr/Kconfig.sensor_devices b/zephyr/Kconfig.sensor_devices
deleted file mode 100644
index 623919d775..0000000000
--- a/zephyr/Kconfig.sensor_devices
+++ /dev/null
@@ -1,113 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menu "Sensor Devices"
-
-config PLATFORM_EC_ACCELGYRO_BMI
-	bool "Config used to include common accelgyro BMI features"
-	help
-	  Do not set this directly in a .conf file. This value should be set
-	  using an `select` statement in other BMI family of drivers such as
-	  BMI260.
-
-config PLATFORM_EC_ACCELGYRO_ICM
-	bool "Config used to include common accelgyro ICM features"
-	help
-	  Do not set this directly in a .conf file. This value should be set
-	  using an `select` statement in other ICM family of drivers such as
-	  ICM426XX.
-
-config PLATFORM_EC_ACCEL_BMA255
-	bool "BMA2X2 Accelerometer Family Driver"
-	help
-	  The driver supports Bosch's a triaxial, low-g acceleration sensor.
-	  It allows measurements of acceleration in three perpendicular axes.
-	  Currently the driver supports BMA253, BMA255, BMA355, BMA280, BMA282,
-	  BMA223, BMA254, BMA284, BMA250E, BMA222E, BMC150 BMC056, BMC156.
-
-config PLATFORM_EC_ACCEL_BMA4XX
-	bool "BMA4XX Accelerometer Family Driver"
-	help
-	  The driver supports Bosch's a triaxial, low-g acceleration sensor.
-	  It allows measurements of acceleration in three perpendicular axes.
-	  Currently the driver supports BMA4XX.
-
-config PLATFORM_EC_ACCEL_KX022
-	bool "KX022 Accelerometer Driver"
-	help
-	  The driver supports Kionix's KX022 triaxial low-g acceleration sensor.
-	  It allows measurements of acceleration in three perpendicular axes.
-
-config PLATFORM_EC_ACCEL_LIS2DW12
-	bool "LIS2DW12 Accelerometer Driver"
-	select PLATFORM_EC_STM_MEMS_COMMON
-	help
-	  The driver supports ST's LIS2DW12 3D digital accelerometer sensor.
-	  It allows measurements of acceleration in three perpendicular axes.
-
-config PLATFORM_EC_ACCEL_LIS2DW12_AS_BASE
-	bool "LIS2DW12 Interrupt force mode"
-	depends on PLATFORM_EC_ACCEL_LIS2DW12
-	help
-	  The LIS2DW driver supports fifo and interrupt, but letting lid accel
-	  sensor work at polling mode is a common selection in current usage
-	  model. This option will select interrupt (foced mode).
-
-config PLATFORM_EC_ACCELGYRO_BMI160
-	bool "BMI160 Accelgyrometer Driver"
-	select PLATFORM_EC_ACCELGYRO_BMI
-	help
-	  The driver supports Bosch's BMI160 which is an Inertial Measurement
-	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
-	  tri-axial accelerometer.
-
-config PLATFORM_EC_ACCELGYRO_BMI260
-	bool "BMI260 Accelgyrometer Driver"
-	select PLATFORM_EC_ACCELGYRO_BMI
-	help
-	  The driver supports Bosch's BMI260 which is an Inertial Measurement
-	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
-	  tri-axial accelerometer.
-
-config PLATFORM_EC_ACCELGYRO_BMI3XX
-	bool "BMI3XX Accelgyrometer Driver"
-	select PLATFORM_EC_ACCELGYRO_BMI
-	help
-	  The driver supports Bosch's BMI3XX which is an Inertial Measurement
-	  Unit (IMU) consisting of a 16-bit tri-axial gyroscope and a 16-bit
-	  tri-axial accelerometer.
-
-config PLATFORM_EC_ALS_TCS3400
-	bool "TCS3400 Ambient Light Senseor Driver"
-	help
-	  The driver supports TCS3400 which provides color and
-	  IR (red, green, blue, clear and IR) ambient light sensing.
-
-config PLATFORM_EC_ACCELGYRO_ICM426XX
-	bool "ICM426XX Accelgyro Driver"
-	select PLATFORM_EC_ACCELGYRO_ICM
-	help
-	  The driver supports ICM425XX which provides both accelerometer and
-	  gyroscope readings.
-
-config PLATFORM_EC_ACCELGYRO_ICM42607
-	bool "ICM42607 Accelgyro Driver"
-	select PLATFORM_EC_ACCELGYRO_ICM
-	help
-	  The driver supports ICM42607 which provides both accelerometer and
-	  gyroscope readings.
-
-config PLATFORM_EC_STM_MEMS_COMMON
-	bool
-	help
-	  The driver supports functionality that is common to
-	  STMicroelectronics(STM) micro-electromechanical system(MEMS)
-	  sensor devices.  This should be enabled by drivers that use
-	  this common framework.  It cannot be set otherwise, even in
-	  prj.conf.
-
-rsource "Kconfig.accelgyro_bmi"
-rsource "Kconfig.accelgyro_icm"
-
-endmenu # Sensor devices
diff --git a/zephyr/Kconfig.stacks b/zephyr/Kconfig.stacks
deleted file mode 100644
index 8df0ca23f1..0000000000
--- a/zephyr/Kconfig.stacks
+++ /dev/null
@@ -1,111 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-##############################################################################
-if SOC_SERIES_NPCX7
-
-# Zephyr internal stack sizes
-
-config IDLE_STACK_SIZE
-	default 192
-
-config ISR_STACK_SIZE
-	default 1024
-
-config SHELL_STACK_SIZE
-	default 1536
-
-config SYSTEM_WORKQUEUE_STACK_SIZE
-	default 704
-
-# Chromium EC stack sizes
-
-config TASK_CHARGER_STACK_SIZE
-	default 704
-
-config TASK_CHG_RAMP_STACK_SIZE
-	default 608
-
-config TASK_CHIPSET_STACK_SIZE
-	default 1056
-
-config TASK_HOOKS_STACK_SIZE
-	default 672
-
-config TASK_HOSTCMD_STACK_SIZE
-	default 672
-
-config TASK_KEYPROTO_STACK_SIZE
-	default 640
-
-config TASK_KEYSCAN_STACK_SIZE
-	default 640
-
-config TASK_MOTIONSENSE_STACK_SIZE
-	default 800
-
-config TASK_POWERBTN_STACK_SIZE
-	default 672
-
-config TASK_PD_STACK_SIZE
-	default 1184
-
-config TASK_PD_INT_STACK_SIZE
-	default 736
-
-config TASK_USB_CHG_STACK_SIZE
-	default 544
-
-endif # SOC_SERIES_NPCX7
-##############################################################################
-
-
-##############################################################################
-if SOC_SERIES_NPCX9
-
-# Zephyr internal stack sizes
-
-config IDLE_STACK_SIZE
-	default 192
-
-config ISR_STACK_SIZE
-	default 1024
-
-config SHELL_STACK_SIZE
-	default 1536
-
-config SYSTEM_WORKQUEUE_STACK_SIZE
-	default 800
-
-# Chromium EC stack sizes
-
-config TASK_CHARGER_STACK_SIZE
-	default 750
-
-config TASK_CHIPSET_STACK_SIZE
-	default 684
-
-config TASK_HOOKS_STACK_SIZE
-	default 672
-
-config TASK_HOSTCMD_STACK_SIZE
-	default 700
-
-config TASK_KEYSCAN_STACK_SIZE
-	default 700
-
-config TASK_MOTIONSENSE_STACK_SIZE
-	default 812
-
-config TASK_PD_STACK_SIZE
-	default 1184
-
-config TASK_PD_INT_STACK_SIZE
-	default 736
-
-config TASK_USB_CHG_STACK_SIZE
-	default 544
-
-endif # SOC_SERIES_NPCX9
-##############################################################################
diff --git a/zephyr/Kconfig.system b/zephyr/Kconfig.system
deleted file mode 100644
index c9b67a6ab7..0000000000
--- a/zephyr/Kconfig.system
+++ /dev/null
@@ -1,49 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC
-
-config PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD
-	bool "Console Command: scratchpad"
-	help
-	  Enable the scratchpad console command. The scratchpad register
-	  maintain its contents across a software-requested warm reset. The
-	  command is used to set or get the scratchpad.
-
-config PLATFORM_EC_CONSOLE_CMD_SYSINFO
-	bool "Console Command: sysinfo"
-	default y
-	help
-	  Enable the sysinfo console command, which shows statistics
-	  about the current image copy running, reset flags, etc.
-
-config PLATFORM_EC_HIBERNATE_PSL
-	bool "System hibernating with PSL (Power Switch Logic) mechanism"
-	depends on SOC_FAMILY_NPCX
-	help
-	  Use PSL (Power Switch Logic) for hibernating. It turns off VCC power
-	  rail for ultra-low power consumption and uses PSL inputs rely on VSBY
-	  power rail to wake up ec and the whole system.
-
-config PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
-	int "System pre-initialization priority"
-	default 20
-	range 0 99
-	help
-	  This defines the initialization priority for the CROS
-	  system_pre_init() function. system_pre_init() reads chip level reset
-	  cause and stores it into the system reset flags. All drivers, except
-	  those critical to determining the reset type, should be initialized at
-	  lower priority so that the system reset flags are valid.
-
-config PLATFORM_EC_FW_RESET_VECTOR
-	bool "Firmware Reset Vector chip specific retrieval"
-	default y if SOC_FAMILY_RISCV_ITE
-	help
-	  This defines if there is a chip specific machanism for
-	  retrieving the firmware reset vector. The function that
-	  needs to be provided is system_get_fw_reset_vector that
-	  will return the address of the reset vector.
-
-endif # PLATFORM_EC
diff --git a/zephyr/Kconfig.tasks b/zephyr/Kconfig.tasks
deleted file mode 100644
index 35dfc1c2f1..0000000000
--- a/zephyr/Kconfig.tasks
+++ /dev/null
@@ -1,303 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Please keep these tasks in alphabetical order
-
-menu "Tasks"
-
-config HAS_TASK_CHARGER
-	bool "Charger task"
-	depends on PLATFORM_EC_BATTERY
-	help
-	  This turns on the charger task. This deals with monitoring the
-	  battery to make sure it is present and is responding properly to
-	  requests. If the battery is not full, it enables charging from a
-	  suitable power source.
-
-if HAS_TASK_CHARGER
-
-config TASK_CHARGER_STACK_SIZE
-	int "Stack size"
-	default 1024	# EC uses VENTI_TASK_STACK_SIZE which is 896
-	help
-	  The stack size of the charger task.
-
-	  See b/176180736 for checking these stack sizes.
-
-endif # HAS_TASK_CHARGER
-
-config HAS_TASK_CHG_RAMP
-	bool "Charger-ramp task"
-	depends on PLATFORM_EC_BATTERY
-	help
-	  This turns on the charger ramp task. This attempts to ramp up the
-	  current from an attached charger to the maximum available current.
-	  It handles the incoming VBUS voltage sagging as well as the user
-	  attaching different chargers.
-
-if HAS_TASK_CHG_RAMP
-
-config TASK_CHG_RAMP_STACK_SIZE
-	int "Stack size"
-	default 768	# EC uses TASK_STACK_SIZE which is 512 for npcx
-	help
-	  The stack size of the charger task.
-
-	  See b/176180736 for checking these stack sizes.
-
-endif # HAS_TASK_CHG_RAMP
-
-config HAS_TASK_CHIPSET
-	bool "Chipset task"
-	depends on PLATFORM_EC_POWERSEQ
-	help
-	  This turns on the chipset task which handles powering the chipset
-	  on and off. Powering on involves going through a sequence of enabling
-	  different power rails (e.g. by enabling GPIOs that control a PMIC)
-	  and monitoring power-good indicators to meet the specifications
-	  defined by the vendor.
-
-if HAS_TASK_CHIPSET
-
-config TASK_CHIPSET_STACK_SIZE
-	int "Stack size"
-	default 1024
-	help
-	  The stack size of the power button task.
-
-endif # HAS_TASK_CHIPSET
-
-config HAS_TASK_HOOKS
-	bool "Hooks task"
-	default y
-	help
-	  This required task runs periodic routines connected to the HOOK_TICK
-	  and HOOK_SECOND events. This task is responsible for running
-	  deferred routines.
-
-if HAS_TASK_HOOKS
-
-config TASK_HOOKS_STACK_SIZE
-	int "Stack size"
-	default 1024
-	help
-	  The stack size of the hooks task.
-
-	  See b/176180736 for checking these stack sizes.
-
-endif # HAS_TASK_HOOKS
-
-config HAS_TASK_HOSTCMD
-	bool "Host-command task"
-	depends on PLATFORM_EC_HOSTCMD
-	help
-	  This turns on the hostcmd task which handles communication with the
-	  AP. The AP sends a command to the EC and it responds when able. An
-	  interrupt can be used to indicate to the AP that the EC has something
-	  for it.
-
-if HAS_TASK_HOSTCMD
-
-config TASK_HOSTCMD_STACK_SIZE
-	int "Stack size"
-	default 1024
-	help
-	  The size of the host-command task stack.
-
-endif # HAS_TASK_HOSTCMD
-
-config HAS_TASK_KEYPROTO
-	bool "Keyboard-protocol task (x86)"
-	depends on PLATFORM_EC_KEYBOARD_PROTOCOL_8042
-	help
-	  This turns on the keyproto task which handles conversion of keyboard
-	  scans into i8042 messages on x86 platforms. This is not used or needed
-	  on ARM platforms, which send the raw keyboard scans to the AP for
-	  processing.
-
-if HAS_TASK_KEYPROTO
-
-config TASK_KEYPROTO_STACK_SIZE
-	int "Stack size"
-	default 768
-	help
-	  The stack size of the keyproto task.
-
-endif # HAS_TASK_KEYPROTO
-
-config HAS_TASK_KEYSCAN
-	bool "Keyboard-scanning task"
-	depends on PLATFORM_EC_KEYBOARD
-	help
-	  This turns on the keyscan task which handles scanning the keyboard
-	  and producing a list of changes in the key state. This list can either
-	  be sent to the keyboard-protocol task or directly to the AP for
-	  processing.
-
-if HAS_TASK_KEYSCAN
-
-config TASK_KEYSCAN_STACK_SIZE
-	int "Stack size"
-	default 768
-	help
-	  The stack size of the keyscan task.
-
-endif # HAS_TASK_KEYSCAN
-
-config HAS_TASK_MOTIONSENSE
-	bool "Enable motionsense task"
-	help
-	  This turns on the motion sense task which collects sensor data from the
-	  sensors and reports them to AP. Using the data, it also produces other
-	  meaningful reports to AP like lid angle and tablet mode.
-
-if HAS_TASK_MOTIONSENSE
-
-config TASK_MOTIONSENSE_STACK_SIZE
-	int "motionsense task stack size"
-	default 4096
-	help
-	  The size of the motion sense task stack.
-
-endif # HAS_TASK_MOTIONSENSE
-
-config HAS_TASK_POWERBTN
-	bool "Power-button task (x86)"
-	depends on PLATFORM_EC_POWER_BUTTON
-	help
-	  This turns on the powerbtn task which handles monitoring the power
-	  button. When the application processor (AP) is off (S5 or G3 states),
-	  this task triggers a power-up sequence on a power-button press. When
-	  the AP is on (S3 or above state) x86 machines normally reset when the
-	  power button is held for 4 seconds but this tasks adjusts that to 8
-	  seconds, to allow time for the usual Chromium OS shutdown sequence.
-
-if HAS_TASK_POWERBTN
-
-config TASK_POWERBTN_STACK_SIZE
-	int "Stack size"
-	default 1024
-	help
-	  The stack size of the power-button task.
-
-endif # HAS_TASK_POWERBTN
-
-config HAS_TASK_PD_C0
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	default y
-	help
-	  This turns on the PD_C0 task which handles the rather complex USB
-	  Power Delivery protocol for port 0. There is one of these tasks for
-	  each USB-C port on the device, but they are enabled separately
-	  depending on how many ports are present.
-
-if HAS_TASK_PD_C0
-
-config TASK_PD_STACK_SIZE
-	int "Stack size"
-	default 1024	# EC uses VENTI_TASK_STACK_SIZE which is 896
-	help
-	  The stack size of the PD_Cx tasks.
-
-endif # HAS_TASK_PD_C0
-
-config HAS_TASK_PD_C1
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_C1 task for devices with >=2 ports.
-
-config HAS_TASK_PD_C2
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_C2 task for devices with >=3 ports.
-
-config HAS_TASK_PD_C3
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_C3 task for devices with 4 ports.
-
-config HAS_TASK_PD_INT_C0
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	default y
-	help
-	  This turns on the PD_INT_C0 task which handles servicing of Power
-	  Delivery (PD) message interrupts for port 0. There is one of these
-	  tasks for each USB-C port on the device, but they are enabled
-	  separately depending on how many ports are present.
-
-if HAS_TASK_PD_INT_C0
-
-config TASK_PD_INT_STACK_SIZE
-	int "Stack size"
-	default 1280
-	help
-	  The stack size of the PD_Cn_INT tasks.
-
-endif # HAS_TASK_PD_INT_C0
-
-config HAS_TASK_PD_INT_C1
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_INT_C1 task for devices with >=2 ports.
-
-config HAS_TASK_PD_INT_C2
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_INT_C2 task for devices with >=3 ports.
-
-config HAS_TASK_PD_INT_C3
-	bool "USB Power Delivery task"
-	depends on PLATFORM_EC_USB_POWER_DELIVERY
-	help
-	  This turns on the PD_INT_C3 task for devices with 4 ports.
-
-config HAS_TASK_USB_CHG_P0
-	bool "USB Charger (port 0)"
-	depends on PLATFORM_EC_USB_CHARGER
-	help
-	  This turns on the USB charger task for port 0. This handles
-	  negotiating power from an attached charger, trying to get the maximum
-	  available power consistent with the needs of the device.
-
-	  There is one of these tasks for each USB-C port on the device.
-
-if HAS_TASK_USB_CHG_P0
-
-config TASK_USB_CHG_STACK_SIZE
-	int "(all ports) task stack size"
-	default 1280	# EC uses VENTI_TASK_STACK_SIZE which is 896
-	help
-	  The stack size of the USB charger task. If there are multiple tasks,
-	  each one gets the same stack size.
-
-	  See b/176180736 for checking these stack sizes.
-
-endif # HAS_TASK_USB_CHG_P0
-
-config HAS_TASK_USB_CHG_P1
-	bool "USB Charger (port 1)"
-	help
-	  This turns on the USB charger task for port 1. This handles
-	  negotiating power from an attached charger, trying to get the maximum
-	  available power consistent with the needs of the device.
-
-	  There is one of these tasks for each USB-C port on the device.
-
-config HAS_TASK_USB_CHG_P2
-	bool "USB Charger (port 2)"
-	help
-	  This turns on the USB charger task for port 2. This handles
-	  negotiating power from an attached charger, trying to get the maximum
-	  available power consistent with the needs of the device.
-
-	  There is one of these tasks for each USB-C port on the device.
-
-endmenu # Tasks
diff --git a/zephyr/Kconfig.temperature b/zephyr/Kconfig.temperature
deleted file mode 100644
index 4af5aa99f8..0000000000
--- a/zephyr/Kconfig.temperature
+++ /dev/null
@@ -1,65 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig PLATFORM_EC_TEMP_SENSOR
-	bool "Temperature sensors"
-	help
-	  Support for temperature sensors. Once enabled, "temps" console
-	  command and EC_CMD_TEMP_SENSOR_GET_INFO host command are available.
-
-if PLATFORM_EC_TEMP_SENSOR
-
-config PLATFORM_EC_DPTF
-	bool "Dynamic Platform and Thermal Framework"
-	default y if PLATFORM_EC_ACPI
-	help
-	  Enables the Dynamic Platform and Thermal Framework (DPTF). DPTF
-	  exposes the temperature sensors and the fan controls to the
-	  Applicaiton Processor (AP) using Advanced Configuration and Power
-	  Interface (ACPI). This permits the AP to control thermal management
-	  independent of the EC.
-
-	  Even when DPTF is enabled, the EC still monitors temperature sensors
-	  and will take corrective actions for high temperatures such as turning
-	  on the fans or powering down the AP.
-
-config PLATFORM_EC_THERMISTOR
-	bool "Thermistor support"
-	depends on PLATFORM_EC_ADC
-	help
-	  Enables support for thermistors (resistor whose resistance is
-	  strongly dependent on temperature) as temperature-sensor type.
-
-endif # PLATFORM_EC_TEMP_SENSOR
-
-
-config PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
-	bool "Enable a delay before reading temperature seensors"
-	help
-	  Enables a delay on the first read of temperature sensors after
-	  the EC powers on. This allows for setting of any power rails that
-	  control the temperature sensors on the platform.
-
-if PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
-
-config PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY_MS
-	int "Temperature sensor read delay time"
-	default 500
-	help
-	  Sets the delay time, in milliseconds, before the first the EC will
-	  read any temperature sensors and perform any thermal management.
-
-endif # PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
-
-config PLATFORM_EC_FAN
-	bool "Fan support"
-	depends on PLATFORM_EC_PWM
-	help
-	  Enables support for fans. Allows periodic thermal task to
-	  automatically set the fan speed (control temperature).
-	  Once enabled fanduty, fanset, faninfo, fanauto consol command and
-	  EC_CMD_PWM_GET_FAN_TARGET_RPM, EC_CMD_PWM_SET_FAN_TARGET_RPM,
-	  EC_CMD_PWM_SET_FAN_DUTY, EC_CMD_THERMAL_AUTO_FAN_CTRL are
-	  available. Also enables a periodic task (1s) to verify fan is
-	  running (is not stalled).
diff --git a/zephyr/Kconfig.throttle_ap b/zephyr/Kconfig.throttle_ap
deleted file mode 100644
index 153aefd085..0000000000
--- a/zephyr/Kconfig.throttle_ap
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_THROTTLE_AP
-
-# TODO(b/177676794): Add the CONFIG_THROTTLE_AP_ON_... options
-
-config PLATFORM_EC_CHIPSET_CAN_THROTTLE
-	bool "CPU can support throttling"
-	default y
-	help
-	  Indicates that the SoC supports throttling. This means that a
-	  chipset_throttle_cpu() function is provided by the chipset, to be
-	  called to set the throttle state. The typical implementation asserts
-	  GPIO_CPU_PROCHOT, to make the CPU slow down.
-
-config PLATFORM_EC_CONSOLE_CMD_APTHROTTLE
-	bool "Console command: apthrottle"
-	default y
-	help
-	  This command shows the current status of AP throttling. Both soft
-	  (type 0) and hard (type 1) throttling are supported. Soft throttling
-	  is typically controlled by the AP via a host event. Hard throttling
-	  typically uses the PROCHOT (Processor Hot) signal on x86 CPUs.
-
-	  Example output:
-
-	     AP throttling type 0 is off (0x00000000)
-	     AP throttling type 1 is off (0x00000000)
-
-endif # PLATFORM_EC_THROTTLE_AP
diff --git a/zephyr/Kconfig.timer b/zephyr/Kconfig.timer
deleted file mode 100644
index 5b615961eb..0000000000
--- a/zephyr/Kconfig.timer
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_TIMER
-
-config PLATFORM_EC_CONSOLE_CMD_GETTIME
-	bool "Console command: gettime"
-	default y
-	help
-	  Enable the "gettime" command. This shows the current time (in
-	  microseconds since boot) in both hex and in decimal converted to
-	  seconds. For example:
-
-	     Time: 0x0000000002706a62 = 40.921698 s
-
-
-config PLATFORM_EC_CONSOLE_CMD_TIMERINFO
-	bool "Console command: timerinfo"
-	default y
-	help
-	  Enable the "timerinfo" command which shows the current time (in
-	  microseconds and seconds since boot), the deadline (next time the EC
-	  needs to wake up) and a list of active timers along with when they
-	  will next fire.
-
-	  Example:
-
-	    Time:     0x0000000002706a62 us,   40.921698 s
-	    Deadline: 0x000000000270774d ->    0.003307 s from now
-	    Active timers:
-	      Tsk  1  0x000000000271db8f ->    0.094509
-	      Tsk  4  0x00000000027396b3 ->    0.207953
-	      Tsk 13  0x00000000027133a1 ->    0.051519
-
-
-config PLATFORM_EC_CONSOLE_CMD_WAITMS
-	bool "Console command: waitms"
-	default y
-	help
-	  Enable the "waitms" command. This waits for a given number of
-	  milliseconds. For example:
-
-	    waitms 100
-
-	  waits for 100ms. Note that long waits can introduce problems since
-	  it stops the EC from executing its normal tasks. For example, a
-	  two-second wait can cause the EC to reset.
-
-endif # PLATFORM_EC_TIMER
diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc
deleted file mode 100644
index ee79eb1d04..0000000000
--- a/zephyr/Kconfig.usbc
+++ /dev/null
@@ -1,1231 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# TODO(sjg): Not USB-C: perhaps we should have a 'power' thing at the top level?
-config PLATFORM_EC_USB_A_PORT_COUNT
-	int "Number of USB-A ports"
-	default 0
-	help
-	  This sets the number of USB-A ports on the device. These ports do
-	  not support USB Power Delivery features but can be used to power
-	  external devices (according to the USB 3 spec, not the Battery Charger
-	  standard) and to charge devices slowly if power is enabled to them.
-
-config PLATFORM_EC_USB_PORT_POWER_DUMB
-	bool "Simple control of power to USB-A ports"
-	depends on PLATFORM_EC_USB_A_PORT_COUNT > 0
-	default y
-	help
-	  Enable this to provide simple control of the power to USB ports
-	  using GPIOs. To use this your board code must provide a
-	  usb_port_enable[] array with the GPIOs to use for each port. This
-	  implements the EC_CMD_USB_CHARGE_SET_MODE host command and provides
-	  a 'usbchargemode' console command.
-
-config PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-	bool "Simple control of power to USB-A ports"
-	depends on PLATFORM_EC_USB_PORT_POWER_DUMB
-	help
-	  Enable this if your board does not want to use the default S3 hooks
-	  from USB_PORT_POWER_DUMB.
-
-menuconfig PLATFORM_EC_USBC
-	bool "USB Type-C"
-	default y if PLATFORM_EC_BATTERY
-	help
-	  Enable this to support various USB Type-C features chosen by the
-	  options below. USB-C is widely used on modern Chromebooks and the EC's
-	  role is to negotiate power contracts (for sourcing or sinking power
-	  over USB). The EC is also responsible for discovering the capabilities
-	  of attached USB-C partners and enabling alternate operational modes,
-	  including Display Port, Thunderbolt, and USB4.
-
-if PLATFORM_EC_USBC
-
-config PLATFORM_EC_CHARGE_MANAGER
-	bool "Charge manager"
-	default y
-	help
-	  The EC charge manager manages charging the battery from all supported
-	  power sources.  This includes dedicated charge ports (such as a
-	  barrel jack connector), BC1.2 (Battery Charging 1.2) sources, and
-	  USB-C sources. When multiple charge sources are connected to a
-	  Chromebook simultaneously, the charge manager is responsible for
-	  picking the best source.
-
-	  Note that the charge manager assumes that at least one USB-C power
-	  source is available on the hardware, so cannot be built without
-	  PLATFORM_EC_USBC.
-
-config PLATFORM_EC_CHARGER_INPUT_CURRENT
-	int "Charger input current in mA"
-	depends on PLATFORM_EC_CHARGE_MANAGER
-	default 512
-	help
-	  This is the default input current for the board in mA.  Many boards
-	  also use this as the least maximum input current during transients.
-
-	  This value should depend on external power adapter, designed charging
-	  voltage, and the maximum power of the running system. For type-C
-	  chargers, this should be set to 512 mA in order to not brown-out
-	  low-current USB charge ports in accordance with USB-PD r3.0 Sec. 7.3
-
-menuconfig PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
-	bool "Power requirements to boot AP"
-	default y
-	help
-	  Power thresholds for AP boot.
-	  If one of the following conditions is met, EC boots AP:
-	   1. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON.
-	   2. AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON.
-	   3. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
-	    and
-	    AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT.
-
-if PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
-
-config PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-	int "Minimal battery level to boot AP without AC"
-	depends on PLATFORM_EC_BATTERY
-	default 3
-	help
-	  Sets the minimum battery capacity, as a percentage, needed to boot
-	  the AP when AC power is not supplied.
-
-config PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
-	int "Minimal battery level to boot AP with AC"
-	depends on PLATFORM_EC_BATTERY && PLATFORM_EC_CHARGE_MANAGER
-	default 1
-	help
-	  Sets the minimum battery capacity, as a percentage, needed to boot
-	  the AP when AC power is supplied. The AC power supplied must also
-	  be greater than CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT.
-
-config PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
-	int "Minimal AC power to boot AP with battery"
-	depends on PLATFORM_EC_BATTERY && PLATFORM_EC_CHARGE_MANAGER
-	default 15000
-	help
-	  Sets the minimum power, in milliwatts, supplied by an external
-	  charger required to boot the AP when the battery capacity is also
-	  above CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC.
-
-config PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-	int "Minimal AC power to boot AP without battery"
-	depends on PLATFORM_EC_CHARGE_MANAGER
-	default 15000
-	help
-	  Sets the minimum power, in milliwatts, supplied by an external
-	  charger requires to boot the AP when no battery is present or
-	  under dead battery conditions. If the AP requires greater than
-	  15W to boot, check the
-	  CONFIG_PLATFORM_EC_CHARGER_LIMIT_POWER_THRESH_CHG_MW setting.
-
-endif # PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS
-
-config PLATFORM_EC_USBC_OCP
-	bool
-	help
-	  USB-C overcurrent protection: Enable this to detect when a connected
-	  USB-C partner draws too much power from the Chromebook and
-	  automatically shut off power to the USB-C partner.
-
-	  This should be enabled by drivers which can detect over-current. It
-	  cannot be set otherwise, even in prj.conf
-
-config PLATFORM_EC_USB_PID
-	hex "USB Product ID"
-	help
-	  Each platform (e.g. baseboard set) should have a single VID/PID
-	  combination. If there is a big enough change within a platform,
-	  then we can differentiate USB topologies by varying the hardware
-	  version field in the Sink and Source Capabilities Extended messages.
-
-	  To reserve a new PID within Google, use go/usb and see
-	  http://google3/hardware/standards/usb
-
-config PLATFORM_EC_USB_BCD_DEV
-	hex "USB Device ID"
-	default 0
-	help
-	  This specifies the USB device version, reported by board when acting
-	  as the upstream facing port (UFP). This is a 16-bit unsigned integer
-	  and should be set to a version number relevant to the release version
-	  of the product.
-
-config PLATFORM_EC_USB_VID
-	hex "USB Vendor ID"
-	default 0x18d1
-	help
-	  This specifies the USB vendor ID used for boards which expose a
-	  USB endpont when the port is in UFP mode. The default value is
-	  set to Google's assigned VID and typically would not need to be
-	  changed. But, in certain cases this may need to be changed to
-	  match an OEM's vendor ID.
-
-config PLATFORM_EC_USBC_RETIMER_INTEL_BB
-	bool "Support Intel Burnside Bridge retimer"
-	help
-	  Enable this to support the Intel Burnside Bridge Thunderbolt / USB /
-	  DisplayPort retimer.
-
-	  Intel Burnside Bridge is a Type-C multi-protocol retimer to be used
-	  in on-board applications. Burnside Bridge offers the ability to latch
-	  protocol signals into on-chip memory before retransmitting them
-	  onwards. It can be used to extend the physical length of the system
-	  without increasing high-frequency jitter.
-
-	  Burnside Bridge supports spec compliant retimer of following
-	  protocols:
-
-	    - Display Port: four unidirectional DP lanes
-	    - USB3.1 Gen1/2: one bi-directional USB lane
-	    - Thunderbolt: two bi-directional CIO lanes
-	    - Multifunction Display (MFD): two unidirectional lanes of DP and
-	      one bidirectional lane of USB3.1 Gen1/2
-
-config PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-	bool "Use runtime configuration of Intel Burnside Bridge"
-	depends on PLATFORM_EC_USBC_RETIMER_INTEL_BB
-	default y
-	help
-	  Enable this to allow run-time configuration of the Burnside Bridge
-	  driver structure. This makes the bb_controls[] array writable, i.e.
-	  not const. It should be declared as such in the board config.
-
-	  This is useful when the board has runtime information that changes
-	  the configuration, such as Chromium OS Board Info (CBI set in the
-	  factory. Without this, multiple EC images would need to be installed
-	  depending on the board.
-
-config PLATFORM_EC_USBC_RETIMER_ANX7451
-	bool "Support Analogix ANX7451 10G Active Mux and Retimer"
-	help
-	  ANX7451 is a 4x4 re-timing mux capable of switching DisplayPort (DP)
-	  and USB3.2 Gen 2 10Gbps signals to support a single USB Type-C port.
-	  ANX7451 has built-in re-timers to recover both the USB and DP signals
-	  with loss compensation of 23dB for USB and up to 27dB for DP.
-
-config PLATFORM_EC_USBC_RETIMER_PS8811
-	bool "Support Parade PS8811 Single Port USB 3.1 Gen 2 10G Retimer"
-	help
-	  The PS8811 is a one-port bidirectional USB 3.1 Gen 2 retimer that
-	  integrates the UniEye equalizer and a retimer to re-condition USB 3.1
-	  signals for long media link applications. It supports USB 3.1 Gen 2
-	  with operation speed up to 10Gbps as well as Gen 1 operation at 5Gbps.
-
-config PLATFORM_EC_USBC_RETIMER_KB800X
-	bool "Enable KB800X retimer"
-	help
-	  The KB8001 is a Universal Serial Bus (USB) Type-C 40 Gb/s multiprotocol
-	  switch and bidirectional Bit-Level Retimer (BLR) which supports:
-	    - Display Port: four unidirectional DP lanes
-	    - USB3.1 Gen1/2: one bi-directional USB lane
-	    - USB4/Thunderbolt: two bi-directional CIO lanes
-	    - Multifunction Display (MFD): two unidirectional lanes of DP and
-	      one bidirectional lane of USB3.1 Gen1/2
-
-config PLATFORM_EC_KB800X_CUSTOM_XBAR
-	bool "Use custom remapping of HSIO XBAR"
-	depends on PLATFORM_EC_USBC_RETIMER_KB800X
-	default n
-	help
-	  Enable this to allow using a custom crossbar configuration for the HSIO
-	  lanes.
-
-menuconfig PLATFORM_EC_USB_POWER_DELIVERY
-	bool "USB Type-C Power Delivery (PD)"
-	default y
-	select HAS_TASK_PD_C0
-	help
-	  USB has always provided basic power to an attached peripheral. USB-C
-	  PD is part of the USB 3.0 standard and allows a lot more functionality
-	  than the basic 500mA @ 5V. It allows negotiating power delivery over
-	  the USB cable to select voltages up to 20V with current up to 5A.
-
-	  This option also enables the Type-C Port Manager (TCPM) on the EC. The
-	  TCPM deals with the various state changes in the system as devices are
-	  plugged and unplugged, as well as changes in power requirements from
-	  those devices.
-
-if PLATFORM_EC_USB_POWER_DELIVERY
-
-config PLATFORM_EC_USB_PD_HOST_CMD
-	bool "Host commands related to USB Power Delivery"
-	default y
-	help
-	  This enables host commands which allow finding out the capabilities
-	  of USB PD, checking is status and controlling how it operates. For
-	  devices which support firmware update, this is provided as well,
-	  with the firmware being sent from the AP.
-
-config PLATFORM_EC_USB_PD_PORT_MAX_COUNT
-	int "Maximum number of USB PD ports supported"
-	default 2
-	help
-	  This sets the limit on the number of PD ports supported on the
-	  device. This is used to set the size for tables used by devices.
-
-	  TODO(b/176237074): Can we calculate this from the devicetree at some
-	  point? Or update the sn5S330 driver to use an 8-bit flag byte for
-	  source_enabled[] so that plenty of ports are supported without this
-	  configuration option?
-
-config PLATFORM_EC_CONSOLE_CMD_MFALLOW
-	bool "Console command: mfallow"
-	default y
-	help
-	  Controls whether multi-function support is allowed for DP (Display
-	  Port) connections. Default setting allows multi-function support when
-	  the attached device also supports multi-function mode.
-
-	    mfallow <port> [true | false]
-
-config PLATFORM_EC_CONSOLE_CMD_PD
-	bool "Console command: pd"
-	default y
-	help
-	  Provides information about the current USB Power Delivery state and
-	  also allows various changes to be made for testing purposes.
-
-	  It has a number of subcommands:
-
-	     pd dump <n>  - sets the debug level (0-3). This affects all layers
-	                    of the stack
-	     pd trysrc [0/1/2] - prints or sets the Try.SRC override. Use 0 to
-	                    force Try.SRC off, 1 to force Try.SRC on, and 2 to
-	                    let USB PD stack control the Try.SRC behavior.
-	     pd version   - show PD version in use
-	     pd <port> state  - show start for a PD port
-
-	  Ssee usb_pd_console.c for full details including various commands
-	  for role swap, reset, enable/disable, requesting SNK or SRC, etc.
-
-config PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
-	bool "USB Power Delivery debug level is fixed at build time"
-	help
-	  Enable this to set the debug level to a fixed value in the build.
-	  This saves space but means that the level cannot be changed using
-	  commands like 'pd dump'. Typically this should be set when a platform
-	  is shipped.
-
-config PLATFORM_EC_USB_PD_DEBUG_LEVEL
-	int "Debug level to use"
-	depends on PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
-	help
-	  Sets the value of the debug level to use. If this is 0 then no
-	  debugging output is available from the USB Power Delivery stack.
-	  The meaning of each level depends on the module in question, but
-	  the maximum available level is 3.
-
-config PLATFORM_EC_USB_PD_5V_EN_CUSTOM
-	bool "Custom method of detecting VBUS"
-	help
-	  Enable this if your board needs a custom method to determine if VBUS
-	  is enabled on a source port. You must provide an implementation of:
-
-	     int board_is_sourcing_vbus(int port)
-
-	  It should return 0 if not sourcing VBUS on that port and non-zero
-	  if sourcing.
-
-choice "Measuring VBUS voltage"
-	prompt "Select how VBUS voltage is measured"
-
-config PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT
-	bool "VBUS voltage cannot be read"
-	help
-	  Enable this if the board does not provide any mechanism for the EC to
-	  read the analog VBUS voltage.
-
-config PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER
-	bool "On-board charger supports VBUS measurement"
-	help
-	  Enable this if the VBUS voltage can be read using a charger on the
-	  board.
-
-config PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC
-	bool "Type-C Port Controller supports VBUS measurement"
-	help
-	  Enable this if the VBUS voltage can be read using the on-board
-	  TCPC.
-
-config PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-	bool "VBUS on each port is measured using an ADC channel"
-	help
-	  Enable this is there is a separate ADC channel for each USB-C VBUS
-	  voltage.
-
-endchoice  # Measuring VBUS voltage
-
-config PLATFORM_EC_USBC_VCONN
-	bool "Support USB Type-C VCONN"
-	default y
-	help
-	  This enables support for USB Type-C connector voltage (VCONN). This
-	  option must be enabled to communicate with electronically marked
-	  (E-Mark) cables. This option is required for operation with USB4 and
-	  Thunderbolt devices.
-
-	  This is not needed for captive cables.
-
-config PLATFORM_EC_USB_PD_DUAL_ROLE
-	bool "Board can act as a dual-role Power Delivery port"
-	default y
-	help
-	  This enables support for switching between source and sink during
-	  operation. This means that the port can accept power (e.g. to charge
-	  up its battery), or send out power to an attached device on the same
-	  port.
-
-config PLATFORM_EC_USB_PD_FRS
-	bool "Support Fast Role Swap protocol"
-	help
-	  Enables the protocol side of Fast Role Swap (FRS). This allows the
-	  device to switch from a SNK to a SRC (or vice versa) based on
-	  communication with the partner device.
-
-	  For this to work the trigger must be implemented in either the
-	  Type-C Port Controller (TCPC) or Power Path Controller (PPC).
-
-	  FRS differs from the traditional power-role swap in that FRS
-	  guarantees there is no interruption of power nor disruption of data
-	  communication to any downstream devices (such as devices connected
-	  to a USB-C hub or dock).
-
-if PLATFORM_EC_USB_PD_FRS
-
-choice "Trigger implementation"
-	prompt "Select where the trigger is implemented"
-	help
-	  The Fast Role Swap (protocol requires that a trigger be implemented to
-	  initiate the swap. Use this option to select which of the available
-	  options should be used.
-
-config PLATFORM_EC_USB_PD_FRS_PPC
-	bool "PPC"
-	depends on PLATFORM_EC_USBC_PPC
-	help
-	  Enable this if the Fast Role Swap trigger is implemented in the
-	  Power Path Controller (PPC).
-
-config PLATFORM_EC_USB_PD_FRS_TCPC
-	bool "TCPC"
-	depends on PLATFORM_EC_USBC_TCPC
-	help
-	  Enable this if the Fast Role Swap trigger is implemented in the
-	  Type-C Port Controller (TCPC).
-
-endchoice # Trigger implementation
-
-endif # PLATFORM_EC_USB_PD_FRS
-
-config PLATFORM_EC_USB_PD_DPS
-	bool "Board can support Dynamic PDO Selection"
-	depends on PLATFORM_EC_BATTERY
-	default n
-	help
-	  Enable this if the board needs dynamic PDO selection.
-	  DPS picks a power efficient PDO regarding to the underlying battery
-	  configuration and the system loading.
-	  Default configuration can be overrided by `dps_config` to adapt
-	  to each board's need.
-
-config PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	bool "Board can use TCPC-controlled DRP toggle"
-	depends on PLATFORM_EC_USB_PD_DUAL_ROLE
-	default y
-	help
-	  Enable this if the USB Type-C Port Controllers (TCPC) used on the
-	  board supports toggling of the power role autonomously. When this is
-	  disabled, the USB power delivery task is responsible for manually
-	  toggling the power role.
-
-config PLATFORM_EC_USB_PD_DISCHARGE
-	bool "Board can discharge VBUS"
-	default y
-	help
-	  Enable this if the board can enable VBUS discharge (eg. through a
-	  GPIO-controlled discharge circuit, or through port controller
-	  registers) to discharge VBUS rapidly on disconnect
-
-choice "Discharge method"
-	prompt "Select the discharge method"
-	depends on PLATFORM_EC_USB_PD_DISCHARGE
-
-config PLATFORM_EC_USB_PD_DISCHARGE_GPIO
-	bool "GPIO control"
-	help
-	  Enable this if the discharge circuit is controlled by a GPIO
-
-	  TODO: How to specify the GPIO?
-
-config PLATFORM_EC_USB_PD_DISCHARGE_TCPC
-	bool "Discharge circuit is provided by the TCPC"
-	help
-	  Enable this if the discharge circuit is provided by Power-Delivery
-	  resistors on the USB Type-C Port Controller (TCPC).
-
-config PLATFORM_EC_USB_PD_DISCHARGE_PPC
-	bool "Discharge circuit is provided by the PPC"
-	help
-	  Enable this if the discharge circuit is using Power Delivery
-	  resistors on the Power Path Controller.
-
-endchoice  # Discharge method
-
-config PLATFORM_EC_USB_PD_REV30
-	bool "USB PD Rev3.0 functionality"
-	default y
-	help
-	  Enable this to allow Rev3.0 functionality, including features such as
-	  Fast Role Swap, advertising the available power across all ports of a
-	  multi-port charger, and USB4. If disabled, only USB Power Delivery
-	  Rev2.0 functionality is supported.
-
-	  This defaults to y because PD Rev3.0 is required for USB4
-	  functionality.
-
-config PLATFORM_EC_USB_PD_ALT_MODE
-	bool "USB Power Delivery alternate mode"
-	default y
-	help
-	  Enable this to support USB PD alternate mode. This allows negotiation
-	  of a different mode of operation to allow non-USB traffic to pass over
-	  a USB Type-C link. This makes use of some or all of the USB 3.0 bus
-	  differential pairs. If all are used for the alternate mode, then USB
-	  transmission is not available at all while in this mode.
-
-config PLATFORM_EC_USB_PD_ALT_MODE_DFP
-	bool "Downward Facing Port support"
-	default y
-	help
-	  Enable support for USB Power Delivery alternate mode of Downward
-	  Facing Port.
-
-	  TODO: Add more help here
-
-config PLATFORM_EC_USB_PD_ALT_MODE_UFP
-	bool "Upward Facing Port support"
-	help
-	  Enable support for USB Power Delivery alternate mode of Upward
-	  Facing Port (UFP).
-
-	  By default, Chromium OS only enables alternate modes (Display Port,
-	  USB4, Thuderbolt, etc) when the USB data role resolves to the
-	  Downstream Facing Port (DFP) role. Enable this option to support
-	  USB4 and ThunderBolt operation when the Chromium OS data role
-	  resolves to the UFP role.
-
-config PLATFORM_EC_USB_PD_USB32_DRD
-	bool "Port is cable of operating as an USB3.2 device"
-	default y
-	help
-	  Enable this if the board's USB Power Delivery Downward Facing Port is
-	  able to support the USB3.2 standard. This is advertised to the
-	  other end so that it can potentially take advantage of the additional
-	  features available.
-
-config PLATFORM_EC_USB_PD_DP_HPD_GPIO
-	bool "Hotplug Detect (HPD) is controlled by an EC GPIO"
-	help
-	  Enable this if the EC must send the Hotplug Detect (HPD) signal to
-	  the DisplayPort Graphics Processing Unit (GPU) via a GPIO. Otherwise
-	  this is sent by the display device.
-
-config PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM
-	bool "Custom handling of HPD GPIO"
-	depends on PLATFORM_EC_USB_PD_DP_HPD_GPIO
-	help
-	  Enable this if the Hotplug Detect (HPD) GPIO level has to be handled
-	  by custom functions. In this case your board must implement a
-	  function to enable the feature for a port and another function to
-	  check the current state:
-
-	    void svdm_set_hpd_gpio(int port, int enable);
-
-	    int svdm_get_hpd_gpio(int port);
-
-choice "VBUS detection method"
-	prompt "Select the method to detect VBUS"
-
-config PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC
-	bool "TCPC detects VBUS"
-	help
-	  Choose this option if the TCPC can detect the presence of VBUS
-
-config PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER
-	bool "Charger detects VBUS"
-	help
-	  Choose this option if the battery charger can detect the presence
-	  of VBUS
-
-config PLATFORM_EC_USB_PD_VBUS_DETECT_PPC
-	bool "PPC detects VBUS"
-	help
-	  Choose this option if the Power-Path Controller (PPC) can detect the
-	  presence of VBUS
-
-config PLATFORM_EC_USB_PD_VBUS_DETECT_NONE
-	bool "No way to detect VBUS"
-	help
-	  Choose this option if it is not possible to detect VBUS.
-
-endchoice  # VBUS detection method
-
-config PLATFORM_EC_USB_TYPEC_SM
-	bool "Type-C (TC) physical-layer state machine"
-	default y
-	help
-	  This enables the bottom layer of the TCPMv2 state machine which
-	  handles using CC lines to set the voltage-level of the power supplied.
-	  You should normally define this unless you want to override it in your
-	  board code, which is not recommended.
-
-config PLATFORM_EC_USB_PRL_SM
-	bool "Protocol layer (PRL) state machine"
-	default y
-	help
-	  This enables the middle layer of the power-delivery (PD) protocol,
-	  which deals with the flow of power messages across the USB Type-C
-	  interface. You should normally define this unless you want to override
-	  it in your board code, which is not recommended.
-
-config PLATFORM_EC_USB_PE_SM
-	bool "Policy engine (PE) state machine"
-	default y
-	help
-	  This enables the top layer of the power-delivery (PD) protocol, which
-	  deals with the actually PD messages that are exchanged with attached
-	  USB devices. You should normally define this unless you want to
-	  override it in your board code, which is not recommended.
-
-config PLATFORM_EC_USB_PD_DECODE_SOP
-	def_bool y  # Required for TCPMV2
-	help
-	  This enables support for encoding of the message's Start Of Packet
-	  (SOP, SOP' and SOP'', collectively called SOP*) in bits 31-28 of the
-	  32-bit msg header type.
-
-config PLATFORM_EC_HOSTCMD_PD_CONTROL
-	bool "Host command: EC_CMD_PD_CONTROL"
-	default y
-	help
-	  Enable the EC_CMD_PD_CONTROL host command. This allows control
-	  of the USB-PD chip from the AP, including reset, suspend/resume
-	  and enabling power.
-
-	  This host command can be manually executed using the
-	  "ectool pdcontrol" command from the Chromium OS shell.
-
-config PLATFORM_EC_USB_PD_LOGGING
-	bool "Host command: EC_CMD_PD_GET_LOG_ENTRY"
-	help
-	  Enable logging of USB Power Delivery events. The AP can request the
-	  log to see what has happened recently.
-
-	  The log events are stored in a circular buffer, each one being a
-	  struct event_log_entry.
-
-menuconfig PLATFORM_EC_USB_PD_CONSOLE_CMD
-	bool "Enable USB PD console commands"
-	default y if PLATFORM_EC_USB_PD_ALT_MODE_DFP
-	help
-	  Enables various USB-C PD related console commands.
-
-if PLATFORM_EC_USB_PD_CONSOLE_CMD
-
-config PLATFORM_EC_CONSOLE_CMD_USB_PD_PE
-	bool "Console command: pe"
-	default y
-	help
-	  This command dumps information about the USB PD alternate mode options
-	  discovered from the partner device. It can be useful for debugging.
-
-	  Example: pe 1 dump
-	     IDENT SOP:
-
-	             [ID Header] 2c000bda :: AMA, VID:0bda
-	             [Cert Stat] 00000000
-	             [2] 00000209    [3] 11000f09
-	     IDENT SOP':
-	             [ID Header] 1c000489 :: PCable, VID:0489
-	             [Cert Stat] 000001c6
-	             [2] f6810000    [3] 11082051
-	     SVID[0]: ff01 MODES: [1] 000c0045
-	     MODE[1]: svid:ff01 caps:000c0045
-
-config PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE
-	bool "Console command: pdcable"
-	default y
-	help
-	  This commands shows the USB cable charactistics as detected from the
-	  device. It can be useful for debugging problems with cables and the
-	  device's response to them.
-
-	  Example: pdcable 1
-	     Cable Type: Passive
-	     Cable Rev: 1.0
-	     Connector Type: 2
-	     Cable Current: 5A
-	     USB Superspeed Signaling support: 1
-	     Rounded support: No
-	     Optical cable: No
-	     Retimer support: No
-	     Link training: Bi-directional
-	     Thunderbolt cable type: Passive
-
-endif  # PLATFORM_EC_USB_PD_CONSOLE_CMD
-
-choice "USB-C device type"
-	prompt "Select the USB-C device type"
-	default PLATFORM_EC_USB_DRP_ACC_TRYSRC
-
-config PLATFORM_EC_USB_VPD
-	bool "VCONN-Powered Device"
-	help
-	  This enables support for supplying power to devices that accept power
-	  over the USB VCONN line.
-
-	  See here for details:
-
-	  https://www.usb.org/sites/default/files/D1T2-3a%20-%20CTVPDs%20and%20Making%20Your%20Own%20USB-C%20Thingamajig.pdf
-
-config PLATFORM_EC_USB_CTVPD
-	bool "Charge-Through VCONN-Powered Device"
-	help
-	  This enables support for supplying power to devices, with a circuit
-	  that deals with this without needing the involvement of the main
-	  device.
-
-config PLATFORM_EC_USB_DRP_ACC_TRYSRC
-	bool "Dual-Role Port, Audio Accessory, and Try.SRC Device"
-	help
-	  This is the most flexible option, allowing the port to operate in
-	  a dual-role capacity, so that power can be accepted or supplied on
-	  a port.
-
-endchoice  # USB-C device type
-
-config PLATFORM_EC_USB_PD_TRY_SRC
-	bool "Enable Try.SRC mode"
-	depends on PLATFORM_EC_USB_DRP_ACC_TRYSRC
-	default y
-	help
-	  This enables Try.SRC mode so that the board will try to be a source
-	  for power if the other end offers both options. This can be useful
-	  for laptops, for example, since when attaching to a cellphone we want
-	  the laptop to charge the phone, not vice versa.
-
-config PLATFORM_EC_USB_PD_USB4
-	bool "USB4 support"
-	depends on PLATFORM_EC_USB_PD_REV30
-	default y
-	help
-	  This enables support for entering into USB4 mode between two port
-	  partners. The provides new features such as higher speeds and more
-	  flexible multiplexing of data on the cable for different purposes,
-	  e.g. attaching multiple displays and storage devices on the same bus.
-
-config PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
-	bool "Thunderbolt-compatible mode support"
-	depends on PLATFORM_EC_USB_PD_REV30
-	default y
-	help
-	  Enable this to allow entering into Thunderbolt-compatible mode between
-	  two port partners. This does not require that USB4 mode be enabled.
-
-endif  # PLATFORM_EC_USB_POWER_DELIVERY
-
-menuconfig PLATFORM_EC_USBC_PPC
-	bool "USB Type-C Power Path Controller"
-	default y
-	help
-	  Enable this to support the USB Type-C PPC on your board. This enables
-	  common routines for things like figuring out whether power is being
-	  supplied to the Chromebook over USB-C, whether the Chromebook is
-	  supplying power to another device, etc.
-
-if PLATFORM_EC_USBC_PPC
-
-config PLATFORM_EC_USBC_PPC_POLARITY
-	bool
-	help
-	  Enable this if a Power Path Controller needs to be informed of
-	  the polarity of the Configuration Channel (CC) pins. This can change
-	  depending on which way up the USB-C cable is inserted into the
-	  device.
-
-	  This should be enabled by drivers which can detect this. It cannot be
-	  set otherwise, even in prj.conf
-
-config PLATFORM_EC_USBC_PPC_SBU
-	bool
-	help
-	  Enable this if a Power Path Controller is capable of gating the
-	  Sideband Use (SBU) lines. If so, the USB mux will use this feature
-	  to isolate the lines before entering into alternate mode.
-
-	  This should be enabled by drivers which can detect this. It cannot be
-	  set otherwise, even in prj.conf
-
-config PLATFORM_EC_USBC_PPC_VCONN
-	bool
-	depends on PLATFORM_EC_USBC_VCONN
-	help
-	  Enable this if a Power Path Controller is capable of providing
-	  VCONN. If so, the USB stack will enable / disable VCONN as needed.
-
-	  This should be enabled by drivers which can detect this. It cannot be
-	  set otherwise, even in prj.conf
-
-	  Note: This may not be true, as there may be scenarios where the board
-	  might need to disable this feature (for instance when both the PPC and
-	  TCPC can supply VCONN). We can cross that bridge when we come to it.
-
-config PLATFORM_EC_USBC_PPC_SN5S330
-	bool "TI SN5S330 PD 3.0 power mux"
-	select PLATFORM_EC_USBC_OCP
-	select PLATFORM_EC_USBC_PPC_POLARITY
-	select PLATFORM_EC_USBC_PPC_SBU
-	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
-	help
-	  This is a USB Type-C Power Delivery 3.0 Bidirectional Power Mux with
-	  CC and SBU short-to-VBUS Protection and Integrated Dead Battery
-	  LDO. This chips provides protection against pins shorting to Vbus as
-	  well as ESD (Electostatic discharge) protection. It provides a simple
-	  I2C interface for for Mode Selection, Fast Role Swap, and Fault
-	  Reporting.
-
-config PLATFORM_EC_USBC_PPC_SYV682X
-	bool "SYV682X which is a Power Mux for USB PD"
-	select PLATFORM_EC_USBC_OCP
-	select PLATFORM_EC_USBC_PPC_POLARITY
-	select PLATFORM_EC_USBC_PPC_VCONN if PLATFORM_EC_USBC_VCONN
-	help
-	  The SYV682A is a 2 to 1 power mux switch for USB PD applications. The
-	  SYV682A supports dead battery wake up function and Fast Role Swap
-	  features. It provides protection against overcurrent, overvoltage,
-	  thermal shutdown, and undervoltage conditions.
-
-config PLATFORM_EC_USBC_PPC_SYV682C
-	bool "SYV682C Power Mux for USB PD (subset of SYV682X)"
-	depends on PLATFORM_EC_USBC_PPC_SYV682X
-	help
-	  The C version of this chip won't block I2C accessing to the CONTROL4
-	  rer (to on/off Vconn) when smart discahrge is enabled. This allows us
-	  to re-enable the smart discharge on boards using SYV682C.
-
-config PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
-	bool "SYV682X does not pass through CC"
-	help
-	  Enable this if a SYV682X does not pass through CC.
-	  There is a 3.6V limit on the HOST_CC signals, so the TCPC
-	  should not source 5V VCONN. This config determines if
-	  sourcing VCONN should be enabled by default.
-
-config PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE
-	bool "Enable smart discharge on the SYV682X PPC"
-	help
-	  Enable the smart discharge feature on VBUS provided by the SYV682x
-	  PPC.  This should be enabled for revision C and above of the SYV682X.
-	  Earlier revisions of the chip block I2C transactions during smart
-	  discharge, causing USB PD compliance issues.
-
-config PLATFORM_EC_USBC_PPC_DEDICATED_INT
-	bool "Power Power Controller has a dedicated interrupt pin"
-	help
-	  Enable this if the Power Power Controller (PPC) has level interrupts
-	  (as opposed to edge) and a dedicated interrupt pin to check the
-	  current state.
-
-	  If this is enabled the USB Power Delivery (PD) stack will call
-	  ppc_get_alert_status() to find out he interrupt status for a port.
-	  This function should be provided by the board code.
-
-config PLATFORM_EC_USB_PD_TCPC_LOW_POWER
-	bool "Allow Type-C Port Controller to enter low-power mode"
-	default y
-	help
-	  Allows entry to a low power mode when the USB port is idle.
-	  When enabled, an enter_low_power_mode member is present in tcpm_drv
-	  and should be set to a function that selects that mode, such as
-	  tcpci_enter_low_power_mode() for TCPCI-compatible TCPCs.
-
-config PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
-	int "Debounce delay when exiting low-power mode (uS)"
-	depends on PLATFORM_EC_USB_PD_TCPC_LOW_POWER
-	default 25000
-	help
-	  Some TCPCs need additional time following a VBUS change to internally
-	  debounce the CC line status and update the CC_STATUS register. This
-	  is the delay in microseconds to allow before checking the CC line
-	  status in the EC.
-
-config PLATFORM_EC_USB_PD_TCPC_VCONN
-	bool "If VCONN is enabled, the TCPC will provide VCONN"
-	default y if !PLATFORM_EC_USBC_PPC_SYV682X
-	default y if PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	default y if PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
-	help
-	  Source USB Type-C connector voltage (VCONN) from the Type-C Port
-	  Controller (TCPC), and also the Power Path Controller (PPC) if
-	  present. Some TCPC/PPC can't handle 5V on its host-side CC pins, so
-          disable this config in those cases.
-
-choice "Type-C Port Manager (TCPM)"
-	prompt "Choose a Type-C Port Manager (TCPM) to manage TCPC"
-
-config PLATFORM_EC_USB_PD_TCPM_TCPCI
-	bool "Use TCPCI"
-	help
-	  Enable a TCPC compatible with the Type-C Port Controller Interface
-	  (TCPCI) Specification. This driver supports both Rev1 v1.2 and Rev2
-	  v1.0 of the TCPCI specification. Select this driver directly only
-	  if your specific TCPC chip is not listed as a separate config option.
-
-	  Note: most of the TCPC will depend on PLATFORM_EC_USB_PD_TCPM_TCPCI.
-
-# TODO: Add other choices:
-#  CONFIG_USB_PD_TCPM_STUB
-#  CONFIG_USB_PD_TCPM_FUSB302
-#  CONFIG_USB_PD_TCPM_ANX3429
-#  CONFIG_USB_PD_TCPM_ANX740X
-#  CONFIG_USB_PD_TCPM_ANX741X
-#  CONFIG_USB_PD_TCPM_ANX7447
-#  CONFIG_USB_PD_TCPM_ANX7688
-#  CONFIG_USB_PD_TCPM_NCT38XX
-#  CONFIG_USB_PD_TCPM_MT6370
-#  CONFIG_USB_PD_TCPM_RAA489000
-#  CONFIG_USB_PD_TCPM_FUSB307
-#  CONFIG_USB_PD_TCPM_STM32GX
-#  CONFIG_USB_PD_TCPM_CCGXXF
-
-endchoice  # Type-C Port Manager (TCPM)
-
-menuconfig PLATFORM_EC_USB_MUX
-	bool "USB muxes"
-	default y
-	help
-	  Enables support for USB muxes. These allow multiplexing
-
-if PLATFORM_EC_USB_MUX
-
-config PLATFORM_EC_USB_MUX_IT5205
-	bool "ITE IT5205 USB Type-C 3:2 Alternative mode passive mux"
-	help
-	  This is a USB Type-C 3:2 Alternative mode mux, supporting USB 3.1
-	  Gen 2 10Gbps as well as DisplayPort (DP1.4) at 8Gbps. It provides a
-	  cross-point mux for low-speed Side-Band-Use (SBU) pins. The mux can
-	  be controlled via I2C.
-
-config PLATFORM_EC_USB_MUX_PS8743
-	bool "Parade PS8743 USB-C Host Switch with redriver"
-	help
-	  This is a Parade USB 3.1 Gen 1 / DisplayPort (DP) Alt Mode
-	  High-Bit-Rate 2 (HBR2) redriver. It provides control of switching
-	  modes through either GPIO or I2C.
-
-endif
-
-config PLATFORM_EC_USBC_SS_MUX
-	bool "SuperSpeed mux"
-	default y
-	help
-	  Enable this to support the USB Type-C SuperSpeed Mux. If enabled,
-	  the USB stack will call usb_mux_set() to change the mux settings.
-	  The board must provide a driver in usb_muxes[] for each port so
-	  that this can work.
-
-if PLATFORM_EC_USBC_SS_MUX
-
-config PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
-	bool "USB mux runtime config"
-	default y
-	help
-	  Allows the configuration of the USB mux to be set up at runtime. This
-	  makes the usb_muxes[] array writable, i.e. not const. It should be
-	  declared as such in the board config.
-
-	  This is useful when the board has runtime information that changes
-	  the configuration, such as Chromium OS Board Info (CBI set in the
-	  factory. Without this, multiple EC images would need to be installed
-	  depending on the board.
-
-config PLATFORM_EC_USBC_SS_MUX_DFP_ONLY
-	bool "Use SuperSpeed mux only when DFP"
-        help
-	  Only configure the USB Type-C SuperSpeed Mux when a port is a
-	  Downstream Facing Port (DFP). This is needed for chipsets which
-	  don't support being an Upstream Facing Port UFP).
-
-config PLATFORM_EC_USB_MUX_VIRTUAL
-	bool "USB Mux is virtual"
-	depends on PLATFORM_EC_USBC_SS_MUX
-	help
-	  Enable this if a virtual USB mux is supported on the EC, which is
-	  actually handled by the AP. In this case the AP gets an interrupt
-	  and is is informed when status changes, via the
-	  EC_CMD_USB_PD_MUX_INFO host command.
-
-config PLATFORM_EC_USBC_RETIMER_FW_UPDATE
-	bool "Support firmware update of USB Type-C retimers"
-	default y
-	depends on PLATFORM_EC_USBC_SS_MUX
-	help
-	   Enable this to support USB Type-C retimer firmware update. Each
-	   Type-C retimer indicates its capability of supporting firmware update
-	   independently in its usb_mux_driver.
-
-	   During AP boot-up, the AP scans each PD port for retimers but only
-	   if there are no Type-C devices attached to the port. The firmware
-	   update can only be performed on retimers which show up in the AP
-	   thunderbolt device entries.
-
-endif  # PLATFORM_EC_USBC_SS_MUX
-
-config PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
-	bool "Console command: ppc_dump"
-	depends on PLATFORM_EC_USBC_PPC
-	default y
-	help
-	  Allows dumping of the Power Path Controller (PPC) state, which is
-	  basically a list of registers and their values. The actual dump
-	  function is driver-specific (the reg_dump member of ppc_drv). By
-	  reference to the datasheet for the part this can help you figure out
-	  what is going on.
-
-if PLATFORM_EC_USB_PD_TCPM_TCPCI
-
-config PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	bool "Use on-chip ITE"
-	help
-	  Use the ITE-series TCPM driver built into the EC chip.
-
-	  This is selected by the ITE USB Type-C drivers. It cannot be set
-	  otherwise, even in prj.conf
-
-config PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-	int "Number of ITE USB PD active ports"
-	depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	default 1
-	help
-	  This sets the number of active USB Power Delivery (USB PD) ports
-	  in use on the ITE microcontroller. The active port usage should
-	  follow the order of ITE TCPC port index.
-
-config PLATFORM_EC_USB_PD_PPC
-	bool "Enable Power Path Control from PD"
-	default n
-	help
-	  Some PD chips have integrated SRC FET and control the SRC/SINK FET
-	  from internal GPIOs. Enable this if the Power Path Control is
-	  controlled by the PD chip without EC GPIOs.
-
-config PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
-	bool "Type-C Port Controller runtime config"
-	default y
-	help
-	  Allows the configuration of the TCPC to be set up at runtime. This
-	  makes the tcpc_config[] array writable, i.e. not const. It should be
-	  declared as such in the board config.
-
-	  This is useful when the board has runtime information that sets
-	  the configuration, such as Chromium OS Board Info (CBI set in the
-	  factory. Without this, multiple EC images would need to be installed
-	  depending on the board.
-
-config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
-	bool "Support multiple PS8xxx devices"
-	help
-	  PS8XXX-series chips are all supported by a single driver. Enable
-	  this If a board with the same EC firmware is expected to support
-	  multiple products here. Then enable the required PS8xxx options
-	  below.
-
-	  In this case the board must provide a function to return the correct
-	  product ID actually used by a particular board:
-
-	     uint16_t board_get_ps8xxx_product_id(int port)
-
-	  Supported return values are:
-
-	     PS8705_PRODUCT_ID
-	     PS8751_PRODUCT_ID
-	     PS8755_PRODUCT_ID
-	     PS8805_PRODUCT_ID
-	     PS8815_PRODUCT_ID
-
-config PLATFORM_EC_USB_PD_TCPM_PS8751
-	bool "Parade PS8751 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	help
-	  The Parade Technologies PS8751 is a USB Type-C Port Controller (TCPC)
-	  for USB Type-C Host and DisplayPort applications. It supports
-	  Power Delivery Rev. 2.0 and the DisplayPort Alt Mode version 1.0a.
-
-config PLATFORM_EC_USB_PD_TCPM_PS8805
-	bool "Parade PS8805 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	help
-	  The Parade Technologies PS8805 is an active retiming/redriving
-	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
-	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
-	  DisplayPort applications. It supports Power Delivery and the
-	  DisplayPort Alt Mode.
-
-if PLATFORM_EC_USB_PD_TCPM_PS8805
-config PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID
-	bool "Parade PS8805 Force Device ID"
-	default y
-	help
-	  Early firmware versions of the PS8805 report an incorrect device ID
-	  value for A3 silicon. Enable this option to check the vendor specific
-	  chip version register and force the correct device ID.
-endif # PLATFORM_EC_USB_PD_TCPM_PS8805
-
-config PLATFORM_EC_USB_PD_TCPM_PS8815
-	bool "Parade PS8815 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	help
-	  The Parade Technologies PS8815 is an active retiming/redriving
-	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
-	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
-	  DisplayPort applications. It supports Power Delivery and the
-	  DisplayPort Alt Mode.
-
-if PLATFORM_EC_USB_PD_TCPM_PS8815
-config PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID
-	bool "Parade PS8815 Force Device ID"
-	default y
-	help
-	  Early firmware versions of the PS8815 report an incorrect device ID
-	  value for A1 silicon. Enable this option to check the vendor specific
-	  chip version register and force the correct device ID.
-endif # PLATFORM_EC_USB_PD_TCPM_PS8815
-
-config PLATFORM_EC_USB_PD_TCPM_RT1715
-	bool "Ricktek RT1715 Type-C Port Controller"
-	help
-	  The RT1715 is a USB Type-C controller, integrating a complete Type-C
-	  Transceiver including the Rp and Rd resistors. It does the USB Type-C
-	  detection including attach and orientation. The RT1715 integrates the
-	  physical layer of the USB BMC power delivery protocol to allow up to
-	  100W of power and role swap. The BMC PD block enables full support
-	  for alternative interfaces of the Type-C specification.
-
-config PLATFORM_EC_USB_PD_TCPM_TUSB422
-	bool "TI TUSB422 Port Control with USB PD"
-	help
-	  This is a a USB PD PHY that enables a USB Type-C port with the
-	  Configuration Channel (CC) logic needed for USB Type-C ecosystems. It
-	  integrates the physical layer of the USB BMC power delivery (PD)
-	  protocol to allow up to 100-W of power and support for alternate mode
-	  interfaces. An external microprocessor, containing USB Type-C Port
-	  Manager (TCPM), communicates with the TUSB422 through an I2C
-	  interface.
-
-config PLATFORM_EC_USB_PD_TCPM_MUX
-	bool "Support optional register 18h steer the high-speed muxes"
-	help
-	  Enable this option if the TCPC port controller supports the optional
-	  register 18h CONFIG_STANDARD_OUTPUT to steer the high-speed muxes.
-
-	  See section 4.4.4 (CONFIGURE STANDARD OUTPUT) of the USB Type-C Port
-	  Controller Interface Specification, Revision 2.0, Version 1.2 for more
-	  information.
-
-config PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP
-	bool "Console command: tcpc_dump"
-	# anx7447 also supports this command, but is not yet enabled
-	default y
-	help
-	  Allows dumping of the Type-C Port Controller (TCPC) state, which is
-	  basically a list of registers and their values. By reference to the
-	  Universal Serial Bus Type-C Port Controller Interface Specification
-	  this can help you figure out what is going on.
-
-endif  # PLATFORM_EC_USB_PD_TCPM_TCPCI
-
-config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
-	bool "Enable IT83XX driver"
-	depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	help
-	  Enable a driver for the ITE IT83XX on-chip UBB Type-C Port Manager.
-	  This supports up to two USB Type-C ports with Dual Role function
-	  (provider and consumer) and Fast Role Swap detection.
-
-config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
-	bool "Enable IT8XXX2 driver"
-	depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	help
-	  Enable a driver for the ITE IT8XXX2 on-chip UBB Type-C Port Manager.
-	  This supports up to two USB Type-C ports with Dual Role function
-	  (provider and consumer) and Fast Role Swap detection.
-
-endif  # PLATFORM_EC_USBC_PPC
-
-config PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS
-	bool "Only support FIXED type PDOs"
-	help
-	  Ignore all non-fixed PDOs received from a src_caps message. Enable
-	  this for boards (like servo_v4) which only support FIXED PDO types.
-
-config PLATFORM_EC_USB_CHARGER
-	bool "Support charging from a USB-C port"
-	default y
-	select HAS_TASK_USB_CHG_P0
-	help
-	  This enables common BC1.2 (Battery-Charging Specification Rev1.2)
-	  charger-detection routines. With this is possible to negotiate a
-	  power contract with an attached battery charger and use this to
-	  charge the device's battery.
-
-if PLATFORM_EC_USB_CHARGER
-
-config PLATFORM_EC_BC12_DETECT_PI3USB9201
-	bool "Enable support for Pericom PI3USB9201"
-	help
-	  This is a Dual-Role USB Charging-Type Detector. It can operate in
-	  host or client mode. It supports Battery Charging Specification, rev
-	  1.2 (BC1.2) with Standard/Charging/Dedicated downstream port
-	  (SDP/CDP/DCP) advertisement when in host mode. In client mode it
-	  starts BC1.2 detection to detect the attached host type. It provides
-	  an I2C interface to report detection results.
-
-config PLATFORM_EC_BC12_DETECT_MT6360
-	bool "MediaTek MT6360P PMIC"
-	help
-	  This PMIC includes a battery charger with an On-The-Go (OTG) output
-	  range of 4.85 to 5.825V. It provides integrated ADCs for system
-	  monitoring. The MT6360 also supports USB Power Delivery 3.0 with
-	  Dual-Role, with host or client mode. It supports alternate mode as
-	  well as VCONN with programmable over-current protection (OCP).
-
-config PLATFORM_EC_MT6360_BC12_GPIO
-	bool "USB-PHY connection is controlled by a GPIO"
-	depends on PLATFORM_EC_BC12_DETECT_MT6360
-	help
-	  If enabled, the MT6360 USB-PHY connection is controlled by
-	  a GPIO: GPIO_BC12_DET_EN. Assert GPIO_BC12_DET_EN to detect a BC1.2
-	  device, and deassert GPIO_BC12_DET_EN to mux the USB-PHY back.
-
-config PLATFORM_EC_BC12_SINGLE_DRIVER
-	bool "Only support a single BC12 driver"
-	default y
-	help
-	  Enable this if the board only needs one BC12 driver. This includes
-	  the case that has multiple chips that use the same driver.
-
-	  If undefined, the board should define a bc12_ports[] array which
-	  associates each port to its bc12 driver:
-
-	     struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	        { .drv = &xxx_drv },
-	        { .drv = &yyy_drv },
-	     };
-
-endif  # PLATFORM_EC_USB_CHARGER
-
-endif  # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.watchdog b/zephyr/Kconfig.watchdog
deleted file mode 100644
index 7d5860ce34..0000000000
--- a/zephyr/Kconfig.watchdog
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_WATCHDOG
-
-config PLATFORM_EC_WATCHDOG_PERIOD_MS
-	int "Watchdog timeout in ms"
-	default 1600
-	help
-	  Set the timeout of the watchdog timer. The watchdog timer reboots
-	  the system if no one reloads the watchdog timer before the timeout.
-
-config PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS
-	int "Leading time of the watchdog warning timer in ms"
-	default 500
-	depends on !WDT_NPCX && !WDT_ITE_IT8XXX2
-	help
-	  Set the leading time of the watchdog warning timer. Chromium EC system
-	  uses an auxiliary timer to handle the system warning event. The
-	  auxiliary timer period (CONFIG_AUX_TIMER_PERIOD_MS) is set to
-	  PLATFORM_EC_WATCHDOG_PERIOD_MS -
-	  PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS.
-
-	  For the NPCX chip, use WDT_NPCX_DELAY_CYCLES instead of this config.
-	  For the ITE chip, use CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS instead
-	  of this config.
-
-endif # PLATFORM_EC_WATCHDOG
diff --git a/zephyr/README.md b/zephyr/README.md
deleted file mode 100644
index fc9f7e7c72..0000000000
--- a/zephyr/README.md
+++ /dev/null
@@ -1,30 +0,0 @@
-# Zephyr EC
-
-[TOC]
-
-## Introduction
-
-Zephyr EC is an effort to create an industry-standard Embedded Controller
-implementation for use primarily on laptops. It is born out of the Chromium OS
-EC.
-
-## Gitlab integration
-
-As an experiment we have a basic gitlab integration. It watches the EC repo and
-kicks of a build when new commits appear. So far it just builds for volteer and
-does not run any tests. For firmware branches, it also builds, but fails.
-
-The gitlab builder works without a chroot and uses the Zephyr toolchain. This
-is intended to ensure that we have a path to upstreaming our code eventually and
-do not rely on Chrome OS-specific tools. It does make use of 'zmake', however.
-
-See the piplines [here](https://gitlab.com/zephyr-ec/ec/-/pipelines).
-
-## News and Breaking Changes
-
-* Support for Zephyr v2.4 has been dropped as of
-  [CL:2715345](https://crrev.com/c/2715345).  If you wish to build for
-  kernel v2.4 now, you must invoke `zmake configure` similar to below:
-
-      $ zmake --zephyr-base ~/trunk/src/third_party/zephyr/main/v2.4 \
-              configure --ignore-unsupported-zephyr-version ...
diff --git a/zephyr/app/CMakeLists.txt b/zephyr/app/CMakeLists.txt
deleted file mode 100644
index dfc45f19f9..0000000000
--- a/zephyr/app/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-add_subdirectory_ifdef(CONFIG_CROS_EC ec)
diff --git a/zephyr/app/Kconfig b/zephyr/app/Kconfig
deleted file mode 100644
index 3cac46afa7..0000000000
--- a/zephyr/app/Kconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-rsource "ec/Kconfig"
diff --git a/zephyr/app/ec/CMakeLists.txt b/zephyr/app/ec/CMakeLists.txt
deleted file mode 100644
index f12067a5b5..0000000000
--- a/zephyr/app/ec/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_include_directories(include)
-zephyr_library_sources(ec_app_main.c)
-if(NOT DEFINED CONFIG_ZTEST)
-    zephyr_library_sources(main_shim.c)
-endif()
diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig
deleted file mode 100644
index 9f4bdd95a1..0000000000
--- a/zephyr/app/ec/Kconfig
+++ /dev/null
@@ -1,137 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig CROS_EC
-	bool "Chromium OS EC app"
-	imply SHELL
-	imply SHELL_MINIMAL
-	imply PRINTK
-	help
-	  Enable the common Chromium OS EC application. This prints a message,
-	  starts the EC tasks and sets up any drivers that are needed.
-
-	  This depends on PLATFORM_EC at present, since without the shimmed
-	  tasks, almost nothing can operate.
-
-if CROS_EC
-
-rsource "soc/Kconfig"
-orsource "chip/$(ARCH)/*/Kconfig.*"
-
-config LTO
-	bool "Link Time Optimization (LTO)"
-	default y if !SOC_POSIX
-	help
-	  Enable the Link Time Optimization (LTO) feature for the toolchain.
-	  LTO expands the scope of optimizations to encompass the whole program,
-	  reducing the image size.
-
-	  At this time, LTO is only enabled for Chromium OS source files and
-	  is not enabled for the Zephyr kernel or drivers due.
-	  https://github.com/zephyrproject-rtos/zephyr/issues/2112
-
-choice CBPRINTF_IMPLEMENTATION
-	default CBPRINTF_NANO
-
-endchoice
-
-choice
-	prompt "Chromium OS EC firmware section"
-
-config CROS_EC_RO
-	bool "This build is will be for the RO copy of the EC"
-	help
-	  This build will be used to produce a copy for the read-only
-	  section of the EC firmware.
-
-config CROS_EC_RW
-	bool "This build is will be for the RW copy of the EC"
-	help
-	  This build will be used to produce a copy for the read-write
-	  section of the EC firmware.
-
-endchoice
-
-config CROS_EC_ACTIVE_COPY
-	string
-	default "RO" if CROS_EC_RO
-	default "RW" if CROS_EC_RW
-	help
-	  When the active copy name is output to a console, this
-	  string will be displayed.
-
-config CROS_EC_HOOK_TICK_INTERVAL
-	int "The interval time for the HOOK_TICK"
-	default 250000
-	help
-	  Specificies the interval time for the HOOK_TICK, specified in
-	  microseconds. Modules register with HOOK_TICK to be called
-	  periodically by the HOOKS task. The interval must be shorter than
-	  1 second and is set according the EC chipset's sleep requirements.
-
-# When building for the host, we still need values for the various memory
-# sizes, though they aren't actually used, so just set some reasonable-looking
-# values and then ignore them.
-config CROS_EC_RAM_SIZE
-	hex "The total available RAM size."
-	default 0x0000f800 if ARCH_POSIX
-	help
-		This value describes the total available RAM size for the chip.
-
-config CROS_EC_DATA_RAM_SIZE
-	hex "The total available RAM size for data."
-	default 0x00010000 if ARCH_POSIX
-	help
-		This value describes the total available RAM size for data on the chip.
-
-config CROS_EC_RAM_BASE
-	hex "Base address of RAM for the chip."
-	default 0x200c0000 if ARCH_POSIX
-	help
-		Base address of RAM for the chip.
-
-config CROS_EC_PROGRAM_MEMORY_BASE
-	hex "The base address of the program memory region."
-	default 0x10090000 if ARCH_POSIX
-	help
-		This will be used (among other things) to calculate the current PC's
-		offset within the program memory.
-
-config CROS_EC_RO_MEM_OFF
-	hex "The RO region's offset."
-	default 0x0 if ARCH_POSIX
-	help
-		This will be used to determine if the current PC is in the RO section.
-
-config CROS_EC_RO_SIZE
-	hex "The size of the RO region."
-	default 0xb000 if ARCH_POSIX
-	help
-		This will be used (along with SYSTEM_RO_MEM_OFF) to determine if the
-		current PC is in the RO section.
-
-config CROS_EC_RW_MEM_OFF
-	hex "The RW region's offset."
-	default 0xb000 if ARCH_POSIX
-	help
-		This will be used to determine if the current PC is in the RW section.
-
-config CROS_EC_RW_SIZE
-	hex "The size of the RW region."
-	default 0x75000 if ARCH_POSIX
-	help
-		This will be used (along with SYSTEM_RW_MEM_OFF) to determine if the
-		current PC is in the RW section.
-
-# By default, a unit test doesn't need shimmed tasks.
-config SHIMMED_TASKS
-	bool "Add support for shimming in platform/ec tasks as Zephyr threads"
-	default n if ARCH_POSIX
-	help
-	  When this option is enabled, a shimmed_tasks.h header with the
-	  CROS_EC_TASK_LIST defined needs to be included for the project to
-	  build. The CROS_EC_TASK_LIST defines a list of CROS_EC_TASK that
-	  should be shimmed in.
-
-endif # CROS_EC
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
deleted file mode 100644
index 2da9252775..0000000000
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
+++ /dev/null
@@ -1,53 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-#
-# This file defines the default config values shared by all NPCX chipsets
-#
-
-if SOC_FAMILY_NPCX
-
-# Enable NPCX firmware header generator
-config NPCX_HEADER
-	default y
-
-choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
-	default NPCX_HEADER_SPI_MAX_CLOCK_50
-endchoice
-
-choice NPCX_HEADER_SPI_READ_MODE_CHOICE
-	default NPCX_HEADER_SPI_READ_MODE_DUAL
-endchoice
-
-choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
-	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
-endchoice
-
-# ADC
-# The resolution and oversamplig values are fixed by the NPCX ADC driver
-config PLATFORM_EC_ADC_RESOLUTION
-	default 10
-
-config PLATFORM_EC_ADC_OVERSAMPLING
-	default 0
-
-# Set the system clock to 15MHz.
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 15000000
-
-if WATCHDOG
-
-# Set the delay time for printing panic data.
-# 1 cycle is about 32ms. 500ms is about 16 cycles.
-config WDT_NPCX_DELAY_CYCLES
-	default 16
-
-endif # WATCHDOG
-
-# The maximum supported time the NPCX can spend in deep-sleep with instant
-# wake is 200 ms, so the hook tick interval is set to match.
-config CROS_EC_HOOK_TICK_INTERVAL
-	default 200000
-
-endif # SOC_FAMILY_NPCX
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
deleted file mode 100644
index 3c59d5405e..0000000000
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
+++ /dev/null
@@ -1,53 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-#
-# This file defines the correct defaults when using the NPCX7 series chipset
-#
-
-if SOC_SERIES_NPCX7
-
-#
-# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM
-# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM
-# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM
-#
-
-# Code RAM base for NPCX7 series
-config CROS_EC_PROGRAM_MEMORY_BASE
-	default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
-	default 0x10070000 if SOC_NPCX7M7FC
-
-config CROS_EC_RAM_BASE
-	default 0x200c0000
-
-config CROS_EC_DATA_RAM_SIZE
-	default 0x00010000
-
-config CROS_EC_RAM_SIZE
-	default 0x0000f800
-
-config FLASH_SIZE
-	default 1024 if SOC_NPCX7M6FB
-	default 512  if SOC_NPCX7M6FC || SOC_NPCX7M7FC
-
-config CROS_EC_RO_MEM_OFF
-	default 0x0
-
-# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB)
-# NPCX797FC:           Image size limited by 1/2 Flash size (256 KiB)
-config CROS_EC_RO_SIZE
-	default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
-	default 0x40000 if SOC_NPCX7M7FC
-
-# RW firmware in program memory - Identical to RO, only one image loaded at a
-# time.
-config CROS_EC_RW_MEM_OFF
-	default 0x0
-
-config CROS_EC_RW_SIZE
-	default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC
-	default 0x40000 if SOC_NPCX7M7FC
-
-endif # SOC_SERIES_NPCX7
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
deleted file mode 100644
index 5fd1fbd308..0000000000
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-#
-# This file defines the correct defaults when using the NPCX9 series chipset
-#
-
-if SOC_SERIES_NPCX9
-
-#
-# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM
-# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM
-#
-
-# Code RAM base for NPCX9 series
-config CROS_EC_PROGRAM_MEMORY_BASE
-	default 0x10080000 if SOC_NPCX9M3F
-	default 0x10090000 if SOC_NPCX9M6F
-
-config CROS_EC_RAM_BASE
-	default 0x200c0000
-
-config CROS_EC_DATA_RAM_SIZE
-	default 0x0000f800
-
-config CROS_EC_RAM_SIZE
-	default 0x0000f800
-
-config FLASH_SIZE
-	default 512
-
-config CROS_EC_RO_MEM_OFF
-	default 0x0
-
-# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and
-#           code RAM size (256 KiB)
-# NPCX996F: Image size limited by code RAM size (192 KiB)
-
-config CROS_EC_RO_SIZE
-	default 0x40000 if SOC_NPCX9M3F
-	default 0x30000 if SOC_NPCX9M6F
-
-config CROS_EC_RW_MEM_OFF
-	default 0x0
-
-config CROS_EC_RW_SIZE
-	default 0x40000 if SOC_NPCX9M3F
-	default 0x30000 if SOC_NPCX9M6F
-
-endif # SOC_SERIES_NPCX9
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
deleted file mode 100644
index dab9e6b8b2..0000000000
--- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
+++ /dev/null
@@ -1,41 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if SOC_FAMILY_RISCV_ITE
-
-# Code RAM base for IT8XXX2
-config CROS_EC_PROGRAM_MEMORY_BASE
-	default 0x80000000
-
-# The total RAM size of IT8xxx2 is 60 KB.
-# The first 4KB block be always reserved for ram code functions,
-# so the total available RAM size will be 56KB.
-config CROS_EC_RAM_BASE
-	default 0x80101000
-
-config CROS_EC_DATA_RAM_SIZE
-	default 0x0000e000
-
-config CROS_EC_RAM_SIZE
-	default 0x0000e000
-
-# The 512KB flash space layout are as the below:
-# - RO image starts at the beginning of flash.
-# - RW image starts at the second half of flash.
-config CROS_EC_RO_MEM_OFF
-	default 0x0
-
-config CROS_EC_RO_SIZE
-	default 0x40000
-
-config CROS_EC_RW_MEM_OFF
-	default 0x40000
-
-config CROS_EC_RW_SIZE
-	default 0x40000
-
-config FLASH_LOAD_OFFSET
-	default CROS_EC_RW_MEM_OFF if CROS_EC_RW
-
-endif # SOC_FAMILY_RISCV_ITE
diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c
deleted file mode 100644
index 7cc5b170f1..0000000000
--- a/zephyr/app/ec/ec_app_main.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <sys/printk.h>
-#include <shell/shell_uart.h>
-#include <zephyr.h>
-
-#include "button.h"
-#include "chipset.h"
-#include "ec_tasks.h"
-#include "hooks.h"
-#include "keyboard_scan.h"
-#include "lpc.h"
-#include "system.h"
-#include "vboot.h"
-#include "watchdog.h"
-#include "zephyr_espi_shim.h"
-#include "ec_app_main.h"
-
-/* For testing purposes this is not named main. See main_shim.c for the real
- * main() function.
- */
-void ec_app_main(void)
-{
-	system_common_pre_init();
-
-	/*
-	 * Initialize reset logs. This needs to be done before any updates of
-	 * reset logs because we need to verify if the values remain the same
-	 * after every EC reset.
-	 */
-	if (IS_ENABLED(CONFIG_CMD_AP_RESET_LOG)) {
-		init_reset_log();
-	}
-
-	system_print_banner();
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG)) {
-		watchdog_init();
-	}
-
-	/*
-	 * Keyboard scan init/Button init can set recovery events to
-	 * indicate to host entry into recovery mode. Before this is
-	 * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized
-	 * correctly.
-	 */
-	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
-		lpc_init_mask();
-	}
-
-	if (IS_ENABLED(HAS_TASK_KEYSCAN)) {
-		keyboard_scan_init();
-	}
-
-	if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON) ||
-	    IS_ENABLED(CONFIG_VOLUME_BUTTONS)) {
-		button_init();
-	}
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_ESPI)) {
-		if (zephyr_shim_setup_espi() < 0) {
-			printk("Failed to init eSPI!\n");
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_VBOOT_EFS2)) {
-		/*
-		 * For RO, it behaves as follows:
-		 *   In recovery, it enables PD communication and returns.
-		 *   In normal boot, it verifies and jumps to RW.
-		 * For RW, it returns immediately.
-		 */
-		vboot_main();
-	}
-
-	/*
-	 * Hooks run from the system workqueue and must be the lowest priority
-	 * thread. By default, the system workqueue is run at the lowest
-	 * cooperative thread priority, blocking all preemptive threads until
-	 * the deferred work is completed.
-	 */
-	k_thread_priority_set(&k_sys_work_q.thread, LOWEST_THREAD_PRIORITY);
-
-	/* Call init hooks before main tasks start */
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOOKS)) {
-		hook_notify(HOOK_INIT);
-	}
-
-
-	/*
-	 * Increase priority of shell thread.
-	 * This is temporary code that'll be removed
-	 * after the feature outlined in bug b/191795553
-	 * is implemented.
-	 */
-	{
-		static const struct shell *shell;
-
-		shell = shell_backend_uart_get_ptr();
-		k_thread_priority_set(shell->ctx->tid,
-				K_HIGHEST_APPLICATION_THREAD_PRIO);
-	}
-
-	/*
-	 * Print the init time.  Not completely accurate because it can't take
-	 * into account the time before timer_init(), but it'll at least catch
-	 * the majority of the time.
-	 */
-	cprints(CC_SYSTEM, "Inits done");
-
-	/* Start the EC tasks after performing all main initialization */
-	if (IS_ENABLED(CONFIG_SHIMMED_TASKS)) {
-		start_ec_tasks();
-	}
-}
diff --git a/zephyr/app/ec/include/ec_app_main.h b/zephyr/app/ec/include/ec_app_main.h
deleted file mode 100644
index a5043be84a..0000000000
--- a/zephyr/app/ec/include/ec_app_main.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-void ec_app_main(void);
diff --git a/zephyr/app/ec/main_shim.c b/zephyr/app/ec/main_shim.c
deleted file mode 100644
index 35f45e0286..0000000000
--- a/zephyr/app/ec/main_shim.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include "ec_app_main.h"
-
-/** A stub main to call the real ec app main function. LCOV_EXCL_START */
-void main(void)
-{
-	ec_app_main();
-
-#ifdef CONFIG_THREAD_MONITOR
-	/*
-	 * Avoid returning so that the main stack is displayed by the
-	 * "kernel stacks" shell command.
-	 */
-	k_sleep(K_FOREVER);
-#endif
-}
-/* LCOV_EXCL_STOP */
diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig
deleted file mode 100644
index d7befb39b7..0000000000
--- a/zephyr/app/ec/soc/Kconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-menuconfig AP
-	bool "Enable AP SoC support code"
-	default y
-	help
-	  This device has an application processor (AP) on-board and
-	  support code should be enabled.
-
-if AP
-
-choice
-	prompt "SoC chipset generation"
-
-config AP_X86_INTEL_CML
-	bool "AP is CML chipset"
-	select AP_X86_INTEL
-	help
-	  The application processor is Intel Comet Lake (CML) chipset.
-
-config AP_X86_INTEL_TGL
-	bool "AP is TGL chipset"
-	select AP_X86_INTEL
-	help
-	  The application processor is Intel Tiger Lake (TGL) chipset.
-
-config AP_X86_INTEL_ADL
-	bool "AP is ADL chipset"
-	select AP_X86_INTEL
-	help
-	  The application processor is Intel Alder Lake (ADL) chipset.
-
-config AP_X86_AMD
-	bool "AP is an AMD chipset"
-	select AP_x86
-	help
-	  The application processor is a product of AMD.
-
-config AP_ARM_MTK_MT8192
-	bool "MediaTek MT8192"
-	select AP_AARCH64
-	help
-	  The application processor is a MediaTek MT8192 processor.
-
-config AP_ARM_QUALCOMM_SC7180
-	bool "Qualcomm Snapdragon SC7180"
-	select AP_AARCH64
-	help
-	  The application processor is a Qualcomm Snapdragon SC7180
-	  ARMv8 processor.
-
-config AP_ARM_QUALCOMM_SC7280
-	bool "Qualcomm Snapdragon SC7280"
-	select AP_AARCH64
-	help
-	  The application processor is a Qualcomm Snapdragon SC7280
-	  ARMv8 processor.
-
-endchoice
-
-# Invisible meta-symbols generated by the selected chipset.
-config AP_X86_INTEL
-	bool
-	select AP_X86
-	help
-	  The application processor (AP) is an Intel SoC.
-
-config AP_X86
-	bool
-	help
-	  The application processor (AP) is X86-like.
-
-config AP_AARCH64
-	bool
-	select AP_ARM
-	help
-	  The application processor (AP) is 64-bit ARMv8 architecture.
-
-config AP_ARM
-	bool
-	help
-	  The application processor (AP) is ARM-like.
-
-endif # AP
diff --git a/zephyr/boards/arm/brya/Kconfig.board b/zephyr/boards/arm/brya/Kconfig.board
deleted file mode 100644
index 8add483941..0000000000
--- a/zephyr/boards/arm/brya/Kconfig.board
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# "BOARD" below refers to a Zephyr board, which does not have a 1:1
-# mapping with the Chrome OS concept of a board.  By Zephyr's
-# conventions, we'll still call it "BOARD_*" to make this more
-# applicable to be upstreamed, even though this code is shared by all
-# projects using Brya baseboard.
-config BOARD_BRYA
-	bool "Google Brya Baseboard"
-	depends on SOC_NPCX9M3F
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/brya/Kconfig.defconfig b/zephyr/boards/arm/brya/Kconfig.defconfig
deleted file mode 100644
index e4de179311..0000000000
--- a/zephyr/boards/arm/brya/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_BRYA
-
-config BOARD
-	default "brya"
-
-endif # BOARD_BRYA
diff --git a/zephyr/boards/arm/brya/board.cmake b/zephyr/boards/arm/brya/board.cmake
deleted file mode 100644
index 67ade59f57..0000000000
--- a/zephyr/boards/arm/brya/board.cmake
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
-
diff --git a/zephyr/boards/arm/brya/brya.dts b/zephyr/boards/arm/brya/brya.dts
deleted file mode 100644
index 4ba8704cd2..0000000000
--- a/zephyr/boards/arm/brya/brya.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx9.dtsi>
-#include <dt-bindings/gpio_defines.h>
-#include <nuvoton/npcx9m3f.dtsi>
-
-/ {
-	model = "Google Brya Baseboard";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-		i2c_sensor: sensor {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		tcpc0_2 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_TCPC";
-			label = "TCPC0,2";
-		};
-		tcpc1 {
-			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
-			label = "TCPC1";
-		};
-		ppc0_2 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_PPC";
-			label = "PPC0,2";
-		};
-		ppc1 {
-			i2c-port = <&i2c6_1>;
-			enum-name = "I2C_PORT_USB_C1_PPC";
-			label = "PPC1";
-		};
-		retimer0_2 {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_MUX";
-			label = "RETIMER0,2";
-		};
-		battery {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		charger {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "EEPROM";
-		};
-	};
-
-	named-pwms {
-		compatible = "named-pwms";
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c4_1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl4 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c6_1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl6 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     &alt9_no_kso13_sl
-		     &alt9_no_kso14_sl
-		     >;
-};
diff --git a/zephyr/boards/arm/brya/brya_defconfig b/zephyr/boards/arm/brya/brya_defconfig
deleted file mode 100644
index e8c412a592..0000000000
--- a/zephyr/boards/arm/brya/brya_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX9=y
-
-# Platform Configuration
-CONFIG_SOC_NPCX9M3F=y
-CONFIG_BOARD_BRYA=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board b/zephyr/boards/arm/herobrine_npcx9/Kconfig.board
deleted file mode 100644
index d9e7faf3af..0000000000
--- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# "BOARD" below refers to a Zephyr board, which does not have a 1:1
-# mapping with the Chrome OS concept of a board.  By Zephyr's
-# conventions, we'll still call it "BOARD_*" to make this more
-# applicable to be upstreamed, even though this code is shared by all
-# projects using Herobrine-NPCX9 baseboard.
-config BOARD_HEROBRINE_NPCX9
-	bool "Google Herobrine-NPCX9 Baseboard"
-	depends on SOC_NPCX9M3F
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig b/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig
deleted file mode 100644
index 65f3225d91..0000000000
--- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_HEROBRINE_NPCX9
-
-config BOARD
-	default "herobrine_npcx9"
-
-endif # BOARD_HEROBRINE_NPCX9
diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts
deleted file mode 100644
index 34884a8275..0000000000
--- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx9.dtsi>
-#include <dt-bindings/adc/adc.h>
-#include <dt-bindings/gpio_defines.h>
-#include <dt-bindings/wake_mask_event_defines.h>
-#include <nuvoton/npcx9m3f.dtsi>
-
-/ {
-	model = "Google Herobrine-NPCX9 Baseboard";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		cros,rtc = &pcf85063a;
-	};
-
-	ec-console {
-		compatible = "ec-console";
-
-		disabled = "hostcmd";
-	};
-
-	ec-mkbp-host-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(HOST_EVENT_LID_OPEN | \
-				HOST_EVENT_POWER_BUTTON | \
-				HOST_EVENT_AC_CONNECTED | \
-				HOST_EVENT_AC_DISCONNECTED | \
-				HOST_EVENT_HANG_DETECT | \
-				HOST_EVENT_RTC | \
-				HOST_EVENT_MODE_CHANGE | \
-				HOST_EVENT_DEVICE)>;
-	};
-
-	ec-mkbp-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
-				MKBP_EVENT_HOST_EVENT | \
-				MKBP_EVENT_SENSOR_FIFO)>;
-	};
-
-	named-pwms {
-		compatible = "named-pwms";
-
-		kblight {
-			pwms = <&pwm3 0 0>;
-			label = "KBLIGHT";
-			frequency = <10000>;
-		};
-		displight {
-			pwms = <&pwm5 0 0>;
-			label = "DISPLIGHT";
-			frequency = <4800>;
-		};
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		vbus {
-			label = "ADC_VBUS";
-			enum-name = "ADC_VBUS";
-			channel = <1>;
-			/* Measure VBUS through a 1/10 voltage divider */
-			mul = <10>;
-		};
-		amon_bmon {
-			label = "ADC_AMON_BMON";
-			enum-name = "ADC_AMON_BMON";
-			channel = <2>;
-			/*
-			 * Adapter current output or battery charging/
-			 * discharging current (uV) 18x amplification on
-			 * charger side.
-			 */
-			mul = <1000>;
-			div = <18>;
-		};
-		psys {
-			label = "ADC_PSYS";
-			enum-name = "ADC_PSYS";
-			channel = <3>;
-			/*
-			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
-			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
-			 */
-			mul = <124000>;
-		};
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
-};
-
-/* Keyboard backlight */
-&pwm3 {
-	status = "okay";
-};
-
-/* Display backlight */
-&pwm5 {
-	status = "okay";
-};
-
-&adc0 {
-	status = "okay";
-};
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     >;
-};
diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig
deleted file mode 100644
index 907ae9ed34..0000000000
--- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX9=y
-CONFIG_SOC_NPCX9M3F=y
-
-# Platform Configuration
-CONFIG_BOARD_HEROBRINE_NPCX9=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/kohaku/Kconfig.board b/zephyr/boards/arm/kohaku/Kconfig.board
deleted file mode 100644
index c1a1718847..0000000000
--- a/zephyr/boards/arm/kohaku/Kconfig.board
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config BOARD_KOHAKU
-	bool "Google Kohaku EC"
-	depends on SOC_NPCX7M6FC
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/kohaku/Kconfig.defconfig b/zephyr/boards/arm/kohaku/Kconfig.defconfig
deleted file mode 100644
index 83b97d8ef7..0000000000
--- a/zephyr/boards/arm/kohaku/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_KOHAKU
-
-config BOARD
-	default "kohaku"
-
-endif # BOARD_KOHAKU
diff --git a/zephyr/boards/arm/kohaku/board.cmake b/zephyr/boards/arm/kohaku/board.cmake
deleted file mode 100644
index a204305534..0000000000
--- a/zephyr/boards/arm/kohaku/board.cmake
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/kohaku/kohaku.dts b/zephyr/boards/arm/kohaku/kohaku.dts
deleted file mode 100644
index 00e340faea..0000000000
--- a/zephyr/boards/arm/kohaku/kohaku.dts
+++ /dev/null
@@ -1,418 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx7.dtsi>
-#include <dt-bindings/gpio_defines.h>
-#include <nuvoton/npcx7m6fc.dtsi>
-
-/ {
-	model = "Google Kohaku EC";
-
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-	};
-
-	named-gpios {
-		compatible = "named-gpios";
-
-		lid_open {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-		wp_l {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		power_button_l {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "POWER_BUTTON_L";
-		};
-		acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		slp_s0_l {
-			gpios = <&gpiod 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S0_L";
-			label = "SLP_S0_L";
-		};
-		slp_s3_l {
-			gpios = <&gpioa 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S3_L";
-			label = "SLP_S3_L";
-		};
-		slp_s4_l {
-			gpios = <&gpiod 4 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S4_L";
-			label = "SLP_S4_L";
-		};
-		pg_ec_rsmrst_l {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_RSMRST_L_PGOOD";
-			label = "PG_EC_RSMRST_L";
-		};
-		pg_ec_all_sys_pwrgd {
-			gpios = <&gpiof 4 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
-			label = "PG_EC_ALL_SYS_PWRGD";
-		};
-		pp5000_a_pg_od {
-			gpios = <&gpiod 7 GPIO_INPUT>;
-			enum-name = "GPIO_PP5000_A_PG_OD";
-			label = "PP5000_A_PG_OD";
-		};
-		base_sixaxis_int_l {
-			gpios = <&gpio5 6 GPIO_INPUT>;
-			label = "BASE_SIXAXIS_INT_L";
-		};
-		wfcam_vsync {
-			gpios = <&gpiob 7 GPIO_INPUT>;
-			label = "WFCAM_VSYNC";
-		};
-		tcs3400_int_odl {
-			gpios = <&gpio7 2 GPIO_INPUT>;
-			label = "TCS3400_INT_ODL";
-		};
-		usb_c0_ppc_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			label = "USB_C0_PPC_INT_ODL";
-		};
-		usb_c1_ppc_int_odl {
-			gpios = <&gpioa 2 GPIO_INPUT>;
-			label = "USB_C1_PPC_INT_ODL";
-		};
-		usb_c0_tcpc_int_odl {
-			gpios = <&gpio6 2 GPIO_INPUT>;
-			label = "USB_C0_TCPC_INT_ODL";
-		};
-		usb_c1_tcpc_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			label = "USB_C1_TCPC_INT_ODL";
-		};
-		usb_c0_bc12_int_odl {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-			label = "USB_C0_BC12_INT_ODL";
-		};
-		usb_c1_bc12_int_odl {
-			gpios = <&gpioe 4 GPIO_INPUT>;
-			label = "USB_C1_BC12_INT_ODL";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpio7 5 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		sys_reset_l {
-			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_SYS_RESET_L";
-			label = "SYS_RESET_L";
-		};
-		entering_rw {
-			gpios = <&gpioe 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "ENTERING_RW";
-		};
-		pch_wake_l {
-			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "PCH_WAKE_L";
-		};
-		pch_pwrbtn_l {
-			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PCH_PWRBTN_L";
-			label = "PCH_PWRBTN_L";
-		};
-		en_pp5000_a {
-			gpios = <&gpioa 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_A";
-			label = "EN_PP5000_A";
-		};
-		en_pp5000 {
-			gpios = <&gpioa 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000";
-		};
-		gpio_edp_bklten_od {
-			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EDP_BKLTEN_OD";
-		};
-		en_a_rails {
-			gpios = <&gpioa 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_A_RAILS";
-			label = "EN_A_RAILS";
-		};
-		ec_pch_rsmrst_l {
-			gpios = <&gpioa 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PCH_RSMRST_L";
-			label = "EC_PCH_RSMRST_L";
-		};
-		ec_prochot_odl {
-			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_CPU_PROCHOT";
-			label = "EC_PROCHOT_ODL";
-		};
-		ec_prochot_in_od {
-			gpios = <&gpio3 4 GPIO_INPUT>;
-			label = "EC_PROCHOT_IN_OD";
-		};
-		ec_pch_sys_pwrok {
-			gpios = <&gpio3 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PCH_SYS_PWROK";
-			label = "EC_PCH_SYS_PWROK";
-		};
-		cpu_c10_gate_l {
-			gpios = <&gpio6 7 GPIO_INPUT>;
-			label = "CPU_C10_GATE_L";
-		};
-		ec_int_l {
-			gpios = <&gpio7 0 GPIO_ODR_HIGH>;
-			label = "EC_INT_L";
-		};
-		ec_rst_odl {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			label = "EC_RST_ODL";
-		};
-		usb_c_oc_odl {
-			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
-			label = "USB_C_OC_ODL";
-		};
-		usb_c0_tcpc_rst_odl {
-			gpios = <&gpio9 7 GPIO_ODR_HIGH>;
-			label = "USB_C0_TCPC_RST_ODL";
-		};
-		usb_c1_tcpc_rst_odl {
-			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
-			label = "USB_C1_TCPC_RST_ODL";
-		};
-		usb_c0_bc12_chg_det_l {
-			gpios = <&gpio6 0 GPIO_INPUT>;
-			label = "USB_C0_BC12_CHG_DET_L";
-		};
-		usb_c1_bc12_chg_det_l {
-			gpios = <&gpio9 6 GPIO_INPUT>;
-			label = "USB_C1_BC12_CHG_DET_L";
-		};
-		usb_c0_bc12_vbus_on {
-			gpios = <&gpio9 4 GPIO_OUT_LOW>;
-			label = "USB_C0_BC12_VBUS_ON";
-		};
-		usb_c1_bc12_vbus_on {
-			gpios = <&gpioc 6 GPIO_OUT_LOW>;
-			label = "USB_C1_BC12_VBUS_ON";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioe 1 GPIO_INPUT>;
-			label = "EC_BATT_PRES_ODL";
-		};
-		led_1_l {
-			gpios = <&gpioc 4 GPIO_OUT_HIGH>;
-			label = "LED_1_L";
-		};
-		led_2_l {
-			gpios = <&gpioc 3 GPIO_OUT_HIGH>;
-			label = "LED_2_L";
-		};
-		led_3_l {
-			gpios = <&gpioc 2 GPIO_OUT_HIGH>;
-			label = "LED_3_L";
-		};
-		ec_kb_bl_en {
-			gpios = <&gpio8 6 GPIO_OUT_LOW>;
-			label = "EC_KB_BL_EN";
-		};
-		edp_bklten_od {
-			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
-			label = "EDP_BKLTEN_OD";
-		};
-		lid_accel_int_l {
-			gpios = <&gpio5 0 GPIO_INPUT>;
-			label = "LID_ACCEL_INT_L";
-		};
-		m2_sd_pln {
-			gpios = <&gpioa 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "M2_SD_PLN";
-		};
-		imvp8_pe {
-			gpios = <&gpioa 7 GPIO_INPUT>;
-			label = "IMVP8_PE";
-		};
-		i2c0_scl {
-			gpios = <&gpiob 5 GPIO_INPUT>;
-			label = "I2C0_SCL";
-		};
-		i2c0_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			label = "I2C0_SDA";
-		};
-		i2c1_scl {
-			gpios = <&gpio9 0 GPIO_INPUT>;
-			label = "I2C1_SCL";
-		};
-		i2c1_sda {
-			gpios = <&gpio8 7 GPIO_INPUT>;
-			label = "I2C1_SDA";
-		};
-		i2c2_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
-			label = "I2C2_SCL";
-		};
-		i2c2_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
-			label = "I2C2_SDA";
-		};
-		i2c3_scl {
-			gpios = <&gpiod 1 GPIO_INPUT>;
-			label = "I2C3_SCL";
-		};
-		i2c3_sda {
-			gpios = <&gpiod 0 GPIO_INPUT>;
-			label = "I2C3_SDA";
-		};
-		i2c5_scl {
-			gpios = <&gpio3 3 GPIO_INPUT>;
-			label = "I2C5_SCL";
-		};
-		i2c5_sda {
-			gpios = <&gpio3 6 GPIO_INPUT>;
-			label = "I2C5_SDA";
-		};
-		i2c7_scl {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			label = "I2C7_SCL";
-		};
-		i2c7_sda {
-			gpios = <&gpiob 2 GPIO_INPUT>;
-			label = "I2C7_SDA";
-		};
-		tp58 {
-			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP58";
-		};
-		tp73 {
-			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP73";
-		};
-		tp18 {
-			gpios = <&gpioc 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP18";
-		};
-		tp54 {
-			gpios = <&gpio4 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP54";
-		};
-		tp56 {
-			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP56";
-		};
-		tp57 {
-			gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP57";
-		};
-		tp55 {
-			gpios = <&gpio7 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP55";
-		};
-		tp59 {
-			gpios = <&gpiob 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "TP59";
-		};
-		kbd_kso2 {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			label = "KBD_KSO2";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <&lvol_iob4 &lvol_iob5 /* I2C_SDA0 & SCL0 */
-		                &lvol_io50>;          /* GPIO50 */
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
diff --git a/zephyr/boards/arm/kohaku/kohaku.yaml b/zephyr/boards/arm/kohaku/kohaku.yaml
deleted file mode 100644
index 48cc85e7df..0000000000
--- a/zephyr/boards/arm/kohaku/kohaku.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2020 Google LLC.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-identifier: kohaku
-name: "Google Kohaku (Samsung Galaxy Chromebook) Embedded Controller"
-type: mcu
-arch: arm
-toolchain:
-  - zephyr
-  - gnuarmemb
-ram: 64
-flash: 512
-testing:
-  ignore_tags:
-    - net
-    - bluetooth
diff --git a/zephyr/boards/arm/kohaku/kohaku_defconfig b/zephyr/boards/arm/kohaku/kohaku_defconfig
deleted file mode 100644
index eccf6da6ab..0000000000
--- a/zephyr/boards/arm/kohaku/kohaku_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX7=y
-CONFIG_SOC_NPCX7M6FC=y
-
-# Platform Configuration
-CONFIG_BOARD_KOHAKU=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/npcx9/Kconfig.board b/zephyr/boards/arm/npcx9/Kconfig.board
deleted file mode 100644
index e4b184d83e..0000000000
--- a/zephyr/boards/arm/npcx9/Kconfig.board
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config BOARD_NPCX9
-	bool "NPCX9 Zephyr Board"
-	depends on SOC_NPCX9M3F
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx9/Kconfig.defconfig b/zephyr/boards/arm/npcx9/Kconfig.defconfig
deleted file mode 100644
index 9b83915f04..0000000000
--- a/zephyr/boards/arm/npcx9/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_NPCX9
-
-config BOARD
-	default "npcx9"
-
-endif # BOARD_TROGDOR
diff --git a/zephyr/boards/arm/npcx9/board.cmake b/zephyr/boards/arm/npcx9/board.cmake
deleted file mode 100644
index a204305534..0000000000
--- a/zephyr/boards/arm/npcx9/board.cmake
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/npcx9/npcx9.dts b/zephyr/boards/arm/npcx9/npcx9.dts
deleted file mode 100644
index ab44d8119e..0000000000
--- a/zephyr/boards/arm/npcx9/npcx9.dts
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx9.dtsi>
-#include <dt-bindings/adc/adc.h>
-#include <dt-bindings/gpio_defines.h>
-#include <dt-bindings/wake_mask_event_defines.h>
-#include <nuvoton/npcx9m3f.dtsi>
-
-/ {
-	model = "NPCX9";
-
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-		i2c_sensor: sensor {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		tcpc0_2 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_TCPC";
-			label = "TCPC0,2";
-		};
-		tcpc1 {
-			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
-			label = "TCPC1";
-		};
-		ppc0_2 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_PPC";
-			label = "PPC0,2";
-		};
-		ppc1 {
-			i2c-port = <&i2c6_1>;
-			enum-name = "I2C_PORT_USB_C1_PPC";
-			label = "PPC1";
-		};
-		retimer0_2 {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_MUX";
-			label = "RETIMER0,2";
-		};
-		battery {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		charger {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "EEPROM";
-		};
-	};
-
-	named-pwms {
-		compatible = "named-pwms";
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c4_1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl4 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c6_1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl6 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     &alt9_no_kso13_sl
-		     &alt9_no_kso14_sl
-		     >;
-};
diff --git a/zephyr/boards/arm/npcx9/npcx9_defconfig b/zephyr/boards/arm/npcx9/npcx9_defconfig
deleted file mode 100644
index d20fd87f3a..0000000000
--- a/zephyr/boards/arm/npcx9/npcx9_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX9=y
-CONFIG_SOC_NPCX9M3F=y
-
-# Platform Configuration
-CONFIG_BOARD_NPCX9=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board
deleted file mode 100644
index 0ac4a80833..0000000000
--- a/zephyr/boards/arm/npcx_evb/Kconfig.board
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Note: this Zephyr board more closely represents the Chrome OS
-# concept of a baseboard.  Zephyr boards and Chrome OS boards do not
-# have a 1:1 mapping.
-config BOARD_NPCX7_EVB
-	bool "NPCX7 Evaluation Board"
-	depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC
-	# Allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
-
-config BOARD_NPCX9_EVB
-	bool "NPCX9 Evaluation Board"
-	depends on SOC_NPCX9M3F || SOC_NPCX9M6F
-	# Allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
deleted file mode 100644
index c0c874ad26..0000000000
--- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config BOARD
-	default "npcx7_evb" if BOARD_NPCX7_EVB
-	default "npcx9_evb" if BOARD_NPCX9_EVB
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
deleted file mode 100644
index c20589d637..0000000000
--- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx7.dtsi>
-
-/*
- * #include <nuvoton/npcx7m6fb.dtsi>
- * #include <nuvoton/npcx7m6fc.dtsi>
- * #include <nuvoton/npcx7m7fc.dtsi>
- */
-#include <nuvoton/npcx7m6fc.dtsi>
-#include "npcx_evb.dtsi"
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
-};
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
deleted file mode 100644
index b2fc879cbc..0000000000
--- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX7=y
-# NPCX7 soc list
-#  CONFIG_SOC_NPCX7M6FB
-#  CONFIG_SOC_NPCX7M6FC
-#  CONFIG_SOC_NPCX7M7FC
-CONFIG_SOC_NPCX7M6FC=y
-
-# Platform Configuration
-CONFIG_BOARD_NPCX7_EVB=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# I2C
-CONFIG_I2C=y
-
-# ADC
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
deleted file mode 100644
index 4ab68cdde1..0000000000
--- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx9.dtsi>
-
-/*
- * #include <nuvoton/npcx9m3f.dtsi>
- * #include <nuvoton/npcx9m6f.dtsi>
- */
-#include <nuvoton/npcx9m6f.dtsi>
-#include "npcx_evb.dtsi"
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
-};
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
deleted file mode 100644
index 9a946584ef..0000000000
--- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX9=y
-# NPCX9 soc list
-#  CONFIG_SOC_NPCX9M3F
-#  CONFIG_SOC_NPCX9M6F
-CONFIG_SOC_NPCX9M6F=y
-
-# Platform Configuration
-CONFIG_BOARD_NPCX9_EVB=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# I2C
-CONFIG_I2C=y
-
-# ADC
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
deleted file mode 100644
index 61a1e79783..0000000000
--- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/gpio_defines.h>
-
-/ {
-	model = "Nuvoton NPCX Evaluation Board";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		cros,rtc = &mtc;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		i2c_evb_0_0 {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_EVB_0";
-			label = "I2C0_0";
-		};
-		i2c_evb_1_0 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_EVB_1";
-			label = "I2C1_0";
-		};
-		i2c_evb_2_0 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_EVB_2";
-			label = "I2C2_0";
-		};
-		i2c_evb_3_0 {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_EVB_3";
-			label = "I2C3_0";
-		};
-		i2c_evb_7_0 {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EVB_7";
-			label = "I2C7_0";
-		};
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_ch_0 {
-			label = "ADC0";
-			enum-name = "ADC_EVB_CH_0";
-			channel = <0>;
-		};
-		adc_ch_1 {
-			label = "ADC1";
-			enum-name = "ADC_EVB_CH_1";
-			channel = <1>;
-		};
-		adc_ch_2 {
-			label = "ADC2";
-			enum-name = "ADC_EVB_CH_2";
-			channel = <2>;
-		};
-		adc_ch_3 {
-			label = "ADC3";
-			enum-name = "ADC_EVB_CH_3";
-			channel = <3>;
-		};
-		adc_ch_4 {
-			label = "ADC4";
-			enum-name = "ADC_EVB_CH_4";
-			channel = <4>;
-		};
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>;
-	};
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
-
-&adc0 {
-	status = "okay";
-};
-
-/* Power switch logic input pads */
-&psl_in1 {
-	flag = <NPCX_PSL_FALLING_EDGE>;
-};
-&psl_in2 {
-	flag = <NPCX_PSL_FALLING_EDGE>;
-};
-&psl_in3 {
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&cros_kb_raw {
-	status = "okay";
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso02_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     >;
-};
diff --git a/zephyr/boards/arm/trogdor/Kconfig.board b/zephyr/boards/arm/trogdor/Kconfig.board
deleted file mode 100644
index 4bfa4e50ac..0000000000
--- a/zephyr/boards/arm/trogdor/Kconfig.board
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# "BOARD" below refers to a Zephyr board, which does not have a 1:1
-# mapping with the Chrome OS concept of a board.  By Zephyr's
-# conventions, we'll still call it "BOARD_*" to make this more
-# applicable to be upstreamed, even though this code is shared by all
-# projects using Trogdor baseboard.
-config BOARD_TROGDOR
-	bool "Google Trogdor Baseboard"
-	depends on SOC_NPCX7M7FC
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/trogdor/Kconfig.defconfig b/zephyr/boards/arm/trogdor/Kconfig.defconfig
deleted file mode 100644
index bfd2e43bbf..0000000000
--- a/zephyr/boards/arm/trogdor/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_TROGDOR
-
-config BOARD
-	default "trogdor"
-
-endif # BOARD_TROGDOR
diff --git a/zephyr/boards/arm/trogdor/board.cmake b/zephyr/boards/arm/trogdor/board.cmake
deleted file mode 100644
index a204305534..0000000000
--- a/zephyr/boards/arm/trogdor/board.cmake
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/trogdor/trogdor.dts b/zephyr/boards/arm/trogdor/trogdor.dts
deleted file mode 100644
index 4bc7f7efc1..0000000000
--- a/zephyr/boards/arm/trogdor/trogdor.dts
+++ /dev/null
@@ -1,272 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx7.dtsi>
-#include <dt-bindings/adc/adc.h>
-#include <dt-bindings/gpio_defines.h>
-#include <dt-bindings/wake_mask_event_defines.h>
-#include <nuvoton/npcx7m7fc.dtsi>
-
-/ {
-	model = "Google Trogdor Baseboard";
-
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		cros,rtc = &mtc;
-	};
-
-	ec-console {
-		compatible = "ec-console";
-
-		disabled = "hostcmd";
-	};
-
-	ec-mkbp-host-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(
-			HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) |
-			HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) |
-			HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) |
-			HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) |
-			HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) |
-			HOST_EVENT_MASK(HOST_EVENT_RTC) |
-			HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE) |
-			HOST_EVENT_MASK(HOST_EVENT_DEVICE))>;
-	};
-
-	ec-mkbp-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
-				MKBP_EVENT_HOST_EVENT |
-				MKBP_EVENT_SENSOR_FIFO)>;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		power {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_POWER";
-			label = "POWER";
-		};
-		battery {
-			i2c-port = <&i2c0_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		virtual {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_VIRTUAL";
-			label = "VIRTUAL";
-		};
-		charger {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "CHARGER";
-		};
-		tcpc0 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_TCPC0";
-			label = "TCPC0";
-		};
-		tcpc1 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_TCPC1";
-			label = "TCPC1";
-		};
-		eeprom {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		accel {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL";
-		};
-	};
-
-	named-pwms {
-		compatible = "named-pwms";
-
-		kblight {
-			pwms = <&pwm3 0 0>;
-			label = "KBLIGHT";
-			frequency = <10000>;
-		};
-		displight {
-			pwms = <&pwm5 0 0>;
-			label = "DISPLIGHT";
-			frequency = <4800>;
-		};
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		vbus {
-			label = "ADC_VBUS";
-			enum-name = "ADC_VBUS";
-			channel = <1>;
-			/* Measure VBUS through a 1/10 voltage divider */
-			mul = <10>;
-		};
-		amon_bmon {
-			label = "ADC_AMON_BMON";
-			enum-name = "ADC_AMON_BMON";
-			channel = <2>;
-			/*
-			 * Adapter current output or battery charging/
-			 * discharging current (uV) 18x amplification on
-			 * charger side.
-			 */
-			mul = <1000>;
-			div = <18>;
-		};
-		psys {
-			label = "ADC_PSYS";
-			enum-name = "ADC_PSYS";
-			channel = <3>;
-			/*
-			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
-			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
-			 */
-			mul = <124000>;
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-
-		/* I2C_SDA0 & SCL0 */
-		lvol-io-pads = <&lvol_iob4 &lvol_iob5>;
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-
-	isl9238: isl9238@9 {
-		compatible = "intersil,isl9238";
-		reg = <0x09>;
-		label = "ISL9238_CHARGER";
-	};
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	/* Not used as no WLC connected */
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
-
-/* Keyboard backlight */
-&pwm3 {
-	status = "okay";
-};
-
-/* Display backlight */
-&pwm5 {
-	status = "okay";
-};
-
-&adc0 {
-	status = "okay";
-};
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     >;
-};
diff --git a/zephyr/boards/arm/trogdor/trogdor_defconfig b/zephyr/boards/arm/trogdor/trogdor_defconfig
deleted file mode 100644
index 2a61f3dd5c..0000000000
--- a/zephyr/boards/arm/trogdor/trogdor_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX7=y
-CONFIG_SOC_NPCX7M7FC=y
-
-# Platform Configuration
-CONFIG_BOARD_TROGDOR=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/arm/volteer/Kconfig.board b/zephyr/boards/arm/volteer/Kconfig.board
deleted file mode 100644
index 5a0390e16f..0000000000
--- a/zephyr/boards/arm/volteer/Kconfig.board
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Note: this Zephyr board more closely represents the Chrome OS
-# concept of a baseboard.  Zephyr boards and Chrome OS boards do not
-# have a 1:1 mapping.
-config BOARD_VOLTEER
-	bool "Google Volteer Baseboard"
-	depends on SOC_NPCX7M6FC || SOC_NPCX7M7FC
-	# NPCX doesn't actually have enough ram for coverage, but this will
-	# allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/volteer/Kconfig.defconfig b/zephyr/boards/arm/volteer/Kconfig.defconfig
deleted file mode 100644
index 05361962d9..0000000000
--- a/zephyr/boards/arm/volteer/Kconfig.defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-# Google Volteer EC
-
-# Copyright 2020 The Chromium OS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_VOLTEER
-
-config BOARD
-	default "volteer"
-
-endif # BOARD_VOLTEER
diff --git a/zephyr/boards/arm/volteer/board.cmake b/zephyr/boards/arm/volteer/board.cmake
deleted file mode 100644
index e29e12278d..0000000000
--- a/zephyr/boards/arm/volteer/board.cmake
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin)
diff --git a/zephyr/boards/arm/volteer/volteer.dts b/zephyr/boards/arm/volteer/volteer.dts
deleted file mode 100644
index d837f8ab55..0000000000
--- a/zephyr/boards/arm/volteer/volteer.dts
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Copyright (c) 2020 The Chromium OS Authors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx7.dtsi>
-#include <dt-bindings/adc/adc.h>
-#include <dt-bindings/charger/intersil_isl9241.h>
-#include <dt-bindings/gpio_defines.h>
-#include <nuvoton/npcx7m7fc.dtsi>
-#include <cros/thermistor/thermistor.dtsi>
-
-/ {
-	model = "Google Volteer EC";
-
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		cros,rtc = &mtc;
-	};
-
-	ec-console {
-		compatible = "ec-console";
-
-		disabled = "hostcmd";
-	};
-
-	named-batteries {
-		compatible = "named-batteries";
-
-		lgc011 {
-			enum-name = "lgc011";
-		};
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		i2c_sensor: sensor {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		i2c-accel {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL";
-		};
-		usb-c0 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_USB_C0";
-			label = "USB_C0";
-		};
-		usb-c1 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C1";
-			label = "USB_C1";
-		};
-		usb1-mix {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_1_MIX";
-			label = "USB_1_MIX";
-		};
-		power {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_POWER";
-			label = "POWER";
-		};
-		battery {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c7_0>;
-			remote-port = <7>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		charger {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "CHARGER";
-		};
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_charger: charger {
-			label = "ADC_TEMP_SENSOR_CHARGER";
-			enum-name = "ADC_TEMP_SENSOR_CHARGER";
-			channel = <0>;
-		};
-		adc_pp3300_regulator: pp3300_regulator {
-			label = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
-			enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
-			channel = <1>;
-		};
-		adc_ddr_soc: ddr_soc {
-			label = "ADC_TEMP_SENSOR_DDR_SOC";
-			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
-			channel = <8>;
-		};
-		adc_fan: fan {
-			label = "ADC_TEMP_SENSOR_FAN";
-			enum-name = "ADC_TEMP_SENSOR_FAN";
-			channel = <3>;
-		};
-	};
-
-	named-temp-sensors {
-		charger {
-			compatible = "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "TEMP_SENSOR_CHARGER";
-			enum-name = "TEMP_SENSOR_CHARGER";
-			temp_fan_off = <40>;
-			temp_fan_max = <55>;
-			temp_host_high = <75>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_charger>;
-		};
-		pp3300_regulator {
-			compatible = "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "TEMP_SENSOR_PP3300_REGULATOR";
-			enum-name = "TEMP_SENSOR_PP3300_REGULATOR";
-			temp_fan_off = <40>;
-			temp_fan_max = <55>;
-			temp_host_high = <75>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_pp3300_regulator>;
-		};
-		ddr_soc {
-			compatible = "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "TEMP_SENSOR_DDR_SOC";
-			enum-name = "TEMP_SENSOR_DDR_SOC";
-			temp_fan_off = <35>;
-			temp_fan_max = <50>;
-			temp_host_high = <70>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_ddr_soc>;
-		};
-		fan {
-			compatible = "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "TEMP_SENSOR_FAN";
-			enum-name = "TEMP_SENSOR_FAN";
-			temp_fan_off = <35>;
-			temp_fan_max = <50>;
-			temp_host_high = <70>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_fan>;
-		};
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
-	};
-
-	/*
-	 * The CBI Second Source Factory Cache (SSFC) layout definition.
-	 * Specific fields values are defined per board.
-	 */
-	cbi-ssfc {
-		compatible = "named-cbi-ssfc";
-
-		cbi_ssfc_base_sensor: base_sensor {
-			enum-name = "BASE_SENSOR";
-			size = <3>;
-		};
-		cbi_ssfc_lid_sensor: lid_sensor {
-			enum-name = "LID_SENSOR";
-			size = <3>;
-		};
-		cbi_ssfc_lightbar: lightbar {
-			enum-name = "LIGHTBAR";
-			size = <2>;
-		};
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-
-	isl9241: isl9241@9 {
-		compatible = "intersil,isl9241";
-		reg = <0x09>;
-		label = "ISL9241_CHARGER";
-		switching-frequency = <SWITCHING_FREQ_724KHZ>;
-	};
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <&alt7_no_ksi0_sl
-		     &alt7_no_ksi1_sl
-		     &alt7_no_ksi2_sl
-		     &alt7_no_ksi3_sl
-		     &alt7_no_ksi4_sl
-		     &alt7_no_ksi5_sl
-		     &alt7_no_ksi6_sl
-		     &alt7_no_ksi7_sl
-		     &alt8_no_kso00_sl
-		     &alt8_no_kso01_sl
-		     &alt8_no_kso03_sl
-		     &alt8_no_kso04_sl
-		     &alt8_no_kso05_sl
-		     &alt8_no_kso06_sl
-		     &alt8_no_kso07_sl
-		     &alt9_no_kso08_sl
-		     &alt9_no_kso09_sl
-		     &alt9_no_kso10_sl
-		     &alt9_no_kso11_sl
-		     &alt9_no_kso12_sl
-		     &alt9_no_kso13_sl
-		     &alt9_no_kso14_sl
-		     >;
-};
-
-&adc0 {
-	status = "okay";
-};
-
-/* Power switch logic input pads */
-&psl_in1 {
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&psl_in2 {
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&psl_in3 {
-	flag = <NPCX_PSL_FALLING_EDGE>;
-};
-
-&psl_in4 {
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&thermistor_3V3_30K9_47K_4050B {
-	status = "okay";
-};
diff --git a/zephyr/boards/arm/volteer/volteer_defconfig b/zephyr/boards/arm/volteer/volteer_defconfig
deleted file mode 100644
index a3f184dff8..0000000000
--- a/zephyr/boards/arm/volteer/volteer_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_NPCX7=y
-CONFIG_SOC_NPCX7M7FC=y
-
-# Platform Configuration
-CONFIG_BOARD_VOLTEER=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-
-# ADC
-# The resolution and oversamplig values are fixed by the NPCX ADC driver
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# Power Management
-CONFIG_SOC_POWER_MANAGEMENT=y
-CONFIG_PM_POLICY_APP=y
-CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
-CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_NPCX=y
diff --git a/zephyr/boards/riscv/asurada/Kconfig.board b/zephyr/boards/riscv/asurada/Kconfig.board
deleted file mode 100644
index f17a00d2fd..0000000000
--- a/zephyr/boards/riscv/asurada/Kconfig.board
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# "BOARD" below refers to a Zephyr board, which does not have a 1:1
-# mapping with the Chrome OS concept of a board.  By Zephyr's
-# conventions, we'll still call it "BOARD_*" to make this more
-# applicable to be upstreamed, even though this code is shared by all
-# projects using Trogdor baseboard.
-config BOARD_ASURADA
-	bool "Google Asurada Baseboard"
-	depends on SOC_IT8XXX2
-	# Allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/riscv/asurada/Kconfig.defconfig b/zephyr/boards/riscv/asurada/Kconfig.defconfig
deleted file mode 100644
index cc3e4b000c..0000000000
--- a/zephyr/boards/riscv/asurada/Kconfig.defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_ASURADA
-
-config BOARD
-	default "asurada"
-
-# Zephyr internal stack sizes
-
-config IDLE_STACK_SIZE
-	default 256
-
-config ISR_STACK_SIZE
-	default 800
-
-config SHELL_STACK_SIZE
-	default 1048
-
-config SYSTEM_WORKQUEUE_STACK_SIZE
-	default 1024
-
-
-# Chromium EC stack sizes
-
-config TASK_CHARGER_STACK_SIZE
-	default 960
-
-config TASK_CHIPSET_STACK_SIZE
-	default 820
-
-config TASK_HOOKS_STACK_SIZE
-	default 672
-
-config TASK_HOSTCMD_STACK_SIZE
-	default 1024
-
-config TASK_KEYSCAN_STACK_SIZE
-	default 920
-
-config TASK_MOTIONSENSE_STACK_SIZE
-	default 920
-
-config TASK_PD_STACK_SIZE
-	default 1024
-
-config TASK_USB_CHG_STACK_SIZE
-	default 800
-
-
-choice PLATFORM_EC_HOSTCMD_DEBUG_MODE
-	default HCDEBUG_OFF
-endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE
-
-endif # BOARD_ASURADA
diff --git a/zephyr/boards/riscv/asurada/asurada.dts b/zephyr/boards/riscv/asurada/asurada.dts
deleted file mode 100644
index 7b4519c0e1..0000000000
--- a/zephyr/boards/riscv/asurada/asurada.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/ite/it8xxx2.dtsi>
-#include <dt-bindings/adc/adc.h>
-#include <dt-bindings/gpio_defines.h>
-#include <it8xxx2.dtsi>
-#include <dt-bindings/wake_mask_event_defines.h>
-
-/ {
-	model = "Google Asurada Baseboard";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		zephyr,flash-controller = &flashctrl;
-	};
-
-	ec-mkbp-host-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(
-			HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) |
-			HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) |
-			HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) |
-			HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) |
-			HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) |
-			HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE))>;
-	};
-
-	ec-mkbp-event-wakeup-mask {
-		compatible = "ec-wake-mask-event";
-		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX |
-				MKBP_EVENT_HOST_EVENT)>;
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_vbus_c0 {
-			label = "ADC_VBUS_C0";
-			enum-name = "ADC_VBUS_C0";
-			channel = <0>;
-			mul = <10>;
-		};
-		adc_board_id0 {
-			label = "ADC_BOARD_ID_0";
-			enum-name = "ADC_BOARD_ID_0";
-			channel = <1>;
-		};
-		adc_board_id1 {
-			label = "ADC_BOARD_ID_1";
-			enum-name = "ADC_BOARD_ID_1";
-			channel = <2>;
-		};
-		adc_charger_amon_r {
-			label = "ADC_AMON_BMON";
-			enum-name = "ADC_AMON_BMON";
-			channel = <3>;
-			mul = <1000>;
-			div = <18>;
-		};
-		adc_vbus_c1 {
-			label = "ADC_VBUS_C1";
-			enum-name = "ADC_VBUS_C1";
-			channel = <5>;
-			mul = <10>;
-		};
-		adc_charger_pmon {
-			label = "ADC_PMON";
-			enum-name = "ADC_PMON";
-			channel = <6>;
-		};
-		adc-psys {
-			label = "ADC_PSYS";
-			enum-name = "ADC_PSYS";
-			channel = <6>;
-		};
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		power {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_POWER";
-			label = "POWER";
-		};
-		battery {
-			i2c-port = <&i2c0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		charger {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "CHARGER";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		i2c-accel {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL";
-		};
-		ppc0 {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_PPC0";
-			label = "PPC0";
-		};
-		ppc1 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_PPC1";
-			label = "PPC1";
-		};
-		usb-c0 {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_USB_C0";
-			label = "USB_C0";
-		};
-		usb-c1 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_USB_C1";
-			label = "USB_C1";
-		};
-		usb-mux0 {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_USB_MUX0";
-			label = "USB_MUX0";
-		};
-		usb-mux1 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_USB_MUX1";
-			label = "USB_MUX1";
-		};
-	};
-
-	soc {
-		cros_kb_raw: cros-kb-raw@f01d00 {
-			compatible = "ite,it8xxx2-cros-kb-raw";
-			reg = <0x00f01d00 0x29>;
-			label = "CROS_KB_RAW_0";
-			interrupt-parent = <&intc>;
-			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-	};
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	clock-frequency = <1804800>;
-};
-
-&adc0 {
-	status = "okay";
-};
-
-&i2c0 {
-	/* EC_I2C_PWR_CBI */
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c1 {
-	/* EC_I2C_SENSOR */
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c2 {
-	/* EC_I2C_USB_C0 */
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c4{
-	/* EC_I2C_USB_C1 */
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&cros_kb_raw {
-	status = "okay";
-};
diff --git a/zephyr/boards/riscv/asurada/asurada_defconfig b/zephyr/boards/riscv/asurada/asurada_defconfig
deleted file mode 100644
index be85cd0f07..0000000000
--- a/zephyr/boards/riscv/asurada/asurada_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
-
-# Platform Configuration
-CONFIG_SOC_IT8XXX2=y
-CONFIG_BOARD_ASURADA=y
-
-# SoC configuration
-CONFIG_AP=y
-CONFIG_AP_ARM_MTK_MT8192=y
-CONFIG_HAS_TASK_CHIPSET=y
-
-# Console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_NS16550=y
-CONFIG_SHELL_TAB=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-CONFIG_SHELL_HISTORY=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-CONFIG_GPIO_ITE_IT8XXX2=y
-
-# ADC Driver
-CONFIG_ADC_ITE_IT8XXX2=y
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_PLATFORM_EC_ADC_RESOLUTION=10
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
-
-# Flash
-CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
-CONFIG_PLATFORM_EC_FLASH_CROS=y
-CONFIG_SOC_FLASH_ITE_IT8XXX2=y
-
-# I2C
-CONFIG_I2C_ITE_IT8XXX2=y
-CONFIG_PLATFORM_EC_I2C=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-
-# Lid Switch
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-
-# MKBP
-CONFIG_PLATFORM_EC_MKBP_EVENT=y
-CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
-CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
-CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-CONFIG_PINMUX_ITE_IT8XXX2=y
-
-# Power Button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
-CONFIG_PLATFORM_EC_POWERSEQ_IT8XXX2=y
-CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-CONFIG_PWM_ITE_IT8XXX2=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Serial Host Interface (SHI) device.
-CONFIG_CROS_SHI_IT8XXX2=y
-
-# Timer configuration
-CONFIG_ITE_IT8XXX2_TIMER=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500
-CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_IT8XXX2=y
diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board
deleted file mode 100644
index f0691edb39..0000000000
--- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config BOARD_IT8XXX2_EVB
-	bool "IT8XXX2 EV-board"
-	depends on SOC_IT8XXX2
-	# Allow generating initial 0 line coverage.
-	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig
deleted file mode 100644
index de08d278de..0000000000
--- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if BOARD_IT8XXX2_EVB
-
-config BOARD
-	default "it8xxx2_evb"
-
-endif # BOARD_IT8XXX2_EVB
diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts
deleted file mode 100644
index a1b61d02ec..0000000000
--- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts
+++ /dev/null
@@ -1,255 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-#include <cros/ite/it8xxx2.dtsi>
-#include <dt-bindings/gpio_defines.h>
-#include <it8xxx2.dtsi>
-
-/ {
-	model = "IT8XXX2 EV-Board";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart1;
-		zephyr,shell-uart = &uart1;
-		zephyr,flash = &flash0;
-		zephyr,flash-controller = &flashctrl;
-	};
-
-	named-gpios {
-		compatible = "named-gpios";
-
-		power_button_l: power_button_l {
-			gpios = <&gpioe 4 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "POWER_BUTTON_L";
-		};
-		lid_open: lid_open {
-			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-		wp_l {
-			gpios = <&gpioi 4 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		pch_pltrst_l {
-			gpios = <&gpioe 3 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_PCH_RSMRST_L";
-			label = "PCH_PLTRST_L";
-		};
-		uart1_rx {
-			gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>;
-			#enum-name = "GPIO_UART1_RX";
-			label = "UART1_RX";
-		};
-		pch_smi_l {
-			gpios = <&gpiod 3 GPIO_OUT_HIGH>;
-			#enum-name = "GPIO_PCH_SMI_L";
-			label = "PCH_SMI_L";
-		};
-		pch_sci_l {
-			gpios = <&gpiod 4 GPIO_OUT_HIGH>;
-			#enum-name = "GPIO_PCH_SCI_L";
-			label = "PCH_SCI_L";
-		};
-		gate_a20_h {
-			gpios = <&gpiob 5 GPIO_OUT_HIGH>;
-			#enum-name = "GPIO_GATE_A20_H";
-			label = "GATE_A20_H";
-		};
-		sys_reset_l {
-			gpios = <&gpiob 6 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_SYS_RESET_L";
-			label = "SYS_RESET_L";
-		};
-		lpc_clkrun_l {
-			gpios = <&gpioh 0 GPIO_OUT_LOW>;
-			#enum-name = "GPIO_LPC_CLKRUN_L";
-			label = "LPC_CLKRUN_L";
-		};
-		pch_wake_l {
-			gpios = <&gpiob 7 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "PCH_WAKE_L";
-		};
-		i2c_a_scl {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SCL";
-			label = "I2C_A_SCL";
-		};
-		i2c_a_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SDA";
-			label = "I2C_A_SDA";
-		};
-		i2c_b_scl {
-			gpios = <&gpioc 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SCL";
-			label = "I2C_B_SCL";
-		};
-		i2c_b_sda {
-			gpios = <&gpioc 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SDA";
-			label = "I2C_B_SDA";
-		};
-		i2c_c_scl {
-			gpios = <&gpiof 6 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SCL";
-			label = "I2C_C_SCL";
-		};
-		i2c_c_sda {
-			gpios = <&gpiof 7 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SDA";
-			label = "I2C_C_SDA";
-		};
-		i2c_e_scl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SCL";
-			label = "I2C_E_SCL";
-		};
-		i2c_e_sda {
-			gpios = <&gpioe 7 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SDA";
-			label = "I2C_E_SDA";
-		};
-
-		spi0_cs {
-			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_SPI0_CS";
-			label = "SPI0_CS";
-		};
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <&power_button_l
-			       &lid_open>;
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_vbussa: vbussa {
-			label = "ADC_VBUSSA";
-			enum-name = "ADC_VBUS";
-			channel = <0>;
-		};
-		adc_vbussb: vbussb {
-			label = "ADC_VBUSSB";
-			enum-name = "ADC_PSYS";
-			channel = <1>;
-		};
-		adc_evb_ch_13: evb_ch_13 {
-			label = "ADC_EVB_CH_13";
-			enum-name = "ADC_AMON_BMON";
-			channel = <2>;
-		};
-		adc_evb_ch_14: evb_ch_14 {
-			label = "ADC_EVB_CH_14";
-			enum-name = "ADC_TEMP_SENSOR_FAN";
-			channel = <3>;
-		};
-		adc_evb_ch_15: evb_ch_15 {
-			label = "ADC_EVB_CH_15";
-			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
-			channel = <4>;
-		};
-		adc_evb_ch_16: evb_ch_16 {
-			label = "ADC_EVB_CH_16";
-			enum-name = "ADC_TEMP_SENSOR_CHARGER";
-			channel = <5>;
-		};
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		battery {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		evb-1 {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EVB_1";
-			label = "EVB_1";
-		};
-		evb-2 {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_EVB_2";
-			label = "EVB_2";
-		};
-		opt-4 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_OPT_4";
-			label = "OPT_4";
-		};
-	};
-
-	named-pwms {
-		compatible = "named-pwms";
-		/* NOTE: &pwm number needs same with channel number */
-		test0 {
-			pwms = <&pwm7 PWM_CHANNEL_7 PWM_POLARITY_INVERTED>;
-			label = "TEST0";
-			/*
-			 * If we need pwm output in ITE chip power saving
-			 * mode, then we should set frequency <=324Hz.
-			 */
-			frequency = <324>;
-		};
-		test1 {
-			pwms = <&pwm0 PWM_CHANNEL_0 PWM_POLARITY_NORMAL>;
-			label = "TEST1";
-			frequency = <30000>;
-		};
-	};
-};
-
-&adc0 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c2 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&i2c4 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-};
-
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	clock-frequency = <1804800>;
-};
-
-/* TEST1 */
-&pwm0 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C6>;
-};
-
-/* TEST0 */
-&pwm7 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-};
diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig
deleted file mode 100644
index d667fac5a1..0000000000
--- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
-
-# Platform Configuration
-CONFIG_SOC_IT8XXX2=y
-CONFIG_BOARD_IT8XXX2_EVB=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_NS16550=y
-CONFIG_SHELL_TAB=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-CONFIG_SHELL_HISTORY=y
-
-# Pinmux Driver
-CONFIG_PINMUX=y
-CONFIG_PINMUX_ITE_IT8XXX2=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-CONFIG_PWM_ITE_IT8XXX2=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-CONFIG_GPIO_ITE_IT8XXX2=y
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500
-
-# I2C Controller
-CONFIG_I2C_ITE_IT8XXX2=y
-
-CONFIG_ITE_IT8XXX2_TIMER=y
-
-# ADC
-CONFIG_ADC=y
-CONFIG_ADC_ITE_IT8XXX2=y
-CONFIG_PLATFORM_EC_ADC_RESOLUTION=10
-
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
-
-# Flash
-CONFIG_SOC_FLASH_ITE_IT8XXX2=y
-
-# Code RAM base for IT8XXX2
-CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x80000000
-CONFIG_CROS_EC_RAM_BASE=0x80100000
-CONFIG_CROS_EC_DATA_RAM_SIZE=0x00100000
-CONFIG_CROS_EC_RAM_SIZE=0x0000f000
-
-
-CONFIG_CROS_EC_RO_MEM_OFF=0x0
-CONFIG_CROS_EC_RO_SIZE=0x80000
-CONFIG_CROS_EC_RW_MEM_OFF=0x0
-CONFIG_CROS_EC_RW_SIZE=0x80000
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_IT8XXX2=y
diff --git a/zephyr/cmake/bintools/gnu/target.cmake b/zephyr/cmake/bintools/gnu/target.cmake
deleted file mode 100644
index 2ec9d075dc..0000000000
--- a/zephyr/cmake/bintools/gnu/target.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
-# this out to the copy in ${ZEPHYR_BASE}.
-include("${ZEPHYR_BASE}/cmake/bintools/gnu/target.cmake")
diff --git a/zephyr/cmake/bintools/llvm/generic.cmake b/zephyr/cmake/bintools/llvm/generic.cmake
deleted file mode 100644
index 94b35ed51d..0000000000
--- a/zephyr/cmake/bintools/llvm/generic.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(CMAKE_AR         "/usr/bin/llvm-ar")
-set(CMAKE_NM         "/usr/bin/llvm-nm")
-set(CMAKE_OBJCOPY    "/usr/bin/llvm-objcopy")
-set(CMAKE_OBJDUMP    "/usr/bin/llvm-objdump")
-set(CMAKE_RANLIB     "/usr/bin/llvm-ranlib")
-set(CMAKE_READELF    "/usr/bin/llvm-readelf")
diff --git a/zephyr/cmake/bintools/llvm/target.cmake b/zephyr/cmake/bintools/llvm/target.cmake
deleted file mode 100644
index a77d459288..0000000000
--- a/zephyr/cmake/bintools/llvm/target.cmake
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Use generic bintools.
-include("${TOOLCHAIN_ROOT}/cmake/bintools/llvm/generic.cmake")
-
-# Include the GNU bintools properties as a base.
-include("${ZEPHYR_BASE}/cmake/bintools/gnu/target_bintools.cmake")
diff --git a/zephyr/cmake/compiler/clang/compiler_flags.cmake b/zephyr/cmake/compiler/clang/compiler_flags.cmake
deleted file mode 100644
index d247bd622d..0000000000
--- a/zephyr/cmake/compiler/clang/compiler_flags.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-include("${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake")
-
-# Disable -fno-freestanding.
-set_compiler_property(PROPERTY hosted)
-
-check_set_compiler_property(APPEND PROPERTY warning_extended -Wunused-variable -Werror=unused-variable)
diff --git a/zephyr/cmake/compiler/clang/generic.cmake b/zephyr/cmake/compiler/clang/generic.cmake
deleted file mode 100644
index aa3665ad39..0000000000
--- a/zephyr/cmake/compiler/clang/generic.cmake
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(CMAKE_C_COMPILER "/usr/bin/x86_64-pc-linux-gnu-clang")
-set(CMAKE_GCOV "/usr/bin/llvm-cov gcov")
diff --git a/zephyr/cmake/compiler/clang/target.cmake b/zephyr/cmake/compiler/clang/target.cmake
deleted file mode 100644
index 6702087df5..0000000000
--- a/zephyr/cmake/compiler/clang/target.cmake
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(CMAKE_C_COMPILER "${CROSS_COMPILE}clang")
-set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}clang++")
diff --git a/zephyr/cmake/compiler/gcc/compiler_flags.cmake b/zephyr/cmake/compiler/gcc/compiler_flags.cmake
deleted file mode 100644
index 125f909c87..0000000000
--- a/zephyr/cmake/compiler/gcc/compiler_flags.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
-# this out to the copy in ${ZEPHYR_BASE}.
-include("${ZEPHYR_BASE}/cmake/compiler/gcc/compiler_flags.cmake")
diff --git a/zephyr/cmake/compiler/gcc/target.cmake b/zephyr/cmake/compiler/gcc/target.cmake
deleted file mode 100644
index 5bdb6fc5f6..0000000000
--- a/zephyr/cmake/compiler/gcc/target.cmake
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
-# this out to the copy in ${ZEPHYR_BASE}.
-include("${ZEPHYR_BASE}/cmake/compiler/gcc/target.cmake")
-
-# no_libgcc support has been removed in upstream zephyr, but we still
-# depend on it.  This ugly hack emulates what it used to do by undoing
-# what some of target.cmake does.
-if(no_libgcc)
-  list(REMOVE_ITEM TOOLCHAIN_LIBS gcc)
-endif()
diff --git a/zephyr/cmake/linker/ld/linker_flags.cmake b/zephyr/cmake/linker/ld/linker_flags.cmake
deleted file mode 100644
index c80d1d2452..0000000000
--- a/zephyr/cmake/linker/ld/linker_flags.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
-# this out to the copy in ${ZEPHYR_BASE}.
-include("${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake")
diff --git a/zephyr/cmake/linker/ld/target.cmake b/zephyr/cmake/linker/ld/target.cmake
deleted file mode 100644
index 0e2ad1f4d7..0000000000
--- a/zephyr/cmake/linker/ld/target.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
-# this out to the copy in ${ZEPHYR_BASE}.
-include("${ZEPHYR_BASE}/cmake/linker/ld/target.cmake")
diff --git a/zephyr/cmake/linker/lld/linker_flags.cmake b/zephyr/cmake/linker/lld/linker_flags.cmake
deleted file mode 100644
index 5055e4c5a4..0000000000
--- a/zephyr/cmake/linker/lld/linker_flags.cmake
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Include definitions for bfd as a base.
-include("${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake")
-# ld/linker_flags.cmake includes ${LINKER}/${COMPILER}/linker_flags.cmake but
-# that doesn't exist for ldd, so import the path that actually exists.
-include("${ZEPHYR_BASE}/cmake/linker/ld/${COMPILER}/linker_flags.cmake" OPTIONAL)
diff --git a/zephyr/cmake/linker/lld/target.cmake b/zephyr/cmake/linker/lld/target.cmake
deleted file mode 100644
index 1bbc6f479d..0000000000
--- a/zephyr/cmake/linker/lld/target.cmake
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Include definitions for bfd as a base.  We need to pretend that
-# LINKER=ld to do this.
-set(LINKER ld)
-include("${ZEPHYR_BASE}/cmake/linker/ld/target.cmake")
-set(LINKER lld)
-
-# Override the path to the linker.
-set(CMAKE_LINKER "${CROSS_COMPILE}ld.lld")
-
-# Zephyr CMake system expects this macro to be defined to provide
-# default linker flags.
-macro(toolchain_ld_base)
-  # For linker scripts, we pretend to bfd-like
-  set_property(GLOBAL PROPERTY PROPERTY_LINKER_SCRIPT_DEFINES
-    -D__GCC_LINKER_CMD__)
-
-  # Default flags
-  zephyr_ld_options(
-    ${TOOLCHAIN_LD_FLAGS}
-    -Wl,--gc-sections
-    --build-id=none)
-endmacro()
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake b/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
deleted file mode 100644
index 1b86948bcd..0000000000
--- a/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# generic.cmake is used for host-side compilation and preprocessing
-# (e.g., for device-tree).  Thus, we should use LLVM for this
-# actually, as that's what's currently supported compiler-wise in the
-# chroot right now.
-include("${TOOLCHAIN_ROOT}/cmake/toolchain/llvm/generic.cmake")
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/target.cmake b/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
deleted file mode 100644
index 5f3d86459b..0000000000
--- a/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Coreboot SDK uses GCC
-set(COMPILER gcc)
-set(LINKER ld)
-set(BINTOOLS gnu)
-
-# Mapping of Zephyr architecture -> coreboot-sdk toolchain
-set(CROSS_COMPILE_TARGET_arm    arm-eabi)
-set(CROSS_COMPILE_TARGET_riscv  riscv64-elf)
-set(CROSS_COMPILE_TARGET_x86    i386-elf)
-
-set(CROSS_COMPILE_TARGET        ${CROSS_COMPILE_TARGET_${ARCH}})
-
-if("${ARCH}" STREQUAL "arm" AND CONFIG_ARM64)
-  set(CROSS_COMPILE_TARGET      aarch64-elf)
-elseif("${ARCH}" STREQUAL "x86" AND CONFIG_X86_64)
-  set(CROSS_COMPILE_TARGET      x86_64-elf)
-endif()
-
-set(CC gcc)
-set(CROSS_COMPILE "/opt/coreboot-sdk/bin/${CROSS_COMPILE_TARGET}-")
-
-set(CMAKE_AR         "${CROSS_COMPILE}ar")
-set(CMAKE_NM         "${CROSS_COMPILE}nm")
-set(CMAKE_OBJCOPY    "${CROSS_COMPILE}objcopy")
-set(CMAKE_OBJDUMP    "${CROSS_COMPILE}objdump")
-set(CMAKE_RANLIB     "${CROSS_COMPILE}ranlib")
-set(CMAKE_READELF    "${CROSS_COMPILE}readelf")
-
-# On ARM, we don't use libgcc: It's built against a fixed target (e.g.
-# used instruction set, ABI, ISA extensions) and doesn't adapt when
-# compiler flags change any of these assumptions. Use our own mini-libgcc
-# instead.
-if("${ARCH}" STREQUAL "arm")
-  set(no_libgcc True)
-endif()
diff --git a/zephyr/cmake/toolchain/llvm/generic.cmake b/zephyr/cmake/toolchain/llvm/generic.cmake
deleted file mode 100644
index 6a248a13cf..0000000000
--- a/zephyr/cmake/toolchain/llvm/generic.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(COMPILER clang)
-set(LINKER   lld)
-set(BINTOOLS llvm)
diff --git a/zephyr/cmake/toolchain/llvm/target.cmake b/zephyr/cmake/toolchain/llvm/target.cmake
deleted file mode 100644
index d79d73d1ae..0000000000
--- a/zephyr/cmake/toolchain/llvm/target.cmake
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-set(COMPILER clang)
-set(LINKER lld)
-set(BINTOOLS llvm)
-
-# Mapping of Zephyr architecture -> toolchain triple
-# Note only "posix" is supported at the moment.
-set(CROSS_COMPILE_TARGET_posix    x86_64-pc-linux-gnu)
-
-set(CROSS_COMPILE_TARGET          ${CROSS_COMPILE_TARGET_${ARCH}})
-
-set(CC clang)
-set(CROSS_COMPILE "/usr/bin/${CROSS_COMPILE_TARGET}-")
diff --git a/zephyr/drivers/CMakeLists.txt b/zephyr/drivers/CMakeLists.txt
deleted file mode 100644
index d246f31703..0000000000
--- a/zephyr/drivers/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-add_subdirectory(cros_cbi)
-add_subdirectory(cros_flash)
-add_subdirectory(cros_kb_raw)
-add_subdirectory(cros_rtc)
-add_subdirectory(cros_shi)
-add_subdirectory(cros_system)
diff --git a/zephyr/drivers/Kconfig b/zephyr/drivers/Kconfig
deleted file mode 100644
index 041a6cf212..0000000000
--- a/zephyr/drivers/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-rsource "cros_flash/Kconfig"
-rsource "cros_kb_raw/Kconfig"
-rsource "cros_rtc/Kconfig"
-rsource "cros_system/Kconfig"
-rsource "cros_shi/Kconfig"
diff --git a/zephyr/drivers/cros_cbi/CMakeLists.txt b/zephyr/drivers/cros_cbi/CMakeLists.txt
deleted file mode 100644
index 644865ae77..0000000000
--- a/zephyr/drivers/cros_cbi/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM	cros_cbi.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_GPIO	cros_cbi.c)
diff --git a/zephyr/drivers/cros_cbi/cros_cbi.c b/zephyr/drivers/cros_cbi/cros_cbi.c
deleted file mode 100644
index a36a4e9143..0000000000
--- a/zephyr/drivers/cros_cbi/cros_cbi.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <drivers/cros_cbi.h>
-#include "cros_board_info.h"
-#include <logging/log.h>
-
-LOG_MODULE_REGISTER(cros_cbi, LOG_LEVEL_ERR);
-
-/* CBI SSFC part */
-
-/* This part of the driver is about CBI SSFC part.
- * Actually, two "compatible" values are handle here -
- * named_cbi_ssfc_value and named_cbi_ssfc. named_cbi_ssfc_value nodes are
- * grandchildren of the named_cbi_ssfc node. named_cbi_ssfc_value is introduced
- * to iterate over grandchildren of the named_cbi_ssfc(macro
- * DT_FOREACH_CHILD can not be nested) and it can be pointed by a sensor dts to
- * indicate alternative usage.
- */
-#define DT_DRV_COMPAT named_cbi_ssfc_value
-
-BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(named_cbi_ssfc) < 2,
-	     "More than 1 CBI SSFS node");
-#define CBI_SSFC_NODE DT_INST(0, named_cbi_ssfc)
-
-#define CBI_SSFC_INIT_DEFAULT_ID(id)                                           \
-	do {                                                                   \
-		if (DT_PROP(id, default)) {                                    \
-			cached_ssfc.CBI_SSFC_UNION_ENTRY_NAME(DT_PARENT(id)) = \
-				DT_PROP(id, value);                            \
-		}                                                              \
-	} while (0);
-
-#define CBI_SSFC_INIT_DEFAULT(inst) CBI_SSFC_INIT_DEFAULT_ID(DT_DRV_INST(inst))
-
-#define CBI_SSFC_VALUE_ARRAY_ID(id) \
-	[CBI_SSFC_VALUE_ID(id)] = DT_PROP(id, value),
-
-#define CBI_SSFC_VALUE_ARRAY(inst) CBI_SSFC_VALUE_ARRAY_ID(DT_DRV_INST(inst))
-
-#define CBI_SSFC_VALUE_BUILD_ASSERT(inst)                    \
-	BUILD_ASSERT(DT_INST_PROP(inst, value) <= UINT8_MAX, \
-		     "CBI SSFS value too big");
-
-#define CBI_SSFC_PARENT_VALUE_CASE_GENERATE(value_id, value_parent) \
-	case value_id:                                              \
-		return value_parent;
-
-#define CBI_SSFC_PARENT_VALUE_CASE_ID(id)    \
-	CBI_SSFC_PARENT_VALUE_CASE_GENERATE( \
-		CBI_SSFC_VALUE_ID(id),       \
-		cached_ssfc.CBI_SSFC_UNION_ENTRY_NAME(DT_PARENT(id)))
-
-#define CBI_SSFC_PARENT_VALUE_CASE(inst) \
-	CBI_SSFC_PARENT_VALUE_CASE_ID(DT_DRV_INST(inst))
-
-#define CBI_SSFC_UNION_ENTRY_NAME(id) DT_CAT(cbi_ssfc_, id)
-#define CBI_SSFC_UNION_ENTRY(id)               \
-	uint32_t CBI_SSFC_UNION_ENTRY_NAME(id) \
-		: DT_PROP(id, size);
-
-#define CBI_SSFC_PLUS_FIELD_SIZE(id) +DT_PROP(id, size)
-#define CBI_SSFC_FIELDS_SIZE                                                 \
-	(0 COND_CODE_1(                                                      \
-		DT_NODE_EXISTS(CBI_SSFC_NODE),                               \
-		(DT_FOREACH_CHILD(CBI_SSFC_NODE, CBI_SSFC_PLUS_FIELD_SIZE)), \
-		()))
-
-BUILD_ASSERT(CBI_SSFC_FIELDS_SIZE <= 32, "CBI SSFS is bigger than 32 bits");
-
-/*
- * Define union bit fields based on the device tree entries. Example:
- * cbi-ssfc {
- *	compatible = "named-cbi-ssfc";
- *
- *	base_sensor {
- *		enum-name = "BASE_SENSOR";
- *		size = <3>;
- *		bmi160 {
- *			compatible = "named-cbi-ssfc-value";
- *			status = "okay";
- *			value = <1>;
- *		};
- *	};
- *	lid_sensor {
- *		enum-name = "LID_SENSOR";
- *		size = <3>;
- *		bma255 {
- *			compatible = "named-cbi-ssfc-value";
- *			status = "okay";
- *			value = <1>;
- *		};
- *	};
- *	lightbar {
- *		enum-name = "LIGHTBAR";
- *		size = <2>;
- *		10_led {
- *			compatible = "named-cbi-ssfc-value";
- *			status = "okay";
- *			value = <1>;
- *		};
- *	};
- * };
- * Should be converted into
- * union cbi_ssfc {
- *	struct {
- *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_base_sensor:3
- *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_lid_sensor:3
- *		uint32_t cbi_ssfc_DT_N_S_cbi_ssfc_S_lightbar:2
- *		uint32_t reserved : 24;
- *	};
- *	uint32_t raw_value;
- * };
- */
-union cbi_ssfc {
-	struct {
-#if DT_NODE_EXISTS(CBI_SSFC_NODE)
-		DT_FOREACH_CHILD(CBI_SSFC_NODE, CBI_SSFC_UNION_ENTRY)
-		uint32_t reserved : (32 - CBI_SSFC_FIELDS_SIZE);
-#endif
-	};
-	uint32_t raw_value;
-};
-
-BUILD_ASSERT(sizeof(union cbi_ssfc) == sizeof(uint32_t),
-	     "CBI SSFS structure exceedes 32 bits");
-
-DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_BUILD_ASSERT)
-
-static const uint8_t ssfc_values[] = {
-	DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_ARRAY)
-};
-static union cbi_ssfc cached_ssfc __attribute__((unused));
-
-/* CBI SSFC part end */
-
-/* Device config */
-struct cros_cbi_config {
-	/* SSFC values for specific configs */
-	const uint8_t *ssfc_values;
-};
-
-/* Device data */
-struct cros_cbi_data {
-	/* Cached SSFC configs */
-	union cbi_ssfc cached_ssfc;
-};
-
-/* CBI SSFC part */
-
-static void cros_cbi_ssfc_init(const struct device *dev)
-{
-	struct cros_cbi_data *data = (struct cros_cbi_data *)(dev->data);
-
-	if (cbi_get_ssfc(&data->cached_ssfc.raw_value) != EC_SUCCESS) {
-		DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_INIT_DEFAULT)
-	}
-
-	LOG_INF("Read CBI SSFC : 0x%08X\n", data->cached_ssfc.raw_value);
-}
-
-static uint32_t cros_cbi_ssfc_get_parent_field_value(union cbi_ssfc cached_ssfc,
-						enum cbi_ssfc_value_id value_id)
-{
-	switch (value_id) {
-		DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_PARENT_VALUE_CASE)
-	default:
-		LOG_ERR("CBI SSFC parent field value not found: %d\n",
-		        value_id);
-		return 0;
-	}
-}
-
-static int cros_cbi_ec_ssfc_check_match(const struct device *dev,
-					enum cbi_ssfc_value_id value_id)
-{
-	struct cros_cbi_data *data = (struct cros_cbi_data *)(dev->data);
-	struct cros_cbi_config *cfg = (struct cros_cbi_config *)(dev->config);
-
-	return cros_cbi_ssfc_get_parent_field_value(data->cached_ssfc,
-						    value_id) ==
-	       cfg->ssfc_values[value_id];
-}
-
-/* CBI SSFC part end */
-#undef DT_DRV_COMPAT
-
-static int cros_cbi_ec_init(const struct device *dev)
-{
-	cros_cbi_ssfc_init(dev);
-
-	return 0;
-}
-
-/* cros ec cbi driver registration */
-static const struct cros_cbi_driver_api cros_cbi_driver_api = {
-	.init = cros_cbi_ec_init,
-	.ssfc_check_match = cros_cbi_ec_ssfc_check_match,
-};
-
-static int cbi_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return 0;
-}
-
-static const struct cros_cbi_config cros_cbi_cfg = {
-	.ssfc_values = ssfc_values,
-};
-
-static struct cros_cbi_data cros_cbi_data;
-
-DEVICE_DEFINE(cros_cbi, CROS_CBI_LABEL, cbi_init, NULL, &cros_cbi_data,
-	      &cros_cbi_cfg, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-	      &cros_cbi_driver_api);
diff --git a/zephyr/drivers/cros_flash/CMakeLists.txt b/zephyr/drivers/cros_flash/CMakeLists.txt
deleted file mode 100644
index 6611589ad4..0000000000
--- a/zephyr/drivers/cros_flash/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_IT8XXX2	cros_flash_it8xxx2.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_FLASH_NPCX	cros_flash_npcx.c)
diff --git a/zephyr/drivers/cros_flash/Kconfig b/zephyr/drivers/cros_flash/Kconfig
deleted file mode 100644
index 1d100a6068..0000000000
--- a/zephyr/drivers/cros_flash/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig CROS_FLASH_NPCX
-	bool "Nuvoton NPCX flash driver for the Zephyr shim"
-	depends on SOC_FAMILY_NPCX
-	default y if FLASH_SIZE > 0
-	help
-	  This option enables a flash unit interface (FIU) driver for the NPCX
-	  chip. This is used instead of the flash memory interface so we can
-	  continue to use most of the existing flash memory processing code in
-	  ECOS.
-
-config CROS_FLASH_IT8XXX2
-	bool "ITE IT81202 flash driver for the Zephyr shim"
-	depends on SOC_FAMILY_RISCV_ITE
-	default y
-	help
-	  This option enables the flash driver for the it8xxx2 chip. We can
-	  access the flash by read, write and erase. The it8xxx2 flash size
-	  is 1M byte.
diff --git a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
deleted file mode 100644
index f238b1557b..0000000000
--- a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT ite_it8xxx2_cros_flash
-
-#include <drivers/cros_flash.h>
-#include <drivers/flash.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-
-#include "flash.h"
-#include "host_command.h"
-#include "system.h"
-#include "watchdog.h"
-
-LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
-
-/* Device data */
-struct cros_flash_it8xxx2_data {
-	bool stuck_locked;
-	bool inconsistent_locked;
-	bool all_protected;
-};
-
-/* Driver convenience defines */
-#define DRV_DATA(dev) ((struct cros_flash_it8xxx2_data *)(dev)->data)
-
-#define FLASH_DEV_NAME DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL
-static const struct device *flash_controller;
-
-#define FWP_REG(bank) (bank / 8)
-#define FWP_MASK(bank) (1 << (bank % 8))
-
-enum flash_wp_interface {
-	FLASH_WP_HOST = 0x01,
-	FLASH_WP_DBGR = 0x02,
-	FLASH_WP_EC = 0x04,
-};
-
-enum flash_wp_status {
-	FLASH_WP_STATUS_PROTECT_RO = EC_FLASH_PROTECT_RO_NOW,
-	FLASH_WP_STATUS_PROTECT_ALL = EC_FLASH_PROTECT_ALL_NOW,
-};
-
-/**
- * Protect flash banks until reboot.
- *
- * @param start_bank    Start bank to protect
- * @param bank_count    Number of banks to protect
- */
-static void flash_protect_banks(int start_bank, int bank_count,
-				enum flash_wp_interface wp_if)
-{
-	int bank;
-
-	for (bank = start_bank; bank < start_bank + bank_count; bank++) {
-		if (wp_if & FLASH_WP_EC)
-			IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_HOST)
-			IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank);
-		if (wp_if & FLASH_WP_DBGR)
-			IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank);
-	}
-}
-
-static enum flash_wp_status flash_check_wp(void)
-{
-	enum flash_wp_status wp_status;
-	int all_bank_count, bank;
-
-	all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE;
-
-	for (bank = 0; bank < all_bank_count; bank++) {
-		if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank)))
-			break;
-	}
-
-	if (bank == WP_BANK_COUNT)
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == (WP_BANK_COUNT + PSTATE_BANK_COUNT))
-		wp_status = FLASH_WP_STATUS_PROTECT_RO;
-	else if (bank == all_bank_count)
-		wp_status = FLASH_WP_STATUS_PROTECT_ALL;
-	else
-		wp_status = 0;
-
-	return wp_status;
-}
-
-/* cros ec flash api functions */
-static int cros_flash_it8xxx2_init(const struct device *dev)
-{
-	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
-	int32_t reset_flags, prot_flags, unwanted_prot_flags;
-
-	reset_flags = system_get_reset_flags();
-	prot_flags = crec_flash_get_protect();
-	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/*
-	 * If we have already jumped between images, an earlier image could
-	 * have applied write protection.  Nothing additional needs to be done.
-	 */
-	if (reset_flags & EC_RESET_FLAG_SYSJUMP)
-		return EC_SUCCESS;
-
-	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
-		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_HOST);
-		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_DBGR);
-		/*
-		 * Write protect is asserted.  If we want RO flash protected,
-		 * protect it now.
-		 */
-		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
-		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
-			if (rv)
-				return rv;
-
-			/* Re-read flags */
-			prot_flags = crec_flash_get_protect();
-		}
-	} else {
-		/* Don't want RO flash protected */
-		unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW;
-	}
-
-	/* If there are no unwanted flags, done */
-	if (!(prot_flags & unwanted_prot_flags))
-		return EC_SUCCESS;
-
-	/*
-	 * If the last reboot was a power-on reset, it should have cleared
-	 * write-protect.  If it didn't, then the flash write protect registers
-	 * have been permanently committed and we can't fix that.
-	 */
-	if (reset_flags & EC_RESET_FLAG_POWER_ON) {
-		data->stuck_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	} else {
-		/*
-		 * Set inconsistent flag, because there is no software
-		 * reset can clear write-protect.
-		 */
-		data->inconsistent_locked = 1;
-		return EC_ERROR_ACCESS_DENIED;
-	}
-
-	/* That doesn't return, so if we're still here that's an error */
-	return EC_ERROR_UNKNOWN;
-}
-
-static int cros_flash_it8xxx2_read(const struct device *dev, int offset,
-				   int size, char *dst_data)
-{
-	ARG_UNUSED(dev);
-
-	return flash_read(flash_controller, offset, dst_data, size);
-}
-
-static int cros_flash_it8xxx2_write(const struct device *dev, int offset,
-				    int size, const char *src_data)
-{
-	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
-
-	if (data->all_protected) {
-		return -EACCES;
-	}
-
-	/*
-	 * If AP sends write flash command continuously, EC might not have
-	 * chance to go back to hook task to touch watchdog. Reload watchdog
-	 * on each flash write to prevent the reset.
-	 */
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG))
-		watchdog_reload();
-
-	return flash_write(flash_controller, offset, src_data, size);
-}
-
-static int cros_flash_it8xxx2_erase(const struct device *dev, int offset,
-				    int size)
-{
-	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
-	int ret = 0;
-
-	if (data->all_protected) {
-		return -EACCES;
-	}
-	/*
-	 * Before the flash erasing, the interrupts should be disabled. In
-	 * the flash erasing loop, the SHI interrupt should be enabled to
-	 * handle AP's command, so irq_lock() is not used here.
-	 */
-	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
-		ite_intc_save_and_disable_interrupts();
-	}
-	/*
-	 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command
-	 * during erasing.
-	 */
-	if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
-		IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
-		irq_enable(DT_IRQN(DT_NODELABEL(shi)));
-	}
-	/* Always use sector erase command */
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE) {
-		ret = flash_erase(flash_controller, offset,
-			CONFIG_FLASH_ERASE_SIZE);
-		if (ret)
-			break;
-
-		offset += CONFIG_FLASH_ERASE_SIZE;
-		/*
-		 * If requested erase size is too large at one time on KGD
-		 * flash, we need to reload watchdog to prevent the reset.
-		 */
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG) && (size > 0x10000))
-			watchdog_reload();
-	}
-	/* Restore interrupts */
-	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC)) {
-		ite_intc_restore_interrupts();
-	}
-
-	return ret;
-}
-
-static int cros_flash_it8xxx2_get_protect(const struct device *dev, int bank)
-{
-	ARG_UNUSED(dev);
-
-	return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank);
-}
-
-static uint32_t cros_flash_it8xxx2_get_protect_flags(const struct device *dev)
-{
-	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
-	uint32_t flags = 0;
-
-	flags |= flash_check_wp();
-
-	if (data->all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	/* Check if blocks were stuck locked at pre-init */
-	if (data->stuck_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_STUCK;
-
-	/* Check if flash protection is in inconsistent state at pre-init */
-	if (data->inconsistent_locked)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	return flags;
-}
-
-static int cros_flash_it8xxx2_protect_at_boot(const struct device *dev,
-					      uint32_t new_flags)
-{
-	return -ENOTSUP;
-}
-
-static int cros_flash_it8xxx2_protect_now(const struct device *dev, int all)
-{
-	struct cros_flash_it8xxx2_data *const data = DRV_DATA(dev);
-
-	if (all) {
-		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
-			FLASH_WP_EC);
-		data->all_protected = 1;
-	} else {
-		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
-#ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
-#endif
-	}
-
-	return EC_SUCCESS;
-}
-
-/* cros ec flash driver registration */
-static const struct cros_flash_driver_api cros_flash_it8xxx2_driver_api = {
-	.init = cros_flash_it8xxx2_init,
-	.physical_read = cros_flash_it8xxx2_read,
-	.physical_write = cros_flash_it8xxx2_write,
-	.physical_erase = cros_flash_it8xxx2_erase,
-	.physical_get_protect = cros_flash_it8xxx2_get_protect,
-	.physical_get_protect_flags = cros_flash_it8xxx2_get_protect_flags,
-	.physical_protect_at_boot = cros_flash_it8xxx2_protect_at_boot,
-	.physical_protect_now = cros_flash_it8xxx2_protect_now,
-};
-
-static int flash_it8xxx2_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	flash_controller = device_get_binding(FLASH_DEV_NAME);
-	if (!flash_controller) {
-		LOG_ERR("Fail to find %s", FLASH_DEV_NAME);
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-static struct cros_flash_it8xxx2_data cros_flash_data;
-
-DEVICE_DEFINE(cros_flash_it8xxx2_0, DT_INST_LABEL(0), flash_it8xxx2_init, NULL,
-	      &cros_flash_data, NULL, PRE_KERNEL_1,
-	      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
-	      &cros_flash_it8xxx2_driver_api);
diff --git a/zephyr/drivers/cros_flash/cros_flash_npcx.c b/zephyr/drivers/cros_flash/cros_flash_npcx.c
deleted file mode 100644
index bb1bd12d89..0000000000
--- a/zephyr/drivers/cros_flash/cros_flash_npcx.c
+++ /dev/null
@@ -1,821 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_flash
-
-#include <dt-bindings/clock/npcx_clock.h>
-#include <drivers/cros_flash.h>
-#include <drivers/clock_control.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-#include <sys/__assert.h>
-#include "ec_tasks.h"
-#include "flash.h"
-#include "gpio.h"
-#include "soc_miwu.h"
-#include "spi_flash_reg.h"
-#include "task.h"
-#include "../drivers/flash/spi_nor.h"
-
-LOG_MODULE_REGISTER(cros_flash, LOG_LEVEL_ERR);
-
-static int all_protected; /* Has all-flash protection been requested? */
-static int addr_prot_start;
-static int addr_prot_length;
-static uint8_t flag_prot_inconsistent;
-static uint8_t saved_sr1;
-static uint8_t saved_sr2;
-
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-
-/* Device config */
-struct cros_flash_npcx_config {
-	/* flash interface unit base address */
-	uintptr_t base;
-	/* clock configuration */
-	struct npcx_clk_cfg clk_cfg;
-	/* Flash size (Unit:bytes) */
-	int size;
-	/* pinmux configuration */
-	const uint8_t alts_size;
-	const struct npcx_alt *alts_list;
-};
-
-/* Device data */
-struct cros_flash_npcx_data {
-	/* flag of flash write protection */
-	bool write_protectied;
-	/* mutex of flash interface controller */
-	struct k_sem lock_sem;
-};
-
-/* TODO: Should we replace them with Kconfig variables */
-#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
-
-/* TODO: It should be defined in the spi_nor.h in the zephyr repository */
-#define SPI_NOR_CMD_FAST_READ 0x0B
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_flash_npcx_config *)(dev)->config)
-#define DRV_DATA(dev) ((struct cros_flash_npcx_data *)(dev)->data)
-#define HAL_INSTANCE(dev) (struct fiu_reg *)(DRV_CONFIG(dev)->base)
-
-/* cros ec flash local inline functions */
-static inline void cros_flash_npcx_mutex_lock(const struct device *dev)
-{
-	struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
-	k_sem_take(&data->lock_sem, K_FOREVER);
-}
-
-static inline void cros_flash_npcx_mutex_unlock(const struct device *dev)
-{
-	struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
-	k_sem_give(&data->lock_sem);
-}
-
-static inline void cros_flash_npcx_set_address(const struct device *dev,
-					       uint32_t qspi_addr)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-	uint8_t *addr = (uint8_t *)&qspi_addr;
-
-	/* Write 3 bytes address to UMA registers */
-	inst->UMA_AB2 = addr[2];
-	inst->UMA_AB1 = addr[1];
-	inst->UMA_AB0 = addr[0];
-}
-
-static inline void cros_flash_npcx_cs_level(const struct device *dev, int level)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Set chip select to high/low level */
-	if (level == 0)
-		inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_SW_CS1);
-	else
-		inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_SW_CS1);
-}
-
-static inline void cros_flash_npcx_exec_cmd(const struct device *dev,
-					    uint8_t code, uint8_t cts)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-#ifdef CONFIG_ASSERT
-	struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
-	/* Flash mutex must be held while executing UMA commands */
-	__ASSERT((k_sem_count_get(&data->lock_sem) == 0), "UMA is not locked");
-#endif
-
-	/* set UMA_CODE */
-	inst->UMA_CODE = code;
-	/* execute UMA flash transaction */
-	inst->UMA_CTS = cts;
-	while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-static inline void cros_flash_npcx_burst_read(const struct device *dev,
-					      char *dst_data, int dst_size)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Burst read transaction */
-	for (int idx = 0; idx < dst_size; idx++) {
-		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
-		inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
-		/* wait for UMA to complete */
-		while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-		/* Get read transaction results*/
-		dst_data[idx] = inst->UMA_DB0;
-	}
-}
-
-static inline int cros_flash_npcx_wait_busy_bit_clear(const struct device *dev)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-	int wait_period = 10; /* 10 us period t0 check status register */
-	int timeout = (10 * USEC_PER_SEC) / wait_period; /* 10 seconds */
-
-	do {
-		/* Read status register */
-		inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
-		while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-		/* Status bit is clear */
-		if ((inst->UMA_DB0 & SPI_NOR_WIP_BIT) == 0)
-			break;
-		k_usleep(wait_period);
-	} while (--timeout); /* Wait for busy bit clear */
-
-	if (timeout) {
-		return 0;
-	} else {
-		return -ETIMEDOUT;
-	}
-}
-
-/* cros ec flash local functions */
-static int cros_flash_npcx_wait_ready(const struct device *dev)
-{
-	int ret = 0;
-
-	/* Drive CS to low */
-	cros_flash_npcx_cs_level(dev, 0);
-
-	/* Command for Read status register of flash */
-	cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_RDSR, UMA_CODE_CMD_ONLY);
-	/* Wait busy bit is clear */
-	ret = cros_flash_npcx_wait_busy_bit_clear(dev);
-	/* Drive CS to low */
-	cros_flash_npcx_cs_level(dev, 1);
-
-	return ret;
-}
-
-static int cros_flash_npcx_set_write_enable(const struct device *dev)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-	int ret;
-
-	/* Wait for previous operation to complete */
-	ret = cros_flash_npcx_wait_ready(dev);
-	if (ret != 0)
-		return ret;
-
-	/* Write enable command */
-	cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_WREN, UMA_CODE_CMD_ONLY);
-
-	/* Wait for flash is not busy */
-	ret = cros_flash_npcx_wait_ready(dev);
-	if (ret != 0)
-		return ret;
-
-	if ((inst->UMA_DB0 & SPI_NOR_WEL_BIT) != 0)
-		return 0;
-	else
-		return -EINVAL;
-}
-
-static void cros_flash_npcx_burst_write(const struct device *dev,
-					unsigned int dest_addr,
-					unsigned int bytes,
-					const char *src_data)
-{
-	/* Chip Select down */
-	cros_flash_npcx_cs_level(dev, 0);
-
-	/* Set write address */
-	cros_flash_npcx_set_address(dev, dest_addr);
-	/* Start programming */
-	cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_PP, UMA_CODE_CMD_WR_ADR);
-	for (int i = 0; i < bytes; i++) {
-		cros_flash_npcx_exec_cmd(dev, *src_data, UMA_CODE_CMD_WR_ONLY);
-		src_data++;
-	}
-
-	/* Chip Select up */
-	cros_flash_npcx_cs_level(dev, 1);
-}
-
-static int cros_flash_npcx_program_bytes(const struct device *dev,
-					 uint32_t offset, uint32_t bytes,
-					 const uint8_t *src_data)
-{
-	int write_size;
-	int ret = 0;
-
-	while (bytes > 0) {
-		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes,
-				 CONFIG_FLASH_WRITE_IDEAL_SIZE -
-					 (offset &
-					  (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
-
-		/* Enable write */
-		ret = cros_flash_npcx_set_write_enable(dev);
-		if (ret != 0)
-			return ret;
-
-		/* Executr UMA burst write transaction */
-		cros_flash_npcx_burst_write(dev, offset, write_size, src_data);
-
-		/* Wait write completed */
-		ret = cros_flash_npcx_wait_ready(dev);
-		if (ret != 0)
-			return ret;
-
-		src_data += write_size;
-		offset += write_size;
-		bytes -= write_size;
-	}
-
-	return ret;
-}
-
-static int cros_flash_npcx_get_status_reg(const struct device *dev,
-					  char cmd_code, char *data)
-{
-	int ret = 0;
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-	if (data == 0) {
-		return -EINVAL;
-	}
-
-	/* Lock flash interface device during reading status register */
-	cros_flash_npcx_mutex_lock(dev);
-
-	cros_flash_npcx_exec_cmd(dev, cmd_code, UMA_CODE_CMD_RD_BYTE(1));
-	*data = inst->UMA_DB0;
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_set_status_reg(const struct device *dev, char *data)
-{
-	int ret = 0;
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Lock flash interface device */
-	cros_flash_npcx_mutex_lock(dev);
-	/* Enable write */
-	ret = cros_flash_npcx_set_write_enable(dev);
-	if (ret != 0)
-		return ret;
-
-	inst->UMA_DB0 = data[0];
-	inst->UMA_DB1 = data[1];
-	/* Write status register 1/2 */
-	cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_WRSR,
-				 UMA_CODE_CMD_WR_BYTE(2));
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_write_protection_set(const struct device *dev,
-						bool enable)
-{
-	int ret = 0;
-
-	/* Write protection can be cleared only by core domain reset */
-	if (!enable) {
-		LOG_ERR("WP can be disabled only via core domain reset ");
-		return -ENOTSUP;
-	}
-	/* Lock flash interface device */
-	cros_flash_npcx_mutex_lock(dev);
-	ret = npcx_pinctrl_flash_write_protect_set();
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_write_protection_is_set(const struct device *dev)
-{
-	return npcx_pinctrl_flash_write_protect_is_set();
-}
-
-static int cros_flash_npcx_uma_lock(const struct device *dev, bool enable)
-{
-	struct fiu_reg *const inst = HAL_INSTANCE(dev);
-
-	if (enable) {
-		inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_UMA_LOCK);
-	} else {
-		inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_UMA_LOCK);
-	}
-
-	return 0;
-}
-
-static int flash_get_status1(const struct device *dev)
-{
-	uint8_t reg;
-
-	if (all_protected)
-		return saved_sr1;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	cros_flash_npcx_get_status_reg(dev, CMD_READ_STATUS_REG, &reg);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return reg;
-}
-
-static int flash_get_status2(const struct device *dev)
-{
-	uint8_t reg;
-
-	if (all_protected)
-		return saved_sr1;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	cros_flash_npcx_get_status_reg(dev, CMD_READ_STATUS_REG2, &reg);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return reg;
-}
-
-static int flash_write_status_reg(const struct device *dev, uint8_t *data)
-{
-	return cros_flash_npcx_set_status_reg(dev, data);
-}
-
-static int is_int_flash_protected(const struct device *dev)
-{
-	return cros_flash_npcx_write_protection_is_set(dev);
-}
-
-static void flash_protect_int_flash(const struct device *dev, int enable)
-{
-	/*
-	 * Please notice the type of WP_IF bit is R/W1S. Once it's set,
-	 * only rebooting EC can clear it.
-	 */
-	if (enable)
-		cros_flash_npcx_write_protection_set(dev, enable);
-}
-
-static void flash_uma_lock(const struct device *dev, int enable)
-{
-	if (enable && !all_protected) {
-		/*
-		 * Store SR1 / SR2 for later use since we're about to lock
-		 * out all access (including read access) to these regs.
-		 */
-		saved_sr1 = flash_get_status1(dev);
-		saved_sr2 = flash_get_status2(dev);
-	}
-
-	cros_flash_npcx_uma_lock(dev, enable);
-	all_protected = enable;
-}
-
-static int flash_set_status_for_prot(const struct device *dev, int reg1,
-				     int reg2)
-{
-	uint8_t regs[2];
-
-	/*
-	 * Writing SR regs will fail if our UMA lock is enabled. If WP
-	 * is deasserted then remove the lock and allow the write.
-	 */
-	if (all_protected) {
-		if (is_int_flash_protected(dev))
-			return EC_ERROR_ACCESS_DENIED;
-
-		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED)
-			return EC_ERROR_ACCESS_DENIED;
-		flash_uma_lock(dev, 0);
-	}
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now before setting them.
-	 */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(dev, gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(dev, !gpio_get_level(GPIO_WP_L));
-#endif /*_CONFIG_WP_ACTIVE_HIGH_*/
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	regs[0] = reg1;
-	regs[1] = reg2;
-	flash_write_status_reg(dev, regs);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start,
-				 &addr_prot_length);
-
-	return EC_SUCCESS;
-}
-
-static int flash_check_prot_reg(const struct device *dev, unsigned int offset,
-				unsigned int bytes)
-{
-	unsigned int start;
-	unsigned int len;
-	uint8_t sr1, sr2;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * If WP# is active and ec doesn't protect the status registers of
-	 * internal spi-flash, protect it now.
-	 */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(dev, gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(dev, !gpio_get_level(GPIO_WP_L));
-#endif /* CONFIG_WP_ACTIVE_HIGH */
-
-	sr1 = flash_get_status1(dev);
-	sr2 = flash_get_status2(dev);
-
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute current protect range */
-	rv = spi_flash_reg_to_protect(sr1, sr2, &start, &len);
-	if (rv)
-		return rv;
-
-	/* Check if ranges overlap */
-	if (MAX(start, offset) < MIN(start + len, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-}
-
-static int flash_write_prot_reg(const struct device *dev, unsigned int offset,
-				unsigned int bytes, int hw_protect)
-{
-	int rv;
-	uint8_t sr1 = flash_get_status1(dev);
-	uint8_t sr2 = flash_get_status2(dev);
-
-	/* Invalid values */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Compute desired protect range */
-	rv = spi_flash_protect_to_reg(offset, bytes, &sr1, &sr2);
-	if (rv)
-		return rv;
-
-	if (hw_protect)
-		sr1 |= SPI_FLASH_SR1_SRP0;
-
-	return flash_set_status_for_prot(dev, sr1, sr2);
-}
-
-static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
-{
-	/* Invalid value */
-	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
-		return EC_ERROR_INVAL;
-
-	/* Check if ranges overlap */
-	if (MAX(addr_prot_start, offset) <
-	    MIN(addr_prot_start + addr_prot_length, offset + bytes))
-		return EC_ERROR_ACCESS_DENIED;
-
-	return EC_SUCCESS;
-}
-
-/* cros ec flash api functions */
-static int cros_flash_npcx_init(const struct device *dev)
-{
-	const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
-	struct cros_flash_npcx_data *data = DRV_DATA(dev);
-
-	/* initialize mutux for flash interface controller */
-	k_sem_init(&data->lock_sem, 1, 1);
-
-	/* Configure pin-mux for FIU device */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
-
-	/*
-	 * Protect status registers of internal spi-flash if WP# is active
-	 * during ec initialization.
-	 */
-#ifdef CONFIG_WP_ACTIVE_HIGH
-	flash_protect_int_flash(dev, gpio_get_level(GPIO_WP));
-#else
-	flash_protect_int_flash(dev, !gpio_get_level(GPIO_WP_L));
-#endif /*CONFIG_WP_ACTIVE_HIGH */
-
-	/* Initialize UMA to unlocked */
-	flash_uma_lock(dev, 0);
-
-	return 0;
-}
-
-static int cros_flash_npcx_read(const struct device *dev, int offset, int size,
-				char *dst_data)
-{
-	int ret = 0;
-
-	/* Unlock flash interface device during reading flash */
-	cros_flash_npcx_mutex_lock(dev);
-
-	/* Chip Select down */
-	cros_flash_npcx_cs_level(dev, 0);
-
-	/* Set read address */
-	cros_flash_npcx_set_address(dev, offset);
-	/* Start with fast read command (skip one dummy byte) */
-	cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_FAST_READ,
-				 UMA_CODE_CMD_ADR_WR_BYTE(1));
-	/* Execute burst read */
-	cros_flash_npcx_burst_read(dev, dst_data, size);
-
-	/* Chip Select up */
-	cros_flash_npcx_cs_level(dev, 1);
-
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_write(const struct device *dev, int offset, int size,
-				 const char *src_data)
-{
-	struct cros_flash_npcx_data *const data = DRV_DATA(dev);
-	int ret = 0;
-
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* check protection */
-	if (flash_check_prot_range(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Is write protection enabled? */
-	if (data->write_protectied) {
-		return -EACCES;
-	}
-
-	/* Invalid data pointer? */
-	if (src_data == 0) {
-		return -EINVAL;
-	}
-
-	/* Unlock flash interface device during writing flash */
-	cros_flash_npcx_mutex_lock(dev);
-
-	while (size > 0) {
-		/* First write multiples of 256, then (size % 256) last */
-		int write_len =
-			((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
-				      size :
-				      CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-		ret = cros_flash_npcx_program_bytes(dev, offset, write_len,
-						    src_data);
-		if (ret != 0)
-			break;
-
-		src_data += write_len;
-		offset += write_len;
-		size -= write_len;
-	}
-
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_erase(const struct device *dev, int offset, int size)
-{
-	const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
-	struct cros_flash_npcx_data *const data = DRV_DATA(dev);
-	int ret = 0;
-
-	/* check protection */
-	if (all_protected)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* check protection */
-	if (flash_check_prot_range(offset, size))
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Is write protection enabled? */
-	if (data->write_protectied) {
-		return -EACCES;
-	}
-	/* affected region should be within device */
-	if (offset < 0 || (offset + size) > config->size) {
-		LOG_ERR("Flash erase address or size exceeds expected values. "
-			"Addr: 0x%lx size %zu",
-			(long)offset, size);
-		return -EINVAL;
-	}
-
-	/* address must be aligned to erase size */
-	if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0) {
-		return -EINVAL;
-	}
-
-	/* Erase size must be a non-zero multiple of sectors */
-	if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0) {
-		return -EINVAL;
-	}
-
-	/* Unlock flash interface device during erasing flash */
-	cros_flash_npcx_mutex_lock(dev);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-			 offset += CONFIG_FLASH_ERASE_SIZE) {
-
-		/* Enable write */
-		ret = cros_flash_npcx_set_write_enable(dev);
-		if (ret != 0)
-			break;
-
-		/* Set erase address */
-		cros_flash_npcx_set_address(dev, offset);
-		/* Start erasing */
-		cros_flash_npcx_exec_cmd(dev, SPI_NOR_CMD_BE, UMA_CODE_CMD_ADR);
-
-		/* Wait erase completed */
-		ret = cros_flash_npcx_wait_ready(dev);
-		if (ret != 0) {
-			break;
-		}
-	}
-
-	/* Unlock flash interface device */
-	cros_flash_npcx_mutex_unlock(dev);
-
-	return ret;
-}
-
-static int cros_flash_npcx_get_protect(const struct device *dev, int bank)
-{
-	uint32_t addr = bank * CONFIG_FLASH_BANK_SIZE;
-
-	return flash_check_prot_reg(dev, addr, CONFIG_FLASH_BANK_SIZE);
-}
-
-static uint32_t cros_flash_npcx_get_protect_flags(const struct device *dev)
-{
-	uint32_t flags = 0;
-
-	/* Check if WP region is protected in status register */
-	if (flash_check_prot_reg(dev, WP_BANK_OFFSET * CONFIG_FLASH_BANK_SIZE,
-				 WP_BANK_COUNT * CONFIG_FLASH_BANK_SIZE))
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * TODO: If status register protects a range, but SRP0 is not set,
-	 * flags should indicate EC_FLASH_PROTECT_ERROR_INCONSISTENT.
-	 */
-	if (flag_prot_inconsistent)
-		flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT;
-
-	/* Read all-protected state from our shadow copy */
-	if (all_protected)
-		flags |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return flags;
-}
-
-static int cros_flash_npcx_protect_at_boot(const struct device *dev,
-					   uint32_t new_flags)
-{
-	int ret;
-
-	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
-			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
-		/* Clear protection bits in status register */
-		return flash_set_status_for_prot(dev, 0, 0);
-	}
-
-	ret = flash_write_prot_reg(dev, CONFIG_WP_STORAGE_OFF,
-				   CONFIG_WP_STORAGE_SIZE, 1);
-
-	/*
-	 * Set UMA_LOCK bit for locking all UMA transaction.
-	 * But we still can read directly from flash mapping address
-	 */
-	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
-		flash_uma_lock(dev, 1);
-
-	return ret;
-}
-
-static int cros_flash_npcx_protect_now(const struct device *dev, int all)
-{
-	if (all) {
-		/*
-		 * Set UMA_LOCK bit for locking all UMA transaction.
-		 * But we still can read directly from flash mapping address
-		 */
-		flash_uma_lock(dev, 1);
-	} else {
-		/* TODO: Implement RO "now" protection */
-	}
-
-	return EC_SUCCESS;
-}
-
-/* cros ec flash driver registration */
-static const struct cros_flash_driver_api cros_flash_npcx_driver_api = {
-	.init = cros_flash_npcx_init,
-	.physical_read = cros_flash_npcx_read,
-	.physical_write = cros_flash_npcx_write,
-	.physical_erase = cros_flash_npcx_erase,
-	.physical_get_protect = cros_flash_npcx_get_protect,
-	.physical_get_protect_flags = cros_flash_npcx_get_protect_flags,
-	.physical_protect_at_boot = cros_flash_npcx_protect_at_boot,
-	.physical_protect_now = cros_flash_npcx_protect_now,
-};
-
-static int flash_npcx_init(const struct device *dev)
-{
-	const struct cros_flash_npcx_config *const config = DRV_CONFIG(dev);
-	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
-
-	int ret;
-
-	/* Turn on device clock first and get source clock freq. */
-	ret = clock_control_on(clk_dev,
-			       (clock_control_subsys_t *)&config->clk_cfg);
-	if (ret < 0) {
-		LOG_ERR("Turn on FIU clock fail %d", ret);
-		return ret;
-	}
-
-	return ret;
-}
-
-static const struct npcx_alt cros_flash_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
-static const struct cros_flash_npcx_config cros_flash_cfg = {
-	.base = DT_INST_REG_ADDR(0),
-	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
-	.size = DT_INST_PROP(0, size),
-	.alts_size = ARRAY_SIZE(cros_flash_alts),
-	.alts_list = cros_flash_alts,
-};
-
-static struct cros_flash_npcx_data cros_flash_data;
-
-DEVICE_DT_INST_DEFINE(0, flash_npcx_init, NULL, &cros_flash_data,
-		      &cros_flash_cfg, PRE_KERNEL_1,
-		      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		      &cros_flash_npcx_driver_api);
diff --git a/zephyr/drivers/cros_kb_raw/CMakeLists.txt b/zephyr/drivers/cros_kb_raw/CMakeLists.txt
deleted file mode 100644
index a9ef2b4bb2..0000000000
--- a/zephyr/drivers/cros_kb_raw/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX	cros_kb_raw_npcx.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE	cros_kb_raw_ite.c)
diff --git a/zephyr/drivers/cros_kb_raw/Kconfig b/zephyr/drivers/cros_kb_raw/Kconfig
deleted file mode 100644
index a037cdd451..0000000000
--- a/zephyr/drivers/cros_kb_raw/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig CROS_KB_RAW_NPCX
-	bool "Nuvoton NPCX raw-keyboard-scan driver for the Zephyr shim"
-	depends on SOC_FAMILY_NPCX
-	default y
-	help
-	  This option enables a driver for providing raw access to the
-	  keyboard-scan peripheral in the chip. This is used instead of the
-	  kscan interface so we can continue to use most of the existing
-	  keyboard-scanning code in ECOS.
-
-if CROS_KB_RAW_NPCX
-
-config CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE
-	bool "Enable quasi-bidirectional buffers for KSO pins"
-	help
-	  This option enables quasi-bidirectional buffers for KSO pins. The
-	  low-impedance high drive is active when ec changes the output data
-	  buffers from 0 to 1, thereby reducing the low-to-high transition time.
-
-endif # CROS_KB_RAW_NPCX
-
-menuconfig CROS_KB_RAW_ITE
-	bool "ITE raw-keyboard-scan driver for the Zephyr shim"
-	depends on SOC_FAMILY_RISCV_ITE
-	default y
-	help
-	  This option enables a driver for providing raw access to the
-	  keyboard-scan peripheral in the chip. This is used instead of the
-	  kscan interface so we can continue to use most of the existing
-	  keyboard-scanning code in ECOS.
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
deleted file mode 100644
index 85b2a1a8ee..0000000000
--- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT ite_it8xxx2_cros_kb_raw
-
-#include <assert.h>
-#include <drivers/cros_kb_raw.h>
-#include <drivers/clock_control.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <soc.h>
-#include <soc/ite_it8xxx2/reg_def_cros.h>
-
-#include "ec_tasks.h"
-#include "keyboard_raw.h"
-#include "task.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
-
-#define KSOH_PIN_MASK (((1 << (KEYBOARD_COLS_MAX - 8)) - 1) & 0xff)
-
-/* Device config */
-struct cros_kb_raw_ite_config {
-	/* keyboard scan controller base address */
-	uintptr_t base;
-	/* Keyboard scan input (KSI) wake-up irq */
-	int irq;
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_kb_raw_ite_config *)(dev)->config)
-#define HAL_INSTANCE(dev) (struct kbs_reg *)(DRV_CONFIG(dev)->base)
-
-static int kb_raw_ite_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	/* Clock default is on */
-	return 0;
-}
-
-/* Cros ec keyboard raw api functions */
-static int cros_kb_raw_ite_enable_interrupt(const struct device *dev,
-					    int enable)
-{
-	const struct cros_kb_raw_ite_config *const config = DRV_CONFIG(dev);
-
-	if (enable) {
-		ECREG(IT8XXX2_WUC_WUESR3) = 0xFF;
-		ite_intc_isr_clear(config->irq);
-		irq_enable(config->irq);
-	} else {
-		irq_disable(config->irq);
-	}
-
-	return 0;
-}
-
-static int cros_kb_raw_ite_read_row(const struct device *dev)
-{
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Bits are active-low, so invert returned levels */
-	return ((inst->KBS_KSI) ^ 0xff);
-}
-
-static int cros_kb_raw_ite_drive_column(const struct device *dev, int col)
-{
-	int mask;
-	unsigned int key;
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Tri-state all outputs */
-	if (col == KEYBOARD_COLUMN_NONE)
-		mask = 0xffff;
-	/* Assert all outputs */
-	else if (col == KEYBOARD_COLUMN_ALL)
-		mask = 0;
-	/* Assert a single output */
-	else
-		mask = 0xffff ^ BIT(col);
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
-	/* KSO[2] is inverted. */
-	mask ^= BIT(2);
-#endif
-	inst->KBS_KSOL = mask & 0xff;
-	/* critical section with interrupts off */
-	key = irq_lock();
-	/*
-	 * Because IT8XXX2_KBS_KSOH1 register is shared by keyboard scan
-	 * out and GPIO output mode, so we don't drive all KSOH pins
-	 * here (this depends on how many keyboard matrix output pin
-	 * we are using).
-	 */
-	inst->KBS_KSOH1 = ((inst->KBS_KSOH1) & ~KSOH_PIN_MASK) |
-		      ((mask >> 8) & KSOH_PIN_MASK);
-	/* restore interrupts */
-	irq_unlock(key);
-
-	return 0;
-}
-
-static void cros_kb_raw_ite_ksi_isr(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	/*
-	 * We clear IT8XXX2_IRQ_WKINTC irq status in
-	 * ite_intc_irq_handler(), after interrupt was fired.
-	 */
-	/* W/C wakeup interrupt status for KSI[0-7] */
-	ECREG(IT8XXX2_WUC_WUESR3) = 0xFF;
-
-	/* Wake-up keyboard scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-static int cros_kb_raw_ite_init(const struct device *dev)
-{
-	unsigned int key;
-	const struct cros_kb_raw_ite_config *const config = DRV_CONFIG(dev);
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Ensure top-level interrupt is disabled */
-	cros_kb_raw_ite_enable_interrupt(dev, 0);
-
-	/*
-	 * bit2, Setting 1 enables the internal pull-up of the KSO[15:0] pins.
-	 * To pull up KSO[17:16], set the GPCR registers of their
-	 * corresponding GPIO ports.
-	 * bit0, Setting 1 enables the open-drain mode of the KSO[17:0] pins.
-	 */
-	inst->KBS_KSOCTRL = (IT8XXX2_KBS_KSOPU | IT8XXX2_KBS_KSOOD);
-	/* bit2, 1 enables the internal pull-up of the KSI[7:0] pins. */
-	inst->KBS_KSICTRL = IT8XXX2_KBS_KSIPU;
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
-	/* KSO[2] output high, others output low. */
-	inst->KBS_KSOL = BIT(2);
-	/* Enable KSO2's push-pull */
-	inst->KBS_KSOLGCTRL |= IT8XXX2_KBS_KSO2GCTRL;
-	inst->KBS_KSOLGOEN |= IT8XXX2_KBS_KSO2GOEN;
-#else
-	/* KSO[7:0] pins output low. */
-	inst->KBS_KSOL = 0x00;
-#endif
-	/* critical section with interrupts off */
-	key = irq_lock();
-	/*
-	 * KSO[COLS_MAX:8] pins low.
-	 * NOTE: KSO[15:8] pins can part be enabled for keyboard function and
-	 *       rest be configured as GPIO output mode. In this case that we
-	 *       disable the ISR in critical section to avoid race condition.
-	 */
-	inst->KBS_KSOH1 &= ~KSOH_PIN_MASK;
-	/* restore interrupts */
-	irq_unlock(key);
-	/* Select falling-edge triggered of wakeup interrupt for KSI[0-7] */
-	ECREG(IT8XXX2_WUC_WUEMR3) = 0xFF;
-	/* W/C wakeup interrupt status for KSI[0-7] */
-	ECREG(IT8XXX2_WUC_WUESR3) = 0xFF;
-	ite_intc_isr_clear(config->irq);
-	/* Enable wakeup interrupt for KSI[0-7] */
-	ECREG(IT8XXX2_WUC_WUENR3) = 0xFF;
-
-	IRQ_CONNECT(DT_INST_IRQN(0), 0, cros_kb_raw_ite_ksi_isr, NULL, 0);
-
-	return 0;
-}
-
-static const struct cros_kb_raw_driver_api cros_kb_raw_ite_driver_api = {
-	.init = cros_kb_raw_ite_init,
-	.drive_colum = cros_kb_raw_ite_drive_column,
-	.read_rows = cros_kb_raw_ite_read_row,
-	.enable_interrupt = cros_kb_raw_ite_enable_interrupt,
-};
-
-static const struct cros_kb_raw_ite_config cros_kb_raw_cfg = {
-	.base = DT_INST_REG_ADDR(0),
-	.irq = DT_INST_IRQN(0),
-};
-
-DEVICE_DT_INST_DEFINE(0, kb_raw_ite_init, NULL, NULL, &cros_kb_raw_cfg,
-		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		      &cros_kb_raw_ite_driver_api);
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
deleted file mode 100644
index 00965b74ca..0000000000
--- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_kb_raw
-
-#include <assert.h>
-#include <dt-bindings/clock/npcx_clock.h>
-#include <drivers/cros_kb_raw.h>
-#include <drivers/clock_control.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-
-#include "ec_tasks.h"
-#include "keyboard_raw.h"
-#include "soc_miwu.h"
-#include "task.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_kb_raw, LOG_LEVEL_ERR);
-
-#define NPCX_MAX_KEY_COLS 18 /* Maximum rows of keyboard matrix */
-#define NPCX_MAX_KEY_ROWS 8 /* Maximum columns of keyboard matrix */
-#define NPCX_KB_ROW_MASK (BIT(NPCX_MAX_KEY_ROWS) - 1)
-
-/* Device config */
-struct cros_kb_raw_npcx_config {
-	/* keyboard scan controller base address */
-	uintptr_t base;
-	/* clock configuration */
-	struct npcx_clk_cfg clk_cfg;
-	/* pinmux configuration */
-	const uint8_t alts_size;
-	const struct npcx_alt *alts_list;
-	/* Keyboard scan input (KSI) wake-up irq */
-	int irq;
-	/* Size of keyboard inputs-wui mapping array */
-	int wui_size;
-	/* Mapping table between keyboard inputs and wui */
-	struct npcx_wui wui_maps[];
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_kb_raw_npcx_config *)(dev)->config)
-#define HAL_INSTANCE(dev) (struct kbs_reg *)(DRV_CONFIG(dev)->base)
-
-/* Keyboard Scan local functions */
-static struct miwu_dev_callback ksi_callback[NPCX_MAX_KEY_ROWS];
-
-static void kb_raw_npcx_init_ksi_wui_callback(
-	const struct device *dev, struct miwu_dev_callback *callback,
-	const struct npcx_wui *wui, miwu_dev_callback_handler_t handler)
-{
-	/* KSI signal which has no wake-up input source */
-	if (wui->table == NPCX_MIWU_TABLE_NONE)
-		return;
-
-	/* Install callback function */
-	npcx_miwu_init_dev_callback(callback, wui, handler, dev);
-	npcx_miwu_manage_dev_callback(callback, 1);
-
-	/* Configure MIWU setting and enable its interrupt */
-	npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
-				      NPCX_MIWU_TRIG_BOTH);
-	npcx_miwu_irq_enable(wui);
-}
-
-static int kb_raw_npcx_init(const struct device *dev)
-{
-	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
-	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
-	int ret;
-
-	/* Turn on device clock first and get source clock freq. */
-	ret = clock_control_on(clk_dev,
-			       (clock_control_subsys_t *)&config->clk_cfg);
-	if (ret < 0) {
-		LOG_ERR("Turn on KSCAN clock fail %d", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-/* Cros ec keyboard raw api functions */
-static int cros_kb_raw_npcx_enable_interrupt(const struct device *dev,
-					     int enable)
-{
-	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
-
-	if (enable)
-		irq_enable(config->irq);
-	else
-		irq_disable(config->irq);
-
-	return 0;
-}
-
-static int cros_kb_raw_npcx_read_row(const struct device *dev)
-{
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-	int val;
-
-	val = inst->KBSIN;
-	LOG_DBG("rows raw %02x", val);
-
-	/* 1 means key pressed, otherwise means key released. */
-	return (~val & NPCX_KB_ROW_MASK);
-}
-
-static int cros_kb_raw_npcx_drive_column(const struct device *dev, int col)
-{
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
-	/*
-	 * Nuvoton 'Keyboard Scan' module supports 18x8 matrix
-	 * It also support automatic scan functionality.
-	 */
-	uint32_t mask, col_out;
-
-	/* Add support for CONFIG_KEYBOARD_KSO_BASE shifting */
-	col_out = col + CONFIG_KEYBOARD_KSO_BASE;
-
-	/* Drive all lines to high. ie. Key detection is disabled. */
-	if (col == KEYBOARD_COLUMN_NONE) {
-		mask = ~0;
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
-			gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-	}
-	/* Drive all lines to low for detection any key press */
-	else if (col == KEYBOARD_COLUMN_ALL) {
-		mask = ~(BIT(keyboard_cols) - 1);
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
-			gpio_set_level(GPIO_KBD_KSO2, 1);
-		}
-	}
-	/* Drive one line to low for determining which key's state changed. */
-	else {
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED)) {
-			if (col == 2)
-				gpio_set_level(GPIO_KBD_KSO2, 1);
-			else
-				gpio_set_level(GPIO_KBD_KSO2, 0);
-		}
-		mask = ~BIT(col_out);
-	}
-
-	/* Set KBSOUT */
-	inst->KBSOUT0 = (mask & 0xFFFF);
-	inst->KBSOUT1 = ((mask >> 16) & 0x03);
-
-	return 0;
-}
-
-static void cros_kb_raw_npcx_ksi_isr(const struct device *dev,
-				     struct npcx_wui *wui)
-{
-	ARG_UNUSED(dev);
-	ARG_UNUSED(wui);
-
-	LOG_DBG("%s: KSI%d is changed", __func__, wui->bit);
-	/* Wake-up keyboard scan task */
-	task_wake(TASK_ID_KEYSCAN);
-}
-
-static int cros_kb_raw_npcx_init(const struct device *dev)
-{
-	const struct cros_kb_raw_npcx_config *const config = DRV_CONFIG(dev);
-	struct kbs_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Pull-up KBSIN0-7 internally */
-	inst->KBSINPU = 0xFF;
-
-	/*
-	 * Keyboard Scan Control Register
-	 *
-	 * [6:7] - KBHDRV KBSOUTn signals output buffers are open-drain.
-	 * [3] - KBSINC   Auto-increment of Buffer Data register is disabled
-	 * [2] - KBSIEN   Interrupt of Auto-Scan is disabled
-	 * [1] - KBSMODE  Key detection mechanism is implemented by firmware
-	 * [0] - START    Write 0 to this field is not affected
-	 */
-	inst->KBSCTL = 0x00;
-
-	/*
-	 * Select quasi-bidirectional buffers for KSO pins. It reduces the
-	 * low-to-high transition time. This feature only supports in npcx7.
-	 */
-	if (IS_ENABLED(CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE)) {
-		SET_FIELD(inst->KBSCTL, NPCX_KBSCTL_KBHDRV_FIELD, 0x01);
-	}
-
-	/* Configure pin-mux for kscan device */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
-
-	/* Drive all column lines to low for detection any key press */
-	cros_kb_raw_npcx_drive_column(dev, KEYBOARD_COLUMN_ALL);
-
-	/* Configure wake-up input and callback for keyboard input signal */
-	for (int i = 0; i < ARRAY_SIZE(ksi_callback); i++)
-		kb_raw_npcx_init_ksi_wui_callback(dev, &ksi_callback[i],
-						  &config->wui_maps[i],
-						  cros_kb_raw_npcx_ksi_isr);
-
-	return 0;
-}
-
-static const struct cros_kb_raw_driver_api cros_kb_raw_npcx_driver_api = {
-	.init = cros_kb_raw_npcx_init,
-	.drive_colum = cros_kb_raw_npcx_drive_column,
-	.read_rows = cros_kb_raw_npcx_read_row,
-	.enable_interrupt = cros_kb_raw_npcx_enable_interrupt,
-};
-
-static const struct npcx_alt cros_kb_raw_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
-
-static const struct cros_kb_raw_npcx_config cros_kb_raw_cfg = {
-	.base = DT_INST_REG_ADDR(0),
-	.alts_size = ARRAY_SIZE(cros_kb_raw_alts),
-	.alts_list = cros_kb_raw_alts,
-	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
-	.irq = DT_INST_IRQN(0),
-	.wui_size = NPCX_DT_WUI_ITEMS_LEN(0),
-	.wui_maps = NPCX_DT_WUI_ITEMS_LIST(0),
-};
-
-/* Verify there's exactly 1 enabled cros,kb-raw-npcx node. */
-BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1);
-DEVICE_DT_INST_DEFINE(0, kb_raw_npcx_init, NULL, NULL, &cros_kb_raw_cfg,
-		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		      &cros_kb_raw_npcx_driver_api);
-
-/* KBS register structure check */
-NPCX_REG_SIZE_CHECK(kbs_reg, 0x010);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBSIN, 0x004);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBSOUT0, 0x006);
-NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
diff --git a/zephyr/drivers/cros_rtc/CMakeLists.txt b/zephyr/drivers/cros_rtc/CMakeLists.txt
deleted file mode 100644
index f6ce9b6890..0000000000
--- a/zephyr/drivers/cros_rtc/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_CROS_RTC_NPCX	cros_rtc_npcx.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_RTC_NXP_PCF85063A
-	nxp_rtc_pcf85063a.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_RTC_RENESAS_IDT1337AG
-	renesas_rtc_idt1337ag.c)
diff --git a/zephyr/drivers/cros_rtc/Kconfig b/zephyr/drivers/cros_rtc/Kconfig
deleted file mode 100644
index 9abe8e27e0..0000000000
--- a/zephyr/drivers/cros_rtc/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC_RTC
-
-choice CROS_RTC_TYPE
-	prompt "Select the RTC to use"
-	default CROS_RTC_NPCX if SOC_FAMILY_NPCX
-	help
-	  Select the RTC used on the board.
-
-config CROS_RTC_NPCX
-	bool "Nuvoton NPCX Real-Time Clock (RTC) driver for the Zephyr shim"
-	depends on SOC_FAMILY_NPCX
-	help
-	  This option enables a driver for providing the support of Real-Time
-	  Clock (RTC) on the NPCX chip.
-
-config CROS_RTC_NXP_PCF85063A
-	bool "NXP PCF85063A Real-Time Clock (RTC) driver for the Zephyr shim"
-	depends on PLATFORM_EC_I2C
-	help
-	  This option enables a driver for providing the support of NXP
-	  Real-Time Clock (RTC) on the the I2C bus.
-
-config CROS_RTC_RENESAS_IDT1337AG
-	bool "RENESAS IDT1337AG Real-Time Clock (RTC) driver for the Zephyr shim"
-	depends on PLATFORM_EC_I2C
-	help
-	  This option enables a driver for providing the support of RENESAS
-	  Real-Time Clock (RTC) on the the I2C bus.
-
-endchoice  # RTC Select
-
-endif # PLATFORM_EC_RTC
diff --git a/zephyr/drivers/cros_rtc/cros_rtc_npcx.c b/zephyr/drivers/cros_rtc/cros_rtc_npcx.c
deleted file mode 100644
index 0ecbe5f47c..0000000000
--- a/zephyr/drivers/cros_rtc/cros_rtc_npcx.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright 2021 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_mtc
-
-#include <assert.h>
-#include <drivers/cros_rtc.h>
-#include <drivers/gpio.h>
-#include <kernel.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-
-#include "ec_tasks.h"
-#include "soc_miwu.h"
-#include "task.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
-
-#define NPCX_MTC_TTC_LOAD_DELAY_US 250 /* Delay after writing TTC */
-#define NPCX_MTC_ALARM_MASK GENMASK(24, 0) /* Valid field of alarm in WTC */
-
-/* Driver config */
-struct cros_rtc_npcx_config {
-	/* Monotonic counter base address */
-	uintptr_t base;
-	/* Monotonic counter wake-up input source configuration */
-	const struct npcx_wui mtc_alarm;
-};
-
-/* Driver data */
-struct cros_rtc_npcx_data {
-	/* Monotonic counter wake-up callback object */
-	struct miwu_dev_callback miwu_mtc_cb;
-	cros_rtc_alarm_callback_t alarm_callback;
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_rtc_npcx_config *)(dev)->config)
-
-#define DRV_DATA(dev) ((struct cros_rtc_npcx_data *)(dev)->data)
-
-#define HAL_INSTANCE(dev) (struct mtc_reg *)(DRV_CONFIG(dev)->base)
-
-/* Counter internal local functions */
-static uint32_t counter_npcx_get_val(const struct device *dev)
-{
-	struct mtc_reg *const inst = HAL_INSTANCE(dev);
-
-	/*
-	 * Get value of monotonic counter which keeps counting when VCC1 power
-	 * domain exists (Unit:sec)
-	 */
-	return inst->TTC;
-}
-
-static void counter_npcx_set_val(const struct device *dev, uint32_t val)
-{
-	struct mtc_reg *const inst = HAL_INSTANCE(dev);
-
-	/*
-	 * Set monotonic counter. Write it twice to ensure the value latch to
-	 * TTC register. A delay (~250 us) is also needed before writing again.
-	 */
-	inst->TTC = val;
-	k_busy_wait(NPCX_MTC_TTC_LOAD_DELAY_US);
-
-	inst->TTC = val;
-	k_busy_wait(NPCX_MTC_TTC_LOAD_DELAY_US);
-}
-
-static uint32_t counter_npcx_get_alarm_val(const struct device *dev)
-{
-	struct mtc_reg *const inst = HAL_INSTANCE(dev);
-
-	/*
-	 * If alarm is not set or it is set and has already gone off, return
-	 * zero directly.
-	 */
-	if (!IS_BIT_SET(inst->WTC, NPCX_WTC_WIE) ||
-	    IS_BIT_SET(inst->WTC, NPCX_WTC_PTO)) {
-		return 0;
-	}
-
-	/* Return 25-bit alarm value */
-	return inst->WTC & NPCX_MTC_ALARM_MASK;
-}
-
-static void counter_npcx_set_alarm_val(const struct device *dev, uint32_t val)
-{
-	struct mtc_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Disable alarm interrupt */
-	inst->WTC &= ~BIT(NPCX_WTC_WIE);
-
-	/* Set new alarm value */
-	inst->WTC = val & NPCX_MTC_ALARM_MASK;
-
-	/* Enable alarm interrupt */
-	inst->WTC |= BIT(NPCX_WTC_WIE);
-}
-
-static void counter_npcx_reset_alarm(const struct device *dev)
-{
-	struct mtc_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Disable alarm interrupt first */
-	if (IS_BIT_SET(inst->WTC, NPCX_WTC_WIE)) {
-		inst->WTC &= ~BIT(NPCX_WTC_WIE);
-	}
-
-	/* Set alarm to maximum value and clear its pending bit */
-	if (IS_BIT_SET(inst->WTC, NPCX_WTC_PTO)) {
-		inst->WTC = NPCX_MTC_ALARM_MASK;
-		inst->WTC |= BIT(NPCX_WTC_PTO);
-	}
-}
-
-/* Counter local functions */
-static void counter_npcx_isr(const struct device *dev, struct npcx_wui *wui)
-{
-	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
-
-	LOG_DBG("%s", __func__);
-
-	/* Alarm is one-shot, so reset alarm to default */
-	counter_npcx_reset_alarm(dev);
-
-	/* Call callback function */
-	if (data->alarm_callback) {
-		data->alarm_callback(dev);
-	}
-}
-
-/* cros ec RTC api functions */
-static int cros_rtc_npcx_configure(const struct device *dev,
-				   cros_rtc_alarm_callback_t callback)
-{
-	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
-
-	if (callback == NULL) {
-		return -EINVAL;
-	}
-
-	data->alarm_callback = callback;
-	return 0;
-}
-
-static int cros_rtc_npcx_get_value(const struct device *dev, uint32_t *value)
-{
-	*value = counter_npcx_get_val(dev);
-
-	return 0;
-}
-
-static int cros_rtc_npcx_set_value(const struct device *dev, uint32_t value)
-{
-	counter_npcx_set_val(dev, value);
-
-	return 0;
-}
-static int cros_rtc_npcx_get_alarm(const struct device *dev, uint32_t *seconds,
-				   uint32_t *microseconds)
-{
-	*seconds = counter_npcx_get_alarm_val(dev);
-	*microseconds = 0;
-
-	return 0;
-}
-static int cros_rtc_npcx_set_alarm(const struct device *dev, uint32_t seconds,
-				   uint32_t microseconds)
-{
-	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
-	ARG_UNUSED(microseconds);
-
-	/* Enable interrupt of the MTC alarm wake-up input source */
-	npcx_miwu_irq_enable(&config->mtc_alarm);
-
-	/* Make sure alarm restore to default state */
-	counter_npcx_reset_alarm(dev);
-	counter_npcx_set_alarm_val(dev, seconds);
-
-	return 0;
-}
-
-static int cros_rtc_npcx_reset_alarm(const struct device *dev)
-{
-	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
-
-	/* Disable interrupt of the MTC alarm wake-up input source */
-	npcx_miwu_irq_disable(&config->mtc_alarm);
-
-	counter_npcx_reset_alarm(dev);
-
-	return 0;
-}
-
-/* cros ec RTC driver registration */
-static const struct cros_rtc_driver_api cros_rtc_npcx_driver_api = {
-	.configure = cros_rtc_npcx_configure,
-	.get_value = cros_rtc_npcx_get_value,
-	.set_value = cros_rtc_npcx_set_value,
-	.get_alarm = cros_rtc_npcx_get_alarm,
-	.set_alarm = cros_rtc_npcx_set_alarm,
-	.reset_alarm = cros_rtc_npcx_reset_alarm,
-};
-
-static int cros_rtc_npcx_init(const struct device *dev)
-{
-	const struct cros_rtc_npcx_config *config = DRV_CONFIG(dev);
-	struct cros_rtc_npcx_data *data = DRV_DATA(dev);
-
-	/* Initialize the miwu input and its callback for monotonic counter */
-	npcx_miwu_init_dev_callback(&data->miwu_mtc_cb, &config->mtc_alarm,
-				    counter_npcx_isr, dev);
-	npcx_miwu_manage_dev_callback(&data->miwu_mtc_cb, true);
-
-	/*
-	 * Configure the monotonic counter wake-up event triggered from a rising
-	 * edge on its signal.
-	 */
-	npcx_miwu_interrupt_configure(&config->mtc_alarm, NPCX_MIWU_MODE_EDGE,
-				      NPCX_MIWU_TRIG_HIGH);
-
-	return 0;
-}
-
-static const struct cros_rtc_npcx_config cros_rtc_npcx_cfg_0 = {
-	.base = DT_INST_REG_ADDR(0),
-	.mtc_alarm = NPCX_DT_WUI_ITEM_BY_NAME(0, mtc_alarm)
-};
-
-static struct cros_rtc_npcx_data cros_rtc_npcx_data_0;
-
-DEVICE_DT_INST_DEFINE(0, cros_rtc_npcx_init, /* pm_control_fn= */ NULL,
-		      &cros_rtc_npcx_data_0, &cros_rtc_npcx_cfg_0, POST_KERNEL,
-		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
-		      &cros_rtc_npcx_driver_api);
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
deleted file mode 100644
index 94632947c6..0000000000
--- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT nxp_rtc_pcf85063a
-
-#include <assert.h>
-#include <device.h>
-#include <drivers/cros_rtc.h>
-#include <drivers/gpio.h>
-#include <drivers/i2c.h>
-#include <kernel.h>
-#include <rtc.h>
-#include <soc.h>
-
-#include "nxp_rtc_pcf85063a.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
-
-/* Driver config */
-struct nxp_rtc_pcf85063a_config {
-	const struct device *bus;
-	const uint16_t i2c_addr_flags;
-	const struct gpio_dt_spec gpio_alert;
-};
-
-/* Driver data */
-struct nxp_rtc_pcf85063a_data {
-	const struct device *dev;
-	uint8_t time_reg[NUM_TIMER_REGS];
-	struct gpio_callback gpio_cb;
-	cros_rtc_alarm_callback_t alarm_callback;
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct nxp_rtc_pcf85063a_config *)(dev)->config)
-#define DRV_DATA(dev) ((struct nxp_rtc_pcf85063a_data *)(dev)->data)
-
-/*
- * is_alarm == true: Reads alarm registers SECONDS, MINUTES, HOURS, and DAYS
- * is_alarm == false: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and
- *			MONTHS, YEARS
- */
-static int pcf85063a_read_time_regs(const struct device *dev, bool is_alarm)
-{
-	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	uint8_t start_reg;
-	uint8_t num_reg;
-
-	if (is_alarm) {
-		start_reg = REG_SECOND_ALARM;
-		num_reg = NUM_ALARM_REGS;
-	} else {
-		start_reg = REG_SECONDS;
-		num_reg = NUM_TIMER_REGS;
-	}
-
-	return i2c_burst_read(config->bus,
-		config->i2c_addr_flags, start_reg, data->time_reg, num_reg);
-}
-
-static int pcf85063a_read_reg(const struct device *dev,
-						uint8_t reg, uint8_t *val)
-{
-	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
-
-	return i2c_reg_read_byte(config->bus, config->i2c_addr_flags, reg, val);
-}
-
-/*
- * is_alarm == true: Writes alarm registers SECONDS, MINUTES, HOURS, and DAYS
- * is_alarm == false: Writes time registers SECONDS, MINUTES, HOURS, DAYS, and
- *			MONTHS, YEARS
- */
-static int pcf85063a_write_time_regs(const struct device *dev, bool is_alarm)
-{
-	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	uint8_t tx_buf[NUM_TIMER_REGS];
-	uint8_t start_reg;
-	uint8_t num_reg;
-
-	if (is_alarm) {
-		start_reg = REG_SECOND_ALARM;
-		num_reg = NUM_ALARM_REGS;
-	} else {
-		start_reg = REG_SECONDS;
-		num_reg = NUM_TIMER_REGS;
-	}
-
-	for (int i = 0; i < num_reg; i++) {
-		tx_buf[i] = data->time_reg[i];
-	}
-
-	return i2c_burst_write(config->bus,
-			config->i2c_addr_flags, start_reg, tx_buf, num_reg);
-}
-
-
-static int pcf85063a_write_reg(const struct device *dev,
-						uint8_t reg, uint8_t val)
-{
-	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
-	uint8_t tx_buf[2];
-
-	tx_buf[0] = reg;
-	tx_buf[1] = val;
-
-	return i2c_write(config->bus,
-		tx_buf, sizeof(tx_buf), config->i2c_addr_flags);
-}
-
-/*
- * val bits 7 to 4 - tens place
- * val bits 3 to 0 - ones place
- */
-static int bcd_to_dec(uint8_t val, enum bcd_mask mask)
-{
-	int tens = ((val & mask) >> 4) * 10;
-	int ones = (val & 0xf);
-
-	return tens + ones;
-}
-
-/*
- * val bits 7 to 4 - tens place
- * val bits 3 to 0 - ones place
- */
-static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
-{
-	int tens = val / 10;
-	int ones = val - (tens * 10);
-
-	return ((tens << 4) & mask) | ones;
-}
-
-static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev,
-					uint32_t *value, bool is_alarm)
-{
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	struct calendar_date time;
-	int ret;
-
-	ret = pcf85063a_read_time_regs(dev, is_alarm);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	if (is_alarm) {
-		*value = (bcd_to_dec(data->time_reg[DAYS], DAYS_MASK) *
-				SECS_PER_DAY) +
-			(bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
-	} else {
-		time.year = bcd_to_dec(data->time_reg[YEARS], YEARS_MASK);
-		time.month =
-			bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK);
-		time.day = bcd_to_dec(data->time_reg[DAYS], DAYS_MASK);
-
-		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
-			(bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
-	}
-
-	return ret;
-}
-
-static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev,
-				uint32_t value, bool is_alarm)
-{
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	struct calendar_date time;
-	uint32_t tmp_sec;
-
-	time = sec_to_date(value + SECS_TILL_YEAR_2K);
-
-	if (!is_alarm) {
-		data->time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK);
-		data->time_reg[MONTHS] =
-				dec_to_bcd(time.month, MONTHS_MASK);
-	}
-
-	data->time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK);
-
-	if (is_alarm && data->time_reg[DAYS] == 0) {
-		data->time_reg[DAYS] |= DISABLE_ALARM;
-	}
-
-	value %= SECS_PER_DAY;
-	tmp_sec = value / SECS_PER_HOUR;
-	data->time_reg[HOURS] = dec_to_bcd(tmp_sec, HOURS24_MASK);
-
-	if (is_alarm && data->time_reg[HOURS] == 0) {
-		data->time_reg[HOURS] |= DISABLE_ALARM;
-	}
-
-	value -= (tmp_sec * SECS_PER_HOUR);
-	tmp_sec = value / SECS_PER_MINUTE;
-	data->time_reg[MINUTES] = dec_to_bcd(tmp_sec, MINUTES_MASK);
-
-	if (is_alarm && data->time_reg[MINUTES] == 0) {
-		data->time_reg[MINUTES] |= DISABLE_ALARM;
-	}
-
-	value -= (tmp_sec * SECS_PER_MINUTE);
-	data->time_reg[SECONDS] = dec_to_bcd(value, SECONDS_MASK);
-
-	if (is_alarm && data->time_reg[SECONDS] == 0) {
-		data->time_reg[SECONDS] |= DISABLE_ALARM;
-	}
-
-	return pcf85063a_write_time_regs(dev, is_alarm);
-}
-
-static int nxp_rtc_pcf85063a_configure(const struct device *dev,
-				   cros_rtc_alarm_callback_t callback)
-{
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-
-	if (callback == NULL) {
-		return -EINVAL;
-	}
-
-	data->alarm_callback = callback;
-
-	return 0;
-}
-
-static int nxp_rtc_pcf85063a_get_value(const struct device *dev,
-							uint32_t *value)
-{
-	return nxp_rtc_pcf85063a_read_seconds(dev, value, false);
-}
-
-static int nxp_rtc_pcf85063a_set_value(const struct device *dev, uint32_t value)
-{
-	return nxp_rtc_pcf85063a_write_seconds(dev, value, false);
-}
-
-static int nxp_rtc_pcf85063a_get_alarm(const struct device *dev,
-			uint32_t *seconds, uint32_t *microseconds)
-{
-	*microseconds = 0;
-	return nxp_rtc_pcf85063a_read_seconds(dev, seconds, true);
-}
-
-static int nxp_rtc_pcf85063a_reset_alarm(const struct device *dev)
-{
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	int ret;
-
-	/* Disable alarm interrupt and clear pending alarm flag */
-	ret = pcf85063a_write_reg(dev, REG_CONTROL_2, 0);
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Clear and disable the alarm registers */
-	data->time_reg[SECONDS] = DISABLE_ALARM;
-	data->time_reg[MINUTES] = DISABLE_ALARM;
-	data->time_reg[HOURS] = DISABLE_ALARM;
-	data->time_reg[DAYS] = DISABLE_ALARM;
-
-	return pcf85063a_write_time_regs(dev, true);
-}
-
-static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev,
-			uint32_t seconds, uint32_t microseconds)
-{
-	int ret;
-
-	ARG_UNUSED(microseconds);
-
-	ret = nxp_rtc_pcf85063a_reset_alarm(dev);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = nxp_rtc_pcf85063a_write_seconds(dev, seconds, true);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	return pcf85063a_write_reg(dev, REG_CONTROL_2, ENABLE_ALARM_INTERRUPT);
-}
-
-static void nxp_pcf85063a_isr(const struct device *port,
-				struct gpio_callback *cb, uint32_t pin)
-{
-	struct nxp_rtc_pcf85063a_data *data =
-		CONTAINER_OF(cb, struct nxp_rtc_pcf85063a_data, gpio_cb);
-	const struct device *dev = (const struct device *)data->dev;
-
-	ARG_UNUSED(port);
-	ARG_UNUSED(pin);
-	ARG_UNUSED(cb);
-
-	LOG_DBG("%s", __func__);
-
-	/* Call callback function */
-	if (data->alarm_callback) {
-		data->alarm_callback(dev);
-	}
-}
-
-static const struct cros_rtc_driver_api nxp_rtc_pcf85063a_driver_api = {
-	.configure = nxp_rtc_pcf85063a_configure,
-	.get_value = nxp_rtc_pcf85063a_get_value,
-	.set_value = nxp_rtc_pcf85063a_set_value,
-	.get_alarm = nxp_rtc_pcf85063a_get_alarm,
-	.set_alarm = nxp_rtc_pcf85063a_set_alarm,
-	.reset_alarm = nxp_rtc_pcf85063a_reset_alarm,
-};
-
-static int nxp_rtc_pcf85063a_init(const struct device *dev)
-{
-	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
-	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
-	uint8_t val;
-	int ret;
-
-	if (!device_is_ready(config->bus)) {
-		LOG_ERR("Device %s is not ready", config->bus->name);
-		return -ENODEV;
-	}
-
-	/*
-	 * Read Control_1 register. For normal operation,
-	 * the values should be as follows:
-	 *	Bit 7 (external clock test mode)    : (0) normal mode
-	 *	Bit 6 (unused)                      : (0)
-	 *	Bit 5 (STOP bit)                    : (0) RTC clock runs
-	 *	BIT 4 (software reset)              : (0) no software reset
-	 *	BIT 3 (unused)                      : (0)
-	 *	BIT 2 (correction interrupt enable) : (0) no correction
-	 *	                                          interrupt generated
-	 *	BIT 1 (12 or 24-hour mode)          : (0) 24-hour mode
-	 *	BIT 0 (internal oscillator capacitor: (0) 7pF
-	 */
-	ret = pcf85063a_read_reg(dev, REG_CONTROL_1, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	if (val != CONTROL_1_DEFAULT_VALUE) {
-		/* PCF85063A is not initialized, so send soft reset */
-		ret = pcf85063a_write_reg(dev, REG_CONTROL_1, SOFT_RESET);
-
-		if (ret < 0) {
-			return ret;
-		}
-	}
-
-	/*
-	 * Read Seconds register and check if oscillator is stopped.
-	 * If so, clear the bit.
-	 */
-	ret = pcf85063a_read_reg(dev, REG_SECONDS, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	if (val & OS_BIT) {
-		/* Oscillator stop bit is set, clear it. */
-		val &= ~OS_BIT;
-		ret = pcf85063a_write_reg(dev, REG_SECONDS, val);
-
-		if (ret < 0) {
-			return ret;
-		}
-	}
-
-	nxp_rtc_pcf85063a_reset_alarm(dev);
-
-	/* Configure GPIO interrupt pin for PCF85063A alarm pin */
-
-	if (!device_is_ready(config->gpio_alert.port)) {
-		LOG_ERR("Alert GPIO device not ready");
-		return -ENODEV;
-	}
-
-	ret = gpio_pin_configure_dt(&config->gpio_alert, GPIO_INPUT);
-
-	if (ret < 0) {
-		LOG_ERR("Could not configure RTC alert pin");
-		return ret;
-	}
-
-	gpio_init_callback(&data->gpio_cb,
-			nxp_pcf85063a_isr, BIT(config->gpio_alert.pin));
-
-	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
-
-	if (ret < 0) {
-		LOG_ERR("Could not set RTC alert pin callback");
-		return ret;
-	}
-
-	data->dev = dev;
-
-	return gpio_pin_interrupt_configure_dt(&config->gpio_alert,
-					       GPIO_INT_EDGE_FALLING);
-}
-
-#define PCF85063A_INT_GPIOS \
-	DT_PHANDLE_BY_IDX(DT_NODELABEL(pcf85063a), int_gpios, 0)
-
-/*
- * dt_flags is a uint8_t type.  However, for platform/ec
- * the GPIO flags in the devicetree are expanded past 8 bits
- * to support the INPUT/OUTPUT and PULLUP/PULLDOWN properties.
- * Cast back to a gpio_dt_flags to compile, discarding the bits
- * that are not supported by the Zephyr GPIO API.
- */
-#define CROS_EC_GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx)                \
-	{                                                                  \
-		.port =                                                    \
-		DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx)),    \
-		.pin = DT_GPIO_PIN_BY_IDX(node_id, prop, idx),             \
-		.dt_flags =                                                \
-		(gpio_dt_flags_t)DT_GPIO_FLAGS_BY_IDX(node_id, prop, idx), \
-	}
-
-static const struct nxp_rtc_pcf85063a_config nxp_rtc_pcf85063a_cfg_0 = {
-	.bus = DEVICE_DT_GET(DT_INST_BUS(0)),
-	.i2c_addr_flags = DT_INST_REG_ADDR(0),
-	.gpio_alert =
-		CROS_EC_GPIO_DT_SPEC_GET_BY_IDX(PCF85063A_INT_GPIOS, gpios, 0)
-};
-
-static struct nxp_rtc_pcf85063a_data nxp_rtc_pcf85063a_data_0;
-
-DEVICE_DT_INST_DEFINE(0, nxp_rtc_pcf85063a_init, /* pm_control_fn= */ NULL,
-		      &nxp_rtc_pcf85063a_data_0, &nxp_rtc_pcf85063a_cfg_0,
-		      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
-		      &nxp_rtc_pcf85063a_driver_api);
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
deleted file mode 100644
index dc4fcd24fc..0000000000
--- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_RTC_PCF85063A_H
-#define __CROS_EC_RTC_PCF85063A_H
-
-#define PCF85063A_REG_NUM       18
-#define SOFT_RESET              0x58
-#define CONTROL_1_DEFAULT_VALUE 0
-#define OS_BIT                  0x80
-#define DISABLE_ALARM           0x80
-#define ENABLE_ALARM_INTERRUPT	0x80
-#define RTC_STOP_CLOCKS		0x20
-#define RTC_START_CLOCKS	0x00
-
-#define NUM_TIMER_REGS       7
-#define NUM_ALARM_REGS       4
-
-#define REG_CONTROL_1        0x00
-#define REG_CONTROL_2        0x01
-#define REG_OFFSET           0x02
-#define REG_RAM_BYTE         0x03
-#define REG_SECONDS          0x04
-#define REG_MINUTES          0x05
-#define REG_HOURS            0x06
-#define REG_DAYS             0x07
-#define REG_WEEKDAYS         0x08
-#define REG_MONTHS           0x09
-#define REG_YEARS            0x0a
-#define REG_SECOND_ALARM     0x0b
-#define REG_MINUTE_ALARM     0x0c
-#define REG_HOUR_ALARM       0x0d
-#define REG_DAY_ALARM        0x0e
-#define REG_WEEKDAY_ALARM    0x0f
-#define REG_TIMER_VALUE      0x10
-#define REG_TIMER_MODE       0x11
-
-/* Macros for indexing time_reg buffer */
-#define SECONDS           0
-#define MINUTES           1
-#define HOURS             2
-#define DAYS              3
-#define WEEKDAYS          4
-#define MONTHS            5
-#define YEARS             6
-
-enum bcd_mask {
-	SECONDS_MASK = 0x70,
-	MINUTES_MASK = 0x70,
-	HOURS24_MASK = 0x30,
-	DAYS_MASK    = 0x30,
-	MONTHS_MASK  = 0x10,
-	YEARS_MASK   = 0xf0
-};
-
-#endif /* __CROS_EC_RTC_PCF85063A_H */
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
deleted file mode 100644
index bbe76f5286..0000000000
--- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT renesas_rtc_idt1337ag
-
-#include <assert.h>
-#include <device.h>
-#include <drivers/cros_rtc.h>
-#include <drivers/gpio.h>
-#include <drivers/i2c.h>
-#include <kernel.h>
-#include <rtc.h>
-#include <soc.h>
-
-#include "renesas_rtc_idt1337ag.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(cros_rtc, LOG_LEVEL_ERR);
-
-/* Driver config */
-struct renesas_rtc_idt1337ag_config {
-	const struct device *bus;
-	const uint16_t i2c_addr_flags;
-	const struct gpio_dt_spec gpio_alert;
-};
-
-/* Driver data */
-struct renesas_rtc_idt1337ag_data {
-	const struct device *dev;
-	struct gpio_callback gpio_cb;
-	cros_rtc_alarm_callback_t alarm_callback;
-};
-
-enum timer_type {
-	RTC_TIMER,
-	ALARM_TIMER,
-};
-
-/*
- * type == ALARM_TIMER: Reads alarm registers SECONDS, MINUTES, HOURS, and DAYS
- * type == RTC_TIMER: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and
- *			MONTHS, YEARS
- */
-static int idt1337ag_read_time_regs(const struct device *dev,
-				    uint8_t *time_reg, enum timer_type type)
-{
-	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
-	uint8_t start_reg;
-	uint8_t num_reg;
-
-	if (type == ALARM_TIMER) {
-		start_reg = REG_SECOND_ALARM1;
-		num_reg = NUM_ALARM_REGS;
-	} else {
-		start_reg = REG_SECONDS;
-		num_reg = NUM_TIMER_REGS;
-	}
-
-	return i2c_burst_read(config->bus,
-		config->i2c_addr_flags, start_reg, time_reg, num_reg);
-}
-
-static int idt1337ag_read_reg(const struct device *dev,
-			      uint8_t reg, uint8_t *val)
-{
-	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
-
-	return i2c_reg_read_byte(config->bus, config->i2c_addr_flags, reg, val);
-}
-
-/*
- * type == ALARM_TIMER: Writes alarm registers SECONDS, MINUTES, HOURS, and DAYS
- * type == RTC_TIMER: Writes time registers SECONDS, MINUTES, HOURS, DAYS, and
- *			MONTHS, YEARS
- */
-static int idt1337ag_write_time_regs(const struct device *dev,
-				     uint8_t *time_reg, enum timer_type type)
-{
-	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
-	uint8_t start_reg;
-	uint8_t num_reg;
-
-	if (type == ALARM_TIMER) {
-		/*
-		 * Register 0x0A bit 6 determines if the DAY(1b) or DATE(0b)
-		 * alarm is selected.
-		 * Select the DAY alarm
-		 */
-		time_reg[DAYS] |= SELECT_DAYS_ALARM;
-
-		start_reg = REG_SECOND_ALARM1;
-		num_reg = NUM_ALARM_REGS;
-	} else {
-		start_reg = REG_SECONDS;
-		num_reg = NUM_TIMER_REGS;
-	}
-
-	return i2c_burst_write(config->bus,
-			config->i2c_addr_flags, start_reg, time_reg, num_reg);
-}
-
-static int idt1337ag_write_reg(const struct device *dev,
-			       uint8_t reg, uint8_t val)
-{
-	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
-	uint8_t tx_buf[2];
-
-	tx_buf[0] = reg;
-	tx_buf[1] = val;
-
-	return i2c_write(config->bus,
-		tx_buf, sizeof(tx_buf), config->i2c_addr_flags);
-}
-
-/*
- * val bits 7 to 4 - tens place
- * val bits 3 to 0 - ones place
- */
-static int bcd_to_dec(uint8_t val, enum bcd_mask mask)
-{
-	int tens = ((val & mask) >> 4) * 10;
-	int ones = (val & 0xf);
-
-	return tens + ones;
-}
-
-/*
- * val bits 7 to 4 - tens place
- * val bits 3 to 0 - ones place
- */
-static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
-{
-	int tens = val / 10;
-	int ones = val - (tens * 10);
-
-	return ((tens << 4) & mask) | ones;
-}
-
-static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev,
-					uint32_t *value, enum timer_type type)
-{
-	uint8_t time_reg[NUM_TIMER_REGS];
-	struct calendar_date time;
-	int ret;
-
-	ret = idt1337ag_read_time_regs(dev, time_reg, type);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	if (type == ALARM_TIMER) {
-		*value = (bcd_to_dec(time_reg[DAYS], DAYS_MASK) *
-				SECS_PER_DAY) +
-			(bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
-	} else {
-		time.year = bcd_to_dec(time_reg[YEARS], YEARS_MASK);
-		time.month = bcd_to_dec(time_reg[MONTHS], MONTHS_MASK);
-		time.day = bcd_to_dec(time_reg[DAYS], DAYS_MASK);
-
-		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
-			(bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
-	}
-
-	return ret;
-}
-
-static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev,
-					uint32_t value, enum timer_type type)
-{
-	uint8_t time_reg[NUM_TIMER_REGS];
-	struct calendar_date time;
-	uint32_t tmp_sec;
-
-	time = sec_to_date(value + SECS_TILL_YEAR_2K);
-
-	if (type == RTC_TIMER) {
-		time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK);
-		time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK);
-	}
-
-	time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK);
-
-	value %= SECS_PER_DAY;
-	tmp_sec = value / SECS_PER_HOUR;
-	time_reg[HOURS] = dec_to_bcd(tmp_sec, HOURS24_MASK);
-
-	value -= (tmp_sec * SECS_PER_HOUR);
-	tmp_sec = value / SECS_PER_MINUTE;
-	time_reg[MINUTES] = dec_to_bcd(tmp_sec, MINUTES_MASK);
-
-	value -= (tmp_sec * SECS_PER_MINUTE);
-	time_reg[SECONDS] = dec_to_bcd(value, SECONDS_MASK);
-
-	return idt1337ag_write_time_regs(dev, time_reg, type);
-}
-
-static int renesas_rtc_idt1337ag_configure(const struct device *dev,
-				   cros_rtc_alarm_callback_t callback)
-{
-	struct renesas_rtc_idt1337ag_data *data = dev->data;
-
-	if (callback == NULL) {
-		return -EINVAL;
-	}
-
-	data->alarm_callback = callback;
-
-	return 0;
-}
-
-static int renesas_rtc_idt1337ag_get_value(const struct device *dev,
-					   uint32_t *value)
-{
-	return renesas_rtc_idt1337ag_read_seconds(dev, value, RTC_TIMER);
-}
-
-static int renesas_rtc_idt1337ag_set_value(const struct device *dev,
-					   uint32_t value)
-{
-	return renesas_rtc_idt1337ag_write_seconds(dev, value, RTC_TIMER);
-}
-
-static int renesas_rtc_idt1337ag_get_alarm(const struct device *dev,
-				uint32_t *seconds, uint32_t *microseconds)
-{
-	*microseconds = 0;
-	return renesas_rtc_idt1337ag_read_seconds(dev, seconds, ALARM_TIMER);
-}
-
-static int renesas_rtc_idt1337ag_reset_alarm(const struct device *dev)
-{
-	uint8_t time_reg[NUM_ALARM_REGS];
-	int ret;
-	uint8_t val;
-
-	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Disable alarm interrupt and clear pending alarm flag */
-	val &= ~CONTROL_A1IE;
-	ret = idt1337ag_write_reg(dev, REG_CONTROL, val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Clear alarm1 flag if set */
-	ret = idt1337ag_read_reg(dev, REG_STATUS, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Clear the alarm1 and alarm2 flag */
-	val &= ~(STATUS_A1F | STATUS_A2F);
-	ret = idt1337ag_write_reg(dev, REG_STATUS, val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Clear and disable the alarm registers */
-	time_reg[SECONDS] = DISABLE_ALARM;
-	time_reg[MINUTES] = DISABLE_ALARM;
-	time_reg[HOURS] = DISABLE_ALARM;
-	time_reg[DAYS] = DISABLE_ALARM;
-
-	return idt1337ag_write_time_regs(dev, time_reg, ALARM_TIMER);
-}
-
-static int renesas_rtc_idt1337ag_set_alarm(const struct device *dev,
-				uint32_t seconds, uint32_t microseconds)
-{
-	int ret;
-	uint8_t val;
-
-	ARG_UNUSED(microseconds);
-
-	ret = renesas_rtc_idt1337ag_reset_alarm(dev);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = renesas_rtc_idt1337ag_write_seconds(dev, seconds, ALARM_TIMER);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
-	if (ret < 0) {
-		return ret;
-	}
-
-	val |= CONTROL_A1IE;
-	idt1337ag_write_reg(dev, REG_CONTROL, val);
-
-	return 0;
-}
-
-static void renesas_rtc_idt1337ag_isr(const struct device *port,
-				      struct gpio_callback *cb, uint32_t pin)
-{
-	struct renesas_rtc_idt1337ag_data *data =
-		CONTAINER_OF(cb, struct renesas_rtc_idt1337ag_data, gpio_cb);
-	const struct device *dev = data->dev;
-
-	ARG_UNUSED(port);
-	ARG_UNUSED(pin);
-	ARG_UNUSED(cb);
-
-	LOG_DBG("%s", __func__);
-
-	/* Call callback function */
-	if (data->alarm_callback) {
-		data->alarm_callback(dev);
-	}
-}
-
-static const struct cros_rtc_driver_api renesas_rtc_idt1337ag_driver_api = {
-	.configure = renesas_rtc_idt1337ag_configure,
-	.get_value = renesas_rtc_idt1337ag_get_value,
-	.set_value = renesas_rtc_idt1337ag_set_value,
-	.get_alarm = renesas_rtc_idt1337ag_get_alarm,
-	.set_alarm = renesas_rtc_idt1337ag_set_alarm,
-	.reset_alarm = renesas_rtc_idt1337ag_reset_alarm,
-};
-
-static int renesas_rtc_idt1337ag_init(const struct device *dev)
-{
-	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
-	struct renesas_rtc_idt1337ag_data *data = dev->data;
-	uint8_t val;
-	int ret;
-
-	if (!device_is_ready(config->bus)) {
-		LOG_ERR("Device %s is not ready", config->bus->name);
-		return -ENODEV;
-	}
-
-	/*
-	 * Read Control register. For normal operation,
-	 * the values should be as follows:
-	 *	Bit 7 (enable oscillator) : (0) normal mode
-	 *	Bit 6 (unused)            : (0)
-	 *	Bit 5 (unused)            : (0)
-	 *	BIT 4 (RS2)               : (0) Not used when INTCN == 1
-	 *	BIT 3 (RS1)               : (0) Not used when INTCN == 1
-	 *	BIT 2 (INTCN)             : (1) a match between the timekeeping
-	 *	                                registers and the alarm 1
-	 *	                                registers activate the INTA pin
-	 *	BIT 1 (A2IE)              : (0) Alarm 2 is not used
-	 *	BIT 0 (A1IE)              : (1) Enables Alarm 1
-	 */
-	ret = idt1337ag_read_reg(dev, REG_CONTROL, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Enable IDT1337AG oscillator */
-	val &= ~CONTROL_EOSC;
-
-	/* Disable Alarm 2 */
-	val &= ~CONTROL_A2IE;
-
-	/* Alarm 1 assert INTA pin */
-	val |= CONTROL_INTCN;
-
-	ret = idt1337ag_write_reg(dev, REG_CONTROL, val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Date register isn't used. Set it to zero */
-	ret = idt1337ag_write_reg(dev, REG_DATE, 0);
-
-	/* Make sure the oscillator is running */
-	ret = idt1337ag_read_reg(dev, REG_STATUS, &val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Clear IDT1337AG oscillator not running flag */
-	val &= ~STATUS_OSF;
-
-	/* Clear Alarm 2 flag */
-	val &= ~STATUS_A2F;
-
-	ret = idt1337ag_write_reg(dev, REG_STATUS, val);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	renesas_rtc_idt1337ag_reset_alarm(dev);
-
-	/* Disable Alarm2 */
-	idt1337ag_write_reg(dev, REG_MINUTE_ALARM2, DISABLE_ALARM);
-	idt1337ag_write_reg(dev, REG_HOUR_ALARM2, DISABLE_ALARM);
-	idt1337ag_write_reg(dev, REG_DAY_ALARM2, DISABLE_ALARM);
-
-	/* Configure GPIO interrupt pin for IDT1337AG alarm pin */
-
-	if (!device_is_ready(config->gpio_alert.port)) {
-		LOG_ERR("Alert GPIO device not ready");
-		return -ENODEV;
-	}
-
-	ret = gpio_pin_configure_dt(&config->gpio_alert, GPIO_INPUT);
-
-	if (ret < 0) {
-		LOG_ERR("Could not configure RTC alert pin");
-		return ret;
-	}
-
-	gpio_init_callback(&data->gpio_cb,
-			renesas_rtc_idt1337ag_isr, BIT(config->gpio_alert.pin));
-
-	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
-
-	if (ret < 0) {
-		LOG_ERR("Could not set RTC alert pin callback");
-		return ret;
-	}
-
-	data->dev = dev;
-
-	return gpio_pin_interrupt_configure_dt(&config->gpio_alert,
-					       GPIO_INT_EDGE_FALLING);
-}
-
-#define IDT1337AG_INT_GPIOS \
-	DT_PHANDLE_BY_IDX(DT_NODELABEL(idt1337ag), int_gpios, 0)
-
-/*
- * dt_flags is a uint8_t type.  However, for platform/ec
- * the GPIO flags in the devicetree are expanded past 8 bits
- * to support the INPUT/OUTPUT and PULLUP/PULLDOWN properties.
- * Cast back to a gpio_dt_flags to compile, discarding the bits
- * that are not supported by the Zephyr GPIO API.
- */
-#define CROS_EC_GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx)                \
-	{                                                                  \
-		.port =                                                    \
-		DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx)),    \
-		.pin = DT_GPIO_PIN_BY_IDX(node_id, prop, idx),             \
-		.dt_flags =                                                \
-		(gpio_dt_flags_t)DT_GPIO_FLAGS_BY_IDX(node_id, prop, idx), \
-	}
-
-static const struct renesas_rtc_idt1337ag_config renesas_rtc_idt1337ag_cfg_0 = {
-	.bus = DEVICE_DT_GET(DT_INST_BUS(0)),
-	.i2c_addr_flags = DT_INST_REG_ADDR(0),
-	.gpio_alert =
-		CROS_EC_GPIO_DT_SPEC_GET_BY_IDX(IDT1337AG_INT_GPIOS, gpios, 0)
-};
-
-static struct renesas_rtc_idt1337ag_data renesas_rtc_idt1337ag_data_0;
-
-DEVICE_DT_INST_DEFINE(0, renesas_rtc_idt1337ag_init, /* pm_control_fn= */ NULL,
-		      &renesas_rtc_idt1337ag_data_0,
-		      &renesas_rtc_idt1337ag_cfg_0,
-		      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
-		      &renesas_rtc_idt1337ag_driver_api);
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
deleted file mode 100644
index 3296f80992..0000000000
--- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_RTC_IDT1337AG_H
-#define __CROS_EC_RTC_IDT1337AG_H
-
-/* Setting bit 6 of register 0Ah selects the DAY as alarm source */
-#define SELECT_DAYS_ALARM  0x40
-#define DISABLE_ALARM      0x80
-
-#define CONTROL_A1IE       BIT(0)
-#define CONTROL_A2IE       BIT(1)
-#define CONTROL_INTCN      BIT(2)
-#define CONTROL_EOSC       BIT(7)
-
-#define STATUS_A1F         BIT(0)
-#define STATUS_A2F         BIT(1)
-#define STATUS_OSF         BIT(7)
-
-#define NUM_TIMER_REGS       7
-#define NUM_ALARM_REGS       4
-
-#define REG_SECONDS        0x00
-#define REG_MINUTES        0x01
-#define REG_HOURS          0x02
-#define REG_DAYS           0x03
-#define REG_DATE           0x04
-#define REG_MONTHS         0x05
-#define REG_YEARS          0x06
-#define REG_SECOND_ALARM1  0x07
-#define REG_MINUTE_ALARM1  0x08
-#define REG_HOUR_ALARM1    0x09
-#define REG_DAY_ALARM1     0x0a
-#define REG_MINUTE_ALARM2  0x0b
-#define REG_HOUR_ALARM2    0x0c
-#define REG_DAY_ALARM2     0x0d
-#define REG_CONTROL        0x0e
-#define REG_STATUS         0x0f
-
-/* Macros for indexing time_reg buffer */
-#define SECONDS           0
-#define MINUTES           1
-#define HOURS             2
-#define DAYS              3
-#define DATE              4
-#define MONTHS            5
-#define YEARS             6
-
-enum bcd_mask {
-	SECONDS_MASK = 0x70,
-	MINUTES_MASK = 0x70,
-	HOURS24_MASK = 0x30,
-	DAYS_MASK    = 0x00,
-	MONTHS_MASK  = 0x10,
-	YEARS_MASK   = 0xf0
-};
-
-#endif /* __CROS_EC_RTC_IDT1337AG_H */
diff --git a/zephyr/drivers/cros_shi/CMakeLists.txt b/zephyr/drivers/cros_shi/CMakeLists.txt
deleted file mode 100644
index f0b3c8bb5a..0000000000
--- a/zephyr/drivers/cros_shi/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_CROS_SHI_IT8XXX2	cros_shi_it8xxx2.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX	cros_shi_npcx.c)
diff --git a/zephyr/drivers/cros_shi/Kconfig b/zephyr/drivers/cros_shi/Kconfig
deleted file mode 100644
index 0baa8a5d80..0000000000
--- a/zephyr/drivers/cros_shi/Kconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig CROS_SHI_NPCX
-	bool "Nuvoton NPCX Serial Host Interface driver for the Zephyr shim"
-	depends on SOC_FAMILY_NPCX
-	help
-	  This option enables Serial Host Interface driver for the NPCX family
-	  of processors. This is used for host-command communication on the
-	  platform which AP is ARM-based SoC.
-
-if CROS_SHI_NPCX
-config CROS_SHI_MAX_REQUEST
-	hex "Max data size for the version 3 request packet"
-	default 0x220
-	help
-	  This option indicates maximum data size for a version 3 request
-	  packet. This must be big enough to handle a request header of host
-	  command, flash write offset/size, and 512 bytes of flash data.
-
-config CROS_SHI_MAX_RESPONSE
-	hex "Max data size for the version 3 response packet"
-	default 0x220
-	help
-	  This option indicates maximum data size for a version 3 response
-	  packet. This must be big enough to handle a response header of host
-	  command, flash read offset/size, and 512 bytes of flash data.
-
-config CROS_SHI_NPCX_DEBUG
-	bool "Enable SHI debug"
-	help
-	  print the debug messages for SHI module
-
-endif # CROS_SHI_NPCX
-
-config CROS_SHI_IT8XXX2
-	bool "ITE it81202 spi host interface driver for Zephyr"
-	depends on SOC_FAMILY_RISCV_ITE && AP_ARM
-	default y if PLATFORM_EC_HOSTCMD
-	help
-	  This option enables spi host interface driver which is required to
-	  communicate with the EC when the CPU is the ARM processor.
-
-if CROS_SHI_IT8XXX2
-
-config CROS_SHI_IT8XXX2_INIT_PRIORITY
-	int "cros_shi it8xxx2 initialization priority"
-	default 52
-	help
-	  This sets the it8xxx2 cros_shi driver initialization priority.
-	  In the GPIO shim, the alt function of SHI will be configured
-	  as GPIO input pin. So the priority of cros_shi driver must be
-	  lower than CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY, and
-	  configuration these pins to alt function of SHI.
-
-endif # CROS_SHI_IT8XXX2
diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
deleted file mode 100644
index 522d48ff09..0000000000
--- a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT ite_it8xxx2_cros_shi
-
-#include <device.h>
-#include <errno.h>
-#include <init.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc_dt.h>
-#include <drivers/pinmux.h>
-#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
-
-#include "chipset.h"
-#include "console.h"
-#include "host_command.h"
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
-
-LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_ERR);
-
-#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg * const)(dev)->config)
-
-/*
- * Strcture cros_shi_it8xxx2_cfg is about the setting of SHI,
- * this config will be used at initial time
- */
-struct cros_shi_it8xxx2_cfg {
-	/* Pinmux control group */
-	const struct device *pinctrls;
-	/* GPIO pin */
-	uint8_t pin;
-	/* Alternate function */
-	uint8_t alt_fun;
-};
-
-#define SPI_RX_MAX_FIFO_SIZE 256
-#define SPI_TX_MAX_FIFO_SIZE 256
-
-#define EC_SPI_PREAMBLE_LENGTH 4
-#define EC_SPI_PAST_END_LENGTH 4
-
-/* Max data size for a version 3 request/response packet. */
-#define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
-
-static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	/* This is the byte which matters */
-	EC_SPI_FRAME_START,
-};
-
-/* Store read and write data buffer */
-static uint8_t in_msg[SPI_RX_MAX_FIFO_SIZE] __aligned(4);
-static uint8_t out_msg[SPI_TX_MAX_FIFO_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet spi_packet;
-
-enum shi_state_machine {
-	/* Ready to receive next request */
-	SPI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SPI_STATE_RECEIVING,
-	/* Processing request */
-	SPI_STATE_PROCESSING,
-	/* Received bad data */
-	SPI_STATE_RX_BAD,
-
-	SPI_STATE_COUNT,
-};
-
-static enum shi_state_machine shi_state;
-
-static const int spi_response_state[] = {
-	[SPI_STATE_READY_TO_RECV] = EC_SPI_OLD_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
-};
-BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
-
-static void spi_set_state(int state)
-{
-	/* SPI slave state machine */
-	shi_state = state;
-	/* Response spi slave state */
-	IT83XX_SPI_SPISRDR = spi_response_state[state];
-}
-
-static void reset_rx_fifo(void)
-{
-	/* End Rx FIFO access */
-	IT83XX_SPI_TXRXFAR = 0x00;
-	/* Rx FIFO reset and count monitor reset */
-	IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR;
-}
-
-/* This routine handles spi received unexcepted data */
-static void spi_bad_received_data(int count)
-{
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	spi_set_state(SPI_STATE_RX_BAD);
-	/* End CPU access Rx FIFO, so it can clock in bytes from AP again. */
-	IT83XX_SPI_TXRXFAR = 0;
-
-	CPRINTS("SPI rx bad data");
-	CPRINTF("in_msg=[");
-	for (int i = 0; i < count; i++)
-		CPRINTF("%02x ", in_msg[i]);
-	CPRINTF("]\n");
-}
-
-static void spi_response_host_data(uint8_t *out_msg_addr, int tx_size)
-{
-	/*
-	 * Protect sequence of filling response packet for host.
-	 * This will ensure CPU access FIFO is disabled at SPI end interrupt no
-	 * matter the interrupt is triggered before or after the sequence.
-	 */
-	unsigned int key = irq_lock();
-
-	if (shi_state == SPI_STATE_PROCESSING) {
-		/* Tx FIFO reset and count monitor reset */
-		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR;
-		/* CPU Tx FIFO1 and FIFO2 access */
-		IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA;
-
-		for (int i = 0; i < tx_size; i += 4) {
-			/* Write response data from out_msg buffer to Tx FIFO */
-			IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(out_msg_addr + i);
-		}
-
-		/*
-		 * After writing data to Tx FIFO is finished, this bit will
-		 * be to indicate the SPI slave controller.
-		 */
-		IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS;
-		/* End Tx FIFO access */
-		IT83XX_SPI_TXRXFAR = 0;
-		/* SPI slave read Tx FIFO */
-		IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF;
-	}
-
-	irq_unlock(key);
-}
-
-/*
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command when it completes.
- *
- */
-static void spi_send_response_packet(struct host_packet *pkt)
-{
-	int tx_size;
-
-	if (shi_state != SPI_STATE_PROCESSING) {
-		CPRINTS("The request data is not processing.");
-		return;
-	}
-
-	/* Append our past-end byte, which we reserved space for. */
-	for (int i = 0; i < EC_SPI_PAST_END_LENGTH; i++) {
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
-	}
-
-	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
-
-	/* Transmit the reply */
-	spi_response_host_data(out_msg, tx_size);
-}
-
-/* Store request data from Rx FIFO to in_msg buffer */
-static void spi_host_request_data(uint8_t *in_msg_addr, int count)
-{
-	/* CPU Rx FIFO1 access */
-	IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPURXF1A;
-	/*
-	 * In spi_parse_header, the request data will separate to
-	 * write in_msg buffer so we cannot set CPU to end accessing
-	 * Rx FIFO in this function. We will set IT83XX_SPI_TXRXFAR = 0
-	 * in reset_rx_fifo.
-	 */
-
-	for (int i = 0; i < count; i += 4) {
-		/* Get data from master to buffer */
-		*(uint32_t *)(in_msg_addr + i) = IT83XX_SPI_RXFRDRB0;
-	}
-}
-
-/* Parse header for version of spi-protocol */
-static void spi_parse_header(void)
-{
-	struct ec_host_request *r = (struct ec_host_request *)in_msg;
-
-	/* Store request data from Rx FIFO to in_msg buffer */
-	spi_host_request_data(in_msg, sizeof(*r));
-
-	/* Protocol version 3 */
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		int pkt_size;
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg)) {
-			spi_bad_received_data(pkt_size);
-			return;
-		}
-
-		/* Store request data from Rx FIFO to in_msg buffer */
-		spi_host_request_data(in_msg + sizeof(*r),
-				      pkt_size - sizeof(*r));
-
-		/* Set up parameters for host request */
-		spi_packet.send_response = spi_send_response_packet;
-		spi_packet.request = in_msg;
-		spi_packet.request_temp = NULL;
-		spi_packet.request_max = sizeof(in_msg);
-		spi_packet.request_size = pkt_size;
-
-		/* Response must start with the preamble */
-		memcpy(out_msg, out_preamble, sizeof(out_preamble));
-
-		spi_packet.response = out_msg + EC_SPI_PREAMBLE_LENGTH;
-		/* Reserve space for frame start and trailing past-end byte */
-		spi_packet.response_max = SPI_MAX_RESPONSE_SIZE;
-		spi_packet.response_size = 0;
-		spi_packet.driver_result = EC_RES_SUCCESS;
-
-		/* Go to common-layer to handle request */
-		host_packet_receive(&spi_packet);
-	} else {
-		/* Invalid version number */
-		CPRINTS("Invalid version number");
-		spi_bad_received_data(1);
-	}
-}
-
-static void shi_ite_int_handler(const void *arg)
-{
-	/*
-	 * The status of SPI end detection interrupt bit is set, it
-	 * means that host command parse has been completed and AP
-	 * has received the last byte which is EC_SPI_PAST_END from
-	 * EC responded data, then AP ended the transaction.
-	 */
-	if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) {
-		/* Disable CPU access Rx FIFO to clock in data from AP again */
-		IT83XX_SPI_TXRXFAR = 0;
-		/* Ready to receive */
-		spi_set_state(SPI_STATE_READY_TO_RECV);
-		/*
-		 * Once there is no SPI active, enable idle task deep
-		 * sleep bit of SPI in S3 or lower.
-		 * TODO(b:185176098): enable_sleep(SLEEP_MASK_SPI);
-		 */
-
-		/* CS# is deasserted, so write clear all slave status */
-		IT83XX_SPI_ISR = 0xff;
-	}
-	/*
-	 * The status of Rx valid length interrupt bit is set that
-	 * indicates reached target count(IT83XX_SPI_FTCB1R,
-	 * IT83XX_SPI_FTCB0R) and the length field of the host
-	 * requested data.
-	 */
-	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
-		/* write clear slave status */
-		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
-		/* Move to processing state */
-		spi_set_state(SPI_STATE_PROCESSING);
-		/* Parse header for version of spi-protocol */
-		spi_parse_header();
-	}
-}
-
-void spi_event(enum gpio_signal signal)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		/* Move to processing state */
-		spi_set_state(SPI_STATE_PROCESSING);
-		/* Disable idle task deep sleep bit of SPI in S0. */
-		/* TODO(b:185176098): disable_sleep(SLEEP_MASK_SPI); */
-	}
-}
-
-/*
- * SHI init priority is behind CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY to
- * overwrite GPIO_INPUT setting of spi chip select pin.
- */
-static int cros_shi_ite_init(const struct device *dev)
-{
-	const struct cros_shi_it8xxx2_cfg *const config = DRV_CONFIG(dev);
-	/* Set FIFO data target count */
-	struct ec_host_request cmd_head;
-
-	/*
-	 * Target count means the size of host request.
-	 * And plus extra 4 bytes because the CPU accesses FIFO base on
-	 * word. If host requested data length is one byte, we need to
-	 * align the data length to 4 bytes.
-	 */
-	int target_count = sizeof(cmd_head) + 4;
-	/* Offset of data_len member of host request. */
-	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
-
-	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
-	IT83XX_SPI_FTCB0R = target_count & 0xff;
-	/*
-	 * The register setting can capture the length field of host
-	 * request.
-	 */
-	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
-	IT83XX_SPI_TCCB0 = offset & 0xff;
-
-	/*
-	 * Memory controller configuration register 3.
-	 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
-	 */
-	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
-	/* Set unused blocked byte */
-	IT83XX_SPI_HPR2 = 0x00;
-	/* Rx valid length interrupt enabled */
-	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
-	/*
-	 * General control register2
-	 * bit4 : Rx FIFO2 will not be overwrited once it's full.
-	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
-	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
-	 */
-	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-				| IT83XX_SPI_RXFAR;
-	/*
-	 * Interrupt mask register (0b:Enable, 1b:Mask)
-	 * bit5 : Rx byte reach interrupt mask
-	 * bit2 : SPI end detection interrupt mask
-	 */
-	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
-	/* Reset fifo and prepare to for next transaction */
-	reset_rx_fifo();
-	/* Ready to receive */
-	spi_set_state(SPI_STATE_READY_TO_RECV);
-	/* Interrupt status register(write one to clear) */
-	IT83XX_SPI_ISR = 0xff;
-	/* SPI slave controller enable (after settings are ready) */
-	IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN;
-
-	/* Ensure spi chip select alt function is enabled. */
-	for (int i = 0; i < DT_INST_PROP_LEN(0, pinctrl_0); i++) {
-		pinmux_pin_set(config[i].pinctrls, config[i].pin,
-			       config[i].alt_fun);
-	}
-
-	/* Enable SPI slave interrupt */
-	IRQ_CONNECT(DT_INST_IRQN(0), 0, shi_ite_int_handler, 0, 0);
-	irq_enable(DT_INST_IRQN(0));
-
-	/* Enable SPI chip select pin interrupt */
-	gpio_enable_interrupt(GPIO_SPI0_CS);
-
-	return 0;
-}
-
-static const struct cros_shi_it8xxx2_cfg cros_shi_cfg[] =
-	IT8XXX2_DT_ALT_ITEMS_LIST(0);
-
-#if CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY <= \
-	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY
-#error "CROS_SHI must initialize after the GPIOs initialization"
-#endif
-DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL,
-		      NULL, &cros_shi_cfg, POST_KERNEL,
-		      CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY,
-		      NULL);
-
-/* Get protocol information */
-enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
-	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     spi_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c
deleted file mode 100644
index a290e320fc..0000000000
--- a/zephyr/drivers/cros_shi/cros_shi_npcx.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT nuvoton_npcx_cros_shi
-
-#include <arch/arm/aarch32/cortex_m/cmsis.h>
-#include <assert.h>
-#include <dt-bindings/clock/npcx_clock.h>
-#include <drivers/clock_control.h>
-#include <drivers/cros_shi.h>
-#include <drivers/gpio.h>
-#include <logging/log.h>
-#include <kernel.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-
-#include "host_command.h"
-#include "soc_miwu.h"
-#include "system.h"
-
-#ifdef CONFIG_CROS_SHI_NPCX_DEBUG
-#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
-#else
-#define DEBUG_CPRINTS(...)
-#define DEBUG_CPRINTF(...)
-#endif
-
-LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_DBG);
-
-#define SHI_NODE DT_NODELABEL(shi)
-#define SHI_VER_CTRL_PH DT_PHANDLE_BY_IDX(SHI_NODE, ver_ctrl, 0)
-#define SHI_VER_CTRL_ALT_FILED(f) DT_PHA_BY_IDX(SHI_VER_CTRL_PH, alts, 0, f)
-
-/* Full output buffer size */
-#define SHI_OBUF_FULL_SIZE 128
-/* Full input buffer size  */
-#define SHI_IBUF_FULL_SIZE 128
-/* Configure the IBUFLVL2 = the size of V3 protocol header */
-#define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
-/* Half output buffer size */
-#define SHI_OBUF_HALF_SIZE (SHI_OBUF_FULL_SIZE / 2)
-/* Half input buffer size */
-#define SHI_IBUF_HALF_SIZE (SHI_IBUF_FULL_SIZE / 2)
-
-/*
- * Timeout to wait for SHI request packet
- *
- * This affects the slowest SPI clock we can support. A delay of 8192 us
- * permits a 512-byte request at 500 KHz, assuming the SPI controller starts
- * sending bytes as soon as it asserts chip select. That's as slow as we would
- * practically want to run the SHI interface, since running it slower
- * significantly impacts firmware update times.
- */
-#define SHI_CMD_RX_TIMEOUT_MS 9
-
-/*
- * The AP blindly clocks back bytes over the SPI interface looking for a
- * framing byte.  So this preamble must always precede the actual response
- * packet.
- */
-#define SHI_OUT_PREAMBLE_LENGTH 2
-
-/*
- * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg
- * buffer.
- */
-#define EC_SPI_PAST_END_LENGTH 1
-/*
- * Space allocation of the frame status byte (EC_SPI_FRAME_START) in the out_msg
- * buffer.
- */
-#define EC_SPI_FRAME_START_LENGTH 1
-
-/*
- * Offset of output parameters needs to account for pad and framing bytes and
- * one last past-end byte at the end so any additional bytes clocked out by
- * the AP will have a known and identifiable value.
- */
-#define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
-
-/*
- * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size, and 512 bytes
- * of flash data:
- *  sizeof(ec_host_request):          8
- *  sizeof(ec_params_flash_write):    8
- *  payload                         512
- */
-#define SHI_MAX_REQUEST_SIZE CONFIG_CROS_SHI_MAX_REQUEST
-#define SHI_MAX_RESPONSE_SIZE CONFIG_CROS_SHI_MAX_RESPONSE
-
-/*
- * Our input and output msg buffers. These must be large enough for our largest
- * message, including protocol overhead.  The pointers after the protocol
- * overhead, as passed to the host command handler, must be 32-bit aligned.
- */
-#define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
-#define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
-static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE +
-			      SHI_OUT_END_PAD] __aligned(4);
-static uint8_t *const out_msg =
-	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
-static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
-
-/* Parameters used by host protocols */
-static struct host_packet shi_packet;
-
-enum cros_shi_npcx_state {
-	SHI_STATE_NONE = -1,
-	/* SHI not enabled (initial state, and when chipset is off) */
-	SHI_STATE_DISABLED = 0,
-	/* Ready to receive next request */
-	SHI_STATE_READY_TO_RECV,
-	/* Receiving request */
-	SHI_STATE_RECEIVING,
-	/* Processing request */
-	SHI_STATE_PROCESSING,
-	/* Canceling response since CS deasserted and output NOT_READY byte */
-	SHI_STATE_CNL_RESP_NOT_RDY,
-	/* Sending response */
-	SHI_STATE_SENDING,
-	/* Received data is invalid */
-	SHI_STATE_BAD_RECEIVED_DATA,
-};
-
-static enum cros_shi_npcx_state state;
-
-/* Device config */
-struct cros_shi_npcx_config {
-	/* Serial Host Interface (SHI) base address */
-	uintptr_t base;
-	/* clock configuration */
-	struct npcx_clk_cfg clk_cfg;
-	/* pinmux configuration */
-	const uint8_t alts_size;
-	const struct npcx_alt *alts_list;
-	/* SHI IRQ */
-	int irq;
-	struct npcx_wui shi_cs_wui;
-};
-
-/* SHI bus parameters */
-struct shi_bus_parameters {
-	uint8_t *rx_msg; /* Entry pointer of msg rx buffer   */
-	uint8_t *tx_msg; /* Entry pointer of msg tx buffer   */
-	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
-	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
-	uint16_t sz_received; /* Size of received data in bytes   */
-	uint16_t sz_sending; /* Size of sending data in bytes    */
-	uint16_t sz_request; /* request bytes need to receive    */
-	uint16_t sz_response; /* response bytes need to receive   */
-	uint64_t rx_deadline; /* deadline of receiving            */
-} shi_params;
-
-static const struct npcx_alt cros_shi_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
-
-static const struct cros_shi_npcx_config cros_shi_cfg = {
-	.base = DT_INST_REG_ADDR(0),
-	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
-	.alts_size = ARRAY_SIZE(cros_shi_alts),
-	.alts_list = cros_shi_alts,
-	.irq = DT_INST_IRQN(0),
-	.shi_cs_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, shi_cs_wui),
-};
-
-struct cros_shi_npcx_data {
-	struct host_packet shi_packet;
-	sys_slist_t callbacks;
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_shi_npcx_config *)(dev)->config)
-#define DRV_DATA(dev) ((struct cros_shi_npcx_data *)(dev)->data)
-#define HAL_INSTANCE(dev) (struct shi_reg *)(DRV_CONFIG(dev)->base)
-
-/* Forward declaration */
-static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst);
-
-/* Read pointer of input or output buffer by consecutive reading */
-static uint32_t shi_read_buf_pointer(struct shi_reg *const inst)
-{
-	uint8_t stat;
-
-	/* Wait for two consecutive equal values are read */
-	do {
-		stat = inst->IBUFSTAT;
-	} while (stat != inst->IBUFSTAT);
-
-	return (uint32_t)stat;
-}
-
-/*
- * Valid offset of SHI output buffer to write.
- * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
- */
-static uint32_t shi_valid_obuf_offset(struct shi_reg *const inst)
-{
-	return (shi_read_buf_pointer(inst) + SHI_OUT_PREAMBLE_LENGTH) %
-	       SHI_OBUF_FULL_SIZE;
-}
-
-/*
- * This routine write SHI next half output buffer from msg buffer
- */
-static void shi_write_half_outbuf(void)
-{
-	const uint32_t size =
-		MIN(SHI_OBUF_HALF_SIZE,
-		    shi_params.sz_response - shi_params.sz_sending);
-	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
-	const uint8_t *obuf_end = obuf_ptr + size;
-	uint8_t *msg_ptr = shi_params.tx_msg;
-
-	/* Fill half output buffer */
-	while (obuf_ptr != obuf_end)
-		*obuf_ptr++ = *msg_ptr++;
-
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/*
- * This routine read SHI input buffer to msg buffer until
- * we have received a certain number of bytes
- */
-static int shi_read_inbuf_wait(struct shi_reg *const inst, uint32_t szbytes)
-{
-	/* Copy data to msg buffer from input buffer */
-	for (uint32_t i = 0; i < szbytes; i++, shi_params.sz_received++) {
-		/*
-		 * If input buffer pointer equals pointer which wants to read,
-		 * it means data is not ready.
-		 */
-		while (shi_params.rx_buf ==
-		       inst->IBUF + shi_read_buf_pointer(inst)) {
-			if (k_uptime_get() > shi_params.rx_deadline) {
-				return 0;
-			}
-		}
-		/* Restore data to msg buffer */
-		*shi_params.rx_msg++ = *shi_params.rx_buf++;
-	}
-	return 1;
-}
-
-/* This routine fills out all SHI output buffer with status byte */
-static void shi_fill_out_status(struct shi_reg *const inst, uint8_t status)
-{
-	uint8_t start, end;
-	volatile uint8_t *fill_ptr;
-	volatile uint8_t *fill_end;
-	volatile uint8_t *obuf_end;
-
-	/*
-	 * Disable interrupts in case the interfere by the other interrupts.
-	 * Use __disable_irq/__enable_irq instead of using irq_lock/irq_unlock
-	 * here because irq_lock/irq_unlock leave some system exceptions (like
-	 * SVC, NMI, and faults) still enabled.
-	 */
-	__disable_irq();
-
-	/*
-	 * Fill out output buffer with status byte and leave a gap for PREAMBLE.
-	 * The gap guarantees the synchronization. The critical section should
-	 * be done within this gap. No racing happens.
-	 */
-	start = shi_valid_obuf_offset(inst);
-	end = (start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) %
-	      SHI_OBUF_FULL_SIZE;
-
-	fill_ptr = inst->OBUF + start;
-	fill_end = inst->OBUF + end;
-	obuf_end = inst->OBUF + SHI_OBUF_FULL_SIZE;
-	while (fill_ptr != fill_end) {
-		*fill_ptr++ = status;
-		if (fill_ptr == obuf_end)
-			fill_ptr = inst->OBUF;
-	}
-
-	/* End of critical section */
-	__enable_irq();
-}
-
-/* This routine handles shi received unexpected data */
-static void shi_bad_received_data(struct shi_reg *const inst)
-{
-	/* State machine mismatch, timeout, or protocol we can't handle. */
-	shi_fill_out_status(inst, EC_SPI_RX_BAD_DATA);
-	state = SHI_STATE_BAD_RECEIVED_DATA;
-
-	DEBUG_CPRINTF("BAD-");
-	DEBUG_CPRINTF("in_msg=[");
-	for (uint32_t i = 0; i < shi_params.sz_received; i++)
-		DEBUG_CPRINTF("%02x ", in_msg[i]);
-	DEBUG_CPRINTF("]\n");
-
-	/* Reset shi's state machine for error recovery */
-	cros_shi_npcx_reset_prepare(inst);
-
-	DEBUG_CPRINTF("END\n");
-}
-
-/*
- * This routine write SHI output buffer from msg buffer over halt of it.
- * It make sure we have enough time to handle next operations.
- */
-static void shi_write_first_pkg_outbuf(struct shi_reg *const inst,
-				       uint16_t szbytes)
-{
-	uint8_t size, offset;
-	volatile uint8_t *obuf_ptr;
-	volatile uint8_t *obuf_end;
-	uint8_t *msg_ptr;
-	uint32_t half_buf_remain; /* Remains in half buffer are free to write */
-
-	/* Start writing at our current OBUF position */
-	offset = shi_valid_obuf_offset(inst);
-	obuf_ptr = inst->OBUF + offset;
-	msg_ptr = shi_params.tx_msg;
-
-	/* Fill up to OBUF mid point, or OBUF end */
-	half_buf_remain = SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE);
-	size = MIN(half_buf_remain, szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*obuf_ptr++ = *msg_ptr++;
-
-	/* Track bytes sent for later accounting */
-	shi_params.sz_sending += size;
-
-	/* Write data to beginning of OBUF if we've reached the end */
-	if (obuf_ptr == inst->OBUF + SHI_IBUF_FULL_SIZE)
-		obuf_ptr = inst->OBUF;
-
-	/* Fill next half output buffer */
-	size = MIN(SHI_OBUF_HALF_SIZE, szbytes - shi_params.sz_sending);
-	obuf_end = obuf_ptr + size;
-	while (obuf_ptr != obuf_end)
-		*obuf_ptr++ = *msg_ptr++;
-
-	/* Track bytes sent / last OBUF position written for later accounting */
-	shi_params.sz_sending += size;
-	shi_params.tx_buf = obuf_ptr;
-	shi_params.tx_msg = msg_ptr;
-}
-
-/**
- * Called to send a response back to the host.
- *
- * Some commands can continue for a while. This function is called by
- * host_command task after processing request is completed. It fills up the
- * FIFOs with response package and the remaining data is handled in shi's ISR.
- */
-static void shi_send_response_packet(struct host_packet *pkt)
-{
-	struct shi_reg *const inst = (struct shi_reg *)(cros_shi_cfg.base);
-
-	/*
-	 * Disable interrupts. This routine is not called from interrupt
-	 * context and buffer underrun will likely occur if it is
-	 * preempted after writing its initial reply byte. Also, we must be
-	 * sure our state doesn't unexpectedly change, in case we're expected
-	 * to take RESP_NOT_RDY actions.
-	 */
-	__disable_irq();
-
-	if (state == SHI_STATE_PROCESSING) {
-		/* Append our past-end byte, which we reserved space for. */
-		((uint8_t *)pkt->response)[pkt->response_size] =
-			EC_SPI_PAST_END;
-
-		/* Computing sending bytes of response */
-		shi_params.sz_response =
-			pkt->response_size + SHI_PROTO3_OVERHEAD;
-
-		/* Start to fill output buffer with msg buffer */
-		shi_write_first_pkg_outbuf(inst, shi_params.sz_response);
-		/* Transmit the reply */
-		state = SHI_STATE_SENDING;
-		DEBUG_CPRINTF("SND-");
-	} else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
-		/*
-		 * If we're not processing, then the AP has already terminated
-		 * the transaction, and won't be listening for a response.
-		 * Reset state machine for next transaction.
-		 */
-		cros_shi_npcx_reset_prepare(inst);
-		DEBUG_CPRINTF("END\n");
-	} else
-		DEBUG_CPRINTS("Unexpected state %d in response handler", state);
-
-	__enable_irq();
-}
-
-void shi_handle_host_package(struct shi_reg *const inst)
-{
-	uint32_t sz_inbuf_int = shi_params.sz_request / SHI_IBUF_HALF_SIZE;
-	uint32_t cnt_inbuf_int = shi_params.sz_received / SHI_IBUF_HALF_SIZE;
-
-	if (sz_inbuf_int - cnt_inbuf_int)
-		/* Need to receive data from buffer */
-		return;
-	uint32_t remain_bytes = shi_params.sz_request - shi_params.sz_received;
-
-	/* Read remaining bytes from input buffer */
-	if (!shi_read_inbuf_wait(inst, remain_bytes))
-		return shi_bad_received_data(inst);
-
-	/* Move to processing state */
-	state = SHI_STATE_PROCESSING;
-	DEBUG_CPRINTF("PRC-");
-
-	/* Fill output buffer to indicate we`re processing request */
-	shi_fill_out_status(inst, EC_SPI_PROCESSING);
-
-	/* Set up parameters for host request */
-	shi_packet.send_response = shi_send_response_packet;
-
-	shi_packet.request = in_msg;
-	shi_packet.request_temp = NULL;
-	shi_packet.request_max = sizeof(in_msg);
-	shi_packet.request_size = shi_params.sz_request;
-
-	/* Put FRAME_START in first byte */
-	out_msg[0] = EC_SPI_FRAME_START;
-	shi_packet.response = out_msg + EC_SPI_FRAME_START_LENGTH;
-
-	/* Reserve space for frame start and trailing past-end byte */
-	shi_packet.response_max = SHI_MAX_RESPONSE_SIZE;
-	shi_packet.response_size = 0;
-	shi_packet.driver_result = EC_RES_SUCCESS;
-
-	/* Go to common layer to handle request */
-	host_packet_receive(&shi_packet);
-}
-
-static void shi_parse_header(struct shi_reg *const inst)
-{
-	/* We're now inside a transaction */
-	state = SHI_STATE_RECEIVING;
-	DEBUG_CPRINTF("RV-");
-
-	/* Setup deadline time for receiving */
-	shi_params.rx_deadline = k_uptime_get() + SHI_CMD_RX_TIMEOUT_MS;
-
-	/* Wait for version, command, length bytes */
-	if (!shi_read_inbuf_wait(inst, 3))
-		return shi_bad_received_data(inst);
-
-	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
-		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *)in_msg;
-		int pkt_size;
-		/*
-		 * If request is over half of input buffer,
-		 * we need to modified the algorithm again.
-		 */
-		__ASSERT_NO_MSG(sizeof(*r) < SHI_IBUF_HALF_SIZE);
-
-		/* Wait for the rest of the command header */
-		if (!shi_read_inbuf_wait(inst, sizeof(*r) - 3))
-			return shi_bad_received_data(inst);
-
-		/* Check how big the packet should be */
-		pkt_size = host_request_expected_size(r);
-		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
-			return shi_bad_received_data(inst);
-
-		/* Computing total bytes need to receive */
-		shi_params.sz_request = pkt_size;
-
-		shi_handle_host_package(inst);
-	} else {
-		/* Invalid version number */
-		return shi_bad_received_data(inst);
-	}
-}
-
-static void shi_sec_ibf_int_enable(struct shi_reg *const inst, int enable)
-{
-	if (enable) {
-		/* Setup IBUFLVL2 threshold and enable it */
-		inst->SHICFG5 |= BIT(NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(inst->SHICFG5, NPCX_SHICFG5_IBUFLVL2,
-			  SHI_IBUFLVL2_THRESHOLD);
-		inst->SHICFG5 &= ~BIT(NPCX_SHICFG5_IBUFLVL2DIS);
-		/* Enable IBHF2 event */
-		inst->EVENABLE2 |= BIT(NPCX_EVENABLE2_IBHF2EN);
-	} else {
-		/* Disable IBHF2 event first */
-		inst->EVENABLE2 &= ~BIT(NPCX_EVENABLE2_IBHF2EN);
-		/* Disable IBUFLVL2 and set threshold back to zero */
-		inst->SHICFG5 |= BIT(NPCX_SHICFG5_IBUFLVL2DIS);
-		SET_FIELD(inst->SHICFG5, NPCX_SHICFG5_IBUFLVL2, 0);
-	}
-}
-
-/* This routine copies SHI half input buffer data to msg buffer */
-static void shi_read_half_inbuf(void)
-{
-	/*
-	 * Copy to read buffer until reaching middle/top address of
-	 * input buffer or completing receiving data
-	 */
-	do {
-		/* Restore data to msg buffer */
-		*shi_params.rx_msg++ = *shi_params.rx_buf++;
-		shi_params.sz_received++;
-	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE &&
-		 shi_params.sz_received != shi_params.sz_request);
-}
-
-/*
- * Avoid spamming the console with prints every IBF / IBHF interrupt, if
- * we find ourselves in an unexpected state.
- */
-static enum cros_shi_npcx_state last_error_state = SHI_STATE_NONE;
-
-static void log_unexpected_state(char *isr_name)
-{
-	if (state != last_error_state)
-		DEBUG_CPRINTF("Unexpected state %d in %s ISR", state, isr_name);
-	last_error_state = state;
-}
-
-static void shi_handle_cs_assert(struct shi_reg *const inst)
-{
-	/* If not enabled, ignore glitches on SHI_CS_L */
-	if (state == SHI_STATE_DISABLED)
-		return;
-
-	/* NOT_READY should be sent and there're no spi transaction now. */
-	if (state == SHI_STATE_CNL_RESP_NOT_RDY)
-		return;
-
-	/* Chip select is low = asserted */
-	if (state != SHI_STATE_READY_TO_RECV) {
-		/* State machine should be reset in EVSTAT_EOR ISR */
-		DEBUG_CPRINTF("Unexpected state %d in CS ISR", state);
-		return;
-	}
-
-	DEBUG_CPRINTF("CSL-");
-
-	/*
-	 * Clear possible EOR event from previous transaction since it's
-	 * irrelevant now that CS is re-asserted.
-	 */
-	inst->EVSTAT = BIT(NPCX_EVSTAT_EOR);
-
-	/* Do not deep sleep during SHI transaction */
-	disable_sleep(SLEEP_MASK_SPI);
-}
-
-static void shi_handle_cs_deassert(struct shi_reg *const inst)
-{
-	/*
-	 * If the buffer is still used by the host command.
-	 * Change state machine for response handler.
-	 */
-	if (state == SHI_STATE_PROCESSING) {
-		/*
-		 * Mark not ready to prevent the other
-		 * transaction immediately
-		 */
-		shi_fill_out_status(inst, EC_SPI_NOT_READY);
-
-		state = SHI_STATE_CNL_RESP_NOT_RDY;
-
-		/*
-		 * Disable SHI interrupt, it will remain disabled
-		 * until shi_send_response_packet() is called and
-		 * CS is asserted for a new transaction.
-		 */
-		irq_disable(DT_INST_IRQN(0));
-
-		DEBUG_CPRINTF("CNL-");
-		return;
-		/* Next transaction but we're not ready */
-	} else if (state == SHI_STATE_CNL_RESP_NOT_RDY) {
-		return;
-	}
-
-	/* Error state for checking*/
-	if (state != SHI_STATE_SENDING) {
-		log_unexpected_state("CSNRE");
-	}
-	/* reset SHI and prepare to next transaction again */
-	cros_shi_npcx_reset_prepare(inst);
-	DEBUG_CPRINTF("END\n");
-}
-
-static void shi_handle_input_buf_half_full(struct shi_reg *const inst)
-{
-	if (state == SHI_STATE_RECEIVING) {
-		/* Read data from input to msg buffer */
-		shi_read_half_inbuf();
-		return shi_handle_host_package(inst);
-	} else if (state == SHI_STATE_SENDING) {
-		/* Write data from msg buffer to output buffer */
-		if (shi_params.tx_buf == inst->OBUF + SHI_OBUF_FULL_SIZE) {
-			/* Write data from bottom address again */
-			shi_params.tx_buf = inst->OBUF;
-			return shi_write_half_outbuf();
-		} else /* ignore it */
-			return;
-	} else if (state == SHI_STATE_PROCESSING) {
-		/* Wait for host to handle request */
-	} else {
-		/* Unexpected status */
-		log_unexpected_state("IBHF");
-	}
-}
-
-static void shi_handle_input_buf_full(struct shi_reg *const inst)
-{
-	if (state == SHI_STATE_RECEIVING) {
-		/* read data from input to msg buffer */
-		shi_read_half_inbuf();
-		/* Read to bottom address again */
-		shi_params.rx_buf = inst->IBUF;
-		return shi_handle_host_package(inst);
-	} else if (state == SHI_STATE_SENDING) {
-		/* Write data from msg buffer to output buffer */
-		if (shi_params.tx_buf == inst->OBUF + SHI_OBUF_HALF_SIZE)
-			return shi_write_half_outbuf();
-		else /* ignore it */
-			return;
-	} else if (state == SHI_STATE_PROCESSING) {
-		/* Wait for host to handle request */
-		return;
-	}
-	/* Unexpected status */
-	log_unexpected_state("IBF");
-}
-
-static void cros_shi_npcx_isr(const struct device *dev)
-{
-	uint8_t stat;
-	uint8_t stat2;
-	struct shi_reg *const inst = HAL_INSTANCE(dev);
-
-	/* Read status register and clear interrupt status early */
-	stat = inst->EVSTAT;
-	inst->EVSTAT = stat;
-	stat2 = inst->EVSTAT2;
-
-	/* SHI CS pin is asserted in EVSTAT2 */
-	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_CSNFE)) {
-		/* Clear pending bit of CSNFE */
-		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE);
-		DEBUG_CPRINTF("CSNFE-");
-		/*
-		 * BUSY bit is set when SHI_CS is asserted. If not, leave it for
-		 * SHI_CS de-asserted event.
-		 */
-		if (!IS_BIT_SET(inst->SHICFG2, NPCX_SHICFG2_BUSY)) {
-			DEBUG_CPRINTF("CSNB-");
-			return;
-		}
-		shi_handle_cs_assert(inst);
-	}
-
-	/*
-	 * End of data for read/write transaction. i.e. SHI_CS is deasserted.
-	 * Host completed or aborted transaction
-	 *
-	 * EOR has the limitation that it will not be set even if the SHI_CS is
-	 * deasserted without SPI clocks. The new SHI module introduce the
-	 * CSNRE bit which will be set when SHI_CS is deasserted regardless of
-	 * SPI clocks.
-	 */
-	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_CSNRE)) {
-		/* Clear pending bit of CSNRE */
-		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE);
-		/*
-		 * We're not in proper state.
-		 * Mark not ready to abort next transaction
-		 */
-		DEBUG_CPRINTF("CSH-");
-		return shi_handle_cs_deassert(inst);
-	}
-
-	/*
-	 * The number of bytes received reaches the size of
-	 * protocol V3 header(=8) after CS asserted.
-	 */
-	if (IS_BIT_SET(stat2, NPCX_EVSTAT2_IBHF2)) {
-		/* Clear IBHF2 */
-		inst->EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2);
-		DEBUG_CPRINTF("HDR-");
-		/* Disable second IBF interrupt and start to parse header */
-		shi_sec_ibf_int_enable(inst, 0);
-		shi_parse_header(inst);
-	}
-
-	/*
-	 * Indicate input/output buffer pointer reaches the half buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat, NPCX_EVSTAT_IBHF)) {
-		return shi_handle_input_buf_half_full(inst);
-	}
-
-	/*
-	 * Indicate input/output buffer pointer reaches the full buffer size.
-	 * Transaction is processing.
-	 */
-	if (IS_BIT_SET(stat, NPCX_EVSTAT_IBF)) {
-		return shi_handle_input_buf_full(inst);
-	}
-}
-
-static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst)
-{
-	uint32_t i;
-
-	state = SHI_STATE_DISABLED;
-
-	irq_disable(DT_INST_IRQN(0));
-
-	/* Disable SHI unit to clear all status bits */
-	inst->SHICFG1 &= ~BIT(NPCX_SHICFG1_EN);
-
-	/* Initialize parameters of next transaction */
-	shi_params.rx_msg = in_msg;
-	shi_params.tx_msg = out_msg;
-	shi_params.rx_buf = inst->IBUF;
-	shi_params.tx_buf = inst->IBUF + SHI_OBUF_HALF_SIZE;
-	shi_params.sz_received = 0;
-	shi_params.sz_sending = 0;
-	shi_params.sz_request = 0;
-	shi_params.sz_response = 0;
-
-	/*
-	 * Fill output buffer to indicate we`re
-	 * ready to receive next transaction.
-	 */
-	for (i = 1; i < SHI_OBUF_FULL_SIZE; i++)
-		inst->OBUF[i] = EC_SPI_RECEIVING;
-	inst->OBUF[0] = EC_SPI_OLD_READY;
-
-	/* SHI/Host Write/input buffer wrap-around enable */
-	inst->SHICFG1 = BIT(NPCX_SHICFG1_IWRAP) | BIT(NPCX_SHICFG1_WEN) |
-			BIT(NPCX_SHICFG1_EN);
-
-	state = SHI_STATE_READY_TO_RECV;
-	last_error_state = SHI_STATE_NONE;
-
-	shi_sec_ibf_int_enable(inst, 1);
-	irq_enable(DT_INST_IRQN(0));
-
-	/* Allow deep sleep at the end of SHI transaction */
-	enable_sleep(SLEEP_MASK_SPI);
-
-	DEBUG_CPRINTF("RDY-");
-}
-
-static int cros_shi_npcx_enable(const struct device *dev)
-{
-	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
-	struct shi_reg *const inst = HAL_INSTANCE(dev);
-
-	cros_shi_npcx_reset_prepare(inst);
-	npcx_miwu_irq_disable(&config->shi_cs_wui);
-
-	/* Configure pin-mux from GPIO to SHI. */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
-
-	NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
-	npcx_miwu_irq_enable(&config->shi_cs_wui);
-	irq_enable(DT_INST_IRQN(0));
-
-	return 0;
-}
-
-static int cros_shi_npcx_disable(const struct device *dev)
-{
-	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
-
-	state = SHI_STATE_DISABLED;
-
-	irq_disable(DT_INST_IRQN(0));
-	npcx_miwu_irq_disable(&config->shi_cs_wui);
-
-	/* Configure pin-mux from SHI to GPIO. */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 0);
-
-	/*
-	 * Allow deep sleep again in case CS dropped before ec was
-	 * informed in hook function and turn off SHI's interrupt in time.
-	 */
-	enable_sleep(SLEEP_MASK_SPI);
-
-	return 0;
-}
-
-static int shi_npcx_init(const struct device *dev)
-{
-	int ret;
-	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
-	struct shi_reg *const inst = HAL_INSTANCE(dev);
-	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
-
-	/* Turn on shi device clock first */
-	ret = clock_control_on(clk_dev,
-			       (clock_control_subsys_t *)&config->clk_cfg);
-	if (ret < 0) {
-		DEBUG_CPRINTF("Turn on SHI clock fail %d", ret);
-		return ret;
-	}
-
-	/* If booter doesn't set the host interface type */
-	if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
-		npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
-	}
-
-	/*
-	 * SHICFG1 (SHI Configuration 1) setting
-	 * [7] - IWRAP	= 1: Wrap input buffer to the first address
-	 * [6] - CPOL	= 0: Sampling on rising edge and output on falling edge
-	 * [5] - DAS	= 0: return STATUS reg data after Status command
-	 * [4] - AUTOBE	= 0: Automatically update the OBES bit in STATUS reg
-	 * [3] - AUTIBF	= 0: Automatically update the IBFS bit in STATUS reg
-	 * [2] - WEN    = 0: Enable host write to input buffer
-	 * [1] - Reserved 0
-	 * [0] - ENABLE	= 0: Disable SHI at the beginning
-	 */
-	inst->SHICFG1 = 0x80;
-
-	/*
-	 * SHICFG2 (SHI Configuration 2) setting
-	 * [7] - Reserved 0
-	 * [6] - REEVEN = 0: Restart events are not used
-	 * [5] - Reserved 0
-	 * [4] - REEN   = 0: Restart transactions are not used
-	 * [3] - SLWU   = 0: Seem-less wake-up is enabled by default
-	 * [2] - ONESHOT= 0: WEN is cleared at the end of a write transaction
-	 * [1] - BUSY   = 0: SHI bus is busy 0: idle.
-	 * [0] - SIMUL	= 1: Turn on simultaneous Read/Write
-	 */
-	inst->SHICFG2 = 0x01;
-
-	/*
-	 * EVENABLE (Event Enable) setting
-	 * [7] - IBOREN = 0: Input buffer overrun interrupt enable
-	 * [6] - STSREN = 0: status read interrupt disable
-	 * [5] - EOWEN  = 0: End-of-Data for Write Transaction Interrupt Enable
-	 * [4] - EOREN  = 1: End-of-Data for Read Transaction Interrupt Enable
-	 * [3] - IBHFEN = 1: Input Buffer Half Full Interrupt Enable
-	 * [2] - IBFEN  = 1: Input Buffer Full Interrupt Enable
-	 * [1] - OBHEEN = 0: Output Buffer Half Empty Interrupt Enable
-	 * [0] - OBEEN  = 0: Output Buffer Empty Interrupt Enable
-	 */
-	inst->EVENABLE = 0x1C;
-
-	/*
-	 * EVENABLE2 (Event Enable 2) setting
-	 * [2] - CSNFEEN = 1: SHI_CS Falling Edge Interrupt Enable
-	 * [1] - CSNREEN = 1: SHI_CS Rising Edge Interrupt Enable
-	 * [0] - IBHF2EN = 0: Input Buffer Half Full 2 Interrupt Enable
-	 */
-	inst->EVENABLE2 = 0x06;
-
-	/* Clear SHI events status register */
-	inst->EVSTAT = 0xff;
-
-	npcx_miwu_interrupt_configure(&config->shi_cs_wui, NPCX_MIWU_MODE_EDGE,
-				      NPCX_MIWU_TRIG_LOW);
-	/* SHI interrupt installation */
-	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
-		    cros_shi_npcx_isr, DEVICE_DT_INST_GET(0), 0);
-
-	return ret;
-}
-
-static const struct cros_shi_driver_api cros_shi_npcx_driver_api = {
-	.enable = cros_shi_npcx_enable,
-	.disable = cros_shi_npcx_disable,
-};
-
-static struct cros_shi_npcx_data cros_shi_data;
-DEVICE_DT_INST_DEFINE(0, shi_npcx_init, /* pm_control_fn= */ NULL,
-		      &cros_shi_data, &cros_shi_cfg, PRE_KERNEL_1,
-		      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		      &cros_shi_npcx_driver_api);
-
-/* KBS register structure check */
-NPCX_REG_SIZE_CHECK(shi_reg, 0x120);
-NPCX_REG_OFFSET_CHECK(shi_reg, SHICFG1, 0x001);
-NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE, 0x005);
-NPCX_REG_OFFSET_CHECK(shi_reg, IBUFSTAT, 0x00a);
-NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE2, 0x010);
-NPCX_REG_OFFSET_CHECK(shi_reg, OBUF, 0x020);
-NPCX_REG_OFFSET_CHECK(shi_reg, IBUF, 0x0A0);
diff --git a/zephyr/drivers/cros_system/CMakeLists.txt b/zephyr/drivers/cros_system/CMakeLists.txt
deleted file mode 100644
index 733b8be450..0000000000
--- a/zephyr/drivers/cros_system/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_IT8XXX2	cros_system_it8xxx2.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_SYSTEM_NPCX	cros_system_npcx.c)
diff --git a/zephyr/drivers/cros_system/Kconfig b/zephyr/drivers/cros_system/Kconfig
deleted file mode 100644
index c5d98b6081..0000000000
--- a/zephyr/drivers/cros_system/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-menuconfig CROS_SYSTEM_NPCX
-	bool "Nuvoton NPCX cros system driver"
-	depends on SOC_FAMILY_NPCX
-	default y
-	help
-	  This option enables the cros system driver for the NPCX family of
-	  processors. Currently, Zephyr doesn't provide the system related API.
-	  The cros system driver provides the low-level driver related to
-	  chromium ec system functionality.
-
-if CROS_SYSTEM_NPCX
-
-config CROS_SYSTEM_NPCX_INIT_PRIORITY
-	int "cros_system npcx initialization priority"
-	default 10
-	range 10 19
-	help
-	  This sets the npcx cros_system driver initialization priority. The
-	  cros_system driver provides access to the NPCX reset cause and must be
-	  higher priority than CONFIG_SYSTEM_PRE_INIT_PRIORITY.
-
-endif # CROS_SYSTEM_NPCX
-
-config CROS_SYSTEM_IT8XXX2
-	bool "ITE IT8XXX2 cros system driver"
-	depends on SOC_FAMILY_RISCV_ITE
-	default y
-	help
-	  This option enables the cros system driver for the it8xxx2 family of
-	  processors.
-
-if CROS_SYSTEM_IT8XXX2
-
-config CROS_SYSTEM_IT8XXX2_INIT_PRIORITY
-	int "cros_system it8xxx2 initialization priority"
-	default 10
-	help
-	  This sets the it8xxx2 cros_system driver initialization priority.
-	  The cros_system driver provides access to the it8xxx2 reset cause
-	  and must be higher priority than
-	  CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY.
-
-endif # CROS_SYSTEM_IT8XXX2
diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
deleted file mode 100644
index 5731dcf984..0000000000
--- a/zephyr/drivers/cros_system/cros_system_it8xxx2.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT ite_it8xxx2_gctrl
-
-#include <device.h>
-#include <drivers/cros_system.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc/ite_it8xxx2/reg_def_cros.h>
-
-#include "gpio.h"
-#include "system.h"
-#include "util.h"
-
-LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
-
-#define GCTRL_IT8XXX2_REG_BASE \
-	((struct gctrl_it8xxx2_regs *)DT_INST_REG_ADDR(0))
-
-#define WDT_IT8XXX2_REG_BASE \
-	((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
-
-static const char *cros_system_it8xxx2_get_chip_vendor(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return "ite";
-}
-
-static uint32_t system_get_chip_id(void)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	return (gctrl_base->GCTRL_ECHIPID1 << 16) |
-		(gctrl_base->GCTRL_ECHIPID2 << 8) |
-		gctrl_base->GCTRL_ECHIPID3;
-}
-
-static uint8_t system_get_chip_version(void)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	/* bit[3-0], chip version */
-	return gctrl_base->GCTRL_ECHIPVER & 0x0F;
-}
-
-static const char *cros_system_it8xxx2_get_chip_name(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	static char buf[8] = {'i', 't'};
-	uint32_t chip_id = system_get_chip_id();
-	int num = 4;
-
-	for (int n = 2; num >= 0; n++, num--)
-		snprintf(buf+n, (sizeof(buf)-n), "%x",
-			 chip_id >> (num * 4) & 0xF);
-
-	return buf;
-}
-
-static const char *cros_system_it8xxx2_get_chip_revision(const struct device
-							 *dev)
-{
-	ARG_UNUSED(dev);
-
-	static char buf[3];
-	uint8_t rev = system_get_chip_version();
-
-	snprintf(buf, sizeof(buf), "%1xx", rev+0xa);
-
-	return buf;
-}
-
-static int cros_system_it8xxx2_get_reset_cause(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-	/* system reset flag */
-	uint32_t system_flags = chip_read_reset_flags();
-	int chip_reset_cause = 0;
-	uint8_t raw_reset_cause = gctrl_base->GCTRL_RSTS & IT8XXX2_GCTRL_LRS;
-	uint8_t raw_reset_cause2 = gctrl_base->GCTRL_SPCTRL4 &
-		(IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR |
-		IT8XXX2_GCTRL_LRSIPGWR);
-
-	/* Clear reset cause. */
-	gctrl_base->GCTRL_RSTS |= IT8XXX2_GCTRL_LRS;
-	gctrl_base->GCTRL_SPCTRL4 |= (IT8XXX2_GCTRL_LRSIWR |
-		IT8XXX2_GCTRL_LRSIPWRSWTR | IT8XXX2_GCTRL_LRSIPGWR);
-
-	/* Determine if watchdog reset or power on reset. */
-	if (raw_reset_cause & IT8XXX2_GCTRL_IWDTR) {
-		system_flags |= EC_RESET_FLAG_WATCHDOG;
-		chip_reset_cause = WATCHDOG_RST;
-	} else if (raw_reset_cause < 2) {
-		system_flags |= EC_RESET_FLAG_POWER_ON;
-		chip_reset_cause = POWERUP;
-	}
-	/* Determine reset-pin reset. */
-	if (raw_reset_cause2 & IT8XXX2_GCTRL_LRSIWR) {
-		system_flags |= EC_RESET_FLAG_RESET_PIN;
-		chip_reset_cause = VCC1_RST_PIN;
-	}
-
-	/* watchdog module triggers these reset */
-	if (system_flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_SOFT))
-		system_flags &= ~EC_RESET_FLAG_WATCHDOG;
-
-	/* Set the system reset flags. */
-	system_set_reset_flags(system_flags);
-
-	return chip_reset_cause;
-}
-
-static int cros_system_it8xxx2_init(const struct device *dev)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-
-	/* System triggers a soft reset by default (command: reboot). */
-	gctrl_base->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN;
-
-	return 0;
-}
-
-static int cros_system_it8xxx2_soc_reset(const struct device *dev)
-{
-	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
-	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
-	uint32_t chip_reset_flags = chip_read_reset_flags();
-
-	/* Disable interrupts to avoid task swaps during reboot. */
-	interrupt_disable_all();
-
-	if (chip_reset_flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_HIBERNATE))
-		gctrl_base->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN;
-
-	/*
-	 * Writing invalid key to watchdog module triggers a soft or hardware
-	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
-	 */
-	wdt_base->ETWCFG |= IT8XXX2_WDT_EWDKEYEN;
-	wdt_base->EWDKEYR = 0x00;
-
-	/* Spin and wait for reboot */
-	while (1)
-		;
-
-	/* Should never return */
-	return 0;
-}
-
-static int cros_system_it8xxx2_hibernate(const struct device *dev,
-					 uint32_t seconds,
-					 uint32_t microseconds)
-{
-	struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE;
-
-	/* Disable all interrupts. */
-	interrupt_disable_all();
-
-	/* Save and disable interrupts */
-	if (IS_ENABLED(CONFIG_ITE_IT8XXX2_INTC))
-		ite_intc_save_and_disable_interrupts();
-
-	/* bit5: watchdog is disabled. */
-	wdt_base->ETWCTRL |= IT8XXX2_WDT_EWDSCEN;
-
-	/*
-	 * Setup GPIOs for hibernate. On some boards, it's possible that this
-	 * may not return at all. On those boards, power to the EC is likely
-	 * being turn off entirely.
-	 */
-	if (board_hibernate_late) {
-		/*
-		 * Set reset flag in case board_hibernate_late() doesn't
-		 * return.
-		 */
-		chip_save_reset_flags(EC_RESET_FLAG_HIBERNATE);
-		board_hibernate_late();
-	}
-
-	if (seconds || microseconds) {
-		/*
-		 * Convert milliseconds(or at least 1 ms) to 32 Hz
-		 * free run timer count for hibernate.
-		 */
-		uint32_t c = (seconds * 1000 + microseconds / 1000 + 1) *
-				32 / 1000;
-
-		/* Enable a 32-bit timer and clock source is 32 Hz */
-		/* Disable external timer x */
-		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) &= ~IT8XXX2_EXT_ETXEN;
-		irq_disable(FREE_RUN_TIMER_IRQ);
-		IT8XXX2_EXT_PSRX(FREE_RUN_TIMER) = EXT_PSR_32;
-		IT8XXX2_EXT_CNTX(FREE_RUN_TIMER) = c & FREE_RUN_TIMER_MAX_CNT;
-		/* Enable and re-start external timer x */
-		IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER) |=
-			(IT8XXX2_EXT_ETXEN | IT8XXX2_EXT_ETXRST);
-		irq_enable(FREE_RUN_TIMER_IRQ);
-	}
-
-	static const int wakeup_pin_list[] = {
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
-		UTIL_LISTIFY(SYSTEM_DT_NODE_WAKEUP_PIN_LEN,
-			     SYSTEM_DT_WAKEUP_GPIO_ENUM_BY_IDX, _)
-#endif
-	};
-
-	/* Reconfigure wake-up GPIOs */
-	for (int i = 0; i < ARRAY_SIZE(wakeup_pin_list); i++)
-		/* Re-enable interrupt for wake-up inputs */
-		gpio_enable_interrupt(wakeup_pin_list[i]);
-
-	/* EC sleep mode */
-	chip_pll_ctrl(CHIP_PLL_SLEEP);
-
-	/* Chip sleep and wait timer wake it up */
-	__asm__ volatile ("wfi");
-
-	/* Reset EC when wake up from sleep mode (system hibernate) */
-	system_reset(SYSTEM_RESET_HIBERNATE);
-
-	return 0;
-}
-
-static const struct cros_system_driver_api cros_system_driver_it8xxx2_api = {
-	.get_reset_cause = cros_system_it8xxx2_get_reset_cause,
-	.soc_reset = cros_system_it8xxx2_soc_reset,
-	.hibernate = cros_system_it8xxx2_hibernate,
-	.chip_vendor = cros_system_it8xxx2_get_chip_vendor,
-	.chip_name = cros_system_it8xxx2_get_chip_name,
-	.chip_revision = cros_system_it8xxx2_get_chip_revision,
-};
-
-#if CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY >= \
-	CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY
-#error "CROS_SYSTEM must initialize before the SYSTEM_PRE initialization"
-#endif
-DEVICE_DEFINE(cros_system_it8xxx2_0, "CROS_SYSTEM", cros_system_it8xxx2_init,
-	      NULL, NULL, NULL, PRE_KERNEL_1,
-	      CONFIG_CROS_SYSTEM_IT8XXX2_INIT_PRIORITY,
-	      &cros_system_driver_it8xxx2_api);
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c
deleted file mode 100644
index e3d3bc29b2..0000000000
--- a/zephyr/drivers/cros_system/cros_system_npcx.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <arch/arm/aarch32/cortex_m/cmsis.h>
-#include <drivers/cros_system.h>
-#include <drivers/gpio.h>
-#include <drivers/watchdog.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc/nuvoton_npcx/reg_def_cros.h>
-#include <sys/util.h>
-
-#include "gpio.h"
-#include "rom_chip.h"
-#include "soc_gpio.h"
-#include "soc_miwu.h"
-#include "system.h"
-
-LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
-
-/* Driver config */
-struct cros_system_npcx_config {
-	/* hardware module base address */
-	uintptr_t base_scfg;
-	uintptr_t base_twd;
-	uintptr_t base_mswc;
-};
-
-/* Driver data */
-struct cros_system_npcx_data {
-	int reset; /* reset cause */
-};
-
-/* Driver convenience defines */
-#define DRV_CONFIG(dev) ((const struct cros_system_npcx_config *)(dev)->config)
-
-#define HAL_SCFG_INST(dev) (struct scfg_reg *)(DRV_CONFIG(dev)->base_scfg)
-#define HAL_TWD_INST(dev) (struct twd_reg *)(DRV_CONFIG(dev)->base_twd)
-#define HAL_MSWC_INST(dev) (struct mswc_reg *)(DRV_CONFIG(dev)->base_mswc)
-
-#define DRV_DATA(dev) ((struct cros_system_npcx_data *)(dev)->data)
-
-#define SYSTEM_DT_NODE_SOC_ID_CONFIG DT_INST(0, nuvoton_npcx_soc_id)
-
-/* Chip info devicetree data */
-#define NPCX_FAMILY_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, family_id)
-
-#define NPCX_CHIP_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, chip_id)
-
-#define NPCX_DEVICE_ID DT_PROP(SYSTEM_DT_NODE_SOC_ID_CONFIG, device_id)
-
-#define NPCX_REVISION_ADDR \
-	DT_PROP_BY_IDX(SYSTEM_DT_NODE_SOC_ID_CONFIG, revision_reg, 0)
-#define NPCX_REVISION_LEN \
-	DT_PROP_BY_IDX(SYSTEM_DT_NODE_SOC_ID_CONFIG, revision_reg, 1)
-
-/* RAM block size in npcx family (Unit: bytes) */
-#define NPCX_RAM_BLOCK_SIZE (32 * 1024)
-/* RAM block number in npcx7 series */
-
-/* Calculate the number of RAM blocks:
- * total RAM size = code ram + data ram + extra 2K for ROM functions
- * divided by the block size 32k.
- */
-#define DATA_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
-#define CODE_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(flash0))
-#define NPCX_RAM_BLOCK_COUNT \
-	((DATA_RAM_SIZE + CODE_RAM_SIZE + KB(2)) / NPCX_RAM_BLOCK_SIZE)
-
-/* Valid bit-depth of RAM block Power-Down control (RAM_PD) registers. Use its
- * mask to power down all unnecessary RAM blocks before hibernating.
- */
-#define NPCX_RAM_PD_DEPTH DT_PROP(DT_NODELABEL(pcc), ram_pd_depth)
-#define NPCX_RAM_BLOCK_PD_MASK (BIT(NPCX_RAM_PD_DEPTH) - 1)
-
-/* Get saved reset flag address in battery-backed ram */
-#define BBRAM_SAVED_RESET_FLAG_ADDR                         \
-	(DT_REG_ADDR(DT_INST(0, nuvoton_npcx_bbram)) + \
-	 DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset))
-
-/* Soc specific system local functions */
-static int system_npcx_watchdog_stop(void)
-{
-	if (IS_ENABLED(CONFIG_WATCHDOG)) {
-		const struct device *wdt_dev = DEVICE_DT_GET(
-				DT_NODELABEL(twd0));
-		if (!device_is_ready(wdt_dev)) {
-			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
-			return -ENODEV;
-		}
-
-		wdt_disable(wdt_dev);
-	}
-
-	return 0;
-}
-
-static void system_npcx_set_flash_pins_tri_state(const struct device *dev)
-{
-	struct scfg_reg *const inst_scfg = HAL_SCFG_INST(dev);
-
-	inst_scfg->DEVCNT |= BIT(NPCX_DEVCNT_F_SPI_TRIS);
-}
-
-static void system_npcx_init_watchdog_reset(const struct device *dev)
-{
-	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
-
-	/* Enable early touch */
-	inst_twd->T0CSR &= ~BIT(NPCX_T0CSR_TESDIS);
-	/* watchdog touched by writing 5Ch to WDSDM */
-	inst_twd->TWCFG |= BIT(NPCX_TWCFG_WDSDME);
-}
-
-static void system_npcx_turn_off_adc(void)
-{
-	struct adc_reg *const inst_adc =
-		(struct adc_reg *)(DT_REG_ADDR(DT_INST(0, nuvoton_npcx_adc)));
-
-	inst_adc->ADCCNF = 0;
-	/* Wait for 1000 us to make sure conversion is completed. */
-	k_busy_wait(1000);
-}
-
-static void system_npcx_turn_off_kernel_timer(void)
-{
-	static struct itim32_reg *const evt_tmr =
-		(struct itim32_reg *)DT_REG_ADDR_BY_NAME(
-			DT_INST(0, nuvoton_npcx_itim_timer), evt_itim);
-
-	evt_tmr->ITCTS32 &= ~BIT(NPCX_ITCTSXX_ITEN);
-}
-
-static void system_npcx_disable_instant_wakeup(void)
-{
-	struct pmc_reg *const inst_pmc = (struct pmc_reg *)(DT_REG_ADDR_BY_NAME(
-		DT_INST(0, nuvoton_npcx_pcc), pmc));
-
-	inst_pmc->ENIDL_CTL &= ~BIT(NPCX_ENIDL_CTL_LP_WK_CTL);
-}
-
-static void system_npcx_set_wakeup_gpios_before_hibernate(void)
-{
-	const uintptr_t miwu_base[] = {
-		DT_REG_ADDR(DT_INST(0, nuvoton_npcx_miwu)),
-		DT_REG_ADDR(DT_INST(1, nuvoton_npcx_miwu)),
-		DT_REG_ADDR(DT_INST(2, nuvoton_npcx_miwu)),
-	};
-
-	/* Disable all MIWU inputs before entering hibernate */
-	for (int table = 0; table < ARRAY_SIZE(miwu_base); table++) {
-		for (int group = 0; group < NPCX_MIWU_GROUP_COUNT; group++) {
-			/* Disable all wake-ups */
-			NPCX_WKEN(miwu_base[table], group) = 0x00;
-			/* Clear all pending bits of wake-ups */
-			NPCX_WKPCL(miwu_base[table], group) = 0xFF;
-			/*
-			 * Disable all inputs of wake-ups to prevent leakage
-			 * caused by input floating.
-			 */
-			NPCX_WKINEN(miwu_base[table], group) = 0x00;
-		}
-	}
-
-	static const int wakeup_pin_list[] = {
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
-		UTIL_LISTIFY(SYSTEM_DT_NODE_WAKEUP_PIN_LEN,
-			     SYSTEM_DT_WAKEUP_GPIO_ENUM_BY_IDX, _)
-#endif
-	};
-
-	/* Reconfigure wake-up GPIOs */
-	for (int i = 0; i < ARRAY_SIZE(wakeup_pin_list); i++) {
-		gpio_reset(wakeup_pin_list[i]);
-		/* Re-enable interrupt for wake-up inputs */
-		gpio_enable_interrupt(wakeup_pin_list[i]);
-	}
-}
-
-/*
- * Hibernate function locates in the last 32K ram block in npcx7 series.
- * Do not use global variables or call functions since we have turned off
- * the other ram blocks.
- */
-noreturn void __keep __attribute__((section(".lfw.hiber")))
-system_npcx_hibernate_by_lfw_in_last_ram(const struct device *dev,
-					 uint32_t pd_ram_mask)
-{
-	/* Modules used for hibernating */
-	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
-	struct mtc_reg *const inst_mtc = (struct mtc_reg *)(DT_REG_ADDR(
-		DT_INST(0, nuvoton_npcx_cros_mtc)));
-	struct pmc_reg *const inst_pmc = (struct pmc_reg *)(DT_REG_ADDR_BY_NAME(
-		DT_INST(0, nuvoton_npcx_pcc), pmc));
-	uint32_t reset_flags;
-	volatile uint8_t *saved_reset_flags =
-		(volatile uint8_t *)BBRAM_SAVED_RESET_FLAG_ADDR;
-
-	/* Turn off all blocks except last one for better power consumption */
-	inst_pmc->RAM_PD[0] = (uint8_t)pd_ram_mask;
-	inst_pmc->RAM_PD[1] = (uint8_t)(pd_ram_mask >> 8);
-
-	/* Set deep idle mode */
-	inst_pmc->PMCSR = BIT(NPCX_PMCSR_IDLE) | BIT(NPCX_PMCSR_DHF);
-
-	/* Enter system sleep mode */
-	__asm__ volatile("wfi");
-
-	/*
-	 * Mark wake-up reason for hibernate. Do not call bbram utilities
-	 * directly since the other ram blocks are power down.
-	 */
-	if (IS_BIT_SET(inst_mtc->WTC, NPCX_WTC_PTO)) {
-		/* Save wake-up reason as RTC alarm. */
-		reset_flags = EC_RESET_FLAG_RTC_ALARM;
-	} else {
-		/* Otherwise, we treat it as GPIOs wake-up */
-		reset_flags = EC_RESET_FLAG_WAKE_PIN;
-	}
-
-	saved_reset_flags[0] |= reset_flags;
-	saved_reset_flags[1] |= reset_flags >> 8;
-	saved_reset_flags[2] |= reset_flags >> 16;
-	saved_reset_flags[3] |= reset_flags >> 24;
-
-	/*
-	 * The trigger of a watchdog event by a "too early service" condition.
-	 * When the watchdog is written more than once during three watchdog
-	 * clock cycle.
-	 */
-	inst_twd->WDSDM = 0x5C;
-	inst_twd->WDSDM = 0x5C;
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		continue;
-}
-
-static inline int system_npcx_get_ram_blk_by_lfw_addr(char *address)
-{
-	return NPCX_RAM_BLOCK_COUNT -
-	       ceiling_fraction((uint32_t)address -
-					CONFIG_CROS_EC_PROGRAM_MEMORY_BASE,
-				NPCX_RAM_BLOCK_SIZE);
-}
-
-static void system_npcx_hibernate_by_disable_ram(const struct device *dev,
-						 uint32_t seconds,
-						 uint32_t microseconds)
-{
-	/* Get 32kb ram block order of lfw function */
-	extern char __lfw_text_start[], __lfw_text_end[];
-	int lfw_block = system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_start);
-	uint32_t pd_ram_mask = ~BIT(lfw_block) & NPCX_RAM_BLOCK_PD_MASK;
-
-	if (lfw_block != system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_end)) {
-		LOG_ERR("LFW cannot cross ram blocks!");
-		return;
-	}
-
-	/*
-	 * Set status of pins which connect to flash to tri-state in case
-	 * the leakage current.
-	 */
-	system_npcx_set_flash_pins_tri_state(dev);
-
-	/* Initialize watchdog for reset after wake-up from hibernating */
-	system_npcx_init_watchdog_reset(dev);
-
-	/* Disable ADC and wait for 1000 us to make sure conversion is done */
-	if (IS_ENABLED(CONFIG_ADC))
-		system_npcx_turn_off_adc();
-
-	/* Disable kernel timer */
-	system_npcx_turn_off_kernel_timer();
-
-	/* Disable instant wake up mode for better power consumption */
-	system_npcx_disable_instant_wakeup();
-
-	/*
-	 * Set wake-up input GPIOs and turn off the other sources for better
-	 * power consumption before entering hibernate mode.
-	 */
-	system_npcx_set_wakeup_gpios_before_hibernate();
-
-	/*
-	 * Give the board a chance to do any late stage hibernation work.  This
-	 * is likely going to configure GPIOs for hibernation.  On some boards,
-	 * it's possible that this may not return at all.  On those boards,
-	 * power to the EC is likely being turn off entirely.
-	 */
-	if (board_hibernate_late) {
-		board_hibernate_late();
-	}
-
-	/* Setup a RTC alarm if needed */
-	if (IS_ENABLED(CONFIG_RTC) && (seconds || microseconds)) {
-		system_set_rtc_alarm(seconds, microseconds);
-	}
-
-	/* Clear all pending IRQs in case wake-up immediately after sleeping */
-	for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
-		NVIC_ClearPendingIRQ(i);
-	}
-
-	/* Execute hibernate by lfw which locates in last 32K block ram */
-	system_npcx_hibernate_by_lfw_in_last_ram(dev, pd_ram_mask);
-}
-
-static const char *cros_system_npcx_get_chip_vendor(const struct device *dev)
-{
-	struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev);
-	static char str[11] = "Unknown-XX";
-	char *p = str + 8;
-	uint8_t fam_id = inst_mswc->SID_CR;
-
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
-	if (fam_id == NPCX_FAMILY_ID) {
-		return "Nuvoton";
-	}
-#endif
-
-	hex2char(fam_id >> 4, p++);
-	hex2char(fam_id & 0xf, p);
-	return str;
-}
-
-static const char *cros_system_npcx_get_chip_name(const struct device *dev)
-{
-	struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev);
-	static char str[13] = "Unknown-XXXX";
-	char *p = str + 8;
-	uint8_t chip_id = inst_mswc->SRID_CR;
-	uint8_t device_id = inst_mswc->DEVICE_ID_CR;
-
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
-	if (chip_id == NPCX_CHIP_ID && device_id == NPCX_DEVICE_ID) {
-		return CONFIG_SOC;
-	}
-#endif
-
-	hex2char(chip_id >> 4, p++);
-	hex2char(chip_id & 0xf, p++);
-	hex2char(device_id >> 4, p++);
-	hex2char(device_id & 0xf, p);
-	return str;
-}
-
-static const char *cros_system_npcx_get_chip_revision(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
-	static char rev[NPCX_REVISION_LEN * 2 + 1];
-#else
-	static char rev[1];
-#endif
-	char *p = rev;
-
-#if DT_NODE_EXISTS(SYSTEM_DT_NODE_SOC_ID_CONFIG)
-	/*
-	 * For NPCX7, the revision number is 1 byte.
-	 * For NPCX9 and later chips, the revision number is 4 bytes.
-	 */
-	for (int s = NPCX_REVISION_ADDR + NPCX_REVISION_LEN - 1;
-	     s >= NPCX_REVISION_ADDR; s--) {
-		uint8_t r = *((volatile uint8_t *)s);
-		hex2char(r >> 4, p++);
-		hex2char(r & 0xf, p++);
-	}
-#endif
-	*p = '\0';
-
-	return rev;
-}
-
-static void system_npcx_hibernate_by_psl(const struct device *dev,
-					 uint32_t seconds,
-					 uint32_t microseconds)
-{
-	ARG_UNUSED(dev);
-	/*
-	 * TODO(b/178230662): RTC wake-up in PSL mode only support in npcx9
-	 * series. Nuvoton will introduce CLs for it later.
-	 */
-	ARG_UNUSED(seconds);
-	ARG_UNUSED(microseconds);
-
-	/*
-	 * Configure PSL input pads from "psl-in-pads" property in device tree
-	 * file.
-	 */
-	npcx_pinctrl_psl_input_configure();
-
-	/*
-	 * Give the board a chance to do any late stage hibernation work.  This
-	 * is likely going to configure GPIOs for hibernation.  On some boards,
-	 * it's possible that this may not return at all.  On those boards,
-	 * power to the EC is likely being turn off entirely.
-	 */
-	if (board_hibernate_late)
-		board_hibernate_late();
-
-	/* Turn off VCC1 to enter ultra-low-power mode for hibernating */
-	npcx_pinctrl_psl_output_set_inactive();
-}
-
-static int cros_system_npcx_get_reset_cause(const struct device *dev)
-{
-	struct cros_system_npcx_data *data = DRV_DATA(dev);
-
-	return data->reset;
-}
-
-static int cros_system_npcx_init(const struct device *dev)
-{
-	struct scfg_reg *const inst_scfg = HAL_SCFG_INST(dev);
-	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
-	struct cros_system_npcx_data *data = DRV_DATA(dev);
-
-	/* check reset cause */
-	if (IS_BIT_SET(inst_twd->T0CSR, NPCX_T0CSR_WDRST_STS)) {
-		data->reset = WATCHDOG_RST;
-		inst_twd->T0CSR |= BIT(NPCX_T0CSR_WDRST_STS);
-	} else if (IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_DBGRST_STS)) {
-		data->reset = DEBUG_RST;
-		inst_scfg->RSTCTL |= BIT(NPCX_RSTCTL_DBGRST_STS);
-	} else if (IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) {
-		data->reset = VCC1_RST_PIN;
-	} else {
-		data->reset = POWERUP;
-	}
-
-	return 0;
-}
-
-static int cros_system_npcx_soc_reset(const struct device *dev)
-{
-	struct twd_reg *const inst_twd = HAL_TWD_INST(dev);
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable_all();
-
-	/*
-	 * NPCX chip doesn't have the specific system reset functionality. Use
-	 * watchdog reset as a system reset.
-	 */
-
-	/* Stop the watchdog */
-	system_npcx_watchdog_stop();
-
-	/* Initialize watchdog for reset */
-	system_npcx_init_watchdog_reset(dev);
-
-	/*
-	 * The trigger of a watchdog event by a "too early service" condition.
-	 * When the watchdog is written more than once during three watchdog
-	 * clock cycle.
-	 */
-	inst_twd->WDSDM = 0x5C;
-	inst_twd->WDSDM = 0x5C;
-
-	/* Wait for the soc reset. */
-	while (1) {
-		;
-	}
-
-	/* should never return */
-	return 0;
-}
-
-static int cros_system_npcx_hibernate(const struct device *dev,
-				      uint32_t seconds, uint32_t microseconds)
-{
-	/* Disable interrupt first */
-	interrupt_disable_all();
-
-	/* Stop the watchdog */
-	system_npcx_watchdog_stop();
-
-	/* Enter hibernate mode */
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_HIBERNATE_PSL)) {
-		system_npcx_hibernate_by_psl(dev, seconds, microseconds);
-	} else {
-		system_npcx_hibernate_by_disable_ram(dev, seconds,
-						     microseconds);
-	}
-
-	return 0;
-}
-
-__maybe_unused static uint64_t
-cros_system_npcx_deep_sleep_ticks(const struct device *dev)
-{
-	return npcx_clock_get_sleep_ticks();
-}
-
-static struct cros_system_npcx_data cros_system_npcx_dev_data;
-
-static const struct cros_system_npcx_config cros_system_dev_cfg = {
-	.base_scfg = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_scfg)),
-	.base_twd = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_watchdog)),
-	.base_mswc =
-		DT_REG_ADDR_BY_NAME(DT_INST(0, nuvoton_npcx_host_sub), mswc),
-};
-
-static const struct cros_system_driver_api cros_system_driver_npcx_api = {
-	.get_reset_cause = cros_system_npcx_get_reset_cause,
-	.soc_reset = cros_system_npcx_soc_reset,
-	.hibernate = cros_system_npcx_hibernate,
-	.chip_vendor = cros_system_npcx_get_chip_vendor,
-	.chip_name = cros_system_npcx_get_chip_name,
-	.chip_revision = cros_system_npcx_get_chip_revision,
-#ifdef CONFIG_SOC_POWER_MANAGEMENT_TRACE
-	.deep_sleep_ticks = cros_system_npcx_deep_sleep_ticks,
-#endif
-};
-
-DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL,
-	      &cros_system_npcx_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1,
-	      CONFIG_CROS_SYSTEM_NPCX_INIT_PRIORITY,
-	      &cros_system_driver_npcx_api);
-
-#if DT_NODE_EXISTS(DT_NODELABEL(dbg))
-#define HAL_DBG_REG_BASE_ADDR \
-	((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg)))
-
-#define DBG_NODE           DT_NODELABEL(dbg)
-#define DBG_PINCTRL_PH     DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0)
-#define DBG_ALT_FILED(f)   DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f)
-
-static int jtag_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-	struct dbg_reg *const dbg_reg_base = HAL_DBG_REG_BASE_ADDR;
-	const struct npcx_alt jtag_alts[] = {
-		{
-			.group = DBG_ALT_FILED(group),
-			.bit = DBG_ALT_FILED(bit),
-			.inverted = DBG_ALT_FILED(inv)
-		}
-	};
-
-	dbg_reg_base->DBGCTRL = 0x04;
-	dbg_reg_base->DBGFRZEN3 &= ~BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
-	if (DT_NODE_HAS_STATUS(DT_NODELABEL(dbg), okay))
-		npcx_pinctrl_mux_configure(jtag_alts, 1, 1);
-
-	return 0;
-}
-#if CONFIG_KERNEL_INIT_PRIORITY_DEFAULT >= 41
-#error "jtag_init must be called after default kernel init"
-#endif
-SYS_INIT(jtag_init, PRE_KERNEL_1, 41);
-#endif /* DT_NODE_EXISTS(DT_NODELABEL(dbg)) */
diff --git a/zephyr/dts/bindings/adc/named-adc.yaml b/zephyr/dts/bindings/adc/named-adc.yaml
deleted file mode 100644
index 6f06d73b86..0000000000
--- a/zephyr/dts/bindings/adc/named-adc.yaml
+++ /dev/null
@@ -1,107 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: ADC parent node
-
-compatible: "named-adc-channels"
-
-child-binding:
-  description: Named ADCs child node
-  properties:
-    label:
-      required: true
-      type: string
-      description:
-        Human-readable string describing the device (used as
-        device_get_binding() argument)
-    channel:
-      required: true
-      type: int
-      description: ADC channel used
-    mul:
-      required: false
-      type: int
-      default: 1
-      description: Multiplication factor of ADC measurement
-    div:
-      required: false
-      type: int
-      default: 1
-      description: Division factor of ADC measurement
-    gain:
-      required: false
-      type: string
-      description:
-        Gain selection for the ADC channel. Source of valid gain settings is
-        "enum adc_gain" found in <zephyr-base>/include/drivers/adc.h
-      enum:
-        - ADC_GAIN_1_6
-        - ADC_GAIN_1_5
-        - ADC_GAIN_1_4
-        - ADC_GAIN_1_3
-        - ADC_GAIN_1_2
-        - ADC_GAIN_2_3
-        - ADC_GAIN_1
-        - ADC_GAIN_2
-        - ADC_GAIN_3
-        - ADC_GAIN_4
-        - ADC_GAIN_8
-        - ADC_GAIN_16
-        - ADC_GAIN_32
-        - ADC_GAIN_64
-        - ADC_GAIN_128
-      default: ADC_GAIN_1
-    reference:
-      required: false
-      type: string
-      description:
-        Sets the reference voltage for the ADC channel. Source of valid
-        reference voltages is "enum adc_reference" found in
-        <zephyr-base>/include/drivers/adc.
-      enum:
-        - ADC_REF_VDD_1
-        - ADC_REF_VDD_1_2
-        - ADC_REF_VDD_1_3
-        - ADC_REF_VDD_1_4
-        - ADC_REF_INTERNAL
-        - ADC_REF_EXTERNAL0
-        - ADC_REF_EXTERNAL1
-      default: ADC_REF_INTERNAL
-    acquisition-time:
-      required: false
-      type: int
-      description:
-        Set the acquisition time for ADC conversion. Use the ADC_ACQ_TIME macro
-        to compose this value. If the hardware doesn't support a configurable
-        acquisition time, use ADC_ACQ_TIME_DEFAULT (0).
-      default: 0
-    differential:
-      required: false
-      type: boolean
-      description:
-        Set the ADC acquisition mode to differential. Default mode is
-        single-ended acquisition.
-    enum-name:
-      type: string
-      required: true
-      description:
-        Enum values used in the source code to refer to the ADC channels
-      enum:
-      - ADC_AMON_BMON
-      - ADC_BOARD_ID_0
-      - ADC_BOARD_ID_1
-      - ADC_PMON
-      - ADC_PSYS
-      - ADC_TEMP_SENSOR_CHARGER
-      - ADC_TEMP_SENSOR_DDR_SOC
-      - ADC_TEMP_SENSOR_FAN
-      - ADC_TEMP_SENSOR_PP3300_REGULATOR
-      - ADC_VBUS
-      - ADC_VBUS_C0
-      - ADC_VBUS_C1
-      - ADC_EVB_CH_0
-      - ADC_EVB_CH_1
-      - ADC_EVB_CH_2
-      - ADC_EVB_CH_3
-      - ADC_EVB_CH_4
diff --git a/zephyr/dts/bindings/battery/as3gwrc3ka,c235-41.yaml b/zephyr/dts/bindings/battery/as3gwrc3ka,c235-41.yaml
deleted file mode 100644
index c4359b29d2..0000000000
--- a/zephyr/dts/bindings/battery/as3gwrc3ka,c235-41.yaml
+++ /dev/null
@@ -1,56 +0,0 @@
-description: "AS3GWRc3KA C235-41"
-compatible: "as3gwrc3ka,c235-41"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "as3gwrc3ka,c235-41"
-
-   # Fuel gauge
-   manuf_name:
-      default: "AS3GWRc3KA"
-   device_name:
-      default: "C235-41"
-   ship_mode_reg_addr:
-      default: 0x00
-   ship_mode_reg_data:
-      default: [ 0x10, 0x10 ]
-   # Documentation: b/150833879
-   # Charging/Discharging FETs Status
-   # Register SBS_PackStatus_ACCESS (0x99)
-   # Bit-3: XDSG
-   # Bit-2: XCHG
-   fet_reg_addr:
-      default: 0x99
-   fet_reg_mask:
-      default: 0x08
-   fet_disconnect_val:
-      default: 0x08
-   fet_cfet_mask:
-      default: 0x04
-   fet_cfet_off_val:
-      default: 0x04
-
-   # Battery info
-   voltage_max:
-      default: 8800
-   voltage_normal:
-      default: 7700
-   voltage_min:
-      default: 6000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 45
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: 0
-   discharging_max_c:
-      default: 60
diff --git a/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml b/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
deleted file mode 100644
index 2572090024..0000000000
--- a/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
+++ /dev/null
@@ -1,85 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: |
-   Battery fuel gauge parameters
-
-compatible: "battery-fuel-gauge"
-
-properties:
-   manuf_name:
-      description: Manufacturer name
-      type: string
-   device_name:
-      description: Model/Device name
-      type: string
-   ship_mode_wb_support:
-      description: |
-         Write Block support. If this is true, then i2c write block command
-         will be used instead of a 16-bit write
-         Value must be either 0 or 1.
-      type: int
-   ship_mode_reg_addr:
-      description: |
-         Address of register responsible for enabling ship mode.
-      type: int
-   ship_mode_reg_data:
-      description: |
-         Values written to register to enable ship mode.
-      type: array
-   sleep_mode_support:
-      description: |
-         Defines if battery support fuel gauge sleep command.
-         Value must be either 0 or 1.
-      type: int
-   sleep_mode_reg_addr:
-      description: |
-         Defines address where command will be sent to go into sleep mode.
-      type: int
-   sleep_mode_reg_data:
-      description: |
-         Defines value which will be sent to register to go into sleep mode.
-      type: int
-   fet_mfgacc_support:
-      description: |
-         Defines if battery supports manufacturer access command.
-         If enabled, FET status is read using the ManufacturerBlockAccess (0x44)
-         to read the OperationStatus (0x54) register.
-         The fet_reg_mask and fet_disconnect_val properties must still be
-         defined.
-         Value must be either 0 or 1.
-      type: int
-   fet_reg_addr:
-      description: |
-         Address of register which reports charging and discharging FETs status.
-         This property is ignored if fet_mfgacc_support is true.
-      type: int
-   fet_reg_mask:
-      description: |
-         Mask which determines which bit in status value contains the
-         discharge FET status.
-      type: int
-   fet_disconnect_val:
-      description: |
-         Value that describes which bits must be set to determine that
-         discharge FET has disconnected the battery.
-      type: int
-   fet_cfet_mask:
-      description: |
-         Mask which determines which bit in status value contains the
-         charge FET status. If this value is 0, this means there's
-         no charge FET.
-      type: int
-   fet_cfet_off_val:
-      description: |
-         Value that describes which bits must be set to determine that
-         charge FET has disconnected the battery.
-      type: int
-   imbalance_mv:
-      description: |
-         This property is used only if
-         CONFIG_PLATFORM_EC_BATTERY_MEASURE_IMBALANCE is enabled.
-         It should be an enum and its value should be a name of function
-         which will be assigned to imbalance_mv pointer.
-      type: string
diff --git a/zephyr/dts/bindings/battery/battery-info.yaml b/zephyr/dts/bindings/battery/battery-info.yaml
deleted file mode 100644
index 3a4cb875e7..0000000000
--- a/zephyr/dts/bindings/battery/battery-info.yaml
+++ /dev/null
@@ -1,71 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description:
-   Information about battery
-   Voltage is in millivolts
-   Current is in milliamperes
-   Temperature is in Celsius degrees
-
-compatible: "battery-info"
-
-properties:
-   voltage_max:
-      description: |
-         Maximum voltage that can be applied to the battery.
-      type: int
-   voltage_normal:
-      description: |
-         Nominal voltage of the battery.
-      type: int
-   voltage_min:
-      description: |
-         Minimum voltage of the battery.
-         If current voltage is below this value, system will shutdown.
-      type: int
-   precharge_voltage:
-      description: |
-         Voltage used during the precharge phase. Not all chargers
-         may take these into account.
-      type: int
-   precharge_current:
-      description: |
-         Maximum current used during the precharge phase.
-      type: int
-   start_charging_min_c:
-      description: |
-         Minimum temperature of battery to start charging it.
-         This value is used only if
-         CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
-      type: int
-   start_charging_max_c:
-      description: |
-         Maximum temperature of battery to start charging it.
-         This value is used only if
-         CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
-      type: int
-   charging_min_c:
-      description: |
-         Minimum temperature of battery during charging it. If the battery
-         temperature falls below this value, charging will be stopped.
-         This value is used only if
-         CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
-      type: int
-   charging_max_c:
-      description: |
-         Maximum temperature of battery during charging it. If the battery
-         temperature raises above this value, charging will be stopped.
-         This value is used only if
-         CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS is enabled.
-      type: int
-   discharging_min_c:
-      description: |
-         Minimum working temperature of battery.
-         If temperature is below this value, the system will shutdown.
-      type: int
-   discharging_max_c:
-      description: |
-         Maximum working temperature of battery.
-         If temperature is above this value, the system will shutdown.
-      type: int
diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml
deleted file mode 100644
index ce0a330077..0000000000
--- a/zephyr/dts/bindings/battery/battery-smart.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-compatible: "battery-smart"
-
-include: [ "base.yaml", "battery-info.yaml", "battery-fuel-gauge.yaml" ]
-
-properties:
-   enum-name:
-      description: Unique value used for creating enum of batteries types
-      type: string
-      enum:
-         - "as3gwrc3ka,c235-41"
-         - "lgc,ap16l8j"
-         - "lgc,ap18c8k"
-         - "murata,ap18c4k"
-         - "panasonic,ap16l5j"
-         - "panasonic,ap16l5j-009"
diff --git a/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml b/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml
deleted file mode 100644
index e57cf48e24..0000000000
--- a/zephyr/dts/bindings/battery/lgc,ap16l8j.yaml
+++ /dev/null
@@ -1,55 +0,0 @@
-description: "LGC KT0020G010 AP16L8J"
-compatible: "lgc,ap16l8j"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "lgc,ap16l8j"
-
-   # Fuel gauge
-   manuf_name:
-      default: "LGC KT0020G010"
-   device_name:
-      default: "AP16L8J"
-   ship_mode_reg_addr:
-      default: 0x3A
-   ship_mode_reg_data:
-      default: [ 0xC574, 0xC574 ]
-   # Documentation: b/148625782
-   # ManufacturerAccess() 0x0054 OperationStatus
-   # CHG (Bit 2): CHG FET status (1 = Active 0 = Inactive)
-   # DSG (Bit 1): DSG FET status (1 = Active 0 = Inactive)
-   fet_mfgacc_support:
-      default: 1
-   fet_reg_mask:
-      default: 0x0002
-   fet_disconnect_val:
-      default: 0x0000
-   fet_cfet_mask:
-      default: 0x0004
-   fet_cfet_off_val:
-      default: 0x0000
-
-   # Battery info
-   voltage_max:
-      default: 8700
-   voltage_normal:
-      default: 7500
-   voltage_min:
-      default: 6000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 50
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: -20
-   discharging_max_c:
-      default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml b/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml
deleted file mode 100644
index b997004f3d..0000000000
--- a/zephyr/dts/bindings/battery/lgc,ap18c8k.yaml
+++ /dev/null
@@ -1,57 +0,0 @@
-description: "LGC KT0030G020 AP18C8K"
-compatible: "lgc,ap18c8k"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "lgc,ap18c8k"
-
-   # Fuel gauge
-   manuf_name:
-      default: "LGC KT0030G020"
-   device_name:
-      default: "AP18C8K"
-   ship_mode_reg_addr:
-      default: 0x3A
-   ship_mode_reg_data:
-      default: [ 0xC574, 0xC574 ]
-   # Documentation: b/130608940
-   # Command Code: 0x43
-   # Bit 0 - DFET - Condition of D-FET ( 0=OFF, 1=ON )
-   # Bit 1 - CFET - Condition of C-FET ( 0=OFF, 1=ON )
-   fet_mfgacc_support:
-      default: 0
-   fet_reg_addr:
-      default: 0x43
-   fet_reg_mask:
-      default: 0x0001
-   fet_disconnect_val:
-      default: 0x0000
-   fet_cfet_mask:
-      default: 0x0002
-   fet_cfet_off_val:
-      default: 0x0000
-
-   # Battery info
-   voltage_max:
-      default: 13050
-   voltage_normal:
-      default: 11250
-   voltage_min:
-      default: 9000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 50
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: -20
-   discharging_max_c:
-      default: 75
diff --git a/zephyr/dts/bindings/battery/murata,ap18c4k.yaml b/zephyr/dts/bindings/battery/murata,ap18c4k.yaml
deleted file mode 100644
index ca028b82cb..0000000000
--- a/zephyr/dts/bindings/battery/murata,ap18c4k.yaml
+++ /dev/null
@@ -1,57 +0,0 @@
-description: "Murata KT00304012 AP18C4K"
-compatible: "murata,ap18c4k"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "murata,ap18c4k"
-
-   # Fuel gauge
-   manuf_name:
-      default: "Murata KT00304012"
-   device_name:
-      default: "AP18C4K"
-   ship_mode_reg_addr:
-      default: 0x3A
-   ship_mode_reg_data:
-      default: [ 0xC574, 0xC574 ]
-   # Documentation: b/130615670
-   # Manufacturer Access 0x00
-   # b14: Charging Disabled (0: Off, 1: On)
-   # b13: Discharging Disabled (0: Off, 1: On)
-   fet_mfgacc_support:
-      default: 0
-   fet_reg_addr:
-      default: 0x0
-   fet_reg_mask:
-      default: 0x2000
-   fet_disconnect_val:
-      default: 0x2000
-   fet_cfet_mask:
-      default: 0x4000
-   fet_cfet_off_val:
-      default: 0x4000
-
-   # Battery info
-   voltage_max:
-      default: 13200
-   voltage_normal:
-      default: 11400
-   voltage_min:
-      default: 9000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 50
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: -20
-   discharging_max_c:
-      default: 75
diff --git a/zephyr/dts/bindings/battery/named-batteries.yaml b/zephyr/dts/bindings/battery/named-batteries.yaml
deleted file mode 100644
index 1c922e2100..0000000000
--- a/zephyr/dts/bindings/battery/named-batteries.yaml
+++ /dev/null
@@ -1,20 +0,0 @@
-description: Named Batteries parent node
-
-compatible: "named-batteries"
-
-# TODO(b/183544739): Move this to use compatible strings
-
-child-binding:
-    description: Named batteries child node
-    properties:
-       enum-name:
-          type: string
-          required: true
-          enum:
-            - "ap16l5j"
-            - "ap16l5j_009"
-            - "ap16l8j"
-            - "c235"
-            - "lgc011"
-            - "lgc_ap18c8k"
-            - "murata_ap18c4k"
diff --git a/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml b/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml
deleted file mode 100644
index 5791549092..0000000000
--- a/zephyr/dts/bindings/battery/panasonic,ap16l5j-009.yaml
+++ /dev/null
@@ -1,59 +0,0 @@
-description: "Panasonic KT00205009 AP16L5J"
-compatible: "panasonic,ap16l5j-009"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "panasonic,ap16l5j-009"
-
-   # Fuel gauge
-   manuf_name:
-      default: "PANASONIC KT00205009"
-   device_name:
-      default: "AP16L5J"
-   ship_mode_reg_addr:
-      default: 0x3A
-   ship_mode_reg_data:
-      default: [ 0xC574, 0xC574 ]
-   # Documentation: b/144674480
-   # ManufacturerAccess() 0x00
-   # Bit14 Discharge FET status
-   # Set - Discharge FET is ON, Reset - Discharge FET is OFF
-   # Bit15 Charge FET status
-   # Set - Charge FET is ON, Reset - Charge FET is OFF
-   fet_mfgacc_support:
-      default: 0
-   fet_reg_addr:
-      default: 0x0
-   fet_reg_mask:
-      default: 0x4000
-   fet_disconnect_val:
-      default: 0x0000
-   fet_cfet_mask:
-      default: 0x8000
-   fet_cfet_off_val:
-      default: 0x0000
-
-   # Battery info
-   voltage_max:
-      default: 8800
-   voltage_normal:
-      default: 7700
-   voltage_min:
-      default: 6000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 50
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: -20
-   discharging_max_c:
-      default: 75
diff --git a/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml b/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml
deleted file mode 100644
index fe0923dd87..0000000000
--- a/zephyr/dts/bindings/battery/panasonic,ap16l5j.yaml
+++ /dev/null
@@ -1,59 +0,0 @@
-description: "Panasonic AP16L5J"
-compatible: "panasonic,ap16l5j"
-
-include: battery-smart.yaml
-
-properties:
-   enum-name:
-      type: string
-      default: "panasonic,ap16l5j"
-
-   # Fuel gauge
-   manuf_name:
-      default: "PANASONIC"
-   device_name:
-      default: "AP16L5J"
-   ship_mode_reg_addr:
-      default: 0x3A
-   ship_mode_reg_data:
-      default: [ 0xC574, 0xC574 ]
-   # Documentation: b/144674480
-   # ManufacturerAccess() 0x00
-   # Bit14 Discharge FET status
-   # Set - Discharge FET is ON, Reset - Discharge FET is OFF
-   # Bit15 Charge FET status
-   # Set - Charge FET is ON, Reset - Charge FET is OFF
-   fet_mfgacc_support:
-      default: 0
-   fet_reg_addr:
-      default: 0x0
-   fet_reg_mask:
-      default: 0x4000
-   fet_disconnect_val:
-      default: 0x0000
-   fet_cfet_mask:
-      default: 0x8000
-   fet_cfet_off_val:
-      default: 0x0000
-
-   # Battery info
-   voltage_max:
-      default: 8800
-   voltage_normal:
-      default: 7700
-   voltage_min:
-      default: 6000
-   precharge_current:
-      default: 256
-   start_charging_min_c:
-      default: 0
-   start_charging_max_c:
-      default: 50
-   charging_min_c:
-      default: 0
-   charging_max_c:
-      default: 60
-   discharging_min_c:
-      default: -20
-   discharging_max_c:
-      default: 75
diff --git a/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml b/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml
deleted file mode 100644
index f97d688727..0000000000
--- a/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description:
-    Possible CBI SSFC field values.
-    It has to be defied as grandchild on the "named-cbi-ssfc"
-
-compatible: "named-cbi-ssfc-value"
-
-properties:
-    value:
-        type: int
-        required: true
-        description:
-          Unique value of CBI SSFC field
-    default:
-        type: boolean
-        description:
-          Indicates that the specified value is default for the parent
-          CBI SSFC field node. It should appear only once for the CBI SSFC
-          definition.
diff --git a/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml b/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml
deleted file mode 100644
index bd6c1d535b..0000000000
--- a/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: CBI Second Source Factory Cache (SSFC)
-
-compatible: "named-cbi-ssfc"
-
-child-binding:
-    description:
-        CBI SSFC fields definition.
-        The order of the children in this node define the order
-        of the SSFC bit fields from least significant bit to most
-        significant bit. The total size of all SSFC bit fields
-        must not exceed 32 bits.
-    properties:
-        enum-name:
-            type: string
-            required: true
-            description:
-              Enum values used only for description purposes
-            enum:
-            - BASE_SENSOR
-            - LID_SENSOR
-            - LIGHTBAR
-            - USB_SS_MUX
-        size:
-            type: int
-            required: true
-            description: The size of the field in bits.
-
-# Example:
-#
-# cbi-ssfc {
-#     compatible = "named-cbi-ssfc";
-#
-#     base_sensor {
-#         enum-name = "BASE_SENSOR";
-#         size = <3>;
-#         bmi160 {
-#             compatible = "named-cbi-ssfc-value";
-#             status = "okay";
-#
-#             value = <1>;
-#             devices = <&alt_base_accel &alt_base_gyro>;
-#         };
-#         kx022 {
-#             compatible = "named-cbi-ssfc-value";
-#             status = "okay";
-#
-#             value = <3>;
-#             devices = <&base_accel_kx022>;
-#         };
-#     };
-# };
\ No newline at end of file
diff --git a/zephyr/dts/bindings/charger/intersil,isl9238.yaml b/zephyr/dts/bindings/charger/intersil,isl9238.yaml
deleted file mode 100644
index 08e00bf313..0000000000
--- a/zephyr/dts/bindings/charger/intersil,isl9238.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Intersil ISL9238 Charger IC
-
-compatible: "intersil,isl9238"
-
-include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/charger/intersil,isl9241.yaml b/zephyr/dts/bindings/charger/intersil,isl9241.yaml
deleted file mode 100644
index 7557b949d8..0000000000
--- a/zephyr/dts/bindings/charger/intersil,isl9241.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Intersil ISL9241 Charger IC
-
-compatible: "intersil,isl9241"
-
-include: i2c-device.yaml
-
-properties:
-    switching-frequency:
-      type: int
-      required: false
-      description:
-        Sets the charger switching frequency. If not defined then the switching
-        frequency is configured by the resistor connected to the PROG pin on
-        the board.
diff --git a/zephyr/dts/bindings/console/ec-console.yaml b/zephyr/dts/bindings/console/ec-console.yaml
deleted file mode 100644
index f79ddd67b0..0000000000
--- a/zephyr/dts/bindings/console/ec-console.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: EC Console node
-
-compatible: "ec-console"
-
-properties:
-    disabled:
-        required: false
-        type: string-array
-        description:
-          List of EC channel names that are disabled in the output by default.
diff --git a/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml b/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
deleted file mode 100644
index 8b12473d0a..0000000000
--- a/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright (c) 2021 Google Inc.
-# SPDX-License-Identifier: Apache-2.0
-description: Named battery-backed RAM parent node
-
-compatible: "named-bbram-regions"
-
-child-binding:
-    description: Named battery-backed RAM child node
-    properties:
-        offset:
-            type: int
-            required: true
-        size:
-            type: int
-            required: true
diff --git a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
deleted file mode 100644
index 109fa11d50..0000000000
--- a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright (c) 2021 Google Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-description: Nuvoton, NPCX Debug Interface
-
-compatible: "nuvoton,npcx-cros-dbg"
-
-include: base.yaml
-
-properties:
-    reg:
-        required: true
-
-    pinctrl-0:
-        type: phandles
-        required: true
-        description: configurations of pinmux controllers
diff --git a/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml b/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
deleted file mode 100644
index 991f3c71cf..0000000000
--- a/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Describes the size and offset of the RO and RW regions
-
-compatible: "cros-ec,flash-layout"
-
-include: base.yaml
-
-properties:
-  type:
-    type: string
-    required: true
-    description: >-
-      A property required by the binman utility, defined here only to
-      prevent Zephyr's binding generator from erroring about
-      additional properties.
-
-      The property should be set to the value "section" (done by
-      binman.dtsi) and should not be used anywhere in C code.
-
-      See README.entries in binman for a description of what binman
-      uses this for.
-  offset:
-    type: int
-    required: true
-    description: >-
-      The offset of the flash region from the base of the flash.
-  size:
-    type: int
-    required: true
-    description: >-
-      The size of the flash region, in bytes.
-  read-only:
-    type: boolean
-    required: false
-    description: >-
-      Set if the section should be read-only.
diff --git a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
deleted file mode 100644
index b9c8a9f149..0000000000
--- a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# Common fields for Chrome OS flash devices
-
-include: base.yaml
-
-bus: crosflash
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml b/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml
deleted file mode 100644
index 23c0f92c9c..0000000000
--- a/zephyr/dts/bindings/cros_flash/nuvoton,npcx-cros-flash.yaml
+++ /dev/null
@@ -1,24 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: Nuvoton, NPCX-cros-flash node
-
-compatible: "nuvoton,npcx-cros-flash"
-
-include: cros-flash-controller.yaml
-
-properties:
-    reg:
-        required: true
-
-    clocks:
-        required: true
-
-    size:
-        type: int
-        required: true
-
-    pinctrl-0:
-        type: phandles
-        required: true
-        description: configurations of pinmux controllers
diff --git a/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml b/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml
deleted file mode 100644
index e8c95419e1..0000000000
--- a/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# Common fields for Chrome OS raw keyboard devices
-
-include: base.yaml
-
-bus: croskb
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
deleted file mode 100644
index 7544039ffc..0000000000
--- a/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: Nuvoton, NPCX-cros-kb-raw node
-
-compatible: "nuvoton,npcx-cros-kb-raw"
-
-include: cros-kb-raw-controller.yaml
-
-properties:
-    reg:
-        required: true
-
-    clocks:
-        required: true
-
-    pinctrl-0:
-        type: phandles
-        required: true
-        description: configurations of pinmux controllers
-
-    wui_maps:
-        type: phandles
-        required: true
-        description: |
-            Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device.
-            Please notice not all IOs connect to WUIs.
-
-            In this case, it will be presented by wui_none.
-            For example the WUI mapping on NPCX7 KSI pads would be
-               wui_maps = <&wui_io30 &wui_io31 &wui_io27 &wui_io26
-                           &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
diff --git a/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml b/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml
deleted file mode 100644
index 73f0e8fdca..0000000000
--- a/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: EC MKBP Event node
-
-compatible: "ec-wake-mask-event"
-
-properties:
-  wakeup-mask:
-    required: false
-    type: int
-    default: 0
-    description:
-      Define the MKBP or host events that will wake up the application
-      processor from suspend mode.
-      HOST_EVENT_MASK should be used for ec-mkbp-host-event-wakeup-mask e.g.
-      ec-mkbp-host-event-wakeup-mask {
-        compatible = "ec-wake-mask-event";
-        wakeup-mask = <(
-          HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) |
-          HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) |
-          HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) |
-          HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) |
-          HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) |
-          HOST_EVENT_MASK(HOST_EVENT_RTC) |
-          HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE) |
-          HOST_EVENT_MASK(HOST_EVENT_DEVICE))>;
-      };
diff --git a/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml b/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml
deleted file mode 100644
index f754826404..0000000000
--- a/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# Common fields for Chrome OS RTC devices
-
-include: base.yaml
-
-bus: crosrtc
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml b/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
deleted file mode 100644
index 547b6897e8..0000000000
--- a/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2021 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: Nuvoton, NPCX Monotonic Counter (MTC) node
-
-compatible: "nuvoton,npcx-cros-mtc"
-
-include: base.yaml
-
-properties:
-    reg:
-      required: true
-
-    label:
-      required: true
-
-    mtc-alarm:
-      type: phandle
-      required: true
-      description: |
-        Mapping table between Wake-Up Input (WUI) and monotonic counter alarm
-        signal.
-
-        For example, the WUI mapping on NPCX7 monotonic counter alarm would be
-           mtc-alarm = <&wui_mtc>;
-
diff --git a/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml b/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
deleted file mode 100644
index 7717649ede..0000000000
--- a/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: NXP, Real-Time Clock
-
-compatible: "nxp,rtc-pcf85063a"
-
-include: [base.yaml, i2c-device.yaml]
-
-properties:
-    label:
-      required: true
-
-    int-gpios:
-      type: phandle-array
-      required: true
-      description: Interrupt from RTC
diff --git a/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml b/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
deleted file mode 100644
index a741a98aef..0000000000
--- a/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: RENESAS, Real-Time Clock
-
-compatible: "renesas,rtc-idt1337ag"
-
-include: [base.yaml, i2c-device.yaml]
-
-properties:
-    label:
-      required: true
-
-    int-gpios:
-      type: phandle-array
-      required: true
-      description: Interrupt from RTC
diff --git a/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml
deleted file mode 100644
index 3e5a32f63f..0000000000
--- a/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: ITE, IT8XXX2 Serial Host Interface (SHI) node
-
-compatible: "ite,it8xxx2-cros-shi"
-
-include: base.yaml
-
-properties:
-    reg:
-      required: true
-
-    pinctrl-0:
-        type: phandles
-        required: true
-        description: Configuration of SHI pinmux controller
diff --git a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
deleted file mode 100644
index c13f3e2b5a..0000000000
--- a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
+++ /dev/null
@@ -1,31 +0,0 @@
-# Copyright (c) 2021 Google Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-description: Nuvoton, NPCX Serial Host Interface (SHI) node
-
-compatible: "nuvoton,npcx-cros-shi"
-
-include: base.yaml
-
-properties:
-    reg:
-      description: mmio register space
-      required: true
-
-    clocks:
-        required: true
-        description: configurations of device source clock controller
-
-    pinctrl-0:
-        type: phandles
-        required: true
-        description: configurations of pinmux controllers
-
-    shi-cs-wui:
-        type: phandle
-        required: true
-        description: |
-            Mapping table between Wake-Up Input (WUI) and SHI_CS signal.
-
-            For example the WUI mapping on NPCX7 would be
-               shi-cs-wui = <&wui_io53>;
diff --git a/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml b/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml
deleted file mode 100644
index 007a73b17b..0000000000
--- a/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml
+++ /dev/null
@@ -1,30 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr BB retimer Emulator
-
-compatible: "cros,bb-retimer-emul"
-
-include: base.yaml
-
-properties:
-    vendor:
-        type: string
-        required: true
-        enum:
-          - BB_RETIMER_VENDOR_ID_1
-          - BB_RETIMER_VENDOR_ID_2
-        description: Vendor ID used by device that is emulated.
-
-    error-on-ro-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when read only register
-          is being written.
-
-    error-on-reserved-bit-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when reserved bit
-          is being written.
diff --git a/zephyr/dts/bindings/emul/cros,i2c-mock.yaml b/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
deleted file mode 100644
index 7da69028bd..0000000000
--- a/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: A generic I2C mock
-
-compatible: "cros,i2c-mock"
-
-include: base.yaml
-properties:
-   reg:
-     required: true
diff --git a/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml b/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
deleted file mode 100644
index 44c29fbe56..0000000000
--- a/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: CROS implementation of the LIS2DW12 emulator
-
-compatible: "cros,lis2dw12-emul"
-
-include: base.yaml
-properties:
-  reg:
-    required: true
diff --git a/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml b/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
deleted file mode 100644
index 811f77206f..0000000000
--- a/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Cros LN9310 Emulator
-
-compatible: "cros,ln9310-emul"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
diff --git a/zephyr/dts/bindings/emul/zephyr,bma255.yaml b/zephyr/dts/bindings/emul/zephyr,bma255.yaml
deleted file mode 100644
index 40750196c1..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,bma255.yaml
+++ /dev/null
@@ -1,83 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr BMA255 Emulator
-
-compatible: "zephyr,bma255"
-
-include: base.yaml
-
-properties:
-    nvm-off-x:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer offset of x axis stored in NVM.
-
-    nvm-off-y:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer offset of y axis stored in NVM.
-
-    nvm-off-z:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer offset of z axis stored in NVM.
-
-    nvm-gp0:
-        type: int
-        required: false
-        default: 0
-        description: GP0 value stored in NVM.
-
-    nvm-gp1:
-        type: int
-        required: false
-        default: 0
-        description: GP1 value stored in NVM.
-
-    nvm-acc-x:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer value of x axis used until new value is set.
-
-    nvm-acc-y:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer value of y axis used until new value is set.
-
-    nvm-acc-z:
-        type: int
-        required: false
-        default: 0
-        description: Accelerometer value of z axis used until new value is set.
-
-    error-on-compensation-not-ready:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when fast compensation
-          is started when not ready bit is set.
-
-    error-on-ro-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when read only register
-          is being written.
-
-    error-on-reserved-bit-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when reserved bit
-          is being written.
-
-    error-on-msb-first-access:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when MSB register of
-          accelerometer value is accessed before LSB and shadowing is enabled
-          at the same time.
diff --git a/zephyr/dts/bindings/emul/zephyr,bmi.yaml b/zephyr/dts/bindings/emul/zephyr,bmi.yaml
deleted file mode 100644
index a754287bcc..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,bmi.yaml
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr BMI Emulator
-
-compatible: "zephyr,bmi"
-
-include: base.yaml
-
-properties:
-    device-model:
-        type: string
-        required: true
-        enum:
-          - BMI_EMUL_160
-          - BMI_EMUL_260
-        description: Model of device that is emulated.
-
-    error-on-ro-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when read only register
-          is being written.
-
-    error-on-wo-read:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when write only register
-          is being read.
-
-    error-on-reserved-bit-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when reserved bit
-          is being written.
-
-    simulate-command-exec-time:
-        type: boolean
-        description:
-          Flag indicating if emulator should wait the same amount of time before
-          finishing command as real device would.
diff --git a/zephyr/dts/bindings/emul/zephyr,pi3usb9201.yaml b/zephyr/dts/bindings/emul/zephyr,pi3usb9201.yaml
deleted file mode 100644
index 856703e9d7..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,pi3usb9201.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr pi3usb9201 Emulator
-
-compatible: "zephyr,pi3usb9201-emul"
-
-include: base.yaml
diff --git a/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml b/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml
deleted file mode 100644
index cc1d2f368d..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml
+++ /dev/null
@@ -1,155 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr Smart Battery Emulator
-
-compatible: "zephyr,smart-battery"
-
-include: base.yaml
-
-properties:
-    mf-access:
-        type: int
-        required: false
-        default: 0
-        description: Word returned on manufacturer access command.
-
-    at-rate-full-mw-support:
-        type: boolean
-        description:
-          Flag indicating if AT_RATE_TIME_TO_FULL command supports mW capacity
-          mode.
-
-    version:
-        type: string
-        required: false
-        enum:
-          - BATTERY_SPEC_VER_1_0
-          - BATTERY_SPEC_VER_1_1
-          - BATTERY_SPEC_VER_1_1_WITH_PEC
-        default: BATTERY_SPEC_VER_1_1_WITH_PEC
-        description: Version of Smart Battery.
-
-    vscale:
-        type: int
-        required: false
-        default: 0
-        description: Scaling of voltage.
-
-    ipscale:
-        type: int
-        required: false
-        default: 0
-        description: Scaling of current.
-
-    int-charge-controller:
-        type: boolean
-        description: Flag indicating if internal charge controller is supported.
-
-    primary-battery:
-        type: boolean
-        description:
-          Flag indicating if primary battery role selection is supported.
-
-    design-mv:
-        type: int
-        required: false
-        default: 5000
-        description: Design battery voltage in mV.
-
-    design-cap:
-        type: int
-        required: false
-        default: 5000
-        description: Design battery capacity in mAh.
-
-    temperature:
-        type: int
-        required: false
-        default: 2930
-        description: Battery temperature in 0.1 Kelvins.
-
-    volt:
-        type: int
-        required: false
-        default: 5000
-        description: Battery voltage in mV.
-
-    cur:
-        type: int
-        required: false
-        default: 1000
-        description: Current charging (> 0) or discharging (< 0) battery in mA.
-
-    avg-cur:
-        type: int
-        required: false
-        default: 1000
-        description: Average current from 1 minute.
-
-    max-error:
-        type: int
-        required: false
-        default: 0
-        description: Maximum error of commands return value in percent.
-
-    cap:
-        type: int
-        required: false
-        default: 2000
-        description: Capacity of the battery in mAh.
-
-    full-cap:
-        type: int
-        required: false
-        default: 4000
-        description: Full capacity of the battery in mAh.
-
-    desired-charg-cur:
-        type: int
-        required: false
-        default: 2000
-        description: Charging current requested by battery.
-
-    desired-charg-volt:
-        type: int
-        required: false
-        default: 7000
-        description: Charging voltage requested by battery.
-
-    cycle-count:
-        type: int
-        required: false
-        default: 125
-        description: Number of cycles.
-
-    serial-number:
-        type: int
-        required: false
-        default: 7
-        description: Serial number of battery.
-
-    mf-name:
-        type: string
-        required: false
-        default: "zephyr"
-        description: Manufacturer name. Length has to be smaller than 32 bytes.
-
-    dev-name:
-        type: string
-        required: false
-        default: "smartbat"
-        description: Device name. Length has to be smaller than 32 bytes.
-
-    dev-chem:
-        type: string
-        required: false
-        default: "LION"
-        description: Device chemistry. Length has to be smaller than 32 bytes.
-
-    mf-data:
-        type: string
-        required: false
-        default: "LION"
-        description: Manufacturer data. Length has to be smaller than 32 bytes.
diff --git a/zephyr/dts/bindings/emul/zephyr,syv682x.yaml b/zephyr/dts/bindings/emul/zephyr,syv682x.yaml
deleted file mode 100644
index 75de7cf743..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,syv682x.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr SYV682X Emulator
-
-compatible: "zephyr,syv682x-emul"
-
-include: base.yaml
diff --git a/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml b/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml
deleted file mode 100644
index a4474ec279..0000000000
--- a/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml
+++ /dev/null
@@ -1,44 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Zephyr ALS TCS3400 light sensor i2c emulator
-
-compatible: "zephyr,tcs3400"
-
-include: base.yaml
-
-properties:
-    device-id:
-        type: string
-        required: false
-        enum:
-          - TCS340015_DEVICE_ID
-          - TCS340037_DEVICE_ID
-        default: TCS340015_DEVICE_ID
-        description: Device ID that is set in the register.
-
-    revision:
-        type: int
-        required: false
-        default: 0
-        description: Wafer die revision level that is set in the register.
-
-    error-on-ro-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when read only register
-          is being written.
-
-    error-on-reserved-bit-write:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when reserved bit
-          is being written.
-
-    error-on-msb-first-access:
-        type: boolean
-        description:
-          Flag indicating if error should be generated when MSB register of
-          accelerometer value is accessed before LSB and shadowing is enabled
-          at the same time.
diff --git a/zephyr/dts/bindings/fan/named-fans.yaml b/zephyr/dts/bindings/fan/named-fans.yaml
deleted file mode 100644
index 0595a20f54..0000000000
--- a/zephyr/dts/bindings/fan/named-fans.yaml
+++ /dev/null
@@ -1,63 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Fan parent node
-
-compatible: "named-fans"
-
-child-binding:
-  description: Named fan's child node
-  properties:
-    label:
-      required: true
-      type: string
-      description:
-        Human-readable string describing the device (used as
-        device_get_binding() argument)
-    rpm_min:
-      required: true
-      type: int
-      description:
-        Minimum fan speed (in RPM) to keep turning
-    rpm_start:
-      required: true
-      type: int
-      description:
-        Fan speed (in RPM) to begin turning
-    rpm_max:
-      required: true
-      type: int
-      description:
-        Maximum fan speed (in RPM)
-    pwm:
-      type: phandle
-      required: true
-      description:
-        PWM channel to control the fan
-    tach:
-      type: phandle
-      required: false
-      description:
-        Tachometer to measure the fan speed
-    not_use_rpm_mode:
-      required: false
-      type: boolean
-      description:
-        Disable automatic RPM control using tachometer input
-    use_fast_start:
-      required: false
-      type: boolean
-      description:
-        Fan requires a higher duty cycle to start up than to keep
-        running
-    pgood_gpio:
-      required: false
-      type: phandle
-      description:
-        Active high input GPIO which signals the power is good
-    enable_gpio:
-      required: false
-      type: phandle
-      description:
-        Active high output GPIO to enable the power
diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
deleted file mode 100644
index b7fc3809ac..0000000000
--- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
+++ /dev/null
@@ -1,180 +0,0 @@
-description: Named GPIOs parent node
-properties:
-  enum-name:
-    type: string
-    description:
-      Enum used in code.
-    enum:
-      - GPIO_ACCEL_GYRO_INT_L
-      - GPIO_AC_PRESENT
-      - GPIO_ALS_RGB_INT_ODL
-      - GPIO_AP_EC_WARM_RST_REQ
-      - GPIO_AP_EC_WATCHDOG_L
-      - GPIO_AP_IN_SLEEP_L
-      - GPIO_AP_RST_L
-      - GPIO_AP_SUSPEND
-      - GPIO_AP_XHCI_INIT_DONE
-      - GPIO_BASE_IMU_INT_L
-      - GPIO_BATT_PRES_ODL
-      - GPIO_BC12_DET_EN
-      - GPIO_BOARD_VERSION1
-      - GPIO_BOARD_VERSION2
-      - GPIO_BOARD_VERSION3
-      - GPIO_CCD_MODE_ODL
-      - GPIO_CHARGER_PROCHOT_ODL
-      - GPIO_CPU_PROCHOT
-      - GPIO_DA9313_GPIO0
-      - GPIO_DEPRECATED_AP_RST_REQ
-      - GPIO_DP_AUX_PATH_SEL
-      - GPIO_DP_HOT_PLUG_DET
-      - GPIO_DP_MUX_OE_L
-      - GPIO_DP_MUX_SEL
-      - GPIO_EC_ACCEL_INT
-      - GPIO_EC_ALS_RGB_INT_L
-      - GPIO_EC_BL_EN_OD
-      - GPIO_EC_CHG_LED_W_C0
-      - GPIO_EC_CHG_LED_Y_C0
-      - GPIO_EC_CHG_LED_B_C1
-      - GPIO_EC_CHG_LED_W_C1
-      - GPIO_EC_CHG_LED_Y_C1
-      - GPIO_EC_DPBRDG_HPD_ODL
-      - GPIO_EC_I2C_SENSOR_SCL
-      - GPIO_EC_I2C_SENSOR_SDA
-      - GPIO_EC_I2C0_SENSOR_SCL
-      - GPIO_EC_I2C0_SENSOR_SDA
-      - GPIO_EC_I2C1_USB_C0_SCL
-      - GPIO_EC_I2C1_USB_C0_SDA
-      - GPIO_EC_I2C2_USB_C1_SCL
-      - GPIO_EC_I2C2_USB_C1_SDA
-      - GPIO_EC_I2C3_USB_1_MIX_SCL
-      - GPIO_EC_I2C3_USB_1_MIX_SDA
-      - GPIO_EC_I2C5_BATTERY_SCL
-      - GPIO_EC_I2C5_BATTERY_SDA
-      - GPIO_EC_I2C7_EEPROM_PWR_SCL_R
-      - GPIO_EC_I2C7_EEPROM_PWR_SDA_R
-      - GPIO_EC_IMU_INT_L
-      - GPIO_EC_INT_L
-      - GPIO_EC_PCH_SYS_PWROK
-      - GPIO_EC_PCH_WAKE_ODL
-      - GPIO_EC_PCORE_INT_ODL
-      - GPIO_EC_PMIC_EN_ODL
-      - GPIO_EC_PMIC_WATCHDOG_L
-      - GPIO_EC_PROCHOT_IN_L
-      - GPIO_EC_PWR_BTN_ODL
-      - GPIO_EC_RST_ODL
-      - GPIO_EC_WP_L
-      - GPIO_EC_X_GPIO1
-      - GPIO_EC_X_GPIO3
-      - GPIO_EN_5V_USM
-      - GPIO_EN_A_RAILS
-      - GPIO_EN_EC_ID_ODL
-      - GPIO_EN_PP3000_SD_U
-      - GPIO_EN_PP3000_VMC_PMU
-      - GPIO_EN_PP3300_A
-      - GPIO_EN_PP5000
-      - GPIO_EN_PP5000_A
-      - GPIO_EN_PP5000_FAN
-      - GPIO_EN_PP5000_USB_A0_VBUS
-      - GPIO_EN_PP5000_USBA
-      - GPIO_EN_PPVAR_VCCIN
-      - GPIO_EN_PWR_A
-      - GPIO_EN_PWR_PCORE_S0_R
-      - GPIO_EN_PWR_S0_R
-      - GPIO_EN_SLP_Z
-      - GPIO_EN_USB_A_5V
-      - GPIO_ENABLE_BACKLIGHT
-      - GPIO_ENTERING_RW
-      - GPIO_HIBERNATE_L
-      - GPIO_I2C_B_SCL
-      - GPIO_I2C_B_SDA
-      - GPIO_I2C_C_SCL
-      - GPIO_I2C_C_SDA
-      - GPIO_I2C_E_SCL
-      - GPIO_I2C_E_SDA
-      - GPIO_I2C_F_SCL
-      - GPIO_I2C_F_SDA
-      - GPIO_KBD_KSO2
-      - GPIO_LID_ACCEL_INT_L
-      - GPIO_LID_OPEN
-      - GPIO_M2_SSD_PLN
-      - GPIO_PACKET_MODE_EN
-      - GPIO_PCH_DSW_PWROK
-      - GPIO_PCH_PWRBTN_L
-      - GPIO_PCH_RSMRST_L
-      - GPIO_PCH_RTCRST
-      - GPIO_PCH_SLP_S0_L
-      - GPIO_PCH_SLP_S3_L
-      - GPIO_PCH_SLP_S4_L
-      - GPIO_PCH_SLP_S5_L
-      - GPIO_PCH_SLP_SUS_L
-      - GPIO_PCH_SYS_PWROK
-      - GPIO_PG_EC_ALL_SYS_PWRGD
-      - GPIO_PG_EC_DSW_PWROK
-      - GPIO_PG_EC_RSMRST_ODL
-      - GPIO_PG_GROUPC_S0_OD
-      - GPIO_PG_LPDDR4X_S3_OD
-      - GPIO_PG_MT6360_ODL
-      - GPIO_PG_MT6315_GPU_ODL
-      - GPIO_PG_MT6315_PROC_ODL
-      - GPIO_PG_PP5000_A_ODL
-      - GPIO_PGOOD_FAN
-      - GPIO_PMIC_EC_PWRGD
-      - GPIO_PMIC_KPD_PWR_ODL
-      - GPIO_PMIC_RESIN_L
-      - GPIO_POWER_BUTTON_L
-      - GPIO_POWER_GOOD
-      - GPIO_PP5000_A_PG_OD
-      - GPIO_PS_HOLD
-      - GPIO_QSIP_ON
-      - GPIO_RSMRST_L_PGOOD
-      - GPIO_S0_PGOOD
-      - GPIO_S5_PGOOD
-      - GPIO_SET_VMC_VOLT_AT_1V8
-      - GPIO_SKU_ID0
-      - GPIO_SKU_ID1
-      - GPIO_SKU_ID2
-      - GPIO_SLP_SUS_L
-      - GPIO_SPI_CLK_GPG6
-      - GPIO_SPI_CS_GPG7
-      - GPIO_SPI_MISO_GPG5
-      - GPIO_SPI_MOSI_GPG4
-      - GPIO_SPI0_CS
-      - GPIO_SWITCHCAP_ON
-      - GPIO_SWITCHCAP_ON_L
-      - GPIO_SWITCHCAP_PG
-      - GPIO_SWITCHCAP_PG_INT_L
-      - GPIO_SYS_RESET_L
-      - GPIO_SYS_RST_ODL
-      - GPIO_TABLET_MODE_L
-      - GPIO_TRACKPAD_INT_GATE
-      - GPIO_USB_A_LOW_PWR_OD
-      - GPIO_USB_A0_FAULT_ODL
-      - GPIO_USB_A0_OC_ODL
-      - GPIO_USB_C0_BC12_INT_L
-      - GPIO_USB_C0_BC12_INT_ODL
-      - GPIO_USB_C0_FRS_EN
-      - GPIO_USB_C0_OC_ODL
-      - GPIO_USB_C0_PD_INT_ODL
-      - GPIO_USB_C0_PD_RST_L
-      - GPIO_USB_C0_PPC_INT_ODL
-      - GPIO_USB_C0_SWCTL_INT_ODL
-      - GPIO_USB_C0_TCPC_INT_ODL
-      - GPIO_USB_C1_BC12_INT_L
-      - GPIO_USB_C1_BC12_INT_ODL
-      - GPIO_USB_C1_FRS_EN
-      - GPIO_USB_C1_LS_EN
-      - GPIO_USB_C1_MIX_INT_ODL
-      - GPIO_USB_C1_OC_ODL
-      - GPIO_USB_C1_PD_INT_ODL
-      - GPIO_USB_C1_PD_RST_L
-      - GPIO_USB_C1_PPC_INT_ODL
-      - GPIO_USB_C1_RT_RST_ODL
-      - GPIO_USB_C1_SWCTL_INT_ODL
-      - GPIO_USB_C1_TCPC_INT_ODL
-      - GPIO_VBOB_EN
-      - GPIO_VOLUME_DOWN_L
-      - GPIO_VOLUME_UP_L
-      - GPIO_WARM_RESET_L
-      - GPIO_WP
-      - GPIO_WP_L
-      - GPIO_X_EC_GPIO2
diff --git a/zephyr/dts/bindings/gpio/gpio-id.yaml b/zephyr/dts/bindings/gpio/gpio-id.yaml
deleted file mode 100644
index 24322b3de8..0000000000
--- a/zephyr/dts/bindings/gpio/gpio-id.yaml
+++ /dev/null
@@ -1,27 +0,0 @@
-description: Defines board version and sku id gpios
-
-compatible: cros-ec,gpio-id
-
-properties:
-  bits:
-    type: phandles
-    required: true
-    description: GPIO list to read, LSB to MSB
-
-  system:
-    type: string
-    description:
-      Numeral system used to decode values
-      - binary - expects array with values of 0 and 1.
-      - binary_first_base3 - non-standard ternary number system
-          where the first 2^n natural numbers are represented as
-          they would be in a binary system (without any Z digits)
-          and the following 3^n-2^n numbers use the remaining
-          ternary representations in the normal ternary system order
-      - ternary - expects array with values of 0, 1 and 2.
-          It treats 'Z' state as digit '2'.
-    enum:
-      - binary
-      - binary_first_base3
-      - ternary
-
diff --git a/zephyr/dts/bindings/gpio/hibernate-wake-pins.yaml b/zephyr/dts/bindings/gpio/hibernate-wake-pins.yaml
deleted file mode 100644
index 64435f7b3b..0000000000
--- a/zephyr/dts/bindings/gpio/hibernate-wake-pins.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Hibernate Wake-up Pins Configurations
-
-compatible: "cros-ec,hibernate-wake-pins"
-
-properties:
-  wakeup-pins:
-    type: phandles
-    required: true
-    description: GPIO list for hibernate wake-up
diff --git a/zephyr/dts/bindings/gpio/named-gpios.yaml b/zephyr/dts/bindings/gpio/named-gpios.yaml
deleted file mode 100644
index 563c841f54..0000000000
--- a/zephyr/dts/bindings/gpio/named-gpios.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-description: Named GPIOs parent node
-
-compatible: "named-gpios"
-
-child-binding:
-    description: Named GPIOs child node
-    include: gpio-enum-name.yaml
-    properties:
-       gpios:
-          type: phandle-array
-          required: true
-       label:
-          required: true
-          type: string
-          description: |
-            Human readable string describing the device (used as
-            device_get_binding() argument)
-       "#gpio-cells":
-          type: int
-          required: false
-          const: 0
diff --git a/zephyr/dts/bindings/gpio/unused-gpios.yaml b/zephyr/dts/bindings/gpio/unused-gpios.yaml
deleted file mode 100644
index 99f649e25e..0000000000
--- a/zephyr/dts/bindings/gpio/unused-gpios.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-description: Unused GPIOs node
-
-compatible: "unused-gpios"
-
-properties:
-  unused-gpios:
-    type: phandle-array
-    required: true
-    description: |
-      A list contains unused GPIOs. The chip vendor needs to configure them for
-      better power consumption in the lowest power state.
diff --git a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
deleted file mode 100644
index ba2cc7b172..0000000000
--- a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
+++ /dev/null
@@ -1,56 +0,0 @@
-# Copyright (c) 2021 The Chromium OS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-description: I2C port base properties
-
-properties:
-  i2c-port:
-    type: phandle
-    required: true
-  remote-port:
-    type: int
-    required: false
-    description:
-      A port number used by remote components like Kernel via the I2C_PASSTHRU
-      Host Command
-  enum-name:
-    type: string
-    required: true
-    description:
-      Enum values used in the source code to refer to the i2c port
-    enum:
-    - I2C_PORT_ACCEL
-    - I2C_PORT_BATTERY
-    - I2C_PORT_CHARGER
-    - I2C_PORT_EEPROM
-    - I2C_PORT_EVB_0
-    - I2C_PORT_EVB_1
-    - I2C_PORT_EVB_2
-    - I2C_PORT_EVB_3
-    - I2C_PORT_EVB_7
-    - I2C_PORT_OPT_4
-    - I2C_PORT_POWER
-    - I2C_PORT_PPC0
-    - I2C_PORT_PPC1
-    - I2C_PORT_RTC
-    - I2C_PORT_SENSOR
-    - I2C_PORT_TCPC0
-    - I2C_PORT_TCPC1
-    - I2C_PORT_USB_1_MIX
-    - I2C_PORT_USB_C0
-    - I2C_PORT_USB_C0_C2_MUX
-    - I2C_PORT_USB_C0_C2_PPC
-    - I2C_PORT_USB_C0_C2_TCPC
-    - I2C_PORT_USB_C1
-    - I2C_PORT_USB_C1_PPC
-    - I2C_PORT_USB_C1_TCPC
-    - I2C_PORT_USB_MUX0
-    - I2C_PORT_USB_MUX1
-    - I2C_PORT_VIRTUAL
-    - I2C_PORT_WLC
-  label:
-    required: true
-    type: string
-    description:
-      Human readable string describing the device (used as device_get_binding()
-      argument).
diff --git a/zephyr/dts/bindings/i2c/named-i2c-ports.yaml b/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
deleted file mode 100644
index 4fce9c3229..0000000000
--- a/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright (c) 2020 The Chromium OS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-description: Named I2C ports parent node
-
-compatible: "named-i2c-ports"
-
-child-binding:
-  description: Named I2C ports child node
-  include: [cros-ec-i2c-port-base.yaml]
diff --git a/zephyr/dts/bindings/keyboard/cros-keyscan.yaml b/zephyr/dts/bindings/keyboard/cros-keyscan.yaml
deleted file mode 100644
index 11caf7fd11..0000000000
--- a/zephyr/dts/bindings/keyboard/cros-keyscan.yaml
+++ /dev/null
@@ -1,82 +0,0 @@
- # Copyright 2021 The Chromium OS Authors. All rights reserved.
- # Use of this source code is governed by a BSD-style license that can be
- # found in the LICENSE file.
-
-description: Keyboard scanning properties
-
-compatible: "cros-keyscan"
-
-properties:
-    output-settle:
-      type: int
-      required: false
-      default: 80
-      description: |
-          Delay time, in microseconds, between setting up output and waiting for
-          it to settle. 80 microseconds is the recommended value when column 2
-          of the keyboard passes through the Google Security Chip. Otherwise 50
-          microseconds is the recommended value.
-
-    debounce-down:
-      type: int
-      required: false
-      default: 9000
-      description: |
-          Time, in microseconds, to debounce key-down.
-
-    debounce-up:
-      type: int
-      required: false
-      default: 30000
-      description: |
-          Time, in microseconds, to debounce key-up.
-
-    scan-period:
-      type: int
-      required: false
-      default: 3000
-      description: |
-          Time between scans when keyboard scan task runs in polling mode.
-
-    min-post-scan-delay:
-      type: int
-      required: false
-      default: 1000
-      description: |
-          Minimum time between end of one scan and start of the next one.
-          This ensures keyboard scanning doesn't starve the rest of the system
-          if the scan period is set too short, or if other higher-priority
-          system activity is starving the keyboard scan task too.
-
-    poll-timeout:
-      type: int
-      required: false
-      default: 100000
-      description: |
-          Revert to interrupt mode after no keyboard activity for this period.
-          Specified in microseconds.
-
-    actual-key-mask:
-      type: array
-      required: false
-      default: [
-        0x1c, # C0
-        0xff, # C1
-        0xff, # C2
-        0xff, # C3
-        0xff, # C4
-        0xf5, # C5
-        0xff, # C6
-        0xa4, # C7
-        0xfe, # C8
-        0x55, # C9
-        0xfa, # C10
-        0xff, # C11
-        0xca, # C12
-        0x00, # C13 for keypad
-        0x00, # C14 for keypad
-      ]
-      description: |
-          Keyboard scanning mask. For each keyboard column, specify which
-          keyboard rows actually exist. Default key mask includes scanning for
-          full Chromebook keyboard, excluding the keypad.
diff --git a/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml b/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
deleted file mode 100644
index fd99e3202a..0000000000
--- a/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
+++ /dev/null
@@ -1,75 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: PWM LED configuration
-
-compatible: "cros-ec,pwm-leds"
-
-include: base.yaml
-
-properties:
-  leds:
-    type: phandles
-    required: true
-    description: |
-      List of pwm-leds nodes. These are expected to have a pwms property
-      pointing to the relevant PWMs, in red, green, blue and optionally sidesel
-      order.
-
-      For example
-        pwmleds {
-                compatible = "pwm-leds";
-                pwm_led0: pwm_led_0 {
-                        pwms = <&led3_red
-                                &led2_green
-                                &led1_blue
-                                &led3_sidesel
-                                >;
-                };
-        };
-        cros-pwmleds {
-                compatible = "cros-ec,pwm-leds";
-                leds = <&pwm_led0>;
-        };
-
-  color-map-red:
-    type: array
-    required: true
-    description: |
-      A map of PWM duty cycles per color, up to three channels.
-
-      For example
-        color-map-red    = <100   0   0>;
-        color-map-green  = <  0 100   0>;
-        color-map-blue   = <  0   0 100>;
-        color-map-yellow = <100  70   0>;
-        color-map-white  = <100  70 100>;
-        color-map-amber  = <100  20   0>;
-
-  color-map-green:
-    type: array
-    required: true
-
-  color-map-blue:
-    type: array
-    required: true
-
-  color-map-yellow:
-    type: array
-    required: true
-
-  color-map-white:
-    type: array
-    required: true
-
-  color-map-amber:
-    type: array
-    required: true
-
-  brightness-range:
-    type: array
-    required: true
-    description: |
-      A list of brigthness range value for all supported channels in order,
-      Red, Green, Blue, Yellow, White, Amber (0 to 255).
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
deleted file mode 100644
index c988af258d..0000000000
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright (c) 2021 The Chromium OS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-description: Motion sense mutex parent node
-
-compatible: "cros-ec,motionsense-mutex"
-
-child-binding:
-  description: A mutex node is used to create an instance of mutex_t.
-               A mutex node is referenced by one or more sensor nodes in
-               "/motionsense-sensors" node.
-  properties:
-    label:
-      required: true
-      type: string
-      description: Human readable string describing the mutex.
-                   This is a brief explanation about the mutex.
-                   The property is not actually used in code.
-
-
-#
-# examples:
-#
-# motionsense-mutex {
-#         compatible = "cros-ec,motionsense-mutex";
-#         mutex_bma255: bma255-mutex {
-#                 label = "BMA255_MUTEX";
-#         };
-#
-#         mutex_bmi260: bmi260-mutex {
-#                 label = "BMI260_MUTEX";
-#         };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
deleted file mode 100644
index 7de86ec8db..0000000000
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: rotation reference parent node
-
-compatible: "cros-ec,motionsense-rotation-ref"
-
-child-binding:
-  description: |
-    A rotation matrix node is used to create
-    an instance of mat33_fp_t which is used by
-    sensor drivers.
-  properties:
-    mat33:
-      required: true
-      type: array
-      description: |
-        3x3 matrix to rotate x, y, and z axes.
-        Applications with the sensor API expects sansor data
-        based on the same defined coordinate system.
-        * X-axis is horizontal and positive toward the right
-        * Y-axis is vertical and positive toward the top
-        * Z-axis points toward the user
-
-        Depending on how the sensor is mounted on board(PCB), we
-        may need to change the direction of a axis and swap X and
-        Y-axis. Using the 3x3 matrix, it generates the correct
-        X,Y, and Z on the defined coordinate system.
-
-        +-        -+   +-        -+   +- -+
-        | v1 v2 v3 |   | sensor_X |   | X |
-        | v4 v5 v6 | * | sensor_Y | = | Y |
-        | v7 v8 v9 |   | sensor_Z |   | Z |
-        +-        -+   +-        -+   +- -+
-
-#
-# examples:
-#
-# motionsense-rotation-ref {
-#        compatible = "cros-ec,motionsense-rotation-ref";
-#        /* change the direction of Y and Z-axis */
-#        lid_rot_ref: lid-rotation-ref {
-#                mat33 = <1 0 0
-#                         0 (-1) 0
-#                         0 0 (-1)>;
-#        };
-#        /* swap X and Y-axis, and then change the direction of Y-axis */
-#        base_rot_ref: base-rotation-ref {
-#                mat33 = <0 1 0
-#                         (-1) 0 0
-#                         0 0 1>;
-#        };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
deleted file mode 100644
index 68cdd15637..0000000000
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
+++ /dev/null
@@ -1,66 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: |
-    There are 4 configuration parameters to deal with different
-    configuration
-    Power   |         S0        |            S3     |      S5
-    --------+-------------------+-------------------+-----------------
-    From AP | <------- SENSOR_CONFIG_AP ----------> |
-            | Use for normal    | While sleeping    | Always disabled
-            | operation (game,  | For Activity      |
-            | screen rotation)  | Recognition       |
-    --------+-------------------+-------------------+------------------
-    From EC |SENSOR_CONFIG_EC_S0|SENSOR_CONFIG_EC_S3|SENSOR_CONFIG_EC_S5
-            | Background        | Gesture  Recognition (Double tap, ...)
-            | Activity (compass,|
-            | ambient light)    |
-
-compatible: "cros-ec,motionsense-sensor-config"
-
-child-binding:
-  description: |
-    A config node is used to create a motion_data_t instance.
-    Node name can only be either ap, ec-s0, ec-s3, or ec-s5,
-    and it is used to indicate one of the 4 configurations.
-    For example, node name ec-s0 is for SENSOR_CONFIG_EC_S0.
-    ec-s0 {
-       label = "SENSOR_CONFIG_EC_S0";
-       odr = <1000>;
-       ec_rate = <1000>;
-    };
-  properties:
-    label:
-      type: string
-      required: false
-      description: |
-        Human-readable string describing the config.
-        see the example the above.
-    odr:
-      type: int
-      required: false
-      description: |
-        Sensor output data rate in mHz.
-        MSB is used to know if we are rounding up.
-    ec-rate:
-      type: int
-      required: false
-      description: Delay between collection by EC, in us.
-
-#
-# examples:
-#
-# configs {
-#         compatible =
-#                 "cros-ec,motionsense-sensor-config";
-#         ec-s0 {
-#                 label = "SENSOR_CONFIG_EC_S0";
-#                 odr = <(10000 | ROUND_UP_FLAG)>;
-#         };
-#         ec-s3 {
-#                 label = "SENSOR_CONFIG_EC_S3";
-#                 odr = <(10000 | ROUND_UP_FLAG)>;
-#         };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
deleted file mode 100644
index e413e2bfff..0000000000
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
+++ /dev/null
@@ -1,56 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: The node has the information required by motion sense running
-
-compatible: "cros-ec,motionsense-sensor-info"
-
-properties:
-  als-sensors:
-    type: phandles
-    required: false
-    description: |
-        List of ALS sensors to create motion_als_sensors array.
-        The ALS sensors listed in the motion_als_sensors array
-        are managed by motion sense task. The task reads the sensor
-        data from the sensors and put them into the designated part
-        in the ec mmap. For example, als_clear and als_rgb are aliases
-        of ALS sensor noded defined in motionsense-sensor node.
-        als-sensors = <&als_clear, &als_rgb>;
-        This will automatically generate motion_als_sensors array from it.
-  sensor-irqs:
-    type: phandles
-    required: false
-    description: |
-        List of GPIO interrupts from sensors to be enabled.
-        GPIOs specified here will be enabled before motion sense task starts.
-        sensor-irqs = <&gpio_ec_imu_int_l &gpio_ec_als_rgb_int_l>;
-  accel-force-mode-sensors:
-    type: phandles
-    required: false
-    description: |
-        List of sensors should be handled in force mode. Sensors listed will be
-        used to define CONFIG_ACCEL_FORCE_MODE_MASK so that motion sense task can
-        manage them in force mode.
-        accel-force-mode-sensors = <&lid_accel &als_clear>;
-
-#
-# examples:
-#
-# motionsense-sensor-info {
-#        compatible = "cros-ec,motionsense-sensor-info";
-#
-#        /* list of entries for motion_als_sensors */
-#        als-sensors = <&als_clear>;
-#
-#        /*
-#         * list of GPIO interrupts that have to
-#         * be enabled at initial stage
-#         */
-#        sensor-irqs = <&gpio_ec_imu_int_l &gpio_ec_als_rgb_int_l>;
-#
-#        /* list of sensors in force mode */
-#        accel-force-mode-sensors = <&lid_accel &als_clear>;
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi160.yaml b/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
deleted file mode 100644
index 8f490254a3..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# common fields for both BMI160 accel and BMI160 gyro
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI slave logic GPIO
-    enum:
-      - "BMI160_ADDR0_FLAGS"
-    default: "BMI160_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi260.yaml b/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
deleted file mode 100644
index f308472ec3..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# common fields for both BMI260 accel and BMI260 gyro
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI slave logic GPIO
-    enum:
-      - "BMI260_ADDR0_FLAGS"
-    default: "BMI260_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
deleted file mode 100644
index 77d6282d7f..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motionsense sensor node for BMA255
-
-compatible: "cros-ec,bma255"
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI slave logic GPIO
-    enum:
-      - "BMA2x2_I2C_ADDR1_FLAGS"
-      - "BMA2x2_I2C_ADDR2_FLAGS"
-      - "BMA2x2_I2C_ADDR3_FLAGS"
-      - "BMA2x2_I2C_ADDR4_FLAGS"
-    default: "BMA2x2_I2C_ADDR1_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
deleted file mode 100644
index 4eabf12cd5..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for BMI160 accel
-
-compatible: "cros-ec,bmi160-accel"
-
-include: bmi160.yaml
-
-properties:
-  default-range:
-    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
deleted file mode 100644
index b7a0b38290..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for BMI160 gyro
-
-compatible: "cros-ec,bmi160-gyro"
-
-include: bmi160.yaml
-
-properties:
-  default-range:
-    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
deleted file mode 100644
index 130600cca2..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for BMI260 accel
-
-compatible: "cros-ec,bmi260-accel"
-
-include: bmi260.yaml
-
-properties:
-  default-range:
-    default: 4
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
deleted file mode 100644
index 00226d0304..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for BMI260 gyro
-
-compatible: "cros-ec,bmi260-gyro"
-
-include: bmi260.yaml
-
-properties:
-  default-range:
-    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
deleted file mode 100644
index b90d824575..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motionsense sensor node for KX022
-
-compatible: "cros-ec,kx022"
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI slave logic GPIO
-    enum:
-      - "KX022_ADDR0_FLAGS"
-      - "KX022_ADDR1_FLAGS"
-    default: "KX022_ADDR0_FLAGS"
-  default-range:
-    default: 2
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
deleted file mode 100644
index bacf8f2c75..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motionsense sensor node for LIS2DW12 Accelerometer
-
-compatible: "cros-ec,lis2dw12"
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI peripheral logic GPIO
-    enum:
-      - "LIS2DWL_ADDR0_FLAGS"
-      - "LIS2DWL_ADDR1_FLAGS"
-    default: "LIS2DWL_ADDR1_FLAGS"
-  default-range:
-    default: 2
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
deleted file mode 100644
index 323286c462..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for TCS3400 CLEAR
-
-compatible: "cros-ec,tcs3400-clear"
-
-include: tcs3400.yaml
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
deleted file mode 100644
index e2987cf44b..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: motion sense sensor node for TCS3400 RGB
-
-compatible: "cros-ec,tcs3400-rgb"
-
-include: tcs3400.yaml
diff --git a/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml b/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
deleted file mode 100644
index 2fc3d7eacd..0000000000
--- a/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# common fields for both TCS3400 clear and TCS3400 rgb
-
-# every motionsense sensor node should include motionsense-sensor-base.yaml
-include: motionsense-sensor-base.yaml
-
-properties:
-  i2c-spi-addr-flags:
-    type: string
-    description: i2c address or SPI slave logic GPIO
-    enum:
-      - "TCS3400_I2C_ADDR_FLAGS"
-    default: "TCS3400_I2C_ADDR_FLAGS"
-  default-range:
-    default: 0x10000 # scale = 1x, uscale = 0
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
deleted file mode 100644
index 753edc7ea8..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: |
-  Bindings for als_channel_scale_t in accelgyro.h.
-  Each channel has scaling factor for normalization & cover
-
-compatible: cros-ec,accelgyro-als-channel-scale
-
-properties:
-  k-channel-scale:
-    type: int
-    required: true
-    description: Channel scale factor
-  cover-scale:
-    type: int
-    required: true
-    description: Cover compensation scale factor
-
-#
-# examples:
-#
-# als-channel-scale {
-#        compatible = "cros-ec,accelgyro-als-channel-scale";
-#        k-channel-scale = <1>;
-#        cover-scale = <1>;
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
deleted file mode 100644
index 7d64689cf2..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
+++ /dev/null
@@ -1,44 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: ALS driver data
-
-compatible: "cros-ec,accelgyro-als-drv-data"
-
-child-binding:
-  description: ALS calibration data
-  properties:
-    scale:
-      type: int
-      required: true
-      description: |
-        Scale, uscale, and offset are used to correct the raw 16 bit ALS data
-        and then to convert it to 32 bit using the following equations
-        raw_value += offset;\n
-        adjusted_value = raw_value * scale + raw_value * uscale / 10000;
-    uscale:
-      type: int
-      required: true
-      description: uscale
-    offset:
-      type: int
-      required: true
-      description: offset
-
-#
-# examples:
-# als-drv-data {
-#        compatible = "cros-ec,accelgyro-als-drv-data";
-#        als-cal {
-#                scale = <1>;
-#                uscale = <0>;
-#                offset = <0>;
-#                als-channel-scale {
-#                compatible = "cros-ec,accelgyro-als-channel-scale";
-#                        k-channel-scale = <1>;
-#                        cover-scale = <1>;
-#                };
-#        };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
deleted file mode 100644
index 4204a63cff..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
+++ /dev/null
@@ -1,63 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: bindings for rgb_calibration_t in accelgyro.h
-
-compatible: "cros-ec,accelgyro-rgb-calibration"
-
-properties:
-  irt:
-    type: int
-    required: true
-    description: incandecent scaling factor
-
-child-binding:
-  description: RGB ALS Calibration Data
-  properties:
-    offset:
-      type: int
-      required: true
-      description: Any offset to add to raw channel data
-    coeff:
-      type: array
-      required: true
-      description: Clear, R, G, and B coefficients for this channel
-
-#
-# examples:
-#
-# rgb_calibration {
-#        compatible = "cros-ec,accelgyro-rgb-calibration";
-#
-#        irt = <1>;
-#
-#        rgb-cal-x {
-#                offset = <0>;
-#                coeff = <0 0 0 0>;
-#                als-channel-scale {
-#                compatible = "cros-ec,accelgyro-als-channel-scale";
-#                        k-channel-scale = <1>;
-#                        cover-scale = <1>;
-#                };
-#        };
-#        rgb-cal-y {
-#                offset = <0>;
-#                coeff = <0 0 0 0>;
-#                als-channel-scale {
-#                compatible = "cros-ec,accelgyro-als-channel-scale";
-#                        k-channel-scale = <1>;
-#                        cover-scale = <1>;
-#                };
-#        };
-#        rgb-cal-z {
-#                offset = <0>;
-#                coeff = <0 0 0 0>;
-#                als-channel-scale {
-#                compatible = "cros-ec,accelgyro-als-channel-scale";
-#                        k-channel-scale = <1>;
-#                        cover-scale = <1>;
-#                };
-#        };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
deleted file mode 100644
index 4cabd620da..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: BMA255 driver data node
-
-compatible: "cros-ec,drvdata-bma255"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# bma255_data: bma255-drv-data {
-#       compatible = "cros-ec,drvdata-bma255";
-#       status = "okay";
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
deleted file mode 100644
index 52f5c346fc..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: BMI160 driver data node
-
-compatible: "cros-ec,drvdata-bmi160"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# bmi160_data: bmi160-drv-data {
-#        compatible = "cros-ec,drvdata-bmi160";
-#        status = "okay";
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
deleted file mode 100644
index 4d414121d1..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: BMI260 driver data node
-
-compatible: "cros-ec,drvdata-bmi260"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# bmi260_data: bmi260-drv-data {
-#        compatible = "cros-ec,drvdata-bmi260";
-#        status = "okay";
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
deleted file mode 100644
index 3151412b79..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Kionix driver data node
-
-compatible: "cros-ec,drvdata-kionix"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# kx022_data: kx022-drv-data {
-#       compatible = "cros-ec,drvdata-kionix";
-#       status = "okay";
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
deleted file mode 100644
index ecb182a4fd..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: LIS2DW12 driver data node
-
-compatible: "cros-ec,drvdata-lis2dw12"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# lis2dw12_data: lis2dw12-drv-data {
-#        compatible = "cros-ec,drvdata-lis2dw12";
-#        status = "okay";
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
deleted file mode 100644
index c1059d40be..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: TCS3400 CLEAR driver data
-
-compatible: "cros-ec,drvdata-tcs3400-clear"
-
-include: drvdata-base.yaml
-
-#
-# examples:
-#
-# tcs_clear_data: tcs3400-clear-drv-data {
-#        compatible = "cros-ec,drvdata-tcs3400-clear";
-#        status = "okay";
-#
-#        als-drv-data {
-#                compatible = "cros-ec,accelgyro-als-drv-data";
-#                als-cal {
-#                        scale = <1>;
-#                        uscale = <0>;
-#                        offset = <0>;
-#                        als-channel-scale {
-#                        compatible = "cros-ec,accelgyro-als-channel-scale";
-#                                k-channel-scale = <1>;
-#                                cover-scale = <1>;
-#                        };
-#                };
-#        };
-# };
-#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
deleted file mode 100644
index 7ae7bc5983..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: TCS3400 RGB driver data
-
-compatible: "cros-ec,drvdata-tcs3400-rgb"
-
-include: drvdata-base.yaml
-
-child-binding:
-  description: saturation auto-adjustment
-  properties:
-    again:
-      type: int
-      required: false
-      description: Gain Scaling; must be value between 0 and 3
-    atime:
-      type: int
-      required: false
-      description: Acquisition Time, controlled by the ATIME register
diff --git a/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml b/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
deleted file mode 100644
index dc32d69d21..0000000000
--- a/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# common fields for driver data
-
-include: base.yaml
-
-properties:
-  status:
-    required: true
diff --git a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
deleted file mode 100644
index 6948ce6997..0000000000
--- a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
+++ /dev/null
@@ -1,82 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Common fields for motion sensors
-
-include: base.yaml
-
-properties:
-  status:
-    required: true
-  label:
-    type: string
-    required: true
-    description: |
-        Human readable string describing the motion sensor.
-        This is used as the name of the motion sensor.
-        e.g) label = "Lid Accel";
-  active-mask:
-    type: string
-    description: indicates system power state for sensor to be active
-    enum:
-      - "SENSOR_ACTIVE_S5"
-      - "SENSOR_ACTIVE_S3"
-      - "SENSOR_ACTIVE_S0"
-      - "SENSOR_ACTIVE_S0_S3"
-      - "SENSOR_ACTIVE_S0_S3_S5"
-    default: "SENSOR_ACTIVE_S0_S3"
-  location:
-    type: string
-    required: true
-    description: location of the motion sensor
-    enum:
-      - "MOTIONSENSE_LOC_BASE"
-      - "MOTIONSENSE_LOC_LID"
-      - "MOTIONSENSE_LOC_CAMERA"
-  mutex:
-    type: phandle
-    required: false
-    description: mutex used by chip driver
-  port:
-    type: phandle
-    required: false
-    description: phandle to the named i2c port
-  rot-standard-ref:
-    type: phandle
-    required: false
-    description: phandle to 3x3 rotation matrix
-  default-range:
-    type: int
-    required: false
-    description: default range of sensor read
-  drv-data:
-    type: phandle
-    required: false
-    description: phandle to driver data to be used for the motion sensor
-  alternate-for:
-    type: phandle
-    description: phandle to another sensor that can be swapped with this one
-      at runtime.
-  alternate-indicator:
-    type: phandle
-    description: phandle to CBI SSGC value indicating that the sensor
-      should be used
-
-#
-# examples:
-#
-# lid_accel: lid-accel {
-#           compatible = "cros-ec,bma255";
-#           status = "okay";
-#
-#           label = "Lid Accel";
-#           active-mask = "SENSOR_ACTIVE_S0_S3";
-#           location = "MOTIONSENSE_LOC_LID";
-#           mutex = <&mutex_bma255>;
-#           port = <&i2c_sensor>;
-#           rot-standard-ref = <&lid_rot_ref>;
-#           default-range = <2>;
-#           drv-data = <&bma255_data>;
-# };
-#
diff --git a/zephyr/dts/bindings/pwm/named-pwms.yaml b/zephyr/dts/bindings/pwm/named-pwms.yaml
deleted file mode 100644
index f01fd5a30a..0000000000
--- a/zephyr/dts/bindings/pwm/named-pwms.yaml
+++ /dev/null
@@ -1,24 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: PWM KEYS parent node
-
-compatible: "named-pwms"
-
-child-binding:
-  description: Named PWMs child node
-  properties:
-    pwms:
-      type: phandle-array
-      required: true
-    label:
-      required: true
-      type: string
-      description:
-        Human readable string describing the device (used as
-        device_get_binding() argument)
-    frequency:
-      required: true
-      type: int
-      description: PWM frequency, in Hz
diff --git a/zephyr/dts/bindings/retimer/intel,jhl8040r.yaml b/zephyr/dts/bindings/retimer/intel,jhl8040r.yaml
deleted file mode 100644
index 6b39833048..0000000000
--- a/zephyr/dts/bindings/retimer/intel,jhl8040r.yaml
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Intel JHL8040R Thunderbolt 4 Retimer
-
-compatible: "intel,jhl8040r"
-
-include: i2c-device.yaml
-
-properties:
-    reset-gpios:
-      type: phandle-array
-      required: true
-
-    int-gpios:
-      type: phandle-array
-      required: false
-
-    ls-en-gpios:
-      type: phandle-array
-      required: false
diff --git a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml b/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml
deleted file mode 100644
index 5d1a25bf94..0000000000
--- a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-description: SwitchCap controlled by gpios
-
-compatible: "switchcap-gpio"
-
-properties:
-  enable-pin:
-    type: phandle
-    required: true
-    description: |
-      GPIO used to enable the switch cap
-
-  power-good-pin:
-    type: phandle
-    required: false
-    description: |
-      GPIO used to read if power is good
diff --git a/zephyr/dts/bindings/switchcap/switchcap-ln9310.yaml b/zephyr/dts/bindings/switchcap/switchcap-ln9310.yaml
deleted file mode 100644
index afd89aacc6..0000000000
--- a/zephyr/dts/bindings/switchcap/switchcap-ln9310.yaml
+++ /dev/null
@@ -1,27 +0,0 @@
-description: SwitchCap controlled by LN9310
-
-compatible: "switchcap-ln9310"
-
-properties:
-  enable-l-pin:
-    type: phandle
-    required: true
-    description: |
-      GPIO used to enable the switch cap - active low
-
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  addr-flags:
-    type: string
-    default: "LN9310_I2C_ADDR_0_FLAGS"
-    enum:
-      - "LN9310_I2C_ADDR_0_FLAGS"
-      - "LN9310_I2C_ADDR_1_FLAGS"
-      - "LN9310_I2C_ADDR_2_FLAGS"
-      - "LN9310_I2C_ADDR_3_FLAGS"
-    description: |
-      I2C address of controller
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml b/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml
deleted file mode 100644
index 288dc2d1c8..0000000000
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml
+++ /dev/null
@@ -1,86 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: >
-  Common properties for temperature sensors
-  Zero values in degrees K(-273 in degrees C)in thermal thresholds will
-  be ignored
-
-compatible: cros-ec,temp-sensor
-
-properties:
-    adc:
-      required: true
-      type: phandle
-      description: The named adc channel
-
-    thermistor:
-      type: phandle
-      description: Underlying thermistor device if used
-
-    label:
-      required: true
-      type: string
-      description:
-        Human-readable string describing the device (used as
-        device_get_binding() argument)
-
-    enum-name:
-      type: string
-      required: true
-      description:
-        Enum values used in the source code to refer to the temperature sensors
-      enum:
-      - TEMP_SENSOR_CHARGER
-      - TEMP_SENSOR_DDR_SOC
-      - TEMP_SENSOR_FAN
-      - TEMP_SENSOR_PP3300_REGULATOR
-
-    temp_fan_off:
-      type: int
-      description:
-        Temperature threshold in degrees C when no active cooling
-        is needed
-
-    temp_fan_max:
-      type: int
-      description:
-        Temperature threshold in degrees C when max active cooling
-        is needed
-
-    temp_host_warn:
-      type: int
-      description:
-        Temperature threshold in degrees C of thermal warn.
-        Temperatures above the thermal warn threshold generate a
-        request to the AP to throttle itself.
-
-    temp_host_high:
-      type: int
-      description:
-        Temperature threshold in degrees C of thermal high.
-        Temperatures above the thermal high threshold cause the EC to
-        assert a signal (usually PROCHOT) to the AP and force the AP to
-        throttle.
-
-    temp_host_halt:
-      type: int
-      description:
-        Temperature threshold in degrees C that forces AP to shutdown
-        due to thermal reason
-
-    temp_host_release_warn:
-      type: int
-      description:
-        Temperature release threshold in degrees C of thermal warn
-
-    temp_host_release_high:
-      type: int
-      description:
-        Temperature release threshold in degrees C of thermal high
-
-    temp_host_release_halt:
-      type: int
-      description:
-        Temperature release threshold in degrees C of thermal shutdown
diff --git a/zephyr/dts/bindings/temp/cros_ec_thermistor.yaml b/zephyr/dts/bindings/temp/cros_ec_thermistor.yaml
deleted file mode 100644
index d4bc32ed3c..0000000000
--- a/zephyr/dts/bindings/temp/cros_ec_thermistor.yaml
+++ /dev/null
@@ -1,57 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# For more information:
-# https://www.electronics-tutorials.ws/io/thermistors.html
-
-description: Common properties for thermistors
-
-compatible: cros-ec,thermistor
-
-properties:
-  scaling-factor:
-    required: true
-    type: int
-    description: Scaling factor for voltage pairs
-
-  num-pairs:
-    required: true
-    type: int
-    description: Number of sample data points for linear interpolation
-
-  steinhart-reference-mv:
-    required: true
-    type: int
-    description: >
-      Used only for testing.
-      Is the reference voltage for temperature 25C.
-
-  steinhart-reference-res:
-    required: true
-    type: int
-    description: >
-      Used only for testing.
-      Is the reference resistance for temperature 25C.
-
-child-binding:
-  description: >
-    Data samples derived from Steinhart-Hart
-    equation in a resistor divider circuit.
-    Used in linear interpolation.
-
-  properties:
-    milivolt:
-      type: int
-      required: true
-      description: Voltage reading for a given temperature sample
-
-    temp:
-      type: int
-      required: true
-      description: Temperature (Celcius) in a sample
-
-    sample-index:
-      type: int
-      required: true
-      description: The index of a datum to maintain sample order to interpolate.
diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt
deleted file mode 100644
index 856fa81426..0000000000
--- a/zephyr/dts/bindings/vendor-prefixes.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Valid device-tree compatible string prefixes used in this
-# Zephyr module.  The format is:
-#  vendor-prefix<TAB>vendor name
-cros-ec	The Chromium OS Embedded Controller Project
diff --git a/zephyr/dts/board-overlays/native_posix.dts b/zephyr/dts/board-overlays/native_posix.dts
deleted file mode 100644
index b8faf65842..0000000000
--- a/zephyr/dts/board-overlays/native_posix.dts
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* TODO(sjg): add things */
diff --git a/zephyr/emul/CMakeLists.txt b/zephyr/emul/CMakeLists.txt
deleted file mode 100644
index 02b176b942..0000000000
--- a/zephyr/emul/CMakeLists.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_EMUL_COMMON_I2C	emul_common_i2c.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_SMART_BATTERY	emul_smart_battery.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BMA255		emul_bma255.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BC12_DETECT_PI3USB9201	emul_pi3usb9201.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_PPC_SYV682X	emul_syv682x.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi160.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BMI		emul_bmi260.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_TCS3400	emul_tcs3400.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_BB_RETIMER	emul_bb_retimer.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_LN9310		emul_ln9310.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_LIS2DW12	emul_lis2dw12.c)
-zephyr_library_sources_ifdef(CONFIG_I2C_MOCK		i2c_mock.c)
diff --git a/zephyr/emul/Kconfig b/zephyr/emul/Kconfig
deleted file mode 100644
index 8d9c8e42ea..0000000000
--- a/zephyr/emul/Kconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-config EMUL_COMMON_I2C
-	bool "Common handler for I2C emulator messages"
-	help
-	  Enable common code that is used by many emulators of devices on I2C
-	  bus. It allows to share code for handling I2C messages, locking and
-	  custom user handlers between these emulators.
-
-config EMUL_SMART_BATTERY
-	bool "Smart Battery emulator"
-	select EMUL_COMMON_I2C
-	help
-	  Enable the Smart Battery emulator. This driver use emulated I2C bus.
-
-config EMUL_BMA255
-	bool "BMA255 emulator"
-	select EMUL_COMMON_I2C
-	help
-	  Enable the BMA255 emulator. This driver use emulated I2C bus.
-	  It is used to test bma2x2 driver. Emulators API is available in
-	  zephyr/include/emul/emul_bma255.h
-
-config EMUL_BC12_DETECT_PI3USB9201
-	bool "PI3USB9201 emulator"
-	help
-	  Enable the PI3USB9201 emulator. PI3USB9201 is a BC1.2 charger
-	  detector/advertiser. The emulator supports reading and writing the
-	  4 I2C registers of the PI3USB9201 using the emulated I2C bus.
-
-config EMUL_PPC_SYV682X
-	bool "Silergy SYV682x PPC emulator"
-	select PLATFORM_EC_USBC_PPC_SYV682X
-	help
-	  Enable the SYV682x emulator. SYV682 is a USB Type-C PPC. This driver
-	  uses the emulated I2C bus.
-
-config EMUL_BMI
-	bool "BMI emulator"
-	select EMUL_COMMON_I2C
-	help
-	  Enable the BMI emulator. This driver use emulated I2C bus.
-	  It is used to test bmi 160 and 260 drivers. Emulators API is
-	  available in zephyr/include/emul/emul_bmi.h
-
-config EMUL_TCS3400
-	bool "TCS3400 emulator"
-	select EMUL_COMMON_I2C
-	help
-	  Enable the TCS3400 light sensor. This driver use emulated I2C bus.
-	  It is used to test als_tcs3400 driver. It supports reading sensor
-	  values which are correctly scaled using current gain and integration
-	  time configuration, switching between IR and clear sensor and
-	  clearing status register using clear interrupt registers. Other
-	  TCS3400 registers support read and write with optional checking
-	  of proper access to reserved bits. Emulators API is available in
-	  zephyr/include/emul/emul_tcs3400.h
-
-config EMUL_BB_RETIMER
-	bool "BB retimer emulator"
-	select EMUL_COMMON_I2C
-	help
-	  Enable the BB (Burnside Bridge) retimer emulator. This driver use
-	  emulated I2C bus. It is used to test bb_retimer driver. It supports
-	  reads and writes to all emulator registers. Emulators API is
-	  available in zephyr/include/emul/emul_bb_retimer.h
-
-rsource "Kconfig.ln9310"
-rsource "Kconfig.lis2dw12"
-rsource "Kconfig.i2c_mock"
diff --git a/zephyr/emul/Kconfig.i2c_mock b/zephyr/emul/Kconfig.i2c_mock
deleted file mode 100644
index 6c98a32739..0000000000
--- a/zephyr/emul/Kconfig.i2c_mock
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-DT_COMPAT_I2C_MOCK := cros,i2c-mock
-
-menuconfig I2C_MOCK
-	bool "Mock implementation of an I2C device"
-	default $(dt_compat_enabled,$(DT_COMPAT_I2C_MOCK))
-	depends on I2C_EMUL
-	help
-	  Enable the I2C mock. This driver is a pure mock and does nothing by
-	  default. It is used to test common i2c code. Mock API is available in
-	  zephyr/include/emul/i2c_mock.h
-
-if I2C_MOCK
-
-module = I2C_MOCK
-module-str = i2c_mock
-source "subsys/logging/Kconfig.template.log_config"
-
-endif # I2C_MOCK
diff --git a/zephyr/emul/Kconfig.lis2dw12 b/zephyr/emul/Kconfig.lis2dw12
deleted file mode 100644
index 2263255418..0000000000
--- a/zephyr/emul/Kconfig.lis2dw12
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-DT_COMPAT_LIS2DW12_EMUL := cros,lis2dw12-emul
-
-menuconfig EMUL_LIS2DW12
-	bool "LIS2DW12 accelerometer emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_LIS2DW12_EMUL))
-	depends on I2C_EMUL
-	select PLATFORM_EC_ACCEL_LIS2DW12
-	help
-	  Enable the LIS2DW12 emulator. This driver uses the emulated I2C bus.
-	  It is used to test the lis2dw12 driver. Emulator API is available in
-	  zephyr/include/emul/emul_lis2dw12.h
-
-if EMUL_LIS2DW12
-
-module = LIS2DW12_EMUL
-module-str = lis2dw12_emul
-source "subsys/logging/Kconfig.template.log_config"
-
-endif # EMUL_LIS2DW12
diff --git a/zephyr/emul/Kconfig.ln9310 b/zephyr/emul/Kconfig.ln9310
deleted file mode 100644
index 5773cf3721..0000000000
--- a/zephyr/emul/Kconfig.ln9310
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-DT_COMPAT_LN9310_EMUL := cros,ln9310-emul
-
-menuconfig EMUL_LN9310
-	bool "LN9310 switchcap emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_LN9310_EMUL))
-	depends on I2C_EMUL
-	help
-	  Enable the LN9310 emulator. This driver uses the emulated I2C bus. It
-	  is used to test the ln9310 driver. Emulator API is available in
-	  zephyr/include/emul/emul_ln9310.h
-
-if EMUL_LN9310
-
-module = LN9310_EMUL
-module-str = ln9310_emul
-source "subsys/logging/Kconfig.template.log_config"
-
-endif # EMUL_LN9310
diff --git a/zephyr/emul/emul_bb_retimer.c b/zephyr/emul/emul_bb_retimer.c
deleted file mode 100644
index b391070b1f..0000000000
--- a/zephyr/emul/emul_bb_retimer.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_bb_retimer_emul
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_bb_retimer);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_bb_retimer.h"
-
-#include "driver/retimer/bb_retimer.h"
-
-#define BB_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bb_emul_data, common)
-
-/** Run-time data used by the emulator */
-struct bb_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Current state of all emulated BB retimer registers */
-	uint32_t reg[BB_RETIMER_REG_COUNT];
-
-	/** Vendor ID of emulated device */
-	uint32_t vendor_id;
-
-	/** Return error when trying to write to RO register */
-	bool error_on_ro_write;
-	/** Return error when trying to write 1 to reserved bit */
-	bool error_on_rsvd_write;
-
-	/** Value of data dword in ongoing i2c message */
-	uint32_t data_dword;
-};
-
-/** Check description in emul_bb_retimer.h */
-void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val)
-{
-	struct bb_emul_data *data;
-
-	if (reg < 0 || reg > BB_RETIMER_REG_COUNT) {
-		return;
-	}
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-	data->reg[reg] = val;
-}
-
-/** Check description in emul_bb_retimer.h */
-uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg)
-{
-	struct bb_emul_data *data;
-
-	if (reg < 0 || reg > BB_RETIMER_REG_COUNT) {
-		return 0;
-	}
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	return data->reg[reg];
-}
-
-/** Check description in emul_bb_retimer.h */
-void bb_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_ro_write = set;
-}
-
-/** Check description in emul_bb_retimer.h */
-void bb_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_rsvd_write = set;
-}
-
-/** Mask reserved bits in each register of BB retimer */
-static const uint32_t bb_emul_rsvd_mask[] = {
-	[BB_RETIMER_REG_VENDOR_ID]		= 0x00000000,
-	[BB_RETIMER_REG_DEVICE_ID]		= 0x00000000,
-	[0x02]					= 0xffffffff, /* Reserved */
-	[0x03]					= 0xffffffff, /* Reserved */
-	[BB_RETIMER_REG_CONNECTION_STATE]	= 0xc0201000,
-	[BB_RETIMER_REG_TBT_CONTROL]		= 0xffffdfff,
-	[0x06]					= 0xffffffff, /* Reserved */
-	[BB_RETIMER_REG_EXT_CONNECTION_MODE]	= 0x08007f00,
-};
-
-/**
- * @brief Reset registers to default values
- *
- * @param emul Pointer to BB retimer emulator
- */
-static void bb_emul_reset(struct i2c_emul *emul)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[BB_RETIMER_REG_VENDOR_ID]		= data->vendor_id;
-	data->reg[BB_RETIMER_REG_DEVICE_ID]		= BB_RETIMER_DEVICE_ID;
-	data->reg[0x02]					= 0x00; /* Reserved */
-	data->reg[0x03]					= 0x00; /* Reserved */
-	data->reg[BB_RETIMER_REG_CONNECTION_STATE]	= 0x00;
-	data->reg[BB_RETIMER_REG_TBT_CONTROL]		= 0x00;
-	data->reg[0x06]					= 0x00; /* Reserved */
-	data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE]	= 0x00;
-}
-
-/**
- * @brief Handle I2C write message. It is checked if accessed register isn't RO
- *        and reserved bits are set to 0. Write set value of reg field of BB
- *        retimer emulator data ignoring reserved bits and write only bits.
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg Register which is written
- * @param msg_len Length of handled I2C message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bb_emul_handle_write(struct i2c_emul *emul, int reg, int msg_len)
-{
-	struct bb_emul_data *data;
-	uint32_t val;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	/* This write only selected register for I2C read message */
-	if (msg_len < 2) {
-		return 0;
-	}
-
-	val = data->data_dword;
-
-	/*
-	 * BB retimer ignores data bytes above 4 and use zeros if there is less
-	 * then 4 data bytes. Emulator prints warning in that case.
-	 */
-	if (msg_len != 6) {
-		LOG_WRN("Got %d bytes of WR data, expected 4", msg_len - 2);
-	}
-
-	if (reg <= BB_RETIMER_REG_DEVICE_ID ||
-	    reg >= BB_RETIMER_REG_COUNT ||
-	    reg == BB_RETIMER_REG_TBT_CONTROL) {
-		if (data->error_on_ro_write) {
-			LOG_ERR("Writing to reg 0x%x which is RO", reg);
-			return -EIO;
-		}
-
-		return 0;
-	}
-
-	if (data->error_on_rsvd_write && bb_emul_rsvd_mask[reg] & val) {
-		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
-			val, reg, bb_emul_rsvd_mask[reg]);
-		return -EIO;
-	}
-
-	/* Ignore all reserved bits */
-	val &= ~bb_emul_rsvd_mask[reg];
-	val |= data->reg[reg] & bb_emul_rsvd_mask[reg];
-
-	data->reg[reg] = val;
-
-	return 0;
-}
-
-/**
- * @brief Handle I2C read message. Response is obtained from reg field of bb
- *        emul data.
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg Register address to read
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bb_emul_handle_read(struct i2c_emul *emul, int reg)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	if (reg >= BB_RETIMER_REG_COUNT) {
-		LOG_ERR("Read unknown register 0x%x", reg);
-
-		return -EIO;
-	}
-
-	data->data_dword = data->reg[reg];
-
-	return 0;
-}
-
-/**
- * @brief Function called for each byte of write message. Data are stored
- *        in data_dword field of bb_emul_data
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg First byte of write message
- * @param val Received byte of write message
- * @param bytes Number of bytes already received
- *
- * @return 0 on success
- */
-static int bb_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-			      int bytes)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	if (bytes == 1) {
-		data->data_dword = 0;
-		if (val != 4) {
-			LOG_WRN("Invalid write size");
-		}
-	} else if (bytes < 6) {
-		data->data_dword |= val << (8 * (bytes - 2));
-	}
-
-	return 0;
-}
-
-/**
- * @brief Function called for each byte of read message. data_dword is converted
- *        to read message response.
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg First byte of last write message
- * @param val Pointer where byte to read should be stored
- * @param bytes Number of bytes already readed
- *
- * @return 0 on success
- */
-static int bb_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-			     int bytes)
-{
-	struct bb_emul_data *data;
-
-	data = BB_DATA_FROM_I2C_EMUL(emul);
-
-	/* First byte of read message is read size which is always 4 */
-	if (bytes == 0) {
-		*val = 4;
-		return 0;
-	}
-
-	*val = data->data_dword & 0xff;
-	data->data_dword >>= 8;
-
-	return 0;
-}
-
-/**
- * @brief Get currently accessed register, which always equals to selected
- *        register.
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg First byte of last write message
- * @param bytes Number of bytes already handled from current message
- * @param read If currently handled is read message
- *
- * @return Currently accessed register
- */
-static int bb_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
-			      bool read)
-{
-	return reg;
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api bb_emul_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-/**
- * @brief Set up a new BB retimer emulator
- *
- * This should be called for each BB retimer device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int bb_emul_init(const struct emul *emul,
-			const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &bb_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	bb_emul_reset(&data->emul);
-
-	return ret;
-}
-
-#define BB_RETIMER_EMUL(n)						\
-	static struct bb_emul_data bb_emul_data_##n = {			\
-		.vendor_id = DT_STRING_TOKEN(DT_DRV_INST(n), vendor),	\
-		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
-		.error_on_rsvd_write = DT_INST_PROP(n,			\
-					error_on_reserved_bit_write),	\
-		.common = {						\
-			.start_write = NULL,				\
-			.write_byte = bb_emul_write_byte,		\
-			.finish_write = bb_emul_handle_write,		\
-			.start_read = bb_emul_handle_read,		\
-			.read_byte = bb_emul_read_byte,			\
-			.finish_read = NULL,				\
-			.access_reg = bb_emul_access_reg,		\
-		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bb_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bb_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bb_emul_init, DT_DRV_INST(n), &bb_emul_cfg_##n,	\
-		    &bb_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL)
-
-#define BB_RETIMER_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bb_emul_data_##n.common.emul;
-
-/** Check description in emul_bb_emulator.h */
-struct i2c_emul *bb_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_bma255.c b/zephyr/emul/emul_bma255.c
deleted file mode 100644
index 77b1f5246c..0000000000
--- a/zephyr/emul/emul_bma255.c
+++ /dev/null
@@ -1,1042 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_bma255
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_bma255);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_bma255.h"
-
-#include "driver/accel_bma2x2.h"
-
-#define BMA_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bma_emul_data, common)
-
-/** Run-time data used by the emulator */
-struct bma_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Value of data byte in ongoing write message */
-	uint8_t write_byte;
-
-	/** Current state of all emulated BMA255 registers */
-	uint8_t reg[0x40];
-	/** Current state of NVM where offset and GP0/1 can be saved */
-	uint8_t nvm_x;
-	uint8_t nvm_y;
-	uint8_t nvm_z;
-	uint8_t nvm_gp0;
-	uint8_t nvm_gp1;
-	/** Internal offset values used in calculations */
-	int16_t off_x;
-	int16_t off_y;
-	int16_t off_z;
-	/** Internal values of accelerometr */
-	int16_t acc_x;
-	int16_t acc_y;
-	int16_t acc_z;
-
-	/**
-	 * Return error when trying to start offset compensation when not ready
-	 * flag is set.
-	 */
-	bool error_on_cal_trg_nrdy;
-	/**
-	 * Return error when trying to start offset compensation with range
-	 * set to value different than 2G.
-	 */
-	bool error_on_cal_trg_bad_range;
-	/** Return error when trying to write to RO register */
-	bool error_on_ro_write;
-	/** Return error when trying to write 1 to reserved bit */
-	bool error_on_rsvd_write;
-	/** Return error when trying to access MSB before LSB */
-	bool error_on_msb_first;
-	/**
-	 * Flag set when LSB register is accessed and cleared when MSB is
-	 * accessed. Allows to track order of accessing acc registers
-	 */
-	bool lsb_x_read;
-	bool lsb_y_read;
-	bool lsb_z_read;
-};
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
-{
-	struct bma_emul_data *data;
-
-	if (reg < 0 || reg > BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
-		return;
-	}
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->reg[reg] = val;
-}
-
-/** Check description in emul_bma255.h */
-uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg)
-{
-	struct bma_emul_data *data;
-
-	if (reg < 0 || reg > BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
-		return 0;
-	}
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	return data->reg[reg];
-}
-
-/**
- * @brief Convert @p val to two's complement representation. It makes sure that
- *        bit representation is correct even on platforms which represent
- *        signed inteager in different format. Unsigned bit representation
- *        allows to use well defined bitwise operations on returned value.
- *
- * @param val Inteager that is converted
- *
- * @return two's complement representation of @p val
- */
-static uint16_t bma_emul_val_to_twos_comp(int16_t val)
-{
-	uint16_t twos_comp_val;
-
-	/* Make sure that value is converted to twos compliment format */
-	if (val < 0) {
-		twos_comp_val = (uint16_t)(-val);
-		twos_comp_val = ~twos_comp_val + 1;
-	} else {
-		twos_comp_val = (uint16_t)val;
-	}
-
-	return twos_comp_val;
-}
-
-/**
- * @brief Convert value from NVM format (8bit, 0x01 == 7.8mg) to internal
- *        offset format (16bit, 0x01 == 0.97mg).
- *
- * @param nvm Value in NVM format (8bit, 0x01 == 7.8mg). This is binary
- *            representation of two's complement signed number.
- *
- * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.97mg)
- */
-static int16_t bma_emul_nvm_to_off(uint8_t nvm)
-{
-	int16_t offset;
-	int8_t sign;
-
-	if (nvm & BIT(7)) {
-		sign = -1;
-		/* NVM value is in two's complement format */
-		nvm = ~nvm + 1;
-	} else {
-		sign = 1;
-	}
-
-	offset = (int16_t)nvm;
-	/* LSB in NVM is 7.8mg, while LSB in internal offset is 0.97mg */
-	offset *= sign * 8;
-
-	return offset;
-}
-
-/**
- * @brief Convert value from internal offset format (16bit, 0x01 == 0.97mg) to
- *        NVM format (8bit, 0x01 == 7.8mg). Function makes sure that NVM value
- *        is representation of two's complement signed number.
- *
- * @param val Value in internal offset format (16bit, 0x01 == 0.97mg).
- *
- * @return nvm NVM format representation of @p val (8bit, 0x01 == 7.8mg)
- */
-static uint8_t bma_emul_off_to_nvm(int16_t off)
-{
-	uint16_t twos_comp_val;
-	uint8_t nvm = 0;
-
-	twos_comp_val = bma_emul_val_to_twos_comp(off);
-
-	/*
-	 * LSB in internal representation has value 0.97mg, while in NVM
-	 * LSB is 7.8mg. Skip 0.97mg, 1.9mg and 3.9mg bits.
-	 */
-	nvm |= (twos_comp_val >> 3) & 0x7f;
-	/* Set sign bit */
-	nvm |= (twos_comp_val & BIT(15)) ? BIT(7) : 0x00;
-
-	return nvm;
-}
-
-/** Check description in emul_bma255.h */
-int16_t bma_emul_get_off(struct i2c_emul *emul, int axis)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMA_EMUL_AXIS_X:
-		return data->off_x;
-	case BMA_EMUL_AXIS_Y:
-		return data->off_y;
-	case BMA_EMUL_AXIS_Z:
-		return data->off_z;
-	}
-
-	return 0;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMA_EMUL_AXIS_X:
-		data->off_x = val;
-		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_x);
-		break;
-	case BMA_EMUL_AXIS_Y:
-		data->off_y = val;
-		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_y);
-		break;
-	case BMA_EMUL_AXIS_Z:
-		data->off_z = val;
-		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_z);
-		break;
-	}
-}
-
-/** Check description in emul_bma255.h */
-int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMA_EMUL_AXIS_X:
-		return data->acc_x;
-	case BMA_EMUL_AXIS_Y:
-		return data->acc_y;
-	case BMA_EMUL_AXIS_Z:
-		return data->acc_z;
-	}
-
-	return 0;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMA_EMUL_AXIS_X:
-		data->acc_x = val;
-		break;
-	case BMA_EMUL_AXIS_Y:
-		data->acc_y = val;
-		break;
-	case BMA_EMUL_AXIS_Z:
-		data->acc_z = val;
-		break;
-	}
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_err_on_cal_nrdy(struct i2c_emul *emul, bool set)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_cal_trg_nrdy = set;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_err_on_cal_bad_range(struct i2c_emul *emul, bool set)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_cal_trg_bad_range = set;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_ro_write = set;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_rsvd_write = set;
-}
-
-/** Check description in emul_bma255.h */
-void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_msb_first = set;
-}
-
-/** Mask reserved bits in each register of BMA255 */
-static const uint8_t bma_emul_rsvd_mask[] = {
-	[BMA2x2_CHIP_ID_ADDR]			= 0x00,
-	[0x01]					= 0xff, /* Reserved */
-	[BMA2x2_X_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_X_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_Y_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_Y_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_Z_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_Z_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_TEMP_ADDR]			= 0x00,
-	[BMA2x2_STAT1_ADDR]			= 0x00,
-	[BMA2x2_STAT2_ADDR]			= 0x1f,
-	[BMA2x2_STAT_TAP_SLOPE_ADDR]		= 0x00,
-	[BMA2x2_STAT_ORIENT_HIGH_ADDR]		= 0x00,
-	[0x0d]					= 0xff, /* Reserved */
-	[BMA2x2_STAT_FIFO_ADDR]			= 0x00,
-	[BMA2x2_RANGE_SELECT_ADDR]		= 0xf0,
-	[BMA2x2_BW_SELECT_ADDR]			= 0xe0,
-	[BMA2x2_MODE_CTRL_ADDR]			= 0x01,
-	[BMA2x2_LOW_NOISE_CTRL_ADDR]		= 0x9f,
-	[BMA2x2_DATA_CTRL_ADDR]			= 0x3f,
-	[BMA2x2_RST_ADDR]			= 0x00,
-	[0x15]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_ENABLE1_ADDR]		= 0x08,
-	[BMA2x2_INTR_ENABLE2_ADDR]		= 0x80,
-	[BMA2x2_INTR_SLOW_NO_MOTION_ADDR]	= 0xf0,
-	[BMA2x2_INTR1_PAD_SELECT_ADDR]		= 0x00,
-	[BMA2x2_INTR_DATA_SELECT_ADDR]		= 0x18,
-	[BMA2x2_INTR2_PAD_SELECT_ADDR]		= 0x00,
-	[0x1c]					= 0xff, /* Reserved */
-	[0x1d]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_SOURCE_ADDR]		= 0xc0,
-	[0x1f]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_SET_ADDR]			= 0xf0,
-	[BMA2x2_INTR_CTRL_ADDR]			= 0x70,
-	[BMA2x2_LOW_DURN_ADDR]			= 0x00,
-	[BMA2x2_LOW_THRES_ADDR]			= 0x00,
-	[BMA2x2_LOW_HIGH_HYST_ADDR]		= 0x38,
-	[BMA2x2_HIGH_DURN_ADDR]			= 0x00,
-	[BMA2x2_HIGH_THRES_ADDR]		= 0x00,
-	[BMA2x2_SLOPE_DURN_ADDR]		= 0x00,
-	[BMA2x2_SLOPE_THRES_ADDR]		= 0x00,
-	[BMA2x2_SLOW_NO_MOTION_THRES_ADDR]	= 0x00,
-	[BMA2x2_TAP_PARAM_ADDR]			= 0x38,
-	[BMA2x2_TAP_THRES_ADDR]			= 0x20,
-	[BMA2x2_ORIENT_PARAM_ADDR]		= 0x80,
-	[BMA2x2_THETA_BLOCK_ADDR]		= 0x80,
-	[BMA2x2_THETA_FLAT_ADDR]		= 0xc0,
-	[BMA2x2_FLAT_HOLD_TIME_ADDR]		= 0xc8,
-	[BMA2x2_FIFO_WML_TRIG]			= 0xc0,
-	[0x31]					= 0xff, /* Reserved */
-	[BMA2x2_SELFTEST_ADDR]			= 0xf8,
-	[BMA2x2_EEPROM_CTRL_ADDR]		= 0x00,
-	[BMA2x2_SERIAL_CTRL_ADDR]		= 0xf8,
-	[0x35]					= 0xff, /* Reserved */
-	[BMA2x2_OFFSET_CTRL_ADDR]		= 0x08,
-	[BMA2x2_OFC_SETTING_ADDR]		= 0x80,
-	[BMA2x2_OFFSET_X_AXIS_ADDR]		= 0x00,
-	[BMA2x2_OFFSET_Y_AXIS_ADDR]		= 0x00,
-	[BMA2x2_OFFSET_Z_AXIS_ADDR]		= 0x00,
-	[BMA2x2_GP0_ADDR]			= 0x00,
-	[BMA2x2_GP1_ADDR]			= 0x00,
-	[0x3d]					= 0xff, /* Reserved */
-	[BMA2x2_FIFO_MODE_ADDR]			= 0x3c,
-	[BMA2x2_FIFO_DATA_OUTPUT_ADDR]		= 0x00,
-};
-
-/**
- * @brief Reset register values and internal representation of offset and two
- *        general purpose registers
- *
- * @param emul Pointer to BMA255 emulator
- */
-static void bma_emul_restore_nvm(struct i2c_emul *emul)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	/* Restore registers values */
-	data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = data->nvm_x;
-	data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = data->nvm_y;
-	data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = data->nvm_z;
-	data->reg[BMA2x2_GP0_ADDR] = data->nvm_gp0;
-	data->reg[BMA2x2_GP1_ADDR] = data->nvm_gp1;
-
-	/* Restore internal offset values */
-	data->off_x = bma_emul_nvm_to_off(data->nvm_x);
-	data->off_y = bma_emul_nvm_to_off(data->nvm_y);
-	data->off_z = bma_emul_nvm_to_off(data->nvm_z);
-}
-
-/**
- * @brief Reset registers to default values and restore registers backed by NVM
- *
- * @param emul Pointer to BMA255 emulator
- */
-static void bma_emul_reset(struct i2c_emul *emul)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[BMA2x2_CHIP_ID_ADDR]			= 0xfa;
-	data->reg[0x01]					= 0x00; /* Reserved */
-	data->reg[BMA2x2_X_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_X_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Y_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Y_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Z_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Z_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_TEMP_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT1_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT2_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR]		= 0x00;
-	data->reg[0x0d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_STAT_FIFO_ADDR]		= 0x00;
-	data->reg[BMA2x2_RANGE_SELECT_ADDR]		= 0x03;
-	data->reg[BMA2x2_BW_SELECT_ADDR]		= 0x0f;
-	data->reg[BMA2x2_MODE_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_DATA_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_RST_ADDR]			= 0x00;
-	data->reg[0x15]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_ENABLE1_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_ENABLE2_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR]	= 0x00;
-	data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_DATA_SELECT_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR]		= 0x00;
-	data->reg[0x1c]					= 0xff; /* Reserved */
-	data->reg[0x1d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_SOURCE_ADDR]		= 0x00;
-	data->reg[0x1f]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_SET_ADDR]			= 0x05;
-	data->reg[BMA2x2_INTR_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_LOW_DURN_ADDR]			= 0x09;
-	data->reg[BMA2x2_LOW_THRES_ADDR]		= 0x30;
-	data->reg[BMA2x2_LOW_HIGH_HYST_ADDR]		= 0x81;
-	data->reg[BMA2x2_HIGH_DURN_ADDR]		= 0x0f;
-	data->reg[BMA2x2_HIGH_THRES_ADDR]		= 0xc0;
-	data->reg[BMA2x2_SLOPE_DURN_ADDR]		= 0x00;
-	data->reg[BMA2x2_SLOPE_THRES_ADDR]		= 0x14;
-	data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR]	= 0x14;
-	data->reg[BMA2x2_TAP_PARAM_ADDR]		= 0x04;
-	data->reg[BMA2x2_TAP_THRES_ADDR]		= 0x0a;
-	data->reg[BMA2x2_ORIENT_PARAM_ADDR]		= 0x18;
-	data->reg[BMA2x2_THETA_BLOCK_ADDR]		= 0x48;
-	data->reg[BMA2x2_THETA_FLAT_ADDR]		= 0x08;
-	data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR]		= 0x11;
-	data->reg[BMA2x2_FIFO_WML_TRIG]			= 0x00;
-	data->reg[0x31]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_SELFTEST_ADDR]			= 0x00;
-	data->reg[BMA2x2_EEPROM_CTRL_ADDR]		= 0xf0;
-	data->reg[BMA2x2_SERIAL_CTRL_ADDR]		= 0x00;
-	data->reg[0x35]					= 0x00; /* Reserved */
-	data->reg[BMA2x2_OFFSET_CTRL_ADDR]		= 0x10;
-	data->reg[BMA2x2_OFC_SETTING_ADDR]		= 0x00;
-	data->reg[0x3d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_FIFO_MODE_ADDR]		= 0x00;
-	data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR]		= 0x00;
-
-	/* Restore registers backed in NVM */
-	bma_emul_restore_nvm(emul);
-}
-
-/**
- * @brief Convert range in format of RANGE_SELECT register to number of bits
- *        that should be shifted right to obtain 12 bit reported accelerometer
- *        value from internal 16 bit value
- *
- * @param range Value of RANGE_SELECT register
- *
- * @return shift Number of LSB that should be ignored from internal
- *               accelerometer value
- */
-static int bma_emul_range_to_shift(uint8_t range)
-{
-	switch (range & BMA2x2_RANGE_SELECT_MSK) {
-	case BMA2x2_RANGE_2G:
-		return 0;
-	case BMA2x2_RANGE_4G:
-		return 1;
-	case BMA2x2_RANGE_8G:
-		return 2;
-	case BMA2x2_RANGE_16G:
-		return 3;
-	default:
-		return -1;
-	}
-}
-
-/**
- * @brief Handle write requests to NVM control register. Allows to load/store
- *        NVM only when ready in current NVM control register is set. Load and
- *        stores to NVM are backed in bma_emul_data structure
- *
- * @param emul Pointer to BMA255 emulator
- * @param val Value that is being written to NVM contorl register
- *
- * @return 0 on success
- */
-static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val)
-{
-	struct bma_emul_data *data;
-	uint8_t writes_rem;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	/* NVM not ready, ignore write/load requests */
-	if (!(data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_RDY)) {
-		return 0;
-	}
-
-	/* Restore data from NVM */
-	if (val & BMA2x2_EEPROM_LOAD) {
-		bma_emul_restore_nvm(emul);
-	}
-
-	writes_rem = (data->reg[BMA2x2_EEPROM_CTRL_ADDR] &
-		      BMA2x2_EEPROM_REMAIN_MSK) >> BMA2x2_EEPROM_REMAIN_OFF;
-	/* Trigger write is set, write is unlocked and writes remaining */
-	if (val & BMA2x2_EEPROM_PROG &&
-	    data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_PROG_EN &&
-	    writes_rem > 0) {
-		data->nvm_x = data->reg[BMA2x2_OFFSET_X_AXIS_ADDR];
-		data->nvm_y = data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR];
-		data->nvm_z = data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR];
-		data->nvm_gp0 = data->reg[BMA2x2_GP0_ADDR];
-		data->nvm_gp1 = data->reg[BMA2x2_GP1_ADDR];
-		/* Decrement number of remaining writes and save it in reg */
-		writes_rem--;
-		data->reg[BMA2x2_EEPROM_CTRL_ADDR] &=
-					~BMA2x2_EEPROM_REMAIN_MSK;
-		data->reg[BMA2x2_EEPROM_CTRL_ADDR] |=
-					writes_rem << BMA2x2_EEPROM_REMAIN_OFF;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Clear all interrupt registers
- *
- * @param emul Pointer to BMA255 emulator
- */
-static void bma_emul_clear_int(struct i2c_emul *emul)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[BMA2x2_STAT1_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT2_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR]	= 0x00;
-	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR]	= 0x00;
-}
-
-/**
- * @brief Get target value from offset compensation setting register for given
- *        @p axis
- *
- * @param emul Pointer to BMA255 emulator
- * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
- *
- * @return target Value to which offset compensation should be calculated
- */
-static int16_t bma_emul_get_target(struct i2c_emul *emul, int axis)
-{
-	struct bma_emul_data *data;
-	uint8_t target;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	target = data->reg[BMA2x2_OFC_SETTING_ADDR] >>
-		 BMA2x2_OFC_TARGET_AXIS(axis);
-	switch (target) {
-	case BMA2x2_OFC_TARGET_0G:
-		return 0;
-	case BMA2x2_OFC_TARGET_PLUS_1G:
-		return BMA_EMUL_1G;
-	case BMA2x2_OFC_TARGET_MINUS_1G:
-		return -((int)BMA_EMUL_1G);
-	}
-
-	return 0;
-}
-
-/**
- * @brief Handle writes to offset compensation control register. It allows to
- *        reset offset registers. It check if offset compenstation is ready
- *        and if range is set to 2G (required for fast compensation according
- *        to BMA255 documentation). If fast compensation is successfully
- *        triggered, internal offset value is set to
- *        (target - internal accelerometer value).
- *
- * @param emul Pointer to BMA255 emulator
- * @param val Value being written to offset compensation control register
- *
- * @return 0 on success
- * @return -EIO when trying to start fast compensation in wrong emulator state
- */
-static int bma_emul_handle_off_comp(struct i2c_emul *emul, uint8_t val)
-{
-	struct bma_emul_data *data;
-	uint8_t trigger;
-	int16_t target;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	if (val & BMA2x2_OFFSET_RESET) {
-		data->off_x = 0;
-		data->off_y = 0;
-		data->off_z = 0;
-		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = 0;
-		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = 0;
-		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0;
-	}
-
-
-	trigger = (val & BMA2x2_OFFSET_TRIGGER_MASK) >>
-		  BMA2x2_OFFSET_TRIGGER_OFF;
-
-	if (!(data->reg[BMA2x2_OFFSET_CTRL_ADDR] & BMA2x2_OFFSET_CAL_READY)) {
-		if (data->error_on_cal_trg_nrdy && trigger) {
-			LOG_ERR("Trying to start offset comp when not ready");
-			return -EIO;
-		}
-
-		return 0;
-	}
-
-	if (bma_emul_range_to_shift(data->reg[BMA2x2_RANGE_SELECT_ADDR]) != 0 &&
-	    trigger && data->error_on_cal_trg_bad_range) {
-		LOG_ERR("Trying to start offset comp with range other than 2G");
-		return -EIO;
-	}
-
-	switch (trigger) {
-	case 1:
-		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_X);
-		bma_emul_set_off(emul, BMA_EMUL_AXIS_X, target - data->acc_x);
-		break;
-	case 2:
-		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_Y);
-		bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, target - data->acc_y);
-		break;
-	case 3:
-		target = bma_emul_get_target(emul, BMA_EMUL_AXIS_Z);
-		bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, target - data->acc_z);
-		break;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Handle I2C write message. It is checked if accessed register isn't RO
- *        and reserved bits are set to 0. Write set value of reg field of bma
- *        emulator data ignoring reserved bits and write only bits. Some
- *        commands are handled specialy.
- *
- * @param emul Pointer to BMA255 emulator
- * @param reg Register which is written
- * @param bytes Number of bytes in I2C write message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
-{
-	struct bma_emul_data *data;
-	uint8_t val;
-	int ret;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	val = data->write_byte;
-
-	if (bytes > 2) {
-		LOG_ERR("Too long write command");
-		return -EIO;
-	}
-
-	/* This write only selected register for I2C read message */
-	if (bytes < 2) {
-		return 0;
-	}
-
-	if (reg <= BMA2x2_STAT_FIFO_ADDR ||
-	    reg >= BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
-		if (data->error_on_ro_write) {
-			LOG_ERR("Writing to reg 0x%x which is RO", reg);
-			return -EIO;
-		}
-
-		return 0;
-	}
-
-	if (data->error_on_rsvd_write && bma_emul_rsvd_mask[reg] & val) {
-		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
-			val, reg, bma_emul_rsvd_mask[reg]);
-		return -EIO;
-	}
-
-
-	switch (reg) {
-	case BMA2x2_RST_ADDR:
-		if (val == BMA2x2_CMD_SOFT_RESET) {
-			bma_emul_reset(emul);
-		}
-		return 0;
-	case BMA2x2_INTR_CTRL_ADDR:
-		if (val & BMA2x2_INTR_CTRL_RST_INT) {
-			bma_emul_clear_int(emul);
-		}
-		/* Don't set write only bit in register */
-		val &= ~BMA2x2_INTR_CTRL_RST_INT;
-		break;
-	case BMA2x2_EEPROM_CTRL_ADDR:
-		bma_emul_handle_nvm_write(emul, val);
-		/* Only programing enable bit is RW */
-		val &= BMA2x2_EEPROM_PROG_EN;
-		val |= data->reg[reg] & ~BMA2x2_EEPROM_PROG_EN;
-		break;
-	case BMA2x2_OFFSET_CTRL_ADDR:
-		ret = bma_emul_handle_off_comp(emul, val);
-		if (ret) {
-			return -EIO;
-		}
-		/* Only slow compensation bits are RW */
-		val &= BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y |
-		       BMA2x2_OFFSET_CAL_SLOW_Z;
-		val |= data->reg[reg] & ~(BMA2x2_OFFSET_CAL_SLOW_X |
-					  BMA2x2_OFFSET_CAL_SLOW_Y |
-					  BMA2x2_OFFSET_CAL_SLOW_Z);
-		break;
-	/* Change internal offset to value set in I2C message */
-	case BMA2x2_OFFSET_X_AXIS_ADDR:
-		data->off_x = bma_emul_nvm_to_off(val);
-		break;
-	case BMA2x2_OFFSET_Y_AXIS_ADDR:
-		data->off_y = bma_emul_nvm_to_off(val);
-		break;
-	case BMA2x2_OFFSET_Z_AXIS_ADDR:
-		data->off_z = bma_emul_nvm_to_off(val);
-		break;
-	case BMA2x2_RANGE_SELECT_ADDR:
-		ret = bma_emul_range_to_shift(val);
-		if (ret < 0) {
-			LOG_ERR("Unknown range select value 0x%x", val);
-			return -EIO;
-		}
-		break;
-	}
-
-	/* Ignore all reserved bits */
-	val &= ~bma_emul_rsvd_mask[reg];
-	val |= data->reg[reg] & bma_emul_rsvd_mask[reg];
-
-	data->reg[reg] = val;
-
-	return 0;
-}
-
-/**
- * @brief Get set accelerometer value for given register using internal axis
- *        state @p val. In case of accessing MSB with enabled shadowing,
- *        check if LSB was accessed first.
- *
- * @param emul Pointer to BMA255 emulator
- * @param lsb_reg LSB register address (BMA2x2_X_AXIS_LSB_ADDR,
- *                BMA2x2_Y_AXIS_LSB_ADDR, BMA2x2_Z_AXIS_LSB_ADDR)
- * @param lsb_read Pointer to variable which represent if last access to this
- *                 accelerometer value was through LSB register
- * @param lsb True if now accessing LSB, Flase if now accessing MSB
- * @param val Internal value of accessed accelerometer axis
- *
- * @return 0 on success
- * @return -EIO when accessing MSB before LSB with enabled shadowing
- */
-static int bma_emul_get_acc_val(struct i2c_emul *emul, int lsb_reg,
-				bool *lsb_read, bool lsb, int16_t val)
-{
-	struct bma_emul_data *data;
-	uint16_t twos_comp_val;
-	uint8_t new_data;
-	int msb_reg;
-	int shift;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	if (lsb) {
-		*lsb_read = 1;
-	} else if (!(data->reg[BMA2x2_DATA_CTRL_ADDR] &
-		     BMA2x2_DATA_SHADOW_DIS)) {
-		/*
-		 * If shadowing is enabled, error on first accessing MSB and
-		 * LSB wasn't accessed before, then return error.
-		 */
-		if (data->error_on_msb_first && !(*lsb_read)) {
-			return -EIO;
-		}
-		*lsb_read = 0;
-		/* If shadowing is enabled, LSB read should set correct value */
-		return 0;
-	}
-
-	twos_comp_val = bma_emul_val_to_twos_comp(val);
-	msb_reg = lsb_reg + 1;
-	shift = bma_emul_range_to_shift(data->reg[BMA2x2_RANGE_SELECT_ADDR]);
-
-	/* Save new data bit from register */
-	new_data = data->reg[lsb_reg] & BMA2x2_AXIS_LSB_NEW_DATA;
-	/* Shift 16 bit value to 12 bit set in range register */
-	twos_comp_val >>= shift;
-	/* Set [3:0] bits in first register */
-	data->reg[lsb_reg] = ((twos_comp_val << 4) & 0xf0) | new_data;
-	/* Set [11:4] bits in second register */
-	data->reg[msb_reg] = (twos_comp_val >> 4) & 0xff;
-
-	return 0;
-}
-
-/** Check description in emul_bma255.h */
-int bma_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, bool read)
-{
-	/*
-	 * Exclude first byte (select register) from total number of bytes
-	 * in I2C write message
-	 */
-	if (!read) {
-		bytes--;
-	}
-
-	if (reg <= BMA2x2_FIFO_DATA_OUTPUT_ADDR &&
-	    reg + bytes >= BMA2x2_FIFO_DATA_OUTPUT_ADDR) {
-		return BMA2x2_FIFO_DATA_OUTPUT_ADDR;
-	}
-
-	return reg + bytes;
-}
-
-/**
- * @brief Handle I2C read message. Response is obtained from reg field of bma
- *        emul data. When accessing accelerometer value, register data is first
- *        computed using internal emulator state.
- *
- * @param emul Pointer to BMA255 emulator
- * @param reg Register address to read
- * @param val Pointer where resultat should be stored
- * @param bytes Number of bytes in I2C read message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bma_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *val,
-				int bytes)
-{
-	struct bma_emul_data *data;
-	int ret;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
-
-	switch (reg) {
-	case BMA2x2_X_AXIS_LSB_ADDR:
-		/* Shouldn't fail for LSB */
-		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_x_read, true,
-					   data->acc_x + data->off_x);
-		break;
-	case BMA2x2_X_AXIS_MSB_ADDR:
-		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_x_read,
-					   false, data->acc_x + data->off_x);
-		if (ret) {
-			LOG_ERR("MSB X readed before LSB X");
-			return -EIO;
-		}
-		break;
-	case BMA2x2_Y_AXIS_LSB_ADDR:
-		/* Shouldn't fail for LSB */
-		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_y_read, true,
-					   data->acc_y + data->off_y);
-		break;
-	case BMA2x2_Y_AXIS_MSB_ADDR:
-		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_y_read,
-					   false, data->acc_y + data->off_y);
-		if (ret) {
-			LOG_ERR("MSB Y readed before LSB Y");
-			return -EIO;
-		}
-		break;
-	case BMA2x2_Z_AXIS_LSB_ADDR:
-		/* Shouldn't fail for LSB */
-		ret = bma_emul_get_acc_val(emul, reg, &data->lsb_z_read, true,
-					   data->acc_z + data->off_z);
-		break;
-	case BMA2x2_Z_AXIS_MSB_ADDR:
-		ret = bma_emul_get_acc_val(emul, reg - 1, &data->lsb_z_read,
-					   false, data->acc_z + data->off_z);
-		if (ret) {
-			LOG_ERR("MSB Z readed before LSB Z");
-			return -EIO;
-		}
-		break;
-	}
-
-	*val = data->reg[reg];
-
-	return 0;
-}
-
-/**
- * @brief Handle I2C write message. Saves data that will be stored in register.
- *
- * @param emul Pointer to BMA emulator
- * @param reg Register address that is accessed
- * @param val Data to write to the register
- * @param bytes Number of bytes already handled in this read message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bma_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-			       int bytes)
-{
-	struct bma_emul_data *data;
-
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	data->write_byte = val;
-
-	return 0;
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api bma_emul_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-/**
- * @brief Set up a new BMA255 emulator
- *
- * This should be called for each BMA255 device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int bma_emul_init(const struct emul *emul,
-			 const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &bma_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	bma_emul_reset(&data->emul);
-
-	return ret;
-}
-
-#define BMA255_EMUL(n)							\
-	static struct bma_emul_data bma_emul_data_##n = {		\
-		.nvm_x = DT_INST_PROP(n, nvm_off_x),			\
-		.nvm_y = DT_INST_PROP(n, nvm_off_y),			\
-		.nvm_z = DT_INST_PROP(n, nvm_off_z),			\
-		.nvm_gp0 = DT_INST_PROP(n, nvm_gp0),			\
-		.nvm_gp1 = DT_INST_PROP(n, nvm_gp1),			\
-		.acc_x = DT_INST_PROP(n, nvm_acc_x),			\
-		.acc_y = DT_INST_PROP(n, nvm_acc_y),			\
-		.acc_z = DT_INST_PROP(n, nvm_acc_z),			\
-		.error_on_cal_trg_nrdy = DT_INST_PROP(n,		\
-				error_on_compensation_not_ready),	\
-		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
-		.error_on_rsvd_write = DT_INST_PROP(n,			\
-					error_on_reserved_bit_write),	\
-		.error_on_msb_first = DT_INST_PROP(n,			\
-					error_on_msb_first_access),	\
-		.lsb_x_read = 0,					\
-		.lsb_y_read = 0,					\
-		.lsb_z_read = 0,					\
-		.common = {						\
-			.start_write = NULL,				\
-			.write_byte = bma_emul_write_byte,		\
-			.finish_write = bma_emul_handle_write,		\
-			.start_read = NULL,				\
-			.read_byte = bma_emul_handle_read,		\
-			.finish_read = NULL,				\
-			.access_reg = bma_emul_access_reg,		\
-		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bma_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bma_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bma_emul_init, DT_DRV_INST(n), &bma_emul_cfg_##n,	\
-		    &bma_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL)
-
-#define BMA255_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bma_emul_data_##n.common.emul;
-
-/** Check description in emul_bma255.h */
-struct i2c_emul *bma_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_bmi.c b/zephyr/emul/emul_bmi.c
deleted file mode 100644
index 7923fe0eb5..0000000000
--- a/zephyr/emul/emul_bmi.c
+++ /dev/null
@@ -1,1116 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_bmi
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_bmi);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_bmi.h"
-
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/accelgyro_bmi_common.h"
-
-#define BMI_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bmi_emul_data, common)
-
-/** Run-time data used by the emulator */
-struct bmi_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Current state of all emulated BMI registers */
-	uint8_t reg[BMI_EMUL_MAX_REG];
-	/** Internal offset values used in calculations */
-	int16_t off_acc_x;
-	int16_t off_acc_y;
-	int16_t off_acc_z;
-	int16_t off_gyr_x;
-	int16_t off_gyr_y;
-	int16_t off_gyr_z;
-	/** Internal values of sensors */
-	int32_t acc_x;
-	int32_t acc_y;
-	int32_t acc_z;
-	int32_t gyr_x;
-	int32_t gyr_y;
-	int32_t gyr_z;
-	/** Current state of NVM where offset and configuration can be saved */
-	uint8_t nvm[BMI_EMUL_MAX_NVM_REGS];
-
-	/** Return error when trying to write to RO register */
-	bool error_on_ro_write;
-	/** Return error when trying to write 1 to reserved bit */
-	bool error_on_rsvd_write;
-	/**
-	 * If effect of command is vissable after simulated time from issuing
-	 * command
-	 */
-	bool simulate_command_exec_time;
-	/** Return error when trying to read WO register */
-	bool error_on_wo_read;
-
-	/** Value of data byte in ongoing write message */
-	uint8_t write_byte;
-
-	/** List of FIFO frames */
-	struct bmi_emul_frame *fifo_frame;
-	/** First FIFO frame in byte format */
-	uint8_t fifo[21];
-	/** Number of FIFO frames that were skipped */
-	uint8_t fifo_skip;
-	/** Currently accessed byte of first frame */
-	int fifo_frame_byte;
-	/** Length of first frame */
-	int fifo_frame_len;
-
-	/** Last time when emulator was resetted in sensor time units */
-	int64_t zero_time;
-	/** Time when current command should end */
-	uint32_t cmd_end_time;
-
-	/** Emulated model of BMI */
-	int type;
-	/** Pointer to data specific for emulated model of BMI */
-	const struct bmi_emul_type_data *type_data;
-};
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
-{
-	struct bmi_emul_data *data;
-
-	if (reg < 0 || reg > BMI_EMUL_MAX_REG) {
-		return;
-	}
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-	data->reg[reg] = val;
-}
-
-/** Check description in emul_bmi.h */
-uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg)
-{
-	struct bmi_emul_data *data;
-
-	if (reg < 0 || reg > BMI_EMUL_MAX_REG) {
-		return 0;
-	}
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	return data->reg[reg];
-}
-
-/**
- * @brief Convert @p val to two's complement representation. It makes sure that
- *        bit representation is correct even on platforms which represent
- *        signed inteager in different format. Unsigned bit representation
- *        allows to use well defined bitwise operations on returned value.
- *
- * @param val Inteager that is converted
- *
- * @return two's complement representation of @p val
- */
-static uint32_t bmi_emul_val_to_twos_comp(int32_t val)
-{
-	uint32_t twos_comp_val;
-
-	/* Make sure that value is converted to twos compliment format */
-	if (val < 0) {
-		twos_comp_val = (uint32_t)(-val);
-		twos_comp_val = ~twos_comp_val + 1;
-	} else {
-		twos_comp_val = (uint32_t)val;
-	}
-
-	return twos_comp_val;
-}
-
-/**
- * @brief Convert accelerometer value from NVM format (8bit, 0x01 == 3.9mg)
- *        to internal offset format (16bit, 0x01 == 0.061mg).
- *
- * @param nvm Value in NVM format (8bit, 0x01 == 3.9mg). This is binary
- *            representation of two's complement signed number.
- *
- * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.061mg)
- */
-static int16_t bmi_emul_acc_nvm_to_off(uint8_t nvm)
-{
-	int16_t offset;
-	int8_t sign;
-
-	if (nvm & BIT(7)) {
-		sign = -1;
-		/* NVM value is in two's complement format */
-		nvm = ~nvm + 1;
-	} else {
-		sign = 1;
-	}
-
-	offset = (int16_t)nvm;
-	/* LSB in NVM is 3.9mg, while LSB in internal offset is 0.061mg */
-	offset *= sign * 64;
-
-	return offset;
-}
-
-/**
- * @brief Convert gyroscope value from NVM format (10bit, 0x01 == 0.061 °/s)
- *        to internal offset format (16bit, 0x01 == 0.0038 °/s)
- *
- * @param nvm Value in NVM format (10bit, 0x01 == 0.061 °/s). This is binary
- *            representation of two's complement signed number.
- *
- * @return offset Internal representation of @p nvm (16bit, 0x01 == 0.0038 °/s)
- */
-static int16_t bmi_emul_gyr_nvm_to_off(uint16_t nvm)
-{
-	int16_t offset;
-	int8_t sign;
-
-	if (nvm & BIT(9)) {
-		sign = -1;
-		/* NVM value is in two's complement format */
-		nvm = ~nvm + 1;
-	} else {
-		sign = 1;
-	}
-
-	/* Mask 10 bits which holds value */
-	nvm &= 0x3ff;
-
-	offset = (int16_t)nvm;
-	/* LSB in NVM is 0.061°/s, while LSB in internal offset is 0.0038°/s */
-	offset *= sign * 16;
-
-	return offset;
-}
-
-/**
- * @brief Convert accelerometer value from internal offset format
- *        (16bit, 0x01 == 0.061mg) to NVM format (8bit, 0x01 == 7.8mg).
- *        Function makes sure that NVM value is representation of two's
- *        complement signed number.
- *
- * @param val Value in internal offset format (16bit, 0x01 == 0.061mg).
- *
- * @return nvm NVM format representation of @p val (8bit, 0x01 == 3.9mg)
- */
-static uint8_t bmi_emul_acc_off_to_nvm(int16_t off)
-{
-	uint32_t twos_comp_val;
-	uint8_t nvm = 0;
-
-	twos_comp_val = bmi_emul_val_to_twos_comp(off);
-
-	/*
-	 * LSB in internal representation has value 0.061mg, while in NVM
-	 * LSB is 3.9mg. Skip 0.06mg, 0.12mg, 0.24mg, 0.48mg, 0.97mg and
-	 * 1.9mg bits.
-	 */
-	nvm |= (twos_comp_val >> 6) & 0x7f;
-	/* Set sign bit */
-	nvm |= (twos_comp_val & BIT(31)) ? BIT(7) : 0x00;
-
-	return nvm;
-}
-
-/**
- * @brief Convert gyroscope value from internal offset format
- *        (16bit, 0x01 == 0.0038°/s) to NVM format (10bit, 0x01 == 0.061°/s).
- *        Function makes sure that NVM value is representation of two's
- *        complement signed number.
- *
- * @param val Value in internal offset format (16bit, 0x01 == 0.0038°/s).
- *
- * @return nvm NVM format representation of @p val (10bit, 0x01 == 0.061°/s)
- */
-static uint16_t bmi_emul_gyr_off_to_nvm(int16_t off)
-{
-	uint32_t twos_comp_val;
-	uint16_t nvm = 0;
-
-	twos_comp_val = bmi_emul_val_to_twos_comp(off);
-
-	/*
-	 * LSB in internal representation has value 0.0038°/s, while in NVM
-	 * LSB is 0.061°/s. Skip 0.0038°/s, 0.0076°/s, 0.015°/s, and
-	 * 0.03°/s bits.
-	 */
-	nvm |= (twos_comp_val >> 4) & 0x1ff;
-	/* Set sign bit */
-	nvm |= (twos_comp_val & BIT(31)) ? BIT(9) : 0x00;
-
-	return nvm;
-}
-
-/** Check description in emul_bmi.h */
-int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMI_EMUL_ACC_X:
-		return data->off_acc_x;
-	case BMI_EMUL_ACC_Y:
-		return data->off_acc_y;
-	case BMI_EMUL_ACC_Z:
-		return data->off_acc_z;
-	case BMI_EMUL_GYR_X:
-		return data->off_gyr_x;
-	case BMI_EMUL_GYR_Y:
-		return data->off_gyr_y;
-	case BMI_EMUL_GYR_Z:
-		return data->off_gyr_z;
-	}
-
-	return 0;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
-		      int16_t val)
-{
-	struct bmi_emul_data *data;
-	uint16_t gyr_off;
-	uint8_t gyr98_shift;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMI_EMUL_ACC_X:
-		data->off_acc_x = val;
-		data->reg[data->type_data->acc_off_reg] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_x);
-		break;
-	case BMI_EMUL_ACC_Y:
-		data->off_acc_y = val;
-		data->reg[data->type_data->acc_off_reg + 1] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_y);
-		break;
-	case BMI_EMUL_ACC_Z:
-		data->off_acc_z = val;
-		data->reg[data->type_data->acc_off_reg + 2] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_z);
-		break;
-	case BMI_EMUL_GYR_X:
-		data->off_gyr_x = val;
-		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_x);
-		data->reg[data->type_data->gyr_off_reg] = gyr_off & 0xff;
-		gyr98_shift = 0;
-		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
-		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
-		break;
-	case BMI_EMUL_GYR_Y:
-		data->off_gyr_y = val;
-		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_y);
-		data->reg[data->type_data->gyr_off_reg + 1] = gyr_off & 0xff;
-		gyr98_shift = 2;
-		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
-		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
-		break;
-	case BMI_EMUL_GYR_Z:
-		data->off_gyr_z = val;
-		gyr_off = bmi_emul_gyr_off_to_nvm(data->off_gyr_z);
-		data->reg[data->type_data->gyr_off_reg + 2] = gyr_off & 0xff;
-		gyr98_shift = 4;
-		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
-		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
-		break;
-	}
-}
-
-/** Check description in emul_bmi.h */
-int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMI_EMUL_ACC_X:
-		return data->acc_x;
-	case BMI_EMUL_ACC_Y:
-		return data->acc_y;
-	case BMI_EMUL_ACC_Z:
-		return data->acc_z;
-	case BMI_EMUL_GYR_X:
-		return data->gyr_x;
-	case BMI_EMUL_GYR_Y:
-		return data->gyr_y;
-	case BMI_EMUL_GYR_Z:
-		return data->gyr_z;
-	}
-
-	return 0;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
-			int32_t val)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case BMI_EMUL_ACC_X:
-		data->acc_x = val;
-		break;
-	case BMI_EMUL_ACC_Y:
-		data->acc_y = val;
-		break;
-	case BMI_EMUL_ACC_Z:
-		data->acc_z = val;
-		break;
-	case BMI_EMUL_GYR_X:
-		data->gyr_x = val;
-		break;
-	case BMI_EMUL_GYR_Y:
-		data->gyr_y = val;
-		break;
-	case BMI_EMUL_GYR_Z:
-		data->gyr_z = val;
-		break;
-	}
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_ro_write = set;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_rsvd_write = set;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_wo_read(struct i2c_emul *emul, bool set)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_wo_read = set;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_simulate_cmd_exec_time(struct i2c_emul *emul, bool set)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-	data->simulate_command_exec_time = set;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_skipped_frames(struct i2c_emul *emul, uint8_t skip)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	data->fifo_skip = skip;
-}
-
-/**
- * @brief Convert current time to sensor time (39 us units)
- *
- * @return time in 39 us units
- */
-static int64_t bmi_emul_get_sensortime(void)
-{
-	return k_uptime_ticks() * 1000000 / 39 / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
-}
-
-/**
- * @brief Set registers at address @p reg with sensor time that elapsed since
- *        last reset of emulator
- *
- * @param emul Pointer to BMI emulator
- * @param reg Pointer to 3 byte array, where current sensor time should be
- *            stored
- */
-static void bmi_emul_set_sensortime_reg(struct i2c_emul *emul, uint8_t *reg)
-{
-	struct bmi_emul_data *data;
-	uint32_t twos_comp_val;
-	int64_t time;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	time = bmi_emul_get_sensortime();
-
-	twos_comp_val = bmi_emul_val_to_twos_comp(time - data->zero_time);
-
-	*reg = twos_comp_val & 0xff;
-	*(reg + 1) = (twos_comp_val >> 8) & 0xff;
-	*(reg + 2) = (twos_comp_val >> 16) & 0xff;
-}
-
-/**
- * @brief Convert given sensor axis @p val from internal units to register
- *        units. It shifts value by @p shift bits to the right to account
- *        range set in emulator's registers. Result is saved at address @p reg
- *
- * @param emul Pointer to BMI emulator
- * @param val Accelerometer or gyroscope value in internal units
- * @param reg Pointer to 2 byte array, where sensor value should be stored
- * @param shift How many bits should be shift to the right
- */
-static void bmi_emul_set_data_reg(struct i2c_emul *emul, int32_t val,
-				  uint8_t *reg, int shift)
-{
-	struct bmi_emul_data *data;
-	uint32_t twos_comp_val;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	twos_comp_val = bmi_emul_val_to_twos_comp(val);
-
-	/* Shift unused bits because of selected range */
-	twos_comp_val >>= shift;
-
-	*reg = twos_comp_val & 0xff;
-	*(reg + 1) = (twos_comp_val >> 8) & 0xff;
-}
-
-/**
- * @brief Compute length of given FIFO @p frame. If frame is null then length
- *        of empty frame is returned.
- *
- * @param emul Pointer to BMI emulator
- * @param frame Pointer to FIFO frame
- * @param tag_time Indicate if sensor time should be included in empty frame
- * @param header Indicate if header should be included in frame
- *
- * @return length of frame
- */
-static uint8_t bmi_emul_get_frame_len(struct i2c_emul *emul,
-				      struct bmi_emul_frame *frame,
-				      bool tag_time, bool header)
-{
-	struct bmi_emul_data *data;
-	int len;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	/* Empty FIFO frame */
-	if (frame == NULL) {
-		if (tag_time && header) {
-			/* Header of sensortime + sensortime + empty FIFO */
-			return 5;
-		}
-
-		/* Empty fifo */
-		return 1;
-	}
-
-	/* Config FIFO frame */
-	if (frame->type & BMI_EMUL_FRAME_CONFIG) {
-		if (header) {
-			/* Header + byte of data */
-			len = 2;
-			if (data->type_data->sensortime_follow_config_frame) {
-				/* Sensortime data */
-				len += 3;
-			}
-
-			return len;
-		}
-
-		/* This frame doesn't exist in headerless mode */
-		return 0;
-	}
-
-	/* Sensor data FIFO frame */
-	if (header) {
-		len = 1;
-	} else {
-		len = 0;
-	}
-
-	if (frame->type & BMI_EMUL_FRAME_ACC) {
-		len += 6;
-	}
-	if (frame->type & BMI_EMUL_FRAME_MAG) {
-		len += 8;
-	}
-	if (frame->type & BMI_EMUL_FRAME_GYR) {
-		len += 6;
-	}
-
-	return len;
-}
-
-/**
- * @brief Set given FIFO @p frame as current frame in fifo field of emulator
- *        data structure
- *
- * @param emul Pointer to BMI emulator
- * @param frame Pointer to FIFO frame
- * @param tag_time Indicate if sensor time should be included in empty frame
- * @param header Indicate if header should be included in frame
- * @param acc_shift How many bits should be right shifted from accelerometer
- *                  data
- * @param gyr_shift How many bits should be right shifted from gyroscope data
- */
-static void bmi_emul_set_current_frame(struct i2c_emul *emul,
-				       struct bmi_emul_frame *frame,
-				       bool tag_time, bool header,
-				       int acc_shift, int gyr_shift)
-{
-	struct bmi_emul_data *data;
-	int i = 0;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	data->fifo_frame_byte = 0;
-	data->fifo_frame_len = bmi_emul_get_frame_len(emul, frame, tag_time,
-						      header);
-	/* Empty FIFO frame */
-	if (frame == NULL) {
-		if (tag_time && header) {
-			/* Header */
-			data->fifo[0] = BMI_EMUL_FIFO_HEAD_TIME;
-			bmi_emul_set_sensortime_reg(emul, &(data->fifo[1]));
-			i = 4;
-		}
-
-		/* Empty header */
-		data->fifo[i] = BMI_EMUL_FIFO_HEAD_EMPTY;
-
-		return;
-	}
-
-	/* Config FIFO frame */
-	if (frame->type & BMI_EMUL_FRAME_CONFIG) {
-		/* Header */
-		data->fifo[0] = BMI_EMUL_FIFO_HEAD_CONFIG;
-		data->fifo[1] = frame->config;
-		if (data->type_data->sensortime_follow_config_frame) {
-			bmi_emul_set_sensortime_reg(emul, &(data->fifo[2]));
-		}
-
-		return;
-	}
-
-	/* Sensor data FIFO frame */
-	if (header) {
-		data->fifo[0] = BMI_EMUL_FIFO_HEAD_DATA;
-		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_MAG ?
-						BMI_EMUL_FIFO_HEAD_DATA_MAG : 0;
-		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_GYR ?
-						BMI_EMUL_FIFO_HEAD_DATA_GYR : 0;
-		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_ACC ?
-						BMI_EMUL_FIFO_HEAD_DATA_ACC : 0;
-		data->fifo[0] |= frame->tag & BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK;
-		i = 1;
-	}
-
-	if (frame->type & BMI_EMUL_FRAME_MAG) {
-		bmi_emul_set_data_reg(emul, frame->mag_x, &(data->fifo[i]), 0);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->mag_y, &(data->fifo[i]), 0);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->mag_z, &(data->fifo[i]), 0);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->rhall, &(data->fifo[i]), 0);
-		i += 2;
-	}
-
-	if (frame->type & BMI_EMUL_FRAME_GYR) {
-		bmi_emul_set_data_reg(emul, frame->gyr_x, &(data->fifo[i]),
-				      gyr_shift);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->gyr_y, &(data->fifo[i]),
-				      gyr_shift);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->gyr_z, &(data->fifo[i]),
-				      gyr_shift);
-		i += 2;
-	}
-
-	if (frame->type & BMI_EMUL_FRAME_ACC) {
-		bmi_emul_set_data_reg(emul, frame->acc_x, &(data->fifo[i]),
-				      acc_shift);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->acc_y, &(data->fifo[i]),
-				      acc_shift);
-		i += 2;
-		bmi_emul_set_data_reg(emul, frame->acc_z, &(data->fifo[i]),
-				      acc_shift);
-		i += 2;
-	}
-}
-
-/**
- * @brief Update internal sensors offset values using values from emulated
- *        registers.
- *
- * @param emul Pointer to BMI emulator
- */
-static void bmi_emul_updata_int_off(struct i2c_emul *emul)
-{
-	struct bmi_emul_data *data;
-	uint16_t gyr_nvm;
-	uint8_t gyr98;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	data->off_acc_x = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg]);
-	data->off_acc_y = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg + 1]);
-	data->off_acc_z = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg + 2]);
-
-	gyr98 = data->reg[data->type_data->gyr98_off_reg];
-
-	gyr_nvm = data->reg[data->type_data->gyr_off_reg];
-	gyr_nvm |= (gyr98 & 0x3) << 8;
-	data->off_gyr_x = bmi_emul_gyr_nvm_to_off(gyr_nvm);
-	gyr_nvm = data->reg[data->type_data->gyr_off_reg + 1];
-	gyr_nvm |= (gyr98 & 0xc) << 6;
-	data->off_gyr_y = bmi_emul_gyr_nvm_to_off(gyr_nvm);
-	gyr_nvm = data->reg[data->type_data->gyr_off_reg + 2];
-	gyr_nvm |= (gyr98 & 0x30) << 4;
-	data->off_gyr_z = bmi_emul_gyr_nvm_to_off(gyr_nvm);
-}
-
-/**
- * @brief Restore registers backed in NVM to emulator's registers. Each model
- *        of BMI may have different set of NVM backed registers.
- *
- * @param emul Pointer to BMI emulator
- */
-static void bmi_emul_restore_nvm(struct i2c_emul *emul)
-{
-	struct bmi_emul_data *data;
-	int i;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	ASSERT(data->type_data->nvm_len <= BMI_EMUL_MAX_NVM_REGS);
-
-	/* Restore registers values */
-	for (i = 0; i < data->type_data->nvm_len; i++) {
-		data->reg[data->type_data->nvm_reg[i]] = data->nvm[i];
-	}
-
-	bmi_emul_updata_int_off(emul);
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_flush_fifo(struct i2c_emul *emul, bool tag_time, bool header)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	data->fifo_skip = 0;
-	data->fifo_frame = NULL;
-	/*
-	 * Gyroscope and accelerometer shift (last two arguments)
-	 * are not important for NULL (empty) FIFO frame.
-	 */
-	bmi_emul_set_current_frame(emul, NULL, tag_time, header, 0, 0);
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	/* Restore registers backed in NVM */
-	bmi_emul_restore_nvm(emul);
-
-	/* Flush FIFO */
-	bmi_emul_flush_fifo(emul, tag_time, header);
-
-	/* Reset sensor timer */
-	data->zero_time = bmi_emul_get_sensortime();
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_set_cmd_end_time(struct i2c_emul *emul, int time)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	data->cmd_end_time = k_uptime_get_32() + time;
-}
-
-/** Check description in emul_bmi.h */
-bool bmi_emul_is_cmd_end(struct i2c_emul *emul)
-{
-	struct bmi_emul_data *data;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	/* We are simulating command execution time and it doesn't expired */
-	if (data->simulate_command_exec_time &&
-	    data->cmd_end_time > k_uptime_get_32()) {
-		return false;
-	}
-
-	return true;
-}
-
-/**
- * @brief Handle I2C write message. BMI model specific write function is called.
- *        It is checked if accessed register isn't RO and reserved bits are set
- *        to 0. Write set value of reg field of bmi emulator data ignoring
- *        reserved bits. If required internal sensor offset values are updated.
- *
- * @param emul Pointer to BMI emulator
- * @param reg Register which is written
- * @param val Value being written to @p reg
- * @param byte Number of handled bytes in this write command
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bmi_emul_handle_write(struct i2c_emul *emul, int reg, uint8_t val,
-				 int byte)
-{
-	struct bmi_emul_data *data;
-	uint8_t rsvd_mask;
-	int ret;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	ret = data->type_data->handle_write(data->reg, emul, reg, byte, val);
-	reg = data->type_data->access_reg(emul, reg, byte, false /* = read */);
-	if (ret != 0) {
-		if (ret == BMI_EMUL_ACCESS_E) {
-			if (!data->error_on_ro_write) {
-				return 0;
-			}
-			LOG_ERR("Writing to reg 0x%x which is RO", reg);
-		}
-
-		return -EIO;
-	}
-
-	rsvd_mask = data->type_data->rsvd_mask[reg];
-
-	if (data->error_on_rsvd_write && rsvd_mask & val) {
-		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
-			val, reg, rsvd_mask);
-		return -EIO;
-	}
-
-	/* Ignore all reserved bits */
-	val &= ~rsvd_mask;
-	val |= data->reg[reg] & rsvd_mask;
-
-	data->reg[reg] = val;
-
-	if ((reg >= data->type_data->acc_off_reg &&
-	     reg <= data->type_data->acc_off_reg + 2) ||
-	    (reg >= data->type_data->gyr_off_reg &&
-	     reg <= data->type_data->gyr_off_reg + 2) ||
-	    reg == data->type_data->gyr98_off_reg) {
-		/*
-		 * Internal offset value should be updated to new value of
-		 * offset registers
-		 */
-		bmi_emul_updata_int_off(emul);
-	}
-
-	return 0;
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift,
-			   int gyr_shift, int acc_reg, int gyr_reg,
-			   int sensortime_reg, bool acc_off_en,
-			   bool gyr_off_en)
-{
-	struct bmi_emul_data *data;
-	int32_t val[3];
-	int i;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	if (gyr_off_en) {
-		val[0] = data->gyr_x - data->off_gyr_x;
-		val[1] = data->gyr_y - data->off_gyr_y;
-		val[2] = data->gyr_z - data->off_gyr_z;
-	} else {
-		val[0] = data->gyr_x;
-		val[1] = data->gyr_y;
-		val[2] = data->gyr_z;
-	}
-
-	for (i = 0; i < 3; i++) {
-		bmi_emul_set_data_reg(emul, val[i],
-				      &(data->reg[gyr_reg + i * 2]), gyr_shift);
-	}
-
-	if (acc_off_en) {
-		val[0] = data->acc_x - data->off_acc_x;
-		val[1] = data->acc_y - data->off_acc_y;
-		val[2] = data->acc_z - data->off_acc_z;
-	} else {
-		val[0] = data->acc_x;
-		val[1] = data->acc_y;
-		val[2] = data->acc_z;
-	}
-
-	for (i = 0; i < 3; i++) {
-		bmi_emul_set_data_reg(emul, val[i],
-				      &(data->reg[acc_reg + i * 2]), acc_shift);
-	}
-
-	bmi_emul_set_sensortime_reg(emul, &(data->reg[sensortime_reg]));
-}
-
-/** Check description in emul_bmi.h */
-void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame)
-{
-	struct bmi_emul_data *data;
-	struct bmi_emul_frame *tmp_frame;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	if (data->fifo_frame == NULL) {
-		data->fifo_frame = frame;
-	} else {
-		tmp_frame = data->fifo_frame;
-		while (tmp_frame->next != NULL) {
-			tmp_frame = tmp_frame->next;
-		}
-		tmp_frame->next = frame;
-	}
-}
-
-/** Check description in emul_bmi.h */
-uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header)
-{
-	struct bmi_emul_frame *frame;
-	struct bmi_emul_data *data;
-	uint16_t len = 0;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	if (data->fifo_skip != 0 && header) {
-		len += 2;
-	}
-
-	frame = data->fifo_frame;
-	while (frame != NULL) {
-		len += bmi_emul_get_frame_len(emul, frame, tag_time, header);
-		frame = frame->next;
-	}
-
-	len += bmi_emul_get_frame_len(emul, NULL, tag_time, header);
-	/* Do not count last empty frame byte */
-	len--;
-
-	return len;
-}
-
-/** Check description in emul_bmi.h */
-uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
-			       bool tag_time, bool header, int acc_shift,
-			       int gyr_shift)
-{
-	struct bmi_emul_data *data;
-	int ret;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	if (byte == 0) {
-		/* Repeat uncompleated read of frame */
-		bmi_emul_set_current_frame(emul, data->fifo_frame, tag_time,
-					   header, acc_shift, gyr_shift);
-
-		/* Return header for skip frame */
-		if (data->fifo_skip != 0 && header) {
-			return BMI_EMUL_FIFO_HEAD_SKIP;
-		}
-	}
-
-	if (data->fifo_skip != 0 && byte == 1 && header) {
-		/* Return number of skipped frames */
-		ret = data->fifo_skip;
-		data->fifo_skip = 0;
-
-		return ret;
-	}
-
-	/* Get next valid frame */
-	while (data->fifo_frame_byte >= data->fifo_frame_len) {
-		/* No data */
-		if (data->fifo_frame == NULL) {
-			return 0;
-		}
-		data->fifo_frame = data->fifo_frame->next;
-		bmi_emul_set_current_frame(emul, data->fifo_frame, tag_time,
-					   header, acc_shift, gyr_shift);
-	}
-
-	return data->fifo[data->fifo_frame_byte++];
-}
-
-/**
- * @brief Handle I2C read message. BMI model specific read function is called.
- *        It is checked if accessed register isn't WO.
- *
- * @param emul Pointer to BMI emulator
- * @param reg Register address to read
- * @param buf Pointer where result should be stored
- * @param byte Byte which is accessed during block read
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int bmi_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
-				int byte)
-{
-	struct bmi_emul_data *data;
-	int ret;
-
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
-
-	ret = data->type_data->handle_read(data->reg, emul, reg, byte, buf);
-	reg = data->type_data->access_reg(emul, reg, byte, true /* = read */);
-	if (ret == BMI_EMUL_ACCESS_E && data->error_on_wo_read) {
-		LOG_ERR("Reading reg 0x%x which is WO", reg);
-	} else if (ret != 0) {
-		return ret;
-	}
-
-	return 0;
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api bmi_emul_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-/**
- * @brief Set up a new BMI emulator
- *
- * This should be called for each BMI device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int bmi_emul_init(const struct emul *emul,
-			 const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	struct bmi_emul_data *bmi_data;
-	int ret;
-
-	data->emul.api = &bmi_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	bmi_data = CONTAINER_OF(data, struct bmi_emul_data, common);
-
-	switch (bmi_data->type) {
-	case BMI_EMUL_160:
-		bmi_data->type_data = get_bmi160_emul_type_data();
-		break;
-	case BMI_EMUL_260:
-		bmi_data->type_data = get_bmi260_emul_type_data();
-		break;
-	}
-
-	/* Set callback access_reg to type specific function */
-	data->access_reg = bmi_data->type_data->access_reg;
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	bmi_data->type_data->reset(bmi_data->reg, &data->emul);
-
-	return ret;
-}
-
-#define BMI_EMUL(n)							\
-	static struct bmi_emul_data bmi_emul_data_##n = {		\
-		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
-		.error_on_wo_read = DT_INST_PROP(n, error_on_wo_read),	\
-		.error_on_rsvd_write = DT_INST_PROP(n,			\
-					error_on_reserved_bit_write),	\
-		.simulate_command_exec_time = DT_INST_PROP(n,		\
-					simulate_command_exec_time),	\
-		.type = DT_STRING_TOKEN(DT_DRV_INST(n), device_model),	\
-		.common = {						\
-			.start_write = NULL,				\
-			.write_byte = bmi_emul_handle_write,		\
-			.finish_write = NULL,				\
-			.start_read = NULL,				\
-			.read_byte = bmi_emul_handle_read,		\
-			.finish_read = NULL,				\
-			.access_reg = NULL,				\
-		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bmi_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bmi_emul_init, DT_DRV_INST(n), &bmi_emul_cfg_##n,	\
-		    &bmi_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL)
-
-#define BMI_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bmi_emul_data_##n.common.emul;
-
-/** Check description in emul_bmi.h */
-struct i2c_emul *bmi_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_bmi160.c b/zephyr/emul/emul_bmi160.c
deleted file mode 100644
index 2a68b688ff..0000000000
--- a/zephyr/emul/emul_bmi160.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_bmi
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_bmi160);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_bmi.h"
-
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi_common.h"
-
-/** Mask reserved bits in each register of BMI160 */
-static const uint8_t bmi_emul_160_rsvd_mask[] = {
-	[BMI160_CHIP_ID]		= 0x00,
-	[0x01]				= 0xff, /* Reserved */
-	[BMI160_ERR_REG]		= 0x00,
-	[BMI160_PMU_STATUS]		= 0xc0,
-	[BMI160_MAG_X_L_G]		= 0x00,
-	[BMI160_MAG_X_H_G]		= 0x00,
-	[BMI160_MAG_Y_L_G]		= 0x00,
-	[BMI160_MAG_Y_H_G]		= 0x00,
-	[BMI160_MAG_Z_L_G]		= 0x00,
-	[BMI160_MAG_Z_H_G]		= 0x00,
-	[BMI160_RHALL_L_G]		= 0x00,
-	[BMI160_RHALL_H_G]		= 0x00,
-	[BMI160_GYR_X_L_G]		= 0x00,
-	[BMI160_GYR_X_H_G]		= 0x00,
-	[BMI160_GYR_Y_L_G]		= 0x00,
-	[BMI160_GYR_Y_H_G]		= 0x00,
-	[BMI160_GYR_Z_L_G]		= 0x00,
-	[BMI160_GYR_Z_H_G]		= 0x00,
-	[BMI160_ACC_X_L_G]		= 0x00,
-	[BMI160_ACC_X_H_G]		= 0x00,
-	[BMI160_ACC_Y_L_G]		= 0x00,
-	[BMI160_ACC_Y_H_G]		= 0x00,
-	[BMI160_ACC_Z_L_G]		= 0x00,
-	[BMI160_ACC_Z_H_G]		= 0x00,
-	[BMI160_SENSORTIME_0]		= 0x00,
-	[BMI160_SENSORTIME_1]		= 0x00,
-	[BMI160_SENSORTIME_2]		= 0x00,
-	[BMI160_STATUS]			= 0x01,
-	[BMI160_INT_STATUS_0]		= 0x00,
-	[BMI160_INT_STATUS_1]		= 0x03,
-	[BMI160_INT_STATUS_2]		= 0x00,
-	[BMI160_INT_STATUS_3]		= 0x00,
-	[BMI160_TEMPERATURE_0]		= 0x00,
-	[BMI160_TEMPERATURE_1]		= 0x00,
-	[BMI160_FIFO_LENGTH_0]		= 0x00,
-	[BMI160_FIFO_LENGTH_1]		= 0xf8,
-	[BMI160_FIFO_DATA]		= 0x00,
-	[0x25 ... 0x3f]			= 0xff, /* Reserved */
-	[BMI160_ACC_CONF]		= 0x00,
-	[BMI160_ACC_RANGE]		= 0xf0,
-	[BMI160_GYR_CONF]		= 0xc0,
-	[BMI160_GYR_RANGE]		= 0xf8,
-	[BMI160_MAG_CONF]		= 0xf0,
-	[BMI160_FIFO_DOWNS]		= 0x00,
-	[BMI160_FIFO_CONFIG_0]		= 0x00,
-	[BMI160_FIFO_CONFIG_1]		= 0x01,
-	[0x48 ... 0x4a]			= 0xff, /* Reserved */
-	[BMI160_MAG_IF_0]		= 0x01,
-	[BMI160_MAG_IF_1]		= 0x40,
-	[BMI160_MAG_IF_2]		= 0x00,
-	[BMI160_MAG_IF_3]		= 0x00,
-	[BMI160_MAG_IF_4]		= 0x00,
-	[BMI160_INT_EN_0]		= 0x08,
-	[BMI160_INT_EN_1]		= 0x80,
-	[BMI160_INT_EN_2]		= 0xf0,
-	[BMI160_INT_OUT_CTRL]		= 0x00,
-	[BMI160_INT_LATCH]		= 0xc0,
-	[BMI160_INT_MAP_0]		= 0x00,
-	[BMI160_INT_MAP_1]		= 0x00,
-	[BMI160_INT_MAP_2]		= 0x00,
-	[BMI160_INT_DATA_0]		= 0x77,
-	[BMI160_INT_DATA_1]		= 0x7f,
-	[BMI160_INT_LOW_HIGH_0]		= 0x00,
-	[BMI160_INT_LOW_HIGH_1]		= 0x00,
-	[BMI160_INT_LOW_HIGH_2]		= 0x3c,
-	[BMI160_INT_LOW_HIGH_3]		= 0x00,
-	[BMI160_INT_LOW_HIGH_4]		= 0x00,
-	[BMI160_INT_MOTION_0]		= 0x00,
-	[BMI160_INT_MOTION_1]		= 0x00,
-	[BMI160_INT_MOTION_2]		= 0x00,
-	[BMI160_INT_MOTION_3]		= 0xc0,
-	[BMI160_INT_TAP_0]		= 0x38,
-	[BMI160_INT_TAP_1]		= 0xe0,
-	[BMI160_INT_ORIENT_0]		= 0x00,
-	[BMI160_INT_ORIENT_1]		= 0x00,
-	[BMI160_INT_FLAT_0]		= 0xc0,
-	[BMI160_INT_FLAT_1]		= 0xc8,
-	[BMI160_FOC_CONF]		= 0x80,
-	[BMI160_CONF]			= 0xfd,
-	[BMI160_IF_CONF]		= 0xce,
-	[BMI160_PMU_TRIGGER]		= 0x80,
-	[BMI160_SELF_TEST]		= 0xe0,
-	[0x6e]				= 0xff, /* Reserved */
-	[0x6f]				= 0xff, /* Reserved */
-	[BMI160_NV_CONF]		= 0xf0,
-	[BMI160_OFFSET_ACC70]		= 0x00,
-	[BMI160_OFFSET_ACC70 + 1]	= 0x00,
-	[BMI160_OFFSET_ACC70 + 2]	= 0x00,
-	[BMI160_OFFSET_GYR70]		= 0x00,
-	[BMI160_OFFSET_GYR70 + 1]	= 0x00,
-	[BMI160_OFFSET_GYR70 + 2]	= 0x00,
-	[BMI160_OFFSET_EN_GYR98]	= 0x00,
-	[BMI160_STEP_CNT_0]		= 0x00,
-	[BMI160_STEP_CNT_1]		= 0x00,
-	[BMI160_STEP_CONF_0]		= 0x00,
-	[BMI160_STEP_CONF_1]		= 0xf0,
-	[0x7c]				= 0xff, /* Reserved */
-	[0x7d]				= 0xff, /* Reserved */
-	[BMI160_CMD_REG]		= 0x00,
-};
-
-/**
- * @brief Convert range in format of ACC_RANGE register to number of bits
- *        that should be shifted right to obtain 16 bit reported accelerometer
- *        value from internal 32 bit value
- *
- * @param range Value of ACC_RANGE register
- *
- * @return shift Number of LSB that should be ignored from internal
- *               accelerometer value
- */
-static int bmi160_emul_acc_range_to_shift(uint8_t range)
-{
-	switch (range & 0xf) {
-	case BMI160_GSEL_2G:
-		return 0;
-	case BMI160_GSEL_4G:
-		return 1;
-	case BMI160_GSEL_8G:
-		return 2;
-	case BMI160_GSEL_16G:
-		return 3;
-	default:
-		return 0;
-	}
-}
-
-/**
- * @brief Convert range in format of GYR_RANGE register to number of bits
- *        that should be shifted right to obtain 16 bit reported gyroscope
- *        value from internal 32 bit value
- *
- * @param range Value of GYR_RANGE register
- *
- * @return shift Number of LSB that should be ignored from internal
- *               gyroscope value
- */
-static int bmi160_emul_gyr_range_to_shift(uint8_t range)
-{
-	switch (range & 0x7) {
-	case BMI160_DPS_SEL_2000:
-		return 4;
-	case BMI160_DPS_SEL_1000:
-		return 3;
-	case BMI160_DPS_SEL_500:
-		return 2;
-	case BMI160_DPS_SEL_250:
-		return 1;
-	case BMI160_DPS_SEL_125:
-		return 0;
-	default:
-		return 0;
-	}
-}
-
-/**
- * @brief Reset registers to default values and restore registers backed by NVM
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- */
-static void bmi160_emul_reset(uint8_t *regs, struct i2c_emul *emul)
-{
-	bool tag_time;
-	bool header;
-
-	regs[BMI160_CHIP_ID]		= 0xd1;
-	regs[BMI160_ERR_REG]		= 0x00;
-	regs[BMI160_PMU_STATUS]		= 0x00;
-	regs[BMI160_MAG_X_L_G]		= 0x00;
-	regs[BMI160_MAG_X_H_G]		= 0x00;
-	regs[BMI160_MAG_Y_L_G]		= 0x00;
-	regs[BMI160_MAG_Y_H_G]		= 0x00;
-	regs[BMI160_MAG_Z_L_G]		= 0x00;
-	regs[BMI160_MAG_Z_H_G]		= 0x00;
-	regs[BMI160_RHALL_L_G]		= 0x00;
-	regs[BMI160_RHALL_H_G]		= 0x00;
-	regs[BMI160_GYR_X_L_G]		= 0x00;
-	regs[BMI160_GYR_X_H_G]		= 0x00;
-	regs[BMI160_GYR_Y_L_G]		= 0x00;
-	regs[BMI160_GYR_Y_H_G]		= 0x00;
-	regs[BMI160_GYR_Z_L_G]		= 0x00;
-	regs[BMI160_GYR_Z_H_G]		= 0x00;
-	regs[BMI160_ACC_X_L_G]		= 0x00;
-	regs[BMI160_ACC_X_H_G]		= 0x00;
-	regs[BMI160_ACC_Y_L_G]		= 0x00;
-	regs[BMI160_ACC_Y_H_G]		= 0x00;
-	regs[BMI160_ACC_Z_L_G]		= 0x00;
-	regs[BMI160_ACC_Z_H_G]		= 0x00;
-	regs[BMI160_SENSORTIME_0]	= 0x00;
-	regs[BMI160_SENSORTIME_1]	= 0x00;
-	regs[BMI160_SENSORTIME_2]	= 0x00;
-	regs[BMI160_STATUS]		= 0x01;
-	regs[BMI160_INT_STATUS_0]	= 0x00;
-	regs[BMI160_INT_STATUS_1]	= 0x00;
-	regs[BMI160_INT_STATUS_2]	= 0x00;
-	regs[BMI160_INT_STATUS_3]	= 0x00;
-	regs[BMI160_TEMPERATURE_0]	= 0x00;
-	regs[BMI160_TEMPERATURE_1]	= 0x00;
-	regs[BMI160_FIFO_LENGTH_0]	= 0x00;
-	regs[BMI160_FIFO_LENGTH_1]	= 0x00;
-	regs[BMI160_FIFO_DATA]		= 0x00;
-	regs[BMI160_ACC_CONF]		= 0x28;
-	regs[BMI160_ACC_RANGE]		= 0x03;
-	regs[BMI160_GYR_CONF]		= 0x28;
-	regs[BMI160_GYR_RANGE]		= 0x00;
-	regs[BMI160_MAG_CONF]		= 0x0b;
-	regs[BMI160_FIFO_DOWNS]		= 0x88;
-	regs[BMI160_FIFO_CONFIG_0]	= 0x80;
-	regs[BMI160_FIFO_CONFIG_1]	= 0x10;
-	regs[BMI160_MAG_IF_0]		= 0x20;
-	regs[BMI160_MAG_IF_1]		= 0x80;
-	regs[BMI160_MAG_IF_2]		= 0x42;
-	regs[BMI160_MAG_IF_3]		= 0x4c;
-	regs[BMI160_MAG_IF_4]		= 0x00;
-	regs[BMI160_INT_EN_0]		= 0x00;
-	regs[BMI160_INT_EN_1]		= 0x00;
-	regs[BMI160_INT_EN_2]		= 0x00;
-	regs[BMI160_INT_OUT_CTRL]	= 0x00;
-	regs[BMI160_INT_LATCH]		= 0x00;
-	regs[BMI160_INT_MAP_0]		= 0x00;
-	regs[BMI160_INT_MAP_1]		= 0x00;
-	regs[BMI160_INT_MAP_2]		= 0x00;
-	regs[BMI160_INT_DATA_0]		= 0x00;
-	regs[BMI160_INT_DATA_1]		= 0x00;
-	regs[BMI160_INT_LOW_HIGH_0]	= 0x07;
-	regs[BMI160_INT_LOW_HIGH_1]	= 0x30;
-	regs[BMI160_INT_LOW_HIGH_2]	= 0x81;
-	regs[BMI160_INT_LOW_HIGH_3]	= 0xdb;
-	regs[BMI160_INT_LOW_HIGH_4]	= 0xc0;
-	regs[BMI160_INT_MOTION_0]	= 0x00;
-	regs[BMI160_INT_MOTION_1]	= 0x14;
-	regs[BMI160_INT_MOTION_2]	= 0x14;
-	regs[BMI160_INT_MOTION_3]	= 0x24;
-	regs[BMI160_INT_TAP_0]		= 0x04;
-	regs[BMI160_INT_TAP_1]		= 0xda;
-	regs[BMI160_INT_ORIENT_0]	= 0x18;
-	regs[BMI160_INT_ORIENT_1]	= 0x48;
-	regs[BMI160_INT_FLAT_0]		= 0x08;
-	regs[BMI160_INT_FLAT_1]		= 0x11;
-	regs[BMI160_FOC_CONF]		= 0x00;
-	regs[BMI160_CONF]		= 0x00;
-	regs[BMI160_IF_CONF]		= 0x00;
-	regs[BMI160_PMU_TRIGGER]	= 0x00;
-	regs[BMI160_SELF_TEST]		= 0x00;
-	regs[BMI160_STEP_CNT_0]		= 0x00;
-	regs[BMI160_STEP_CNT_1]		= 0x00;
-	regs[BMI160_STEP_CONF_0]	= 0x00;
-	regs[BMI160_STEP_CONF_1]	= 0x15;
-	regs[BMI160_CMD_REG]		= 0x03;
-
-	/* Call generic reset */
-	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
-	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
-	bmi_emul_reset_common(emul, tag_time, header);
-}
-
-/**
- * @brief Clear all interrupt registers
- *
- * @param regs Pointer to array of emulator's registers
- */
-static void bmi160_emul_clear_int(uint8_t *regs)
-{
-	regs[BMI160_INT_STATUS_0] = 0x00;
-	regs[BMI160_INT_STATUS_1] = 0x00;
-	regs[BMI160_INT_STATUS_2] = 0x00;
-	regs[BMI160_INT_STATUS_3] = 0x00;
-}
-
-/**
- * @brief Get offset value for given gyroscope value. If gyroscope value is
- *        above maximum (belowe minimum), then minimum -31,25°/s
- *        (maximum 31,25°/s) offset value is returned.
- *
- * @param gyr Gyroscope value
- */
-static int16_t bmi160_emul_get_gyr_target_off(int32_t gyr)
-{
-	if (gyr > (int32_t)BMI_EMUL_125_DEG_S / 4) {
-		return -((int32_t)BMI_EMUL_125_DEG_S / 4);
-	}
-
-	if (gyr < -((int32_t)BMI_EMUL_125_DEG_S / 4)) {
-		return BMI_EMUL_125_DEG_S / 4;
-	}
-
-	return -gyr;
-}
-
-/**
- * @brief Get offset value for given accelerometer value. If accelerometer
- *        value - target is above maximum (belowe minimum), then minimum -0.5g
- *        (maximum 0.5g) offset value is returned.
- *
- * @param acc Accelerometer value
- * @param target Target value in FOC configuration register format
- */
-static int16_t bmi160_emul_get_acc_target_off(int32_t acc, uint8_t target)
-{
-	switch (target) {
-	case BMI160_FOC_ACC_PLUS_1G:
-		acc -= BMI_EMUL_1G;
-		break;
-	case BMI160_FOC_ACC_MINUS_1G:
-		acc += BMI_EMUL_1G;
-		break;
-	}
-
-	if (acc > (int32_t)BMI_EMUL_1G / 2) {
-		return -((int32_t)BMI_EMUL_1G / 2);
-	}
-
-	if (acc < -((int32_t)BMI_EMUL_1G / 2)) {
-		return BMI_EMUL_1G / 2;
-	}
-
-	return -acc;
-}
-
-/**
- * @brief Handle fast offset compensation. Check FOC configuration register
- *        and sets gyroscope and/or accelerometer offset using current emulator
- *        state.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- */
-static void bmi160_emul_handle_off_comp(uint8_t *regs, struct i2c_emul *emul)
-{
-	uint8_t target;
-	int16_t off;
-	int32_t val;
-
-	if (regs[BMI160_FOC_CONF] & BMI160_FOC_GYRO_EN) {
-		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_X);
-		off = bmi160_emul_get_gyr_target_off(val);
-		bmi_emul_set_off(emul, BMI_EMUL_GYR_X, off);
-		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Y);
-		off = bmi160_emul_get_gyr_target_off(val);
-		bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, off);
-		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Z);
-		off = bmi160_emul_get_gyr_target_off(val);
-		bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, off);
-	}
-
-	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_X_OFFSET) & 0x3;
-	if (target) {
-		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_X);
-		off = bmi160_emul_get_acc_target_off(val, target);
-		bmi_emul_set_off(emul, BMI_EMUL_ACC_X, off);
-	}
-
-	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_Y_OFFSET) & 0x3;
-	if (target) {
-		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_Y);
-		off = bmi160_emul_get_acc_target_off(val, target);
-		bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, off);
-	}
-
-	target = (regs[BMI160_FOC_CONF] >> BMI160_FOC_ACC_Z_OFFSET) & 0x3;
-	if (target) {
-		val = bmi_emul_get_value(emul, BMI_EMUL_ACC_Z);
-		off = bmi160_emul_get_acc_target_off(val, target);
-		bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, off);
-	}
-}
-
-/**
- * @brief Execute first part of command. Emulate state of device which is
- *        during handling command (status bits etc). This function save time
- *        on which command should end.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param cmd Command that is starting
- *
- * @return 0 on success
- * @return -EIO on failure
- */
-static int bmi160_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
-{
-	int time;
-
-	switch (cmd) {
-	case BMI160_CMD_SOFT_RESET:
-		time = 1;
-		break;
-	case BMI160_CMD_START_FOC:
-		if ((regs[BMI160_FOC_CONF] & BMI160_FOC_GYRO_EN) &&
-		    ((regs[BMI160_PMU_STATUS] &
-		      (0x3 << BMI160_PMU_GYR_OFFSET)) !=
-		     BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET)) {
-			LOG_ERR("Starting gyroscope FOC in low power mode");
-			return -EIO;
-		}
-
-		if ((regs[BMI160_FOC_CONF] & ~BMI160_FOC_GYRO_EN) &&
-		    ((regs[BMI160_PMU_STATUS] &
-		      (0x3 << BMI160_PMU_ACC_OFFSET)) !=
-		     BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET)) {
-			LOG_ERR("Starting accelerometer FOC in low power mode");
-			return -EIO;
-		}
-
-		regs[BMI160_STATUS] &= ~BMI160_FOC_RDY;
-		time = 250;
-		break;
-	case BMI160_CMD_ACC_MODE_SUSP:
-	case BMI160_CMD_GYR_MODE_SUSP:
-	case BMI160_CMD_MAG_MODE_SUSP:
-		time = 0;
-		break;
-	/* Real hardware probably switch faster if not in suspend mode */
-	case BMI160_CMD_ACC_MODE_NORMAL:
-	case BMI160_CMD_ACC_MODE_LOWPOWER:
-		time = 4;
-		break;
-	case BMI160_CMD_GYR_MODE_NORMAL:
-	case BMI160_CMD_GYR_MODE_FAST_STARTUP:
-		time = 80;
-		break;
-	case BMI160_CMD_MAG_MODE_NORMAL:
-	case BMI160_CMD_MAG_MODE_LOWPOWER:
-		time = 1;
-		break;
-	case BMI160_CMD_FIFO_FLUSH:
-		time = 0;
-		break;
-	case BMI160_CMD_INT_RESET:
-		time = 0;
-		break;
-	default:
-		LOG_ERR("Unknown command 0x%x", cmd);
-		return -EIO;
-	}
-
-	regs[BMI160_CMD_REG] = cmd;
-	bmi_emul_set_cmd_end_time(emul, time);
-
-	return 0;
-}
-
-/**
- * @brief Emulate end of ongoing command.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- */
-static void bmi160_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
-{
-	uint8_t pmu_status;
-	bool tag_time;
-	bool header;
-	int cmd;
-
-	pmu_status = regs[BMI160_PMU_STATUS];
-	cmd = regs[BMI160_CMD_REG];
-	regs[BMI160_CMD_REG] = BMI160_CMD_NOOP;
-	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
-	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
-
-	switch (cmd) {
-	case BMI160_CMD_SOFT_RESET:
-		bmi160_emul_reset(regs, emul);
-		break;
-	case BMI160_CMD_START_FOC:
-		bmi160_emul_handle_off_comp(regs, emul);
-		regs[BMI160_STATUS] |= BMI160_FOC_RDY;
-		break;
-	case BMI160_CMD_ACC_MODE_SUSP:
-		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
-		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_ACC_OFFSET;
-		break;
-	case BMI160_CMD_ACC_MODE_NORMAL:
-		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
-		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
-		break;
-	case BMI160_CMD_ACC_MODE_LOWPOWER:
-		pmu_status &= ~(0x3 << BMI160_PMU_ACC_OFFSET);
-		pmu_status |= BMI160_PMU_LOW_POWER << BMI160_PMU_ACC_OFFSET;
-		break;
-	case BMI160_CMD_GYR_MODE_SUSP:
-		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
-		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_GYR_OFFSET;
-		break;
-	case BMI160_CMD_GYR_MODE_NORMAL:
-		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
-		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
-		break;
-	case BMI160_CMD_GYR_MODE_FAST_STARTUP:
-		pmu_status &= ~(0x3 << BMI160_PMU_GYR_OFFSET);
-		pmu_status |= BMI160_PMU_FAST_STARTUP << BMI160_PMU_GYR_OFFSET;
-		break;
-	case BMI160_CMD_MAG_MODE_SUSP:
-		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
-		pmu_status |= BMI160_PMU_SUSPEND << BMI160_PMU_MAG_OFFSET;
-		break;
-	case BMI160_CMD_MAG_MODE_NORMAL:
-		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
-		pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_MAG_OFFSET;
-		break;
-	case BMI160_CMD_MAG_MODE_LOWPOWER:
-		pmu_status &= ~(0x3 << BMI160_PMU_MAG_OFFSET);
-		pmu_status |= BMI160_PMU_LOW_POWER << BMI160_PMU_MAG_OFFSET;
-		break;
-	case BMI160_CMD_FIFO_FLUSH:
-		bmi_emul_flush_fifo(emul, tag_time, header);
-		break;
-	case BMI160_CMD_INT_RESET:
-		bmi160_emul_clear_int(regs);
-		break;
-	}
-
-	/* Clear FIFO on sensor on/off in headerless mode */
-	if (pmu_status != regs[BMI160_PMU_STATUS] && !header) {
-		bmi_emul_flush_fifo(emul, tag_time, header);
-	}
-
-	regs[BMI160_PMU_STATUS] = pmu_status;
-}
-
-/**
- * @brief BMI160 specific write function. It doesn't handle block writes.
- *        Check if read only register is not accessed. Before writing value,
- *        ongoing command is finished if possible. Write to CMD register is
- *        handled by BMI160 specific function. On changing of FIFO
- *        header/headerless mode, FIFO is flushed.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param reg Register address that is accessed
- * @param byte Number of handled bytes in this write command
- * @param val Value that is being written
- *
- * @return 0 on success
- * @return BMI_EMUL_ACCESS_E on RO register access
- * @return -EIO on error
- */
-static int bmi160_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
-				    int reg, int byte, uint8_t val)
-{
-	bool tag_time;
-	bool header;
-
-	if (byte > 1) {
-		LOG_ERR("Block writes are not allowed");
-		return -EIO;
-	}
-
-	if (reg <= BMI160_FIFO_DATA ||
-	    (reg >= BMI160_STEP_CNT_0 && reg <= BMI160_STEP_CNT_1)) {
-		return BMI_EMUL_ACCESS_E;
-	}
-
-	/* Stop on going command if required */
-	if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP &&
-	    bmi_emul_is_cmd_end(emul)) {
-		bmi160_emul_end_cmd(regs, emul);
-	}
-
-	switch (reg) {
-	case BMI160_CMD_REG:
-		if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP) {
-			LOG_ERR("Issued command before previous end");
-			return -EIO;
-		}
-
-		return bmi160_emul_start_cmd(regs, emul, val);
-	case BMI160_FIFO_CONFIG_1:
-		tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
-		header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
-		/*
-		 * Clear FIFO on transition between headerless and
-		 * header mode
-		 */
-		if (!!(val & BMI160_FIFO_HEADER_EN) != header) {
-			bmi_emul_flush_fifo(emul, tag_time, header);
-		}
-		break;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Get currently accessed register. It is first register plus number of
- *        handled bytes for all registers except BMI160_FIFO_DATA for which
- *        address incrementation is disabled.
- *
- * @param emul Pointer to BMI emulator
- * @param reg First byte of last write message
- * @param bytes Number of bytes already handled from current message
- * @param read If currently handled is read message
- *
- * @return Currently accessed register
- */
-static int bmi160_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
-				  bool read)
-{
-	if (!read) {
-		return reg;
-	}
-
-	/*
-	 * If register is FIFO data, then read data from FIFO.
-	 * Else block read access subsequent registers.
-	 */
-	if (reg <= BMI160_FIFO_DATA && reg + byte >= BMI160_FIFO_DATA) {
-		return BMI160_FIFO_DATA;
-	}
-
-	return reg + byte;
-}
-
-/**
- * @brief BMI160 specific read function. It handle block reads but only if
- *        device is not suspended. FIFO data register is trap register, so
- *        after reaching it, register address is not increased on block reads.
- *        Before reading value, ongoing command is finished if possible.
- *        Read of sensor data traps current emulator state in registers.
- *        Read of FIFO length and FIFO data triggers default BMI functions.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param reg Register address that is accessed
- * @param byte Byte which is accessed during block read
- * @param buf Pointer where read byte should be stored
- *
- * @return 0 on success
- * @return BMI_EMUL_ACCESS_E on WO register access
- * @return -EIO on other error
- */
-static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
-				   int reg, int byte, char *buf)
-{
-	uint16_t fifo_len;
-	bool acc_off_en;
-	bool gyr_off_en;
-	bool tag_time;
-	bool header;
-	int gyr_shift;
-	int acc_shift;
-	int fifo_byte;
-
-	/* Get number of bytes readed from FIFO */
-	fifo_byte = byte - (reg - BMI160_FIFO_DATA);
-
-	reg = bmi160_emul_access_reg(emul, reg, byte, true /* = read */);
-
-	/* Stop on going command if required */
-	if (regs[BMI160_CMD_REG] != BMI160_CMD_NOOP &&
-	    bmi_emul_is_cmd_end(emul)) {
-		bmi160_emul_end_cmd(regs, emul);
-	}
-
-	/* Burst reads are not supported if all sensors are in suspend mode */
-	if ((regs[BMI160_PMU_STATUS] & 0x3f) == 0 && byte > 0) {
-		LOG_ERR("Block reads are not supported in suspend mode");
-		return -EIO;
-	}
-
-	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
-	header = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_HEADER_EN;
-	acc_off_en = regs[BMI160_OFFSET_EN_GYR98] & BMI160_OFFSET_ACC_EN;
-	gyr_off_en = regs[BMI160_OFFSET_EN_GYR98] & BMI160_OFFSET_GYRO_EN;
-	gyr_shift = bmi160_emul_gyr_range_to_shift(regs[BMI160_GYR_RANGE]);
-	acc_shift = bmi160_emul_acc_range_to_shift(regs[BMI160_ACC_RANGE]);
-
-	switch (reg) {
-	case BMI160_GYR_X_L_G:
-	case BMI160_GYR_X_H_G:
-	case BMI160_GYR_Y_L_G:
-	case BMI160_GYR_Y_H_G:
-	case BMI160_GYR_Z_L_G:
-	case BMI160_GYR_Z_H_G:
-	case BMI160_ACC_X_L_G:
-	case BMI160_ACC_X_H_G:
-	case BMI160_ACC_Y_L_G:
-	case BMI160_ACC_Y_H_G:
-	case BMI160_ACC_Z_L_G:
-	case BMI160_ACC_Z_H_G:
-	case BMI160_SENSORTIME_0:
-	case BMI160_SENSORTIME_1:
-	case BMI160_SENSORTIME_2:
-		/*
-		 * Snapshot of current emulator state is created on data read
-		 * and shouldn't be changed until next I2C operation
-		 */
-		if (byte == 0) {
-			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
-					      BMI160_ACC_X_L_G,
-					      BMI160_GYR_X_L_G,
-					      BMI160_SENSORTIME_0,
-					      acc_off_en, gyr_off_en);
-		}
-		break;
-	case BMI160_FIFO_LENGTH_0:
-	case BMI160_FIFO_LENGTH_1:
-		if (byte == 0) {
-			fifo_len = bmi_emul_fifo_len(emul, tag_time, header);
-			regs[BMI160_FIFO_LENGTH_0] = fifo_len & 0xff;
-			regs[BMI160_FIFO_LENGTH_1] = (fifo_len >> 8) & 0x7;
-		}
-		break;
-	case BMI160_FIFO_DATA:
-		regs[reg] = bmi_emul_get_fifo_data(emul, fifo_byte, tag_time,
-						   header, acc_shift,
-						   gyr_shift);
-		break;
-	}
-
-	*buf = regs[reg];
-
-	return 0;
-}
-
-/** Registers backed in NVM by BMI160 */
-const int bmi160_nvm_reg[] = {BMI160_NV_CONF,
-			      BMI160_OFFSET_ACC70,
-			      BMI160_OFFSET_ACC70 + 1,
-			      BMI160_OFFSET_ACC70 + 2,
-			      BMI160_OFFSET_GYR70,
-			      BMI160_OFFSET_GYR70 + 1,
-			      BMI160_OFFSET_GYR70 + 2,
-			      BMI160_OFFSET_EN_GYR98};
-
-/** Confguration of BMI160 */
-struct bmi_emul_type_data bmi160_emul = {
-	.sensortime_follow_config_frame = false,
-	.handle_write = bmi160_emul_handle_write,
-	.handle_read = bmi160_emul_handle_read,
-	.access_reg = bmi160_emul_access_reg,
-	.reset = bmi160_emul_reset,
-	.rsvd_mask = bmi_emul_160_rsvd_mask,
-	.nvm_reg = bmi160_nvm_reg,
-	.nvm_len = ARRAY_SIZE(bmi160_nvm_reg),
-	.gyr_off_reg = BMI160_OFFSET_GYR70,
-	.acc_off_reg = BMI160_OFFSET_ACC70,
-	.gyr98_off_reg = BMI160_OFFSET_EN_GYR98,
-};
-
-/** Check description in emul_bmi.h */
-const struct bmi_emul_type_data *get_bmi160_emul_type_data(void)
-{
-	return &bmi160_emul;
-}
diff --git a/zephyr/emul/emul_bmi260.c b/zephyr/emul/emul_bmi260.c
deleted file mode 100644
index 235b1e219e..0000000000
--- a/zephyr/emul/emul_bmi260.c
+++ /dev/null
@@ -1,571 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_bmi
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_bmi260);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_bmi.h"
-
-#include "driver/accelgyro_bmi260.h"
-#include "driver/accelgyro_bmi_common.h"
-
-/** Mask reserved bits in each register of BMI260 */
-static const uint8_t bmi_emul_260_rsvd_mask[] = {
-	[BMI260_CHIP_ID]		= 0x00,
-	[0x01]				= 0xff, /* Reserved */
-	[BMI260_ERR_REG]		= 0x20,
-	[BMI260_STATUS]			= 0x0b,
-	[BMI260_AUX_X_L_G]		= 0x00,
-	[BMI260_AUX_X_H_G]		= 0x00,
-	[BMI260_AUX_Y_L_G]		= 0x00,
-	[BMI260_AUX_Y_H_G]		= 0x00,
-	[BMI260_AUX_Z_L_G]		= 0x00,
-	[BMI260_AUX_Z_H_G]		= 0x00,
-	[BMI260_AUX_R_L_G]		= 0x00,
-	[BMI260_AUX_R_H_G]		= 0x00,
-	[BMI260_ACC_X_L_G]		= 0x00,
-	[BMI260_ACC_X_H_G]		= 0x00,
-	[BMI260_ACC_Y_L_G]		= 0x00,
-	[BMI260_ACC_Y_H_G]		= 0x00,
-	[BMI260_ACC_Z_L_G]		= 0x00,
-	[BMI260_ACC_Z_H_G]		= 0x00,
-	[BMI260_GYR_X_L_G]		= 0x00,
-	[BMI260_GYR_X_H_G]		= 0x00,
-	[BMI260_GYR_Y_L_G]		= 0x00,
-	[BMI260_GYR_Y_H_G]		= 0x00,
-	[BMI260_GYR_Z_L_G]		= 0x00,
-	[BMI260_GYR_Z_H_G]		= 0x00,
-	[BMI260_SENSORTIME_0]		= 0x00,
-	[BMI260_SENSORTIME_1]		= 0x00,
-	[BMI260_SENSORTIME_2]		= 0x00,
-	[BMI260_EVENT]			= 0xe2,
-	[BMI260_INT_STATUS_0]		= 0x00,
-	[BMI260_INT_STATUS_1]		= 0x18,
-	[BMI260_SC_OUT_0]		= 0x00,
-	[BMI260_SC_OUT_1]		= 0x00,
-	[BMI260_ORIENT_ACT]		= 0xe0,
-	[BMI260_INTERNAL_STATUS]	= 0x00,
-	[BMI260_TEMPERATURE_0]		= 0x00,
-	[BMI260_TEMPERATURE_1]		= 0x00,
-	[BMI260_FIFO_LENGTH_0]		= 0x00,
-	[BMI260_FIFO_LENGTH_1]		= 0xc0,
-	[BMI160_FIFO_DATA]		= 0x00,
-	[0x27 ... 0x2e]			= 0xff, /* Reserved */
-	[BMI260_FEAT_PAGE]		= 0xf8,
-	[0x30 ... 0x3f]			= 0x00, /* Features */
-	[BMI260_ACC_CONF]		= 0x00,
-	[BMI260_ACC_RANGE]		= 0xfc,
-	[BMI260_GYR_CONF]		= 0x00,
-	[BMI260_GYR_RANGE]		= 0xf0,
-	[BMI260_AUX_CONF]		= 0x00,
-	[BMI260_FIFO_DOWNS]		= 0x00,
-	[BMI260_FIFO_WTM_0]		= 0x00,
-	[BMI260_FIFO_WTM_1]		= 0xe0,
-	[BMI260_FIFO_CONFIG_0]		= 0xfc,
-	[BMI260_FIFO_CONFIG_1]		= 0x00,
-	[BMI260_SATURATION]		= 0xc0,
-	[BMI260_AUX_DEV_ID]		= 0x01,
-	[BMI260_AUX_IF_CONF]		= 0x30,
-	[BMI260_AUX_RD_ADDR]		= 0x00,
-	[BMI260_AUX_WR_ADDR]		= 0x00,
-	[BMI260_AUX_WR_DATA]		= 0x00,
-	[0x50 ... 0x51]			= 0xff, /* Reserved */
-	[BMI260_ERR_REG_MSK]		= 0x20,
-	[BMI260_INT1_IO_CTRL]		= 0xe1,
-	[BMI260_INT2_IO_CTRL]		= 0xe1,
-	[BMI260_INT_LATCH]		= 0xfe,
-	[BMI260_INT1_MAP_FEAT]		= 0x00,
-	[BMI260_INT2_MAP_FEAT]		= 0x00,
-	[BMI260_INT_MAP_DATA]		= 0x00,
-	[BMI260_INIT_CTRL]		= 0x00,
-	[0x5a]				= 0xff, /* Reserved */
-	[BMI260_INIT_ADDR_0]		= 0xf0,
-	[BMI260_INIT_ADDR_1]		= 0x00,
-	[0x5d]				= 0xff, /* Reserved */
-	[BMI260_INIT_DATA]		= 0x00,
-	[BMI260_INTERNAL_ERROR]		= 0xe9,
-	[0x60 ... 0x67]			= 0xff, /* Reserved */
-	[BMI260_AUX_IF_TRIM]		= 0xf8,
-	[BMI260_GYR_CRT_CONF]		= 0xf2,
-	[BMI260_NVM_CONF]		= 0xfd,
-	[BMI260_IF_CONF]		= 0xcc,
-	[BMI260_DRV]			= 0x00,
-	[BMI260_ACC_SELF_TEST]		= 0xf2,
-	[BMI260_GYR_SELF_TEST_AXES]	= 0xf0,
-	[0x6f]				= 0xff, /* Reserved */
-	[BMI260_NV_CONF]		= 0xf0,
-	[BMI260_OFFSET_ACC70]		= 0x00,
-	[BMI260_OFFSET_ACC70 + 1]	= 0x00,
-	[BMI260_OFFSET_ACC70 + 2]	= 0x00,
-	[BMI260_OFFSET_GYR70]		= 0x00,
-	[BMI260_OFFSET_GYR70 + 1]	= 0x00,
-	[BMI260_OFFSET_GYR70 + 2]	= 0x00,
-	[BMI160_OFFSET_EN_GYR98]	= 0x00,
-	[0x78 ... 0x7b]			= 0xff, /* Reserved */
-	[BMI260_PWR_CONF]		= 0xf8,
-	[BMI260_PWR_CTRL]		= 0xf0,
-	[BMI260_CMD_REG]		= 0x00,
-};
-
-/**
- * @brief Reset registers to default values and restore registers backed by NVM
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- */
-static void bmi260_emul_reset(uint8_t *regs, struct i2c_emul *emul)
-{
-	bool tag_time;
-	bool header;
-
-	regs[BMI260_CHIP_ID]		= 0x27;
-	regs[BMI260_ERR_REG]		= 0x00;
-	regs[BMI260_STATUS]		= 0x10;
-	regs[BMI260_AUX_X_L_G]		= 0x00;
-	regs[BMI260_AUX_X_H_G]		= 0x00;
-	regs[BMI260_AUX_Y_L_G]		= 0x00;
-	regs[BMI260_AUX_Y_H_G]		= 0x00;
-	regs[BMI260_AUX_Z_L_G]		= 0x00;
-	regs[BMI260_AUX_Z_H_G]		= 0x00;
-	regs[BMI260_AUX_R_L_G]		= 0x00;
-	regs[BMI260_AUX_R_H_G]		= 0x00;
-	regs[BMI260_ACC_X_L_G]		= 0x00;
-	regs[BMI260_ACC_X_H_G]		= 0x00;
-	regs[BMI260_ACC_Y_L_G]		= 0x00;
-	regs[BMI260_ACC_Y_H_G]		= 0x00;
-	regs[BMI260_ACC_Z_L_G]		= 0x00;
-	regs[BMI260_ACC_Z_H_G]		= 0x00;
-	regs[BMI260_GYR_X_L_G]		= 0x00;
-	regs[BMI260_GYR_X_H_G]		= 0x00;
-	regs[BMI260_GYR_Y_L_G]		= 0x00;
-	regs[BMI260_GYR_Y_H_G]		= 0x00;
-	regs[BMI260_GYR_Z_L_G]		= 0x00;
-	regs[BMI260_GYR_Z_H_G]		= 0x00;
-	regs[BMI260_SENSORTIME_0]	= 0x00;
-	regs[BMI260_SENSORTIME_1]	= 0x00;
-	regs[BMI260_SENSORTIME_2]	= 0x00;
-	regs[BMI260_EVENT]		= 0x01;
-	regs[BMI260_INT_STATUS_0]	= 0x00;
-	regs[BMI260_INT_STATUS_1]	= 0x00;
-	regs[BMI260_SC_OUT_0]		= 0x00;
-	regs[BMI260_SC_OUT_1]		= 0x00;
-	regs[BMI260_ORIENT_ACT]		= 0x00;
-	regs[BMI260_INTERNAL_STATUS]	= 0x00;
-	regs[BMI260_TEMPERATURE_0]	= 0x00;
-	regs[BMI260_TEMPERATURE_1]	= 0x80;
-	regs[BMI260_FIFO_LENGTH_0]	= 0x00;
-	regs[BMI260_FIFO_LENGTH_1]	= 0x00;
-	regs[BMI160_FIFO_DATA]		= 0x00;
-	regs[BMI260_FEAT_PAGE]		= 0x00;
-	regs[BMI260_ACC_CONF]		= 0xa8;
-	regs[BMI260_ACC_RANGE]		= 0x02;
-	regs[BMI260_GYR_CONF]		= 0xa9;
-	regs[BMI260_GYR_RANGE]		= 0x00;
-	regs[BMI260_AUX_CONF]		= 0x46;
-	regs[BMI260_FIFO_DOWNS]		= 0x88;
-	regs[BMI260_FIFO_WTM_0]		= 0x00;
-	regs[BMI260_FIFO_WTM_1]		= 0x02;
-	regs[BMI260_FIFO_CONFIG_0]	= 0x02;
-	regs[BMI260_FIFO_CONFIG_1]	= 0x10;
-	regs[BMI260_SATURATION]		= 0x00;
-	regs[BMI260_AUX_DEV_ID]		= 0x20;
-	regs[BMI260_AUX_IF_CONF]	= 0x83;
-	regs[BMI260_AUX_RD_ADDR]	= 0x42;
-	regs[BMI260_AUX_WR_ADDR]	= 0x4c;
-	regs[BMI260_AUX_WR_DATA]	= 0x02;
-	regs[BMI260_ERR_REG_MSK]	= 0x00;
-	regs[BMI260_INT1_IO_CTRL]	= 0x00;
-	regs[BMI260_INT2_IO_CTRL]	= 0x00;
-	regs[BMI260_INT_LATCH]		= 0x00;
-	regs[BMI260_INT1_MAP_FEAT]	= 0x00;
-	regs[BMI260_INT2_MAP_FEAT]	= 0x00;
-	regs[BMI260_INT_MAP_DATA]	= 0x00;
-	regs[BMI260_INIT_CTRL]		= 0x00;
-	regs[BMI260_INIT_ADDR_0]	= 0x00;
-	regs[BMI260_INIT_ADDR_1]	= 0x00;
-	regs[BMI260_INIT_DATA]		= 0x00;
-	regs[BMI260_INTERNAL_ERROR]	= 0x00;
-	regs[BMI260_AUX_IF_TRIM]	= 0x01;
-	regs[BMI260_GYR_CRT_CONF]	= 0x00;
-	regs[BMI260_NVM_CONF]		= 0x00;
-	regs[BMI260_IF_CONF]		= 0x00;
-	regs[BMI260_DRV]		= 0xff;
-	regs[BMI260_ACC_SELF_TEST]	= 0x00;
-	regs[BMI260_GYR_SELF_TEST_AXES]	= 0x00;
-	regs[BMI260_PWR_CONF]		= 0x03;
-	regs[BMI260_PWR_CTRL]		= 0x00;
-	regs[BMI260_CMD_REG]		= 0x00;
-
-	/* Call generic reset */
-	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
-	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
-	bmi_emul_reset_common(emul, tag_time, header);
-}
-
-/**
- * @brief Convert range in format of ACC_RANGE register to number of bits
- *        that should be shifted right to obtain 16 bit reported accelerometer
- *        value from internal 32 bit value
- *
- * @param range Value of ACC_RANGE register
- *
- * @return shift Number of LSB that should be ignored from internal
- *               accelerometer value
- */
-static int bmi260_emul_acc_range_to_shift(uint8_t range)
-{
-	switch (range & 0xf) {
-	case BMI260_GSEL_2G:
-		return 0;
-	case BMI260_GSEL_4G:
-		return 1;
-	case BMI260_GSEL_8G:
-		return 2;
-	case BMI260_GSEL_16G:
-		return 3;
-	default:
-		return 0;
-	}
-}
-
-/**
- * @brief Convert range in format of GYR_RANGE register to number of bits
- *        that should be shifted right to obtain 16 bit reported gyroscope
- *        value from internal 32 bit value
- *
- * @param range Value of GYR_RANGE register
- *
- * @return shift Number of LSB that should be ignored from internal
- *               gyroscope value
- */
-static int bmi260_emul_gyr_range_to_shift(uint8_t range)
-{
-	switch (range & 0x7) {
-	case BMI260_DPS_SEL_2000:
-		return 4;
-	case BMI260_DPS_SEL_1000:
-		return 3;
-	case BMI260_DPS_SEL_500:
-		return 2;
-	case BMI260_DPS_SEL_250:
-		return 1;
-	case BMI260_DPS_SEL_125:
-		return 0;
-	default:
-		return 0;
-	}
-}
-
-/**
- * @brief Execute first part of command. Emulate state of device which is
- *        during handling command (status bits etc). This function save time
- *        on which command should end.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param cmd Command that is starting
- *
- * @return 0 on success
- * @return -EIO on failure
- */
-static int bmi260_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
-{
-	int time;
-
-	switch (cmd) {
-	case BMI260_CMD_SOFT_RESET:
-		time = 1;
-		break;
-	case BMI260_CMD_FIFO_FLUSH:
-		time = 0;
-		break;
-	default:
-		LOG_ERR("Unknown command 0x%x", cmd);
-		return -EIO;
-	}
-
-	regs[BMI260_CMD_REG] = cmd;
-	bmi_emul_set_cmd_end_time(emul, time);
-
-	return 0;
-}
-
-/**
- * @brief Emulate end of ongoing command.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- */
-static void bmi260_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
-{
-	bool tag_time;
-	bool header;
-	int cmd;
-
-	cmd = regs[BMI260_CMD_REG];
-	regs[BMI260_CMD_REG] = 0;
-	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
-	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
-
-	switch (cmd) {
-	case BMI160_CMD_SOFT_RESET:
-		bmi260_emul_reset(regs, emul);
-		break;
-	case BMI160_CMD_FIFO_FLUSH:
-		bmi_emul_flush_fifo(emul, tag_time, header);
-		break;
-	}
-}
-
-/**
- * @brief Get currently accessed register. It is first register plus number of
- *        handled bytes for all registers except BMI260_FIFO_DATA and
- *        BMI260_INIT_DATA for which address incrementation is disabled.
- *
- * @param emul Pointer to BMI emulator
- * @param reg First byte of last write message
- * @param bytes Number of bytes already handled from current message
- * @param read If currently handled is read message
- *
- * @return Currently accessed register
- */
-static int bmi260_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
-				  bool read)
-{
-	/* Ignore first byte which sets starting register */
-	if (!read) {
-		byte -= 1;
-	}
-
-	/*
-	 * If register is FIFO data, then read data from FIFO.
-	 * Init data is also block, but it is not implemented in emulator.
-	 * Else block read access subsequent registers.
-	 */
-	if (reg <= BMI260_FIFO_DATA && reg + byte >= BMI260_FIFO_DATA) {
-		return BMI260_FIFO_DATA;
-	} else if (reg <= BMI260_INIT_DATA &&
-		   reg + byte >= BMI260_INIT_DATA) {
-		return BMI260_INIT_DATA;
-	}
-
-	return reg + byte;
-}
-
-/**
- * @brief BMI260 specific write function. It handle block writes. Init data
- *        register is trap register, so after reaching it, register address
- *        is not increased on block writes. Check if read only register is not
- *        accessed. Before writing value, ongoing command is finished if
- *        possible. Write to CMD register is handled by BMI260 specific
- *        function. On changing of FIFO header/headerless mode or
- *        enabling/disabling sensor in headerless mode FIFO is flushed.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param reg Register address that is accessed
- * @param byte Number of handled bytes in this write command
- * @param val Value that is being written
- *
- * @return 0 on success
- * @return BMI_EMUL_ACCESS_E on RO register access
- * @return -EIO on error
- */
-static int bmi260_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
-				    int reg, int byte, uint8_t val)
-{
-	uint8_t mask;
-	bool tag_time;
-	bool header;
-
-	reg = bmi260_emul_access_reg(emul, reg, byte, false /* = read */);
-
-	if (reg <= BMI260_FIFO_DATA || reg == BMI260_GYR_SELF_TEST_AXES ||
-	    reg == BMI260_INTERNAL_ERROR || reg == BMI260_SATURATION) {
-		return BMI_EMUL_ACCESS_E;
-	}
-
-
-	/* Stop on going command if required */
-	if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) {
-		bmi260_emul_end_cmd(regs, emul);
-	}
-
-	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
-	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
-
-	switch (reg) {
-	case BMI260_CMD_REG:
-		if (regs[BMI260_CMD_REG] != 0) {
-			LOG_ERR("Issued command before previous end");
-			return -EIO;
-		}
-
-		return bmi260_emul_start_cmd(regs, emul, val);
-	case BMI260_FIFO_CONFIG_1:
-		/*
-		 * Clear FIFO on transition between headerless and
-		 * header mode
-		 */
-		if (!!(val & BMI260_FIFO_HEADER_EN) != header) {
-			bmi_emul_flush_fifo(emul, tag_time, header);
-		}
-		break;
-	case BMI260_PWR_CTRL:
-		/*
-		 * Clear FIFO on enabling/disabling sensors in headerless
-		 * mode
-		 */
-		mask = BMI260_AUX_EN & BMI260_GYR_EN & BMI260_ACC_EN;
-		if ((val & mask) != (regs[BMI260_PWR_CTRL] & mask) && !header) {
-			bmi_emul_flush_fifo(emul, tag_time, header);
-		}
-		break;
-	}
-
-	return 0;
-}
-
-/**
- * @brief BMI260 specific read function. It handle block reads. FIFO data
- *        register and init data register are trap registers, so
- *        after reaching it, register address is not increased on block reads.
- *        Before reading value, ongoing command is finished if possible.
- *        Read of sensor data traps current emulator state in registers.
- *        Read of FIFO length and FIFO data triggers default BMI functions.
- *
- * @param regs Pointer to array of emulator's registers
- * @param emul Pointer to BMI emulator
- * @param reg Register address that is accessed
- * @param byte Byte which is accessed during block read
- * @param buf Pointer where read byte should be stored
- *
- * @return 0 on success
- * @return BMI_EMUL_ACCESS_E on WO register access
- * @return -EIO on other error
- */
-static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
-				   int reg, int byte, char *buf)
-{
-	uint16_t fifo_len;
-	bool acc_off_en;
-	bool gyr_off_en;
-	bool tag_time;
-	bool header;
-	int gyr_shift;
-	int acc_shift;
-	int fifo_byte;
-
-	/* Get number of bytes readed from FIFO */
-	fifo_byte = byte - (reg - BMI260_FIFO_DATA);
-
-	reg = bmi260_emul_access_reg(emul, reg, byte, true /* = read */);
-
-	if (reg == BMI260_CMD_REG) {
-		*buf = 0;
-
-		return BMI_EMUL_ACCESS_E;
-	}
-
-	/* Stop on going command if required */
-	if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) {
-		bmi260_emul_end_cmd(regs, emul);
-	}
-
-	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
-	header = regs[BMI260_FIFO_CONFIG_1] & BMI260_FIFO_HEADER_EN;
-	acc_off_en = regs[BMI260_NV_CONF] & BMI260_ACC_OFFSET_EN;
-	gyr_off_en = regs[BMI260_OFFSET_EN_GYR98] & BMI260_OFFSET_GYRO_EN;
-	gyr_shift = bmi260_emul_gyr_range_to_shift(regs[BMI260_GYR_RANGE]);
-	acc_shift = bmi260_emul_acc_range_to_shift(regs[BMI260_ACC_RANGE]);
-
-	switch (reg) {
-	case BMI260_GYR_X_L_G:
-	case BMI260_GYR_X_H_G:
-	case BMI260_GYR_Y_L_G:
-	case BMI260_GYR_Y_H_G:
-	case BMI260_GYR_Z_L_G:
-	case BMI260_GYR_Z_H_G:
-	case BMI260_ACC_X_L_G:
-	case BMI260_ACC_X_H_G:
-	case BMI260_ACC_Y_L_G:
-	case BMI260_ACC_Y_H_G:
-	case BMI260_ACC_Z_L_G:
-	case BMI260_ACC_Z_H_G:
-	case BMI260_SENSORTIME_0:
-	case BMI260_SENSORTIME_1:
-	case BMI260_SENSORTIME_2:
-		/*
-		 * Snapshot of current emulator state is created on data read
-		 * and shouldn't be changed until next I2C operation
-		 */
-		if (byte == 0) {
-			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
-					      BMI260_ACC_X_L_G,
-					      BMI260_GYR_X_L_G,
-					      BMI260_SENSORTIME_0,
-					      acc_off_en, gyr_off_en);
-		}
-		break;
-	case BMI260_FIFO_LENGTH_0:
-	case BMI260_FIFO_LENGTH_1:
-		if (byte == 0) {
-			fifo_len = bmi_emul_fifo_len(emul, tag_time, header);
-			regs[BMI260_FIFO_LENGTH_0] = fifo_len & 0xff;
-			regs[BMI260_FIFO_LENGTH_1] = (fifo_len >> 8) & 0x7;
-		}
-		break;
-	case BMI260_FIFO_DATA:
-		regs[reg] = bmi_emul_get_fifo_data(emul, fifo_byte, tag_time,
-						   header, acc_shift,
-						   gyr_shift);
-		break;
-	}
-
-	*buf = regs[reg];
-
-	return 0;
-}
-
-/** Registers backed in NVM by BMI260 */
-const int bmi260_nvm_reg[] = {BMI260_AUX_IF_TRIM,
-			      BMI260_NV_CONF,
-			      BMI260_DRV,
-			      BMI260_OFFSET_ACC70,
-			      BMI260_OFFSET_ACC70 + 1,
-			      BMI260_OFFSET_ACC70 + 2,
-			      BMI260_OFFSET_GYR70,
-			      BMI260_OFFSET_GYR70 + 1,
-			      BMI260_OFFSET_GYR70 + 2,
-			      BMI260_OFFSET_EN_GYR98};
-
-/** Confguration of BMI260 */
-struct bmi_emul_type_data bmi260_emul = {
-	.sensortime_follow_config_frame = true,
-	.handle_write = bmi260_emul_handle_write,
-	.handle_read = bmi260_emul_handle_read,
-	.access_reg = bmi260_emul_access_reg,
-	.reset = bmi260_emul_reset,
-	.rsvd_mask = bmi_emul_260_rsvd_mask,
-	.nvm_reg = bmi260_nvm_reg,
-	.nvm_len = ARRAY_SIZE(bmi260_nvm_reg),
-	.gyr_off_reg = BMI260_OFFSET_GYR70,
-	.acc_off_reg = BMI260_OFFSET_ACC70,
-	.gyr98_off_reg = BMI260_OFFSET_EN_GYR98,
-};
-
-/** Check description in emul_bmi.h */
-const struct bmi_emul_type_data *get_bmi260_emul_type_data(void)
-{
-	return &bmi260_emul;
-}
diff --git a/zephyr/emul/emul_common_i2c.c b/zephyr/emul/emul_common_i2c.c
deleted file mode 100644
index bd811f1424..0000000000
--- a/zephyr/emul/emul_common_i2c.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_common_i2c);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-
-/** Check description in emul_common_i2c.h */
-int i2c_common_emul_lock_data(struct i2c_emul *emul, k_timeout_t timeout)
-{
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-
-	return k_mutex_lock(&data->data_mtx, timeout);
-}
-
-/** Check description in emul_common_i2c.h */
-int i2c_common_emul_unlock_data(struct i2c_emul *emul)
-{
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-
-	return k_mutex_unlock(&data->data_mtx);
-}
-
-/** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_write_func(struct i2c_emul *emul,
-				    i2c_common_emul_write_func func, void *data)
-{
-	struct i2c_common_emul_data *emul_data;
-
-	emul_data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	emul_data->write_func = func;
-	emul_data->write_func_data = data;
-}
-
-/** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_read_func(struct i2c_emul *emul,
-				   i2c_common_emul_read_func func, void *data)
-{
-	struct i2c_common_emul_data *emul_data;
-
-	emul_data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	emul_data->read_func = func;
-	emul_data->read_func_data = data;
-}
-
-/** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_read_fail_reg(struct i2c_emul *emul, int reg)
-{
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	data->read_fail_reg = reg;
-}
-
-/** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg)
-{
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	data->write_fail_reg = reg;
-}
-
-/**
- * @brief Call start_write emulator callback if set. It handles first byte
- *        of I2C write message.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- *
- * @retval start_write emulator callback return code
- */
-static int i2c_common_emul_start_write(struct i2c_emul *emul,
-				       struct i2c_common_emul_data *data)
-{
-	int ret = 0;
-
-	data->msg_byte = 0;
-
-	if (data->start_write) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->start_write(emul, data->cur_reg);
-		k_mutex_unlock(&data->data_mtx);
-	}
-
-	return ret;
-}
-
-/**
- * @brief Call finish_write emulator callback if set. It is called after last
- *        byte of I2C write message.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- *
- * @retval finish_write emulator callback return code
- */
-static int i2c_common_emul_finish_write(struct i2c_emul *emul,
-					struct i2c_common_emul_data *data)
-{
-	int ret = 0;
-
-	if (data->finish_write) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->finish_write(emul, data->cur_reg, data->msg_byte);
-		k_mutex_unlock(&data->data_mtx);
-	}
-
-	return ret;
-}
-
-/**
- * @brief Call start_read emulator callback if set. It prepares emulator at
- *        the beginning of I2C read message.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- *
- * @retval start_read emulator callback return code
- */
-static int i2c_common_emul_start_read(struct i2c_emul *emul,
-				      struct i2c_common_emul_data *data)
-{
-	int ret = 0;
-
-	data->msg_byte = 0;
-
-	if (data->start_read) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->start_read(emul, data->cur_reg);
-		k_mutex_unlock(&data->data_mtx);
-	}
-
-	return ret;
-}
-
-/**
- * @brief Call finish_read emulator callback if set. It is called after last
- *        byte of I2C read message.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- *
- * @retval finish_read emulator callback return code
- */
-static int i2c_common_emul_finish_read(struct i2c_emul *emul,
-				       struct i2c_common_emul_data *data)
-{
-	int ret = 0;
-
-	if (data->finish_read) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->finish_read(emul, data->cur_reg, data->msg_byte);
-		k_mutex_unlock(&data->data_mtx);
-	}
-
-	return ret;
-}
-
-/**
- * @brief Handle byte from I2C write message. First custom user handler is
- *        called (if set). Next accessed register is compared with selected
- *        by user fail register. Lastly, specific I2C device emulator handler
- *        is called.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- * @param val Value of current byte
- *
- * @retval 0 If successful
- * @retval -EIO General input / output error
- */
-static int i2c_common_emul_write_byte(struct i2c_emul *emul,
-				      struct i2c_common_emul_data *data,
-				      uint8_t val)
-{
-	int reg, ret;
-
-	/* Custom user handler */
-	if (data->write_func) {
-		ret = data->write_func(emul, data->cur_reg, val, data->msg_byte,
-				       data->write_func_data);
-		if (ret < 0) {
-			return -EIO;
-		} else if (ret == 0) {
-			return 0;
-		}
-	}
-	/* Check if user wants to fail on accessed register */
-	if (data->access_reg) {
-		reg = data->access_reg(emul, data->cur_reg, data->msg_byte,
-				       false /* = read */);
-	} else {
-		/* Ignore first (register address) byte */
-		reg = data->cur_reg + data->msg_byte - 1;
-	}
-
-	if (data->write_fail_reg == reg ||
-	    data->write_fail_reg == I2C_COMMON_EMUL_FAIL_ALL_REG) {
-		return -EIO;
-	}
-	/* Emulator handler */
-	if (data->write_byte) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->write_byte(emul, data->cur_reg, val,
-				       data->msg_byte);
-		k_mutex_unlock(&data->data_mtx);
-		if (ret) {
-			return -EIO;
-		}
-	}
-
-	return 0;
-}
-
-/**
- * @brief Handle byte from I2C read message. First custom user handler is
- *        called (if set). Next accessed register is compared with selected
- *        by user fail register. Lastly, specific I2C device emulator handler
- *        is called.
- *
- * @param emul Pointer to emulator
- * @param data Pointer to emulator data
- * @param val Pointer to buffer where current response byte should be stored
- *
- * @retval 0 If successful
- * @retval -EIO General input / output error
- */
-static int i2c_common_emul_read_byte(struct i2c_emul *emul,
-				     struct i2c_common_emul_data *data,
-				     uint8_t *val)
-{
-	int reg, ret;
-
-	/* Custom user handler */
-	if (data->read_func) {
-		ret = data->read_func(emul, data->cur_reg, val, data->msg_byte,
-				      data->read_func_data);
-		if (ret < 0) {
-			return -EIO;
-		} else if (ret == 0) {
-			return 0;
-		}
-	}
-	/* Check if user wants to fail on accessed register */
-	if (data->access_reg) {
-		reg = data->access_reg(emul, data->cur_reg, data->msg_byte,
-				       true /* = read */);
-	} else {
-		reg = data->cur_reg + data->msg_byte;
-	}
-
-	if (data->read_fail_reg == reg ||
-	    data->read_fail_reg == I2C_COMMON_EMUL_FAIL_ALL_REG) {
-		return -EIO;
-	}
-	/* Emulator handler */
-	if (data->read_byte) {
-		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->read_byte(emul, data->cur_reg, val, data->msg_byte);
-		k_mutex_unlock(&data->data_mtx);
-		if (ret) {
-			return -EIO;
-		}
-	}
-
-	return 0;
-}
-
-/** Check description in emul_common_i2c.h */
-int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-			     int num_msgs, int addr)
-{
-	const struct i2c_common_emul_cfg *cfg;
-	struct i2c_common_emul_data *data;
-	bool read, stop;
-	int ret, i;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	cfg = data->cfg;
-
-	if (cfg->addr != addr) {
-		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
-			addr);
-		return -EIO;
-	}
-
-	i2c_dump_msgs(cfg->dev_label, msgs, num_msgs, addr);
-
-	for (; num_msgs > 0; num_msgs--, msgs++) {
-		read = msgs->flags & I2C_MSG_READ;
-		stop = msgs->flags & I2C_MSG_STOP;
-
-		switch (data->msg_state) {
-		case I2C_COMMON_EMUL_IN_WRITE:
-			if (read) {
-				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-				ret = i2c_common_emul_finish_write(emul, data);
-				if (ret) {
-					return ret;
-				}
-				ret = i2c_common_emul_start_read(emul, data);
-				if (ret) {
-					return ret;
-				}
-			}
-			break;
-		case I2C_COMMON_EMUL_IN_READ:
-			if (!read) {
-				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-				ret = i2c_common_emul_finish_read(emul, data);
-				if (ret) {
-					return ret;
-				}
-				/* Wait for write message with acctual data */
-				if (msgs->len == 0) {
-					continue;
-				}
-				/* Dispatch command/register address */
-				data->cur_reg = msgs->buf[0];
-				ret = i2c_common_emul_start_write(emul, data);
-				if (ret) {
-					return ret;
-				}
-			}
-			break;
-		case I2C_COMMON_EMUL_NONE_MSG:
-			if (read) {
-				ret = i2c_common_emul_start_read(emul, data);
-				if (ret) {
-					return ret;
-				}
-			} else {
-				/* Wait for write message with acctual data */
-				if (msgs->len == 0) {
-					continue;
-				}
-				/* Dispatch command/register address */
-				data->cur_reg = msgs->buf[0];
-				ret = i2c_common_emul_start_write(emul, data);
-				if (ret) {
-					return ret;
-				}
-			}
-		}
-
-		data->msg_state = read ? I2C_COMMON_EMUL_IN_READ
-				       : I2C_COMMON_EMUL_IN_WRITE;
-
-		if (stop) {
-			data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-		}
-
-		if (!read) {
-			/*
-			 * All current emulators use first byte of write message
-			 * as command/register address for following write bytes
-			 * or read message. Skip first byte which was dispatched
-			 * already.
-			 */
-			if (data->msg_byte == 0) {
-				data->msg_byte = 1;
-				i = 1;
-			} else {
-				i = 0;
-			}
-			/* Dispatch write command */
-			for (; i < msgs->len; i++, data->msg_byte++) {
-				ret = i2c_common_emul_write_byte(emul, data,
-								 msgs->buf[i]);
-				if (ret) {
-					return ret;
-				}
-			}
-			/* Finish write command */
-			if (stop) {
-				ret = i2c_common_emul_finish_write(emul, data);
-				if (ret) {
-					return ret;
-				}
-			}
-		} else {
-			/* Dispatch read command */
-			for (i = 0; i < msgs->len; i++, data->msg_byte++) {
-				ret = i2c_common_emul_read_byte(emul, data,
-							       &(msgs->buf[i]));
-				if (ret) {
-					return ret;
-				}
-			}
-
-			/* Finish read command */
-			if (stop) {
-				ret = i2c_common_emul_finish_read(emul, data);
-				if (ret) {
-					return ret;
-				}
-			}
-		}
-	}
-
-	return 0;
-}
-
-/** Check description in emul_common_i2c.h */
-void i2c_common_emul_init(struct i2c_common_emul_data *data)
-{
-	data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-	data->msg_byte = 0;
-	data->cur_reg = 0;
-
-	data->write_func = NULL;
-	data->read_func = NULL;
-
-	data->write_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
-	data->read_fail_reg = I2C_COMMON_EMUL_NO_FAIL_REG;
-
-	k_mutex_init(&data->data_mtx);
-}
diff --git a/zephyr/emul/emul_lis2dw12.c b/zephyr/emul/emul_lis2dw12.c
deleted file mode 100644
index 6fa8b31cc9..0000000000
--- a/zephyr/emul/emul_lis2dw12.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_lis2dw12_emul
-
-#include <device.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-#include <emul.h>
-#include <errno.h>
-#include <sys/__assert.h>
-
-#include "driver/accel_lis2dw12.h"
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_lis2dw12.h"
-#include "i2c.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(lis2dw12_emul, CONFIG_LIS2DW12_EMUL_LOG_LEVEL);
-
-#define LIS2DW12_DATA_FROM_I2C_EMUL(_emul)                                   \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct lis2dw12_emul_data, common)
-
-struct lis2dw12_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-	/** Emulated who-am-i register */
-	uint8_t who_am_i_reg;
-	/** Emulated ctrl2 register */
-	uint8_t ctrl2_reg;
-	/** Soft reset count */
-	uint32_t soft_reset_count;
-};
-
-struct lis2dw12_emul_cfg {
-	/** Common I2C config */
-	struct i2c_common_emul_cfg common;
-};
-
-struct i2c_emul *lis2dw12_emul_to_i2c_emul(const struct emul *emul)
-{
-	struct lis2dw12_emul_data *data = emul->data;
-
-	return &(data->common.emul);
-}
-
-void lis2dw12_emul_reset(const struct emul *emul)
-{
-	struct lis2dw12_emul_data *data = emul->data;
-	struct i2c_emul *i2c_emul = lis2dw12_emul_to_i2c_emul(emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
-					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
-					   I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
-	data->who_am_i_reg = LIS2DW12_WHO_AM_I;
-	data->ctrl2_reg = 0;
-	data->soft_reset_count = 0;
-}
-
-void lis2dw12_emul_set_who_am_i(const struct emul *emul, uint8_t who_am_i)
-{
-	struct lis2dw12_emul_data *data = emul->data;
-
-	data->who_am_i_reg = who_am_i;
-}
-
-uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul)
-{
-	struct lis2dw12_emul_data *data = emul->data;
-
-	return data->soft_reset_count;
-}
-
-static int lis2dw12_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				   int bytes)
-{
-	struct lis2dw12_emul_data *data = LIS2DW12_DATA_FROM_I2C_EMUL(emul);
-
-	switch (reg) {
-	case LIS2DW12_WHO_AM_I_REG:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->who_am_i_reg;
-		break;
-	case LIS2DW12_CTRL2_ADDR:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->ctrl2_reg;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int lis2dw12_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				    int bytes)
-{
-	struct lis2dw12_emul_data *data = LIS2DW12_DATA_FROM_I2C_EMUL(emul);
-
-	switch (reg) {
-	case LIS2DW12_WHO_AM_I_REG:
-		LOG_ERR("Can't write to who-am-i register");
-		return -EINVAL;
-	case LIS2DW12_CTRL2_ADDR:
-		__ASSERT_NO_MSG(bytes == 1);
-		if ((val & LIS2DW12_SOFT_RESET_MASK) != 0) {
-			/* Soft reset */
-			data->soft_reset_count++;
-		}
-		data->ctrl2_reg = val & ~LIS2DW12_SOFT_RESET_MASK;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static struct i2c_emul_api lis2dw12_emul_api_i2c = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-static int emul_lis2dw12_init(const struct emul *emul,
-			      const struct device *parent)
-{
-	const struct lis2dw12_emul_cfg *lis2dw12_cfg = emul->cfg;
-	const struct i2c_common_emul_cfg *cfg = &(lis2dw12_cfg->common);
-	struct lis2dw12_emul_data *data = emul->data;
-
-	data->common.emul.api = &lis2dw12_emul_api_i2c;
-	data->common.emul.addr = cfg->addr;
-	data->common.emul.parent = emul;
-	data->common.i2c = parent;
-	data->common.cfg = cfg;
-	i2c_common_emul_init(&data->common);
-
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
-}
-
-#define INIT_LIS2DW12(n)                                                  \
-	static struct lis2dw12_emul_data lis2dw12_emul_data_##n = {       \
-		.common = {                                               \
-			.write_byte = lis2dw12_emul_write_byte,           \
-			.read_byte = lis2dw12_emul_read_byte,             \
-		},                                                        \
-	};                                                                \
-	static const struct lis2dw12_emul_cfg lis2dw12_emul_cfg_##n = {   \
-		.common = {                                               \
-			.i2c_label = DT_INST_BUS_LABEL(n),                \
-			.dev_label = DT_INST_LABEL(n),                    \
-			.addr = DT_INST_REG_ADDR(n),                      \
-		},                                                        \
-	};                                                                \
-	EMUL_DEFINE(emul_lis2dw12_init, DT_DRV_INST(n),                   \
-		    &lis2dw12_emul_cfg_##n, &lis2dw12_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(INIT_LIS2DW12)
diff --git a/zephyr/emul/emul_ln9310.c b/zephyr/emul/emul_ln9310.c
deleted file mode 100644
index d4eaa8e38d..0000000000
--- a/zephyr/emul/emul_ln9310.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_ln9310_emul
-
-#include <device.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-#include <emul.h>
-#include <errno.h>
-#include <sys/__assert.h>
-
-#include "driver/ln9310.h"
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_ln9310.h"
-#include "i2c.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(ln9310_emul, CONFIG_LN9310_EMUL_LOG_LEVEL);
-
-#define LN9310_DATA_FROM_I2C_EMUL(_emul)                                     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct ln9310_emul_data, common)
-
-struct ln9310_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-	/** The current emulated battery cell type */
-	enum battery_cell_type battery_cell_type;
-	/** Emulated INT1 MSK register */
-	uint8_t int1_msk_reg;
-	/** Emulated Lion control register */
-	uint8_t lion_ctrl_reg;
-	/** Emulated startup control register */
-	uint8_t startup_ctrl_reg;
-	/** Emulated BC STST B register */
-	uint8_t bc_sts_b_reg;
-	/** Emulated BC STST C register */
-	uint8_t bc_sts_c_reg;
-	/** Emulated cfg 0 register */
-	uint8_t cfg_0_reg;
-	/** Emulated cfg 4 register */
-	uint8_t cfg_4_reg;
-	/** Emulated cfg 5 register */
-	uint8_t cfg_5_reg;
-	/** Emulated power control register */
-	uint8_t power_ctrl_reg;
-	/** Emulated timer control register */
-	uint8_t timer_ctrl_reg;
-	/** Emulated lower bound (LB) control register */
-	uint8_t lower_bound_ctrl_reg;
-	/** Emulated spare 0 register */
-	uint8_t spare_0_reg;
-	/** Emulated swap control 0 register */
-	uint8_t swap_ctrl_0_reg;
-	/** Emulated swap control 1 register */
-	uint8_t swap_ctrl_1_reg;
-	/** Emulated swap control 2 register */
-	uint8_t swap_ctrl_2_reg;
-	/** Emulated swap control 3 register */
-	uint8_t swap_ctrl_3_reg;
-	/** Emulated track control register */
-	uint8_t track_ctrl_reg;
-	/** Emulated mode change register */
-	uint8_t mode_change_reg;
-	/** Emulated system control register */
-	uint8_t sys_ctrl_reg;
-};
-
-static const struct emul *singleton;
-
-void ln9310_emul_set_context(const struct emul *emulator)
-{
-	singleton = emulator;
-}
-
-void ln9310_emul_reset(const struct emul *emulator)
-{
-	struct ln9310_emul_data *data = emulator->data;
-
-	data->lion_ctrl_reg = 0;
-	data->startup_ctrl_reg = 0;
-	data->bc_sts_b_reg = 0;
-	data->cfg_0_reg = 0;
-	data->cfg_4_reg = 0;
-	data->cfg_5_reg = 0;
-	data->power_ctrl_reg = 0;
-	data->timer_ctrl_reg = 0;
-	data->lower_bound_ctrl_reg = 0;
-	data->spare_0_reg = 0;
-	data->swap_ctrl_0_reg = 0;
-	data->swap_ctrl_1_reg = 0;
-	data->swap_ctrl_2_reg = 0;
-	data->swap_ctrl_3_reg = 0;
-	data->track_ctrl_reg = 0;
-	data->mode_change_reg = 0;
-	data->sys_ctrl_reg = 0;
-}
-
-void ln9310_emul_set_battery_cell_type(const struct emul *emulator,
-				       enum battery_cell_type type)
-{
-	struct ln9310_emul_data *data = emulator->data;
-
-	data->battery_cell_type = type;
-}
-
-void ln9310_emul_set_version(const struct emul *emulator, int version)
-{
-	struct ln9310_emul_data *data = emulator->data;
-
-	data->bc_sts_c_reg |= version & LN9310_BC_STS_C_CHIP_REV_MASK;
-}
-
-void ln9310_emul_set_vin_gt_10v(const struct emul *emulator, bool is_gt_10v)
-{
-	struct ln9310_emul_data *data = emulator->data;
-
-	if (is_gt_10v)
-		data->bc_sts_b_reg |= LN9310_BC_STS_B_INFET_OUT_SWITCH_OK;
-	else
-		data->bc_sts_b_reg &= ~LN9310_BC_STS_B_INFET_OUT_SWITCH_OK;
-}
-
-bool ln9310_emul_is_init(const struct emul *emulator)
-{
-	struct ln9310_emul_data *data =  emulator->data;
-
-	return (data->int1_msk_reg & LN9310_INT1_MODE) == 0;
-}
-
-enum battery_cell_type board_get_battery_cell_type(void)
-{
-	struct ln9310_emul_data *data = singleton->data;
-
-	return data->battery_cell_type;
-}
-
-static struct i2c_emul_api ln9310_emul_api_i2c = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-static int ln9310_emul_start_write(struct i2c_emul *emul, int reg)
-{
-	return 0;
-}
-
-static int ln9310_emul_finish_write(struct i2c_emul *emul, int reg, int bytes)
-{
-	return 0;
-}
-
-static int ln9310_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				  int bytes)
-{
-	struct ln9310_emul_data *data = LN9310_DATA_FROM_I2C_EMUL(emul);
-
-	switch (reg) {
-	case LN9310_REG_INT1_MSK:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->int1_msk_reg = val;
-		break;
-	case LN9310_REG_STARTUP_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->startup_ctrl_reg = val;
-		break;
-	case LN9310_REG_LION_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->lion_ctrl_reg = val;
-		break;
-	case LN9310_REG_BC_STS_B:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->bc_sts_b_reg = val;
-		break;
-	case LN9310_REG_BC_STS_C:
-		LOG_ERR("Can't write to BC STS C register");
-		return -EINVAL;
-	case LN9310_REG_CFG_0:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->cfg_0_reg = val;
-		break;
-	case LN9310_REG_CFG_4:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->cfg_4_reg = val;
-		break;
-	case LN9310_REG_CFG_5:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->cfg_5_reg = val;
-		break;
-	case LN9310_REG_PWR_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->power_ctrl_reg = val;
-		break;
-	case LN9310_REG_TIMER_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->timer_ctrl_reg = val;
-		break;
-	case LN9310_REG_LB_CTRL:
-		__ASSERT_NO_MSG(bytes = 1);
-		data->lower_bound_ctrl_reg = val;
-		break;
-	case LN9310_REG_SPARE_0:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->spare_0_reg = val;
-		break;
-	case LN9310_REG_SWAP_CTRL_0:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->swap_ctrl_0_reg = val;
-		break;
-	case LN9310_REG_SWAP_CTRL_1:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->swap_ctrl_1_reg = val;
-		break;
-	case LN9310_REG_SWAP_CTRL_2:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->swap_ctrl_2_reg = val;
-		break;
-	case LN9310_REG_SWAP_CTRL_3:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->swap_ctrl_3_reg = val;
-		break;
-	case LN9310_REG_TRACK_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->track_ctrl_reg = val;
-		break;
-	case LN9310_REG_MODE_CHANGE_CFG:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->mode_change_reg = val;
-		break;
-	case LN9310_REG_SYS_CTRL:
-		__ASSERT_NO_MSG(bytes == 1);
-		data->sys_ctrl_reg = val;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int ln9310_emul_start_read(struct i2c_emul *emul, int reg)
-{
-	return 0;
-}
-
-static int ln9310_emul_finish_read(struct i2c_emul *emul, int reg, int bytes)
-{
-	return 0;
-}
-
-static int ln9310_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				 int bytes)
-{
-	struct ln9310_emul_data *data = LN9310_DATA_FROM_I2C_EMUL(emul);
-
-	switch (reg) {
-	case LN9310_REG_INT1_MSK:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->int1_msk_reg;
-		break;
-	case LN9310_REG_STARTUP_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->startup_ctrl_reg;
-		break;
-	case LN9310_REG_LION_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->lion_ctrl_reg;
-		break;
-	case LN9310_REG_BC_STS_B:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->bc_sts_b_reg;
-		break;
-	case LN9310_REG_BC_STS_C:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->bc_sts_c_reg;
-		break;
-	case LN9310_REG_CFG_0:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->cfg_0_reg;
-		break;
-	case LN9310_REG_CFG_4:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->cfg_4_reg;
-		break;
-	case LN9310_REG_CFG_5:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->cfg_5_reg;
-		break;
-	case LN9310_REG_PWR_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->power_ctrl_reg;
-		break;
-	case LN9310_REG_TIMER_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->timer_ctrl_reg;
-		break;
-	case LN9310_REG_LB_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->lower_bound_ctrl_reg;
-		break;
-	case LN9310_REG_SPARE_0:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->spare_0_reg;
-		break;
-	case LN9310_REG_SWAP_CTRL_0:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->swap_ctrl_0_reg;
-		break;
-	case LN9310_REG_SWAP_CTRL_1:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->swap_ctrl_1_reg;
-		break;
-	case LN9310_REG_SWAP_CTRL_2:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->swap_ctrl_2_reg;
-		break;
-	case LN9310_REG_SWAP_CTRL_3:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->swap_ctrl_3_reg;
-		break;
-	case LN9310_REG_TRACK_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->track_ctrl_reg;
-		break;
-	case LN9310_REG_MODE_CHANGE_CFG:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->mode_change_reg;
-		break;
-	case LN9310_REG_SYS_CTRL:
-		__ASSERT_NO_MSG(bytes == 0);
-		*val = data->sys_ctrl_reg;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int ln9310_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
-				  bool read)
-{
-	return 0;
-}
-
-static int emul_ln9310_init(const struct emul *emul,
-			    const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct ln9310_emul_data *data = emul->data;
-
-	data->common.emul.api = &ln9310_emul_api_i2c;
-	data->common.emul.addr = cfg->addr;
-	data->common.emul.parent = emul;
-	data->common.i2c = parent;
-	data->common.cfg = cfg;
-	i2c_common_emul_init(&data->common);
-
-	singleton = emul;
-
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
-}
-
-#define INIT_LN9310(n)                                                         \
-	const struct ln9310_config_t ln9310_config = {                         \
-		.i2c_port = NAMED_I2C(power),                                  \
-		.i2c_addr_flags = DT_INST_REG_ADDR(n),                         \
-	};                                                                     \
-	static struct ln9310_emul_data ln9310_emul_data_##n = {                \
-		.common = {                                                    \
-			.start_write = ln9310_emul_start_write,                \
-			.write_byte = ln9310_emul_write_byte,                  \
-			.finish_write = ln9310_emul_finish_write,              \
-			.start_read = ln9310_emul_start_read,                  \
-			.read_byte = ln9310_emul_read_byte,                    \
-			.finish_read = ln9310_emul_finish_read,                \
-			.access_reg = ln9310_emul_access_reg,                  \
-		},                                                             \
-	};                                                                     \
-	static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = {        \
-		.i2c_label = DT_INST_BUS_LABEL(n),                             \
-		.dev_label = DT_INST_LABEL(n),                                 \
-		.addr = DT_INST_REG_ADDR(n),                                   \
-	};                                                                     \
-	EMUL_DEFINE(emul_ln9310_init, DT_DRV_INST(n), &ln9310_emul_cfg_##n,    \
-		    &ln9310_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(INIT_LN9310)
diff --git a/zephyr/emul/emul_pi3usb9201.c b/zephyr/emul/emul_pi3usb9201.c
deleted file mode 100644
index babef58c75..0000000000
--- a/zephyr/emul/emul_pi3usb9201.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_pi3usb9201_emul
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_pi3usb9201.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_pi3usb9201, LOG_LEVEL_DBG);
-
-#define EMUL_REG_COUNT (PI3USB9201_REG_HOST_STS + 1)
-#define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
-
-/** Run-time data used by the emulator */
-struct pi3usb9201_emul_data {
-	/** I2C emulator detail */
-	struct i2c_emul emul;
-	/** pi3usb9201 device being emulated */
-	const struct device *i2c;
-	/** Configuration information */
-	const struct pi3usb9201_emul_cfg *cfg;
-	/** Current state of all emulated pi3usb9201 registers */
-	uint8_t reg[EMUL_REG_COUNT];
-};
-
-/** Static configuration for the emulator */
-struct pi3usb9201_emul_cfg {
-	/** Label of the I2C bus this emulator connects to */
-	const char *i2c_label;
-	/** Pointer to run-time data */
-	struct pi3usb9201_emul_data *data;
-	/** Address of pi3usb9201 on i2c bus */
-	uint16_t addr;
-};
-
-int pi3usb9201_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
-{
-	struct pi3usb9201_emul_data *data;
-
-	if (!EMUL_REG_IS_VALID(reg))
-		return -EIO;
-
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
-	data->reg[reg] = val;
-
-	return 0;
-}
-
-int pi3usb9201_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val)
-{
-	struct pi3usb9201_emul_data *data;
-
-	if (!EMUL_REG_IS_VALID(reg))
-		return -EIO;
-
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
-	*val = data->reg[reg];
-
-	return 0;
-}
-
-static void pi3usb9201_emul_reset(struct i2c_emul *emul)
-{
-	struct pi3usb9201_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
-
-	data->reg[PI3USB9201_REG_CTRL_1]     = 0;
-	data->reg[PI3USB9201_REG_CTRL_2]     = 0;
-	data->reg[PI3USB9201_REG_CLIENT_STS] = 0;
-	data->reg[PI3USB9201_REG_HOST_STS]   = 0;
-}
-
-/**
- * Emulate an I2C transfer to a pi3usb9201
- *
- * This handles simple reads and writes
- *
- * @param emul I2C emulation information
- * @param msgs List of messages to process
- * @param num_msgs Number of messages to process
- * @param addr Address of the I2C target device
- *
- * @retval 0 If successful
- * @retval -EIO General input / output error
- */
-static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-				    int num_msgs, int addr)
-{
-	const struct pi3usb9201_emul_cfg *cfg;
-	struct pi3usb9201_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
-	cfg = data->cfg;
-
-	if (cfg->addr != addr) {
-		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
-			addr);
-		return -EIO;
-	}
-
-	i2c_dump_msgs("emul", msgs, num_msgs, addr);
-
-	if (num_msgs == 1) {
-		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
-		      && (msgs[0].len == 2))) {
-			LOG_ERR("Unexpected write msgs");
-			return -EIO;
-		}
-		return pi3usb9201_emul_set_reg(emul, msgs[0].buf[0],
-					       msgs[0].buf[1]);
-	} else if (num_msgs == 2) {
-		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
-		      && (msgs[0].len == 1)
-		      && ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)
-		      && (msgs[1].len == 1))) {
-			LOG_ERR("Unexpected read msgs");
-			return -EIO;
-		}
-		return pi3usb9201_emul_get_reg(emul, msgs[0].buf[0],
-					       &(msgs[1].buf[0]));
-	} else {
-		LOG_ERR("Unexpected num_msgs");
-		return -EIO;
-	}
-
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api pi3usb9201_emul_api = {
-	.transfer = pi3usb9201_emul_transfer,
-};
-
-/**
- * @brief Set up a new pi3usb9201 emulator
- *
- * This should be called for each pi3usb9201 device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int pi3usb9201_emul_init(const struct emul *emul,
-			 const struct device *parent)
-{
-	const struct pi3usb9201_emul_cfg *cfg = emul->cfg;
-	struct pi3usb9201_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &pi3usb9201_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	pi3usb9201_emul_reset(&data->emul);
-
-	return ret;
-}
-
-#define PI3USB9201_EMUL(n)                                                  \
-	static struct pi3usb9201_emul_data pi3usb9201_emul_data_##n = {};   \
-	static const struct pi3usb9201_emul_cfg pi3usb9201_emul_cfg_##n = { \
-		.i2c_label = DT_INST_BUS_LABEL(n),                          \
-		.data = &pi3usb9201_emul_data_##n,                          \
-		.addr = DT_INST_REG_ADDR(n),                                \
-	};                                                                  \
-	EMUL_DEFINE(pi3usb9201_emul_init, DT_DRV_INST(n),                   \
-		    &pi3usb9201_emul_cfg_##n, &pi3usb9201_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL)
-
-#define PI3USB9201_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &pi3usb9201_emul_data_##n.emul;
-
-struct i2c_emul *pi3usb9201_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c
deleted file mode 100644
index 4b1d87336e..0000000000
--- a/zephyr/emul/emul_smart_battery.c
+++ /dev/null
@@ -1,893 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_smart_battery
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(smart_battery);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_smart_battery.h"
-
-#include "crc8.h"
-#include "battery_smart.h"
-
-#define SBAT_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct sbat_emul_data, common)
-
-/** Run-time data used by the emulator */
-struct sbat_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Data required to simulate battery */
-	struct sbat_emul_bat_data bat;
-	/** Command that should be handled next */
-	int cur_cmd;
-	/** Message buffer which is used to handle smb transactions */
-	uint8_t msg_buf[MSG_BUF_LEN];
-	/** Total bytes that were generated in response to smb read operation */
-	int num_to_read;
-};
-
-/** Check description in emul_smart_battery.h */
-struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul)
-{
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-
-	return &data->bat;
-}
-
-/** Check description in emul_smart_battery.h */
-uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
-				unsigned int year)
-{
-	year   -= MANUFACTURE_DATE_YEAR_OFFSET;
-	year  <<= MANUFACTURE_DATE_YEAR_SHIFT;
-	year   &= MANUFACTURE_DATE_YEAR_MASK;
-	month <<= MANUFACTURE_DATE_MONTH_SHIFT;
-	month  &= MANUFACTURE_DATE_MONTH_MASK;
-	day   <<= MANUFACTURE_DATE_DAY_SHIFT;
-	day    &= MANUFACTURE_DATE_DAY_MASK;
-
-	return day | month | year;
-}
-
-/**
- * @brief Compute CRC from the beginning of the message
- *
- * @param addr Smart battery address on SMBus
- * @param read If message for which CRC is computed is read. For read message
- *             byte command and repeated address is added to CRC
- * @param cmd Command used in read message
- *
- * @return pec CRC from first bytes of message
- */
-static uint8_t sbat_emul_pec_head(uint8_t addr, int read, uint8_t cmd)
-{
-	uint8_t pec;
-
-	addr <<= 1;
-
-	pec = cros_crc8(&addr, 1);
-	if (!read) {
-		return pec;
-	}
-
-	pec = cros_crc8_arg(&cmd, 1, pec);
-	addr |= I2C_MSG_READ;
-	pec = cros_crc8_arg(&addr, 1, pec);
-
-	return pec;
-}
-
-/**
- * @brief Convert from 10mW power units to mA current under given mV voltage
- *
- * @param mw Power in 10mW units
- * @param mv Voltage in mV units
- *
- * @return Current in mA units
- */
-static uint16_t sbat_emul_10mw_to_ma(int mw, int mv)
-{
-	/* Smart battery use 10mW units, convert to mW */
-	mw *= 10;
-	/* Multiple by 1000 to get mA instead of A */
-	return 1000 * mw/mv;
-}
-
-/**
- * @brief Convert from mA current to 10mW power under given mV voltage
- *
- * @param ma Current in mA units
- * @param mv Voltage in mV units
- *
- * @return Power in 10mW units
- */
-static uint16_t sbat_emul_ma_to_10mw(int ma, int mv)
-{
-	int mw;
-	/* Divide by 1000 to get mW instead of uW */
-	mw = ma * mv / 1000;
-	/* Smart battery use 10mW units, convert to 10mW */
-	return mw / 10;
-}
-
-/**
- * @brief Get time in minutes how long it will take to get given amount of
- *        charge at given current flow
- *
- * @param bat Pointer to battery data to set error code in case of
- *            over/under flow in time calculation
- * @param rate Rate of current in mAh
- * @param cap Required amount of charge in mA
- * @param time Pointer to memory where calculated time will be stored
- *
- * @return 0 on success
- * @return -EINVAL when over or under flow occurred
- */
-static int sbat_emul_get_time_to_complete(struct sbat_emul_bat_data *bat,
-					  int rate, int cap, uint16_t *ret_time)
-{
-	int time;
-
-	/* At negative rate process never ends, return maximum value */
-	if (rate <= 0) {
-		*ret_time = UINT16_MAX;
-
-		return 0;
-	}
-	/* Convert capacity from mAh to mAmin */
-	time = cap * 60 / rate;
-	/* Check overflow */
-	if (time >= UINT16_MAX) {
-		*ret_time = UINT16_MAX;
-		bat->error_code = STATUS_CODE_OVERUNDERFLOW;
-
-		return -EINVAL;
-	}
-	/* Check underflow */
-	if (time < 0) {
-		*ret_time = 0;
-		bat->error_code = STATUS_CODE_OVERUNDERFLOW;
-
-		return -EINVAL;
-	}
-
-	*ret_time = time;
-
-	return 0;
-}
-
-/**
- * @brief Get time in minutes how long it will take to charge battery
- *
- * @param bat Pointer to battery data
- * @param rate Rate of charging current in mAh
- * @param time Pointer to memory where calculated time will be stored
- *
- * @return 0 on success
- * @return -EINVAL when over or under flow occurred
- */
-static int sbat_emul_time_to_full(struct sbat_emul_bat_data *bat, int rate,
-				  uint16_t *time)
-{
-	int cap;
-
-	cap = bat->full_cap - bat->cap;
-	return sbat_emul_get_time_to_complete(bat, rate, cap, time);
-}
-
-/**
- * @brief Get time in minutes how long it will take to discharge battery. Note,
- *        that rate should be negative to indicate discharging.
- *
- * @param bat Pointer to battery data
- * @param rate Rate of charging current in mAh
- * @param time Pointer to memory where calculated time will be stored
- *
- * @return 0 on success
- * @return -EINVAL when over or under flow occurred
- */
-static int sbat_emul_time_to_empty(struct sbat_emul_bat_data *bat, int rate,
-				   uint16_t *time)
-{
-	int cap;
-
-	/* Reverse to have discharging rate instead of charging rate */
-	rate = -rate;
-	cap = bat->cap;
-	return sbat_emul_get_time_to_complete(bat, rate, cap, time);
-}
-
-/**
- * @brief Check if battery can supply for 10 seconds additional power/current
- *        set in at_rate register.
- *
- * @param bat Pointer to battery data
- * @param rate Rate of charging current in mAh
- * @param ok Pointer to memory where 0 is written if battery is able to supply
- *           additional power/curent or 1 is written if battery is unable
- *           to do so.
- *
- * @return 0 on success
- */
-static int sbat_emul_read_at_rate_ok(struct sbat_emul_bat_data *bat,
-				     uint16_t *ok)
-{
-	int rem_time_s;
-	int rate;
-
-	rate = bat->at_rate;
-	if (bat->mode & MODE_CAPACITY) {
-		rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
-	}
-
-	/* Add current battery usage */
-	rate += bat->cur;
-	if (rate >= 0) {
-		/* Battery will be charged */
-		*ok = 1;
-
-		return 0;
-	}
-	/* Reverse to have discharging rate instead of charging rate */
-	rate = -rate;
-
-	rem_time_s = bat->cap * 3600 / rate;
-	if (rem_time_s > 10) {
-		/*
-		 * Battery can support 10 seconds of additional at_rate
-		 * current/power
-		 */
-		*ok = 1;
-	} else {
-		*ok = 0;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Get battery status. This function use emulated status register and
- *        set or clear some of the flags based on other properties of emulated
- *        smart battery. Discharge bit, capacity alarm, time alarm, fully
- *        discharged bit and error code are controlled by battery properties.
- *        Terminate charge/discharge/overcharge alarms are set only if they are
- *        set in emulated status register and battery is charging/discharging,
- *        so they are partialy controlled by emulated status register.
- *        Other bits are controlled by emulated status register
- *
- * @param emul Pointer to smart battery emulator
- *
- * @return value which equals to computed status register
- */
-static uint16_t sbat_emul_read_status(struct i2c_emul *emul)
-{
-	uint16_t status, cap, rem_time, charge_percent;
-	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
-
-	status = bat->status;
-
-	/*
-	 * Over charged and terminate charger alarm cannot appear when battery
-	 * is not charged
-	 */
-	if (bat->cur <= 0) {
-		status &= ~(STATUS_TERMINATE_CHARGE_ALARM |
-			    STATUS_OVERCHARGED_ALARM);
-		status |= STATUS_DISCHARGING;
-	}
-	/* Terminate discharge alarm cannot appear when battery is charged */
-	if (bat->cur >= 0) {
-		status &= ~(STATUS_TERMINATE_DISCHARGE_ALARM |
-			    STATUS_DISCHARGING);
-	}
-
-	sbat_emul_get_word_val(emul, SB_REMAINING_CAPACITY, &cap);
-	if (bat->cap_alarm && cap < bat->cap_alarm) {
-		status |= STATUS_REMAINING_CAPACITY_ALARM;
-	} else {
-		status &= ~STATUS_REMAINING_CAPACITY_ALARM;
-	}
-
-	sbat_emul_get_word_val(emul, SB_AVERAGE_TIME_TO_EMPTY, &rem_time);
-	if (bat->time_alarm && rem_time < bat->time_alarm) {
-		status |= STATUS_REMAINING_TIME_ALARM;
-	} else {
-		status &= ~STATUS_REMAINING_TIME_ALARM;
-	}
-
-	/* Unset fully discharged bit when charge is grater than 20% */
-	sbat_emul_get_word_val(emul, SB_RELATIVE_STATE_OF_CHARGE,
-			       &charge_percent);
-	if (charge_percent > 20) {
-		status &= ~STATUS_FULLY_DISCHARGED;
-	} else {
-		status |= STATUS_FULLY_DISCHARGED;
-	}
-
-	status |= bat->error_code & STATUS_ERR_CODE_MASK;
-
-	return status;
-}
-
-/** Check description in emul_smart_battery.h */
-int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val)
-{
-	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
-	int mode_mw;
-	int rate;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
-	mode_mw = bat->mode & MODE_CAPACITY;
-
-	switch (cmd) {
-	case SB_MANUFACTURER_ACCESS:
-		*val = bat->mf_access;
-		return 0;
-	case SB_REMAINING_CAPACITY_ALARM:
-		*val = bat->cap_alarm;
-		return 0;
-	case SB_REMAINING_TIME_ALARM:
-		*val = bat->time_alarm;
-		return 0;
-	case SB_BATTERY_MODE:
-		*val = bat->mode;
-		return 0;
-	case SB_AT_RATE:
-		*val = bat->at_rate;
-		return 0;
-	case SB_AT_RATE_TIME_TO_FULL:
-		/* Support for reporting time to full in mW mode is optional */
-		if (mode_mw && !bat->at_rate_full_mw_support) {
-			bat->error_code = STATUS_CODE_OVERUNDERFLOW;
-			*val = UINT16_MAX;
-
-			return -EINVAL;
-		}
-
-		rate = bat->at_rate;
-		if (mode_mw) {
-			rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
-		}
-		return sbat_emul_time_to_full(bat, rate, val);
-
-	case SB_AT_RATE_TIME_TO_EMPTY:
-		rate = bat->at_rate;
-		if (mode_mw) {
-			rate = sbat_emul_10mw_to_ma(rate, bat->design_mv);
-		}
-		return sbat_emul_time_to_empty(bat, rate, val);
-
-	case SB_AT_RATE_OK:
-		return sbat_emul_read_at_rate_ok(bat, val);
-	case SB_TEMPERATURE:
-		*val = bat->temp;
-		return 0;
-	case SB_VOLTAGE:
-		*val = bat->volt;
-		return 0;
-	case SB_CURRENT:
-		*val = bat->cur;
-		return 0;
-	case SB_AVERAGE_CURRENT:
-		*val = bat->avg_cur;
-		return 0;
-	case SB_MAX_ERROR:
-		*val = bat->max_error;
-		return 0;
-	case SB_RELATIVE_STATE_OF_CHARGE:
-		/* Percent of charge according to full capacity */
-		*val = 100 * bat->cap / bat->full_cap;
-		return 0;
-	case SB_ABSOLUTE_STATE_OF_CHARGE:
-		/* Percent of charge according to design capacity */
-		*val = 100 * bat->cap / bat->design_cap;
-		return 0;
-	case SB_REMAINING_CAPACITY:
-		if (mode_mw) {
-			*val = sbat_emul_ma_to_10mw(bat->cap, bat->design_mv);
-		} else {
-			*val = bat->cap;
-		}
-		return 0;
-	case SB_FULL_CHARGE_CAPACITY:
-		if (mode_mw) {
-			*val = sbat_emul_ma_to_10mw(bat->full_cap,
-						    bat->design_mv);
-		} else {
-			*val = bat->full_cap;
-		}
-		return 0;
-	case SB_RUN_TIME_TO_EMPTY:
-		rate = bat->cur;
-		return sbat_emul_time_to_empty(bat, rate, val);
-	case SB_AVERAGE_TIME_TO_EMPTY:
-		rate = bat->avg_cur;
-		return sbat_emul_time_to_empty(bat, rate, val);
-	case SB_AVERAGE_TIME_TO_FULL:
-		rate = bat->avg_cur;
-		return sbat_emul_time_to_full(bat, rate, val);
-	case SB_CHARGING_CURRENT:
-		*val = bat->desired_charg_cur;
-		return 0;
-	case SB_CHARGING_VOLTAGE:
-		*val = bat->desired_charg_volt;
-		return 0;
-	case SB_BATTERY_STATUS:
-		*val = sbat_emul_read_status(emul);
-		return 0;
-	case SB_CYCLE_COUNT:
-		*val = bat->cycle_count;
-		return 0;
-	case SB_DESIGN_CAPACITY:
-		if (mode_mw) {
-			*val = sbat_emul_ma_to_10mw(bat->design_cap,
-						    bat->design_mv);
-		} else {
-			*val = bat->design_cap;
-		}
-		return 0;
-	case SB_DESIGN_VOLTAGE:
-		*val = bat->design_mv;
-		return 0;
-	case SB_SPECIFICATION_INFO:
-		*val = bat->spec_info;
-		return 0;
-	case SB_MANUFACTURE_DATE:
-		*val = bat->mf_date;
-		return 0;
-	case SB_SERIAL_NUMBER:
-		*val = bat->sn;
-		return 0;
-	default:
-		/* Unknown command or return value is not word */
-		return 1;
-	}
-}
-
-/** Check description in emul_smart_battery.h */
-int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
-			     int *len)
-{
-	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
-
-	switch (cmd) {
-	case SB_MANUFACTURER_NAME:
-		*blk = bat->mf_name;
-		*len = bat->mf_name_len;
-		return 0;
-	case SB_DEVICE_NAME:
-		*blk = bat->dev_name;
-		*len = bat->dev_name_len;
-		return 0;
-	case SB_DEVICE_CHEMISTRY:
-		*blk = bat->dev_chem;
-		*len = bat->dev_chem_len;
-		return 0;
-	case SB_MANUFACTURER_DATA:
-		*blk = bat->mf_data;
-		*len = bat->mf_data_len;
-		return 0;
-	default:
-		/* Unknown command or return value is not word */
-		return 1;
-	}
-}
-
-/**
- * @brief Append PEC to read command response if battery support it
- *
- * @param data Pointer to smart battery emulator data
- * @param cmd Command for which PEC is calculated
- */
-static void sbat_emul_append_pec(struct sbat_emul_data *data, int cmd)
-{
-	uint8_t pec;
-
-	if (BATTERY_SPEC_VERSION(data->bat.spec_info) ==
-	    BATTERY_SPEC_VER_1_1_WITH_PEC) {
-		pec = sbat_emul_pec_head(data->common.cfg->addr, 1, cmd);
-		pec = cros_crc8_arg(data->msg_buf, data->num_to_read, pec);
-		data->msg_buf[data->num_to_read] = pec;
-		data->num_to_read++;
-	}
-}
-
-/** Check description in emul_smart_battery.h */
-void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
-			    int len, bool fail)
-{
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-
-	if (fail) {
-		data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
-		data->num_to_read = 0;
-		return;
-	}
-
-	data->num_to_read = MIN(len, MSG_BUF_LEN - 1);
-	memcpy(data->msg_buf, buf, data->num_to_read);
-	data->bat.error_code = STATUS_CODE_OK;
-	sbat_emul_append_pec(data, cmd);
-}
-
-/**
- * @brief Function which handles read messages. It expects that data->cur_cmd
- *        is set to command number which should be handled. It guarantee that
- *        data->num_to_read is set to number of bytes in data->msg_buf on
- *        successful handling read request. On error, data->num_to_read is
- *        always set to 0.
- *
- * @param emul Pointer to smart battery emulator
- * @param reg Command selected by last write message. If data->cur_cmd is
- *            different than SBAT_EMUL_NO_CMD, then reg should equal to
- *            data->cur_cmd
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int sbat_emul_handle_read_msg(struct i2c_emul *emul, int reg)
-{
-	struct sbat_emul_data *data;
-	uint16_t word;
-	uint8_t *blk;
-	int ret, len;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-
-	if (data->cur_cmd == SBAT_EMUL_NO_CMD) {
-		/* Unexpected read message without preceding command select */
-		data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
-		return -EIO;
-	}
-	data->cur_cmd = SBAT_EMUL_NO_CMD;
-	data->num_to_read = 0;
-
-	/* Handle commands which return word */
-	ret = sbat_emul_get_word_val(emul, reg, &word);
-	if (ret < 0) {
-		return -EIO;
-	}
-	if (ret == 0) {
-		data->num_to_read = 2;
-		data->msg_buf[0] = word & 0xff;
-		data->msg_buf[1] = (word >> 8) & 0xff;
-		data->bat.error_code = STATUS_CODE_OK;
-		sbat_emul_append_pec(data, reg);
-
-		return 0;
-	}
-
-	/* Handle commands which return block */
-	ret = sbat_emul_get_block_data(emul, reg, &blk, &len);
-	if (ret != 0) {
-		if (ret == 1) {
-			data->bat.error_code = STATUS_CODE_UNSUPPORTED;
-			LOG_ERR("Unknown read command (0x%x)", reg);
-		}
-
-		return -EIO;
-	}
-
-	data->num_to_read = len + 1;
-	data->msg_buf[0] = len;
-	memcpy(&data->msg_buf[1], blk, len);
-	data->bat.error_code = STATUS_CODE_OK;
-	sbat_emul_append_pec(data, reg);
-
-	return 0;
-}
-
-/**
- * @brief Function which finalize write messages.
- *
- * @param emul Pointer to smart battery emulator
- * @param reg First byte of write message, usually selected command
- * @param bytes Number of bytes received in data->msg_buf
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg,
-					int bytes)
-{
-	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
-	uint16_t word;
-	uint8_t pec;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
-
-	/*
-	 * Fail if:
-	 *  - there are no bytes to handle
-	 *  - there are too many bytes
-	 *  - there is command byte and only one data byte
-	 */
-	if (bytes <= 0 || bytes > 4 || bytes == 2) {
-		data->bat.error_code = STATUS_CODE_BADSIZE;
-		LOG_ERR("wrong write message size (%d)", bytes);
-
-		return -EIO;
-	}
-
-	/* There is only command for read */
-	if (bytes == 1) {
-		data->cur_cmd = reg;
-		return 0;
-	}
-
-	/* Handle PEC */
-	data->msg_buf[0] = reg;
-	if (bytes == 4) {
-		if (BATTERY_SPEC_VERSION(data->bat.spec_info) !=
-		    BATTERY_SPEC_VER_1_1_WITH_PEC) {
-			data->bat.error_code = STATUS_CODE_BADSIZE;
-			LOG_ERR("Unexpected PEC; No support in this version");
-
-			return -EIO;
-		}
-		pec = sbat_emul_pec_head(data->common.cfg->addr, 0, 0);
-		pec = cros_crc8_arg(data->msg_buf, 3, pec);
-		if (pec != data->msg_buf[3]) {
-			data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
-			LOG_ERR("Wrong PEC 0x%x != 0x%x",
-				pec, data->msg_buf[3]);
-
-			return -EIO;
-		}
-	}
-
-	word = ((int)data->msg_buf[2] << 8) | data->msg_buf[1];
-
-	switch (data->msg_buf[0]) {
-	case SB_MANUFACTURER_ACCESS:
-		bat->mf_access = word;
-		break;
-	case SB_REMAINING_CAPACITY_ALARM:
-		bat->cap_alarm = word;
-		break;
-	case SB_REMAINING_TIME_ALARM:
-		bat->time_alarm = word;
-		break;
-	case SB_BATTERY_MODE:
-		/* Allow to set only upper byte */
-		bat->mode &= 0xff;
-		bat->mode |= word & 0xff00;
-		break;
-	case SB_AT_RATE:
-		bat->at_rate = word;
-		break;
-	default:
-		data->bat.error_code = STATUS_CODE_ACCESS_DENIED;
-		LOG_ERR("Unknown write command (0x%x)", data->msg_buf[0]);
-
-		return -EIO;
-	}
-
-	data->bat.error_code = STATUS_CODE_OK;
-
-	return 0;
-}
-
-/**
- * @brief Function called for each byte of write message which is saved in
- *        data->msg_buf
- *
- * @param emul Pointer to smart battery emulator
- * @param reg First byte of write message, usually selected command
- * @param val Received byte of write message
- * @param bytes Number of bytes already received
- *
- * @return 0 on success
- */
-static int sbat_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				int bytes)
-{
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-
-	if (bytes < MSG_BUF_LEN) {
-		data->msg_buf[bytes] = val;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Function called for each byte of read message. Byte from data->msg_buf
- *        is copied to read message response.
- *
- * @param emul Pointer to smart battery emulator
- * @param reg First byte of last write message, usually selected command
- * @param val Pointer where byte to read should be stored
- * @param bytes Number of bytes already readed
- *
- * @return 0 on success
- */
-static int sbat_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-			       int bytes)
-{
-	struct sbat_emul_data *data;
-
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-
-	if (bytes < data->num_to_read) {
-		*val = data->msg_buf[bytes];
-	}
-
-	return 0;
-}
-
-/**
- * @brief Get currently accessed register, which always equals to selected
- *        command.
- *
- * @param emul Pointer to smart battery emulator
- * @param reg First byte of last write message, usually selected command
- * @param bytes Number of bytes already handled from current message
- * @param read If currently handled is read message
- *
- * @return Currently accessed register
- */
-static int sbat_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
-				bool read)
-{
-	return reg;
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api sbat_emul_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-/**
- * @brief Set up a new Smart Battery emulator
- *
- * This should be called for each Smart Battery device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int sbat_emul_init(const struct emul *emul,
-			  const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &sbat_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	return ret;
-}
-
-#define SMART_BATTERY_EMUL(n)						\
-	static struct sbat_emul_data sbat_emul_data_##n = {		\
-		.bat = {						\
-			.mf_access = DT_INST_PROP(n, mf_access),	\
-			.at_rate_full_mw_support = DT_INST_PROP(n,	\
-					at_rate_full_mw_support),	\
-			.spec_info = ((DT_STRING_TOKEN(DT_DRV_INST(n),	\
-						       version) <<	\
-				       BATTERY_SPEC_VERSION_SHIFT) &	\
-				      BATTERY_SPEC_VERSION_MASK) |	\
-				     ((DT_INST_PROP(n, vscale) <<	\
-				       BATTERY_SPEC_VSCALE_SHIFT) &	\
-				      BATTERY_SPEC_VSCALE_MASK) |	\
-				     ((DT_INST_PROP(n, ipscale) <<	\
-				       BATTERY_SPEC_IPSCALE_SHIFT) &	\
-				      BATTERY_SPEC_IPSCALE_MASK) |	\
-				     BATTERY_SPEC_REVISION_1,		\
-			.mode = (DT_INST_PROP(n,			\
-					      int_charge_controller) *	\
-				 MODE_INTERNAL_CHARGE_CONTROLLER) |	\
-				(DT_INST_PROP(n, primary_battery) *	\
-				 MODE_PRIMARY_BATTERY_SUPPORT),		\
-			.design_mv = DT_INST_PROP(n, design_mv),	\
-			.design_cap = DT_INST_PROP(n, design_cap),	\
-			.temp = DT_INST_PROP(n, temperature),		\
-			.volt = DT_INST_PROP(n, volt),			\
-			.cur = DT_INST_PROP(n, cur),			\
-			.avg_cur = DT_INST_PROP(n, avg_cur),		\
-			.max_error = DT_INST_PROP(n, max_error),	\
-			.cap = DT_INST_PROP(n, cap),			\
-			.full_cap = DT_INST_PROP(n, full_cap),		\
-			.desired_charg_cur = DT_INST_PROP(n,		\
-						desired_charg_cur),	\
-			.desired_charg_volt = DT_INST_PROP(n,		\
-						desired_charg_volt),	\
-			.cycle_count = DT_INST_PROP(n, cycle_count),	\
-			.sn = DT_INST_PROP(n, serial_number),		\
-			.mf_name = DT_INST_PROP(n, mf_name),		\
-			.mf_name_len = sizeof(				\
-					DT_INST_PROP(n, mf_name)) - 1,	\
-			.mf_data = DT_INST_PROP(n, mf_data),		\
-			.mf_data_len = sizeof(				\
-					DT_INST_PROP(n, mf_data)) - 1,	\
-			.dev_name = DT_INST_PROP(n, dev_name),		\
-			.dev_name_len = sizeof(				\
-					DT_INST_PROP(n, dev_name)) - 1,	\
-			.dev_chem = DT_INST_PROP(n, dev_chem),		\
-			.dev_chem_len = sizeof(				\
-					DT_INST_PROP(n, dev_chem)) - 1,	\
-			.mf_date = 0,					\
-			.cap_alarm = 0,					\
-			.time_alarm = 0,				\
-			.at_rate = 0,					\
-			.status = STATUS_INITIALIZED,			\
-			.error_code = STATUS_CODE_OK,			\
-		},							\
-		.cur_cmd = SBAT_EMUL_NO_CMD,				\
-		.common = {						\
-			.start_write = NULL,				\
-			.write_byte = sbat_emul_write_byte,		\
-			.finish_write = sbat_emul_finalize_write_msg,	\
-			.start_read = sbat_emul_handle_read_msg,	\
-			.read_byte = sbat_emul_read_byte,		\
-			.finish_read = NULL,				\
-			.access_reg = sbat_emul_access_reg,		\
-		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &sbat_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(sbat_emul_init, DT_DRV_INST(n), &sbat_emul_cfg_##n,	\
-		    &sbat_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL)
-
-#define SMART_BATTERY_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &sbat_emul_data_##n.common.emul;
-
-/** Check description in emul_smart_battery.h */
-struct i2c_emul *sbat_emul_get_ptr(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_syv682x.c b/zephyr/emul/emul_syv682x.c
deleted file mode 100644
index 3d76d10492..0000000000
--- a/zephyr/emul/emul_syv682x.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_syv682x_emul
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(syv682x);
-#include <stdint.h>
-#include <string.h>
-
-#include "emul/emul_syv682x.h"
-
-#define EMUL_REG_COUNT (SYV682X_CONTROL_4_REG + 1)
-#define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
-
-struct syv682x_emul_data {
-	/** I2C emulator detail */
-	struct i2c_emul emul;
-	/** Smart battery device being emulated */
-	const struct device *i2c;
-	/** Configuration information */
-	const struct syv682x_emul_cfg *cfg;
-	/** Current state of all emulated SYV682x registers */
-	uint8_t reg[EMUL_REG_COUNT];
-	/**
-	 * Current state of conditions affecting interrupt bits, as distinct
-	 * from the current values of those bits stored in reg.
-	 */
-	uint8_t status_cond;
-	uint8_t control_4_cond;
-};
-
-/** Static configuration for the emulator */
-struct syv682x_emul_cfg {
-	/** Label of the I2C bus this emulator connects to */
-	const char *i2c_label;
-	/** Address of smart battery on i2c bus */
-	uint16_t addr;
-	/** Pointer to runtime data */
-	struct syv682x_emul_data *data;
-};
-
-int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
-{
-	struct syv682x_emul_data *data;
-
-	if (!EMUL_REG_IS_VALID(reg))
-		return -EIO;
-
-	data = CONTAINER_OF(emul, struct syv682x_emul_data, emul);
-	data->reg[reg] = val;
-
-	return 0;
-}
-
-void syv682x_emul_set_status(struct i2c_emul *emul, uint8_t val)
-{
-	struct syv682x_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct syv682x_emul_data, emul);
-	data->status_cond = val;
-	data->reg[SYV682X_STATUS_REG] |= val;
-}
-
-int syv682x_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val)
-{
-	struct syv682x_emul_data *data;
-
-	if (!EMUL_REG_IS_VALID(reg))
-		return -EIO;
-
-	data = CONTAINER_OF(emul, struct syv682x_emul_data, emul);
-	*val = data->reg[reg];
-
-	return 0;
-}
-
-/**
- * Emulate an I2C transfer to an SYV682x. This handles simple reads and writes.
- *
- * @param emul I2C emulation information
- * @param msgs List of messages to process. For 'read' messages, this function
- *             updates the 'buf' member with the data that was read
- * @param num_msgs Number of messages to process
- * @param addr Address of the I2C target device.
- *
- * @return 0 on success, -EIO on general input / output error
- */
-static int syv682x_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-			      int num_msgs, int addr)
-{
-	const struct syv682x_emul_cfg *cfg;
-	struct syv682x_emul_data *data;
-	data = CONTAINER_OF(emul, struct syv682x_emul_data, emul);
-	cfg = data->cfg;
-
-	if (cfg->addr != addr) {
-		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
-				addr);
-		return -EIO;
-	}
-
-	i2c_dump_msgs("emul", msgs, num_msgs, addr);
-
-	if (num_msgs == 1) {
-		if (!((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE
-					&& msgs[0].len == 2)) {
-			LOG_ERR("Unexpected write msgs");
-			return -EIO;
-		}
-		return syv682x_emul_set_reg(emul, msgs[0].buf[0],
-				msgs[0].buf[1]);
-	} else if (num_msgs == 2) {
-		int ret;
-		int reg;
-		uint8_t *buf;
-
-		if (!((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE
-					&& msgs[0].len == 1
-					&& (msgs[1].flags & I2C_MSG_RW_MASK) ==
-						I2C_MSG_READ
-					&& (msgs[1].len == 1))) {
-			LOG_ERR("Unexpected read msgs");
-			return -EIO;
-		}
-
-		reg = msgs[0].buf[0];
-		buf = &msgs[1].buf[0];
-		ret = syv682x_emul_get_reg(emul, reg, buf);
-
-		switch (reg) {
-		/*
-		 * These registers are clear-on-read (if the underlying
-		 * condition has cleared).
-		 */
-		case SYV682X_STATUS_REG:
-			syv682x_emul_set_reg(emul, reg, data->status_cond);
-			break;
-		case SYV682X_CONTROL_4_REG:
-			syv682x_emul_set_reg(emul, reg, data->control_4_cond);
-			break;
-		default:
-			break;
-		}
-
-		return ret;
-	} else {
-		LOG_ERR("Unexpected num_msgs");
-		return -EIO;
-	}
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api syv682x_emul_api = {
-	.transfer = syv682x_emul_transfer,
-};
-
-/**
- * @brief Set up a new SYV682x emulator
- *
- * This should be called for each SYV682x device that needs to be emulated. It
- * registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int syv682x_emul_init(const struct emul *emul,
-			  const struct device *parent)
-{
-	const struct syv682x_emul_cfg *cfg = emul->cfg;
-	struct syv682x_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &syv682x_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	memset(data->reg, 0, sizeof(data->reg));
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	return ret;
-}
-
-#define SYV682X_EMUL(n)                                                       \
-	static struct syv682x_emul_data syv682x_emul_data_##n = {};           \
-	static const struct syv682x_emul_cfg syv682x_emul_cfg_##n = {         \
-		.i2c_label = DT_INST_BUS_LABEL(n),                            \
-		.data = &syv682x_emul_data_##n,                               \
-		.addr = DT_INST_REG_ADDR(n),                                  \
-	};                                                                    \
-	EMUL_DEFINE(syv682x_emul_init, DT_DRV_INST(n), &syv682x_emul_cfg_##n, \
-		    &syv682x_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL)
-
-#define SYV682X_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &syv682x_emul_data_##n.emul;
-
-
-struct i2c_emul *syv682x_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/emul_tcs3400.c b/zephyr/emul/emul_tcs3400.c
deleted file mode 100644
index 0fc432e9ff..0000000000
--- a/zephyr/emul/emul_tcs3400.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT zephyr_tcs3400
-
-#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(emul_tcs);
-
-#include <device.h>
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_tcs3400.h"
-
-#include "driver/als_tcs3400.h"
-
-#define TCS_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct tcs_emul_data, common)
-
-/** Run-time data used by the emulator */
-struct tcs_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Value of data byte in ongoing write message */
-	uint8_t write_byte;
-
-	/** Current state of emulated TCS3400 registers */
-	uint8_t reg[TCS_EMUL_REG_COUNT];
-	/** Return IR value instead of clear */
-	bool ir_select;
-	/** Internal values of light sensor registers */
-	int red;
-	int green;
-	int blue;
-	int clear;
-	int ir;
-
-	/** ID registers value */
-	uint8_t revision;
-	uint8_t id;
-
-	/** Return error when trying to write to RO register */
-	bool error_on_ro_write;
-	/** Return error when trying to write 1 to reserved bit */
-	bool error_on_rsvd_write;
-	/** Return error when trying to access MSB before LSB */
-	bool error_on_msb_first;
-	/**
-	 * Flag set when LSB register is accessed and cleared when MSB is
-	 * accessed. Allows to track order of accessing data registers
-	 */
-	bool lsb_r_read;
-	bool lsb_g_read;
-	bool lsb_b_read;
-	bool lsb_c_ir_read;
-};
-
-/** Check description in emul_tcs3400.h */
-void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
-{
-	struct tcs_emul_data *data;
-
-	if (reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) {
-		return;
-	}
-
-	reg -= TCS_EMUL_FIRST_REG;
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-	data->reg[reg] = val;
-}
-
-/** Check description in emul_tcs3400.h */
-uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg)
-{
-	struct tcs_emul_data *data;
-
-	if (reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) {
-		return 0;
-	}
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-	reg -= TCS_EMUL_FIRST_REG;
-
-	return data->reg[reg];
-}
-
-/** Check description in emul_tcs3400.h */
-int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case TCS_EMUL_R:
-		return data->red;
-	case TCS_EMUL_G:
-		return data->green;
-	case TCS_EMUL_B:
-		return data->blue;
-	case TCS_EMUL_C:
-		return data->clear;
-	case TCS_EMUL_IR:
-		return data->ir;
-	}
-
-	return 0;
-}
-
-/** Check description in emul_tcs3400.h */
-void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	switch (axis) {
-	case TCS_EMUL_R:
-		data->red = val;
-		break;
-	case TCS_EMUL_G:
-		data->green = val;
-		break;
-	case TCS_EMUL_B:
-		data->blue = val;
-		break;
-	case TCS_EMUL_C:
-		data->clear = val;
-		break;
-	case TCS_EMUL_IR:
-		data->ir = val;
-		break;
-	}
-}
-
-/** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_ro_write = set;
-}
-
-/** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_rsvd_write = set;
-}
-
-/** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-	data->error_on_msb_first = set;
-}
-
-/** Mask reserved bits in registers of TCS3400 */
-static const uint8_t tcs_emul_rsvd_mask[] = {
-	[TCS_I2C_ENABLE  - TCS_EMUL_FIRST_REG]	= 0xa4,
-	[TCS_I2C_ATIME   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[0x2]					= 0xff, /* Reserved */
-	[TCS_I2C_WTIME   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AILTL   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AILTH   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AIHTL   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AIHTH   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[0x8 ... 0xb]				= 0xff, /* Reserved */
-	[TCS_I2C_PERS    - TCS_EMUL_FIRST_REG]	= 0xf0,
-	[TCS_I2C_CONFIG  - TCS_EMUL_FIRST_REG]	= 0x81,
-	[0xe]					= 0xff, /* Reserved */
-	[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG]	= 0xfc,
-	[TCS_I2C_AUX     - TCS_EMUL_FIRST_REG]	= 0xdf,
-	[TCS_I2C_REVID   - TCS_EMUL_FIRST_REG]	= 0xf0,
-	[TCS_I2C_ID      - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG]	= 0x6e,
-	[TCS_I2C_CDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_CDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_RDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_RDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_GDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_GDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_BDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_BDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-};
-
-/**
- * @brief Reset registers to default values
- *
- * @param emul Pointer to TCS3400 emulator
- */
-static void tcs_emul_reset(struct i2c_emul *emul)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[TCS_I2C_ENABLE  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_ATIME   - TCS_EMUL_FIRST_REG] = 0xff;
-	data->reg[TCS_I2C_WTIME   - TCS_EMUL_FIRST_REG] = 0xff;
-	data->reg[TCS_I2C_AILTL   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AILTH   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AIHTL   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AIHTH   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_PERS    - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CONFIG  - TCS_EMUL_FIRST_REG] = 0x40;
-	data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AUX     - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_REVID   - TCS_EMUL_FIRST_REG] = data->revision;
-	data->reg[TCS_I2C_ID      - TCS_EMUL_FIRST_REG] = data->id;
-	data->reg[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_RDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_RDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_GDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_GDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_BDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_BDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-
-	data->ir_select = false;
-}
-
-/**
- * @brief Convert gain in format of CONTROL register to multiplyer
- *
- * @param control Value of CONTROL register
- *
- * @return gain by which messured value should be multiplied
- */
-static int tcs_emul_get_gain(uint8_t control)
-{
-	switch (control & TCS_I2C_CONTROL_MASK) {
-	case 0:
-		return 1;
-	case 1:
-		return 4;
-	case 2:
-		return 16;
-	case 3:
-		return 64;
-	default:
-		return -1;
-	}
-}
-
-/**
- * @brief Convert number of cycles in format of ATIME register
- *
- * @param atime Value of ATIME register
- *
- * @return cycles count that should be used to obtain light sensor values
- */
-static int tcs_emul_get_cycles(uint8_t atime)
-{
-	return TCS_EMUL_MAX_CYCLES - (int)atime;
-}
-
-/**
- * @brief Clear all interrupt registers
- *
- * @param emul Pointer to TCS3400 emulator
- */
-static void tcs_emul_clear_int(struct i2c_emul *emul)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG] = 0x00;
-}
-
-/**
- * @brief Handle I2C write message. It is checked if accessed register isn't RO
- *        and reserved bits are set to 0. Write set value of reg field of TCS
- *        emulator data ignoring reserved bits and write only bits. Some
- *        commands are handled specialy.
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg Register which is written
- * @param bytes Number of bytes received in this write message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int tcs_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
-{
-	struct tcs_emul_data *data;
-	uint8_t val;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	/* This write only selected register for I2C read message */
-	if (bytes < 2) {
-		return 0;
-	}
-
-	val = data->write_byte;
-
-	/* Register is in data->reg */
-	if (reg >= TCS_EMUL_FIRST_REG && reg <= TCS_EMUL_LAST_REG) {
-		if (reg >= TCS_I2C_REVID && reg <= TCS_I2C_BDATAH) {
-			if (data->error_on_ro_write) {
-				LOG_ERR("Writing to reg 0x%x which is RO", reg);
-				return -EIO;
-			}
-
-			return 0;
-		}
-
-		if (reg == TCS_I2C_CONFIG && data->error_on_rsvd_write &&
-		    !(BIT(6) & val)) {
-			LOG_ERR("CONFIG reg bit 6 is write as 6 (writing 0x%x)",
-				val);
-			return -EIO;
-		}
-
-		reg -= TCS_EMUL_FIRST_REG;
-		if (data->error_on_rsvd_write &&
-		    tcs_emul_rsvd_mask[reg] & val) {
-			LOG_ERR("Writing 0x%x to reg 0x%x with rsvd mask 0x%x",
-				val, reg + TCS_EMUL_FIRST_REG,
-				tcs_emul_rsvd_mask[reg]);
-			return -EIO;
-		}
-
-		/* Ignore all reserved bits */
-		val &= ~tcs_emul_rsvd_mask[reg];
-		val |= data->reg[reg] & tcs_emul_rsvd_mask[reg];
-
-		data->reg[reg] = val;
-
-		return 0;
-	}
-
-	switch (reg) {
-	case TCS_I2C_IR:
-		if (data->error_on_rsvd_write && 0x7f & val) {
-			LOG_ERR("Writing 0x%x to reg 0x%x with rsvd mask 0x7f",
-				val, reg);
-			return -EIO;
-		}
-		data->ir_select = !!(val & BIT(7));
-		break;
-	case TCS_I2C_IFORCE:
-		/* Interrupt generate is not supported */
-		break;
-	case TCS_I2C_CICLEAR:
-	case TCS_I2C_AICLEAR:
-		tcs_emul_clear_int(emul);
-		break;
-	default:
-		/* Assume that other registers are RO */
-		if (data->error_on_ro_write) {
-			LOG_ERR("Writing to reg 0x%x which is RO (unknown)",
-				reg);
-			return -EIO;
-		}
-	}
-
-	return 0;
-}
-
-/**
- * @brief Get set light sensor value for given register using internal
- *        state @p val. In case of accessing MSB check if LSB was accessed first
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg LSB or MSB register address. LSB has to be aligned to 2
- * @param lsb_read Pointer to variable which represent if last access to this
- *                 accelerometer value was through LSB register
- * @param lsb True if now accessing LSB, Flase if now accessing MSB
- * @param val Internal value of accessed light sensor
- *
- * @return 0 on success
- * @return -EIO when accessing MSB before LSB
- */
-static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg,
-				bool *lsb_read, bool lsb, unsigned int val)
-{
-	struct tcs_emul_data *data;
-	uint64_t reg_val;
-	int msb_reg;
-	int lsb_reg;
-	int cycles;
-	int gain;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	if (lsb) {
-		*lsb_read = 1;
-	} else {
-		/*
-		 * If error on first accessing MSB is set and LSB wasn't
-		 * accessed before, then return error.
-		 */
-		if (data->error_on_msb_first && !(*lsb_read)) {
-			return -EIO;
-		}
-		*lsb_read = 0;
-		/* LSB read should set correct value */
-		return 0;
-	}
-
-	lsb_reg = (reg - TCS_EMUL_FIRST_REG) & ~(0x1);
-	msb_reg = (reg - TCS_EMUL_FIRST_REG) | 0x1;
-
-	gain = tcs_emul_get_gain(data->reg[TCS_I2C_CONTROL -
-					   TCS_EMUL_FIRST_REG]);
-	cycles = tcs_emul_get_cycles(data->reg[TCS_I2C_ATIME -
-					       TCS_EMUL_FIRST_REG]);
-	/*
-	 * Internal value is with 256 cycles and x64 gain, so divide it to get
-	 * registers value
-	 */
-	reg_val = (uint64_t)val * cycles * gain / TCS_EMUL_MAX_CYCLES /
-		  TCS_EMUL_MAX_GAIN;
-
-	if (reg_val > UINT16_MAX) {
-		reg_val = UINT16_MAX;
-	}
-
-	data->reg[lsb_reg] = reg_val & 0xff;
-	data->reg[msb_reg] = (reg_val >> 8) & 0xff;
-
-	return 0;
-}
-
-/**
- * @brief Handle I2C read message. Response is obtained from reg field of TCS
- *        emul data. When accessing light sensor value, register data is first
- *        computed using internal emulator state.
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg First register address that is accessed in this read message
- * @param buf Pointer where result should be stored
- * @param bytes Number of bytes already handled in this read message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
-				int bytes)
-{
-	struct tcs_emul_data *data;
-	unsigned int c_ir;
-	int ret;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	reg += bytes;
-
-	if ((reg < TCS_EMUL_FIRST_REG || reg > TCS_EMUL_LAST_REG) &&
-	    reg != TCS_I2C_IR) {
-		LOG_ERR("Accessing register 0x%x which cannot be read", reg);
-		return -EIO;
-	}
-
-	switch (reg) {
-	case TCS_I2C_CDATAL:
-		/* Shouldn't fail for LSB */
-		c_ir = data->ir_select ? data->ir : data->clear;
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_c_ir_read,
-					   true, c_ir);
-		break;
-	case TCS_I2C_CDATAH:
-		c_ir = data->ir_select ? data->ir : data->clear;
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_c_ir_read,
-					   false, c_ir);
-		if (ret) {
-			LOG_ERR("MSB C read before LSB C");
-			return -EIO;
-		}
-		break;
-	case TCS_I2C_RDATAL:
-		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read,
-					   true, data->red);
-		break;
-	case TCS_I2C_RDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read,
-					   false, data->red);
-		if (ret) {
-			LOG_ERR("MSB R read before LSB R");
-			return -EIO;
-		}
-		break;
-	case TCS_I2C_GDATAL:
-		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read,
-					   true, data->green);
-		break;
-	case TCS_I2C_GDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read,
-					   false, data->green);
-		if (ret) {
-			LOG_ERR("MSB G read before LSB G");
-			return -EIO;
-		}
-		break;
-	case TCS_I2C_BDATAL:
-		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read,
-					   true, data->blue);
-		break;
-	case TCS_I2C_BDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read,
-					   false, data->blue);
-		if (ret) {
-			LOG_ERR("MSB B read before LSB B");
-			return -EIO;
-		}
-		break;
-	case TCS_I2C_IR:
-		*buf = data->ir_select ? BIT(7) : 0;
-
-		return 0;
-	}
-
-	*buf = data->reg[reg - TCS_EMUL_FIRST_REG];
-
-	return 0;
-}
-
-/**
- * @brief Handle I2C write message. Check if message is not too long and saves
- *        data that will be stored in register
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg Register address that is accessed
- * @param val Data to write to the register
- * @param bytes Number of bytes already handled in this read message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int tcs_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-			       int bytes)
-{
-	struct tcs_emul_data *data;
-
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	if (bytes > 1) {
-		LOG_ERR("Too long write command");
-		return -EIO;
-	}
-
-	data->write_byte = val;
-
-	return 0;
-}
-
-/* Device instantiation */
-
-static struct i2c_emul_api tcs_emul_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-/**
- * @brief Set up a new TCS3400 emulator
- *
- * This should be called for each TCS3400 device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int tcs_emul_init(const struct emul *emul,
-			 const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
-
-	data->emul.api = &tcs_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	tcs_emul_reset(&data->emul);
-
-	return ret;
-}
-
-#define TCS3400_EMUL(n)							\
-	static struct tcs_emul_data tcs_emul_data_##n = {		\
-		.revision = DT_INST_PROP(n, revision),			\
-		.id = DT_STRING_TOKEN(DT_DRV_INST(n), device_id),		\
-		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
-		.error_on_rsvd_write = DT_INST_PROP(n,			\
-					error_on_reserved_bit_write),	\
-		.error_on_msb_first = DT_INST_PROP(n,			\
-					error_on_msb_first_access),	\
-		.lsb_c_ir_read = 0,					\
-		.lsb_r_read = 0,					\
-		.lsb_g_read = 0,					\
-		.lsb_b_read = 0,					\
-		.common = {						\
-			.start_write = NULL,				\
-			.write_byte = tcs_emul_write_byte,		\
-			.finish_write = tcs_emul_handle_write,		\
-			.start_read = NULL,				\
-			.read_byte = tcs_emul_handle_read,		\
-			.finish_read = NULL,				\
-			.access_reg = NULL,				\
-		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &tcs_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(tcs_emul_init, DT_DRV_INST(n), &tcs_emul_cfg_##n,	\
-		    &tcs_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL)
-
-#define TCS3400_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &tcs_emul_data_##n.common.emul;
-
-/** Check description in emul_tcs3400.h */
-struct i2c_emul *tcs_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
diff --git a/zephyr/emul/i2c_mock.c b/zephyr/emul/i2c_mock.c
deleted file mode 100644
index 7c3722ad2e..0000000000
--- a/zephyr/emul/i2c_mock.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_i2c_mock
-
-#include <device.h>
-#include "emul/emul_common_i2c.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(i2c_mock, CONFIG_I2C_MOCK_LOG_LEVEL);
-
-struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul)
-{
-	struct i2c_common_emul_data *data = emul->data;
-
-	return &(data->emul);
-}
-
-void i2c_mock_reset(const struct emul *emul)
-{
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
-					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
-					   I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
-}
-
-uint16_t i2c_mock_get_addr(const struct emul *emul)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-
-	return cfg->addr;
-}
-
-static const struct i2c_emul_api i2c_mock_api = {
-	.transfer = i2c_common_emul_transfer,
-};
-
-static int i2c_mock_init(const struct emul *emul,
-			 const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = emul->data;
-
-	data->emul.api = &i2c_mock_api;
-	data->emul.addr = cfg->addr;
-	data->emul.parent = emul;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
-
-	return i2c_emul_register(parent, emul->dev_label, &data->emul);
-}
-
-#define INIT_I2C_MOCK(n)                                              \
-	static const struct i2c_common_emul_cfg i2c_mock_cfg_##n = {  \
-		.i2c_label = DT_INST_BUS_LABEL(n),                    \
-		.dev_label = DT_INST_LABEL(n),                        \
-		.addr = DT_INST_REG_ADDR(n),                          \
-	};                                                            \
-	static struct i2c_common_emul_data i2c_mock_data_##n;         \
-	EMUL_DEFINE(i2c_mock_init, DT_DRV_INST(n), &i2c_mock_cfg_##n, \
-		    &i2c_mock_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(INIT_I2C_MOCK)
diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py
deleted file mode 100755
index 446ad20bee..0000000000
--- a/zephyr/firmware_builder.py
+++ /dev/null
@@ -1,226 +0,0 @@
-#!/usr/bin/env python3
-# -*- coding: utf-8 -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Build and test all of the Zephyr boards.
-
-This is the entry point for the custom firmware builder workflow recipe.
-"""
-
-import argparse
-import multiprocessing
-import pathlib
-import subprocess
-import sys
-import zmake.project
-
-# TODO(crbug/1181505): Code outside of chromite should not be importing from
-# chromite.api.gen.  Import json_format after that so we get the matching one.
-from chromite.api.gen.chromite.api import firmware_pb2
-from google.protobuf import json_format
-
-DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles'
-DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata'
-
-
-def build(opts):
-    """Builds all Zephyr firmware targets"""
-    # TODO(b/169178847): Add appropriate metric information
-    metrics = firmware_pb2.FwBuildMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-
-    targets = [
-        'projects/kohaku',
-        'projects/posix-ec',
-        'projects/volteer/volteer',
-    ]
-    for target in targets:
-        print('Building {}'.format(target))
-        cmd = ['zmake', '-D', 'configure', '-b', target]
-        rv = subprocess.run(cmd, cwd=pathlib.Path(__file__).parent).returncode
-        if rv != 0:
-            return rv
-    return 0
-
-
-def bundle(opts):
-    if opts.code_coverage:
-        bundle_coverage(opts)
-    else:
-        bundle_firmware(opts)
-
-
-def get_bundle_dir(opts):
-    """Get the directory for the bundle from opts or use the default.
-
-    Also create the directory if it doesn't exist."""
-    bundle_dir = (opts.output_dir
-                  if opts.output_dir else DEFAULT_BUNDLE_DIRECTORY)
-    bundle_dir = pathlib.Path(bundle_dir)
-    if not bundle_dir.is_dir():
-        bundle_dir.mkdir()
-    return bundle_dir
-
-
-def write_metadata(opts, info):
-    """Write the metadata about the bundle."""
-    bundle_metadata_file = (opts.metadata
-                            if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE)
-    with open(bundle_metadata_file, 'w') as f:
-        f.write(json_format.MessageToJson(info))
-
-
-def bundle_coverage(opts):
-    """Bundles the artifacts from code coverage into its own tarball."""
-    info = firmware_pb2.FirmwareArtifactInfo()
-    info.bcs_version_info.version_string = opts.bcs_version
-    bundle_dir = get_bundle_dir(opts)
-    zephyr_dir = pathlib.Path(__file__).parent
-    platform_ec = zephyr_dir.resolve().parent
-    build_dir = platform_ec / 'build/zephyr-coverage'
-    tarball_name = 'coverage.tbz2'
-    tarball_path = bundle_dir / tarball_name
-    cmd = ['tar', 'cvfj', tarball_path, 'lcov.info']
-    subprocess.run(cmd, cwd=build_dir, check=True)
-    meta = info.objects.add()
-    meta.file_name = tarball_name
-    meta.lcov_info.type = firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV
-
-    write_metadata(opts, info)
-
-
-
-def bundle_firmware(opts):
-    """Bundles the artifacts from each target into its own tarball."""
-    info = firmware_pb2.FirmwareArtifactInfo()
-    info.bcs_version_info.version_string = opts.bcs_version
-    bundle_dir = get_bundle_dir(opts)
-    zephyr_dir = pathlib.Path(__file__).parent
-    platform_ec = zephyr_dir.resolve().parent
-    for project in zmake.project.find_projects(zephyr_dir):
-        build_dir = zmake.util.resolve_build_dir(platform_ec,
-                                                 project.project_dir, None)
-        artifacts_dir = build_dir / 'output'
-        # TODO(kmshelton): Remove once the build command does not rely
-        # on a pre-defined list of targets.
-        if not artifacts_dir.is_dir():
-            continue
-        project_identifier = '_'.join(
-            project.project_dir.
-            parts[project.project_dir.parts.index('projects') + 1:])
-        tarball_name = '{}.firmware.tbz2'.format(project_identifier)
-        tarball_path = bundle_dir.joinpath(tarball_name)
-        cmd = ['tar', 'cvfj', tarball_path, '.']
-        subprocess.run(cmd, cwd=artifacts_dir, check=True)
-        meta = info.objects.add()
-        meta.file_name = tarball_name
-        meta.tarball_info.type = (
-            firmware_pb2.FirmwareArtifactInfo.TarballInfo.FirmwareType.EC)
-        # TODO(kmshelton): Populate the rest of metadata contents as it
-        # gets defined in infra/proto/src/chromite/api/firmware.proto.
-
-    write_metadata(opts, info)
-
-
-def test(opts):
-    """Runs all of the unit tests for Zephyr firmware"""
-    # TODO(b/169178847): Add appropriate metric information
-    metrics = firmware_pb2.FwTestMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
-
-    zephyr_dir = pathlib.Path(__file__).parent.resolve()
-
-    # Run zmake tests to ensure we have a fully working zmake before
-    # proceeding.
-    subprocess.run([zephyr_dir / 'zmake' / 'run_tests.sh'], check=True)
-
-    subprocess.run(['zmake', '-D', 'testall'], check=True)
-
-    # Run the test with coverage also, as sometimes they behave differently.
-    platform_ec = zephyr_dir.parent
-    build_dir = platform_ec / 'build/zephyr-coverage'
-    return subprocess.run(
-        ['zmake', '-D', 'coverage', build_dir], cwd=platform_ec).returncode
-
-
-def main(args):
-    """Builds and tests all of the Zephyr targets and reports build metrics"""
-    opts = parse_args(args)
-
-    if not hasattr(opts, 'func'):
-        print("Must select a valid sub command!")
-        return -1
-
-    # Run selected sub command function
-    return opts.func(opts)
-
-
-def parse_args(args):
-    parser = argparse.ArgumentParser(description=__doc__)
-
-    parser.add_argument(
-        '--cpus',
-        default=multiprocessing.cpu_count(),
-        help='The number of cores to use.',
-    )
-
-    parser.add_argument(
-        '--metrics',
-        dest='metrics',
-        required=True,
-        help='File to write the json-encoded MetricsList proto message.',
-    )
-
-    parser.add_argument(
-        '--metadata',
-        required=False,
-        help=('Full pathname for the file in which to write build artifact '
-              'metadata.'),
-    )
-
-    parser.add_argument(
-        '--output-dir',
-        required=False,
-        help=
-        'Full pathanme for the directory in which to bundle build artifacts.',
-    )
-
-    parser.add_argument(
-        '--code-coverage',
-        required=False,
-        action='store_true',
-        help='Build host-based unit tests for code coverage.',
-    )
-
-    parser.add_argument(
-        '--bcs-version',
-        dest='bcs_version',
-        default='',
-        required=False,
-        # TODO(b/180008931): make this required=True.
-        help='BCS version to include in metadata.',
-    )
-
-    # Would make this required=True, but not available until 3.7
-    sub_cmds = parser.add_subparsers()
-
-    build_cmd = sub_cmds.add_parser('build',
-                                    help='Builds all firmware targets')
-    build_cmd.set_defaults(func=build)
-
-    build_cmd = sub_cmds.add_parser('bundle',
-                                    help='Creates a tarball containing build '
-                                    'artifacts from all firmware targets')
-    build_cmd.set_defaults(func=bundle)
-
-    test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests')
-    test_cmd.set_defaults(func=test)
-
-    return parser.parse_args(args)
-
-
-if __name__ == '__main__':
-    sys.exit(main(sys.argv[1:]))
diff --git a/zephyr/fpu.cmake b/zephyr/fpu.cmake
deleted file mode 100644
index 5f1c698b15..0000000000
--- a/zephyr/fpu.cmake
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-#[[
-Disclaimer: the following example is pieced together from
-https://lemire.me/blog/2020/06/26/gcc-not-nearest/ along with other information
-found in GCC documentation.
-
-The following flags are needed to to ensure consistent FPU rounding in unit
-tests. For example using GNU GCC 7.5 rounds down. Note that at the time of
-writing, Clang 13.0.0 passes all the FPU unit tests without these flags.
-
-Some of the sensor logic which requires FPU support is susceptible to rounding
-errors. In GCC 7.5, as an example:
-
-  double x = 50178230318.0;
-  double y = 100000000000.0;
-  double ratio = x/y;
-
-In this example, we would expect ratio to be 0.50178230318. Instead, using a
-64-bit float, it falls between:
-* The floating-point number 0.501782303179999944 == 4519653187245114  * 2 ** -53
-* The floating-point number 0.501782303180000055 == 4519653187245115  * 2 ** -53
-
-The real mantissa using the same logic should be:
-0.50178230318 = 4519653187245114.50011795456 * 2 ** -53
-
-Since the mantissa's decimal is just over 0.5, it should stand to reason that
-the correct solution is 0.501782303180000055. To force GCC to round correctly
-we must set the following modes:
-1. 'sse' - Generate SSE instructions.
-2. 'fpmath=sse' - Use scalar floating-point instructions present in the SSE
-   instruction set.
-3. 'arch=pentium4' - Choose the Pentium4 because it's a stable choice that
-   supports SSE and is known to work (there may be other good choices).
-]]
-if(DEFINED CONFIG_SOC_POSIX)
-  zephyr_cc_option(-msse -mfpmath=sse -march=pentium4)
-endif()
diff --git a/zephyr/gcov.tmpl.sh b/zephyr/gcov.tmpl.sh
deleted file mode 100755
index 96bd82ab51..0000000000
--- a/zephyr/gcov.tmpl.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/bash
-#
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-exec ${CMAKE_GCOV} "$@"
diff --git a/zephyr/hayato_get_cfg.sh b/zephyr/hayato_get_cfg.sh
deleted file mode 100755
index 5ebe3dc364..0000000000
--- a/zephyr/hayato_get_cfg.sh
+++ /dev/null
@@ -1,45 +0,0 @@
-#!/bin/bash
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# This is an example script showing how to compare configs on hayato
-
-# Usage of this script:
-# - set the three variables below
-# - set up the ecos.conf3 file as follows:
-#   $ make print-configs BOARD=hayato >econ.conf
-#   $ grep CONFIG ecos.conf |sort |uniq >ecos.conf2
-#   $ cat ecos.conf2  |awk '{print $1}' >ecos.conf3
-# - configure and build hayato for zephyr
-#   $ zmake configure -B /tmp/z/hay zephyr/projects/asurada/hayato/ -t zephyr -b
-# - run this script to check for CONFIG mismatches
-#   $ zephyr/get_cfg.sh
-
-set -e
-
-dir=/tmp/z/hay
-subdir=build-singleimage
-in=~/cosarm/src/platform/ec/ecos.conf3
-
-cd "${dir}"
-pushd "${subdir}"
-
-# This is created by running:
-#
-#    ninja -v -C /tmp/z/hay/build-singleimage
-#
-# then replacing '-C' by '-E -dM'
-# The idea is to get a list of the #defines used to compile the code
-ccache /opt/zephyr-sdk/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gcc -DBUILD_VERSION=zephyr-v2.5.0-101-g7a99b4a3ee12 -DCHROMIUM_EC -DCONFIG_ZEPHYR -DKERNEL -D_FORTIFY_SOURCE=2 -D__ZEPHYR__=1 -I/scratch/sglass/cosarm/src/platform/ec/zephyr/include -I/tmp/z/hay/modules/ec/zephyr/shim/include -I/tmp/z/hay/modules/ec/fuzz -I/tmp/z/hay/modules/ec/test -I/tmp/z/hay/modules/ec/include -I/tmp/z/hay/modules/ec/include/driver -I/tmp/z/hay/modules/ec/third_party -I/scratch/sglass/cosarm/src/platform/ec/zephyr/app/ec/include -I/scratch/sglass/cosarm/src/platform/ec/zephyr/shim/chip/it8xxx2/include -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/include -Izephyr/include/generated -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/soc/riscv/riscv-ite/it8xxx2 -I/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/soc/riscv/riscv-ite/common/. -Iec/include/generated -I/scratch/sglass/cosarm/src/platform/ec/zephyr/projects/asurada/hayato/include -isystem /scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/lib/libc/minimal/include -isystem /opt/zephyr-sdk/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/9.2.0/include -isystem /opt/zephyr-sdk/riscv64-zephyr-elf/bin/../lib/gcc/riscv64-zephyr-elf/9.2.0/include-fixed -Os -imacros /tmp/z/hay/build-singleimage/zephyr/include/generated/autoconf.h -ffreestanding -fno-common -g -mabi=ilp32 -march=rv32imac -imacros /scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5/include/toolchain/zephyr_stdint.h -Wall -Wformat -Wformat-security -Wno-format-zero-length -Wno-main -Wno-pointer-sign -Wpointer-arith -Wno-address-of-packed-member -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -fno-pie -fno-pic -fno-strict-overflow -fno-reorder-functions -fno-defer-pop -fmacro-prefix-map=/scratch/sglass/cosarm/src/platform/ec/zephyr/projects/asurada/hayato=CMAKE_SOURCE_DIR -fmacro-prefix-map=/scratch/sglass/cosarm/src/third_party/zephyr/main/v2.5=ZEPHYR_BASE -ffunction-sections -fdata-sections -march=rv32i -std=c99 -nostdinc -MD -MT CMakeFiles/app.dir/tmp/z/hay/modules/ec/common/virtual_battery.c.obj -MF CMakeFiles/app.dir/tmp/z/hay/modules/ec/common/virtual_battery.c.obj.d \
-	-o /tmp/z/hay/zephyr.conf -E -dM \
-	/tmp/z/hay/modules/ec/common/virtual_battery.c
-popd
-
-sort <zephyr.conf >zephyr.conf2
-
-# Only look at CONFIG_xxx where xxx does not start with PLATFORM_EC
-grep <zephyr.conf2 -P 'CONFIG_(?!PLATFORM_EC)[A-Z]+' | \
-	awk '{print $2}' | \
-	sort >zephyr.conf3
-comm -23 "${in}" zephyr.conf3
diff --git a/zephyr/include/cros/binman.dtsi b/zephyr/include/cros/binman.dtsi
deleted file mode 100644
index 82bb801e6c..0000000000
--- a/zephyr/include/cros/binman.dtsi
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/dts-v1/;
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	binman {
-		filename = "zephyr.bin";
-		pad-byte = <0x1d>;
-		wp-ro {
-			compatible = "cros-ec,flash-layout";
-			type = "section";
-			offset = <0x0>;
-			size = <0x40000>;
-			read-only;
-			ec-ro {
-				type = "section";
-				ro-fw {
-					type = "blob";
-					filename = "zephyr_ro.bin";
-				};
-				fmap {
-				};
-				ro-frid {
-					type = "text";
-					size = <32>;
-					text-label = "version";
-				};
-			};
-		};
-		ec-rw {
-			compatible = "cros-ec,flash-layout";
-			type = "section";
-			offset = <0x40000>;
-			size = <0x40000>;
-			rw-fw {
-				type = "blob";
-				filename = "zephyr_rw.bin";
-			};
-			rw-fwid {
-				type = "text";
-				size = <32>;
-				text-label = "version";
-			};
-		};
-	};
-};
diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi
deleted file mode 100644
index 54ca7f63e3..0000000000
--- a/zephyr/include/cros/ite/it8xxx2.dtsi
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <cros/binman.dtsi>
-
-/ {
-	named-bbram-regions {
-		compatible = "named-bbram-regions";
-
-		scratchpad {
-			offset = <0x08>;
-			size = <0x04>;
-		};
-		saved-reset-flags {
-			offset = <0x00>;
-			size = <0x04>;
-		};
-		wake {
-			offset = <0x08>;
-			size = <0x04>;
-		};
-		pd0 {
-			offset = <0x04>;
-			size = <0x01>;
-		};
-		pd1 {
-			offset = <0x05>;
-			size = <0x01>;
-		};
-		try_slot {
-			offset = <0x0e>;
-			size = <0x01>;
-		};
-		pd2 {
-			offset = <0x06>;
-			size = <0x01>;
-		};
-	};
-
-	soc {
-		bbram: bb-ram@f02200 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "ite,it8xxx2-cros-bbram";
-			status = "okay";
-			reg = <0x00f02200 0xbf>;
-			reg-names = "memory";
-			label = "BBRAM";
-		};
-
-		shi: shi@f03a00 {
-			compatible = "ite,it8xxx2-cros-shi";
-			reg = <0x00f03a00 0x30>;
-			label = "SHI";
-			interrupts = <171 0>;
-			interrupt-parent = <&intc>;
-			pinctrl-0 = <&pinctrl_shi_mosi  /* GPM0 */
-				     &pinctrl_shi_miso  /* GPM1 */
-				     &pinctrl_shi_clk   /* GPM4 */
-				     &pinctrl_shi_cs>;  /* GPM5 */
-		};
-
-		fiu0: cros-flash@80000000 {
-			compatible = "ite,it8xxx2-cros-flash";
-			reg = <0x80000000 0x100000>;
-			label = "FLASH";
-		};
-	};
-
-	/* it8xxx2 has 1MB of flash. currently, we use 512KB from flash. */
-	binman {
-		wp-ro {
-			offset = <0x0>;
-			size = <0x40000>;
-		};
-		ec-rw {
-			offset = <0x40000>;
-			size = <0x40000>;
-		};
-	};
-};
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
deleted file mode 100644
index 9c84d5712d..0000000000
--- a/zephyr/include/cros/nuvoton/npcx.dtsi
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2021 The Chromium OS Authors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <cros/binman.dtsi>
-#include <nuvoton/npcx.dtsi>
-
-/ {
-
-	named-bbram-regions {
-		compatible = "named-bbram-regions";
-
-		scratchpad {
-			offset = <0x00>;
-			size = <0x04>;
-		};
-		saved-reset-flags {
-			offset = <0x04>;
-			size = <0x04>;
-		};
-		wake {
-			offset = <0x08>;
-			size = <0x04>;
-		};
-		pd0 {
-			offset = <0x0c>;
-			size = <0x01>;
-		};
-		pd1 {
-			offset = <0x0d>;
-			size = <0x01>;
-		};
-		try_slot {
-			offset = <0x0e>;
-			size = <0x01>;
-		};
-		pd2 {
-			offset = <0x0f>;
-			size = <0x01>;
-		};
-		ramlog {
-			offset = <0x20>;
-			size = <0x01>;
-		};
-		panic_flags {
-			offset = <0x23>;
-			size = <0x01>;
-		};
-		panic_bkup {
-			offset = <0x24>;
-			size = <0x1c>;
-		};
-		lct_time {
-			offset = <0x40>;
-			size = <0x04>;
-		};
-	};
-
-	soc {
-
-		cros_kb_raw: cros-kb-raw@400a3000 {
-			compatible = "nuvoton,npcx-cros-kb-raw";
-			reg = <0x400a3000 0x2000>;
-			label = "CROS_KB_RAW_0";
-			interrupts = <49 4>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
-			/*
-			 * No KSO2 (It's inverted and implemented by GPIO for
-			 * CONFIG_KEYBOARD_COL2_INVERTED.)
-			 */
-			pinctrl-0 = <&alt7_no_ksi0_sl
-				     &alt7_no_ksi1_sl
-				     &alt7_no_ksi2_sl
-				     &alt7_no_ksi3_sl
-				     &alt7_no_ksi4_sl
-				     &alt7_no_ksi5_sl
-				     &alt7_no_ksi6_sl
-				     &alt7_no_ksi7_sl
-				     &alt8_no_kso00_sl
-				     &alt8_no_kso01_sl
-				     &alt8_no_kso03_sl
-				     &alt8_no_kso04_sl
-				     &alt8_no_kso05_sl
-				     &alt8_no_kso06_sl
-				     &alt8_no_kso07_sl
-				     &alt9_no_kso08_sl
-				     &alt9_no_kso09_sl
-				     &alt9_no_kso10_sl
-				     &alt9_no_kso11_sl
-				     &alt9_no_kso12_sl
-				     &alt9_no_kso13_sl
-				     &alt9_no_kso14_sl
-				     &alt9_no_kso15_sl
-				     &alta_no_kso16_sl
-				     &alta_no_kso17_sl
-				     >;
-			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
-				    &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
-		};
-
-		mtc: mtc@400b7000 {
-			compatible = "nuvoton,npcx-cros-mtc";
-			reg = <0x400b7000 0x2000>;
-			mtc-alarm = <&wui_mtc>;
-			label = "MTC";
-		};
-
-		fiu0: cros-flash@40020000 {
-			compatible = "nuvoton,npcx-cros-flash";
-			reg = <0x40020000 0x2000>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL1 2>;
-			size = <0x80000>;
-			label = "FLASH_INTERFACE_UNIT0";
-			pinctrl-0 = <>;
-		};
-
-		shi: shi@4000f000 {
-			compatible = "nuvoton,npcx-cros-shi";
-			reg = <0x4000f000 0x120>;
-			interrupts = <18 1>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
-			pinctrl-0 = <&altc_shi_sl>;
-			shi-cs-wui =<&wui_io53>;
-			label = "SHI";
-		};
-	};
-
-	power-states {
-		suspend_to_idle_instant: suspend_to_idle_instant {
-			compatible = "zephyr,power-state";
-			power-state-name = "suspend-to-idle";
-			substate-id = <0>;
-			min-residency-us = <500>;
-		};
-
-		suspend_to_idle_normal: suspend_to_idle_normal {
-			compatible = "zephyr,power-state";
-			power-state-name = "suspend-to-idle";
-			substate-id = <1>;
-			min-residency-us = <200100>;
-		};
-	};
-};
-
-&cpu0 {
-	cpu-power-states = <&suspend_to_idle_instant &suspend_to_idle_normal>;
-};
-
-&bbram {
-	status = "okay";
-};
-
-&mdc {
-	status = "okay";
-};
diff --git a/zephyr/include/cros/nuvoton/npcx7.dtsi b/zephyr/include/cros/nuvoton/npcx7.dtsi
deleted file mode 100644
index 0526341e2c..0000000000
--- a/zephyr/include/cros/nuvoton/npcx7.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2021 The Chromium OS Authors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx.dtsi>
-
-/ {
-
-	soc {
-
-		dbg: dbg@400c3074 {
-			compatible = "nuvoton,npcx-cros-dbg";
-			reg = <0x400c3074 0x0C>;
-			pinctrl-0 = <&alt5_njen0_en>;
-			label = "DBG";
-			status = "disabled";
-		};
-	};
-
-};
diff --git a/zephyr/include/cros/nuvoton/npcx9.dtsi b/zephyr/include/cros/nuvoton/npcx9.dtsi
deleted file mode 100644
index de492d3306..0000000000
--- a/zephyr/include/cros/nuvoton/npcx9.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2021 The Chromium OS Authors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <cros/nuvoton/npcx.dtsi>
-
-/ {
-	soc {
-
-	};
-};
diff --git a/zephyr/include/cros/thermistor/thermistor.dtsi b/zephyr/include/cros/thermistor/thermistor.dtsi
deleted file mode 100644
index 033d5639e2..0000000000
--- a/zephyr/include/cros/thermistor/thermistor.dtsi
+++ /dev/null
@@ -1,308 +0,0 @@
-/ {
-	thermistor_3V3_30K9_47K_4050B: thermistor-3V3-30K9-47K-4050B {
-		status = "disabled";
-		compatible = "cros-ec,thermistor";
-		scaling-factor = <11>;
-		num-pairs = <10>;
-		steinhart-reference-mv = <3300>;
-		steinhart-reference-res = <30900>;
-
-		/*
-		 * Data derived from Steinhart-Hart equation in a resistor
-		 * divider circuit with Vdd=3300mV, R = 30.9Kohm, and thermistor
-		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
-		 */
-		sample-datum-0 {
-			milivolt = <(2753 / 11)>;
-			temp = <0>;
-			sample-index = <0>;
-		};
-		sample-datum-1 {
-			milivolt = <(2487 / 11)>;
-			temp = <10>;
-			sample-index = <1>;
-		};
-		sample-datum-2 {
-			milivolt = <(2165 / 11)>;
-			temp = <20>;
-			sample-index = <2>;
-		};
-		sample-datum-3 {
-			milivolt = <(1813 / 11)>;
-			temp = <30>;
-			sample-index = <3>;
-		};
-		sample-datum-4 {
-			milivolt = <(1145 / 11)>;
-			temp = <50>;
-			sample-index = <4>;
-		};
-		sample-datum-5 {
-			milivolt = <(878 / 11)>;
-			temp = <60>;
-			sample-index = <5>;
-		};
-		sample-datum-6 {
-			milivolt = <(665 / 11)>;
-			temp = <70>;
-			sample-index = <6>;
-		};
-		sample-datum-7 {
-			milivolt = <(500 / 11)>;
-			temp = <80>;
-			sample-index = <7>;
-		};
-		sample-datum-8 {
-			milivolt = <(375 / 11)>;
-			temp = <90>;
-			sample-index = <8>;
-		};
-		sample-datum-9 {
-			milivolt = <(282 / 11)>;
-			temp = <100>;
-			sample-index = <9>;
-		};
-	};
-
-
-	thermistor_3V0_22K6_47K_4050B: thermistor-3V0-22K6-47K-4050B {
-		status = "disabled";
-		compatible = "cros-ec,thermistor";
-		scaling-factor = <11>;
-		num-pairs = <13>;
-		steinhart-reference-mv = <3000>;
-		steinhart-reference-res = <22600>;
-
-		/*
-		 * Data derived from Steinhart-Hart equation in a resistor
-		 * divider circuit with Vdd=3000mV, R = 22.6Kohm, and thermistor
-		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
-		 */
-		sample-datum-0 {
-			milivolt = <( 2619 / 11)>;
-			temp = <0>;
-			sample-index = <0>;
-		};
-		sample-datum-1 {
-			milivolt = <( 2421 / 11)>;
-			temp = <10>;
-			sample-index = <1>;
-		};
-		sample-datum-2 {
-			milivolt = <( 2168 / 11)>;
-			temp = <20>;
-			sample-index = <2>;
-		};
-		sample-datum-3 {
-			milivolt = <( 1875 / 11)>;
-			temp = <30>;
-			sample-index = <3>;
-		};
-		sample-datum-4 {
-			milivolt = <( 1563 / 11)>;
-			temp = <40>;
-			sample-index = <4>;
-		};
-		sample-datum-5 {
-			milivolt = <( 1262 / 11)>;
-			temp = <50>;
-			sample-index = <5>;
-		};
-		sample-datum-6 {
-			milivolt = <(  994 / 11)>;
-			temp = <60>;
-			sample-index = <6>;
-		};
-		sample-datum-7 {
-			milivolt = <(  769 / 11)>;
-			temp = <70>;
-			sample-index = <7>;
-		};
-		sample-datum-8 {
-			milivolt = <(  588 / 11)>;
-			temp = <80>;
-			sample-index = <8>;
-		};
-		sample-datum-9 {
-			milivolt = <(  513 / 11)>;
-			temp = <85>;
-			sample-index = <9>;
-		};
-		sample-datum-10 {
-			milivolt = <(  448 / 11)>;
-			temp = <90>;
-			sample-index = <10>;
-		};
-		sample-datum-11 {
-			milivolt = <(  390 / 11)>;
-			temp = <95>;
-			sample-index = <11>;
-		};
-		sample-datum-12 {
-			milivolt = <(  340 / 11)>;
-			temp = <100>;
-			sample-index = <12>;
-		};
-	};
-
-	thermistor_3V3_13K7_47K_4050B: thermistor-3V3-13K7-47K-4050B {
-		status = "disabled";
-		compatible = "cros-ec,thermistor";
-		scaling-factor = <13>;
-		num-pairs = <13>;
-		steinhart-reference-mv = <3300>;
-		steinhart-reference-res = <13700>;
-
-		/*
-		 * Data derived from Steinhart-Hart equation in a resistor
-		 * divider circuit with Vdd=3300mV, R = 13.7Kohm, and thermistor
-		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
-		 */
-		sample-datum-0 {
-			milivolt = <(3033 / 13)>;
-			temp = <0>;
-			sample-index = <0>;
-		};
-		sample-datum-1 {
-			milivolt = <(2882 / 13)>;
-			temp = <10>;
-			sample-index = <1>;
-		};
-		sample-datum-2 {
-			milivolt = <(2677 / 13)>;
-			temp = <20>;
-			sample-index = <2>;
-		};
-		sample-datum-3 {
-			milivolt = <(2420 / 13)>;
-			temp = <30>;
-			sample-index = <3>;
-		};
-		sample-datum-4 {
-			milivolt = <(2119 / 13)>;
-			temp = <40>;
-			sample-index = <4>;
-		};
-		sample-datum-5 {
-			milivolt = <(1799 / 13)>;
-			temp = <50>;
-			sample-index = <5>;
-		};
-		sample-datum-6 {
-			milivolt = <(1485 / 13)>;
-			temp = <60>;
-			sample-index = <6>;
-		};
-		sample-datum-7 {
-			milivolt = <(1197 / 13)>;
-			temp = <70>;
-			sample-index = <7>;
-		};
-		sample-datum-8 {
-			milivolt = <( 947 / 13)>;
-			temp = <80>;
-			sample-index = <8>;
-		};
-		sample-datum-9 {
-			milivolt = <( 839 / 13)>;
-			temp = <85>;
-			sample-index = <9>;
-		};
-		sample-datum-10 {
-			milivolt = <( 741 / 13)>;
-			temp = <90>;
-			sample-index = <10>;
-		};
-		sample-datum-11 {
-			milivolt = <( 653 / 13)>;
-			temp = <95>;
-			sample-index = <11>;
-		};
-		sample-datum-12 {
-			milivolt = <( 576 / 13)>;
-			temp = <100>;
-			sample-index = <12>;
-		};
-	};
-
-
-	thermistor_3V3_51K1_47K_4050B: thermistor-3V3-51K1-47K-4050B {
-		status = "disabled";
-		compatible = "cros-ec,thermistor";
-		scaling-factor = <11>;
-		num-pairs = <13>;
-		steinhart-reference-mv = <3300>;
-		steinhart-reference-res = <51100>;
-
-		/*
-		 * Data derived from Steinhart-Hart equation in a resistor
-		 * divider circuit with Vdd=3300mV, R = 51.1Kohm, and thermistor
-		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
-		 */
-		sample-datum-0 {
-			milivolt = <(2484 / 11)>;
-			temp = <0>;
-			sample-index = <0>;
-		};
-		sample-datum-1 {
-			milivolt = <(2142 / 11)>;
-			temp = <10>;
-			sample-index = <1>;
-		};
-		sample-datum-2 {
-			milivolt = <(1767 / 11)>;
-			temp = <20>;
-			sample-index = <2>;
-		};
-		sample-datum-3 {
-			milivolt = <(1400 / 11)>;
-			temp = <30>;
-			sample-index = <3>;
-		};
-		sample-datum-4 {
-			milivolt = <(1072 / 11)>;
-			temp = <40>;
-			sample-index = <4>;
-		};
-		sample-datum-5 {
-			milivolt = <( 802 / 11)>;
-			temp = <50>;
-			sample-index = <5>;
-		};
-		sample-datum-6 {
-			milivolt = <( 593 / 11)>;
-			temp = <60>;
-			sample-index = <6>;
-		};
-		sample-datum-7 {
-			milivolt = <( 436 / 11)>;
-			temp = <70>;
-			sample-index = <7>;
-		};
-		sample-datum-8 {
-			milivolt = <( 321 / 11)>;
-			temp = <80>;
-			sample-index = <8>;
-		};
-		sample-datum-9 {
-			milivolt = <( 276 / 11)>;
-			temp = <85>;
-			sample-index = <9>;
-		};
-		sample-datum-10 {
-			milivolt = <( 237 / 11)>;
-			temp = <90>;
-			sample-index = <10>;
-		};
-		sample-datum-11 {
-			milivolt = <( 204 / 11)>;
-			temp = <95>;
-			sample-index = <11>;
-		};
-		sample-datum-12 {
-			milivolt = <( 177 / 11)>;
-			temp = <100>;
-			sample-index = <12>;
-		};
-	};
-};
diff --git a/zephyr/include/drivers/cros_cbi.h b/zephyr/include/drivers/cros_cbi.h
deleted file mode 100644
index aa55e03b77..0000000000
--- a/zephyr/include/drivers/cros_cbi.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Chrome OS-specific API for access to Cros Board Info(CBI)
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_CBI_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_CBI_H_
-
-#include <kernel.h>
-#include <device.h>
-#include <devicetree.h>
-
-#define CBI_SSFC_VALUE_COMPAT			named_cbi_ssfc_value
-#define CBI_SSFC_VALUE_ID(id)			DT_CAT(CBI_SSFC_VALUE_, id)
-#define CBI_SSFC_VALUE_ID_WITH_COMMA(id)	CBI_SSFC_VALUE_ID(id),
-#define CBI_SSFC_VALUE_INST_ENUM(inst, _) \
-	CBI_SSFC_VALUE_ID_WITH_COMMA(DT_INST(inst, CBI_SSFC_VALUE_COMPAT))
-#define CROS_CBI_LABEL				"cros_cbi"
-
-enum cbi_ssfc_value_id {
-	UTIL_LISTIFY(DT_NUM_INST_STATUS_OKAY(CBI_SSFC_VALUE_COMPAT),
-		     CBI_SSFC_VALUE_INST_ENUM)
-	CBI_SSFC_VALUE_COUNT
-};
-
-/**
- * @cond INTERNAL_HIDDEN
- *
- * cros cbi raw driver API definition and system call entry points
- *
- * (Internal use only.)
- */
-typedef int (*cros_cbi_api_init)(const struct device *dev);
-typedef int (*cros_cbi_api_ssfc_check_match)(const struct device *dev,
-					     enum cbi_ssfc_value_id value_id);
-
-__subsystem struct cros_cbi_driver_api {
-	cros_cbi_api_init init;
-	cros_cbi_api_ssfc_check_match ssfc_check_match;
-};
-
-/**
- * @endcond
- */
-
-/**
- * @brief Initialize CBI.
- *
- * @param dev Pointer to the device structure for the CBI instance.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_cbi_init(const struct device *dev);
-
-static inline int z_impl_cros_cbi_init(const struct device *dev)
-{
-	const struct cros_cbi_driver_api *api =
-		(const struct cros_cbi_driver_api *)dev->api;
-
-	if (!api->init) {
-		return -ENOTSUP;
-	}
-
-	return api->init(dev);
-}
-
-/**
- * @brief Check if the CBI SSFC value matches the one in the EEPROM
- *
- * @param dev Pointer to the device.
- *
- * @return 1 If matches, 0 if not.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_cbi_ssfc_check_match(const struct device *dev,
-					enum cbi_ssfc_value_id value_id);
-
-static inline int
-z_impl_cros_cbi_ssfc_check_match(const struct device *dev,
-				 enum cbi_ssfc_value_id value_id)
-{
-	const struct cros_cbi_driver_api *api =
-		(const struct cros_cbi_driver_api *)dev->api;
-
-	if (!api->ssfc_check_match) {
-		return -ENOTSUP;
-	}
-
-	return api->ssfc_check_match(dev, value_id);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_cbi.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_CBI_H_ */
diff --git a/zephyr/include/drivers/cros_flash.h b/zephyr/include/drivers/cros_flash.h
deleted file mode 100644
index 7f48cf7285..0000000000
--- a/zephyr/include/drivers/cros_flash.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * Copyright 2020 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Chrome OS-specific API for flash memory access
- * This exists only support the interface expected by the Chrome OS EC. It seems
- * better to implement this so we can make use of most of the existing code in
- * its keyboard_scan.c file and thus make sure we operate the same way.
- *
- * It provides raw access to flash memory module.
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_
-
-#include <kernel.h>
-#include <device.h>
-
-/**
- * @brief CROS Flash Driver APIs
- * @defgroup cros_flash_interface CROS Flash Driver APIs
- * @ingroup io_interfaces
- * @{
- */
-
-/**
- * @cond INTERNAL_HIDDEN
- *
- * cros keyboard raw driver API definition and system call entry points
- *
- * (Internal use only.)
- */
-typedef int (*cros_flash_api_init)(const struct device *dev);
-
-typedef int (*cros_flash_api_physical_read)(const struct device *dev,
-					    int offset, int size, char *data);
-
-typedef int (*cros_flash_api_physical_write)(const struct device *dev,
-					     int offset, int size,
-					     const char *data);
-
-typedef int (*cros_flash_api_physical_erase)(const struct device *dev,
-					     int offset, int size);
-
-typedef int (*cros_flash_api_physical_get_protect)(const struct device *dev,
-						   int bank);
-
-typedef uint32_t
-(*cros_flash_api_physical_get_protect_flags)(const struct device *dev);
-
-typedef int (*cros_flash_api_physical_protect_at_boot)(const struct device *dev,
-						       uint32_t new_flags);
-
-typedef int (*cros_flash_api_physical_protect_now)(const struct device *dev,
-						   int all);
-
-__subsystem struct cros_flash_driver_api {
-	cros_flash_api_init init;
-	cros_flash_api_physical_read physical_read;
-	cros_flash_api_physical_write physical_write;
-	cros_flash_api_physical_erase physical_erase;
-	cros_flash_api_physical_get_protect physical_get_protect;
-	cros_flash_api_physical_get_protect_flags physical_get_protect_flags;
-	cros_flash_api_physical_protect_at_boot physical_protect_at_boot;
-	cros_flash_api_physical_protect_now physical_protect_now;
-};
-
-/**
- * @endcond
- */
-
-/**
- * @brief Initialize physical flash.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_init(const struct device *dev);
-
-static inline int z_impl_cros_flash_init(const struct device *dev)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->init) {
-		return -ENOTSUP;
-	}
-
-	return api->init(dev);
-}
-
-/**
- * @brief Read from physical flash.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param offset Flash offset to read.
- * @param size Number of bytes to read.
- * @param data Destination buffer for data.  Must be 32-bit aligned.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_read(const struct device *dev, int offset,
-				       int size, char *data);
-
-static inline int z_impl_cros_flash_physical_read(const struct device *dev,
-						  int offset, int size,
-						  char *data)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_read) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_read(dev, offset, size, data);
-}
-
-/**
- * @brief Write to physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param offset Flash offset to write.
- * @param size Number of bytes to write.
- * @param data Destination buffer for data.  Must be 32-bit aligned.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_write(const struct device *dev, int offset,
-					int size, const char *data);
-
-static inline int z_impl_cros_flash_physical_write(const struct device *dev,
-						   int offset, int size,
-						   const char *data)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_write) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_write(dev, offset, size, data);
-}
-
-/**
- * @brief Erase physical flash.
- *
- * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param offset	Flash offset to erase.
- * @param size	        Number of bytes to erase.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_erase(const struct device *dev, int offset,
-					int size);
-
-static inline int z_impl_cros_flash_physical_erase(const struct device *dev,
-						   int offset, int size)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_erase) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_erase(dev, offset, size);
-}
-
-/**
- * @brief Read physical write protect setting for a flash bank.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param bank	Bank index to check.
- *
- * @return non-zero if bank is protected until reboot.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_get_protect(const struct device *dev,
-					      int bank);
-
-static inline int
-z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_get_protect) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_get_protect(dev, bank);
-}
-
-/**
- * @brief Return flash protect state flags from the physical layer.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- *
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall
-uint32_t cros_flash_physical_get_protect_flags(const struct device *dev);
-
-static inline uint32_t
-z_impl_cros_flash_physical_get_protect_flags(const struct device *dev)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_get_protect_flags) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_get_protect_flags(dev);
-}
-
-/**
- * @brief Enable/disable protecting firmware/pstate at boot.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param new_flags	to protect (only EC_FLASH_PROTECT_*_AT_BOOT are
- * taken care of)
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_protect_at_boot(const struct device *dev,
-						  uint32_t new_flags);
-
-static inline int
-z_impl_cros_flash_physical_protect_at_boot(const struct device *dev,
-					   uint32_t new_flags)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_protect_at_boot) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_protect_at_boot(dev, new_flags);
-}
-
-/**
- * @brief Protect now physical flash.
- *
- * @param dev Pointer to the device structure for the flash driver instance.
- * @param all	Protect all (=1) or just read-only and pstate (=0).
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_flash_physical_protect_now(const struct device *dev,
-					      int all);
-
-static inline int
-z_impl_cros_flash_physical_protect_now(const struct device *dev, int all)
-{
-	const struct cros_flash_driver_api *api =
-		(const struct cros_flash_driver_api *)dev->api;
-
-	if (!api->physical_protect_now) {
-		return -ENOTSUP;
-	}
-
-	return api->physical_protect_now(dev, all);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_flash.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_FLASH_H_ */
diff --git a/zephyr/include/drivers/cros_kb_raw.h b/zephyr/include/drivers/cros_kb_raw.h
deleted file mode 100644
index 1724f59d95..0000000000
--- a/zephyr/include/drivers/cros_kb_raw.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright 2020 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Chrome OS-specific API for raw keyboard access
- * This exists only support the interface expected by the Chrome OS EC. It seems
- * better to implement this so we can make use of most of the existing code in
- * its keyboard_scan.c file and thus make sure we operate the same way.
- *
- * It provides raw access to keyboard GPIOs.
- *
- * The keyboard matrix is read (by the caller, keyboard_scan.c in ECOS) by
- * driving output signals on the column lines and reading the row lines.
- *
- * This API and any drivers should be removed once we can safely move to using
- * the Zephyr kscan API.
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_
-
-#include <kernel.h>
-#include <device.h>
-
-/**
- * @brief CROS Keyboard Raw Driver APIs
- * @defgroup cros_kb_raw_interface CROS Keyboard Raw Driver APIs
- * @ingroup io_interfaces
- * @{
- */
-
-/**
- * @cond INTERNAL_HIDDEN
- *
- * cros keyboard raw driver API definition and system call entry points
- *
- * (Internal use only.)
- */
-typedef int (*cros_kb_raw_api_init)(const struct device *dev);
-
-typedef int (*cros_kb_raw_api_drive_column)(const struct device *dev, int col);
-
-typedef int (*cros_kb_raw_api_read_rows)(const struct device *dev);
-
-typedef int (*cros_kb_raw_api_enable_interrupt)(const struct device *dev,
-						int enable);
-
-__subsystem struct cros_kb_raw_driver_api {
-	cros_kb_raw_api_init init;
-	cros_kb_raw_api_drive_column drive_colum;
-	cros_kb_raw_api_read_rows read_rows;
-	cros_kb_raw_api_enable_interrupt enable_interrupt;
-};
-
-/**
- * @endcond
- */
-
-/**
- * @brief Initialize the raw keyboard interface.
- *
- * Must be called before any other functions in this interface.
- *
- * @param dev Pointer to the device structure for the keyboard driver instance.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_kb_raw_init(const struct device *dev);
-
-static inline int z_impl_cros_kb_raw_init(const struct device *dev)
-{
-	const struct cros_kb_raw_driver_api *api =
-		(const struct cros_kb_raw_driver_api *)dev->api;
-
-	if (!api->init) {
-		return -ENOTSUP;
-	}
-
-	return api->init(dev);
-}
-
-/**
- * @brief Drive the specified column low.
- *
- * Other columns are tristated.  See enum keyboard_column_index for special
- * values for <col>.
- *
- * @param dev Pointer to the device structure for the keyboard driver instance.
- * @param col Specified column is driven to low.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_kb_raw_drive_column(const struct device *dev, int col);
-static inline int z_impl_cros_kb_raw_drive_column(const struct device *dev,
-						  int col)
-{
-	const struct cros_kb_raw_driver_api *api =
-		(const struct cros_kb_raw_driver_api *)dev->api;
-
-	if (!api->drive_colum) {
-		return -ENOTSUP;
-	}
-
-	return api->drive_colum(dev, col);
-}
-
-/**
- * @brief Read raw row state.
- *
- * Bits are 1 if signal is present, 0 if not present.
- *
- * @param dev Pointer to the device structure for the keyboard driver instance.
- *
- * @return current raw row state value.
- */
-__syscall int cros_kb_raw_read_rows(const struct device *dev);
-static inline int z_impl_cros_kb_raw_read_rows(const struct device *dev)
-{
-	const struct cros_kb_raw_driver_api *api =
-		(const struct cros_kb_raw_driver_api *)dev->api;
-
-	if (!api->read_rows) {
-		return 0;
-	}
-
-	return api->read_rows(dev);
-}
-
-/**
- * @brief Enable or disable keyboard interrupts.
- *
- * Enabling interrupts will clear any pending interrupt bits.  To avoid missing
- * any interrupts that occur between the end of scanning and then, you should
- * call cros_kb_raw_read_rows() after this.  If it returns non-zero, disable
- * interrupts and go back to polling mode instead of waiting for an interrupt.
- *
- * @param dev Pointer to the device structure for the keyboard driver instance.
- * @param enable If 1, enable keyboard interrupt. Otherwise, disable it.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_kb_raw_enable_interrupt(const struct device *dev,
-					   int enable);
-
-static inline int z_impl_cros_kb_raw_enable_interrupt(const struct device *dev,
-						      int enable)
-{
-	const struct cros_kb_raw_driver_api *api =
-		(const struct cros_kb_raw_driver_api *)dev->api;
-
-	if (!api->enable_interrupt) {
-		return -ENOTSUP;
-	}
-
-	return api->enable_interrupt(dev, enable);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_kb_raw.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_KB_RAW_H_ */
diff --git a/zephyr/include/drivers/cros_rtc.h b/zephyr/include/drivers/cros_rtc.h
deleted file mode 100644
index 695aabef73..0000000000
--- a/zephyr/include/drivers/cros_rtc.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Chrome OS-specific API for real-time clock (RTC).
- * This exists only support the interface expected by the Chrome OS EC. It
- * provides raw access to RTC module.
- *
- * This API and any drivers should be removed once we can safely move to using
- * the Zephyr rtc API.
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_
-
-#include <kernel.h>
-#include <device.h>
-
-/**
- * @brief CROS Real-Time Clock (RTC) Driver APIs
- * @defgroup cros_rtc_interface CROS RTC Driver APIs
- * @ingroup io_interfaces
- * @{
- */
-
-/**
- * @brief RTC alarm callback
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- */
-typedef void (*cros_rtc_alarm_callback_t)(const struct device *dev);
-
-/**
- * @cond INTERNAL_HIDDEN
- *
- * cros real-time clock driver API definition and system call entry points
- *
- * (Internal use only.)
- */
-typedef int (*cros_rtc_api_configure)(const struct device *dev,
-				      cros_rtc_alarm_callback_t callback);
-
-typedef int (*cros_rtc_api_get_value)(const struct device *dev,
-				      uint32_t *value);
-
-typedef int (*cros_rtc_api_set_value)(const struct device *dev, uint32_t value);
-
-typedef int (*cros_rtc_api_get_alarm)(const struct device *dev,
-				      uint32_t *seconds,
-				      uint32_t *microseconds);
-
-typedef int (*cros_rtc_api_set_alarm)(const struct device *dev,
-				      uint32_t seconds, uint32_t microseconds);
-
-typedef int (*cros_rtc_api_reset_alarm)(const struct device *dev);
-
-__subsystem struct cros_rtc_driver_api {
-	cros_rtc_api_configure configure;
-	cros_rtc_api_get_value get_value;
-	cros_rtc_api_set_value set_value;
-	cros_rtc_api_get_alarm get_alarm;
-	cros_rtc_api_set_alarm set_alarm;
-	cros_rtc_api_reset_alarm reset_alarm;
-};
-
-/**
- * @endcond
- */
-
-/**
- * @brief Configure real-time clock callback func.
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- * @param callback Callback func when RTC alarm issued.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- * @retval -EINVAL Not valid callback func.
- */
-__syscall int cros_rtc_configure(const struct device *dev,
-				 cros_rtc_alarm_callback_t callback);
-static inline int z_impl_cros_rtc_configure(const struct device *dev,
-					    cros_rtc_alarm_callback_t callback)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->configure) {
-		return -ENOTSUP;
-	}
-
-	return api->configure(dev, callback);
-}
-
-/**
- * @brief Get the current real-time clock value.
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- * @param value Pointer to the number of current real-time clock value.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_rtc_get_value(const struct device *dev, uint32_t *value);
-static inline int z_impl_cros_rtc_get_value(const struct device *dev,
-					    uint32_t *value)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->get_value) {
-		return -ENOTSUP;
-	}
-
-	return api->get_value(dev, value);
-}
-
-/**
- * @brief Set a desired value to real-time clock.
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- * @param value Number of desired real-time clock value.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_rtc_set_value(const struct device *dev, uint32_t value);
-static inline int z_impl_cros_rtc_set_value(const struct device *dev,
-					    uint32_t value)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->set_value) {
-		return -ENOTSUP;
-	}
-
-	return api->set_value(dev, value);
-}
-
-/**
- * @brief Get a given time when an RTC alarm interrupt issued.
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- * @param seconds Pointer to number of seconds before RTC alarm issued.
- * @param microseconds Pointer to number of micro-secs before RTC alarm issued.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_rtc_get_alarm(const struct device *dev, uint32_t *seconds,
-				 uint32_t *microseconds);
-
-static inline int z_impl_cros_rtc_get_alarm(const struct device *dev,
-					    uint32_t *seconds,
-					    uint32_t *microseconds)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->get_alarm) {
-		return 0;
-	}
-
-	return api->get_alarm(dev, seconds, microseconds);
-}
-
-/**
- * @brief Set up an RTC alarm interrupt at a given time from now
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- * @param seconds Number of seconds before RTC alarm issued.
- * @param microseconds Number of microseconds before alarm RTC issued.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_rtc_set_alarm(const struct device *dev, uint32_t seconds,
-				 uint32_t microseconds);
-
-static inline int z_impl_cros_rtc_set_alarm(const struct device *dev,
-					    uint32_t seconds,
-					    uint32_t microseconds)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->set_alarm) {
-		return 0;
-	}
-
-	return api->set_alarm(dev, seconds, microseconds);
-}
-
-/**
- * @brief Disable and clear the RTC alarm interrupt.
- *
- * @param dev Pointer to the device structure for the RTC driver instance.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported api function.
- */
-__syscall int cros_rtc_reset_alarm(const struct device *dev);
-
-static inline int z_impl_cros_rtc_reset_alarm(const struct device *dev)
-{
-	const struct cros_rtc_driver_api *api =
-		(const struct cros_rtc_driver_api *)dev->api;
-
-	if (!api->reset_alarm) {
-		return -ENOTSUP;
-	}
-
-	return api->reset_alarm(dev);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_rtc.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_RTC_H_ */
diff --git a/zephyr/include/drivers/cros_shi.h b/zephyr/include/drivers/cros_shi.h
deleted file mode 100644
index aab3507dd3..0000000000
--- a/zephyr/include/drivers/cros_shi.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Chrome OS-specific API for Serial Host Interface (SHI)
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_
-
-/**
- * @brief CROS Serial Host Interface Driver APIs
- * @defgroup cros_shi_interface CROS Serial Host Interface Driver APIs
- * @ingroup io_interfaces
- * @{
- */
-
-#include <kernel.h>
-#include <device.h>
-
-/**
- * @cond INTERNAL_HIDDEN
- *
- * cros Serial Host Interface driver API definition and system call entry points
- *
- * (Internal use only.)
- */
-typedef int (*cros_shi_api_enable)(const struct device *dev);
-
-typedef int (*cros_shi_api_disable)(const struct device *dev);
-
-/** @brief Driver API structure. */
-__subsystem struct cros_shi_driver_api {
-	cros_shi_api_enable enable;
-	cros_shi_api_disable disable;
-};
-
-/**
- * @brief Enable SHI module.
- *
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval non-negative if successful.
- * @retval Negative errno code if failure.
- */
-__syscall int cros_shi_enable(const struct device *dev);
-
-static inline int z_impl_cros_shi_enable(const struct device *dev)
-{
-	const struct cros_shi_driver_api *api =
-		(const struct cros_shi_driver_api *)dev->api;
-
-	if (!api->enable) {
-		return -ENOTSUP;
-	}
-
-	return api->enable(dev);
-}
-
-/**
- * @brief Disable SHI module.
- *
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval no return if successful.
- * @retval Negative errno code if failure.
- */
-__syscall int cros_shi_disable(const struct device *dev);
-
-static inline int z_impl_cros_shi_disable(const struct device *dev)
-{
-	const struct cros_shi_driver_api *api =
-		(const struct cros_shi_driver_api *)dev->api;
-
-	if (!api->disable) {
-		return -ENOTSUP;
-	}
-
-	return api->disable(dev);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_shi.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_SHI_H_ */
diff --git a/zephyr/include/drivers/cros_system.h b/zephyr/include/drivers/cros_system.h
deleted file mode 100644
index b0e06f1b59..0000000000
--- a/zephyr/include/drivers/cros_system.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- * @brief Public API for cros system drivers
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_
-#define ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_
-
-/**
- * @brief cros system Interface
- * @defgroup cros_system_interface cros system Interface
- * @ingroup io_interfaces
- * @{
- */
-
-#include <kernel.h>
-#include <device.h>
-
-/**
- * @brief system_reset_cause enum
- * Identify the reset cause.
- */
-enum system_reset_cause {
-	/* the reset is triggered by VCC power-up */
-	POWERUP = 0,
-	/* the reset is triggered by external VCC1 reset pin */
-	VCC1_RST_PIN = 1,
-	/* the reset is triggered by ICE debug reset request */
-	DEBUG_RST = 2,
-	/* the reset is triggered by watchdog */
-	WATCHDOG_RST = 3,
-	/* unknown reset type */
-	UNKNOWN_RST,
-};
-
-/**
- * @brief Get a node from path '/hibernate_wakeup_pins' which has a property
- *        'wakeup-pins' contains GPIO list for hibernate wake-up
- *
- * @return node identifier with that path.
- */
-#define SYSTEM_DT_NODE_HIBERNATE_CONFIG DT_INST(0, cros_ec_hibernate_wake_pins)
-
-/**
- * @brief Get the length of 'wakeup-pins' property
- *
- * @return length of 'wakeup-pins' prop which type is 'phandles'
- */
-#define SYSTEM_DT_NODE_WAKEUP_PIN_LEN \
-	DT_PROP_LEN(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_pins)
-
-/**
- * @brief Get a node identifier from a phandle in property 'wakeup-pins' at
- *        index i.
- *
- * @param i index of 'wakeup-pins' prop which type is 'phandles'
- * @return node identifier with that path.
- */
-#define SYSTEM_DT_NODE_WAKEUP_PIN_BY_IDX(i) \
-	DT_PHANDLE_BY_IDX(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_pins, i)
-
-/**
- * @brief Get the enum using in chromium system by index i in 'wakeup-pins'
- *        list.
- *
- * @param i index of 'wakeup-pins' prop which type is 'phandles'
- * @return GPIO enumeration
- */
-#define SYSTEM_DT_WAKEUP_GPIO_ENUM_BY_IDX(i, _)                           \
-	COND_CODE_1(DT_NODE_HAS_PROP(SYSTEM_DT_NODE_WAKEUP_PIN_BY_IDX(i), \
-				     enum_name),                          \
-		    (GPIO_SIGNAL(SYSTEM_DT_NODE_WAKEUP_PIN_BY_IDX(i)), ), ())
-
-/**
- * @typedef cros_system_get_reset_cause_api
- * @brief Callback API for getting reset cause instance.
- * See cros_system_get_reset_cause() for argument descriptions
- */
-typedef int (*cros_system_get_reset_cause_api)(const struct device *dev);
-
-/**
- * @typedef cros_system_soc_reset_api
- * @brief Callback API for soc-reset instance.
- * See cros_system_soc_reset() for argument descriptions
- */
-typedef int (*cros_system_soc_reset_api)(const struct device *dev);
-
-/**
- * @typedef cros_system_hibernate_api
- * @brief Callback API for entering hibernate state (lowest EC power state).
- * See cros_system_hibernate() for argument descriptions
- */
-typedef int (*cros_system_hibernate_api)(const struct device *dev,
-					 uint32_t seconds,
-					 uint32_t microseconds);
-
-/**
- * @typedef cros_system_chip_vendor_api
- * @brief Callback API for getting the chip vendor.
- * See cros_system_chip_vendor() for argument descriptions
- */
-typedef const char *(*cros_system_chip_vendor_api)(const struct device *dev);
-
-/**
- * @typedef cros_system_chip_name_api
- * @brief Callback API for getting the chip name.
- * See cros_system_chip_name() for argument descriptions
- */
-typedef const char *(*cros_system_chip_name_api)(const struct device *dev);
-
-/**
- * @typedef cros_system_chip_revision_api
- * @brief Callback API for getting the chip revision.
- * See cros_system_chip_revision() for argument descriptions
- */
-typedef const char *(*cros_system_chip_revision_api)(const struct device *dev);
-
-/**
- * @typedef cros_system_get_deep_sleep_ticks_api
- * @brief Callback API for getting number of ticks spent in deep sleep.
- * See cros_system_deep_sleep_ticks() for argument descriptions
- */
-typedef uint64_t (*cros_system_deep_sleep_ticks_api)(const struct device *dev);
-
-/** @brief Driver API structure. */
-__subsystem struct cros_system_driver_api {
-	cros_system_get_reset_cause_api get_reset_cause;
-	cros_system_soc_reset_api soc_reset;
-	cros_system_hibernate_api hibernate;
-	cros_system_chip_vendor_api chip_vendor;
-	cros_system_chip_name_api chip_name;
-	cros_system_chip_revision_api chip_revision;
-	cros_system_deep_sleep_ticks_api deep_sleep_ticks;
-};
-
-/**
- * @brief Get the chip-reset cause
- *
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval non-negative if successful.
- * @retval Negative errno code if failure.
- */
-__syscall int cros_system_get_reset_cause(const struct device *dev);
-
-static inline int z_impl_cros_system_get_reset_cause(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->get_reset_cause) {
-		return -ENOTSUP;
-	}
-
-	return api->get_reset_cause(dev);
-}
-
-/**
- * @brief reset the soc
- *
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval no return if successful.
- * @retval Negative errno code if failure.
- */
-__syscall int cros_system_soc_reset(const struct device *dev);
-
-static inline int z_impl_cros_system_soc_reset(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->soc_reset) {
-		return -ENOTSUP;
-	}
-
-	return api->soc_reset(dev);
-}
-
-/**
- * @brief put the EC in hibernate (lowest EC power state).
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @param seconds Number of seconds before EC enters hibernate state.
- * @param microseconds Number of micro-secs before EC enters hibernate state.
-
- * @retval no return if successful.
- * @retval Negative errno code if failure.
- */
-__syscall int cros_system_hibernate(const struct device *dev, uint32_t seconds,
-				    uint32_t microseconds);
-
-static inline int z_impl_cros_system_hibernate(const struct device *dev,
-					       uint32_t seconds,
-					       uint32_t microseconds)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->hibernate) {
-		return -ENOTSUP;
-	}
-
-	return api->hibernate(dev, seconds, microseconds);
-}
-
-/**
- * @brief Get the chip vendor.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @retval Chip vendor string if successful.
- * @retval Null string if failure.
- */
-__syscall const char *cros_system_chip_vendor(const struct device *dev);
-
-static inline const char *
-z_impl_cros_system_chip_vendor(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->chip_vendor) {
-		return "";
-	}
-
-	return api->chip_vendor(dev);
-}
-
-/**
- * @brief Get the chip name.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @retval Chip name string if successful.
- * @retval Null string if failure.
- */
-__syscall const char *cros_system_chip_name(const struct device *dev);
-
-static inline const char *z_impl_cros_system_chip_name(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->chip_name) {
-		return "";
-	}
-
-	return api->chip_name(dev);
-}
-
-/**
- * @brief Get the chip revision.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @retval Chip revision string if successful.
- * @retval Null string if failure.
- */
-__syscall const char *cros_system_chip_revision(const struct device *dev);
-
-static inline const char *
-z_impl_cros_system_chip_revision(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->chip_revision) {
-		return "";
-	}
-
-	return api->chip_revision(dev);
-}
-
-/**
- * @brief Get total number of ticks spent in deep sleep.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @retval Number of ticks spent in deep sleep.
- */
-__syscall uint64_t cros_system_deep_sleep_ticks(const struct device *dev);
-
-static inline uint64_t
-z_impl_cros_system_deep_sleep_ticks(const struct device *dev)
-{
-	const struct cros_system_driver_api *api =
-		(const struct cros_system_driver_api *)dev->api;
-
-	if (!api->deep_sleep_ticks) {
-		return 0;
-	}
-
-	return api->deep_sleep_ticks(dev);
-}
-
-/**
- * @}
- */
-#include <syscalls/cros_system.h>
-#endif /* ZEPHYR_INCLUDE_DRIVERS_CROS_SYSTEM_H_ */
diff --git a/zephyr/include/dt-bindings/charger/intersil_isl9241.h b/zephyr/include/dt-bindings/charger/intersil_isl9241.h
deleted file mode 100644
index 5a2742570e..0000000000
--- a/zephyr/include/dt-bindings/charger/intersil_isl9241.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_
-
-#define SWITCHING_FREQ_1420KHZ 0
-#define SWITCHING_FREQ_1180KHZ 1
-#define SWITCHING_FREQ_1020KHZ 2
-#define SWITCHING_FREQ_890KHZ  3
-#define SWITCHING_FREQ_808KHZ  4
-#define SWITCHING_FREQ_724KHZ  5
-#define SWITCHING_FREQ_656KHZ  6
-#define SWITCHING_FREQ_600KHZ  7
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_ */
diff --git a/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h b/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h
deleted file mode 100644
index f88efed949..0000000000
--- a/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_ITE_CROS_KB_RAW_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_ITE_CROS_KB_RAW_H_
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_ITE_CROS_KB_RAW_H_ */
diff --git a/zephyr/include/dt-bindings/cros-kb-raw/npcx_cros_kb_raw.h b/zephyr/include/dt-bindings/cros-kb-raw/npcx_cros_kb_raw.h
deleted file mode 100644
index f979ae8481..0000000000
--- a/zephyr/include/dt-bindings/cros-kb-raw/npcx_cros_kb_raw.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2020 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_NPCX_CROS_KB_RAW_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_NPCX_CROS_KB_RAW_H_
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CROS_KB_RAW_NPCX_CROS_KB_RAW_H_ */
diff --git a/zephyr/include/dt-bindings/gpio_defines.h b/zephyr/include/dt-bindings/gpio_defines.h
deleted file mode 100644
index 37552b8d6c..0000000000
--- a/zephyr/include/dt-bindings/gpio_defines.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2020 Google LLC.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef DT_BINDINGS_GPIO_DEFINES_H_
-#define DT_BINDINGS_GPIO_DEFINES_H_
-
-#include <dt-bindings/gpio/gpio.h>
-
-/*
- * The GPIO_INPUT and GPIO_OUTPUT defines are normally not available to
- * the device tree. For GPIOs that are controlled by the platform/ec module, we
- * allow device tree to set the initial state.
- *
- * Note the raw defines (e.g. GPIO_OUTPUT) in this file are copies from
- * <drivers/gpio.h>
- *
- * The combined defined (e.g. GPIO_OUT_LOW) have been renamed to fit with
- * gpio defined in platform/ec codebase.
- */
-
-/** Enables pin as input. */
-#define GPIO_INPUT              (1U << 8)
-
-/** Enables pin as output, no change to the output state. */
-#define GPIO_OUTPUT             (1U << 9)
-
-/* Initializes output to a low state. */
-#define GPIO_OUTPUT_INIT_LOW    (1U << 10)
-
-/* Initializes output to a high state. */
-#define GPIO_OUTPUT_INIT_HIGH   (1U << 11)
-
-/* Configures GPIO pin as output and initializes it to a low state. */
-#define GPIO_OUTPUT_LOW         (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
-
-/* Configures GPIO pin as output and initializes it to a high state. */
-#define GPIO_OUTPUT_HIGH        (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
-
-/* Configures GPIO pin as input with pull-up. */
-#define GPIO_INPUT_PULL_UP      (GPIO_INPUT | GPIO_PULL_UP)
-
-/* Configures GPIO pin as input with pull-down. */
-#define GPIO_INPUT_PULL_DOWN    (GPIO_INPUT | GPIO_PULL_DOWN)
-
-/** Configures GPIO pin as output and initializes it to a low state. */
-#define GPIO_OUT_LOW         (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
-
-/** Configures GPIO pin as output and initializes it to a high state. */
-#define GPIO_OUT_HIGH        (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
-
-/** Configures GPIO pin as ODR output and initializes it to a low state. */
-#define GPIO_ODR_LOW (GPIO_OUT_LOW | GPIO_OPEN_DRAIN)
-
-/** Configures GPIO pin as ODR output and initializes it to a high state. */
-#define GPIO_ODR_HIGH (GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
-
-#endif /* DT_BINDINGS_GPIO_DEFINES_H_ */
diff --git a/zephyr/include/dt-bindings/motionsense/utils.h b/zephyr/include/dt-bindings/motionsense/utils.h
deleted file mode 100644
index 7f0e5f5fc8..0000000000
--- a/zephyr/include/dt-bindings/motionsense/utils.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2021 Google LLC.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DT_BINDINGS_UTILS_H
-#define DT_BINDINGS_UTILS_H
-
-#define BIT(x)			(1U << (x))
-#define ROUND_UP_FLAG		BIT(31)
-#define USEC_PER_MSEC		1000
-
-#endif /* DT_BINDINGS_UTILS_H */
diff --git a/zephyr/include/dt-bindings/wake_mask_event_defines.h b/zephyr/include/dt-bindings/wake_mask_event_defines.h
deleted file mode 100644
index 0413fa249c..0000000000
--- a/zephyr/include/dt-bindings/wake_mask_event_defines.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2021 Google LLC.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_
-#define DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_
-
-#ifndef BIT
-#define BIT(n) (1U << n)
-#endif
-
-/*
- * NOTE: The convention in the Zephyr code is to have the public header file
- * include the dt-binding header file to avoid duplicate definitions.
- * However, ec_commands.h is shared with the linux kernel so we can't do that.
- *
- * Please consult include/ec_commands.h for explanations of the macros
- * defined in this file.
- */
-
-#define MKBP_EVENT_KEY_MATRIX		BIT(0)
-#define MKBP_EVENT_HOST_EVENT		BIT(1)
-#define MKBP_EVENT_SENSOR_FIFO		BIT(2)
-#define MKBP_EVENT_BUTTON		BIT(3)
-#define MKBP_EVENT_SWITCH		BIT(4)
-#define MKBP_EVENT_FINGERPRINT		BIT(5)
-#define MKBP_EVENT_SYSRQ		BIT(6)
-#define MKBP_EVENT_HOST_EVENT64		BIT(7)
-#define MKBP_EVENT_CEC_EVENT		BIT(8)
-#define MKBP_EVENT_CEC_MESSAGE		BIT(9)
-#define MKBP_EVENT_DP_ALT_MODE_ENTERED	BIT(10)
-#define MKBP_EVENT_ONLINE_CALIBRATION	BIT(11)
-#define MKBP_EVENT_PCHG			BIT(12)
-
-#define HOST_EVENT_MASK(event)		((event) >> 1)
-
-#define HOST_EVENT_NONE			BIT(0)
-#define HOST_EVENT_LID_CLOSED		BIT(1)
-#define HOST_EVENT_LID_OPEN		BIT(2)
-#define HOST_EVENT_POWER_BUTTON		BIT(3)
-#define HOST_EVENT_AC_CONNECTED		BIT(4)
-#define HOST_EVENT_AC_DISCONNECTED	BIT(5)
-#define HOST_EVENT_BATTERY_LOW		BIT(6)
-#define HOST_EVENT_BATTERY_CRITICAL	BIT(7)
-#define HOST_EVENT_BATTERY		BIT(8)
-#define HOST_EVENT_THERMAL_THRESHOLD	BIT(9)
-#define HOST_EVENT_DEVICE		BIT(10)
-#define HOST_EVENT_THERMAL		BIT(11)
-#define HOST_EVENT_USB_CHARGER		BIT(12)
-#define HOST_EVENT_KEY_PRESSED		BIT(13)
-#define HOST_EVENT_INTERFACE_READY	BIT(14)
-#define HOST_EVENT_KEYBOARD_RECOVERY	BIT(15)
-#define HOST_EVENT_THERMAL_SHUTDOWN	BIT(16)
-#define HOST_EVENT_BATTERY_SHUTDOWN	BIT(17)
-#define HOST_EVENT_THROTTLE_START	BIT(18)
-#define HOST_EVENT_THROTTLE_STOP	BIT(19)
-#define HOST_EVENT_HANG_DETECT		BIT(20)
-#define HOST_EVENT_HANG_REBOOT		BIT(21)
-#define HOST_EVENT_PD_MCU		BIT(22)
-#define HOST_EVENT_BATTERY_STATUS	BIT(23)
-#define HOST_EVENT_PANIC		BIT(24)
-#define HOST_EVENT_KEYBOARD_FASTBOOT	BIT(25)
-#define HOST_EVENT_RTC			BIT(26)
-#define HOST_EVENT_MKBP			BIT(27)
-#define HOST_EVENT_USB_MUX		BIT(28)
-#define HOST_EVENT_MODE_CHANGE		BIT(29)
-#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT	BIT(30)
-#define HOST_EVENT_WOV			BIT(31)
-#define HOST_EVENT_INVALID		BIT(32)
-
-#endif /* DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_ */
-
diff --git a/zephyr/include/emul/emul_bb_retimer.h b/zephyr/include/emul/emul_bb_retimer.h
deleted file mode 100644
index c63cc651c0..0000000000
--- a/zephyr/include/emul/emul_bb_retimer.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for BB retimer emulator
- */
-
-#ifndef __EMUL_BB_RETIMER_H
-#define __EMUL_BB_RETIMER_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief BB retimer emulator backend API
- * @defgroup bb_emul BB retimer emulator
- * @{
- *
- * BB retimer emulator supports access to all its registers using I2C messages.
- * It supports not four bytes writes by padding zeros (the same as real
- * device), but show warning in that case.
- * Application may alter emulator state:
- *
- * - define a Device Tree overlay file to set default vendor ID and which
- *   inadvisable driver behaviour should be treated as errors
- * - call @ref bb_emul_set_reg and @ref bb_emul_get_reg to set and get value
- *   of BB retimers registers
- * - call bb_emul_set_err_* to change emulator behaviour on inadvisable driver
- *   behaviour
- * - call functions from emul_common_i2c.h to setup custom handlers for I2C
- *   messages
- */
-
-/**
- * @brief Get pointer to BB retimer emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BB retimer emulator
- */
-struct i2c_emul *bb_emul_get(int ord);
-
-/**
- * @brief Set value of given register of BB retimer
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg Register address which value will be changed
- * @param val New value of the register
- */
-void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val);
-
-/**
- * @brief Get value of given register of BB retimer
- *
- * @param emul Pointer to BB retimer emulator
- * @param reg Register address
- *
- * @return Value of the register
- */
-uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Set if error should be generated when read only register is being
- *        written
- *
- * @param emul Pointer to BB retimer emulator
- * @param set Check for this error
- */
-void bb_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when reserved bits of register are
- *        not set to 0 on write I2C message
- *
- * @param emul Pointer to BB retimer emulator
- * @param set Check for this error
- */
-void bb_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_BB_RETIMER */
diff --git a/zephyr/include/emul/emul_bma255.h b/zephyr/include/emul/emul_bma255.h
deleted file mode 100644
index b2f71df88b..0000000000
--- a/zephyr/include/emul/emul_bma255.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for BMA255 emulator
- */
-
-#ifndef __EMUL_BMA255_H
-#define __EMUL_BMA255_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief BMA255 emulator backend API
- * @defgroup bma_emul BMA255 emulator
- * @{
- *
- * BMA255 emulator supports responses to all write and read I2C messages.
- * Accelerometer registers are obtained from internal emulator state, range
- * register and offset. Only fast compensation is supported by default handler.
- * Registers backed in NVM are fully supported (GP0, GP1, offset). For proper
- * support for interrupts and FIFO, user needs to use custom handlers.
- * Application may alter emulator state:
- *
- * - define a Device Tree overlay file to set default NVM content, default
- *   static accelerometer value and which inadvisable driver behaviour should
- *   be treated as errors
- * - call @ref bma_emul_set_reg and @ref bma_emul_get_reg to set and get value
- *   of BMA255 registers
- * - call @ref bma_emul_set_off and @ref bma_emul_set_off to set and get
- *   internal offset value
- * - call @ref bma_emul_set_acc and @ref bma_emul_set_acc to set and get
- *   accelerometer value
- * - call bma_emul_set_err_* to change emulator behaviour on inadvisable driver
- *   behaviour
- * - call functions from emul_common_i2c.h to setup custom handlers for I2C
- *   messages
- */
-
-/**
- * Axis argument used in @ref bma_emul_set_acc @ref bma_emul_get_acc
- * @ref bma_emul_set_off and @ref bma_emul_get_off
- */
-#define BMA_EMUL_AXIS_X		0
-#define BMA_EMUL_AXIS_Y		1
-#define BMA_EMUL_AXIS_Z		2
-
-/**
- * Acceleration 1g in internal emulator units. It is helpful for using
- * functions @ref bma_emul_set_acc @ref bma_emul_get_acc
- * @ref bma_emul_set_off and @ref bma_emul_get_off
- */
-#define BMA_EMUL_1G		BIT(10)
-
-/**
- * @brief Get pointer to BMA255 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BMA255 emulator
- */
-struct i2c_emul *bma_emul_get(int ord);
-
-/**
- * @brief Set value of given register of BMA255
- *
- * @param emul Pointer to BMA255 emulator
- * @param reg Register address which value will be changed
- * @param val New value of the register
- */
-void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
-
-/**
- * @brief Get value of given register of BMA255
- *
- * @param emul Pointer to BMA255 emulator
- * @param reg Register address
- *
- * @return Value of the register
- */
-uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Get internal value of offset for given axis
- *
- * @param emul Pointer to BMA255 emulator
- * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
- *
- * @return Offset of given axis. LSB is 0.97mg
- */
-int16_t bma_emul_get_off(struct i2c_emul *emul, int axis);
-
-/**
- * @brief Set internal value of offset for given axis
- *
- * @param emul Pointer to BMA255 emulator
- * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
- * @param val New value of offset. LSB is 0.97mg
- */
-void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val);
-
-/**
- * @brief Get internal value of accelerometer for given axis
- *
- * @param emul Pointer to BMA255 emulator
- * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
- *
- * @return Acceleration of given axis. LSB is 0.97mg
- */
-int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis);
-
-/**
- * @brief Set internal value of accelerometr for given axis
- *
- * @param emul Pointer to BMA255 emulator
- * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
- * @param val New value of accelerometer axis. LSB is 0.97mg
- */
-void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val);
-
-/**
- * @brief Set if error should be generated when fast compensation is triggered
- *        when not ready flag is set
- *
- * @param emul Pointer to BMA255 emulator
- * @param set Check for this error
- */
-void bma_emul_set_err_on_cal_nrdy(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when fast compensation is triggered
- *        when range is not 2G
- *
- * @param emul Pointer to BMA255 emulator
- * @param set Check for this error
- */
-void bma_emul_set_err_on_cal_bad_range(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when read only register is being
- *        written
- *
- * @param emul Pointer to BMA255 emulator
- * @param set Check for this error
- */
-void bma_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when reserved bits of register are
- *        not set to 0 on write I2C message
- *
- * @param emul Pointer to BMA255 emulator
- * @param set Check for this error
- */
-void bma_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when MSB register is accessed before
- *        LSB register
- *
- * @param emul Pointer to BMA255 emulator
- * @param set Check for this error
- */
-void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Function calculate register that should be accessed when I2C message
- *        started from @p reg register and now byte number @p bytes is handled.
- *        This function is used in I2C common emulator code and can be used in
- *        custom user functions.
- *
- * @param emul Pointer to BMA255 emulator
- * @param reg Starting register
- * @param bytes Number of bytes already processed in the I2C message handler
- * @param read If current I2C message is read
- *
- * @retval Register address that should be accessed
- */
-int bma_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, bool read);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_BMA255_H */
diff --git a/zephyr/include/emul/emul_bmi.h b/zephyr/include/emul/emul_bmi.h
deleted file mode 100644
index 9eac9c3f85..0000000000
--- a/zephyr/include/emul/emul_bmi.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for BMI emulator
- */
-
-#ifndef __EMUL_BMI_H
-#define __EMUL_BMI_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief BMI emulator backend API
- * @defgroup bmi_emul BMI emulator
- * @{
- *
- * BMI emulator supports responses to all write and read I2C messages.
- * Accelerometer and gyroscope registers are obtained from internal emulator
- * state, range register and offset. FIFO is fully simulated. Emulator can be
- * extended to support more models of BMI.
- * Application may alter emulator state:
- *
- * - define a Device Tree overlay file to set which inadvisable driver behaviour
- *   should be treated as errors and which model is emulated
- * - call @ref bmi_emul_set_reg and @ref bmi_emul_get_reg to set and get value
- *   of BMI registers
- * - call @ref bmi_emul_set_off and @ref bmi_emul_get_off to set and get
- *   internal offset value
- * - call @ref bmi_emul_set_value and @ref bmi_emul_get_value to set and get
- *   accelerometer or gyroscope value
- * - call bmi_emul_set_err_* to change emulator behaviour on inadvisable driver
- *   behaviour
- * - call @ref bmi_emul_simulate_cmd_exec_time to enable or disable simulation
- *   of command execution time
- * - call @ref bmi_emul_append_frame to add frame to FIFO
- * - call @reg bmi_emul_set_skipped_frames to generate skip frame on next access
- *   to FIFO
- * - call functions from emul_common_i2c.h to setup custom handlers for I2C
- *   messages
- */
-
-/**
- * Axis argument used in @ref bmi_emul_set_value @ref bmi_emul_get_value
- * @ref bmi_emul_set_off and @ref bmi_emul_get_off
- */
-enum bmi_emul_axis {
-	BMI_EMUL_ACC_X,
-	BMI_EMUL_ACC_Y,
-	BMI_EMUL_ACC_Z,
-	BMI_EMUL_GYR_X,
-	BMI_EMUL_GYR_Y,
-	BMI_EMUL_GYR_Z,
-};
-
-/** BMI emulator models */
-#define BMI_EMUL_160		1
-#define BMI_EMUL_260		2
-
-/** Last register supported by emulator */
-#define BMI_EMUL_MAX_REG	0x80
-/** Maximum number of registers that can be backed in NVM */
-#define BMI_EMUL_MAX_NVM_REGS	10
-
-/** Headers used in FIFO frames */
-#define BMI_EMUL_FIFO_HEAD_SKIP			0x40
-#define BMI_EMUL_FIFO_HEAD_TIME			0x44
-#define BMI_EMUL_FIFO_HEAD_CONFIG		0x48
-#define BMI_EMUL_FIFO_HEAD_EMPTY		0x80
-#define BMI_EMUL_FIFO_HEAD_DATA			0x80
-#define BMI_EMUL_FIFO_HEAD_DATA_MAG		BIT(4)
-#define BMI_EMUL_FIFO_HEAD_DATA_GYR		BIT(3)
-#define BMI_EMUL_FIFO_HEAD_DATA_ACC		BIT(2)
-#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK	0x03
-
-/**
- * Acceleration 1g in internal emulator units. It is helpful for using
- * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
- * @ref bmi_emul_set_off and @ref bmi_emul_get_off
- */
-#define BMI_EMUL_1G		BIT(14)
-/**
- * Gyroscope 125°/s in internal emulator units. It is helpful for using
- * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
- * @ref bmi_emul_set_off and @ref bmi_emul_get_off
- */
-#define BMI_EMUL_125_DEG_S	BIT(15)
-
-/** Type of frames that can be added to the emulator frames list */
-#define BMI_EMUL_FRAME_CONFIG	BIT(0)
-#define BMI_EMUL_FRAME_ACC	BIT(1)
-#define BMI_EMUL_FRAME_MAG	BIT(2)
-#define BMI_EMUL_FRAME_GYR	BIT(3)
-
-/**
- * Code returned by model specific handle_read and handle_write functions, when
- * RO register is accessed on write or WO register is accessed on read
- */
-#define BMI_EMUL_ACCESS_E	1
-
-/** Structure used to describe single FIFO frame */
-struct bmi_emul_frame {
-	/** Type of frame */
-	uint8_t type;
-	/** Tag added to data frame */
-	uint8_t tag;
-	/** Value used in config frame */
-	uint8_t config;
-	/** Accelerometer sensor values in internal emulator units */
-	int32_t acc_x;
-	int32_t acc_y;
-	int32_t acc_z;
-	/** Gyroscope sensor values in internal emulator units */
-	int32_t gyr_x;
-	int32_t gyr_y;
-	int32_t gyr_z;
-	/** Magnetometer/other sensor values in internal emulator units */
-	int32_t mag_x;
-	int32_t mag_y;
-	int32_t mag_z;
-	int32_t rhall;
-
-	/** Pointer to next frame or NULL */
-	struct bmi_emul_frame *next;
-};
-
-/** Structure describing specific BMI model */
-struct bmi_emul_type_data {
-	/** Indicate if time frame should follow config frame */
-	bool sensortime_follow_config_frame;
-
-	/**
-	 * @brief Compute register address that acctually will be accessed, when
-	 *        selected register is @p reg and there was @p byte handled in
-	 *        the current I2C message
-	 *
-	 * @param emul Pointer to BMI emulator
-	 * @param reg Selected register
-	 * @param byte Number of handled bytes in the current I2C message
-	 * @param read If current I2C message is read
-	 *
-	 * @return Register address that will be accessed
-	 */
-	int (*access_reg)(struct i2c_emul *emul, int reg, int byte, bool read);
-
-	/**
-	 * @brief Model specific write function. It should modify state of
-	 *        emulator if required.
-	 *
-	 * @param regs Pointer to array of emulator's registers
-	 * @param emul Pointer to BMI emulator
-	 * @param reg Selected register
-	 * @param byte Number of handled bytes in this write command
-	 * @param val Value that is being written
-	 *
-	 * @return 0 on success
-	 * @return BMI_EMUL_ACCESS_E on RO register access
-	 * @return other on error
-	 */
-	int (*handle_write)(uint8_t *regs, struct i2c_emul *emul, int reg,
-			    int byte, uint8_t val);
-	/**
-	 * @brief Model specific read function. It should modify state of
-	 *        emulator if required. @p buf should be set to response value.
-	 *
-	 * @param regs Pointer to array of emulator's registers
-	 * @param emul Pointer to BMI emulator
-	 * @param reg Selected register
-	 * @param byte Byte which is accessed during block read
-	 * @param buf Pointer where read byte should be stored
-	 *
-	 * @return 0 on success
-	 * @return BMI_EMUL_ACCESS_E on WO register access
-	 * @return other on error
-	 */
-	int (*handle_read)(uint8_t *regs, struct i2c_emul *emul, int reg,
-			   int byte, char *buf);
-	/**
-	 * @brief Model specific reset function. It should modify state of
-	 *        emulator to imitate after reset conditions.
-	 *
-	 * @param regs Pointer to array of emulator's registers
-	 * @param emul Pointer to BMI emulator
-	 */
-	void (*reset)(uint8_t *regs, struct i2c_emul *emul);
-
-	/** Array of reserved bits mask for each register */
-	const uint8_t *rsvd_mask;
-
-	/** Array of registers that are backed in NVM */
-	const int *nvm_reg;
-	/** Number of registers backed in NVM */
-	int nvm_len;
-
-	/** Gyroscope X axis register */
-	int gyr_off_reg;
-	/** Accelerometer X axis register */
-	int acc_off_reg;
-	/** Gyroscope 9 and 8 bits register */
-	int gyr98_off_reg;
-};
-
-/**
- * @brief Get BMI160 model specific structure.
- *
- * @return Pointer to BMI160 specific structure
- */
-const struct bmi_emul_type_data *get_bmi160_emul_type_data(void);
-/**
- * @brief Get BMI260 model specific structure.
- *
- * @return Pointer to BMI260 specific structure
- */
-const struct bmi_emul_type_data *get_bmi260_emul_type_data(void);
-
-/**
- * @brief Get pointer to BMI emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BMI emulator
- */
-struct i2c_emul *bmi_emul_get(int ord);
-
-/**
- * @brief Set value of given register of BMI
- *
- * @param emul Pointer to BMI emulator
- * @param reg Register address which value will be changed
- * @param val New value of the register
- */
-void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
-
-/**
- * @brief Get value of given register of BMI
- *
- * @param emul Pointer to BMI emulator
- * @param reg Register address
- *
- * @return Value of the register
- */
-uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Get internal value of offset for given axis and sensor
- *
- * @param emul Pointer to BMI emulator
- * @param axis Axis to access
- *
- * @return Offset of given axis. LSB for accelerometer is 0.061mg and for
- *         gyroscope is 0.0037°/s.
- */
-int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis);
-
-/**
- * @brief Set internal value of offset for given axis and sensor
- *
- * @param emul Pointer to BMI emulator
- * @param axis Axis to access
- * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
- *            gyroscope is 0.0037°/s.
- */
-void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
-		      int16_t val);
-
-/**
- * @brief Get internal value of sensor for given axis
- *
- * @param emul Pointer to BMI emulator
- * @param axis Axis to access
- *
- * @return Sensor value of given axis. LSB for accelerometer is 0.061mg and for
- *         gyroscope is 0.0037°/s.
- */
-int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis);
-
-/**
- * @brief Set internal value of sensor for given axis
- *
- * @param emul Pointer to BMI emulator
- * @param axis Axis to access
- * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
- *            gyroscope is 0.0037°/s.
- */
-void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
-			int32_t val);
-
-/**
- * @brief Set if error should be generated when read only register is being
- *        written
- *
- * @param emul Pointer to BMI emulator
- * @param set Check for this error
- */
-void bmi_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when reserved bits of register are
- *        not set to 0 on write I2C message
- *
- * @param emul Pointer to BMI emulator
- * @param set Check for this error
- */
-void bmi_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when write only register is read
- *
- * @param emul Pointer to BMI emulator
- * @param set Check for this error
- */
-void bmi_emul_set_err_on_wo_read(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if effect of simulated command should take place after simulated
- *        time pass from issuing command.
- *
- * @param emul Pointer to BMI emulator
- * @param set Simulate command execution time
- */
-void bmi_emul_simulate_cmd_exec_time(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set number of skipped frames. It will generate skip frame on next
- *        access to FIFO. After that number of skipped frames is reset to 0.
- *
- * @param emul Pointer to BMI emulator
- * @param skip Number of skipped frames
- */
-void bmi_emul_set_skipped_frames(struct i2c_emul *emul, uint8_t skip);
-
-/**
- * @brief Clear all FIFO frames, set current frame to empty and reset fifo_skip
- *        counter
- *
- * @param emul Pointer to BMI emulator
- * @param tag_time Indicate if sensor time should be included in empty frame
- * @param header Indicate if header should be included in frame
- */
-void bmi_emul_flush_fifo(struct i2c_emul *emul, bool tag_time, bool header);
-
-/**
- * @brief Restore registers backed by NVM, reset sensor time and flush FIFO
- *
- * @param emul Pointer to BMI emulator
- */
-void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header);
-
-/**
- * @brief Set command end time to @p time ms from now
- *
- * @param emul Pointer to BMI emulator
- * @param time After this amount of ms command should end
- */
-void bmi_emul_set_cmd_end_time(struct i2c_emul *emul, int time);
-
-/**
- * @brief Check if command should end
- *
- * @param emul Pointer to BMI emulator
- */
-bool bmi_emul_is_cmd_end(struct i2c_emul *emul);
-
-/**
- * @brief Append FIFO @p frame to the emulator list of frames. It can be read
- *        using I2C interface.
- *
- * @param emul Pointer to BMI emulator
- * @param frame Pointer to new FIFO frame. Pointed data has to be valid while
- *              emulator may use this frame (until flush of FIFO or reading
- *              it out through I2C)
- */
-void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame);
-
-/**
- * @brief Get length of all frames that are on the emulator list of frames.
- *
- * @param emul Pointer to BMI emulator
- * @param tag_time Indicate if sensor time should be included in empty frame
- * @param header Indicate if header should be included in frame
- */
-uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header);
-
-/**
- * @brief Get next byte that should be returned on FIFO data access.
- *
- * @param emul Pointer to BMI emulator
- * @param byte Which byte of block read command is currently handled
- * @param tag_time Indicate if sensor time should be included in empty frame
- * @param header Indicate if header should be included in frame
- * @param acc_shift How many bits should be right shifted from accelerometer
- *                  data
- * @param gyr_shift How many bits should be right shifted from gyroscope data
- *
- * @return FIFO data byte
- */
-uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
-			       bool tag_time, bool header, int acc_shift,
-			       int gyr_shift);
-
-/**
- * @brief Saves current internal state of sensors to emulator's registers.
- *
- * @param emul Pointer to BMI emulator
- * @param acc_shift How many bits should be right shifted from accelerometer
- *                  data
- * @param gyr_shift How many bits should be right shifted from gyroscope data
- * @param acc_reg Register which holds LSB of accelerometer sensor
- * @param gyr_reg Register which holds LSB of gyroscope sensor
- * @param sensortime_reg Register which holds LSB of sensor time
- * @param acc_off_en Indicate if accelerometer offset should be included to
- *                   sensor data value
- * @param gyr_off_en Indicate if gyroscope offset should be included to
- *                   sensor data value
- */
-void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift,
-			   int gyr_shift, int acc_reg, int gyr_reg,
-			   int sensortime_reg, bool acc_off_en,
-			   bool gyr_off_en);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_BMI_H */
diff --git a/zephyr/include/emul/emul_common_i2c.h b/zephyr/include/emul/emul_common_i2c.h
deleted file mode 100644
index 0457842a71..0000000000
--- a/zephyr/include/emul/emul_common_i2c.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Common code used by devices emulated on I2C bus
- */
-
-#ifndef __EMUL_COMMON_I2C_H
-#define __EMUL_COMMON_I2C_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief Common I2C API useb by emulators
- * @defgroup i2c_common_emul common I2C emulator's code
- * @{
- *
- * I2C common emulator functionality is dispatching I2C messages. It supports
- * setting custom user handler and selecting register on which access emulator
- * should fail. To use common I2C handling, emulator should call or setup
- * @ref i2c_common_emul_transfer as transfer callback of i2c_emul_api and
- * register emulator with @ref i2c_common_emul_data structure as data. In data
- * structure, emualtor should set callback called before read/write I2C message
- * (start_read, start_write), for each byte of I2C message (read_byte,
- * write_byte) and after I2C message (finish_read, finish_byte). If specific
- * function is not needed by emulator, than it can be set to NULL.
- *
- * @ref i2c_common_emul_lock_data and @ref i2c_common_emul_unlock_data functions
- * may be used to guard emulator data when accessed from multiple threads.
- *
- * User of emulator with common I2C code can use following API to define custom
- * behaviour of emulator:
- *
- * - call @ref i2c_common_emul_set_read_func and
- *   @ref i2c_common_emul_set_write_func to setup custom handlers for I2C
- *   messages
- * - call @ref i2c_common_emul_set_read_fail_reg and
- *   @ref i2c_common_emul_set_write_fail_reg to configure emulator to fail on
- *   given register read or write
- */
-
-/**
- * Special register values used in @ref i2c_common_emul_set_read_fail_reg and
- * @ref i2c_common_emul_set_write_fail_reg
- */
-#define I2C_COMMON_EMUL_FAIL_ALL_REG	(-1)
-#define I2C_COMMON_EMUL_NO_FAIL_REG	(-2)
-
-/**
- * Describe if there is no ongoing I2C message or if there is message handled
- * at the moment (last message doesn't ended with stop or write is not followed
- * by read).
- */
-enum i2c_common_emul_msg_state {
-	I2C_COMMON_EMUL_NONE_MSG,
-	I2C_COMMON_EMUL_IN_WRITE,
-	I2C_COMMON_EMUL_IN_READ
-};
-
-/**
- * @brief Function type that is used by I2C device emulator for first byte of
- *        I2C write message.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by write command (first byte of I2C
- *            write message)
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_start_write_func)(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Function type that is used by I2C device emulator at the end of
- *        I2C write message.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by write command (first byte of I2C
- *            write message)
- * @param bytes Number of bytes received from the I2C write message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_finish_write_func)(struct i2c_emul *emul, int reg,
-						 int bytes);
-
-/**
- * @brief Function type that is used by I2C device emulator on each byte of
- *        I2C write message (except first byte).
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by write command (first byte of I2C
- *            write message)
- * @param val Value of current byte
- * @param bytes Number of bytes already received from the I2C write message
- *              (excluding current byte)
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_write_byte_func)(struct i2c_emul *emul, int reg,
-					       uint8_t val, int bytes);
-
-/**
- * @brief Function type that is used by I2C device emulator before first byte of
- *        I2C read message.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by read command (first byte of last
- *            I2C write message)
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_start_read_func)(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Function type that is used by I2C device emulator at the end of
- *        I2C read message.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by read command (first byte of last
- *            I2C write message)
- * @param bytes Number of bytes responeded to the I2C read message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_finish_read_func)(struct i2c_emul *emul, int reg,
-						int bytes);
-
-/**
- * @brief Function type that is used by I2C device emulator on each byte of
- *        I2C read message.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by read command (first byte of last
- *            I2C write message)
- * @param val Pointer to buffer where current response byte should be stored
- * @param bytes Number of bytes already responded to the I2C read message
- *              (excluding current byte)
- *
- * @return 0 on success
- * @return -EIO on error
- */
-typedef int (*i2c_common_emul_read_byte_func)(struct i2c_emul *emul, int reg,
-					      uint8_t *val, int bytes);
-
-/**
- * @brief Function type that is used by I2C device emulator to select register
- *        address that should be compared with fail register set by user using
- *        @ref i2c_common_emul_set_read_fail_reg and
- *        @ref i2c_common_emul_set_write_fail_reg
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by read/write command (first byte
- *            of last I2C write message)
- * @param bytes Number of bytes already processed in the I2C message handler
- *              (excluding current byte)
- * @param read If current I2C message is read
- *
- * @return Register address that should be compared with user-defined fail
- *         register
- */
-typedef int (*i2c_common_emul_access_reg_func)(struct i2c_emul *emul, int reg,
-					       int bytes, bool read);
-
-/**
- * @brief Custom function type that is used as user-defined callback in read
- *        I2C messages handling.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by read command (first byte of last
- *            I2C write message)
- * @param val Pointer to buffer where current response byte should be stored
- * @param bytes Number of bytes already responded to the I2C read message
- *              (excluding current byte)
- * @param data Pointer to custom user data
- *
- * @return 0 on success
- * @return 1 continue with normal emulator handler
- * @return negative on error
- */
-typedef int (*i2c_common_emul_read_func)(struct i2c_emul *emul, int reg,
-					 uint8_t *val, int bytes, void *data);
-
-/**
- * @brief Custom function type that is used as user-defined callback in write
- *        I2C messages handling.
- *
- * @param emul Pointer to emulator
- * @param reg Address which is now accessed by write command (first byte of I2C
- *            write message)
- * @param val Value of current byte
- * @param bytes Number of bytes already received from the I2C write message
- *              (excluding current byte)
- * @param data Pointer to custom user data
- *
- * @return 0 on success
- * @return 1 continue with normal emulator handler
- * @return negative on error
- */
-typedef int (*i2c_common_emul_write_func)(struct i2c_emul *emul, int reg,
-					  uint8_t val, int bytes, void *data);
-
-/** Static configuration, common for all i2c emulators */
-struct i2c_common_emul_cfg {
-	/** Label of the I2C bus this emulator connects to */
-	const char *i2c_label;
-	/** Label of the I2C device being emulated */
-	const char *dev_label;
-	/** Pointer to run-time data */
-	struct i2c_common_emul_data *data;
-	/** Address of emulator on i2c bus */
-	uint16_t addr;
-};
-
-/** Run-time data used by the emulator, common for all i2c emulators */
-struct i2c_common_emul_data {
-	/** I2C emulator detail */
-	struct i2c_emul emul;
-	/** Emulator device */
-	const struct device *i2c;
-	/** Configuration information */
-	const struct i2c_common_emul_cfg *cfg;
-
-	/** Current state of I2C bus (if emulator is handling message) */
-	enum i2c_common_emul_msg_state msg_state;
-	/** Number of already handled bytes in ongoing message */
-	int msg_byte;
-	/** Register selected in last write command */
-	uint8_t cur_reg;
-
-	/** Custom write function called on I2C write opperation */
-	i2c_common_emul_write_func write_func;
-	/** Data passed to custom write function */
-	void *write_func_data;
-	/** Custom read function called on I2C read opperation */
-	i2c_common_emul_read_func read_func;
-	/** Data passed to custom read function */
-	void *read_func_data;
-
-	/** Control if read should fail on given register */
-	int read_fail_reg;
-	/** Control if write should fail on given register */
-	int write_fail_reg;
-
-	/** Emulator function, called for first byte of write message */
-	i2c_common_emul_start_write_func start_write;
-	/** Emulator function, called for each byte of write message */
-	i2c_common_emul_write_byte_func write_byte;
-	/** Emulator function, called at the end of write message */
-	i2c_common_emul_finish_write_func finish_write;
-
-	/** Emulator function, called before first byte of read message */
-	i2c_common_emul_start_read_func start_read;
-	/** Emulator function, called for each byte of read message */
-	i2c_common_emul_read_byte_func read_byte;
-	/** Emulator function, called at the end of read message */
-	i2c_common_emul_finish_read_func finish_read;
-
-	/**
-	 * Emulator function, called to get register that should be checked
-	 * if was selected by user in set_read/write_fail_reg.
-	 */
-	i2c_common_emul_access_reg_func access_reg;
-
-	/** Mutex used to control access to emulator data */
-	struct k_mutex data_mtx;
-};
-
-/**
- * @brief Lock access to emulator properties. After acquiring lock, user
- *        may change emulator behaviour in multi-thread setup.
- *
- * @param emul Pointer to emulator
- * @param timeout Timeout in getting lock
- *
- * @return k_mutex_lock return code
- */
-int i2c_common_emul_lock_data(struct i2c_emul *emul, k_timeout_t timeout);
-
-/**
- * @brief Unlock access to emulator properties.
- *
- * @param emul Pointer to emulator
- *
- * @return k_mutex_unlock return code
- */
-int i2c_common_emul_unlock_data(struct i2c_emul *emul);
-
-/**
- * @brief Set write handler for I2C messages. This function is called before
- *        generic handler.
- *
- * @param emul Pointer to emulator
- * @param func Pointer to custom function
- * @param data User data passed on call of custom function
- */
-void i2c_common_emul_set_write_func(struct i2c_emul *emul,
-				    i2c_common_emul_write_func func,
-				    void *data);
-
-/**
- * @brief Set read handler for I2C messages. This function is called before
- *        generic handler.
- *
- * @param emul Pointer to emulator
- * @param func Pointer to custom function
- * @param data User data passed on call of custom function
- */
-void i2c_common_emul_set_read_func(struct i2c_emul *emul,
-				   i2c_common_emul_read_func func, void *data);
-
-/**
- * @brief Setup fail on read of given register of emulator
- *
- * @param emul Pointer to emulator
- * @param reg Register address or one of special values
- *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
- */
-void i2c_common_emul_set_read_fail_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Setup fail on write of given register of emulator
- *
- * @param emul Pointer to emulator
- * @param reg Register address or one of special values
- *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
- */
-void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @biref Emulate an I2C transfer to an emulator
- *
- * This is common function used by I2C device emulators. It handles dispatching
- * I2C message, calling user custom functions, failing on reading/writing
- * registers selected by user and calling device specific functions.
- *
- * @param emul I2C emulation information
- * @param msgs List of messages to process
- * @param num_msgs Number of messages to process
- * @param addr Address of the I2C target device
- *
- * @retval 0 If successful
- * @retval -EIO General input / output error
- */
-int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-			     int num_msgs, int addr);
-
-/**
- * @brief Initialize common emulator data structure
- *
- * @param data Pointer to emulator data
- */
-void i2c_common_emul_init(struct i2c_common_emul_data *data);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_COMMON_I2C_H */
diff --git a/zephyr/include/emul/emul_lis2dw12.h b/zephyr/include/emul/emul_lis2dw12.h
deleted file mode 100644
index b136e24f0a..0000000000
--- a/zephyr/include/emul/emul_lis2dw12.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_
-#define ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_
-
-#include <emul.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief The the i2c emulator pointer from the top level emul.
- *
- * @param emul The emulator to query
- * @return Pointer to the i2c emulator struct
- */
-struct i2c_emul *lis2dw12_emul_to_i2c_emul(const struct emul *emul);
-
-/**
- * @brief Reset the state of the lis2dw12 emulator.
- *
- * @param emul The emulator to reset.
- */
-void lis2dw12_emul_reset(const struct emul *emul);
-
-/**
- * @brief Set the who-am-i register value.
- *
- * By default the who-am-i register holds LIS2DW12_WHO_AM_I, this function
- * enables overriding that value in order to drive testing.
- *
- * @param emul The emulator to modify.
- * @param who_am_i The new who-am-i register value.
- */
-void lis2dw12_emul_set_who_am_i(const struct emul *emul, uint8_t who_am_i);
-
-/**
- * @brief Check the number of times the chip was soft reset.
- *
- * This value is reset by a call to lis2dw12_emul_reset().
- *
- * @param emul The emulator to query
- * @return The number of times that the chip was reset.
- */
-uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul);
-
-#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_ */
diff --git a/zephyr/include/emul/emul_ln9310.h b/zephyr/include/emul/emul_ln9310.h
deleted file mode 100644
index dfa03eaa28..0000000000
--- a/zephyr/include/emul/emul_ln9310.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for LN9310 emulator
- */
-
-#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_
-#define ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_
-
-#include <emul.h>
-#include "driver/ln9310.h"
-#include <stdbool.h>
-
-/**
- * @brief Select the current emulator to use.
- *
- * Currently, only a single ln9310 can be instantiated at any given instance due
- * to how the driver was written. Once this restriction is removed, there's
- * still an issue with the board_get_battery_cell_type() function as it doesn't
- * take a device pointer. This function selects the current LN9310 context which
- * will serve the data for that board function.
- *
- * @param emulator The LN9310 emulator to select.
- */
-void ln9310_emul_set_context(const struct emul *emulator);
-
-/**
- * @brief Clear all the emulator data.
- *
- * @param emulator The LN9310 emulator to clear.
- */
-void ln9310_emul_reset(const struct emul *emulator);
-
-/**
- * @brief Update the emulator's battery cell type.
- *
- * @param emulator The LN9310 emulator to update.
- * @param type The battery type to use.
- */
-void ln9310_emul_set_battery_cell_type(const struct emul *emulator,
-				       enum battery_cell_type type);
-
-/**
- * @brief Update the emulator's version number.
- *
- * @param emulator The LN9310 emulator to update.
- * @param version The LN9310 chip version number.
- */
-void ln9310_emul_set_version(const struct emul *emulator, int version);
-
-/**
- * @brief Update whether or not the LN9310 is currently getting more than 10V.
- *
- * @param emulator The LN9310 emulator to update.
- * @param is_gt_10v Whether or not the chip is currently getting more than 10V.
- */
-void ln9310_emul_set_vin_gt_10v(const struct emul *emulator, bool is_gt_10v);
-
-/**
- * @brief Get whether or not the LN9310 is initialized.
- *
- * @param emulator The LN9310 emulator to read.
- *
- * @return true if the LN9310 was correctly initialized.
- */
-bool ln9310_emul_is_init(const struct emul *emulator);
-
-#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_ */
diff --git a/zephyr/include/emul/emul_pi3usb9201.h b/zephyr/include/emul/emul_pi3usb9201.h
deleted file mode 100644
index b171cfefc9..0000000000
--- a/zephyr/include/emul/emul_pi3usb9201.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for pi3usb9201 emulator
- */
-
-#ifndef __EMUL_PI3USB9201_H
-#define __EMUL_PI3USB9201_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-#define PI3USB9201_REG_CTRL_1 0x0
-#define PI3USB9201_REG_CTRL_2 0x1
-#define PI3USB9201_REG_CLIENT_STS 0x2
-#define PI3USB9201_REG_HOST_STS 0x3
-
-/**
- * @brief Get pointer to pi3usb9201 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to pi3usb9201 emulator
- */
-struct i2c_emul *pi3usb9201_emul_get(int ord);
-
-/**
- * @brief Set value of given register of pi3usb9201
- *
- * @param emul Pointer to pi3usb9201 emulator
- * @param reg Register address
- * @param val New value of the register
- *
- * @return 0 on success or error
- */
-int pi3usb9201_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
-
-/**
- * @brief Get value of given register of pi3usb9201
- *
- * @param emul Pointer to pi3usb9201 emulator
- * @param reg Register address
- * @param val Pointer to write current value of register
- *
- * @return 0 on success or error
- */
-int pi3usb9201_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val);
-
-#endif /* __EMUL_PI3USB9201_H */
diff --git a/zephyr/include/emul/emul_smart_battery.h b/zephyr/include/emul/emul_smart_battery.h
deleted file mode 100644
index b48f836d66..0000000000
--- a/zephyr/include/emul/emul_smart_battery.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for Smart Battery emulator
- */
-
-#ifndef __EMUL_SMART_BATTERY_H
-#define __EMUL_SMART_BATTERY_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief Smart Battery emulator backend API
- * @defgroup sbat_emul Smart Battery emulator
- * @{
- *
- * Smart Battery emulator handle static state of device. E.g. setting charging
- * current will not charge battery over time. Sending periodic status messages
- * and alarms to SMBus Host or charging voltage/current to Smart Battery Charger
- * is not supported. Behaviour of Smart Battery emulator is application-defined.
- * As-such, each application may
- *
- * - define a Device Tree overlay file to set the most of battery properties
- * - get battery properties calling @ref sbat_emul_get_bat_data Battery
- *   properties can be changed through obtained pointer. In multithread
- *   environment access to battery can be guarded by calling
- *   @ref sbat_emul_lock_bat_data and @ref sbat_emul_unlock_bat_data
- * - call functions from emul_common_i2c.h to setup custom handlers for SMBus
- *   messages
- */
-
-/* Value used to indicate that no command is selected */
-#define SBAT_EMUL_NO_CMD	-1
-/* Maximum size of data that can be returned in SMBus block transaction */
-#define MAX_BLOCK_SIZE		32
-/* Maximum length of command to send is maximum size of data + len byte + PEC */
-#define MSG_BUF_LEN		(MAX_BLOCK_SIZE + 2)
-
-/** @brief Emulated smart battery properties */
-struct sbat_emul_bat_data {
-	/** Battery mode - bit field configuring some battery behaviours */
-	uint16_t mode;
-	/** Word returned on manufacturer access command */
-	uint16_t mf_access;
-	/** Capacity alarm value */
-	uint16_t cap_alarm;
-	/** Remaing time alarm value */
-	uint16_t time_alarm;
-	/** Rate of charge used in some commands */
-	int16_t at_rate;
-	/**
-	 * Flag indicating if AT_RATE_TIME_TO_FULL command supports mW
-	 * capacity mode
-	 */
-	int at_rate_full_mw_support;
-	/** Error code returned by last command */
-	uint16_t error_code;
-	/** Design battery voltage in mV */
-	uint16_t design_mv;
-	/** Battery temperature at the moment in Kelvins */
-	uint16_t temp;
-	/** Battery voltage at the moment in mV */
-	uint16_t volt;
-	/** Current charging (> 0) or discharging (< 0) battery in mA */
-	int16_t cur;
-	/** Average current from 1 minute */
-	int16_t avg_cur;
-	/** Maximum error of returned values in percent */
-	uint16_t max_error;
-	/** Capacity of the battery at the moment in mAh */
-	uint16_t cap;
-	/** Full capacity of the battery in mAh */
-	uint16_t full_cap;
-	/** Design battery capacity in mAh */
-	uint16_t design_cap;
-	/** Charging current requested by battery */
-	uint16_t desired_charg_cur;
-	/** Charging voltage requested by battery */
-	uint16_t desired_charg_volt;
-	/** Number of cycles */
-	uint16_t cycle_count;
-	/** Specification of battery */
-	uint16_t spec_info;
-	/** Status of battery */
-	uint16_t status;
-	/** Date of manufacturing */
-	uint16_t mf_date;
-	/** Serial number */
-	uint16_t sn;
-	/** Manufacturer name */
-	uint8_t mf_name[MAX_BLOCK_SIZE];
-	/** Manufacturer name length */
-	int mf_name_len;
-	/** Device name */
-	uint8_t dev_name[MAX_BLOCK_SIZE];
-	/** Device name length */
-	int dev_name_len;
-	/** Device chemistry */
-	uint8_t dev_chem[MAX_BLOCK_SIZE];
-	/** Device chemistry length */
-	int dev_chem_len;
-	/** Manufacturer data */
-	uint8_t mf_data[MAX_BLOCK_SIZE];
-	/** Manufacturer data length */
-	int mf_data_len;
-};
-
-/**
- * @brief Get pointer to smart battery emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to smart battery emulator
- */
-struct i2c_emul *sbat_emul_get_ptr(int ord);
-
-/**
- * @brief Function which allows to get properties of emulated smart battery
- *
- * @param emul Pointer to smart battery emulator
- *
- * @return Pointer to smart battery properties
- */
-struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul);
-
-/**
- * @brief Convert date to format used by smart battery
- *
- * @param day Day
- * @param month Month
- * @param year Year
- *
- * @return Converted date
- */
-uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
-				unsigned int year);
-
-/**
- * @brief Function which gets return value for read commands that returns word.
- *        This function may be used to obtain battery properties that are
- *        calculated e.g. time to empty/full.
- *
- * @param emul Pointer to smart battery emulator
- * @param cmd Read command
- * @param val Pointer to where word should be stored
- *
- * @return 0 on success
- * @return 1 if command is unknown or return type different then word
- * @return negative on error while reading value
- */
-int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val);
-
-/**
- * @brief Function which gets return value for read commands that returns block
- *        data
- *
- * @param emul Pointer to smart battery emulator
- * @param cmd Read command
- * @param blk Pointer to where data pointer should be stored
- * @param len Pointer to where data length should be stored
- *
- * @return 0 on success
- * @return 1 if command is unknown or return type different then word
- * @return negative on error while reading value
- */
-int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
-			     int *len);
-
-/**
- * @brief Set next response of emulator. This function may be used in user
- *        custom read callback to setup response with calculated PEC.
- *
- * @param emul Pointer to smart battery emulator
- * @param cmd Read command
- * @param buf Buffer with the response
- * @param len Length of the response
- * @param fail If emulator should fail to send response
- */
-void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
-			    int len, bool fail);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_SMART_BATTERY_H */
diff --git a/zephyr/include/emul/emul_syv682x.h b/zephyr/include/emul/emul_syv682x.h
deleted file mode 100644
index aa0d8840f7..0000000000
--- a/zephyr/include/emul/emul_syv682x.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/** @file
- *
- * @brief Backend API for SYV682X emulator
- */
-
-#ifndef __EMUL_SYV682X_H
-#define __EMUL_SYV682X_H
-
-#include <drivers/i2c_emul.h>
-#include <stdint.h>
-
-/* Register info copied from syv682.h */
-
-/* SYV682x register addresses */
-#define SYV682X_STATUS_REG		0x00
-#define SYV682X_CONTROL_1_REG		0x01
-#define SYV682X_CONTROL_2_REG		0x02
-#define SYV682X_CONTROL_3_REG		0x03
-#define SYV682X_CONTROL_4_REG		0x04
-
-/* Status Register */
-#define SYV682X_STATUS_OC_HV		BIT(7)
-#define SYV682X_STATUS_RVS		BIT(6)
-#define SYV682X_STATUS_OC_5V		BIT(5)
-#define SYV682X_STATUS_OVP		BIT(4)
-#define SYV682X_STATUS_FRS		BIT(3)
-#define SYV682X_STATUS_TSD		BIT(2)
-#define SYV682X_STATUS_VSAFE_5V		BIT(1)
-#define SYV682X_STATUS_VSAFE_0V		BIT(0)
-#define SYV682X_STATUS_INT_MASK		0xfc
-
-/* Control Register 1 */
-#define SYV682X_CONTROL_1_CH_SEL	BIT(1)
-#define SYV682X_CONTROL_1_HV_DR		BIT(2)
-#define SYV682X_CONTROL_1_PWR_ENB	BIT(7)
-
-#define SYV682X_5V_ILIM_MASK		0x18
-#define SYV682X_5V_ILIM_BIT_SHIFT	3
-#define SYV682X_5V_ILIM_1_25		0
-#define SYV682X_5V_ILIM_1_75		1
-#define SYV682X_5V_ILIM_2_25		2
-#define SYV682X_5V_ILIM_3_30		3
-
-#define SYV682X_HV_ILIM_MASK		0x60
-#define SYV682X_HV_ILIM_BIT_SHIFT	5
-#define SYV682X_HV_ILIM_1_25		0
-#define SYV682X_HV_ILIM_1_75		1
-#define SYV682X_HV_ILIM_3_30		2
-#define SYV682X_HV_ILIM_5_50		3
-
-/* Control Register 2 */
-#define SYV682X_OC_DELAY_MASK		GENMASK(7, 6)
-#define SYV682X_OC_DELAY_SHIFT		6
-#define SYV682X_OC_DELAY_1MS		0
-#define SYV682X_OC_DELAY_10MS		1
-#define SYV682X_OC_DELAY_50MS		2
-#define SYV682X_OC_DELAY_100MS		3
-#define SYV682X_DSG_TIME_MASK		GENMASK(5, 4)
-#define SYV682X_DSG_TIME_SHIFT		4
-#define SYV682X_DSG_TIME_50MS		0
-#define SYV682X_DSG_TIME_100MS		1
-#define SYV682X_DSG_TIME_200MS		2
-#define SYV682X_DSG_TIME_400MS		3
-#define SYV682X_DSG_RON_MASK		GENMASK(3, 2)
-#define SYV682X_DSG_RON_SHIFT		2
-#define SYV682X_DSG_RON_200_OHM		0
-#define SYV682X_DSG_RON_400_OHM		1
-#define SYV682X_DSG_RON_800_OHM		2
-#define SYV682X_DSG_RON_1600_OHM	3
-#define SYV682X_CONTROL_2_SDSG		BIT(1)
-#define SYV682X_CONTROL_2_FDSG		BIT(0)
-
-/* Control Register 3 */
-#define SYV682X_BUSY			BIT(7)
-#define SYV682X_RVS_MASK		BIT(3)
-#define SYV682X_RST_REG			BIT(0)
-#define SYV682X_OVP_MASK		0x70
-#define SYV682X_OVP_BIT_SHIFT		4
-#define SYV682X_OVP_06_0		0
-#define SYV682X_OVP_08_0		1
-#define SYV682X_OVP_11_1		2
-#define SYV682X_OVP_12_1		3
-#define SYV682X_OVP_14_2		4
-#define SYV682X_OVP_17_9		5
-#define SYV682X_OVP_21_6		6
-#define SYV682X_OVP_23_7		7
-
-/* Control Register 4 */
-#define SYV682X_CONTROL_4_CC1_BPS	BIT(7)
-#define SYV682X_CONTROL_4_CC2_BPS	BIT(6)
-#define SYV682X_CONTROL_4_VCONN1	BIT(5)
-#define SYV682X_CONTROL_4_VCONN2	BIT(4)
-#define SYV682X_CONTROL_4_VBAT_OVP	BIT(3)
-#define SYV682X_CONTROL_4_VCONN_OCP	BIT(2)
-#define SYV682X_CONTROL_4_CC_FRS	BIT(1)
-#define SYV682X_CONTROL_4_INT_MASK	0x0c
-
-/**
- * @brief Get pointer to SYV682x emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to smart battery emulator
- */
-struct i2c_emul *syv682x_emul_get(int ord);
-
-/**
- * @brief Set the underlying interrupt conditions affecting the status register
- *
- * @param emul SYV682x emulator
- * @param val  A status register value corresponding to the underlying
- *             conditions
- */
-void syv682x_emul_set_status(struct i2c_emul *emul, uint8_t val);
-
-/**
- * @brief Set value of a register of SYV682x
- *
- * @param emul SYV682x emulator
- * @param reg  Register address
- * @param val  Value to write to the register
- *
- * @return 0 on success, error code on error
- */
-int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
-
-/**
- * @brief Get value of a register of SYV682x
- *
- * @param emul SYV682x emulator
- * @param reg  Register address
- * @param val  Pointer at which to store current value of register
- *
- * @return 0 on success, error code on error
- */
-int syv682x_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val);
-
-#endif /* __EMUL_SYV682X_H */
diff --git a/zephyr/include/emul/emul_tcs3400.h b/zephyr/include/emul/emul_tcs3400.h
deleted file mode 100644
index 49ec382a66..0000000000
--- a/zephyr/include/emul/emul_tcs3400.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for TCS3400 emulator
- */
-
-#ifndef __EMUL_TCS3400_H
-#define __EMUL_TCS3400_H
-
-#include <emul.h>
-#include <drivers/i2c.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief TCS3400 emulator backend API
- * @defgroup tcs_emul TCS3400 emulator
- * @{
- *
- * TCS3400 emulator supports responses to all write and read I2C messages.
- * Light sensor data registers are obtained from internal emulator state, gain
- * and acquisition time. Application may alter emulator state:
- *
- * - define a devicetree overlay file to set which inadvisable driver behaviour
- *   should be treated as error and emulated device ID and revision
- * - call @ref tcs_emul_set_reg and @ref tcs_emul_get_reg to set and get value
- *   of TCS3400 registers
- * - call @ref tcs_emul_set_val and @ref tcs_emul_set_val to set and get
- *   light sensor value
- * - call tcs_emul_set_err_* to change emulator behaviour on inadvisable driver
- *   behaviour
- * - call functions from emul_common_i2c.h to setup custom handlers for I2C
- *   messages
- */
-
-/**
- * Maximum number of integration cycles (when ATIME is zero). Value read from
- * sensor is proportional to number of integration cycles, e.g. with constant
- * light, value obtainded with 128 cycles will be two times smaller than value
- * obtained with 256 cycles.
- */
-#define TCS_EMUL_MAX_CYCLES	256
-/**
- * Maximum gain supported by TCS3400. Value read from sensor is multiplied by
- * gain selected in CONTROL register.
- */
-#define TCS_EMUL_MAX_GAIN	64
-
-/**
- * Emulator units are value returned with gain x64 and 256 integration cycles.
- * Max value is 1024 returned when gain is x1 and 1 integration cycle. Max value
- * represented in emulator units is 1024 * 64 * 256
- */
-#define TCS_EMUL_MAX_VALUE	(1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES)
-
-/** Axis argument used in @ref tcs_emul_set_val @ref tcs_emul_get_val */
-enum tcs_emul_axis {
-	TCS_EMUL_R,
-	TCS_EMUL_G,
-	TCS_EMUL_B,
-	TCS_EMUL_C,
-	TCS_EMUL_IR,
-};
-
-/**
- * Emulator saves only those registers in memory. IR select is stored sparately
- * and other registers are write only.
- */
-#define TCS_EMUL_FIRST_REG	TCS_I2C_ENABLE
-#define TCS_EMUL_LAST_REG	TCS_I2C_BDATAH
-#define TCS_EMUL_REG_COUNT	(TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1)
-
-/**
- * @brief Get pointer to TCS3400 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to TCS3400 emulator
- */
-struct i2c_emul *tcs_emul_get(int ord);
-
-/**
- * @brief Set value of given register of TCS3400
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg Register address which value will be changed
- * @param val New value of the register
- */
-void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
-
-/**
- * @brief Get value of given register of TCS3400
- *
- * @param emul Pointer to TCS3400 emulator
- * @param reg Register address
- *
- * @return Value of the register
- */
-uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg);
-
-/**
- * @brief Get internal value of light sensor for given axis
- *
- * @param emul Pointer to TCS3400 emulator
- * @param axis Axis to access
- *
- * @return Value of given axis with gain x64 and 256 integration cycles
- */
-int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis);
-
-/**
- * @brief Set internal value of light sensor for given axis
- *
- * @param emul Pointer to TCS3400 emulator
- * @param axis Axis to access
- * @param val New value of light sensor for given axis with gain x64 and
- *            256 integration cycles
- */
-void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val);
-
-/**
- * @brief Set if error should be generated when read only register is being
- *        written
- *
- * @param emul Pointer to TCS3400 emulator
- * @param set Check for this error
- */
-void tcs_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when reserved bits of register are
- *        not set to 0 on write I2C message
- *
- * @param emul Pointer to TCS3400 emulator
- * @param set Check for this error
- */
-void tcs_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
-
-/**
- * @brief Set if error should be generated when MSB register is accessed before
- *        LSB register
- *
- * @param emul Pointer to TCS3400 emulator
- * @param set Check for this error
- */
-void tcs_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_TCS3400_H */
diff --git a/zephyr/include/emul/i2c_mock.h b/zephyr/include/emul/i2c_mock.h
deleted file mode 100644
index e9e8d97252..0000000000
--- a/zephyr/include/emul/i2c_mock.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_
-#define ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_
-
-#include <emul.h>
-#include <drivers/i2c_emul.h>
-
-/**
- * @brief reset the I2C mock.
- *
- * @param emul The mock device to reset.
- */
-void i2c_mock_reset(const struct emul *emul);
-
-/**
- * @brief Get the i2c emulator pointer from the top level mock.
- *
- * @param emul The mock device to query
- * @return Pointer to the i2c emulator struct
- */
-struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul);
-
-/**
- * @brief Get the I2C address of the mock
- *
- * @param emul The mock device to query
- * @return The address on the I2C bus
- */
-uint16_t i2c_mock_get_addr(const struct emul *emul);
-
-#endif /* ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_ */
diff --git a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
deleted file mode 100644
index 8d3b56878e..0000000000
--- a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * @file
- * @brief ITE it8xxx2 register structure definitions used by the Chrome OS EC.
- */
-
-#ifndef _ITE_IT8XXX2_REG_DEF_CROS_H
-#define _ITE_IT8XXX2_REG_DEF_CROS_H
-
-/*
- * KBS (Keyboard Scan) device registers
- */
-struct kbs_reg {
-	/* 0x000: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOL;
-	/* 0x001: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOH1;
-	/* 0x002: Keyboard Scan Out Control */
-	volatile uint8_t KBS_KSOCTRL;
-	/* 0x003: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOH2;
-	/* 0x004: Keyboard Scan In */
-	volatile uint8_t KBS_KSI;
-	/* 0x005: Keyboard Scan In Control */
-	volatile uint8_t KBS_KSICTRL;
-	/* 0x006: Keyboard Scan In [7:0] GPIO Control */
-	volatile uint8_t KBS_KSIGCTRL;
-	/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
-	volatile uint8_t KBS_KSIGOEN;
-	/* 0x008: Keyboard Scan In [7:0] GPIO Data */
-	volatile uint8_t KBS_KSIGDAT;
-	/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
-	volatile uint8_t KBS_KSIGDMRR;
-	/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
-	volatile uint8_t KBS_KSOHGCTRL;
-	/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
-	volatile uint8_t KBS_KSOHGOEN;
-	/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
-	volatile uint8_t KBS_KSOHGDMRR;
-	/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
-	volatile uint8_t KBS_KSOLGCTRL;
-	/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
-	volatile uint8_t KBS_KSOLGOEN;
-};
-
-/* KBS register fields */
-#define IT8XXX2_KBS_KSOPU	BIT(2)
-#define IT8XXX2_KBS_KSOOD	BIT(0)
-#define IT8XXX2_KBS_KSIPU	BIT(2)
-#define IT8XXX2_KBS_KSO2GCTRL	BIT(2)
-#define IT8XXX2_KBS_KSO2GOEN	BIT(2)
-
-/*
- * ECPM (EC Clock and Power Management) device registers
- */
-struct ecpm_reg {
-	/* 0x000: Reserved1 */
-	volatile uint8_t reserved1;
-	/* 0x001: Clock Gating Control 1 */
-	volatile uint8_t ECPM_CGCTRL1;
-	/* 0x002: Clock Gating Control 2 */
-	volatile uint8_t ECPM_CGCTRL2;
-	/* 0x003: PLL Control */
-	volatile uint8_t ECPM_PLLCTRL;
-	/* 0x004: Auto Clock Gating */
-	volatile uint8_t ECPM_AUTOCG;
-	/* 0x005: Clock Gating Control 3 */
-	volatile uint8_t ECPM_CGCTRL3;
-	/* 0x006: PLL Frequency */
-	volatile uint8_t ECPM_PLLFREQ;
-	/* 0x007: Reserved2 */
-	volatile uint8_t reserved2;
-	/* 0x008: PLL Clock Source Status */
-	volatile uint8_t ECPM_PLLCSS;
-	/* 0x009: Clock Gating Control 4 */
-	volatile uint8_t ECPM_CGCTRL4;
-	/* 0x00A: Reserved3 */
-	volatile uint8_t reserved3;
-	/* 0x00B: Reserved4 */
-	volatile uint8_t reserved4;
-	/* 0x00C: System Clock Divide Control 0 */
-	volatile uint8_t ECPM_SCDCR0;
-	/* 0x00D: System Clock Divide Control 1 */
-	volatile uint8_t ECPM_SCDCR1;
-	/* 0x00E: System Clock Divide Control 2 */
-	volatile uint8_t ECPM_SCDCR2;
-	/* 0x00F: System Clock Divide Control 3 */
-	volatile uint8_t ECPM_SCDCR3;
-	/* 0x010: System Clock Divide Control 4 */
-	volatile uint8_t ECPM_SCDCR4;
-};
-
-#endif /* _ITE_IT8XXX2_REG_DEF_CROS_H */
diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
deleted file mode 100644
index 8702502a13..0000000000
--- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright (c) 2020 Nuvoton Technology Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * @file
- * @brief Nuvoton NPCX register structure definitions used by the Chrome OS EC.
- */
-
-#ifndef _NUVOTON_NPCX_REG_DEF_CROS_H
-#define _NUVOTON_NPCX_REG_DEF_CROS_H
-
-/*
- * KBS (Keyboard Scan) device registers
- */
-struct kbs_reg {
-	volatile uint8_t reserved1[4];
-	/* 0x004: Keyboard Scan In */
-	volatile uint8_t KBSIN;
-	/* 0x005: Keyboard Scan In Pull-Up Enable */
-	volatile uint8_t KBSINPU;
-	/* 0x006: Keyboard Scan Out 0 */
-	volatile uint16_t KBSOUT0;
-	/* 0x008: Keyboard Scan Out 1 */
-	volatile uint16_t KBSOUT1;
-	/* 0x00A: Keyboard Scan Buffer Index */
-	volatile uint8_t KBS_BUF_INDX;
-	/* 0x00B: Keyboard Scan Buffer Data */
-	volatile uint8_t KBS_BUF_DATA;
-	/* 0x00C: Keyboard Scan Event */
-	volatile uint8_t KBSEVT;
-	/* 0x00D: Keyboard Scan Control */
-	volatile uint8_t KBSCTL;
-	/* 0x00E: Keyboard Scan Configuration Index */
-	volatile uint8_t KBS_CFG_INDX;
-	/* 0x00F: Keyboard Scan Configuration Data */
-	volatile uint8_t KBS_CFG_DATA;
-};
-
-/* KBS register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSEVT_KBSDONE              0
-#define NPCX_KBSEVT_KBSERR               1
-#define NPCX_KBSCTL_START                0
-#define NPCX_KBSCTL_KBSMODE              1
-#define NPCX_KBSCTL_KBSIEN               2
-#define NPCX_KBSCTL_KBSINC               3
-#define NPCX_KBSCTL_KBHDRV_FIELD         FIELD(6, 2)
-#define NPCX_KBSCFGINDX                  0
-/* Index of 'Automatic Scan' configuration register */
-#define KBS_CFG_INDX_DLY1                0 /* Keyboard Scan Delay T1 Byte */
-#define KBS_CFG_INDX_DLY2                1 /* Keyboard Scan Delay T2 Byte */
-#define KBS_CFG_INDX_RTYTO               2 /* Keyboard Scan Retry Timeout */
-#define KBS_CFG_INDX_CNUM                3 /* Keyboard Scan Columns Number */
-#define KBS_CFG_INDX_CDIV                4 /* Keyboard Scan Clock Divisor */
-
-/*
- * Flash Interface Unit (FIU) device registers
- */
-struct fiu_reg {
-	/* 0x001: Burst Configuration */
-	volatile uint8_t BURST_CFG;
-	/* 0x002: FIU Response Configuration */
-	volatile uint8_t RESP_CFG;
-	volatile uint8_t reserved1[18];
-	/* 0x014: SPI Flash Configuration */
-	volatile uint8_t SPI_FL_CFG;
-	volatile uint8_t reserved2;
-	/* 0x016: UMA Code Byte */
-	volatile uint8_t UMA_CODE;
-	/* 0x017: UMA Address Byte 0 */
-	volatile uint8_t UMA_AB0;
-	/* 0x018: UMA Address Byte 1 */
-	volatile uint8_t UMA_AB1;
-	/* 0x019: UMA Address Byte 2 */
-	volatile uint8_t UMA_AB2;
-	/* 0x01A: UMA Data Byte 0 */
-	volatile uint8_t UMA_DB0;
-	/* 0x01B: UMA Data Byte 1 */
-	volatile uint8_t UMA_DB1;
-	/* 0x01C: UMA Data Byte 2 */
-	volatile uint8_t UMA_DB2;
-	/* 0x01D: UMA Data Byte 3 */
-	volatile uint8_t UMA_DB3;
-	/* 0x01E: UMA Control and Status */
-	volatile uint8_t UMA_CTS;
-	/* 0x01F: UMA Extended Control and Status */
-	volatile uint8_t UMA_ECTS;
-	/* 0x020: UMA Data Bytes 0-3 */
-	volatile uint32_t UMA_DB0_3;
-	volatile uint8_t reserved3[2];
-	/* 0x026: CRC Control Register */
-	volatile uint8_t CRCCON;
-	/* 0x027: CRC Entry Register */
-	volatile uint8_t CRCENT;
-	/* 0x028: CRC Initialization and Result Register */
-	volatile uint32_t CRCRSLT;
-	volatile uint8_t reserved4[4];
-	/* 0x030: FIU Read Command */
-	volatile uint8_t FIU_RD_CMD;
-	volatile uint8_t reserved5;
-	/* 0x032: FIU Dummy Cycles */
-	volatile uint8_t FIU_DMM_CYC;
-	/* 0x033: FIU Extended Configuration */
-	volatile uint8_t FIU_EXT_CFG;
-};
-
-/* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
-
-/* UMA fields selections */
-#define UMA_FLD_ADDR     BIT(NPCX_UMA_CTS_A_SIZE)  /* 3-bytes ADR field */
-#define UMA_FLD_NO_CMD   BIT(NPCX_UMA_CTS_C_SIZE)  /* No 1-Byte CMD field */
-#define UMA_FLD_WRITE    BIT(NPCX_UMA_CTS_RD_WR)   /* Write transaction */
-#define UMA_FLD_SHD_SL   BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
-#define UMA_FLD_EXEC     BIT(NPCX_UMA_CTS_EXEC_DONE)
-
-#define UMA_FIELD_DATA_1 0x01
-#define UMA_FIELD_DATA_2 0x02
-#define UMA_FIELD_DATA_3 0x03
-#define UMA_FIELD_DATA_4 0x04
-
-/* UMA code for transaction */
-#define UMA_CODE_CMD_ONLY       (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_ADR        (UMA_FLD_EXEC | UMA_FLD_ADDR | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_RD_BYTE(n)     (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
-					UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_ONLY    (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_ADR     (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
-				UMA_FLD_SHD_SL)
-
-#define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
-					UMA_FLD_SHD_SL)
-
-/*
- * Monotonic Counter (MTC) device registers
- */
-struct mtc_reg {
-	/* 0x000: Timing Ticks Count Register */
-	volatile uint32_t TTC;
-	/* 0x004: Wake-Up Ticks Count Register */
-	volatile uint32_t WTC;
-};
-
-/* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
-
-/* SHI (Serial Host Interface) registers */
-struct shi_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: SHI Configuration 1 */
-	volatile uint8_t SHICFG1;
-	/* 0x002: SHI Configuration 2 */
-	volatile uint8_t SHICFG2;
-	volatile uint8_t reserved2[2];
-	/* 0x005: Event Enable */
-	volatile uint8_t EVENABLE;
-	/* 0x006: Event Status */
-	volatile uint8_t EVSTAT;
-	/* 0x007: SHI Capabilities */
-	volatile uint8_t CAPABILITY;
-	/* 0x008: Status */
-	volatile uint8_t STATUS;
-	volatile uint8_t reserved3;
-	/* 0x00A: Input Buffer Status */
-	volatile uint8_t IBUFSTAT;
-	/* 0x00B: Output Buffer Status */
-	volatile uint8_t OBUFSTAT;
-	/* 0x00C: SHI Configuration 3 */
-	volatile uint8_t SHICFG3;
-	/* 0x00D: SHI Configuration 4 */
-	volatile uint8_t SHICFG4;
-	/* 0x00E: SHI Configuration 5 */
-	volatile uint8_t SHICFG5;
-	/* 0x00F: Event Status 2 */
-	volatile uint8_t EVSTAT2;
-	/* 0x010: Event Enable 2 */
-	volatile uint8_t EVENABLE2;
-	volatile uint8_t reserved4[15];
-	/* 0x20~0x9F: Output Buffer */
-	volatile uint8_t OBUF[128];
-	/* 0xA0~0x11F: Input Buffer */
-	volatile uint8_t IBUF[128];
-};
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
-#define NPCX_SHICFG3_OBUFLVLDIS          7
-#define NPCX_SHICFG4_IBUFLVLDIS          7
-#define NPCX_SHICFG5_IBUFLVL2            FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS         7
-#define NPCX_EVSTAT2_IBHF2               0
-#define NPCX_EVSTAT2_CSNRE               1
-#define NPCX_EVSTAT2_CSNFE               2
-#define NPCX_EVENABLE2_IBHF2EN           0
-#define NPCX_EVENABLE2_CSNREEN           1
-#define NPCX_EVENABLE2_CSNFEEN           2
-
-#endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */
diff --git a/zephyr/linker/CMakeLists.txt b/zephyr/linker/CMakeLists.txt
deleted file mode 100644
index 71955c6d9d..0000000000
--- a/zephyr/linker/CMakeLists.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Add the fixed sections to the output image.
-zephyr_linker_sources(ROM_START SORT_KEY 1 fixed-sections.ld)
-
-# Support protection of part of the internal RAM
-zephyr_linker_sources(RWDATA SORT_KEY 1 iram_text.ld)
-
-# Compute the image size
-zephyr_linker_sources(RAM_SECTIONS image_size.ld)
-
-# Little FW with specific purposes used by NPCX EC
-zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_NPCX ROM_START SORT_KEY 1
-  npcx-lfw.ld)
-
-zephyr_linker_sources(DATA_SECTIONS iterables-ram.ld)
-zephyr_linker_sources(SECTIONS iterables-rom.ld)
diff --git a/zephyr/linker/fixed-sections.ld b/zephyr/linker/fixed-sections.ld
deleted file mode 100644
index 5046823713..0000000000
--- a/zephyr/linker/fixed-sections.ld
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if defined(CONFIG_PLATFORM_EC) && !defined(CONFIG_ARCH_POSIX)
-*(.fixed.*)
-#endif
diff --git a/zephyr/linker/image_size.ld b/zephyr/linker/image_size.ld
deleted file mode 100644
index b1e401ae7f..0000000000
--- a/zephyr/linker/image_size.ld
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \
-	defined(CONFIG_CPU_CORTEX_A)
-__image_size = _flash_used;
-#elif defined(CONFIG_RISCV)
-__image_size = __rom_region_size;
-#else
-/*
- * Intentionally set to 0. Some components, such as EFS2, need this value.
- * Having it be 0 will make it easier to find and add new cores.
- */
-__image_size = 0;
-#endif
diff --git a/zephyr/linker/iram_text.ld b/zephyr/linker/iram_text.ld
deleted file mode 100644
index 3ea3f4db7e..0000000000
--- a/zephyr/linker/iram_text.ld
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef CONFIG_ARCH_POSIX
-
-/* This code taken from core/cortex-m/ec.lds.S */
-
-#if defined(CONFIG_PLATFORM_EC_MPU)
-/* MPU regions must be aligned to a 32-byte boundary */
-#define _IRAM_ALIGN	32
-#else
-#define _IRAM_ALIGN	4
-#endif
-
-	. = ALIGN(_IRAM_ALIGN);
-	__iram_text_start = .;
-	*(.iram.text)
-	. = ALIGN(_IRAM_ALIGN);
-	__iram_text_end = .;
-
-#endif /* CONFIG_ARCH_POSIX */
diff --git a/zephyr/linker/iterables-ram.ld b/zephyr/linker/iterables-ram.ld
deleted file mode 100644
index 58318a0e78..0000000000
--- a/zephyr/linker/iterables-ram.ld
+++ /dev/null
@@ -1,3 +0,0 @@
-#ifdef CONFIG_PLATFORM_EC_HOOKS
-ITERABLE_SECTION_RAM(zephyr_shim_hook_list, 4)
-#endif
diff --git a/zephyr/linker/iterables-rom.ld b/zephyr/linker/iterables-rom.ld
deleted file mode 100644
index b8e451a085..0000000000
--- a/zephyr/linker/iterables-rom.ld
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD
-ITERABLE_SECTION_ROM(host_command, 4)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
-ITERABLE_SECTION_ROM(mkbp_event_source, 4)
-#endif
diff --git a/zephyr/linker/npcx-lfw.ld b/zephyr/linker/npcx-lfw.ld
deleted file mode 100644
index a6de1df65a..0000000000
--- a/zephyr/linker/npcx-lfw.ld
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-. = ALIGN(4);
-__lfw_text_start = .;
-*(.lfw.*)
-. = ALIGN(4);
-__lfw_text_end = .;
-
-#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
-. = ALIGN(4);
-__flash_lpfw_start = .;
-/* Entering deep idle FW for better power consumption */
-KEEP(*(.lowpower_ram))
-. = ALIGN(4);
-__flash_lpfw_end = .;
-__flash_lplfw_start = .;
-/* GDMA utilities for better FW download speed */
-KEEP(*(.lowpower_ram2))
-. = ALIGN(4);
-__flash_lplfw_end = .;
-#endif /* CONFIG_PLATFORM_EC_EXTERNAL_STORAGE */
diff --git a/zephyr/module.yml b/zephyr/module.yml
deleted file mode 100644
index 66bfcd8d9f..0000000000
--- a/zephyr/module.yml
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-build:
-  cmake: zephyr/
-  kconfig: zephyr/Kconfig
-  settings:
-    board_root: zephyr/
diff --git a/zephyr/projects/asurada/hayato/CMakeLists.txt b/zephyr/projects/asurada/hayato/CMakeLists.txt
deleted file mode 100644
index 660b0a9088..0000000000
--- a/zephyr/projects/asurada/hayato/CMakeLists.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-add_compile_definitions(BOARD_HAYATO)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(hayato)
-
-zephyr_library_include_directories(include)
-
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/asurada" CACHE PATH
-    "Path to the platform/ec baseboard directory")
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/hayato" CACHE PATH
-  "Path to the platform/ec board directory")
-
-zephyr_library_sources(
-  "${PLATFORM_EC_BASEBOARD}/board_chipset.c"
-  "${PLATFORM_EC_BASEBOARD}/board_id.c"
-  "${PLATFORM_EC_BASEBOARD}/hibernate.c"
-  "${PLATFORM_EC_BASEBOARD}/regulator.c"
-  "${PLATFORM_EC_BASEBOARD}/usbc_config.c"
-  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
-  "src/i2c.c")
diff --git a/zephyr/projects/asurada/hayato/battery.dts b/zephyr/projects/asurada/hayato/battery.dts
deleted file mode 100644
index deb803bb8c..0000000000
--- a/zephyr/projects/asurada/hayato/battery.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	batteries {
-		default_battery: c235 {
-			compatible = "as3gwrc3ka,c235-41";
-		};
-	};
-};
diff --git a/zephyr/projects/asurada/hayato/gpio.dts b/zephyr/projects/asurada/hayato/gpio.dts
deleted file mode 100644
index f04171651f..0000000000
--- a/zephyr/projects/asurada/hayato/gpio.dts
+++ /dev/null
@@ -1,347 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		power_button_l: power_button_l {
-			gpios = <&gpioe 4 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "POWER_BUTTON_L";
-		};
-		lid_open: lid_open {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-		tablet_mode_l {
-			gpios = <&gpioj 7 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		ap_ec_warm_rst_req {
-			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
-			label = "AP_EC_WARM_RST_REQ";
-		};
-		ap_ec_watchdog_l {
-			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_AP_EC_WATCHDOG_L";
-			label = "AP_EC_WATCHDOG_L";
-		};
-		ap_in_sleep_l {
-			gpios = <&gpiof 2 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_AP_IN_SLEEP_L";
-			label = "AP_IN_SLEEP_L";
-		};
-		ap-xhci-init-done {
-			gpios = <&gpiod 2 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_AP_XHCI_INIT_DONE";
-			label = "AP_XHCI_INIT_DONE";
-		};
-		pmic_ec_pwrgd {
-			gpios = <&gpiof 3 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_PMIC_EC_PWRGD";
-			label = "PMIC_EC_PWRGD";
-		};
-		gpio_accel_gyro_int_l: base_imu_int_l {
-			gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_IMU_INT_L";
-			label = "BASE_IMU_INT_L";
-		};
-		lid_accel_int_l {
-			gpios = <&gpioj 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_LID_ACCEL_INT_L";
-			label = "LID_ACCEL_INT_L";
-		};
-		als_rgb_int_odl {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-			enum-name = "GPIO_ALS_RGB_INT_ODL";
-			label = "ALS_RGB_INT_ODL";
-		};
-		usb_c0_ppc_int_odl {
-			gpios = <&gpiod 1 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
-			label = "USB_C0_PPC_INT_ODL";
-		};
-		usb_c0_bc12_int_odl {
-			gpios = <&gpioj 6 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
-			label = "USB_C0_BC12_INT_ODL";
-		};
-		usb_c1_bc12_int_l {
-			gpios = <&gpioj 4 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_BC12_INT_L";
-			label = "USB_C1_BC12_INT_L";
-		};
-		volume_down_l {
-			gpios = <&gpiod 5 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-			label = "VOLUME_DOWN_L";
-		};
-		volume_up_l {
-			gpios = <&gpiod 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_UP_L";
-			label = "VOLUME_UP_L";
-		};
-		ac_present: ac_present {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "AC_PRESENT";
-		};
-		wp {
-			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_WP";
-			label = "WP";
-		};
-		spi0_cs {
-			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_SPI0_CS";
-			label = "SPI0_CS";
-		};
-		x_ec_gpio2 {
-			gpios = <&gpiob 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_X_EC_GPIO2";
-			label = "X_EC_GPIO2";
-		};
-		ec_pmic_en_odl {
-			gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_PMIC_EN_ODL";
-			label = "EC_PMIC_EN_ODL";
-		};
-		ec_pmic_watchdog_l {
-			gpios = <&gpioh 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_PMIC_WATCHDOG_L";
-			label = "EC_PMIC_WATCHDOG_L";
-		};
-		en_pp5000_a {
-			gpios = <&gpioc 6 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EN_PP5000_A";
-			label = "EN_PP5000_A";
-		};
-		pg_mt6315_proc_odl {
-			gpios = <&gpioe 1 GPIO_INPUT>;
-			enum-name = "GPIO_PG_MT6315_PROC_ODL";
-			label = "PG_MT6315_PROC_ODL";
-		};
-		pg_mt6360_odl {
-			gpios = <&gpiof 1 GPIO_INPUT>;
-			enum-name = "GPIO_PG_MT6360_ODL";
-			label = "PG_MT6360_ODL";
-		};
-		pg_pp5000_a_odl {
-			gpios = <&gpioa 6 GPIO_INPUT>;
-			enum-name = "GPIO_PG_PP5000_A_ODL";
-			label = "PG_PP5000_A_ODL";
-		};
-		en_slp_z {
-			gpios = <&gpioe 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_SLP_Z";
-			label = "EN_SLP_Z";
-		};
-		sys_rst_odl {
-			gpios = <&gpiob 6 GPIO_ODR_LOW>;
-			enum-name = "GPIO_SYS_RST_ODL";
-			label = "SYS_RST_ODL";
-		};
-		ec_bl_en_od {
-			gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_BL_EN_OD";
-			label = "EC_BL_EN_OD";
-		};
-		ec_int_l {
-			gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "EC_INT_L";
-		};
-		dp_aux_path_sel {
-			gpios = <&gpiog 0 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_DP_AUX_PATH_SEL";
-			label = "DP_AUX_PATH_SEL";
-		};
-		ec_dpbrdg_hpd_odl {
-			gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EC_DPBRDG_HPD_ODL";
-			label = "EC_DPBRDG_HPD_ODL";
-		};
-		en_pp5000_usb_a0_vbus {
-			gpios = <&gpiob 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USB_A0_VBUS";
-			label = "EN_PP5000_USB_A0_VBUS";
-		};
-		usb_c0_frs_en {
-			gpios = <&gpioh 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_USB_C0_FRS_EN";
-			label = "USB_C0_FRS_EN";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioc 0 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		bc12_det_en {
-			gpios = <&gpioj 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_BC12_DET_EN";
-			label = "BC12_DET_EN";
-		};
-		en_ec_id_odl {
-			gpios = <&gpioh 5 GPIO_ODR_LOW>;
-			enum-name = "GPIO_EN_EC_ID_ODL";
-			label = "EN_EC_ID_ODL";
-		};
-		entering_rw {
-			gpios = <&gpioc 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "ENTERING_RW";
-		};
-		en_5v_usm {
-			gpios = <&gpiod 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_5V_USM";
-			label = "EN_5V_USM";
-		};
-		i2c_b_scl {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_B_SCL";
-			label = "I2C_B_SCL";
-		};
-		i2c_b_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_B_SDA";
-			label = "I2C_B_SDA";
-		};
-		i2c_c_scl {
-			gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_I2C_C_SCL";
-			label = "I2C_C_SCL";
-		};
-		i2c_c_sda {
-			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_I2C_C_SDA";
-			label = "I2C_C_SDA";
-		};
-		i2c_e_scl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_E_SCL";
-			label = "I2C_E_SCL";
-		};
-		i2c_e_sda {
-			gpios = <&gpioe 7 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_E_SDA";
-			label = "I2C_E_SDA";
-		};
-		i2c_f_scl {
-			gpios = <&gpiof 6 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_F_SCL";
-			label = "I2C_F_SCL";
-		};
-		i2c_f_sda {
-			gpios = <&gpiof 7 GPIO_INPUT>;
-			enum-name = "GPIO_I2C_F_SDA";
-			label = "I2C_F_SDA";
-		};
-		ec_x_gpio1 {
-			gpios = <&gpioh 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_X_GPIO1";
-			label = "EC_X_GPIO1";
-		};
-		ec_x_gpio3 {
-			gpios = <&gpioj 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_X_GPIO3";
-			label = "EC_X_GPIO3";
-		};
-		set_vmc_volt_at_1v8 {
-			gpios = <&gpiod 4 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_SET_VMC_VOLT_AT_1V8";
-			label = "SET_VMC_VOLT_AT_1V8";
-		};
-		en_pp3000_vmc_pmu {
-			gpios = <&gpiod 2 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EN_PP3000_VMC_PMU";
-			label = "EN_PP3000_VMC_PMU";
-		};
-		packet_mode_en {
-			gpios = <&gpioa 3 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_PACKET_MODE_EN";
-			label = "PACKET_MODE_EN";
-		};
-		usb_a0_fault_odl {
-			gpios = <&gpioa 7 GPIO_INPUT>;
-			enum-name = "GPIO_USB_A0_FAULT_ODL";
-			label = "USB_A0_FAULT_ODL";
-		};
-		charger_prochot_odl {
-			gpios = <&gpioc 3 GPIO_INPUT>;
-			enum-name = "GPIO_CHARGER_PROCHOT_ODL";
-			label = "CHARGER_PROCHOT_ODL";
-		};
-		pg_mt6315_gpu_odl {
-			gpios = <&gpioh 6 GPIO_INPUT>;
-			enum-name = "GPIO_PG_MT6315_GPU_ODL";
-			label = "PG_MT6315_GPU_ODL";
-		};
-		en_pp3000_sd_u {
-			gpios = <&gpiog 1 (GPIO_INPUT | GPIO_PULL_DOWN |
-					GPIO_VOLTAGE_1P8)>;
-			enum-name = "GPIO_EN_PP3000_SD_U";
-			label = "EN_PP3000_SD_U";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioc 4 GPIO_INPUT>;
-			enum-name = "GPIO_CCD_MODE_ODL";
-			label = "CCD_MODE_ODL";
-		};
-		spi_clk_gpg6 {
-			gpios = <&gpiog 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_SPI_CLK_GPG6";
-			label = "SPI_CLK_GPG6";
-		};
-		spi_mosi_gpg4 {
-			gpios = <&gpiog 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SPI_MOSI_GPG4";
-			label = "SPI_MOSI_GPG4";
-		};
-		spi_miso_gpg5 {
-			gpios = <&gpiog 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SPI_MISO_GPG5";
-			label = "SPI_MISO_GPG5";
-		};
-		spi_cs_gpg7 {
-			gpios = <&gpiog 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SPI_CS_GPG7";
-			label = "SPI_CS_GPG7";
-		};
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <&ac_present
-			       &power_button_l
-			       &lid_open>;
-	};
-
-	unused-pins {
-		compatible = "unused-gpios";
-
-		unused-gpios =
-			/* uart1_rx */
-			<&gpiob 0 GPIO_INPUT>,
-			/* nc_gpg3 */
-			<&gpiog 3 GPIO_OUT_LOW>,
-			/* nc_gpi7 */
-			<&gpioi 7 GPIO_OUT_LOW>,
-			/* nc_gpm2 */
-			<&gpiom 2 (GPIO_INPUT | GPIO_PULL_DOWN)>,
-			/* nc_gpm3 */
-			<&gpiom 3 (GPIO_INPUT | GPIO_PULL_DOWN)>,
-			/* nc_gpm6 */
-			<&gpiom 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-	};
-};
diff --git a/zephyr/projects/asurada/hayato/include/gpio_map.h b/zephyr/projects/asurada/hayato/include/gpio_map.h
deleted file mode 100644
index 5f01f290d2..0000000000
--- a/zephyr/projects/asurada/hayato/include/gpio_map.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-/*
- * TODO(b:188674805) create a driver to pull this information from DeviceTree
- */
-#include "power/mt8192.h"
-
-#define GPIO_ENTERING_RW		GPIO_UNIMPLEMENTED
-#define GPIO_WP_L			GPIO_UNIMPLEMENTED
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#endif
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS						\
-	GPIO_INT(GPIO_LID_OPEN,						\
-		 GPIO_INT_EDGE_BOTH, lid_interrupt)			\
-	GPIO_INT(GPIO_POWER_BUTTON_L,					\
-		 GPIO_INT_EDGE_BOTH, power_button_interrupt)		\
-	GPIO_INT(GPIO_EC_IMU_INT_L,					\
-		 GPIO_INT_EDGE_FALLING, bmi160_interrupt)		\
-	GPIO_INT(GPIO_LID_ACCEL_INT_L,					\
-		 GPIO_INT_EDGE_FALLING, lis2dw12_interrupt)		\
-	GPIO_INT(GPIO_TABLET_MODE_L,					\
-		 GPIO_INT_EDGE_BOTH, gmr_tablet_switch_isr)		\
-	GPIO_INT(GPIO_USB_C0_PPC_INT_ODL,				\
-		 GPIO_INT_EDGE_BOTH, ppc_interrupt)			\
-	GPIO_INT(GPIO_USB_C0_BC12_INT_ODL,				\
-		 GPIO_INT_EDGE_FALLING, bc12_interrupt)			\
-	GPIO_INT(GPIO_USB_C1_BC12_INT_L,				\
-		 GPIO_INT_EDGE_FALLING, bc12_interrupt)			\
-	GPIO_INT(GPIO_AC_PRESENT,					\
-		 GPIO_INT_EDGE_BOTH, extpower_interrupt)		\
-	GPIO_INT(GPIO_X_EC_GPIO2,					\
-		 GPIO_INT_EDGE_FALLING, x_ec_interrupt)			\
-	GPIO_INT(GPIO_AP_XHCI_INIT_DONE,				\
-		 GPIO_INT_EDGE_BOTH, usb_a0_interrupt)			\
-	GPIO_INT(GPIO_AP_EC_WATCHDOG_L,					\
-		 GPIO_INT_EDGE_BOTH, chipset_watchdog_interrupt)	\
-	GPIO_INT(GPIO_AP_IN_SLEEP_L,					\
-		 GPIO_INT_EDGE_BOTH, power_signal_interrupt)		\
-	GPIO_INT(GPIO_PMIC_EC_PWRGD,					\
-		 GPIO_INT_EDGE_BOTH, power_signal_interrupt)		\
-	GPIO_INT(GPIO_AP_EC_WARM_RST_REQ,				\
-		 GPIO_INT_EDGE_RISING, chipset_reset_request_interrupt) \
-	GPIO_INT(GPIO_SPI0_CS,						\
-		 GPIO_INT_EDGE_FALLING, spi_event)
-
-#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/asurada/hayato/include/i2c_map.h b/zephyr/projects/asurada/hayato/include/i2c_map.h
deleted file mode 100644
index 898d5c398c..0000000000
--- a/zephyr/projects/asurada/hayato/include/i2c_map.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_I2C_MAP_H
-#define __ZEPHYR_I2C_MAP_H
-
-#include <devicetree.h>
-
-#include "i2c/i2c.h"
-
-#endif /* __ZEPHYR_I2C_MAP_H */
diff --git a/zephyr/projects/asurada/hayato/include/pwm_map.h b/zephyr/projects/asurada/hayato/include/pwm_map.h
deleted file mode 100644
index 0f74812827..0000000000
--- a/zephyr/projects/asurada/hayato/include/pwm_map.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_CHROME_PWM_MAP_H
-#define __ZEPHYR_CHROME_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "config.h"
-
-#include "pwm/pwm.h"
-
-/*
- * TODO(b/177452529): eliminate the dependency on enum pwm_channel
- * and configure this information directly from the device tree.
- */
-#define PWM_CH_LED1	NAMED_PWM(led1)
-#define PWM_CH_LED2	NAMED_PWM(led2)
-#define PWM_CH_LED3	NAMED_PWM(led3)
-
-#endif /* __ZEPHYR_CHROME_PWM_MAP_H */
diff --git a/zephyr/projects/asurada/hayato/motionsense.dts b/zephyr/projects/asurada/hayato/motionsense.dts
deleted file mode 100644
index 10128b0838..0000000000
--- a/zephyr/projects/asurada/hayato/motionsense.dts
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi160-int = &base_accel;
-		lis2dw12-int = &lid_accel;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
-		};
-
-		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 (-1) 0
-				 0 0 1>;
-		};
-
-		base_rot_ref: base-rotation-ref {
-			mat33 = <1 0 0
-				 0 (-1) 0
-				 0 0 (-1)>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bmi160_data: bmi160-drv-data {
-			compatible = "cros-ec,drvdata-bmi160";
-			status = "okay";
-		};
-
-		lis2dw12_data: lis2dw12-drv-data {
-			compatible = "cros-ec,drvdata-lis2dw12";
-			status = "okay";
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,lis2dw12";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&lis2dw12_data>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi160-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi160-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_accel_gyro_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel>;
-	};
-};
diff --git a/zephyr/projects/asurada/hayato/prj.conf b/zephyr/projects/asurada/hayato/prj.conf
deleted file mode 100644
index 2faab291f2..0000000000
--- a/zephyr/projects/asurada/hayato/prj.conf
+++ /dev/null
@@ -1,120 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-
-# Bring up options
-CONFIG_KERNEL_SHELL=y
-CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
-CONFIG_PLATFORM_EC_CONSOLE_USES_PRINTK=y
-
-# Battery
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-
-# Charger
-CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
-CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
-CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
-CONFIG_PLATFORM_EC_CHARGER_OTG=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-# BOARD_RS2
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-# BOARD_RS1
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-
-# Host Commands
-CONFIG_PLATFORM_EC_HOSTCMD=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
-CONFIG_PLATFORM_EC_HOSTCMD_REGULATOR=y
-CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
-
-# MKBP event mask
-CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
-CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
-CONFIG_PLATFORM_EC_ACCEL_LIS2DW12_AS_BASE=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-
-# USB-A
-CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
-
-# USB-C
-CONFIG_HAS_TASK_PD_C1=y
-CONFIG_HAS_TASK_PD_INT_C1=n
-CONFIG_HAS_TASK_PD_INT_C0=n
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_BC12_DETECT_MT6360=y
-CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
-CONFIG_PLATFORM_EC_MT6360_BC12_GPIO=y
-CONFIG_PLATFORM_EC_SMBUS_PEC=y
-CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
-CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
-CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
-CONFIG_PLATFORM_EC_USB_MUX_IT5205=y
-CONFIG_PLATFORM_EC_USB_MUX_PS8743=y
-CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_FRS=y
-CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT=2
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
-CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
-CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y
-CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
-CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
-CONFIG_PLATFORM_EC_USB_PD_USB4=n
-CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
-
-# USB ID
-# This is allocated for Asurada
-# http://google3/hardware/standards/usb/
-# TODO(b/183608112): Move to device tree
-CONFIG_PLATFORM_EC_USB_PID=0x5053
-
-# VBoot without EFS2
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-CONFIG_PLATFORM_EC_VBOOT_HASH=y
-
-# TODO(b/180980668): bring these features up
-CONFIG_LTO=n
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
diff --git a/zephyr/projects/asurada/hayato/pwm.dts b/zephyr/projects/asurada/hayato/pwm.dts
deleted file mode 100644
index fc8e0b169b..0000000000
--- a/zephyr/projects/asurada/hayato/pwm.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-pwms {
-		compatible = "named-pwms";
-		/* NOTE: &pwm number needs same with channel number */
-		led1 {
-			pwms = <&pwm0 PWM_CHANNEL_0 PWM_POLARITY_INVERTED>;
-			label = "LED1";
-			/*
-			 * If we need pwm output in ITE chip power saving
-			 * mode, then we should set frequency <=324Hz.
-			 */
-			frequency = <324>;
-		};
-		led2 {
-			pwms = <&pwm1 PWM_CHANNEL_1 PWM_POLARITY_INVERTED>;
-			label = "LED2";
-			frequency = <324>;
-		};
-		led3 {
-			pwms = <&pwm2 PWM_CHANNEL_2 PWM_POLARITY_INVERTED>;
-			label = "LED3";
-			frequency = <324>;
-		};
-	};
-};
-
-/* LED1 */
-&pwm0 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-};
-
-/* LED2 */
-&pwm1 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-};
-
-/* LED3 */
-&pwm2 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-};
diff --git a/zephyr/projects/asurada/hayato/src/i2c.c b/zephyr/projects/asurada/hayato/src/i2c.c
deleted file mode 100644
index 2c7a9c7130..0000000000
--- a/zephyr/projects/asurada/hayato/src/i2c.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c/i2c.h"
-#include "i2c.h"
-
-/* Hayato board specific i2c implementation */
-
-#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-int board_allow_i2c_passthru(int port)
-{
-	return (i2c_get_device_for_port(port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
-}
-#endif
diff --git a/zephyr/projects/asurada/hayato/zmake.yaml b/zephyr/projects/asurada/hayato/zmake.yaml
deleted file mode 100644
index f4e821d582..0000000000
--- a/zephyr/projects/asurada/hayato/zmake.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: asurada
-dts-overlays:
-  - battery.dts
-  - gpio.dts
-  - motionsense.dts
-  - pwm.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: binman
diff --git a/zephyr/projects/brya/brya/CMakeLists.txt b/zephyr/projects/brya/brya/CMakeLists.txt
deleted file mode 100644
index 59af20ebfe..0000000000
--- a/zephyr/projects/brya/brya/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(brya)
-
-zephyr_include_directories(include)
diff --git a/zephyr/projects/brya/brya/gpio.dts b/zephyr/projects/brya/brya/gpio.dts
deleted file mode 100644
index a472d7b8f7..0000000000
--- a/zephyr/projects/brya/brya/gpio.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		lid_open: lid_open {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-
-		gsc_ec_pwr_btn_odl: power_btn {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "GSC_EC_PWR_BTN_ODL";
-		};
-
-		wp_l {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "EC_WP_ODL";
-		};
-
-		ec_chg_led_y_c1 {
-			gpios = <&gpioc 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C1";
-			label = "EC_CHG_LED_Y_C1";
-		};
-
-		ec_chg_led_b_c1 {
-			gpios = <&gpioc 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_B_C1";
-			label = "EC_CHG_LED_B_C1";
-		};
-
-		packet_mode_en {
-			gpios = <&gpio7 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PACKET_MODE_EN";
-			label = "EC_GSC_PACKET_MODE";
-		};
-		acok_od: acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-		pch_wake_odl {
-			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "EC_PCH_WAKE_R_ODL";
-		};
-		pch_int_odl {
-			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "EC_PCH_INT_ODL";
-		};
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&acok_od
-			&gsc_ec_pwr_btn_odl
-			&lid_open
-		>;
-	};
-};
diff --git a/zephyr/projects/brya/brya/include/gpio_map.h b/zephyr/projects/brya/brya/include/gpio_map.h
deleted file mode 100644
index 2bc104c6b9..0000000000
--- a/zephyr/projects/brya/brya/include/gpio_map.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
-#define GPIO_WP_L		GPIO_UNIMPLEMENTED
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                           \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)        \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                 \
-		 power_button_interrupt)                                  \
-	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)         \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/brya/brya/prj.conf b/zephyr/projects/brya/brya/prj.conf
deleted file mode 100644
index b9dd1de26f..0000000000
--- a/zephyr/projects/brya/brya/prj.conf
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_LTO=y
-CONFIG_CROS_FLASH_NPCX=y
-CONFIG_CROS_SYSTEM_NPCX=y
-CONFIG_PLATFORM_EC_VBOOT_EFS2=y
-CONFIG_PLATFORM_EC_VBOOT_HASH=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
-CONFIG_PLATFORM_EC_I2C=y
-
-# eSPI, note that PLATFORM_EC_ESPI needs to be explicitly enabled because
-# CONFIG_AP is not yet enabled.
-CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI=y
-
-# Host command
-CONFIG_PLATFORM_EC_HOSTCMD=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
-CONFIG_PLATFORM_EC_CMD_BUTTON=n
-CONFIG_CROS_KB_RAW_NPCX=y
-
-CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
-
-CONFIG_SYSCON=y
-
-# TODO(b/188605676): bring these features up
-CONFIG_PLATFORM_EC_ADC=n
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
diff --git a/zephyr/projects/brya/brya/zmake.yaml b/zephyr/projects/brya/brya/zmake.yaml
deleted file mode 100644
index 71687e0f3e..0000000000
--- a/zephyr/projects/brya/brya/zmake.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: brya
-dts-overlays:
-  - gpio.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/guybrush/CMakeLists.txt b/zephyr/projects/guybrush/CMakeLists.txt
deleted file mode 100644
index b565aad308..0000000000
--- a/zephyr/projects/guybrush/CMakeLists.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(guybrush)
-
-zephyr_library_include_directories(include)
-
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/guybrush" CACHE PATH
-  "Path to the platform/ec baseboard directory")
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/guybrush" CACHE PATH
-  "Path to the platform/ec board directory")
-
-zephyr_library_sources("power_signals.c")
diff --git a/zephyr/projects/guybrush/gpio.dts b/zephyr/projects/guybrush/gpio.dts
deleted file mode 100644
index 221b5f7182..0000000000
--- a/zephyr/projects/guybrush/gpio.dts
+++ /dev/null
@@ -1,336 +0,0 @@
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		ec_wp_l {
-			gpios = <&gpio5 0 GPIO_INPUT>;
-			label = "EC_WP_L";
-			enum-name = "GPIO_WP_L";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioc 6 GPIO_ODR_HIGH>;
-			label = "CCD_MODE_ODL";
-		};
-		ec_gsc_packet_mode {
-			gpios = <&gpiob 1 GPIO_OUT_LOW>;
-			label = "EC_GSC_PACKET_MODE";
-		};
-		mech_pwr_btn_odl {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			label = "MECH_PWR_BTN_ODL";
-			enum-name = "GPIO_POWER_BUTTON_L";
-		};
-		ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			label = "EC_PWR_BTN_ODL";
-			enum-name = "GPIO_EC_PWR_BTN_ODL";
-		};
-		slp_s3_l {
-			gpios = <&gpio6 1 GPIO_INPUT>;
-			label = "SLP_S3_L";
-			enum-name = "GPIO_PCH_SLP_S3_L";
-		};
-		slp_s5_l {
-			gpios = <&gpio7 2 GPIO_INPUT>;
-			label = "SLP_S5_L";
-			enum-name = "GPIO_PCH_SLP_S5_L";
-		};
-		slp_s3_s0i3_l {
-			gpios = <&gpio7 4 GPIO_INPUT>;
-			label = "SLP_S3_S0I3_L";
-			enum-name = "GPIO_PCH_SLP_S0_L";
-		};
-		pg_pwr_s5 {
-			gpios = <&gpioc 0 GPIO_INPUT>;
-			label = "PG_PWR_S5";
-			enum-name = "GPIO_S5_PGOOD";
-		};
-		pg_pcore_s0_r_od {
-			gpios = <&gpiob 6 GPIO_INPUT>;
-			label = "PG_PCORE_S0_R_OD";
-			enum-name = "GPIO_S0_PGOOD";
-		};
-		acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			label = "ACOK_OD";
-			enum-name = "GPIO_AC_PRESENT";
-		};
-		ec_pcore_int_odl {
-			gpios = <&gpiof 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PCORE_INT_ODL";
-			enum-name = "GPIO_EC_PCORE_INT_ODL";
-		};
-		pg_groupc_s0_od {
-			gpios = <&gpioa 3 GPIO_INPUT>;
-			label = "PG_GROUPC_S0_OD";
-			enum-name = "GPIO_PG_GROUPC_S0_OD";
-		};
-		pg_lpddr4x_s3_od {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-			label = "PG_LPDDR4X_S3_OD";
-			enum-name = "GPIO_PG_LPDDR4X_S3_OD";
-		};
-		en_pwr_s5 {
-			gpios = <&gpiob 7 GPIO_OUT_LOW>;
-			label = "EN_PWR_S5";
-			enum-name = "GPIO_EN_PWR_A";
-		};
-		en_pwr_s0_r {
-			gpios = <&gpiof 1 GPIO_OUT_LOW>;
-			label = "EN_PWR_S0_R";
-			enum-name = "GPIO_EN_PWR_S0_R";
-		};
-		en_pwr_pcore_s0_r {
-			gpios = <&gpioe 1 GPIO_OUT_LOW>;
-			label = "EN_PWR_PCORE_S0_R";
-			enum-name = "GPIO_EN_PWR_PCORE_S0_R";
-		};
-		ec_entering_rw {
-			gpios = <&gpio6 6 GPIO_OUT_LOW>;
-			label = "EC_ENTERING_RW";
-			enum-name = "GPIO_ENTERING_RW";
-		};
-		ec_sys_rst_l {
-			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
-			label = "EC_SYS_RST_L";
-			enum-name = "GPIO_SYS_RESET_L";
-		};
-		ec_soc_rsmrst_l {
-			gpios = <&gpioc 5 GPIO_OUT_LOW>;
-			label = "EC_SOC_RSMRST_L";
-			enum-name = "GPIO_PCH_RSMRST_L";
-		};
-		ec_clr_cmos {
-			gpios = <&gpioa 1 GPIO_OUT_LOW>;
-			label = "EC_CLR_CMOS";
-		};
-		ec_mem_event {
-			gpios = <&gpioa 5 GPIO_OUT_LOW>;
-			label = "EC_MEM_EVENT";
-		};
-		ec_soc_pwr_btn_l {
-			gpios = <&gpio6 3 GPIO_OUT_HIGH>;
-			label = "EC_SOC_PWR_BTN_L";
-			enum-name = "GPIO_PCH_PWRBTN_L";
-		};
-		ec_soc_pwr_good {
-			gpios = <&gpiod 3 GPIO_OUT_LOW>;
-			label = "EC_SOC_PWR_GOOD";
-			enum-name = "GPIO_PCH_SYS_PWROK";
-		};
-		ec_soc_wake_l {
-			gpios = <&gpio0 3 GPIO_OUT_HIGH>;
-			label = "EC_SOC_WAKE_L";
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-		};
-		ec_soc_int_l {
-			gpios = <&gpio8 3 GPIO_OUT_HIGH>;
-			label = "EC_SOC_INT_L";
-		};
-		prochot_odl {
-			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
-			label = "PROCHOT_ODL";
-			enum-name = "GPIO_CPU_PROCHOT";
-		};
-		soc_alert_ec_l {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			label = "SOC_ALERT_EC_L";
-		};
-		soc_thermtrip_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			label = "SOC_THERMTRIP_ODL";
-		};
-		usb_c0_tcpc_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			label = "USB_C0_TCPC_INT_ODL";
-		};
-		usb_c1_tcpc_int_odl {
-			gpios = <&gpioc 7 GPIO_INPUT>;
-			label = "USB_C1_TCPC_INT_ODL";
-		};
-		usb_c0_ppc_int_odl {
-			gpios = <&gpio7 5 GPIO_INPUT>;
-			label = "USB_C0_PPC_INT_ODL";
-		};
-		usb_c1_ppc_int_odl {
-			gpios = <&gpiod 4 GPIO_INPUT>;
-			label = "USB_C1_PPC_INT_ODL";
-		};
-		usb_c0_bc12_int_odl {
-			gpios = <&gpioa 4 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "USB_C0_BC12_INT_ODL";
-		};
-		usb_c1_bc12_int_odl {
-			gpios = <&gpio9 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "USB_C1_BC12_INT_ODL";
-		};
-		usb_c0_c1_fault_odl {
-			gpios = <&gpio7 3 GPIO_ODR_HIGH>;
-			label = "USB_C0_C1_FAULT_ODL";
-		};
-		usb_c0_tcpc_rst_l {
-			gpios = <&gpio3 4 GPIO_OUT_HIGH>;
-			label = "USB_C0_TCPC_RST_L";
-		};
-		usb_c1_tcpc_rst_l {
-			gpios = <&gpio3 7 GPIO_OUT_HIGH>;
-			label = "USB_C1_TCPC_RST_L";
-		};
-		usb_c0_hpd {
-			gpios = <&gpiof 5 GPIO_OUT_LOW>;
-			label = "USB_C0_HPD";
-		};
-		usb_c1_hpd {
-			gpios = <&gpiof 4 GPIO_OUT_LOW>;
-			label = "USB_C1_HPD";
-		};
-		3axis_int_l {
-			gpios = <&gpioa 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "3AXIS_INT_L";
-		};
-		lid_open {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			label = "LID_OPEN";
-			enum-name = "GPIO_LID_OPEN";
-		};
-		voldn_btn_odl {
-			gpios = <&gpioa 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "VOLDN_BTN_ODL";
-			enum-name = "GPIO_VOLUME_DOWN_L";
-		};
-		volup_btn_odl {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "VOLUP_BTN_ODL";
-			enum-name = "GPIO_VOLUME_UP_L";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpio9 4 GPIO_INPUT>;
-			label = "EC_BATT_PRES_ODL";
-		};
-		ec_disable_disp_bl {
-			gpios = <&gpioa 6 GPIO_OUT_HIGH>;
-			label = "EC_DISABLE_DISP_BL";
-		};
-		ec_i2c_usb_a0_c0_scl {
-			gpios = <&gpiob 5 GPIO_INPUT>;
-			label = "EC_I2C_USB_A0_C0_SCL";
-		};
-		ec_i2c_usb_a0_c0_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			label = "EC_I2C_USB_A0_C0_SDA";
-		};
-		ec_i2c_usb_a1_c1_scl {
-			gpios = <&gpio9 0 GPIO_INPUT>;
-			label = "EC_I2C_USB_A1_C1_SCL";
-		};
-		ec_i2c_usb_a1_c1_sda {
-			gpios = <&gpio8 7 GPIO_INPUT>;
-			label = "EC_I2C_USB_A1_C1_SDA";
-		};
-		ec_i2c_batt_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
-			label = "EC_I2C_BATT_SCL";
-		};
-		ec_i2c_batt_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
-			label = "EC_I2C_BATT_SDA";
-		};
-		ec_i2c_usbc_mux_scl {
-			gpios = <&gpiod 1 GPIO_INPUT>;
-			label = "EC_I2C_USBC_MUX_SCL";
-		};
-		ec_i2c_usbc_mux_sda {
-			gpios = <&gpiod 0 GPIO_INPUT>;
-			label = "EC_I2C_USBC_MUX_SDA";
-		};
-		ec_i2c_power_scl {
-			gpios = <&gpiof 3 GPIO_INPUT>;
-			label = "EC_I2C_POWER_SCL";
-		};
-		ec_i2c_power_sda {
-			gpios = <&gpiof 2 GPIO_INPUT>;
-			label = "EC_I2C_POWER_SDA";
-		};
-		ec_i2c_cbi_scl {
-			gpios = <&gpio3 3 GPIO_INPUT>;
-			label = "EC_I2C_CBI_SCL";
-		};
-		ec_i2c_cbi_sda {
-			gpios = <&gpio3 6 GPIO_INPUT>;
-			label = "EC_I2C_CBI_SDA";
-		};
-		ec_i2c_sensor_scl {
-			gpios = <&gpioe 4 GPIO_INPUT>;
-			label = "EC_I2C_SENSOR_SCL";
-		};
-		ec_i2c_sensor_sda {
-			gpios = <&gpioe 3 GPIO_INPUT>;
-			label = "EC_I2C_SENSOR_SDA";
-		};
-		ec_i2c_soc_sic {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			label = "EC_I2C_SOC_SIC";
-		};
-		ec_i2c_soc_sid {
-			gpios = <&gpiob 2 GPIO_INPUT>;
-			label = "EC_I2C_SOC_SID";
-		};
-		en_kb_bl {
-			gpios = <&gpio9 7 GPIO_OUT_HIGH>;
-			label = "EN_KB_BL";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			label = "EC_KSO_02_INV";
-			enum-name = "GPIO_KBD_KSO2";
-		};
-		ec_espi_rst_l {
-			gpios = <&gpio5 4 GPIO_PULL_UP>;
-			label = "EC_ESPI_RST_L";
-		};
-		6axis_int_l {
-			gpios = <&gpioa 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "6AXIS_INT_L";
-		};
-		tablet_mode {
-			gpios = <&gpioc 1 GPIO_INPUT>;
-			label = "TABLET_MODE";
-		};
-		ec_gpio56 {
-			gpios = <&gpio5 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_GPIO56";
-		};
-		ec_ps2_clk {
-			gpios = <&gpio6 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PS2_CLK";
-		};
-		ec_ps2_dat {
-			gpios = <&gpio7 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PS2_DAT";
-		};
-		ec_ps2_rst {
-			gpios = <&gpio6 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PS2_RST";
-		};
-		ec_gpiob0 {
-			gpios = <&gpiob 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_GPIOB0";
-		};
-		ec_gpio81 {
-			gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_GPIO81";
-		};
-		ec_flprg2 {
-			gpios = <&gpio8 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_FLPRG2";
-		};
-		ec_psl_gpo {
-			gpios = <&gpiod 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PSL_GPO";
-		};
-		ec_pwm7 {
-			gpios = <&gpio6 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_PWM7";
-		};
-	};
-};
diff --git a/zephyr/projects/guybrush/include/gpio_map.h b/zephyr/projects/guybrush/include/gpio_map.h
deleted file mode 100644
index 5af244bead..0000000000
--- a/zephyr/projects/guybrush/include/gpio_map.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-/* Power input signals */
-enum power_signal {
-	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
-
-	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                              \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)           \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)    \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                    \
-		 power_button_interrupt)                                     \
-	GPIO_INT(GPIO_EC_PWR_BTN_ODL, GPIO_INT_EDGE_BOTH,                    \
-		 power_button_interrupt)                                     \
-	GPIO_INT(GPIO_PCH_SLP_S3_L, GPIO_INT_EDGE_BOTH, baseboard_en_pwr_s0) \
-	GPIO_INT(GPIO_PCH_SLP_S5_L, GPIO_INT_EDGE_BOTH,                      \
-		 power_signal_interrupt)                                     \
-	GPIO_INT(GPIO_PCH_SLP_S0_L, GPIO_INT_EDGE_BOTH,                      \
-		 power_signal_interrupt)                                     \
-	GPIO_INT(GPIO_S5_PGOOD, GPIO_INT_EDGE_BOTH, baseboard_en_pwr_s0)     \
-	GPIO_INT(GPIO_S0_PGOOD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)  \
-	GPIO_INT(GPIO_EC_PCORE_INT_ODL, GPIO_INT_EDGE_BOTH,                  \
-		 power_signal_interrupt)                                     \
-	GPIO_INT(GPIO_PG_GROUPC_S0_OD, GPIO_INT_EDGE_BOTH,                   \
-		 baseboard_en_pwr_pcore_s0)                                  \
-	GPIO_INT(GPIO_PG_LPDDR4X_S3_OD, GPIO_INT_EDGE_BOTH,                  \
-		 baseboard_en_pwr_pcore_s0)                                  \
-	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)     \
-	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/guybrush/power_signals.c b/zephyr/projects/guybrush/power_signals.c
deleted file mode 100644
index 7d5781d0cb..0000000000
--- a/zephyr/projects/guybrush/power_signals.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "chipset.h"
-#include "config.h"
-#include "gpio.h"
-#include "power.h"
-#include "timer.h"
-
-/* Wake Sources */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* Power Signal Input List */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_N] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-/**
- * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
- * PCH_PWRBTN_L.
- */
-void board_pwrbtn_to_pch(int level)
-{
-	timestamp_t start;
-	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
-
-	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
-	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
-		start = get_time();
-		do {
-			usleep(200);
-			if (gpio_get_level(GPIO_PCH_RSMRST_L))
-				break;
-		} while (time_since32(start) < timeout_rsmrst_rise_us);
-
-		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
-			ccprints("Error pwrbtn: RSMRST_L still low");
-
-		msleep(16);
-	}
-	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
-}
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
-	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
-		       gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
-		       gpio_get_level(GPIO_PG_GROUPC_S0_OD));
-}
-
-void baseboard_en_pwr_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
-	gpio_set_level(GPIO_EN_PWR_S0_R,
-		       gpio_get_level(GPIO_PCH_SLP_S3_L) &&
-		       gpio_get_level(GPIO_S5_PGOOD));
-
-	/* Now chain off to the normal power signal interrupt handler. */
-	power_signal_interrupt(signal);
-}
diff --git a/zephyr/projects/guybrush/prj.conf b/zephyr/projects/guybrush/prj.conf
deleted file mode 100644
index d9f2b31d2f..0000000000
--- a/zephyr/projects/guybrush/prj.conf
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_ESPI=y
-
-# Shell features
-CONFIG_SHELL_HELP=y
-CONFIG_SHELL_HISTORY=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-CONFIG_KERNEL_SHELL=y
-
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-# Power sequencing
-CONFIG_AP=y
-CONFIG_AP_X86_AMD=y
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y
-CONFIG_PLATFORM_EC_PORT80=y
-
-# Power button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-
-# External power
-CONFIG_PLATFORM_EC_HOSTCMD=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_SWITCH=n
-
-# Lid switch
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-
-CONFIG_SYSCON=y
-
-# This is not yet supported
-CONFIG_PLATFORM_EC_ADC=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
diff --git a/zephyr/projects/guybrush/zmake.yaml b/zephyr/projects/guybrush/zmake.yaml
deleted file mode 100644
index 386ff315bf..0000000000
--- a/zephyr/projects/guybrush/zmake.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: npcx9
-dts-overlays:
-  - gpio.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt b/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt
deleted file mode 100644
index dfccaf12c6..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(herobrine_npcx9)
-
-zephyr_library_include_directories(include)
-
-# Board specific implementation
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-  "src/usbc_config.c"
-  "src/usb_pd_policy.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-  "src/led.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
-  "src/i2c.c")
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/battery.dts b/zephyr/projects/herobrine/herobrine_npcx9/battery.dts
deleted file mode 100644
index ab4b28999a..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/battery.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	batteries {
-		default_battery: ap16l5j {
-			compatible = "panasonic,ap16l5j";
-		};
-	};
-};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts b/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
deleted file mode 100644
index 1f5052af04..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
+++ /dev/null
@@ -1,388 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		usb_c0_pd_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_PD_INT_ODL";
-			label = "USB_C0_PD_INT_ODL";
-		};
-		usb_c1_pd_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_PD_INT_ODL";
-			label = "USB_C1_PD_INT_ODL";
-		};
-		usb_c0_swctl_int_odl {
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
-			label = "USB_C0_SWCTL_INT_ODL";
-		};
-		usb_c1_swctl_int_odl {
-			gpios = <&gpio4 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
-			label = "USB_C1_SWCTL_INT_ODL";
-		};
-		usb_c0_bc12_int_l {
-			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C0_BC12_INT_L";
-			label = "USB_C0_BC12_INT_L";
-		};
-		usb_c1_bc12_int_l {
-			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C1_BC12_INT_L";
-			label = "USB_C1_BC12_INT_L";
-		};
-		usb_a0_oc_odl {
-			gpios = <&gpiof 4 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_A0_OC_ODL";
-			label = "USB_A0_OC_ODL";
-		};
-		gpio_chg_acok_od: chg_acok_od {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "CHG_ACOK_OD";
-		};
-		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "EC_PWR_BTN_ODL";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio6 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_UP_L";
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		ec_wp_odl {
-			gpios = <&gpiod 3 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "EC_WP_ODL";
-		};
-		gpio_lid_open_ec: lid_open_ec {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN_EC";
-		};
-		ap_rst_l {
-			gpios = <&gpio5 1 GPIO_INPUT>;
-			enum-name = "GPIO_AP_RST_L";
-			label = "AP_RST_L";
-		};
-		ps_hold {
-			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_PS_HOLD";
-			label = "PS_HOLD";
-		};
-		ap_suspend {
-			gpios = <&gpio5 7 GPIO_INPUT>;
-			enum-name = "GPIO_AP_SUSPEND";
-			label = "AP_SUSPEND";
-		};
-		power_good {
-			gpios = <&gpio3 7 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_POWER_GOOD";
-			label = "MB_POWER_GOOD";
-		};
-		warm_reset_l {
-			gpios = <&gpiob 0 GPIO_INPUT>;
-			enum-name = "GPIO_WARM_RESET_L";
-			label = "WARM_RESET_L";
-		};
-		ap_ec_spi_cs_l {
-			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CS_L";
-		};
-		tablet_mode_l {
-			gpios = <&gpioc 6 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		gpio_accel_gyro_int_l: accel_gyro_int_l {
-			gpios = <&gpioa 3 GPIO_INPUT>;
-			enum-name = "GPIO_ACCEL_GYRO_INT_L";
-			label = "ACCEL_GYRO_INT_L";
-		};
-		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
-			#gpio-cells = <0>;
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_RST_ODL";
-			label = "EC_RST_ODL";
-		};
-		ec_entering_rw {
-			gpios = <&gpio7 2 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "EC_ENTERING_RW";
-		};
-		ccd_mode_odl {
-			gpios = <&gpio6 3 GPIO_INPUT>;
-			enum-name = "GPIO_CCD_MODE_ODL";
-			label = "CCD_MODE_ODL";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		ec_gsc_packet_mode {
-			gpios = <&gpio8 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PACKET_MODE_EN";
-			label = "EC_GSC_PACKET_MODE";
-		};
-		pmic_resin_l {
-			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_RESIN_L";
-			label = "PMIC_RESIN_L";
-		};
-		pmic_kpd_pwr_odl {
-			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
-			label = "PMIC_KPD_PWR_ODL";
-		};
-		ap_ec_int_l {
-			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "AP_EC_INT_L";
-		};
-		gpio_switchcap_on: switchcap_on {
-			gpios = <&gpiod 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SWITCHCAP_ON";
-			label = "SWITCHCAP_ON";
-		};
-		en_pp5000_s5 {
-			gpios = <&gpio7 3 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000_S5";
-		};
-		ec_bl_disable_l {
-			gpios = <&gpiob 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EC_BL_DISABLE_L";
-		};
-		lid_accel_int_l {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_LID_ACCEL_INT_L";
-			label = "LID_ACCEL_INT_L";
-		};
-		tp_int_gate {
-			gpios = <&gpio7 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_TRACKPAD_INT_GATE";
-			label = "TP_INT_GATE";
-		};
-		usb_c0_pd_rst_l {
-			gpios = <&gpiof 1 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_USB_C0_PD_RST_L";
-			label = "USB_C0_PD_RST_L";
-		};
-		usb_c1_pd_rst_l {
-			gpios = <&gpioe 4 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_USB_C1_PD_RST_L";
-			label = "USB_C1_PD_RST_L";
-		};
-		dp_mux_oe_l {
-			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_DP_MUX_OE_L";
-			label = "DP_MUX_OE_L";
-		};
-		dp_mux_sel {
-			gpios = <&gpio4 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_MUX_SEL";
-			label = "DP_MUX_SEL";
-		};
-		dp_hot_plug_det_r {
-			gpios = <&gpio9 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_HOT_PLUG_DET";
-			label = "DP_HOT_PLUG_DET_R";
-		};
-		en_usb_a_5v {
-			gpios = <&gpiof 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_USB_A_5V";
-			label = "EN_USB_A_5V";
-		};
-		usb_a_cdp_ilim_en_l {
-			gpios = <&gpio7 5 GPIO_OUT_HIGH>;
-			label = "USB_A_CDP_ILIM_EN_L";
-		};
-		ec_chg_led_y_c0 {
-			gpios = <&gpio6 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C0";
-			label = "EC_CHG_LED_Y_C0";
-		};
-		ec_chg_led_w_c0 {
-			gpios = <&gpioc 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_W_C0";
-			label = "EC_CHG_LED_W_C0";
-		};
-		ec_chg_led_y_c1 {
-			gpios = <&gpioc 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C1";
-			label = "EC_CHG_LED_Y_C1";
-		};
-		ec_chg_led_w_c1 {
-			gpios = <&gpioc 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_W_C1";
-			label = "EC_CHG_LED_W_C1";
-		};
-		ap_ec_spi_mosi {
-			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MOSI";
-		};
-		ap_ec_spi_miso {
-			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MISO";
-		};
-		ap_ec_spi_clk {
-			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CLK";
-		};
-		gpio_brd_id0: brd_id0 {
-			gpios = <&gpio9 4 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION1";
-			label = "BRD_ID0";
-		};
-		gpio_brd_id1: brd_id1 {
-			gpios = <&gpio9 7 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION2";
-			label = "BRD_ID1";
-		};
-		gpio_brd_id2: brd_id2 {
-			gpios = <&gpioa 5 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION3";
-			label = "BRD_ID2";
-		};
-		gpio_sku_id0: sku_id0 {
-			gpios = <&gpio6 7 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID0";
-			label = "SKU_ID0";
-		};
-		gpio_sku_id1: sku_id1 {
-			gpios = <&gpio7 0 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID1";
-			label = "SKU_ID1";
-		};
-		gpio_sku_id2: sku_id2 {
-			gpios = <&gpioe 1 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID2";
-			label = "SKU_ID2";
-		};
-		gpio_switchcap_pg: src_vph_pwr_pg {
-			gpios = <&gpioe 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_SWITCHCAP_PG";
-			label = "SRC_VPH_PWR_PG";
-		};
-		arm_x86 {
-			gpios = <&gpio6 6 GPIO_OUT_LOW>;
-			label = "ARM_X86";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&gpio_chg_acok_od
-			&gpio_ec_pwr_btn_odl
-			&gpio_lid_open_ec
-			&gpio_rtc_ec_wake_odl
-		>;
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
-	};
-
-	sku {
-		compatible = "cros-ec,gpio-id";
-
-		bits  = <
-			&gpio_sku_id0
-			&gpio_sku_id1
-			&gpio_sku_id2
-		>;
-
-		system = "binary_first_base3";
-	};
-
-	board {
-		compatible = "cros-ec,gpio-id";
-
-		bits  = <
-			&gpio_brd_id0
-			&gpio_brd_id1
-			&gpio_brd_id2
-		>;
-
-		system = "binary_first_base3";
-	};
-
-	unused-pins {
-		compatible = "unused-gpios";
-		unused-gpios =
-			<&gpio5 2 0>,
-			<&gpio5 4 0>,
-			<&gpio7 6 0>,
-			<&gpioc 5 0>,
-			<&gpiod 1 0>,
-			<&gpiod 0 0>,
-			<&gpioe 3 0>,
-			<&gpioc 1 0>,
-			<&gpio0 4 0>,
-			<&gpiod 6 0>,
-			<&gpio3 2 0>,
-			<&gpio3 5 0>,
-			<&gpiod 7 0>,
-			<&gpio8 6 0>,
-			<&gpiod 4 0>,
-			<&gpio4 1 0>,
-			<&gpio3 4 0>,
-			<&gpioc 7 0>,
-			<&gpioa 4 0>,
-			<&gpio9 6 0>,
-			<&gpio9 3 0>,
-			<&gpioa 7 0>,
-			<&gpio5 0 0>,
-			<&gpio8 1 0>;
-	};
-};
-
-/* Power switch logic input pads */
-&psl_in1 {
-	/* ACOK_OD */
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&psl_in2 {
-	/* EC_PWR_BTN_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
-};
-
-&psl_in3 {
-	/* LID_OPEN_EC */
-	flag = <NPCX_PSL_RISING_EDGE>;
-};
-
-&psl_in4 {
-	/* RTC_EC_WAKE_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
-};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/i2c.dts b/zephyr/projects/herobrine/herobrine_npcx9/i2c.dts
deleted file mode 100644
index 0821f8b806..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/i2c.dts
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-4 = &i2c4_1;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		power {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_POWER";
-			label = "POWER";
-		};
-		battery {
-			i2c-port = <&i2c0_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		virtual {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_VIRTUAL";
-			label = "VIRTUAL";
-		};
-		charger {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "CHARGER";
-		};
-		tcpc0 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_TCPC0";
-			label = "TCPC0";
-		};
-		tcpc1 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_TCPC1";
-			label = "TCPC1";
-		};
-		rtc {
-			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_RTC";
-			label = "RTC";
-		};
-		eeprom {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-		accel {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL";
-		};
-	};
-
-
-};
-
-&i2c0_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-
-	isl9238: isl9238@9 {
-		compatible = "intersil,isl9238";
-		reg = <0x09>;
-		label = "ISL9238_CHARGER";
-	};
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	/*
-	 * TODO(b/200280341): PS8805 SPI ROM access
-	 *
-	 * The PS8805 supports 1 MHz during normal operation, but only
-	 * 400 Khz during firmware updates. The I2C passthru commands don't
-	 * currently support changing the I2C frequency or notifying the EC
-	 * that a programming operation is going to start.  Lower the clock
-	 * rate to 400 kHz for all accesses.
-	 */
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	/* TODO(b/200280341): PS8805 SPI ROM access */
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	/* Not used as no WLC connected */
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c4_1 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-
-	pcf85063a: pcf85063a@51 {
-		compatible = "nxp,rtc-pcf85063a";
-		reg = <0x51>;
-		label = "RTC_PCF85063A";
-		int-gpios = <&gpio_rtc_ec_wake_odl>;
-	};
-};
-
-&i2c_ctrl4 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h b/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h
deleted file mode 100644
index 00ab9bd98c..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#endif
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
-	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)             \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
-		 power_button_interrupt)                                      \
-	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt)    \
-	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)      \
-	GPIO_INT(GPIO_AP_RST_L, GPIO_INT_EDGE_BOTH, chipset_ap_rst_interrupt) \
-	GPIO_INT(GPIO_AP_SUSPEND, GPIO_INT_EDGE_BOTH, power_signal_interrupt) \
-	GPIO_INT(GPIO_POWER_GOOD, GPIO_INT_EDGE_BOTH, power_signal_interrupt) \
-	GPIO_INT(GPIO_PS_HOLD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)    \
-	GPIO_INT(GPIO_WARM_RESET_L, GPIO_INT_EDGE_BOTH,                       \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(GPIO_USB_C0_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C1_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C0_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C1_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C0_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb0_evt)     \
-	GPIO_INT(GPIO_USB_C1_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb1_evt)     \
-	GPIO_INT(GPIO_USB_A0_OC_ODL, GPIO_INT_EDGE_BOTH, usba_oc_interrupt)   \
-	GPIO_INT(GPIO_ACCEL_GYRO_INT_L, GPIO_INT_EDGE_FALLING,                \
-		 bmi260_interrupt)                                            \
-	GPIO_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH, gmr_tablet_switch_isr)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h b/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h
deleted file mode 100644
index e704b6d6d3..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_PWM_MAP_H
-#define __ZEPHYR_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "pwm/pwm.h"
-
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-#define PWM_CH_DISPLIGHT	NAMED_PWM(displight)
-
-#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts b/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts
deleted file mode 100644
index 977c27bfc3..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi260-int = &base_accel;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
-		};
-
-		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <0 1 0
-				 (-1) 0 0
-				 0 0 1>;
-		};
-
-		base_rot_ref: base-rotation-ref {
-			mat33 = <1 0 0
-				 0 (-1) 0
-				 0 0 (-1)>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bma255_data: bma255-drv-data {
-			compatible = "cros-ec,drvdata-bma255";
-			status = "okay";
-		};
-
-		bmi260_data: bmi260-drv-data {
-			compatible = "cros-ec,drvdata-bmi260";
-			status = "okay";
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,bma255";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&bma255_data>;
-			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi260-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi260_data>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi260-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi260_data>;
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_accel_gyro_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel>;
-	};
-};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
deleted file mode 100644
index 8c8576c78f..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
+++ /dev/null
@@ -1,168 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_I2C=y
-CONFIG_KERNEL_SHELL=y
-
-# Shell history and tab autocompletion (for convenience)
-CONFIG_SHELL_HELP=y
-CONFIG_SHELL_HISTORY=y
-CONFIG_SHELL_TAB=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-
-# Miscellaneous configs
-CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
-
-# LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-CONFIG_PLATFORM_EC_PWM_DISPLIGHT=y
-CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
-
-# Application Processor is Qualcomm SC7280
-CONFIG_AP_ARM_QUALCOMM_SC7280=y
-
-# GPIO Switchcap
-CONFIG_PLATFORM_EC_SWITCHCAP_GPIO=y
-
-# Board version is selected over GPIO board ID pins.
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
-CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
-CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
-CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
-CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
-
-# TODO(b:193719620): Enable EC EFS2.
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-# MKBP event mask
-CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
-CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
-
-# MKBP event
-CONFIG_PLATFORM_EC_MKBP_EVENT=y
-CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
-CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-CONFIG_PLATFORM_EC_CMD_BUTTON=y
-CONFIG_CROS_KB_RAW_NPCX=y
-
-# ADC
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# Battery
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
-CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
-CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
-CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
-CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
-CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
-CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-
-# USB-A
-CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
-
-# USB-C
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
-CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
-CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n
-CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
-CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT=2
-CONFIG_PLATFORM_EC_USB_PD_REV30=n
-CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
-CONFIG_HAS_TASK_PD_C1=y
-CONFIG_HAS_TASK_PD_INT_C1=y
-
-# USB ID
-# This is allocated specifically for Herobrine
-# http://google3/hardware/standards/usb/
-# TODO(b/183608112): Move to device tree
-CONFIG_PLATFORM_EC_USB_PID=0x5055
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-CONFIG_CROS_RTC_NXP_PCF85063A=y
-CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM=y
-
-# EC software sync
-CONFIG_PLATFORM_EC_VBOOT_HASH=y
-
-# Serial Host Interface (SHI) device.
-CONFIG_CROS_SHI_NPCX=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-
-CONFIG_SYSCON=y
-
-# Features should be enabled. But the code RAM is not enough, disable them.
-#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
-#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c b/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c
deleted file mode 100644
index f78ea56513..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c/i2c.h"
-#include "i2c.h"
-
-/* Herobrine-NPCX9 board specific i2c implementation */
-
-#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-int board_allow_i2c_passthru(int port)
-{
-	return (i2c_get_device_for_port(port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
-}
-#endif
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/led.c b/zephyr/projects/herobrine/herobrine_npcx9/src/led.c
deleted file mode 100644
index 295c8effeb..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/src/led.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_LEFT_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void side_led_set_color(int port, enum led_color color)
-{
-	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_WHITE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	int port;
-
-	switch (led_id) {
-	case EC_LED_ID_RIGHT_LED:
-		port = 0;
-		break;
-	case EC_LED_ID_LEFT_LED:
-		port = 1;
-		break;
-	default:
-		return EC_ERROR_PARAM1;
-	}
-
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		side_led_set_color(port, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		side_led_set_color(port, LED_AMBER);
-	else
-		side_led_set_color(port, LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-/*
- * Set active charge port color to the parameter, turn off all others.
- * If no port is active (-1), turn off all LEDs.
- */
-static void set_active_port_color(enum led_color color)
-{
-	int port = charge_manager_get_active_charge_port();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		side_led_set_color(0, (port == 0) ? color : LED_OFF);
-	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		side_led_set_color(1, (port == 1) ? color : LED_OFF);
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate when charging, even in suspend. */
-		set_active_port_color(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
-			else
-				side_led_set_color(0, LED_OFF);
-		}
-
-		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(1, LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_LEFT_LED, 1);
-		led_auto_control(EC_LED_ID_RIGHT_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_WHITE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_LEFT_LED, 0);
-	led_auto_control(EC_LED_ID_RIGHT_LED, 0);
-
-	side_led_set_color(0, color);
-	side_led_set_color(1, color);
-}
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/usb_pd_policy.c b/zephyr/projects/herobrine/herobrine_npcx9/src/usb_pd_policy.c
deleted file mode 100644
index 7ca2688aef..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/src/usb_pd_policy.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* In G3, do not allow vconn swap since PP5000 rail is off */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-#if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
-#else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
-#endif
-
-static void board_vbus_update_source_current(int port)
-{
-	/* Both port are controlled by PPC SN5S330. */
-	ppc_set_vbus_source_current_limit(port, vbus_rp[port]);
-	ppc_vbus_source_enable(port, vbus_en[port]);
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = vbus_en[port];
-
-	/* Disable VBUS */
-	vbus_en[port] = 0;
-	board_vbus_update_source_current(port);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	/* Disable charging */
-	board_vbus_sink_enable(port, 0);
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide VBUS */
-	vbus_en[port] = 1;
-	board_vbus_update_source_current(port);
-
-	/* notify host of power info change */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS; /* we are ready */
-}
-
-int board_vbus_source_enabled(int port)
-{
-	return vbus_en[port];
-}
-
-__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
-{
-	vbus_rp[port] = rp;
-	board_vbus_update_source_current(port);
-}
-
-int pd_snk_is_vbus_provided(int port)
-{
-	return tcpm_check_vbus_level(port, VBUS_PRESENT);
-}
-
-/* ----------------- Vendor Defined Messages ------------------ */
-#ifdef CONFIG_USB_PD_ALT_MODE_DFP
-__override int svdm_dp_config(int port, uint32_t *payload)
-{
-	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
-	uint8_t pin_mode = get_dp_pin_mode(port);
-
-	if (!pin_mode)
-		return 0;
-
-	/*
-	 * Defer setting the usb_mux until HPD goes high, svdm_dp_attention().
-	 * The AP only supports one DP phy. An external DP mux switches between
-	 * the two ports. Should switch those muxes when it is really used,
-	 * i.e. HPD high; otherwise, the real use case is preempted, like:
-	 *  (1) plug a dongle without monitor connected to port-0,
-	 *  (2) plug a dongle without monitor connected to port-1,
-	 *  (3) plug a monitor to the port-1 dongle.
-	 */
-
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
-	return 2;
-};
-
-__override void svdm_dp_post_config(int port)
-{
-	dp_flags[port] |= DP_FLAGS_DP_ON;
-}
-
-/**
- * Is the port fine to be muxed its DisplayPort lines?
- *
- * Only one port can be muxed to DisplayPort at a time.
- *
- * @param port	Port number of TCPC.
- * @return	1 is fine; 0 is bad as other port is already muxed;
- */
-static int is_dp_muxable(int port)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
-		if (i != port) {
-			if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED)
-				return 0;
-		}
-
-	return 1;
-}
-
-__override int svdm_dp_attention(int port, uint32_t *payload)
-{
-	enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET;
-	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
-	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	int cur_lvl = gpio_get_level(hpd);
-	mux_state_t mux_state;
-
-	dp_status[port] = payload[1];
-
-	if (!is_dp_muxable(port)) {
-		/* TODO(waihong): Info user? */
-		CPRINTS("p%d: The other port is already muxed.", port);
-		return 0;
-	}
-
-	/*
-	 * Initial implementation to handle HPD. Only the first-plugged port
-	 * works, i.e. sending HPD signal to AP. The second-plugged port
-	 * will be ignored.
-	 *
-	 * TODO(waihong): Continue the above case, if the first-plugged port
-	 * is then unplugged, switch to the second-plugged port and signal AP?
-	 */
-	if (lvl) {
-		/*
-		 * Enable and switch the DP port selection mux to the
-		 * correct port.
-		 *
-		 * TODO(waihong): Better to move switching DP mux to
-		 * the usb_mux abstraction.
-		 */
-		gpio_set_level(GPIO_DP_MUX_SEL, port == 1);
-		gpio_set_level(GPIO_DP_MUX_OE_L, 0);
-
-		/* Connect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 1);
-
-		/*
-		 * Connect the USB SS/DP lines in TCPC chip.
-		 *
-		 * When mf_pref not true, still use the dock muxing
-		 * because of the board USB-C topology (limited to 2
-		 * lanes DP).
-		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	} else {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Disconnect the SBU lines in PPC chip. */
-		if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-			ppc_set_sbu(port, 0);
-
-		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
-			    polarity_rm_dts(pd_get_polarity(port)));
-	}
-
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
-		/*
-		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
-		 * present.
-		 */
-		pd_notify_dp_alt_mode_entry(port);
-
-	/* Configure TCPC for the HPD event, for proper muxing */
-	mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
-		    (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
-	usb_mux_hpd_update(port, mux_state);
-
-	/* Signal AP for the HPD event, through GPIO to AP */
-	if (irq & cur_lvl) {
-		uint64_t now = get_time().val;
-		/* Wait for the minimum spacing between IRQ_HPD if needed */
-		if (now < svdm_hpd_deadline[port])
-			usleep(svdm_hpd_deadline[port] - now);
-
-		/* Generate IRQ_HPD pulse */
-		gpio_set_level(hpd, 0);
-		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
-		gpio_set_level(hpd, 1);
-
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	} else if (irq & !lvl) {
-		CPRINTF("ERR:HPD:IRQ&LOW\n");
-		return 0;
-	} else {
-		gpio_set_level(hpd, lvl);
-		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
-	}
-
-	return 1;
-}
-
-__override void svdm_exit_dp_mode(int port)
-{
-	if (is_dp_muxable(port)) {
-		/* Disconnect the DP port selection mux. */
-		gpio_set_level(GPIO_DP_MUX_OE_L, 1);
-		gpio_set_level(GPIO_DP_MUX_SEL, 0);
-
-		/* Signal AP for the HPD low event */
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
-	}
-}
-#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/usbc_config.c b/zephyr/projects/herobrine/herobrine_npcx9/src/usbc_config.c
deleted file mode 100644
index 20646c28c2..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/src/usbc_config.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Herobrine board-specific USB-C configuration */
-
-#include "bc12/pi3usb9201_public.h"
-#include "charger.h"
-#include "charger/isl923x_public.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "common.h"
-#include "config.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "ppc/sn5s330_public.h"
-#include "system.h"
-#include "tcpm/ps8xxx_public.h"
-#include "tcpm/tcpci.h"
-#include "timer.h"
-#include "usb_pd.h"
-#include "usb_mux.h"
-#include "usbc_ocp.h"
-#include "usbc_ppc.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-
-/* GPIO Interrupt Handlers */
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port = -1;
-
-	switch (signal) {
-	case GPIO_USB_C0_PD_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_PD_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-void usb0_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-}
-
-void usb1_evt(enum gpio_signal signal)
-{
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-}
-
-static void usba_oc_deferred(void)
-{
-	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_get_level(GPIO_USB_A0_OC_ODL));
-}
-DECLARE_DEFERRED(usba_oc_deferred);
-
-void usba_oc_interrupt(enum gpio_signal signal)
-{
-	hook_call_deferred(&usba_oc_deferred_data, 0);
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_SWCTL_INT_ODL:
-		sn5s330_interrupt(0);
-		break;
-	case GPIO_USB_C1_SWCTL_INT_ODL:
-		sn5s330_interrupt(1);
-		break;
-	default:
-		break;
-	}
-}
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	},
-};
-
-int charger_profile_override(struct charge_state_data *curr)
-{
-	int usb_mv;
-	int port;
-
-	if (curr->state != ST_CHARGE)
-		return 0;
-
-	/* Lower the max requested voltage to 5V when battery is full. */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-	    !(curr->batt.flags & BATT_FLAG_BAD_STATUS) &&
-	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-	    (curr->batt.status & STATUS_FULLY_CHARGED))
-		usb_mv = 5000;
-	else
-		usb_mv = PD_MAX_VOLTAGE_MV;
-
-	if (pd_get_max_voltage() != usb_mv) {
-		CPRINTS("VBUS limited to %dmV", usb_mv);
-		for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++)
-			pd_set_external_voltage_limit(port, usb_mv);
-	}
-
-	return 0;
-}
-
-enum ec_status charger_profile_override_get_param(uint32_t param,
-						  uint32_t *value)
-{
-	return EC_RES_INVALID_PARAM;
-}
-
-enum ec_status charger_profile_override_set_param(uint32_t param,
-						  uint32_t value)
-{
-	return EC_RES_INVALID_PARAM;
-}/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* TCPC mux configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = PS8751_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-
-/*
- * Port-0/1 USB mux driver.
- *
- * The USB mux is handled by TCPC chip and the HPD update is through a GPIO
- * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
- * the mux misbehaves.
- */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	}
-};
-
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A_5V,
-};
-
-/* BC1.2 */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_POWER,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	{
-		.i2c_port = I2C_PORT_EEPROM,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-
-/* Initialize board USC-C things */
-static void board_init_usbc(void)
-{
-	/* Enable BC1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
-
-	/* Enable USB-A overcurrent interrupt */
-	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT);
-
-void board_tcpc_init(void)
-{
-	/* Only reset TCPC if not sysjump */
-	if (!system_jumped_late()) {
-		/* TODO(crosbug.com/p/61098): How long do we need to wait? */
-		board_reset_pd_mcu();
-	}
-
-	/* Enable PPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
-
-	/* Enable TCPC interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
-
-	/*
-	 * Initialize HPD to low; after sysjump SOC needs to see
-	 * HPD pulse to enable video path
-	 */
-	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
-		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-void board_reset_pd_mcu(void)
-{
-	cprints(CC_USB, "Resetting TCPCs...");
-	cflush();
-
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
-	msleep(PS8XXX_RESET_DELAY_MS);
-	gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
-	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
-	msleep(PS8805_FW_INIT_DELAY_MS);
-}
-
-void board_set_tcpc_power_mode(int port, int mode)
-{
-	/* Ignore the "mode" to turn the chip on.  We can only do a reset. */
-	if (mode)
-		return;
-
-	board_reset_pd_mcu();
-}
-
-int board_vbus_sink_enable(int port, int enable)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_vbus_sink_enable(port, enable);
-}
-
-int board_is_sourcing_vbus(int port)
-{
-	/* Both ports are controlled by PPC SN5S330 */
-	return ppc_is_sourcing_vbus(port);
-}
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	/* TODO(b/120231371): Notify AP */
-	CPRINTS("p%d: overcurrent!", port);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_real_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTS("Disabling all charging port");
-
-		/* Disable all ports. */
-		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (board_vbus_sink_enable(i, 0))
-				CPRINTS("Disabling p%d sink path failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (board_is_sourcing_vbus(port)) {
-		CPRINTS("Skip enable p%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-
-	CPRINTS("New charge port: p%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if (i == port)
-			continue;
-
-		if (board_vbus_sink_enable(i, 0))
-			CPRINTS("p%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (board_vbus_sink_enable(port, 1)) {
-		CPRINTS("p%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	/*
-	 * Ignore lower charge ceiling on PD transition if our battery is
-	 * critical, as we may brownout.
-	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
-	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-		CPRINTS("Using max ilim %d", max_ma);
-		charge_ma = max_ma;
-	}
-
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C0_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_0;
-	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL))
-		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
-			status |= PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/switchcap.dts b/zephyr/projects/herobrine/herobrine_npcx9/switchcap.dts
deleted file mode 100644
index b246274a7a..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/switchcap.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	switchcap {
-		compatible = "switchcap-gpio";
-		enable-pin = <&gpio_switchcap_on>;
-		power-good-pin = <&gpio_switchcap_pg>;
-	};
-};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml b/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml
deleted file mode 100644
index 775ab65ead..0000000000
--- a/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: herobrine_npcx9
-dts-overlays:
-  - gpio.dts
-  - battery.dts
-  - i2c.dts
-  - motionsense.dts
-  - switchcap.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/it8xxx2_evb/CMakeLists.txt b/zephyr/projects/it8xxx2_evb/CMakeLists.txt
deleted file mode 100644
index dc2eb449b0..0000000000
--- a/zephyr/projects/it8xxx2_evb/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(it8xxx2_evb)
-
-# Include board specific header files
-zephyr_include_directories(include)
diff --git a/zephyr/projects/it8xxx2_evb/include/gpio_map.h b/zephyr/projects/it8xxx2_evb/include/gpio_map.h
deleted file mode 100644
index c92b71d523..0000000000
--- a/zephyr/projects/it8xxx2_evb/include/gpio_map.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
-#define GPIO_WP_L		GPIO_UNIMPLEMENTED
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS						\
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)	\
-	GPIO_INT(GPIO_POWER_BUTTON_L,					\
-		 GPIO_INT_EDGE_BOTH, power_button_interrupt)		\
-	GPIO_INT(GPIO_SPI0_CS,						\
-		 GPIO_INT_EDGE_FALLING, spi_event)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/it8xxx2_evb/include/i2c_map.h b/zephyr/projects/it8xxx2_evb/include/i2c_map.h
deleted file mode 100644
index 9d1fc1ca36..0000000000
--- a/zephyr/projects/it8xxx2_evb/include/i2c_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_CHROME_I2C_MAP_H
-#define __ZEPHYR_CHROME_I2C_MAP_H
-
-#include <devicetree.h>
-
-#include "config.h"
-
-/* We need registers.h to get the chip specific defines for now */
-#include "i2c/i2c.h"
-
-#endif /* __ZEPHYR_CHROME_I2C_MAP_H */
diff --git a/zephyr/projects/it8xxx2_evb/include/pwm_map.h b/zephyr/projects/it8xxx2_evb/include/pwm_map.h
deleted file mode 100644
index 531b86ccf6..0000000000
--- a/zephyr/projects/it8xxx2_evb/include/pwm_map.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_CHROME_PWM_MAP_H
-#define __ZEPHYR_CHROME_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "config.h"
-
-#include "pwm/pwm.h"
-
-/*
- * TODO(b/177452529): eliminate the dependency on enum pwm_channel
- * and configure this information directly from the device tree.
- */
-#define PWM_CH_FAN		NAMED_PWM(test0)
-#define PWM_CH_WITH_DSLEEP_FLAG	NAMED_PWM(test1)
-
-#endif /* __ZEPHYR_CHROME_PWM_MAP_H */
diff --git a/zephyr/projects/it8xxx2_evb/prj.conf b/zephyr/projects/it8xxx2_evb/prj.conf
deleted file mode 100644
index 23a7ab2275..0000000000
--- a/zephyr/projects/it8xxx2_evb/prj.conf
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-
-# SoC configuration
-CONFIG_AP=y
-CONFIG_AP_ARM_MTK_MT8192=y
-
-# ADC
-CONFIG_PLATFORM_EC_ADC=y
-
-# I2C
-CONFIG_PLATFORM_EC_I2C=y
-
-# Flash
-CONFIG_PLATFORM_EC_FLASH_CROS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
-
-# Lid switch
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-
-# Power button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-
-# Logging
-CONFIG_LOG=y
-
-# TODO(b:185202623): bring these features up
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
-CONFIG_PLATFORM_EC_KEYBOARD=n
-CONFIG_CROS_KB_RAW_ITE=n
-CONFIG_PLATFORM_EC_SWITCH=n
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-CONFIG_PLATFORM_EC_VBOOT_HASH=n
diff --git a/zephyr/projects/it8xxx2_evb/zmake.yaml b/zephyr/projects/it8xxx2_evb/zmake.yaml
deleted file mode 100644
index d05a938500..0000000000
--- a/zephyr/projects/it8xxx2_evb/zmake.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: it8xxx2_evb
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: raw
diff --git a/zephyr/projects/kohaku/CMakeLists.txt b/zephyr/projects/kohaku/CMakeLists.txt
deleted file mode 100644
index 5a8c045731..0000000000
--- a/zephyr/projects/kohaku/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(kohaku)
-
-zephyr_library_include_directories(include)
diff --git a/zephyr/projects/kohaku/include/gpio_map.h b/zephyr/projects/kohaku/include/gpio_map.h
deleted file mode 100644
index 05fc93d5d5..0000000000
--- a/zephyr/projects/kohaku/include/gpio_map.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-/* Cometlake power sequencing requires this definition */
-#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(NAMED_GPIO(lid_open), GPIO_INT_EDGE_BOTH, lid_interrupt)     \
-	GPIO_INT(NAMED_GPIO(power_button_l), GPIO_INT_EDGE_BOTH,              \
-		 power_button_interrupt)                                      \
-	GPIO_INT(NAMED_GPIO(acok_od), GPIO_INT_EDGE_BOTH, extpower_interrupt) \
-	GPIO_INT(NAMED_GPIO(slp_s0_l), GPIO_INT_EDGE_BOTH,                    \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(NAMED_GPIO(slp_s3_l), GPIO_INT_EDGE_BOTH,                    \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(NAMED_GPIO(slp_s4_l), GPIO_INT_EDGE_BOTH,                    \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(NAMED_GPIO(pg_ec_rsmrst_l), GPIO_INT_EDGE_BOTH,              \
-		 intel_x86_rsmrst_signal_interrupt)                           \
-	GPIO_INT(NAMED_GPIO(pg_ec_all_sys_pwrgd), GPIO_INT_EDGE_BOTH,         \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(NAMED_GPIO(pp5000_a_pg_od), GPIO_INT_EDGE_BOTH,              \
-		 power_signal_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/kohaku/prj.conf b/zephyr/projects/kohaku/prj.conf
deleted file mode 100644
index 48d512fc39..0000000000
--- a/zephyr/projects/kohaku/prj.conf
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-
-CONFIG_ESPI=y
-CONFIG_I2C=y
-
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-# Power sequencing
-CONFIG_AP=y
-CONFIG_AP_X86_INTEL_CML=y
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
-
-# Power button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_HAS_TASK_POWERBTN=y
-
-# External power
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-
-# Lid switch
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-
-CONFIG_PLATFORM_EC_KEYBOARD=n
-CONFIG_CROS_KB_RAW_NPCX=n
-
-# This is not yet supported
-CONFIG_PLATFORM_EC_ADC=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
-
-CONFIG_SYSCON=y
diff --git a/zephyr/projects/kohaku/zmake.yaml b/zephyr/projects/kohaku/zmake.yaml
deleted file mode 100644
index 99e4f135fb..0000000000
--- a/zephyr/projects/kohaku/zmake.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: kohaku
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
deleted file mode 100644
index a61ddf6755..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(npcx7)
-
-zephyr_include_directories(include)
diff --git a/zephyr/projects/npcx_evb/npcx7/fan.dts b/zephyr/projects/npcx_evb/npcx7/fan.dts
deleted file mode 100644
index de2852d73a..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/fan.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-fans {
-		compatible = "named-fans";
-
-		fan_0 {
-			label = "FAN_0";
-			pwm = <&pwm_fan>;
-			rpm_min = <1000>;
-			rpm_start = <1000>;
-			rpm_max = <5200>;
-			tach = <&tach1>;
-			pgood_gpio = <&gpio_pgood_fan>;
-		};
-	};
-};
-
-/* Tachometer for fan speed measurement */
-&tach1 {
-	status = "okay";
-	pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1 as input pin */
-	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
-	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
-	pulses-per-round = <2>; /* number of pulses per round of encoder */
-};
diff --git a/zephyr/projects/npcx_evb/npcx7/gpio.dts b/zephyr/projects/npcx_evb/npcx7/gpio.dts
deleted file mode 100644
index fb8f83803f..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/gpio.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		recovery_l {
-			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "RECOVERY_L";
-		};
-		wp_l {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		gpio_ac_present: ac_present {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "AC_PRESENT";
-		};
-		gpio_power_button_l: power_button_l {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "POWER_BUTTON_L";
-		};
-		gpio_lid_open: lid_open {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-		entering_rw {
-			gpios = <&gpio3 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "ENTERING_RW";
-		};
-		pch_wake_l {
-			gpios = <&gpio5 0 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "PCH_WAKE_L";
-		};
-		gpio_pgood_fan: pgood_fan {
-			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_PGOOD_FAN";
-			label = "PGOOD_FAN";
-		};
-		spi_cs_l {
-			gpios = <&gpioa 5 GPIO_OUT_HIGH>;
-			label = "SPI_CS_L";
-		};
-		board_version1 {
-			gpios = <&gpio6 4 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION1";
-			label = "BOARD_VERSION1";
-		};
-		board_version2 {
-			gpios = <&gpio6 5 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION2";
-			label = "BOARD_VERSION2";
-		};
-		board_version3 {
-			gpios = <&gpio6 6 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION3";
-			label = "BOARD_VERSION3";
-		};
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&gpio_ac_present
-			&gpio_power_button_l
-			&gpio_lid_open
-		>;
-	};
-};
diff --git a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
deleted file mode 100644
index 741cbd89a2..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_KBD_KSO2		GPIO_UNIMPLEMENTED
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
-		 power_button_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx7/include/pwm_map.h b/zephyr/projects/npcx_evb/npcx7/include/pwm_map.h
deleted file mode 100644
index 371e95c116..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/include/pwm_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_PWM_MAP_H
-#define __ZEPHYR_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "pwm/pwm.h"
-
-#define PWM_CH_FAN		NAMED_PWM(fan)
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-
-#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx7/keyboard.dts b/zephyr/projects/npcx_evb/npcx7/keyboard.dts
deleted file mode 100644
index fdeee3c02c..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/keyboard.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	cros-keyscan {
-		compatible = "cros-keyscan";
-
-		output-settle = <40>;
-		debounce-down = <6000>;
-		scan-period = <1500>;
-		poll-timeout = <1000000>;
-
-		actual-key-mask = <
-			0x14	/* C0 */
-			0xff	/* C1 */
-			0xff	/* C2 */
-			0xff	/* C3 */
-			0xff	/* C4 */
-			0xf5	/* C5 */
-			0xff	/* C6 */
-			0xa4	/* C7 */
-			0xff	/* C8 */
-			0xf6	/* C9 */
-			0x55	/* C10 */
-			0xfa	/* C11 */
-			0xc8	/* C12 */
-			>;
-	};
-};
diff --git a/zephyr/projects/npcx_evb/npcx7/prj.conf b/zephyr/projects/npcx_evb/npcx7/prj.conf
deleted file mode 100644
index d05c6174cf..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/prj.conf
+++ /dev/null
@@ -1,55 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_SHIMMED_TASKS=y
-
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_SWITCH=n
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-CONFIG_PLATFORM_EC_VSTORE=n
-
-# Board version is selected over GPIO board ID pins.
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
-
-# PWM
-CONFIG_PLATFORM_EC_PWM=y
-
-# Fan
-CONFIG_SENSOR=y
-CONFIG_SENSOR_SHELL=n
-CONFIG_PLATFORM_EC_FAN=y
-
-# Console command
-CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y
-
-# eSPI
-CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-
-# Keyboard
-CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
-
-# Zephyr feature
-CONFIG_ASSERT=y
-CONFIG_SHELL_MINIMAL=n
-CONFIG_LOG=y
-
-# Avoid underflow info from tachometer
-CONFIG_SENSOR_LOG_LEVEL_ERR=y
-
-# Avoid info storm from power management
-CONFIG_SOC_LOG_LEVEL_ERR=y
-
-CONFIG_SYSCON=y
diff --git a/zephyr/projects/npcx_evb/npcx7/pwm.dts b/zephyr/projects/npcx_evb/npcx7/pwm.dts
deleted file mode 100644
index 144b4d96b9..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/pwm.dts
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-pwms {
-		compatible = "named-pwms";
-
-		pwm_fan: fan {
-			pwms = <&pwm0 0 0>;
-			label = "FAN";
-			frequency = <25000>;
-		};
-		kblight {
-			pwms = <&pwm2 0 0>;
-			label = "KBLIGHT";
-			frequency = <10000>;
-		};
-	};
-};
-
-/* fan */
-&pwm0 {
-	status = "okay";
-	drive-open-drain;
-};
-
-/* kblight */
-&pwm2 {
-	status = "okay";
-};
diff --git a/zephyr/projects/npcx_evb/npcx7/zmake.yaml b/zephyr/projects/npcx_evb/npcx7/zmake.yaml
deleted file mode 100644
index e846e582e7..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/zmake.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: npcx7_evb
-dts-overlays:
-  - gpio.dts
-  - pwm.dts
-  - fan.dts
-  - keyboard.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt
deleted file mode 100644
index a81ae87820..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(npcx9)
-
-zephyr_include_directories(include)
diff --git a/zephyr/projects/npcx_evb/npcx9/fan.dts b/zephyr/projects/npcx_evb/npcx9/fan.dts
deleted file mode 100644
index de2852d73a..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/fan.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-fans {
-		compatible = "named-fans";
-
-		fan_0 {
-			label = "FAN_0";
-			pwm = <&pwm_fan>;
-			rpm_min = <1000>;
-			rpm_start = <1000>;
-			rpm_max = <5200>;
-			tach = <&tach1>;
-			pgood_gpio = <&gpio_pgood_fan>;
-		};
-	};
-};
-
-/* Tachometer for fan speed measurement */
-&tach1 {
-	status = "okay";
-	pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1 as input pin */
-	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
-	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
-	pulses-per-round = <2>; /* number of pulses per round of encoder */
-};
diff --git a/zephyr/projects/npcx_evb/npcx9/gpio.dts b/zephyr/projects/npcx_evb/npcx9/gpio.dts
deleted file mode 100644
index fb8f83803f..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/gpio.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		recovery_l {
-			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "RECOVERY_L";
-		};
-		wp_l {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		gpio_ac_present: ac_present {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "AC_PRESENT";
-		};
-		gpio_power_button_l: power_button_l {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "POWER_BUTTON_L";
-		};
-		gpio_lid_open: lid_open {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN";
-		};
-		entering_rw {
-			gpios = <&gpio3 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "ENTERING_RW";
-		};
-		pch_wake_l {
-			gpios = <&gpio5 0 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "PCH_WAKE_L";
-		};
-		gpio_pgood_fan: pgood_fan {
-			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_PGOOD_FAN";
-			label = "PGOOD_FAN";
-		};
-		spi_cs_l {
-			gpios = <&gpioa 5 GPIO_OUT_HIGH>;
-			label = "SPI_CS_L";
-		};
-		board_version1 {
-			gpios = <&gpio6 4 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION1";
-			label = "BOARD_VERSION1";
-		};
-		board_version2 {
-			gpios = <&gpio6 5 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION2";
-			label = "BOARD_VERSION2";
-		};
-		board_version3 {
-			gpios = <&gpio6 6 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION3";
-			label = "BOARD_VERSION3";
-		};
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&gpio_ac_present
-			&gpio_power_button_l
-			&gpio_lid_open
-		>;
-	};
-};
diff --git a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h
deleted file mode 100644
index 741cbd89a2..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_KBD_KSO2		GPIO_UNIMPLEMENTED
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
-		 power_button_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx9/include/pwm_map.h b/zephyr/projects/npcx_evb/npcx9/include/pwm_map.h
deleted file mode 100644
index 371e95c116..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/include/pwm_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_PWM_MAP_H
-#define __ZEPHYR_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "pwm/pwm.h"
-
-#define PWM_CH_FAN		NAMED_PWM(fan)
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-
-#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts
deleted file mode 100644
index fdeee3c02c..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/keyboard.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	cros-keyscan {
-		compatible = "cros-keyscan";
-
-		output-settle = <40>;
-		debounce-down = <6000>;
-		scan-period = <1500>;
-		poll-timeout = <1000000>;
-
-		actual-key-mask = <
-			0x14	/* C0 */
-			0xff	/* C1 */
-			0xff	/* C2 */
-			0xff	/* C3 */
-			0xff	/* C4 */
-			0xf5	/* C5 */
-			0xff	/* C6 */
-			0xa4	/* C7 */
-			0xff	/* C8 */
-			0xf6	/* C9 */
-			0x55	/* C10 */
-			0xfa	/* C11 */
-			0xc8	/* C12 */
-			>;
-	};
-};
diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf
deleted file mode 100644
index ea383a600d..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/prj.conf
+++ /dev/null
@@ -1,59 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_SHIMMED_TASKS=y
-
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_SWITCH=n
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-CONFIG_PLATFORM_EC_VSTORE=n
-
-# Workaround npcx9 A1 chip's bug for download_from_flash API in th booter.
-# This can be removed when A2 chip is available.
-CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
-
-# Board version is selected over GPIO board ID pins.
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
-
-# PWM
-CONFIG_PLATFORM_EC_PWM=y
-
-# Fan
-CONFIG_SENSOR=y
-CONFIG_SENSOR_SHELL=n
-CONFIG_PLATFORM_EC_FAN=y
-
-# Console command
-CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y
-
-# eSPI
-CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-
-# Keyboard
-CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
-
-# Zephyr feature
-CONFIG_ASSERT=y
-CONFIG_SHELL_MINIMAL=n
-CONFIG_LOG=y
-
-# Avoid underflow info from tachometer
-CONFIG_SENSOR_LOG_LEVEL_ERR=y
-
-# Avoid info storm from power management
-CONFIG_SOC_LOG_LEVEL_ERR=y
-
-CONFIG_SYSCON=y
diff --git a/zephyr/projects/npcx_evb/npcx9/pwm.dts b/zephyr/projects/npcx_evb/npcx9/pwm.dts
deleted file mode 100644
index 144b4d96b9..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/pwm.dts
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-pwms {
-		compatible = "named-pwms";
-
-		pwm_fan: fan {
-			pwms = <&pwm0 0 0>;
-			label = "FAN";
-			frequency = <25000>;
-		};
-		kblight {
-			pwms = <&pwm2 0 0>;
-			label = "KBLIGHT";
-			frequency = <10000>;
-		};
-	};
-};
-
-/* fan */
-&pwm0 {
-	status = "okay";
-	drive-open-drain;
-};
-
-/* kblight */
-&pwm2 {
-	status = "okay";
-};
diff --git a/zephyr/projects/npcx_evb/npcx9/zmake.yaml b/zephyr/projects/npcx_evb/npcx9/zmake.yaml
deleted file mode 100644
index 1d750cc813..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/zmake.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: npcx9_evb
-dts-overlays:
-  - gpio.dts
-  - pwm.dts
-  - fan.dts
-  - keyboard.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/posix-ec/CMakeLists.txt b/zephyr/projects/posix-ec/CMakeLists.txt
deleted file mode 100644
index c4ac80228d..0000000000
--- a/zephyr/projects/posix-ec/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.13.1)
-set(BOARD native_posix)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(posix-ec)
diff --git a/zephyr/projects/posix-ec/prj.conf b/zephyr/projects/posix-ec/prj.conf
deleted file mode 100644
index e79730789d..0000000000
--- a/zephyr/projects/posix-ec/prj.conf
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-
-# Disable shimmed code. Can enabled selectively later
-CONFIG_SHIMMED_TASKS=n
-CONFIG_PLATFORM_EC_KEYBOARD=n
-CONFIG_PLATFORM_EC_HOSTCMD=n
-CONFIG_PLATFORM_EC_I2C=n
-
-# Define necessary program memory locations. These are meaning less though
-CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10090000
-CONFIG_CROS_EC_RAM_BASE=0x200c0000
-CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000
-CONFIG_CROS_EC_RAM_SIZE=0x0000f800
-CONFIG_CROS_EC_RO_MEM_OFF=0x0
-CONFIG_CROS_EC_RO_SIZE=0xb000
-CONFIG_CROS_EC_RW_MEM_OFF=0xb000
-CONFIG_CROS_EC_RW_SIZE=0x75000
diff --git a/zephyr/projects/posix-ec/zmake.yaml b/zephyr/projects/posix-ec/zmake.yaml
deleted file mode 100644
index e06fd99183..0000000000
--- a/zephyr/projects/posix-ec/zmake.yaml
+++ /dev/null
@@ -1,7 +0,0 @@
-board: native_posix
-supported-toolchains:
-  - llvm
-  - host
-supported-zephyr-versions:
-  - v2.6
-output-type: elf
diff --git a/zephyr/projects/trogdor/lazor/CMakeLists.txt b/zephyr/projects/trogdor/lazor/CMakeLists.txt
deleted file mode 100644
index 7ab5d6a92e..0000000000
--- a/zephyr/projects/trogdor/lazor/CMakeLists.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(lazor)
-
-zephyr_library_include_directories(include)
-
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/trogdor" CACHE PATH
-    "Path to the platform/ec baseboard directory")
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/lazor" CACHE PATH
-  "Path to the platform/ec board directory")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-  "${PLATFORM_EC_BASEBOARD}/hibernate.c"
-  "${PLATFORM_EC_BASEBOARD}/power.c"
-  "${PLATFORM_EC_BASEBOARD}/usbc_config.c"
-  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
-
-zephyr_library_sources(
-  "${PLATFORM_EC_BOARD}/hibernate.c"
-  "${PLATFORM_EC_BOARD}/sku.c"
-  "${PLATFORM_EC_BOARD}/switchcap.c"
-  "${PLATFORM_EC_BOARD}/usbc_config.c")
-
-# Board specific implementation
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
-  "src/i2c.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-  "src/led.c")
diff --git a/zephyr/projects/trogdor/lazor/battery.dts b/zephyr/projects/trogdor/lazor/battery.dts
deleted file mode 100644
index 52aa69d400..0000000000
--- a/zephyr/projects/trogdor/lazor/battery.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	batteries {
-		default_battery: ap16l5j {
-			compatible = "panasonic,ap16l5j";
-		};
-		ap16l5j_009 {
-			compatible = "panasonic,ap16l5j-009";
-		};
-		ap16l8j {
-			compatible = "lgc,ap16l8j";
-		};
-		lgc_ap18c8k {
-			compatible = "lgc,ap18c8k";
-		};
-		murata_ap18c4k {
-			compatible = "murata,ap18c4k";
-		};
-	};
-};
diff --git a/zephyr/projects/trogdor/lazor/gpio.dts b/zephyr/projects/trogdor/lazor/gpio.dts
deleted file mode 100644
index 282ea97bb4..0000000000
--- a/zephyr/projects/trogdor/lazor/gpio.dts
+++ /dev/null
@@ -1,446 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		usb_c0_pd_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_PD_INT_ODL";
-			label = "USB_C0_PD_INT_ODL";
-		};
-		usb_c1_pd_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_PD_INT_ODL";
-			label = "USB_C1_PD_INT_ODL";
-		};
-		usb_c0_swctl_int_odl {
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
-			label = "USB_C0_SWCTL_INT_ODL";
-		};
-		usb_c1_swctl_int_odl {
-			gpios = <&gpio4 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
-			label = "USB_C1_SWCTL_INT_ODL";
-		};
-		usb_c0_bc12_int_l {
-			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C0_BC12_INT_L";
-			label = "USB_C0_BC12_INT_L";
-		};
-		usb_c1_bc12_int_l {
-			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C1_BC12_INT_L";
-			label = "USB_C1_BC12_INT_L";
-		};
-		usb_a0_oc_odl {
-			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_A0_OC_ODL";
-			label = "USB_A0_OC_ODL";
-		};
-		gpio_acok_od: acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioe 3 GPIO_INPUT>;
-			enum-name = "GPIO_CCD_MODE_ODL";
-			label = "CCD_MODE_ODL";
-		};
-		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "EC_PWR_BTN_ODL";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio7 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpiof 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_UP_L";
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		ec_wp_odl {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "EC_WP_ODL";
-		};
-		gpio_lid_open_ec: lid_open_ec {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN_EC";
-		};
-		ap_rst_l {
-			gpios = <&gpioc 1 GPIO_INPUT>;
-			enum-name = "GPIO_AP_RST_L";
-			label = "AP_RST_L";
-		};
-		ps_hold {
-			gpios = <&gpioa 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_PS_HOLD";
-			label = "PS_HOLD";
-		};
-		ap_suspend {
-			gpios = <&gpio5 7 GPIO_INPUT>;
-			enum-name = "GPIO_AP_SUSPEND";
-			label = "AP_SUSPEND";
-		};
-		deprecated_ap_rst_req {
-			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_DEPRECATED_AP_RST_REQ";
-			label = "DEPRECATED_AP_RST_REQ";
-		};
-		power_good {
-			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_POWER_GOOD";
-			label = "POWER_GOOD";
-		};
-		warm_reset_l {
-			gpios = <&gpiof 4 GPIO_INPUT>;
-			enum-name = "GPIO_WARM_RESET_L";
-			label = "WARM_RESET_L";
-		};
-		ap_ec_spi_cs_l {
-			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CS_L";
-		};
-		tablet_mode_l {
-			gpios = <&gpioc 6 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		gpio_accel_gyro_int_l: accel_gyro_int_l {
-			gpios = <&gpioa 0 GPIO_INPUT>;
-			enum-name = "GPIO_ACCEL_GYRO_INT_L";
-			label = "ACCEL_GYRO_INT_L";
-		};
-		da9313_gpio0 {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_DA9313_GPIO0";
-			label = "DA9313_GPIO0";
-		};
-		switchcap_pg_int_l {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_SWITCHCAP_PG_INT_L";
-			label = "SWITCHCAP_PG_INT_L";
-		};
-		gpio_ec_rst_odl: ec_rst_odl {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_RST_ODL";
-			label = "EC_RST_ODL";
-		};
-		ec_entering_rw {
-			gpios = <&gpioe 1 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "EC_ENTERING_RW";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		pm845_resin_l {
-			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_RESIN_L";
-			label = "PM845_RESIN_L";
-		};
-		pmic_kpd_pwr_odl {
-			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
-			label = "PMIC_KPD_PWR_ODL";
-		};
-		ec_int_l {
-			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "EC_INT_L";
-		};
-		qsip_on {
-			gpios = <&gpio5 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_QSIP_ON";
-			label = "QSIP_ON";
-		};
-		hibernate_l {
-			gpios = <&gpio5 2 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_HIBERNATE_L";
-			label = "HIBERNATE_L";
-		};
-		switchcap_on {
-			gpios = <&gpiod 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SWITCHCAP_ON";
-			label = "SWITCHCAP_ON";
-		};
-		switchcap_on_l {
-			gpios = <&gpiod 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SWITCHCAP_ON_L";
-			label = "SWITCHCAP_ON_L";
-		};
-		vbob_en {
-			gpios = <&gpiod 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_VBOB_EN";
-			label = "VBOB_EN";
-		};
-		en_pp3300_a {
-			gpios = <&gpioa 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP3300_A";
-			label = "EN_PP3300_A";
-		};
-		en_pp5000_a {
-			gpios = <&gpio6 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000_A";
-		};
-		ec_bl_disable_l {
-			gpios = <&gpiob 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EC_BL_DISABLE_L";
-		};
-		lid_accel_int_l {
-			gpios = <&gpio5 6 GPIO_INPUT>;
-			enum-name = "GPIO_LID_ACCEL_INT_L";
-			label = "LID_ACCEL_INT_L";
-		};
-		trackpad_int_gate {
-			gpios = <&gpio7 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_TRACKPAD_INT_GATE";
-			label = "TRACKPAD_INT_GATE";
-		};
-		usb_c0_pd_rst_l {
-			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_USB_C0_PD_RST_L";
-			label = "USB_C0_PD_RST_L";
-		};
-		usb_c1_pd_rst_l {
-			gpios = <&gpioe 4 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_USB_C1_PD_RST_L";
-			label = "USB_C1_PD_RST_L";
-		};
-		dp_mux_oe_l {
-			gpios = <&gpio9 6 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_DP_MUX_OE_L";
-			label = "DP_MUX_OE_L";
-		};
-		dp_mux_sel {
-			gpios = <&gpio4 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_MUX_SEL";
-			label = "DP_MUX_SEL";
-		};
-		dp_hot_plug_det {
-			gpios = <&gpio9 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_HOT_PLUG_DET";
-			label = "DP_HOT_PLUG_DET";
-		};
-		en_usb_a_5v {
-			gpios = <&gpio8 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_USB_A_5V";
-			label = "EN_USB_A_5V";
-		};
-		usb_a_cdp_ilim_en {
-			gpios = <&gpio7 5 GPIO_OUT_HIGH>;
-			label = "USB_A_CDP_ILIM_EN";
-		};
-		ec_chg_led_y_c1 {
-			gpios = <&gpioc 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C1";
-			label = "EC_CHG_LED_Y_C1";
-		};
-		ec_chg_led_b_c1 {
-			gpios = <&gpioc 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_B_C1";
-			label = "EC_CHG_LED_B_C1";
-		};
-		ap_ec_spi_mosi {
-			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MOSI";
-		};
-		ap_ec_spi_miso {
-			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MISO";
-		};
-		ap_ec_spi_clk {
-			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CLK";
-		};
-		kb_bl_pwm {
-			gpios = <&gpio8 0 GPIO_INPUT>;
-			label = "KB_BL_PWM";
-		};
-		edp_bkltctl {
-			gpios = <&gpiob 7 GPIO_INPUT>;
-			label = "EDP_BKLTCTL";
-		};
-		ppvar_boostin_sense {
-			gpios = <&gpio4 4 GPIO_INPUT>;
-			label = "PPVAR_BOOSTIN_SENSE";
-		};
-		charger_iadp {
-			gpios = <&gpio4 3 GPIO_INPUT>;
-			label = "CHARGER_IADP";
-		};
-		charger_pmon {
-			gpios = <&gpio4 2 GPIO_INPUT>;
-			label = "CHARGER_PMON";
-		};
-		ec_i2c_power_scl {
-			gpios = <&gpiob 5 GPIO_INPUT>;
-			label = "EC_I2C_POWER_SCL";
-		};
-		ec_i2c_power_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			label = "EC_I2C_POWER_SDA";
-		};
-		ec_i2c_usb_c0_pd_scl {
-			gpios = <&gpio9 0 GPIO_INPUT>;
-			label = "EC_I2C_USB_C0_PD_SCL";
-		};
-		ec_i2c_usb_c0_pd_sda {
-			gpios = <&gpio8 7 GPIO_INPUT>;
-			label = "EC_I2C_USB_C0_PD_SDA";
-		};
-		ec_i2c_usb_c1_pd_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
-			label = "EC_I2C_USB_C1_PD_SCL";
-		};
-		ec_i2c_usb_c1_pd_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
-			label = "EC_I2C_USB_C1_PD_SDA";
-		};
-		ec_i2c_eeprom_scl {
-			gpios = <&gpio3 3 GPIO_INPUT>;
-			label = "EC_I2C_EEPROM_SCL";
-		};
-		ec_i2c_eeprom_sda {
-			gpios = <&gpio3 6 GPIO_INPUT>;
-			label = "EC_I2C_EEPROM_SDA";
-		};
-		ec_i2c_sensor_scl {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C_SENSOR_SCL";
-			label = "EC_I2C_SENSOR_SCL";
-		};
-		ec_i2c_sensor_sda {
-			gpios = <&gpiob 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C_SENSOR_SDA";
-			label = "EC_I2C_SENSOR_SDA";
-		};
-		gpio_brd_id0: brd_id0 {
-			gpios = <&gpioc 7 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION1";
-			label = "BRD_ID0";
-		};
-		gpio_brd_id1: brd_id1 {
-			gpios = <&gpio9 3 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION2";
-			label = "BRD_ID1";
-		};
-		gpio_brd_id2: brd_id2 {
-			gpios = <&gpio6 3 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION3";
-			label = "BRD_ID2";
-		};
-		gpio_sku_id0: sku_id0 {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID0";
-			label = "SKU_ID0";
-		};
-		gpio_sku_id1: sku_id1 {
-			gpios = <&gpio4 1 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID1";
-			label = "SKU_ID1";
-		};
-		gpio_sku_id2: sku_id2 {
-			gpios = <&gpiod 4 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID2";
-			label = "SKU_ID2";
-		};
-		arm_x86 {
-			gpios = <&gpio6 6 GPIO_OUT_LOW>;
-			label = "ARM_X86";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_ioc1 /* AP_RST_L */
-			&lvol_ioc2 /* DEPRECATED_AP_RST_REQ */
-			&lvol_iof4 /* WARM_RESET_L */
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&gpio_acok_od
-			&gpio_ec_pwr_btn_odl
-			&gpio_lid_open_ec
-			&gpio_ec_rst_odl
-		>;
-	};
-
-	sku {
-		compatible = "cros-ec,gpio-id";
-
-		bits  = <
-			&gpio_sku_id0
-			&gpio_sku_id1
-			&gpio_sku_id2
-		>;
-
-		system = "binary";
-	};
-
-	board {
-		compatible = "cros-ec,gpio-id";
-
-		bits  = <
-			&gpio_brd_id0
-			&gpio_brd_id1
-			&gpio_brd_id2
-		>;
-
-		system = "binary_first_base3";
-	};
-
-	unused-pins {
-		compatible = "unused-gpios";
-		unused-gpios =
-			<&gpio5 1 0>,
-			<&gpiod 0 0>,
-			<&gpiof 3 0>,
-			<&gpio0 4 0>,
-			<&gpioc 0 0>,
-			<&gpioa 7 0>,
-			<&gpio8 3 0>,
-			<&gpio8 1 0>,
-			<&gpio3 7 0>,
-			<&gpio7 6 0>,
-			<&gpio3 4 0>,
-			<&gpioc 5 0>,
-			<&gpioa 3 0>,
-			<&gpio7 3 0>,
-			<&gpiod 7 0>,
-			<&gpioa 5 0>,
-			<&gpiob 0 0>,
-			<&gpio9 4 0>,
-			<&gpiob 1 0>,
-			<&gpio6 2 0>,
-			<&gpio3 5 0>,
-			<&gpio9 7 0>,
-			<&gpio6 0 0>,
-			<&gpio7 2 0>;
-	};
-};
diff --git a/zephyr/projects/trogdor/lazor/include/gpio_map.h b/zephyr/projects/trogdor/lazor/include/gpio_map.h
deleted file mode 100644
index 00ee9c48e1..0000000000
--- a/zephyr/projects/trogdor/lazor/include/gpio_map.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#endif
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
-	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)             \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
-		 power_button_interrupt)                                      \
-	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt)    \
-	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)      \
-	GPIO_INT(GPIO_SWITCHCAP_PG_INT_L, GPIO_INT_EDGE_FALLING,              \
-		 ln9310_interrupt)                                            \
-	GPIO_INT(GPIO_AP_RST_L, GPIO_INT_EDGE_BOTH, chipset_ap_rst_interrupt) \
-	GPIO_INT(GPIO_AP_SUSPEND, GPIO_INT_EDGE_BOTH, power_signal_interrupt) \
-	GPIO_INT(GPIO_DEPRECATED_AP_RST_REQ, GPIO_INT_EDGE_BOTH,              \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(GPIO_POWER_GOOD, GPIO_INT_EDGE_BOTH,                         \
-		 chipset_power_good_interrupt)                                \
-	GPIO_INT(GPIO_PS_HOLD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)    \
-	GPIO_INT(GPIO_WARM_RESET_L, GPIO_INT_EDGE_BOTH,                       \
-		 chipset_warm_reset_interrupt)                                \
-	GPIO_INT(GPIO_USB_C0_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C1_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C0_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C1_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C0_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb0_evt)     \
-	GPIO_INT(GPIO_USB_C1_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb1_evt)     \
-	GPIO_INT(GPIO_USB_A0_OC_ODL, GPIO_INT_EDGE_BOTH, usba_oc_interrupt)   \
-	GPIO_INT(GPIO_CCD_MODE_ODL, GPIO_INT_EDGE_FALLING,                    \
-		 board_connect_c0_sbu)                                        \
-	GPIO_INT(GPIO_ACCEL_GYRO_INT_L, GPIO_INT_EDGE_FALLING,                \
-		 bmi160_interrupt)                                            \
-	GPIO_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH, gmr_tablet_switch_isr)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/trogdor/lazor/include/pwm_map.h b/zephyr/projects/trogdor/lazor/include/pwm_map.h
deleted file mode 100644
index e704b6d6d3..0000000000
--- a/zephyr/projects/trogdor/lazor/include/pwm_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_PWM_MAP_H
-#define __ZEPHYR_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "pwm/pwm.h"
-
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-#define PWM_CH_DISPLIGHT	NAMED_PWM(displight)
-
-#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/trogdor/lazor/keyboard.dts b/zephyr/projects/trogdor/lazor/keyboard.dts
deleted file mode 100644
index 1b683d0eba..0000000000
--- a/zephyr/projects/trogdor/lazor/keyboard.dts
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	cros-keyscan {
-		compatible = "cros-keyscan";
-
-		actual-key-mask = <
-			0x14	/* C0 */
-			0xff	/* C1 */
-			0xff	/* C2 */
-			0xff	/* C3 */
-			0xff	/* C4 */
-			0xf5	/* C5 */
-			0xff	/* C6 */
-			0xa4	/* C7 */
-			0xff	/* C8 */
-			0xfe	/* C9 */
-			0x55	/* C10 */
-			0xfa	/* C11 */
-			0xca	/* C12 */
-			>;
-	};
-};
diff --git a/zephyr/projects/trogdor/lazor/motionsense.dts b/zephyr/projects/trogdor/lazor/motionsense.dts
deleted file mode 100644
index 51d8505078..0000000000
--- a/zephyr/projects/trogdor/lazor/motionsense.dts
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi160-int = &base_accel;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
-		};
-
-		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 (-1) 0
-				 0 0 1>;
-		};
-
-		base_rot_ref: base-rotation-ref {
-			mat33 = <1 0 0
-				 0 (-1) 0
-				 0 0 (-1)>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bma255_data: bma255-drv-data {
-			compatible = "cros-ec,drvdata-bma255";
-			status = "okay";
-		};
-
-		bmi160_data: bmi160-drv-data {
-			compatible = "cros-ec,drvdata-bmi160";
-			status = "okay";
-		};
-
-		kx022_data: kx022-drv-data {
-			compatible = "cros-ec,drvdata-kionix";
-			status = "okay";
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,bma255";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&bma255_data>;
-			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi160-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi160-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-		};
-	};
-
-	/*
-	 * List of alternative motion sensors that creates
-	 * motion_sensors_alt array.
-	 */
-	motionsense-sensor-alt {
-		alt_lid_accel {
-			compatible = "cros-ec,kx022";
-			status = "okay";
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			drv-data = <&kx022_data>;
-			alternate-for = <&lid_accel>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_accel_gyro_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel>;
-	};
-};
diff --git a/zephyr/projects/trogdor/lazor/prj.conf b/zephyr/projects/trogdor/lazor/prj.conf
deleted file mode 100644
index e16994e327..0000000000
--- a/zephyr/projects/trogdor/lazor/prj.conf
+++ /dev/null
@@ -1,165 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_I2C=y
-
-# LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-CONFIG_PLATFORM_EC_PWM_DISPLIGHT=y
-CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
-
-# Application Processor is Qualcomm SC7180
-CONFIG_AP_ARM_QUALCOMM_SC7180=y
-
-# Board version is selected over GPIO board ID pins.
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
-
-# LN9310 Switchcap
-CONFIG_PLATFORM_EC_SWITCHCAP_LN9310=y
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
-CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
-CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
-CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
-
-# Trogdor family does not use EFS2
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-# MKBP event mask
-CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
-CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
-
-# MKBP event
-CONFIG_PLATFORM_EC_MKBP_EVENT=y
-CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
-CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-CONFIG_PLATFORM_EC_CMD_BUTTON=y
-CONFIG_CROS_KB_RAW_NPCX=y
-
-# ADC
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# Battery
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
-CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
-CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
-CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
-CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
-CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
-CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-
-# USB-A
-CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
-
-# USB-C
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
-CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
-CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n
-CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
-CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT=2
-CONFIG_PLATFORM_EC_USB_PD_REV30=n
-CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
-CONFIG_HAS_TASK_PD_C1=y
-CONFIG_HAS_TASK_PD_INT_C1=y
-
-# USB ID
-# This is allocated specifically for Trogdor
-# http://google3/hardware/standards/usb/
-# TODO(b/183608112): Move to device tree
-CONFIG_PLATFORM_EC_USB_PID=0x5043
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-CONFIG_CROS_RTC_NPCX=y
-CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
-
-# EC software sync
-CONFIG_PLATFORM_EC_VBOOT_HASH=y
-
-# Serial Host Interface (SHI) device.
-CONFIG_CROS_SHI_NPCX=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-
-# Console history
-CONFIG_SHELL_HISTORY=y
-CONFIG_SHELL_CMDS=y
-
-# Taskinfo
-CONFIG_THREAD_MONITOR=y
-CONFIG_KERNEL_SHELL=y
-
-CONFIG_SYSCON=y
-
-# Features should be enabled. But the code RAM is not enough, disable them.
-#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
-#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/projects/trogdor/lazor/src/i2c.c b/zephyr/projects/trogdor/lazor/src/i2c.c
deleted file mode 100644
index a7ce970843..0000000000
--- a/zephyr/projects/trogdor/lazor/src/i2c.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c/i2c.h"
-#include "i2c.h"
-
-/* Lazor board specific i2c implementation */
-
-#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-int board_allow_i2c_passthru(int port)
-{
-	return (i2c_get_device_for_port(port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
-}
-#endif
diff --git a/zephyr/projects/trogdor/lazor/src/led.c b/zephyr/projects/trogdor/lazor/src/led.c
deleted file mode 100644
index e4b34576c8..0000000000
--- a/zephyr/projects/trogdor/lazor/src/led.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Power and battery LED control.
- */
-
-#include "battery.h"
-#include "charge_manager.h"
-#include "charge_state.h"
-#include "chipset.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "led_common.h"
-#include "system.h"
-#include "util.h"
-
-#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-
-#define BAT_LED_ON 1
-#define BAT_LED_OFF 0
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-enum led_color {
-	LED_OFF = 0,
-	LED_AMBER,
-	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
-};
-
-static void led_set_color(enum led_color color)
-{
-	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
-	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	brightness_range[EC_LED_COLOR_AMBER] = 1;
-	brightness_range[EC_LED_COLOR_BLUE] = 1;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (brightness[EC_LED_COLOR_BLUE] != 0)
-		led_set_color(LED_BLUE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(LED_AMBER);
-	else
-		led_set_color(LED_OFF);
-
-	return EC_SUCCESS;
-}
-
-static void board_led_set_battery(void)
-{
-	static int battery_ticks;
-	int color = LED_OFF;
-	int period = 0;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		/* Always indicate amber on when charging. */
-		color = LED_AMBER;
-		break;
-	case PWR_STATE_DISCHARGE:
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
-			/* Discharging in S3: Amber 1 sec, off 3 sec */
-			period = (1 + 3) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 1 * LED_ONE_SEC)
-				color = LED_AMBER;
-			else
-				color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-			/* Discharging in S5: off */
-			color = LED_OFF;
-		} else if (chipset_in_state(CHIPSET_STATE_ON)) {
-			/* Discharging in S0: Blue on */
-			color = LED_BLUE;
-		}
-		break;
-	case PWR_STATE_ERROR:
-		/* Battery error: Amber 1 sec, off 1 sec */
-		period = (1 + 1) * LED_ONE_SEC;
-		battery_ticks = battery_ticks % period;
-		if (battery_ticks < 1 * LED_ONE_SEC)
-			color = LED_AMBER;
-		else
-			color = LED_OFF;
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		/* Full Charged: Blue on */
-		color = LED_BLUE;
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
-			color = LED_BLUE;
-		break;
-	default:
-		/* Other states don't alter LED behavior */
-		break;
-	}
-
-	led_set_color(color);
-}
-
-/* Called by hook task every TICK */
-static void led_tick(void)
-{
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		board_led_set_battery();
-}
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
-
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
-{
-	enum led_color color;
-
-	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
-		return;
-
-	if (state == LED_STATE_RESET) {
-		led_auto_control(EC_LED_ID_BATTERY_LED, 1);
-		board_led_set_battery();
-		return;
-	}
-
-	color = state ? LED_BLUE : LED_OFF;
-
-	led_auto_control(EC_LED_ID_BATTERY_LED, 0);
-
-	led_set_color(color);
-}
diff --git a/zephyr/projects/trogdor/lazor/zmake.yaml b/zephyr/projects/trogdor/lazor/zmake.yaml
deleted file mode 100644
index c1c14d07d5..0000000000
--- a/zephyr/projects/trogdor/lazor/zmake.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: trogdor
-dts-overlays:
-  - battery.dts
-  - gpio.dts
-  - keyboard.dts
-  - motionsense.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/trogdor/trogdor/CMakeLists.txt b/zephyr/projects/trogdor/trogdor/CMakeLists.txt
deleted file mode 100644
index 99c72e1b81..0000000000
--- a/zephyr/projects/trogdor/trogdor/CMakeLists.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(trogdor)
-
-zephyr_library_include_directories(include)
-
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/trogdor" CACHE PATH
-    "Path to the platform/ec baseboard directory")
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/trogdor" CACHE PATH
-  "Path to the platform/ec board directory")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-  "${PLATFORM_EC_BASEBOARD}/hibernate.c"
-  "${PLATFORM_EC_BASEBOARD}/usbc_config.c"
-  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-  "${PLATFORM_EC_BOARD}/led.c")
-
-zephyr_library_sources(
-  "${PLATFORM_EC_BOARD}/hibernate.c"
-  "${PLATFORM_EC_BOARD}/switchcap.c"
-  "${PLATFORM_EC_BOARD}/usbc_config.c")
-
-# Board specific implementation
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
-  "src/i2c.c")
diff --git a/zephyr/projects/trogdor/trogdor/battery.dts b/zephyr/projects/trogdor/trogdor/battery.dts
deleted file mode 100644
index ab4b28999a..0000000000
--- a/zephyr/projects/trogdor/trogdor/battery.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	batteries {
-		default_battery: ap16l5j {
-			compatible = "panasonic,ap16l5j";
-		};
-	};
-};
diff --git a/zephyr/projects/trogdor/trogdor/gpio.dts b/zephyr/projects/trogdor/trogdor/gpio.dts
deleted file mode 100644
index 956db72960..0000000000
--- a/zephyr/projects/trogdor/trogdor/gpio.dts
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		usb_c0_pd_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_PD_INT_ODL";
-			label = "USB_C0_PD_INT_ODL";
-		};
-		usb_c1_pd_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_PD_INT_ODL";
-			label = "USB_C1_PD_INT_ODL";
-		};
-		usb_c0_swctl_int_odl {
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
-			label = "USB_C0_SWCTL_INT_ODL";
-		};
-		usb_c1_swctl_int_odl {
-			gpios = <&gpio4 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
-			label = "USB_C1_SWCTL_INT_ODL";
-		};
-		usb_c0_bc12_int_l {
-			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C0_BC12_INT_L";
-			label = "USB_C0_BC12_INT_L";
-		};
-		usb_c1_bc12_int_l {
-			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C1_BC12_INT_L";
-			label = "USB_C1_BC12_INT_L";
-		};
-		usb_a0_oc_odl {
-			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_A0_OC_ODL";
-			label = "USB_A0_OC_ODL";
-		};
-		gpio_chg_acok_od: chg_acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "CHG_ACOK_OD";
-		};
-		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "EC_PWR_BTN_ODL";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio7 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpiof 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_UP_L";
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		ec_wp_odl {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "EC_WP_ODL";
-		};
-		gpio_lid_open_ec: lid_open_ec {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "LID_OPEN_EC";
-		};
-		ap_rst_l {
-			gpios = <&gpioc 1 GPIO_INPUT>;
-			enum-name = "GPIO_AP_RST_L";
-			label = "AP_RST_L";
-		};
-		ps_hold {
-			gpios = <&gpioa 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_PS_HOLD";
-			label = "PS_HOLD";
-		};
-		ap_suspend {
-			gpios = <&gpio5 7 GPIO_INPUT>;
-			enum-name = "GPIO_AP_SUSPEND";
-			label = "AP_SUSPEND";
-		};
-		deprecated_ap_rst_req {
-			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_DEPRECATED_AP_RST_REQ";
-			label = "DEPRECATED_AP_RST_REQ";
-		};
-		power_good {
-			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_POWER_GOOD";
-			label = "POWER_GOOD";
-		};
-		warm_reset_l {
-			gpios = <&gpiof 4 GPIO_INPUT>;
-			enum-name = "GPIO_WARM_RESET_L";
-			label = "WARM_RESET_L";
-		};
-		ap_ec_spi_cs_l {
-			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CS_L";
-		};
-		tablet_mode_l {
-			gpios = <&gpioc 6 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		gpio_accel_gyro_int_l: accel_gyro_int_l {
-			gpios = <&gpioa 0 GPIO_INPUT>;
-			enum-name = "GPIO_ACCEL_GYRO_INT_L";
-			label = "ACCEL_GYRO_INT_L";
-		};
-		gpio_ec_rst_odl: ec_rst_odl {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_RST_ODL";
-			label = "EC_RST_ODL";
-		};
-		ec_entering_rw {
-			gpios = <&gpioe 1 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "EC_ENTERING_RW";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioe 3 GPIO_INPUT>;
-			enum-name = "GPIO_CCD_MODE_ODL";
-			label = "CCD_MODE_ODL";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		pmic_resin_l {
-			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_RESIN_L";
-			label = "PMIC_RESIN_L";
-		};
-		pmic_kpd_pwr_odl {
-			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
-			label = "PMIC_KPD_PWR_ODL";
-		};
-		ec_int_l {
-			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "EC_INT_L";
-		};
-		hibernate_l {
-			gpios = <&gpio5 2 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_HIBERNATE_L";
-			label = "HIBERNATE_L";
-		};
-		switchcap_on {
-			gpios = <&gpiod 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_SWITCHCAP_ON";
-			label = "SWITCHCAP_ON";
-		};
-		en_pp3300_a {
-			gpios = <&gpioa 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP3300_A";
-			label = "EN_PP3300_A";
-		};
-		en_pp5000_a {
-			gpios = <&gpio6 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000_A";
-		};
-		ec_bl_disable_l {
-			gpios = <&gpiob 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EC_BL_DISABLE_L";
-		};
-		lid_accel_int_l {
-			gpios = <&gpio5 6 GPIO_INPUT>;
-			enum-name = "GPIO_LID_ACCEL_INT_L";
-			label = "LID_ACCEL_INT_L";
-		};
-		trackpad_int_gate {
-			gpios = <&gpio7 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_TRACKPAD_INT_GATE";
-			label = "TRACKPAD_INT_GATE";
-		};
-		usb_c0_pd_rst_l {
-			gpios = <&gpiof 1 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_USB_C0_PD_RST_L";
-			label = "USB_C0_PD_RST_L";
-		};
-		usb_c1_pd_rst_l {
-			gpios = <&gpioe 4 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_USB_C1_PD_RST_L";
-			label = "USB_C1_PD_RST_L";
-		};
-		dp_mux_oe_l {
-			gpios = <&gpio9 6 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_DP_MUX_OE_L";
-			label = "DP_MUX_OE_L";
-		};
-		dp_mux_sel {
-			gpios = <&gpio4 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_MUX_SEL";
-			label = "DP_MUX_SEL";
-		};
-		dp_hot_plug_det {
-			gpios = <&gpio9 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_DP_HOT_PLUG_DET";
-			label = "DP_HOT_PLUG_DET";
-		};
-		en_usb_a_5v {
-			gpios = <&gpio8 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_USB_A_5V";
-			label = "EN_USB_A_5V";
-		};
-		usb_a_cdp_ilim_en_l {
-			gpios = <&gpio7 5 GPIO_OUT_HIGH>;
-			label = "USB_A_CDP_ILIM_EN_L";
-		};
-		ec_chg_led_y_c0 {
-			gpios = <&gpio6 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C0";
-			label = "EC_CHG_LED_Y_C0";
-		};
-		ec_chg_led_w_c0 {
-			gpios = <&gpioc 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_W_C0";
-			label = "EC_CHG_LED_W_C0";
-		};
-		ec_chg_led_y_c1 {
-			gpios = <&gpioc 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_Y_C1";
-			label = "EC_CHG_LED_Y_C1";
-		};
-		ec_chg_led_w_c1 {
-			gpios = <&gpioc 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_CHG_LED_W_C1";
-			label = "EC_CHG_LED_W_C1";
-		};
-		ap_ec_spi_mosi {
-			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MOSI";
-		};
-		ap_ec_spi_miso {
-			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_MISO";
-		};
-		ap_ec_spi_clk {
-			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			label = "AP_EC_SPI_CLK";
-		};
-		kb_bl_pwm {
-			gpios = <&gpio8 0 GPIO_INPUT>;
-			label = "KB_BL_PWM";
-		};
-		edp_bkltctl {
-			gpios = <&gpiob 7 GPIO_INPUT>;
-			label = "EDP_BKLTCTL";
-		};
-		ppvar_boostin_sense {
-			gpios = <&gpio4 4 GPIO_INPUT>;
-			label = "PPVAR_BOOSTIN_SENSE";
-		};
-		charger_iadp {
-			gpios = <&gpio4 3 GPIO_INPUT>;
-			label = "CHARGER_IADP";
-		};
-		charger_pmon {
-			gpios = <&gpio4 2 GPIO_INPUT>;
-			label = "CHARGER_PMON";
-		};
-		brd_id0 {
-			gpios = <&gpioc 7 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION1";
-			label = "BRD_ID0";
-		};
-		brd_id1 {
-			gpios = <&gpio9 3 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION2";
-			label = "BRD_ID1";
-		};
-		brd_id2 {
-			gpios = <&gpio6 3 GPIO_INPUT>;
-			enum-name = "GPIO_BOARD_VERSION3";
-			label = "BRD_ID2";
-		};
-		sku_id0 {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID0";
-			label = "SKU_ID0";
-		};
-		sku_id1 {
-			gpios = <&gpio4 1 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID1";
-			label = "SKU_ID1";
-		};
-		sku_id2 {
-			gpios = <&gpiod 4 GPIO_INPUT>;
-			enum-name = "GPIO_SKU_ID2";
-			label = "SKU_ID2";
-		};
-		switchcap_gpio_1 {
-			gpios = <&gpioe 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
-			enum-name = "GPIO_SWITCHCAP_PG";
-			label = "SWITCHCAP_GPIO_1";
-		};
-		arm_x86 {
-			gpios = <&gpio6 6 GPIO_OUT_LOW>;
-			label = "ARM_X86";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_ioc1 /* AP_RST_L */
-			&lvol_ioc2 /* DEPRECATED_AP_RST_REQ */
-			&lvol_iof4 /* WARM_RESET_L */
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-pins = <
-			&gpio_chg_acok_od
-			&gpio_ec_pwr_btn_odl
-			&gpio_lid_open_ec
-			&gpio_ec_rst_odl
-		>;
-	};
-
-	unused-pins {
-		compatible = "unused-gpios";
-		unused-gpios =
-			<&gpio5 1 0>,
-			<&gpiod 0 0>,
-			<&gpiof 3 0>,
-			<&gpio9 4 0>,
-			<&gpio9 7 0>,
-			<&gpioa 7 0>,
-			<&gpiob 0 0>,
-			<&gpioa 5 0>,
-			<&gpio3 5 0>,
-			<&gpio7 2 0>,
-			<&gpio8 1 0>,
-			<&gpio3 7 0>,
-			<&gpio7 6 0>,
-			<&gpio3 4 0>,
-			<&gpioc 5 0>,
-			<&gpio7 3 0>,
-			<&gpiod 7 0>,
-			<&gpioa 3 0>,
-			<&gpio6 2 0>,
-			<&gpio0 4 0>,
-			<&gpio8 3 0>,
-			<&gpiob 1 0>,
-			<&gpio5 0 0>,
-			<&gpiod 3 0>;
-	};
-};
diff --git a/zephyr/projects/trogdor/trogdor/include/gpio_map.h b/zephyr/projects/trogdor/trogdor/include/gpio_map.h
deleted file mode 100644
index df4dcb0e25..0000000000
--- a/zephyr/projects/trogdor/trogdor/include/gpio_map.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
-#endif
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                               \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
-	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)             \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
-		 power_button_interrupt)                                      \
-	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt)    \
-	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)      \
-	GPIO_INT(GPIO_AP_RST_L, GPIO_INT_EDGE_BOTH, chipset_ap_rst_interrupt) \
-	GPIO_INT(GPIO_AP_SUSPEND, GPIO_INT_EDGE_BOTH, power_signal_interrupt) \
-	GPIO_INT(GPIO_DEPRECATED_AP_RST_REQ, GPIO_INT_EDGE_BOTH,              \
-		 power_signal_interrupt)                                      \
-	GPIO_INT(GPIO_POWER_GOOD, GPIO_INT_EDGE_BOTH,                         \
-		 chipset_power_good_interrupt)                                \
-	GPIO_INT(GPIO_PS_HOLD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)    \
-	GPIO_INT(GPIO_WARM_RESET_L, GPIO_INT_EDGE_BOTH,                       \
-		 chipset_warm_reset_interrupt)                                \
-	GPIO_INT(GPIO_USB_C0_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C1_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
-		 tcpc_alert_event)                                            \
-	GPIO_INT(GPIO_USB_C0_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C1_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
-		 ppc_interrupt)                                               \
-	GPIO_INT(GPIO_USB_C0_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb0_evt)     \
-	GPIO_INT(GPIO_USB_C1_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb1_evt)     \
-	GPIO_INT(GPIO_USB_A0_OC_ODL, GPIO_INT_EDGE_BOTH, usba_oc_interrupt)   \
-	GPIO_INT(GPIO_ACCEL_GYRO_INT_L, GPIO_INT_EDGE_FALLING,                \
-		 bmi160_interrupt)                                            \
-	GPIO_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH, gmr_tablet_switch_isr)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/trogdor/trogdor/include/pwm_map.h b/zephyr/projects/trogdor/trogdor/include/pwm_map.h
deleted file mode 100644
index e704b6d6d3..0000000000
--- a/zephyr/projects/trogdor/trogdor/include/pwm_map.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_PWM_MAP_H
-#define __ZEPHYR_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "pwm/pwm.h"
-
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-#define PWM_CH_DISPLIGHT	NAMED_PWM(displight)
-
-#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/trogdor/trogdor/motionsense.dts b/zephyr/projects/trogdor/trogdor/motionsense.dts
deleted file mode 100644
index 1f222c8f18..0000000000
--- a/zephyr/projects/trogdor/trogdor/motionsense.dts
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi160-int = &base_accel;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
-		};
-
-		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <0 1 0
-				 (-1) 0 0
-				 0 0 1>;
-		};
-
-		base_rot_ref: base-rotation-ref {
-			mat33 = <1 0 0
-				 0 (-1) 0
-				 0 0 (-1)>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bma255_data: bma255-drv-data {
-			compatible = "cros-ec,drvdata-bma255";
-			status = "okay";
-		};
-
-		bmi160_data: bmi160-drv-data {
-			compatible = "cros-ec,drvdata-bmi160";
-			status = "okay";
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,bma255";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&bma255_data>;
-			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi160-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi160-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&bmi160_data>;
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_accel_gyro_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel>;
-	};
-};
diff --git a/zephyr/projects/trogdor/trogdor/prj.conf b/zephyr/projects/trogdor/trogdor/prj.conf
deleted file mode 100644
index 59d87f54a1..0000000000
--- a/zephyr/projects/trogdor/trogdor/prj.conf
+++ /dev/null
@@ -1,152 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_I2C=y
-
-# LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-CONFIG_PLATFORM_EC_PWM_DISPLIGHT=y
-CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
-
-# Application Processor is Qualcomm SC7180
-CONFIG_AP_ARM_QUALCOMM_SC7180=y
-
-# Board version is selected over GPIO board ID pins.
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
-CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
-CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
-CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
-
-# Trogdor family does not use EFS2.
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-# MKBP event mask
-CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
-CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
-
-# MKBP event
-CONFIG_PLATFORM_EC_MKBP_EVENT=y
-CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
-CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-CONFIG_PLATFORM_EC_CMD_BUTTON=y
-CONFIG_CROS_KB_RAW_NPCX=y
-
-# ADC
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_ADC=y
-CONFIG_ADC_SHELL=n
-
-# Battery
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
-CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
-CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
-CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
-CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
-CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
-CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-
-# USB-A
-CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
-
-# USB-C
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
-CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
-CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n
-CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
-CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT=2
-CONFIG_PLATFORM_EC_USB_PD_REV30=n
-CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
-CONFIG_HAS_TASK_PD_C1=y
-CONFIG_HAS_TASK_PD_INT_C1=y
-
-# USB ID
-# This is allocated specifically for Trogdor
-# http://google3/hardware/standards/usb/
-# TODO(b/183608112): Move to device tree
-CONFIG_PLATFORM_EC_USB_PID=0x5043
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-CONFIG_CROS_RTC_NPCX=y
-CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
-
-# EC software sync
-CONFIG_PLATFORM_EC_VBOOT_HASH=y
-
-# Serial Host Interface (SHI) device.
-CONFIG_CROS_SHI_NPCX=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-
-CONFIG_SYSCON=y
-
-# Features should be enabled. But the code RAM is not enough, disable them.
-#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
-#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/projects/trogdor/trogdor/src/i2c.c b/zephyr/projects/trogdor/trogdor/src/i2c.c
deleted file mode 100644
index bd5fe82473..0000000000
--- a/zephyr/projects/trogdor/trogdor/src/i2c.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "i2c/i2c.h"
-#include "i2c.h"
-
-/* Trogdor board specific i2c implementation */
-
-#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-int board_allow_i2c_passthru(int port)
-{
-	return (i2c_get_device_for_port(port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
-}
-#endif
diff --git a/zephyr/projects/trogdor/trogdor/zmake.yaml b/zephyr/projects/trogdor/trogdor/zmake.yaml
deleted file mode 100644
index ef0e8a178e..0000000000
--- a/zephyr/projects/trogdor/trogdor/zmake.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: trogdor
-dts-overlays:
-  - gpio.dts
-  - battery.dts
-  - motionsense.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/volteer/delbin/CMakeLists.txt b/zephyr/projects/volteer/delbin/CMakeLists.txt
deleted file mode 100644
index 0303ee7c62..0000000000
--- a/zephyr/projects/volteer/delbin/CMakeLists.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(delbin)
-
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/delbin" CACHE PATH
-  "Path to the platform/ec board directory")
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/volteer" CACHE PATH
-  "Path to the platform/ec baseboard directory")
-
-# Include board specific header files
-zephyr_library_include_directories(
-  include
-  "${PLATFORM_EC_BASEBOARD}"
-  "${PLATFORM_EC_BOARD}")
-
-# Include selected EC source for the baseboard
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
-  "${PLATFORM_EC_BASEBOARD}/power.c")
diff --git a/zephyr/projects/volteer/delbin/gpio.dts b/zephyr/projects/volteer/delbin/gpio.dts
deleted file mode 100644
index 7d7a89d4f2..0000000000
--- a/zephyr/projects/volteer/delbin/gpio.dts
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		ec_lid_open {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "EC_LID_OPEN";
-		};
-		ec_wp_l {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "EC_WP_L";
-		};
-		h1_ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "H1_EC_PWR_BTN_ODL";
-		};
-		acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		slp_s0_l {
-			gpios = <&gpiod 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S0_L";
-			label = "SLP_S0_L";
-		};
-		slp_s3_l {
-			gpios = <&gpioa 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S3_L";
-			label = "SLP_S3_L";
-		};
-		slp_sus_l {
-			gpios = <&gpiod 7 GPIO_INPUT>;
-			enum-name = "GPIO_SLP_SUS_L";
-			label = "SLP_SUS_L";
-		};
-		pg_ec_rsmrst_odl {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_RSMRST_ODL";
-			label = "PG_EC_RSMRST_ODL";
-		};
-		rsmrst_l_pgood {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_RSMRST_L_PGOOD";
-			label = "RSMRST_L_PGOOD";
-		};
-		dsw_pwrok {
-			gpios = <&gpioc 7 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_DSW_PWROK";
-			label = "DSW_PWROK";
-		};
-		pg_ec_all_sys_pwrgd {
-			gpios = <&gpiof 4 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
-			label = "PG_EC_ALL_SYS_PWRGD";
-		};
-		gpio_ec_imu_int_l: ec_imu_int_l {
-			gpios = <&gpio5 6 GPIO_INPUT>;
-			enum-name = "GPIO_EC_IMU_INT_L";
-			label = "EC_IMU_INT_L";
-		};
-		tablet_mode_l {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		ec_accel_int {
-			gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_ACCEL_INT";
-		};
-		usb_c0_tcpc_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			label = "USB_C0_TCPC_INT_ODL";
-		};
-		usb_c1_tcpc_int_odl {
-			gpios = <&gpioa 2 GPIO_INPUT>;
-			label = "USB_C1_TCPC_INT_ODL";
-		};
-		usb_c0_ppc_int_odl {
-			gpios = <&gpio6 2 GPIO_INPUT>;
-			label = "USB_C0_PPC_INT_ODL";
-		};
-		usb_c1_ppc_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			label = "USB_C1_PPC_INT_ODL";
-		};
-		usb_c0_bc12_int_odl {
-			gpios = <&gpioe 4 GPIO_INPUT>;
-			label = "USB_C0_BC12_INT_ODL";
-		};
-		usb_c1_mix_int_odl {
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			label = "USB_C1_MIX_INT_ODL";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpio9 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		en_pp3300_a {
-			gpios = <&gpioa 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP3300_A";
-			label = "EN_PP3300_A";
-		};
-		en_pp5000_a {
-			gpios = <&gpioa 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000_A";
-		};
-		en_ppvar_vccin {
-			gpios = <&gpio4 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PPVAR_VCCIN";
-			label = "EN_PPVAR_VCCIN";
-		};
-		ec_rst_odl {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			label = "EC_RST_ODL";
-		};
-		ec_pch_sys_pwrok {
-			gpios = <&gpio3 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_PCH_SYS_PWROK";
-			label = "EC_PCH_SYS_PWROK";
-		};
-		ec_pch_rsmrst_odl {
-			gpios = <&gpioa 6 GPIO_ODR_LOW>;
-			enum-name = "GPIO_PCH_RSMRST_L";
-			label = "EC_PCH_RSMRST_ODL";
-		};
-		ec_pch_pwr_btn_odl {
-			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PCH_PWRBTN_L";
-			label = "EC_PCH_PWR_BTN_ODL";
-		};
-		ec_pch_rtcrst {
-			gpios = <&gpio7 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PCH_RTCRST";
-			label = "EC_PCH_RTCRST";
-		};
-		ec_pch_wake_odl {
-			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "EC_PCH_WAKE_ODL";
-		};
-		ec_entering_rw {
-			gpios = <&gpioe 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "EC_ENTERING_RW";
-		};
-		ec_prochot_odl {
-			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_CPU_PROCHOT";
-			label = "EC_PROCHOT_ODL";
-		};
-		ec_prochot_in_l {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_PROCHOT_IN_L";
-			label = "EC_PROCHOT_IN_L";
-		};
-		sys_rst_odl {
-			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_SYS_RESET_L";
-			label = "SYS_RST_ODL";
-		};
-		ec_pch_int_odl {
-			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
-			label = "EC_PCH_INT_ODL";
-		};
-		en_pp5000_usba {
-			gpios = <&gpioc 6 GPIO_OUT_LOW>;
-			label = "EN_PP5000_USBA";
-		};
-		usb_a_low_pwr_od {
-			gpios = <&gpio6 6 GPIO_ODR_LOW>;
-			label = "USB_A_LOW_PWR_OD";
-		};
-		usb_c0_rt_rst_odl {
-			gpios = <&gpiod 4 GPIO_ODR_LOW>;
-			label = "USB_C0_RT_RST_ODL";
-		};
-		usb_c1_rt_rst_odl {
-			gpios = <&gpio8 3 GPIO_ODR_LOW>;
-			label = "USB_C1_RT_RST_ODL";
-		};
-		usb_c0_oc_odl {
-			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
-			label = "USB_C0_OC_ODL";
-		};
-		usb_c1_oc_odl {
-			gpios = <&gpio5 0 GPIO_ODR_HIGH>;
-			label = "USB_C1_OC_ODL";
-		};
-		uart2_ec_rx {
-			gpios = <&gpio7 5 GPIO_OUT_LOW>;
-			label = "UART2_EC_RX";
-		};
-		led_1_l {
-			gpios = <&gpioc 4 GPIO_OUT_HIGH>;
-			label = "LED_1_L";
-		};
-		led_2_l {
-			gpios = <&gpioc 3 GPIO_OUT_HIGH>;
-			label = "LED_2_L";
-		};
-		led_3_l {
-			gpios = <&gpioc 2 GPIO_OUT_HIGH>;
-			label = "LED_3_L";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			label = "CCD_MODE_ODL";
-		};
-		ec_kb_bl_en {
-			gpios = <&gpio8 6 GPIO_OUT_LOW>;
-			label = "EC_KB_BL_EN";
-		};
-		unused_gpio34 {
-			gpios = <&gpio3 4 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIO34";
-		};
-		unused_gpio41 {
-			gpios = <&gpio4 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIO41";
-		};
-		unused_gpio72 {
-			gpios = <&gpio7 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIO72";
-		};
-		unused_gpio96 {
-			gpios = <&gpio9 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIO96";
-		};
-		unused_gpioa7 {
-			gpios = <&gpioa 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIOA7";
-		};
-		unused_gpioc0 {
-			gpios = <&gpioc 0 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIOC0";
-		};
-		unused_gpiof2 {
-			gpios = <&gpiof 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "UNUSED_GPIOF2";
-		};
-		ec_edp_bl_en {
-			gpios = <&gpiod 3 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EC_EDP_BL_EN";
-		};
-		ec_i2c0_sensor_scl {
-			gpios = <&gpiob 5 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SCL";
-			label = "EC_I2C0_SENSOR_SCL";
-		};
-		ec_i2c0_sensor_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SDA";
-			label = "EC_I2C0_SENSOR_SDA";
-		};
-		ec_i2c1_usb_c0_scl {
-			gpios = <&gpio9 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SCL";
-			label = "EC_I2C1_USB_C0_SCL";
-		};
-		ec_i2c1_usb_c0_sda {
-			gpios = <&gpio8 7 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SDA";
-			label = "EC_I2C1_USB_C0_SDA";
-		};
-		ec_i2c2_usb_c1_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SCL";
-			label = "EC_I2C2_USB_C1_SCL";
-		};
-		ec_i2c2_usb_c1_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SDA";
-			label = "EC_I2C2_USB_C1_SDA";
-		};
-		ec_i2c3_usb_1_mix_scl {
-			gpios = <&gpiod 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C3_USB_1_MIX_SCL";
-			label = "EC_I2C3_USB_1_MIX_SCL";
-		};
-		ec_i2c3_usb_1_mix_sda {
-			gpios = <&gpiod 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C3_USB_1_MIX_SDA";
-			label = "EC_I2C3_USB_1_MIX_SDA";
-		};
-		ec_i2c5_power_scl {
-			gpios = <&gpio3 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SCL";
-			label = "EC_I2C5_POWER_SCL";
-		};
-		ec_i2c5_power_sda {
-			gpios = <&gpio3 6 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SDA";
-			label = "EC_I2C5_POWER_SDA";
-		};
-		ec_i2c7_eeprom_scl {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C7_EEPROM_PWR_SCL_R";
-			label = "EC_I2C7_EEPROM_SCL";
-		};
-		ec_i2c7_eeprom_sda {
-			gpios = <&gpiob 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C7_EEPROM_PWR_SDA_R";
-			label = "EC_I2C7_EEPROM_SDA";
-		};
-		ec_batt_pres_odl {
-			gpios = <&gpioe 1 GPIO_INPUT>;
-			label = "EC_BATT_PRES_ODL";
-		};
-		usb_c0_dp_hpd {
-			gpios = <&gpiof 3 GPIO_INPUT>;
-			label = "USB_C0_DP_HPD";
-		};
-		usb_c1_dp_hpd {
-			gpios = <&gpio7 0 GPIO_INPUT>;
-			label = "USB_C1_DP_HPD";
-		};
-		en_pp5000_fan {
-			gpios = <&gpio6 1 GPIO_OUT_LOW>;
-			label = "EN_PP5000_FAN";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-
-		/* I2C_SDA0 & SCL0 */
-		lvol-io-pads = <&lvol_iob4 &lvol_iob5>;
-	};
-};
diff --git a/zephyr/projects/volteer/delbin/include/gpio_map.h b/zephyr/projects/volteer/delbin/include/gpio_map.h
deleted file mode 100644
index 1f4b4e1ee0..0000000000
--- a/zephyr/projects/volteer/delbin/include/gpio_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_PCH_DSW_PWROK	GPIO_UNIMPLEMENTED
-#define GPIO_USB_C1_LS_EN	GPIO_UNIMPLEMENTED
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ
-#define POWER_SIGNAL_INT(gpio, edge) \
-	GPIO_INT(gpio, edge, power_signal_interrupt)
-#define AP_PROCHOT_INT(gpio, edge) \
-	GPIO_INT(gpio, edge, throttle_ap_prochot_input_interrupt)
-#else
-#define POWER_SIGNAL_INT(gpio, edge)
-#define AP_PROCHOT_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
-#define BMI260_INT(gpio, edge) GPIO_INT(gpio, edge, bmi260_interrupt)
-#else
-#define BMI260_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_INT(gpio, edge) GPIO_INT(gpio, edge, \
-						 gmr_tablet_switch_isr)
-#define GMR_TABLET_MODE_GPIO_L	GPIO_TABLET_MODE_L
-#else
-#define GMR_TABLET_MODE_INT(gpio, edge)
-#endif
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                           \
-	BMI260_INT(GPIO_EC_IMU_INT_L, GPIO_INT_EDGE_FALLING)              \
-	GMR_TABLET_MODE_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH)       \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt) \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)        \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                 \
-		 power_button_interrupt)                                  \
-	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)         \
-	POWER_SIGNAL_INT(GPIO_PCH_SLP_S0_L, GPIO_INT_EDGE_BOTH)           \
-	POWER_SIGNAL_INT(GPIO_PCH_SLP_S3_L, GPIO_INT_EDGE_BOTH)           \
-	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)        \
-	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)       \
-	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)    \
-	POWER_SIGNAL_INT(GPIO_SLP_SUS_L, GPIO_INT_EDGE_BOTH)              \
-	AP_PROCHOT_INT(GPIO_EC_PROCHOT_IN_L, GPIO_INT_EDGE_BOTH)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/volteer/delbin/motionsense.dts b/zephyr/projects/volteer/delbin/motionsense.dts
deleted file mode 100644
index badc21a5e7..0000000000
--- a/zephyr/projects/volteer/delbin/motionsense.dts
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi260-int = &base_accel;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		mutex_bma255: bma255-mutex {
-			label = "BMA255_MUTEX";
-		};
-
-		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 (-1) 0
-				 0 0 1>;
-		};
-		base_rot_ref: base-rotation-ref {
-			mat33 = <1 0 0
-				 0 1 0
-				 0 0 1>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bma255_data: bma255-drv-data {
-			compatible = "cros-ec,drvdata-bma255";
-			status = "okay";
-		};
-
-		bmi260_data: bmi260-drv-data {
-			compatible = "cros-ec,drvdata-bmi260";
-			status = "okay";
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,bma255";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&mutex_bma255>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&bma255_data>;
-			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi260-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			default-range = <4>;
-			drv-data = <&bmi260_data>;
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-					ec-rate = <(100 * USEC_PER_MSEC)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-					ec-rate = <(100 * USEC_PER_MSEC)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi260-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			default-range = <1000>; /* dps */
-			drv-data = <&bmi260_data>;
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_ec_imu_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel>;
-	};
-};
diff --git a/zephyr/projects/volteer/delbin/prj.conf b/zephyr/projects/volteer/delbin/prj.conf
deleted file mode 100644
index 1ef881f686..0000000000
--- a/zephyr/projects/volteer/delbin/prj.conf
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_I2C=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-
-CONFIG_ARM_MPU=y
-
-CONFIG_PLATFORM_EC_VBOOT_EFS2=n
-
-CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-
-# Power sequencing
-CONFIG_AP=y
-CONFIG_AP_X86_INTEL_TGL=y
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=y
-CONFIG_PLATFORM_EC_THROTTLE_AP=y
-
-# TODO(b/180410072): bringup these features
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
-CONFIG_PLATFORM_EC_VBOOT_HASH=n
-CONFIG_PLATFORM_EC_VSTORE=n
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-
-CONFIG_SYSCON=y
diff --git a/zephyr/projects/volteer/delbin/zmake.yaml b/zephyr/projects/volteer/delbin/zmake.yaml
deleted file mode 100644
index dc5217e042..0000000000
--- a/zephyr/projects/volteer/delbin/zmake.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: volteer
-dts-overlays:
-  - gpio.dts
-  - motionsense.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/projects/volteer/volteer/CMakeLists.txt b/zephyr/projects/volteer/volteer/CMakeLists.txt
deleted file mode 100644
index 8c01874b1b..0000000000
--- a/zephyr/projects/volteer/volteer/CMakeLists.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.13.1)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(volteer)
-
-set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/volteer" CACHE PATH
-    "Path to the platform/ec board directory")
-set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/volteer" CACHE PATH
-    "Path to the platform/ec baseboard directory")
-
-# Include board specific header files
-zephyr_library_include_directories(
-  include
-  "${PLATFORM_EC_BASEBOARD}"
-  "${PLATFORM_EC_BOARD}")
-
-# Include selected EC source for the baseboard
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
-  "${PLATFORM_EC_BASEBOARD}/battery_presence.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER
-  "${PLATFORM_EC_BASEBOARD}/charger.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM
-  "${PLATFORM_EC_BASEBOARD}/cbi.c"
-  "${PLATFORM_EC_BASEBOARD}/cbi_ec_fw_config.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
-  "${PLATFORM_EC_BASEBOARD}/power.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
-  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-  "${PLATFORM_EC_BASEBOARD}/usbc_config.c")
-
-# Include selected EC source for the board
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
-  "${PLATFORM_EC_BOARD}/battery.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM
-  "${PLATFORM_EC_BOARD}/cbi.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-  "${PLATFORM_EC_BOARD}/led.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-  "${PLATFORM_EC_BOARD}/usbc_config.c")
diff --git a/zephyr/projects/volteer/volteer/bb_retimer.dts b/zephyr/projects/volteer/volteer/bb_retimer.dts
deleted file mode 100644
index 226356d030..0000000000
--- a/zephyr/projects/volteer/volteer/bb_retimer.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-&i2c3_0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-
-	usb_c1_bb_retimer: jhl8040r@40 {
-		compatible = "intel,jhl8040r";
-		reg = <0x40>;
-		label = "USB_C1_BB_RETIMER";
-		int-gpios = <&gpio_usb_c1_mix_int_odl>;
-		reset-gpios = <&gpio_usb_c1_rt_rst_odl>;
-		ls-en-gpios = <&gpio_unused_gpio41>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/cbi_eeprom.dts b/zephyr/projects/volteer/volteer/cbi_eeprom.dts
deleted file mode 100644
index 65248a5f48..0000000000
--- a/zephyr/projects/volteer/volteer/cbi_eeprom.dts
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-&i2c7_0 {
-	cbi_eeprom: eeprom@50 {
-		compatible = "atmel,at24";
-		reg = <0x50>;
-		label = "EEPROM_CBI";
-		size = <2048>;
-		pagesize = <16>;
-		address-width = <8>;
-		timeout = <5>;
-		wp-gpios = <&gpio_ec_wp_l>;
-	};
-};
-
-&cbi_ssfc_base_sensor {
-	base_sensor_bmi160: bmi160 {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <1>;
-	};
-	base_sensor_icm426xx: icm426xx {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <2>;
-	};
-	base_sensor_kx022: kx022 {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <3>;
-	};
-};
-
-&cbi_ssfc_lid_sensor {
-	lid_sensor_bma255: bma255 {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <1>;
-	};
-	lid_sensor_kx022: kx022 {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <2>;
-	};
-};
-
-&cbi_ssfc_lightbar {
-	lightbar_10_led: 10_led {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <1>;
-	};
-	lightbar_12_led: 12_led {
-		compatible = "named-cbi-ssfc-value";
-		status = "okay";
-
-		value = <2>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/fan.dts b/zephyr/projects/volteer/volteer/fan.dts
deleted file mode 100644
index e8fcc7194c..0000000000
--- a/zephyr/projects/volteer/volteer/fan.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-fans {
-		compatible = "named-fans";
-
-		fan_0 {
-			label = "FAN_0";
-			pwm = <&pwm_fan>;
-			rpm_min = <1900>;
-			rpm_start = <1900>;
-			rpm_max = <5900>;
-			tach = <&tach1>;
-			enable_gpio = <&gpio_en_pp5000_fan>;
-		};
-	};
-};
-
-/* Tachemeter for fan speed measurement */
-&tach1 {
-	status = "okay";
-	pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1 as input pin */
-	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
-	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
-	pulses-per-round = <2>; /* number of pulses per round of encoder */
-};
diff --git a/zephyr/projects/volteer/volteer/gpio.dts b/zephyr/projects/volteer/volteer/gpio.dts
deleted file mode 100644
index 4466689481..0000000000
--- a/zephyr/projects/volteer/volteer/gpio.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-gpios {
-		compatible = "named-gpios";
-
-		ec_lid_open {
-			gpios = <&gpiod 2 GPIO_INPUT>;
-			enum-name = "GPIO_LID_OPEN";
-			label = "EC_LID_OPEN";
-		};
-		gpio_ec_wp_l: ec_wp_l {
-			#gpio-cells = <0>;
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_WP_L";
-			label = "EC_WP_L";
-		};
-		wp_l {
-			gpios = <&gpioa 1 GPIO_INPUT>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		h1_ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_POWER_BUTTON_L";
-			label = "H1_EC_PWR_BTN_ODL";
-		};
-		acok_od {
-			gpios = <&gpio0 0 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		slp_s0_l {
-			gpios = <&gpiod 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S0_L";
-			label = "SLP_S0_L";
-		};
-		slp_s3_l {
-			gpios = <&gpioa 5 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S3_L";
-			label = "SLP_S3_L";
-		};
-		pch_slp_sus_l {
-			gpios = <&gpiod 7 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_SUS_L";
-			label = "PCH_SLP_SUS_L";
-		};
-		slp_sus_l {
-			gpios = <&gpiod 7 GPIO_INPUT>;
-			enum-name = "GPIO_SLP_SUS_L";
-			label = "SLP_SUS_L";
-		};
-		pg_ec_rsmrst_odl {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_RSMRST_ODL";
-			label = "PG_EC_RSMRST_ODL";
-		};
-		rsmrst_l_pgood {
-			gpios = <&gpioe 2 GPIO_INPUT>;
-			enum-name = "GPIO_RSMRST_L_PGOOD";
-			label = "RSMRST_L_PGOOD";
-		};
-		pg_ec_dsw_pwrok {
-			gpios = <&gpioc 7 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_DSW_PWROK";
-			label = "PG_EC_DSW_PWROK";
-		};
-		pg_ec_all_sys_pwrgd {
-			gpios = <&gpiof 4 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
-			label = "PG_EC_ALL_SYS_PWRGD";
-		};
-		gpio_ec_imu_int_l: ec_imu_int_l {
-			gpios = <&gpio5 6 GPIO_INPUT>;
-			enum-name = "GPIO_EC_IMU_INT_L";
-			label = "EC_IMU_INT_L";
-		};
-		gpio_ec_als_rgb_int_l: ec_als_rgb_int_l {
-			gpios = <&gpiod 4 GPIO_INPUT>;
-			enum-name = "GPIO_EC_ALS_RGB_INT_L";
-			label = "EC_ALS_RGB_INT_L";
-		};
-		tablet_mode_l {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-			enum-name = "GPIO_TABLET_MODE_L";
-			label = "TABLET_MODE_L";
-		};
-		ec_accel_int {
-			gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_EC_ACCEL_INT";
-			label = "EC_ACCEL_INT";
-		};
-		usb_c0_tcpc_int_odl {
-			gpios = <&gpioe 0 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
-			label = "USB_C0_TCPC_INT_ODL";
-		};
-		usb_c1_tcpc_int_odl {
-			gpios = <&gpioa 2 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
-			label = "USB_C1_TCPC_INT_ODL";
-		};
-		usb_c0_ppc_int_odl {
-			gpios = <&gpio6 2 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
-			label = "USB_C0_PPC_INT_ODL";
-		};
-		usb_c1_ppc_int_odl {
-			gpios = <&gpiof 5 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
-			label = "USB_C1_PPC_INT_ODL";
-		};
-		usb_c0_bc12_int_odl {
-			gpios = <&gpioe 4 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
-			label = "USB_C0_BC12_INT_ODL";
-		};
-		gpio_usb_c1_mix_int_odl: usb_c1_mix_int_odl {
-			#gpio-cells = <0>;
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_MIX_INT_ODL";
-			label = "USB_C1_MIX_INT_ODL";
-		};
-		usb_c1_bc12_int_odl {
-			#gpio-cells = <0>;
-			gpios = <&gpio0 3 GPIO_INPUT>;
-			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
-			label = "USB_C1_BC12_INT_ODL";
-		};
-		usb_c1_frs_en {
-			gpios = <&gpio9 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_USB_C1_FRS_EN";
-			label = "USB_C1_FRS_EN";
-		};
-		ec_voldn_btn_odl {
-			gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-			label = "EC_VOLDN_BTN_ODL";
-		};
-		ec_volup_btn_odl {
-			gpios = <&gpio9 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_VOLUME_UP_L";
-			label = "EC_VOLUP_BTN_ODL";
-		};
-		en_pp3300_a {
-			gpios = <&gpioa 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP3300_A";
-			label = "EN_PP3300_A";
-		};
-		en_pp5000 {
-			gpios = <&gpioa 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000";
-			label = "EN_PP5000";
-		};
-		en_pp5000_a {
-			gpios = <&gpioa 4 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_A";
-			label = "EN_PP5000_A";
-		};
-		en_ppvar_vccin {
-			gpios = <&gpio4 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PPVAR_VCCIN";
-			label = "EN_PPVAR_VCCIN";
-		};
-		ec_pch_dsw_pwrok {
-			gpios = <&gpioc 0 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PCH_DSW_PWROK";
-			label = "EC_PCH_DSW_PWROK";
-		};
-		ec_rst_odl {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			label = "EC_RST_ODL";
-		};
-		ec_pch_sys_pwrok {
-			gpios = <&gpio3 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EC_PCH_SYS_PWROK";
-			label = "EC_PCH_SYS_PWROK";
-		};
-		ec_pch_rsmrst_odl {
-			gpios = <&gpioa 6 GPIO_ODR_LOW>;
-			enum-name = "GPIO_PCH_RSMRST_L";
-			label = "EC_PCH_RSMRST_ODL";
-		};
-		ec_pch_pwr_btn_odl {
-			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_PCH_PWRBTN_L";
-			label = "EC_PCH_PWR_BTN_ODL";
-		};
-		ec_pch_rtcrst {
-			gpios = <&gpio7 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PCH_RTCRST";
-			label = "EC_PCH_RTCRST";
-		};
-		ec_pch_wake_odl {
-			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "EC_PCH_WAKE_ODL";
-		};
-		ec_entering_rw {
-			gpios = <&gpioe 3 GPIO_OUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-			label = "EC_ENTERING_RW";
-		};
-		ec_prochot_odl {
-			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_CPU_PROCHOT";
-			label = "EC_PROCHOT_ODL";
-		};
-		ec_prochot_in_l {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_PROCHOT_IN_L";
-			label = "EC_PROCHOT_IN_L";
-		};
-		sys_rst_odl {
-			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_SYS_RESET_L";
-			label = "SYS_RST_ODL";
-		};
-		ec_pch_int_odl {
-			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-			label = "EC_PCH_INT_ODL";
-		};
-		en_pp5000_usba {
-			gpios = <&gpioc 6 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USBA";
-			label = "EN_PP5000_USBA";
-		};
-		usb_a_low_pwr_od {
-			gpios = <&gpio6 6 GPIO_ODR_LOW>;
-			enum-name = "GPIO_USB_A_LOW_PWR_OD";
-			label = "USB_A_LOW_PWR_OD";
-		};
-		gpio_usb_c1_rt_rst_odl_boardid_0: usb_c1_rt_rst_odl_boardid_0 {
-			#gpio-cells = <0>;
-			gpios = <&gpio3 2 GPIO_ODR_LOW>;
-			label = "USB_C1_RT_RST_ODL_BOARDID_0";
-		};
-		gpio_usb_c1_rt_rst_odl: usb_c1_rt_rst_odl {
-			#gpio-cells = <0>;
-			gpios = <&gpio8 3 GPIO_ODR_LOW>;
-			enum-name = "GPIO_USB_C1_RT_RST_ODL";
-			label = "USB_C1_RT_RST_ODL";
-		};
-		usb_c0_oc_odl {
-			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_USB_C0_OC_ODL";
-			label = "USB_C0_OC_ODL";
-		};
-		usb_c1_oc_odl {
-			gpios = <&gpio5 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_USB_C1_OC_ODL";
-			label = "USB_C1_OC_ODL";
-		};
-		usb_c1_rt_int_odl {
-			gpios = <&gpiof 3 GPIO_INPUT>;
-			label = "USB_C1_RT_INT_ODL";
-		};
-		ec_h1_packet_mode {
-			gpios = <&gpio7 5 GPIO_OUT_LOW>;
-			enum-name = "GPIO_PACKET_MODE_EN";
-			label = "EC_H1_PACKET_MODE";
-		};
-		m2_ssd_pln {
-			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
-			enum-name = "GPIO_M2_SSD_PLN";
-			label = "M2_SSD_PLN";
-		};
-		m2_ssd_pla {
-			gpios = <&gpio7 0 GPIO_INPUT>;
-			label = "M2_SSD_PLA";
-		};
-		ccd_mode_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-			label = "CCD_MODE_ODL";
-		};
-		ec_slp_s0ix {
-			gpios = <&gpio7 2 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_SLP_S0IX";
-		};
-		gpio_unused_gpio41: unused_gpio41 {
-			#gpio-cells = <0>;
-			gpios = <&gpio4 1 (GPIO_INPUT | GPIO_PULL_UP)>;
-			enum-name = "GPIO_USB_C1_LS_EN";
-			label = "UNUSED_GPIO41";
-		};
-		ec_kb_bl_en {
-			gpios = <&gpio8 6 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_KB_BL_EN";
-		};
-		ec_espi_alert_l {
-			gpios = <&gpio5 7 (GPIO_INPUT | GPIO_PULL_UP)>;
-			label = "EC_ESPI_ALERT_L";
-		};
-		ec_edp_bl_en {
-			gpios = <&gpiod 3 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_ENABLE_BACKLIGHT";
-			label = "EC_EDP_BL_EN";
-		};
-		ec_i2c0_sensor_scl {
-			gpios = <&gpiob 5 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SCL";
-			label = "EC_I2C0_SENSOR_SCL";
-		};
-		ec_i2c0_sensor_sda {
-			gpios = <&gpiob 4 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C0_SENSOR_SDA";
-			label = "EC_I2C0_SENSOR_SDA";
-		};
-		ec_i2c1_usb_c0_scl {
-			gpios = <&gpio9 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SCL";
-			label = "EC_I2C1_USB_C0_SCL";
-		};
-		ec_i2c1_usb_c0_sda {
-			gpios = <&gpio8 7 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C1_USB_C0_SDA";
-			label = "EC_I2C1_USB_C0_SDA";
-		};
-		ec_i2c2_usb_c1_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SCL";
-			label = "EC_I2C2_USB_C1_SCL";
-		};
-		ec_i2c2_usb_c1_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C2_USB_C1_SDA";
-			label = "EC_I2C2_USB_C1_SDA";
-		};
-		ec_i2c3_usb_1_mix_scl {
-			gpios = <&gpiod 1 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C3_USB_1_MIX_SCL";
-			label = "EC_I2C3_USB_1_MIX_SCL";
-		};
-		ec_i2c3_usb_1_mix_sda {
-			gpios = <&gpiod 0 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C3_USB_1_MIX_SDA";
-			label = "EC_I2C3_USB_1_MIX_SDA";
-		};
-		ec_i2c5_battery_scl {
-			gpios = <&gpio3 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SCL";
-			label = "EC_I2C5_BATTERY_SCL";
-		};
-		ec_i2c5_battery_sda {
-			gpios = <&gpio3 6 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C5_BATTERY_SDA";
-			label = "EC_I2C5_BATTERY_SDA";
-		};
-		ec_i2c7_eeprom_pwr_scl_r {
-			gpios = <&gpiob 3 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C7_EEPROM_PWR_SCL_R";
-			label = "EC_I2C7_EEPROM_PWR_SCL_R";
-		};
-		ec_i2c7_eeprom_pwr_sda_r {
-			gpios = <&gpiob 2 GPIO_INPUT>;
-			enum-name = "GPIO_EC_I2C7_EEPROM_PWR_SDA_R";
-			label = "EC_I2C7_EEPROM_PWR_SDA_R";
-		};
-		/*
-		 * TODO(b:190743662) Cleanup to possibly remove the enum
-		 */
-		ec_batt_pres_odl {
-			gpios = <&gpioe 1 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		gpio_en_pp5000_fan: en_pp5000_fan {
-			gpios = <&gpio6 1 GPIO_OUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_FAN";
-			label = "EN_PP5000_FAN";
-		};
-		ec_kso_02_inv {
-			gpios = <&gpio1 7 GPIO_OUT_LOW>;
-			enum-name = "GPIO_KBD_KSO2";
-			label = "EC_KSO_02_INV";
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <&lvol_iob4 &lvol_iob5>; /* I2C_SDA0 & SCL0 */
-	};
-
-	unused-pins {
-		compatible = "unused-gpios";
-		unused-gpios =
-			<&gpio3 4 0>,
-			<&gpio4 1 0>,
-			<&gpio5 7 0>, /* EC_ESPI_ALERT_L not stuffed */
-			<&gpio9 6 0>,
-			<&gpio7 2 0>, /* EC_SLP_S0IX not stuffed */
-			<&gpio8 6 0>, /* EC_KB_BL_EN not stuffed */
-			<&gpioa 7 0>, /* EN_PP5000_USB_AG not stuffed */
-			<&gpiof 2 0>,
-			/*
-			 * GPIOB6 cannot be configured as an input.
-			 * Drive output low so signal level doesn't
-			 * depend on default setting of PxDOUT register.
-			 */
-			 <&gpiob 6 GPIO_OUTPUT_LOW>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/include/gpio_map.h b/zephyr/projects/volteer/volteer/include/gpio_map.h
deleted file mode 100644
index 2d6f5f87ee..0000000000
--- a/zephyr/projects/volteer/volteer/include/gpio_map.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-#include "extpower.h"
-#include "lid_switch.h"
-#include "power_button.h"
-
-/*
- * Without https://github.com/zephyrproject-rtos/zephyr/pull/29282, we need
- * to manually link GPIO_ defines that platform/ec code expects to the
- * enum gpio_signal values that are generated by device tree bindings.
- *
- * Note we only need to create aliases for GPIOs that are referenced in common
- * platform/ec code.
- */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PG_EC_DSW_PWROK
-
-/* Helper macros for generating CROS_EC_GPIO_INTERRUPTS */
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ
-#define POWER_SIGNAL_INT(gpio, edge) \
-	GPIO_INT(gpio, edge, power_signal_interrupt)
-#define AP_PROCHOT_INT(gpio, edge) \
-	GPIO_INT(gpio, edge, throttle_ap_prochot_input_interrupt)
-#define POWER_BUTTON_INT(gpio, edge) \
-	GPIO_INT(gpio, edge, power_button_interrupt)
-#else
-#define POWER_SIGNAL_INT(gpio, edge)
-#define AP_PROCHOT_INT(gpio, edge)
-#define POWER_BUTTON_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_USBC
-#define TCPC_ALERT_INT(gpio, edge) GPIO_INT(gpio, edge, tcpc_alert_event)
-#define PPC_INT(gpio, edge) GPIO_INT(gpio, edge, ppc_interrupt)
-#define BC12_INT(gpio, edge) GPIO_INT(gpio, edge, bc12_interrupt)
-#else
-#define TCPC_ALERT_INT(gpio, edge)
-#define PPC_INT(gpio, edge)
-#define BC12_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400
-#define TCS3400_INT(gpio, edge) GPIO_INT(gpio, edge, tcs3400_interrupt)
-#else
-#define TCS3400_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
-#define BMI260_INT(gpio, edge) GPIO_INT(gpio, edge, bmi260_interrupt)
-#else
-#define BMI260_INT(gpio, edge)
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_INT(gpio, edge) GPIO_INT(gpio, edge, \
-						 gmr_tablet_switch_isr)
-#define GMR_TABLET_MODE_GPIO_L	GPIO_TABLET_MODE_L
-#else
-#define GMR_TABLET_MODE_INT(gpio, edge)
-#endif
-
-#define GPIO_EC_BATT_PRES_ODL GPIO_BATT_PRES_ODL
-
-/*
- * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
- *
- * Each GPIO_INT requires three parameters:
- *   gpio_signal - The enum gpio_signal for the interrupt gpio
- *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
- *   handler - The platform/ec interrupt handler.
- *
- * Ensure that this files includes all necessary headers to declare all
- * referenced handler functions.
- *
- * For example, one could use the follow definition:
- * #define EC_CROS_GPIO_INTERRUPTS \
- *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
- */
-#define EC_CROS_GPIO_INTERRUPTS                                            \
-	BMI260_INT(GPIO_EC_IMU_INT_L, GPIO_INT_EDGE_FALLING)               \
-	GMR_TABLET_MODE_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH)        \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)  \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)         \
-	GPIO_INT(GPIO_EC_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)       \
-	POWER_SIGNAL_INT(GPIO_PCH_SLP_S0_L, GPIO_INT_EDGE_BOTH)            \
-	POWER_SIGNAL_INT(GPIO_PCH_SLP_S3_L, GPIO_INT_EDGE_BOTH)            \
-	POWER_SIGNAL_INT(GPIO_PCH_SLP_SUS_L, GPIO_INT_EDGE_BOTH)           \
-	POWER_SIGNAL_INT(GPIO_PG_EC_DSW_PWROK, GPIO_INT_EDGE_BOTH)         \
-	POWER_SIGNAL_INT(GPIO_PG_EC_RSMRST_ODL, GPIO_INT_EDGE_BOTH)        \
-	POWER_SIGNAL_INT(GPIO_PCH_DSW_PWROK, GPIO_INT_EDGE_BOTH)           \
-	POWER_SIGNAL_INT(GPIO_PG_EC_ALL_SYS_PWRGD, GPIO_INT_EDGE_BOTH)     \
-	POWER_BUTTON_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH)          \
-	TCPC_ALERT_INT(GPIO_USB_C0_TCPC_INT_ODL, GPIO_INT_EDGE_BOTH)       \
-	TCPC_ALERT_INT(GPIO_USB_C1_TCPC_INT_ODL, GPIO_INT_EDGE_BOTH)       \
-	TCS3400_INT(GPIO_EC_ALS_RGB_INT_L, GPIO_INT_EDGE_FALLING)          \
-	PPC_INT(GPIO_USB_C0_PPC_INT_ODL, GPIO_INT_EDGE_BOTH)               \
-	PPC_INT(GPIO_USB_C1_PPC_INT_ODL, GPIO_INT_EDGE_BOTH)               \
-	BC12_INT(GPIO_USB_C0_BC12_INT_ODL, GPIO_INT_EDGE_BOTH)             \
-	BC12_INT(GPIO_USB_C1_MIX_INT_ODL, GPIO_INT_EDGE_BOTH)              \
-	AP_PROCHOT_INT(GPIO_EC_PROCHOT_IN_L, GPIO_INT_EDGE_BOTH)           \
-	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt) \
-	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/volteer/volteer/include/pwm_map.h b/zephyr/projects/volteer/volteer/include/pwm_map.h
deleted file mode 100644
index 67ab70936f..0000000000
--- a/zephyr/projects/volteer/volteer/include/pwm_map.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_CHROME_PWM_MAP_H
-#define __ZEPHYR_CHROME_PWM_MAP_H
-
-#include <devicetree.h>
-
-#include "config.h"
-
-#include "pwm/pwm.h"
-
-/*
- * TODO(b/177452529): eliminate the dependency on enum pwm_channel
- * and configure this information directly from the device tree.
- */
-#define PWM_CH_LED4_SIDESEL	NAMED_PWM(led3_sidesel)
-
-#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
-
-#define PWM_CH_FAN		NAMED_PWM(fan)
-
-#endif /* __ZEPHYR_CHROME_PWM_MAP_H */
diff --git a/zephyr/projects/volteer/volteer/keyboard.dts b/zephyr/projects/volteer/volteer/keyboard.dts
deleted file mode 100644
index e9b5cdf0a1..0000000000
--- a/zephyr/projects/volteer/volteer/keyboard.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	cros-keyscan {
-		compatible = "cros-keyscan";
-
-		actual-key-mask = <
-			0x14	/* C0 */
-			0xff	/* C1 */
-			0xff	/* C2 */
-			0xff	/* C3 */
-			0xff	/* C4 */
-			0xf5	/* C5 */
-			0xff	/* C6 */
-			0xa4	/* C7 */
-			0xff	/* C8 */
-			0xfe	/* C9 */
-			0x55	/* C10 */
-			0xfa	/* C11 */
-			0xca	/* C12 */
-			0	/* C13 - for keypad */
-			0	/* C14 - for keypad */
-			>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/motionsense.dts b/zephyr/projects/volteer/volteer/motionsense.dts
deleted file mode 100644
index e22d5571dc..0000000000
--- a/zephyr/projects/volteer/volteer/motionsense.dts
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright (c) 2020 The Chromium OS Authors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <dt-bindings/motionsense/utils.h>
-
-
-/ {
-	aliases {
-		/*
-		 * motion sense's <>_INT_EVENT is handled
-		 * by alias. Using the alias, each driver creates
-		 * its own <>_INT_EVENT.
-		 */
-		bmi260-int = &base_accel;
-		tcs3400-int = &als_clear;
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		mutex_bma255: bma255-mutex {
-			label = "BMA255_MUTEX";
-		};
-
-		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
-		};
-	};
-
-	/* Rotation matrix used by drivers. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <1 0 0
-				 0 (-1) 0
-				 0 0 (-1)>;
-		};
-		base_rot_ref: base-rotation-ref {
-			mat33 = <0 1 0
-				 (-1) 0 0
-				 0 0 1>;
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 *
-	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
-	 * a common structure defined in accelgyro.h.
-	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
-	 * "struct als_drv_data_t" in accelgyro.h
-	 */
-	motionsense-sensor-data {
-		bma255_data: bma255-drv-data {
-			compatible = "cros-ec,drvdata-bma255";
-			status = "okay";
-		};
-
-		bmi260_data: bmi260-drv-data {
-			compatible = "cros-ec,drvdata-bmi260";
-			status = "okay";
-		};
-
-		tcs_clear_data: tcs3400-clear-drv-data {
-			compatible = "cros-ec,drvdata-tcs3400-clear";
-			status = "okay";
-
-			als-drv-data {
-				compatible = "cros-ec,accelgyro-als-drv-data";
-				als-cal {
-					scale = <1>;
-					uscale = <0>;
-					offset = <0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-			};
-		};
-
-		tcs_rgb_data: tcs3400-rgb-drv-data {
-			compatible = "cros-ec,drvdata-tcs3400-rgb";
-			status = "okay";
-
-			/* node for rgb_calibration_t defined in accelgyro.h */
-			rgb_calibration {
-				compatible =
-					"cros-ec,accelgyro-rgb-calibration";
-
-				irt = <1>;
-
-				rgb-cal-x {
-					offset = <0>;
-					coeff = <0 0 0 0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-				rgb-cal-y {
-					offset = <0>;
-					coeff = <0 0 0 0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-				rgb-cal-z {
-					offset = <0>;
-					coeff = <0 0 0 0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-			};
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		lid_accel: lid-accel {
-			compatible = "cros-ec,bma255";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&mutex_bma255>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&bma255_data>;
-			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-				};
-			};
-		};
-
-		base_accel: base-accel {
-			compatible = "cros-ec,bmi260-accel";
-			status = "okay";
-
-			label = "Base Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			default-range = <4>;
-			drv-data = <&bmi260_data>;
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-					ec-rate = <(100 * USEC_PER_MSEC)>;
-				};
-				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
-					odr = <(10000 | ROUND_UP_FLAG)>;
-					ec-rate = <(100 * USEC_PER_MSEC)>;
-				};
-			};
-		};
-
-		base-gyro {
-			compatible = "cros-ec,bmi260-gyro";
-			status = "okay";
-
-			label = "Base Gyro";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			default-range = <1000>; /* dps */
-			drv-data = <&bmi260_data>;
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-		};
-
-		als_clear: base-als-clear {
-			compatible = "cros-ec,tcs3400-clear";
-			status = "okay";
-
-			label = "Clear Light";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			port = <&i2c_sensor>;
-			default-range = <0x10000>;
-			drv-data = <&tcs_clear_data>;
-			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <1000>;
-				};
-			};
-		};
-
-		base-als-rgb {
-			compatible = "cros-ec,tcs3400-rgb";
-			status = "okay";
-
-			label = "RGB Light";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
-			drv-data = <&tcs_rgb_data>;
-		};
-	};
-
-	motionsense-sensor-info {
-		compatible = "cros-ec,motionsense-sensor-info";
-
-		/* list of entries for motion_als_sensors */
-		als-sensors = <&als_clear>;
-		/*
-		 * list of GPIO interrupts that have to
-		 * be enabled at initial stage
-		 */
-		sensor-irqs = <&gpio_ec_imu_int_l &gpio_ec_als_rgb_int_l>;
-		/* list of sensors in force mode */
-		accel-force-mode-sensors = <&lid_accel &als_clear>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/prj.conf b/zephyr/projects/volteer/volteer/prj.conf
deleted file mode 100644
index 80bdc2ad44..0000000000
--- a/zephyr/projects/volteer/volteer/prj.conf
+++ /dev/null
@@ -1,152 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-
-CONFIG_WATCHDOG=y
-
-# SoC configuration
-CONFIG_AP=y
-CONFIG_AP_X86_INTEL_TGL=y
-CONFIG_FPU=y
-CONFIG_ARM_MPU=y
-
-# eSPI
-CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_I2C=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_PLATFORM_EC_CBI_EEPROM=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_HCDEBUG=n
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHGRAMP=n
-
-# Keyboard
-CONFIG_PLATFORM_EC_KEYBOARD=y
-CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
-CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
-CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-
-# Battery
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-
-CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM=y
-CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-
-# Keyboard Backlight
-CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
-
-# LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-CONFIG_PLATFORM_EC_LED_PWM=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST=n
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=y
-CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
-CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
-CONFIG_PLATFORM_EC_THROTTLE_AP=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PLATFORM_EC_PWM=y
-
-# Fan
-CONFIG_PLATFORM_EC_FAN=y
-CONFIG_SENSOR=y
-CONFIG_SENSOR_SHELL=n
-CONFIG_TACH_NPCX=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_ALS=y
-CONFIG_PLATFORM_EC_ALS_COUNT=1
-CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-CONFIG_PLATFORM_EC_ALS_TCS3400=y
-
-# Temperature sensors
-CONFIG_PLATFORM_EC_TEMP_SENSOR=y
-CONFIG_PLATFORM_EC_THERMISTOR=y
-
-# Miscellaneous tasks
-CONFIG_HAS_TASK_KEYPROTO=y
-CONFIG_HAS_TASK_POWERBTN=y
-
-# Miscellaneous configs
-CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
-CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
-
-# MKBP event
-CONFIG_PLATFORM_EC_MKBP_EVENT=y
-CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
-
-# USB-C and charging
-CONFIG_HAS_TASK_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
-CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=3
-CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC=1
-CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
-CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_USB_PID=0x503e
-CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
-CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
-CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB=y
-CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
-CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
-CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
-CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2
-CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_FRS=y
-CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_REV30=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
-CONFIG_HAS_TASK_PD_C1=y
-CONFIG_HAS_TASK_PD_INT_C1=y
-CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
-CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
-CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP=n
-CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n
-
-# Flash
-CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=n
-
-# RTC
-CONFIG_PLATFORM_EC_RTC=y
-
-CONFIG_SYSCON=y
diff --git a/zephyr/projects/volteer/volteer/pwm.dts b/zephyr/projects/volteer/volteer/pwm.dts
deleted file mode 100644
index f8a0fef7df..0000000000
--- a/zephyr/projects/volteer/volteer/pwm.dts
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-pwms {
-		compatible = "named-pwms";
-
-		led1_blue: led1_blue {
-			#pwm-cells = <0>;
-			pwms = <&pwm2 0 PWM_POLARITY_INVERTED>;
-			label = "LED1_BLUE";
-			frequency = <4800>;
-		};
-		led2_green: led2_green  {
-			#pwm-cells = <0>;
-			pwms = <&pwm0 0 PWM_POLARITY_INVERTED>;
-			label = "LED2_GREEN";
-			frequency = <4800>;
-		};
-		led3_red: led3_red {
-			#pwm-cells = <0>;
-			pwms = <&pwm1 0 PWM_POLARITY_INVERTED>;
-			label = "LED3_RED";
-			frequency = <4800>;
-		};
-		led3_sidesel: led3_sidesel {
-			#pwm-cells = <0>;
-			pwms = <&pwm7 0 PWM_POLARITY_INVERTED>;
-			label = "LED4_SIDESEL";
-			frequency = <2400>;
-		};
-		kblight {
-			pwms = <&pwm3 0 0>;
-			label = "KBLIGHT";
-			frequency = <2400>;
-		};
-		pwm_fan: fan {
-			pwms = <&pwm5 0 0>;
-			label = "FAN";
-			frequency = <25000>;
-		};
-	};
-};
-
-/* Green LED */
-&pwm0 {
-	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-};
-
-/* Red LED */
-&pwm1 {
-	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-};
-
-/* Blue LED */
-&pwm2 {
-	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-};
-
-/* Keyboard backlight */
-&pwm3 {
-	status = "okay";
-};
-
-/* Fan control */
-&pwm5 {
-	status = "okay";
-	drive-open-drain;
-};
-
-/* Side selection LED */
-&pwm7 {
-	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-};
diff --git a/zephyr/projects/volteer/volteer/pwm_leds.dts b/zephyr/projects/volteer/volteer/pwm_leds.dts
deleted file mode 100644
index 659cdecbf2..0000000000
--- a/zephyr/projects/volteer/volteer/pwm_leds.dts
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	pwmleds {
-		compatible = "pwm-leds";
-		pwm_led0: pwm_led_0 {
-			pwms = <&led3_red
-				&led2_green
-				&led1_blue
-				&led3_sidesel
-				>;
-		};
-	};
-
-	cros-pwmleds {
-		compatible = "cros-ec,pwm-leds";
-
-		leds = <&pwm_led0>;
-
-		color-map-red    = <100   0   0>;
-		color-map-green  = <  0 100   0>;
-		color-map-blue   = <  0   0 100>;
-		color-map-yellow = <100  70   0>;
-		color-map-white  = <100  70 100>;
-		color-map-amber  = <100  20   0>;
-
-		brightness-range = <255 255 255 0 0 0>;
-	};
-};
diff --git a/zephyr/projects/volteer/volteer/zmake.yaml b/zephyr/projects/volteer/volteer/zmake.yaml
deleted file mode 100644
index a89c0287af..0000000000
--- a/zephyr/projects/volteer/volteer/zmake.yaml
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: volteer
-dts-overlays:
-  - bb_retimer.dts
-  - cbi_eeprom.dts
-  - fan.dts
-  - gpio.dts
-  - keyboard.dts
-  - motionsense.dts
-  - pwm.dts
-  - pwm_leds.dts
-supported-toolchains:
-  - coreboot-sdk
-  - zephyr
-supported-zephyr-versions:
-  - v2.6
-output-type: npcx
diff --git a/zephyr/shim/CMakeLists.txt b/zephyr/shim/CMakeLists.txt
deleted file mode 100644
index e36101756a..0000000000
--- a/zephyr/shim/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-add_subdirectory("chip")
-add_subdirectory("core")
-add_subdirectory("src")
diff --git a/zephyr/shim/chip/CMakeLists.txt b/zephyr/shim/chip/CMakeLists.txt
deleted file mode 100644
index 5c76a4163a..0000000000
--- a/zephyr/shim/chip/CMakeLists.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if (DEFINED CONFIG_SOC_FAMILY_NPCX)
-	add_subdirectory(npcx)
-elseif (DEFINED CONFIG_SOC_FAMILY_RISCV_ITE)
-	add_subdirectory(it8xxx2)
-elseif (DEFINED CONFIG_SOC_POSIX)
-	add_subdirectory(posix)
-endif()
-
diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt
deleted file mode 100644
index 7a92a3cfb6..0000000000
--- a/zephyr/shim/chip/it8xxx2/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_include_directories(include)
-
-zephyr_library_sources(clock.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_EC           pinmux.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_ITE   keyboard_raw.c)
diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c
deleted file mode 100644
index 2bcf9e2899..0000000000
--- a/zephyr/shim/chip/it8xxx2/clock.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/clock_control.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <zephyr.h>
-#include <soc/ite_it8xxx2/reg_def_cros.h>
-#include <sys/util.h>
-
-#include "module_id.h"
-
-LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
-
-#define ECPM_NODE		DT_INST(0, ite_it8xxx2_ecpm)
-#define HAL_ECPM_REG_BASE_ADDR	\
-			((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0))
-#define PLLFREQ_MASK		0xf
-
-static const int pll_reg_to_freq[8] = {
-	MHZ(8),
-	MHZ(16),
-	MHZ(24),
-	MHZ(32),
-	MHZ(48),
-	MHZ(64),
-	MHZ(72),
-	MHZ(96)
-};
-
-int clock_get_freq(void)
-{
-	struct ecpm_reg *const ecpm_base = HAL_ECPM_REG_BASE_ADDR;
-	int reg_val = ecpm_base->ECPM_PLLFREQ & PLLFREQ_MASK;
-
-	return pll_reg_to_freq[reg_val];
-}
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
deleted file mode 100644
index e45a08296f..0000000000
--- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FLASH_CHIP_H
-#define __CROS_EC_FLASH_CHIP_H
-
-/*
- * Flash size of IT81202 is 1MB.
- * We use only half space of flash to save time of erasing RW image from flash.
- */
-#define CONFIG_FLASH_SIZE_BYTES         (DT_REG_SIZE(DT_NODELABEL(flash0)) / 2)
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE      DT_REG_ADDR(DT_NODELABEL(flash0))
-/*
- * One page program instruction allows maximum 256 bytes (a page) of data
- * to be programmed.
- */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE   256
-/* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
-						write_block_size)
-/* Erase bank size */
-#define CONFIG_FLASH_ERASE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
-						erase_block_size)
-/* Protect bank size */
-#define CONFIG_FLASH_BANK_SIZE          CONFIG_FLASH_ERASE_SIZE
-
-#define CONFIG_RO_STORAGE_OFF           0x0
-#define CONFIG_RW_STORAGE_OFF           0x0
-
-/*
- * The EC uses the one bank of flash to emulate a SPI-like write protect
- * register with persistent state.
- */
-#define CONFIG_FW_PSTATE_SIZE           CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF            (CONFIG_FLASH_SIZE_BYTES / 2 - \
-						CONFIG_FW_PSTATE_SIZE)
-
-#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/it8xxx2/keyboard_raw.c b/zephyr/shim/chip/it8xxx2/keyboard_raw.c
deleted file mode 100644
index 0096798915..0000000000
--- a/zephyr/shim/chip/it8xxx2/keyboard_raw.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include <device.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <zephyr.h>
-
-#include "drivers/cros_kb_raw.h"
-#include "keyboard_raw.h"
-
-/**
- * Return true if the current value of the given input GPIO port is zero
- */
-int keyboard_raw_is_input_low(int port, int id)
-{
-	/*
-	 * TODO: implement for factory testing KSI and KSO pin as GPIO
-	 *       function.
-	 */
-	return 0;
-}
diff --git a/zephyr/shim/chip/it8xxx2/pinmux.c b/zephyr/shim/chip/it8xxx2/pinmux.c
deleted file mode 100644
index fd8dc7fc8e..0000000000
--- a/zephyr/shim/chip/it8xxx2/pinmux.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <init.h>
-#include <drivers/pinmux.h>
-#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
-#include <soc.h>
-
-static int it8xxx2_pinmux_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxb), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
-	const struct device *portb = DEVICE_DT_GET(DT_NODELABEL(pinmuxb));
-
-	/* SIN0 */
-	pinmux_pin_set(portb, 0, IT8XXX2_PINMUX_FUNC_3);
-	/* SOUT0 */
-	pinmux_pin_set(portb, 1, IT8XXX2_PINMUX_FUNC_3);
-#endif
-
-	return 0;
-}
-SYS_INIT(it8xxx2_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);
-
-/*
- * Init priority is behind CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY to overwrite
- * GPIO_INPUT setting of i2c ports.
- */
-static int it8xxx2_pinmux_init_latr(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxb), okay)
-	{
-		const struct device *portb =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxb));
-
-		/* I2C0 CLK */
-		pinmux_pin_set(portb, 3, IT8XXX2_PINMUX_FUNC_1);
-		/* I2C0 DAT */
-		pinmux_pin_set(portb, 4, IT8XXX2_PINMUX_FUNC_1);
-	}
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxc), okay)
-	{
-		const struct device *portc =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxc));
-
-		/* I2C1 CLK */
-		pinmux_pin_set(portc, 1, IT8XXX2_PINMUX_FUNC_1);
-		/* I2C1 DAT */
-		pinmux_pin_set(portc, 2, IT8XXX2_PINMUX_FUNC_1);
-	}
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxf), okay)
-	{
-		const struct device *portf =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxf));
-
-		/* I2C2 CLK */
-		pinmux_pin_set(portf, 6, IT8XXX2_PINMUX_FUNC_1);
-		/* I2C2 DAT */
-		pinmux_pin_set(portf, 7, IT8XXX2_PINMUX_FUNC_1);
-	}
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxh), okay)
-	{
-		const struct device *porth =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxh));
-
-		/* I2C3 CLK */
-		pinmux_pin_set(porth, 1, IT8XXX2_PINMUX_FUNC_3);
-		/* I2C3 DAT */
-		pinmux_pin_set(porth, 2, IT8XXX2_PINMUX_FUNC_3);
-	}
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxe), okay)
-	{
-		const struct device *porte =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxe));
-
-		/* I2C4 CLK */
-		pinmux_pin_set(porte, 0, IT8XXX2_PINMUX_FUNC_3);
-		/* I2C4 DAT */
-		pinmux_pin_set(porte, 7, IT8XXX2_PINMUX_FUNC_3);
-	}
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c5), okay) && \
-	DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxa), okay)
-	{
-		const struct device *porta =
-				DEVICE_DT_GET(DT_NODELABEL(pinmuxa));
-
-		/* I2C5 CLK */
-		pinmux_pin_set(porta, 4, IT8XXX2_PINMUX_FUNC_3);
-		/* I2C5 DAT */
-		pinmux_pin_set(porta, 5, IT8XXX2_PINMUX_FUNC_3);
-	}
-#endif
-
-	return 0;
-}
-SYS_INIT(it8xxx2_pinmux_init_latr, POST_KERNEL, 52);
diff --git a/zephyr/shim/chip/it8xxx2/system.c b/zephyr/shim/chip/it8xxx2/system.c
deleted file mode 100644
index d9dcd7ccfb..0000000000
--- a/zephyr/shim/chip/it8xxx2/system.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "system.h"
-
-uintptr_t system_get_fw_reset_vector(uintptr_t base)
-{
-	/*
-	 * Because our reset vector is at the beginning of image copy
-	 * (see init.S). So I just need to return 'base' here and EC will jump
-	 * to the reset vector.
-	 */
-	return base;
-}
diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt
deleted file mode 100644
index d3cd4b48fd..0000000000
--- a/zephyr/shim/chip/npcx/CMakeLists.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# When building code coverage, the final Zephyr image isn't actually linked
-# and there's no valid image to program. Skip compiling and linking the NPCX
-# monitor when coverage is enabled.
-if (NOT DEFINED CONFIG_COVERAGE)
-  add_subdirectory(npcx_monitor)
-endif()
-
-zephyr_library_include_directories(include)
-
-zephyr_library_sources(clock.c)
-zephyr_library_sources(gpio.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI  espi.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX  keyboard_raw.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX     shi.c)
-zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
-        system_external_storage.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API
-        system_download_from_flash.c)
-zephyr_library_sources_ifdef(CONFIG_PM_POLICY_APP     power_policy.c)
diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx
deleted file mode 100644
index b044912ae1..0000000000
--- a/zephyr/shim/chip/npcx/Kconfig.npcx
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if PLATFORM_EC
-
-config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY
-	int "System pre-initialization priority"
-	default 15
-	range 10 19
-	depends on SOC_FAMILY_NPCX
-	help
-	  This sets the priority of the NPCX chip system initialization. The
-	  chip system initialization verifies the integrity of the BBRAM and
-	  must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and
-	  must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT.
-
-endif # PLATFORM_EC
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c
deleted file mode 100644
index 8c8bad5596..0000000000
--- a/zephyr/shim/chip/npcx/clock.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/clock_control.h>
-#include <dt-bindings/clock/npcx_clock.h>
-#include <kernel.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <zephyr.h>
-
-#include "clock_chip.h"
-#include "module_id.h"
-
-LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
-
-#define CDCG_NODE		DT_INST(0, nuvoton_npcx_pcc)
-#define HAL_CDCG_REG_BASE_ADDR \
-			((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1))
-
-int clock_get_freq(void)
-{
-	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
-	const struct npcx_clk_cfg clk_cfg = {
-		.bus = NPCX_CLOCK_BUS_CORE,
-	};
-	uint32_t rate;
-
-	if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&clk_cfg,
-				   &rate) != 0) {
-		LOG_ERR("Get %s clock rate error", clk_dev->name);
-		return -EIO;
-	}
-
-	return rate;
-}
-
-void clock_turbo(void)
-{
-	struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR;
-
-	/* For NPCX7:
-	 * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since
-	 * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
-	 */
-	cdcg_base->HFCGP = 0x01;
-	cdcg_base->HFCBCD = BIT(4);
-}
-
-void clock_normal(void)
-{
-	struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR;
-
-	cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
-	cdcg_base->HFCBCD  = (FIUDIV_VAL << 4);
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	/* Assume we have a single task using MODULE_FAST_CPU */
-	if (module == MODULE_FAST_CPU) {
-		if (enable)
-			clock_turbo();
-		else
-			clock_normal();
-	}
-}
diff --git a/zephyr/shim/chip/npcx/espi.c b/zephyr/shim/chip/npcx/espi.c
deleted file mode 100644
index 2115f388d6..0000000000
--- a/zephyr/shim/chip/npcx/espi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <sys/util.h>
-
-#include "drivers/espi.h"
-#include "soc_espi.h"
-#include "zephyr_espi_shim.h"
-
-bool is_acpi_command(uint32_t data)
-{
-	struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data;
-
-	return acpi->type;
-}
-
-uint32_t get_acpi_value(uint32_t data)
-{
-	struct espi_evt_data_acpi *acpi = (struct espi_evt_data_acpi *)&data;
-
-	return acpi->data;
-}
-
-bool is_8042_ibf(uint32_t data)
-{
-	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
-
-	return kbc->evt & HOST_KBC_EVT_IBF;
-}
-
-bool is_8042_obe(uint32_t data)
-{
-	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
-
-	return kbc->evt & HOST_KBC_EVT_OBE;
-}
-
-uint32_t get_8042_type(uint32_t data)
-{
-	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
-
-	return kbc->type;
-}
-
-uint32_t get_8042_data(uint32_t data)
-{
-	struct espi_evt_data_kbc *kbc = (struct espi_evt_data_kbc *)&data;
-
-	return kbc->data;
-}
diff --git a/zephyr/shim/chip/npcx/gpio.c b/zephyr/shim/chip/npcx/gpio.c
deleted file mode 100644
index 148e1a97c9..0000000000
--- a/zephyr/shim/chip/npcx/gpio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <kernel.h>
-
-#include <logging/log.h>
-
-#include "gpio.h"
-#include "gpio/gpio.h"
-
-LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR);
-
-static const struct unused_pin_config unused_pin_configs[] = {
-	UNUSED_GPIO_CONFIG_LIST
-};
-
-int gpio_config_unused_pins(void)
-{
-	for (size_t i = 0; i < ARRAY_SIZE(unused_pin_configs); ++i) {
-		int rv;
-		int flags;
-		const struct device *dev =
-			device_get_binding(unused_pin_configs[i].dev_name);
-
-		if (dev == NULL) {
-			LOG_ERR("Not found (%s)",
-				unused_pin_configs[i].dev_name);
-			return -ENOTSUP;
-		}
-
-		/*
-		 * Set the default setting for the floating IOs. The floating
-		 * IOs cause the leakage current. Set unused pins as input with
-		 * internal PU to prevent extra power consumption.
-		 */
-		if (unused_pin_configs[i].flags == 0)
-			flags = GPIO_INPUT | GPIO_PULL_UP;
-		else
-			flags = unused_pin_configs[i].flags;
-
-		rv = gpio_pin_configure(dev, unused_pin_configs[i].pin, flags);
-
-		if (rv < 0) {
-			LOG_ERR("Config failed %s-%d (%d)",
-				unused_pin_configs[i].dev_name,
-				unused_pin_configs[i].pin, rv);
-			return rv;
-		}
-	}
-
-	return 0;
-}
diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h
deleted file mode 100644
index 0c39ed8174..0000000000
--- a/zephyr/shim/chip/npcx/include/clock_chip.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CLOCK_CHIP_H
-#define __CROS_EC_CLOCK_CHIP_H
-
-/**
- * TODO(b:180112248) implement in zephyr's clock_control.h
- */
-void clock_turbo(void);
-
-#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h
deleted file mode 100644
index 622633c570..0000000000
--- a/zephyr/shim/chip/npcx/include/flash_chip.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FLASH_CHIP_H
-#define __CROS_EC_FLASH_CHIP_H
-
-#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#ifdef CONFIG_FLASH_SIZE
-#define CONFIG_FLASH_SIZE_BYTES	(CONFIG_FLASH_SIZE * 1024)
-#else
-#define CONFIG_FLASH_SIZE_BYTES 0x0
-#endif
-
-/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */
-#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
-
-/* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
-
-#define CONFIG_RW_STORAGE_OFF 0
-
-/* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
-
-#endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h
deleted file mode 100644
index aab166e6f1..0000000000
--- a/zephyr/shim/chip/npcx/include/rom_chip.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ROM_CHIP_H
-#define __CROS_EC_ROM_CHIP_H
-
-#include "common.h"
-
-/* Enumerations of ROM api functions */
-enum API_SIGN_OPTIONS_T {
-	SIGN_NO_CHECK = 0,
-	SIGN_CRC_CHECK = 1,
-};
-
-enum API_RETURN_STATUS_T {
-	/* Successful download */
-	API_RET_STATUS_OK = 0,
-	/* Address is outside of flash or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SRC_ADDR = 1,
-	/* Address is outside of RAM or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_DST_ADDR = 2,
-	/* Size is 0 or not 4 bytes aligned. */
-	API_RET_STATUS_INVALID_SIZE = 3,
-	/* Flash Address + Size is out of flash. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4,
-	/* RAM Address + Size is out of RAM. */
-	API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5,
-	/* Wrong sign option. */
-	API_RET_STATUS_INVALID_SIGN = 6,
-	/* Error during Code copy. */
-	API_RET_STATUS_COPY_FAILED = 7,
-	/* Execution Address is outside of RAM */
-	API_RET_STATUS_INVALID_EXE_ADDR = 8,
-	/* Bad CRC value */
-	API_RET_STATUS_INVALID_SIGNATURE = 9,
-};
-
-/* Macro functions of ROM api functions */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
-#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
-
-/* Declarations of ROM api functions */
-typedef void (*download_from_flash_ptr) (
-	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
-	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
-	uint32_t exe_addr, /* jump to this address after download if not zero */
-	enum API_RETURN_STATUS_T *status /* Status fo download */
-);
-
-#endif /* __CROS_EC_ROM_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h
deleted file mode 100644
index c77c2a8338..0000000000
--- a/zephyr/shim/chip/npcx/include/system_chip.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SYSTEM_CHIP_H_
-#define __CROS_EC_SYSTEM_CHIP_H_
-
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-
-/* TODO(b:179900857) Clean this up too */
-#undef IS_BIT_SET
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-
-/*****************************************************************************/
-/* Memory mapping */
-#define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-
-/******************************************************************************/
-/* Optional M4 Registers */
-#define CPU_MPU_CTRL		REG32(0xE000ED94)
-#define CPU_MPU_RNR		REG32(0xE000ED98)
-#define CPU_MPU_RBAR		REG32(0xE000ED9C)
-#define CPU_MPU_RASR		REG32(0xE000EDA0)
-
-/*
- * Region assignment. 7 as the highest, a higher index has a higher priority.
- * For example, using 7 for .iram.text allows us to mark entire RAM XN except
- * .iram.text, which is used for hibernation.
- * Region assignment is currently wasteful and can be changed if more
- * regions are needed in the future. For example, a second region may not
- * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be
- * made mutually exclusive.
- */
-enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
-	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
-};
-
-/*
- * Configure the specific memory addresses in the the MPU
- * (Memory Protection Unit) for Nuvoton different chip series.
- */
-void system_mpu_config(void);
-
-/* The utilities and variables depend on npcx chip family */
-#if defined(CONFIG_SOC_SERIES_NPCX5) || \
-	defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series or if
- * CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API is defined.
- */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-				uint32_t size, uint32_t exeAddr);
-
-/* Begin address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_start;
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_end;
-
-/* Begin address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_start;
-
-/* End address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_end;
-#endif
-
-#endif // __CROS_EC_SYSTEM_CHIP_H_
diff --git a/zephyr/shim/chip/npcx/keyboard_raw.c b/zephyr/shim/chip/npcx/keyboard_raw.c
deleted file mode 100644
index aa075d2d56..0000000000
--- a/zephyr/shim/chip/npcx/keyboard_raw.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include <device.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <soc_gpio.h>
-#include <zephyr.h>
-
-#include "drivers/cros_kb_raw.h"
-#include "keyboard_raw.h"
-
-/**
- * Return true if the current value of the given input GPIO port is zero
- */
-int keyboard_raw_is_input_low(int port, int id)
-{
-	const struct device *io_dev = npcx_get_gpio_dev(port);
-
-	return gpio_pin_get_raw(io_dev, id) == 0;
-}
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
deleted file mode 100644
index 661eb86e91..0000000000
--- a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# The NPCX monitor source needs the chip type and flash layout information
-# provided by the board configuration. This is provided by
-# zephyr/shim/include/config_chip.h, so we need all the include directories
-# of the Zephyr application.
-zephyr_get_include_directories_for_lang(C zephyr_includes STRIP_PREFIX)
-
-# Something in the zephyr_get_compile_options_for_lang() output causes the
-# "-imacros" option to get dropped during expansion when passed to
-# target_compile_options().  Fetch the compile options directly from
-# zephyr_interface which works as expected.
-get_property(
-  zephyr_compile_options
-  TARGET zephyr_interface
-  PROPERTY INTERFACE_COMPILE_OPTIONS
-  )
-
-add_executable(npcx_monitor npcx_monitor.c)
-target_include_directories(npcx_monitor PRIVATE
-  "${PLATFORM_EC}/zephyr/shim/include"
-  "${PLATFORM_EC}/zephyr/shim/chip/npcx/include"
-  )
-target_include_directories(npcx_monitor PRIVATE "${zephyr_includes}")
-target_compile_options(npcx_monitor PRIVATE "${zephyr_compile_options}")
-
-target_link_options(npcx_monitor BEFORE PRIVATE
-  -nostdlib
-  -g
-  -mthumb
-  -Wl,-T,${CMAKE_CURRENT_SOURCE_DIR}/npcx_monitor.ld
-  )
-
-# Create the NPCX monitor binary, locate it the root of the build
-# directory as it needs to be found by the flash_util script
-set(npcx_monitor_elf ${CMAKE_CURRENT_BINARY_DIR}/npcx_monitor.elf)
-set(npcx_monitor_bin ${CMAKE_BINARY_DIR}/npcx_monitor.bin)
-
-add_custom_target(generate_npcx_monitor
-  COMMAND ${CMAKE_OBJCOPY} -O binary ${npcx_monitor_elf} ${npcx_monitor_bin}
-  BYPRODUCTS ${npcx_monitor_bin}
-  DEPENDS npcx_monitor
-  )
-
-add_dependencies(zephyr generate_npcx_monitor)
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
deleted file mode 100644
index 2bd9455a91..0000000000
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool - monitor firmware
- */
-
-#include <stdint.h>
-#include <sys/util.h>
-#include "config_chip.h"
-#include "npcx_monitor.h"
-#include "registers.h"
-
-/*
- * TODO(b/197162681): This was copied from chip/npcx/spiflashfw but this
- * needs to be moved to Zephyr upstream
- */
-
-/*****************************************************************************/
-/* spi flash internal functions */
-void sspi_flash_pinmux(int enable)
-{
-	if (enable)
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-
-	/* CS0/1 pinmux */
-	if (enable) {
-#if (FIU_CHIP_SELECT == 1)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-#elif (FIU_CHIP_SELECT == 2)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-#endif
-	} else {
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_1);
-		CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_F_SPI_CS1_2);
-	}
-}
-
-void sspi_flash_tristate(int enable)
-{
-	if (enable) {
-		/* Enable FIU pins to tri-state */
-		SET_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	} else {
-		/* Disable FIU pins to tri-state */
-		CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
-	}
-}
-
-void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
-{
-	/* set UMA_CODE */
-	NPCX_UMA_CODE = code;
-	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
-	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-		;
-}
-
-void sspi_flash_cs_level(int level)
-{
-	/* level is high */
-	if (level) {
-		/* Set chip select to high */
-		SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	} else { /* level is low */
-		/* Set chip select to low */
-		CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
-	}
-}
-
-void sspi_flash_wait_ready(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_BUSY;
-
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Command for Read status register */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
-	do {
-		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
-		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
-			;
-	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
-	/* Chip Select high. */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_write_enable(void)
-{
-	uint8_t mask = SPI_FLASH_SR1_WEL;
-	/* Write enable command */
-	sspi_flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
-	/* Wait for flash is not busy */
-	sspi_flash_wait_ready();
-
-	if (NPCX_UMA_DB0 & mask)
-		return 1;
-	else
-		return 0;
-}
-
-void sspi_flash_set_address(uint32_t dest_addr)
-{
-	uint8_t *addr = (uint8_t *)&dest_addr;
-	/* Write address */
-	NPCX_UMA_AB2 = addr[2];
-	NPCX_UMA_AB1 = addr[1];
-	NPCX_UMA_AB0 = addr[0];
-}
-
-void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
-{
-	unsigned int i;
-	/* Chip Select down. */
-	sspi_flash_cs_level(0);
-	/* Set erase address */
-	sspi_flash_set_address(dest_addr);
-	/* Start write */
-	sspi_flash_execute_cmd(CMD_FLASH_PROGRAM, MASK_CMD_WR_ADR);
-	for (i = 0; i < bytes; i++) {
-		sspi_flash_execute_cmd(*data, MASK_CMD_WR_ONLY);
-		data++;
-	}
-	/* Chip Select up */
-	sspi_flash_cs_level(1);
-}
-
-int sspi_flash_physical_clear_stsreg(void)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-	/* Enable write */
-	sspi_flash_write_enable();
-
-	NPCX_UMA_DB0 = 0x0;
-	NPCX_UMA_DB1 = 0x0;
-
-	/* Write status register 1/2 */
-	sspi_flash_execute_cmd(CMD_WRITE_STATUS_REG, MASK_CMD_WR_2BYTE);
-
-	/* Wait writing completed */
-	sspi_flash_wait_ready();
-
-	/* Read status register 1/2 for checking */
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	sspi_flash_execute_cmd(CMD_READ_STATUS_REG2, MASK_CMD_RD_1BYTE);
-	if (NPCX_UMA_DB0 != 0x00)
-		return 0;
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-
-	return 1;
-}
-
-void sspi_flash_physical_write(int offset, int size, const char *data)
-{
-	int dest_addr = offset;
-	const int sz_page = CONFIG_FLASH_WRITE_IDEAL_SIZE;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Write the data per CONFIG_FLASH_WRITE_IDEAL_SIZE bytes */
-	for (; size >= sz_page; size -= sz_page) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, sz_page, data);
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-
-		data += sz_page;
-		dest_addr += sz_page;
-	}
-
-	/* Handle final partial page, if any */
-	if (size != 0) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Burst UMA transaction */
-		sspi_flash_burst_write(dest_addr, size, data);
-
-		/* Wait write completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-void sspi_flash_physical_erase(int offset, int size)
-{
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Alignment has been checked in upper layer */
-	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
-		/* Enable write */
-		sspi_flash_write_enable();
-		/* Set erase address */
-		sspi_flash_set_address(offset);
-		/* Start erase */
-		sspi_flash_execute_cmd(CMD_SECTOR_ERASE, MASK_CMD_ADR);
-
-		/* Wait erase completed */
-		sspi_flash_wait_ready();
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-}
-
-int sspi_flash_verify(int offset, int size, const char *data)
-{
-	int i, result;
-	uint8_t *ptr_flash;
-	uint8_t *ptr_mram;
-	uint8_t cmp_data;
-
-	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
-	result = 1;
-
-	/* Disable tri-state */
-	sspi_flash_tristate(0);
-
-	/* Start to verify */
-	for (i = 0; i < size; i++) {
-		cmp_data = ptr_mram ? ptr_mram[i] : 0xFF;
-		if (ptr_flash[i] != cmp_data) {
-			result = 0;
-			break;
-		}
-	}
-
-	/* Enable tri-state */
-	sspi_flash_tristate(1);
-	return result;
-}
-
-int sspi_flash_get_image_used(const char *fw_base)
-{
-	const uint8_t *image;
-	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
-
-	image = (const uint8_t *)fw_base;
-	/*
-	 * Scan backwards looking for 0xea byte, which is by definition the
-	 * last byte of the image.  See ec.lds.S for how this is inserted at
-	 * the end of the image.
-	 */
-	for (size--; size > 0 && image[size] != 0xea; size--)
-		;
-
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
-}
-
-/* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
-sspi_flash_upload(int spi_offset, int spi_size)
-{
-	/*
-	 * Flash image has been uploaded to Code RAM
-	 */
-	uint32_t sz_image;
-	uint32_t uut_tag;
-	const char *image_base;
-	uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG;
-	struct monitor_header_tag *monitor_header =
-		(struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR;
-
-	*flag_upload = 0;
-
-	uut_tag = monitor_header->tag;
-	/* If it is UUT tag, read required parameters from header */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG) {
-		sz_image = monitor_header->size;
-		spi_offset = monitor_header->dest_addr;
-		image_base = (const char *)(monitor_header->src_addr);
-	} else {
-		sz_image = spi_size;
-		image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
-	}
-
-	/* Unlock & stop watchdog */
-	NPCX_WDSDM = 0x87;
-	NPCX_WDSDM = 0x61;
-	NPCX_WDSDM = 0x63;
-
-	/* UMA Unlock */
-	CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK);
-
-	/*
-	 * If UUT is used, assuming the target is the internal flash.
-	 * Don't switch the pinmux and make sure bit 7 of DEVALT0 is set.
-	 */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-	else
-		/* Set pinmux first */
-		sspi_flash_pinmux(1);
-
-	/* Get size of image automatically */
-	if (sz_image == 0)
-		sz_image = sspi_flash_get_image_used(image_base);
-
-	/* Clear status reg of spi flash for protection */
-	if (sspi_flash_physical_clear_stsreg()) {
-		/* Start to erase */
-		sspi_flash_physical_erase(spi_offset, sz_image);
-		/* Start to write */
-		if (image_base != NULL)
-			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
-		/* Verify data */
-		if (sspi_flash_verify(spi_offset, sz_image, image_base))
-			*flag_upload |= 0x02;
-	}
-	if (uut_tag != NPCX_MONITOR_UUT_TAG)
-		/* Disable pinmux */
-		sspi_flash_pinmux(0);
-
-	/* Mark we have finished upload work */
-	*flag_upload |= 0x01;
-
-	/* Return the status back to ROM code is required for UUT */
-	if (uut_tag == NPCX_MONITOR_UUT_TAG)
-		return *flag_upload;
-
-	/* Infinite loop */
-	for (;;)
-		;
-}
-
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
deleted file mode 100644
index c5415d94db..0000000000
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_NPCX_MONITOR_H
-#define __CROS_EC_NPCX_MONITOR_H
-
-#include <stdint.h>
-
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
-
-/* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
-
-struct monitor_header_tag {
-	/* offset 0x00: TAG NPCX_MONITOR_TAG */
-	uint32_t tag;
-	/* offset 0x04: Size of the binary being programmed (in bytes) */
-	uint32_t size;
-	/* offset 0x08: The RAM address of the binary to program into the SPI */
-	uint32_t src_addr;
-	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
-	uint32_t dest_addr;
-	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
-	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
-	/* offset 0x12: Reserved */
-	uint16_t reserved;
-} __packed;
-
-#endif /* __CROS_EC_NPCX_MONITOR_H */
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
deleted file mode 100644
index 03e38b0609..0000000000
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX SoC spi flash update tool
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0
-}
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(sspi_flash_upload)
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    .startup_text :
-    {
-        . = ALIGN(4);
-        *(.startup_text )	/* Startup code */
-        . = ALIGN(4);
-    } >CODERAM
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to CODERAM.
-     */
-    .text :
-    {
-        . = ALIGN(4);
-        *(.text .text.*)			/* all remaining code */
-        *(.rodata .rodata.*)		/* read-only data (constants) */
-    } >CODERAM
-
-    . = ALIGN(4);
-    _etext = .;
-
-    /*
-     * This address is used by the startup code to
-     * initialise the .data section.
-     */
-    _sidata = _etext;
-
-}
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h
deleted file mode 100644
index cc0a6b96fe..0000000000
--- a/zephyr/shim/chip/npcx/npcx_monitor/registers.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for NPCX processor
- *
- * This is meant to be temporary until the NPCX monitor support is moved
- * to Zephyr upstream
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-/*
- * The monitor code doesn't build cleanly under the Zephyr environment if
- * include/common.h is included. Replicate the register access macros until
- * this code is moved upstream.
- */
-
-/* Macros to access registers */
-#define REG64_ADDR(addr) ((volatile uint64_t *)(addr))
-#define REG32_ADDR(addr) ((volatile uint32_t *)(addr))
-#define REG16_ADDR(addr) ((volatile uint16_t *)(addr))
-#define REG8_ADDR(addr)  ((volatile uint8_t  *)(addr))
-
-#define REG64(addr) (*REG64_ADDR(addr))
-#define REG32(addr) (*REG32_ADDR(addr))
-#define REG16(addr) (*REG16_ADDR(addr))
-#define REG8(addr)  (*REG8_ADDR(addr))
-
-/* Standard macros / definitions */
-#define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
-#define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
-#ifndef MAX
-#define MAX(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MAX(temp_a, temp_b);		\
-	})
-#endif
-#ifndef MIN
-#define MIN(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MIN(temp_a, temp_b);		\
-	})
-#endif
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-/******************************************************************************/
-/*
- * Macro Functions
- */
-/* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
-/* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
-/* Read field functions */
-#define GET_FIELD(reg, field) \
-	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
-/* Write field functions */
-#define SET_FIELD(reg, field, value) \
-	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
-
-
-/* NPCX7 & NPCX9 */
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
-
-/******************************************************************************/
-/*
- * NPCX (Nuvoton M4 EC) Register Definitions
- */
-
-/* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
-
-/* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
-
-
-/******************************************************************************/
-/* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
-
-/* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
-
-/* DEVALT */
-/* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
-
-/******************************************************************************/
-/* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
-
-/* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
-
-/******************************************************************************/
-/* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
-
-/* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
-
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
-
-/******************************************************************************/
-/* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
-
-/* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
-
-/******************************************************************************/
-/* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
-
-/* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
-
-/******************************************************************************/
-/* Flash Utiltiy definition */
-/*
- *  Flash commands for the W25Q16CV SPI flash
- */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
-
-/*
- * Status registers for the W25Q16CV SPI flash
- */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
-
-/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
-/* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
-
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/zephyr/shim/chip/npcx/power_policy.c b/zephyr/shim/chip/npcx/power_policy.c
deleted file mode 100644
index 803ac51e9b..0000000000
--- a/zephyr/shim/chip/npcx/power_policy.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <pm/pm.h>
-#include <soc.h>
-
-#include "console.h"
-#include "cros_version.h"
-#include "system.h"
-
-static const struct pm_state_info pm_min_residency[] =
-	PM_STATE_INFO_DT_ITEMS_LIST(DT_NODELABEL(cpu0));
-
-/* CROS PM policy handler */
-struct pm_state_info pm_policy_next_state(int32_t ticks)
-{
-	/* Deep sleep is allowed and console is not in use. */
-	if (DEEP_SLEEP_ALLOWED != 0 && !npcx_power_console_is_in_use()) {
-		for (int i = ARRAY_SIZE(pm_min_residency) - 1; i >= 0; i--) {
-			/* Find suitable power state by residency time */
-			if (ticks == K_TICKS_FOREVER ||
-			    ticks >= k_us_to_ticks_ceil32(
-					     pm_min_residency[i]
-						     .min_residency_us)) {
-				return pm_min_residency[i];
-			}
-		}
-	}
-
-	return (struct pm_state_info){ PM_STATE_ACTIVE, 0, 0 };
-}
diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c
deleted file mode 100644
index 22b153a806..0000000000
--- a/zephyr/shim/chip/npcx/shi.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by Serial Host Interface module for Chrome EC */
-
-#include <device.h>
-#include <dt-bindings/clock/npcx_clock.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <zephyr.h>
-
-#include "chipset.h"
-#include "drivers/cros_shi.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "system.h"
-
-LOG_MODULE_REGISTER(shim_cros_shi, LOG_LEVEL_DBG);
-
-#define SHI_NODE DT_NODELABEL(shi)
-
-static void shi_enable(void)
-{
-	const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE);
-
-	if (!device_is_ready(cros_shi_dev)) {
-		LOG_ERR("Error: device %s is not ready", cros_shi_dev->name);
-		return;
-	}
-
-	LOG_INF("%s", __func__);
-	cros_shi_enable(cros_shi_dev);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, shi_enable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT);
-#endif
-
-static void shi_reenable_on_sysjump(void)
-{
-	if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) ||
-	    (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))) {
-		shi_enable();
-	}
-}
-/* Call hook after chipset sets initial power state */
-DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_INIT_CHIPSET + 1);
-
-static void shi_disable(void)
-{
-	const struct device *cros_shi_dev = DEVICE_DT_GET(SHI_NODE);
-
-	if (!device_is_ready(cros_shi_dev)) {
-		LOG_ERR("Error: device %s is not ready", cros_shi_dev->name);
-		return;
-	}
-
-	LOG_INF("%s", __func__);
-	cros_shi_disable(cros_shi_dev);
-}
-#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, shi_disable, HOOK_PRIO_DEFAULT);
-#else
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT);
-#endif
-DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT);
-
-/* Get protocol information */
-static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, '\0', sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = CONFIG_CROS_SHI_MAX_REQUEST;
-	r->max_response_packet_size = CONFIG_CROS_SHI_MAX_RESPONSE;
-	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
-
-	args->response_size = sizeof(*r);
-
-	return EC_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
-		     EC_VER_MASK(0));
diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c
deleted file mode 100644
index 9809e138d5..0000000000
--- a/zephyr/shim/chip/npcx/system.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <drivers/bbram.h>
-#include <logging/log.h>
-
-#include "system.h"
-#include "system_chip.h"
-
-LOG_MODULE_REGISTER(shim_npcx_system, LOG_LEVEL_ERR);
-
-static void chip_bbram_status_check(void)
-{
-	const struct device *bbram_dev;
-	int res;
-
-	bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
-	if (!device_is_ready(bbram_dev)) {
-		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
-		return;
-	}
-
-	res = bbram_check_invalid(bbram_dev);
-	if (res != 0 && res != -ENOTSUP)
-		LOG_INF("VBAT power drop!");
-
-	res = bbram_check_standby_power(bbram_dev);
-	if (res != 0 && res != -ENOTSUP)
-		LOG_INF("VSBY power drop!");
-
-	res = bbram_check_power(bbram_dev);
-	if (res != 0 && res != -ENOTSUP)
-		LOG_INF("VCC1 power drop!");
-}
-
-/*
- * Configure address 0x40001600 (Low Power RAM) in the the MPU
- * (Memory Protection Unit) as a "regular" memory
- */
-void system_mpu_config(void)
-{
-	if (!IS_ENABLED(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API))
-		return;
-
-	/*
-	 * npcx9 Rev.1 has the problem for download_from_flash API.
-	 * Workaround it by implementing the system_download_from_flash function
-	 * in the suspend RAM. The functions will do the same, but will provide
-	 * a software solution similar to what's done in the npcx5.
-	 */
-	/* Enable MPU */
-	CPU_MPU_CTRL = 0x7;
-
-	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
-	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
-	/*
-	 * Set region size & attribute and enable region
-	 * [31:29] - Reserved.
-	 * [28]    - XN (Execute Never) = 0
-	 * [27]    - Reserved.
-	 * [26:24] - AP                 = 011 (Full access)
-	 * [23:22] - Reserved.
-	 * [21:19,18,17,16] - TEX,S,C,B = 001000 (Normal memory)
-	 * [15:8]  - SRD                = 0 (Subregions enabled)
-	 * [7:6]   - Reserved.
-	 * [5:1]   - SIZE               = 01001 (1K)
-	 * [0]     - ENABLE             = 1 (enabled)
-	 */
-	CPU_MPU_RASR = 0x03080013;
-}
-
-static int chip_system_init(const struct device *unused)
-{
-	ARG_UNUSED(unused);
-
-	/*
-	 * Check BBRAM power status.
-	 */
-	chip_bbram_status_check();
-
-	system_mpu_config();
-
-	return 0;
-}
-/*
- * The priority should be lower than CROS_BBRAM_NPCX_INIT_PRIORITY.
- */
-#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY)
-#error CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must greater than \
-	CONFIG_BBRAM_INIT_PRIORITY
-#endif
-SYS_INIT(chip_system_init, PRE_KERNEL_1,
-	 CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c
deleted file mode 100644
index 28ec22962c..0000000000
--- a/zephyr/shim/chip/npcx/system_download_from_flash.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <dt-bindings/clock/npcx_clock.h>
-#include <stdnoreturn.h>
-#include <sys/__assert.h>
-
-#include "common.h"
-#include "soc.h"
-#include "system_chip.h"
-
-/* Modules Map */
-#define NPCX_PMC_BASE_ADDR	0x4000D000
-#define NPCX_GDMA_BASE_ADDR	0x40011000
-
-/******************************************************************************/
-/* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL		REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB		REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB		REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT		REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
-
-/******************************************************************************/
-/* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
-
-/******************************************************************************/
-/* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL		REG32(0x40001044)
-
-/******************************************************************************/
-/* Sysjump utilities in low power ram for npcx series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
-__start_gdma(uint32_t exeAddr)
-{
-	/* Enable GDMA now */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/* Start GDMA */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
-
-	/* Wait for transfer to complete/fail */
-	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		;
-
-	/* Disable GDMA now */
-	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
-
-	/*
-	 * Failure occurs during GMDA transaction. Let watchdog issue and
-	 * boot from RO region again.
-	 */
-	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
-		while (1)
-			;
-
-	/*
-	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
-	 * indicate it's a thumb branch for cortex-m series CPU.
-	 */
-	((void (*)(void))(exeAddr | 0x01))();
-
-	/* Should never get here */
-	while (1)
-		;
-}
-
-/* Begin address of Suspend RAM for little FW (GDMA utilities). */
-#define LFW_OFFSET		0x160
-uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
-
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
-{
-	int i;
-	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
-	/*
-	 * GDMA utility in Suspend RAM. Setting bit 0 of address to indicate
-	 * it's a thumb branch for cortex-m series CPU.
-	 */
-	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
-
-	/*
-	 * Before enabling burst mode for better performance of GDMA, it's
-	 * important to make sure srcAddr, dstAddr and size of transactions
-	 * are 16 bytes aligned in case failure occurs.
-	 */
-	__ASSERT_NO_MSG((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
-
-	/* Check valid address for jumpiing */
-	__ASSERT_NO_MSG(exeAddr != 0x0);
-
-	/* Enable power for the Low Power RAM */
-	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_BASE_ADDR, NPCX_PWDWN_CTL6), 6);
-
-	/* Enable Low Power RAM */
-	NPCX_LPRAM_CTRL = 1;
-
-	/*
-	 * Initialize GDMA for flash reading.
-	 * [31:21] - Reserved.
-	 * [20]    - GDMAERR   = 0  (Indicate GMDA transfer error)
-	 * [19]    - Reserved.
-	 * [18]    - TC        = 0  (Terminal Count. Indicate operation is end.)
-	 * [17]    - Reserved.
-	 * [16]    - SOFTREQ   = 0  (Don't trigger here)
-	 * [15]    - DM        = 0  (Set normal demand mode)
-	 * [14]    - Reserved.
-	 * [13:12] - TWS.      = 10 (One double-word for every GDMA transaction)
-	 * [11:10] - Reserved.
-	 * [9]     - BME       = 1  (4-data ie.16 bytes - Burst mode enable)
-	 * [8]     - SIEN      = 0  (Stop interrupt disable)
-	 * [7]     - SAFIX     = 0  (Fixed source address)
-	 * [6]     - Reserved.
-	 * [5]     - SADIR     = 0  (Source address incremented)
-	 * [4]     - DADIR     = 0  (Destination address incremented)
-	 * [3:2]   - GDMAMS    = 00 (Software mode)
-	 * [1]     - Reserved.
-	 * [0]     - ENABLE    = 0  (Don't enable yet)
-	 */
-	NPCX_GDMA_CTL = 0x00002200;
-
-	/* Set source base address */
-	NPCX_GDMA_SRCB = CONFIG_MAPPED_STORAGE_BASE + srcAddr;
-
-	/* Set destination base address */
-	NPCX_GDMA_DSTB = dstAddr;
-
-	/* Set number of transfers */
-	NPCX_GDMA_TCNT = (size / chunkSize);
-
-	/* Clear Transfer Complete event */
-	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC);
-
-	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
-	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
-		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
-
-	/* Start GDMA in Suspend RAM */
-	__start_gdma_in_lpram(exeAddr);
-}
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c
deleted file mode 100644
index 373a4a48f7..0000000000
--- a/zephyr/shim/chip/npcx/system_external_storage.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <devicetree.h>
-#include <drivers/syscon.h>
-
-#include "clock_chip.h"
-#include "common.h"
-#include "rom_chip.h"
-#include "system.h"
-#include "system_chip.h"
-
-/* TODO (b:179900857) Make this implementation not npcx specific. */
-
-static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc));
-
-#ifdef CONFIG_SOC_SERIES_NPCX7
-#define NPCX_FWCTRL                       0x007
-#define NPCX_FWCTRL_RO_REGION             0
-#define NPCX_FWCTRL_FW_SLOT               1
-#elif defined(CONFIG_SOC_SERIES_NPCX9)
-#define NPCX_FWCTRL                       0x009
-#define NPCX_FWCTRL_RO_REGION             6
-#define NPCX_FWCTRL_FW_SLOT               7
-#else
-#error "Unsupported NPCX SoC series."
-#endif
-
-void system_jump_to_booter(void)
-{
-	enum API_RETURN_STATUS_T status __attribute__((unused));
-	static uint32_t flash_offset;
-	static uint32_t flash_used;
-	static uint32_t addr_entry;
-
-	/*
-	 * Get memory offset and size for RO/RW regions.
-	 * Both of them need 16-bytes alignment since GDMA burst mode.
-	 */
-	switch (system_get_shrspi_image_copy()) {
-	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
-		flash_used = CONFIG_RW_SIZE;
-		break;
-#endif
-	case EC_IMAGE_RO:
-	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
-		flash_used = CONFIG_RO_SIZE;
-		break;
-	}
-
-	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
-
-	/*
-	 * Speed up FW download time by increasing clock freq of EC. It will
-	 * restore to default in clock_init() later.
-	 */
-	clock_turbo();
-
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
-	/* Bypass for GMDA issue of ROM api utilities */
-#if defined(CONFIG_SOC_SERIES_NPCX5) || \
-	defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
-	);
-#else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
-	);
-#endif
-}
-
-uint32_t system_get_lfw_address()
-{
-	/*
-	 * In A3 version, we don't use little FW anymore
-	 * We provide the alternative function in ROM
-	 */
-	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
-	return jump_addr;
-}
-
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	uint32_t fwctrl = 0;
-
-	syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl);
-	if (IS_BIT_SET(fwctrl, NPCX_FWCTRL_RO_REGION)) {
-		/* RO image */
-#ifdef CHIP_HAS_RO_B
-		if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT))
-			return EC_IMAGE_RO_B;
-#endif
-		return EC_IMAGE_RO;
-	} else {
-#ifdef CONFIG_RW_B
-		/* RW image */
-		if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT))
-			/* Slot A */
-			return EC_IMAGE_RW_B;
-#endif
-		return EC_IMAGE_RW;
-	}
-}
-
-void system_set_image_copy(enum ec_image copy)
-{
-	uint32_t fwctrl = 0;
-
-	syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl);
-	switch (copy) {
-	case EC_IMAGE_RW:
-		CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
-		break;
-#ifdef CONFIG_RW_B
-	case EC_IMAGE_RW_B:
-		CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
-		CLEAR_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
-		break;
-#endif
-	default:
-		/* Fall through to EC_IMAGE_RO */
-	case EC_IMAGE_RO:
-		SET_BIT(fwctrl, NPCX_FWCTRL_RO_REGION);
-		SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT);
-		break;
-	}
-	syscon_write_reg(mdc_dev, NPCX_FWCTRL, fwctrl);
-}
diff --git a/zephyr/shim/chip/posix/CMakeLists.txt b/zephyr/shim/chip/posix/CMakeLists.txt
deleted file mode 100644
index 70e8b6269a..0000000000
--- a/zephyr/shim/chip/posix/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI  espi.c)
\ No newline at end of file
diff --git a/zephyr/shim/chip/posix/espi.c b/zephyr/shim/chip/posix/espi.c
deleted file mode 100644
index cf348744d7..0000000000
--- a/zephyr/shim/chip/posix/espi.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <sys/util.h>
-#include "zephyr_espi_shim.h"
-
-#define ACPI_TYPE_POS 0U
-#define ACPI_DATA_POS 8U
-
-/* 8042 event data format */
-#define POSIX_8042_EVT_POS 16U
-#define POSIX_8042_DATA_POS 8U
-#define POSIX_8042_TYPE_POS 0U
-
-/* 8042 event type format */
-#define POSIX_8042_EVT_IBF BIT(0)
-#define POSIX_8042_EVT_OBE BIT(1)
-
-bool is_acpi_command(uint32_t data)
-{
-	return (data >> ACPI_TYPE_POS) & 0x01;
-}
-
-uint32_t get_acpi_value(uint32_t data)
-{
-	return (data >> ACPI_TYPE_POS) & 0xff;
-}
-
-bool is_POSIX_8042_ibf(uint32_t data)
-{
-	return (data >> POSIX_8042_EVT_POS) & POSIX_8042_EVT_IBF;
-}
-
-bool is_POSIX_8042_obe(uint32_t data)
-{
-	return (data >> POSIX_8042_EVT_POS) & POSIX_8042_EVT_OBE;
-}
-
-uint32_t get_POSIX_8042_type(uint32_t data)
-{
-	return (data >> POSIX_8042_TYPE_POS) & 0xFF;
-}
-
-uint32_t get_POSIX_8042_data(uint32_t data)
-{
-	return (data >> POSIX_8042_DATA_POS) & 0xFF;
-}
diff --git a/zephyr/shim/core/CMakeLists.txt b/zephyr/shim/core/CMakeLists.txt
deleted file mode 100644
index e1b13f21f4..0000000000
--- a/zephyr/shim/core/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if (DEFINED CONFIG_CPU_CORTEX_M)
-    add_subdirectory(cortex-m)
-endif()
diff --git a/zephyr/shim/core/cortex-m/CMakeLists.txt b/zephyr/shim/core/cortex-m/CMakeLists.txt
deleted file mode 100644
index 01e5673f9e..0000000000
--- a/zephyr/shim/core/cortex-m/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MPU mpu.c)
diff --git a/zephyr/shim/core/cortex-m/mpu.c b/zephyr/shim/core/cortex-m/mpu.c
deleted file mode 100644
index 24d7948143..0000000000
--- a/zephyr/shim/core/cortex-m/mpu.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "mpu.h"
-#include "logging/log.h"
-#include <arch/arm/aarch32/cortex_m/cmsis.h>
-#include <arch/cpu.h>
-#include <init.h>
-
-LOG_MODULE_REGISTER(shim_mpu, LOG_LEVEL_ERR);
-
-void mpu_enable(void)
-{
-	for (int index = 0; index < mpu_config.num_regions; index++) {
-		MPU->RNR = index;
-		MPU->RASR |= MPU_RASR_ENABLE_Msk;
-		LOG_DBG("[%d] %08x %08x", index, MPU->RBAR, MPU->RASR);
-	}
-}
-
-static int mpu_disable_fixed_regions(const struct device *dev)
-{
-	/* MPU is configured and enabled by the Zephyr init code, disable the
-	 * fixed sections by default.
-	 */
-	for (int index = 0; index < mpu_config.num_regions; index++) {
-		MPU->RNR = index;
-		MPU->RASR &= ~MPU_RASR_ENABLE_Msk;
-		LOG_DBG("[%d] %08x %08x", index, MPU->RBAR, MPU->RASR);
-	}
-
-	return 0;
-}
-
-SYS_INIT(mpu_disable_fixed_regions, PRE_KERNEL_1, 50);
diff --git a/zephyr/shim/include/adc_chip.h b/zephyr/shim/include/adc_chip.h
deleted file mode 100644
index c51cdfbb30..0000000000
--- a/zephyr/shim/include/adc_chip.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This file is left intentionally blank. It is required since the
- * platform/ec/common/adc.c file includes it. Normally, this file
- * would define chip specific ADC configs and would reside under
- * platform/ec/chip/...
- */
-
-#ifndef __CROS_EC_ADC_CHIP_H
-#define __CROS_EC_ADC_CHIP_H
-
-#endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/zephyr/shim/include/atomic.h b/zephyr/shim/include/atomic.h
deleted file mode 100644
index ad534d116b..0000000000
--- a/zephyr/shim/include/atomic.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ATOMIC_H
-#define __CROS_EC_ATOMIC_H
-
-#include <sys/atomic.h>
-
-static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
-{
-	return atomic_and(addr, ~bits);
-}
-
-#endif  /* __CROS_EC_ATOMIC_H */
diff --git a/zephyr/shim/include/battery_enum.h b/zephyr/shim/include/battery_enum.h
deleted file mode 100644
index a461829a31..0000000000
--- a/zephyr/shim/include/battery_enum.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#error "This file must only be included from config_chip.h and it should be" \
-	"included in all zephyr builds automatically"
-#endif
-
-#define BATTERY_ENUM(val)	DT_CAT(BATTERY_, val)
-#define BATTERY_TYPE(id) BATTERY_ENUM(DT_STRING_UPPER_TOKEN(id, enum_name))
-#define BATTERY_TYPE_WITH_COMMA(id)	BATTERY_TYPE(id),
-
-/* This produces a list of BATTERY_<ENUM_NAME> identifiers */
-#if DT_NODE_EXISTS(DT_PATH(batteries))
-
-enum battery_type {
-	DT_FOREACH_CHILD(DT_PATH(batteries), BATTERY_TYPE_WITH_COMMA)
-
-	BATTERY_TYPE_COUNT,
-};
-
-#else /* DT_NODE_EXISTS(DT_PATH(batteries)) */
-
-enum battery_type {
-#if DT_NODE_EXISTS(DT_PATH(named_batteries))
-	DT_FOREACH_CHILD(DT_PATH(named_batteries), BATTERY_TYPE_WITH_COMMA)
-#endif
-
-	BATTERY_TYPE_COUNT,
-};
-
-#endif /* DT_NODE_EXISTS(DT_PATH(batteries)) */
-
-#undef BATTERY_TYPE_WITH_COMMA
diff --git a/zephyr/shim/include/bbram.h b/zephyr/shim/include/bbram.h
deleted file mode 100644
index 3eba4b157b..0000000000
--- a/zephyr/shim/include/bbram.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_SHIM_INCLUDE_BBRAM_H_
-#define ZEPHYR_SHIM_INCLUDE_BBRAM_H_
-
-#include <devicetree.h>
-
-#define BBRAM_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(bbram), memory)
-#define BBRAM_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(bbram), memory)
-#define BBRAM(offset) REG8(BBRAM_ADDR + offset)
-#define BBRAM_BKUP_STS BBRAM(CONFIG_BBRAM_BKUP_STS)
-
-#endif /* ZEPHYR_SHIM_INCLUDE_BBRAM_H_ */
diff --git a/zephyr/shim/include/board.h b/zephyr/shim/include/board.h
deleted file mode 100644
index df3ef33c0e..0000000000
--- a/zephyr/shim/include/board.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_H
-#define __BOARD_H
-
-#include <devicetree.h>
-
-/* Included shimed version of gpio signal. */
-#include "gpio_signal.h"
-
-/* Include board specific gpio mapping/aliases if named_pgios node exists */
-#if DT_NODE_EXISTS(DT_PATH(named_gpios))
-#include "gpio_map.h"
-#endif
-
-/* Include board specific i2c mapping if I2C is enabled. */
-#if defined(CONFIG_I2C)
-#include "i2c/i2c.h"
-#endif
-
-#ifdef CONFIG_PWM
-#include "pwm_map.h"
-#endif
-
-/* Include board specific sensor configuration if motionsense is enabled */
-#ifdef CONFIG_MOTIONSENSE
-#include "motionsense_sensors.h"
-#endif
-
-#endif  /* __BOARD_H */
diff --git a/zephyr/shim/include/builtin/assert.h b/zephyr/shim/include/builtin/assert.h
deleted file mode 100644
index 21a6c5b3d7..0000000000
--- a/zephyr/shim/include/builtin/assert.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ASSERT_H
-#define __CROS_EC_ASSERT_H
-
-#include <sys/__assert.h>
-
-#undef ASSERT
-#undef assert
-#define ASSERT __ASSERT_NO_MSG
-#define assert __ASSERT_NO_MSG
-
-#endif /* __CROS_EC_ASSERT_H */
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
deleted file mode 100644
index 04d2ca1d5d..0000000000
--- a/zephyr/shim/include/config_chip.h
+++ /dev/null
@@ -1,1811 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include <devicetree.h>
-#include <autoconf.h>
-
-/*
- * The battery enum is used in various drivers and these assume that it is
- * always available (defined in board.h). With Zephyr we don't include board.h
- * so we have a battery_enum.h header in the shim which defines
- * enum battery_type based on settings in the device tree. Include that here.
- */
-#ifdef CONFIG_PLATFORM_EC_BATTERY
-#include "battery_enum.h"
-#endif
-
-/*
- * This file translates Kconfig options to platform/ec options.
- *
- * Options which are from Zephyr platform/ec module (Kconfig) start
- * with CONFIG_PLATFORM_EC_, and can be found in the Kconfig file.
- *
- * Options which are for the platform/ec configuration can be found in
- * common/config.h.
- */
-
-/*
- * Obsolete configs - these are options that are not needed, either because
- * Zephyr features directly replace the option, or because the config option
- * will not be used with Zephyr OS.
- */
-
-/*
- * ROM resident support. The ROM resident capabilities in the Chromium OS
- * code are used with EC chipsets that provide more flash space than
- * executable RAM. These options allow storing the initialized data into
- * an unused area of flash where it is copied directly from flash into data
- * RAM by the early boot code.
- *
- * When ROM resident is disabled, the initialized data is stored in the main
- * image, copied from flash to executable RAM by the chip boot loader, and
- * then copied from executable RAM to data RAM by the early boot code.
- *
- * Supporting this under Zephyr would require linker changes to the common
- * Zephyr linking.
- */
-#undef CONFIG_CHIP_DATA_IN_INIT_ROM
-#undef CONFIG_CHIP_INIT_ROM_REGION
-#undef CONFIG_RO_ROM_RESIDENT_MEM_OFF
-#undef CONFIG_RO_ROM_RESIDENT_SIZE
-#undef CONFIG_RW_ROM_RESIDENT_MEM_OFF
-#undef CONFIG_RW_ROM_RESIDENT_SIZE
-
-/*
- * ECOS specific options, not used in Zephyr.
- */
-#undef CONFIG_CONSOLE_UART /* Only used by the Chromium EC chip drivers */
-#undef CONFIG_I2C_MULTI_PORT_CONTROLLER /* Not required by I2C shim */
-#undef CONFIG_IRQ_COUNT /* Only used by Chromium EC core drivers */
-#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers */
-#undef CONFIG_LTO /* Link time optimization enabled by Zephyr build system */
-#undef CONFIG_STACK_SIZE /* Only used in Chromium EC core init code */
-#ifndef CONFIG_FPU
-#undef CONFIG_FPU /* Used in Zephyr as well, enabled in Kconfig directly */
-#endif
-#ifndef CONFIG_WATCHDOG
-#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly */
-#endif
-
-/*
- * The Zephyr I2C shell command provides the same functionality as the Chromium
- * EC i2cscan and i2cxfer commands, so they are always disabled.
- */
-#undef CONFIG_CMD_I2C_SCAN
-#undef CONFIG_CMD_I2C_XFER
-
-/*
- * This not used by the Zephyr code since we always make cros_crc8() available.
- * Define it here to reduce the delta from the ECOS CONFIG.
- */
-#undef CONFIG_CRC8
-#define CONFIG_CRC8
-
-/*
- * This is not used by the Zephyr code.
- * Define it here to reduce the delta from the ECOS CONFIG.
- */
-#undef CONFIG_CHIP_PRE_INIT
-#define CONFIG_CHIP_PRE_INIT
-
-#undef CONFIG_BC12_SINGLE_DRIVER
-#ifdef CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER
-#define CONFIG_BC12_SINGLE_DRIVER
-#endif
-
-#undef CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_CHARGER_SINGLE_CHIP
-
-/* EC chipset configuration */
-#define HOOK_TICK_INTERVAL	CONFIG_CROS_EC_HOOK_TICK_INTERVAL
-#define HOOK_TICK_INTERVAL_MS	(HOOK_TICK_INTERVAL / 1000)
-
-/* Chipset and power configuration */
-#ifdef CONFIG_AP_ARM_QUALCOMM_SC7180
-#define CONFIG_CHIPSET_SC7180
-#endif
-
-#ifdef CONFIG_AP_ARM_QUALCOMM_SC7280
-#define CONFIG_CHIPSET_SC7280
-#endif
-
-#ifdef CONFIG_AP_X86_INTEL_CML
-#define CONFIG_CHIPSET_COMETLAKE
-#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
-#endif
-
-#ifdef CONFIG_AP_X86_INTEL_TGL
-#define CONFIG_CHIPSET_TIGERLAKE
-#endif
-
-#undef CONFIG_THROTTLE_AP
-#ifdef CONFIG_PLATFORM_EC_THROTTLE_AP
-#define CONFIG_THROTTLE_AP
-#endif
-
-#undef CONFIG_CHIPSET_CAN_THROTTLE
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#endif
-
-#undef CONFIG_CMD_APTHROTTLE
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_APTHROTTLE
-#define CONFIG_CMD_APTHROTTLE
-#endif
-
-#undef CONFIG_BACKLIGHT_LID
-#ifdef CONFIG_PLATFORM_EC_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID
-#endif
-
-/* Battery configuration */
-#undef CONFIG_BATTERY
-#undef CONFIG_BATTERY_FUEL_GAUGE
-#ifdef CONFIG_PLATFORM_EC_BATTERY
-#define CONFIG_BATTERY
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-#endif /* CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE */
-
-#undef CONFIG_BATTERY_SMART
-#ifdef CONFIG_PLATFORM_EC_BATTERY_SMART
-#define CONFIG_BATTERY_SMART
-#endif
-
-#undef CONFIG_I2C_VIRTUAL_BATTERY
-#undef I2C_PORT_VIRTUAL_BATTERY
-#ifdef CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY
-#define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#endif
-
-#undef CONFIG_I2C_PASSTHRU_RESTRICTED
-#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
-#define CONFIG_I2C_PASSTHRU_RESTRICTED
-#endif
-
-#undef CONFIG_CMD_I2C_SPEED
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED
-#define CONFIG_CMD_I2C_SPEED
-#endif
-
-#undef CONFIG_BATTERY_PRESENT_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#endif
-
-#undef CONFIG_BATTERY_PRESENT_GPIO
-#ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO
-/* This is always GPIO_BATT_PRES_ODL with Zephyr */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BATT_PRES_ODL
-#endif
-
-#undef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-#ifdef CONFIG_PLATFORM_EC_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
-#endif
-
-#undef CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-#ifdef CONFIG_PLATFORM_EC_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-#define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
-#endif
-
-#undef CONFIG_BATTERY_CUT_OFF
-#ifdef CONFIG_PLATFORM_EC_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_CUT_OFF
-#endif
-
-#undef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#endif
-
-#undef CONFIG_BATTERY_REVIVE_DISCONNECT
-#ifdef CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#endif
-
-#undef CONFIG_BATTERY_MEASURE_IMBALANCE
-#ifdef CONFIG_PLATFORM_EC_BATTERY_MEASURE_IMBALANCE
-
-#define CONFIG_BATTERY_MEASURE_IMBALANCE
-#define CONFIG_BATTERY_MAX_IMBALANCE_MV \
-	CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV
-#define CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON \
-	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
-
-#endif
-
-#undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
-#if defined(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) && \
-    (CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0)
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV \
-    CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
-#endif
-
-#undef CONFIG_BOARD_RESET_AFTER_POWER_ON
-#ifdef CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-#endif
-
-#undef CONFIG_CHARGER_ISL9241
-#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9241
-#define CONFIG_CHARGER_ISL9241
-#endif
-
-/*
- * Note - ISL9241 chargers for all channels are configured with the same
- * switching frequency. Use the first ISL9241 instance found in the device tree.
- */
-#undef CONFIG_ISL9241_SWITCHING_FREQ
-#define ISL9241_NODE	DT_INST(0, intersil_isl9241)
-#if DT_NODE_EXISTS(ISL9241_NODE) && \
-	DT_NODE_HAS_PROP(ISL9241_NODE, switching_frequency)
-#define CONFIG_ISL9241_SWITCHING_FREQ \
-	DT_PROP(ISL9241_NODE, switching_frequency)
-#endif
-
-#undef CONFIG_CHARGER_ISL9237
-#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9237
-#define CONFIG_CHARGER_ISL9237
-#endif
-
-#undef CONFIG_CHARGER_ISL9238
-#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9238
-#define CONFIG_CHARGER_ISL9238
-#endif
-
-#undef CONFIG_CHARGER_ISL9238C
-#ifdef CONFIG_PLATFORM_EC_CHARGER_ISL9238C
-#define CONFIG_CHARGER_ISL9238C
-#endif
-
-#undef CONFIG_CHARGER_MAINTAIN_VBAT
-#ifdef CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT
-#define CONFIG_CHARGER_MAINTAIN_VBAT
-#endif
-
-#undef CONFIG_CHARGER_NARROW_VDC
-#ifdef CONFIG_PLATFORM_EC_CHARGER_NARROW_VDC
-#define CONFIG_CHARGER_NARROW_VDC
-#endif
-
-#undef CONFIG_CHARGER_OTG
-#ifdef CONFIG_PLATFORM_EC_CHARGER_OTG
-#define CONFIG_CHARGER_OTG
-#endif
-
-#undef CONFIG_CHIPSET_RESET_HOOK
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
-#define CONFIG_CHIPSET_RESET_HOOK
-#endif
-
-#undef CONFIG_CHIPSET_RESUME_INIT_HOOK
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
-#define CONFIG_CHIPSET_RESUME_INIT_HOOK
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_EXTPOWER_GPIO
-#define CONFIG_EXTPOWER_GPIO
-
-/* This always needs to be defined for this option to work */
-#define CONFIG_EXTPOWER
-#endif
-
-/* Bringup configuration */
-#ifdef CONFIG_PLATFORM_EC_BRINGUP
-#define CONFIG_BRINGUP
-#endif
-
-#undef CONFIG_EMULATED_SYSRQ
-#ifdef CONFIG_PLATFORM_EC_EMULATED_SYSRQ
-#define CONFIG_EMULATED_SYSRQ
-#endif
-
-/* eSPI configuration */
-#ifdef CONFIG_PLATFORM_EC_ESPI
-
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD
-#define CONFIG_HOSTCMD_ESPI
-#endif
-
-/* eSPI signals */
-#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-#endif
-
-#endif /* CONFIG_PLATFORM_EC_ESPI */
-
-#if DT_NODE_EXISTS(DT_NODELABEL(flash0))
-#define CONFIG_PROGRAM_MEMORY_BASE DT_REG_ADDR(DT_NODELABEL(flash0))
-#else
-#define CONFIG_PROGRAM_MEMORY_BASE 0X0
-#endif
-
-#if DT_NODE_EXISTS(DT_NODELABEL(sram0))
-#define CONFIG_RAM_BASE DT_REG_ADDR(DT_NODELABEL(sram0))
-#define CONFIG_DATA_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
-#else
-#define CONFIG_RAM_BASE 0x0
-#define CONFIG_DATA_RAM_SIZE 0x0
-#endif
-
-#define CONFIG_RO_MEM_OFF CONFIG_CROS_EC_RO_MEM_OFF
-#define CONFIG_RO_MEM_SIZE CONFIG_CROS_EC_RO_MEM_SIZE
-#define CONFIG_RW_MEM_OFF CONFIG_CROS_EC_RW_MEM_OFF
-#define CONFIG_RW_MEM_SIZE CONFIG_CROS_EC_RW_MEM_SIZE
-
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
-#define CONFIG_RO_SIZE		CONFIG_CROS_EC_RO_SIZE
-#define CONFIG_RW_SIZE		CONFIG_CROS_EC_RW_SIZE
-
-/* Flash settings */
-#undef CONFIG_EXTERNAL_STORAGE
-#undef CONFIG_INTERNAL_STORAGE
-#undef CONFIG_MAPPED_STORAGE
-#undef CONFIG_FLASH_PSTATE
-#undef CONFIG_FLASH_SIZE_BYTES
-#ifdef CONFIG_PLATFORM_EC_FLASH_CROS
-#include "flash_chip.h"
-#define CONFIG_FLASH_CROS
-
-/* Internal, don't use outside this header */
-#define _BINMAN_RO_PATH DT_PATH(binman, wp_ro)
-#define _BINMAN_RW_PATH DT_PATH(binman, ec_rw)
-
-#define CONFIG_EC_PROTECTED_STORAGE_OFF DT_PROP(_BINMAN_RO_PATH, offset)
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE DT_PROP(_BINMAN_RO_PATH, size)
-#define CONFIG_EC_WRITABLE_STORAGE_OFF DT_PROP(_BINMAN_RW_PATH, offset)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE DT_PROP(_BINMAN_RW_PATH, size)
-
-#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
-
-#ifdef CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
-#define CONFIG_EXTERNAL_STORAGE
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_INTERNAL_STORAGE
-#define CONFIG_INTERNAL_STORAGE
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_MAPPED_STORAGE
-#define CONFIG_MAPPED_STORAGE
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_FLASH_PSTATE
-#define CONFIG_FLASH_PSTATE
-#endif
-
-#undef CONFIG_CMD_FLASH
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH
-#define CONFIG_CMD_FLASH
-#endif
-
-#undef CONFIG_CMD_FLASHINFO
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASHINFO
-#define CONFIG_CMD_FLASHINFO
-#endif
-
-#undef CONFIG_CMD_FLASH_WP
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH_WP
-#define CONFIG_CMD_FLASH_WP
-#endif
-
-#endif /* CONFIG_PLATFORM_EC_FLASH_CROS */
-
-#undef CONFIG_ADC
-#ifdef CONFIG_PLATFORM_EC_ADC
-#define CONFIG_ADC
-#endif
-
-#undef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-#ifdef CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
-#define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-#endif
-
-#undef CONFIG_CMD_ADC
-#ifdef CONFIG_PLATFORM_EC_ADC_CMD
-#define CONFIG_CMD_ADC
-#endif
-
-#undef CONFIG_TEMP_SENSOR
-#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR
-#endif
-
-#undef CONFIG_THERMISTOR
-#ifdef CONFIG_PLATFORM_EC_THERMISTOR
-#define CONFIG_THERMISTOR
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_I2C
-/* Also see shim/include/i2c/i2c.h which defines the ports enum */
-#define CONFIG_I2C_CONTROLLER
-#endif
-
-#undef CONFIG_I2C_DEBUG
-#ifdef CONFIG_PLATFORM_EC_I2C_DEBUG
-#define CONFIG_I2C_DEBUG
-#endif
-
-#undef CONFIG_I2C_DEBUG_PASSTHRU
-#ifdef CONFIG_PLATFORM_EC_I2C_DEBUG_PASSTHRU
-#define CONFIG_I2C_DEBUG_PASSTHRU
-#endif
-
-#undef CONFIG_SMBUS_PEC
-#ifdef CONFIG_PLATFORM_EC_SMBUS_PEC
-#define CONFIG_SMBUS_PEC
-#endif
-
-#undef CONFIG_KEYBOARD_PROTOCOL_8042
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#endif /* CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042 */
-
-#undef CONFIG_KEYBOARD_PROTOCOL_MKBP
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP
-#endif
-
-#undef CONFIG_MKBP_INPUT_DEVICES
-#ifdef CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES
-#define CONFIG_MKBP_INPUT_DEVICES
-#endif
-
-#undef CONFIG_MKBP_EVENT_WAKEUP_MASK
-#if defined(CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK) && \
-			DT_NODE_EXISTS(DT_PATH(ec_mkbp_event_wakeup_mask))
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		DT_PROP(DT_PATH(ec_mkbp_event_wakeup_mask), wakeup_mask)
-#endif
-
-#undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
-#if defined(CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK) && \
-			DT_NODE_EXISTS(DT_PATH(ec_mkbp_host_event_wakeup_mask))
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		DT_PROP(DT_PATH(ec_mkbp_host_event_wakeup_mask), wakeup_mask)
-#endif
-
-#undef CONFIG_CMD_KEYBOARD
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_KEYBOARD
-#define CONFIG_CMD_KEYBOARD
-#endif
-
-#undef CONFIG_KEYBOARD_COL2_INVERTED
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#endif  /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
-
-#undef CONFIG_KEYBOARD_REFRESH_ROW3
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3
-#define CONFIG_KEYBOARD_REFRESH_ROW3
-#endif  /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */
-
-#undef CONFIG_KEYBOARD_KEYPAD
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD
-#define CONFIG_KEYBOARD_KEYPAD
-#endif
-
-#undef CONFIG_KEYBOARD_VIVALDI
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_VIVALDI
-#define CONFIG_KEYBOARD_VIVALDI
-#endif
-
-#undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#endif
-
-#undef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
-#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3
-#endif
-
-#undef CONFIG_VOLUME_BUTTONS
-#ifdef CONFIG_PLATFORM_EC_VOLUME_BUTTONS
-#define CONFIG_VOLUME_BUTTONS
-#endif
-
-#undef CONFIG_CMD_BUTTON
-#ifdef CONFIG_PLATFORM_EC_CMD_BUTTON
-#define CONFIG_CMD_BUTTON
-#endif
-
-#undef CONFIG_PWM_KBLIGHT
-#undef CONFIG_KEYBOARD_BACKLIGHT
-#ifdef CONFIG_PLATFORM_EC_PWM_KBLIGHT
-#define CONFIG_PWM_KBLIGHT
-#define CONFIG_KEYBOARD_BACKLIGHT
-#endif
-
-#undef CONFIG_LED_COMMON
-#ifdef CONFIG_PLATFORM_EC_LED_COMMON
-#define CONFIG_LED_COMMON
-#endif
-
-#undef CONFIG_LED_PWM
-#ifdef CONFIG_PLATFORM_EC_LED_PWM
-#define CONFIG_LED_PWM
-#endif
-
-#undef CONFIG_LED_PWM_COUNT
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_pwm_leds)
-#define CONFIG_LED_PWM_COUNT DT_PROP_LEN(DT_INST(0, cros_ec_pwm_leds), leds)
-#endif
-
-#undef CONFIG_CMD_LEDTEST
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST
-#define CONFIG_CMD_LEDTEST
-#endif
-
-#undef CONFIG_PWM_DISPLIGHT
-#ifdef CONFIG_PLATFORM_EC_PWM_DISPLIGHT
-#define CONFIG_PWM_DISPLIGHT
-#endif
-
-#undef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#endif
-
-#undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#endif
-
-#undef CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#ifdef CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#endif
-
-#undef CONFIG_HOSTCMD_AP_RESET
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET
-#define CONFIG_HOSTCMD_AP_RESET
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY
-#define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
-#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
-#define CONFIG_CHIPSET_PP3300_RAIL_FIRST
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET
-#define CONFIG_BOARD_HAS_RTC_RESET
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL
-#define CONFIG_POWER_PP5000_CONTROL
-#endif
-
-#undef CONFIG_POWER_S0IX
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX
-#define CONFIG_POWER_S0IX
-#endif
-
-#undef CONFIG_POWER_BUTTON_X86
-#ifdef CONFIG_PLATFORM_EC_POWERSEQ_INTEL
-#define CONFIG_POWER_BUTTON_X86
-#endif
-
-#undef CONFIG_FAKE_SHMEM
-#ifdef CONFIG_ARCH_POSIX
-#define CONFIG_FAKE_SHMEM
-#endif
-
-#undef CONFIG_PWM
-#ifdef CONFIG_PLATFORM_EC_PWM
-#define CONFIG_PWM
-#endif
-
-#undef CONFIG_CMD_S5_TIMEOUT
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
-#define CONFIG_CMD_S5_TIMEOUT
-#endif
-
-#undef CONFIG_CMD_SHMEM
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SHMEM
-#define CONFIG_CMD_SHMEM
-#endif
-
-#undef CONFIG_CROS_FWID_VERSION
-#ifdef CONFIG_PLATFORM_EC_CROS_FWID_VERSION
-#define CONFIG_CROS_FWID_VERSION
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_TIMER
-#define CONFIG_HWTIMER_64BIT
-#define CONFIG_HW_SPECIFIC_UDELAY
-
-#undef CONFIG_CMD_GETTIME
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME
-#define CONFIG_CMD_GETTIME
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */
-
-#undef CONFIG_CMD_TIMERINFO
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO
-#define CONFIG_CMD_TIMERINFO
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
-
-#undef CONFIG_CMD_WAITMS
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS
-#define CONFIG_CMD_WAITMS
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
-
-#endif  /* CONFIG_PLATFORM_EC_TIMER */
-
-/* USB-C things */
-#ifdef CONFIG_PLATFORM_EC_USBC
-
-/* Zephyr only supports v2 so we always define this */
-#define CONFIG_USB_PD_TCPMV2
-
-/*
- * Define these here for now. They are not actually CONFIG options in the EC
- * code base. Ideally they would be defined in the devicetree (perhaps for a
- * 'board' driver if not in the USB chip driver itself).
- *
- * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
- * cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#endif
-
-#undef CONFIG_CMD_PPC_DUMP
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
-#define CONFIG_CMD_PPC_DUMP
-#endif
-
-#undef CONFIG_CMD_TCPC_DUMP
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP
-#define CONFIG_CMD_TCPC_DUMP
-#endif
-
-#undef CONFIG_USB_POWER_DELIVERY
-#ifdef CONFIG_PLATFORM_EC_USB_POWER_DELIVERY
-#define CONFIG_USB_POWER_DELIVERY
-#endif
-
-#undef CONFIG_CHARGER
-#undef CONFIG_CHARGE_MANAGER
-#ifdef CONFIG_PLATFORM_EC_CHARGE_MANAGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER
-
-/* TODO: Put these charger defines in the devicetree? */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
-
-#endif
-
-#undef CONFIG_CHARGER_INPUT_CURRENT
-#ifdef CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT
-#define CONFIG_CHARGER_INPUT_CURRENT	CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT
-#endif
-
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
-#endif
-
-#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
-#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
-#endif
-
-#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
-#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
-#endif
-
-#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#endif
-
-#undef CONFIG_CHARGE_RAMP_SW
-#ifdef CONFIG_PLATFORM_EC_CHARGE_RAMP_SW
-#define CONFIG_CHARGE_RAMP_SW
-#endif
-
-#undef CONFIG_CHARGE_RAMP_HW
-#ifdef CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
-#define CONFIG_CHARGE_RAMP_HW
-#endif
-
-#undef CONFIG_CMD_CHGRAMP
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHGRAMP
-#define CONFIG_CMD_CHGRAMP
-#endif
-
-#undef CONFIG_USB_PID
-#ifdef CONFIG_PLATFORM_EC_USB_PID
-#define CONFIG_USB_PID		CONFIG_PLATFORM_EC_USB_PID
-#endif
-
-#undef CONFIG_USB_BCD_DEV
-#ifdef CONFIG_PLATFORM_EC_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV	CONFIG_PLATFORM_EC_USB_BCD_DEV
-#endif
-
-#undef CONFIG_USB_VID
-#ifdef CONFIG_PLATFORM_EC_USB_VID
-#define CONFIG_USB_VID	CONFIG_PLATFORM_EC_USB_VID
-#endif
-
-/* VBUS-voltage measurement */
-#undef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#undef CONFIG_USB_PD_VBUS_MEASURE_CHARGER
-#undef CONFIG_USB_PD_VBUS_MEASURE_TCPC
-#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#undef CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
-#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
-#elif defined(CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER)
-#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
-#elif defined(CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC)
-#define CONFIG_USB_PD_VBUS_MEASURE_TCPC
-#elif defined(CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT)
-#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
-#elif defined(CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD)
-#define CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD
-#endif /* VBUS-voltage measurement */
-
-#undef CONFIG_USB_CHARGER
-#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
-#define CONFIG_USB_CHARGER
-#endif
-
-#define USB_PORT_COUNT	CONFIG_PLATFORM_EC_USB_A_PORT_COUNT
-
-#undef CONFIG_USB_PORT_POWER_DUMB
-#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB
-#define CONFIG_USB_PORT_POWER_DUMB
-#endif
-
-#undef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-#endif
-
-#undef CONFIG_BC12_DETECT_PI3USB9201
-#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
-#define CONFIG_BC12_DETECT_PI3USB9201
-#endif
-
-#undef CONFIG_BC12_DETECT_MT6360
-#ifdef CONFIG_PLATFORM_EC_BC12_DETECT_MT6360
-#define CONFIG_BC12_DETECT_MT6360
-#endif
-
-#undef CONFIG_MT6360_BC12_GPIO
-#ifdef CONFIG_PLATFORM_EC_MT6360_BC12_GPIO
-#define CONFIG_MT6360_BC12_GPIO
-#endif
-
-#undef CONFIG_HOSTCMD_REGULATOR
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_REGULATOR
-#define CONFIG_HOSTCMD_REGULATOR
-#endif
-
-#undef CONFIG_USB_PD_DUAL_ROLE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE
-#endif
-
-#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#endif
-
-#undef CONFIG_USB_PD_DISCHARGE_PPC
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#endif
-
-#undef CONFIG_USB_PD_LOGGING
-#ifdef CONFIG_PLATFORM_EC_USB_PD_LOGGING
-#define CONFIG_USB_PD_LOGGING
-#endif
-
-#undef CONFIG_USBC_OCP
-#ifdef CONFIG_PLATFORM_EC_USBC_OCP
-#define CONFIG_USBC_OCP
-#endif
-
-#undef CONFIG_USB_PD_CONSOLE_CMD
-#ifdef CONFIG_PLATFORM_EC_USB_PD_CONSOLE_CMD
-#define CONFIG_USB_PD_CONSOLE_CMD
-#endif
-
-#undef CONFIG_USB_PD_HOST_CMD
-#ifdef CONFIG_PLATFORM_EC_USB_PD_HOST_CMD
-#define CONFIG_USB_PD_HOST_CMD
-#endif
-
-#undef CONFIG_USB_PD_REV30
-#ifdef CONFIG_PLATFORM_EC_USB_PD_REV30
-#define CONFIG_USB_PD_REV30
-
-/*
- * Support USB PD 3.0 Extended Messages. Note that Chromebooks disabling this
- * config item are non-compliant with PD 3.0, because they have batteries but do
- * not support Get_Battery_Cap or Get_Battery_Status.
- */
-#define CONFIG_USB_PD_EXTENDED_MESSAGES
-#endif
-
-#undef CONFIG_USB_PD_VBUS_DETECT_TCPC
-#undef CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#undef CONFIG_USB_PD_VBUS_DETECT_GPIO
-#undef CONFIG_USB_PD_VBUS_DETECT_PPC
-#undef CONFIG_USB_PD_VBUS_DETECT_NONE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#endif
-#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER
-#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
-#endif
-#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#endif
-#ifdef CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_NONE
-#define CONFIG_USB_PD_VBUS_DETECT_NONE
-#endif
-
-#undef CONFIG_USB_PD_5V_EN_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#endif
-
-#undef CONFIG_USB_TYPEC_SM
-#ifdef CONFIG_PLATFORM_EC_USB_TYPEC_SM
-#define CONFIG_USB_TYPEC_SM
-#endif
-
-#undef CONFIG_USB_PRL_SM
-#ifdef CONFIG_PLATFORM_EC_USB_PRL_SM
-#define CONFIG_USB_PRL_SM
-#endif
-
-#undef CONFIG_USB_PE_SM
-#ifdef CONFIG_PLATFORM_EC_USB_PE_SM
-#define CONFIG_USB_PE_SM
-#endif
-
-#undef CONFIG_USB_PD_DECODE_SOP
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_DECODE_SOP
-#endif
-
-#undef CONFIG_USB_VPD
-#ifdef CONFIG_PLATFORM_EC_USB_VPD
-#define CONFIG_USB_VPD
-#endif
-
-#undef CONFIG_USB_CTVPD
-#ifdef CONFIG_PLATFORM_EC_USB_CTVPD
-#define CONFIG_USB_CTVPD
-#endif
-
-#undef CONFIG_USB_DRP_ACC_TRYSRC
-#ifdef CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#endif
-
-#undef CONFIG_USB_PD_TCPM_PS8751
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751
-#define CONFIG_USB_PD_TCPM_PS8751
-#endif
-
-#undef CONFIG_USB_PD_TCPM_PS8805
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805
-#define CONFIG_USB_PD_TCPM_PS8805
-#endif
-
-#undef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805_FORCE_DID
-#define CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-#endif
-
-#undef CONFIG_USB_PD_TCPM_PS8815
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815
-#define CONFIG_USB_PD_TCPM_PS8815
-#endif
-
-#undef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID
-#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
-#endif
-
-#undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
-#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX
-#endif
-
-#undef CONFIG_USB_PD_TCPM_RT1715
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715
-#define CONFIG_USB_PD_TCPM_RT1715
-#endif
-
-#undef CONFIG_USB_PD_TCPM_TUSB422
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422
-#define CONFIG_USB_PD_TCPM_TUSB422
-#endif
-
-#undef CONFIG_USB_PD_TCPM_TCPCI
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_TCPM_TCPCI
-#endif
-
-#undef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-
-/* TODO(b:189855648): hard-code a few things here; move to zephyr? */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
-#endif
-
-#undef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2
-#define CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
-#endif
-
-#undef CONFIG_USB_PD_TCPM_DRIVER_IT83XX
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
-#define CONFIG_USB_PD_TCPM_DRIVER_IT83XX
-#endif
-
-#undef CONFIG_USB_PD_PORT_MAX_COUNT
-#ifdef CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT
-#define CONFIG_USB_PD_PORT_MAX_COUNT CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT
-#endif
-
-#undef CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT \
-	CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-#endif
-
-#undef CONFIG_USBC_PPC
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC
-#define CONFIG_USBC_PPC
-#endif
-
-#undef CONFIG_USBC_PPC_SN5S330
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SN5S330
-#define CONFIG_USBC_PPC_SN5S330
-#endif
-
-#undef CONFIG_USBC_PPC_SYV682X
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X
-#define CONFIG_USBC_PPC_SYV682X
-#endif
-
-#undef CONFIG_USBC_PPC_SYV682C
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682C
-#define CONFIG_USBC_PPC_SYV682C
-#endif
-
-#undef CONFIG_USBC_PPC_SYV682X_NO_CC
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_NO_CC
-#define CONFIG_USBC_PPC_SYV682X_NO_CC
-#endif
-
-#undef CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE
-#define CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE
-#endif
-
-#undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-#undef CONFIG_USB_MUX_RUNTIME_CONFIG
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
-#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
-
-#ifdef CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-#endif /* CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG */
-
-#endif /* CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG */
-
-#undef CONFIG_USB_PD_ALT_MODE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE
-#endif
-
-#undef CONFIG_USB_PD_ALT_MODE_DFP
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#endif
-
-#undef CONFIG_USB_PD_ALT_MODE_UFP
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP
-#define CONFIG_USB_PD_ALT_MODE_UFP
-#endif
-
-#undef CONFIG_USB_PD_DPS
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DPS
-#define CONFIG_USB_PD_DPS
-#endif
-
-#undef CONFIG_DP_REDRIVER_TDP142
-#ifdef CONFIG_PLATFORM_EC_DP_REDRIVER_TDP142
-#define CONFIG_DP_REDRIVER_TDP142
-#endif
-
-#undef CONFIG_USBC_RETIMER_FW_UPDATE
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-#endif
-
-#undef CONFIG_USBC_RETIMER_INTEL_BB
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
-
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR \
-	DT_REG_ADDR(DT_NODELABEL(usb_c1_bb_retimer))
-#define CONFIG_USBC_RETIMER_INTEL_BB
-#endif
-
-#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
-#endif
-
-#undef CONFIG_USBC_RETIMER_ANX7451
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7451
-#define CONFIG_USBC_RETIMER_ANX7451
-#endif
-
-#undef CONFIG_USBC_RETIMER_PS8811
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811
-#define CONFIG_USBC_RETIMER_PS8811
-#endif
-
-#undef CONFIG_USBC_SS_MUX
-#ifdef CONFIG_PLATFORM_EC_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX
-#endif
-
-#undef CONFIG_USBC_SS_MUX_DFP_ONLY
-#ifdef CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#endif
-
-#undef CONFIG_USB_MUX_IT5205
-#ifdef CONFIG_PLATFORM_EC_USB_MUX_IT5205
-#define CONFIG_USB_MUX_IT5205
-#endif
-
-#undef CONFIG_USB_MUX_PS8743
-#ifdef CONFIG_PLATFORM_EC_USB_MUX_PS8743
-#define CONFIG_USB_MUX_PS8743
-#endif
-
-#undef CONFIG_USB_MUX_VIRTUAL
-#ifdef CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL
-#define CONFIG_USB_MUX_VIRTUAL
-#endif
-
-#undef CONFIG_USB_PD_TCPM_MUX
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_MUX
-#endif
-
-#undef CONFIG_USBC_PPC_DEDICATED_INT
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT
-#define CONFIG_USBC_PPC_DEDICATED_INT
-#endif
-
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_PD
-#define CONFIG_CONSOLE_CMD_PD
-#endif
-
-#ifdef CONFIG_HAS_TASK_PD_INT_C0
-/* This must be defined if any task is active */
-#define CONFIG_HAS_TASK_PD_INT
-#endif
-
-#undef CONFIG_MKBP_EVENT
-#undef CONFIG_MKBP_USE_GPIO
-#undef CONFIG_MKBP_USE_HOST_EVENT
-#undef CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#undef CONFIG_MKBP_USE_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
-#define CONFIG_MKBP_EVENT
-#ifdef CONFIG_PLATFORM_EC_MKBP_USE_GPIO
-#define CONFIG_MKBP_USE_GPIO
-#elif defined(CONFIG_PLATFORM_EC_MKBP_USE_HOST_EVENT)
-#define CONFIG_MKBP_USE_HOST_EVENT
-#elif defined(CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT)
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#elif defined(CONFIG_PLATFORM_EC_MKBP_USE_CUSTOM)
-#define CONFIG_MKBP_USE_CUSTOM
-#endif
-#endif /* CONFIG_PLATFORM_EC_MKBP_EVENT */
-
-#undef CONFIG_USB_PD_TCPC_LOW_POWER
-#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE \
-		CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
-#endif /* CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER */
-
-#undef CONFIG_USB_PD_DEBUG_LEVEL
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
-#define CONFIG_USB_PD_DEBUG_LEVEL	CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL
-#endif
-
-#undef CONFIG_USBC_VCONN
-#ifdef CONFIG_PLATFORM_EC_USBC_VCONN
-#define CONFIG_USBC_VCONN
-
-/* This must be defined as well */
-#define CONFIG_USBC_VCONN_SWAP
-#endif /* CONFIG_PLATFORM_EC_USBC_VCONN */
-
-#undef CONFIG_USB_PD_TRY_SRC
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_TRY_SRC
-#endif
-
-#undef CONFIG_USBC_PPC_POLARITY
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_POLARITY
-#define CONFIG_USBC_PPC_POLARITY
-#endif
-
-#undef CONFIG_USBC_PPC_SBU
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_SBU
-#define CONFIG_USBC_PPC_SBU
-#endif
-
-#undef CONFIG_USBC_PPC_VCONN
-#ifdef CONFIG_PLATFORM_EC_USBC_PPC_VCONN
-#define CONFIG_USBC_PPC_VCONN
-#endif
-
-#undef CONFIG_USB_PD_USB32_DRD
-#ifdef CONFIG_PLATFORM_EC_USB_PD_USB32_DRD
-#define CONFIG_USB_PD_USB32_DRD
-#endif
-
-#undef CONFIG_HOSTCMD_PD_CONTROL
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_PD_CONTROL
-#define CONFIG_HOSTCMD_PD_CONTROL
-#endif
-
-#undef CONFIG_CMD_HCDEBUG
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_HCDEBUG
-#define CONFIG_CMD_HCDEBUG
-#endif
-
-#undef CONFIG_CMD_USB_PD_PE
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_PE
-#define CONFIG_CMD_USB_PD_PE
-#endif
-
-#undef CONFIG_CMD_USB_PD_CABLE
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE
-#define CONFIG_CMD_USB_PD_CABLE
-#endif
-
-#undef CONFIG_USB_PD_TBT_COMPAT_MODE
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-#endif
-
-#undef CONFIG_USB_PD_USB4
-#ifdef CONFIG_PLATFORM_EC_USB_PD_USB4
-#define CONFIG_USB_PD_USB4
-#endif
-
-#undef CONFIG_USB_PD_FRS
-#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS
-#define CONFIG_USB_PD_FRS
-#endif
-
-#undef CONFIG_USB_PD_FRS_TCPC
-#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC
-#define CONFIG_USB_PD_FRS_TCPC
-#endif
-
-#undef CONFIG_USB_PD_FRS_PPC
-#ifdef CONFIG_PLATFORM_EC_USB_PD_FRS_PPC
-#define CONFIG_USB_PD_FRS_PPC
-#endif
-
-#undef CONFIG_VSTORE
-#undef VSTORE_SLOT_COUNT
-#ifdef CONFIG_PLATFORM_EC_VSTORE
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT	CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT
-#endif
-
-/* motion sense */
-#undef CONFIG_MOTIONSENSE
-#ifdef CONFIG_PLATFORM_EC_MOTIONSENSE
-#define CONFIG_MOTIONSENSE
-
-#undef CONFIG_ACCEL_FIFO
-#undef CONFIG_ACCEL_FIFO_SIZE
-#undef CONFIG_ACCEL_FIFO_THRES
-#ifdef CONFIG_PLATFORM_EC_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE CONFIG_PLATFORM_EC_ACCEL_FIFO_SIZE
-#define CONFIG_ACCEL_FIFO_THRES CONFIG_PLATFORM_EC_ACCEL_FIFO_THRES
-#endif /* CONFIG_PLATFORM_EC_ACCEL_FIFO */
-
-#undef CONFIG_CMD_ACCELS
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS
-#define CONFIG_CMD_ACCELS
-#endif
-
-#undef CONFIG_CMD_ACCEL_INFO
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO
-#define CONFIG_CMD_ACCEL_INFO
-#endif
-
-#undef CONFIG_ACCEL_SPOOF_MODE
-#ifdef CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE
-#define CONFIG_ACCEL_SPOOF_MODE
-#endif
-
-#undef CONFIG_CMD_ACCEL_SPOOF
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF
-#define CONFIG_CMD_ACCEL_SPOOF
-#endif
-
-#undef CONFIG_SENSOR_TIGHT_TIMESTAMPS
-#ifdef CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS
-#define CONFIG_SENSOR_TIGHT_TIMESTAMPS
-#endif
-
-#undef CONFIG_ACCEL_INTERRUPTS
-#ifdef CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS
-#define CONFIG_ACCEL_INTERRUPTS
-#endif
-
-#undef CONFIG_ALS
-#undef CONFIG_ALS_COUNT
-#ifdef CONFIG_PLATFORM_EC_ALS
-#define CONFIG_ALS
-#define ALS_COUNT CONFIG_PLATFORM_EC_ALS_COUNT
-#else
-#define ALS_COUNT 0
-#endif
-
-#undef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#ifdef CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#endif
-
-#undef CONFIG_LID_ANGLE
-#ifdef CONFIG_PLATFORM_EC_LID_ANGLE
-#define CONFIG_LID_ANGLE
-#endif
-
-#undef CONFIG_LID_ANGLE_UPDATE
-#ifdef CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_UPDATE
-#endif
-
-#undef CONFIG_TABLET_MODE
-#ifdef CONFIG_PLATFORM_EC_TABLET_MODE
-#define CONFIG_TABLET_MODE
-#endif
-
-#undef CONFIG_TABLET_MODE_SWITCH
-#ifdef CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH
-#define CONFIG_TABLET_MODE_SWITCH
-#endif
-
-#undef CONFIG_GMR_TABLET_MODE
-#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-#endif
-
-/* sensors */
-#undef CONFIG_ACCELGYRO_BMI160
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160
-#endif
-
-#undef CONFIG_ACCELGYRO_BMI260
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
-#define CONFIG_ACCELGYRO_BMI260
-#endif
-
-#undef CONFIG_ACCELGYRO_BMI3XX
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX
-#define CONFIG_ACCELGYRO_BMI3XX
-#endif
-
-#undef CONFIG_ACCEL_BMA255
-#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA255
-#define CONFIG_ACCEL_BMA255
-#endif
-
-#undef CONFIG_ACCEL_BMA4XX
-#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA4XX
-#define CONFIG_ACCEL_BMA4XX
-#endif
-
-#undef CONFIG_ACCEL_KX022
-#ifdef CONFIG_PLATFORM_EC_ACCEL_KX022
-#define CONFIG_ACCEL_KX022
-#endif
-
-#undef CONFIG_ALS_TCS3400
-#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400
-#define CONFIG_ALS_TCS3400
-#endif
-
-#undef CONFIG_ACCELGYRO_ICM426XX
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM426XX
-#define CONFIG_ACCELGYRO_ICM426XX
-#endif
-
-#undef CONFIG_ACCELGYRO_ICM42607
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607
-#define CONFIG_ACCELGYRO_ICM42607
-#endif
-
-#endif /* CONFIG_PLATFORM_EC_MOTIONSENSE */
-
-#undef CONFIG_HOSTCMD_GET_UPTIME_INFO
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_GET_UPTIME_INFO
-#define CONFIG_HOSTCMD_GET_UPTIME_INFO
-#endif
-
-#undef CONFIG_CMD_AP_RESET_LOG
-#ifdef CONFIG_PLATFORM_EC_AP_RESET_LOG
-#define CONFIG_CMD_AP_RESET_LOG
-#endif
-
-#undef CONFIG_POWER_BUTTON
-#ifdef CONFIG_PLATFORM_EC_POWER_BUTTON
-#define CONFIG_POWER_BUTTON
-#endif
-
-#undef CONFIG_COMMON_PANIC_OUTPUT
-#ifdef CONFIG_PLATFORM_EC_PANIC
-#define CONFIG_COMMON_PANIC_OUTPUT
-#endif
-
-#undef CONFIG_SOFTWARE_PANIC
-#ifdef CONFIG_PLATFORM_EC_SOFTWARE_PANIC
-#define CONFIG_SOFTWARE_PANIC
-#endif
-
-#undef CONFIG_CMD_CRASH
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CRASH
-#define CONFIG_CMD_CRASH
-#endif
-
-#undef CONFIG_CMD_STACKOVERFLOW
-#ifdef CONFIG_PLATFORM_EC_STACKOVERFLOW
-#define CONFIG_CMD_STACKOVERFLOW
-#endif
-
-#undef CONFIG_CMD_MEM
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM
-#define CONFIG_CMD_MEM
-#endif
-
-#undef CONFIG_CMD_MD
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MD
-#define CONFIG_CMD_MD
-#endif
-
-#undef CONFIG_CMD_RW
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RW
-#define CONFIG_CMD_RW
-#endif
-
-#undef CONFIG_RTC
-#ifdef CONFIG_PLATFORM_EC_RTC
-#define CONFIG_RTC
-#endif
-
-#undef CONFIG_CMD_RTC
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC
-#define CONFIG_CMD_RTC
-#endif
-
-#undef CONFIG_CMD_RTC_ALARM
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
-#define CONFIG_CMD_RTC_ALARM
-#endif
-
-#undef CONFIG_HOSTCMD_RTC
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_RTC
-#define CONFIG_HOSTCMD_RTC
-#endif
-
-#undef CONFIG_HOST_COMMAND_STATUS
-#ifdef CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS
-#define CONFIG_HOST_COMMAND_STATUS
-#endif
-
-#undef CONFIG_SWITCH
-#ifdef CONFIG_PLATFORM_EC_SWITCH
-#define CONFIG_SWITCH
-#endif
-
-#undef CONFIG_LN9310
-#ifdef CONFIG_PLATFORM_EC_SWITCHCAP_LN9310
-#define CONFIG_LN9310
-#endif
-
-#undef CONFIG_BOARD_VERSION_CBI
-#ifdef CONFIG_PLATFORM_EC_BOARD_VERSION_CBI
-#define CONFIG_BOARD_VERSION_CBI
-#endif
-
-#undef CONFIG_BOARD_VERSION_GPIO
-#ifdef CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO
-#define CONFIG_BOARD_VERSION_GPIO
-#endif
-
-#undef CONFIG_CBI_EEPROM
-#ifdef CONFIG_PLATFORM_EC_CBI_EEPROM
-#define CONFIG_CBI_EEPROM
-#define I2C_ADDR_EEPROM_FLAGS DT_REG_ADDR(DT_NODELABEL(cbi_eeprom))
-#endif
-
-#undef CONFIG_CBI_GPIO
-#ifdef CONFIG_PLATFORM_EC_CBI_GPIO
-#define CONFIG_CBI_GPIO
-#endif
-
-#undef CONFIG_VBOOT_HASH
-#ifdef CONFIG_PLATFORM_EC_VBOOT_HASH
-#define CONFIG_VBOOT_HASH
-#endif
-
-#undef CONFIG_SHA256_HW_ACCELERATE
-#ifdef CONFIG_PLATFORM_EC_SHA256_HW_ACCELERATE
-#define CONFIG_SHA256_HW_ACCELERATE
-#endif
-
-#undef CONFIG_RO_HDR_MEM_OFF
-#ifdef CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
-#define CONFIG_RO_HDR_MEM_OFF	CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
-#else
-#define CONFIG_RO_HDR_MEM_OFF 0
-#endif
-
-#undef CONFIG_RO_HDR_SIZE
-#ifdef CONFIG_PLATFORM_EC_RO_HEADER_SIZE
-#define CONFIG_RO_HDR_SIZE	CONFIG_PLATFORM_EC_RO_HEADER_SIZE
-#else
-#define CONFIG_RO_HDR_SIZE 0
-#endif
-
-#undef CONFIG_SYSTEM_UNLOCKED
-#ifdef CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED
-#define CONFIG_SYSTEM_UNLOCKED
-#endif
-
-#undef CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
-#ifdef CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK
-#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK
-#endif
-
-#undef CONFIG_SPI_FLASH_REGS
-#ifdef CONFIG_PLATFORM_EC_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_REGS
-#endif
-
-#undef CONFIG_CMD_CHARGEN
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGEN
-#define CONFIG_CMD_CHARGEN
-#endif
-
-#undef CONFIG_DEBUG_ASSERT
-#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT
-#define CONFIG_DEBUG_ASSERT
-#endif
-
-#undef CONFIG_DEBUG_ASSERT_BRIEF
-#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF
-#define CONFIG_DEBUG_ASSERT_BRIEF
-#endif
-
-#undef CONFIG_DEBUG_ASSERT_REBOOTS
-#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS
-#define CONFIG_DEBUG_ASSERT_REBOOTS
-#endif
-
-#undef CONFIG_MPU
-#ifdef CONFIG_PLATFORM_EC_MPU
-#define CONFIG_MPU
-#endif
-
-#undef CONFIG_CMD_SYSINFO
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO
-#define CONFIG_CMD_SYSINFO
-#endif
-
-#undef CONFIG_CMD_SCRATCHPAD
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD
-#define CONFIG_CMD_SCRATCHPAD
-#endif
-
-#undef CONFIG_CMD_SYSJUMP
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSJUMP
-#define CONFIG_CMD_SYSJUMP
-#endif
-
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#ifdef CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS
-#endif
-
-#undef CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS
-#if defined(CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS) || \
-	defined(CONFIG_WDT_NPCX_DELAY_CYCLES) || \
-	defined(CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS)
-/*
- * Note:
- * NPCX wdt driver uses CONFIG_WDT_NPCX_DELAY_CYCLES to set the leading
- * time of the watchdog warning timer.
- * IT8XXX2 WDT driver uses CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS period
- * between watchdog warning and reset.
- */
-#ifdef CONFIG_WDT_NPCX_DELAY_CYCLES
-#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
-	(CONFIG_WDT_NPCX_DELAY_CYCLES * 31)
-#elif CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS
-#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
-	CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS
-#else
-#define CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS \
-	CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS
-#endif
-#endif
-
-#undef CONFIG_VBOOT_EFS
-#undef CONFIG_VBOOT_EFS2
-#ifdef CONFIG_PLATFORM_EC_VBOOT_EFS2
-#define CONFIG_VBOOT_EFS2
-#endif
-
-#undef CONFIG_USB_PD_TCPC_VCONN
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_VCONN
-#define CONFIG_USB_PD_TCPC_VCONN
-#endif
-
-#undef CONFIG_DPTF
-#ifdef CONFIG_PLATFORM_EC_DPTF
-#define CONFIG_DPTF
-#endif
-
-#undef CONFIG_CHARGER_BQ25710
-#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710
-#define CONFIG_CHARGER_BQ25710
-#endif
-
-#undef CONFIG_CHARGER_BQ25720
-#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720
-#define CONFIG_CHARGER_BQ25720
-#endif
-
-#undef CONFIG_CHARGER_BQ25720_VSYS_TH2_DV
-#ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV \
-	CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV
-#endif
-
-#undef CONFIG_HIBERNATE_PSL
-#ifdef CONFIG_PLATFORM_EC_HIBERNATE_PSL
-#define CONFIG_HIBERNATE_PSL
-#endif
-
-#undef CONFIG_BATTERY_DEVICE_CHEMISTRY
-#ifdef CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY	\
-	CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY
-#endif
-
-#undef CONFIG_CHARGER_DISCHARGE_ON_AC
-#ifdef CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#endif
-
-#undef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
-#endif
-
-#undef CONFIG_CHARGER_SENSE_RESISTOR
-#ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
-#define CONFIG_CHARGER_SENSE_RESISTOR	\
-	CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
-#endif
-
-#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
-#ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	\
-	CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
-#endif
-
-#undef CONFIG_CHARGER_PROFILE_OVERRIDE
-#ifdef CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE
-#define CONFIG_CHARGER_PROFILE_OVERRIDE
-#endif
-
-#undef CONFIG_CHARGER_PSYS
-#ifdef CONFIG_PLATFORM_EC_CHARGER_PSYS
-#define CONFIG_CHARGER_PSYS
-#endif
-
-#undef CONFIG_CHARGER_PSYS_READ
-#ifdef CONFIG_PLATFORM_EC_CHARGER_PSYS_READ
-#define CONFIG_CHARGER_PSYS_READ
-#endif
-
-#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#endif
-
-#undef CONFIG_USB_PD_ONLY_FIXED_PDOS
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS
-#define CONFIG_USB_PD_ONLY_FIXED_PDOS
-#endif
-
-#undef CONFIG_MP2964
-#ifdef CONFIG_PLATFORM_EC_MP2964
-#define CONFIG_MP2964
-#endif
-
-#undef CONFIG_ACCELGYRO_ICM_COMM_SPI
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_SPI
-#define CONFIG_ACCELGYRO_ICM_COMM_SPI
-#endif
-
-#undef CONFIG_ACCELGYRO_ICM_COMM_I2C
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C
-#define CONFIG_ACCELGYRO_ICM_COMM_I2C
-#endif
-
-#undef CONFIG_ACCELGYRO_BMI_COMM_SPI
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_SPI
-#define CONFIG_ACCELGYRO_BMI_COMM_SPI
-#endif
-
-#undef CONFIG_ACCELGYRO_BMI_COMM_I2C
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C
-#define CONFIG_ACCELGYRO_BMI_COMM_I2C
-#endif
-
-#undef CONFIG_CMD_SLEEPMASK
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SLEEPMASK
-#define CONFIG_CMD_SLEEPMASK
-#endif
-
-#undef CONFIG_CMD_SLEEPMASK_SET
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SLEEPMASK_SET
-#define CONFIG_CMD_SLEEPMASK_SET
-#endif
-
-#undef CONFIG_LOW_POWER_IDLE
-#ifdef CONFIG_PLATFORM_EC_LOW_POWER_IDLE
-#define CONFIG_LOW_POWER_IDLE
-#endif
-
-#undef CONFIG_PORT80_4_BYTE
-#ifdef CONFIG_PLATFORM_EC_PORT80_4_BYTE
-#define CONFIG_PORT80_4_BYTE
-#endif
-
-#undef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#ifdef CONFIG_PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#endif
-
-#undef CONFIG_CCD_USBC_PORT_NUMBER
-#ifdef CONFIG_PLATFORM_EC_CCD_USBC_PORT_NUMBER
-#define CONFIG_CCD_USBC_PORT_NUMBER CONFIG_PLATFORM_EC_CCD_USBC_PORT_NUMBER
-#endif
-
-#undef CONFIG_ACCEL_LIS2DW12
-#ifdef CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
-#define CONFIG_ACCEL_LIS2DW12
-#endif
-
-#undef CONFIG_ACCEL_LIS2DW_AS_BASE
-#ifdef CONFIG_PLATFORM_EC_ACCEL_LIS2DW12_AS_BASE
-#define CONFIG_ACCEL_LIS2DW_AS_BASE
-#endif
-
-#undef CONFIG_CONSOLE_CHANNEL
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CHANNEL
-#define CONFIG_CONSOLE_CHANNEL
-#endif
-
-#undef CONFIG_USB_PD_DP_HPD_GPIO
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#endif
-
-#undef CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#ifdef CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM
-#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
-#endif
-
-#undef CONSOLE_CMD_MFALLOW
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_MFALLOW
-#define CONSOLE_CMD_MFALLOW
-#endif
-
-#undef CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS
-#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
-#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS \
-	CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY_MS
-#endif
-
-#undef CONFIG_CMD_S5_TIMEOUT
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_S5_TIMEOUT
-#define CONFIG_CMD_S5_TIMEOUT
-#endif
-
-#undef CONFIG_FW_RESET_VECTOR
-#ifdef CONFIG_PLATFORM_EC_FW_RESET_VECTOR
-#define CONFIG_FW_RESET_VECTOR
-#endif
-
-#undef CONFIG_HOSTCMD_DEBUG_MODE
-#if defined(CONFIG_HCDEBUG_OFF)
-#define CONFIG_HOSTCMD_DEBUG_MODE 0
-#elif defined(CONFIG_HCDEBUG_NORMAL)
-#define CONFIG_HOSTCMD_DEBUG_MODE 1
-#elif defined(CONFIG_HCDEBUG_EVERY)
-#define CONFIG_HOSTCMD_DEBUG_MODE 2
-#elif defined(CONFIG_HCDEBUG_PARAMS)
-#define CONFIG_HOSTCMD_DEBUG_MODE 3
-#endif
-
-#undef CONFIG_AMD_SB_RMI
-#ifdef CONFIG_PLATFORM_EC_AMD_SB_RMI
-#define CONFIG_AMD_SB_RMI
-#endif
-
-#undef CONFIG_AMD_STT
-#ifdef CONFIG_PLATFORM_EC_AMD_STT
-#define CONFIG_AMD_STT
-#endif
-
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/zephyr/shim/include/cpu.h b/zephyr/shim/include/cpu.h
deleted file mode 100644
index 617f644fa9..0000000000
--- a/zephyr/shim/include/cpu.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-/* Do nothing for Zephyr */
-static inline void cpu_init(void)
-{
-}
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/zephyr/shim/include/ec_tasks.h b/zephyr/shim/include/ec_tasks.h
deleted file mode 100644
index 6f75bd577e..0000000000
--- a/zephyr/shim/include/ec_tasks.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_EC_TASKS_H
-#define __CROS_EC_EC_TASKS_H
-
-/*
- * The lowest preemptive thread priority is (CONFIG_NUM_PREEMT_PRIORITIES-1)
- * while the lowest cooperative thread priority is -1.
- *
- * https://docs.zephyrproject.org/latest/reference/kernel/threads/index.html#thread-priorities
- */
-#define LOWEST_THREAD_PRIORITY              \
-	COND_CODE_1(CONFIG_PREEMPT_ENABLED, \
-		    (CONFIG_NUM_PREEMPT_PRIORITIES - 1), (-1))
-
-/** Starts all of the shimmed EC tasks. Requires CONFIG_SHIMMED_TASKS=y. */
-void start_ec_tasks(void);
-
-#ifdef TEST_BUILD
-/**
- * Set TASK_ID_TEST_RUNNER to current thread tid. Some functions that are tested
- * require to run in any task context.
- */
-void set_test_runner_tid(void);
-#endif
-
-#endif /* __CROS_EC_EC_TASKS_H */
diff --git a/zephyr/shim/include/fpu.h b/zephyr/shim/include/fpu.h
deleted file mode 100644
index da36f50492..0000000000
--- a/zephyr/shim/include/fpu.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_FPU_H
-#define __CROS_EC_FPU_H
-
-/*
- * These functions are available in newlib but we are are using Zephyr's
- * minimal library at present.
- *
- * This file is not called math.h to avoid a conflict with the toolchain's
- * built-in version.
- *
- * This code is taken from core/cortex-m/include/fpu.h
- */
-
-#ifdef CONFIG_PLATFORM_EC_FPU
-
-/* Implementation for Cortex-M */
-#ifdef CONFIG_CPU_CORTEX_M
-static inline float sqrtf(float v)
-{
-	float root;
-
-	/* Use the CPU instruction */
-	__asm__ volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-
-	return root;
-}
-
-static inline float fabsf(float v)
-{
-	float root;
-
-	/* Use the CPU instruction */
-	__asm__ volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
-
-	return root;
-}
-#else
-#error "Unsupported core: please add an implementation"
-#endif /* CONFIG_CPU_CORTEX_M */
-
-#endif  /* CONFIG_PLATFORM_EC_FPU */
-
-#endif  /* __CROS_EC_MATH_H */
diff --git a/zephyr/shim/include/gpio/gpio.h b/zephyr/shim/include/gpio/gpio.h
deleted file mode 100644
index 18089e8a8e..0000000000
--- a/zephyr/shim/include/gpio/gpio.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_
-#define ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_
-
-#include <device.h>
-#include <devicetree.h>
-
-/* Information about each unused pin in the 'unused-pins' device tree node. */
-struct unused_pin_config {
-	/* Device name of a unused gpio pin */
-	const char *dev_name;
-	/* Bit number of pin within a unused gpio pin */
-	gpio_pin_t pin;
-	/* Config flags of unused gpio pin */
-	gpio_flags_t flags;
-};
-
-/**
- * @brief Set proper configuration for all unused pins.
- *
- * This function loops through all unused GPIOs in the node of "unused-gpios"
- * in the device tree file to set proper configuration. If the GPIO flag is 0,
- * set the GPIOs default setting for floating IOs to improve the power
- * consumption.
- *
- * @return 0 If successful.
- * @retval -ENOTSUP Not supported gpio device.
- * @retval -EIO I/O error when accessing an external GPIO chip.
- */
-int gpio_config_unused_pins(void) __attribute__((weak));
-
-#if DT_NODE_EXISTS(DT_PATH(unused_pins))
-/**
- * @brief Get a node from path '/unused-pins' which has a prop 'unused-gpios'.
- *        It contains unused GPIOs and chip vendor needs to configure them for
- *        better power consumption in the lowest power state.
- *
- * @return node identifier with that path.
- */
-#define UNUSED_PINS_LIST DT_PATH(unused_pins)
-
-/**
- * @brief Length of 'unused-gpios' property
- *
- * @return length of 'unused-gpios' prop which type is 'phandle-array'
- */
-#define UNUSED_GPIOS_LIST_LEN DT_PROP_LEN(UNUSED_PINS_LIST, unused_gpios)
-
-/**
- * @brief Construct a unused_pin_config structure from 'unused-gpios' property
- *        at index 'i'
- *
- * @param i index of 'unused-gpios' prop which type is 'phandles-array'
- * @return unused_pin_config item at index 'i'
- */
-#define UNUSED_GPIO_CONFIG_BY_IDX(i, _)                                       \
-	{                                                                     \
-		.dev_name = DT_GPIO_LABEL_BY_IDX(UNUSED_PINS_LIST,            \
-						 unused_gpios, i),            \
-		.pin = DT_GPIO_PIN_BY_IDX(UNUSED_PINS_LIST, unused_gpios, i), \
-		.flags = DT_GPIO_FLAGS_BY_IDX(UNUSED_PINS_LIST, unused_gpios, \
-					      i),                             \
-	},
-
-/**
- * @brief Macro function to construct a list of unused_pin_config items by
- *        UTIL_LISTIFY func.
- *
- * Example devicetree fragment:
- *    / {
- *          unused-pins {
- *		compatible = "unused-gpios";
- *		unused-gpios = <&gpio5 1 0>,
- *			       <&gpiod 0 0>,
- *			       <&gpiof 3 0>;
- *	};
- *
- * Example usage:
- * static const struct unused_pin_config unused_pin_configs[] = {
- * 	UNUSED_GPIO_CONFIG_LIST
- * };
- *
- * @return a list of unused_pin_config items
- */
-#define UNUSED_GPIO_CONFIG_LIST \
-	UTIL_LISTIFY(UNUSED_GPIOS_LIST_LEN, UNUSED_GPIO_CONFIG_BY_IDX, _)
-
-#else
-#define UNUSED_GPIO_CONFIG_LIST /* Nothing if no 'unused-pins' node */
-#endif /* unused_pins */
-#endif /* ZEPHYR_SHIM_INCLUDE_GPIO_GPIO_H_ */
diff --git a/zephyr/shim/include/i2c/i2c.h b/zephyr/shim/include/i2c/i2c.h
deleted file mode 100644
index d945732856..0000000000
--- a/zephyr/shim/include/i2c/i2c.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_CHROME_I2C_I2C_H
-#define ZEPHYR_CHROME_I2C_I2C_H
-
-#include <device.h>
-#include <devicetree.h>
-
-#ifdef CONFIG_PLATFORM_EC_I2C
-#if DT_NODE_EXISTS(DT_PATH(named_i2c_ports))
-
-#define I2C_PORT(id) DT_STRING_UPPER_TOKEN(id, enum_name)
-#define I2C_PORT_WITH_COMMA(id) I2C_PORT(id),
-
-enum i2c_ports {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_WITH_COMMA)
-	I2C_PORT_COUNT
-};
-#define NAMED_I2C(name) I2C_PORT(DT_PATH(named_i2c_ports, name))
-#endif /* named_i2c_ports */
-#endif /* CONFIG_PLATFORM_EC_I2C */
-
-/**
- * @brief Adaptation of platform/ec's port IDs which map a port/bus to a device.
- *
- * This function should be implemented per chip and should map the enum value
- * defined for the chip for encoding each valid port/bus combination. For
- * example, the npcx chip defines the port/bus combinations NPCX_I2C_PORT* under
- * chip/npcx/registers-npcx7.h.
- *
- * Thus, the npcx shim should implement this function to map the enum values
- * to the correct devicetree device.
- *
- * @param port The port to get the device for.
- * @return Pointer to the device struct or {@code NULL} if none are available.
- */
-const struct device *i2c_get_device_for_port(const int port);
-
-/**
- * @brief Get a port number for a received remote port number.
- *
- * This function translate a received port number via the I2C_PASSTHRU host
- * command to a port number used in ZephyrEC based on remote_port property in
- * dts. The first port which matches the remote port number is returned.
- *
- * @param port The received remote port.
- * @return Port number used in EC. -1 if the remote port is not defined
- */
-int i2c_get_port_from_remote_port(int remote_port);
-
-#endif /* ZEPHYR_CHROME_I2C_I2C_H */
diff --git a/zephyr/shim/include/linker.h b/zephyr/shim/include/linker.h
deleted file mode 100644
index 335f4f0f19..0000000000
--- a/zephyr/shim/include/linker.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_LINKER_H
-#define __CROS_EC_LINKER_H
-
-/* Put the start of shared memory after all allocated RAM symbols */
-#define __shared_mem_buf	_image_ram_end
-
-#endif
diff --git a/zephyr/shim/include/motionsense_sensors.h b/zephyr/shim/include/motionsense_sensors.h
deleted file mode 100644
index bdec8e79bd..0000000000
--- a/zephyr/shim/include/motionsense_sensors.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MOTIONSENSE_SENSORS_H
-#define __CROS_EC_MOTIONSENSE_SENSORS_H
-
-#include <devicetree.h>
-
-#define SENSOR_NODE			DT_PATH(motionsense_sensor)
-#define SENSOR_INFO_NODE		DT_PATH(motionsense_sensor_info)
-#define SENSOR_ALT_NODE			DT_PATH(motionsense_sensor_alt)
-
-#define SENSOR_ID(id)			DT_CAT(SENSOR_, id)
-
-/* Define the SENSOR_ID if:
- * DT_NODE_HAS_STATUS(id, okay) && !DT_NODE_HAS_PROP(id, alternate_for)
- */
-#define SENSOR_ID_WITH_COMMA(id)                                     \
-	IF_ENABLED(DT_NODE_HAS_STATUS(id, okay),                     \
-		   (COND_CODE_0(DT_NODE_HAS_PROP(id, alternate_for), \
-				(SENSOR_ID(id), ), ())))
-
-enum sensor_id {
-#if DT_NODE_EXISTS(SENSOR_NODE)
-	DT_FOREACH_CHILD(SENSOR_NODE, SENSOR_ID_WITH_COMMA)
-#endif
-	SENSOR_COUNT,
-};
-
-#undef SENSOR_ID_WITH_COMMA
-/* Define the SENSOR_ID if:
- * DT_NODE_HAS_STATUS(id, okay) && DT_NODE_HAS_PROP(id, alternate_for)
- */
-#define SENSOR_ID_WITH_COMMA(id)                                     \
-	IF_ENABLED(DT_NODE_HAS_STATUS(id, okay),                     \
-		   (COND_CODE_1(DT_NODE_HAS_PROP(id, alternate_for), \
-				(SENSOR_ID(id), ), ())))
-enum sensor_alt_id {
-#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
-	DT_FOREACH_CHILD(SENSOR_ALT_NODE, SENSOR_ID_WITH_COMMA)
-#endif
-	SENSOR_ALT_COUNT,
-};
-
-/*
- * Find the accelerometers for lid angle calculation.
- *
- * The angle calculation requires two accelerometers. One is on the lid
- * and the other one is on the base. So we need to specify which sensor is
- * on the lid and which one is on the base. We use two labels "lid_accel"
- * and "base_accel".
- *
- * base_accel - label for the accelerometer sensor on the base.
- * lid_accel - label for the accelerometer sensor on the lid.
- *
- * e.g) below shows BMA255 is the accelerometer on the lid and bmi260 is
- *     the accelerometer on the base.
- *
- * motionsense-sensor {
- *         lid_accel: lid-accel {
- *                 compatible = "cros-ec,bma255";
- *                 status = "okay";
- *                         :
- *                         :
- *         };
- *
- *	   base_accel: base-accel {
- *                 compatible = "cros-ec,bmi260";
- *                 status = "okay";
- *                      :
- *                      :
- *         };
- * };
- */
-#ifdef CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_LID	SENSOR_ID(DT_NODELABEL(lid_accel))
-#define CONFIG_LID_ANGLE_SENSOR_BASE	SENSOR_ID(DT_NODELABEL(base_accel))
-#endif
-
-/*
- * Get the sensors running in force mode from DT and create a bit mask for it.
- *
- * e.g) lid accel and als_clear are in accel_force_mode. The macro below finds
- *      the corresponding bit for each sensor in bit mask and set it.
- * motionsense-sensor-info {
- *        compatible = "cros-ec,motionsense-sensor-info";
- *
- *        // list of sensors in force mode
- *        accel-force-mode-sensors = <&lid_accel &als_clear>;
- * };
- */
-#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, accel_force_mode_sensors)
-#define SENSOR_IN_FORCE_MODE(i, id)					\
-	| BIT(SENSOR_ID(DT_PHANDLE_BY_IDX(id, accel_force_mode_sensors, i)))
-#define CONFIG_ACCEL_FORCE_MODE_MASK					\
-	(0 UTIL_LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE,			\
-		accel_force_mode_sensors), SENSOR_IN_FORCE_MODE,	\
-		SENSOR_INFO_NODE))
-#endif
-
-#endif /* __CROS_EC_MOTIONSENSE_SENSORS_H */
diff --git a/zephyr/shim/include/mpu.h b/zephyr/shim/include/mpu.h
deleted file mode 100644
index 3555ef0db1..0000000000
--- a/zephyr/shim/include/mpu.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_MPU_H
-#define __CROS_EC_MPU_H
-
-/* This matches up with core/cortex-m/include/mpu.h */
-
-/* Location of iram.text */
-extern char __iram_text_start;
-extern char __iram_text_end;
-
-/** Enable MPU */
-void mpu_enable(void);
-
-/**
- * Returns the value of MPU type register
- *
- * @returns 0 for now (always)
- */
-uint32_t mpu_get_type(void);
-
-/** Protect RAM from code execution */
-int mpu_protect_data_ram(void);
-
-/** Protect code RAM from being overwritten */
-int mpu_protect_code_ram(void);
-
-/** Protect internal mapped flash memory from code execution */
-int mpu_lock_ro_flash(void);
-int mpu_lock_rw_flash(void);
-
-#endif /* __CROS_EC_CPU_H */
diff --git a/zephyr/shim/include/pwm/pwm.h b/zephyr/shim/include/pwm/pwm.h
deleted file mode 100644
index 1bf4685837..0000000000
--- a/zephyr/shim/include/pwm/pwm.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_SHIM_INCLUDE_PWM_PWM_H_
-#define ZEPHYR_SHIM_INCLUDE_PWM_PWM_H_
-
-#include <device.h>
-#include <devicetree.h>
-
-#if DT_NODE_EXISTS(DT_PATH(named_pwms))
-
-#define PWM_CHANNEL(id) DT_CAT(PWM_, id)
-#define PWM_CHANNEL_WITH_COMMA(id) PWM_CHANNEL(id),
-
-enum pwm_channel {
-	DT_FOREACH_CHILD(DT_PATH(named_pwms), PWM_CHANNEL_WITH_COMMA)
-		PWM_CH_COUNT,
-};
-
-#define NAMED_PWM(name) PWM_CHANNEL(DT_PATH(named_pwms, name))
-
-#endif /* named_pwms */
-
-#endif /* ZEPHYR_SHIM_INCLUDE_PWM_PWM_H_ */
diff --git a/zephyr/shim/include/registers.h b/zephyr/shim/include/registers.h
deleted file mode 100644
index b693733a21..0000000000
--- a/zephyr/shim/include/registers.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-/*
- * This file is left intentionally blank. It is required since many of the
- * shimmed files from platform/ec/common include it. Normally, this file
- * would define chip specific registers and would reside under
- * platform/ec/chip/...
- */
-
-#endif /* __CROS_EC_REGISTERS_H */
diff --git a/zephyr/shim/include/shimmed_task_id.h b/zephyr/shim/include/shimmed_task_id.h
deleted file mode 100644
index f56edf0806..0000000000
--- a/zephyr/shim/include/shimmed_task_id.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SHIMMED_TASK_ID_H
-#define __CROS_EC_SHIMMED_TASK_ID_H
-
-#include "common.h"
-
-/* Task identifier (8 bits) */
-typedef uint8_t task_id_t;
-
-/*
- * Highest priority on bottom -- same as in platform/ec. List of CROS_EC_TASK
- * items. See CONFIG_TASK_LIST in platform/ec's config.h for more information.
- * For tests that want their own custom tasks, use CONFIG_HAS_TEST_TASKS and not
- * CONFIG_SHIMMED_TASKS.
- */
-#ifdef CONFIG_SHIMMED_TASKS
-#define CROS_EC_TASK_LIST                                                 \
-	COND_CODE_1(HAS_TASK_HOOKS,                                       \
-		     (CROS_EC_TASK(HOOKS, hook_task, 0,                   \
-				   CONFIG_TASK_HOOKS_STACK_SIZE)), ())    \
-	COND_CODE_1(HAS_TASK_CHG_RAMP,                                    \
-		     (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0,            \
-				   CONFIG_TASK_CHG_RAMP_STACK_SIZE)), ()) \
-	COND_CODE_1(HAS_TASK_USB_CHG_P0,                                  \
-		     (CROS_EC_TASK(USB_CHG_P0, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_USB_CHG_P1,                                  \
-		     (CROS_EC_TASK(USB_CHG_P1, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_USB_CHG_P2,                                  \
-		     (CROS_EC_TASK(USB_CHG_P2, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_CHARGER,                                     \
-		     (CROS_EC_TASK(CHARGER, charger_task, 0,              \
-				   CONFIG_TASK_CHARGER_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_CHIPSET,                                     \
-		     (CROS_EC_TASK(CHIPSET, chipset_task, 0,              \
-				   CONFIG_TASK_CHIPSET_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_MOTIONSENSE,                                     \
-		     (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0,         \
-				   CONFIG_TASK_MOTIONSENSE_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_HOSTCMD,                                     \
-		     (CROS_EC_TASK(HOSTCMD, host_command_task, 0,         \
-				   CONFIG_TASK_HOSTCMD_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_KEYPROTO,                                    \
-		     (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0,   \
-				   CONFIG_TASK_KEYPROTO_STACK_SIZE)), ()) \
-	COND_CODE_1(HAS_TASK_POWERBTN,                                    \
-		     (CROS_EC_TASK(POWERBTN, power_button_task, 0,        \
-				   CONFIG_TASK_POWERBTN_STACK_SIZE)), ()) \
-	COND_CODE_1(HAS_TASK_KEYSCAN,                                     \
-		     (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0,        \
-				   CONFIG_TASK_KEYSCAN_STACK_SIZE)), ())  \
-	COND_CODE_1(HAS_TASK_PD_C0,                                       \
-		     (CROS_EC_TASK(PD_C0, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE)), ())       \
-	COND_CODE_1(HAS_TASK_PD_C1,                                       \
-		     (CROS_EC_TASK(PD_C1, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE)), ())       \
-	COND_CODE_1(HAS_TASK_PD_C2,                                       \
-		     (CROS_EC_TASK(PD_C2, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE)), ())       \
-	COND_CODE_1(HAS_TASK_PD_C3,                                       \
-		     (CROS_EC_TASK(PD_C3, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE)), ())       \
-	COND_CODE_1(HAS_TASK_PD_INT_C0,                                   \
-		     (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE)), ())   \
-	COND_CODE_1(HAS_TASK_PD_INT_C1,                                   \
-		     (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE)), ())   \
-	COND_CODE_1(HAS_TASK_PD_INT_C2,                                   \
-		     (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE)), ())   \
-	COND_CODE_1(HAS_TASK_PD_INT_C3,                                   \
-		     (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE)), ())
-#elif defined(CONFIG_HAS_TEST_TASKS)
-#include "shimmed_test_tasks.h"
-/*
- * There are two different ways to define a task list (because historical
- * reasons). Applications use CROS_EC_TASK_LIST to define their tasks, while
- * unit tests that need additional tasks use CONFIG_TEST_TASK_LIST. For
- * shimming a unit test, define CROS_EC_TASk_LIST as whatever
- * CONFIG_TEST_TASK_LIST expands to.
- */
-#if defined(CONFIG_TEST_TASK_LIST) && !defined(CROS_EC_TASK_LIST)
-#define CROS_EC_TASK_LIST CONFIG_TEST_TASK_LIST
-#endif /* CONFIG_TEST_TASK_LIST && !CROS_EC_TASK_LIST */
-#endif /* !CONFIG_ZTEST */
-
-#ifndef CROS_EC_TASK_LIST
-#define CROS_EC_TASK_LIST
-#endif /* CROS_EC_TASK_LIST */
-
-/*
- * Define the task_ids globally for all shimmed platform/ec code to use.
- * Note that unit test task lists use TASK_TEST, which we can just alias
- * into a regular CROS_EC_TASK.
- */
-#define CROS_EC_TASK(name, ...) TASK_ID_##name,
-#define TASK_TEST(name, ...) CROS_EC_TASK(name)
-enum {
-	TASK_ID_IDLE = -1, /* We don't shim the idle task */
-	CROS_EC_TASK_LIST
-#ifdef TEST_BUILD
-	TASK_ID_TEST_RUNNER,
-#endif
-	TASK_ID_COUNT,
-	TASK_ID_INVALID = 0xff, /* Unable to find the task */
-};
-#undef CROS_EC_TASK
-#undef TASK_TEST
-
-#endif /* __CROS_EC_SHIMMED_TASK_ID_H */
diff --git a/zephyr/shim/include/shimmed_tasks.h b/zephyr/shim/include/shimmed_tasks.h
deleted file mode 100644
index 631b3fcb16..0000000000
--- a/zephyr/shim/include/shimmed_tasks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SHIMMED_TASKS_H
-#define __CROS_EC_SHIMMED_TASKS_H
-
-#ifdef CONFIG_HAS_TASK_CHARGER
-#define HAS_TASK_CHARGER 1
-#endif /* CONFIG_HAS_TASK_CHARGER */
-
-#ifdef CONFIG_HAS_TASK_CHG_RAMP
-#define HAS_TASK_CHG_RAMP 1
-#endif /* CONFIG_HAS_TASK_CHG_RAMP */
-
-#ifdef CONFIG_HAS_TASK_CHIPSET
-#define HAS_TASK_CHIPSET 1
-#endif /* CONFIG_HAS_TASK_CHIPSET */
-
-#ifdef CONFIG_HAS_TASK_HOOKS
-#define HAS_TASK_HOOKS 1
-#endif /* CONFIG_HAS_TASK_HOOKS */
-
-#ifdef CONFIG_HAS_TASK_HOSTCMD
-#define HAS_TASK_HOSTCMD 1
-#define CONFIG_HOSTCMD_EVENTS
-#endif /* CONFIG_HAS_TASK_HOSTCMD */
-
-#ifdef CONFIG_HAS_TASK_KEYSCAN
-#define HAS_TASK_KEYSCAN 1
-#endif /* CONFIG_HAS_TASK_KEYSCAN */
-
-#ifdef CONFIG_HAS_TASK_KEYPROTO
-#define HAS_TASK_KEYPROTO 1
-#endif /* CONFIG_HAS_TASK_KEYPROTO */
-
-#ifdef CONFIG_HAS_TASK_MOTIONSENSE
-#define HAS_TASK_MOTIONSENSE 1
-#endif /* CONFIG_HAS_TASK_MOTIONSENSE */
-
-#ifdef CONFIG_HAS_TASK_PD_C0
-#define HAS_TASK_PD_C0 1
-#endif /* CONFIG_HAS_TASK_PD_C0 */
-
-#ifdef CONFIG_HAS_TASK_PD_C1
-#define HAS_TASK_PD_C1 1
-#endif /* CONFIG_HAS_TASK_PD_C1 */
-
-#ifdef CONFIG_HAS_TASK_PD_C2
-#define HAS_TASK_PD_C2 1
-#endif /* CONFIG_HAS_TASK_PD_C2 */
-
-#ifdef CONFIG_HAS_TASK_PD_C3
-#define HAS_TASK_PD_C3 1
-#endif /* CONFIG_HAS_TASK_PD_C3 */
-
-#ifdef CONFIG_HAS_TASK_PD_INT_C0
-#define HAS_TASK_PD_INT_C0 1
-#endif /* CONFIG_HAS_TASK_PD_INT_C0 */
-
-#ifdef CONFIG_HAS_TASK_PD_INT_C1
-#define HAS_TASK_PD_INT_C1 1
-#endif /* CONFIG_HAS_TASK_PD_INT_C1 */
-
-#ifdef CONFIG_HAS_TASK_PD_INT_C2
-#define HAS_TASK_PD_INT_C2 1
-#endif /* CONFIG_HAS_TASK_PD_INT_C2 */
-
-#ifdef CONFIG_HAS_TASK_PD_INT_C3
-#define HAS_TASK_PD_INT_C3 1
-#endif /* CONFIG_HAS_TASK_PD_INT_C3 */
-
-#ifdef CONFIG_HAS_TASK_POWERBTN
-#define HAS_TASK_POWERBTN 1
-#endif /* CONFIG_HAS_TASK_POWERBTN */
-
-#ifdef CONFIG_HAS_TASK_USB_CHG_P0
-#define HAS_TASK_USB_CHG_P0 1
-#endif /* CONFIG_HAS_TASK_USB_CHG_P0 */
-
-#ifdef CONFIG_HAS_TASK_USB_CHG_P1
-#define HAS_TASK_USB_CHG_P1 1
-#endif /* CONFIG_HAS_TASK_USB_CHG_P1 */
-
-#ifdef CONFIG_HAS_TASK_USB_CHG_P2
-#define HAS_TASK_USB_CHG_P2 1
-#endif /* CONFIG_HAS_TASK_USB_CHG_P2 */
-
-#endif /* __CROS_EC_SHIMMED_TASKS_H */
diff --git a/zephyr/shim/include/temp_sensor/temp_sensor.h b/zephyr/shim/include/temp_sensor/temp_sensor.h
deleted file mode 100644
index b0cadd4303..0000000000
--- a/zephyr/shim/include/temp_sensor/temp_sensor.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_
-#define ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_
-
-#include <devicetree.h>
-
-#ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR
-
-#define ZSHIM_TEMP_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name)
-#define TEMP_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_TEMP_SENSOR_ID(node_id),
-
-enum temp_sensor_id {
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors),
-			 TEMP_SENSOR_ID_WITH_COMMA)
-#endif /* named_temp_sensors */
-	TEMP_SENSOR_COUNT
-};
-
-#undef TEMP_SENSOR_ID_WITH_COMMA
-
-#endif /* CONFIG_PLATFORM_EC_TEMP_SENSOR */
-
-#endif /* ZEPHYR_SHIM_INCLUDE_TEMP_SENSOR_TEMP_SENSOR_H_ */
diff --git a/zephyr/shim/include/zephyr_adc.h b/zephyr/shim/include/zephyr_adc.h
deleted file mode 100644
index 7c0f3f3232..0000000000
--- a/zephyr/shim/include/zephyr_adc.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ZEPHYR_ADC_H
-#define __CROS_EC_ZEPHYR_ADC_H
-
-#include <drivers/adc.h>
-
-#ifdef CONFIG_PLATFORM_EC_ADC
-
-#define ZSHIM_ADC_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name)
-#define ADC_ID_WITH_COMMA(node_id)    ZSHIM_ADC_ID(node_id),
-
-enum adc_channel {
-#if DT_NODE_EXISTS(DT_INST(0, named_adc_channels))
-	DT_FOREACH_CHILD(DT_INST(0, named_adc_channels), ADC_ID_WITH_COMMA)
-#endif /* named_adc_channels */
-	ADC_CH_COUNT
-};
-
-#undef ADC_ID_WITH_COMMA
-
-struct adc_t {
-	const char *name;
-	uint8_t input_ch;
-	int factor_mul;
-	int factor_div;
-	struct adc_channel_cfg channel_cfg;
-};
-
-extern const struct adc_t adc_channels[];
-#else
-/* Empty declaration to avoid warnings if adc.h is included */
-enum adc_channel {
-	ADC_CH_COUNT
-};
-#endif /* CONFIG_PLATFORM_EC_ADC */
-
-#endif /* __CROS_EC_ZEPHYR_ADC_H */
diff --git a/zephyr/shim/include/zephyr_console_shim.h b/zephyr/shim/include/zephyr_console_shim.h
deleted file mode 100644
index b3c1f23922..0000000000
--- a/zephyr/shim/include/zephyr_console_shim.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ZEPHYR_CONSOLE_SHIM_H
-#define __CROS_EC_ZEPHYR_CONSOLE_SHIM_H
-
-#include <shell/shell.h>
-
-struct zephyr_console_command {
-	/* Handler for the command.  argv[0] will be the command name. */
-	int (*handler)(int argc, char **argv);
-#ifdef CONFIG_SHELL_HELP
-	/* Description of args */
-	const char *argdesc;
-	/* Short help for command */
-	const char *help;
-#endif
-};
-
-#ifdef CONFIG_SHELL_HELP
-#define _HELP_ARGS(A, H) \
-	.argdesc = A,     \
-	.help = H,
-#else
-#define _HELP_ARGS(A, H)
-#endif
-
-/**
- * zshim_run_ec_console_command() - Dispatch a CrOS EC console command
- * using Zephyr's shell
- *
- * @command:		Pointer to a struct zephyr_console_command
- * @argc:		The number of command line arguments.
- * @argv:		The NULL-terminated list of arguments.
- *
- * Return: the return value from the handler.
- */
-int zshim_run_ec_console_command(const struct zephyr_console_command *command,
-				 size_t argc, char **argv);
-
-/* Internal wrappers for DECLARE_CONSOLE_COMMAND_* macros. */
-#define _ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,       \
-				     WRAPPER_ID, ENTRY_ID)                  \
-	static const struct zephyr_console_command ENTRY_ID = {             \
-		.handler = ROUTINE_ID,                                      \
-		_HELP_ARGS(ARGDESC, HELP)                                   \
-	};                                                                  \
-	static int WRAPPER_ID(const struct shell *shell, size_t argc,       \
-			      char **argv)                                  \
-	{                                                                   \
-		return zshim_run_ec_console_command(&ENTRY_ID, argc, argv); \
-	}                                                                   \
-	SHELL_CMD_ARG_REGISTER(NAME, NULL, HELP, WRAPPER_ID, 0,             \
-			       SHELL_OPT_ARG_MAX)
-
-#define _ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE_ID, ARGDESC, HELP)        \
-	_ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,      \
-				     UTIL_CAT(zshim_wrapper_, ROUTINE_ID), \
-				     UTIL_CAT(zshim_entry_, ROUTINE_ID))
-
-/* These macros mirror the macros provided by the CrOS EC. */
-#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
-	_ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE, ARGDESC, HELP)
-
-/*
- * TODO(jrosenth): implement flags and restricted commands?  We just
- * discard this in the shim layer for now.
- */
-#define DECLARE_CONSOLE_COMMAND_FLAGS(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \
-	_ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE, ARGDESC, HELP)
-#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
-	_ZEPHYR_SHELL_COMMAND_SHIM(NAME, ROUTINE, ARGDESC, HELP)
-
-/**
- * console_buf_notify_chars() - Notify the console host command buffer
- * of bytes on the console.
- *
- * @s:			The pointer to the string.
- * @len:		The size of the string.
- */
-void console_buf_notify_chars(const char *s, size_t len);
-
-#endif /* __CROS_EC_ZEPHYR_CONSOLE_SHIM_H */
diff --git a/zephyr/shim/include/zephyr_espi_shim.h b/zephyr/shim/include/zephyr_espi_shim.h
deleted file mode 100644
index a7b151cec8..0000000000
--- a/zephyr/shim/include/zephyr_espi_shim.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_ZEPHYR_ESPI_SHIM_H
-#define __CROS_EC_ZEPHYR_ESPI_SHIM_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/**
- * zephyr_shim_setup_espi() - initialize eSPI device
- *
- * Return: 0 upon success, or <0 upon failure.
- */
-int zephyr_shim_setup_espi(void);
-
-/**
- * Check if the message is an ACPI command.
- *
- * @param data The full ACPI event data.
- * @return True if the message is a command.
- */
-bool is_acpi_command(uint32_t data);
-
-/**
- * Get the value component of the ACPI message.
- *
- * @param data The full ACPI event data.
- * @return The value component of the ACPI message.
- */
-uint32_t get_acpi_value(uint32_t data);
-
-/**
- * Check if the 8042 event data contains an input-buffer-full (IBF) event.
- *
- * @param data The full 8042 event data.
- * @return True if the data contains an IBF event.
- */
-bool is_8042_ibf(uint32_t data);
-
-/**
- * Check if the 8042 event data contains an output-buffer-empty (OBE) event.
- *
- * @param data The full 8042 event data.
- * @return True if the data contains an OBE event.
- */
-bool is_8042_obe(uint32_t data);
-
-/**
- * Get the type of 8042 message.
- *
- * @param data The full 8042 event data.
- * @return The type component of the message.
- */
-uint32_t get_8042_type(uint32_t data);
-
-/**
- * Get the data from an 8042 message.
- *
- * @param data The full 8042 event data.
- * @return The data component of the message.
- */
-uint32_t get_8042_data(uint32_t data);
-
-#endif /* __CROS_EC_ZEPHYR_ESPI_SHIM_H */
diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h
deleted file mode 100644
index 6c90db81f4..0000000000
--- a/zephyr/shim/include/zephyr_gpio_signal.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if !defined(__CROS_EC_GPIO_SIGNAL_H) || defined(__CROS_EC_ZEPHYR_GPIO_SIGNAL_H)
-#error "This file must only be included from gpio_signal.h. Include gpio_signal.h directly."
-#endif
-#define __CROS_EC_ZEPHYR_GPIO_SIGNAL_H
-
-#include <devicetree.h>
-#include <toolchain.h>
-
-#define GPIO_SIGNAL(id) DT_STRING_UPPER_TOKEN(id, enum_name)
-#define GPIO_SIGNAL_WITH_COMMA(id) \
-	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), (GPIO_SIGNAL(id), ), ())
-enum gpio_signal {
-	GPIO_UNIMPLEMENTED = -1,
-#if DT_NODE_EXISTS(DT_PATH(named_gpios))
-	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_SIGNAL_WITH_COMMA)
-#endif
-	GPIO_COUNT,
-	GPIO_LIMIT = 0x0FFF,
-};
-#undef GPIO_SIGNAL_WITH_COMMA
-BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT);
-
-/** @brief Converts a node identifier under named gpios to enum
- *
- * Converts the specified node identifier name, which should be nested under
- * the named_gpios node, into the correct enum gpio_signal that can be used
- * with platform/ec gpio API
- */
-#define NAMED_GPIO(name) GPIO_SIGNAL(DT_PATH(named_gpios, name))
-
-/** @brief Obtain a named gpio enum from a label and property
- *
- * Obtains a valid enum gpio_signal that can be used with platform/ec gpio API
- * from the property of a labeled node. The property has to point to a
- * named_gpios node.
- */
-#define NAMED_GPIO_NODELABEL(label, prop) \
-	GPIO_SIGNAL(DT_PHANDLE(DT_NODELABEL(label), prop))
-
-/*
- * While we don't support IO expanders at the moment, multiple
- * platform/ec headers (e.g., espi.h) require some of these constants
- * to be defined.  Define them as a compatibility measure.
- */
-enum ioex_signal {
-	IOEX_SIGNAL_START = GPIO_LIMIT + 1,
-	IOEX_SIGNAL_END = IOEX_SIGNAL_START,
-	IOEX_LIMIT = 0x1FFF,
-};
-BUILD_ASSERT(IOEX_SIGNAL_END < IOEX_LIMIT);
-
-#define IOEX_COUNT (IOEX_SIGNAL_END - IOEX_SIGNAL_START)
diff --git a/zephyr/shim/include/zephyr_hooks_shim.h b/zephyr/shim/include/zephyr_hooks_shim.h
deleted file mode 100644
index 96dcf9d8f4..0000000000
--- a/zephyr/shim/include/zephyr_hooks_shim.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if !defined(__CROS_EC_HOOKS_H) || defined(__CROS_EC_ZEPHYR_HOOKS_SHIM_H)
-#error "This file must only be included from hooks.h. Include hooks.h directly."
-#endif
-#define __CROS_EC_ZEPHYR_HOOKS_SHIM_H
-
-#include <init.h>
-#include <kernel.h>
-#include <zephyr.h>
-
-#include "common.h"
-#include "cros_version.h"
-
-/**
- * The internal data structure stored for a deferred function.
- */
-struct deferred_data {
-	struct k_work_delayable *work;
-};
-
-/**
- * See include/hooks.h for documentation.
- */
-int hook_call_deferred(const struct deferred_data *data, int us);
-
-#define DECLARE_DEFERRED(routine)                                    \
-	K_WORK_DELAYABLE_DEFINE(routine##_work_data,                 \
-				(void (*)(struct k_work *))routine); \
-	__maybe_unused const struct deferred_data routine##_data = { \
-		.work = &routine##_work_data,                \
-	}
-
-/**
- * Internal linked-list structure used to store hook lists.
- */
-struct zephyr_shim_hook_list {
-	void (*routine)(void);
-	uint16_t priority; /* HOOK_PRIO_LAST = 9999 */
-	enum hook_type type;
-	struct zephyr_shim_hook_list *next;
-};
-
-/**
- * See include/hooks.h for documentation.
- */
-#define DECLARE_HOOK(_hooktype, _routine, _priority)             \
-	STRUCT_SECTION_ITERABLE(zephyr_shim_hook_list,           \
-			_cros_hook_##_hooktype##_##_routine) = { \
-		.type = _hooktype,                               \
-		.routine = _routine,                             \
-		.priority = _priority,                           \
-	}
diff --git a/zephyr/shim/include/zephyr_host_command.h b/zephyr/shim/include/zephyr_host_command.h
deleted file mode 100644
index ae8e1f9ee3..0000000000
--- a/zephyr/shim/include/zephyr_host_command.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if !defined(__CROS_EC_HOST_COMMAND_H) || \
-	defined(__CROS_EC_ZEPHYR_HOST_COMMAND_H)
-#error "This file must only be included from host_command.h. " \
-	"Include host_command.h directly"
-#endif
-#define __CROS_EC_ZEPHYR_HOST_COMMAND_H
-
-#include <init.h>
-
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD
-
-/**
- * See include/host_command.h for documentation.
- */
-#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask)            \
-	STRUCT_SECTION_ITERABLE(host_command, _cros_hcmd_##_command) = {   \
-		.command = _command,                                       \
-		.handler = _routine,                                       \
-		.version_mask = _version_mask,                             \
-	}
-#else /* !CONFIG_PLATFORM_EC_HOSTCMD */
-#ifdef __clang__
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)
-#else
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)         \
-	enum ec_status (routine)(struct host_cmd_handler_args *args) \
-		__attribute__((unused))
-#endif /* __clang__ */
-#endif /* CONFIG_PLATFORM_EC_HOSTCMD */
diff --git a/zephyr/shim/include/zephyr_mkbp_event.h b/zephyr/shim/include/zephyr_mkbp_event.h
deleted file mode 100644
index 159aebc8e1..0000000000
--- a/zephyr/shim/include/zephyr_mkbp_event.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#if !defined(__CROS_EC_MKBP_EVENT_H) || \
-	defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H)
-#error "This file must only be included from mkbp_event.h. " \
-	"Include mkbp_event.h directly"
-#endif
-#define __CROS_EC_ZEPHYR_MKBP_EVENT_H
-
-const struct mkbp_event_source *zephyr_find_mkbp_event_source(
-		uint8_t event_type);
-
-/**
- * See include/mkbp_event.h for documentation.
- */
-#define DECLARE_EVENT_SOURCE(_type, _func)                                     \
-	STRUCT_SECTION_ITERABLE(mkbp_event_source, _cros_evtsrc_##_func) = {   \
-		.event_type = _type,                                           \
-		.get_data = _func,                                             \
-	}
diff --git a/zephyr/shim/src/CMakeLists.txt b/zephyr/shim/src/CMakeLists.txt
deleted file mode 100644
index e30671c6d6..0000000000
--- a/zephyr/shim/src/CMakeLists.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-zephyr_library_sources(console.c)
-zephyr_library_sources(crc.c)
-zephyr_library_sources(gpio.c)
-zephyr_library_sources(gpio_id.c)
-
-if (DEFINED CONFIG_ARCH_POSIX)
-  zephyr_library_sources(ztest_system.c)
-else()
-  zephyr_library_sources(system.c)
-  zephyr_library_sources("${PLATFORM_EC}/common/system.c")
-endif()
-zephyr_library_sources_ifdef(no_libgcc                  libgcc_${ARCH}.S)
-
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ADC         adc.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE
-                                                            battery.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM  cbi.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_GPIO    cbi.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ESPI        espi.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN         fan.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FLASH_CROS  flash.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOOKS       hooks.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD     host_command.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE
-                                                            console_buffer.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD    keyboard_raw.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD    keyscan.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT  mkbp_event.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
-                                                            motionsense_sensors.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PANIC       panic.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM         pwm.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON  pwm_led.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_RTC         rtc.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCHCAP_GPIO
-															switchcap_gpio.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_SWITCHCAP_LN9310
-															switchcap_ln9310.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TEMP_SENSOR temp_sensors.c
-                                                            thermal.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_TIMER       hwtimer.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C         i2c.c)
-zephyr_library_sources_ifdef(CONFIG_SHIMMED_TASKS           tasks.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_WATCHDOG    watchdog.c)
diff --git a/zephyr/shim/src/adc.c b/zephyr/shim/src/adc.c
deleted file mode 100644
index 4f66774466..0000000000
--- a/zephyr/shim/src/adc.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <drivers/adc.h>
-#include <logging/log.h>
-#include "adc.h"
-#include "zephyr_adc.h"
-
-LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR);
-
-#define ADC_NODE DT_NODELABEL(adc0)
-const struct device *adc_dev;
-
-#define HAS_NAMED_ADC_CHANNELS DT_NODE_EXISTS(DT_INST(0, named_adc_channels))
-
-#if HAS_NAMED_ADC_CHANNELS
-#define ADC_CHANNEL_COMMA(node_id)                                        \
-	[ZSHIM_ADC_ID(node_id)] = {                                       \
-		.name = DT_LABEL(node_id),                                \
-		.input_ch = DT_PROP(node_id, channel),                    \
-		.factor_mul = DT_PROP(node_id, mul),                      \
-		.factor_div = DT_PROP(node_id, div),                      \
-		.channel_cfg = {                                          \
-			.channel_id = DT_PROP(node_id, channel),          \
-			.gain = DT_STRING_TOKEN(node_id, gain),           \
-			.reference = DT_STRING_TOKEN(node_id, reference), \
-			.acquisition_time =                               \
-				DT_PROP(node_id, acquisition_time),       \
-			.differential = DT_PROP(node_id, differential),   \
-		},                                                        \
-	},
-#ifdef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-struct adc_t adc_channels[] = { DT_FOREACH_CHILD(
-	DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) };
-#else
-const struct adc_t adc_channels[] = { DT_FOREACH_CHILD(
-	DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) };
-#endif
-#endif /* named_adc_channels */
-
-static int init_device_bindings(const struct device *device)
-{
-	ARG_UNUSED(device);
-	adc_dev = DEVICE_DT_GET(ADC_NODE);
-
-	if (!device_is_ready(adc_dev)) {
-		LOG_ERR("Error: device %s is not ready", adc_dev->name);
-		return -1;
-	}
-
-#if HAS_NAMED_ADC_CHANNELS
-	for (int i = 0; i < ARRAY_SIZE(adc_channels); i++)
-		adc_channel_setup(adc_dev, &adc_channels[i].channel_cfg);
-#endif
-
-	return 0;
-}
-SYS_INIT(init_device_bindings, POST_KERNEL, 51);
-
-int adc_read_channel(enum adc_channel ch)
-{
-	int ret = 0, rv;
-	struct adc_sequence seq = {
-		.options = NULL,
-		.channels = BIT(adc_channels[ch].input_ch),
-		.buffer = &ret,
-		.buffer_size = sizeof(ret),
-		.resolution = CONFIG_PLATFORM_EC_ADC_RESOLUTION,
-		.oversampling = CONFIG_PLATFORM_EC_ADC_OVERSAMPLING,
-		.calibrate = false,
-	};
-
-	rv = adc_read(adc_dev, &seq);
-	if (rv)
-		return rv;
-
-	adc_raw_to_millivolts(adc_ref_internal(adc_dev), ADC_GAIN_1,
-			      CONFIG_PLATFORM_EC_ADC_RESOLUTION, &ret);
-	ret = (ret * adc_channels[ch].factor_mul) / adc_channels[ch].factor_div;
-	return ret;
-}
diff --git a/zephyr/shim/src/battery.c b/zephyr/shim/src/battery.c
deleted file mode 100644
index 6c4f211eda..0000000000
--- a/zephyr/shim/src/battery.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include<devicetree.h>
-#include"battery_fuel_gauge.h"
-
-#if DT_NODE_EXISTS(DT_PATH(batteries))
-
-#define NODE_FUEL_GAUGE(node) \
-{ \
-	.manuf_name = DT_PROP(node, manuf_name), \
-	.device_name = DT_PROP(node, device_name), \
-	.ship_mode = { \
-		.wb_support = DT_PROP_OR(node, ship_mode_wb_support, 0), \
-		.reg_addr = DT_PROP(node, ship_mode_reg_addr), \
-		.reg_data = DT_PROP(node, ship_mode_reg_data), \
-	}, \
-	.sleep_mode = { \
-		.sleep_supported = DT_PROP_OR(node, sleep_mode_supported, 0), \
-		.reg_addr = DT_PROP_OR(node, sleep_mode_reg_addr, 0), \
-		.reg_data = DT_PROP_OR(node, sleep_mode_reg_data, 0), \
-	}, \
-	.fet = { \
-		.mfgacc_support = DT_PROP_OR(node, fet_mgfacc_support, 0), \
-		.reg_addr = DT_PROP_OR(node, fet_reg_addr, 0), \
-		.reg_mask = DT_PROP(node, fet_reg_mask), \
-		.disconnect_val = DT_PROP(node, fet_disconnect_val), \
-		.cfet_mask = DT_PROP_OR(node, fet_cfet_mask, 0), \
-		.cfet_off_val = DT_PROP_OR(node, fet_cfet_off_val, 0), \
-	}, \
-	COND_CODE_1(UTIL_AND(IS_ENABLED(CONFIG_BATTERY_MEASURE_IMBALANCE), \
-			     DT_NODE_HAS_PROP(node, imbalance_mv)), \
-		(.imbalance_mv = DT_STRING_TOKEN(node, imbalance_mv),), ()) \
-},
-
-#define NODE_BATT_INFO(node) \
-{ \
-	.voltage_max = DT_PROP(node, voltage_max), \
-	.voltage_normal = DT_PROP(node, voltage_normal), \
-	.voltage_min = DT_PROP(node, voltage_min), \
-	.precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \
-	.precharge_current = DT_PROP_OR(node, precharge_current, 0), \
-	.start_charging_min_c = DT_PROP(node, start_charging_min_c), \
-	.start_charging_max_c = DT_PROP(node, start_charging_max_c), \
-	.charging_min_c = DT_PROP(node, charging_min_c), \
-	.charging_max_c = DT_PROP(node, charging_max_c), \
-	.discharging_min_c = DT_PROP(node, discharging_min_c), \
-	.discharging_max_c = DT_PROP(node, discharging_max_c), \
-},
-
-#define NODE_BATT_PARAMS(node) \
-{ \
-	.fuel_gauge = NODE_FUEL_GAUGE(node) \
-	.batt_info = NODE_BATT_INFO(node) \
-},
-
-const struct board_batt_params board_battery_info[] = {
-	DT_FOREACH_CHILD(DT_PATH(batteries), NODE_BATT_PARAMS)
-};
-
-#if DT_NODE_EXISTS(DT_NODELABEL(default_battery))
-#define BAT_ENUM(node) DT_CAT(BATTERY_, node)
-const enum battery_type DEFAULT_BATTERY_TYPE =
-	BATTERY_TYPE(DT_NODELABEL(default_battery));
-#endif
-
-#endif /* DT_NODE_EXISTS(DT_PATH(batteries)) */
diff --git a/zephyr/shim/src/cbi.c b/zephyr/shim/src/cbi.c
deleted file mode 100644
index e9d85b6088..0000000000
--- a/zephyr/shim/src/cbi.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <drivers/cros_cbi.h>
-#include <logging/log.h>
-#include "hooks.h"
-
-LOG_MODULE_REGISTER(shim_cbi, LOG_LEVEL_ERR);
-
-static void cbi_dev_init(void)
-{
-	const struct device *dev = device_get_binding(CROS_CBI_LABEL);
-
-	if (!dev)
-		LOG_ERR("Fail to find %s", CROS_CBI_LABEL);
-
-	cros_cbi_init(dev);
-}
-
-DECLARE_HOOK(HOOK_INIT, cbi_dev_init, HOOK_PRIO_FIRST);
diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c
deleted file mode 100644
index 3fc3896ec2..0000000000
--- a/zephyr/shim/src/console.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/uart.h>
-#include <shell/shell.h>
-#include <shell/shell_uart.h>
-#include <stdbool.h>
-#include <string.h>
-#include <sys/printk.h>
-#include <sys/ring_buffer.h>
-#include <zephyr.h>
-#include <logging/log.h>
-
-#include "console.h"
-#include "printf.h"
-#include "uart.h"
-#include "usb_console.h"
-#include "zephyr_console_shim.h"
-
-LOG_MODULE_REGISTER(shim_console, LOG_LEVEL_ERR);
-
-static const struct device *uart_shell_dev =
-	DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
-static const struct shell *shell_zephyr;
-static struct k_poll_signal shell_uninit_signal;
-static struct k_poll_signal shell_init_signal;
-RING_BUF_DECLARE(rx_buffer, CONFIG_UART_RX_BUF_SIZE);
-
-static void uart_rx_handle(const struct device *dev)
-{
-	static uint8_t scratch;
-	static uint8_t *data;
-	static uint32_t len, rd_len;
-
-	do {
-		/* Get some bytes on the ring buffer */
-		len = ring_buf_put_claim(&rx_buffer, &data, rx_buffer.size);
-		if (len > 0) {
-			/* Read from the FIFO up to `len` bytes */
-			rd_len = uart_fifo_read(dev, data, len);
-
-			/* Put `rd_len` bytes on the ring buffer */
-			ring_buf_put_finish(&rx_buffer, rd_len);
-		} else {
-			/*
-			 * There's no room on the ring buffer, throw away 1
-			 * byte.
-			 */
-			rd_len = uart_fifo_read(dev, &scratch, 1);
-		}
-	} while (rd_len != 0 && rd_len == len);
-}
-
-static void uart_callback(const struct device *dev, void *user_data)
-{
-	uart_irq_update(dev);
-
-	if (uart_irq_rx_ready(dev))
-		uart_rx_handle(dev);
-}
-
-static void shell_uninit_callback(const struct shell *shell, int res)
-{
-	if (!res) {
-		/* Set the new callback */
-		uart_irq_callback_user_data_set(uart_shell_dev, uart_callback,
-						NULL);
-
-		/*
-		 * Disable TX interrupts. We don't actually use TX but for some
-		 * reason none of this works without this line.
-		 */
-		uart_irq_tx_disable(uart_shell_dev);
-
-		/* Enable RX interrupts */
-		uart_irq_rx_enable(uart_shell_dev);
-	}
-
-	/* Notify the uninit signal that we finished */
-	k_poll_signal_raise(&shell_uninit_signal, res);
-}
-
-int uart_shell_stop(void)
-{
-	struct k_poll_event event = K_POLL_EVENT_INITIALIZER(
-		K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
-		&shell_uninit_signal);
-
-	/* Clear all pending input */
-	uart_clear_input();
-
-	/* Disable RX and TX interrupts */
-	uart_irq_rx_disable(uart_shell_dev);
-	uart_irq_tx_disable(uart_shell_dev);
-
-	/* Initialize the uninit signal */
-	k_poll_signal_init(&shell_uninit_signal);
-
-	/* Stop the shell */
-	shell_uninit(shell_backend_uart_get_ptr(), shell_uninit_callback);
-
-	/* Wait for the shell to be turned off, the signal will wake us */
-	k_poll(&event, 1, K_FOREVER);
-
-	/* Event was signaled, return the result */
-	return event.signal->result;
-}
-
-static void shell_init_from_work(struct k_work *work)
-{
-	bool log_backend = CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL > 0;
-	uint32_t level;
-	ARG_UNUSED(work);
-
-	if (CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL > LOG_LEVEL_DBG) {
-		level = CONFIG_LOG_MAX_LEVEL;
-	} else {
-		level = CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL;
-	}
-
-	/* Initialize the shell and re-enable both RX and TX */
-	shell_init(shell_backend_uart_get_ptr(), uart_shell_dev, false,
-		   log_backend, level);
-	uart_irq_rx_enable(uart_shell_dev);
-	uart_irq_tx_enable(uart_shell_dev);
-
-	/* Notify the init signal that initialization is complete */
-	k_poll_signal_raise(&shell_init_signal, 0);
-}
-
-void uart_shell_start(void)
-{
-	static struct k_work shell_init_work;
-	struct k_poll_event event = K_POLL_EVENT_INITIALIZER(
-		K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
-		&shell_init_signal);
-
-	/* Disable RX and TX interrupts */
-	uart_irq_rx_disable(uart_shell_dev);
-	uart_irq_tx_disable(uart_shell_dev);
-
-	/* Initialize k_work to call shell init (this makes it thread safe) */
-	k_work_init(&shell_init_work, shell_init_from_work);
-
-	/* Initialize the init signal to make sure we're read to listen */
-	k_poll_signal_init(&shell_init_signal);
-
-	/* Submit the work to be run by the kernel */
-	k_work_submit(&shell_init_work);
-
-	/* Wait for initialization to be run, the signal will wake us */
-	k_poll(&event, 1, K_FOREVER);
-}
-
-int zshim_run_ec_console_command(const struct zephyr_console_command *command,
-				 size_t argc, char **argv)
-{
-	/*
-	 * The Zephyr shell only displays the help string and not
-	 * the argument descriptor when passing "-h" or "--help".  Mimic the
-	 * cros-ec behavior by displaying both the user types "<command> help",
-	 */
-#ifdef CONFIG_SHELL_HELP
-	for (int i = 1; i < argc; i++) {
-		if (!command->help && !command->argdesc)
-			break;
-		if (!strcmp(argv[i], "help")) {
-			if (command->help)
-				printk("%s\n", command->help);
-			if (command->argdesc)
-				printk("Usage: %s\n", command->argdesc);
-			return 0;
-		}
-	}
-#endif
-
-	return command->handler(argc, argv);
-}
-
-#if defined(CONFIG_CONSOLE_CHANNEL) && DT_NODE_EXISTS(DT_PATH(ec_console))
-#define EC_CONSOLE DT_PATH(ec_console)
-
-static const char * const disabled_channels[] = DT_PROP(EC_CONSOLE, disabled);
-static const size_t disabled_channel_count = DT_PROP_LEN(EC_CONSOLE, disabled);
-static int init_ec_console(const struct device *unused)
-{
-	for (size_t i = 0; i < disabled_channel_count; i++)
-		console_channel_disable(disabled_channels[i]);
-
-	return 0;
-} SYS_INIT(init_ec_console, PRE_KERNEL_1, 50);
-#endif /* CONFIG_CONSOLE_CHANNEL && DT_NODE_EXISTS(DT_PATH(ec_console)) */
-
-static int init_ec_shell(const struct device *unused)
-{
-	shell_zephyr = shell_backend_uart_get_ptr();
-	return 0;
-} SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50);
-
-void uart_tx_start(void)
-{
-}
-
-int uart_tx_ready(void)
-{
-	return 1;
-}
-
-int uart_tx_char_raw(void *context, int c)
-{
-	uart_write_char(c);
-	return 0;
-}
-
-void uart_write_char(char c)
-{
-	printk("%c", c);
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE))
-		console_buf_notify_chars(&c, 1);
-}
-
-void uart_flush_output(void)
-{
-	shell_process(shell_zephyr);
-	uart_tx_flush();
-}
-
-void uart_tx_flush(void)
-{
-	while (!uart_irq_tx_complete(uart_shell_dev))
-		;
-}
-
-int uart_getc(void)
-{
-	uint8_t c;
-
-	if (ring_buf_get(&rx_buffer, &c, 1)) {
-		return c;
-	}
-	return -1;
-}
-
-void uart_clear_input(void)
-{
-	/* Clear any remaining shell processing. */
-	shell_process(shell_zephyr);
-	ring_buf_reset(&rx_buffer);
-}
-
-static void handle_sprintf_rv(int rv, size_t *len)
-{
-	if (rv < 0) {
-		LOG_ERR("Print buffer is too small");
-		*len = CONFIG_SHELL_PRINTF_BUFF_SIZE;
-	} else {
-		*len += rv;
-	}
-}
-
-static void zephyr_print(const char *buff, size_t size)
-{
-	/*
-	 * shell_* functions can not be used in ISRs so use printk instead.
-	 * Also, console_buf_notify_chars uses a mutex, which may not be
-	 * locked in ISRs.
-	 */
-	if (k_is_in_isr() || shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) {
-		printk("%s", buff);
-	} else {
-		/*
-		 * On some platforms, shell_* functions are not as fast
-		 * as printk and they need the added speed to avoid
-		 * timeouts.
-		 */
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_CONSOLE_USES_PRINTK))
-			printk("%s", buff);
-		else
-			shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", buff);
-		if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE))
-			console_buf_notify_chars(buff, size);
-	}
-}
-
-#if defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM)
-BUILD_ASSERT(0, "USB console is not supported with Zephyr");
-#endif /* defined(CONFIG_USB_CONSOLE) || defined(CONFIG_USB_CONSOLE_STREAM) */
-
-int cputs(enum console_channel channel, const char *outstr)
-{
-	/* Filter out inactive channels */
-	if (console_channel_is_disabled(channel))
-		return EC_SUCCESS;
-
-	zephyr_print(outstr, strlen(outstr));
-
-	return 0;
-}
-
-int cprintf(enum console_channel channel, const char *format, ...)
-{
-	int rv;
-	va_list args;
-	size_t len = 0;
-	char buff[CONFIG_SHELL_PRINTF_BUFF_SIZE];
-
-	/* Filter out inactive channels */
-	if (console_channel_is_disabled(channel))
-		return EC_SUCCESS;
-
-	va_start(args, format);
-	rv = crec_vsnprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, format, args);
-	va_end(args);
-	handle_sprintf_rv(rv, &len);
-
-	zephyr_print(buff, len);
-
-	return rv > 0 ? EC_SUCCESS : rv;
-}
-
-int cprints(enum console_channel channel, const char *format, ...)
-{
-	int rv;
-	va_list args;
-	char buff[CONFIG_SHELL_PRINTF_BUFF_SIZE];
-	size_t len = 0;
-
-	/* Filter out inactive channels */
-	if (console_channel_is_disabled(channel))
-		return EC_SUCCESS;
-
-	rv = crec_snprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, "[%pT ",
-			 PRINTF_TIMESTAMP_NOW);
-	handle_sprintf_rv(rv, &len);
-
-	va_start(args, format);
-	rv = crec_vsnprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
-			  format, args);
-	va_end(args);
-	handle_sprintf_rv(rv, &len);
-
-	rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
-			 "]\n");
-	handle_sprintf_rv(rv, &len);
-
-	zephyr_print(buff, len);
-
-	return rv > 0 ? EC_SUCCESS : rv;
-}
diff --git a/zephyr/shim/src/console_buffer.c b/zephyr/shim/src/console_buffer.c
deleted file mode 100644
index 427ae47768..0000000000
--- a/zephyr/shim/src/console_buffer.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <zephyr.h>
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-
-static char console_buf[CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE];
-static uint32_t previous_snapshot_idx;
-static uint32_t current_snapshot_idx;
-static uint32_t tail_idx;
-
-static inline uint32_t next_idx(uint32_t cur_idx)
-{
-	return (cur_idx + 1) % ARRAY_SIZE(console_buf);
-}
-
-K_MUTEX_DEFINE(console_write_lock);
-
-void console_buf_notify_chars(const char *s, size_t len)
-{
-	/*
-	 * This is just notifying of console characters for debugging
-	 * output, so if we are unable to lock the mutex immediately,
-	 * then just drop the string.
-	 */
-	if (k_mutex_lock(&console_write_lock, K_NO_WAIT))
-		return;
-	/* We got the mutex. */
-	while (len--) {
-		/* Don't copy null byte into buffer */
-		if (!(*s))
-			continue;
-
-		uint32_t new_tail = next_idx(tail_idx);
-
-		/* Check if we are starting to overwrite our snapshot
-		 * heads
-		 */
-		if (new_tail == previous_snapshot_idx)
-			previous_snapshot_idx =
-				next_idx(previous_snapshot_idx);
-		if (new_tail == current_snapshot_idx)
-			current_snapshot_idx =
-				next_idx(current_snapshot_idx);
-
-		console_buf[new_tail] = *s++;
-		tail_idx = new_tail;
-	}
-	k_mutex_unlock(&console_write_lock);
-}
-
-enum ec_status uart_console_read_buffer_init(void)
-{
-	if (k_mutex_lock(&console_write_lock, K_MSEC(100)))
-		/* Failed to acquire console buffer mutex */
-		return EC_RES_TIMEOUT;
-
-	previous_snapshot_idx = current_snapshot_idx;
-	current_snapshot_idx = tail_idx;
-
-	k_mutex_unlock(&console_write_lock);
-
-	return EC_RES_SUCCESS;
-}
-
-int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
-			     uint16_t *write_count_out)
-{
-	uint32_t *head;
-	uint16_t write_count = 0;
-
-	switch (type) {
-	case CONSOLE_READ_NEXT:
-		/* Start from beginning of latest snapshot */
-		head = &current_snapshot_idx;
-		break;
-	case CONSOLE_READ_RECENT:
-		/* Start from end of previous snapshot */
-		head = &previous_snapshot_idx;
-		break;
-	default:
-		return EC_RES_INVALID_PARAM;
-	}
-
-	/* We need to make sure we have room for at least the null byte */
-	if (dest_size == 0)
-		return EC_RES_INVALID_PARAM;
-
-	if (k_mutex_lock(&console_write_lock, K_MSEC(100)))
-		/* Failed to acquire console buffer mutex */
-		return EC_RES_TIMEOUT;
-
-	if (*head == tail_idx) {
-		/* No new data, return empty response */
-		k_mutex_unlock(&console_write_lock);
-		return EC_RES_SUCCESS;
-	}
-
-	do {
-		if (write_count >= dest_size - 1)
-			/* Buffer is full, minus the space for a null byte */
-			break;
-
-		dest[write_count] = console_buf[*head];
-		write_count++;
-		*head = next_idx(*head);
-	} while (*head != tail_idx);
-
-	dest[write_count] = '\0';
-	write_count++;
-
-	*write_count_out = write_count;
-	k_mutex_unlock(&console_write_lock);
-
-	return EC_RES_SUCCESS;
-}
-
-/* ECOS uart buffer, putc is blocking instead. */
-int uart_buffer_full(void)
-{
-	return false;
-}
diff --git a/zephyr/shim/src/crc.c b/zephyr/shim/src/crc.c
deleted file mode 100644
index 5c726619ee..0000000000
--- a/zephyr/shim/src/crc.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <sys/crc.h>
-
-#include "crc8.h"
-
-/* Polynomial representation for x^8 + x^2 + x + 1 is 0x07 */
-#define SMBUS_POLYNOMIAL 0x07
-
-inline uint8_t cros_crc8(const uint8_t *data, int len)
-{
-	return crc8(data, len, SMBUS_POLYNOMIAL, 0, false);
-}
-
-uint8_t cros_crc8_arg(const uint8_t *data, int len, uint8_t previous_crc)
-{
-	return crc8(data, len, SMBUS_POLYNOMIAL, previous_crc, false);
-}
diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c
deleted file mode 100644
index c064bd6157..0000000000
--- a/zephyr/shim/src/espi.c
+++ /dev/null
@@ -1,563 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <atomic.h>
-#include <device.h>
-#include <drivers/espi.h>
-#include <logging/log.h>
-#include <kernel.h>
-#include <stdint.h>
-#include <zephyr.h>
-
-#include "acpi.h"
-#include "chipset.h"
-#include "common.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i8042_protocol.h"
-#include "keyboard_protocol.h"
-#include "lpc.h"
-#include "port80.h"
-#include "power.h"
-#include "task.h"
-#include "timer.h"
-#include "zephyr_espi_shim.h"
-
-#define VWIRE_PULSE_TRIGGER_TIME 65
-
-LOG_MODULE_REGISTER(espi_shim, CONFIG_ESPI_LOG_LEVEL);
-
-/* host command packet handler structure */
-static struct host_packet lpc_packet;
-/*
- * For the eSPI host command, request & response use the same share memory.
- * This is for input request temp buffer.
- */
-static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
-static bool init_done;
-
-/*
- * A mapping of platform/ec signals to Zephyr virtual wires.
- *
- * This should be a macro which takes a parameter M, and does a
- * functional application of M to 2-tuples of (platform/ec signal,
- * zephyr vwire).
- */
-#define VW_SIGNAL_TRANSLATION_LIST(M)                                      \
-	M(VW_SLP_S3_L, ESPI_VWIRE_SIGNAL_SLP_S3)                           \
-	M(VW_SLP_S4_L, ESPI_VWIRE_SIGNAL_SLP_S4)                           \
-	M(VW_SLP_S5_L, ESPI_VWIRE_SIGNAL_SLP_S5)                           \
-	M(VW_SUS_STAT_L, ESPI_VWIRE_SIGNAL_SUS_STAT)                       \
-	M(VW_PLTRST_L, ESPI_VWIRE_SIGNAL_PLTRST)                           \
-	M(VW_OOB_RST_WARN, ESPI_VWIRE_SIGNAL_OOB_RST_WARN)                 \
-	M(VW_OOB_RST_ACK, ESPI_VWIRE_SIGNAL_OOB_RST_ACK)                   \
-	M(VW_WAKE_L, ESPI_VWIRE_SIGNAL_WAKE)                               \
-	M(VW_PME_L, ESPI_VWIRE_SIGNAL_PME)                                 \
-	M(VW_ERROR_FATAL, ESPI_VWIRE_SIGNAL_ERR_FATAL)                     \
-	M(VW_ERROR_NON_FATAL, ESPI_VWIRE_SIGNAL_ERR_NON_FATAL)             \
-	M(VW_PERIPHERAL_BTLD_STATUS_DONE, ESPI_VWIRE_SIGNAL_SLV_BOOT_DONE) \
-	M(VW_SCI_L, ESPI_VWIRE_SIGNAL_SCI)                                 \
-	M(VW_SMI_L, ESPI_VWIRE_SIGNAL_SMI)                                 \
-	M(VW_HOST_RST_ACK, ESPI_VWIRE_SIGNAL_HOST_RST_ACK)                 \
-	M(VW_HOST_RST_WARN, ESPI_VWIRE_SIGNAL_HOST_RST_WARN)               \
-	M(VW_SUS_ACK, ESPI_VWIRE_SIGNAL_SUS_ACK)                           \
-	M(VW_SUS_WARN_L, ESPI_VWIRE_SIGNAL_SUS_WARN)                       \
-	M(VW_SUS_PWRDN_ACK_L, ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK)             \
-	M(VW_SLP_A_L, ESPI_VWIRE_SIGNAL_SLP_A)                             \
-	M(VW_SLP_LAN, ESPI_VWIRE_SIGNAL_SLP_LAN)                           \
-	M(VW_SLP_WLAN, ESPI_VWIRE_SIGNAL_SLP_WLAN)
-
-/*
- * These two macros are intended to be used as as the M parameter to
- * the list above, generating case statements returning the
- * translation for the first parameter to the second, and the second
- * to the first, respectively.
- */
-#define CASE_CROS_TO_ZEPHYR(A, B) \
-	case A:                   \
-		return B;
-#define CASE_ZEPHYR_TO_CROS(A, B) CASE_CROS_TO_ZEPHYR(B, A)
-
-/* Translate a platform/ec signal to a Zephyr signal */
-static enum espi_vwire_signal signal_to_zephyr_vwire(enum espi_vw_signal signal)
-{
-	switch (signal) {
-		VW_SIGNAL_TRANSLATION_LIST(CASE_CROS_TO_ZEPHYR);
-	default:
-		LOG_ERR("Invalid virtual wire signal (%d)", signal);
-		return -1;
-	}
-}
-
-/* Translate a Zephyr vwire to a platform/ec signal */
-static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire)
-{
-	switch (vwire) {
-		VW_SIGNAL_TRANSLATION_LIST(CASE_ZEPHYR_TO_CROS);
-	default:
-		LOG_ERR("Invalid zephyr vwire (%d)", vwire);
-		return -1;
-	}
-}
-
-/*
- * Bit field for each signal which can have an interrupt enabled.
- * Note the interrupt is always enabled, it just depends whether we
- * route it to the power_signal_interrupt handler or not.
- */
-static atomic_t signal_interrupt_enabled;
-
-/* To be used with VW_SIGNAL_TRASLATION_LIST */
-#define CASE_CROS_TO_BIT(A, _) CASE_CROS_TO_ZEPHYR(A, BIT(A - VW_SIGNAL_START))
-
-/* Convert from an EC signal to the corresponding interrupt enabled bit. */
-static uint32_t signal_to_interrupt_bit(enum espi_vw_signal signal)
-{
-	switch (signal) {
-		VW_SIGNAL_TRANSLATION_LIST(CASE_CROS_TO_BIT);
-	default:
-		return 0;
-	}
-}
-
-/* Callback for vwire received */
-static void espi_vwire_handler(const struct device *dev,
-			       struct espi_callback *cb,
-			       struct espi_event event)
-{
-	int ec_signal = zephyr_vwire_to_signal(event.evt_details);
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_POWERSEQ) &&
-	    (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal))) {
-		power_signal_interrupt(ec_signal);
-	}
-}
-
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
-static void espi_chipset_reset(void)
-{
-	hook_notify(HOOK_CHIPSET_RESET);
-}
-DECLARE_DEFERRED(espi_chipset_reset);
-
-/* Callback for reset */
-static void espi_reset_handler(const struct device *dev,
-			       struct espi_callback *cb,
-			       struct espi_event event)
-{
-	hook_call_deferred(&espi_chipset_reset_data, MSEC);
-
-}
-#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */
-
-#define ESPI_NODE DT_NODELABEL(espi0)
-static const struct device *espi_dev;
-
-
-int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
-{
-	int ret = espi_send_vwire(espi_dev, signal_to_zephyr_vwire(signal),
-				  level);
-
-	if (ret != 0)
-		LOG_ERR("Encountered error sending virtual wire signal");
-
-	return ret;
-}
-
-int espi_vw_get_wire(enum espi_vw_signal signal)
-{
-	uint8_t level;
-
-	if (espi_receive_vwire(espi_dev, signal_to_zephyr_vwire(signal),
-			       &level) < 0) {
-		LOG_ERR("Encountered error receiving virtual wire signal");
-		return 0;
-	}
-
-	return level;
-}
-
-int espi_vw_enable_wire_int(enum espi_vw_signal signal)
-{
-	atomic_or(&signal_interrupt_enabled, signal_to_interrupt_bit(signal));
-	return 0;
-}
-
-int espi_vw_disable_wire_int(enum espi_vw_signal signal)
-{
-	atomic_and(&signal_interrupt_enabled, ~signal_to_interrupt_bit(signal));
-	return 0;
-}
-
-uint8_t *lpc_get_memmap_range(void)
-{
-	uint32_t lpc_memmap = 0;
-	int result = espi_read_lpc_request(espi_dev, EACPI_GET_SHARED_MEMORY,
-					   &lpc_memmap);
-
-	if (result != EC_SUCCESS)
-		LOG_ERR("Get lpc_memmap failed (%d)!\n", result);
-
-	return (uint8_t *)lpc_memmap;
-}
-
-/**
- * Update the level-sensitive wake signal to the AP.
- *
- * @param wake_events	Currently asserted wake events
- */
-static void lpc_update_wake(host_event_t wake_events)
-{
-	/*
-	 * Mask off power button event, since the AP gets that through a
-	 * separate dedicated GPIO.
-	 */
-	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
-
-	/* Signal is asserted low when wake events is non-zero */
-	gpio_set_level(GPIO_EC_PCH_WAKE_ODL, !wake_events);
-}
-
-static void lpc_generate_smi(void)
-{
-	/* Enforce signal-high for long enough to debounce high */
-	espi_vw_set_wire(VW_SMI_L, 1);
-	udelay(VWIRE_PULSE_TRIGGER_TIME);
-	espi_vw_set_wire(VW_SMI_L, 0);
-	udelay(VWIRE_PULSE_TRIGGER_TIME);
-	espi_vw_set_wire(VW_SMI_L, 1);
-}
-
-static void lpc_generate_sci(void)
-{
-	/* Enforce signal-high for long enough to debounce high */
-	espi_vw_set_wire(VW_SCI_L, 1);
-	udelay(VWIRE_PULSE_TRIGGER_TIME);
-	espi_vw_set_wire(VW_SCI_L, 0);
-	udelay(VWIRE_PULSE_TRIGGER_TIME);
-	espi_vw_set_wire(VW_SCI_L, 1);
-}
-
-void lpc_update_host_event_status(void)
-{
-	uint32_t enable;
-	uint32_t status;
-	int need_sci = 0;
-	int need_smi = 0;
-
-	if (!init_done)
-		return;
-
-	/* Disable PMC1 interrupt while updating status register */
-	enable = 0;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
-			       &enable);
-
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(status & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
-
-		status |= EC_LPC_STATUS_SMI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-	} else {
-		status &= ~EC_LPC_STATUS_SMI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-	}
-
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-
-		status |= EC_LPC_STATUS_SCI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-	} else {
-		status &= ~EC_LPC_STATUS_SCI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-	}
-
-	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-		lpc_get_host_events();
-
-	enable = 1;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
-			       &enable);
-
-	/* Process the wake events. */
-	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
-
-	/* Send pulse on SMI signal if needed */
-	if (need_smi)
-		lpc_generate_smi();
-
-	/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
-	if (need_sci)
-		lpc_generate_sci();
-}
-
-static void host_command_init(void)
-{
-	/* We support LPC args and version 3 protocol */
-	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-		EC_HOST_CMD_FLAG_VERSION_3;
-
-	/* Sufficiently initialized */
-	init_done = 1;
-
-	lpc_update_host_event_status();
-}
-
-DECLARE_HOOK(HOOK_INIT, host_command_init, HOOK_PRIO_INIT_LPC);
-
-static void handle_acpi_write(uint32_t data)
-{
-	uint8_t value, result;
-	uint8_t is_cmd = is_acpi_command(data);
-	uint32_t status;
-
-	value = get_acpi_value(data);
-
-	/* Handle whatever this was. */
-	if (acpi_ap_to_ec(is_cmd, value, &result)) {
-		data = result;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_CHAR, &data);
-	}
-
-	/* Clear processing flag */
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	status &= ~EC_LPC_STATUS_PROCESSING;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-
-	/*
-	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
-	 * Full condition on the kernel channel.
-	 */
-	lpc_generate_sci();
-}
-
-static void lpc_send_response_packet(struct host_packet *pkt)
-{
-	uint32_t data;
-
-	/* TODO(b/176523211): check whether add EC_RES_IN_PROGRESS handle */
-
-	/* Write result to the data byte.  This sets the TOH status bit. */
-	data = pkt->driver_result;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_CMD_SEND_RESULT, &data);
-}
-
-static void handle_host_write(uint32_t data)
-{
-	uint32_t shm_mem_host_cmd;
-
-	if (EC_COMMAND_PROTOCOL_3 != (data & 0xff)) {
-		LOG_ERR("Don't support this version of the host command");
-		/* TODO:(b/175217186): error response for other versions */
-		return;
-	}
-
-	espi_read_lpc_request(espi_dev, ECUSTOM_HOST_CMD_GET_PARAM_MEMORY,
-			      &shm_mem_host_cmd);
-
-	lpc_packet.send_response = lpc_send_response_packet;
-
-	lpc_packet.request = (const void *)shm_mem_host_cmd;
-	lpc_packet.request_temp = params_copy;
-	lpc_packet.request_max = sizeof(params_copy);
-	/* Don't know the request size so pass in the entire buffer */
-	lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
-
-	lpc_packet.response = (void *)shm_mem_host_cmd;
-	lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
-	lpc_packet.response_size = 0;
-
-	lpc_packet.driver_result = EC_RES_SUCCESS;
-
-	host_packet_receive(&lpc_packet);
-	return;
-}
-
-void lpc_set_acpi_status_mask(uint8_t mask)
-{
-	uint32_t status;
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	status |= mask;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-}
-
-void lpc_clear_acpi_status_mask(uint8_t mask)
-{
-	uint32_t status;
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	status &= ~mask;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
-}
-
-/* Get protocol information */
-static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
-{
-	struct ec_response_get_protocol_info *r = args->response;
-
-	memset(r, 0, sizeof(*r));
-	r->protocol_versions = BIT(3);
-	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
-	r->flags = 0;
-
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
-		     EC_VER_MASK(0));
-
-/*
- * This function is needed only for the obsolete platform which uses the GPIO
- * for KBC's IRQ.
- */
-void lpc_keyboard_resume_irq(void) {}
-
-void lpc_keyboard_clear_buffer(void)
-{
-	/* Clear OBF flag in host STATUS and HIKMST regs */
-	espi_write_lpc_request(espi_dev, E8042_CLEAR_OBF, 0);
-}
-int lpc_keyboard_has_char(void)
-{
-	uint32_t status;
-
-	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	espi_read_lpc_request(espi_dev, E8042_OBF_HAS_CHAR, &status);
-	return status;
-}
-
-void lpc_keyboard_put_char(uint8_t chr, int send_irq)
-{
-	uint32_t kb_char = chr;
-
-	espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
-	LOG_INF("KB put %02x", kb_char);
-}
-
-/* Put an aux char to host buffer by HIMDO and assert status bit 5. */
-void lpc_aux_put_char(uint8_t chr, int send_irq)
-{
-	uint32_t kb_char = chr;
-	uint32_t status = I8042_AUX_DATA;
-
-	espi_write_lpc_request(espi_dev, E8042_SET_FLAG, &status);
-	espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
-	LOG_INF("AUX put %02x", kb_char);
-}
-
-static void kbc_ibf_obe_handler(uint32_t data)
-{
-#ifdef HAS_TASK_KEYPROTO
-	uint8_t is_ibf = is_8042_ibf(data);
-	uint32_t status = I8042_AUX_DATA;
-
-	if (is_ibf) {
-		keyboard_host_write(get_8042_data(data),
-				    get_8042_type(data));
-	} else if (IS_ENABLED(CONFIG_8042_AUX)) {
-		espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG, &status);
-	}
-	task_wake(TASK_ID_KEYPROTO);
-#endif
-}
-
-int lpc_keyboard_input_pending(void)
-{
-	uint32_t status;
-
-	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	espi_read_lpc_request(espi_dev, E8042_IBF_HAS_CHAR, &status);
-	return status;
-}
-
-static void espi_peripheral_handler(const struct device *dev,
-				    struct espi_callback *cb,
-				    struct espi_event event)
-{
-	uint16_t event_type = event.evt_details;
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_PORT80) &&
-	    event_type == ESPI_PERIPHERAL_DEBUG_PORT80) {
-		port_80_write(event.evt_data);
-	}
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_ACPI) &&
-	    event_type == ESPI_PERIPHERAL_HOST_IO) {
-		handle_acpi_write(event.evt_data);
-	}
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_HOSTCMD) &&
-	    event_type == ESPI_PERIPHERAL_EC_HOST_CMD) {
-		handle_host_write(event.evt_data);
-	}
-
-	if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_8042_KBC) &&
-	    IS_ENABLED(HAS_TASK_KEYPROTO) &&
-	    event_type == ESPI_PERIPHERAL_8042_KBC) {
-		kbc_ibf_obe_handler(event.evt_data);
-	}
-}
-
-int zephyr_shim_setup_espi(void)
-{
-	static struct {
-		struct espi_callback cb;
-		espi_callback_handler_t handler;
-		enum espi_bus_event event_type;
-	} callbacks[] = {
-		{
-			.handler = espi_vwire_handler,
-			.event_type = ESPI_BUS_EVENT_VWIRE_RECEIVED,
-		},
-		{
-			.handler = espi_peripheral_handler,
-			.event_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
-		},
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
-		{
-			.handler = espi_reset_handler,
-			.event_type = ESPI_BUS_RESET,
-		},
-#endif
-	};
-
-	struct espi_cfg cfg = {
-		.io_caps = ESPI_IO_MODE_SINGLE_LINE,
-		.channel_caps = ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_PERIPHERAL |
-				ESPI_CHANNEL_OOB,
-		.max_freq = 20,
-	};
-
-	espi_dev = DEVICE_DT_GET(ESPI_NODE);
-	if (!device_is_ready(espi_dev)) {
-		LOG_ERR("Error: device %s is not ready", espi_dev->name);
-		return -1;
-	}
-
-	/* Configure eSPI */
-	if (espi_config(espi_dev, &cfg)) {
-		LOG_ERR("Failed to configure eSPI device");
-		return -1;
-	}
-
-	/* Setup callbacks */
-	for (size_t i = 0; i < ARRAY_SIZE(callbacks); i++) {
-		espi_init_callback(&callbacks[i].cb, callbacks[i].handler,
-				   callbacks[i].event_type);
-		espi_add_callback(espi_dev, &callbacks[i].cb);
-	}
-
-	return 0;
-}
diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c
deleted file mode 100644
index 932688fc9c..0000000000
--- a/zephyr/shim/src/fan.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "fan.h"
-#include "pwm.h"
-#include "pwm/pwm.h"
-#include "system.h"
-#include "math_util.h"
-#include "hooks.h"
-#include "gpio_signal.h"
-#include "gpio.h"
-#include <logging/log.h>
-#include <sys/util_macro.h>
-#include <drivers/sensor.h>
-
-LOG_MODULE_REGISTER(fan_shim, LOG_LEVEL_ERR);
-
-#define FAN_CONFIGS(node_id)                                                   \
-	const struct fan_conf node_id##_conf = {                               \
-		.flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode),      \
-				      (0), (FAN_USE_RPM_MODE))) |              \
-			 (COND_CODE_1(DT_PROP(node_id, use_fast_start),        \
-				      (FAN_USE_FAST_START), (0))),             \
-		.ch = node_id,                                                 \
-		.pgood_gpio = COND_CODE_1(                                     \
-			DT_NODE_HAS_PROP(node_id, pgood_gpio),                 \
-			(GPIO_SIGNAL(DT_PHANDLE(node_id, pgood_gpio))),        \
-			(GPIO_UNIMPLEMENTED)),                                 \
-		.enable_gpio = COND_CODE_1(                                    \
-			DT_NODE_HAS_PROP(node_id, enable_gpio),                \
-			(GPIO_SIGNAL(DT_PHANDLE(node_id, enable_gpio))),       \
-			(GPIO_UNIMPLEMENTED)),                                 \
-	};                                                                     \
-	const struct fan_rpm node_id##_rpm = {                                 \
-		.rpm_min = DT_PROP(node_id, rpm_min),                          \
-		.rpm_start = DT_PROP(node_id, rpm_start),                      \
-		.rpm_max = DT_PROP(node_id, rpm_max),                          \
-	};
-
-#define FAN_INST(node_id)              \
-	[node_id] = {                  \
-		.conf = &node_id##_conf, \
-		.rpm = &node_id##_rpm,   \
-	},
-
-#define FAN_CONTROL_INST(node_id)                                \
-	[node_id] = {                                            \
-		.pwm_id = PWM_CHANNEL(DT_PHANDLE(node_id, pwm)), \
-	},
-
-#if DT_NODE_EXISTS(DT_INST(0, named_fans))
-DT_FOREACH_CHILD(DT_INST(0, named_fans), FAN_CONFIGS)
-#endif /* named_fan */
-
-const struct fan_t fans[] = {
-#if DT_NODE_EXISTS(DT_INST(0, named_fans))
-	DT_FOREACH_CHILD(DT_INST(0, named_fans), FAN_INST)
-#endif /* named_fan */
-};
-
-#define TACHO_DEV_INIT(node_id) {                         \
-	fan_control[node_id].tach =                       \
-		DEVICE_DT_GET(DT_PHANDLE(node_id, tach)); \
-	}
-
-/* Rpm deviation (Unit:percent) */
-#ifndef RPM_DEVIATION
-#define RPM_DEVIATION 7
-#endif
-
-/* Margin of target rpm */
-#define RPM_MARGIN(rpm_target) (((rpm_target)*RPM_DEVIATION) / 100)
-
-/* Fan mode */
-enum fan_mode {
-	/* FAN rpm mode */
-	FAN_RPM = 0,
-	/* FAN duty mode */
-	FAN_DUTY,
-};
-
-/* Fan status data structure */
-struct fan_status_t {
-	/* Fan mode */
-	enum fan_mode current_fan_mode;
-	/* Actual rpm */
-	int rpm_actual;
-	/* Target rpm */
-	int rpm_target;
-	/* Fan config flags */
-	unsigned int flags;
-	/* Automatic fan status */
-	enum fan_status auto_status;
-};
-
-/* Data structure to define tachometer. */
-struct fan_control_t {
-	const struct device *tach;
-	enum pwm_channel pwm_id;
-};
-
-static struct fan_status_t fan_status[FAN_CH_COUNT];
-static int rpm_pre[FAN_CH_COUNT];
-static struct fan_control_t fan_control[] = {
-#if DT_NODE_EXISTS(DT_INST(0, named_fans))
-	DT_FOREACH_CHILD(DT_INST(0, named_fans), FAN_CONTROL_INST)
-#endif /* named_fan */
-};
-
-/**
- * Get fan rpm value
- *
- * @param   ch      operation channel
- * @return          Actual rpm
- */
-static int fan_rpm(int ch)
-{
-	struct sensor_value val = { 0 };
-
-	sensor_sample_fetch_chan(fan_control[ch].tach, SENSOR_CHAN_RPM);
-	sensor_channel_get(fan_control[ch].tach, SENSOR_CHAN_RPM, &val);
-	return (int)val.val1;
-}
-
-/**
- * Check all fans are stopped
- *
- * @return   1: all fans are stopped. 0: else.
- */
-static int fan_all_disabled(void)
-{
-	int ch;
-
-	for (ch = 0; ch < fan_get_count(); ch++)
-		if (fan_status[ch].auto_status != FAN_STATUS_STOPPED)
-			return 0;
-	return 1;
-}
-
-/**
- * Adjust fan duty by difference between target and actual rpm
- *
- * @param   ch        operation channel
- * @param   rpm_diff  difference between target and actual rpm
- * @param   duty      current fan duty
- */
-static void fan_adjust_duty(int ch, int rpm_diff, int duty)
-{
-	int duty_step = 0;
-
-	/* Find suitable duty step */
-	if (ABS(rpm_diff) >= 2000)
-		duty_step = 20;
-	else if (ABS(rpm_diff) >= 1000)
-		duty_step = 10;
-	else if (ABS(rpm_diff) >= 500)
-		duty_step = 5;
-	else if (ABS(rpm_diff) >= 250)
-		duty_step = 3;
-	else
-		duty_step = 1;
-
-	/* Adjust fan duty step by step */
-	if (rpm_diff > 0)
-		duty = MIN(duty + duty_step, 100);
-	else
-		duty = MAX(duty - duty_step, 1);
-
-	fan_set_duty(ch, duty);
-
-	LOG_DBG("fan%d: duty %d, rpm_diff %d", ch, duty, rpm_diff);
-}
-
-/**
- * Smart fan control function.
- *
- * The function sets the pwm duty to reach the target rpm
- *
- * @param   ch         operation channel
- * @param   rpm_actual actual operation rpm value
- * @param   rpm_target target operation rpm value
- * @return  current    fan control status
- */
-enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
-{
-	int duty, rpm_diff;
-
-	/* wait rpm is stable */
-	if (ABS(rpm_actual - rpm_pre[ch]) > RPM_MARGIN(rpm_actual)) {
-		rpm_pre[ch] = rpm_actual;
-		return FAN_STATUS_CHANGING;
-	}
-
-	/* Record previous rpm */
-	rpm_pre[ch] = rpm_actual;
-
-	/* Adjust PWM duty */
-	rpm_diff = rpm_target - rpm_actual;
-	duty = fan_get_duty(ch);
-	if (duty == 0 && rpm_target == 0)
-		return FAN_STATUS_STOPPED;
-
-	/* Increase PWM duty */
-	if (rpm_diff > RPM_MARGIN(rpm_target)) {
-		if (duty == 100)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-		/* Decrease PWM duty */
-	} else if (rpm_diff < -RPM_MARGIN(rpm_target)) {
-		if (duty == 1 && rpm_target != 0)
-			return FAN_STATUS_FRUSTRATED;
-
-		fan_adjust_duty(ch, rpm_diff, duty);
-		return FAN_STATUS_CHANGING;
-	}
-
-	return FAN_STATUS_LOCKED;
-}
-
-void fan_tick_func(void)
-{
-	int ch;
-
-	for (ch = 0; ch < FAN_CH_COUNT; ch++) {
-		volatile struct fan_status_t *p_status = fan_status + ch;
-		/* Make sure rpm mode is enabled */
-		if (p_status->current_fan_mode != FAN_RPM) {
-			/* Fan in duty mode still want rpm_actual being updated.
-			 */
-			if (p_status->flags & FAN_USE_RPM_MODE) {
-				p_status->rpm_actual = fan_rpm(ch);
-				if (p_status->rpm_actual > 0)
-					p_status->auto_status =
-						FAN_STATUS_LOCKED;
-				else
-					p_status->auto_status =
-						FAN_STATUS_STOPPED;
-				continue;
-			} else {
-				if (fan_get_duty(ch) > 0)
-					p_status->auto_status =
-						FAN_STATUS_LOCKED;
-				else
-					p_status->auto_status =
-						FAN_STATUS_STOPPED;
-			}
-			continue;
-		}
-		if (!fan_get_enabled(ch))
-			continue;
-		/* Get actual rpm */
-		p_status->rpm_actual = fan_rpm(ch);
-		/* Do smart fan stuff */
-		p_status->auto_status = fan_smart_control(
-			ch, p_status->rpm_actual, p_status->rpm_target);
-	}
-}
-DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
-
-int fan_get_duty(int ch)
-{
-	enum pwm_channel pwm_id = fan_control[ch].pwm_id;
-
-	/* Return percent */
-	return pwm_get_duty(pwm_id);
-}
-
-int fan_get_rpm_mode(int ch)
-{
-	return fan_status[ch].current_fan_mode == FAN_RPM ? 1 : 0;
-}
-
-void fan_set_rpm_mode(int ch, int rpm_mode)
-{
-	if (rpm_mode && (fan_status[ch].flags & FAN_USE_RPM_MODE))
-		fan_status[ch].current_fan_mode = FAN_RPM;
-	else
-		fan_status[ch].current_fan_mode = FAN_DUTY;
-}
-
-int fan_get_rpm_actual(int ch)
-{
-	/* Check PWM is enabled first */
-	if (fan_get_duty(ch) == 0)
-		return 0;
-
-	LOG_DBG("fan %d: get actual rpm = %d", ch, fan_status[ch].rpm_actual);
-	return fan_status[ch].rpm_actual;
-}
-
-int fan_get_enabled(int ch)
-{
-	enum pwm_channel pwm_id = fan_control[ch].pwm_id;
-
-	return pwm_get_enabled(pwm_id);
-}
-
-void fan_set_enabled(int ch, int enabled)
-{
-	enum pwm_channel pwm_id = fan_control[ch].pwm_id;
-
-	if (!enabled)
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-	pwm_enable(pwm_id, enabled);
-}
-
-void fan_channel_setup(int ch, unsigned int flags)
-{
-	volatile struct fan_status_t *p_status = fan_status + ch;
-
-	if (flags & FAN_USE_RPM_MODE) {
-		DT_FOREACH_CHILD(DT_INST(0, named_fans), TACHO_DEV_INIT)
-	}
-
-	p_status->flags = flags;
-	/* Set default fan states */
-	p_status->current_fan_mode = FAN_DUTY;
-	p_status->auto_status = FAN_STATUS_STOPPED;
-}
-
-void fan_set_duty(int ch, int percent)
-{
-	enum pwm_channel pwm_id = fan_control[ch].pwm_id;
-
-	/* duty is zero */
-	if (!percent) {
-		fan_status[ch].auto_status = FAN_STATUS_STOPPED;
-		if (fan_all_disabled())
-			enable_sleep(SLEEP_MASK_FAN);
-	} else
-		disable_sleep(SLEEP_MASK_FAN);
-
-	/* Set the duty cycle of PWM */
-	pwm_set_duty(pwm_id, percent);
-}
-
-int fan_get_rpm_target(int ch)
-{
-	return fan_status[ch].rpm_target;
-}
-
-enum fan_status fan_get_status(int ch)
-{
-	return fan_status[ch].auto_status;
-}
-
-void fan_set_rpm_target(int ch, int rpm)
-{
-	if (rpm == 0) {
-		/* If rpm = 0, disable PWM immediately. Why?*/
-		fan_set_duty(ch, 0);
-	} else {
-		/* This is the counterpart of disabling PWM above. */
-		if (!fan_get_enabled(ch))
-			fan_set_enabled(ch, 1);
-		if (rpm > fans[ch].rpm->rpm_max)
-			rpm = fans[ch].rpm->rpm_max;
-		else if (rpm < fans[ch].rpm->rpm_min)
-			rpm = fans[ch].rpm->rpm_min;
-	}
-
-	/* Set target rpm */
-	fan_status[ch].rpm_target = rpm;
-	LOG_DBG("fan %d: set target rpm = %d", ch, fan_status[ch].rpm_target);
-}
-
-int fan_is_stalled(int ch)
-{
-	int is_pgood = 1;
-
-	if (gpio_is_implemented(fans[ch].conf->enable_gpio))
-		is_pgood = gpio_get_level(fans[ch].conf->enable_gpio);
-
-	return fan_get_enabled(ch) && fan_get_duty(ch) &&
-	       !fan_get_rpm_actual(ch) && is_pgood;
-}
diff --git a/zephyr/shim/src/flash.c b/zephyr/shim/src/flash.c
deleted file mode 100644
index b72d7b5763..0000000000
--- a/zephyr/shim/src/flash.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <flash.h>
-#include <kernel.h>
-#include <logging/log.h>
-
-#include "console.h"
-#include "drivers/cros_flash.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-LOG_MODULE_REGISTER(shim_flash, LOG_LEVEL_ERR);
-
-#define CROS_FLASH_DEV DT_LABEL(DT_NODELABEL(fiu0))
-static const struct device *cros_flash_dev;
-
-K_MUTEX_DEFINE(flash_lock);
-
-/* TODO(b/174873770): Add calls to Zephyr code here */
-#ifdef CONFIG_EXTERNAL_STORAGE
-void crec_flash_lock_mapped_storage(int lock)
-{
-	if (lock)
-		mutex_lock(&flash_lock);
-	else
-		mutex_unlock(&flash_lock);
-}
-#endif
-
-int crec_flash_physical_write(int offset, int size, const char *data)
-{
-	int rv;
-
-	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size | (uint32_t)(uintptr_t)data) &
-	    (CONFIG_FLASH_WRITE_SIZE - 1))
-		return EC_ERROR_INVAL;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	rv = cros_flash_physical_write(cros_flash_dev, offset, size, data);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_erase(int offset, int size)
-{
-	int rv;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-
-	rv = cros_flash_physical_erase(cros_flash_dev, offset, size);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-int crec_flash_physical_get_protect(int bank)
-{
-	return cros_flash_physical_get_protect(cros_flash_dev, bank);
-}
-
-uint32_t crec_flash_physical_get_protect_flags(void)
-{
-	return cros_flash_physical_get_protect_flags(cros_flash_dev);
-}
-
-int crec_flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	return cros_flash_physical_protect_at_boot(cros_flash_dev, new_flags);
-}
-
-int crec_flash_physical_protect_now(int all)
-{
-	return cros_flash_physical_protect_now(cros_flash_dev, all);
-}
-
-int crec_flash_physical_read(int offset, int size, char *data)
-{
-	int rv;
-
-	/* Lock physical flash operations */
-	crec_flash_lock_mapped_storage(1);
-	rv = cros_flash_physical_read(cros_flash_dev, offset, size, data);
-
-	/* Unlock physical flash operations */
-	crec_flash_lock_mapped_storage(0);
-
-	return rv;
-}
-
-static int flash_dev_init(const struct device *unused)
-{
-	ARG_UNUSED(unused);
-
-	cros_flash_dev = device_get_binding(CROS_FLASH_DEV);
-	if (!cros_flash_dev) {
-		LOG_ERR("Fail to find %s", CROS_FLASH_DEV);
-		return -ENODEV;
-	}
-	cros_flash_init(cros_flash_dev);
-
-	return 0;
-}
-
-uint32_t crec_flash_physical_get_valid_flags(void)
-{
-	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
-	       EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	uint32_t ret = 0;
-
-	/* If RO protection isn't enabled, its at-boot state can be changed. */
-	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
-		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
-
-	/*
-	 * If entire flash isn't protected at this boot, it can be enabled if
-	 * the WP GPIO is asserted.
-	 */
-	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
-		ret |= EC_FLASH_PROTECT_ALL_NOW;
-
-	return ret;
-}
-
-/*
- * The priority flash_dev_init should be lower than GPIO initialization because
- * it calls gpio_get_level function.
- */
-#if CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY <= \
-	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY
-#error "Flash must be initialized after GPIOs"
-#endif
-SYS_INIT(flash_dev_init, POST_KERNEL, CONFIG_PLATFORM_EC_FLASH_INIT_PRIORITY);
diff --git a/zephyr/shim/src/gpio.c b/zephyr/shim/src/gpio.c
deleted file mode 100644
index 2bae272361..0000000000
--- a/zephyr/shim/src/gpio.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <init.h>
-#include <kernel.h>
-#include <logging/log.h>
-
-#include "gpio.h"
-#include "gpio/gpio.h"
-#include "sysjump.h"
-#include "cros_version.h"
-
-LOG_MODULE_REGISTER(gpio_shim, LOG_LEVEL_ERR);
-
-/*
- * Static information about each GPIO that is configured in the named_gpios
- * device tree node.
- */
-struct gpio_config {
-	/* GPIO net name */
-	const char *name;
-	/* Set at build time for lookup */
-	const struct device *dev;
-	/* Bit number of pin within device */
-	gpio_pin_t pin;
-	/* From DTS, excludes interrupts flags */
-	gpio_flags_t init_flags;
-};
-
-#define GPIO_CONFIG(id)                                                      \
-	COND_CODE_1(                                                         \
-		DT_NODE_HAS_PROP(id, enum_name),                             \
-		(                                                            \
-			{                                                    \
-				.name = DT_LABEL(id),                        \
-				.dev = DEVICE_DT_GET(DT_PHANDLE(id, gpios)), \
-				.pin = DT_GPIO_PIN(id, gpios),               \
-				.init_flags = DT_GPIO_FLAGS(id, gpios),      \
-			}, ),                                                \
-		())
-static const struct gpio_config configs[] = {
-#if DT_NODE_EXISTS(DT_PATH(named_gpios))
-	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_CONFIG)
-#endif
-};
-
-/* Runtime information for each GPIO that is configured in named_gpios */
-struct gpio_data {
-	/* Runtime device for gpio port. Set during in init function */
-	const struct device *dev;
-};
-
-#define GPIO_DATA(id) COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), ({}, ), ())
-static struct gpio_data data[] = {
-#if DT_NODE_EXISTS(DT_PATH(named_gpios))
-	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DATA)
-#endif
-};
-
-/* Maps platform/ec gpio callback information */
-struct gpio_signal_callback {
-	/* The platform/ec gpio_signal */
-	const enum gpio_signal signal;
-	/* IRQ handler from platform/ec code */
-	void (*const irq_handler)(enum gpio_signal signal);
-	/* Interrupt-related gpio flags */
-	const gpio_flags_t flags;
-};
-
-/*
- * Each zephyr project should define EC_CROS_GPIO_INTERRUPTS in their gpio_map.h
- * file if there are any interrupts that should be registered.  The
- * corresponding handler will be declared here, which will prevent
- * needing to include headers with complex dependencies in gpio_map.h.
- *
- * EC_CROS_GPIO_INTERRUPTS is a space-separated list of GPIO_INT items.
- */
-
-/*
- * Validate interrupt flags are valid for the Zephyr GPIO driver.
- */
-#define IS_GPIO_INTERRUPT_FLAG(flag, mask) ((flag & mask) == mask)
-#define VALID_GPIO_INTERRUPT_FLAG(flag)                             \
-	(IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_RISING) ||      \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_FALLING) ||     \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_BOTH) ||        \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_LOW) ||        \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_HIGH) ||       \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_TO_INACTIVE) || \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_EDGE_TO_ACTIVE) ||   \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_INACTIVE) ||   \
-	 IS_GPIO_INTERRUPT_FLAG(flag, GPIO_INT_LEVEL_ACTIVE))
-
-#define GPIO_INT(sig, f, cb)                       \
-	BUILD_ASSERT(VALID_GPIO_INTERRUPT_FLAG(f), \
-		     STRINGIFY(sig) " is not using Zephyr interrupt flags");
-#ifdef EC_CROS_GPIO_INTERRUPTS
-EC_CROS_GPIO_INTERRUPTS
-#endif
-#undef GPIO_INT
-
-/*
- * Create unique enum values for each GPIO_INT entry, which also sets
- * the ZEPHYR_GPIO_INT_COUNT value.
- */
-#define ZEPHYR_GPIO_INT_ID(sig) INT_##sig
-#define GPIO_INT(sig, f, cb) ZEPHYR_GPIO_INT_ID(sig),
-enum zephyr_gpio_int_id {
-#ifdef EC_CROS_GPIO_INTERRUPTS
-	EC_CROS_GPIO_INTERRUPTS
-#endif
-	ZEPHYR_GPIO_INT_COUNT,
-};
-#undef GPIO_INT
-
-/* Create prototypes for each GPIO IRQ handler */
-#define GPIO_INT(sig, f, cb) void cb(enum gpio_signal signal);
-#ifdef EC_CROS_GPIO_INTERRUPTS
-EC_CROS_GPIO_INTERRUPTS
-#endif
-#undef GPIO_INT
-
-/*
- * The Zephyr gpio_callback data needs to be updated at runtime, so allocate
- * into uninitialized data (BSS). The constant data pulled from
- * EC_CROS_GPIO_INTERRUPTS is stored separately in the gpio_interrupts[] array.
- */
-static struct gpio_callback zephyr_gpio_callbacks[ZEPHYR_GPIO_INT_COUNT];
-
-#define ZEPHYR_GPIO_CALLBACK_TO_INDEX(cb)                 \
-	(int)(((int)(cb) - (int)&zephyr_gpio_callbacks) / \
-	      sizeof(struct gpio_callback))
-
-#define GPIO_INT(sig, f, cb)       \
-	{                          \
-		.signal = sig,     \
-		.flags = f,        \
-		.irq_handler = cb, \
-	},
-const static struct gpio_signal_callback
-	gpio_interrupts[ZEPHYR_GPIO_INT_COUNT] = {
-#ifdef EC_CROS_GPIO_INTERRUPTS
-		EC_CROS_GPIO_INTERRUPTS
-#endif
-#undef GPIO_INT
-	};
-
-/* The single zephyr gpio handler that routes to appropriate platform/ec cb */
-static void gpio_handler_shim(const struct device *port,
-			      struct gpio_callback *cb, gpio_port_pins_t pins)
-{
-	int callback_index = ZEPHYR_GPIO_CALLBACK_TO_INDEX(cb);
-	const struct gpio_signal_callback *const gpio =
-		&gpio_interrupts[callback_index];
-
-	/* Call the platform/ec gpio interrupt handler */
-	gpio->irq_handler(gpio->signal);
-}
-
-/**
- * get_interrupt_from_signal() - Translate a gpio_signal to the
- * corresponding gpio_signal_callback
- *
- * @signal		The signal to convert.
- *
- * Return: A pointer to the corresponding entry in gpio_interrupts, or
- * NULL if one does not exist.
- */
-const static struct gpio_signal_callback *
-get_interrupt_from_signal(enum gpio_signal signal)
-{
-	if (!gpio_is_implemented(signal))
-		return NULL;
-
-	for (size_t i = 0; i < ARRAY_SIZE(gpio_interrupts); i++) {
-		if (gpio_interrupts[i].signal == signal)
-			return &gpio_interrupts[i];
-	}
-
-	LOG_ERR("No interrupt defined for GPIO %s", configs[signal].name);
-	return NULL;
-}
-
-int gpio_is_implemented(enum gpio_signal signal)
-{
-	return signal >= 0 && signal < ARRAY_SIZE(configs);
-}
-
-int gpio_get_level(enum gpio_signal signal)
-{
-	if (!gpio_is_implemented(signal))
-		return 0;
-
-	const int l = gpio_pin_get_raw(data[signal].dev, configs[signal].pin);
-
-	if (l < 0) {
-		LOG_ERR("Cannot read %s (%d)", configs[signal].name, l);
-		return 0;
-	}
-	return l;
-}
-
-int gpio_get_ternary(enum gpio_signal signal)
-{
-	int pd, pu;
-	int flags = gpio_get_default_flags(signal);
-
-	/* Read GPIO with internal pull-down */
-	gpio_set_flags(signal, GPIO_INPUT | GPIO_PULL_DOWN);
-	pd = gpio_get_level(signal);
-	udelay(100);
-
-	/* Read GPIO with internal pull-up */
-	gpio_set_flags(signal, GPIO_INPUT | GPIO_PULL_UP);
-	pu = gpio_get_level(signal);
-	udelay(100);
-
-	/* Reset GPIO flags */
-	gpio_set_flags(signal, flags);
-
-	/* Check PU and PD readings to determine tristate */
-	return pu && !pd ? 2 : pd;
-}
-
-const char *gpio_get_name(enum gpio_signal signal)
-{
-	if (!gpio_is_implemented(signal))
-		return "UNIMPLEMENTED";
-
-	return configs[signal].name;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (!gpio_is_implemented(signal))
-		return;
-
-	int rv = gpio_pin_set_raw(data[signal].dev, configs[signal].pin, value);
-
-	if (rv < 0) {
-		LOG_ERR("Cannot write %s (%d)", configs[signal].name, rv);
-	}
-}
-
-void gpio_set_level_verbose(enum console_channel channel,
-			    enum gpio_signal signal, int value)
-{
-	cprints(channel, "Set %s: %d", gpio_get_name(signal), value);
-	gpio_set_level(signal, value);
-}
-
-/* GPIO flags which are the same in Zephyr and this codebase */
-#define GPIO_CONVERSION_SAME_BITS                                       \
-	(GPIO_OPEN_DRAIN | GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_INPUT | \
-	 GPIO_OUTPUT)
-
-static int convert_from_zephyr_flags(const gpio_flags_t zephyr)
-{
-	/* Start out with the bits that are the same. */
-	int ec_flags = zephyr & GPIO_CONVERSION_SAME_BITS;
-	gpio_flags_t unhandled_flags = zephyr & ~GPIO_CONVERSION_SAME_BITS;
-
-	/* TODO(b/173789980): handle conversion of more bits? */
-	if (unhandled_flags) {
-		LOG_WRN("Unhandled GPIO bits in zephyr->ec conversion: 0x%08X",
-			unhandled_flags);
-	}
-
-	return ec_flags;
-}
-
-static gpio_flags_t convert_to_zephyr_flags(int ec_flags)
-{
-	/* Start out with the bits that are the same. */
-	gpio_flags_t zephyr_flags = ec_flags & GPIO_CONVERSION_SAME_BITS;
-	int unhandled_flags = ec_flags & ~GPIO_CONVERSION_SAME_BITS;
-
-	/* TODO(b/173789980): handle conversion of more bits? */
-	if (unhandled_flags) {
-		LOG_WRN("Unhandled GPIO bits in ec->zephyr conversion: 0x%08X",
-			unhandled_flags);
-	}
-
-	return zephyr_flags;
-}
-
-int gpio_get_default_flags(enum gpio_signal signal)
-{
-	if (!gpio_is_implemented(signal))
-		return 0;
-
-	return convert_from_zephyr_flags(configs[signal].init_flags);
-}
-
-static int init_gpios(const struct device *unused)
-{
-	gpio_flags_t flags;
-	struct jump_data *jdata;
-	bool is_sys_jumped;
-
-	ARG_UNUSED(unused);
-
-	jdata = get_jump_data();
-
-	if (jdata && jdata->magic == JUMP_DATA_MAGIC)
-		is_sys_jumped = true;
-	else
-		is_sys_jumped = false;
-
-	/* Loop through all GPIOs in device tree to set initial configuration */
-	for (size_t i = 0; i < ARRAY_SIZE(configs); ++i) {
-		data[i].dev = configs[i].dev;
-		int rv;
-
-		if (!device_is_ready(data[i].dev))
-			LOG_ERR("Not found (%s)", configs[i].name);
-
-		/*
-		 * The configs[i].init_flags variable is read-only, so the
-		 * following assignment is needed because the flags need
-		 * adjusting on a warm reboot.
-		 */
-		flags = configs[i].init_flags;
-
-		if (is_sys_jumped) {
-			flags &=
-				~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH);
-		}
-
-		rv = gpio_pin_configure(data[i].dev, configs[i].pin, flags);
-		if (rv < 0) {
-			LOG_ERR("Config failed %s (%d)", configs[i].name, rv);
-		}
-	}
-
-	/*
-	 * Loop through all interrupt pins and set their callback.
-	 */
-	for (size_t i = 0; i < ARRAY_SIZE(gpio_interrupts); ++i) {
-		const enum gpio_signal signal = gpio_interrupts[i].signal;
-		int rv;
-
-		if (signal == GPIO_UNIMPLEMENTED)
-			continue;
-
-		gpio_init_callback(&zephyr_gpio_callbacks[i], gpio_handler_shim,
-				   BIT(configs[signal].pin));
-		rv = gpio_add_callback(data[signal].dev,
-				       &zephyr_gpio_callbacks[i]);
-
-		if (rv < 0) {
-			LOG_ERR("Callback reg failed %s (%d)",
-				configs[signal].name, rv);
-			continue;
-		}
-	}
-
-	/* Configure unused pins in chip driver for better power consumption */
-	if (gpio_config_unused_pins) {
-		int rv;
-
-		rv = gpio_config_unused_pins();
-		if (rv < 0) {
-			return rv;
-		}
-	}
-
-	return 0;
-}
-#if CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY <= CONFIG_KERNEL_INIT_PRIORITY_DEFAULT
-#error "GPIOs must initialize after the kernel default initialization"
-#endif
-SYS_INIT(init_gpios, POST_KERNEL, CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY);
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int rv;
-	const struct gpio_signal_callback *interrupt;
-
-	interrupt = get_interrupt_from_signal(signal);
-
-	if (!interrupt)
-		return -1;
-
-	/*
-	 * Config interrupt flags (e.g. INT_EDGE_BOTH) & enable interrupt
-	 * together.
-	 */
-	rv = gpio_pin_interrupt_configure(data[signal].dev, configs[signal].pin,
-					  (interrupt->flags | GPIO_INT_ENABLE) &
-						  ~GPIO_INT_DISABLE);
-	if (rv < 0) {
-		LOG_ERR("Failed to enable interrupt on %s (%d)",
-			configs[signal].name, rv);
-	}
-
-	return rv;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	int rv;
-
-	if (!gpio_is_implemented(signal))
-		return -1;
-
-	rv = gpio_pin_interrupt_configure(data[signal].dev, configs[signal].pin,
-					  GPIO_INT_DISABLE);
-	if (rv < 0) {
-		LOG_ERR("Failed to disable interrupt on %s (%d)",
-			configs[signal].name, rv);
-	}
-
-	return rv;
-}
-
-void gpio_reset(enum gpio_signal signal)
-{
-	if (!gpio_is_implemented(signal))
-		return;
-
-	gpio_pin_configure(data[signal].dev, configs[signal].pin,
-			   configs[signal].init_flags);
-}
-
-void gpio_set_flags(enum gpio_signal signal, int flags)
-{
-	if (!gpio_is_implemented(signal))
-		return;
-
-	gpio_pin_configure(data[signal].dev, configs[signal].pin,
-			   convert_to_zephyr_flags(flags));
-}
-
-int signal_is_gpio(int signal)
-{
-	return true;
-}
diff --git a/zephyr/shim/src/gpio_id.c b/zephyr/shim/src/gpio_id.c
deleted file mode 100644
index 1dddac2c88..0000000000
--- a/zephyr/shim/src/gpio_id.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <devicetree.h>
-#include "gpio.h"
-#include "util.h"
-
-#define IS_BOARD_COMPATIBLE \
-	DT_NODE_HAS_COMPAT(DT_PATH(board), cros_ec_gpio_id)
-#define IS_SKU_COMPATIBLE \
-	DT_NODE_HAS_COMPAT(DT_PATH(sku), cros_ec_gpio_id)
-
-#define CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits) \
-	system##_from_bits(bits, nbits)
-#define CONVERT_NUMERAL_SYSTEM(system, bits, nbits) \
-	CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits)
-
-#define READ_PIN_FROM_PHANDLE(node_id, prop, idx) \
-	gpio_get_ternary(GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx))),
-
-#if DT_NODE_EXISTS(DT_PATH(sku)) && IS_SKU_COMPATIBLE
-
-__override uint32_t board_get_sku_id(void)
-{
-	static uint32_t sku_id = (uint32_t)-1;
-
-	if (sku_id == (uint32_t)-1) {
-		int bits[] = {
-			DT_FOREACH_PROP_ELEM(DT_PATH(sku),
-					bits,
-					READ_PIN_FROM_PHANDLE)
-		};
-
-		if (sizeof(bits) == 0)
-			return (uint32_t)-1;
-
-		sku_id = CONVERT_NUMERAL_SYSTEM(DT_STRING_TOKEN(DT_PATH(sku),
-								system),
-						bits, ARRAY_SIZE(bits));
-	}
-
-	return sku_id;
-}
-
-#endif
-
-#if DT_NODE_EXISTS(DT_PATH(board)) && IS_BOARD_COMPATIBLE
-
-__override int board_get_version(void)
-{
-	static int board_version = -1;
-
-	if (board_version == -1) {
-		int bits[] = {
-			DT_FOREACH_PROP_ELEM(DT_PATH(board),
-					bits,
-					READ_PIN_FROM_PHANDLE)
-		};
-
-		if (sizeof(bits) == 0)
-			return -1;
-
-		board_version = CONVERT_NUMERAL_SYSTEM(
-			DT_STRING_TOKEN(DT_PATH(board), system), bits,
-			ARRAY_SIZE(bits));
-	}
-
-	return board_version;
-}
-
-#endif
diff --git a/zephyr/shim/src/hooks.c b/zephyr/shim/src/hooks.c
deleted file mode 100644
index 79a611812f..0000000000
--- a/zephyr/shim/src/hooks.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <zephyr.h>
-
-#include "common.h"
-#include "console.h"
-#include "ec_tasks.h"
-#include "hooks.h"
-#include "task.h"
-#include "timer.h"
-
-int hook_call_deferred(const struct deferred_data *data, int us)
-{
-	struct k_work_delayable *work = data->work;
-	int rv = 0;
-
-	if (us == -1) {
-		k_work_cancel_delayable(work);
-	} else if (us >= 0) {
-		rv = k_work_reschedule(work, K_USEC(us));
-		if (rv == -EINVAL) {
-			/* Already processing or completed. */
-			return 0;
-		} else if (rv < 0) {
-			cprints(CC_HOOK,
-				"Warning: deferred call not submitted, "
-				"deferred_data=0x%pP, err=%d",
-				data, rv);
-		}
-	} else {
-		return EC_ERROR_PARAM2;
-	}
-
-	return rv;
-}
-
-static struct zephyr_shim_hook_list *hook_registry[HOOK_TYPE_COUNT];
-
-static int zephyr_shim_setup_hooks(const struct device *unused)
-{
-	STRUCT_SECTION_FOREACH(zephyr_shim_hook_list, entry) {
-		struct zephyr_shim_hook_list **loc = &hook_registry[entry->type];
-
-		/* Find the correct place to put the entry in the registry. */
-		while (*loc && (*loc)->priority < entry->priority)
-			loc = &((*loc)->next);
-
-		entry->next = *loc;
-
-		/* Insert the entry. */
-		*loc = entry;
-	}
-
-	return 0;
-}
-
-SYS_INIT(zephyr_shim_setup_hooks, APPLICATION, 1);
-
-void hook_notify(enum hook_type type)
-{
-	struct zephyr_shim_hook_list *p;
-
-	for (p = hook_registry[type]; p; p = p->next)
-		p->routine();
-}
-
-static void check_hook_task_priority(k_tid_t thread)
-{
-	/*
-	 * Numerically lower priorities take precedence, so verify the hook
-	 * related threads cannot preempt any of the shimmed tasks.
-	 */
-	if (k_thread_priority_get(thread) < (TASK_ID_COUNT - 1))
-		cprintf(CC_HOOK,
-			"ERROR: %s has priority %d but must be >= %d\n",
-			k_thread_name_get(thread),
-			k_thread_priority_get(thread), (TASK_ID_COUNT - 1));
-}
-
-void hook_task(void *u)
-{
-	/* Periodic hooks will be called first time through the loop */
-	static uint64_t last_second = -SECOND;
-	static uint64_t last_tick = -HOOK_TICK_INTERVAL;
-
-	/*
-	 * Verify deferred routines are run at the lowest priority.
-	 */
-	check_hook_task_priority(&k_sys_work_q.thread);
-	check_hook_task_priority(k_current_get());
-
-	while (1) {
-		uint64_t t = get_time().val;
-		int next = 0;
-
-		if (t - last_tick >= HOOK_TICK_INTERVAL) {
-			hook_notify(HOOK_TICK);
-			last_tick = t;
-		}
-
-		if (t - last_second >= SECOND) {
-			hook_notify(HOOK_SECOND);
-			last_second = t;
-		}
-
-		/* Calculate when next tick needs to occur */
-		t = get_time().val;
-		if (last_tick + HOOK_TICK_INTERVAL > t)
-			next = last_tick + HOOK_TICK_INTERVAL - t;
-
-		/*
-		 * Sleep until next tick, unless we've already exceeded
-		 * HOOK_TICK_INTERVAL.
-		 */
-		if (next > 0)
-			task_wait_event(next);
-	}
-}
diff --git a/zephyr/shim/src/host_command.c b/zephyr/shim/src/host_command.c
deleted file mode 100644
index bf863b48de..0000000000
--- a/zephyr/shim/src/host_command.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "host_command.h"
-
-struct host_command *zephyr_find_host_command(int command)
-{
-	STRUCT_SECTION_FOREACH(host_command, cmd) {
-		if (cmd->command == command)
-			return cmd;
-	}
-
-	return NULL;
-}
diff --git a/zephyr/shim/src/hwtimer.c b/zephyr/shim/src/hwtimer.c
deleted file mode 100644
index 85c72c5c59..0000000000
--- a/zephyr/shim/src/hwtimer.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <stdint.h>
-#include <zephyr.h>
-
-#include "hwtimer.h"
-
-uint64_t __hw_clock_source_read64(void)
-{
-	return k_ticks_to_us_floor64(k_uptime_ticks());
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	/*
-	 * CrOS EC event deadlines don't quite make sense in Zephyr
-	 * terms.  Evaluate what to do about this later...
-	 */
-	return 0;
-}
-
-void udelay(unsigned us)
-{
-	k_busy_wait(us);
-}
diff --git a/zephyr/shim/src/i2c.c b/zephyr/shim/src/i2c.c
deleted file mode 100644
index 3dba7cde38..0000000000
--- a/zephyr/shim/src/i2c.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <sys/util.h>
-
-#include "console.h"
-#include "i2c.h"
-#include "i2c/i2c.h"
-
-/*
- * The named-i2c-ports node is required by the I2C shim
- */
-#if !DT_NODE_EXISTS(DT_PATH(named_i2c_ports))
-#error I2C shim requires the named-i2c-ports node to be defined.
-#endif
-
-/*
- * Initialize device bindings in i2c_devices.
- * This macro should be called from within DT_FOREACH_CHILD.
- */
-#define INIT_DEV_BINDING(id) \
-	[I2C_PORT(id)] = DEVICE_DT_GET(DT_PHANDLE(id, i2c_port)),
-
-#define INIT_REMOTE_PORTS(id) \
-	[I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1),
-
-#define I2C_PORT_INIT(id)             \
-	{                             \
-		.name = DT_LABEL(id), \
-		.port = I2C_PORT(id), \
-	},
-/*
- * Long term we will not need these, for now they're needed to get things to
- * build since these extern symbols are usually defined in
- * board/${BOARD}/board.c.
- *
- * Since all the ports will eventually be handled by device tree. This will
- * be removed at that point.
- */
-const struct i2c_port_t i2c_ports[] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_INIT)
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-static const int i2c_remote_ports[I2C_PORT_COUNT] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_REMOTE_PORTS)
-};
-static int i2c_physical_ports[I2C_PORT_COUNT];
-
-static const struct device *i2c_devices[I2C_PORT_COUNT] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_DEV_BINDING)
-};
-
-static int init_device_bindings(const struct device *device)
-{
-	ARG_UNUSED(device);
-
-	/*
-	 * The EC application may lock the I2C bus for more than a single
-	 * I2C transaction. Initialize the i2c_physical_ports[] array to map
-	 * each named-i2c-ports child to the physical bus assignment.
-	 *
-	 * TODO(b/199918263): zephyr: Optimize I2C mutexes
-	 * Modify the port_mutex[] array defined by i2c_controller.c
-	 * so that only mutexes for unique physical ports are created to
-	 * save space.
-	 */
-	i2c_physical_ports[0] = 0;
-	for (int child = 1; child < I2C_PORT_COUNT; child++) {
-		for (int phys_port = 0; phys_port < I2C_PORT_COUNT;
-		     phys_port++) {
-			if (i2c_devices[child] == i2c_devices[phys_port]) {
-				i2c_physical_ports[child] = phys_port;
-				break;
-			}
-		}
-	}
-	return 0;
-}
-SYS_INIT(init_device_bindings, POST_KERNEL, 51);
-
-const struct device *i2c_get_device_for_port(const int port)
-{
-	if (port < 0 || port >= I2C_PORT_COUNT)
-		return NULL;
-	return i2c_devices[port];
-}
-
-int i2c_get_port_from_remote_port(int remote_port)
-{
-	for (int port = 0; port < I2C_PORT_COUNT; port++) {
-		if (i2c_remote_ports[port] == remote_port)
-			return port;
-	}
-
-	/*
-	 * Remote port is not defined, return 1:1 mapping to support TCPC
-	 * firmware updates, which always query the EC for the correct I2C
-	 * port number.
-	 */
-	return remote_port;
-}
-
-int i2c_get_physical_port(int enum_port)
-{
-	int i2c_port = i2c_physical_ports[enum_port];
-
-	/*
-	 * Return -1 for caller if physical port is not defined or the
-	 * port number is out of port_mutex space.
-	 * Please ensure the caller won't change anything if -1 received.
-	 */
-	return (i2c_port < I2C_PORT_COUNT) ? i2c_port : -1;
-}
-
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP
-static int command_i2c_portmap(int argc, char **argv)
-{
-	int i;
-
-	ccprintf("Zephyr physical I2C ports (%d):\n", I2C_PORT_COUNT);
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		ccprintf("  %d : %d\n", i, i2c_physical_ports[i]);
-	}
-	ccprintf("Zephyr remote I2C ports (%d):\n", I2C_PORT_COUNT);
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		ccprintf("  %d : %d\n", i, i2c_remote_ports[i]);
-	}
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(i2c_portmap, command_i2c_portmap, NULL,
-			"Show I2C port mapping");
-#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP */
diff --git a/zephyr/shim/src/keyboard_raw.c b/zephyr/shim/src/keyboard_raw.c
deleted file mode 100644
index 8de585a78f..0000000000
--- a/zephyr/shim/src/keyboard_raw.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Functions needed by keyboard scanner module for Chrome EC */
-
-#include <device.h>
-#include <logging/log.h>
-#include <soc.h>
-#include <zephyr.h>
-
-#include "drivers/cros_kb_raw.h"
-#include "keyboard_raw.h"
-
-LOG_MODULE_REGISTER(shim_cros_kb_raw, LOG_LEVEL_ERR);
-
-#define CROS_KB_RAW_NODE DT_NODELABEL(cros_kb_raw)
-static const struct device *cros_kb_raw_dev;
-
-/**
- * Initialize the raw keyboard interface.
- */
-void keyboard_raw_init(void)
-{
-	cros_kb_raw_dev = DEVICE_DT_GET(CROS_KB_RAW_NODE);
-	if (!device_is_ready(cros_kb_raw_dev)) {
-		LOG_ERR("Error: device %s is not ready", cros_kb_raw_dev->name);
-		return;
-	}
-
-	LOG_INF("%s", __func__);
-	cros_kb_raw_init(cros_kb_raw_dev);
-}
-
-/**
- * Finish initialization after task scheduling has started.
- */
-void keyboard_raw_task_start(void)
-{
-	keyboard_raw_enable_interrupt(1);
-}
-
-/**
- * Drive the specified column low.
- */
-test_mockable void keyboard_raw_drive_column(int col)
-{
-	if (cros_kb_raw_dev)
-		cros_kb_raw_drive_column(cros_kb_raw_dev, col);
-	else
-		LOG_ERR("%s: no cros_kb_raw device!", __func__);
-}
-
-/**
- * Read raw row state.
- * Bits are 1 if signal is present, 0 if not present.
- */
-test_mockable int keyboard_raw_read_rows(void)
-{
-	if (cros_kb_raw_dev)
-		return cros_kb_raw_read_rows(cros_kb_raw_dev);
-
-	LOG_ERR("%s: no cros_kb_raw device!", __func__);
-	return -EIO;
-}
-
-/**
- * Enable or disable keyboard interrupts.
- */
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (cros_kb_raw_dev)
-		cros_kb_raw_enable_interrupt(cros_kb_raw_dev, enable);
-	else
-		LOG_ERR("%s: no cros_kb_raw device!", __func__);
-}
diff --git a/zephyr/shim/src/keyscan.c b/zephyr/shim/src/keyscan.c
deleted file mode 100644
index fa8fb11dd2..0000000000
--- a/zephyr/shim/src/keyscan.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_keyscan
-
-#include <assert.h>
-#include <kernel.h>
-#include <soc.h>
-
-#include "keyboard_scan.h"
-
-#if DT_NODE_EXISTS(DT_INST(0, cros_keyscan))
-
-/* The keyboard matrix should have at least enough columns for the
- * standard keyboard with no keypad.
- */
-BUILD_ASSERT(DT_INST_PROP_LEN(0, actual_key_mask) >= KEYBOARD_COLS_NO_KEYPAD);
-
-/*
- * Override the default keyscan_config if the board defines a
- * cros-kb-raw-keyscan node.
- */
-__override struct keyboard_scan_config keyscan_config = {
-	.output_settle_us = DT_INST_PROP(0, output_settle),
-	.debounce_down_us = DT_INST_PROP(0, debounce_down),
-	.debounce_up_us = DT_INST_PROP(0, debounce_up),
-	.scan_period_us = DT_INST_PROP(0, scan_period),
-	.min_post_scan_delay_us = DT_INST_PROP(0, min_post_scan_delay),
-	.poll_timeout_us = DT_INST_PROP(0, poll_timeout),
-	.actual_key_mask = DT_INST_PROP(0, actual_key_mask),
-};
-#endif
diff --git a/zephyr/shim/src/libgcc_arm.S b/zephyr/shim/src/libgcc_arm.S
deleted file mode 100644
index ffdbefc675..0000000000
--- a/zephyr/shim/src/libgcc_arm.S
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "../../third_party/libaeabi-cortexm0/core/cortex-m/ldivmod.S"
-#include "../../third_party/libaeabi-cortexm0/core/cortex-m/uldivmod.S"
-
-exception_panic:
-	mov r0, #3 @ K_ERR_KERNEL_OOPS
-	b z_fatal_error
diff --git a/zephyr/shim/src/mkbp_event.c b/zephyr/shim/src/mkbp_event.c
deleted file mode 100644
index 39bcb001b8..0000000000
--- a/zephyr/shim/src/mkbp_event.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "mkbp_event.h"
-
-const struct mkbp_event_source *zephyr_find_mkbp_event_source(uint8_t type)
-{
-	STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc) {
-		if (evtsrc->event_type == type)
-			return evtsrc;
-	}
-
-	return NULL;
-}
diff --git a/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
deleted file mode 100644
index 7db46811ad..0000000000
--- a/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "driver/accel_bma2x2_public.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/*
- * Create driver data for each BMI260 drvinfo instance in device tree.
- * (compatible = "cros-ec,drvdata-bma255")
- */
-/* Declare BMA255 driver data */
-#define CREATE_SENSOR_DATA_BMA255(id, drvdata_name)	\
-	static struct accelgyro_saved_data_t drvdata_name;
-
-CREATE_SENSOR_DATA(cros_ec_drvdata_bma255, CREATE_SENSOR_DATA_BMA255)
-
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Create a motion_sensor_t entry for each BMA255
- * instance(compatible = "cros-ec,bma255") in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_bma255, MOTIONSENSE_CHIP_BMA255,	\
-	MOTIONSENSE_TYPE_ACCEL, bma2x2_accel_drv,		\
-	BMA255_ACCEL_MIN_FREQ, BMA255_ACCEL_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
deleted file mode 100644
index dd7b21641b..0000000000
--- a/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "driver/accelgyro_bmi_common_public.h"
-#include "driver/accelgyro_bmi160_public.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/*
- * Create driver data. It can be shared among the entries in
- * motion_sensors array which are using the same bmi160 driver.
- */
-#define CREATE_SENSOR_DATA_BMI160(id, drvdata_name)			\
-	static struct bmi_drv_data_t drvdata_name;
-
-/*
- * Create driver data for each BMI160 drvinfo instance in device tree.
- * (compatible = "cros-ec,drvdata-bmi160")
- */
-CREATE_SENSOR_DATA(cros_ec_drvdata_bmi160, CREATE_SENSOR_DATA_BMI160)
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each BMI160_accel instance(compatible = "cros-ec,bmi160-accel")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_bmi160_accel, MOTIONSENSE_CHIP_BMI160,	\
-		MOTIONSENSE_TYPE_ACCEL,	bmi160_drv,			\
-		BMI_ACCEL_MIN_FREQ, BMI_ACCEL_MAX_FREQ)
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each BMI260_gyro instance (compatible = "cros-ec,bmi160-gyro")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_bmi160_gyro, MOTIONSENSE_CHIP_BMI160,	\
-		MOTIONSENSE_TYPE_GYRO, bmi160_drv,			\
-		BMI_GYRO_MIN_FREQ, BMI_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
deleted file mode 100644
index 2457fca31a..0000000000
--- a/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "driver/accelgyro_bmi_common_public.h"
-#include "driver/accelgyro_bmi260_public.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/*
- * Create driver data. It can be shared among the entries in
- * motion_sensors array which are using the same bmi260 driver.
- */
-#define CREATE_SENSOR_DATA_BMI260(id, drvdata_name)			\
-	static struct bmi_drv_data_t drvdata_name;
-
-/*
- * Create driver data for each BMI260 drvinfo instance in device tree.
- * (compatible = "cros-ec,drvdata-bmi260")
- */
-CREATE_SENSOR_DATA(cros_ec_drvdata_bmi260, CREATE_SENSOR_DATA_BMI260)
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensros.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each BMI260_accel instance(compatible = "cros-ec,bmi260-accel")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_bmi260_accel, MOTIONSENSE_CHIP_BMI260,	\
-		MOTIONSENSE_TYPE_ACCEL,	bmi260_drv,			\
-		BMI_ACCEL_MIN_FREQ, BMI_ACCEL_MAX_FREQ)
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each BMI260_gyro instance (compatible = "cros-ec,bmi260-gyro")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_bmi260_gyro, MOTIONSENSE_CHIP_BMI260,	\
-		MOTIONSENSE_TYPE_GYRO, bmi260_drv,			\
-		BMI_GYRO_MIN_FREQ, BMI_GYRO_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
deleted file mode 100644
index 069587f90f..0000000000
--- a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Macros are to help creating driver data. A driver data that uses
- * any data structures defined in accelgyro.h should use the macros here
- * to utilize the information in device tree.
- *
- */
-#ifndef __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H
-#define __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H
-
-/*
- * compatible = "cros-ec,accelgyro-als-channel-scale"
- * als_channel_scale_t in accelgyro.h
- *
- * e.g) The following is the example in DT for als_channel_scale_t
- * als-channel-scale {
- *	compatible = "cros-ec,accelgyro-als-channel-scale";
- *		k-channel-scale = <1>;
- *		cover-scale = <1>;
- *	};
- */
-#define ACCELGYRO_ALS_CHANNEL_SCALE(id)					\
-	{								\
-		.k_channel_scale =					\
-			ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)),\
-		.cover_scale =						\
-			ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)),	\
-	}
-
-#define ALS_CALIBRATION_CHANNEL_SCALE(id)				\
-	.als_cal.channel_scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
-
-#define ALS_CALIBRATION_SET(id)					\
-	.als_cal.scale = DT_PROP(id, scale),			\
-	.als_cal.uscale = DT_PROP(id, uscale),			\
-	.als_cal.offset = DT_PROP(id, offset),			\
-	ALS_CALIBRATION_CHANNEL_SCALE(DT_CHILD(id, als_channel_scale))
-
-/*
- * compatible = "cros-ec,accelgyro-als-drv-data"
- * als_drv_data_t in accelgyro.h
- *
- * e.g) The following is the example in DT for als_drv_data_t 
- * als-drv-data {
- *	compatible = "cros-ec,accelgyro-als-drv-data";
- *	als-cal {
- *		scale = <1>;
- *		uscale = <0>;
- *		offset = <0>;
- *		als-channel-scale {
- *		compatible = "cros-ec,accelgyro-als-channel-scale";
- *			k-channel-scale = <1>;
- *			cover-scale = <1>;
- *		};
- *	};
- * };
- */
-#define ACCELGYRO_ALS_DRV_DATA(id)					\
-	{								\
-		ALS_CALIBRATION_SET(DT_CHILD(id, als_cal))		\
-	}
-
-#define RGB_CAL_RGB_SET_SCALE(id)			\
-	.scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
-
-#define RGB_CAL_RGB_SET_ONE(id, suffix)					\
-	.rgb_cal[suffix] = {						\
-	    .offset = DT_PROP(id, offset),				\
-	    .coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)),	\
-	    .coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)),	\
-	    .coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)),	\
-	    .coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)),	\
-	    RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale))	\
-	},
-
-/*
- * compatible = "cros-ec,accelgyro-rgb-calibration"
- * rgb_calibration_t in accelgyro.h
- *
- * e.g) The following is the example in DT for rgb_calibration_t
- * rgb_calibration {
- * 	compatible = "cros-ec,accelgyro-rgb-calibration";
- *
- *	irt = <1>;
- *
- *	rgb-cal-x {
- *		offset = <0>;
- *		coeff = <0 0 0 0>;
- *		als-channel-scale {
- *		compatible = "cros-ec,accelgyro-als-channel-scale";
- *			k-channel-scale = <1>;
- *			cover-scale = <1>;
- *		};
- *	};
- *	rgb-cal-y {
- *		offset = <0>;
- *		coeff = <0 0 0 0>;
- *		als-channel-scale {
- *		compatible = "cros-ec,accelgyro-als-channel-scale";
- *			k-channel-scale = <1>;
- *			cover-scale = <1>;
- *		};
- *	};
- *	rgb-cal-z {
- *		offset = <0>;
- *		coeff = <0 0 0 0>;
- *		als-channel-scale {
- *		compatible = "cros-ec,accelgyro-als-channel-scale";
- *			k-channel-scale = <1>;
- *			cover-scale = <1>;
- *		};
- *	};
- * };
- */
-#define ACCELGYRO_RGB_CALIBRATION(id)				\
-	{							\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X)	\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y)	\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z)	\
-		.irt = INT_TO_FP(DT_PROP(id, irt)),		\
-	}
-
-#endif /* __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H */
diff --git a/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc b/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
deleted file mode 100644
index 800a9a1543..0000000000
--- a/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "driver/accel_kionix.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/*
- * Create driver data for each Kionix drvinfo instance in device tree.
- * (compatible = "cros-ec,drvdata-kionix")
- */
-/* Declare Kionix driver data */
-#define CREATE_SENSOR_DATA_KIONIX(id, drvdata_name)	\
-	static struct kionix_accel_data drvdata_name;
-
-CREATE_SENSOR_DATA(cros_ec_drvdata_kionix, CREATE_SENSOR_DATA_KIONIX)
-
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Create a motion_sensor_t entry for each KX022
- * instance(compatible = "cros-ec,kx022") in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_kx022, MOTIONSENSE_CHIP_KX022,      \
-		     MOTIONSENSE_TYPE_ACCEL, kionix_accel_drv,   \
-		     KX022_ACCEL_MIN_FREQ, KX022_ACCEL_MAX_FREQ)
diff --git a/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
deleted file mode 100644
index 433a9d4192..0000000000
--- a/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accel_lis2dw12_public.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/*
- * Create driver data for each Kionix drvinfo instance in device tree.
- * (compatible = "cros-ec,drvdata-lis2dw12")
- */
-/* Declare LIS2DW12 driver data */
-#define CREATE_SENSOR_DATA_LIS2DW12(id, drvdata_name)	\
-	static struct motion_sensor_t drvdata_name;
-
-CREATE_SENSOR_DATA(cros_ec_drvdata_lis2dw12, CREATE_SENSOR_DATA_LIS2DW12)
-
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Create a motion_sensor_t entry for each LIS2DW12
- * instance(compatible = "cros-ec,lis2dw12") in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_lis2dw12, MOTIONSENSE_CHIP_LIS2DW12,	\
-		     MOTIONSENSE_TYPE_ACCEL, lis2dw12_drv,		\
-		     LIS2DW12_ODR_MIN_VAL, LIS2DW12_ODR_MAX_VAL)
diff --git a/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc b/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
deleted file mode 100644
index f8fa4b7e53..0000000000
--- a/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * A driver should create <chip>-drvinfo.inc to create
- * driver-specific data and an motion sensor entry in
- * motion_sensors array that are used by motion sense task.
- *
- * This file includes the .inc file and is used by motionsense_sensrs.c to
- * create the sensor driver data and the entries in mostion_sensors array.
- *
- * e.g) bma255-drvinfo.inc is provided for BMA255 chip
- *
- * #ifdef CONFIG_ACCEL_BMA255
- * #include "bma255-drvinfo.inc"
- * #endif
- */
-
-/* supported sensor driver list */
-#ifdef CONFIG_PLATFORM_EC_ACCEL_BMA255
-#include "bma255-drvinfo.inc"
-#endif
-#ifdef CONFIG_PLATFORM_EC_ACCEL_KX022
-#include "kx022-drvinfo.inc"
-#endif
-#ifdef CONFIG_PLATFORM_EC_ACCEL_LIS2DW12
-#include "lis2dw12-drvinfo.inc"
-#endif
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI160
-#include "bmi160-drvinfo.inc"
-#endif
-#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_BMI260
-#include "bmi260-drvinfo.inc"
-#endif
-#ifdef CONFIG_PLATFORM_EC_ALS_TCS3400
-#include "tcs3400-drvinfo.inc"
-#endif
diff --git a/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc b/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
deleted file mode 100644
index 346688d646..0000000000
--- a/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "driver/als_tcs3400_public.h"
-
-/*
- * CREATE_SENSOR_DATA which is defined in motionsense_sensros.c is
- * the helper to create sensor driver specific data.
- *
- * CREATE_SENSOR_DATA gets two arguments. One is the compatible
- * property value specified in device tree and the other one is the macro
- * that actually creates sensor driver specific data. The macro gets
- * node id and the name to be used for the sensor driver data.
- */
-
-/* include macros for common data strutures from accelgyro.h */
-#include "drvdata-accelgyro.h"
-
-/* Create driver data for tcs3400 driver. */
-#define CREATE_SENSOR_DATA_TCS3400_CLEAR(id, drvdata_name)		\
-	static struct als_drv_data_t drvdata_name =			\
-	    ACCELGYRO_ALS_DRV_DATA(DT_CHILD(id, als_drv_data));
-
-/*
- * Create driver data for each TCS3400-clear drvdata instance in device tree.
- * (compatible = "cros-ec,drvdata-tcs3400-clear")
- */
-CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear,	\
-	CREATE_SENSOR_DATA_TCS3400_CLEAR)
-
-/* driver data for tcs3400 rgb */
-#define TCS3400_RGB_SATRURATION(id)					\
-		COND_CODE_1(DT_NODE_HAS_PROP(id, again),		\
-			(.saturation.again = DT_PROP(id, again),),	\
-			(.saturation.again = TCS_DEFAULT_AGAIN,))	\
-		COND_CODE_1(DT_NODE_HAS_PROP(id, atime),		\
-			(.saturation.again = DT_PROP(id, atime),),	\
-			(.saturation.again = TCS_DEFAULT_ATIME,))
-
-#define CREATE_SENSOR_DATA_TCS3400_RGB(id, drvdata_name)		\
-	static struct tcs3400_rgb_drv_data_t drvdata_name = {		\
-		.calibration = ACCELGYRO_RGB_CALIBRATION(		\
-			DT_CHILD(id, rgb_calibration)),			\
-		TCS3400_RGB_SATRURATION(DT_CHILD(id, saturation))	\
-	};
-
-/*
- * Create driver data for each TCS3400-rgb drvdata instance in device tree.
- * (compatible = "cros-ec,drvdata-tcs3400-rgb")
- */
-CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_rgb, CREATE_SENSOR_DATA_TCS3400_RGB)
-/*
- * CREATE_MOTION_SENSOR which is defined in motionsense_sensros.c is
- * the macro to create an entry in motion_sensors array.
- * The macro gets value of compatible property of
- * the sensor in device tree and sensor specific values like chip ID,
- * type of sensor, name of driver, default min/max frequency.
- * Then using the values, it creates the corresponding motion_sense_t entry
- * in motion_sensors array.
- */
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each TCS3400 clear instance (compatible = "cros-ec,tcs3400-clear")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_tcs3400_clear, MOTIONSENSE_CHIP_TCS3400,	\
-		MOTIONSENSE_TYPE_LIGHT, tcs3400_drv,			\
-		TCS3400_LIGHT_MIN_FREQ, TCS3400_LIGHT_MAX_FREQ)
-
-/*
- * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * for each TCS3400 RGB instance (compatible = "cros-ec,tcs3400-rgb")
- * in device tree.
- */
-CREATE_MOTION_SENSOR(cros_ec_tcs3400_rgb, MOTIONSENSE_CHIP_TCS3400,	\
-		MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0)
diff --git a/zephyr/shim/src/motionsense_sensors.c b/zephyr/shim/src/motionsense_sensors.c
deleted file mode 100644
index 0c54160e2e..0000000000
--- a/zephyr/shim/src/motionsense_sensors.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "accelgyro.h"
-#include "hooks.h"
-#include "drivers/cros_cbi.h"
-
-#define SENSOR_MUTEX_NODE		DT_PATH(motionsense_mutex)
-#define SENSOR_MUTEX_NAME(id)		DT_CAT(MUTEX_, id)
-
-#if DT_NODE_EXISTS(SENSOR_MUTEX_NODE)
-#define DECLARE_SENSOR_MUTEX(id)	K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id));
-
-/*
- * Declare mutex for
- * each child node of "/motionsense-mutex" node in DT.
- *
- * A mutex can be shared among the motion sensors.
- */
-DT_FOREACH_CHILD(SENSOR_MUTEX_NODE, DECLARE_SENSOR_MUTEX)
-#endif /* DT_NODE_EXISTS(SENSOR_MUTEX_NODE) */
-
-#define SENSOR_ROT_REF_NODE		DT_PATH(motionsense_rotation_ref)
-#define SENSOR_ROT_STD_REF_NAME(id)	DT_CAT(ROT_REF_, id)
-#define MAT_ITEM(i, id)	FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i)))
-#define DECLARE_SENSOR_ROT_REF(id)					\
-	static const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = {	\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 0, 1, 2)	\
-		},							\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 3, 4, 5)	\
-		},							\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 6, 7, 8)	\
-		},							\
-	};
-
-/*
- * Declare 3x3 rotation matrix for
- * each child node of "/motionsense-rotation-ref" node in DT.
- *
- * A rotation matrix can be shared among the motion sensors.
- */
-#if DT_NODE_EXISTS(SENSOR_ROT_REF_NODE)
-DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
-#endif
-
-/*
- * Declare sensor driver data for
- * each child node with status = "okay" of
- * "/motionsense-sensor-data" node in DT.
- *
- * A driver data can be shared among the motion sensors.
- */
-#define SENSOR_DATA_NAME(id)		DT_CAT(SENSOR_DAT_, id)
-#define SENSOR_DATA_NODE		DT_PATH(motionsense_sensor_data)
-
-#define SENSOR_DATA(inst, compat, create_data_macro)			\
-	create_data_macro(DT_INST(inst, compat),			\
-		SENSOR_DATA_NAME(DT_INST(inst, compat)))
-
-/*
- * CREATE_SENSOR_DATA is a helper macro that gets
- * compat and create_data_macro as parameters.
- *
- * For each node with compatible = "compat",
- * CREATE_SENSOR_DATA expands "create_data_macro" macro with the node id and
- * the designated name for the sensor driver data to be created. The
- * "create_datda_macro" macro is responsible for creating the sensor driver
- * data with the name.
- *
- * Sensor drivers should provide <chip>-drvinfo.inc file and, in the file,
- * it should have the macro that creates its sensor driver data using device
- * tree and pass the macro via CREATE_SENSOR_DATA.
- *
- * e.g) The below is contents of tcs3400-drvinfo.inc file. The file has
- * CREATE_SENSOR_DATA_TCS3400_CLEAR that creates the static instance of
- * "struct als_drv_data_t" with the given name and initializes it
- * with device tree. Then use CREATE_SENSOR_DATA.
- *
- * ----------- bma255-drvinfo.inc -----------
- * #define CREATE_SENSOR_DATA_TCS3400_CLEAR(id, drvdata_name)      \
- *       static struct als_drv_data_t drvdata_name =               \
- *           ACCELGYRO_ALS_DRV_DATA(DT_CHILD(id, als_drv_data));
- *
- * CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear,   \
- *                    CREATE_SENSOR_DATA_TCS3400_CLEAR)
- */
-#define CREATE_SENSOR_DATA(compat, create_data_macro)			\
-	UTIL_LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA,	\
-		compat, create_data_macro)
-
-/*
- * sensor_drv_list.inc is included three times in this file. This is the first
- * time and it is for creating sensor driver-specific data. So we ignore
- * CREATE_MOTION_SENSOR() that creates motion sensor at this time.
- */
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv,		\
-		s_min_freq, s_max_freq)
-
-/*
- * Here, we declare all sensor driver data. How to create the data is
- * defined in <chip>-drvinfo.inc file and ,in turn, the file is included
- * in sensor_drv_list.inc.
- */
-#if DT_NODE_EXISTS(SENSOR_DATA_NODE)
-#include "motionsense_driver/sensor_drv_list.inc"
-#endif
-
-/*
- * Get the address of the mutex which is referred by phandle.
- * See motionsense-sensor-base.yaml and cros-ec,motionsense-mutex.yaml
- * for DT example and details.
- */
-#define SENSOR_MUTEX(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, mutex),				\
-		(.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)),))
-
-/*
- * Get I2C port number which is referred by phandle.
- * See motionsense-sensor-base.yaml for DT example and details.
- */
-#define SENSOR_I2C_PORT(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, port),				\
-		(.port = I2C_PORT(DT_PHANDLE(id, port)),))
-
-/*
- * Get I2C or SPI address.
- * See motionsense-sensor-base.yaml for DT example and details.
- */
-#define SENSOR_I2C_SPI_ADDR_FLAGS(id)                        \
-	IF_ENABLED(DT_NODE_HAS_PROP(id, i2c_spi_addr_flags), \
-		   (.i2c_spi_addr_flags =                    \
-			    DT_STRING_TOKEN(id, i2c_spi_addr_flags), ))
-
-/*
- * Get the address of rotation matrix which is referred by phandle.
- * See motionsense-sensor-base.yaml and cros-ec,motionsense-rotation-ref.yaml
- * for DT example and details.
- */
-#define SENSOR_ROT_STD_REF(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref),		\
-		(.rot_standard_ref =					\
-		 &SENSOR_ROT_STD_REF_NAME(DT_PHANDLE(id, rot_standard_ref)),))
-
-/*
- * Get the address of driver-specific data which is referred by phandle.
- * See motionsense-sensor-base.yaml for DT example and details.
- */
-#define SENSOR_DRV_DATA(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data),			\
-		   (.drv_data = &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)),))
-
-/*
- * Get odr and ec_rate for the motion sensor.
- * See motionsense-sensor-base.yaml and cros-ec,motionsense-sensor-config.yaml
- * for DT example and details.
- */
-#define SET_CONFIG_EC(cfg_id, cfg_suffix)				\
-	[SENSOR_CONFIG_##cfg_suffix] = {				\
-		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr),		\
-		   (.odr = DT_PROP(cfg_id, odr),))			\
-		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate),		\
-		   (.ec_rate = DT_PROP(cfg_id, ec_rate),))		\
-	}
-
-/* Get configs */
-#define CREATE_SENSOR_CONFIG(cfgs_id)					      \
-	.config = {							      \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP),))       \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0), EC_S0),)) \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s3)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s3), EC_S3),)) \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s5)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s5), EC_S5),)) \
-	}
-
-#define SENSOR_CONFIG(id)						\
-	IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)),		\
-		   (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)),))
-
-/* Get and assign the basic information for a motion sensor */
-#define SENSOR_BASIC_INFO(id)						\
-	.name = DT_LABEL(id),						\
-	.active_mask = DT_STRING_TOKEN(id, active_mask),		\
-	.location = DT_STRING_TOKEN(id, location),			\
-	.default_range = DT_PROP(id, default_range),			\
-	SENSOR_I2C_SPI_ADDR_FLAGS(id)					\
-	SENSOR_MUTEX(id)						\
-	SENSOR_I2C_PORT(id)						\
-	SENSOR_ROT_STD_REF(id)						\
-	SENSOR_DRV_DATA(id)						\
-	SENSOR_CONFIG(id)
-
-/* Create motion sensor node with node ID */
-#define DO_MK_SENSOR_ENTRY(						\
-		id, s_chip, s_type, s_drv, s_min_freq, s_max_freq)	\
-	[SENSOR_ID(id)] = {						\
-		SENSOR_BASIC_INFO(id)					\
-		.chip = s_chip,						\
-		.type = s_type,						\
-		.drv = &s_drv,						\
-		.min_frequency = s_min_freq,				\
-		.max_frequency = s_max_freq				\
-	},
-
-/* Construct an entry iff the alternate_for property is missing. */
-#define MK_SENSOR_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq,    \
-			s_max_freq)                                           \
-	COND_CODE_0(DT_NODE_HAS_PROP(DT_INST(inst, s_compat), alternate_for), \
-		    (DO_MK_SENSOR_ENTRY(DT_INST(inst, s_compat), s_chip,      \
-					s_type, s_drv, s_min_freq,            \
-					s_max_freq)),                         \
-		    ())
-
-/* Construct an entry iff the alternate_for property exists. */
-#define MK_SENSOR_ALT_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq, \
-			    s_max_freq)                                        \
-	COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, s_compat), alternate_for),  \
-		    (DO_MK_SENSOR_ENTRY(DT_INST(inst, s_compat), s_chip,       \
-					s_type, s_drv, s_min_freq,             \
-					s_max_freq)),                          \
-		    ())
-
-#undef CREATE_SENSOR_DATA
-/*
- * Sensor driver-specific data creation stage is already done. So this
- * time we ignore CREATE_SENSOR_DATA().
- */
-#define CREATE_SENSOR_DATA(compat, create_data_macro)
-#undef CREATE_MOTION_SENSOR
-
-/*
- * CREATE_MOTION_SENSOR is a help macro that read the sensor information from
- * device tree and creates an entry in motion_sensors array which is used
- * by motion sense task. The help macro gets compatible value of the
- * sensor node and several driver specific information like CHIP_ID,
- * SENSOR_TYPE, driver instance name, and min/max frequency.
- *
- * <chip>-drvinfo.inc file which is provided by sensor driver should use
- * CREATE_MOTION_SENSOR to provide driver specific information.
- *
- * e.g) The below is contents of tcs3400-drvinfo.inc file. The file has
- * CREATE_MOTION_SENSOR like below to create the sensor entry. The file uses
- * the help macro two times since the chip supports two functions
- * ALS clear and ALS RGB.
-
- * ------------- tcs3400-drvinfo.inc -------------
- * // Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * // for each TCS3400 clear instance (compatible = "cros-ec,tcs3400-clear")
- * // in device tree.
- * CREATE_MOTION_SENSOR(cros_ec_tcs3400_clear, MOTIONSENSE_CHIP_TCS3400,   \
- *       MOTIONSENSE_TYPE_LIGHT, tcs3400_drv,            \
- *       TCS3400_LIGHT_MIN_FREQ, TCS3400_LIGHT_MAX_FREQ)
-
- *
- * // Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
- * // for each TCS3400 RGB instance (compatible = "cros-ec,tcs3400-rgb")
- * // in device tree.
- *
- * CREATE_MOTION_SENSOR(cros_ec_tcs3400_rgb, MOTIONSENSE_CHIP_TCS3400, \
- *       MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0)
- * -----------------------------------------------
- */
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv,		\
-		s_min_freq, s_max_freq)					\
-	UTIL_LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY,\
-		s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
-
-/*
- * Here, we include sensor_drv_list.inc AGAIN but this time it only
- * uses CREATE_MOTION_SENSOR to create the motion sensor entries.
- */
-struct motion_sensor_t motion_sensors[] = {
-#if DT_NODE_EXISTS(SENSOR_NODE)
-#include "motionsense_driver/sensor_drv_list.inc"
-#endif
-};
-
-/*
- * Remap the CREATE_MOTION_SENSOR to call MK_SENSOR_ALT_ENTRY to create a list
- * of alternate sensors that will be used at runtime.
- */
-#undef CREATE_MOTION_SENSOR
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq,    \
-			     s_max_freq)                                     \
-	UTIL_LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, \
-		     s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
-
-/*
- * The list of alternate motion sensors that may be used at runtime to replace
- * an entry in the motion_sensors array.
- */
-__maybe_unused struct motion_sensor_t motion_sensors_alt[] = {
-#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
-#include "motionsense_driver/sensor_drv_list.inc"
-#endif
-};
-
-#ifdef CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#else
-const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-#endif
-
-/*
- * Create a list of ALS sensors needed by motion sense
- *
- * The following example adds tcs3400 als sensor to motion_als_sensors array
- *
- * motionsense-sensors {
- *         lid_accel: bma255 {
- *             :
- *         };
- *             :
- *             :
- *         als_clear: tcs3400 {
- *             :
- *         };
- * };
- *
- * motionsense-sensor-info {
- *       compatible = "cros-ec,motionsense-sensor-info";
- *
- *       // list of entries for motion_als_sensors
- *       als-sensors = <&als_clear>;
- *                  :
- *                  :
- * };
- */
-#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, als_sensors)
-#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id)		\
-	&motion_sensors[SENSOR_ID(DT_PHANDLE_BY_IDX(id, als_sensors, i))],
-const struct motion_sensor_t *motion_als_sensors[] = {
-	UTIL_LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors),
-		     ALS_SENSOR_ENTRY_WITH_COMMA, SENSOR_INFO_NODE)
-};
-BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
-#endif
-
-/*
- * Enable interrupts for motion sensors
- *
- * e.g) list of named-gpio nodes
- * motionsense-sensor-info {
- *        compatible = "cros-ec,motionsense-sensor-info";
- *
- *         // list of GPIO interrupts that have to
- *         // be enabled at initial stage
- *        sensor-irqs = <&gpio_ec_imu_int_l &gpio_ec_als_rgb_int_l>;
- * };
- */
-#if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, sensor_irqs)
-#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id)		\
-	gpio_enable_interrupt(				\
-		GPIO_SIGNAL(DT_PHANDLE_BY_IDX(id, sensor_irqs, i)));
-static void sensor_enable_irqs(void)
-{
-	UTIL_LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, sensor_irqs),
-		     SENSOR_GPIO_ENABLE_INTERRUPT, SENSOR_INFO_NODE)
-}
-DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT);
-#endif
-
-/* Handle the alternative motion sensors */
-#define REPLACE_ALT_MOTION_SENSOR(new_id, old_id) \
-	motion_sensors[SENSOR_ID(old_id)] =       \
-		motion_sensors_alt[SENSOR_ID(new_id)];
-
-#define CHECK_AND_REPLACE_ALT_MOTION_SENSOR(id)                        \
-	do {                                                           \
-		if (cros_cbi_ssfc_check_match(                         \
-			    dev, CBI_SSFC_VALUE_ID(DT_PHANDLE(         \
-					 id, alternate_indicator)))) { \
-			REPLACE_ALT_MOTION_SENSOR(                     \
-				id, DT_PHANDLE(id, alternate_for))     \
-		}                                                      \
-	} while (0);
-
-#define ALT_MOTION_SENSOR_INIT_ID(id)                                    \
-	COND_CODE_1(UTIL_AND(DT_NODE_HAS_PROP(id, alternate_for),        \
-			     DT_NODE_HAS_PROP(id, alternate_indicator)), \
-		    (CHECK_AND_REPLACE_ALT_MOTION_SENSOR(id)), ())
-
-void motion_sensors_init_alt(void)
-{
-	const struct device *dev = device_get_binding("cros_cbi");
-
-	if (dev == NULL)
-		return;
-
-#if DT_NODE_EXISTS(SENSOR_ALT_NODE)
-	DT_FOREACH_CHILD(SENSOR_ALT_NODE, ALT_MOTION_SENSOR_INIT_ID)
-#endif
-}
-
-DECLARE_HOOK(HOOK_INIT, motion_sensors_init_alt, HOOK_PRIO_INIT_I2C + 1);
diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c
deleted file mode 100644
index 22322cc4ee..0000000000
--- a/zephyr/shim/src/panic.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <arch/cpu.h>
-#include <fatal.h>
-#include <logging/log.h>
-#include <logging/log_ctrl.h>
-#include <zephyr.h>
-
-#include "common.h"
-#include "panic.h"
-
-/*
- * Arch-specific configuration
- *
- * For each architecture, define:
- * - PANIC_ARCH, which should be the corresponding arch field of the
- *   panic_data struct.
- * - PANIC_REG_LIST, which is a macro that takes a parameter M, and
- *   applies M to 3-tuples of:
- *   - zephyr esf field name
- *   - panic_data struct field name
- *   - human readable name
- */
-
-#if defined(CONFIG_ARM)
-#define PANIC_ARCH PANIC_ARCH_CORTEX_M
-#define PANIC_REG_LIST(M)             \
-	M(basic.r0, cm.frame[0], a1)  \
-	M(basic.r1, cm.frame[1], a2)  \
-	M(basic.r2, cm.frame[2], a3)  \
-	M(basic.r3, cm.frame[3], a4)  \
-	M(basic.r12, cm.frame[4], ip) \
-	M(basic.lr, cm.frame[5], lr)  \
-	M(basic.pc, cm.frame[6], pc)  \
-	M(basic.xpsr, cm.frame[7], xpsr)
-#define PANIC_REG_EXCEPTION(pdata) pdata->cm.regs[1]
-#define PANIC_REG_REASON(pdata) pdata->cm.regs[3]
-#define PANIC_REG_INFO(pdata) pdata->cm.regs[4]
-#elif defined(CONFIG_RISCV) && !defined(CONFIG_64BIT)
-#define PANIC_ARCH PANIC_ARCH_RISCV_RV32I
-#define PANIC_REG_LIST(M)         \
-	M(ra, riscv.regs[1], ra)  \
-	M(tp, riscv.regs[3], tp)  \
-	M(a0, riscv.regs[4], a0)  \
-	M(a1, riscv.regs[5], a1)  \
-	M(a2, riscv.regs[6], a2)  \
-	M(a3, riscv.regs[7], a3)  \
-	M(a4, riscv.regs[8], a4)  \
-	M(a5, riscv.regs[9], a5)  \
-	M(a6, riscv.regs[10], a6) \
-	M(a7, riscv.regs[11], a7) \
-	M(t0, riscv.regs[12], t0) \
-	M(t1, riscv.regs[13], t1) \
-	M(t2, riscv.regs[14], t2) \
-	M(t3, riscv.regs[15], t3) \
-	M(t4, riscv.regs[16], t4) \
-	M(t5, riscv.regs[17], t5) \
-	M(t6, riscv.regs[18], t6) \
-	M(mepc, riscv.mepc, mepc) \
-	M(mstatus, riscv.mcause, mstatus)
-#define PANIC_REG_EXCEPTION(pdata) (pdata->riscv.mcause)
-#define PANIC_REG_REASON(pdata) (pdata->riscv.regs[11])
-#define PANIC_REG_INFO(pdata) (pdata->riscv.regs[10])
-#else
-/* Not implemented for this arch */
-#define PANIC_ARCH 0
-#define PANIC_REG_LIST(M)
-#ifdef CONFIG_PLATFORM_EC_SOFTWARE_PANIC
-static uint8_t placeholder_exception_reg;
-static uint32_t placeholder_reason_reg;
-static uint32_t placeholder_info_reg;
-#define PANIC_REG_EXCEPTION(unused) placeholder_exception_reg
-#define PANIC_REG_REASON(unused) placeholder_reason_reg
-#define PANIC_REG_INFO(unused) placeholder_info_reg
-#endif /* CONFIG_PLATFORM_EC_SOFTWARE_PANIC */
-#endif
-
-/* Macros to be applied to PANIC_REG_LIST as M */
-#define PANIC_COPY_REGS(esf_field, pdata_field, human_name) \
-	pdata->pdata_field = esf->esf_field;
-#define PANIC_PRINT_REGS(esf_field, pdata_field, human_name) \
-	panic_printf("  %-8s = 0x%08X\n", #human_name, pdata->pdata_field);
-
-void panic_data_print(const struct panic_data *pdata)
-{
-	PANIC_REG_LIST(PANIC_PRINT_REGS);
-}
-
-#ifndef CONFIG_LOG
-static void copy_esf_to_panic_data(const z_arch_esf_t *esf,
-				   struct panic_data *pdata)
-{
-	pdata->arch = PANIC_ARCH;
-	pdata->struct_version = 2;
-	pdata->flags = 0;
-	pdata->reserved = 0;
-	pdata->struct_size = sizeof(*pdata);
-	pdata->magic = PANIC_DATA_MAGIC;
-
-	PANIC_REG_LIST(PANIC_COPY_REGS);
-}
-
-void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *esf)
-{
-	panic_printf("Fatal error: %u\n", reason);
-
-	if (PANIC_ARCH && esf) {
-		copy_esf_to_panic_data(esf, get_panic_data_write());
-		panic_data_print(panic_get_data());
-	}
-
-	LOG_PANIC();
-	k_fatal_halt(reason);
-	CODE_UNREACHABLE;
-}
-#endif /* CONFIG_LOG */
-
-#ifdef CONFIG_PLATFORM_EC_SOFTWARE_PANIC
-void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
-{
-	struct panic_data * const pdata = get_panic_data_write();
-
-	/* Setup panic data structure */
-	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
-	pdata->magic = PANIC_DATA_MAGIC;
-	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
-	pdata->struct_version = 2;
-	pdata->arch = PANIC_ARCH;
-
-	/* Log panic cause */
-	PANIC_REG_EXCEPTION(pdata) = exception;
-	PANIC_REG_REASON(pdata) = reason;
-	PANIC_REG_INFO(pdata) = info;
-
-	/* Allow architecture specific logic */
-	arch_panic_set_reason(reason, info, exception);
-}
-
-void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
-{
-	struct panic_data * const pdata = panic_get_data();
-
-	if (pdata && pdata->struct_version == 2) {
-		*exception = PANIC_REG_EXCEPTION(pdata);
-		*reason = PANIC_REG_REASON(pdata);
-		*info = PANIC_REG_INFO(pdata);
-	} else {
-		*exception = *reason = *info = 0;
-	}
-}
-
-__overridable void arch_panic_set_reason(uint32_t reason, uint32_t info,
-					 uint8_t exception)
-{
-	/* Default implementation, do nothing. */
-}
-#endif /* CONFIG_PLATFORM_EC_SOFTWARE_PANIC */
diff --git a/zephyr/shim/src/pwm.c b/zephyr/shim/src/pwm.c
deleted file mode 100644
index 39fd72007e..0000000000
--- a/zephyr/shim/src/pwm.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <devicetree.h>
-#include <drivers/pwm.h>
-#include <logging/log.h>
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "pwm.h"
-#include "util.h"
-
-#include "pwm/pwm.h"
-
-LOG_MODULE_REGISTER(pwm_shim, LOG_LEVEL_ERR);
-
-#define USECS_PER_SEC 1000000
-
-/*
- * Initialize the device bindings in pwm_channels.
- * This macro is called from within DT_FOREACH_CHILD
- */
-#define INIT_DEV_BINDING(id) {                                              \
-		pwm_configs[PWM_CHANNEL(id)].name = DT_LABEL(id);           \
-		pwm_configs[PWM_CHANNEL(id)].dev = DEVICE_DT_GET(           \
-			DT_PHANDLE(id, pwms));                              \
-		pwm_configs[PWM_CHANNEL(id)].pin = DT_PWMS_CHANNEL(id);     \
-		pwm_configs[PWM_CHANNEL(id)].flags = DT_PWMS_FLAGS(id);     \
-		pwm_configs[PWM_CHANNEL(id)].freq = DT_PROP(id, frequency); \
-	}
-
-struct pwm_config {
-	/* Name */
-	const char *name;
-	/* PWM pin */
-	uint32_t pin;
-	/* PWM channel flags. See dt-bindings/pwm/pwm.h */
-	pwm_flags_t flags;
-	/* PWM operating frequency. Configured by the devicetree */
-	uint32_t freq;
-
-	/* PWM period in microseconds. Automatically set to 1/frequency */
-	uint32_t period_us;
-	/* PWM pulse in microseconds. Set by pwm_set_raw_duty */
-	uint32_t pulse_us;
-	/* Saves whether the PWM channel is currently enabled */
-	bool enabled;
-
-	/* Runtime device for PWM */
-	const struct device *dev;
-};
-
-static struct pwm_config pwm_configs[PWM_CH_COUNT];
-
-static int init_pwms(const struct device *unused)
-{
-	struct pwm_config *pwm;
-	int rv = 0;
-
-	ARG_UNUSED(unused);
-
-	/* Initialize PWM data from the device tree */
-	DT_FOREACH_CHILD(DT_PATH(named_pwms), INIT_DEV_BINDING)
-
-	/* Read the PWM operating frequency, set by the chip driver */
-	for (size_t i = 0; i < PWM_CH_COUNT; ++i) {
-		pwm = &pwm_configs[i];
-
-		if (pwm->dev == NULL) {
-			LOG_ERR("Not found (%s)", pwm->name);
-			rv = -ENODEV;
-			continue;
-		}
-
-		/*
-		 * TODO - check that devicetree frequency is less than 1/2
-		 * max frequency from the chip driver.
-		 */
-		pwm->period_us = USECS_PER_SEC / pwm->freq;
-	}
-
-	return rv;
-}
-#if CONFIG_PLATFORM_EC_PWM_INIT_PRIORITY <= CONFIG_KERNEL_INIT_PRIORITY_DEVICE
-#error "PWM init priority must be > KERNEL_INIT_PRIORITY_DEVICE"
-#endif
-SYS_INIT(init_pwms, PRE_KERNEL_1, CONFIG_PLATFORM_EC_PWM_INIT_PRIORITY);
-
-static struct pwm_config* pwm_lookup(enum pwm_channel ch)
-{
-	__ASSERT(ch < ARRAY_SIZE(pwm_configs), "Invalid PWM channel %d", ch);
-
-	return &pwm_configs[ch];
-}
-
-void pwm_enable(enum pwm_channel ch, int enabled)
-{
-	struct pwm_config *pwm;
-	uint32_t pulse_us;
-	int rv;
-
-	pwm = pwm_lookup(ch);
-	pwm->enabled = enabled;
-
-	/*
-	 * The Zephyr API doesn't provide explicit enable and disable
-	 * commands. However, setting the pulse width to zero disables
-	 * the PWM.
-	 */
-	if (enabled)
-		pulse_us = pwm->pulse_us;
-	else
-		pulse_us = 0;
-
-	rv = pwm_pin_set_usec(pwm->dev, pwm->pin, pwm->period_us, pulse_us,
-			      pwm->flags);
-
-	if (rv)
-		LOG_ERR("pwm_pin_set_usec() failed %s (%d)", pwm->name, rv);
-}
-
-int pwm_get_enabled(enum pwm_channel ch)
-{
-	struct pwm_config *pwm;
-
-	pwm = pwm_lookup(ch);
-	return pwm->enabled;
-}
-
-void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
-{
-	struct pwm_config *pwm;
-	int rv;
-
-	pwm = pwm_lookup(ch);
-
-	pwm->pulse_us =
-		DIV_ROUND_NEAREST(pwm->period_us * duty, EC_PWM_MAX_DUTY);
-
-	LOG_DBG("PWM %s set raw duty (0x%04x), pulse %d", pwm->name, duty,
-		pwm->pulse_us);
-
-	rv = pwm_pin_set_usec(pwm->dev, pwm->pin, pwm->period_us, pwm->pulse_us,
-			      pwm->flags);
-
-	if (rv)
-		LOG_ERR("pwm_pin_set_usec() failed %s (%d)", pwm->name, rv);
-}
-
-uint16_t pwm_get_raw_duty(enum pwm_channel ch)
-{
-	struct pwm_config *pwm;
-
-	pwm = pwm_lookup(ch);
-
-	return DIV_ROUND_NEAREST(pwm->pulse_us * EC_PWM_MAX_DUTY,
-				 pwm->period_us);
-}
-
-void pwm_set_duty(enum pwm_channel ch, int percent)
-{
-	struct pwm_config *pwm;
-	int rv;
-
-	pwm = pwm_lookup(ch);
-
-	pwm->pulse_us = DIV_ROUND_NEAREST(pwm->period_us * percent, 100);
-
-	LOG_DBG("PWM %s set percent (%d), pulse %d", pwm->name, percent,
-		pwm->pulse_us);
-
-	rv = pwm_pin_set_usec(pwm->dev, pwm->pin, pwm->period_us, pwm->pulse_us,
-			      pwm->flags);
-
-	if (rv)
-		LOG_ERR("pwm_pin_set_usec() failed %s (%d)", pwm->name, rv);
-}
-
-int pwm_get_duty(enum pwm_channel ch)
-{
-	struct pwm_config *pwm;
-
-	pwm = pwm_lookup(ch);
-
-	return DIV_ROUND_NEAREST(pwm->pulse_us * 100, pwm->period_us);
-}
diff --git a/zephyr/shim/src/pwm_led.c b/zephyr/shim/src/pwm_led.c
deleted file mode 100644
index 48565d2e56..0000000000
--- a/zephyr/shim/src/pwm_led.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define DT_DRV_COMPAT cros_ec_pwm_leds
-
-#include <string.h>
-#include <devicetree.h>
-
-#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
-
-#include "led_pwm.h"
-#include "pwm.h"
-
-BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(cros_ec_pwm_leds) <= 1,
-	     "Multiple CrOS EC PWM LED instances defined");
-BUILD_ASSERT(DT_INST_PROP_LEN(0, leds) <= 2,
-	     "Unsupported number of LEDs defined");
-
-#define PWM_CHANNEL_BY_IDX(node_id, prop, idx, led_ch)          \
-	PWM_CHANNEL(DT_PWMS_CTLR_BY_IDX(                        \
-		DT_PHANDLE_BY_IDX(node_id, prop, idx), led_ch))
-
-#define PWM_LED_INIT(node_id, prop, idx) \
-	[PWM_LED##idx] = { \
-		.ch0 = PWM_CHANNEL_BY_IDX(node_id, prop, idx, 0), \
-		.ch1 = PWM_CHANNEL_BY_IDX(node_id, prop, idx, 1), \
-		.ch2 = PWM_CHANNEL_BY_IDX(node_id, prop, idx, 2), \
-		.enable = &pwm_enable, \
-		.set_duty = &pwm_set_duty, \
-	},
-
-struct pwm_led pwm_leds[] = {
-	DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_INIT)
-};
-
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-	[EC_LED_COLOR_RED]    = DT_INST_PROP(0, color_map_red),
-	[EC_LED_COLOR_GREEN]  = DT_INST_PROP(0, color_map_green),
-	[EC_LED_COLOR_BLUE]   = DT_INST_PROP(0, color_map_blue),
-	[EC_LED_COLOR_YELLOW] = DT_INST_PROP(0, color_map_yellow),
-	[EC_LED_COLOR_WHITE]  = DT_INST_PROP(0, color_map_white),
-	[EC_LED_COLOR_AMBER]  = DT_INST_PROP(0, color_map_amber),
-};
-
-BUILD_ASSERT(DT_INST_PROP_LEN(0, brightness_range) == EC_LED_COLOR_COUNT,
-	     "brightness_range must have exactly EC_LED_COLOR_COUNT values");
-
-static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] = DT_INST_PROP(
-		0, brightness_range);
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	/* led_id is ignored, same ranges for all LEDs */
-	memcpy(brightness_range, dt_brigthness_range,
-	       sizeof(dt_brigthness_range));
-}
-
-#endif /* DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/rtc.c b/zephyr/shim/src/rtc.c
deleted file mode 100644
index 002e60148d..0000000000
--- a/zephyr/shim/src/rtc.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <logging/log.h>
-#include <kernel.h>
-#include <zephyr.h>
-
-#include "console.h"
-#include "drivers/cros_rtc.h"
-#include "hooks.h"
-#include "host_command.h"
-#include "util.h"
-
-LOG_MODULE_REGISTER(shim_cros_rtc, LOG_LEVEL_ERR);
-
-#define CROS_RTC_NODE DT_CHOSEN(cros_rtc)
-static const struct device *cros_rtc_dev;
-
-#ifdef CONFIG_HOSTCMD_EVENTS
-static void set_rtc_host_event(void)
-{
-	host_set_single_event(EC_HOST_EVENT_RTC);
-}
-DECLARE_DEFERRED(set_rtc_host_event);
-#endif
-
-void rtc_callback(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS)) {
-		hook_call_deferred(&set_rtc_host_event_data, 0);
-	}
-}
-
-/** Initialize the rtc. */
-static int system_init_rtc(const struct device *unused)
-{
-	ARG_UNUSED(unused);
-
-	cros_rtc_dev = DEVICE_DT_GET(CROS_RTC_NODE);
-	if (!cros_rtc_dev) {
-		LOG_ERR("Error: device %s is not ready", cros_rtc_dev->name);
-		return -ENODEV;
-	}
-
-	/* set the RTC callback */
-	cros_rtc_configure(cros_rtc_dev, rtc_callback);
-
-	return 0;
-}
-SYS_INIT(system_init_rtc, APPLICATION, 1);
-
-uint32_t system_get_rtc_sec(void)
-{
-	uint32_t seconds;
-
-	cros_rtc_get_value(cros_rtc_dev, &seconds);
-
-	return seconds;
-}
-
-void system_set_rtc(uint32_t seconds)
-{
-	cros_rtc_set_value(cros_rtc_dev, seconds);
-}
-
-void system_reset_rtc_alarm(void)
-{
-	if (!cros_rtc_dev) {
-		/* TODO(b/183115086): check the error handler for NULL device */
-		LOG_ERR("rtc_dev hasn't initialized.");
-		return;
-	}
-
-	cros_rtc_reset_alarm(cros_rtc_dev);
-}
-
-/*
- * For NPCX series, The alarm counter only stores wakeup time in seconds.
- * Microseconds will be ignored.
- */
-void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
-{
-	if (!cros_rtc_dev) {
-		LOG_ERR("rtc_dev hasn't initialized.");
-		return;
-	}
-
-	/* If time = 0, clear the current alarm */
-	if (seconds == EC_RTC_ALARM_CLEAR && microseconds == 0) {
-		system_reset_rtc_alarm();
-		return;
-	}
-
-	seconds += system_get_rtc_sec();
-
-	cros_rtc_set_alarm(cros_rtc_dev, seconds, microseconds);
-}
-
-/*
- * Return the seconds remaining before the RTC alarm goes off.
- * Returns 0 if alarm is not set.
- */
-uint32_t system_get_rtc_alarm(void)
-{
-	uint32_t seconds, microseconds;
-
-	cros_rtc_get_alarm(cros_rtc_dev, &seconds, &microseconds);
-
-	/*
-	 * Return 0:
-	 * 1. If alarm is not set to go off, OR
-	 * 2. If alarm is set and has already gone off
-	 */
-	if (seconds == 0) {
-		return 0;
-	}
-
-	return seconds - system_get_rtc_sec();
-}
-
-/* Console commands */
-void print_system_rtc(enum console_channel ch)
-{
-	uint32_t sec = system_get_rtc_sec();
-
-	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
-}
-
-/*
- * TODO(b/179055201): This is similar to the same function in some of the
- * chip-specific code. We should factor out the common parts.
- */
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
-{
-	if (argc == 3 && !strcasecmp(argv[1], "set")) {
-		char *e;
-		unsigned int t = strtoi(argv[2], &e, 0);
-
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		system_set_rtc(t);
-	} else if (argc > 1) {
-		return EC_ERROR_INVAL;
-	}
-
-	print_system_rtc(CC_COMMAND);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
-			"Get/set real-time clock");
-
-#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM
-/**
- * Test the RTC alarm by setting an interrupt on RTC match.
- */
-static int command_rtc_alarm_test(int argc, char **argv)
-{
-	int s = 1, us = 0;
-	char *e;
-
-	if (argc > 1) {
-		s = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-	if (argc > 2) {
-		us = strtoi(argv[2], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM2;
-	}
-
-	ccprintf("Setting RTC alarm\n");
-
-	system_set_rtc_alarm(s, us);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]", "Test alarm");
-#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM */
-#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC */
-
-#ifdef CONFIG_PLATFORM_EC_HOSTCMD_RTC
-static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_sec();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc(p->time);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
-{
-	const struct ec_params_rtc *p = args->params;
-
-	system_set_rtc_alarm(p->time, 0);
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
-		     EC_VER_MASK(0));
-
-static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
-{
-	struct ec_response_rtc *r = args->response;
-
-	r->time = system_get_rtc_alarm();
-	args->response_size = sizeof(*r);
-
-	return EC_RES_SUCCESS;
-}
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
-		     EC_VER_MASK(0));
-
-#endif /* CONFIG_PLATFORM_EC_HOSTCMD_RTC */
diff --git a/zephyr/shim/src/switchcap_gpio.c b/zephyr/shim/src/switchcap_gpio.c
deleted file mode 100644
index c635978b8b..0000000000
--- a/zephyr/shim/src/switchcap_gpio.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <devicetree.h>
-#include "common.h"
-#include "gpio.h"
-
-#if DT_NODE_EXISTS(DT_PATH(switchcap))
-
-#if !DT_NODE_HAS_COMPAT(DT_PATH(switchcap), switchcap_gpio)
-#error "Invalid /switchcap node in device tree"
-#endif
-
-#define SC_PIN_ENABLE_PHANDLE \
-	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_pin, 0)
-#define SC_PIN_ENABLE \
-	GPIO_SIGNAL(SC_PIN_ENABLE_PHANDLE)
-
-#define SC_PIN_POWER_GOOD_PHANDLE \
-	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), power_good_pin, 0)
-#define SC_PIN_POWER_GOOD_EXISTS \
-	DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE)
-#define SC_PIN_POWER_GOOD \
-	GPIO_SIGNAL(SC_PIN_POWER_GOOD_PHANDLE)
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(SC_PIN_ENABLE, enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return gpio_get_level(SC_PIN_ENABLE);
-}
-
-int board_is_switchcap_power_good(void)
-{
-#if SC_PIN_POWER_GOOD_EXISTS
-	return gpio_get_level(SC_PIN_POWER_GOOD);
-#else
-	return 1;
-#endif
-}
-
-#endif
diff --git a/zephyr/shim/src/switchcap_ln9310.c b/zephyr/shim/src/switchcap_ln9310.c
deleted file mode 100644
index 0647c2d9ae..0000000000
--- a/zephyr/shim/src/switchcap_ln9310.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <devicetree.h>
-#include "common.h"
-#include "gpio.h"
-#include "ln9310.h"
-
-#if DT_NODE_EXISTS(DT_PATH(switchcap))
-
-#if !DT_NODE_HAS_COMPAT(DT_PATH(switchcap), switchcap_ln9310)
-#error "Invalid /switchcap node in device tree"
-#endif
-
-#define SC_PIN_ENABLE_L_PHANDLE \
-	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_l_pin, 0)
-#define SC_PIN_ENABLE_L \
-	GPIO_SIGNAL(SC_PIN_ENABLE_L_PHANDLE)
-
-#define SC_PORT_PHANDLE \
-	DT_PHANDLE(DT_PATH(switchcap), port)
-#define SC_PORT DT_STRING_UPPER_TOKEN(SC_PORT_PHANDLE, enum_name)
-
-#define SC_ADDR_FLAGS DT_STRING_UPPER_TOKEN(DT_PATH(switchcap), addr_flags)
-
-void board_set_switchcap_power(int enable)
-{
-	gpio_set_level(SC_PIN_ENABLE_L, !enable);
-	ln9310_software_enable(enable);
-}
-
-int board_is_switchcap_enabled(void)
-{
-	return !gpio_get_level(SC_PIN_ENABLE_L);
-}
-
-int board_is_switchcap_power_good(void)
-{
-	return ln9310_power_good();
-}
-
-const struct ln9310_config_t ln9310_config = {
-	.i2c_port = SC_PORT,
-	.i2c_addr_flags = SC_ADDR_FLAGS,
-};
-
-#endif
diff --git a/zephyr/shim/src/system.c b/zephyr/shim/src/system.c
deleted file mode 100644
index 8db8ba437a..0000000000
--- a/zephyr/shim/src/system.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/bbram.h>
-#include <drivers/cros_system.h>
-#include <logging/log.h>
-
-#include "bbram.h"
-#include "common.h"
-#include "console.h"
-#include "cros_version.h"
-#include "system.h"
-#include "watchdog.h"
-
-#define BBRAM_REGION_PD0	DT_PATH(named_bbram_regions, pd0)
-#define BBRAM_REGION_PD1	DT_PATH(named_bbram_regions, pd1)
-#define BBRAM_REGION_PD2	DT_PATH(named_bbram_regions, pd2)
-#define BBRAM_REGION_TRY_SLOT	DT_PATH(named_bbram_regions, try_slot)
-
-#define GET_BBRAM_OFFSET(node) \
-	DT_PROP(DT_PATH(named_bbram_regions, node), offset)
-#define GET_BBRAM_SIZE(node) DT_PROP(DT_PATH(named_bbram_regions, node), size)
-
-/* 2 second delay for waiting the H1 reset */
-#define WAIT_RESET_TIME                                     \
-	(CONFIG_PLATFORM_EC_PREINIT_HW_CYCLES_PER_SEC * 2 / \
-	 CONFIG_PLATFORM_EC_WAIT_RESET_CYCLES_PER_ITERATION)
-
-LOG_MODULE_REGISTER(shim_system, LOG_LEVEL_ERR);
-
-STATIC_IF_NOT(CONFIG_ZTEST) const struct device *bbram_dev;
-static const struct device *sys_dev;
-
-/* Map idx to a bbram offset/size, or return -1 on invalid idx */
-static int bbram_lookup(enum system_bbram_idx idx, int *offset_out,
-			int *size_out)
-{
-	switch (idx) {
-	case SYSTEM_BBRAM_IDX_PD0:
-		*offset_out = DT_PROP(BBRAM_REGION_PD0, offset);
-		*size_out = DT_PROP(BBRAM_REGION_PD0, size);
-		break;
-	case SYSTEM_BBRAM_IDX_PD1:
-		*offset_out = DT_PROP(BBRAM_REGION_PD1, offset);
-		*size_out = DT_PROP(BBRAM_REGION_PD1, size);
-		break;
-	case SYSTEM_BBRAM_IDX_PD2:
-		*offset_out = DT_PROP(BBRAM_REGION_PD2, offset);
-		*size_out = DT_PROP(BBRAM_REGION_PD2, size);
-		break;
-	case SYSTEM_BBRAM_IDX_TRY_SLOT:
-		*offset_out = DT_PROP(BBRAM_REGION_TRY_SLOT, offset);
-		*size_out = DT_PROP(BBRAM_REGION_TRY_SLOT, size);
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-	return EC_SUCCESS;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	int offset, size, rc;
-
-	if (bbram_dev == NULL)
-		return EC_ERROR_INVAL;
-
-	rc = bbram_lookup(idx, &offset, &size);
-	if (rc)
-		return rc;
-
-	rc = bbram_read(bbram_dev, offset, size, value);
-
-	return rc ? EC_ERROR_INVAL : EC_SUCCESS;
-}
-
-void chip_save_reset_flags(uint32_t flags)
-{
-	if (bbram_dev == NULL) {
-		LOG_ERR("bbram_dev doesn't binding");
-		return;
-	}
-
-	bbram_write(bbram_dev, GET_BBRAM_OFFSET(saved_reset_flags),
-		    GET_BBRAM_SIZE(saved_reset_flags), (uint8_t *)&flags);
-}
-
-uint32_t chip_read_reset_flags(void)
-{
-	uint32_t flags;
-
-	if (bbram_dev == NULL) {
-		LOG_ERR("bbram_dev doesn't binding");
-		return 0;
-	}
-
-	bbram_read(bbram_dev, GET_BBRAM_OFFSET(saved_reset_flags),
-		   GET_BBRAM_SIZE(saved_reset_flags), (uint8_t *)&flags);
-
-	return flags;
-}
-
-int system_set_scratchpad(uint32_t value)
-{
-	if (bbram_dev == NULL) {
-		LOG_ERR("bbram_dev doesn't binding");
-		return -EC_ERROR_INVAL;
-	}
-
-	return bbram_write(bbram_dev, GET_BBRAM_OFFSET(scratchpad),
-			   GET_BBRAM_SIZE(scratchpad), (uint8_t *)&value);
-}
-
-int system_get_scratchpad(uint32_t *value)
-{
-	if (bbram_dev == NULL) {
-		LOG_ERR("bbram_dev doesn't binding");
-		return -EC_ERROR_INVAL;
-	}
-
-	if (bbram_read(bbram_dev, GET_BBRAM_OFFSET(scratchpad),
-		       GET_BBRAM_SIZE(scratchpad), (uint8_t *)value)) {
-		return -EC_ERROR_INVAL;
-	}
-
-	return 0;
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-	int err;
-
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* Save 'wake-up from hibernate' reset flag */
-	chip_save_reset_flags(chip_read_reset_flags() |
-			      EC_RESET_FLAG_HIBERNATE);
-
-	err = cros_system_hibernate(sys_dev, seconds, microseconds);
-	if (err < 0) {
-		LOG_ERR("hibernate failed %d", err);
-		return;
-	}
-
-	/* should never reach this point */
-	while (1)
-		continue;
-}
-
-#ifdef CONFIG_PM
-/**
- * Print low power idle statistics
- */
-static int command_idle_stats(int argc, char **argv)
-{
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-
-	timestamp_t ts = get_time();
-	uint64_t deep_sleep_ticks = cros_system_deep_sleep_ticks(sys_dev);
-
-	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-		 k_ticks_to_us_near64(deep_sleep_ticks));
-	ccprintf("Total time on:                       %.6llds\n", ts.val);
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
-#endif
-
-const char *system_get_chip_vendor(void)
-{
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-
-	return cros_system_chip_vendor(sys_dev);
-}
-
-const char *system_get_chip_name(void)
-{
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-
-	return cros_system_chip_name(sys_dev);
-}
-
-const char *system_get_chip_revision(void)
-{
-	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
-
-	return cros_system_chip_revision(sys_dev);
-}
-
-void system_reset(int flags)
-{
-	int err;
-	uint32_t save_flags;
-
-	if (!sys_dev)
-		LOG_ERR("sys_dev get binding failed");
-
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable_all();
-
-	/*  Get flags to be saved in BBRAM */
-	system_encode_save_flags(flags, &save_flags);
-
-	/* Store flags to battery backed RAM. */
-	chip_save_reset_flags(save_flags);
-
-	/* If WAIT_EXT is set, then allow 10 seconds for external reset */
-	if (flags & SYSTEM_RESET_WAIT_EXT) {
-		int i;
-
-		/* Wait 10 seconds for external reset */
-		for (i = 0; i < 1000; i++) {
-			watchdog_reload();
-			udelay(10000);
-		}
-	}
-
-	err = cros_system_soc_reset(sys_dev);
-
-	if (err < 0)
-		LOG_ERR("soc reset failed");
-
-	/* should never return */
-	while (1)
-		continue;
-}
-
-static int check_reset_cause(void)
-{
-	uint32_t chip_flags = 0; /* used to write back to the BBRAM */
-	uint32_t system_flags = chip_read_reset_flags(); /* system reset flag */
-	int chip_reset_cause = 0; /* chip-level reset cause */
-
-	chip_reset_cause = cros_system_get_reset_cause(sys_dev);
-	if (chip_reset_cause < 0)
-		return -1;
-
-	/*
-	 * TODO(b/182876692): Implement CONFIG_POWER_BUTTON_INIT_IDLE &
-	 * CONFIG_BOARD_FORCE_RESET_PIN.
-	 */
-
-	switch (chip_reset_cause) {
-	case POWERUP:
-		system_flags |= EC_RESET_FLAG_POWER_ON;
-		/*
-		 * Power-on restart, so set a flag and save it for the next
-		 * imminent reset. Later code will check for this flag and wait
-		 * for the second reset. Waking from PSL hibernate is power-on
-		 * for EC but not for H1, so do not wait for the second reset.
-		 */
-		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-		    ((system_flags & EC_RESET_FLAG_HIBERNATE) == 0)) {
-			system_flags |= EC_RESET_FLAG_INITIAL_PWR;
-			chip_flags |= EC_RESET_FLAG_INITIAL_PWR;
-		}
-		break;
-
-	case VCC1_RST_PIN:
-		/*
-		 * If configured, check the saved flags to see whether the
-		 * previous restart was a power-on, in which case treat this
-		 * restart as a power-on as well. This is to workaround the fact
-		 * that the H1 will reset the EC at power up.
-		 */
-		if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON)) {
-			if (system_flags & EC_RESET_FLAG_INITIAL_PWR) {
-				/*
-				 * The previous restart was a power-on so treat
-				 * this restart as that, and clear the flag so
-				 * later code will not wait for the second
-				 * reset.
-				 */
-				system_flags = (system_flags &
-						~EC_RESET_FLAG_INITIAL_PWR) |
-					       EC_RESET_FLAG_POWER_ON;
-			} else {
-				/*
-				 * No previous reset flag, so this is a
-				 * subsequent restart i.e any restarts after the
-				 * second restart caused by the H1.
-				 */
-				system_flags |= EC_RESET_FLAG_RESET_PIN;
-			}
-		} else {
-			system_flags |= EC_RESET_FLAG_RESET_PIN;
-		}
-		break;
-
-	case DEBUG_RST:
-		system_flags |= EC_RESET_FLAG_SOFT;
-		break;
-
-	case WATCHDOG_RST:
-		/*
-		 * Don't set EC_RESET_FLAG_WATCHDOG flag if watchdog is issued
-		 * by system_reset or hibernate in order to distinguish reset
-		 * cause is panic reason or not.
-		 */
-		if (!(system_flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
-				      EC_RESET_FLAG_HIBERNATE)))
-			system_flags |= EC_RESET_FLAG_WATCHDOG;
-		break;
-	}
-
-	/* Clear & set the reset flags for the following reset. */
-	chip_save_reset_flags(chip_flags);
-
-	/* Set the system reset flags. */
-	system_set_reset_flags(system_flags);
-
-	return 0;
-}
-
-static int system_preinitialize(const struct device *unused)
-{
-	ARG_UNUSED(unused);
-
-#if DT_NODE_EXISTS(DT_NODELABEL(bbram))
-	bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
-	if (!device_is_ready(bbram_dev)) {
-		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
-		return -1;
-	}
-#endif
-
-	sys_dev = device_get_binding("CROS_SYSTEM");
-	if (!sys_dev) {
-		/*
-		 * TODO(b/183022804): This should not happen in normal
-		 * operation. Check whether the error check can be change to
-		 * build-time error, or at least a fatal run-time error.
-		 */
-		LOG_ERR("sys_dev gets binding failed");
-		return -1;
-	}
-
-	/* check the reset cause */
-	if (check_reset_cause() != 0) {
-		LOG_ERR("check the reset cause failed");
-		return -1;
-	}
-
-	/*
-	 * For some boards on power-on, the EC is reset by the H1 after
-	 * power-on, so the EC sees 2 resets. This config enables the EC to save
-	 * a flag on the first power-up restart, and then wait for the second
-	 * reset before any other setup is done (such as GPIOs, timers, UART
-	 * etc.) On the second reset, the saved flag is used to detect the
-	 * previous power-on, and treat the second reset as a power-on instead
-	 * of a reset.
-	 */
-#ifdef CONFIG_BOARD_RESET_AFTER_POWER_ON
-	if (system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR) {
-		/*
-		 * The current initial stage couldn't use the kernel delay
-		 * function. Use CPU nop instruction to wait for the external
-		 * reset from H1.
-		 */
-		for (uint32_t i = WAIT_RESET_TIME; i; i--)
-			arch_nop();
-	}
-#endif
-	return 0;
-}
-
-SYS_INIT(system_preinitialize, PRE_KERNEL_1,
-	 CONFIG_PLATFORM_EC_SYSTEM_PRE_INIT_PRIORITY);
diff --git a/zephyr/shim/src/tasks.c b/zephyr/shim/src/tasks.c
deleted file mode 100644
index 2f1fec16d6..0000000000
--- a/zephyr/shim/src/tasks.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <init.h>
-#include <sys/atomic.h>
-#include <shell/shell.h>
-
-#include "common.h"
-#include "timer.h"
-#include "task.h"
-
-/* We need to ensure that is one lower priority for the deferred task */
-BUILD_ASSERT(CONFIG_NUM_PREEMPT_PRIORITIES + 1 >= TASK_ID_COUNT,
-	     "Must increase number of available preempt priorities");
-
-/* Declare all task stacks here */
-#define CROS_EC_TASK(name, e, p, size) \
-	K_THREAD_STACK_DEFINE(name##_STACK, size);
-#define TASK_TEST(name, e, p, size) CROS_EC_TASK(name, e, p, size)
-CROS_EC_TASK_LIST
-#undef CROS_EC_TASK
-#undef TASK_TEST
-
-/* Forward declare all task entry point functions */
-#define CROS_EC_TASK(name, entry, ...) void entry(void *p);
-#define TASK_TEST(name, entry, ...) CROS_EC_TASK(name, entry)
-CROS_EC_TASK_LIST
-#undef CROS_EC_TASK
-#undef TASK_TEST
-
-/** Context for each CROS EC task that is run in its own zephyr thread */
-struct task_ctx {
-#ifdef CONFIG_THREAD_NAME
-	/** Name of thread (for debugging) */
-	const char *name;
-#endif
-	/** Zephyr thread structure that hosts EC tasks */
-	struct k_thread zephyr_thread;
-	/** Zephyr thread id for above thread */
-	k_tid_t zephyr_tid;
-	/** Address of Zephyr thread's stack */
-	k_thread_stack_t *stack;
-	/** Usabled size in bytes of above thread stack */
-	size_t stack_size;
-	/** Task (platform/ec) entry point */
-	void (*entry)(void *p);
-	/** The parameter that is passed into the task entry point */
-	intptr_t parameter;
-	/** A wait-able event that is raised when a new task event is posted */
-	struct k_poll_signal new_event;
-	/** The current platform/ec events set for this task/thread */
-	uint32_t event_mask;
-	/**
-	 * The timer associated with this task, which can be set using
-	 * timer_arm().
-	 */
-	struct k_timer timer;
-};
-
-#ifdef CONFIG_THREAD_NAME
-#define CROS_EC_TASK(_name, _entry, _parameter, _size) \
-	{                                              \
-		.entry = _entry,                       \
-		.parameter = _parameter,               \
-		.stack = _name##_STACK,                \
-		.stack_size = _size,                   \
-		.name = #_name,                        \
-	},
-#else
-#define CROS_EC_TASK(_name, _entry, _parameter, _size) \
-	{                                              \
-		.entry = _entry,                       \
-		.parameter = _parameter,               \
-		.stack = _name##_STACK,                \
-		.stack_size = _size,                   \
-	},
-#endif /* CONFIG_THREAD_NAME */
-#define TASK_TEST(_name, _entry, _parameter, _size) \
-	CROS_EC_TASK(_name, _entry, _parameter, _size)
-static struct task_ctx shimmed_tasks[] = {
-	CROS_EC_TASK_LIST
-#ifdef TEST_BUILD
-	[TASK_ID_TEST_RUNNER] = {},
-#endif
-};
-static int tasks_started;
-#undef CROS_EC_TASK
-#undef TASK_TEST
-
-task_id_t task_get_current(void)
-{
-	for (size_t i = 0; i < ARRAY_SIZE(shimmed_tasks); ++i) {
-		if (shimmed_tasks[i].zephyr_tid == k_current_get()) {
-			return i;
-		}
-	}
-
-#if defined(HAS_TASK_HOOKS)
-	/* Hooks ID should be returned for deferred calls */
-	if (k_current_get() == &k_sys_work_q.thread) {
-		return TASK_ID_HOOKS;
-	}
-#endif /* HAS_TASK_HOOKS */
-
-	__ASSERT(false, "Task index out of bound");
-	return 0;
-}
-
-uint32_t *task_get_event_bitmap(task_id_t cros_task_id)
-{
-	struct task_ctx *const ctx = &shimmed_tasks[cros_task_id];
-
-	return &ctx->event_mask;
-}
-
-uint32_t task_set_event(task_id_t cros_task_id, uint32_t event)
-{
-	struct task_ctx *const ctx = &shimmed_tasks[cros_task_id];
-
-	atomic_or(&ctx->event_mask, event);
-	k_poll_signal_raise(&ctx->new_event, 0);
-
-	return 0;
-}
-
-uint32_t task_wait_event(int timeout_us)
-{
-	struct task_ctx *const ctx = &shimmed_tasks[task_get_current()];
-	const k_timeout_t timeout = (timeout_us == -1) ? K_FOREVER :
-							 K_USEC(timeout_us);
-	const int64_t tick_deadline =
-		k_uptime_ticks() + k_us_to_ticks_near64(timeout_us);
-
-	struct k_poll_event poll_events[1] = {
-		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL,
-					 K_POLL_MODE_NOTIFY_ONLY,
-					 &ctx->new_event),
-	};
-
-	/* Wait for signal, then clear it before reading events */
-	const int rv = k_poll(poll_events, ARRAY_SIZE(poll_events), timeout);
-
-	k_poll_signal_reset(&ctx->new_event);
-	uint32_t events = atomic_set(&ctx->event_mask, 0);
-
-	if (rv == -EAGAIN) {
-		events |= TASK_EVENT_TIMER;
-	}
-
-	/* If we didn't get an event, we need to wait again. There is a very
-	 * small change of us reading the event_mask one signaled event too
-	 * early. In that case, just wait again for the remaining timeout
-	 */
-	if (events == 0) {
-		const int64_t ticks_left = tick_deadline - k_uptime_ticks();
-
-		if (ticks_left > 0) {
-			return task_wait_event(
-				k_ticks_to_us_near64(ticks_left));
-		}
-
-		events |= TASK_EVENT_TIMER;
-	}
-
-	return events;
-}
-
-uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
-{
-	struct task_ctx *const ctx = &shimmed_tasks[task_get_current()];
-	uint32_t events = 0;
-	const int64_t tick_deadline =
-		k_uptime_ticks() + k_us_to_ticks_near64(timeout_us);
-
-	/*  Need to return timeout flags if it occurs as well */
-	event_mask |= TASK_EVENT_TIMER;
-
-	while (!(event_mask & events)) {
-		const int64_t ticks_left = tick_deadline - k_uptime_ticks();
-
-		if (timeout_us != -1 && ticks_left <= 0) {
-			events |= TASK_EVENT_TIMER;
-			break;
-		}
-
-		struct k_poll_event poll_events[1] = {
-			K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL,
-						 K_POLL_MODE_NOTIFY_ONLY,
-						 &ctx->new_event),
-		};
-
-		/* Ensure to honor the -1 timeout as FOREVER */
-		k_poll(poll_events, ARRAY_SIZE(poll_events),
-		       timeout_us == -1 ? K_FOREVER : K_TICKS(ticks_left));
-		k_poll_signal_reset(&ctx->new_event);
-		events |= atomic_set(&ctx->event_mask, 0);
-	}
-
-	/* Replace any events that weren't in the mask */
-	if (events & ~event_mask) {
-		atomic_or(&ctx->event_mask, events & ~event_mask);
-		k_poll_signal_raise(&ctx->new_event, 0);
-	}
-
-	return events & event_mask;
-}
-
-static void task_entry(void *task_contex, void *unused1, void *unused2)
-{
-	ARG_UNUSED(unused1);
-	ARG_UNUSED(unused2);
-
-	struct task_ctx *const ctx = (struct task_ctx *)task_contex;
-
-#ifdef CONFIG_THREAD_NAME
-	/* Name thread for debugging */
-	k_thread_name_set(ctx->zephyr_tid, ctx->name);
-#endif
-
-	/* Call into task entry point */
-	ctx->entry((void *)ctx->parameter);
-}
-
-/*
- * Callback function to use with k_timer_start to set the
- * TASK_EVENT_TIMER event on a task.
- */
-static void timer_expire(struct k_timer *timer_id)
-{
-	struct task_ctx *const ctx =
-		CONTAINER_OF(timer_id, struct task_ctx, timer);
-	task_id_t cros_ec_task_id = ctx - shimmed_tasks;
-
-	task_set_event(cros_ec_task_id, TASK_EVENT_TIMER);
-}
-
-int timer_arm(timestamp_t event, task_id_t cros_ec_task_id)
-{
-	timestamp_t now = get_time();
-	struct task_ctx *const ctx = &shimmed_tasks[cros_ec_task_id];
-
-	if (event.val <= now.val) {
-		/* Timer requested for now or in the past, fire right away */
-		task_set_event(cros_ec_task_id, TASK_EVENT_TIMER);
-		return EC_SUCCESS;
-	}
-
-	/* Check for a running timer */
-	if (k_timer_remaining_get(&ctx->timer))
-		return EC_ERROR_BUSY;
-
-	k_timer_start(&ctx->timer, K_USEC(event.val - now.val), K_NO_WAIT);
-	return EC_SUCCESS;
-}
-
-void timer_cancel(task_id_t cros_ec_task_id)
-{
-	struct task_ctx *const ctx = &shimmed_tasks[cros_ec_task_id];
-
-	k_timer_stop(&ctx->timer);
-}
-
-#ifdef TEST_BUILD
-void set_test_runner_tid(void)
-{
-	shimmed_tasks[TASK_ID_TEST_RUNNER].zephyr_tid = k_current_get();
-}
-#endif
-
-void start_ec_tasks(void)
-{
-	for (size_t i = 0; i < ARRAY_SIZE(shimmed_tasks); ++i) {
-		struct task_ctx *const ctx = &shimmed_tasks[i];
-
-		k_timer_init(&ctx->timer, timer_expire, NULL);
-
-#ifdef TEST_BUILD
-		/* Do not create thread for test runner; it will be set later */
-		if (i == TASK_ID_TEST_RUNNER) {
-			ctx->zephyr_tid = NULL;
-			continue;
-		}
-#endif
-		/*
-		 * TODO(b/172361873): Add K_FP_REGS for FPU tasks. See
-		 * comment in config.h for CONFIG_TASK_LIST for existing flags
-		 * implementation.
-		 */
-		ctx->zephyr_tid = k_thread_create(
-			&ctx->zephyr_thread, ctx->stack, ctx->stack_size,
-			task_entry, ctx, NULL, NULL,
-			K_PRIO_PREEMPT(TASK_ID_COUNT - i - 1), 0, K_NO_WAIT);
-	}
-	tasks_started = 1;
-}
-
-/*
- * Initialize all of the kernel objects before application code starts.
- * This allows us to set events on tasks before they even start, e.g. in
- * INIT_HOOKS.
- */
-int init_signals(const struct device *unused)
-{
-	ARG_UNUSED(unused);
-
-	for (size_t i = 0; i < ARRAY_SIZE(shimmed_tasks); ++i) {
-		struct task_ctx *const ctx = &shimmed_tasks[i];
-
-		/* Initialize the new_event structure */
-		k_poll_signal_init(&ctx->new_event);
-	}
-
-	return 0;
-}
-SYS_INIT(init_signals, POST_KERNEL, 50);
-
-int task_start_called(void)
-{
-	return tasks_started;
-}
-
-void task_disable_task(task_id_t tskid)
-{
-	/* TODO(b/190203712): Implement this */
-}
-
-void task_clear_pending_irq(int irq)
-{
-#if CONFIG_ITE_IT8XXX2_INTC
-	ite_intc_isr_clear(irq);
-#endif
-}
-
-void task_enable_irq(int irq)
-{
-	arch_irq_enable(irq);
-}
-
-inline int in_interrupt_context(void)
-{
-	return k_is_in_isr();
-}
-
-#if IS_ENABLED(CONFIG_KERNEL_SHELL) && IS_ENABLED(CONFIG_THREAD_MONITOR)
-static int taskinfo(const struct shell *shell, size_t argc, char **argv)
-{
-	return shell_execute_cmd(shell, "kernel threads");
-}
-SHELL_CMD_REGISTER(taskinfo, NULL, "Threads statistics", taskinfo);
-#endif
diff --git a/zephyr/shim/src/temp_sensors.c b/zephyr/shim/src/temp_sensors.c
deleted file mode 100644
index 4d8be4fa42..0000000000
--- a/zephyr/shim/src/temp_sensors.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "temp_sensor.h"
-#include "temp_sensor/temp_sensor.h"
-#include "adc.h"
-#include "temp_sensor/thermistor.h"
-
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
-static int thermistor_get_temp(const struct temp_sensor_t *sensor,
-			       int *temp_ptr)
-{
-	return thermistor_get_temperature(sensor->idx, temp_ptr,
-					  sensor->thermistor);
-}
-
-#define GET_THERMISTOR_DATUM(node_sample_id)                                 \
-	[DT_PROP(node_sample_id,                                             \
-		 sample_index)] = { .mv = DT_PROP(node_sample_id, milivolt), \
-				    .temp = DT_PROP(node_sample_id, temp) },
-
-#define DEFINE_THERMISTOR_DATA(node_id)                         \
-	static const struct thermistor_data_pair DT_CAT(        \
-		node_id, _thermistor_data)[] = {                \
-		DT_FOREACH_CHILD(node_id, GET_THERMISTOR_DATUM) \
-	};
-
-#define GET_THERMISTOR_INFO(node_id)                                \
-	(&(struct thermistor_info){                                 \
-		.scaling_factor = DT_PROP(node_id, scaling_factor), \
-		.num_pairs = DT_PROP(node_id, num_pairs),           \
-		.data = DT_CAT(node_id, _thermistor_data),          \
-	})
-
-#define TEMP_THERMISTOR(node_id)                                              \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {                                   \
-		.name = DT_LABEL(node_id),                                    \
-		.read = &thermistor_get_temp,                                 \
-		.idx = ZSHIM_ADC_ID(DT_PHANDLE(node_id, adc)),                \
-		.type = TEMP_SENSOR_TYPE_BOARD,                               \
-		.thermistor =                                                 \
-			GET_THERMISTOR_INFO(DT_PHANDLE(node_id, thermistor)), \
-	},
-
-DT_FOREACH_STATUS_OKAY(cros_ec_thermistor, DEFINE_THERMISTOR_DATA)
-
-const struct temp_sensor_t temp_sensors[] = {
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, TEMP_THERMISTOR)
-};
-#endif /* named_temp_sensors */
diff --git a/zephyr/shim/src/test_util.c b/zephyr/shim/src/test_util.c
deleted file mode 100644
index 28be596043..0000000000
--- a/zephyr/shim/src/test_util.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test utilities.
- */
-
-#include "test_util.h"
-
-/* Linear congruential pseudo random number generator */
-uint32_t prng(uint32_t seed)
-{
-	return 22695477 * seed + 1;
-}
-
-uint32_t prng_no_seed(void)
-{
-	static uint32_t seed = 0x1234abcd;
-	return seed = prng(seed);
-}
diff --git a/zephyr/shim/src/thermal.c b/zephyr/shim/src/thermal.c
deleted file mode 100644
index c31e2bfcc6..0000000000
--- a/zephyr/shim/src/thermal.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "temp_sensor.h"
-#include "temp_sensor/temp_sensor.h"
-#include "ec_commands.h"
-
-#define THERMAL_CONFIG(node_id)					\
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {				\
-		.temp_host = {						\
-			[EC_TEMP_THRESH_WARN] =			\
-			C_TO_K(DT_PROP_OR(node_id,			\
-					  temp_host_warn,		\
-					  -273)),			\
-			[EC_TEMP_THRESH_HIGH] =			\
-			C_TO_K(DT_PROP_OR(node_id,			\
-					  temp_host_high,		\
-					  -273)),			\
-			[EC_TEMP_THRESH_HALT] =			\
-			C_TO_K(DT_PROP_OR(node_id,			\
-					  temp_host_halt,		\
-					  -273)),			\
-		},							\
-		.temp_host_release = {					\
-			[EC_TEMP_THRESH_WARN] = C_TO_K(		\
-				DT_PROP_OR(node_id,			\
-					   temp_host_release_warn,	\
-					   -273)),			\
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(		\
-				DT_PROP_OR(node_id,			\
-					   temp_host_release_high,	\
-					   -273)),			\
-			[EC_TEMP_THRESH_HALT] = C_TO_K(		\
-				DT_PROP_OR(node_id,			\
-					   temp_host_release_halt,	\
-					   -273)),			\
-		},							\
-		.temp_fan_off = C_TO_K(DT_PROP_OR(node_id,		\
-						  temp_fan_off,	\
-						  -273)),		\
-		.temp_fan_max = C_TO_K(DT_PROP_OR(node_id,		\
-						  temp_fan_max,	\
-						  -273)),		\
-	},
-
-struct ec_thermal_config thermal_params[] = {
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), THERMAL_CONFIG)
-#endif /* named_temp_sensors */
-};
diff --git a/zephyr/shim/src/watchdog.c b/zephyr/shim/src/watchdog.c
deleted file mode 100644
index 4c78ac9b0f..0000000000
--- a/zephyr/shim/src/watchdog.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/watchdog.h>
-#include <logging/log.h>
-#include <zephyr.h>
-
-#include "config.h"
-#include "hooks.h"
-#include "watchdog.h"
-
-LOG_MODULE_REGISTER(watchdog_shim, LOG_LEVEL_ERR);
-
-static void wdt_warning_handler(const struct device *wdt_dev, int channel_id)
-{
-	/* TODO(b/176523207): watchdog warning message */
-	printk("Watchdog deadline is close!\n");
-}
-
-int watchdog_init(void)
-{
-	int err;
-	const struct device *wdt;
-	struct wdt_timeout_cfg wdt_config;
-
-	wdt = DEVICE_DT_GET(DT_NODELABEL(twd0));
-	if (!device_is_ready(wdt)) {
-		LOG_ERR("Error: device %s is not ready", wdt->name);
-		return -1;
-	}
-
-	/* Reset SoC when watchdog timer expires. */
-	wdt_config.flags = WDT_FLAG_RESET_SOC;
-
-	/*
-	 * Set the Warning timer as CONFIG_AUX_TIMER_PERIOD_MS.
-	 * Then the watchdog reset time = CONFIG_WATCHDOG_PERIOD_MS.
-	 */
-	wdt_config.window.min = 0U;
-	wdt_config.window.max = CONFIG_AUX_TIMER_PERIOD_MS;
-	wdt_config.callback = wdt_warning_handler;
-
-	err = wdt_install_timeout(wdt, &wdt_config);
-
-	/* If watchdog is running, reinstall it. */
-	if (err == -EBUSY) {
-		wdt_disable(wdt);
-		err = wdt_install_timeout(wdt, &wdt_config);
-	}
-
-	if (err < 0) {
-		LOG_ERR("Watchdog install error");
-		return err;
-	}
-
-	err = wdt_setup(wdt, 0);
-	if (err < 0) {
-		LOG_ERR("Watchdog setup error");
-		return err;
-	}
-
-	return EC_SUCCESS;
-}
-
-void watchdog_reload(void)
-{
-	const struct device *wdt;
-
-	wdt = DEVICE_DT_GET(DT_NODELABEL(twd0));
-	if (!device_is_ready(wdt))
-		LOG_ERR("Error: device %s is not ready", wdt->name);
-
-	wdt_feed(wdt, 0);
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/shim/src/ztest_system.c b/zephyr/shim/src/ztest_system.c
deleted file mode 100644
index 14796b5bd5..0000000000
--- a/zephyr/shim/src/ztest_system.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "system.h"
-#include "cros_version.h"
-
-/* Ongoing actions preventing going into deep-sleep mode. */
-uint32_t sleep_mask;
-
-void system_common_pre_init(void)
-{
-}
-
-int system_add_jump_tag(uint16_t tag, int version, int size, const void *data)
-{
-	return EC_SUCCESS;
-}
-
-const uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
-{
-	return NULL;
-}
-
-int system_jumped_late(void)
-{
-	return 0;
-}
-
-enum ec_image system_get_image_copy(void)
-{
-	return EC_IMAGE_RW;
-}
-
-int system_is_locked(void)
-{
-	return 0;
-}
-
-int system_is_in_rw(void)
-{
-	return 1;
-}
-
-uint32_t system_get_reset_flags(void)
-{
-	return 0;
-}
-
-void system_print_banner(void)
-{
-	printk("Image: %s\n", build_info);
-}
-
-void system_set_reset_flags(uint32_t flags)
-{
-}
-
-struct jump_data *get_jump_data(void)
-{
-	return NULL;
-}
-
-__attribute__((weak))
-void system_reset(int flags)
-{
-	__builtin_unreachable();
-}
diff --git a/zephyr/test/accel_cal/CMakeLists.txt b/zephyr/test/accel_cal/CMakeLists.txt
deleted file mode 100644
index 14fd70e01a..0000000000
--- a/zephyr/test/accel_cal/CMakeLists.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(accel_cal)
-
-# Ensure that we get the definitions from test_config.h
-zephyr_compile_definitions("TEST_ACCEL_CAL")
-
-# Include the local test directory for shimmed_test_tasks.h
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-
-# Include test file and unit under test
-target_sources(app PRIVATE
-	"${PLATFORM_EC}/test/accel_cal.c"
-	"${PLATFORM_EC}/common/accel_cal.c"
-	"${PLATFORM_EC}/common/kasa.c"
-	"${PLATFORM_EC}/common/mat44.c"
-	"${PLATFORM_EC}/common/math_util.c"
-	"${PLATFORM_EC}/common/newton_fit.c"
-	"${PLATFORM_EC}/common/stillness_detector.c"
-	"${PLATFORM_EC}/common/vec3.c")
diff --git a/zephyr/test/accel_cal/prj.conf b/zephyr/test/accel_cal/prj.conf
deleted file mode 100644
index 5efe3ec6b7..0000000000
--- a/zephyr/test/accel_cal/prj.conf
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_HAS_TEST_TASKS=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
diff --git a/zephyr/test/accel_cal/shimmed_test_tasks.h b/zephyr/test/accel_cal/shimmed_test_tasks.h
deleted file mode 100644
index ff221a5ba3..0000000000
--- a/zephyr/test/accel_cal/shimmed_test_tasks.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "accel_cal.tasklist"
diff --git a/zephyr/test/accel_cal/zmake.yaml b/zephyr/test/accel_cal/zmake.yaml
deleted file mode 100644
index decc749ae1..0000000000
--- a/zephyr/test/accel_cal/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/test/base32/CMakeLists.txt b/zephyr/test/base32/CMakeLists.txt
deleted file mode 100644
index 674ad0d244..0000000000
--- a/zephyr/test/base32/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(base32)
-
-target_sources(app PRIVATE "${PLATFORM_EC}/test/base32.c")
diff --git a/zephyr/test/base32/prj.conf b/zephyr/test/base32/prj.conf
deleted file mode 100644
index ec8c5035f5..0000000000
--- a/zephyr/test/base32/prj.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
diff --git a/zephyr/test/base32/zmake.yaml b/zephyr/test/base32/zmake.yaml
deleted file mode 100644
index 6aa10c2661..0000000000
--- a/zephyr/test/base32/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/test/crc/CMakeLists.txt b/zephyr/test/crc/CMakeLists.txt
deleted file mode 100644
index 0b46729578..0000000000
--- a/zephyr/test/crc/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(crc)
-
-# Include the test source and the file under test
-target_sources(app PRIVATE main.c)
diff --git a/zephyr/test/crc/main.c b/zephyr/test/crc/main.c
deleted file mode 100644
index 34fec7199a..0000000000
--- a/zephyr/test/crc/main.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <ztest.h>
-
-#include "crc8.h"
-
-/* Note this test makes the pure platform/ec test that uses the same value */
-static void test_crc8_known_data(void)
-{
-	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
-
-	int crc = cros_crc8(buffer, 10);
-
-	/* Verifies polynomial values of 0x07 representing x^8 + x^2 + x + 1 */
-	zassert_equal(crc, 170, "CRC8 hash did not match");
-}
-
-void test_main(void)
-{
-	ztest_test_suite(test_task_shim,
-			 ztest_unit_test(test_crc8_known_data));
-	ztest_run_test_suite(test_task_shim);
-}
diff --git a/zephyr/test/crc/prj.conf b/zephyr/test/crc/prj.conf
deleted file mode 100644
index ec8c5035f5..0000000000
--- a/zephyr/test/crc/prj.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
diff --git a/zephyr/test/crc/zmake.yaml b/zephyr/test/crc/zmake.yaml
deleted file mode 100644
index 6aa10c2661..0000000000
--- a/zephyr/test/crc/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt
deleted file mode 100644
index c90b334e60..0000000000
--- a/zephyr/test/drivers/CMakeLists.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(drivers)
-
-# Include the local test directory for shimmed_test_tasks.h
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
-zephyr_include_directories("${PLATFORM_EC}/driver/ppc/")
-
-FILE(GLOB test_sources src/*.c)
-target_sources(app PRIVATE ${test_sources})
-
-target_sources(app PRIVATE "${PLATFORM_EC}/test/cbi.c")
diff --git a/zephyr/test/drivers/README.md b/zephyr/test/drivers/README.md
deleted file mode 100644
index 8ea3dcdde1..0000000000
--- a/zephyr/test/drivers/README.md
+++ /dev/null
@@ -1,50 +0,0 @@
-This is the combined driver test. The goal is to have many driver test suites
-in one binary, so that compile time will be faster than many small tests, and
-so we can test interactions between different subsystems easily.
-
-## Run all the test suites
-
-```bash
-(chroot) zmake configure --test zephyr/test/drivers
-```
-
-To see all the output of zmake (for example if the build fails)
-
-```bash
-(chroot) zmake -l DEBUG -j 1 configure --test zephyr/test/drivers
-```
-
-## Code coverage
-
-To calculate code coverage for this test only
-
-```bash
-(chroot) zmake configure --coverage --test zephyr/test/drivers
-(chroot) lcov --gcov-tool ~/trunk/src/platform/ec/util/llvm-gcov.sh -q \
-        -o build/zephyr/test/drivers/lcov.info -c -d build/zephyr/test/drivers
-(chroot) genhtml -q -o build/zephyr/test/drivers/coverage_rpt \
-        build/zephyr/test/drivers/lcov.info
-```
-
-The report will be in build/zephyr/test/drivers/coverage_rpt/index.html
-
-## Debugging
-
-You need the host version of gdb:
-
-```bash
-(chroot) sudo emerge -j sys-devel/gdb
-```
-
-Build the test
-```bash
-(chroot) zmake configure --build zephyr/test/drivers
-```
-
-Then run gdb
-
-```
-(chroot) gdb build/zephyr/test/drivers/build-singleimage/zephyr/zephyr.exe
-# Set breakpoints, run, etc.
-```
-
diff --git a/zephyr/test/drivers/include/gpio_map.h b/zephyr/test/drivers/include/gpio_map.h
deleted file mode 100644
index 1f67138bd2..0000000000
--- a/zephyr/test/drivers/include/gpio_map.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <devicetree.h>
-#include <gpio_signal.h>
-
-/*
- * Without https://github.com/zephyrproject-rtos/zephyr/pull/29282, we need
- * to manually link GPIO_ defines that platform/ec code expects to the
- * enum gpio_signal values that are generated by device tree bindings.
- *
- * Note we only need to create aliases for GPIOs that are referenced in common
- * platform/ec code.
- */
-#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PG_EC_DSW_PWROK
-
-#define EC_CROS_GPIO_INTERRUPTS                                           \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/test/drivers/include/stubs.h b/zephyr/test/drivers/include/stubs.h
deleted file mode 100644
index 1ae0f3a50d..0000000000
--- a/zephyr/test/drivers/include/stubs.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "power.h"
-
-enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
-
-void set_mock_power_state(enum power_state state);
diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts
deleted file mode 100644
index b211d77caa..0000000000
--- a/zephyr/test/drivers/overlay.dts
+++ /dev/null
@@ -1,561 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/gpio_defines.h>
-#include <cros/thermistor/thermistor.dtsi>
-
-/ {
-	aliases {
-		bmi260-int = &ms_bmi260_accel;
-		bmi160-int = &ms_bmi160_accel;
-		lis2dw12-int = &ms_lis2dw12_accel;
-		tcs3400-int = &tcs3400_clear;
-	};
-	named-gpios {
-		compatible = "named-gpios";
-
-		ec_batt_pres_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-			enum-name = "GPIO_BATT_PRES_ODL";
-			label = "EC_BATT_PRES_ODL";
-		};
-		acok_od {
-			gpios = <&gpio0 2 GPIO_INPUT>;
-			enum-name = "GPIO_AC_PRESENT";
-			label = "ACOK_OD";
-		};
-		/* In test WP is output because CBI use it, but it is also
-		 * input, because test_all_tags set it to enable write
-		 * protection.
-		 */
-		gpio_wp_l: wp_l {
-			#gpio-cells = <0>;
-			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_OUTPUT)>;
-			enum-name = "GPIO_WP_L";
-			label = "WP_L";
-		};
-		pg_ec_dsw_pwrok {
-			gpios = <&gpio0 4 GPIO_INPUT>;
-			enum-name = "GPIO_PG_EC_DSW_PWROK";
-			label = "PG_EC_DSW_PWROK";
-		};
-		ec_pch_wake_odl {
-			gpios = <&gpio0 5 GPIO_OUT_HIGH>;
-			enum-name = "GPIO_EC_PCH_WAKE_ODL";
-			label = "EC_PCH_WAKE_ODL";
-		};
-		/* Setup USB C1 pin as output to check their state in test */
-		usb_c1_ls_en {
-			gpios = <&gpio0 6 (GPIO_INPUT | GPIO_PULL_UP |
-					   GPIO_OUTPUT)>;
-			enum-name = "GPIO_USB_C1_LS_EN";
-			label = "USB_C1_LS_EN";
-		};
-		usb_c1_rt_rst_odl {
-			gpios = <&gpio0 7 (GPIO_OUTPUT | GPIO_INPUT)>;
-			enum-name = "GPIO_USB_C1_RT_RST_ODL";
-			label = "USB_C1_RT_RST_ODL";
-		};
-	};
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		usb-c0 {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_USB_C0";
-			label = "USB_C0";
-		};
-		usb-c1 {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_USB_C1";
-			label = "USB_C1";
-		};
-		battery {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_BATTERY";
-			label = "BATTERY";
-		};
-		power {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_POWER";
-			label = "POWER";
-		};
-		charger {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_CHARGER";
-			label = "CHARGER";
-		};
-		eeprom {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EEPROM";
-			label = "EEPROM";
-		};
-		i2c_accel: accel {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_SENSOR";
-			label = "SENSOR";
-		};
-	};
-
-	named-batteries {
-		compatible = "named-batteries";
-
-		lgc011 {
-			enum-name = "lgc011";
-		};
-	};
-
-	adc0: adc {
-		compatible = "zephyr,adc-emul";
-		nchannels = <4>;
-		ref-internal-mv = <3300>;
-		#io-channel-cells = <1>;
-		label = "ADC_0";
-		status = "okay";
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_charger: charger {
-			label = "ADC_TEMP_SENSOR_CHARGER";
-			enum-name = "ADC_TEMP_SENSOR_CHARGER";
-			channel = <0>;
-		};
-		adc_pp3300_regulator: pp3300-regulator {
-			label = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
-			enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
-			channel = <1>;
-		};
-		adc_ddr_soc: ddr-soc {
-			label = "ADC_TEMP_SENSOR_DDR_SOC";
-			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
-			channel = <2>;
-		};
-		adc_fan: fan {
-			label = "ADC_TEMP_SENSOR_FAN";
-			enum-name = "ADC_TEMP_SENSOR_FAN";
-			channel = <3>;
-		};
-	};
-
-	named-temp-sensors {
-		charger {
-			thermistor = <&thermistor_3V3_13K7_47K_4050B>;
-			status = "okay";
-			compatible = "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_CHARGER";
-			enum-name = "TEMP_SENSOR_CHARGER";
-			temp_fan_off = <40>;
-			temp_fan_max = <55>;
-			temp_host_high = <75>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_charger>;
-		};
-		pp3300-regulator {
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			status = "okay";
-			compatible = "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_PP3300_REGULATOR";
-			enum-name = "TEMP_SENSOR_PP3300_REGULATOR";
-			temp_fan_off = <40>;
-			temp_fan_max = <55>;
-			temp_host_high = <75>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_pp3300_regulator>;
-		};
-		ddr-soc {
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			status = "okay";
-			compatible = "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_DDR_SOC";
-			enum-name = "TEMP_SENSOR_DDR_SOC";
-			temp_fan_off = <35>;
-			temp_fan_max = <50>;
-			temp_host_high = <70>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_ddr_soc>;
-		};
-		fan {
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
-			status = "okay";
-			compatible = "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_FAN";
-			enum-name = "TEMP_SENSOR_FAN";
-			temp_fan_off = <35>;
-			temp_fan_max = <50>;
-			temp_host_high = <70>;
-			temp_host_halt = <80>;
-			temp_host_release_high = <65>;
-			adc = <&adc_fan>;
-		};
-	};
-
-	/*
-	 * Declare mutexes used by sensor drivers.
-	 * A mutex node is used to create an instance of mutex_t.
-	 * A mutex node is referenced by a sensor node if the
-	 * corresponding sensor driver needs to use the
-	 * instance of the mutex.
-	 */
-	motionsense-mutex {
-		compatible = "cros-ec,motionsense-mutex";
-		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
-		};
-
-		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
-		};
-
-		mutex_lis2dw12: lis2dw12-mutex {
-			label = "LIS2DW12_MUTEX";
-		};
-	};
-
-	/*
-	 * Driver specific data. A driver-specific data can be shared with
-	 * different motion sensors while they are using the same driver.
-	 */
-	motionsense-sensor-data {
-		bmi260_data: bmi260-drv-data {
-			compatible = "cros-ec,drvdata-bmi260";
-			status = "okay";
-		};
-
-		bmi160_data: bmi160-drv-data {
-			compatible = "cros-ec,drvdata-bmi160";
-			status = "okay";
-		};
-
-		lis2dw12_data: lis2dw12-drv-data {
-			compatible = "cros-ec,drvdata-lis2dw12";
-			status = "okay";
-		};
-
-		tcs_clear_data: tcs3400-clear-drv-data {
-			compatible = "cros-ec,drvdata-tcs3400-clear";
-			status = "okay";
-
-			als-drv-data {
-				compatible = "cros-ec,accelgyro-als-drv-data";
-				als-cal {
-					scale = <1>;
-					uscale = <0>;
-					offset = <0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-			};
-		};
-
-		tcs_rgb_data: tcs3400-rgb-drv-data {
-			compatible = "cros-ec,drvdata-tcs3400-rgb";
-			status = "okay";
-
-			/* node for rgb_calibration_t defined in accelgyro.h */
-			rgb_calibration {
-				compatible =
-					"cros-ec,accelgyro-rgb-calibration";
-
-				irt = <1>;
-
-				rgb-cal-x {
-					offset = <0>;
-					coeff = <0 1 0 0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-				rgb-cal-y {
-					offset = <0>;
-					coeff = <0 0 1 0>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-				rgb-cal-z {
-					offset = <0>;
-					coeff = <0 0 0 1>;
-					als-channel-scale {
-					compatible =
-					"cros-ec,accelgyro-als-channel-scale";
-						k-channel-scale = <1>;
-						cover-scale = <1>;
-					};
-				};
-			};
-		};
-	};
-
-	/*
-	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
-	 * motion sensor IDs for lid angle calculation.
-	 */
-	motionsense-sensor {
-		ms_bmi260_accel: ms-bmi260-accel {
-			compatible = "cros-ec,bmi260-accel";
-			status = "okay";
-
-			label = "BMI260 emul accel";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_accel>;
-			drv-data = <&bmi260_data>;
-			default-range = <4>;
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-		};
-
-		ms_bmi260_gyro: ms-bmi260-gyro {
-			compatible = "cros-ec,bmi260-gyro";
-			status = "okay";
-
-			label = "BMI260 emul gyro";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi260>;
-			port = <&i2c_accel>;
-			drv-data = <&bmi260_data>;
-			default-range = <1000>; /* dps */
-			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
-		};
-
-		ms_bmi160_accel: ms-bmi160-accel {
-			compatible = "cros-ec,bmi160-accel";
-			status = "okay";
-
-			label = "BMI160 emul accel";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			drv-data = <&bmi160_data>;
-			default-range = <4>;
-			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
-		};
-
-		ms_bmi160_gyro: ms-bmi160-gyro {
-			compatible = "cros-ec,bmi160-gyro";
-			status = "okay";
-
-			label = "BMI160 emul gyro";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
-			drv-data = <&bmi160_data>;
-			default-range = <1000>; /* dps */
-			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
-		};
-
-		ms_lis2dw12_accel: ms-lis2dw12-accel {
-			compatible = "cros-ec,lis2dw12";
-			status = "okay";
-
-			label = "LIS2DW12";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&mutex_lis2dw12>;
-			port = <&i2c_accel>;
-			drv-data = <&lis2dw12_data>;
-			default-range = <2>;
-			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
-		};
-
-		tcs3400_clear: tcs3400-clear {
-			compatible = "cros-ec,tcs3400-clear";
-			status = "okay";
-
-			label = "Clear Light";
-			location = "MOTIONSENSE_LOC_BASE";
-			port = <&i2c_sensor>;
-			default-range = <0x10000>;
-			drv-data = <&tcs_clear_data>;
-			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
-			configs {
-				compatible =
-					"cros-ec,motionsense-sensor-config";
-				ec-s0 {
-					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
-					odr = <1000>;
-				};
-			};
-		};
-
-		tcs3400_rgb: tcs3400-rgb {
-			compatible = "cros-ec,tcs3400-rgb";
-			status = "okay";
-
-			label = "RGB Light";
-			location = "MOTIONSENSE_LOC_BASE";
-			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
-			drv-data = <&tcs_rgb_data>;
-		};
-	};
-
-	/*
-	 * Second i2c bus is required, because there is already device with
-	 * address 0x68 on the first bus
-	 */
-	i2c1: i2c@400 {
-		status = "okay";
-		compatible = "zephyr,i2c-emul-controller";
-		clock-frequency = <I2C_BITRATE_STANDARD>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x400 4>;
-		label = "I2C_1";
-
-		accel_bmi160: bmi160@68 {
-			compatible = "zephyr,bmi";
-			reg = <0x68>;
-			label = "BMI160";
-			device-model = "BMI_EMUL_160";
-			error-on-ro-write;
-			error-on-wo-read;
-			error-on-reserved-bit-write;
-			simulate-command-exec-time;
-		};
-
-		tcs_emul: tcs@39 {
-			compatible = "zephyr,tcs3400";
-			reg = <0x39>;
-			label = "TCS_EMUL";
-			error-on-ro-write;
-			error-on-reserved-bit-write;
-			error-on-msb-first-access;
-		};
-	};
-};
-
-&espi0 {
-	espi-host@0 {
-		status = "okay";
-		compatible = "zephyr,espi-emul-espi-host";
-		reg = <0x0>;
-		label = "ESPI_HOST";
-	};
-};
-
-&gpio0 {
-	ngpios = <8>;
-};
-
-&i2c0 {
-	cbi_eeprom: eeprom@56 {
-		compatible = "atmel,at24";
-		reg = <0x56>;
-		label = "EEPROM_CBI";
-		size = <512>;
-		pagesize = <8>;
-		address-width = <8>;
-		timeout = <5>;
-		wp-gpios = <&gpio_wp_l>;
-	};
-
-	battery: sb@b {
-		compatible = "zephyr,smart-battery";
-		reg = <0xb>;
-		label = "BATTERY";
-		cycle-count = <99>;
-		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
-	};
-
-	bma_emul: bma@18 {
-		compatible = "zephyr,bma255";
-		reg = <0x18>;
-		label = "BMA_EMUL";
-		error-on-compensation-not-ready;
-		error-on-ro-write;
-		error-on-reserved-bit-write;
-		error-on-msb-first-access;
-	};
-
-	pi3usb9201_emul: pi3usb9201@5f {
-		compatible = "zephyr,pi3usb9201-emul";
-		reg = <0x5f>;
-		label = "PI3USB9201_EMUL";
-	};
-
-	syv682x_emul: syv682x@41 {
-		compatible = "zephyr,syv682x-emul";
-		reg = <0x41>;
-		label = "SYV682X_EMUL";
-	};
-
-	accel_bmi260: bmi260@68 {
-		compatible = "zephyr,bmi";
-		reg = <0x68>;
-		label = "BMI260";
-		device-model = "BMI_EMUL_260";
-		error-on-ro-write;
-		error-on-wo-read;
-		error-on-reserved-bit-write;
-		simulate-command-exec-time;
-	};
-
-	usb_c1_bb_retimer_emul: bbretimer@42 {
-		compatible = "cros,bb-retimer-emul";
-		reg = <0x42>;
-		label = "USB_C1_BB_RETIMER";
-		vendor = "BB_RETIMER_VENDOR_ID_1";
-		error-on-ro-write;
-		error-on-reserved-bit-write;
-	};
-
-	ln9310: ln9310@80 {
-		compatible = "cros,ln9310-emul";
-		status = "okay";
-		reg = <0x80>;
-		label = "LN9310";
-	};
-
-	lis2dw12_emul: lis2dw12@19 {
-		compatible = "cros,lis2dw12-emul";
-		status = "okay";
-		reg = <0x19>;
-		label = "LIS2DW12_EMUL";
-	};
-
-	i2c_mock: i2c_mock@84 {
-		compatible = "cros,i2c-mock";
-		status = "okay";
-		reg = <0x84>;
-		label = "I2C_MOCK";
-	};
-};
-
-/* Enable all thermistors for testing */
-&thermistor_3V3_30K9_47K_4050B  {
-	status = "okay";
-};
-
-&thermistor_3V0_22K6_47K_4050B  {
-	status = "okay";
-};
-
-&thermistor_3V3_13K7_47K_4050B  {
-	status = "okay";
-};
-
-&thermistor_3V3_51K1_47K_4050B  {
-	status = "okay";
-};
diff --git a/zephyr/test/drivers/prj.conf b/zephyr/test/drivers/prj.conf
deleted file mode 100644
index 99a275f9e2..0000000000
--- a/zephyr/test/drivers/prj.conf
+++ /dev/null
@@ -1,90 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Enabling this config will show all I2C traffic, do not commit with this line
-# uncommented, it is here to make it easy to find/enable.
-# CONFIG_I2C_LOG_LEVEL_DBG=y
-
-CONFIG_ZTEST=y
-CONFIG_ZTEST_ASSERT_VERBOSE=1
-CONFIG_ZTEST_MOCKING=y
-CONFIG_ZTEST_PARAMETER_COUNT=5
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_EMUL=y
-CONFIG_LOG=y
-CONFIG_I2C=y
-CONFIG_I2C_EMUL=y
-CONFIG_GPIO=y
-CONFIG_GPIO_EMUL=y
-CONFIG_EMUL_EEPROM_AT2X=y
-CONFIG_EMUL_SMART_BATTERY=y
-CONFIG_EMUL_BC12_DETECT_PI3USB9201=y
-CONFIG_EMUL_PPC_SYV682X=y
-CONFIG_ADC=y
-CONFIG_ADC_EMUL=y
-CONFIG_HEAP_MEM_POOL_SIZE=1024
-CONFIG_EMUL_BMA255=y
-CONFIG_EMUL_BMI=y
-CONFIG_EMUL_TCS3400=y
-CONFIG_EMUL_BB_RETIMER=y
-
-CONFIG_PLATFORM_EC_POWERSEQ=y
-
-CONFIG_HAS_TASK_USB_CHG_P0=y
-CONFIG_HAS_TASK_USB_CHG_P1=y
-CONFIG_HAS_TASK_PD_C1=y
-
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-
-CONFIG_PLATFORM_EC_USB_PID=0x5000
-CONFIG_PLATFORM_EC_USBC=y
-CONFIG_PLATFORM_EC_USB_CHARGER=y
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=y
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-CONFIG_PLATFORM_EC_I2C=y
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
-CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_HOSTCMD=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=y
-CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
-CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
-CONFIG_PLATFORM_EC_CBI_EEPROM=y
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_PLATFORM_EC_TEMP_SENSOR=y
-CONFIG_PLATFORM_EC_THERMISTOR=y
-CONFIG_PLATFORM_EC_SWITCHCAP_LN9310=y
-CONFIG_PLATFORM_EC_ACCEL_BMA255=y
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_ALS_TCS3400=y
-CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB=y
-
-CONFIG_ESPI=y
-CONFIG_ESPI_EMUL=y
-CONFIG_EMUL_ESPI_HOST=y
-CONFIG_PLATFORM_EC_ESPI=y
-CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
-CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
-CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
-
-# Things that default to on, but aren't working yet
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_SWITCH=n
-CONFIG_PLATFORM_EC_VBOOT_HASH=n
-CONFIG_PLATFORM_EC_POWERSEQ_INTEL=n
-CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
diff --git a/zephyr/test/drivers/src/battery.c b/zephyr/test/drivers/src/battery.c
deleted file mode 100644
index 315f822985..0000000000
--- a/zephyr/test/drivers/src/battery.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <drivers/gpio.h>
-#include <drivers/gpio/gpio_emul.h>
-
-#include "battery.h"
-
-#define GPIO_BATT_PRES_ODL_PATH DT_PATH(named_gpios, ec_batt_pres_odl)
-#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
-
-static void test_battery_is_present_gpio(void)
-{
-	const struct device *dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
-
-	zassert_not_null(dev, NULL);
-	/* ec_batt_pres_odl = 0 means battery present. */
-	zassert_ok(gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 0), NULL);
-	zassert_equal(BP_YES, battery_is_present(), NULL);
-	/* ec_batt_pres_odl = 1 means battery missing. */
-	zassert_ok(gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 1), NULL);
-	zassert_equal(BP_NO, battery_is_present(), NULL);
-}
-
-void test_suite_battery(void)
-{
-	ztest_test_suite(battery,
-			 ztest_user_unit_test(test_battery_is_present_gpio));
-	ztest_run_test_suite(battery);
-}
diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/src/bb_retimer.c
deleted file mode 100644
index cecee6020f..0000000000
--- a/zephyr/test/drivers/src/bb_retimer.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <drivers/gpio.h>
-#include <drivers/gpio/gpio_emul.h>
-
-#include "common.h"
-#include "ec_tasks.h"
-#include "emul/emul_bb_retimer.h"
-#include "emul/emul_common_i2c.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "stubs.h"
-#include "usb_prl_sm.h"
-#include "usb_tc_sm.h"
-
-#include "driver/retimer/bb_retimer.h"
-
-#define GPIO_USB_C1_LS_EN_PATH DT_PATH(named_gpios, usb_c1_ls_en)
-#define GPIO_USB_C1_LS_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_LS_EN_PATH, gpios)
-#define GPIO_USB_C1_RT_RST_ODL_PATH DT_PATH(named_gpios, usb_c1_rt_rst_odl)
-#define GPIO_USB_C1_RT_RST_ODL_PORT	\
-		DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios)
-#define EMUL_LABEL DT_NODELABEL(usb_c1_bb_retimer_emul)
-
-#define BB_RETIMER_ORD DT_DEP_ORD(EMUL_LABEL)
-
-/** Test is retimer fw update capable function. */
-static void test_bb_is_fw_update_capable(void)
-{
-	/* BB retimer is fw update capable */
-	zassert_true(bb_usb_retimer.is_retimer_fw_update_capable(), NULL);
-}
-
-/** Test is retimer fw update capable function. */
-static void test_bb_set_state(void)
-{
-	struct pd_discovery *disc;
-	uint32_t conn, exp_conn;
-	struct i2c_emul *emul;
-	bool ack_required;
-
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
-	set_test_runner_tid();
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul,
-					   BB_RETIMER_REG_CONNECTION_STATE);
-
-	/* Test fail on reset register write */
-	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-					 USB_PD_MUX_NONE, &ack_required),
-		      NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set UFP role for whole test */
-	tc_set_data_role(USBC_PORT_C1, PD_ROLE_UFP);
-
-	/* Test none mode */
-	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_NONE,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	/* Only UFP mode is set */
-	exp_conn = BB_RETIMER_USB_DATA_ROLE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test USB3 gen1 mode */
-	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV10);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB_3_CONNECTION;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test USB3 gen2 mode */
-	disc = pd_get_am_discovery_and_notify_access(
-					USBC_PORT_C1, TCPCI_MSG_SOP_PRIME);
-	disc->identity.product_t1.p_rev20.ss = USB_R20_SS_U31_GEN1_GEN2;
-	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB_3_CONNECTION |
-		   BB_RETIMER_USB_3_SPEED;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test USB4 mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB4_ENABLED,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB4_ENABLED;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test USB4 mode with polarity inverted */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_USB4_ENABLED |
-						USB_PD_MUX_POLARITY_INVERTED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_CONNECTION_ORIENTATION |
-		   BB_RETIMER_USB4_ENABLED;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test DP mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED |
-						     USB_PD_MUX_HPD_IRQ,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION |
-		   BB_RETIMER_IRQ_HPD;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED |
-						     USB_PD_MUX_HPD_LVL,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION |
-		   BB_RETIMER_HPD_LVL;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-}
-
-/** Test setting different options for DFP role */
-static void test_bb_set_dfp_state(void)
-{
-	union tbt_mode_resp_device device_resp;
-	union tbt_mode_resp_cable cable_resp;
-	struct pd_discovery *disc, *dev_disc;
-	uint32_t conn, exp_conn;
-	struct i2c_emul *emul;
-	bool ack_required;
-
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
-	set_test_runner_tid();
-
-	tc_set_data_role(USBC_PORT_C1, PD_ROLE_DFP);
-
-	/* Test PD mux none mode with DFP should clear all bits in state */
-	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_NONE,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = 0;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Set active cable type */
-	disc = pd_get_am_discovery_and_notify_access(
-					USBC_PORT_C1, TCPCI_MSG_SOP_PRIME);
-	disc->identity.idh.product_type = IDH_PTYPE_ACABLE;
-	disc->identity.product_t2.a2_rev30.active_elem = ACTIVE_RETIMER;
-	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30);
-
-	/* Set cable VDO */
-	disc->svid_cnt = 1;
-	disc->svids[0].svid = USB_VID_INTEL;
-	disc->svids[0].discovery = PD_DISC_COMPLETE;
-	disc->svids[0].mode_cnt = 1;
-	cable_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
-	cable_resp.tbt_cable_speed = TBT_SS_RES_0;
-	cable_resp.tbt_rounded = TBT_GEN3_NON_ROUNDED;
-	cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL;
-	cable_resp.retimer_type = USB_NOT_RETIMER;
-	cable_resp.lsrx_comm = BIDIR_LSRX_COMM;
-	cable_resp.tbt_active_passive = TBT_CABLE_PASSIVE;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-
-	/* Set device VDO */
-	dev_disc = pd_get_am_discovery_and_notify_access(
-						USBC_PORT_C1, TCPCI_MSG_SOP);
-	dev_disc->svid_cnt = 1;
-	dev_disc->svids[0].svid = USB_VID_INTEL;
-	dev_disc->svids[0].discovery = PD_DISC_COMPLETE;
-	dev_disc->svids[0].mode_cnt = 1;
-	device_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
-	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
-	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
-	device_resp.vendor_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
-	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_NOT_SUPPORTED;
-	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-
-	/* Test USB mode with active cable */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB_3_CONNECTION |
-		   BB_RETIMER_USB_3_SPEED |
-		   BB_RETIMER_RE_TIMER_DRIVER |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with active cable */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with retimer */
-	cable_resp.retimer_type = USB_RETIMER;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_RE_TIMER_DRIVER |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with optical cable */
-	cable_resp.retimer_type = USB_NOT_RETIMER;
-	cable_resp.tbt_cable = TBT_CABLE_OPTICAL;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_CABLE_TYPE |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with active link training */
-	cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL;
-	cable_resp.lsrx_comm = UNIDIR_LSRX_COMM;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_ACTIVE_LINK_TRAINING |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with different cable speeds */
-	cable_resp.lsrx_comm = BIDIR_LSRX_COMM;
-	cable_resp.tbt_cable_speed = TBT_SS_U31_GEN1;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(1) |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	cable_resp.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(2) |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	cable_resp.tbt_cable_speed = TBT_SS_TBT_GEN3;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(3) |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with TBT gen4 cable */
-	cable_resp.tbt_cable_speed = TBT_SS_RES_0;
-	cable_resp.tbt_rounded = TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_CABLE_GENERATION(1) |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with legacy TBT adapter */
-	cable_resp.tbt_rounded = TBT_GEN3_NON_ROUNDED;
-	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	device_resp.tbt_adapter = TBT_ADAPTER_TBT2_LEGACY;
-	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_TYPE |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with Intel specific b0 */
-	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
-	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_SUPPORTED;
-	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-
-	/* Test TBT mode with vendor specific b1 */
-	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
-	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_SUPPORTED;
-	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
-	zassert_false(ack_required, "ACK is never required for BB retimer");
-	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE |
-		   BB_RETIMER_ACTIVE_PASSIVE;
-	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
-		      exp_conn, conn);
-}
-
-/** Test BB retimer init */
-static void test_bb_init(void)
-{
-	const struct device *gpio_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_LS_EN_PATH, gpios));
-	struct i2c_emul *emul;
-
-	zassert_not_null(gpio_dev, "Cannot get GPIO device");
-
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
-	/* Set AP to normal state and wait for chipset task */
-	set_mock_power_state(POWER_S0);
-	k_msleep(1);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BB_RETIMER_REG_VENDOR_ID);
-	/* Test fail on vendor ID read */
-	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
-	/* Enable pins should be set always after init, when AP is on */
-	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-
-	/* Setup wrong vendor ID */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, 0x12144678);
-	/* Test fail on wrong vendor ID */
-	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-
-	/* Setup emulator fail on device ID read */
-	i2c_common_emul_set_read_fail_reg(emul, BB_RETIMER_REG_DEVICE_ID);
-	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, BB_RETIMER_VENDOR_ID_1);
-	/* Test fail on device ID read */
-	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-
-	/* Setup wrong device ID */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, 0x12144678);
-	/* Test fail on wrong device ID */
-	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-
-	/* Test successful init */
-	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, BB_RETIMER_DEVICE_ID);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-
-	/* Set AP to off state and wait for chipset task */
-	set_mock_power_state(POWER_G3);
-	k_msleep(1);
-
-	/* With AP off, init should fail and pins should be unset */
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
-	zassert_equal(0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
-		      NULL);
-	zassert_equal(0, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
-}
-
-
-void test_suite_bb_retimer(void)
-{
-	ztest_test_suite(bb_retimer,
-			 ztest_user_unit_test(test_bb_is_fw_update_capable),
-			 ztest_user_unit_test(test_bb_set_state),
-			 ztest_user_unit_test(test_bb_set_dfp_state),
-			 ztest_user_unit_test(test_bb_init));
-	ztest_run_test_suite(bb_retimer);
-}
diff --git a/zephyr/test/drivers/src/bc12.c b/zephyr/test/drivers/src/bc12.c
deleted file mode 100644
index 4251448f2c..0000000000
--- a/zephyr/test/drivers/src/bc12.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <drivers/gpio.h>
-#include <drivers/gpio/gpio_emul.h>
-
-#include "emul/emul_pi3usb9201.h"
-
-#include "timer.h"
-#include "usb_charge.h"
-#include "battery.h"
-#include "extpower.h"
-#include "stubs.h"
-
-#include <logging/log.h>
-LOG_MODULE_REGISTER(test_drivers_bc12, LOG_LEVEL_DBG);
-
-#define EMUL_LABEL DT_NODELABEL(pi3usb9201_emul)
-
-#define PI3USB9201_ORD DT_DEP_ORD(EMUL_LABEL)
-
-/* Control_1 register bit definitions */
-#define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
-#define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
-#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \
-					 PI3USB9201_REG_CTRL_1_MODE_SHIFT)
-
-/* Control_2 register bit definitions */
-#define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
-#define PI3USB9201_REG_CTRL_2_START_DET BIT(3)
-
-/* Host status register bit definitions */
-#define PI3USB9201_REG_HOST_STS_BC12_DET BIT(0)
-#define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1)
-#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2)
-
-enum pi3usb9201_mode {
-	PI3USB9201_POWER_DOWN,
-	PI3USB9201_SDP_HOST_MODE,
-	PI3USB9201_DCP_HOST_MODE,
-	PI3USB9201_CDP_HOST_MODE,
-	PI3USB9201_CLIENT_MODE,
-	PI3USB9201_RESERVED_1,
-	PI3USB9201_RESERVED_2,
-	PI3USB9201_USB_PATH_ON,
-};
-
-enum pi3usb9201_client_sts {
-	CHG_OTHER = 0,
-	CHG_2_4A,
-	CHG_2_0A,
-	CHG_1_0A,
-	CHG_RESERVED,
-	CHG_CDP,
-	CHG_SDP,
-	CHG_DCP,
-};
-
-struct bc12_status {
-	enum charge_supplier supplier;
-	int current_limit;
-};
-
-static const struct bc12_status bc12_chg_limits[] = {
-	[CHG_OTHER]    = { .supplier = CHARGE_SUPPLIER_OTHER,
-			   .current_limit = 500 },
-	[CHG_2_4A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_2_0A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_1_0A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = 1000 },
-	[CHG_RESERVED] = { .supplier = CHARGE_SUPPLIER_NONE,
-			   .current_limit = 0 },
-	[CHG_CDP]      = { .supplier = CHARGE_SUPPLIER_BC12_CDP,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_SDP]      = { .supplier = CHARGE_SUPPLIER_BC12_SDP,
-			   .current_limit = 500 },
-#if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	[CHG_DCP]      = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-#else
-	[CHG_DCP]      = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
-			   .current_limit = 500 },
-#endif
-};
-
-#define GPIO_BATT_PRES_ODL_PATH DT_PATH(named_gpios, ec_batt_pres_odl)
-#define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
-
-#define GPIO_ACOK_OD_PATH DT_PATH(named_gpios, acok_od)
-#define GPIO_ACOK_OD_PORT DT_GPIO_PIN(GPIO_ACOK_OD_PATH, gpios)
-
-static void test_bc12_pi3usb9201_host_mode(void)
-{
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
-	uint8_t a, b;
-
-	/*
-	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
-	 * role to DFP.
-	 */
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_DR_DFP);
-	msleep(1);
-	/*
-	 * Expect the pi3usb9201 driver to configure CDP host mode and unmask
-	 * interrupts.
-	 */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_CDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	zassert_equal(a, b, NULL);
-
-	/* Pretend that a device has been plugged in. */
-	msleep(500);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS,
-				PI3USB9201_REG_HOST_STS_DEV_PLUG);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	msleep(1);
-	/* Expect the pi3usb9201 driver to configure SDP host mode. */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_SDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	zassert_equal(a, b, NULL);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0);
-
-	/* Pretend that a device has been unplugged. */
-	msleep(500);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS,
-				PI3USB9201_REG_HOST_STS_DEV_UNPLUG);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	msleep(1);
-	/* Expect the pi3usb9201 driver to configure CDP host mode. */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_CDP_HOST_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	zassert_equal(a, b, NULL);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0);
-}
-
-static void test_bc12_pi3usb9201_client_mode(
-			enum pi3usb9201_client_sts detect_result,
-			enum charge_supplier supplier, int current_limit)
-{
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
-	uint8_t a, b;
-	int port, voltage;
-
-	/*
-	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
-	 * role to UFP and decided charging from the port is allowed.
-	 */
-	msleep(500);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_DR_UFP);
-	charge_manager_update_dualrole(USBC_PORT_C0, CAP_DEDICATED);
-	msleep(1);
-	/*
-	 * Expect the pi3usb9201 driver to configure client mode and start
-	 * detection.
-	 */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_CLIENT_MODE << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	zassert_equal(a, b, NULL);
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_2, &a);
-	b = PI3USB9201_REG_CTRL_2_START_DET;
-	zassert_equal(a, b, NULL);
-
-	/* Pretend that detection completed. */
-	msleep(500);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_CLIENT_STS,
-				1 << detect_result);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-	msleep(1);
-	/* Expect the pi3usb9201 driver to clear the start bit. */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_2, &a);
-	zassert_equal(a, 0, NULL);
-	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_CLIENT_STS, 0);
-	/*
-	 * Expect the charge manager to select the detected BC1.2 supplier.
-	 */
-	port = CHARGE_PORT_NONE;
-	voltage = 0;
-	if (supplier != CHARGE_SUPPLIER_NONE) {
-		port = USBC_PORT_C0;
-		voltage = USB_CHARGER_VOLTAGE_MV;
-	}
-	zassert_equal(charge_manager_get_active_charge_port(),
-		      port, NULL);
-	zassert_equal(charge_manager_get_supplier(),
-		      supplier, NULL);
-	zassert_equal(charge_manager_get_charger_current(),
-		      current_limit, NULL);
-	zassert_equal(charge_manager_get_charger_voltage(),
-		      voltage, NULL);
-
-	/*
-	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
-	 * role to disconnected.
-	 */
-	msleep(500);
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_CC_OPEN);
-	msleep(1);
-	/*
-	 * Expect the pi3usb9201 driver to configure power down mode and mask
-	 * interrupts.
-	 */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_POWER_DOWN << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	b |= PI3USB9201_REG_CTRL_1_INT_MASK;
-	zassert_equal(a, b, NULL);
-	/* Expect the charge manager to have no active supplier. */
-	zassert_equal(charge_manager_get_active_charge_port(),
-		      CHARGE_PORT_NONE, NULL);
-	zassert_equal(charge_manager_get_supplier(),
-		      CHARGE_SUPPLIER_NONE, NULL);
-	zassert_equal(charge_manager_get_charger_current(), 0, NULL);
-	zassert_equal(charge_manager_get_charger_voltage(), 0, NULL);
-}
-
-/*
- * PI3USB9201 is a dual-role BC1.2 charger detector/advertiser used on USB
- * ports. It can be programmed to operate in host mode or client mode through
- * I2C. When operating as a host, PI3USB9201 enables BC1.2 SDP/CDP/DCP
- * advertisement to the attached USB devices via the D+/- connection. When
- * operating as a client, PI3USB9201 starts BC1.2 detection to detect the
- * attached host type. In both host mode and client mode, the detection results
- * are reported through I2C to the controller.
- */
-static void test_bc12_pi3usb9201(void)
-{
-	const struct device *batt_pres_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
-	const struct device *acok_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_ACOK_OD_PATH, gpios));
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
-	uint8_t a, b;
-
-	/* Pretend we have battery and AC so charging works normally. */
-	zassert_ok(gpio_emul_input_set(batt_pres_dev,
-				       GPIO_BATT_PRES_ODL_PORT, 0), NULL);
-	zassert_equal(BP_YES, battery_is_present(), NULL);
-	zassert_ok(gpio_emul_input_set(acok_dev, GPIO_ACOK_OD_PORT, 1), NULL);
-	msleep(CONFIG_EXTPOWER_DEBOUNCE_MS + 1);
-	zassert_equal(1, extpower_is_present(), NULL);
-
-	/* Wait long enough for TCPMv2 to be idle. */
-	msleep(2000);
-
-	/*
-	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
-	 * role to disconnected.
-	 */
-	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_CC_OPEN);
-	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_CC_OPEN);
-	msleep(1);
-	/*
-	 * Expect the pi3usb9201 driver to configure power down mode and mask
-	 * interrupts.
-	 */
-	pi3usb9201_emul_get_reg(emul, PI3USB9201_REG_CTRL_1, &a);
-	b = PI3USB9201_POWER_DOWN << PI3USB9201_REG_CTRL_1_MODE_SHIFT;
-	b |= PI3USB9201_REG_CTRL_1_INT_MASK;
-	zassert_equal(a, b, NULL);
-
-	test_bc12_pi3usb9201_host_mode();
-
-	for (int c = CHG_OTHER; c <= CHG_DCP; c++) {
-		test_bc12_pi3usb9201_client_mode(c,
-					bc12_chg_limits[c].supplier,
-					bc12_chg_limits[c].current_limit);
-	}
-}
-
-void test_suite_bc12(void)
-{
-	ztest_test_suite(bc12,
-			 ztest_user_unit_test(test_bc12_pi3usb9201));
-	ztest_run_test_suite(bc12);
-}
diff --git a/zephyr/test/drivers/src/bma2x2.c b/zephyr/test/drivers/src/bma2x2.c
deleted file mode 100644
index 8b77464b48..0000000000
--- a/zephyr/test/drivers/src/bma2x2.c
+++ /dev/null
@@ -1,926 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c.h"
-#include "emul/emul_bma255.h"
-#include "emul/emul_common_i2c.h"
-
-#include "accelgyro.h"
-#include "motion_sense.h"
-#include "driver/accel_bma2x2.h"
-
-/** How accurate comparision of vectors should be. */
-#define V_EPS 8
-
-#define EMUL_LABEL DT_NODELABEL(bma_emul)
-
-#define BMA_ORD DT_DEP_ORD(EMUL_LABEL)
-
-/** Mutex for test motion sensor  */
-static mutex_t sensor_mutex;
-
-/** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/** Rotate given vector by test rotation */
-void rotate_int3v_by_test_rotation(int16_t *v)
-{
-	int16_t t;
-
-	t = v[0];
-	v[0] = -v[1];
-	v[1] = t;
-	v[2] = -v[2];
-}
-
-static struct accelgyro_saved_data_t acc_data;
-
-/** Mock minimal motion sensor setup required for bma2x2 driver test */
-static struct motion_sensor_t ms = {
-	.name = "bma_emul",
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.drv = &bma2x2_accel_drv,
-	.mutex = &sensor_mutex,
-	.drv_data = &acc_data,
-	.port = NAMED_I2C(accel),
-	.i2c_spi_addr_flags = DT_REG_ADDR(EMUL_LABEL),
-	.rot_standard_ref = NULL,
-	.current_range = 0,
-};
-
-/** Set emulator offset values to vector of three int16_t */
-static void set_emul_offset(struct i2c_emul *emul, int16_t *offset)
-{
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, offset[0]);
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, offset[1]);
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, offset[2]);
-}
-
-/** Save emulator offset values to vector of three int16_t */
-static void get_emul_offset(struct i2c_emul *emul, int16_t *offset)
-{
-	offset[0] = bma_emul_get_off(emul, BMA_EMUL_AXIS_X);
-	offset[1] = bma_emul_get_off(emul, BMA_EMUL_AXIS_Y);
-	offset[2] = bma_emul_get_off(emul, BMA_EMUL_AXIS_Z);
-}
-
-/** Set emulator accelerometer values to vector of three int16_t */
-static void set_emul_acc(struct i2c_emul *emul, int16_t *acc)
-{
-	bma_emul_set_acc(emul, BMA_EMUL_AXIS_X, acc[0]);
-	bma_emul_set_acc(emul, BMA_EMUL_AXIS_Y, acc[1]);
-	bma_emul_set_acc(emul, BMA_EMUL_AXIS_Z, acc[2]);
-}
-
-/** Convert accelerometer read to units used by emulator */
-static void drv_acc_to_emul(intv3_t drv, int range, int16_t *out)
-{
-	const int scale = MOTION_SCALING_FACTOR / BMA_EMUL_1G;
-
-	out[0] = drv[0] * range / scale;
-	out[1] = drv[1] * range / scale;
-	out[2] = drv[2] * range / scale;
-}
-
-/** Compare two vectors of three int16_t */
-static void compare_int3v_f(int16_t *exp_v, int16_t *v, int line)
-{
-	int i;
-
-	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], V_EPS,
-			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
-			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
-	}
-}
-#define compare_int3v(exp_v, v) compare_int3v_f(exp_v, v, __LINE__)
-
-/** Data for reset fail function */
-struct reset_func_data {
-	/** Fail for given attempts */
-	int fail_attempts;
-	/** Do not fail for given attempts */
-	int ok_before_fail;
-	/** Reset register value after given attempts */
-	int reset_value;
-};
-
-/**
- * Custom emulator function used in init test. It returns cmd soft when reset
- * register is accessed data.reset_value times. Error is returned after
- * accessing register data.ok_before_fail times. Error is returned during next
- * data.fail_attempts times.
- */
-static int emul_read_reset(struct i2c_emul *emul, int reg, uint8_t *buf,
-			   int bytes, void *data)
-{
-	struct reset_func_data *d = data;
-
-	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
-	if (reg != BMA2x2_RST_ADDR) {
-		return 1;
-	}
-
-	if (d->reset_value > 0) {
-		d->reset_value--;
-		bma_emul_set_reg(emul, BMA2x2_RST_ADDR, BMA2x2_CMD_SOFT_RESET);
-	} else {
-		bma_emul_set_reg(emul, BMA2x2_RST_ADDR, 0);
-	}
-
-	if (d->ok_before_fail > 0) {
-		d->ok_before_fail--;
-		return 1;
-	}
-
-	if (d->fail_attempts > 0) {
-		d->fail_attempts--;
-		return -EIO;
-	}
-
-	return 1;
-}
-
-/**
- * Test get offset with and without rotation. Also test behaviour on I2C error.
- */
-static void test_bma_get_offset(void)
-{
-	struct i2c_emul *emul;
-	int16_t ret_offset[3];
-	int16_t exp_offset[3];
-	int16_t temp;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Test fail on each axis */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_X_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL,
-		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_Y_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL,
-		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_Z_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL,
-		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set emulator offset */
-	exp_offset[0] = BMA_EMUL_1G / 10;
-	exp_offset[1] = BMA_EMUL_1G / 20;
-	exp_offset[2] = -(int)BMA_EMUL_1G / 30;
-	set_emul_offset(emul, exp_offset);
-	/* Disable rotation */
-	ms.rot_standard_ref = NULL;
-
-	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->get_offset(&ms, ret_offset, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	compare_int3v(exp_offset, ret_offset);
-
-	/* Setup rotation and rotate expected offset */
-	ms.rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_offset);
-
-	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->get_offset(&ms, ret_offset, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	compare_int3v(exp_offset, ret_offset);
-}
-
-/**
- * Test set offset with and without rotation. Also test behaviour on I2C error.
- */
-static void test_bma_set_offset(void)
-{
-	struct i2c_emul *emul;
-	int16_t ret_offset[3];
-	int16_t exp_offset[3];
-	int16_t temp = 0;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Test fail on each axis */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_X_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_Y_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_Z_AXIS_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
-		      NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set input offset */
-	exp_offset[0] = BMA_EMUL_1G / 10;
-	exp_offset[1] = BMA_EMUL_1G / 20;
-	exp_offset[2] = -(int)BMA_EMUL_1G / 30;
-	/* Disable rotation */
-	ms.rot_standard_ref = NULL;
-
-	/* Test set offset without rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->set_offset(&ms, exp_offset, temp),
-		      NULL);
-	get_emul_offset(emul, ret_offset);
-	compare_int3v(exp_offset, ret_offset);
-
-	/* Setup rotation and rotate input for set_offset function */
-	ms.rot_standard_ref = &test_rotation;
-	ret_offset[0] = exp_offset[0];
-	ret_offset[1] = exp_offset[1];
-	ret_offset[2] = exp_offset[2];
-	rotate_int3v_by_test_rotation(ret_offset);
-
-	/* Test set offset with rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->set_offset(&ms, ret_offset, temp),
-		      NULL);
-	get_emul_offset(emul, ret_offset);
-	compare_int3v(exp_offset, ret_offset);
-}
-
-/*
- * Try to set range and check if expected range was set in driver and in
- * emulator.
- */
-static void check_set_range_f(struct i2c_emul *emul, int range, int rnd,
-			      int exp_range, int line)
-{
-	uint8_t exp_range_reg;
-	uint8_t range_reg;
-
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, rnd),
-		      "set_range failed; line: %d", line);
-	zassert_equal(exp_range, ms.current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms.current_range, line);
-	range_reg = bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
-	range_reg &= BMA2x2_RANGE_SELECT_MSK;
-
-	switch (exp_range) {
-	case 2:
-		exp_range_reg = BMA2x2_RANGE_2G;
-		break;
-	case 4:
-		exp_range_reg = BMA2x2_RANGE_4G;
-		break;
-	case 8:
-		exp_range_reg = BMA2x2_RANGE_8G;
-		break;
-	case 16:
-		exp_range_reg = BMA2x2_RANGE_16G;
-		break;
-	default:
-		/* Unknown expected range */
-		zassert_unreachable(
-			"Expected range %d not supported by device; line %d",
-			exp_range, line);
-		return;
-	}
-
-	zassert_equal(exp_range_reg, range_reg,
-		      "Expected range reg 0x%x, got 0x%x; line %d",
-		      exp_range_reg, range_reg, line);
-}
-#define check_set_range(emul, range, rnd, exp_range)	\
-	check_set_range_f(emul, range, rnd, exp_range, __LINE__)
-
-/** Test set range with and without I2C errors. */
-static void test_bma_set_range(void)
-{
-	struct i2c_emul *emul;
-	int start_range;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Setup starting range, shouldn't be changed on error */
-	start_range = 2;
-	ms.current_range = start_range;
-	bma_emul_set_reg(emul, BMA2x2_RANGE_SELECT_ADDR, BMA2x2_RANGE_2G);
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0), NULL);
-	zassert_equal(start_range, ms.current_range, NULL);
-	zassert_equal(BMA2x2_RANGE_2G,
-		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 1), NULL);
-	zassert_equal(start_range, ms.current_range, NULL);
-	zassert_equal(BMA2x2_RANGE_2G,
-		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0), NULL);
-	zassert_equal(start_range, ms.current_range, NULL);
-	zassert_equal(BMA2x2_RANGE_2G,
-		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 1), NULL);
-	zassert_equal(start_range, ms.current_range, NULL);
-	zassert_equal(BMA2x2_RANGE_2G,
-		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting range with rounding down */
-	check_set_range(emul, 1, 0, 2);
-	check_set_range(emul, 2, 0, 2);
-	check_set_range(emul, 3, 0, 2);
-	check_set_range(emul, 4, 0, 4);
-	check_set_range(emul, 5, 0, 4);
-	check_set_range(emul, 6, 0, 4);
-	check_set_range(emul, 7, 0, 4);
-	check_set_range(emul, 8, 0, 8);
-	check_set_range(emul, 9, 0, 8);
-	check_set_range(emul, 15, 0, 8);
-	check_set_range(emul, 16, 0, 16);
-	check_set_range(emul, 17, 0, 16);
-
-	/* Test setting range with rounding up */
-	check_set_range(emul, 1, 1, 2);
-	check_set_range(emul, 2, 1, 2);
-	check_set_range(emul, 3, 1, 4);
-	check_set_range(emul, 4, 1, 4);
-	check_set_range(emul, 5, 1, 8);
-	check_set_range(emul, 6, 1, 8);
-	check_set_range(emul, 7, 1, 8);
-	check_set_range(emul, 8, 1, 8);
-	check_set_range(emul, 9, 1, 16);
-	check_set_range(emul, 15, 1, 16);
-	check_set_range(emul, 16, 1, 16);
-	check_set_range(emul, 17, 1, 16);
-}
-
-/** Test init with and without I2C errors. */
-static void test_bma_init(void)
-{
-	struct reset_func_data reset_func_data;
-	struct i2c_emul *emul;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Setup emulator fail read function */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_CHIP_ID_ADDR);
-
-	/* Test fail on chip id read */
-	zassert_equal(EC_ERROR_UNKNOWN, ms.drv->init(&ms), NULL);
-
-	/* Disable failing on chip id read, but set wrong value */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, 23);
-
-	/* Test wrong chip id */
-	zassert_equal(EC_ERROR_ACCESS_DENIED, ms.drv->init(&ms), NULL);
-
-	/* Set correct chip id, but fail on reset reg read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_RST_ADDR);
-	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, BMA255_CHIP_ID_MAJOR);
-
-	/* Test fail on reset register read */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_RST_ADDR);
-
-	/* Test fail on reset register write */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail reset read function */
-	reset_func_data.ok_before_fail = 1;
-	reset_func_data.fail_attempts = 100;
-	reset_func_data.reset_value = 0;
-	i2c_common_emul_set_read_func(emul, emul_read_reset, &reset_func_data);
-
-	/* Test fail on too many reset read errors */
-	zassert_equal(EC_ERROR_TIMEOUT, ms.drv->init(&ms), NULL);
-
-	/* Test success after reset read errors */
-	reset_func_data.ok_before_fail = 1;
-	reset_func_data.fail_attempts = 3;
-	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms), NULL);
-
-	/* Test success without read errors */
-	reset_func_data.fail_attempts = 0;
-	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms), NULL);
-
-	/* Test fail on too many reset read wrong value */
-	reset_func_data.fail_attempts = 0;
-	reset_func_data.reset_value = 100;
-	zassert_equal(EC_ERROR_TIMEOUT, ms.drv->init(&ms), NULL);
-
-	/* Test success on few reset read wrong value */
-	reset_func_data.fail_attempts = 0;
-	reset_func_data.reset_value = 4;
-	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms), NULL);
-
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-}
-
-/*
- * Try to set data rate and check if expected rate was set in driver and in
- * emulator.
- */
-static void check_set_rate_f(struct i2c_emul *emul, int rate, int rnd,
-			     int exp_rate, int line)
-{
-	uint8_t exp_rate_reg;
-	uint8_t rate_reg;
-	int drv_rate;
-
-	zassert_equal(EC_SUCCESS, ms.drv->set_data_rate(&ms, rate, rnd),
-		      "set_data_rate failed; line: %d", line);
-	drv_rate = ms.drv->get_data_rate(&ms);
-	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
-		      exp_rate, drv_rate, line);
-	rate_reg = bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR);
-	rate_reg &= BMA2x2_BW_MSK;
-
-	switch (exp_rate) {
-	case 7812:
-		exp_rate_reg = BMA2x2_BW_7_81HZ;
-		break;
-	case 15625:
-		exp_rate_reg = BMA2x2_BW_15_63HZ;
-		break;
-	case 31250:
-		exp_rate_reg = BMA2x2_BW_31_25HZ;
-		break;
-	case 62500:
-		exp_rate_reg = BMA2x2_BW_62_50HZ;
-		break;
-	case 125000:
-		exp_rate_reg = BMA2x2_BW_125HZ;
-		break;
-	case 250000:
-		exp_rate_reg = BMA2x2_BW_250HZ;
-		break;
-	case 500000:
-		exp_rate_reg = BMA2x2_BW_500HZ;
-		break;
-	case 1000000:
-		exp_rate_reg = BMA2x2_BW_1000HZ;
-		break;
-	default:
-		/* Unknown expected rate */
-		zassert_unreachable(
-			"Expected rate %d not supported by device; line %d",
-			exp_rate, line);
-		return;
-	}
-
-	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
-}
-#define check_set_rate(emul, rate, rnd, exp_rate)	\
-	check_set_rate_f(emul, rate, rnd, exp_rate, __LINE__)
-
-/** Test set and get rate with and without I2C errors. */
-static void test_bma_rate(void)
-{
-	struct i2c_emul *emul;
-	uint8_t reg_rate;
-	int drv_rate;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Test setting rate with rounding down */
-	check_set_rate(emul, 1, 0, 7812);
-	check_set_rate(emul, 1, 0, 7812);
-	check_set_rate(emul, 7811, 0, 7812);
-	check_set_rate(emul, 7812, 0, 7812);
-	check_set_rate(emul, 7813, 0, 7812);
-	check_set_rate(emul, 15624, 0, 7812);
-	check_set_rate(emul, 15625, 0, 15625);
-	check_set_rate(emul, 15626, 0, 15625);
-	check_set_rate(emul, 31249, 0, 15625);
-	check_set_rate(emul, 31250, 0, 31250);
-	check_set_rate(emul, 31251, 0, 31250);
-	check_set_rate(emul, 62499, 0, 31250);
-	check_set_rate(emul, 62500, 0, 62500);
-	check_set_rate(emul, 62501, 0, 62500);
-	check_set_rate(emul, 124999, 0, 62500);
-	check_set_rate(emul, 125000, 0, 125000);
-	check_set_rate(emul, 125001, 0, 125000);
-	check_set_rate(emul, 249999, 0, 125000);
-	check_set_rate(emul, 250000, 0, 250000);
-	check_set_rate(emul, 250001, 0, 250000);
-	check_set_rate(emul, 499999, 0, 250000);
-	check_set_rate(emul, 500000, 0, 500000);
-	check_set_rate(emul, 500001, 0, 500000);
-	check_set_rate(emul, 999999, 0, 500000);
-	check_set_rate(emul, 1000000, 0, 1000000);
-	check_set_rate(emul, 1000001, 0, 1000000);
-	check_set_rate(emul, 2000000, 0, 1000000);
-
-	/* Test setting rate with rounding up */
-	check_set_rate(emul, 1, 1, 7812);
-	check_set_rate(emul, 1, 1, 7812);
-	check_set_rate(emul, 7811, 1, 7812);
-	check_set_rate(emul, 7812, 1, 7812);
-	check_set_rate(emul, 7813, 1, 15625);
-	check_set_rate(emul, 15624, 1, 15625);
-	check_set_rate(emul, 15625, 1, 15625);
-	check_set_rate(emul, 15626, 1, 31250);
-	check_set_rate(emul, 31249, 1, 31250);
-	check_set_rate(emul, 31250, 1, 31250);
-	check_set_rate(emul, 31251, 1, 62500);
-	check_set_rate(emul, 62499, 1, 62500);
-	check_set_rate(emul, 62500, 1, 62500);
-	check_set_rate(emul, 62501, 1, 125000);
-	check_set_rate(emul, 124999, 1, 125000);
-	check_set_rate(emul, 125000, 1, 125000);
-	check_set_rate(emul, 125001, 1, 250000);
-	check_set_rate(emul, 249999, 1, 250000);
-	check_set_rate(emul, 250000, 1, 250000);
-	check_set_rate(emul, 250001, 1, 500000);
-	check_set_rate(emul, 499999, 1, 500000);
-	check_set_rate(emul, 500000, 1, 500000);
-	check_set_rate(emul, 500001, 1, 1000000);
-	check_set_rate(emul, 999999, 1, 1000000);
-	check_set_rate(emul, 1000000, 1, 1000000);
-	check_set_rate(emul, 1000001, 1, 1000000);
-	check_set_rate(emul, 2000000, 1, 1000000);
-
-	/* Current rate shouldn't be changed on error */
-	drv_rate = ms.drv->get_data_rate(&ms);
-	reg_rate = bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_BW_SELECT_ADDR);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL);
-	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
-		      NULL);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL);
-	zassert_equal(reg_rate,
-		      bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_BW_SELECT_ADDR);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL);
-	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
-		      NULL);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL);
-	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
-		      NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-}
-
-/** Test read with and without I2C errors. */
-static void test_bma_read(void)
-{
-	struct i2c_emul *emul;
-	int16_t ret_acc[3];
-	int16_t exp_acc[3];
-	intv3_t ret_acc_v;
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Set offset 0 to simplify test */
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, 0);
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, 0);
-	bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, 0);
-
-	/* Test fail on each axis */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_X_AXIS_LSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_X_AXIS_MSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Y_AXIS_LSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Y_AXIS_MSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Z_AXIS_LSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Z_AXIS_MSB_ADDR);
-	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set input accelerometer values */
-	exp_acc[0] = BMA_EMUL_1G / 10;
-	exp_acc[1] = BMA_EMUL_1G / 20;
-	exp_acc[2] = -(int)BMA_EMUL_1G / 30;
-	set_emul_acc(emul, exp_acc);
-	/* Disable rotation */
-	ms.rot_standard_ref = NULL;
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 2, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v), NULL);
-	drv_acc_to_emul(ret_acc_v, 2, ret_acc);
-	compare_int3v(exp_acc, ret_acc);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 4, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v), NULL);
-	drv_acc_to_emul(ret_acc_v, 4, ret_acc);
-	compare_int3v(exp_acc, ret_acc);
-
-	/* Setup rotation and rotate expected vector */
-	ms.rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_acc);
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 2, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v), NULL);
-	drv_acc_to_emul(ret_acc_v, 2, ret_acc);
-	compare_int3v(exp_acc, ret_acc);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, 4, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->read(&ms, ret_acc_v), NULL);
-	drv_acc_to_emul(ret_acc_v, 4, ret_acc);
-	compare_int3v(exp_acc, ret_acc);
-}
-
-/** Data for functions used in perform_calib test */
-struct calib_func_data {
-	/** Time when offset compensation where triggered */
-	int calib_start;
-	/** Time how long offset cal ready should be unset */
-	int time;
-	/** Flag indicate if read should fail after compensation is triggered */
-	int read_fail;
-};
-
-/**
- * Custom emulator read function used in perform_calib test. It controls if
- * cal ready bit in offset control register should be set. It is set after
- * data.time miliseconds passed from data.calib_start time. Function returns
- * error when offset control register is accessed when cal ready bit is not set
- * and data.read_fail is not zero.
- */
-static int emul_read_calib_func(struct i2c_emul *emul, int reg, uint8_t *val,
-				int bytes, void *data)
-{
-	struct calib_func_data *d = data;
-	uint8_t reg_val;
-	int cur_time;
-
-	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
-	if (reg != BMA2x2_OFFSET_CTRL_ADDR) {
-		return 1;
-	}
-
-	reg_val = bma_emul_get_reg(emul, BMA2x2_OFFSET_CTRL_ADDR);
-	cur_time = k_uptime_get_32();
-	if (cur_time - d->calib_start < d->time) {
-		if (d->read_fail) {
-			return -EIO;
-		}
-		reg_val &= ~BMA2x2_OFFSET_CAL_READY;
-	} else {
-		reg_val |= BMA2x2_OFFSET_CAL_READY;
-	}
-	bma_emul_set_reg(emul, BMA2x2_OFFSET_CTRL_ADDR, reg_val);
-
-	return 1;
-}
-
-/**
- * Custom emulator write function used in perform_calib test. It sets
- * calib_start field in data with time when offset compensation process was
- * triggerd.
- */
-static int emul_write_calib_func(struct i2c_emul *emul, int reg, uint8_t val,
-				 int bytes, void *data)
-{
-	struct calib_func_data *d = data;
-
-	reg = bma_emul_access_reg(emul, reg, bytes, false /* = read */);
-	if (reg != BMA2x2_OFFSET_CTRL_ADDR) {
-		return 1;
-	}
-
-	if (val & BMA2x2_OFFSET_TRIGGER_MASK) {
-		d->calib_start = k_uptime_get_32();
-	}
-
-	return 1;
-}
-
-/** Test offset compensation with and without I2C errors. */
-static void test_bma_perform_calib(void)
-{
-	struct calib_func_data func_data;
-	struct i2c_emul *emul;
-	int16_t start_off[3];
-	int16_t exp_off[3];
-	int16_t ret_off[3];
-	int range;
-	int rate;
-	mat33_fp_t rot = {
-		{ FLOAT_TO_FP(1), 0, 0},
-		{ 0, FLOAT_TO_FP(1), 0},
-		{ 0, 0, FLOAT_TO_FP(-1)}
-	};
-
-	emul = bma_emul_get(BMA_ORD);
-
-	/* Range and rate cannot change after calibration */
-	range = 4;
-	rate = 125000;
-	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms.drv->set_data_rate(&ms, rate, 0), NULL);
-
-	/* Set offset 0 */
-	start_off[0] = 0;
-	start_off[1] = 0;
-	start_off[2] = 0;
-	set_emul_offset(emul, start_off);
-
-	/* Set input accelerometer values */
-	exp_off[0] = BMA_EMUL_1G / 10;
-	exp_off[1] = BMA_EMUL_1G / 20;
-	exp_off[2] = -(int)BMA_EMUL_1G / 30;
-	set_emul_acc(emul, exp_off);
-
-	/*
-	 * Expected offset is [-X, -Y, 1G - Z] for no rotation or positive
-	 * rotation on Z axis
-	 */
-	exp_off[0] = -exp_off[0];
-	exp_off[1] = -exp_off[1];
-	exp_off[2] = BMA_EMUL_1G - exp_off[2];
-
-	/* Setup emulator calibration functions */
-	i2c_common_emul_set_read_func(emul, emul_read_calib_func, &func_data);
-	i2c_common_emul_set_write_func(emul, emul_write_calib_func, &func_data);
-
-	/* Setup emulator to fail on first access to offset control register */
-	func_data.calib_start = k_uptime_get_32();
-	func_data.read_fail = 1;
-	func_data.time = 1000000;
-
-	/* Test success on disabling calibration */
-	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 0), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-
-	/* Test fail on first access to offset control register */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-
-	/* Setup emulator to return cal not ready */
-	func_data.calib_start = k_uptime_get_32();
-	func_data.read_fail = 0;
-	func_data.time = 1000000;
-
-	/* Test fail on cal not ready */
-	zassert_equal(EC_ERROR_ACCESS_DENIED, ms.drv->perform_calib(&ms, 1),
-		      NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-
-	/*
-	 * Setup emulator to fail on access to offset control register after
-	 * triggering offset compensation
-	 */
-	func_data.calib_start = 0;
-	func_data.read_fail = 1;
-	func_data.time = 160;
-
-	/* Test fail on read during offset compensation */
-	zassert_equal(EC_ERROR_INVAL, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-
-	/*
-	 * Setup emulator to return cal not ready for 1s after triggering
-	 * offset compensation
-	 */
-	func_data.calib_start = 0;
-	func_data.read_fail = 0;
-	func_data.time = 1000;
-
-	zassert_equal(EC_RES_TIMEOUT, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-
-	/*
-	 * Setup emulator to return cal not ready for 160ms after triggering
-	 * offset compensation
-	 */
-	func_data.calib_start = 0;
-	func_data.read_fail = 0;
-	func_data.time = 160;
-	/* Disable rotation */
-	ms.rot_standard_ref = NULL;
-
-	/* Test successful offset compenastion without rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-	get_emul_offset(emul, ret_off);
-	compare_int3v(exp_off, ret_off);
-
-	func_data.calib_start = 0;
-	/* Enable rotation with negative value on Z axis */
-	ms.rot_standard_ref = &rot;
-	/* Expected offset -1G - accelerometer[Z] */
-	exp_off[2] = -((int)BMA_EMUL_1G) - bma_emul_get_acc(emul,
-							    BMA_EMUL_AXIS_Z);
-
-	/* Test successful offset compenastion with negative Z rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-	get_emul_offset(emul, ret_off);
-	compare_int3v(exp_off, ret_off);
-
-	func_data.calib_start = 0;
-	/* Set positive rotation on Z axis */
-	rot[2][2] = FLOAT_TO_FP(1);
-	/* Expected offset 1G - accelerometer[Z] */
-	exp_off[2] = BMA_EMUL_1G - bma_emul_get_acc(emul, BMA_EMUL_AXIS_Z);
-
-	/* Test successful offset compenastion with positive Z rotation */
-	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1), NULL);
-	zassert_equal(range, ms.current_range, NULL);
-	zassert_equal(rate, ms.drv->get_data_rate(&ms), NULL);
-	get_emul_offset(emul, ret_off);
-	compare_int3v(exp_off, ret_off);
-
-	/* Remove custom emulator functions */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
-}
-
-/** Test get resolution. */
-static void test_bma_get_resolution(void)
-{
-	/* Resolution should be always 12 bits */
-	zassert_equal(12, ms.drv->get_resolution(&ms), NULL);
-}
-
-void test_suite_bma2x2(void)
-{
-	k_mutex_init(&sensor_mutex);
-
-	ztest_test_suite(bma2x2,
-			 ztest_user_unit_test(test_bma_get_offset),
-			 ztest_user_unit_test(test_bma_set_offset),
-			 ztest_user_unit_test(test_bma_set_range),
-			 ztest_user_unit_test(test_bma_init),
-			 ztest_user_unit_test(test_bma_rate),
-			 ztest_user_unit_test(test_bma_read),
-			 ztest_user_unit_test(test_bma_perform_calib),
-			 ztest_user_unit_test(test_bma_get_resolution));
-	ztest_run_test_suite(bma2x2);
-}
diff --git a/zephyr/test/drivers/src/bmi160.c b/zephyr/test/drivers/src/bmi160.c
deleted file mode 100644
index ceb55896eb..0000000000
--- a/zephyr/test/drivers/src/bmi160.c
+++ /dev/null
@@ -1,1873 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c.h"
-#include "emul/emul_bmi.h"
-#include "emul/emul_common_i2c.h"
-
-#include "motion_sense_fifo.h"
-#include "driver/accelgyro_bmi160.h"
-#include "driver/accelgyro_bmi_common.h"
-
-#define BMI_ORD			DT_DEP_ORD(DT_NODELABEL(accel_bmi160))
-#define BMI_ACC_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi160_accel))
-#define BMI_GYR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro))
-#define BMI_INT_EVENT		\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
-
-/** How accurate comparision of vectors should be */
-#define V_EPS		8
-
-/** Convert from one type of vector to another */
-#define convert_int3v_int16(v, r) do {	\
-		r[0] = v[0];		\
-		r[1] = v[1];		\
-		r[2] = v[2];		\
-	} while (0)
-
-/** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-/** Rotate given vector by test rotation */
-static void rotate_int3v_by_test_rotation(intv3_t v)
-{
-	int16_t t;
-
-	t = v[0];
-	v[0] = -v[1];
-	v[1] = t;
-	v[2] = -v[2];
-}
-
-/** Set emulator accelerometer offset values to intv3_t vector */
-static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, offset[2]);
-}
-
-/** Save emulator accelerometer offset values to intv3_t vector */
-static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
-	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
-	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Z);
-}
-
-/** Set emulator accelerometer values to intv3_t vector */
-static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
-{
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, acc[2]);
-}
-
-/** Set emulator gyroscope offset values to intv3_t vector */
-static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, offset[2]);
-}
-
-/** Save emulator gyroscope offset values to intv3_t vector */
-static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
-	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
-	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Z);
-}
-
-/** Set emulator gyroscope values to vector of three int16_t */
-static void set_emul_gyr(struct i2c_emul *emul, intv3_t gyr)
-{
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_Z, gyr[2]);
-}
-
-/** Convert accelerometer read to units used by emulator */
-static void drv_acc_to_emul(intv3_t drv, int range, intv3_t out)
-{
-	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_1G;
-
-	out[0] = drv[0] * range / scale;
-	out[1] = drv[1] * range / scale;
-	out[2] = drv[2] * range / scale;
-}
-
-/** Convert gyroscope read to units used by emulator */
-static void drv_gyr_to_emul(intv3_t drv, int range, intv3_t out)
-{
-	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_125_DEG_S;
-
-	range /= 125;
-	out[0] = drv[0] * range / scale;
-	out[1] = drv[1] * range / scale;
-	out[2] = drv[2] * range / scale;
-}
-
-/** Compare two vectors of intv3_t type */
-static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
-{
-	int i;
-
-	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], eps,
-			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
-			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
-	}
-}
-#define compare_int3v_eps(exp_v, v, e) compare_int3v_f(exp_v, v, e, __LINE__)
-#define compare_int3v(exp_v, v) compare_int3v_eps(exp_v, v, V_EPS)
-
-/** Test get accelerometer offset with and without rotation */
-static void test_bmi_acc_get_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t ret[3];
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Set emulator offset */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	set_emul_acc_offset(emul, exp_v);
-	/* BMI driver returns value in mg units */
-	exp_v[0] = 1000 / 10;
-	exp_v[1] = 1000 / 20;
-	exp_v[2] = -1000 / 30;
-
-	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected offset */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-
-	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v(exp_v, ret_v);
-}
-
-/** Test get gyroscope offset with and without rotation */
-static void test_bmi_gyr_get_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t ret[3];
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set emulator offset */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	set_emul_gyr_offset(emul, exp_v);
-	/* BMI driver returns value in mdeg/s units */
-	exp_v[0] = 125000 / 100;
-	exp_v[1] = 125000 / 200;
-	exp_v[2] = -125000 / 300;
-
-	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-
-	/* Setup rotation and rotate expected offset */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-
-	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-}
-
-/**
- * Test set accelerometer offset with and without rotation. Also test behaviour
- * on I2C error.
- */
-static void test_bmi_acc_set_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t input_v[3];
-	int16_t temp = 0;
-	intv3_t ret_v;
-	intv3_t exp_v;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set input offset */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	/* BMI driver accept value in mg units */
-	input_v[0] = 1000 / 10;
-	input_v[1] = 1000 / 20;
-	input_v[2] = -1000 / 30;
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test set offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_acc_offset(emul, ret_v);
-	/*
-	 * Depending on used range, accelerometer values may be up to 6 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_v, ret_v, 64);
-	/* Accelerometer offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
-
-	/* Setup rotation and rotate input for set_offset function */
-	ms->rot_standard_ref = &test_rotation;
-	convert_int3v_int16(input_v, ret_v);
-	rotate_int3v_by_test_rotation(ret_v);
-	convert_int3v_int16(ret_v, input_v);
-
-	/* Test set offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_acc_offset(emul, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-	/* Accelerometer offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
-}
-
-/**
- * Test set gyroscope offset with and without rotation. Also test behaviour
- * on I2C error.
- */
-static void test_bmi_gyr_set_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t input_v[3];
-	int16_t temp = 0;
-	intv3_t ret_v;
-	intv3_t exp_v;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set input offset */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	/* BMI driver accept value in mdeg/s units */
-	input_v[0] = 125000 / 100;
-	input_v[1] = 125000 / 200;
-	input_v[2] = -125000 / 300;
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test set offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_gyr_offset(emul, ret_v);
-	compare_int3v(exp_v, ret_v);
-	/* Gyroscope offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
-
-	/* Setup rotation and rotate input for set_offset function */
-	ms->rot_standard_ref = &test_rotation;
-	convert_int3v_int16(input_v, ret_v);
-	rotate_int3v_by_test_rotation(ret_v);
-	convert_int3v_int16(ret_v, input_v);
-
-	/* Test set offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_gyr_offset(emul, ret_v);
-	compare_int3v(exp_v, ret_v);
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
-}
-
-/**
- * Try to set accelerometer range and check if expected range was set
- * in driver and in emulator.
- */
-static void check_set_acc_range_f(struct i2c_emul *emul,
-				  struct motion_sensor_t *ms, int range,
-				  int rnd, int exp_range, int line)
-{
-	uint8_t exp_range_reg;
-	uint8_t range_reg;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
-		      "set_range failed; line: %d", line);
-	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
-	range_reg = bmi_emul_get_reg(emul, BMI160_ACC_RANGE);
-
-	switch (exp_range) {
-	case 2:
-		exp_range_reg = BMI160_GSEL_2G;
-		break;
-	case 4:
-		exp_range_reg = BMI160_GSEL_4G;
-		break;
-	case 8:
-		exp_range_reg = BMI160_GSEL_8G;
-		break;
-	case 16:
-		exp_range_reg = BMI160_GSEL_16G;
-		break;
-	default:
-		/* Unknown expected range */
-		zassert_unreachable(
-			"Expected range %d not supported by device; line %d",
-			exp_range, line);
-		return;
-	}
-
-	zassert_equal(exp_range_reg, range_reg,
-		      "Expected range reg 0x%x, got 0x%x; line %d",
-		      exp_range_reg, range_reg, line);
-}
-#define check_set_acc_range(emul, ms, range, rnd, exp_range)	\
-	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
-
-/** Test set accelerometer range with and without I2C errors */
-static void test_bmi_acc_set_range(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int start_range;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Setup starting range, shouldn't be changed on error */
-	start_range = 2;
-	ms->current_range = start_range;
-	bmi_emul_set_reg(emul, BMI160_ACC_RANGE, BMI160_GSEL_2G);
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_ACC_RANGE);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting range with rounding down */
-	check_set_acc_range(emul, ms, 1, 0, 2);
-	check_set_acc_range(emul, ms, 2, 0, 2);
-	check_set_acc_range(emul, ms, 3, 0, 2);
-	check_set_acc_range(emul, ms, 4, 0, 4);
-	check_set_acc_range(emul, ms, 5, 0, 4);
-	check_set_acc_range(emul, ms, 6, 0, 4);
-	check_set_acc_range(emul, ms, 7, 0, 4);
-	check_set_acc_range(emul, ms, 8, 0, 8);
-	check_set_acc_range(emul, ms, 9, 0, 8);
-	check_set_acc_range(emul, ms, 15, 0, 8);
-	check_set_acc_range(emul, ms, 16, 0, 16);
-	check_set_acc_range(emul, ms, 17, 0, 16);
-
-	/* Test setting range with rounding up */
-	check_set_acc_range(emul, ms, 1, 1, 2);
-	check_set_acc_range(emul, ms, 2, 1, 2);
-	check_set_acc_range(emul, ms, 3, 1, 4);
-	check_set_acc_range(emul, ms, 4, 1, 4);
-	check_set_acc_range(emul, ms, 5, 1, 8);
-	check_set_acc_range(emul, ms, 6, 1, 8);
-	check_set_acc_range(emul, ms, 7, 1, 8);
-	check_set_acc_range(emul, ms, 8, 1, 8);
-	check_set_acc_range(emul, ms, 9, 1, 16);
-	check_set_acc_range(emul, ms, 15, 1, 16);
-	check_set_acc_range(emul, ms, 16, 1, 16);
-	check_set_acc_range(emul, ms, 17, 1, 16);
-}
-
-/**
- * Try to set gyroscope range and check if expected range was set in driver and
- * in emulator.
- */
-static void check_set_gyr_range_f(struct i2c_emul *emul,
-				  struct motion_sensor_t *ms, int range,
-				  int rnd, int exp_range, int line)
-{
-	uint8_t exp_range_reg;
-	uint8_t range_reg;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
-		      "set_range failed; line: %d", line);
-	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
-	range_reg = bmi_emul_get_reg(emul, BMI160_GYR_RANGE);
-
-	switch (exp_range) {
-	case 125:
-		exp_range_reg = BMI160_DPS_SEL_125;
-		break;
-	case 250:
-		exp_range_reg = BMI160_DPS_SEL_250;
-		break;
-	case 500:
-		exp_range_reg = BMI160_DPS_SEL_500;
-		break;
-	case 1000:
-		exp_range_reg = BMI160_DPS_SEL_1000;
-		break;
-	case 2000:
-		exp_range_reg = BMI160_DPS_SEL_2000;
-		break;
-	default:
-		/* Unknown expected range */
-		zassert_unreachable(
-			"Expected range %d not supported by device; line %d",
-			exp_range, line);
-		return;
-	}
-
-	zassert_equal(exp_range_reg, range_reg,
-		      "Expected range reg 0x%x, got 0x%x; line %d",
-		      exp_range_reg, range_reg, line);
-}
-#define check_set_gyr_range(emul, ms, range, rnd, exp_range)	\
-	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
-
-/** Test set gyroscope range with and without I2C errors */
-static void test_bmi_gyr_set_range(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int start_range;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Setup starting range, shouldn't be changed on error */
-	start_range = 250;
-	ms->current_range = start_range;
-	bmi_emul_set_reg(emul, BMI160_GYR_RANGE, BMI160_DPS_SEL_250);
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_GYR_RANGE);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_DPS_SEL_250,
-		      bmi_emul_get_reg(emul, BMI160_GYR_RANGE), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 1), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_DPS_SEL_250,
-		      bmi_emul_get_reg(emul, BMI160_GYR_RANGE), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting range with rounding down */
-	check_set_gyr_range(emul, ms, 1, 0, 125);
-	check_set_gyr_range(emul, ms, 124, 0, 125);
-	check_set_gyr_range(emul, ms, 125, 0, 125);
-	check_set_gyr_range(emul, ms, 126, 0, 125);
-	check_set_gyr_range(emul, ms, 249, 0, 125);
-	check_set_gyr_range(emul, ms, 250, 0, 250);
-	check_set_gyr_range(emul, ms, 251, 0, 250);
-	check_set_gyr_range(emul, ms, 499, 0, 250);
-	check_set_gyr_range(emul, ms, 500, 0, 500);
-	check_set_gyr_range(emul, ms, 501, 0, 500);
-	check_set_gyr_range(emul, ms, 999, 0, 500);
-	check_set_gyr_range(emul, ms, 1000, 0, 1000);
-	check_set_gyr_range(emul, ms, 1001, 0, 1000);
-	check_set_gyr_range(emul, ms, 1999, 0, 1000);
-	check_set_gyr_range(emul, ms, 2000, 0, 2000);
-	check_set_gyr_range(emul, ms, 2001, 0, 2000);
-
-	/* Test setting range with rounding up */
-	check_set_gyr_range(emul, ms, 1, 1, 125);
-	check_set_gyr_range(emul, ms, 124, 1, 125);
-	check_set_gyr_range(emul, ms, 125, 1, 125);
-	check_set_gyr_range(emul, ms, 126, 1, 250);
-	check_set_gyr_range(emul, ms, 249, 1, 250);
-	check_set_gyr_range(emul, ms, 250, 1, 250);
-	check_set_gyr_range(emul, ms, 251, 1, 500);
-	check_set_gyr_range(emul, ms, 499, 1, 500);
-	check_set_gyr_range(emul, ms, 500, 1, 500);
-	check_set_gyr_range(emul, ms, 501, 1, 1000);
-	check_set_gyr_range(emul, ms, 999, 1, 1000);
-	check_set_gyr_range(emul, ms, 1000, 1, 1000);
-	check_set_gyr_range(emul, ms, 1001, 1, 2000);
-	check_set_gyr_range(emul, ms, 1999, 1, 2000);
-	check_set_gyr_range(emul, ms, 2000, 1, 2000);
-	check_set_gyr_range(emul, ms, 2001, 1, 2000);
-}
-
-/** Test get resolution of acclerometer and gyroscope sensor */
-static void test_bmi_get_resolution(void)
-{
-	struct motion_sensor_t *ms;
-
-	/* Test accelerometer */
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Resolution should be always 16 bits */
-	zassert_equal(16, ms->drv->get_resolution(ms), NULL);
-
-	/* Test gyroscope */
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Resolution should be always 16 bits */
-	zassert_equal(16, ms->drv->get_resolution(ms), NULL);
-}
-
-/**
- * Try to set accelerometer data rate and check if expected rate was set
- * in driver and in emulator.
- */
-static void check_set_acc_rate_f(struct i2c_emul *emul,
-				 struct motion_sensor_t *ms, int rate, int rnd,
-				 int exp_rate, int line)
-{
-	uint8_t exp_rate_reg;
-	uint8_t rate_reg;
-	int drv_rate;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
-		      "set_data_rate failed; line: %d", line);
-	drv_rate = ms->drv->get_data_rate(ms);
-	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
-		      exp_rate, drv_rate, line);
-	rate_reg = bmi_emul_get_reg(emul, BMI160_ACC_CONF);
-	rate_reg &= BMI_ODR_MASK;
-
-	switch (exp_rate) {
-	case 12500:
-		exp_rate_reg = 0x5;
-		break;
-	case 25000:
-		exp_rate_reg = 0x6;
-		break;
-	case 50000:
-		exp_rate_reg = 0x7;
-		break;
-	case 100000:
-		exp_rate_reg = 0x8;
-		break;
-	case 200000:
-		exp_rate_reg = 0x9;
-		break;
-	case 400000:
-		exp_rate_reg = 0xa;
-		break;
-	case 800000:
-		exp_rate_reg = 0xb;
-		break;
-	case 1600000:
-		exp_rate_reg = 0xc;
-		break;
-	default:
-		/* Unknown expected rate */
-		zassert_unreachable(
-			"Expected rate %d not supported by device; line %d",
-			exp_rate, line);
-		return;
-	}
-
-	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
-}
-#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate)	\
-	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
-
-/** Test set and get accelerometer rate with and without I2C errors */
-static void test_bmi_acc_rate(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t reg_rate;
-	int pmu_status;
-	int drv_rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Test setting rate with rounding down */
-	check_set_acc_rate(emul, ms, 12500, 0, 12500);
-	check_set_acc_rate(emul, ms, 12501, 0, 12500);
-	check_set_acc_rate(emul, ms, 24999, 0, 12500);
-	check_set_acc_rate(emul, ms, 25000, 0, 25000);
-	check_set_acc_rate(emul, ms, 25001, 0, 25000);
-	check_set_acc_rate(emul, ms, 49999, 0, 25000);
-	check_set_acc_rate(emul, ms, 50000, 0, 50000);
-	check_set_acc_rate(emul, ms, 50001, 0, 50000);
-	check_set_acc_rate(emul, ms, 99999, 0, 50000);
-	check_set_acc_rate(emul, ms, 100000, 0, 100000);
-	check_set_acc_rate(emul, ms, 100001, 0, 100000);
-	check_set_acc_rate(emul, ms, 199999, 0, 100000);
-	check_set_acc_rate(emul, ms, 200000, 0, 200000);
-	check_set_acc_rate(emul, ms, 200001, 0, 200000);
-	check_set_acc_rate(emul, ms, 399999, 0, 200000);
-	/*
-	 * We cannot test frequencies from 400000 to 1600000 because
-	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
-	 */
-
-	/* Test setting rate with rounding up */
-	check_set_acc_rate(emul, ms, 6251, 1, 12500);
-	check_set_acc_rate(emul, ms, 12499, 1, 12500);
-	check_set_acc_rate(emul, ms, 12500, 1, 12500);
-	check_set_acc_rate(emul, ms, 12501, 1, 25000);
-	check_set_acc_rate(emul, ms, 24999, 1, 25000);
-	check_set_acc_rate(emul, ms, 25000, 1, 25000);
-	check_set_acc_rate(emul, ms, 25001, 1, 50000);
-	check_set_acc_rate(emul, ms, 49999, 1, 50000);
-	check_set_acc_rate(emul, ms, 50000, 1, 50000);
-	check_set_acc_rate(emul, ms, 50001, 1, 100000);
-	check_set_acc_rate(emul, ms, 99999, 1, 100000);
-	check_set_acc_rate(emul, ms, 100000, 1, 100000);
-	check_set_acc_rate(emul, ms, 100001, 1, 200000);
-	check_set_acc_rate(emul, ms, 199999, 1, 200000);
-	check_set_acc_rate(emul, ms, 200000, 1, 200000);
-
-	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
-
-	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 6250, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 2000000, 1), NULL);
-
-	/* Current rate shouldn't be changed on error */
-	drv_rate = ms->drv->get_data_rate(ms);
-	reg_rate = bmi_emul_get_reg(emul, BMI160_ACC_CONF);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_CONF);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_ACC_CONF);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test disabling sensor */
-	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
-	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
-
-	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
-		  &pmu_status);
-	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET, pmu_status,
-		      "Gyroscope should be still enabled");
-
-	/* Test enabling sensor */
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-
-	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
-		  &pmu_status);
-	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET, pmu_status,
-		      "Accelerometer should be enabled");
-}
-
-/**
- * Try to set gyroscope data rate and check if expected rate was set
- * in driver and in emulator.
- */
-static void check_set_gyr_rate_f(struct i2c_emul *emul,
-				 struct motion_sensor_t *ms, int rate, int rnd,
-				 int exp_rate, int line)
-{
-	uint8_t exp_rate_reg;
-	uint8_t rate_reg;
-	int drv_rate;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
-		      "set_data_rate failed; line: %d", line);
-	drv_rate = ms->drv->get_data_rate(ms);
-	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
-		      exp_rate, drv_rate, line);
-	rate_reg = bmi_emul_get_reg(emul, BMI160_GYR_CONF);
-	rate_reg &= BMI_ODR_MASK;
-
-	switch (exp_rate) {
-	case 25000:
-		exp_rate_reg = 0x6;
-		break;
-	case 50000:
-		exp_rate_reg = 0x7;
-		break;
-	case 100000:
-		exp_rate_reg = 0x8;
-		break;
-	case 200000:
-		exp_rate_reg = 0x9;
-		break;
-	case 400000:
-		exp_rate_reg = 0xa;
-		break;
-	case 800000:
-		exp_rate_reg = 0xb;
-		break;
-	case 1600000:
-		exp_rate_reg = 0xc;
-		break;
-	case 3200000:
-		exp_rate_reg = 0xc;
-		break;
-	default:
-		/* Unknown expected rate */
-		zassert_unreachable(
-			"Expected rate %d not supported by device; line %d",
-			exp_rate, line);
-		return;
-	}
-
-	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
-}
-#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate)	\
-	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
-
-/** Test set and get gyroscope rate with and without I2C errors */
-static void test_bmi_gyr_rate(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t reg_rate;
-	int pmu_status;
-	int drv_rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Test setting rate with rounding down */
-	check_set_gyr_rate(emul, ms, 25000, 0, 25000);
-	check_set_gyr_rate(emul, ms, 25001, 0, 25000);
-	check_set_gyr_rate(emul, ms, 49999, 0, 25000);
-	check_set_gyr_rate(emul, ms, 50000, 0, 50000);
-	check_set_gyr_rate(emul, ms, 50001, 0, 50000);
-	check_set_gyr_rate(emul, ms, 99999, 0, 50000);
-	check_set_gyr_rate(emul, ms, 100000, 0, 100000);
-	check_set_gyr_rate(emul, ms, 100001, 0, 100000);
-	check_set_gyr_rate(emul, ms, 199999, 0, 100000);
-	check_set_gyr_rate(emul, ms, 200000, 0, 200000);
-	check_set_gyr_rate(emul, ms, 200001, 0, 200000);
-	check_set_gyr_rate(emul, ms, 399999, 0, 200000);
-	/*
-	 * We cannot test frequencies from 400000 to 3200000 because
-	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
-	 */
-
-	/* Test setting rate with rounding up */
-	check_set_gyr_rate(emul, ms, 12501, 1, 25000);
-	check_set_gyr_rate(emul, ms, 24999, 1, 25000);
-	check_set_gyr_rate(emul, ms, 25000, 1, 25000);
-	check_set_gyr_rate(emul, ms, 25001, 1, 50000);
-	check_set_gyr_rate(emul, ms, 49999, 1, 50000);
-	check_set_gyr_rate(emul, ms, 50000, 1, 50000);
-	check_set_gyr_rate(emul, ms, 50001, 1, 100000);
-	check_set_gyr_rate(emul, ms, 99999, 1, 100000);
-	check_set_gyr_rate(emul, ms, 100000, 1, 100000);
-	check_set_gyr_rate(emul, ms, 100001, 1, 200000);
-	check_set_gyr_rate(emul, ms, 199999, 1, 200000);
-	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
-
-	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
-
-	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 4000000, 1), NULL);
-
-	/* Current rate shouldn't be changed on error */
-	drv_rate = ms->drv->get_data_rate(ms);
-	reg_rate = bmi_emul_get_reg(emul, BMI160_GYR_CONF);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_CONF);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_GYR_CONF);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test disabling sensor */
-	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
-	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
-
-	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
-		  &pmu_status);
-	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET, pmu_status,
-		      "Accelerometer should be still enabled");
-
-	/* Test enabling sensor */
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-
-	bmi_read8(ms->port, ms->i2c_spi_addr_flags, BMI160_PMU_STATUS,
-		  &pmu_status);
-	zassert_equal(BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET, pmu_status,
-		      "Gyroscope should be enabled");
-}
-
-/**
- * Test setting and getting scale in accelerometer and gyroscope sensors.
- * Correct appling scale to results is checked in "read" test.
- */
-static void test_bmi_scale(void)
-{
-	struct motion_sensor_t *ms;
-	int16_t ret_scale[3];
-	int16_t exp_scale[3] = {100, 231, 421};
-	int16_t t;
-
-	/* Test accelerometer */
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t), NULL);
-
-	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	zassert_equal(exp_scale[0], ret_scale[0], NULL);
-	zassert_equal(exp_scale[1], ret_scale[1], NULL);
-	zassert_equal(exp_scale[2], ret_scale[2], NULL);
-
-	/* Test gyroscope */
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t), NULL);
-
-	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	zassert_equal(exp_scale[0], ret_scale[0], NULL);
-	zassert_equal(exp_scale[1], ret_scale[1], NULL);
-	zassert_equal(exp_scale[2], ret_scale[2], NULL);
-}
-
-/** Test reading temperature using accelerometer and gyroscope sensors */
-static void test_bmi_read_temp(void)
-{
-	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
-	int ret_temp;
-	int exp_temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_TEMPERATURE_0);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_TEMPERATURE_1);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Fail on invalid temperature */
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x80);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-
-	/*
-	 * Test correct values. Both motion sensors should return the same
-	 * temperature.
-	 */
-	exp_temp = C_TO_K(23);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x00);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(87);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0xff);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x7f);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(-41);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x01);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x80);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(47);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_1, 0x30);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-}
-
-/** Test reading accelerometer sensor data */
-static void test_bmi_acc_read(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Set offset 0 to simplify test */
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
-
-	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* When not ready, driver should return saved raw value */
-	exp_v[0] = 100;
-	exp_v[1] = 200;
-	exp_v[2] = 300;
-	ms->raw_xyz[0] = exp_v[0];
-	ms->raw_xyz[1] = exp_v[1];
-	ms->raw_xyz[2] = exp_v[2];
-
-	/* Status not ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status only GYR ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_GYR);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status ACC ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_ACC);
-
-	/* Set input accelerometer values */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	set_emul_acc(emul, exp_v);
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-	/* Set scale */
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0), NULL);
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 2, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 4, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected vector */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 2, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 4, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_X_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Y_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Y_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Z_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Z_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	ms->rot_standard_ref = NULL;
-}
-
-/** Test reading gyroscope sensor data */
-static void test_bmi_gyr_read(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Set offset 0 to simplify test */
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
-
-	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* When not ready, driver should return saved raw value */
-	exp_v[0] = 100;
-	exp_v[1] = 200;
-	exp_v[2] = 300;
-	ms->raw_xyz[0] = exp_v[0];
-	ms->raw_xyz[1] = exp_v[1];
-	ms->raw_xyz[2] = exp_v[2];
-
-	/* Status not ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status only ACC ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_ACC);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status GYR ready */
-	bmi_emul_set_reg(emul, BMI160_STATUS, BMI160_DRDY_GYR);
-
-	/* Set input accelerometer values */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 10;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 20;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 30;
-	set_emul_gyr(emul, exp_v);
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-	/* Set scale */
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0), NULL);
-	/* Set range to 125°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 125, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 1000°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 1000, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected vector */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-	/* Set range to 125°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 125, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 1000°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 1000, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_X_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Y_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Y_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Z_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Z_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	ms->rot_standard_ref = NULL;
-}
-
-/**
- * Custom emulatro read function which always return not ready STATUS register.
- * Used in calibration test.
- */
-static int emul_nrdy(struct i2c_emul *emul, int reg, uint8_t *val, int byte,
-		     void *data)
-{
-	if (reg == BMI160_STATUS) {
-		bmi_emul_set_reg(emul, BMI160_STATUS, 0);
-		*val = 0;
-
-		return 0;
-	}
-
-	return 1;
-}
-
-/** Test acceleromtere calibration */
-static void test_bmi_acc_perform_calib(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t pmu_status;
-	intv3_t start_off;
-	intv3_t exp_off;
-	intv3_t ret_off;
-	int range;
-	int rate;
-	mat33_fp_t rot = {
-		{ FLOAT_TO_FP(1), 0, 0},
-		{ 0, FLOAT_TO_FP(1), 0},
-		{ 0, 0, FLOAT_TO_FP(-1)}
-	};
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Enable sensors */
-	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
-	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
-
-	/* Range and rate cannot change after calibration */
-	range = 4;
-	rate = 50000;
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0), NULL);
-
-	/* Set offset 0 */
-	start_off[0] = 0;
-	start_off[1] = 0;
-	start_off[2] = 0;
-	set_emul_acc_offset(emul, start_off);
-
-	/* Set input accelerometer values */
-	exp_off[0] = BMI_EMUL_1G / 10;
-	exp_off[1] = BMI_EMUL_1G / 20;
-	exp_off[2] = BMI_EMUL_1G - (int)BMI_EMUL_1G / 30;
-	set_emul_acc(emul, exp_off);
-
-	/*
-	 * Expected offset is [-X, -Y, 1G - Z] for no rotation or positive
-	 * rotation on Z axis
-	 */
-	exp_off[0] = -exp_off[0];
-	exp_off[1] = -exp_off[1];
-	exp_off[2] = BMI_EMUL_1G - exp_off[2];
-
-	/* Test fail on rate set */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	/* Stop fast offset compensation before next test */
-	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
-
-	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(emul, emul_nrdy, NULL);
-	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-	/* Stop fast offset compensation before next test */
-	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
-
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-	/* Test successful offset compenastion without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_acc_offset(emul, ret_off);
-	/*
-	 * Depending on used range, accelerometer values may be up to 6 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_off, ret_off, 64);
-	/* Acelerometer offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
-
-	/* Enable rotation with negative value on Z axis */
-	ms->rot_standard_ref = &rot;
-	/* Expected offset -1G - accelerometer[Z] */
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, -(int)BMI_EMUL_1G - 1234);
-	exp_off[2] = 1234;
-
-	/* Test successful offset compenastion with negative Z rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_acc_offset(emul, ret_off);
-	compare_int3v_eps(exp_off, ret_off, 64);
-	/* Acelerometer offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
-
-	/* Set positive rotation on Z axis */
-	rot[2][2] = FLOAT_TO_FP(1);
-	/* Expected offset 1G - accelerometer[Z] */
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, BMI_EMUL_1G - 1234);
-	exp_off[2] = 1234;
-
-	/* Test successful offset compenastion with positive Z rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_acc_offset(emul, ret_off);
-	compare_int3v_eps(exp_off, ret_off, 64);
-	/* Acelerometer offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-}
-
-/** Test gyroscope calibration */
-static void test_bmi_gyr_perform_calib(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t pmu_status;
-	intv3_t start_off;
-	intv3_t exp_off;
-	intv3_t ret_off;
-	int range;
-	int rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Enable sensors */
-	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
-	pmu_status |= BMI160_PMU_NORMAL << BMI160_PMU_GYR_OFFSET;
-	bmi_emul_set_reg(emul, BMI160_PMU_STATUS, pmu_status);
-
-	/* Range and rate cannot change after calibration */
-	range = 250;
-	rate = 50000;
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0), NULL);
-
-	/* Set offset 0 */
-	start_off[0] = 0;
-	start_off[1] = 0;
-	start_off[2] = 0;
-	set_emul_gyr_offset(emul, start_off);
-
-	/* Set input accelerometer values */
-	exp_off[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_off[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_off[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	set_emul_gyr(emul, exp_off);
-
-	/* Expected offset is [-X, -Y, -Z] */
-	exp_off[0] = -exp_off[0];
-	exp_off[1] = -exp_off[1];
-	exp_off[2] = -exp_off[2];
-
-	/* Test success on disabling calibration */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on rate set */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	/* Stop fast offset compensation before next test */
-	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
-
-	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(emul, emul_nrdy, NULL);
-	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-	/* Stop fast offset compensation before next test */
-	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
-
-	/* Test successful offset compenastion */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_gyr_offset(emul, ret_off);
-	/*
-	 * Depending on used range, gyroscope values may be up to 4 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_off, ret_off, 32);
-	/* Gyroscope offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
-}
-
-/** Test init function of BMI160 accelerometer and gyroscope sensors */
-static void test_bmi_init(void)
-{
-	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Test successful init */
-	zassert_equal(EC_RES_SUCCESS, ms_acc->drv->init(ms_acc), NULL);
-
-	zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr), NULL);
-}
-
-/** Data for custom emulator read function used in FIFO test */
-struct fifo_func_data {
-	uint16_t interrupts;
-};
-
-/**
- * Custom emulator read function used in FIFO test. It sets interrupt registers
- * to value passed as additional data. It sets interrupt registers to 0 after
- * access.
- */
-static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
-			  int byte, void *data)
-{
-	struct fifo_func_data *d = data;
-
-	if (reg + byte == BMI160_INT_STATUS_0) {
-		bmi_emul_set_reg(emul, BMI160_INT_STATUS_0,
-				 d->interrupts & 0xff);
-		d->interrupts &= 0xff00;
-	} else if (reg + byte == BMI160_INT_STATUS_1) {
-		bmi_emul_set_reg(emul, BMI160_INT_STATUS_1,
-				 (d->interrupts >> 8) & 0xff);
-		d->interrupts &= 0xff;
-	}
-
-	return 1;
-}
-
-/**
- * Run irq handler on accelerometer sensor and check if committed data in FIFO
- * match what was set in FIFO frames in emulator.
- */
-static void check_fifo_f(struct motion_sensor_t *ms_acc,
-			 struct motion_sensor_t *ms_gyr,
-			 struct bmi_emul_frame *frame,
-			 int acc_range, int gyr_range,
-			 int line)
-{
-	struct ec_response_motion_sensor_data vector;
-	struct bmi_emul_frame *f_acc, *f_gyr;
-	uint32_t event = BMI_INT_EVENT;
-	uint16_t size;
-	intv3_t exp_v;
-	intv3_t ret_v;
-
-	/* Find first frame of acc and gyr type */
-	f_acc = frame;
-	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
-		f_acc = f_acc->next;
-	}
-
-	f_gyr = frame;
-	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
-		f_gyr = f_gyr->next;
-	}
-
-	/* Read FIFO in driver */
-	zassert_equal(EC_SUCCESS, ms_acc->drv->irq_handler(ms_acc, &event),
-		      NULL);
-
-	/* Read all data committed to FIFO */
-	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
-		/* Ignore timestamp frames */
-		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
-			continue;
-		}
-
-		/* Check acclerometer frames */
-		if (ms_acc - motion_sensors == vector.sensor_num) {
-			if (f_acc == NULL) {
-				zassert_unreachable(
-					"Not expected acclerometer data in FIFO, line %d",
-					line);
-			}
-
-			convert_int3v_int16(vector.data, ret_v);
-			drv_acc_to_emul(ret_v, acc_range, ret_v);
-			exp_v[0] = f_acc->acc_x;
-			exp_v[1] = f_acc->acc_y;
-			exp_v[2] = f_acc->acc_z;
-			compare_int3v_f(exp_v, ret_v, V_EPS, line);
-			f_acc = f_acc->next;
-		}
-
-		/* Check gyroscope frames */
-		if (ms_gyr - motion_sensors == vector.sensor_num) {
-			if (f_gyr == NULL) {
-				zassert_unreachable(
-					"Not expected gyroscope data in FIFO, line %d",
-					line);
-			}
-
-			convert_int3v_int16(vector.data, ret_v);
-			drv_gyr_to_emul(ret_v, gyr_range, ret_v);
-			exp_v[0] = f_gyr->gyr_x;
-			exp_v[1] = f_gyr->gyr_y;
-			exp_v[2] = f_gyr->gyr_z;
-			compare_int3v_f(exp_v, ret_v, V_EPS, line);
-			f_gyr = f_gyr->next;
-		}
-	}
-
-	/* Skip frames of different type at the end */
-	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
-		f_acc = f_acc->next;
-	}
-
-	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
-		f_gyr = f_gyr->next;
-	}
-
-	/* All frames are readed */
-	zassert_is_null(f_acc, "Not all accelerometer frames are read, line %d",
-			line);
-	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
-			line);
-}
-#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range)		\
-	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
-
-/** Test irq handler of accelerometer sensor */
-static void test_bmi_acc_fifo(void)
-{
-	struct motion_sensor_t *ms, *ms_gyr;
-	struct fifo_func_data func_data;
-	struct bmi_emul_frame f[3];
-	struct i2c_emul *emul;
-	int gyr_range = 125;
-	int acc_range = 2;
-	int event;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Need to be set to collect all data in FIFO */
-	ms->oversampling_ratio = 1;
-	ms_gyr->oversampling_ratio = 1;
-	/* Only BMI event should be handled */
-	event = 0x1234 & ~BMI_INT_EVENT;
-	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
-		      NULL);
-
-	event = BMI_INT_EVENT;
-
-	/* Test fail to read interrupt status registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_INT_STATUS_0);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_INT_STATUS_1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test no interrupt */
-	bmi_emul_set_reg(emul, BMI160_INT_STATUS_0, 0);
-	bmi_emul_set_reg(emul, BMI160_INT_STATUS_1, 0);
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
-
-	/* Set custom function for FIFO test */
-	i2c_common_emul_set_read_func(emul, emul_fifo_func, &func_data);
-	/* Enable sensor FIFO */
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-	/* Set range */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
-		      NULL);
-	/* Setup single accelerometer frame */
-	f[0].type = BMI_EMUL_FRAME_ACC;
-	f[0].acc_x = BMI_EMUL_1G / 10;
-	f[0].acc_y = BMI_EMUL_1G / 20;
-	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
-	f[0].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second accelerometer frame */
-	f[1].type = BMI_EMUL_FRAME_ACC;
-	f[1].acc_x = -(int)BMI_EMUL_1G / 40;
-	f[1].acc_y = BMI_EMUL_1G / 50;
-	f[1].acc_z = BMI_EMUL_1G / 60;
-	f[0].next = &(f[1]);
-	f[1].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Enable sensor FIFO */
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_data_rate(ms_gyr, 50000, 0),
-		      NULL);
-
-	/* Setup first gyroscope frame (after two accelerometer frames) */
-	f[2].type = BMI_EMUL_FRAME_GYR;
-	f[2].gyr_x = -(int)BMI_EMUL_125_DEG_S / 100;
-	f[2].gyr_y = BMI_EMUL_125_DEG_S / 200;
-	f[2].gyr_z = BMI_EMUL_125_DEG_S / 300;
-	f[1].next = &(f[2]);
-	f[2].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second accelerometer frame to by gyroscope frame too */
-	f[1].type |= BMI_EMUL_FRAME_GYR;
-	f[1].gyr_x = -(int)BMI_EMUL_125_DEG_S / 300;
-	f[1].gyr_y = BMI_EMUL_125_DEG_S / 400;
-	f[1].gyr_z = BMI_EMUL_125_DEG_S / 500;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Skip frame should be ignored by driver */
-	bmi_emul_set_skipped_frames(emul, 8);
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second frame as an config frame */
-	f[1].type = BMI_EMUL_FRAME_CONFIG;
-	/* Indicate that accelerometer range changed */
-	f[1].config = 0x1;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI160_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-}
-
-/** Test irq handler of gyroscope sensor */
-static void test_bmi_gyr_fifo(void)
-{
-	struct motion_sensor_t *ms;
-	uint32_t event;
-
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Interrupt shuldn't be triggered for gyroscope motion sense */
-	event = BMI_INT_EVENT;
-	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
-		      NULL);
-}
-
-void test_suite_bmi160(void)
-{
-	ztest_test_suite(bmi160,
-			 ztest_user_unit_test(test_bmi_acc_get_offset),
-			 ztest_user_unit_test(test_bmi_gyr_get_offset),
-			 ztest_user_unit_test(test_bmi_acc_set_offset),
-			 ztest_user_unit_test(test_bmi_gyr_set_offset),
-			 ztest_user_unit_test(test_bmi_acc_set_range),
-			 ztest_user_unit_test(test_bmi_gyr_set_range),
-			 ztest_user_unit_test(test_bmi_get_resolution),
-			 ztest_user_unit_test(test_bmi_acc_rate),
-			 ztest_user_unit_test(test_bmi_gyr_rate),
-			 ztest_user_unit_test(test_bmi_scale),
-			 ztest_user_unit_test(test_bmi_read_temp),
-			 ztest_user_unit_test(test_bmi_acc_read),
-			 ztest_user_unit_test(test_bmi_gyr_read),
-			 ztest_user_unit_test(test_bmi_acc_perform_calib),
-			 ztest_user_unit_test(test_bmi_gyr_perform_calib),
-			 ztest_user_unit_test(test_bmi_init),
-			 ztest_user_unit_test(test_bmi_acc_fifo),
-			 ztest_user_unit_test(test_bmi_gyr_fifo));
-	ztest_run_test_suite(bmi160);
-}
diff --git a/zephyr/test/drivers/src/bmi260.c b/zephyr/test/drivers/src/bmi260.c
deleted file mode 100644
index 637e5f353b..0000000000
--- a/zephyr/test/drivers/src/bmi260.c
+++ /dev/null
@@ -1,1864 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c.h"
-#include "emul/emul_bmi.h"
-#include "emul/emul_common_i2c.h"
-
-#include "motion_sense_fifo.h"
-#include "driver/accelgyro_bmi260.h"
-#include "driver/accelgyro_bmi_common.h"
-
-#define BMI_ORD			DT_DEP_ORD(DT_NODELABEL(accel_bmi260))
-#define BMI_ACC_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi260_accel))
-#define BMI_GYR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro))
-#define BMI_INT_EVENT		\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
-
-/** How accurate comparision of vectors should be */
-#define V_EPS		8
-
-/** Convert from one type of vector to another */
-#define convert_int3v_int16(v, r) do {	\
-		r[0] = v[0];		\
-		r[1] = v[1];		\
-		r[2] = v[2];		\
-	} while (0)
-
-/** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-/** Rotate given vector by test rotation */
-static void rotate_int3v_by_test_rotation(intv3_t v)
-{
-	int16_t t;
-
-	t = v[0];
-	v[0] = -v[1];
-	v[1] = t;
-	v[2] = -v[2];
-}
-
-/** Set emulator accelerometer offset values to intv3_t vector */
-static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, offset[2]);
-}
-
-/** Save emulator accelerometer offset values to intv3_t vector */
-static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
-	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
-	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Z);
-}
-
-/** Set emulator accelerometer values to intv3_t vector */
-static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
-{
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
-	bmi_emul_set_value(emul, BMI_EMUL_ACC_Z, acc[2]);
-}
-
-/** Set emulator gyroscope offset values to intv3_t vector */
-static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, offset[2]);
-}
-
-/** Save emulator gyroscope offset values to intv3_t vector */
-static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
-{
-	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
-	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
-	offset[2] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Z);
-}
-
-/** Set emulator gyroscope values to vector of three int16_t */
-static void set_emul_gyr(struct i2c_emul *emul, intv3_t gyr)
-{
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
-	bmi_emul_set_value(emul, BMI_EMUL_GYR_Z, gyr[2]);
-}
-
-/** Convert accelerometer read to units used by emulator */
-static void drv_acc_to_emul(intv3_t drv, int range, intv3_t out)
-{
-	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_1G;
-
-	out[0] = drv[0] * range / scale;
-	out[1] = drv[1] * range / scale;
-	out[2] = drv[2] * range / scale;
-}
-
-/** Convert gyroscope read to units used by emulator */
-static void drv_gyr_to_emul(intv3_t drv, int range, intv3_t out)
-{
-	const int scale = MOTION_SCALING_FACTOR / BMI_EMUL_125_DEG_S;
-
-	range /= 125;
-	out[0] = drv[0] * range / scale;
-	out[1] = drv[1] * range / scale;
-	out[2] = drv[2] * range / scale;
-}
-
-/** Compare two vectors of intv3_t type */
-static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
-{
-	int i;
-
-	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], eps,
-			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
-			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
-	}
-}
-#define compare_int3v_eps(exp_v, v, e) compare_int3v_f(exp_v, v, e, __LINE__)
-#define compare_int3v(exp_v, v) compare_int3v_eps(exp_v, v, V_EPS)
-
-/** Test get accelerometer offset with and without rotation */
-static void test_bmi_acc_get_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t ret[3];
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Set emulator offset */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	set_emul_acc_offset(emul, exp_v);
-	/* BMI driver returns value in mg units */
-	exp_v[0] = 1000 / 10;
-	exp_v[1] = 1000 / 20;
-	exp_v[2] = -1000 / 30;
-
-	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected offset */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-
-	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v(exp_v, ret_v);
-}
-
-/** Test get gyroscope offset with and without rotation */
-static void test_bmi_gyr_get_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t ret[3];
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set emulator offset */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	set_emul_gyr_offset(emul, exp_v);
-	/* BMI driver returns value in mdeg/s units */
-	exp_v[0] = 125000 / 100;
-	exp_v[1] = 125000 / 200;
-	exp_v[2] = -125000 / 300;
-
-	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-
-	/* Setup rotation and rotate expected offset */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-
-	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
-	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	convert_int3v_int16(ret, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-}
-
-/**
- * Test set accelerometer offset with and without rotation. Also test behaviour
- * on I2C error.
- */
-static void test_bmi_acc_set_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t input_v[3];
-	int16_t temp = 0;
-	intv3_t ret_v;
-	intv3_t exp_v;
-	uint8_t nv_c;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Test fail on NV CONF register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_NV_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_NV_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup NV_CONF register value */
-	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0x7);
-	/* Set input offset */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	/* BMI driver accept value in mg units */
-	input_v[0] = 1000 / 10;
-	input_v[1] = 1000 / 20;
-	input_v[2] = -1000 / 30;
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test set offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_acc_offset(emul, ret_v);
-	/*
-	 * Depending on used range, accelerometer values may be up to 6 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_v, ret_v, 64);
-	nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF);
-	/* Only ACC_OFFSET_EN bit should be changed */
-	zassert_equal(0x7 | BMI260_ACC_OFFSET_EN, nv_c,
-		      "Expected 0x%x, got 0x%x",
-		      0x7 | BMI260_ACC_OFFSET_EN, nv_c);
-
-	/* Setup NV_CONF register value */
-	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0);
-	/* Setup rotation and rotate input for set_offset function */
-	ms->rot_standard_ref = &test_rotation;
-	convert_int3v_int16(input_v, ret_v);
-	rotate_int3v_by_test_rotation(ret_v);
-	convert_int3v_int16(ret_v, input_v);
-
-	/* Test set offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_acc_offset(emul, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 64);
-	nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF);
-	/* Only ACC_OFFSET_EN bit should be changed */
-	zassert_equal(BMI260_ACC_OFFSET_EN, nv_c, "Expected 0x%x, got 0x%x",
-		      BMI260_ACC_OFFSET_EN, nv_c);
-}
-
-/**
- * Test set gyroscope offset with and without rotation. Also test behaviour
- * on I2C error.
- */
-static void test_bmi_gyr_set_offset(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t input_v[3];
-	int16_t temp = 0;
-	intv3_t ret_v;
-	intv3_t exp_v;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70 + 1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70 + 2);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Set input offset */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	/* BMI driver accept value in mdeg/s units */
-	input_v[0] = 125000 / 100;
-	input_v[1] = 125000 / 200;
-	input_v[2] = -125000 / 300;
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-
-	/* Test set offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_gyr_offset(emul, ret_v);
-	/*
-	 * Depending on used range, gyroscope values may be up to 4 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_v, ret_v, 32);
-	/* Gyroscope offset should be enabled */
-	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
-		     BMI260_OFFSET_GYRO_EN, NULL);
-
-	/* Setup rotation and rotate input for set_offset function */
-	ms->rot_standard_ref = &test_rotation;
-	convert_int3v_int16(input_v, ret_v);
-	rotate_int3v_by_test_rotation(ret_v);
-	convert_int3v_int16(ret_v, input_v);
-
-	/* Test set offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->set_offset(ms, input_v, temp), NULL);
-	get_emul_gyr_offset(emul, ret_v);
-	compare_int3v_eps(exp_v, ret_v, 32);
-	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
-		     BMI260_OFFSET_GYRO_EN, NULL);
-}
-
-/**
- * Try to set accelerometer range and check if expected range was set
- * in driver and in emulator.
- */
-static void check_set_acc_range_f(struct i2c_emul *emul,
-				  struct motion_sensor_t *ms, int range,
-				  int rnd, int exp_range, int line)
-{
-	uint8_t exp_range_reg;
-	uint8_t range_reg;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
-		      "set_range failed; line: %d", line);
-	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
-	range_reg = bmi_emul_get_reg(emul, BMI260_ACC_RANGE);
-
-	switch (exp_range) {
-	case 2:
-		exp_range_reg = BMI260_GSEL_2G;
-		break;
-	case 4:
-		exp_range_reg = BMI260_GSEL_4G;
-		break;
-	case 8:
-		exp_range_reg = BMI260_GSEL_8G;
-		break;
-	case 16:
-		exp_range_reg = BMI260_GSEL_16G;
-		break;
-	default:
-		/* Unknown expected range */
-		zassert_unreachable(
-			"Expected range %d not supported by device; line %d",
-			exp_range, line);
-		return;
-	}
-
-	zassert_equal(exp_range_reg, range_reg,
-		      "Expected range reg 0x%x, got 0x%x; line %d",
-		      exp_range_reg, range_reg, line);
-}
-#define check_set_acc_range(emul, ms, range, rnd, exp_range)	\
-	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
-
-/** Test set accelerometer range with and without I2C errors */
-static void test_bmi_acc_set_range(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int start_range;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Setup starting range, shouldn't be changed on error */
-	start_range = 2;
-	ms->current_range = start_range;
-	bmi_emul_set_reg(emul, BMI260_ACC_RANGE, BMI260_GSEL_2G);
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_ACC_RANGE);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting range with rounding down */
-	check_set_acc_range(emul, ms, 1, 0, 2);
-	check_set_acc_range(emul, ms, 2, 0, 2);
-	check_set_acc_range(emul, ms, 3, 0, 2);
-	check_set_acc_range(emul, ms, 4, 0, 4);
-	check_set_acc_range(emul, ms, 5, 0, 4);
-	check_set_acc_range(emul, ms, 6, 0, 4);
-	check_set_acc_range(emul, ms, 7, 0, 4);
-	check_set_acc_range(emul, ms, 8, 0, 8);
-	check_set_acc_range(emul, ms, 9, 0, 8);
-	check_set_acc_range(emul, ms, 15, 0, 8);
-	check_set_acc_range(emul, ms, 16, 0, 16);
-	check_set_acc_range(emul, ms, 17, 0, 16);
-
-	/* Test setting range with rounding up */
-	check_set_acc_range(emul, ms, 1, 1, 2);
-	check_set_acc_range(emul, ms, 2, 1, 2);
-	check_set_acc_range(emul, ms, 3, 1, 4);
-	check_set_acc_range(emul, ms, 4, 1, 4);
-	check_set_acc_range(emul, ms, 5, 1, 8);
-	check_set_acc_range(emul, ms, 6, 1, 8);
-	check_set_acc_range(emul, ms, 7, 1, 8);
-	check_set_acc_range(emul, ms, 8, 1, 8);
-	check_set_acc_range(emul, ms, 9, 1, 16);
-	check_set_acc_range(emul, ms, 15, 1, 16);
-	check_set_acc_range(emul, ms, 16, 1, 16);
-	check_set_acc_range(emul, ms, 17, 1, 16);
-}
-
-/**
- * Try to set gyroscope range and check if expected range was set in driver and
- * in emulator.
- */
-static void check_set_gyr_range_f(struct i2c_emul *emul,
-				  struct motion_sensor_t *ms, int range,
-				  int rnd, int exp_range, int line)
-{
-	uint8_t exp_range_reg;
-	uint8_t range_reg;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
-		      "set_range failed; line: %d", line);
-	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
-	range_reg = bmi_emul_get_reg(emul, BMI260_GYR_RANGE);
-
-	switch (exp_range) {
-	case 125:
-		exp_range_reg = BMI260_DPS_SEL_125;
-		break;
-	case 250:
-		exp_range_reg = BMI260_DPS_SEL_250;
-		break;
-	case 500:
-		exp_range_reg = BMI260_DPS_SEL_500;
-		break;
-	case 1000:
-		exp_range_reg = BMI260_DPS_SEL_1000;
-		break;
-	case 2000:
-		exp_range_reg = BMI260_DPS_SEL_2000;
-		break;
-	default:
-		/* Unknown expected range */
-		zassert_unreachable(
-			"Expected range %d not supported by device; line %d",
-			exp_range, line);
-		return;
-	}
-
-	zassert_equal(exp_range_reg, range_reg,
-		      "Expected range reg 0x%x, got 0x%x; line %d",
-		      exp_range_reg, range_reg, line);
-}
-#define check_set_gyr_range(emul, ms, range, rnd, exp_range)	\
-	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
-
-/** Test set gyroscope range with and without I2C errors */
-static void test_bmi_gyr_set_range(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int start_range;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Setup starting range, shouldn't be changed on error */
-	start_range = 250;
-	ms->current_range = start_range;
-	bmi_emul_set_reg(emul, BMI260_GYR_RANGE, BMI260_DPS_SEL_250);
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_GYR_RANGE);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_DPS_SEL_250,
-		      bmi_emul_get_reg(emul, BMI260_GYR_RANGE), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 1), NULL);
-	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_DPS_SEL_250,
-		      bmi_emul_get_reg(emul, BMI260_GYR_RANGE), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting range with rounding down */
-	check_set_gyr_range(emul, ms, 1, 0, 125);
-	check_set_gyr_range(emul, ms, 124, 0, 125);
-	check_set_gyr_range(emul, ms, 125, 0, 125);
-	check_set_gyr_range(emul, ms, 126, 0, 125);
-	check_set_gyr_range(emul, ms, 249, 0, 125);
-	check_set_gyr_range(emul, ms, 250, 0, 250);
-	check_set_gyr_range(emul, ms, 251, 0, 250);
-	check_set_gyr_range(emul, ms, 499, 0, 250);
-	check_set_gyr_range(emul, ms, 500, 0, 500);
-	check_set_gyr_range(emul, ms, 501, 0, 500);
-	check_set_gyr_range(emul, ms, 999, 0, 500);
-	check_set_gyr_range(emul, ms, 1000, 0, 1000);
-	check_set_gyr_range(emul, ms, 1001, 0, 1000);
-	check_set_gyr_range(emul, ms, 1999, 0, 1000);
-	check_set_gyr_range(emul, ms, 2000, 0, 2000);
-	check_set_gyr_range(emul, ms, 2001, 0, 2000);
-
-	/* Test setting range with rounding up */
-	check_set_gyr_range(emul, ms, 1, 1, 125);
-	check_set_gyr_range(emul, ms, 124, 1, 125);
-	check_set_gyr_range(emul, ms, 125, 1, 125);
-	check_set_gyr_range(emul, ms, 126, 1, 250);
-	check_set_gyr_range(emul, ms, 249, 1, 250);
-	check_set_gyr_range(emul, ms, 250, 1, 250);
-	check_set_gyr_range(emul, ms, 251, 1, 500);
-	check_set_gyr_range(emul, ms, 499, 1, 500);
-	check_set_gyr_range(emul, ms, 500, 1, 500);
-	check_set_gyr_range(emul, ms, 501, 1, 1000);
-	check_set_gyr_range(emul, ms, 999, 1, 1000);
-	check_set_gyr_range(emul, ms, 1000, 1, 1000);
-	check_set_gyr_range(emul, ms, 1001, 1, 2000);
-	check_set_gyr_range(emul, ms, 1999, 1, 2000);
-	check_set_gyr_range(emul, ms, 2000, 1, 2000);
-	check_set_gyr_range(emul, ms, 2001, 1, 2000);
-}
-
-/** Test get resolution of acclerometer and gyroscope sensor */
-static void test_bmi_get_resolution(void)
-{
-	struct motion_sensor_t *ms;
-
-	/* Test accelerometer */
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Resolution should be always 16 bits */
-	zassert_equal(16, ms->drv->get_resolution(ms), NULL);
-
-	/* Test gyroscope */
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Resolution should be always 16 bits */
-	zassert_equal(16, ms->drv->get_resolution(ms), NULL);
-}
-
-/**
- * Try to set accelerometer data rate and check if expected rate was set
- * in driver and in emulator.
- */
-static void check_set_acc_rate_f(struct i2c_emul *emul,
-				 struct motion_sensor_t *ms, int rate, int rnd,
-				 int exp_rate, int line)
-{
-	uint8_t exp_rate_reg;
-	uint8_t rate_reg;
-	int drv_rate;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
-		      "set_data_rate failed; line: %d", line);
-	drv_rate = ms->drv->get_data_rate(ms);
-	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
-		      exp_rate, drv_rate, line);
-	rate_reg = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
-	rate_reg &= BMI_ODR_MASK;
-
-	switch (exp_rate) {
-	case 12500:
-		exp_rate_reg = 0x5;
-		break;
-	case 25000:
-		exp_rate_reg = 0x6;
-		break;
-	case 50000:
-		exp_rate_reg = 0x7;
-		break;
-	case 100000:
-		exp_rate_reg = 0x8;
-		break;
-	case 200000:
-		exp_rate_reg = 0x9;
-		break;
-	case 400000:
-		exp_rate_reg = 0xa;
-		break;
-	case 800000:
-		exp_rate_reg = 0xb;
-		break;
-	case 1600000:
-		exp_rate_reg = 0xc;
-		break;
-	default:
-		/* Unknown expected rate */
-		zassert_unreachable(
-			"Expected rate %d not supported by device; line %d",
-			exp_rate, line);
-		return;
-	}
-
-	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
-}
-#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate)	\
-	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
-
-/** Test set and get accelerometer rate with and without I2C errors */
-static void test_bmi_acc_rate(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t reg_rate;
-	uint8_t pwr_ctrl;
-	int drv_rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Test setting rate with rounding down */
-	check_set_acc_rate(emul, ms, 12500, 0, 12500);
-	check_set_acc_rate(emul, ms, 12501, 0, 12500);
-	check_set_acc_rate(emul, ms, 24999, 0, 12500);
-	check_set_acc_rate(emul, ms, 25000, 0, 25000);
-	check_set_acc_rate(emul, ms, 25001, 0, 25000);
-	check_set_acc_rate(emul, ms, 49999, 0, 25000);
-	check_set_acc_rate(emul, ms, 50000, 0, 50000);
-	check_set_acc_rate(emul, ms, 50001, 0, 50000);
-	check_set_acc_rate(emul, ms, 99999, 0, 50000);
-	check_set_acc_rate(emul, ms, 100000, 0, 100000);
-	check_set_acc_rate(emul, ms, 100001, 0, 100000);
-	check_set_acc_rate(emul, ms, 199999, 0, 100000);
-	check_set_acc_rate(emul, ms, 200000, 0, 200000);
-	check_set_acc_rate(emul, ms, 200001, 0, 200000);
-	check_set_acc_rate(emul, ms, 399999, 0, 200000);
-	/*
-	 * We cannot test frequencies from 400000 to 1600000 because
-	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
-	 */
-
-	/* Test setting rate with rounding up */
-	check_set_acc_rate(emul, ms, 6251, 1, 12500);
-	check_set_acc_rate(emul, ms, 12499, 1, 12500);
-	check_set_acc_rate(emul, ms, 12500, 1, 12500);
-	check_set_acc_rate(emul, ms, 12501, 1, 25000);
-	check_set_acc_rate(emul, ms, 24999, 1, 25000);
-	check_set_acc_rate(emul, ms, 25000, 1, 25000);
-	check_set_acc_rate(emul, ms, 25001, 1, 50000);
-	check_set_acc_rate(emul, ms, 49999, 1, 50000);
-	check_set_acc_rate(emul, ms, 50000, 1, 50000);
-	check_set_acc_rate(emul, ms, 50001, 1, 100000);
-	check_set_acc_rate(emul, ms, 99999, 1, 100000);
-	check_set_acc_rate(emul, ms, 100000, 1, 100000);
-	check_set_acc_rate(emul, ms, 100001, 1, 200000);
-	check_set_acc_rate(emul, ms, 199999, 1, 200000);
-	check_set_acc_rate(emul, ms, 200000, 1, 200000);
-
-	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
-
-	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 6250, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 2000000, 1), NULL);
-
-	/* Current rate shouldn't be changed on error */
-	drv_rate = ms->drv->get_data_rate(ms);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_CONF);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_ACC_CONF);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test disabling sensor */
-	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
-			 BMI260_AUX_EN | BMI260_GYR_EN | BMI260_ACC_EN);
-	bmi_emul_set_reg(emul, BMI260_ACC_CONF, BMI260_FILTER_PERF);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
-
-	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
-	zassert_equal(BMI260_AUX_EN | BMI260_GYR_EN, pwr_ctrl, NULL);
-	zassert_true(!(reg_rate & BMI260_FILTER_PERF), NULL);
-
-	/* Test enabling sensor */
-	bmi_emul_set_reg(emul, BMI260_PWR_CTRL, 0);
-	bmi_emul_set_reg(emul, BMI260_ACC_CONF, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-
-	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
-	zassert_equal(BMI260_ACC_EN, pwr_ctrl, NULL);
-	zassert_true(reg_rate & BMI260_FILTER_PERF, NULL);
-}
-
-/**
- * Try to set gyroscope data rate and check if expected rate was set
- * in driver and in emulator.
- */
-static void check_set_gyr_rate_f(struct i2c_emul *emul,
-				 struct motion_sensor_t *ms, int rate, int rnd,
-				 int exp_rate, int line)
-{
-	uint8_t exp_rate_reg;
-	uint8_t rate_reg;
-	int drv_rate;
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, rnd),
-		      "set_data_rate failed; line: %d", line);
-	drv_rate = ms->drv->get_data_rate(ms);
-	zassert_equal(exp_rate, drv_rate, "Expected rate %d, got %d; line %d",
-		      exp_rate, drv_rate, line);
-	rate_reg = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
-	rate_reg &= BMI_ODR_MASK;
-
-	switch (exp_rate) {
-	case 25000:
-		exp_rate_reg = 0x6;
-		break;
-	case 50000:
-		exp_rate_reg = 0x7;
-		break;
-	case 100000:
-		exp_rate_reg = 0x8;
-		break;
-	case 200000:
-		exp_rate_reg = 0x9;
-		break;
-	case 400000:
-		exp_rate_reg = 0xa;
-		break;
-	case 800000:
-		exp_rate_reg = 0xb;
-		break;
-	case 1600000:
-		exp_rate_reg = 0xc;
-		break;
-	case 3200000:
-		exp_rate_reg = 0xc;
-		break;
-	default:
-		/* Unknown expected rate */
-		zassert_unreachable(
-			"Expected rate %d not supported by device; line %d",
-			exp_rate, line);
-		return;
-	}
-
-	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
-}
-#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate)	\
-	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
-
-/** Test set and get gyroscope rate with and without I2C errors */
-static void test_bmi_gyr_rate(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t reg_rate;
-	uint8_t pwr_ctrl;
-	int drv_rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Test setting rate with rounding down */
-	check_set_gyr_rate(emul, ms, 25000, 0, 25000);
-	check_set_gyr_rate(emul, ms, 25001, 0, 25000);
-	check_set_gyr_rate(emul, ms, 49999, 0, 25000);
-	check_set_gyr_rate(emul, ms, 50000, 0, 50000);
-	check_set_gyr_rate(emul, ms, 50001, 0, 50000);
-	check_set_gyr_rate(emul, ms, 99999, 0, 50000);
-	check_set_gyr_rate(emul, ms, 100000, 0, 100000);
-	check_set_gyr_rate(emul, ms, 100001, 0, 100000);
-	check_set_gyr_rate(emul, ms, 199999, 0, 100000);
-	check_set_gyr_rate(emul, ms, 200000, 0, 200000);
-	check_set_gyr_rate(emul, ms, 200001, 0, 200000);
-	check_set_gyr_rate(emul, ms, 399999, 0, 200000);
-	/*
-	 * We cannot test frequencies from 400000 to 3200000 because
-	 * CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ is set to 250000
-	 */
-
-	/* Test setting rate with rounding up */
-	check_set_gyr_rate(emul, ms, 12501, 1, 25000);
-	check_set_gyr_rate(emul, ms, 24999, 1, 25000);
-	check_set_gyr_rate(emul, ms, 25000, 1, 25000);
-	check_set_gyr_rate(emul, ms, 25001, 1, 50000);
-	check_set_gyr_rate(emul, ms, 49999, 1, 50000);
-	check_set_gyr_rate(emul, ms, 50000, 1, 50000);
-	check_set_gyr_rate(emul, ms, 50001, 1, 100000);
-	check_set_gyr_rate(emul, ms, 99999, 1, 100000);
-	check_set_gyr_rate(emul, ms, 100000, 1, 100000);
-	check_set_gyr_rate(emul, ms, 100001, 1, 200000);
-	check_set_gyr_rate(emul, ms, 199999, 1, 200000);
-	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
-
-	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 0), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
-
-	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 400000, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 4000000, 1), NULL);
-
-	/* Current rate shouldn't be changed on error */
-	drv_rate = ms->drv->get_data_rate(ms);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_CONF);
-
-	/* Test fail on read */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
-
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_GYR_CONF);
-
-	/* Test fail on write */
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 1),
-		      NULL);
-	zassert_equal(drv_rate, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
-
-	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test disabling sensor */
-	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
-			 BMI260_AUX_EN | BMI260_GYR_EN | BMI260_ACC_EN);
-	bmi_emul_set_reg(emul, BMI260_GYR_CONF,
-			 BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
-
-	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
-	zassert_equal(BMI260_AUX_EN | BMI260_ACC_EN, pwr_ctrl, NULL);
-	zassert_true(!(reg_rate & (BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF)),
-		     NULL);
-
-	/* Test enabling sensor */
-	bmi_emul_set_reg(emul, BMI260_PWR_CTRL, 0);
-	bmi_emul_set_reg(emul, BMI260_GYR_CONF, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-
-	pwr_ctrl = bmi_emul_get_reg(emul, BMI260_PWR_CTRL);
-	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
-	zassert_equal(BMI260_GYR_EN, pwr_ctrl, NULL);
-	zassert_true(reg_rate & (BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF),
-		     NULL);
-}
-
-/**
- * Test setting and getting scale in accelerometer and gyroscope sensors.
- * Correct appling scale to results is checked in "read" test.
- */
-static void test_bmi_scale(void)
-{
-	struct motion_sensor_t *ms;
-	int16_t ret_scale[3];
-	int16_t exp_scale[3] = {100, 231, 421};
-	int16_t t;
-
-	/* Test accelerometer */
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t), NULL);
-
-	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	zassert_equal(exp_scale[0], ret_scale[0], NULL);
-	zassert_equal(exp_scale[1], ret_scale[1], NULL);
-	zassert_equal(exp_scale[2], ret_scale[2], NULL);
-
-	/* Test gyroscope */
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, ret_scale, &t), NULL);
-
-	zassert_equal(t, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
-	zassert_equal(exp_scale[0], ret_scale[0], NULL);
-	zassert_equal(exp_scale[1], ret_scale[1], NULL);
-	zassert_equal(exp_scale[2], ret_scale[2], NULL);
-}
-
-/** Test reading temperature using accelerometer and gyroscope sensors */
-static void test_bmi_read_temp(void)
-{
-	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
-	int ret_temp;
-	int exp_temp;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_TEMPERATURE_0);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_TEMPERATURE_1);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Fail on invalid temperature */
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x80);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-
-	/*
-	 * Test correct values. Both motion sensors should return the same
-	 * temperature.
-	 */
-	exp_temp = C_TO_K(23);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x00);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(87);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0xff);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x7f);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(-41);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x01);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x80);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-
-	exp_temp = C_TO_K(47);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
-	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_1, 0x30);
-	zassert_equal(EC_SUCCESS, ms_acc->drv->read_temp(ms_acc, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->read_temp(ms_gyr, &ret_temp),
-		      NULL);
-	zassert_equal(exp_temp, ret_temp, NULL);
-}
-
-/** Test reading accelerometer sensor data */
-static void test_bmi_acc_read(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Set offset 0 to simplify test */
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
-
-	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* When not ready, driver should return saved raw value */
-	exp_v[0] = 100;
-	exp_v[1] = 200;
-	exp_v[2] = 300;
-	ms->raw_xyz[0] = exp_v[0];
-	ms->raw_xyz[1] = exp_v[1];
-	ms->raw_xyz[2] = exp_v[2];
-
-	/* Status not ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status only GYR ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_GYR);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status ACC ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
-
-	/* Set input accelerometer values */
-	exp_v[0] = BMI_EMUL_1G / 10;
-	exp_v[1] = BMI_EMUL_1G / 20;
-	exp_v[2] = -(int)BMI_EMUL_1G / 30;
-	set_emul_acc(emul, exp_v);
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-	/* Set scale */
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0), NULL);
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 2, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 4, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected vector */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-	/* Set range to 2G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 2, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 2, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 4G */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 4, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_acc_to_emul(ret_v, 4, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Y_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Y_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Z_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Z_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	ms->rot_standard_ref = NULL;
-}
-
-/** Test reading gyroscope sensor data */
-static void test_bmi_gyr_read(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t ret_v;
-	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Set offset 0 to simplify test */
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, 0);
-	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
-
-	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* When not ready, driver should return saved raw value */
-	exp_v[0] = 100;
-	exp_v[1] = 200;
-	exp_v[2] = 300;
-	ms->raw_xyz[0] = exp_v[0];
-	ms->raw_xyz[1] = exp_v[1];
-	ms->raw_xyz[2] = exp_v[2];
-
-	/* Status not ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status only ACC ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	compare_int3v(exp_v, ret_v);
-
-	/* Status GYR ready */
-	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_GYR);
-
-	/* Set input accelerometer values */
-	exp_v[0] = BMI_EMUL_125_DEG_S / 10;
-	exp_v[1] = BMI_EMUL_125_DEG_S / 20;
-	exp_v[2] = -(int)BMI_EMUL_125_DEG_S / 30;
-	set_emul_gyr(emul, exp_v);
-	/* Disable rotation */
-	ms->rot_standard_ref = NULL;
-	/* Set scale */
-	zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, scale, 0), NULL);
-	/* Set range to 125°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 125, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 1000°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0), NULL);
-
-	/* Test read without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 1000, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Setup rotation and rotate expected vector */
-	ms->rot_standard_ref = &test_rotation;
-	rotate_int3v_by_test_rotation(exp_v);
-	/* Set range to 125°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 125, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 125, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Set range to 1000°/s */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 1000, 0), NULL);
-
-	/* Test read with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->read(ms, ret_v), NULL);
-	drv_gyr_to_emul(ret_v, 1000, ret_v);
-	compare_int3v(exp_v, ret_v);
-
-	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Y_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Y_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Z_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Z_H_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	ms->rot_standard_ref = NULL;
-}
-
-/** Test acceleromtere calibration */
-static void test_bmi_acc_perform_calib(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t start_off;
-	intv3_t exp_off;
-	intv3_t ret_off;
-	int range;
-	int rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-
-	/* Range and rate cannot change after calibration */
-	range = 4;
-	rate = 50000;
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0), NULL);
-
-	/* Set offset 0 */
-	start_off[0] = 0;
-	start_off[1] = 0;
-	start_off[2] = 0;
-	set_emul_acc_offset(emul, start_off);
-
-	/* Set input accelerometer values */
-	exp_off[0] = BMI_EMUL_1G / 10;
-	exp_off[1] = BMI_EMUL_1G / 20;
-	exp_off[2] = BMI_EMUL_1G - (int)BMI_EMUL_1G / 30;
-	set_emul_acc(emul, exp_off);
-
-	/* Expected offset is [-X, -Y, 1G - Z] */
-	exp_off[0] = -exp_off[0];
-	exp_off[1] = -exp_off[1];
-	exp_off[2] = BMI_EMUL_1G - exp_off[2];
-
-	/* Test success on disabling calibration */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on rate read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
-	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Setup data status ready for rest of the test */
-	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
-
-	/* Test fail on data read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on setting offset */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_NV_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test successful offset compenastion */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_acc_offset(emul, ret_off);
-	/*
-	 * Depending on used range, accelerometer values may be up to 6 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_off, ret_off, 64);
-}
-
-/** Test gyroscope calibration */
-static void test_bmi_gyr_perform_calib(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	intv3_t start_off;
-	intv3_t exp_off;
-	intv3_t ret_off;
-	int range;
-	int rate;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Range and rate cannot change after calibration */
-	range = 125;
-	rate = 50000;
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, rate, 0), NULL);
-
-	/* Set offset 0 */
-	start_off[0] = 0;
-	start_off[1] = 0;
-	start_off[2] = 0;
-	set_emul_gyr_offset(emul, start_off);
-
-	/* Set input accelerometer values */
-	exp_off[0] = BMI_EMUL_125_DEG_S / 100;
-	exp_off[1] = BMI_EMUL_125_DEG_S / 200;
-	exp_off[2] = -(int)BMI_EMUL_125_DEG_S / 300;
-	set_emul_gyr(emul, exp_off);
-
-	/* Expected offset is [-X, -Y, -Z] */
-	exp_off[0] = -exp_off[0];
-	exp_off[1] = -exp_off[1];
-	exp_off[2] = -exp_off[2];
-
-	/* Test success on disabling calibration */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on rate read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_CONF);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
-	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/*
-	 * Setup data status ready for rest of the test. Gyroscope calibration
-	 * should check DRDY_GYR bit, but current driver check only for ACC.
-	 */
-	bmi_emul_set_reg(emul, BMI260_STATUS,
-			 BMI260_DRDY_ACC | BMI260_DRDY_GYR);
-
-	/* Test fail on data read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_L_G);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	/* Test fail on setting offset */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test successful offset compenastion */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(range, ms->current_range, NULL);
-	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
-	get_emul_gyr_offset(emul, ret_off);
-	/*
-	 * Depending on used range, gyroscope values may be up to 4 bits
-	 * more accurate then offset value resolution.
-	 */
-	compare_int3v_eps(exp_off, ret_off, 32);
-}
-
-/**
- * Custom emulatro read function which always return INIT OK status in
- * INTERNAL STATUS register. Used in init test.
- */
-static int emul_init_ok(struct i2c_emul *emul, int reg, uint8_t *val, int byte,
-			void *data)
-{
-	bmi_emul_set_reg(emul, BMI260_INTERNAL_STATUS, BMI260_INIT_OK);
-
-	return 1;
-}
-
-/** Test init function of BMI260 accelerometer and gyroscope sensors */
-static void test_bmi_init(void)
-{
-	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/*
-	 * Test successful init. It is needed custom function to set value of
-	 * BMI260_INTERNAL_STATUS register, because init function triggers reset
-	 * which clears value set in this register before test.
-	 */
-	i2c_common_emul_set_read_func(emul, emul_init_ok, NULL);
-	zassert_equal(EC_RES_SUCCESS, ms_acc->drv->init(ms_acc), NULL);
-
-	zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr), NULL);
-
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-}
-
-/** Data for custom emulator read function used in FIFO test */
-struct fifo_func_data {
-	uint16_t interrupts;
-};
-
-/**
- * Custom emulator read function used in FIFO test. It sets interrupt registers
- * to value passed as additional data. It sets interrupt registers to 0 after
- * access.
- */
-static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
-			  int byte, void *data)
-{
-	struct fifo_func_data *d = data;
-
-	if (reg + byte == BMI260_INT_STATUS_0) {
-		bmi_emul_set_reg(emul, BMI260_INT_STATUS_0,
-				 d->interrupts & 0xff);
-		d->interrupts &= 0xff00;
-	} else if (reg + byte == BMI260_INT_STATUS_1) {
-		bmi_emul_set_reg(emul, BMI260_INT_STATUS_1,
-				 (d->interrupts >> 8) & 0xff);
-		d->interrupts &= 0xff;
-	}
-
-	return 1;
-}
-
-/**
- * Run irq handler on accelerometer sensor and check if committed data in FIFO
- * match what was set in FIFO frames in emulator.
- */
-static void check_fifo_f(struct motion_sensor_t *ms_acc,
-			 struct motion_sensor_t *ms_gyr,
-			 struct bmi_emul_frame *frame,
-			 int acc_range, int gyr_range,
-			 int line)
-{
-	struct ec_response_motion_sensor_data vector;
-	struct bmi_emul_frame *f_acc, *f_gyr;
-	uint32_t event = BMI_INT_EVENT;
-	uint16_t size;
-	intv3_t exp_v;
-	intv3_t ret_v;
-
-	/* Find first frame of acc and gyr type */
-	f_acc = frame;
-	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
-		f_acc = f_acc->next;
-	}
-
-	f_gyr = frame;
-	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
-		f_gyr = f_gyr->next;
-	}
-
-	/* Read FIFO in driver */
-	zassert_equal(EC_SUCCESS, ms_acc->drv->irq_handler(ms_acc, &event),
-		      NULL);
-
-	/* Read all data committed to FIFO */
-	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
-		/* Ignore timestamp frames */
-		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
-			continue;
-		}
-
-		/* Check acclerometer frames */
-		if (ms_acc - motion_sensors == vector.sensor_num) {
-			if (f_acc == NULL) {
-				zassert_unreachable(
-					"Not expected acclerometer data in FIFO, line %d",
-					line);
-			}
-
-			convert_int3v_int16(vector.data, ret_v);
-			drv_acc_to_emul(ret_v, acc_range, ret_v);
-			exp_v[0] = f_acc->acc_x;
-			exp_v[1] = f_acc->acc_y;
-			exp_v[2] = f_acc->acc_z;
-			compare_int3v_f(exp_v, ret_v, V_EPS, line);
-			f_acc = f_acc->next;
-		}
-
-		/* Check gyroscope frames */
-		if (ms_gyr - motion_sensors == vector.sensor_num) {
-			if (f_gyr == NULL) {
-				zassert_unreachable(
-					"Not expected gyroscope data in FIFO, line %d",
-					line);
-			}
-
-			convert_int3v_int16(vector.data, ret_v);
-			drv_gyr_to_emul(ret_v, gyr_range, ret_v);
-			exp_v[0] = f_gyr->gyr_x;
-			exp_v[1] = f_gyr->gyr_y;
-			exp_v[2] = f_gyr->gyr_z;
-			compare_int3v_f(exp_v, ret_v, V_EPS, line);
-			f_gyr = f_gyr->next;
-		}
-	}
-
-	/* Skip frames of different type at the end */
-	while (f_acc != NULL && !(f_acc->type & BMI_EMUL_FRAME_ACC)) {
-		f_acc = f_acc->next;
-	}
-
-	while (f_gyr != NULL && !(f_gyr->type & BMI_EMUL_FRAME_GYR)) {
-		f_gyr = f_gyr->next;
-	}
-
-	/* All frames are readed */
-	zassert_is_null(f_acc, "Not all accelerometer frames are read, line %d",
-			line);
-	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
-			line);
-}
-#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range)		\
-	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
-
-/** Test irq handler of accelerometer sensor */
-static void test_bmi_acc_fifo(void)
-{
-	struct motion_sensor_t *ms, *ms_gyr;
-	struct fifo_func_data func_data;
-	struct bmi_emul_frame f[3];
-	struct i2c_emul *emul;
-	int gyr_range = 125;
-	int acc_range = 2;
-	int event;
-
-	emul = bmi_emul_get(BMI_ORD);
-	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Need to be set to collect all data in FIFO */
-	ms->oversampling_ratio = 1;
-	ms_gyr->oversampling_ratio = 1;
-	/* Only BMI event should be handled */
-	event = 0x1234 & ~BMI_INT_EVENT;
-	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
-		      NULL);
-
-	event = BMI_INT_EVENT;
-
-	/* Test fail to read interrupt status registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_INT_STATUS_0);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_INT_STATUS_1);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test no interrupt */
-	bmi_emul_set_reg(emul, BMI260_INT_STATUS_0, 0);
-	bmi_emul_set_reg(emul, BMI260_INT_STATUS_1, 0);
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
-
-	/* Set custom function for FIFO test */
-	i2c_common_emul_set_read_func(emul, emul_fifo_func, &func_data);
-	/* Enable sensor FIFO */
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 50000, 0), NULL);
-	/* Set range */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0), NULL);
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
-		      NULL);
-	/* Setup single accelerometer frame */
-	f[0].type = BMI_EMUL_FRAME_ACC;
-	f[0].acc_x = BMI_EMUL_1G / 10;
-	f[0].acc_y = BMI_EMUL_1G / 20;
-	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
-	f[0].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second accelerometer frame */
-	f[1].type = BMI_EMUL_FRAME_ACC;
-	f[1].acc_x = -(int)BMI_EMUL_1G / 40;
-	f[1].acc_y = BMI_EMUL_1G / 50;
-	f[1].acc_z = BMI_EMUL_1G / 60;
-	f[0].next = &(f[1]);
-	f[1].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Enable sensor FIFO */
-	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_data_rate(ms_gyr, 50000, 0),
-		      NULL);
-
-	/* Setup first gyroscope frame (after two accelerometer frames) */
-	f[2].type = BMI_EMUL_FRAME_GYR;
-	f[2].gyr_x = -(int)BMI_EMUL_125_DEG_S / 100;
-	f[2].gyr_y = BMI_EMUL_125_DEG_S / 200;
-	f[2].gyr_z = BMI_EMUL_125_DEG_S / 300;
-	f[1].next = &(f[2]);
-	f[2].next = NULL;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second accelerometer frame to by gyroscope frame too */
-	f[1].type |= BMI_EMUL_FRAME_GYR;
-	f[1].gyr_x = -(int)BMI_EMUL_125_DEG_S / 300;
-	f[1].gyr_y = BMI_EMUL_125_DEG_S / 400;
-	f[1].gyr_z = BMI_EMUL_125_DEG_S / 500;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Skip frame should be ignored by driver */
-	bmi_emul_set_skipped_frames(emul, 8);
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Setup second frame as an config frame */
-	f[1].type = BMI_EMUL_FRAME_CONFIG;
-	/* Indicate that accelerometer range changed */
-	f[1].config = 0x1;
-	bmi_emul_append_frame(emul, f);
-	/* Setup interrupts register */
-	func_data.interrupts = BMI260_FWM_INT;
-
-	/* Trigger irq handler and check results */
-	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
-
-	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-}
-
-/** Test irq handler of gyroscope sensor */
-static void test_bmi_gyr_fifo(void)
-{
-	struct motion_sensor_t *ms;
-	uint32_t event;
-
-	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
-
-	/* Interrupt shuldn't be triggered for gyroscope motion sense */
-	event = BMI_INT_EVENT;
-	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
-		      NULL);
-}
-
-void test_suite_bmi260(void)
-{
-	ztest_test_suite(bmi260,
-			 ztest_user_unit_test(test_bmi_acc_get_offset),
-			 ztest_user_unit_test(test_bmi_gyr_get_offset),
-			 ztest_user_unit_test(test_bmi_acc_set_offset),
-			 ztest_user_unit_test(test_bmi_gyr_set_offset),
-			 ztest_user_unit_test(test_bmi_acc_set_range),
-			 ztest_user_unit_test(test_bmi_gyr_set_range),
-			 ztest_user_unit_test(test_bmi_get_resolution),
-			 ztest_user_unit_test(test_bmi_acc_rate),
-			 ztest_user_unit_test(test_bmi_gyr_rate),
-			 ztest_user_unit_test(test_bmi_scale),
-			 ztest_user_unit_test(test_bmi_read_temp),
-			 ztest_user_unit_test(test_bmi_acc_read),
-			 ztest_user_unit_test(test_bmi_gyr_read),
-			 ztest_user_unit_test(test_bmi_acc_perform_calib),
-			 ztest_user_unit_test(test_bmi_gyr_perform_calib),
-			 ztest_user_unit_test(test_bmi_init),
-			 ztest_user_unit_test(test_bmi_acc_fifo),
-			 ztest_user_unit_test(test_bmi_gyr_fifo));
-	ztest_run_test_suite(bmi260);
-}
diff --git a/zephyr/test/drivers/src/espi.c b/zephyr/test/drivers/src/espi.c
deleted file mode 100644
index c852f1b771..0000000000
--- a/zephyr/test/drivers/src/espi.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "ec_commands.h"
-#include "host_command.h"
-
-static void test_host_command_get_protocol_info(void)
-{
-	struct ec_response_get_protocol_info response;
-	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, 0, response);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(args.response_size, sizeof(response), NULL);
-	zassert_equal(response.protocol_versions, BIT(3), NULL);
-	zassert_equal(response.max_request_packet_size, EC_LPC_HOST_PACKET_SIZE,
-		      NULL);
-	zassert_equal(response.max_response_packet_size,
-		      EC_LPC_HOST_PACKET_SIZE, NULL);
-	zassert_equal(response.flags, 0, NULL);
-}
-
-void test_suite_espi(void)
-{
-	ztest_test_suite(espi,
-			 ztest_user_unit_test(
-				 test_host_command_get_protocol_info));
-	ztest_run_test_suite(espi);
-}
diff --git a/zephyr/test/drivers/src/lis2dw12.c b/zephyr/test/drivers/src/lis2dw12.c
deleted file mode 100644
index 287430e65b..0000000000
--- a/zephyr/test/drivers/src/lis2dw12.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ztest.h>
-#include <drivers/emul.h>
-#include "driver/accel_lis2dw12.h"
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_lis2dw12.h"
-
-#define LIS2DW12_NODELABEL DT_NODELABEL(ms_lis2dw12_accel)
-#define LIS2DW12_SENSOR_ID SENSOR_ID(LIS2DW12_NODELABEL)
-#define EMUL_LABEL DT_LABEL(DT_NODELABEL(lis2dw12_emul))
-
-#include <stdio.h>
-static void lis2dw12_setup(void)
-{
-	lis2dw12_emul_reset(emul_get_binding(EMUL_LABEL));
-}
-
-static void test_lis2dw12_init__fail_read_who_am_i(void)
-{
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
-	int rv;
-
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_WHO_AM_I_REG);
-	rv = ms->drv->init(ms);
-	zassert_equal(EC_ERROR_INVAL, rv, NULL);
-}
-
-static void test_lis2dw12_init__fail_who_am_i(void)
-{
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
-	int rv;
-
-	lis2dw12_emul_set_who_am_i(emul, ~LIS2DW12_WHO_AM_I);
-
-	rv = ms->drv->init(ms);
-	zassert_equal(EC_ERROR_ACCESS_DENIED, rv,
-		      "init returned %d but was expecting %d", rv,
-		      EC_ERROR_ACCESS_DENIED);
-}
-
-static void test_lis2dw12_init__fail_write_soft_reset(void)
-{
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
-	int rv;
-
-	i2c_common_emul_set_write_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					   LIS2DW12_SOFT_RESET_ADDR);
-	rv = ms->drv->init(ms);
-	zassert_equal(EC_ERROR_INVAL, rv, NULL);
-}
-
-static void test_lis2dw12_init__timeout_read_soft_reset(void)
-{
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
-	int rv;
-
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_SOFT_RESET_ADDR);
-	rv = ms->drv->init(ms);
-	zassert_equal(EC_ERROR_TIMEOUT, rv, "init returned %d but expected %d",
-		      rv, EC_ERROR_TIMEOUT);
-}
-
-static int lis2dw12_test_mock_write_fail_set_bdu(struct i2c_emul *emul, int reg,
-						uint8_t val, int bytes,
-						void *data)
-{
-	if (reg == LIS2DW12_BDU_ADDR && bytes == 1 &&
-	    (val & LIS2DW12_BDU_MASK) != 0) {
-		return -EIO;
-	}
-	return 1;
-}
-
-static void test_lis2dw12_init__fail_set_bdu(void)
-{
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
-	int rv;
-
-	i2c_common_emul_set_write_func(lis2dw12_emul_to_i2c_emul(emul),
-				      lis2dw12_test_mock_write_fail_set_bdu,
-				      NULL);
-	rv = ms->drv->init(ms);
-	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
-		      rv, EC_ERROR_INVAL);
-	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
-		      "expected at least one soft reset");
-}
-
-void test_suite_lis2dw12(void)
-{
-	ztest_test_suite(lis2dw12,
-			 ztest_unit_test_setup_teardown(
-				 test_lis2dw12_init__fail_read_who_am_i,
-				 lis2dw12_setup, unit_test_noop),
-			 ztest_unit_test_setup_teardown(
-				 test_lis2dw12_init__fail_who_am_i,
-				 lis2dw12_setup, unit_test_noop),
-			 ztest_unit_test_setup_teardown(
-				 test_lis2dw12_init__fail_write_soft_reset,
-				 lis2dw12_setup, unit_test_noop),
-			 ztest_unit_test_setup_teardown(
-				 test_lis2dw12_init__timeout_read_soft_reset,
-				 lis2dw12_setup, unit_test_noop),
-			 ztest_unit_test_setup_teardown(
-				 test_lis2dw12_init__fail_set_bdu,
-				 lis2dw12_setup, unit_test_noop));
-	ztest_run_test_suite(lis2dw12);
-}
diff --git a/zephyr/test/drivers/src/ln9310.c b/zephyr/test/drivers/src/ln9310.c
deleted file mode 100644
index 0033931039..0000000000
--- a/zephyr/test/drivers/src/ln9310.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ztest.h>
-#include <drivers/emul.h>
-#include "driver/ln9310.h"
-#include "emul/emul_ln9310.h"
-
-void test_ln9310_2s_no_startup__passes_init(void)
-{
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-
-	zassert_not_null(emulator, NULL);
-
-	ln9310_emul_set_context(emulator);
-	ln9310_emul_reset(emulator);
-	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
-	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
-
-	zassert_ok(ln9310_init(), NULL);
-	zassert_true(ln9310_emul_is_init(emulator), NULL);
-}
-
-void test_ln9310_3s_no_startup__passes_init(void)
-{
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-
-	zassert_not_null(emulator, NULL);
-
-	ln9310_emul_set_context(emulator);
-	ln9310_emul_reset(emulator);
-	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_3S);
-	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
-
-	zassert_ok(ln9310_init(), NULL);
-	zassert_true(ln9310_emul_is_init(emulator), NULL);
-}
-
-void test_suite_ln9310(void)
-{
-	ztest_test_suite(
-		ln9310,
-		ztest_unit_test(test_ln9310_2s_no_startup__passes_init),
-		ztest_unit_test(test_ln9310_3s_no_startup__passes_init));
-	ztest_run_test_suite(ln9310);
-}
diff --git a/zephyr/test/drivers/src/main.c b/zephyr/test/drivers/src/main.c
deleted file mode 100644
index 8d40bc4373..0000000000
--- a/zephyr/test/drivers/src/main.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include "ec_app_main.h"
-
-extern void test_suite_battery(void);
-extern void test_suite_cbi(void);
-extern void test_suite_smart_battery(void);
-extern void test_suite_thermistor(void);
-extern void test_suite_temp_sensor(void);
-extern void test_suite_bma2x2(void);
-extern void test_suite_bc12(void);
-extern void test_suite_ppc(void);
-extern void test_suite_bmi260(void);
-extern void test_suite_bmi160(void);
-extern void test_suite_tcs3400(void);
-extern void test_suite_espi(void);
-extern void test_suite_bb_retimer(void);
-extern void test_suite_ln9310(void);
-extern void test_suite_lis2dw12(void);
-extern void test_suite_stm_mems_common(void);
-
-void test_main(void)
-{
-	/* Test suites to run before ec_app_main.*/
-
-	ec_app_main();
-
-	/* Test suites to run after ec_app_main.*/
-	test_suite_battery();
-	test_suite_cbi();
-	test_suite_smart_battery();
-	test_suite_thermistor();
-	test_suite_temp_sensor();
-	test_suite_bma2x2();
-	test_suite_bc12();
-	test_suite_ppc();
-	test_suite_bmi260();
-	test_suite_bmi160();
-	test_suite_tcs3400();
-	test_suite_espi();
-	test_suite_bb_retimer();
-	test_suite_ln9310();
-	test_suite_lis2dw12();
-	test_suite_stm_mems_common();
-}
diff --git a/zephyr/test/drivers/src/ppc.c b/zephyr/test/drivers/src/ppc.c
deleted file mode 100644
index dced25c227..0000000000
--- a/zephyr/test/drivers/src/ppc.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <ztest_assert.h>
-
-#include "emul/emul_syv682x.h"
-
-#include "stubs.h"
-#include "syv682x.h"
-#include "timer.h"
-#include "usbc_ppc.h"
-
-#define SYV682X_ORD DT_DEP_ORD(DT_NODELABEL(syv682x_emul))
-
-static const int syv682x_port = 1;
-
-static void test_ppc_syv682x_vbus_enable(void)
-{
-	struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD);
-	uint8_t reg;
-
-	zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, &reg),
-			"Reading CONTROL_1 failed");
-	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB,
-			SYV682X_CONTROL_1_PWR_ENB, "VBUS sourcing disabled");
-	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
-			"PPC sourcing VBUS at beginning of test");
-
-	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
-			"VBUS enable failed");
-	zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, &reg),
-			"Reading CONTROL_1 failed");
-	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
-			"VBUS sourcing disabled");
-	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
-			"PPC is not sourcing VBUS after VBUS enabled");
-}
-
-static void test_ppc_syv682x_interrupt(void)
-{
-	struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD);
-
-	syv682x_emul_set_status(emul, SYV682X_STATUS_OC_5V);
-	syv682x_interrupt(syv682x_port);
-
-	/* An OC event less than 100 ms should not cause VBUS to turn off. */
-	msleep(50);
-	syv682x_interrupt(syv682x_port);
-	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
-			"PPC is not sourcing VBUS after 50 ms OC");
-	/* But one greater than 100 ms should. */
-	msleep(60);
-	syv682x_interrupt(syv682x_port);
-	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
-			"PPC is sourcing VBUS after 100 ms OC");
-
-	syv682x_emul_set_status(emul, 0x0);
-	/*
-	 * TODO(b/190519131): Organize the tests to be more hermetic and avoid
-	 * the following issue: The driver triggers overcurrent protection. If
-	 * overcurrent protection is triggered 3 times, the TC won't turn the
-	 * port back on without a detach. This could frustrate efforts to test
-	 * the TC.
-	 */
-}
-
-static void test_ppc_syv682x(void)
-{
-	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
-
-	test_ppc_syv682x_vbus_enable();
-	test_ppc_syv682x_interrupt();
-}
-
-void test_suite_ppc(void)
-{
-	ztest_test_suite(ppc,
-			 ztest_user_unit_test(test_ppc_syv682x));
-	ztest_run_test_suite(ppc);
-}
diff --git a/zephyr/test/drivers/src/smart.c b/zephyr/test/drivers/src/smart.c
deleted file mode 100644
index 7c053f1c23..0000000000
--- a/zephyr/test/drivers/src/smart.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c.h"
-#include "emul/emul_common_i2c.h"
-#include "emul/emul_smart_battery.h"
-
-#include "battery.h"
-#include "battery_smart.h"
-
-#define BATTERY_ORD	DT_DEP_ORD(DT_NODELABEL(battery))
-
-/** Test all simple getters */
-static void test_battery_getters(void)
-{
-	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
-	char block[32];
-	int expected;
-	int word;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(emul);
-
-	zassert_equal(EC_SUCCESS, battery_get_mode(&word), NULL);
-	zassert_equal(bat->mode, word, "%d != %d", bat->mode, word);
-
-	expected = 100 * bat->cap / bat->design_cap;
-	zassert_equal(EC_SUCCESS, battery_state_of_charge_abs(&word), NULL);
-	zassert_equal(expected, word, "%d != %d", expected, word);
-
-	zassert_equal(EC_SUCCESS, battery_remaining_capacity(&word), NULL);
-	zassert_equal(bat->cap, word, "%d != %d", bat->cap, word);
-	zassert_equal(EC_SUCCESS, battery_full_charge_capacity(&word), NULL);
-	zassert_equal(bat->full_cap, word, "%d != %d", bat->full_cap, word);
-	zassert_equal(EC_SUCCESS, battery_cycle_count(&word), NULL);
-	zassert_equal(bat->cycle_count, word, "%d != %d",
-		      bat->cycle_count, word);
-	zassert_equal(EC_SUCCESS, battery_design_capacity(&word), NULL);
-	zassert_equal(bat->design_cap, word, "%d != %d", bat->design_cap, word);
-	zassert_equal(EC_SUCCESS, battery_design_voltage(&word), NULL);
-	zassert_equal(bat->design_mv, word, "%d != %d", bat->design_mv, word);
-	zassert_equal(EC_SUCCESS, battery_serial_number(&word), NULL);
-	zassert_equal(bat->sn, word, "%d != %d", bat->sn, word);
-	zassert_equal(EC_SUCCESS, get_battery_manufacturer_name(block, 32),
-		      NULL);
-	zassert_mem_equal(block, bat->mf_name, bat->mf_name_len,
-			  "%s != %s", block, bat->mf_name);
-	zassert_equal(EC_SUCCESS, battery_device_name(block, 32), NULL);
-	zassert_mem_equal(block, bat->dev_name, bat->dev_name_len,
-			  "%s != %s", block, bat->dev_name);
-	zassert_equal(EC_SUCCESS, battery_device_chemistry(block, 32), NULL);
-	zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len,
-			  "%s != %s", block, bat->dev_chem);
-	word = battery_get_avg_current();
-	zassert_equal(bat->avg_cur, word, "%d != %d", bat->avg_cur, word);
-
-	bat->avg_cur = 200;
-	expected = (bat->full_cap - bat->cap) * 60 / bat->avg_cur;
-	zassert_equal(EC_SUCCESS, battery_time_to_full(&word), NULL);
-	zassert_equal(expected, word, "%d != %d", expected, word);
-
-	bat->cur = -200;
-	expected = bat->cap * 60 / (-bat->cur);
-	zassert_equal(EC_SUCCESS, battery_run_time_to_empty(&word), NULL);
-	zassert_equal(expected, word, "%d != %d", expected, word);
-
-	bat->avg_cur = -200;
-	expected = bat->cap * 60 / (-bat->avg_cur);
-	zassert_equal(EC_SUCCESS, battery_time_to_empty(&word), NULL);
-	zassert_equal(expected, word, "%d != %d", expected, word);
-}
-
-/** Test battery status */
-static void test_battery_status(void)
-{
-	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
-	int expected;
-	int status;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(emul);
-
-	bat->status = 0;
-	bat->cur = -200;
-	bat->cap_alarm = 0;
-	bat->time_alarm = 0;
-	bat->cap = bat->full_cap / 2;
-	bat->error_code = STATUS_CODE_OVERUNDERFLOW;
-
-	expected = 0;
-	expected |= STATUS_DISCHARGING;
-	expected |= STATUS_CODE_OVERUNDERFLOW;
-
-	zassert_equal(EC_SUCCESS, battery_status(&status), NULL);
-	zassert_equal(expected, status, "%d != %d", expected, status);
-}
-
-/** Test wait for stable function */
-static void test_battery_wait_for_stable(void)
-{
-	struct i2c_emul *emul;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-
-	/* Should fail when read function always fail */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
-	zassert_equal(EC_ERROR_NOT_POWERED, battery_wait_for_stable(), NULL);
-
-	/* Should be ok with default handler */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	zassert_equal(EC_SUCCESS, battery_wait_for_stable(), NULL);
-}
-
-/** Test manufacture date */
-static void test_battery_manufacture_date(void)
-{
-	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
-	int day, month, year;
-	int exp_month = 5;
-	int exp_year = 2018;
-	int exp_day = 19;
-	uint16_t date;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(emul);
-
-	date = sbat_emul_date_to_word(exp_day, exp_month, exp_year);
-	bat->mf_date = date;
-
-	zassert_equal(EC_SUCCESS, battery_manufacture_date(&year, &month, &day),
-		      NULL);
-	zassert_equal(exp_day, day, "%d != %d", exp_day, day);
-	zassert_equal(exp_month, month, "%d != %d", exp_month, month);
-	zassert_equal(exp_year, year, "%d != %d", exp_year, year);
-}
-
-/** Test time at rate */
-static void test_battery_time_at_rate(void)
-{
-	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
-	int expect_time;
-	int minutes;
-	int rate;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(emul);
-
-	/* 3000mAh at rate 300mA will be discharged in 10h */
-	bat->cap = 3000;
-	rate = -300;
-	expect_time = 600;
-
-	zassert_equal(EC_SUCCESS, battery_time_at_rate(rate, &minutes), NULL);
-	zassert_equal(expect_time, minutes, "%d != %d", expect_time, minutes);
-
-	/* 1000mAh at rate 1000mA will be charged in 1h */
-	bat->cap = bat->full_cap - 1000;
-	rate = 1000;
-	/* battery_time_at_rate report time to full as negative number */
-	expect_time = -60;
-
-	zassert_equal(EC_SUCCESS, battery_time_at_rate(rate, &minutes), NULL);
-	zassert_equal(expect_time, minutes, "%d != %d", expect_time, minutes);
-}
-
-/** Test battery get params */
-static void test_battery_get_params(void)
-{
-	struct sbat_emul_bat_data *bat;
-	struct batt_params batt;
-	struct i2c_emul *emul;
-	int flags;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(emul);
-
-	/* Battery wants to charge */
-	bat->desired_charg_cur = 1000;
-	bat->desired_charg_volt = 5000;
-
-	/* Fail temperature read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_TEMPERATURE);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_TEMPERATURE;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail state of charge read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_RELATIVE_STATE_OF_CHARGE);
-	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_STATE_OF_CHARGE;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail voltage read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_VOLTAGE);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_VOLTAGE;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail current read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CURRENT);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_CURRENT;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail average current read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_AVERAGE_CURRENT);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_AVERAGE_CURRENT;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail charging voltage read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CHARGING_VOLTAGE);
-	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_VOLTAGE;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail charging voltage read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CHARGING_CURRENT);
-	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_CURRENT;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail remaining capacity read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_REMAINING_CAPACITY);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_REMAINING_CAPACITY;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail full capacity read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_FULL_CHARGE_CAPACITY);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_FULL_CAPACITY;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail status read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_BATTERY_STATUS);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
-		BATT_FLAG_BAD_STATUS;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Fail all */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
-	flags = BATT_FLAG_BAD_ANY;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-
-	/* Use default handler, everything should be ok */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
-	battery_get_params(&batt);
-	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-}
-
-void test_suite_smart_battery(void)
-{
-	ztest_test_suite(smart_battery,
-			 ztest_user_unit_test(test_battery_getters),
-			 ztest_user_unit_test(test_battery_status),
-			 ztest_user_unit_test(test_battery_wait_for_stable),
-			 ztest_user_unit_test(test_battery_manufacture_date),
-			 ztest_user_unit_test(test_battery_time_at_rate),
-			 ztest_user_unit_test(test_battery_get_params));
-	ztest_run_test_suite(smart_battery);
-}
diff --git a/zephyr/test/drivers/src/stm_mems_common.c b/zephyr/test/drivers/src/stm_mems_common.c
deleted file mode 100644
index 3085007f4d..0000000000
--- a/zephyr/test/drivers/src/stm_mems_common.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ztest.h>
-#include <device.h>
-#include <devicetree.h>
-#include <errno.h>
-
-#include "common.h"
-#include "driver/stm_mems_common.h"
-#include "emul/emul_common_i2c.h"
-#include "emul/i2c_mock.h"
-#include "i2c/i2c.h"
-
-#define MOCK_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(i2c_mock)))
-
-static void setup(void)
-{
-	i2c_mock_reset(MOCK_EMUL);
-}
-
-static int mock_read_fn(struct i2c_emul *emul, int reg, uint8_t *val, int bytes,
-			void *data)
-{
-	ztest_check_expected_value(reg);
-	ztest_check_expected_value(bytes);
-	return ztest_get_return_value();
-}
-
-static void test_st_raw_read_n(void)
-{
-	const struct emul *emul = MOCK_EMUL;
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
-	int rv;
-
-	i2c_common_emul_set_read_func(i2c_emul, mock_read_fn, NULL);
-	ztest_expect_value(mock_read_fn, reg, 0x80);
-	ztest_expect_value(mock_read_fn, bytes, 0);
-	ztest_returns_value(mock_read_fn, -EIO);
-
-	rv = st_raw_read_n(I2C_PORT_POWER, i2c_mock_get_addr(emul), 0, NULL, 2);
-	/* The shim layer translates -EIO to EC_ERROR_INVAL. */
-	zassert_equal(rv, EC_ERROR_INVAL, "rv was %d but expected %d", rv,
-		      EC_ERROR_INVAL);
-}
-
-void test_suite_stm_mems_common(void)
-{
-	ztest_test_suite(stm_mems_common,
-			 ztest_unit_test_setup_teardown(
-				 test_st_raw_read_n,
-				 setup, unit_test_noop));
-	ztest_run_test_suite(stm_mems_common);
-}
diff --git a/zephyr/test/drivers/src/stubs.c b/zephyr/test/drivers/src/stubs.c
deleted file mode 100644
index 6dab320b9a..0000000000
--- a/zephyr/test/drivers/src/stubs.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "bc12/pi3usb9201_public.h"
-#include "charge_ramp.h"
-#include "charger.h"
-#include "charger/isl9241_public.h"
-#include "config.h"
-#include "i2c/i2c.h"
-#include "power.h"
-#include "ppc/sn5s330_public.h"
-#include "ppc/syv682x_public.h"
-#include "retimer/bb_retimer_public.h"
-#include "stubs.h"
-#include "tcpm/tusb422_public.h"
-#include "tcpm/tusb422_public.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-/* All of these definitions are just to get the test to link. None of these
- * functions are useful or behave as they should. Please remove them once the
- * real code is able to be added.  Most of the things here should either be
- * in emulators or in the native_posix board-specific code or part of the
- * device tree.
- */
-
-/* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-const struct board_batt_params board_battery_info[] = {
-	/* LGC\011 L17L3PB0 Battery Information */
-	/*
-	 * Battery info provided by ODM on b/143477210, comment #11
-	 */
-	[BATTERY_LGC011] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x0,
-				.reg_mask = 0x6000,
-				.disconnect_val = 0x6000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13200, 5),
-			.voltage_normal		= 11550, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 256,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 75,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_LGC011;
-
-int board_set_active_charge_port(int port)
-{
-	return EC_SUCCESS;
-}
-
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	return 0;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
-{
-}
-
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-int board_is_sourcing_vbus(int port)
-{
-	return 0;
-}
-
-struct usb_mux usbc1_virtual_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.next_mux = &usbc1_virtual_usb_mux,
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(
-					usb_c1_bb_retimer_emul)),
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct bb_usb_control bb_controls[] = {
-	[USBC_PORT_C0] = {
-		/* USB-C port 0 doesn't have a retimer */
-	},
-	[USBC_PORT_C1] = {
-		.usb_ls_en_gpio = GPIO_USB_C1_LS_EN,
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_ODL,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(bb_controls) == USBC_PORT_COUNT);
-
-void pd_power_supply_reset(int port)
-{
-}
-
-int pd_check_vconn_swap(int port)
-{
-	return 0;
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	return EC_SUCCESS;
-}
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = SYV682X_ADDR1_FLAGS,
-		/* TODO(b/190519131): Add FRS GPIO, test FRS */
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	return 0;
-}
-
-enum power_state power_chipset_init(void)
-{
-	return POWER_G3;
-}
-
-enum power_state mock_state = POWER_G3;
-
-void set_mock_power_state(enum power_state state)
-{
-	mock_state = state;
-	task_wake(TASK_ID_CHIPSET);
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	return mock_state;
-}
-
-void chipset_reset(enum chipset_reset_reason reason)
-{
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-}
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {};
diff --git a/zephyr/test/drivers/src/tcs3400.c b/zephyr/test/drivers/src/tcs3400.c
deleted file mode 100644
index c20137c1ad..0000000000
--- a/zephyr/test/drivers/src/tcs3400.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c.h"
-#include "emul/emul_tcs3400.h"
-#include "emul/emul_common_i2c.h"
-
-#include "motion_sense.h"
-#include "motion_sense_fifo.h"
-#include "driver/als_tcs3400.h"
-
-#define TCS_ORD			DT_DEP_ORD(DT_NODELABEL(tcs_emul))
-#define TCS_CLR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(tcs3400_clear))
-#define TCS_RGB_SENSOR_ID	SENSOR_ID(DT_NODELABEL(tcs3400_rgb))
-#define TCS_INT_EVENT		\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
-
-/** How accurate comparision of rgb sensors should be */
-#define V_EPS		8
-
-/** Test initialization of light sensor driver and device */
-static void test_tcs_init(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* RGB sensor initialization is always successful */
-	zassert_equal(EC_SUCCESS, ms_rgb->drv->init(ms_rgb), NULL);
-
-	/* Fail init on communication errors */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->init(ms), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Fail on bad ID */
-	tcs_emul_set_reg(emul, TCS_I2C_ID, 0);
-	zassert_equal(EC_ERROR_ACCESS_DENIED, ms->drv->init(ms), NULL);
-	/* Restore ID */
-	tcs_emul_set_reg(emul, TCS_I2C_ID,
-			 DT_STRING_TOKEN(DT_NODELABEL(tcs_emul), device_id));
-
-	/* Test successful init. ATIME and AGAIN should be changed on init */
-	zassert_equal(EC_SUCCESS, ms->drv->init(ms), NULL);
-	zassert_equal(TCS_DEFAULT_ATIME,
-		      tcs_emul_get_reg(emul, TCS_I2C_ATIME), NULL);
-	zassert_equal(TCS_DEFAULT_AGAIN,
-		      tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL);
-}
-
-/** Test if read function leaves device in correct mode to accuire data */
-static void test_tcs_read(void)
-{
-	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	uint8_t enable;
-	intv3_t v;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-
-	/* Test error on writing registers */
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ATIME);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_CONTROL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ENABLE);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test starting read with calibration */
-	tcs_emul_set_reg(emul, TCS_I2C_ATIME, 0);
-	tcs_emul_set_reg(emul, TCS_I2C_CONTROL, 0);
-	tcs_emul_set_reg(emul, TCS_I2C_ENABLE, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v), NULL);
-	zassert_equal(TCS_CALIBRATION_ATIME,
-		      tcs_emul_get_reg(emul, TCS_I2C_ATIME), NULL);
-	zassert_equal(TCS_CALIBRATION_AGAIN,
-		      tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL);
-	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
-	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE, NULL);
-
-	/* Test starting read without calibration */
-	tcs_emul_set_reg(emul, TCS_I2C_ATIME, 0);
-	tcs_emul_set_reg(emul, TCS_I2C_CONTROL, 0);
-	tcs_emul_set_reg(emul, TCS_I2C_ENABLE, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v), NULL);
-	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
-	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE, NULL);
-}
-
-/** Check if FIFO for RGB and clear sensor is empty */
-static void check_fifo_empty_f(struct motion_sensor_t *ms,
-			       struct motion_sensor_t *ms_rgb, int line)
-{
-	struct ec_response_motion_sensor_data vector;
-	uint16_t size;
-
-	/* Read all data committed to FIFO */
-	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
-		/* Ignore timestamp frames */
-		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
-			continue;
-		}
-
-		if (ms - motion_sensors == vector.sensor_num) {
-			zassert_unreachable(
-					"Unexpected frame for clear sensor");
-		}
-
-		if (ms_rgb - motion_sensors == vector.sensor_num) {
-			zassert_unreachable("Unexpected frame for rgb sensor");
-		}
-	}
-}
-#define check_fifo_empty(ms, ms_rgb)		\
-	check_fifo_empty_f(ms, ms_rgb, __LINE__)
-
-/**
- * Test different conditions where irq handler fail or commit no data
- * to fifo
- */
-static void test_tcs_irq_handler_fail(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-	uint32_t event;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* Fail on wrong event */
-	event = 0x1234 & ~TCS_INT_EVENT;
-	zassert_equal(EC_ERROR_NOT_HANDLED, ms->drv->irq_handler(ms, &event),
-		      NULL);
-	check_fifo_empty(ms, ms_rgb);
-
-	event = TCS_INT_EVENT;
-	/* Test error on reading status */
-	i2c_common_emul_set_read_fail_reg(emul, TCS_I2C_STATUS);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	check_fifo_empty(ms, ms_rgb);
-
-	/* Test fail on changing device power state */
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ENABLE);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	check_fifo_empty(ms, ms_rgb);
-
-	/* Test that no data is committed when status is 0 */
-	tcs_emul_set_reg(emul, TCS_I2C_STATUS, 0);
-	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event), NULL);
-	check_fifo_empty(ms, ms_rgb);
-}
-
-/**
- * Check if last data committed to FIFO for RGB and clear sensor equals to
- * expected value.
- */
-static void check_fifo_f(struct motion_sensor_t *ms,
-			 struct motion_sensor_t *ms_rgb,
-			 int *exp_v, int eps, int line)
-{
-	struct ec_response_motion_sensor_data vector;
-	uint16_t size;
-	int ret_v[4] = {-1, -1, -1, -1};
-	int i;
-
-	/* Read all data committed to FIFO */
-	while (motion_sense_fifo_read(sizeof(vector), 1, &vector, &size)) {
-		/* Ignore timestamp frames */
-		if (vector.flags == MOTIONSENSE_SENSOR_FLAG_TIMESTAMP) {
-			continue;
-		}
-
-		/* Get clear frame */
-		if (ms - motion_sensors == vector.sensor_num) {
-			ret_v[0] = vector.udata[0];
-		}
-
-		/* Get rgb frame */
-		if (ms_rgb - motion_sensors == vector.sensor_num) {
-			ret_v[1] = vector.udata[0];
-			ret_v[2] = vector.udata[1];
-			ret_v[3] = vector.udata[2];
-		}
-	}
-
-	if (ret_v[0] == -1) {
-		zassert_unreachable("No frame for clear sensor, line %d", line);
-	}
-
-	if (ret_v[1] == -1) {
-		zassert_unreachable("No frame for rgb sensor, line %d", line);
-	}
-
-	/* Compare with last committed data */
-	for (i = 0; i < 4; i++) {
-		zassert_within(exp_v[i], ret_v[i], eps,
-			"Expected [%d; %d; %d; %d], got [%d; %d; %d; %d]; line: %d",
-			exp_v[0], exp_v[1], exp_v[2], exp_v[3],
-			ret_v[0], ret_v[1], ret_v[2], ret_v[3], line);
-	}
-}
-#define check_fifo(ms, ms_rgb, exp_v, eps)		\
-	check_fifo_f(ms, ms_rgb, exp_v, eps, __LINE__)
-
-/** Test calibration mode reading of light sensor values */
-static void test_tcs_read_calibration(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-	uint32_t event = TCS_INT_EVENT;
-	int emul_v[4];
-	int exp_v[4];
-	intv3_t v;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* Need to be set to collect all data in FIFO */
-	ms->oversampling_ratio = 1;
-	ms_rgb->oversampling_ratio = 1;
-	/* Enable calibration mode */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
-	/* Setup AGAIN and ATIME for calibration */
-	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v), NULL);
-
-	/* Test data that are in calibration range */
-	exp_v[0] = 12;
-	exp_v[1] = 123;
-	exp_v[2] = 1234;
-	exp_v[3] = 12345;
-	/*
-	 * Emulator value is with gain 64, while expected value is
-	 * with gain 16
-	 */
-	emul_v[0] = exp_v[0] * 64 / 16;
-	emul_v[1] = exp_v[1] * 64 / 16;
-	emul_v[2] = exp_v[2] * 64 / 16;
-	emul_v[3] = exp_v[3] * 64 / 16;
-	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
-	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
-	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
-	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
-	/* Set status to show valid data */
-	tcs_emul_set_reg(emul, TCS_I2C_STATUS, TCS_I2C_STATUS_RGBC_VALID);
-
-	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event), NULL);
-	/* In calibration mode check for exact match */
-	check_fifo(ms, ms_rgb, exp_v, 1);
-
-	/* Test data that are outside of calibration range */
-	exp_v[0] = 0;
-	exp_v[1] = UINT16_MAX;
-	exp_v[2] = UINT16_MAX;
-	exp_v[3] = 213;
-	/*
-	 * Emulator value is with gain 64, while expected value is
-	 * with gain 16
-	 */
-	emul_v[0] = 0;
-	emul_v[1] = exp_v[1] * 64 / 16;
-	emul_v[2] = (UINT16_MAX + 23) * 64 / 16;
-	emul_v[3] = exp_v[3] * 64 / 16;
-	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
-	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
-	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
-	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
-	/* Set status to show valid data */
-	tcs_emul_set_reg(emul, TCS_I2C_STATUS, TCS_I2C_STATUS_RGBC_VALID);
-
-	zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event), NULL);
-	/* In calibration mode check for exact match */
-	check_fifo(ms, ms_rgb, exp_v, 1);
-}
-
-/**
- * Set emulator internal value using expected output value returned by
- * the driver. First element of expected vector is IR value used in
- * calculations. Based on that clear light value is calculated.
- * First element of expected vector is updated by this function.
- */
-static void set_emul_val_from_exp(int *exp_v, uint16_t *scale,
-				  struct i2c_emul *emul)
-{
-	int emul_v[4];
-	int ir;
-
-	/* We use exp_v[0] as IR value */
-	ir = exp_v[0];
-	/* Driver will return lux value as calculated blue light value */
-	exp_v[0] = exp_v[2];
-
-	/*
-	 * Driver takes care of different ATIME and AGAIN value, so expected
-	 * value is always normalized to ATIME 256 and AGAIN 16. Convert it
-	 * to internal emulator value (ATIME 256, AGAIN 64) and add expected IR
-	 * value. Clear light is the sum of rgb light and IR component.
-	 */
-	emul_v[1] = (exp_v[1] + ir) * 64 / 16;
-	emul_v[2] = (exp_v[2] + ir) * 64 / 16;
-	emul_v[3] = (exp_v[3] + ir) * 64 / 16;
-	emul_v[0] = (exp_v[1] + exp_v[2] + exp_v[3] + ir) * 64 / 16;
-
-	/* Apply scale, driver should divide by this value */
-	emul_v[0] = SENSOR_APPLY_SCALE(emul_v[0], scale[0]);
-	emul_v[1] = SENSOR_APPLY_SCALE(emul_v[1], scale[1]);
-	emul_v[2] = SENSOR_APPLY_SCALE(emul_v[2], scale[2]);
-	emul_v[3] = SENSOR_APPLY_SCALE(emul_v[3], scale[3]);
-
-	/* Set emulator values */
-	tcs_emul_set_val(emul, TCS_EMUL_C, emul_v[0]);
-	tcs_emul_set_val(emul, TCS_EMUL_R, emul_v[1]);
-	tcs_emul_set_val(emul, TCS_EMUL_G, emul_v[2]);
-	tcs_emul_set_val(emul, TCS_EMUL_B, emul_v[3]);
-}
-
-/** Test normal mode reading of light sensor values */
-static void test_tcs_read_xyz(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-	uint32_t event = TCS_INT_EVENT;
-	/* Expected data to test: IR, R, G, B */
-	int exp_v[][4] = {
-		{200,	1110,	870,	850},
-		{300,	1110,	10000,	8500},
-		{600,	50000,	40000,	30000},
-		{1000,	3000,	40000,	2000},
-		{1000,	65000,	65000,	65000},
-		{100,	214,	541,	516},
-		{143,	2141,	5414,	5163},
-		{100,	50000,	40000,	30000},
-		{1430,	2141,	5414,	5163},
-		{10000,	50000,	40000,	30000},
-		{10000,	214,	541,	516},
-		{15000,	50000,	40000,	30000},
-	};
-	uint16_t scale[4] = {
-		MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE
-	};
-	int i, test;
-	intv3_t v;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* Need to be set to collect all data in FIFO */
-	ms->oversampling_ratio = 1;
-	ms_rgb->oversampling_ratio = 1;
-	/* Disable calibration mode */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	/* Setup AGAIN and ATIME for normal mode */
-	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v), NULL);
-
-	/* Test different data in supported range */
-	for (test = 0; test < ARRAY_SIZE(exp_v); test++) {
-		set_emul_val_from_exp(exp_v[test], scale, emul);
-
-		/* Run few times to allow driver change gain */
-		for (i = 0; i < 5; i++) {
-			tcs_emul_set_reg(emul, TCS_I2C_STATUS,
-					 TCS_I2C_STATUS_RGBC_VALID);
-			zassert_equal(EC_SUCCESS,
-				      ms->drv->irq_handler(ms, &event), NULL);
-		}
-		check_fifo(ms, ms_rgb, exp_v[test], V_EPS);
-	}
-
-	/* Test data that are outside of supported range */
-	exp_v[0][0] = 3000;
-	exp_v[0][1] = UINT16_MAX;
-	exp_v[0][2] = UINT16_MAX * 32;
-	exp_v[0][3] = 200;
-	set_emul_val_from_exp(exp_v[0], scale, emul);
-
-	/* Run few times to allow driver change gain */
-	for (i = 0; i < 10; i++) {
-		tcs_emul_set_reg(emul, TCS_I2C_STATUS,
-				 TCS_I2C_STATUS_RGBC_VALID);
-		zassert_equal(EC_SUCCESS, ms->drv->irq_handler(ms, &event),
-			      NULL);
-	}
-	/*
-	 * If saturation value is exceeded on any rgb sensor, than data
-	 * shouldn't be committed to FIFO.
-	 */
-	check_fifo_empty(ms, ms_rgb);
-}
-
-/**
- * Test getting and setting scale of light sensor. Checks if collected values
- * are scaled properly.
- */
-static void test_tcs_scale(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-	uint32_t event = TCS_INT_EVENT;
-	/* Expected data to test: IR, R, G, B */
-	int exp_v[][4] = {
-		{200,	1110,	870,	850},
-		{300,	1110,	10000,	8500},
-		{600,	5000,	4000,	3000},
-		{100,	3000,	4000,	2000},
-		{100,	1000,	1000,	1000},
-	};
-	/* Scale for each test */
-	uint16_t exp_scale[][4] = {
-		{MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		 MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE},
-		{MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300},
-		{MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300},
-		{MOTION_SENSE_DEFAULT_SCALE + 345,
-		 MOTION_SENSE_DEFAULT_SCALE - 5423,
-		 MOTION_SENSE_DEFAULT_SCALE - 30,
-		 MOTION_SENSE_DEFAULT_SCALE + 400},
-		{MOTION_SENSE_DEFAULT_SCALE - 345,
-		 MOTION_SENSE_DEFAULT_SCALE + 5423,
-		 MOTION_SENSE_DEFAULT_SCALE + 30,
-		 MOTION_SENSE_DEFAULT_SCALE - 400},
-		{MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		 MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE}
-	};
-	uint16_t scale[3];
-	int16_t temp;
-	int i, test;
-	intv3_t v;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* Need to be set to collect all data in FIFO */
-	ms->oversampling_ratio = 1;
-	ms_rgb->oversampling_ratio = 1;
-	/* Disable calibration mode */
-	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 0), NULL);
-	/* Setup AGAIN and ATIME for normal mode */
-	zassert_equal(EC_RES_IN_PROGRESS, ms->drv->read(ms, v), NULL);
-
-	/* Test different data in supported range */
-	for (test = 0; test < ARRAY_SIZE(exp_v); test++) {
-		/* Set and test clear sensor scale */
-		zassert_equal(EC_SUCCESS,
-			      ms->drv->set_scale(ms, exp_scale[test], 0),
-			      "test %d", test);
-		zassert_equal(EC_SUCCESS,
-			      ms->drv->get_scale(ms, scale, &temp),
-			      "test %d", test);
-		zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp,
-			      "test %d, %d", test, temp);
-		zassert_equal(exp_scale[test][0], scale[0], "test %d", test);
-
-		/* Set and test RGB sensor scale */
-		zassert_equal(EC_SUCCESS, ms_rgb->drv->set_scale(ms_rgb,
-						&(exp_scale[test][1]), 0),
-			      "test %d", test);
-		zassert_equal(EC_SUCCESS,
-			      ms_rgb->drv->get_scale(ms_rgb, scale, &temp),
-			      "test %d", test);
-		zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp,
-			      "test %d", test);
-		zassert_equal(exp_scale[test][1], scale[0], "test %d", test);
-		zassert_equal(exp_scale[test][2], scale[1], "test %d", test);
-		zassert_equal(exp_scale[test][3], scale[2], "test %d", test);
-
-		set_emul_val_from_exp(exp_v[test], exp_scale[test], emul);
-
-		/* Run few times to allow driver change gain */
-		for (i = 0; i < 5; i++) {
-			tcs_emul_set_reg(emul, TCS_I2C_STATUS,
-					 TCS_I2C_STATUS_RGBC_VALID);
-			zassert_equal(EC_SUCCESS,
-				      ms->drv->irq_handler(ms, &event), NULL);
-		}
-		check_fifo(ms, ms_rgb, exp_v[test], V_EPS);
-	}
-
-	/* Test fail if scale equals 0 */
-	scale[0] = 0;
-	scale[1] = MOTION_SENSE_DEFAULT_SCALE;
-	scale[2] = MOTION_SENSE_DEFAULT_SCALE;
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_scale(ms, scale, 0), NULL);
-
-	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
-		      NULL);
-	scale[0] = MOTION_SENSE_DEFAULT_SCALE;
-	scale[1] = 0;
-	scale[2] = MOTION_SENSE_DEFAULT_SCALE;
-	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
-		      NULL);
-	scale[0] = MOTION_SENSE_DEFAULT_SCALE;
-	scale[1] = MOTION_SENSE_DEFAULT_SCALE;
-	scale[2] = 0;
-	zassert_equal(EC_ERROR_INVAL, ms_rgb->drv->set_scale(ms_rgb, scale, 0),
-		      NULL);
-}
-
-/** Test setting and getting data rate of light sensor */
-static void test_tcs_data_rate(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-	uint8_t enable;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	/* RGB sensor doesn't set rate, but return rate of clear sesnor */
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* Test fail on reading device power state */
-	i2c_common_emul_set_read_fail_reg(emul, TCS_I2C_ENABLE);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 0), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 1), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 0), NULL);
-	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 1), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-
-	/* Test setting 0 rate disables device */
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
-	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE), NULL);
-	zassert_equal(0, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 1), NULL);
-	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE), NULL);
-	zassert_equal(0, tcs_emul_get_reg(emul, TCS_I2C_ENABLE), NULL);
-	zassert_equal(0, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-
-
-	/* Test setting non-zero rate enables device */
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 0), NULL);
-	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
-	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE, NULL);
-	zassert_equal(100, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 1), NULL);
-	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
-	zassert_true(enable & TCS_I2C_ENABLE_POWER_ON, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_ADC_ENABLE, NULL);
-	zassert_true(enable & TCS_I2C_ENABLE_INT_ENABLE, NULL);
-	zassert_equal(100, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-
-	/* Test RGB sensor doesn't change data rate */
-	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_data_rate(ms_rgb, 300, 0),
-		      NULL);
-	zassert_equal(100, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-
-	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_data_rate(ms_rgb, 300, 1),
-		      NULL);
-	zassert_equal(100, ms->drv->get_data_rate(ms), NULL);
-	zassert_equal(100, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
-}
-
-/** Test set range function of clear and RGB sensors */
-static void test_tcs_set_range(void)
-{
-	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
-
-	emul = tcs_emul_get(TCS_ORD);
-	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
-	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
-
-	/* RGB sensor doesn't set anything */
-	zassert_equal(EC_SUCCESS, ms_rgb->drv->set_range(ms_rgb, 1, 0), NULL);
-
-	/* Clear sensor doesn't change anything on device to set range */
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 0x12300, 1), NULL);
-	zassert_equal(0x12300, ms->current_range, NULL);
-
-	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, 0x10000, 0), NULL);
-	zassert_equal(0x10000, ms->current_range, NULL);
-}
-
-void test_suite_tcs3400(void)
-{
-	ztest_test_suite(tcs3400,
-			 ztest_user_unit_test(test_tcs_init),
-			 ztest_user_unit_test(test_tcs_read),
-			 ztest_user_unit_test(test_tcs_irq_handler_fail),
-			 ztest_user_unit_test(test_tcs_read_calibration),
-			 ztest_user_unit_test(test_tcs_read_xyz),
-			 ztest_user_unit_test(test_tcs_scale),
-			 ztest_user_unit_test(test_tcs_data_rate),
-			 ztest_user_unit_test(test_tcs_set_range));
-	ztest_run_test_suite(tcs3400);
-}
diff --git a/zephyr/test/drivers/src/temp_sensor.c b/zephyr/test/drivers/src/temp_sensor.c
deleted file mode 100644
index 83a343e572..0000000000
--- a/zephyr/test/drivers/src/temp_sensor.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <drivers/adc.h>
-#include <drivers/adc/adc_emul.h>
-#include <drivers/gpio.h>
-#include <drivers/gpio/gpio_emul.h>
-
-#include <math.h>
-
-#include "common.h"
-#include "temp_sensor.h"
-#include "temp_sensor/temp_sensor.h"
-
-#define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok)
-#define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
-
-#define ADC_DEVICE_NODE		DT_NODELABEL(adc0)
-#define ADC_CHANNELS_NUM	DT_PROP(DT_NODELABEL(adc0), nchannels)
-
-/** Test error code when invalid sensor is passed to temp_sensor_read() */
-static void test_temp_sensor_wrong_id(void)
-{
-	int temp;
-
-	zassert_equal(EC_ERROR_INVAL, temp_sensor_read(TEMP_SENSOR_COUNT,
-						       &temp),
-		      NULL);
-}
-
-/** Test error code when temp_sensor_read() is called with powered off ADC */
-static void test_temp_sensor_adc_error(void)
-{
-	const struct device *gpio_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
-	int temp;
-
-	zassert_not_null(gpio_dev, "Cannot get GPIO device");
-
-	/*
-	 * pg_ec_dsw_pwrok = 0 means ADC is not powered.
-	 * adc_read will return error
-	 */
-	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 0),
-		   NULL);
-
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_CHARGER, &temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_DDR_SOC, &temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_FAN, &temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_PP3300_REGULATOR, &temp),
-		      NULL);
-
-	/* power ADC */
-	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
-		   NULL);
-}
-
-/** Simple ADC emulator custom function which always return error */
-static int adc_error_func(const struct device *dev, unsigned int channel,
-			  void *param, uint32_t *result)
-{
-	return -EINVAL;
-}
-
-/**
- * Set valid response only for ADC channel connected with tested sensor.
- * Check if temp_sensor_read() from tested sensor returns EC_SUCCESS and
- * valid temperature. Set invalid response on ADC channel for next test.
- */
-static void check_valid_temperature(const struct device *adc_dev, int sensor)
-{
-	int temp;
-
-	/* ADC channel of tested sensor return valid value */
-	zassert_ok(adc_emul_const_value_set(adc_dev, temp_sensors[sensor].idx,
-					    1000),
-		   "adc_emul_const_value_set() failed (sensor %d)", sensor);
-	zassert_equal(EC_SUCCESS, temp_sensor_read(sensor, &temp), NULL);
-	zassert_within(temp, 273 + 50, 51,
-		       "Expected temperature in 0*C-100*C, got %d*C (sensor %d)",
-		       temp - 273, sensor);
-	/* Return error on ADC channel of tested sensor */
-	zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensors[sensor].idx,
-					   adc_error_func, NULL),
-		   "adc_emul_value_func_set() failed (sensor %d)", sensor);
-}
-
-/** Test if temp_sensor_read() returns temperature on success */
-static void test_temp_sensor_read(void)
-{
-	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
-	int chan;
-
-	zassert_not_null(adc_dev, "Cannot get ADC device");
-
-	/* Return error on all ADC channels */
-	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
-		zassert_ok(adc_emul_value_func_set(adc_dev, chan,
-						    adc_error_func, NULL),
-			   "channel %d adc_emul_value_func_set() failed", chan);
-	}
-
-	check_valid_temperature(adc_dev, TEMP_SENSOR_CHARGER);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_DDR_SOC);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_FAN);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_PP3300_REGULATOR);
-
-	/* Return correct value on all ADC channels */
-	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
-		zassert_ok(adc_emul_const_value_set(adc_dev, chan, 1000),
-			   "channel %d adc_emul_const_value_set() failed",
-			   chan);
-	}
-}
-
-void test_suite_temp_sensor(void)
-{
-	const struct device *dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
-
-	zassert_not_null(dev, NULL);
-	/* Before tests make sure that power pin is set. */
-	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
-		   NULL);
-
-	ztest_test_suite(temp_sensor,
-			 ztest_user_unit_test(test_temp_sensor_wrong_id),
-			 ztest_user_unit_test(test_temp_sensor_adc_error),
-			 ztest_user_unit_test(test_temp_sensor_read));
-	ztest_run_test_suite(temp_sensor);
-}
diff --git a/zephyr/test/drivers/src/thermistor.c b/zephyr/test/drivers/src/thermistor.c
deleted file mode 100644
index a7137d5f19..0000000000
--- a/zephyr/test/drivers/src/thermistor.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr.h>
-#include <ztest.h>
-#include <drivers/adc.h>
-#include <drivers/adc/adc_emul.h>
-#include <drivers/gpio.h>
-#include <drivers/gpio/gpio_emul.h>
-#include <temp_sensor.h>
-
-#include "common.h"
-#include "../driver/temp_sensor/thermistor.h"
-#include "temp_sensor/temp_sensor.h"
-
-
-#define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok)
-#define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
-
-#define ADC_DEVICE_NODE		DT_NODELABEL(adc0)
-
-/* TODO replace counting macros with DT macro when
- * https://github.com/zephyrproject-rtos/zephyr/issues/38715 lands
- */
-#define _ACCUMULATOR(x)
-#define NAMED_TEMP_SENSORS_SIZE                                     \
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), _ACCUMULATOR) \
-	0
-#define TEMP_SENSORS_ENABLED_SIZE \
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, _ACCUMULATOR) 0
-
-/* Conversion of temperature doesn't need to be 100% accurate */
-#define TEMP_EPS	2
-
-#define A_VALID_VOLTAGE 1000
-/**
- * Test if get temp function return expected error when ADC is not powered
- * (indicated as GPIO pin set to low) and return success after powering on ADC.
- */
-static void test_thermistor_power_pin(void)
-{
-	int temp;
-	int sensor_idx;
-
-	const struct device *gpio_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
-	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
-
-	zassert_not_null(gpio_dev, "Cannot get GPIO device");
-	zassert_not_null(adc_dev, "Cannot get ADC device");
-
-	/* Make sure that ADC return a valid value */
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
-	     sensor_idx++) {
-		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
-
-		zassert_ok(adc_emul_const_value_set(adc_dev,
-						   sensor->idx,
-						   A_VALID_VOLTAGE),
-			   "adc_emul_value_func_set() failed on %s",
-			   sensor->name);
-	}
-
-	/* pg_ec_dsw_pwrok = 0 means ADC is not powered. */
-	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 0),
-		   NULL);
-
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
-	     sensor_idx++) {
-		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
-
-		zassert_equal(EC_ERROR_NOT_POWERED, sensor->read(sensor, &temp),
-			      "%s failed", sensor->name);
-	}
-
-	/* pg_ec_dsw_pwrok = 1 means ADC is powered. */
-	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
-		   NULL);
-
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
-	     sensor_idx++) {
-		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
-
-		zassert_equal(EC_SUCCESS, sensor->read(sensor, &temp),
-			      "%s failed", sensor->name);
-	}
-}
-
-/* Simple ADC emulator custom function which always return error */
-static int adc_error_func(const struct device *dev, unsigned int channel,
-			  void *param, uint32_t *result)
-{
-	return -EINVAL;
-}
-
-/** Test if get temp function return expected error on ADC malfunction */
-static void test_thermistor_adc_read_error(void)
-{
-	int temp;
-	int sensor_idx;
-
-	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
-
-	zassert_not_null(adc_dev, "Cannot get ADC device");
-
-	/* Return error on all ADC channels */
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
-	     sensor_idx++) {
-		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
-
-		zassert_ok(adc_emul_value_func_set(adc_dev, sensor->idx,
-						   adc_error_func, NULL),
-			   "adc_emul_value_func_set() failed on %s",
-			   sensor->name);
-	}
-
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
-	     sensor_idx++) {
-		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
-
-		zassert_equal(EC_ERROR_UNKNOWN, sensor->read(sensor, &temp),
-			      "%s failed", sensor->name);
-	}
-}
-
-/** Get resistance of thermistor for given temperature */
-static int resistance_47kohm_B4050(int t)
-{
-	/* Thermistor manufacturer resistance lookup table*/
-	int r_table[] = {
-		155700, 147900, 140600, 133700, 127200, /* 0*C  - 4*C */
-		121000, 115100, 109600, 104300, 99310,  /* 5*C  - 9*C */
-		94600,  90130,  85890,  81870,  78070,  /* 10*C - 14*C */
-		74450,  71020,  67770,  64680,  61750,  /* 15*C - 19*C */
-		58970,  56320,  53810,  51430,  49160,  /* 20*C - 24*C */
-		47000,  44950,  42990,  41130,  39360,  /* 25*C - 29*C */
-		37680,  36070,  34540,  33080,  31690,  /* 30*C - 34*C */
-		30360,  29100,  27900,  26750,  25650,  /* 35*C - 39*C */
-		24610,  23610,  22660,  21750,  20880,  /* 40*C - 44*C */
-		20050,  19260,  18500,  17780,  17090,  /* 45*C - 49*C */
-		16430,  15800,  15200,  14620,  14070,  /* 50*C - 54*C */
-		13540,  13030,  12550,  12090,  11640,  /* 55*C - 59*C */
-		11210,  10800,  10410,  10040,  9676,   /* 60*C - 64*C */
-		9331,   8999,   8680,   8374,   8081,   /* 65*C - 69*C */
-		7799,   7528,   7268,   7018,   6777,   /* 70*C - 74*C */
-		6546,   6324,   6111,   5906,   5708,   /* 75*C - 79*C */
-		5518,   5335,   5160,   4990,   4827,   /* 80*C - 84*C */
-		4671,   4519,   4374,   4233,   4098,   /* 85*C - 89*C */
-		3968,   3842,   3721,   3605,   3492,   /* 90*C - 94*C */
-		3384,   3279,   3179,   3082,   2988,   /* 95*C - 99*C */
-		2898                                    /* 100*C */
-	};
-
-	t -= 273;
-	if (t < 0)
-		return r_table[0] + 10000;
-
-	if (t >= ARRAY_SIZE(r_table))
-		return r_table[ARRAY_SIZE(r_table) - 1] - 100;
-
-	return r_table[t];
-}
-
-/**
- * Calculate output voltage in voltage divider circuit using formula
- * Vout = Vs * r2 / (r1 + r2)
- */
-static int volt_divider(int vs, int r1, int r2)
-{
-	return vs * r2 / (r1 + r2);
-}
-
-struct thermistor_state {
-	const int v;
-	const int r;
-	int temp_expected;
-};
-
-/** ADC emulator function which calculate output voltage for given thermistor */
-static int adc_temperature_func(const struct device *dev, unsigned int channel,
-				void *param, uint32_t *result)
-{
-	struct thermistor_state *s = (struct thermistor_state *)param;
-
-	*result = volt_divider(s->v,
-			       s->r,
-			       resistance_47kohm_B4050(s->temp_expected));
-
-	return 0;
-}
-
-/** Test conversion from ADC raw value to temperature */
-static void do_thermistor_test(const struct temp_sensor_t *temp_sensor,
-			       int reference_mv, int reference_ohms)
-{
-	int temp_expected;
-	int temp;
-
-	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
-	struct thermistor_state state = {
-		.v = reference_mv,
-		.r = reference_ohms,
-	};
-
-	zassert_not_null(adc_dev, "Cannot get ADC device");
-
-	/* Setup ADC channel */
-	zassert_ok(adc_emul_value_func_set(adc_dev,
-					   temp_sensor->idx,
-					   adc_temperature_func, &state),
-		   "adc_emul_value_func_set() failed on %s", temp_sensor->name);
-
-	/* Makes sure that reference voltage is correct for given thermistor */
-	zassert_ok(adc_emul_ref_voltage_set(adc_dev, ADC_REF_INTERNAL, state.v),
-		   "adc_emul_ref_voltage_set() failed %s on ",
-		   temp_sensor->name);
-
-	/* Test whole supported range from 0*C to 100*C (273*K to 373*K) */
-	for (temp_expected = 273; temp_expected <= 373; temp_expected++) {
-		state.temp_expected = temp_expected;
-		zassert_equal(EC_SUCCESS, temp_sensor->read(temp_sensor, &temp),
-			      "failed on %s", temp_sensor->name);
-		zassert_within(temp_expected, temp, TEMP_EPS,
-			       "Expected %d*K, got %d*K on %s", temp_expected,
-			       temp, temp_sensor->name);
-	}
-
-	/* Temperatures below 0*C should be reported as 0*C */
-	state.temp_expected = -15 + 273;
-	zassert_equal(EC_SUCCESS, temp_sensor->read(temp_sensor, &temp),
-		      "failed on %s", temp_sensor->name);
-	zassert_equal(273, temp, "Expected %d*K, got %d*K on %s", 273, temp,
-		      temp_sensor->name);
-
-	/* Temperatures above 100*C should be reported as 100*C */
-	state.temp_expected = 115 + 273;
-	zassert_equal(EC_SUCCESS, temp_sensor->read(temp_sensor, &temp),
-		      "failed on %s", temp_sensor->name);
-	zassert_equal(373, temp, "Expected %d*K, got %d*K on %s", 373, temp,
-		      temp_sensor->name);
-}
-
-#define GET_THERMISTOR_REF_MV(node_id)             \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = DT_PROP( \
-		DT_PHANDLE(node_id, thermistor), steinhart_reference_mv),
-
-#define GET_THERMISTOR_REF_RES(node_id)            \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = DT_PROP( \
-		DT_PHANDLE(node_id, thermistor), steinhart_reference_res),
-
-static void test_thermistors_adc_temperature_conversion(void)
-{
-	int sensor_idx;
-
-	const static int reference_mv_arr[] = { DT_FOREACH_STATUS_OKAY(
-		cros_temp_sensor, GET_THERMISTOR_REF_MV) };
-	const static int reference_res_arr[] = { DT_FOREACH_STATUS_OKAY(
-		cros_temp_sensor, GET_THERMISTOR_REF_RES) };
-
-	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE; sensor_idx++)
-		do_thermistor_test(&temp_sensors[sensor_idx],
-				   reference_mv_arr[sensor_idx],
-				   reference_res_arr[sensor_idx]);
-}
-
-static void test_device_nodes_enabled(void)
-{
-	zassert_equal(NAMED_TEMP_SENSORS_SIZE, TEMP_SENSORS_ENABLED_SIZE,
-		      "Temperature sensors in device tree and "
-		      "those enabled for test differ");
-
-	/* Thermistor nodes being enabled are already tested by compilation. */
-}
-
-void test_suite_thermistor(void)
-{
-	const struct device *dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
-
-	zassert_not_null(dev, NULL);
-	/* Before tests make sure that power pin is set. */
-	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
-		   NULL);
-
-	ztest_test_suite(thermistor,
-			 ztest_user_unit_test(test_device_nodes_enabled),
-			 ztest_user_unit_test(test_thermistor_power_pin),
-			 ztest_user_unit_test(test_thermistor_adc_read_error),
-			 ztest_user_unit_test(
-				test_thermistors_adc_temperature_conversion));
-
-	ztest_run_test_suite(thermistor);
-}
diff --git a/zephyr/test/drivers/zmake.yaml b/zephyr/test/drivers/zmake.yaml
deleted file mode 100644
index 31d8523e8e..0000000000
--- a/zephyr/test/drivers/zmake.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
-dts-overlays:
-  - overlay.dts
diff --git a/zephyr/test/ec_app/CMakeLists.txt b/zephyr/test/ec_app/CMakeLists.txt
deleted file mode 100644
index 8ee9a554a7..0000000000
--- a/zephyr/test/ec_app/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(ec_app)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/ec_app/prj.conf b/zephyr/test/ec_app/prj.conf
deleted file mode 100644
index b398d0dd8c..0000000000
--- a/zephyr/test/ec_app/prj.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
diff --git a/zephyr/test/ec_app/src/main.c b/zephyr/test/ec_app/src/main.c
deleted file mode 100644
index 6aa2d6c1b9..0000000000
--- a/zephyr/test/ec_app/src/main.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ztest.h>
-#include "ec_app_main.h"
-#include "hooks.h"
-
-static void test_init_reset_log(void)
-{
-#ifdef CONFIG_CMD_AP_RESET_LOG
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_lpc_init_mask(void)
-{
-#ifdef CONFIG_HOSTCMD_X86
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_keyboard_scan_init(void)
-{
-#ifdef HAS_TASK_KEYSCAN
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_button_init(void)
-{
-#if defined(CONFIG_DEDICATED_RECOVERY_BUTTON) || defined(CONFIG_VOLUME_BUTTONS)
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_setup_espi(void)
-{
-#ifdef CONFIG_PLATFORM_EC_ESPI
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_watchdog_init(void)
-{
-#ifdef CONFIG_PLATFORM_EC_WATCHDOG
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-static void test_vboot_main(void)
-{
-#ifdef CONFIG_PLATFORM_EC_VBOOT_EFS2
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-#ifdef CONFIG_PLATFORM_EC_HOOKS
-static int sample_init_hook_count;
-/**
- * Just a sample hook.
- */
-static void sample_init_hook(void)
-{
-	printk("Running hook.\n");
-	sample_init_hook_count++;
-}
-DECLARE_HOOK(HOOK_INIT, sample_init_hook, HOOK_PRIO_DEFAULT);
-
-/**
- * @brief Test EC App main runs hooks of type HOOK_INIT.
- *
- * This test installs a hook, runs main and verifies that the hook ran.
- *
- */
-static void test_hook_notify_init(void)
-{
-	sample_init_hook_count = 0;
-	ec_app_main();
-	zassert_equal(1, sample_init_hook_count,
-		      "Expected sample_init_hook to run once.");
-}
-#else
-static void test_hook_notify_init(void)
-{
-	ztest_test_skip();
-}
-#endif
-
-static void test_start_ec_tasks(void)
-{
-#ifdef CONFIG_SHIMMED_TASKS
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
-}
-
-void test_main(void)
-{
-	ztest_test_suite(ec_app_tests, ztest_unit_test(test_init_reset_log),
-			 ztest_unit_test(test_lpc_init_mask),
-			 ztest_unit_test(test_keyboard_scan_init),
-			 ztest_unit_test(test_button_init),
-			 ztest_unit_test(test_setup_espi),
-			 ztest_unit_test(test_watchdog_init),
-			 ztest_unit_test(test_vboot_main),
-			 ztest_unit_test(test_hook_notify_init),
-			 ztest_unit_test(test_start_ec_tasks));
-
-	ztest_run_test_suite(ec_app_tests);
-}
diff --git a/zephyr/test/ec_app/zmake.yaml b/zephyr/test/ec_app/zmake.yaml
deleted file mode 100644
index decc749ae1..0000000000
--- a/zephyr/test/ec_app/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/test/hooks/CMakeLists.txt b/zephyr/test/hooks/CMakeLists.txt
deleted file mode 100644
index 81ff57d69d..0000000000
--- a/zephyr/test/hooks/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(hooks)
-
-target_sources(app PRIVATE hooks.c)
diff --git a/zephyr/test/hooks/hooks.c b/zephyr/test/hooks/hooks.c
deleted file mode 100644
index a9e0982e46..0000000000
--- a/zephyr/test/hooks/hooks.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdbool.h>
-#include <ztest.h>
-
-#include "hooks.h"
-
-static bool h1_called;
-static bool h2_called;
-static bool h3_called;
-
-static void h1(void)
-{
-	zassert_false(h1_called, "h1 was called, but should not have been");
-	zassert_false(h2_called, "h2 was called, but should not have been");
-	zassert_false(h3_called, "h3 was called, but should not have been");
-	h1_called = true;
-}
-DECLARE_HOOK(HOOK_TEST_1, h1, HOOK_PRIO_FIRST);
-
-static void h2(void)
-{
-	zassert_true(h1_called, "h1 was not called, but should have been");
-	zassert_false(h2_called, "h2 was called, but should not have been");
-	zassert_false(h3_called, "h3 was called, but should not have been");
-	h2_called = true;
-}
-DECLARE_HOOK(HOOK_TEST_1, h2, HOOK_PRIO_DEFAULT);
-
-static void h3(void)
-{
-	zassert_true(h1_called, "h1 was not called, but should have been");
-	zassert_true(h2_called, "h2 was not called, but should have been");
-	zassert_false(h3_called, "h3 was called, but should not have been");
-	h3_called = true;
-}
-DECLARE_HOOK(HOOK_TEST_1, h3, HOOK_PRIO_LAST);
-
-static void test_hook_list_multiple(void)
-{
-	hook_notify(HOOK_TEST_1);
-	zassert_true(h1_called, "h1 was not called, but should have been");
-	zassert_true(h2_called, "h2 was not called, but should have been");
-	zassert_true(h3_called, "h3 was not called, but should have been");
-}
-
-static bool h4_called;
-
-static void h4(void)
-{
-	zassert_false(h4_called, "h4 was called, but should not have been");
-	h4_called = true;
-}
-DECLARE_HOOK(HOOK_TEST_2, h4, HOOK_PRIO_DEFAULT);
-
-static void test_hook_list_single(void)
-{
-	hook_notify(HOOK_TEST_2);
-	zassert_true(h4_called, "h4 was not called, but should have been");
-}
-
-static void test_hook_list_empty(void)
-{
-	hook_notify(HOOK_TEST_3);
-}
-
-static bool deferred_func_called;
-
-#define DEFERRED_DELAY_US (500 * 1000)
-static void deferred_func(void)
-{
-	deferred_func_called = true;
-}
-DECLARE_DEFERRED(deferred_func);
-
-static void test_deferred_func(void)
-{
-	zassert_false(
-		deferred_func_called,
-		"The deferred function was called, but should not have been");
-	hook_call_deferred(&deferred_func_data, DEFERRED_DELAY_US);
-	zassert_false(
-		deferred_func_called,
-		"The deferred function was called, but should not have been");
-	k_usleep(DEFERRED_DELAY_US * 2);
-	zassert_true(
-		deferred_func_called,
-		"The deferred function was not called, but should have been");
-}
-
-static bool deferred_func_2_called;
-
-static void deferred_func_2(void)
-{
-	deferred_func_2_called = true;
-}
-DECLARE_DEFERRED(deferred_func_2);
-
-/*
- * Test that repeated calls to hook_call_deferred result in the
- * function being pushed out.
- */
-static void test_deferred_func_push_out(void)
-{
-	zassert_false(
-		deferred_func_2_called,
-		"The deferred function was called, but should not have been");
-	hook_call_deferred(&deferred_func_2_data, DEFERRED_DELAY_US);
-	hook_call_deferred(&deferred_func_2_data, DEFERRED_DELAY_US * 3);
-	k_usleep(DEFERRED_DELAY_US * 2);
-	zassert_false(
-		deferred_func_2_called,
-		"The deferred function was called, but should not have been");
-	k_usleep(DEFERRED_DELAY_US * 2);
-	zassert_true(
-		deferred_func_called,
-		"The deferred function was not called, but should have been");
-}
-
-static bool deferred_func_3_called;
-
-static void deferred_func_3(void)
-{
-	deferred_func_3_called = true;
-}
-DECLARE_DEFERRED(deferred_func_3);
-
-static void test_deferred_func_cancel(void)
-{
-	zassert_false(
-		deferred_func_3_called,
-		"The deferred function was called, but should not have been");
-	hook_call_deferred(&deferred_func_3_data, DEFERRED_DELAY_US);
-	hook_call_deferred(&deferred_func_3_data, -1);
-	k_usleep(DEFERRED_DELAY_US * 2);
-	zassert_false(
-		deferred_func_3_called,
-		"The deferred function was called, but should not have been");
-}
-
-void test_main(void)
-{
-	ztest_test_suite(
-		hooks_tests,
-		ztest_unit_test(test_hook_list_multiple),
-		ztest_unit_test(test_hook_list_single),
-		ztest_unit_test(test_hook_list_empty),
-		ztest_unit_test(test_deferred_func),
-		ztest_unit_test(test_deferred_func_push_out),
-		ztest_unit_test(test_deferred_func_cancel));
-
-	ztest_run_test_suite(hooks_tests);
-}
diff --git a/zephyr/test/hooks/prj.conf b/zephyr/test/hooks/prj.conf
deleted file mode 100644
index c0c02e22ca..0000000000
--- a/zephyr/test/hooks/prj.conf
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_HOOKS=y
-CONFIG_CROS_EC=y
diff --git a/zephyr/test/hooks/zmake.yaml b/zephyr/test/hooks/zmake.yaml
deleted file mode 100644
index 6aa10c2661..0000000000
--- a/zephyr/test/hooks/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/test/i2c/CMakeLists.txt b/zephyr/test/i2c/CMakeLists.txt
deleted file mode 100644
index 214177013f..0000000000
--- a/zephyr/test/i2c/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(i2c)
-
-target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/i2c/overlay.dts b/zephyr/test/i2c/overlay.dts
deleted file mode 100644
index 2c56ee3b7a..0000000000
--- a/zephyr/test/i2c/overlay.dts
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-		accel-0 {
-			i2c-port = <&bmi_i2c>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL_0";
-		};
-	};
-};
-
-&i2c0 {
-	bmi_i2c: bmi@68 {
-		compatible = "bosch,bmi160";
-		reg = <0x68>;
-		label = "accel-i2c";
-	};
-};
diff --git a/zephyr/test/i2c/prj.conf b/zephyr/test/i2c/prj.conf
deleted file mode 100644
index 8023c0492b..0000000000
--- a/zephyr/test/i2c/prj.conf
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_LOG=y
-
-CONFIG_EMUL=y
-CONFIG_I2C=y
-CONFIG_I2C_EMUL=y
-CONFIG_BMI160=y
-CONFIG_EMUL_BMI160=y
-CONFIG_SENSOR=y
-CONFIG_BMI160_TRIGGER_NONE=y
-
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_I2C=y
-CONFIG_CROS_EC=y
-
-# TODO(b/173711210) figure out why SPI is required here when we're not using it.
-CONFIG_SPI=y
-CONFIG_SPI_EMUL=y
diff --git a/zephyr/test/i2c/src/main.c b/zephyr/test/i2c/src/main.c
deleted file mode 100644
index 064ce78816..0000000000
--- a/zephyr/test/i2c/src/main.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <devicetree.h>
-#include <ztest.h>
-
-#include "common.h"
-#include "i2c/i2c.h"
-
-/* Unused: required for shimming i2c. */
-void watchdog_reload(void)
-{
-}
-
-static void test_i2c_port_count(void)
-{
-	zassert_equal(NAMED_I2C(accel_0), 0,
-		      "accel_0 expected to be 0 but was %d",
-		      NAMED_I2C(accel_0));
-	zassert_equal(I2C_PORT_COUNT, 1,
-		      "I2C_PORT_COUNT expected to be 1 but was %d",
-		      I2C_PORT_COUNT);
-}
-
-/* Test case main entry. */
-void test_main(void)
-{
-	ztest_test_suite(test_i2c,
-			 ztest_user_unit_test(test_i2c_port_count));
-	ztest_run_test_suite(test_i2c);
-}
-
diff --git a/zephyr/test/i2c/zmake.yaml b/zephyr/test/i2c/zmake.yaml
deleted file mode 100644
index f5e794c0f8..0000000000
--- a/zephyr/test/i2c/zmake.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
-dts-overlays:
-  - overlay.dts
diff --git a/zephyr/test/i2c_dts/CMakeLists.txt b/zephyr/test/i2c_dts/CMakeLists.txt
deleted file mode 100644
index eea2834af1..0000000000
--- a/zephyr/test/i2c_dts/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(i2c_test)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/i2c_dts/overlay.dts b/zephyr/test/i2c_dts/overlay.dts
deleted file mode 100644
index 2c56ee3b7a..0000000000
--- a/zephyr/test/i2c_dts/overlay.dts
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-		accel-0 {
-			i2c-port = <&bmi_i2c>;
-			enum-name = "I2C_PORT_ACCEL";
-			label = "ACCEL_0";
-		};
-	};
-};
-
-&i2c0 {
-	bmi_i2c: bmi@68 {
-		compatible = "bosch,bmi160";
-		reg = <0x68>;
-		label = "accel-i2c";
-	};
-};
diff --git a/zephyr/test/i2c_dts/prj.conf b/zephyr/test/i2c_dts/prj.conf
deleted file mode 100644
index a08cdbb7fb..0000000000
--- a/zephyr/test/i2c_dts/prj.conf
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ZTEST=y
-CONFIG_LOG=y
-
-CONFIG_EMUL=y
-CONFIG_I2C=y
-CONFIG_I2C_EMUL=y
-CONFIG_BMI160=y
-CONFIG_EMUL_BMI160=y
-CONFIG_SENSOR=y
-CONFIG_BMI160_TRIGGER_NONE=y
-
-# TODO(b/173711210) figure out why SPI is required here when we're not using it.
-CONFIG_SPI=y
-CONFIG_SPI_EMUL=y
diff --git a/zephyr/test/i2c_dts/src/main.c b/zephyr/test/i2c_dts/src/main.c
deleted file mode 100644
index ccd58dde67..0000000000
--- a/zephyr/test/i2c_dts/src/main.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <devicetree.h>
-#include <ztest.h>
-
-static void test_i2c_get_device(void)
-{
-	const struct device *accel0 = DEVICE_DT_GET(
-			DT_PHANDLE(DT_PATH(named_i2c_ports, accel_0),
-				   i2c_port));
-	const struct device *bmi_i2c = DEVICE_DT_GET(
-			DT_NODELABEL(bmi_i2c));
-
-	zassert_not_null(accel0, "accel0 was NULL");
-	zassert_not_null(bmi_i2c, "bmi_i2c was NULL");
-	zassert_equal(accel0, bmi_i2c,
-		"named_i2c_ports/accel0 and bmi_i2c should resolve to the same device");
-}
-
-/* test case main entry */
-void test_main(void)
-{
-	ztest_test_suite(test_i2c_bindings,
-			 ztest_user_unit_test(test_i2c_get_device));
-	ztest_run_test_suite(test_i2c_bindings);
-}
diff --git a/zephyr/test/i2c_dts/zmake.yaml b/zephyr/test/i2c_dts/zmake.yaml
deleted file mode 100644
index c3fca2272e..0000000000
--- a/zephyr/test/i2c_dts/zmake.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-output-type: elf
-supported-toolchains:
-  - llvm
-  - host
-is-test: true
-dts-overlays:
-  - overlay.dts
diff --git a/zephyr/test/system/CMakeLists.txt b/zephyr/test/system/CMakeLists.txt
deleted file mode 100644
index f91786841e..0000000000
--- a/zephyr/test/system/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(system_test)
-
-target_sources(app PRIVATE test_system.c
-                           ${PLATFORM_EC}/zephyr/shim/src/system.c)
diff --git a/zephyr/test/system/overlay.dts b/zephyr/test/system/overlay.dts
deleted file mode 100644
index 37bac97680..0000000000
--- a/zephyr/test/system/overlay.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-bbram-regions {
-		compatible = "named-bbram-regions";
-		pd0 {
-			offset = <0x00>;
-			size = <0x01>;
-		};
-		pd1 {
-			offset = <0x01>;
-			size = <0x02>;
-		};
-		try_slot {
-			offset = <0x03>;
-			size = <0x04>;
-		};
-		pd2 {
-			offset = <0x07>;
-			size = <0x05>;
-		};
-		scratchpad {
-			offset = <0x0c>;
-			size = <0x04>;
-		};
-		saved-reset-flags {
-			offset = <0x10>;
-			size = <0x04>;
-		};
-	};
-};
diff --git a/zephyr/test/system/prj.conf b/zephyr/test/system/prj.conf
deleted file mode 100644
index 03357fa10f..0000000000
--- a/zephyr/test/system/prj.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ZTEST=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
-CONFIG_LOG=y
diff --git a/zephyr/test/system/test_system.c b/zephyr/test/system/test_system.c
deleted file mode 100644
index e8eba44fc8..0000000000
--- a/zephyr/test/system/test_system.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <device.h>
-#include <drivers/bbram.h>
-#include <logging/log.h>
-#include <ztest.h>
-
-#include "bbram.h"
-#include "system.h"
-
-LOG_MODULE_REGISTER(test);
-
-#define BBRAM_REGION_OFF(name) \
-	DT_PROP(DT_PATH(named_bbram_regions, name), offset)
-#define BBRAM_REGION_SIZE(name) \
-	DT_PROP(DT_PATH(named_bbram_regions, name), size)
-
-static char mock_data[64] =
-	"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!@";
-
-static int mock_bbram_read(const struct device *unused, size_t offset,
-			   size_t size, uint8_t *data)
-{
-	if (offset < 0 || offset + size >= ARRAY_SIZE(mock_data))
-		return -1;
-	memcpy(data, mock_data + offset, size);
-	return EC_SUCCESS;
-}
-
-static const struct bbram_driver_api bbram_api = {
-	.read = mock_bbram_read,
-};
-
-static const struct device bbram_dev_instance = {
-	.name = "TEST_BBRAM_DEV",
-	.config = NULL,
-	.api = &bbram_api,
-	.data = NULL,
-};
-
-const struct device *bbram_dev = &bbram_dev_instance;
-
-static void test_bbram_get(void)
-{
-	uint8_t output[10];
-	int rc;
-
-	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD0, output);
-	zassert_equal(rc, 0, NULL);
-	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFF(pd0),
-			  BBRAM_REGION_SIZE(pd0), NULL);
-
-	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD1, output);
-	zassert_equal(rc, 0, NULL);
-	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFF(pd1),
-			  BBRAM_REGION_SIZE(pd1), NULL);
-
-	rc = system_get_bbram(SYSTEM_BBRAM_IDX_PD2, output);
-	zassert_equal(rc, 0, NULL);
-	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFF(pd2),
-			  BBRAM_REGION_SIZE(pd2), NULL);
-
-	rc = system_get_bbram(SYSTEM_BBRAM_IDX_TRY_SLOT, output);
-	zassert_equal(rc, 0, NULL);
-	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFF(try_slot),
-			  BBRAM_REGION_SIZE(try_slot), NULL);
-}
-
-void test_main(void)
-{
-	ztest_test_suite(system, ztest_unit_test(test_bbram_get));
-	ztest_run_test_suite(system);
-}
diff --git a/zephyr/test/system/zmake.yaml b/zephyr/test/system/zmake.yaml
deleted file mode 100644
index c3fca2272e..0000000000
--- a/zephyr/test/system/zmake.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-output-type: elf
-supported-toolchains:
-  - llvm
-  - host
-is-test: true
-dts-overlays:
-  - overlay.dts
diff --git a/zephyr/test/tasks/CMakeLists.txt b/zephyr/test/tasks/CMakeLists.txt
deleted file mode 100644
index f5ea76e67e..0000000000
--- a/zephyr/test/tasks/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(tasks)
-
-# Include the local test directory for shimmed_test_tasks.h
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-
-target_sources(app PRIVATE
-	main.c
-	"${CMAKE_CURRENT_SOURCE_DIR}/../../shim/src/tasks.c")
\ No newline at end of file
diff --git a/zephyr/test/tasks/main.c b/zephyr/test/tasks/main.c
deleted file mode 100644
index 91216b9518..0000000000
--- a/zephyr/test/tasks/main.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <kernel.h>
-#include <stdbool.h>
-#include <ztest.h>
-
-#include "ec_tasks.h"
-#include "task.h"
-#include "timer.h"
-
-/* Second for platform/ec task API (in microseconds). */
-#define TASK_SEC(s) (s * 1000 * 1000)
-
-K_SEM_DEFINE(task_done1, 0, 1);
-K_SEM_DEFINE(task_done2, 0, 1);
-K_SEM_DEFINE(test_ready1, 0, 1);
-K_SEM_DEFINE(test_ready2, 0, 1);
-
-static void (*task1)(void);
-static void (*task2)(void);
-
-static void run_test(void (*task1_run)(void), void (*task2_run)(void))
-{
-	task1 = task1_run;
-	task2 = task2_run;
-	k_sem_give(&test_ready1);
-	k_sem_give(&test_ready2);
-	k_sem_take(&task_done1, K_FOREVER);
-	k_sem_take(&task_done2, K_FOREVER);
-}
-
-void task1_entry(void *p)
-{
-	while (1) {
-		k_sem_take(&test_ready1, K_FOREVER);
-		task1();
-		k_sem_give(&task_done1);
-	}
-}
-
-void task2_entry(void *p)
-{
-	while (1) {
-		k_sem_take(&test_ready2, K_FOREVER);
-		task2();
-		k_sem_give(&task_done2);
-	}
-}
-
-/*
- * Unlike Tasks 1 & 2, it is allowed to run Task 3 more than once per
- * call to run_test().  It will call task3_entry_func if set, and wait
- * for the next event.  This is useful to test things like timers,
- * which you are expecting the event to fire at some point in the
- * future, and you want to test that it happens.
- */
-static void (*task3_entry_func)(uint32_t event_mask);
-
-void task3_entry(void *p)
-{
-	uint32_t events = 0;
-
-	for (;;) {
-		if (task3_entry_func)
-			task3_entry_func(events);
-		events = task_wait_event(-1);
-	}
-}
-
-static void set_event_before_task_start1(void)
-{
-	const uint32_t events = task_wait_event(TASK_SEC(2));
-
-	zassert_equal(events, 0xAAAA, "Should have 0xAAAA events");
-}
-
-static void set_event_before_task_start2(void)
-{
-	/* Do nothing */
-}
-
-static void test_set_event_before_task_start(void)
-{
-	/* Send event before tasks start */
-	task_set_event(TASK_ID_TASK_1, 0xAAAA);
-
-	start_ec_tasks();
-
-	run_test(set_event_before_task_start1, set_event_before_task_start2);
-}
-
-static void task_get_current1(void)
-{
-	zassert_equal(task_get_current(), TASK_ID_TASK_1, "ID matches");
-}
-
-static void task_get_current2(void)
-{
-	zassert_equal(task_get_current(), TASK_ID_TASK_2, "ID matches");
-}
-
-static void test_task_get_current(void)
-{
-	run_test(&task_get_current1, &task_get_current2);
-}
-
-
-static void timeout1(void)
-{
-	const uint32_t start_ms = k_uptime_get();
-	const uint32_t events = task_wait_event(TASK_SEC(2));
-	const uint32_t end_ms = k_uptime_get();
-
-	zassert_equal(events, TASK_EVENT_TIMER, "Should have timeout event");
-	zassert_within(end_ms - start_ms, 2000, 100, "Timeout for 2 seconds");
-}
-
-static void timeout2(void)
-{
-	/* Do nothing */
-}
-
-static void test_timeout(void)
-{
-	run_test(&timeout1, &timeout2);
-}
-
-/*
- * Timer test:
- *   1. Task 1 arms a timer for Task 3 in expiring 2 seconds.
- *   2. Task 2 does nothing.
- *   3. Task 3 validates that the it receives a TASK_EVENT_TIMER event
- *      2 seconds after Task 1 armed the timer (within 100ms
- *      tolerance).
- */
-static timestamp_t timer_armed_at;
-K_SEM_DEFINE(check_timer_finished, 0, 1);
-
-static void check_timer(uint32_t event_mask)
-{
-	timestamp_t now = get_time();
-
-	zassert_equal(event_mask & TASK_EVENT_TIMER, TASK_EVENT_TIMER,
-		      "Timer event mask should be set");
-	zassert_within(now.val - timer_armed_at.val, TASK_SEC(2),
-		       TASK_SEC(1) / 10,
-		       "Timer should expire at 2 seconds from arm time");
-	k_sem_give(&check_timer_finished);
-}
-
-static void timer_task_1(void)
-{
-	timestamp_t timer_timeout;
-
-	timer_armed_at = get_time();
-
-	timer_timeout.val = timer_armed_at.val + TASK_SEC(2);
-
-	task3_entry_func = check_timer;
-	zassert_equal(timer_arm(timer_timeout, TASK_ID_TASK_3), EC_SUCCESS,
-		      "Setting timer should succeed");
-}
-
-static void timer_task_2(void)
-{
-	/* Do nothing */
-}
-
-static void test_timer(void)
-{
-	run_test(timer_task_1, timer_task_2);
-	zassert_equal(k_sem_take(&check_timer_finished, K_SECONDS(4 * 1000)), 0,
-		      "Task 3 did not finish within timeout");
-	zassert_equal(task3_entry_func, check_timer,
-		      "check_timer should have been enabled");
-	task3_entry_func = NULL;
-}
-
-static void event_delivered1(void)
-{
-	const uint32_t start_ms = k_uptime_get();
-	const uint32_t events = task_wait_event(-1);
-	const uint32_t end_ms = k_uptime_get();
-
-	zassert_equal(events, 0x1234, "Verify event bits");
-	zassert_within(end_ms - start_ms, 5000, 100, "Waited for 5 seconds");
-}
-
-static void event_delivered2(void)
-{
-	k_sleep(K_SECONDS(5));
-
-	task_set_event(TASK_ID_TASK_1, 0x1234);
-}
-
-static void test_event_delivered(void)
-{
-	run_test(&event_delivered1, &event_delivered2);
-}
-
-
-static void event_mask_not_delivered1(void)
-{
-	task_set_event(TASK_ID_TASK_2, 0x007F);
-}
-
-static void event_mask_not_delivered2(void)
-{
-	const uint32_t start_ms = k_uptime_get();
-	const uint32_t events = task_wait_event_mask(0x0080, TASK_SEC(7));
-	const uint32_t end_ms = k_uptime_get();
-
-	zassert_equal(events, TASK_EVENT_TIMER, "Should have timeout event");
-	zassert_within(end_ms - start_ms, 7000, 100, "Timeout for 7 seconds");
-
-	const uint32_t leftover_events = task_wait_event(0);
-
-	zassert_equal(leftover_events, 0x007F, "All events should be waiting");
-}
-
-static void test_event_mask_not_delivered(void)
-{
-	run_test(&event_mask_not_delivered1, &event_mask_not_delivered2);
-}
-
-
-static void event_mask_extra1(void)
-{
-	k_sleep(K_SECONDS(1));
-
-	task_set_event(TASK_ID_TASK_2, 0x00FF);
-}
-
-static void event_mask_extra2(void)
-{
-	const uint32_t start_ms = k_uptime_get();
-	const uint32_t events = task_wait_event_mask(0x0001, TASK_SEC(10));
-	const uint32_t end_ms = k_uptime_get();
-
-	zassert_equal(events, 0x0001, "Verify only waited for event");
-	zassert_within(end_ms - start_ms, 1000, 100, "Timeout for 1 second");
-
-	const uint32_t leftover_events = task_wait_event(0);
-
-	zassert_equal(leftover_events, 0x00FE, "All events should be waiting");
-}
-
-static void test_event_mask_extra(void)
-{
-	run_test(&event_mask_extra1, &event_mask_extra2);
-}
-
-
-static void empty_set_mask1(void)
-{
-	k_sleep(K_SECONDS(1));
-	/*
-	 * It is generally invalid to set a 0 event, but this simulates a race
-	 * condition and exercises fallback code in task_wait_event
-	 */
-	task_set_event(TASK_ID_TASK_2, 0);
-	k_sleep(K_SECONDS(1));
-	task_set_event(TASK_ID_TASK_2, 0x1234);
-}
-
-static void empty_set_mask2(void)
-{
-	const uint32_t start_ms = k_uptime_get();
-	const uint32_t events = task_wait_event_mask(0x1234, TASK_SEC(10));
-	const uint32_t end_ms = k_uptime_get();
-
-	zassert_equal(events, 0x1234, "Verify only waited for event");
-	zassert_within(end_ms - start_ms, 2000, 100, "Timeout for 2 seconds");
-}
-
-static void test_empty_set_mask(void)
-{
-	run_test(&empty_set_mask1, &empty_set_mask2);
-}
-
-
-void test_main(void)
-{
-	/* Note that test_set_event_before_task_start calls start_ec_tasks */
-	ztest_test_suite(test_task_shim,
-			 ztest_unit_test(test_set_event_before_task_start),
-			 ztest_unit_test(test_task_get_current),
-			 ztest_unit_test(test_timeout),
-			 ztest_unit_test(test_timer),
-			 ztest_unit_test(test_event_delivered),
-			 ztest_unit_test(test_event_mask_not_delivered),
-			 ztest_unit_test(test_event_mask_extra),
-			 ztest_unit_test(test_empty_set_mask));
-	ztest_run_test_suite(test_task_shim);
-}
diff --git a/zephyr/test/tasks/prj.conf b/zephyr/test/tasks/prj.conf
deleted file mode 100644
index f5ddf014a7..0000000000
--- a/zephyr/test/tasks/prj.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_ZTEST=y
-CONFIG_HAS_TEST_TASKS=y
-CONFIG_PLATFORM_EC=y
-CONFIG_CROS_EC=y
-CONFIG_HAS_TASK_HOOKS=n
diff --git a/zephyr/test/tasks/shimmed_test_tasks.h b/zephyr/test/tasks/shimmed_test_tasks.h
deleted file mode 100644
index b7d72b59d5..0000000000
--- a/zephyr/test/tasks/shimmed_test_tasks.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_SHIMMED_TEST_TASKS_H
-#define __CROS_EC_SHIMMED_TEST_TASKS_H
-
-/*
- * Manually define these HAS_TASK_* defines. There is a build time assert
- * to at least verify we have the minimum set defined correctly. */
-#define HAS_TASK_TASK_1 1
-#define HAS_TASK_TASK_2 1
-#define HAS_TASK_TASK_3 1
-
-/* Highest priority on bottom same as in platform/ec */
-#define CROS_EC_TASK_LIST \
-	CROS_EC_TASK(TASK_1, task1_entry, 0, 512) \
-	CROS_EC_TASK(TASK_2, task2_entry, 0, 512) \
-	CROS_EC_TASK(TASK_3, task3_entry, 0, 512)
-
-#endif /* __CROS_EC_SHIMMED_TEST_TASKS_H */
diff --git a/zephyr/test/tasks/zmake.yaml b/zephyr/test/tasks/zmake.yaml
deleted file mode 100644
index 6aa10c2661..0000000000
--- a/zephyr/test/tasks/zmake.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-board: native_posix
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - llvm
-  - host
-output-type: elf
-is-test: true
diff --git a/zephyr/zmake/.flake8 b/zephyr/zmake/.flake8
deleted file mode 100644
index 0a0a9c29ab..0000000000
--- a/zephyr/zmake/.flake8
+++ /dev/null
@@ -1,9 +0,0 @@
-[flake8]
-max-line-length = 88
-extend-ignore = E203
-exclude =
-    .hypothesis,
-    .pytest_cache,
-    __pycache__,
-    build,
-    dist
diff --git a/zephyr/zmake/.isort.cfg b/zephyr/zmake/.isort.cfg
deleted file mode 100644
index b9fb3f3e8c..0000000000
--- a/zephyr/zmake/.isort.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-[settings]
-profile=black
diff --git a/zephyr/zmake/run_tests.sh b/zephyr/zmake/run_tests.sh
deleted file mode 100755
index 60e93cdf1a..0000000000
--- a/zephyr/zmake/run_tests.sh
+++ /dev/null
@@ -1,35 +0,0 @@
-#!/bin/bash
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Run tests for zmake itself (not including Zephyr builds).
-
-# Show commands being run.
-set -x
-
-# Exit if any command exits non-zero.
-set -e
-
-# cd to the directory containing this script.
-cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"
-
-# Test the copy in-tree, instead of what setuptools or the ebuild
-# installed.
-export PYTHONPATH="${PWD}"
-
-# Run pytest.
-# TODO(jrosenth): --hypothesis-profile=cq is very likely to be
-# unnecessary, as this was only needed when we were heavily taxing the
-# CPU by running pytest alongside all the ninjas, which no longer
-# happens.  Remove this flag.
-pytest --hypothesis-profile=cq .
-
-# Check import sorting.
-isort --check .
-
-# Check black formatting.
-black --check --diff .
-
-# Check flake8 reports no issues.
-flake8 .
diff --git a/zephyr/zmake/setup.py b/zephyr/zmake/setup.py
deleted file mode 100644
index 4328dc48d7..0000000000
--- a/zephyr/zmake/setup.py
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import setuptools
-
-setuptools.setup(
-    name="zephyr-chrome-utils",
-    version="0.1",
-    description="CrOS Zephyr Utilities",
-    long_description="Utilities used for working on a Zephyr-based EC",
-    url="https://chromium.googlesource.com/chromiumos/platform/ec",
-    author="Chromium OS Authors",
-    author_email="chromiumos-dev@chromium.org",
-    license="BSD",
-    # What does your project relate to?
-    keywords="chromeos",
-    # You can just specify the packages manually here if your project is
-    # simple. Or you can use find_packages().
-    packages=["zmake"],
-    python_requires=">=3.6, <4",
-    # List run-time dependencies here.  These will be installed by pip when
-    # your project is installed. For an analysis of "install_requires" vs pip's
-    # requirements files see:
-    # https://packaging.python.org/en/latest/requirements.html
-    install_requires=[
-        "jsonschema>=3.2.0",
-        "pyyaml>=3.13",
-    ],
-    # To provide executable scripts, use entry points in preference to the
-    # "scripts" keyword. Entry points provide cross-platform support and allow
-    # pip to create the appropriate form of executable for the target platform.
-    entry_points={
-        "console_scripts": [
-            "zmake=zmake.__main__:main",
-        ],
-    },
-)
diff --git a/zephyr/zmake/tests/conftest.py b/zephyr/zmake/tests/conftest.py
deleted file mode 100644
index 4572e23ffe..0000000000
--- a/zephyr/zmake/tests/conftest.py
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import hypothesis
-
-hypothesis.settings.register_profile(
-    "cq", suppress_health_check=hypothesis.HealthCheck.all()
-)
diff --git a/zephyr/zmake/tests/files/sample_err.txt b/zephyr/zmake/tests/files/sample_err.txt
deleted file mode 100644
index d627885a6f..0000000000
--- a/zephyr/zmake/tests/files/sample_err.txt
+++ /dev/null
@@ -1,321 +0,0 @@
-Building /tmp/z/vol:ro: /usr/bin/ninja -C /tmp/z/vol/build-ro
-Running /usr/bin/ninja -C /tmp/z/vol/build-ro
-ninja: Entering directory `/tmp/z/vol/build-ro'
-devicetree error: 'adc' is marked as required in 'properties:' in /home/sjg/c/src/platform/ec/zephyr/dts/bindings/temp/temp-3v3-30k9-47k-4050b.yaml, but does not appear in <Node /named-temp-sensors/ddr_soc in 'volteer.dts.pre.tmp'>
-[1/310] Preparing syscall dependency handling
-[2/310] Generating misc/generated/syscalls_subdirs.trigger
-[3/310] Generating ../../ec/include/generated/ec_version.h
-[4/310] Generating misc/generated/syscalls.json, misc/generated/struct_tags.json
-[5/310] Generating include/generated/syscall_dispatch.c, include/generated/syscall_list.h
-[6/310] Generating include/generated/kobj-types-enum.h, include/generated/otype-to-str.h
-[7/310] Generating include/generated/driver-validation.h
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-[9/310] Generating include/generated/offsets.h
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diff --git a/zephyr/zmake/tests/test_build_config.py b/zephyr/zmake/tests/test_build_config.py
deleted file mode 100644
index bf69b8a1fa..0000000000
--- a/zephyr/zmake/tests/test_build_config.py
+++ /dev/null
@@ -1,202 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import argparse
-import os
-import pathlib
-import string
-import tempfile
-
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
-import zmake.jobserver
-import zmake.util as util
-from zmake.build_config import BuildConfig
-
-# Strategies for use with hypothesis
-filenames = st.text(
-    alphabet=set(string.printable) - {"/", ";"}, min_size=1, max_size=254
-).filter(lambda name: name not in (".", ".."))
-paths = st.builds(
-    lambda parts: pathlib.Path("/", *parts), st.iterables(filenames, min_size=1)
-)
-config_keys = st.text(alphabet=set(string.ascii_uppercase) | {"_"}, min_size=1)
-config_values = st.builds(str, st.just("y") | st.just("n") | st.integers())
-config_dicts = st.dictionaries(keys=config_keys, values=config_values)
-config_dicts_at_least_one_entry = st.dictionaries(
-    keys=config_keys, values=config_values, min_size=1
-)
-
-build_configs = st.builds(
-    BuildConfig,
-    environ_defs=config_dicts,
-    cmake_defs=config_dicts,
-    kconfig_defs=config_dicts,
-    kconfig_files=st.lists(paths),
-)
-build_configs_no_kconfig = st.builds(
-    BuildConfig, environ_defs=config_dicts, cmake_defs=config_dicts
-)
-build_configs_with_at_least_one_kconfig = st.builds(
-    BuildConfig,
-    environ_defs=config_dicts,
-    cmake_defs=config_dicts,
-    kconfig_defs=config_dicts_at_least_one_entry,
-)
-
-
-@hypothesis.given(st.data(), build_configs)
-def test_merge(coins, combined):
-    """Test that when splitting a config in half and merging the two
-    halves, we get the original config back.
-    """
-
-    def split(iterable):
-        left = []
-        right = []
-        bools = st.booleans()
-        for item in iterable:
-            if coins.draw(bools):
-                left.append(item)
-            else:
-                right.append(item)
-        return left, right
-
-    # Split the original config into two
-    env1, env2 = split(combined.environ_defs.items())
-    cmake1, cmake2 = split(combined.cmake_defs.items())
-    kconf1, kconf2 = split(combined.kconfig_defs.items())
-    files1, files2 = split(combined.kconfig_files)
-
-    c1 = BuildConfig(
-        environ_defs=dict(env1),
-        cmake_defs=dict(cmake1),
-        kconfig_defs=dict(kconf1),
-        kconfig_files=files1,
-    )
-    c2 = BuildConfig(
-        environ_defs=dict(env2),
-        cmake_defs=dict(cmake2),
-        kconfig_defs=dict(kconf2),
-        kconfig_files=files2,
-    )
-
-    # Merge the split configs
-    merged = c1 | c2
-
-    # Assert that the merged split configs is the original config
-    assert merged.environ_defs == combined.environ_defs
-    assert merged.cmake_defs == combined.cmake_defs
-    assert merged.kconfig_defs == combined.kconfig_defs
-    assert set(merged.kconfig_files) == set(combined.kconfig_files)
-
-
-class FakeJobClient(zmake.jobserver.JobClient):
-    """Simple job client to capture argv/environ."""
-
-    def __init__(self):
-        self.captured_argv = []
-        self.captured_env = {}
-
-    def get_job(self):
-        return zmake.jobserver.JobHandle(lambda: None)
-
-    def popen(self, argv, env={}, **kwargs):
-        self.captured_argv = [str(arg) for arg in argv]
-        self.captured_env = {str(k): str(v) for k, v in env.items()}
-
-
-def parse_cmake_args(argv):
-    """Parse command line arguments like cmake does.
-
-    This is an intenionally minimal implementation, which only
-    understands the subset of arguments actually used by zmake.
-
-    Args:
-        argv: The argument list.
-
-    Returns:
-        A 2-tuple of a namespace from argparse and the corresponding
-        parsed Cmake definitions.
-    """
-    assert argv[0] == "/usr/bin/cmake"
-
-    parser = argparse.ArgumentParser(add_help=False)
-    parser.add_argument("-S", dest="source_dir", type=pathlib.Path)
-    parser.add_argument("-B", dest="build_dir", type=pathlib.Path)
-    parser.add_argument("-G", dest="generator")
-    parser.add_argument("-D", dest="defs", action="append", default=[])
-    args = parser.parse_args(argv[1:])
-
-    # Build the definition dictionary
-    cmake_defs = {}
-    for defn in args.defs:
-        key, sep, val = defn.partition("=")
-        if not sep:
-            val = "1"
-        assert key not in cmake_defs
-        cmake_defs[key] = val
-
-    return args, cmake_defs
-
-
-@hypothesis.given(build_configs_no_kconfig, paths, paths)
-@hypothesis.settings(deadline=60000)
-def test_popen_cmake_no_kconfig(conf, project_dir, build_dir):
-    """Test popen_cmake for a config with no kconfig definitions."""
-    job_client = FakeJobClient()
-    conf.popen_cmake(job_client, project_dir, build_dir)
-
-    args, cmake_defs = parse_cmake_args(job_client.captured_argv)
-
-    assert cmake_defs == conf.cmake_defs
-    assert job_client.captured_env == conf.environ_defs
-
-
-@hypothesis.given(build_configs_with_at_least_one_kconfig, paths, paths)
-@hypothesis.settings(deadline=60000)
-def test_popen_cmake_kconfig_but_no_file(conf, project_dir, build_dir):
-    """Test that running popen_cmake with Kconfig definitions to write
-    out, but no path to do so, should raise an error.
-    """
-    job_client = FakeJobClient()
-
-    with pytest.raises(ValueError):
-        conf.popen_cmake(job_client, project_dir, build_dir)
-
-
-@hypothesis.given(build_configs, paths, paths)
-@hypothesis.settings(deadline=60000)
-def test_popen_cmake_kconfig(conf, project_dir, build_dir):
-    job_client = FakeJobClient()
-
-    with tempfile.NamedTemporaryFile("w", delete=False) as f:
-        temp_path = f.name
-
-    try:
-        conf.popen_cmake(
-            job_client, project_dir, build_dir, kconfig_path=pathlib.Path(temp_path)
-        )
-
-        args, cmake_defs = parse_cmake_args(job_client.captured_argv)
-
-        expected_kconfig_files = set(str(f) for f in conf.kconfig_files)
-        expected_kconfig_files.add(temp_path)
-
-        if expected_kconfig_files:
-            kconfig_files = set(cmake_defs.pop("CONF_FILE").split(";"))
-        else:
-            assert "CONF_FILE" not in cmake_defs
-            kconfig_files = set()
-
-        assert cmake_defs == conf.cmake_defs
-        assert job_client.captured_env == conf.environ_defs
-        assert kconfig_files == expected_kconfig_files
-
-        kconfig_defs = util.read_kconfig_file(temp_path)
-        assert kconfig_defs == conf.kconfig_defs
-    finally:
-        os.unlink(temp_path)
diff --git a/zephyr/zmake/tests/test_modules.py b/zephyr/zmake/tests/test_modules.py
deleted file mode 100644
index 87e5d7bfc9..0000000000
--- a/zephyr/zmake/tests/test_modules.py
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import pathlib
-import tempfile
-
-import hypothesis
-import hypothesis.strategies as st
-
-import zmake.modules
-
-module_lists = st.lists(
-    st.one_of(*map(st.just, zmake.modules.known_modules)), unique=True
-)
-
-
-@hypothesis.given(module_lists)
-@hypothesis.settings(deadline=None)
-def test_locate_in_directory(modules):
-    """Test the basic functionality of locate_from_directory"""
-
-    with tempfile.TemporaryDirectory() as modules_dir:
-        modules_dir = pathlib.Path(modules_dir).resolve()
-
-        expected_modules = {}
-
-        for module in modules:
-            module_dir = modules_dir / module
-            zephyr_dir = module_dir / "zephyr"
-            zephyr_dir.mkdir(parents=True)
-
-            module_yml = zephyr_dir / "module.yml"
-            module_yml.write_bytes(b"")
-
-            expected_modules[module] = module_dir
-
-        assert zmake.modules.locate_from_directory(modules_dir) == expected_modules
diff --git a/zephyr/zmake/tests/test_multiproc_executor.py b/zephyr/zmake/tests/test_multiproc_executor.py
deleted file mode 100644
index ebc2be5e4f..0000000000
--- a/zephyr/zmake/tests/test_multiproc_executor.py
+++ /dev/null
@@ -1,52 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-import threading
-
-import zmake.multiproc
-
-
-def test_single_function_executor_success():
-    executor = zmake.multiproc.Executor()
-    executor.append(lambda: 0)
-    assert executor.wait() == 0
-
-
-def test_single_function_executor_fail():
-    executor = zmake.multiproc.Executor()
-    executor.append(lambda: -2)
-    assert executor.wait() == -2
-
-
-def test_single_function_executor_raise():
-    executor = zmake.multiproc.Executor()
-    executor.append(lambda: 1 / 0)
-    assert executor.wait() != 0
-
-
-def _lock_step(cv, predicate, step, return_value=0):
-    with cv:
-        cv.wait_for(predicate=lambda: step[0] == predicate)
-        step[0] += 1
-        cv.notify_all()
-    return return_value
-
-
-def test_two_function_executor_wait_for_both():
-    cv = threading.Condition()
-    step = [0]
-    executor = zmake.multiproc.Executor()
-    executor.append(lambda: _lock_step(cv=cv, predicate=0, step=step))
-    executor.append(lambda: _lock_step(cv=cv, predicate=1, step=step))
-    assert executor.wait() == 0
-    assert step[0] == 2
-
-
-def test_two_function_executor_one_fails():
-    cv = threading.Condition()
-    step = [0]
-    executor = zmake.multiproc.Executor()
-    executor.append(lambda: _lock_step(cv=cv, predicate=0, step=step, return_value=-1))
-    executor.append(lambda: _lock_step(cv=cv, predicate=1, step=step))
-    assert executor.wait() == -1
-    assert step[0] == 2
diff --git a/zephyr/zmake/tests/test_multiproc_logging.py b/zephyr/zmake/tests/test_multiproc_logging.py
deleted file mode 100644
index 2eac9326d3..0000000000
--- a/zephyr/zmake/tests/test_multiproc_logging.py
+++ /dev/null
@@ -1,106 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-import io
-import logging
-import os
-import threading
-import unittest.mock as mock
-
-import zmake.multiproc
-
-
-def test_read_output_from_pipe():
-    semaphore = threading.Semaphore(0)
-    pipe = os.pipe()
-    fd = io.TextIOWrapper(os.fdopen(pipe[0], "rb"), encoding="utf-8")
-    logger = mock.Mock(spec=logging.Logger)
-    logger.log.side_effect = lambda log_lvl, line: semaphore.release()
-    zmake.multiproc.log_output(logger, logging.DEBUG, fd, job_id="")
-    os.write(pipe[1], "Hello\n".encode("utf-8"))
-    semaphore.acquire()
-    logger.log.assert_called_with(logging.DEBUG, "Hello")
-
-
-def test_read_output_change_log_level():
-    semaphore = threading.Semaphore(0)
-    pipe = os.pipe()
-    fd = io.TextIOWrapper(os.fdopen(pipe[0], "rb"), encoding="utf-8")
-    logger = mock.Mock(spec=logging.Logger)
-    logger.log.side_effect = lambda log_lvl, line: semaphore.release()
-    # This call will log output from fd (the file descriptor) to DEBUG, though
-    # when the line starts with 'World', the logging level will be switched to
-    # CRITICAL (see the content of the log_lvl_override_func).
-    zmake.multiproc.log_output(
-        logger=logger,
-        log_level=logging.DEBUG,
-        file_descriptor=fd,
-        log_level_override_func=lambda line, lvl: logging.CRITICAL
-        if line.startswith("World")
-        else lvl,
-        job_id="",
-    )
-    os.write(pipe[1], "Hello\n".encode("utf-8"))
-    semaphore.acquire()
-    os.write(pipe[1], "World\n".encode("utf-8"))
-    semaphore.acquire()
-    os.write(pipe[1], "Bye\n".encode("utf-8"))
-    semaphore.acquire()
-    logger.log.assert_has_calls(
-        [
-            mock.call(logging.DEBUG, "Hello"),
-            mock.call(logging.CRITICAL, "World"),
-            mock.call(logging.CRITICAL, "Bye"),
-        ]
-    )
-
-
-def test_read_output_from_second_pipe():
-    """Test that we can read from more than one pipe.
-
-    This is particularly important since we will block on a read/select once we
-    have a file descriptor. It is important that we break from the select and
-    start it again with the updated list when a new one is added.
-    """
-    semaphore = threading.Semaphore(0)
-    pipes = [os.pipe(), os.pipe()]
-    fds = [
-        io.TextIOWrapper(os.fdopen(pipes[0][0], "rb"), encoding="utf-8"),
-        io.TextIOWrapper(os.fdopen(pipes[1][0], "rb"), encoding="utf-8"),
-    ]
-
-    logger = mock.Mock(spec=logging.Logger)
-    logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
-
-    zmake.multiproc.log_output(logger, logging.DEBUG, fds[0], job_id="0")
-    zmake.multiproc.log_output(logger, logging.ERROR, fds[1], job_id="1")
-
-    os.write(pipes[1][1], "Hello\n".encode("utf-8"))
-    semaphore.acquire()
-    logger.log.assert_called_with(logging.ERROR, "[%s]%s", "1", "Hello")
-
-
-def test_read_output_after_another_pipe_closed():
-    """Test processing output from a pipe after closing another.
-
-    Since we don't want to complicate the API. File descriptors are
-    automatically pruned away when closed. Make sure that the other descriptors
-    remain functional when that happens.
-    """
-    semaphore = threading.Semaphore(0)
-    pipes = [os.pipe(), os.pipe()]
-    fds = [
-        io.TextIOWrapper(os.fdopen(pipes[0][0], "rb"), encoding="utf-8"),
-        io.TextIOWrapper(os.fdopen(pipes[1][0], "rb"), encoding="utf-8"),
-    ]
-
-    logger = mock.Mock(spec=logging.Logger)
-    logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
-
-    zmake.multiproc.log_output(logger, logging.DEBUG, fds[0], job_id="0")
-    zmake.multiproc.log_output(logger, logging.ERROR, fds[1], job_id="1")
-
-    fds[0].close()
-    os.write(pipes[1][1], "Hello\n".encode("utf-8"))
-    semaphore.acquire()
-    logger.log.assert_called_with(logging.ERROR, "[%s]%s", "1", "Hello")
diff --git a/zephyr/zmake/tests/test_packers.py b/zephyr/zmake/tests/test_packers.py
deleted file mode 100644
index 1709c68098..0000000000
--- a/zephyr/zmake/tests/test_packers.py
+++ /dev/null
@@ -1,57 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import pathlib
-import tempfile
-import unittest.mock as mock
-
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
-import zmake.output_packers as packers
-
-# Strategies for use with hypothesis
-absolute_path = st.from_regex(regex=r"\A/[\w/]*\Z")
-
-
-@hypothesis.given(absolute_path)
-@hypothesis.settings(deadline=60000)
-def test_file_size_unbounded(path):
-    packer = packers.BasePacker(project=None)
-    packer._is_size_bound = mock.Mock(name="_is_size_bound", return_value=False)
-    file = pathlib.Path(path) / "zephyr.bin"
-    assert packer._check_packed_file_size(file=file, dirs={}) == file
-    packer._is_size_bound.assert_called_once_with(file)
-
-
-@hypothesis.given(st.binary(min_size=5, max_size=100))
-@hypothesis.settings(deadline=60000)
-def test_file_size_in_bounds(data):
-    packer = packers.BasePacker(project=None)
-    packer._is_size_bound = mock.Mock(name="_is_size_bound", return_value=True)
-    packer._get_max_image_bytes = mock.Mock(
-        name="_get_max_image_bytes", return_value=100
-    )
-    with tempfile.TemporaryDirectory() as temp_dir_name:
-        file = pathlib.Path(temp_dir_name) / "zephyr.bin"
-        with open(file, "wb") as f:
-            f.write(data)
-        assert packer._check_packed_file_size(file=file, dirs={}) == file
-
-
-@hypothesis.given(st.binary(min_size=101, max_size=200))
-@hypothesis.settings(deadline=60000)
-def test_file_size_out_of_bounds(data):
-    packer = packers.BasePacker(project=None)
-    packer._is_size_bound = mock.Mock(name="_is_size_bound", return_value=True)
-    packer._get_max_image_bytes = mock.Mock(
-        name="_get_max_image_bytes", return_value=100
-    )
-    with tempfile.TemporaryDirectory() as temp_dir_name:
-        file = pathlib.Path(temp_dir_name) / "zephyr.bin"
-        with open(file, "wb") as f:
-            f.write(data)
-        with pytest.raises(RuntimeError):
-            packer._check_packed_file_size(file=file, dirs={})
diff --git a/zephyr/zmake/tests/test_project.py b/zephyr/zmake/tests/test_project.py
deleted file mode 100644
index 2442ceedf6..0000000000
--- a/zephyr/zmake/tests/test_project.py
+++ /dev/null
@@ -1,173 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import pathlib
-import string
-import tempfile
-
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
-import zmake.modules
-import zmake.project
-
-board_names = st.text(alphabet=set(string.ascii_lowercase) | {"_"}, min_size=1)
-sets_of_board_names = st.lists(st.lists(board_names, unique=True))
-
-
-class TemporaryProject(tempfile.TemporaryDirectory):
-    """A temporary project wrapper.
-
-    Args:
-        config: The config dictionary to be used with the project.
-    """
-
-    def __init__(self, config):
-        self.config = config
-        super().__init__()
-
-    def __enter__(self):
-        project_path = pathlib.Path(super().__enter__())
-        return zmake.project.Project(project_path, config_dict=self.config)
-
-
-@hypothesis.given(sets_of_board_names)
-@hypothesis.settings(deadline=None)
-def test_find_dts_overlays(modules):
-    """Test the functionality of find_dts_overlays with multiple
-    modules, each with sets of board names."""
-
-    # Recursive function to wind up all the temporary directories and
-    # call the actual test.
-    def setup_modules_and_dispatch(modules, test_fn, module_list=()):
-        if modules:
-            boards = modules[0]
-            with tempfile.TemporaryDirectory() as modpath:
-                modpath = pathlib.Path(modpath)
-                for board in boards:
-                    dts_path = zmake.project.module_dts_overlay_name(modpath, board)
-                    dts_path.parent.mkdir(parents=True, exist_ok=True)
-                    dts_path.touch()
-                setup_modules_and_dispatch(
-                    modules[1:], test_fn, module_list=module_list + (modpath,)
-                )
-        else:
-            test_fn(module_list)
-
-    # The actual test case, once temp modules have been setup.
-    def testcase(module_paths):
-        # Maps board_name→overlay_files
-        board_file_mapping = {}
-        for modpath, board_list in zip(module_paths, modules):
-            for board in board_list:
-                file_name = zmake.project.module_dts_overlay_name(modpath, board)
-                files = board_file_mapping.get(board, set())
-                board_file_mapping[board] = files | {file_name}
-
-        for board, expected_dts_files in board_file_mapping.items():
-            with TemporaryProject(
-                {
-                    "board": board,
-                    "output-type": "elf",
-                    "supported-toolchains": ["llvm"],
-                    "supported-zephyr-versions": ["v2.6"],
-                }
-            ) as project:
-                config = project.find_dts_overlays(dict(enumerate(module_paths)))
-
-                actual_dts_files = set(
-                    config.cmake_defs.get("DTC_OVERLAY_FILE", "").split(";")
-                )
-
-                assert actual_dts_files == set(map(str, expected_dts_files))
-
-    setup_modules_and_dispatch(modules, testcase)
-
-
-module_lists = st.lists(
-    st.one_of(*map(st.just, zmake.modules.known_modules)), unique=True
-)
-
-
-@hypothesis.given(module_lists)
-@hypothesis.settings(deadline=None)
-def test_prune_modules(modules):
-    """Test the Project.prune_modules method in the usual case (all
-    modules available)."""
-    module_paths = {
-        name: pathlib.Path("/fake/module/path", name)
-        for name in zmake.modules.known_modules
-    }
-
-    with TemporaryProject(
-        {
-            "board": "native_posix",
-            "output-type": "elf",
-            "supported-toolchains": ["coreboot-sdk"],
-            "supported-zephyr-versions": ["v2.6"],
-            "modules": modules,
-        }
-    ) as project:
-        assert set(project.prune_modules(module_paths)) == set(modules)
-
-
-def test_prune_modules_unavailable():
-    """The Project.prune_modules method should raise a KeyError when
-    not all modules are available."""
-
-    # Missing 'cmsis'
-    module_paths = {
-        "hal_stm32": pathlib.Path("/mod/halstm"),
-    }
-
-    with TemporaryProject(
-        {
-            "board": "native_posix",
-            "output-type": "elf",
-            "supported-toolchains": ["coreboot-sdk"],
-            "supported-zephyr-versions": ["v2.6"],
-            "modules": ["hal_stm32", "cmsis"],
-        }
-    ) as project:
-        with pytest.raises(KeyError):
-            project.prune_modules(module_paths)
-
-
-def test_find_projects_empty(tmp_path):
-    """Test the find_projects method when there are no projects."""
-    projects = list(zmake.project.find_projects(tmp_path))
-    assert len(projects) == 0
-
-
-YAML_FILE = """
-supported-zephyr-versions:
-  - v2.6
-supported-toolchains:
-  - coreboot-sdk
-output-type: npcx
-"""
-
-
-def test_find_projects(tmp_path):
-    """Test the find_projects method when there are projects."""
-    dir = tmp_path.joinpath("one")
-    dir.mkdir()
-    dir.joinpath("zmake.yaml").write_text("board: one\n" + YAML_FILE)
-    tmp_path.joinpath("two").mkdir()
-    dir = tmp_path.joinpath("two/a")
-    dir.mkdir()
-    dir.joinpath("zmake.yaml").write_text("board: twoa\nis-test: true\n" + YAML_FILE)
-    dir = tmp_path.joinpath("two/b")
-    dir.mkdir()
-    dir.joinpath("zmake.yaml").write_text("board: twob\n" + YAML_FILE)
-    projects = list(zmake.project.find_projects(tmp_path))
-    projects.sort(key=lambda x: x.project_dir)
-    assert len(projects) == 3
-    assert projects[0].project_dir == tmp_path.joinpath("one")
-    assert projects[1].project_dir == tmp_path.joinpath("two/a")
-    assert projects[2].project_dir == tmp_path.joinpath("two/b")
-    assert not projects[0].config.is_test
-    assert projects[1].config.is_test
-    assert not projects[2].config.is_test
diff --git a/zephyr/zmake/tests/test_reexec.py b/zephyr/zmake/tests/test_reexec.py
deleted file mode 100644
index 9f25b5a834..0000000000
--- a/zephyr/zmake/tests/test_reexec.py
+++ /dev/null
@@ -1,59 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Test the zmake re-exec functionality."""
-
-import os
-import sys
-import unittest.mock as mock
-
-import pytest
-
-import zmake.__main__ as main
-
-
-@pytest.fixture
-def fake_env(monkeypatch):
-    environ = {}
-    monkeypatch.setattr(os, "environ", environ)
-    return environ
-
-
-@pytest.fixture
-def mock_execve():
-    with mock.patch("os.execve", autospec=True) as mocked_function:
-        yield mocked_function
-
-
-def test_out_of_chroot(fake_env, mock_execve):
-    # When CROS_WORKON_SRCROOT is not set, we should not re-exec.
-    main.maybe_reexec(["--help"])
-    mock_execve.assert_not_called()
-
-
-def test_pythonpath_set(fake_env, mock_execve):
-    # With PYTHONPATH set, we should not re-exec.
-    fake_env["CROS_WORKON_SRCROOT"] = "/mnt/host/source"
-    fake_env["PYTHONPATH"] = "/foo/bar/baz"
-    main.maybe_reexec(["--help"])
-    mock_execve.assert_not_called()
-
-
-def test_zmake_does_not_exist(fake_env, mock_execve):
-    # When zmake is not at src/platform/ec/zephyr/zmake, don't re-exec.
-    fake_env["CROS_WORKON_SRCROOT"] = "/this/does/not/exist"
-    main.maybe_reexec(["--help"])
-    mock_execve.assert_not_called()
-
-
-def test_zmake_reexec(fake_env, mock_execve):
-    # Nothing else applies?  The re-exec should happen.
-    fake_env["CROS_WORKON_SRCROOT"] = "/mnt/host/source"
-    main.maybe_reexec(["--help"])
-    new_env = dict(fake_env)
-    new_env["PYTHONPATH"] = "/mnt/host/source/src/platform/ec/zephyr/zmake"
-    mock_execve.assert_called_once_with(
-        sys.executable,
-        [sys.executable, "-m", "zmake", "--help"],
-        new_env,
-    )
diff --git a/zephyr/zmake/tests/test_toolchains.py b/zephyr/zmake/tests/test_toolchains.py
deleted file mode 100644
index 515f54a112..0000000000
--- a/zephyr/zmake/tests/test_toolchains.py
+++ /dev/null
@@ -1,155 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import os
-import pathlib
-
-import pytest
-
-import zmake.project as project
-import zmake.toolchains as toolchains
-
-
-@pytest.fixture
-def mockfs(monkeypatch, tmp_path):
-    """Setup a fake fs root for pathlib objects at tmp_path/mockfs."""
-    mockfs_dir = pathlib.PosixPath(tmp_path / "mockfs")
-    mockfs_dir.mkdir()
-
-    class FakePath(pathlib.Path):
-        def __new__(cls, *args, **kwargs):
-            parts = pathlib.PosixPath(*args).relative_to("/").parts
-            # Make sure we don't double up our mocked directory.
-            mock_dir_parts = mockfs_dir.relative_to("/").parts
-            if parts[: len(mock_dir_parts)] == mock_dir_parts:
-                return pathlib.PosixPath(*args)
-            return pathlib.PosixPath("/", *mock_dir_parts, *parts)
-
-    monkeypatch.setattr(pathlib, "Path", FakePath)
-    return mockfs_dir
-
-
-@pytest.fixture
-def coreboot_sdk_exists(mockfs):
-    coreboot_sdk_dir = mockfs / "opt" / "coreboot-sdk"
-    coreboot_sdk_dir.mkdir(parents=True)
-
-
-@pytest.fixture
-def llvm_exists(mockfs):
-    llvm_file = mockfs / "usr" / "bin" / "x86_64-pc-linux-gnu-clang"
-    llvm_file.parent.mkdir(parents=True)
-    llvm_file.write_text("")
-
-
-@pytest.fixture
-def host_toolchain_exists(mockfs, monkeypatch):
-    monkeypatch.setattr(os, "environ", {})
-
-    gcc_file = mockfs / "usr" / "bin" / "gcc"
-    gcc_file.parent.mkdir(parents=True)
-    gcc_file.write_text("")
-
-
-@pytest.fixture
-def zephyr_exists(mockfs):
-    zephyr_sdk_version_file = mockfs / "opt" / "zephyr-sdk" / "sdk_version"
-    zephyr_sdk_version_file.parent.mkdir(parents=True)
-    zephyr_sdk_version_file.write_text("")
-
-
-@pytest.fixture
-def fake_project(tmp_path):
-    return project.Project(
-        tmp_path,
-        config_dict={
-            "board": "foo",
-            "supported-zephyr-versions": ["v2.6"],
-            "supported-toolchains": [
-                "coreboot-sdk",
-                "host",
-                "llvm",
-                "zephyr",
-            ],
-            "output-type": "raw",
-        },
-    )
-
-
-module_paths = {
-    "ec": pathlib.Path("/mnt/host/source/src/platform/ec"),
-}
-
-
-def test_coreboot_sdk(fake_project, coreboot_sdk_exists):
-    tc = fake_project.get_toolchain(module_paths)
-    assert isinstance(tc, toolchains.CorebootSdkToolchain)
-
-    config = tc.get_build_config()
-    assert config.cmake_defs == {
-        "ZEPHYR_TOOLCHAIN_VARIANT": "coreboot-sdk",
-        "TOOLCHAIN_ROOT": "/mnt/host/source/src/platform/ec/zephyr",
-    }
-
-
-def test_llvm(fake_project, llvm_exists):
-    tc = fake_project.get_toolchain(module_paths)
-    assert isinstance(tc, toolchains.LlvmToolchain)
-
-    config = tc.get_build_config()
-    assert config.cmake_defs == {
-        "ZEPHYR_TOOLCHAIN_VARIANT": "llvm",
-        "TOOLCHAIN_ROOT": "/mnt/host/source/src/platform/ec/zephyr",
-    }
-
-
-def test_zephyr(fake_project, zephyr_exists):
-    tc = fake_project.get_toolchain(module_paths)
-    assert isinstance(tc, toolchains.ZephyrToolchain)
-
-    config = tc.get_build_config()
-    assert config.cmake_defs == {
-        "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
-        "ZEPHYR_SDK_INSTALL_DIR": str(pathlib.Path("/opt/zephyr-sdk")),
-    }
-    assert config.environ_defs == {
-        "ZEPHYR_SDK_INSTALL_DIR": str(pathlib.Path("/opt/zephyr-sdk")),
-    }
-
-
-def test_zephyr_from_env(mockfs, monkeypatch, fake_project):
-    zephyr_sdk_path = mockfs / "zsdk"
-    zephyr_sdk_path.mkdir()
-
-    environ = {"ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path)}
-    monkeypatch.setattr(os, "environ", environ)
-
-    tc = fake_project.get_toolchain(module_paths)
-    assert isinstance(tc, toolchains.ZephyrToolchain)
-
-    config = tc.get_build_config()
-    assert config.cmake_defs == {
-        "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
-        "ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path),
-    }
-    assert config.environ_defs == {
-        "ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path),
-    }
-
-
-def test_host_toolchain(fake_project, host_toolchain_exists):
-    tc = fake_project.get_toolchain(module_paths)
-    assert isinstance(tc, toolchains.HostToolchain)
-
-    config = tc.get_build_config()
-    assert config.cmake_defs == {
-        "ZEPHYR_TOOLCHAIN_VARIANT": "host",
-    }
-
-
-def test_toolchain_override(mockfs, fake_project):
-    tc = fake_project.get_toolchain(module_paths, override="foo")
-    config = tc.get_build_config()
-    assert isinstance(tc, toolchains.GenericToolchain)
-    assert config.cmake_defs == {"ZEPHYR_TOOLCHAIN_VARIANT": "foo"}
diff --git a/zephyr/zmake/tests/test_util.py b/zephyr/zmake/tests/test_util.py
deleted file mode 100644
index 0c4cd4dda5..0000000000
--- a/zephyr/zmake/tests/test_util.py
+++ /dev/null
@@ -1,107 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import pathlib
-import re
-import tempfile
-
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
-import zmake.util as util
-
-# Strategies for use with hypothesis
-relative_path = st.from_regex(
-    regex=re.compile(r"\A\w{1,255}(/\w{1,255}){0,15}\Z", re.ASCII)
-)
-
-
-@hypothesis.given(relative_path, relative_path, relative_path)
-@hypothesis.settings(deadline=60000)
-def test_resolve_build_dir_with_build_dir(
-    platform_ec_subdir, project_subdir, build_subdir
-):
-    with tempfile.TemporaryDirectory() as temp_dir_name:
-        platform_ec_dir = pathlib.Path(temp_dir_name) / platform_ec_subdir
-        build_dir = util.resolve_build_dir(
-            platform_ec_dir=platform_ec_dir,
-            project_dir=platform_ec_dir / project_subdir,
-            build_dir=platform_ec_dir / build_subdir,
-        )
-
-        assert build_dir == platform_ec_dir / build_subdir
-
-
-@hypothesis.given(relative_path, relative_path)
-@hypothesis.settings(deadline=60000)
-def test_resolve_build_dir_invalid_project(platform_ec_subdir, project_subdir):
-    try:
-        with tempfile.TemporaryDirectory() as temp_dir_name:
-            platform_ec_dir = pathlib.Path(temp_dir_name) / platform_ec_subdir
-            util.resolve_build_dir(
-                platform_ec_dir=platform_ec_dir,
-                project_dir=platform_ec_dir / project_subdir,
-                build_dir=None,
-            )
-            pytest.fail()
-    except Exception:
-        pass
-
-
-@hypothesis.given(relative_path, relative_path)
-@hypothesis.settings(deadline=60000)
-def test_resolve_build_dir_from_project(platform_ec_subdir, project_subdir):
-    with tempfile.TemporaryDirectory() as temp_dir_name:
-        platform_ec_dir = pathlib.Path(temp_dir_name) / platform_ec_subdir
-        project_dir = platform_ec_dir / project_subdir
-        project_dir.mkdir(parents=True)
-        (project_dir / "zmake.yaml").touch()
-        build_dir = util.resolve_build_dir(
-            platform_ec_dir=platform_ec_dir, project_dir=project_dir, build_dir=None
-        )
-        assert build_dir == platform_ec_dir / "build" / project_subdir
-
-
-version_integers = st.integers(min_value=0)
-version_tuples = st.tuples(version_integers, version_integers, version_integers)
-
-
-@hypothesis.given(version_tuples)
-@hypothesis.settings(deadline=60000)
-def test_read_zephyr_version(version_tuple):
-    with tempfile.TemporaryDirectory() as zephyr_base:
-        with open(pathlib.Path(zephyr_base) / "VERSION", "w") as f:
-            for name, value in zip(
-                ("VERSION_MAJOR", "VERSION_MINOR", "PATCHLEVEL"), version_tuple
-            ):
-                f.write("{} = {}\n".format(name, value))
-
-        assert util.read_zephyr_version(zephyr_base) == version_tuple
-
-
-@hypothesis.given(st.integers())
-@hypothesis.settings(deadline=60000)
-def test_read_kconfig_autoconf_value(value):
-    with tempfile.TemporaryDirectory() as dir:
-        path = pathlib.Path(dir)
-        with open(path / "autoconf.h", "w") as f:
-            f.write("#define TEST {}".format(value))
-        read_value = util.read_kconfig_autoconf_value(path, "TEST")
-        assert int(read_value) == value
-
-
-@pytest.mark.parametrize(
-    ["input_str", "expected_result"],
-    [
-        ("", '""'),
-        ("TROGDOR ABC-123", '"TROGDOR ABC-123"'),
-        ("hello world", '"hello world"'),
-        ("hello\nworld", r'"hello\nworld"'),
-        ('hello"world', r'"hello\"world"'),
-        ("hello\\world", '"hello\\\\world"'),
-    ],
-)
-def test_c_str(input_str, expected_result):
-    assert util.c_str(input_str) == expected_result
diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py
deleted file mode 100644
index a238a8ac02..0000000000
--- a/zephyr/zmake/tests/test_version.py
+++ /dev/null
@@ -1,183 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import datetime
-import subprocess
-import unittest.mock as mock
-
-import pytest
-
-import zmake.project
-import zmake.version as version
-
-
-def _git_init(repo):
-    """Create a new git repository."""
-    repo.mkdir()
-    subprocess.run(
-        ["git", "-c", "init.defaultBranch=main", "-C", repo, "init"], check=True
-    )
-
-
-def _git_add(repo, path, contents="example!\n"):
-    """Write contents and stage a file."""
-    path.write_text(contents)
-    subprocess.run(["git", "-C", repo, "add", path], check=True)
-
-
-def _git_commit(repo, message="message!"):
-    env = {
-        "GIT_AUTHOR_NAME": "Alyssa P. Hacker",
-        "GIT_AUTHOR_EMAIL": "aphacker@example.org",
-        "GIT_AUTHOR_DATE": "Thu, 07 Apr 2005 22:13:13 +0200",
-        "GIT_COMMITTER_NAME": "Ben Bitdiddle",
-        "GIT_COMMITTER_EMAIL": "bitdiddle@example.org",
-        "GIT_COMMITTER_DATE": "Tue, 30 Aug 2005 10:50:30 -0700",
-    }
-    subprocess.run(["git", "-C", repo, "commit", "-m", message], check=True, env=env)
-
-
-def _setup_example_repos(tmp_path):
-    """Setup temporary project, zephyr base, and module repos.
-
-    Args:
-        tmp_path: Directory to set up files in.
-
-    Returns:
-        A 3-tuple of project, zephyr_base, modules_dict.
-    """
-    project_path = tmp_path / "prj"
-    project_path.mkdir()
-
-    project = zmake.project.Project(
-        project_path,
-        config_dict={
-            "board": "foo",
-            "output-type": "raw",
-            "supported-toolchains": ["coreboot-sdk"],
-            "supported-zephyr-versions": ["v2.6"],
-        },
-    )
-    # Has one commit.
-    zephyr_base = tmp_path / "zephyr_base"
-    _git_init(zephyr_base)
-    _git_add(
-        zephyr_base,
-        zephyr_base / "VERSION",
-        "VERSION_MAJOR=2\nVERSION_MINOR=6\nPATCHLEVEL=99\n",
-    )
-    _git_commit(zephyr_base, "Added version file")
-
-    # Has one commit.
-    mod1 = tmp_path / "mod1"
-    _git_init(mod1)
-    _git_add(mod1, mod1 / "file1")
-    _git_commit(mod1)
-
-    # Has two commits.
-    mod2 = tmp_path / "ec"
-    _git_init(mod2)
-    _git_add(mod2, mod2 / "file2")
-    _git_commit(mod2)
-    _git_add(mod2, mod2 / "file3")
-    _git_commit(mod2)
-
-    return project, zephyr_base, {"mod1": mod1, "ec": mod2}
-
-
-def test_version_string(tmp_path):
-    project, zephyr_base, modules = _setup_example_repos(tmp_path)
-    assert (
-        version.get_version_string(project, zephyr_base, modules)
-        == "prj_v2.6.4-ec:b5991f,os:377d26,mod1:02fd7a"
-    )
-
-
-def test_version_string_static(tmp_path):
-    project, zephyr_base, modules = _setup_example_repos(tmp_path)
-    assert (
-        version.get_version_string(project, zephyr_base, modules, static=True)
-        == "prj_v2.6.0-STATIC"
-    )
-
-
-@pytest.fixture
-def fake_user_hostname():
-    with mock.patch("getpass.getuser", return_value="toukmond", autospec=True):
-        with mock.patch("platform.node", return_value="pokey", autospec=True):
-            yield
-
-
-@pytest.fixture
-def fake_date():
-    fixed_date = datetime.datetime(2021, 6, 28, 3, 18, 53)
-    with mock.patch("datetime.datetime") as mock_datetime:
-        mock_datetime.now.return_value = fixed_date
-        yield
-
-
-HEADER_VERSION_STR = "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"
-EXPECTED_HEADER = (
-    "/* This file is automatically generated by zmake */\n"
-    '#define VERSION "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"\n'
-    '#define CROS_EC_VERSION32 "trogdor_v2.6.1004-cmsis:0dead0,"\n'
-    '#define BUILDER "toukmond@pokey"\n'
-    '#define DATE "2021-06-28 03:18:53"\n'
-    '#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"\n'
-    "#define CROS_FWID32 CROS_FWID_MISSING_STR\n"
-)
-HEADER_VERSION_STR_STATIC = "trogdor_v2.6.0-STATIC"
-EXPECTED_HEADER_STATIC = (
-    "/* This file is automatically generated by zmake */\n"
-    '#define VERSION "trogdor_v2.6.0-STATIC"\n'
-    '#define CROS_EC_VERSION32 "trogdor_v2.6.0-STATIC"\n'
-    '#define BUILDER "reproducible@build"\n'
-    '#define DATE "STATIC_VERSION_DATE"\n'
-    '#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"\n'
-    "#define CROS_FWID32 CROS_FWID_MISSING_STR\n"
-)
-
-
-def test_header_gen(fake_user_hostname, fake_date, tmp_path):
-    # Test the simple case (static=False, no existing header).
-    output_file = tmp_path / "ec_version.h"
-    version.write_version_header(HEADER_VERSION_STR, output_file)
-    assert output_file.read_text() == EXPECTED_HEADER
-
-
-def test_header_gen_reproducible_build(tmp_path):
-    # With static=True this time.
-    output_file = tmp_path / "ec_version.h"
-    version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True)
-    assert output_file.read_text() == EXPECTED_HEADER_STATIC
-
-
-def test_header_gen_exists_not_changed(fake_user_hostname, fake_date, tmp_path):
-    # Test we don't overwrite if no changes needed.
-    output_file = tmp_path / "ec_version.h"
-
-    # First time, write and record mtime.
-    version.write_version_header(HEADER_VERSION_STR, output_file)
-    expected_mtime = output_file.stat().st_mtime
-
-    # Do another write (contents should be unchanged).
-    version.write_version_header(HEADER_VERSION_STR, output_file)
-
-    # Assert we didn't write again.
-    assert output_file.stat().st_mtime == expected_mtime
-
-
-def test_header_gen_exists_needs_changes(fake_user_hostname, fake_date, tmp_path):
-    # Test we overwrite when it exists already and changes are needed.
-    output_file = tmp_path / "ec_version.h"
-
-    # First time, write and save contents.
-    version.write_version_header(HEADER_VERSION_STR, output_file)
-    original_contents = output_file.read_text()
-
-    # Do another write (contents should be changed).
-    version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True)
-
-    # Assert we overwrote.
-    assert output_file.read_text() != original_contents
diff --git a/zephyr/zmake/tests/test_zmake.py b/zephyr/zmake/tests/test_zmake.py
deleted file mode 100644
index 641f9f3db9..0000000000
--- a/zephyr/zmake/tests/test_zmake.py
+++ /dev/null
@@ -1,224 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Do a run of 'zmake build' and check the output"""
-
-import logging
-import os
-import pathlib
-import re
-import tempfile
-import unittest
-import unittest.mock as mock
-from unittest.mock import patch
-
-from testfixtures import LogCapture
-
-import zmake.build_config
-import zmake.jobserver
-import zmake.multiproc as multiproc
-import zmake.project
-import zmake.toolchains
-import zmake.zmake as zm
-
-OUR_PATH = os.path.dirname(os.path.realpath(__file__))
-
-
-class FakeProject:
-    """A fake project which requests two builds and does no packing"""
-
-    # pylint: disable=too-few-public-methods
-
-    def __init__(self):
-        self.packer = mock.Mock()
-        self.packer.pack_firmware = mock.Mock(return_value=[])
-        self.project_dir = pathlib.Path("FakeProjectDir")
-
-        self.config = mock.Mock()
-        self.config.supported_zephyr_versions = [(2, 5)]
-
-    @staticmethod
-    def iter_builds():
-        """Yield the two builds that zmake normally does"""
-        yield "build-ro", zmake.build_config.BuildConfig()
-        yield "build-rw", zmake.build_config.BuildConfig()
-
-    def prune_modules(self, paths):
-        return {}  # pathlib.Path('path')]
-
-    def find_dts_overlays(self, module_paths):
-        return zmake.build_config.BuildConfig()
-
-    def get_toolchain(self, module_paths, override=None):
-        return zmake.toolchains.GenericToolchain(
-            override or "foo",
-            modules=module_paths,
-        )
-
-
-class FakeJobserver(zmake.jobserver.GNUMakeJobServer):
-    """A fake jobserver which just runs 'cat' on the provided files"""
-
-    def __init__(self, fnames):
-        """Start up a jobserver with two jobs
-
-        Args:
-            fnames: Dict of regexp to filename. If the regexp matches the
-            command, then the filename will be returned as the output.
-        """
-        super().__init__()
-        self.jobserver = zmake.jobserver.GNUMakeJobServer(jobs=2)
-        self.fnames = fnames
-
-    def get_job(self):
-        """Fake implementation of get_job(), which returns a real JobHandle()"""
-        return zmake.jobserver.JobHandle(mock.Mock())
-
-    # pylint: disable=arguments-differ
-    def popen(self, cmd, *args, **kwargs):
-        """Ignores the provided command and just runs 'cat' instead"""
-        for pattern, filename in self.fnames.items():
-            # Convert to a list of strings
-            cmd = [isinstance(c, pathlib.PosixPath) and c.as_posix() or c for c in cmd]
-            if pattern.match(" ".join(cmd)):
-                new_cmd = ["cat", filename]
-                break
-        else:
-            raise Exception('No pattern matched "%s"' % " ".join(cmd))
-        kwargs.pop("env", None)
-        return self.jobserver.popen(new_cmd, *args, **kwargs)
-
-
-def get_test_filepath(suffix):
-    """Get the filepath for a particular test file
-
-    Args:
-        suffix: Suffix of the file to read, e.g. 'ro' or 'ro_INFO'
-
-    Returns:
-        Full path to the test file
-    """
-    return os.path.join(OUR_PATH, "files", "sample_{}.txt".format(suffix))
-
-
-def do_test_with_log_level(log_level, use_configure=False, fnames=None):
-    """Test filtering using a particular log level
-
-    Args:
-        log_level: Level to use
-        use_configure: Run the 'configure' subcommand instead of 'build'
-        fnames: Dict of regexp to filename. If the regexp matches the
-            command, then the filename will be returned as the output.
-            (None to use default ro/rw output)
-
-    Returns:
-        tuple:
-            - List of log strings obtained from the run
-            - Temporary directory used for build
-    """
-    if fnames is None:
-        fnames = {
-            re.compile(r".*build-ro"): get_test_filepath("ro"),
-            re.compile(r".*build-rw"): get_test_filepath("rw"),
-        }
-    zephyr_base = mock.Mock()
-
-    zmk = zm.Zmake(
-        jobserver=FakeJobserver(fnames),
-        zephyr_base=zephyr_base,
-    )
-
-    with LogCapture(level=log_level) as cap:
-        with tempfile.TemporaryDirectory() as tmpname:
-            with open(os.path.join(tmpname, "VERSION"), "w") as fd:
-                fd.write(
-                    """VERSION_MAJOR = 2
-VERSION_MINOR = 5
-PATCHLEVEL = 0
-VERSION_TWEAK = 0
-EXTRAVERSION =
-"""
-                )
-            zephyr_base.resolve = mock.Mock(return_value=pathlib.Path(tmpname))
-            with patch("zmake.version.get_version_string", return_value="123"):
-                with patch.object(zmake.project, "Project", return_value=FakeProject()):
-                    if use_configure:
-                        zmk.configure(
-                            pathlib.Path(tmpname), build_dir=pathlib.Path("build")
-                        )
-                    else:
-                        with patch("zmake.version.write_version_header", autospec=True):
-                            zmk.build(pathlib.Path(tmpname))
-                    multiproc.wait_for_log_end()
-
-    recs = [rec.getMessage() for rec in cap.records]
-    return recs, tmpname
-
-
-class TestFilters(unittest.TestCase):
-    """Test filtering of stdout and stderr"""
-
-    def test_filter_normal(self):
-        """Test filtering of a normal build (with no errors)"""
-        recs, _ = do_test_with_log_level(logging.ERROR)
-        self.assertFalse(recs)
-
-    def test_filter_info(self):
-        """Test what appears on the INFO level"""
-        recs, tmpname = do_test_with_log_level(logging.INFO)
-        # TODO: Remove sets and figure out how to check the lines are in the
-        # right order.
-        expected = {
-            "Building {}:build-ro: /usr/bin/ninja -C {}/build-build-ro".format(
-                tmpname, tmpname
-            ),
-            "Building {}:build-rw: /usr/bin/ninja -C {}/build-build-rw".format(
-                tmpname, tmpname
-            ),
-        }
-        for suffix in ["ro", "rw"]:
-            with open(get_test_filepath("%s_INFO" % suffix)) as f:
-                for line in f:
-                    expected.add(
-                        "[{}:build-{}]{}".format(tmpname, suffix, line.strip())
-                    )
-        # This produces an easy-to-read diff if there is a difference
-        self.assertEqual(expected, set(recs))
-
-    def test_filter_debug(self):
-        """Test what appears on the DEBUG level"""
-        recs, tmpname = do_test_with_log_level(logging.DEBUG)
-        # TODO: Remove sets and figure out how to check the lines are in the
-        # right order.
-        expected = {
-            "Building {}:build-ro: /usr/bin/ninja -C {}/build-build-ro".format(
-                tmpname, tmpname
-            ),
-            "Building {}:build-rw: /usr/bin/ninja -C {}/build-build-rw".format(
-                tmpname, tmpname
-            ),
-            "Running cat {}/files/sample_ro.txt".format(OUR_PATH),
-            "Running cat {}/files/sample_rw.txt".format(OUR_PATH),
-        }
-        for suffix in ["ro", "rw"]:
-            with open(get_test_filepath(suffix)) as f:
-                for line in f:
-                    expected.add(
-                        "[{}:build-{}]{}".format(tmpname, suffix, line.strip())
-                    )
-        # This produces an easy-to-read diff if there is a difference
-        self.assertEqual(expected, set(recs))
-
-    def test_filter_devicetree_error(self):
-        """Test that devicetree errors appear"""
-        recs, tmpname = do_test_with_log_level(
-            logging.ERROR, True, {re.compile(r".*"): get_test_filepath("err")}
-        )
-
-        dt_errs = [rec for rec in recs if "adc" in rec]
-        assert "devicetree error: 'adc' is marked as required" in list(dt_errs)[0]
-
-
-if __name__ == "__main__":
-    unittest.main()
diff --git a/zephyr/zmake/zmake/__init__.py b/zephyr/zmake/zmake/__init__.py
deleted file mode 100644
index e69de29bb2..0000000000
--- a/zephyr/zmake/zmake/__init__.py
+++ /dev/null
diff --git a/zephyr/zmake/zmake/__main__.py b/zephyr/zmake/zmake/__main__.py
deleted file mode 100644
index 31f0436b5a..0000000000
--- a/zephyr/zmake/zmake/__main__.py
+++ /dev/null
@@ -1,273 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""The entry point into zmake."""
-import argparse
-import inspect
-import logging
-import os
-import pathlib
-import sys
-
-import zmake.multiproc as multiproc
-import zmake.zmake as zm
-
-
-def maybe_reexec(argv):
-    """Re-exec zmake from the EC source tree, if possible and desired.
-
-    Zmake installs into the users' chroot, which makes it convenient
-    to execute, but can sometimes become tedious when zmake changes
-    land and users haven't upgraded their chroots yet.
-
-    We can partially subvert this problem by re-execing zmake from the
-    source if it's available.  This won't make it so developers never
-    need to upgrade their chroots (e.g., a toolchain upgrade could
-    require chroot upgrades), but at least makes it slightly more
-    convenient for an average repo sync.
-
-    Args:
-        argv: The argument list passed to the main function, not
-            including the executable path.
-
-    Returns:
-        None, if the re-exec did not happen, or never returns if the
-        re-exec did happen.
-    """
-    # We only re-exec if we are inside of a chroot (since if installed
-    # standalone using pip, there's already an "editable install"
-    # feature for that in pip.)
-    env = dict(os.environ)
-    srcroot = env.get("CROS_WORKON_SRCROOT")
-    if not srcroot:
-        return
-
-    # If for some reason we decide to move zmake in the future, then
-    # we don't want to use the re-exec logic.
-    zmake_path = (
-        pathlib.Path(srcroot) / "src" / "platform" / "ec" / "zephyr" / "zmake"
-    ).resolve()
-    if not zmake_path.is_dir():
-        return
-
-    # If PYTHONPATH is set, it is either because we just did a
-    # re-exec, or because the user wants to run a specific copy of
-    # zmake.  In either case, we don't want to re-exec.
-    if "PYTHONPATH" in env:
-        return
-
-    # Set PYTHONPATH so that we run zmake from source.
-    env["PYTHONPATH"] = str(zmake_path)
-
-    os.execve(sys.executable, [sys.executable, "-m", "zmake", *argv], env)
-
-
-def call_with_namespace(func, namespace):
-    """Call a function with arguments applied from a Namespace.
-
-    Args:
-        func: The callable to call.
-        namespace: The namespace to apply to the callable.
-
-    Returns:
-        The result of calling the callable.
-    """
-    kwds = {}
-    sig = inspect.signature(func)
-    names = [p.name for p in sig.parameters.values()]
-    for name, value in vars(namespace).items():
-        pyname = name.replace("-", "_")
-        if pyname in names:
-            kwds[pyname] = value
-    return func(**kwds)
-
-
-# Dictionary used to map log level strings to their corresponding int values.
-log_level_map = {
-    "DEBUG": logging.DEBUG,
-    "INFO": logging.INFO,
-    "WARNING": logging.WARNING,
-    "ERROR": logging.ERROR,
-    "CRITICAL": logging.CRITICAL,
-}
-
-
-def main(argv=None):
-    """The main function.
-
-    Args:
-        argv: Optionally, the command-line to parse, not including argv[0].
-
-    Returns:
-        Zero upon success, or non-zero upon failure.
-    """
-    if argv is None:
-        argv = sys.argv[1:]
-
-    maybe_reexec(argv)
-
-    parser = argparse.ArgumentParser()
-    parser.add_argument(
-        "--checkout", type=pathlib.Path, help="Path to ChromiumOS checkout"
-    )
-    parser.add_argument(
-        "-D",
-        "--debug",
-        action="store_true",
-        default=False,
-        help=("Turn on debug features (e.g., stack trace, " "verbose logging)"),
-    )
-    parser.add_argument(
-        "-j",
-        "--jobs",
-        # TODO(b/178196029): ninja doesn't know how to talk to a
-        # jobserver properly and spams our CPU on all cores.  Default
-        # to -j1 to execute sequentially until we switch to GNU Make.
-        default=1,
-        type=int,
-        help="Degree of multiprogramming to use",
-    )
-    parser.add_argument(
-        "-l",
-        "--log-level",
-        choices=list(log_level_map.keys()),
-        dest="log_level",
-        help="Set the logging level (default=INFO)",
-    )
-    parser.add_argument(
-        "-L",
-        "--no-log-label",
-        action="store_false",
-        help="Turn off logging labels",
-        dest="log_label",
-        default=None,
-    )
-    parser.add_argument(
-        "--log-label",
-        action="store_true",
-        help="Turn on logging labels",
-        dest="log_label",
-        default=None,
-    )
-    parser.add_argument(
-        "--modules-dir",
-        type=pathlib.Path,
-        help="The path to a directory containing all modules "
-        "needed.  If unspecified, zmake will assume you have "
-        "a Chrome OS checkout and try locating them in the "
-        "checkout.",
-    )
-    parser.add_argument(
-        "--zephyr-base", type=pathlib.Path, help="Path to Zephyr OS repository"
-    )
-
-    sub = parser.add_subparsers(dest="subcommand", help="Subcommand")
-    sub.required = True
-
-    configure = sub.add_parser("configure")
-    configure.add_argument(
-        "--ignore-unsupported-zephyr-version",
-        action="store_true",
-        help="Don't warn about using an unsupported Zephyr version",
-    )
-    configure.add_argument("-t", "--toolchain", help="Name of toolchain to use")
-    configure.add_argument(
-        "--bringup",
-        action="store_true",
-        dest="bringup",
-        help="Enable bringup debugging features",
-    )
-    configure.add_argument(
-        "-B", "--build-dir", type=pathlib.Path, help="Build directory"
-    )
-    configure.add_argument(
-        "-b",
-        "--build",
-        action="store_true",
-        dest="build_after_configure",
-        help="Run the build after configuration",
-    )
-    configure.add_argument(
-        "--test",
-        action="store_true",
-        dest="test_after_configure",
-        help="Test the .elf file after configuration",
-    )
-    configure.add_argument(
-        "project_dir", type=pathlib.Path, help="Path to the project to build"
-    )
-    configure.add_argument(
-        "-c",
-        "--coverage",
-        action="store_true",
-        dest="coverage",
-        help="Enable CONFIG_COVERAGE Kconfig.",
-    )
-
-    build = sub.add_parser("build")
-    build.add_argument(
-        "build_dir",
-        type=pathlib.Path,
-        help="The build directory used during configuration",
-    )
-    build.add_argument(
-        "-w",
-        "--fail-on-warnings",
-        action="store_true",
-        help="Exit with code 2 if warnings are detected",
-    )
-
-    test = sub.add_parser("test")
-    test.add_argument(
-        "build_dir",
-        type=pathlib.Path,
-        help="The build directory used during configuration",
-    )
-
-    sub.add_parser("testall")
-
-    coverage = sub.add_parser("coverage")
-    coverage.add_argument(
-        "build_dir",
-        type=pathlib.Path,
-        help="The build directory used during configuration",
-    )
-
-    opts = parser.parse_args(argv)
-
-    # Default logging
-    log_level = logging.INFO
-    log_label = False
-
-    if opts.log_level:
-        log_level = log_level_map[opts.log_level]
-        log_label = True
-    elif opts.debug:
-        log_level = logging.DEBUG
-        log_label = True
-
-    if opts.log_label is not None:
-        log_label = opts.log_label
-    if log_label:
-        log_format = "%(levelname)s: %(message)s"
-    else:
-        log_format = "%(message)s"
-        multiproc.log_job_names = False
-
-    logging.basicConfig(format=log_format, level=log_level)
-
-    if not opts.debug:
-        sys.tracebacklimit = 0
-
-    try:
-        zmake = call_with_namespace(zm.Zmake, opts)
-        subcommand_method = getattr(zmake, opts.subcommand.replace("-", "_"))
-        result = call_with_namespace(subcommand_method, opts)
-        return result
-    finally:
-        multiproc.wait_for_log_end()
-
-
-if __name__ == "__main__":
-    sys.exit(main())
diff --git a/zephyr/zmake/zmake/build_config.py b/zephyr/zmake/zmake/build_config.py
deleted file mode 100644
index 9a9c7f36a2..0000000000
--- a/zephyr/zmake/zmake/build_config.py
+++ /dev/null
@@ -1,100 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Encapsulation of a build configuration."""
-
-
-import zmake.util as util
-
-
-class BuildConfig:
-    """A container for build configurations.
-
-    A build config is a tuple of environment variables, cmake
-    variables, kconfig definitons, and kconfig files.
-    """
-
-    def __init__(
-        self, environ_defs={}, cmake_defs={}, kconfig_defs={}, kconfig_files=[]
-    ):
-        self.environ_defs = dict(environ_defs)
-        self.cmake_defs = dict(cmake_defs)
-        self.kconfig_defs = dict(kconfig_defs)
-        self.kconfig_files = kconfig_files
-
-    def popen_cmake(
-        self, jobclient, project_dir, build_dir, kconfig_path=None, **kwargs
-    ):
-        """Run Cmake with this config using a jobclient.
-
-        Args:
-            jobclient: A JobClient instance.
-            project_dir: The project directory.
-            build_dir: Directory to use for Cmake build.
-            kconfig_path: The path to write out Kconfig definitions.
-            kwargs: forwarded to popen.
-        """
-        kconfig_files = list(self.kconfig_files)
-        if kconfig_path:
-            util.write_kconfig_file(kconfig_path, self.kconfig_defs)
-            kconfig_files.append(kconfig_path)
-        elif self.kconfig_defs:
-            raise ValueError(
-                "Cannot start Cmake on a config with Kconfig items without a "
-                "kconfig_path"
-            )
-
-        if kconfig_files:
-            base_config = BuildConfig(
-                environ_defs=self.environ_defs, cmake_defs=self.cmake_defs
-            )
-            conf_file_config = BuildConfig(
-                cmake_defs={
-                    "CONF_FILE": ";".join(str(p.resolve()) for p in kconfig_files)
-                }
-            )
-            return (base_config | conf_file_config).popen_cmake(
-                jobclient, project_dir, build_dir, **kwargs
-            )
-
-        kwargs["env"] = dict(**kwargs.get("env", {}), **self.environ_defs)
-        return jobclient.popen(
-            [
-                "/usr/bin/cmake",
-                "-S",
-                project_dir,
-                "-B",
-                build_dir,
-                "-GNinja",
-                *("-D{}={}".format(*pair) for pair in self.cmake_defs.items()),
-            ],
-            **kwargs
-        )
-
-    def __or__(self, other):
-        """Combine two BuildConfig instances."""
-        if not isinstance(other, BuildConfig):
-            raise TypeError(
-                "Unsupported operation | for {} and {}".format(type(self), type(other))
-            )
-
-        return BuildConfig(
-            environ_defs=dict(**self.environ_defs, **other.environ_defs),
-            cmake_defs=dict(**self.cmake_defs, **other.cmake_defs),
-            kconfig_defs=dict(**self.kconfig_defs, **other.kconfig_defs),
-            kconfig_files=list({*self.kconfig_files, *other.kconfig_files}),
-        )
-
-    def __repr__(self):
-        return "BuildConfig({})".format(
-            ", ".join(
-                "{}={!r}".format(name, getattr(self, name))
-                for name in [
-                    "environ_defs",
-                    "cmake_defs",
-                    "kconfig_defs",
-                    "kconfig_files",
-                ]
-                if getattr(self, name)
-            )
-        )
diff --git a/zephyr/zmake/zmake/jobserver.py b/zephyr/zmake/zmake/jobserver.py
deleted file mode 100644
index 69199a2dc8..0000000000
--- a/zephyr/zmake/zmake/jobserver.py
+++ /dev/null
@@ -1,144 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Module for job counters, limiting the amount of concurrent executions."""
-
-import logging
-import multiprocessing
-import os
-import re
-import select
-import subprocess
-
-import zmake
-
-
-class JobHandle:
-    """Small object to handle claim of a job."""
-
-    def __init__(self, release_func, *args, **kwargs):
-        self.release_func = release_func
-        self.args = args
-        self.kwargs = kwargs
-
-    def __enter__(self):
-        pass
-
-    def __exit__(self, exc_type, exc_value, traceback):
-        self.release_func(*self.args, **self.kwargs)
-
-
-class JobClient:
-    """Abstract base class for all job clients."""
-
-    def get_job(self):
-        """Claim a job."""
-        raise NotImplementedError("Abstract method not implemented")
-
-    def env(self):
-        """Get the environment variables necessary to share the job server."""
-        return {}
-
-    def popen(self, *args, **kwargs):
-        """Start a process using subprocess.Popen
-
-        All other arguments are passed to subprocess.Popen.
-
-        Returns:
-            A Popen object.
-        """
-        kwargs.setdefault("env", os.environ)
-        kwargs["env"].update(self.env())
-
-        logger = logging.getLogger(self.__class__.__name__)
-        logger.debug("Running %s", zmake.util.repr_command(*args))
-        return subprocess.Popen(*args, **kwargs)
-
-    def run(self, *args, claim_job=True, **kwargs):
-        """Run a process using subprocess.run, optionally claiming a job.
-
-        Args:
-            claim_job: True if a job should be claimed.
-
-        All other arguments are passed to subprocess.run.
-
-        Returns:
-            A CompletedProcess object.
-        """
-        if claim_job:
-            with self.get_job():
-                return self.run(*args, claim_job=False, **kwargs)
-
-        kwargs.setdefault("env", os.environ)
-        kwargs["env"].update(self.env())
-
-        return subprocess.run(*args, **kwargs)
-
-
-class JobServer(JobClient):
-    """Abstract Job Server."""
-
-    def __init__(self, jobs=0):
-        raise NotImplementedError("Abstract method not implemented")
-
-
-class GNUMakeJobClient(JobClient):
-    def __init__(self, read_fd, write_fd):
-        self._pipe = [read_fd, write_fd]
-
-    @classmethod
-    def from_environ(cls, env=None):
-        """Create a job client from an environment with the MAKEFLAGS variable.
-
-        If we are started under a GNU Make Job Server, we can search
-        the environment for a string "--jobserver-auth=R,W", where R
-        and W will be the read and write file descriptors to the pipe
-        respectively.  If we don't find this environment variable (or
-        the string inside of it), this will raise an OSError.
-
-        Args:
-            env: Optionally, the environment to search.
-
-        Returns:
-            A GNUMakeJobClient configured appropriately.
-        """
-        if env is None:
-            env = os.environ
-        makeflags = env.get("MAKEFLAGS")
-        if not makeflags:
-            raise OSError("MAKEFLAGS is not set in the environment")
-        match = re.search(r"--jobserver-auth=(\d+),(\d+)", makeflags)
-        if not match:
-            raise OSError("MAKEFLAGS did not contain jobserver flags")
-        read_fd, write_fd = map(int, match.groups())
-        return cls(read_fd, write_fd)
-
-    def get_job(self):
-        """Claim a job.
-
-        Returns:
-            A JobHandle object.
-        """
-        byte = os.read(self._pipe[0], 1)
-        return JobHandle(lambda: os.write(self._pipe[1], byte))
-
-    def env(self):
-        """Get the environment variables necessary to share the job server."""
-        return {"MAKEFLAGS": "--jobserver-auth={},{}".format(*self._pipe)}
-
-
-class GNUMakeJobServer(JobServer, GNUMakeJobClient):
-    """Implements a GNU Make POSIX Job Server.
-
-    See https://www.gnu.org/software/make/manual/html_node/POSIX-Jobserver.html
-    for specification.
-    """
-
-    def __init__(self, jobs=0):
-        if not jobs:
-            jobs = multiprocessing.cpu_count()
-        elif jobs > select.PIPE_BUF:
-            jobs = select.PIPE_BUF
-
-        self._pipe = os.pipe()
-        os.write(self._pipe[1], b"+" * jobs)
diff --git a/zephyr/zmake/zmake/modules.py b/zephyr/zmake/zmake/modules.py
deleted file mode 100644
index 5ba0ef73f8..0000000000
--- a/zephyr/zmake/zmake/modules.py
+++ /dev/null
@@ -1,99 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Registry of known Zephyr modules."""
-
-import zmake.build_config as build_config
-import zmake.util as util
-
-
-def third_party_module(name, checkout):
-    """Common callback in registry for all third_party/zephyr modules.
-
-    Args:
-        name: The name of the module.
-        checkout: The path to the chromiumos source.
-
-    Return:
-        The path to the module module.
-    """
-    return checkout / "src" / "third_party" / "zephyr" / name
-
-
-known_modules = {
-    "hal_stm32": third_party_module,
-    "cmsis": third_party_module,
-    "ec": lambda name, checkout: (checkout / "src" / "platform" / "ec"),
-    "nanopb": third_party_module,
-}
-
-
-def locate_from_checkout(checkout_dir):
-    """Find modules from a Chrome OS checkout.
-
-    Important: this function should only conditionally be called if a
-    checkout exists.  Zmake *can* be used without a Chrome OS source
-    tree.  You should call locate_from_directory if outside of a
-    Chrome OS source tree.
-
-    Args:
-        checkout_dir: The path to the chromiumos source.
-
-    Returns:
-        A dictionary mapping module names to paths.
-    """
-    result = {}
-    for name, locator in known_modules.items():
-        result[name] = locator(name, checkout_dir)
-    return result
-
-
-def locate_from_directory(directory):
-    """Create a modules dictionary from a directory.
-
-    This takes a directory, and searches for the known module names
-    located in it.
-
-    Args:
-        directory: the directory to search in.
-
-    Returns:
-        A dictionary mapping module names to paths.
-    """
-    result = {}
-
-    for name in known_modules:
-        modpath = (directory / name).resolve()
-        if (modpath / "zephyr" / "module.yml").is_file():
-            result[name] = modpath
-
-    return result
-
-
-def setup_module_symlinks(output_dir, modules):
-    """Setup a directory with symlinks to modules.
-
-    Args:
-        output_dir: The directory to place the symlinks in.
-        modules: A dictionary of module names mapping to paths.
-
-    Returns:
-        The resultant BuildConfig that should be applied to use each
-        of these modules.
-    """
-    if not output_dir.exists():
-        output_dir.mkdir(parents=True)
-
-    module_links = []
-
-    for name, path in modules.items():
-        link_path = output_dir.resolve() / name
-        util.update_symlink(path, link_path)
-        module_links.append(link_path)
-
-    if module_links:
-        return build_config.BuildConfig(
-            cmake_defs={"ZEPHYR_MODULES": ";".join(map(str, module_links))}
-        )
-    else:
-        return build_config.BuildConfig()
diff --git a/zephyr/zmake/zmake/multiproc.py b/zephyr/zmake/zmake/multiproc.py
deleted file mode 100644
index 5e98374c8c..0000000000
--- a/zephyr/zmake/zmake/multiproc.py
+++ /dev/null
@@ -1,322 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-import collections
-import logging
-import os
-import select
-import threading
-
-"""Zmake multiprocessing utility module.
-
-This module is used to aid in zmake's multiprocessing. It contains tools
-available to log output from multiple processes on the fly. This means that a
-process does not need to finish before the output is available to the developer
-on the screen.
-"""
-
-# A local pipe use to signal the look that a new file descriptor was added and
-# should be included in the select statement.
-_logging_interrupt_pipe = os.pipe()
-# A condition variable used to synchronize logging operations.
-_logging_cv = threading.Condition()
-# A map of file descriptors to their LogWriter
-_logging_map = {}
-# Should we log job names or not
-log_job_names = True
-
-
-def reset():
-    """Reset this module to its starting state (useful for tests)"""
-    global _logging_map
-
-    _logging_map = {}
-
-
-class LogWriter:
-    """Contains information about a file descriptor that is producing output
-
-    There is typically one of these for each file descriptor that a process is
-    writing to while running (stdout and stderr).
-
-    Properties:
-        _logger: The logger object to use.
-        _log_level: The logging level to use.
-        _override_func: A function used to override the log level. The
-            function will be called once per line prior to logging and will be
-            passed the arguments of the line and the default log level.
-        _written_at_level: dict:
-            key: log_level
-            value: True if output was written at that level
-        _job_id: The name to prepend to logged lines
-        _file_descriptor: The file descriptor being logged.
-    """
-
-    def __init__(
-        self, logger, log_level, log_level_override_func, job_id, file_descriptor
-    ):
-        self._logger = logger
-        self._log_level = log_level
-        self._override_func = log_level_override_func
-        # A map whether output was printed at each logging level
-        self._written_at_level = collections.defaultdict(lambda: False)
-        self._job_id = job_id
-        self._file_descriptor = file_descriptor
-
-    def log_line(self, line):
-        """Log a line of output
-
-        If the log-level override function requests a change in log level, that
-        causes self._log_level to be updated accordingly.
-
-        Args:
-            line: Text line to log
-        """
-        if self._override_func:
-            # Get the new log level and update the default. The reason we
-            # want to update the default is that if we hit an error, all
-            # future logging should be moved to the new logging level. This
-            # greatly simplifies the logic that is needed to update the log
-            # level.
-            self._log_level = self._override_func(line, self._log_level)
-        if self._job_id and log_job_names:
-            self._logger.log(self._log_level, "[%s]%s", self._job_id, line)
-        else:
-            self._logger.log(self._log_level, line)
-        self._written_at_level[self._log_level] = True
-
-    def has_written(self, log_level):
-        """Check if output was written at a certain log level
-
-        Args:
-            log_level: log level to check
-
-        Returns:
-            True if any output was written at that log level, False if not
-        """
-        return self._written_at_level[log_level]
-
-    def wait(self):
-        """Wait for this LogWriter to finish.
-
-        This method will block execution until all the logs have been flushed out.
-        """
-        with _logging_cv:
-            _logging_cv.wait_for(lambda: self._file_descriptor not in _logging_map)
-
-
-def _log_fd(fd):
-    """Log information from a single file descriptor.
-
-    This function is BLOCKING. It will read from the given file descriptor until
-    either the end of line is read or EOF. Once EOF is read it will remove the
-    file descriptor from _logging_map so it will no longer be used.
-    Additionally, in some cases, the file descriptor will be closed (caused by
-    a call to Popen.wait()). In these cases, the file descriptor will also be
-    removed from the map as it is no longer valid.
-    """
-    with _logging_cv:
-        writer = _logging_map[fd]
-        if fd.closed:
-            del _logging_map[fd]
-            _logging_cv.notify_all()
-            return
-        line = fd.readline()
-        if not line:
-            # EOF
-            del _logging_map[fd]
-            _logging_cv.notify_all()
-            return
-        line = line.rstrip("\n")
-        if line:
-            writer.log_line(line)
-
-
-def _prune_logging_fds():
-    """Prune the current file descriptors under _logging_map.
-
-    This function will iterate over the logging map and check for closed file
-    descriptors. Every closed file descriptor will be removed.
-    """
-    with _logging_cv:
-        remove = [fd for fd in _logging_map.keys() if fd.closed]
-        for fd in remove:
-            del _logging_map[fd]
-        if remove:
-            _logging_cv.notify_all()
-
-
-def _logging_loop():
-    """The primary logging thread loop.
-
-    This is the entry point of the logging thread. It will listen for (1) any
-    new data on the output file descriptors that were added via log_output() and
-    (2) any new file descriptors being added by log_output(). Once a file
-    descriptor is ready to be read, this function will call _log_fd to perform
-    the actual read and logging.
-    """
-    while True:
-        with _logging_cv:
-            _logging_cv.wait_for(lambda: _logging_map)
-            keys = list(_logging_map.keys()) + [_logging_interrupt_pipe[0]]
-        try:
-            fds, _, _ = select.select(keys, [], [])
-        except ValueError:
-            # One of the file descriptors must be closed, prune them and try
-            # again.
-            _prune_logging_fds()
-            continue
-        if _logging_interrupt_pipe[0] in fds:
-            # We got a dummy byte sent by log_output(), this is a signal used to
-            # break out of the blocking select.select call to tell us that the
-            # file descriptor set has changed. We just need to read the byte and
-            # remove this descriptor from the list. If we actually have data
-            # that should be read it will be read in the for loop below.
-            os.read(_logging_interrupt_pipe[0], 1)
-            fds.remove(_logging_interrupt_pipe[0])
-        for fd in fds:
-            _log_fd(fd)
-
-
-_logging_thread = None
-
-
-def log_output(
-    logger, log_level, file_descriptor, log_level_override_func=None, job_id=None
-):
-    """Log the output from the given file descriptor.
-
-    Args:
-        logger: The logger object to use.
-        log_level: The logging level to use.
-        file_descriptor: The file descriptor to read from.
-        log_level_override_func: A function used to override the log level. The
-          function will be called once per line prior to logging and will be
-          passed the arguments of the line and the default log level.
-
-    Returns:
-        LogWriter object for the resulting output
-    """
-    with _logging_cv:
-        global _logging_thread
-        if _logging_thread is None or not _logging_thread.is_alive():
-            # First pass or thread must have died, create a new one.
-            _logging_thread = threading.Thread(target=_logging_loop, daemon=True)
-            _logging_thread.start()
-
-        writer = LogWriter(
-            logger, log_level, log_level_override_func, job_id, file_descriptor
-        )
-        _logging_map[file_descriptor] = writer
-        # Write a dummy byte to the pipe to break the select so we can add the
-        # new fd.
-        os.write(_logging_interrupt_pipe[1], b"x")
-        # Notify the condition so we can run the select on the current fds.
-        _logging_cv.notify_all()
-    return writer
-
-
-def wait_for_log_end():
-    """Wait for all the logs to be printed.
-
-    This method will block execution until all the logs have been flushed out.
-    """
-    with _logging_cv:
-        _logging_cv.wait_for(lambda: not _logging_map)
-
-
-class Executor:
-    """Parallel executor helper class.
-
-    This class is used to run multiple functions in parallel. The functions MUST
-    return an integer result code (or throw an exception). This class will start
-    a thread per operation and wait() for all the threads to resolve.
-
-    Attributes:
-        lock: The condition variable used to synchronize across threads.
-        threads: A list of threading.Thread objects currently under this
-         Executor.
-        results: A list of result codes returned by each of the functions called
-         by this Executor.
-    """
-
-    def __init__(self):
-        self.lock = threading.Condition()
-        self.threads = []
-        self.results = []
-        self.logger = logging.getLogger(self.__class__.__name__)
-
-    def append(self, func):
-        """Append the given function to the wait list.
-
-        Once added, the function's return value will be used to determine the
-        Executor's final result value. The function must return an int result
-        code or throw an exception. For example: If two functions were added
-        to the Executor, they will both be run in parallel and their results
-        will determine whether or not the Executor succeeded. If both functions
-        returned 0, then the Executor's wait function will also return 0.
-
-        Args:
-            func: A function which returns an int result code or throws an
-             exception.
-        """
-        with self.lock:
-            thread = threading.Thread(target=lambda: self._run_fn(func), daemon=True)
-            thread.start()
-            self.threads.append(thread)
-
-    def wait(self):
-        """Wait for a result to be available.
-
-        This function waits for the executor to resolve (i.e., all
-        threads have finished).
-
-        Returns:
-            An integer result code of either the first failed function or 0 if
-            they all succeeded.
-        """
-        with self.lock:
-            self.lock.wait_for(predicate=lambda: self._is_finished)
-            return self._result
-
-    def _run_fn(self, func):
-        """Entry point to each running thread.
-
-        This function will run the function provided in the append() function.
-        The result value of the function will be used to determine the
-        Executor's result value. If the function throws any exception it will be
-        caught and -1 will be used as the assumed result value.
-
-        Args:
-            func: The function to run.
-        """
-        try:
-            result = func()
-        except Exception as ex:
-            self.logger.exception(ex)
-            result = -1
-        with self.lock:
-            self.results.append(result)
-            self.lock.notify_all()
-
-    @property
-    def _is_finished(self):
-        """Whether or not the Executor is considered to be done.
-
-        Returns:
-            True if the Executor is considered done.
-        """
-        if len(self.threads) == len(self.results):
-            return True
-        return False
-
-    @property
-    def _result(self):
-        """The result code of the Executor.
-
-        Note that _is_finished must be True for this to have any meaning.
-
-        Returns:
-            An int representing the result value of the underlying functions.
-        """
-        return next((result for result in self.results if result), 0)
diff --git a/zephyr/zmake/zmake/output_packers.py b/zephyr/zmake/zmake/output_packers.py
deleted file mode 100644
index 1ba38cf96c..0000000000
--- a/zephyr/zmake/zmake/output_packers.py
+++ /dev/null
@@ -1,230 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Types which provide many builds and composite them into a single binary."""
-import logging
-import shutil
-import subprocess
-
-import zmake.build_config as build_config
-import zmake.multiproc
-import zmake.util as util
-
-
-class BasePacker:
-    """Abstract base for all packers."""
-
-    def __init__(self, project):
-        self.project = project
-
-    def configs(self):
-        """Get all of the build configurations necessary.
-
-        Yields:
-            2-tuples of config name and a BuildConfig.
-        """
-        yield "singleimage", build_config.BuildConfig()
-
-    def pack_firmware(self, work_dir, jobclient, version_string=""):
-        """Pack a firmware image.
-
-        Config names from the configs generator are passed as keyword
-        arguments, with each argument being set to the path of the
-        build directory.
-
-        Args:
-            work_dir: A directory to write outputs and temporary files
-            into.
-            jobclient: A JobClient object to use.
-            version_string: The version string, which may end up in
-               certain parts of the outputs.
-
-        Yields:
-            2-tuples of the path of each file in the work_dir (or any
-            other directory) which should be copied into the output
-            directory, and the output filename.
-        """
-        raise NotImplementedError("Abstract method not implemented")
-
-    def _get_max_image_bytes(self):
-        """Get the maximum allowed image size (in bytes).
-
-        This value will generally be found in CONFIG_FLASH_SIZE but may vary
-        depending on the specific way things are being packed.
-
-        Returns:
-            The maximum allowed size of the image in bytes.
-        """
-        raise NotImplementedError("Abstract method not implemented")
-
-    def _is_size_bound(self, path):
-        """Check whether the given path should be constrained by size.
-
-        Generally, .elf files will be unconstrained while .bin files will be
-        constrained.
-
-        Args:
-            path: A file's path to test.
-
-        Returns:
-            True if the file size should be checked. False otherwise.
-        """
-        return path.suffix == ".bin"
-
-    def _check_packed_file_size(self, file, dirs):
-        """Check that a packed file passes size constraints.
-
-        Args:
-            file: A file to test.
-            dirs: A map of the arguments to pass to _get_max_image_bytes
-
-        Returns:
-            The file if it passes the test.
-        """
-        if not self._is_size_bound(
-            file
-        ) or file.stat().st_size <= self._get_max_image_bytes(**dirs):
-            return file
-        raise RuntimeError("Output file ({}) too large".format(file))
-
-
-class ElfPacker(BasePacker):
-    """Raw proxy for ELF output of a single build."""
-
-    def pack_firmware(self, work_dir, jobclient, singleimage, version_string=""):
-        yield singleimage / "zephyr" / "zephyr.elf", "zephyr.elf"
-
-
-class RawBinPacker(BasePacker):
-    """Raw proxy for zephyr.bin output of a single build."""
-
-    def pack_firmware(self, work_dir, jobclient, singleimage, version_string=""):
-        yield singleimage / "zephyr" / "zephyr.bin", "zephyr.bin"
-
-
-class BinmanPacker(BasePacker):
-    """Packer for RO/RW image to generate a .bin build using FMAP."""
-
-    ro_file = "zephyr.bin"
-    rw_file = "zephyr.bin"
-
-    def __init__(self, project):
-        self.logger = logging.getLogger(self.__class__.__name__)
-        super().__init__(project)
-
-    def configs(self):
-        yield "ro", build_config.BuildConfig(kconfig_defs={"CONFIG_CROS_EC_RO": "y"})
-        yield "rw", build_config.BuildConfig(kconfig_defs={"CONFIG_CROS_EC_RW": "y"})
-
-    def pack_firmware(self, work_dir, jobclient, ro, rw, version_string=""):
-        """Pack RO and RW sections using Binman.
-
-        Binman configuration is expected to be found in the RO build
-        device-tree configuration.
-
-        Args:
-            work_dir: The directory used for packing.
-            jobclient: The client used to run subprocesses.
-            ro: Directory containing the RO image build.
-            rw: Directory containing the RW image build.
-            version_string: The version string to use in FRID/FWID.
-
-        Yields:
-            2-tuples of the path of each file in the work_dir that
-            should be copied into the output directory, and the output
-            filename.
-        """
-        dts_file_path = ro / "zephyr" / "zephyr.dts"
-
-        # Copy the inputs into the work directory so that Binman can
-        # find them under a hard-coded name.
-        shutil.copy2(ro / "zephyr" / self.ro_file, work_dir / "zephyr_ro.bin")
-        shutil.copy2(rw / "zephyr" / self.rw_file, work_dir / "zephyr_rw.bin")
-
-        # Version in FRID/FWID can be at most 31 bytes long (32, minus
-        # one for null character).
-        if len(version_string) > 31:
-            version_string = version_string[:31]
-
-        proc = jobclient.popen(
-            [
-                "binman",
-                "-v",
-                "5",
-                "build",
-                "-a",
-                "version={}".format(version_string),
-                "-d",
-                dts_file_path,
-                "-m",
-                "-O",
-                work_dir,
-            ],
-            cwd=work_dir,
-            stdout=subprocess.PIPE,
-            stderr=subprocess.PIPE,
-            encoding="utf-8",
-        )
-
-        zmake.multiproc.log_output(self.logger, logging.DEBUG, proc.stdout)
-        zmake.multiproc.log_output(self.logger, logging.ERROR, proc.stderr)
-        if proc.wait(timeout=60):
-            raise OSError("Failed to run binman")
-
-        yield work_dir / "zephyr.bin", "zephyr.bin"
-        yield ro / "zephyr" / "zephyr.elf", "zephyr.ro.elf"
-        yield rw / "zephyr" / "zephyr.elf", "zephyr.rw.elf"
-
-
-class NpcxPacker(BinmanPacker):
-    """Packer for RO/RW image to generate a .bin build using FMAP.
-
-    This expects that the build is setup to generate a
-    zephyr.npcx.bin for the RO image, which should be packed using
-    Nuvoton's loader format.
-    """
-
-    ro_file = "zephyr.npcx.bin"
-    npcx_monitor = "npcx_monitor.bin"
-
-    # TODO(b/192401039): CONFIG_FLASH_SIZE is nuvoton-only.  Since
-    # binman already checks sizes, perhaps we can just remove this
-    # code?
-    def _get_max_image_bytes(self, ro, rw):
-        ro_size = util.read_kconfig_autoconf_value(
-            ro / "zephyr" / "include" / "generated", "CONFIG_FLASH_SIZE"
-        )
-        rw_size = util.read_kconfig_autoconf_value(
-            ro / "zephyr" / "include" / "generated", "CONFIG_FLASH_SIZE"
-        )
-        return max(int(ro_size, 0), int(rw_size, 0)) * 1024
-
-    # This can probably be removed too and just rely on binman to
-    # check the sizes... see the comment above.
-    def pack_firmware(self, work_dir, jobclient, ro, rw, version_string=""):
-        for path, output_file in super().pack_firmware(
-            work_dir,
-            jobclient,
-            ro,
-            rw,
-            version_string=version_string,
-        ):
-            if output_file == "zephyr.bin":
-                yield (
-                    self._check_packed_file_size(path, {"ro": ro, "rw": rw}),
-                    "zephyr.bin",
-                )
-            else:
-                yield path, output_file
-
-        # Include the NPCX monitor file as an output artifact.
-        yield ro / self.npcx_monitor, self.npcx_monitor
-
-
-# A dictionary mapping packer config names to classes.
-packer_registry = {
-    "binman": BinmanPacker,
-    "elf": ElfPacker,
-    "npcx": NpcxPacker,
-    "raw": RawBinPacker,
-}
diff --git a/zephyr/zmake/zmake/project.py b/zephyr/zmake/zmake/project.py
deleted file mode 100644
index 84151a90b3..0000000000
--- a/zephyr/zmake/zmake/project.py
+++ /dev/null
@@ -1,248 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Module for project config wrapper object."""
-
-import logging
-import pathlib
-import warnings
-
-import yaml
-
-import zmake.build_config as build_config
-import zmake.modules as modules
-import zmake.output_packers as packers
-import zmake.toolchains as toolchains
-import zmake.util as util
-
-# The version of jsonschema in the chroot has a bunch of
-# DeprecationWarnings that fire when we import it.  Suppress these
-# during the import to keep the noise down.
-with warnings.catch_warnings():
-    warnings.simplefilter("ignore")
-    import jsonschema
-
-
-def module_dts_overlay_name(modpath, board_name):
-    """Given a board name, return the expected DTS overlay path.
-
-    Args:
-        modpath: the module path as a pathlib.Path object
-        board_name: the name of the board
-
-    Returns:
-        A pathlib.Path object to the expected overlay path.
-    """
-    return modpath / "zephyr" / "dts" / "board-overlays" / "{}.dts".format(board_name)
-
-
-def find_projects(root_dir):
-    """Finds all zmake projects in root_dir.
-
-    Args:
-        root_dir: the root dir as a pathlib.Path object
-
-    Yields:
-        Project: The next project found.
-    """
-    logging.info("Finding zmake targets under '%s'.", root_dir)
-    for path in pathlib.Path(root_dir).rglob("zmake.yaml"):
-        yield Project(path.parent)
-
-
-class ProjectConfig:
-    """An object wrapping zmake.yaml."""
-
-    validator = jsonschema.Draft7Validator
-    schema = {
-        "type": "object",
-        "required": [
-            "board",
-            "output-type",
-            "supported-toolchains",
-            "supported-zephyr-versions",
-        ],
-        "properties": {
-            "supported-zephyr-versions": {
-                "type": "array",
-                "items": {
-                    "type": "string",
-                    "enum": ["v2.6"],
-                },
-                "minItems": 1,
-                "uniqueItems": True,
-            },
-            "board": {
-                "type": "string",
-            },
-            "modules": {
-                "type": "array",
-                "items": {
-                    "type": "string",
-                    "enum": list(modules.known_modules),
-                },
-            },
-            "output-type": {
-                "type": "string",
-                "enum": list(packers.packer_registry),
-            },
-            "supported-toolchains": {
-                "type": "array",
-                "items": {
-                    "type": "string",
-                    "enum": list(toolchains.support_classes),
-                },
-            },
-            "is-test": {
-                "type": "boolean",
-            },
-            "dts-overlays": {
-                "type": "array",
-                "items": {
-                    "type": "string",
-                },
-            },
-        },
-    }
-
-    def __init__(self, config_dict):
-        self.validator.check_schema(self.schema)
-        jsonschema.validate(config_dict, self.schema, cls=self.validator)
-        self.config_dict = config_dict
-
-    @property
-    def supported_zephyr_versions(self):
-        return [
-            util.parse_zephyr_version(x)
-            for x in self.config_dict["supported-zephyr-versions"]
-        ]
-
-    @property
-    def board(self):
-        return self.config_dict["board"]
-
-    @property
-    def modules(self):
-        return self.config_dict.get("modules", list(modules.known_modules))
-
-    @property
-    def output_packer(self):
-        return packers.packer_registry[self.config_dict["output-type"]]
-
-    @property
-    def supported_toolchains(self):
-        return self.config_dict["supported-toolchains"]
-
-    @property
-    def is_test(self):
-        return self.config_dict.get("is-test", False)
-
-    @property
-    def dts_overlays(self):
-        return self.config_dict.get("dts-overlays", [])
-
-
-class Project:
-    """An object encapsulating a project directory."""
-
-    def __init__(self, project_dir, config_dict=None):
-        self.project_dir = project_dir.resolve()
-        if not config_dict:
-            with open(self.project_dir / "zmake.yaml") as f:
-                config_dict = yaml.safe_load(f)
-        self.config = ProjectConfig(config_dict)
-        self.packer = self.config.output_packer(self)
-
-    def iter_builds(self):
-        """Iterate thru the build combinations provided by the project's packer.
-
-        Yields:
-            2-tuples of a build configuration name and a BuildConfig.
-        """
-        conf = build_config.BuildConfig(cmake_defs={"BOARD": self.config.board})
-        prj_conf = self.project_dir / "prj.conf"
-        if prj_conf.is_file():
-            conf |= build_config.BuildConfig(kconfig_files=[prj_conf])
-        for build_name, packer_config in self.packer.configs():
-            yield build_name, conf | packer_config
-
-    def find_dts_overlays(self, modules):
-        """Find appropriate dts overlays from registered modules.
-
-        Args:
-            modules: A dictionary of module names mapping to paths.
-
-        Returns:
-            A BuildConfig with relevant configurations to enable the
-            found DTS overlay files.
-        """
-        overlays = []
-        for module_path in modules.values():
-            dts_path = module_dts_overlay_name(module_path, self.config.board)
-            if dts_path.is_file():
-                overlays.append(dts_path.resolve())
-
-        overlays.extend(self.project_dir / f for f in self.config.dts_overlays)
-
-        if overlays:
-            return build_config.BuildConfig(
-                cmake_defs={"DTC_OVERLAY_FILE": ";".join(map(str, overlays))}
-            )
-        else:
-            return build_config.BuildConfig()
-
-    def prune_modules(self, module_paths):
-        """Reduce a modules dict to the ones required by this project.
-
-        If this project does not define a modules list in the
-        configuration, it is assumed that all known modules to Zmake
-        are required.  This is typically inconsequential as Zephyr
-        module design conventions require a Kconfig option to actually
-        enable most modules.
-
-        Args:
-            module_paths: A dictionary mapping module names to their
-                paths.  This dictionary is not modified.
-
-        Returns:
-            A new module_paths dictionary with only the modules
-            required by this project.
-
-        Raises:
-            A KeyError, if a required module is unavailable.
-        """
-        result = {}
-        for module in self.config.modules:
-            try:
-                result[module] = module_paths[module]
-            except KeyError as e:
-                raise KeyError(
-                    "The {!r} module is required by the {} project, but is not "
-                    "available.".format(module, self.project_dir)
-                ) from e
-        return result
-
-    def get_toolchain(self, module_paths, override=None):
-        if override:
-            if override not in self.config.supported_toolchains:
-                logging.warning(
-                    "Toolchain %r isn't supported by this project. You're on your own.",
-                    override,
-                )
-            support_class = toolchains.support_classes.get(
-                override, toolchains.GenericToolchain
-            )
-            return support_class(name=override, modules=module_paths)
-        else:
-            for name in self.config.supported_toolchains:
-                support_class = toolchains.support_classes[name]
-                toolchain = support_class(name=name, modules=module_paths)
-                if toolchain.probe():
-                    logging.info("Toolchain %r selected by probe function.", toolchain)
-                    return toolchain
-            raise OSError(
-                "No supported toolchains could be found on your system. If you see "
-                "this message in the chroot, it indicates a bug. Otherwise, you'll "
-                "either want to setup your system with a supported toolchain, or "
-                "manually select an unsupported toolchain with the -t flag."
-            )
diff --git a/zephyr/zmake/zmake/toolchains.py b/zephyr/zmake/zmake/toolchains.py
deleted file mode 100644
index 924448aec5..0000000000
--- a/zephyr/zmake/zmake/toolchains.py
+++ /dev/null
@@ -1,154 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Definitions of toolchain variables."""
-
-import os
-import pathlib
-
-import zmake.build_config as build_config
-
-
-class GenericToolchain:
-    """Default toolchain if not known to zmake.
-
-    Simply pass ZEPHYR_TOOLCHAIN_VARIANT=name to the build, with
-    nothing extra.
-    """
-
-    def __init__(self, name, modules=None):
-        self.name = name
-        self.modules = modules or {}
-
-    def probe(self):
-        """Probe if the toolchain is available on the system."""
-        # Since the toolchain is not known to zmake, we have no way to
-        # know if it's installed.  Simply return False to indicate not
-        # installed.  An unknown toolchain would only be used if -t
-        # was manually passed to zmake, and is not valid to put in a
-        # zmake.yaml file.
-        return False
-
-    def get_build_config(self):
-        """Get the build configuration for the toolchain.
-
-        Returns:
-            A build_config.BuildConfig to be applied to the build.
-        """
-        return build_config.BuildConfig(
-            cmake_defs={
-                "ZEPHYR_TOOLCHAIN_VARIANT": self.name,
-            },
-        )
-
-
-class CorebootSdkToolchain(GenericToolchain):
-    def probe(self):
-        # For now, we always assume it's at /opt/coreboot-sdk, since
-        # that's where it's installed in the chroot.  We may want to
-        # consider adding support for a coreboot-sdk built in the
-        # user's home directory, for example, which happens if a
-        # "make crossgcc" is done from the coreboot repository.
-        return pathlib.Path("/opt/coreboot-sdk").is_dir()
-
-    def get_build_config(self):
-        return (
-            build_config.BuildConfig(
-                cmake_defs={
-                    "TOOLCHAIN_ROOT": str(self.modules["ec"] / "zephyr"),
-                },
-            )
-            | super().get_build_config()
-        )
-
-
-class ZephyrToolchain(GenericToolchain):
-    def __init__(self, *args, **kwargs):
-        self.zephyr_sdk_install_dir = self._find_zephyr_sdk()
-        super().__init__(*args, **kwargs)
-
-    @staticmethod
-    def _find_zephyr_sdk():
-        """Find the Zephyr SDK, if it's installed.
-
-        Returns:
-            The path to the Zephyr SDK, using the search rules defined by
-            https://docs.zephyrproject.org/latest/getting_started/installation_linux.html,
-            or None, if one cannot be found on the system.
-        """
-        from_env = os.getenv("ZEPHYR_SDK_INSTALL_DIR")
-        if from_env:
-            return pathlib.Path(from_env)
-
-        def _gen_sdk_paths():
-            for prefix in (
-                "~",
-                "~/.local",
-                "~/.local/opt",
-                "~/bin",
-                "/opt",
-                "/usr",
-                "/usr/local",
-            ):
-                prefix = pathlib.Path(os.path.expanduser(prefix))
-                yield prefix / "zephyr-sdk"
-                yield from prefix.glob("zephyr-sdk-*")
-
-        for path in _gen_sdk_paths():
-            if (path / "sdk_version").is_file():
-                return path
-
-        return None
-
-    def probe(self):
-        return bool(self.zephyr_sdk_install_dir)
-
-    def get_build_config(self):
-        assert self.zephyr_sdk_install_dir
-        tc_vars = {
-            "ZEPHYR_SDK_INSTALL_DIR": str(self.zephyr_sdk_install_dir),
-        }
-        return (
-            build_config.BuildConfig(
-                environ_defs=tc_vars,
-                cmake_defs=tc_vars,
-            )
-            | super().get_build_config()
-        )
-
-
-class LlvmToolchain(GenericToolchain):
-    def probe(self):
-        # TODO: differentiate chroot llvm path vs. something more
-        # generic?
-        return pathlib.Path("/usr/bin/x86_64-pc-linux-gnu-clang").exists()
-
-    def get_build_config(self):
-        # TODO: this contains custom settings for the chroot.  Plumb a
-        # toolchain for "generic-llvm" for external uses?
-        return (
-            build_config.BuildConfig(
-                cmake_defs={
-                    "TOOLCHAIN_ROOT": str(self.modules["ec"] / "zephyr"),
-                },
-            )
-            | super().get_build_config()
-        )
-
-
-class HostToolchain(GenericToolchain):
-    def probe(self):
-        # "host" toolchain for Zephyr means GCC.
-        for search_path in os.getenv("PATH", "/usr/bin").split(":"):
-            if (pathlib.Path(search_path) / "gcc").exists():
-                return True
-        return False
-
-
-# Mapping of toolchain names -> support class
-support_classes = {
-    "coreboot-sdk": CorebootSdkToolchain,
-    "host": HostToolchain,
-    "llvm": LlvmToolchain,
-    "zephyr": ZephyrToolchain,
-}
diff --git a/zephyr/zmake/zmake/util.py b/zephyr/zmake/zmake/util.py
deleted file mode 100644
index 455cb7c9d6..0000000000
--- a/zephyr/zmake/zmake/util.py
+++ /dev/null
@@ -1,255 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Common miscellaneous utility functions for zmake."""
-
-import os
-import pathlib
-import re
-import shlex
-
-
-def c_str(input_str):
-    """Make a string that can be included as a literal in C source code.
-
-    Args:
-        input_str: The string to process.
-
-    Returns:
-        A string which can be included in C source code.
-    """
-
-    def c_chr(char):
-        # Convert a char in a string to the C representation.  Per the
-        # C standard, we can use all characters but quote, newline,
-        # and backslash directly with no replacements.
-        return {
-            '"': r"\"",
-            "\n": r"\n",
-            "\\": "\\\\",
-        }.get(char, char)
-
-    return '"{}"'.format("".join(map(c_chr, input_str)))
-
-
-def locate_cros_checkout():
-    """Find the path to the ChromiumOS checkout.
-
-    Returns:
-        The first directory found with a .repo directory in it,
-        starting by checking the CROS_WORKON_SRCROOT environment
-        variable, then scanning upwards from the current directory,
-        and finally from a known set of common paths.
-    """
-
-    def propose_checkouts():
-        yield os.getenv("CROS_WORKON_SRCROOT")
-
-        path = pathlib.Path.cwd()
-        while path.resolve() != pathlib.Path("/"):
-            yield path
-            path = path / ".."
-
-        yield "/mnt/host/source"
-        yield pathlib.Path.home() / "trunk"
-        yield pathlib.Path.home() / "chromiumos"
-
-    for path in propose_checkouts():
-        if not path:
-            continue
-        path = pathlib.Path(path)
-        if (path / ".repo").is_dir():
-            return path.resolve()
-
-    raise FileNotFoundError("Unable to locate a ChromiumOS checkout")
-
-
-def locate_zephyr_base(checkout, version):
-    """Locate the path to the Zephyr RTOS in a ChromiumOS checkout.
-
-    Args:
-        checkout: The path to the ChromiumOS checkout.
-        version: The requested zephyr version, as a tuple of integers.
-
-    Returns:
-        The path to the Zephyr source.
-    """
-    return (
-        checkout
-        / "src"
-        / "third_party"
-        / "zephyr"
-        / "main"
-        / "v{}.{}".format(*version[:2])
-    )
-
-
-def read_kconfig_file(path):
-    """Parse a Kconfig file.
-
-    Args:
-        path: The path to open.
-
-    Returns:
-        A dictionary of kconfig items to their values.
-    """
-    result = {}
-    with open(path) as f:
-        for line in f:
-            line, _, _ = line.partition("#")
-            line = line.strip()
-            if line:
-                name, _, value = line.partition("=")
-                result[name.strip()] = value.strip()
-    return result
-
-
-def read_kconfig_autoconf_value(path, key):
-    """Parse an autoconf.h file for a resolved kconfig value
-
-    Args:
-        path: The path to the autoconf.h file.
-        key: The define key to lookup.
-
-    Returns:
-        The value associated with the key or nothing if the key wasn't found.
-    """
-    prog = re.compile(r"^#define\s{}\s(\S+)$".format(key))
-    with open(path / "autoconf.h") as f:
-        for line in f:
-            m = prog.match(line)
-            if m:
-                return m.group(1)
-
-
-def write_kconfig_file(path, config, only_if_changed=True):
-    """Write out a dictionary to Kconfig format.
-
-    Args:
-        path: The path to write to.
-        config: The dictionary to write.
-        only_if_changed: Set to True if the file should not be written
-            unless it has changed.
-    """
-    if only_if_changed:
-        if path.exists() and read_kconfig_file(path) == config:
-            return
-    with open(path, "w") as f:
-        for name, value in config.items():
-            f.write("{}={}\n".format(name, value))
-
-
-def parse_zephyr_version(version_string):
-    """Parse a human-readable version string (e.g., "v2.4") as a tuple.
-
-    Args:
-        version_string: The human-readable version string.
-
-    Returns:
-        A 2-tuple or 3-tuple of integers representing the version.
-    """
-    match = re.fullmatch(r"v?(\d+)[._](\d+)(?:[._](\d+))?", version_string)
-    if not match:
-        raise ValueError(
-            "{} does not look like a Zephyr version.".format(version_string)
-        )
-    return tuple(int(x) for x in match.groups() if x is not None)
-
-
-def read_zephyr_version(zephyr_base):
-    """Read the Zephyr version from a Zephyr OS checkout.
-
-    Args:
-         zephyr_base: path to the Zephyr OS repository.
-
-    Returns:
-         A 3-tuple of the version number (major, minor, patchset).
-    """
-    version_file = pathlib.Path(zephyr_base) / "VERSION"
-
-    file_vars = {}
-    with open(version_file) as f:
-        for line in f:
-            key, sep, value = line.partition("=")
-            file_vars[key.strip()] = value.strip()
-
-    return (
-        int(file_vars["VERSION_MAJOR"]),
-        int(file_vars["VERSION_MINOR"]),
-        int(file_vars["PATCHLEVEL"]),
-    )
-
-
-def repr_command(argv):
-    """Represent an argument array as a string.
-
-    Args:
-        argv: The arguments of the command.
-
-    Returns:
-        A string which could be pasted into a shell for execution.
-    """
-    return " ".join(shlex.quote(str(arg)) for arg in argv)
-
-
-def update_symlink(target_path, link_path):
-    """Create a symlink if it does not exist, or links to a different path.
-
-    Args:
-        target_path: A Path-like object of the desired symlink path.
-        link_path: A Path-like object of the symlink.
-    """
-    target = target_path.resolve()
-    if (
-        not link_path.is_symlink()
-        or pathlib.Path(os.readlink(link_path)).resolve() != target
-    ):
-        if link_path.exists():
-            link_path.unlink()
-        link_path.symlink_to(target)
-
-
-def log_multi_line(logger, level, message):
-    """Log a potentially multi-line message to the logger.
-
-    Args:
-        logger: The Logger object to log to.
-        level: The logging level to use when logging.
-        message: The (potentially) multi-line message to log.
-    """
-    for line in message.splitlines():
-        if line:
-            logger.log(level, line)
-
-
-def resolve_build_dir(platform_ec_dir, project_dir, build_dir):
-    """Resolve the build directory using platform/ec/build/... as default.
-
-    Args:
-        platform_ec_dir: The path to the chromiumos source's platform/ec
-          directory.
-        project_dir: The directory of the project.
-        build_dir: The directory to build in (may be None).
-    Returns:
-        The resolved build directory (using build_dir if not None).
-    """
-    if build_dir:
-        return build_dir
-
-    if not pathlib.Path.exists(project_dir / "zmake.yaml"):
-        raise OSError("Invalid configuration")
-
-    # Resolve project_dir to absolute path.
-    project_dir = project_dir.resolve()
-
-    # Compute the path of project_dir relative to platform_ec_dir.
-    project_relative_path = pathlib.Path.relative_to(project_dir, platform_ec_dir)
-
-    # Make sure that the project_dir is a subdirectory of platform_ec_dir.
-    if platform_ec_dir / project_relative_path != project_dir:
-        raise OSError(
-            "Can't resolve project directory {} which is not a subdirectory"
-            " of the platform/ec directory {}".format(project_dir, platform_ec_dir)
-        )
-
-    return platform_ec_dir / "build" / project_relative_path
diff --git a/zephyr/zmake/zmake/version.py b/zephyr/zmake/zmake/version.py
deleted file mode 100644
index 47aba6d804..0000000000
--- a/zephyr/zmake/zmake/version.py
+++ /dev/null
@@ -1,166 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-import datetime
-import getpass
-import io
-import os
-import platform
-import subprocess
-
-import zmake.util as util
-
-
-def _get_num_commits(repo):
-    """Get the number of commits that have been made.
-
-    If a Git repository is available, return the number of commits that have
-    been made. Otherwise return a fixed count.
-
-    Args:
-        repo: The path to the git repo.
-
-    Returns:
-        An integer, the number of commits that have been made.
-    """
-    try:
-        result = subprocess.run(
-            ["git", "-C", repo, "rev-list", "HEAD", "--count"],
-            check=True,
-            stdout=subprocess.PIPE,
-            stderr=subprocess.DEVNULL,
-            encoding="utf-8",
-        )
-    except subprocess.CalledProcessError:
-        commits = "9999"
-    else:
-        commits = result.stdout
-
-    return int(commits)
-
-
-def _get_revision(repo):
-    """Get the current revision hash.
-
-    If a Git repository is available, return the hash of the current index.
-    Otherwise return the hash of the VCSID environment variable provided by
-    the packaging system.
-
-    Args:
-        repo: The path to the git repo.
-
-    Returns:
-        A string, of the current revision.
-    """
-    try:
-        result = subprocess.run(
-            ["git", "-C", repo, "log", "-n1", "--format=%H"],
-            check=True,
-            stdout=subprocess.PIPE,
-            stderr=subprocess.DEVNULL,
-            encoding="utf-8",
-        )
-    except subprocess.CalledProcessError:
-        # Fall back to the VCSID provided by the packaging system.
-        # Format is 0.0.1-r425-032666c418782c14fe912ba6d9f98ffdf0b941e9 for
-        # releases and 9999-032666c418782c14fe912ba6d9f98ffdf0b941e9 for
-        # 9999 ebuilds.
-        vcsid = os.environ.get("VCSID", "9999-unknown")
-        revision = vcsid.rsplit("-", 1)[1]
-    else:
-        revision = result.stdout
-
-    return revision
-
-
-def get_version_string(project, zephyr_base, modules, static=False):
-    """Get the version string associated with a build.
-
-    Args:
-        project: a zmake.project.Project object
-        zephyr_base: the path to the zephyr directory
-        modules: a dictionary mapping module names to module paths
-        static: if set, create a version string not dependent on git
-            commits, thus allowing binaries to be compared between two
-            commits.
-
-    Returns:
-        A version string which can be placed in FRID, FWID, or used in
-        the build for the OS.
-    """
-    major_version, minor_version, *_ = util.read_zephyr_version(zephyr_base)
-    project_id = project.project_dir.parts[-1]
-    num_commits = 0
-
-    if static:
-        vcs_hashes = "STATIC"
-    else:
-        repos = {
-            "os": zephyr_base,
-            **modules,
-        }
-
-        for repo in repos.values():
-            num_commits += _get_num_commits(repo)
-
-        vcs_hashes = ",".join(
-            "{}:{}".format(name, _get_revision(repo)[:6])
-            for name, repo in sorted(
-                repos.items(),
-                # Put the EC module first, then Zephyr OS kernel, as
-                # these are probably the most important hashes to
-                # developers.
-                key=lambda p: (p[0] != "ec", p[0] != "os", p),
-            )
-        )
-
-    return "{}_v{}.{}.{}-{}".format(
-        project_id, major_version, minor_version, num_commits, vcs_hashes
-    )
-
-
-def write_version_header(version_str, output_path, static=False):
-    """Generate a version header and write it to the specified path.
-
-    Generate a version header in the format expected by the EC build
-    system, and write it out only if the version header does not exist
-    or changes.  We don't write in the case that the version header
-    does exist and was unchanged, which allows "zmake build" commands
-    on an unchanged tree to be an effective no-op.
-
-    Args:
-        version_str: The version string to be used in the header, such
-            as one generated by get_version_string.
-        output_path: The file path to write at (a pathlib.Path
-            object).
-        static: If true, generate a header which does not include
-            information like the username, hostname, or date, allowing
-            the build to be reproducible.
-    """
-    output = io.StringIO()
-    output.write("/* This file is automatically generated by zmake */\n")
-
-    def add_def(name, value):
-        output.write("#define {} {}\n".format(name, util.c_str(value)))
-
-    def add_def_unquoted(name, value):
-        output.write("#define {} {}\n".format(name, value))
-
-    add_def("VERSION", version_str)
-    add_def("CROS_EC_VERSION32", version_str[:31])
-
-    if static:
-        add_def("BUILDER", "reproducible@build")
-        add_def("DATE", "STATIC_VERSION_DATE")
-    else:
-        add_def("BUILDER", "{}@{}".format(getpass.getuser(), platform.node()))
-        add_def("DATE", datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S"))
-
-    add_def("CROS_FWID_MISSING_STR", "CROS_FWID_MISSING")
-    # TODO(b/198475757): Add zmake support for getting CROS_FWID32
-    add_def_unquoted("CROS_FWID32", "CROS_FWID_MISSING_STR")
-
-    contents = output.getvalue()
-    if not output_path.exists() or output_path.read_text() != contents:
-        output_path.write_text(contents)
diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py
deleted file mode 100644
index 1b60e66f66..0000000000
--- a/zephyr/zmake/zmake/zmake.py
+++ /dev/null
@@ -1,757 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module encapsulating Zmake wrapper object."""
-import logging
-import os
-import pathlib
-import re
-import shutil
-import subprocess
-import tempfile
-
-import zmake.build_config
-import zmake.jobserver
-import zmake.modules
-import zmake.multiproc
-import zmake.project
-import zmake.util as util
-import zmake.version
-
-ninja_warnings = re.compile(r"^(\S*: )?warning:.*")
-ninja_errors = re.compile(r"error:.*")
-
-
-def ninja_stdout_log_level_override(line, current_log_level):
-    """Update the log level for ninja builds if we hit an error.
-
-    Ninja builds prints everything to stdout, but really we want to start
-    logging things to CRITICAL
-
-    Args:
-        line: The line that is about to be logged.
-        current_log_level: The active logging level that would be used for the
-          line.
-    """
-    # Output lines from Zephyr that are not normally useful
-    # Send any lines that start with these strings to INFO
-    cmake_suppress = [
-        "-- ",  # device tree messages
-        "Loaded configuration",
-        "Including boilerplate",
-        "Parsing ",
-        "No change to configuration",
-        "No change to Kconfig header",
-    ]
-
-    # Herewith a long list of things which are really for debugging, not
-    # development. Return logging.DEBUG for each of these.
-
-    # ninja puts progress information on stdout
-    if line.startswith("["):
-        return logging.DEBUG
-    # we don't care about entering directories since it happens every time
-    if line.startswith("ninja: Entering directory"):
-        return logging.DEBUG
-    # we know the build stops from the compiler messages and ninja return code
-    if line.startswith("ninja: build stopped"):
-        return logging.DEBUG
-    # someone prints a *** SUCCESS *** message which we don't need
-    if line.startswith("***"):
-        return logging.DEBUG
-    # dopey ninja puts errors on stdout, so fix that. It does not look
-    # likely that it will be fixed upstream:
-    # https://github.com/ninja-build/ninja/issues/1537
-    # Try to drop output about the device tree
-    if any(line.startswith(x) for x in cmake_suppress):
-        return logging.INFO
-    # this message is a bit like make failing. We already got the error output.
-    if line.startswith("FAILED: CMakeFiles"):
-        return logging.INFO
-    # if a particular file fails it shows the build line used, but that is not
-    # useful except for debugging.
-    if line.startswith("ccache"):
-        return logging.DEBUG
-    if ninja_warnings.match(line):
-        return logging.WARNING
-    if ninja_errors.match(line):
-        return logging.ERROR
-    # When we see "Memory region" go into INFO, and stay there as long as the
-    # line starts with \S+:
-    if line.startswith("Memory region"):
-        return logging.INFO
-    if current_log_level == logging.INFO and line.split()[0].endswith(":"):
-        return current_log_level
-    if current_log_level == logging.WARNING:
-        return current_log_level
-    return logging.ERROR
-
-
-def cmake_log_level_override(line, default_log_level):
-    """Update the log level for cmake output if we hit an error.
-
-    Cmake prints some messages that are less than useful during
-    development.
-
-    Args:
-        line: The line that is about to be logged.
-        default_log_level: The default logging level that will be used for the
-          line.
-    """
-    # Strange output from Zephyr that we normally ignore
-    if line.startswith("Including boilerplate"):
-        return logging.DEBUG
-    elif line.startswith("devicetree error:"):
-        return logging.ERROR
-    if ninja_warnings.match(line):
-        return logging.WARNING
-    if ninja_errors.match(line):
-        return logging.ERROR
-    return default_log_level
-
-
-def get_process_failure_msg(proc):
-    """Creates a suitable failure message if something exits badly
-
-    Args:
-        proc: subprocess.Popen object containing the thing that failed
-
-    Returns:
-        Failure message as a string:
-    """
-    return "Execution failed (return code={}): {}\n".format(
-        proc.returncode, util.repr_command(proc.args)
-    )
-
-
-class Zmake:
-    """Wrapper class encapsulating zmake's supported operations.
-
-    The invocations of the constructor and the methods actually comes
-    from the main function.  The command line arguments are translated
-    such that dashes are replaced with underscores and applied as
-    keyword arguments to the constructor and the method, and the
-    subcommand invoked becomes the method run.
-
-    As such, you won't find documentation for each method's parameters
-    here, as it would be duplicate of the help strings from the
-    command line.  Run "zmake --help" for full documentation of each
-    parameter.
-
-    Properties:
-        executor: a zmake.multiproc.Executor object for submitting
-            tasks to.
-        _sequential: True to check the results of each build job sequentially,
-            before launching more, False to just do this after all jobs complete
-    """
-
-    def __init__(
-        self, checkout=None, jobserver=None, jobs=0, modules_dir=None, zephyr_base=None
-    ):
-        zmake.multiproc.reset()
-        self._checkout = checkout
-        self._zephyr_base = zephyr_base
-
-        if modules_dir:
-            self.module_paths = zmake.modules.locate_from_directory(modules_dir)
-        else:
-            self.module_paths = zmake.modules.locate_from_checkout(self.checkout)
-
-        if jobserver:
-            self.jobserver = jobserver
-        else:
-            try:
-                self.jobserver = zmake.jobserver.GNUMakeJobClient.from_environ()
-            except OSError:
-                self.jobserver = zmake.jobserver.GNUMakeJobServer(jobs=jobs)
-
-        self.logger = logging.getLogger(self.__class__.__name__)
-        self.executor = zmake.multiproc.Executor()
-        self._sequential = jobs == 1
-
-    @property
-    def checkout(self):
-        if not self._checkout:
-            self._checkout = util.locate_cros_checkout()
-        return self._checkout.resolve()
-
-    def locate_zephyr_base(self, version):
-        """Locate the Zephyr OS repository.
-
-        Args:
-            version: If a Zephyr OS base was not supplied to Zmake,
-                which version to search for as a tuple of integers.
-                This argument is ignored if a Zephyr base was supplied
-                to Zmake.
-        Returns:
-            A pathlib.Path to the found Zephyr OS repository.
-        """
-        if self._zephyr_base:
-            return self._zephyr_base
-
-        return util.locate_zephyr_base(self.checkout, version)
-
-    def configure(
-        self,
-        project_dir,
-        build_dir=None,
-        toolchain=None,
-        ignore_unsupported_zephyr_version=False,
-        build_after_configure=False,
-        test_after_configure=False,
-        bringup=False,
-        coverage=False,
-    ):
-        """Set up a build directory to later be built by "zmake build"."""
-        project = zmake.project.Project(project_dir)
-        supported_versions = project.config.supported_zephyr_versions
-
-        zephyr_base = self.locate_zephyr_base(max(supported_versions)).resolve()
-
-        # Ignore the patchset from the Zephyr version.
-        zephyr_version = util.read_zephyr_version(zephyr_base)[:2]
-
-        if (
-            not ignore_unsupported_zephyr_version
-            and zephyr_version not in supported_versions
-        ):
-            raise ValueError(
-                "The Zephyr OS version (v{}.{}) is not supported by the "
-                "project.  You may wish to either configure zmake.yaml to "
-                "support this version, or pass "
-                "--ignore-unsupported-zephyr-version.".format(*zephyr_version)
-            )
-
-        # Resolve build_dir if needed.
-        build_dir = util.resolve_build_dir(
-            platform_ec_dir=self.module_paths["ec"],
-            project_dir=project_dir,
-            build_dir=build_dir,
-        )
-        # Make sure the build directory is clean.
-        if os.path.exists(build_dir):
-            self.logger.info("Clearing old build directory %s", build_dir)
-            shutil.rmtree(build_dir)
-
-        generated_include_dir = (build_dir / "include").resolve()
-        base_config = zmake.build_config.BuildConfig(
-            environ_defs={"ZEPHYR_BASE": str(zephyr_base), "PATH": "/usr/bin"},
-            cmake_defs={
-                "DTS_ROOT": str(self.module_paths["ec"] / "zephyr"),
-                "SYSCALL_INCLUDE_DIRS": str(
-                    self.module_paths["ec"] / "zephyr" / "include" / "drivers"
-                ),
-                "ZMAKE_INCLUDE_DIR": str(generated_include_dir),
-            },
-        )
-
-        # Prune the module paths to just those required by the project.
-        module_paths = project.prune_modules(self.module_paths)
-
-        module_config = zmake.modules.setup_module_symlinks(
-            build_dir / "modules", module_paths
-        )
-
-        # Symlink the Zephyr base into the build directory so it can
-        # be used in the build phase.
-        util.update_symlink(zephyr_base, build_dir / "zephyr_base")
-
-        dts_overlay_config = project.find_dts_overlays(module_paths)
-
-        toolchain_support = project.get_toolchain(module_paths, override=toolchain)
-        toolchain_config = toolchain_support.get_build_config()
-
-        if bringup:
-            base_config |= zmake.build_config.BuildConfig(
-                kconfig_defs={"CONFIG_PLATFORM_EC_BRINGUP": "y"}
-            )
-        if coverage:
-            base_config |= zmake.build_config.BuildConfig(
-                kconfig_defs={"CONFIG_COVERAGE": "y"}
-            )
-
-        if not build_dir.exists():
-            build_dir = build_dir.mkdir()
-        if not generated_include_dir.exists():
-            generated_include_dir.mkdir()
-        processes = []
-        self.logger.info("Building %s in %s.", project_dir, build_dir)
-        for build_name, build_config in project.iter_builds():
-            self.logger.info("Configuring %s:%s.", project_dir, build_name)
-            config = (
-                base_config
-                | toolchain_config
-                | module_config
-                | dts_overlay_config
-                | build_config
-            )
-            output_dir = build_dir / "build-{}".format(build_name)
-            kconfig_file = build_dir / "kconfig-{}.conf".format(build_name)
-            proc = config.popen_cmake(
-                self.jobserver,
-                project_dir,
-                output_dir,
-                kconfig_file,
-                stdin=subprocess.DEVNULL,
-                stdout=subprocess.PIPE,
-                stderr=subprocess.PIPE,
-                encoding="utf-8",
-                errors="replace",
-            )
-            job_id = "{}:{}".format(project_dir, build_name)
-            zmake.multiproc.log_output(
-                self.logger,
-                logging.DEBUG,
-                proc.stdout,
-                log_level_override_func=cmake_log_level_override,
-                job_id=job_id,
-            )
-            zmake.multiproc.log_output(
-                self.logger,
-                logging.ERROR,
-                proc.stderr,
-                log_level_override_func=cmake_log_level_override,
-                job_id=job_id,
-            )
-            if self._sequential:
-                if proc.wait():
-                    raise OSError(get_process_failure_msg(proc))
-            else:
-                processes.append(proc)
-        for proc in processes:
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-
-        # Create symlink to project
-        util.update_symlink(project_dir, build_dir / "project")
-
-        if test_after_configure:
-            return self.test(build_dir=build_dir)
-        elif build_after_configure:
-            return self.build(build_dir=build_dir)
-
-    def build(self, build_dir, output_files_out=None, fail_on_warnings=False):
-        """Build a pre-configured build directory."""
-
-        def wait_and_check_success(procs, writers):
-            """Wait for processes to complete and check for errors
-
-            Args:
-                procs: List of subprocess.Popen objects to check
-                writers: List of LogWriter objects to check
-
-            Returns:
-                True if all if OK
-                False if an error was found (so that zmake should exit)
-            """
-            bad = None
-            for proc in procs:
-                if proc.wait() and not bad:
-                    bad = proc
-            if bad:
-                # Just show the first bad process for now. Both builds likely
-                # produce the same error anyway. If they don't, the user can
-                # still take action on the errors/warnings provided. Showing
-                # multiple 'Execution failed' messages is not very friendly
-                # since it exposes the fragmented nature of the build.
-                raise OSError(get_process_failure_msg(bad))
-
-            # Let all output be produced before exiting
-            for writer in writers:
-                writer.wait()
-            if fail_on_warnings and any(
-                w.has_written(logging.WARNING) or w.has_written(logging.ERROR)
-                for w in writers
-            ):
-                self.logger.warning("zmake: Warnings detected in build: aborting")
-                return False
-            return True
-
-        procs = []
-        log_writers = []
-        dirs = {}
-
-        build_dir = build_dir.resolve()
-        project = zmake.project.Project(build_dir / "project")
-
-        # Compute the version string.
-        version_string = zmake.version.get_version_string(
-            project,
-            build_dir / "zephyr_base",
-            zmake.modules.locate_from_directory(build_dir / "modules"),
-        )
-
-        # The version header needs to generated during the build phase
-        # instead of configure, as the tree may have changed since
-        # configure was run.
-        zmake.version.write_version_header(
-            version_string,
-            build_dir / "include" / "ec_version.h",
-        )
-
-        for build_name, build_config in project.iter_builds():
-            with self.jobserver.get_job():
-                dirs[build_name] = build_dir / "build-{}".format(build_name)
-                cmd = ["/usr/bin/ninja", "-C", dirs[build_name].as_posix()]
-                self.logger.info(
-                    "Building %s:%s: %s",
-                    build_dir,
-                    build_name,
-                    zmake.util.repr_command(cmd),
-                )
-                proc = self.jobserver.popen(
-                    cmd,
-                    stdout=subprocess.PIPE,
-                    stderr=subprocess.PIPE,
-                    encoding="utf-8",
-                    errors="replace",
-                )
-                job_id = "{}:{}".format(build_dir, build_name)
-                out = zmake.multiproc.log_output(
-                    logger=self.logger,
-                    log_level=logging.INFO,
-                    file_descriptor=proc.stdout,
-                    log_level_override_func=ninja_stdout_log_level_override,
-                    job_id=job_id,
-                )
-                err = zmake.multiproc.log_output(
-                    self.logger,
-                    logging.ERROR,
-                    proc.stderr,
-                    job_id=job_id,
-                )
-
-                if self._sequential:
-                    if not wait_and_check_success([proc], [out, err]):
-                        return 2
-                else:
-                    procs.append(proc)
-                    log_writers += [out, err]
-
-        if not wait_and_check_success(procs, log_writers):
-            return 2
-
-        # Run the packer.
-        packer_work_dir = build_dir / "packer"
-        output_dir = build_dir / "output"
-        for d in output_dir, packer_work_dir:
-            if not d.exists():
-                d.mkdir()
-
-        if output_files_out is None:
-            output_files_out = []
-        for output_file, output_name in project.packer.pack_firmware(
-            packer_work_dir, self.jobserver, version_string=version_string, **dirs
-        ):
-            shutil.copy2(output_file, output_dir / output_name)
-            self.logger.debug("Output file '%s' created.", output_file)
-            output_files_out.append(output_file)
-
-        return 0
-
-    def test(self, build_dir):
-        """Test a build directory."""
-        procs = []
-        output_files = []
-        self.build(build_dir, output_files_out=output_files)
-
-        # If the project built but isn't a test, just bail.
-        project = zmake.project.Project(build_dir / "project")
-        if not project.config.is_test:
-            return 0
-
-        for output_file in output_files:
-            self.logger.info("Running tests in %s.", output_file)
-            with self.jobserver.get_job():
-                proc = self.jobserver.popen(
-                    [output_file],
-                    stdout=subprocess.PIPE,
-                    stderr=subprocess.PIPE,
-                    encoding="utf-8",
-                    errors="replace",
-                )
-                job_id = "test {}".format(output_file)
-                zmake.multiproc.log_output(
-                    self.logger,
-                    logging.DEBUG,
-                    proc.stdout,
-                    job_id=job_id,
-                )
-                zmake.multiproc.log_output(
-                    self.logger,
-                    logging.ERROR,
-                    proc.stderr,
-                    job_id=job_id,
-                )
-                procs.append(proc)
-
-        for idx, proc in enumerate(procs):
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-        return 0
-
-    def testall(self):
-        """Test all the valid test targets"""
-        tmp_dirs = []
-        for project in zmake.project.find_projects(self.module_paths["ec"] / "zephyr"):
-            is_test = project.config.is_test
-            temp_build_dir = tempfile.mkdtemp(
-                suffix="-{}".format(os.path.basename(project.project_dir.as_posix())),
-                prefix="zbuild-",
-            )
-            tmp_dirs.append(temp_build_dir)
-            # Configure and run the test.
-            self.executor.append(
-                func=lambda: self.configure(
-                    project_dir=project.project_dir,
-                    build_dir=pathlib.Path(temp_build_dir),
-                    build_after_configure=True,
-                    test_after_configure=is_test,
-                )
-            )
-
-        rv = self.executor.wait()
-        for tmpdir in tmp_dirs:
-            shutil.rmtree(tmpdir)
-        return rv
-
-    def _run_lcov(self, build_dir, lcov_file, initial=False, gcov=""):
-        gcov = os.path.abspath(gcov)
-        with self.jobserver.get_job():
-            if initial:
-                self.logger.info("Running (initial) lcov on %s.", build_dir)
-            else:
-                self.logger.info("Running lcov on %s.", build_dir)
-            cmd = [
-                "/usr/bin/lcov",
-                "--gcov-tool",
-                gcov,
-                "-q",
-                "-o",
-                "-",
-                "-c",
-                "-d",
-                build_dir,
-                "-t",
-                lcov_file.stem,
-                "--exclude",
-                "*/build-*/zephyr/*/generated/*",
-                "--exclude",
-                "*/ec/test/*",
-                "--exclude",
-                "*/ec/zephyr/shim/chip/npcx/npcx_monitor/*",
-                "--exclude",
-                "*/ec/zephyr/emul/*",
-                "--exclude",
-                "*/ec/zephyr/test/*",
-                "--exclude",
-                "*/testsuite/*",
-                "--exclude",
-                "*/subsys/emul/*",
-            ]
-            if initial:
-                cmd += ["-i"]
-            proc = self.jobserver.popen(
-                cmd,
-                stdout=subprocess.PIPE,
-                stderr=subprocess.PIPE,
-                encoding="utf-8",
-                errors="replace",
-            )
-            zmake.multiproc.log_output(
-                self.logger,
-                logging.WARNING,
-                proc.stderr,
-                job_id="{}-lcov".format(build_dir),
-            )
-
-            with open(lcov_file, "w") as outfile:
-                for line in proc.stdout:
-                    if line.startswith("SF:"):
-                        path = line[3:].rstrip()
-                        outfile.write("SF:%s\n" % os.path.realpath(path))
-                    else:
-                        outfile.write(line)
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-
-            return 0
-
-    def _coverage_compile_only(self, project, build_dir, lcov_file):
-        self.logger.info("Building %s in %s", project.project_dir, build_dir)
-        rv = self.configure(
-            project_dir=project.project_dir,
-            build_dir=build_dir,
-            build_after_configure=False,
-            test_after_configure=False,
-            coverage=True,
-        )
-        if rv:
-            return rv
-
-        # Compute the version string.
-        version_string = zmake.version.get_version_string(
-            project,
-            build_dir / "zephyr_base",
-            zmake.modules.locate_from_directory(build_dir / "modules"),
-        )
-
-        # The version header needs to generated during the build phase
-        # instead of configure, as the tree may have changed since
-        # configure was run.
-        zmake.version.write_version_header(
-            version_string,
-            build_dir / "include" / "ec_version.h",
-        )
-
-        # Use ninja to compile the all.libraries target.
-        build_project = zmake.project.Project(build_dir / "project")
-
-        procs = []
-        dirs = {}
-        gcov = "gcov.sh-not-found"
-        for build_name, build_config in build_project.iter_builds():
-            self.logger.info("Building %s:%s all.libraries.", build_dir, build_name)
-            dirs[build_name] = build_dir / "build-{}".format(build_name)
-            gcov = dirs[build_name] / "gcov.sh"
-            proc = self.jobserver.popen(
-                ["/usr/bin/ninja", "-C", dirs[build_name], "all.libraries"],
-                # Ninja will connect as a job client instead and claim
-                # many jobs.
-                stdout=subprocess.PIPE,
-                stderr=subprocess.PIPE,
-                encoding="utf-8",
-                errors="replace",
-            )
-            job_id = "{}:{}".format(build_dir, build_name)
-            zmake.multiproc.log_output(
-                logger=self.logger,
-                log_level=logging.DEBUG,
-                file_descriptor=proc.stdout,
-                log_level_override_func=ninja_stdout_log_level_override,
-                job_id=job_id,
-            )
-            zmake.multiproc.log_output(
-                self.logger,
-                logging.ERROR,
-                proc.stderr,
-                job_id=job_id,
-            )
-            if self._sequential:
-                if proc.wait():
-                    raise OSError(get_process_failure_msg(proc))
-            else:
-                procs.append(proc)
-
-        for proc in procs:
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-
-        return self._run_lcov(build_dir, lcov_file, initial=True, gcov=gcov)
-
-    def _coverage_run_test(self, project, build_dir, lcov_file):
-        self.logger.info("Running test %s in %s", project.project_dir, build_dir)
-        rv = self.configure(
-            project_dir=project.project_dir,
-            build_dir=build_dir,
-            build_after_configure=True,
-            test_after_configure=True,
-            coverage=True,
-        )
-        if rv:
-            return rv
-        gcov = "gcov.sh-not-found"
-        for build_name, build_config in project.iter_builds():
-            gcov = build_dir / "build-{}".format(build_name) / "gcov.sh"
-        return self._run_lcov(build_dir, lcov_file, initial=False, gcov=gcov)
-
-    def coverage(self, build_dir):
-        """Builds all targets with coverage enabled, and then runs the tests."""
-        all_lcov_files = []
-        root_dir = self.module_paths["ec"] / "zephyr"
-        for project in zmake.project.find_projects(root_dir):
-            is_test = project.config.is_test
-            rel_path = project.project_dir.relative_to(root_dir)
-            project_build_dir = pathlib.Path(build_dir).joinpath(rel_path)
-            lcov_file = pathlib.Path(build_dir).joinpath(
-                str(rel_path).replace("/", "_") + ".info"
-            )
-            all_lcov_files.append(lcov_file)
-            if is_test:
-                # Configure and run the test.
-                self.executor.append(
-                    func=lambda: self._coverage_run_test(
-                        project, project_build_dir, lcov_file
-                    )
-                )
-            else:
-                # Configure and compile the non-test project.
-                self.executor.append(
-                    func=lambda: self._coverage_compile_only(
-                        project, project_build_dir, lcov_file
-                    )
-                )
-            if self._sequential:
-                rv = self.executor.wait()
-                if rv:
-                    return rv
-
-        rv = self.executor.wait()
-        if rv:
-            return rv
-
-        with self.jobserver.get_job():
-            # Merge info files into a single lcov.info
-            self.logger.info("Merging coverage data into %s.", build_dir / "lcov.info")
-            cmd = ["/usr/bin/lcov", "-o", build_dir / "lcov.info"]
-            for info in all_lcov_files:
-                cmd += ["-a", info]
-            proc = self.jobserver.popen(
-                cmd,
-                stdout=subprocess.PIPE,
-                stderr=subprocess.PIPE,
-                encoding="utf-8",
-                errors="replace",
-            )
-            zmake.multiproc.log_output(
-                self.logger, logging.ERROR, proc.stderr, job_id="lcov"
-            )
-            zmake.multiproc.log_output(
-                self.logger, logging.DEBUG, proc.stdout, job_id="lcov"
-            )
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-
-            # Find the common root dir
-            prefixdir = os.path.commonprefix(list(self.module_paths.values()))
-
-            # Merge into a nice html report
-            self.logger.info("Creating coverage report %s.", build_dir / "coverage_rpt")
-            proc = self.jobserver.popen(
-                [
-                    "/usr/bin/genhtml",
-                    "-q",
-                    "-o",
-                    build_dir / "coverage_rpt",
-                    "-t",
-                    "Zephyr EC Unittest",
-                    "-p",
-                    prefixdir,
-                    "-s",
-                ]
-                + all_lcov_files,
-                stdout=subprocess.PIPE,
-                stderr=subprocess.PIPE,
-                encoding="utf-8",
-                errors="replace",
-            )
-            zmake.multiproc.log_output(
-                self.logger, logging.ERROR, proc.stderr, job_id="genhtml"
-            )
-            zmake.multiproc.log_output(
-                self.logger, logging.DEBUG, proc.stdout, job_id="genhtml"
-            )
-            if proc.wait():
-                raise OSError(get_process_failure_msg(proc))
-            return 0